144 files changed, 524175 insertions, 0 deletions

diff --git a/bsps/arm/stm32h7/include/Legacy/stm32_hal_legacy.h b/bsps/arm/stm32h7/include/Legacy/stm32_hal_legacy.h
new file mode 100644
index 0000000000..7b859e3782
--- /dev/null
+++ b/bsps/arm/stm32h7/include/Legacy/stm32_hal_legacy.h
@@ -0,0 +1,3775 @@
+/**

+  ******************************************************************************

+  * @file    stm32_hal_legacy.h

+  * @author  MCD Application Team

+  * @brief   This file contains aliases definition for the STM32Cube HAL constants

+  *          macros and functions maintained for legacy purpose.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32_HAL_LEGACY

+#define STM32_HAL_LEGACY

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+/* Exported types ------------------------------------------------------------*/

+/* Exported constants --------------------------------------------------------*/

+

+/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose

+  * @{

+  */

+#define AES_FLAG_RDERR                  CRYP_FLAG_RDERR

+#define AES_FLAG_WRERR                  CRYP_FLAG_WRERR

+#define AES_CLEARFLAG_CCF               CRYP_CLEARFLAG_CCF

+#define AES_CLEARFLAG_RDERR             CRYP_CLEARFLAG_RDERR

+#define AES_CLEARFLAG_WRERR             CRYP_CLEARFLAG_WRERR

+

+/**

+  * @}

+  */

+

+/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose

+  * @{

+  */

+#define ADC_RESOLUTION12b               ADC_RESOLUTION_12B

+#define ADC_RESOLUTION10b               ADC_RESOLUTION_10B

+#define ADC_RESOLUTION8b                ADC_RESOLUTION_8B

+#define ADC_RESOLUTION6b                ADC_RESOLUTION_6B

+#define OVR_DATA_OVERWRITTEN            ADC_OVR_DATA_OVERWRITTEN

+#define OVR_DATA_PRESERVED              ADC_OVR_DATA_PRESERVED

+#define EOC_SINGLE_CONV                 ADC_EOC_SINGLE_CONV

+#define EOC_SEQ_CONV                    ADC_EOC_SEQ_CONV

+#define EOC_SINGLE_SEQ_CONV             ADC_EOC_SINGLE_SEQ_CONV

+#define REGULAR_GROUP                   ADC_REGULAR_GROUP

+#define INJECTED_GROUP                  ADC_INJECTED_GROUP

+#define REGULAR_INJECTED_GROUP          ADC_REGULAR_INJECTED_GROUP

+#define AWD_EVENT                       ADC_AWD_EVENT

+#define AWD1_EVENT                      ADC_AWD1_EVENT

+#define AWD2_EVENT                      ADC_AWD2_EVENT

+#define AWD3_EVENT                      ADC_AWD3_EVENT

+#define OVR_EVENT                       ADC_OVR_EVENT

+#define JQOVF_EVENT                     ADC_JQOVF_EVENT

+#define ALL_CHANNELS                    ADC_ALL_CHANNELS

+#define REGULAR_CHANNELS                ADC_REGULAR_CHANNELS

+#define INJECTED_CHANNELS               ADC_INJECTED_CHANNELS

+#define SYSCFG_FLAG_SENSOR_ADC          ADC_FLAG_SENSOR

+#define SYSCFG_FLAG_VREF_ADC            ADC_FLAG_VREFINT

+#define ADC_CLOCKPRESCALER_PCLK_DIV1    ADC_CLOCK_SYNC_PCLK_DIV1

+#define ADC_CLOCKPRESCALER_PCLK_DIV2    ADC_CLOCK_SYNC_PCLK_DIV2

+#define ADC_CLOCKPRESCALER_PCLK_DIV4    ADC_CLOCK_SYNC_PCLK_DIV4

+#define ADC_CLOCKPRESCALER_PCLK_DIV6    ADC_CLOCK_SYNC_PCLK_DIV6

+#define ADC_CLOCKPRESCALER_PCLK_DIV8    ADC_CLOCK_SYNC_PCLK_DIV8

+#define ADC_EXTERNALTRIG0_T6_TRGO       ADC_EXTERNALTRIGCONV_T6_TRGO

+#define ADC_EXTERNALTRIG1_T21_CC2       ADC_EXTERNALTRIGCONV_T21_CC2

+#define ADC_EXTERNALTRIG2_T2_TRGO       ADC_EXTERNALTRIGCONV_T2_TRGO

+#define ADC_EXTERNALTRIG3_T2_CC4        ADC_EXTERNALTRIGCONV_T2_CC4

+#define ADC_EXTERNALTRIG4_T22_TRGO      ADC_EXTERNALTRIGCONV_T22_TRGO

+#define ADC_EXTERNALTRIG7_EXT_IT11      ADC_EXTERNALTRIGCONV_EXT_IT11

+#define ADC_CLOCK_ASYNC                 ADC_CLOCK_ASYNC_DIV1

+#define ADC_EXTERNALTRIG_EDGE_NONE      ADC_EXTERNALTRIGCONVEDGE_NONE

+#define ADC_EXTERNALTRIG_EDGE_RISING    ADC_EXTERNALTRIGCONVEDGE_RISING

+#define ADC_EXTERNALTRIG_EDGE_FALLING   ADC_EXTERNALTRIGCONVEDGE_FALLING

+#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING

+#define ADC_SAMPLETIME_2CYCLE_5         ADC_SAMPLETIME_2CYCLES_5

+

+#define HAL_ADC_STATE_BUSY_REG          HAL_ADC_STATE_REG_BUSY

+#define HAL_ADC_STATE_BUSY_INJ          HAL_ADC_STATE_INJ_BUSY

+#define HAL_ADC_STATE_EOC_REG           HAL_ADC_STATE_REG_EOC

+#define HAL_ADC_STATE_EOC_INJ           HAL_ADC_STATE_INJ_EOC

+#define HAL_ADC_STATE_ERROR             HAL_ADC_STATE_ERROR_INTERNAL

+#define HAL_ADC_STATE_BUSY              HAL_ADC_STATE_BUSY_INTERNAL

+#define HAL_ADC_STATE_AWD               HAL_ADC_STATE_AWD1

+

+#if defined(STM32H7)

+#define ADC_CHANNEL_VBAT_DIV4           ADC_CHANNEL_VBAT

+#endif /* STM32H7 */

+/**

+  * @}

+  */

+

+/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose

+  * @{

+  */

+

+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG

+

+/**

+  * @}

+  */

+

+/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose

+  * @{

+  */

+#define COMP_WINDOWMODE_DISABLED       COMP_WINDOWMODE_DISABLE

+#define COMP_WINDOWMODE_ENABLED        COMP_WINDOWMODE_ENABLE

+#define COMP_EXTI_LINE_COMP1_EVENT     COMP_EXTI_LINE_COMP1

+#define COMP_EXTI_LINE_COMP2_EVENT     COMP_EXTI_LINE_COMP2

+#define COMP_EXTI_LINE_COMP3_EVENT     COMP_EXTI_LINE_COMP3

+#define COMP_EXTI_LINE_COMP4_EVENT     COMP_EXTI_LINE_COMP4

+#define COMP_EXTI_LINE_COMP5_EVENT     COMP_EXTI_LINE_COMP5

+#define COMP_EXTI_LINE_COMP6_EVENT     COMP_EXTI_LINE_COMP6

+#define COMP_EXTI_LINE_COMP7_EVENT     COMP_EXTI_LINE_COMP7

+#if defined(STM32L0)

+#define COMP_LPTIMCONNECTION_ENABLED   ((uint32_t)0x00000003U)    /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */

+#endif

+#define COMP_OUTPUT_COMP6TIM2OCREFCLR  COMP_OUTPUT_COMP6_TIM2OCREFCLR

+#if defined(STM32F373xC) || defined(STM32F378xx)

+#define COMP_OUTPUT_TIM3IC1            COMP_OUTPUT_COMP1_TIM3IC1

+#define COMP_OUTPUT_TIM3OCREFCLR       COMP_OUTPUT_COMP1_TIM3OCREFCLR

+#endif /* STM32F373xC || STM32F378xx */

+

+#if defined(STM32L0) || defined(STM32L4)

+#define COMP_WINDOWMODE_ENABLE         COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON

+

+#define COMP_NONINVERTINGINPUT_IO1      COMP_INPUT_PLUS_IO1

+#define COMP_NONINVERTINGINPUT_IO2      COMP_INPUT_PLUS_IO2

+#define COMP_NONINVERTINGINPUT_IO3      COMP_INPUT_PLUS_IO3

+#define COMP_NONINVERTINGINPUT_IO4      COMP_INPUT_PLUS_IO4

+#define COMP_NONINVERTINGINPUT_IO5      COMP_INPUT_PLUS_IO5

+#define COMP_NONINVERTINGINPUT_IO6      COMP_INPUT_PLUS_IO6

+

+#define COMP_INVERTINGINPUT_1_4VREFINT  COMP_INPUT_MINUS_1_4VREFINT

+#define COMP_INVERTINGINPUT_1_2VREFINT  COMP_INPUT_MINUS_1_2VREFINT

+#define COMP_INVERTINGINPUT_3_4VREFINT  COMP_INPUT_MINUS_3_4VREFINT

+#define COMP_INVERTINGINPUT_VREFINT     COMP_INPUT_MINUS_VREFINT

+#define COMP_INVERTINGINPUT_DAC1_CH1    COMP_INPUT_MINUS_DAC1_CH1

+#define COMP_INVERTINGINPUT_DAC1_CH2    COMP_INPUT_MINUS_DAC1_CH2

+#define COMP_INVERTINGINPUT_DAC1        COMP_INPUT_MINUS_DAC1_CH1

+#define COMP_INVERTINGINPUT_DAC2        COMP_INPUT_MINUS_DAC1_CH2

+#define COMP_INVERTINGINPUT_IO1         COMP_INPUT_MINUS_IO1

+#if defined(STM32L0)

+/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2),     */

+/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding   */

+/* to the second dedicated IO (only for COMP2).                               */

+#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_DAC1_CH2

+#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO2

+#else

+#define COMP_INVERTINGINPUT_IO2         COMP_INPUT_MINUS_IO2

+#define COMP_INVERTINGINPUT_IO3         COMP_INPUT_MINUS_IO3

+#endif

+#define COMP_INVERTINGINPUT_IO4         COMP_INPUT_MINUS_IO4

+#define COMP_INVERTINGINPUT_IO5         COMP_INPUT_MINUS_IO5

+

+#define COMP_OUTPUTLEVEL_LOW            COMP_OUTPUT_LEVEL_LOW

+#define COMP_OUTPUTLEVEL_HIGH           COMP_OUTPUT_LEVEL_HIGH

+

+/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose.                    */

+/*       To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()".        */

+#if defined(COMP_CSR_LOCK)

+#define COMP_FLAG_LOCK                 COMP_CSR_LOCK

+#elif defined(COMP_CSR_COMP1LOCK)

+#define COMP_FLAG_LOCK                 COMP_CSR_COMP1LOCK

+#elif defined(COMP_CSR_COMPxLOCK)

+#define COMP_FLAG_LOCK                 COMP_CSR_COMPxLOCK

+#endif

+

+#if defined(STM32L4)

+#define COMP_BLANKINGSRCE_TIM1OC5        COMP_BLANKINGSRC_TIM1_OC5_COMP1

+#define COMP_BLANKINGSRCE_TIM2OC3        COMP_BLANKINGSRC_TIM2_OC3_COMP1

+#define COMP_BLANKINGSRCE_TIM3OC3        COMP_BLANKINGSRC_TIM3_OC3_COMP1

+#define COMP_BLANKINGSRCE_TIM3OC4        COMP_BLANKINGSRC_TIM3_OC4_COMP2

+#define COMP_BLANKINGSRCE_TIM8OC5        COMP_BLANKINGSRC_TIM8_OC5_COMP2

+#define COMP_BLANKINGSRCE_TIM15OC1       COMP_BLANKINGSRC_TIM15_OC1_COMP2

+#define COMP_BLANKINGSRCE_NONE           COMP_BLANKINGSRC_NONE

+#endif

+

+#if defined(STM32L0)

+#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_MEDIUMSPEED

+#define COMP_MODE_LOWSPEED               COMP_POWERMODE_ULTRALOWPOWER

+#else

+#define COMP_MODE_HIGHSPEED              COMP_POWERMODE_HIGHSPEED

+#define COMP_MODE_MEDIUMSPEED            COMP_POWERMODE_MEDIUMSPEED

+#define COMP_MODE_LOWPOWER               COMP_POWERMODE_LOWPOWER

+#define COMP_MODE_ULTRALOWPOWER          COMP_POWERMODE_ULTRALOWPOWER

+#endif

+

+#endif

+/**

+  * @}

+  */

+

+/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose

+  * @{

+  */

+#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig

+/**

+  * @}

+  */

+

+/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose

+  * @{

+  */

+

+#define CRC_OUTPUTDATA_INVERSION_DISABLED    CRC_OUTPUTDATA_INVERSION_DISABLE

+#define CRC_OUTPUTDATA_INVERSION_ENABLED     CRC_OUTPUTDATA_INVERSION_ENABLE

+

+/**

+  * @}

+  */

+

+/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose

+  * @{

+  */

+

+#define DAC1_CHANNEL_1                                  DAC_CHANNEL_1

+#define DAC1_CHANNEL_2                                  DAC_CHANNEL_2

+#define DAC2_CHANNEL_1                                  DAC_CHANNEL_1

+#define DAC_WAVE_NONE                                   0x00000000U

+#define DAC_WAVE_NOISE                                  DAC_CR_WAVE1_0

+#define DAC_WAVE_TRIANGLE                               DAC_CR_WAVE1_1

+#define DAC_WAVEGENERATION_NONE                         DAC_WAVE_NONE

+#define DAC_WAVEGENERATION_NOISE                        DAC_WAVE_NOISE

+#define DAC_WAVEGENERATION_TRIANGLE                     DAC_WAVE_TRIANGLE

+

+#if defined(STM32G4) || defined(STM32H7)

+#define DAC_CHIPCONNECT_DISABLE       DAC_CHIPCONNECT_EXTERNAL

+#define DAC_CHIPCONNECT_ENABLE        DAC_CHIPCONNECT_INTERNAL

+#endif

+

+#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)

+#define HAL_DAC_MSP_INIT_CB_ID       HAL_DAC_MSPINIT_CB_ID

+#define HAL_DAC_MSP_DEINIT_CB_ID     HAL_DAC_MSPDEINIT_CB_ID

+#endif

+

+/**

+  * @}

+  */

+

+/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose

+  * @{

+  */

+#define HAL_REMAPDMA_ADC_DMA_CH2                DMA_REMAP_ADC_DMA_CH2

+#define HAL_REMAPDMA_USART1_TX_DMA_CH4          DMA_REMAP_USART1_TX_DMA_CH4

+#define HAL_REMAPDMA_USART1_RX_DMA_CH5          DMA_REMAP_USART1_RX_DMA_CH5

+#define HAL_REMAPDMA_TIM16_DMA_CH4              DMA_REMAP_TIM16_DMA_CH4

+#define HAL_REMAPDMA_TIM17_DMA_CH2              DMA_REMAP_TIM17_DMA_CH2

+#define HAL_REMAPDMA_USART3_DMA_CH32            DMA_REMAP_USART3_DMA_CH32

+#define HAL_REMAPDMA_TIM16_DMA_CH6              DMA_REMAP_TIM16_DMA_CH6

+#define HAL_REMAPDMA_TIM17_DMA_CH7              DMA_REMAP_TIM17_DMA_CH7

+#define HAL_REMAPDMA_SPI2_DMA_CH67              DMA_REMAP_SPI2_DMA_CH67

+#define HAL_REMAPDMA_USART2_DMA_CH67            DMA_REMAP_USART2_DMA_CH67

+#define HAL_REMAPDMA_I2C1_DMA_CH76              DMA_REMAP_I2C1_DMA_CH76

+#define HAL_REMAPDMA_TIM1_DMA_CH6               DMA_REMAP_TIM1_DMA_CH6

+#define HAL_REMAPDMA_TIM2_DMA_CH7               DMA_REMAP_TIM2_DMA_CH7

+#define HAL_REMAPDMA_TIM3_DMA_CH6               DMA_REMAP_TIM3_DMA_CH6

+

+#define IS_HAL_REMAPDMA                          IS_DMA_REMAP

+#define __HAL_REMAPDMA_CHANNEL_ENABLE            __HAL_DMA_REMAP_CHANNEL_ENABLE

+#define __HAL_REMAPDMA_CHANNEL_DISABLE           __HAL_DMA_REMAP_CHANNEL_DISABLE

+

+#if defined(STM32L4)

+

+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0            HAL_DMAMUX1_REQ_GEN_EXTI0

+#define HAL_DMAMUX1_REQUEST_GEN_EXTI1            HAL_DMAMUX1_REQ_GEN_EXTI1

+#define HAL_DMAMUX1_REQUEST_GEN_EXTI2            HAL_DMAMUX1_REQ_GEN_EXTI2

+#define HAL_DMAMUX1_REQUEST_GEN_EXTI3            HAL_DMAMUX1_REQ_GEN_EXTI3

+#define HAL_DMAMUX1_REQUEST_GEN_EXTI4            HAL_DMAMUX1_REQ_GEN_EXTI4

+#define HAL_DMAMUX1_REQUEST_GEN_EXTI5            HAL_DMAMUX1_REQ_GEN_EXTI5

+#define HAL_DMAMUX1_REQUEST_GEN_EXTI6            HAL_DMAMUX1_REQ_GEN_EXTI6

+#define HAL_DMAMUX1_REQUEST_GEN_EXTI7            HAL_DMAMUX1_REQ_GEN_EXTI7

+#define HAL_DMAMUX1_REQUEST_GEN_EXTI8            HAL_DMAMUX1_REQ_GEN_EXTI8

+#define HAL_DMAMUX1_REQUEST_GEN_EXTI9            HAL_DMAMUX1_REQ_GEN_EXTI9

+#define HAL_DMAMUX1_REQUEST_GEN_EXTI10           HAL_DMAMUX1_REQ_GEN_EXTI10

+#define HAL_DMAMUX1_REQUEST_GEN_EXTI11           HAL_DMAMUX1_REQ_GEN_EXTI11

+#define HAL_DMAMUX1_REQUEST_GEN_EXTI12           HAL_DMAMUX1_REQ_GEN_EXTI12

+#define HAL_DMAMUX1_REQUEST_GEN_EXTI13           HAL_DMAMUX1_REQ_GEN_EXTI13

+#define HAL_DMAMUX1_REQUEST_GEN_EXTI14           HAL_DMAMUX1_REQ_GEN_EXTI14

+#define HAL_DMAMUX1_REQUEST_GEN_EXTI15           HAL_DMAMUX1_REQ_GEN_EXTI15

+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT

+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT

+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT

+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT  HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT

+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT

+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT       HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT

+#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE           HAL_DMAMUX1_REQ_GEN_DSI_TE

+#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT          HAL_DMAMUX1_REQ_GEN_DSI_EOT

+#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT        HAL_DMAMUX1_REQ_GEN_DMA2D_EOT

+#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT          HAL_DMAMUX1_REQ_GEN_LTDC_IT

+

+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT          HAL_DMAMUX_REQ_GEN_NO_EVENT

+#define HAL_DMAMUX_REQUEST_GEN_RISING            HAL_DMAMUX_REQ_GEN_RISING

+#define HAL_DMAMUX_REQUEST_GEN_FALLING           HAL_DMAMUX_REQ_GEN_FALLING

+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING    HAL_DMAMUX_REQ_GEN_RISING_FALLING

+

+#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)

+#define DMA_REQUEST_DCMI_PSSI                    DMA_REQUEST_DCMI

+#endif

+

+#endif /* STM32L4 */

+

+#if defined(STM32G0)

+#define DMA_REQUEST_DAC1_CHANNEL1                DMA_REQUEST_DAC1_CH1

+#define DMA_REQUEST_DAC1_CHANNEL2                DMA_REQUEST_DAC1_CH2

+#endif

+

+#if defined(STM32H7)

+

+#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1

+#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2

+

+#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX

+#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX

+

+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT

+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT

+#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT    HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT

+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT

+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT

+#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT

+#define HAL_DMAMUX1_REQUEST_GEN_EXTI0              HAL_DMAMUX1_REQ_GEN_EXTI0

+#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO         HAL_DMAMUX1_REQ_GEN_TIM12_TRGO

+

+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT

+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT

+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT

+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT

+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT

+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT

+#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT    HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT

+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP

+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP    HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP

+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP

+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT

+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP

+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT         HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT

+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP

+#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP        HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP

+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP          HAL_DMAMUX2_REQ_GEN_I2C4_WKUP

+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP          HAL_DMAMUX2_REQ_GEN_SPI6_WKUP

+#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT          HAL_DMAMUX2_REQ_GEN_COMP1_OUT

+#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT          HAL_DMAMUX2_REQ_GEN_COMP2_OUT

+#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP           HAL_DMAMUX2_REQ_GEN_RTC_WKUP

+#define HAL_DMAMUX2_REQUEST_GEN_EXTI0              HAL_DMAMUX2_REQ_GEN_EXTI0

+#define HAL_DMAMUX2_REQUEST_GEN_EXTI2              HAL_DMAMUX2_REQ_GEN_EXTI2

+#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT        HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT

+#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT            HAL_DMAMUX2_REQ_GEN_SPI6_IT

+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT

+#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT      HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT

+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT            HAL_DMAMUX2_REQ_GEN_ADC3_IT

+#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT      HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT

+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT

+#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT        HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT

+

+#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT            HAL_DMAMUX_REQ_GEN_NO_EVENT

+#define HAL_DMAMUX_REQUEST_GEN_RISING              HAL_DMAMUX_REQ_GEN_RISING

+#define HAL_DMAMUX_REQUEST_GEN_FALLING             HAL_DMAMUX_REQ_GEN_FALLING

+#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING      HAL_DMAMUX_REQ_GEN_RISING_FALLING

+

+#define DFSDM_FILTER_EXT_TRIG_LPTIM1               DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT

+#define DFSDM_FILTER_EXT_TRIG_LPTIM2               DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT

+#define DFSDM_FILTER_EXT_TRIG_LPTIM3               DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT

+

+#define DAC_TRIGGER_LP1_OUT                        DAC_TRIGGER_LPTIM1_OUT

+#define DAC_TRIGGER_LP2_OUT                        DAC_TRIGGER_LPTIM2_OUT

+

+#endif /* STM32H7 */

+

+/**

+  * @}

+  */

+

+/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose

+  * @{

+  */

+

+#define TYPEPROGRAM_BYTE              FLASH_TYPEPROGRAM_BYTE

+#define TYPEPROGRAM_HALFWORD          FLASH_TYPEPROGRAM_HALFWORD

+#define TYPEPROGRAM_WORD              FLASH_TYPEPROGRAM_WORD

+#define TYPEPROGRAM_DOUBLEWORD        FLASH_TYPEPROGRAM_DOUBLEWORD

+#define TYPEERASE_SECTORS             FLASH_TYPEERASE_SECTORS

+#define TYPEERASE_PAGES               FLASH_TYPEERASE_PAGES

+#define TYPEERASE_PAGEERASE           FLASH_TYPEERASE_PAGES

+#define TYPEERASE_MASSERASE           FLASH_TYPEERASE_MASSERASE

+#define WRPSTATE_DISABLE              OB_WRPSTATE_DISABLE

+#define WRPSTATE_ENABLE               OB_WRPSTATE_ENABLE

+#define HAL_FLASH_TIMEOUT_VALUE       FLASH_TIMEOUT_VALUE

+#define OBEX_PCROP                    OPTIONBYTE_PCROP

+#define OBEX_BOOTCONFIG               OPTIONBYTE_BOOTCONFIG

+#define PCROPSTATE_DISABLE            OB_PCROP_STATE_DISABLE

+#define PCROPSTATE_ENABLE             OB_PCROP_STATE_ENABLE

+#define TYPEERASEDATA_BYTE            FLASH_TYPEERASEDATA_BYTE

+#define TYPEERASEDATA_HALFWORD        FLASH_TYPEERASEDATA_HALFWORD

+#define TYPEERASEDATA_WORD            FLASH_TYPEERASEDATA_WORD

+#define TYPEPROGRAMDATA_BYTE          FLASH_TYPEPROGRAMDATA_BYTE

+#define TYPEPROGRAMDATA_HALFWORD      FLASH_TYPEPROGRAMDATA_HALFWORD

+#define TYPEPROGRAMDATA_WORD          FLASH_TYPEPROGRAMDATA_WORD

+#define TYPEPROGRAMDATA_FASTBYTE      FLASH_TYPEPROGRAMDATA_FASTBYTE

+#define TYPEPROGRAMDATA_FASTHALFWORD  FLASH_TYPEPROGRAMDATA_FASTHALFWORD

+#define TYPEPROGRAMDATA_FASTWORD      FLASH_TYPEPROGRAMDATA_FASTWORD

+#define PAGESIZE                      FLASH_PAGE_SIZE

+#define TYPEPROGRAM_FASTBYTE          FLASH_TYPEPROGRAM_BYTE

+#define TYPEPROGRAM_FASTHALFWORD      FLASH_TYPEPROGRAM_HALFWORD

+#define TYPEPROGRAM_FASTWORD          FLASH_TYPEPROGRAM_WORD

+#define VOLTAGE_RANGE_1               FLASH_VOLTAGE_RANGE_1

+#define VOLTAGE_RANGE_2               FLASH_VOLTAGE_RANGE_2

+#define VOLTAGE_RANGE_3               FLASH_VOLTAGE_RANGE_3

+#define VOLTAGE_RANGE_4               FLASH_VOLTAGE_RANGE_4

+#define TYPEPROGRAM_FAST              FLASH_TYPEPROGRAM_FAST

+#define TYPEPROGRAM_FAST_AND_LAST     FLASH_TYPEPROGRAM_FAST_AND_LAST

+#define WRPAREA_BANK1_AREAA           OB_WRPAREA_BANK1_AREAA

+#define WRPAREA_BANK1_AREAB           OB_WRPAREA_BANK1_AREAB

+#define WRPAREA_BANK2_AREAA           OB_WRPAREA_BANK2_AREAA

+#define WRPAREA_BANK2_AREAB           OB_WRPAREA_BANK2_AREAB

+#define IWDG_STDBY_FREEZE             OB_IWDG_STDBY_FREEZE

+#define IWDG_STDBY_ACTIVE             OB_IWDG_STDBY_RUN

+#define IWDG_STOP_FREEZE              OB_IWDG_STOP_FREEZE

+#define IWDG_STOP_ACTIVE              OB_IWDG_STOP_RUN

+#define FLASH_ERROR_NONE              HAL_FLASH_ERROR_NONE

+#define FLASH_ERROR_RD                HAL_FLASH_ERROR_RD

+#define FLASH_ERROR_PG                HAL_FLASH_ERROR_PROG

+#define FLASH_ERROR_PGP               HAL_FLASH_ERROR_PGS

+#define FLASH_ERROR_WRP               HAL_FLASH_ERROR_WRP

+#define FLASH_ERROR_OPTV              HAL_FLASH_ERROR_OPTV

+#define FLASH_ERROR_OPTVUSR           HAL_FLASH_ERROR_OPTVUSR

+#define FLASH_ERROR_PROG              HAL_FLASH_ERROR_PROG

+#define FLASH_ERROR_OP                HAL_FLASH_ERROR_OPERATION

+#define FLASH_ERROR_PGA               HAL_FLASH_ERROR_PGA

+#define FLASH_ERROR_SIZE              HAL_FLASH_ERROR_SIZE

+#define FLASH_ERROR_SIZ               HAL_FLASH_ERROR_SIZE

+#define FLASH_ERROR_PGS               HAL_FLASH_ERROR_PGS

+#define FLASH_ERROR_MIS               HAL_FLASH_ERROR_MIS

+#define FLASH_ERROR_FAST              HAL_FLASH_ERROR_FAST

+#define FLASH_ERROR_FWWERR            HAL_FLASH_ERROR_FWWERR

+#define FLASH_ERROR_NOTZERO           HAL_FLASH_ERROR_NOTZERO

+#define FLASH_ERROR_OPERATION         HAL_FLASH_ERROR_OPERATION

+#define FLASH_ERROR_ERS               HAL_FLASH_ERROR_ERS

+#define OB_WDG_SW                     OB_IWDG_SW

+#define OB_WDG_HW                     OB_IWDG_HW

+#define OB_SDADC12_VDD_MONITOR_SET    OB_SDACD_VDD_MONITOR_SET

+#define OB_SDADC12_VDD_MONITOR_RESET  OB_SDACD_VDD_MONITOR_RESET

+#define OB_RAM_PARITY_CHECK_SET       OB_SRAM_PARITY_SET

+#define OB_RAM_PARITY_CHECK_RESET     OB_SRAM_PARITY_RESET

+#define IS_OB_SDADC12_VDD_MONITOR     IS_OB_SDACD_VDD_MONITOR

+#define OB_RDP_LEVEL0                 OB_RDP_LEVEL_0

+#define OB_RDP_LEVEL1                 OB_RDP_LEVEL_1

+#define OB_RDP_LEVEL2                 OB_RDP_LEVEL_2

+#if defined(STM32G0)

+#define OB_BOOT_LOCK_DISABLE          OB_BOOT_ENTRY_FORCED_NONE

+#define OB_BOOT_LOCK_ENABLE           OB_BOOT_ENTRY_FORCED_FLASH

+#else

+#define OB_BOOT_ENTRY_FORCED_NONE     OB_BOOT_LOCK_DISABLE

+#define OB_BOOT_ENTRY_FORCED_FLASH    OB_BOOT_LOCK_ENABLE

+#endif

+#if defined(STM32H7)

+#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1

+#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1

+#define FLASH_FLAG_STRBER_BANK1R  FLASH_FLAG_STRBERR_BANK1

+#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2

+#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2

+#define FLASH_FLAG_STRBER_BANK2R  FLASH_FLAG_STRBERR_BANK2

+#define FLASH_FLAG_WDW            FLASH_FLAG_WBNE

+#define OB_WRP_SECTOR_All         OB_WRP_SECTOR_ALL

+#endif /* STM32H7 */

+

+/**

+  * @}

+  */

+

+/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose

+  * @{

+  */

+

+#if defined(STM32H7)

+#define __HAL_RCC_JPEG_CLK_ENABLE               __HAL_RCC_JPGDECEN_CLK_ENABLE

+#define __HAL_RCC_JPEG_CLK_DISABLE              __HAL_RCC_JPGDECEN_CLK_DISABLE

+#define __HAL_RCC_JPEG_FORCE_RESET              __HAL_RCC_JPGDECRST_FORCE_RESET

+#define __HAL_RCC_JPEG_RELEASE_RESET            __HAL_RCC_JPGDECRST_RELEASE_RESET

+#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE         __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE

+#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE        __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE

+#endif /* STM32H7 */

+

+/**

+  * @}

+  */

+

+/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose

+  * @{

+  */

+

+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9    I2C_FASTMODEPLUS_PA9

+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10   I2C_FASTMODEPLUS_PA10

+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6    I2C_FASTMODEPLUS_PB6

+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7    I2C_FASTMODEPLUS_PB7

+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8    I2C_FASTMODEPLUS_PB8

+#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9    I2C_FASTMODEPLUS_PB9

+#define HAL_SYSCFG_FASTMODEPLUS_I2C1       I2C_FASTMODEPLUS_I2C1

+#define HAL_SYSCFG_FASTMODEPLUS_I2C2       I2C_FASTMODEPLUS_I2C2

+#define HAL_SYSCFG_FASTMODEPLUS_I2C3       I2C_FASTMODEPLUS_I2C3

+#if defined(STM32G4)

+

+#define HAL_SYSCFG_EnableIOAnalogSwitchBooster    HAL_SYSCFG_EnableIOSwitchBooster

+#define HAL_SYSCFG_DisableIOAnalogSwitchBooster   HAL_SYSCFG_DisableIOSwitchBooster

+#define HAL_SYSCFG_EnableIOAnalogSwitchVDD        HAL_SYSCFG_EnableIOSwitchVDD

+#define HAL_SYSCFG_DisableIOAnalogSwitchVDD       HAL_SYSCFG_DisableIOSwitchVDD

+#endif /* STM32G4 */

+/**

+  * @}

+  */

+

+

+/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose

+  * @{

+  */

+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)

+#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE

+#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE

+#define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8

+#define FMC_NAND_PCC_MEM_BUS_WIDTH_16           FMC_NAND_MEM_BUS_WIDTH_16

+#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4)

+#define FMC_NAND_WAIT_FEATURE_DISABLE           FMC_NAND_PCC_WAIT_FEATURE_DISABLE

+#define FMC_NAND_WAIT_FEATURE_ENABLE            FMC_NAND_PCC_WAIT_FEATURE_ENABLE

+#define FMC_NAND_MEM_BUS_WIDTH_8                FMC_NAND_PCC_MEM_BUS_WIDTH_8

+#define FMC_NAND_MEM_BUS_WIDTH_16               FMC_NAND_PCC_MEM_BUS_WIDTH_16

+#endif

+/**

+  * @}

+  */

+

+/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose

+  * @{

+  */

+

+#define FSMC_NORSRAM_TYPEDEF                      FSMC_NORSRAM_TypeDef

+#define FSMC_NORSRAM_EXTENDED_TYPEDEF             FSMC_NORSRAM_EXTENDED_TypeDef

+/**

+  * @}

+  */

+

+/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose

+  * @{

+  */

+#define GET_GPIO_SOURCE                           GPIO_GET_INDEX

+#define GET_GPIO_INDEX                            GPIO_GET_INDEX

+

+#if defined(STM32F4)

+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDIO

+#define GPIO_AF12_SDMMC1                          GPIO_AF12_SDIO

+#endif

+

+#if defined(STM32F7)

+#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1

+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1

+#endif

+

+#if defined(STM32L4)

+#define GPIO_AF12_SDIO                            GPIO_AF12_SDMMC1

+#define GPIO_AF12_SDMMC                           GPIO_AF12_SDMMC1

+#endif

+

+#if defined(STM32H7)

+#define GPIO_AF7_SDIO1                            GPIO_AF7_SDMMC1

+#define GPIO_AF8_SDIO1                            GPIO_AF8_SDMMC1

+#define GPIO_AF12_SDIO1                           GPIO_AF12_SDMMC1

+#define GPIO_AF9_SDIO2                            GPIO_AF9_SDMMC2

+#define GPIO_AF10_SDIO2                           GPIO_AF10_SDMMC2

+#define GPIO_AF11_SDIO2                           GPIO_AF11_SDMMC2

+

+#if defined (STM32H743xx) || defined (STM32H753xx)  || defined (STM32H750xx) || defined (STM32H742xx) || \

+    defined (STM32H745xx) || defined (STM32H755xx)  || defined (STM32H747xx) || defined (STM32H757xx)

+#define GPIO_AF10_OTG2_HS  GPIO_AF10_OTG2_FS

+#define GPIO_AF10_OTG1_FS  GPIO_AF10_OTG1_HS

+#define GPIO_AF12_OTG2_FS  GPIO_AF12_OTG1_FS

+#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */

+#endif /* STM32H7 */

+

+#define GPIO_AF0_LPTIM                            GPIO_AF0_LPTIM1

+#define GPIO_AF1_LPTIM                            GPIO_AF1_LPTIM1

+#define GPIO_AF2_LPTIM                            GPIO_AF2_LPTIM1

+

+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)

+#define  GPIO_SPEED_LOW                           GPIO_SPEED_FREQ_LOW

+#define  GPIO_SPEED_MEDIUM                        GPIO_SPEED_FREQ_MEDIUM

+#define  GPIO_SPEED_FAST                          GPIO_SPEED_FREQ_HIGH

+#define  GPIO_SPEED_HIGH                          GPIO_SPEED_FREQ_VERY_HIGH

+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/

+

+#if defined(STM32L1)

+ #define  GPIO_SPEED_VERY_LOW    GPIO_SPEED_FREQ_LOW

+ #define  GPIO_SPEED_LOW         GPIO_SPEED_FREQ_MEDIUM

+ #define  GPIO_SPEED_MEDIUM      GPIO_SPEED_FREQ_HIGH

+ #define  GPIO_SPEED_HIGH        GPIO_SPEED_FREQ_VERY_HIGH

+#endif /* STM32L1 */

+

+#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)

+ #define  GPIO_SPEED_LOW    GPIO_SPEED_FREQ_LOW

+ #define  GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM

+ #define  GPIO_SPEED_HIGH   GPIO_SPEED_FREQ_HIGH

+#endif /* STM32F0 || STM32F3 || STM32F1 */

+

+#define GPIO_AF6_DFSDM                            GPIO_AF6_DFSDM1

+/**

+  * @}

+  */

+

+/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose

+  * @{

+  */

+#define HRTIM_TIMDELAYEDPROTECTION_DISABLED           HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED

+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6

+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6

+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6

+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6

+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7

+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7

+#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79  HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7

+#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79     HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7

+

+#define __HAL_HRTIM_SetCounter        __HAL_HRTIM_SETCOUNTER

+#define __HAL_HRTIM_GetCounter        __HAL_HRTIM_GETCOUNTER

+#define __HAL_HRTIM_SetPeriod         __HAL_HRTIM_SETPERIOD

+#define __HAL_HRTIM_GetPeriod         __HAL_HRTIM_GETPERIOD

+#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER

+#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER

+#define __HAL_HRTIM_SetCompare        __HAL_HRTIM_SETCOMPARE

+#define __HAL_HRTIM_GetCompare        __HAL_HRTIM_GETCOMPARE

+

+#if defined(STM32G4)

+#define HAL_HRTIM_ExternalEventCounterConfig    HAL_HRTIM_ExtEventCounterConfig

+#define HAL_HRTIM_ExternalEventCounterEnable    HAL_HRTIM_ExtEventCounterEnable

+#define HAL_HRTIM_ExternalEventCounterDisable   HAL_HRTIM_ExtEventCounterDisable

+#define HAL_HRTIM_ExternalEventCounterReset     HAL_HRTIM_ExtEventCounterReset

+#endif /* STM32G4 */

+

+#if defined(STM32H7)

+#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1

+#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2

+#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3

+#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4

+#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5

+#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6

+#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7

+#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8

+#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9

+#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1

+#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2

+#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3

+#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4

+#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5

+#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6

+#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7

+#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8

+#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9

+#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1

+#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2

+#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3

+#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4

+#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5

+#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6

+#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7

+#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8

+#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9

+#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1

+#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2

+#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3

+#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4

+#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5

+#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6

+#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7

+#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8

+#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9

+#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1

+#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2

+#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3

+#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4

+#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5

+#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6

+#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7

+#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8

+#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9

+#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1

+#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2

+#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3

+#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4

+#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5

+#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6

+#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7

+#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8

+#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9

+

+#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1

+#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2

+#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3

+#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4

+#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5

+#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6

+#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7

+#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8

+#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9

+#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1

+#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2

+#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3

+#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4

+#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5

+#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6

+#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7

+#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8

+#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9

+#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1

+#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2

+#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3

+#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4

+#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5

+#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6

+#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7

+#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8

+#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9

+#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1

+#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2

+#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3

+#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4

+#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5

+#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6

+#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7

+#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8

+#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9

+#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1

+#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2

+#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3

+#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4

+#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5

+#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6

+#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7

+#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8

+#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9

+#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1

+#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2

+#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3

+#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4

+#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5

+#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6

+#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7

+#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8

+#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9

+#endif /* STM32H7 */

+

+#if defined(STM32F3)

+/** @brief Constants defining available sources associated to external events.

+  */

+#define HRTIM_EVENTSRC_1              (0x00000000U)

+#define HRTIM_EVENTSRC_2              (HRTIM_EECR1_EE1SRC_0)

+#define HRTIM_EVENTSRC_3              (HRTIM_EECR1_EE1SRC_1)

+#define HRTIM_EVENTSRC_4              (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)

+

+/** @brief Constants defining the events that can be selected to configure the

+  *        set/reset crossbar of a timer output

+  */

+#define HRTIM_OUTPUTSET_TIMEV_1       (HRTIM_SET1R_TIMEVNT1)

+#define HRTIM_OUTPUTSET_TIMEV_2       (HRTIM_SET1R_TIMEVNT2)

+#define HRTIM_OUTPUTSET_TIMEV_3       (HRTIM_SET1R_TIMEVNT3)

+#define HRTIM_OUTPUTSET_TIMEV_4       (HRTIM_SET1R_TIMEVNT4)

+#define HRTIM_OUTPUTSET_TIMEV_5       (HRTIM_SET1R_TIMEVNT5)

+#define HRTIM_OUTPUTSET_TIMEV_6       (HRTIM_SET1R_TIMEVNT6)

+#define HRTIM_OUTPUTSET_TIMEV_7       (HRTIM_SET1R_TIMEVNT7)

+#define HRTIM_OUTPUTSET_TIMEV_8       (HRTIM_SET1R_TIMEVNT8)

+#define HRTIM_OUTPUTSET_TIMEV_9       (HRTIM_SET1R_TIMEVNT9)

+

+#define HRTIM_OUTPUTRESET_TIMEV_1     (HRTIM_RST1R_TIMEVNT1)

+#define HRTIM_OUTPUTRESET_TIMEV_2     (HRTIM_RST1R_TIMEVNT2)

+#define HRTIM_OUTPUTRESET_TIMEV_3     (HRTIM_RST1R_TIMEVNT3)

+#define HRTIM_OUTPUTRESET_TIMEV_4     (HRTIM_RST1R_TIMEVNT4)

+#define HRTIM_OUTPUTRESET_TIMEV_5     (HRTIM_RST1R_TIMEVNT5)

+#define HRTIM_OUTPUTRESET_TIMEV_6     (HRTIM_RST1R_TIMEVNT6)

+#define HRTIM_OUTPUTRESET_TIMEV_7     (HRTIM_RST1R_TIMEVNT7)

+#define HRTIM_OUTPUTRESET_TIMEV_8     (HRTIM_RST1R_TIMEVNT8)

+#define HRTIM_OUTPUTRESET_TIMEV_9     (HRTIM_RST1R_TIMEVNT9)

+

+/** @brief Constants defining the event filtering applied to external events

+  *        by a timer

+  */

+#define HRTIM_TIMEVENTFILTER_NONE             (0x00000000U)

+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1     (HRTIM_EEFR1_EE1FLTR_0)

+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2     (HRTIM_EEFR1_EE1FLTR_1)

+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3     (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)

+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4     (HRTIM_EEFR1_EE1FLTR_2)

+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)

+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)

+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)

+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4    (HRTIM_EEFR1_EE1FLTR_3)

+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)

+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)

+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)

+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)

+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)

+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)

+#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM     (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)

+

+/** @brief Constants defining the DLL calibration periods (in micro seconds)

+  */

+#define HRTIM_CALIBRATIONRATE_7300             0x00000000U

+#define HRTIM_CALIBRATIONRATE_910              (HRTIM_DLLCR_CALRTE_0)

+#define HRTIM_CALIBRATIONRATE_114              (HRTIM_DLLCR_CALRTE_1)

+#define HRTIM_CALIBRATIONRATE_14               (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)

+

+#endif /* STM32F3 */

+/**

+  * @}

+  */

+

+/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose

+  * @{

+  */

+#define I2C_DUALADDRESS_DISABLED                I2C_DUALADDRESS_DISABLE

+#define I2C_DUALADDRESS_ENABLED                 I2C_DUALADDRESS_ENABLE

+#define I2C_GENERALCALL_DISABLED                I2C_GENERALCALL_DISABLE

+#define I2C_GENERALCALL_ENABLED                 I2C_GENERALCALL_ENABLE

+#define I2C_NOSTRETCH_DISABLED                  I2C_NOSTRETCH_DISABLE

+#define I2C_NOSTRETCH_ENABLED                   I2C_NOSTRETCH_ENABLE

+#define I2C_ANALOGFILTER_ENABLED                I2C_ANALOGFILTER_ENABLE

+#define I2C_ANALOGFILTER_DISABLED               I2C_ANALOGFILTER_DISABLE

+#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)

+#define HAL_I2C_STATE_MEM_BUSY_TX               HAL_I2C_STATE_BUSY_TX

+#define HAL_I2C_STATE_MEM_BUSY_RX               HAL_I2C_STATE_BUSY_RX

+#define HAL_I2C_STATE_MASTER_BUSY_TX            HAL_I2C_STATE_BUSY_TX

+#define HAL_I2C_STATE_MASTER_BUSY_RX            HAL_I2C_STATE_BUSY_RX

+#define HAL_I2C_STATE_SLAVE_BUSY_TX             HAL_I2C_STATE_BUSY_TX

+#define HAL_I2C_STATE_SLAVE_BUSY_RX             HAL_I2C_STATE_BUSY_RX

+#endif

+/**

+  * @}

+  */

+

+/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose

+  * @{

+  */

+#define IRDA_ONE_BIT_SAMPLE_DISABLED            IRDA_ONE_BIT_SAMPLE_DISABLE

+#define IRDA_ONE_BIT_SAMPLE_ENABLED             IRDA_ONE_BIT_SAMPLE_ENABLE

+

+/**

+  * @}

+  */

+

+/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose

+  * @{

+  */

+#define KR_KEY_RELOAD                   IWDG_KEY_RELOAD

+#define KR_KEY_ENABLE                   IWDG_KEY_ENABLE

+#define KR_KEY_EWA                      IWDG_KEY_WRITE_ACCESS_ENABLE

+#define KR_KEY_DWA                      IWDG_KEY_WRITE_ACCESS_DISABLE

+/**

+  * @}

+  */

+

+/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose

+  * @{

+  */

+

+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION

+#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_2TRANSITIONS

+#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_4TRANSITIONS

+#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS     LPTIM_CLOCKSAMPLETIME_8TRANSITIONS

+

+#define LPTIM_CLOCKPOLARITY_RISINGEDGE          LPTIM_CLOCKPOLARITY_RISING

+#define LPTIM_CLOCKPOLARITY_FALLINGEDGE         LPTIM_CLOCKPOLARITY_FALLING

+#define LPTIM_CLOCKPOLARITY_BOTHEDGES           LPTIM_CLOCKPOLARITY_RISING_FALLING

+

+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION  LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION

+#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS      LPTIM_TRIGSAMPLETIME_2TRANSITIONS

+#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS      LPTIM_TRIGSAMPLETIME_4TRANSITIONS

+#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS      LPTIM_TRIGSAMPLETIME_8TRANSITIONS

+

+/* The following 3 definition have also been present in a temporary version of lptim.h */

+/* They need to be renamed also to the right name, just in case */

+#define LPTIM_TRIGSAMPLETIME_2TRANSITION        LPTIM_TRIGSAMPLETIME_2TRANSITIONS

+#define LPTIM_TRIGSAMPLETIME_4TRANSITION        LPTIM_TRIGSAMPLETIME_4TRANSITIONS

+#define LPTIM_TRIGSAMPLETIME_8TRANSITION        LPTIM_TRIGSAMPLETIME_8TRANSITIONS

+

+/**

+  * @}

+  */

+

+/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose

+  * @{

+  */

+#define HAL_NAND_Read_Page              HAL_NAND_Read_Page_8b

+#define HAL_NAND_Write_Page             HAL_NAND_Write_Page_8b

+#define HAL_NAND_Read_SpareArea         HAL_NAND_Read_SpareArea_8b

+#define HAL_NAND_Write_SpareArea        HAL_NAND_Write_SpareArea_8b

+

+#define NAND_AddressTypedef             NAND_AddressTypeDef

+

+#define __ARRAY_ADDRESS                 ARRAY_ADDRESS

+#define __ADDR_1st_CYCLE                ADDR_1ST_CYCLE

+#define __ADDR_2nd_CYCLE                ADDR_2ND_CYCLE

+#define __ADDR_3rd_CYCLE                ADDR_3RD_CYCLE

+#define __ADDR_4th_CYCLE                ADDR_4TH_CYCLE

+/**

+  * @}

+  */

+

+/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose

+  * @{

+  */

+#define NOR_StatusTypedef              HAL_NOR_StatusTypeDef

+#define NOR_SUCCESS                    HAL_NOR_STATUS_SUCCESS

+#define NOR_ONGOING                    HAL_NOR_STATUS_ONGOING

+#define NOR_ERROR                      HAL_NOR_STATUS_ERROR

+#define NOR_TIMEOUT                    HAL_NOR_STATUS_TIMEOUT

+

+#define __NOR_WRITE                    NOR_WRITE

+#define __NOR_ADDR_SHIFT               NOR_ADDR_SHIFT

+/**

+  * @}

+  */

+

+/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose

+  * @{

+  */

+

+#define OPAMP_NONINVERTINGINPUT_VP0           OPAMP_NONINVERTINGINPUT_IO0

+#define OPAMP_NONINVERTINGINPUT_VP1           OPAMP_NONINVERTINGINPUT_IO1

+#define OPAMP_NONINVERTINGINPUT_VP2           OPAMP_NONINVERTINGINPUT_IO2

+#define OPAMP_NONINVERTINGINPUT_VP3           OPAMP_NONINVERTINGINPUT_IO3

+

+#define OPAMP_SEC_NONINVERTINGINPUT_VP0       OPAMP_SEC_NONINVERTINGINPUT_IO0

+#define OPAMP_SEC_NONINVERTINGINPUT_VP1       OPAMP_SEC_NONINVERTINGINPUT_IO1

+#define OPAMP_SEC_NONINVERTINGINPUT_VP2       OPAMP_SEC_NONINVERTINGINPUT_IO2

+#define OPAMP_SEC_NONINVERTINGINPUT_VP3       OPAMP_SEC_NONINVERTINGINPUT_IO3

+

+#define OPAMP_INVERTINGINPUT_VM0              OPAMP_INVERTINGINPUT_IO0

+#define OPAMP_INVERTINGINPUT_VM1              OPAMP_INVERTINGINPUT_IO1

+

+#define IOPAMP_INVERTINGINPUT_VM0             OPAMP_INVERTINGINPUT_IO0

+#define IOPAMP_INVERTINGINPUT_VM1             OPAMP_INVERTINGINPUT_IO1

+

+#define OPAMP_SEC_INVERTINGINPUT_VM0          OPAMP_SEC_INVERTINGINPUT_IO0

+#define OPAMP_SEC_INVERTINGINPUT_VM1          OPAMP_SEC_INVERTINGINPUT_IO1

+

+#define OPAMP_INVERTINGINPUT_VINM             OPAMP_SEC_INVERTINGINPUT_IO1

+

+#define OPAMP_PGACONNECT_NO                   OPAMP_PGA_CONNECT_INVERTINGINPUT_NO

+#define OPAMP_PGACONNECT_VM0                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0

+#define OPAMP_PGACONNECT_VM1                  OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1

+

+#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4)

+#define HAL_OPAMP_MSP_INIT_CB_ID       HAL_OPAMP_MSPINIT_CB_ID

+#define HAL_OPAMP_MSP_DEINIT_CB_ID     HAL_OPAMP_MSPDEINIT_CB_ID

+#endif

+

+

+/**

+  * @}

+  */

+

+/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose

+  * @{

+  */

+#define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS

+

+#if defined(STM32H7)

+  #define I2S_IT_TXE               I2S_IT_TXP

+  #define I2S_IT_RXNE              I2S_IT_RXP

+

+  #define I2S_FLAG_TXE             I2S_FLAG_TXP

+  #define I2S_FLAG_RXNE            I2S_FLAG_RXP

+#endif

+

+#if defined(STM32F7)

+  #define I2S_CLOCK_SYSCLK           I2S_CLOCK_PLL

+#endif

+/**

+  * @}

+  */

+

+/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose

+  * @{

+  */

+

+/* Compact Flash-ATA registers description */

+#define CF_DATA                       ATA_DATA

+#define CF_SECTOR_COUNT               ATA_SECTOR_COUNT

+#define CF_SECTOR_NUMBER              ATA_SECTOR_NUMBER

+#define CF_CYLINDER_LOW               ATA_CYLINDER_LOW

+#define CF_CYLINDER_HIGH              ATA_CYLINDER_HIGH

+#define CF_CARD_HEAD                  ATA_CARD_HEAD

+#define CF_STATUS_CMD                 ATA_STATUS_CMD

+#define CF_STATUS_CMD_ALTERNATE       ATA_STATUS_CMD_ALTERNATE

+#define CF_COMMON_DATA_AREA           ATA_COMMON_DATA_AREA

+

+/* Compact Flash-ATA commands */

+#define CF_READ_SECTOR_CMD            ATA_READ_SECTOR_CMD

+#define CF_WRITE_SECTOR_CMD           ATA_WRITE_SECTOR_CMD

+#define CF_ERASE_SECTOR_CMD           ATA_ERASE_SECTOR_CMD

+#define CF_IDENTIFY_CMD               ATA_IDENTIFY_CMD

+

+#define PCCARD_StatusTypedef          HAL_PCCARD_StatusTypeDef

+#define PCCARD_SUCCESS                HAL_PCCARD_STATUS_SUCCESS

+#define PCCARD_ONGOING                HAL_PCCARD_STATUS_ONGOING

+#define PCCARD_ERROR                  HAL_PCCARD_STATUS_ERROR

+#define PCCARD_TIMEOUT                HAL_PCCARD_STATUS_TIMEOUT

+/**

+  * @}

+  */

+  

+/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose

+  * @{

+  */

+

+#define FORMAT_BIN                  RTC_FORMAT_BIN

+#define FORMAT_BCD                  RTC_FORMAT_BCD

+

+#define RTC_ALARMSUBSECONDMASK_None     RTC_ALARMSUBSECONDMASK_NONE

+#define RTC_TAMPERERASEBACKUP_DISABLED  RTC_TAMPER_ERASE_BACKUP_DISABLE

+#define RTC_TAMPERMASK_FLAG_DISABLED    RTC_TAMPERMASK_FLAG_DISABLE

+#define RTC_TAMPERMASK_FLAG_ENABLED     RTC_TAMPERMASK_FLAG_ENABLE

+

+#define RTC_MASKTAMPERFLAG_DISABLED     RTC_TAMPERMASK_FLAG_DISABLE

+#define RTC_MASKTAMPERFLAG_ENABLED      RTC_TAMPERMASK_FLAG_ENABLE

+#define RTC_TAMPERERASEBACKUP_ENABLED   RTC_TAMPER_ERASE_BACKUP_ENABLE

+#define RTC_TAMPER1_2_INTERRUPT         RTC_ALL_TAMPER_INTERRUPT

+#define RTC_TAMPER1_2_3_INTERRUPT       RTC_ALL_TAMPER_INTERRUPT

+

+#define RTC_TIMESTAMPPIN_PC13  RTC_TIMESTAMPPIN_DEFAULT

+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1

+#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1

+#define RTC_TIMESTAMPPIN_PC1   RTC_TIMESTAMPPIN_POS2

+

+#define RTC_OUTPUT_REMAP_PC13  RTC_OUTPUT_REMAP_NONE

+#define RTC_OUTPUT_REMAP_PB14  RTC_OUTPUT_REMAP_POS1

+#define RTC_OUTPUT_REMAP_PB2   RTC_OUTPUT_REMAP_POS1

+

+#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT

+#define RTC_TAMPERPIN_PA0  RTC_TAMPERPIN_POS1

+#define RTC_TAMPERPIN_PI8  RTC_TAMPERPIN_POS1

+

+#if defined(STM32H7)

+#define RTC_TAMPCR_TAMPXE          RTC_TAMPER_X

+#define RTC_TAMPCR_TAMPXIE         RTC_TAMPER_X_INTERRUPT

+

+#define RTC_TAMPER1_INTERRUPT      RTC_IT_TAMP1

+#define RTC_TAMPER2_INTERRUPT      RTC_IT_TAMP2

+#define RTC_TAMPER3_INTERRUPT      RTC_IT_TAMP3

+#define RTC_ALL_TAMPER_INTERRUPT   RTC_IT_TAMPALL

+#endif /* STM32H7 */

+

+/**

+  * @}

+  */

+

+

+/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose

+  * @{

+  */

+#define SMARTCARD_NACK_ENABLED                  SMARTCARD_NACK_ENABLE

+#define SMARTCARD_NACK_DISABLED                 SMARTCARD_NACK_DISABLE

+

+#define SMARTCARD_ONEBIT_SAMPLING_DISABLED      SMARTCARD_ONE_BIT_SAMPLE_DISABLE

+#define SMARTCARD_ONEBIT_SAMPLING_ENABLED       SMARTCARD_ONE_BIT_SAMPLE_ENABLE

+#define SMARTCARD_ONEBIT_SAMPLING_DISABLE       SMARTCARD_ONE_BIT_SAMPLE_DISABLE

+#define SMARTCARD_ONEBIT_SAMPLING_ENABLE        SMARTCARD_ONE_BIT_SAMPLE_ENABLE

+

+#define SMARTCARD_TIMEOUT_DISABLED              SMARTCARD_TIMEOUT_DISABLE

+#define SMARTCARD_TIMEOUT_ENABLED               SMARTCARD_TIMEOUT_ENABLE

+

+#define SMARTCARD_LASTBIT_DISABLED              SMARTCARD_LASTBIT_DISABLE

+#define SMARTCARD_LASTBIT_ENABLED               SMARTCARD_LASTBIT_ENABLE

+/**

+  * @}

+  */

+

+

+/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose

+  * @{

+  */

+#define SMBUS_DUALADDRESS_DISABLED      SMBUS_DUALADDRESS_DISABLE

+#define SMBUS_DUALADDRESS_ENABLED       SMBUS_DUALADDRESS_ENABLE

+#define SMBUS_GENERALCALL_DISABLED      SMBUS_GENERALCALL_DISABLE

+#define SMBUS_GENERALCALL_ENABLED       SMBUS_GENERALCALL_ENABLE

+#define SMBUS_NOSTRETCH_DISABLED        SMBUS_NOSTRETCH_DISABLE

+#define SMBUS_NOSTRETCH_ENABLED         SMBUS_NOSTRETCH_ENABLE

+#define SMBUS_ANALOGFILTER_ENABLED      SMBUS_ANALOGFILTER_ENABLE

+#define SMBUS_ANALOGFILTER_DISABLED     SMBUS_ANALOGFILTER_DISABLE

+#define SMBUS_PEC_DISABLED              SMBUS_PEC_DISABLE

+#define SMBUS_PEC_ENABLED               SMBUS_PEC_ENABLE

+#define HAL_SMBUS_STATE_SLAVE_LISTEN    HAL_SMBUS_STATE_LISTEN

+/**

+  * @}

+  */

+

+/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose

+  * @{

+  */

+#define SPI_TIMODE_DISABLED             SPI_TIMODE_DISABLE

+#define SPI_TIMODE_ENABLED              SPI_TIMODE_ENABLE

+

+#define SPI_CRCCALCULATION_DISABLED     SPI_CRCCALCULATION_DISABLE

+#define SPI_CRCCALCULATION_ENABLED      SPI_CRCCALCULATION_ENABLE

+

+#define SPI_NSS_PULSE_DISABLED          SPI_NSS_PULSE_DISABLE

+#define SPI_NSS_PULSE_ENABLED           SPI_NSS_PULSE_ENABLE

+

+#if defined(STM32H7)

+

+ #define SPI_FLAG_TXE                    SPI_FLAG_TXP

+ #define SPI_FLAG_RXNE                   SPI_FLAG_RXP

+

+ #define SPI_IT_TXE                      SPI_IT_TXP

+ #define SPI_IT_RXNE                     SPI_IT_RXP

+

+ #define SPI_FRLVL_EMPTY                 SPI_RX_FIFO_0PACKET

+ #define SPI_FRLVL_QUARTER_FULL          SPI_RX_FIFO_1PACKET

+ #define SPI_FRLVL_HALF_FULL             SPI_RX_FIFO_2PACKET

+ #define SPI_FRLVL_FULL                  SPI_RX_FIFO_3PACKET

+

+#endif /* STM32H7 */

+

+/**

+  * @}

+  */

+

+/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose

+  * @{

+  */

+#define CCER_CCxE_MASK                   TIM_CCER_CCxE_MASK

+#define CCER_CCxNE_MASK                  TIM_CCER_CCxNE_MASK

+

+#define TIM_DMABase_CR1                  TIM_DMABASE_CR1

+#define TIM_DMABase_CR2                  TIM_DMABASE_CR2

+#define TIM_DMABase_SMCR                 TIM_DMABASE_SMCR

+#define TIM_DMABase_DIER                 TIM_DMABASE_DIER

+#define TIM_DMABase_SR                   TIM_DMABASE_SR

+#define TIM_DMABase_EGR                  TIM_DMABASE_EGR

+#define TIM_DMABase_CCMR1                TIM_DMABASE_CCMR1

+#define TIM_DMABase_CCMR2                TIM_DMABASE_CCMR2

+#define TIM_DMABase_CCER                 TIM_DMABASE_CCER

+#define TIM_DMABase_CNT                  TIM_DMABASE_CNT

+#define TIM_DMABase_PSC                  TIM_DMABASE_PSC

+#define TIM_DMABase_ARR                  TIM_DMABASE_ARR

+#define TIM_DMABase_RCR                  TIM_DMABASE_RCR

+#define TIM_DMABase_CCR1                 TIM_DMABASE_CCR1

+#define TIM_DMABase_CCR2                 TIM_DMABASE_CCR2

+#define TIM_DMABase_CCR3                 TIM_DMABASE_CCR3

+#define TIM_DMABase_CCR4                 TIM_DMABASE_CCR4

+#define TIM_DMABase_BDTR                 TIM_DMABASE_BDTR

+#define TIM_DMABase_DCR                  TIM_DMABASE_DCR

+#define TIM_DMABase_DMAR                 TIM_DMABASE_DMAR

+#define TIM_DMABase_OR1                  TIM_DMABASE_OR1

+#define TIM_DMABase_CCMR3                TIM_DMABASE_CCMR3

+#define TIM_DMABase_CCR5                 TIM_DMABASE_CCR5

+#define TIM_DMABase_CCR6                 TIM_DMABASE_CCR6

+#define TIM_DMABase_OR2                  TIM_DMABASE_OR2

+#define TIM_DMABase_OR3                  TIM_DMABASE_OR3

+#define TIM_DMABase_OR                   TIM_DMABASE_OR

+

+#define TIM_EventSource_Update           TIM_EVENTSOURCE_UPDATE

+#define TIM_EventSource_CC1              TIM_EVENTSOURCE_CC1

+#define TIM_EventSource_CC2              TIM_EVENTSOURCE_CC2

+#define TIM_EventSource_CC3              TIM_EVENTSOURCE_CC3

+#define TIM_EventSource_CC4              TIM_EVENTSOURCE_CC4

+#define TIM_EventSource_COM              TIM_EVENTSOURCE_COM

+#define TIM_EventSource_Trigger          TIM_EVENTSOURCE_TRIGGER

+#define TIM_EventSource_Break            TIM_EVENTSOURCE_BREAK

+#define TIM_EventSource_Break2           TIM_EVENTSOURCE_BREAK2

+

+#define TIM_DMABurstLength_1Transfer     TIM_DMABURSTLENGTH_1TRANSFER

+#define TIM_DMABurstLength_2Transfers    TIM_DMABURSTLENGTH_2TRANSFERS

+#define TIM_DMABurstLength_3Transfers    TIM_DMABURSTLENGTH_3TRANSFERS

+#define TIM_DMABurstLength_4Transfers    TIM_DMABURSTLENGTH_4TRANSFERS

+#define TIM_DMABurstLength_5Transfers    TIM_DMABURSTLENGTH_5TRANSFERS

+#define TIM_DMABurstLength_6Transfers    TIM_DMABURSTLENGTH_6TRANSFERS

+#define TIM_DMABurstLength_7Transfers    TIM_DMABURSTLENGTH_7TRANSFERS

+#define TIM_DMABurstLength_8Transfers    TIM_DMABURSTLENGTH_8TRANSFERS

+#define TIM_DMABurstLength_9Transfers    TIM_DMABURSTLENGTH_9TRANSFERS

+#define TIM_DMABurstLength_10Transfers   TIM_DMABURSTLENGTH_10TRANSFERS

+#define TIM_DMABurstLength_11Transfers   TIM_DMABURSTLENGTH_11TRANSFERS

+#define TIM_DMABurstLength_12Transfers   TIM_DMABURSTLENGTH_12TRANSFERS

+#define TIM_DMABurstLength_13Transfers   TIM_DMABURSTLENGTH_13TRANSFERS

+#define TIM_DMABurstLength_14Transfers   TIM_DMABURSTLENGTH_14TRANSFERS

+#define TIM_DMABurstLength_15Transfers   TIM_DMABURSTLENGTH_15TRANSFERS

+#define TIM_DMABurstLength_16Transfers   TIM_DMABURSTLENGTH_16TRANSFERS

+#define TIM_DMABurstLength_17Transfers   TIM_DMABURSTLENGTH_17TRANSFERS

+#define TIM_DMABurstLength_18Transfers   TIM_DMABURSTLENGTH_18TRANSFERS

+

+#if defined(STM32L0)

+#define TIM22_TI1_GPIO1   TIM22_TI1_GPIO

+#define TIM22_TI1_GPIO2   TIM22_TI1_GPIO

+#endif

+

+#if defined(STM32F3)

+#define IS_TIM_HALL_INTERFACE_INSTANCE   IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE

+#endif

+

+#if defined(STM32H7)

+#define TIM_TIM1_ETR_COMP1_OUT        TIM_TIM1_ETR_COMP1

+#define TIM_TIM1_ETR_COMP2_OUT        TIM_TIM1_ETR_COMP2

+#define TIM_TIM8_ETR_COMP1_OUT        TIM_TIM8_ETR_COMP1

+#define TIM_TIM8_ETR_COMP2_OUT        TIM_TIM8_ETR_COMP2

+#define TIM_TIM2_ETR_COMP1_OUT        TIM_TIM2_ETR_COMP1

+#define TIM_TIM2_ETR_COMP2_OUT        TIM_TIM2_ETR_COMP2

+#define TIM_TIM3_ETR_COMP1_OUT        TIM_TIM3_ETR_COMP1

+#define TIM_TIM1_TI1_COMP1_OUT        TIM_TIM1_TI1_COMP1

+#define TIM_TIM8_TI1_COMP2_OUT        TIM_TIM8_TI1_COMP2

+#define TIM_TIM2_TI4_COMP1_OUT        TIM_TIM2_TI4_COMP1

+#define TIM_TIM2_TI4_COMP2_OUT        TIM_TIM2_TI4_COMP2

+#define TIM_TIM2_TI4_COMP1COMP2_OUT   TIM_TIM2_TI4_COMP1_COMP2

+#define TIM_TIM3_TI1_COMP1_OUT        TIM_TIM3_TI1_COMP1

+#define TIM_TIM3_TI1_COMP2_OUT        TIM_TIM3_TI1_COMP2

+#define TIM_TIM3_TI1_COMP1COMP2_OUT   TIM_TIM3_TI1_COMP1_COMP2

+#endif

+

+/**

+  * @}

+  */

+

+/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose

+  * @{

+  */

+#define TSC_SYNC_POL_FALL        TSC_SYNC_POLARITY_FALLING

+#define TSC_SYNC_POL_RISE_HIGH   TSC_SYNC_POLARITY_RISING

+/**

+  * @}

+  */

+

+/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose

+  * @{

+  */

+#define UART_ONEBIT_SAMPLING_DISABLED   UART_ONE_BIT_SAMPLE_DISABLE

+#define UART_ONEBIT_SAMPLING_ENABLED    UART_ONE_BIT_SAMPLE_ENABLE

+#define UART_ONE_BIT_SAMPLE_DISABLED    UART_ONE_BIT_SAMPLE_DISABLE

+#define UART_ONE_BIT_SAMPLE_ENABLED     UART_ONE_BIT_SAMPLE_ENABLE

+

+#define __HAL_UART_ONEBIT_ENABLE        __HAL_UART_ONE_BIT_SAMPLE_ENABLE

+#define __HAL_UART_ONEBIT_DISABLE       __HAL_UART_ONE_BIT_SAMPLE_DISABLE

+

+#define __DIV_SAMPLING16                UART_DIV_SAMPLING16

+#define __DIVMANT_SAMPLING16            UART_DIVMANT_SAMPLING16

+#define __DIVFRAQ_SAMPLING16            UART_DIVFRAQ_SAMPLING16

+#define __UART_BRR_SAMPLING16           UART_BRR_SAMPLING16

+

+#define __DIV_SAMPLING8                 UART_DIV_SAMPLING8

+#define __DIVMANT_SAMPLING8             UART_DIVMANT_SAMPLING8

+#define __DIVFRAQ_SAMPLING8             UART_DIVFRAQ_SAMPLING8

+#define __UART_BRR_SAMPLING8            UART_BRR_SAMPLING8

+

+#define __DIV_LPUART                    UART_DIV_LPUART

+

+#define UART_WAKEUPMETHODE_IDLELINE     UART_WAKEUPMETHOD_IDLELINE

+#define UART_WAKEUPMETHODE_ADDRESSMARK  UART_WAKEUPMETHOD_ADDRESSMARK

+

+/**

+  * @}

+  */

+

+

+/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose

+  * @{

+  */

+

+#define USART_CLOCK_DISABLED            USART_CLOCK_DISABLE

+#define USART_CLOCK_ENABLED             USART_CLOCK_ENABLE

+

+#define USARTNACK_ENABLED               USART_NACK_ENABLE

+#define USARTNACK_DISABLED              USART_NACK_DISABLE

+/**

+  * @}

+  */

+

+/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose

+  * @{

+  */

+#define CFR_BASE                    WWDG_CFR_BASE

+

+/**

+  * @}

+  */

+

+/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose

+  * @{

+  */

+#define CAN_FilterFIFO0             CAN_FILTER_FIFO0

+#define CAN_FilterFIFO1             CAN_FILTER_FIFO1

+#define CAN_IT_RQCP0                CAN_IT_TME

+#define CAN_IT_RQCP1                CAN_IT_TME

+#define CAN_IT_RQCP2                CAN_IT_TME

+#define INAK_TIMEOUT                CAN_TIMEOUT_VALUE

+#define SLAK_TIMEOUT                CAN_TIMEOUT_VALUE

+#define CAN_TXSTATUS_FAILED         ((uint8_t)0x00U)

+#define CAN_TXSTATUS_OK             ((uint8_t)0x01U)

+#define CAN_TXSTATUS_PENDING        ((uint8_t)0x02U)

+

+/**

+  * @}

+  */

+

+/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose

+  * @{

+  */

+

+#define VLAN_TAG                ETH_VLAN_TAG

+#define MIN_ETH_PAYLOAD         ETH_MIN_ETH_PAYLOAD

+#define MAX_ETH_PAYLOAD         ETH_MAX_ETH_PAYLOAD

+#define JUMBO_FRAME_PAYLOAD     ETH_JUMBO_FRAME_PAYLOAD

+#define MACMIIAR_CR_MASK        ETH_MACMIIAR_CR_MASK

+#define MACCR_CLEAR_MASK        ETH_MACCR_CLEAR_MASK

+#define MACFCR_CLEAR_MASK       ETH_MACFCR_CLEAR_MASK

+#define DMAOMR_CLEAR_MASK       ETH_DMAOMR_CLEAR_MASK

+

+#define ETH_MMCCR              0x00000100U

+#define ETH_MMCRIR             0x00000104U

+#define ETH_MMCTIR             0x00000108U

+#define ETH_MMCRIMR            0x0000010CU

+#define ETH_MMCTIMR            0x00000110U

+#define ETH_MMCTGFSCCR         0x0000014CU

+#define ETH_MMCTGFMSCCR        0x00000150U

+#define ETH_MMCTGFCR           0x00000168U

+#define ETH_MMCRFCECR          0x00000194U

+#define ETH_MMCRFAECR          0x00000198U

+#define ETH_MMCRGUFCR          0x000001C4U

+

+#define ETH_MAC_TXFIFO_FULL                             0x02000000U  /* Tx FIFO full */

+#define ETH_MAC_TXFIFONOT_EMPTY                         0x01000000U  /* Tx FIFO not empty */

+#define ETH_MAC_TXFIFO_WRITE_ACTIVE                     0x00400000U  /* Tx FIFO write active */

+#define ETH_MAC_TXFIFO_IDLE                             0x00000000U  /* Tx FIFO read status: Idle */

+#define ETH_MAC_TXFIFO_READ                             0x00100000U  /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */

+#define ETH_MAC_TXFIFO_WAITING                          0x00200000U  /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */

+#define ETH_MAC_TXFIFO_WRITING                          0x00300000U  /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */

+#define ETH_MAC_TRANSMISSION_PAUSE                      0x00080000U  /* MAC transmitter in pause */

+#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE            0x00000000U  /* MAC transmit frame controller: Idle */

+#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING         0x00020000U  /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */

+#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF   0x00040000U  /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */

+#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING    0x00060000U  /* MAC transmit frame controller: Transferring input frame for transmission */

+#define ETH_MAC_MII_TRANSMIT_ACTIVE           0x00010000U  /* MAC MII transmit engine active */

+#define ETH_MAC_RXFIFO_EMPTY                  0x00000000U  /* Rx FIFO fill level: empty */

+#define ETH_MAC_RXFIFO_BELOW_THRESHOLD        0x00000100U  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */

+#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD        0x00000200U  /* Rx FIFO fill level: fill-level above flow-control activate threshold */

+#define ETH_MAC_RXFIFO_FULL                   0x00000300U  /* Rx FIFO fill level: full */

+#if defined(STM32F1)

+#else

+#define ETH_MAC_READCONTROLLER_IDLE           0x00000000U  /* Rx FIFO read controller IDLE state */

+#define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U  /* Rx FIFO read controller Reading frame data */

+#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U  /* Rx FIFO read controller Reading frame status (or time-stamp) */

+#endif

+#define ETH_MAC_READCONTROLLER_FLUSHING       0x00000060U  /* Rx FIFO read controller Flushing the frame data and status */

+#define ETH_MAC_RXFIFO_WRITE_ACTIVE           0x00000010U  /* Rx FIFO write controller active */

+#define ETH_MAC_SMALL_FIFO_NOTACTIVE          0x00000000U  /* MAC small FIFO read / write controllers not active */

+#define ETH_MAC_SMALL_FIFO_READ_ACTIVE        0x00000002U  /* MAC small FIFO read controller active */

+#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE       0x00000004U  /* MAC small FIFO write controller active */

+#define ETH_MAC_SMALL_FIFO_RW_ACTIVE          0x00000006U  /* MAC small FIFO read / write controllers active */

+#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE   0x00000001U  /* MAC MII receive protocol engine active */

+

+/**

+  * @}

+  */

+

+/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose

+  * @{

+  */

+#define HAL_DCMI_ERROR_OVF      HAL_DCMI_ERROR_OVR

+#define DCMI_IT_OVF             DCMI_IT_OVR

+#define DCMI_FLAG_OVFRI         DCMI_FLAG_OVRRI

+#define DCMI_FLAG_OVFMI         DCMI_FLAG_OVRMI

+

+#define HAL_DCMI_ConfigCROP     HAL_DCMI_ConfigCrop

+#define HAL_DCMI_EnableCROP     HAL_DCMI_EnableCrop

+#define HAL_DCMI_DisableCROP    HAL_DCMI_DisableCrop

+

+/**

+  * @}

+  */

+

+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \

+  || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \

+  || defined(STM32H7)

+/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose

+  * @{

+  */

+#define DMA2D_ARGB8888          DMA2D_OUTPUT_ARGB8888

+#define DMA2D_RGB888            DMA2D_OUTPUT_RGB888

+#define DMA2D_RGB565            DMA2D_OUTPUT_RGB565

+#define DMA2D_ARGB1555          DMA2D_OUTPUT_ARGB1555

+#define DMA2D_ARGB4444          DMA2D_OUTPUT_ARGB4444

+

+#define CM_ARGB8888             DMA2D_INPUT_ARGB8888

+#define CM_RGB888               DMA2D_INPUT_RGB888

+#define CM_RGB565               DMA2D_INPUT_RGB565

+#define CM_ARGB1555             DMA2D_INPUT_ARGB1555

+#define CM_ARGB4444             DMA2D_INPUT_ARGB4444

+#define CM_L8                   DMA2D_INPUT_L8

+#define CM_AL44                 DMA2D_INPUT_AL44

+#define CM_AL88                 DMA2D_INPUT_AL88

+#define CM_L4                   DMA2D_INPUT_L4

+#define CM_A8                   DMA2D_INPUT_A8

+#define CM_A4                   DMA2D_INPUT_A4

+/**

+  * @}

+  */

+#endif  /* STM32L4 ||  STM32F7 ||  STM32F4 ||  STM32H7 */

+

+/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+

+/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose

+  * @{

+  */

+#define HAL_CRYP_ComputationCpltCallback     HAL_CRYPEx_ComputationCpltCallback

+/**

+  * @}

+  */

+

+/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose

+  * @{

+  */

+#define HAL_HASH_STATETypeDef        HAL_HASH_StateTypeDef

+#define HAL_HASHPhaseTypeDef         HAL_HASH_PhaseTypeDef

+#define HAL_HMAC_MD5_Finish          HAL_HASH_MD5_Finish

+#define HAL_HMAC_SHA1_Finish         HAL_HASH_SHA1_Finish

+#define HAL_HMAC_SHA224_Finish       HAL_HASH_SHA224_Finish

+#define HAL_HMAC_SHA256_Finish       HAL_HASH_SHA256_Finish

+

+/*HASH Algorithm Selection*/

+

+#define HASH_AlgoSelection_SHA1      HASH_ALGOSELECTION_SHA1

+#define HASH_AlgoSelection_SHA224    HASH_ALGOSELECTION_SHA224

+#define HASH_AlgoSelection_SHA256    HASH_ALGOSELECTION_SHA256

+#define HASH_AlgoSelection_MD5       HASH_ALGOSELECTION_MD5

+

+#define HASH_AlgoMode_HASH         HASH_ALGOMODE_HASH

+#define HASH_AlgoMode_HMAC         HASH_ALGOMODE_HMAC

+

+#define HASH_HMACKeyType_ShortKey  HASH_HMAC_KEYTYPE_SHORTKEY

+#define HASH_HMACKeyType_LongKey   HASH_HMAC_KEYTYPE_LONGKEY

+

+#if defined(STM32L4) || defined(STM32L5) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7)

+

+#define HAL_HASH_MD5_Accumulate                HAL_HASH_MD5_Accmlt

+#define HAL_HASH_MD5_Accumulate_End            HAL_HASH_MD5_Accmlt_End

+#define HAL_HASH_MD5_Accumulate_IT             HAL_HASH_MD5_Accmlt_IT

+#define HAL_HASH_MD5_Accumulate_End_IT         HAL_HASH_MD5_Accmlt_End_IT

+

+#define HAL_HASH_SHA1_Accumulate               HAL_HASH_SHA1_Accmlt

+#define HAL_HASH_SHA1_Accumulate_End           HAL_HASH_SHA1_Accmlt_End

+#define HAL_HASH_SHA1_Accumulate_IT            HAL_HASH_SHA1_Accmlt_IT

+#define HAL_HASH_SHA1_Accumulate_End_IT        HAL_HASH_SHA1_Accmlt_End_IT

+

+#define HAL_HASHEx_SHA224_Accumulate           HAL_HASHEx_SHA224_Accmlt

+#define HAL_HASHEx_SHA224_Accumulate_End       HAL_HASHEx_SHA224_Accmlt_End

+#define HAL_HASHEx_SHA224_Accumulate_IT        HAL_HASHEx_SHA224_Accmlt_IT

+#define HAL_HASHEx_SHA224_Accumulate_End_IT    HAL_HASHEx_SHA224_Accmlt_End_IT

+

+#define HAL_HASHEx_SHA256_Accumulate           HAL_HASHEx_SHA256_Accmlt

+#define HAL_HASHEx_SHA256_Accumulate_End       HAL_HASHEx_SHA256_Accmlt_End

+#define HAL_HASHEx_SHA256_Accumulate_IT        HAL_HASHEx_SHA256_Accmlt_IT

+#define HAL_HASHEx_SHA256_Accumulate_End_IT    HAL_HASHEx_SHA256_Accmlt_End_IT

+

+#endif  /* STM32L4 || STM32L5 || STM32F4 || STM32F7 || STM32H7 */

+/**

+  * @}

+  */

+

+/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose

+  * @{

+  */

+#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode

+#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode

+#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode

+#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode

+#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode

+#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode

+#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))

+#define HAL_VREFINT_OutputSelect  HAL_SYSCFG_VREFINT_OutputSelect

+#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())

+#if defined(STM32L0)

+#else

+#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())

+#endif

+#define HAL_ADC_EnableBuffer_Cmd(cmd)  (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())

+#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ?  HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())

+#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)

+#define HAL_EnableSRDomainDBGStopMode      HAL_EnableDomain3DBGStopMode

+#define HAL_DisableSRDomainDBGStopMode     HAL_DisableDomain3DBGStopMode

+#define HAL_EnableSRDomainDBGStandbyMode   HAL_EnableDomain3DBGStandbyMode

+#define HAL_DisableSRDomainDBGStandbyMode  HAL_DisableDomain3DBGStandbyMode

+#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ  || STM32H7B0xxQ */

+

+/**

+  * @}

+  */

+

+/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose

+  * @{

+  */

+#define FLASH_HalfPageProgram      HAL_FLASHEx_HalfPageProgram

+#define FLASH_EnableRunPowerDown   HAL_FLASHEx_EnableRunPowerDown

+#define FLASH_DisableRunPowerDown  HAL_FLASHEx_DisableRunPowerDown

+#define HAL_DATA_EEPROMEx_Unlock   HAL_FLASHEx_DATAEEPROM_Unlock

+#define HAL_DATA_EEPROMEx_Lock     HAL_FLASHEx_DATAEEPROM_Lock

+#define HAL_DATA_EEPROMEx_Erase    HAL_FLASHEx_DATAEEPROM_Erase

+#define HAL_DATA_EEPROMEx_Program  HAL_FLASHEx_DATAEEPROM_Program

+

+ /**

+  * @}

+  */

+

+/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose

+  * @{

+  */

+#define HAL_I2CEx_AnalogFilter_Config         HAL_I2CEx_ConfigAnalogFilter

+#define HAL_I2CEx_DigitalFilter_Config        HAL_I2CEx_ConfigDigitalFilter

+#define HAL_FMPI2CEx_AnalogFilter_Config      HAL_FMPI2CEx_ConfigAnalogFilter

+#define HAL_FMPI2CEx_DigitalFilter_Config     HAL_FMPI2CEx_ConfigDigitalFilter

+

+#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))

+

+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)

+#define HAL_I2C_Master_Sequential_Transmit_IT  HAL_I2C_Master_Seq_Transmit_IT

+#define HAL_I2C_Master_Sequential_Receive_IT   HAL_I2C_Master_Seq_Receive_IT

+#define HAL_I2C_Slave_Sequential_Transmit_IT   HAL_I2C_Slave_Seq_Transmit_IT

+#define HAL_I2C_Slave_Sequential_Receive_IT    HAL_I2C_Slave_Seq_Receive_IT

+#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */

+#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)

+#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA

+#define HAL_I2C_Master_Sequential_Receive_DMA  HAL_I2C_Master_Seq_Receive_DMA

+#define HAL_I2C_Slave_Sequential_Transmit_DMA  HAL_I2C_Slave_Seq_Transmit_DMA

+#define HAL_I2C_Slave_Sequential_Receive_DMA   HAL_I2C_Slave_Seq_Receive_DMA

+#endif /* STM32H7 || STM32WB  || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */

+

+#if defined(STM32F4)

+#define HAL_FMPI2C_Master_Sequential_Transmit_IT  HAL_FMPI2C_Master_Seq_Transmit_IT

+#define HAL_FMPI2C_Master_Sequential_Receive_IT   HAL_FMPI2C_Master_Seq_Receive_IT

+#define HAL_FMPI2C_Slave_Sequential_Transmit_IT   HAL_FMPI2C_Slave_Seq_Transmit_IT

+#define HAL_FMPI2C_Slave_Sequential_Receive_IT    HAL_FMPI2C_Slave_Seq_Receive_IT

+#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA

+#define HAL_FMPI2C_Master_Sequential_Receive_DMA  HAL_FMPI2C_Master_Seq_Receive_DMA

+#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA  HAL_FMPI2C_Slave_Seq_Transmit_DMA

+#define HAL_FMPI2C_Slave_Sequential_Receive_DMA   HAL_FMPI2C_Slave_Seq_Receive_DMA

+#endif /* STM32F4 */

+ /**

+  * @}

+  */

+

+/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose

+  * @{

+  */

+

+#if defined(STM32G0)

+#define HAL_PWR_ConfigPVD                             HAL_PWREx_ConfigPVD

+#define HAL_PWR_EnablePVD                             HAL_PWREx_EnablePVD

+#define HAL_PWR_DisablePVD                            HAL_PWREx_DisablePVD

+#define HAL_PWR_PVD_IRQHandler                        HAL_PWREx_PVD_IRQHandler

+#endif

+#define HAL_PWR_PVDConfig                             HAL_PWR_ConfigPVD

+#define HAL_PWR_DisableBkUpReg                        HAL_PWREx_DisableBkUpReg

+#define HAL_PWR_DisableFlashPowerDown                 HAL_PWREx_DisableFlashPowerDown

+#define HAL_PWR_DisableVddio2Monitor                  HAL_PWREx_DisableVddio2Monitor

+#define HAL_PWR_EnableBkUpReg                         HAL_PWREx_EnableBkUpReg

+#define HAL_PWR_EnableFlashPowerDown                  HAL_PWREx_EnableFlashPowerDown

+#define HAL_PWR_EnableVddio2Monitor                   HAL_PWREx_EnableVddio2Monitor

+#define HAL_PWR_PVD_PVM_IRQHandler                    HAL_PWREx_PVD_PVM_IRQHandler

+#define HAL_PWR_PVDLevelConfig                        HAL_PWR_ConfigPVD

+#define HAL_PWR_Vddio2Monitor_IRQHandler              HAL_PWREx_Vddio2Monitor_IRQHandler

+#define HAL_PWR_Vddio2MonitorCallback                 HAL_PWREx_Vddio2MonitorCallback

+#define HAL_PWREx_ActivateOverDrive                   HAL_PWREx_EnableOverDrive

+#define HAL_PWREx_DeactivateOverDrive                 HAL_PWREx_DisableOverDrive

+#define HAL_PWREx_DisableSDADCAnalog                  HAL_PWREx_DisableSDADC

+#define HAL_PWREx_EnableSDADCAnalog                   HAL_PWREx_EnableSDADC

+#define HAL_PWREx_PVMConfig                           HAL_PWREx_ConfigPVM

+

+#define PWR_MODE_NORMAL                               PWR_PVD_MODE_NORMAL

+#define PWR_MODE_IT_RISING                            PWR_PVD_MODE_IT_RISING

+#define PWR_MODE_IT_FALLING                           PWR_PVD_MODE_IT_FALLING

+#define PWR_MODE_IT_RISING_FALLING                    PWR_PVD_MODE_IT_RISING_FALLING

+#define PWR_MODE_EVENT_RISING                         PWR_PVD_MODE_EVENT_RISING

+#define PWR_MODE_EVENT_FALLING                        PWR_PVD_MODE_EVENT_FALLING

+#define PWR_MODE_EVENT_RISING_FALLING                 PWR_PVD_MODE_EVENT_RISING_FALLING

+

+#define CR_OFFSET_BB                                  PWR_CR_OFFSET_BB

+#define CSR_OFFSET_BB                                 PWR_CSR_OFFSET_BB

+#define PMODE_BIT_NUMBER                              VOS_BIT_NUMBER

+#define CR_PMODE_BB                                   CR_VOS_BB

+

+#define DBP_BitNumber                                 DBP_BIT_NUMBER

+#define PVDE_BitNumber                                PVDE_BIT_NUMBER

+#define PMODE_BitNumber                               PMODE_BIT_NUMBER

+#define EWUP_BitNumber                                EWUP_BIT_NUMBER

+#define FPDS_BitNumber                                FPDS_BIT_NUMBER

+#define ODEN_BitNumber                                ODEN_BIT_NUMBER

+#define ODSWEN_BitNumber                              ODSWEN_BIT_NUMBER

+#define MRLVDS_BitNumber                              MRLVDS_BIT_NUMBER

+#define LPLVDS_BitNumber                              LPLVDS_BIT_NUMBER

+#define BRE_BitNumber                                 BRE_BIT_NUMBER

+

+#define PWR_MODE_EVT                                  PWR_PVD_MODE_NORMAL

+

+ /**

+  * @}

+  */

+

+/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose

+  * @{

+  */

+#define HAL_SMBUS_Slave_Listen_IT          HAL_SMBUS_EnableListen_IT

+#define HAL_SMBUS_SlaveAddrCallback        HAL_SMBUS_AddrCallback

+#define HAL_SMBUS_SlaveListenCpltCallback  HAL_SMBUS_ListenCpltCallback

+/**

+  * @}

+  */

+

+/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose

+  * @{

+  */

+#define HAL_SPI_FlushRxFifo                HAL_SPIEx_FlushRxFifo

+/**

+  * @}

+  */

+

+/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose

+  * @{

+  */

+#define HAL_TIM_DMADelayPulseCplt                       TIM_DMADelayPulseCplt

+#define HAL_TIM_DMAError                                TIM_DMAError

+#define HAL_TIM_DMACaptureCplt                          TIM_DMACaptureCplt

+#define HAL_TIMEx_DMACommutationCplt                    TIMEx_DMACommutationCplt

+#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)

+#define HAL_TIM_SlaveConfigSynchronization              HAL_TIM_SlaveConfigSynchro

+#define HAL_TIM_SlaveConfigSynchronization_IT           HAL_TIM_SlaveConfigSynchro_IT

+#define HAL_TIMEx_CommutationCallback                   HAL_TIMEx_CommutCallback

+#define HAL_TIMEx_ConfigCommutationEvent                HAL_TIMEx_ConfigCommutEvent

+#define HAL_TIMEx_ConfigCommutationEvent_IT             HAL_TIMEx_ConfigCommutEvent_IT

+#define HAL_TIMEx_ConfigCommutationEvent_DMA            HAL_TIMEx_ConfigCommutEvent_DMA

+#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */

+/**

+  * @}

+  */

+

+/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose

+  * @{

+  */

+#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback

+/**

+  * @}

+  */

+

+/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose

+  * @{

+  */

+#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback

+#define HAL_LTDC_Relaod           HAL_LTDC_Reload

+#define HAL_LTDC_StructInitFromVideoConfig  HAL_LTDCEx_StructInitFromVideoConfig

+#define HAL_LTDC_StructInitFromAdaptedCommandConfig  HAL_LTDCEx_StructInitFromAdaptedCommandConfig

+/**

+  * @}

+  */

+

+

+/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macros ------------------------------------------------------------*/

+

+/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose

+  * @{

+  */

+#define AES_IT_CC                      CRYP_IT_CC

+#define AES_IT_ERR                     CRYP_IT_ERR

+#define AES_FLAG_CCF                   CRYP_FLAG_CCF

+/**

+  * @}

+  */

+

+/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose

+  * @{

+  */

+#define __HAL_GET_BOOT_MODE                   __HAL_SYSCFG_GET_BOOT_MODE

+#define __HAL_REMAPMEMORY_FLASH               __HAL_SYSCFG_REMAPMEMORY_FLASH

+#define __HAL_REMAPMEMORY_SYSTEMFLASH         __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH

+#define __HAL_REMAPMEMORY_SRAM                __HAL_SYSCFG_REMAPMEMORY_SRAM

+#define __HAL_REMAPMEMORY_FMC                 __HAL_SYSCFG_REMAPMEMORY_FMC

+#define __HAL_REMAPMEMORY_FMC_SDRAM           __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM

+#define __HAL_REMAPMEMORY_FSMC                __HAL_SYSCFG_REMAPMEMORY_FSMC

+#define __HAL_REMAPMEMORY_QUADSPI             __HAL_SYSCFG_REMAPMEMORY_QUADSPI

+#define __HAL_FMC_BANK                        __HAL_SYSCFG_FMC_BANK

+#define __HAL_GET_FLAG                        __HAL_SYSCFG_GET_FLAG

+#define __HAL_CLEAR_FLAG                      __HAL_SYSCFG_CLEAR_FLAG

+#define __HAL_VREFINT_OUT_ENABLE              __HAL_SYSCFG_VREFINT_OUT_ENABLE

+#define __HAL_VREFINT_OUT_DISABLE             __HAL_SYSCFG_VREFINT_OUT_DISABLE

+#define __HAL_SYSCFG_SRAM2_WRP_ENABLE         __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE

+

+#define SYSCFG_FLAG_VREF_READY                SYSCFG_FLAG_VREFINT_READY

+#define SYSCFG_FLAG_RC48                      RCC_FLAG_HSI48

+#define IS_SYSCFG_FASTMODEPLUS_CONFIG         IS_I2C_FASTMODEPLUS

+#define UFB_MODE_BitNumber                    UFB_MODE_BIT_NUMBER

+#define CMP_PD_BitNumber                      CMP_PD_BIT_NUMBER

+

+/**

+  * @}

+  */

+

+

+/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose

+  * @{

+  */

+#define __ADC_ENABLE                                     __HAL_ADC_ENABLE

+#define __ADC_DISABLE                                    __HAL_ADC_DISABLE

+#define __HAL_ADC_ENABLING_CONDITIONS                    ADC_ENABLING_CONDITIONS

+#define __HAL_ADC_DISABLING_CONDITIONS                   ADC_DISABLING_CONDITIONS

+#define __HAL_ADC_IS_ENABLED                             ADC_IS_ENABLE

+#define __ADC_IS_ENABLED                                 ADC_IS_ENABLE

+#define __HAL_ADC_IS_SOFTWARE_START_REGULAR              ADC_IS_SOFTWARE_START_REGULAR

+#define __HAL_ADC_IS_SOFTWARE_START_INJECTED             ADC_IS_SOFTWARE_START_INJECTED

+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED

+#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR          ADC_IS_CONVERSION_ONGOING_REGULAR

+#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED         ADC_IS_CONVERSION_ONGOING_INJECTED

+#define __HAL_ADC_IS_CONVERSION_ONGOING                  ADC_IS_CONVERSION_ONGOING

+#define __HAL_ADC_CLEAR_ERRORCODE                        ADC_CLEAR_ERRORCODE

+

+#define __HAL_ADC_GET_RESOLUTION                         ADC_GET_RESOLUTION

+#define __HAL_ADC_JSQR_RK                                ADC_JSQR_RK

+#define __HAL_ADC_CFGR_AWD1CH                            ADC_CFGR_AWD1CH_SHIFT

+#define __HAL_ADC_CFGR_AWD23CR                           ADC_CFGR_AWD23CR

+#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION            ADC_CFGR_INJECT_AUTO_CONVERSION

+#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE              ADC_CFGR_INJECT_CONTEXT_QUEUE

+#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS             ADC_CFGR_INJECT_DISCCONTINUOUS

+#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS                ADC_CFGR_REG_DISCCONTINUOUS

+#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM                 ADC_CFGR_DISCONTINUOUS_NUM

+#define __HAL_ADC_CFGR_AUTOWAIT                          ADC_CFGR_AUTOWAIT

+#define __HAL_ADC_CFGR_CONTINUOUS                        ADC_CFGR_CONTINUOUS

+#define __HAL_ADC_CFGR_OVERRUN                           ADC_CFGR_OVERRUN

+#define __HAL_ADC_CFGR_DMACONTREQ                        ADC_CFGR_DMACONTREQ

+#define __HAL_ADC_CFGR_EXTSEL                            ADC_CFGR_EXTSEL_SET

+#define __HAL_ADC_JSQR_JEXTSEL                           ADC_JSQR_JEXTSEL_SET

+#define __HAL_ADC_OFR_CHANNEL                            ADC_OFR_CHANNEL

+#define __HAL_ADC_DIFSEL_CHANNEL                         ADC_DIFSEL_CHANNEL

+#define __HAL_ADC_CALFACT_DIFF_SET                       ADC_CALFACT_DIFF_SET

+#define __HAL_ADC_CALFACT_DIFF_GET                       ADC_CALFACT_DIFF_GET

+#define __HAL_ADC_TRX_HIGHTHRESHOLD                      ADC_TRX_HIGHTHRESHOLD

+

+#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION                ADC_OFFSET_SHIFT_RESOLUTION

+#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION         ADC_AWD1THRESHOLD_SHIFT_RESOLUTION

+#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION        ADC_AWD23THRESHOLD_SHIFT_RESOLUTION

+#define __HAL_ADC_COMMON_REGISTER                        ADC_COMMON_REGISTER

+#define __HAL_ADC_COMMON_CCR_MULTI                       ADC_COMMON_CCR_MULTI

+#define __HAL_ADC_MULTIMODE_IS_ENABLED                   ADC_MULTIMODE_IS_ENABLE

+#define __ADC_MULTIMODE_IS_ENABLED                       ADC_MULTIMODE_IS_ENABLE

+#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER        ADC_NONMULTIMODE_OR_MULTIMODEMASTER

+#define __HAL_ADC_COMMON_ADC_OTHER                       ADC_COMMON_ADC_OTHER

+#define __HAL_ADC_MULTI_SLAVE                            ADC_MULTI_SLAVE

+

+#define __HAL_ADC_SQR1_L                                 ADC_SQR1_L_SHIFT

+#define __HAL_ADC_JSQR_JL                                ADC_JSQR_JL_SHIFT

+#define __HAL_ADC_JSQR_RK_JL                             ADC_JSQR_RK_JL

+#define __HAL_ADC_CR1_DISCONTINUOUS_NUM                  ADC_CR1_DISCONTINUOUS_NUM

+#define __HAL_ADC_CR1_SCAN                               ADC_CR1_SCAN_SET

+#define __HAL_ADC_CONVCYCLES_MAX_RANGE                   ADC_CONVCYCLES_MAX_RANGE

+#define __HAL_ADC_CLOCK_PRESCALER_RANGE                  ADC_CLOCK_PRESCALER_RANGE

+#define __HAL_ADC_GET_CLOCK_PRESCALER                    ADC_GET_CLOCK_PRESCALER

+

+#define __HAL_ADC_SQR1                                   ADC_SQR1

+#define __HAL_ADC_SMPR1                                  ADC_SMPR1

+#define __HAL_ADC_SMPR2                                  ADC_SMPR2

+#define __HAL_ADC_SQR3_RK                                ADC_SQR3_RK

+#define __HAL_ADC_SQR2_RK                                ADC_SQR2_RK

+#define __HAL_ADC_SQR1_RK                                ADC_SQR1_RK

+#define __HAL_ADC_CR2_CONTINUOUS                         ADC_CR2_CONTINUOUS

+#define __HAL_ADC_CR1_DISCONTINUOUS                      ADC_CR1_DISCONTINUOUS

+#define __HAL_ADC_CR1_SCANCONV                           ADC_CR1_SCANCONV

+#define __HAL_ADC_CR2_EOCSelection                       ADC_CR2_EOCSelection

+#define __HAL_ADC_CR2_DMAContReq                         ADC_CR2_DMAContReq

+#define __HAL_ADC_JSQR                                   ADC_JSQR

+

+#define __HAL_ADC_CHSELR_CHANNEL                         ADC_CHSELR_CHANNEL

+#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS               ADC_CFGR1_REG_DISCCONTINUOUS

+#define __HAL_ADC_CFGR1_AUTOOFF                          ADC_CFGR1_AUTOOFF

+#define __HAL_ADC_CFGR1_AUTOWAIT                         ADC_CFGR1_AUTOWAIT

+#define __HAL_ADC_CFGR1_CONTINUOUS                       ADC_CFGR1_CONTINUOUS

+#define __HAL_ADC_CFGR1_OVERRUN                          ADC_CFGR1_OVERRUN

+#define __HAL_ADC_CFGR1_SCANDIR                          ADC_CFGR1_SCANDIR

+#define __HAL_ADC_CFGR1_DMACONTREQ                       ADC_CFGR1_DMACONTREQ

+

+/**

+  * @}

+  */

+

+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose

+  * @{

+  */

+#define __HAL_DHR12R1_ALIGNEMENT                        DAC_DHR12R1_ALIGNMENT

+#define __HAL_DHR12R2_ALIGNEMENT                        DAC_DHR12R2_ALIGNMENT

+#define __HAL_DHR12RD_ALIGNEMENT                        DAC_DHR12RD_ALIGNMENT

+#define IS_DAC_GENERATE_WAVE                            IS_DAC_WAVE

+

+/**

+  * @}

+  */

+

+/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose

+  * @{

+  */

+#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1

+#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1

+#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2

+#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2

+#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3

+#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3

+#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4

+#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4

+#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5

+#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5

+#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6

+#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6

+#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7

+#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7

+#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8

+#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8

+

+#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9

+#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9

+#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10

+#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10

+#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11

+#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11

+#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12

+#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12

+#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13

+#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13

+#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14

+#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14

+#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2

+#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2

+

+

+#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15

+#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15

+#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16

+#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16

+#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17

+#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17

+#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC

+#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC

+#if defined(STM32H7)

+  #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1

+  #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1

+  #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1

+  #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1

+#else

+  #define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG

+  #define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG

+  #define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG

+  #define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG

+#endif /* STM32H7 */

+#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT

+#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT

+#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT

+#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT

+#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT

+#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT

+#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1

+#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1

+#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1

+#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1

+#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2

+#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2

+

+/**

+  * @}

+  */

+

+/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose

+  * @{

+  */

+#if defined(STM32F3)

+#define COMP_START                                       __HAL_COMP_ENABLE

+#define COMP_STOP                                        __HAL_COMP_DISABLE

+#define COMP_LOCK                                        __HAL_COMP_LOCK

+

+#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)

+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \

+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())

+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \

+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())

+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \

+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())

+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \

+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())

+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \

+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())

+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \

+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())

+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \

+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \

+                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())

+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \

+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \

+                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())

+# endif

+# if defined(STM32F302xE) || defined(STM32F302xC)

+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \

+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())

+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \

+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE())

+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \

+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE())

+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \

+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE())

+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \

+                                                          __HAL_COMP_COMP6_EXTI_ENABLE_IT())

+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \

+                                                          __HAL_COMP_COMP6_EXTI_DISABLE_IT())

+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \

+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \

+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \

+                                                          __HAL_COMP_COMP6_EXTI_GET_FLAG())

+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \

+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \

+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \

+                                                          __HAL_COMP_COMP6_EXTI_CLEAR_FLAG())

+# endif

+# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)

+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \

+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE())

+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \

+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE())

+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \

+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE())

+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \

+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE())

+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \

+                                                          __HAL_COMP_COMP7_EXTI_ENABLE_IT())

+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \

+                                                          ((__EXTILINE__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \

+                                                          __HAL_COMP_COMP7_EXTI_DISABLE_IT())

+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \

+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \

+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \

+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \

+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \

+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \

+                                                          __HAL_COMP_COMP7_EXTI_GET_FLAG())

+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \

+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \

+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \

+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \

+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \

+                                                          ((__FLAG__)  == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \

+                                                          __HAL_COMP_COMP7_EXTI_CLEAR_FLAG())

+# endif

+# if defined(STM32F373xC) ||defined(STM32F378xx)

+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \

+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())

+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \

+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())

+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \

+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())

+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \

+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())

+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \

+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())

+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \

+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())

+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \

+                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())

+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \

+                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())

+# endif

+#else

+#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__)   (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \

+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())

+#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \

+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE())

+#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__)  (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \

+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE())

+#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \

+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE())

+#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__)          (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \

+                                                          __HAL_COMP_COMP2_EXTI_ENABLE_IT())

+#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__)         (((__EXTILINE__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \

+                                                          __HAL_COMP_COMP2_EXTI_DISABLE_IT())

+#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__)               (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \

+                                                          __HAL_COMP_COMP2_EXTI_GET_FLAG())

+#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)             (((__FLAG__)  == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \

+                                                          __HAL_COMP_COMP2_EXTI_CLEAR_FLAG())

+#endif

+

+#define __HAL_COMP_GET_EXTI_LINE  COMP_GET_EXTI_LINE

+

+#if defined(STM32L0) || defined(STM32L4)

+/* Note: On these STM32 families, the only argument of this macro             */

+/*       is COMP_FLAG_LOCK.                                                   */

+/*       This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle  */

+/*       argument.                                                            */

+#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__)  (__HAL_COMP_IS_LOCKED(__HANDLE__))

+#endif

+/**

+  * @}

+  */

+

+#if defined(STM32L0) || defined(STM32L4)

+/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose

+  * @{

+  */

+#define HAL_COMP_Start_IT       HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */

+#define HAL_COMP_Stop_IT        HAL_COMP_Stop  /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */

+/**

+  * @}

+  */

+#endif

+

+/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose

+  * @{

+  */

+

+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \

+                          ((WAVE) == DAC_WAVE_NOISE)|| \

+                          ((WAVE) == DAC_WAVE_TRIANGLE))

+

+/**

+  * @}

+  */

+

+/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose

+  * @{

+  */

+

+#define IS_WRPAREA          IS_OB_WRPAREA

+#define IS_TYPEPROGRAM      IS_FLASH_TYPEPROGRAM

+#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM

+#define IS_TYPEERASE        IS_FLASH_TYPEERASE

+#define IS_NBSECTORS        IS_FLASH_NBSECTORS

+#define IS_OB_WDG_SOURCE    IS_OB_IWDG_SOURCE

+

+/**

+  * @}

+  */

+

+/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose

+  * @{

+  */

+

+#define __HAL_I2C_RESET_CR2             I2C_RESET_CR2

+#define __HAL_I2C_GENERATE_START        I2C_GENERATE_START

+#if defined(STM32F1)

+#define __HAL_I2C_FREQ_RANGE            I2C_FREQRANGE

+#else

+#define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE

+#endif /* STM32F1 */

+#define __HAL_I2C_RISE_TIME             I2C_RISE_TIME

+#define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD

+#define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST

+#define __HAL_I2C_SPEED                 I2C_SPEED

+#define __HAL_I2C_7BIT_ADD_WRITE        I2C_7BIT_ADD_WRITE

+#define __HAL_I2C_7BIT_ADD_READ         I2C_7BIT_ADD_READ

+#define __HAL_I2C_10BIT_ADDRESS         I2C_10BIT_ADDRESS

+#define __HAL_I2C_10BIT_HEADER_WRITE    I2C_10BIT_HEADER_WRITE

+#define __HAL_I2C_10BIT_HEADER_READ     I2C_10BIT_HEADER_READ

+#define __HAL_I2C_MEM_ADD_MSB           I2C_MEM_ADD_MSB

+#define __HAL_I2C_MEM_ADD_LSB           I2C_MEM_ADD_LSB

+#define __HAL_I2C_FREQRANGE             I2C_FREQRANGE

+/**

+  * @}

+  */

+

+/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose

+  * @{

+  */

+

+#define IS_I2S_INSTANCE                 IS_I2S_ALL_INSTANCE

+#define IS_I2S_INSTANCE_EXT             IS_I2S_ALL_INSTANCE_EXT

+

+#if defined(STM32H7)

+  #define __HAL_I2S_CLEAR_FREFLAG       __HAL_I2S_CLEAR_TIFREFLAG

+#endif

+

+/**

+  * @}

+  */

+

+/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose

+  * @{

+  */

+

+#define __IRDA_DISABLE                  __HAL_IRDA_DISABLE

+#define __IRDA_ENABLE                   __HAL_IRDA_ENABLE

+

+#define __HAL_IRDA_GETCLOCKSOURCE       IRDA_GETCLOCKSOURCE

+#define __HAL_IRDA_MASK_COMPUTATION     IRDA_MASK_COMPUTATION

+#define __IRDA_GETCLOCKSOURCE           IRDA_GETCLOCKSOURCE

+#define __IRDA_MASK_COMPUTATION         IRDA_MASK_COMPUTATION

+

+#define IS_IRDA_ONEBIT_SAMPLE           IS_IRDA_ONE_BIT_SAMPLE

+

+

+/**

+  * @}

+  */

+

+

+/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose

+  * @{

+  */

+#define __HAL_IWDG_ENABLE_WRITE_ACCESS  IWDG_ENABLE_WRITE_ACCESS

+#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS

+/**

+  * @}

+  */

+

+

+/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose

+  * @{

+  */

+

+#define __HAL_LPTIM_ENABLE_INTERRUPT    __HAL_LPTIM_ENABLE_IT

+#define __HAL_LPTIM_DISABLE_INTERRUPT   __HAL_LPTIM_DISABLE_IT

+#define __HAL_LPTIM_GET_ITSTATUS        __HAL_LPTIM_GET_IT_SOURCE

+

+/**

+  * @}

+  */

+

+

+/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose

+  * @{

+  */

+#define __OPAMP_CSR_OPAXPD                OPAMP_CSR_OPAXPD

+#define __OPAMP_CSR_S3SELX                OPAMP_CSR_S3SELX

+#define __OPAMP_CSR_S4SELX                OPAMP_CSR_S4SELX

+#define __OPAMP_CSR_S5SELX                OPAMP_CSR_S5SELX

+#define __OPAMP_CSR_S6SELX                OPAMP_CSR_S6SELX

+#define __OPAMP_CSR_OPAXCAL_L             OPAMP_CSR_OPAXCAL_L

+#define __OPAMP_CSR_OPAXCAL_H             OPAMP_CSR_OPAXCAL_H

+#define __OPAMP_CSR_OPAXLPM               OPAMP_CSR_OPAXLPM

+#define __OPAMP_CSR_ALL_SWITCHES          OPAMP_CSR_ALL_SWITCHES

+#define __OPAMP_CSR_ANAWSELX              OPAMP_CSR_ANAWSELX

+#define __OPAMP_CSR_OPAXCALOUT            OPAMP_CSR_OPAXCALOUT

+#define __OPAMP_OFFSET_TRIM_BITSPOSITION  OPAMP_OFFSET_TRIM_BITSPOSITION

+#define __OPAMP_OFFSET_TRIM_SET           OPAMP_OFFSET_TRIM_SET

+

+/**

+  * @}

+  */

+

+

+/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose

+  * @{

+  */

+#define __HAL_PVD_EVENT_DISABLE                                  __HAL_PWR_PVD_EXTI_DISABLE_EVENT

+#define __HAL_PVD_EVENT_ENABLE                                   __HAL_PWR_PVD_EXTI_ENABLE_EVENT

+#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE

+#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE

+#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE

+#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE

+#define __HAL_PVM_EVENT_DISABLE                                  __HAL_PWR_PVM_EVENT_DISABLE

+#define __HAL_PVM_EVENT_ENABLE                                   __HAL_PWR_PVM_EVENT_ENABLE

+#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE                    __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE

+#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE                     __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE

+#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE                     __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE

+#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE                      __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE

+#define __HAL_PWR_INTERNALWAKEUP_DISABLE                         HAL_PWREx_DisableInternalWakeUpLine

+#define __HAL_PWR_INTERNALWAKEUP_ENABLE                          HAL_PWREx_EnableInternalWakeUpLine

+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE                    HAL_PWREx_DisablePullUpPullDownConfig

+#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE                     HAL_PWREx_EnablePullUpPullDownConfig

+#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()                  do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)

+#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE                         __HAL_PWR_PVD_EXTI_DISABLE_EVENT

+#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE                          __HAL_PWR_PVD_EXTI_ENABLE_EVENT

+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE                __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE

+#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE                 __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE

+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE                 __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE

+#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE                  __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE

+#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER              __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE

+#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER               __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE

+#define __HAL_PWR_PVM_DISABLE()                                  do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)

+#define __HAL_PWR_PVM_ENABLE()                                   do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)

+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE                  HAL_PWREx_DisableSRAM2ContentRetention

+#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE                   HAL_PWREx_EnableSRAM2ContentRetention

+#define __HAL_PWR_VDDIO2_DISABLE                                 HAL_PWREx_DisableVddIO2

+#define __HAL_PWR_VDDIO2_ENABLE                                  HAL_PWREx_EnableVddIO2

+#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER                 __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE

+#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER           __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE

+#define __HAL_PWR_VDDUSB_DISABLE                                 HAL_PWREx_DisableVddUSB

+#define __HAL_PWR_VDDUSB_ENABLE                                  HAL_PWREx_EnableVddUSB

+

+#if defined (STM32F4)

+#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD)         __HAL_PWR_PVD_EXTI_ENABLE_IT()

+#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_DISABLE_IT()

+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD)          __HAL_PWR_PVD_EXTI_GET_FLAG()

+#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD)        __HAL_PWR_PVD_EXTI_CLEAR_FLAG()

+#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD)     __HAL_PWR_PVD_EXTI_GENERATE_SWIT()

+#else

+#define __HAL_PVD_EXTI_CLEAR_FLAG                                __HAL_PWR_PVD_EXTI_CLEAR_FLAG

+#define __HAL_PVD_EXTI_DISABLE_IT                                __HAL_PWR_PVD_EXTI_DISABLE_IT

+#define __HAL_PVD_EXTI_ENABLE_IT                                 __HAL_PWR_PVD_EXTI_ENABLE_IT

+#define __HAL_PVD_EXTI_GENERATE_SWIT                             __HAL_PWR_PVD_EXTI_GENERATE_SWIT

+#define __HAL_PVD_EXTI_GET_FLAG                                  __HAL_PWR_PVD_EXTI_GET_FLAG

+#endif /* STM32F4 */

+/**

+  * @}

+  */

+

+

+/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose

+  * @{

+  */

+

+#define RCC_StopWakeUpClock_MSI     RCC_STOP_WAKEUPCLOCK_MSI

+#define RCC_StopWakeUpClock_HSI     RCC_STOP_WAKEUPCLOCK_HSI

+

+#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback

+#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())

+

+#define __ADC_CLK_DISABLE          __HAL_RCC_ADC_CLK_DISABLE

+#define __ADC_CLK_ENABLE           __HAL_RCC_ADC_CLK_ENABLE

+#define __ADC_CLK_SLEEP_DISABLE    __HAL_RCC_ADC_CLK_SLEEP_DISABLE

+#define __ADC_CLK_SLEEP_ENABLE     __HAL_RCC_ADC_CLK_SLEEP_ENABLE

+#define __ADC_FORCE_RESET          __HAL_RCC_ADC_FORCE_RESET

+#define __ADC_RELEASE_RESET        __HAL_RCC_ADC_RELEASE_RESET

+#define __ADC1_CLK_DISABLE         __HAL_RCC_ADC1_CLK_DISABLE

+#define __ADC1_CLK_ENABLE          __HAL_RCC_ADC1_CLK_ENABLE

+#define __ADC1_FORCE_RESET         __HAL_RCC_ADC1_FORCE_RESET

+#define __ADC1_RELEASE_RESET       __HAL_RCC_ADC1_RELEASE_RESET

+#define __ADC1_CLK_SLEEP_ENABLE    __HAL_RCC_ADC1_CLK_SLEEP_ENABLE

+#define __ADC1_CLK_SLEEP_DISABLE   __HAL_RCC_ADC1_CLK_SLEEP_DISABLE

+#define __ADC2_CLK_DISABLE         __HAL_RCC_ADC2_CLK_DISABLE

+#define __ADC2_CLK_ENABLE          __HAL_RCC_ADC2_CLK_ENABLE

+#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET

+#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET

+#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE

+#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE

+#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET

+#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET

+#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE

+#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE

+#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE

+#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE

+#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET

+#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET

+#define __CRYP_CLK_SLEEP_ENABLE      __HAL_RCC_CRYP_CLK_SLEEP_ENABLE

+#define __CRYP_CLK_SLEEP_DISABLE  __HAL_RCC_CRYP_CLK_SLEEP_DISABLE

+#define __CRYP_CLK_ENABLE  __HAL_RCC_CRYP_CLK_ENABLE

+#define __CRYP_CLK_DISABLE  __HAL_RCC_CRYP_CLK_DISABLE

+#define __CRYP_FORCE_RESET       __HAL_RCC_CRYP_FORCE_RESET

+#define __CRYP_RELEASE_RESET  __HAL_RCC_CRYP_RELEASE_RESET

+#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE

+#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE

+#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET

+#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET

+#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET

+#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET

+#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET

+#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET

+#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET

+#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET

+#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET

+#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET

+#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET

+#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET

+#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET

+#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET

+#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE

+#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE

+#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET

+#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET

+#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE

+#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE

+#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE

+#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE

+#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET

+#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET

+#define __CAN_CLK_DISABLE         __HAL_RCC_CAN1_CLK_DISABLE

+#define __CAN_CLK_ENABLE          __HAL_RCC_CAN1_CLK_ENABLE

+#define __CAN_FORCE_RESET         __HAL_RCC_CAN1_FORCE_RESET

+#define __CAN_RELEASE_RESET       __HAL_RCC_CAN1_RELEASE_RESET

+#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE

+#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE

+#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET

+#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET

+#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE

+#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE

+#define __COMP_CLK_DISABLE        __HAL_RCC_COMP_CLK_DISABLE

+#define __COMP_CLK_ENABLE         __HAL_RCC_COMP_CLK_ENABLE

+#define __COMP_FORCE_RESET        __HAL_RCC_COMP_FORCE_RESET

+#define __COMP_RELEASE_RESET      __HAL_RCC_COMP_RELEASE_RESET

+#define __COMP_CLK_SLEEP_ENABLE   __HAL_RCC_COMP_CLK_SLEEP_ENABLE

+#define __COMP_CLK_SLEEP_DISABLE  __HAL_RCC_COMP_CLK_SLEEP_DISABLE

+#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET

+#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET

+#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE

+#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE

+#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE

+#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE

+#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET

+#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET

+#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE

+#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE

+#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET

+#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET

+#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE

+#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE

+#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE

+#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE

+#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET

+#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET

+#define __DBGMCU_CLK_ENABLE     __HAL_RCC_DBGMCU_CLK_ENABLE

+#define __DBGMCU_CLK_DISABLE     __HAL_RCC_DBGMCU_CLK_DISABLE

+#define __DBGMCU_FORCE_RESET    __HAL_RCC_DBGMCU_FORCE_RESET

+#define __DBGMCU_RELEASE_RESET  __HAL_RCC_DBGMCU_RELEASE_RESET

+#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE

+#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE

+#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE

+#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE

+#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET

+#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET

+#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE

+#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE

+#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE

+#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE

+#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET

+#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET

+#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE

+#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE

+#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE

+#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE

+#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET

+#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET

+#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE

+#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE

+#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET

+#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET

+#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE

+#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE

+#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE

+#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE

+#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE

+#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE

+#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE

+#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE

+#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE

+#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE

+#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET

+#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET

+#define __FLITF_CLK_DISABLE       __HAL_RCC_FLITF_CLK_DISABLE

+#define __FLITF_CLK_ENABLE        __HAL_RCC_FLITF_CLK_ENABLE

+#define __FLITF_FORCE_RESET       __HAL_RCC_FLITF_FORCE_RESET

+#define __FLITF_RELEASE_RESET     __HAL_RCC_FLITF_RELEASE_RESET

+#define __FLITF_CLK_SLEEP_ENABLE  __HAL_RCC_FLITF_CLK_SLEEP_ENABLE

+#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE

+#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE

+#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE

+#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE

+#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE

+#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET

+#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET

+#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE

+#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE

+#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE

+#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE

+#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE

+#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE

+#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET

+#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET

+#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE

+#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE

+#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE

+#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE

+#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET

+#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET

+#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE

+#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE

+#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE

+#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE

+#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET

+#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET

+#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE

+#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE

+#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE

+#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE

+#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET

+#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET

+#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE

+#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE

+#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE

+#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE

+#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET

+#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET

+#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE

+#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE

+#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE

+#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE

+#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET

+#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET

+#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE

+#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE

+#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE

+#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE

+#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET

+#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET

+#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE

+#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE

+#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE

+#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE

+#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET

+#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET

+#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE

+#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE

+#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE

+#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE

+#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET

+#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET

+#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE

+#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE

+#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE

+#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE

+#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET

+#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET

+#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE

+#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE

+#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE

+#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE

+#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET

+#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET

+#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE

+#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE

+#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE

+#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE

+#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET

+#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET

+#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE

+#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE

+#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE

+#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE

+#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET

+#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET

+#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE

+#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE

+#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE

+#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE

+#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET

+#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET

+#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE

+#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE

+#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE

+#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE

+#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET

+#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET

+#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE

+#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE

+#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE

+#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE

+#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET

+#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET

+#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE

+#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE

+#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE

+#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE

+#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET

+#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET

+#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE

+#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE

+#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE

+#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE

+#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET

+#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET

+#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE

+#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE

+#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE

+#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE

+#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET

+#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET

+

+#if defined(STM32WB)

+#define __HAL_RCC_QSPI_CLK_DISABLE            __HAL_RCC_QUADSPI_CLK_DISABLE

+#define __HAL_RCC_QSPI_CLK_ENABLE             __HAL_RCC_QUADSPI_CLK_ENABLE

+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE      __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE

+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE       __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE

+#define __HAL_RCC_QSPI_FORCE_RESET            __HAL_RCC_QUADSPI_FORCE_RESET

+#define __HAL_RCC_QSPI_RELEASE_RESET          __HAL_RCC_QUADSPI_RELEASE_RESET

+#define __HAL_RCC_QSPI_IS_CLK_ENABLED         __HAL_RCC_QUADSPI_IS_CLK_ENABLED

+#define __HAL_RCC_QSPI_IS_CLK_DISABLED        __HAL_RCC_QUADSPI_IS_CLK_DISABLED

+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED   __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED

+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED  __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED

+#define QSPI_IRQHandler QUADSPI_IRQHandler

+#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */

+

+#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE

+#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE

+#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE

+#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE

+#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET

+#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET

+#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE

+#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE

+#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE

+#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE

+#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET

+#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET

+#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE

+#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE

+#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE

+#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE

+#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET

+#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET

+#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE

+#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE

+#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE

+#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE

+#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE

+#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE

+#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET

+#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET

+#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE

+#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE

+#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE

+#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE

+#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET

+#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET

+#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE

+#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE

+#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE

+#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE

+#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET

+#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET

+#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE

+#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE

+#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE

+#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE

+#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET

+#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET

+#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE

+#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE

+#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE

+#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE

+#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE

+#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE

+#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE

+#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE

+#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE

+#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE

+#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET

+#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET

+#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE

+#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE

+#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE

+#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE

+#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET

+#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET

+#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE

+#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE

+#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE

+#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE

+#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET

+#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET

+#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE

+#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE

+#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET

+#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET

+#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE

+#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE

+#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET

+#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET

+#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE

+#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE

+#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET

+#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET

+#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE

+#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE

+#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET

+#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET

+#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE

+#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE

+#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET

+#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET

+#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE

+#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE

+#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE

+#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE

+#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET

+#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET

+#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE

+#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE

+#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE

+#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE

+#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET

+#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET

+#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE

+#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE

+#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE

+#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE

+#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET

+#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET

+#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE

+#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE

+#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE

+#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE

+#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET

+#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET

+#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE

+#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE

+#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE

+#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE

+#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET

+#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET

+#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE

+#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE

+#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE

+#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE

+#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET

+#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET

+#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE

+#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE

+#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE

+#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE

+#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET

+#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET

+#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE

+#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE

+#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE

+#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE

+#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET

+#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET

+#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE

+#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE

+#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE

+#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE

+#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET

+#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET

+#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE

+#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE

+#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE

+#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE

+#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET

+#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET

+#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE

+#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE

+#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET

+#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET

+#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE

+#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE

+#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE

+#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE

+#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET

+#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET

+#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE

+#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE

+#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE

+#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE

+#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET

+#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET

+#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE

+#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE

+#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE

+#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE

+#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET

+#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET

+#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE

+#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE

+#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE

+#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE

+#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET

+#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET

+#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE

+#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE

+#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE

+#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE

+#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET

+#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET

+#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE

+#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE

+#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE

+#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE

+#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET

+#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET

+#define __USART4_CLK_DISABLE        __HAL_RCC_UART4_CLK_DISABLE

+#define __USART4_CLK_ENABLE         __HAL_RCC_UART4_CLK_ENABLE

+#define __USART4_CLK_SLEEP_ENABLE   __HAL_RCC_UART4_CLK_SLEEP_ENABLE

+#define __USART4_CLK_SLEEP_DISABLE  __HAL_RCC_UART4_CLK_SLEEP_DISABLE

+#define __USART4_FORCE_RESET        __HAL_RCC_UART4_FORCE_RESET

+#define __USART4_RELEASE_RESET      __HAL_RCC_UART4_RELEASE_RESET

+#define __USART5_CLK_DISABLE        __HAL_RCC_UART5_CLK_DISABLE

+#define __USART5_CLK_ENABLE         __HAL_RCC_UART5_CLK_ENABLE

+#define __USART5_CLK_SLEEP_ENABLE   __HAL_RCC_UART5_CLK_SLEEP_ENABLE

+#define __USART5_CLK_SLEEP_DISABLE  __HAL_RCC_UART5_CLK_SLEEP_DISABLE

+#define __USART5_FORCE_RESET        __HAL_RCC_UART5_FORCE_RESET

+#define __USART5_RELEASE_RESET      __HAL_RCC_UART5_RELEASE_RESET

+#define __USART7_CLK_DISABLE        __HAL_RCC_UART7_CLK_DISABLE

+#define __USART7_CLK_ENABLE         __HAL_RCC_UART7_CLK_ENABLE

+#define __USART7_FORCE_RESET        __HAL_RCC_UART7_FORCE_RESET

+#define __USART7_RELEASE_RESET      __HAL_RCC_UART7_RELEASE_RESET

+#define __USART8_CLK_DISABLE        __HAL_RCC_UART8_CLK_DISABLE

+#define __USART8_CLK_ENABLE         __HAL_RCC_UART8_CLK_ENABLE

+#define __USART8_FORCE_RESET        __HAL_RCC_UART8_FORCE_RESET

+#define __USART8_RELEASE_RESET      __HAL_RCC_UART8_RELEASE_RESET

+#define __USB_CLK_DISABLE         __HAL_RCC_USB_CLK_DISABLE

+#define __USB_CLK_ENABLE          __HAL_RCC_USB_CLK_ENABLE

+#define __USB_FORCE_RESET         __HAL_RCC_USB_FORCE_RESET

+#define __USB_CLK_SLEEP_ENABLE    __HAL_RCC_USB_CLK_SLEEP_ENABLE

+#define __USB_CLK_SLEEP_DISABLE   __HAL_RCC_USB_CLK_SLEEP_DISABLE

+#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE

+#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE

+#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET

+

+#if defined(STM32H7)

+#define __HAL_RCC_WWDG_CLK_DISABLE   __HAL_RCC_WWDG1_CLK_DISABLE

+#define __HAL_RCC_WWDG_CLK_ENABLE   __HAL_RCC_WWDG1_CLK_ENABLE

+#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE  __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE

+#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE  __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE

+

+#define __HAL_RCC_WWDG_FORCE_RESET    ((void)0U)  /* Not available on the STM32H7*/

+#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/

+

+

+#define  __HAL_RCC_WWDG_IS_CLK_ENABLED    __HAL_RCC_WWDG1_IS_CLK_ENABLED

+#define  __HAL_RCC_WWDG_IS_CLK_DISABLED  __HAL_RCC_WWDG1_IS_CLK_DISABLED

+#endif

+

+#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE

+#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE

+#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE

+#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE

+#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET

+#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET

+

+#define __TIM21_CLK_ENABLE   __HAL_RCC_TIM21_CLK_ENABLE

+#define __TIM21_CLK_DISABLE   __HAL_RCC_TIM21_CLK_DISABLE

+#define __TIM21_FORCE_RESET   __HAL_RCC_TIM21_FORCE_RESET

+#define __TIM21_RELEASE_RESET  __HAL_RCC_TIM21_RELEASE_RESET

+#define __TIM21_CLK_SLEEP_ENABLE   __HAL_RCC_TIM21_CLK_SLEEP_ENABLE

+#define __TIM21_CLK_SLEEP_DISABLE   __HAL_RCC_TIM21_CLK_SLEEP_DISABLE

+#define __TIM22_CLK_ENABLE   __HAL_RCC_TIM22_CLK_ENABLE

+#define __TIM22_CLK_DISABLE   __HAL_RCC_TIM22_CLK_DISABLE

+#define __TIM22_FORCE_RESET   __HAL_RCC_TIM22_FORCE_RESET

+#define __TIM22_RELEASE_RESET  __HAL_RCC_TIM22_RELEASE_RESET

+#define __TIM22_CLK_SLEEP_ENABLE   __HAL_RCC_TIM22_CLK_SLEEP_ENABLE

+#define __TIM22_CLK_SLEEP_DISABLE   __HAL_RCC_TIM22_CLK_SLEEP_DISABLE

+#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE

+#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE

+#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE

+#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE

+#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET

+#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET

+#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE

+#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE

+

+#define __USB_OTG_FS_FORCE_RESET  __HAL_RCC_USB_OTG_FS_FORCE_RESET

+#define __USB_OTG_FS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET

+#define __USB_OTG_FS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE

+#define __USB_OTG_FS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE

+#define __USB_OTG_HS_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_DISABLE

+#define __USB_OTG_HS_CLK_ENABLE          __HAL_RCC_USB_OTG_HS_CLK_ENABLE

+#define __USB_OTG_HS_ULPI_CLK_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE

+#define __USB_OTG_HS_ULPI_CLK_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE

+#define __TIM9_CLK_SLEEP_ENABLE          __HAL_RCC_TIM9_CLK_SLEEP_ENABLE

+#define __TIM9_CLK_SLEEP_DISABLE  __HAL_RCC_TIM9_CLK_SLEEP_DISABLE

+#define __TIM10_CLK_SLEEP_ENABLE  __HAL_RCC_TIM10_CLK_SLEEP_ENABLE

+#define __TIM10_CLK_SLEEP_DISABLE  __HAL_RCC_TIM10_CLK_SLEEP_DISABLE

+#define __TIM11_CLK_SLEEP_ENABLE  __HAL_RCC_TIM11_CLK_SLEEP_ENABLE

+#define __TIM11_CLK_SLEEP_DISABLE  __HAL_RCC_TIM11_CLK_SLEEP_DISABLE

+#define __ETHMACPTP_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE

+#define __ETHMACPTP_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE

+#define __ETHMACPTP_CLK_ENABLE          __HAL_RCC_ETHMACPTP_CLK_ENABLE

+#define __ETHMACPTP_CLK_DISABLE          __HAL_RCC_ETHMACPTP_CLK_DISABLE

+#define __HASH_CLK_ENABLE          __HAL_RCC_HASH_CLK_ENABLE

+#define __HASH_FORCE_RESET          __HAL_RCC_HASH_FORCE_RESET

+#define __HASH_RELEASE_RESET          __HAL_RCC_HASH_RELEASE_RESET

+#define __HASH_CLK_SLEEP_ENABLE          __HAL_RCC_HASH_CLK_SLEEP_ENABLE

+#define __HASH_CLK_SLEEP_DISABLE  __HAL_RCC_HASH_CLK_SLEEP_DISABLE

+#define __HASH_CLK_DISABLE            __HAL_RCC_HASH_CLK_DISABLE

+#define __SPI5_CLK_ENABLE          __HAL_RCC_SPI5_CLK_ENABLE

+#define __SPI5_CLK_DISABLE              __HAL_RCC_SPI5_CLK_DISABLE

+#define __SPI5_FORCE_RESET          __HAL_RCC_SPI5_FORCE_RESET

+#define __SPI5_RELEASE_RESET          __HAL_RCC_SPI5_RELEASE_RESET

+#define __SPI5_CLK_SLEEP_ENABLE          __HAL_RCC_SPI5_CLK_SLEEP_ENABLE

+#define __SPI5_CLK_SLEEP_DISABLE  __HAL_RCC_SPI5_CLK_SLEEP_DISABLE

+#define __SPI6_CLK_ENABLE          __HAL_RCC_SPI6_CLK_ENABLE

+#define __SPI6_CLK_DISABLE          __HAL_RCC_SPI6_CLK_DISABLE

+#define __SPI6_FORCE_RESET          __HAL_RCC_SPI6_FORCE_RESET

+#define __SPI6_RELEASE_RESET         __HAL_RCC_SPI6_RELEASE_RESET

+#define __SPI6_CLK_SLEEP_ENABLE          __HAL_RCC_SPI6_CLK_SLEEP_ENABLE

+#define __SPI6_CLK_SLEEP_DISABLE  __HAL_RCC_SPI6_CLK_SLEEP_DISABLE

+#define __LTDC_CLK_ENABLE          __HAL_RCC_LTDC_CLK_ENABLE

+#define __LTDC_CLK_DISABLE          __HAL_RCC_LTDC_CLK_DISABLE

+#define __LTDC_FORCE_RESET          __HAL_RCC_LTDC_FORCE_RESET

+#define __LTDC_RELEASE_RESET          __HAL_RCC_LTDC_RELEASE_RESET

+#define __LTDC_CLK_SLEEP_ENABLE          __HAL_RCC_LTDC_CLK_SLEEP_ENABLE

+#define __ETHMAC_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE

+#define __ETHMAC_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE

+#define __ETHMACTX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE

+#define __ETHMACTX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE

+#define __ETHMACRX_CLK_SLEEP_ENABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE

+#define __ETHMACRX_CLK_SLEEP_DISABLE  __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE

+#define __TIM12_CLK_SLEEP_ENABLE  __HAL_RCC_TIM12_CLK_SLEEP_ENABLE

+#define __TIM12_CLK_SLEEP_DISABLE  __HAL_RCC_TIM12_CLK_SLEEP_DISABLE

+#define __TIM13_CLK_SLEEP_ENABLE  __HAL_RCC_TIM13_CLK_SLEEP_ENABLE

+#define __TIM13_CLK_SLEEP_DISABLE  __HAL_RCC_TIM13_CLK_SLEEP_DISABLE

+#define __TIM14_CLK_SLEEP_ENABLE  __HAL_RCC_TIM14_CLK_SLEEP_ENABLE

+#define __TIM14_CLK_SLEEP_DISABLE  __HAL_RCC_TIM14_CLK_SLEEP_DISABLE

+#define __BKPSRAM_CLK_ENABLE          __HAL_RCC_BKPSRAM_CLK_ENABLE

+#define __BKPSRAM_CLK_DISABLE          __HAL_RCC_BKPSRAM_CLK_DISABLE

+#define __BKPSRAM_CLK_SLEEP_ENABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE

+#define __BKPSRAM_CLK_SLEEP_DISABLE  __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE

+#define __CCMDATARAMEN_CLK_ENABLE  __HAL_RCC_CCMDATARAMEN_CLK_ENABLE

+#define __CCMDATARAMEN_CLK_DISABLE  __HAL_RCC_CCMDATARAMEN_CLK_DISABLE

+#define __USART6_CLK_ENABLE          __HAL_RCC_USART6_CLK_ENABLE

+#define __USART6_CLK_DISABLE          __HAL_RCC_USART6_CLK_DISABLE

+#define __USART6_FORCE_RESET        __HAL_RCC_USART6_FORCE_RESET

+#define __USART6_RELEASE_RESET        __HAL_RCC_USART6_RELEASE_RESET

+#define __USART6_CLK_SLEEP_ENABLE  __HAL_RCC_USART6_CLK_SLEEP_ENABLE

+#define __USART6_CLK_SLEEP_DISABLE  __HAL_RCC_USART6_CLK_SLEEP_DISABLE

+#define __SPI4_CLK_ENABLE          __HAL_RCC_SPI4_CLK_ENABLE

+#define __SPI4_CLK_DISABLE          __HAL_RCC_SPI4_CLK_DISABLE

+#define __SPI4_FORCE_RESET          __HAL_RCC_SPI4_FORCE_RESET

+#define __SPI4_RELEASE_RESET        __HAL_RCC_SPI4_RELEASE_RESET

+#define __SPI4_CLK_SLEEP_ENABLE   __HAL_RCC_SPI4_CLK_SLEEP_ENABLE

+#define __SPI4_CLK_SLEEP_DISABLE  __HAL_RCC_SPI4_CLK_SLEEP_DISABLE

+#define __GPIOI_CLK_ENABLE          __HAL_RCC_GPIOI_CLK_ENABLE

+#define __GPIOI_CLK_DISABLE          __HAL_RCC_GPIOI_CLK_DISABLE

+#define __GPIOI_FORCE_RESET          __HAL_RCC_GPIOI_FORCE_RESET

+#define __GPIOI_RELEASE_RESET          __HAL_RCC_GPIOI_RELEASE_RESET

+#define __GPIOI_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE

+#define __GPIOI_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE

+#define __GPIOJ_CLK_ENABLE          __HAL_RCC_GPIOJ_CLK_ENABLE

+#define __GPIOJ_CLK_DISABLE          __HAL_RCC_GPIOJ_CLK_DISABLE

+#define __GPIOJ_FORCE_RESET         __HAL_RCC_GPIOJ_FORCE_RESET

+#define __GPIOJ_RELEASE_RESET          __HAL_RCC_GPIOJ_RELEASE_RESET

+#define __GPIOJ_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE

+#define __GPIOJ_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE

+#define __GPIOK_CLK_ENABLE          __HAL_RCC_GPIOK_CLK_ENABLE

+#define __GPIOK_CLK_DISABLE          __HAL_RCC_GPIOK_CLK_DISABLE

+#define __GPIOK_RELEASE_RESET          __HAL_RCC_GPIOK_RELEASE_RESET

+#define __GPIOK_CLK_SLEEP_ENABLE  __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE

+#define __GPIOK_CLK_SLEEP_DISABLE  __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE

+#define __ETH_CLK_ENABLE          __HAL_RCC_ETH_CLK_ENABLE

+#define __ETH_CLK_DISABLE          __HAL_RCC_ETH_CLK_DISABLE

+#define __DCMI_CLK_ENABLE          __HAL_RCC_DCMI_CLK_ENABLE

+#define __DCMI_CLK_DISABLE          __HAL_RCC_DCMI_CLK_DISABLE

+#define __DCMI_FORCE_RESET          __HAL_RCC_DCMI_FORCE_RESET

+#define __DCMI_RELEASE_RESET          __HAL_RCC_DCMI_RELEASE_RESET

+#define __DCMI_CLK_SLEEP_ENABLE   __HAL_RCC_DCMI_CLK_SLEEP_ENABLE

+#define __DCMI_CLK_SLEEP_DISABLE  __HAL_RCC_DCMI_CLK_SLEEP_DISABLE

+#define __UART7_CLK_ENABLE          __HAL_RCC_UART7_CLK_ENABLE

+#define __UART7_CLK_DISABLE          __HAL_RCC_UART7_CLK_DISABLE

+#define __UART7_RELEASE_RESET       __HAL_RCC_UART7_RELEASE_RESET

+#define __UART7_FORCE_RESET       __HAL_RCC_UART7_FORCE_RESET

+#define __UART7_CLK_SLEEP_ENABLE  __HAL_RCC_UART7_CLK_SLEEP_ENABLE

+#define __UART7_CLK_SLEEP_DISABLE  __HAL_RCC_UART7_CLK_SLEEP_DISABLE

+#define __UART8_CLK_ENABLE          __HAL_RCC_UART8_CLK_ENABLE

+#define __UART8_CLK_DISABLE          __HAL_RCC_UART8_CLK_DISABLE

+#define __UART8_FORCE_RESET          __HAL_RCC_UART8_FORCE_RESET

+#define __UART8_RELEASE_RESET          __HAL_RCC_UART8_RELEASE_RESET

+#define __UART8_CLK_SLEEP_ENABLE  __HAL_RCC_UART8_CLK_SLEEP_ENABLE

+#define __UART8_CLK_SLEEP_DISABLE  __HAL_RCC_UART8_CLK_SLEEP_DISABLE

+#define __OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE

+#define __OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE

+#define __OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET

+#define __OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET

+#define __OTGHSULPI_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE

+#define __OTGHSULPI_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE

+#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE

+#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE  __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE

+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED

+#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED

+#define __HAL_RCC_OTGHS_FORCE_RESET          __HAL_RCC_USB_OTG_HS_FORCE_RESET

+#define __HAL_RCC_OTGHS_RELEASE_RESET          __HAL_RCC_USB_OTG_HS_RELEASE_RESET

+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE      __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE

+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE     __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE

+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED  __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED

+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED

+#define __SRAM3_CLK_SLEEP_ENABLE       __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE

+#define __CAN2_CLK_SLEEP_ENABLE        __HAL_RCC_CAN2_CLK_SLEEP_ENABLE

+#define __CAN2_CLK_SLEEP_DISABLE       __HAL_RCC_CAN2_CLK_SLEEP_DISABLE

+#define __DAC_CLK_SLEEP_ENABLE         __HAL_RCC_DAC_CLK_SLEEP_ENABLE

+#define __DAC_CLK_SLEEP_DISABLE        __HAL_RCC_DAC_CLK_SLEEP_DISABLE

+#define __ADC2_CLK_SLEEP_ENABLE        __HAL_RCC_ADC2_CLK_SLEEP_ENABLE

+#define __ADC2_CLK_SLEEP_DISABLE       __HAL_RCC_ADC2_CLK_SLEEP_DISABLE

+#define __ADC3_CLK_SLEEP_ENABLE        __HAL_RCC_ADC3_CLK_SLEEP_ENABLE

+#define __ADC3_CLK_SLEEP_DISABLE       __HAL_RCC_ADC3_CLK_SLEEP_DISABLE

+#define __FSMC_FORCE_RESET             __HAL_RCC_FSMC_FORCE_RESET

+#define __FSMC_RELEASE_RESET           __HAL_RCC_FSMC_RELEASE_RESET

+#define __FSMC_CLK_SLEEP_ENABLE        __HAL_RCC_FSMC_CLK_SLEEP_ENABLE

+#define __FSMC_CLK_SLEEP_DISABLE       __HAL_RCC_FSMC_CLK_SLEEP_DISABLE

+#define __SDIO_FORCE_RESET             __HAL_RCC_SDIO_FORCE_RESET

+#define __SDIO_RELEASE_RESET           __HAL_RCC_SDIO_RELEASE_RESET

+#define __SDIO_CLK_SLEEP_DISABLE       __HAL_RCC_SDIO_CLK_SLEEP_DISABLE

+#define __SDIO_CLK_SLEEP_ENABLE        __HAL_RCC_SDIO_CLK_SLEEP_ENABLE

+#define __DMA2D_CLK_ENABLE             __HAL_RCC_DMA2D_CLK_ENABLE

+#define __DMA2D_CLK_DISABLE            __HAL_RCC_DMA2D_CLK_DISABLE

+#define __DMA2D_FORCE_RESET            __HAL_RCC_DMA2D_FORCE_RESET

+#define __DMA2D_RELEASE_RESET          __HAL_RCC_DMA2D_RELEASE_RESET

+#define __DMA2D_CLK_SLEEP_ENABLE       __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE

+#define __DMA2D_CLK_SLEEP_DISABLE      __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE

+

+/* alias define maintained for legacy */

+#define __HAL_RCC_OTGFS_FORCE_RESET    __HAL_RCC_USB_OTG_FS_FORCE_RESET

+#define __HAL_RCC_OTGFS_RELEASE_RESET  __HAL_RCC_USB_OTG_FS_RELEASE_RESET

+

+#define __ADC12_CLK_ENABLE          __HAL_RCC_ADC12_CLK_ENABLE

+#define __ADC12_CLK_DISABLE         __HAL_RCC_ADC12_CLK_DISABLE

+#define __ADC34_CLK_ENABLE          __HAL_RCC_ADC34_CLK_ENABLE

+#define __ADC34_CLK_DISABLE         __HAL_RCC_ADC34_CLK_DISABLE

+#define __DAC2_CLK_ENABLE           __HAL_RCC_DAC2_CLK_ENABLE

+#define __DAC2_CLK_DISABLE          __HAL_RCC_DAC2_CLK_DISABLE

+#define __TIM18_CLK_ENABLE          __HAL_RCC_TIM18_CLK_ENABLE

+#define __TIM18_CLK_DISABLE         __HAL_RCC_TIM18_CLK_DISABLE

+#define __TIM19_CLK_ENABLE          __HAL_RCC_TIM19_CLK_ENABLE

+#define __TIM19_CLK_DISABLE         __HAL_RCC_TIM19_CLK_DISABLE

+#define __TIM20_CLK_ENABLE          __HAL_RCC_TIM20_CLK_ENABLE

+#define __TIM20_CLK_DISABLE         __HAL_RCC_TIM20_CLK_DISABLE

+#define __HRTIM1_CLK_ENABLE         __HAL_RCC_HRTIM1_CLK_ENABLE

+#define __HRTIM1_CLK_DISABLE        __HAL_RCC_HRTIM1_CLK_DISABLE

+#define __SDADC1_CLK_ENABLE         __HAL_RCC_SDADC1_CLK_ENABLE

+#define __SDADC2_CLK_ENABLE         __HAL_RCC_SDADC2_CLK_ENABLE

+#define __SDADC3_CLK_ENABLE         __HAL_RCC_SDADC3_CLK_ENABLE

+#define __SDADC1_CLK_DISABLE        __HAL_RCC_SDADC1_CLK_DISABLE

+#define __SDADC2_CLK_DISABLE        __HAL_RCC_SDADC2_CLK_DISABLE

+#define __SDADC3_CLK_DISABLE        __HAL_RCC_SDADC3_CLK_DISABLE

+

+#define __ADC12_FORCE_RESET         __HAL_RCC_ADC12_FORCE_RESET

+#define __ADC12_RELEASE_RESET       __HAL_RCC_ADC12_RELEASE_RESET

+#define __ADC34_FORCE_RESET         __HAL_RCC_ADC34_FORCE_RESET

+#define __ADC34_RELEASE_RESET       __HAL_RCC_ADC34_RELEASE_RESET

+#define __DAC2_FORCE_RESET          __HAL_RCC_DAC2_FORCE_RESET

+#define __DAC2_RELEASE_RESET        __HAL_RCC_DAC2_RELEASE_RESET

+#define __TIM18_FORCE_RESET         __HAL_RCC_TIM18_FORCE_RESET

+#define __TIM18_RELEASE_RESET       __HAL_RCC_TIM18_RELEASE_RESET

+#define __TIM19_FORCE_RESET         __HAL_RCC_TIM19_FORCE_RESET

+#define __TIM19_RELEASE_RESET       __HAL_RCC_TIM19_RELEASE_RESET

+#define __TIM20_FORCE_RESET         __HAL_RCC_TIM20_FORCE_RESET

+#define __TIM20_RELEASE_RESET       __HAL_RCC_TIM20_RELEASE_RESET

+#define __HRTIM1_FORCE_RESET        __HAL_RCC_HRTIM1_FORCE_RESET

+#define __HRTIM1_RELEASE_RESET      __HAL_RCC_HRTIM1_RELEASE_RESET

+#define __SDADC1_FORCE_RESET        __HAL_RCC_SDADC1_FORCE_RESET

+#define __SDADC2_FORCE_RESET        __HAL_RCC_SDADC2_FORCE_RESET

+#define __SDADC3_FORCE_RESET        __HAL_RCC_SDADC3_FORCE_RESET

+#define __SDADC1_RELEASE_RESET      __HAL_RCC_SDADC1_RELEASE_RESET

+#define __SDADC2_RELEASE_RESET      __HAL_RCC_SDADC2_RELEASE_RESET

+#define __SDADC3_RELEASE_RESET      __HAL_RCC_SDADC3_RELEASE_RESET

+

+#define __ADC1_IS_CLK_ENABLED       __HAL_RCC_ADC1_IS_CLK_ENABLED

+#define __ADC1_IS_CLK_DISABLED      __HAL_RCC_ADC1_IS_CLK_DISABLED

+#define __ADC12_IS_CLK_ENABLED      __HAL_RCC_ADC12_IS_CLK_ENABLED

+#define __ADC12_IS_CLK_DISABLED     __HAL_RCC_ADC12_IS_CLK_DISABLED

+#define __ADC34_IS_CLK_ENABLED      __HAL_RCC_ADC34_IS_CLK_ENABLED

+#define __ADC34_IS_CLK_DISABLED     __HAL_RCC_ADC34_IS_CLK_DISABLED

+#define __CEC_IS_CLK_ENABLED        __HAL_RCC_CEC_IS_CLK_ENABLED

+#define __CEC_IS_CLK_DISABLED       __HAL_RCC_CEC_IS_CLK_DISABLED

+#define __CRC_IS_CLK_ENABLED        __HAL_RCC_CRC_IS_CLK_ENABLED

+#define __CRC_IS_CLK_DISABLED       __HAL_RCC_CRC_IS_CLK_DISABLED

+#define __DAC1_IS_CLK_ENABLED       __HAL_RCC_DAC1_IS_CLK_ENABLED

+#define __DAC1_IS_CLK_DISABLED      __HAL_RCC_DAC1_IS_CLK_DISABLED

+#define __DAC2_IS_CLK_ENABLED       __HAL_RCC_DAC2_IS_CLK_ENABLED

+#define __DAC2_IS_CLK_DISABLED      __HAL_RCC_DAC2_IS_CLK_DISABLED

+#define __DMA1_IS_CLK_ENABLED       __HAL_RCC_DMA1_IS_CLK_ENABLED

+#define __DMA1_IS_CLK_DISABLED      __HAL_RCC_DMA1_IS_CLK_DISABLED

+#define __DMA2_IS_CLK_ENABLED       __HAL_RCC_DMA2_IS_CLK_ENABLED

+#define __DMA2_IS_CLK_DISABLED      __HAL_RCC_DMA2_IS_CLK_DISABLED

+#define __FLITF_IS_CLK_ENABLED      __HAL_RCC_FLITF_IS_CLK_ENABLED

+#define __FLITF_IS_CLK_DISABLED     __HAL_RCC_FLITF_IS_CLK_DISABLED

+#define __FMC_IS_CLK_ENABLED        __HAL_RCC_FMC_IS_CLK_ENABLED

+#define __FMC_IS_CLK_DISABLED       __HAL_RCC_FMC_IS_CLK_DISABLED

+#define __GPIOA_IS_CLK_ENABLED      __HAL_RCC_GPIOA_IS_CLK_ENABLED

+#define __GPIOA_IS_CLK_DISABLED     __HAL_RCC_GPIOA_IS_CLK_DISABLED

+#define __GPIOB_IS_CLK_ENABLED      __HAL_RCC_GPIOB_IS_CLK_ENABLED

+#define __GPIOB_IS_CLK_DISABLED     __HAL_RCC_GPIOB_IS_CLK_DISABLED

+#define __GPIOC_IS_CLK_ENABLED      __HAL_RCC_GPIOC_IS_CLK_ENABLED

+#define __GPIOC_IS_CLK_DISABLED     __HAL_RCC_GPIOC_IS_CLK_DISABLED

+#define __GPIOD_IS_CLK_ENABLED      __HAL_RCC_GPIOD_IS_CLK_ENABLED

+#define __GPIOD_IS_CLK_DISABLED     __HAL_RCC_GPIOD_IS_CLK_DISABLED

+#define __GPIOE_IS_CLK_ENABLED      __HAL_RCC_GPIOE_IS_CLK_ENABLED

+#define __GPIOE_IS_CLK_DISABLED     __HAL_RCC_GPIOE_IS_CLK_DISABLED

+#define __GPIOF_IS_CLK_ENABLED      __HAL_RCC_GPIOF_IS_CLK_ENABLED

+#define __GPIOF_IS_CLK_DISABLED     __HAL_RCC_GPIOF_IS_CLK_DISABLED

+#define __GPIOG_IS_CLK_ENABLED      __HAL_RCC_GPIOG_IS_CLK_ENABLED

+#define __GPIOG_IS_CLK_DISABLED     __HAL_RCC_GPIOG_IS_CLK_DISABLED

+#define __GPIOH_IS_CLK_ENABLED      __HAL_RCC_GPIOH_IS_CLK_ENABLED

+#define __GPIOH_IS_CLK_DISABLED     __HAL_RCC_GPIOH_IS_CLK_DISABLED

+#define __HRTIM1_IS_CLK_ENABLED     __HAL_RCC_HRTIM1_IS_CLK_ENABLED

+#define __HRTIM1_IS_CLK_DISABLED    __HAL_RCC_HRTIM1_IS_CLK_DISABLED

+#define __I2C1_IS_CLK_ENABLED       __HAL_RCC_I2C1_IS_CLK_ENABLED

+#define __I2C1_IS_CLK_DISABLED      __HAL_RCC_I2C1_IS_CLK_DISABLED

+#define __I2C2_IS_CLK_ENABLED       __HAL_RCC_I2C2_IS_CLK_ENABLED

+#define __I2C2_IS_CLK_DISABLED      __HAL_RCC_I2C2_IS_CLK_DISABLED

+#define __I2C3_IS_CLK_ENABLED       __HAL_RCC_I2C3_IS_CLK_ENABLED

+#define __I2C3_IS_CLK_DISABLED      __HAL_RCC_I2C3_IS_CLK_DISABLED

+#define __PWR_IS_CLK_ENABLED        __HAL_RCC_PWR_IS_CLK_ENABLED

+#define __PWR_IS_CLK_DISABLED       __HAL_RCC_PWR_IS_CLK_DISABLED

+#define __SYSCFG_IS_CLK_ENABLED     __HAL_RCC_SYSCFG_IS_CLK_ENABLED

+#define __SYSCFG_IS_CLK_DISABLED    __HAL_RCC_SYSCFG_IS_CLK_DISABLED

+#define __SPI1_IS_CLK_ENABLED       __HAL_RCC_SPI1_IS_CLK_ENABLED

+#define __SPI1_IS_CLK_DISABLED      __HAL_RCC_SPI1_IS_CLK_DISABLED

+#define __SPI2_IS_CLK_ENABLED       __HAL_RCC_SPI2_IS_CLK_ENABLED

+#define __SPI2_IS_CLK_DISABLED      __HAL_RCC_SPI2_IS_CLK_DISABLED

+#define __SPI3_IS_CLK_ENABLED       __HAL_RCC_SPI3_IS_CLK_ENABLED

+#define __SPI3_IS_CLK_DISABLED      __HAL_RCC_SPI3_IS_CLK_DISABLED

+#define __SPI4_IS_CLK_ENABLED       __HAL_RCC_SPI4_IS_CLK_ENABLED

+#define __SPI4_IS_CLK_DISABLED      __HAL_RCC_SPI4_IS_CLK_DISABLED

+#define __SDADC1_IS_CLK_ENABLED     __HAL_RCC_SDADC1_IS_CLK_ENABLED

+#define __SDADC1_IS_CLK_DISABLED    __HAL_RCC_SDADC1_IS_CLK_DISABLED

+#define __SDADC2_IS_CLK_ENABLED     __HAL_RCC_SDADC2_IS_CLK_ENABLED

+#define __SDADC2_IS_CLK_DISABLED    __HAL_RCC_SDADC2_IS_CLK_DISABLED

+#define __SDADC3_IS_CLK_ENABLED     __HAL_RCC_SDADC3_IS_CLK_ENABLED

+#define __SDADC3_IS_CLK_DISABLED    __HAL_RCC_SDADC3_IS_CLK_DISABLED

+#define __SRAM_IS_CLK_ENABLED       __HAL_RCC_SRAM_IS_CLK_ENABLED

+#define __SRAM_IS_CLK_DISABLED      __HAL_RCC_SRAM_IS_CLK_DISABLED

+#define __TIM1_IS_CLK_ENABLED       __HAL_RCC_TIM1_IS_CLK_ENABLED

+#define __TIM1_IS_CLK_DISABLED      __HAL_RCC_TIM1_IS_CLK_DISABLED

+#define __TIM2_IS_CLK_ENABLED       __HAL_RCC_TIM2_IS_CLK_ENABLED

+#define __TIM2_IS_CLK_DISABLED      __HAL_RCC_TIM2_IS_CLK_DISABLED

+#define __TIM3_IS_CLK_ENABLED       __HAL_RCC_TIM3_IS_CLK_ENABLED

+#define __TIM3_IS_CLK_DISABLED      __HAL_RCC_TIM3_IS_CLK_DISABLED

+#define __TIM4_IS_CLK_ENABLED       __HAL_RCC_TIM4_IS_CLK_ENABLED

+#define __TIM4_IS_CLK_DISABLED      __HAL_RCC_TIM4_IS_CLK_DISABLED

+#define __TIM5_IS_CLK_ENABLED       __HAL_RCC_TIM5_IS_CLK_ENABLED

+#define __TIM5_IS_CLK_DISABLED      __HAL_RCC_TIM5_IS_CLK_DISABLED

+#define __TIM6_IS_CLK_ENABLED       __HAL_RCC_TIM6_IS_CLK_ENABLED

+#define __TIM6_IS_CLK_DISABLED      __HAL_RCC_TIM6_IS_CLK_DISABLED

+#define __TIM7_IS_CLK_ENABLED       __HAL_RCC_TIM7_IS_CLK_ENABLED

+#define __TIM7_IS_CLK_DISABLED      __HAL_RCC_TIM7_IS_CLK_DISABLED

+#define __TIM8_IS_CLK_ENABLED       __HAL_RCC_TIM8_IS_CLK_ENABLED

+#define __TIM8_IS_CLK_DISABLED      __HAL_RCC_TIM8_IS_CLK_DISABLED

+#define __TIM12_IS_CLK_ENABLED      __HAL_RCC_TIM12_IS_CLK_ENABLED

+#define __TIM12_IS_CLK_DISABLED     __HAL_RCC_TIM12_IS_CLK_DISABLED

+#define __TIM13_IS_CLK_ENABLED      __HAL_RCC_TIM13_IS_CLK_ENABLED

+#define __TIM13_IS_CLK_DISABLED     __HAL_RCC_TIM13_IS_CLK_DISABLED

+#define __TIM14_IS_CLK_ENABLED      __HAL_RCC_TIM14_IS_CLK_ENABLED

+#define __TIM14_IS_CLK_DISABLED     __HAL_RCC_TIM14_IS_CLK_DISABLED

+#define __TIM15_IS_CLK_ENABLED      __HAL_RCC_TIM15_IS_CLK_ENABLED

+#define __TIM15_IS_CLK_DISABLED     __HAL_RCC_TIM15_IS_CLK_DISABLED

+#define __TIM16_IS_CLK_ENABLED      __HAL_RCC_TIM16_IS_CLK_ENABLED

+#define __TIM16_IS_CLK_DISABLED     __HAL_RCC_TIM16_IS_CLK_DISABLED

+#define __TIM17_IS_CLK_ENABLED      __HAL_RCC_TIM17_IS_CLK_ENABLED

+#define __TIM17_IS_CLK_DISABLED     __HAL_RCC_TIM17_IS_CLK_DISABLED

+#define __TIM18_IS_CLK_ENABLED      __HAL_RCC_TIM18_IS_CLK_ENABLED

+#define __TIM18_IS_CLK_DISABLED     __HAL_RCC_TIM18_IS_CLK_DISABLED

+#define __TIM19_IS_CLK_ENABLED      __HAL_RCC_TIM19_IS_CLK_ENABLED

+#define __TIM19_IS_CLK_DISABLED     __HAL_RCC_TIM19_IS_CLK_DISABLED

+#define __TIM20_IS_CLK_ENABLED      __HAL_RCC_TIM20_IS_CLK_ENABLED

+#define __TIM20_IS_CLK_DISABLED     __HAL_RCC_TIM20_IS_CLK_DISABLED

+#define __TSC_IS_CLK_ENABLED        __HAL_RCC_TSC_IS_CLK_ENABLED

+#define __TSC_IS_CLK_DISABLED       __HAL_RCC_TSC_IS_CLK_DISABLED

+#define __UART4_IS_CLK_ENABLED      __HAL_RCC_UART4_IS_CLK_ENABLED

+#define __UART4_IS_CLK_DISABLED     __HAL_RCC_UART4_IS_CLK_DISABLED

+#define __UART5_IS_CLK_ENABLED      __HAL_RCC_UART5_IS_CLK_ENABLED

+#define __UART5_IS_CLK_DISABLED     __HAL_RCC_UART5_IS_CLK_DISABLED

+#define __USART1_IS_CLK_ENABLED     __HAL_RCC_USART1_IS_CLK_ENABLED

+#define __USART1_IS_CLK_DISABLED    __HAL_RCC_USART1_IS_CLK_DISABLED

+#define __USART2_IS_CLK_ENABLED     __HAL_RCC_USART2_IS_CLK_ENABLED

+#define __USART2_IS_CLK_DISABLED    __HAL_RCC_USART2_IS_CLK_DISABLED

+#define __USART3_IS_CLK_ENABLED     __HAL_RCC_USART3_IS_CLK_ENABLED

+#define __USART3_IS_CLK_DISABLED    __HAL_RCC_USART3_IS_CLK_DISABLED

+#define __USB_IS_CLK_ENABLED        __HAL_RCC_USB_IS_CLK_ENABLED

+#define __USB_IS_CLK_DISABLED       __HAL_RCC_USB_IS_CLK_DISABLED

+#define __WWDG_IS_CLK_ENABLED       __HAL_RCC_WWDG_IS_CLK_ENABLED

+#define __WWDG_IS_CLK_DISABLED      __HAL_RCC_WWDG_IS_CLK_DISABLED

+

+#if defined(STM32L1)

+#define __HAL_RCC_CRYP_CLK_DISABLE         __HAL_RCC_AES_CLK_DISABLE

+#define __HAL_RCC_CRYP_CLK_ENABLE          __HAL_RCC_AES_CLK_ENABLE

+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE   __HAL_RCC_AES_CLK_SLEEP_DISABLE

+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE    __HAL_RCC_AES_CLK_SLEEP_ENABLE

+#define __HAL_RCC_CRYP_FORCE_RESET         __HAL_RCC_AES_FORCE_RESET

+#define __HAL_RCC_CRYP_RELEASE_RESET       __HAL_RCC_AES_RELEASE_RESET

+#endif /* STM32L1 */

+

+#if defined(STM32F4)

+#define __HAL_RCC_SDMMC1_FORCE_RESET       __HAL_RCC_SDIO_FORCE_RESET

+#define __HAL_RCC_SDMMC1_RELEASE_RESET     __HAL_RCC_SDIO_RELEASE_RESET

+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE  __HAL_RCC_SDIO_CLK_SLEEP_ENABLE

+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE

+#define __HAL_RCC_SDMMC1_CLK_ENABLE        __HAL_RCC_SDIO_CLK_ENABLE

+#define __HAL_RCC_SDMMC1_CLK_DISABLE       __HAL_RCC_SDIO_CLK_DISABLE

+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED    __HAL_RCC_SDIO_IS_CLK_ENABLED

+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED   __HAL_RCC_SDIO_IS_CLK_DISABLED

+#define Sdmmc1ClockSelection               SdioClockSelection

+#define RCC_PERIPHCLK_SDMMC1               RCC_PERIPHCLK_SDIO

+#define RCC_SDMMC1CLKSOURCE_CLK48          RCC_SDIOCLKSOURCE_CK48

+#define RCC_SDMMC1CLKSOURCE_SYSCLK         RCC_SDIOCLKSOURCE_SYSCLK

+#define __HAL_RCC_SDMMC1_CONFIG            __HAL_RCC_SDIO_CONFIG

+#define __HAL_RCC_GET_SDMMC1_SOURCE        __HAL_RCC_GET_SDIO_SOURCE

+#endif

+

+#if defined(STM32F7) || defined(STM32L4)

+#define __HAL_RCC_SDIO_FORCE_RESET         __HAL_RCC_SDMMC1_FORCE_RESET

+#define __HAL_RCC_SDIO_RELEASE_RESET       __HAL_RCC_SDMMC1_RELEASE_RESET

+#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE    __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE

+#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE   __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE

+#define __HAL_RCC_SDIO_CLK_ENABLE          __HAL_RCC_SDMMC1_CLK_ENABLE

+#define __HAL_RCC_SDIO_CLK_DISABLE         __HAL_RCC_SDMMC1_CLK_DISABLE

+#define __HAL_RCC_SDIO_IS_CLK_ENABLED      __HAL_RCC_SDMMC1_IS_CLK_ENABLED

+#define __HAL_RCC_SDIO_IS_CLK_DISABLED     __HAL_RCC_SDMMC1_IS_CLK_DISABLED

+#define SdioClockSelection                 Sdmmc1ClockSelection

+#define RCC_PERIPHCLK_SDIO                 RCC_PERIPHCLK_SDMMC1

+#define __HAL_RCC_SDIO_CONFIG              __HAL_RCC_SDMMC1_CONFIG

+#define __HAL_RCC_GET_SDIO_SOURCE          __HAL_RCC_GET_SDMMC1_SOURCE

+#endif

+

+#if defined(STM32F7)

+#define RCC_SDIOCLKSOURCE_CLK48             RCC_SDMMC1CLKSOURCE_CLK48

+#define RCC_SDIOCLKSOURCE_SYSCLK           RCC_SDMMC1CLKSOURCE_SYSCLK

+#endif

+

+#if defined(STM32H7)

+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE()              __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()

+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE()         __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()

+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE()             __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()

+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE()        __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()

+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET()             __HAL_RCC_USB1_OTG_HS_FORCE_RESET()

+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET()           __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()

+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE()        __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()

+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE()   __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()

+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE()       __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()

+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE()  __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()

+

+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE()             __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()

+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE()        __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()

+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE()            __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()

+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE()       __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()

+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET()            __HAL_RCC_USB2_OTG_FS_FORCE_RESET()

+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET()          __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()

+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE()       __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()

+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE()  __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()

+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE()      __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()

+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()

+#endif

+

+#define __HAL_RCC_I2SCLK            __HAL_RCC_I2S_CONFIG

+#define __HAL_RCC_I2SCLK_CONFIG     __HAL_RCC_I2S_CONFIG

+

+#define __RCC_PLLSRC                RCC_GET_PLL_OSCSOURCE

+

+#define IS_RCC_MSIRANGE             IS_RCC_MSI_CLOCK_RANGE

+#define IS_RCC_RTCCLK_SOURCE        IS_RCC_RTCCLKSOURCE

+#define IS_RCC_SYSCLK_DIV           IS_RCC_HCLK

+#define IS_RCC_HCLK_DIV             IS_RCC_PCLK

+#define IS_RCC_PERIPHCLK            IS_RCC_PERIPHCLOCK

+

+#define RCC_IT_HSI14                RCC_IT_HSI14RDY

+

+#define RCC_IT_CSSLSE               RCC_IT_LSECSS

+#define RCC_IT_CSSHSE               RCC_IT_CSS

+

+#define RCC_PLLMUL_3                RCC_PLL_MUL3

+#define RCC_PLLMUL_4                RCC_PLL_MUL4

+#define RCC_PLLMUL_6                RCC_PLL_MUL6

+#define RCC_PLLMUL_8                RCC_PLL_MUL8

+#define RCC_PLLMUL_12               RCC_PLL_MUL12

+#define RCC_PLLMUL_16               RCC_PLL_MUL16

+#define RCC_PLLMUL_24               RCC_PLL_MUL24

+#define RCC_PLLMUL_32               RCC_PLL_MUL32

+#define RCC_PLLMUL_48               RCC_PLL_MUL48

+

+#define RCC_PLLDIV_2                RCC_PLL_DIV2

+#define RCC_PLLDIV_3                RCC_PLL_DIV3

+#define RCC_PLLDIV_4                RCC_PLL_DIV4

+

+#define IS_RCC_MCOSOURCE            IS_RCC_MCO1SOURCE

+#define __HAL_RCC_MCO_CONFIG        __HAL_RCC_MCO1_CONFIG

+#define RCC_MCO_NODIV               RCC_MCODIV_1

+#define RCC_MCO_DIV1                RCC_MCODIV_1

+#define RCC_MCO_DIV2                RCC_MCODIV_2

+#define RCC_MCO_DIV4                RCC_MCODIV_4

+#define RCC_MCO_DIV8                RCC_MCODIV_8

+#define RCC_MCO_DIV16               RCC_MCODIV_16

+#define RCC_MCO_DIV32               RCC_MCODIV_32

+#define RCC_MCO_DIV64               RCC_MCODIV_64

+#define RCC_MCO_DIV128              RCC_MCODIV_128

+#define RCC_MCOSOURCE_NONE          RCC_MCO1SOURCE_NOCLOCK

+#define RCC_MCOSOURCE_LSI           RCC_MCO1SOURCE_LSI

+#define RCC_MCOSOURCE_LSE           RCC_MCO1SOURCE_LSE

+#define RCC_MCOSOURCE_SYSCLK        RCC_MCO1SOURCE_SYSCLK

+#define RCC_MCOSOURCE_HSI           RCC_MCO1SOURCE_HSI

+#define RCC_MCOSOURCE_HSI14         RCC_MCO1SOURCE_HSI14

+#define RCC_MCOSOURCE_HSI48         RCC_MCO1SOURCE_HSI48

+#define RCC_MCOSOURCE_HSE           RCC_MCO1SOURCE_HSE

+#define RCC_MCOSOURCE_PLLCLK_DIV1   RCC_MCO1SOURCE_PLLCLK

+#define RCC_MCOSOURCE_PLLCLK_NODIV  RCC_MCO1SOURCE_PLLCLK

+#define RCC_MCOSOURCE_PLLCLK_DIV2   RCC_MCO1SOURCE_PLLCLK_DIV2

+

+#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)

+#define RCC_RTCCLKSOURCE_NO_CLK     RCC_RTCCLKSOURCE_NONE

+#else

+#define RCC_RTCCLKSOURCE_NONE       RCC_RTCCLKSOURCE_NO_CLK

+#endif

+

+#define RCC_USBCLK_PLLSAI1          RCC_USBCLKSOURCE_PLLSAI1

+#define RCC_USBCLK_PLL              RCC_USBCLKSOURCE_PLL

+#define RCC_USBCLK_MSI              RCC_USBCLKSOURCE_MSI

+#define RCC_USBCLKSOURCE_PLLCLK     RCC_USBCLKSOURCE_PLL

+#define RCC_USBPLLCLK_DIV1          RCC_USBCLKSOURCE_PLL

+#define RCC_USBPLLCLK_DIV1_5        RCC_USBCLKSOURCE_PLL_DIV1_5

+#define RCC_USBPLLCLK_DIV2          RCC_USBCLKSOURCE_PLL_DIV2

+#define RCC_USBPLLCLK_DIV3          RCC_USBCLKSOURCE_PLL_DIV3

+

+#define HSION_BitNumber        RCC_HSION_BIT_NUMBER

+#define HSION_BITNUMBER        RCC_HSION_BIT_NUMBER

+#define HSEON_BitNumber        RCC_HSEON_BIT_NUMBER

+#define HSEON_BITNUMBER        RCC_HSEON_BIT_NUMBER

+#define MSION_BITNUMBER        RCC_MSION_BIT_NUMBER

+#define CSSON_BitNumber        RCC_CSSON_BIT_NUMBER

+#define CSSON_BITNUMBER        RCC_CSSON_BIT_NUMBER

+#define PLLON_BitNumber        RCC_PLLON_BIT_NUMBER

+#define PLLON_BITNUMBER        RCC_PLLON_BIT_NUMBER

+#define PLLI2SON_BitNumber     RCC_PLLI2SON_BIT_NUMBER

+#define I2SSRC_BitNumber       RCC_I2SSRC_BIT_NUMBER

+#define RTCEN_BitNumber        RCC_RTCEN_BIT_NUMBER

+#define RTCEN_BITNUMBER        RCC_RTCEN_BIT_NUMBER

+#define BDRST_BitNumber        RCC_BDRST_BIT_NUMBER

+#define BDRST_BITNUMBER        RCC_BDRST_BIT_NUMBER

+#define RTCRST_BITNUMBER       RCC_RTCRST_BIT_NUMBER

+#define LSION_BitNumber        RCC_LSION_BIT_NUMBER

+#define LSION_BITNUMBER        RCC_LSION_BIT_NUMBER

+#define LSEON_BitNumber        RCC_LSEON_BIT_NUMBER

+#define LSEON_BITNUMBER        RCC_LSEON_BIT_NUMBER

+#define LSEBYP_BITNUMBER       RCC_LSEBYP_BIT_NUMBER

+#define PLLSAION_BitNumber     RCC_PLLSAION_BIT_NUMBER

+#define TIMPRE_BitNumber       RCC_TIMPRE_BIT_NUMBER

+#define RMVF_BitNumber         RCC_RMVF_BIT_NUMBER

+#define RMVF_BITNUMBER         RCC_RMVF_BIT_NUMBER

+#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER

+#define CR_BYTE2_ADDRESS       RCC_CR_BYTE2_ADDRESS

+#define CIR_BYTE1_ADDRESS      RCC_CIR_BYTE1_ADDRESS

+#define CIR_BYTE2_ADDRESS      RCC_CIR_BYTE2_ADDRESS

+#define BDCR_BYTE0_ADDRESS     RCC_BDCR_BYTE0_ADDRESS

+#define DBP_TIMEOUT_VALUE      RCC_DBP_TIMEOUT_VALUE

+#define LSE_TIMEOUT_VALUE      RCC_LSE_TIMEOUT_VALUE

+

+#define CR_HSION_BB            RCC_CR_HSION_BB

+#define CR_CSSON_BB            RCC_CR_CSSON_BB

+#define CR_PLLON_BB            RCC_CR_PLLON_BB

+#define CR_PLLI2SON_BB         RCC_CR_PLLI2SON_BB

+#define CR_MSION_BB            RCC_CR_MSION_BB

+#define CSR_LSION_BB           RCC_CSR_LSION_BB

+#define CSR_LSEON_BB           RCC_CSR_LSEON_BB

+#define CSR_LSEBYP_BB          RCC_CSR_LSEBYP_BB

+#define CSR_RTCEN_BB           RCC_CSR_RTCEN_BB

+#define CSR_RTCRST_BB          RCC_CSR_RTCRST_BB

+#define CFGR_I2SSRC_BB         RCC_CFGR_I2SSRC_BB

+#define BDCR_RTCEN_BB          RCC_BDCR_RTCEN_BB

+#define BDCR_BDRST_BB          RCC_BDCR_BDRST_BB

+#define CR_HSEON_BB            RCC_CR_HSEON_BB

+#define CSR_RMVF_BB            RCC_CSR_RMVF_BB

+#define CR_PLLSAION_BB         RCC_CR_PLLSAION_BB

+#define DCKCFGR_TIMPRE_BB      RCC_DCKCFGR_TIMPRE_BB

+

+#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER     __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE

+#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER    __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE

+#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB        __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE

+#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB       __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE

+#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE         __HAL_RCC_CRS_RELOADVALUE_CALCULATE

+

+#define __HAL_RCC_GET_IT_SOURCE                     __HAL_RCC_GET_IT

+

+#define RCC_CRS_SYNCWARM       RCC_CRS_SYNCWARN

+#define RCC_CRS_TRIMOV         RCC_CRS_TRIMOVF

+

+#define RCC_PERIPHCLK_CK48               RCC_PERIPHCLK_CLK48

+#define RCC_CK48CLKSOURCE_PLLQ           RCC_CLK48CLKSOURCE_PLLQ

+#define RCC_CK48CLKSOURCE_PLLSAIP        RCC_CLK48CLKSOURCE_PLLSAIP

+#define RCC_CK48CLKSOURCE_PLLI2SQ        RCC_CLK48CLKSOURCE_PLLI2SQ

+#define IS_RCC_CK48CLKSOURCE             IS_RCC_CLK48CLKSOURCE

+#define RCC_SDIOCLKSOURCE_CK48           RCC_SDIOCLKSOURCE_CLK48

+

+#define __HAL_RCC_DFSDM_CLK_ENABLE             __HAL_RCC_DFSDM1_CLK_ENABLE

+#define __HAL_RCC_DFSDM_CLK_DISABLE            __HAL_RCC_DFSDM1_CLK_DISABLE

+#define __HAL_RCC_DFSDM_IS_CLK_ENABLED         __HAL_RCC_DFSDM1_IS_CLK_ENABLED

+#define __HAL_RCC_DFSDM_IS_CLK_DISABLED        __HAL_RCC_DFSDM1_IS_CLK_DISABLED

+#define __HAL_RCC_DFSDM_FORCE_RESET            __HAL_RCC_DFSDM1_FORCE_RESET

+#define __HAL_RCC_DFSDM_RELEASE_RESET          __HAL_RCC_DFSDM1_RELEASE_RESET

+#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE       __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE

+#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE      __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE

+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED   __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED

+#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED  __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED

+#define DfsdmClockSelection         Dfsdm1ClockSelection

+#define RCC_PERIPHCLK_DFSDM         RCC_PERIPHCLK_DFSDM1

+#define RCC_DFSDMCLKSOURCE_PCLK     RCC_DFSDM1CLKSOURCE_PCLK2

+#define RCC_DFSDMCLKSOURCE_SYSCLK   RCC_DFSDM1CLKSOURCE_SYSCLK

+#define __HAL_RCC_DFSDM_CONFIG      __HAL_RCC_DFSDM1_CONFIG

+#define __HAL_RCC_GET_DFSDM_SOURCE  __HAL_RCC_GET_DFSDM1_SOURCE

+#define RCC_DFSDM1CLKSOURCE_PCLK    RCC_DFSDM1CLKSOURCE_PCLK2

+#define RCC_SWPMI1CLKSOURCE_PCLK    RCC_SWPMI1CLKSOURCE_PCLK1

+#define RCC_LPTIM1CLKSOURCE_PCLK    RCC_LPTIM1CLKSOURCE_PCLK1

+#define RCC_LPTIM2CLKSOURCE_PCLK    RCC_LPTIM2CLKSOURCE_PCLK1

+

+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM1AUDIOCLKSOURCE_I2S1

+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM1AUDIOCLKSOURCE_I2S2

+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM2AUDIOCLKSOURCE_I2S1

+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM2AUDIOCLKSOURCE_I2S2

+#define RCC_DFSDM1CLKSOURCE_APB2            RCC_DFSDM1CLKSOURCE_PCLK2

+#define RCC_DFSDM2CLKSOURCE_APB2            RCC_DFSDM2CLKSOURCE_PCLK2

+#define RCC_FMPI2C1CLKSOURCE_APB            RCC_FMPI2C1CLKSOURCE_PCLK1

+

+/**

+  * @}

+  */

+

+/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose

+  * @{

+  */

+#define  HAL_RNG_ReadyCallback(__HANDLE__)  HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)

+

+/**

+  * @}

+  */

+

+/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose

+  * @{

+  */

+#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4)

+#else

+#define __HAL_RTC_CLEAR_FLAG                      __HAL_RTC_EXTI_CLEAR_FLAG

+#endif

+#define __HAL_RTC_DISABLE_IT                      __HAL_RTC_EXTI_DISABLE_IT

+#define __HAL_RTC_ENABLE_IT                       __HAL_RTC_EXTI_ENABLE_IT

+

+#if defined (STM32F1)

+#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()

+

+#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_ENABLE_IT()

+

+#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT)  __HAL_RTC_ALARM_EXTI_DISABLE_IT()

+

+#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT)    __HAL_RTC_ALARM_EXTI_GET_FLAG()

+

+#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT)   __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()

+#else

+#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \

+                                                   (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \

+                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()))

+#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__)   (((__EXTI_LINE__)  == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \

+                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \

+                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()))

+#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__)  (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \

+                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \

+                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()))

+#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__)    (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \

+                                                  (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \

+                                                      __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()))

+#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__)   (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \

+                                                      (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() :  \

+                                                          __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))

+#endif   /* STM32F1 */

+

+#define IS_ALARM                                  IS_RTC_ALARM

+#define IS_ALARM_MASK                             IS_RTC_ALARM_MASK

+#define IS_TAMPER                                 IS_RTC_TAMPER

+#define IS_TAMPER_ERASE_MODE                      IS_RTC_TAMPER_ERASE_MODE

+#define IS_TAMPER_FILTER                          IS_RTC_TAMPER_FILTER

+#define IS_TAMPER_INTERRUPT                       IS_RTC_TAMPER_INTERRUPT

+#define IS_TAMPER_MASKFLAG_STATE                  IS_RTC_TAMPER_MASKFLAG_STATE

+#define IS_TAMPER_PRECHARGE_DURATION              IS_RTC_TAMPER_PRECHARGE_DURATION

+#define IS_TAMPER_PULLUP_STATE                    IS_RTC_TAMPER_PULLUP_STATE

+#define IS_TAMPER_SAMPLING_FREQ                   IS_RTC_TAMPER_SAMPLING_FREQ

+#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION     IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION

+#define IS_TAMPER_TRIGGER                         IS_RTC_TAMPER_TRIGGER

+#define IS_WAKEUP_CLOCK                           IS_RTC_WAKEUP_CLOCK

+#define IS_WAKEUP_COUNTER                         IS_RTC_WAKEUP_COUNTER

+

+#define __RTC_WRITEPROTECTION_ENABLE  __HAL_RTC_WRITEPROTECTION_ENABLE

+#define __RTC_WRITEPROTECTION_DISABLE  __HAL_RTC_WRITEPROTECTION_DISABLE

+

+/**

+  * @}

+  */

+

+/** @defgroup HAL_SD_Aliased_Macros HAL SD Aliased Macros maintained for legacy purpose

+  * @{

+  */

+

+#define SD_OCR_CID_CSD_OVERWRIETE   SD_OCR_CID_CSD_OVERWRITE

+#define SD_CMD_SD_APP_STAUS         SD_CMD_SD_APP_STATUS

+

+#if defined(STM32F4) || defined(STM32F2)

+#define  SD_SDMMC_DISABLED          SD_SDIO_DISABLED

+#define  SD_SDMMC_FUNCTION_BUSY     SD_SDIO_FUNCTION_BUSY

+#define  SD_SDMMC_FUNCTION_FAILED   SD_SDIO_FUNCTION_FAILED

+#define  SD_SDMMC_UNKNOWN_FUNCTION  SD_SDIO_UNKNOWN_FUNCTION

+#define  SD_CMD_SDMMC_SEN_OP_COND   SD_CMD_SDIO_SEN_OP_COND

+#define  SD_CMD_SDMMC_RW_DIRECT     SD_CMD_SDIO_RW_DIRECT

+#define  SD_CMD_SDMMC_RW_EXTENDED   SD_CMD_SDIO_RW_EXTENDED

+#define  __HAL_SD_SDMMC_ENABLE      __HAL_SD_SDIO_ENABLE

+#define  __HAL_SD_SDMMC_DISABLE     __HAL_SD_SDIO_DISABLE

+#define  __HAL_SD_SDMMC_DMA_ENABLE  __HAL_SD_SDIO_DMA_ENABLE

+#define  __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL

+#define  __HAL_SD_SDMMC_ENABLE_IT   __HAL_SD_SDIO_ENABLE_IT

+#define  __HAL_SD_SDMMC_DISABLE_IT  __HAL_SD_SDIO_DISABLE_IT

+#define  __HAL_SD_SDMMC_GET_FLAG    __HAL_SD_SDIO_GET_FLAG

+#define  __HAL_SD_SDMMC_CLEAR_FLAG  __HAL_SD_SDIO_CLEAR_FLAG

+#define  __HAL_SD_SDMMC_GET_IT      __HAL_SD_SDIO_GET_IT

+#define  __HAL_SD_SDMMC_CLEAR_IT    __HAL_SD_SDIO_CLEAR_IT

+#define  SDMMC_STATIC_FLAGS         SDIO_STATIC_FLAGS

+#define  SDMMC_CMD0TIMEOUT          SDIO_CMD0TIMEOUT

+#define  SD_SDMMC_SEND_IF_COND      SD_SDIO_SEND_IF_COND

+/* alias CMSIS */

+#define  SDMMC1_IRQn                SDIO_IRQn

+#define  SDMMC1_IRQHandler          SDIO_IRQHandler

+#endif

+

+#if defined(STM32F7) || defined(STM32L4)

+#define  SD_SDIO_DISABLED           SD_SDMMC_DISABLED

+#define  SD_SDIO_FUNCTION_BUSY      SD_SDMMC_FUNCTION_BUSY

+#define  SD_SDIO_FUNCTION_FAILED    SD_SDMMC_FUNCTION_FAILED

+#define  SD_SDIO_UNKNOWN_FUNCTION   SD_SDMMC_UNKNOWN_FUNCTION

+#define  SD_CMD_SDIO_SEN_OP_COND    SD_CMD_SDMMC_SEN_OP_COND

+#define  SD_CMD_SDIO_RW_DIRECT      SD_CMD_SDMMC_RW_DIRECT

+#define  SD_CMD_SDIO_RW_EXTENDED    SD_CMD_SDMMC_RW_EXTENDED

+#define  __HAL_SD_SDIO_ENABLE       __HAL_SD_SDMMC_ENABLE

+#define  __HAL_SD_SDIO_DISABLE      __HAL_SD_SDMMC_DISABLE

+#define  __HAL_SD_SDIO_DMA_ENABLE   __HAL_SD_SDMMC_DMA_ENABLE

+#define  __HAL_SD_SDIO_DMA_DISABL   __HAL_SD_SDMMC_DMA_DISABLE

+#define  __HAL_SD_SDIO_ENABLE_IT    __HAL_SD_SDMMC_ENABLE_IT

+#define  __HAL_SD_SDIO_DISABLE_IT   __HAL_SD_SDMMC_DISABLE_IT

+#define  __HAL_SD_SDIO_GET_FLAG     __HAL_SD_SDMMC_GET_FLAG

+#define  __HAL_SD_SDIO_CLEAR_FLAG   __HAL_SD_SDMMC_CLEAR_FLAG

+#define  __HAL_SD_SDIO_GET_IT       __HAL_SD_SDMMC_GET_IT

+#define  __HAL_SD_SDIO_CLEAR_IT     __HAL_SD_SDMMC_CLEAR_IT

+#define  SDIO_STATIC_FLAGS          SDMMC_STATIC_FLAGS

+#define  SDIO_CMD0TIMEOUT           SDMMC_CMD0TIMEOUT

+#define  SD_SDIO_SEND_IF_COND       SD_SDMMC_SEND_IF_COND

+/* alias CMSIS for compatibilities */

+#define  SDIO_IRQn                  SDMMC1_IRQn

+#define  SDIO_IRQHandler            SDMMC1_IRQHandler

+#endif

+

+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)

+#define  HAL_SD_CardCIDTypedef       HAL_SD_CardCIDTypeDef

+#define  HAL_SD_CardCSDTypedef       HAL_SD_CardCSDTypeDef

+#define  HAL_SD_CardStatusTypedef    HAL_SD_CardStatusTypeDef

+#define  HAL_SD_CardStateTypedef     HAL_SD_CardStateTypeDef

+#endif

+

+#if defined(STM32H7) || defined(STM32L5)

+#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback   HAL_MMCEx_Read_DMADoubleBuf0CpltCallback

+#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback   HAL_MMCEx_Read_DMADoubleBuf1CpltCallback

+#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback  HAL_MMCEx_Write_DMADoubleBuf0CpltCallback

+#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback  HAL_MMCEx_Write_DMADoubleBuf1CpltCallback

+#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback    HAL_SDEx_Read_DMADoubleBuf0CpltCallback

+#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback    HAL_SDEx_Read_DMADoubleBuf1CpltCallback

+#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback   HAL_SDEx_Write_DMADoubleBuf0CpltCallback

+#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback   HAL_SDEx_Write_DMADoubleBuf1CpltCallback

+#define HAL_SD_DriveTransciver_1_8V_Callback          HAL_SD_DriveTransceiver_1_8V_Callback

+#endif

+/**

+  * @}

+  */

+

+/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose

+  * @{

+  */

+

+#define __SMARTCARD_ENABLE_IT           __HAL_SMARTCARD_ENABLE_IT

+#define __SMARTCARD_DISABLE_IT          __HAL_SMARTCARD_DISABLE_IT

+#define __SMARTCARD_ENABLE              __HAL_SMARTCARD_ENABLE

+#define __SMARTCARD_DISABLE             __HAL_SMARTCARD_DISABLE

+#define __SMARTCARD_DMA_REQUEST_ENABLE  __HAL_SMARTCARD_DMA_REQUEST_ENABLE

+#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE

+

+#define __HAL_SMARTCARD_GETCLOCKSOURCE  SMARTCARD_GETCLOCKSOURCE

+#define __SMARTCARD_GETCLOCKSOURCE      SMARTCARD_GETCLOCKSOURCE

+

+#define IS_SMARTCARD_ONEBIT_SAMPLING    IS_SMARTCARD_ONE_BIT_SAMPLE

+

+/**

+  * @}

+  */

+

+/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose

+  * @{

+  */

+#define __HAL_SMBUS_RESET_CR1           SMBUS_RESET_CR1

+#define __HAL_SMBUS_RESET_CR2           SMBUS_RESET_CR2

+#define __HAL_SMBUS_GENERATE_START      SMBUS_GENERATE_START

+#define __HAL_SMBUS_GET_ADDR_MATCH      SMBUS_GET_ADDR_MATCH

+#define __HAL_SMBUS_GET_DIR             SMBUS_GET_DIR

+#define __HAL_SMBUS_GET_STOP_MODE       SMBUS_GET_STOP_MODE

+#define __HAL_SMBUS_GET_PEC_MODE        SMBUS_GET_PEC_MODE

+#define __HAL_SMBUS_GET_ALERT_ENABLED   SMBUS_GET_ALERT_ENABLED

+/**

+  * @}

+  */

+

+/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose

+  * @{

+  */

+

+#define __HAL_SPI_1LINE_TX              SPI_1LINE_TX

+#define __HAL_SPI_1LINE_RX              SPI_1LINE_RX

+#define __HAL_SPI_RESET_CRC             SPI_RESET_CRC

+

+/**

+  * @}

+  */

+

+/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose

+  * @{

+  */

+

+#define __HAL_UART_GETCLOCKSOURCE       UART_GETCLOCKSOURCE

+#define __HAL_UART_MASK_COMPUTATION     UART_MASK_COMPUTATION

+#define __UART_GETCLOCKSOURCE           UART_GETCLOCKSOURCE

+#define __UART_MASK_COMPUTATION         UART_MASK_COMPUTATION

+

+#define IS_UART_WAKEUPMETHODE           IS_UART_WAKEUPMETHOD

+

+#define IS_UART_ONEBIT_SAMPLE           IS_UART_ONE_BIT_SAMPLE

+#define IS_UART_ONEBIT_SAMPLING         IS_UART_ONE_BIT_SAMPLE

+

+/**

+  * @}

+  */

+

+

+/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose

+  * @{

+  */

+

+#define __USART_ENABLE_IT               __HAL_USART_ENABLE_IT

+#define __USART_DISABLE_IT              __HAL_USART_DISABLE_IT

+#define __USART_ENABLE                  __HAL_USART_ENABLE

+#define __USART_DISABLE                 __HAL_USART_DISABLE

+

+#define __HAL_USART_GETCLOCKSOURCE      USART_GETCLOCKSOURCE

+#define __USART_GETCLOCKSOURCE          USART_GETCLOCKSOURCE

+

+/**

+  * @}

+  */

+

+/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose

+  * @{

+  */

+#define USB_EXTI_LINE_WAKEUP                               USB_WAKEUP_EXTI_LINE

+

+#define USB_FS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE

+#define USB_FS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE

+#define USB_FS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE

+#define USB_FS_EXTI_LINE_WAKEUP                            USB_OTG_FS_WAKEUP_EXTI_LINE

+

+#define USB_HS_EXTI_TRIGGER_RISING_EDGE                    USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE

+#define USB_HS_EXTI_TRIGGER_FALLING_EDGE                   USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE

+#define USB_HS_EXTI_TRIGGER_BOTH_EDGE                      USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE

+#define USB_HS_EXTI_LINE_WAKEUP                            USB_OTG_HS_WAKEUP_EXTI_LINE

+

+#define __HAL_USB_EXTI_ENABLE_IT                           __HAL_USB_WAKEUP_EXTI_ENABLE_IT

+#define __HAL_USB_EXTI_DISABLE_IT                          __HAL_USB_WAKEUP_EXTI_DISABLE_IT

+#define __HAL_USB_EXTI_GET_FLAG                            __HAL_USB_WAKEUP_EXTI_GET_FLAG

+#define __HAL_USB_EXTI_CLEAR_FLAG                          __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG

+#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER             __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE

+#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER            __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE

+#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER           __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE

+

+#define __HAL_USB_FS_EXTI_ENABLE_IT                        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT

+#define __HAL_USB_FS_EXTI_DISABLE_IT                       __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT

+#define __HAL_USB_FS_EXTI_GET_FLAG                         __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG

+#define __HAL_USB_FS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG

+#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE

+#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE

+#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE

+#define __HAL_USB_FS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT

+

+#define __HAL_USB_HS_EXTI_ENABLE_IT                        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT

+#define __HAL_USB_HS_EXTI_DISABLE_IT                       __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT

+#define __HAL_USB_HS_EXTI_GET_FLAG                         __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG

+#define __HAL_USB_HS_EXTI_CLEAR_FLAG                       __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG

+#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER          __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE

+#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER         __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE

+#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER        __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE

+#define __HAL_USB_HS_EXTI_GENERATE_SWIT                    __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT

+

+#define HAL_PCD_ActiveRemoteWakeup                         HAL_PCD_ActivateRemoteWakeup

+#define HAL_PCD_DeActiveRemoteWakeup                       HAL_PCD_DeActivateRemoteWakeup

+

+#define HAL_PCD_SetTxFiFo                                  HAL_PCDEx_SetTxFiFo

+#define HAL_PCD_SetRxFiFo                                  HAL_PCDEx_SetRxFiFo

+/**

+  * @}

+  */

+

+/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose

+  * @{

+  */

+#define __HAL_TIM_SetICPrescalerValue   TIM_SET_ICPRESCALERVALUE

+#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE

+

+#define TIM_GET_ITSTATUS                __HAL_TIM_GET_IT_SOURCE

+#define TIM_GET_CLEAR_IT                __HAL_TIM_CLEAR_IT

+

+#define __HAL_TIM_GET_ITSTATUS          __HAL_TIM_GET_IT_SOURCE

+

+#define __HAL_TIM_DIRECTION_STATUS      __HAL_TIM_IS_TIM_COUNTING_DOWN

+#define __HAL_TIM_PRESCALER             __HAL_TIM_SET_PRESCALER

+#define __HAL_TIM_SetCounter            __HAL_TIM_SET_COUNTER

+#define __HAL_TIM_GetCounter            __HAL_TIM_GET_COUNTER

+#define __HAL_TIM_SetAutoreload         __HAL_TIM_SET_AUTORELOAD

+#define __HAL_TIM_GetAutoreload         __HAL_TIM_GET_AUTORELOAD

+#define __HAL_TIM_SetClockDivision      __HAL_TIM_SET_CLOCKDIVISION

+#define __HAL_TIM_GetClockDivision      __HAL_TIM_GET_CLOCKDIVISION

+#define __HAL_TIM_SetICPrescaler        __HAL_TIM_SET_ICPRESCALER

+#define __HAL_TIM_GetICPrescaler        __HAL_TIM_GET_ICPRESCALER

+#define __HAL_TIM_SetCompare            __HAL_TIM_SET_COMPARE

+#define __HAL_TIM_GetCompare            __HAL_TIM_GET_COMPARE

+

+#define TIM_BREAKINPUTSOURCE_DFSDM  TIM_BREAKINPUTSOURCE_DFSDM1

+/**

+  * @}

+  */

+

+/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose

+  * @{

+  */

+

+#define __HAL_ETH_EXTI_ENABLE_IT                   __HAL_ETH_WAKEUP_EXTI_ENABLE_IT

+#define __HAL_ETH_EXTI_DISABLE_IT                  __HAL_ETH_WAKEUP_EXTI_DISABLE_IT

+#define __HAL_ETH_EXTI_GET_FLAG                    __HAL_ETH_WAKEUP_EXTI_GET_FLAG

+#define __HAL_ETH_EXTI_CLEAR_FLAG                  __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG

+#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER     __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER

+#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER    __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER

+#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER   __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER

+

+#define ETH_PROMISCIOUSMODE_ENABLE   ETH_PROMISCUOUS_MODE_ENABLE

+#define ETH_PROMISCIOUSMODE_DISABLE  ETH_PROMISCUOUS_MODE_DISABLE

+#define IS_ETH_PROMISCIOUS_MODE      IS_ETH_PROMISCUOUS_MODE

+/**

+  * @}

+  */

+

+/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose

+  * @{

+  */

+#define __HAL_LTDC_LAYER LTDC_LAYER

+#define __HAL_LTDC_RELOAD_CONFIG  __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG

+/**

+  * @}

+  */

+

+/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose

+  * @{

+  */

+#define SAI_OUTPUTDRIVE_DISABLED          SAI_OUTPUTDRIVE_DISABLE

+#define SAI_OUTPUTDRIVE_ENABLED           SAI_OUTPUTDRIVE_ENABLE

+#define SAI_MASTERDIVIDER_ENABLED         SAI_MASTERDIVIDER_ENABLE

+#define SAI_MASTERDIVIDER_DISABLED        SAI_MASTERDIVIDER_DISABLE

+#define SAI_STREOMODE                     SAI_STEREOMODE

+#define SAI_FIFOStatus_Empty              SAI_FIFOSTATUS_EMPTY

+#define SAI_FIFOStatus_Less1QuarterFull   SAI_FIFOSTATUS_LESS1QUARTERFULL

+#define SAI_FIFOStatus_1QuarterFull       SAI_FIFOSTATUS_1QUARTERFULL

+#define SAI_FIFOStatus_HalfFull           SAI_FIFOSTATUS_HALFFULL

+#define SAI_FIFOStatus_3QuartersFull      SAI_FIFOSTATUS_3QUARTERFULL

+#define SAI_FIFOStatus_Full               SAI_FIFOSTATUS_FULL

+#define IS_SAI_BLOCK_MONO_STREO_MODE      IS_SAI_BLOCK_MONO_STEREO_MODE

+#define SAI_SYNCHRONOUS_EXT               SAI_SYNCHRONOUS_EXT_SAI1

+#define SAI_SYNCEXT_IN_ENABLE             SAI_SYNCEXT_OUTBLOCKA_ENABLE

+/**

+  * @}

+  */

+

+/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose

+  * @{

+  */

+#if defined(STM32H7)

+#define HAL_SPDIFRX_ReceiveControlFlow      HAL_SPDIFRX_ReceiveCtrlFlow

+#define HAL_SPDIFRX_ReceiveControlFlow_IT   HAL_SPDIFRX_ReceiveCtrlFlow_IT

+#define HAL_SPDIFRX_ReceiveControlFlow_DMA  HAL_SPDIFRX_ReceiveCtrlFlow_DMA

+#endif

+/**

+  * @}

+  */

+

+/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose

+  * @{

+  */

+#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)

+#define HAL_HRTIM_WaveformCounterStart_IT      HAL_HRTIM_WaveformCountStart_IT

+#define HAL_HRTIM_WaveformCounterStart_DMA     HAL_HRTIM_WaveformCountStart_DMA

+#define HAL_HRTIM_WaveformCounterStart         HAL_HRTIM_WaveformCountStart

+#define HAL_HRTIM_WaveformCounterStop_IT       HAL_HRTIM_WaveformCountStop_IT

+#define HAL_HRTIM_WaveformCounterStop_DMA      HAL_HRTIM_WaveformCountStop_DMA

+#define HAL_HRTIM_WaveformCounterStop          HAL_HRTIM_WaveformCountStop

+#endif

+/**

+  * @}

+  */

+

+/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose

+  * @{

+  */

+#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7)

+#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE

+#endif /* STM32L4 || STM32F4 || STM32F7 */

+/**

+  * @}

+  */

+

+/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32_HAL_LEGACY */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+

diff --git a/bsps/arm/stm32h7/include/stm32_assert_template.h b/bsps/arm/stm32h7/include/stm32_assert_template.h
new file mode 100644
index 0000000000..37a667cce9
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32_assert_template.h
@@ -0,0 +1,57 @@
+/**

+  ******************************************************************************

+  * @file    stm32_assert.h

+  * @author  MCD Application Team

+  * @brief   STM32 assert template file.

+  *          This file should be copied to the application folder and renamed

+  *          to stm32_assert.h.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef __STM32_ASSERT_H

+#define __STM32_ASSERT_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Exported types ------------------------------------------------------------*/

+/* Exported constants --------------------------------------------------------*/

+/* Includes ------------------------------------------------------------------*/

+/* Exported macro ------------------------------------------------------------*/

+#ifdef  USE_FULL_ASSERT

+/**

+  * @brief  The assert_param macro is used for function's parameters check.

+  * @param  expr If expr is false, it calls assert_failed function

+  *         which reports the name of the source file and the source

+  *         line number of the call that failed.

+  *         If expr is true, it returns no value.

+  * @retval None

+  */

+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))

+/* Exported functions ------------------------------------------------------- */

+  void assert_failed(uint8_t* file, uint32_t line);

+#else

+  #define assert_param(expr) ((void)0U)

+#endif /* USE_FULL_ASSERT */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* __STM32_ASSERT_H */

+

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h742xx.h b/bsps/arm/stm32h7/include/stm32h742xx.h
new file mode 100644
index 0000000000..eed60f7c78
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h742xx.h
@@ -0,0 +1,25638 @@
+/**

+  ******************************************************************************

+  * @file    stm32h742xx.h

+  * @author  MCD Application Team

+  * @brief   CMSIS STM32H742xx Device Peripheral Access Layer Header File.

+  *

+  *          This file contains:

+  *           - Data structures and the address mapping for all peripherals

+  *           - Peripheral's registers declarations and bits definition

+  *           - Macros to access peripheral's registers hardware

+  *

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/** @addtogroup CMSIS_Device

+  * @{

+  */

+

+/** @addtogroup stm32h742xx

+  * @{

+  */

+

+#ifndef STM32H742xx_H

+#define STM32H742xx_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif /* __cplusplus */

+

+/** @addtogroup Peripheral_interrupt_number_definition

+  * @{

+  */

+

+/**

+ * @brief STM32H7XX Interrupt Number Definition, according to the selected device

+ *        in @ref Library_configuration_section

+ */

+typedef enum

+{

+/******  Cortex-M Processor Exceptions Numbers *****************************************************************/

+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */

+  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */

+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */

+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */

+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */

+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M SV Call Interrupt                                     */

+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M Debug Monitor Interrupt                               */

+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M Pend SV Interrupt                                     */

+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M System Tick Interrupt                                 */

+/******  STM32 specific Interrupt Numbers **********************************************************************/

+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)                   */

+  PVD_AVD_IRQn                = 1,      /*!< PVD/AVD through EXTI Line detection Interrupt                     */

+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */

+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */

+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */

+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */

+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */

+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */

+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */

+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */

+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */

+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */

+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */

+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */

+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */

+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */

+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */

+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */

+  ADC_IRQn                    = 18,     /*!< ADC1 and  ADC2 global Interrupts                                  */

+  FDCAN1_IT0_IRQn             = 19,     /*!< FDCAN1 Interrupt line 0                                           */

+  FDCAN2_IT0_IRQn             = 20,     /*!< FDCAN2 Interrupt line 0                                           */

+  FDCAN1_IT1_IRQn             = 21,     /*!< FDCAN1 Interrupt line 1                                           */

+  FDCAN2_IT1_IRQn             = 22,     /*!< FDCAN2 Interrupt line 1                                           */

+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */

+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                              */

+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                             */

+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt                            */

+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */

+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */

+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */

+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */

+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */

+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */

+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */

+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */

+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */

+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */

+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */

+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */

+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */

+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */

+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */

+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */

+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */

+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */

+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */

+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */

+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */

+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */

+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */

+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */

+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */

+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */

+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */

+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */

+  DMA2_Stream0_IRQn           = 56,     /*!<   DMA2 Stream 0 global Interrupt                                  */

+  DMA2_Stream1_IRQn           = 57,     /*!<   DMA2 Stream 1 global Interrupt                                  */

+  DMA2_Stream2_IRQn           = 58,     /*!<   DMA2 Stream 2 global Interrupt                                  */

+  DMA2_Stream3_IRQn           = 59,     /*!<   DMA2 Stream 3 global Interrupt                                  */

+  DMA2_Stream4_IRQn           = 60,     /*!<   DMA2 Stream 4 global Interrupt                                  */

+  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */

+  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */

+  FDCAN_CAL_IRQn              = 63,     /*!< FDCAN Calibration unit Interrupt                                  */

+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */

+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */

+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */

+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */

+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */

+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */

+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */

+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */

+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */

+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */

+  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */

+  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */

+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */

+  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */

+  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */

+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */

+  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */

+  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */

+  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */

+  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */

+  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */

+  QUADSPI_IRQn                = 92,     /*!< Quad SPI global interrupt                                         */

+  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */

+  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */

+  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */

+  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */

+  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */

+  OTG_FS_EP1_OUT_IRQn         = 98,     /*!< USB OTG HS2 global interrupt                                      */

+  OTG_FS_EP1_IN_IRQn          = 99,     /*!< USB OTG HS2 End Point 1 Out global interrupt                      */

+  OTG_FS_WKUP_IRQn            = 100,    /*!< USB OTG HS2 End Point 1 In global interrupt                       */

+  OTG_FS_IRQn                 = 101,    /*!< USB OTG HS2 Wakeup through EXTI interrupt                         */

+  DMAMUX1_OVR_IRQn            = 102,    /*!<DMAMUX1 Overrun interrupt                                          */

+  HRTIM1_Master_IRQn          = 103,    /*!< HRTIM Master Timer global Interrupts                              */

+  HRTIM1_TIMA_IRQn            = 104,    /*!< HRTIM Timer A global Interrupt                                    */

+  HRTIM1_TIMB_IRQn            = 105,    /*!< HRTIM Timer B global Interrupt                                    */

+  HRTIM1_TIMC_IRQn            = 106,    /*!< HRTIM Timer C global Interrupt                                    */

+  HRTIM1_TIMD_IRQn            = 107,    /*!< HRTIM Timer D global Interrupt                                    */

+  HRTIM1_TIME_IRQn            = 108,    /*!< HRTIM Timer E global Interrupt                                    */

+  HRTIM1_FLT_IRQn             = 109,    /*!< HRTIM Fault global Interrupt                                      */

+  DFSDM1_FLT0_IRQn            = 110,    /*!<DFSDM Filter1 Interrupt                                            */

+  DFSDM1_FLT1_IRQn            = 111,    /*!<DFSDM Filter2 Interrupt                                            */

+  DFSDM1_FLT2_IRQn            = 112,    /*!<DFSDM Filter3 Interrupt                                            */

+  DFSDM1_FLT3_IRQn            = 113,    /*!<DFSDM Filter4 Interrupt                                            */

+  SAI3_IRQn                   = 114,    /*!< SAI3 global Interrupt                                             */

+  SWPMI1_IRQn                 = 115,    /*!< Serial Wire Interface 1 global interrupt                          */

+  TIM15_IRQn                  = 116,    /*!< TIM15 global Interrupt                                            */

+  TIM16_IRQn                  = 117,    /*!< TIM16 global Interrupt                                            */

+  TIM17_IRQn                  = 118,    /*!< TIM17 global Interrupt                                            */

+  MDIOS_WKUP_IRQn             = 119,    /*!< MDIOS Wakeup  Interrupt                                           */

+  MDIOS_IRQn                  = 120,    /*!< MDIOS global Interrupt                                            */

+  MDMA_IRQn                   = 122,    /*!< MDMA global Interrupt                                             */

+  SDMMC2_IRQn                 = 124,    /*!< SDMMC2 global Interrupt                                           */

+  HSEM1_IRQn                  = 125,    /*!< HSEM1 global Interrupt                                            */

+  ADC3_IRQn                   = 127,    /*!< ADC3 global Interrupt                                             */

+  DMAMUX2_OVR_IRQn            = 128,    /*!<DMAMUX2 Overrun interrupt                                          */

+  BDMA_Channel0_IRQn          = 129,    /*!< BDMA Channel 0 global Interrupt                                   */

+  BDMA_Channel1_IRQn          = 130,    /*!< BDMA Channel 1 global Interrupt                                   */

+  BDMA_Channel2_IRQn          = 131,    /*!< BDMA Channel 2 global Interrupt                                   */

+  BDMA_Channel3_IRQn          = 132,    /*!< BDMA Channel 3 global Interrupt                                   */

+  BDMA_Channel4_IRQn          = 133,    /*!< BDMA Channel 4 global Interrupt                                   */

+  BDMA_Channel5_IRQn          = 134,    /*!< BDMA Channel 5 global Interrupt                                   */

+  BDMA_Channel6_IRQn          = 135,    /*!< BDMA Channel 6 global Interrupt                                   */

+  BDMA_Channel7_IRQn          = 136,    /*!< BDMA Channel 7 global Interrupt                                   */

+  COMP_IRQn                   = 137 ,   /*!< COMP global Interrupt                                             */

+  LPTIM2_IRQn                 = 138,    /*!< LP TIM2 global interrupt                                          */

+  LPTIM3_IRQn                 = 139,    /*!< LP TIM3 global interrupt                                          */

+  LPTIM4_IRQn                 = 140,    /*!< LP TIM4 global interrupt                                          */

+  LPTIM5_IRQn                 = 141,    /*!< LP TIM5 global interrupt                                          */

+  LPUART1_IRQn                = 142,    /*!< LP UART1 interrupt                                                */

+  CRS_IRQn                    = 144,    /*!< Clock Recovery Global Interrupt                                   */

+  ECC_IRQn                    = 145,    /*!< ECC diagnostic Global Interrupt                                   */

+  SAI4_IRQn                   = 146,    /*!< SAI4 global interrupt                                             */

+  WAKEUP_PIN_IRQn             = 149,    /*!< Interrupt for all 6 wake-up pins                                  */

+} IRQn_Type;

+

+/**

+  * @}

+  */

+

+/** @addtogroup Configuration_section_for_CMSIS

+  * @{

+  */

+

+

+

+

+/**

+  * @brief Configuration of the Cortex-M7 Processor and Core Peripherals

+   */

+#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */

+#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */

+#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */

+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */

+#define __FPU_PRESENT             1       /*!< FPU present                                   */

+#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */

+#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */

+#include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */

+

+/**

+  * @}

+  */

+

+

+

+

+#include "system_stm32h7xx.h"

+#include <stdint.h>

+

+/** @addtogroup Peripheral_registers_structures

+  * @{

+  */

+

+/**

+  * @brief Analog to Digital Converter

+  */

+

+typedef struct

+{

+  __IO uint32_t ISR;              /*!< ADC Interrupt and Status Register,                          Address offset: 0x00 */

+  __IO uint32_t IER;              /*!< ADC Interrupt Enable Register,                              Address offset: 0x04 */

+  __IO uint32_t CR;               /*!< ADC control register,                                       Address offset: 0x08 */

+  __IO uint32_t CFGR;             /*!< ADC Configuration register,                                 Address offset: 0x0C */

+  __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                               Address offset: 0x10 */

+  __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                                 Address offset: 0x14 */

+  __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                                 Address offset: 0x18 */

+  __IO uint32_t PCSEL;            /*!< ADC pre-channel selection,                                  Address offset: 0x1C */

+  __IO uint32_t LTR1;             /*!< ADC watchdog Lower threshold register 1,                    Address offset: 0x20 */

+  __IO uint32_t HTR1;             /*!< ADC watchdog higher threshold register 1,                   Address offset: 0x24 */

+  uint32_t      RESERVED1;        /*!< Reserved, 0x028                                                                  */

+  uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                                  */

+  __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                            Address offset: 0x30 */

+  __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                            Address offset: 0x34 */

+  __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                            Address offset: 0x38 */

+  __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                            Address offset: 0x3C */

+  __IO uint32_t DR;               /*!< ADC regular data register,                                  Address offset: 0x40 */

+  uint32_t      RESERVED3;        /*!< Reserved, 0x044                                                                  */

+  uint32_t      RESERVED4;        /*!< Reserved, 0x048                                                                  */

+  __IO uint32_t JSQR;             /*!< ADC injected sequence register,                             Address offset: 0x4C */

+  uint32_t      RESERVED5[4];     /*!< Reserved, 0x050 - 0x05C                                                          */

+  __IO uint32_t OFR1;             /*!< ADC offset register 1,                                      Address offset: 0x60 */

+  __IO uint32_t OFR2;             /*!< ADC offset register 2,                                      Address offset: 0x64 */

+  __IO uint32_t OFR3;             /*!< ADC offset register 3,                                      Address offset: 0x68 */

+  __IO uint32_t OFR4;             /*!< ADC offset register 4,                                      Address offset: 0x6C */

+  uint32_t      RESERVED6[4];     /*!< Reserved, 0x070 - 0x07C                                                          */

+  __IO uint32_t JDR1;             /*!< ADC injected data register 1,                               Address offset: 0x80 */

+  __IO uint32_t JDR2;             /*!< ADC injected data register 2,                               Address offset: 0x84 */

+  __IO uint32_t JDR3;             /*!< ADC injected data register 3,                               Address offset: 0x88 */

+  __IO uint32_t JDR4;             /*!< ADC injected data register 4,                               Address offset: 0x8C */

+  uint32_t      RESERVED7[4];     /*!< Reserved, 0x090 - 0x09C                                                          */

+  __IO uint32_t AWD2CR;           /*!< ADC  Analog Watchdog 2 Configuration Register,              Address offset: 0xA0 */

+  __IO uint32_t AWD3CR;           /*!< ADC  Analog Watchdog 3 Configuration Register,              Address offset: 0xA4 */

+  uint32_t      RESERVED8;        /*!< Reserved, 0x0A8                                                                  */

+  uint32_t      RESERVED9;        /*!< Reserved, 0x0AC                                                                  */

+  __IO uint32_t LTR2;             /*!< ADC watchdog Lower threshold register 2,                    Address offset: 0xB0 */

+  __IO uint32_t HTR2;             /*!< ADC watchdog Higher threshold register 2,                   Address offset: 0xB4 */

+  __IO uint32_t LTR3;             /*!< ADC watchdog Lower threshold register 3,                    Address offset: 0xB8 */

+  __IO uint32_t HTR3;             /*!< ADC watchdog Higher threshold register 3,                   Address offset: 0xBC */

+  __IO uint32_t DIFSEL;           /*!< ADC  Differential Mode Selection Register,                  Address offset: 0xC0 */

+  __IO uint32_t CALFACT;          /*!< ADC  Calibration Factors,                                   Address offset: 0xC4 */

+  __IO uint32_t CALFACT2;         /*!< ADC  Linearity Calibration Factors,                         Address offset: 0xC8 */

+} ADC_TypeDef;

+

+

+typedef struct

+{

+__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */

+uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */

+__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */

+__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */

+__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */

+

+} ADC_Common_TypeDef;

+

+

+/**

+  * @brief VREFBUF

+  */

+

+typedef struct

+{

+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */

+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */

+} VREFBUF_TypeDef;

+

+

+/**

+  * @brief FD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */

+  __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */

+  __IO uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */

+  __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */

+  __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */

+  __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */

+  __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */

+  __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */

+  __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */

+  __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */

+  __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */

+  __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */

+  __IO uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */

+  __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */

+  __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */

+  __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */

+  __IO uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */

+  __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */

+  __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */

+  __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */

+  __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */

+  __IO uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */

+  __IO uint32_t GFC;          /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */

+  __IO uint32_t SIDFC;        /*!< FDCAN Standard ID Filter Configuration register,                 Address offset: 0x084 */

+  __IO uint32_t XIDFC;        /*!< FDCAN Extended ID Filter Configuration register,                 Address offset: 0x088 */

+  __IO uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */

+  __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x090 */

+  __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x094 */

+  __IO uint32_t NDAT1;        /*!< FDCAN New Data 1 register,                                       Address offset: 0x098 */

+  __IO uint32_t NDAT2;        /*!< FDCAN New Data 2 register,                                       Address offset: 0x09C */

+  __IO uint32_t RXF0C;        /*!< FDCAN Rx FIFO 0 Configuration register,                          Address offset: 0x0A0 */

+  __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x0A4 */

+  __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x0A8 */

+  __IO uint32_t RXBC;         /*!< FDCAN Rx Buffer Configuration register,                          Address offset: 0x0AC */

+  __IO uint32_t RXF1C;        /*!< FDCAN Rx FIFO 1 Configuration register,                          Address offset: 0x0B0 */

+  __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x0B4 */

+  __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x0B8 */

+  __IO uint32_t RXESC;        /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register,        Address offset: 0x0BC */

+  __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */

+  __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */

+  __IO uint32_t TXESC;        /*!< FDCAN Tx Buffer Element Size Configuration register,             Address offset: 0x0C8 */

+  __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0CC */

+  __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0D0 */

+  __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D4 */

+  __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D8 */

+  __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0DC */

+  __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0E0 */

+  __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */

+  __IO uint32_t RESERVED6[2]; /*!< Reserved,                                                                0x0E8 - 0x0EC */

+  __IO uint32_t TXEFC;        /*!< FDCAN Tx Event FIFO Configuration register,                      Address offset: 0x0F0 */

+  __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0F4 */

+  __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0F8 */

+  __IO uint32_t RESERVED7;    /*!< Reserved,                                                                        0x0FC */

+} FDCAN_GlobalTypeDef;

+

+/**

+  * @brief TTFD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t TTTMC;          /*!< TT Trigger Memory Configuration register,    Address offset: 0x100 */

+  __IO uint32_t TTRMC;          /*!< TT Reference Message Configuration register, Address offset: 0x104 */

+  __IO uint32_t TTOCF;          /*!< TT Operation Configuration register,         Address offset: 0x108 */

+  __IO uint32_t TTMLM;          /*!< TT Matrix Limits register,                   Address offset: 0x10C */

+  __IO uint32_t TURCF;          /*!< TUR Configuration register,                  Address offset: 0x110 */

+  __IO uint32_t TTOCN;          /*!< TT Operation Control register,               Address offset: 0x114 */

+  __IO uint32_t TTGTP;          /*!< TT Global Time Preset register,              Address offset: 0x118 */

+  __IO uint32_t TTTMK;          /*!< TT Time Mark register,                       Address offset: 0x11C */

+  __IO uint32_t TTIR;           /*!< TT Interrupt register,                       Address offset: 0x120 */

+  __IO uint32_t TTIE;           /*!< TT Interrupt Enable register,                Address offset: 0x124 */

+  __IO uint32_t TTILS;          /*!< TT Interrupt Line Select register,           Address offset: 0x128 */

+  __IO uint32_t TTOST;          /*!< TT Operation Status register,                Address offset: 0x12C */

+  __IO uint32_t TURNA;          /*!< TT TUR Numerator Actual register,            Address offset: 0x130 */

+  __IO uint32_t TTLGT;          /*!< TT Local and Global Time register,           Address offset: 0x134 */

+  __IO uint32_t TTCTC;          /*!< TT Cycle Time and Count register,            Address offset: 0x138 */

+  __IO uint32_t TTCPT;          /*!< TT Capture Time register,                    Address offset: 0x13C */

+  __IO uint32_t TTCSM;          /*!< TT Cycle Sync Mark register,                 Address offset: 0x140 */

+  __IO uint32_t RESERVED1[111]; /*!< Reserved,                                            0x144 - 0x2FC */

+  __IO uint32_t TTTS;           /*!< TT Trigger Select register,                  Address offset: 0x300 */

+} TTCAN_TypeDef;

+

+/**

+  * @brief FD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t CREL;  /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */

+  __IO uint32_t CCFG;  /*!< Calibration Configuration register,           Address offset: 0x04 */

+  __IO uint32_t CSTAT; /*!< Calibration Status register,                  Address offset: 0x08 */

+  __IO uint32_t CWD;   /*!< Calibration Watchdog register,                Address offset: 0x0C */

+  __IO uint32_t IR;    /*!< CCU Interrupt register,                       Address offset: 0x10 */

+  __IO uint32_t IE;    /*!< CCU Interrupt Enable register,                Address offset: 0x14 */

+} FDCAN_ClockCalibrationUnit_TypeDef;

+

+

+/**

+  * @brief Consumer Electronics Control

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;           /*!< CEC control register,              Address offset:0x00 */

+  __IO uint32_t CFGR;         /*!< CEC configuration register,        Address offset:0x04 */

+  __IO uint32_t TXDR;         /*!< CEC Tx data register ,             Address offset:0x08 */

+  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,              Address offset:0x0C */

+  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register, Address offset:0x10 */

+  __IO uint32_t IER;          /*!< CEC interrupt enable register,     Address offset:0x14 */

+}CEC_TypeDef;

+

+/**

+  * @brief CRC calculation unit

+  */

+

+typedef struct

+{

+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */

+  __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */

+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */

+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */

+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */

+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */

+} CRC_TypeDef;

+

+

+/**

+  * @brief Clock Recovery System

+  */

+typedef struct

+{

+__IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */

+__IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */

+__IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */

+__IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */

+} CRS_TypeDef;

+

+

+/**

+  * @brief Digital to Analog Converter

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */

+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */

+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */

+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */

+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */

+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */

+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */

+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */

+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */

+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */

+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */

+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */

+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */

+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */

+  __IO uint32_t CCR;      /*!< DAC calibration control register,                        Address offset: 0x38 */

+  __IO uint32_t MCR;      /*!< DAC mode control register,                               Address offset: 0x3C */

+  __IO uint32_t SHSR1;    /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */

+  __IO uint32_t SHSR2;    /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */

+  __IO uint32_t SHHR;     /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */

+  __IO uint32_t SHRR;     /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */

+} DAC_TypeDef;

+

+/**

+  * @brief DFSDM module registers

+  */

+typedef struct

+{

+  __IO uint32_t FLTCR1;          /*!< DFSDM control register1,                          Address offset: 0x100 */

+  __IO uint32_t FLTCR2;          /*!< DFSDM control register2,                          Address offset: 0x104 */

+  __IO uint32_t FLTISR;          /*!< DFSDM interrupt and status register,              Address offset: 0x108 */

+  __IO uint32_t FLTICR;          /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */

+  __IO uint32_t FLTJCHGR;        /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */

+  __IO uint32_t FLTFCR;          /*!< DFSDM filter control register,                    Address offset: 0x114 */

+  __IO uint32_t FLTJDATAR;       /*!< DFSDM data register for injected group,           Address offset: 0x118 */

+  __IO uint32_t FLTRDATAR;       /*!< DFSDM data register for regular group,            Address offset: 0x11C */

+  __IO uint32_t FLTAWHTR;        /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */

+  __IO uint32_t FLTAWLTR;        /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */

+  __IO uint32_t FLTAWSR;         /*!< DFSDM analog watchdog status register             Address offset: 0x128 */

+  __IO uint32_t FLTAWCFR;        /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */

+  __IO uint32_t FLTEXMAX;        /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */

+  __IO uint32_t FLTEXMIN;        /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */

+  __IO uint32_t FLTCNVTIMR;      /*!< DFSDM conversion timer,                           Address offset: 0x138 */

+} DFSDM_Filter_TypeDef;

+

+/**

+  * @brief DFSDM channel configuration registers

+  */

+typedef struct

+{

+  __IO uint32_t CHCFGR1;      /*!< DFSDM channel configuration register1,            Address offset: 0x00 */

+  __IO uint32_t CHCFGR2;      /*!< DFSDM channel configuration register2,            Address offset: 0x04 */

+  __IO uint32_t CHAWSCDR;     /*!< DFSDM channel analog watchdog and

+                                   short circuit detector register,                  Address offset: 0x08 */

+  __IO uint32_t CHWDATAR;     /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */

+  __IO uint32_t CHDATINR;     /*!< DFSDM channel data input register,                Address offset: 0x10 */

+} DFSDM_Channel_TypeDef;

+

+/**

+  * @brief Debug MCU

+  */

+typedef struct

+{

+  __IO uint32_t IDCODE;        /*!< MCU device ID code,                     Address offset: 0x00 */

+  __IO uint32_t CR;            /*!< Debug MCU configuration register,       Address offset: 0x04 */

+  uint32_t RESERVED4[11];      /*!< Reserved,                             Address offset: 0x08 */

+  __IO uint32_t APB3FZ1;     /*!< Debug MCU APB3FZ1 freeze register,    Address offset: 0x34 */

+  uint32_t RESERVED5;          /*!< Reserved,                             Address offset: 0x38 */

+  __IO uint32_t APB1LFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x3C */

+  uint32_t RESERVED6;          /*!< Reserved,                             Address offset: 0x40 */

+  __IO uint32_t APB1HFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x44 */

+  uint32_t RESERVED7;          /*!< Reserved,                             Address offset: 0x48 */

+  __IO uint32_t APB2FZ1;     /*!< Debug MCU APB2FZ1 freeze register,    Address offset: 0x4C */

+  uint32_t RESERVED8;          /*!< Reserved,                             Address offset: 0x50 */

+  __IO uint32_t APB4FZ1;     /*!< Debug MCU APB4FZ1 freeze register,    Address offset: 0x54 */

+}DBGMCU_TypeDef;

+/**

+  * @brief DCMI

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */

+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */

+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */

+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */

+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */

+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */

+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */

+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */

+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */

+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */

+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */

+} DCMI_TypeDef;

+

+/**

+  * @brief DMA Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */

+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */

+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */

+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */

+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */

+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */

+} DMA_Stream_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */

+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */

+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */

+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */

+} DMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CCR;          /*!< DMA channel x configuration register          */

+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register         */

+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register     */

+  __IO uint32_t CM0AR;        /*!< DMA channel x memory 0 address register       */

+  __IO uint32_t CM1AR;        /*!< DMA channel x memory 1 address register       */

+} BDMA_Channel_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */

+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */

+} BDMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CCR;        /*!< DMA Multiplexer Channel x Control Register   */

+}DMAMUX_Channel_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CSR;      /*!< DMA Channel Status Register     */

+  __IO uint32_t  CFR;      /*!< DMA Channel Clear Flag Register */

+}DMAMUX_ChannelStatus_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  RGCR;        /*!< DMA Request Generator x Control Register   */

+}DMAMUX_RequestGen_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  RGSR;        /*!< DMA Request Generator Status Register       */

+  __IO uint32_t  RGCFR;       /*!< DMA Request Generator Clear Flag Register   */

+}DMAMUX_RequestGenStatus_TypeDef;

+

+/**

+  * @brief MDMA Controller

+  */

+typedef struct

+{

+  __IO uint32_t  GISR0;   /*!< MDMA Global Interrupt/Status Register 0,          Address offset: 0x00 */

+}MDMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CISR;      /*!< MDMA channel x interrupt/status register,             Address offset: 0x40 */

+  __IO uint32_t  CIFCR;     /*!< MDMA channel x interrupt flag clear register,         Address offset: 0x44 */

+  __IO uint32_t  CESR;      /*!< MDMA Channel x error status register,                 Address offset: 0x48 */

+  __IO uint32_t  CCR;       /*!< MDMA channel x control register,                      Address offset: 0x4C */

+  __IO uint32_t  CTCR;      /*!< MDMA channel x Transfer Configuration register,       Address offset: 0x50 */

+  __IO uint32_t  CBNDTR;    /*!< MDMA Channel x block number of data register,         Address offset: 0x54 */

+  __IO uint32_t  CSAR;      /*!< MDMA channel x source address register,               Address offset: 0x58 */

+  __IO uint32_t  CDAR;      /*!< MDMA channel x destination address register,          Address offset: 0x5C */

+  __IO uint32_t  CBRUR;     /*!< MDMA channel x Block Repeat address Update register,  Address offset: 0x60 */

+  __IO uint32_t  CLAR;      /*!< MDMA channel x Link Address register,                 Address offset: 0x64 */

+  __IO uint32_t  CTBR;      /*!< MDMA channel x Trigger and Bus selection Register,    Address offset: 0x68 */

+  uint32_t       RESERVED0; /*!< Reserved, 0x68                                                             */

+  __IO uint32_t  CMAR;      /*!< MDMA channel x Mask address register,                 Address offset: 0x70 */

+  __IO uint32_t  CMDR;      /*!< MDMA channel x Mask Data register,                    Address offset: 0x74 */

+}MDMA_Channel_TypeDef;

+

+/**

+  * @brief DMA2D Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */

+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */

+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */

+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */

+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */

+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */

+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */

+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */

+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */

+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */

+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */

+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */

+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */

+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */

+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */

+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */

+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */

+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */

+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */

+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */

+  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */

+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */

+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */

+} DMA2D_TypeDef;

+

+

+/**

+  * @brief Ethernet MAC

+  */

+typedef struct

+{

+  __IO uint32_t MACCR;

+  __IO uint32_t MACECR;

+  __IO uint32_t MACPFR;

+  __IO uint32_t MACWTR;

+  __IO uint32_t MACHT0R;

+  __IO uint32_t MACHT1R;

+  uint32_t      RESERVED1[14];

+  __IO uint32_t MACVTR;

+  uint32_t      RESERVED2;

+  __IO uint32_t MACVHTR;

+  uint32_t      RESERVED3;

+  __IO uint32_t MACVIR;

+  __IO uint32_t MACIVIR;

+  uint32_t      RESERVED4[2];

+  __IO uint32_t MACTFCR;

+  uint32_t      RESERVED5[7];

+  __IO uint32_t MACRFCR;

+  uint32_t      RESERVED6[7];

+  __IO uint32_t MACISR;

+  __IO uint32_t MACIER;

+  __IO uint32_t MACRXTXSR;

+  uint32_t      RESERVED7;

+  __IO uint32_t MACPCSR;

+  __IO uint32_t MACRWKPFR;

+  uint32_t      RESERVED8[2];

+  __IO uint32_t MACLCSR;

+  __IO uint32_t MACLTCR;

+  __IO uint32_t MACLETR;

+  __IO uint32_t MAC1USTCR;

+  uint32_t      RESERVED9[12];

+  __IO uint32_t MACVR;

+  __IO uint32_t MACDR;

+  uint32_t      RESERVED10;

+  __IO uint32_t MACHWF0R;

+  __IO uint32_t MACHWF1R;

+  __IO uint32_t MACHWF2R;

+  uint32_t      RESERVED11[54];

+  __IO uint32_t MACMDIOAR;

+  __IO uint32_t MACMDIODR;

+  uint32_t      RESERVED12[2];

+  __IO uint32_t MACARPAR;

+  uint32_t      RESERVED13[59];

+  __IO uint32_t MACA0HR;

+  __IO uint32_t MACA0LR;

+  __IO uint32_t MACA1HR;

+  __IO uint32_t MACA1LR;

+  __IO uint32_t MACA2HR;

+  __IO uint32_t MACA2LR;

+  __IO uint32_t MACA3HR;

+  __IO uint32_t MACA3LR;

+  uint32_t      RESERVED14[248];

+  __IO uint32_t MMCCR;

+  __IO uint32_t MMCRIR;

+  __IO uint32_t MMCTIR;

+  __IO uint32_t MMCRIMR;

+  __IO uint32_t MMCTIMR;

+  uint32_t      RESERVED15[14];

+  __IO uint32_t MMCTSCGPR;

+  __IO uint32_t MMCTMCGPR;

+  uint32_t      RESERVED16[5];

+  __IO uint32_t MMCTPCGR;

+  uint32_t      RESERVED17[10];

+  __IO uint32_t MMCRCRCEPR;

+  __IO uint32_t MMCRAEPR;

+  uint32_t      RESERVED18[10];

+  __IO uint32_t MMCRUPGR;

+  uint32_t      RESERVED19[9];

+  __IO uint32_t MMCTLPIMSTR;

+  __IO uint32_t MMCTLPITCR;

+  __IO uint32_t MMCRLPIMSTR;

+  __IO uint32_t MMCRLPITCR;

+  uint32_t      RESERVED20[65];

+  __IO uint32_t MACL3L4C0R;

+  __IO uint32_t MACL4A0R;

+  uint32_t      RESERVED21[2];

+  __IO uint32_t MACL3A0R0R;

+  __IO uint32_t MACL3A1R0R;

+  __IO uint32_t MACL3A2R0R;

+  __IO uint32_t MACL3A3R0R;

+  uint32_t      RESERVED22[4];

+  __IO uint32_t MACL3L4C1R;

+  __IO uint32_t MACL4A1R;

+  uint32_t      RESERVED23[2];

+  __IO uint32_t MACL3A0R1R;

+  __IO uint32_t MACL3A1R1R;

+  __IO uint32_t MACL3A2R1R;

+  __IO uint32_t MACL3A3R1R;

+  uint32_t      RESERVED24[108];

+  __IO uint32_t MACTSCR;

+  __IO uint32_t MACSSIR;

+  __IO uint32_t MACSTSR;

+  __IO uint32_t MACSTNR;

+  __IO uint32_t MACSTSUR;

+  __IO uint32_t MACSTNUR;

+  __IO uint32_t MACTSAR;

+  uint32_t      RESERVED25;

+  __IO uint32_t MACTSSR;

+  uint32_t      RESERVED26[3];

+  __IO uint32_t MACTTSSNR;

+  __IO uint32_t MACTTSSSR;

+  uint32_t      RESERVED27[2];

+  __IO uint32_t MACACR;

+  uint32_t      RESERVED28;

+  __IO uint32_t MACATSNR;

+  __IO uint32_t MACATSSR;

+  __IO uint32_t MACTSIACR;

+  __IO uint32_t MACTSEACR;

+  __IO uint32_t MACTSICNR;

+  __IO uint32_t MACTSECNR;

+  uint32_t      RESERVED29[4];

+  __IO uint32_t MACPPSCR;

+  uint32_t      RESERVED30[3];

+  __IO uint32_t MACPPSTTSR;

+  __IO uint32_t MACPPSTTNR;

+  __IO uint32_t MACPPSIR;

+  __IO uint32_t MACPPSWR;

+  uint32_t      RESERVED31[12];

+  __IO uint32_t MACPOCR;

+  __IO uint32_t MACSPI0R;

+  __IO uint32_t MACSPI1R;

+  __IO uint32_t MACSPI2R;

+  __IO uint32_t MACLMIR;

+  uint32_t      RESERVED32[11];

+  __IO uint32_t MTLOMR;

+  uint32_t      RESERVED33[7];

+  __IO uint32_t MTLISR;

+  uint32_t      RESERVED34[55];

+  __IO uint32_t MTLTQOMR;

+  __IO uint32_t MTLTQUR;

+  __IO uint32_t MTLTQDR;

+  uint32_t      RESERVED35[8];

+  __IO uint32_t MTLQICSR;

+  __IO uint32_t MTLRQOMR;

+  __IO uint32_t MTLRQMPOCR;

+  __IO uint32_t MTLRQDR;

+  uint32_t      RESERVED36[177];

+  __IO uint32_t DMAMR;

+  __IO uint32_t DMASBMR;

+  __IO uint32_t DMAISR;

+  __IO uint32_t DMADSR;

+  uint32_t      RESERVED37[60];

+  __IO uint32_t DMACCR;

+  __IO uint32_t DMACTCR;

+  __IO uint32_t DMACRCR;

+  uint32_t      RESERVED38[2];

+  __IO uint32_t DMACTDLAR;

+  uint32_t      RESERVED39;

+  __IO uint32_t DMACRDLAR;

+  __IO uint32_t DMACTDTPR;

+  uint32_t      RESERVED40;

+  __IO uint32_t DMACRDTPR;

+  __IO uint32_t DMACTDRLR;

+  __IO uint32_t DMACRDRLR;

+  __IO uint32_t DMACIER;

+  __IO uint32_t DMACRIWTR;

+__IO uint32_t DMACSFCSR;

+  uint32_t      RESERVED41;

+  __IO uint32_t DMACCATDR;

+  uint32_t      RESERVED42;

+  __IO uint32_t DMACCARDR;

+  uint32_t      RESERVED43;

+  __IO uint32_t DMACCATBR;

+  uint32_t      RESERVED44;

+  __IO uint32_t DMACCARBR;

+  __IO uint32_t DMACSR;

+uint32_t      RESERVED45[2];

+__IO uint32_t DMACMFCR;

+}ETH_TypeDef;

+/**

+  * @brief External Interrupt/Event Controller

+  */

+

+typedef struct

+{

+__IO uint32_t RTSR1;               /*!< EXTI Rising trigger selection register,          Address offset: 0x00 */

+__IO uint32_t FTSR1;               /*!< EXTI Falling trigger selection register,         Address offset: 0x04 */

+__IO uint32_t SWIER1;              /*!< EXTI Software interrupt event register,          Address offset: 0x08 */

+__IO uint32_t D3PMR1;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */

+__IO uint32_t D3PCR1L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L)     Address offset: 0x10 */

+__IO uint32_t D3PCR1H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H)   Address offset: 0x14 */

+uint32_t      RESERVED1[2];        /*!< Reserved,                                        0x18 to 0x1C         */

+__IO uint32_t RTSR2;               /*!< EXTI Rising trigger selection register,          Address offset: 0x20 */

+__IO uint32_t FTSR2;               /*!< EXTI Falling trigger selection register,         Address offset: 0x24 */

+__IO uint32_t SWIER2;              /*!< EXTI Software interrupt event register,          Address offset: 0x28 */

+__IO uint32_t D3PMR2;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */

+__IO uint32_t D3PCR2L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L)  Address offset: 0x30 */

+__IO uint32_t D3PCR2H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */

+uint32_t      RESERVED2[2];        /*!< Reserved,                                        0x38 to 0x3C         */

+__IO uint32_t RTSR3;               /*!< EXTI Rising trigger selection register,          Address offset: 0x40 */

+__IO uint32_t FTSR3;               /*!< EXTI Falling trigger selection register,         Address offset: 0x44 */

+__IO uint32_t SWIER3;              /*!< EXTI Software interrupt event register,          Address offset: 0x48 */

+__IO uint32_t D3PMR3;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */

+__IO uint32_t D3PCR3L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */

+__IO uint32_t D3PCR3H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */

+uint32_t      RESERVED3[10];       /*!< Reserved,                                        0x58 to 0x7C         */

+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                    Address offset: 0x80 */

+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                        Address offset: 0x84 */

+__IO uint32_t PR1;                 /*!< EXTI Pending register,                           Address offset: 0x88 */

+uint32_t      RESERVED4;           /*!< Reserved,                                        0x8C                 */

+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                    Address offset: 0x90 */

+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                        Address offset: 0x94 */

+__IO uint32_t PR2;                 /*!< EXTI Pending register,                           Address offset: 0x98 */

+uint32_t      RESERVED5;           /*!< Reserved,                                        0x9C                 */

+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                    Address offset: 0xA0 */

+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                        Address offset: 0xA4 */

+__IO uint32_t PR3;                 /*!< EXTI Pending register,                           Address offset: 0xA8 */

+}EXTI_TypeDef;

+

+typedef struct

+{

+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                Address offset: 0x00 */

+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                    Address offset: 0x04 */

+__IO uint32_t PR1;                 /*!< EXTI Pending register,                       Address offset: 0x08 */

+uint32_t      RESERVED1;           /*!< Reserved, 0x0C                                                    */

+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                Address offset: 0x10 */

+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                    Address offset: 0x14 */

+__IO uint32_t PR2;                 /*!< EXTI Pending register,                       Address offset: 0x18 */

+uint32_t      RESERVED2;           /*!< Reserved, 0x1C                                                    */

+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                Address offset: 0x20 */

+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                    Address offset: 0x24 */

+__IO uint32_t PR3;                 /*!< EXTI Pending register,                       Address offset: 0x28 */

+}EXTI_Core_TypeDef;

+

+

+/**

+  * @brief FLASH Registers

+  */

+

+typedef struct

+{

+  __IO uint32_t ACR;             /*!< FLASH access control register,                            Address offset: 0x00  */

+  __IO uint32_t KEYR1;           /*!< Flash Key Register for bank1,                             Address offset: 0x04  */

+  __IO uint32_t OPTKEYR;         /*!< Flash Option Key Register,                                Address offset: 0x08  */

+  __IO uint32_t CR1;             /*!< Flash Control Register for bank1,                         Address offset: 0x0C  */

+  __IO uint32_t SR1;             /*!< Flash Status Register for bank1,                          Address offset: 0x10  */

+  __IO uint32_t CCR1;            /*!< Flash Control Register for bank1,                         Address offset: 0x14  */

+  __IO uint32_t OPTCR;           /*!< Flash Option Control Register,                            Address offset: 0x18  */

+  __IO uint32_t OPTSR_CUR;       /*!< Flash Option Status Current Register,                     Address offset: 0x1C  */

+  __IO uint32_t OPTSR_PRG;       /*!< Flash Option Status to Program Register,                  Address offset: 0x20  */

+  __IO uint32_t OPTCCR;          /*!< Flash Option Clear Control Register,                      Address offset: 0x24  */

+  __IO uint32_t PRAR_CUR1;       /*!< Flash Current Protection Address Register for bank1,      Address offset: 0x28  */

+  __IO uint32_t PRAR_PRG1;       /*!< Flash Protection Address to Program Register for bank1,   Address offset: 0x2C  */

+  __IO uint32_t SCAR_CUR1;       /*!< Flash Current Secure Address Register for bank1,          Address offset: 0x30  */

+  __IO uint32_t SCAR_PRG1;       /*!< Flash Secure Address to Program Register for bank1,       Address offset: 0x34  */

+  __IO uint32_t WPSN_CUR1;       /*!< Flash Current Write Protection Register on bank1,         Address offset: 0x38  */

+  __IO uint32_t WPSN_PRG1;       /*!< Flash Write Protection to Program Register on bank1,      Address offset: 0x3C  */

+  __IO uint32_t BOOT_CUR;        /*!< Flash Current Boot Address for Pelican Core Register,     Address offset: 0x40  */

+  __IO uint32_t BOOT_PRG;        /*!< Flash Boot Address to Program for Pelican Core Register,  Address offset: 0x44  */

+  uint32_t      RESERVED0[2];    /*!< Reserved, 0x48 to 0x4C                                                          */

+  __IO uint32_t CRCCR1;          /*!< Flash CRC Control register For Bank1 Register ,           Address offset: 0x50  */

+  __IO uint32_t CRCSADD1;        /*!< Flash CRC Start Address Register for Bank1 ,              Address offset: 0x54  */

+  __IO uint32_t CRCEADD1;        /*!< Flash CRC End Address Register for Bank1 ,                Address offset: 0x58  */

+  __IO uint32_t CRCDATA;         /*!< Flash CRC Data Register for Bank1 ,                       Address offset: 0x5C  */

+  __IO uint32_t ECC_FA1;         /*!< Flash ECC Fail Address For Bank1 Register ,               Address offset: 0x60  */

+  uint32_t      RESERVED1[40];   /*!< Reserved, 0x64 to 0x100                                                         */

+  __IO uint32_t KEYR2;           /*!< Flash Key Register for bank2,                             Address offset: 0x104 */

+  uint32_t      RESERVED2;       /*!< Reserved, 0x108                                                                 */

+  __IO uint32_t CR2;             /*!< Flash Control Register for bank2,                         Address offset: 0x10C */

+  __IO uint32_t SR2;             /*!< Flash Status Register for bank2,                          Address offset: 0x110 */

+  __IO uint32_t CCR2;            /*!< Flash Status Register for bank2,                          Address offset: 0x114 */

+  uint32_t      RESERVED3[4];    /*!< Reserved, 0x118 to 0x124                                                        */

+  __IO uint32_t PRAR_CUR2;       /*!< Flash Current Protection Address Register for bank2,      Address offset: 0x128 */

+  __IO uint32_t PRAR_PRG2;       /*!< Flash Protection Address to Program Register for bank2,   Address offset: 0x12C */

+  __IO uint32_t SCAR_CUR2;       /*!< Flash Current Secure Address Register for bank2,          Address offset: 0x130 */

+  __IO uint32_t SCAR_PRG2;       /*!< Flash Secure Address Register for bank2,                  Address offset: 0x134 */

+  __IO uint32_t WPSN_CUR2;       /*!< Flash Current Write Protection Register on bank2,         Address offset: 0x138 */

+  __IO uint32_t WPSN_PRG2;       /*!< Flash Write Protection to Program Register on bank2,      Address offset: 0x13C */

+  uint32_t      RESERVED4[4];    /*!< Reserved, 0x140 to 0x14C                                                        */

+  __IO uint32_t CRCCR2;          /*!< Flash CRC Control register For Bank2 Register ,           Address offset: 0x150 */

+  __IO uint32_t CRCSADD2;        /*!< Flash CRC Start Address Register for Bank2 ,              Address offset: 0x154 */

+  __IO uint32_t CRCEADD2;        /*!< Flash CRC End Address Register for Bank2 ,                Address offset: 0x158 */

+  __IO uint32_t CRCDATA2;        /*!< Flash CRC Data Register for Bank2 ,                       Address offset: 0x15C */

+  __IO uint32_t ECC_FA2;         /*!< Flash ECC Fail Address For Bank2 Register ,               Address offset: 0x160 */

+} FLASH_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */

+} FMC_Bank1_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank1E

+  */

+

+typedef struct

+{

+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */

+} FMC_Bank1E_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank2

+  */

+

+typedef struct

+{

+  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */

+  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */

+  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */

+  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */

+  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */

+  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */

+} FMC_Bank2_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank3

+  */

+

+typedef struct

+{

+  __IO uint32_t PCR;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */

+  __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */

+  __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */

+  __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */

+  uint32_t      RESERVED;  /*!< Reserved, 0x90                                                            */

+  __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */

+} FMC_Bank3_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank5 and 6

+  */

+

+

+typedef struct

+{

+  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */

+  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */

+  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */

+  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */

+  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */

+} FMC_Bank5_6_TypeDef;

+

+/**

+  * @brief General Purpose I/O

+  */

+

+typedef struct

+{

+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */

+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */

+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */

+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */

+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */

+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */

+  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset,               Address offset: 0x18      */

+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */

+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */

+} GPIO_TypeDef;

+

+/**

+  * @brief Operational Amplifier (OPAMP)

+  */

+

+typedef struct

+{

+  __IO uint32_t CSR;          /*!< OPAMP control/status register,                      Address offset: 0x00 */

+  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,     Address offset: 0x04 */

+  __IO uint32_t HSOTR;        /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */

+} OPAMP_TypeDef;

+

+/**

+  * @brief System configuration controller

+  */

+

+typedef struct

+{

+ uint32_t RESERVED1;           /*!< Reserved,                                           Address offset: 0x00        */

+ __IO uint32_t PMCR;           /*!< SYSCFG peripheral mode configuration register,      Address offset: 0x04        */

+ __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration registers,  Address offset: 0x08-0x14   */

+ __IO uint32_t CFGR;           /*!< SYSCFG configuration registers,                     Address offset: 0x18        */

+ uint32_t RESERVED2;           /*!< Reserved,                                           Address offset: 0x1C        */

+ __IO uint32_t CCCSR;          /*!< SYSCFG compensation cell control/status register,   Address offset: 0x20        */

+ __IO uint32_t CCVR;           /*!< SYSCFG compensation cell value register,            Address offset: 0x24        */

+ __IO uint32_t CCCR;           /*!< SYSCFG compensation cell code register,             Address offset: 0x28        */

+ __IO uint32_t PWRCR;          /*!< PWR control register,                               Address offset: 0x2C        */

+  uint32_t     RESERVED3[61];  /*!< Reserved, 0x30-0x120                                                            */

+  __IO uint32_t PKGR;          /*!< SYSCFG package register,                            Address offset: 0x124       */

+  uint32_t     RESERVED4[118]; /*!< Reserved, 0x128-0x2FC                                                           */

+ __IO uint32_t UR0;            /*!< SYSCFG user register 0,                             Address offset: 0x300       */

+ __IO uint32_t UR1;            /*!< SYSCFG user register 1,                             Address offset: 0x304       */

+ __IO uint32_t UR2;            /*!< SYSCFG user register 2,                             Address offset: 0x308       */

+ __IO uint32_t UR3;            /*!< SYSCFG user register 3,                             Address offset: 0x30C       */

+ __IO uint32_t UR4;            /*!< SYSCFG user register 4,                             Address offset: 0x310       */

+ __IO uint32_t UR5;            /*!< SYSCFG user register 5,                             Address offset: 0x314       */

+ __IO uint32_t UR6;            /*!< SYSCFG user register 6,                             Address offset: 0x318       */

+ __IO uint32_t UR7;            /*!< SYSCFG user register 7,                             Address offset: 0x31C       */

+ __IO uint32_t UR8;            /*!< SYSCFG user register 8,                             Address offset: 0x320       */

+ __IO uint32_t UR9;            /*!< SYSCFG user register 9,                             Address offset: 0x324       */

+ __IO uint32_t UR10;           /*!< SYSCFG user register 10,                            Address offset: 0x328       */

+ __IO uint32_t UR11;           /*!< SYSCFG user register 11,                            Address offset: 0x32C       */

+ __IO uint32_t UR12;           /*!< SYSCFG user register 12,                            Address offset: 0x330       */

+ __IO uint32_t UR13;           /*!< SYSCFG user register 13,                            Address offset: 0x334       */

+ __IO uint32_t UR14;           /*!< SYSCFG user register 14,                            Address offset: 0x338       */

+ __IO uint32_t UR15;           /*!< SYSCFG user register 15,                            Address offset: 0x33C       */

+ __IO uint32_t UR16;           /*!< SYSCFG user register 16,                            Address offset: 0x340       */

+ __IO uint32_t UR17;           /*!< SYSCFG user register 17,                            Address offset: 0x344       */

+

+} SYSCFG_TypeDef;

+

+/**

+  * @brief Inter-integrated Circuit Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */

+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */

+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */

+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */

+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */

+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */

+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */

+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */

+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */

+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */

+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */

+} I2C_TypeDef;

+

+/**

+  * @brief Independent WATCHDOG

+  */

+

+typedef struct

+{

+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */

+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */

+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */

+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */

+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */

+} IWDG_TypeDef;

+

+

+

+/**

+  * @brief Power Control

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;       /*!< PWR power control register 1,            Address offset: 0x00 */

+  __IO uint32_t CSR1;      /*!< PWR power control status register 1,     Address offset: 0x04 */

+  __IO uint32_t CR2;       /*!< PWR power control register 2,            Address offset: 0x08 */

+  __IO uint32_t CR3;       /*!< PWR power control register 3,            Address offset: 0x0C */

+  __IO uint32_t CPUCR;     /*!< PWR CPU control register,                Address offset: 0x10 */

+       uint32_t RESERVED0; /*!< Reserved,                                Address offset: 0x14 */

+  __IO uint32_t D3CR;      /*!< PWR D3 domain control register,          Address offset: 0x18 */

+       uint32_t RESERVED1; /*!< Reserved,                                Address offset: 0x1C */

+  __IO uint32_t WKUPCR;    /*!< PWR wakeup clear register,               Address offset: 0x20 */

+  __IO uint32_t WKUPFR;    /*!< PWR wakeup flag register,                Address offset: 0x24 */

+  __IO uint32_t WKUPEPR;   /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */

+} PWR_TypeDef;

+

+/**

+  * @brief Reset and Clock Control

+  */

+

+typedef struct

+{

+ __IO uint32_t CR;             /*!< RCC clock control register,                                              Address offset: 0x00  */

+ __IO uint32_t HSICFGR;        /*!< HSI Clock Calibration Register,                                          Address offset: 0x04  */

+ __IO uint32_t CRRCR;          /*!< Clock Recovery RC  Register,                                             Address offset: 0x08  */

+ __IO uint32_t CSICFGR;        /*!< CSI Clock Calibration Register,                                          Address offset: 0x0C  */

+ __IO uint32_t CFGR;           /*!< RCC clock configuration register,                                        Address offset: 0x10  */

+ uint32_t     RESERVED1;       /*!< Reserved,                                                                Address offset: 0x14  */

+ __IO uint32_t D1CFGR;         /*!< RCC Domain 1 configuration register,                                     Address offset: 0x18  */

+ __IO uint32_t D2CFGR;         /*!< RCC Domain 2 configuration register,                                     Address offset: 0x1C  */

+ __IO uint32_t D3CFGR;         /*!< RCC Domain 3 configuration register,                                     Address offset: 0x20  */

+ uint32_t     RESERVED2;       /*!< Reserved,                                                                Address offset: 0x24  */

+ __IO uint32_t PLLCKSELR;      /*!< RCC PLLs Clock Source Selection Register,                                Address offset: 0x28  */

+ __IO uint32_t PLLCFGR;        /*!< RCC PLLs  Configuration Register,                                        Address offset: 0x2C  */

+ __IO uint32_t PLL1DIVR;       /*!< RCC PLL1 Dividers Configuration Register,                                Address offset: 0x30  */

+ __IO uint32_t PLL1FRACR;      /*!< RCC PLL1 Fractional Divider Configuration Register,                      Address offset: 0x34  */

+ __IO uint32_t PLL2DIVR;       /*!< RCC PLL2 Dividers Configuration Register,                                Address offset: 0x38  */

+ __IO uint32_t PLL2FRACR;      /*!< RCC PLL2 Fractional Divider Configuration Register,                      Address offset: 0x3C  */

+ __IO uint32_t PLL3DIVR;       /*!< RCC PLL3 Dividers Configuration Register,                                Address offset: 0x40  */

+ __IO uint32_t PLL3FRACR;      /*!< RCC PLL3 Fractional Divider Configuration Register,                      Address offset: 0x44  */

+ uint32_t      RESERVED3;      /*!< Reserved,                                                                Address offset: 0x48  */

+ __IO uint32_t  D1CCIPR;       /*!< RCC Domain 1 Kernel Clock Configuration Register                         Address offset: 0x4C  */

+ __IO uint32_t  D2CCIP1R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x50  */

+ __IO uint32_t  D2CCIP2R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x54  */

+ __IO uint32_t  D3CCIPR;       /*!< RCC Domain 3 Kernel Clock Configuration Register                         Address offset: 0x58  */

+ uint32_t      RESERVED4;      /*!< Reserved,                                                                Address offset: 0x5C  */

+ __IO uint32_t  CIER;          /*!< RCC Clock Source Interrupt Enable Register                               Address offset: 0x60  */

+ __IO uint32_t  CIFR;          /*!< RCC Clock Source Interrupt Flag Register                                 Address offset: 0x64  */

+ __IO uint32_t  CICR;          /*!< RCC Clock Source Interrupt Clear Register                                Address offset: 0x68  */

+ uint32_t     RESERVED5;       /*!< Reserved,                                                                Address offset: 0x6C  */

+ __IO uint32_t  BDCR;          /*!< RCC Vswitch Backup Domain Control Register,                              Address offset: 0x70  */

+ __IO uint32_t  CSR;           /*!< RCC clock control & status register,                                     Address offset: 0x74  */

+ uint32_t     RESERVED6;       /*!< Reserved,                                                                Address offset: 0x78  */

+ __IO uint32_t AHB3RSTR;       /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x7C  */

+ __IO uint32_t AHB1RSTR;       /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x80  */

+ __IO uint32_t AHB2RSTR;       /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x84  */

+ __IO uint32_t AHB4RSTR;       /*!< RCC AHB4 peripheral reset register,                                      Address offset: 0x88  */

+ __IO uint32_t APB3RSTR;       /*!< RCC APB3 peripheral reset register,                                      Address offset: 0x8C  */

+ __IO uint32_t APB1LRSTR;      /*!< RCC APB1 peripheral reset Low Word register,                             Address offset: 0x90  */

+ __IO uint32_t APB1HRSTR;      /*!< RCC APB1 peripheral reset High Word register,                            Address offset: 0x94  */

+ __IO uint32_t APB2RSTR;       /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x98  */

+ __IO uint32_t APB4RSTR;       /*!< RCC APB4 peripheral reset register,                                      Address offset: 0x9C  */

+ __IO uint32_t GCR;            /*!< RCC RCC Global Control  Register,                                        Address offset: 0xA0  */

+ uint32_t     RESERVED8;       /*!< Reserved,                                                                Address offset: 0xA4  */

+ __IO uint32_t D3AMR;          /*!< RCC Domain 3 Autonomous Mode Register,                                   Address offset: 0xA8  */

+ uint32_t     RESERVED11[9];    /*!< Reserved, 0xAC-0xCC                                                      Address offset: 0xAC  */

+ __IO uint32_t RSR;            /*!< RCC Reset status register,                                               Address offset: 0xD0  */

+ __IO uint32_t AHB3ENR;        /*!< RCC AHB3 peripheral clock  register,                                     Address offset: 0xD4  */

+ __IO uint32_t AHB1ENR;        /*!< RCC AHB1 peripheral clock  register,                                     Address offset: 0xD8  */

+ __IO uint32_t AHB2ENR;        /*!< RCC AHB2 peripheral clock  register,                                     Address offset: 0xDC  */

+ __IO uint32_t AHB4ENR;        /*!< RCC AHB4 peripheral clock  register,                                     Address offset: 0xE0  */

+ __IO uint32_t APB3ENR;        /*!< RCC APB3 peripheral clock  register,                                     Address offset: 0xE4  */

+ __IO uint32_t APB1LENR;       /*!< RCC APB1 peripheral clock  Low Word register,                            Address offset: 0xE8  */

+ __IO uint32_t APB1HENR;       /*!< RCC APB1 peripheral clock  High Word register,                           Address offset: 0xEC  */

+ __IO uint32_t APB2ENR;        /*!< RCC APB2 peripheral clock  register,                                     Address offset: 0xF0  */

+ __IO uint32_t APB4ENR;        /*!< RCC APB4 peripheral clock  register,                                     Address offset: 0xF4  */

+ uint32_t      RESERVED12;      /*!< Reserved,                                                                Address offset: 0xF8  */

+ __IO uint32_t AHB3LPENR;      /*!< RCC AHB3 peripheral sleep clock  register,                               Address offset: 0xFC  */

+ __IO uint32_t AHB1LPENR;      /*!< RCC AHB1 peripheral sleep clock  register,                               Address offset: 0x100 */

+ __IO uint32_t AHB2LPENR;      /*!< RCC AHB2 peripheral sleep clock  register,                               Address offset: 0x104 */

+ __IO uint32_t AHB4LPENR;      /*!< RCC AHB4 peripheral sleep clock  register,                               Address offset: 0x108 */

+ __IO uint32_t APB3LPENR;      /*!< RCC APB3 peripheral sleep clock  register,                               Address offset: 0x10C */

+ __IO uint32_t APB1LLPENR;     /*!< RCC APB1 peripheral sleep clock  Low Word register,                      Address offset: 0x110 */

+ __IO uint32_t APB1HLPENR;     /*!< RCC APB1 peripheral sleep clock  High Word register,                     Address offset: 0x114 */

+ __IO uint32_t APB2LPENR;      /*!< RCC APB2 peripheral sleep clock  register,                               Address offset: 0x118 */

+ __IO uint32_t APB4LPENR;      /*!< RCC APB4 peripheral sleep clock  register,                               Address offset: 0x11C */

+ uint32_t     RESERVED13[4];   /*!< Reserved, 0x120-0x12C                                                    Address offset: 0x120 */

+

+} RCC_TypeDef;

+

+

+/**

+  * @brief Real-Time Clock

+  */

+typedef struct

+{

+  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */

+  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */

+  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */

+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */

+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */

+  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */

+       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */

+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */

+  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */

+  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */

+  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */

+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */

+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */

+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */

+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */

+  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */

+  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */

+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */

+  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */

+  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset: 0x4C */

+  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */

+  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */

+  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */

+  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */

+  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */

+  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */

+  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */

+  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */

+  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */

+  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */

+  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */

+  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */

+  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */

+  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */

+  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */

+  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */

+  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */

+  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */

+  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */

+  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */

+  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */

+  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */

+  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */

+  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */

+  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */

+  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */

+  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */

+  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */

+  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */

+  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */

+  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */

+  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */

+} RTC_TypeDef;

+

+/**

+  * @brief Serial Audio Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t GCR;           /*!< SAI global configuration register, Address offset: 0x00 */

+  uint32_t      RESERVED0[16]; /*!< Reserved, 0x04 - 0x43                                   */

+  __IO uint32_t PDMCR;         /*!< SAI PDM control register,          Address offset: 0x44 */

+  __IO uint32_t PDMDLY;        /*!< SAI PDM delay register,            Address offset: 0x48 */

+} SAI_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */

+  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */

+  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */

+  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */

+  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */

+  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */

+  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */

+  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */

+} SAI_Block_TypeDef;

+

+/**

+  * @brief SPDIF-RX Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */

+  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */

+  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */

+  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */

+  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */

+  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */

+  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */

+  uint32_t        RESERVED2;    /*!< Reserved,  0x1A                                          */

+} SPDIFRX_TypeDef;

+

+

+/**

+  * @brief Secure digital input/output Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t POWER;          /*!< SDMMC power control register,             Address offset: 0x00  */

+  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,             Address offset: 0x04  */

+  __IO uint32_t ARG;            /*!< SDMMC argument register,                  Address offset: 0x08  */

+  __IO uint32_t CMD;            /*!< SDMMC command register,                   Address offset: 0x0C  */

+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register,          Address offset: 0x10  */

+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                Address offset: 0x14  */

+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                Address offset: 0x18  */

+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                Address offset: 0x1C  */

+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                Address offset: 0x20  */

+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                Address offset: 0x24  */

+  __IO uint32_t DLEN;           /*!< SDMMC data length register,               Address offset: 0x28  */

+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,              Address offset: 0x2C  */

+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,              Address offset: 0x30  */

+  __I uint32_t  STA;            /*!< SDMMC status register,                    Address offset: 0x34  */

+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,           Address offset: 0x38  */

+  __IO uint32_t MASK;           /*!< SDMMC mask register,                      Address offset: 0x3C  */

+  __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,     Address offset: 0x40  */

+  uint32_t      RESERVED0[3];   /*!< Reserved, 0x44 - 0x4C - 0x4C                                    */

+  __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,               Address offset: 0x50  */

+  __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,           Address offset: 0x54  */

+  __IO uint32_t IDMABASE0;      /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58  */

+  __IO uint32_t IDMABASE1;      /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C  */

+  uint32_t      RESERVED1[8];   /*!< Reserved, 0x60-0x7C                                             */

+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,                 Address offset: 0x80  */

+  uint32_t      RESERVED2[222]; /*!< Reserved, 0x84-0x3F8                                            */

+  __IO uint32_t IPVR;           /*!< SDMMC data FIFO register,                 Address offset: 0x3FC */

+} SDMMC_TypeDef;

+

+

+/**

+  * @brief Delay Block DLYB

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;          /*!< DELAY BLOCK control register,  Address offset: 0x00 */

+  __IO uint32_t CFGR;        /*!< DELAY BLOCK configuration register,  Address offset: 0x04 */

+} DLYB_TypeDef;

+

+/**

+  * @brief HW Semaphore HSEM

+  */

+

+typedef struct

+{

+  __IO uint32_t R[32];      /*!< 2-step write lock and read back registers,     Address offset: 00h-7Ch  */

+  __IO uint32_t RLR[32];    /*!< 1-step read lock registers,                    Address offset: 80h-FCh  */

+  __IO uint32_t C1IER;      /*!< HSEM Interrupt enable register ,             Address offset: 100h     */

+  __IO uint32_t C1ICR;      /*!< HSEM Interrupt clear register ,              Address offset: 104h     */

+  __IO uint32_t C1ISR;      /*!< HSEM Interrupt Status register ,             Address offset: 108h     */

+  __IO uint32_t C1MISR;     /*!< HSEM Interrupt Masked Status register ,      Address offset: 10Ch     */

+  uint32_t  Reserved[12];   /* Reserved                                       Address offset: 110h-13Ch  */

+  __IO uint32_t CR;         /*!< HSEM Semaphore clear register ,                Address offset: 140h      */

+  __IO uint32_t KEYR;       /*!< HSEM Semaphore clear key register ,            Address offset: 144h      */

+

+} HSEM_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t IER;        /*!< HSEM interrupt enable register ,                Address offset:   0h     */

+  __IO uint32_t ICR;        /*!< HSEM interrupt clear register ,                 Address offset:   4h     */

+  __IO uint32_t ISR;        /*!< HSEM interrupt status register ,                Address offset:   8h     */

+  __IO uint32_t MISR;       /*!< HSEM masked interrupt status register ,         Address offset:   Ch     */

+} HSEM_Common_TypeDef;

+

+/**

+  * @brief Serial Peripheral Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */

+  __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */

+  __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */

+  __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */

+  __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */

+  __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */

+  __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */

+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */

+  __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */

+  uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */

+  __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */

+  uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */

+  __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */

+  __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */

+  __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */

+  __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */

+  __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */

+

+} SPI_TypeDef;

+/**

+  * @brief QUAD Serial Peripheral Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */

+  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */

+  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */

+  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */

+  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */

+  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */

+  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */

+  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */

+  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */

+  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */

+  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */

+  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */

+  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */

+} QUADSPI_TypeDef;

+

+/**

+  * @brief TIM

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */

+  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */

+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */

+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */

+  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */

+  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */

+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */

+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */

+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */

+  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */

+  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */

+  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */

+  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */

+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */

+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */

+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */

+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */

+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */

+  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */

+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */

+  uint32_t      RESERVED1;   /*!< Reserved, 0x50                                                 */

+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */

+  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */

+  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */

+  __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */

+  __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */

+  __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x68 */

+} TIM_TypeDef;

+

+/**

+  * @brief LPTIMIMER

+  */

+typedef struct

+{

+  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,         Address offset: 0x00 */

+  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,              Address offset: 0x04 */

+  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,             Address offset: 0x08 */

+  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                Address offset: 0x0C */

+  __IO uint32_t CR;       /*!< LPTIM Control register,                      Address offset: 0x10 */

+  __IO uint32_t CMP;      /*!< LPTIM Compare register,                      Address offset: 0x14 */

+  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                   Address offset: 0x18 */

+  __IO uint32_t CNT;      /*!< LPTIM Counter register,                      Address offset: 0x1C */

+  uint32_t  RESERVED1;    /*!< Reserved, 0x20                                                    */

+  __IO uint32_t CFGR2;    /*!< LPTIM Configuration register,                Address offset: 0x24 */

+} LPTIM_TypeDef;

+

+/**

+  * @brief Comparator

+  */

+typedef struct

+{

+  __IO uint32_t SR;        /*!< Comparator status register,                    Address offset: 0x00 */

+  __IO uint32_t ICFR;      /*!< Comparator interrupt clear flag register,       Address offset: 0x04 */

+  __IO uint32_t OR;        /*!< Comparator option register,                  Address offset: 0x08 */

+} COMPOPT_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CFGR;      /*!< Comparator configuration register  ,           Address offset: 0x00 */

+} COMP_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CFGR;       /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */

+} COMP_Common_TypeDef;

+/**

+  * @brief Universal Synchronous Asynchronous Receiver Transmitter

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */

+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */

+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */

+  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */

+  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */

+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */

+  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */

+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */

+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */

+  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */

+  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */

+  __IO uint32_t PRESC;  /*!< USART clock Prescaler register,           Address offset: 0x2C */

+} USART_TypeDef;

+

+/**

+  * @brief Single Wire Protocol Master Interface SPWMI

+  */

+typedef struct

+{

+  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */

+  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */

+    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */

+  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */

+  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */

+  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */

+  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */

+  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */

+  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */

+  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */

+} SWPMI_TypeDef;

+

+/**

+  * @brief Window WATCHDOG

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */

+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */

+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */

+} WWDG_TypeDef;

+

+

+/**

+  * @brief RAM_ECC_Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t CR;           /*!< RAMECC monitor configuration register          */

+  __IO uint32_t SR;           /*!< RAMECC monitor status register                 */

+  __IO uint32_t FAR;          /*!< RAMECC monitor failing address register        */

+  __IO uint32_t FDRL;         /*!< RAMECC monitor failing data low register       */

+  __IO uint32_t FDRH;         /*!< RAMECC monitor failing data high register      */

+  __IO uint32_t FECR;         /*!< RAMECC monitor failing ECC error code register */

+} RAMECC_MonitorTypeDef;

+

+typedef struct

+{

+  __IO uint32_t IER;          /*!< RAMECC interrupt enable register */

+} RAMECC_TypeDef;

+/**

+  * @}

+  */

+

+

+

+/**

+  * @brief High resolution Timer (HRTIM)

+  */

+/* HRTIM master registers definition */

+typedef struct

+{

+  __IO uint32_t MCR;            /*!< HRTIM Master Timer control register,                     Address offset: 0x00 */

+  __IO uint32_t MISR;           /*!< HRTIM Master Timer interrupt status register,            Address offset: 0x04 */

+  __IO uint32_t MICR;           /*!< HRTIM Master Timer interupt clear register,              Address offset: 0x08 */

+  __IO uint32_t MDIER;          /*!< HRTIM Master Timer DMA/interrupt enable register         Address offset: 0x0C */

+  __IO uint32_t MCNTR;          /*!< HRTIM Master Timer counter register,                     Address offset: 0x10 */

+  __IO uint32_t MPER;           /*!< HRTIM Master Timer period register,                      Address offset: 0x14 */

+  __IO uint32_t MREP;           /*!< HRTIM Master Timer repetition register,                  Address offset: 0x18 */

+  __IO uint32_t MCMP1R;         /*!< HRTIM Master Timer compare 1 register,                   Address offset: 0x1C */

+  uint32_t      RESERVED0;     /*!< Reserved,                                                                 0x20 */

+  __IO uint32_t MCMP2R;         /*!< HRTIM Master Timer compare 2 register,                   Address offset: 0x24 */

+  __IO uint32_t MCMP3R;         /*!< HRTIM Master Timer compare 3 register,                   Address offset: 0x28 */

+  __IO uint32_t MCMP4R;         /*!< HRTIM Master Timer compare 4 register,                   Address offset: 0x2C */

+  uint32_t      RESERVED1[20];  /*!< Reserved,                                                          0x30..0x7C */

+}HRTIM_Master_TypeDef;

+

+/* HRTIM Timer A to E registers definition */

+typedef struct

+{

+  __IO uint32_t TIMxCR;     /*!< HRTIM Timerx control register,                              Address offset: 0x00 */

+  __IO uint32_t TIMxISR;    /*!< HRTIM Timerx interrupt status register,                     Address offset: 0x04 */

+  __IO uint32_t TIMxICR;    /*!< HRTIM Timerx interrupt clear register,                      Address offset: 0x08 */

+  __IO uint32_t TIMxDIER;   /*!< HRTIM Timerx DMA/interrupt enable register,                 Address offset: 0x0C */

+  __IO uint32_t CNTxR;      /*!< HRTIM Timerx counter register,                              Address offset: 0x10 */

+  __IO uint32_t PERxR;      /*!< HRTIM Timerx period register,                               Address offset: 0x14 */

+  __IO uint32_t REPxR;      /*!< HRTIM Timerx repetition register,                           Address offset: 0x18 */

+  __IO uint32_t CMP1xR;     /*!< HRTIM Timerx compare 1 register,                            Address offset: 0x1C */

+  __IO uint32_t CMP1CxR;    /*!< HRTIM Timerx compare 1 compound register,                   Address offset: 0x20 */

+  __IO uint32_t CMP2xR;     /*!< HRTIM Timerx compare 2 register,                            Address offset: 0x24 */

+  __IO uint32_t CMP3xR;     /*!< HRTIM Timerx compare 3 register,                            Address offset: 0x28 */

+  __IO uint32_t CMP4xR;     /*!< HRTIM Timerx compare 4 register,                            Address offset: 0x2C */

+  __IO uint32_t CPT1xR;     /*!< HRTIM Timerx capture 1 register,                            Address offset: 0x30 */

+  __IO uint32_t CPT2xR;     /*!< HRTIM Timerx capture 2 register,                            Address offset: 0x34 */

+  __IO uint32_t DTxR;       /*!< HRTIM Timerx dead time register,                            Address offset: 0x38 */

+  __IO uint32_t SETx1R;     /*!< HRTIM Timerx output 1 set register,                         Address offset: 0x3C */

+  __IO uint32_t RSTx1R;     /*!< HRTIM Timerx output 1 reset register,                       Address offset: 0x40 */

+  __IO uint32_t SETx2R;     /*!< HRTIM Timerx output 2 set register,                         Address offset: 0x44 */

+  __IO uint32_t RSTx2R;     /*!< HRTIM Timerx output 2 reset register,                       Address offset: 0x48 */

+  __IO uint32_t EEFxR1;     /*!< HRTIM Timerx external event filtering 1 register,           Address offset: 0x4C */

+  __IO uint32_t EEFxR2;     /*!< HRTIM Timerx external event filtering 2 register,           Address offset: 0x50 */

+  __IO uint32_t RSTxR;      /*!< HRTIM Timerx Reset register,                                Address offset: 0x54 */

+  __IO uint32_t CHPxR;      /*!< HRTIM Timerx Chopper register,                              Address offset: 0x58 */

+  __IO uint32_t CPT1xCR;    /*!< HRTIM Timerx Capture 1 register,                            Address offset: 0x5C */

+  __IO uint32_t CPT2xCR;    /*!< HRTIM Timerx Capture 2 register,                            Address offset: 0x60 */

+  __IO uint32_t OUTxR;      /*!< HRTIM Timerx Output register,                               Address offset: 0x64 */

+  __IO uint32_t FLTxR;      /*!< HRTIM Timerx Fault register,                                Address offset: 0x68 */

+  uint32_t      RESERVED0[5];  /*!< Reserved,                                                          0x6C..0x7C */

+}HRTIM_Timerx_TypeDef;

+

+/* HRTIM common register definition */

+typedef struct

+{

+  __IO uint32_t CR1;        /*!< HRTIM control register1,                                    Address offset: 0x00 */

+  __IO uint32_t CR2;        /*!< HRTIM control register2,                                    Address offset: 0x04 */

+  __IO uint32_t ISR;        /*!< HRTIM interrupt status register,                            Address offset: 0x08 */

+  __IO uint32_t ICR;        /*!< HRTIM interrupt clear register,                             Address offset: 0x0C */

+  __IO uint32_t IER;        /*!< HRTIM interrupt enable register,                            Address offset: 0x10 */

+  __IO uint32_t OENR;       /*!< HRTIM Output enable register,                               Address offset: 0x14 */

+  __IO uint32_t ODISR;      /*!< HRTIM Output disable register,                              Address offset: 0x18 */

+  __IO uint32_t ODSR;       /*!< HRTIM Output disable status register,                       Address offset: 0x1C */

+  __IO uint32_t BMCR;       /*!< HRTIM Burst mode control register,                          Address offset: 0x20 */

+  __IO uint32_t BMTRGR;     /*!< HRTIM Busrt mode trigger register,                          Address offset: 0x24 */

+  __IO uint32_t BMCMPR;     /*!< HRTIM Burst mode compare register,                          Address offset: 0x28 */

+  __IO uint32_t BMPER;      /*!< HRTIM Burst mode period register,                           Address offset: 0x2C */

+  __IO uint32_t EECR1;      /*!< HRTIM Timer external event control register1,               Address offset: 0x30 */

+  __IO uint32_t EECR2;      /*!< HRTIM Timer external event control register2,               Address offset: 0x34 */

+  __IO uint32_t EECR3;      /*!< HRTIM Timer external event control register3,               Address offset: 0x38 */

+  __IO uint32_t ADC1R;      /*!< HRTIM ADC Trigger 1 register,                               Address offset: 0x3C */

+  __IO uint32_t ADC2R;      /*!< HRTIM ADC Trigger 2 register,                               Address offset: 0x40 */

+  __IO uint32_t ADC3R;      /*!< HRTIM ADC Trigger 3 register,                               Address offset: 0x44 */

+  __IO uint32_t ADC4R;      /*!< HRTIM ADC Trigger 4 register,                               Address offset: 0x48 */

+  __IO uint32_t RESERVED0;  /*!< Reserved,                                                   Address offset: 0x4C */

+  __IO uint32_t FLTINR1;    /*!< HRTIM Fault input register1,                                Address offset: 0x50 */

+  __IO uint32_t FLTINR2;    /*!< HRTIM Fault input register2,                                Address offset: 0x54 */

+  __IO uint32_t BDMUPR;     /*!< HRTIM Burst DMA Master Timer update register,               Address offset: 0x58 */

+  __IO uint32_t BDTAUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x5C */

+  __IO uint32_t BDTBUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x60 */

+  __IO uint32_t BDTCUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x64 */

+  __IO uint32_t BDTDUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x68 */

+  __IO uint32_t BDTEUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x6C */

+  __IO uint32_t BDMADR;     /*!< HRTIM Burst DMA Master Data register,                       Address offset: 0x70 */

+}HRTIM_Common_TypeDef;

+

+/* HRTIM  register definition */

+typedef struct {

+  HRTIM_Master_TypeDef sMasterRegs;

+  HRTIM_Timerx_TypeDef sTimerxRegs[5];

+  uint32_t             RESERVED0[32];

+  HRTIM_Common_TypeDef sCommonRegs;

+}HRTIM_TypeDef;

+/**

+  * @brief RNG

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */

+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */

+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */

+} RNG_TypeDef;

+

+/**

+  * @brief MDIOS

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;

+  __IO uint32_t WRFR;

+  __IO uint32_t CWRFR;

+  __IO uint32_t RDFR;

+  __IO uint32_t CRDFR;

+  __IO uint32_t SR;

+  __IO uint32_t CLRFR;

+  uint32_t RESERVED[57];

+  __IO uint32_t DINR0;

+  __IO uint32_t DINR1;

+  __IO uint32_t DINR2;

+  __IO uint32_t DINR3;

+  __IO uint32_t DINR4;

+  __IO uint32_t DINR5;

+  __IO uint32_t DINR6;

+  __IO uint32_t DINR7;

+  __IO uint32_t DINR8;

+  __IO uint32_t DINR9;

+  __IO uint32_t DINR10;

+  __IO uint32_t DINR11;

+  __IO uint32_t DINR12;

+  __IO uint32_t DINR13;

+  __IO uint32_t DINR14;

+  __IO uint32_t DINR15;

+  __IO uint32_t DINR16;

+  __IO uint32_t DINR17;

+  __IO uint32_t DINR18;

+  __IO uint32_t DINR19;

+  __IO uint32_t DINR20;

+  __IO uint32_t DINR21;

+  __IO uint32_t DINR22;

+  __IO uint32_t DINR23;

+  __IO uint32_t DINR24;

+  __IO uint32_t DINR25;

+  __IO uint32_t DINR26;

+  __IO uint32_t DINR27;

+  __IO uint32_t DINR28;

+  __IO uint32_t DINR29;

+  __IO uint32_t DINR30;

+  __IO uint32_t DINR31;

+  __IO uint32_t DOUTR0;

+  __IO uint32_t DOUTR1;

+  __IO uint32_t DOUTR2;

+  __IO uint32_t DOUTR3;

+  __IO uint32_t DOUTR4;

+  __IO uint32_t DOUTR5;

+  __IO uint32_t DOUTR6;

+  __IO uint32_t DOUTR7;

+  __IO uint32_t DOUTR8;

+  __IO uint32_t DOUTR9;

+  __IO uint32_t DOUTR10;

+  __IO uint32_t DOUTR11;

+  __IO uint32_t DOUTR12;

+  __IO uint32_t DOUTR13;

+  __IO uint32_t DOUTR14;

+  __IO uint32_t DOUTR15;

+  __IO uint32_t DOUTR16;

+  __IO uint32_t DOUTR17;

+  __IO uint32_t DOUTR18;

+  __IO uint32_t DOUTR19;

+  __IO uint32_t DOUTR20;

+  __IO uint32_t DOUTR21;

+  __IO uint32_t DOUTR22;

+  __IO uint32_t DOUTR23;

+  __IO uint32_t DOUTR24;

+  __IO uint32_t DOUTR25;

+  __IO uint32_t DOUTR26;

+  __IO uint32_t DOUTR27;

+  __IO uint32_t DOUTR28;

+  __IO uint32_t DOUTR29;

+  __IO uint32_t DOUTR30;

+  __IO uint32_t DOUTR31;

+} MDIOS_TypeDef;

+

+

+/**

+  * @brief USB_OTG_Core_Registers

+  */

+typedef struct

+{

+ __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */

+  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */

+  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */

+  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */

+  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */

+  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */

+  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */

+  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */

+  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */

+  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */

+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */

+  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */

+  uint32_t Reserved30[2];             /*!< Reserved                                     030h */

+  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */

+  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */

+  __IO uint32_t GSNPSID;              /* USB_OTG core ID                                040h*/

+  __IO uint32_t GHWCFG1;              /* User HW config1                                044h*/

+  __IO uint32_t GHWCFG2;              /* User HW config2                                048h*/

+  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */

+  uint32_t  Reserved6;                /*!< Reserved                                     050h */

+  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */

+  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */

+  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */

+   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */

+    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */

+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */

+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */

+} USB_OTG_GlobalTypeDef;

+

+

+/**

+  * @brief USB_OTG_device_Registers

+  */

+typedef struct

+{

+  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */

+  __IO uint32_t DCTL;            /*!< dev Control Register         804h */

+  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */

+  uint32_t Reserved0C;           /*!< Reserved                     80Ch */

+  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */

+  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */

+  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */

+  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */

+  uint32_t  Reserved20;          /*!< Reserved                     820h */

+  uint32_t Reserved9;            /*!< Reserved                     824h */

+  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */

+  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */

+  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */

+  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */

+  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */

+  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */

+  uint32_t Reserved40;           /*!< dedicated EP mask            840h */

+  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */

+  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */

+  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */

+} USB_OTG_DeviceTypeDef;

+

+

+/**

+  * @brief USB_OTG_IN_Endpoint-Specific_Register

+  */

+typedef struct

+{

+  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */

+  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */

+  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */

+  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */

+  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */

+  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */

+  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */

+  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */

+} USB_OTG_INEndpointTypeDef;

+

+

+/**

+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */

+  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */

+  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */

+  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */

+  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */

+  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */

+  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */

+} USB_OTG_OUTEndpointTypeDef;

+

+

+/**

+  * @brief USB_OTG_Host_Mode_Register_Structures

+  */

+typedef struct

+{

+  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */

+  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */

+  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */

+  uint32_t Reserved40C;           /*!< Reserved                             40Ch */

+  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */

+  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */

+  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */

+} USB_OTG_HostTypeDef;

+

+/**

+  * @brief USB_OTG_Host_Channel_Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */

+  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */

+  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */

+  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */

+  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */

+  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */

+  uint32_t Reserved[2];           /*!< Reserved                                      */

+} USB_OTG_HostChannelTypeDef;

+/**

+  * @}

+  */

+

+

+/** @addtogroup Peripheral_memory_map

+  * @{

+  */

+#define D1_ITCMRAM_BASE           (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM  */

+#define D1_ITCMICP_BASE           (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM         */

+#define D1_DTCMRAM_BASE           (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM                            */

+#define D1_AXIFLASH_BASE          (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI                */

+#define D1_AXIICP_BASE            (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI          */

+#define D1_AXISRAM_BASE           (0x24000000UL) /*!< Base address of : (up to 384KB) system data RAM accessible over over AXI                */

+

+#define D2_AXISRAM_BASE           (0x10000000UL) /*!< Base address of : (up to 48KB) system data RAM accessible over over AXI                */

+#define D2_AHBSRAM_BASE           (0x30000000UL) /*!< Base address of : (up to 48KB) system data RAM accessible over over AXI->AHB Bridge    */

+

+#define D3_BKPSRAM_BASE           (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge                                */

+#define D3_SRAM_BASE              (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge                               */

+

+#define PERIPH_BASE               (0x40000000UL) /*!< Base address of : AHB/APB Peripherals                                                   */

+#define QSPI_BASE                 (0x90000000UL) /*!< Base address of : QSPI memories  accessible over AXI                                    */

+

+#define FLASH_BANK1_BASE          (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI                          */

+#define FLASH_BANK2_BASE          (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI                          */

+#define FLASH_END                 (0x081FFFFFUL) /*!< FLASH end address                                                                       */

+

+/* Legacy define */

+#define FLASH_BASE                FLASH_BANK1_BASE

+

+/*!< Device electronic signature memory map */

+#define UID_BASE                  (0x1FF1E800UL)            /*!< Unique device ID register base address */

+#define FLASHSIZE_BASE            (0x1FF1E880UL)            /*!< FLASH Size register base address */

+

+

+/*!< Peripheral memory map */

+#define D2_APB1PERIPH_BASE        PERIPH_BASE

+#define D2_APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)

+#define D2_AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)

+#define D2_AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)

+

+#define D1_APB1PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)

+#define D1_AHB1PERIPH_BASE       (PERIPH_BASE + 0x12000000UL)

+

+#define D3_APB1PERIPH_BASE       (PERIPH_BASE + 0x18000000UL)

+#define D3_AHB1PERIPH_BASE       (PERIPH_BASE + 0x18020000UL)

+

+/*!< Legacy Peripheral memory map */

+#define APB1PERIPH_BASE        PERIPH_BASE

+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)

+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)

+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)

+

+

+/*!< D1_AHB1PERIPH peripherals */

+

+#define MDMA_BASE             (D1_AHB1PERIPH_BASE + 0x0000UL)

+#define DMA2D_BASE            (D1_AHB1PERIPH_BASE + 0x1000UL)

+#define FLASH_R_BASE          (D1_AHB1PERIPH_BASE + 0x2000UL)

+#define FMC_R_BASE            (D1_AHB1PERIPH_BASE + 0x4000UL)

+#define QSPI_R_BASE           (D1_AHB1PERIPH_BASE + 0x5000UL)

+#define DLYB_QSPI_BASE        (D1_AHB1PERIPH_BASE + 0x6000UL)

+#define SDMMC1_BASE           (D1_AHB1PERIPH_BASE + 0x7000UL)

+#define DLYB_SDMMC1_BASE      (D1_AHB1PERIPH_BASE + 0x8000UL)

+#define RAMECC1_BASE          (D1_AHB1PERIPH_BASE + 0x9000UL)

+

+/*!< D2_AHB1PERIPH peripherals */

+

+#define DMA1_BASE               (D2_AHB1PERIPH_BASE + 0x0000UL)

+#define DMA2_BASE               (D2_AHB1PERIPH_BASE + 0x0400UL)

+#define DMAMUX1_BASE            (D2_AHB1PERIPH_BASE + 0x0800UL)

+#define ADC1_BASE               (D2_AHB1PERIPH_BASE + 0x2000UL)

+#define ADC2_BASE               (D2_AHB1PERIPH_BASE + 0x2100UL)

+#define ADC12_COMMON_BASE       (D2_AHB1PERIPH_BASE + 0x2300UL)

+#define ETH_BASE                (D2_AHB1PERIPH_BASE + 0x8000UL)

+#define ETH_MAC_BASE            (ETH_BASE)

+

+/*!< USB registers base address */

+#define USB1_OTG_HS_PERIPH_BASE              (0x40040000UL)

+#define USB2_OTG_FS_PERIPH_BASE              (0x40080000UL)

+#define USB_OTG_GLOBAL_BASE                  (0x000UL)

+#define USB_OTG_DEVICE_BASE                  (0x800UL)

+#define USB_OTG_IN_ENDPOINT_BASE             (0x900UL)

+#define USB_OTG_OUT_ENDPOINT_BASE            (0xB00UL)

+#define USB_OTG_EP_REG_SIZE                  (0x20UL)

+#define USB_OTG_HOST_BASE                    (0x400UL)

+#define USB_OTG_HOST_PORT_BASE               (0x440UL)

+#define USB_OTG_HOST_CHANNEL_BASE            (0x500UL)

+#define USB_OTG_HOST_CHANNEL_SIZE            (0x20UL)

+#define USB_OTG_PCGCCTL_BASE                 (0xE00UL)

+#define USB_OTG_FIFO_BASE                    (0x1000UL)

+#define USB_OTG_FIFO_SIZE                    (0x1000UL)

+

+/*!< D2_AHB2PERIPH peripherals */

+

+#define DCMI_BASE              (D2_AHB2PERIPH_BASE + 0x0000UL)

+#define RNG_BASE               (D2_AHB2PERIPH_BASE + 0x1800UL)

+#define SDMMC2_BASE            (D2_AHB2PERIPH_BASE + 0x2400UL)

+#define DLYB_SDMMC2_BASE       (D2_AHB2PERIPH_BASE + 0x2800UL)

+#define RAMECC2_BASE           (D2_AHB2PERIPH_BASE + 0x3000UL)

+

+/*!< D3_AHB1PERIPH peripherals */

+#define GPIOA_BASE            (D3_AHB1PERIPH_BASE + 0x0000UL)

+#define GPIOB_BASE            (D3_AHB1PERIPH_BASE + 0x0400UL)

+#define GPIOC_BASE            (D3_AHB1PERIPH_BASE + 0x0800UL)

+#define GPIOD_BASE            (D3_AHB1PERIPH_BASE + 0x0C00UL)

+#define GPIOE_BASE            (D3_AHB1PERIPH_BASE + 0x1000UL)

+#define GPIOF_BASE            (D3_AHB1PERIPH_BASE + 0x1400UL)

+#define GPIOG_BASE            (D3_AHB1PERIPH_BASE + 0x1800UL)

+#define GPIOH_BASE            (D3_AHB1PERIPH_BASE + 0x1C00UL)

+#define GPIOI_BASE            (D3_AHB1PERIPH_BASE + 0x2000UL)

+#define GPIOJ_BASE            (D3_AHB1PERIPH_BASE + 0x2400UL)

+#define GPIOK_BASE            (D3_AHB1PERIPH_BASE + 0x2800UL)

+#define RCC_BASE              (D3_AHB1PERIPH_BASE + 0x4400UL)

+#define PWR_BASE              (D3_AHB1PERIPH_BASE + 0x4800UL)

+#define CRC_BASE              (D3_AHB1PERIPH_BASE + 0x4C00UL)

+#define BDMA_BASE             (D3_AHB1PERIPH_BASE + 0x5400UL)

+#define DMAMUX2_BASE          (D3_AHB1PERIPH_BASE + 0x5800UL)

+#define ADC3_BASE             (D3_AHB1PERIPH_BASE + 0x6000UL)

+#define ADC3_COMMON_BASE      (D3_AHB1PERIPH_BASE + 0x6300UL)

+#define HSEM_BASE             (D3_AHB1PERIPH_BASE + 0x6400UL)

+#define RAMECC3_BASE          (D3_AHB1PERIPH_BASE + 0x7000UL)

+

+/*!< D1_APB1PERIPH peripherals */

+#define WWDG1_BASE            (D1_APB1PERIPH_BASE + 0x3000UL)

+

+/*!< D2_APB1PERIPH peripherals */

+#define TIM2_BASE             (D2_APB1PERIPH_BASE + 0x0000UL)

+#define TIM3_BASE             (D2_APB1PERIPH_BASE + 0x0400UL)

+#define TIM4_BASE             (D2_APB1PERIPH_BASE + 0x0800UL)

+#define TIM5_BASE             (D2_APB1PERIPH_BASE + 0x0C00UL)

+#define TIM6_BASE             (D2_APB1PERIPH_BASE + 0x1000UL)

+#define TIM7_BASE             (D2_APB1PERIPH_BASE + 0x1400UL)

+#define TIM12_BASE            (D2_APB1PERIPH_BASE + 0x1800UL)

+#define TIM13_BASE            (D2_APB1PERIPH_BASE + 0x1C00UL)

+#define TIM14_BASE            (D2_APB1PERIPH_BASE + 0x2000UL)

+#define LPTIM1_BASE           (D2_APB1PERIPH_BASE + 0x2400UL)

+

+

+#define SPI2_BASE             (D2_APB1PERIPH_BASE + 0x3800UL)

+#define SPI3_BASE             (D2_APB1PERIPH_BASE + 0x3C00UL)

+#define SPDIFRX_BASE          (D2_APB1PERIPH_BASE + 0x4000UL)

+#define USART2_BASE           (D2_APB1PERIPH_BASE + 0x4400UL)

+#define USART3_BASE           (D2_APB1PERIPH_BASE + 0x4800UL)

+#define UART4_BASE            (D2_APB1PERIPH_BASE + 0x4C00UL)

+#define UART5_BASE            (D2_APB1PERIPH_BASE + 0x5000UL)

+#define I2C1_BASE             (D2_APB1PERIPH_BASE + 0x5400UL)

+#define I2C2_BASE             (D2_APB1PERIPH_BASE + 0x5800UL)

+#define I2C3_BASE             (D2_APB1PERIPH_BASE + 0x5C00UL)

+#define CEC_BASE              (D2_APB1PERIPH_BASE + 0x6C00UL)

+#define DAC1_BASE             (D2_APB1PERIPH_BASE + 0x7400UL)

+#define UART7_BASE            (D2_APB1PERIPH_BASE + 0x7800UL)

+#define UART8_BASE            (D2_APB1PERIPH_BASE + 0x7C00UL)

+#define CRS_BASE              (D2_APB1PERIPH_BASE + 0x8400UL)

+#define SWPMI1_BASE           (D2_APB1PERIPH_BASE + 0x8800UL)

+#define OPAMP_BASE            (D2_APB1PERIPH_BASE + 0x9000UL)

+#define OPAMP1_BASE           (D2_APB1PERIPH_BASE + 0x9000UL)

+#define OPAMP2_BASE           (D2_APB1PERIPH_BASE + 0x9010UL)

+#define MDIOS_BASE            (D2_APB1PERIPH_BASE + 0x9400UL)

+#define FDCAN1_BASE           (D2_APB1PERIPH_BASE + 0xA000UL)

+#define FDCAN2_BASE           (D2_APB1PERIPH_BASE + 0xA400UL)

+#define FDCAN_CCU_BASE        (D2_APB1PERIPH_BASE + 0xA800UL)

+#define SRAMCAN_BASE          (D2_APB1PERIPH_BASE + 0xAC00UL)

+

+/*!< D2_APB2PERIPH peripherals */

+

+#define TIM1_BASE             (D2_APB2PERIPH_BASE + 0x0000UL)

+#define TIM8_BASE             (D2_APB2PERIPH_BASE + 0x0400UL)

+#define USART1_BASE           (D2_APB2PERIPH_BASE + 0x1000UL)

+#define USART6_BASE           (D2_APB2PERIPH_BASE + 0x1400UL)

+#define SPI1_BASE             (D2_APB2PERIPH_BASE + 0x3000UL)

+#define SPI4_BASE             (D2_APB2PERIPH_BASE + 0x3400UL)

+#define TIM15_BASE            (D2_APB2PERIPH_BASE + 0x4000UL)

+#define TIM16_BASE            (D2_APB2PERIPH_BASE + 0x4400UL)

+#define TIM17_BASE            (D2_APB2PERIPH_BASE + 0x4800UL)

+#define SPI5_BASE             (D2_APB2PERIPH_BASE + 0x5000UL)

+#define SAI1_BASE             (D2_APB2PERIPH_BASE + 0x5800UL)

+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)

+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)

+#define SAI2_BASE             (D2_APB2PERIPH_BASE + 0x5C00UL)

+#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004UL)

+#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024UL)

+#define SAI3_BASE             (D2_APB2PERIPH_BASE + 0x6000UL)

+#define SAI3_Block_A_BASE     (SAI3_BASE + 0x004UL)

+#define SAI3_Block_B_BASE     (SAI3_BASE + 0x024UL)

+#define DFSDM1_BASE           (D2_APB2PERIPH_BASE + 0x7000UL)

+#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00UL)

+#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20UL)

+#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40UL)

+#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60UL)

+#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80UL)

+#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0UL)

+#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0UL)

+#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0UL)

+#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)

+#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)

+#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)

+#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)

+#define HRTIM1_BASE           (D2_APB2PERIPH_BASE + 0x7400UL)

+#define HRTIM1_TIMA_BASE      (HRTIM1_BASE + 0x00000080UL)

+#define HRTIM1_TIMB_BASE      (HRTIM1_BASE + 0x00000100UL)

+#define HRTIM1_TIMC_BASE      (HRTIM1_BASE + 0x00000180UL)

+#define HRTIM1_TIMD_BASE      (HRTIM1_BASE + 0x00000200UL)

+#define HRTIM1_TIME_BASE      (HRTIM1_BASE + 0x00000280UL)

+#define HRTIM1_COMMON_BASE    (HRTIM1_BASE + 0x00000380UL)

+

+

+/*!< D3_APB1PERIPH peripherals */

+#define EXTI_BASE             (D3_APB1PERIPH_BASE + 0x0000UL)

+#define EXTI_D1_BASE          (EXTI_BASE + 0x0080UL)

+#define EXTI_D2_BASE          (EXTI_BASE + 0x00C0UL)

+#define SYSCFG_BASE           (D3_APB1PERIPH_BASE + 0x0400UL)

+#define LPUART1_BASE          (D3_APB1PERIPH_BASE + 0x0C00UL)

+#define SPI6_BASE             (D3_APB1PERIPH_BASE + 0x1400UL)

+#define I2C4_BASE             (D3_APB1PERIPH_BASE + 0x1C00UL)

+#define LPTIM2_BASE           (D3_APB1PERIPH_BASE + 0x2400UL)

+#define LPTIM3_BASE           (D3_APB1PERIPH_BASE + 0x2800UL)

+#define LPTIM4_BASE           (D3_APB1PERIPH_BASE + 0x2C00UL)

+#define LPTIM5_BASE           (D3_APB1PERIPH_BASE + 0x3000UL)

+#define COMP12_BASE           (D3_APB1PERIPH_BASE + 0x3800UL)

+#define COMP1_BASE            (COMP12_BASE + 0x0CUL)

+#define COMP2_BASE            (COMP12_BASE + 0x10UL)

+#define VREFBUF_BASE          (D3_APB1PERIPH_BASE + 0x3C00UL)

+#define RTC_BASE              (D3_APB1PERIPH_BASE + 0x4000UL)

+#define IWDG1_BASE            (D3_APB1PERIPH_BASE + 0x4800UL)

+

+

+#define SAI4_BASE             (D3_APB1PERIPH_BASE + 0x5400UL)

+#define SAI4_Block_A_BASE     (SAI4_BASE + 0x004UL)

+#define SAI4_Block_B_BASE     (SAI4_BASE + 0x024UL)

+

+

+

+

+#define BDMA_Channel0_BASE    (BDMA_BASE + 0x0008UL)

+#define BDMA_Channel1_BASE    (BDMA_BASE + 0x001CUL)

+#define BDMA_Channel2_BASE    (BDMA_BASE + 0x0030UL)

+#define BDMA_Channel3_BASE    (BDMA_BASE + 0x0044UL)

+#define BDMA_Channel4_BASE    (BDMA_BASE + 0x0058UL)

+#define BDMA_Channel5_BASE    (BDMA_BASE + 0x006CUL)

+#define BDMA_Channel6_BASE    (BDMA_BASE + 0x0080UL)

+#define BDMA_Channel7_BASE    (BDMA_BASE + 0x0094UL)

+

+#define DMAMUX2_Channel0_BASE    (DMAMUX2_BASE)

+#define DMAMUX2_Channel1_BASE    (DMAMUX2_BASE + 0x0004UL)

+#define DMAMUX2_Channel2_BASE    (DMAMUX2_BASE + 0x0008UL)

+#define DMAMUX2_Channel3_BASE    (DMAMUX2_BASE + 0x000CUL)

+#define DMAMUX2_Channel4_BASE    (DMAMUX2_BASE + 0x0010UL)

+#define DMAMUX2_Channel5_BASE    (DMAMUX2_BASE + 0x0014UL)

+#define DMAMUX2_Channel6_BASE    (DMAMUX2_BASE + 0x0018UL)

+#define DMAMUX2_Channel7_BASE    (DMAMUX2_BASE + 0x001CUL)

+

+#define DMAMUX2_RequestGenerator0_BASE  (DMAMUX2_BASE + 0x0100UL)

+#define DMAMUX2_RequestGenerator1_BASE  (DMAMUX2_BASE + 0x0104UL)

+#define DMAMUX2_RequestGenerator2_BASE  (DMAMUX2_BASE + 0x0108UL)

+#define DMAMUX2_RequestGenerator3_BASE  (DMAMUX2_BASE + 0x010CUL)

+#define DMAMUX2_RequestGenerator4_BASE  (DMAMUX2_BASE + 0x0110UL)

+#define DMAMUX2_RequestGenerator5_BASE  (DMAMUX2_BASE + 0x0114UL)

+#define DMAMUX2_RequestGenerator6_BASE  (DMAMUX2_BASE + 0x0118UL)

+#define DMAMUX2_RequestGenerator7_BASE  (DMAMUX2_BASE + 0x011CUL)

+

+#define DMAMUX2_ChannelStatus_BASE      (DMAMUX2_BASE + 0x0080UL)

+#define DMAMUX2_RequestGenStatus_BASE   (DMAMUX2_BASE + 0x0140UL)

+

+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)

+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)

+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)

+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)

+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)

+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)

+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)

+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)

+

+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)

+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)

+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)

+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)

+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)

+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)

+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)

+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)

+

+#define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)

+#define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)

+#define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)

+#define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)

+#define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)

+#define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)

+#define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0018UL)

+#define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x001CUL)

+#define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0020UL)

+#define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x0024UL)

+#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)

+#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)

+#define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)

+#define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)

+#define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)

+#define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)

+

+#define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)

+#define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)

+#define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)

+#define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)

+#define DMAMUX1_RequestGenerator4_BASE  (DMAMUX1_BASE + 0x0110UL)

+#define DMAMUX1_RequestGenerator5_BASE  (DMAMUX1_BASE + 0x0114UL)

+#define DMAMUX1_RequestGenerator6_BASE  (DMAMUX1_BASE + 0x0118UL)

+#define DMAMUX1_RequestGenerator7_BASE  (DMAMUX1_BASE + 0x011CUL)

+

+#define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)

+#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)

+

+/*!< FMC Banks registers base  address */

+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)

+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)

+#define FMC_Bank2_R_BASE      (FMC_R_BASE + 0x0060UL)

+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)

+#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)

+

+/* Debug MCU registers base address */

+#define DBGMCU_BASE           (0x5C001000UL)

+

+#define MDMA_Channel0_BASE    (MDMA_BASE + 0x00000040UL)

+#define MDMA_Channel1_BASE    (MDMA_BASE + 0x00000080UL)

+#define MDMA_Channel2_BASE    (MDMA_BASE + 0x000000C0UL)

+#define MDMA_Channel3_BASE    (MDMA_BASE + 0x00000100UL)

+#define MDMA_Channel4_BASE    (MDMA_BASE + 0x00000140UL)

+#define MDMA_Channel5_BASE    (MDMA_BASE + 0x00000180UL)

+#define MDMA_Channel6_BASE    (MDMA_BASE + 0x000001C0UL)

+#define MDMA_Channel7_BASE    (MDMA_BASE + 0x00000200UL)

+#define MDMA_Channel8_BASE    (MDMA_BASE + 0x00000240UL)

+#define MDMA_Channel9_BASE    (MDMA_BASE + 0x00000280UL)

+#define MDMA_Channel10_BASE   (MDMA_BASE + 0x000002C0UL)

+#define MDMA_Channel11_BASE   (MDMA_BASE + 0x00000300UL)

+#define MDMA_Channel12_BASE   (MDMA_BASE + 0x00000340UL)

+#define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)

+#define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)

+#define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)

+

+#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)

+#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)

+#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)

+#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)

+#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)

+

+#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)

+#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)

+#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)

+#define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL)

+#define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL)

+

+#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)

+#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)

+

+

+/**

+  * @}

+  */

+

+/** @addtogroup Peripheral_declaration

+  * @{

+  */

+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)

+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)

+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)

+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)

+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)

+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)

+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)

+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)

+#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)

+#define RTC                 ((RTC_TypeDef *) RTC_BASE)

+#define WWDG1               ((WWDG_TypeDef *) WWDG1_BASE)

+

+

+#define IWDG1               ((IWDG_TypeDef *) IWDG1_BASE)

+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)

+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)

+#define SPI4                ((SPI_TypeDef *) SPI4_BASE)

+#define SPI5                ((SPI_TypeDef *) SPI5_BASE)

+#define SPI6                ((SPI_TypeDef *) SPI6_BASE)

+#define USART2              ((USART_TypeDef *) USART2_BASE)

+#define USART3              ((USART_TypeDef *) USART3_BASE)

+#define USART6              ((USART_TypeDef *) USART6_BASE)

+#define UART7               ((USART_TypeDef *) UART7_BASE)

+#define UART8               ((USART_TypeDef *) UART8_BASE)

+#define CRS                 ((CRS_TypeDef *) CRS_BASE)

+#define UART4               ((USART_TypeDef *) UART4_BASE)

+#define UART5               ((USART_TypeDef *) UART5_BASE)

+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)

+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)

+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)

+#define I2C4                ((I2C_TypeDef *) I2C4_BASE)

+#define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

+#define FDCAN2              ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

+#define FDCAN_CCU           ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

+#define CEC                 ((CEC_TypeDef *) CEC_BASE)

+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)

+#define PWR                 ((PWR_TypeDef *) PWR_BASE)

+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)

+#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)

+#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)

+#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)

+#define LPTIM3              ((LPTIM_TypeDef *) LPTIM3_BASE)

+#define LPTIM4              ((LPTIM_TypeDef *) LPTIM4_BASE)

+#define LPTIM5              ((LPTIM_TypeDef *) LPTIM5_BASE)

+

+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)

+#define COMP12              ((COMPOPT_TypeDef *) COMP12_BASE)

+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)

+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)

+#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)

+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)

+#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)

+#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)

+

+

+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)

+#define EXTI_D1             ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

+#define EXTI_D2             ((EXTI_Core_TypeDef *) EXTI_D2_BASE)

+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)

+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)

+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)

+#define USART1              ((USART_TypeDef *) USART1_BASE)

+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)

+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)

+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)

+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)

+#define HRTIM1              ((HRTIM_TypeDef *) HRTIM1_BASE)

+#define HRTIM1_TIMA         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)

+#define HRTIM1_TIMB         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)

+#define HRTIM1_TIMC         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)

+#define HRTIM1_TIMD         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)

+#define HRTIM1_TIME         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)

+#define HRTIM1_COMMON       ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)

+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)

+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

+#define SAI2                ((SAI_TypeDef *) SAI2_BASE)

+#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)

+#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)

+#define SAI3                ((SAI_TypeDef *) SAI3_BASE)

+#define SAI3_Block_A        ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)

+#define SAI3_Block_B        ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)

+#define SAI4                ((SAI_TypeDef *) SAI4_BASE)

+#define SAI4_Block_A        ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)

+#define SAI4_Block_B        ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)

+

+#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

+#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

+#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

+#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

+#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

+#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

+#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

+#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

+#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

+#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

+#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

+#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

+#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

+#define DMA2D               ((DMA2D_TypeDef *) DMA2D_BASE)

+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)

+#define RCC                 ((RCC_TypeDef *) RCC_BASE)

+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)

+#define CRC                 ((CRC_TypeDef *) CRC_BASE)

+

+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)

+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)

+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)

+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)

+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)

+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)

+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)

+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)

+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)

+#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)

+#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)

+

+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)

+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)

+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)

+#define ADC3_COMMON         ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)

+#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

+

+#define RNG                 ((RNG_TypeDef *) RNG_BASE)

+#define SDMMC2              ((SDMMC_TypeDef *) SDMMC2_BASE)

+#define DLYB_SDMMC2         ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

+

+#define BDMA                ((BDMA_TypeDef *) BDMA_BASE)

+#define BDMA_Channel0       ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)

+#define BDMA_Channel1       ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)

+#define BDMA_Channel2       ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)

+#define BDMA_Channel3       ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)

+#define BDMA_Channel4       ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)

+#define BDMA_Channel5       ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)

+#define BDMA_Channel6       ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)

+#define BDMA_Channel7       ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)

+

+#define RAMECC1              ((RAMECC_TypeDef *)RAMECC1_BASE)

+#define RAMECC1_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)

+#define RAMECC1_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)

+#define RAMECC1_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)

+#define RAMECC1_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)

+#define RAMECC1_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)

+

+#define RAMECC2              ((RAMECC_TypeDef *)RAMECC2_BASE)

+#define RAMECC2_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)

+#define RAMECC2_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)

+#define RAMECC2_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)

+#define RAMECC2_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)

+#define RAMECC2_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)

+

+#define RAMECC3              ((RAMECC_TypeDef *)RAMECC3_BASE)

+#define RAMECC3_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)

+#define RAMECC3_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)

+

+#define DMAMUX2                ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

+#define DMAMUX2_Channel0       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

+#define DMAMUX2_Channel1       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

+#define DMAMUX2_Channel2       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

+#define DMAMUX2_Channel3       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

+#define DMAMUX2_Channel4       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

+#define DMAMUX2_Channel5       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

+#define DMAMUX2_Channel6       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

+#define DMAMUX2_Channel7       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

+

+

+#define DMAMUX2_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

+#define DMAMUX2_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

+#define DMAMUX2_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

+#define DMAMUX2_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

+#define DMAMUX2_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

+#define DMAMUX2_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

+#define DMAMUX2_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

+#define DMAMUX2_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

+

+#define DMAMUX2_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

+#define DMAMUX2_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

+

+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)

+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

+

+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)

+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

+

+

+#define DMAMUX1              ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

+#define DMAMUX1_Channel0     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

+#define DMAMUX1_Channel1     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

+#define DMAMUX1_Channel2     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

+#define DMAMUX1_Channel3     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

+#define DMAMUX1_Channel4     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

+#define DMAMUX1_Channel5     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

+#define DMAMUX1_Channel6     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

+#define DMAMUX1_Channel7     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

+#define DMAMUX1_Channel8     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

+#define DMAMUX1_Channel9     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

+#define DMAMUX1_Channel10    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

+#define DMAMUX1_Channel11    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

+#define DMAMUX1_Channel12    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

+#define DMAMUX1_Channel13    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

+#define DMAMUX1_Channel14    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

+#define DMAMUX1_Channel15    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

+

+#define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

+#define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

+#define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

+#define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

+#define DMAMUX1_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

+#define DMAMUX1_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

+#define DMAMUX1_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

+#define DMAMUX1_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

+

+#define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *)    DMAMUX1_ChannelStatus_BASE)

+#define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

+

+

+#define FMC_Bank1_R           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

+#define FMC_Bank1E_R          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

+#define FMC_Bank2_R           ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

+#define FMC_Bank3_R           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

+#define FMC_Bank5_6_R         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

+

+

+#define QUADSPI               ((QUADSPI_TypeDef *) QSPI_R_BASE)

+#define DLYB_QUADSPI          ((DLYB_TypeDef *) DLYB_QSPI_BASE)

+#define SDMMC1                ((SDMMC_TypeDef *) SDMMC1_BASE)

+#define DLYB_SDMMC1           ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

+

+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)

+

+#define HSEM                ((HSEM_TypeDef *) HSEM_BASE)

+#define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

+

+

+#define MDIOS               ((MDIOS_TypeDef *) MDIOS_BASE)

+

+#define ETH                 ((ETH_TypeDef *)ETH_BASE)

+#define MDMA                ((MDMA_TypeDef *)MDMA_BASE)

+#define MDMA_Channel0       ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

+#define MDMA_Channel1       ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

+#define MDMA_Channel2       ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

+#define MDMA_Channel3       ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

+#define MDMA_Channel4       ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

+#define MDMA_Channel5       ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

+#define MDMA_Channel6       ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

+#define MDMA_Channel7       ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

+#define MDMA_Channel8       ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

+#define MDMA_Channel9       ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

+#define MDMA_Channel10      ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

+#define MDMA_Channel11      ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

+#define MDMA_Channel12      ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

+#define MDMA_Channel13      ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

+#define MDMA_Channel14      ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

+#define MDMA_Channel15      ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

+

+

+#define USB1_OTG_HS         ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

+#define USB2_OTG_FS         ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)

+

+/* Legacy defines */

+#define USB_OTG_HS                   USB1_OTG_HS

+#define USB_OTG_HS_PERIPH_BASE       USB1_OTG_HS_PERIPH_BASE

+#define USB_OTG_FS                   USB2_OTG_FS

+#define USB_OTG_FS_PERIPH_BASE       USB2_OTG_FS_PERIPH_BASE

+

+/**

+  * @}

+  */

+

+/** @addtogroup Exported_constants

+  * @{

+  */

+

+  /** @addtogroup Peripheral_Registers_Bits_Definition

+  * @{

+  */

+

+/******************************************************************************/

+/*                         Peripheral Registers_Bits_Definition               */

+/******************************************************************************/

+

+/******************************************************************************/

+/*                                                                            */

+/*                        Analog to Digital Converter                         */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  ADC VERSION  ********************************/

+#define ADC_VER_V5_X

+/********************  Bit definition for ADC_ISR register  ********************/

+#define ADC_ISR_ADRDY_Pos                 (0U)

+#define ADC_ISR_ADRDY_Msk                 (0x1UL << ADC_ISR_ADRDY_Pos)         /*!< 0x00000001 */

+#define ADC_ISR_ADRDY                     ADC_ISR_ADRDY_Msk                    /*!< ADC Ready (ADRDY) flag  */

+#define ADC_ISR_EOSMP_Pos                 (1U)

+#define ADC_ISR_EOSMP_Msk                 (0x1UL << ADC_ISR_EOSMP_Pos)         /*!< 0x00000002 */

+#define ADC_ISR_EOSMP                     ADC_ISR_EOSMP_Msk                    /*!< ADC End of Sampling flag */

+#define ADC_ISR_EOC_Pos                   (2U)

+#define ADC_ISR_EOC_Msk                   (0x1UL << ADC_ISR_EOC_Pos)           /*!< 0x00000004 */

+#define ADC_ISR_EOC                       ADC_ISR_EOC_Msk                      /*!< ADC End of Regular Conversion flag */

+#define ADC_ISR_EOS_Pos                   (3U)

+#define ADC_ISR_EOS_Msk                   (0x1UL << ADC_ISR_EOS_Pos)           /*!< 0x00000008 */

+#define ADC_ISR_EOS                       ADC_ISR_EOS_Msk                      /*!< ADC End of Regular sequence of Conversions flag */

+#define ADC_ISR_OVR_Pos                   (4U)

+#define ADC_ISR_OVR_Msk                   (0x1UL << ADC_ISR_OVR_Pos)           /*!< 0x00000010 */

+#define ADC_ISR_OVR                       ADC_ISR_OVR_Msk                      /*!< ADC overrun flag */

+#define ADC_ISR_JEOC_Pos                  (5U)

+#define ADC_ISR_JEOC_Msk                  (0x1UL << ADC_ISR_JEOC_Pos)          /*!< 0x00000020 */

+#define ADC_ISR_JEOC                      ADC_ISR_JEOC_Msk                     /*!< ADC End of Injected Conversion flag */

+#define ADC_ISR_JEOS_Pos                  (6U)

+#define ADC_ISR_JEOS_Msk                  (0x1UL << ADC_ISR_JEOS_Pos)          /*!< 0x00000040 */

+#define ADC_ISR_JEOS                      ADC_ISR_JEOS_Msk                     /*!< ADC End of Injected sequence of Conversions flag */

+#define ADC_ISR_AWD1_Pos                  (7U)

+#define ADC_ISR_AWD1_Msk                  (0x1UL << ADC_ISR_AWD1_Pos)          /*!< 0x00000080 */

+#define ADC_ISR_AWD1                      ADC_ISR_AWD1_Msk                     /*!< ADC Analog watchdog 1 flag */

+#define ADC_ISR_AWD2_Pos                  (8U)

+#define ADC_ISR_AWD2_Msk                  (0x1UL << ADC_ISR_AWD2_Pos)          /*!< 0x00000100 */

+#define ADC_ISR_AWD2                      ADC_ISR_AWD2_Msk                     /*!< ADC Analog watchdog 2 flag */

+#define ADC_ISR_AWD3_Pos                  (9U)

+#define ADC_ISR_AWD3_Msk                  (0x1UL << ADC_ISR_AWD3_Pos)          /*!< 0x00000200 */

+#define ADC_ISR_AWD3                      ADC_ISR_AWD3_Msk                     /*!< ADC Analog watchdog 3 flag */

+#define ADC_ISR_JQOVF_Pos                 (10U)

+#define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */

+#define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */

+

+/********************  Bit definition for ADC_IER register  ********************/

+#define ADC_IER_ADRDYIE_Pos               (0U)

+#define ADC_IER_ADRDYIE_Msk               (0x1UL << ADC_IER_ADRDYIE_Pos)       /*!< 0x00000001 */

+#define ADC_IER_ADRDYIE                   ADC_IER_ADRDYIE_Msk                  /*!< ADC Ready (ADRDY) interrupt source */

+#define ADC_IER_EOSMPIE_Pos               (1U)

+#define ADC_IER_EOSMPIE_Msk               (0x1UL << ADC_IER_EOSMPIE_Pos)       /*!< 0x00000002 */

+#define ADC_IER_EOSMPIE                   ADC_IER_EOSMPIE_Msk                  /*!< ADC End of Sampling interrupt source */

+#define ADC_IER_EOCIE_Pos                 (2U)

+#define ADC_IER_EOCIE_Msk                 (0x1UL << ADC_IER_EOCIE_Pos)         /*!< 0x00000004 */

+#define ADC_IER_EOCIE                     ADC_IER_EOCIE_Msk                    /*!< ADC End of Regular Conversion interrupt source */

+#define ADC_IER_EOSIE_Pos                 (3U)

+#define ADC_IER_EOSIE_Msk                 (0x1UL << ADC_IER_EOSIE_Pos)         /*!< 0x00000008 */

+#define ADC_IER_EOSIE                     ADC_IER_EOSIE_Msk                    /*!< ADC End of Regular sequence of Conversions interrupt source */

+#define ADC_IER_OVRIE_Pos                 (4U)

+#define ADC_IER_OVRIE_Msk                 (0x1UL << ADC_IER_OVRIE_Pos)         /*!< 0x00000010 */

+#define ADC_IER_OVRIE                     ADC_IER_OVRIE_Msk                    /*!< ADC overrun interrupt source */

+#define ADC_IER_JEOCIE_Pos                (5U)

+#define ADC_IER_JEOCIE_Msk                (0x1UL << ADC_IER_JEOCIE_Pos)        /*!< 0x00000020 */

+#define ADC_IER_JEOCIE                    ADC_IER_JEOCIE_Msk                   /*!< ADC End of Injected Conversion interrupt source */

+#define ADC_IER_JEOSIE_Pos                (6U)

+#define ADC_IER_JEOSIE_Msk                (0x1UL << ADC_IER_JEOSIE_Pos)        /*!< 0x00000040 */

+#define ADC_IER_JEOSIE                    ADC_IER_JEOSIE_Msk                   /*!< ADC End of Injected sequence of Conversions interrupt source */

+#define ADC_IER_AWD1IE_Pos                (7U)

+#define ADC_IER_AWD1IE_Msk                (0x1UL << ADC_IER_AWD1IE_Pos)        /*!< 0x00000080 */

+#define ADC_IER_AWD1IE                    ADC_IER_AWD1IE_Msk                   /*!< ADC Analog watchdog 1 interrupt source */

+#define ADC_IER_AWD2IE_Pos                (8U)

+#define ADC_IER_AWD2IE_Msk                (0x1UL << ADC_IER_AWD2IE_Pos)        /*!< 0x00000100 */

+#define ADC_IER_AWD2IE                    ADC_IER_AWD2IE_Msk                   /*!< ADC Analog watchdog 2 interrupt source */

+#define ADC_IER_AWD3IE_Pos                (9U)

+#define ADC_IER_AWD3IE_Msk                (0x1UL << ADC_IER_AWD3IE_Pos)        /*!< 0x00000200 */

+#define ADC_IER_AWD3IE                    ADC_IER_AWD3IE_Msk                   /*!< ADC Analog watchdog 3 interrupt source */

+#define ADC_IER_JQOVFIE_Pos               (10U)

+#define ADC_IER_JQOVFIE_Msk               (0x1UL << ADC_IER_JQOVFIE_Pos)       /*!< 0x00000400 */

+#define ADC_IER_JQOVFIE                   ADC_IER_JQOVFIE_Msk                  /*!< ADC Injected Context Queue Overflow interrupt source */

+

+/********************  Bit definition for ADC_CR register  ********************/

+#define ADC_CR_ADEN_Pos                   (0U)

+#define ADC_CR_ADEN_Msk                   (0x1UL << ADC_CR_ADEN_Pos)           /*!< 0x00000001 */

+#define ADC_CR_ADEN                       ADC_CR_ADEN_Msk                      /*!< ADC Enable control */

+#define ADC_CR_ADDIS_Pos                  (1U)

+#define ADC_CR_ADDIS_Msk                  (0x1UL << ADC_CR_ADDIS_Pos)          /*!< 0x00000002 */

+#define ADC_CR_ADDIS                      ADC_CR_ADDIS_Msk                     /*!< ADC Disable command */

+#define ADC_CR_ADSTART_Pos                (2U)

+#define ADC_CR_ADSTART_Msk                (0x1UL << ADC_CR_ADSTART_Pos)        /*!< 0x00000004 */

+#define ADC_CR_ADSTART                    ADC_CR_ADSTART_Msk                   /*!< ADC Start of Regular conversion */

+#define ADC_CR_JADSTART_Pos               (3U)

+#define ADC_CR_JADSTART_Msk               (0x1UL << ADC_CR_JADSTART_Pos)       /*!< 0x00000008 */

+#define ADC_CR_JADSTART                   ADC_CR_JADSTART_Msk                  /*!< ADC Start of injected conversion */

+#define ADC_CR_ADSTP_Pos                  (4U)

+#define ADC_CR_ADSTP_Msk                  (0x1UL << ADC_CR_ADSTP_Pos)          /*!< 0x00000010 */

+#define ADC_CR_ADSTP                      ADC_CR_ADSTP_Msk                     /*!< ADC Stop of Regular conversion */

+#define ADC_CR_JADSTP_Pos                 (5U)

+#define ADC_CR_JADSTP_Msk                 (0x1UL << ADC_CR_JADSTP_Pos)         /*!< 0x00000020 */

+#define ADC_CR_JADSTP                     ADC_CR_JADSTP_Msk                    /*!< ADC Stop of injected conversion */

+#define ADC_CR_BOOST_Pos                  (8U)

+#define ADC_CR_BOOST_Msk                  (0x3UL << ADC_CR_BOOST_Pos)          /*!< 0x00000300 */

+#define ADC_CR_BOOST                      ADC_CR_BOOST_Msk                     /*!< ADC Boost Mode configuration */

+#define ADC_CR_BOOST_0                    (0x1UL << ADC_CR_BOOST_Pos)           /*!< 0x00000100 */

+#define ADC_CR_BOOST_1                    (0x2UL << ADC_CR_BOOST_Pos)           /*!< 0x00000200 */

+#define ADC_CR_ADCALLIN_Pos               (16U)

+#define ADC_CR_ADCALLIN_Msk               (0x1UL << ADC_CR_ADCALLIN_Pos)       /*!< 0x00010000 */

+#define ADC_CR_ADCALLIN                   ADC_CR_ADCALLIN_Msk                  /*!< ADC Linearity calibration */

+#define ADC_CR_LINCALRDYW1_Pos            (22U)

+#define ADC_CR_LINCALRDYW1_Msk            (0x1UL << ADC_CR_LINCALRDYW1_Pos)    /*!< 0x00400000 */

+#define ADC_CR_LINCALRDYW1                ADC_CR_LINCALRDYW1_Msk               /*!< ADC Linearity calibration ready Word 1 */

+#define ADC_CR_LINCALRDYW2_Pos            (23U)

+#define ADC_CR_LINCALRDYW2_Msk            (0x1UL << ADC_CR_LINCALRDYW2_Pos)    /*!< 0x00800000 */

+#define ADC_CR_LINCALRDYW2                ADC_CR_LINCALRDYW2_Msk               /*!< ADC Linearity calibration ready Word 2 */

+#define ADC_CR_LINCALRDYW3_Pos            (24U)

+#define ADC_CR_LINCALRDYW3_Msk            (0x1UL << ADC_CR_LINCALRDYW3_Pos)    /*!< 0x01000000 */

+#define ADC_CR_LINCALRDYW3                ADC_CR_LINCALRDYW3_Msk               /*!< ADC Linearity calibration ready Word 3 */

+#define ADC_CR_LINCALRDYW4_Pos            (25U)

+#define ADC_CR_LINCALRDYW4_Msk            (0x1UL << ADC_CR_LINCALRDYW4_Pos)    /*!< 0x02000000 */

+#define ADC_CR_LINCALRDYW4                ADC_CR_LINCALRDYW4_Msk               /*!< ADC Linearity calibration ready Word 4 */

+#define ADC_CR_LINCALRDYW5_Pos            (26U)

+#define ADC_CR_LINCALRDYW5_Msk            (0x1UL << ADC_CR_LINCALRDYW5_Pos)    /*!< 0x04000000 */

+#define ADC_CR_LINCALRDYW5                ADC_CR_LINCALRDYW5_Msk               /*!< ADC Linearity calibration ready Word 5 */

+#define ADC_CR_LINCALRDYW6_Pos            (27U)

+#define ADC_CR_LINCALRDYW6_Msk            (0x1UL << ADC_CR_LINCALRDYW6_Pos)    /*!< 0x08000000 */

+#define ADC_CR_LINCALRDYW6                ADC_CR_LINCALRDYW6_Msk               /*!< ADC Linearity calibration ready Word 6 */

+#define ADC_CR_ADVREGEN_Pos               (28U)

+#define ADC_CR_ADVREGEN_Msk               (0x1UL << ADC_CR_ADVREGEN_Pos)       /*!< 0x10000000 */

+#define ADC_CR_ADVREGEN                   ADC_CR_ADVREGEN_Msk                  /*!< ADC Voltage regulator Enable */

+#define ADC_CR_DEEPPWD_Pos                (29U)

+#define ADC_CR_DEEPPWD_Msk                (0x1UL << ADC_CR_DEEPPWD_Pos)        /*!< 0x20000000 */

+#define ADC_CR_DEEPPWD                    ADC_CR_DEEPPWD_Msk                   /*!< ADC Deep power down Enable */

+#define ADC_CR_ADCALDIF_Pos               (30U)

+#define ADC_CR_ADCALDIF_Msk               (0x1UL << ADC_CR_ADCALDIF_Pos)       /*!< 0x40000000 */

+#define ADC_CR_ADCALDIF                   ADC_CR_ADCALDIF_Msk                  /*!< ADC Differential Mode for calibration */

+#define ADC_CR_ADCAL_Pos                  (31U)

+#define ADC_CR_ADCAL_Msk                  (0x1UL << ADC_CR_ADCAL_Pos)          /*!< 0x80000000 */

+#define ADC_CR_ADCAL                      ADC_CR_ADCAL_Msk                     /*!< ADC Calibration */

+

+/********************  Bit definition for ADC_CFGR register  ********************/

+#define ADC_CFGR_DMNGT_Pos                (0U)

+#define ADC_CFGR_DMNGT_Msk                (0x3UL << ADC_CFGR_DMNGT_Pos)        /*!< 0x00000003 */

+#define ADC_CFGR_DMNGT                    ADC_CFGR_DMNGT_Msk                   /*!< ADC Data Management configuration */

+#define ADC_CFGR_DMNGT_0                  (0x1UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000001 */

+#define ADC_CFGR_DMNGT_1                  (0x2UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000002 */

+

+#define ADC_CFGR_RES_Pos                  (2U)

+#define ADC_CFGR_RES_Msk                  (0x7UL << ADC_CFGR_RES_Pos)          /*!< 0x0000001C */

+#define ADC_CFGR_RES                      ADC_CFGR_RES_Msk                     /*!< ADC Data resolution */

+#define ADC_CFGR_RES_0                    (0x1UL << ADC_CFGR_RES_Pos)           /*!< 0x00000004 */

+#define ADC_CFGR_RES_1                    (0x2UL << ADC_CFGR_RES_Pos)           /*!< 0x00000008 */

+#define ADC_CFGR_RES_2                    (0x4UL << ADC_CFGR_RES_Pos)           /*!< 0x00000010 */

+

+#define ADC_CFGR_EXTSEL_Pos               (5U)

+#define ADC_CFGR_EXTSEL_Msk               (0x1FUL << ADC_CFGR_EXTSEL_Pos)      /*!< 0x000003E0 */

+#define ADC_CFGR_EXTSEL                   ADC_CFGR_EXTSEL_Msk                  /*!< ADC External trigger selection for regular group */

+#define ADC_CFGR_EXTSEL_0                 (0x01UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000020 */

+#define ADC_CFGR_EXTSEL_1                 (0x02UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000040 */

+#define ADC_CFGR_EXTSEL_2                 (0x04UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000080 */

+#define ADC_CFGR_EXTSEL_3                 (0x08UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000100 */

+#define ADC_CFGR_EXTSEL_4                 (0x10UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000200 */

+

+#define ADC_CFGR_EXTEN_Pos                (10U)

+#define ADC_CFGR_EXTEN_Msk                (0x3UL << ADC_CFGR_EXTEN_Pos)        /*!< 0x00000C00 */

+#define ADC_CFGR_EXTEN                    ADC_CFGR_EXTEN_Msk                   /*!< ADC External trigger enable and polarity selection for regular channels */

+#define ADC_CFGR_EXTEN_0                  (0x1UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000400 */

+#define ADC_CFGR_EXTEN_1                  (0x2UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000800 */

+

+#define ADC_CFGR_OVRMOD_Pos               (12U)

+#define ADC_CFGR_OVRMOD_Msk               (0x1UL << ADC_CFGR_OVRMOD_Pos)       /*!< 0x00001000 */

+#define ADC_CFGR_OVRMOD                   ADC_CFGR_OVRMOD_Msk                  /*!< ADC overrun mode */

+#define ADC_CFGR_CONT_Pos                 (13U)

+#define ADC_CFGR_CONT_Msk                 (0x1UL << ADC_CFGR_CONT_Pos)         /*!< 0x00002000 */

+#define ADC_CFGR_CONT                     ADC_CFGR_CONT_Msk                    /*!< ADC Single/continuous conversion mode for regular conversion */

+#define ADC_CFGR_AUTDLY_Pos               (14U)

+#define ADC_CFGR_AUTDLY_Msk               (0x1UL << ADC_CFGR_AUTDLY_Pos)       /*!< 0x00004000 */

+#define ADC_CFGR_AUTDLY                   ADC_CFGR_AUTDLY_Msk                  /*!< ADC Delayed conversion mode */

+

+#define ADC_CFGR_DISCEN_Pos               (16U)

+#define ADC_CFGR_DISCEN_Msk               (0x1UL << ADC_CFGR_DISCEN_Pos)       /*!< 0x00010000 */

+#define ADC_CFGR_DISCEN                   ADC_CFGR_DISCEN_Msk                  /*!< ADC Discontinuous mode for regular channels */

+

+#define ADC_CFGR_DISCNUM_Pos              (17U)

+#define ADC_CFGR_DISCNUM_Msk              (0x7UL << ADC_CFGR_DISCNUM_Pos)      /*!< 0x000E0000 */

+#define ADC_CFGR_DISCNUM                  ADC_CFGR_DISCNUM_Msk                 /*!< ADC Discontinuous mode channel count */

+#define ADC_CFGR_DISCNUM_0                (0x1UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00020000 */

+#define ADC_CFGR_DISCNUM_1                (0x2UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00040000 */

+#define ADC_CFGR_DISCNUM_2                (0x4UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00080000 */

+

+#define ADC_CFGR_JDISCEN_Pos              (20U)

+#define ADC_CFGR_JDISCEN_Msk              (0x1UL << ADC_CFGR_JDISCEN_Pos)      /*!< 0x00100000 */

+#define ADC_CFGR_JDISCEN                  ADC_CFGR_JDISCEN_Msk                 /*!< ADC Discontinuous mode on injected channels */

+#define ADC_CFGR_JQM_Pos                  (21U)

+#define ADC_CFGR_JQM_Msk                  (0x1UL << ADC_CFGR_JQM_Pos)          /*!< 0x00200000 */

+#define ADC_CFGR_JQM                      ADC_CFGR_JQM_Msk                     /*!< ADC JSQR Queue mode */

+#define ADC_CFGR_AWD1SGL_Pos              (22U)

+#define ADC_CFGR_AWD1SGL_Msk              (0x1UL << ADC_CFGR_AWD1SGL_Pos)      /*!< 0x00400000 */

+#define ADC_CFGR_AWD1SGL                  ADC_CFGR_AWD1SGL_Msk                 /*!< Enable the watchdog 1 on a single channel or on all channels */

+#define ADC_CFGR_AWD1EN_Pos               (23U)

+#define ADC_CFGR_AWD1EN_Msk               (0x1UL << ADC_CFGR_AWD1EN_Pos)       /*!< 0x00800000 */

+#define ADC_CFGR_AWD1EN                   ADC_CFGR_AWD1EN_Msk                  /*!< ADC Analog watchdog 1 enable on regular Channels */

+#define ADC_CFGR_JAWD1EN_Pos              (24U)

+#define ADC_CFGR_JAWD1EN_Msk              (0x1UL << ADC_CFGR_JAWD1EN_Pos)      /*!< 0x01000000 */

+#define ADC_CFGR_JAWD1EN                  ADC_CFGR_JAWD1EN_Msk                 /*!< ADC Analog watchdog 1 enable on injected Channels */

+#define ADC_CFGR_JAUTO_Pos                (25U)

+#define ADC_CFGR_JAUTO_Msk                (0x1UL << ADC_CFGR_JAUTO_Pos)        /*!< 0x02000000 */

+#define ADC_CFGR_JAUTO                    ADC_CFGR_JAUTO_Msk                   /*!< ADC Automatic injected group conversion */

+

+#define ADC_CFGR_AWD1CH_Pos               (26U)

+#define ADC_CFGR_AWD1CH_Msk               (0x1FUL << ADC_CFGR_AWD1CH_Pos)      /*!< 0x7C000000 */

+#define ADC_CFGR_AWD1CH                   ADC_CFGR_AWD1CH_Msk                  /*!< ADC Analog watchdog 1 Channel selection */

+#define ADC_CFGR_AWD1CH_0                 (0x01UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x04000000 */

+#define ADC_CFGR_AWD1CH_1                 (0x02UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x08000000 */

+#define ADC_CFGR_AWD1CH_2                 (0x04UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x10000000 */

+#define ADC_CFGR_AWD1CH_3                 (0x08UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x20000000 */

+#define ADC_CFGR_AWD1CH_4                 (0x10UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x40000000 */

+

+#define ADC_CFGR_JQDIS_Pos                (31U)

+#define ADC_CFGR_JQDIS_Msk                (0x1UL << ADC_CFGR_JQDIS_Pos)        /*!< 0x80000000 */

+#define ADC_CFGR_JQDIS                    ADC_CFGR_JQDIS_Msk                   /*!< ADC Injected queue disable */

+

+/********************  Bit definition for ADC_CFGR2 register  ********************/

+#define ADC_CFGR2_ROVSE_Pos               (0U)

+#define ADC_CFGR2_ROVSE_Msk               (0x1UL << ADC_CFGR2_ROVSE_Pos)       /*!< 0x00000001 */

+#define ADC_CFGR2_ROVSE                   ADC_CFGR2_ROVSE_Msk                  /*!< ADC Regular group oversampler enable */

+#define ADC_CFGR2_JOVSE_Pos               (1U)

+#define ADC_CFGR2_JOVSE_Msk               (0x1UL << ADC_CFGR2_JOVSE_Pos)       /*!< 0x00000002 */

+#define ADC_CFGR2_JOVSE                   ADC_CFGR2_JOVSE_Msk                  /*!< ADC Injected group oversampler enable */

+

+#define ADC_CFGR2_OVSS_Pos                (5U)

+#define ADC_CFGR2_OVSS_Msk                (0xFUL << ADC_CFGR2_OVSS_Pos)        /*!< 0x000001E0 */

+#define ADC_CFGR2_OVSS                    ADC_CFGR2_OVSS_Msk                   /*!< ADC Regular Oversampling shift */

+#define ADC_CFGR2_OVSS_0                  (0x1UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000020 */

+#define ADC_CFGR2_OVSS_1                  (0x2UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000040 */

+#define ADC_CFGR2_OVSS_2                  (0x4UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000080 */

+#define ADC_CFGR2_OVSS_3                  (0x8UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000100 */

+

+#define ADC_CFGR2_TROVS_Pos               (9U)

+#define ADC_CFGR2_TROVS_Msk               (0x1UL << ADC_CFGR2_TROVS_Pos)       /*!< 0x00000200 */

+#define ADC_CFGR2_TROVS                   ADC_CFGR2_TROVS_Msk                  /*!< ADC Triggered regular Oversampling */

+#define ADC_CFGR2_ROVSM_Pos               (10U)

+#define ADC_CFGR2_ROVSM_Msk               (0x1UL << ADC_CFGR2_ROVSM_Pos)       /*!< 0x00000400 */

+#define ADC_CFGR2_ROVSM                   ADC_CFGR2_ROVSM_Msk                  /*!< ADC Regular oversampling mode */

+

+#define ADC_CFGR2_RSHIFT1_Pos             (11U)

+#define ADC_CFGR2_RSHIFT1_Msk             (0x1UL << ADC_CFGR2_RSHIFT1_Pos)     /*!< 0x00000800 */

+#define ADC_CFGR2_RSHIFT1                 ADC_CFGR2_RSHIFT1_Msk                /*!< ADC Right-shift data after Offset 1 correction */

+#define ADC_CFGR2_RSHIFT2_Pos             (12U)

+#define ADC_CFGR2_RSHIFT2_Msk             (0x1UL << ADC_CFGR2_RSHIFT2_Pos)     /*!< 0x00001000 */

+#define ADC_CFGR2_RSHIFT2                 ADC_CFGR2_RSHIFT2_Msk                /*!< ADC Right-shift data after Offset 2 correction */

+#define ADC_CFGR2_RSHIFT3_Pos             (13U)

+#define ADC_CFGR2_RSHIFT3_Msk             (0x1UL << ADC_CFGR2_RSHIFT3_Pos)     /*!< 0x00002000 */

+#define ADC_CFGR2_RSHIFT3                 ADC_CFGR2_RSHIFT3_Msk                /*!< ADC Right-shift data after Offset 3 correction */

+#define ADC_CFGR2_RSHIFT4_Pos             (14U)

+#define ADC_CFGR2_RSHIFT4_Msk             (0x1UL << ADC_CFGR2_RSHIFT4_Pos)     /*!< 0x00004000 */

+#define ADC_CFGR2_RSHIFT4                 ADC_CFGR2_RSHIFT4_Msk                /*!< ADC Right-shift data after Offset 4 correction */

+

+#define ADC_CFGR2_OVSR_Pos                (16U)

+#define ADC_CFGR2_OVSR_Msk                (0x3FFUL << ADC_CFGR2_OVSR_Pos)      /*!< 0x03FF0000 */

+#define ADC_CFGR2_OVSR                    ADC_CFGR2_OVSR_Msk                   /*!< ADC oversampling Ratio */

+#define ADC_CFGR2_OVSR_0                  (0x001UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00010000 */

+#define ADC_CFGR2_OVSR_1                  (0x002UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00020000 */

+#define ADC_CFGR2_OVSR_2                  (0x004UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00040000 */

+#define ADC_CFGR2_OVSR_3                  (0x008UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00080000 */

+#define ADC_CFGR2_OVSR_4                  (0x010UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00100000 */

+#define ADC_CFGR2_OVSR_5                  (0x020UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00200000 */

+#define ADC_CFGR2_OVSR_6                  (0x040UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00400000 */

+#define ADC_CFGR2_OVSR_7                  (0x080UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00800000 */

+#define ADC_CFGR2_OVSR_8                  (0x100UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x01000000 */

+#define ADC_CFGR2_OVSR_9                  (0x200UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x02000000 */

+

+#define ADC_CFGR2_LSHIFT_Pos              (28U)

+#define ADC_CFGR2_LSHIFT_Msk              (0xFUL << ADC_CFGR2_LSHIFT_Pos)      /*!< 0xF0000000 */

+#define ADC_CFGR2_LSHIFT                  ADC_CFGR2_LSHIFT_Msk                 /*!< ADC Left shift factor */

+#define ADC_CFGR2_LSHIFT_0                (0x1UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x10000000 */

+#define ADC_CFGR2_LSHIFT_1                (0x2UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x20000000 */

+#define ADC_CFGR2_LSHIFT_2                (0x4UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x40000000 */

+#define ADC_CFGR2_LSHIFT_3                (0x8UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_SMPR1 register  ********************/

+#define ADC_SMPR1_SMP0_Pos                (0U)

+#define ADC_SMPR1_SMP0_Msk                (0x7UL << ADC_SMPR1_SMP0_Pos)        /*!< 0x00000007 */

+#define ADC_SMPR1_SMP0                    ADC_SMPR1_SMP0_Msk                   /*!< ADC Channel 0 Sampling time selection  */

+#define ADC_SMPR1_SMP0_0                  (0x1UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000001 */

+#define ADC_SMPR1_SMP0_1                  (0x2UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000002 */

+#define ADC_SMPR1_SMP0_2                  (0x4UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000004 */

+

+#define ADC_SMPR1_SMP1_Pos                (3U)

+#define ADC_SMPR1_SMP1_Msk                (0x7UL << ADC_SMPR1_SMP1_Pos)        /*!< 0x00000038 */

+#define ADC_SMPR1_SMP1                    ADC_SMPR1_SMP1_Msk                   /*!< ADC Channel 1 Sampling time selection  */

+#define ADC_SMPR1_SMP1_0                  (0x1UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000008 */

+#define ADC_SMPR1_SMP1_1                  (0x2UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000010 */

+#define ADC_SMPR1_SMP1_2                  (0x4UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000020 */

+

+#define ADC_SMPR1_SMP2_Pos                (6U)

+#define ADC_SMPR1_SMP2_Msk                (0x7UL << ADC_SMPR1_SMP2_Pos)        /*!< 0x000001C0 */

+#define ADC_SMPR1_SMP2                    ADC_SMPR1_SMP2_Msk                   /*!< ADC Channel 2 Sampling time selection  */

+#define ADC_SMPR1_SMP2_0                  (0x1UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000040 */

+#define ADC_SMPR1_SMP2_1                  (0x2UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000080 */

+#define ADC_SMPR1_SMP2_2                  (0x4UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000100 */

+

+#define ADC_SMPR1_SMP3_Pos                (9U)

+#define ADC_SMPR1_SMP3_Msk                (0x7UL << ADC_SMPR1_SMP3_Pos)        /*!< 0x00000E00 */

+#define ADC_SMPR1_SMP3                    ADC_SMPR1_SMP3_Msk                   /*!< ADC Channel 3 Sampling time selection  */

+#define ADC_SMPR1_SMP3_0                  (0x1UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000200 */

+#define ADC_SMPR1_SMP3_1                  (0x2UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000400 */

+#define ADC_SMPR1_SMP3_2                  (0x4UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000800 */

+

+#define ADC_SMPR1_SMP4_Pos                (12U)

+#define ADC_SMPR1_SMP4_Msk                (0x7UL << ADC_SMPR1_SMP4_Pos)        /*!< 0x00007000 */

+#define ADC_SMPR1_SMP4                    ADC_SMPR1_SMP4_Msk                   /*!< ADC Channel 4 Sampling time selection  */

+#define ADC_SMPR1_SMP4_0                  (0x1UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00001000 */

+#define ADC_SMPR1_SMP4_1                  (0x2UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00002000 */

+#define ADC_SMPR1_SMP4_2                  (0x4UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00004000 */

+

+#define ADC_SMPR1_SMP5_Pos                (15U)

+#define ADC_SMPR1_SMP5_Msk                (0x7UL << ADC_SMPR1_SMP5_Pos)        /*!< 0x00038000 */

+#define ADC_SMPR1_SMP5                    ADC_SMPR1_SMP5_Msk                   /*!< ADC Channel 5 Sampling time selection  */

+#define ADC_SMPR1_SMP5_0                  (0x1UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00008000 */

+#define ADC_SMPR1_SMP5_1                  (0x2UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00010000 */

+#define ADC_SMPR1_SMP5_2                  (0x4UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00020000 */

+

+#define ADC_SMPR1_SMP6_Pos                (18U)

+#define ADC_SMPR1_SMP6_Msk                (0x7UL << ADC_SMPR1_SMP6_Pos)        /*!< 0x001C0000 */

+#define ADC_SMPR1_SMP6                    ADC_SMPR1_SMP6_Msk                   /*!< ADC Channel 6 Sampling time selection  */

+#define ADC_SMPR1_SMP6_0                  (0x1UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00040000 */

+#define ADC_SMPR1_SMP6_1                  (0x2UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00080000 */

+#define ADC_SMPR1_SMP6_2                  (0x4UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00100000 */

+

+#define ADC_SMPR1_SMP7_Pos                (21U)

+#define ADC_SMPR1_SMP7_Msk                (0x7UL << ADC_SMPR1_SMP7_Pos)        /*!< 0x00E00000 */

+#define ADC_SMPR1_SMP7                    ADC_SMPR1_SMP7_Msk                   /*!< ADC Channel 7 Sampling time selection  */

+#define ADC_SMPR1_SMP7_0                  (0x1UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00200000 */

+#define ADC_SMPR1_SMP7_1                  (0x2UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00400000 */

+#define ADC_SMPR1_SMP7_2                  (0x4UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00800000 */

+

+#define ADC_SMPR1_SMP8_Pos                (24U)

+#define ADC_SMPR1_SMP8_Msk                (0x7UL << ADC_SMPR1_SMP8_Pos)        /*!< 0x07000000 */

+#define ADC_SMPR1_SMP8                    ADC_SMPR1_SMP8_Msk                   /*!< ADC Channel 8 Sampling time selection  */

+#define ADC_SMPR1_SMP8_0                  (0x1UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x01000000 */

+#define ADC_SMPR1_SMP8_1                  (0x2UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x02000000 */

+#define ADC_SMPR1_SMP8_2                  (0x4UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x04000000 */

+

+#define ADC_SMPR1_SMP9_Pos                (27U)

+#define ADC_SMPR1_SMP9_Msk                (0x7UL << ADC_SMPR1_SMP9_Pos)        /*!< 0x38000000 */

+#define ADC_SMPR1_SMP9                    ADC_SMPR1_SMP9_Msk                   /*!< ADC Channel 9 Sampling time selection  */

+#define ADC_SMPR1_SMP9_0                  (0x1UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x08000000 */

+#define ADC_SMPR1_SMP9_1                  (0x2UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x10000000 */

+#define ADC_SMPR1_SMP9_2                  (0x4UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x20000000 */

+

+/********************  Bit definition for ADC_SMPR2 register  ********************/

+#define ADC_SMPR2_SMP10_Pos               (0U)

+#define ADC_SMPR2_SMP10_Msk               (0x7UL << ADC_SMPR2_SMP10_Pos)       /*!< 0x00000007 */

+#define ADC_SMPR2_SMP10                   ADC_SMPR2_SMP10_Msk                  /*!< ADC Channel 10 Sampling time selection  */

+#define ADC_SMPR2_SMP10_0                 (0x1UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000001 */

+#define ADC_SMPR2_SMP10_1                 (0x2UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000002 */

+#define ADC_SMPR2_SMP10_2                 (0x4UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000004 */

+

+#define ADC_SMPR2_SMP11_Pos               (3U)

+#define ADC_SMPR2_SMP11_Msk               (0x7UL << ADC_SMPR2_SMP11_Pos)       /*!< 0x00000038 */

+#define ADC_SMPR2_SMP11                   ADC_SMPR2_SMP11_Msk                  /*!< ADC Channel 11 Sampling time selection  */

+#define ADC_SMPR2_SMP11_0                 (0x1UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000008 */

+#define ADC_SMPR2_SMP11_1                 (0x2UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000010 */

+#define ADC_SMPR2_SMP11_2                 (0x4UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000020 */

+

+#define ADC_SMPR2_SMP12_Pos               (6U)

+#define ADC_SMPR2_SMP12_Msk               (0x7UL << ADC_SMPR2_SMP12_Pos)       /*!< 0x000001C0 */

+#define ADC_SMPR2_SMP12                   ADC_SMPR2_SMP12_Msk                  /*!< ADC Channel 12 Sampling time selection  */

+#define ADC_SMPR2_SMP12_0                 (0x1UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000040 */

+#define ADC_SMPR2_SMP12_1                 (0x2UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000080 */

+#define ADC_SMPR2_SMP12_2                 (0x4UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000100 */

+

+#define ADC_SMPR2_SMP13_Pos               (9U)

+#define ADC_SMPR2_SMP13_Msk               (0x7UL << ADC_SMPR2_SMP13_Pos)       /*!< 0x00000E00 */

+#define ADC_SMPR2_SMP13                   ADC_SMPR2_SMP13_Msk                  /*!< ADC Channel 13 Sampling time selection  */

+#define ADC_SMPR2_SMP13_0                 (0x1UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000200 */

+#define ADC_SMPR2_SMP13_1                 (0x2UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000400 */

+#define ADC_SMPR2_SMP13_2                 (0x4UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000800 */

+

+#define ADC_SMPR2_SMP14_Pos               (12U)

+#define ADC_SMPR2_SMP14_Msk               (0x7UL << ADC_SMPR2_SMP14_Pos)       /*!< 0x00007000 */

+#define ADC_SMPR2_SMP14                   ADC_SMPR2_SMP14_Msk                  /*!< ADC Channel 14 Sampling time selection  */

+#define ADC_SMPR2_SMP14_0                 (0x1UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00001000 */

+#define ADC_SMPR2_SMP14_1                 (0x2UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00002000 */

+#define ADC_SMPR2_SMP14_2                 (0x4UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00004000 */

+

+#define ADC_SMPR2_SMP15_Pos               (15U)

+#define ADC_SMPR2_SMP15_Msk               (0x7UL << ADC_SMPR2_SMP15_Pos)       /*!< 0x00038000 */

+#define ADC_SMPR2_SMP15                   ADC_SMPR2_SMP15_Msk                  /*!< ADC Channel 15 Sampling time selection  */

+#define ADC_SMPR2_SMP15_0                 (0x1UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00008000 */

+#define ADC_SMPR2_SMP15_1                 (0x2UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00010000 */

+#define ADC_SMPR2_SMP15_2                 (0x4UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00020000 */

+

+#define ADC_SMPR2_SMP16_Pos               (18U)

+#define ADC_SMPR2_SMP16_Msk               (0x7UL << ADC_SMPR2_SMP16_Pos)       /*!< 0x001C0000 */

+#define ADC_SMPR2_SMP16                   ADC_SMPR2_SMP16_Msk                  /*!< ADC Channel 16 Sampling time selection  */

+#define ADC_SMPR2_SMP16_0                 (0x1UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00040000 */

+#define ADC_SMPR2_SMP16_1                 (0x2UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00080000 */

+#define ADC_SMPR2_SMP16_2                 (0x4UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00100000 */

+

+#define ADC_SMPR2_SMP17_Pos               (21U)

+#define ADC_SMPR2_SMP17_Msk               (0x7UL << ADC_SMPR2_SMP17_Pos)       /*!< 0x00E00000 */

+#define ADC_SMPR2_SMP17                   ADC_SMPR2_SMP17_Msk                  /*!< ADC Channel 17 Sampling time selection  */

+#define ADC_SMPR2_SMP17_0                 (0x1UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00200000 */

+#define ADC_SMPR2_SMP17_1                 (0x2UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00400000 */

+#define ADC_SMPR2_SMP17_2                 (0x4UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00800000 */

+

+#define ADC_SMPR2_SMP18_Pos               (24U)

+#define ADC_SMPR2_SMP18_Msk               (0x7UL << ADC_SMPR2_SMP18_Pos)       /*!< 0x07000000 */

+#define ADC_SMPR2_SMP18                   ADC_SMPR2_SMP18_Msk                  /*!< ADC Channel 18 Sampling time selection  */

+#define ADC_SMPR2_SMP18_0                 (0x1UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x01000000 */

+#define ADC_SMPR2_SMP18_1                 (0x2UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x02000000 */

+#define ADC_SMPR2_SMP18_2                 (0x4UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x04000000 */

+

+#define ADC_SMPR2_SMP19_Pos               (27U)

+#define ADC_SMPR2_SMP19_Msk               (0x7UL << ADC_SMPR2_SMP19_Pos)       /*!< 0x38000000 */

+#define ADC_SMPR2_SMP19                   ADC_SMPR2_SMP19_Msk                  /*!< ADC Channel 19 Sampling time selection  */

+#define ADC_SMPR2_SMP19_0                 (0x1UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x08000000 */

+#define ADC_SMPR2_SMP19_1                 (0x2UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x10000000 */

+#define ADC_SMPR2_SMP19_2                 (0x4UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x20000000 */

+

+/********************  Bit definition for ADC_PCSEL register  ********************/

+#define ADC_PCSEL_PCSEL_Pos               (0U)

+#define ADC_PCSEL_PCSEL_Msk               (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)   /*!< 0x000FFFFF */

+#define ADC_PCSEL_PCSEL                   ADC_PCSEL_PCSEL_Msk                  /*!< ADC pre channel selection */

+#define ADC_PCSEL_PCSEL_0                 (0x00001UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */

+#define ADC_PCSEL_PCSEL_1                 (0x00002UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */

+#define ADC_PCSEL_PCSEL_2                 (0x00004UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */

+#define ADC_PCSEL_PCSEL_3                 (0x00008UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */

+#define ADC_PCSEL_PCSEL_4                 (0x00010UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */

+#define ADC_PCSEL_PCSEL_5                 (0x00020UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */

+#define ADC_PCSEL_PCSEL_6                 (0x00040UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */

+#define ADC_PCSEL_PCSEL_7                 (0x00080UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */

+#define ADC_PCSEL_PCSEL_8                 (0x00100UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */

+#define ADC_PCSEL_PCSEL_9                 (0x00200UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */

+#define ADC_PCSEL_PCSEL_10                (0x00400UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */

+#define ADC_PCSEL_PCSEL_11                (0x00800UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */

+#define ADC_PCSEL_PCSEL_12                (0x01000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */

+#define ADC_PCSEL_PCSEL_13                (0x02000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */

+#define ADC_PCSEL_PCSEL_14                (0x04000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */

+#define ADC_PCSEL_PCSEL_15                (0x08000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */

+#define ADC_PCSEL_PCSEL_16                (0x10000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */

+#define ADC_PCSEL_PCSEL_17                (0x20000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */

+#define ADC_PCSEL_PCSEL_18                (0x40000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */

+#define ADC_PCSEL_PCSEL_19                (0x80000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00080000 */

+

+/*****************  Bit definition for ADC_LTR1, 2, 3 registers *****************/

+#define ADC_LTR_LT_Pos                    (0U)

+#define ADC_LTR_LT_Msk                    (0x3FFFFFFUL << ADC_LTR_LT_Pos)      /*!< 0x03FFFFFF */

+#define ADC_LTR_LT                        ADC_LTR_LT_Msk                       /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */

+

+/*****************  Bit definition for ADC_HTR1, 2, 3 registers  ****************/

+#define ADC_HTR_HT_Pos                    (0U)

+#define ADC_HTR_HT_Msk                    (0x3FFFFFFUL << ADC_HTR_HT_Pos)      /*!< 0x03FFFFFF */

+#define ADC_HTR_HT                        ADC_HTR_HT_Msk                       /*!< ADC Analog watchdog 1,2 and 3 higher threshold */

+

+

+/********************  Bit definition for ADC_SQR1 register  ********************/

+#define ADC_SQR1_L_Pos                    (0U)

+#define ADC_SQR1_L_Msk                    (0xFUL << ADC_SQR1_L_Pos)            /*!< 0x0000000F */

+#define ADC_SQR1_L                        ADC_SQR1_L_Msk                       /*!< ADC regular channel sequence lenght */

+#define ADC_SQR1_L_0                      (0x1UL << ADC_SQR1_L_Pos)             /*!< 0x00000001 */

+#define ADC_SQR1_L_1                      (0x2UL << ADC_SQR1_L_Pos)             /*!< 0x00000002 */

+#define ADC_SQR1_L_2                      (0x4UL << ADC_SQR1_L_Pos)             /*!< 0x00000004 */

+#define ADC_SQR1_L_3                      (0x8UL << ADC_SQR1_L_Pos)             /*!< 0x00000008 */

+

+#define ADC_SQR1_SQ1_Pos                  (6U)

+#define ADC_SQR1_SQ1_Msk                  (0x1FUL << ADC_SQR1_SQ1_Pos)         /*!< 0x000007C0 */

+#define ADC_SQR1_SQ1                      ADC_SQR1_SQ1_Msk                     /*!< ADC 1st conversion in regular sequence */

+#define ADC_SQR1_SQ1_0                    (0x01UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000040 */

+#define ADC_SQR1_SQ1_1                    (0x02UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000080 */

+#define ADC_SQR1_SQ1_2                    (0x04UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000100 */

+#define ADC_SQR1_SQ1_3                    (0x08UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000200 */

+#define ADC_SQR1_SQ1_4                    (0x10UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000400 */

+

+#define ADC_SQR1_SQ2_Pos                  (12U)

+#define ADC_SQR1_SQ2_Msk                  (0x1FUL << ADC_SQR1_SQ2_Pos)         /*!< 0x0001F000 */

+#define ADC_SQR1_SQ2                      ADC_SQR1_SQ2_Msk                     /*!< ADC 2nd conversion in regular sequence */

+#define ADC_SQR1_SQ2_0                    (0x01UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00001000 */

+#define ADC_SQR1_SQ2_1                    (0x02UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00002000 */

+#define ADC_SQR1_SQ2_2                    (0x04UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00004000 */

+#define ADC_SQR1_SQ2_3                    (0x08UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00008000 */

+#define ADC_SQR1_SQ2_4                    (0x10UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00010000 */

+

+#define ADC_SQR1_SQ3_Pos                  (18U)

+#define ADC_SQR1_SQ3_Msk                  (0x1FUL << ADC_SQR1_SQ3_Pos)         /*!< 0x007C0000 */

+#define ADC_SQR1_SQ3                      ADC_SQR1_SQ3_Msk                     /*!< ADC 3rd conversion in regular sequence */

+#define ADC_SQR1_SQ3_0                    (0x01UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00040000 */

+#define ADC_SQR1_SQ3_1                    (0x02UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00080000 */

+#define ADC_SQR1_SQ3_2                    (0x04UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00100000 */

+#define ADC_SQR1_SQ3_3                    (0x08UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00200000 */

+#define ADC_SQR1_SQ3_4                    (0x10UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00400000 */

+

+#define ADC_SQR1_SQ4_Pos                  (24U)

+#define ADC_SQR1_SQ4_Msk                  (0x1FUL << ADC_SQR1_SQ4_Pos)         /*!< 0x1F000000 */

+#define ADC_SQR1_SQ4                      ADC_SQR1_SQ4_Msk                     /*!< ADC 4th conversion in regular sequence */

+#define ADC_SQR1_SQ4_0                    (0x01UL << ADC_SQR1_SQ4_Pos)          /*!< 0x01000000 */

+#define ADC_SQR1_SQ4_1                    (0x02UL << ADC_SQR1_SQ4_Pos)          /*!< 0x02000000 */

+#define ADC_SQR1_SQ4_2                    (0x04UL << ADC_SQR1_SQ4_Pos)          /*!< 0x04000000 */

+#define ADC_SQR1_SQ4_3                    (0x08UL << ADC_SQR1_SQ4_Pos)          /*!< 0x08000000 */

+#define ADC_SQR1_SQ4_4                    (0x10UL << ADC_SQR1_SQ4_Pos)          /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR2 register  ********************/

+#define ADC_SQR2_SQ5_Pos                  (0U)

+#define ADC_SQR2_SQ5_Msk                  (0x1FUL << ADC_SQR2_SQ5_Pos)         /*!< 0x0000001F */

+#define ADC_SQR2_SQ5                      ADC_SQR2_SQ5_Msk                     /*!< ADC 5th conversion in regular sequence */

+#define ADC_SQR2_SQ5_0                    (0x01UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000001 */

+#define ADC_SQR2_SQ5_1                    (0x02UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000002 */

+#define ADC_SQR2_SQ5_2                    (0x04UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000004 */

+#define ADC_SQR2_SQ5_3                    (0x08UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000008 */

+#define ADC_SQR2_SQ5_4                    (0x10UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000010 */

+

+#define ADC_SQR2_SQ6_Pos                  (6U)

+#define ADC_SQR2_SQ6_Msk                  (0x1FUL << ADC_SQR2_SQ6_Pos)         /*!< 0x000007C0 */

+#define ADC_SQR2_SQ6                      ADC_SQR2_SQ6_Msk                     /*!< ADC 6th conversion in regular sequence */

+#define ADC_SQR2_SQ6_0                    (0x01UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000040 */

+#define ADC_SQR2_SQ6_1                    (0x02UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000080 */

+#define ADC_SQR2_SQ6_2                    (0x04UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000100 */

+#define ADC_SQR2_SQ6_3                    (0x08UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000200 */

+#define ADC_SQR2_SQ6_4                    (0x10UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000400 */

+

+#define ADC_SQR2_SQ7_Pos                  (12U)

+#define ADC_SQR2_SQ7_Msk                  (0x1FUL << ADC_SQR2_SQ7_Pos)         /*!< 0x0001F000 */

+#define ADC_SQR2_SQ7                      ADC_SQR2_SQ7_Msk                     /*!< ADC 7th conversion in regular sequence */

+#define ADC_SQR2_SQ7_0                    (0x01UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00001000 */

+#define ADC_SQR2_SQ7_1                    (0x02UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00002000 */

+#define ADC_SQR2_SQ7_2                    (0x04UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00004000 */

+#define ADC_SQR2_SQ7_3                    (0x08UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00008000 */

+#define ADC_SQR2_SQ7_4                    (0x10UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00010000 */

+

+#define ADC_SQR2_SQ8_Pos                  (18U)

+#define ADC_SQR2_SQ8_Msk                  (0x1FUL << ADC_SQR2_SQ8_Pos)         /*!< 0x007C0000 */

+#define ADC_SQR2_SQ8                      ADC_SQR2_SQ8_Msk                     /*!< ADC 8th conversion in regular sequence */

+#define ADC_SQR2_SQ8_0                    (0x01UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00040000 */

+#define ADC_SQR2_SQ8_1                    (0x02UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00080000 */

+#define ADC_SQR2_SQ8_2                    (0x04UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00100000 */

+#define ADC_SQR2_SQ8_3                    (0x08UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00200000 */

+#define ADC_SQR2_SQ8_4                    (0x10UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00400000 */

+

+#define ADC_SQR2_SQ9_Pos                  (24U)

+#define ADC_SQR2_SQ9_Msk                  (0x1FUL << ADC_SQR2_SQ9_Pos)         /*!< 0x1F000000 */

+#define ADC_SQR2_SQ9                      ADC_SQR2_SQ9_Msk                     /*!< ADC 9th conversion in regular sequence */

+#define ADC_SQR2_SQ9_0                    (0x01UL << ADC_SQR2_SQ9_Pos)          /*!< 0x01000000 */

+#define ADC_SQR2_SQ9_1                    (0x02UL << ADC_SQR2_SQ9_Pos)          /*!< 0x02000000 */

+#define ADC_SQR2_SQ9_2                    (0x04UL << ADC_SQR2_SQ9_Pos)          /*!< 0x04000000 */

+#define ADC_SQR2_SQ9_3                    (0x08UL << ADC_SQR2_SQ9_Pos)          /*!< 0x08000000 */

+#define ADC_SQR2_SQ9_4                    (0x10UL << ADC_SQR2_SQ9_Pos)          /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR3 register  ********************/

+#define ADC_SQR3_SQ10_Pos                 (0U)

+#define ADC_SQR3_SQ10_Msk                 (0x1FUL << ADC_SQR3_SQ10_Pos)        /*!< 0x0000001F */

+#define ADC_SQR3_SQ10                     ADC_SQR3_SQ10_Msk                    /*!< ADC 10th conversion in regular sequence */

+#define ADC_SQR3_SQ10_0                   (0x01UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000001 */

+#define ADC_SQR3_SQ10_1                   (0x02UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000002 */

+#define ADC_SQR3_SQ10_2                   (0x04UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000004 */

+#define ADC_SQR3_SQ10_3                   (0x08UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000008 */

+#define ADC_SQR3_SQ10_4                   (0x10UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000010 */

+

+#define ADC_SQR3_SQ11_Pos                 (6U)

+#define ADC_SQR3_SQ11_Msk                 (0x1FUL << ADC_SQR3_SQ11_Pos)        /*!< 0x000007C0 */

+#define ADC_SQR3_SQ11                     ADC_SQR3_SQ11_Msk                    /*!< ADC 11th conversion in regular sequence */

+#define ADC_SQR3_SQ11_0                   (0x01UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000040 */

+#define ADC_SQR3_SQ11_1                   (0x02UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000080 */

+#define ADC_SQR3_SQ11_2                   (0x04UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000100 */

+#define ADC_SQR3_SQ11_3                   (0x08UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000200 */

+#define ADC_SQR3_SQ11_4                   (0x10UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000400 */

+

+#define ADC_SQR3_SQ12_Pos                 (12U)

+#define ADC_SQR3_SQ12_Msk                 (0x1FUL << ADC_SQR3_SQ12_Pos)        /*!< 0x0001F000 */

+#define ADC_SQR3_SQ12                     ADC_SQR3_SQ12_Msk                    /*!< ADC 12th conversion in regular sequence */

+#define ADC_SQR3_SQ12_0                   (0x01UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00001000 */

+#define ADC_SQR3_SQ12_1                   (0x02UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00002000 */

+#define ADC_SQR3_SQ12_2                   (0x04UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00004000 */

+#define ADC_SQR3_SQ12_3                   (0x08UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00008000 */

+#define ADC_SQR3_SQ12_4                   (0x10UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00010000 */

+

+#define ADC_SQR3_SQ13_Pos                 (18U)

+#define ADC_SQR3_SQ13_Msk                 (0x1FUL << ADC_SQR3_SQ13_Pos)        /*!< 0x007C0000 */

+#define ADC_SQR3_SQ13                     ADC_SQR3_SQ13_Msk                    /*!< ADC 13th conversion in regular sequence */

+#define ADC_SQR3_SQ13_0                   (0x01UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00040000 */

+#define ADC_SQR3_SQ13_1                   (0x02UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00080000 */

+#define ADC_SQR3_SQ13_2                   (0x04UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00100000 */

+#define ADC_SQR3_SQ13_3                   (0x08UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00200000 */

+#define ADC_SQR3_SQ13_4                   (0x10UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00400000 */

+

+#define ADC_SQR3_SQ14_Pos                 (24U)

+#define ADC_SQR3_SQ14_Msk                 (0x1FUL << ADC_SQR3_SQ14_Pos)        /*!< 0x1F000000 */

+#define ADC_SQR3_SQ14                     ADC_SQR3_SQ14_Msk                    /*!< ADC 14th conversion in regular sequence */

+#define ADC_SQR3_SQ14_0                   (0x01UL << ADC_SQR3_SQ14_Pos)         /*!< 0x01000000 */

+#define ADC_SQR3_SQ14_1                   (0x02UL << ADC_SQR3_SQ14_Pos)         /*!< 0x02000000 */

+#define ADC_SQR3_SQ14_2                   (0x04UL << ADC_SQR3_SQ14_Pos)         /*!< 0x04000000 */

+#define ADC_SQR3_SQ14_3                   (0x08UL << ADC_SQR3_SQ14_Pos)         /*!< 0x08000000 */

+#define ADC_SQR3_SQ14_4                   (0x10UL << ADC_SQR3_SQ14_Pos)         /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR4 register  ********************/

+#define ADC_SQR4_SQ15_Pos                 (0U)

+#define ADC_SQR4_SQ15_Msk                 (0x1FUL << ADC_SQR4_SQ15_Pos)        /*!< 0x0000001F */

+#define ADC_SQR4_SQ15                     ADC_SQR4_SQ15_Msk                    /*!< ADC 15th conversion in regular sequence */

+#define ADC_SQR4_SQ15_0                   (0x01UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000001 */

+#define ADC_SQR4_SQ15_1                   (0x02UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000002 */

+#define ADC_SQR4_SQ15_2                   (0x04UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000004 */

+#define ADC_SQR4_SQ15_3                   (0x08UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000008 */

+#define ADC_SQR4_SQ15_4                   (0x10UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000010 */

+

+#define ADC_SQR4_SQ16_Pos                 (6U)

+#define ADC_SQR4_SQ16_Msk                 (0x1FUL << ADC_SQR4_SQ16_Pos)        /*!< 0x000007C0 */

+#define ADC_SQR4_SQ16                     ADC_SQR4_SQ16_Msk                    /*!< ADC 16th conversion in regular sequence */

+#define ADC_SQR4_SQ16_0                   (0x01UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000040 */

+#define ADC_SQR4_SQ16_1                   (0x02UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000080 */

+#define ADC_SQR4_SQ16_2                   (0x04UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000100 */

+#define ADC_SQR4_SQ16_3                   (0x08UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000200 */

+#define ADC_SQR4_SQ16_4                   (0x10UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000400 */

+/********************  Bit definition for ADC_DR register  ********************/

+#define ADC_DR_RDATA_Pos                  (0U)

+#define ADC_DR_RDATA_Msk                  (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)   /*!< 0xFFFFFFFF */

+#define ADC_DR_RDATA                      ADC_DR_RDATA_Msk                     /*!< ADC regular Data converted */

+

+/********************  Bit definition for ADC_JSQR register  ********************/

+#define ADC_JSQR_JL_Pos                   (0U)

+#define ADC_JSQR_JL_Msk                   (0x3UL << ADC_JSQR_JL_Pos)           /*!< 0x00000003 */

+#define ADC_JSQR_JL                       ADC_JSQR_JL_Msk                      /*!< ADC injected channel sequence length */

+#define ADC_JSQR_JL_0                     (0x1UL << ADC_JSQR_JL_Pos)           /*!< 0x00000001 */

+#define ADC_JSQR_JL_1                     (0x2UL << ADC_JSQR_JL_Pos)           /*!< 0x00000002 */

+

+#define ADC_JSQR_JEXTSEL_Pos              (2U)

+#define ADC_JSQR_JEXTSEL_Msk              (0x1FUL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x0000007C */

+#define ADC_JSQR_JEXTSEL                  ADC_JSQR_JEXTSEL_Msk                 /*!< ADC external trigger selection for injected group */

+#define ADC_JSQR_JEXTSEL_0                (0x01UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000004 */

+#define ADC_JSQR_JEXTSEL_1                (0x02UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000008 */

+#define ADC_JSQR_JEXTSEL_2                (0x04UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000010 */

+#define ADC_JSQR_JEXTSEL_3                (0x08UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000020 */

+#define ADC_JSQR_JEXTSEL_4                (0x10UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000040 */

+

+#define ADC_JSQR_JEXTEN_Pos               (7U)

+#define ADC_JSQR_JEXTEN_Msk               (0x3UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000180 */

+#define ADC_JSQR_JEXTEN                   ADC_JSQR_JEXTEN_Msk                  /*!< ADC external trigger enable and polarity selection for injected channels */

+#define ADC_JSQR_JEXTEN_0                 (0x1UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000080 */

+#define ADC_JSQR_JEXTEN_1                 (0x2UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000100 */

+

+#define ADC_JSQR_JSQ1_Pos                 (9U)

+#define ADC_JSQR_JSQ1_Msk                 (0x1FUL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00003E00 */

+#define ADC_JSQR_JSQ1                     ADC_JSQR_JSQ1_Msk                    /*!< ADC 1st conversion in injected sequence */

+#define ADC_JSQR_JSQ1_0                   (0x01UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000200 */

+#define ADC_JSQR_JSQ1_1                   (0x02UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000400 */

+#define ADC_JSQR_JSQ1_2                   (0x04UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000800 */

+#define ADC_JSQR_JSQ1_3                   (0x08UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00001000 */

+#define ADC_JSQR_JSQ1_4                   (0x10UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00002000 */

+

+#define ADC_JSQR_JSQ2_Pos                 (15U)

+#define ADC_JSQR_JSQ2_Msk                 (0x1FUL << ADC_JSQR_JSQ2_Pos)        /*!< 0x000F8000 */

+#define ADC_JSQR_JSQ2                     ADC_JSQR_JSQ2_Msk                    /*!< ADC 2nd conversion in injected sequence */

+#define ADC_JSQR_JSQ2_0                   (0x01UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00008000 */

+#define ADC_JSQR_JSQ2_1                   (0x02UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00010000 */

+#define ADC_JSQR_JSQ2_2                   (0x04UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00020000 */

+#define ADC_JSQR_JSQ2_3                   (0x08UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00040000 */

+#define ADC_JSQR_JSQ2_4                   (0x10UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00080000 */

+

+#define ADC_JSQR_JSQ3_Pos                 (21U)

+#define ADC_JSQR_JSQ3_Msk                 (0x1FUL << ADC_JSQR_JSQ3_Pos)        /*!< 0x03E00000 */

+#define ADC_JSQR_JSQ3                     ADC_JSQR_JSQ3_Msk                    /*!< ADC 3rd conversion in injected sequence */

+#define ADC_JSQR_JSQ3_0                   (0x01UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00200000 */

+#define ADC_JSQR_JSQ3_1                   (0x02UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00400000 */

+#define ADC_JSQR_JSQ3_2                   (0x04UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00800000 */

+#define ADC_JSQR_JSQ3_3                   (0x08UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x01000000 */

+#define ADC_JSQR_JSQ3_4                   (0x10UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x02000000 */

+

+#define ADC_JSQR_JSQ4_Pos                 (27U)

+#define ADC_JSQR_JSQ4_Msk                 (0x1FUL << ADC_JSQR_JSQ4_Pos)        /*!< 0xF8000000 */

+#define ADC_JSQR_JSQ4                     ADC_JSQR_JSQ4_Msk                    /*!< ADC 4th conversion in injected sequence */

+#define ADC_JSQR_JSQ4_0                   (0x01UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x08000000 */

+#define ADC_JSQR_JSQ4_1                   (0x02UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x10000000 */

+#define ADC_JSQR_JSQ4_2                   (0x04UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x20000000 */

+#define ADC_JSQR_JSQ4_3                   (0x08UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x40000000 */

+#define ADC_JSQR_JSQ4_4                   (0x10UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_OFR1 register  ********************/

+#define ADC_OFR1_OFFSET1_Pos              (0U)

+#define ADC_OFR1_OFFSET1_Msk              (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR1_OFFSET1                  ADC_OFR1_OFFSET1_Msk                  /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */

+#define ADC_OFR1_OFFSET1_0                (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */

+#define ADC_OFR1_OFFSET1_1                (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */

+#define ADC_OFR1_OFFSET1_2                (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */

+#define ADC_OFR1_OFFSET1_3                (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */

+#define ADC_OFR1_OFFSET1_4                (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */

+#define ADC_OFR1_OFFSET1_5                (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */

+#define ADC_OFR1_OFFSET1_6                (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */

+#define ADC_OFR1_OFFSET1_7                (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */

+#define ADC_OFR1_OFFSET1_8                (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */

+#define ADC_OFR1_OFFSET1_9                (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */

+#define ADC_OFR1_OFFSET1_10               (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */

+#define ADC_OFR1_OFFSET1_11               (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */

+#define ADC_OFR1_OFFSET1_12               (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */

+#define ADC_OFR1_OFFSET1_13               (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */

+#define ADC_OFR1_OFFSET1_14               (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */

+#define ADC_OFR1_OFFSET1_15               (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */

+#define ADC_OFR1_OFFSET1_16               (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */

+#define ADC_OFR1_OFFSET1_17               (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */

+#define ADC_OFR1_OFFSET1_18               (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */

+#define ADC_OFR1_OFFSET1_19               (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */

+#define ADC_OFR1_OFFSET1_20               (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */

+#define ADC_OFR1_OFFSET1_21               (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */

+#define ADC_OFR1_OFFSET1_22               (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */

+#define ADC_OFR1_OFFSET1_23               (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */

+#define ADC_OFR1_OFFSET1_24               (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */

+#define ADC_OFR1_OFFSET1_25               (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR1_OFFSET1_CH_Pos           (26U)

+#define ADC_OFR1_OFFSET1_CH_Msk           (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR1_OFFSET1_CH               ADC_OFR1_OFFSET1_CH_Msk               /*!< ADC Channel selection for the data offset 1 */

+#define ADC_OFR1_OFFSET1_CH_0             (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR1_OFFSET1_CH_1             (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR1_OFFSET1_CH_2             (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR1_OFFSET1_CH_3             (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR1_OFFSET1_CH_4             (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR1_SSATE_Pos                (31U)

+#define ADC_OFR1_SSATE_Msk                (0x1UL << ADC_OFR1_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR1_SSATE                    ADC_OFR1_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR2 register  ********************/

+#define ADC_OFR2_OFFSET2_Pos              (0U)

+#define ADC_OFR2_OFFSET2_Msk              (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR2_OFFSET2                  ADC_OFR2_OFFSET2_Msk                  /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */

+#define ADC_OFR2_OFFSET2_0                (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */

+#define ADC_OFR2_OFFSET2_1                (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */

+#define ADC_OFR2_OFFSET2_2                (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */

+#define ADC_OFR2_OFFSET2_3                (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */

+#define ADC_OFR2_OFFSET2_4                (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */

+#define ADC_OFR2_OFFSET2_5                (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */

+#define ADC_OFR2_OFFSET2_6                (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */

+#define ADC_OFR2_OFFSET2_7                (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */

+#define ADC_OFR2_OFFSET2_8                (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */

+#define ADC_OFR2_OFFSET2_9                (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */

+#define ADC_OFR2_OFFSET2_10               (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */

+#define ADC_OFR2_OFFSET2_11               (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */

+#define ADC_OFR2_OFFSET2_12               (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */

+#define ADC_OFR2_OFFSET2_13               (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */

+#define ADC_OFR2_OFFSET2_14               (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */

+#define ADC_OFR2_OFFSET2_15               (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */

+#define ADC_OFR2_OFFSET2_16               (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */

+#define ADC_OFR2_OFFSET2_17               (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */

+#define ADC_OFR2_OFFSET2_18               (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */

+#define ADC_OFR2_OFFSET2_19               (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */

+#define ADC_OFR2_OFFSET2_20               (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */

+#define ADC_OFR2_OFFSET2_21               (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */

+#define ADC_OFR2_OFFSET2_22               (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */

+#define ADC_OFR2_OFFSET2_23               (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */

+#define ADC_OFR2_OFFSET2_24               (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */

+#define ADC_OFR2_OFFSET2_25               (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR2_OFFSET2_CH_Pos           (26U)

+#define ADC_OFR2_OFFSET2_CH_Msk           (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR2_OFFSET2_CH               ADC_OFR2_OFFSET2_CH_Msk               /*!< ADC Channel selection for the data offset 2 */

+#define ADC_OFR2_OFFSET2_CH_0             (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR2_OFFSET2_CH_1             (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR2_OFFSET2_CH_2             (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR2_OFFSET2_CH_3             (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR2_OFFSET2_CH_4             (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR2_SSATE_Pos                (31U)

+#define ADC_OFR2_SSATE_Msk                (0x1UL << ADC_OFR2_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR2_SSATE                    ADC_OFR2_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR3 register  ********************/

+#define ADC_OFR3_OFFSET3_Pos              (0U)

+#define ADC_OFR3_OFFSET3_Msk              (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR3_OFFSET3                  ADC_OFR3_OFFSET3_Msk                  /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */

+#define ADC_OFR3_OFFSET3_0                (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */

+#define ADC_OFR3_OFFSET3_1                (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */

+#define ADC_OFR3_OFFSET3_2                (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */

+#define ADC_OFR3_OFFSET3_3                (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */

+#define ADC_OFR3_OFFSET3_4                (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */

+#define ADC_OFR3_OFFSET3_5                (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */

+#define ADC_OFR3_OFFSET3_6                (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */

+#define ADC_OFR3_OFFSET3_7                (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */

+#define ADC_OFR3_OFFSET3_8                (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */

+#define ADC_OFR3_OFFSET3_9                (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */

+#define ADC_OFR3_OFFSET3_10               (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */

+#define ADC_OFR3_OFFSET3_11               (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */

+#define ADC_OFR3_OFFSET3_12               (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */

+#define ADC_OFR3_OFFSET3_13               (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */

+#define ADC_OFR3_OFFSET3_14               (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */

+#define ADC_OFR3_OFFSET3_15               (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */

+#define ADC_OFR3_OFFSET3_16               (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */

+#define ADC_OFR3_OFFSET3_17               (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */

+#define ADC_OFR3_OFFSET3_18               (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */

+#define ADC_OFR3_OFFSET3_19               (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */

+#define ADC_OFR3_OFFSET3_20               (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */

+#define ADC_OFR3_OFFSET3_21               (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */

+#define ADC_OFR3_OFFSET3_22               (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */

+#define ADC_OFR3_OFFSET3_23               (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */

+#define ADC_OFR3_OFFSET3_24               (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */

+#define ADC_OFR3_OFFSET3_25               (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR3_OFFSET3_CH_Pos           (26U)

+#define ADC_OFR3_OFFSET3_CH_Msk           (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR3_OFFSET3_CH               ADC_OFR3_OFFSET3_CH_Msk               /*!< ADC Channel selection for the data offset 3 */

+#define ADC_OFR3_OFFSET3_CH_0             (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR3_OFFSET3_CH_1             (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR3_OFFSET3_CH_2             (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR3_OFFSET3_CH_3             (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR3_OFFSET3_CH_4             (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR3_SSATE_Pos                (31U)

+#define ADC_OFR3_SSATE_Msk                (0x1UL << ADC_OFR3_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR3_SSATE                    ADC_OFR3_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR4 register  ********************/

+#define ADC_OFR4_OFFSET4_Pos              (0U)

+#define ADC_OFR4_OFFSET4_Msk              (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR4_OFFSET4                  ADC_OFR4_OFFSET4_Msk                  /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */

+#define ADC_OFR4_OFFSET4_0                (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */

+#define ADC_OFR4_OFFSET4_1                (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */

+#define ADC_OFR4_OFFSET4_2                (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */

+#define ADC_OFR4_OFFSET4_3                (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */

+#define ADC_OFR4_OFFSET4_4                (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */

+#define ADC_OFR4_OFFSET4_5                (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */

+#define ADC_OFR4_OFFSET4_6                (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */

+#define ADC_OFR4_OFFSET4_7                (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */

+#define ADC_OFR4_OFFSET4_8                (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */

+#define ADC_OFR4_OFFSET4_9                (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */

+#define ADC_OFR4_OFFSET4_10               (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */

+#define ADC_OFR4_OFFSET4_11               (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */

+#define ADC_OFR4_OFFSET4_12               (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */

+#define ADC_OFR4_OFFSET4_13               (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */

+#define ADC_OFR4_OFFSET4_14               (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */

+#define ADC_OFR4_OFFSET4_15               (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */

+#define ADC_OFR4_OFFSET4_16               (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */

+#define ADC_OFR4_OFFSET4_17               (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */

+#define ADC_OFR4_OFFSET4_18               (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */

+#define ADC_OFR4_OFFSET4_19               (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */

+#define ADC_OFR4_OFFSET4_20               (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */

+#define ADC_OFR4_OFFSET4_21               (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */

+#define ADC_OFR4_OFFSET4_22               (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */

+#define ADC_OFR4_OFFSET4_23               (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */

+#define ADC_OFR4_OFFSET4_24               (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */

+#define ADC_OFR4_OFFSET4_25               (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR4_OFFSET4_CH_Pos           (26U)

+#define ADC_OFR4_OFFSET4_CH_Msk           (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR4_OFFSET4_CH               ADC_OFR4_OFFSET4_CH_Msk               /*!< ADC Channel selection for the data offset 4 */

+#define ADC_OFR4_OFFSET4_CH_0             (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR4_OFFSET4_CH_1             (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR4_OFFSET4_CH_2             (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR4_OFFSET4_CH_3             (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR4_OFFSET4_CH_4             (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR4_SSATE_Pos                (31U)

+#define ADC_OFR4_SSATE_Msk                (0x1UL << ADC_OFR4_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR4_SSATE                    ADC_OFR4_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_JDR1 register  ********************/

+#define ADC_JDR1_JDATA_Pos                (0U)

+#define ADC_JDR1_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR1_JDATA                    ADC_JDR1_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR1_JDATA_0                  (0x00000001UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR1_JDATA_1                  (0x00000002UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR1_JDATA_2                  (0x00000004UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR1_JDATA_3                  (0x00000008UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR1_JDATA_4                  (0x00000010UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR1_JDATA_5                  (0x00000020UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR1_JDATA_6                  (0x00000040UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR1_JDATA_7                  (0x00000080UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR1_JDATA_8                  (0x00000100UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR1_JDATA_9                  (0x00000200UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR1_JDATA_10                 (0x00000400UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR1_JDATA_11                 (0x00000800UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR1_JDATA_12                 (0x00001000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR1_JDATA_13                 (0x00002000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR1_JDATA_14                 (0x00004000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR1_JDATA_15                 (0x00008000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR1_JDATA_16                 (0x00010000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR1_JDATA_17                 (0x00020000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR1_JDATA_18                 (0x00040000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR1_JDATA_19                 (0x00080000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR1_JDATA_20                 (0x00100000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR1_JDATA_21                 (0x00200000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR1_JDATA_22                 (0x00400000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR1_JDATA_23                 (0x00800000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR1_JDATA_24                 (0x01000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR1_JDATA_25                 (0x02000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR1_JDATA_26                 (0x04000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR1_JDATA_27                 (0x08000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR1_JDATA_28                 (0x10000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR1_JDATA_29                 (0x20000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR1_JDATA_30                 (0x40000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR1_JDATA_31                 (0x80000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR2 register  ********************/

+#define ADC_JDR2_JDATA_Pos                (0U)

+#define ADC_JDR2_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR2_JDATA                    ADC_JDR2_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR2_JDATA_0                  (0x00000001UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR2_JDATA_1                  (0x00000002UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR2_JDATA_2                  (0x00000004UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR2_JDATA_3                  (0x00000008UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR2_JDATA_4                  (0x00000010UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR2_JDATA_5                  (0x00000020UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR2_JDATA_6                  (0x00000040UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR2_JDATA_7                  (0x00000080UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR2_JDATA_8                  (0x00000100UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR2_JDATA_9                  (0x00000200UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR2_JDATA_10                 (0x00000400UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR2_JDATA_11                 (0x00000800UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR2_JDATA_12                 (0x00001000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR2_JDATA_13                 (0x00002000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR2_JDATA_14                 (0x00004000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR2_JDATA_15                 (0x00008000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR2_JDATA_16                 (0x00010000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR2_JDATA_17                 (0x00020000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR2_JDATA_18                 (0x00040000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR2_JDATA_19                 (0x00080000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR2_JDATA_20                 (0x00100000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR2_JDATA_21                 (0x00200000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR2_JDATA_22                 (0x00400000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR2_JDATA_23                 (0x00800000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR2_JDATA_24                 (0x01000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR2_JDATA_25                 (0x02000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR2_JDATA_26                 (0x04000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR2_JDATA_27                 (0x08000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR2_JDATA_28                 (0x10000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR2_JDATA_29                 (0x20000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR2_JDATA_30                 (0x40000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR2_JDATA_31                 (0x80000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR3 register  ********************/

+#define ADC_JDR3_JDATA_Pos                (0U)

+#define ADC_JDR3_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR3_JDATA                    ADC_JDR3_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR3_JDATA_0                  (0x00000001UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR3_JDATA_1                  (0x00000002UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR3_JDATA_2                  (0x00000004UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR3_JDATA_3                  (0x00000008UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR3_JDATA_4                  (0x00000010UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR3_JDATA_5                  (0x00000020UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR3_JDATA_6                  (0x00000040UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR3_JDATA_7                  (0x00000080UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR3_JDATA_8                  (0x00000100UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR3_JDATA_9                  (0x00000200UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR3_JDATA_10                 (0x00000400UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR3_JDATA_11                 (0x00000800UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR3_JDATA_12                 (0x00001000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR3_JDATA_13                 (0x00002000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR3_JDATA_14                 (0x00004000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR3_JDATA_15                 (0x00008000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR3_JDATA_16                 (0x00010000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR3_JDATA_17                 (0x00020000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR3_JDATA_18                 (0x00040000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR3_JDATA_19                 (0x00080000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR3_JDATA_20                 (0x00100000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR3_JDATA_21                 (0x00200000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR3_JDATA_22                 (0x00400000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR3_JDATA_23                 (0x00800000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR3_JDATA_24                 (0x01000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR3_JDATA_25                 (0x02000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR3_JDATA_26                 (0x04000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR3_JDATA_27                 (0x08000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR3_JDATA_28                 (0x10000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR3_JDATA_29                 (0x20000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR3_JDATA_30                 (0x40000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR3_JDATA_31                 (0x80000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR4 register  ********************/

+#define ADC_JDR4_JDATA_Pos                (0U)

+#define ADC_JDR4_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR4_JDATA                    ADC_JDR4_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR4_JDATA_0                  (0x00000001UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR4_JDATA_1                  (0x00000002UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR4_JDATA_2                  (0x00000004UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR4_JDATA_3                  (0x00000008UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR4_JDATA_4                  (0x00000010UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR4_JDATA_5                  (0x00000020UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR4_JDATA_6                  (0x00000040UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR4_JDATA_7                  (0x00000080UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR4_JDATA_8                  (0x00000100UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR4_JDATA_9                  (0x00000200UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR4_JDATA_10                 (0x00000400UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR4_JDATA_11                 (0x00000800UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR4_JDATA_12                 (0x00001000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR4_JDATA_13                 (0x00002000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR4_JDATA_14                 (0x00004000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR4_JDATA_15                 (0x00008000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR4_JDATA_16                 (0x00010000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR4_JDATA_17                 (0x00020000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR4_JDATA_18                 (0x00040000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR4_JDATA_19                 (0x00080000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR4_JDATA_20                 (0x00100000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR4_JDATA_21                 (0x00200000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR4_JDATA_22                 (0x00400000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR4_JDATA_23                 (0x00800000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR4_JDATA_24                 (0x01000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR4_JDATA_25                 (0x02000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR4_JDATA_26                 (0x04000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR4_JDATA_27                 (0x08000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR4_JDATA_28                 (0x10000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR4_JDATA_29                 (0x20000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR4_JDATA_30                 (0x40000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR4_JDATA_31                 (0x80000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_AWD2CR register  ********************/

+#define ADC_AWD2CR_AWD2CH_Pos             (0U)

+#define ADC_AWD2CR_AWD2CH_Msk             (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x000FFFFF */

+#define ADC_AWD2CR_AWD2CH                 ADC_AWD2CR_AWD2CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */

+#define ADC_AWD2CR_AWD2CH_0               (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000001 */

+#define ADC_AWD2CR_AWD2CH_1               (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000002 */

+#define ADC_AWD2CR_AWD2CH_2               (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000004 */

+#define ADC_AWD2CR_AWD2CH_3               (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000008 */

+#define ADC_AWD2CR_AWD2CH_4               (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000010 */

+#define ADC_AWD2CR_AWD2CH_5               (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000020 */

+#define ADC_AWD2CR_AWD2CH_6               (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000040 */

+#define ADC_AWD2CR_AWD2CH_7               (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000080 */

+#define ADC_AWD2CR_AWD2CH_8               (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000100 */

+#define ADC_AWD2CR_AWD2CH_9               (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000200 */

+#define ADC_AWD2CR_AWD2CH_10              (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000400 */

+#define ADC_AWD2CR_AWD2CH_11              (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000800 */

+#define ADC_AWD2CR_AWD2CH_12              (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00001000 */

+#define ADC_AWD2CR_AWD2CH_13              (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00002000 */

+#define ADC_AWD2CR_AWD2CH_14              (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00004000 */

+#define ADC_AWD2CR_AWD2CH_15              (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00008000 */

+#define ADC_AWD2CR_AWD2CH_16              (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00010000 */

+#define ADC_AWD2CR_AWD2CH_17              (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00020000 */

+#define ADC_AWD2CR_AWD2CH_18              (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */

+#define ADC_AWD2CR_AWD2CH_19              (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_AWD3CR register  ********************/

+#define ADC_AWD3CR_AWD3CH_Pos             (0U)

+#define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x000FFFFF */

+#define ADC_AWD3CR_AWD3CH                 ADC_AWD3CR_AWD3CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */

+#define ADC_AWD3CR_AWD3CH_0               (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000001 */

+#define ADC_AWD3CR_AWD3CH_1               (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000002 */

+#define ADC_AWD3CR_AWD3CH_2               (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000004 */

+#define ADC_AWD3CR_AWD3CH_3               (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000008 */

+#define ADC_AWD3CR_AWD3CH_4               (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000010 */

+#define ADC_AWD3CR_AWD3CH_5               (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000020 */

+#define ADC_AWD3CR_AWD3CH_6               (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000040 */

+#define ADC_AWD3CR_AWD3CH_7               (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000080 */

+#define ADC_AWD3CR_AWD3CH_8               (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000100 */

+#define ADC_AWD3CR_AWD3CH_9               (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000200 */

+#define ADC_AWD3CR_AWD3CH_10              (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000400 */

+#define ADC_AWD3CR_AWD3CH_11              (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000800 */

+#define ADC_AWD3CR_AWD3CH_12              (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00001000 */

+#define ADC_AWD3CR_AWD3CH_13              (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00002000 */

+#define ADC_AWD3CR_AWD3CH_14              (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00004000 */

+#define ADC_AWD3CR_AWD3CH_15              (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00008000 */

+#define ADC_AWD3CR_AWD3CH_16              (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00010000 */

+#define ADC_AWD3CR_AWD3CH_17              (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00020000 */

+#define ADC_AWD3CR_AWD3CH_18              (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */

+#define ADC_AWD3CR_AWD3CH_19              (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_DIFSEL register  ********************/

+#define ADC_DIFSEL_DIFSEL_Pos             (0U)

+#define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */

+#define ADC_DIFSEL_DIFSEL                 ADC_DIFSEL_DIFSEL_Msk                 /*!< ADC differential modes for channels 1 to 18 */

+#define ADC_DIFSEL_DIFSEL_0               (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000001 */

+#define ADC_DIFSEL_DIFSEL_1               (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000002 */

+#define ADC_DIFSEL_DIFSEL_2               (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000004 */

+#define ADC_DIFSEL_DIFSEL_3               (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000008 */

+#define ADC_DIFSEL_DIFSEL_4               (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000010 */

+#define ADC_DIFSEL_DIFSEL_5               (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000020 */

+#define ADC_DIFSEL_DIFSEL_6               (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000040 */

+#define ADC_DIFSEL_DIFSEL_7               (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000080 */

+#define ADC_DIFSEL_DIFSEL_8               (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000100 */

+#define ADC_DIFSEL_DIFSEL_9               (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000200 */

+#define ADC_DIFSEL_DIFSEL_10              (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000400 */

+#define ADC_DIFSEL_DIFSEL_11              (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000800 */

+#define ADC_DIFSEL_DIFSEL_12              (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00001000 */

+#define ADC_DIFSEL_DIFSEL_13              (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00002000 */

+#define ADC_DIFSEL_DIFSEL_14              (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00004000 */

+#define ADC_DIFSEL_DIFSEL_15              (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00008000 */

+#define ADC_DIFSEL_DIFSEL_16              (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00010000 */

+#define ADC_DIFSEL_DIFSEL_17              (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00020000 */

+#define ADC_DIFSEL_DIFSEL_18              (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00040000 */

+#define ADC_DIFSEL_DIFSEL_19              (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_CALFACT register  ********************/

+#define ADC_CALFACT_CALFACT_S_Pos         (0U)

+#define ADC_CALFACT_CALFACT_S_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */

+#define ADC_CALFACT_CALFACT_S             ADC_CALFACT_CALFACT_S_Msk              /*!< ADC calibration factors in single-ended mode */

+#define ADC_CALFACT_CALFACT_S_0           (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */

+#define ADC_CALFACT_CALFACT_S_1           (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */

+#define ADC_CALFACT_CALFACT_S_2           (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */

+#define ADC_CALFACT_CALFACT_S_3           (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */

+#define ADC_CALFACT_CALFACT_S_4           (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */

+#define ADC_CALFACT_CALFACT_S_5           (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */

+#define ADC_CALFACT_CALFACT_S_6           (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */

+#define ADC_CALFACT_CALFACT_S_7           (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */

+#define ADC_CALFACT_CALFACT_S_8           (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */

+#define ADC_CALFACT_CALFACT_S_9           (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */

+#define ADC_CALFACT_CALFACT_S_10          (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */

+#define ADC_CALFACT_CALFACT_D_Pos         (16U)

+#define ADC_CALFACT_CALFACT_D_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */

+#define ADC_CALFACT_CALFACT_D             ADC_CALFACT_CALFACT_D_Msk              /*!< ADC calibration factors in differential mode */

+#define ADC_CALFACT_CALFACT_D_0           (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */

+#define ADC_CALFACT_CALFACT_D_1           (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */

+#define ADC_CALFACT_CALFACT_D_2           (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */

+#define ADC_CALFACT_CALFACT_D_3           (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */

+#define ADC_CALFACT_CALFACT_D_4           (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */

+#define ADC_CALFACT_CALFACT_D_5           (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */

+#define ADC_CALFACT_CALFACT_D_6           (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */

+#define ADC_CALFACT_CALFACT_D_7           (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */

+#define ADC_CALFACT_CALFACT_D_8           (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */

+#define ADC_CALFACT_CALFACT_D_9           (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */

+#define ADC_CALFACT_CALFACT_D_10          (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */

+

+/********************  Bit definition for ADC_CALFACT2 register  ********************/

+#define ADC_CALFACT2_LINCALFACT_Pos       (0U)

+#define ADC_CALFACT2_LINCALFACT_Msk       (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */

+#define ADC_CALFACT2_LINCALFACT           ADC_CALFACT2_LINCALFACT_Msk                   /*!< ADC Linearity calibration factors */

+#define ADC_CALFACT2_LINCALFACT_0         (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */

+#define ADC_CALFACT2_LINCALFACT_1         (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */

+#define ADC_CALFACT2_LINCALFACT_2         (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */

+#define ADC_CALFACT2_LINCALFACT_3         (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */

+#define ADC_CALFACT2_LINCALFACT_4         (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */

+#define ADC_CALFACT2_LINCALFACT_5         (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */

+#define ADC_CALFACT2_LINCALFACT_6         (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */

+#define ADC_CALFACT2_LINCALFACT_7         (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */

+#define ADC_CALFACT2_LINCALFACT_8         (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */

+#define ADC_CALFACT2_LINCALFACT_9         (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */

+#define ADC_CALFACT2_LINCALFACT_10        (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */

+#define ADC_CALFACT2_LINCALFACT_11        (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */

+#define ADC_CALFACT2_LINCALFACT_12        (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */

+#define ADC_CALFACT2_LINCALFACT_13        (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */

+#define ADC_CALFACT2_LINCALFACT_14        (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */

+#define ADC_CALFACT2_LINCALFACT_15        (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */

+#define ADC_CALFACT2_LINCALFACT_16        (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */

+#define ADC_CALFACT2_LINCALFACT_17        (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */

+#define ADC_CALFACT2_LINCALFACT_18        (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */

+#define ADC_CALFACT2_LINCALFACT_19        (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */

+#define ADC_CALFACT2_LINCALFACT_20        (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */

+#define ADC_CALFACT2_LINCALFACT_21        (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */

+#define ADC_CALFACT2_LINCALFACT_22        (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */

+#define ADC_CALFACT2_LINCALFACT_23        (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */

+#define ADC_CALFACT2_LINCALFACT_24        (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */

+#define ADC_CALFACT2_LINCALFACT_25        (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */

+#define ADC_CALFACT2_LINCALFACT_26        (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */

+#define ADC_CALFACT2_LINCALFACT_27        (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */

+#define ADC_CALFACT2_LINCALFACT_28        (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */

+#define ADC_CALFACT2_LINCALFACT_29        (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */

+

+/*************************  ADC Common registers  *****************************/

+/********************  Bit definition for ADC_CSR register  ********************/

+#define ADC_CSR_ADRDY_MST_Pos             (0U)

+#define ADC_CSR_ADRDY_MST_Msk             (0x1UL << ADC_CSR_ADRDY_MST_Pos)     /*!< 0x00000001 */

+#define ADC_CSR_ADRDY_MST                 ADC_CSR_ADRDY_MST_Msk                /*!< Master ADC ready */

+#define ADC_CSR_EOSMP_MST_Pos             (1U)

+#define ADC_CSR_EOSMP_MST_Msk             (0x1UL << ADC_CSR_EOSMP_MST_Pos)     /*!< 0x00000002 */

+#define ADC_CSR_EOSMP_MST                 ADC_CSR_EOSMP_MST_Msk                /*!< End of sampling phase flag of the master ADC */

+#define ADC_CSR_EOC_MST_Pos               (2U)

+#define ADC_CSR_EOC_MST_Msk               (0x1UL << ADC_CSR_EOC_MST_Pos)       /*!< 0x00000004 */

+#define ADC_CSR_EOC_MST                   ADC_CSR_EOC_MST_Msk                  /*!< End of regular conversion of the master ADC */

+#define ADC_CSR_EOS_MST_Pos               (3U)

+#define ADC_CSR_EOS_MST_Msk               (0x1UL << ADC_CSR_EOS_MST_Pos)       /*!< 0x00000008 */

+#define ADC_CSR_EOS_MST                   ADC_CSR_EOS_MST_Msk                  /*!< End of regular sequence flag of the master ADC */

+#define ADC_CSR_OVR_MST_Pos               (4U)

+#define ADC_CSR_OVR_MST_Msk               (0x1UL << ADC_CSR_OVR_MST_Pos)       /*!< 0x00000010 */

+#define ADC_CSR_OVR_MST                   ADC_CSR_OVR_MST_Msk                  /*!< Overrun flag of the master ADC */

+#define ADC_CSR_JEOC_MST_Pos              (5U)

+#define ADC_CSR_JEOC_MST_Msk              (0x1UL << ADC_CSR_JEOC_MST_Pos)      /*!< 0x00000020 */

+#define ADC_CSR_JEOC_MST                  ADC_CSR_JEOC_MST_Msk                 /*!< End of injected conversion of the master ADC */

+#define ADC_CSR_JEOS_MST_Pos              (6U)

+#define ADC_CSR_JEOS_MST_Msk              (0x1UL << ADC_CSR_JEOS_MST_Pos)      /*!< 0x00000040 */

+#define ADC_CSR_JEOS_MST                  ADC_CSR_JEOS_MST_Msk                 /*!< End of injected sequence flag of the master ADC */

+#define ADC_CSR_AWD1_MST_Pos              (7U)

+#define ADC_CSR_AWD1_MST_Msk              (0x1UL << ADC_CSR_AWD1_MST_Pos)      /*!< 0x00000080 */

+#define ADC_CSR_AWD1_MST                  ADC_CSR_AWD1_MST_Msk                 /*!< Analog watchdog 1 flag of the master ADC */

+#define ADC_CSR_AWD2_MST_Pos              (8U)

+#define ADC_CSR_AWD2_MST_Msk              (0x1UL << ADC_CSR_AWD2_MST_Pos)      /*!< 0x00000100 */

+#define ADC_CSR_AWD2_MST                  ADC_CSR_AWD2_MST_Msk                 /*!< Analog watchdog 2 flag of the master ADC */

+#define ADC_CSR_AWD3_MST_Pos              (9U)

+#define ADC_CSR_AWD3_MST_Msk              (0x1UL << ADC_CSR_AWD3_MST_Pos)      /*!< 0x00000200 */

+#define ADC_CSR_AWD3_MST                  ADC_CSR_AWD3_MST_Msk                 /*!< Analog watchdog 3 flag of the master ADC */

+#define ADC_CSR_JQOVF_MST_Pos             (10U)

+#define ADC_CSR_JQOVF_MST_Msk             (0x1UL << ADC_CSR_JQOVF_MST_Pos)     /*!< 0x00000400 */

+#define ADC_CSR_JQOVF_MST                 ADC_CSR_JQOVF_MST_Msk                /*!< Injected context queue overflow flag of the master ADC */

+#define ADC_CSR_ADRDY_SLV_Pos             (16U)

+#define ADC_CSR_ADRDY_SLV_Msk             (0x1UL << ADC_CSR_ADRDY_SLV_Pos)     /*!< 0x00010000 */

+#define ADC_CSR_ADRDY_SLV                 ADC_CSR_ADRDY_SLV_Msk                /*!< Slave ADC ready */

+#define ADC_CSR_EOSMP_SLV_Pos             (17U)

+#define ADC_CSR_EOSMP_SLV_Msk             (0x1UL << ADC_CSR_EOSMP_SLV_Pos)     /*!< 0x00020000 */

+#define ADC_CSR_EOSMP_SLV                 ADC_CSR_EOSMP_SLV_Msk                /*!< End of sampling phase flag of the slave ADC */

+#define ADC_CSR_EOC_SLV_Pos               (18U)

+#define ADC_CSR_EOC_SLV_Msk               (0x1UL << ADC_CSR_EOC_SLV_Pos)       /*!< 0x00040000 */

+#define ADC_CSR_EOC_SLV                   ADC_CSR_EOC_SLV_Msk                  /*!< End of regular conversion of the slave ADC */

+#define ADC_CSR_EOS_SLV_Pos               (19U)

+#define ADC_CSR_EOS_SLV_Msk               (0x1UL << ADC_CSR_EOS_SLV_Pos)       /*!< 0x00080000 */

+#define ADC_CSR_EOS_SLV                   ADC_CSR_EOS_SLV_Msk                  /*!< End of regular sequence flag of the slave ADC */

+#define ADC_CSR_OVR_SLV_Pos               (20U)

+#define ADC_CSR_OVR_SLV_Msk               (0x1UL << ADC_CSR_OVR_SLV_Pos)       /*!< 0x00100000 */

+#define ADC_CSR_OVR_SLV                   ADC_CSR_OVR_SLV_Msk                  /*!< Overrun flag of the slave ADC */

+#define ADC_CSR_JEOC_SLV_Pos              (21U)

+#define ADC_CSR_JEOC_SLV_Msk              (0x1UL << ADC_CSR_JEOC_SLV_Pos)      /*!< 0x00200000 */

+#define ADC_CSR_JEOC_SLV                  ADC_CSR_JEOC_SLV_Msk                 /*!< End of injected conversion of the slave ADC */

+#define ADC_CSR_JEOS_SLV_Pos              (22U)

+#define ADC_CSR_JEOS_SLV_Msk              (0x1UL << ADC_CSR_JEOS_SLV_Pos)      /*!< 0x00400000 */

+#define ADC_CSR_JEOS_SLV                  ADC_CSR_JEOS_SLV_Msk                 /*!< End of injected sequence flag of the slave ADC */

+#define ADC_CSR_AWD1_SLV_Pos              (23U)

+#define ADC_CSR_AWD1_SLV_Msk              (0x1UL << ADC_CSR_AWD1_SLV_Pos)      /*!< 0x00800000 */

+#define ADC_CSR_AWD1_SLV                  ADC_CSR_AWD1_SLV_Msk                 /*!< Analog watchdog 1 flag of the slave ADC */

+#define ADC_CSR_AWD2_SLV_Pos              (24U)

+#define ADC_CSR_AWD2_SLV_Msk              (0x1UL << ADC_CSR_AWD2_SLV_Pos)      /*!< 0x01000000 */

+#define ADC_CSR_AWD2_SLV                  ADC_CSR_AWD2_SLV_Msk                 /*!< Analog watchdog 2 flag of the slave ADC */

+#define ADC_CSR_AWD3_SLV_Pos              (25U)

+#define ADC_CSR_AWD3_SLV_Msk              (0x1UL << ADC_CSR_AWD3_SLV_Pos)      /*!< 0x02000000 */

+#define ADC_CSR_AWD3_SLV                  ADC_CSR_AWD3_SLV_Msk                 /*!< Analog watchdog 3 flag of the slave ADC */

+#define ADC_CSR_JQOVF_SLV_Pos             (26U)

+#define ADC_CSR_JQOVF_SLV_Msk             (0x1UL << ADC_CSR_JQOVF_SLV_Pos)     /*!< 0x04000000 */

+#define ADC_CSR_JQOVF_SLV                 ADC_CSR_JQOVF_SLV_Msk                /*!< Injected context queue overflow flag of the slave ADC */

+

+/********************  Bit definition for ADC_CCR register  ********************/

+#define ADC_CCR_DUAL_Pos                  (0U)

+#define ADC_CCR_DUAL_Msk                  (0x1FUL << ADC_CCR_DUAL_Pos)          /*!< 0x0000001F */

+#define ADC_CCR_DUAL                      ADC_CCR_DUAL_Msk                      /*!< Dual ADC mode selection */

+#define ADC_CCR_DUAL_0                    (0x01UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000001 */

+#define ADC_CCR_DUAL_1                    (0x02UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000002 */

+#define ADC_CCR_DUAL_2                    (0x04UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000004 */

+#define ADC_CCR_DUAL_3                    (0x08UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000008 */

+#define ADC_CCR_DUAL_4                    (0x10UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000010 */

+

+#define ADC_CCR_DELAY_Pos                 (8U)

+#define ADC_CCR_DELAY_Msk                 (0xFUL << ADC_CCR_DELAY_Pos)          /*!< 0x00000F00 */

+#define ADC_CCR_DELAY                     ADC_CCR_DELAY_Msk                     /*!< Delay between 2 sampling phases */

+#define ADC_CCR_DELAY_0                   (0x1UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000100 */

+#define ADC_CCR_DELAY_1                   (0x2UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000200 */

+#define ADC_CCR_DELAY_2                   (0x4UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000400 */

+#define ADC_CCR_DELAY_3                   (0x8UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000800 */

+

+

+#define ADC_CCR_DAMDF_Pos                 (14U)

+#define ADC_CCR_DAMDF_Msk                 (0x3UL << ADC_CCR_DAMDF_Pos)          /*!< 0x0000C000 */

+#define ADC_CCR_DAMDF                     ADC_CCR_DAMDF_Msk                     /*!< Dual ADC mode Data format */

+#define ADC_CCR_DAMDF_0                   (0x1UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00004000 */

+#define ADC_CCR_DAMDF_1                   (0x2UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00008000 */

+

+#define ADC_CCR_CKMODE_Pos                (16U)

+#define ADC_CCR_CKMODE_Msk                (0x3UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00030000 */

+#define ADC_CCR_CKMODE                    ADC_CCR_CKMODE_Msk                    /*!< ADC clock mode */

+#define ADC_CCR_CKMODE_0                  (0x1UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00010000 */

+#define ADC_CCR_CKMODE_1                  (0x2UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00020000 */

+

+#define ADC_CCR_PRESC_Pos                 (18U)

+#define ADC_CCR_PRESC_Msk                 (0xFUL << ADC_CCR_PRESC_Pos)          /*!< 0x003C0000 */

+#define ADC_CCR_PRESC                     ADC_CCR_PRESC_Msk                     /*!< ADC prescaler */

+#define ADC_CCR_PRESC_0                   (0x1UL << ADC_CCR_PRESC_Pos)          /*!< 0x00040000 */

+#define ADC_CCR_PRESC_1                   (0x2UL << ADC_CCR_PRESC_Pos)          /*!< 0x00080000 */

+#define ADC_CCR_PRESC_2                   (0x4UL << ADC_CCR_PRESC_Pos)          /*!< 0x00100000 */

+#define ADC_CCR_PRESC_3                   (0x8UL << ADC_CCR_PRESC_Pos)          /*!< 0x00200000 */

+

+#define ADC_CCR_VREFEN_Pos                (22U)

+#define ADC_CCR_VREFEN_Msk                (0x1UL << ADC_CCR_VREFEN_Pos)         /*!< 0x00400000 */

+#define ADC_CCR_VREFEN                    ADC_CCR_VREFEN_Msk                    /*!< VREFINT enable */

+#define ADC_CCR_TSEN_Pos                  (23U)

+#define ADC_CCR_TSEN_Msk                  (0x1UL << ADC_CCR_TSEN_Pos)           /*!< 0x00800000 */

+#define ADC_CCR_TSEN                      ADC_CCR_TSEN_Msk                      /*!< Temperature sensor enable */

+#define ADC_CCR_VBATEN_Pos                (24U)

+#define ADC_CCR_VBATEN_Msk                (0x1UL << ADC_CCR_VBATEN_Pos)         /*!< 0x01000000 */

+#define ADC_CCR_VBATEN                    ADC_CCR_VBATEN_Msk                    /*!< VBAT enable */

+

+/********************  Bit definition for ADC_CDR register  *******************/

+#define ADC_CDR_RDATA_MST_Pos             (0U)

+#define ADC_CDR_RDATA_MST_Msk             (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)   /*!< 0x0000FFFF */

+#define ADC_CDR_RDATA_MST                 ADC_CDR_RDATA_MST_Msk                 /*!< ADC multimode master group regular conversion data */

+

+#define ADC_CDR_RDATA_SLV_Pos             (16U)

+#define ADC_CDR_RDATA_SLV_Msk             (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)   /*!< 0xFFFF0000 */

+#define ADC_CDR_RDATA_SLV                 ADC_CDR_RDATA_SLV_Msk                 /*!< ADC multimode slave group regular conversion data */

+

+/********************  Bit definition for ADC_CDR2 register  ******************/

+#define ADC_CDR2_RDATA_ALT_Pos            (0U)

+#define ADC_CDR2_RDATA_ALT_Msk            (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */

+#define ADC_CDR2_RDATA_ALT                ADC_CDR2_RDATA_ALT_Msk                   /*!< Regular data of the master/slave alternated ADCs */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                   VREFBUF                                  */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for VREFBUF_CSR register  ****************/

+#define VREFBUF_CSR_ENVR_Pos        (0U)

+#define VREFBUF_CSR_ENVR_Msk        (0x1UL << VREFBUF_CSR_ENVR_Pos)            /*!< 0x00000001 */

+#define VREFBUF_CSR_ENVR            VREFBUF_CSR_ENVR_Msk                       /*!<Voltage reference buffer enable */

+#define VREFBUF_CSR_HIZ_Pos         (1U)

+#define VREFBUF_CSR_HIZ_Msk         (0x1UL << VREFBUF_CSR_HIZ_Pos)             /*!< 0x00000002 */

+#define VREFBUF_CSR_HIZ             VREFBUF_CSR_HIZ_Msk                        /*!<High impedance mode             */

+#define VREFBUF_CSR_VRR_Pos         (3U)

+#define VREFBUF_CSR_VRR_Msk         (0x1UL << VREFBUF_CSR_VRR_Pos)             /*!< 0x00000008 */

+#define VREFBUF_CSR_VRR             VREFBUF_CSR_VRR_Msk                        /*!<Voltage reference buffer ready  */

+#define VREFBUF_CSR_VRS_Pos         (4U)

+#define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */

+#define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */

+

+#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */

+#define VREFBUF_CSR_VRS_OUT2_Pos    (4U)

+#define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */

+#define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */

+#define VREFBUF_CSR_VRS_OUT3_Pos    (5U)

+#define VREFBUF_CSR_VRS_OUT3_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)        /*!< 0x00000020 */

+#define VREFBUF_CSR_VRS_OUT3        VREFBUF_CSR_VRS_OUT3_Msk                   /*!<Voltage reference VREF_OUT3     */

+#define VREFBUF_CSR_VRS_OUT4_Pos    (4U)

+#define VREFBUF_CSR_VRS_OUT4_Msk    (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)        /*!< 0x00000030 */

+#define VREFBUF_CSR_VRS_OUT4        VREFBUF_CSR_VRS_OUT4_Msk                   /*!<Voltage reference VREF_OUT4     */

+

+/*******************  Bit definition for VREFBUF_CCR register  ****************/

+#define VREFBUF_CCR_TRIM_Pos        (0U)

+#define VREFBUF_CCR_TRIM_Msk        (0x3FUL << VREFBUF_CCR_TRIM_Pos)           /*!< 0x0000003F */

+#define VREFBUF_CCR_TRIM            VREFBUF_CCR_TRIM_Msk                       /*!<TRIM[5:0] bits (Trimming code)  */

+

+/******************************************************************************/

+/*                                                                            */

+/*                 Flexible Datarate Controller Area Network                  */

+/*                                                                            */

+/******************************************************************************/

+/*!<FDCAN control and status registers */

+/*****************  Bit definition for FDCAN_CREL register  *******************/

+#define FDCAN_CREL_DAY_Pos        (0U)

+#define FDCAN_CREL_DAY_Msk        (0xFFUL << FDCAN_CREL_DAY_Pos)               /*!< 0x000000FF */

+#define FDCAN_CREL_DAY            FDCAN_CREL_DAY_Msk                           /*!<Timestamp Day                           */

+#define FDCAN_CREL_MON_Pos        (8U)

+#define FDCAN_CREL_MON_Msk        (0xFFUL << FDCAN_CREL_MON_Pos)               /*!< 0x0000FF00 */

+#define FDCAN_CREL_MON            FDCAN_CREL_MON_Msk                           /*!<Timestamp Month                         */

+#define FDCAN_CREL_YEAR_Pos       (16U)

+#define FDCAN_CREL_YEAR_Msk       (0xFUL << FDCAN_CREL_YEAR_Pos)               /*!< 0x000F0000 */

+#define FDCAN_CREL_YEAR           FDCAN_CREL_YEAR_Msk                          /*!<Timestamp Year                          */

+#define FDCAN_CREL_SUBSTEP_Pos    (20U)

+#define FDCAN_CREL_SUBSTEP_Msk    (0xFUL << FDCAN_CREL_SUBSTEP_Pos)            /*!< 0x00F00000 */

+#define FDCAN_CREL_SUBSTEP        FDCAN_CREL_SUBSTEP_Msk                       /*!<Sub-step of Core release                */

+#define FDCAN_CREL_STEP_Pos       (24U)

+#define FDCAN_CREL_STEP_Msk       (0xFUL << FDCAN_CREL_STEP_Pos)               /*!< 0x0F000000 */

+#define FDCAN_CREL_STEP           FDCAN_CREL_STEP_Msk                          /*!<Step of Core release                    */

+#define FDCAN_CREL_REL_Pos        (28U)

+#define FDCAN_CREL_REL_Msk        (0xFUL << FDCAN_CREL_REL_Pos)                /*!< 0xF0000000 */

+#define FDCAN_CREL_REL            FDCAN_CREL_REL_Msk                           /*!<Core release                            */

+

+/*****************  Bit definition for FDCAN_ENDN register  *******************/

+#define FDCAN_ENDN_ETV_Pos        (0U)

+#define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endiannes Test Value                    */

+

+/*****************  Bit definition for FDCAN_DBTP register  *******************/

+#define FDCAN_DBTP_DSJW_Pos       (0U)

+#define FDCAN_DBTP_DSJW_Msk       (0xFUL << FDCAN_DBTP_DSJW_Pos)               /*!< 0x0000000F */

+#define FDCAN_DBTP_DSJW           FDCAN_DBTP_DSJW_Msk                          /*!<Synchronization Jump Width              */

+#define FDCAN_DBTP_DTSEG2_Pos     (4U)

+#define FDCAN_DBTP_DTSEG2_Msk     (0xFUL << FDCAN_DBTP_DTSEG2_Pos)             /*!< 0x000000F0 */

+#define FDCAN_DBTP_DTSEG2         FDCAN_DBTP_DTSEG2_Msk                        /*!<Data time segment after sample point    */

+#define FDCAN_DBTP_DTSEG1_Pos     (8U)

+#define FDCAN_DBTP_DTSEG1_Msk     (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)            /*!< 0x00001F00 */

+#define FDCAN_DBTP_DTSEG1         FDCAN_DBTP_DTSEG1_Msk                        /*!<Data time segment before sample point   */

+#define FDCAN_DBTP_DBRP_Pos       (16U)

+#define FDCAN_DBTP_DBRP_Msk       (0x1FUL << FDCAN_DBTP_DBRP_Pos)              /*!< 0x001F0000 */

+#define FDCAN_DBTP_DBRP           FDCAN_DBTP_DBRP_Msk                          /*!<Data BIt Rate Prescaler                 */

+#define FDCAN_DBTP_TDC_Pos        (23U)

+#define FDCAN_DBTP_TDC_Msk        (0x1UL << FDCAN_DBTP_TDC_Pos)                /*!< 0x00800000 */

+#define FDCAN_DBTP_TDC            FDCAN_DBTP_TDC_Msk                           /*!<Transceiver Delay Compensation          */

+

+/*****************  Bit definition for FDCAN_TEST register  *******************/

+#define FDCAN_TEST_LBCK_Pos       (4U)

+#define FDCAN_TEST_LBCK_Msk       (0x1UL << FDCAN_TEST_LBCK_Pos)               /*!< 0x00000010 */

+#define FDCAN_TEST_LBCK           FDCAN_TEST_LBCK_Msk                          /*!<Loop Back mode                           */

+#define FDCAN_TEST_TX_Pos         (5U)

+#define FDCAN_TEST_TX_Msk         (0x3UL << FDCAN_TEST_TX_Pos)                 /*!< 0x00000060 */

+#define FDCAN_TEST_TX             FDCAN_TEST_TX_Msk                            /*!<Control of Transmit Pin                  */

+#define FDCAN_TEST_RX_Pos         (7U)

+#define FDCAN_TEST_RX_Msk         (0x1UL << FDCAN_TEST_RX_Pos)                 /*!< 0x00000080 */

+#define FDCAN_TEST_RX             FDCAN_TEST_RX_Msk                            /*!<Receive Pin                              */

+

+/*****************  Bit definition for FDCAN_RWD register  ********************/

+#define FDCAN_RWD_WDC_Pos         (0U)

+#define FDCAN_RWD_WDC_Msk         (0xFFUL << FDCAN_RWD_WDC_Pos)                /*!< 0x000000FF */

+#define FDCAN_RWD_WDC             FDCAN_RWD_WDC_Msk                            /*!<Watchdog configuration                   */

+#define FDCAN_RWD_WDV_Pos         (8U)

+#define FDCAN_RWD_WDV_Msk         (0xFFUL << FDCAN_RWD_WDV_Pos)                /*!< 0x0000FF00 */

+#define FDCAN_RWD_WDV             FDCAN_RWD_WDV_Msk                            /*!<Watchdog value                           */

+

+/*****************  Bit definition for FDCAN_CCCR register  ********************/

+#define FDCAN_CCCR_INIT_Pos       (0U)

+#define FDCAN_CCCR_INIT_Msk       (0x1UL << FDCAN_CCCR_INIT_Pos)               /*!< 0x00000001 */

+#define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!<Initialization                           */

+#define FDCAN_CCCR_CCE_Pos        (1U)

+#define FDCAN_CCCR_CCE_Msk        (0x1UL << FDCAN_CCCR_CCE_Pos)                /*!< 0x00000002 */

+#define FDCAN_CCCR_CCE            FDCAN_CCCR_CCE_Msk                           /*!<Configuration Change Enable              */

+#define FDCAN_CCCR_ASM_Pos        (2U)

+#define FDCAN_CCCR_ASM_Msk        (0x1UL << FDCAN_CCCR_ASM_Pos)                /*!< 0x00000004 */

+#define FDCAN_CCCR_ASM            FDCAN_CCCR_ASM_Msk                           /*!<ASM Restricted Operation Mode            */

+#define FDCAN_CCCR_CSA_Pos        (3U)

+#define FDCAN_CCCR_CSA_Msk        (0x1UL << FDCAN_CCCR_CSA_Pos)                /*!< 0x00000008 */

+#define FDCAN_CCCR_CSA            FDCAN_CCCR_CSA_Msk                           /*!<Clock Stop Acknowledge                   */

+#define FDCAN_CCCR_CSR_Pos        (4U)

+#define FDCAN_CCCR_CSR_Msk        (0x1UL << FDCAN_CCCR_CSR_Pos)                /*!< 0x00000010 */

+#define FDCAN_CCCR_CSR            FDCAN_CCCR_CSR_Msk                           /*!<Clock Stop Request                       */

+#define FDCAN_CCCR_MON_Pos        (5U)

+#define FDCAN_CCCR_MON_Msk        (0x1UL << FDCAN_CCCR_MON_Pos)                /*!< 0x00000020 */

+#define FDCAN_CCCR_MON            FDCAN_CCCR_MON_Msk                           /*!<Bus Monitoring Mode                      */

+#define FDCAN_CCCR_DAR_Pos        (6U)

+#define FDCAN_CCCR_DAR_Msk        (0x1UL << FDCAN_CCCR_DAR_Pos)                /*!< 0x00000040 */

+#define FDCAN_CCCR_DAR            FDCAN_CCCR_DAR_Msk                           /*!<Disable Automatic Retransmission         */

+#define FDCAN_CCCR_TEST_Pos       (7U)

+#define FDCAN_CCCR_TEST_Msk       (0x1UL << FDCAN_CCCR_TEST_Pos)               /*!< 0x00000080 */

+#define FDCAN_CCCR_TEST           FDCAN_CCCR_TEST_Msk                          /*!<Test Mode Enable                         */

+#define FDCAN_CCCR_FDOE_Pos       (8U)

+#define FDCAN_CCCR_FDOE_Msk       (0x1UL << FDCAN_CCCR_FDOE_Pos)               /*!< 0x00000100 */

+#define FDCAN_CCCR_FDOE           FDCAN_CCCR_FDOE_Msk                          /*!<FD Operation Enable                      */

+#define FDCAN_CCCR_BRSE_Pos       (9U)

+#define FDCAN_CCCR_BRSE_Msk       (0x1UL << FDCAN_CCCR_BRSE_Pos)               /*!< 0x00000200 */

+#define FDCAN_CCCR_BRSE           FDCAN_CCCR_BRSE_Msk                          /*!<FDCAN Bit Rate Switching                 */

+#define FDCAN_CCCR_PXHD_Pos       (12U)

+#define FDCAN_CCCR_PXHD_Msk       (0x1UL << FDCAN_CCCR_PXHD_Pos)               /*!< 0x00001000 */

+#define FDCAN_CCCR_PXHD           FDCAN_CCCR_PXHD_Msk                          /*!<Protocol Exception Handling Disable      */

+#define FDCAN_CCCR_EFBI_Pos       (13U)

+#define FDCAN_CCCR_EFBI_Msk       (0x1UL << FDCAN_CCCR_EFBI_Pos)               /*!< 0x00002000 */

+#define FDCAN_CCCR_EFBI           FDCAN_CCCR_EFBI_Msk                          /*!<Edge Filtering during Bus Integration    */

+#define FDCAN_CCCR_TXP_Pos        (14U)

+#define FDCAN_CCCR_TXP_Msk        (0x1UL << FDCAN_CCCR_TXP_Pos)                /*!< 0x00004000 */

+#define FDCAN_CCCR_TXP            FDCAN_CCCR_TXP_Msk                           /*!<Two CAN bit times Pause                  */

+#define FDCAN_CCCR_NISO_Pos       (15U)

+#define FDCAN_CCCR_NISO_Msk       (0x1UL << FDCAN_CCCR_NISO_Pos)               /*!< 0x00008000 */

+#define FDCAN_CCCR_NISO           FDCAN_CCCR_NISO_Msk                          /*!<Non ISO Operation                        */

+

+/*****************  Bit definition for FDCAN_NBTP register  ********************/

+#define FDCAN_NBTP_NTSEG2_Pos     (0U)

+#define FDCAN_NBTP_NTSEG2_Msk     (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)            /*!< 0x0000007F */

+#define FDCAN_NBTP_NTSEG2         FDCAN_NBTP_NTSEG2_Msk                        /*!<Nominal Time segment after sample point  */

+#define FDCAN_NBTP_NTSEG1_Pos     (8U)

+#define FDCAN_NBTP_NTSEG1_Msk     (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)            /*!< 0x0000FF00 */

+#define FDCAN_NBTP_NTSEG1         FDCAN_NBTP_NTSEG1_Msk                        /*!<Nominal Time segment before sample point */

+#define FDCAN_NBTP_NBRP_Pos       (16U)

+#define FDCAN_NBTP_NBRP_Msk       (0x1FFUL << FDCAN_NBTP_NBRP_Pos)             /*!< 0x01FF0000 */

+#define FDCAN_NBTP_NBRP           FDCAN_NBTP_NBRP_Msk                          /*!<Bit Rate Prescaler                       */

+#define FDCAN_NBTP_NSJW_Pos       (25U)

+#define FDCAN_NBTP_NSJW_Msk       (0x7FUL << FDCAN_NBTP_NSJW_Pos)              /*!< 0xFE000000 */

+#define FDCAN_NBTP_NSJW           FDCAN_NBTP_NSJW_Msk                          /*!<Nominal (Re)Synchronization Jump Width   */

+

+/*****************  Bit definition for FDCAN_TSCC register  ********************/

+#define FDCAN_TSCC_TSS_Pos        (0U)

+#define FDCAN_TSCC_TSS_Msk        (0x3UL << FDCAN_TSCC_TSS_Pos)                /*!< 0x00000003 */

+#define FDCAN_TSCC_TSS            FDCAN_TSCC_TSS_Msk                           /*!<Timestamp Select                         */

+#define FDCAN_TSCC_TCP_Pos        (16U)

+#define FDCAN_TSCC_TCP_Msk        (0xFUL << FDCAN_TSCC_TCP_Pos)                /*!< 0x000F0000 */

+#define FDCAN_TSCC_TCP            FDCAN_TSCC_TCP_Msk                           /*!<Timestamp Counter Prescaler              */

+

+/*****************  Bit definition for FDCAN_TSCV register  ********************/

+#define FDCAN_TSCV_TSC_Pos        (0U)

+#define FDCAN_TSCV_TSC_Msk        (0xFFFFUL << FDCAN_TSCV_TSC_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TSCV_TSC            FDCAN_TSCV_TSC_Msk                           /*!<Timestamp Counter                        */

+

+/*****************  Bit definition for FDCAN_TOCC register  ********************/

+#define FDCAN_TOCC_ETOC_Pos       (0U)

+#define FDCAN_TOCC_ETOC_Msk       (0x1UL << FDCAN_TOCC_ETOC_Pos)               /*!< 0x00000001 */

+#define FDCAN_TOCC_ETOC           FDCAN_TOCC_ETOC_Msk                          /*!<Enable Timeout Counter                   */

+#define FDCAN_TOCC_TOS_Pos        (1U)

+#define FDCAN_TOCC_TOS_Msk        (0x3UL << FDCAN_TOCC_TOS_Pos)                /*!< 0x00000006 */

+#define FDCAN_TOCC_TOS            FDCAN_TOCC_TOS_Msk                           /*!<Timeout Select                           */

+#define FDCAN_TOCC_TOP_Pos        (16U)

+#define FDCAN_TOCC_TOP_Msk        (0xFFFFUL << FDCAN_TOCC_TOP_Pos)             /*!< 0xFFFF0000 */

+#define FDCAN_TOCC_TOP            FDCAN_TOCC_TOP_Msk                           /*!<Timeout Period                           */

+

+/*****************  Bit definition for FDCAN_TOCV register  ********************/

+#define FDCAN_TOCV_TOC_Pos        (0U)

+#define FDCAN_TOCV_TOC_Msk        (0xFFFFUL << FDCAN_TOCV_TOC_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TOCV_TOC            FDCAN_TOCV_TOC_Msk                           /*!<Timeout Counter                          */

+

+/*****************  Bit definition for FDCAN_ECR register  *********************/

+#define FDCAN_ECR_TEC_Pos         (0U)

+#define FDCAN_ECR_TEC_Msk         (0xFUL << FDCAN_ECR_TEC_Pos)                 /*!< 0x0000000F */

+#define FDCAN_ECR_TEC             FDCAN_ECR_TEC_Msk                            /*!<Transmit Error Counter                   */

+#define FDCAN_ECR_REC_Pos         (8U)

+#define FDCAN_ECR_REC_Msk         (0x7FUL << FDCAN_ECR_REC_Pos)                /*!< 0x00007F00 */

+#define FDCAN_ECR_REC             FDCAN_ECR_REC_Msk                            /*!<Receive Error Counter                    */

+#define FDCAN_ECR_RP_Pos          (15U)

+#define FDCAN_ECR_RP_Msk          (0x1UL << FDCAN_ECR_RP_Pos)                  /*!< 0x00008000 */

+#define FDCAN_ECR_RP              FDCAN_ECR_RP_Msk                             /*!<Receive Error Passive                    */

+#define FDCAN_ECR_CEL_Pos         (16U)

+#define FDCAN_ECR_CEL_Msk         (0xFFUL << FDCAN_ECR_CEL_Pos)                /*!< 0x00FF0000 */

+#define FDCAN_ECR_CEL             FDCAN_ECR_CEL_Msk                            /*!<CAN Error Logging                        */

+

+/*****************  Bit definition for FDCAN_PSR register  *********************/

+#define FDCAN_PSR_LEC_Pos         (0U)

+#define FDCAN_PSR_LEC_Msk         (0x7UL << FDCAN_PSR_LEC_Pos)                 /*!< 0x00000007 */

+#define FDCAN_PSR_LEC             FDCAN_PSR_LEC_Msk                            /*!<Last Error Code                          */

+#define FDCAN_PSR_ACT_Pos         (3U)

+#define FDCAN_PSR_ACT_Msk         (0x3UL << FDCAN_PSR_ACT_Pos)                 /*!< 0x00000018 */

+#define FDCAN_PSR_ACT             FDCAN_PSR_ACT_Msk                            /*!<Activity                                 */

+#define FDCAN_PSR_EP_Pos          (5U)

+#define FDCAN_PSR_EP_Msk          (0x1UL << FDCAN_PSR_EP_Pos)                  /*!< 0x00000020 */

+#define FDCAN_PSR_EP              FDCAN_PSR_EP_Msk                             /*!<Error Passive                            */

+#define FDCAN_PSR_EW_Pos          (6U)

+#define FDCAN_PSR_EW_Msk          (0x1UL << FDCAN_PSR_EW_Pos)                  /*!< 0x00000040 */

+#define FDCAN_PSR_EW              FDCAN_PSR_EW_Msk                             /*!<Warning Status                           */

+#define FDCAN_PSR_BO_Pos          (7U)

+#define FDCAN_PSR_BO_Msk          (0x1UL << FDCAN_PSR_BO_Pos)                  /*!< 0x00000080 */

+#define FDCAN_PSR_BO              FDCAN_PSR_BO_Msk                             /*!<Bus_Off Status                           */

+#define FDCAN_PSR_DLEC_Pos        (8U)

+#define FDCAN_PSR_DLEC_Msk        (0x7UL << FDCAN_PSR_DLEC_Pos)                /*!< 0x00000700 */

+#define FDCAN_PSR_DLEC            FDCAN_PSR_DLEC_Msk                           /*!<Data Last Error Code                     */

+#define FDCAN_PSR_RESI_Pos        (11U)

+#define FDCAN_PSR_RESI_Msk        (0x1UL << FDCAN_PSR_RESI_Pos)                /*!< 0x00000800 */

+#define FDCAN_PSR_RESI            FDCAN_PSR_RESI_Msk                           /*!<ESI flag of last received FDCAN Message  */

+#define FDCAN_PSR_RBRS_Pos        (12U)

+#define FDCAN_PSR_RBRS_Msk        (0x1UL << FDCAN_PSR_RBRS_Pos)                /*!< 0x00001000 */

+#define FDCAN_PSR_RBRS            FDCAN_PSR_RBRS_Msk                           /*!<BRS flag of last received FDCAN Message  */

+#define FDCAN_PSR_REDL_Pos        (13U)

+#define FDCAN_PSR_REDL_Msk        (0x1UL << FDCAN_PSR_REDL_Pos)                /*!< 0x00002000 */

+#define FDCAN_PSR_REDL            FDCAN_PSR_REDL_Msk                           /*!<Received FDCAN Message                   */

+#define FDCAN_PSR_PXE_Pos         (14U)

+#define FDCAN_PSR_PXE_Msk         (0x1UL << FDCAN_PSR_PXE_Pos)                 /*!< 0x00004000 */

+#define FDCAN_PSR_PXE             FDCAN_PSR_PXE_Msk                            /*!<Protocol Exception Event                 */

+#define FDCAN_PSR_TDCV_Pos        (16U)

+#define FDCAN_PSR_TDCV_Msk        (0x7FUL << FDCAN_PSR_TDCV_Pos)               /*!< 0x007F0000 */

+#define FDCAN_PSR_TDCV            FDCAN_PSR_TDCV_Msk                           /*!<Transmitter Delay Compensation Value     */

+

+/*****************  Bit definition for FDCAN_TDCR register  ********************/

+#define FDCAN_TDCR_TDCF_Pos       (0U)

+#define FDCAN_TDCR_TDCF_Msk       (0x7FUL << FDCAN_TDCR_TDCF_Pos)              /*!< 0x0000007F */

+#define FDCAN_TDCR_TDCF           FDCAN_TDCR_TDCF_Msk                          /*!<Transmitter Delay Compensation Filter    */

+#define FDCAN_TDCR_TDCO_Pos       (8U)

+#define FDCAN_TDCR_TDCO_Msk       (0x7FUL << FDCAN_TDCR_TDCO_Pos)              /*!< 0x00007F00 */

+#define FDCAN_TDCR_TDCO           FDCAN_TDCR_TDCO_Msk                          /*!<Transmitter Delay Compensation Offset    */

+

+/*****************  Bit definition for FDCAN_IR register  **********************/

+#define FDCAN_IR_RF0N_Pos         (0U)

+#define FDCAN_IR_RF0N_Msk         (0x1UL << FDCAN_IR_RF0N_Pos)                 /*!< 0x00000001 */

+#define FDCAN_IR_RF0N             FDCAN_IR_RF0N_Msk                            /*!<Rx FIFO 0 New Message                    */

+#define FDCAN_IR_RF0W_Pos         (1U)

+#define FDCAN_IR_RF0W_Msk         (0x1UL << FDCAN_IR_RF0W_Pos)                 /*!< 0x00000002 */

+#define FDCAN_IR_RF0W             FDCAN_IR_RF0W_Msk                            /*!<Rx FIFO 0 Watermark Reached              */

+#define FDCAN_IR_RF0F_Pos         (2U)

+#define FDCAN_IR_RF0F_Msk         (0x1UL << FDCAN_IR_RF0F_Pos)                 /*!< 0x00000004 */

+#define FDCAN_IR_RF0F             FDCAN_IR_RF0F_Msk                            /*!<Rx FIFO 0 Full                           */

+#define FDCAN_IR_RF0L_Pos         (3U)

+#define FDCAN_IR_RF0L_Msk         (0x1UL << FDCAN_IR_RF0L_Pos)                 /*!< 0x00000008 */

+#define FDCAN_IR_RF0L             FDCAN_IR_RF0L_Msk                            /*!<Rx FIFO 0 Message Lost                   */

+#define FDCAN_IR_RF1N_Pos         (4U)

+#define FDCAN_IR_RF1N_Msk         (0x1UL << FDCAN_IR_RF1N_Pos)                 /*!< 0x00000010 */

+#define FDCAN_IR_RF1N             FDCAN_IR_RF1N_Msk                            /*!<Rx FIFO 1 New Message                    */

+#define FDCAN_IR_RF1W_Pos         (5U)

+#define FDCAN_IR_RF1W_Msk         (0x1UL << FDCAN_IR_RF1W_Pos)                 /*!< 0x00000020 */

+#define FDCAN_IR_RF1W             FDCAN_IR_RF1W_Msk                            /*!<Rx FIFO 1 Watermark Reached              */

+#define FDCAN_IR_RF1F_Pos         (6U)

+#define FDCAN_IR_RF1F_Msk         (0x1UL << FDCAN_IR_RF1F_Pos)                 /*!< 0x00000040 */

+#define FDCAN_IR_RF1F             FDCAN_IR_RF1F_Msk                            /*!<Rx FIFO 1 Full                           */

+#define FDCAN_IR_RF1L_Pos         (7U)

+#define FDCAN_IR_RF1L_Msk         (0x1UL << FDCAN_IR_RF1L_Pos)                 /*!< 0x00000080 */

+#define FDCAN_IR_RF1L             FDCAN_IR_RF1L_Msk                            /*!<Rx FIFO 1 Message Lost                   */

+#define FDCAN_IR_HPM_Pos          (8U)

+#define FDCAN_IR_HPM_Msk          (0x1UL << FDCAN_IR_HPM_Pos)                  /*!< 0x00000100 */

+#define FDCAN_IR_HPM              FDCAN_IR_HPM_Msk                             /*!<High Priority Message                    */

+#define FDCAN_IR_TC_Pos           (9U)

+#define FDCAN_IR_TC_Msk           (0x1UL << FDCAN_IR_TC_Pos)                   /*!< 0x00000200 */

+#define FDCAN_IR_TC               FDCAN_IR_TC_Msk                              /*!<Transmission Completed                   */

+#define FDCAN_IR_TCF_Pos          (10U)

+#define FDCAN_IR_TCF_Msk          (0x1UL << FDCAN_IR_TCF_Pos)                  /*!< 0x00000400 */

+#define FDCAN_IR_TCF              FDCAN_IR_TCF_Msk                             /*!<Transmission Cancellation Finished       */

+#define FDCAN_IR_TFE_Pos          (11U)

+#define FDCAN_IR_TFE_Msk          (0x1UL << FDCAN_IR_TFE_Pos)                  /*!< 0x00000800 */

+#define FDCAN_IR_TFE              FDCAN_IR_TFE_Msk                             /*!<Tx FIFO Empty                            */

+#define FDCAN_IR_TEFN_Pos         (12U)

+#define FDCAN_IR_TEFN_Msk         (0x1UL << FDCAN_IR_TEFN_Pos)                 /*!< 0x00001000 */

+#define FDCAN_IR_TEFN             FDCAN_IR_TEFN_Msk                            /*!<Tx Event FIFO New Entry                  */

+#define FDCAN_IR_TEFW_Pos         (13U)

+#define FDCAN_IR_TEFW_Msk         (0x1UL << FDCAN_IR_TEFW_Pos)                 /*!< 0x00002000 */

+#define FDCAN_IR_TEFW             FDCAN_IR_TEFW_Msk                            /*!<Tx Event FIFO Watermark Reached          */

+#define FDCAN_IR_TEFF_Pos         (14U)

+#define FDCAN_IR_TEFF_Msk         (0x1UL << FDCAN_IR_TEFF_Pos)                 /*!< 0x00004000 */

+#define FDCAN_IR_TEFF             FDCAN_IR_TEFF_Msk                            /*!<Tx Event FIFO Full                       */

+#define FDCAN_IR_TEFL_Pos         (15U)

+#define FDCAN_IR_TEFL_Msk         (0x1UL << FDCAN_IR_TEFL_Pos)                 /*!< 0x00008000 */

+#define FDCAN_IR_TEFL             FDCAN_IR_TEFL_Msk                            /*!<Tx Event FIFO Element Lost               */

+#define FDCAN_IR_TSW_Pos          (16U)

+#define FDCAN_IR_TSW_Msk          (0x1UL << FDCAN_IR_TSW_Pos)                  /*!< 0x00010000 */

+#define FDCAN_IR_TSW              FDCAN_IR_TSW_Msk                             /*!<Timestamp Wraparound                     */

+#define FDCAN_IR_MRAF_Pos         (17U)

+#define FDCAN_IR_MRAF_Msk         (0x1UL << FDCAN_IR_MRAF_Pos)                 /*!< 0x00020000 */

+#define FDCAN_IR_MRAF             FDCAN_IR_MRAF_Msk                            /*!<Message RAM Access Failure               */

+#define FDCAN_IR_TOO_Pos          (18U)

+#define FDCAN_IR_TOO_Msk          (0x1UL << FDCAN_IR_TOO_Pos)                  /*!< 0x00040000 */

+#define FDCAN_IR_TOO              FDCAN_IR_TOO_Msk                             /*!<Timeout Occurred                         */

+#define FDCAN_IR_DRX_Pos          (19U)

+#define FDCAN_IR_DRX_Msk          (0x1UL << FDCAN_IR_DRX_Pos)                  /*!< 0x00080000 */

+#define FDCAN_IR_DRX              FDCAN_IR_DRX_Msk                             /*!<Message stored to Dedicated Rx Buffer    */

+#define FDCAN_IR_ELO_Pos          (22U)

+#define FDCAN_IR_ELO_Msk          (0x1UL << FDCAN_IR_ELO_Pos)                  /*!< 0x00400000 */

+#define FDCAN_IR_ELO              FDCAN_IR_ELO_Msk                             /*!<Error Logging Overflow                   */

+#define FDCAN_IR_EP_Pos           (23U)

+#define FDCAN_IR_EP_Msk           (0x1UL << FDCAN_IR_EP_Pos)                   /*!< 0x00800000 */

+#define FDCAN_IR_EP               FDCAN_IR_EP_Msk                              /*!<Error Passive                            */

+#define FDCAN_IR_EW_Pos           (24U)

+#define FDCAN_IR_EW_Msk           (0x1UL << FDCAN_IR_EW_Pos)                   /*!< 0x01000000 */

+#define FDCAN_IR_EW               FDCAN_IR_EW_Msk                              /*!<Warning Status                           */

+#define FDCAN_IR_BO_Pos           (25U)

+#define FDCAN_IR_BO_Msk           (0x1UL << FDCAN_IR_BO_Pos)                   /*!< 0x02000000 */

+#define FDCAN_IR_BO               FDCAN_IR_BO_Msk                              /*!<Bus_Off Status                           */

+#define FDCAN_IR_WDI_Pos          (26U)

+#define FDCAN_IR_WDI_Msk          (0x1UL << FDCAN_IR_WDI_Pos)                  /*!< 0x04000000 */

+#define FDCAN_IR_WDI              FDCAN_IR_WDI_Msk                             /*!<Watchdog Interrupt                       */

+#define FDCAN_IR_PEA_Pos          (27U)

+#define FDCAN_IR_PEA_Msk          (0x1UL << FDCAN_IR_PEA_Pos)                  /*!< 0x08000000 */

+#define FDCAN_IR_PEA              FDCAN_IR_PEA_Msk                             /*!<Protocol Error in Arbitration Phase      */

+#define FDCAN_IR_PED_Pos          (28U)

+#define FDCAN_IR_PED_Msk          (0x1UL << FDCAN_IR_PED_Pos)                  /*!< 0x10000000 */

+#define FDCAN_IR_PED              FDCAN_IR_PED_Msk                             /*!<Protocol Error in Data Phase             */

+#define FDCAN_IR_ARA_Pos          (29U)

+#define FDCAN_IR_ARA_Msk          (0x1UL << FDCAN_IR_ARA_Pos)                  /*!< 0x20000000 */

+#define FDCAN_IR_ARA              FDCAN_IR_ARA_Msk                             /*!<Access to Reserved Address               */

+

+/*****************  Bit definition for FDCAN_IE register  **********************/

+#define FDCAN_IE_RF0NE_Pos        (0U)

+#define FDCAN_IE_RF0NE_Msk        (0x1UL << FDCAN_IE_RF0NE_Pos)                /*!< 0x00000001 */

+#define FDCAN_IE_RF0NE            FDCAN_IE_RF0NE_Msk                           /*!<Rx FIFO 0 New Message Enable                 */

+#define FDCAN_IE_RF0WE_Pos        (1U)

+#define FDCAN_IE_RF0WE_Msk        (0x1UL << FDCAN_IE_RF0WE_Pos)                /*!< 0x00000002 */

+#define FDCAN_IE_RF0WE            FDCAN_IE_RF0WE_Msk                           /*!<Rx FIFO 0 Watermark Reached Enable           */

+#define FDCAN_IE_RF0FE_Pos        (2U)

+#define FDCAN_IE_RF0FE_Msk        (0x1UL << FDCAN_IE_RF0FE_Pos)                /*!< 0x00000004 */

+#define FDCAN_IE_RF0FE            FDCAN_IE_RF0FE_Msk                           /*!<Rx FIFO 0 Full Enable                        */

+#define FDCAN_IE_RF0LE_Pos        (3U)

+#define FDCAN_IE_RF0LE_Msk        (0x1UL << FDCAN_IE_RF0LE_Pos)                /*!< 0x00000008 */

+#define FDCAN_IE_RF0LE            FDCAN_IE_RF0LE_Msk                           /*!<Rx FIFO 0 Message Lost Enable                */

+#define FDCAN_IE_RF1NE_Pos        (4U)

+#define FDCAN_IE_RF1NE_Msk        (0x1UL << FDCAN_IE_RF1NE_Pos)                /*!< 0x00000010 */

+#define FDCAN_IE_RF1NE            FDCAN_IE_RF1NE_Msk                           /*!<Rx FIFO 1 New Message Enable                 */

+#define FDCAN_IE_RF1WE_Pos        (5U)

+#define FDCAN_IE_RF1WE_Msk        (0x1UL << FDCAN_IE_RF1WE_Pos)                /*!< 0x00000020 */

+#define FDCAN_IE_RF1WE            FDCAN_IE_RF1WE_Msk                           /*!<Rx FIFO 1 Watermark Reached Enable           */

+#define FDCAN_IE_RF1FE_Pos        (6U)

+#define FDCAN_IE_RF1FE_Msk        (0x1UL << FDCAN_IE_RF1FE_Pos)                /*!< 0x00000040 */

+#define FDCAN_IE_RF1FE            FDCAN_IE_RF1FE_Msk                           /*!<Rx FIFO 1 Full Enable                        */

+#define FDCAN_IE_RF1LE_Pos        (7U)

+#define FDCAN_IE_RF1LE_Msk        (0x1UL << FDCAN_IE_RF1LE_Pos)                /*!< 0x00000080 */

+#define FDCAN_IE_RF1LE            FDCAN_IE_RF1LE_Msk                           /*!<Rx FIFO 1 Message Lost Enable                */

+#define FDCAN_IE_HPME_Pos         (8U)

+#define FDCAN_IE_HPME_Msk         (0x1UL << FDCAN_IE_HPME_Pos)                 /*!< 0x00000100 */

+#define FDCAN_IE_HPME             FDCAN_IE_HPME_Msk                            /*!<High Priority Message Enable                 */

+#define FDCAN_IE_TCE_Pos          (9U)

+#define FDCAN_IE_TCE_Msk          (0x1UL << FDCAN_IE_TCE_Pos)                  /*!< 0x00000200 */

+#define FDCAN_IE_TCE              FDCAN_IE_TCE_Msk                             /*!<Transmission Completed Enable                */

+#define FDCAN_IE_TCFE_Pos         (10U)

+#define FDCAN_IE_TCFE_Msk         (0x1UL << FDCAN_IE_TCFE_Pos)                 /*!< 0x00000400 */

+#define FDCAN_IE_TCFE             FDCAN_IE_TCFE_Msk                            /*!<Transmission Cancellation Finished Enable    */

+#define FDCAN_IE_TFEE_Pos         (11U)

+#define FDCAN_IE_TFEE_Msk         (0x1UL << FDCAN_IE_TFEE_Pos)                 /*!< 0x00000800 */

+#define FDCAN_IE_TFEE             FDCAN_IE_TFEE_Msk                            /*!<Tx FIFO Empty Enable                         */

+#define FDCAN_IE_TEFNE_Pos        (12U)

+#define FDCAN_IE_TEFNE_Msk        (0x1UL << FDCAN_IE_TEFNE_Pos)                /*!< 0x00001000 */

+#define FDCAN_IE_TEFNE            FDCAN_IE_TEFNE_Msk                           /*!<Tx Event FIFO New Entry Enable               */

+#define FDCAN_IE_TEFWE_Pos        (13U)

+#define FDCAN_IE_TEFWE_Msk        (0x1UL << FDCAN_IE_TEFWE_Pos)                /*!< 0x00002000 */

+#define FDCAN_IE_TEFWE            FDCAN_IE_TEFWE_Msk                           /*!<Tx Event FIFO Watermark Reached Enable       */

+#define FDCAN_IE_TEFFE_Pos        (14U)

+#define FDCAN_IE_TEFFE_Msk        (0x1UL << FDCAN_IE_TEFFE_Pos)                /*!< 0x00004000 */

+#define FDCAN_IE_TEFFE            FDCAN_IE_TEFFE_Msk                           /*!<Tx Event FIFO Full Enable                    */

+#define FDCAN_IE_TEFLE_Pos        (15U)

+#define FDCAN_IE_TEFLE_Msk        (0x1UL << FDCAN_IE_TEFLE_Pos)                /*!< 0x00008000 */

+#define FDCAN_IE_TEFLE            FDCAN_IE_TEFLE_Msk                           /*!<Tx Event FIFO Element Lost Enable            */

+#define FDCAN_IE_TSWE_Pos         (16U)

+#define FDCAN_IE_TSWE_Msk         (0x1UL << FDCAN_IE_TSWE_Pos)                 /*!< 0x00010000 */

+#define FDCAN_IE_TSWE             FDCAN_IE_TSWE_Msk                            /*!<Timestamp Wraparound Enable                  */

+#define FDCAN_IE_MRAFE_Pos        (17U)

+#define FDCAN_IE_MRAFE_Msk        (0x1UL << FDCAN_IE_MRAFE_Pos)                /*!< 0x00020000 */

+#define FDCAN_IE_MRAFE            FDCAN_IE_MRAFE_Msk                           /*!<Message RAM Access Failure Enable            */

+#define FDCAN_IE_TOOE_Pos         (18U)

+#define FDCAN_IE_TOOE_Msk         (0x1UL << FDCAN_IE_TOOE_Pos)                 /*!< 0x00040000 */

+#define FDCAN_IE_TOOE             FDCAN_IE_TOOE_Msk                            /*!<Timeout Occurred Enable                      */

+#define FDCAN_IE_DRXE_Pos         (19U)

+#define FDCAN_IE_DRXE_Msk         (0x1UL << FDCAN_IE_DRXE_Pos)                 /*!< 0x00080000 */

+#define FDCAN_IE_DRXE             FDCAN_IE_DRXE_Msk                            /*!<Message stored to Dedicated Rx Buffer Enable */

+#define FDCAN_IE_BECE_Pos         (20U)

+#define FDCAN_IE_BECE_Msk         (0x1UL << FDCAN_IE_BECE_Pos)                 /*!< 0x00100000 */

+#define FDCAN_IE_BECE             FDCAN_IE_BECE_Msk                            /*!<Bit Error Corrected Interrupt Enable         */

+#define FDCAN_IE_BEUE_Pos         (21U)

+#define FDCAN_IE_BEUE_Msk         (0x1UL << FDCAN_IE_BEUE_Pos)                 /*!< 0x00200000 */

+#define FDCAN_IE_BEUE             FDCAN_IE_BEUE_Msk                            /*!<Bit Error Uncorrected Interrupt Enable       */

+#define FDCAN_IE_ELOE_Pos         (22U)

+#define FDCAN_IE_ELOE_Msk         (0x1UL << FDCAN_IE_ELOE_Pos)                 /*!< 0x00400000 */

+#define FDCAN_IE_ELOE             FDCAN_IE_ELOE_Msk                            /*!<Error Logging Overflow Enable                */

+#define FDCAN_IE_EPE_Pos          (23U)

+#define FDCAN_IE_EPE_Msk          (0x1UL << FDCAN_IE_EPE_Pos)                  /*!< 0x00800000 */

+#define FDCAN_IE_EPE              FDCAN_IE_EPE_Msk                             /*!<Error Passive Enable                         */

+#define FDCAN_IE_EWE_Pos          (24U)

+#define FDCAN_IE_EWE_Msk          (0x1UL << FDCAN_IE_EWE_Pos)                  /*!< 0x01000000 */

+#define FDCAN_IE_EWE              FDCAN_IE_EWE_Msk                             /*!<Warning Status Enable                        */

+#define FDCAN_IE_BOE_Pos          (25U)

+#define FDCAN_IE_BOE_Msk          (0x1UL << FDCAN_IE_BOE_Pos)                  /*!< 0x02000000 */

+#define FDCAN_IE_BOE              FDCAN_IE_BOE_Msk                             /*!<Bus_Off Status Enable                        */

+#define FDCAN_IE_WDIE_Pos         (26U)

+#define FDCAN_IE_WDIE_Msk         (0x1UL << FDCAN_IE_WDIE_Pos)                 /*!< 0x04000000 */

+#define FDCAN_IE_WDIE             FDCAN_IE_WDIE_Msk                            /*!<Watchdog Interrupt Enable                    */

+#define FDCAN_IE_PEAE_Pos         (27U)

+#define FDCAN_IE_PEAE_Msk         (0x1UL << FDCAN_IE_PEAE_Pos)                 /*!< 0x08000000 */

+#define FDCAN_IE_PEAE             FDCAN_IE_PEAE_Msk                            /*!<Protocol Error in Arbitration Phase Enable   */

+#define FDCAN_IE_PEDE_Pos         (28U)

+#define FDCAN_IE_PEDE_Msk         (0x1UL << FDCAN_IE_PEDE_Pos)                 /*!< 0x10000000 */

+#define FDCAN_IE_PEDE             FDCAN_IE_PEDE_Msk                            /*!<Protocol Error in Data Phase Enable          */

+#define FDCAN_IE_ARAE_Pos         (29U)

+#define FDCAN_IE_ARAE_Msk         (0x1UL << FDCAN_IE_ARAE_Pos)                 /*!< 0x20000000 */

+#define FDCAN_IE_ARAE             FDCAN_IE_ARAE_Msk                            /*!<Access to Reserved Address Enable            */

+

+/*****************  Bit definition for FDCAN_ILS register  **********************/

+#define FDCAN_ILS_RF0NL_Pos       (0U)

+#define FDCAN_ILS_RF0NL_Msk       (0x1UL << FDCAN_ILS_RF0NL_Pos)               /*!< 0x00000001 */

+#define FDCAN_ILS_RF0NL           FDCAN_ILS_RF0NL_Msk                          /*!<Rx FIFO 0 New Message Line                  */

+#define FDCAN_ILS_RF0WL_Pos       (1U)

+#define FDCAN_ILS_RF0WL_Msk       (0x1UL << FDCAN_ILS_RF0WL_Pos)               /*!< 0x00000002 */

+#define FDCAN_ILS_RF0WL           FDCAN_ILS_RF0WL_Msk                          /*!<Rx FIFO 0 Watermark Reached Line            */

+#define FDCAN_ILS_RF0FL_Pos       (2U)

+#define FDCAN_ILS_RF0FL_Msk       (0x1UL << FDCAN_ILS_RF0FL_Pos)               /*!< 0x00000004 */

+#define FDCAN_ILS_RF0FL           FDCAN_ILS_RF0FL_Msk                          /*!<Rx FIFO 0 Full Line                         */

+#define FDCAN_ILS_RF0LL_Pos       (3U)

+#define FDCAN_ILS_RF0LL_Msk       (0x1UL << FDCAN_ILS_RF0LL_Pos)               /*!< 0x00000008 */

+#define FDCAN_ILS_RF0LL           FDCAN_ILS_RF0LL_Msk                          /*!<Rx FIFO 0 Message Lost Line                 */

+#define FDCAN_ILS_RF1NL_Pos       (4U)

+#define FDCAN_ILS_RF1NL_Msk       (0x1UL << FDCAN_ILS_RF1NL_Pos)               /*!< 0x00000010 */

+#define FDCAN_ILS_RF1NL           FDCAN_ILS_RF1NL_Msk                          /*!<Rx FIFO 1 New Message Line                  */

+#define FDCAN_ILS_RF1WL_Pos       (5U)

+#define FDCAN_ILS_RF1WL_Msk       (0x1UL << FDCAN_ILS_RF1WL_Pos)               /*!< 0x00000020 */

+#define FDCAN_ILS_RF1WL           FDCAN_ILS_RF1WL_Msk                          /*!<Rx FIFO 1 Watermark Reached Line            */

+#define FDCAN_ILS_RF1FL_Pos       (6U)

+#define FDCAN_ILS_RF1FL_Msk       (0x1UL << FDCAN_ILS_RF1FL_Pos)               /*!< 0x00000040 */

+#define FDCAN_ILS_RF1FL           FDCAN_ILS_RF1FL_Msk                          /*!<Rx FIFO 1 Full Line                         */

+#define FDCAN_ILS_RF1LL_Pos       (7U)

+#define FDCAN_ILS_RF1LL_Msk       (0x1UL << FDCAN_ILS_RF1LL_Pos)               /*!< 0x00000080 */

+#define FDCAN_ILS_RF1LL           FDCAN_ILS_RF1LL_Msk                          /*!<Rx FIFO 1 Message Lost Line                 */

+#define FDCAN_ILS_HPML_Pos        (8U)

+#define FDCAN_ILS_HPML_Msk        (0x1UL << FDCAN_ILS_HPML_Pos)                /*!< 0x00000100 */

+#define FDCAN_ILS_HPML            FDCAN_ILS_HPML_Msk                           /*!<High Priority Message Line                  */

+#define FDCAN_ILS_TCL_Pos         (9U)

+#define FDCAN_ILS_TCL_Msk         (0x1UL << FDCAN_ILS_TCL_Pos)                 /*!< 0x00000200 */

+#define FDCAN_ILS_TCL             FDCAN_ILS_TCL_Msk                            /*!<Transmission Completed Line                 */

+#define FDCAN_ILS_TCFL_Pos        (10U)

+#define FDCAN_ILS_TCFL_Msk        (0x1UL << FDCAN_ILS_TCFL_Pos)                /*!< 0x00000400 */

+#define FDCAN_ILS_TCFL            FDCAN_ILS_TCFL_Msk                           /*!<Transmission Cancellation Finished Line     */

+#define FDCAN_ILS_TFEL_Pos        (11U)

+#define FDCAN_ILS_TFEL_Msk        (0x1UL << FDCAN_ILS_TFEL_Pos)                /*!< 0x00000800 */

+#define FDCAN_ILS_TFEL            FDCAN_ILS_TFEL_Msk                           /*!<Tx FIFO Empty Line                          */

+#define FDCAN_ILS_TEFNL_Pos       (12U)

+#define FDCAN_ILS_TEFNL_Msk       (0x1UL << FDCAN_ILS_TEFNL_Pos)               /*!< 0x00001000 */

+#define FDCAN_ILS_TEFNL           FDCAN_ILS_TEFNL_Msk                          /*!<Tx Event FIFO New Entry Line                */

+#define FDCAN_ILS_TEFWL_Pos       (13U)

+#define FDCAN_ILS_TEFWL_Msk       (0x1UL << FDCAN_ILS_TEFWL_Pos)               /*!< 0x00002000 */

+#define FDCAN_ILS_TEFWL           FDCAN_ILS_TEFWL_Msk                          /*!<Tx Event FIFO Watermark Reached Line        */

+#define FDCAN_ILS_TEFFL_Pos       (14U)

+#define FDCAN_ILS_TEFFL_Msk       (0x1UL << FDCAN_ILS_TEFFL_Pos)               /*!< 0x00004000 */

+#define FDCAN_ILS_TEFFL           FDCAN_ILS_TEFFL_Msk                          /*!<Tx Event FIFO Full Line                     */

+#define FDCAN_ILS_TEFLL_Pos       (15U)

+#define FDCAN_ILS_TEFLL_Msk       (0x1UL << FDCAN_ILS_TEFLL_Pos)               /*!< 0x00008000 */

+#define FDCAN_ILS_TEFLL           FDCAN_ILS_TEFLL_Msk                          /*!<Tx Event FIFO Element Lost Line             */

+#define FDCAN_ILS_TSWL_Pos        (16U)

+#define FDCAN_ILS_TSWL_Msk        (0x1UL << FDCAN_ILS_TSWL_Pos)                /*!< 0x00010000 */

+#define FDCAN_ILS_TSWL            FDCAN_ILS_TSWL_Msk                           /*!<Timestamp Wraparound Line                   */

+#define FDCAN_ILS_MRAFE_Pos       (17U)

+#define FDCAN_ILS_MRAFE_Msk       (0x1UL << FDCAN_ILS_MRAFE_Pos)               /*!< 0x00020000 */

+#define FDCAN_ILS_MRAFE           FDCAN_ILS_MRAFE_Msk                          /*!<Message RAM Access Failure Line             */

+#define FDCAN_ILS_TOOE_Pos        (18U)

+#define FDCAN_ILS_TOOE_Msk        (0x1UL << FDCAN_ILS_TOOE_Pos)                /*!< 0x00040000 */

+#define FDCAN_ILS_TOOE            FDCAN_ILS_TOOE_Msk                           /*!<Timeout Occurred Line                       */

+#define FDCAN_ILS_DRXE_Pos        (19U)

+#define FDCAN_ILS_DRXE_Msk        (0x1UL << FDCAN_ILS_DRXE_Pos)                /*!< 0x00080000 */

+#define FDCAN_ILS_DRXE            FDCAN_ILS_DRXE_Msk                           /*!<Message stored to Dedicated Rx Buffer Line  */

+#define FDCAN_ILS_BECE_Pos        (20U)

+#define FDCAN_ILS_BECE_Msk        (0x1UL << FDCAN_ILS_BECE_Pos)                /*!< 0x00100000 */

+#define FDCAN_ILS_BECE            FDCAN_ILS_BECE_Msk                           /*!<Bit Error Corrected Interrupt Line          */

+#define FDCAN_ILS_BEUE_Pos        (21U)

+#define FDCAN_ILS_BEUE_Msk        (0x1UL << FDCAN_ILS_BEUE_Pos)                /*!< 0x00200000 */

+#define FDCAN_ILS_BEUE            FDCAN_ILS_BEUE_Msk                           /*!<Bit Error Uncorrected Interrupt Line        */

+#define FDCAN_ILS_ELOE_Pos        (22U)

+#define FDCAN_ILS_ELOE_Msk        (0x1UL << FDCAN_ILS_ELOE_Pos)                /*!< 0x00400000 */

+#define FDCAN_ILS_ELOE            FDCAN_ILS_ELOE_Msk                           /*!<Error Logging Overflow Line                 */

+#define FDCAN_ILS_EPE_Pos         (23U)

+#define FDCAN_ILS_EPE_Msk         (0x1UL << FDCAN_ILS_EPE_Pos)                 /*!< 0x00800000 */

+#define FDCAN_ILS_EPE             FDCAN_ILS_EPE_Msk                            /*!<Error Passive Line                          */

+#define FDCAN_ILS_EWE_Pos         (24U)

+#define FDCAN_ILS_EWE_Msk         (0x1UL << FDCAN_ILS_EWE_Pos)                 /*!< 0x01000000 */

+#define FDCAN_ILS_EWE             FDCAN_ILS_EWE_Msk                            /*!<Warning Status Line                         */

+#define FDCAN_ILS_BOE_Pos         (25U)

+#define FDCAN_ILS_BOE_Msk         (0x1UL << FDCAN_ILS_BOE_Pos)                 /*!< 0x02000000 */

+#define FDCAN_ILS_BOE             FDCAN_ILS_BOE_Msk                            /*!<Bus_Off Status Line                         */

+#define FDCAN_ILS_WDIE_Pos        (26U)

+#define FDCAN_ILS_WDIE_Msk        (0x1UL << FDCAN_ILS_WDIE_Pos)                /*!< 0x04000000 */

+#define FDCAN_ILS_WDIE            FDCAN_ILS_WDIE_Msk                           /*!<Watchdog Interrupt Line                     */

+#define FDCAN_ILS_PEAE_Pos        (27U)

+#define FDCAN_ILS_PEAE_Msk        (0x1UL << FDCAN_ILS_PEAE_Pos)                /*!< 0x08000000 */

+#define FDCAN_ILS_PEAE            FDCAN_ILS_PEAE_Msk                           /*!<Protocol Error in Arbitration Phase Line    */

+#define FDCAN_ILS_PEDE_Pos        (28U)

+#define FDCAN_ILS_PEDE_Msk        (0x1UL << FDCAN_ILS_PEDE_Pos)                /*!< 0x10000000 */

+#define FDCAN_ILS_PEDE            FDCAN_ILS_PEDE_Msk                           /*!<Protocol Error in Data Phase Line           */

+#define FDCAN_ILS_ARAE_Pos        (29U)

+#define FDCAN_ILS_ARAE_Msk        (0x1UL << FDCAN_ILS_ARAE_Pos)                /*!< 0x20000000 */

+#define FDCAN_ILS_ARAE            FDCAN_ILS_ARAE_Msk                           /*!<Access to Reserved Address Line             */

+

+/*****************  Bit definition for FDCAN_ILE register  **********************/

+#define FDCAN_ILE_EINT0_Pos       (0U)

+#define FDCAN_ILE_EINT0_Msk       (0x1UL << FDCAN_ILE_EINT0_Pos)               /*!< 0x00000001 */

+#define FDCAN_ILE_EINT0           FDCAN_ILE_EINT0_Msk                          /*!<Enable Interrupt Line 0                   */

+#define FDCAN_ILE_EINT1_Pos       (1U)

+#define FDCAN_ILE_EINT1_Msk       (0x1UL << FDCAN_ILE_EINT1_Pos)               /*!< 0x00000002 */

+#define FDCAN_ILE_EINT1           FDCAN_ILE_EINT1_Msk                          /*!<Enable Interrupt Line 1                   */

+

+/*****************  Bit definition for FDCAN_GFC register  **********************/

+#define FDCAN_GFC_RRFE_Pos        (0U)

+#define FDCAN_GFC_RRFE_Msk        (0x1UL << FDCAN_GFC_RRFE_Pos)                /*!< 0x00000001 */

+#define FDCAN_GFC_RRFE            FDCAN_GFC_RRFE_Msk                           /*!<Reject Remote Frames Extended             */

+#define FDCAN_GFC_RRFS_Pos        (1U)

+#define FDCAN_GFC_RRFS_Msk        (0x1UL << FDCAN_GFC_RRFS_Pos)                /*!< 0x00000002 */

+#define FDCAN_GFC_RRFS            FDCAN_GFC_RRFS_Msk                           /*!<Reject Remote Frames Standard             */

+#define FDCAN_GFC_ANFE_Pos        (2U)

+#define FDCAN_GFC_ANFE_Msk        (0x3UL << FDCAN_GFC_ANFE_Pos)                /*!< 0x0000000C */

+#define FDCAN_GFC_ANFE            FDCAN_GFC_ANFE_Msk                           /*!<Accept Non-matching Frames Extended       */

+#define FDCAN_GFC_ANFS_Pos        (4U)

+#define FDCAN_GFC_ANFS_Msk        (0x3UL << FDCAN_GFC_ANFS_Pos)                /*!< 0x00000030 */

+#define FDCAN_GFC_ANFS            FDCAN_GFC_ANFS_Msk                           /*!<Accept Non-matching Frames Standard       */

+

+/*****************  Bit definition for FDCAN_SIDFC register  ********************/

+#define FDCAN_SIDFC_FLSSA_Pos     (2U)

+#define FDCAN_SIDFC_FLSSA_Msk     (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)          /*!< 0x0000FFFC */

+#define FDCAN_SIDFC_FLSSA         FDCAN_SIDFC_FLSSA_Msk                        /*!<Filter List Standard Start Address        */

+#define FDCAN_SIDFC_LSS_Pos       (16U)

+#define FDCAN_SIDFC_LSS_Msk       (0xFFUL << FDCAN_SIDFC_LSS_Pos)              /*!< 0x00FF0000 */

+#define FDCAN_SIDFC_LSS           FDCAN_SIDFC_LSS_Msk                          /*!<List Size Standard                        */

+

+/*****************  Bit definition for FDCAN_XIDFC register  ********************/

+#define FDCAN_XIDFC_FLESA_Pos     (2U)

+#define FDCAN_XIDFC_FLESA_Msk     (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)          /*!< 0x0000FFFC */

+#define FDCAN_XIDFC_FLESA         FDCAN_XIDFC_FLESA_Msk                        /*!<Filter List Standard Start Address        */

+#define FDCAN_XIDFC_LSE_Pos       (16U)

+#define FDCAN_XIDFC_LSE_Msk       (0x7FUL << FDCAN_XIDFC_LSE_Pos)              /*!< 0x007F0000 */

+#define FDCAN_XIDFC_LSE           FDCAN_XIDFC_LSE_Msk                          /*!<List Size Extended                        */

+

+/*****************  Bit definition for FDCAN_XIDAM register  ********************/

+#define FDCAN_XIDAM_EIDM_Pos      (0U)

+#define FDCAN_XIDAM_EIDM_Msk      (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)       /*!< 0x1FFFFFFF */

+#define FDCAN_XIDAM_EIDM          FDCAN_XIDAM_EIDM_Msk                         /*!<Extended ID Mask                          */

+

+/*****************  Bit definition for FDCAN_HPMS register  *********************/

+#define FDCAN_HPMS_BIDX_Pos       (0U)

+#define FDCAN_HPMS_BIDX_Msk       (0x3FUL << FDCAN_HPMS_BIDX_Pos)              /*!< 0x0000003F */

+#define FDCAN_HPMS_BIDX           FDCAN_HPMS_BIDX_Msk                          /*!<Buffer Index                              */

+#define FDCAN_HPMS_MSI_Pos        (6U)

+#define FDCAN_HPMS_MSI_Msk        (0x3UL << FDCAN_HPMS_MSI_Pos)                /*!< 0x000000C0 */

+#define FDCAN_HPMS_MSI            FDCAN_HPMS_MSI_Msk                           /*!<Message Storage Indicator                 */

+#define FDCAN_HPMS_FIDX_Pos       (8U)

+#define FDCAN_HPMS_FIDX_Msk       (0x7FUL << FDCAN_HPMS_FIDX_Pos)              /*!< 0x00007F00 */

+#define FDCAN_HPMS_FIDX           FDCAN_HPMS_FIDX_Msk                          /*!<Filter Index                              */

+#define FDCAN_HPMS_FLST_Pos       (15U)

+#define FDCAN_HPMS_FLST_Msk       (0x1UL << FDCAN_HPMS_FLST_Pos)               /*!< 0x00008000 */

+#define FDCAN_HPMS_FLST           FDCAN_HPMS_FLST_Msk                          /*!<Filter List                               */

+

+/*****************  Bit definition for FDCAN_NDAT1 register  ********************/

+#define FDCAN_NDAT1_ND0_Pos       (0U)

+#define FDCAN_NDAT1_ND0_Msk       (0x1UL << FDCAN_NDAT1_ND0_Pos)               /*!< 0x00000001 */

+#define FDCAN_NDAT1_ND0           FDCAN_NDAT1_ND0_Msk                          /*!<New Data flag of Rx Buffer 0              */

+#define FDCAN_NDAT1_ND1_Pos       (1U)

+#define FDCAN_NDAT1_ND1_Msk       (0x1UL << FDCAN_NDAT1_ND1_Pos)               /*!< 0x00000002 */

+#define FDCAN_NDAT1_ND1           FDCAN_NDAT1_ND1_Msk                          /*!<New Data flag of Rx Buffer 1              */

+#define FDCAN_NDAT1_ND2_Pos       (2U)

+#define FDCAN_NDAT1_ND2_Msk       (0x1UL << FDCAN_NDAT1_ND2_Pos)               /*!< 0x00000004 */

+#define FDCAN_NDAT1_ND2           FDCAN_NDAT1_ND2_Msk                          /*!<New Data flag of Rx Buffer 2              */

+#define FDCAN_NDAT1_ND3_Pos       (3U)

+#define FDCAN_NDAT1_ND3_Msk       (0x1UL << FDCAN_NDAT1_ND3_Pos)               /*!< 0x00000008 */

+#define FDCAN_NDAT1_ND3           FDCAN_NDAT1_ND3_Msk                          /*!<New Data flag of Rx Buffer 3              */

+#define FDCAN_NDAT1_ND4_Pos       (4U)

+#define FDCAN_NDAT1_ND4_Msk       (0x1UL << FDCAN_NDAT1_ND4_Pos)               /*!< 0x00000010 */

+#define FDCAN_NDAT1_ND4           FDCAN_NDAT1_ND4_Msk                          /*!<New Data flag of Rx Buffer 4              */

+#define FDCAN_NDAT1_ND5_Pos       (5U)

+#define FDCAN_NDAT1_ND5_Msk       (0x1UL << FDCAN_NDAT1_ND5_Pos)               /*!< 0x00000020 */

+#define FDCAN_NDAT1_ND5           FDCAN_NDAT1_ND5_Msk                          /*!<New Data flag of Rx Buffer 5              */

+#define FDCAN_NDAT1_ND6_Pos       (6U)

+#define FDCAN_NDAT1_ND6_Msk       (0x1UL << FDCAN_NDAT1_ND6_Pos)               /*!< 0x00000040 */

+#define FDCAN_NDAT1_ND6           FDCAN_NDAT1_ND6_Msk                          /*!<New Data flag of Rx Buffer 6              */

+#define FDCAN_NDAT1_ND7_Pos       (7U)

+#define FDCAN_NDAT1_ND7_Msk       (0x1UL << FDCAN_NDAT1_ND7_Pos)               /*!< 0x00000080 */

+#define FDCAN_NDAT1_ND7           FDCAN_NDAT1_ND7_Msk                          /*!<New Data flag of Rx Buffer 7              */

+#define FDCAN_NDAT1_ND8_Pos       (8U)

+#define FDCAN_NDAT1_ND8_Msk       (0x1UL << FDCAN_NDAT1_ND8_Pos)               /*!< 0x00000100 */

+#define FDCAN_NDAT1_ND8           FDCAN_NDAT1_ND8_Msk                          /*!<New Data flag of Rx Buffer 8              */

+#define FDCAN_NDAT1_ND9_Pos       (9U)

+#define FDCAN_NDAT1_ND9_Msk       (0x1UL << FDCAN_NDAT1_ND9_Pos)               /*!< 0x00000200 */

+#define FDCAN_NDAT1_ND9           FDCAN_NDAT1_ND9_Msk                          /*!<New Data flag of Rx Buffer 9              */

+#define FDCAN_NDAT1_ND10_Pos      (10U)

+#define FDCAN_NDAT1_ND10_Msk      (0x1UL << FDCAN_NDAT1_ND10_Pos)              /*!< 0x00000400 */

+#define FDCAN_NDAT1_ND10          FDCAN_NDAT1_ND10_Msk                         /*!<New Data flag of Rx Buffer 10             */

+#define FDCAN_NDAT1_ND11_Pos      (11U)

+#define FDCAN_NDAT1_ND11_Msk      (0x1UL << FDCAN_NDAT1_ND11_Pos)              /*!< 0x00000800 */

+#define FDCAN_NDAT1_ND11          FDCAN_NDAT1_ND11_Msk                         /*!<New Data flag of Rx Buffer 11             */

+#define FDCAN_NDAT1_ND12_Pos      (12U)

+#define FDCAN_NDAT1_ND12_Msk      (0x1UL << FDCAN_NDAT1_ND12_Pos)              /*!< 0x00001000 */

+#define FDCAN_NDAT1_ND12          FDCAN_NDAT1_ND12_Msk                         /*!<New Data flag of Rx Buffer 12             */

+#define FDCAN_NDAT1_ND13_Pos      (13U)

+#define FDCAN_NDAT1_ND13_Msk      (0x1UL << FDCAN_NDAT1_ND13_Pos)              /*!< 0x00002000 */

+#define FDCAN_NDAT1_ND13          FDCAN_NDAT1_ND13_Msk                         /*!<New Data flag of Rx Buffer 13             */

+#define FDCAN_NDAT1_ND14_Pos      (14U)

+#define FDCAN_NDAT1_ND14_Msk      (0x1UL << FDCAN_NDAT1_ND14_Pos)              /*!< 0x00004000 */

+#define FDCAN_NDAT1_ND14          FDCAN_NDAT1_ND14_Msk                         /*!<New Data flag of Rx Buffer 14             */

+#define FDCAN_NDAT1_ND15_Pos      (15U)

+#define FDCAN_NDAT1_ND15_Msk      (0x1UL << FDCAN_NDAT1_ND15_Pos)              /*!< 0x00008000 */

+#define FDCAN_NDAT1_ND15          FDCAN_NDAT1_ND15_Msk                         /*!<New Data flag of Rx Buffer 15             */

+#define FDCAN_NDAT1_ND16_Pos      (16U)

+#define FDCAN_NDAT1_ND16_Msk      (0x1UL << FDCAN_NDAT1_ND16_Pos)              /*!< 0x00010000 */

+#define FDCAN_NDAT1_ND16          FDCAN_NDAT1_ND16_Msk                         /*!<New Data flag of Rx Buffer 16             */

+#define FDCAN_NDAT1_ND17_Pos      (17U)

+#define FDCAN_NDAT1_ND17_Msk      (0x1UL << FDCAN_NDAT1_ND17_Pos)              /*!< 0x00020000 */

+#define FDCAN_NDAT1_ND17          FDCAN_NDAT1_ND17_Msk                         /*!<New Data flag of Rx Buffer 17             */

+#define FDCAN_NDAT1_ND18_Pos      (18U)

+#define FDCAN_NDAT1_ND18_Msk      (0x1UL << FDCAN_NDAT1_ND18_Pos)              /*!< 0x00040000 */

+#define FDCAN_NDAT1_ND18          FDCAN_NDAT1_ND18_Msk                         /*!<New Data flag of Rx Buffer 18             */

+#define FDCAN_NDAT1_ND19_Pos      (19U)

+#define FDCAN_NDAT1_ND19_Msk      (0x1UL << FDCAN_NDAT1_ND19_Pos)              /*!< 0x00080000 */

+#define FDCAN_NDAT1_ND19          FDCAN_NDAT1_ND19_Msk                         /*!<New Data flag of Rx Buffer 19             */

+#define FDCAN_NDAT1_ND20_Pos      (20U)

+#define FDCAN_NDAT1_ND20_Msk      (0x1UL << FDCAN_NDAT1_ND20_Pos)              /*!< 0x00100000 */

+#define FDCAN_NDAT1_ND20          FDCAN_NDAT1_ND20_Msk                         /*!<New Data flag of Rx Buffer 20             */

+#define FDCAN_NDAT1_ND21_Pos      (21U)

+#define FDCAN_NDAT1_ND21_Msk      (0x1UL << FDCAN_NDAT1_ND21_Pos)              /*!< 0x00200000 */

+#define FDCAN_NDAT1_ND21          FDCAN_NDAT1_ND21_Msk                         /*!<New Data flag of Rx Buffer 21             */

+#define FDCAN_NDAT1_ND22_Pos      (22U)

+#define FDCAN_NDAT1_ND22_Msk      (0x1UL << FDCAN_NDAT1_ND22_Pos)              /*!< 0x00400000 */

+#define FDCAN_NDAT1_ND22          FDCAN_NDAT1_ND22_Msk                         /*!<New Data flag of Rx Buffer 22             */

+#define FDCAN_NDAT1_ND23_Pos      (23U)

+#define FDCAN_NDAT1_ND23_Msk      (0x1UL << FDCAN_NDAT1_ND23_Pos)              /*!< 0x00800000 */

+#define FDCAN_NDAT1_ND23          FDCAN_NDAT1_ND23_Msk                         /*!<New Data flag of Rx Buffer 23             */

+#define FDCAN_NDAT1_ND24_Pos      (24U)

+#define FDCAN_NDAT1_ND24_Msk      (0x1UL << FDCAN_NDAT1_ND24_Pos)              /*!< 0x01000000 */

+#define FDCAN_NDAT1_ND24          FDCAN_NDAT1_ND24_Msk                         /*!<New Data flag of Rx Buffer 24             */

+#define FDCAN_NDAT1_ND25_Pos      (25U)

+#define FDCAN_NDAT1_ND25_Msk      (0x1UL << FDCAN_NDAT1_ND25_Pos)              /*!< 0x02000000 */

+#define FDCAN_NDAT1_ND25          FDCAN_NDAT1_ND25_Msk                         /*!<New Data flag of Rx Buffer 25             */

+#define FDCAN_NDAT1_ND26_Pos      (26U)

+#define FDCAN_NDAT1_ND26_Msk      (0x1UL << FDCAN_NDAT1_ND26_Pos)              /*!< 0x04000000 */

+#define FDCAN_NDAT1_ND26          FDCAN_NDAT1_ND26_Msk                         /*!<New Data flag of Rx Buffer 26             */

+#define FDCAN_NDAT1_ND27_Pos      (27U)

+#define FDCAN_NDAT1_ND27_Msk      (0x1UL << FDCAN_NDAT1_ND27_Pos)              /*!< 0x08000000 */

+#define FDCAN_NDAT1_ND27          FDCAN_NDAT1_ND27_Msk                         /*!<New Data flag of Rx Buffer 27             */

+#define FDCAN_NDAT1_ND28_Pos      (28U)

+#define FDCAN_NDAT1_ND28_Msk      (0x1UL << FDCAN_NDAT1_ND28_Pos)              /*!< 0x10000000 */

+#define FDCAN_NDAT1_ND28          FDCAN_NDAT1_ND28_Msk                         /*!<New Data flag of Rx Buffer 28             */

+#define FDCAN_NDAT1_ND29_Pos      (29U)

+#define FDCAN_NDAT1_ND29_Msk      (0x1UL << FDCAN_NDAT1_ND29_Pos)              /*!< 0x20000000 */

+#define FDCAN_NDAT1_ND29          FDCAN_NDAT1_ND29_Msk                         /*!<New Data flag of Rx Buffer 29             */

+#define FDCAN_NDAT1_ND30_Pos      (30U)

+#define FDCAN_NDAT1_ND30_Msk      (0x1UL << FDCAN_NDAT1_ND30_Pos)              /*!< 0x40000000 */

+#define FDCAN_NDAT1_ND30          FDCAN_NDAT1_ND30_Msk                         /*!<New Data flag of Rx Buffer 30             */

+#define FDCAN_NDAT1_ND31_Pos      (31U)

+#define FDCAN_NDAT1_ND31_Msk      (0x1UL << FDCAN_NDAT1_ND31_Pos)              /*!< 0x80000000 */

+#define FDCAN_NDAT1_ND31          FDCAN_NDAT1_ND31_Msk                         /*!<New Data flag of Rx Buffer 31             */

+

+/*****************  Bit definition for FDCAN_NDAT2 register  ********************/

+#define FDCAN_NDAT2_ND32_Pos      (0U)

+#define FDCAN_NDAT2_ND32_Msk      (0x1UL << FDCAN_NDAT2_ND32_Pos)              /*!< 0x00000001 */

+#define FDCAN_NDAT2_ND32          FDCAN_NDAT2_ND32_Msk                         /*!<New Data flag of Rx Buffer 32             */

+#define FDCAN_NDAT2_ND33_Pos      (1U)

+#define FDCAN_NDAT2_ND33_Msk      (0x1UL << FDCAN_NDAT2_ND33_Pos)              /*!< 0x00000002 */

+#define FDCAN_NDAT2_ND33          FDCAN_NDAT2_ND33_Msk                         /*!<New Data flag of Rx Buffer 33             */

+#define FDCAN_NDAT2_ND34_Pos      (2U)

+#define FDCAN_NDAT2_ND34_Msk      (0x1UL << FDCAN_NDAT2_ND34_Pos)              /*!< 0x00000004 */

+#define FDCAN_NDAT2_ND34          FDCAN_NDAT2_ND34_Msk                         /*!<New Data flag of Rx Buffer 34             */

+#define FDCAN_NDAT2_ND35_Pos      (3U)

+#define FDCAN_NDAT2_ND35_Msk      (0x1UL << FDCAN_NDAT2_ND35_Pos)              /*!< 0x00000008 */

+#define FDCAN_NDAT2_ND35          FDCAN_NDAT2_ND35_Msk                         /*!<New Data flag of Rx Buffer 35             */

+#define FDCAN_NDAT2_ND36_Pos      (4U)

+#define FDCAN_NDAT2_ND36_Msk      (0x1UL << FDCAN_NDAT2_ND36_Pos)              /*!< 0x00000010 */

+#define FDCAN_NDAT2_ND36          FDCAN_NDAT2_ND36_Msk                         /*!<New Data flag of Rx Buffer 36             */

+#define FDCAN_NDAT2_ND37_Pos      (5U)

+#define FDCAN_NDAT2_ND37_Msk      (0x1UL << FDCAN_NDAT2_ND37_Pos)              /*!< 0x00000020 */

+#define FDCAN_NDAT2_ND37          FDCAN_NDAT2_ND37_Msk                         /*!<New Data flag of Rx Buffer 37             */

+#define FDCAN_NDAT2_ND38_Pos      (6U)

+#define FDCAN_NDAT2_ND38_Msk      (0x1UL << FDCAN_NDAT2_ND38_Pos)              /*!< 0x00000040 */

+#define FDCAN_NDAT2_ND38          FDCAN_NDAT2_ND38_Msk                         /*!<New Data flag of Rx Buffer 38             */

+#define FDCAN_NDAT2_ND39_Pos      (7U)

+#define FDCAN_NDAT2_ND39_Msk      (0x1UL << FDCAN_NDAT2_ND39_Pos)              /*!< 0x00000080 */

+#define FDCAN_NDAT2_ND39          FDCAN_NDAT2_ND39_Msk                         /*!<New Data flag of Rx Buffer 39             */

+#define FDCAN_NDAT2_ND40_Pos      (8U)

+#define FDCAN_NDAT2_ND40_Msk      (0x1UL << FDCAN_NDAT2_ND40_Pos)              /*!< 0x00000100 */

+#define FDCAN_NDAT2_ND40          FDCAN_NDAT2_ND40_Msk                         /*!<New Data flag of Rx Buffer 40             */

+#define FDCAN_NDAT2_ND41_Pos      (9U)

+#define FDCAN_NDAT2_ND41_Msk      (0x1UL << FDCAN_NDAT2_ND41_Pos)              /*!< 0x00000200 */

+#define FDCAN_NDAT2_ND41          FDCAN_NDAT2_ND41_Msk                         /*!<New Data flag of Rx Buffer 41             */

+#define FDCAN_NDAT2_ND42_Pos      (10U)

+#define FDCAN_NDAT2_ND42_Msk      (0x1UL << FDCAN_NDAT2_ND42_Pos)              /*!< 0x00000400 */

+#define FDCAN_NDAT2_ND42          FDCAN_NDAT2_ND42_Msk                         /*!<New Data flag of Rx Buffer 42             */

+#define FDCAN_NDAT2_ND43_Pos      (11U)

+#define FDCAN_NDAT2_ND43_Msk      (0x1UL << FDCAN_NDAT2_ND43_Pos)              /*!< 0x00000800 */

+#define FDCAN_NDAT2_ND43          FDCAN_NDAT2_ND43_Msk                         /*!<New Data flag of Rx Buffer 43             */

+#define FDCAN_NDAT2_ND44_Pos      (12U)

+#define FDCAN_NDAT2_ND44_Msk      (0x1UL << FDCAN_NDAT2_ND44_Pos)              /*!< 0x00001000 */

+#define FDCAN_NDAT2_ND44          FDCAN_NDAT2_ND44_Msk                         /*!<New Data flag of Rx Buffer 44             */

+#define FDCAN_NDAT2_ND45_Pos      (13U)

+#define FDCAN_NDAT2_ND45_Msk      (0x1UL << FDCAN_NDAT2_ND45_Pos)              /*!< 0x00002000 */

+#define FDCAN_NDAT2_ND45          FDCAN_NDAT2_ND45_Msk                         /*!<New Data flag of Rx Buffer 45             */

+#define FDCAN_NDAT2_ND46_Pos      (14U)

+#define FDCAN_NDAT2_ND46_Msk      (0x1UL << FDCAN_NDAT2_ND46_Pos)              /*!< 0x00004000 */

+#define FDCAN_NDAT2_ND46          FDCAN_NDAT2_ND46_Msk                         /*!<New Data flag of Rx Buffer 46             */

+#define FDCAN_NDAT2_ND47_Pos      (15U)

+#define FDCAN_NDAT2_ND47_Msk      (0x1UL << FDCAN_NDAT2_ND47_Pos)              /*!< 0x00008000 */

+#define FDCAN_NDAT2_ND47          FDCAN_NDAT2_ND47_Msk                         /*!<New Data flag of Rx Buffer 47             */

+#define FDCAN_NDAT2_ND48_Pos      (16U)

+#define FDCAN_NDAT2_ND48_Msk      (0x1UL << FDCAN_NDAT2_ND48_Pos)              /*!< 0x00010000 */

+#define FDCAN_NDAT2_ND48          FDCAN_NDAT2_ND48_Msk                         /*!<New Data flag of Rx Buffer 48             */

+#define FDCAN_NDAT2_ND49_Pos      (17U)

+#define FDCAN_NDAT2_ND49_Msk      (0x1UL << FDCAN_NDAT2_ND49_Pos)              /*!< 0x00020000 */

+#define FDCAN_NDAT2_ND49          FDCAN_NDAT2_ND49_Msk                         /*!<New Data flag of Rx Buffer 49             */

+#define FDCAN_NDAT2_ND50_Pos      (18U)

+#define FDCAN_NDAT2_ND50_Msk      (0x1UL << FDCAN_NDAT2_ND50_Pos)              /*!< 0x00040000 */

+#define FDCAN_NDAT2_ND50          FDCAN_NDAT2_ND50_Msk                         /*!<New Data flag of Rx Buffer 50             */

+#define FDCAN_NDAT2_ND51_Pos      (19U)

+#define FDCAN_NDAT2_ND51_Msk      (0x1UL << FDCAN_NDAT2_ND51_Pos)              /*!< 0x00080000 */

+#define FDCAN_NDAT2_ND51          FDCAN_NDAT2_ND51_Msk                         /*!<New Data flag of Rx Buffer 51             */

+#define FDCAN_NDAT2_ND52_Pos      (20U)

+#define FDCAN_NDAT2_ND52_Msk      (0x1UL << FDCAN_NDAT2_ND52_Pos)              /*!< 0x00100000 */

+#define FDCAN_NDAT2_ND52          FDCAN_NDAT2_ND52_Msk                         /*!<New Data flag of Rx Buffer 52             */

+#define FDCAN_NDAT2_ND53_Pos      (21U)

+#define FDCAN_NDAT2_ND53_Msk      (0x1UL << FDCAN_NDAT2_ND53_Pos)              /*!< 0x00200000 */

+#define FDCAN_NDAT2_ND53          FDCAN_NDAT2_ND53_Msk                         /*!<New Data flag of Rx Buffer 53             */

+#define FDCAN_NDAT2_ND54_Pos      (22U)

+#define FDCAN_NDAT2_ND54_Msk      (0x1UL << FDCAN_NDAT2_ND54_Pos)              /*!< 0x00400000 */

+#define FDCAN_NDAT2_ND54          FDCAN_NDAT2_ND54_Msk                         /*!<New Data flag of Rx Buffer 54             */

+#define FDCAN_NDAT2_ND55_Pos      (23U)

+#define FDCAN_NDAT2_ND55_Msk      (0x1UL << FDCAN_NDAT2_ND55_Pos)              /*!< 0x00800000 */

+#define FDCAN_NDAT2_ND55          FDCAN_NDAT2_ND55_Msk                         /*!<New Data flag of Rx Buffer 55             */

+#define FDCAN_NDAT2_ND56_Pos      (24U)

+#define FDCAN_NDAT2_ND56_Msk      (0x1UL << FDCAN_NDAT2_ND56_Pos)              /*!< 0x01000000 */

+#define FDCAN_NDAT2_ND56          FDCAN_NDAT2_ND56_Msk                         /*!<New Data flag of Rx Buffer 56             */

+#define FDCAN_NDAT2_ND57_Pos      (25U)

+#define FDCAN_NDAT2_ND57_Msk      (0x1UL << FDCAN_NDAT2_ND57_Pos)              /*!< 0x02000000 */

+#define FDCAN_NDAT2_ND57          FDCAN_NDAT2_ND57_Msk                         /*!<New Data flag of Rx Buffer 57             */

+#define FDCAN_NDAT2_ND58_Pos      (26U)

+#define FDCAN_NDAT2_ND58_Msk      (0x1UL << FDCAN_NDAT2_ND58_Pos)              /*!< 0x04000000 */

+#define FDCAN_NDAT2_ND58          FDCAN_NDAT2_ND58_Msk                         /*!<New Data flag of Rx Buffer 58             */

+#define FDCAN_NDAT2_ND59_Pos      (27U)

+#define FDCAN_NDAT2_ND59_Msk      (0x1UL << FDCAN_NDAT2_ND59_Pos)              /*!< 0x08000000 */

+#define FDCAN_NDAT2_ND59          FDCAN_NDAT2_ND59_Msk                         /*!<New Data flag of Rx Buffer 59             */

+#define FDCAN_NDAT2_ND60_Pos      (28U)

+#define FDCAN_NDAT2_ND60_Msk      (0x1UL << FDCAN_NDAT2_ND60_Pos)              /*!< 0x10000000 */

+#define FDCAN_NDAT2_ND60          FDCAN_NDAT2_ND60_Msk                         /*!<New Data flag of Rx Buffer 60             */

+#define FDCAN_NDAT2_ND61_Pos      (29U)

+#define FDCAN_NDAT2_ND61_Msk      (0x1UL << FDCAN_NDAT2_ND61_Pos)              /*!< 0x20000000 */

+#define FDCAN_NDAT2_ND61          FDCAN_NDAT2_ND61_Msk                         /*!<New Data flag of Rx Buffer 61             */

+#define FDCAN_NDAT2_ND62_Pos      (30U)

+#define FDCAN_NDAT2_ND62_Msk      (0x1UL << FDCAN_NDAT2_ND62_Pos)              /*!< 0x40000000 */

+#define FDCAN_NDAT2_ND62          FDCAN_NDAT2_ND62_Msk                         /*!<New Data flag of Rx Buffer 62             */

+#define FDCAN_NDAT2_ND63_Pos      (31U)

+#define FDCAN_NDAT2_ND63_Msk      (0x1UL << FDCAN_NDAT2_ND63_Pos)              /*!< 0x80000000 */

+#define FDCAN_NDAT2_ND63          FDCAN_NDAT2_ND63_Msk                         /*!<New Data flag of Rx Buffer 63             */

+

+/*****************  Bit definition for FDCAN_RXF0C register  ********************/

+#define FDCAN_RXF0C_F0SA_Pos      (2U)

+#define FDCAN_RXF0C_F0SA_Msk      (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_RXF0C_F0SA          FDCAN_RXF0C_F0SA_Msk                         /*!<Rx FIFO 0 Start Address                   */

+#define FDCAN_RXF0C_F0S_Pos       (16U)

+#define FDCAN_RXF0C_F0S_Msk       (0x7FUL << FDCAN_RXF0C_F0S_Pos)              /*!< 0x007F0000 */

+#define FDCAN_RXF0C_F0S           FDCAN_RXF0C_F0S_Msk                          /*!<Number of Rx FIFO 0 elements              */

+#define FDCAN_RXF0C_F0WM_Pos      (24U)

+#define FDCAN_RXF0C_F0WM_Msk      (0x7FUL << FDCAN_RXF0C_F0WM_Pos)             /*!< 0x7F000000 */

+#define FDCAN_RXF0C_F0WM          FDCAN_RXF0C_F0WM_Msk                         /*!<FIFO 0 Watermark                          */

+#define FDCAN_RXF0C_F0OM_Pos      (31U)

+#define FDCAN_RXF0C_F0OM_Msk      (0x1UL << FDCAN_RXF0C_F0OM_Pos)              /*!< 0x80000000 */

+#define FDCAN_RXF0C_F0OM          FDCAN_RXF0C_F0OM_Msk                         /*!<FIFO 0 Operation Mode                     */

+

+/*****************  Bit definition for FDCAN_RXF0S register  ********************/

+#define FDCAN_RXF0S_F0FL_Pos      (0U)

+#define FDCAN_RXF0S_F0FL_Msk      (0x7FUL << FDCAN_RXF0S_F0FL_Pos)             /*!< 0x0000007F */

+#define FDCAN_RXF0S_F0FL          FDCAN_RXF0S_F0FL_Msk                         /*!<Rx FIFO 0 Fill Level                      */

+#define FDCAN_RXF0S_F0GI_Pos      (8U)

+#define FDCAN_RXF0S_F0GI_Msk      (0x3FUL << FDCAN_RXF0S_F0GI_Pos)             /*!< 0x00003F00 */

+#define FDCAN_RXF0S_F0GI          FDCAN_RXF0S_F0GI_Msk                         /*!<Rx FIFO 0 Get Index                       */

+#define FDCAN_RXF0S_F0PI_Pos      (16U)

+#define FDCAN_RXF0S_F0PI_Msk      (0x3FUL << FDCAN_RXF0S_F0PI_Pos)             /*!< 0x003F0000 */

+#define FDCAN_RXF0S_F0PI          FDCAN_RXF0S_F0PI_Msk                         /*!<Rx FIFO 0 Put Index                       */

+#define FDCAN_RXF0S_F0F_Pos       (24U)

+#define FDCAN_RXF0S_F0F_Msk       (0x1UL << FDCAN_RXF0S_F0F_Pos)               /*!< 0x01000000 */

+#define FDCAN_RXF0S_F0F           FDCAN_RXF0S_F0F_Msk                          /*!<Rx FIFO 0 Full                            */

+#define FDCAN_RXF0S_RF0L_Pos      (25U)

+#define FDCAN_RXF0S_RF0L_Msk      (0x1UL << FDCAN_RXF0S_RF0L_Pos)              /*!< 0x02000000 */

+#define FDCAN_RXF0S_RF0L          FDCAN_RXF0S_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                    */

+

+/*****************  Bit definition for FDCAN_RXF0A register  ********************/

+#define FDCAN_RXF0A_F0AI_Pos      (0U)

+#define FDCAN_RXF0A_F0AI_Msk      (0x3FUL << FDCAN_RXF0A_F0AI_Pos)             /*!< 0x0000003F */

+#define FDCAN_RXF0A_F0AI          FDCAN_RXF0A_F0AI_Msk                         /*!<Rx FIFO 0 Acknowledge Index               */

+

+/*****************  Bit definition for FDCAN_RXBC register  ********************/

+#define FDCAN_RXBC_RBSA_Pos       (2U)

+#define FDCAN_RXBC_RBSA_Msk       (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)            /*!< 0x0000FFFC */

+#define FDCAN_RXBC_RBSA           FDCAN_RXBC_RBSA_Msk                          /*!<Rx Buffer Start Address                   */

+

+/*****************  Bit definition for FDCAN_RXF1C register  ********************/

+#define FDCAN_RXF1C_F1SA_Pos      (2U)

+#define FDCAN_RXF1C_F1SA_Msk      (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_RXF1C_F1SA          FDCAN_RXF1C_F1SA_Msk                         /*!<Rx FIFO 1 Start Address                   */

+#define FDCAN_RXF1C_F1S_Pos       (16U)

+#define FDCAN_RXF1C_F1S_Msk       (0x7FUL << FDCAN_RXF1C_F1S_Pos)              /*!< 0x007F0000 */

+#define FDCAN_RXF1C_F1S           FDCAN_RXF1C_F1S_Msk                          /*!<Number of Rx FIFO 1 elements              */

+#define FDCAN_RXF1C_F1WM_Pos      (24U)

+#define FDCAN_RXF1C_F1WM_Msk      (0x7FUL << FDCAN_RXF1C_F1WM_Pos)             /*!< 0x7F000000 */

+#define FDCAN_RXF1C_F1WM          FDCAN_RXF1C_F1WM_Msk                         /*!<Rx FIFO 1 Watermark                       */

+#define FDCAN_RXF1C_F1OM_Pos      (31U)

+#define FDCAN_RXF1C_F1OM_Msk      (0x1UL << FDCAN_RXF1C_F1OM_Pos)              /*!< 0x80000000 */

+#define FDCAN_RXF1C_F1OM          FDCAN_RXF1C_F1OM_Msk                         /*!<FIFO 1 Operation Mode                     */

+

+/*****************  Bit definition for FDCAN_RXF1S register  ********************/

+#define FDCAN_RXF1S_F1FL_Pos      (0U)

+#define FDCAN_RXF1S_F1FL_Msk      (0x7FUL << FDCAN_RXF1S_F1FL_Pos)             /*!< 0x0000007F */

+#define FDCAN_RXF1S_F1FL          FDCAN_RXF1S_F1FL_Msk                         /*!<Rx FIFO 1 Fill Level                      */

+#define FDCAN_RXF1S_F1GI_Pos      (8U)

+#define FDCAN_RXF1S_F1GI_Msk      (0x3FUL << FDCAN_RXF1S_F1GI_Pos)             /*!< 0x00003F00 */

+#define FDCAN_RXF1S_F1GI          FDCAN_RXF1S_F1GI_Msk                         /*!<Rx FIFO 1 Get Index                       */

+#define FDCAN_RXF1S_F1PI_Pos      (16U)

+#define FDCAN_RXF1S_F1PI_Msk      (0x3FUL << FDCAN_RXF1S_F1PI_Pos)             /*!< 0x003F0000 */

+#define FDCAN_RXF1S_F1PI          FDCAN_RXF1S_F1PI_Msk                         /*!<Rx FIFO 1 Put Index                       */

+#define FDCAN_RXF1S_F1F_Pos       (24U)

+#define FDCAN_RXF1S_F1F_Msk       (0x1UL << FDCAN_RXF1S_F1F_Pos)               /*!< 0x01000000 */

+#define FDCAN_RXF1S_F1F           FDCAN_RXF1S_F1F_Msk                          /*!<Rx FIFO 1 Full                            */

+#define FDCAN_RXF1S_RF1L_Pos      (25U)

+#define FDCAN_RXF1S_RF1L_Msk      (0x1UL << FDCAN_RXF1S_RF1L_Pos)              /*!< 0x02000000 */

+#define FDCAN_RXF1S_RF1L          FDCAN_RXF1S_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                    */

+

+/*****************  Bit definition for FDCAN_RXF1A register  ********************/

+#define FDCAN_RXF1A_F1AI_Pos      (0U)

+#define FDCAN_RXF1A_F1AI_Msk      (0x3FUL << FDCAN_RXF1A_F1AI_Pos)             /*!< 0x0000003F */

+#define FDCAN_RXF1A_F1AI          FDCAN_RXF1A_F1AI_Msk                         /*!<Rx FIFO 1 Acknowledge Index               */

+

+/*****************  Bit definition for FDCAN_RXESC register  ********************/

+#define FDCAN_RXESC_F0DS_Pos      (0U)

+#define FDCAN_RXESC_F0DS_Msk      (0x7UL << FDCAN_RXESC_F0DS_Pos)              /*!< 0x00000007 */

+#define FDCAN_RXESC_F0DS          FDCAN_RXESC_F0DS_Msk                         /*!<Rx FIFO 1 Data Field Size                 */

+#define FDCAN_RXESC_F1DS_Pos      (4U)

+#define FDCAN_RXESC_F1DS_Msk      (0x7UL << FDCAN_RXESC_F1DS_Pos)              /*!< 0x00000070 */

+#define FDCAN_RXESC_F1DS          FDCAN_RXESC_F1DS_Msk                         /*!<Rx FIFO 0 Data Field Size                 */

+#define FDCAN_RXESC_RBDS_Pos      (8U)

+#define FDCAN_RXESC_RBDS_Msk      (0x7UL << FDCAN_RXESC_RBDS_Pos)              /*!< 0x00000700 */

+#define FDCAN_RXESC_RBDS          FDCAN_RXESC_RBDS_Msk                         /*!<Rx Buffer Data Field Size                 */

+

+/*****************  Bit definition for FDCAN_TXBC register  *********************/

+#define FDCAN_TXBC_TBSA_Pos       (2U)

+#define FDCAN_TXBC_TBSA_Msk       (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)            /*!< 0x0000FFFC */

+#define FDCAN_TXBC_TBSA           FDCAN_TXBC_TBSA_Msk                          /*!<Tx Buffers Start Address                  */

+#define FDCAN_TXBC_NDTB_Pos       (16U)

+#define FDCAN_TXBC_NDTB_Msk       (0x3FUL << FDCAN_TXBC_NDTB_Pos)              /*!< 0x003F0000 */

+#define FDCAN_TXBC_NDTB           FDCAN_TXBC_NDTB_Msk                          /*!<Number of Dedicated Transmit Buffers      */

+#define FDCAN_TXBC_TFQS_Pos       (24U)

+#define FDCAN_TXBC_TFQS_Msk       (0x3FUL << FDCAN_TXBC_TFQS_Pos)              /*!< 0x3F000000 */

+#define FDCAN_TXBC_TFQS           FDCAN_TXBC_TFQS_Msk                          /*!<Transmit FIFO/Queue Size                  */

+#define FDCAN_TXBC_TFQM_Pos       (30U)

+#define FDCAN_TXBC_TFQM_Msk       (0x1UL << FDCAN_TXBC_TFQM_Pos)               /*!< 0x40000000 */

+#define FDCAN_TXBC_TFQM           FDCAN_TXBC_TFQM_Msk                          /*!<Tx FIFO/Queue Mode                        */

+

+/*****************  Bit definition for FDCAN_TXFQS register  *********************/

+#define FDCAN_TXFQS_TFFL_Pos      (0U)

+#define FDCAN_TXFQS_TFFL_Msk      (0x3FUL << FDCAN_TXFQS_TFFL_Pos)             /*!< 0x0000003F */

+#define FDCAN_TXFQS_TFFL          FDCAN_TXFQS_TFFL_Msk                         /*!<Tx FIFO Free Level                        */

+#define FDCAN_TXFQS_TFGI_Pos      (8U)

+#define FDCAN_TXFQS_TFGI_Msk      (0x1FUL << FDCAN_TXFQS_TFGI_Pos)             /*!< 0x00001F00 */

+#define FDCAN_TXFQS_TFGI          FDCAN_TXFQS_TFGI_Msk                         /*!<Tx FIFO Get Index                         */

+#define FDCAN_TXFQS_TFQPI_Pos     (16U)

+#define FDCAN_TXFQS_TFQPI_Msk     (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)            /*!< 0x001F0000 */

+#define FDCAN_TXFQS_TFQPI         FDCAN_TXFQS_TFQPI_Msk                        /*!<Tx FIFO/Queue Put Index                   */

+#define FDCAN_TXFQS_TFQF_Pos      (21U)

+#define FDCAN_TXFQS_TFQF_Msk      (0x1UL << FDCAN_TXFQS_TFQF_Pos)              /*!< 0x00200000 */

+#define FDCAN_TXFQS_TFQF          FDCAN_TXFQS_TFQF_Msk                         /*!<Tx FIFO/Queue Full                        */

+

+/*****************  Bit definition for FDCAN_TXESC register  *********************/

+#define FDCAN_TXESC_TBDS_Pos      (0U)

+#define FDCAN_TXESC_TBDS_Msk      (0x7UL << FDCAN_TXESC_TBDS_Pos)              /*!< 0x00000007 */

+#define FDCAN_TXESC_TBDS          FDCAN_TXESC_TBDS_Msk                         /*!<Tx Buffer Data Field Size                 */

+

+/*****************  Bit definition for FDCAN_TXBRP register  *********************/

+#define FDCAN_TXBRP_TRP_Pos       (0U)

+#define FDCAN_TXBRP_TRP_Msk       (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)        /*!< 0xFFFFFFFF */

+#define FDCAN_TXBRP_TRP           FDCAN_TXBRP_TRP_Msk                          /*!<Transmission Request Pending              */

+

+/*****************  Bit definition for FDCAN_TXBAR register  *********************/

+#define FDCAN_TXBAR_AR_Pos        (0U)

+#define FDCAN_TXBAR_AR_Msk        (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBAR_AR            FDCAN_TXBAR_AR_Msk                           /*!<Add Request                               */

+

+/*****************  Bit definition for FDCAN_TXBCR register  *********************/

+#define FDCAN_TXBCR_CR_Pos        (0U)

+#define FDCAN_TXBCR_CR_Msk        (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCR_CR            FDCAN_TXBCR_CR_Msk                           /*!<Cancellation Request                      */

+

+/*****************  Bit definition for FDCAN_TXBTO register  *********************/

+#define FDCAN_TXBTO_TO_Pos        (0U)

+#define FDCAN_TXBTO_TO_Msk        (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBTO_TO            FDCAN_TXBTO_TO_Msk                           /*!<Transmission Occurred                     */

+

+/*****************  Bit definition for FDCAN_TXBCF register  *********************/

+#define FDCAN_TXBCF_CF_Pos        (0U)

+#define FDCAN_TXBCF_CF_Msk        (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCF_CF            FDCAN_TXBCF_CF_Msk                           /*!<Cancellation Finished                     */

+

+/*****************  Bit definition for FDCAN_TXBTIE register  ********************/

+#define FDCAN_TXBTIE_TIE_Pos      (0U)

+#define FDCAN_TXBTIE_TIE_Msk      (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)       /*!< 0xFFFFFFFF */

+#define FDCAN_TXBTIE_TIE          FDCAN_TXBTIE_TIE_Msk                         /*!<Transmission Interrupt Enable             */

+

+/*****************  Bit definition for FDCAN_ TXBCIE register  *******************/

+#define FDCAN_TXBCIE_CFIE_Pos     (0U)

+#define FDCAN_TXBCIE_CFIE_Msk     (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)      /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCIE_CFIE         FDCAN_TXBCIE_CFIE_Msk                        /*!<Cancellation Finished Interrupt Enable    */

+

+/*****************  Bit definition for FDCAN_TXEFC register  *********************/

+#define FDCAN_TXEFC_EFSA_Pos      (2U)

+#define FDCAN_TXEFC_EFSA_Msk      (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_TXEFC_EFSA          FDCAN_TXEFC_EFSA_Msk                         /*!<Event FIFO Start Address                  */

+#define FDCAN_TXEFC_EFS_Pos       (16U)

+#define FDCAN_TXEFC_EFS_Msk       (0x3FUL << FDCAN_TXEFC_EFS_Pos)              /*!< 0x003F0000 */

+#define FDCAN_TXEFC_EFS           FDCAN_TXEFC_EFS_Msk                          /*!<Event FIFO Size                           */

+#define FDCAN_TXEFC_EFWM_Pos      (24U)

+#define FDCAN_TXEFC_EFWM_Msk      (0x3FUL << FDCAN_TXEFC_EFWM_Pos)             /*!< 0x3F000000 */

+#define FDCAN_TXEFC_EFWM          FDCAN_TXEFC_EFWM_Msk                         /*!<Event FIFO Watermark                      */

+

+/*****************  Bit definition for FDCAN_TXEFS register  *********************/

+#define FDCAN_TXEFS_EFFL_Pos      (0U)

+#define FDCAN_TXEFS_EFFL_Msk      (0x3FUL << FDCAN_TXEFS_EFFL_Pos)             /*!< 0x0000003F */

+#define FDCAN_TXEFS_EFFL          FDCAN_TXEFS_EFFL_Msk                         /*!<Event FIFO Fill Level                     */

+#define FDCAN_TXEFS_EFGI_Pos      (8U)

+#define FDCAN_TXEFS_EFGI_Msk      (0x1FUL << FDCAN_TXEFS_EFGI_Pos)             /*!< 0x00001F00 */

+#define FDCAN_TXEFS_EFGI          FDCAN_TXEFS_EFGI_Msk                         /*!<Event FIFO Get Index                      */

+#define FDCAN_TXEFS_EFPI_Pos      (16U)

+#define FDCAN_TXEFS_EFPI_Msk      (0x1FUL << FDCAN_TXEFS_EFPI_Pos)             /*!< 0x001F0000 */

+#define FDCAN_TXEFS_EFPI          FDCAN_TXEFS_EFPI_Msk                         /*!<Event FIFO Put Index                      */

+#define FDCAN_TXEFS_EFF_Pos       (24U)

+#define FDCAN_TXEFS_EFF_Msk       (0x1UL << FDCAN_TXEFS_EFF_Pos)               /*!< 0x01000000 */

+#define FDCAN_TXEFS_EFF           FDCAN_TXEFS_EFF_Msk                          /*!<Event FIFO Full                           */

+#define FDCAN_TXEFS_TEFL_Pos      (25U)

+#define FDCAN_TXEFS_TEFL_Msk      (0x1UL << FDCAN_TXEFS_TEFL_Pos)              /*!< 0x02000000 */

+#define FDCAN_TXEFS_TEFL          FDCAN_TXEFS_TEFL_Msk                         /*!<Tx Event FIFO Element Lost                */

+

+/*****************  Bit definition for FDCAN_TXEFA register  *********************/

+#define FDCAN_TXEFA_EFAI_Pos      (0U)

+#define FDCAN_TXEFA_EFAI_Msk      (0x1FUL << FDCAN_TXEFA_EFAI_Pos)             /*!< 0x0000001F */

+#define FDCAN_TXEFA_EFAI          FDCAN_TXEFA_EFAI_Msk                         /*!<Event FIFO Acknowledge Index              */

+

+/*****************  Bit definition for FDCAN_TTTMC register  *********************/

+#define FDCAN_TTTMC_TMSA_Pos      (2U)

+#define FDCAN_TTTMC_TMSA_Msk      (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_TTTMC_TMSA          FDCAN_TTTMC_TMSA_Msk                         /*!<Trigger Memory Start Address              */

+#define FDCAN_TTTMC_TME_Pos       (16U)

+#define FDCAN_TTTMC_TME_Msk       (0x7FUL << FDCAN_TTTMC_TME_Pos)              /*!< 0x007F0000 */

+#define FDCAN_TTTMC_TME           FDCAN_TTTMC_TME_Msk                          /*!<Trigger Memory Elements                   */

+

+/*****************  Bit definition for FDCAN_TTRMC register  *********************/

+#define FDCAN_TTRMC_RID_Pos       (0U)

+#define FDCAN_TTRMC_RID_Msk       (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)        /*!< 0x1FFFFFFF */

+#define FDCAN_TTRMC_RID           FDCAN_TTRMC_RID_Msk                          /*!<Reference Identifier                      */

+#define FDCAN_TTRMC_XTD_Pos       (30U)

+#define FDCAN_TTRMC_XTD_Msk       (0x1UL << FDCAN_TTRMC_XTD_Pos)               /*!< 0x40000000 */

+#define FDCAN_TTRMC_XTD           FDCAN_TTRMC_XTD_Msk                          /*!< Extended Identifier                      */

+#define FDCAN_TTRMC_RMPS_Pos      (31U)

+#define FDCAN_TTRMC_RMPS_Msk      (0x1UL << FDCAN_TTRMC_RMPS_Pos)              /*!< 0x80000000 */

+#define FDCAN_TTRMC_RMPS          FDCAN_TTRMC_RMPS_Msk                         /*!<Reference Message Payload Select          */

+

+/*****************  Bit definition for FDCAN_TTOCF register  *********************/

+#define FDCAN_TTOCF_OM_Pos        (0U)

+#define FDCAN_TTOCF_OM_Msk        (0x3UL << FDCAN_TTOCF_OM_Pos)                /*!< 0x00000003 */

+#define FDCAN_TTOCF_OM            FDCAN_TTOCF_OM_Msk                           /*!<Operation Mode                            */

+#define FDCAN_TTOCF_GEN_Pos       (3U)

+#define FDCAN_TTOCF_GEN_Msk       (0x1UL << FDCAN_TTOCF_GEN_Pos)               /*!< 0x00000008 */

+#define FDCAN_TTOCF_GEN           FDCAN_TTOCF_GEN_Msk                          /*!<Gap Enable                                */

+#define FDCAN_TTOCF_TM_Pos        (4U)

+#define FDCAN_TTOCF_TM_Msk        (0x1UL << FDCAN_TTOCF_TM_Pos)                /*!< 0x00000010 */

+#define FDCAN_TTOCF_TM            FDCAN_TTOCF_TM_Msk                           /*!<Time Master                               */

+#define FDCAN_TTOCF_LDSDL_Pos     (5U)

+#define FDCAN_TTOCF_LDSDL_Msk     (0x7UL << FDCAN_TTOCF_LDSDL_Pos)             /*!< 0x000000E0 */

+#define FDCAN_TTOCF_LDSDL         FDCAN_TTOCF_LDSDL_Msk                        /*!<LD of Synchronization Deviation Limit     */

+#define FDCAN_TTOCF_IRTO_Pos      (8U)

+#define FDCAN_TTOCF_IRTO_Msk      (0x7FUL << FDCAN_TTOCF_IRTO_Pos)             /*!< 0x00007F00 */

+#define FDCAN_TTOCF_IRTO          FDCAN_TTOCF_IRTO_Msk                         /*!<Initial Reference Trigger Offset          */

+#define FDCAN_TTOCF_EECS_Pos      (15U)

+#define FDCAN_TTOCF_EECS_Msk      (0x1UL << FDCAN_TTOCF_EECS_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTOCF_EECS          FDCAN_TTOCF_EECS_Msk                         /*!<Enable External Clock Synchronization     */

+#define FDCAN_TTOCF_AWL_Pos       (16U)

+#define FDCAN_TTOCF_AWL_Msk       (0xFFUL << FDCAN_TTOCF_AWL_Pos)              /*!< 0x00FF0000 */

+#define FDCAN_TTOCF_AWL           FDCAN_TTOCF_AWL_Msk                          /*!<Application Watchdog Limit                */

+#define FDCAN_TTOCF_EGTF_Pos      (24U)

+#define FDCAN_TTOCF_EGTF_Msk      (0x1UL << FDCAN_TTOCF_EGTF_Pos)              /*!< 0x01000000 */

+#define FDCAN_TTOCF_EGTF          FDCAN_TTOCF_EGTF_Msk                         /*!<Enable Global Time Filtering              */

+#define FDCAN_TTOCF_ECC_Pos       (25U)

+#define FDCAN_TTOCF_ECC_Msk       (0x1UL << FDCAN_TTOCF_ECC_Pos)               /*!< 0x02000000 */

+#define FDCAN_TTOCF_ECC           FDCAN_TTOCF_ECC_Msk                          /*!<Enable Clock Calibration                  */

+#define FDCAN_TTOCF_EVTP_Pos      (26U)

+#define FDCAN_TTOCF_EVTP_Msk      (0x1UL << FDCAN_TTOCF_EVTP_Pos)              /*!< 0x04000000 */

+#define FDCAN_TTOCF_EVTP          FDCAN_TTOCF_EVTP_Msk                         /*!<Event Trigger Polarity                    */

+

+/*****************  Bit definition for FDCAN_TTMLM register  *********************/

+#define FDCAN_TTMLM_CCM_Pos       (0U)

+#define FDCAN_TTMLM_CCM_Msk       (0x3FUL << FDCAN_TTMLM_CCM_Pos)              /*!< 0x0000003F */

+#define FDCAN_TTMLM_CCM           FDCAN_TTMLM_CCM_Msk                          /*!<Cycle Count Max                           */

+#define FDCAN_TTMLM_CSS_Pos       (6U)

+#define FDCAN_TTMLM_CSS_Msk       (0x3UL << FDCAN_TTMLM_CSS_Pos)               /*!< 0x000000C0 */

+#define FDCAN_TTMLM_CSS           FDCAN_TTMLM_CSS_Msk                          /*!<Cycle Start Synchronization               */

+#define FDCAN_TTMLM_TXEW_Pos      (8U)

+#define FDCAN_TTMLM_TXEW_Msk      (0xFUL << FDCAN_TTMLM_TXEW_Pos)              /*!< 0x00000F00 */

+#define FDCAN_TTMLM_TXEW          FDCAN_TTMLM_TXEW_Msk                         /*!<Tx Enable Window                          */

+#define FDCAN_TTMLM_ENTT_Pos      (16U)

+#define FDCAN_TTMLM_ENTT_Msk      (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)            /*!< 0x0FFF0000 */

+#define FDCAN_TTMLM_ENTT          FDCAN_TTMLM_ENTT_Msk                         /*!<Expected Number of Tx Triggers            */

+

+/*****************  Bit definition for FDCAN_TURCF register  *********************/

+#define FDCAN_TURCF_NCL_Pos       (0U)

+#define FDCAN_TURCF_NCL_Msk       (0xFFFFUL << FDCAN_TURCF_NCL_Pos)            /*!< 0x0000FFFF */

+#define FDCAN_TURCF_NCL           FDCAN_TURCF_NCL_Msk                          /*!<Numerator Configuration Low               */

+#define FDCAN_TURCF_DC_Pos        (16U)

+#define FDCAN_TURCF_DC_Msk        (0x3FFFUL << FDCAN_TURCF_DC_Pos)             /*!< 0x3FFF0000 */

+#define FDCAN_TURCF_DC            FDCAN_TURCF_DC_Msk                           /*!<Denominator Configuration                 */

+#define FDCAN_TURCF_ELT_Pos       (31U)

+#define FDCAN_TURCF_ELT_Msk       (0x1UL << FDCAN_TURCF_ELT_Pos)               /*!< 0x80000000 */

+#define FDCAN_TURCF_ELT           FDCAN_TURCF_ELT_Msk                          /*!<Enable Local Time                         */

+

+/*****************  Bit definition for FDCAN_TTOCN register  ********************/

+#define FDCAN_TTOCN_SGT_Pos       (0U)

+#define FDCAN_TTOCN_SGT_Msk       (0x1UL << FDCAN_TTOCN_SGT_Pos)               /*!< 0x00000001 */

+#define FDCAN_TTOCN_SGT           FDCAN_TTOCN_SGT_Msk                          /*!<Set Global time                           */

+#define FDCAN_TTOCN_ECS_Pos       (1U)

+#define FDCAN_TTOCN_ECS_Msk       (0x1UL << FDCAN_TTOCN_ECS_Pos)               /*!< 0x00000002 */

+#define FDCAN_TTOCN_ECS           FDCAN_TTOCN_ECS_Msk                          /*!<External Clock Synchronization            */

+#define FDCAN_TTOCN_SWP_Pos       (2U)

+#define FDCAN_TTOCN_SWP_Msk       (0x1UL << FDCAN_TTOCN_SWP_Pos)               /*!< 0x00000004 */

+#define FDCAN_TTOCN_SWP           FDCAN_TTOCN_SWP_Msk                          /*!<Stop Watch Polarity                       */

+#define FDCAN_TTOCN_SWS_Pos       (3U)

+#define FDCAN_TTOCN_SWS_Msk       (0x3UL << FDCAN_TTOCN_SWS_Pos)               /*!< 0x00000018 */

+#define FDCAN_TTOCN_SWS           FDCAN_TTOCN_SWS_Msk                          /*!<Stop Watch Source                         */

+#define FDCAN_TTOCN_RTIE_Pos      (5U)

+#define FDCAN_TTOCN_RTIE_Msk      (0x1UL << FDCAN_TTOCN_RTIE_Pos)              /*!< 0x00000020 */

+#define FDCAN_TTOCN_RTIE          FDCAN_TTOCN_RTIE_Msk                         /*!<Register Time Mark Interrupt Pulse Enable */

+#define FDCAN_TTOCN_TMC_Pos       (6U)

+#define FDCAN_TTOCN_TMC_Msk       (0x3UL << FDCAN_TTOCN_TMC_Pos)               /*!< 0x000000C0 */

+#define FDCAN_TTOCN_TMC           FDCAN_TTOCN_TMC_Msk                          /*!<Register Time Mark Compare                */

+#define FDCAN_TTOCN_TTIE_Pos      (8U)

+#define FDCAN_TTOCN_TTIE_Msk      (0x1UL << FDCAN_TTOCN_TTIE_Pos)              /*!< 0x00000100 */

+#define FDCAN_TTOCN_TTIE          FDCAN_TTOCN_TTIE_Msk                         /*!<Trigger Time Mark Interrupt Pulse Enable  */

+#define FDCAN_TTOCN_GCS_Pos       (9U)

+#define FDCAN_TTOCN_GCS_Msk       (0x1UL << FDCAN_TTOCN_GCS_Pos)               /*!< 0x00000200 */

+#define FDCAN_TTOCN_GCS           FDCAN_TTOCN_GCS_Msk                          /*!<Gap Control Select                        */

+#define FDCAN_TTOCN_FGP_Pos       (10U)

+#define FDCAN_TTOCN_FGP_Msk       (0x1UL << FDCAN_TTOCN_FGP_Pos)               /*!< 0x00000400 */

+#define FDCAN_TTOCN_FGP           FDCAN_TTOCN_FGP_Msk                          /*!<Finish Gap                                */

+#define FDCAN_TTOCN_TMG_Pos       (11U)

+#define FDCAN_TTOCN_TMG_Msk       (0x1UL << FDCAN_TTOCN_TMG_Pos)               /*!< 0x00000800 */

+#define FDCAN_TTOCN_TMG           FDCAN_TTOCN_TMG_Msk                          /*!<Time Mark Gap                             */

+#define FDCAN_TTOCN_NIG_Pos       (12U)

+#define FDCAN_TTOCN_NIG_Msk       (0x1UL << FDCAN_TTOCN_NIG_Pos)               /*!< 0x00001000 */

+#define FDCAN_TTOCN_NIG           FDCAN_TTOCN_NIG_Msk                          /*!<Next is Gap                               */

+#define FDCAN_TTOCN_ESCN_Pos      (13U)

+#define FDCAN_TTOCN_ESCN_Msk      (0x1UL << FDCAN_TTOCN_ESCN_Pos)              /*!< 0x00002000 */

+#define FDCAN_TTOCN_ESCN          FDCAN_TTOCN_ESCN_Msk                         /*!<External Synchronization Control          */

+#define FDCAN_TTOCN_LCKC_Pos      (15U)

+#define FDCAN_TTOCN_LCKC_Msk      (0x1UL << FDCAN_TTOCN_LCKC_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTOCN_LCKC          FDCAN_TTOCN_LCKC_Msk                         /*!<TT Operation Control Register Locked      */

+

+/*****************  Bit definition for FDCAN_TTGTP register  ********************/

+#define FDCAN_TTGTP_TP_Pos        (0U)

+#define FDCAN_TTGTP_TP_Msk        (0xFFFFUL << FDCAN_TTGTP_TP_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTGTP_TP            FDCAN_TTGTP_TP_Msk                           /*!<Time Preset                               */

+#define FDCAN_TTGTP_CTP_Pos       (16U)

+#define FDCAN_TTGTP_CTP_Msk       (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)            /*!< 0xFFFF0000 */

+#define FDCAN_TTGTP_CTP           FDCAN_TTGTP_CTP_Msk                          /*!<Cycle Time Target Phase                   */

+

+/*****************  Bit definition for FDCAN_TTTMK register  ********************/

+#define FDCAN_TTTMK_TM_Pos        (0U)

+#define FDCAN_TTTMK_TM_Msk        (0xFFFFUL << FDCAN_TTTMK_TM_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTTMK_TM            FDCAN_TTTMK_TM_Msk                           /*!<Time Mark                                 */

+#define FDCAN_TTTMK_TICC_Pos      (16U)

+#define FDCAN_TTTMK_TICC_Msk      (0x7FUL << FDCAN_TTTMK_TICC_Pos)             /*!< 0x007F0000 */

+#define FDCAN_TTTMK_TICC          FDCAN_TTTMK_TICC_Msk                         /*!<Time Mark Cycle Code                      */

+#define FDCAN_TTTMK_LCKM_Pos      (31U)

+#define FDCAN_TTTMK_LCKM_Msk      (0x1UL << FDCAN_TTTMK_LCKM_Pos)              /*!< 0x80000000 */

+#define FDCAN_TTTMK_LCKM          FDCAN_TTTMK_LCKM_Msk                         /*!<TT Time Mark Register Locked              */

+

+/*****************  Bit definition for FDCAN_TTIR register  ********************/

+#define FDCAN_TTIR_SBC_Pos        (0U)

+#define FDCAN_TTIR_SBC_Msk        (0x1UL << FDCAN_TTIR_SBC_Pos)                /*!< 0x00000001 */

+#define FDCAN_TTIR_SBC            FDCAN_TTIR_SBC_Msk                           /*!<Start of Basic Cycle                      */

+#define FDCAN_TTIR_SMC_Pos        (1U)

+#define FDCAN_TTIR_SMC_Msk        (0x1UL << FDCAN_TTIR_SMC_Pos)                /*!< 0x00000002 */

+#define FDCAN_TTIR_SMC            FDCAN_TTIR_SMC_Msk                           /*!<Start of Matrix Cycle                     */

+#define FDCAN_TTIR_CSM_Pos        (2U)

+#define FDCAN_TTIR_CSM_Msk        (0x1UL << FDCAN_TTIR_CSM_Pos)                /*!< 0x00000004 */

+#define FDCAN_TTIR_CSM            FDCAN_TTIR_CSM_Msk                           /*!<Change of Synchronization Mode            */

+#define FDCAN_TTIR_SOG_Pos        (3U)

+#define FDCAN_TTIR_SOG_Msk        (0x1UL << FDCAN_TTIR_SOG_Pos)                /*!< 0x00000008 */

+#define FDCAN_TTIR_SOG            FDCAN_TTIR_SOG_Msk                           /*!<Start of Gap                              */

+#define FDCAN_TTIR_RTMI_Pos       (4U)

+#define FDCAN_TTIR_RTMI_Msk       (0x1UL << FDCAN_TTIR_RTMI_Pos)               /*!< 0x00000010 */

+#define FDCAN_TTIR_RTMI           FDCAN_TTIR_RTMI_Msk                          /*!<Register Time Mark Interrupt              */

+#define FDCAN_TTIR_TTMI_Pos       (5U)

+#define FDCAN_TTIR_TTMI_Msk       (0x1UL << FDCAN_TTIR_TTMI_Pos)               /*!< 0x00000020 */

+#define FDCAN_TTIR_TTMI           FDCAN_TTIR_TTMI_Msk                          /*!<Trigger Time Mark Event Internal          */

+#define FDCAN_TTIR_SWE_Pos        (6U)

+#define FDCAN_TTIR_SWE_Msk        (0x1UL << FDCAN_TTIR_SWE_Pos)                /*!< 0x00000040 */

+#define FDCAN_TTIR_SWE            FDCAN_TTIR_SWE_Msk                           /*!<Stop Watch Event                          */

+#define FDCAN_TTIR_GTW_Pos        (7U)

+#define FDCAN_TTIR_GTW_Msk        (0x1UL << FDCAN_TTIR_GTW_Pos)                /*!< 0x00000080 */

+#define FDCAN_TTIR_GTW            FDCAN_TTIR_GTW_Msk                           /*!<Global Time Wrap                          */

+#define FDCAN_TTIR_GTD_Pos        (8U)

+#define FDCAN_TTIR_GTD_Msk        (0x1UL << FDCAN_TTIR_GTD_Pos)                /*!< 0x00000100 */

+#define FDCAN_TTIR_GTD            FDCAN_TTIR_GTD_Msk                           /*!<Global Time Discontinuity                 */

+#define FDCAN_TTIR_GTE_Pos        (9U)

+#define FDCAN_TTIR_GTE_Msk        (0x1UL << FDCAN_TTIR_GTE_Pos)                /*!< 0x00000200 */

+#define FDCAN_TTIR_GTE            FDCAN_TTIR_GTE_Msk                           /*!<Global Time Error                         */

+#define FDCAN_TTIR_TXU_Pos        (10U)

+#define FDCAN_TTIR_TXU_Msk        (0x1UL << FDCAN_TTIR_TXU_Pos)                /*!< 0x00000400 */

+#define FDCAN_TTIR_TXU            FDCAN_TTIR_TXU_Msk                           /*!<Tx Count Underflow                        */

+#define FDCAN_TTIR_TXO_Pos        (11U)

+#define FDCAN_TTIR_TXO_Msk        (0x1UL << FDCAN_TTIR_TXO_Pos)                /*!< 0x00000800 */

+#define FDCAN_TTIR_TXO            FDCAN_TTIR_TXO_Msk                           /*!<Tx Count Overflow                         */

+#define FDCAN_TTIR_SE1_Pos        (12U)

+#define FDCAN_TTIR_SE1_Msk        (0x1UL << FDCAN_TTIR_SE1_Pos)                /*!< 0x00001000 */

+#define FDCAN_TTIR_SE1            FDCAN_TTIR_SE1_Msk                           /*!<Scheduling Error 1                        */

+#define FDCAN_TTIR_SE2_Pos        (13U)

+#define FDCAN_TTIR_SE2_Msk        (0x1UL << FDCAN_TTIR_SE2_Pos)                /*!< 0x00002000 */

+#define FDCAN_TTIR_SE2            FDCAN_TTIR_SE2_Msk                           /*!<Scheduling Error 2                        */

+#define FDCAN_TTIR_ELC_Pos        (14U)

+#define FDCAN_TTIR_ELC_Msk        (0x1UL << FDCAN_TTIR_ELC_Pos)                /*!< 0x00004000 */

+#define FDCAN_TTIR_ELC            FDCAN_TTIR_ELC_Msk                           /*!<Error Level Changed                       */

+#define FDCAN_TTIR_IWT_Pos        (15U)

+#define FDCAN_TTIR_IWT_Msk        (0x1UL << FDCAN_TTIR_IWT_Pos)                /*!< 0x00008000 */

+#define FDCAN_TTIR_IWT            FDCAN_TTIR_IWT_Msk                           /*!<Initialization Watch Trigger              */

+#define FDCAN_TTIR_WT_Pos         (16U)

+#define FDCAN_TTIR_WT_Msk         (0x1UL << FDCAN_TTIR_WT_Pos)                 /*!< 0x00010000 */

+#define FDCAN_TTIR_WT             FDCAN_TTIR_WT_Msk                            /*!<Watch Trigger                             */

+#define FDCAN_TTIR_AW_Pos         (17U)

+#define FDCAN_TTIR_AW_Msk         (0x1UL << FDCAN_TTIR_AW_Pos)                 /*!< 0x00020000 */

+#define FDCAN_TTIR_AW             FDCAN_TTIR_AW_Msk                            /*!<Application Watchdog                      */

+#define FDCAN_TTIR_CER_Pos        (18U)

+#define FDCAN_TTIR_CER_Msk        (0x1UL << FDCAN_TTIR_CER_Pos)                /*!< 0x00040000 */

+#define FDCAN_TTIR_CER            FDCAN_TTIR_CER_Msk                           /*!<Configuration Error                       */

+

+/*****************  Bit definition for FDCAN_TTIE register  ********************/

+#define FDCAN_TTIE_SBCE_Pos       (0U)

+#define FDCAN_TTIE_SBCE_Msk       (0x1UL << FDCAN_TTIE_SBCE_Pos)               /*!< 0x00000001 */

+#define FDCAN_TTIE_SBCE           FDCAN_TTIE_SBCE_Msk                          /*!<Start of Basic Cycle Interrupt Enable             */

+#define FDCAN_TTIE_SMCE_Pos       (1U)

+#define FDCAN_TTIE_SMCE_Msk       (0x1UL << FDCAN_TTIE_SMCE_Pos)               /*!< 0x00000002 */

+#define FDCAN_TTIE_SMCE           FDCAN_TTIE_SMCE_Msk                          /*!<Start of Matrix Cycle Interrupt Enable            */

+#define FDCAN_TTIE_CSME_Pos       (2U)

+#define FDCAN_TTIE_CSME_Msk       (0x1UL << FDCAN_TTIE_CSME_Pos)               /*!< 0x00000004 */

+#define FDCAN_TTIE_CSME           FDCAN_TTIE_CSME_Msk                          /*!<Change of Synchronization Mode Interrupt Enable   */

+#define FDCAN_TTIE_SOGE_Pos       (3U)

+#define FDCAN_TTIE_SOGE_Msk       (0x1UL << FDCAN_TTIE_SOGE_Pos)               /*!< 0x00000008 */

+#define FDCAN_TTIE_SOGE           FDCAN_TTIE_SOGE_Msk                          /*!<Start of Gap Interrupt Enable                     */

+#define FDCAN_TTIE_RTMIE_Pos      (4U)

+#define FDCAN_TTIE_RTMIE_Msk      (0x1UL << FDCAN_TTIE_RTMIE_Pos)              /*!< 0x00000010 */

+#define FDCAN_TTIE_RTMIE          FDCAN_TTIE_RTMIE_Msk                         /*!<Register Time Mark Interrupt Interrupt Enable     */

+#define FDCAN_TTIE_TTMIE_Pos      (5U)

+#define FDCAN_TTIE_TTMIE_Msk      (0x1UL << FDCAN_TTIE_TTMIE_Pos)              /*!< 0x00000020 */

+#define FDCAN_TTIE_TTMIE          FDCAN_TTIE_TTMIE_Msk                         /*!<Trigger Time Mark Event Internal Interrupt Enable */

+#define FDCAN_TTIE_SWEE_Pos       (6U)

+#define FDCAN_TTIE_SWEE_Msk       (0x1UL << FDCAN_TTIE_SWEE_Pos)               /*!< 0x00000040 */

+#define FDCAN_TTIE_SWEE           FDCAN_TTIE_SWEE_Msk                          /*!<Stop Watch Event Interrupt Enable                 */

+#define FDCAN_TTIE_GTWE_Pos       (7U)

+#define FDCAN_TTIE_GTWE_Msk       (0x1UL << FDCAN_TTIE_GTWE_Pos)               /*!< 0x00000080 */

+#define FDCAN_TTIE_GTWE           FDCAN_TTIE_GTWE_Msk                          /*!<Global Time Wrap Interrupt Enable                 */

+#define FDCAN_TTIE_GTDE_Pos       (8U)

+#define FDCAN_TTIE_GTDE_Msk       (0x1UL << FDCAN_TTIE_GTDE_Pos)               /*!< 0x00000100 */

+#define FDCAN_TTIE_GTDE           FDCAN_TTIE_GTDE_Msk                          /*!<Global Time Discontinuity Interrupt Enable        */

+#define FDCAN_TTIE_GTEE_Pos       (9U)

+#define FDCAN_TTIE_GTEE_Msk       (0x1UL << FDCAN_TTIE_GTEE_Pos)               /*!< 0x00000200 */

+#define FDCAN_TTIE_GTEE           FDCAN_TTIE_GTEE_Msk                          /*!<Global Time Error Interrupt Enable                */

+#define FDCAN_TTIE_TXUE_Pos       (10U)

+#define FDCAN_TTIE_TXUE_Msk       (0x1UL << FDCAN_TTIE_TXUE_Pos)               /*!< 0x00000400 */

+#define FDCAN_TTIE_TXUE           FDCAN_TTIE_TXUE_Msk                          /*!<Tx Count Underflow Interrupt Enable               */

+#define FDCAN_TTIE_TXOE_Pos       (11U)

+#define FDCAN_TTIE_TXOE_Msk       (0x1UL << FDCAN_TTIE_TXOE_Pos)               /*!< 0x00000800 */

+#define FDCAN_TTIE_TXOE           FDCAN_TTIE_TXOE_Msk                          /*!<Tx Count Overflow Interrupt Enable                */

+#define FDCAN_TTIE_SE1E_Pos       (12U)

+#define FDCAN_TTIE_SE1E_Msk       (0x1UL << FDCAN_TTIE_SE1E_Pos)               /*!< 0x00001000 */

+#define FDCAN_TTIE_SE1E           FDCAN_TTIE_SE1E_Msk                          /*!<Scheduling Error 1 Interrupt Enable               */

+#define FDCAN_TTIE_SE2E_Pos       (13U)

+#define FDCAN_TTIE_SE2E_Msk       (0x1UL << FDCAN_TTIE_SE2E_Pos)               /*!< 0x00002000 */

+#define FDCAN_TTIE_SE2E           FDCAN_TTIE_SE2E_Msk                          /*!<Scheduling Error 2 Interrupt Enable               */

+#define FDCAN_TTIE_ELCE_Pos       (14U)

+#define FDCAN_TTIE_ELCE_Msk       (0x1UL << FDCAN_TTIE_ELCE_Pos)               /*!< 0x00004000 */

+#define FDCAN_TTIE_ELCE           FDCAN_TTIE_ELCE_Msk                          /*!<Error Level Changed Interrupt Enable              */

+#define FDCAN_TTIE_IWTE_Pos       (15U)

+#define FDCAN_TTIE_IWTE_Msk       (0x1UL << FDCAN_TTIE_IWTE_Pos)               /*!< 0x00008000 */

+#define FDCAN_TTIE_IWTE           FDCAN_TTIE_IWTE_Msk                          /*!<Initialization Watch Trigger Interrupt Enable     */

+#define FDCAN_TTIE_WTE_Pos        (16U)

+#define FDCAN_TTIE_WTE_Msk        (0x1UL << FDCAN_TTIE_WTE_Pos)                /*!< 0x00010000 */

+#define FDCAN_TTIE_WTE            FDCAN_TTIE_WTE_Msk                           /*!<Watch Trigger Interrupt Enable                    */

+#define FDCAN_TTIE_AWE_Pos        (17U)

+#define FDCAN_TTIE_AWE_Msk        (0x1UL << FDCAN_TTIE_AWE_Pos)                /*!< 0x00020000 */

+#define FDCAN_TTIE_AWE            FDCAN_TTIE_AWE_Msk                           /*!<Application Watchdog Interrupt Enable             */

+#define FDCAN_TTIE_CERE_Pos       (18U)

+#define FDCAN_TTIE_CERE_Msk       (0x1UL << FDCAN_TTIE_CERE_Pos)               /*!< 0x00040000 */

+#define FDCAN_TTIE_CERE           FDCAN_TTIE_CERE_Msk                          /*!<Configuration Error Interrupt Enable              */

+

+/*****************  Bit definition for FDCAN_TTILS register  ********************/

+#define FDCAN_TTILS_SBCS_Pos      (0U)

+#define FDCAN_TTILS_SBCS_Msk      (0x1UL << FDCAN_TTILS_SBCS_Pos)              /*!< 0x00000001 */

+#define FDCAN_TTILS_SBCS          FDCAN_TTILS_SBCS_Msk                         /*!<Start of Basic Cycle Interrupt Line               */

+#define FDCAN_TTILS_SMCS_Pos      (1U)

+#define FDCAN_TTILS_SMCS_Msk      (0x1UL << FDCAN_TTILS_SMCS_Pos)              /*!< 0x00000002 */

+#define FDCAN_TTILS_SMCS          FDCAN_TTILS_SMCS_Msk                         /*!<Start of Matrix Cycle Interrupt Line              */

+#define FDCAN_TTILS_CSMS_Pos      (2U)

+#define FDCAN_TTILS_CSMS_Msk      (0x1UL << FDCAN_TTILS_CSMS_Pos)              /*!< 0x00000004 */

+#define FDCAN_TTILS_CSMS          FDCAN_TTILS_CSMS_Msk                         /*!<Change of Synchronization Mode Interrupt Line     */

+#define FDCAN_TTILS_SOGS_Pos      (3U)

+#define FDCAN_TTILS_SOGS_Msk      (0x1UL << FDCAN_TTILS_SOGS_Pos)              /*!< 0x00000008 */

+#define FDCAN_TTILS_SOGS          FDCAN_TTILS_SOGS_Msk                         /*!<Start of Gap Interrupt Line                       */

+#define FDCAN_TTILS_RTMIS_Pos     (4U)

+#define FDCAN_TTILS_RTMIS_Msk     (0x1UL << FDCAN_TTILS_RTMIS_Pos)             /*!< 0x00000010 */

+#define FDCAN_TTILS_RTMIS         FDCAN_TTILS_RTMIS_Msk                        /*!<Register Time Mark Interrupt Interrupt Line       */

+#define FDCAN_TTILS_TTMIS_Pos     (5U)

+#define FDCAN_TTILS_TTMIS_Msk     (0x1UL << FDCAN_TTILS_TTMIS_Pos)             /*!< 0x00000020 */

+#define FDCAN_TTILS_TTMIS         FDCAN_TTILS_TTMIS_Msk                        /*!<Trigger Time Mark Event Internal Interrupt Line   */

+#define FDCAN_TTILS_SWES_Pos      (6U)

+#define FDCAN_TTILS_SWES_Msk      (0x1UL << FDCAN_TTILS_SWES_Pos)              /*!< 0x00000040 */

+#define FDCAN_TTILS_SWES          FDCAN_TTILS_SWES_Msk                         /*!<Stop Watch Event Interrupt Line                   */

+#define FDCAN_TTILS_GTWS_Pos      (7U)

+#define FDCAN_TTILS_GTWS_Msk      (0x1UL << FDCAN_TTILS_GTWS_Pos)              /*!< 0x00000080 */

+#define FDCAN_TTILS_GTWS          FDCAN_TTILS_GTWS_Msk                         /*!<Global Time Wrap Interrupt Line                   */

+#define FDCAN_TTILS_GTDS_Pos      (8U)

+#define FDCAN_TTILS_GTDS_Msk      (0x1UL << FDCAN_TTILS_GTDS_Pos)              /*!< 0x00000100 */

+#define FDCAN_TTILS_GTDS          FDCAN_TTILS_GTDS_Msk                         /*!<Global Time Discontinuity Interrupt Line          */

+#define FDCAN_TTILS_GTES_Pos      (9U)

+#define FDCAN_TTILS_GTES_Msk      (0x1UL << FDCAN_TTILS_GTES_Pos)              /*!< 0x00000200 */

+#define FDCAN_TTILS_GTES          FDCAN_TTILS_GTES_Msk                         /*!<Global Time Error Interrupt Line                  */

+#define FDCAN_TTILS_TXUS_Pos      (10U)

+#define FDCAN_TTILS_TXUS_Msk      (0x1UL << FDCAN_TTILS_TXUS_Pos)              /*!< 0x00000400 */

+#define FDCAN_TTILS_TXUS          FDCAN_TTILS_TXUS_Msk                         /*!<Tx Count Underflow Interrupt Line                 */

+#define FDCAN_TTILS_TXOS_Pos      (11U)

+#define FDCAN_TTILS_TXOS_Msk      (0x1UL << FDCAN_TTILS_TXOS_Pos)              /*!< 0x00000800 */

+#define FDCAN_TTILS_TXOS          FDCAN_TTILS_TXOS_Msk                         /*!<Tx Count Overflow Interrupt Line                  */

+#define FDCAN_TTILS_SE1S_Pos      (12U)

+#define FDCAN_TTILS_SE1S_Msk      (0x1UL << FDCAN_TTILS_SE1S_Pos)              /*!< 0x00001000 */

+#define FDCAN_TTILS_SE1S          FDCAN_TTILS_SE1S_Msk                         /*!<Scheduling Error 1 Interrupt Line                 */

+#define FDCAN_TTILS_SE2S_Pos      (13U)

+#define FDCAN_TTILS_SE2S_Msk      (0x1UL << FDCAN_TTILS_SE2S_Pos)              /*!< 0x00002000 */

+#define FDCAN_TTILS_SE2S          FDCAN_TTILS_SE2S_Msk                         /*!<Scheduling Error 2 Interrupt Line                 */

+#define FDCAN_TTILS_ELCS_Pos      (14U)

+#define FDCAN_TTILS_ELCS_Msk      (0x1UL << FDCAN_TTILS_ELCS_Pos)              /*!< 0x00004000 */

+#define FDCAN_TTILS_ELCS          FDCAN_TTILS_ELCS_Msk                         /*!<Error Level Changed Interrupt Line                */

+#define FDCAN_TTILS_IWTS_Pos      (15U)

+#define FDCAN_TTILS_IWTS_Msk      (0x1UL << FDCAN_TTILS_IWTS_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTILS_IWTS          FDCAN_TTILS_IWTS_Msk                         /*!<Initialization Watch Trigger Interrupt Line       */

+#define FDCAN_TTILS_WTS_Pos       (16U)

+#define FDCAN_TTILS_WTS_Msk       (0x1UL << FDCAN_TTILS_WTS_Pos)               /*!< 0x00010000 */

+#define FDCAN_TTILS_WTS           FDCAN_TTILS_WTS_Msk                          /*!<Watch Trigger Interrupt Line                      */

+#define FDCAN_TTILS_AWS_Pos       (17U)

+#define FDCAN_TTILS_AWS_Msk       (0x1UL << FDCAN_TTILS_AWS_Pos)               /*!< 0x00020000 */

+#define FDCAN_TTILS_AWS           FDCAN_TTILS_AWS_Msk                          /*!<Application Watchdog Interrupt Line               */

+#define FDCAN_TTILS_CERS_Pos      (18U)

+#define FDCAN_TTILS_CERS_Msk      (0x1UL << FDCAN_TTILS_CERS_Pos)              /*!< 0x00040000 */

+#define FDCAN_TTILS_CERS          FDCAN_TTILS_CERS_Msk                         /*!<Configuration Error Interrupt Line                */

+

+/*****************  Bit definition for FDCAN_TTOST register  ********************/

+#define FDCAN_TTOST_EL_Pos        (0U)

+#define FDCAN_TTOST_EL_Msk        (0x3UL << FDCAN_TTOST_EL_Pos)                /*!< 0x00000003 */

+#define FDCAN_TTOST_EL            FDCAN_TTOST_EL_Msk                           /*!<Error Level                              */

+#define FDCAN_TTOST_MS_Pos        (2U)

+#define FDCAN_TTOST_MS_Msk        (0x3UL << FDCAN_TTOST_MS_Pos)                /*!< 0x0000000C */

+#define FDCAN_TTOST_MS            FDCAN_TTOST_MS_Msk                           /*!<Master State                             */

+#define FDCAN_TTOST_SYS_Pos       (4U)

+#define FDCAN_TTOST_SYS_Msk       (0x3UL << FDCAN_TTOST_SYS_Pos)               /*!< 0x00000030 */

+#define FDCAN_TTOST_SYS           FDCAN_TTOST_SYS_Msk                          /*!<Synchronization State                    */

+#define FDCAN_TTOST_QGTP_Pos      (6U)

+#define FDCAN_TTOST_QGTP_Msk      (0x1UL << FDCAN_TTOST_QGTP_Pos)              /*!< 0x00000040 */

+#define FDCAN_TTOST_QGTP          FDCAN_TTOST_QGTP_Msk                         /*!<Quality of Global Time Phase             */

+#define FDCAN_TTOST_QCS_Pos       (7U)

+#define FDCAN_TTOST_QCS_Msk       (0x1UL << FDCAN_TTOST_QCS_Pos)               /*!< 0x00000080 */

+#define FDCAN_TTOST_QCS           FDCAN_TTOST_QCS_Msk                          /*!<Quality of Clock Speed                   */

+#define FDCAN_TTOST_RTO_Pos       (8U)

+#define FDCAN_TTOST_RTO_Msk       (0xFFUL << FDCAN_TTOST_RTO_Pos)              /*!< 0x0000FF00 */

+#define FDCAN_TTOST_RTO           FDCAN_TTOST_RTO_Msk                          /*!<Reference Trigger Offset                 */

+#define FDCAN_TTOST_WGTD_Pos      (22U)

+#define FDCAN_TTOST_WGTD_Msk      (0x1UL << FDCAN_TTOST_WGTD_Pos)              /*!< 0x00400000 */

+#define FDCAN_TTOST_WGTD          FDCAN_TTOST_WGTD_Msk                         /*!<Wait for Global Time Discontinuity       */

+#define FDCAN_TTOST_GFI_Pos       (23U)

+#define FDCAN_TTOST_GFI_Msk       (0x1UL << FDCAN_TTOST_GFI_Pos)               /*!< 0x00800000 */

+#define FDCAN_TTOST_GFI           FDCAN_TTOST_GFI_Msk                          /*!<Gap Finished Indicator                   */

+#define FDCAN_TTOST_TMP_Pos       (24U)

+#define FDCAN_TTOST_TMP_Msk       (0x7UL << FDCAN_TTOST_TMP_Pos)               /*!< 0x07000000 */

+#define FDCAN_TTOST_TMP           FDCAN_TTOST_TMP_Msk                          /*!<Time Master Priority                     */

+#define FDCAN_TTOST_GSI_Pos       (27U)

+#define FDCAN_TTOST_GSI_Msk       (0x1UL << FDCAN_TTOST_GSI_Pos)               /*!< 0x08000000 */

+#define FDCAN_TTOST_GSI           FDCAN_TTOST_GSI_Msk                          /*!<Gap Started Indicator                    */

+#define FDCAN_TTOST_WFE_Pos       (28U)

+#define FDCAN_TTOST_WFE_Msk       (0x1UL << FDCAN_TTOST_WFE_Pos)               /*!< 0x10000000 */

+#define FDCAN_TTOST_WFE           FDCAN_TTOST_WFE_Msk                          /*!<Wait for Event                           */

+#define FDCAN_TTOST_AWE_Pos       (29U)

+#define FDCAN_TTOST_AWE_Msk       (0x1UL << FDCAN_TTOST_AWE_Pos)               /*!< 0x20000000 */

+#define FDCAN_TTOST_AWE           FDCAN_TTOST_AWE_Msk                          /*!<Application Watchdog Event               */

+#define FDCAN_TTOST_WECS_Pos      (30U)

+#define FDCAN_TTOST_WECS_Msk      (0x1UL << FDCAN_TTOST_WECS_Pos)              /*!< 0x40000000 */

+#define FDCAN_TTOST_WECS          FDCAN_TTOST_WECS_Msk                         /*!<Wait for External Clock Synchronization  */

+#define FDCAN_TTOST_SPL_Pos       (31U)

+#define FDCAN_TTOST_SPL_Msk       (0x1UL << FDCAN_TTOST_SPL_Pos)               /*!< 0x80000000 */

+#define FDCAN_TTOST_SPL           FDCAN_TTOST_SPL_Msk                          /*!<Schedule Phase Lock                      */

+

+/*****************  Bit definition for FDCAN_TURNA register  ********************/

+#define FDCAN_TURNA_NAV_Pos       (0U)

+#define FDCAN_TURNA_NAV_Msk       (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)           /*!< 0x0003FFFF */

+#define FDCAN_TURNA_NAV           FDCAN_TURNA_NAV_Msk                          /*!<Numerator Actual Value                   */

+

+/*****************  Bit definition for FDCAN_TTLGT register  ********************/

+#define FDCAN_TTLGT_LT_Pos        (0U)

+#define FDCAN_TTLGT_LT_Msk        (0xFFFFUL << FDCAN_TTLGT_LT_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTLGT_LT            FDCAN_TTLGT_LT_Msk                           /*!<Local Time                               */

+#define FDCAN_TTLGT_GT_Pos        (16U)

+#define FDCAN_TTLGT_GT_Msk        (0xFFFFUL << FDCAN_TTLGT_GT_Pos)             /*!< 0xFFFF0000 */

+#define FDCAN_TTLGT_GT            FDCAN_TTLGT_GT_Msk                           /*!<Global Time                              */

+

+/*****************  Bit definition for FDCAN_TTCTC register  ********************/

+#define FDCAN_TTCTC_CT_Pos        (0U)

+#define FDCAN_TTCTC_CT_Msk        (0xFFFFUL << FDCAN_TTCTC_CT_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTCTC_CT            FDCAN_TTCTC_CT_Msk                           /*!<Cycle Time                               */

+#define FDCAN_TTCTC_CC_Pos        (16U)

+#define FDCAN_TTCTC_CC_Msk        (0x3FUL << FDCAN_TTCTC_CC_Pos)               /*!< 0x003F0000 */

+#define FDCAN_TTCTC_CC            FDCAN_TTCTC_CC_Msk                           /*!<Cycle Count                              */

+

+/*****************  Bit definition for FDCAN_TTCPT register  ********************/

+#define FDCAN_TTCPT_CCV_Pos       (0U)

+#define FDCAN_TTCPT_CCV_Msk       (0x3FUL << FDCAN_TTCPT_CCV_Pos)              /*!< 0x0000003F */

+#define FDCAN_TTCPT_CCV           FDCAN_TTCPT_CCV_Msk                          /*!<Cycle Count Value                        */

+#define FDCAN_TTCPT_SWV_Pos       (16U)

+#define FDCAN_TTCPT_SWV_Msk       (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)            /*!< 0xFFFF0000 */

+#define FDCAN_TTCPT_SWV           FDCAN_TTCPT_SWV_Msk                          /*!<Stop Watch Value                         */

+

+/*****************  Bit definition for FDCAN_TTCSM register  ********************/

+#define FDCAN_TTCSM_CSM_Pos       (0U)

+#define FDCAN_TTCSM_CSM_Msk       (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)            /*!< 0x0000FFFF */

+#define FDCAN_TTCSM_CSM           FDCAN_TTCSM_CSM_Msk                          /*!<Cycle Sync Mark                          */

+

+/*****************  Bit definition for FDCAN_TTTS register  *********************/

+#define FDCAN_TTTS_SWTSEL_Pos     (0U)

+#define FDCAN_TTTS_SWTSEL_Msk     (0x3UL << FDCAN_TTTS_SWTSEL_Pos)             /*!< 0x00000003 */

+#define FDCAN_TTTS_SWTSEL         FDCAN_TTTS_SWTSEL_Msk                        /*!<Stop watch trigger input selection       */

+#define FDCAN_TTTS_EVTSEL_Pos     (4U)

+#define FDCAN_TTTS_EVTSEL_Msk     (0x3UL << FDCAN_TTTS_EVTSEL_Pos)             /*!< 0x00000030 */

+#define FDCAN_TTTS_EVTSEL         FDCAN_TTTS_EVTSEL_Msk                        /*!<Event trigger input selection            */

+

+/********************************************************************************/

+/*                                                                              */

+/*                      FDCANCCU (Clock Calibration unit)                       */

+/*                                                                              */

+/********************************************************************************/

+

+/*****************  Bit definition for FDCANCCU_CREL register  ******************/

+#define FDCANCCU_CREL_DAY_Pos        (0U)

+#define FDCANCCU_CREL_DAY_Msk        (0xFFUL << FDCANCCU_CREL_DAY_Pos)         /*!< 0x000000FF */

+#define FDCANCCU_CREL_DAY            FDCANCCU_CREL_DAY_Msk                     /*!<Timestamp Day                           */

+#define FDCANCCU_CREL_MON_Pos        (8U)

+#define FDCANCCU_CREL_MON_Msk        (0xFFUL << FDCANCCU_CREL_MON_Pos)         /*!< 0x0000FF00 */

+#define FDCANCCU_CREL_MON            FDCANCCU_CREL_MON_Msk                     /*!<Timestamp Month                         */

+#define FDCANCCU_CREL_YEAR_Pos       (16U)

+#define FDCANCCU_CREL_YEAR_Msk       (0xFUL << FDCANCCU_CREL_YEAR_Pos)         /*!< 0x000F0000 */

+#define FDCANCCU_CREL_YEAR           FDCANCCU_CREL_YEAR_Msk                    /*!<Timestamp Year                          */

+#define FDCANCCU_CREL_SUBSTEP_Pos    (20U)

+#define FDCANCCU_CREL_SUBSTEP_Msk    (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)      /*!< 0x00F00000 */

+#define FDCANCCU_CREL_SUBSTEP        FDCANCCU_CREL_SUBSTEP_Msk                 /*!<Sub-step of Core release                */

+#define FDCANCCU_CREL_STEP_Pos       (24U)

+#define FDCANCCU_CREL_STEP_Msk       (0xFUL << FDCANCCU_CREL_STEP_Pos)         /*!< 0x0F000000 */

+#define FDCANCCU_CREL_STEP           FDCANCCU_CREL_STEP_Msk                    /*!<Step of Core release                    */

+#define FDCANCCU_CREL_REL_Pos        (28U)

+#define FDCANCCU_CREL_REL_Msk        (0xFUL << FDCANCCU_CREL_REL_Pos)          /*!< 0xF0000000 */

+#define FDCANCCU_CREL_REL            FDCANCCU_CREL_REL_Msk                     /*!<Core release                            */

+

+/*****************  Bit definition for FDCANCCU_CCFG register  ******************/

+#define FDCANCCU_CCFG_TQBT_Pos       (0U)

+#define FDCANCCU_CCFG_TQBT_Msk       (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)        /*!< 0x0000001F */

+#define FDCANCCU_CCFG_TQBT           FDCANCCU_CCFG_TQBT_Msk                    /*!<Time Quanta per Bit Time                */

+#define FDCANCCU_CCFG_BCC_Pos        (6U)

+#define FDCANCCU_CCFG_BCC_Msk        (0x1UL << FDCANCCU_CCFG_BCC_Pos)          /*!< 0x00000040 */

+#define FDCANCCU_CCFG_BCC            FDCANCCU_CCFG_BCC_Msk                     /*!<Bypass Clock Calibration                */

+#define FDCANCCU_CCFG_CFL_Pos        (7U)

+#define FDCANCCU_CCFG_CFL_Msk        (0x1UL << FDCANCCU_CCFG_CFL_Pos)          /*!< 0x00000080 */

+#define FDCANCCU_CCFG_CFL            FDCANCCU_CCFG_CFL_Msk                     /*!<Calibration Field Length                */

+#define FDCANCCU_CCFG_OCPM_Pos       (8U)

+#define FDCANCCU_CCFG_OCPM_Msk       (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)        /*!< 0x0000FF00 */

+#define FDCANCCU_CCFG_OCPM           FDCANCCU_CCFG_OCPM_Msk                    /*!<Oscillator Clock Periods Minimum        */

+#define FDCANCCU_CCFG_CDIV_Pos       (16U)

+#define FDCANCCU_CCFG_CDIV_Msk       (0xFUL << FDCANCCU_CCFG_CDIV_Pos)         /*!< 0x000F0000 */

+#define FDCANCCU_CCFG_CDIV           FDCANCCU_CCFG_CDIV_Msk                    /*!<Clock Divider                           */

+#define FDCANCCU_CCFG_SWR_Pos        (31U)

+#define FDCANCCU_CCFG_SWR_Msk        (0x1UL << FDCANCCU_CCFG_SWR_Pos)          /*!< 0x80000000 */

+#define FDCANCCU_CCFG_SWR            FDCANCCU_CCFG_SWR_Msk                     /*!<Software Reset                          */

+

+/*****************  Bit definition for FDCANCCU_CSTAT register  *****************/

+#define FDCANCCU_CSTAT_OCPC_Pos      (0U)

+#define FDCANCCU_CSTAT_OCPC_Msk      (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)    /*!< 0x0003FFFF */

+#define FDCANCCU_CSTAT_OCPC          FDCANCCU_CSTAT_OCPC_Msk                   /*!<Oscillator Clock Period Counter        */

+#define FDCANCCU_CSTAT_TQC_Pos       (18U)

+#define FDCANCCU_CSTAT_TQC_Msk       (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)       /*!< 0x1FFC0000 */

+#define FDCANCCU_CSTAT_TQC           FDCANCCU_CSTAT_TQC_Msk                    /*!<Time Quanta Counter                    */

+#define FDCANCCU_CSTAT_CALS_Pos      (30U)

+#define FDCANCCU_CSTAT_CALS_Msk      (0x3UL << FDCANCCU_CSTAT_CALS_Pos)        /*!< 0xC0000000 */

+#define FDCANCCU_CSTAT_CALS          FDCANCCU_CSTAT_CALS_Msk                   /*!<Calibration State                      */

+

+/******************  Bit definition for FDCANCCU_CWD register  ******************/

+#define FDCANCCU_CWD_WDC_Pos         (0U)

+#define FDCANCCU_CWD_WDC_Msk         (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)        /*!< 0x0000FFFF */

+#define FDCANCCU_CWD_WDC             FDCANCCU_CWD_WDC_Msk                      /*!<Watchdog Configuration                 */

+#define FDCANCCU_CWD_WDV_Pos         (16U)

+#define FDCANCCU_CWD_WDV_Msk         (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)        /*!< 0xFFFF0000 */

+#define FDCANCCU_CWD_WDV             FDCANCCU_CWD_WDV_Msk                      /*!<Watchdog Value                         */

+

+/******************  Bit definition for FDCANCCU_IR register  *******************/

+#define FDCANCCU_IR_CWE_Pos          (0U)

+#define FDCANCCU_IR_CWE_Msk          (0x1UL << FDCANCCU_IR_CWE_Pos)            /*!< 0x00000001 */

+#define FDCANCCU_IR_CWE              FDCANCCU_IR_CWE_Msk                       /*!<Calibration Watchdog Event             */

+#define FDCANCCU_IR_CSC_Pos          (1U)

+#define FDCANCCU_IR_CSC_Msk          (0x1UL << FDCANCCU_IR_CSC_Pos)            /*!< 0x00000002 */

+#define FDCANCCU_IR_CSC              FDCANCCU_IR_CSC_Msk                       /*!<Calibration State Changed              */

+

+/******************  Bit definition for FDCANCCU_IE register  *******************/

+#define FDCANCCU_IE_CWEE_Pos         (0U)

+#define FDCANCCU_IE_CWEE_Msk         (0x1UL << FDCANCCU_IE_CWEE_Pos)           /*!< 0x00000001 */

+#define FDCANCCU_IE_CWEE             FDCANCCU_IE_CWEE_Msk                      /*!<Calibration Watchdog Event Enable      */

+#define FDCANCCU_IE_CSCE_Pos         (1U)

+#define FDCANCCU_IE_CSCE_Msk         (0x1UL << FDCANCCU_IE_CSCE_Pos)           /*!< 0x00000002 */

+#define FDCANCCU_IE_CSCE             FDCANCCU_IE_CSCE_Msk                      /*!<Calibration State Changed Enable       */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          HDMI-CEC (CEC)                                    */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for CEC_CR register  *********************/

+#define CEC_CR_CECEN_Pos         (0U)

+#define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                   /*!< 0x00000001 */

+#define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                                */

+#define CEC_CR_TXSOM_Pos         (1U)

+#define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                   /*!< 0x00000002 */

+#define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message                   */

+#define CEC_CR_TXEOM_Pos         (2U)

+#define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                   /*!< 0x00000004 */

+#define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message                     */

+

+/*******************  Bit definition for CEC_CFGR register  *******************/

+#define CEC_CFGR_SFT_Pos         (0U)

+#define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                   /*!< 0x00000007 */

+#define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time                      */

+#define CEC_CFGR_RXTOL_Pos       (3U)

+#define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                 /*!< 0x00000008 */

+#define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                             */

+#define CEC_CFGR_BRESTP_Pos      (4U)

+#define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                /*!< 0x00000010 */

+#define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                               */

+#define CEC_CFGR_BREGEN_Pos      (5U)

+#define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                /*!< 0x00000020 */

+#define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation           */

+#define CEC_CFGR_LBPEGEN_Pos     (6U)

+#define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)               /*!< 0x00000040 */

+#define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error generation      */

+#define CEC_CFGR_SFTOPT_Pos      (8U)

+#define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                /*!< 0x00000100 */

+#define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional             */

+#define CEC_CFGR_BRDNOGEN_Pos    (7U)

+#define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)              /*!< 0x00000080 */

+#define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No error generation         */

+#define CEC_CFGR_OAR_Pos         (16U)

+#define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                /*!< 0x7FFF0000 */

+#define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                           */

+#define CEC_CFGR_LSTN_Pos        (31U)

+#define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                  /*!< 0x80000000 */

+#define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                           */

+

+/*******************  Bit definition for CEC_TXDR register  *******************/

+#define CEC_TXDR_TXD_Pos         (0U)

+#define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                  /*!< 0x000000FF */

+#define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                               */

+

+/*******************  Bit definition for CEC_RXDR register  *******************/

+#define CEC_RXDR_RXD_Pos         (0U)

+#define CEC_RXDR_RXD_Msk         (0xFFUL << CEC_RXDR_RXD_Pos)                  /*!< 0x000000FF */

+#define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                              /*!< CEC Rx Data                               */

+

+/*******************  Bit definition for CEC_ISR register  ********************/

+#define CEC_ISR_RXBR_Pos         (0U)

+#define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                   /*!< 0x00000001 */

+#define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                      */

+#define CEC_ISR_RXEND_Pos        (1U)

+#define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                  /*!< 0x00000002 */

+#define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                      */

+#define CEC_ISR_RXOVR_Pos        (2U)

+#define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                  /*!< 0x00000004 */

+#define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                            */

+#define CEC_ISR_BRE_Pos          (3U)

+#define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                    /*!< 0x00000008 */

+#define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                   */

+#define CEC_ISR_SBPE_Pos         (4U)

+#define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                   /*!< 0x00000010 */

+#define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error             */

+#define CEC_ISR_LBPE_Pos         (5U)

+#define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                   /*!< 0x00000020 */

+#define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error              */

+#define CEC_ISR_RXACKE_Pos       (6U)

+#define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                 /*!< 0x00000040 */

+#define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge                */

+#define CEC_ISR_ARBLST_Pos       (7U)

+#define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                 /*!< 0x00000080 */

+#define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                      */

+#define CEC_ISR_TXBR_Pos         (8U)

+#define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                   /*!< 0x00000100 */

+#define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                       */

+#define CEC_ISR_TXEND_Pos        (9U)

+#define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                  /*!< 0x00000200 */

+#define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                   */

+#define CEC_ISR_TXUDR_Pos        (10U)

+#define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                  /*!< 0x00000400 */

+#define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                    */

+#define CEC_ISR_TXERR_Pos        (11U)

+#define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                  /*!< 0x00000800 */

+#define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                              */

+#define CEC_ISR_TXACKE_Pos       (12U)

+#define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                 /*!< 0x00001000 */

+#define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge                */

+

+/*******************  Bit definition for CEC_IER register  ********************/

+#define CEC_IER_RXBRIE_Pos       (0U)

+#define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                 /*!< 0x00000001 */

+#define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable            */

+#define CEC_IER_RXENDIE_Pos      (1U)

+#define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                /*!< 0x00000002 */

+#define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable            */

+#define CEC_IER_RXOVRIE_Pos      (2U)

+#define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                /*!< 0x00000004 */

+#define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable                  */

+#define CEC_IER_BREIE_Pos        (3U)

+#define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                  /*!< 0x00000008 */

+#define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable         */

+#define CEC_IER_SBPEIE_Pos       (4U)

+#define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                 /*!< 0x00000010 */

+#define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable   */

+#define CEC_IER_LBPEIE_Pos       (5U)

+#define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                 /*!< 0x00000020 */

+#define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable    */

+#define CEC_IER_RXACKEIE_Pos     (6U)

+#define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)               /*!< 0x00000040 */

+#define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable      */

+#define CEC_IER_ARBLSTIE_Pos     (7U)

+#define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)               /*!< 0x00000080 */

+#define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable            */

+#define CEC_IER_TXBRIE_Pos       (8U)

+#define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                 /*!< 0x00000100 */

+#define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable            */

+#define CEC_IER_TXENDIE_Pos      (9U)

+#define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                /*!< 0x00000200 */

+#define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable         */

+#define CEC_IER_TXUDRIE_Pos      (10U)

+#define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                /*!< 0x00000400 */

+#define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable          */

+#define CEC_IER_TXERRIE_Pos      (11U)

+#define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                /*!< 0x00000800 */

+#define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                    */

+#define CEC_IER_TXACKEIE_Pos     (12U)

+#define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)               /*!< 0x00001000 */

+#define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable      */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          CRC calculation unit                              */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for CRC_DR register  *********************/

+#define CRC_DR_DR_Pos            (0U)

+#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */

+#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */

+

+/*******************  Bit definition for CRC_IDR register  ********************/

+#define CRC_IDR_IDR_Pos          (0U)

+#define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */

+#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */

+

+/********************  Bit definition for CRC_CR register  ********************/

+#define CRC_CR_RESET_Pos         (0U)

+#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */

+#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */

+#define CRC_CR_POLYSIZE_Pos      (3U)

+#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */

+#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */

+#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */

+#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */

+#define CRC_CR_REV_IN_Pos        (5U)

+#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */

+#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */

+#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */

+#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */

+#define CRC_CR_REV_OUT_Pos       (7U)

+#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */

+#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */

+

+/*******************  Bit definition for CRC_INIT register  *******************/

+#define CRC_INIT_INIT_Pos        (0U)

+#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */

+#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */

+

+/*******************  Bit definition for CRC_POL register  ********************/

+#define CRC_POL_POL_Pos          (0U)

+#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */

+#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          CRS Clock Recovery System                         */

+/******************************************************************************/

+

+/*******************  Bit definition for CRS_CR register  *********************/

+#define CRS_CR_SYNCOKIE_Pos       (0U)

+#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */

+#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */

+#define CRS_CR_SYNCWARNIE_Pos     (1U)

+#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */

+#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */

+#define CRS_CR_ERRIE_Pos          (2U)

+#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */

+#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */

+#define CRS_CR_ESYNCIE_Pos        (3U)

+#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */

+#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */

+#define CRS_CR_CEN_Pos            (5U)

+#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */

+#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */

+#define CRS_CR_AUTOTRIMEN_Pos     (6U)

+#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */

+#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */

+#define CRS_CR_SWSYNC_Pos         (7U)

+#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */

+#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */

+#define CRS_CR_TRIM_Pos           (8U)

+#define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00003F00 */

+#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */

+

+/*******************  Bit definition for CRS_CFGR register  *********************/

+#define CRS_CFGR_RELOAD_Pos       (0U)

+#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */

+#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */

+#define CRS_CFGR_FELIM_Pos        (16U)

+#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */

+#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */

+

+#define CRS_CFGR_SYNCDIV_Pos      (24U)

+#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */

+#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */

+#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */

+#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */

+#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */

+

+#define CRS_CFGR_SYNCSRC_Pos      (28U)

+#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */

+#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */

+#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */

+#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */

+

+#define CRS_CFGR_SYNCPOL_Pos      (31U)

+#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */

+#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */

+

+/*******************  Bit definition for CRS_ISR register  *********************/

+#define CRS_ISR_SYNCOKF_Pos       (0U)

+#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */

+#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */

+#define CRS_ISR_SYNCWARNF_Pos     (1U)

+#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */

+#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */

+#define CRS_ISR_ERRF_Pos          (2U)

+#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */

+#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */

+#define CRS_ISR_ESYNCF_Pos        (3U)

+#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */

+#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */

+#define CRS_ISR_SYNCERR_Pos       (8U)

+#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */

+#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */

+#define CRS_ISR_SYNCMISS_Pos      (9U)

+#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */

+#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */

+#define CRS_ISR_TRIMOVF_Pos       (10U)

+#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */

+#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */

+#define CRS_ISR_FEDIR_Pos         (15U)

+#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */

+#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */

+#define CRS_ISR_FECAP_Pos         (16U)

+#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */

+#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */

+

+/*******************  Bit definition for CRS_ICR register  *********************/

+#define CRS_ICR_SYNCOKC_Pos       (0U)

+#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */

+#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */

+#define CRS_ICR_SYNCWARNC_Pos     (1U)

+#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */

+#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */

+#define CRS_ICR_ERRC_Pos          (2U)

+#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */

+#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */

+#define CRS_ICR_ESYNCC_Pos        (3U)

+#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */

+#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      Digital to Analog Converter                           */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for DAC_CR register  ********************/

+#define DAC_CR_EN1_Pos              (0U)

+#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */

+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */

+#define DAC_CR_TEN1_Pos             (1U)

+#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */

+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */

+

+#define DAC_CR_TSEL1_Pos            (2U)

+#define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */

+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */

+#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000004 */

+#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */

+#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */

+#define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */

+

+

+#define DAC_CR_WAVE1_Pos            (6U)

+#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */

+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */

+#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */

+#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */

+

+#define DAC_CR_MAMP1_Pos            (8U)

+#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */

+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */

+#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */

+#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */

+#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */

+#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */

+

+#define DAC_CR_DMAEN1_Pos           (12U)

+#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */

+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */

+#define DAC_CR_DMAUDRIE1_Pos        (13U)

+#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */

+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/

+#define DAC_CR_CEN1_Pos             (14U)

+#define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */

+#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/

+

+#define DAC_CR_EN2_Pos              (16U)

+#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */

+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */

+#define DAC_CR_TEN2_Pos             (17U)

+#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */

+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */

+

+#define DAC_CR_TSEL2_Pos            (18U)

+#define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */

+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */

+#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00040000 */

+#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */

+#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */

+#define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */

+

+

+#define DAC_CR_WAVE2_Pos            (22U)

+#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */

+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */

+#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */

+#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */

+

+#define DAC_CR_MAMP2_Pos            (24U)

+#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */

+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */

+#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */

+#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */

+#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */

+#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */

+

+#define DAC_CR_DMAEN2_Pos           (28U)

+#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */

+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */

+#define DAC_CR_DMAUDRIE2_Pos        (29U)

+#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */

+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/

+#define DAC_CR_CEN2_Pos             (30U)

+#define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */

+#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/

+

+/*****************  Bit definition for DAC_SWTRIGR register  ******************/

+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)

+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */

+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */

+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)

+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */

+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */

+

+/*****************  Bit definition for DAC_DHR12R1 register  ******************/

+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)

+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12L1 register  ******************/

+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)

+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8R1 register  ******************/

+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)

+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12R2 register  ******************/

+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)

+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12L2 register  ******************/

+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)

+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8R2 register  ******************/

+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)

+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12RD register  ******************/

+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)

+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */

+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)

+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */

+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12LD register  ******************/

+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)

+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */

+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)

+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */

+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8RD register  ******************/

+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)

+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */

+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)

+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */

+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */

+

+/*******************  Bit definition for DAC_DOR1 register  *******************/

+#define DAC_DOR1_DACC1DOR_Pos       (0U)

+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */

+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */

+

+/*******************  Bit definition for DAC_DOR2 register  *******************/

+#define DAC_DOR2_DACC2DOR_Pos       (0U)

+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */

+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */

+

+/********************  Bit definition for DAC_SR register  ********************/

+#define DAC_SR_DMAUDR1_Pos          (13U)

+#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */

+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */

+#define DAC_SR_CAL_FLAG1_Pos        (14U)

+#define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */

+#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */

+#define DAC_SR_BWST1_Pos            (15U)

+#define DAC_SR_BWST1_Msk            (0x4001UL << DAC_SR_BWST1_Pos)             /*!< 0x20008000 */

+#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */

+

+#define DAC_SR_DMAUDR2_Pos          (29U)

+#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */

+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */

+#define DAC_SR_CAL_FLAG2_Pos        (30U)

+#define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */

+#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */

+#define DAC_SR_BWST2_Pos            (31U)

+#define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */

+#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */

+

+/*******************  Bit definition for DAC_CCR register  ********************/

+#define DAC_CCR_OTRIM1_Pos          (0U)

+#define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */

+#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */

+#define DAC_CCR_OTRIM2_Pos          (16U)

+#define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */

+#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */

+

+/*******************  Bit definition for DAC_MCR register  *******************/

+#define DAC_MCR_MODE1_Pos           (0U)

+#define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */

+#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */

+#define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */

+#define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */

+#define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */

+

+#define DAC_MCR_MODE2_Pos           (16U)

+#define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */

+#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */

+#define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */

+#define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */

+#define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */

+

+/******************  Bit definition for DAC_SHSR1 register  ******************/

+#define DAC_SHSR1_TSAMPLE1_Pos      (0U)

+#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */

+#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */

+

+/******************  Bit definition for DAC_SHSR2 register  ******************/

+#define DAC_SHSR2_TSAMPLE2_Pos      (0U)

+#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */

+#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */

+

+/******************  Bit definition for DAC_SHHR register  ******************/

+#define DAC_SHHR_THOLD1_Pos         (0U)

+#define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */

+#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */

+#define DAC_SHHR_THOLD2_Pos         (16U)

+#define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */

+#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */

+

+/******************  Bit definition for DAC_SHRR register  ******************/

+#define DAC_SHRR_TREFRESH1_Pos      (0U)

+#define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */

+#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */

+#define DAC_SHRR_TREFRESH2_Pos      (16U)

+#define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */

+#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    DCMI                                    */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DCMI_CR register  ******************/

+#define DCMI_CR_CAPTURE_Pos        (0U)

+#define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)              /*!< 0x00000001 */

+#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk

+#define DCMI_CR_CM_Pos             (1U)

+#define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                   /*!< 0x00000002 */

+#define DCMI_CR_CM                 DCMI_CR_CM_Msk

+#define DCMI_CR_CROP_Pos           (2U)

+#define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                 /*!< 0x00000004 */

+#define DCMI_CR_CROP               DCMI_CR_CROP_Msk

+#define DCMI_CR_JPEG_Pos           (3U)

+#define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                 /*!< 0x00000008 */

+#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk

+#define DCMI_CR_ESS_Pos            (4U)

+#define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                  /*!< 0x00000010 */

+#define DCMI_CR_ESS                DCMI_CR_ESS_Msk

+#define DCMI_CR_PCKPOL_Pos         (5U)

+#define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)               /*!< 0x00000020 */

+#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk

+#define DCMI_CR_HSPOL_Pos          (6U)

+#define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                /*!< 0x00000040 */

+#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk

+#define DCMI_CR_VSPOL_Pos          (7U)

+#define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */

+#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk

+#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)

+#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)

+#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)

+#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)

+#define DCMI_CR_CRE_Pos            (12U)

+#define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */

+#define DCMI_CR_CRE                DCMI_CR_CRE_Msk

+#define DCMI_CR_ENABLE_Pos         (14U)

+#define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)               /*!< 0x00004000 */

+#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk

+#define DCMI_CR_BSM_Pos            (16U)

+#define DCMI_CR_BSM_Msk            (0x3UL << DCMI_CR_BSM_Pos)                  /*!< 0x00030000 */

+#define DCMI_CR_BSM                DCMI_CR_BSM_Msk

+#define DCMI_CR_BSM_0              (0x1UL << DCMI_CR_BSM_Pos)                   /*!< 0x00010000 */

+#define DCMI_CR_BSM_1              (0x2UL << DCMI_CR_BSM_Pos)                   /*!< 0x00020000 */

+#define DCMI_CR_OEBS_Pos           (18U)

+#define DCMI_CR_OEBS_Msk           (0x1UL << DCMI_CR_OEBS_Pos)                 /*!< 0x00040000 */

+#define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk

+#define DCMI_CR_LSM_Pos            (19U)

+#define DCMI_CR_LSM_Msk            (0x1UL << DCMI_CR_LSM_Pos)                  /*!< 0x00080000 */

+#define DCMI_CR_LSM                DCMI_CR_LSM_Msk

+#define DCMI_CR_OELS_Pos           (20U)

+#define DCMI_CR_OELS_Msk           (0x1UL << DCMI_CR_OELS_Pos)                 /*!< 0x00100000 */

+#define DCMI_CR_OELS               DCMI_CR_OELS_Msk

+

+/********************  Bits definition for DCMI_SR register  ******************/

+#define DCMI_SR_HSYNC_Pos          (0U)

+#define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                /*!< 0x00000001 */

+#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk

+#define DCMI_SR_VSYNC_Pos          (1U)

+#define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                /*!< 0x00000002 */

+#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk

+#define DCMI_SR_FNE_Pos            (2U)

+#define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                  /*!< 0x00000004 */

+#define DCMI_SR_FNE                DCMI_SR_FNE_Msk

+

+/********************  Bits definition for DCMI_RIS register   ****************/

+#define DCMI_RIS_FRAME_RIS_Pos     (0U)

+#define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)           /*!< 0x00000001 */

+#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk

+#define DCMI_RIS_OVR_RIS_Pos       (1U)

+#define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)             /*!< 0x00000002 */

+#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk

+#define DCMI_RIS_ERR_RIS_Pos       (2U)

+#define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)             /*!< 0x00000004 */

+#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk

+#define DCMI_RIS_VSYNC_RIS_Pos     (3U)

+#define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)           /*!< 0x00000008 */

+#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk

+#define DCMI_RIS_LINE_RIS_Pos      (4U)

+#define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)            /*!< 0x00000010 */

+#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk

+

+/********************  Bits definition for DCMI_IER register  *****************/

+#define DCMI_IER_FRAME_IE_Pos      (0U)

+#define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)            /*!< 0x00000001 */

+#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk

+#define DCMI_IER_OVR_IE_Pos        (1U)

+#define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)              /*!< 0x00000002 */

+#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk

+#define DCMI_IER_ERR_IE_Pos        (2U)

+#define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)              /*!< 0x00000004 */

+#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk

+#define DCMI_IER_VSYNC_IE_Pos      (3U)

+#define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)            /*!< 0x00000008 */

+#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk

+#define DCMI_IER_LINE_IE_Pos       (4U)

+#define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)             /*!< 0x00000010 */

+#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk

+

+

+/********************  Bits definition for DCMI_MIS register  *****************/

+#define DCMI_MIS_FRAME_MIS_Pos     (0U)

+#define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)           /*!< 0x00000001 */

+#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk

+#define DCMI_MIS_OVR_MIS_Pos       (1U)

+#define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)             /*!< 0x00000002 */

+#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk

+#define DCMI_MIS_ERR_MIS_Pos       (2U)

+#define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)             /*!< 0x00000004 */

+#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk

+#define DCMI_MIS_VSYNC_MIS_Pos     (3U)

+#define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)           /*!< 0x00000008 */

+#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk

+#define DCMI_MIS_LINE_MIS_Pos      (4U)

+#define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)            /*!< 0x00000010 */

+#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk

+

+

+/********************  Bits definition for DCMI_ICR register  *****************/

+#define DCMI_ICR_FRAME_ISC_Pos     (0U)

+#define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)           /*!< 0x00000001 */

+#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk

+#define DCMI_ICR_OVR_ISC_Pos       (1U)

+#define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)             /*!< 0x00000002 */

+#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk

+#define DCMI_ICR_ERR_ISC_Pos       (2U)

+#define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)             /*!< 0x00000004 */

+#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk

+#define DCMI_ICR_VSYNC_ISC_Pos     (3U)

+#define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)           /*!< 0x00000008 */

+#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk

+#define DCMI_ICR_LINE_ISC_Pos      (4U)

+#define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)            /*!< 0x00000010 */

+#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk

+

+

+/********************  Bits definition for DCMI_ESCR register  ******************/

+#define DCMI_ESCR_FSC_Pos          (0U)

+#define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)               /*!< 0x000000FF */

+#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk

+#define DCMI_ESCR_LSC_Pos          (8U)

+#define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)               /*!< 0x0000FF00 */

+#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk

+#define DCMI_ESCR_LEC_Pos          (16U)

+#define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)               /*!< 0x00FF0000 */

+#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk

+#define DCMI_ESCR_FEC_Pos          (24U)

+#define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)               /*!< 0xFF000000 */

+#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk

+

+/********************  Bits definition for DCMI_ESUR register  ******************/

+#define DCMI_ESUR_FSU_Pos          (0U)

+#define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)               /*!< 0x000000FF */

+#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk

+#define DCMI_ESUR_LSU_Pos          (8U)

+#define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)               /*!< 0x0000FF00 */

+#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk

+#define DCMI_ESUR_LEU_Pos          (16U)

+#define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)               /*!< 0x00FF0000 */

+#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk

+#define DCMI_ESUR_FEU_Pos          (24U)

+#define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)               /*!< 0xFF000000 */

+#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk

+

+/********************  Bits definition for DCMI_CWSTRT register  ******************/

+#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)

+#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)       /*!< 0x00003FFF */

+#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk

+#define DCMI_CWSTRT_VST_Pos        (16U)

+#define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)           /*!< 0x1FFF0000 */

+#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk

+

+/********************  Bits definition for DCMI_CWSIZE register  ******************/

+#define DCMI_CWSIZE_CAPCNT_Pos     (0U)

+#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)        /*!< 0x00003FFF */

+#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk

+#define DCMI_CWSIZE_VLINE_Pos      (16U)

+#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)         /*!< 0x3FFF0000 */

+#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk

+

+/********************  Bits definition for DCMI_DR register  ******************/

+#define DCMI_DR_BYTE0_Pos          (0U)

+#define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)               /*!< 0x000000FF */

+#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk

+#define DCMI_DR_BYTE1_Pos          (8U)

+#define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)               /*!< 0x0000FF00 */

+#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk

+#define DCMI_DR_BYTE2_Pos          (16U)

+#define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)               /*!< 0x00FF0000 */

+#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk

+#define DCMI_DR_BYTE3_Pos          (24U)

+#define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)               /*!< 0xFF000000 */

+#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                 Digital Filter for Sigma Delta Modulators                  */

+/*                                                                            */

+/******************************************************************************/

+

+/****************   DFSDM channel configuration registers  ********************/

+

+/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/

+#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)

+#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)   /*!< 0x80000000 */

+#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */

+#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)

+#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)  /*!< 0x40000000 */

+#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */

+#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)

+#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */

+#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */

+#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)

+#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x0000C000 */

+#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */

+#define DFSDM_CHCFGR1_DATPACK_1         (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */

+#define DFSDM_CHCFGR1_DATPACK_0         (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */

+#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)

+#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00003000 */

+#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */

+#define DFSDM_CHCFGR1_DATMPX_1          (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */

+#define DFSDM_CHCFGR1_DATMPX_0          (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */

+#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)

+#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)   /*!< 0x00000100 */

+#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */

+#define DFSDM_CHCFGR1_CHEN_Pos          (7U)

+#define DFSDM_CHCFGR1_CHEN_Msk          (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)      /*!< 0x00000080 */

+#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */

+#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)

+#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)    /*!< 0x00000040 */

+#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */

+#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)

+#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)     /*!< 0x00000020 */

+#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */

+#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)

+#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x0000000C */

+#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */

+#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */

+#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */

+#define DFSDM_CHCFGR1_SITP_Pos          (0U)

+#define DFSDM_CHCFGR1_SITP_Msk          (0x3UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000003 */

+#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */

+#define DFSDM_CHCFGR1_SITP_1            (0x2UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */

+#define DFSDM_CHCFGR1_SITP_0            (0x1UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */

+

+/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/

+#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)

+#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */

+#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)

+#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)    /*!< 0x000000F8 */

+#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */

+

+/******************  Bit definition for DFSDM_CHAWSCDR register *****************/

+#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)

+#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00C00000 */

+#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */

+#define DFSDM_CHAWSCDR_AWFORD_1         (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */

+#define DFSDM_CHAWSCDR_AWFORD_0         (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */

+#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)

+#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)  /*!< 0x001F0000 */

+#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */

+#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)

+#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)    /*!< 0x0000F000 */

+#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */

+#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)

+#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)    /*!< 0x000000FF */

+#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */

+

+/****************  Bit definition for DFSDM_CHWDATR register *******************/

+#define DFSDM_CHWDATR_WDATA_Pos         (0U)

+#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)  /*!< 0x0000FFFF */

+#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */

+

+/****************  Bit definition for DFSDM_CHDATINR register *****************/

+#define DFSDM_CHDATINR_INDAT0_Pos       (0U)

+#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */

+#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */

+#define DFSDM_CHDATINR_INDAT1_Pos       (16U)

+#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */

+#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */

+

+/************************   DFSDM module registers  ****************************/

+

+/********************  Bit definition for DFSDM_FLTCR1 register *******************/

+#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)

+#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)     /*!< 0x40000000 */

+#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */

+#define DFSDM_FLTCR1_FAST_Pos           (29U)

+#define DFSDM_FLTCR1_FAST_Msk           (0x1UL << DFSDM_FLTCR1_FAST_Pos)       /*!< 0x20000000 */

+#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */

+#define DFSDM_FLTCR1_RCH_Pos            (24U)

+#define DFSDM_FLTCR1_RCH_Msk            (0x7UL << DFSDM_FLTCR1_RCH_Pos)        /*!< 0x07000000 */

+#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */

+#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)

+#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)     /*!< 0x00200000 */

+#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */

+#define DFSDM_FLTCR1_RSYNC_Pos          (19U)

+#define DFSDM_FLTCR1_RSYNC_Msk          (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)      /*!< 0x00080000 */

+#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */

+#define DFSDM_FLTCR1_RCONT_Pos          (18U)

+#define DFSDM_FLTCR1_RCONT_Msk          (0x1UL << DFSDM_FLTCR1_RCONT_Pos)      /*!< 0x00040000 */

+#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */

+#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)

+#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)   /*!< 0x00020000 */

+#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */

+#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)

+#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00006000 */

+#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */

+#define DFSDM_FLTCR1_JEXTEN_1           (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */

+#define DFSDM_FLTCR1_JEXTEN_0           (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */

+#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)

+#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)   /*!< 0x00001F00 */

+#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */

+#define DFSDM_FLTCR1_JEXTSEL_0          (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000100 */

+#define DFSDM_FLTCR1_JEXTSEL_1          (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000200 */

+#define DFSDM_FLTCR1_JEXTSEL_2          (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000400 */

+#define DFSDM_FLTCR1_JEXTSEL_3          (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000800 */

+#define DFSDM_FLTCR1_JEXTSEL_4          (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00001000 */

+

+#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)

+#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)     /*!< 0x00000020 */

+#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */

+#define DFSDM_FLTCR1_JSCAN_Pos          (4U)

+#define DFSDM_FLTCR1_JSCAN_Msk          (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)      /*!< 0x00000010 */

+#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */

+#define DFSDM_FLTCR1_JSYNC_Pos          (3U)

+#define DFSDM_FLTCR1_JSYNC_Msk          (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)      /*!< 0x00000008 */

+#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */

+#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)

+#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)   /*!< 0x00000002 */

+#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */

+#define DFSDM_FLTCR1_DFEN_Pos           (0U)

+#define DFSDM_FLTCR1_DFEN_Msk           (0x1UL << DFSDM_FLTCR1_DFEN_Pos)       /*!< 0x00000001 */

+#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */

+

+/********************  Bit definition for DFSDM_FLTCR2 register *******************/

+#define DFSDM_FLTCR2_AWDCH_Pos          (16U)

+#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)     /*!< 0x00FF0000 */

+#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */

+#define DFSDM_FLTCR2_EXCH_Pos           (8U)

+#define DFSDM_FLTCR2_EXCH_Msk           (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)      /*!< 0x0000FF00 */

+#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */

+#define DFSDM_FLTCR2_CKABIE_Pos         (6U)

+#define DFSDM_FLTCR2_CKABIE_Msk         (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)     /*!< 0x00000040 */

+#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */

+#define DFSDM_FLTCR2_SCDIE_Pos          (5U)

+#define DFSDM_FLTCR2_SCDIE_Msk          (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)      /*!< 0x00000020 */

+#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */

+#define DFSDM_FLTCR2_AWDIE_Pos          (4U)

+#define DFSDM_FLTCR2_AWDIE_Msk          (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)      /*!< 0x00000010 */

+#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */

+#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)

+#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)     /*!< 0x00000008 */

+#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */

+#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)

+#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)     /*!< 0x00000004 */

+#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */

+#define DFSDM_FLTCR2_REOCIE_Pos         (1U)

+#define DFSDM_FLTCR2_REOCIE_Msk         (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)     /*!< 0x00000002 */

+#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */

+#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)

+#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)     /*!< 0x00000001 */

+#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */

+

+/********************  Bit definition for DFSDM_FLTISR register *******************/

+#define DFSDM_FLTISR_SCDF_Pos           (24U)

+#define DFSDM_FLTISR_SCDF_Msk           (0xFFUL << DFSDM_FLTISR_SCDF_Pos)      /*!< 0xFF000000 */

+#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */

+#define DFSDM_FLTISR_CKABF_Pos          (16U)

+#define DFSDM_FLTISR_CKABF_Msk          (0xFFUL << DFSDM_FLTISR_CKABF_Pos)     /*!< 0x00FF0000 */

+#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */

+#define DFSDM_FLTISR_RCIP_Pos           (14U)

+#define DFSDM_FLTISR_RCIP_Msk           (0x1UL << DFSDM_FLTISR_RCIP_Pos)       /*!< 0x00004000 */

+#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */

+#define DFSDM_FLTISR_JCIP_Pos           (13U)

+#define DFSDM_FLTISR_JCIP_Msk           (0x1UL << DFSDM_FLTISR_JCIP_Pos)       /*!< 0x00002000 */

+#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */

+#define DFSDM_FLTISR_AWDF_Pos           (4U)

+#define DFSDM_FLTISR_AWDF_Msk           (0x1UL << DFSDM_FLTISR_AWDF_Pos)       /*!< 0x00000010 */

+#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */

+#define DFSDM_FLTISR_ROVRF_Pos          (3U)

+#define DFSDM_FLTISR_ROVRF_Msk          (0x1UL << DFSDM_FLTISR_ROVRF_Pos)      /*!< 0x00000008 */

+#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */

+#define DFSDM_FLTISR_JOVRF_Pos          (2U)

+#define DFSDM_FLTISR_JOVRF_Msk          (0x1UL << DFSDM_FLTISR_JOVRF_Pos)      /*!< 0x00000004 */

+#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */

+#define DFSDM_FLTISR_REOCF_Pos          (1U)

+#define DFSDM_FLTISR_REOCF_Msk          (0x1UL << DFSDM_FLTISR_REOCF_Pos)      /*!< 0x00000002 */

+#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */

+#define DFSDM_FLTISR_JEOCF_Pos          (0U)

+#define DFSDM_FLTISR_JEOCF_Msk          (0x1UL << DFSDM_FLTISR_JEOCF_Pos)      /*!< 0x00000001 */

+#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */

+

+/********************  Bit definition for DFSDM_FLTICR register *******************/

+#define DFSDM_FLTICR_CLRSCDF_Pos        (24U)

+#define DFSDM_FLTICR_CLRSCDF_Msk        (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)   /*!< 0xFF000000 */

+#define DFSDM_FLTICR_CLRSCDF            DFSDM_FLTICR_CLRSCDF_Msk               /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */

+#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)

+#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)  /*!< 0x00FF0000 */

+#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */

+#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)

+#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)   /*!< 0x00000008 */

+#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */

+#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)

+#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)   /*!< 0x00000004 */

+#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */

+

+/*******************  Bit definition for DFSDM_FLTJCHGR register ******************/

+#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)

+#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)    /*!< 0x000000FF */

+#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */

+

+/********************  Bit definition for DFSDM_FLTFCR register *******************/

+#define DFSDM_FLTFCR_FORD_Pos           (29U)

+#define DFSDM_FLTFCR_FORD_Msk           (0x7UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0xE0000000 */

+#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */

+#define DFSDM_FLTFCR_FORD_2             (0x4UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */

+#define DFSDM_FLTFCR_FORD_1             (0x2UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */

+#define DFSDM_FLTFCR_FORD_0             (0x1UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */

+#define DFSDM_FLTFCR_FOSR_Pos           (16U)

+#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)     /*!< 0x03FF0000 */

+#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */

+#define DFSDM_FLTFCR_IOSR_Pos           (0U)

+#define DFSDM_FLTFCR_IOSR_Msk           (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)      /*!< 0x000000FF */

+#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */

+

+/******************  Bit definition for DFSDM_FLTJDATAR register *****************/

+#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)

+#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */

+#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)

+#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */

+#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */

+

+/******************  Bit definition for DFSDM_FLTRDATAR register *****************/

+#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)

+#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */

+#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)

+#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)   /*!< 0x00000010 */

+#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */

+#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)

+#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */

+#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */

+

+/******************  Bit definition for DFSDM_FLTAWHTR register ******************/

+#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)

+#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */

+#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)

+#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)    /*!< 0x0000000F */

+#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */

+

+/******************  Bit definition for DFSDM_FLTAWLTR register ******************/

+#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)

+#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWHT[23:0] Analog watchdog low threshold */

+#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)

+#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)    /*!< 0x0000000F */

+#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */

+

+/******************  Bit definition for DFSDM_FLTAWSR register ******************/

+#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)

+#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)    /*!< 0x0000FF00 */

+#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */

+#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)

+#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)    /*!< 0x000000FF */

+#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */

+

+/******************  Bit definition for DFSDM_FLTAWCFR) register *****************/

+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)

+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */

+#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */

+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)

+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */

+#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */

+

+/******************  Bit definition for DFSDM_FLTEXMAX register ******************/

+#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)

+#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */

+#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)

+#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)  /*!< 0x00000007 */

+#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */

+

+/******************  Bit definition for DFSDM_FLTEXMIN register ******************/

+#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)

+#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */

+#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)

+#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)  /*!< 0x00000007 */

+#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */

+

+/******************  Bit definition for DFSDM_FLTCNVTIMR register ******************/

+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)

+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */

+#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           BDMA Controller                                  */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for BDMA_ISR register  ********************/

+#define BDMA_ISR_GIF0_Pos       (0U)

+#define BDMA_ISR_GIF0_Msk       (0x1UL << BDMA_ISR_GIF0_Pos)                   /*!< 0x00000001 */

+#define BDMA_ISR_GIF0           BDMA_ISR_GIF0_Msk                              /*!< Channel 0 Global interrupt flag */

+#define BDMA_ISR_TCIF0_Pos      (1U)

+#define BDMA_ISR_TCIF0_Msk      (0x1UL << BDMA_ISR_TCIF0_Pos)                  /*!< 0x00000002 */

+#define BDMA_ISR_TCIF0          BDMA_ISR_TCIF0_Msk                             /*!< Channel 0 Transfer Complete flag */

+#define BDMA_ISR_HTIF0_Pos      (2U)

+#define BDMA_ISR_HTIF0_Msk      (0x1UL << BDMA_ISR_HTIF0_Pos)                  /*!< 0x00000004 */

+#define BDMA_ISR_HTIF0          BDMA_ISR_HTIF0_Msk                             /*!< Channel 0 Half Transfer flag */

+#define BDMA_ISR_TEIF0_Pos      (3U)

+#define BDMA_ISR_TEIF0_Msk      (0x1UL << BDMA_ISR_TEIF0_Pos)                  /*!< 0x00000008 */

+#define BDMA_ISR_TEIF0          BDMA_ISR_TEIF0_Msk                             /*!< Channel 0 Transfer Error flag */

+#define BDMA_ISR_GIF1_Pos       (4U)

+#define BDMA_ISR_GIF1_Msk       (0x1UL << BDMA_ISR_GIF1_Pos)                   /*!< 0x00000010 */

+#define BDMA_ISR_GIF1           BDMA_ISR_GIF1_Msk                              /*!< Channel 1 Global interrupt flag */

+#define BDMA_ISR_TCIF1_Pos      (5U)

+#define BDMA_ISR_TCIF1_Msk      (0x1UL << BDMA_ISR_TCIF1_Pos)                  /*!< 0x00000020 */

+#define BDMA_ISR_TCIF1          BDMA_ISR_TCIF1_Msk                             /*!< Channel 1 Transfer Complete flag */

+#define BDMA_ISR_HTIF1_Pos      (6U)

+#define BDMA_ISR_HTIF1_Msk      (0x1UL << BDMA_ISR_HTIF1_Pos)                  /*!< 0x00000040 */

+#define BDMA_ISR_HTIF1          BDMA_ISR_HTIF1_Msk                             /*!< Channel 1 Half Transfer flag */

+#define BDMA_ISR_TEIF1_Pos      (7U)

+#define BDMA_ISR_TEIF1_Msk      (0x1UL << BDMA_ISR_TEIF1_Pos)                  /*!< 0x00000080 */

+#define BDMA_ISR_TEIF1          BDMA_ISR_TEIF1_Msk                             /*!< Channel 1 Transfer Error flag */

+#define BDMA_ISR_GIF2_Pos       (8U)

+#define BDMA_ISR_GIF2_Msk       (0x1UL << BDMA_ISR_GIF2_Pos)                   /*!< 0x00000100 */

+#define BDMA_ISR_GIF2           BDMA_ISR_GIF2_Msk                              /*!< Channel 2 Global interrupt flag */

+#define BDMA_ISR_TCIF2_Pos      (9U)

+#define BDMA_ISR_TCIF2_Msk      (0x1UL << BDMA_ISR_TCIF2_Pos)                  /*!< 0x00000200 */

+#define BDMA_ISR_TCIF2          BDMA_ISR_TCIF2_Msk                             /*!< Channel 2 Transfer Complete flag */

+#define BDMA_ISR_HTIF2_Pos      (10U)

+#define BDMA_ISR_HTIF2_Msk      (0x1UL << BDMA_ISR_HTIF2_Pos)                  /*!< 0x00000400 */

+#define BDMA_ISR_HTIF2          BDMA_ISR_HTIF2_Msk                             /*!< Channel 2 Half Transfer flag */

+#define BDMA_ISR_TEIF2_Pos      (11U)

+#define BDMA_ISR_TEIF2_Msk      (0x1UL << BDMA_ISR_TEIF2_Pos)                  /*!< 0x00000800 */

+#define BDMA_ISR_TEIF2          BDMA_ISR_TEIF2_Msk                             /*!< Channel 2 Transfer Error flag */

+#define BDMA_ISR_GIF3_Pos       (12U)

+#define BDMA_ISR_GIF3_Msk       (0x1UL << BDMA_ISR_GIF3_Pos)                   /*!< 0x00001000 */

+#define BDMA_ISR_GIF3           BDMA_ISR_GIF3_Msk                              /*!< Channel 3 Global interrupt flag */

+#define BDMA_ISR_TCIF3_Pos      (13U)

+#define BDMA_ISR_TCIF3_Msk      (0x1UL << BDMA_ISR_TCIF3_Pos)                  /*!< 0x00002000 */

+#define BDMA_ISR_TCIF3          BDMA_ISR_TCIF3_Msk                             /*!< Channel 3 Transfer Complete flag */

+#define BDMA_ISR_HTIF3_Pos      (14U)

+#define BDMA_ISR_HTIF3_Msk      (0x1UL << BDMA_ISR_HTIF3_Pos)                  /*!< 0x00004000 */

+#define BDMA_ISR_HTIF3          BDMA_ISR_HTIF3_Msk                             /*!< Channel 3 Half Transfer flag */

+#define BDMA_ISR_TEIF3_Pos      (15U)

+#define BDMA_ISR_TEIF3_Msk      (0x1UL << BDMA_ISR_TEIF3_Pos)                  /*!< 0x00008000 */

+#define BDMA_ISR_TEIF3          BDMA_ISR_TEIF3_Msk                             /*!< Channel 3 Transfer Error flag */

+#define BDMA_ISR_GIF4_Pos       (16U)

+#define BDMA_ISR_GIF4_Msk       (0x1UL << BDMA_ISR_GIF4_Pos)                   /*!< 0x00010000 */

+#define BDMA_ISR_GIF4           BDMA_ISR_GIF4_Msk                              /*!< Channel 4 Global interrupt flag */

+#define BDMA_ISR_TCIF4_Pos      (17U)

+#define BDMA_ISR_TCIF4_Msk      (0x1UL << BDMA_ISR_TCIF4_Pos)                  /*!< 0x00020000 */

+#define BDMA_ISR_TCIF4          BDMA_ISR_TCIF4_Msk                             /*!< Channel 4 Transfer Complete flag */

+#define BDMA_ISR_HTIF4_Pos      (18U)

+#define BDMA_ISR_HTIF4_Msk      (0x1UL << BDMA_ISR_HTIF4_Pos)                  /*!< 0x00040000 */

+#define BDMA_ISR_HTIF4          BDMA_ISR_HTIF4_Msk                             /*!< Channel 4 Half Transfer flag */

+#define BDMA_ISR_TEIF4_Pos      (19U)

+#define BDMA_ISR_TEIF4_Msk      (0x1UL << BDMA_ISR_TEIF4_Pos)                  /*!< 0x00080000 */

+#define BDMA_ISR_TEIF4          BDMA_ISR_TEIF4_Msk                             /*!< Channel 4 Transfer Error flag */

+#define BDMA_ISR_GIF5_Pos       (20U)

+#define BDMA_ISR_GIF5_Msk       (0x1UL << BDMA_ISR_GIF5_Pos)                   /*!< 0x00100000 */

+#define BDMA_ISR_GIF5           BDMA_ISR_GIF5_Msk                              /*!< Channel 5 Global interrupt flag */

+#define BDMA_ISR_TCIF5_Pos      (21U)

+#define BDMA_ISR_TCIF5_Msk      (0x1UL << BDMA_ISR_TCIF5_Pos)                  /*!< 0x00200000 */

+#define BDMA_ISR_TCIF5          BDMA_ISR_TCIF5_Msk                             /*!< Channel 5 Transfer Complete flag */

+#define BDMA_ISR_HTIF5_Pos      (22U)

+#define BDMA_ISR_HTIF5_Msk      (0x1UL << BDMA_ISR_HTIF5_Pos)                  /*!< 0x00400000 */

+#define BDMA_ISR_HTIF5          BDMA_ISR_HTIF5_Msk                             /*!< Channel 5 Half Transfer flag */

+#define BDMA_ISR_TEIF5_Pos      (23U)

+#define BDMA_ISR_TEIF5_Msk      (0x1UL << BDMA_ISR_TEIF5_Pos)                  /*!< 0x00800000 */

+#define BDMA_ISR_TEIF5          BDMA_ISR_TEIF5_Msk                             /*!< Channel 5 Transfer Error flag */

+#define BDMA_ISR_GIF6_Pos       (24U)

+#define BDMA_ISR_GIF6_Msk       (0x1UL << BDMA_ISR_GIF6_Pos)                   /*!< 0x01000000 */

+#define BDMA_ISR_GIF6           BDMA_ISR_GIF6_Msk                              /*!< Channel 6 Global interrupt flag */

+#define BDMA_ISR_TCIF6_Pos      (25U)

+#define BDMA_ISR_TCIF6_Msk      (0x1UL << BDMA_ISR_TCIF6_Pos)                  /*!< 0x02000000 */

+#define BDMA_ISR_TCIF6          BDMA_ISR_TCIF6_Msk                             /*!< Channel 6 Transfer Complete flag */

+#define BDMA_ISR_HTIF6_Pos      (26U)

+#define BDMA_ISR_HTIF6_Msk      (0x1UL << BDMA_ISR_HTIF6_Pos)                  /*!< 0x04000000 */

+#define BDMA_ISR_HTIF6          BDMA_ISR_HTIF6_Msk                             /*!< Channel 6 Half Transfer flag */

+#define BDMA_ISR_TEIF6_Pos      (27U)

+#define BDMA_ISR_TEIF6_Msk      (0x1UL << BDMA_ISR_TEIF6_Pos)                  /*!< 0x08000000 */

+#define BDMA_ISR_TEIF6          BDMA_ISR_TEIF6_Msk                             /*!< Channel 6 Transfer Error flag */

+#define BDMA_ISR_GIF7_Pos       (28U)

+#define BDMA_ISR_GIF7_Msk       (0x1UL << BDMA_ISR_GIF7_Pos)                   /*!< 0x10000000 */

+#define BDMA_ISR_GIF7           BDMA_ISR_GIF7_Msk                              /*!< Channel 7 Global interrupt flag */

+#define BDMA_ISR_TCIF7_Pos      (29U)

+#define BDMA_ISR_TCIF7_Msk      (0x1UL << BDMA_ISR_TCIF7_Pos)                  /*!< 0x20000000 */

+#define BDMA_ISR_TCIF7          BDMA_ISR_TCIF7_Msk                             /*!< Channel 7 Transfer Complete flag */

+#define BDMA_ISR_HTIF7_Pos      (30U)

+#define BDMA_ISR_HTIF7_Msk      (0x1UL << BDMA_ISR_HTIF7_Pos)                  /*!< 0x40000000 */

+#define BDMA_ISR_HTIF7          BDMA_ISR_HTIF7_Msk                             /*!< Channel 7 Half Transfer flag */

+#define BDMA_ISR_TEIF7_Pos      (31U)

+#define BDMA_ISR_TEIF7_Msk      (0x1UL << BDMA_ISR_TEIF7_Pos)                  /*!< 0x80000000 */

+#define BDMA_ISR_TEIF7          BDMA_ISR_TEIF7_Msk                             /*!< Channel 7 Transfer Error flag */

+

+/*******************  Bit definition for BDMA_IFCR register  *******************/

+#define BDMA_IFCR_CGIF0_Pos     (0U)

+#define BDMA_IFCR_CGIF0_Msk     (0x1UL << BDMA_IFCR_CGIF0_Pos)                 /*!< 0x00000001 */

+#define BDMA_IFCR_CGIF0         BDMA_IFCR_CGIF0_Msk                            /*!< Channel 0 Global interrupt clearr */

+#define BDMA_IFCR_CTCIF0_Pos    (1U)

+#define BDMA_IFCR_CTCIF0_Msk    (0x1UL << BDMA_IFCR_CTCIF0_Pos)                /*!< 0x00000002 */

+#define BDMA_IFCR_CTCIF0        BDMA_IFCR_CTCIF0_Msk                           /*!< Channel 0 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF0_Pos    (2U)

+#define BDMA_IFCR_CHTIF0_Msk    (0x1UL << BDMA_IFCR_CHTIF0_Pos)                /*!< 0x00000004 */

+#define BDMA_IFCR_CHTIF0        BDMA_IFCR_CHTIF0_Msk                           /*!< Channel 0 Half Transfer clear */

+#define BDMA_IFCR_CTEIF0_Pos    (3U)

+#define BDMA_IFCR_CTEIF0_Msk    (0x1UL << BDMA_IFCR_CTEIF0_Pos)                /*!< 0x00000008 */

+#define BDMA_IFCR_CTEIF0        BDMA_IFCR_CTEIF0_Msk                           /*!< Channel 0 Transfer Error clear */

+#define BDMA_IFCR_CGIF1_Pos     (4U)

+#define BDMA_IFCR_CGIF1_Msk     (0x1UL << BDMA_IFCR_CGIF1_Pos)                 /*!< 0x00000010 */

+#define BDMA_IFCR_CGIF1         BDMA_IFCR_CGIF1_Msk                            /*!< Channel 1 Global interrupt clear */

+#define BDMA_IFCR_CTCIF1_Pos    (5U)

+#define BDMA_IFCR_CTCIF1_Msk    (0x1UL << BDMA_IFCR_CTCIF1_Pos)                /*!< 0x00000020 */

+#define BDMA_IFCR_CTCIF1        BDMA_IFCR_CTCIF1_Msk                           /*!< Channel 1 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF1_Pos    (6U)

+#define BDMA_IFCR_CHTIF1_Msk    (0x1UL << BDMA_IFCR_CHTIF1_Pos)                /*!< 0x00000040 */

+#define BDMA_IFCR_CHTIF1        BDMA_IFCR_CHTIF1_Msk                           /*!< Channel 1 Half Transfer clear */

+#define BDMA_IFCR_CTEIF1_Pos    (7U)

+#define BDMA_IFCR_CTEIF1_Msk    (0x1UL << BDMA_IFCR_CTEIF1_Pos)                /*!< 0x00000080 */

+#define BDMA_IFCR_CTEIF1        BDMA_IFCR_CTEIF1_Msk                           /*!< Channel 1 Transfer Error clear */

+#define BDMA_IFCR_CGIF2_Pos     (8U)

+#define BDMA_IFCR_CGIF2_Msk     (0x1UL << BDMA_IFCR_CGIF2_Pos)                 /*!< 0x00000100 */

+#define BDMA_IFCR_CGIF2         BDMA_IFCR_CGIF2_Msk                            /*!< Channel 2 Global interrupt clear */

+#define BDMA_IFCR_CTCIF2_Pos    (9U)

+#define BDMA_IFCR_CTCIF2_Msk    (0x1UL << BDMA_IFCR_CTCIF2_Pos)                /*!< 0x00000200 */

+#define BDMA_IFCR_CTCIF2        BDMA_IFCR_CTCIF2_Msk                           /*!< Channel 2 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF2_Pos    (10U)

+#define BDMA_IFCR_CHTIF2_Msk    (0x1UL << BDMA_IFCR_CHTIF2_Pos)                /*!< 0x00000400 */

+#define BDMA_IFCR_CHTIF2        BDMA_IFCR_CHTIF2_Msk                           /*!< Channel 2 Half Transfer clear */

+#define BDMA_IFCR_CTEIF2_Pos    (11U)

+#define BDMA_IFCR_CTEIF2_Msk    (0x1UL << BDMA_IFCR_CTEIF2_Pos)                /*!< 0x00000800 */

+#define BDMA_IFCR_CTEIF2        BDMA_IFCR_CTEIF2_Msk                           /*!< Channel 2 Transfer Error clear */

+#define BDMA_IFCR_CGIF3_Pos     (12U)

+#define BDMA_IFCR_CGIF3_Msk     (0x1UL << BDMA_IFCR_CGIF3_Pos)                 /*!< 0x00001000 */

+#define BDMA_IFCR_CGIF3         BDMA_IFCR_CGIF3_Msk                            /*!< Channel 3 Global interrupt clear */

+#define BDMA_IFCR_CTCIF3_Pos    (13U)

+#define BDMA_IFCR_CTCIF3_Msk    (0x1UL << BDMA_IFCR_CTCIF3_Pos)                /*!< 0x00002000 */

+#define BDMA_IFCR_CTCIF3        BDMA_IFCR_CTCIF3_Msk                           /*!< Channel 3 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF3_Pos    (14U)

+#define BDMA_IFCR_CHTIF3_Msk    (0x1UL << BDMA_IFCR_CHTIF3_Pos)                /*!< 0x00004000 */

+#define BDMA_IFCR_CHTIF3        BDMA_IFCR_CHTIF3_Msk                           /*!< Channel 3 Half Transfer clear */

+#define BDMA_IFCR_CTEIF3_Pos    (15U)

+#define BDMA_IFCR_CTEIF3_Msk    (0x1UL << BDMA_IFCR_CTEIF3_Pos)                /*!< 0x00008000 */

+#define BDMA_IFCR_CTEIF3        BDMA_IFCR_CTEIF3_Msk                           /*!< Channel 3 Transfer Error clear */

+#define BDMA_IFCR_CGIF4_Pos     (16U)

+#define BDMA_IFCR_CGIF4_Msk     (0x1UL << BDMA_IFCR_CGIF4_Pos)                 /*!< 0x00010000 */

+#define BDMA_IFCR_CGIF4         BDMA_IFCR_CGIF4_Msk                            /*!< Channel 4 Global interrupt clear */

+#define BDMA_IFCR_CTCIF4_Pos    (17U)

+#define BDMA_IFCR_CTCIF4_Msk    (0x1UL << BDMA_IFCR_CTCIF4_Pos)                /*!< 0x00020000 */

+#define BDMA_IFCR_CTCIF4        BDMA_IFCR_CTCIF4_Msk                           /*!< Channel 4 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF4_Pos    (18U)

+#define BDMA_IFCR_CHTIF4_Msk    (0x1UL << BDMA_IFCR_CHTIF4_Pos)                /*!< 0x00040000 */

+#define BDMA_IFCR_CHTIF4        BDMA_IFCR_CHTIF4_Msk                           /*!< Channel 4 Half Transfer clear */

+#define BDMA_IFCR_CTEIF4_Pos    (19U)

+#define BDMA_IFCR_CTEIF4_Msk    (0x1UL << BDMA_IFCR_CTEIF4_Pos)                /*!< 0x00080000 */

+#define BDMA_IFCR_CTEIF4        BDMA_IFCR_CTEIF4_Msk                           /*!< Channel 4 Transfer Error clear */

+#define BDMA_IFCR_CGIF5_Pos     (20U)

+#define BDMA_IFCR_CGIF5_Msk     (0x1UL << BDMA_IFCR_CGIF5_Pos)                 /*!< 0x00100000 */

+#define BDMA_IFCR_CGIF5         BDMA_IFCR_CGIF5_Msk                            /*!< Channel 5 Global interrupt clear */

+#define BDMA_IFCR_CTCIF5_Pos    (21U)

+#define BDMA_IFCR_CTCIF5_Msk    (0x1UL << BDMA_IFCR_CTCIF5_Pos)                /*!< 0x00200000 */

+#define BDMA_IFCR_CTCIF5        BDMA_IFCR_CTCIF5_Msk                           /*!< Channel 5 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF5_Pos    (22U)

+#define BDMA_IFCR_CHTIF5_Msk    (0x1UL << BDMA_IFCR_CHTIF5_Pos)                /*!< 0x00400000 */

+#define BDMA_IFCR_CHTIF5        BDMA_IFCR_CHTIF5_Msk                           /*!< Channel 5 Half Transfer clear */

+#define BDMA_IFCR_CTEIF5_Pos    (23U)

+#define BDMA_IFCR_CTEIF5_Msk    (0x1UL << BDMA_IFCR_CTEIF5_Pos)                /*!< 0x00800000 */

+#define BDMA_IFCR_CTEIF5        BDMA_IFCR_CTEIF5_Msk                           /*!< Channel 5 Transfer Error clear */

+#define BDMA_IFCR_CGIF6_Pos     (24U)

+#define BDMA_IFCR_CGIF6_Msk     (0x1UL << BDMA_IFCR_CGIF6_Pos)                 /*!< 0x01000000 */

+#define BDMA_IFCR_CGIF6         BDMA_IFCR_CGIF6_Msk                            /*!< Channel 6 Global interrupt clear */

+#define BDMA_IFCR_CTCIF6_Pos    (25U)

+#define BDMA_IFCR_CTCIF6_Msk    (0x1UL << BDMA_IFCR_CTCIF6_Pos)                /*!< 0x02000000 */

+#define BDMA_IFCR_CTCIF6        BDMA_IFCR_CTCIF6_Msk                           /*!< Channel 6 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF6_Pos    (26U)

+#define BDMA_IFCR_CHTIF6_Msk    (0x1UL << BDMA_IFCR_CHTIF6_Pos)                /*!< 0x04000000 */

+#define BDMA_IFCR_CHTIF6        BDMA_IFCR_CHTIF6_Msk                           /*!< Channel 6 Half Transfer clear */

+#define BDMA_IFCR_CTEIF6_Pos    (27U)

+#define BDMA_IFCR_CTEIF6_Msk    (0x1UL << BDMA_IFCR_CTEIF6_Pos)                /*!< 0x08000000 */

+#define BDMA_IFCR_CTEIF6        BDMA_IFCR_CTEIF6_Msk                           /*!< Channel 6 Transfer Error clear */

+#define BDMA_IFCR_CGIF7_Pos     (28U)

+#define BDMA_IFCR_CGIF7_Msk     (0x1UL << BDMA_IFCR_CGIF7_Pos)                 /*!< 0x10000000 */

+#define BDMA_IFCR_CGIF7         BDMA_IFCR_CGIF7_Msk                            /*!< Channel 7 Global interrupt clear */

+#define BDMA_IFCR_CTCIF7_Pos    (29U)

+#define BDMA_IFCR_CTCIF7_Msk    (0x1UL << BDMA_IFCR_CTCIF7_Pos)                /*!< 0x20000000 */

+#define BDMA_IFCR_CTCIF7        BDMA_IFCR_CTCIF7_Msk                           /*!< Channel 7 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF7_Pos    (30U)

+#define BDMA_IFCR_CHTIF7_Msk    (0x1UL << BDMA_IFCR_CHTIF7_Pos)                /*!< 0x40000000 */

+#define BDMA_IFCR_CHTIF7        BDMA_IFCR_CHTIF7_Msk                           /*!< Channel 7 Half Transfer clear */

+#define BDMA_IFCR_CTEIF7_Pos    (31U)

+#define BDMA_IFCR_CTEIF7_Msk    (0x1UL << BDMA_IFCR_CTEIF7_Pos)                /*!< 0x80000000 */

+#define BDMA_IFCR_CTEIF7        BDMA_IFCR_CTEIF7_Msk                           /*!< Channel 7 Transfer Error clear */

+

+/*******************  Bit definition for BDMA_CCR register  ********************/

+#define BDMA_CCR_EN_Pos         (0U)

+#define BDMA_CCR_EN_Msk         (0x1UL << BDMA_CCR_EN_Pos)                     /*!< 0x00000001 */

+#define BDMA_CCR_EN             BDMA_CCR_EN_Msk                                /*!< Channel enable                      */

+#define BDMA_CCR_TCIE_Pos       (1U)

+#define BDMA_CCR_TCIE_Msk       (0x1UL << BDMA_CCR_TCIE_Pos)                   /*!< 0x00000002 */

+#define BDMA_CCR_TCIE           BDMA_CCR_TCIE_Msk                              /*!< Transfer complete interrupt enable  */

+#define BDMA_CCR_HTIE_Pos       (2U)

+#define BDMA_CCR_HTIE_Msk       (0x1UL << BDMA_CCR_HTIE_Pos)                   /*!< 0x00000004 */

+#define BDMA_CCR_HTIE           BDMA_CCR_HTIE_Msk                              /*!< Half Transfer interrupt enable      */

+#define BDMA_CCR_TEIE_Pos       (3U)

+#define BDMA_CCR_TEIE_Msk       (0x1UL << BDMA_CCR_TEIE_Pos)                   /*!< 0x00000008 */

+#define BDMA_CCR_TEIE           BDMA_CCR_TEIE_Msk                              /*!< Transfer error interrupt enable     */

+#define BDMA_CCR_DIR_Pos        (4U)

+#define BDMA_CCR_DIR_Msk        (0x1UL << BDMA_CCR_DIR_Pos)                    /*!< 0x00000010 */

+#define BDMA_CCR_DIR            BDMA_CCR_DIR_Msk                               /*!< Data transfer direction             */

+#define BDMA_CCR_CIRC_Pos       (5U)

+#define BDMA_CCR_CIRC_Msk       (0x1UL << BDMA_CCR_CIRC_Pos)                   /*!< 0x00000020 */

+#define BDMA_CCR_CIRC           BDMA_CCR_CIRC_Msk                              /*!< Circular mode                       */

+#define BDMA_CCR_PINC_Pos       (6U)

+#define BDMA_CCR_PINC_Msk       (0x1UL << BDMA_CCR_PINC_Pos)                   /*!< 0x00000040 */

+#define BDMA_CCR_PINC           BDMA_CCR_PINC_Msk                              /*!< Peripheral increment mode           */

+#define BDMA_CCR_MINC_Pos       (7U)

+#define BDMA_CCR_MINC_Msk       (0x1UL << BDMA_CCR_MINC_Pos)                   /*!< 0x00000080 */

+#define BDMA_CCR_MINC           BDMA_CCR_MINC_Msk                              /*!< Memory increment mode               */

+

+#define BDMA_CCR_PSIZE_Pos      (8U)

+#define BDMA_CCR_PSIZE_Msk      (0x3UL << BDMA_CCR_PSIZE_Pos)                  /*!< 0x00000300 */

+#define BDMA_CCR_PSIZE          BDMA_CCR_PSIZE_Msk                             /*!< PSIZE[1:0] bits (Peripheral size)   */

+#define BDMA_CCR_PSIZE_0        (0x1UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000100 */

+#define BDMA_CCR_PSIZE_1        (0x2UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000200 */

+

+#define BDMA_CCR_MSIZE_Pos      (10U)

+#define BDMA_CCR_MSIZE_Msk      (0x3UL << BDMA_CCR_MSIZE_Pos)                  /*!< 0x00000C00 */

+#define BDMA_CCR_MSIZE          BDMA_CCR_MSIZE_Msk                             /*!< MSIZE[1:0] bits (Memory size)       */

+#define BDMA_CCR_MSIZE_0        (0x1UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000400 */

+#define BDMA_CCR_MSIZE_1        (0x2UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000800 */

+

+#define BDMA_CCR_PL_Pos         (12U)

+#define BDMA_CCR_PL_Msk         (0x3UL << BDMA_CCR_PL_Pos)                     /*!< 0x00003000 */

+#define BDMA_CCR_PL             BDMA_CCR_PL_Msk                                /*!< PL[1:0] bits(Channel Priority level)*/

+#define BDMA_CCR_PL_0           (0x1UL << BDMA_CCR_PL_Pos)                      /*!< 0x00001000 */

+#define BDMA_CCR_PL_1           (0x2UL << BDMA_CCR_PL_Pos)                      /*!< 0x00002000 */

+

+#define BDMA_CCR_MEM2MEM_Pos    (14U)

+#define BDMA_CCR_MEM2MEM_Msk    (0x1UL << BDMA_CCR_MEM2MEM_Pos)                /*!< 0x00004000 */

+#define BDMA_CCR_MEM2MEM        BDMA_CCR_MEM2MEM_Msk                           /*!< Memory to memory mode               */

+#define BDMA_CCR_DBM_Pos        (15U)

+#define BDMA_CCR_DBM_Msk        (0x1UL << BDMA_CCR_DBM_Pos)                    /*!< 0x0000A000 */

+#define BDMA_CCR_DBM            BDMA_CCR_DBM_Msk                               /*!< Memory to memory mode               */

+#define BDMA_CCR_CT_Pos         (16U)

+#define BDMA_CCR_CT_Msk         (0x1UL << BDMA_CCR_CT_Pos)                     /*!< 0x00010000 */

+#define BDMA_CCR_CT             BDMA_CCR_CT_Msk                                /*!< Memory to memory mode               */

+

+/******************  Bit definition for BDMA_CNDTR register  *******************/

+#define BDMA_CNDTR_NDT_Pos      (0U)

+#define BDMA_CNDTR_NDT_Msk      (0xFFFFUL << BDMA_CNDTR_NDT_Pos)               /*!< 0x0000FFFF */

+#define BDMA_CNDTR_NDT          BDMA_CNDTR_NDT_Msk                             /*!< Number of data to Transfer          */

+

+/******************  Bit definition for BDMA_CPAR register  ********************/

+#define BDMA_CPAR_PA_Pos        (0U)

+#define BDMA_CPAR_PA_Msk        (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CPAR_PA            BDMA_CPAR_PA_Msk                               /*!< Peripheral Address                  */

+

+/******************  Bit definition for BDMA_CM0AR register  ********************/

+#define BDMA_CM0AR_MA_Pos        (0U)

+#define BDMA_CM0AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CM0AR_MA            BDMA_CM0AR_MA_Msk                               /*!< Memory Address                      */

+

+/******************  Bit definition for BDMA_CM1AR register  ********************/

+#define BDMA_CM1AR_MA_Pos        (0U)

+#define BDMA_CM1AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CM1AR_MA            BDMA_CM1AR_MA_Msk                               /*!< Memory Address                      */

+

+/******************************************************************************/

+/*                                                                            */

+/*                Ethernet MAC Registers bits definitions                     */

+/*                                                                            */

+/******************************************************************************/

+/* Bit definition for Ethernet MAC Configuration Register register */

+#define ETH_MACCR_ARP_Pos                             (31U)

+#define ETH_MACCR_ARP_Msk                             (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */

+#define ETH_MACCR_ARP                                 ETH_MACCR_ARP_Msk        /* ARP Offload Enable */

+#define ETH_MACCR_SARC_Pos                            (28U)

+#define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */

+#define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */

+#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */

+#define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)

+#define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */

+#define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */

+#define ETH_MACCR_SARC_INSADDR1_Pos                   (29U)

+#define ETH_MACCR_SARC_INSADDR1_Msk                   (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */

+#define ETH_MACCR_SARC_INSADDR1                       ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */

+#define ETH_MACCR_SARC_REPADDR0_Pos                   (28U)

+#define ETH_MACCR_SARC_REPADDR0_Msk                   (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */

+#define ETH_MACCR_SARC_REPADDR0                       ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */

+#define ETH_MACCR_SARC_REPADDR1_Pos                   (28U)

+#define ETH_MACCR_SARC_REPADDR1_Msk                   (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */

+#define ETH_MACCR_SARC_REPADDR1                       ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */

+#define ETH_MACCR_IPC_Pos                             (27U)

+#define ETH_MACCR_IPC_Msk                             (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */

+#define ETH_MACCR_IPC                                 ETH_MACCR_IPC_Msk        /* Checksum Offload */

+#define ETH_MACCR_IPG_Pos                             (24U)

+#define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */

+#define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */

+#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */

+#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */

+#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */

+#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */

+#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */

+#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */

+#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */

+#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */

+#define ETH_MACCR_GPSLCE_Pos                          (23U)

+#define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */

+#define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */

+#define ETH_MACCR_S2KP_Pos                            (22U)

+#define ETH_MACCR_S2KP_Msk                            (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */

+#define ETH_MACCR_S2KP                                ETH_MACCR_S2KP_Msk       /* IEEE 802.3as Support for 2K Packets */

+#define ETH_MACCR_CST_Pos                             (21U)

+#define ETH_MACCR_CST_Msk                             (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */

+#define ETH_MACCR_CST                                 ETH_MACCR_CST_Msk        /* CRC stripping for Type packets */

+#define ETH_MACCR_ACS_Pos                             (20U)

+#define ETH_MACCR_ACS_Msk                             (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */

+#define ETH_MACCR_ACS                                 ETH_MACCR_ACS_Msk        /* Automatic Pad or CRC Stripping */

+#define ETH_MACCR_WD_Pos                              (19U)

+#define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */

+#define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */

+#define ETH_MACCR_JD_Pos                              (17U)

+#define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */

+#define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */

+#define ETH_MACCR_JE_Pos                              (16U)

+#define ETH_MACCR_JE_Msk                              (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */

+#define ETH_MACCR_JE                                  ETH_MACCR_JE_Msk         /* Jumbo Packet Enable */

+#define ETH_MACCR_FES_Pos                             (14U)

+#define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */

+#define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */

+#define ETH_MACCR_DM_Pos                              (13U)

+#define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */

+#define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */

+#define ETH_MACCR_LM_Pos                              (12U)

+#define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */

+#define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */

+#define ETH_MACCR_ECRSFD_Pos                          (11U)

+#define ETH_MACCR_ECRSFD_Msk                          (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */

+#define ETH_MACCR_ECRSFD                              ETH_MACCR_ECRSFD_Msk     /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */

+#define ETH_MACCR_DO_Pos                              (10U)

+#define ETH_MACCR_DO_Msk                              (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */

+#define ETH_MACCR_DO                                  ETH_MACCR_DO_Msk         /* Disable Receive own  */

+#define ETH_MACCR_DCRS_Pos                            (9U)

+#define ETH_MACCR_DCRS_Msk                            (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */

+#define ETH_MACCR_DCRS                                ETH_MACCR_DCRS_Msk       /* Disable Carrier Sense During Transmission */

+#define ETH_MACCR_DR_Pos                              (8U)

+#define ETH_MACCR_DR_Msk                              (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */

+#define ETH_MACCR_DR                                  ETH_MACCR_DR_Msk         /* Disable Retry */

+#define ETH_MACCR_BL_Pos                              (5U)

+#define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */

+#define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit mask */

+#define ETH_MACCR_BL_10                               (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */

+#define ETH_MACCR_BL_8                                (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */

+#define ETH_MACCR_BL_4                                (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */

+#define ETH_MACCR_BL_1                                (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */

+#define ETH_MACCR_DC_Pos                              (4U)

+#define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */

+#define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */

+#define ETH_MACCR_PRELEN_Pos                          (2U)

+#define ETH_MACCR_PRELEN_Msk                          (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */

+#define ETH_MACCR_PRELEN                              ETH_MACCR_PRELEN_Msk     /* Preamble Length for Transmit packets */

+#define ETH_MACCR_PRELEN_7                            (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */

+#define ETH_MACCR_PRELEN_5                            (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */

+#define ETH_MACCR_PRELEN_3                            (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */

+#define ETH_MACCR_TE_Pos                              (1U)

+#define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */

+#define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */

+#define ETH_MACCR_RE_Pos                              (0U)

+#define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */

+#define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */

+

+/* Bit definition for Ethernet MAC Extended Configuration Register register */

+#define ETH_MACECR_EIPG_Pos                           (25U)

+#define ETH_MACECR_EIPG_Msk                           (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */

+#define ETH_MACECR_EIPG                               ETH_MACECR_EIPG_Msk      /* Extended Inter-Packet Gap */

+#define ETH_MACECR_EIPGEN_Pos                         (24U)

+#define ETH_MACECR_EIPGEN_Msk                         (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */

+#define ETH_MACECR_EIPGEN                             ETH_MACECR_EIPGEN_Msk    /* Extended Inter-Packet Gap Enable */

+#define ETH_MACECR_USP_Pos                            (18U)

+#define ETH_MACECR_USP_Msk                            (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */

+#define ETH_MACECR_USP                                ETH_MACECR_USP_Msk       /* Unicast Slow Protocol Packet Detect */

+#define ETH_MACECR_SPEN_Pos                           (17U)

+#define ETH_MACECR_SPEN_Msk                           (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */

+#define ETH_MACECR_SPEN                               ETH_MACECR_SPEN_Msk      /* Slow Protocol Detection Enable */

+#define ETH_MACECR_DCRCC_Pos                          (16U)

+#define ETH_MACECR_DCRCC_Msk                          (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */

+#define ETH_MACECR_DCRCC                              ETH_MACECR_DCRCC_Msk     /* Disable CRC Checking for Received Packets */

+#define ETH_MACECR_GPSL_Pos                           (0U)

+#define ETH_MACECR_GPSL_Msk                           (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */

+#define ETH_MACECR_GPSL                               ETH_MACECR_GPSL_Msk      /* Giant Packet Size Limit */

+

+/* Bit definition for Ethernet MAC Packet Filter Register */

+#define ETH_MACPFR_RA_Pos                             (31U)

+#define ETH_MACPFR_RA_Msk                             (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */

+#define ETH_MACPFR_RA                                 ETH_MACPFR_RA_Msk        /* Receive all */

+#define ETH_MACPFR_DNTU_Pos                           (21U)

+#define ETH_MACPFR_DNTU_Msk                           (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */

+#define ETH_MACPFR_DNTU                               ETH_MACPFR_DNTU_Msk      /* Drop Non-TCP/UDP over IP Packets */

+#define ETH_MACPFR_IPFE_Pos                           (20U)

+#define ETH_MACPFR_IPFE_Msk                           (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */

+#define ETH_MACPFR_IPFE                               ETH_MACPFR_IPFE_Msk      /* Layer 3 and Layer 4 Filter Enable */

+#define ETH_MACPFR_VTFE_Pos                           (16U)

+#define ETH_MACPFR_VTFE_Msk                           (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */

+#define ETH_MACPFR_VTFE                               ETH_MACPFR_VTFE_Msk      /* VLAN Tag Filter Enable */

+#define ETH_MACPFR_HPF_Pos                            (10U)

+#define ETH_MACPFR_HPF_Msk                            (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */

+#define ETH_MACPFR_HPF                                ETH_MACPFR_HPF_Msk       /* Hash or perfect filter */

+#define ETH_MACPFR_SAF_Pos                            (9U)

+#define ETH_MACPFR_SAF_Msk                            (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */

+#define ETH_MACPFR_SAF                                ETH_MACPFR_SAF_Msk       /* Source address filter enable */

+#define ETH_MACPFR_SAIF_Pos                           (8U)

+#define ETH_MACPFR_SAIF_Msk                           (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */

+#define ETH_MACPFR_SAIF                               ETH_MACPFR_SAIF_Msk      /* SA inverse filtering */

+#define ETH_MACPFR_PCF_Pos                            (6U)

+#define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */

+#define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */

+#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */

+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)

+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */

+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */

+#define ETH_MACPFR_PCF_FORWARDALL_Pos                 (7U)

+#define ETH_MACPFR_PCF_FORWARDALL_Msk                 (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */

+#define ETH_MACPFR_PCF_FORWARDALL                     ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */

+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos    (6U)

+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk    (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */

+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER        ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */

+#define ETH_MACPFR_DBF_Pos                            (5U)

+#define ETH_MACPFR_DBF_Msk                            (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */

+#define ETH_MACPFR_DBF                                ETH_MACPFR_DBF_Msk       /* Disable Broadcast Packets */

+#define ETH_MACPFR_PM_Pos                             (4U)

+#define ETH_MACPFR_PM_Msk                             (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */

+#define ETH_MACPFR_PM                                 ETH_MACPFR_PM_Msk        /* Pass all mutlicast */

+#define ETH_MACPFR_DAIF_Pos                           (3U)

+#define ETH_MACPFR_DAIF_Msk                           (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */

+#define ETH_MACPFR_DAIF                               ETH_MACPFR_DAIF_Msk      /* DA Inverse filtering */

+#define ETH_MACPFR_HMC_Pos                            (2U)

+#define ETH_MACPFR_HMC_Msk                            (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */

+#define ETH_MACPFR_HMC                                ETH_MACPFR_HMC_Msk       /* Hash multicast */

+#define ETH_MACPFR_HUC_Pos                            (1U)

+#define ETH_MACPFR_HUC_Msk                            (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */

+#define ETH_MACPFR_HUC                                ETH_MACPFR_HUC_Msk       /* Hash unicast */

+#define ETH_MACPFR_PR_Pos                             (0U)

+#define ETH_MACPFR_PR_Msk                             (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */

+#define ETH_MACPFR_PR                                 ETH_MACPFR_PR_Msk        /* Promiscuous mode */

+

+/* Bit definition for Ethernet MAC Watchdog Timeout Register */

+#define ETH_MACWTR_PWE_Pos                            (8U)

+#define ETH_MACWTR_PWE_Msk                            (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */

+#define ETH_MACWTR_PWE                                ETH_MACWTR_PWE_Msk       /* Programmable Watchdog Enable */

+#define ETH_MACWTR_WTO_Pos                            (0U)

+#define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */

+#define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */

+#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/

+#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */

+#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */

+#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */

+#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */

+#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */

+#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */

+#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */

+#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */

+#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */

+#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */

+#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */

+#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */

+#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */

+#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */

+

+/* Bit definition for Ethernet MAC Hash Table High Register */

+#define ETH_MACHTHR_HTH_Pos                           (0U)

+#define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */

+

+/* Bit definition for Ethernet MAC Hash Table Low Register */

+#define ETH_MACHTLR_HTL_Pos                           (0U)

+#define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */

+

+/* Bit definition for Ethernet MAC VLAN Tag Register */

+#define ETH_MACVTR_EIVLRXS_Pos                        (31U)

+#define ETH_MACVTR_EIVLRXS_Msk                        (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */

+#define ETH_MACVTR_EIVLRXS                            ETH_MACVTR_EIVLRXS_Msk   /* Enable Inner VLAN Tag in Rx Status */

+#define ETH_MACVTR_EIVLS_Pos                          (28U)

+#define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */

+#define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */

+#define ETH_MACVTR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */

+#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)

+#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */

+#define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */

+#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos             (29U)

+#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk             (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */

+#define ETH_MACVTR_EIVLS_STRIPIFFAILS                 ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */

+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos              (28U)

+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk              (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */

+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP                  ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */

+#define ETH_MACVTR_ERIVLT_Pos                         (27U)

+#define ETH_MACVTR_ERIVLT_Msk                         (0x1UL << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */

+#define ETH_MACVTR_ERIVLT                             ETH_MACVTR_ERIVLT_Msk    /* Enable Inner VLAN Tag */

+#define ETH_MACVTR_EDVLP_Pos                          (26U)

+#define ETH_MACVTR_EDVLP_Msk                          (0x1UL << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */

+#define ETH_MACVTR_EDVLP                              ETH_MACVTR_EDVLP_Msk     /* Enable Double VLAN Processing */

+#define ETH_MACVTR_VTHM_Pos                           (25U)

+#define ETH_MACVTR_VTHM_Msk                           (0x1UL << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */

+#define ETH_MACVTR_VTHM                               ETH_MACVTR_VTHM_Msk      /* VLAN Tag Hash Table Match Enable */

+#define ETH_MACVTR_EVLRXS_Pos                         (24U)

+#define ETH_MACVTR_EVLRXS_Msk                         (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */

+#define ETH_MACVTR_EVLRXS                             ETH_MACVTR_EVLRXS_Msk    /* Enable VLAN Tag in Rx status */

+#define ETH_MACVTR_EVLS_Pos                           (21U)

+#define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */

+#define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */

+#define ETH_MACVTR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */

+#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)

+#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */

+#define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */

+#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos              (22U)

+#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk              (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */

+#define ETH_MACVTR_EVLS_STRIPIFFAILS                  ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */

+#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos               (21U)

+#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk               (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */

+#define ETH_MACVTR_EVLS_ALWAYSSTRIP                   ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */

+#define ETH_MACVTR_DOVLTC_Pos                         (20U)

+#define ETH_MACVTR_DOVLTC_Msk                         (0x1UL << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */

+#define ETH_MACVTR_DOVLTC                             ETH_MACVTR_DOVLTC_Msk    /* Disable VLAN Type Check */

+#define ETH_MACVTR_ERSVLM_Pos                         (19U)

+#define ETH_MACVTR_ERSVLM_Msk                         (0x1UL << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */

+#define ETH_MACVTR_ERSVLM                             ETH_MACVTR_ERSVLM_Msk    /* Enable Receive S-VLAN Match */

+#define ETH_MACVTR_ESVL_Pos                           (18U)

+#define ETH_MACVTR_ESVL_Msk                           (0x1UL << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */

+#define ETH_MACVTR_ESVL                               ETH_MACVTR_ESVL_Msk      /* Enable S-VLAN */

+#define ETH_MACVTR_VTIM_Pos                           (17U)

+#define ETH_MACVTR_VTIM_Msk                           (0x1UL << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */

+#define ETH_MACVTR_VTIM                               ETH_MACVTR_VTIM_Msk      /* VLAN Tag Inverse Match Enable */

+#define ETH_MACVTR_ETV_Pos                            (16U)

+#define ETH_MACVTR_ETV_Msk                            (0x1UL << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */

+#define ETH_MACVTR_ETV                                ETH_MACVTR_ETV_Msk       /* Enable 12-Bit VLAN Tag Comparison */

+#define ETH_MACVTR_VL_Pos                             (0U)

+#define ETH_MACVTR_VL_Msk                             (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */

+#define ETH_MACVTR_VL                                 ETH_MACVTR_VL_Msk        /* VLAN Tag Identifier for Receive Packets */

+#define ETH_MACVTR_VL_UP_Pos                          (13U)

+#define ETH_MACVTR_VL_UP_Msk                          (0x7UL << ETH_MACVTR_VL_UP_Pos) /*!< 0x0000E000 */

+#define ETH_MACVTR_VL_UP                              ETH_MACVTR_VL_UP_Msk     /* User Priority */

+#define ETH_MACVTR_VL_CFIDEI_Pos                      (12U)

+#define ETH_MACVTR_VL_CFIDEI_Msk                      (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos) /*!< 0x00001000 */

+#define ETH_MACVTR_VL_CFIDEI                          ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */

+#define ETH_MACVTR_VL_VID_Pos                         (0U)

+#define ETH_MACVTR_VL_VID_Msk                         (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */

+#define ETH_MACVTR_VL_VID                             ETH_MACVTR_VL_VID_Msk    /* VLAN Identifier field of VLAN tag */

+

+/* Bit definition for Ethernet MAC VLAN Hash Table Register */

+#define ETH_MACVHTR_VLHT_Pos                          (0U)

+#define ETH_MACVHTR_VLHT_Msk                          (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACVHTR_VLHT                              ETH_MACVHTR_VLHT_Msk     /* VLAN Hash Table */

+

+/* Bit definition for Ethernet MAC VLAN Incl Register */

+#define ETH_MACVIR_VLTI_Pos                           (20U)

+#define ETH_MACVIR_VLTI_Msk                           (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */

+#define ETH_MACVIR_VLTI                               ETH_MACVIR_VLTI_Msk      /* VLAN Tag Input */

+#define ETH_MACVIR_CSVL_Pos                           (19U)

+#define ETH_MACVIR_CSVL_Msk                           (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */

+#define ETH_MACVIR_CSVL                               ETH_MACVIR_CSVL_Msk      /* C-VLAN or S-VLAN */

+#define ETH_MACVIR_VLP_Pos                            (18U)

+#define ETH_MACVIR_VLP_Msk                            (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */

+#define ETH_MACVIR_VLP                                ETH_MACVIR_VLP_Msk       /* VLAN Priority Control */

+#define ETH_MACVIR_VLC_Pos                            (16U)

+#define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */

+#define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */

+#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */

+#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)

+#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */

+#define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */

+#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos              (17U)

+#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */

+#define ETH_MACVIR_VLC_VLANTAGINSERT                  ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */

+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos             (16U)

+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk             (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */

+#define ETH_MACVIR_VLC_VLANTAGREPLACE                 ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */

+#define ETH_MACVIR_VLT_Pos                            (0U)

+#define ETH_MACVIR_VLT_Msk                            (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACVIR_VLT                                ETH_MACVIR_VLT_Msk       /* VLAN Tag for Transmit Packets */

+#define ETH_MACVIR_VLT_UP_Pos                         (13U)

+#define ETH_MACVIR_VLT_UP_Msk                         (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */

+#define ETH_MACVIR_VLT_UP                             ETH_MACVIR_VLT_UP_Msk    /* User Priority */

+#define ETH_MACVIR_VLT_CFIDEI_Pos                     (12U)

+#define ETH_MACVIR_VLT_CFIDEI_Msk                     (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */

+#define ETH_MACVIR_VLT_CFIDEI                         ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */

+#define ETH_MACVIR_VLT_VID_Pos                        (0U)

+#define ETH_MACVIR_VLT_VID_Msk                        (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */

+#define ETH_MACVIR_VLT_VID                            ETH_MACVIR_VLT_VID_Msk   /* VLAN Identifier field of VLAN tag */

+

+/* Bit definition for Ethernet MAC Inner_VLAN Incl Register */

+#define ETH_MACIVIR_VLTI_Pos                          (20U)

+#define ETH_MACIVIR_VLTI_Msk                          (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */

+#define ETH_MACIVIR_VLTI                              ETH_MACIVIR_VLTI_Msk     /* VLAN Tag Input */

+#define ETH_MACIVIR_CSVL_Pos                          (19U)

+#define ETH_MACIVIR_CSVL_Msk                          (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */

+#define ETH_MACIVIR_CSVL                              ETH_MACIVIR_CSVL_Msk     /* C-VLAN or S-VLAN */

+#define ETH_MACIVIR_VLP_Pos                           (18U)

+#define ETH_MACIVIR_VLP_Msk                           (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */

+#define ETH_MACIVIR_VLP                               ETH_MACIVIR_VLP_Msk      /* VLAN Priority Control */

+#define ETH_MACIVIR_VLC_Pos                           (16U)

+#define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */

+#define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */

+#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */

+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)

+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */

+#define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */

+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos             (17U)

+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */

+#define ETH_MACIVIR_VLC_VLANTAGINSERT                 ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */

+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos            (16U)

+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk            (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */

+#define ETH_MACIVIR_VLC_VLANTAGREPLACE                ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */

+#define ETH_MACIVIR_VLT_Pos                           (0U)

+#define ETH_MACIVIR_VLT_Msk                           (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACIVIR_VLT                               ETH_MACIVIR_VLT_Msk      /* VLAN Tag for Transmit Packets */

+#define ETH_MACIVIR_VLT_UP_Pos                        (13U)

+#define ETH_MACIVIR_VLT_UP_Msk                        (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */

+#define ETH_MACIVIR_VLT_UP                            ETH_MACIVIR_VLT_UP_Msk   /* User Priority */

+#define ETH_MACIVIR_VLT_CFIDEI_Pos                    (12U)

+#define ETH_MACIVIR_VLT_CFIDEI_Msk                    (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */

+#define ETH_MACIVIR_VLT_CFIDEI                        ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */

+#define ETH_MACIVIR_VLT_VID_Pos                       (0U)

+#define ETH_MACIVIR_VLT_VID_Msk                       (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */

+#define ETH_MACIVIR_VLT_VID                           ETH_MACIVIR_VLT_VID_Msk  /* VLAN Identifier field of VLAN tag */

+

+/* Bit definition for Ethernet MAC Tx Flow Ctrl Register */

+#define ETH_MACTFCR_PT_Pos                            (16U)

+#define ETH_MACTFCR_PT_Msk                            (0xFFFFUL << ETH_MACTFCR_PT_Pos) /*!< 0xFFFF0000 */

+#define ETH_MACTFCR_PT                                ETH_MACTFCR_PT_Msk       /* Pause Time */

+#define ETH_MACTFCR_DZPQ_Pos                          (7U)

+#define ETH_MACTFCR_DZPQ_Msk                          (0x1UL << ETH_MACTFCR_DZPQ_Pos) /*!< 0x00000080 */

+#define ETH_MACTFCR_DZPQ                              ETH_MACTFCR_DZPQ_Msk     /* Disable Zero-Quanta Pause */

+#define ETH_MACTFCR_PLT_Pos                           (4U)

+#define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */

+#define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */

+#define ETH_MACTFCR_PLT_MINUS4                        ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */

+#define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)

+#define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */

+#define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */

+#define ETH_MACTFCR_PLT_MINUS36_Pos                   (5U)

+#define ETH_MACTFCR_PLT_MINUS36_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */

+#define ETH_MACTFCR_PLT_MINUS36                       ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */

+#define ETH_MACTFCR_PLT_MINUS144_Pos                  (4U)

+#define ETH_MACTFCR_PLT_MINUS144_Msk                  (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */

+#define ETH_MACTFCR_PLT_MINUS144                      ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */

+#define ETH_MACTFCR_PLT_MINUS256_Pos                  (6U)

+#define ETH_MACTFCR_PLT_MINUS256_Msk                  (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */

+#define ETH_MACTFCR_PLT_MINUS256                      ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */

+#define ETH_MACTFCR_PLT_MINUS512_Pos                  (4U)

+#define ETH_MACTFCR_PLT_MINUS512_Msk                  (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */

+#define ETH_MACTFCR_PLT_MINUS512                      ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */

+#define ETH_MACTFCR_TFE_Pos                           (1U)

+#define ETH_MACTFCR_TFE_Msk                           (0x1UL << ETH_MACTFCR_TFE_Pos) /*!< 0x00000002 */

+#define ETH_MACTFCR_TFE                               ETH_MACTFCR_TFE_Msk      /* Transmit Flow Control Enable */

+#define ETH_MACTFCR_FCB_Pos                           (0U)

+#define ETH_MACTFCR_FCB_Msk                           (0x1UL << ETH_MACTFCR_FCB_Pos) /*!< 0x00000001 */

+#define ETH_MACTFCR_FCB                               ETH_MACTFCR_FCB_Msk      /* Flow Control Busy or Backpressure Activate */

+

+/* Bit definition for Ethernet MAC Rx Flow Ctrl Register */

+#define ETH_MACRFCR_UP_Pos                            (1U)

+#define ETH_MACRFCR_UP_Msk                            (0x1UL << ETH_MACRFCR_UP_Pos) /*!< 0x00000002 */

+#define ETH_MACRFCR_UP                                ETH_MACRFCR_UP_Msk       /* Unicast Pause Packet Detect */

+#define ETH_MACRFCR_RFE_Pos                           (0U)

+#define ETH_MACRFCR_RFE_Msk                           (0x1UL << ETH_MACRFCR_RFE_Pos) /*!< 0x00000001 */

+#define ETH_MACRFCR_RFE                               ETH_MACRFCR_RFE_Msk      /* Receive Flow Control Enable */

+

+/* Bit definition for Ethernet MAC Interrupt Status Register */

+#define ETH_MACISR_RXSTSIS_Pos                        (14U)

+#define ETH_MACISR_RXSTSIS_Msk                        (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */

+#define ETH_MACISR_RXSTSIS                            ETH_MACISR_RXSTSIS_Msk   /* Receive Status Interrupt */

+#define ETH_MACISR_TXSTSIS_Pos                        (13U)

+#define ETH_MACISR_TXSTSIS_Msk                        (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */

+#define ETH_MACISR_TXSTSIS                            ETH_MACISR_TXSTSIS_Msk   /* Transmit Status Interrupt */

+#define ETH_MACISR_TSIS_Pos                           (12U)

+#define ETH_MACISR_TSIS_Msk                           (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */

+#define ETH_MACISR_TSIS                               ETH_MACISR_TSIS_Msk      /* Timestamp Interrupt Status */

+#define ETH_MACISR_MMCTXIS_Pos                        (10U)

+#define ETH_MACISR_MMCTXIS_Msk                        (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */

+#define ETH_MACISR_MMCTXIS                            ETH_MACISR_MMCTXIS_Msk   /* MMC Transmit Interrupt Status */

+#define ETH_MACISR_MMCRXIS_Pos                        (9U)

+#define ETH_MACISR_MMCRXIS_Msk                        (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */

+#define ETH_MACISR_MMCRXIS                            ETH_MACISR_MMCRXIS_Msk   /* MMC Receive Interrupt Status */

+#define ETH_MACISR_MMCIS_Pos                          (8U)

+#define ETH_MACISR_MMCIS_Msk                          (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */

+#define ETH_MACISR_MMCIS                              ETH_MACISR_MMCIS_Msk     /* MMC Interrupt Status */

+#define ETH_MACISR_LPIIS_Pos                          (5U)

+#define ETH_MACISR_LPIIS_Msk                          (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */

+#define ETH_MACISR_LPIIS                              ETH_MACISR_LPIIS_Msk     /* LPI Interrupt Status */

+#define ETH_MACISR_PMTIS_Pos                          (4U)

+#define ETH_MACISR_PMTIS_Msk                          (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */

+#define ETH_MACISR_PMTIS                              ETH_MACISR_PMTIS_Msk     /* PMT Interrupt Status */

+#define ETH_MACISR_PHYIS_Pos                          (3U)

+#define ETH_MACISR_PHYIS_Msk                          (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */

+#define ETH_MACISR_PHYIS                              ETH_MACISR_PHYIS_Msk     /* PHY Interrupt */

+

+/* Bit definition for Ethernet MAC Interrupt Enable Register */

+#define ETH_MACIER_RXSTSIE_Pos                        (14U)

+#define ETH_MACIER_RXSTSIE_Msk                        (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */

+#define ETH_MACIER_RXSTSIE                            ETH_MACIER_RXSTSIE_Msk   /* Receive Status Interrupt Enable */

+#define ETH_MACIER_TXSTSIE_Pos                        (13U)

+#define ETH_MACIER_TXSTSIE_Msk                        (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */

+#define ETH_MACIER_TXSTSIE                            ETH_MACIER_TXSTSIE_Msk   /* Transmit Status Interrupt Enable */

+#define ETH_MACIER_TSIE_Pos                           (12U)

+#define ETH_MACIER_TSIE_Msk                           (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */

+#define ETH_MACIER_TSIE                               ETH_MACIER_TSIE_Msk      /* Timestamp Interrupt Enable */

+#define ETH_MACIER_LPIIE_Pos                          (5U)

+#define ETH_MACIER_LPIIE_Msk                          (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */

+#define ETH_MACIER_LPIIE                              ETH_MACIER_LPIIE_Msk     /* LPI Interrupt Enable */

+#define ETH_MACIER_PMTIE_Pos                          (4U)

+#define ETH_MACIER_PMTIE_Msk                          (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */

+#define ETH_MACIER_PMTIE                              ETH_MACIER_PMTIE_Msk     /* PMT Interrupt Enable */

+#define ETH_MACIER_PHYIE_Pos                          (3U)

+#define ETH_MACIER_PHYIE_Msk                          (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */

+#define ETH_MACIER_PHYIE                              ETH_MACIER_PHYIE_Msk     /* PHY Interrupt Enable */

+

+/* Bit definition for Ethernet MAC Rx Tx Status Register */

+#define ETH_MACRXTXSR_RWT_Pos                         (8U)

+#define ETH_MACRXTXSR_RWT_Msk                         (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */

+#define ETH_MACRXTXSR_RWT                             ETH_MACRXTXSR_RWT_Msk    /* Receive Watchdog Timeout */

+#define ETH_MACRXTXSR_EXCOL_Pos                       (5U)

+#define ETH_MACRXTXSR_EXCOL_Msk                       (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */

+#define ETH_MACRXTXSR_EXCOL                           ETH_MACRXTXSR_EXCOL_Msk  /* Excessive Collisions */

+#define ETH_MACRXTXSR_LCOL_Pos                        (4U)

+#define ETH_MACRXTXSR_LCOL_Msk                        (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */

+#define ETH_MACRXTXSR_LCOL                            ETH_MACRXTXSR_LCOL_Msk   /* Late Collision */

+#define ETH_MACRXTXSR_EXDEF_Pos                       (3U)

+#define ETH_MACRXTXSR_EXDEF_Msk                       (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */

+#define ETH_MACRXTXSR_EXDEF                           ETH_MACRXTXSR_EXDEF_Msk  /* Excessive Deferral */

+#define ETH_MACRXTXSR_LCARR_Pos                       (2U)

+#define ETH_MACRXTXSR_LCARR_Msk                       (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */

+#define ETH_MACRXTXSR_LCARR                           ETH_MACRXTXSR_LCARR_Msk  /* Loss of Carrier */

+#define ETH_MACRXTXSR_NCARR_Pos                       (1U)

+#define ETH_MACRXTXSR_NCARR_Msk                       (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */

+#define ETH_MACRXTXSR_NCARR                           ETH_MACRXTXSR_NCARR_Msk  /* No Carrier */

+#define ETH_MACRXTXSR_TJT_Pos                         (0U)

+#define ETH_MACRXTXSR_TJT_Msk                         (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */

+#define ETH_MACRXTXSR_TJT                             ETH_MACRXTXSR_TJT_Msk    /* Transmit Jabber Timeout */

+

+/* Bit definition for Ethernet MAC PMT Control Status Register */

+#define ETH_MACPCSR_RWKFILTRST_Pos                    (31U)

+#define ETH_MACPCSR_RWKFILTRST_Msk                    (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */

+#define ETH_MACPCSR_RWKFILTRST                        ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */

+#define ETH_MACPCSR_RWKPTR_Pos                        (24U)

+#define ETH_MACPCSR_RWKPTR_Msk                        (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */

+#define ETH_MACPCSR_RWKPTR                            ETH_MACPCSR_RWKPTR_Msk   /* Remote Wake-up FIFO Pointer */

+#define ETH_MACPCSR_RWKPFE_Pos                        (10U)

+#define ETH_MACPCSR_RWKPFE_Msk                        (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */

+#define ETH_MACPCSR_RWKPFE                            ETH_MACPCSR_RWKPFE_Msk   /* Remote Wake-up Packet Forwarding Enable */

+#define ETH_MACPCSR_GLBLUCAST_Pos                     (9U)

+#define ETH_MACPCSR_GLBLUCAST_Msk                     (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */

+#define ETH_MACPCSR_GLBLUCAST                         ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */

+#define ETH_MACPCSR_RWKPRCVD_Pos                      (6U)

+#define ETH_MACPCSR_RWKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */

+#define ETH_MACPCSR_RWKPRCVD                          ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */

+#define ETH_MACPCSR_MGKPRCVD_Pos                      (5U)

+#define ETH_MACPCSR_MGKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */

+#define ETH_MACPCSR_MGKPRCVD                          ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */

+#define ETH_MACPCSR_RWKPKTEN_Pos                      (2U)

+#define ETH_MACPCSR_RWKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */

+#define ETH_MACPCSR_RWKPKTEN                          ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */

+#define ETH_MACPCSR_MGKPKTEN_Pos                      (1U)

+#define ETH_MACPCSR_MGKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */

+#define ETH_MACPCSR_MGKPKTEN                          ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */

+#define ETH_MACPCSR_PWRDWN_Pos                        (0U)

+#define ETH_MACPCSR_PWRDWN_Msk                        (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */

+#define ETH_MACPCSR_PWRDWN                            ETH_MACPCSR_PWRDWN_Msk   /* Power Down */

+

+/* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */

+#define ETH_MACRWUPFR_D_Pos                           (0U)

+#define ETH_MACRWUPFR_D_Msk                           (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACRWUPFR_D                               ETH_MACRWUPFR_D_Msk      /* Wake-up Packet filter register data */

+

+/* Bit definition for Ethernet MAC LPI Control Status Register */

+#define ETH_MACLCSR_LPITCSE_Pos                       (21U)

+#define ETH_MACLCSR_LPITCSE_Msk                       (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */

+#define ETH_MACLCSR_LPITCSE                           ETH_MACLCSR_LPITCSE_Msk  /* LPI Tx Clock Stop Enable */

+#define ETH_MACLCSR_LPITE_Pos                         (20U)

+#define ETH_MACLCSR_LPITE_Msk                         (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */

+#define ETH_MACLCSR_LPITE                             ETH_MACLCSR_LPITE_Msk    /* LPI Timer Enable */

+#define ETH_MACLCSR_LPITXA_Pos                        (19U)

+#define ETH_MACLCSR_LPITXA_Msk                        (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */

+#define ETH_MACLCSR_LPITXA                            ETH_MACLCSR_LPITXA_Msk   /* LPI Tx Automate */

+#define ETH_MACLCSR_PLS_Pos                           (17U)

+#define ETH_MACLCSR_PLS_Msk                           (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */

+#define ETH_MACLCSR_PLS                               ETH_MACLCSR_PLS_Msk      /* PHY Link Status */

+#define ETH_MACLCSR_LPIEN_Pos                         (16U)

+#define ETH_MACLCSR_LPIEN_Msk                         (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */

+#define ETH_MACLCSR_LPIEN                             ETH_MACLCSR_LPIEN_Msk    /* LPI Enable */

+#define ETH_MACLCSR_RLPIST_Pos                        (9U)

+#define ETH_MACLCSR_RLPIST_Msk                        (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */

+#define ETH_MACLCSR_RLPIST                            ETH_MACLCSR_RLPIST_Msk   /* Receive LPI State */

+#define ETH_MACLCSR_TLPIST_Pos                        (8U)

+#define ETH_MACLCSR_TLPIST_Msk                        (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */

+#define ETH_MACLCSR_TLPIST                            ETH_MACLCSR_TLPIST_Msk   /* Transmit LPI State */

+#define ETH_MACLCSR_RLPIEX_Pos                        (3U)

+#define ETH_MACLCSR_RLPIEX_Msk                        (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */

+#define ETH_MACLCSR_RLPIEX                            ETH_MACLCSR_RLPIEX_Msk   /* Receive LPI Exit */

+#define ETH_MACLCSR_RLPIEN_Pos                        (2U)

+#define ETH_MACLCSR_RLPIEN_Msk                        (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */

+#define ETH_MACLCSR_RLPIEN                            ETH_MACLCSR_RLPIEN_Msk   /* Receive LPI Entry */

+#define ETH_MACLCSR_TLPIEX_Pos                        (1U)

+#define ETH_MACLCSR_TLPIEX_Msk                        (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */

+#define ETH_MACLCSR_TLPIEX                            ETH_MACLCSR_TLPIEX_Msk   /* Transmit LPI Exit */

+#define ETH_MACLCSR_TLPIEN_Pos                        (0U)

+#define ETH_MACLCSR_TLPIEN_Msk                        (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */

+#define ETH_MACLCSR_TLPIEN                            ETH_MACLCSR_TLPIEN_Msk   /* Transmit LPI Entry */

+

+/* Bit definition for Ethernet MAC LPI Timers Control Register */

+#define ETH_MACLTCR_LST_Pos                           (16U)

+#define ETH_MACLTCR_LST_Msk                           (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */

+#define ETH_MACLTCR_LST                               ETH_MACLTCR_LST_Msk      /* LPI LS TIMER */

+#define ETH_MACLTCR_TWT_Pos                           (0U)

+#define ETH_MACLTCR_TWT_Msk                           (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACLTCR_TWT                               ETH_MACLTCR_TWT_Msk      /* LPI TW TIMER */

+

+/* Bit definition for Ethernet MAC LPI Entry Timer Register */

+#define ETH_MACLETR_LPIET_Pos                         (0U)

+#define ETH_MACLETR_LPIET_Msk                         (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */

+#define ETH_MACLETR_LPIET                             ETH_MACLETR_LPIET_Msk    /* LPI Entry Timer */

+

+/* Bit definition for Ethernet MAC 1US Tic Counter Register */

+#define ETH_MAC1USTCR_TIC1USCNTR_Pos                  (0U)

+#define ETH_MAC1USTCR_TIC1USCNTR_Msk                  (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */

+#define ETH_MAC1USTCR_TIC1USCNTR                      ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */

+

+/* Bit definition for Ethernet MAC Version Register */

+#define ETH_MACVR_USERVER_Pos                         (8U)

+#define ETH_MACVR_USERVER_Msk                         (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */

+#define ETH_MACVR_USERVER                             ETH_MACVR_USERVER_Msk    /* User-defined Version */

+#define ETH_MACVR_SNPSVER_Pos                         (0U)

+#define ETH_MACVR_SNPSVER_Msk                         (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */

+#define ETH_MACVR_SNPSVER                             ETH_MACVR_SNPSVER_Msk    /* Synopsys-defined Version */

+

+/* Bit definition for Ethernet MAC Debug Register */

+#define ETH_MACDR_TFCSTS_Pos                          (17U)

+#define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */

+#define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */

+#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */

+#define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)

+#define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */

+#define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */

+#define ETH_MACDR_TFCSTS_GENERATEPCP_Pos              (18U)

+#define ETH_MACDR_TFCSTS_GENERATEPCP_Msk              (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */

+#define ETH_MACDR_TFCSTS_GENERATEPCP                  ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */

+#define ETH_MACDR_TFCSTS_TRASFERIP_Pos                (17U)

+#define ETH_MACDR_TFCSTS_TRASFERIP_Msk                (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */

+#define ETH_MACDR_TFCSTS_TRASFERIP                    ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */

+#define ETH_MACDR_TPESTS_Pos                          (16U)

+#define ETH_MACDR_TPESTS_Msk                          (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */

+#define ETH_MACDR_TPESTS                              ETH_MACDR_TPESTS_Msk     /* MAC Receive Packet Controller FIFO Status */

+#define ETH_MACDR_RFCFCSTS_Pos                        (1U)

+#define ETH_MACDR_RFCFCSTS_Msk                        (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */

+#define ETH_MACDR_RFCFCSTS                            ETH_MACDR_RFCFCSTS_Msk   /* MAC MII Transmit Protocol Engine Status */

+#define ETH_MACDR_RPESTS_Pos                          (0U)

+#define ETH_MACDR_RPESTS_Msk                          (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */

+#define ETH_MACDR_RPESTS                              ETH_MACDR_RPESTS_Msk     /* MAC MII Receive Protocol Engine Status */

+

+/* Bit definition for Ethernet MAC HW Feature0 Register */

+#define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)

+#define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */

+#define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */

+#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */

+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)

+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */

+#define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */

+#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos             (28U)

+#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk             (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos) /*!< 0x70000000 */

+#define ETH_MACHWF0R_ACTPHYSEL_REVMII                 ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */

+#define ETH_MACHWF0R_SAVLANINS_Pos                    (27U)

+#define ETH_MACHWF0R_SAVLANINS_Msk                    (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */

+#define ETH_MACHWF0R_SAVLANINS                        ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */

+#define ETH_MACHWF0R_TSSTSSEL_Pos                     (25U)

+#define ETH_MACHWF0R_TSSTSSEL_Msk                     (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */

+#define ETH_MACHWF0R_TSSTSSEL                         ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */

+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos            (25U)

+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */

+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL                ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */

+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos            (26U)

+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */

+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL                ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */

+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos                (25U)

+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk                (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */

+#define ETH_MACHWF0R_TSSTSSEL_BOTH                    ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */

+#define ETH_MACHWF0R_MACADR64SEL_Pos                  (24U)

+#define ETH_MACHWF0R_MACADR64SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */

+#define ETH_MACHWF0R_MACADR64SEL                      ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */

+#define ETH_MACHWF0R_MACADR32SEL_Pos                  (23U)

+#define ETH_MACHWF0R_MACADR32SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */

+#define ETH_MACHWF0R_MACADR32SEL                      ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */

+#define ETH_MACHWF0R_ADDMACADRSEL_Pos                 (18U)

+#define ETH_MACHWF0R_ADDMACADRSEL_Msk                 (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */

+#define ETH_MACHWF0R_ADDMACADRSEL                     ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */

+#define ETH_MACHWF0R_RXCOESEL_Pos                     (16U)

+#define ETH_MACHWF0R_RXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */

+#define ETH_MACHWF0R_RXCOESEL                         ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */

+#define ETH_MACHWF0R_TXCOESEL_Pos                     (14U)

+#define ETH_MACHWF0R_TXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */

+#define ETH_MACHWF0R_TXCOESEL                         ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */

+#define ETH_MACHWF0R_EEESEL_Pos                       (13U)

+#define ETH_MACHWF0R_EEESEL_Msk                       (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */

+#define ETH_MACHWF0R_EEESEL                           ETH_MACHWF0R_EEESEL_Msk  /* Energy Efficient Ethernet Enabled */

+#define ETH_MACHWF0R_TSSEL_Pos                        (12U)

+#define ETH_MACHWF0R_TSSEL_Msk                        (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */

+#define ETH_MACHWF0R_TSSEL                            ETH_MACHWF0R_TSSEL_Msk   /* IEEE 1588-2008 Timestamp Enabled */

+#define ETH_MACHWF0R_ARPOFFSEL_Pos                    (9U)

+#define ETH_MACHWF0R_ARPOFFSEL_Msk                    (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */

+#define ETH_MACHWF0R_ARPOFFSEL                        ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */

+#define ETH_MACHWF0R_MMCSEL_Pos                       (8U)

+#define ETH_MACHWF0R_MMCSEL_Msk                       (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */

+#define ETH_MACHWF0R_MMCSEL                           ETH_MACHWF0R_MMCSEL_Msk  /* RMON Module Enable */

+#define ETH_MACHWF0R_MGKSEL_Pos                       (7U)

+#define ETH_MACHWF0R_MGKSEL_Msk                       (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */

+#define ETH_MACHWF0R_MGKSEL                           ETH_MACHWF0R_MGKSEL_Msk  /* PMT Magic Packet Enable */

+#define ETH_MACHWF0R_RWKSEL_Pos                       (6U)

+#define ETH_MACHWF0R_RWKSEL_Msk                       (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */

+#define ETH_MACHWF0R_RWKSEL                           ETH_MACHWF0R_RWKSEL_Msk  /* PMT Remote Wake-up Packet Enable */

+#define ETH_MACHWF0R_SMASEL_Pos                       (5U)

+#define ETH_MACHWF0R_SMASEL_Msk                       (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */

+#define ETH_MACHWF0R_SMASEL                           ETH_MACHWF0R_SMASEL_Msk  /* SMA (MDIO) Interface */

+#define ETH_MACHWF0R_VLHASH_Pos                       (4U)

+#define ETH_MACHWF0R_VLHASH_Msk                       (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */

+#define ETH_MACHWF0R_VLHASH                           ETH_MACHWF0R_VLHASH_Msk  /* VLAN Hash Filter Selected */

+#define ETH_MACHWF0R_PCSSEL_Pos                       (3U)

+#define ETH_MACHWF0R_PCSSEL_Msk                       (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */

+#define ETH_MACHWF0R_PCSSEL                           ETH_MACHWF0R_PCSSEL_Msk  /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */

+#define ETH_MACHWF0R_HDSEL_Pos                        (2U)

+#define ETH_MACHWF0R_HDSEL_Msk                        (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */

+#define ETH_MACHWF0R_HDSEL                            ETH_MACHWF0R_HDSEL_Msk   /* Half-duplex Support */

+#define ETH_MACHWF0R_GMIISEL_Pos                      (1U)

+#define ETH_MACHWF0R_GMIISEL_Msk                      (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */

+#define ETH_MACHWF0R_GMIISEL                          ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */

+#define ETH_MACHWF0R_MIISEL_Pos                       (0U)

+#define ETH_MACHWF0R_MIISEL_Msk                       (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */

+#define ETH_MACHWF0R_MIISEL                           ETH_MACHWF0R_MIISEL_Msk  /* 10 or 100 Mbps Support */

+

+/* Bit definition for Ethernet MAC HW Feature1 Register */

+#define ETH_MACHWF1R_L3L4FNUM_Pos                     (27U)

+#define ETH_MACHWF1R_L3L4FNUM_Msk                     (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */

+#define ETH_MACHWF1R_L3L4FNUM                         ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */

+#define ETH_MACHWF1R_HASHTBLSZ_Pos                    (24U)

+#define ETH_MACHWF1R_HASHTBLSZ_Msk                    (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */

+#define ETH_MACHWF1R_HASHTBLSZ                        ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */

+#define ETH_MACHWF1R_AVSEL_Pos                        (20U)

+#define ETH_MACHWF1R_AVSEL_Msk                        (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */

+#define ETH_MACHWF1R_AVSEL                            ETH_MACHWF1R_AVSEL_Msk   /* AV Feature Enabled */

+#define ETH_MACHWF1R_DBGMEMA_Pos                      (19U)

+#define ETH_MACHWF1R_DBGMEMA_Msk                      (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */

+#define ETH_MACHWF1R_DBGMEMA                          ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */

+#define ETH_MACHWF1R_TSOEN_Pos                        (18U)

+#define ETH_MACHWF1R_TSOEN_Msk                        (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */

+#define ETH_MACHWF1R_TSOEN                            ETH_MACHWF1R_TSOEN_Msk   /* TCP Segmentation Offload Enable */

+#define ETH_MACHWF1R_SPHEN_Pos                        (17U)

+#define ETH_MACHWF1R_SPHEN_Msk                        (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */

+#define ETH_MACHWF1R_SPHEN                            ETH_MACHWF1R_SPHEN_Msk   /* Split Header Feature Enable */

+#define ETH_MACHWF1R_DCBEN_Pos                        (16U)

+#define ETH_MACHWF1R_DCBEN_Msk                        (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */

+#define ETH_MACHWF1R_DCBEN                            ETH_MACHWF1R_DCBEN_Msk   /* DCB Feature Enable */

+#define ETH_MACHWF1R_ADDR64_Pos                       (14U)

+#define ETH_MACHWF1R_ADDR64_Msk                       (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */

+#define ETH_MACHWF1R_ADDR64                           ETH_MACHWF1R_ADDR64_Msk  /* Address Width */

+#define ETH_MACHWF1R_ADDR64_32                        (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */

+#define ETH_MACHWF1R_ADDR64_40                        (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */

+#define ETH_MACHWF1R_ADDR64_48                        (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */

+#define ETH_MACHWF1R_ADVTHWORD_Pos                    (13U)

+#define ETH_MACHWF1R_ADVTHWORD_Msk                    (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */

+#define ETH_MACHWF1R_ADVTHWORD                        ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */

+#define ETH_MACHWF1R_PTOEN_Pos                        (12U)

+#define ETH_MACHWF1R_PTOEN_Msk                        (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */

+#define ETH_MACHWF1R_PTOEN                            ETH_MACHWF1R_PTOEN_Msk   /* PTP Offload Enable */

+#define ETH_MACHWF1R_OSTEN_Pos                        (11U)

+#define ETH_MACHWF1R_OSTEN_Msk                        (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */

+#define ETH_MACHWF1R_OSTEN                            ETH_MACHWF1R_OSTEN_Msk   /* One-Step Timestamping Enable */

+#define ETH_MACHWF1R_TXFIFOSIZE_Pos                   (6U)

+#define ETH_MACHWF1R_TXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */

+#define ETH_MACHWF1R_TXFIFOSIZE                       ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */

+#define ETH_MACHWF1R_RXFIFOSIZE_Pos                   (0U)

+#define ETH_MACHWF1R_RXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */

+#define ETH_MACHWF1R_RXFIFOSIZE                       ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */

+

+/* Bit definition for Ethernet MAC HW Feature2 Register */

+#define ETH_MACHWF2R_AUXSNAPNUM_Pos                   (28U)

+#define ETH_MACHWF2R_AUXSNAPNUM_Msk                   (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */

+#define ETH_MACHWF2R_AUXSNAPNUM                       ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */

+#define ETH_MACHWF2R_PPSOUTNUM_Pos                    (24U)

+#define ETH_MACHWF2R_PPSOUTNUM_Msk                    (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */

+#define ETH_MACHWF2R_PPSOUTNUM                        ETH_MACHWF2R_PPSOUTNUM_Msk /*  Number of PPS Outputs */

+#define ETH_MACHWF2R_TXCHCNT_Pos                      (18U)

+#define ETH_MACHWF2R_TXCHCNT_Msk                      (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */

+#define ETH_MACHWF2R_TXCHCNT                          ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */

+#define ETH_MACHWF2R_RXCHCNT_Pos                      (13U)

+#define ETH_MACHWF2R_RXCHCNT_Msk                      (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000E000 */

+#define ETH_MACHWF2R_RXCHCNT                          ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */

+#define ETH_MACHWF2R_TXQCNT_Pos                       (6U)

+#define ETH_MACHWF2R_TXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */

+#define ETH_MACHWF2R_TXQCNT                           ETH_MACHWF2R_TXQCNT_Msk  /* Number of MTL Transmit Queues */

+#define ETH_MACHWF2R_RXQCNT_Pos                       (0U)

+#define ETH_MACHWF2R_RXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */

+#define ETH_MACHWF2R_RXQCNT                           ETH_MACHWF2R_RXQCNT_Msk  /* Number of MTL Receive Queues */

+

+/* Bit definition for Ethernet MAC MDIO Address Register */

+#define ETH_MACMDIOAR_PSE_Pos                         (27U)

+#define ETH_MACMDIOAR_PSE_Msk                         (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */

+#define ETH_MACMDIOAR_PSE                             ETH_MACMDIOAR_PSE_Msk    /* Preamble Suppression Enable */

+#define ETH_MACMDIOAR_BTB_Pos                         (26U)

+#define ETH_MACMDIOAR_BTB_Msk                         (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */

+#define ETH_MACMDIOAR_BTB                             ETH_MACMDIOAR_BTB_Msk    /* Back to Back transactions */

+#define ETH_MACMDIOAR_PA_Pos                          (21U)

+#define ETH_MACMDIOAR_PA_Msk                          (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */

+#define ETH_MACMDIOAR_PA                              ETH_MACMDIOAR_PA_Msk     /* Physical Layer Address */

+#define ETH_MACMDIOAR_RDA_Pos                         (16U)

+#define ETH_MACMDIOAR_RDA_Msk                         (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */

+#define ETH_MACMDIOAR_RDA                             ETH_MACMDIOAR_RDA_Msk    /* Register/Device Address */

+#define ETH_MACMDIOAR_NTC_Pos                         (12U)

+#define ETH_MACMDIOAR_NTC_Msk                         (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */

+#define ETH_MACMDIOAR_NTC                             ETH_MACMDIOAR_NTC_Msk    /* Number of Trailing Clocks */

+#define ETH_MACMDIOAR_CR_Pos                          (8U)

+#define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */

+#define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */

+#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */

+#define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)

+#define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */

+#define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */

+#define ETH_MACMDIOAR_CR_DIV16_Pos                    (9U)

+#define ETH_MACMDIOAR_CR_DIV16_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */

+#define ETH_MACMDIOAR_CR_DIV16                        ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */

+#define ETH_MACMDIOAR_CR_DIV26_Pos                    (8U)

+#define ETH_MACMDIOAR_CR_DIV26_Msk                    (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */

+#define ETH_MACMDIOAR_CR_DIV26                        ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */

+#define ETH_MACMDIOAR_CR_DIV102_Pos                   (10U)

+#define ETH_MACMDIOAR_CR_DIV102_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */

+#define ETH_MACMDIOAR_CR_DIV102                       ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */

+#define ETH_MACMDIOAR_CR_DIV124_Pos                   (8U)

+#define ETH_MACMDIOAR_CR_DIV124_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */

+#define ETH_MACMDIOAR_CR_DIV124                       ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */

+#define ETH_MACMDIOAR_CR_DIV4AR_Pos                   (11U)

+#define ETH_MACMDIOAR_CR_DIV4AR_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */

+#define ETH_MACMDIOAR_CR_DIV4AR                       ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV6AR_Pos                   (8U)

+#define ETH_MACMDIOAR_CR_DIV6AR_Msk                   (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */

+#define ETH_MACMDIOAR_CR_DIV6AR                       ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV8AR_Pos                   (9U)

+#define ETH_MACMDIOAR_CR_DIV8AR_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */

+#define ETH_MACMDIOAR_CR_DIV8AR                       ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV10AR_Pos                  (8U)

+#define ETH_MACMDIOAR_CR_DIV10AR_Msk                  (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */

+#define ETH_MACMDIOAR_CR_DIV10AR                      ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV12AR_Pos                  (10U)

+#define ETH_MACMDIOAR_CR_DIV12AR_Msk                  (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */

+#define ETH_MACMDIOAR_CR_DIV12AR                      ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV14AR_Pos                  (8U)

+#define ETH_MACMDIOAR_CR_DIV14AR_Msk                  (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */

+#define ETH_MACMDIOAR_CR_DIV14AR                      ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV16AR_Pos                  (9U)

+#define ETH_MACMDIOAR_CR_DIV16AR_Msk                  (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */

+#define ETH_MACMDIOAR_CR_DIV16AR                      ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV18AR_Pos                  (8U)

+#define ETH_MACMDIOAR_CR_DIV18AR_Msk                  (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */

+#define ETH_MACMDIOAR_CR_DIV18AR                      ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_SKAP_Pos                        (4U)

+#define ETH_MACMDIOAR_SKAP_Msk                        (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */

+#define ETH_MACMDIOAR_SKAP                            ETH_MACMDIOAR_SKAP_Msk   /* Skip Address Packet */

+#define ETH_MACMDIOAR_MOC_Pos                         (2U)

+#define ETH_MACMDIOAR_MOC_Msk                         (0x3UL << ETH_MACMDIOAR_MOC_Pos) /*!< 0x0000000C */

+#define ETH_MACMDIOAR_MOC                             ETH_MACMDIOAR_MOC_Msk    /* MII Operation Command */

+#define ETH_MACMDIOAR_MOC_WR_Pos                      (2U)

+#define ETH_MACMDIOAR_MOC_WR_Msk                      (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos) /*!< 0x00000004 */

+#define ETH_MACMDIOAR_MOC_WR                          ETH_MACMDIOAR_MOC_WR_Msk /* Write */

+#define ETH_MACMDIOAR_MOC_PRDIA_Pos                   (3U)

+#define ETH_MACMDIOAR_MOC_PRDIA_Msk                   (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos) /*!< 0x00000008 */

+#define ETH_MACMDIOAR_MOC_PRDIA                       ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */

+#define ETH_MACMDIOAR_MOC_RD_Pos                      (2U)

+#define ETH_MACMDIOAR_MOC_RD_Msk                      (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos) /*!< 0x0000000C */

+#define ETH_MACMDIOAR_MOC_RD                          ETH_MACMDIOAR_MOC_RD_Msk /* Read */

+#define ETH_MACMDIOAR_C45E_Pos                        (1U)

+#define ETH_MACMDIOAR_C45E_Msk                        (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */

+#define ETH_MACMDIOAR_C45E                            ETH_MACMDIOAR_C45E_Msk   /* Clause 45 PHY Enable */

+#define ETH_MACMDIOAR_MB_Pos                          (0U)

+#define ETH_MACMDIOAR_MB_Msk                          (0x1UL << ETH_MACMDIOAR_MB_Pos) /*!< 0x00000001 */

+#define ETH_MACMDIOAR_MB                              ETH_MACMDIOAR_MB_Msk     /* MII Busy */

+

+/* Bit definition for Ethernet MAC MDIO Data Register */

+#define ETH_MACMDIODR_RA_Pos                          (16U)

+#define ETH_MACMDIODR_RA_Msk                          (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */

+#define ETH_MACMDIODR_RA                              ETH_MACMDIODR_RA_Msk     /* Register Address */

+#define ETH_MACMDIODR_MD_Pos                          (0U)

+#define ETH_MACMDIODR_MD_Msk                          (0xFFFFUL << ETH_MACMDIODR_MD_Pos) /*!< 0x0000FFFF */

+#define ETH_MACMDIODR_MD                              ETH_MACMDIODR_MD_Msk     /* MII Data */

+

+/* Bit definition for Ethernet ARP Address Register */

+#define ETH_MACARPAR_ARPPA_Pos                         (0U)

+#define ETH_MACARPAR_ARPPA_Msk                         (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACARPAR_ARPPA                             ETH_MACARPAR_ARPPA_Msk     /* ARP Protocol Address */

+

+/* Bit definition for Ethernet MAC Address 0 High Register */

+#define ETH_MACA0HR_AE_Pos                            (31U)

+#define ETH_MACA0HR_AE_Msk                            (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA0HR_AE                                ETH_MACA0HR_AE_Msk /* Address Enable*/

+#define ETH_MACA0HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA0HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA0HR_ADDRHI                            ETH_MACA0HR_ADDRHI_Msk   /* MAC Address 0*/

+

+/* Bit definition for Ethernet MAC Address 0 Low Register */

+#define ETH_MACA0LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA0LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA0LR_ADDRLO                            ETH_MACA0LR_ADDRLO_Msk   /* MAC Address 0*/

+

+/* Bit definition for Ethernet MAC Address 1 High Register */

+#define ETH_MACA1HR_AE_Pos                            (31U)

+#define ETH_MACA1HR_AE_Msk                            (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk /* Address Enable*/

+#define ETH_MACA1HR_SA_Pos                            (30U)

+#define ETH_MACA1HR_SA_Msk                            (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk /* Source Address */

+#define ETH_MACA1HR_MBC_Pos                           (24U)

+#define ETH_MACA1HR_MBC_Msk                           (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk /* Mask Byte Control */

+#define ETH_MACA1HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA1HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA1HR_ADDRHI                            ETH_MACA1HR_ADDRHI_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 1 Low Register */

+#define ETH_MACA1LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA1LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA1LR_ADDRLO                            ETH_MACA1LR_ADDRLO_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 2 High Register */

+#define ETH_MACA2HR_AE_Pos                            (31U)

+#define ETH_MACA2HR_AE_Msk                            (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk /* Address Enable*/

+#define ETH_MACA2HR_SA_Pos                            (30U)

+#define ETH_MACA2HR_SA_Msk                            (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk /* Source Address */

+#define ETH_MACA2HR_MBC_Pos                           (24U)

+#define ETH_MACA2HR_MBC_Msk                           (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk /* Mask Byte Control */

+#define ETH_MACA2HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA2HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA2HR_ADDRHI                            ETH_MACA2HR_ADDRHI_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 2 Low Register */

+#define ETH_MACA2LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA2LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA2LR_ADDRLO                            ETH_MACA2LR_ADDRLO_Msk   /* MAC Address 2*/

+

+/* Bit definition for Ethernet MAC Address 3 High Register */

+#define ETH_MACA3HR_AE_Pos                            (31U)

+#define ETH_MACA3HR_AE_Msk                            (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk /* Address Enable*/

+#define ETH_MACA3HR_SA_Pos                            (30U)

+#define ETH_MACA3HR_SA_Msk                            (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk /* Source Address */

+#define ETH_MACA3HR_MBC_Pos                           (24U)

+#define ETH_MACA3HR_MBC_Msk                           (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk /* Mask Byte Control */

+#define ETH_MACA3HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA3HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA3HR_ADDRHI                            ETH_MACA3HR_ADDRHI_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 3 Low Register */

+#define ETH_MACA3LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA3LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA3LR_ADDRLO                            ETH_MACA3LR_ADDRLO_Msk   /* MAC Address 3*/

+

+/* Bit definition for Ethernet MAC Address High Register */

+#define ETH_MACAHR_AE_Pos                             (31U)

+#define ETH_MACAHR_AE_Msk                             (0x1UL << ETH_MACAHR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACAHR_AE                                 ETH_MACAHR_AE_Msk        /* Address enable */

+#define ETH_MACAHR_SA_Pos                             (30U)

+#define ETH_MACAHR_SA_Msk                             (0x1UL << ETH_MACAHR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACAHR_SA                                 ETH_MACAHR_SA_Msk        /* Source address */

+#define ETH_MACAHR_MBC_Pos                            (24U)

+#define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */

+#define ETH_MACAHR_MBC_HBITS15_8                      ((uint32_t)0x20000000)   /* Mask MAC Address high reg bits [15:8] */

+#define ETH_MACAHR_MBC_HBITS7_0                       ((uint32_t)0x10000000)   /* Mask MAC Address high reg bits [7:0] */

+#define ETH_MACAHR_MBC_LBITS31_24                     ((uint32_t)0x08000000)   /* Mask MAC Address low reg bits [31:24] */

+#define ETH_MACAHR_MBC_LBITS23_16                     ((uint32_t)0x04000000)   /* Mask MAC Address low reg bits [23:16] */

+#define ETH_MACAHR_MBC_LBITS15_8                      ((uint32_t)0x02000000)   /* Mask MAC Address low reg bits [15:8] */

+#define ETH_MACAHR_MBC_LBITS7_0                       ((uint32_t)0x01000000)   /* Mask MAC Address low reg bits [7:0] */

+#define ETH_MACAHR_MACAH_Pos                          (0U)

+#define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */

+#define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */

+

+/* Bit definition for Ethernet MAC Address Low Register */

+#define ETH_MACALR_MACAL_Pos                          (0U)

+#define ETH_MACALR_MACAL_Msk                          (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACALR_MACAL                              ETH_MACALR_MACAL_Msk     /* MAC address low */

+

+/* Bit definition for Ethernet MMC Control Register */

+#define ETH_MMCCR_UCDBC_Pos                           (8U)

+#define ETH_MMCCR_UCDBC_Msk                           (0x1UL << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */

+#define ETH_MMCCR_UCDBC                               ETH_MMCCR_UCDBC_Msk  /* Update MMC Counters for Dropped Broadcast Packets */

+#define ETH_MMCCR_CNTPRSTLVL_Pos                      (5U)

+#define ETH_MMCCR_CNTPRSTLVL_Msk                      (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */

+#define ETH_MMCCR_CNTPRSTLVL                          ETH_MMCCR_CNTPRSTLVL_Msk  /* Full-Half Preset */

+#define ETH_MMCCR_CNTPRST_Pos                         (4U)

+#define ETH_MMCCR_CNTPRST_Msk                         (0x1UL << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */

+#define ETH_MMCCR_CNTPRST                             ETH_MMCCR_CNTPRST_Msk  /* Counters Reset */

+#define ETH_MMCCR_CNTFREEZ_Pos                        (3U)

+#define ETH_MMCCR_CNTFREEZ_Msk                        (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */

+#define ETH_MMCCR_CNTFREEZ                            ETH_MMCCR_CNTFREEZ_Msk  /* MMC Counter Freeze */

+#define ETH_MMCCR_RSTONRD_Pos                         (2U)

+#define ETH_MMCCR_RSTONRD_Msk                         (0x1UL << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */

+#define ETH_MMCCR_RSTONRD                             ETH_MMCCR_RSTONRD_Msk  /* Reset On Read */

+#define ETH_MMCCR_CNTSTOPRO_Pos                       (1U)

+#define ETH_MMCCR_CNTSTOPRO_Msk                       (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */

+#define ETH_MMCCR_CNTSTOPRO                           ETH_MMCCR_CNTSTOPRO_Msk  /* Counter Stop Rollover */

+#define ETH_MMCCR_CNTRST_Pos                          (0U)

+#define ETH_MMCCR_CNTRST_Msk                          (0x1UL << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */

+#define ETH_MMCCR_CNTRST                              ETH_MMCCR_CNTRST_Msk  /* Counters Reset */

+

+/* Bit definition for Ethernet MMC Rx Interrupt Register */

+#define ETH_MMCRIR_RXLPITRCIS_Pos                     (27U)

+#define ETH_MMCRIR_RXLPITRCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) /*!< 0x08000000 */

+#define ETH_MMCRIR_RXLPITRCIS                         ETH_MMCRIR_RXLPITRCIS_Msk  /* MMC Receive LPI transition counter interrupt status */

+#define ETH_MMCRIR_RXLPIUSCIS_Pos                     (26U)

+#define ETH_MMCRIR_RXLPIUSCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */

+#define ETH_MMCRIR_RXLPIUSCIS                         ETH_MMCRIR_RXLPIUSCIS_Msk  /* MMC Receive LPI microsecond counter interrupt status */

+#define ETH_MMCRIR_RXUCGPIS_Pos                       (17U)

+#define ETH_MMCRIR_RXUCGPIS_Msk                       (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) /*!< 0x00020000 */

+#define ETH_MMCRIR_RXUCGPIS                           ETH_MMCRIR_RXUCGPIS_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Status */

+#define ETH_MMCRIR_RXALGNERPIS_Pos                    (6U)

+#define ETH_MMCRIR_RXALGNERPIS_Msk                    (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) /*!< 0x00000040 */

+#define ETH_MMCRIR_RXALGNERPIS                        ETH_MMCRIR_RXALGNERPIS_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Status */

+#define ETH_MMCRIR_RXCRCERPIS_Pos                     (5U)

+#define ETH_MMCRIR_RXCRCERPIS_Msk                     (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) /*!< 0x00000020 */

+#define ETH_MMCRIR_RXCRCERPIS                         ETH_MMCRIR_RXCRCERPIS_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Status */

+

+/* Bit definition for Ethernet MMC Tx Interrupt Register */

+#define ETH_MMCTIR_TXLPITRCIS_Pos                     (27U)

+#define ETH_MMCTIR_TXLPITRCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) /*!< 0x08000000 */

+#define ETH_MMCTIR_TXLPITRCIS                         ETH_MMCTIR_TXLPITRCIS_Msk  /* MMC Transmit LPI transition counter interrupt status */

+#define ETH_MMCTIR_TXLPIUSCIS_Pos                     (26U)

+#define ETH_MMCTIR_TXLPIUSCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */

+#define ETH_MMCTIR_TXLPIUSCIS                         ETH_MMCTIR_TXLPIUSCIS_Msk  /* MMC Transmit LPI microsecond counter interrupt status */

+#define ETH_MMCTIR_TXGPKTIS_Pos                       (21U)

+#define ETH_MMCTIR_TXGPKTIS_Msk                       (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) /*!< 0x00200000 */

+#define ETH_MMCTIR_TXGPKTIS                           ETH_MMCTIR_TXGPKTIS_Msk  /* MMC Transmit Good Packet Counter Interrupt Status */

+#define ETH_MMCTIR_TXMCOLGPIS_Pos                     (15U)

+#define ETH_MMCTIR_TXMCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */

+#define ETH_MMCTIR_TXMCOLGPIS                         ETH_MMCTIR_TXMCOLGPIS_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */

+#define ETH_MMCTIR_TXSCOLGPIS_Pos                     (14U)

+#define ETH_MMCTIR_TXSCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */

+#define ETH_MMCTIR_TXSCOLGPIS                         ETH_MMCTIR_TXSCOLGPIS_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */

+

+/* Bit definition for Ethernet MMC Rx interrupt Mask register */

+#define ETH_MMCRIMR_RXLPITRCIM_Pos                    (27U)

+#define ETH_MMCRIMR_RXLPITRCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */

+#define ETH_MMCRIMR_RXLPITRCIM                        ETH_MMCRIMR_RXLPITRCIM_Msk  /* MMC Receive LPI transition counter interrupt Mask */

+#define ETH_MMCRIMR_RXLPIUSCIM_Pos                    (26U)

+#define ETH_MMCRIMR_RXLPIUSCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */

+#define ETH_MMCRIMR_RXLPIUSCIM                        ETH_MMCRIMR_RXLPIUSCIM_Msk  /* MMC Receive LPI microsecond counter interrupt Mask */

+#define ETH_MMCRIMR_RXUCGPIM_Pos                      (17U)

+#define ETH_MMCRIMR_RXUCGPIM_Msk                      (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) /*!< 0x00020000 */

+#define ETH_MMCRIMR_RXUCGPIM                          ETH_MMCRIMR_RXUCGPIM_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Mask */

+#define ETH_MMCRIMR_RXALGNERPIM_Pos                   (6U)

+#define ETH_MMCRIMR_RXALGNERPIM_Msk                   (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */

+#define ETH_MMCRIMR_RXALGNERPIM                       ETH_MMCRIMR_RXALGNERPIM_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Mask */

+#define ETH_MMCRIMR_RXCRCERPIM_Pos                    (5U)

+#define ETH_MMCRIMR_RXCRCERPIM_Msk                    (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */

+#define ETH_MMCRIMR_RXCRCERPIM                        ETH_MMCRIMR_RXCRCERPIM_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Mask */

+

+/* Bit definition for Ethernet MMC Tx Interrupt Mask Register */

+#define ETH_MMCTIMR_TXLPITRCIM_Pos                    (27U)

+#define ETH_MMCTIMR_TXLPITRCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */

+#define ETH_MMCTIMR_TXLPITRCIM                        ETH_MMCTIMR_TXLPITRCIM_Msk  /* MMC Transmit LPI transition counter interrupt Mask*/

+#define ETH_MMCTIMR_TXLPIUSCIM_Pos                    (26U)

+#define ETH_MMCTIMR_TXLPIUSCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */

+#define ETH_MMCTIMR_TXLPIUSCIM                        ETH_MMCTIMR_TXLPIUSCIM_Msk  /* MMC Transmit LPI microsecond counter interrupt Mask*/

+#define ETH_MMCTIMR_TXGPKTIM_Pos                      (21U)

+#define ETH_MMCTIMR_TXGPKTIM_Msk                      (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) /*!< 0x00200000 */

+#define ETH_MMCTIMR_TXGPKTIM                          ETH_MMCTIMR_TXGPKTIM_Msk  /* MMC Transmit Good Packet Counter Interrupt Mask*/

+#define ETH_MMCTIMR_TXMCOLGPIM_Pos                    (15U)

+#define ETH_MMCTIMR_TXMCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */

+#define ETH_MMCTIMR_TXMCOLGPIM                        ETH_MMCTIMR_TXMCOLGPIM_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */

+#define ETH_MMCTIMR_TXSCOLGPIM_Pos                    (14U)

+#define ETH_MMCTIMR_TXSCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */

+#define ETH_MMCTIMR_TXSCOLGPIM                        ETH_MMCTIMR_TXSCOLGPIM_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */

+

+/* Bit definition for Ethernet MMC Tx Single Collision Good Packets Register */

+#define ETH_MMCTSCGPR_TXSNGLCOLG_Pos                  (0U)

+#define ETH_MMCTSCGPR_TXSNGLCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTSCGPR_TXSNGLCOLG                      ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */

+

+/* Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register */

+#define ETH_MMCTMCGPR_TXMULTCOLG_Pos                  (0U)

+#define ETH_MMCTMCGPR_TXMULTCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTMCGPR_TXMULTCOLG                      ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */

+

+/* Bit definition for Ethernet MMC Tx Packet Count Good Register */

+#define ETH_MMCTPCGR_TXPKTG_Pos                       (0U)

+#define ETH_MMCTPCGR_TXPKTG_msk                       (0xFFFFFFFFUL <<  ETH_MMCTPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTPCGR_TXPKTG                           ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */

+

+/* Bit definition for Ethernet MMC Rx CRC Error Packets Register */

+#define ETH_MMCRCRCEPR_RXCRCERR_Pos                   (0U)

+#define ETH_MMCRCRCEPR_RXCRCERR_msk                   (0xFFFFFFFFUL <<  ETH_MMCRCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRCRCEPR_RXCRCERR                       ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */

+

+/* Bit definition for Ethernet MMC Rx alignment error packets register */

+#define ETH_MMCRAEPR_RXALGNERR_Pos                    (0U)

+#define ETH_MMCRAEPR_RXALGNERR_msk                    (0xFFFFFFFFUL <<  ETH_MMCRAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRAEPR_RXALGNERR                        ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */

+

+/* Bit definition for Ethernet MMC Rx Unicast Packets Good Register */

+#define ETH_MMCRUPGR_RXUCASTG_Pos                     (0U)

+#define ETH_MMCRUPGR_RXUCASTG_msk                     (0xFFFFFFFFUL <<  ETH_MMCRUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRUPGR_RXUCASTG                         ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */

+

+/* Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register */

+#define ETH_MMCTLPIMSTR_TXLPIUSC_Pos                  (0U)

+#define ETH_MMCTLPIMSTR_TXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCTLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTLPIMSTR_TXLPIUSC                      ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */

+

+/* Bit definition for Ethernet MMC Tx LPI Transition Counter Register */

+#define ETH_MMCTLPITCR_TXLPITRC_Pos                   (0U)

+#define ETH_MMCTLPITCR_TXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCTLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTLPITCR_TXLPITRC                       ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */

+

+/* Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register */

+#define ETH_MMCRLPIMSTR_RXLPIUSC_Pos                  (0U)

+#define ETH_MMCRLPIMSTR_RXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCRLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRLPIMSTR_RXLPIUSC                      ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */

+

+/* Bit definition for Ethernet MMC Rx LPI Transition Counter Register */

+#define ETH_MMCRLPITCR_RXLPITRC_Pos                   (0U)

+#define ETH_MMCRLPITCR_RXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCRLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRLPITCR_RXLPITRC                       ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */

+

+/* Bit definition for Ethernet MAC L3 L4 Control Register */

+#define ETH_MACL3L4CR_L4DPIM_Pos                      (21U)

+#define ETH_MACL3L4CR_L4DPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos) /*!< 0x00200000 */

+#define ETH_MACL3L4CR_L4DPIM                          ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */

+#define ETH_MACL3L4CR_L4DPM_Pos                       (20U)

+#define ETH_MACL3L4CR_L4DPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4DPM_Pos) /*!< 0x00100000 */

+#define ETH_MACL3L4CR_L4DPM                           ETH_MACL3L4CR_L4DPM_Msk  /* Layer 4 Destination Port Match Enable */

+#define ETH_MACL3L4CR_L4SPIM_Pos                      (19U)

+#define ETH_MACL3L4CR_L4SPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos) /*!< 0x00080000 */

+#define ETH_MACL3L4CR_L4SPIM                          ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */

+#define ETH_MACL3L4CR_L4SPM_Pos                       (18U)

+#define ETH_MACL3L4CR_L4SPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4SPM_Pos) /*!< 0x00040000 */

+#define ETH_MACL3L4CR_L4SPM                           ETH_MACL3L4CR_L4SPM_Msk  /* Layer 4 Source Port Match Enable */

+#define ETH_MACL3L4CR_L4PEN_Pos                       (16U)

+#define ETH_MACL3L4CR_L4PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L4PEN_Pos) /*!< 0x00010000 */

+#define ETH_MACL3L4CR_L4PEN                           ETH_MACL3L4CR_L4PEN_Msk  /* Layer 4 Protocol Enable */

+#define ETH_MACL3L4CR_L3HDBM_Pos                      (11U)

+#define ETH_MACL3L4CR_L3HDBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos) /*!< 0x0000F800 */

+#define ETH_MACL3L4CR_L3HDBM                          ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */

+#define ETH_MACL3L4CR_L3HSBM_Pos                      (6U)

+#define ETH_MACL3L4CR_L3HSBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos) /*!< 0x000007C0 */

+#define ETH_MACL3L4CR_L3HSBM                          ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */

+#define ETH_MACL3L4CR_L3DAIM_Pos                      (5U)

+#define ETH_MACL3L4CR_L3DAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos) /*!< 0x00000020 */

+#define ETH_MACL3L4CR_L3DAIM                          ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */

+#define ETH_MACL3L4CR_L3DAM_Pos                       (4U)

+#define ETH_MACL3L4CR_L3DAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3DAM_Pos) /*!< 0x00000010 */

+#define ETH_MACL3L4CR_L3DAM                           ETH_MACL3L4CR_L3DAM_Msk  /* Layer 3 IP DA Match Enable */

+#define ETH_MACL3L4CR_L3SAIM_Pos                      (3U)

+#define ETH_MACL3L4CR_L3SAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos) /*!< 0x00000008 */

+#define ETH_MACL3L4CR_L3SAIM                          ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */

+#define ETH_MACL3L4CR_L3SAM_Pos                       (2U)

+#define ETH_MACL3L4CR_L3SAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3SAM_Pos) /*!< 0x00000004 */

+#define ETH_MACL3L4CR_L3SAM                           ETH_MACL3L4CR_L3SAM_Msk  /* Layer 3 IP SA Match Enable*/

+#define ETH_MACL3L4CR_L3PEN_Pos                       (0U)

+#define ETH_MACL3L4CR_L3PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L3PEN_Pos) /*!< 0x00000001 */

+#define ETH_MACL3L4CR_L3PEN                           ETH_MACL3L4CR_L3PEN_Msk  /* Layer 3 Protocol Enable */

+

+/* Bit definition for Ethernet MAC L4 Address Register */

+#define ETH_MACL4AR_L4DP_Pos                          (16U)

+#define ETH_MACL4AR_L4DP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4DP_Pos) /*!< 0xFFFF0000 */

+#define ETH_MACL4AR_L4DP                              ETH_MACL4AR_L4DP_Msk     /* Layer 4 Destination Port Number Field */

+#define ETH_MACL4AR_L4SP_Pos                          (0U)

+#define ETH_MACL4AR_L4SP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4SP_Pos) /*!< 0x0000FFFF */

+#define ETH_MACL4AR_L4SP                              ETH_MACL4AR_L4SP_Msk     /* Layer 4 Source Port Number Field */

+

+/* Bit definition for Ethernet MAC L3 Address0 Register */

+#define ETH_MACL3A0R_L3A0_Pos                         (0U)

+#define ETH_MACL3A0R_L3A0_Msk                         (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A0R_L3A0                             ETH_MACL3A0R_L3A0_Msk    /* Layer 3 Address 0 Field */

+

+/* Bit definition for Ethernet MAC L4 Address1 Register */

+#define ETH_MACL3A1R_L3A1_Pos                         (0U)

+#define ETH_MACL3A1R_L3A1_Msk                         (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A1R_L3A1                             ETH_MACL3A1R_L3A1_Msk    /* Layer 3 Address 1 Field */

+

+/* Bit definition for Ethernet MAC L4 Address2 Register */

+#define ETH_MACL3A2R_L3A2_Pos                         (0U)

+#define ETH_MACL3A2R_L3A2_Msk                         (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A2R_L3A2                             ETH_MACL3A2R_L3A2_Msk    /* Layer 3 Address 2 Field */

+

+/* Bit definition for Ethernet MAC L4 Address3 Register */

+#define ETH_MACL3A3R_L3A3_Pos                         (0U)

+#define ETH_MACL3A3R_L3A3_Msk                         (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A3R_L3A3                             ETH_MACL3A3R_L3A3_Msk    /* Layer 3 Address 3 Field */

+

+/* Bit definition for Ethernet MAC Timestamp Control Register */

+#define ETH_MACTSCR_TXTSSTSM_Pos                      (24U)

+#define ETH_MACTSCR_TXTSSTSM_Msk                      (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */

+#define ETH_MACTSCR_TXTSSTSM                          ETH_MACTSCR_TXTSSTSM_Msk  /* Transmit Timestamp Status Mode */

+#define ETH_MACTSCR_CSC_Pos                           (19U)

+#define ETH_MACTSCR_CSC_Msk                           (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */

+#define ETH_MACTSCR_CSC                               ETH_MACTSCR_CSC_Msk  /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */

+#define ETH_MACTSCR_TSENMACADDR_Pos                   (18U)

+#define ETH_MACTSCR_TSENMACADDR_Msk                   (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */

+#define ETH_MACTSCR_TSENMACADDR                       ETH_MACTSCR_TSENMACADDR_Msk  /* Enable MAC Address for PTP Packet Filtering */

+#define ETH_MACTSCR_SNAPTYPSEL_Pos                    (16U)

+#define ETH_MACTSCR_SNAPTYPSEL_Msk                    (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */

+#define ETH_MACTSCR_SNAPTYPSEL                        ETH_MACTSCR_SNAPTYPSEL_Msk  /* Select PTP packets for Taking Snapshots */

+#define ETH_MACTSCR_TSMSTRENA_Pos                     (15U)

+#define ETH_MACTSCR_TSMSTRENA_Msk                     (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */

+#define ETH_MACTSCR_TSMSTRENA                         ETH_MACTSCR_TSMSTRENA_Msk  /* Enable Snapshot for Messages Relevant to Master */

+#define ETH_MACTSCR_TSEVNTENA_Pos                     (14U)

+#define ETH_MACTSCR_TSEVNTENA_Msk                     (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */

+#define ETH_MACTSCR_TSEVNTENA                         ETH_MACTSCR_TSEVNTENA_Msk  /* Enable Timestamp Snapshot for Event Messages */

+#define ETH_MACTSCR_TSIPV4ENA_Pos                     (13U)

+#define ETH_MACTSCR_TSIPV4ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */

+#define ETH_MACTSCR_TSIPV4ENA                         ETH_MACTSCR_TSIPV4ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv4-UDP */

+#define ETH_MACTSCR_TSIPV6ENA_Pos                     (12U)

+#define ETH_MACTSCR_TSIPV6ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */

+#define ETH_MACTSCR_TSIPV6ENA                         ETH_MACTSCR_TSIPV6ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv6-UDP */

+#define ETH_MACTSCR_TSIPENA_Pos                       (11U)

+#define ETH_MACTSCR_TSIPENA_Msk                       (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */

+#define ETH_MACTSCR_TSIPENA                           ETH_MACTSCR_TSIPENA_Msk  /* Enable Processing of PTP over Ethernet Packets */

+#define ETH_MACTSCR_TSVER2ENA_Pos                     (10U)

+#define ETH_MACTSCR_TSVER2ENA_Msk                     (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */

+#define ETH_MACTSCR_TSVER2ENA                         ETH_MACTSCR_TSVER2ENA_Msk  /* Enable PTP Packet Processing for Version 2 Format */

+#define ETH_MACTSCR_TSCTRLSSR_Pos                     (9U)

+#define ETH_MACTSCR_TSCTRLSSR_Msk                     (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */

+#define ETH_MACTSCR_TSCTRLSSR                         ETH_MACTSCR_TSCTRLSSR_Msk  /* Timestamp Digital or Binary Rollover Control */

+#define ETH_MACTSCR_TSENALL_Pos                       (8U)

+#define ETH_MACTSCR_TSENALL_Msk                       (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */

+#define ETH_MACTSCR_TSENALL                           ETH_MACTSCR_TSENALL_Msk  /* Enable Timestamp for All Packets */

+#define ETH_MACTSCR_TSADDREG_Pos                      (5U)

+#define ETH_MACTSCR_TSADDREG_Msk                      (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */

+#define ETH_MACTSCR_TSADDREG                          ETH_MACTSCR_TSADDREG_Msk  /* Update Addend Register */

+#define ETH_MACTSCR_TSUPDT_Pos                        (3U)

+#define ETH_MACTSCR_TSUPDT_Msk                        (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */

+#define ETH_MACTSCR_TSUPDT                            ETH_MACTSCR_TSUPDT_Msk  /* Update Timestamp */

+#define ETH_MACTSCR_TSINIT_Pos                        (2U)

+#define ETH_MACTSCR_TSINIT_Msk                        (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */

+#define ETH_MACTSCR_TSINIT                             ETH_MACTSCR_TSINIT_Msk  /* Initialize Timestamp */

+#define ETH_MACTSCR_TSCFUPDT_Pos                      (1U)

+#define ETH_MACTSCR_TSCFUPDT_Msk                      (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */

+#define ETH_MACTSCR_TSCFUPDT                          ETH_MACTSCR_TSCFUPDT_Msk  /* Fine or Coarse Timestamp Update*/

+#define ETH_MACTSCR_TSENA_Pos                         (0U)

+#define ETH_MACTSCR_TSENA_Msk                         (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */

+#define ETH_MACTSCR_TSENA                             ETH_MACTSCR_TSENA_Msk  /* Enable Timestamp */

+

+/* Bit definition for Ethernet MAC Sub-second Increment Register */

+#define ETH_MACMACSSIR_SSINC_Pos                      (16U)

+#define ETH_MACMACSSIR_SSINC_Msk                      (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) /*!< 0x0000FF00 */

+#define ETH_MACMACSSIR_SSINC                          ETH_MACMACSSIR_SSINC_Msk  /* Sub-second Increment Value */

+#define ETH_MACMACSSIR_SNSINC_Pos                     (8U)

+#define ETH_MACMACSSIR_SNSINC_Msk                     (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos) /*!< 0x000000FF */

+#define ETH_MACMACSSIR_SNSINC                         ETH_MACMACSSIR_SNSINC_Msk  /* Sub-nanosecond Increment Value */

+

+/* Bit definition for Ethernet MAC System Time Seconds Register */

+#define ETH_MACSTSR_TSS_Pos                           (0U)

+#define ETH_MACSTSR_TSS_Msk                           (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSTSR_TSS                               ETH_MACSTSR_TSS_Msk  /* Timestamp Second */

+

+/* Bit definition for Ethernet MAC System Time Nanoseconds Register */

+#define ETH_MACSTNR_TSSS_Pos                          (0U)

+#define ETH_MACSTNR_TSSS_Msk                          (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACSTNR_TSSS                              ETH_MACSTNR_TSSS_Msk  /* Timestamp Sub-seconds */

+

+/* Bit definition for Ethernet MAC System Time Seconds Update Register */

+#define ETH_MACSTSUR_TSS_Pos                          (0U)

+#define ETH_MACSTSUR_TSS_Msk                          (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSTSUR_TSS                              ETH_MACSTSUR_TSS_Msk  /* Timestamp Seconds */

+

+/* Bit definition for Ethernet MAC System Time Nanoseconds Update Register */

+#define ETH_MACSTNUR_ADDSUB_Pos                       (31U)

+#define ETH_MACSTNUR_ADDSUB_Msk                       (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */

+#define ETH_MACSTNUR_ADDSUB                           ETH_MACSTNUR_ADDSUB_Msk  /* Add or Subtract Time */

+#define ETH_MACSTNUR_TSSS_Pos                         (0U)

+#define ETH_MACSTNUR_TSSS_Msk                         (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACSTNUR_TSSS                             ETH_MACSTNUR_TSSS_Msk  /* Timestamp Sub-seconds */

+

+/* Bit definition for Ethernet MAC Timestamp Addend Register */

+#define ETH_MACTSAR_TSAR_Pos                          (0U)

+#define ETH_MACTSAR_TSAR_Msk                          (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSAR_TSAR                              ETH_MACTSAR_TSAR_Msk  /* Timestamp Addend Register */

+

+/* Bit definition for Ethernet MAC Timestamp Status Register */

+#define ETH_MACTSSR_ATSNS_Pos                         (25U)

+#define ETH_MACTSSR_ATSNS_Msk                         (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */

+#define ETH_MACTSSR_ATSNS                             ETH_MACTSSR_ATSNS_Msk  /* Number of Auxiliary Timestamp Snapshots */

+#define ETH_MACTSSR_ATSSTM_Pos                        (24U)

+#define ETH_MACTSSR_ATSSTM_Msk                        (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */

+#define ETH_MACTSSR_ATSSTM                            ETH_MACTSSR_ATSSTM_Msk  /* Auxiliary Timestamp Snapshot Trigger Missed */

+#define ETH_MACTSSR_ATSSTN_Pos                        (16U)

+#define ETH_MACTSSR_ATSSTN_Msk                        (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */

+#define ETH_MACTSSR_ATSSTN                            ETH_MACTSSR_ATSSTN_Msk  /* Auxiliary Timestamp Snapshot Trigger Identifier */

+#define ETH_MACTSSR_TXTSSIS_Pos                       (15U)

+#define ETH_MACTSSR_TXTSSIS_Msk                       (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */

+#define ETH_MACTSSR_TXTSSIS                           ETH_MACTSSR_TXTSSIS_Msk  /* Tx Timestamp Status Interrupt Status */

+#define ETH_MACTSSR_TSTRGTERR0_Pos                    (3U)

+#define ETH_MACTSSR_TSTRGTERR0_Msk                    (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */

+#define ETH_MACTSSR_TSTRGTERR0                        ETH_MACTSSR_TSTRGTERR0_Msk  /* Timestamp Target Time Error */

+#define ETH_MACTSSR_AUXTSTRIG_Pos                     (2U)

+#define ETH_MACTSSR_AUXTSTRIG_Msk                     (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */

+#define ETH_MACTSSR_AUXTSTRIG                         ETH_MACTSSR_AUXTSTRIG_Msk  /* Auxiliary Timestamp Trigger Snapshot*/

+#define ETH_MACTSSR_TSTARGT0_Pos                      (1U)

+#define ETH_MACTSSR_TSTARGT0_Msk                      (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */

+#define ETH_MACTSSR_TSTARGT0                          ETH_MACTSSR_TSTARGT0_Msk  /* Timestamp Target Time Reached */

+#define ETH_MACTSSR_TSSOVF_Pos                        (0U)

+#define ETH_MACTSSR_TSSOVF_Msk                        (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */

+#define ETH_MACTSSR_TSSOVF                            ETH_MACTSSR_TSSOVF_Msk  /* Timestamp Seconds Overflow */

+

+/* Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register */

+#define ETH_MACTTSSNR_TXTSSMIS_Pos                    (31U)

+#define ETH_MACTTSSNR_TXTSSMIS_Msk                    (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */

+#define ETH_MACTTSSNR_TXTSSMIS                        ETH_MACTTSSNR_TXTSSMIS_Msk  /* Transmit Timestamp Status Missed */

+#define ETH_MACTTSSNR_TXTSSLO_Pos                     (0U)

+#define ETH_MACTTSSNR_TXTSSLO_Msk                     (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACTTSSNR_TXTSSLO                         ETH_MACTTSSNR_TXTSSLO_Msk  /* Transmit Timestamp Status Low */

+

+/* Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register */

+#define ETH_MACTTSSSR_TXTSSHI_Pos                     (0U)

+#define ETH_MACTTSSSR_TXTSSHI_Msk                     (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTTSSSR_TXTSSHI                         ETH_MACTTSSSR_TXTSSHI_Msk  /* Transmit Timestamp Status High */

+

+/* Bit definition for Ethernet MAC Auxiliary Control Register*/

+#define ETH_MACACR_ATSEN3_Pos                         (7U)

+#define ETH_MACACR_ATSEN3_Msk                         (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */

+#define ETH_MACACR_ATSEN3                             ETH_MACACR_ATSEN3_Msk  /* Auxiliary Snapshot 3 Enable */

+#define ETH_MACACR_ATSEN2_Pos                         (6U)

+#define ETH_MACACR_ATSEN2_Msk                         (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */

+#define ETH_MACACR_ATSEN2                             ETH_MACACR_ATSEN2_Msk  /* Auxiliary Snapshot 2 Enable */

+#define ETH_MACACR_ATSEN1_Pos                         (5U)

+#define ETH_MACACR_ATSEN1_Msk                         (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */

+#define ETH_MACACR_ATSEN1                             ETH_MACACR_ATSEN1_Msk  /* Auxiliary Snapshot 1 Enable */

+#define ETH_MACACR_ATSEN0_Pos                         (4U)

+#define ETH_MACACR_ATSEN0_Msk                         (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */

+#define ETH_MACACR_ATSEN0                             ETH_MACACR_ATSEN0_Msk  /* Auxiliary Snapshot 0 Enable */

+#define ETH_MACACR_ATSFC_Pos                          (0U)

+#define ETH_MACACR_ATSFC_Msk                          (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */

+#define ETH_MACACR_ATSFC                              ETH_MACACR_ATSFC_Msk  /* Auxiliary Snapshot FIFO Clear */

+

+/* Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register */

+#define ETH_MACATSNR_AUXTSLO_Pos                      (0U)

+#define ETH_MACATSNR_AUXTSLO_Msk                      (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACATSNR_AUXTSLO                          ETH_MACATSNR_AUXTSLO_Msk  /* Auxiliary Timestamp */

+

+/* Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register */

+#define ETH_MACATSSR_AUXTSHI_Pos                      (0U)

+#define ETH_MACATSSR_AUXTSHI_Msk                      (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACATSSR_AUXTSHI                          ETH_MACATSSR_AUXTSHI_Msk  /* Auxiliary Timestamp */

+

+/* Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register */

+#define ETH_MACTSIACR_OSTIAC_Pos                      (0U)

+#define ETH_MACTSIACR_OSTIAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSIACR_OSTIAC                          ETH_MACTSIACR_OSTIAC_Msk  /* One-Step Timestamp Ingress Asymmetry Correction */

+

+/* Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction Register */

+#define ETH_MACTSEACR_OSTEAC_Pos                      (0U)

+#define ETH_MACTSEACR_OSTEAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSEACR_OSTEAC                          ETH_MACTSEACR_OSTEAC_Msk  /* One-Step Timestamp Egress Asymmetry Correction */

+

+/* Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond Register */

+#define ETH_MACTSICNR_TSIC_Pos                        (0U)

+#define ETH_MACTSICNR_TSIC_Msk                        (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSICNR_TSIC                            ETH_MACTSICNR_TSIC_Msk  /* Timestamp Ingress Correction */

+

+/* Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond Register */

+#define ETH_MACTSECNR_TSEC_Pos                        (0U)

+#define ETH_MACTSECNR_TSEC_Msk                        (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSECNR_TSEC                            ETH_MACTSECNR_TSEC_Msk  /* Timestamp Egress Correction */

+

+/* Bit definition for Ethernet MAC PPS Control Register */

+#define ETH_MACPPSCR_TRGTMODSEL0_Pos                  (5U)

+#define ETH_MACPPSCR_TRGTMODSEL0_Msk                  (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */

+#define ETH_MACPPSCR_TRGTMODSEL0                      ETH_MACPPSCR_TRGTMODSEL0_Msk  /* Target Time Register Mode for PPS Output */

+#define ETH_MACPPSCR_PPSEN0_Pos                       (4U)

+#define ETH_MACPPSCR_PPSEN0_Msk                       (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */

+#define ETH_MACPPSCR_PPSEN0                           ETH_MACPPSCR_PPSEN0_Msk  /* Flexible PPS Output Mode Enable */

+#define ETH_MACPPSCR_PPSCTRL_Pos                      (0U)

+#define ETH_MACPPSCR_PPSCTRL_Msk                      (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */

+#define ETH_MACPPSCR_PPSCTRL                          ETH_MACPPSCR_PPSCTRL_Msk  /* PPS Output Frequency Control */

+

+/* Bit definition for Ethernet MAC PPS Target Time Seconds Register */

+#define ETH_MACPPSTTSR_TSTRH0_Pos                     (0U)

+#define ETH_MACPPSTTSR_TSTRH0_Msk                     (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACPPSTTSR_TSTRH0                         ETH_MACPPSTTSR_TSTRH0_Msk  /* PPS Target Time Seconds Register */

+

+/* Bit definition for Ethernet MAC PPS Target Time Nanoseconds Register */

+#define ETH_MACPPSTTNR_TRGTBUSY0_Pos                  (31U)

+#define ETH_MACPPSTTNR_TRGTBUSY0_Msk                  (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos) /*!< 0x80000000 */

+#define ETH_MACPPSTTNR_TRGTBUSY0                      ETH_MACPPSTTNR_TRGTBUSY0_Msk  /* PPS Target Time Register Busy */

+#define ETH_MACPPSTTNR_TTSL0_Pos                      (0U)

+#define ETH_MACPPSTTNR_TTSL0_Msk                      (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACPPSTTNR_TTSL0                          ETH_MACPPSTTNR_TTSL0_Msk  /* Target Time Low for PPS Register */

+

+/* Bit definition for Ethernet MAC PPS Interval Register */

+#define ETH_MACPPSIR_PPSINT0_Pos                      (0U)

+#define ETH_MACPPSIR_PPSINT0_Msk                      (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACPPSIR_PPSINT0                          ETH_MACPPSIR_PPSINT0_Msk  /* PPS Output Signal Interval */

+

+/* Bit definition for Ethernet MAC PPS Width Register */

+#define ETH_MACPPSWR_PPSWIDTH0_Pos                    (0U)

+#define ETH_MACPPSWR_PPSWIDTH0_Msk                    (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACPPSWR_PPSWIDTH0                        ETH_MACPPSWR_PPSWIDTH0_Msk  /* PPS Output Signal Width */

+

+/* Bit definition for Ethernet MAC PTP Offload Control Register */

+#define ETH_MACPOCR_DN_Pos                            (8U)

+#define ETH_MACPOCR_DN_Msk                            (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */

+#define ETH_MACPOCR_DN                                ETH_MACPOCR_DN_Msk  /* Domain Number */

+#define ETH_MACPOCR_DRRDIS_Pos                        (6U)

+#define ETH_MACPOCR_DRRDIS_Msk                        (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */

+#define ETH_MACPOCR_DRRDIS                            ETH_MACPOCR_DRRDIS_Msk  /* Disable PTO Delay Request/Response response generation */

+#define ETH_MACPOCR_APDREQTRIG_Pos                    (5U)

+#define ETH_MACPOCR_APDREQTRIG_Msk                    (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */

+#define ETH_MACPOCR_APDREQTRIG                        ETH_MACPOCR_APDREQTRIG_Msk  /* Automatic PTP Pdelay_Req message Trigger */

+#define ETH_MACPOCR_ASYNCTRIG_Pos                     (4U)

+#define ETH_MACPOCR_ASYNCTRIG_Msk                     (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */

+#define ETH_MACPOCR_ASYNCTRIG                         ETH_MACPOCR_ASYNCTRIG_Msk  /* Automatic PTP SYNC message Trigger */

+#define ETH_MACPOCR_APDREQEN_Pos                      (2U)

+#define ETH_MACPOCR_APDREQEN_Msk                      (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */

+#define ETH_MACPOCR_APDREQEN                          ETH_MACPOCR_APDREQEN_Msk  /* Automatic PTP Pdelay_Req message Enable */

+#define ETH_MACPOCR_ASYNCEN_Pos                       (1U)

+#define ETH_MACPOCR_ASYNCEN_Msk                       (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */

+#define ETH_MACPOCR_ASYNCEN                           ETH_MACPOCR_ASYNCEN_Msk  /* Automatic PTP SYNC message Enable */

+#define ETH_MACPOCR_PTOEN_Pos                         (0U)

+#define ETH_MACPOCR_PTOEN_Msk                         (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */

+#define ETH_MACPOCR_PTOEN                             ETH_MACPOCR_PTOEN_Msk  /* PTP Offload Enable */

+

+/* Bit definition for Ethernet MAC PTP Source Port Identity 0 Register */

+#define ETH_MACSPI0R_SPI0_Pos                         (0U)

+#define ETH_MACSPI0R_SPI0_Msk                         (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSPI0R_SPI0                             ETH_MACSPI0R_SPI0_Msk  /* Source Port Identity 0 */

+

+/* Bit definition for Ethernet MAC PTP Source Port Identity 1 Register */

+#define ETH_MACSPI1R_SPI1_Pos                         (0U)

+#define ETH_MACSPI1R_SPI1_Msk                         (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSPI1R_SPI1                             ETH_MACSPI1R_SPI1_Msk  /* Source Port Identity 1 */

+

+/* Bit definition for Ethernet MAC PTP Source Port Identity 2 Register */

+#define ETH_MACSPI2R_SPI2_Pos                         (0U)

+#define ETH_MACSPI2R_SPI2_Msk                         (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */

+#define ETH_MACSPI2R_SPI2                             ETH_MACSPI2R_SPI2_Msk  /* Source Port Identity 2 */

+

+/* Bit definition for Ethernet MAC Log Message Interval Register */

+#define ETH_MACLMIR_LMPDRI_Pos                        (24U)

+#define ETH_MACLMIR_LMPDRI_Msk                        (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */

+#define ETH_MACLMIR_LMPDRI                             ETH_MACLMIR_LMPDRI_Msk  /* Log Min Pdelay_Req Interval */

+#define ETH_MACLMIR_DRSYNCR_Pos                       (8U)

+#define ETH_MACLMIR_DRSYNCR_Msk                       (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */

+#define ETH_MACLMIR_DRSYNCR                           ETH_MACLMIR_DRSYNCR_Msk  /* Delay_Req to SYNC Ratio */

+#define ETH_MACLMIR_LSI_Pos                           (0U)

+#define ETH_MACLMIR_LSI_Msk                           (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */

+#define ETH_MACLMIR_LSI                               ETH_MACLMIR_LSI_Msk  /* Log Sync Interval */

+

+/* Bit definition for Ethernet MTL Operation Mode Register */

+#define ETH_MTLOMR_CNTCLR_Pos                         (9U)

+#define ETH_MTLOMR_CNTCLR_Msk                         (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */

+#define ETH_MTLOMR_CNTCLR                             ETH_MTLOMR_CNTCLR_Msk    /* Counters Reset */

+#define ETH_MTLOMR_CNTPRST_Pos                        (8U)

+#define ETH_MTLOMR_CNTPRST_Msk                        (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */

+#define ETH_MTLOMR_CNTPRST                            ETH_MTLOMR_CNTPRST_Msk   /* Counters Preset */

+#define ETH_MTLOMR_DTXSTS_Pos                         (1U)

+#define ETH_MTLOMR_DTXSTS_Msk                         (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */

+#define ETH_MTLOMR_DTXSTS                             ETH_MTLOMR_DTXSTS_Msk  /* Drop Transmit Status */

+

+/* Bit definition for Ethernet MTL Interrupt Status Register */

+#define ETH_MTLISR_MACIS_Pos                          (16U)

+#define ETH_MTLISR_MACIS_Msk                          (0x1UL << ETH_MTLISR_MACIS_Pos) /*!< 0x00010000 */

+#define ETH_MTLISR_MACIS                              ETH_MTLISR_MACIS_Msk     /* MAC Interrupt Status */

+#define ETH_MTLISR_QIS_Pos                            (0U)

+#define ETH_MTLISR_QIS_Msk                            (0x1UL << ETH_MTLISR_QIS_Pos) /*!< 0x00000001 */

+#define ETH_MTLISR_QIS                                ETH_MTLISR_QIS_Msk       /* Queue Interrupt status */

+

+/* Bit definition for Ethernet MTL Tx Queue Operation Mode Register */

+#define ETH_MTLTQOMR_TTC_Pos                          (4U)

+#define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */

+#define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */

+#define ETH_MTLTQOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */

+#define ETH_MTLTQOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */

+#define ETH_MTLTQOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */

+#define ETH_MTLTQOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */

+#define ETH_MTLTQOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */

+#define ETH_MTLTQOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */

+#define ETH_MTLTQOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */

+#define ETH_MTLTQOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */

+#define ETH_MTLTQOMR_TSF_Pos                          (1U)

+#define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */

+#define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */

+#define ETH_MTLTQOMR_FTQ_Pos                          (0U)

+#define ETH_MTLTQOMR_FTQ_Msk                          (0x1UL << ETH_MTLTQOMR_FTQ_Pos) /*!< 0x00000001 */

+#define ETH_MTLTQOMR_FTQ                              ETH_MTLTQOMR_FTQ_Msk     /* Flush Transmit Queue */

+

+/* Bit definition for Ethernet MTL Tx Queue Underflow Register */

+#define ETH_MTLTQUR_UFCNTOVF_Pos                      (11U)

+#define ETH_MTLTQUR_UFCNTOVF_Msk                      (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos) /*!< 0x00000800 */

+#define ETH_MTLTQUR_UFCNTOVF                          ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */

+#define ETH_MTLTQUR_UFPKTCNT_Pos                      (0U)

+#define ETH_MTLTQUR_UFPKTCNT_Msk                      (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos) /*!< 0x000007FF */

+#define ETH_MTLTQUR_UFPKTCNT                          ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */

+

+/* Bit definition for Ethernet MTL Tx Queue Debug Register */

+#define ETH_MTLTQDR_STXSTSF_Pos                       (20U)

+#define ETH_MTLTQDR_STXSTSF_Msk                       (0x7UL << ETH_MTLTQDR_STXSTSF_Pos) /*!< 0x00700000 */

+#define ETH_MTLTQDR_STXSTSF                           ETH_MTLTQDR_STXSTSF_Msk  /* Number of Status Words in the Tx Status FIFO of Queue */

+#define ETH_MTLTQDR_PTXQ_Pos                          (16U)

+#define ETH_MTLTQDR_PTXQ_Msk                          (0x7UL << ETH_MTLTQDR_PTXQ_Pos) /*!< 0x00070000 */

+#define ETH_MTLTQDR_PTXQ                              ETH_MTLTQDR_PTXQ_Msk     /* Number of Packets in the Transmit Queue */

+#define ETH_MTLTQDR_TXSTSFSTS_Pos                     (5U)

+#define ETH_MTLTQDR_TXSTSFSTS_Msk                     (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos) /*!< 0x00000020 */

+#define ETH_MTLTQDR_TXSTSFSTS                         ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */

+#define ETH_MTLTQDR_TXQSTS_Pos                        (4U)

+#define ETH_MTLTQDR_TXQSTS_Msk                        (0x1UL << ETH_MTLTQDR_TXQSTS_Pos) /*!< 0x00000010 */

+#define ETH_MTLTQDR_TXQSTS                            ETH_MTLTQDR_TXQSTS_Msk   /* MTL Tx Queue Not Empty Status */

+#define ETH_MTLTQDR_TWCSTS_Pos                        (3U)

+#define ETH_MTLTQDR_TWCSTS_Msk                        (0x1UL << ETH_MTLTQDR_TWCSTS_Pos) /*!< 0x00000008 */

+#define ETH_MTLTQDR_TWCSTS                            ETH_MTLTQDR_TWCSTS_Msk   /* MTL Tx Queue Write Controller Status */

+#define ETH_MTLTQDR_TRCSTS_Pos                        (1U)

+#define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */

+#define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */

+#define ETH_MTLTQDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */

+#define ETH_MTLTQDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */

+#define ETH_MTLTQDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */

+#define ETH_MTLTQDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */

+#define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)

+#define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */

+#define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */

+

+/* Bit definition for Ethernet MTL Queue Interrupt Control Status Register */

+#define ETH_MTLQICSR_RXOIE_Pos                        (24U)

+#define ETH_MTLQICSR_RXOIE_Msk                        (0x1UL << ETH_MTLQICSR_RXOIE_Pos) /*!< 0x01000000 */

+#define ETH_MTLQICSR_RXOIE                            ETH_MTLQICSR_RXOIE_Msk   /* Receive Queue Overflow Interrupt Enable */

+#define ETH_MTLQICSR_RXOVFIS_Pos                      (16U)

+#define ETH_MTLQICSR_RXOVFIS_Msk                      (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos) /*!< 0x00010000 */

+#define ETH_MTLQICSR_RXOVFIS                          ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */

+#define ETH_MTLQICSR_TXUIE_Pos                        (8U)

+#define ETH_MTLQICSR_TXUIE_Msk                        (0x1UL << ETH_MTLQICSR_TXUIE_Pos) /*!< 0x00000100 */

+#define ETH_MTLQICSR_TXUIE                            ETH_MTLQICSR_TXUIE_Msk   /* Transmit Queue Underflow Interrupt Enable */

+#define ETH_MTLQICSR_TXUNFIS_Pos                      (0U)

+#define ETH_MTLQICSR_TXUNFIS_Msk                      (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos) /*!< 0x00000001 */

+#define ETH_MTLQICSR_TXUNFIS                          ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */

+

+/* Bit definition for Ethernet MTL Rx Queue Operation Mode Register */

+#define ETH_MTLRQOMR_RQS_Pos                          (20U)

+#define ETH_MTLRQOMR_RQS_Msk                          (0x7UL << ETH_MTLRQOMR_RQS_Pos) /*!< 0x00700000 */

+#define ETH_MTLRQOMR_RQS                              ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */

+#define ETH_MTLRQOMR_RFD_Pos                          (14U)

+#define ETH_MTLRQOMR_RFD_Msk                          (0x7UL << ETH_MTLRQOMR_RFD_Pos) /*!< 0x0001C000 */

+#define ETH_MTLRQOMR_RFD                              ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */

+#define ETH_MTLRQOMR_RFA_Pos                          (8U)

+#define ETH_MTLRQOMR_RFA_Msk                          (0x7UL << ETH_MTLRQOMR_RFA_Pos) /*!< 0x00000700 */

+#define ETH_MTLRQOMR_RFA                              ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */

+#define ETH_MTLRQOMR_EHFC_Pos                         (7U)

+#define ETH_MTLRQOMR_EHFC_Msk                         (0x1UL << ETH_MTLRQOMR_EHFC_Pos) /*!< 0x00000080 */

+#define ETH_MTLRQOMR_EHFC                             ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */

+#define ETH_MTLRQOMR_DISTCPEF_Pos                     (6U)

+#define ETH_MTLRQOMR_DISTCPEF_Msk                     (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos) /*!< 0x00000040 */

+#define ETH_MTLRQOMR_DISTCPEF                         ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */

+#define ETH_MTLRQOMR_RSF_Pos                          (5U)

+#define ETH_MTLRQOMR_RSF_Msk                          (0x1UL << ETH_MTLRQOMR_RSF_Pos) /*!< 0x00000020 */

+#define ETH_MTLRQOMR_RSF                              ETH_MTLRQOMR_RSF_Msk     /* Receive Queue Store and Forward */

+#define ETH_MTLRQOMR_FEP_Pos                          (4U)

+#define ETH_MTLRQOMR_FEP_Msk                          (0x1UL << ETH_MTLRQOMR_FEP_Pos) /*!< 0x00000010 */

+#define ETH_MTLRQOMR_FEP                              ETH_MTLRQOMR_FEP_Msk     /* Forward Error Packets */

+#define ETH_MTLRQOMR_FUP_Pos                          (3U)

+#define ETH_MTLRQOMR_FUP_Msk                          (0x1UL << ETH_MTLRQOMR_FUP_Pos) /*!< 0x00000008 */

+#define ETH_MTLRQOMR_FUP                              ETH_MTLRQOMR_FUP_Msk     /* Forward Undersized Good Packets */

+#define ETH_MTLRQOMR_RTC_Pos                          (0U)

+#define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */

+#define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */

+#define ETH_MTLRQOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */

+#define ETH_MTLRQOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */

+#define ETH_MTLRQOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */

+#define ETH_MTLRQOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */

+

+/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */

+#define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)

+#define ETH_MTLRQMPOCR_MISCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */

+#define ETH_MTLRQMPOCR_MISCNTOVF                      ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */

+#define ETH_MTLRQMPOCR_MISPKTCNT_Pos                  (16U)

+#define ETH_MTLRQMPOCR_MISPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */

+#define ETH_MTLRQMPOCR_MISPKTCNT                      ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */

+#define ETH_MTLRQMPOCR_OVFCNTOVF_Pos                  (11U)

+#define ETH_MTLRQMPOCR_OVFCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */

+#define ETH_MTLRQMPOCR_OVFCNTOVF                      ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */

+#define ETH_MTLRQMPOCR_OVFPKTCNT_Pos                  (0U)

+#define ETH_MTLRQMPOCR_OVFPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */

+#define ETH_MTLRQMPOCR_OVFPKTCNT                      ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */

+

+/* Bit definition for Ethernet MTL Rx Queue Debug Register */

+#define ETH_MTLRQDR_PRXQ_Pos                          (16U)

+#define ETH_MTLRQDR_PRXQ_Msk                          (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos) /*!< 0x3FFF0000 */

+#define ETH_MTLRQDR_PRXQ                              ETH_MTLRQDR_PRXQ_Msk     /* Number of Packets in Receive Queue */

+#define ETH_MTLRQDR_RXQSTS_Pos                        (4U)

+#define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */

+#define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */

+#define ETH_MTLRQDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */

+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)

+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */

+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */

+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos         (5U)

+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */

+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD             ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */

+#define ETH_MTLRQDR_RXQSTS_FULL_Pos                   (4U)

+#define ETH_MTLRQDR_RXQSTS_FULL_Msk                   (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */

+#define ETH_MTLRQDR_RXQSTS_FULL                       ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */

+#define ETH_MTLRQDR_RRCSTS_Pos                        (1U)

+#define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */

+#define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */

+#define ETH_MTLRQDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */

+#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)

+#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */

+#define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */

+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos          (2U)

+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk          (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */

+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS              ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */

+#define ETH_MTLRQDR_RRCSTS_FLUSHING_Pos               (1U)

+#define ETH_MTLRQDR_RRCSTS_FLUSHING_Msk               (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */

+#define ETH_MTLRQDR_RRCSTS_FLUSHING                   ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */

+#define ETH_MTLRQDR_RWCSTS_Pos                        (0U)

+#define ETH_MTLRQDR_RWCSTS_Msk                        (0x1UL << ETH_MTLRQDR_RWCSTS_Pos) /*!< 0x00000001 */

+#define ETH_MTLRQDR_RWCSTS                            ETH_MTLRQDR_RWCSTS_Msk   /* MTL Rx Queue Write Controller Active Status */

+

+/* Bit definition for Ethernet MTL Rx Queue Control Register */

+#define ETH_MTLRQCR_RQPA_Pos                          (3U)

+#define ETH_MTLRQCR_RQPA_Msk                          (0x1UL << ETH_MTLRQCR_RQPA_Pos) /*!< 0x00000008 */

+#define ETH_MTLRQCR_RQPA                              ETH_MTLRQCR_RQPA_Msk     /* Receive Queue Packet Arbitration */

+#define ETH_MTLRQCR_RQW_Pos                           (0U)

+#define ETH_MTLRQCR_RQW_Msk                           (0x7UL << ETH_MTLRQCR_RQW_Pos) /*!< 0x00000007 */

+#define ETH_MTLRQCR_RQW                               ETH_MTLRQCR_RQW_Msk      /* Receive Queue Weight */

+

+/* Bit definition for Ethernet DMA Mode Register */

+#define ETH_DMAMR_INTM_Pos                            (16U)

+#define ETH_DMAMR_INTM_Msk                            (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */

+#define ETH_DMAMR_INTM                                ETH_DMAMR_INTM_Msk       /* This field defines the interrupt mode */

+#define ETH_DMAMR_INTM_0                              (0x0UL << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */

+#define ETH_DMAMR_INTM_1                              (0x1UL << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */

+#define ETH_DMAMR_INTM_2                              (0x2UL << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */

+#define ETH_DMAMR_PR_Pos                              (12U)

+#define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */

+#define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */

+#define ETH_DMAMR_PR_1_1                              ((uint32_t)0x00000000)   /* The priority ratio is 1:1 */

+#define ETH_DMAMR_PR_2_1                              ((uint32_t)0x00001000)   /* The priority ratio is 2:1 */

+#define ETH_DMAMR_PR_3_1                              ((uint32_t)0x00002000)   /* The priority ratio is 3:1 */

+#define ETH_DMAMR_PR_4_1                              ((uint32_t)0x00003000)   /* The priority ratio is 4:1 */

+#define ETH_DMAMR_PR_5_1                              ((uint32_t)0x00004000)   /* The priority ratio is 5:1 */

+#define ETH_DMAMR_PR_6_1                              ((uint32_t)0x00005000)   /* The priority ratio is 6:1 */

+#define ETH_DMAMR_PR_7_1                              ((uint32_t)0x00006000)   /* The priority ratio is 7:1 */

+#define ETH_DMAMR_PR_8_1                              ((uint32_t)0x00007000)   /* The priority ratio is 8:1 */

+#define ETH_DMAMR_TXPR_Pos                            (11U)

+#define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */

+#define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */

+#define ETH_DMAMR_DA_Pos                              (1U)

+#define ETH_DMAMR_DA_Msk                              (0x1UL << ETH_DMAMR_DA_Pos) /*!< 0x00000002 */

+#define ETH_DMAMR_DA                                  ETH_DMAMR_DA_Msk         /* DMA Tx or Rx Arbitration Scheme */

+#define ETH_DMAMR_SWR_Pos                             (0U)

+#define ETH_DMAMR_SWR_Msk                             (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */

+#define ETH_DMAMR_SWR                                 ETH_DMAMR_SWR_Msk        /* Software Reset */

+

+/* Bit definition for Ethernet DMA SysBus Mode Register */

+#define ETH_DMASBMR_RB_Pos                            (15U)

+#define ETH_DMASBMR_RB_Msk                            (0x1UL << ETH_DMASBMR_RB_Pos) /*!< 0x00008000 */

+#define ETH_DMASBMR_RB                                ETH_DMASBMR_RB_Msk       /* Rebuild INCRx Burst */

+#define ETH_DMASBMR_MB_Pos                            (14U)

+#define ETH_DMASBMR_MB_Msk                            (0x1UL << ETH_DMASBMR_MB_Pos) /*!< 0x00004000 */

+#define ETH_DMASBMR_MB                                ETH_DMASBMR_MB_Msk       /* Mixed Burst */

+#define ETH_DMASBMR_AAL_Pos                           (12U)

+#define ETH_DMASBMR_AAL_Msk                           (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */

+#define ETH_DMASBMR_AAL                               ETH_DMASBMR_AAL_Msk      /* Address-Aligned Beats */

+#define ETH_DMASBMR_FB_Pos                            (0U)

+#define ETH_DMASBMR_FB_Msk                            (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */

+#define ETH_DMASBMR_FB                                ETH_DMASBMR_FB_Msk       /* Fixed Burst Length */

+

+/* Bit definition for Ethernet DMA Interrupt Status Register */

+#define ETH_DMAISR_MACIS_Pos                          (17U)

+#define ETH_DMAISR_MACIS_Msk                          (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */

+#define ETH_DMAISR_MACIS                              ETH_DMAISR_MACIS_Msk     /* MAC Interrupt Status */

+#define ETH_DMAISR_MTLIS_Pos                          (16U)

+#define ETH_DMAISR_MTLIS_Msk                          (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */

+#define ETH_DMAISR_MTLIS                              ETH_DMAISR_MTLIS_Msk     /* MAC Interrupt Status */

+#define ETH_DMAISR_DMACIS_Pos                         (0U)

+#define ETH_DMAISR_DMACIS_Msk                         (0x1UL << ETH_DMAISR_DMACIS_Pos) /*!< 0x00000001 */

+#define ETH_DMAISR_DMACIS                             ETH_DMAISR_DMACIS_Msk    /* DMA Channel Interrupt Status */

+

+/* Bit definition for Ethernet DMA Debug Status Register */

+#define ETH_DMADSR_TPS_Pos                            (12U)

+#define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */

+#define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */

+#define ETH_DMADSR_TPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */

+#define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)

+#define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */

+#define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */

+#define ETH_DMADSR_TPS_WAITING_Pos                    (13U)

+#define ETH_DMADSR_TPS_WAITING_Msk                    (0x1UL << ETH_DMADSR_TPS_WAITING_Pos) /*!< 0x00002000 */

+#define ETH_DMADSR_TPS_WAITING                        ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */

+#define ETH_DMADSR_TPS_READING_Pos                    (12U)

+#define ETH_DMADSR_TPS_READING_Msk                    (0x3UL << ETH_DMADSR_TPS_READING_Pos) /*!< 0x00003000 */

+#define ETH_DMADSR_TPS_READING                        ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */

+#define ETH_DMADSR_TPS_TIMESTAMP_WR_Pos               (14U)

+#define ETH_DMADSR_TPS_TIMESTAMP_WR_Msk               (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos) /*!< 0x00004000 */

+#define ETH_DMADSR_TPS_TIMESTAMP_WR                   ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */

+#define ETH_DMADSR_TPS_SUSPENDED_Pos                  (13U)

+#define ETH_DMADSR_TPS_SUSPENDED_Msk                  (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos) /*!< 0x00006000 */

+#define ETH_DMADSR_TPS_SUSPENDED                      ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */

+#define ETH_DMADSR_TPS_CLOSING_Pos                    (12U)

+#define ETH_DMADSR_TPS_CLOSING_Msk                    (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos) /*!< 0x00007000 */

+#define ETH_DMADSR_TPS_CLOSING                        ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */

+#define ETH_DMADSR_RPS_Pos                            (8U)

+#define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */

+#define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */

+#define ETH_DMADSR_RPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */

+#define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)

+#define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */

+#define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */

+#define ETH_DMADSR_RPS_WAITING_Pos                    (12U)

+#define ETH_DMADSR_RPS_WAITING_Msk                    (0x3UL << ETH_DMADSR_RPS_WAITING_Pos) /*!< 0x00003000 */

+#define ETH_DMADSR_RPS_WAITING                        ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */

+#define ETH_DMADSR_RPS_SUSPENDED_Pos                  (14U)

+#define ETH_DMADSR_RPS_SUSPENDED_Msk                  (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos) /*!< 0x00004000 */

+#define ETH_DMADSR_RPS_SUSPENDED                      ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */

+#define ETH_DMADSR_RPS_CLOSING_Pos                    (12U)

+#define ETH_DMADSR_RPS_CLOSING_Msk                    (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos) /*!< 0x00005000 */

+#define ETH_DMADSR_RPS_CLOSING                        ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */

+#define ETH_DMADSR_RPS_TIMESTAMP_WR_Pos               (13U)

+#define ETH_DMADSR_RPS_TIMESTAMP_WR_Msk               (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos) /*!< 0x00006000 */

+#define ETH_DMADSR_RPS_TIMESTAMP_WR                   ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */

+#define ETH_DMADSR_RPS_TRANSFERRING_Pos               (12U)

+#define ETH_DMADSR_RPS_TRANSFERRING_Msk               (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos) /*!< 0x00007000 */

+#define ETH_DMADSR_RPS_TRANSFERRING                   ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */

+

+/* Bit definition for Ethernet DMA Channel Control Register */

+#define ETH_DMACCR_DSL_Pos                            (18U)

+#define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */

+#define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */

+#define ETH_DMACCR_DSL_0BIT                           ((uint32_t)0x00000000)

+#define ETH_DMACCR_DSL_32BIT                          ((uint32_t)0x00040000)

+#define ETH_DMACCR_DSL_64BIT                          ((uint32_t)0x00080000)

+#define ETH_DMACCR_DSL_128BIT                         ((uint32_t)0x00100000)

+#define ETH_DMACCR_8PBL                               ((uint32_t)0x00010000)   /* 8xPBL mode */

+#define ETH_DMACCR_MSS_Pos                            (0U)

+#define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */

+#define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */

+

+/* Bit definition for Ethernet DMA Channel Tx Control Register */

+#define ETH_DMACTCR_TPBL_Pos                          (16U)

+#define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */

+#define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */

+#define ETH_DMACTCR_TPBL_1PBL                         ((uint32_t)0x00010000)   /* Transmit Programmable Burst Length 1 */

+#define ETH_DMACTCR_TPBL_2PBL                         ((uint32_t)0x00020000)   /* Transmit Programmable Burst Length 2 */

+#define ETH_DMACTCR_TPBL_4PBL                         ((uint32_t)0x00040000)   /* Transmit Programmable Burst Length 4 */

+#define ETH_DMACTCR_TPBL_8PBL                         ((uint32_t)0x00080000)   /* Transmit Programmable Burst Length 8 */

+#define ETH_DMACTCR_TPBL_16PBL                        ((uint32_t)0x00100000)   /* Transmit Programmable Burst Length 16 */

+#define ETH_DMACTCR_TPBL_32PBL                        ((uint32_t)0x00200000)   /* Transmit Programmable Burst Length 32 */

+#define ETH_DMACTCR_TSE_Pos                           (12U)

+#define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */

+#define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */

+#define ETH_DMACTCR_OSP_Pos                           (4U)

+#define ETH_DMACTCR_OSP_Msk                           (0x1UL << ETH_DMACTCR_OSP_Pos) /*!< 0x00000010 */

+#define ETH_DMACTCR_OSP                               ETH_DMACTCR_OSP_Msk      /* Operate on Second Packet */

+#define ETH_DMACTCR_ST_Pos                            (0U)

+#define ETH_DMACTCR_ST_Msk                            (0x1UL << ETH_DMACTCR_ST_Pos) /*!< 0x00000001 */

+#define ETH_DMACTCR_ST                                ETH_DMACTCR_ST_Msk       /* Start or Stop Transmission Command */

+

+/* Bit definition for Ethernet DMA Channel Rx Control Register */

+#define ETH_DMACRCR_RPF_Pos                           (31U)

+#define ETH_DMACRCR_RPF_Msk                           (0x1UL << ETH_DMACRCR_RPF_Pos) /*!< 0x80000000 */

+#define ETH_DMACRCR_RPF                               ETH_DMACRCR_RPF_Msk      /* Rx Packet Flush */

+#define ETH_DMACRCR_RPBL_Pos                          (16U)

+#define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */

+#define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */

+#define ETH_DMACRCR_RPBL_1PBL                         ((uint32_t)0x00010000)   /* Receive Programmable Burst Length 1 */

+#define ETH_DMACRCR_RPBL_2PBL                         ((uint32_t)0x00020000)   /* Receive Programmable Burst Length 2 */

+#define ETH_DMACRCR_RPBL_4PBL                         ((uint32_t)0x00040000)   /* Receive Programmable Burst Length 4 */

+#define ETH_DMACRCR_RPBL_8PBL                         ((uint32_t)0x00080000)   /* Receive Programmable Burst Length 8 */

+#define ETH_DMACRCR_RPBL_16PBL                        ((uint32_t)0x00100000)   /* Receive Programmable Burst Length 16 */

+#define ETH_DMACRCR_RPBL_32PBL                        ((uint32_t)0x00200000)   /* Receive Programmable Burst Length 32 */

+#define ETH_DMACRCR_RBSZ_Pos                          (1U)

+#define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */

+#define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */

+#define ETH_DMACRCR_SR_Pos                            (0U)

+#define ETH_DMACRCR_SR_Msk                            (0x1UL << ETH_DMACRCR_SR_Pos) /*!< 0x00000001 */

+#define ETH_DMACRCR_SR                                ETH_DMACRCR_SR_Msk       /* Start or Stop Receive */

+

+/* Bit definition for Ethernet DMA CH Tx Desc List Address Register */

+#define ETH_DMACTDLAR_TDESLA_Pos                      (2U)

+#define ETH_DMACTDLAR_TDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACTDLAR_TDESLA                          ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */

+

+/* Bit definition for Ethernet DMA CH Rx Desc List Address Register */

+#define ETH_DMACRDLAR_RDESLA_Pos                      (2U)

+#define ETH_DMACRDLAR_RDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACRDLAR_RDESLA                          ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */

+

+/* Bit definition for Ethernet DMA CH Tx Desc Tail Pointer Register */

+#define ETH_DMACTDTPR_TDT_Pos                         (2U)

+#define ETH_DMACTDTPR_TDT_Msk                         (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACTDTPR_TDT                             ETH_DMACTDTPR_TDT_Msk    /* Transmit Descriptor Tail Pointer */

+

+/* Bit definition for Ethernet DMA CH Rx Desc Tail Pointer Register */

+#define ETH_DMACRDTPR_RDT_Pos                         (2U)

+#define ETH_DMACRDTPR_RDT_Msk                         (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACRDTPR_RDT                             ETH_DMACRDTPR_RDT_Msk    /* Receive Descriptor Tail Pointer */

+

+/* Bit definition for Ethernet DMA CH Tx Desc Ring Length Register */

+#define ETH_DMACTDRLR_TDRL_Pos                        (0U)

+#define ETH_DMACTDRLR_TDRL_Msk                        (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos) /*!< 0x000003FF */

+#define ETH_DMACTDRLR_TDRL                            ETH_DMACTDRLR_TDRL_Msk   /* Transmit Descriptor Ring Length */

+

+/* Bit definition for Ethernet DMA CH Rx Desc Ring Length Register */

+#define ETH_DMACRDRLR_RDRL_Pos                        (0U)

+#define ETH_DMACRDRLR_RDRL_Msk                        (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos) /*!< 0x000003FF */

+#define ETH_DMACRDRLR_RDRL                            ETH_DMACRDRLR_RDRL_Msk   /* Receive Descriptor Ring Length */

+

+/* Bit definition for Ethernet DMA Channel Interrupt Enable Register */

+#define ETH_DMACIER_NIE_Pos                           (15U)

+#define ETH_DMACIER_NIE_Msk                           (0x1UL << ETH_DMACIER_NIE_Pos) /*!< 0x00008000 */

+#define ETH_DMACIER_NIE                               ETH_DMACIER_NIE_Msk      /* Normal Interrupt Summary Enable */

+#define ETH_DMACIER_AIE_Pos                           (14U)

+#define ETH_DMACIER_AIE_Msk                           (0x1UL << ETH_DMACIER_AIE_Pos) /*!< 0x00004000 */

+#define ETH_DMACIER_AIE                               ETH_DMACIER_AIE_Msk      /* Abnormal Interrupt Summary Enable */

+#define ETH_DMACIER_CDEE_Pos                          (13U)

+#define ETH_DMACIER_CDEE_Msk                          (0x1UL << ETH_DMACIER_CDEE_Pos) /*!< 0x00002000 */

+#define ETH_DMACIER_CDEE                              ETH_DMACIER_CDEE_Msk     /* Context Descriptor Error Enable */

+#define ETH_DMACIER_FBEE_Pos                          (12U)

+#define ETH_DMACIER_FBEE_Msk                          (0x1UL << ETH_DMACIER_FBEE_Pos) /*!< 0x00001000 */

+#define ETH_DMACIER_FBEE                              ETH_DMACIER_FBEE_Msk     /* Fatal Bus Error Enable */

+#define ETH_DMACIER_ERIE_Pos                          (11U)

+#define ETH_DMACIER_ERIE_Msk                          (0x1UL << ETH_DMACIER_ERIE_Pos) /*!< 0x00000800 */

+#define ETH_DMACIER_ERIE                              ETH_DMACIER_ERIE_Msk     /* Early Receive Interrupt Enable */

+#define ETH_DMACIER_ETIE_Pos                          (10U)

+#define ETH_DMACIER_ETIE_Msk                          (0x1UL << ETH_DMACIER_ETIE_Pos) /*!< 0x00000400 */

+#define ETH_DMACIER_ETIE                              ETH_DMACIER_ETIE_Msk     /* Early Transmit Interrupt Enable */

+#define ETH_DMACIER_RWTE_Pos                          (9U)

+#define ETH_DMACIER_RWTE_Msk                          (0x1UL << ETH_DMACIER_RWTE_Pos) /*!< 0x00000200 */

+#define ETH_DMACIER_RWTE                              ETH_DMACIER_RWTE_Msk     /* Receive Watchdog Timeout Enable */

+#define ETH_DMACIER_RSE_Pos                           (8U)

+#define ETH_DMACIER_RSE_Msk                           (0x1UL << ETH_DMACIER_RSE_Pos) /*!< 0x00000100 */

+#define ETH_DMACIER_RSE                               ETH_DMACIER_RSE_Msk      /* Receive Stopped Enable */

+#define ETH_DMACIER_RBUE_Pos                          (7U)

+#define ETH_DMACIER_RBUE_Msk                          (0x1UL << ETH_DMACIER_RBUE_Pos) /*!< 0x00000080 */

+#define ETH_DMACIER_RBUE                              ETH_DMACIER_RBUE_Msk     /* Receive Buffer Unavailable Enable */

+#define ETH_DMACIER_RIE_Pos                           (6U)

+#define ETH_DMACIER_RIE_Msk                           (0x1UL << ETH_DMACIER_RIE_Pos) /*!< 0x00000040 */

+#define ETH_DMACIER_RIE                               ETH_DMACIER_RIE_Msk      /* Receive Interrupt Enable */

+#define ETH_DMACIER_TBUE_Pos                          (2U)

+#define ETH_DMACIER_TBUE_Msk                          (0x1UL << ETH_DMACIER_TBUE_Pos) /*!< 0x00000004 */

+#define ETH_DMACIER_TBUE                              ETH_DMACIER_TBUE_Msk     /* Transmit Buffer Unavailable Enable */

+#define ETH_DMACIER_TXSE_Pos                          (1U)

+#define ETH_DMACIER_TXSE_Msk                          (0x1UL << ETH_DMACIER_TXSE_Pos) /*!< 0x00000002 */

+#define ETH_DMACIER_TXSE                              ETH_DMACIER_TXSE_Msk     /* Transmit Stopped Enable */

+#define ETH_DMACIER_TIE_Pos                           (0U)

+#define ETH_DMACIER_TIE_Msk                           (0x1UL << ETH_DMACIER_TIE_Pos) /*!< 0x00000001 */

+#define ETH_DMACIER_TIE                               ETH_DMACIER_TIE_Msk      /* Transmit Interrupt Enable */

+

+/* Bit definition for Ethernet DMA Channel Rx Interrupt Watchdog Timer Register */

+#define ETH_DMACRIWTR_RWT_Pos                         (0U)

+#define ETH_DMACRIWTR_RWT_Msk                         (0xFFUL << ETH_DMACRIWTR_RWT_Pos) /*!< 0x000000FF */

+#define ETH_DMACRIWTR_RWT                             ETH_DMACRIWTR_RWT_Msk    /* Receive Interrupt Watchdog Timer Count */

+

+/* Bit definition for Ethernet DMA Channel Current App Tx Desc Register */

+#define ETH_DMACCATDR_CURTDESAPTR_Pos                 (0U)

+#define ETH_DMACCATDR_CURTDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCATDR_CURTDESAPTR                     ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Current App Rx Desc Register */

+#define ETH_DMACCARDR_CURRDESAPTR_Pos                 (0U)

+#define ETH_DMACCARDR_CURRDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCARDR_CURRDESAPTR                     ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Current App Tx Buffer Register */

+#define ETH_DMACCATBR_CURTBUFAPTR_Pos                 (0U)

+#define ETH_DMACCATBR_CURTBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCATBR_CURTBUFAPTR                     ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Current App Rx Buffer Register */

+#define ETH_DMACCARBR_CURRBUFAPTR_Pos                 (0U)

+#define ETH_DMACCARBR_CURRBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCARBR_CURRBUFAPTR                     ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Status Register */

+#define ETH_DMACSR_REB_Pos                            (19U)

+#define ETH_DMACSR_REB_Msk                            (0x7UL << ETH_DMACSR_REB_Pos) /*!< 0x00380000 */

+#define ETH_DMACSR_REB                                ETH_DMACSR_REB_Msk       /* Rx DMA Error Bits */

+#define ETH_DMACSR_TEB_Pos                            (16U)

+#define ETH_DMACSR_TEB_Msk                            (0x7UL << ETH_DMACSR_TEB_Pos) /*!< 0x00070000 */

+#define ETH_DMACSR_TEB                                ETH_DMACSR_TEB_Msk       /* Tx DMA Error Bits */

+#define ETH_DMACSR_NIS_Pos                            (15U)

+#define ETH_DMACSR_NIS_Msk                            (0x1UL << ETH_DMACSR_NIS_Pos) /*!< 0x00008000 */

+#define ETH_DMACSR_NIS                                ETH_DMACSR_NIS_Msk       /* Normal Interrupt Summary */

+#define ETH_DMACSR_AIS_Pos                            (14U)

+#define ETH_DMACSR_AIS_Msk                            (0x1UL << ETH_DMACSR_AIS_Pos) /*!< 0x00004000 */

+#define ETH_DMACSR_AIS                                ETH_DMACSR_AIS_Msk       /* Abnormal Interrupt Summary */

+#define ETH_DMACSR_CDE_Pos                            (13U)

+#define ETH_DMACSR_CDE_Msk                            (0x1UL << ETH_DMACSR_CDE_Pos) /*!< 0x00002000 */

+#define ETH_DMACSR_CDE                                ETH_DMACSR_CDE_Msk       /* Context Descriptor Error */

+#define ETH_DMACSR_FBE_Pos                            (12U)

+#define ETH_DMACSR_FBE_Msk                            (0x1UL << ETH_DMACSR_FBE_Pos) /*!< 0x00001000 */

+#define ETH_DMACSR_FBE                                ETH_DMACSR_FBE_Msk       /* Fatal Bus Error */

+#define ETH_DMACSR_ERI_Pos                            (11U)

+#define ETH_DMACSR_ERI_Msk                            (0x1UL << ETH_DMACSR_ERI_Pos) /*!< 0x00000800 */

+#define ETH_DMACSR_ERI                                ETH_DMACSR_ERI_Msk       /* Early Receive Interrupt */

+#define ETH_DMACSR_ETI_Pos                            (10U)

+#define ETH_DMACSR_ETI_Msk                            (0x1UL << ETH_DMACSR_ETI_Pos) /*!< 0x00000400 */

+#define ETH_DMACSR_ETI                                ETH_DMACSR_ETI_Msk       /* Early Transmit Interrupt */

+#define ETH_DMACSR_RWT_Pos                            (9U)

+#define ETH_DMACSR_RWT_Msk                            (0x1UL << ETH_DMACSR_RWT_Pos) /*!< 0x00000200 */

+#define ETH_DMACSR_RWT                                ETH_DMACSR_RWT_Msk       /* Receive Watchdog Timeout */

+#define ETH_DMACSR_RPS_Pos                            (8U)

+#define ETH_DMACSR_RPS_Msk                            (0x1UL << ETH_DMACSR_RPS_Pos) /*!< 0x00000100 */

+#define ETH_DMACSR_RPS                                ETH_DMACSR_RPS_Msk       /* Receive Process Stopped */

+#define ETH_DMACSR_RBU_Pos                            (7U)

+#define ETH_DMACSR_RBU_Msk                            (0x1UL << ETH_DMACSR_RBU_Pos) /*!< 0x00000080 */

+#define ETH_DMACSR_RBU                                ETH_DMACSR_RBU_Msk       /* Receive Buffer Unavailable */

+#define ETH_DMACSR_RI_Pos                             (6U)

+#define ETH_DMACSR_RI_Msk                             (0x1UL << ETH_DMACSR_RI_Pos) /*!< 0x00000040 */

+#define ETH_DMACSR_RI                                 ETH_DMACSR_RI_Msk        /* Receive Interrupt */

+#define ETH_DMACSR_TBU_Pos                            (2U)

+#define ETH_DMACSR_TBU_Msk                            (0x1UL << ETH_DMACSR_TBU_Pos) /*!< 0x00000004 */

+#define ETH_DMACSR_TBU                                ETH_DMACSR_TBU_Msk       /* Transmit Buffer Unavailable */

+#define ETH_DMACSR_TPS_Pos                            (1U)

+#define ETH_DMACSR_TPS_Msk                            (0x1UL << ETH_DMACSR_TPS_Pos) /*!< 0x00000002 */

+#define ETH_DMACSR_TPS                                ETH_DMACSR_TPS_Msk       /* Transmit Process Stopped */

+#define ETH_DMACSR_TI_Pos                             (0U)

+#define ETH_DMACSR_TI_Msk                             (0x1UL << ETH_DMACSR_TI_Pos) /*!< 0x00000001 */

+#define ETH_DMACSR_TI                                 ETH_DMACSR_TI_Msk        /* Transmit Interrupt */

+

+/* Bit definition for Ethernet DMA Channel missed frame count register */

+#define ETH_DMACMFCR_MFCO_Pos                         (15U)

+#define ETH_DMACMFCR_MFCO_Msk                         (0x1UL << ETH_DMACMFCR_MFCO_Pos) /*!< 0x00008000 */

+#define ETH_DMACMFCR_MFCO                             ETH_DMACMFCR_MFCO_Msk    /* Overflow status of the MFC Counter */

+#define ETH_DMACMFCR_MFC_Pos                          (0U)

+#define ETH_DMACMFCR_MFC_Msk                          (0x7FFUL << ETH_DMACMFCR_MFC_Pos) /*!< 0x000007FF */

+#define ETH_DMACMFCR_MFC                              ETH_DMACMFCR_MFC_Msk     /* The number of packet counters dropped by the DMA */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             DMA Controller                                 */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DMA_SxCR register  *****************/

+#define DMA_SxCR_MBURST_Pos      (23U)

+#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                /*!< 0x01800000 */

+#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk                           /*!< Memory burst transfer configuration */

+#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */

+#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */

+#define DMA_SxCR_PBURST_Pos      (21U)

+#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                /*!< 0x00600000 */

+#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk                           /*!< Peripheral burst transfer configuration */

+#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */

+#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */

+#define DMA_SxCR_TRBUFF_Pos      (20U)

+#define DMA_SxCR_TRBUFF_Msk      (0x1UL << DMA_SxCR_TRBUFF_Pos)                 /*!< 0x00100000 */

+#define DMA_SxCR_TRBUFF          DMA_SxCR_TRBUFF_Msk                            /*!< bufferable transfers enabled/disable */

+#define DMA_SxCR_CT_Pos          (19U)

+#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                    /*!< 0x00080000 */

+#define DMA_SxCR_CT              DMA_SxCR_CT_Msk                               /*!< Current target (only in double buffer mode) */

+#define DMA_SxCR_DBM_Pos         (18U)

+#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                   /*!< 0x00040000 */

+#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk                              /*!< Double buffer mode */

+#define DMA_SxCR_PL_Pos          (16U)

+#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                    /*!< 0x00030000 */

+#define DMA_SxCR_PL              DMA_SxCR_PL_Msk                               /*!< Priority level */

+#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */

+#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */

+#define DMA_SxCR_PINCOS_Pos      (15U)

+#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                /*!< 0x00008000 */

+#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk                           /*!< Peripheral increment offset size */

+#define DMA_SxCR_MSIZE_Pos       (13U)

+#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                 /*!< 0x00006000 */

+#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk                            /*!< Memory data size */

+#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */

+#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */

+#define DMA_SxCR_PSIZE_Pos       (11U)

+#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                 /*!< 0x00001800 */

+#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk                            /*< Peripheral data size */

+#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */

+#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */

+#define DMA_SxCR_MINC_Pos        (10U)

+#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                  /*!< 0x00000400 */

+#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk                             /*!< Memory increment mode */

+#define DMA_SxCR_PINC_Pos        (9U)

+#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                  /*!< 0x00000200 */

+#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk                             /*!< Peripheral increment mode */

+#define DMA_SxCR_CIRC_Pos        (8U)

+#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                  /*!< 0x00000100 */

+#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk                             /*!< Circular mode */

+#define DMA_SxCR_DIR_Pos         (6U)

+#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                   /*!< 0x000000C0 */

+#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk                              /*!< Data transfer direction */

+#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */

+#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */

+#define DMA_SxCR_PFCTRL_Pos      (5U)

+#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                /*!< 0x00000020 */

+#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk                           /*!< Peripheral flow controller */

+#define DMA_SxCR_TCIE_Pos        (4U)

+#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                  /*!< 0x00000010 */

+#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk                             /*!< Transfer complete interrupt enable */

+#define DMA_SxCR_HTIE_Pos        (3U)

+#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                  /*!< 0x00000008 */

+#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk                             /*!< Half transfer interrupt enable */

+#define DMA_SxCR_TEIE_Pos        (2U)

+#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                  /*!< 0x00000004 */

+#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk                             /*!< Transfer error interrupt enable */

+#define DMA_SxCR_DMEIE_Pos       (1U)

+#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                 /*!< 0x00000002 */

+#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk                            /*!< Direct mode error interrupt enable */

+#define DMA_SxCR_EN_Pos          (0U)

+#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                    /*!< 0x00000001 */

+#define DMA_SxCR_EN              DMA_SxCR_EN_Msk                               /*!< Stream enable / flag stream ready when read low */

+

+/********************  Bits definition for DMA_SxCNDTR register  **************/

+#define DMA_SxNDT_Pos            (0U)

+#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                   /*!< 0x0000FFFF */

+#define DMA_SxNDT                DMA_SxNDT_Msk                                 /*!< Number of data items to transfer */

+#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */

+#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */

+#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */

+#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */

+#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */

+#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */

+#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */

+#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */

+#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */

+#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */

+#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */

+#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */

+#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */

+#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */

+#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */

+#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */

+

+/********************  Bits definition for DMA_SxFCR register  ****************/

+#define DMA_SxFCR_FEIE_Pos       (7U)

+#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                 /*!< 0x00000080 */

+#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk                            /*!< FIFO error interrupt enable */

+#define DMA_SxFCR_FS_Pos         (3U)

+#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                   /*!< 0x00000038 */

+#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk                              /*!< FIFO status */

+#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */

+#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */

+#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */

+#define DMA_SxFCR_DMDIS_Pos      (2U)

+#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                /*!< 0x00000004 */

+#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk                           /*!< Direct mode disable */

+#define DMA_SxFCR_FTH_Pos        (0U)

+#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                  /*!< 0x00000003 */

+#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk                             /*!< FIFO threshold selection */

+#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */

+#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */

+

+/********************  Bits definition for DMA_LISR register  *****************/

+#define DMA_LISR_TCIF3_Pos       (27U)

+#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                 /*!< 0x08000000 */

+#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk                            /*!<  Stream 3 transfer complete interrupt flag */

+#define DMA_LISR_HTIF3_Pos       (26U)

+#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                 /*!< 0x04000000 */

+#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk                            /*!<  Stream 3 half transfer interrupt flag */

+#define DMA_LISR_TEIF3_Pos       (25U)

+#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                 /*!< 0x02000000 */

+#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk                            /*!<  Stream 3 transfer error interrupt flag */

+#define DMA_LISR_DMEIF3_Pos      (24U)

+#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                /*!< 0x01000000 */

+#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk                           /*!<  Stream 3 direct mode error interrupt flag */

+#define DMA_LISR_FEIF3_Pos       (22U)

+#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                 /*!< 0x00400000 */

+#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk                            /*!<  Stream 3 FIFO error interrupt flag */

+#define DMA_LISR_TCIF2_Pos       (21U)

+#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                 /*!< 0x00200000 */

+#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk                            /*!<  Stream 2 transfer complete interrupt flag */

+#define DMA_LISR_HTIF2_Pos       (20U)

+#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                 /*!< 0x00100000 */

+#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk                            /*!<  Stream 2 half transfer interrupt flag */

+#define DMA_LISR_TEIF2_Pos       (19U)

+#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                 /*!< 0x00080000 */

+#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk                            /*!<  Stream 2 transfer error interrupt flag */

+#define DMA_LISR_DMEIF2_Pos      (18U)

+#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                /*!< 0x00040000 */

+#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk                           /*!<  Stream 2 direct mode error interrupt flag */

+#define DMA_LISR_FEIF2_Pos       (16U)

+#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                 /*!< 0x00010000 */

+#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk                            /*!<  Stream 2 FIFO error interrupt flag */

+#define DMA_LISR_TCIF1_Pos       (11U)

+#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                 /*!< 0x00000800 */

+#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk                            /*!<  Stream 1 transfer complete interrupt flag */

+#define DMA_LISR_HTIF1_Pos       (10U)

+#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                 /*!< 0x00000400 */

+#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk                            /*!<  Stream 1 half transfer interrupt flag */

+#define DMA_LISR_TEIF1_Pos       (9U)

+#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                 /*!< 0x00000200 */

+#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk                            /*!<  Stream 1 transfer error interrupt flag */

+#define DMA_LISR_DMEIF1_Pos      (8U)

+#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                /*!< 0x00000100 */

+#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk                           /*!<  Stream 1 direct mode error interrupt flag */

+#define DMA_LISR_FEIF1_Pos       (6U)

+#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                 /*!< 0x00000040 */

+#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk                            /*!<  Stream 1 FIFO error interrupt flag */

+#define DMA_LISR_TCIF0_Pos       (5U)

+#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                 /*!< 0x00000020 */

+#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk                            /*!<  Stream 0 transfer complete interrupt flag */

+#define DMA_LISR_HTIF0_Pos       (4U)

+#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                 /*!< 0x00000010 */

+#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk                            /*!<  Stream 0 half transfer interrupt flag */

+#define DMA_LISR_TEIF0_Pos       (3U)

+#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                 /*!< 0x00000008 */

+#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk                            /*!<  Stream 0 transfer error interrupt flag */

+#define DMA_LISR_DMEIF0_Pos      (2U)

+#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                /*!< 0x00000004 */

+#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk                           /*!<  Stream 0 direct mode error interrupt flag */

+#define DMA_LISR_FEIF0_Pos       (0U)

+#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                 /*!< 0x00000001 */

+#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk                            /*!<  Stream 0 FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_HISR register  *****************/

+#define DMA_HISR_TCIF7_Pos       (27U)

+#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                 /*!< 0x08000000 */

+#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk                            /*!<  Stream 7 transfer complete interrupt flag */

+#define DMA_HISR_HTIF7_Pos       (26U)

+#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                 /*!< 0x04000000 */

+#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk                            /*!<  Stream 7 half transfer interrupt flag */

+#define DMA_HISR_TEIF7_Pos       (25U)

+#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                 /*!< 0x02000000 */

+#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk                            /*!<  Stream 7 transfer error interrupt flag */

+#define DMA_HISR_DMEIF7_Pos      (24U)

+#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                /*!< 0x01000000 */

+#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk                           /*!<  Stream 7 direct mode error interrupt flag */

+#define DMA_HISR_FEIF7_Pos       (22U)

+#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                 /*!< 0x00400000 */

+#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk                            /*!<  Stream 7 FIFO error interrupt flag */

+#define DMA_HISR_TCIF6_Pos       (21U)

+#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                 /*!< 0x00200000 */

+#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk                            /*!<  Stream 6 transfer complete interrupt flag */

+#define DMA_HISR_HTIF6_Pos       (20U)

+#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                 /*!< 0x00100000 */

+#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk                            /*!<  Stream 6 half transfer interrupt flag */

+#define DMA_HISR_TEIF6_Pos       (19U)

+#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                 /*!< 0x00080000 */

+#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk                            /*!<  Stream 6 transfer error interrupt flag */

+#define DMA_HISR_DMEIF6_Pos      (18U)

+#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                /*!< 0x00040000 */

+#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk                           /*!<  Stream 6 direct mode error interrupt flag */

+#define DMA_HISR_FEIF6_Pos       (16U)

+#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                 /*!< 0x00010000 */

+#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk                            /*!<  Stream 6 FIFO error interrupt flag */

+#define DMA_HISR_TCIF5_Pos       (11U)

+#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                 /*!< 0x00000800 */

+#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk                            /*!<  Stream 5 transfer complete interrupt flag */

+#define DMA_HISR_HTIF5_Pos       (10U)

+#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                 /*!< 0x00000400 */

+#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk                            /*!<  Stream 5 half transfer interrupt flag */

+#define DMA_HISR_TEIF5_Pos       (9U)

+#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                 /*!< 0x00000200 */

+#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk                            /*!<  Stream 5 transfer error interrupt flag */

+#define DMA_HISR_DMEIF5_Pos      (8U)

+#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                /*!< 0x00000100 */

+#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk                           /*!<  Stream 5 direct mode error interrupt flag */

+#define DMA_HISR_FEIF5_Pos       (6U)

+#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                 /*!< 0x00000040 */

+#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk                            /*!<  Stream 5 FIFO error interrupt flag */

+#define DMA_HISR_TCIF4_Pos       (5U)

+#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                 /*!< 0x00000020 */

+#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk                            /*!<  Stream 4 transfer complete interrupt flag */

+#define DMA_HISR_HTIF4_Pos       (4U)

+#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                 /*!< 0x00000010 */

+#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk                            /*!<  Stream 4 half transfer interrupt flag */

+#define DMA_HISR_TEIF4_Pos       (3U)

+#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                 /*!< 0x00000008 */

+#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk                            /*!<  Stream 4 transfer error interrupt flag */

+#define DMA_HISR_DMEIF4_Pos      (2U)

+#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                /*!< 0x00000004 */

+#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk                           /*!<  Stream 4 direct mode error interrupt flag */

+#define DMA_HISR_FEIF4_Pos       (0U)

+#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                 /*!< 0x00000001 */

+#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk                            /*!<  Stream 4 FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_LIFCR register  ****************/

+#define DMA_LIFCR_CTCIF3_Pos     (27U)

+#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)               /*!< 0x08000000 */

+#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk                          /*!<  Stream 3 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF3_Pos     (26U)

+#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)               /*!< 0x04000000 */

+#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk                          /*!<  Stream 3 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF3_Pos     (25U)

+#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)               /*!< 0x02000000 */

+#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk                          /*!<  Stream 3 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF3_Pos    (24U)

+#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)              /*!< 0x01000000 */

+#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk                         /*!<  Stream 3 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF3_Pos     (22U)

+#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)               /*!< 0x00400000 */

+#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk                          /*!<  Stream 3 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF2_Pos     (21U)

+#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)               /*!< 0x00200000 */

+#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk                          /*!<  Stream 2 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF2_Pos     (20U)

+#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)               /*!< 0x00100000 */

+#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk                          /*!<  Stream 2 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF2_Pos     (19U)

+#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)               /*!< 0x00080000 */

+#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk                          /*!<  Stream 2 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF2_Pos    (18U)

+#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)              /*!< 0x00040000 */

+#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk                         /*!<  Stream 2 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF2_Pos     (16U)

+#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)               /*!< 0x00010000 */

+#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk                          /*!<  Stream 2 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF1_Pos     (11U)

+#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)               /*!< 0x00000800 */

+#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk                          /*!<  Stream 1 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF1_Pos     (10U)

+#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)               /*!< 0x00000400 */

+#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk                          /*!<  Stream 1 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF1_Pos     (9U)

+#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)               /*!< 0x00000200 */

+#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk                          /*!<  Stream 1 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF1_Pos    (8U)

+#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)              /*!< 0x00000100 */

+#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk                         /*!<  Stream 1 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF1_Pos     (6U)

+#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)               /*!< 0x00000040 */

+#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk                          /*!<  Stream 1 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF0_Pos     (5U)

+#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)               /*!< 0x00000020 */

+#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk                          /*!<  Stream 0 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF0_Pos     (4U)

+#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)               /*!< 0x00000010 */

+#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk                          /*!<  Stream 0 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF0_Pos     (3U)

+#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)               /*!< 0x00000008 */

+#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk                          /*!<  Stream 0 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF0_Pos    (2U)

+#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)              /*!< 0x00000004 */

+#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk                         /*!<  Stream 0 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF0_Pos     (0U)

+#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)               /*!< 0x00000001 */

+#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk                          /*!<  Stream 0 clear FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_HIFCR  register  ****************/

+#define DMA_HIFCR_CTCIF7_Pos     (27U)

+#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)               /*!< 0x08000000 */

+#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk                          /*!<  Stream 7 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF7_Pos     (26U)

+#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)               /*!< 0x04000000 */

+#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk                          /*!<  Stream 7 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF7_Pos     (25U)

+#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)               /*!< 0x02000000 */

+#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk                          /*!<  Stream 7 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF7_Pos    (24U)

+#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)              /*!< 0x01000000 */

+#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk                         /*!<  Stream 7 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF7_Pos     (22U)

+#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)               /*!< 0x00400000 */

+#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk                          /*!<  Stream 7 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF6_Pos     (21U)

+#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)               /*!< 0x00200000 */

+#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk                          /*!<  Stream 6 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF6_Pos     (20U)

+#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)               /*!< 0x00100000 */

+#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk                          /*!<  Stream 6 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF6_Pos     (19U)

+#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)               /*!< 0x00080000 */

+#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk                          /*!<  Stream 6 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF6_Pos    (18U)

+#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)              /*!< 0x00040000 */

+#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk                         /*!<  Stream 6 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF6_Pos     (16U)

+#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)               /*!< 0x00010000 */

+#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk                          /*!<  Stream 6 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF5_Pos     (11U)

+#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)               /*!< 0x00000800 */

+#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk                          /*!<  Stream 5 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF5_Pos     (10U)

+#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)               /*!< 0x00000400 */

+#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk                          /*!<  Stream 5 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF5_Pos     (9U)

+#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)               /*!< 0x00000200 */

+#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk                          /*!<  Stream 5 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF5_Pos    (8U)

+#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)              /*!< 0x00000100 */

+#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk                         /*!<  Stream 5 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF5_Pos     (6U)

+#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)               /*!< 0x00000040 */

+#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk                          /*!<  Stream 5 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF4_Pos     (5U)

+#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)               /*!< 0x00000020 */

+#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk                          /*!<  Stream 4 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF4_Pos     (4U)

+#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)               /*!< 0x00000010 */

+#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk                          /*!<  Stream 4 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF4_Pos     (3U)

+#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)               /*!< 0x00000008 */

+#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk                          /*!<  Stream 4 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF4_Pos    (2U)

+#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)              /*!< 0x00000004 */

+#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk                         /*!<  Stream 4 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF4_Pos     (0U)

+#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)               /*!< 0x00000001 */

+#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk                          /*!<  Stream 4 clear FIFO error interrupt flag */

+

+/******************  Bit definition for DMA_SxPAR register  ********************/

+#define DMA_SxPAR_PA_Pos         (0U)

+#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)            /*!< 0xFFFFFFFF */

+#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */

+

+/******************  Bit definition for DMA_SxM0AR register  ********************/

+#define DMA_SxM0AR_M0A_Pos       (0U)

+#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)          /*!< 0xFFFFFFFF */

+#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory 0 Address */

+

+/******************  Bit definition for DMA_SxM1AR register  ********************/

+#define DMA_SxM1AR_M1A_Pos       (0U)

+#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)          /*!< 0xFFFFFFFF */

+#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory 1 Address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             DMAMUX Controller                              */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DMAMUX_CxCR register  **************/

+#define DMAMUX_CxCR_DMAREQ_ID_Pos      (0U)

+#define DMAMUX_CxCR_DMAREQ_ID_Msk      (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)   /*!< 0x000000FF */

+#define DMAMUX_CxCR_DMAREQ_ID          DMAMUX_CxCR_DMAREQ_ID_Msk               /*!<  DMA request identification */

+#define DMAMUX_CxCR_DMAREQ_ID_0        (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000001 */

+#define DMAMUX_CxCR_DMAREQ_ID_1        (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000002 */

+#define DMAMUX_CxCR_DMAREQ_ID_2        (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000004 */

+#define DMAMUX_CxCR_DMAREQ_ID_3        (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000008 */

+#define DMAMUX_CxCR_DMAREQ_ID_4        (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000010 */

+#define DMAMUX_CxCR_DMAREQ_ID_5        (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000020 */

+#define DMAMUX_CxCR_DMAREQ_ID_6        (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000040 */

+#define DMAMUX_CxCR_DMAREQ_ID_7        (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000080 */

+#define DMAMUX_CxCR_SOIE_Pos           (8U)

+#define DMAMUX_CxCR_SOIE_Msk           (0x1UL << DMAMUX_CxCR_SOIE_Pos)         /*!< 0x00000100 */

+#define DMAMUX_CxCR_SOIE               DMAMUX_CxCR_SOIE_Msk                    /*!<  Synchronization overrun interrupt enable */

+#define DMAMUX_CxCR_EGE_Pos            (9U)

+#define DMAMUX_CxCR_EGE_Msk            (0x1UL << DMAMUX_CxCR_EGE_Pos)          /*!< 0x00000200 */

+#define DMAMUX_CxCR_EGE                DMAMUX_CxCR_EGE_Msk                     /*!<  Event generation enable */

+#define DMAMUX_CxCR_SE_Pos             (16U)

+#define DMAMUX_CxCR_SE_Msk             (0x1UL << DMAMUX_CxCR_SE_Pos)           /*!< 0x00010000 */

+#define DMAMUX_CxCR_SE                 DMAMUX_CxCR_SE_Msk                      /*!<  Synchronization enable */

+#define DMAMUX_CxCR_SPOL_Pos           (17U)

+#define DMAMUX_CxCR_SPOL_Msk           (0x3UL << DMAMUX_CxCR_SPOL_Pos)         /*!< 0x00060000 */

+#define DMAMUX_CxCR_SPOL               DMAMUX_CxCR_SPOL_Msk                    /*!<  Synchronization polarity */

+#define DMAMUX_CxCR_SPOL_0             (0x1UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00020000 */

+#define DMAMUX_CxCR_SPOL_1             (0x2UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00040000 */

+#define DMAMUX_CxCR_NBREQ_Pos          (19U)

+#define DMAMUX_CxCR_NBREQ_Msk          (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)       /*!< 0x00F80000 */

+#define DMAMUX_CxCR_NBREQ              DMAMUX_CxCR_NBREQ_Msk                   /*!<  Number of DMA requests minus 1 to forward */

+#define DMAMUX_CxCR_NBREQ_0            (0x01UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00080000 */

+#define DMAMUX_CxCR_NBREQ_1            (0x02UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00100000 */

+#define DMAMUX_CxCR_NBREQ_2            (0x04UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00200000 */

+#define DMAMUX_CxCR_NBREQ_3            (0x08UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00400000 */

+#define DMAMUX_CxCR_NBREQ_4            (0x10UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00800000 */

+#define DMAMUX_CxCR_SYNC_ID_Pos        (24U)

+#define DMAMUX_CxCR_SYNC_ID_Msk        (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)     /*!< 0x1F000000 */

+#define DMAMUX_CxCR_SYNC_ID            DMAMUX_CxCR_SYNC_ID_Msk                 /*!<  Synchronization identification */

+#define DMAMUX_CxCR_SYNC_ID_0          (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x01000000 */

+#define DMAMUX_CxCR_SYNC_ID_1          (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x02000000 */

+#define DMAMUX_CxCR_SYNC_ID_2          (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x04000000 */

+#define DMAMUX_CxCR_SYNC_ID_3          (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x08000000 */

+#define DMAMUX_CxCR_SYNC_ID_4          (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x10000000 */

+

+/********************  Bits definition for DMAMUX_CSR register  **************/

+#define DMAMUX_CSR_SOF0_Pos            (0U)

+#define DMAMUX_CSR_SOF0_Msk            (0x1UL << DMAMUX_CSR_SOF0_Pos)          /*!< 0x00000001 */

+#define DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0_Msk                     /*!< Channel 0 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF1_Pos            (1U)

+#define DMAMUX_CSR_SOF1_Msk            (0x1UL << DMAMUX_CSR_SOF1_Pos)          /*!< 0x00000002 */

+#define DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1_Msk                     /*!< Channel 1 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF2_Pos            (2U)

+#define DMAMUX_CSR_SOF2_Msk            (0x1UL << DMAMUX_CSR_SOF2_Pos)          /*!< 0x00000004 */

+#define DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2_Msk                     /*!< Channel 2 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF3_Pos            (3U)

+#define DMAMUX_CSR_SOF3_Msk            (0x1UL << DMAMUX_CSR_SOF3_Pos)          /*!< 0x00000008 */

+#define DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3_Msk                     /*!< Channel 3 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF4_Pos            (4U)

+#define DMAMUX_CSR_SOF4_Msk            (0x1UL << DMAMUX_CSR_SOF4_Pos)          /*!< 0x00000010 */

+#define DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4_Msk                     /*!< Channel 4 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF5_Pos            (5U)

+#define DMAMUX_CSR_SOF5_Msk            (0x1UL << DMAMUX_CSR_SOF5_Pos)          /*!< 0x00000020 */

+#define DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5_Msk                     /*!< Channel 5 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF6_Pos            (6U)

+#define DMAMUX_CSR_SOF6_Msk            (0x1UL << DMAMUX_CSR_SOF6_Pos)          /*!< 0x00000040 */

+#define DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6_Msk                     /*!< Channel 6 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF7_Pos            (7U)

+#define DMAMUX_CSR_SOF7_Msk            (0x1UL << DMAMUX_CSR_SOF7_Pos)          /*!< 0x00000080 */

+#define DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7_Msk                     /*!< Channel 7 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF8_Pos            (8U)

+#define DMAMUX_CSR_SOF8_Msk            (0x1UL << DMAMUX_CSR_SOF8_Pos)          /*!< 0x00000100 */

+#define DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8_Msk                     /*!< Channel 8 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF9_Pos            (9U)

+#define DMAMUX_CSR_SOF9_Msk            (0x1UL << DMAMUX_CSR_SOF9_Pos)          /*!< 0x00000200 */

+#define DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9_Msk                     /*!< Channel 9 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF10_Pos           (10U)

+#define DMAMUX_CSR_SOF10_Msk           (0x1UL << DMAMUX_CSR_SOF10_Pos)         /*!< 0x00000400 */

+#define DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10_Msk                    /*!< Channel 10 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF11_Pos           (11U)

+#define DMAMUX_CSR_SOF11_Msk           (0x1UL << DMAMUX_CSR_SOF11_Pos)         /*!< 0x00000800 */

+#define DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11_Msk                    /*!< Channel 11 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF12_Pos           (12U)

+#define DMAMUX_CSR_SOF12_Msk           (0x1UL << DMAMUX_CSR_SOF12_Pos)         /*!< 0x00001000 */

+#define DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12_Msk                    /*!< Channel 12 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF13_Pos           (13U)

+#define DMAMUX_CSR_SOF13_Msk           (0x1UL << DMAMUX_CSR_SOF13_Pos)         /*!< 0x00002000 */

+#define DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13_Msk                    /*!< Channel 13 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF14_Pos           (14U)

+#define DMAMUX_CSR_SOF14_Msk           (0x1UL << DMAMUX_CSR_SOF14_Pos)         /*!< 0x00004000 */

+#define DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14_Msk                    /*!< Channel 14 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF15_Pos           (15U)

+#define DMAMUX_CSR_SOF15_Msk           (0x1UL << DMAMUX_CSR_SOF15_Pos)         /*!< 0x00008000 */

+#define DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15_Msk                    /*!< Channel 15 Synchronization overrun event flag */

+

+/********************  Bits definition for DMAMUX_CFR register  **************/

+#define DMAMUX_CFR_CSOF0_Pos           (0U)

+#define DMAMUX_CFR_CSOF0_Msk           (0x1UL << DMAMUX_CFR_CSOF0_Pos)         /*!< 0x00000001 */

+#define DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0_Msk                    /*!< Channel 0 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF1_Pos           (1U)

+#define DMAMUX_CFR_CSOF1_Msk           (0x1UL << DMAMUX_CFR_CSOF1_Pos)         /*!< 0x00000002 */

+#define DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1_Msk                    /*!< Channel 1 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF2_Pos           (2U)

+#define DMAMUX_CFR_CSOF2_Msk           (0x1UL << DMAMUX_CFR_CSOF2_Pos)         /*!< 0x00000004 */

+#define DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2_Msk                    /*!< Channel 2 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF3_Pos           (3U)

+#define DMAMUX_CFR_CSOF3_Msk           (0x1UL << DMAMUX_CFR_CSOF3_Pos)         /*!< 0x00000008 */

+#define DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3_Msk                    /*!< Channel 3 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF4_Pos           (4U)

+#define DMAMUX_CFR_CSOF4_Msk           (0x1UL << DMAMUX_CFR_CSOF4_Pos)         /*!< 0x00000010 */

+#define DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4_Msk                    /*!< Channel 4 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF5_Pos           (5U)

+#define DMAMUX_CFR_CSOF5_Msk           (0x1UL << DMAMUX_CFR_CSOF5_Pos)         /*!< 0x00000020 */

+#define DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5_Msk                    /*!< Channel 5 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF6_Pos           (6U)

+#define DMAMUX_CFR_CSOF6_Msk           (0x1UL << DMAMUX_CFR_CSOF6_Pos)         /*!< 0x00000040 */

+#define DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6_Msk                    /*!< Channel 6 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF7_Pos           (7U)

+#define DMAMUX_CFR_CSOF7_Msk           (0x1UL << DMAMUX_CFR_CSOF7_Pos)         /*!< 0x00000080 */

+#define DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7_Msk                    /*!< Channel 7 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF8_Pos           (8U)

+#define DMAMUX_CFR_CSOF8_Msk           (0x1UL << DMAMUX_CFR_CSOF8_Pos)         /*!< 0x00000100 */

+#define DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8_Msk                    /*!< Channel 8 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF9_Pos           (9U)

+#define DMAMUX_CFR_CSOF9_Msk           (0x1UL << DMAMUX_CFR_CSOF9_Pos)         /*!< 0x00000200 */

+#define DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9_Msk                    /*!< Channel 9 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF10_Pos          (10U)

+#define DMAMUX_CFR_CSOF10_Msk          (0x1UL << DMAMUX_CFR_CSOF10_Pos)        /*!< 0x00000400 */

+#define DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10_Msk                   /*!< Channel 10 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF11_Pos          (11U)

+#define DMAMUX_CFR_CSOF11_Msk          (0x1UL << DMAMUX_CFR_CSOF11_Pos)        /*!< 0x00000800 */

+#define DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11_Msk                   /*!< Channel 11 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF12_Pos          (12U)

+#define DMAMUX_CFR_CSOF12_Msk          (0x1UL << DMAMUX_CFR_CSOF12_Pos)        /*!< 0x00001000 */

+#define DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12_Msk                   /*!< Channel 12 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF13_Pos          (13U)

+#define DMAMUX_CFR_CSOF13_Msk          (0x1UL << DMAMUX_CFR_CSOF13_Pos)        /*!< 0x00002000 */

+#define DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13_Msk                   /*!< Channel 13 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF14_Pos          (14U)

+#define DMAMUX_CFR_CSOF14_Msk          (0x1UL << DMAMUX_CFR_CSOF14_Pos)        /*!< 0x00004000 */

+#define DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14_Msk                   /*!< Channel 14 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF15_Pos          (15U)

+#define DMAMUX_CFR_CSOF15_Msk          (0x1UL << DMAMUX_CFR_CSOF15_Pos)        /*!< 0x00008000 */

+#define DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15_Msk                   /*!< Channel 15 Clear synchronization overrun event flag */

+

+/********************  Bits definition for DMAMUX_RGxCR register  ************/

+#define DMAMUX_RGxCR_SIG_ID_Pos        (0U)

+#define DMAMUX_RGxCR_SIG_ID_Msk        (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)     /*!< 0x0000001F */

+#define DMAMUX_RGxCR_SIG_ID            DMAMUX_RGxCR_SIG_ID_Msk                 /*!< Signal identification */

+#define DMAMUX_RGxCR_SIG_ID_0          (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000001 */

+#define DMAMUX_RGxCR_SIG_ID_1          (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000002 */

+#define DMAMUX_RGxCR_SIG_ID_2          (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000004 */

+#define DMAMUX_RGxCR_SIG_ID_3          (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000008 */

+#define DMAMUX_RGxCR_SIG_ID_4          (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000010 */

+#define DMAMUX_RGxCR_OIE_Pos           (8U)

+#define DMAMUX_RGxCR_OIE_Msk           (0x1UL << DMAMUX_RGxCR_OIE_Pos)         /*!< 0x00000100 */

+#define DMAMUX_RGxCR_OIE               DMAMUX_RGxCR_OIE_Msk                    /*!< Trigger overrun interrupt enable */

+#define DMAMUX_RGxCR_GE_Pos            (16U)

+#define DMAMUX_RGxCR_GE_Msk            (0x1UL << DMAMUX_RGxCR_GE_Pos)          /*!< 0x00010000 */

+#define DMAMUX_RGxCR_GE                DMAMUX_RGxCR_GE_Msk                     /*!< DMA request generator enable */

+#define DMAMUX_RGxCR_GPOL_Pos          (17U)

+#define DMAMUX_RGxCR_GPOL_Msk          (0x3UL << DMAMUX_RGxCR_GPOL_Pos)        /*!< 0x00060000 */

+#define DMAMUX_RGxCR_GPOL              DMAMUX_RGxCR_GPOL_Msk                   /*!< DMA request generator trigger polarity */

+#define DMAMUX_RGxCR_GPOL_0            (0x1UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00020000 */

+#define DMAMUX_RGxCR_GPOL_1            (0x2UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00040000 */

+#define DMAMUX_RGxCR_GNBREQ_Pos        (19U)

+#define DMAMUX_RGxCR_GNBREQ_Msk        (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)     /*!< 0x00F80000 */

+#define DMAMUX_RGxCR_GNBREQ            DMAMUX_RGxCR_GNBREQ_Msk                 /*!< Number of DMA requests to be generated */

+#define DMAMUX_RGxCR_GNBREQ_0          (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00080000 */

+#define DMAMUX_RGxCR_GNBREQ_1          (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00100000 */

+#define DMAMUX_RGxCR_GNBREQ_2          (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00200000 */

+#define DMAMUX_RGxCR_GNBREQ_3          (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00400000 */

+#define DMAMUX_RGxCR_GNBREQ_4          (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00800000 */

+

+/********************  Bits definition for DMAMUX_RGSR register  **************/

+#define DMAMUX_RGSR_OF0_Pos            (0U)

+#define DMAMUX_RGSR_OF0_Msk            (0x1UL << DMAMUX_RGSR_OF0_Pos)          /*!< 0x00000001 */

+#define DMAMUX_RGSR_OF0                DMAMUX_RGSR_OF0_Msk                     /*!< Request generator channel 0 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF1_Pos            (1U)

+#define DMAMUX_RGSR_OF1_Msk            (0x1UL << DMAMUX_RGSR_OF1_Pos)          /*!< 0x00000002 */

+#define DMAMUX_RGSR_OF1                DMAMUX_RGSR_OF1_Msk                     /*!< Request generator channel 1 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF2_Pos            (2U)

+#define DMAMUX_RGSR_OF2_Msk            (0x1UL << DMAMUX_RGSR_OF2_Pos)          /*!< 0x00000004 */

+#define DMAMUX_RGSR_OF2                DMAMUX_RGSR_OF2_Msk                     /*!< Request generator channel 2 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF3_Pos            (3U)

+#define DMAMUX_RGSR_OF3_Msk            (0x1UL << DMAMUX_RGSR_OF3_Pos)          /*!< 0x00000008 */

+#define DMAMUX_RGSR_OF3                DMAMUX_RGSR_OF3_Msk                     /*!< Request generator channel 3 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF4_Pos            (4U)

+#define DMAMUX_RGSR_OF4_Msk            (0x1UL << DMAMUX_RGSR_OF4_Pos)          /*!< 0x00000010 */

+#define DMAMUX_RGSR_OF4                DMAMUX_RGSR_OF4_Msk                     /*!< Request generator channel 4 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF5_Pos            (5U)

+#define DMAMUX_RGSR_OF5_Msk            (0x1UL << DMAMUX_RGSR_OF5_Pos)          /*!< 0x00000020 */

+#define DMAMUX_RGSR_OF5                DMAMUX_RGSR_OF5_Msk                     /*!< Request generator channel 5 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF6_Pos            (6U)

+#define DMAMUX_RGSR_OF6_Msk            (0x1UL << DMAMUX_RGSR_OF6_Pos)          /*!< 0x00000040 */

+#define DMAMUX_RGSR_OF6                DMAMUX_RGSR_OF6_Msk                     /*!< Request generator channel 6 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF7_Pos            (7U)

+#define DMAMUX_RGSR_OF7_Msk            (0x1UL << DMAMUX_RGSR_OF7_Pos)          /*!< 0x00000080 */

+#define DMAMUX_RGSR_OF7                DMAMUX_RGSR_OF7_Msk                     /*!< Request generator channel 7 Trigger overrun event flag */

+

+/********************  Bits definition for DMAMUX_RGCFR register  **************/

+#define DMAMUX_RGCFR_COF0_Pos          (0U)

+#define DMAMUX_RGCFR_COF0_Msk          (0x1UL << DMAMUX_RGCFR_COF0_Pos)        /*!< 0x00000001 */

+#define DMAMUX_RGCFR_COF0              DMAMUX_RGCFR_COF0_Msk                   /*!< Request generator channel 0 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF1_Pos          (1U)

+#define DMAMUX_RGCFR_COF1_Msk          (0x1UL << DMAMUX_RGCFR_COF1_Pos)        /*!< 0x00000002 */

+#define DMAMUX_RGCFR_COF1              DMAMUX_RGCFR_COF1_Msk                   /*!< Request generator channel 1 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF2_Pos          (2U)

+#define DMAMUX_RGCFR_COF2_Msk          (0x1UL << DMAMUX_RGCFR_COF2_Pos)        /*!< 0x00000004 */

+#define DMAMUX_RGCFR_COF2              DMAMUX_RGCFR_COF2_Msk                   /*!< Request generator channel 2 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF3_Pos          (3U)

+#define DMAMUX_RGCFR_COF3_Msk          (0x1UL << DMAMUX_RGCFR_COF3_Pos)        /*!< 0x00000008 */

+#define DMAMUX_RGCFR_COF3              DMAMUX_RGCFR_COF3_Msk                   /*!< Request generator channel 3 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF4_Pos          (4U)

+#define DMAMUX_RGCFR_COF4_Msk          (0x1UL << DMAMUX_RGCFR_COF4_Pos)        /*!< 0x00000010 */

+#define DMAMUX_RGCFR_COF4              DMAMUX_RGCFR_COF4_Msk                   /*!< Request generator channel 4 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF5_Pos          (5U)

+#define DMAMUX_RGCFR_COF5_Msk          (0x1UL << DMAMUX_RGCFR_COF5_Pos)        /*!< 0x00000020 */

+#define DMAMUX_RGCFR_COF5              DMAMUX_RGCFR_COF5_Msk                   /*!< Request generator channel 5 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF6_Pos          (6U)

+#define DMAMUX_RGCFR_COF6_Msk          (0x1UL << DMAMUX_RGCFR_COF6_Pos)        /*!< 0x00000040 */

+#define DMAMUX_RGCFR_COF6              DMAMUX_RGCFR_COF6_Msk                   /*!< Request generator channel 6 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF7_Pos          (7U)

+#define DMAMUX_RGCFR_COF7_Msk          (0x1UL << DMAMUX_RGCFR_COF7_Pos)        /*!< 0x00000080 */

+#define DMAMUX_RGCFR_COF7              DMAMUX_RGCFR_COF7_Msk                   /*!< Request generator channel 7 Clear trigger overrun event flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         AHB Master DMA2D Controller (DMA2D)                */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for DMA2D_CR register  ******************/

+

+#define DMA2D_CR_START_Pos         (0U)

+#define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)               /*!< 0x00000001 */

+#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer                          */

+#define DMA2D_CR_SUSP_Pos          (1U)

+#define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                /*!< 0x00000002 */

+#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer                        */

+#define DMA2D_CR_ABORT_Pos         (2U)

+#define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)               /*!< 0x00000004 */

+#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer                          */

+#define DMA2D_CR_LOM_Pos           (6U)

+#define DMA2D_CR_LOM_Msk           (0x1UL << DMA2D_CR_LOM_Pos)                 /*!< 0x00000040 */

+#define DMA2D_CR_LOM               DMA2D_CR_LOM_Msk                            /*!< Line Offset Mode                         */

+#define DMA2D_CR_TEIE_Pos          (8U)

+#define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                /*!< 0x00000100 */

+#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable         */

+#define DMA2D_CR_TCIE_Pos          (9U)

+#define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                /*!< 0x00000200 */

+#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable      */

+#define DMA2D_CR_TWIE_Pos          (10U)

+#define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                /*!< 0x00000400 */

+#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable     */

+#define DMA2D_CR_CAEIE_Pos         (11U)

+#define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)               /*!< 0x00000800 */

+#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable      */

+#define DMA2D_CR_CTCIE_Pos         (12U)

+#define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)               /*!< 0x00001000 */

+#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */

+#define DMA2D_CR_CEIE_Pos          (13U)

+#define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                /*!< 0x00002000 */

+#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable    */

+#define DMA2D_CR_MODE_Pos          (16U)

+#define DMA2D_CR_MODE_Msk          (0x7UL << DMA2D_CR_MODE_Pos)                /*!< 0x00070000 */

+#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[2:0]                         */

+#define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */

+#define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */

+#define DMA2D_CR_MODE_2            (0x4UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00040000 */

+

+/********************  Bit definition for DMA2D_ISR register  *****************/

+

+#define DMA2D_ISR_TEIF_Pos         (0U)

+#define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)               /*!< 0x00000001 */

+#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag         */

+#define DMA2D_ISR_TCIF_Pos         (1U)

+#define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)               /*!< 0x00000002 */

+#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag      */

+#define DMA2D_ISR_TWIF_Pos         (2U)

+#define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)               /*!< 0x00000004 */

+#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag     */

+#define DMA2D_ISR_CAEIF_Pos        (3U)

+#define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)              /*!< 0x00000008 */

+#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag      */

+#define DMA2D_ISR_CTCIF_Pos        (4U)

+#define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)              /*!< 0x00000010 */

+#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */

+#define DMA2D_ISR_CEIF_Pos         (5U)

+#define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)               /*!< 0x00000020 */

+#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag    */

+

+/********************  Bit definition for DMA2D_IFCR register  ****************/

+

+#define DMA2D_IFCR_CTEIF_Pos       (0U)

+#define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)             /*!< 0x00000001 */

+#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */

+#define DMA2D_IFCR_CTCIF_Pos       (1U)

+#define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)             /*!< 0x00000002 */

+#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */

+#define DMA2D_IFCR_CTWIF_Pos       (2U)

+#define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)             /*!< 0x00000004 */

+#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */

+#define DMA2D_IFCR_CAECIF_Pos      (3U)

+#define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)            /*!< 0x00000008 */

+#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */

+#define DMA2D_IFCR_CCTCIF_Pos      (4U)

+#define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)            /*!< 0x00000010 */

+#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */

+#define DMA2D_IFCR_CCEIF_Pos       (5U)

+#define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)             /*!< 0x00000020 */

+#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */

+

+/********************  Bit definition for DMA2D_FGMAR register  ***************/

+

+#define DMA2D_FGMAR_MA_Pos         (0U)

+#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)        /*!< 0xFFFFFFFF */

+#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Foreground Memory Address */

+

+/********************  Bit definition for DMA2D_FGOR register  ****************/

+

+#define DMA2D_FGOR_LO_Pos          (0U)

+#define DMA2D_FGOR_LO_Msk          (0xFFFFUL << DMA2D_FGOR_LO_Pos)             /*!< 0x0000FFFF */

+#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */

+

+/********************  Bit definition for DMA2D_BGMAR register  ***************/

+

+#define DMA2D_BGMAR_MA_Pos         (0U)

+#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)        /*!< 0xFFFFFFFF */

+#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Background Memory Address */

+

+/********************  Bit definition for DMA2D_BGOR register  ****************/

+

+#define DMA2D_BGOR_LO_Pos          (0U)

+#define DMA2D_BGOR_LO_Msk          (0xFFFFUL << DMA2D_BGOR_LO_Pos)             /*!< 0x0000FFFF */

+#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */

+

+/********************  Bit definition for DMA2D_FGPFCCR register  *************/

+

+#define DMA2D_FGPFCCR_CM_Pos       (0U)

+#define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x0000000F */

+#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */

+#define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */

+#define DMA2D_FGPFCCR_CCM_Pos      (4U)

+#define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)            /*!< 0x00000010 */

+#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */

+#define DMA2D_FGPFCCR_START_Pos    (5U)

+#define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)          /*!< 0x00000020 */

+#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */

+#define DMA2D_FGPFCCR_CS_Pos       (8U)

+#define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)            /*!< 0x0000FF00 */

+#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */

+#define DMA2D_FGPFCCR_AM_Pos       (16U)

+#define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00030000 */

+#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */

+#define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */

+#define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */

+#define DMA2D_FGPFCCR_CSS_Pos      (18U)

+#define DMA2D_FGPFCCR_CSS_Msk      (0x3UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x000C0000 */

+#define DMA2D_FGPFCCR_CSS          DMA2D_FGPFCCR_CSS_Msk                       /* !< Chroma Sub-Sampling */

+#define DMA2D_FGPFCCR_CSS_0        (0x1UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00040000 */

+#define DMA2D_FGPFCCR_CSS_1        (0x2UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00080000 */

+#define DMA2D_FGPFCCR_AI_Pos       (20U)

+#define DMA2D_FGPFCCR_AI_Msk       (0x1UL << DMA2D_FGPFCCR_AI_Pos)             /*!< 0x00100000 */

+#define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Foreground Input Alpha Inverted */

+#define DMA2D_FGPFCCR_RBS_Pos      (21U)

+#define DMA2D_FGPFCCR_RBS_Msk      (0x1UL << DMA2D_FGPFCCR_RBS_Pos)            /*!< 0x00200000 */

+#define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Foreground Input Red Blue Swap */

+#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)

+#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */

+#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */

+

+/********************  Bit definition for DMA2D_FGCOLR register  **************/

+

+#define DMA2D_FGCOLR_BLUE_Pos      (0U)

+#define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)           /*!< 0x000000FF */

+#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Foreground Blue Value */

+#define DMA2D_FGCOLR_GREEN_Pos     (8U)

+#define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */

+#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Foreground Green Value */

+#define DMA2D_FGCOLR_RED_Pos       (16U)

+#define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)            /*!< 0x00FF0000 */

+#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Foreground Red Value */

+

+/********************  Bit definition for DMA2D_BGPFCCR register  *************/

+

+#define DMA2D_BGPFCCR_CM_Pos       (0U)

+#define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x0000000F */

+#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */

+#define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_BGPFCCR_CM_3         (0x8UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000008 */

+#define DMA2D_BGPFCCR_CCM_Pos      (4U)

+#define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)            /*!< 0x00000010 */

+#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */

+#define DMA2D_BGPFCCR_START_Pos    (5U)

+#define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)          /*!< 0x00000020 */

+#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */

+#define DMA2D_BGPFCCR_CS_Pos       (8U)

+#define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)            /*!< 0x0000FF00 */

+#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */

+#define DMA2D_BGPFCCR_AM_Pos       (16U)

+#define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00030000 */

+#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */

+#define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */

+#define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */

+#define DMA2D_BGPFCCR_AI_Pos       (20U)

+#define DMA2D_BGPFCCR_AI_Msk       (0x1UL << DMA2D_BGPFCCR_AI_Pos)             /*!< 0x00100000 */

+#define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< background Input Alpha Inverted */

+#define DMA2D_BGPFCCR_RBS_Pos      (21U)

+#define DMA2D_BGPFCCR_RBS_Msk      (0x1UL << DMA2D_BGPFCCR_RBS_Pos)            /*!< 0x00200000 */

+#define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Background Input Red Blue Swap */

+#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)

+#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */

+#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */

+

+/********************  Bit definition for DMA2D_BGCOLR register  **************/

+

+#define DMA2D_BGCOLR_BLUE_Pos      (0U)

+#define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)           /*!< 0x000000FF */

+#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Background Blue Value */

+#define DMA2D_BGCOLR_GREEN_Pos     (8U)

+#define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */

+#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Background Green Value */

+#define DMA2D_BGCOLR_RED_Pos       (16U)

+#define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)            /*!< 0x00FF0000 */

+#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Background Red Value */

+

+/********************  Bit definition for DMA2D_FGCMAR register  **************/

+

+#define DMA2D_FGCMAR_MA_Pos        (0U)

+#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */

+#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Foreground CLUT Memory Address */

+

+/********************  Bit definition for DMA2D_BGCMAR register  **************/

+

+#define DMA2D_BGCMAR_MA_Pos        (0U)

+#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */

+#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Background CLUT Memory Address */

+

+/********************  Bit definition for DMA2D_OPFCCR register  **************/

+

+#define DMA2D_OPFCCR_CM_Pos        (0U)

+#define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000007 */

+#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Output Color mode CM[2:0] */

+#define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_OPFCCR_SB_Pos        (8U)

+#define DMA2D_OPFCCR_SB_Msk        (0x1UL << DMA2D_OPFCCR_SB_Pos)              /*!< 0x00000100 */

+#define DMA2D_OPFCCR_SB            DMA2D_OPFCCR_SB_Msk                         /*!< Swap Bytes */

+#define DMA2D_OPFCCR_AI_Pos        (20U)

+#define DMA2D_OPFCCR_AI_Msk        (0x1UL << DMA2D_OPFCCR_AI_Pos)              /*!< 0x00100000 */

+#define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Output Alpha Inverted */

+#define DMA2D_OPFCCR_RBS_Pos       (21U)

+#define DMA2D_OPFCCR_RBS_Msk       (0x1UL << DMA2D_OPFCCR_RBS_Pos)             /*!< 0x00200000 */

+#define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Output Red Blue Swap */

+

+/********************  Bit definition for DMA2D_OCOLR register  ***************/

+

+/*!<Mode_ARGB8888/RGB888 */

+

+#define DMA2D_OCOLR_BLUE_1_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_1_Msk     (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos)            /*0x000000FFU*/

+#define DMA2D_OCOLR_BLUE_1         DMA2D_OCOLR_BLUE_1_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_1_Pos    (8U)

+#define DMA2D_OCOLR_GREEN_1_Msk    (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos)            /*0x0000FF00U)*/

+#define DMA2D_OCOLR_GREEN_1        DMA2D_OCOLR_GREEN_1_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_1_Pos      (16U)

+#define DMA2D_OCOLR_RED_1_Msk      (0xFFUL << DMA2D_OCOLR_RED_1_Pos)            /*0x00FF0000U */

+#define DMA2D_OCOLR_RED_1          DMA2D_OCOLR_RED_1_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_1_Pos    (24U)

+#define DMA2D_OCOLR_ALPHA_1_Msk    (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos)          /*0xFF000000U*/

+#define DMA2D_OCOLR_ALPHA_1        DMA2D_OCOLR_ALPHA_1_Msk                     /*!< Output Alpha Channel Value */

+

+/*!<Mode_RGB565 */

+#define DMA2D_OCOLR_BLUE_2_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_2_Msk     (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos)            /*0x0000001FU*/

+#define DMA2D_OCOLR_BLUE_2         DMA2D_OCOLR_BLUE_2_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_2_Pos    (5U)

+#define DMA2D_OCOLR_GREEN_2_Msk    (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos)          /* 0x000007E0U */

+#define DMA2D_OCOLR_GREEN_2        DMA2D_OCOLR_GREEN_2_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_2_Pos      (11U)

+#define DMA2D_OCOLR_RED_2_Msk      (0xF8UL<<DMA2D_OCOLR_RED_2_Pos)              /*0x0000F800U*/

+#define DMA2D_OCOLR_RED_2          DMA2D_OCOLR_RED_2_Msk                       /*!< Output Red Value */

+

+/*!<Mode_ARGB1555 */

+#define DMA2D_OCOLR_BLUE_3_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_3_Msk     (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos)           /*0x0000001FU*/

+#define DMA2D_OCOLR_BLUE_3         DMA2D_OCOLR_BLUE_3_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_3_Pos    (5U)

+#define DMA2D_OCOLR_GREEN_3_Msk    (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos)          /*0x000003E0U*/

+#define DMA2D_OCOLR_GREEN_3        DMA2D_OCOLR_GREEN_3_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_3_Pos      (10U)

+#define DMA2D_OCOLR_RED_3_Msk      (0x7CUL << DMA2D_OCOLR_RED_3_Pos)            /* 0x00007C00U*/

+#define DMA2D_OCOLR_RED_3          DMA2D_OCOLR_RED_3_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_3_Pos    (15U)

+#define DMA2D_OCOLR_ALPHA_3_Msk    (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos)           /*0x00008000U*/

+#define DMA2D_OCOLR_ALPHA_3        DMA2D_OCOLR_ALPHA_3_Msk                     /*!< Output Alpha Channel Value */

+

+/*!<Mode_ARGB4444 */

+#define DMA2D_OCOLR_BLUE_4_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_4_Msk     (0xFUL << DMA2D_OCOLR_BLUE_4_Pos)            /*0x0000000FU*/

+#define DMA2D_OCOLR_BLUE_4         DMA2D_OCOLR_BLUE_4_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_4_Pos    (4U)

+#define DMA2D_OCOLR_GREEN_4_Msk    (0xFUL << DMA2D_OCOLR_GREEN_4_Pos)           /*0x000000F0U*/

+#define DMA2D_OCOLR_GREEN_4        DMA2D_OCOLR_GREEN_4_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_4_Pos      (8U)

+#define DMA2D_OCOLR_RED_4_Msk      (0xFUL << DMA2D_OCOLR_RED_4_Pos)             /*0x00000F00U*/

+#define DMA2D_OCOLR_RED_4          DMA2D_OCOLR_RED_4_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_4_Pos    (12U)

+#define DMA2D_OCOLR_ALPHA_4_Msk    (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos)            /*0x0000F000U*/

+#define DMA2D_OCOLR_ALPHA_4        DMA2D_OCOLR_ALPHA_4_Msk                     /*!< Output Alpha Channel Value */

+

+/********************  Bit definition for DMA2D_OMAR register  ****************/

+

+#define DMA2D_OMAR_MA_Pos          (0U)

+#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)         /*!< 0xFFFFFFFF */

+#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Output Memory Address */

+

+/********************  Bit definition for DMA2D_OOR register  *****************/

+

+#define DMA2D_OOR_LO_Pos           (0U)

+#define DMA2D_OOR_LO_Msk           (0xFFFFUL << DMA2D_OOR_LO_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Output Line Offset */

+

+/********************  Bit definition for DMA2D_NLR register  *****************/

+

+#define DMA2D_NLR_NL_Pos           (0U)

+#define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */

+#define DMA2D_NLR_PL_Pos           (16U)

+#define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)              /*!< 0x3FFF0000 */

+#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */

+

+/********************  Bit definition for DMA2D_LWR register  *****************/

+

+#define DMA2D_LWR_LW_Pos           (0U)

+#define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */

+

+/********************  Bit definition for DMA2D_AMTCR register  ***************/

+

+#define DMA2D_AMTCR_EN_Pos         (0U)

+#define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)               /*!< 0x00000001 */

+#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */

+#define DMA2D_AMTCR_DT_Pos         (8U)

+#define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)              /*!< 0x0000FF00 */

+#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */

+

+

+/********************  Bit definition for DMA2D_FGCLUT register  **************/

+

+/********************  Bit definition for DMA2D_BGCLUT register  **************/

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                    External Interrupt/Event Controller                     */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for EXTI_RTSR1 register  *******************/

+#define EXTI_RTSR1_TR_Pos          (0U)

+#define EXTI_RTSR1_TR_Msk          (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)           /*!< 0x003FFFFF */

+#define EXTI_RTSR1_TR              EXTI_RTSR1_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR1_TR0_Pos         (0U)

+#define EXTI_RTSR1_TR0_Msk         (0x1UL << EXTI_RTSR1_TR0_Pos)               /*!< 0x00000001 */

+#define EXTI_RTSR1_TR0             EXTI_RTSR1_TR0_Msk                          /*!< Rising trigger event configuration bit of line 0 */

+#define EXTI_RTSR1_TR1_Pos         (1U)

+#define EXTI_RTSR1_TR1_Msk         (0x1UL << EXTI_RTSR1_TR1_Pos)               /*!< 0x00000002 */

+#define EXTI_RTSR1_TR1             EXTI_RTSR1_TR1_Msk                          /*!< Rising trigger event configuration bit of line 1 */

+#define EXTI_RTSR1_TR2_Pos         (2U)

+#define EXTI_RTSR1_TR2_Msk         (0x1UL << EXTI_RTSR1_TR2_Pos)               /*!< 0x00000004 */

+#define EXTI_RTSR1_TR2             EXTI_RTSR1_TR2_Msk                          /*!< Rising trigger event configuration bit of line 2 */

+#define EXTI_RTSR1_TR3_Pos         (3U)

+#define EXTI_RTSR1_TR3_Msk         (0x1UL << EXTI_RTSR1_TR3_Pos)               /*!< 0x00000008 */

+#define EXTI_RTSR1_TR3             EXTI_RTSR1_TR3_Msk                          /*!< Rising trigger event configuration bit of line 3 */

+#define EXTI_RTSR1_TR4_Pos         (4U)

+#define EXTI_RTSR1_TR4_Msk         (0x1UL << EXTI_RTSR1_TR4_Pos)               /*!< 0x00000010 */

+#define EXTI_RTSR1_TR4             EXTI_RTSR1_TR4_Msk                          /*!< Rising trigger event configuration bit of line 4 */

+#define EXTI_RTSR1_TR5_Pos         (5U)

+#define EXTI_RTSR1_TR5_Msk         (0x1UL << EXTI_RTSR1_TR5_Pos)               /*!< 0x00000020 */

+#define EXTI_RTSR1_TR5             EXTI_RTSR1_TR5_Msk                          /*!< Rising trigger event configuration bit of line 5 */

+#define EXTI_RTSR1_TR6_Pos         (6U)

+#define EXTI_RTSR1_TR6_Msk         (0x1UL << EXTI_RTSR1_TR6_Pos)               /*!< 0x00000040 */

+#define EXTI_RTSR1_TR6             EXTI_RTSR1_TR6_Msk                          /*!< Rising trigger event configuration bit of line 6 */

+#define EXTI_RTSR1_TR7_Pos         (7U)

+#define EXTI_RTSR1_TR7_Msk         (0x1UL << EXTI_RTSR1_TR7_Pos)               /*!< 0x00000080 */

+#define EXTI_RTSR1_TR7             EXTI_RTSR1_TR7_Msk                          /*!< Rising trigger event configuration bit of line 7 */

+#define EXTI_RTSR1_TR8_Pos         (8U)

+#define EXTI_RTSR1_TR8_Msk         (0x1UL << EXTI_RTSR1_TR8_Pos)               /*!< 0x00000100 */

+#define EXTI_RTSR1_TR8             EXTI_RTSR1_TR8_Msk                          /*!< Rising trigger event configuration bit of line 8 */

+#define EXTI_RTSR1_TR9_Pos         (9U)

+#define EXTI_RTSR1_TR9_Msk         (0x1UL << EXTI_RTSR1_TR9_Pos)               /*!< 0x00000200 */

+#define EXTI_RTSR1_TR9             EXTI_RTSR1_TR9_Msk                          /*!< Rising trigger event configuration bit of line 9 */

+#define EXTI_RTSR1_TR10_Pos        (10U)

+#define EXTI_RTSR1_TR10_Msk        (0x1UL << EXTI_RTSR1_TR10_Pos)              /*!< 0x00000400 */

+#define EXTI_RTSR1_TR10            EXTI_RTSR1_TR10_Msk                         /*!< Rising trigger event configuration bit of line 10 */

+#define EXTI_RTSR1_TR11_Pos        (11U)

+#define EXTI_RTSR1_TR11_Msk        (0x1UL << EXTI_RTSR1_TR11_Pos)              /*!< 0x00000800 */

+#define EXTI_RTSR1_TR11            EXTI_RTSR1_TR11_Msk                         /*!< Rising trigger event configuration bit of line 11 */

+#define EXTI_RTSR1_TR12_Pos        (12U)

+#define EXTI_RTSR1_TR12_Msk        (0x1UL << EXTI_RTSR1_TR12_Pos)              /*!< 0x00001000 */

+#define EXTI_RTSR1_TR12            EXTI_RTSR1_TR12_Msk                         /*!< Rising trigger event configuration bit of line 12 */

+#define EXTI_RTSR1_TR13_Pos        (13U)

+#define EXTI_RTSR1_TR13_Msk        (0x1UL << EXTI_RTSR1_TR13_Pos)              /*!< 0x00002000 */

+#define EXTI_RTSR1_TR13            EXTI_RTSR1_TR13_Msk                         /*!< Rising trigger event configuration bit of line 13 */

+#define EXTI_RTSR1_TR14_Pos        (14U)

+#define EXTI_RTSR1_TR14_Msk        (0x1UL << EXTI_RTSR1_TR14_Pos)              /*!< 0x00004000 */

+#define EXTI_RTSR1_TR14            EXTI_RTSR1_TR14_Msk                         /*!< Rising trigger event configuration bit of line 14 */

+#define EXTI_RTSR1_TR15_Pos        (15U)

+#define EXTI_RTSR1_TR15_Msk        (0x1UL << EXTI_RTSR1_TR15_Pos)              /*!< 0x00008000 */

+#define EXTI_RTSR1_TR15            EXTI_RTSR1_TR15_Msk                         /*!< Rising trigger event configuration bit of line 15 */

+#define EXTI_RTSR1_TR16_Pos        (16U)

+#define EXTI_RTSR1_TR16_Msk        (0x1UL << EXTI_RTSR1_TR16_Pos)              /*!< 0x00010000 */

+#define EXTI_RTSR1_TR16            EXTI_RTSR1_TR16_Msk                         /*!< Rising trigger event configuration bit of line 16 */

+#define EXTI_RTSR1_TR17_Pos        (17U)

+#define EXTI_RTSR1_TR17_Msk        (0x1UL << EXTI_RTSR1_TR17_Pos)              /*!< 0x00020000 */

+#define EXTI_RTSR1_TR17            EXTI_RTSR1_TR17_Msk                         /*!< Rising trigger event configuration bit of line 17 */

+#define EXTI_RTSR1_TR18_Pos        (18U)

+#define EXTI_RTSR1_TR18_Msk        (0x1UL << EXTI_RTSR1_TR18_Pos)              /*!< 0x00040000 */

+#define EXTI_RTSR1_TR18            EXTI_RTSR1_TR18_Msk                         /*!< Rising trigger event configuration bit of line 18 */

+#define EXTI_RTSR1_TR19_Pos        (19U)

+#define EXTI_RTSR1_TR19_Msk        (0x1UL << EXTI_RTSR1_TR19_Pos)              /*!< 0x00080000 */

+#define EXTI_RTSR1_TR19            EXTI_RTSR1_TR19_Msk                         /*!< Rising trigger event configuration bit of line 19 */

+#define EXTI_RTSR1_TR20_Pos        (20U)

+#define EXTI_RTSR1_TR20_Msk        (0x1UL << EXTI_RTSR1_TR20_Pos)              /*!< 0x00100000 */

+#define EXTI_RTSR1_TR20            EXTI_RTSR1_TR20_Msk                         /*!< Rising trigger event configuration bit of line 20 */

+#define EXTI_RTSR1_TR21_Pos        (21U)

+#define EXTI_RTSR1_TR21_Msk        (0x1UL << EXTI_RTSR1_TR21_Pos)              /*!< 0x00200000 */

+#define EXTI_RTSR1_TR21            EXTI_RTSR1_TR21_Msk                         /*!< Rising trigger event configuration bit of line 21 */

+

+/******************  Bit definition for EXTI_FTSR1 register  *******************/

+#define EXTI_FTSR1_TR_Pos          (0U)

+#define EXTI_FTSR1_TR_Msk          (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)           /*!< 0x003FFFFF */

+#define EXTI_FTSR1_TR              EXTI_FTSR1_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR1_TR0_Pos         (0U)

+#define EXTI_FTSR1_TR0_Msk         (0x1UL << EXTI_FTSR1_TR0_Pos)               /*!< 0x00000001 */

+#define EXTI_FTSR1_TR0             EXTI_FTSR1_TR0_Msk                          /*!< Falling trigger event configuration bit of line 0 */

+#define EXTI_FTSR1_TR1_Pos         (1U)

+#define EXTI_FTSR1_TR1_Msk         (0x1UL << EXTI_FTSR1_TR1_Pos)               /*!< 0x00000002 */

+#define EXTI_FTSR1_TR1             EXTI_FTSR1_TR1_Msk                          /*!< Falling trigger event configuration bit of line 1 */

+#define EXTI_FTSR1_TR2_Pos         (2U)

+#define EXTI_FTSR1_TR2_Msk         (0x1UL << EXTI_FTSR1_TR2_Pos)               /*!< 0x00000004 */

+#define EXTI_FTSR1_TR2             EXTI_FTSR1_TR2_Msk                          /*!< Falling trigger event configuration bit of line 2 */

+#define EXTI_FTSR1_TR3_Pos         (3U)

+#define EXTI_FTSR1_TR3_Msk         (0x1UL << EXTI_FTSR1_TR3_Pos)               /*!< 0x00000008 */

+#define EXTI_FTSR1_TR3             EXTI_FTSR1_TR3_Msk                          /*!< Falling trigger event configuration bit of line 3 */

+#define EXTI_FTSR1_TR4_Pos         (4U)

+#define EXTI_FTSR1_TR4_Msk         (0x1UL << EXTI_FTSR1_TR4_Pos)               /*!< 0x00000010 */

+#define EXTI_FTSR1_TR4             EXTI_FTSR1_TR4_Msk                          /*!< Falling trigger event configuration bit of line 4 */

+#define EXTI_FTSR1_TR5_Pos         (5U)

+#define EXTI_FTSR1_TR5_Msk         (0x1UL << EXTI_FTSR1_TR5_Pos)               /*!< 0x00000020 */

+#define EXTI_FTSR1_TR5             EXTI_FTSR1_TR5_Msk                          /*!< Falling trigger event configuration bit of line 5 */

+#define EXTI_FTSR1_TR6_Pos         (6U)

+#define EXTI_FTSR1_TR6_Msk         (0x1UL << EXTI_FTSR1_TR6_Pos)               /*!< 0x00000040 */

+#define EXTI_FTSR1_TR6             EXTI_FTSR1_TR6_Msk                          /*!< Falling trigger event configuration bit of line 6 */

+#define EXTI_FTSR1_TR7_Pos         (7U)

+#define EXTI_FTSR1_TR7_Msk         (0x1UL << EXTI_FTSR1_TR7_Pos)               /*!< 0x00000080 */

+#define EXTI_FTSR1_TR7             EXTI_FTSR1_TR7_Msk                          /*!< Falling trigger event configuration bit of line 7 */

+#define EXTI_FTSR1_TR8_Pos         (8U)

+#define EXTI_FTSR1_TR8_Msk         (0x1UL << EXTI_FTSR1_TR8_Pos)               /*!< 0x00000100 */

+#define EXTI_FTSR1_TR8             EXTI_FTSR1_TR8_Msk                          /*!< Falling trigger event configuration bit of line 8 */

+#define EXTI_FTSR1_TR9_Pos         (9U)

+#define EXTI_FTSR1_TR9_Msk         (0x1UL << EXTI_FTSR1_TR9_Pos)               /*!< 0x00000200 */

+#define EXTI_FTSR1_TR9             EXTI_FTSR1_TR9_Msk                          /*!< Falling trigger event configuration bit of line 9 */

+#define EXTI_FTSR1_TR10_Pos        (10U)

+#define EXTI_FTSR1_TR10_Msk        (0x1UL << EXTI_FTSR1_TR10_Pos)              /*!< 0x00000400 */

+#define EXTI_FTSR1_TR10            EXTI_FTSR1_TR10_Msk                         /*!< Falling trigger event configuration bit of line 10 */

+#define EXTI_FTSR1_TR11_Pos        (11U)

+#define EXTI_FTSR1_TR11_Msk        (0x1UL << EXTI_FTSR1_TR11_Pos)              /*!< 0x00000800 */

+#define EXTI_FTSR1_TR11            EXTI_FTSR1_TR11_Msk                         /*!< Falling trigger event configuration bit of line 11 */

+#define EXTI_FTSR1_TR12_Pos        (12U)

+#define EXTI_FTSR1_TR12_Msk        (0x1UL << EXTI_FTSR1_TR12_Pos)              /*!< 0x00001000 */

+#define EXTI_FTSR1_TR12            EXTI_FTSR1_TR12_Msk                         /*!< Falling trigger event configuration bit of line 12 */

+#define EXTI_FTSR1_TR13_Pos        (13U)

+#define EXTI_FTSR1_TR13_Msk        (0x1UL << EXTI_FTSR1_TR13_Pos)              /*!< 0x00002000 */

+#define EXTI_FTSR1_TR13            EXTI_FTSR1_TR13_Msk                         /*!< Falling trigger event configuration bit of line 13 */

+#define EXTI_FTSR1_TR14_Pos        (14U)

+#define EXTI_FTSR1_TR14_Msk        (0x1UL << EXTI_FTSR1_TR14_Pos)              /*!< 0x00004000 */

+#define EXTI_FTSR1_TR14            EXTI_FTSR1_TR14_Msk                         /*!< Falling trigger event configuration bit of line 14 */

+#define EXTI_FTSR1_TR15_Pos        (15U)

+#define EXTI_FTSR1_TR15_Msk        (0x1UL << EXTI_FTSR1_TR15_Pos)              /*!< 0x00008000 */

+#define EXTI_FTSR1_TR15            EXTI_FTSR1_TR15_Msk                         /*!< Falling trigger event configuration bit of line 15 */

+#define EXTI_FTSR1_TR16_Pos        (16U)

+#define EXTI_FTSR1_TR16_Msk        (0x1UL << EXTI_FTSR1_TR16_Pos)              /*!< 0x00010000 */

+#define EXTI_FTSR1_TR16            EXTI_FTSR1_TR16_Msk                         /*!< Falling trigger event configuration bit of line 16 */

+#define EXTI_FTSR1_TR17_Pos        (17U)

+#define EXTI_FTSR1_TR17_Msk        (0x1UL << EXTI_FTSR1_TR17_Pos)              /*!< 0x00020000 */

+#define EXTI_FTSR1_TR17            EXTI_FTSR1_TR17_Msk                         /*!< Falling trigger event configuration bit of line 17 */

+#define EXTI_FTSR1_TR18_Pos        (18U)

+#define EXTI_FTSR1_TR18_Msk        (0x1UL << EXTI_FTSR1_TR18_Pos)              /*!< 0x00040000 */

+#define EXTI_FTSR1_TR18            EXTI_FTSR1_TR18_Msk                         /*!< Falling trigger event configuration bit of line 18 */

+#define EXTI_FTSR1_TR19_Pos        (19U)

+#define EXTI_FTSR1_TR19_Msk        (0x1UL << EXTI_FTSR1_TR19_Pos)              /*!< 0x00080000 */

+#define EXTI_FTSR1_TR19            EXTI_FTSR1_TR19_Msk                         /*!< Falling trigger event configuration bit of line 19 */

+#define EXTI_FTSR1_TR20_Pos        (20U)

+#define EXTI_FTSR1_TR20_Msk        (0x1UL << EXTI_FTSR1_TR20_Pos)              /*!< 0x00100000 */

+#define EXTI_FTSR1_TR20            EXTI_FTSR1_TR20_Msk                         /*!< Falling trigger event configuration bit of line 20 */

+#define EXTI_FTSR1_TR21_Pos        (21U)

+#define EXTI_FTSR1_TR21_Msk        (0x1UL << EXTI_FTSR1_TR21_Pos)              /*!< 0x00200000 */

+#define EXTI_FTSR1_TR21            EXTI_FTSR1_TR21_Msk                         /*!< Falling trigger event configuration bit of line 21 */

+

+/******************  Bit definition for EXTI_SWIER1 register  ******************/

+#define EXTI_SWIER1_SWIER0_Pos     (0U)

+#define EXTI_SWIER1_SWIER0_Msk     (0x1UL << EXTI_SWIER1_SWIER0_Pos)           /*!< 0x00000001 */

+#define EXTI_SWIER1_SWIER0         EXTI_SWIER1_SWIER0_Msk                      /*!< Software Interrupt on line 0 */

+#define EXTI_SWIER1_SWIER1_Pos     (1U)

+#define EXTI_SWIER1_SWIER1_Msk     (0x1UL << EXTI_SWIER1_SWIER1_Pos)           /*!< 0x00000002 */

+#define EXTI_SWIER1_SWIER1         EXTI_SWIER1_SWIER1_Msk                      /*!< Software Interrupt on line 1 */

+#define EXTI_SWIER1_SWIER2_Pos     (2U)

+#define EXTI_SWIER1_SWIER2_Msk     (0x1UL << EXTI_SWIER1_SWIER2_Pos)           /*!< 0x00000004 */

+#define EXTI_SWIER1_SWIER2         EXTI_SWIER1_SWIER2_Msk                      /*!< Software Interrupt on line 2 */

+#define EXTI_SWIER1_SWIER3_Pos     (3U)

+#define EXTI_SWIER1_SWIER3_Msk     (0x1UL << EXTI_SWIER1_SWIER3_Pos)           /*!< 0x00000008 */

+#define EXTI_SWIER1_SWIER3         EXTI_SWIER1_SWIER3_Msk                      /*!< Software Interrupt on line 3 */

+#define EXTI_SWIER1_SWIER4_Pos     (4U)

+#define EXTI_SWIER1_SWIER4_Msk     (0x1UL << EXTI_SWIER1_SWIER4_Pos)           /*!< 0x00000010 */

+#define EXTI_SWIER1_SWIER4         EXTI_SWIER1_SWIER4_Msk                      /*!< Software Interrupt on line 4 */

+#define EXTI_SWIER1_SWIER5_Pos     (5U)

+#define EXTI_SWIER1_SWIER5_Msk     (0x1UL << EXTI_SWIER1_SWIER5_Pos)           /*!< 0x00000020 */

+#define EXTI_SWIER1_SWIER5         EXTI_SWIER1_SWIER5_Msk                      /*!< Software Interrupt on line 5 */

+#define EXTI_SWIER1_SWIER6_Pos     (6U)

+#define EXTI_SWIER1_SWIER6_Msk     (0x1UL << EXTI_SWIER1_SWIER6_Pos)           /*!< 0x00000040 */

+#define EXTI_SWIER1_SWIER6         EXTI_SWIER1_SWIER6_Msk                      /*!< Software Interrupt on line 6 */

+#define EXTI_SWIER1_SWIER7_Pos     (7U)

+#define EXTI_SWIER1_SWIER7_Msk     (0x1UL << EXTI_SWIER1_SWIER7_Pos)           /*!< 0x00000080 */

+#define EXTI_SWIER1_SWIER7         EXTI_SWIER1_SWIER7_Msk                      /*!< Software Interrupt on line 7 */

+#define EXTI_SWIER1_SWIER8_Pos     (8U)

+#define EXTI_SWIER1_SWIER8_Msk     (0x1UL << EXTI_SWIER1_SWIER8_Pos)           /*!< 0x00000100 */

+#define EXTI_SWIER1_SWIER8         EXTI_SWIER1_SWIER8_Msk                      /*!< Software Interrupt on line 8 */

+#define EXTI_SWIER1_SWIER9_Pos     (9U)

+#define EXTI_SWIER1_SWIER9_Msk     (0x1UL << EXTI_SWIER1_SWIER9_Pos)           /*!< 0x00000200 */

+#define EXTI_SWIER1_SWIER9         EXTI_SWIER1_SWIER9_Msk                      /*!< Software Interrupt on line 9 */

+#define EXTI_SWIER1_SWIER10_Pos    (10U)

+#define EXTI_SWIER1_SWIER10_Msk    (0x1UL << EXTI_SWIER1_SWIER10_Pos)          /*!< 0x00000400 */

+#define EXTI_SWIER1_SWIER10        EXTI_SWIER1_SWIER10_Msk                     /*!< Software Interrupt on line 10 */

+#define EXTI_SWIER1_SWIER11_Pos    (11U)

+#define EXTI_SWIER1_SWIER11_Msk    (0x1UL << EXTI_SWIER1_SWIER11_Pos)          /*!< 0x00000800 */

+#define EXTI_SWIER1_SWIER11        EXTI_SWIER1_SWIER11_Msk                     /*!< Software Interrupt on line 11 */

+#define EXTI_SWIER1_SWIER12_Pos    (12U)

+#define EXTI_SWIER1_SWIER12_Msk    (0x1UL << EXTI_SWIER1_SWIER12_Pos)          /*!< 0x00001000 */

+#define EXTI_SWIER1_SWIER12        EXTI_SWIER1_SWIER12_Msk                     /*!< Software Interrupt on line 12 */

+#define EXTI_SWIER1_SWIER13_Pos    (13U)

+#define EXTI_SWIER1_SWIER13_Msk    (0x1UL << EXTI_SWIER1_SWIER13_Pos)          /*!< 0x00002000 */

+#define EXTI_SWIER1_SWIER13        EXTI_SWIER1_SWIER13_Msk                     /*!< Software Interrupt on line 13 */

+#define EXTI_SWIER1_SWIER14_Pos    (14U)

+#define EXTI_SWIER1_SWIER14_Msk    (0x1UL << EXTI_SWIER1_SWIER14_Pos)          /*!< 0x00004000 */

+#define EXTI_SWIER1_SWIER14        EXTI_SWIER1_SWIER14_Msk                     /*!< Software Interrupt on line 14 */

+#define EXTI_SWIER1_SWIER15_Pos    (15U)

+#define EXTI_SWIER1_SWIER15_Msk    (0x1UL << EXTI_SWIER1_SWIER15_Pos)          /*!< 0x00008000 */

+#define EXTI_SWIER1_SWIER15        EXTI_SWIER1_SWIER15_Msk                     /*!< Software Interrupt on line 15 */

+#define EXTI_SWIER1_SWIER16_Pos    (16U)

+#define EXTI_SWIER1_SWIER16_Msk    (0x1UL << EXTI_SWIER1_SWIER16_Pos)          /*!< 0x00010000 */

+#define EXTI_SWIER1_SWIER16        EXTI_SWIER1_SWIER16_Msk                     /*!< Software Interrupt on line 16 */

+#define EXTI_SWIER1_SWIER17_Pos    (17U)

+#define EXTI_SWIER1_SWIER17_Msk    (0x1UL << EXTI_SWIER1_SWIER17_Pos)          /*!< 0x00020000 */

+#define EXTI_SWIER1_SWIER17        EXTI_SWIER1_SWIER17_Msk                     /*!< Software Interrupt on line 17 */

+#define EXTI_SWIER1_SWIER18_Pos    (18U)

+#define EXTI_SWIER1_SWIER18_Msk    (0x1UL << EXTI_SWIER1_SWIER18_Pos)          /*!< 0x00040000 */

+#define EXTI_SWIER1_SWIER18        EXTI_SWIER1_SWIER18_Msk                     /*!< Software Interrupt on line 18 */

+#define EXTI_SWIER1_SWIER19_Pos    (19U)

+#define EXTI_SWIER1_SWIER19_Msk    (0x1UL << EXTI_SWIER1_SWIER19_Pos)          /*!< 0x00080000 */

+#define EXTI_SWIER1_SWIER19        EXTI_SWIER1_SWIER19_Msk                     /*!< Software Interrupt on line 19 */

+#define EXTI_SWIER1_SWIER20_Pos    (20U)

+#define EXTI_SWIER1_SWIER20_Msk    (0x1UL << EXTI_SWIER1_SWIER20_Pos)          /*!< 0x00100000 */

+#define EXTI_SWIER1_SWIER20        EXTI_SWIER1_SWIER20_Msk                     /*!< Software Interrupt on line 20 */

+#define EXTI_SWIER1_SWIER21_Pos    (21U)

+#define EXTI_SWIER1_SWIER21_Msk    (0x1UL << EXTI_SWIER1_SWIER21_Pos)          /*!< 0x00200000 */

+#define EXTI_SWIER1_SWIER21        EXTI_SWIER1_SWIER21_Msk                     /*!< Software Interrupt on line 21 */

+

+/******************  Bit definition for EXTI_D3PMR1 register  ******************/

+#define EXTI_D3PMR1_MR0_Pos        (0U)

+#define EXTI_D3PMR1_MR0_Msk        (0x1UL << EXTI_D3PMR1_MR0_Pos)              /*!< 0x00000001 */

+#define EXTI_D3PMR1_MR0            EXTI_D3PMR1_MR0_Msk                         /*!< Pending Mask Event for line 0  */

+#define EXTI_D3PMR1_MR1_Pos        (1U)

+#define EXTI_D3PMR1_MR1_Msk        (0x1UL << EXTI_D3PMR1_MR1_Pos)              /*!< 0x00000002 */

+#define EXTI_D3PMR1_MR1            EXTI_D3PMR1_MR1_Msk                         /*!< Pending Mask Event for line 1  */

+#define EXTI_D3PMR1_MR2_Pos        (2U)

+#define EXTI_D3PMR1_MR2_Msk        (0x1UL << EXTI_D3PMR1_MR2_Pos)              /*!< 0x00000004 */

+#define EXTI_D3PMR1_MR2            EXTI_D3PMR1_MR2_Msk                         /*!< Pending Mask Event for line 2  */

+#define EXTI_D3PMR1_MR3_Pos        (3U)

+#define EXTI_D3PMR1_MR3_Msk        (0x1UL << EXTI_D3PMR1_MR3_Pos)              /*!< 0x00000008 */

+#define EXTI_D3PMR1_MR3            EXTI_D3PMR1_MR3_Msk                         /*!< Pending Mask Event for line 3  */

+#define EXTI_D3PMR1_MR4_Pos        (4U)

+#define EXTI_D3PMR1_MR4_Msk        (0x1UL << EXTI_D3PMR1_MR4_Pos)              /*!< 0x00000010 */

+#define EXTI_D3PMR1_MR4            EXTI_D3PMR1_MR4_Msk                         /*!< Pending Mask Event for line 4  */

+#define EXTI_D3PMR1_MR5_Pos        (5U)

+#define EXTI_D3PMR1_MR5_Msk        (0x1UL << EXTI_D3PMR1_MR5_Pos)              /*!< 0x00000020 */

+#define EXTI_D3PMR1_MR5            EXTI_D3PMR1_MR5_Msk                         /*!< Pending Mask Event for line 5  */

+#define EXTI_D3PMR1_MR6_Pos        (6U)

+#define EXTI_D3PMR1_MR6_Msk        (0x1UL << EXTI_D3PMR1_MR6_Pos)              /*!< 0x00000040 */

+#define EXTI_D3PMR1_MR6            EXTI_D3PMR1_MR6_Msk                         /*!< Pending Mask Event for line 6  */

+#define EXTI_D3PMR1_MR7_Pos        (7U)

+#define EXTI_D3PMR1_MR7_Msk        (0x1UL << EXTI_D3PMR1_MR7_Pos)              /*!< 0x00000080 */

+#define EXTI_D3PMR1_MR7            EXTI_D3PMR1_MR7_Msk                         /*!< Pending Mask Event for line 7  */

+#define EXTI_D3PMR1_MR8_Pos        (8U)

+#define EXTI_D3PMR1_MR8_Msk        (0x1UL << EXTI_D3PMR1_MR8_Pos)              /*!< 0x00000100 */

+#define EXTI_D3PMR1_MR8            EXTI_D3PMR1_MR8_Msk                         /*!< Pending Mask Event for line 8  */

+#define EXTI_D3PMR1_MR9_Pos        (9U)

+#define EXTI_D3PMR1_MR9_Msk        (0x1UL << EXTI_D3PMR1_MR9_Pos)              /*!< 0x00000200 */

+#define EXTI_D3PMR1_MR9            EXTI_D3PMR1_MR9_Msk                         /*!< Pending Mask Event for line 9  */

+#define EXTI_D3PMR1_MR10_Pos       (10U)

+#define EXTI_D3PMR1_MR10_Msk       (0x1UL << EXTI_D3PMR1_MR10_Pos)             /*!< 0x00000400 */

+#define EXTI_D3PMR1_MR10           EXTI_D3PMR1_MR10_Msk                        /*!< Pending Mask Event for line 10 */

+#define EXTI_D3PMR1_MR11_Pos       (11U)

+#define EXTI_D3PMR1_MR11_Msk       (0x1UL << EXTI_D3PMR1_MR11_Pos)             /*!< 0x00000800 */

+#define EXTI_D3PMR1_MR11           EXTI_D3PMR1_MR11_Msk                        /*!< Pending Mask Event for line 11 */

+#define EXTI_D3PMR1_MR12_Pos       (12U)

+#define EXTI_D3PMR1_MR12_Msk       (0x1UL << EXTI_D3PMR1_MR12_Pos)             /*!< 0x00001000 */

+#define EXTI_D3PMR1_MR12           EXTI_D3PMR1_MR12_Msk                        /*!< Pending Mask Event for line 12 */

+#define EXTI_D3PMR1_MR13_Pos       (13U)

+#define EXTI_D3PMR1_MR13_Msk       (0x1UL << EXTI_D3PMR1_MR13_Pos)             /*!< 0x00002000 */

+#define EXTI_D3PMR1_MR13           EXTI_D3PMR1_MR13_Msk                        /*!< Pending Mask Event for line 13 */

+#define EXTI_D3PMR1_MR14_Pos       (14U)

+#define EXTI_D3PMR1_MR14_Msk       (0x1UL << EXTI_D3PMR1_MR14_Pos)             /*!< 0x00004000 */

+#define EXTI_D3PMR1_MR14           EXTI_D3PMR1_MR14_Msk                        /*!< Pending Mask Event for line 14 */

+#define EXTI_D3PMR1_MR15_Pos       (15U)

+#define EXTI_D3PMR1_MR15_Msk       (0x1UL << EXTI_D3PMR1_MR15_Pos)             /*!< 0x00008000 */

+#define EXTI_D3PMR1_MR15           EXTI_D3PMR1_MR15_Msk                        /*!< Pending Mask Event for line 15 */

+#define EXTI_D3PMR1_MR19_Pos       (19U)

+#define EXTI_D3PMR1_MR19_Msk       (0x1UL << EXTI_D3PMR1_MR19_Pos)             /*!< 0x00080000 */

+#define EXTI_D3PMR1_MR19           EXTI_D3PMR1_MR19_Msk                        /*!< Pending Mask Event for line 19 */

+#define EXTI_D3PMR1_MR20_Pos       (20U)

+#define EXTI_D3PMR1_MR20_Msk       (0x1UL << EXTI_D3PMR1_MR20_Pos)             /*!< 0x00100000 */

+#define EXTI_D3PMR1_MR20           EXTI_D3PMR1_MR20_Msk                        /*!< Pending Mask Event for line 20 */

+#define EXTI_D3PMR1_MR21_Pos       (21U)

+#define EXTI_D3PMR1_MR21_Msk       (0x1UL << EXTI_D3PMR1_MR21_Pos)             /*!< 0x00200000 */

+#define EXTI_D3PMR1_MR21           EXTI_D3PMR1_MR21_Msk                        /*!< Pending Mask Event for line 21 */

+#define EXTI_D3PMR1_MR25_Pos       (24U)

+#define EXTI_D3PMR1_MR25_Msk       (0x1UL << EXTI_D3PMR1_MR25_Pos)             /*!< 0x01000000 */

+#define EXTI_D3PMR1_MR25           EXTI_D3PMR1_MR25_Msk                        /*!< Pending Mask Event for line 25 */

+

+/*******************  Bit definition for EXTI_D3PCR1L register  ****************/

+#define EXTI_D3PCR1L_PCS0_Pos       (0U)

+#define EXTI_D3PCR1L_PCS0_Msk       (0x3UL << EXTI_D3PCR1L_PCS0_Pos)           /*!< 0x00000003 */

+#define EXTI_D3PCR1L_PCS0           EXTI_D3PCR1L_PCS0_Msk                      /*!< D3 Pending request clear input signal selection on line 0 */

+#define EXTI_D3PCR1L_PCS1_Pos       (2U)

+#define EXTI_D3PCR1L_PCS1_Msk       (0x3UL << EXTI_D3PCR1L_PCS1_Pos)           /*!< 0x000000C0 */

+#define EXTI_D3PCR1L_PCS1           EXTI_D3PCR1L_PCS1_Msk                      /*!< D3 Pending request clear input signal selection on line 1 */

+#define EXTI_D3PCR1L_PCS2_Pos       (4U)

+#define EXTI_D3PCR1L_PCS2_Msk       (0x3UL << EXTI_D3PCR1L_PCS2_Pos)           /*!< 0x00000030 */

+#define EXTI_D3PCR1L_PCS2           EXTI_D3PCR1L_PCS2_Msk                      /*!< D3 Pending request clear input signal selection on line 2 */

+#define EXTI_D3PCR1L_PCS3_Pos       (6U)

+#define EXTI_D3PCR1L_PCS3_Msk       (0x3UL << EXTI_D3PCR1L_PCS3_Pos)           /*!< 0x000000C0 */

+#define EXTI_D3PCR1L_PCS3           EXTI_D3PCR1L_PCS3_Msk                      /*!< D3 Pending request clear input signal selection on line 3 */

+#define EXTI_D3PCR1L_PCS4_Pos       (8U)

+#define EXTI_D3PCR1L_PCS4_Msk       (0x3UL << EXTI_D3PCR1L_PCS4_Pos)           /*!< 0x00000300 */

+#define EXTI_D3PCR1L_PCS4           EXTI_D3PCR1L_PCS4_Msk                      /*!< D3 Pending request clear input signal selection on line 4 */

+#define EXTI_D3PCR1L_PCS5_Pos       (10U)

+#define EXTI_D3PCR1L_PCS5_Msk       (0x3UL << EXTI_D3PCR1L_PCS5_Pos)           /*!< 0x00000C00 */

+#define EXTI_D3PCR1L_PCS5           EXTI_D3PCR1L_PCS5_Msk                      /*!< D3 Pending request clear input signal selection on line 5 */

+#define EXTI_D3PCR1L_PCS6_Pos       (12U)

+#define EXTI_D3PCR1L_PCS6_Msk       (0x3UL << EXTI_D3PCR1L_PCS6_Pos)           /*!< 0x00003000 */

+#define EXTI_D3PCR1L_PCS6           EXTI_D3PCR1L_PCS6_Msk                      /*!< D3 Pending request clear input signal selection on line 6 */

+#define EXTI_D3PCR1L_PCS7_Pos       (14U)

+#define EXTI_D3PCR1L_PCS7_Msk       (0x3UL << EXTI_D3PCR1L_PCS7_Pos)           /*!< 0x0000C000 */

+#define EXTI_D3PCR1L_PCS7           EXTI_D3PCR1L_PCS7_Msk                      /*!< D3 Pending request clear input signal selection on line 7 */

+#define EXTI_D3PCR1L_PCS8_Pos       (16U)

+#define EXTI_D3PCR1L_PCS8_Msk       (0x3UL << EXTI_D3PCR1L_PCS8_Pos)           /*!< 0x00030000 */

+#define EXTI_D3PCR1L_PCS8           EXTI_D3PCR1L_PCS8_Msk                      /*!< D3 Pending request clear input signal selection on line 8 */

+#define EXTI_D3PCR1L_PCS9_Pos       (18U)

+#define EXTI_D3PCR1L_PCS9_Msk       (0x3UL << EXTI_D3PCR1L_PCS9_Pos)           /*!< 0x000C0000 */

+#define EXTI_D3PCR1L_PCS9           EXTI_D3PCR1L_PCS9_Msk                      /*!< D3 Pending request clear input signal selection on line 9 */

+#define EXTI_D3PCR1L_PCS10_Pos      (20U)

+#define EXTI_D3PCR1L_PCS10_Msk      (0x3UL << EXTI_D3PCR1L_PCS10_Pos)          /*!< 0x00300000 */

+#define EXTI_D3PCR1L_PCS10          EXTI_D3PCR1L_PCS10_Msk                     /*!< D3 Pending request clear input signal selection on line 10*/

+#define EXTI_D3PCR1L_PCS11_Pos      (22U)

+#define EXTI_D3PCR1L_PCS11_Msk      (0x3UL << EXTI_D3PCR1L_PCS11_Pos)          /*!< 0x00C00000 */

+#define EXTI_D3PCR1L_PCS11          EXTI_D3PCR1L_PCS11_Msk                     /*!< D3 Pending request clear input signal selection on line 11*/

+#define EXTI_D3PCR1L_PCS12_Pos      (24U)

+#define EXTI_D3PCR1L_PCS12_Msk      (0x3UL << EXTI_D3PCR1L_PCS12_Pos)          /*!< 0x03000000 */

+#define EXTI_D3PCR1L_PCS12          EXTI_D3PCR1L_PCS12_Msk                     /*!< D3 Pending request clear input signal selection on line 12*/

+#define EXTI_D3PCR1L_PCS13_Pos      (26U)

+#define EXTI_D3PCR1L_PCS13_Msk      (0x3UL << EXTI_D3PCR1L_PCS13_Pos)          /*!< 0x0C000000 */

+#define EXTI_D3PCR1L_PCS13          EXTI_D3PCR1L_PCS13_Msk                     /*!< D3 Pending request clear input signal selection on line 13*/

+#define EXTI_D3PCR1L_PCS14_Pos      (28U)

+#define EXTI_D3PCR1L_PCS14_Msk      (0x3UL << EXTI_D3PCR1L_PCS14_Pos)          /*!< 0x30000000 */

+#define EXTI_D3PCR1L_PCS14          EXTI_D3PCR1L_PCS14_Msk                     /*!< D3 Pending request clear input signal selection on line 14*/

+#define EXTI_D3PCR1L_PCS15_Pos      (30U)

+#define EXTI_D3PCR1L_PCS15_Msk      (0x3UL << EXTI_D3PCR1L_PCS15_Pos)          /*!< 0xC0000000 */

+#define EXTI_D3PCR1L_PCS15          EXTI_D3PCR1L_PCS15_Msk                     /*!< D3 Pending request clear input signal selection on line 15*/

+

+/*******************  Bit definition for EXTI_D3PCR1H register  ****************/

+#define EXTI_D3PCR1H_PCS19_Pos       (6U)

+#define EXTI_D3PCR1H_PCS19_Msk       (0x3UL << EXTI_D3PCR1H_PCS19_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR1H_PCS19           EXTI_D3PCR1H_PCS19_Msk                    /*!< D3 Pending request clear input signal selection on line 19 */

+#define EXTI_D3PCR1H_PCS20_Pos       (8U)

+#define EXTI_D3PCR1H_PCS20_Msk       (0x3UL << EXTI_D3PCR1H_PCS20_Pos)         /*!< 0x00000300 */

+#define EXTI_D3PCR1H_PCS20           EXTI_D3PCR1H_PCS20_Msk                    /*!< D3 Pending request clear input signal selection on line 20 */

+#define EXTI_D3PCR1H_PCS21_Pos       (10U)

+#define EXTI_D3PCR1H_PCS21_Msk       (0x3UL << EXTI_D3PCR1H_PCS21_Pos)         /*!< 0x00000C00 */

+#define EXTI_D3PCR1H_PCS21           EXTI_D3PCR1H_PCS21_Msk                    /*!< D3 Pending request clear input signal selection on line 21 */

+#define EXTI_D3PCR1H_PCS25_Pos       (18U)

+#define EXTI_D3PCR1H_PCS25_Msk       (0x3UL << EXTI_D3PCR1H_PCS25_Pos)         /*!< 0x000C0000 */

+#define EXTI_D3PCR1H_PCS25           EXTI_D3PCR1H_PCS25_Msk                    /*!< D3 Pending request clear input signal selection on line 25 */

+

+/******************  Bit definition for EXTI_RTSR2 register  *******************/

+#define EXTI_RTSR2_TR_Pos          (17U)

+#define EXTI_RTSR2_TR_Msk          (0x5UL << EXTI_RTSR2_TR_Pos)                /*!< 0x000A0000 */

+#define EXTI_RTSR2_TR              EXTI_RTSR2_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR2_TR49_Pos        (17U)

+#define EXTI_RTSR2_TR49_Msk        (0x1UL << EXTI_RTSR2_TR49_Pos)              /*!< 0x00020000 */

+#define EXTI_RTSR2_TR49            EXTI_RTSR2_TR49_Msk                         /*!< Rising trigger event configuration bit of line 49 */

+#define EXTI_RTSR2_TR51_Pos        (19U)

+#define EXTI_RTSR2_TR51_Msk        (0x1UL << EXTI_RTSR2_TR51_Pos)              /*!< 0x00080000 */

+#define EXTI_RTSR2_TR51            EXTI_RTSR2_TR51_Msk                         /*!< Rising trigger event configuration bit of line 51 */

+

+/******************  Bit definition for EXTI_FTSR2 register  *******************/

+#define EXTI_FTSR2_TR_Pos          (17U)

+#define EXTI_FTSR2_TR_Msk          (0x5UL << EXTI_FTSR2_TR_Pos)                /*!< 0x000A0000 */

+#define EXTI_FTSR2_TR              EXTI_FTSR2_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR2_TR49_Pos        (17U)

+#define EXTI_FTSR2_TR49_Msk        (0x1UL << EXTI_FTSR2_TR49_Pos)              /*!< 0x00020000 */

+#define EXTI_FTSR2_TR49            EXTI_FTSR2_TR49_Msk                         /*!< Falling trigger event configuration bit of line 49 */

+#define EXTI_FTSR2_TR51_Pos        (19U)

+#define EXTI_FTSR2_TR51_Msk        (0x1UL << EXTI_FTSR2_TR51_Pos)              /*!< 0x00080000 */

+#define EXTI_FTSR2_TR51            EXTI_FTSR2_TR51_Msk                         /*!< Falling trigger event configuration bit of line 51 */

+

+/******************  Bit definition for EXTI_SWIER2 register  ******************/

+#define EXTI_SWIER2_SWIER49_Pos    (17U)

+#define EXTI_SWIER2_SWIER49_Msk    (0x1UL << EXTI_SWIER2_SWIER49_Pos)          /*!< 0x00020000 */

+#define EXTI_SWIER2_SWIER49        EXTI_SWIER2_SWIER49_Msk                     /*!< Software Interrupt on line 49 */

+#define EXTI_SWIER2_SWIER51_Pos    (19U)

+#define EXTI_SWIER2_SWIER51_Msk    (0x1UL << EXTI_SWIER2_SWIER51_Pos)          /*!< 0x00080000 */

+#define EXTI_SWIER2_SWIER51        EXTI_SWIER2_SWIER51_Msk                     /*!< Software Interrupt on line 51 */

+

+/******************  Bit definition for EXTI_D3PMR2 register  ******************/

+#define EXTI_D3PMR2_MR34_Pos       (2U)

+#define EXTI_D3PMR2_MR34_Msk       (0x1UL << EXTI_D3PMR2_MR34_Pos)             /*!< 0x00000004 */

+#define EXTI_D3PMR2_MR34           EXTI_D3PMR2_MR34_Msk                        /*!< Pending Mask Event for line 34  */

+#define EXTI_D3PMR2_MR35_Pos       (3U)

+#define EXTI_D3PMR2_MR35_Msk       (0x1UL << EXTI_D3PMR2_MR35_Pos)             /*!< 0x00000008 */

+#define EXTI_D3PMR2_MR35           EXTI_D3PMR2_MR35_Msk                        /*!< Pending Mask Event for line 35  */

+#define EXTI_D3PMR2_MR41_Pos       (9U)

+#define EXTI_D3PMR2_MR41_Msk       (0x1UL << EXTI_D3PMR2_MR41_Pos)             /*!< 0x00000200 */

+#define EXTI_D3PMR2_MR41           EXTI_D3PMR2_MR41_Msk                        /*!< Pending Mask Event for line 41  */

+#define EXTI_D3PMR2_MR48_Pos       (16U)

+#define EXTI_D3PMR2_MR48_Msk       (0x1UL << EXTI_D3PMR2_MR48_Pos)             /*!< 0x00010000 */

+#define EXTI_D3PMR2_MR48           EXTI_D3PMR2_MR48_Msk                        /*!< Pending Mask Event for line 48  */

+#define EXTI_D3PMR2_MR49_Pos       (17U)

+#define EXTI_D3PMR2_MR49_Msk       (0x1UL << EXTI_D3PMR2_MR49_Pos)             /*!< 0x00020000 */

+#define EXTI_D3PMR2_MR49           EXTI_D3PMR2_MR49_Msk                        /*!< Pending Mask Event for line 49  */

+#define EXTI_D3PMR2_MR50_Pos       (18U)

+#define EXTI_D3PMR2_MR50_Msk       (0x1UL << EXTI_D3PMR2_MR50_Pos)             /*!< 0x00040000 */

+#define EXTI_D3PMR2_MR50           EXTI_D3PMR2_MR50_Msk                        /*!< Pending Mask Event for line 50  */

+#define EXTI_D3PMR2_MR51_Pos       (19U)

+#define EXTI_D3PMR2_MR51_Msk       (0x1UL << EXTI_D3PMR2_MR51_Pos)             /*!< 0x00080000 */

+#define EXTI_D3PMR2_MR51           EXTI_D3PMR2_MR51_Msk                        /*!< Pending Mask Event for line 51  */

+#define EXTI_D3PMR2_MR52_Pos       (20U)

+#define EXTI_D3PMR2_MR52_Msk       (0x1UL << EXTI_D3PMR2_MR52_Pos)             /*!< 0x00100000 */

+#define EXTI_D3PMR2_MR52           EXTI_D3PMR2_MR52_Msk                        /*!< Pending Mask Event for line 52  */

+#define EXTI_D3PMR2_MR53_Pos       (21U)

+#define EXTI_D3PMR2_MR53_Msk       (0x1UL << EXTI_D3PMR2_MR53_Pos)             /*!< 0x00200000 */

+#define EXTI_D3PMR2_MR53           EXTI_D3PMR2_MR53_Msk                        /*!< Pending Mask Event for line 53  */

+/*******************  Bit definition for EXTI_D3PCR2L register  ****************/

+#define EXTI_D3PCR2L_PCS34_Pos       (4U)

+#define EXTI_D3PCR2L_PCS34_Msk       (0x3UL << EXTI_D3PCR2L_PCS34_Pos)         /*!< 0x00000030 */

+#define EXTI_D3PCR2L_PCS34           EXTI_D3PCR2L_PCS34_Msk                    /*!< D3 Pending request clear input signal selection on line 34 */

+#define EXTI_D3PCR2L_PCS35_Pos       (6U)

+#define EXTI_D3PCR2L_PCS35_Msk       (0x3UL << EXTI_D3PCR2L_PCS35_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR2L_PCS35           EXTI_D3PCR2L_PCS35_Msk                    /*!< D3 Pending request clear input signal selection on line 35 */

+#define EXTI_D3PCR2L_PCS41_Pos       (18U)

+#define EXTI_D3PCR2L_PCS41_Msk       (0x3UL << EXTI_D3PCR2L_PCS41_Pos)         /*!< 0x000C0000 */

+#define EXTI_D3PCR2L_PCS41           EXTI_D3PCR2L_PCS41_Msk                    /*!< D3 Pending request clear input signal selection on line 41 */

+

+

+/*******************  Bit definition for EXTI_D3PCR2H register  ****************/

+#define EXTI_D3PCR2H_PCS48_Pos       (0U)

+#define EXTI_D3PCR2H_PCS48_Msk       (0x3UL << EXTI_D3PCR2H_PCS48_Pos)         /*!< 0x00000003 */

+#define EXTI_D3PCR2H_PCS48           EXTI_D3PCR2H_PCS48_Msk                    /*!< D3 Pending request clear input signal selection on line 48 */

+#define EXTI_D3PCR2H_PCS49_Pos       (2U)

+#define EXTI_D3PCR2H_PCS49_Msk       (0x3UL << EXTI_D3PCR2H_PCS49_Pos)         /*!< 0x0000000C */

+#define EXTI_D3PCR2H_PCS49           EXTI_D3PCR2H_PCS49_Msk                    /*!< D3 Pending request clear input signal selection on line 49 */

+#define EXTI_D3PCR2H_PCS50_Pos       (4U)

+#define EXTI_D3PCR2H_PCS50_Msk       (0x3UL << EXTI_D3PCR2H_PCS50_Pos)         /*!< 0x00000030 */

+#define EXTI_D3PCR2H_PCS50           EXTI_D3PCR2H_PCS50_Msk                    /*!< D3 Pending request clear input signal selection on line 50 */

+#define EXTI_D3PCR2H_PCS51_Pos       (6U)

+#define EXTI_D3PCR2H_PCS51_Msk       (0x3UL << EXTI_D3PCR2H_PCS51_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR2H_PCS51           EXTI_D3PCR2H_PCS51_Msk                    /*!< D3 Pending request clear input signal selection on line 51 */

+#define EXTI_D3PCR2H_PCS52_Pos       (8U)

+#define EXTI_D3PCR2H_PCS52_Msk       (0x3UL << EXTI_D3PCR2H_PCS52_Pos)         /*!< 0x00000300 */

+#define EXTI_D3PCR2H_PCS52           EXTI_D3PCR2H_PCS52_Msk                    /*!< D3 Pending request clear input signal selection on line 52 */

+#define EXTI_D3PCR2H_PCS53_Pos       (10U)

+#define EXTI_D3PCR2H_PCS53_Msk       (0x3UL << EXTI_D3PCR2H_PCS53_Pos)         /*!< 0x00000C00 */

+#define EXTI_D3PCR2H_PCS53           EXTI_D3PCR2H_PCS53_Msk                    /*!< D3 Pending request clear input signal selection on line 53 */

+/******************  Bit definition for EXTI_RTSR3 register  *******************/

+#define EXTI_RTSR3_TR_Pos          (18U)

+#define EXTI_RTSR3_TR_Msk          (0x1DUL << EXTI_RTSR3_TR_Pos)               /*!< 0x00740000 */

+#define EXTI_RTSR3_TR              EXTI_RTSR3_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR3_TR82_Pos        (18U)

+#define EXTI_RTSR3_TR82_Msk        (0x1UL << EXTI_RTSR3_TR82_Pos)              /*!< 0x00040000 */

+#define EXTI_RTSR3_TR82            EXTI_RTSR3_TR82_Msk                         /*!< Rising trigger event configuration bit of line 82 */

+#define EXTI_RTSR3_TR84_Pos        (20U)

+#define EXTI_RTSR3_TR84_Msk        (0x1UL << EXTI_RTSR3_TR84_Pos)              /*!< 0x00100000 */

+#define EXTI_RTSR3_TR84            EXTI_RTSR3_TR84_Msk                         /*!< Rising trigger event configuration bit of line 84 */

+#define EXTI_RTSR3_TR85_Pos        (21U)

+#define EXTI_RTSR3_TR85_Msk        (0x1UL << EXTI_RTSR3_TR85_Pos)              /*!< 0x00200000 */

+#define EXTI_RTSR3_TR85            EXTI_RTSR3_TR85_Msk                         /*!< Rising trigger event configuration bit of line 85 */

+#define EXTI_RTSR3_TR86_Pos        (22U)

+#define EXTI_RTSR3_TR86_Msk        (0x1UL << EXTI_RTSR3_TR86_Pos)              /*!< 0x00400000 */

+#define EXTI_RTSR3_TR86            EXTI_RTSR3_TR86_Msk                         /*!< Rising trigger event configuration bit of line 86 */

+

+/******************  Bit definition for EXTI_FTSR3 register  *******************/

+#define EXTI_FTSR3_TR_Pos          (18U)

+#define EXTI_FTSR3_TR_Msk          (0x1DUL << EXTI_FTSR3_TR_Pos)               /*!< 0x00740000 */

+#define EXTI_FTSR3_TR              EXTI_FTSR3_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR3_TR82_Pos        (18U)

+#define EXTI_FTSR3_TR82_Msk        (0x1UL << EXTI_FTSR3_TR82_Pos)              /*!< 0x00040000 */

+#define EXTI_FTSR3_TR82            EXTI_FTSR3_TR82_Msk                         /*!< Falling trigger event configuration bit of line 82 */

+#define EXTI_FTSR3_TR84_Pos        (20U)

+#define EXTI_FTSR3_TR84_Msk        (0x1UL << EXTI_FTSR3_TR84_Pos)              /*!< 0x00100000 */

+#define EXTI_FTSR3_TR84            EXTI_FTSR3_TR84_Msk                         /*!< Falling trigger event configuration bit of line 84 */

+#define EXTI_FTSR3_TR85_Pos        (21U)

+#define EXTI_FTSR3_TR85_Msk        (0x1UL << EXTI_FTSR3_TR85_Pos)              /*!< 0x00200000 */

+#define EXTI_FTSR3_TR85            EXTI_FTSR3_TR85_Msk                         /*!< Falling trigger event configuration bit of line 85 */

+#define EXTI_FTSR3_TR86_Pos        (22U)

+#define EXTI_FTSR3_TR86_Msk        (0x1UL << EXTI_FTSR3_TR86_Pos)              /*!< 0x00400000 */

+#define EXTI_FTSR3_TR86            EXTI_FTSR3_TR86_Msk                         /*!< Falling trigger event configuration bit of line 86 */

+

+/******************  Bit definition for EXTI_SWIER3 register  ******************/

+#define EXTI_SWIER3_SWI_Pos        (18U)

+#define EXTI_SWIER3_SWI_Msk        (0x1DUL << EXTI_SWIER3_SWI_Pos)             /*!< 0x00740000 */

+#define EXTI_SWIER3_SWI            EXTI_SWIER3_SWI_Msk                         /*!< Software Interrupt event bit */

+#define EXTI_SWIER3_SWIER82_Pos    (18U)

+#define EXTI_SWIER3_SWIER82_Msk    (0x1UL << EXTI_SWIER3_SWIER82_Pos)          /*!< 0x00040000 */

+#define EXTI_SWIER3_SWIER82        EXTI_SWIER3_SWIER82_Msk                     /*!< Software Interrupt on line 82 */

+#define EXTI_SWIER3_SWIER84_Pos    (20U)

+#define EXTI_SWIER3_SWIER84_Msk    (0x1UL << EXTI_SWIER3_SWIER84_Pos)          /*!< 0x00100000 */

+#define EXTI_SWIER3_SWIER84        EXTI_SWIER3_SWIER84_Msk                     /*!< Software Interrupt on line 84 */

+#define EXTI_SWIER3_SWIER85_Pos    (21U)

+#define EXTI_SWIER3_SWIER85_Msk    (0x1UL << EXTI_SWIER3_SWIER85_Pos)          /*!< 0x00200000 */

+#define EXTI_SWIER3_SWIER85        EXTI_SWIER3_SWIER85_Msk                     /*!< Software Interrupt on line 85 */

+#define EXTI_SWIER3_SWIER86_Pos    (22U)

+#define EXTI_SWIER3_SWIER86_Msk    (0x1UL << EXTI_SWIER3_SWIER86_Pos)          /*!< 0x00400000 */

+#define EXTI_SWIER3_SWIER86        EXTI_SWIER3_SWIER86_Msk                     /*!< Software Interrupt on line 86 */

+

+/*******************  Bit definition for EXTI_IMR1 register  *******************/

+#define EXTI_IMR1_IM_Pos           (0U)

+#define EXTI_IMR1_IM_Msk           (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)          /*!< 0xFFFFFFFF */

+#define EXTI_IMR1_IM               EXTI_IMR1_IM_Msk                            /*!< Interrupt Mask */

+#define EXTI_IMR1_IM0_Pos          (0U)

+#define EXTI_IMR1_IM0_Msk          (0x1UL << EXTI_IMR1_IM0_Pos)                /*!< 0x00000001 */

+#define EXTI_IMR1_IM0              EXTI_IMR1_IM0_Msk                           /*!< Interrupt Mask on line 0 */

+#define EXTI_IMR1_IM1_Pos          (1U)

+#define EXTI_IMR1_IM1_Msk          (0x1UL << EXTI_IMR1_IM1_Pos)                /*!< 0x00000002 */

+#define EXTI_IMR1_IM1              EXTI_IMR1_IM1_Msk                           /*!< Interrupt Mask on line 1 */

+#define EXTI_IMR1_IM2_Pos          (2U)

+#define EXTI_IMR1_IM2_Msk          (0x1UL << EXTI_IMR1_IM2_Pos)                /*!< 0x00000004 */

+#define EXTI_IMR1_IM2              EXTI_IMR1_IM2_Msk                           /*!< Interrupt Mask on line 2 */

+#define EXTI_IMR1_IM3_Pos          (3U)

+#define EXTI_IMR1_IM3_Msk          (0x1UL << EXTI_IMR1_IM3_Pos)                /*!< 0x00000008 */

+#define EXTI_IMR1_IM3              EXTI_IMR1_IM3_Msk                           /*!< Interrupt Mask on line 3 */

+#define EXTI_IMR1_IM4_Pos          (4U)

+#define EXTI_IMR1_IM4_Msk          (0x1UL << EXTI_IMR1_IM4_Pos)                /*!< 0x00000010 */

+#define EXTI_IMR1_IM4              EXTI_IMR1_IM4_Msk                           /*!< Interrupt Mask on line 4 */

+#define EXTI_IMR1_IM5_Pos          (5U)

+#define EXTI_IMR1_IM5_Msk          (0x1UL << EXTI_IMR1_IM5_Pos)                /*!< 0x00000020 */

+#define EXTI_IMR1_IM5              EXTI_IMR1_IM5_Msk                           /*!< Interrupt Mask on line 5 */

+#define EXTI_IMR1_IM6_Pos          (6U)

+#define EXTI_IMR1_IM6_Msk          (0x1UL << EXTI_IMR1_IM6_Pos)                /*!< 0x00000040 */

+#define EXTI_IMR1_IM6              EXTI_IMR1_IM6_Msk                           /*!< Interrupt Mask on line 6 */

+#define EXTI_IMR1_IM7_Pos          (7U)

+#define EXTI_IMR1_IM7_Msk          (0x1UL << EXTI_IMR1_IM7_Pos)                /*!< 0x00000080 */

+#define EXTI_IMR1_IM7              EXTI_IMR1_IM7_Msk                           /*!< Interrupt Mask on line 7 */

+#define EXTI_IMR1_IM8_Pos          (8U)

+#define EXTI_IMR1_IM8_Msk          (0x1UL << EXTI_IMR1_IM8_Pos)                /*!< 0x00000100 */

+#define EXTI_IMR1_IM8              EXTI_IMR1_IM8_Msk                           /*!< Interrupt Mask on line 8 */

+#define EXTI_IMR1_IM9_Pos          (9U)

+#define EXTI_IMR1_IM9_Msk          (0x1UL << EXTI_IMR1_IM9_Pos)                /*!< 0x00000200 */

+#define EXTI_IMR1_IM9              EXTI_IMR1_IM9_Msk                           /*!< Interrupt Mask on line 9 */

+#define EXTI_IMR1_IM10_Pos         (10U)

+#define EXTI_IMR1_IM10_Msk         (0x1UL << EXTI_IMR1_IM10_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR1_IM10             EXTI_IMR1_IM10_Msk                          /*!< Interrupt Mask on line 10 */

+#define EXTI_IMR1_IM11_Pos         (11U)

+#define EXTI_IMR1_IM11_Msk         (0x1UL << EXTI_IMR1_IM11_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR1_IM11             EXTI_IMR1_IM11_Msk                          /*!< Interrupt Mask on line 11 */

+#define EXTI_IMR1_IM12_Pos         (12U)

+#define EXTI_IMR1_IM12_Msk         (0x1UL << EXTI_IMR1_IM12_Pos)               /*!< 0x00001000 */

+#define EXTI_IMR1_IM12             EXTI_IMR1_IM12_Msk                          /*!< Interrupt Mask on line 12 */

+#define EXTI_IMR1_IM13_Pos         (13U)

+#define EXTI_IMR1_IM13_Msk         (0x1UL << EXTI_IMR1_IM13_Pos)               /*!< 0x00002000 */

+#define EXTI_IMR1_IM13             EXTI_IMR1_IM13_Msk                          /*!< Interrupt Mask on line 13 */

+#define EXTI_IMR1_IM14_Pos         (14U)

+#define EXTI_IMR1_IM14_Msk         (0x1UL << EXTI_IMR1_IM14_Pos)               /*!< 0x00004000 */

+#define EXTI_IMR1_IM14             EXTI_IMR1_IM14_Msk                          /*!< Interrupt Mask on line 14 */

+#define EXTI_IMR1_IM15_Pos         (15U)

+#define EXTI_IMR1_IM15_Msk         (0x1UL << EXTI_IMR1_IM15_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR1_IM15             EXTI_IMR1_IM15_Msk                          /*!< Interrupt Mask on line 15 */

+#define EXTI_IMR1_IM16_Pos         (16U)

+#define EXTI_IMR1_IM16_Msk         (0x1UL << EXTI_IMR1_IM16_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR1_IM16             EXTI_IMR1_IM16_Msk                          /*!< Interrupt Mask on line 16 */

+#define EXTI_IMR1_IM17_Pos         (17U)

+#define EXTI_IMR1_IM17_Msk         (0x1UL << EXTI_IMR1_IM17_Pos)               /*!< 0x00020000 */

+#define EXTI_IMR1_IM17             EXTI_IMR1_IM17_Msk                          /*!< Interrupt Mask on line 17 */

+#define EXTI_IMR1_IM18_Pos         (18U)

+#define EXTI_IMR1_IM18_Msk         (0x1UL << EXTI_IMR1_IM18_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR1_IM18             EXTI_IMR1_IM18_Msk                          /*!< Interrupt Mask on line 18 */

+#define EXTI_IMR1_IM19_Pos         (19U)

+#define EXTI_IMR1_IM19_Msk         (0x1UL << EXTI_IMR1_IM19_Pos)               /*!< 0x00080000 */

+#define EXTI_IMR1_IM19             EXTI_IMR1_IM19_Msk                          /*!< Interrupt Mask on line 19 */

+#define EXTI_IMR1_IM20_Pos         (20U)

+#define EXTI_IMR1_IM20_Msk         (0x1UL << EXTI_IMR1_IM20_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR1_IM20             EXTI_IMR1_IM20_Msk                          /*!< Interrupt Mask on line 20 */

+#define EXTI_IMR1_IM21_Pos         (21U)

+#define EXTI_IMR1_IM21_Msk         (0x1UL << EXTI_IMR1_IM21_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR1_IM21             EXTI_IMR1_IM21_Msk                          /*!< Interrupt Mask on line 21 */

+#define EXTI_IMR1_IM22_Pos         (22U)

+#define EXTI_IMR1_IM22_Msk         (0x1UL << EXTI_IMR1_IM22_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR1_IM22             EXTI_IMR1_IM22_Msk                          /*!< Interrupt Mask on line 22 */

+#define EXTI_IMR1_IM23_Pos         (23U)

+#define EXTI_IMR1_IM23_Msk         (0x1UL << EXTI_IMR1_IM23_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR1_IM23             EXTI_IMR1_IM23_Msk                          /*!< Interrupt Mask on line 23 */

+#define EXTI_IMR1_IM24_Pos         (24U)

+#define EXTI_IMR1_IM24_Msk         (0x1UL << EXTI_IMR1_IM24_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR1_IM24             EXTI_IMR1_IM24_Msk                          /*!< Interrupt Mask on line 24 */

+#define EXTI_IMR1_IM25_Pos         (25U)

+#define EXTI_IMR1_IM25_Msk         (0x1UL << EXTI_IMR1_IM25_Pos)               /*!< 0x02000000 */

+#define EXTI_IMR1_IM25             EXTI_IMR1_IM25_Msk                          /*!< Interrupt Mask on line 25 */

+#define EXTI_IMR1_IM26_Pos         (26U)

+#define EXTI_IMR1_IM26_Msk         (0x1UL << EXTI_IMR1_IM26_Pos)               /*!< 0x04000000 */

+#define EXTI_IMR1_IM26             EXTI_IMR1_IM26_Msk                          /*!< Interrupt Mask on line 26 */

+#define EXTI_IMR1_IM27_Pos         (27U)

+#define EXTI_IMR1_IM27_Msk         (0x1UL << EXTI_IMR1_IM27_Pos)               /*!< 0x08000000 */

+#define EXTI_IMR1_IM27             EXTI_IMR1_IM27_Msk                          /*!< Interrupt Mask on line 27 */

+#define EXTI_IMR1_IM28_Pos         (28U)

+#define EXTI_IMR1_IM28_Msk         (0x1UL << EXTI_IMR1_IM28_Pos)               /*!< 0x10000000 */

+#define EXTI_IMR1_IM28             EXTI_IMR1_IM28_Msk                          /*!< Interrupt Mask on line 28 */

+#define EXTI_IMR1_IM29_Pos         (29U)

+#define EXTI_IMR1_IM29_Msk         (0x1UL << EXTI_IMR1_IM29_Pos)               /*!< 0x20000000 */

+#define EXTI_IMR1_IM29             EXTI_IMR1_IM29_Msk                          /*!< Interrupt Mask on line 29 */

+#define EXTI_IMR1_IM30_Pos         (30U)

+#define EXTI_IMR1_IM30_Msk         (0x1UL << EXTI_IMR1_IM30_Pos)               /*!< 0x40000000 */

+#define EXTI_IMR1_IM30             EXTI_IMR1_IM30_Msk                          /*!< Interrupt Mask on line 30 */

+#define EXTI_IMR1_IM31_Pos         (31U)

+#define EXTI_IMR1_IM31_Msk         (0x1UL << EXTI_IMR1_IM31_Pos)               /*!< 0x80000000 */

+#define EXTI_IMR1_IM31             EXTI_IMR1_IM31_Msk                          /*!< Interrupt Mask on line 31 */

+

+/*******************  Bit definition for EXTI_EMR1 register  *******************/

+#define EXTI_EMR1_EM_Pos           (0U)

+#define EXTI_EMR1_EM_Msk           (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)          /*!< 0xFFFFFFFF */

+#define EXTI_EMR1_EM               EXTI_EMR1_EM_Msk                            /*!< Event Mask */

+#define EXTI_EMR1_EM0_Pos          (0U)

+#define EXTI_EMR1_EM0_Msk          (0x1UL << EXTI_EMR1_EM0_Pos)                /*!< 0x00000001 */

+#define EXTI_EMR1_EM0              EXTI_EMR1_EM0_Msk                           /*!< Event Mask on line 0 */

+#define EXTI_EMR1_EM1_Pos          (1U)

+#define EXTI_EMR1_EM1_Msk          (0x1UL << EXTI_EMR1_EM1_Pos)                /*!< 0x00000002 */

+#define EXTI_EMR1_EM1              EXTI_EMR1_EM1_Msk                           /*!< Event Mask on line 1 */

+#define EXTI_EMR1_EM2_Pos          (2U)

+#define EXTI_EMR1_EM2_Msk          (0x1UL << EXTI_EMR1_EM2_Pos)                /*!< 0x00000004 */

+#define EXTI_EMR1_EM2              EXTI_EMR1_EM2_Msk                           /*!< Event Mask on line 2 */

+#define EXTI_EMR1_EM3_Pos          (3U)

+#define EXTI_EMR1_EM3_Msk          (0x1UL << EXTI_EMR1_EM3_Pos)                /*!< 0x00000008 */

+#define EXTI_EMR1_EM3              EXTI_EMR1_EM3_Msk                           /*!< Event Mask on line 3 */

+#define EXTI_EMR1_EM4_Pos          (4U)

+#define EXTI_EMR1_EM4_Msk          (0x1UL << EXTI_EMR1_EM4_Pos)                /*!< 0x00000010 */

+#define EXTI_EMR1_EM4              EXTI_EMR1_EM4_Msk                           /*!< Event Mask on line 4 */

+#define EXTI_EMR1_EM5_Pos          (5U)

+#define EXTI_EMR1_EM5_Msk          (0x1UL << EXTI_EMR1_EM5_Pos)                /*!< 0x00000020 */

+#define EXTI_EMR1_EM5              EXTI_EMR1_EM5_Msk                           /*!< Event Mask on line 5 */

+#define EXTI_EMR1_EM6_Pos          (6U)

+#define EXTI_EMR1_EM6_Msk          (0x1UL << EXTI_EMR1_EM6_Pos)                /*!< 0x00000040 */

+#define EXTI_EMR1_EM6              EXTI_EMR1_EM6_Msk                           /*!< Event Mask on line 6 */

+#define EXTI_EMR1_EM7_Pos          (7U)

+#define EXTI_EMR1_EM7_Msk          (0x1UL << EXTI_EMR1_EM7_Pos)                /*!< 0x00000080 */

+#define EXTI_EMR1_EM7              EXTI_EMR1_EM7_Msk                           /*!< Event Mask on line 7 */

+#define EXTI_EMR1_EM8_Pos          (8U)

+#define EXTI_EMR1_EM8_Msk          (0x1UL << EXTI_EMR1_EM8_Pos)                /*!< 0x00000100 */

+#define EXTI_EMR1_EM8              EXTI_EMR1_EM8_Msk                           /*!< Event Mask on line 8 */

+#define EXTI_EMR1_EM9_Pos          (9U)

+#define EXTI_EMR1_EM9_Msk          (0x1UL << EXTI_EMR1_EM9_Pos)                /*!< 0x00000200 */

+#define EXTI_EMR1_EM9              EXTI_EMR1_EM9_Msk                           /*!< Event Mask on line 9 */

+#define EXTI_EMR1_EM10_Pos         (10U)

+#define EXTI_EMR1_EM10_Msk         (0x1UL << EXTI_EMR1_EM10_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR1_EM10             EXTI_EMR1_EM10_Msk                          /*!< Event Mask on line 10 */

+#define EXTI_EMR1_EM11_Pos         (11U)

+#define EXTI_EMR1_EM11_Msk         (0x1UL << EXTI_EMR1_EM11_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR1_EM11             EXTI_EMR1_EM11_Msk                          /*!< Event Mask on line 11 */

+#define EXTI_EMR1_EM12_Pos         (12U)

+#define EXTI_EMR1_EM12_Msk         (0x1UL << EXTI_EMR1_EM12_Pos)               /*!< 0x00001000 */

+#define EXTI_EMR1_EM12             EXTI_EMR1_EM12_Msk                          /*!< Event Mask on line 12 */

+#define EXTI_EMR1_EM13_Pos         (13U)

+#define EXTI_EMR1_EM13_Msk         (0x1UL << EXTI_EMR1_EM13_Pos)               /*!< 0x00002000 */

+#define EXTI_EMR1_EM13             EXTI_EMR1_EM13_Msk                          /*!< Event Mask on line 13 */

+#define EXTI_EMR1_EM14_Pos         (14U)

+#define EXTI_EMR1_EM14_Msk         (0x1UL << EXTI_EMR1_EM14_Pos)               /*!< 0x00004000 */

+#define EXTI_EMR1_EM14             EXTI_EMR1_EM14_Msk                          /*!< Event Mask on line 14 */

+#define EXTI_EMR1_EM15_Pos         (15U)

+#define EXTI_EMR1_EM15_Msk         (0x1UL << EXTI_EMR1_EM15_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR1_EM15             EXTI_EMR1_EM15_Msk                          /*!< Event Mask on line 15 */

+#define EXTI_EMR1_EM16_Pos         (16U)

+#define EXTI_EMR1_EM16_Msk         (0x1UL << EXTI_EMR1_EM16_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR1_EM16             EXTI_EMR1_EM16_Msk                          /*!< Event Mask on line 16 */

+#define EXTI_EMR1_EM17_Pos         (17U)

+#define EXTI_EMR1_EM17_Msk         (0x1UL << EXTI_EMR1_EM17_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR1_EM17             EXTI_EMR1_EM17_Msk                          /*!< Event Mask on line 17 */

+#define EXTI_EMR1_EM18_Pos         (18U)

+#define EXTI_EMR1_EM18_Msk         (0x1UL << EXTI_EMR1_EM18_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR1_EM18             EXTI_EMR1_EM18_Msk                          /*!< Event Mask on line 18 */

+#define EXTI_EMR1_EM20_Pos         (20U)

+#define EXTI_EMR1_EM20_Msk         (0x1UL << EXTI_EMR1_EM20_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR1_EM20             EXTI_EMR1_EM20_Msk                          /*!< Event Mask on line 20 */

+#define EXTI_EMR1_EM21_Pos         (21U)

+#define EXTI_EMR1_EM21_Msk         (0x1UL << EXTI_EMR1_EM21_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR1_EM21             EXTI_EMR1_EM21_Msk                          /*!< Event Mask on line 21 */

+#define EXTI_EMR1_EM22_Pos         (22U)

+#define EXTI_EMR1_EM22_Msk         (0x1UL << EXTI_EMR1_EM22_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR1_EM22             EXTI_EMR1_EM22_Msk                          /*!< Event Mask on line 22 */

+#define EXTI_EMR1_EM23_Pos         (23U)

+#define EXTI_EMR1_EM23_Msk         (0x1UL << EXTI_EMR1_EM23_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR1_EM23             EXTI_EMR1_EM23_Msk                          /*!< Event Mask on line 23 */

+#define EXTI_EMR1_EM24_Pos         (24U)

+#define EXTI_EMR1_EM24_Msk         (0x1UL << EXTI_EMR1_EM24_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR1_EM24             EXTI_EMR1_EM24_Msk                          /*!< Event Mask on line 24 */

+#define EXTI_EMR1_EM25_Pos         (25U)

+#define EXTI_EMR1_EM25_Msk         (0x1UL << EXTI_EMR1_EM25_Pos)               /*!< 0x02000000 */

+#define EXTI_EMR1_EM25             EXTI_EMR1_EM25_Msk                          /*!< Event Mask on line 25 */

+#define EXTI_EMR1_EM26_Pos         (26U)

+#define EXTI_EMR1_EM26_Msk         (0x1UL << EXTI_EMR1_EM26_Pos)               /*!< 0x04000000 */

+#define EXTI_EMR1_EM26             EXTI_EMR1_EM26_Msk                          /*!< Event Mask on line 26 */

+#define EXTI_EMR1_EM27_Pos         (27U)

+#define EXTI_EMR1_EM27_Msk         (0x1UL << EXTI_EMR1_EM27_Pos)               /*!< 0x08000000 */

+#define EXTI_EMR1_EM27             EXTI_EMR1_EM27_Msk                          /*!< Event Mask on line 27 */

+#define EXTI_EMR1_EM28_Pos         (28U)

+#define EXTI_EMR1_EM28_Msk         (0x1UL << EXTI_EMR1_EM28_Pos)               /*!< 0x10000000 */

+#define EXTI_EMR1_EM28             EXTI_EMR1_EM28_Msk                          /*!< Event Mask on line 28 */

+#define EXTI_EMR1_EM29_Pos         (29U)

+#define EXTI_EMR1_EM29_Msk         (0x1UL << EXTI_EMR1_EM29_Pos)               /*!< 0x20000000 */

+#define EXTI_EMR1_EM29             EXTI_EMR1_EM29_Msk                          /*!< Event Mask on line 29 */

+#define EXTI_EMR1_EM30_Pos         (30U)

+#define EXTI_EMR1_EM30_Msk         (0x1UL << EXTI_EMR1_EM30_Pos)               /*!< 0x40000000 */

+#define EXTI_EMR1_EM30             EXTI_EMR1_EM30_Msk                          /*!< Event Mask on line 30 */

+#define EXTI_EMR1_EM31_Pos         (31U)

+#define EXTI_EMR1_EM31_Msk         (0x1UL << EXTI_EMR1_EM31_Pos)               /*!< 0x80000000 */

+#define EXTI_EMR1_EM31             EXTI_EMR1_EM31_Msk                          /*!< Event Mask on line 31 */

+

+/*******************  Bit definition for EXTI_PR1 register  ********************/

+#define EXTI_PR1_PR_Pos            (0U)

+#define EXTI_PR1_PR_Msk            (0x3FFFFFUL << EXTI_PR1_PR_Pos)             /*!< 0x003FFFFF */

+#define EXTI_PR1_PR                EXTI_PR1_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR1_PR0_Pos           (0U)

+#define EXTI_PR1_PR0_Msk           (0x1UL << EXTI_PR1_PR0_Pos)                 /*!< 0x00000001 */

+#define EXTI_PR1_PR0               EXTI_PR1_PR0_Msk                            /*!< Pending bit for line 0 */

+#define EXTI_PR1_PR1_Pos           (1U)

+#define EXTI_PR1_PR1_Msk           (0x1UL << EXTI_PR1_PR1_Pos)                 /*!< 0x00000002 */

+#define EXTI_PR1_PR1               EXTI_PR1_PR1_Msk                            /*!< Pending bit for line 1 */

+#define EXTI_PR1_PR2_Pos           (2U)

+#define EXTI_PR1_PR2_Msk           (0x1UL << EXTI_PR1_PR2_Pos)                 /*!< 0x00000004 */

+#define EXTI_PR1_PR2               EXTI_PR1_PR2_Msk                            /*!< Pending bit for line 2 */

+#define EXTI_PR1_PR3_Pos           (3U)

+#define EXTI_PR1_PR3_Msk           (0x1UL << EXTI_PR1_PR3_Pos)                 /*!< 0x00000008 */

+#define EXTI_PR1_PR3               EXTI_PR1_PR3_Msk                            /*!< Pending bit for line 3 */

+#define EXTI_PR1_PR4_Pos           (4U)

+#define EXTI_PR1_PR4_Msk           (0x1UL << EXTI_PR1_PR4_Pos)                 /*!< 0x00000010 */

+#define EXTI_PR1_PR4               EXTI_PR1_PR4_Msk                            /*!< Pending bit for line 4 */

+#define EXTI_PR1_PR5_Pos           (5U)

+#define EXTI_PR1_PR5_Msk           (0x1UL << EXTI_PR1_PR5_Pos)                 /*!< 0x00000020 */

+#define EXTI_PR1_PR5               EXTI_PR1_PR5_Msk                            /*!< Pending bit for line 5 */

+#define EXTI_PR1_PR6_Pos           (6U)

+#define EXTI_PR1_PR6_Msk           (0x1UL << EXTI_PR1_PR6_Pos)                 /*!< 0x00000040 */

+#define EXTI_PR1_PR6               EXTI_PR1_PR6_Msk                            /*!< Pending bit for line 6 */

+#define EXTI_PR1_PR7_Pos           (7U)

+#define EXTI_PR1_PR7_Msk           (0x1UL << EXTI_PR1_PR7_Pos)                 /*!< 0x00000080 */

+#define EXTI_PR1_PR7               EXTI_PR1_PR7_Msk                            /*!< Pending bit for line 7 */

+#define EXTI_PR1_PR8_Pos           (8U)

+#define EXTI_PR1_PR8_Msk           (0x1UL << EXTI_PR1_PR8_Pos)                 /*!< 0x00000100 */

+#define EXTI_PR1_PR8               EXTI_PR1_PR8_Msk                            /*!< Pending bit for line 8 */

+#define EXTI_PR1_PR9_Pos           (9U)

+#define EXTI_PR1_PR9_Msk           (0x1UL << EXTI_PR1_PR9_Pos)                 /*!< 0x00000200 */

+#define EXTI_PR1_PR9               EXTI_PR1_PR9_Msk                            /*!< Pending bit for line 9 */

+#define EXTI_PR1_PR10_Pos          (10U)

+#define EXTI_PR1_PR10_Msk          (0x1UL << EXTI_PR1_PR10_Pos)                /*!< 0x00000400 */

+#define EXTI_PR1_PR10              EXTI_PR1_PR10_Msk                           /*!< Pending bit for line 10 */

+#define EXTI_PR1_PR11_Pos          (11U)

+#define EXTI_PR1_PR11_Msk          (0x1UL << EXTI_PR1_PR11_Pos)                /*!< 0x00000800 */

+#define EXTI_PR1_PR11              EXTI_PR1_PR11_Msk                           /*!< Pending bit for line 11 */

+#define EXTI_PR1_PR12_Pos          (12U)

+#define EXTI_PR1_PR12_Msk          (0x1UL << EXTI_PR1_PR12_Pos)                /*!< 0x00001000 */

+#define EXTI_PR1_PR12              EXTI_PR1_PR12_Msk                           /*!< Pending bit for line 12 */

+#define EXTI_PR1_PR13_Pos          (13U)

+#define EXTI_PR1_PR13_Msk          (0x1UL << EXTI_PR1_PR13_Pos)                /*!< 0x00002000 */

+#define EXTI_PR1_PR13              EXTI_PR1_PR13_Msk                           /*!< Pending bit for line 13 */

+#define EXTI_PR1_PR14_Pos          (14U)

+#define EXTI_PR1_PR14_Msk          (0x1UL << EXTI_PR1_PR14_Pos)                /*!< 0x00004000 */

+#define EXTI_PR1_PR14              EXTI_PR1_PR14_Msk                           /*!< Pending bit for line 14 */

+#define EXTI_PR1_PR15_Pos          (15U)

+#define EXTI_PR1_PR15_Msk          (0x1UL << EXTI_PR1_PR15_Pos)                /*!< 0x00008000 */

+#define EXTI_PR1_PR15              EXTI_PR1_PR15_Msk                           /*!< Pending bit for line 15 */

+#define EXTI_PR1_PR16_Pos          (16U)

+#define EXTI_PR1_PR16_Msk          (0x1UL << EXTI_PR1_PR16_Pos)                /*!< 0x00010000 */

+#define EXTI_PR1_PR16              EXTI_PR1_PR16_Msk                           /*!< Pending bit for line 16 */

+#define EXTI_PR1_PR17_Pos          (17U)

+#define EXTI_PR1_PR17_Msk          (0x1UL << EXTI_PR1_PR17_Pos)                /*!< 0x00020000 */

+#define EXTI_PR1_PR17              EXTI_PR1_PR17_Msk                           /*!< Pending bit for line 17 */

+#define EXTI_PR1_PR18_Pos          (18U)

+#define EXTI_PR1_PR18_Msk          (0x1UL << EXTI_PR1_PR18_Pos)                /*!< 0x00040000 */

+#define EXTI_PR1_PR18              EXTI_PR1_PR18_Msk                           /*!< Pending bit for line 18 */

+#define EXTI_PR1_PR19_Pos          (19U)

+#define EXTI_PR1_PR19_Msk          (0x1UL << EXTI_PR1_PR19_Pos)                /*!< 0x00080000 */

+#define EXTI_PR1_PR19              EXTI_PR1_PR19_Msk                           /*!< Pending bit for line 19 */

+#define EXTI_PR1_PR20_Pos          (20U)

+#define EXTI_PR1_PR20_Msk          (0x1UL << EXTI_PR1_PR20_Pos)                /*!< 0x00100000 */

+#define EXTI_PR1_PR20              EXTI_PR1_PR20_Msk                           /*!< Pending bit for line 20 */

+#define EXTI_PR1_PR21_Pos          (21U)

+#define EXTI_PR1_PR21_Msk          (0x1UL << EXTI_PR1_PR21_Pos)                /*!< 0x00200000 */

+#define EXTI_PR1_PR21              EXTI_PR1_PR21_Msk                           /*!< Pending bit for line 21 */

+

+/*******************  Bit definition for EXTI_IMR2 register  *******************/

+#define EXTI_IMR2_IM_Pos           (0U)

+#define EXTI_IMR2_IM_Msk           (0xFFFFDFFFUL << EXTI_IMR2_IM_Pos)          /*!< 0xFFFFDFFF */

+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            /*!< Interrupt Mask */

+#define EXTI_IMR2_IM32_Pos         (0U)

+#define EXTI_IMR2_IM32_Msk         (0x1UL << EXTI_IMR2_IM32_Pos)               /*!< 0x00000001 */

+#define EXTI_IMR2_IM32             EXTI_IMR2_IM32_Msk                          /*!< Interrupt Mask on line 32 */

+#define EXTI_IMR2_IM33_Pos         (1U)

+#define EXTI_IMR2_IM33_Msk         (0x1UL << EXTI_IMR2_IM33_Pos)               /*!< 0x00000002 */

+#define EXTI_IMR2_IM33             EXTI_IMR2_IM33_Msk                          /*!< Interrupt Mask on line 33 */

+#define EXTI_IMR2_IM34_Pos         (2U)

+#define EXTI_IMR2_IM34_Msk         (0x1UL << EXTI_IMR2_IM34_Pos)               /*!< 0x00000004 */

+#define EXTI_IMR2_IM34             EXTI_IMR2_IM34_Msk                          /*!< Interrupt Mask on line 34 */

+#define EXTI_IMR2_IM35_Pos         (3U)

+#define EXTI_IMR2_IM35_Msk         (0x1UL << EXTI_IMR2_IM35_Pos)               /*!< 0x00000008 */

+#define EXTI_IMR2_IM35             EXTI_IMR2_IM35_Msk                          /*!< Interrupt Mask on line 35 */

+#define EXTI_IMR2_IM36_Pos         (4U)

+#define EXTI_IMR2_IM36_Msk         (0x1UL << EXTI_IMR2_IM36_Pos)               /*!< 0x00000010 */

+#define EXTI_IMR2_IM36             EXTI_IMR2_IM36_Msk                          /*!< Interrupt Mask on line 36 */

+#define EXTI_IMR2_IM37_Pos         (5U)

+#define EXTI_IMR2_IM37_Msk         (0x1UL << EXTI_IMR2_IM37_Pos)               /*!< 0x00000020 */

+#define EXTI_IMR2_IM37             EXTI_IMR2_IM37_Msk                          /*!< Interrupt Mask on line 37 */

+#define EXTI_IMR2_IM38_Pos         (6U)

+#define EXTI_IMR2_IM38_Msk         (0x1UL << EXTI_IMR2_IM38_Pos)               /*!< 0x00000040 */

+#define EXTI_IMR2_IM38             EXTI_IMR2_IM38_Msk                          /*!< Interrupt Mask on line 38 */

+#define EXTI_IMR2_IM39_Pos         (7U)

+#define EXTI_IMR2_IM39_Msk         (0x1UL << EXTI_IMR2_IM39_Pos)               /*!< 0x00000080 */

+#define EXTI_IMR2_IM39             EXTI_IMR2_IM39_Msk                          /*!< Interrupt Mask on line 39 */

+#define EXTI_IMR2_IM40_Pos         (8U)

+#define EXTI_IMR2_IM40_Msk         (0x1UL << EXTI_IMR2_IM40_Pos)               /*!< 0x00000100 */

+#define EXTI_IMR2_IM40             EXTI_IMR2_IM40_Msk                          /*!< Interrupt Mask on line 40 */

+#define EXTI_IMR2_IM41_Pos         (9U)

+#define EXTI_IMR2_IM41_Msk         (0x1UL << EXTI_IMR2_IM41_Pos)               /*!< 0x00000200 */

+#define EXTI_IMR2_IM41             EXTI_IMR2_IM41_Msk                          /*!< Interrupt Mask on line 41 */

+#define EXTI_IMR2_IM42_Pos         (10U)

+#define EXTI_IMR2_IM42_Msk         (0x1UL << EXTI_IMR2_IM42_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR2_IM42             EXTI_IMR2_IM42_Msk                          /*!< Interrupt Mask on line 42 */

+#define EXTI_IMR2_IM43_Pos         (11U)

+#define EXTI_IMR2_IM43_Msk         (0x1UL << EXTI_IMR2_IM43_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR2_IM43             EXTI_IMR2_IM43_Msk                          /*!< Interrupt Mask on line 43 */

+#define EXTI_IMR2_IM44_Pos         (12U)

+#define EXTI_IMR2_IM44_Msk         (0x1UL << EXTI_IMR2_IM44_Pos)               /*!< 0x00001000 */

+#define EXTI_IMR2_IM44             EXTI_IMR2_IM44_Msk                          /*!< Interrupt Mask on line 44 */

+#define EXTI_IMR2_IM46_Pos         (14U)

+#define EXTI_IMR2_IM46_Msk         (0x1UL << EXTI_IMR2_IM46_Pos)               /*!< 0x00004000 */

+#define EXTI_IMR2_IM46             EXTI_IMR2_IM46_Msk                          /*!< Interrupt Mask on line 46 */

+#define EXTI_IMR2_IM47_Pos         (15U)

+#define EXTI_IMR2_IM47_Msk         (0x1UL << EXTI_IMR2_IM47_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR2_IM47             EXTI_IMR2_IM47_Msk                          /*!< Interrupt Mask on line 47 */

+#define EXTI_IMR2_IM48_Pos         (16U)

+#define EXTI_IMR2_IM48_Msk         (0x1UL << EXTI_IMR2_IM48_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR2_IM48             EXTI_IMR2_IM48_Msk                          /*!< Interrupt Mask on line 48 */

+#define EXTI_IMR2_IM49_Pos         (17U)

+#define EXTI_IMR2_IM49_Msk         (0x1UL << EXTI_IMR2_IM49_Pos)               /*!< 0x00020000 */

+#define EXTI_IMR2_IM49             EXTI_IMR2_IM49_Msk                          /*!< Interrupt Mask on line 49 */

+#define EXTI_IMR2_IM50_Pos         (18U)

+#define EXTI_IMR2_IM50_Msk         (0x1UL << EXTI_IMR2_IM50_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR2_IM50             EXTI_IMR2_IM50_Msk                          /*!< Interrupt Mask on line 50 */

+#define EXTI_IMR2_IM51_Pos         (19U)

+#define EXTI_IMR2_IM51_Msk         (0x1UL << EXTI_IMR2_IM51_Pos)               /*!< 0x00080000 */

+#define EXTI_IMR2_IM51             EXTI_IMR2_IM51_Msk                          /*!< Interrupt Mask on line 51 */

+#define EXTI_IMR2_IM52_Pos         (20U)

+#define EXTI_IMR2_IM52_Msk         (0x1UL << EXTI_IMR2_IM52_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR2_IM52             EXTI_IMR2_IM52_Msk                          /*!< Interrupt Mask on line 52 */

+#define EXTI_IMR2_IM53_Pos         (21U)

+#define EXTI_IMR2_IM53_Msk         (0x1UL << EXTI_IMR2_IM53_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR2_IM53             EXTI_IMR2_IM53_Msk                          /*!< Interrupt Mask on line 53 */

+#define EXTI_IMR2_IM54_Pos         (22U)

+#define EXTI_IMR2_IM54_Msk         (0x1UL << EXTI_IMR2_IM54_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR2_IM54             EXTI_IMR2_IM54_Msk                          /*!< Interrupt Mask on line 54 */

+#define EXTI_IMR2_IM55_Pos         (23U)

+#define EXTI_IMR2_IM55_Msk         (0x1UL << EXTI_IMR2_IM55_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR2_IM55             EXTI_IMR2_IM55_Msk                          /*!< Interrupt Mask on line 55 */

+#define EXTI_IMR2_IM56_Pos         (24U)

+#define EXTI_IMR2_IM56_Msk         (0x1UL << EXTI_IMR2_IM56_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR2_IM56             EXTI_IMR2_IM56_Msk                          /*!< Interrupt Mask on line 56 */

+#define EXTI_IMR2_IM57_Pos         (25U)

+#define EXTI_IMR2_IM57_Msk         (0x1UL << EXTI_IMR2_IM57_Pos)               /*!< 0x02000000 */

+#define EXTI_IMR2_IM57             EXTI_IMR2_IM57_Msk                          /*!< Interrupt Mask on line 57 */

+#define EXTI_IMR2_IM58_Pos         (26U)

+#define EXTI_IMR2_IM58_Msk         (0x1UL << EXTI_IMR2_IM58_Pos)               /*!< 0x04000000 */

+#define EXTI_IMR2_IM58             EXTI_IMR2_IM58_Msk                          /*!< Interrupt Mask on line 58 */

+#define EXTI_IMR2_IM59_Pos         (27U)

+#define EXTI_IMR2_IM59_Msk         (0x1UL << EXTI_IMR2_IM59_Pos)               /*!< 0x08000000 */

+#define EXTI_IMR2_IM59             EXTI_IMR2_IM59_Msk                          /*!< Interrupt Mask on line 59 */

+#define EXTI_IMR2_IM60_Pos         (28U)

+#define EXTI_IMR2_IM60_Msk         (0x1UL << EXTI_IMR2_IM60_Pos)               /*!< 0x10000000 */

+#define EXTI_IMR2_IM60             EXTI_IMR2_IM60_Msk                          /*!< Interrupt Mask on line 60 */

+#define EXTI_IMR2_IM61_Pos         (29U)

+#define EXTI_IMR2_IM61_Msk         (0x1UL << EXTI_IMR2_IM61_Pos)               /*!< 0x20000000 */

+#define EXTI_IMR2_IM61             EXTI_IMR2_IM61_Msk                          /*!< Interrupt Mask on line 61 */

+#define EXTI_IMR2_IM62_Pos         (30U)

+#define EXTI_IMR2_IM62_Msk         (0x1UL << EXTI_IMR2_IM62_Pos)               /*!< 0x40000000 */

+#define EXTI_IMR2_IM62             EXTI_IMR2_IM62_Msk                          /*!< Interrupt Mask on line 62 */

+#define EXTI_IMR2_IM63_Pos         (31U)

+#define EXTI_IMR2_IM63_Msk         (0x1UL << EXTI_IMR2_IM63_Pos)               /*!< 0x80000000 */

+#define EXTI_IMR2_IM63             EXTI_IMR2_IM63_Msk                          /*!< Interrupt Mask on line 63 */

+

+/*******************  Bit definition for EXTI_EMR2 register  *******************/

+#define EXTI_EMR2_EM_Pos           (0U)

+#define EXTI_EMR2_EM_Msk           (0xFFFFDFFFUL << EXTI_EMR2_EM_Pos)          /*!< 0xFFFFDFFF */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            /*!< Event Mask */

+#define EXTI_EMR2_EM32_Pos         (0U)

+#define EXTI_EMR2_EM32_Msk         (0x1UL << EXTI_EMR2_EM32_Pos)               /*!< 0x00000001 */

+#define EXTI_EMR2_EM32             EXTI_EMR2_EM32_Msk                          /*!< Event Mask on line 32*/

+#define EXTI_EMR2_EM33_Pos         (1U)

+#define EXTI_EMR2_EM33_Msk         (0x1UL << EXTI_EMR2_EM33_Pos)               /*!< 0x00000002 */

+#define EXTI_EMR2_EM33             EXTI_EMR2_EM33_Msk                          /*!< Event Mask on line 33*/

+#define EXTI_EMR2_EM34_Pos         (2U)

+#define EXTI_EMR2_EM34_Msk         (0x1UL << EXTI_EMR2_EM34_Pos)               /*!< 0x00000004 */

+#define EXTI_EMR2_EM34             EXTI_EMR2_EM34_Msk                          /*!< Event Mask on line 34*/

+#define EXTI_EMR2_EM35_Pos         (3U)

+#define EXTI_EMR2_EM35_Msk         (0x1UL << EXTI_EMR2_EM35_Pos)               /*!< 0x00000008 */

+#define EXTI_EMR2_EM35             EXTI_EMR2_EM35_Msk                          /*!< Event Mask on line 35*/

+#define EXTI_EMR2_EM36_Pos         (4U)

+#define EXTI_EMR2_EM36_Msk         (0x1UL << EXTI_EMR2_EM36_Pos)               /*!< 0x00000010 */

+#define EXTI_EMR2_EM36             EXTI_EMR2_EM36_Msk                          /*!< Event Mask on line 36*/

+#define EXTI_EMR2_EM37_Pos         (5U)

+#define EXTI_EMR2_EM37_Msk         (0x1UL << EXTI_EMR2_EM37_Pos)               /*!< 0x00000020 */

+#define EXTI_EMR2_EM37             EXTI_EMR2_EM37_Msk                          /*!< Event Mask on line 37*/

+#define EXTI_EMR2_EM38_Pos         (6U)

+#define EXTI_EMR2_EM38_Msk         (0x1UL << EXTI_EMR2_EM38_Pos)               /*!< 0x00000040 */

+#define EXTI_EMR2_EM38             EXTI_EMR2_EM38_Msk                          /*!< Event Mask on line 38*/

+#define EXTI_EMR2_EM39_Pos         (7U)

+#define EXTI_EMR2_EM39_Msk         (0x1UL << EXTI_EMR2_EM39_Pos)               /*!< 0x00000080 */

+#define EXTI_EMR2_EM39             EXTI_EMR2_EM39_Msk                          /*!< Event Mask on line 39*/

+#define EXTI_EMR2_EM40_Pos         (8U)

+#define EXTI_EMR2_EM40_Msk         (0x1UL << EXTI_EMR2_EM40_Pos)               /*!< 0x00000100 */

+#define EXTI_EMR2_EM40             EXTI_EMR2_EM40_Msk                          /*!< Event Mask on line 40*/

+#define EXTI_EMR2_EM41_Pos         (9U)

+#define EXTI_EMR2_EM41_Msk         (0x1UL << EXTI_EMR2_EM41_Pos)               /*!< 0x00000200 */

+#define EXTI_EMR2_EM41             EXTI_EMR2_EM41_Msk                          /*!< Event Mask on line 41*/

+#define EXTI_EMR2_EM42_Pos         (10U)

+#define EXTI_EMR2_EM42_Msk         (0x1UL << EXTI_EMR2_EM42_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR2_EM42             EXTI_EMR2_EM42_Msk                          /*!< Event Mask on line 42 */

+#define EXTI_EMR2_EM43_Pos         (11U)

+#define EXTI_EMR2_EM43_Msk         (0x1UL << EXTI_EMR2_EM43_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR2_EM43             EXTI_EMR2_EM43_Msk                          /*!< Event Mask on line 43 */

+#define EXTI_EMR2_EM44_Pos         (12U)

+#define EXTI_EMR2_EM44_Msk         (0x1UL << EXTI_EMR2_EM44_Pos)               /*!< 0x00001000 */

+#define EXTI_EMR2_EM44             EXTI_EMR2_EM44_Msk                          /*!< Event Mask on line 44 */

+#define EXTI_EMR2_EM46_Pos         (14U)

+#define EXTI_EMR2_EM46_Msk         (0x1UL << EXTI_EMR2_EM46_Pos)               /*!< 0x00004000 */

+#define EXTI_EMR2_EM46             EXTI_EMR2_EM46_Msk                          /*!< Event Mask on line 46 */

+#define EXTI_EMR2_EM47_Pos         (15U)

+#define EXTI_EMR2_EM47_Msk         (0x1UL << EXTI_EMR2_EM47_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR2_EM47             EXTI_EMR2_EM47_Msk                          /*!< Event Mask on line 47 */

+#define EXTI_EMR2_EM48_Pos         (16U)

+#define EXTI_EMR2_EM48_Msk         (0x1UL << EXTI_EMR2_EM48_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR2_EM48             EXTI_EMR2_EM48_Msk                          /*!< Event Mask on line 48 */

+#define EXTI_EMR2_EM49_Pos         (17U)

+#define EXTI_EMR2_EM49_Msk         (0x1UL << EXTI_EMR2_EM49_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR2_EM49             EXTI_EMR2_EM49_Msk                          /*!< Event Mask on line 49 */

+#define EXTI_EMR2_EM50_Pos         (18U)

+#define EXTI_EMR2_EM50_Msk         (0x1UL << EXTI_EMR2_EM50_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR2_EM50             EXTI_EMR2_EM50_Msk                          /*!< Event Mask on line 50 */

+#define EXTI_EMR2_EM51_Pos         (19U)

+#define EXTI_EMR2_EM51_Msk         (0x1UL << EXTI_EMR2_EM51_Pos)               /*!< 0x00080000 */

+#define EXTI_EMR2_EM51             EXTI_EMR2_EM51_Msk                          /*!< Event Mask on line 51 */

+#define EXTI_EMR2_EM52_Pos         (20U)

+#define EXTI_EMR2_EM52_Msk         (0x1UL << EXTI_EMR2_EM52_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR2_EM52             EXTI_EMR2_EM52_Msk                          /*!< Event Mask on line 52 */

+#define EXTI_EMR2_EM53_Pos         (21U)

+#define EXTI_EMR2_EM53_Msk         (0x1UL << EXTI_EMR2_EM53_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR2_EM53             EXTI_EMR2_EM53_Msk                          /*!< Event Mask on line 53 */

+#define EXTI_EMR2_EM54_Pos         (22U)

+#define EXTI_EMR2_EM54_Msk         (0x1UL << EXTI_EMR2_EM54_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR2_EM54             EXTI_EMR2_EM54_Msk                          /*!< Event Mask on line 54 */

+#define EXTI_EMR2_EM55_Pos         (23U)

+#define EXTI_EMR2_EM55_Msk         (0x1UL << EXTI_EMR2_EM55_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR2_EM55             EXTI_EMR2_EM55_Msk                          /*!< Event Mask on line 55 */

+#define EXTI_EMR2_EM56_Pos         (24U)

+#define EXTI_EMR2_EM56_Msk         (0x1UL << EXTI_EMR2_EM56_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR2_EM56             EXTI_EMR2_EM56_Msk                          /*!< Event Mask on line 56 */

+#define EXTI_EMR2_EM57_Pos         (25U)

+#define EXTI_EMR2_EM57_Msk         (0x1UL << EXTI_EMR2_EM57_Pos)               /*!< 0x02000000 */

+#define EXTI_EMR2_EM57             EXTI_EMR2_EM57_Msk                          /*!< Event Mask on line 57 */

+#define EXTI_EMR2_EM58_Pos         (26U)

+#define EXTI_EMR2_EM58_Msk         (0x1UL << EXTI_EMR2_EM58_Pos)               /*!< 0x04000000 */

+#define EXTI_EMR2_EM58             EXTI_EMR2_EM58_Msk                          /*!< Event Mask on line 58 */

+#define EXTI_EMR2_EM59_Pos         (27U)

+#define EXTI_EMR2_EM59_Msk         (0x1UL << EXTI_EMR2_EM59_Pos)               /*!< 0x08000000 */

+#define EXTI_EMR2_EM59             EXTI_EMR2_EM59_Msk                          /*!< Event Mask on line 59 */

+#define EXTI_EMR2_EM60_Pos         (28U)

+#define EXTI_EMR2_EM60_Msk         (0x1UL << EXTI_EMR2_EM60_Pos)               /*!< 0x10000000 */

+#define EXTI_EMR2_EM60             EXTI_EMR2_EM60_Msk                          /*!< Event Mask on line 60 */

+#define EXTI_EMR2_EM61_Pos         (29U)

+#define EXTI_EMR2_EM61_Msk         (0x1UL << EXTI_EMR2_EM61_Pos)               /*!< 0x20000000 */

+#define EXTI_EMR2_EM61             EXTI_EMR2_EM61_Msk                          /*!< Event Mask on line 61 */

+#define EXTI_EMR2_EM62_Pos         (30U)

+#define EXTI_EMR2_EM62_Msk         (0x1UL << EXTI_EMR2_EM62_Pos)               /*!< 0x40000000 */

+#define EXTI_EMR2_EM62             EXTI_EMR2_EM62_Msk                          /*!< Event Mask on line 62 */

+#define EXTI_EMR2_EM63_Pos         (31U)

+#define EXTI_EMR2_EM63_Msk         (0x1UL << EXTI_EMR2_EM63_Pos)               /*!< 0x80000000 */

+#define EXTI_EMR2_EM63             EXTI_EMR2_EM63_Msk                          /*!< Event Mask on line 63 */

+

+/*******************  Bit definition for EXTI_PR2 register  ********************/

+#define EXTI_PR2_PR_Pos            (17U)

+#define EXTI_PR2_PR_Msk            (0x5UL << EXTI_PR2_PR_Pos)                  /*!< 0x000A0000 */

+#define EXTI_PR2_PR                EXTI_PR2_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR2_PR49_Pos          (17U)

+#define EXTI_PR2_PR49_Msk          (0x1UL << EXTI_PR2_PR49_Pos)                /*!< 0x00020000 */

+#define EXTI_PR2_PR49              EXTI_PR2_PR49_Msk                           /*!< Pending bit for line 49 */

+#define EXTI_PR2_PR51_Pos          (19U)

+#define EXTI_PR2_PR51_Msk          (0x1UL << EXTI_PR2_PR51_Pos)                /*!< 0x00080000 */

+#define EXTI_PR2_PR51              EXTI_PR2_PR51_Msk                           /*!< Pending bit for line 51 */

+

+/*******************  Bit definition for EXTI_IMR3 register  *******************/

+#define EXTI_IMR3_IM_Pos           (0U)

+#define EXTI_IMR3_IM_Msk           (0x00F5FFFFUL << EXTI_IMR3_IM_Pos)          /*!< 0x00F5FFFF */

+#define EXTI_IMR3_IM               EXTI_IMR3_IM_Msk                            /*!< Interrupt Mask */

+#define EXTI_IMR3_IM64_Pos         (0U)

+#define EXTI_IMR3_IM64_Msk         (0x1UL << EXTI_IMR3_IM64_Pos)               /*!< 0x00000001 */

+#define EXTI_IMR3_IM64             EXTI_IMR3_IM64_Msk                          /*!< Interrupt Mask on line 64 */

+#define EXTI_IMR3_IM65_Pos         (1U)

+#define EXTI_IMR3_IM65_Msk         (0x1UL << EXTI_IMR3_IM65_Pos)               /*!< 0x00000002 */

+#define EXTI_IMR3_IM65             EXTI_IMR3_IM65_Msk                          /*!< Interrupt Mask on line 65 */

+#define EXTI_IMR3_IM66_Pos         (2U)

+#define EXTI_IMR3_IM66_Msk         (0x1UL << EXTI_IMR3_IM66_Pos)               /*!< 0x00000004 */

+#define EXTI_IMR3_IM66             EXTI_IMR3_IM66_Msk                          /*!< Interrupt Mask on line 66 */

+#define EXTI_IMR3_IM67_Pos         (3U)

+#define EXTI_IMR3_IM67_Msk         (0x1UL << EXTI_IMR3_IM67_Pos)               /*!< 0x00000008 */

+#define EXTI_IMR3_IM67             EXTI_IMR3_IM67_Msk                          /*!< Interrupt Mask on line 67 */

+#define EXTI_IMR3_IM68_Pos         (4U)

+#define EXTI_IMR3_IM68_Msk         (0x1UL << EXTI_IMR3_IM68_Pos)               /*!< 0x00000010 */

+#define EXTI_IMR3_IM68             EXTI_IMR3_IM68_Msk                          /*!< Interrupt Mask on line 68 */

+#define EXTI_IMR3_IM69_Pos         (5U)

+#define EXTI_IMR3_IM69_Msk         (0x1UL << EXTI_IMR3_IM69_Pos)               /*!< 0x00000020 */

+#define EXTI_IMR3_IM69             EXTI_IMR3_IM69_Msk                          /*!< Interrupt Mask on line 69 */

+#define EXTI_IMR3_IM70_Pos         (6U)

+#define EXTI_IMR3_IM70_Msk         (0x1UL << EXTI_IMR3_IM70_Pos)               /*!< 0x00000040 */

+#define EXTI_IMR3_IM70             EXTI_IMR3_IM70_Msk                          /*!< Interrupt Mask on line 70 */

+#define EXTI_IMR3_IM71_Pos         (7U)

+#define EXTI_IMR3_IM71_Msk         (0x1UL << EXTI_IMR3_IM71_Pos)               /*!< 0x00000080 */

+#define EXTI_IMR3_IM71             EXTI_IMR3_IM71_Msk                          /*!< Interrupt Mask on line 71 */

+#define EXTI_IMR3_IM72_Pos         (8U)

+#define EXTI_IMR3_IM72_Msk         (0x1UL << EXTI_IMR3_IM72_Pos)               /*!< 0x00000100 */

+#define EXTI_IMR3_IM72             EXTI_IMR3_IM72_Msk                          /*!< Interrupt Mask on line 72 */

+#define EXTI_IMR3_IM73_Pos         (9U)

+#define EXTI_IMR3_IM73_Msk         (0x1UL << EXTI_IMR3_IM73_Pos)               /*!< 0x00000200 */

+#define EXTI_IMR3_IM73             EXTI_IMR3_IM73_Msk                          /*!< Interrupt Mask on line 73 */

+#define EXTI_IMR3_IM74_Pos         (10U)

+#define EXTI_IMR3_IM74_Msk         (0x1UL << EXTI_IMR3_IM74_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR3_IM74             EXTI_IMR3_IM74_Msk                          /*!< Interrupt Mask on line 74 */

+#define EXTI_IMR3_IM75_Pos         (11U)

+#define EXTI_IMR3_IM75_Msk         (0x1UL << EXTI_IMR3_IM75_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR3_IM75             EXTI_IMR3_IM75_Msk                          /*!< Interrupt Mask on line 75 */

+#define EXTI_IMR3_IM76_Pos         (12U)

+#define EXTI_IMR3_IM76_Msk         (0x1UL << EXTI_IMR3_IM76_Pos)               /*!< 0x00001000 */

+#define EXTI_IMR3_IM76             EXTI_IMR3_IM76_Msk                          /*!< Interrupt Mask on line 76 */

+#define EXTI_IMR3_IM77_Pos         (13U)

+#define EXTI_IMR3_IM77_Msk         (0x1UL << EXTI_IMR3_IM77_Pos)               /*!< 0x00002000 */

+#define EXTI_IMR3_IM77             EXTI_IMR3_IM77_Msk                          /*!< Interrupt Mask on line 77 */

+#define EXTI_IMR3_IM78_Pos         (14U)

+#define EXTI_IMR3_IM78_Msk         (0x1UL << EXTI_IMR3_IM78_Pos)               /*!< 0x00004000 */

+#define EXTI_IMR3_IM78             EXTI_IMR3_IM78_Msk                          /*!< Interrupt Mask on line 78 */

+#define EXTI_IMR3_IM79_Pos         (15U)

+#define EXTI_IMR3_IM79_Msk         (0x1UL << EXTI_IMR3_IM79_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR3_IM79             EXTI_IMR3_IM79_Msk                          /*!< Interrupt Mask on line 79 */

+#define EXTI_IMR3_IM80_Pos         (16U)

+#define EXTI_IMR3_IM80_Msk         (0x1UL << EXTI_IMR3_IM80_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR3_IM80             EXTI_IMR3_IM80_Msk                          /*!< Interrupt Mask on line 80 */

+#define EXTI_IMR3_IM82_Pos         (18U)

+#define EXTI_IMR3_IM82_Msk         (0x1UL << EXTI_IMR3_IM82_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR3_IM82             EXTI_IMR3_IM82_Msk                          /*!< Interrupt Mask on line 82 */

+#define EXTI_IMR3_IM84_Pos         (20U)

+#define EXTI_IMR3_IM84_Msk         (0x1UL << EXTI_IMR3_IM84_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR3_IM84             EXTI_IMR3_IM84_Msk                          /*!< Interrupt Mask on line 84 */

+#define EXTI_IMR3_IM85_Pos         (21U)

+#define EXTI_IMR3_IM85_Msk         (0x1UL << EXTI_IMR3_IM85_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR3_IM85             EXTI_IMR3_IM85_Msk                          /*!< Interrupt Mask on line 85 */

+#define EXTI_IMR3_IM86_Pos         (22U)

+#define EXTI_IMR3_IM86_Msk         (0x1UL << EXTI_IMR3_IM86_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR3_IM86             EXTI_IMR3_IM86_Msk                          /*!< Interrupt Mask on line 86 */

+#define EXTI_IMR3_IM87_Pos         (23U)

+#define EXTI_IMR3_IM87_Msk         (0x1UL << EXTI_IMR3_IM87_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR3_IM87             EXTI_IMR3_IM87_Msk                          /*!< Interrupt Mask on line 87 */

+

+

+/*******************  Bit definition for EXTI_EMR3 register  *******************/

+#define EXTI_EMR3_EM_Pos           (0U)

+#define EXTI_EMR3_EM_Msk           (0x00F5FFFFUL << EXTI_EMR3_EM_Pos)          /*!< 0x00F5FFFF */

+#define EXTI_EMR3_EM               EXTI_EMR3_EM_Msk                            /*!< Event Mask           */

+#define EXTI_EMR3_EM64_Pos         (0U)

+#define EXTI_EMR3_EM64_Msk         (0x1UL << EXTI_EMR3_EM64_Pos)               /*!< 0x00000001 */

+#define EXTI_EMR3_EM64             EXTI_EMR3_EM64_Msk                          /*!< Event Mask on line 64*/

+#define EXTI_EMR3_EM65_Pos         (1U)

+#define EXTI_EMR3_EM65_Msk         (0x1UL << EXTI_EMR3_EM65_Pos)               /*!< 0x00000002 */

+#define EXTI_EMR3_EM65             EXTI_EMR3_EM65_Msk                          /*!< Event Mask on line 65*/

+#define EXTI_EMR3_EM66_Pos         (2U)

+#define EXTI_EMR3_EM66_Msk         (0x1UL << EXTI_EMR3_EM66_Pos)               /*!< 0x00000004 */

+#define EXTI_EMR3_EM66             EXTI_EMR3_EM66_Msk                          /*!< Event Mask on line 66*/

+#define EXTI_EMR3_EM67_Pos         (3U)

+#define EXTI_EMR3_EM67_Msk         (0x1UL << EXTI_EMR3_EM67_Pos)               /*!< 0x00000008 */

+#define EXTI_EMR3_EM67             EXTI_EMR3_EM67_Msk                          /*!< Event Mask on line 67*/

+#define EXTI_EMR3_EM68_Pos         (4U)

+#define EXTI_EMR3_EM68_Msk         (0x1UL << EXTI_EMR3_EM68_Pos)               /*!< 0x00000010 */

+#define EXTI_EMR3_EM68             EXTI_EMR3_EM68_Msk                          /*!< Event Mask on line 68*/

+#define EXTI_EMR3_EM69_Pos         (5U)

+#define EXTI_EMR3_EM69_Msk         (0x1UL << EXTI_EMR3_EM69_Pos)               /*!< 0x00000020 */

+#define EXTI_EMR3_EM69             EXTI_EMR3_EM69_Msk                          /*!< Event Mask on line 69*/

+#define EXTI_EMR3_EM70_Pos         (6U)

+#define EXTI_EMR3_EM70_Msk         (0x1UL << EXTI_EMR3_EM70_Pos)               /*!< 0x00000040 */

+#define EXTI_EMR3_EM70             EXTI_EMR3_EM70_Msk                          /*!< Event Mask on line 70*/

+#define EXTI_EMR3_EM71_Pos         (7U)

+#define EXTI_EMR3_EM71_Msk         (0x1UL << EXTI_EMR3_EM71_Pos)               /*!< 0x00000080 */

+#define EXTI_EMR3_EM71             EXTI_EMR3_EM71_Msk                          /*!< Event Mask on line 71*/

+#define EXTI_EMR3_EM72_Pos         (8U)

+#define EXTI_EMR3_EM72_Msk         (0x1UL << EXTI_EMR3_EM72_Pos)               /*!< 0x00000100 */

+#define EXTI_EMR3_EM72             EXTI_EMR3_EM72_Msk                          /*!< Event Mask on line 72*/

+#define EXTI_EMR3_EM73_Pos         (9U)

+#define EXTI_EMR3_EM73_Msk         (0x1UL << EXTI_EMR3_EM73_Pos)               /*!< 0x00000200 */

+#define EXTI_EMR3_EM73             EXTI_EMR3_EM73_Msk                          /*!< Event Mask on line 73*/

+#define EXTI_EMR3_EM74_Pos         (10U)

+#define EXTI_EMR3_EM74_Msk         (0x1UL << EXTI_EMR3_EM74_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR3_EM74             EXTI_EMR3_EM74_Msk                          /*!< Event Mask on line 74 */

+#define EXTI_EMR3_EM75_Pos         (11U)

+#define EXTI_EMR3_EM75_Msk         (0x1UL << EXTI_EMR3_EM75_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR3_EM75             EXTI_EMR3_EM75_Msk                          /*!< Event Mask on line 75 */

+#define EXTI_EMR3_EM76_Pos         (12U)

+#define EXTI_EMR3_EM76_Msk         (0x1UL << EXTI_EMR3_EM76_Pos)               /*!< 0x00001000 */

+#define EXTI_EMR3_EM76             EXTI_EMR3_EM76_Msk                          /*!< Event Mask on line 76 */

+#define EXTI_EMR3_EM77_Pos         (13U)

+#define EXTI_EMR3_EM77_Msk         (0x1UL << EXTI_EMR3_EM77_Pos)               /*!< 0x00002000 */

+#define EXTI_EMR3_EM77             EXTI_EMR3_EM77_Msk                          /*!< Event Mask on line 77 */

+#define EXTI_EMR3_EM78_Pos         (14U)

+#define EXTI_EMR3_EM78_Msk         (0x1UL << EXTI_EMR3_EM78_Pos)               /*!< 0x00004000 */

+#define EXTI_EMR3_EM78             EXTI_EMR3_EM78_Msk                          /*!< Event Mask on line 78 */

+#define EXTI_EMR3_EM79_Pos         (15U)

+#define EXTI_EMR3_EM79_Msk         (0x1UL << EXTI_EMR3_EM79_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR3_EM79             EXTI_EMR3_EM79_Msk                          /*!< Event Mask on line 79 */

+#define EXTI_EMR3_EM80_Pos         (16U)

+#define EXTI_EMR3_EM80_Msk         (0x1UL << EXTI_EMR3_EM80_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR3_EM80             EXTI_EMR3_EM80_Msk                          /*!< Event Mask on line 80 */

+#define EXTI_EMR3_EM81_Pos         (17U)

+#define EXTI_EMR3_EM81_Msk         (0x1UL << EXTI_EMR3_EM81_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR3_EM81             EXTI_EMR3_EM81_Msk                          /*!< Event Mask on line 81 */

+#define EXTI_EMR3_EM82_Pos         (18U)

+#define EXTI_EMR3_EM82_Msk         (0x1UL << EXTI_EMR3_EM82_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR3_EM82             EXTI_EMR3_EM82_Msk                          /*!< Event Mask on line 82 */

+#define EXTI_EMR3_EM84_Pos         (20U)

+#define EXTI_EMR3_EM84_Msk         (0x1UL << EXTI_EMR3_EM84_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR3_EM84             EXTI_EMR3_EM84_Msk                          /*!< Event Mask on line 84 */

+#define EXTI_EMR3_EM85_Pos         (21U)

+#define EXTI_EMR3_EM85_Msk         (0x1UL << EXTI_EMR3_EM85_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR3_EM85             EXTI_EMR3_EM85_Msk                          /*!< Event Mask on line 85 */

+#define EXTI_EMR3_EM86_Pos         (22U)

+#define EXTI_EMR3_EM86_Msk         (0x1UL << EXTI_EMR3_EM86_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR3_EM86             EXTI_EMR3_EM86_Msk                          /*!< Event Mask on line 86 */

+#define EXTI_EMR3_EM87_Pos         (23U)

+#define EXTI_EMR3_EM87_Msk         (0x1UL << EXTI_EMR3_EM87_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR3_EM87             EXTI_EMR3_EM87_Msk                          /*!< Event Mask on line 87 */

+

+/*******************  Bit definition for EXTI_PR3 register  ********************/

+#define EXTI_PR3_PR_Pos            (18U)

+#define EXTI_PR3_PR_Msk            (0x1DUL << EXTI_PR3_PR_Pos)                 /*!< 0x00740000 */

+#define EXTI_PR3_PR                EXTI_PR3_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR3_PR82_Pos          (18U)

+#define EXTI_PR3_PR82_Msk          (0x1UL << EXTI_PR3_PR82_Pos)                /*!< 0x00040000 */

+#define EXTI_PR3_PR82              EXTI_PR3_PR82_Msk                           /*!< Pending bit for line 82 */

+#define EXTI_PR3_PR84_Pos          (20U)

+#define EXTI_PR3_PR84_Msk          (0x1UL << EXTI_PR3_PR84_Pos)                /*!< 0x00100000 */

+#define EXTI_PR3_PR84              EXTI_PR3_PR84_Msk                           /*!< Pending bit for line 84 */

+#define EXTI_PR3_PR85_Pos          (21U)

+#define EXTI_PR3_PR85_Msk          (0x1UL << EXTI_PR3_PR85_Pos)                /*!< 0x00200000 */

+#define EXTI_PR3_PR85              EXTI_PR3_PR85_Msk                           /*!< Pending bit for line 85 */

+#define EXTI_PR3_PR86_Pos          (22U)

+#define EXTI_PR3_PR86_Msk          (0x1UL << EXTI_PR3_PR86_Pos)                /*!< 0x00400000 */

+#define EXTI_PR3_PR86              EXTI_PR3_PR86_Msk                           /*!< Pending bit for line 86 */

+/******************************************************************************/

+/*                                                                            */

+/*                                    FLASH                                   */

+/*                                                                            */

+/******************************************************************************/

+/*

+* @brief FLASH Global Defines

+*/

+#define FLASH_SECTOR_TOTAL                   8U                    /* 8 sectors */

+#define FLASH_SIZE                           0x200000UL            /* 2 MB   */

+#define FLASH_BANK_SIZE                      (FLASH_SIZE >> 1)     /* 1 MB   */

+#define FLASH_SECTOR_SIZE                    0x00020000UL          /* 128 KB */

+#define FLASH_LATENCY_DEFAULT                FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */

+#define FLASH_NB_32BITWORD_IN_FLASHWORD      8U                    /* 256 bits */

+#define DUAL_BANK                                                  /* Dual-bank Flash */

+

+/*******************  Bits definition for FLASH_ACR register  **********************/

+#define FLASH_ACR_LATENCY_Pos                (0U)

+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */

+#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */

+#define FLASH_ACR_LATENCY_0WS                (0x00000000UL)

+#define FLASH_ACR_LATENCY_1WS                (0x00000001UL)

+#define FLASH_ACR_LATENCY_2WS                (0x00000002UL)

+#define FLASH_ACR_LATENCY_3WS                (0x00000003UL)

+#define FLASH_ACR_LATENCY_4WS                (0x00000004UL)

+#define FLASH_ACR_LATENCY_5WS                (0x00000005UL)

+#define FLASH_ACR_LATENCY_6WS                (0x00000006UL)

+#define FLASH_ACR_LATENCY_7WS                (0x00000007UL)

+#define FLASH_ACR_LATENCY_8WS                (0x00000008UL)

+#define FLASH_ACR_LATENCY_9WS                (0x00000009UL)

+#define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)

+#define FLASH_ACR_LATENCY_11WS               (0x0000000BUL)

+#define FLASH_ACR_LATENCY_12WS               (0x0000000CUL)

+#define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)

+#define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)

+#define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)

+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)

+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */

+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */

+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */

+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */

+

+/*******************  Bits definition for FLASH_CR register  ***********************/

+#define FLASH_CR_LOCK_Pos                    (0U)

+#define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */

+#define FLASH_CR_LOCK                        FLASH_CR_LOCK_Msk                 /*!< Configuration lock bit */

+#define FLASH_CR_PG_Pos                      (1U)

+#define FLASH_CR_PG_Msk                      (0x1UL << FLASH_CR_PG_Pos)        /*!< 0x00000002 */

+#define FLASH_CR_PG                          FLASH_CR_PG_Msk                   /*!< Internal buffer control bit */

+#define FLASH_CR_SER_Pos                     (2U)

+#define FLASH_CR_SER_Msk                     (0x1UL << FLASH_CR_SER_Pos)       /*!< 0x00000004 */

+#define FLASH_CR_SER                         FLASH_CR_SER_Msk                  /*!< Sector erase request */

+#define FLASH_CR_BER_Pos                     (3U)

+#define FLASH_CR_BER_Msk                     (0x1UL << FLASH_CR_BER_Pos)       /*!< 0x00000008 */

+#define FLASH_CR_BER                         FLASH_CR_BER_Msk                  /*!< Bank erase request */

+#define FLASH_CR_PSIZE_Pos                   (4U)

+#define FLASH_CR_PSIZE_Msk                   (0x3UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000030 */

+#define FLASH_CR_PSIZE                       FLASH_CR_PSIZE_Msk                /*!< Program size */

+#define FLASH_CR_PSIZE_0                     (0x1UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000010 */

+#define FLASH_CR_PSIZE_1                     (0x2UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000020 */

+#define FLASH_CR_FW_Pos                      (6U)

+#define FLASH_CR_FW_Msk                      (0x1UL << FLASH_CR_FW_Pos)        /*!< 0x00000040 */

+#define FLASH_CR_FW                          FLASH_CR_FW_Msk                   /*!< Write forcing control bit */

+#define FLASH_CR_START_Pos                   (7U)

+#define FLASH_CR_START_Msk                   (0x1UL << FLASH_CR_START_Pos)     /*!< 0x00000080 */

+#define FLASH_CR_START                       FLASH_CR_START_Msk                /*!< Erase start control bit */

+#define FLASH_CR_SNB_Pos                     (8U)

+#define FLASH_CR_SNB_Msk                     (0x7UL << FLASH_CR_SNB_Pos)       /*!< 0x00000700 */

+#define FLASH_CR_SNB                         FLASH_CR_SNB_Msk                  /*!< Sector erase selection number */

+#define FLASH_CR_SNB_0                       (0x1UL << FLASH_CR_SNB_Pos)       /*!< 0x00000100 */

+#define FLASH_CR_SNB_1                       (0x2UL << FLASH_CR_SNB_Pos)       /*!< 0x00000200 */

+#define FLASH_CR_SNB_2                       (0x4UL << FLASH_CR_SNB_Pos)       /*!< 0x00000400 */

+#define FLASH_CR_CRC_EN_Pos                  (15U)

+#define FLASH_CR_CRC_EN_Msk                  (0x1UL << FLASH_CR_CRC_EN_Pos)    /*!< 0x00008000 */

+#define FLASH_CR_CRC_EN                      FLASH_CR_CRC_EN_Msk               /*!< CRC control bit */

+#define FLASH_CR_EOPIE_Pos                   (16U)

+#define FLASH_CR_EOPIE_Msk                   (0x1UL << FLASH_CR_EOPIE_Pos)     /*!< 0x00010000 */

+#define FLASH_CR_EOPIE                       FLASH_CR_EOPIE_Msk                /*!< End-of-program interrupt control bit */

+#define FLASH_CR_WRPERRIE_Pos                (17U)

+#define FLASH_CR_WRPERRIE_Msk                (0x1UL << FLASH_CR_WRPERRIE_Pos)  /*!< 0x00020000 */

+#define FLASH_CR_WRPERRIE                    FLASH_CR_WRPERRIE_Msk             /*!< Write protection error interrupt enable bit */

+#define FLASH_CR_PGSERRIE_Pos                (18U)

+#define FLASH_CR_PGSERRIE_Msk                (0x1UL << FLASH_CR_PGSERRIE_Pos)  /*!< 0x00040000 */

+#define FLASH_CR_PGSERRIE                    FLASH_CR_PGSERRIE_Msk             /*!< Programming sequence error interrupt enable bit */

+#define FLASH_CR_STRBERRIE_Pos               (19U)

+#define FLASH_CR_STRBERRIE_Msk               (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */

+#define FLASH_CR_STRBERRIE                   FLASH_CR_STRBERRIE_Msk            /*!< Strobe error interrupt enable bit */

+#define FLASH_CR_INCERRIE_Pos                (21U)

+#define FLASH_CR_INCERRIE_Msk                (0x1UL << FLASH_CR_INCERRIE_Pos)  /*!< 0x00200000 */

+#define FLASH_CR_INCERRIE                    FLASH_CR_INCERRIE_Msk             /*!< Inconsistency error interrupt enable bit */

+#define FLASH_CR_OPERRIE_Pos                 (22U)

+#define FLASH_CR_OPERRIE_Msk                 (0x1UL << FLASH_CR_OPERRIE_Pos)   /*!< 0x00400000 */

+#define FLASH_CR_OPERRIE                     FLASH_CR_OPERRIE_Msk              /*!< Write/erase error interrupt enable bit */

+#define FLASH_CR_RDPERRIE_Pos                (23U)

+#define FLASH_CR_RDPERRIE_Msk                (0x1UL << FLASH_CR_RDPERRIE_Pos)  /*!< 0x00800000 */

+#define FLASH_CR_RDPERRIE                    FLASH_CR_RDPERRIE_Msk             /*!< Read protection error interrupt enable bit */

+#define FLASH_CR_RDSERRIE_Pos                (24U)

+#define FLASH_CR_RDSERRIE_Msk                (0x1UL << FLASH_CR_RDSERRIE_Pos)  /*!< 0x01000000 */

+#define FLASH_CR_RDSERRIE                    FLASH_CR_RDSERRIE_Msk             /*!< Secure error interrupt enable bit */

+#define FLASH_CR_SNECCERRIE_Pos              (25U)

+#define FLASH_CR_SNECCERRIE_Msk              (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */

+#define FLASH_CR_SNECCERRIE                  FLASH_CR_SNECCERRIE_Msk            /*!< ECC single correction error interrupt enable bit */

+#define FLASH_CR_DBECCERRIE_Pos              (26U)

+#define FLASH_CR_DBECCERRIE_Msk              (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */

+#define FLASH_CR_DBECCERRIE                  FLASH_CR_DBECCERRIE_Msk            /*!< ECC double detection error interrupt enable bit */

+#define FLASH_CR_CRCENDIE_Pos                (27U)

+#define FLASH_CR_CRCENDIE_Msk                (0x1UL << FLASH_CR_CRCENDIE_Pos)  /*!< 0x08000000 */

+#define FLASH_CR_CRCENDIE                    FLASH_CR_CRCENDIE_Msk             /*!< CRC end of calculation interrupt enable bit */

+#define FLASH_CR_CRCRDERRIE_Pos              (28U)

+#define FLASH_CR_CRCRDERRIE_Msk              (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */

+#define FLASH_CR_CRCRDERRIE                  FLASH_CR_CRCRDERRIE_Msk            /*!< CRC read error interrupt enable bit */

+

+/*******************  Bits definition for FLASH_SR register  ***********************/

+#define FLASH_SR_BSY_Pos                     (0U)

+#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)       /*!< 0x00000001 */

+#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy flag */

+#define FLASH_SR_WBNE_Pos                    (1U)

+#define FLASH_SR_WBNE_Msk                    (0x1UL << FLASH_SR_WBNE_Pos)      /*!< 0x00000002 */

+#define FLASH_SR_WBNE                        FLASH_SR_WBNE_Msk                 /*!< Write buffer not empty flag */

+#define FLASH_SR_QW_Pos                      (2U)

+#define FLASH_SR_QW_Msk                      (0x1UL << FLASH_SR_QW_Pos)        /*!< 0x00000004 */

+#define FLASH_SR_QW                          FLASH_SR_QW_Msk                   /*!< Wait queue flag */

+#define FLASH_SR_CRC_BUSY_Pos                (3U)

+#define FLASH_SR_CRC_BUSY_Msk                (0x1UL << FLASH_SR_CRC_BUSY_Pos)  /*!< 0x00000008 */

+#define FLASH_SR_CRC_BUSY                    FLASH_SR_CRC_BUSY_Msk             /*!< CRC busy flag */

+#define FLASH_SR_EOP_Pos                     (16U)

+#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)       /*!< 0x00010000 */

+#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End-of-program flag */

+#define FLASH_SR_WRPERR_Pos                  (17U)

+#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)    /*!< 0x00020000 */

+#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protection error flag */

+#define FLASH_SR_PGSERR_Pos                  (18U)

+#define FLASH_SR_PGSERR_Msk                  (0x1UL << FLASH_SR_PGSERR_Pos)    /*!< 0x00040000 */

+#define FLASH_SR_PGSERR                      FLASH_SR_PGSERR_Msk               /*!< Programming sequence error flag */

+#define FLASH_SR_STRBERR_Pos                 (19U)

+#define FLASH_SR_STRBERR_Msk                 (0x1UL << FLASH_SR_STRBERR_Pos)   /*!< 0x00080000 */

+#define FLASH_SR_STRBERR                     FLASH_SR_STRBERR_Msk              /*!< Strobe error flag */

+#define FLASH_SR_INCERR_Pos                  (21U)

+#define FLASH_SR_INCERR_Msk                  (0x1UL << FLASH_SR_INCERR_Pos)    /*!< 0x00200000 */

+#define FLASH_SR_INCERR                      FLASH_SR_INCERR_Msk               /*!< Inconsistency error flag */

+#define FLASH_SR_OPERR_Pos                   (22U)

+#define FLASH_SR_OPERR_Msk                   (0x1UL << FLASH_SR_OPERR_Pos)     /*!< 0x00400000 */

+#define FLASH_SR_OPERR                       FLASH_SR_OPERR_Msk                /*!< Write/erase error flag */

+#define FLASH_SR_RDPERR_Pos                  (23U)

+#define FLASH_SR_RDPERR_Msk                  (0x1UL << FLASH_SR_RDPERR_Pos)    /*!< 0x00800000 */

+#define FLASH_SR_RDPERR                      FLASH_SR_RDPERR_Msk               /*!< Read protection error flag */

+#define FLASH_SR_RDSERR_Pos                  (24U)

+#define FLASH_SR_RDSERR_Msk                  (0x1UL << FLASH_SR_RDSERR_Pos)    /*!< 0x01000000 */

+#define FLASH_SR_RDSERR                      FLASH_SR_RDSERR_Msk               /*!< Secure error flag */

+#define FLASH_SR_SNECCERR_Pos                (25U)

+#define FLASH_SR_SNECCERR_Msk                (0x1UL << FLASH_SR_SNECCERR_Pos)  /*!< 0x02000000 */

+#define FLASH_SR_SNECCERR                    FLASH_SR_SNECCERR_Msk             /*!< Single correction error flag */

+#define FLASH_SR_DBECCERR_Pos                (26U)

+#define FLASH_SR_DBECCERR_Msk                (0x1UL << FLASH_SR_DBECCERR_Pos)  /*!< 0x04000000 */

+#define FLASH_SR_DBECCERR                    FLASH_SR_DBECCERR_Msk             /*!< ECC double detection error flag */

+#define FLASH_SR_CRCEND_Pos                  (27U)

+#define FLASH_SR_CRCEND_Msk                  (0x1UL << FLASH_SR_CRCEND_Pos)    /*!< 0x08000000 */

+#define FLASH_SR_CRCEND                      FLASH_SR_CRCEND_Msk               /*!< CRC end of calculation flag */

+#define FLASH_SR_CRCRDERR_Pos                (28U)

+#define FLASH_SR_CRCRDERR_Msk                (0x1UL << FLASH_SR_CRCRDERR_Pos)  /*!< 0x10000000 */

+#define FLASH_SR_CRCRDERR                    FLASH_SR_CRCRDERR_Msk             /*!< CRC read error flag */

+

+/*******************  Bits definition for FLASH_CCR register  *******************/

+#define FLASH_CCR_CLR_EOP_Pos                (16U)

+#define FLASH_CCR_CLR_EOP_Msk                (0x1UL << FLASH_CCR_CLR_EOP_Pos)  /*!< 0x00010000 */

+#define FLASH_CCR_CLR_EOP                    FLASH_CCR_CLR_EOP_Msk             /*!< EOP flag clear bit */

+#define FLASH_CCR_CLR_WRPERR_Pos             (17U)

+#define FLASH_CCR_CLR_WRPERR_Msk             (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */

+#define FLASH_CCR_CLR_WRPERR                 FLASH_CCR_CLR_WRPERR_Msk            /*!< WRPERR flag clear bit */

+#define FLASH_CCR_CLR_PGSERR_Pos             (18U)

+#define FLASH_CCR_CLR_PGSERR_Msk             (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */

+#define FLASH_CCR_CLR_PGSERR                 FLASH_CCR_CLR_PGSERR_Msk            /*!< PGSERR flag clear bit */

+#define FLASH_CCR_CLR_STRBERR_Pos            (19U)

+#define FLASH_CCR_CLR_STRBERR_Msk            (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */

+#define FLASH_CCR_CLR_STRBERR                FLASH_CCR_CLR_STRBERR_Msk            /*!< STRBERR flag clear bit */

+#define FLASH_CCR_CLR_INCERR_Pos             (21U)

+#define FLASH_CCR_CLR_INCERR_Msk             (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */

+#define FLASH_CCR_CLR_INCERR                 FLASH_CCR_CLR_INCERR_Msk            /*!< INCERR flag clear bit */

+#define FLASH_CCR_CLR_OPERR_Pos              (22U)

+#define FLASH_CCR_CLR_OPERR_Msk              (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */

+#define FLASH_CCR_CLR_OPERR                  FLASH_CCR_CLR_OPERR_Msk            /*!< OPERR flag clear bit */

+#define FLASH_CCR_CLR_RDPERR_Pos             (23U)

+#define FLASH_CCR_CLR_RDPERR_Msk             (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */

+#define FLASH_CCR_CLR_RDPERR                 FLASH_CCR_CLR_RDPERR_Msk            /*!< RDPERR flag clear bit */

+#define FLASH_CCR_CLR_RDSERR_Pos             (24U)

+#define FLASH_CCR_CLR_RDSERR_Msk             (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */

+#define FLASH_CCR_CLR_RDSERR                 FLASH_CCR_CLR_RDSERR_Msk            /*!< RDSERR flag clear bit */

+#define FLASH_CCR_CLR_SNECCERR_Pos           (25U)

+#define FLASH_CCR_CLR_SNECCERR_Msk           (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */

+#define FLASH_CCR_CLR_SNECCERR               FLASH_CCR_CLR_SNECCERR_Msk            /*!< SNECCERR flag clear bit */

+#define FLASH_CCR_CLR_DBECCERR_Pos           (26U)

+#define FLASH_CCR_CLR_DBECCERR_Msk           (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */

+#define FLASH_CCR_CLR_DBECCERR               FLASH_CCR_CLR_DBECCERR_Msk            /*!< DBECCERR flag clear bit */

+#define FLASH_CCR_CLR_CRCEND_Pos             (27U)

+#define FLASH_CCR_CLR_CRCEND_Msk             (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */

+#define FLASH_CCR_CLR_CRCEND                 FLASH_CCR_CLR_CRCEND_Msk            /*!< CRCEND flag clear bit */

+#define FLASH_CCR_CLR_CRCRDERR_Pos           (28U)

+#define FLASH_CCR_CLR_CRCRDERR_Msk           (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */

+#define FLASH_CCR_CLR_CRCRDERR               FLASH_CCR_CLR_CRCRDERR_Msk            /*!< CRCRDERR flag clear bit */

+

+/*******************  Bits definition for FLASH_OPTCR register  *******************/

+#define FLASH_OPTCR_OPTLOCK_Pos              (0U)

+#define FLASH_OPTCR_OPTLOCK_Msk              (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)  /*!< 0x00000001 */

+#define FLASH_OPTCR_OPTLOCK                  FLASH_OPTCR_OPTLOCK_Msk             /*!< FLASH_OPTCR lock option configuration bit */

+#define FLASH_OPTCR_OPTSTART_Pos             (1U)

+#define FLASH_OPTCR_OPTSTART_Msk             (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */

+#define FLASH_OPTCR_OPTSTART                 FLASH_OPTCR_OPTSTART_Msk            /*!< Option byte start change option configuration bit */

+#define FLASH_OPTCR_MER_Pos                  (4U)

+#define FLASH_OPTCR_MER_Msk                  (0x1UL << FLASH_OPTCR_MER_Pos)      /*!< 0x00000010 */

+#define FLASH_OPTCR_MER                      FLASH_OPTCR_MER_Msk                 /*!< Mass erase request */

+#define FLASH_OPTCR_OPTCHANGEERRIE_Pos       (30U)

+#define FLASH_OPTCR_OPTCHANGEERRIE_Msk       (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */

+#define FLASH_OPTCR_OPTCHANGEERRIE           FLASH_OPTCR_OPTCHANGEERRIE_Msk            /*!< Option byte change error interrupt enable bit */

+#define FLASH_OPTCR_SWAP_BANK_Pos            (31U)

+#define FLASH_OPTCR_SWAP_BANK_Msk            (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */

+#define FLASH_OPTCR_SWAP_BANK                FLASH_OPTCR_SWAP_BANK_Msk            /*!< Bank swapping option configuration bit */

+

+/*******************  Bits definition for FLASH_OPTSR register  ***************/

+#define FLASH_OPTSR_OPT_BUSY_Pos             (0U)

+#define FLASH_OPTSR_OPT_BUSY_Msk             (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */

+#define FLASH_OPTSR_OPT_BUSY                 FLASH_OPTSR_OPT_BUSY_Msk            /*!< Option byte change ongoing flag */

+#define FLASH_OPTSR_BOR_LEV_Pos              (2U)

+#define FLASH_OPTSR_BOR_LEV_Msk              (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */

+#define FLASH_OPTSR_BOR_LEV                  FLASH_OPTSR_BOR_LEV_Msk            /*!< Brownout level option status bit */

+#define FLASH_OPTSR_BOR_LEV_0                (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */

+#define FLASH_OPTSR_BOR_LEV_1                (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */

+#define FLASH_OPTSR_IWDG1_SW_Pos             (4U)

+#define FLASH_OPTSR_IWDG1_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */

+#define FLASH_OPTSR_IWDG1_SW                 FLASH_OPTSR_IWDG1_SW_Msk            /*!< IWDG1 control mode option status bit */

+#define FLASH_OPTSR_NRST_STOP_D1_Pos         (6U)

+#define FLASH_OPTSR_NRST_STOP_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */

+#define FLASH_OPTSR_NRST_STOP_D1             FLASH_OPTSR_NRST_STOP_D1_Msk            /*!< D1 domain DStop entry reset option status bit */

+#define FLASH_OPTSR_NRST_STBY_D1_Pos         (7U)

+#define FLASH_OPTSR_NRST_STBY_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */

+#define FLASH_OPTSR_NRST_STBY_D1             FLASH_OPTSR_NRST_STBY_D1_Msk            /*!< D1 domain DStandby entry reset option status bit */

+#define FLASH_OPTSR_RDP_Pos                  (8U)

+#define FLASH_OPTSR_RDP_Msk                  (0xFFUL << FLASH_OPTSR_RDP_Pos)   /*!< 0x0000FF00 */

+#define FLASH_OPTSR_RDP                      FLASH_OPTSR_RDP_Msk               /*!< Readout protection level option status byte */

+#define FLASH_OPTSR_FZ_IWDG_STOP_Pos         (17U)

+#define FLASH_OPTSR_FZ_IWDG_STOP_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */

+#define FLASH_OPTSR_FZ_IWDG_STOP             FLASH_OPTSR_FZ_IWDG_STOP_Msk            /*!< IWDG Stop mode freeze option status bit */

+#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos         (18U)

+#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */

+#define FLASH_OPTSR_FZ_IWDG_SDBY             FLASH_OPTSR_FZ_IWDG_SDBY_Msk            /*!< IWDG Standby mode freeze option status bit */

+#define FLASH_OPTSR_ST_RAM_SIZE_Pos          (19U)

+#define FLASH_OPTSR_ST_RAM_SIZE_Msk          (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */

+#define FLASH_OPTSR_ST_RAM_SIZE              FLASH_OPTSR_ST_RAM_SIZE_Msk            /*!< ST RAM size option status */

+#define FLASH_OPTSR_ST_RAM_SIZE_0            (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */

+#define FLASH_OPTSR_ST_RAM_SIZE_1            (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */

+#define FLASH_OPTSR_SECURITY_Pos             (21U)

+#define FLASH_OPTSR_SECURITY_Msk             (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */

+#define FLASH_OPTSR_SECURITY                 FLASH_OPTSR_SECURITY_Msk            /*!< Security enable option status bit */

+#define FLASH_OPTSR_IO_HSLV_Pos              (29U)

+#define FLASH_OPTSR_IO_HSLV_Msk              (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */

+#define FLASH_OPTSR_IO_HSLV                  FLASH_OPTSR_IO_HSLV_Msk            /*!< I/O high-speed at low-voltage status bit */

+#define FLASH_OPTSR_OPTCHANGEERR_Pos         (30U)

+#define FLASH_OPTSR_OPTCHANGEERR_Msk         (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */

+#define FLASH_OPTSR_OPTCHANGEERR             FLASH_OPTSR_OPTCHANGEERR_Msk            /*!< Option byte change error flag */

+#define FLASH_OPTSR_SWAP_BANK_OPT_Pos        (31U)

+#define FLASH_OPTSR_SWAP_BANK_OPT_Msk        (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */

+#define FLASH_OPTSR_SWAP_BANK_OPT            FLASH_OPTSR_SWAP_BANK_OPT_Msk            /*!< Bank swapping option status bit */

+

+/*******************  Bits definition for FLASH_OPTCCR register  *******************/

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos    (30U)

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk    (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR        FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk            /*!< OPTCHANGEERR reset bit */

+

+/*******************  Bits definition for FLASH_PRAR register  *********************/

+#define FLASH_PRAR_PROT_AREA_START_Pos       (0U)

+#define FLASH_PRAR_PROT_AREA_START_Msk       (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */

+#define FLASH_PRAR_PROT_AREA_START           FLASH_PRAR_PROT_AREA_START_Msk              /*!< PCROP area start status bits */

+#define FLASH_PRAR_PROT_AREA_END_Pos         (16U)

+#define FLASH_PRAR_PROT_AREA_END_Msk         (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */

+#define FLASH_PRAR_PROT_AREA_END             FLASH_PRAR_PROT_AREA_END_Msk              /*!< PCROP area end status bits */

+#define FLASH_PRAR_DMEP_Pos                  (31U)

+#define FLASH_PRAR_DMEP_Msk                  (0x1UL << FLASH_PRAR_DMEP_Pos)    /*!< 0x80000000 */

+#define FLASH_PRAR_DMEP                      FLASH_PRAR_DMEP_Msk               /*!< PCROP protected erase enable option status bit */

+

+/*******************  Bits definition for FLASH_SCAR register  *********************/

+#define FLASH_SCAR_SEC_AREA_START_Pos        (0U)

+#define FLASH_SCAR_SEC_AREA_START_Msk        (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */

+#define FLASH_SCAR_SEC_AREA_START            FLASH_SCAR_SEC_AREA_START_Msk              /*!< Secure-only area start status bits */

+#define FLASH_SCAR_SEC_AREA_END_Pos          (16U)

+#define FLASH_SCAR_SEC_AREA_END_Msk          (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */

+#define FLASH_SCAR_SEC_AREA_END              FLASH_SCAR_SEC_AREA_END_Msk              /*!< Secure-only area end status bits */

+#define FLASH_SCAR_DMES_Pos                  (31U)

+#define FLASH_SCAR_DMES_Msk                  (0x1UL << FLASH_SCAR_DMES_Pos)    /*!< 0x80000000 */

+#define FLASH_SCAR_DMES                      FLASH_SCAR_DMES_Msk               /*!< Secure access protected erase enable option status bit */

+

+/*******************  Bits definition for FLASH_WPSN register  *********************/

+#define FLASH_WPSN_WRPSN_Pos                 (0U)

+#define FLASH_WPSN_WRPSN_Msk                 (0xFFUL << FLASH_WPSN_WRPSN_Pos)  /*!< 0x000000FF */

+#define FLASH_WPSN_WRPSN                     FLASH_WPSN_WRPSN_Msk              /*!< Sector write protection option status byte */

+

+/*******************  Bits definition for FLASH_BOOT_CUR register  ****************/

+#define FLASH_BOOT_ADD0_Pos                  (0U)

+#define FLASH_BOOT_ADD0_Msk                  (0xFFFFUL << FLASH_BOOT_ADD0_Pos) /*!< 0x0000FFFF */

+#define FLASH_BOOT_ADD0                      FLASH_BOOT_ADD0_Msk               /*!< Arm Cortex-M7 boot address 0 */

+#define FLASH_BOOT_ADD1_Pos                  (16U)

+#define FLASH_BOOT_ADD1_Msk                  (0xFFFFUL << FLASH_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */

+#define FLASH_BOOT_ADD1                      FLASH_BOOT_ADD1_Msk               /*!< Arm Cortex-M7 boot address 1 */

+

+

+/*******************  Bits definition for FLASH_CRCCR register  ********************/

+#define FLASH_CRCCR_CRC_SECT_Pos             (0U)

+#define FLASH_CRCCR_CRC_SECT_Msk             (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */

+#define FLASH_CRCCR_CRC_SECT                 FLASH_CRCCR_CRC_SECT_Msk            /*!< CRC sector number */

+#define FLASH_CRCCR_CRC_BY_SECT_Pos          (8U)

+#define FLASH_CRCCR_CRC_BY_SECT_Msk          (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */

+#define FLASH_CRCCR_CRC_BY_SECT              FLASH_CRCCR_CRC_BY_SECT_Msk            /*!< CRC sector mode select bit */

+#define FLASH_CRCCR_ADD_SECT_Pos             (9U)

+#define FLASH_CRCCR_ADD_SECT_Msk             (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */

+#define FLASH_CRCCR_ADD_SECT                 FLASH_CRCCR_ADD_SECT_Msk            /*!< CRC sector select bit */

+#define FLASH_CRCCR_CLEAN_SECT_Pos           (10U)

+#define FLASH_CRCCR_CLEAN_SECT_Msk           (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */

+#define FLASH_CRCCR_CLEAN_SECT               FLASH_CRCCR_CLEAN_SECT_Msk            /*!< CRC sector list clear bit */

+#define FLASH_CRCCR_START_CRC_Pos            (16U)

+#define FLASH_CRCCR_START_CRC_Msk            (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */

+#define FLASH_CRCCR_START_CRC                FLASH_CRCCR_START_CRC_Msk            /*!< CRC start bit */

+#define FLASH_CRCCR_CLEAN_CRC_Pos            (17U)

+#define FLASH_CRCCR_CLEAN_CRC_Msk            (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */

+#define FLASH_CRCCR_CLEAN_CRC                FLASH_CRCCR_CLEAN_CRC_Msk            /*!< CRC clear bit */

+#define FLASH_CRCCR_CRC_BURST_Pos            (20U)

+#define FLASH_CRCCR_CRC_BURST_Msk            (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */

+#define FLASH_CRCCR_CRC_BURST                FLASH_CRCCR_CRC_BURST_Msk            /*!< CRC burst size */

+#define FLASH_CRCCR_CRC_BURST_0              (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */

+#define FLASH_CRCCR_CRC_BURST_1              (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */

+#define FLASH_CRCCR_ALL_BANK_Pos             (22U)

+#define FLASH_CRCCR_ALL_BANK_Msk             (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */

+#define FLASH_CRCCR_ALL_BANK                 FLASH_CRCCR_ALL_BANK_Msk            /*!< CRC select bit */

+

+/*******************  Bits definition for FLASH_CRCSADD register  ****************/

+#define FLASH_CRCSADD_CRC_START_ADDR_Pos     (0U)

+#define FLASH_CRCSADD_CRC_START_ADDR_Msk     (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCSADD_CRC_START_ADDR         FLASH_CRCSADD_CRC_START_ADDR_Msk                   /*!< CRC start address */

+

+/*******************  Bits definition for FLASH_CRCEADD register  ****************/

+#define FLASH_CRCEADD_CRC_END_ADDR_Pos       (0U)

+#define FLASH_CRCEADD_CRC_END_ADDR_Msk       (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCEADD_CRC_END_ADDR           FLASH_CRCEADD_CRC_END_ADDR_Msk                   /*!< CRC end address */

+

+/*******************  Bits definition for FLASH_CRCDATA register  ***************/

+#define FLASH_CRCDATA_CRC_DATA_Pos           (0U)

+#define FLASH_CRCDATA_CRC_DATA_Msk           (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCDATA_CRC_DATA               FLASH_CRCDATA_CRC_DATA_Msk                   /*!< CRC result */

+

+/*******************  Bits definition for FLASH_ECC_FA register  *******************/

+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos       (0U)

+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk       (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */

+#define FLASH_ECC_FA_FAIL_ECC_ADDR           FLASH_ECC_FA_FAIL_ECC_ADDR_Msk               /*!< ECC error address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          Flexible Memory Controller                        */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for FMC_BCR1 register  *******************/

+#define FMC_BCR1_CCLKEN_Pos        (20U)

+#define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */

+#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continous clock enable     */

+#define FMC_BCR1_WFDIS_Pos         (21U)

+#define FMC_BCR1_WFDIS_Msk         (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */

+#define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */

+

+#define FMC_BCR1_BMAP_Pos          (24U)

+#define FMC_BCR1_BMAP_Msk          (0x3UL << FMC_BCR1_BMAP_Pos)                /*!< 0x03000000 */

+#define FMC_BCR1_BMAP              FMC_BCR1_BMAP_Msk                           /*!<BMAP[1:0] FMC bank mapping */

+#define FMC_BCR1_BMAP_0            (0x1UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x01000000 */

+#define FMC_BCR1_BMAP_1            (0x2UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x02000000 */

+

+#define FMC_BCR1_FMCEN_Pos         (31U)

+#define FMC_BCR1_FMCEN_Msk         (0x1UL << FMC_BCR1_FMCEN_Pos)               /*!< 0x80000000 */

+#define FMC_BCR1_FMCEN             FMC_BCR1_FMCEN_Msk                          /*!<FMC controller Enable */

+/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/

+#define FMC_BCRx_MBKEN_Pos         (0U)

+#define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */

+#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */

+#define FMC_BCRx_MUXEN_Pos         (1U)

+#define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */

+#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */

+

+#define FMC_BCRx_MTYP_Pos          (2U)

+#define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */

+#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */

+#define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000004 */

+#define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000008 */

+

+#define FMC_BCRx_MWID_Pos          (4U)

+#define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */

+#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */

+#define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000010 */

+#define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000020 */

+

+#define FMC_BCRx_FACCEN_Pos        (6U)

+#define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */

+#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */

+#define FMC_BCRx_BURSTEN_Pos       (8U)

+#define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */

+#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */

+#define FMC_BCRx_WAITPOL_Pos       (9U)

+#define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */

+#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */

+#define FMC_BCRx_WAITCFG_Pos       (11U)

+#define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */

+#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */

+#define FMC_BCRx_WREN_Pos          (12U)

+#define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */

+#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */

+#define FMC_BCRx_WAITEN_Pos        (13U)

+#define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */

+#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */

+#define FMC_BCRx_EXTMOD_Pos        (14U)

+#define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */

+#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */

+#define FMC_BCRx_ASYNCWAIT_Pos     (15U)

+#define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */

+#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */

+

+#define FMC_BCRx_CPSIZE_Pos        (16U)

+#define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */

+#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<PSIZE[2:0] bits CRAM Page Size */

+#define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00010000 */

+#define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00020000 */

+#define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00040000 */

+

+#define FMC_BCRx_CBURSTRW_Pos      (19U)

+#define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */

+#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */

+

+/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/

+#define FMC_BTRx_ADDSET_Pos        (0U)

+#define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */

+#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */

+#define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000001 */

+#define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000002 */

+#define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000004 */

+#define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000008 */

+

+#define FMC_BTRx_ADDHLD_Pos        (4U)

+#define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */

+#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */

+#define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000010 */

+#define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000020 */

+#define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000040 */

+#define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000080 */

+

+#define FMC_BTRx_DATAST_Pos        (8U)

+#define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */

+#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */

+#define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000100 */

+#define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000200 */

+#define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000400 */

+#define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000800 */

+#define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00001000 */

+#define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00002000 */

+#define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00004000 */

+#define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00008000 */

+

+#define FMC_BTRx_BUSTURN_Pos       (16U)

+#define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */

+#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */

+#define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00010000 */

+#define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00020000 */

+#define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00040000 */

+#define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00080000 */

+

+#define FMC_BTRx_CLKDIV_Pos        (20U)

+#define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */

+#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */

+#define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00100000 */

+#define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00200000 */

+#define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00400000 */

+#define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00800000 */

+

+#define FMC_BTRx_DATLAT_Pos        (24U)

+#define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */

+#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */

+#define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x01000000 */

+#define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x02000000 */

+#define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x04000000 */

+#define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x08000000 */

+

+#define FMC_BTRx_ACCMOD_Pos        (28U)

+#define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */

+#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */

+#define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x10000000 */

+#define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x20000000 */

+

+/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/

+#define FMC_BWTRx_ADDSET_Pos       (0U)

+#define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */

+#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */

+#define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000001 */

+#define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000002 */

+#define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000004 */

+#define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000008 */

+

+#define FMC_BWTRx_ADDHLD_Pos       (4U)

+#define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */

+#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */

+#define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000010 */

+#define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000020 */

+#define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000040 */

+#define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000080 */

+

+#define FMC_BWTRx_DATAST_Pos       (8U)

+#define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */

+#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */

+#define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000100 */

+#define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000200 */

+#define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000400 */

+#define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000800 */

+#define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00001000 */

+#define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00002000 */

+#define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00004000 */

+#define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00008000 */

+

+#define FMC_BWTRx_BUSTURN_Pos      (16U)

+#define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */

+#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */

+#define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00010000 */

+#define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00020000 */

+#define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00040000 */

+#define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00080000 */

+

+#define FMC_BWTRx_ACCMOD_Pos       (28U)

+#define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */

+#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */

+#define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x10000000 */

+#define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x20000000 */

+

+/******************  Bit definition for FMC_PCR register  *******************/

+#define FMC_PCR_PWAITEN_Pos        (1U)

+#define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */

+#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */

+#define FMC_PCR_PBKEN_Pos          (2U)

+#define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */

+#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */

+

+#define FMC_PCR_PWID_Pos           (4U)

+#define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */

+#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */

+#define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */

+#define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */

+

+#define FMC_PCR_ECCEN_Pos          (6U)

+#define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */

+#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */

+

+#define FMC_PCR_TCLR_Pos           (9U)

+#define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */

+#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */

+#define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */

+#define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */

+#define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */

+#define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */

+

+#define FMC_PCR_TAR_Pos            (13U)

+#define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */

+#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */

+#define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */

+#define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */

+#define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */

+#define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */

+

+#define FMC_PCR_ECCPS_Pos          (17U)

+#define FMC_PCR_ECCPS_Msk          (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */

+#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */

+#define FMC_PCR_ECCPS_0            (0x1UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */

+#define FMC_PCR_ECCPS_1            (0x2UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */

+#define FMC_PCR_ECCPS_2            (0x4UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */

+

+/*******************  Bit definition for FMC_SR register  *******************/

+#define FMC_SR_IRS_Pos             (0U)

+#define FMC_SR_IRS_Msk             (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */

+#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */

+#define FMC_SR_ILS_Pos             (1U)

+#define FMC_SR_ILS_Msk             (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */

+#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */

+#define FMC_SR_IFS_Pos             (2U)

+#define FMC_SR_IFS_Msk             (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */

+#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */

+#define FMC_SR_IREN_Pos            (3U)

+#define FMC_SR_IREN_Msk            (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */

+#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */

+#define FMC_SR_ILEN_Pos            (4U)

+#define FMC_SR_ILEN_Msk            (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */

+#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */

+#define FMC_SR_IFEN_Pos            (5U)

+#define FMC_SR_IFEN_Msk            (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */

+#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */

+#define FMC_SR_FEMPT_Pos           (6U)

+#define FMC_SR_FEMPT_Msk           (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */

+#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */

+

+/******************  Bit definition for FMC_PMEM register  ******************/

+#define FMC_PMEM_MEMSET_Pos       (0U)

+#define FMC_PMEM_MEMSET_Msk       (0xFFUL << FMC_PMEM_MEMSET_Pos)            /*!< 0x000000FF */

+#define FMC_PMEM_MEMSET           FMC_PMEM_MEMSET_Msk                        /*!<MEMSET[7:0] bits (Common memory setup time) */

+#define FMC_PMEM_MEMSET_0         (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */

+#define FMC_PMEM_MEMSET_1         (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */

+#define FMC_PMEM_MEMSET_2         (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */

+#define FMC_PMEM_MEMSET_3         (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */

+#define FMC_PMEM_MEMSET_4         (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */

+#define FMC_PMEM_MEMSET_5         (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */

+#define FMC_PMEM_MEMSET_6         (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */

+#define FMC_PMEM_MEMSET_7         (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */

+

+#define FMC_PMEM_MEMWAIT_Pos      (8U)

+#define FMC_PMEM_MEMWAIT_Msk      (0xFFUL << FMC_PMEM_MEMWAIT_Pos)           /*!< 0x0000FF00 */

+#define FMC_PMEM_MEMWAIT          FMC_PMEM_MEMWAIT_Msk                       /*!<MEMWAIT[7:0] bits (Common memory wait time) */

+#define FMC_PMEM_MEMWAIT_0        (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */

+#define FMC_PMEM_MEMWAIT_1        (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */

+#define FMC_PMEM_MEMWAIT_2        (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */

+#define FMC_PMEM_MEMWAIT_3        (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */

+#define FMC_PMEM_MEMWAIT_4        (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */

+#define FMC_PMEM_MEMWAIT_5        (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */

+#define FMC_PMEM_MEMWAIT_6        (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */

+#define FMC_PMEM_MEMWAIT_7        (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */

+

+#define FMC_PMEM_MEMHOLD_Pos      (16U)

+#define FMC_PMEM_MEMHOLD_Msk      (0xFFUL << FMC_PMEM_MEMHOLD_Pos)           /*!< 0x00FF0000 */

+#define FMC_PMEM_MEMHOLD          FMC_PMEM_MEMHOLD_Msk                       /*!<MEMHOLD[7:0] bits (Common memory hold time) */

+#define FMC_PMEM_MEMHOLD_0        (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */

+#define FMC_PMEM_MEMHOLD_1        (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */

+#define FMC_PMEM_MEMHOLD_2        (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */

+#define FMC_PMEM_MEMHOLD_3        (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */

+#define FMC_PMEM_MEMHOLD_4        (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */

+#define FMC_PMEM_MEMHOLD_5        (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */

+#define FMC_PMEM_MEMHOLD_6        (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */

+#define FMC_PMEM_MEMHOLD_7        (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */

+

+#define FMC_PMEM_MEMHIZ_Pos       (24U)

+#define FMC_PMEM_MEMHIZ_Msk       (0xFFUL << FMC_PMEM_MEMHIZ_Pos)            /*!< 0xFF000000 */

+#define FMC_PMEM_MEMHIZ           FMC_PMEM_MEMHIZ_Msk                        /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */

+#define FMC_PMEM_MEMHIZ_0         (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */

+#define FMC_PMEM_MEMHIZ_1         (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */

+#define FMC_PMEM_MEMHIZ_2         (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */

+#define FMC_PMEM_MEMHIZ_3         (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */

+#define FMC_PMEM_MEMHIZ_4         (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */

+#define FMC_PMEM_MEMHIZ_5         (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */

+#define FMC_PMEM_MEMHIZ_6         (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */

+#define FMC_PMEM_MEMHIZ_7         (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */

+

+/******************  Bit definition for FMC_PATT register  ******************/

+#define FMC_PATT_ATTSET_Pos       (0U)

+#define FMC_PATT_ATTSET_Msk       (0xFFUL << FMC_PATT_ATTSET_Pos)            /*!< 0x000000FF */

+#define FMC_PATT_ATTSET           FMC_PATT_ATTSET_Msk                        /*!<ATTSET[7:0] bits (Attribute memory setup time) */

+#define FMC_PATT_ATTSET_0         (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */

+#define FMC_PATT_ATTSET_1         (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */

+#define FMC_PATT_ATTSET_2         (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */

+#define FMC_PATT_ATTSET_3         (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */

+#define FMC_PATT_ATTSET_4         (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */

+#define FMC_PATT_ATTSET_5         (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */

+#define FMC_PATT_ATTSET_6         (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */

+#define FMC_PATT_ATTSET_7         (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */

+

+#define FMC_PATT_ATTWAIT_Pos      (8U)

+#define FMC_PATT_ATTWAIT_Msk      (0xFFUL << FMC_PATT_ATTWAIT_Pos)           /*!< 0x0000FF00 */

+#define FMC_PATT_ATTWAIT          FMC_PATT_ATTWAIT_Msk                       /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */

+#define FMC_PATT_ATTWAIT_0        (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */

+#define FMC_PATT_ATTWAIT_1        (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */

+#define FMC_PATT_ATTWAIT_2        (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */

+#define FMC_PATT_ATTWAIT_3        (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */

+#define FMC_PATT_ATTWAIT_4        (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */

+#define FMC_PATT_ATTWAIT_5        (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */

+#define FMC_PATT_ATTWAIT_6        (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */

+#define FMC_PATT_ATTWAIT_7        (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */

+

+#define FMC_PATT_ATTHOLD_Pos      (16U)

+#define FMC_PATT_ATTHOLD_Msk      (0xFFUL << FMC_PATT_ATTHOLD_Pos)           /*!< 0x00FF0000 */

+#define FMC_PATT_ATTHOLD          FMC_PATT_ATTHOLD_Msk                       /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */

+#define FMC_PATT_ATTHOLD_0        (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */

+#define FMC_PATT_ATTHOLD_1        (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */

+#define FMC_PATT_ATTHOLD_2        (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */

+#define FMC_PATT_ATTHOLD_3        (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */

+#define FMC_PATT_ATTHOLD_4        (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */

+#define FMC_PATT_ATTHOLD_5        (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */

+#define FMC_PATT_ATTHOLD_6        (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */

+#define FMC_PATT_ATTHOLD_7        (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */

+

+#define FMC_PATT_ATTHIZ_Pos       (24U)

+#define FMC_PATT_ATTHIZ_Msk       (0xFFUL << FMC_PATT_ATTHIZ_Pos)            /*!< 0xFF000000 */

+#define FMC_PATT_ATTHIZ           FMC_PATT_ATTHIZ_Msk                        /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */

+#define FMC_PATT_ATTHIZ_0         (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */

+#define FMC_PATT_ATTHIZ_1         (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */

+#define FMC_PATT_ATTHIZ_2         (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */

+#define FMC_PATT_ATTHIZ_3         (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */

+#define FMC_PATT_ATTHIZ_4         (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */

+#define FMC_PATT_ATTHIZ_5         (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */

+#define FMC_PATT_ATTHIZ_6         (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */

+#define FMC_PATT_ATTHIZ_7         (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */

+

+/******************  Bit definition for FMC_ECCR3 register  ******************/

+#define FMC_ECCR3_ECC3_Pos         (0U)

+#define FMC_ECCR3_ECC3_Msk         (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)        /*!< 0xFFFFFFFF */

+#define FMC_ECCR3_ECC3             FMC_ECCR3_ECC3_Msk                          /*!<ECC result */

+

+/******************  Bit definition for FMC_SDCRx registers (x=1..4)  *********/

+#define FMC_SDCRx_NC_Pos           (0U)

+#define FMC_SDCRx_NC_Msk           (0x3UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000003 */

+#define FMC_SDCRx_NC               FMC_SDCRx_NC_Msk                            /*!<NC[1:0] bits (Number of column bits) */

+#define FMC_SDCRx_NC_0             (0x1UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000001 */

+#define FMC_SDCRx_NC_1             (0x2UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000002 */

+

+#define FMC_SDCRx_NR_Pos           (2U)

+#define FMC_SDCRx_NR_Msk           (0x3UL << FMC_SDCRx_NR_Pos)                 /*!< 0x0000000C */

+#define FMC_SDCRx_NR               FMC_SDCRx_NR_Msk                            /*!<NR[1:0] bits (Number of row bits) */

+#define FMC_SDCRx_NR_0             (0x1UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000004 */

+#define FMC_SDCRx_NR_1             (0x2UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000008 */

+

+#define FMC_SDCRx_MWID_Pos         (4U)

+#define FMC_SDCRx_MWID_Msk         (0x3UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000030 */

+#define FMC_SDCRx_MWID             FMC_SDCRx_MWID_Msk                          /*!<NR[1:0] bits (Number of row bits) */

+#define FMC_SDCRx_MWID_0           (0x1UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000010 */

+#define FMC_SDCRx_MWID_1           (0x2UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000020 */

+

+#define FMC_SDCRx_NB_Pos           (6U)

+#define FMC_SDCRx_NB_Msk           (0x1UL << FMC_SDCRx_NB_Pos)                 /*!< 0x00000040 */

+#define FMC_SDCRx_NB               FMC_SDCRx_NB_Msk                            /*!<Number of internal bank */

+

+#define FMC_SDCRx_CAS_Pos          (7U)

+#define FMC_SDCRx_CAS_Msk          (0x3UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000180 */

+#define FMC_SDCRx_CAS              FMC_SDCRx_CAS_Msk                           /*!<CAS[1:0] bits (CAS latency) */

+#define FMC_SDCRx_CAS_0            (0x1UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000080 */

+#define FMC_SDCRx_CAS_1            (0x2UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000100 */

+

+#define FMC_SDCRx_WP_Pos           (9U)

+#define FMC_SDCRx_WP_Msk           (0x1UL << FMC_SDCRx_WP_Pos)                 /*!< 0x00000200 */

+#define FMC_SDCRx_WP               FMC_SDCRx_WP_Msk                            /*!<Write protection */

+

+#define FMC_SDCRx_SDCLK_Pos        (10U)

+#define FMC_SDCRx_SDCLK_Msk        (0x3UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000C00 */

+#define FMC_SDCRx_SDCLK            FMC_SDCRx_SDCLK_Msk                         /*!<SDRAM clock configuration */

+#define FMC_SDCRx_SDCLK_0          (0x1UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000400 */

+#define FMC_SDCRx_SDCLK_1          (0x2UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000800 */

+

+#define FMC_SDCRx_RBURST_Pos       (12U)

+#define FMC_SDCRx_RBURST_Msk       (0x1UL << FMC_SDCRx_RBURST_Pos)             /*!< 0x00001000 */

+#define FMC_SDCRx_RBURST           FMC_SDCRx_RBURST_Msk                        /*!<Read burst */

+

+#define FMC_SDCRx_RPIPE_Pos        (13U)

+#define FMC_SDCRx_RPIPE_Msk        (0x3UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00006000 */

+#define FMC_SDCRx_RPIPE            FMC_SDCRx_RPIPE_Msk                         /*!<Write protection */

+#define FMC_SDCRx_RPIPE_0          (0x1UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00002000 */

+#define FMC_SDCRx_RPIPE_1          (0x2UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00004000 */

+

+/******************  Bit definition for FMC_SDTRx(1,2) register  ******************/

+#define FMC_SDTRx_TMRD_Pos         (0U)

+#define FMC_SDTRx_TMRD_Msk         (0xFUL << FMC_SDTRx_TMRD_Pos)               /*!< 0x0000000F */

+#define FMC_SDTRx_TMRD             FMC_SDTRx_TMRD_Msk                          /*!<TMRD[3:0] bits (Load mode register to active) */

+#define FMC_SDTRx_TMRD_0           (0x1UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000001 */

+#define FMC_SDTRx_TMRD_1           (0x2UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000002 */

+#define FMC_SDTRx_TMRD_2           (0x4UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000004 */

+#define FMC_SDTRx_TMRD_3           (0x8UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000008 */

+

+#define FMC_SDTRx_TXSR_Pos         (4U)

+#define FMC_SDTRx_TXSR_Msk         (0xFUL << FMC_SDTRx_TXSR_Pos)               /*!< 0x000000F0 */

+#define FMC_SDTRx_TXSR             FMC_SDTRx_TXSR_Msk                          /*!<TXSR[3:0] bits (Exit self refresh) */

+#define FMC_SDTRx_TXSR_0           (0x1UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000010 */

+#define FMC_SDTRx_TXSR_1           (0x2UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000020 */

+#define FMC_SDTRx_TXSR_2           (0x4UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000040 */

+#define FMC_SDTRx_TXSR_3           (0x8UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000080 */

+

+#define FMC_SDTRx_TRAS_Pos         (8U)

+#define FMC_SDTRx_TRAS_Msk         (0xFUL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000F00 */

+#define FMC_SDTRx_TRAS             FMC_SDTRx_TRAS_Msk                          /*!<TRAS[3:0] bits (Self refresh time) */

+#define FMC_SDTRx_TRAS_0           (0x1UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000100 */

+#define FMC_SDTRx_TRAS_1           (0x2UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000200 */

+#define FMC_SDTRx_TRAS_2           (0x4UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000400 */

+#define FMC_SDTRx_TRAS_3           (0x8UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000800 */

+

+#define FMC_SDTRx_TRC_Pos          (12U)

+#define FMC_SDTRx_TRC_Msk          (0xFUL << FMC_SDTRx_TRC_Pos)                /*!< 0x0000F000 */

+#define FMC_SDTRx_TRC              FMC_SDTRx_TRC_Msk                           /*!<TRC[2:0] bits (Row cycle delay) */

+#define FMC_SDTRx_TRC_0            (0x1UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00001000 */

+#define FMC_SDTRx_TRC_1            (0x2UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00002000 */

+#define FMC_SDTRx_TRC_2            (0x4UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00004000 */

+

+#define FMC_SDTRx_TWR_Pos          (16U)

+#define FMC_SDTRx_TWR_Msk          (0xFUL << FMC_SDTRx_TWR_Pos)                /*!< 0x000F0000 */

+#define FMC_SDTRx_TWR              FMC_SDTRx_TWR_Msk                           /*!<TRC[2:0] bits (Write recovery delay) */

+#define FMC_SDTRx_TWR_0            (0x1UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00010000 */

+#define FMC_SDTRx_TWR_1            (0x2UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00020000 */

+#define FMC_SDTRx_TWR_2            (0x4UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00040000 */

+

+#define FMC_SDTRx_TRP_Pos          (20U)

+#define FMC_SDTRx_TRP_Msk          (0xFUL << FMC_SDTRx_TRP_Pos)                /*!< 0x00F00000 */

+#define FMC_SDTRx_TRP              FMC_SDTRx_TRP_Msk                           /*!<TRP[2:0] bits (Row precharge delay) */

+#define FMC_SDTRx_TRP_0            (0x1UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00100000 */

+#define FMC_SDTRx_TRP_1            (0x2UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00200000 */

+#define FMC_SDTRx_TRP_2            (0x4UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00400000 */

+

+#define FMC_SDTRx_TRCD_Pos         (24U)

+#define FMC_SDTRx_TRCD_Msk         (0xFUL << FMC_SDTRx_TRCD_Pos)               /*!< 0x0F000000 */

+#define FMC_SDTRx_TRCD             FMC_SDTRx_TRCD_Msk                          /*!<TRP[2:0] bits (Row to column delay) */

+#define FMC_SDTRx_TRCD_0           (0x1UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x01000000 */

+#define FMC_SDTRx_TRCD_1           (0x2UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x02000000 */

+#define FMC_SDTRx_TRCD_2           (0x4UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x04000000 */

+

+/******************  Bit definition for FMC_SDCMR register  ******************/

+#define FMC_SDCMR_MODE_Pos         (0U)

+#define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */

+#define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */

+#define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */

+#define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */

+#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */

+

+#define FMC_SDCMR_CTB2_Pos         (3U)

+#define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */

+#define FMC_SDCMR_CTB2             FMC_SDCMR_CTB2_Msk                          /*!<Command target 2 */

+

+#define FMC_SDCMR_CTB1_Pos         (4U)

+#define FMC_SDCMR_CTB1_Msk         (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */

+#define FMC_SDCMR_CTB1             FMC_SDCMR_CTB1_Msk                          /*!<Command target 1 */

+

+#define FMC_SDCMR_NRFS_Pos         (5U)

+#define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */

+#define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!<NRFS[3:0] bits (Number of auto-refresh) */

+#define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000020 */

+#define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000040 */

+#define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000080 */

+#define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000100 */

+

+#define FMC_SDCMR_MRD_Pos          (9U)

+#define FMC_SDCMR_MRD_Msk          (0x1FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */

+#define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!<MRD[12:0] bits (Mode register definition) */

+

+/******************  Bit definition for FMC_SDRTR register  ******************/

+#define FMC_SDRTR_CRE_Pos          (0U)

+#define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */

+#define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!<Clear refresh error flag */

+

+#define FMC_SDRTR_COUNT_Pos        (1U)

+#define FMC_SDRTR_COUNT_Msk        (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */

+#define FMC_SDRTR_COUNT            FMC_SDRTR_COUNT_Msk                         /*!<COUNT[12:0] bits (Refresh timer count) */

+

+#define FMC_SDRTR_REIE_Pos         (14U)

+#define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */

+#define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!<RES interupt enable */

+

+/******************  Bit definition for FMC_SDSR register  ******************/

+#define FMC_SDSR_RE_Pos            (0U)

+#define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */

+#define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!<Refresh error flag */

+

+#define FMC_SDSR_MODES1_Pos        (1U)

+#define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */

+#define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!<MODES1[1:0]bits (Status mode for bank 1) */

+#define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000002 */

+#define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000004 */

+

+#define FMC_SDSR_MODES2_Pos        (3U)

+#define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */

+#define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!<MODES2[1:0]bits (Status mode for bank 2) */

+#define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000008 */

+#define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000010 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            General Purpose I/O                             */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bits definition for GPIO_MODER register  *****************/

+#define GPIO_MODER_MODE0_Pos           (0U)

+#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */

+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk

+#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */

+#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */

+

+#define GPIO_MODER_MODE1_Pos           (2U)

+#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */

+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk

+#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */

+#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */

+

+#define GPIO_MODER_MODE2_Pos           (4U)

+#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */

+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk

+#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */

+#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */

+

+#define GPIO_MODER_MODE3_Pos           (6U)

+#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */

+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk

+#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */

+#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */

+

+#define GPIO_MODER_MODE4_Pos           (8U)

+#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */

+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk

+#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */

+#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */

+

+#define GPIO_MODER_MODE5_Pos           (10U)

+#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */

+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk

+#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */

+#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */

+

+#define GPIO_MODER_MODE6_Pos           (12U)

+#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */

+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk

+#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */

+#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */

+

+#define GPIO_MODER_MODE7_Pos           (14U)

+#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */

+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk

+#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */

+#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */

+

+#define GPIO_MODER_MODE8_Pos           (16U)

+#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */

+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk

+#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */

+#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */

+

+#define GPIO_MODER_MODE9_Pos           (18U)

+#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */

+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk

+#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */

+#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */

+

+#define GPIO_MODER_MODE10_Pos          (20U)

+#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */

+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk

+#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */

+#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */

+

+#define GPIO_MODER_MODE11_Pos          (22U)

+#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */

+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk

+#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */

+#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */

+

+#define GPIO_MODER_MODE12_Pos          (24U)

+#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */

+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk

+#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */

+#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */

+

+#define GPIO_MODER_MODE13_Pos          (26U)

+#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */

+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk

+#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */

+#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */

+

+#define GPIO_MODER_MODE14_Pos          (28U)

+#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */

+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk

+#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */

+#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */

+

+#define GPIO_MODER_MODE15_Pos          (30U)

+#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */

+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk

+#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */

+#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_OTYPER register  ****************/

+#define GPIO_OTYPER_OT0_Pos            (0U)

+#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */

+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk

+#define GPIO_OTYPER_OT1_Pos            (1U)

+#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */

+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk

+#define GPIO_OTYPER_OT2_Pos            (2U)

+#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */

+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk

+#define GPIO_OTYPER_OT3_Pos            (3U)

+#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */

+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk

+#define GPIO_OTYPER_OT4_Pos            (4U)

+#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */

+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk

+#define GPIO_OTYPER_OT5_Pos            (5U)

+#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */

+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk

+#define GPIO_OTYPER_OT6_Pos            (6U)

+#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */

+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk

+#define GPIO_OTYPER_OT7_Pos            (7U)

+#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */

+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk

+#define GPIO_OTYPER_OT8_Pos            (8U)

+#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */

+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk

+#define GPIO_OTYPER_OT9_Pos            (9U)

+#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */

+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk

+#define GPIO_OTYPER_OT10_Pos           (10U)

+#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */

+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk

+#define GPIO_OTYPER_OT11_Pos           (11U)

+#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */

+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk

+#define GPIO_OTYPER_OT12_Pos           (12U)

+#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */

+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk

+#define GPIO_OTYPER_OT13_Pos           (13U)

+#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */

+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk

+#define GPIO_OTYPER_OT14_Pos           (14U)

+#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */

+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk

+#define GPIO_OTYPER_OT15_Pos           (15U)

+#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */

+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk

+

+/******************  Bits definition for GPIO_OSPEEDR register  ***************/

+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)

+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */

+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk

+#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */

+#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */

+

+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)

+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */

+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk

+#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */

+#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */

+

+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)

+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */

+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk

+#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */

+#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */

+

+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)

+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */

+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk

+#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */

+#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */

+

+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)

+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */

+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk

+#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */

+#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */

+

+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)

+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */

+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk

+#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */

+#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */

+

+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)

+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */

+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk

+#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */

+#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */

+

+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)

+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */

+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk

+#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */

+#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */

+

+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)

+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */

+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk

+#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */

+#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */

+

+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)

+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */

+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk

+#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */

+#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */

+

+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)

+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */

+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk

+#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */

+#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */

+

+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)

+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */

+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk

+#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */

+#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */

+

+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)

+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */

+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk

+#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */

+#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */

+

+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)

+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */

+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk

+#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */

+#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */

+

+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)

+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */

+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk

+#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */

+#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */

+

+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)

+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */

+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk

+#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */

+#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_PUPDR register  *****************/

+#define GPIO_PUPDR_PUPD0_Pos           (0U)

+#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */

+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk

+#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */

+#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */

+

+#define GPIO_PUPDR_PUPD1_Pos           (2U)

+#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */

+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk

+#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */

+#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */

+

+#define GPIO_PUPDR_PUPD2_Pos           (4U)

+#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */

+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk

+#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */

+#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */

+

+#define GPIO_PUPDR_PUPD3_Pos           (6U)

+#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */

+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk

+#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */

+#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */

+

+#define GPIO_PUPDR_PUPD4_Pos           (8U)

+#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */

+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk

+#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */

+#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */

+

+#define GPIO_PUPDR_PUPD5_Pos           (10U)

+#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */

+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk

+#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */

+#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */

+

+#define GPIO_PUPDR_PUPD6_Pos           (12U)

+#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */

+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk

+#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */

+#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */

+

+#define GPIO_PUPDR_PUPD7_Pos           (14U)

+#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */

+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk

+#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */

+#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */

+

+#define GPIO_PUPDR_PUPD8_Pos           (16U)

+#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */

+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk

+#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */

+#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */

+

+#define GPIO_PUPDR_PUPD9_Pos           (18U)

+#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */

+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk

+#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */

+#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */

+

+#define GPIO_PUPDR_PUPD10_Pos          (20U)

+#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */

+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk

+#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */

+#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */

+

+#define GPIO_PUPDR_PUPD11_Pos          (22U)

+#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */

+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk

+#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */

+#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */

+

+#define GPIO_PUPDR_PUPD12_Pos          (24U)

+#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */

+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk

+#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */

+#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */

+

+#define GPIO_PUPDR_PUPD13_Pos          (26U)

+#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */

+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk

+#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */

+#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */

+

+#define GPIO_PUPDR_PUPD14_Pos          (28U)

+#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */

+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk

+#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */

+#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */

+

+#define GPIO_PUPDR_PUPD15_Pos          (30U)

+#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */

+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk

+#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */

+#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_IDR register  *******************/

+#define GPIO_IDR_ID0_Pos               (0U)

+#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */

+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk

+#define GPIO_IDR_ID1_Pos               (1U)

+#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */

+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk

+#define GPIO_IDR_ID2_Pos               (2U)

+#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */

+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk

+#define GPIO_IDR_ID3_Pos               (3U)

+#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */

+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk

+#define GPIO_IDR_ID4_Pos               (4U)

+#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */

+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk

+#define GPIO_IDR_ID5_Pos               (5U)

+#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */

+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk

+#define GPIO_IDR_ID6_Pos               (6U)

+#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */

+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk

+#define GPIO_IDR_ID7_Pos               (7U)

+#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */

+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk

+#define GPIO_IDR_ID8_Pos               (8U)

+#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */

+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk

+#define GPIO_IDR_ID9_Pos               (9U)

+#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */

+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk

+#define GPIO_IDR_ID10_Pos              (10U)

+#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */

+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk

+#define GPIO_IDR_ID11_Pos              (11U)

+#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */

+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk

+#define GPIO_IDR_ID12_Pos              (12U)

+#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */

+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk

+#define GPIO_IDR_ID13_Pos              (13U)

+#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */

+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk

+#define GPIO_IDR_ID14_Pos              (14U)

+#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */

+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk

+#define GPIO_IDR_ID15_Pos              (15U)

+#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */

+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk

+

+/******************  Bits definition for GPIO_ODR register  *******************/

+#define GPIO_ODR_OD0_Pos               (0U)

+#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */

+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk

+#define GPIO_ODR_OD1_Pos               (1U)

+#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */

+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk

+#define GPIO_ODR_OD2_Pos               (2U)

+#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */

+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk

+#define GPIO_ODR_OD3_Pos               (3U)

+#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */

+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk

+#define GPIO_ODR_OD4_Pos               (4U)

+#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */

+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk

+#define GPIO_ODR_OD5_Pos               (5U)

+#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */

+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk

+#define GPIO_ODR_OD6_Pos               (6U)

+#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */

+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk

+#define GPIO_ODR_OD7_Pos               (7U)

+#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */

+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk

+#define GPIO_ODR_OD8_Pos               (8U)

+#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */

+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk

+#define GPIO_ODR_OD9_Pos               (9U)

+#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */

+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk

+#define GPIO_ODR_OD10_Pos              (10U)

+#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */

+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk

+#define GPIO_ODR_OD11_Pos              (11U)

+#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */

+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk

+#define GPIO_ODR_OD12_Pos              (12U)

+#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */

+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk

+#define GPIO_ODR_OD13_Pos              (13U)

+#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */

+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk

+#define GPIO_ODR_OD14_Pos              (14U)

+#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */

+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk

+#define GPIO_ODR_OD15_Pos              (15U)

+#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */

+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk

+

+/******************  Bits definition for GPIO_BSRR register  ******************/

+#define GPIO_BSRR_BS0_Pos              (0U)

+#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */

+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk

+#define GPIO_BSRR_BS1_Pos              (1U)

+#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */

+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk

+#define GPIO_BSRR_BS2_Pos              (2U)

+#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */

+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk

+#define GPIO_BSRR_BS3_Pos              (3U)

+#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */

+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk

+#define GPIO_BSRR_BS4_Pos              (4U)

+#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */

+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk

+#define GPIO_BSRR_BS5_Pos              (5U)

+#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */

+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk

+#define GPIO_BSRR_BS6_Pos              (6U)

+#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */

+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk

+#define GPIO_BSRR_BS7_Pos              (7U)

+#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */

+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk

+#define GPIO_BSRR_BS8_Pos              (8U)

+#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */

+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk

+#define GPIO_BSRR_BS9_Pos              (9U)

+#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */

+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk

+#define GPIO_BSRR_BS10_Pos             (10U)

+#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */

+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk

+#define GPIO_BSRR_BS11_Pos             (11U)

+#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */

+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk

+#define GPIO_BSRR_BS12_Pos             (12U)

+#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */

+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk

+#define GPIO_BSRR_BS13_Pos             (13U)

+#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */

+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk

+#define GPIO_BSRR_BS14_Pos             (14U)

+#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */

+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk

+#define GPIO_BSRR_BS15_Pos             (15U)

+#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */

+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk

+#define GPIO_BSRR_BR0_Pos              (16U)

+#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */

+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk

+#define GPIO_BSRR_BR1_Pos              (17U)

+#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */

+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk

+#define GPIO_BSRR_BR2_Pos              (18U)

+#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */

+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk

+#define GPIO_BSRR_BR3_Pos              (19U)

+#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */

+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk

+#define GPIO_BSRR_BR4_Pos              (20U)

+#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */

+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk

+#define GPIO_BSRR_BR5_Pos              (21U)

+#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */

+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk

+#define GPIO_BSRR_BR6_Pos              (22U)

+#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */

+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk

+#define GPIO_BSRR_BR7_Pos              (23U)

+#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */

+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk

+#define GPIO_BSRR_BR8_Pos              (24U)

+#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */

+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk

+#define GPIO_BSRR_BR9_Pos              (25U)

+#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */

+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk

+#define GPIO_BSRR_BR10_Pos             (26U)

+#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */

+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk

+#define GPIO_BSRR_BR11_Pos             (27U)

+#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */

+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk

+#define GPIO_BSRR_BR12_Pos             (28U)

+#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */

+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk

+#define GPIO_BSRR_BR13_Pos             (29U)

+#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */

+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk

+#define GPIO_BSRR_BR14_Pos             (30U)

+#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */

+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk

+#define GPIO_BSRR_BR15_Pos             (31U)

+#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */

+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk

+

+/****************** Bit definition for GPIO_LCKR register *********************/

+#define GPIO_LCKR_LCK0_Pos             (0U)

+#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */

+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk

+#define GPIO_LCKR_LCK1_Pos             (1U)

+#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */

+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk

+#define GPIO_LCKR_LCK2_Pos             (2U)

+#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */

+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk

+#define GPIO_LCKR_LCK3_Pos             (3U)

+#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */

+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk

+#define GPIO_LCKR_LCK4_Pos             (4U)

+#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */

+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk

+#define GPIO_LCKR_LCK5_Pos             (5U)

+#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */

+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk

+#define GPIO_LCKR_LCK6_Pos             (6U)

+#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */

+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk

+#define GPIO_LCKR_LCK7_Pos             (7U)

+#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */

+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk

+#define GPIO_LCKR_LCK8_Pos             (8U)

+#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */

+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk

+#define GPIO_LCKR_LCK9_Pos             (9U)

+#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */

+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk

+#define GPIO_LCKR_LCK10_Pos            (10U)

+#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */

+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk

+#define GPIO_LCKR_LCK11_Pos            (11U)

+#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */

+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk

+#define GPIO_LCKR_LCK12_Pos            (12U)

+#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */

+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk

+#define GPIO_LCKR_LCK13_Pos            (13U)

+#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */

+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk

+#define GPIO_LCKR_LCK14_Pos            (14U)

+#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */

+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk

+#define GPIO_LCKR_LCK15_Pos            (15U)

+#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */

+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk

+#define GPIO_LCKR_LCKK_Pos             (16U)

+#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */

+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk

+

+/****************** Bit definition for GPIO_AFRL register  ********************/

+#define GPIO_AFRL_AFSEL0_Pos           (0U)

+#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */

+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk

+#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */

+#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */

+#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */

+#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */

+#define GPIO_AFRL_AFSEL1_Pos           (4U)

+#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */

+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk

+#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */

+#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */

+#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */

+#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */

+#define GPIO_AFRL_AFSEL2_Pos           (8U)

+#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */

+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk

+#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */

+#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */

+#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */

+#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */

+#define GPIO_AFRL_AFSEL3_Pos           (12U)

+#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */

+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk

+#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */

+#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */

+#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */

+#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */

+#define GPIO_AFRL_AFSEL4_Pos           (16U)

+#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */

+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk

+#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */

+#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */

+#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */

+#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */

+#define GPIO_AFRL_AFSEL5_Pos           (20U)

+#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */

+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk

+#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */

+#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */

+#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */

+#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */

+#define GPIO_AFRL_AFSEL6_Pos           (24U)

+#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */

+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk

+#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */

+#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */

+#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */

+#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */

+#define GPIO_AFRL_AFSEL7_Pos           (28U)

+#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */

+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk

+#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */

+#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */

+#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */

+#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */

+

+/* Legacy defines */

+#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0

+#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1

+#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2

+#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3

+#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4

+#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5

+#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6

+#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7

+

+/****************** Bit definition for GPIO_AFRH register  ********************/

+#define GPIO_AFRH_AFSEL8_Pos           (0U)

+#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */

+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk

+#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */

+#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */

+#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */

+#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */

+#define GPIO_AFRH_AFSEL9_Pos           (4U)

+#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */

+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk

+#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */

+#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */

+#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */

+#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */

+#define GPIO_AFRH_AFSEL10_Pos          (8U)

+#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */

+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk

+#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */

+#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */

+#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */

+#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */

+#define GPIO_AFRH_AFSEL11_Pos          (12U)

+#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */

+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk

+#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */

+#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */

+#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */

+#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */

+#define GPIO_AFRH_AFSEL12_Pos          (16U)

+#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */

+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk

+#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */

+#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */

+#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */

+#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */

+#define GPIO_AFRH_AFSEL13_Pos          (20U)

+#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */

+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk

+#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */

+#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */

+#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */

+#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */

+#define GPIO_AFRH_AFSEL14_Pos          (24U)

+#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */

+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk

+#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */

+#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */

+#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */

+#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */

+#define GPIO_AFRH_AFSEL15_Pos          (28U)

+#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */

+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk

+#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */

+#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */

+#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */

+#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */

+

+/* Legacy defines */

+#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8

+#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9

+#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10

+#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11

+#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12

+#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13

+#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14

+#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15

+

+/******************************************************************************/

+/*                                                                            */

+/*                        HSEM HW Semaphore                                   */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for HSEM_R register  ********************/

+#define HSEM_R_PROCID_Pos         (0U)

+#define HSEM_R_PROCID_Msk         (0xFFUL << HSEM_R_PROCID_Pos)                /*!< 0x000000FF */

+#define HSEM_R_PROCID             HSEM_R_PROCID_Msk                            /*!<Semaphore ProcessID */

+#define HSEM_R_COREID_Pos         (8U)

+#define HSEM_R_COREID_Msk         (0xFFUL << HSEM_R_COREID_Pos)                /*!< 0x0000FF00 */

+#define HSEM_R_COREID             HSEM_R_COREID_Msk                            /*!<Semaphore CoreID.   */

+#define HSEM_R_LOCK_Pos           (31U)

+#define HSEM_R_LOCK_Msk           (0x1UL << HSEM_R_LOCK_Pos)                   /*!< 0x80000000 */

+#define HSEM_R_LOCK               HSEM_R_LOCK_Msk                              /*!<Lock indication.    */

+

+/********************  Bit definition for HSEM_RLR register  ******************/

+#define HSEM_RLR_PROCID_Pos       (0U)

+#define HSEM_RLR_PROCID_Msk       (0xFFUL << HSEM_RLR_PROCID_Pos)              /*!< 0x000000FF */

+#define HSEM_RLR_PROCID           HSEM_RLR_PROCID_Msk                          /*!<Semaphore ProcessID */

+#define HSEM_RLR_COREID_Pos       (8U)

+#define HSEM_RLR_COREID_Msk       (0xFFUL << HSEM_RLR_COREID_Pos)              /*!< 0x0000FF00 */

+#define HSEM_RLR_COREID           HSEM_RLR_COREID_Msk                          /*!<Semaphore CoreID.   */

+#define HSEM_RLR_LOCK_Pos         (31U)

+#define HSEM_RLR_LOCK_Msk         (0x1UL << HSEM_RLR_LOCK_Pos)                 /*!< 0x80000000 */

+#define HSEM_RLR_LOCK             HSEM_RLR_LOCK_Msk                            /*!<Lock indication.    */

+

+/********************  Bit definition for HSEM_C1IER register  *****************/

+#define HSEM_C1IER_ISE0_Pos       (0U)

+#define HSEM_C1IER_ISE0_Msk       (0x1UL << HSEM_C1IER_ISE0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1IER_ISE0           HSEM_C1IER_ISE0_Msk                          /*!<semaphore 0 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE1_Pos       (1U)

+#define HSEM_C1IER_ISE1_Msk       (0x1UL << HSEM_C1IER_ISE1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1IER_ISE1           HSEM_C1IER_ISE1_Msk                          /*!<semaphore 1 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE2_Pos       (2U)

+#define HSEM_C1IER_ISE2_Msk       (0x1UL << HSEM_C1IER_ISE2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1IER_ISE2           HSEM_C1IER_ISE2_Msk                          /*!<semaphore 2 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE3_Pos       (3U)

+#define HSEM_C1IER_ISE3_Msk       (0x1UL << HSEM_C1IER_ISE3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1IER_ISE3           HSEM_C1IER_ISE3_Msk                          /*!<semaphore 3 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE4_Pos       (4U)

+#define HSEM_C1IER_ISE4_Msk       (0x1UL << HSEM_C1IER_ISE4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1IER_ISE4           HSEM_C1IER_ISE4_Msk                          /*!<semaphore 4 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE5_Pos       (5U)

+#define HSEM_C1IER_ISE5_Msk       (0x1UL << HSEM_C1IER_ISE5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1IER_ISE5           HSEM_C1IER_ISE5_Msk                          /*!<semaphore 5 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE6_Pos       (6U)

+#define HSEM_C1IER_ISE6_Msk       (0x1UL << HSEM_C1IER_ISE6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1IER_ISE6           HSEM_C1IER_ISE6_Msk                          /*!<semaphore 6 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE7_Pos       (7U)

+#define HSEM_C1IER_ISE7_Msk       (0x1UL << HSEM_C1IER_ISE7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1IER_ISE7           HSEM_C1IER_ISE7_Msk                          /*!<semaphore 7 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE8_Pos       (8U)

+#define HSEM_C1IER_ISE8_Msk       (0x1UL << HSEM_C1IER_ISE8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1IER_ISE8           HSEM_C1IER_ISE8_Msk                          /*!<semaphore 8 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE9_Pos       (9U)

+#define HSEM_C1IER_ISE9_Msk       (0x1UL << HSEM_C1IER_ISE9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1IER_ISE9           HSEM_C1IER_ISE9_Msk                          /*!<semaphore 9 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE10_Pos      (10U)

+#define HSEM_C1IER_ISE10_Msk      (0x1UL << HSEM_C1IER_ISE10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1IER_ISE10          HSEM_C1IER_ISE10_Msk                         /*!<semaphore 10 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE11_Pos      (11U)

+#define HSEM_C1IER_ISE11_Msk      (0x1UL << HSEM_C1IER_ISE11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1IER_ISE11          HSEM_C1IER_ISE11_Msk                         /*!<semaphore 11 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE12_Pos      (12U)

+#define HSEM_C1IER_ISE12_Msk      (0x1UL << HSEM_C1IER_ISE12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1IER_ISE12          HSEM_C1IER_ISE12_Msk                         /*!<semaphore 12 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE13_Pos      (13U)

+#define HSEM_C1IER_ISE13_Msk      (0x1UL << HSEM_C1IER_ISE13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1IER_ISE13          HSEM_C1IER_ISE13_Msk                         /*!<semaphore 13 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE14_Pos      (14U)

+#define HSEM_C1IER_ISE14_Msk      (0x1UL << HSEM_C1IER_ISE14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1IER_ISE14          HSEM_C1IER_ISE14_Msk                         /*!<semaphore 14 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE15_Pos      (15U)

+#define HSEM_C1IER_ISE15_Msk      (0x1UL << HSEM_C1IER_ISE15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1IER_ISE15          HSEM_C1IER_ISE15_Msk                         /*!<semaphore 15 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE16_Pos      (16U)

+#define HSEM_C1IER_ISE16_Msk      (0x1UL << HSEM_C1IER_ISE16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1IER_ISE16          HSEM_C1IER_ISE16_Msk                         /*!<semaphore 16 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE17_Pos      (17U)

+#define HSEM_C1IER_ISE17_Msk      (0x1UL << HSEM_C1IER_ISE17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1IER_ISE17          HSEM_C1IER_ISE17_Msk                         /*!<semaphore 17 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE18_Pos      (18U)

+#define HSEM_C1IER_ISE18_Msk      (0x1UL << HSEM_C1IER_ISE18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1IER_ISE18          HSEM_C1IER_ISE18_Msk                         /*!<semaphore 18 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE19_Pos      (19U)

+#define HSEM_C1IER_ISE19_Msk      (0x1UL << HSEM_C1IER_ISE19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1IER_ISE19          HSEM_C1IER_ISE19_Msk                         /*!<semaphore 19 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE20_Pos      (20U)

+#define HSEM_C1IER_ISE20_Msk      (0x1UL << HSEM_C1IER_ISE20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1IER_ISE20          HSEM_C1IER_ISE20_Msk                         /*!<semaphore 20 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE21_Pos      (21U)

+#define HSEM_C1IER_ISE21_Msk      (0x1UL << HSEM_C1IER_ISE21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1IER_ISE21          HSEM_C1IER_ISE21_Msk                         /*!<semaphore 21 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE22_Pos      (22U)

+#define HSEM_C1IER_ISE22_Msk      (0x1UL << HSEM_C1IER_ISE22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1IER_ISE22          HSEM_C1IER_ISE22_Msk                         /*!<semaphore 22 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE23_Pos      (23U)

+#define HSEM_C1IER_ISE23_Msk      (0x1UL << HSEM_C1IER_ISE23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1IER_ISE23          HSEM_C1IER_ISE23_Msk                         /*!<semaphore 23 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE24_Pos      (24U)

+#define HSEM_C1IER_ISE24_Msk      (0x1UL << HSEM_C1IER_ISE24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1IER_ISE24          HSEM_C1IER_ISE24_Msk                         /*!<semaphore 24 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE25_Pos      (25U)

+#define HSEM_C1IER_ISE25_Msk      (0x1UL << HSEM_C1IER_ISE25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1IER_ISE25          HSEM_C1IER_ISE25_Msk                         /*!<semaphore 25 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE26_Pos      (26U)

+#define HSEM_C1IER_ISE26_Msk      (0x1UL << HSEM_C1IER_ISE26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1IER_ISE26          HSEM_C1IER_ISE26_Msk                         /*!<semaphore 26 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE27_Pos      (27U)

+#define HSEM_C1IER_ISE27_Msk      (0x1UL << HSEM_C1IER_ISE27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1IER_ISE27          HSEM_C1IER_ISE27_Msk                         /*!<semaphore 27 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE28_Pos      (28U)

+#define HSEM_C1IER_ISE28_Msk      (0x1UL << HSEM_C1IER_ISE28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1IER_ISE28          HSEM_C1IER_ISE28_Msk                         /*!<semaphore 28 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE29_Pos      (29U)

+#define HSEM_C1IER_ISE29_Msk      (0x1UL << HSEM_C1IER_ISE29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1IER_ISE29          HSEM_C1IER_ISE29_Msk                         /*!<semaphore 29 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE30_Pos      (30U)

+#define HSEM_C1IER_ISE30_Msk      (0x1UL << HSEM_C1IER_ISE30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1IER_ISE30          HSEM_C1IER_ISE30_Msk                         /*!<semaphore 30 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE31_Pos      (31U)

+#define HSEM_C1IER_ISE31_Msk      (0x1UL << HSEM_C1IER_ISE31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1IER_ISE31          HSEM_C1IER_ISE31_Msk                         /*!<semaphore 31 interrupt 0 enable bit. */

+

+/********************  Bit definition for HSEM_C1ICR register  *****************/

+#define HSEM_C1ICR_ISC0_Pos       (0U)

+#define HSEM_C1ICR_ISC0_Msk       (0x1UL << HSEM_C1ICR_ISC0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1ICR_ISC0           HSEM_C1ICR_ISC0_Msk                          /*!<semaphore 0 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC1_Pos       (1U)

+#define HSEM_C1ICR_ISC1_Msk       (0x1UL << HSEM_C1ICR_ISC1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1ICR_ISC1           HSEM_C1ICR_ISC1_Msk                          /*!<semaphore 1 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC2_Pos       (2U)

+#define HSEM_C1ICR_ISC2_Msk       (0x1UL << HSEM_C1ICR_ISC2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1ICR_ISC2           HSEM_C1ICR_ISC2_Msk                          /*!<semaphore 2 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC3_Pos       (3U)

+#define HSEM_C1ICR_ISC3_Msk       (0x1UL << HSEM_C1ICR_ISC3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1ICR_ISC3           HSEM_C1ICR_ISC3_Msk                          /*!<semaphore 3 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC4_Pos       (4U)

+#define HSEM_C1ICR_ISC4_Msk       (0x1UL << HSEM_C1ICR_ISC4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1ICR_ISC4           HSEM_C1ICR_ISC4_Msk                          /*!<semaphore 4 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC5_Pos       (5U)

+#define HSEM_C1ICR_ISC5_Msk       (0x1UL << HSEM_C1ICR_ISC5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1ICR_ISC5           HSEM_C1ICR_ISC5_Msk                          /*!<semaphore 5 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC6_Pos       (6U)

+#define HSEM_C1ICR_ISC6_Msk       (0x1UL << HSEM_C1ICR_ISC6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1ICR_ISC6           HSEM_C1ICR_ISC6_Msk                          /*!<semaphore 6 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC7_Pos       (7U)

+#define HSEM_C1ICR_ISC7_Msk       (0x1UL << HSEM_C1ICR_ISC7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1ICR_ISC7           HSEM_C1ICR_ISC7_Msk                          /*!<semaphore 7 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC8_Pos       (8U)

+#define HSEM_C1ICR_ISC8_Msk       (0x1UL << HSEM_C1ICR_ISC8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1ICR_ISC8           HSEM_C1ICR_ISC8_Msk                          /*!<semaphore 8 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC9_Pos       (9U)

+#define HSEM_C1ICR_ISC9_Msk       (0x1UL << HSEM_C1ICR_ISC9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1ICR_ISC9           HSEM_C1ICR_ISC9_Msk                          /*!<semaphore 9 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC10_Pos      (10U)

+#define HSEM_C1ICR_ISC10_Msk      (0x1UL << HSEM_C1ICR_ISC10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1ICR_ISC10          HSEM_C1ICR_ISC10_Msk                         /*!<semaphore 10 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC11_Pos      (11U)

+#define HSEM_C1ICR_ISC11_Msk      (0x1UL << HSEM_C1ICR_ISC11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1ICR_ISC11          HSEM_C1ICR_ISC11_Msk                         /*!<semaphore 11 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC12_Pos      (12U)

+#define HSEM_C1ICR_ISC12_Msk      (0x1UL << HSEM_C1ICR_ISC12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1ICR_ISC12          HSEM_C1ICR_ISC12_Msk                         /*!<semaphore 12 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC13_Pos      (13U)

+#define HSEM_C1ICR_ISC13_Msk      (0x1UL << HSEM_C1ICR_ISC13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1ICR_ISC13          HSEM_C1ICR_ISC13_Msk                         /*!<semaphore 13 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC14_Pos      (14U)

+#define HSEM_C1ICR_ISC14_Msk      (0x1UL << HSEM_C1ICR_ISC14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1ICR_ISC14          HSEM_C1ICR_ISC14_Msk                         /*!<semaphore 14 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC15_Pos      (15U)

+#define HSEM_C1ICR_ISC15_Msk      (0x1UL << HSEM_C1ICR_ISC15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1ICR_ISC15          HSEM_C1ICR_ISC15_Msk                         /*!<semaphore 15 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC16_Pos      (16U)

+#define HSEM_C1ICR_ISC16_Msk      (0x1UL << HSEM_C1ICR_ISC16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1ICR_ISC16          HSEM_C1ICR_ISC16_Msk                         /*!<semaphore 16 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC17_Pos      (17U)

+#define HSEM_C1ICR_ISC17_Msk      (0x1UL << HSEM_C1ICR_ISC17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1ICR_ISC17          HSEM_C1ICR_ISC17_Msk                         /*!<semaphore 17 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC18_Pos      (18U)

+#define HSEM_C1ICR_ISC18_Msk      (0x1UL << HSEM_C1ICR_ISC18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1ICR_ISC18          HSEM_C1ICR_ISC18_Msk                         /*!<semaphore 18 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC19_Pos      (19U)

+#define HSEM_C1ICR_ISC19_Msk      (0x1UL << HSEM_C1ICR_ISC19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1ICR_ISC19          HSEM_C1ICR_ISC19_Msk                         /*!<semaphore 19 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC20_Pos      (20U)

+#define HSEM_C1ICR_ISC20_Msk      (0x1UL << HSEM_C1ICR_ISC20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1ICR_ISC20          HSEM_C1ICR_ISC20_Msk                         /*!<semaphore 20 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC21_Pos      (21U)

+#define HSEM_C1ICR_ISC21_Msk      (0x1UL << HSEM_C1ICR_ISC21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1ICR_ISC21          HSEM_C1ICR_ISC21_Msk                         /*!<semaphore 21 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC22_Pos      (22U)

+#define HSEM_C1ICR_ISC22_Msk      (0x1UL << HSEM_C1ICR_ISC22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1ICR_ISC22          HSEM_C1ICR_ISC22_Msk                         /*!<semaphore 22 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC23_Pos      (23U)

+#define HSEM_C1ICR_ISC23_Msk      (0x1UL << HSEM_C1ICR_ISC23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1ICR_ISC23          HSEM_C1ICR_ISC23_Msk                         /*!<semaphore 23 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC24_Pos      (24U)

+#define HSEM_C1ICR_ISC24_Msk      (0x1UL << HSEM_C1ICR_ISC24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1ICR_ISC24          HSEM_C1ICR_ISC24_Msk                         /*!<semaphore 24 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC25_Pos      (25U)

+#define HSEM_C1ICR_ISC25_Msk      (0x1UL << HSEM_C1ICR_ISC25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1ICR_ISC25          HSEM_C1ICR_ISC25_Msk                         /*!<semaphore 25 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC26_Pos      (26U)

+#define HSEM_C1ICR_ISC26_Msk      (0x1UL << HSEM_C1ICR_ISC26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1ICR_ISC26          HSEM_C1ICR_ISC26_Msk                         /*!<semaphore 26 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC27_Pos      (27U)

+#define HSEM_C1ICR_ISC27_Msk      (0x1UL << HSEM_C1ICR_ISC27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1ICR_ISC27          HSEM_C1ICR_ISC27_Msk                         /*!<semaphore 27 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC28_Pos      (28U)

+#define HSEM_C1ICR_ISC28_Msk      (0x1UL << HSEM_C1ICR_ISC28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1ICR_ISC28          HSEM_C1ICR_ISC28_Msk                         /*!<semaphore 28 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC29_Pos      (29U)

+#define HSEM_C1ICR_ISC29_Msk      (0x1UL << HSEM_C1ICR_ISC29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1ICR_ISC29          HSEM_C1ICR_ISC29_Msk                         /*!<semaphore 29 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC30_Pos      (30U)

+#define HSEM_C1ICR_ISC30_Msk      (0x1UL << HSEM_C1ICR_ISC30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1ICR_ISC30          HSEM_C1ICR_ISC30_Msk                         /*!<semaphore 30 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC31_Pos      (31U)

+#define HSEM_C1ICR_ISC31_Msk      (0x1UL << HSEM_C1ICR_ISC31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1ICR_ISC31          HSEM_C1ICR_ISC31_Msk                         /*!<semaphore 31 interrupt 0 clear bit. */

+

+/********************  Bit definition for HSEM_C1ISR register  *****************/

+#define HSEM_C1ISR_ISF0_Pos       (0U)

+#define HSEM_C1ISR_ISF0_Msk       (0x1UL << HSEM_C1ISR_ISF0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1ISR_ISF0           HSEM_C1ISR_ISF0_Msk                          /*!<semaphore 0 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF1_Pos       (1U)

+#define HSEM_C1ISR_ISF1_Msk       (0x1UL << HSEM_C1ISR_ISF1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1ISR_ISF1           HSEM_C1ISR_ISF1_Msk                          /*!<semaphore 1 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF2_Pos       (2U)

+#define HSEM_C1ISR_ISF2_Msk       (0x1UL << HSEM_C1ISR_ISF2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1ISR_ISF2           HSEM_C1ISR_ISF2_Msk                          /*!<semaphore 2 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF3_Pos       (3U)

+#define HSEM_C1ISR_ISF3_Msk       (0x1UL << HSEM_C1ISR_ISF3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1ISR_ISF3           HSEM_C1ISR_ISF3_Msk                          /*!<semaphore 3 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF4_Pos       (4U)

+#define HSEM_C1ISR_ISF4_Msk       (0x1UL << HSEM_C1ISR_ISF4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1ISR_ISF4           HSEM_C1ISR_ISF4_Msk                          /*!<semaphore 4 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF5_Pos       (5U)

+#define HSEM_C1ISR_ISF5_Msk       (0x1UL << HSEM_C1ISR_ISF5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1ISR_ISF5           HSEM_C1ISR_ISF5_Msk                          /*!<semaphore 5 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF6_Pos       (6U)

+#define HSEM_C1ISR_ISF6_Msk       (0x1UL << HSEM_C1ISR_ISF6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1ISR_ISF6           HSEM_C1ISR_ISF6_Msk                          /*!<semaphore 6 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF7_Pos       (7U)

+#define HSEM_C1ISR_ISF7_Msk       (0x1UL << HSEM_C1ISR_ISF7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1ISR_ISF7           HSEM_C1ISR_ISF7_Msk                          /*!<semaphore 7 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF8_Pos       (8U)

+#define HSEM_C1ISR_ISF8_Msk       (0x1UL << HSEM_C1ISR_ISF8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1ISR_ISF8           HSEM_C1ISR_ISF8_Msk                          /*!<semaphore 8 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF9_Pos       (9U)

+#define HSEM_C1ISR_ISF9_Msk       (0x1UL << HSEM_C1ISR_ISF9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1ISR_ISF9           HSEM_C1ISR_ISF9_Msk                          /*!<semaphore 9 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF10_Pos      (10U)

+#define HSEM_C1ISR_ISF10_Msk      (0x1UL << HSEM_C1ISR_ISF10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1ISR_ISF10          HSEM_C1ISR_ISF10_Msk                         /*!<semaphore 10 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF11_Pos      (11U)

+#define HSEM_C1ISR_ISF11_Msk      (0x1UL << HSEM_C1ISR_ISF11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1ISR_ISF11          HSEM_C1ISR_ISF11_Msk                         /*!<semaphore 11 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF12_Pos      (12U)

+#define HSEM_C1ISR_ISF12_Msk      (0x1UL << HSEM_C1ISR_ISF12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1ISR_ISF12          HSEM_C1ISR_ISF12_Msk                         /*!<semaphore 12 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF13_Pos      (13U)

+#define HSEM_C1ISR_ISF13_Msk      (0x1UL << HSEM_C1ISR_ISF13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1ISR_ISF13          HSEM_C1ISR_ISF13_Msk                         /*!<semaphore 13 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF14_Pos      (14U)

+#define HSEM_C1ISR_ISF14_Msk      (0x1UL << HSEM_C1ISR_ISF14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1ISR_ISF14          HSEM_C1ISR_ISF14_Msk                         /*!<semaphore 14 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF15_Pos      (15U)

+#define HSEM_C1ISR_ISF15_Msk      (0x1UL << HSEM_C1ISR_ISF15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1ISR_ISF15          HSEM_C1ISR_ISF15_Msk                         /*!<semaphore 15 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF16_Pos      (16U)

+#define HSEM_C1ISR_ISF16_Msk      (0x1UL << HSEM_C1ISR_ISF16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1ISR_ISF16          HSEM_C1ISR_ISF16_Msk                         /*!<semaphore 16 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF17_Pos      (17U)

+#define HSEM_C1ISR_ISF17_Msk      (0x1UL << HSEM_C1ISR_ISF17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1ISR_ISF17          HSEM_C1ISR_ISF17_Msk                         /*!<semaphore 17 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF18_Pos      (18U)

+#define HSEM_C1ISR_ISF18_Msk      (0x1UL << HSEM_C1ISR_ISF18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1ISR_ISF18          HSEM_C1ISR_ISF18_Msk                         /*!<semaphore 18 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF19_Pos      (19U)

+#define HSEM_C1ISR_ISF19_Msk      (0x1UL << HSEM_C1ISR_ISF19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1ISR_ISF19          HSEM_C1ISR_ISF19_Msk                         /*!<semaphore 19 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF20_Pos      (20U)

+#define HSEM_C1ISR_ISF20_Msk      (0x1UL << HSEM_C1ISR_ISF20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1ISR_ISF20          HSEM_C1ISR_ISF20_Msk                         /*!<semaphore 20 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF21_Pos      (21U)

+#define HSEM_C1ISR_ISF21_Msk      (0x1UL << HSEM_C1ISR_ISF21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1ISR_ISF21          HSEM_C1ISR_ISF21_Msk                         /*!<semaphore 21 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF22_Pos      (22U)

+#define HSEM_C1ISR_ISF22_Msk      (0x1UL << HSEM_C1ISR_ISF22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1ISR_ISF22          HSEM_C1ISR_ISF22_Msk                         /*!<semaphore 22 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF23_Pos      (23U)

+#define HSEM_C1ISR_ISF23_Msk      (0x1UL << HSEM_C1ISR_ISF23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1ISR_ISF23          HSEM_C1ISR_ISF23_Msk                         /*!<semaphore 23 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF24_Pos      (24U)

+#define HSEM_C1ISR_ISF24_Msk      (0x1UL << HSEM_C1ISR_ISF24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1ISR_ISF24          HSEM_C1ISR_ISF24_Msk                         /*!<semaphore 24 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF25_Pos      (25U)

+#define HSEM_C1ISR_ISF25_Msk      (0x1UL << HSEM_C1ISR_ISF25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1ISR_ISF25          HSEM_C1ISR_ISF25_Msk                         /*!<semaphore 25 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF26_Pos      (26U)

+#define HSEM_C1ISR_ISF26_Msk      (0x1UL << HSEM_C1ISR_ISF26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1ISR_ISF26          HSEM_C1ISR_ISF26_Msk                         /*!<semaphore 26 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF27_Pos      (27U)

+#define HSEM_C1ISR_ISF27_Msk      (0x1UL << HSEM_C1ISR_ISF27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1ISR_ISF27          HSEM_C1ISR_ISF27_Msk                         /*!<semaphore 27 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF28_Pos      (28U)

+#define HSEM_C1ISR_ISF28_Msk      (0x1UL << HSEM_C1ISR_ISF28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1ISR_ISF28          HSEM_C1ISR_ISF28_Msk                         /*!<semaphore 28 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF29_Pos      (29U)

+#define HSEM_C1ISR_ISF29_Msk      (0x1UL << HSEM_C1ISR_ISF29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1ISR_ISF29          HSEM_C1ISR_ISF29_Msk                         /*!<semaphore 29 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF30_Pos      (30U)

+#define HSEM_C1ISR_ISF30_Msk      (0x1UL << HSEM_C1ISR_ISF30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1ISR_ISF30          HSEM_C1ISR_ISF30_Msk                         /*!<semaphore 30 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF31_Pos      (31U)

+#define HSEM_C1ISR_ISF31_Msk      (0x1UL << HSEM_C1ISR_ISF31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1ISR_ISF31          HSEM_C1ISR_ISF31_Msk                         /*!<semaphore 31 interrupt 0 status bit. */

+

+/********************  Bit definition for HSEM_C1MISR register  *****************/

+#define HSEM_C1MISR_MISF0_Pos     (0U)

+#define HSEM_C1MISR_MISF0_Msk     (0x1UL << HSEM_C1MISR_MISF0_Pos)             /*!< 0x00000001 */

+#define HSEM_C1MISR_MISF0         HSEM_C1MISR_MISF0_Msk                        /*!<semaphore 0 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF1_Pos     (1U)

+#define HSEM_C1MISR_MISF1_Msk     (0x1UL << HSEM_C1MISR_MISF1_Pos)             /*!< 0x00000002 */

+#define HSEM_C1MISR_MISF1         HSEM_C1MISR_MISF1_Msk                        /*!<semaphore 1 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF2_Pos     (2U)

+#define HSEM_C1MISR_MISF2_Msk     (0x1UL << HSEM_C1MISR_MISF2_Pos)             /*!< 0x00000004 */

+#define HSEM_C1MISR_MISF2         HSEM_C1MISR_MISF2_Msk                        /*!<semaphore 2 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF3_Pos     (3U)

+#define HSEM_C1MISR_MISF3_Msk     (0x1UL << HSEM_C1MISR_MISF3_Pos)             /*!< 0x00000008 */

+#define HSEM_C1MISR_MISF3         HSEM_C1MISR_MISF3_Msk                        /*!<semaphore 3 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF4_Pos     (4U)

+#define HSEM_C1MISR_MISF4_Msk     (0x1UL << HSEM_C1MISR_MISF4_Pos)             /*!< 0x00000010 */

+#define HSEM_C1MISR_MISF4         HSEM_C1MISR_MISF4_Msk                        /*!<semaphore 4 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF5_Pos     (5U)

+#define HSEM_C1MISR_MISF5_Msk     (0x1UL << HSEM_C1MISR_MISF5_Pos)             /*!< 0x00000020 */

+#define HSEM_C1MISR_MISF5         HSEM_C1MISR_MISF5_Msk                        /*!<semaphore 5 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF6_Pos     (6U)

+#define HSEM_C1MISR_MISF6_Msk     (0x1UL << HSEM_C1MISR_MISF6_Pos)             /*!< 0x00000040 */

+#define HSEM_C1MISR_MISF6         HSEM_C1MISR_MISF6_Msk                        /*!<semaphore 6 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF7_Pos     (7U)

+#define HSEM_C1MISR_MISF7_Msk     (0x1UL << HSEM_C1MISR_MISF7_Pos)             /*!< 0x00000080 */

+#define HSEM_C1MISR_MISF7         HSEM_C1MISR_MISF7_Msk                        /*!<semaphore 7 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF8_Pos     (8U)

+#define HSEM_C1MISR_MISF8_Msk     (0x1UL << HSEM_C1MISR_MISF8_Pos)             /*!< 0x00000100 */

+#define HSEM_C1MISR_MISF8         HSEM_C1MISR_MISF8_Msk                        /*!<semaphore 8 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF9_Pos     (9U)

+#define HSEM_C1MISR_MISF9_Msk     (0x1UL << HSEM_C1MISR_MISF9_Pos)             /*!< 0x00000200 */

+#define HSEM_C1MISR_MISF9         HSEM_C1MISR_MISF9_Msk                        /*!<semaphore 9 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF10_Pos    (10U)

+#define HSEM_C1MISR_MISF10_Msk    (0x1UL << HSEM_C1MISR_MISF10_Pos)            /*!< 0x00000400 */

+#define HSEM_C1MISR_MISF10        HSEM_C1MISR_MISF10_Msk                       /*!<semaphore 10 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF11_Pos    (11U)

+#define HSEM_C1MISR_MISF11_Msk    (0x1UL << HSEM_C1MISR_MISF11_Pos)            /*!< 0x00000800 */

+#define HSEM_C1MISR_MISF11        HSEM_C1MISR_MISF11_Msk                       /*!<semaphore 11 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF12_Pos    (12U)

+#define HSEM_C1MISR_MISF12_Msk    (0x1UL << HSEM_C1MISR_MISF12_Pos)            /*!< 0x00001000 */

+#define HSEM_C1MISR_MISF12        HSEM_C1MISR_MISF12_Msk                       /*!<semaphore 12 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF13_Pos    (13U)

+#define HSEM_C1MISR_MISF13_Msk    (0x1UL << HSEM_C1MISR_MISF13_Pos)            /*!< 0x00002000 */

+#define HSEM_C1MISR_MISF13        HSEM_C1MISR_MISF13_Msk                       /*!<semaphore 13 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF14_Pos    (14U)

+#define HSEM_C1MISR_MISF14_Msk    (0x1UL << HSEM_C1MISR_MISF14_Pos)            /*!< 0x00004000 */

+#define HSEM_C1MISR_MISF14        HSEM_C1MISR_MISF14_Msk                       /*!<semaphore 14 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF15_Pos    (15U)

+#define HSEM_C1MISR_MISF15_Msk    (0x1UL << HSEM_C1MISR_MISF15_Pos)            /*!< 0x00008000 */

+#define HSEM_C1MISR_MISF15        HSEM_C1MISR_MISF15_Msk                       /*!<semaphore 15 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF16_Pos    (16U)

+#define HSEM_C1MISR_MISF16_Msk    (0x1UL << HSEM_C1MISR_MISF16_Pos)            /*!< 0x00010000 */

+#define HSEM_C1MISR_MISF16        HSEM_C1MISR_MISF16_Msk                       /*!<semaphore 16 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF17_Pos    (17U)

+#define HSEM_C1MISR_MISF17_Msk    (0x1UL << HSEM_C1MISR_MISF17_Pos)            /*!< 0x00020000 */

+#define HSEM_C1MISR_MISF17        HSEM_C1MISR_MISF17_Msk                       /*!<semaphore 17 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF18_Pos    (18U)

+#define HSEM_C1MISR_MISF18_Msk    (0x1UL << HSEM_C1MISR_MISF18_Pos)            /*!< 0x00040000 */

+#define HSEM_C1MISR_MISF18        HSEM_C1MISR_MISF18_Msk                       /*!<semaphore 18 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF19_Pos    (19U)

+#define HSEM_C1MISR_MISF19_Msk    (0x1UL << HSEM_C1MISR_MISF19_Pos)            /*!< 0x00080000 */

+#define HSEM_C1MISR_MISF19        HSEM_C1MISR_MISF19_Msk                       /*!<semaphore 19 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF20_Pos    (20U)

+#define HSEM_C1MISR_MISF20_Msk    (0x1UL << HSEM_C1MISR_MISF20_Pos)            /*!< 0x00100000 */

+#define HSEM_C1MISR_MISF20        HSEM_C1MISR_MISF20_Msk                       /*!<semaphore 20 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF21_Pos    (21U)

+#define HSEM_C1MISR_MISF21_Msk    (0x1UL << HSEM_C1MISR_MISF21_Pos)            /*!< 0x00200000 */

+#define HSEM_C1MISR_MISF21        HSEM_C1MISR_MISF21_Msk                       /*!<semaphore 21 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF22_Pos    (22U)

+#define HSEM_C1MISR_MISF22_Msk    (0x1UL << HSEM_C1MISR_MISF22_Pos)            /*!< 0x00400000 */

+#define HSEM_C1MISR_MISF22        HSEM_C1MISR_MISF22_Msk                       /*!<semaphore 22 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF23_Pos    (23U)

+#define HSEM_C1MISR_MISF23_Msk    (0x1UL << HSEM_C1MISR_MISF23_Pos)            /*!< 0x00800000 */

+#define HSEM_C1MISR_MISF23        HSEM_C1MISR_MISF23_Msk                       /*!<semaphore 23 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF24_Pos    (24U)

+#define HSEM_C1MISR_MISF24_Msk    (0x1UL << HSEM_C1MISR_MISF24_Pos)            /*!< 0x01000000 */

+#define HSEM_C1MISR_MISF24        HSEM_C1MISR_MISF24_Msk                       /*!<semaphore 24 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF25_Pos    (25U)

+#define HSEM_C1MISR_MISF25_Msk    (0x1UL << HSEM_C1MISR_MISF25_Pos)            /*!< 0x02000000 */

+#define HSEM_C1MISR_MISF25        HSEM_C1MISR_MISF25_Msk                       /*!<semaphore 25 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF26_Pos    (26U)

+#define HSEM_C1MISR_MISF26_Msk    (0x1UL << HSEM_C1MISR_MISF26_Pos)            /*!< 0x04000000 */

+#define HSEM_C1MISR_MISF26        HSEM_C1MISR_MISF26_Msk                       /*!<semaphore 26 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF27_Pos    (27U)

+#define HSEM_C1MISR_MISF27_Msk    (0x1UL << HSEM_C1MISR_MISF27_Pos)            /*!< 0x08000000 */

+#define HSEM_C1MISR_MISF27        HSEM_C1MISR_MISF27_Msk                       /*!<semaphore 27 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF28_Pos    (28U)

+#define HSEM_C1MISR_MISF28_Msk    (0x1UL << HSEM_C1MISR_MISF28_Pos)            /*!< 0x10000000 */

+#define HSEM_C1MISR_MISF28        HSEM_C1MISR_MISF28_Msk                       /*!<semaphore 28 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF29_Pos    (29U)

+#define HSEM_C1MISR_MISF29_Msk    (0x1UL << HSEM_C1MISR_MISF29_Pos)            /*!< 0x20000000 */

+#define HSEM_C1MISR_MISF29        HSEM_C1MISR_MISF29_Msk                       /*!<semaphore 29 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF30_Pos    (30U)

+#define HSEM_C1MISR_MISF30_Msk    (0x1UL << HSEM_C1MISR_MISF30_Pos)            /*!< 0x40000000 */

+#define HSEM_C1MISR_MISF30        HSEM_C1MISR_MISF30_Msk                       /*!<semaphore 30 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF31_Pos    (31U)

+#define HSEM_C1MISR_MISF31_Msk    (0x1UL << HSEM_C1MISR_MISF31_Pos)            /*!< 0x80000000 */

+#define HSEM_C1MISR_MISF31        HSEM_C1MISR_MISF31_Msk                       /*!<semaphore 31 interrupt 0 masked status bit. */

+

+/********************  Bit definition for HSEM_CR register  *****************/

+#define HSEM_CR_COREID_Pos        (8U)

+#define HSEM_CR_COREID_Msk        (0xFFUL << HSEM_CR_COREID_Pos)               /*!< 0x0000FF00 */

+#define HSEM_CR_COREID            HSEM_CR_COREID_Msk                           /*!<CoreID of semaphores to be cleared. */

+#define HSEM_CR_KEY_Pos           (16U)

+#define HSEM_CR_KEY_Msk           (0xFFFFUL << HSEM_CR_KEY_Pos)                /*!< 0xFFFF0000 */

+#define HSEM_CR_KEY               HSEM_CR_KEY_Msk                              /*!<semaphores clear key. */

+

+/********************  Bit definition for HSEM_KEYR register  *****************/

+#define HSEM_KEYR_KEY_Pos         (16U)

+#define HSEM_KEYR_KEY_Msk         (0xFFFFUL << HSEM_KEYR_KEY_Pos)              /*!< 0xFFFF0000 */

+#define HSEM_KEYR_KEY             HSEM_KEYR_KEY_Msk                            /*!<semaphores clear key. */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      Inter-integrated Circuit Interface (I2C)              */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for I2C_CR1 register  *******************/

+#define I2C_CR1_PE_Pos               (0U)

+#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */

+#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */

+#define I2C_CR1_TXIE_Pos             (1U)

+#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */

+#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */

+#define I2C_CR1_RXIE_Pos             (2U)

+#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */

+#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */

+#define I2C_CR1_ADDRIE_Pos           (3U)

+#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */

+#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */

+#define I2C_CR1_NACKIE_Pos           (4U)

+#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */

+#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */

+#define I2C_CR1_STOPIE_Pos           (5U)

+#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */

+#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */

+#define I2C_CR1_TCIE_Pos             (6U)

+#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */

+#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */

+#define I2C_CR1_ERRIE_Pos            (7U)

+#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */

+#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */

+#define I2C_CR1_DNF_Pos              (8U)

+#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */

+#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */

+#define I2C_CR1_ANFOFF_Pos           (12U)

+#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */

+#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */

+#define I2C_CR1_TXDMAEN_Pos          (14U)

+#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */

+#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */

+#define I2C_CR1_RXDMAEN_Pos          (15U)

+#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */

+#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */

+#define I2C_CR1_SBC_Pos              (16U)

+#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */

+#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */

+#define I2C_CR1_NOSTRETCH_Pos        (17U)

+#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */

+#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */

+#define I2C_CR1_WUPEN_Pos            (18U)

+#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */

+#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */

+#define I2C_CR1_GCEN_Pos             (19U)

+#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */

+#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */

+#define I2C_CR1_SMBHEN_Pos           (20U)

+#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */

+#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */

+#define I2C_CR1_SMBDEN_Pos           (21U)

+#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */

+#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */

+#define I2C_CR1_ALERTEN_Pos          (22U)

+#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */

+#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */

+#define I2C_CR1_PECEN_Pos            (23U)

+#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */

+#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */

+

+/******************  Bit definition for I2C_CR2 register  ********************/

+#define I2C_CR2_SADD_Pos             (0U)

+#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */

+#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */

+#define I2C_CR2_RD_WRN_Pos           (10U)

+#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */

+#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */

+#define I2C_CR2_ADD10_Pos            (11U)

+#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */

+#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */

+#define I2C_CR2_HEAD10R_Pos          (12U)

+#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */

+#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */

+#define I2C_CR2_START_Pos            (13U)

+#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */

+#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */

+#define I2C_CR2_STOP_Pos             (14U)

+#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */

+#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */

+#define I2C_CR2_NACK_Pos             (15U)

+#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */

+#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */

+#define I2C_CR2_NBYTES_Pos           (16U)

+#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */

+#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */

+#define I2C_CR2_RELOAD_Pos           (24U)

+#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */

+#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */

+#define I2C_CR2_AUTOEND_Pos          (25U)

+#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */

+#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */

+#define I2C_CR2_PECBYTE_Pos          (26U)

+#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */

+#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */

+

+/*******************  Bit definition for I2C_OAR1 register  ******************/

+#define I2C_OAR1_OA1_Pos             (0U)

+#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */

+#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */

+#define I2C_OAR1_OA1MODE_Pos         (10U)

+#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */

+#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */

+#define I2C_OAR1_OA1EN_Pos           (15U)

+#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */

+#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */

+

+/*******************  Bit definition for I2C_OAR2 register  ******************/

+#define I2C_OAR2_OA2_Pos             (1U)

+#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */

+#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */

+#define I2C_OAR2_OA2MSK_Pos          (8U)

+#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */

+#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */

+#define I2C_OAR2_OA2NOMASK           0x00000000UL                              /*!< No mask */

+#define I2C_OAR2_OA2MASK01_Pos       (8U)

+#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */

+#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared */

+#define I2C_OAR2_OA2MASK02_Pos       (9U)

+#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */

+#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */

+#define I2C_OAR2_OA2MASK03_Pos       (8U)

+#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */

+#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */

+#define I2C_OAR2_OA2MASK04_Pos       (10U)

+#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */

+#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */

+#define I2C_OAR2_OA2MASK05_Pos       (8U)

+#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */

+#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */

+#define I2C_OAR2_OA2MASK06_Pos       (9U)

+#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */

+#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared */

+#define I2C_OAR2_OA2MASK07_Pos       (8U)

+#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */

+#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done */

+#define I2C_OAR2_OA2EN_Pos           (15U)

+#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */

+#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */

+

+/*******************  Bit definition for I2C_TIMINGR register *******************/

+#define I2C_TIMINGR_SCLL_Pos         (0U)

+#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */

+#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */

+#define I2C_TIMINGR_SCLH_Pos         (8U)

+#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */

+#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */

+#define I2C_TIMINGR_SDADEL_Pos       (16U)

+#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */

+#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */

+#define I2C_TIMINGR_SCLDEL_Pos       (20U)

+#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */

+#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */

+#define I2C_TIMINGR_PRESC_Pos        (28U)

+#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */

+#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */

+

+/******************* Bit definition for I2C_TIMEOUTR register *******************/

+#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)

+#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */

+#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */

+#define I2C_TIMEOUTR_TIDLE_Pos       (12U)

+#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */

+#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */

+#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)

+#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */

+#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */

+#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)

+#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */

+#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/

+#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)

+#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */

+#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */

+

+/******************  Bit definition for I2C_ISR register  *********************/

+#define I2C_ISR_TXE_Pos              (0U)

+#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */

+#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */

+#define I2C_ISR_TXIS_Pos             (1U)

+#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */

+#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */

+#define I2C_ISR_RXNE_Pos             (2U)

+#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */

+#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */

+#define I2C_ISR_ADDR_Pos             (3U)

+#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */

+#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/

+#define I2C_ISR_NACKF_Pos            (4U)

+#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */

+#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */

+#define I2C_ISR_STOPF_Pos            (5U)

+#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */

+#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */

+#define I2C_ISR_TC_Pos               (6U)

+#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */

+#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */

+#define I2C_ISR_TCR_Pos              (7U)

+#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */

+#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */

+#define I2C_ISR_BERR_Pos             (8U)

+#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */

+#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */

+#define I2C_ISR_ARLO_Pos             (9U)

+#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */

+#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */

+#define I2C_ISR_OVR_Pos              (10U)

+#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */

+#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */

+#define I2C_ISR_PECERR_Pos           (11U)

+#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */

+#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */

+#define I2C_ISR_TIMEOUT_Pos          (12U)

+#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */

+#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */

+#define I2C_ISR_ALERT_Pos            (13U)

+#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */

+#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */

+#define I2C_ISR_BUSY_Pos             (15U)

+#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */

+#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */

+#define I2C_ISR_DIR_Pos              (16U)

+#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */

+#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */

+#define I2C_ISR_ADDCODE_Pos          (17U)

+#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */

+#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */

+

+/******************  Bit definition for I2C_ICR register  *********************/

+#define I2C_ICR_ADDRCF_Pos           (3U)

+#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */

+#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */

+#define I2C_ICR_NACKCF_Pos           (4U)

+#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */

+#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */

+#define I2C_ICR_STOPCF_Pos           (5U)

+#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */

+#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */

+#define I2C_ICR_BERRCF_Pos           (8U)

+#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */

+#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */

+#define I2C_ICR_ARLOCF_Pos           (9U)

+#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */

+#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */

+#define I2C_ICR_OVRCF_Pos            (10U)

+#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */

+#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */

+#define I2C_ICR_PECCF_Pos            (11U)

+#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */

+#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */

+#define I2C_ICR_TIMOUTCF_Pos         (12U)

+#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */

+#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */

+#define I2C_ICR_ALERTCF_Pos          (13U)

+#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */

+#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */

+

+/******************  Bit definition for I2C_PECR register  *********************/

+#define I2C_PECR_PEC_Pos             (0U)

+#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */

+#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */

+

+/******************  Bit definition for I2C_RXDR register  *********************/

+#define I2C_RXDR_RXDATA_Pos          (0U)

+#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */

+#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */

+

+/******************  Bit definition for I2C_TXDR register  *********************/

+#define I2C_TXDR_TXDATA_Pos          (0U)

+#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */

+#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           Independent WATCHDOG                             */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for IWDG_KR register  ********************/

+#define IWDG_KR_KEY_Pos      (0U)

+#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */

+#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */

+

+/*******************  Bit definition for IWDG_PR register  ********************/

+#define IWDG_PR_PR_Pos       (0U)

+#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */

+#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */

+#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */

+#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */

+#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */

+

+/*******************  Bit definition for IWDG_RLR register  *******************/

+#define IWDG_RLR_RL_Pos      (0U)

+#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */

+#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */

+

+/*******************  Bit definition for IWDG_SR register  ********************/

+#define IWDG_SR_PVU_Pos      (0U)

+#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */

+#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */

+#define IWDG_SR_RVU_Pos      (1U)

+#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */

+#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */

+#define IWDG_SR_WVU_Pos      (2U)

+#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */

+#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */

+

+/*******************  Bit definition for IWDG_KR register  ********************/

+#define IWDG_WINR_WIN_Pos    (0U)

+#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */

+#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                     MDMA                                   */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for MDMA_GISR0 register  ****************/

+#define MDMA_GISR0_GIF0_Pos       (0U)

+#define MDMA_GISR0_GIF0_Msk       (0x1UL << MDMA_GISR0_GIF0_Pos)               /*!< 0x00000001 */

+#define MDMA_GISR0_GIF0           MDMA_GISR0_GIF0_Msk                          /*!< Channel 0 global interrupt flag */

+#define MDMA_GISR0_GIF1_Pos       (1U)

+#define MDMA_GISR0_GIF1_Msk       (0x1UL << MDMA_GISR0_GIF1_Pos)               /*!< 0x00000002 */

+#define MDMA_GISR0_GIF1           MDMA_GISR0_GIF1_Msk                          /*!< Channel 1 global interrupt flag */

+#define MDMA_GISR0_GIF2_Pos       (2U)

+#define MDMA_GISR0_GIF2_Msk       (0x1UL << MDMA_GISR0_GIF2_Pos)               /*!< 0x00000004 */

+#define MDMA_GISR0_GIF2           MDMA_GISR0_GIF2_Msk                          /*!< Channel 2 global interrupt flag */

+#define MDMA_GISR0_GIF3_Pos       (3U)

+#define MDMA_GISR0_GIF3_Msk       (0x1UL << MDMA_GISR0_GIF3_Pos)               /*!< 0x00000008 */

+#define MDMA_GISR0_GIF3           MDMA_GISR0_GIF3_Msk                          /*!< Channel 3 global interrupt flag */

+#define MDMA_GISR0_GIF4_Pos       (4U)

+#define MDMA_GISR0_GIF4_Msk       (0x1UL << MDMA_GISR0_GIF4_Pos)               /*!< 0x00000010 */

+#define MDMA_GISR0_GIF4           MDMA_GISR0_GIF4_Msk                          /*!< Channel 4 global interrupt flag */

+#define MDMA_GISR0_GIF5_Pos       (5U)

+#define MDMA_GISR0_GIF5_Msk       (0x1UL << MDMA_GISR0_GIF5_Pos)               /*!< 0x00000020 */

+#define MDMA_GISR0_GIF5           MDMA_GISR0_GIF5_Msk                          /*!< Channel 5 global interrupt flag */

+#define MDMA_GISR0_GIF6_Pos       (6U)

+#define MDMA_GISR0_GIF6_Msk       (0x1UL << MDMA_GISR0_GIF6_Pos)               /*!< 0x00000040 */

+#define MDMA_GISR0_GIF6           MDMA_GISR0_GIF6_Msk                          /*!< Channel 6 global interrupt flag */

+#define MDMA_GISR0_GIF7_Pos       (7U)

+#define MDMA_GISR0_GIF7_Msk       (0x1UL << MDMA_GISR0_GIF7_Pos)               /*!< 0x00000080 */

+#define MDMA_GISR0_GIF7           MDMA_GISR0_GIF7_Msk                          /*!< Channel 7 global interrupt flag */

+#define MDMA_GISR0_GIF8_Pos       (8U)

+#define MDMA_GISR0_GIF8_Msk       (0x1UL << MDMA_GISR0_GIF8_Pos)               /*!< 0x00000100 */

+#define MDMA_GISR0_GIF8           MDMA_GISR0_GIF8_Msk                          /*!< Channel 8 global interrupt flag */

+#define MDMA_GISR0_GIF9_Pos       (9U)

+#define MDMA_GISR0_GIF9_Msk       (0x1UL << MDMA_GISR0_GIF9_Pos)               /*!< 0x00000200 */

+#define MDMA_GISR0_GIF9           MDMA_GISR0_GIF9_Msk                          /*!< Channel 9 global interrupt flag */

+#define MDMA_GISR0_GIF10_Pos      (10U)

+#define MDMA_GISR0_GIF10_Msk      (0x1UL << MDMA_GISR0_GIF10_Pos)              /*!< 0x00000400 */

+#define MDMA_GISR0_GIF10          MDMA_GISR0_GIF10_Msk                         /*!< Channel 10 global interrupt flag */

+#define MDMA_GISR0_GIF11_Pos      (11U)

+#define MDMA_GISR0_GIF11_Msk      (0x1UL << MDMA_GISR0_GIF11_Pos)              /*!< 0x00000800 */

+#define MDMA_GISR0_GIF11          MDMA_GISR0_GIF11_Msk                         /*!< Channel 11 global interrupt flag */

+#define MDMA_GISR0_GIF12_Pos      (12U)

+#define MDMA_GISR0_GIF12_Msk      (0x1UL << MDMA_GISR0_GIF12_Pos)              /*!< 0x00001000 */

+#define MDMA_GISR0_GIF12          MDMA_GISR0_GIF12_Msk                         /*!< Channel 12 global interrupt flag */

+#define MDMA_GISR0_GIF13_Pos      (13U)

+#define MDMA_GISR0_GIF13_Msk      (0x1UL << MDMA_GISR0_GIF13_Pos)              /*!< 0x00002000 */

+#define MDMA_GISR0_GIF13          MDMA_GISR0_GIF13_Msk                         /*!< Channel 13 global interrupt flag */

+#define MDMA_GISR0_GIF14_Pos      (14U)

+#define MDMA_GISR0_GIF14_Msk      (0x1UL << MDMA_GISR0_GIF14_Pos)              /*!< 0x00004000 */

+#define MDMA_GISR0_GIF14          MDMA_GISR0_GIF14_Msk                         /*!< Channel 14 global interrupt flag */

+#define MDMA_GISR0_GIF15_Pos      (15U)

+#define MDMA_GISR0_GIF15_Msk      (0x1UL << MDMA_GISR0_GIF15_Pos)              /*!< 0x00008000 */

+#define MDMA_GISR0_GIF15          MDMA_GISR0_GIF15_Msk                         /*!< Channel 15 global interrupt flag */

+

+/********************  Bit definition for MDMA_CxISR register  ****************/

+#define MDMA_CISR_TEIF_Pos        (0U)

+#define MDMA_CISR_TEIF_Msk        (0x1UL << MDMA_CISR_TEIF_Pos)                /*!< 0x00000001 */

+#define MDMA_CISR_TEIF            MDMA_CISR_TEIF_Msk                           /*!< Channel x transfer error interrupt flag */

+#define MDMA_CISR_CTCIF_Pos       (1U)

+#define MDMA_CISR_CTCIF_Msk       (0x1UL << MDMA_CISR_CTCIF_Pos)               /*!< 0x00000002 */

+#define MDMA_CISR_CTCIF           MDMA_CISR_CTCIF_Msk                          /*!< Channel x Channel Transfer Complete interrupt flag */

+#define MDMA_CISR_BRTIF_Pos       (2U)

+#define MDMA_CISR_BRTIF_Msk       (0x1UL << MDMA_CISR_BRTIF_Pos)               /*!< 0x00000004 */

+#define MDMA_CISR_BRTIF           MDMA_CISR_BRTIF_Msk                          /*!< Channel x block repeat transfer complete interrupt flag */

+#define MDMA_CISR_BTIF_Pos        (3U)

+#define MDMA_CISR_BTIF_Msk        (0x1UL << MDMA_CISR_BTIF_Pos)                /*!< 0x00000008 */

+#define MDMA_CISR_BTIF            MDMA_CISR_BTIF_Msk                           /*!< Channel x block transfer complete interrupt flag */

+#define MDMA_CISR_TCIF_Pos        (4U)

+#define MDMA_CISR_TCIF_Msk        (0x1UL << MDMA_CISR_TCIF_Pos)                /*!< 0x00000010 */

+#define MDMA_CISR_TCIF            MDMA_CISR_TCIF_Msk                           /*!< Channel x buffer transfer complete interrupt flag */

+#define MDMA_CISR_CRQA_Pos        (16U)

+#define MDMA_CISR_CRQA_Msk        (0x1UL << MDMA_CISR_CRQA_Pos)                /*!< 0x00010000 */

+#define MDMA_CISR_CRQA            MDMA_CISR_CRQA_Msk                           /*!< Channel x ReQest Active flag */

+

+/********************  Bit definition for MDMA_CxIFCR register  ****************/

+#define MDMA_CIFCR_CTEIF_Pos      (0U)

+#define MDMA_CIFCR_CTEIF_Msk      (0x1UL << MDMA_CIFCR_CTEIF_Pos)              /*!< 0x00000001 */

+#define MDMA_CIFCR_CTEIF          MDMA_CIFCR_CTEIF_Msk                         /*!< Channel x clear transfer error interrupt flag */

+#define MDMA_CIFCR_CCTCIF_Pos     (1U)

+#define MDMA_CIFCR_CCTCIF_Msk     (0x1UL << MDMA_CIFCR_CCTCIF_Pos)             /*!< 0x00000002 */

+#define MDMA_CIFCR_CCTCIF         MDMA_CIFCR_CCTCIF_Msk                        /*!< Clear Channel transfer complete interrupt flag for channel x */

+#define MDMA_CIFCR_CBRTIF_Pos     (2U)

+#define MDMA_CIFCR_CBRTIF_Msk     (0x1UL << MDMA_CIFCR_CBRTIF_Pos)             /*!< 0x00000004 */

+#define MDMA_CIFCR_CBRTIF         MDMA_CIFCR_CBRTIF_Msk                        /*!< Channel x clear block repeat transfer complete interrupt flag */

+#define MDMA_CIFCR_CBTIF_Pos      (3U)

+#define MDMA_CIFCR_CBTIF_Msk      (0x1UL << MDMA_CIFCR_CBTIF_Pos)              /*!< 0x00000008 */

+#define MDMA_CIFCR_CBTIF          MDMA_CIFCR_CBTIF_Msk                         /*!< Channel x Clear block transfer complete interrupt flag */

+#define MDMA_CIFCR_CLTCIF_Pos     (4U)

+#define MDMA_CIFCR_CLTCIF_Msk     (0x1UL << MDMA_CIFCR_CLTCIF_Pos)             /*!< 0x00000010 */

+#define MDMA_CIFCR_CLTCIF         MDMA_CIFCR_CLTCIF_Msk                        /*!< CLear Transfer buffer Complete Interrupt Flag for channel */

+

+/********************  Bit definition for MDMA_CxESR register  ****************/

+#define MDMA_CESR_TEA_Pos         (0U)

+#define MDMA_CESR_TEA_Msk         (0x7FUL << MDMA_CESR_TEA_Pos)                /*!< 0x0000007F */

+#define MDMA_CESR_TEA             MDMA_CESR_TEA_Msk                            /*!< Transfer Error Address */

+#define MDMA_CESR_TED_Pos         (7U)

+#define MDMA_CESR_TED_Msk         (0x1UL << MDMA_CESR_TED_Pos)                 /*!< 0x00000080 */

+#define MDMA_CESR_TED             MDMA_CESR_TED_Msk                            /*!< Transfer Error Direction */

+#define MDMA_CESR_TELD_Pos        (8U)

+#define MDMA_CESR_TELD_Msk        (0x1UL << MDMA_CESR_TELD_Pos)                /*!< 0x00000100 */

+#define MDMA_CESR_TELD            MDMA_CESR_TELD_Msk                           /*!< Transfer Error Link Data */

+#define MDMA_CESR_TEMD_Pos        (9U)

+#define MDMA_CESR_TEMD_Msk        (0x1UL << MDMA_CESR_TEMD_Pos)                /*!< 0x00000200 */

+#define MDMA_CESR_TEMD            MDMA_CESR_TEMD_Msk                           /*!< Transfer Error Mask Data */

+#define MDMA_CESR_ASE_Pos         (10U)

+#define MDMA_CESR_ASE_Msk         (0x1UL << MDMA_CESR_ASE_Pos)                 /*!< 0x00000400 */

+#define MDMA_CESR_ASE             MDMA_CESR_ASE_Msk                            /*!< Address/Size Error       */

+#define MDMA_CESR_BSE_Pos         (11U)

+#define MDMA_CESR_BSE_Msk         (0x1UL << MDMA_CESR_BSE_Pos)                 /*!< 0x00000800 */

+#define MDMA_CESR_BSE             MDMA_CESR_BSE_Msk                            /*!< Block Size Error         */

+

+/********************  Bit definition for MDMA_CxCR register  ****************/

+#define MDMA_CCR_EN_Pos           (0U)

+#define MDMA_CCR_EN_Msk           (0x1UL << MDMA_CCR_EN_Pos)                   /*!< 0x00000001 */

+#define MDMA_CCR_EN               MDMA_CCR_EN_Msk                              /*!< Channel enable / flag channel ready when read low */

+#define MDMA_CCR_TEIE_Pos         (1U)

+#define MDMA_CCR_TEIE_Msk         (0x1UL << MDMA_CCR_TEIE_Pos)                 /*!< 0x00000002 */

+#define MDMA_CCR_TEIE             MDMA_CCR_TEIE_Msk                            /*!< Transfer error interrupt enable */

+#define MDMA_CCR_CTCIE_Pos        (2U)

+#define MDMA_CCR_CTCIE_Msk        (0x1UL << MDMA_CCR_CTCIE_Pos)                /*!< 0x00000004 */

+#define MDMA_CCR_CTCIE            MDMA_CCR_CTCIE_Msk                           /*!< Channel Transfer Complete interrupt enable */

+#define MDMA_CCR_BRTIE_Pos        (3U)

+#define MDMA_CCR_BRTIE_Msk        (0x1UL << MDMA_CCR_BRTIE_Pos)                /*!< 0x00000008 */

+#define MDMA_CCR_BRTIE            MDMA_CCR_BRTIE_Msk                           /*!< Block Repeat transfer interrupt enable */

+#define MDMA_CCR_BTIE_Pos         (4U)

+#define MDMA_CCR_BTIE_Msk         (0x1UL << MDMA_CCR_BTIE_Pos)                 /*!< 0x00000010 */

+#define MDMA_CCR_BTIE             MDMA_CCR_BTIE_Msk                            /*!< Block Transfer interrupt enable */

+#define MDMA_CCR_TCIE_Pos         (5U)

+#define MDMA_CCR_TCIE_Msk         (0x1UL << MDMA_CCR_TCIE_Pos)                 /*!< 0x00000020 */

+#define MDMA_CCR_TCIE             MDMA_CCR_TCIE_Msk                            /*!< buffer Transfer Complete interrupt enable */

+#define MDMA_CCR_PL_Pos           (6U)

+#define MDMA_CCR_PL_Msk           (0x3UL << MDMA_CCR_PL_Pos)                   /*!< 0x000000C0 */

+#define MDMA_CCR_PL               MDMA_CCR_PL_Msk                              /*!< Priority level */

+#define MDMA_CCR_PL_0             (0x1UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000040 */

+#define MDMA_CCR_PL_1             (0x2UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000080 */

+#define MDMA_CCR_BEX_Pos          (12U)

+#define MDMA_CCR_BEX_Msk          (0x1UL << MDMA_CCR_BEX_Pos)                  /*!< 0x00001000 */

+#define MDMA_CCR_BEX              MDMA_CCR_BEX_Msk                             /*!< Byte Endianess eXchange */

+#define MDMA_CCR_HEX_Pos          (13U)

+#define MDMA_CCR_HEX_Msk          (0x1UL << MDMA_CCR_HEX_Pos)                  /*!< 0x00002000 */

+#define MDMA_CCR_HEX              MDMA_CCR_HEX_Msk                             /*!< Half word Endianess eXchange */

+#define MDMA_CCR_WEX_Pos          (14U)

+#define MDMA_CCR_WEX_Msk          (0x1UL << MDMA_CCR_WEX_Pos)                  /*!< 0x00004000 */

+#define MDMA_CCR_WEX              MDMA_CCR_WEX_Msk                             /*!< Word Endianess eXchange */

+#define MDMA_CCR_SWRQ_Pos         (16U)

+#define MDMA_CCR_SWRQ_Msk         (0x1UL << MDMA_CCR_SWRQ_Pos)                 /*!< 0x00010000 */

+#define MDMA_CCR_SWRQ             MDMA_CCR_SWRQ_Msk                            /*!< SW ReQuest */

+

+/********************  Bit definition for MDMA_CxTCR register  ****************/

+#define MDMA_CTCR_SINC_Pos        (0U)

+#define MDMA_CTCR_SINC_Msk        (0x3UL << MDMA_CTCR_SINC_Pos)                /*!< 0x00000003 */

+#define MDMA_CTCR_SINC            MDMA_CTCR_SINC_Msk                           /*!< Source increment mode */

+#define MDMA_CTCR_SINC_0          (0x1UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000001 */

+#define MDMA_CTCR_SINC_1          (0x2UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000002 */

+#define MDMA_CTCR_DINC_Pos        (2U)

+#define MDMA_CTCR_DINC_Msk        (0x3UL << MDMA_CTCR_DINC_Pos)                /*!< 0x0000000C */

+#define MDMA_CTCR_DINC            MDMA_CTCR_DINC_Msk                           /*!< Source increment mode */

+#define MDMA_CTCR_DINC_0          (0x1UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000004 */

+#define MDMA_CTCR_DINC_1          (0x2UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000008 */

+#define MDMA_CTCR_SSIZE_Pos       (4U)

+#define MDMA_CTCR_SSIZE_Msk       (0x3UL << MDMA_CTCR_SSIZE_Pos)               /*!< 0x00000030 */

+#define MDMA_CTCR_SSIZE           MDMA_CTCR_SSIZE_Msk                          /*!< Source data size */

+#define MDMA_CTCR_SSIZE_0         (0x1UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000010 */

+#define MDMA_CTCR_SSIZE_1         (0x2UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000020 */

+#define MDMA_CTCR_DSIZE_Pos       (6U)

+#define MDMA_CTCR_DSIZE_Msk       (0x3UL << MDMA_CTCR_DSIZE_Pos)               /*!< 0x000000C0 */

+#define MDMA_CTCR_DSIZE           MDMA_CTCR_DSIZE_Msk                          /*!< Destination data size */

+#define MDMA_CTCR_DSIZE_0         (0x1UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000040 */

+#define MDMA_CTCR_DSIZE_1         (0x2UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000080 */

+#define MDMA_CTCR_SINCOS_Pos      (8U)

+#define MDMA_CTCR_SINCOS_Msk      (0x3UL << MDMA_CTCR_SINCOS_Pos)              /*!< 0x00000300 */

+#define MDMA_CTCR_SINCOS          MDMA_CTCR_SINCOS_Msk                         /*!< Source increment offset size */

+#define MDMA_CTCR_SINCOS_0        (0x1UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000100 */

+#define MDMA_CTCR_SINCOS_1        (0x2UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000200 */

+#define MDMA_CTCR_DINCOS_Pos      (10U)

+#define MDMA_CTCR_DINCOS_Msk      (0x3UL << MDMA_CTCR_DINCOS_Pos)              /*!< 0x00000C00 */

+#define MDMA_CTCR_DINCOS          MDMA_CTCR_DINCOS_Msk                         /*!< Destination increment offset size */

+#define MDMA_CTCR_DINCOS_0        (0x1UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000400 */

+#define MDMA_CTCR_DINCOS_1        (0x2UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000800 */

+#define MDMA_CTCR_SBURST_Pos      (12U)

+#define MDMA_CTCR_SBURST_Msk      (0x7UL << MDMA_CTCR_SBURST_Pos)              /*!< 0x00007000 */

+#define MDMA_CTCR_SBURST          MDMA_CTCR_SBURST_Msk                         /*!< Source burst transfer configuration */

+#define MDMA_CTCR_SBURST_0        (0x1UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00001000 */

+#define MDMA_CTCR_SBURST_1        (0x2UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00002000 */

+#define MDMA_CTCR_SBURST_2        (0x4UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00004000 */

+#define MDMA_CTCR_DBURST_Pos      (15U)

+#define MDMA_CTCR_DBURST_Msk      (0x7UL << MDMA_CTCR_DBURST_Pos)              /*!< 0x00038000 */

+#define MDMA_CTCR_DBURST          MDMA_CTCR_DBURST_Msk                         /*!< Destination burst transfer configuration */

+#define MDMA_CTCR_DBURST_0        (0x1UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00008000 */

+#define MDMA_CTCR_DBURST_1        (0x2UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00010000 */

+#define MDMA_CTCR_DBURST_2        (0x4UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00020000 */

+#define MDMA_CTCR_TLEN_Pos        (18U)

+#define MDMA_CTCR_TLEN_Msk        (0x7FUL << MDMA_CTCR_TLEN_Pos)               /*!< 0x01FC0000 */

+#define MDMA_CTCR_TLEN            MDMA_CTCR_TLEN_Msk                           /*!< buffer Transfer Length (number of bytes - 1) */

+#define MDMA_CTCR_PKE_Pos         (25U)

+#define MDMA_CTCR_PKE_Msk         (0x1UL << MDMA_CTCR_PKE_Pos)                 /*!< 0x02000000 */

+#define MDMA_CTCR_PKE             MDMA_CTCR_PKE_Msk                            /*!< PacK Enable */

+#define MDMA_CTCR_PAM_Pos         (26U)

+#define MDMA_CTCR_PAM_Msk         (0x3UL << MDMA_CTCR_PAM_Pos)                 /*!< 0x0C000000 */

+#define MDMA_CTCR_PAM             MDMA_CTCR_PAM_Msk                            /*!< Padding/Alignement Mode */

+#define MDMA_CTCR_PAM_0           (0x1UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x4000000 */

+#define MDMA_CTCR_PAM_1           (0x2UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x8000000 */

+#define MDMA_CTCR_TRGM_Pos        (28U)

+#define MDMA_CTCR_TRGM_Msk        (0x3UL << MDMA_CTCR_TRGM_Pos)                /*!< 0x30000000 */

+#define MDMA_CTCR_TRGM            MDMA_CTCR_TRGM_Msk                           /*!< Trigger Mode */

+#define MDMA_CTCR_TRGM_0          (0x1UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x10000000 */

+#define MDMA_CTCR_TRGM_1          (0x2UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x20000000 */

+#define MDMA_CTCR_SWRM_Pos        (30U)

+#define MDMA_CTCR_SWRM_Msk        (0x1UL << MDMA_CTCR_SWRM_Pos)                /*!< 0x40000000 */

+#define MDMA_CTCR_SWRM            MDMA_CTCR_SWRM_Msk                           /*!< SW Request Mode */

+#define MDMA_CTCR_BWM_Pos         (31U)

+#define MDMA_CTCR_BWM_Msk         (0x1UL << MDMA_CTCR_BWM_Pos)                 /*!< 0x80000000 */

+#define MDMA_CTCR_BWM             MDMA_CTCR_BWM_Msk                            /*!< Bufferable Write Mode */

+

+/********************  Bit definition for MDMA_CxBNDTR register  ****************/

+#define MDMA_CBNDTR_BNDT_Pos      (0U)

+#define MDMA_CBNDTR_BNDT_Msk      (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos)          /*!< 0x0001FFFF */

+#define MDMA_CBNDTR_BNDT          MDMA_CBNDTR_BNDT_Msk                         /*!< Block Number of data bytes to transfer */

+#define MDMA_CBNDTR_BRSUM_Pos     (18U)

+#define MDMA_CBNDTR_BRSUM_Msk     (0x1UL << MDMA_CBNDTR_BRSUM_Pos)             /*!< 0x00040000 */

+#define MDMA_CBNDTR_BRSUM         MDMA_CBNDTR_BRSUM_Msk                        /*!< Block Repeat Source address Update Mode */

+#define MDMA_CBNDTR_BRDUM_Pos     (19U)

+#define MDMA_CBNDTR_BRDUM_Msk     (0x1UL << MDMA_CBNDTR_BRDUM_Pos)             /*!< 0x00080000 */

+#define MDMA_CBNDTR_BRDUM         MDMA_CBNDTR_BRDUM_Msk                        /*!< Block Repeat Destination address Update Mode */

+#define MDMA_CBNDTR_BRC_Pos       (20U)

+#define MDMA_CBNDTR_BRC_Msk       (0xFFFUL << MDMA_CBNDTR_BRC_Pos)             /*!< 0xFFF00000 */

+#define MDMA_CBNDTR_BRC           MDMA_CBNDTR_BRC_Msk                          /*!< Block Repeat Count */

+

+/********************  Bit definition for MDMA_CxSAR register  ****************/

+#define MDMA_CSAR_SAR_Pos         (0U)

+#define MDMA_CSAR_SAR_Msk         (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CSAR_SAR             MDMA_CSAR_SAR_Msk                            /*!< Source address */

+

+/********************  Bit definition for MDMA_CxDAR register  ****************/

+#define MDMA_CDAR_DAR_Pos         (0U)

+#define MDMA_CDAR_DAR_Msk         (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CDAR_DAR             MDMA_CDAR_DAR_Msk                            /*!< Destination address */

+

+/********************  Bit definition for MDMA_CxBRUR  ************************/

+#define MDMA_CBRUR_SUV_Pos        (0U)

+#define MDMA_CBRUR_SUV_Msk        (0xFFFFUL << MDMA_CBRUR_SUV_Pos)             /*!< 0x0000FFFF */

+#define MDMA_CBRUR_SUV            MDMA_CBRUR_SUV_Msk                           /*!< Source address Update Value */

+#define MDMA_CBRUR_DUV_Pos        (16U)

+#define MDMA_CBRUR_DUV_Msk        (0xFFFFUL << MDMA_CBRUR_DUV_Pos)             /*!< 0xFFFF0000 */

+#define MDMA_CBRUR_DUV            MDMA_CBRUR_DUV_Msk                           /*!< Destination address Update Value */

+

+/********************  Bit definition for MDMA_CxLAR  *************************/

+#define MDMA_CLAR_LAR_Pos         (0U)

+#define MDMA_CLAR_LAR_Msk         (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CLAR_LAR             MDMA_CLAR_LAR_Msk                            /*!< Link Address Register */

+

+/********************  Bit definition for MDMA_CxTBR)  ************************/

+#define MDMA_CTBR_TSEL_Pos        (0U)

+#define MDMA_CTBR_TSEL_Msk        (0xFFUL << MDMA_CTBR_TSEL_Pos)               /*!< 0x000000FF */

+#define MDMA_CTBR_TSEL            MDMA_CTBR_TSEL_Msk                           /*!< Trigger SELection */

+#define MDMA_CTBR_SBUS_Pos        (16U)

+#define MDMA_CTBR_SBUS_Msk        (0x1UL << MDMA_CTBR_SBUS_Pos)                /*!< 0x00010000 */

+#define MDMA_CTBR_SBUS            MDMA_CTBR_SBUS_Msk                           /*!< Source BUS select */

+#define MDMA_CTBR_DBUS_Pos        (17U)

+#define MDMA_CTBR_DBUS_Msk        (0x1UL << MDMA_CTBR_DBUS_Pos)                /*!< 0x00020000 */

+#define MDMA_CTBR_DBUS            MDMA_CTBR_DBUS_Msk                           /*!< Destination BUS select */

+

+/********************  Bit definition for MDMA_CxMAR)  ************************/

+#define MDMA_CMAR_MAR_Pos         (0U)

+#define MDMA_CMAR_MAR_Msk         (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CMAR_MAR             MDMA_CMAR_MAR_Msk                            /*!< Mask address */

+

+/********************  Bit definition for MDMA_CxMDR)  ************************/

+#define MDMA_CMDR_MDR_Pos         (0U)

+#define MDMA_CMDR_MDR_Msk         (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CMDR_MDR             MDMA_CMDR_MDR_Msk                            /*!< Mask Data */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Operational Amplifier (OPAMP)                      */

+/*                                                                            */

+/******************************************************************************/

+/*********************  Bit definition for OPAMPx_CSR register  ***************/

+#define OPAMP_CSR_OPAMPxEN_Pos           (0U)

+#define OPAMP_CSR_OPAMPxEN_Msk           (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)     /*!< 0x00000001 */

+#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */

+#define OPAMP_CSR_FORCEVP_Pos            (1U)

+#define OPAMP_CSR_FORCEVP_Msk            (0x1UL << OPAMP_CSR_FORCEVP_Pos)      /*!< 0x00000002 */

+#define OPAMP_CSR_FORCEVP                OPAMP_CSR_FORCEVP_Msk                 /*!< Force internal reference on VP */

+

+#define OPAMP_CSR_VPSEL_Pos              (2U)

+#define OPAMP_CSR_VPSEL_Msk              (0x3UL << OPAMP_CSR_VPSEL_Pos)        /*!< 0x0000000C */

+#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */

+#define OPAMP_CSR_VPSEL_0                (0x1UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000004 */

+#define OPAMP_CSR_VPSEL_1                (0x2UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000008 */

+

+#define OPAMP_CSR_VMSEL_Pos              (5U)

+#define OPAMP_CSR_VMSEL_Msk              (0x3UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000060 */

+#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */

+#define OPAMP_CSR_VMSEL_0                (0x1UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000020 */

+#define OPAMP_CSR_VMSEL_1                (0x2UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000040 */

+

+#define OPAMP_CSR_OPAHSM_Pos             (8U)

+#define OPAMP_CSR_OPAHSM_Msk             (0x1UL << OPAMP_CSR_OPAHSM_Pos)       /*!< 0x00000100 */

+#define OPAMP_CSR_OPAHSM                 OPAMP_CSR_OPAHSM_Msk                  /*!< Operational amplifier high speed mode */

+#define OPAMP_CSR_CALON_Pos              (11U)

+#define OPAMP_CSR_CALON_Msk              (0x1UL << OPAMP_CSR_CALON_Pos)        /*!< 0x00000800 */

+#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */

+

+#define OPAMP_CSR_CALSEL_Pos             (12U)

+#define OPAMP_CSR_CALSEL_Msk             (0x3UL << OPAMP_CSR_CALSEL_Pos)       /*!< 0x00003000 */

+#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */

+#define OPAMP_CSR_CALSEL_0               (0x1UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00001000 */

+#define OPAMP_CSR_CALSEL_1               (0x2UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */

+

+#define OPAMP_CSR_PGGAIN_Pos             (14U)

+#define OPAMP_CSR_PGGAIN_Msk             (0xFUL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x0003C000 */

+#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */

+#define OPAMP_CSR_PGGAIN_0               (0x1UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00004000 */

+#define OPAMP_CSR_PGGAIN_1               (0x2UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00008000 */

+#define OPAMP_CSR_PGGAIN_2               (0x4UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00010000 */

+#define OPAMP_CSR_PGGAIN_3               (0x8UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00020000 */

+

+#define OPAMP_CSR_USERTRIM_Pos           (18U)

+#define OPAMP_CSR_USERTRIM_Msk           (0x1UL << OPAMP_CSR_USERTRIM_Pos)     /*!< 0x00040000 */

+#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */

+#define OPAMP_CSR_TSTREF_Pos             (29U)

+#define OPAMP_CSR_TSTREF_Msk             (0x1UL << OPAMP_CSR_TSTREF_Pos)       /*!< 0x20000000 */

+#define OPAMP_CSR_TSTREF                 OPAMP_CSR_TSTREF_Msk                  /*!< OpAmp calibration reference voltage output control */

+#define OPAMP_CSR_CALOUT_Pos             (30U)

+#define OPAMP_CSR_CALOUT_Msk             (0x1UL << OPAMP_CSR_CALOUT_Pos)       /*!< 0x40000000 */

+#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier calibration output */

+

+/*********************  Bit definition for OPAMP1_CSR register  ***************/

+#define OPAMP1_CSR_OPAEN_Pos              (0U)

+#define OPAMP1_CSR_OPAEN_Msk              (0x1UL << OPAMP1_CSR_OPAEN_Pos)      /*!< 0x00000001 */

+#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */

+#define OPAMP1_CSR_FORCEVP_Pos            (1U)

+#define OPAMP1_CSR_FORCEVP_Msk            (0x1UL << OPAMP1_CSR_FORCEVP_Pos)    /*!< 0x00000002 */

+#define OPAMP1_CSR_FORCEVP                OPAMP1_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */

+

+#define OPAMP1_CSR_VPSEL_Pos              (2U)

+#define OPAMP1_CSR_VPSEL_Msk              (0x3UL << OPAMP1_CSR_VPSEL_Pos)      /*!< 0x0000000C */

+#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */

+#define OPAMP1_CSR_VPSEL_0                (0x1UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000004 */

+#define OPAMP1_CSR_VPSEL_1                (0x2UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000008 */

+

+#define OPAMP1_CSR_VMSEL_Pos              (5U)

+#define OPAMP1_CSR_VMSEL_Msk              (0x3UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000060 */

+#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */

+#define OPAMP1_CSR_VMSEL_0                (0x1UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000020 */

+#define OPAMP1_CSR_VMSEL_1                (0x2UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000040 */

+

+#define OPAMP1_CSR_OPAHSM_Pos             (8U)

+#define OPAMP1_CSR_OPAHSM_Msk             (0x1UL << OPAMP1_CSR_OPAHSM_Pos)     /*!< 0x00000100 */

+#define OPAMP1_CSR_OPAHSM                 OPAMP1_CSR_OPAHSM_Msk                /*!< Operational amplifier1 high speed mode */

+#define OPAMP1_CSR_CALON_Pos              (11U)

+#define OPAMP1_CSR_CALON_Msk              (0x1UL << OPAMP1_CSR_CALON_Pos)      /*!< 0x00000800 */

+#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */

+

+#define OPAMP1_CSR_CALSEL_Pos             (12U)

+#define OPAMP1_CSR_CALSEL_Msk             (0x3UL << OPAMP1_CSR_CALSEL_Pos)     /*!< 0x00003000 */

+#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */

+#define OPAMP1_CSR_CALSEL_0               (0x1UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00001000 */

+#define OPAMP1_CSR_CALSEL_1               (0x2UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */

+

+#define OPAMP1_CSR_PGGAIN_Pos             (14U)

+#define OPAMP1_CSR_PGGAIN_Msk             (0xFUL << OPAMP1_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */

+#define OPAMP1_CSR_PGGAIN                 OPAMP1_CSR_PGGAIN_Msk                /*!< Operational amplifier1 Programmable amplifier gain value */

+#define OPAMP1_CSR_PGGAIN_0               (0x1UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00004000 */

+#define OPAMP1_CSR_PGGAIN_1               (0x2UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00008000 */

+#define OPAMP1_CSR_PGGAIN_2               (0x4UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00010000 */

+#define OPAMP1_CSR_PGGAIN_3               (0x8UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00020000 */

+

+#define OPAMP1_CSR_USERTRIM_Pos           (18U)

+#define OPAMP1_CSR_USERTRIM_Msk           (0x1UL << OPAMP1_CSR_USERTRIM_Pos)   /*!< 0x00040000 */

+#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */

+#define OPAMP1_CSR_TSTREF_Pos             (29U)

+#define OPAMP1_CSR_TSTREF_Msk             (0x1UL << OPAMP1_CSR_TSTREF_Pos)     /*!< 0x20000000 */

+#define OPAMP1_CSR_TSTREF                 OPAMP1_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */

+#define OPAMP1_CSR_CALOUT_Pos             (30U)

+#define OPAMP1_CSR_CALOUT_Msk             (0x1UL << OPAMP1_CSR_CALOUT_Pos)     /*!< 0x40000000 */

+#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */

+

+/*********************  Bit definition for OPAMP2_CSR register  ***************/

+#define OPAMP2_CSR_OPAEN_Pos              (0U)

+#define OPAMP2_CSR_OPAEN_Msk              (0x1UL << OPAMP2_CSR_OPAEN_Pos)      /*!< 0x00000001 */

+#define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */

+#define OPAMP2_CSR_FORCEVP_Pos            (1U)

+#define OPAMP2_CSR_FORCEVP_Msk            (0x1UL << OPAMP2_CSR_FORCEVP_Pos)    /*!< 0x00000002 */

+#define OPAMP2_CSR_FORCEVP                OPAMP2_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */

+

+#define OPAMP2_CSR_VPSEL_Pos              (2U)

+#define OPAMP2_CSR_VPSEL_Msk              (0x3UL << OPAMP2_CSR_VPSEL_Pos)      /*!< 0x0000000C */

+#define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */

+#define OPAMP2_CSR_VPSEL_0                (0x1UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000004 */

+#define OPAMP2_CSR_VPSEL_1                (0x2UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000008 */

+

+#define OPAMP2_CSR_VMSEL_Pos              (5U)

+#define OPAMP2_CSR_VMSEL_Msk              (0x3UL << OPAMP2_CSR_VMSEL_Pos)      /*!< 0x00000060 */

+#define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */

+#define OPAMP2_CSR_VMSEL_0                (0x1UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000020 */

+#define OPAMP2_CSR_VMSEL_1                (0x2UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000040 */

+

+#define OPAMP2_CSR_OPAHSM_Pos             (8U)

+#define OPAMP2_CSR_OPAHSM_Msk             (0x1UL << OPAMP2_CSR_OPAHSM_Pos)     /*!< 0x00000100 */

+#define OPAMP2_CSR_OPAHSM                 OPAMP2_CSR_OPAHSM_Msk                /*!< Operational amplifier2 high speed mode */

+#define OPAMP2_CSR_CALON_Pos              (11U)

+#define OPAMP2_CSR_CALON_Msk              (0x1UL << OPAMP2_CSR_CALON_Pos)      /*!< 0x00000800 */

+#define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */

+

+#define OPAMP2_CSR_CALSEL_Pos             (12U)

+#define OPAMP2_CSR_CALSEL_Msk             (0x3UL << OPAMP2_CSR_CALSEL_Pos)     /*!< 0x00003000 */

+#define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */

+#define OPAMP2_CSR_CALSEL_0               (0x1UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00001000 */

+#define OPAMP2_CSR_CALSEL_1               (0x2UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */

+

+#define OPAMP2_CSR_PGGAIN_Pos             (14U)

+#define OPAMP2_CSR_PGGAIN_Msk             (0xFUL << OPAMP2_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */

+#define OPAMP2_CSR_PGGAIN                 OPAMP2_CSR_PGGAIN_Msk                /*!< Operational amplifier2 Programmable amplifier gain value */

+#define OPAMP2_CSR_PGGAIN_0               (0x1UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00004000 */

+#define OPAMP2_CSR_PGGAIN_1               (0x2UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00008000 */

+#define OPAMP2_CSR_PGGAIN_2               (0x4UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00010000 */

+#define OPAMP2_CSR_PGGAIN_3               (0x8UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00020000 */

+

+#define OPAMP2_CSR_USERTRIM_Pos           (18U)

+#define OPAMP2_CSR_USERTRIM_Msk           (0x1UL << OPAMP2_CSR_USERTRIM_Pos)   /*!< 0x00040000 */

+#define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */

+#define OPAMP2_CSR_TSTREF_Pos             (29U)

+#define OPAMP2_CSR_TSTREF_Msk             (0x1UL << OPAMP2_CSR_TSTREF_Pos)     /*!< 0x20000000 */

+#define OPAMP2_CSR_TSTREF                 OPAMP2_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */

+#define OPAMP2_CSR_CALOUT_Pos             (30U)

+#define OPAMP2_CSR_CALOUT_Msk             (0x1UL << OPAMP2_CSR_CALOUT_Pos)     /*!< 0x40000000 */

+#define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */

+

+/*******************  Bit definition for OPAMP_OTR register  ******************/

+#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */

+#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP1_OTR register  ******************/

+#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */

+#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP2_OTR register  ******************/

+#define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */

+#define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP_HSOTR register  ****************/

+#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP_HSOTR_TRIMHSOFFSETN        OPAMP_HSOTR_TRIMHSOFFSETN_Msk         /*!< Trim for NMOS differential pairs */

+#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP_HSOTR_TRIMHSOFFSETP        OPAMP_HSOTR_TRIMHSOFFSETP_Msk         /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP1_HSOTR register  ****************/

+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP1_HSOTR_TRIMHSOFFSETN        OPAMP1_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */

+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP1_HSOTR_TRIMHSOFFSETP        OPAMP1_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP2_HSOTR register  ****************/

+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP2_HSOTR_TRIMHSOFFSETN        OPAMP2_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */

+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP2_HSOTR_TRIMHSOFFSETP        OPAMP2_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             Power Control                                  */

+/*                                                                            */

+/******************************************************************************/

+/*************************  NUMBER OF POWER DOMAINS  **************************/

+#define POWER_DOMAINS_NUMBER           3U                                      /*!< 3 Domains */

+

+/********************  Bit definition for PWR_CR1 register  *******************/

+#define PWR_CR1_ALS_Pos                (17U)

+#define PWR_CR1_ALS_Msk                (0x3UL << PWR_CR1_ALS_Pos)              /*!< 0x00060000 */

+#define PWR_CR1_ALS                    PWR_CR1_ALS_Msk                         /*!< Analog Voltage Detector level selection */

+#define PWR_CR1_ALS_0                  (0x1UL << PWR_CR1_ALS_Pos)              /*!< 0x00020000 */

+#define PWR_CR1_ALS_1                  (0x2UL << PWR_CR1_ALS_Pos)              /*!< 0x00040000 */

+#define PWR_CR1_AVDEN_Pos              (16U)

+#define PWR_CR1_AVDEN_Msk              (0x1UL << PWR_CR1_AVDEN_Pos)            /*!< 0x00010000 */

+#define PWR_CR1_AVDEN                  PWR_CR1_AVDEN_Msk                       /*!< Analog Voltage Detector Enable */

+#define PWR_CR1_SVOS_Pos               (14U)

+#define PWR_CR1_SVOS_Msk               (0x3UL << PWR_CR1_SVOS_Pos)             /*!< 0x0000C000 */

+#define PWR_CR1_SVOS                   PWR_CR1_SVOS_Msk                        /*!< System STOP mode Voltage Scaling selection */

+#define PWR_CR1_SVOS_0                 (0x1UL << PWR_CR1_SVOS_Pos)             /*!< 0x00004000 */

+#define PWR_CR1_SVOS_1                 (0x2UL << PWR_CR1_SVOS_Pos)             /*!< 0x00008000 */

+#define PWR_CR1_FLPS_Pos               (9U)

+#define PWR_CR1_FLPS_Msk               (0x1UL << PWR_CR1_FLPS_Pos)             /*!< 0x00000200 */

+#define PWR_CR1_FLPS                   PWR_CR1_FLPS_Msk                        /*!< Flash low power mode in DSTOP */

+#define PWR_CR1_DBP_Pos                (8U)

+#define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */

+#define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable Back-up domain Protection */

+#define PWR_CR1_PLS_Pos                (5U)

+#define PWR_CR1_PLS_Msk                (0x7UL << PWR_CR1_PLS_Pos)              /*!< 0x000000E0 */

+#define PWR_CR1_PLS                    PWR_CR1_PLS_Msk                         /*!< Programmable Voltage Detector level selection */

+#define PWR_CR1_PLS_0                  (0x1UL << PWR_CR1_PLS_Pos)              /*!< 0x00000020 */

+#define PWR_CR1_PLS_1                  (0x2UL << PWR_CR1_PLS_Pos)              /*!< 0x00000040 */

+#define PWR_CR1_PLS_2                  (0x4UL << PWR_CR1_PLS_Pos)              /*!< 0x00000080 */

+#define PWR_CR1_PVDEN_Pos              (4U)

+#define PWR_CR1_PVDEN_Msk              (0x1UL << PWR_CR1_PVDEN_Pos)            /*!< 0x00000010 */

+#define PWR_CR1_PVDEN                  PWR_CR1_PVDEN_Msk                       /*!< Programmable Voltage detector enable */

+#define PWR_CR1_LPDS_Pos               (0U)

+#define PWR_CR1_LPDS_Msk               (0x1UL << PWR_CR1_LPDS_Pos)             /*!< 0x00000001 */

+#define PWR_CR1_LPDS                   PWR_CR1_LPDS_Msk                        /*!< Low Power Deepsleep with SVOS3 */

+

+/*!< PVD level configuration */

+#define PWR_CR1_PLS_LEV0               (0UL)                                   /*!< PVD level 0 */

+#define PWR_CR1_PLS_LEV1_Pos           (5U)

+#define PWR_CR1_PLS_LEV1_Msk           (0x1UL << PWR_CR1_PLS_LEV1_Pos)         /*!< 0x00000020 */

+#define PWR_CR1_PLS_LEV1               PWR_CR1_PLS_LEV1_Msk                    /*!< PVD level 1 */

+#define PWR_CR1_PLS_LEV2_Pos           (6U)

+#define PWR_CR1_PLS_LEV2_Msk           (0x1UL << PWR_CR1_PLS_LEV2_Pos)         /*!< 0x00000040 */

+#define PWR_CR1_PLS_LEV2               PWR_CR1_PLS_LEV2_Msk                    /*!< PVD level 2 */

+#define PWR_CR1_PLS_LEV3_Pos           (5U)

+#define PWR_CR1_PLS_LEV3_Msk           (0x3UL << PWR_CR1_PLS_LEV3_Pos)         /*!< 0x00000060 */

+#define PWR_CR1_PLS_LEV3               PWR_CR1_PLS_LEV3_Msk                    /*!< PVD level 3 */

+#define PWR_CR1_PLS_LEV4_Pos           (7U)

+#define PWR_CR1_PLS_LEV4_Msk           (0x1UL << PWR_CR1_PLS_LEV4_Pos)         /*!< 0x00000080 */

+#define PWR_CR1_PLS_LEV4               PWR_CR1_PLS_LEV4_Msk                    /*!< PVD level 4 */

+#define PWR_CR1_PLS_LEV5_Pos           (5U)

+#define PWR_CR1_PLS_LEV5_Msk           (0x5UL << PWR_CR1_PLS_LEV5_Pos)         /*!< 0x000000A0 */

+#define PWR_CR1_PLS_LEV5               PWR_CR1_PLS_LEV5_Msk                    /*!< PVD level 5 */

+#define PWR_CR1_PLS_LEV6_Pos           (6U)

+#define PWR_CR1_PLS_LEV6_Msk           (0x3UL << PWR_CR1_PLS_LEV6_Pos)         /*!< 0x000000C0 */

+#define PWR_CR1_PLS_LEV6               PWR_CR1_PLS_LEV6_Msk                    /*!< PVD level 6 */

+#define PWR_CR1_PLS_LEV7_Pos           (5U)

+#define PWR_CR1_PLS_LEV7_Msk           (0x7UL << PWR_CR1_PLS_LEV7_Pos)         /*!< 0x000000E0 */

+#define PWR_CR1_PLS_LEV7               PWR_CR1_PLS_LEV7_Msk                    /*!< PVD level 7 */

+

+/*!< AVD level configuration */

+#define PWR_CR1_ALS_LEV0               (0UL)                                   /*!< AVD level 0 */

+#define PWR_CR1_ALS_LEV1_Pos           (17U)

+#define PWR_CR1_ALS_LEV1_Msk           (0x1UL << PWR_CR1_ALS_LEV1_Pos)         /*!< 0x00020000 */

+#define PWR_CR1_ALS_LEV1               PWR_CR1_ALS_LEV1_Msk                    /*!< AVD level 1 */

+#define PWR_CR1_ALS_LEV2_Pos           (18U)

+#define PWR_CR1_ALS_LEV2_Msk           (0x1UL << PWR_CR1_ALS_LEV2_Pos)         /*!< 0x00040000 */

+#define PWR_CR1_ALS_LEV2               PWR_CR1_ALS_LEV2_Msk                    /*!< AVD level 2 */

+#define PWR_CR1_ALS_LEV3_Pos           (17U)

+#define PWR_CR1_ALS_LEV3_Msk           (0x3UL << PWR_CR1_ALS_LEV3_Pos)         /*!< 0x00060000 */

+#define PWR_CR1_ALS_LEV3               PWR_CR1_ALS_LEV3_Msk                    /*!< AVD level 3 */

+

+/********************  Bit definition for PWR_CSR1 register  ******************/

+#define PWR_CSR1_AVDO_Pos              (16U)

+#define PWR_CSR1_AVDO_Msk              (0x1UL << PWR_CSR1_AVDO_Pos)            /*!< 0x00010000 */

+#define PWR_CSR1_AVDO                  PWR_CSR1_AVDO_Msk                       /*!< Analog Voltage Detect Output */

+#define PWR_CSR1_ACTVOS_Pos            (14U)

+#define PWR_CSR1_ACTVOS_Msk            (0x3UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x0000C000 */

+#define PWR_CSR1_ACTVOS                PWR_CSR1_ACTVOS_Msk                     /*!< Current actual used VOS for VDD11 Voltage Scaling */

+#define PWR_CSR1_ACTVOS_0              (0x1UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00004000 */

+#define PWR_CSR1_ACTVOS_1              (0x2UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00008000 */

+#define PWR_CSR1_ACTVOSRDY_Pos         (13U)

+#define PWR_CSR1_ACTVOSRDY_Msk         (0x1UL << PWR_CSR1_ACTVOSRDY_Pos)       /*!< 0x00002000 */

+#define PWR_CSR1_ACTVOSRDY             PWR_CSR1_ACTVOSRDY_Msk                  /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling  */

+#define PWR_CSR1_PVDO_Pos              (4U)

+#define PWR_CSR1_PVDO_Msk              (0x1UL << PWR_CSR1_PVDO_Pos)            /*!< 0x00000010 */

+#define PWR_CSR1_PVDO                  PWR_CSR1_PVDO_Msk                       /*!< Programmable Voltage Detect Output */

+

+/********************  Bit definition for PWR_CR2 register  *******************/

+#define PWR_CR2_TEMPH_Pos              (23U)

+#define PWR_CR2_TEMPH_Msk              (0x1UL << PWR_CR2_TEMPH_Pos)            /*!< 0x00800000 */

+#define PWR_CR2_TEMPH                  PWR_CR2_TEMPH_Msk                       /*!< Monitored temperature level above high threshold */

+#define PWR_CR2_TEMPL_Pos              (22U)

+#define PWR_CR2_TEMPL_Msk              (0x1UL << PWR_CR2_TEMPL_Pos)            /*!< 0x00400000 */

+#define PWR_CR2_TEMPL                  PWR_CR2_TEMPL_Msk                       /*!< Monitored temperature level above low threshold */

+#define PWR_CR2_VBATH_Pos              (21U)

+#define PWR_CR2_VBATH_Msk              (0x1UL << PWR_CR2_VBATH_Pos)            /*!< 0x00200000 */

+#define PWR_CR2_VBATH                  PWR_CR2_VBATH_Msk                       /*!< Monitored VBAT level above high threshold */

+#define PWR_CR2_VBATL_Pos              (20U)

+#define PWR_CR2_VBATL_Msk              (0x1UL << PWR_CR2_VBATL_Pos)            /*!< 0x00100000 */

+#define PWR_CR2_VBATL                  PWR_CR2_VBATL_Msk                       /*!< Monitored VBAT level above low threshold */

+#define PWR_CR2_BRRDY_Pos              (16U)

+#define PWR_CR2_BRRDY_Msk              (0x1UL << PWR_CR2_BRRDY_Pos)            /*!< 0x00010000 */

+#define PWR_CR2_BRRDY                  PWR_CR2_BRRDY_Msk                       /*!< Backup regulator ready */

+#define PWR_CR2_MONEN_Pos              (4U)

+#define PWR_CR2_MONEN_Msk              (0x1UL << PWR_CR2_MONEN_Pos)            /*!< 0x00000010 */

+#define PWR_CR2_MONEN                  PWR_CR2_MONEN_Msk                       /*!< VBAT and temperature monitoring enable */

+#define PWR_CR2_BREN_Pos               (0U)

+#define PWR_CR2_BREN_Msk               (0x1UL << PWR_CR2_BREN_Pos)             /*!< 0x00000001 */

+#define PWR_CR2_BREN                   PWR_CR2_BREN_Msk                        /*!< Backup regulator enable */

+

+/********************  Bit definition for PWR_CR3 register  *******************/

+#define PWR_CR3_USB33RDY_Pos           (26U)

+#define PWR_CR3_USB33RDY_Msk           (0x1UL << PWR_CR3_USB33RDY_Pos)         /*!< 0x04000000 */

+#define PWR_CR3_USB33RDY               PWR_CR3_USB33RDY_Msk                    /*!< USB supply ready */

+#define PWR_CR3_USBREGEN_Pos           (25U)

+#define PWR_CR3_USBREGEN_Msk           (0x1UL << PWR_CR3_USBREGEN_Pos)         /*!< 0x02000000 */

+#define PWR_CR3_USBREGEN               PWR_CR3_USBREGEN_Msk                    /*!< USB regulator enable */

+#define PWR_CR3_USB33DEN_Pos           (24U)

+#define PWR_CR3_USB33DEN_Msk           (0x1UL << PWR_CR3_USB33DEN_Pos)         /*!< 0x01000000 */

+#define PWR_CR3_USB33DEN               PWR_CR3_USB33DEN_Msk                    /*!< VDD33_USB voltage level detector enable */

+#define PWR_CR3_VBRS_Pos               (9U)

+#define PWR_CR3_VBRS_Msk               (0x1UL << PWR_CR3_VBRS_Pos)             /*!< 0x00000200 */

+#define PWR_CR3_VBRS                   PWR_CR3_VBRS_Msk                        /*!< VBAT charging resistor selection */

+#define PWR_CR3_VBE_Pos                (8U)

+#define PWR_CR3_VBE_Msk                (0x1UL << PWR_CR3_VBE_Pos)              /*!< 0x00000100 */

+#define PWR_CR3_VBE                    PWR_CR3_VBE_Msk                         /*!< VBAT charging enable */

+#define PWR_CR3_SCUEN_Pos              (2U)

+#define PWR_CR3_SCUEN_Msk              (0x1UL << PWR_CR3_SCUEN_Pos)            /*!< 0x00000004 */

+#define PWR_CR3_SCUEN                  PWR_CR3_SCUEN_Msk                       /*!< Supply configuration update enable */

+#define PWR_CR3_LDOEN_Pos              (1U)

+#define PWR_CR3_LDOEN_Msk              (0x1UL << PWR_CR3_LDOEN_Pos)            /*!< 0x00000002 */

+#define PWR_CR3_LDOEN                  PWR_CR3_LDOEN_Msk                       /*!< Low Drop Output regulator enable */

+#define PWR_CR3_BYPASS_Pos             (0U)

+#define PWR_CR3_BYPASS_Msk             (0x1UL << PWR_CR3_BYPASS_Pos)           /*!< 0x00000001 */

+#define PWR_CR3_BYPASS                 PWR_CR3_BYPASS_Msk                      /*!< Power Management Unit bypass */

+

+/********************  Bit definition for PWR_CPUCR register  *****************/

+#define PWR_CPUCR_RUN_D3_Pos           (11U)

+#define PWR_CPUCR_RUN_D3_Msk           (0x1UL << PWR_CPUCR_RUN_D3_Pos)         /*!< 0x00000800 */

+#define PWR_CPUCR_RUN_D3               PWR_CPUCR_RUN_D3_Msk                    /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */

+#define PWR_CPUCR_CSSF_Pos             (9U)

+#define PWR_CPUCR_CSSF_Msk             (0x1UL << PWR_CPUCR_CSSF_Pos)           /*!< 0x00000200 */

+#define PWR_CPUCR_CSSF                 PWR_CPUCR_CSSF_Msk                      /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */

+#define PWR_CPUCR_SBF_D2_Pos           (8U)

+#define PWR_CPUCR_SBF_D2_Msk           (0x1UL << PWR_CPUCR_SBF_D2_Pos)         /*!< 0x00000100 */

+#define PWR_CPUCR_SBF_D2               PWR_CPUCR_SBF_D2_Msk                    /*!< D2 domain DSTANDBY Flag */

+#define PWR_CPUCR_SBF_D1_Pos           (7U)

+#define PWR_CPUCR_SBF_D1_Msk           (0x1UL << PWR_CPUCR_SBF_D1_Pos)         /*!< 0x00000080 */

+#define PWR_CPUCR_SBF_D1               PWR_CPUCR_SBF_D1_Msk                    /*!< D1 domain DSTANDBY Flag */

+#define PWR_CPUCR_SBF_Pos              (6U)

+#define PWR_CPUCR_SBF_Msk              (0x1UL << PWR_CPUCR_SBF_Pos)            /*!< 0x00000040 */

+#define PWR_CPUCR_SBF                  PWR_CPUCR_SBF_Msk                       /*!< System STANDBY Flag */

+#define PWR_CPUCR_STOPF_Pos            (5U)

+#define PWR_CPUCR_STOPF_Msk            (0x1UL << PWR_CPUCR_STOPF_Pos)          /*!< 0x00000020 */

+#define PWR_CPUCR_STOPF                PWR_CPUCR_STOPF_Msk                     /*!< STOP Flag */

+#define PWR_CPUCR_PDDS_D3_Pos          (2U)

+#define PWR_CPUCR_PDDS_D3_Msk          (0x1UL << PWR_CPUCR_PDDS_D3_Pos)        /*!< 0x00000004 */

+#define PWR_CPUCR_PDDS_D3              PWR_CPUCR_PDDS_D3_Msk                   /*!< System D3 domain Power Down Deepsleep */

+#define PWR_CPUCR_PDDS_D2_Pos          (1U)

+#define PWR_CPUCR_PDDS_D2_Msk          (0x1UL << PWR_CPUCR_PDDS_D2_Pos)        /*!< 0x00000002 */

+#define PWR_CPUCR_PDDS_D2              PWR_CPUCR_PDDS_D2_Msk                   /*!< D2 domain Power Down Deepsleep */

+#define PWR_CPUCR_PDDS_D1_Pos          (0U)

+#define PWR_CPUCR_PDDS_D1_Msk          (0x1UL << PWR_CPUCR_PDDS_D1_Pos)        /*!< 0x00000001 */

+#define PWR_CPUCR_PDDS_D1              PWR_CPUCR_PDDS_D1_Msk                   /*!< D1 domain Power Down Deepsleep selection */

+

+

+/********************  Bit definition for PWR_D3CR register  ******************/

+#define PWR_D3CR_VOS_Pos               (14U)

+#define PWR_D3CR_VOS_Msk               (0x3UL << PWR_D3CR_VOS_Pos)             /*!< 0x0000C000 */

+#define PWR_D3CR_VOS                   PWR_D3CR_VOS_Msk                        /*!< Voltage Scaling selection according performance */

+#define PWR_D3CR_VOS_0                 (0x1UL << PWR_D3CR_VOS_Pos)             /*!< 0x00004000 */

+#define PWR_D3CR_VOS_1                 (0x2UL << PWR_D3CR_VOS_Pos)             /*!< 0x00008000 */

+#define PWR_D3CR_VOSRDY_Pos            (13U)

+#define PWR_D3CR_VOSRDY_Msk            (0x1UL << PWR_D3CR_VOSRDY_Pos)          /*!< 0x00002000 */

+#define PWR_D3CR_VOSRDY                PWR_D3CR_VOSRDY_Msk                     /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */

+

+/******************  Bit definition for PWR_WKUPCR register  ******************/

+#define PWR_WKUPCR_WKUPC6_Pos          (5U)

+#define PWR_WKUPCR_WKUPC6_Msk          (0x1UL << PWR_WKUPCR_WKUPC6_Pos)        /*!< 0x00000020 */

+#define PWR_WKUPCR_WKUPC6              PWR_WKUPCR_WKUPC6_Msk                   /*!< Clear Wakeup Pin Flag 6 */

+#define PWR_WKUPCR_WKUPC5_Pos          (4U)

+#define PWR_WKUPCR_WKUPC5_Msk          (0x1UL << PWR_WKUPCR_WKUPC5_Pos)        /*!< 0x00000010 */

+#define PWR_WKUPCR_WKUPC5              PWR_WKUPCR_WKUPC5_Msk                   /*!< Clear Wakeup Pin Flag 5 */

+#define PWR_WKUPCR_WKUPC4_Pos          (3U)

+#define PWR_WKUPCR_WKUPC4_Msk          (0x1UL << PWR_WKUPCR_WKUPC4_Pos)        /*!< 0x00000008 */

+#define PWR_WKUPCR_WKUPC4              PWR_WKUPCR_WKUPC4_Msk                   /*!< Clear Wakeup Pin Flag 4 */

+#define PWR_WKUPCR_WKUPC3_Pos          (2U)

+#define PWR_WKUPCR_WKUPC3_Msk          (0x1UL << PWR_WKUPCR_WKUPC3_Pos)        /*!< 0x00000004 */

+#define PWR_WKUPCR_WKUPC3              PWR_WKUPCR_WKUPC3_Msk                   /*!< Clear Wakeup Pin Flag 3 */

+#define PWR_WKUPCR_WKUPC2_Pos          (1U)

+#define PWR_WKUPCR_WKUPC2_Msk          (0x1UL << PWR_WKUPCR_WKUPC2_Pos)        /*!< 0x00000002 */

+#define PWR_WKUPCR_WKUPC2              PWR_WKUPCR_WKUPC2_Msk                   /*!< Clear Wakeup Pin Flag 2 */

+#define PWR_WKUPCR_WKUPC1_Pos          (0U)

+#define PWR_WKUPCR_WKUPC1_Msk          (0x1UL << PWR_WKUPCR_WKUPC1_Pos)        /*!< 0x00000001 */

+#define PWR_WKUPCR_WKUPC1              PWR_WKUPCR_WKUPC1_Msk                   /*!< Clear Wakeup Pin Flag 1 */

+

+/********************  Bit definition for PWR_WKUPFR register  ****************/

+#define PWR_WKUPFR_WKUPF6_Pos          (5U)

+#define PWR_WKUPFR_WKUPF6_Msk          (0x1UL << PWR_WKUPFR_WKUPF6_Pos)        /*!< 0x00000020 */

+#define PWR_WKUPFR_WKUPF6              PWR_WKUPFR_WKUPF6_Msk                   /*!< Wakeup Pin Flag 6 */

+#define PWR_WKUPFR_WKUPF5_Pos          (4U)

+#define PWR_WKUPFR_WKUPF5_Msk          (0x1UL << PWR_WKUPFR_WKUPF5_Pos)        /*!< 0x00000010 */

+#define PWR_WKUPFR_WKUPF5              PWR_WKUPFR_WKUPF5_Msk                   /*!< Wakeup Pin Flag 5 */

+#define PWR_WKUPFR_WKUPF4_Pos          (3U)

+#define PWR_WKUPFR_WKUPF4_Msk          (0x1UL << PWR_WKUPFR_WKUPF4_Pos)        /*!< 0x00000008 */

+#define PWR_WKUPFR_WKUPF4              PWR_WKUPFR_WKUPF4_Msk                   /*!< Wakeup Pin Flag 4 */

+#define PWR_WKUPFR_WKUPF3_Pos          (2U)

+#define PWR_WKUPFR_WKUPF3_Msk          (0x1UL << PWR_WKUPFR_WKUPF3_Pos)        /*!< 0x00000004 */

+#define PWR_WKUPFR_WKUPF3              PWR_WKUPFR_WKUPF3_Msk                   /*!< Wakeup Pin Flag 3 */

+#define PWR_WKUPFR_WKUPF2_Pos          (1U)

+#define PWR_WKUPFR_WKUPF2_Msk          (0x1UL << PWR_WKUPFR_WKUPF2_Pos)        /*!< 0x00000002 */

+#define PWR_WKUPFR_WKUPF2              PWR_WKUPFR_WKUPF2_Msk                   /*!< Wakeup Pin Flag 2 */

+#define PWR_WKUPFR_WKUPF1_Pos          (0U)

+#define PWR_WKUPFR_WKUPF1_Msk          (0x1UL << PWR_WKUPFR_WKUPF1_Pos)        /*!< 0x00000001 */

+#define PWR_WKUPFR_WKUPF1              PWR_WKUPFR_WKUPF1_Msk                   /*!< Wakeup Pin Flag 1 */

+

+/******************  Bit definition for PWR_WKUPEPR register  *****************/

+#define PWR_WKUPEPR_WKUPPUPD6_Pos      (26U)

+#define PWR_WKUPEPR_WKUPPUPD6_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x0C000000 */

+#define PWR_WKUPEPR_WKUPPUPD6          PWR_WKUPEPR_WKUPPUPD6_Msk               /*!< Wakeup Pin pull configuration for WKUP6 */

+#define PWR_WKUPEPR_WKUPPUPD6_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x04000000 */

+#define PWR_WKUPEPR_WKUPPUPD6_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x08000000 */

+#define PWR_WKUPEPR_WKUPPUPD5_Pos      (24U)

+#define PWR_WKUPEPR_WKUPPUPD5_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x03000000 */

+#define PWR_WKUPEPR_WKUPPUPD5          PWR_WKUPEPR_WKUPPUPD5_Msk               /*!< Wakeup Pin pull configuration for WKUP5 */

+#define PWR_WKUPEPR_WKUPPUPD5_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x01000000 */

+#define PWR_WKUPEPR_WKUPPUPD5_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x02000000 */

+#define PWR_WKUPEPR_WKUPPUPD4_Pos      (22U)

+#define PWR_WKUPEPR_WKUPPUPD4_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00C00000 */

+#define PWR_WKUPEPR_WKUPPUPD4          PWR_WKUPEPR_WKUPPUPD4_Msk               /*!< Wakeup Pin pull configuration for WKUP4 */

+#define PWR_WKUPEPR_WKUPPUPD4_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00400000 */

+#define PWR_WKUPEPR_WKUPPUPD4_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00800000 */

+#define PWR_WKUPEPR_WKUPPUPD3_Pos      (20U)

+#define PWR_WKUPEPR_WKUPPUPD3_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00300000 */

+#define PWR_WKUPEPR_WKUPPUPD3          PWR_WKUPEPR_WKUPPUPD3_Msk               /*!< Wakeup Pin pull configuration for WKUP3 */

+#define PWR_WKUPEPR_WKUPPUPD3_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00100000 */

+#define PWR_WKUPEPR_WKUPPUPD3_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00200000 */

+#define PWR_WKUPEPR_WKUPPUPD2_Pos      (18U)

+#define PWR_WKUPEPR_WKUPPUPD2_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x000C0000 */

+#define PWR_WKUPEPR_WKUPPUPD2          PWR_WKUPEPR_WKUPPUPD2_Msk               /*!< Wakeup Pin pull configuration for WKUP2 */

+#define PWR_WKUPEPR_WKUPPUPD2_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00040000 */

+#define PWR_WKUPEPR_WKUPPUPD2_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00080000 */

+#define PWR_WKUPEPR_WKUPPUPD1_Pos      (16U)

+#define PWR_WKUPEPR_WKUPPUPD1_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00030000 */

+#define PWR_WKUPEPR_WKUPPUPD1          PWR_WKUPEPR_WKUPPUPD1_Msk               /*!< Wakeup Pin pull configuration for WKUP1 */

+#define PWR_WKUPEPR_WKUPPUPD1_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00010000 */

+#define PWR_WKUPEPR_WKUPPUPD1_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00020000 */

+#define PWR_WKUPEPR_WKUPP6_Pos         (13U)

+#define PWR_WKUPEPR_WKUPP6_Msk         (0x1UL << PWR_WKUPEPR_WKUPP6_Pos)       /*!< 0x00002000 */

+#define PWR_WKUPEPR_WKUPP6             PWR_WKUPEPR_WKUPP6_Msk                  /*!< Wakeup Pin Polarity for WKUP6 */

+#define PWR_WKUPEPR_WKUPP5_Pos         (12U)

+#define PWR_WKUPEPR_WKUPP5_Msk         (0x1UL << PWR_WKUPEPR_WKUPP5_Pos)       /*!< 0x00001000 */

+#define PWR_WKUPEPR_WKUPP5             PWR_WKUPEPR_WKUPP5_Msk                  /*!< Wakeup Pin Polarity for WKUP5 */

+#define PWR_WKUPEPR_WKUPP4_Pos         (11U)

+#define PWR_WKUPEPR_WKUPP4_Msk         (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)       /*!< 0x00000800 */

+#define PWR_WKUPEPR_WKUPP4             PWR_WKUPEPR_WKUPP4_Msk                  /*!< Wakeup Pin Polarity for WKUP4 */

+#define PWR_WKUPEPR_WKUPP3_Pos         (10U)

+#define PWR_WKUPEPR_WKUPP3_Msk         (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)       /*!< 0x00000400 */

+#define PWR_WKUPEPR_WKUPP3             PWR_WKUPEPR_WKUPP3_Msk                  /*!< Wakeup Pin Polarity for WKUP3 */

+#define PWR_WKUPEPR_WKUPP2_Pos         (9U)

+#define PWR_WKUPEPR_WKUPP2_Msk         (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)       /*!< 0x00000200 */

+#define PWR_WKUPEPR_WKUPP2             PWR_WKUPEPR_WKUPP2_Msk                  /*!< Wakeup Pin Polarity for WKUP2 */

+#define PWR_WKUPEPR_WKUPP1_Pos         (8U)

+#define PWR_WKUPEPR_WKUPP1_Msk         (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)       /*!< 0x00000100 */

+#define PWR_WKUPEPR_WKUPP1             PWR_WKUPEPR_WKUPP1_Msk                  /*!< Wakeup Pin Polarity for WKUP1 */

+#define PWR_WKUPEPR_WKUPEN6_Pos        (5U)

+#define PWR_WKUPEPR_WKUPEN6_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos)      /*!< 0x00000020 */

+#define PWR_WKUPEPR_WKUPEN6            PWR_WKUPEPR_WKUPEN6_Msk                 /*!< Enable Wakeup Pin WKUP6 */

+#define PWR_WKUPEPR_WKUPEN5_Pos        (4U)

+#define PWR_WKUPEPR_WKUPEN5_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos)      /*!< 0x00000010 */

+#define PWR_WKUPEPR_WKUPEN5            PWR_WKUPEPR_WKUPEN5_Msk                 /*!< Enable Wakeup Pin WKUP5 */

+#define PWR_WKUPEPR_WKUPEN4_Pos        (3U)

+#define PWR_WKUPEPR_WKUPEN4_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)      /*!< 0x00000008 */

+#define PWR_WKUPEPR_WKUPEN4            PWR_WKUPEPR_WKUPEN4_Msk                 /*!< Enable Wakeup Pin WKUP4 */

+#define PWR_WKUPEPR_WKUPEN3_Pos        (2U)

+#define PWR_WKUPEPR_WKUPEN3_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)      /*!< 0x00000004 */

+#define PWR_WKUPEPR_WKUPEN3            PWR_WKUPEPR_WKUPEN3_Msk                 /*!< Enable Wakeup Pin WKUP3 */

+#define PWR_WKUPEPR_WKUPEN2_Pos        (1U)

+#define PWR_WKUPEPR_WKUPEN2_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)      /*!< 0x00000002 */

+#define PWR_WKUPEPR_WKUPEN2            PWR_WKUPEPR_WKUPEN2_Msk                 /*!< Enable Wakeup Pin WKUP2 */

+#define PWR_WKUPEPR_WKUPEN1_Pos        (0U)

+#define PWR_WKUPEPR_WKUPEN1_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)      /*!< 0x00000001 */

+#define PWR_WKUPEPR_WKUPEN1            PWR_WKUPEPR_WKUPEN1_Msk                 /*!< Enable Wakeup Pin WKUP1 */

+#define PWR_WKUPEPR_WKUPEN_Pos         (0U)

+#define PWR_WKUPEPR_WKUPEN_Msk         (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos)      /*!< 0x0000003F */

+#define PWR_WKUPEPR_WKUPEN             PWR_WKUPEPR_WKUPEN_Msk                  /*!< Enable all Wakeup Pin */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Reset and Clock Control                            */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  RCC VERSION  ********************************/

+#define RCC_VER_X

+

+/********************  Bit definition for RCC_CR register  ********************/

+#define RCC_CR_HSION_Pos                       (0U)

+#define RCC_CR_HSION_Msk                       (0x1UL << RCC_CR_HSION_Pos)     /*!< 0x00000001 */

+#define RCC_CR_HSION                           RCC_CR_HSION_Msk                /*!< Internal High Speed clock enable */

+#define RCC_CR_HSIKERON_Pos                    (1U)

+#define RCC_CR_HSIKERON_Msk                    (0x1UL << RCC_CR_HSIKERON_Pos)  /*!< 0x00000002 */

+#define RCC_CR_HSIKERON                        RCC_CR_HSIKERON_Msk             /*!< Internal High Speed clock enable for some IPs Kernel */

+#define RCC_CR_HSIRDY_Pos                      (2U)

+#define RCC_CR_HSIRDY_Msk                      (0x1UL << RCC_CR_HSIRDY_Pos)    /*!< 0x00000004 */

+#define RCC_CR_HSIRDY                          RCC_CR_HSIRDY_Msk               /*!< Internal High Speed clock ready flag */

+#define RCC_CR_HSIDIV_Pos                      (3U)

+#define RCC_CR_HSIDIV_Msk                      (0x3UL << RCC_CR_HSIDIV_Pos)    /*!< 0x00000018 */

+#define RCC_CR_HSIDIV                          RCC_CR_HSIDIV_Msk               /*!< Internal High Speed clock divider selection */

+#define RCC_CR_HSIDIV_1                        (0x0UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000000 */

+#define RCC_CR_HSIDIV_2                        (0x1UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000008 */

+#define RCC_CR_HSIDIV_4                        (0x2UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000010 */

+#define RCC_CR_HSIDIV_8                        (0x3UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000018 */

+

+#define RCC_CR_HSIDIVF_Pos                     (5U)

+#define RCC_CR_HSIDIVF_Msk                     (0x1UL << RCC_CR_HSIDIVF_Pos)   /*!< 0x00000020 */

+#define RCC_CR_HSIDIVF                         RCC_CR_HSIDIVF_Msk              /*!< HSI Divider flag */

+#define RCC_CR_CSION_Pos                       (7U)

+#define RCC_CR_CSION_Msk                       (0x1UL << RCC_CR_CSION_Pos)     /*!< 0x00000080 */

+#define RCC_CR_CSION                           RCC_CR_CSION_Msk                /*!< The Internal RC 4MHz oscillator clock enable */

+#define RCC_CR_CSIRDY_Pos                      (8U)

+#define RCC_CR_CSIRDY_Msk                      (0x1UL << RCC_CR_CSIRDY_Pos)    /*!< 0x00000100 */

+#define RCC_CR_CSIRDY                          RCC_CR_CSIRDY_Msk               /*!< The Internal RC 4MHz oscillator clock ready */

+#define RCC_CR_CSIKERON_Pos                    (9U)

+#define RCC_CR_CSIKERON_Msk                    (0x1UL << RCC_CR_CSIKERON_Pos)  /*!< 0x00000200 */

+#define RCC_CR_CSIKERON                        RCC_CR_CSIKERON_Msk             /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */

+#define RCC_CR_HSI48ON_Pos                     (12U)

+#define RCC_CR_HSI48ON_Msk                     (0x1UL << RCC_CR_HSI48ON_Pos)   /*!< 0x00001000 */

+#define RCC_CR_HSI48ON                         RCC_CR_HSI48ON_Msk              /*!< HSI48 clock enable clock enable  */

+#define RCC_CR_HSI48RDY_Pos                    (13U)

+#define RCC_CR_HSI48RDY_Msk                    (0x1UL << RCC_CR_HSI48RDY_Pos)  /*!< 0x00002000 */

+#define RCC_CR_HSI48RDY                        RCC_CR_HSI48RDY_Msk             /*!< HSI48 clock ready */

+

+#define RCC_CR_D1CKRDY_Pos                     (14U)

+#define RCC_CR_D1CKRDY_Msk                     (0x1UL << RCC_CR_D1CKRDY_Pos)   /*!< 0x00004000 */

+#define RCC_CR_D1CKRDY                         RCC_CR_D1CKRDY_Msk              /*!< D1 domain clocks ready flag  */

+#define RCC_CR_D2CKRDY_Pos                     (15U)

+#define RCC_CR_D2CKRDY_Msk                     (0x1UL << RCC_CR_D2CKRDY_Pos)   /*!< 0x00008000 */

+#define RCC_CR_D2CKRDY                         RCC_CR_D2CKRDY_Msk              /*!< D2 domain clocks ready flag */

+

+#define RCC_CR_HSEON_Pos                       (16U)

+#define RCC_CR_HSEON_Msk                       (0x1UL << RCC_CR_HSEON_Pos)     /*!< 0x00010000 */

+#define RCC_CR_HSEON                           RCC_CR_HSEON_Msk                /*!< External High Speed clock enable */

+#define RCC_CR_HSERDY_Pos                      (17U)

+#define RCC_CR_HSERDY_Msk                      (0x1UL << RCC_CR_HSERDY_Pos)    /*!< 0x00020000 */

+#define RCC_CR_HSERDY                          RCC_CR_HSERDY_Msk               /*!< External High Speed clock ready */

+#define RCC_CR_HSEBYP_Pos                      (18U)

+#define RCC_CR_HSEBYP_Msk                      (0x1UL << RCC_CR_HSEBYP_Pos)    /*!< 0x00040000 */

+#define RCC_CR_HSEBYP                          RCC_CR_HSEBYP_Msk               /*!< External High Speed clock Bypass */

+#define RCC_CR_CSSHSEON_Pos                    (19U)

+#define RCC_CR_CSSHSEON_Msk                    (0x1UL << RCC_CR_CSSHSEON_Pos)  /*!< 0x00080000 */

+#define RCC_CR_CSSHSEON                        RCC_CR_CSSHSEON_Msk             /*!< HSE Clock security System enable */

+

+

+#define RCC_CR_PLL1ON_Pos                      (24U)

+#define RCC_CR_PLL1ON_Msk                      (0x1UL << RCC_CR_PLL1ON_Pos)    /*!< 0x01000000 */

+#define RCC_CR_PLL1ON                          RCC_CR_PLL1ON_Msk               /*!< System PLL1 clock enable */

+#define RCC_CR_PLL1RDY_Pos                     (25U)

+#define RCC_CR_PLL1RDY_Msk                     (0x1UL << RCC_CR_PLL1RDY_Pos)   /*!< 0x02000000 */

+#define RCC_CR_PLL1RDY                         RCC_CR_PLL1RDY_Msk              /*!< System PLL1 clock ready */

+#define RCC_CR_PLL2ON_Pos                      (26U)

+#define RCC_CR_PLL2ON_Msk                      (0x1UL << RCC_CR_PLL2ON_Pos)    /*!< 0x04000000 */

+#define RCC_CR_PLL2ON                          RCC_CR_PLL2ON_Msk               /*!< System PLL2 clock enable */

+#define RCC_CR_PLL2RDY_Pos                     (27U)

+#define RCC_CR_PLL2RDY_Msk                     (0x1UL << RCC_CR_PLL2RDY_Pos)   /*!< 0x08000000 */

+#define RCC_CR_PLL2RDY                         RCC_CR_PLL2RDY_Msk              /*!< System PLL2 clock ready */

+#define RCC_CR_PLL3ON_Pos                      (28U)

+#define RCC_CR_PLL3ON_Msk                      (0x1UL << RCC_CR_PLL3ON_Pos)    /*!< 0x10000000 */

+#define RCC_CR_PLL3ON                          RCC_CR_PLL3ON_Msk               /*!< System PLL3 clock enable */

+#define RCC_CR_PLL3RDY_Pos                     (29U)

+#define RCC_CR_PLL3RDY_Msk                     (0x1UL << RCC_CR_PLL3RDY_Pos)   /*!< 0x20000000 */

+#define RCC_CR_PLL3RDY                         RCC_CR_PLL3RDY_Msk              /*!< System PLL3 clock ready */

+

+/*Legacy */

+#define RCC_CR_PLLON_Pos                       (24U)

+#define RCC_CR_PLLON_Msk                       (0x1UL << RCC_CR_PLLON_Pos)     /*!< 0x01000000 */

+#define RCC_CR_PLLON                           RCC_CR_PLLON_Msk                /*!< System PLL clock enable */

+#define RCC_CR_PLLRDY_Pos                      (25U)

+#define RCC_CR_PLLRDY_Msk                      (0x1UL << RCC_CR_PLLRDY_Pos)    /*!< 0x02000000 */

+#define RCC_CR_PLLRDY                          RCC_CR_PLLRDY_Msk               /*!< System PLL clock ready */

+

+/********************  Bit definition for RCC_HSICFGR register  ***************/

+/*!< HSICAL configuration */

+#define RCC_HSICFGR_HSICAL_Pos                 (0U)

+#define RCC_HSICFGR_HSICAL_Msk                 (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */

+#define RCC_HSICFGR_HSICAL                     RCC_HSICFGR_HSICAL_Msk          /*!< HSICAL[11:0] bits */

+#define RCC_HSICFGR_HSICAL_0                   (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */

+#define RCC_HSICFGR_HSICAL_1                   (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */

+#define RCC_HSICFGR_HSICAL_2                   (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */

+#define RCC_HSICFGR_HSICAL_3                   (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */

+#define RCC_HSICFGR_HSICAL_4                   (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */

+#define RCC_HSICFGR_HSICAL_5                   (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */

+#define RCC_HSICFGR_HSICAL_6                   (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */

+#define RCC_HSICFGR_HSICAL_7                   (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */

+#define RCC_HSICFGR_HSICAL_8                   (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */

+#define RCC_HSICFGR_HSICAL_9                   (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */

+#define RCC_HSICFGR_HSICAL_10                  (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */

+#define RCC_HSICFGR_HSICAL_11                  (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */

+

+/*!< HSITRIM configuration */

+#define RCC_HSICFGR_HSITRIM_Pos                (24U)

+#define RCC_HSICFGR_HSITRIM_Msk                (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */

+#define RCC_HSICFGR_HSITRIM                    RCC_HSICFGR_HSITRIM_Msk         /*!< HSITRIM[6:0] bits */

+#define RCC_HSICFGR_HSITRIM_0                  (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */

+#define RCC_HSICFGR_HSITRIM_1                  (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */

+#define RCC_HSICFGR_HSITRIM_2                  (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */

+#define RCC_HSICFGR_HSITRIM_3                  (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */

+#define RCC_HSICFGR_HSITRIM_4                  (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */

+#define RCC_HSICFGR_HSITRIM_5                  (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */

+#define RCC_HSICFGR_HSITRIM_6                  (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */

+

+

+/********************  Bit definition for RCC_CRRCR register  *****************/

+

+/*!< HSI48CAL configuration */

+#define RCC_CRRCR_HSI48CAL_Pos                 (0U)

+#define RCC_CRRCR_HSI48CAL_Msk                 (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */

+#define RCC_CRRCR_HSI48CAL                     RCC_CRRCR_HSI48CAL_Msk          /*!< HSI48CAL[9:0] bits */

+#define RCC_CRRCR_HSI48CAL_0                   (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */

+#define RCC_CRRCR_HSI48CAL_1                   (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */

+#define RCC_CRRCR_HSI48CAL_2                   (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */

+#define RCC_CRRCR_HSI48CAL_3                   (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */

+#define RCC_CRRCR_HSI48CAL_4                   (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */

+#define RCC_CRRCR_HSI48CAL_5                   (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */

+#define RCC_CRRCR_HSI48CAL_6                   (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */

+#define RCC_CRRCR_HSI48CAL_7                   (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */

+#define RCC_CRRCR_HSI48CAL_8                   (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */

+#define RCC_CRRCR_HSI48CAL_9                   (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */

+

+

+/********************  Bit definition for RCC_CSICFGR register  *****************/

+/*!< CSICAL configuration */

+#define RCC_CSICFGR_CSICAL_Pos                 (0U)

+#define RCC_CSICFGR_CSICAL_Msk                 (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */

+#define RCC_CSICFGR_CSICAL                     RCC_CSICFGR_CSICAL_Msk          /*!< CSICAL[7:0] bits */

+#define RCC_CSICFGR_CSICAL_0                   (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */

+#define RCC_CSICFGR_CSICAL_1                   (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */

+#define RCC_CSICFGR_CSICAL_2                   (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */

+#define RCC_CSICFGR_CSICAL_3                   (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */

+#define RCC_CSICFGR_CSICAL_4                   (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */

+#define RCC_CSICFGR_CSICAL_5                   (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */

+#define RCC_CSICFGR_CSICAL_6                   (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */

+#define RCC_CSICFGR_CSICAL_7                   (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */

+

+/*!< CSITRIM configuration */

+#define RCC_CSICFGR_CSITRIM_Pos                (24U)

+#define RCC_CSICFGR_CSITRIM_Msk                (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */

+#define RCC_CSICFGR_CSITRIM                    RCC_CSICFGR_CSITRIM_Msk         /*!< CSITRIM[5:0] bits */

+#define RCC_CSICFGR_CSITRIM_0                  (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */

+#define RCC_CSICFGR_CSITRIM_1                  (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */

+#define RCC_CSICFGR_CSITRIM_2                  (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */

+#define RCC_CSICFGR_CSITRIM_3                  (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */

+#define RCC_CSICFGR_CSITRIM_4                  (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */

+#define RCC_CSICFGR_CSITRIM_5                  (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */

+

+/********************  Bit definition for RCC_CFGR register  ******************/

+/*!< SW configuration */

+#define RCC_CFGR_SW_Pos                        (0U)

+#define RCC_CFGR_SW_Msk                        (0x7UL << RCC_CFGR_SW_Pos)           /*!< 0x00000007 */

+#define RCC_CFGR_SW                            RCC_CFGR_SW_Msk                     /*!< SW[2:0] bits (System clock Switch) */

+#define RCC_CFGR_SW_0                          (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */

+#define RCC_CFGR_SW_1                          (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */

+#define RCC_CFGR_SW_2                          (0x4UL << RCC_CFGR_SW_Pos)           /*!< 0x00000004 */

+

+#define RCC_CFGR_SW_HSI                        (0x00000000UL)                       /*!< HSI selection as system clock */

+#define RCC_CFGR_SW_CSI                        (0x00000001UL)                       /*!< CSI selection as system clock */

+#define RCC_CFGR_SW_HSE                        (0x00000002UL)                       /*!< HSE selection as system clock */

+#define RCC_CFGR_SW_PLL1                       (0x00000003UL)                       /*!< PLL1 selection as system clock */

+

+/*!< SWS configuration */

+#define RCC_CFGR_SWS_Pos                       (3U)

+#define RCC_CFGR_SWS_Msk                       (0x7UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000038 */

+#define RCC_CFGR_SWS                           RCC_CFGR_SWS_Msk                    /*!< SWS[2:0] bits (System Clock Switch Status) */

+#define RCC_CFGR_SWS_0                         (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */

+#define RCC_CFGR_SWS_1                         (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000010 */

+#define RCC_CFGR_SWS_2                         (0x4UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000020 */

+

+#define RCC_CFGR_SWS_HSI                       (0x00000000UL)                       /*!< HSI used as system clock */

+#define RCC_CFGR_SWS_CSI                       (0x00000008UL)                       /*!< CSI used as system clock */

+#define RCC_CFGR_SWS_HSE                       (0x00000010UL)                       /*!< HSE used as system clock */

+#define RCC_CFGR_SWS_PLL1                      (0x00000018UL)                       /*!< PLL1 used as system clock */

+

+#define RCC_CFGR_STOPWUCK_Pos                  (6U)

+#define RCC_CFGR_STOPWUCK_Msk                  (0x1UL << RCC_CFGR_STOPWUCK_Pos)     /*!< 0x00000040 */

+#define RCC_CFGR_STOPWUCK                      RCC_CFGR_STOPWUCK_Msk                /*!< Wake Up from stop and CSS backup clock selection */

+

+#define RCC_CFGR_STOPKERWUCK_Pos               (7U)

+#define RCC_CFGR_STOPKERWUCK_Msk               (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)  /*!< 0x00000080 */

+#define RCC_CFGR_STOPKERWUCK                   RCC_CFGR_STOPKERWUCK_Msk             /*!< Kernel Clock Selection after a Wake Up from STOP */

+

+/*!< RTCPRE configuration */

+#define RCC_CFGR_RTCPRE_Pos                    (8U)

+#define RCC_CFGR_RTCPRE_Msk                    (0x3FUL << RCC_CFGR_RTCPRE_Pos)

+#define RCC_CFGR_RTCPRE                        RCC_CFGR_RTCPRE_Msk                  /*!< 0x00003F00 */

+#define RCC_CFGR_RTCPRE_0                      (0x1UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000100 */

+#define RCC_CFGR_RTCPRE_1                      (0x2UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000200 */

+#define RCC_CFGR_RTCPRE_2                      (0x4UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000400 */

+#define RCC_CFGR_RTCPRE_3                      (0x8UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000800 */

+#define RCC_CFGR_RTCPRE_4                      (0x10UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00001000 */

+#define RCC_CFGR_RTCPRE_5                      (0x20UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00002000 */

+

+/*!< HRTIMSEL configuration */

+#define RCC_CFGR_HRTIMSEL_Pos                  (14U)

+#define RCC_CFGR_HRTIMSEL_Msk                  (0x1UL << RCC_CFGR_HRTIMSEL_Pos)

+#define RCC_CFGR_HRTIMSEL                      RCC_CFGR_HRTIMSEL_Msk                /*!< 0x00004000 */

+

+/*!< TIMPRE configuration */

+#define RCC_CFGR_TIMPRE_Pos                    (15U)

+#define RCC_CFGR_TIMPRE_Msk                    (0x1UL << RCC_CFGR_TIMPRE_Pos)

+#define RCC_CFGR_TIMPRE                        RCC_CFGR_TIMPRE_Msk                  /*!< 0x00008000 */

+

+/*!< MCO1 configuration */

+#define RCC_CFGR_MCO1_Pos                      (22U)

+#define RCC_CFGR_MCO1_Msk                      (0x7UL << RCC_CFGR_MCO1_Pos)

+#define RCC_CFGR_MCO1                          RCC_CFGR_MCO1_Msk                       /*!< 0x01C00000 */

+#define RCC_CFGR_MCO1_0                        (0x1UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00400000 */

+#define RCC_CFGR_MCO1_1                        (0x2UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00800000 */

+#define RCC_CFGR_MCO1_2                        (0x4UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x01000000 */

+

+#define RCC_CFGR_MCO1PRE_Pos                   (18U)

+#define RCC_CFGR_MCO1PRE_Msk                   (0xFUL << RCC_CFGR_MCO1PRE_Pos)

+#define RCC_CFGR_MCO1PRE                       RCC_CFGR_MCO1PRE_Msk                    /*!< 0x003C0000 */

+#define RCC_CFGR_MCO1PRE_0                     (0x1UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00040000 */

+#define RCC_CFGR_MCO1PRE_1                     (0x2UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00080000 */

+#define RCC_CFGR_MCO1PRE_2                     (0x4UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00100000 */

+#define RCC_CFGR_MCO1PRE_3                     (0x8UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00200000 */

+

+#define RCC_CFGR_MCO2PRE_Pos                   (25U)

+#define RCC_CFGR_MCO2PRE_Msk                   (0xFUL << RCC_CFGR_MCO2PRE_Pos)

+#define RCC_CFGR_MCO2PRE                       RCC_CFGR_MCO2PRE_Msk                    /*!< 0x1E000000 */

+#define RCC_CFGR_MCO2PRE_0                     (0x1UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x02000000 */

+#define RCC_CFGR_MCO2PRE_1                     (0x2UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x04000000 */

+#define RCC_CFGR_MCO2PRE_2                     (0x4UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x08000000 */

+#define RCC_CFGR_MCO2PRE_3                     (0x8UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x10000000 */

+

+#define RCC_CFGR_MCO2_Pos                      (29U)

+#define RCC_CFGR_MCO2_Msk                      (0x7UL << RCC_CFGR_MCO2_Pos)

+#define RCC_CFGR_MCO2                          RCC_CFGR_MCO2_Msk                       /*!< 0xE0000000 */

+#define RCC_CFGR_MCO2_0                        (0x1UL << RCC_CFGR_MCO2_Pos)             /*!< 0x20000000 */

+#define RCC_CFGR_MCO2_1                        (0x2UL << RCC_CFGR_MCO2_Pos)             /*!< 0x40000000 */

+#define RCC_CFGR_MCO2_2                        (0x4UL << RCC_CFGR_MCO2_Pos)             /*!< 0x80000000 */

+

+/********************  Bit definition for RCC_D1CFGR register  ******************/

+/*!< D1HPRE configuration */

+#define RCC_D1CFGR_HPRE_Pos                    (0U)

+#define RCC_D1CFGR_HPRE_Msk                    (0xFUL << RCC_D1CFGR_HPRE_Pos)  /*!< 0x0000000F */

+#define RCC_D1CFGR_HPRE                        RCC_D1CFGR_HPRE_Msk             /*!< HPRE[3:0] bits (AHB3 prescaler) */

+#define RCC_D1CFGR_HPRE_0                      (0x1UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000001 */

+#define RCC_D1CFGR_HPRE_1                      (0x2UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000002 */

+#define RCC_D1CFGR_HPRE_2                      (0x4UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000004 */

+#define RCC_D1CFGR_HPRE_3                      (0x8UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000008 */

+

+

+#define RCC_D1CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)          /*!< AHB3 Clock not divided */

+#define RCC_D1CFGR_HPRE_DIV2_Pos               (3U)

+#define RCC_D1CFGR_HPRE_DIV2_Msk               (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */

+#define RCC_D1CFGR_HPRE_DIV2                   RCC_D1CFGR_HPRE_DIV2_Msk        /*!< AHB3 Clock divided by 2 */

+#define RCC_D1CFGR_HPRE_DIV4_Pos               (0U)

+#define RCC_D1CFGR_HPRE_DIV4_Msk               (0x9UL << RCC_D1CFGR_HPRE_DIV4_Pos) /*!< 0x00000009 */

+#define RCC_D1CFGR_HPRE_DIV4                   RCC_D1CFGR_HPRE_DIV4_Msk        /*!< AHB3 Clock divided by 4 */

+#define RCC_D1CFGR_HPRE_DIV8_Pos               (1U)

+#define RCC_D1CFGR_HPRE_DIV8_Msk               (0x5UL << RCC_D1CFGR_HPRE_DIV8_Pos) /*!< 0x0000000A */

+#define RCC_D1CFGR_HPRE_DIV8                   RCC_D1CFGR_HPRE_DIV8_Msk        /*!< AHB3 Clock divided by 8 */

+#define RCC_D1CFGR_HPRE_DIV16_Pos              (0U)

+#define RCC_D1CFGR_HPRE_DIV16_Msk              (0xBUL << RCC_D1CFGR_HPRE_DIV16_Pos) /*!< 0x0000000B */

+#define RCC_D1CFGR_HPRE_DIV16                  RCC_D1CFGR_HPRE_DIV16_Msk       /*!< AHB3 Clock divided by 16 */

+#define RCC_D1CFGR_HPRE_DIV64_Pos              (2U)

+#define RCC_D1CFGR_HPRE_DIV64_Msk              (0x3UL << RCC_D1CFGR_HPRE_DIV64_Pos) /*!< 0x0000000C */

+#define RCC_D1CFGR_HPRE_DIV64                  RCC_D1CFGR_HPRE_DIV64_Msk       /*!< AHB3 Clock divided by 64 */

+#define RCC_D1CFGR_HPRE_DIV128_Pos             (0U)

+#define RCC_D1CFGR_HPRE_DIV128_Msk             (0xDUL << RCC_D1CFGR_HPRE_DIV128_Pos) /*!< 0x0000000D */

+#define RCC_D1CFGR_HPRE_DIV128                 RCC_D1CFGR_HPRE_DIV128_Msk      /*!< AHB3 Clock divided by 128 */

+#define RCC_D1CFGR_HPRE_DIV256_Pos             (1U)

+#define RCC_D1CFGR_HPRE_DIV256_Msk             (0x7UL << RCC_D1CFGR_HPRE_DIV256_Pos) /*!< 0x0000000E */

+#define RCC_D1CFGR_HPRE_DIV256                 RCC_D1CFGR_HPRE_DIV256_Msk      /*!< AHB3 Clock divided by 256 */

+#define RCC_D1CFGR_HPRE_DIV512_Pos             (0U)

+#define RCC_D1CFGR_HPRE_DIV512_Msk             (0xFUL << RCC_D1CFGR_HPRE_DIV512_Pos) /*!< 0x0000000F */

+#define RCC_D1CFGR_HPRE_DIV512                 RCC_D1CFGR_HPRE_DIV512_Msk      /*!< AHB3 Clock divided by 512 */

+

+/*!< D1PPRE configuration */

+#define RCC_D1CFGR_D1PPRE_Pos                  (4U)

+#define RCC_D1CFGR_D1PPRE_Msk                  (0x7UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000070 */

+#define RCC_D1CFGR_D1PPRE                      RCC_D1CFGR_D1PPRE_Msk           /*!< D1PRE[2:0] bits (APB3 prescaler) */

+#define RCC_D1CFGR_D1PPRE_0                    (0x1UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000010 */

+#define RCC_D1CFGR_D1PPRE_1                    (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */

+#define RCC_D1CFGR_D1PPRE_2                    (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */

+

+#define RCC_D1CFGR_D1PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB3 clock not divided */

+#define RCC_D1CFGR_D1PPRE_DIV2_Pos             (6U)

+#define RCC_D1CFGR_D1PPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_D1CFGR_D1PPRE_DIV2                 RCC_D1CFGR_D1PPRE_DIV2_Msk      /*!< APB3 clock divided by 2 */

+#define RCC_D1CFGR_D1PPRE_DIV4_Pos             (4U)

+#define RCC_D1CFGR_D1PPRE_DIV4_Msk             (0x5UL << RCC_D1CFGR_D1PPRE_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_D1CFGR_D1PPRE_DIV4                 RCC_D1CFGR_D1PPRE_DIV4_Msk      /*!< APB3 clock divided by 4 */

+#define RCC_D1CFGR_D1PPRE_DIV8_Pos             (5U)

+#define RCC_D1CFGR_D1PPRE_DIV8_Msk             (0x3UL << RCC_D1CFGR_D1PPRE_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_D1CFGR_D1PPRE_DIV8                 RCC_D1CFGR_D1PPRE_DIV8_Msk      /*!< APB3 clock divided by 8 */

+#define RCC_D1CFGR_D1PPRE_DIV16_Pos            (4U)

+#define RCC_D1CFGR_D1PPRE_DIV16_Msk            (0x7UL << RCC_D1CFGR_D1PPRE_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_D1CFGR_D1PPRE_DIV16                RCC_D1CFGR_D1PPRE_DIV16_Msk     /*!< APB3 clock divided by 16 */

+

+#define RCC_D1CFGR_D1CPRE_Pos                  (8U)

+#define RCC_D1CFGR_D1CPRE_Msk                  (0xFUL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000F00 */

+#define RCC_D1CFGR_D1CPRE                      RCC_D1CFGR_D1CPRE_Msk           /*!< D1CPRE[2:0] bits (Domain 1 Core prescaler) */

+#define RCC_D1CFGR_D1CPRE_0                    (0x1UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000100 */

+#define RCC_D1CFGR_D1CPRE_1                    (0x2UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000200 */

+#define RCC_D1CFGR_D1CPRE_2                    (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */

+#define RCC_D1CFGR_D1CPRE_3                    (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */

+

+#define RCC_D1CFGR_D1CPRE_DIV1                 ((uint32_t)0x00000000)          /*!< Domain 1 Core clock not divided */

+#define RCC_D1CFGR_D1CPRE_DIV2_Pos             (11U)

+#define RCC_D1CFGR_D1CPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */

+#define RCC_D1CFGR_D1CPRE_DIV2                 RCC_D1CFGR_D1CPRE_DIV2_Msk      /*!< Domain 1 Core clock divided by 2 */

+#define RCC_D1CFGR_D1CPRE_DIV4_Pos             (8U)

+#define RCC_D1CFGR_D1CPRE_DIV4_Msk             (0x9UL << RCC_D1CFGR_D1CPRE_DIV4_Pos) /*!< 0x00000900 */

+#define RCC_D1CFGR_D1CPRE_DIV4                 RCC_D1CFGR_D1CPRE_DIV4_Msk      /*!< Domain 1 Core clock divided by 4 */

+#define RCC_D1CFGR_D1CPRE_DIV8_Pos             (9U)

+#define RCC_D1CFGR_D1CPRE_DIV8_Msk             (0x5UL << RCC_D1CFGR_D1CPRE_DIV8_Pos) /*!< 0x00000A00 */

+#define RCC_D1CFGR_D1CPRE_DIV8                 RCC_D1CFGR_D1CPRE_DIV8_Msk      /*!< Domain 1 Core clock divided by 8 */

+#define RCC_D1CFGR_D1CPRE_DIV16_Pos            (8U)

+#define RCC_D1CFGR_D1CPRE_DIV16_Msk            (0xBUL << RCC_D1CFGR_D1CPRE_DIV16_Pos) /*!< 0x00000B00 */

+#define RCC_D1CFGR_D1CPRE_DIV16                RCC_D1CFGR_D1CPRE_DIV16_Msk     /*!< Domain 1 Core clock divided by 16 */

+#define RCC_D1CFGR_D1CPRE_DIV64_Pos            (10U)

+#define RCC_D1CFGR_D1CPRE_DIV64_Msk            (0x3UL << RCC_D1CFGR_D1CPRE_DIV64_Pos) /*!< 0x00000C00 */

+#define RCC_D1CFGR_D1CPRE_DIV64                RCC_D1CFGR_D1CPRE_DIV64_Msk     /*!< Domain 1 Core clock divided by 64 */

+#define RCC_D1CFGR_D1CPRE_DIV128_Pos           (8U)

+#define RCC_D1CFGR_D1CPRE_DIV128_Msk           (0xDUL << RCC_D1CFGR_D1CPRE_DIV128_Pos) /*!< 0x00000D00 */

+#define RCC_D1CFGR_D1CPRE_DIV128               RCC_D1CFGR_D1CPRE_DIV128_Msk    /*!< Domain 1 Core clock divided by 128 */

+#define RCC_D1CFGR_D1CPRE_DIV256_Pos           (9U)

+#define RCC_D1CFGR_D1CPRE_DIV256_Msk           (0x7UL << RCC_D1CFGR_D1CPRE_DIV256_Pos) /*!< 0x00000E00 */

+#define RCC_D1CFGR_D1CPRE_DIV256               RCC_D1CFGR_D1CPRE_DIV256_Msk    /*!< Domain 1 Core clock divided by 256 */

+#define RCC_D1CFGR_D1CPRE_DIV512_Pos           (8U)

+#define RCC_D1CFGR_D1CPRE_DIV512_Msk           (0xFUL << RCC_D1CFGR_D1CPRE_DIV512_Pos) /*!< 0x00000F00 */

+#define RCC_D1CFGR_D1CPRE_DIV512               RCC_D1CFGR_D1CPRE_DIV512_Msk    /*!< Domain 1 Core clock divided by 512 */

+

+/********************  Bit definition for RCC_D2CFGR register  ******************/

+/*!< D2PPRE1 configuration */

+#define RCC_D2CFGR_D2PPRE1_Pos                 (4U)

+#define RCC_D2CFGR_D2PPRE1_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000070 */

+#define RCC_D2CFGR_D2PPRE1                     RCC_D2CFGR_D2PPRE1_Msk          /*!< D1PPRE1[2:0] bits (APB1 prescaler) */

+#define RCC_D2CFGR_D2PPRE1_0                   (0x1UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000010 */

+#define RCC_D2CFGR_D2PPRE1_1                   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */

+#define RCC_D2CFGR_D2PPRE1_2                   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */

+

+#define RCC_D2CFGR_D2PPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */

+#define RCC_D2CFGR_D2PPRE1_DIV2_Pos            (6U)

+#define RCC_D2CFGR_D2PPRE1_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_D2CFGR_D2PPRE1_DIV2                RCC_D2CFGR_D2PPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */

+#define RCC_D2CFGR_D2PPRE1_DIV4_Pos            (4U)

+#define RCC_D2CFGR_D2PPRE1_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE1_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_D2CFGR_D2PPRE1_DIV4                RCC_D2CFGR_D2PPRE1_DIV4_Msk     /*!< APB1 clock divided by 4 */

+#define RCC_D2CFGR_D2PPRE1_DIV8_Pos            (5U)

+#define RCC_D2CFGR_D2PPRE1_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE1_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_D2CFGR_D2PPRE1_DIV8                RCC_D2CFGR_D2PPRE1_DIV8_Msk     /*!< APB1 clock divided by 8 */

+#define RCC_D2CFGR_D2PPRE1_DIV16_Pos           (4U)

+#define RCC_D2CFGR_D2PPRE1_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE1_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_D2CFGR_D2PPRE1_DIV16               RCC_D2CFGR_D2PPRE1_DIV16_Msk    /*!< APB1 clock divided by 16 */

+

+/*!< D2PPRE2 configuration */

+#define RCC_D2CFGR_D2PPRE2_Pos                 (8U)

+#define RCC_D2CFGR_D2PPRE2_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000700 */

+#define RCC_D2CFGR_D2PPRE2                     RCC_D2CFGR_D2PPRE2_Msk          /*!< D2PPRE2[2:0] bits (APB2 prescaler) */

+#define RCC_D2CFGR_D2PPRE2_0                   (0x1UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000100 */

+#define RCC_D2CFGR_D2PPRE2_1                   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */

+#define RCC_D2CFGR_D2PPRE2_2                   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */

+

+#define RCC_D2CFGR_D2PPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */

+#define RCC_D2CFGR_D2PPRE2_DIV2_Pos            (10U)

+#define RCC_D2CFGR_D2PPRE2_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */

+#define RCC_D2CFGR_D2PPRE2_DIV2                RCC_D2CFGR_D2PPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */

+#define RCC_D2CFGR_D2PPRE2_DIV4_Pos            (8U)

+#define RCC_D2CFGR_D2PPRE2_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE2_DIV4_Pos) /*!< 0x00000500 */

+#define RCC_D2CFGR_D2PPRE2_DIV4                RCC_D2CFGR_D2PPRE2_DIV4_Msk     /*!< APB2 clock divided by 4 */

+#define RCC_D2CFGR_D2PPRE2_DIV8_Pos            (9U)

+#define RCC_D2CFGR_D2PPRE2_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE2_DIV8_Pos) /*!< 0x00000600 */

+#define RCC_D2CFGR_D2PPRE2_DIV8                RCC_D2CFGR_D2PPRE2_DIV8_Msk     /*!< APB2 clock divided by 8 */

+#define RCC_D2CFGR_D2PPRE2_DIV16_Pos           (8U)

+#define RCC_D2CFGR_D2PPRE2_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE2_DIV16_Pos) /*!< 0x00000700 */

+#define RCC_D2CFGR_D2PPRE2_DIV16               RCC_D2CFGR_D2PPRE2_DIV16_Msk    /*!< APB2 clock divided by 16 */

+

+/********************  Bit definition for RCC_D3CFGR register  ******************/

+/*!< D3PPRE configuration */

+#define RCC_D3CFGR_D3PPRE_Pos                  (4U)

+#define RCC_D3CFGR_D3PPRE_Msk                  (0x7UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000070 */

+#define RCC_D3CFGR_D3PPRE                      RCC_D3CFGR_D3PPRE_Msk           /*!< D3PPRE1[2:0] bits (APB4 prescaler) */

+#define RCC_D3CFGR_D3PPRE_0                    (0x1UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000010 */

+#define RCC_D3CFGR_D3PPRE_1                    (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */

+#define RCC_D3CFGR_D3PPRE_2                    (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */

+

+#define RCC_D3CFGR_D3PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */

+#define RCC_D3CFGR_D3PPRE_DIV2_Pos             (6U)

+#define RCC_D3CFGR_D3PPRE_DIV2_Msk             (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_D3CFGR_D3PPRE_DIV2                 RCC_D3CFGR_D3PPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */

+#define RCC_D3CFGR_D3PPRE_DIV4_Pos             (4U)

+#define RCC_D3CFGR_D3PPRE_DIV4_Msk             (0x5UL << RCC_D3CFGR_D3PPRE_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_D3CFGR_D3PPRE_DIV4                 RCC_D3CFGR_D3PPRE_DIV4_Msk      /*!< APB4 clock divided by 4 */

+#define RCC_D3CFGR_D3PPRE_DIV8_Pos             (5U)

+#define RCC_D3CFGR_D3PPRE_DIV8_Msk             (0x3UL << RCC_D3CFGR_D3PPRE_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_D3CFGR_D3PPRE_DIV8                 RCC_D3CFGR_D3PPRE_DIV8_Msk      /*!< APB4 clock divided by 8 */

+#define RCC_D3CFGR_D3PPRE_DIV16_Pos            (4U)

+#define RCC_D3CFGR_D3PPRE_DIV16_Msk            (0x7UL << RCC_D3CFGR_D3PPRE_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_D3CFGR_D3PPRE_DIV16                RCC_D3CFGR_D3PPRE_DIV16_Msk     /*!< APB4 clock divided by 16 */

+

+/********************  Bit definition for RCC_PLLCKSELR register  *************/

+

+#define RCC_PLLCKSELR_PLLSRC_Pos               (0U)

+#define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */

+#define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk

+

+#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)

+#define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */

+#define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_HSE_Pos           (1U)

+#define RCC_PLLCKSELR_PLLSRC_HSE_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */

+#define RCC_PLLCKSELR_PLLSRC_HSE               RCC_PLLCKSELR_PLLSRC_HSE_Msk    /*!< HSE source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_NONE_Pos          (0U)

+#define RCC_PLLCKSELR_PLLSRC_NONE_Msk          (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */

+#define RCC_PLLCKSELR_PLLSRC_NONE              RCC_PLLCKSELR_PLLSRC_NONE_Msk   /*!< No source clock selected  */

+

+#define RCC_PLLCKSELR_DIVM1_Pos                (4U)

+#define RCC_PLLCKSELR_DIVM1_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */

+#define RCC_PLLCKSELR_DIVM1                    RCC_PLLCKSELR_DIVM1_Msk

+#define RCC_PLLCKSELR_DIVM1_0                  (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */

+#define RCC_PLLCKSELR_DIVM1_1                  (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */

+#define RCC_PLLCKSELR_DIVM1_2                  (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */

+#define RCC_PLLCKSELR_DIVM1_3                  (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */

+#define RCC_PLLCKSELR_DIVM1_4                  (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */

+#define RCC_PLLCKSELR_DIVM1_5                  (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */

+

+#define RCC_PLLCKSELR_DIVM2_Pos                (12U)

+#define RCC_PLLCKSELR_DIVM2_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */

+#define RCC_PLLCKSELR_DIVM2                    RCC_PLLCKSELR_DIVM2_Msk

+#define RCC_PLLCKSELR_DIVM2_0                  (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */

+#define RCC_PLLCKSELR_DIVM2_1                  (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */

+#define RCC_PLLCKSELR_DIVM2_2                  (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */

+#define RCC_PLLCKSELR_DIVM2_3                  (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */

+#define RCC_PLLCKSELR_DIVM2_4                  (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */

+#define RCC_PLLCKSELR_DIVM2_5                  (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */

+

+#define RCC_PLLCKSELR_DIVM3_Pos                (20U)

+#define RCC_PLLCKSELR_DIVM3_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */

+#define RCC_PLLCKSELR_DIVM3                    RCC_PLLCKSELR_DIVM3_Msk

+#define RCC_PLLCKSELR_DIVM3_0                  (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */

+#define RCC_PLLCKSELR_DIVM3_1                  (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */

+#define RCC_PLLCKSELR_DIVM3_2                  (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */

+#define RCC_PLLCKSELR_DIVM3_3                  (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */

+#define RCC_PLLCKSELR_DIVM3_4                  (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */

+#define RCC_PLLCKSELR_DIVM3_5                  (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */

+

+/********************  Bit definition for RCC_PLLCFGR register  ***************/

+

+#define RCC_PLLCFGR_PLL1FRACEN_Pos             (0U)

+#define RCC_PLLCFGR_PLL1FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */

+#define RCC_PLLCFGR_PLL1FRACEN                 RCC_PLLCFGR_PLL1FRACEN_Msk

+#define RCC_PLLCFGR_PLL1VCOSEL_Pos             (1U)

+#define RCC_PLLCFGR_PLL1VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */

+#define RCC_PLLCFGR_PLL1VCOSEL                 RCC_PLLCFGR_PLL1VCOSEL_Msk

+#define RCC_PLLCFGR_PLL1RGE_Pos                (2U)

+#define RCC_PLLCFGR_PLL1RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */

+#define RCC_PLLCFGR_PLL1RGE                    RCC_PLLCFGR_PLL1RGE_Msk

+#define RCC_PLLCFGR_PLL1RGE_0                  (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL1RGE_1                  (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */

+#define RCC_PLLCFGR_PLL1RGE_2                  (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */

+#define RCC_PLLCFGR_PLL1RGE_3                  (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */

+

+#define RCC_PLLCFGR_PLL2FRACEN_Pos             (4U)

+#define RCC_PLLCFGR_PLL2FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */

+#define RCC_PLLCFGR_PLL2FRACEN                 RCC_PLLCFGR_PLL2FRACEN_Msk

+#define RCC_PLLCFGR_PLL2VCOSEL_Pos             (5U)

+#define RCC_PLLCFGR_PLL2VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */

+#define RCC_PLLCFGR_PLL2VCOSEL                 RCC_PLLCFGR_PLL2VCOSEL_Msk

+#define RCC_PLLCFGR_PLL2RGE_Pos                (6U)

+#define RCC_PLLCFGR_PLL2RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */

+#define RCC_PLLCFGR_PLL2RGE                    RCC_PLLCFGR_PLL2RGE_Msk

+#define RCC_PLLCFGR_PLL2RGE_0                  (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL2RGE_1                  (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */

+#define RCC_PLLCFGR_PLL2RGE_2                  (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */

+#define RCC_PLLCFGR_PLL2RGE_3                  (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */

+

+#define RCC_PLLCFGR_PLL3FRACEN_Pos             (8U)

+#define RCC_PLLCFGR_PLL3FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */

+#define RCC_PLLCFGR_PLL3FRACEN                 RCC_PLLCFGR_PLL3FRACEN_Msk

+#define RCC_PLLCFGR_PLL3VCOSEL_Pos             (9U)

+#define RCC_PLLCFGR_PLL3VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */

+#define RCC_PLLCFGR_PLL3VCOSEL                 RCC_PLLCFGR_PLL3VCOSEL_Msk

+#define RCC_PLLCFGR_PLL3RGE_Pos                (10U)

+#define RCC_PLLCFGR_PLL3RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */

+#define RCC_PLLCFGR_PLL3RGE                    RCC_PLLCFGR_PLL3RGE_Msk

+#define RCC_PLLCFGR_PLL3RGE_0                  (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL3RGE_1                  (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */

+#define RCC_PLLCFGR_PLL3RGE_2                  (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */

+#define RCC_PLLCFGR_PLL3RGE_3                  (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */

+

+#define RCC_PLLCFGR_DIVP1EN_Pos                (16U)

+#define RCC_PLLCFGR_DIVP1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */

+#define RCC_PLLCFGR_DIVP1EN                    RCC_PLLCFGR_DIVP1EN_Msk

+#define RCC_PLLCFGR_DIVQ1EN_Pos                (17U)

+#define RCC_PLLCFGR_DIVQ1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */

+#define RCC_PLLCFGR_DIVQ1EN                    RCC_PLLCFGR_DIVQ1EN_Msk

+#define RCC_PLLCFGR_DIVR1EN_Pos                (18U)

+#define RCC_PLLCFGR_DIVR1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */

+#define RCC_PLLCFGR_DIVR1EN                    RCC_PLLCFGR_DIVR1EN_Msk

+

+#define RCC_PLLCFGR_DIVP2EN_Pos                (19U)

+#define RCC_PLLCFGR_DIVP2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */

+#define RCC_PLLCFGR_DIVP2EN                    RCC_PLLCFGR_DIVP2EN_Msk

+#define RCC_PLLCFGR_DIVQ2EN_Pos                (20U)

+#define RCC_PLLCFGR_DIVQ2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */

+#define RCC_PLLCFGR_DIVQ2EN                    RCC_PLLCFGR_DIVQ2EN_Msk

+#define RCC_PLLCFGR_DIVR2EN_Pos                (21U)

+#define RCC_PLLCFGR_DIVR2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */

+#define RCC_PLLCFGR_DIVR2EN                    RCC_PLLCFGR_DIVR2EN_Msk

+

+#define RCC_PLLCFGR_DIVP3EN_Pos                (22U)

+#define RCC_PLLCFGR_DIVP3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */

+#define RCC_PLLCFGR_DIVP3EN                    RCC_PLLCFGR_DIVP3EN_Msk

+#define RCC_PLLCFGR_DIVQ3EN_Pos                (23U)

+#define RCC_PLLCFGR_DIVQ3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */

+#define RCC_PLLCFGR_DIVQ3EN                    RCC_PLLCFGR_DIVQ3EN_Msk

+#define RCC_PLLCFGR_DIVR3EN_Pos                (24U)

+#define RCC_PLLCFGR_DIVR3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */

+#define RCC_PLLCFGR_DIVR3EN                    RCC_PLLCFGR_DIVR3EN_Msk

+

+

+/********************  Bit definition for RCC_PLL1DIVR register  ***************/

+#define RCC_PLL1DIVR_N1_Pos                    (0U)

+#define RCC_PLL1DIVR_N1_Msk                    (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */

+#define RCC_PLL1DIVR_N1                        RCC_PLL1DIVR_N1_Msk

+#define RCC_PLL1DIVR_P1_Pos                    (9U)

+#define RCC_PLL1DIVR_P1_Msk                    (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL1DIVR_P1                        RCC_PLL1DIVR_P1_Msk

+#define RCC_PLL1DIVR_Q1_Pos                    (16U)

+#define RCC_PLL1DIVR_Q1_Msk                    (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */

+#define RCC_PLL1DIVR_Q1                        RCC_PLL1DIVR_Q1_Msk

+#define RCC_PLL1DIVR_R1_Pos                    (24U)

+#define RCC_PLL1DIVR_R1_Msk                    (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */

+#define RCC_PLL1DIVR_R1                        RCC_PLL1DIVR_R1_Msk

+

+/********************  Bit definition for RCC_PLL1FRACR register  ***************/

+#define RCC_PLL1FRACR_FRACN1_Pos               (3U)

+#define RCC_PLL1FRACR_FRACN1_Msk               (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL1FRACR_FRACN1                   RCC_PLL1FRACR_FRACN1_Msk

+

+/********************  Bit definition for RCC_PLL2DIVR register  ***************/

+#define RCC_PLL2DIVR_N2_Pos                    (0U)

+#define RCC_PLL2DIVR_N2_Msk                    (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */

+#define RCC_PLL2DIVR_N2                        RCC_PLL2DIVR_N2_Msk

+#define RCC_PLL2DIVR_P2_Pos                    (9U)

+#define RCC_PLL2DIVR_P2_Msk                    (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL2DIVR_P2                        RCC_PLL2DIVR_P2_Msk

+#define RCC_PLL2DIVR_Q2_Pos                    (16U)

+#define RCC_PLL2DIVR_Q2_Msk                    (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */

+#define RCC_PLL2DIVR_Q2                        RCC_PLL2DIVR_Q2_Msk

+#define RCC_PLL2DIVR_R2_Pos                    (24U)

+#define RCC_PLL2DIVR_R2_Msk                    (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */

+#define RCC_PLL2DIVR_R2                        RCC_PLL2DIVR_R2_Msk

+

+/********************  Bit definition for RCC_PLL2FRACR register  ***************/

+#define RCC_PLL2FRACR_FRACN2_Pos               (3U)

+#define RCC_PLL2FRACR_FRACN2_Msk               (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL2FRACR_FRACN2                   RCC_PLL2FRACR_FRACN2_Msk

+

+/********************  Bit definition for RCC_PLL3DIVR register  ***************/

+#define RCC_PLL3DIVR_N3_Pos                    (0U)

+#define RCC_PLL3DIVR_N3_Msk                    (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */

+#define RCC_PLL3DIVR_N3                        RCC_PLL3DIVR_N3_Msk

+#define RCC_PLL3DIVR_P3_Pos                    (9U)

+#define RCC_PLL3DIVR_P3_Msk                    (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL3DIVR_P3                        RCC_PLL3DIVR_P3_Msk

+#define RCC_PLL3DIVR_Q3_Pos                    (16U)

+#define RCC_PLL3DIVR_Q3_Msk                    (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */

+#define RCC_PLL3DIVR_Q3                        RCC_PLL3DIVR_Q3_Msk

+#define RCC_PLL3DIVR_R3_Pos                    (24U)

+#define RCC_PLL3DIVR_R3_Msk                    (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */

+#define RCC_PLL3DIVR_R3                        RCC_PLL3DIVR_R3_Msk

+

+/********************  Bit definition for RCC_PLL3FRACR register  ***************/

+#define RCC_PLL3FRACR_FRACN3_Pos               (3U)

+#define RCC_PLL3FRACR_FRACN3_Msk               (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL3FRACR_FRACN3                   RCC_PLL3FRACR_FRACN3_Msk

+

+/********************  Bit definition for RCC_D1CCIPR register  ***************/

+#define RCC_D1CCIPR_FMCSEL_Pos                 (0U)

+#define RCC_D1CCIPR_FMCSEL_Msk                 (0x3UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000003 */

+#define RCC_D1CCIPR_FMCSEL                     RCC_D1CCIPR_FMCSEL_Msk

+#define RCC_D1CCIPR_FMCSEL_0                   (0x1UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000001 */

+#define RCC_D1CCIPR_FMCSEL_1                   (0x2UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000002 */

+#define RCC_D1CCIPR_QSPISEL_Pos                (4U)

+#define RCC_D1CCIPR_QSPISEL_Msk                (0x3UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000030 */

+#define RCC_D1CCIPR_QSPISEL                    RCC_D1CCIPR_QSPISEL_Msk

+#define RCC_D1CCIPR_QSPISEL_0                  (0x1UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000010 */

+#define RCC_D1CCIPR_QSPISEL_1                  (0x2UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000020 */

+#define RCC_D1CCIPR_SDMMCSEL_Pos               (16U)

+#define RCC_D1CCIPR_SDMMCSEL_Msk               (0x1UL << RCC_D1CCIPR_SDMMCSEL_Pos) /*!< 0x00010000 */

+#define RCC_D1CCIPR_SDMMCSEL                   RCC_D1CCIPR_SDMMCSEL_Msk

+#define RCC_D1CCIPR_CKPERSEL_Pos               (28U)

+#define RCC_D1CCIPR_CKPERSEL_Msk               (0x3UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x30000000 */

+#define RCC_D1CCIPR_CKPERSEL                   RCC_D1CCIPR_CKPERSEL_Msk

+#define RCC_D1CCIPR_CKPERSEL_0                 (0x1UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x10000000 */

+#define RCC_D1CCIPR_CKPERSEL_1                 (0x2UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x20000000 */

+

+/********************  Bit definition for RCC_D2CCIP1R register  ***************/

+#define RCC_D2CCIP1R_SAI1SEL_Pos               (0U)

+#define RCC_D2CCIP1R_SAI1SEL_Msk               (0x7UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000007 */

+#define RCC_D2CCIP1R_SAI1SEL                   RCC_D2CCIP1R_SAI1SEL_Msk

+#define RCC_D2CCIP1R_SAI1SEL_0                 (0x1UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000001 */

+#define RCC_D2CCIP1R_SAI1SEL_1                 (0x2UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000002 */

+#define RCC_D2CCIP1R_SAI1SEL_2                 (0x4UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000004 */

+

+#define RCC_D2CCIP1R_SAI23SEL_Pos              (6U)

+#define RCC_D2CCIP1R_SAI23SEL_Msk              (0x7UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x000001C0 */

+#define RCC_D2CCIP1R_SAI23SEL                  RCC_D2CCIP1R_SAI23SEL_Msk

+#define RCC_D2CCIP1R_SAI23SEL_0                (0x1UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000040 */

+#define RCC_D2CCIP1R_SAI23SEL_1                (0x2UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000080 */

+#define RCC_D2CCIP1R_SAI23SEL_2                (0x4UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000100 */

+

+#define RCC_D2CCIP1R_SPI123SEL_Pos             (12U)

+#define RCC_D2CCIP1R_SPI123SEL_Msk             (0x7UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */

+#define RCC_D2CCIP1R_SPI123SEL                 RCC_D2CCIP1R_SPI123SEL_Msk

+#define RCC_D2CCIP1R_SPI123SEL_0               (0x1UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */

+#define RCC_D2CCIP1R_SPI123SEL_1               (0x2UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */

+#define RCC_D2CCIP1R_SPI123SEL_2               (0x4UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */

+

+#define RCC_D2CCIP1R_SPI45SEL_Pos              (16U)

+#define RCC_D2CCIP1R_SPI45SEL_Msk              (0x7UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00070000 */

+#define RCC_D2CCIP1R_SPI45SEL                  RCC_D2CCIP1R_SPI45SEL_Msk

+#define RCC_D2CCIP1R_SPI45SEL_0                (0x1UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00010000 */

+#define RCC_D2CCIP1R_SPI45SEL_1                (0x2UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00020000 */

+#define RCC_D2CCIP1R_SPI45SEL_2                (0x4UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00040000 */

+

+#define RCC_D2CCIP1R_SPDIFSEL_Pos              (20U)

+#define RCC_D2CCIP1R_SPDIFSEL_Msk              (0x3UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00300000 */

+#define RCC_D2CCIP1R_SPDIFSEL                  RCC_D2CCIP1R_SPDIFSEL_Msk

+#define RCC_D2CCIP1R_SPDIFSEL_0                (0x1UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00100000 */

+#define RCC_D2CCIP1R_SPDIFSEL_1                (0x2UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00200000 */

+

+#define RCC_D2CCIP1R_DFSDM1SEL_Pos             (24U)

+#define RCC_D2CCIP1R_DFSDM1SEL_Msk             (0x1UL << RCC_D2CCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */

+#define RCC_D2CCIP1R_DFSDM1SEL                 RCC_D2CCIP1R_DFSDM1SEL_Msk

+

+#define RCC_D2CCIP1R_FDCANSEL_Pos              (28U)

+#define RCC_D2CCIP1R_FDCANSEL_Msk              (0x3UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x30000000 */

+#define RCC_D2CCIP1R_FDCANSEL                  RCC_D2CCIP1R_FDCANSEL_Msk

+#define RCC_D2CCIP1R_FDCANSEL_0                (0x1UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x10000000 */

+#define RCC_D2CCIP1R_FDCANSEL_1                (0x2UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x20000000 */

+

+#define RCC_D2CCIP1R_SWPSEL_Pos                (31U)

+#define RCC_D2CCIP1R_SWPSEL_Msk                (0x1UL << RCC_D2CCIP1R_SWPSEL_Pos) /*!< 0x80000000 */

+#define RCC_D2CCIP1R_SWPSEL                    RCC_D2CCIP1R_SWPSEL_Msk

+

+/********************  Bit definition for RCC_D2CCIP2R register  ***************/

+#define RCC_D2CCIP2R_USART16SEL_Pos            (3U)

+#define RCC_D2CCIP2R_USART16SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000038 */

+#define RCC_D2CCIP2R_USART16SEL                RCC_D2CCIP2R_USART16SEL_Msk

+#define RCC_D2CCIP2R_USART16SEL_0              (0x1UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000008 */

+#define RCC_D2CCIP2R_USART16SEL_1              (0x2UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000010 */

+#define RCC_D2CCIP2R_USART16SEL_2              (0x4UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000020 */

+

+#define RCC_D2CCIP2R_USART28SEL_Pos            (0U)

+#define RCC_D2CCIP2R_USART28SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000007 */

+#define RCC_D2CCIP2R_USART28SEL                RCC_D2CCIP2R_USART28SEL_Msk

+#define RCC_D2CCIP2R_USART28SEL_0              (0x1UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000001 */

+#define RCC_D2CCIP2R_USART28SEL_1              (0x2UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000002 */

+#define RCC_D2CCIP2R_USART28SEL_2              (0x4UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000004 */

+

+#define RCC_D2CCIP2R_RNGSEL_Pos                (8U)

+#define RCC_D2CCIP2R_RNGSEL_Msk                (0x3UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000300 */

+#define RCC_D2CCIP2R_RNGSEL                    RCC_D2CCIP2R_RNGSEL_Msk

+#define RCC_D2CCIP2R_RNGSEL_0                  (0x1UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000100 */

+#define RCC_D2CCIP2R_RNGSEL_1                  (0x2UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000200 */

+

+#define RCC_D2CCIP2R_I2C123SEL_Pos             (12U)

+#define RCC_D2CCIP2R_I2C123SEL_Msk             (0x3UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00003000 */

+#define RCC_D2CCIP2R_I2C123SEL                 RCC_D2CCIP2R_I2C123SEL_Msk

+#define RCC_D2CCIP2R_I2C123SEL_0               (0x1UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00001000 */

+#define RCC_D2CCIP2R_I2C123SEL_1               (0x2UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00002000 */

+

+#define RCC_D2CCIP2R_USBSEL_Pos                (20U)

+#define RCC_D2CCIP2R_USBSEL_Msk                (0x3UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00300000 */

+#define RCC_D2CCIP2R_USBSEL                    RCC_D2CCIP2R_USBSEL_Msk

+#define RCC_D2CCIP2R_USBSEL_0                  (0x1UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00100000 */

+#define RCC_D2CCIP2R_USBSEL_1                  (0x2UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00200000 */

+

+#define RCC_D2CCIP2R_CECSEL_Pos                (22U)

+#define RCC_D2CCIP2R_CECSEL_Msk                (0x3UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00C00000 */

+#define RCC_D2CCIP2R_CECSEL                    RCC_D2CCIP2R_CECSEL_Msk

+#define RCC_D2CCIP2R_CECSEL_0                  (0x1UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00400000 */

+#define RCC_D2CCIP2R_CECSEL_1                  (0x2UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00800000 */

+

+#define RCC_D2CCIP2R_LPTIM1SEL_Pos             (28U)

+#define RCC_D2CCIP2R_LPTIM1SEL_Msk             (0x7UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x70000000 */

+#define RCC_D2CCIP2R_LPTIM1SEL                 RCC_D2CCIP2R_LPTIM1SEL_Msk

+#define RCC_D2CCIP2R_LPTIM1SEL_0               (0x1UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x10000000 */

+#define RCC_D2CCIP2R_LPTIM1SEL_1               (0x2UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x20000000 */

+#define RCC_D2CCIP2R_LPTIM1SEL_2               (0x4UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition for RCC_D3CCIPR register  ***************/

+#define RCC_D3CCIPR_LPUART1SEL_Pos             (0U)

+#define RCC_D3CCIPR_LPUART1SEL_Msk             (0x7UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000007 */

+#define RCC_D3CCIPR_LPUART1SEL                 RCC_D3CCIPR_LPUART1SEL_Msk

+#define RCC_D3CCIPR_LPUART1SEL_0               (0x1UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000001 */

+#define RCC_D3CCIPR_LPUART1SEL_1               (0x2UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000002 */

+#define RCC_D3CCIPR_LPUART1SEL_2               (0x4UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000004 */

+

+#define RCC_D3CCIPR_I2C4SEL_Pos                (8U)

+#define RCC_D3CCIPR_I2C4SEL_Msk                (0x3UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000300 */

+#define RCC_D3CCIPR_I2C4SEL                    RCC_D3CCIPR_I2C4SEL_Msk

+#define RCC_D3CCIPR_I2C4SEL_0                  (0x1UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000100 */

+#define RCC_D3CCIPR_I2C4SEL_1                  (0x2UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000200 */

+

+#define RCC_D3CCIPR_LPTIM2SEL_Pos              (10U)

+#define RCC_D3CCIPR_LPTIM2SEL_Msk              (0x7UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001C00 */

+#define RCC_D3CCIPR_LPTIM2SEL                  RCC_D3CCIPR_LPTIM2SEL_Msk

+#define RCC_D3CCIPR_LPTIM2SEL_0                (0x1UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000400 */

+#define RCC_D3CCIPR_LPTIM2SEL_1                (0x2UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000800 */

+#define RCC_D3CCIPR_LPTIM2SEL_2                (0x4UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001000 */

+

+#define RCC_D3CCIPR_LPTIM345SEL_Pos            (13U)

+#define RCC_D3CCIPR_LPTIM345SEL_Msk            (0x7UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x0000E000 */

+#define RCC_D3CCIPR_LPTIM345SEL                RCC_D3CCIPR_LPTIM345SEL_Msk

+#define RCC_D3CCIPR_LPTIM345SEL_0              (0x1UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00002000 */

+#define RCC_D3CCIPR_LPTIM345SEL_1              (0x2UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00004000 */

+#define RCC_D3CCIPR_LPTIM345SEL_2              (0x4UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00008000 */

+

+#define RCC_D3CCIPR_SAI4ASEL_Pos               (21U)

+#define RCC_D3CCIPR_SAI4ASEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00E00000 */

+#define RCC_D3CCIPR_SAI4ASEL                   RCC_D3CCIPR_SAI4ASEL_Msk

+#define RCC_D3CCIPR_SAI4ASEL_0                 (0x1UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00200000 */

+#define RCC_D3CCIPR_SAI4ASEL_1                 (0x2UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00400000 */

+#define RCC_D3CCIPR_SAI4ASEL_2                 (0x4UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00800000 */

+

+#define RCC_D3CCIPR_SAI4BSEL_Pos               (24U)

+#define RCC_D3CCIPR_SAI4BSEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x07000000 */

+#define RCC_D3CCIPR_SAI4BSEL                   RCC_D3CCIPR_SAI4BSEL_Msk

+#define RCC_D3CCIPR_SAI4BSEL_0                 (0x1UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x01000000 */

+#define RCC_D3CCIPR_SAI4BSEL_1                 (0x2UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x02000000 */

+#define RCC_D3CCIPR_SAI4BSEL_2                 (0x4UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x04000000 */

+

+#define RCC_D3CCIPR_ADCSEL_Pos                 (16U)

+#define RCC_D3CCIPR_ADCSEL_Msk                 (0x3UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00030000 */

+#define RCC_D3CCIPR_ADCSEL                     RCC_D3CCIPR_ADCSEL_Msk

+#define RCC_D3CCIPR_ADCSEL_0                   (0x1UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00010000 */

+#define RCC_D3CCIPR_ADCSEL_1                   (0x2UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00020000 */

+

+#define RCC_D3CCIPR_SPI6SEL_Pos                (28U)

+#define RCC_D3CCIPR_SPI6SEL_Msk                (0x7UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x70000000 */

+#define RCC_D3CCIPR_SPI6SEL                    RCC_D3CCIPR_SPI6SEL_Msk

+#define RCC_D3CCIPR_SPI6SEL_0                  (0x1UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x10000000 */

+#define RCC_D3CCIPR_SPI6SEL_1                  (0x2UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x20000000 */

+#define RCC_D3CCIPR_SPI6SEL_2                  (0x4UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x40000000 */

+/********************  Bit definition for RCC_CIER register  ******************/

+#define RCC_CIER_LSIRDYIE_Pos                  (0U)

+#define RCC_CIER_LSIRDYIE_Msk                  (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */

+#define RCC_CIER_LSIRDYIE                      RCC_CIER_LSIRDYIE_Msk

+#define RCC_CIER_LSERDYIE_Pos                  (1U)

+#define RCC_CIER_LSERDYIE_Msk                  (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */

+#define RCC_CIER_LSERDYIE                      RCC_CIER_LSERDYIE_Msk

+#define RCC_CIER_HSIRDYIE_Pos                  (2U)

+#define RCC_CIER_HSIRDYIE_Msk                  (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */

+#define RCC_CIER_HSIRDYIE                      RCC_CIER_HSIRDYIE_Msk

+#define RCC_CIER_HSERDYIE_Pos                  (3U)

+#define RCC_CIER_HSERDYIE_Msk                  (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */

+#define RCC_CIER_HSERDYIE                      RCC_CIER_HSERDYIE_Msk

+#define RCC_CIER_CSIRDYIE_Pos                  (4U)

+#define RCC_CIER_CSIRDYIE_Msk                  (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */

+#define RCC_CIER_CSIRDYIE                      RCC_CIER_CSIRDYIE_Msk

+#define RCC_CIER_HSI48RDYIE_Pos                (5U)

+#define RCC_CIER_HSI48RDYIE_Msk                (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */

+#define RCC_CIER_HSI48RDYIE                    RCC_CIER_HSI48RDYIE_Msk

+#define RCC_CIER_PLL1RDYIE_Pos                 (6U)

+#define RCC_CIER_PLL1RDYIE_Msk                 (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */

+#define RCC_CIER_PLL1RDYIE                     RCC_CIER_PLL1RDYIE_Msk

+#define RCC_CIER_PLL2RDYIE_Pos                 (7U)

+#define RCC_CIER_PLL2RDYIE_Msk                 (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */

+#define RCC_CIER_PLL2RDYIE                     RCC_CIER_PLL2RDYIE_Msk

+#define RCC_CIER_PLL3RDYIE_Pos                 (8U)

+#define RCC_CIER_PLL3RDYIE_Msk                 (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */

+#define RCC_CIER_PLL3RDYIE                     RCC_CIER_PLL3RDYIE_Msk

+#define RCC_CIER_LSECSSIE_Pos                  (9U)

+#define RCC_CIER_LSECSSIE_Msk                  (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */

+#define RCC_CIER_LSECSSIE                      RCC_CIER_LSECSSIE_Msk

+

+/********************  Bit definition for RCC_CIFR register  ******************/

+#define RCC_CIFR_LSIRDYF_Pos                   (0U)

+#define RCC_CIFR_LSIRDYF_Msk                   (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */

+#define RCC_CIFR_LSIRDYF                       RCC_CIFR_LSIRDYF_Msk

+#define RCC_CIFR_LSERDYF_Pos                   (1U)

+#define RCC_CIFR_LSERDYF_Msk                   (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */

+#define RCC_CIFR_LSERDYF                       RCC_CIFR_LSERDYF_Msk

+#define RCC_CIFR_HSIRDYF_Pos                   (2U)

+#define RCC_CIFR_HSIRDYF_Msk                   (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */

+#define RCC_CIFR_HSIRDYF                       RCC_CIFR_HSIRDYF_Msk

+#define RCC_CIFR_HSERDYF_Pos                   (3U)

+#define RCC_CIFR_HSERDYF_Msk                   (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */

+#define RCC_CIFR_HSERDYF                       RCC_CIFR_HSERDYF_Msk

+#define RCC_CIFR_CSIRDYF_Pos                   (4U)

+#define RCC_CIFR_CSIRDYF_Msk                   (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */

+#define RCC_CIFR_CSIRDYF                       RCC_CIFR_CSIRDYF_Msk

+#define RCC_CIFR_HSI48RDYF_Pos                 (5U)

+#define RCC_CIFR_HSI48RDYF_Msk                 (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */

+#define RCC_CIFR_HSI48RDYF                     RCC_CIFR_HSI48RDYF_Msk

+#define RCC_CIFR_PLLRDYF_Pos                   (6U)

+#define RCC_CIFR_PLLRDYF_Msk                   (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */

+#define RCC_CIFR_PLLRDYF                       RCC_CIFR_PLLRDYF_Msk

+#define RCC_CIFR_PLL2RDYF_Pos                  (7U)

+#define RCC_CIFR_PLL2RDYF_Msk                  (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */

+#define RCC_CIFR_PLL2RDYF                      RCC_CIFR_PLL2RDYF_Msk

+#define RCC_CIFR_PLL3RDYF_Pos                  (8U)

+#define RCC_CIFR_PLL3RDYF_Msk                  (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */

+#define RCC_CIFR_PLL3RDYF                      RCC_CIFR_PLL3RDYF_Msk

+#define RCC_CIFR_LSECSSF_Pos                   (9U)

+#define RCC_CIFR_LSECSSF_Msk                   (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */

+#define RCC_CIFR_LSECSSF                       RCC_CIFR_LSECSSF_Msk

+#define RCC_CIFR_HSECSSF_Pos                   (10U)

+#define RCC_CIFR_HSECSSF_Msk                   (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */

+#define RCC_CIFR_HSECSSF                       RCC_CIFR_HSECSSF_Msk

+

+/********************  Bit definition for RCC_CICR register  ******************/

+#define RCC_CICR_LSIRDYC_Pos                   (0U)

+#define RCC_CICR_LSIRDYC_Msk                   (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */

+#define RCC_CICR_LSIRDYC                       RCC_CICR_LSIRDYC_Msk

+#define RCC_CICR_LSERDYC_Pos                   (1U)

+#define RCC_CICR_LSERDYC_Msk                   (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */

+#define RCC_CICR_LSERDYC                       RCC_CICR_LSERDYC_Msk

+#define RCC_CICR_HSIRDYC_Pos                   (2U)

+#define RCC_CICR_HSIRDYC_Msk                   (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */

+#define RCC_CICR_HSIRDYC                       RCC_CICR_HSIRDYC_Msk

+#define RCC_CICR_HSERDYC_Pos                   (3U)

+#define RCC_CICR_HSERDYC_Msk                   (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */

+#define RCC_CICR_HSERDYC                       RCC_CICR_HSERDYC_Msk

+#define RCC_CICR_CSIRDYC_Pos                   (4U)

+#define RCC_CICR_CSIRDYC_Msk                   (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */

+#define RCC_CICR_CSIRDYC                       RCC_CICR_CSIRDYC_Msk

+#define RCC_CICR_HSI48RDYC_Pos                 (5U)

+#define RCC_CICR_HSI48RDYC_Msk                 (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */

+#define RCC_CICR_HSI48RDYC                     RCC_CICR_HSI48RDYC_Msk

+#define RCC_CICR_PLLRDYC_Pos                   (6U)

+#define RCC_CICR_PLLRDYC_Msk                   (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */

+#define RCC_CICR_PLLRDYC                       RCC_CICR_PLLRDYC_Msk

+#define RCC_CICR_PLL2RDYC_Pos                  (7U)

+#define RCC_CICR_PLL2RDYC_Msk                  (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */

+#define RCC_CICR_PLL2RDYC                      RCC_CICR_PLL2RDYC_Msk

+#define RCC_CICR_PLL3RDYC_Pos                  (8U)

+#define RCC_CICR_PLL3RDYC_Msk                  (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */

+#define RCC_CICR_PLL3RDYC                      RCC_CICR_PLL3RDYC_Msk

+#define RCC_CICR_LSECSSC_Pos                   (9U)

+#define RCC_CICR_LSECSSC_Msk                   (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */

+#define RCC_CICR_LSECSSC                       RCC_CICR_LSECSSC_Msk

+#define RCC_CICR_HSECSSC_Pos                   (10U)

+#define RCC_CICR_HSECSSC_Msk                   (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */

+#define RCC_CICR_HSECSSC                       RCC_CICR_HSECSSC_Msk

+

+/********************  Bit definition for RCC_BDCR register  ******************/

+#define RCC_BDCR_LSEON_Pos                     (0U)

+#define RCC_BDCR_LSEON_Msk                     (0x1UL << RCC_BDCR_LSEON_Pos)   /*!< 0x00000001 */

+#define RCC_BDCR_LSEON                         RCC_BDCR_LSEON_Msk

+#define RCC_BDCR_LSERDY_Pos                    (1U)

+#define RCC_BDCR_LSERDY_Msk                    (0x1UL << RCC_BDCR_LSERDY_Pos)  /*!< 0x00000002 */

+#define RCC_BDCR_LSERDY                        RCC_BDCR_LSERDY_Msk

+#define RCC_BDCR_LSEBYP_Pos                    (2U)

+#define RCC_BDCR_LSEBYP_Msk                    (0x1UL << RCC_BDCR_LSEBYP_Pos)  /*!< 0x00000004 */

+#define RCC_BDCR_LSEBYP                        RCC_BDCR_LSEBYP_Msk

+

+#define RCC_BDCR_LSEDRV_Pos                    (3U)

+#define RCC_BDCR_LSEDRV_Msk                    (0x3UL << RCC_BDCR_LSEDRV_Pos)  /*!< 0x00000018 */

+#define RCC_BDCR_LSEDRV                        RCC_BDCR_LSEDRV_Msk

+#define RCC_BDCR_LSEDRV_0                      (0x1UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000008 */

+#define RCC_BDCR_LSEDRV_1                      (0x2UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000010 */

+

+#define RCC_BDCR_LSECSSON_Pos                  (5U)

+#define RCC_BDCR_LSECSSON_Msk                  (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */

+#define RCC_BDCR_LSECSSON                      RCC_BDCR_LSECSSON_Msk

+#define RCC_BDCR_LSECSSD_Pos                   (6U)

+#define RCC_BDCR_LSECSSD_Msk                   (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */

+#define RCC_BDCR_LSECSSD                       RCC_BDCR_LSECSSD_Msk

+

+#define RCC_BDCR_RTCSEL_Pos                    (8U)

+#define RCC_BDCR_RTCSEL_Msk                    (0x3UL << RCC_BDCR_RTCSEL_Pos)  /*!< 0x00000300 */

+#define RCC_BDCR_RTCSEL                        RCC_BDCR_RTCSEL_Msk

+#define RCC_BDCR_RTCSEL_0                      (0x1UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000100 */

+#define RCC_BDCR_RTCSEL_1                      (0x2UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000200 */

+

+#define RCC_BDCR_RTCEN_Pos                     (15U)

+#define RCC_BDCR_RTCEN_Msk                     (0x1UL << RCC_BDCR_RTCEN_Pos)   /*!< 0x00008000 */

+#define RCC_BDCR_RTCEN                         RCC_BDCR_RTCEN_Msk

+#define RCC_BDCR_BDRST_Pos                     (16U)

+#define RCC_BDCR_BDRST_Msk                     (0x1UL << RCC_BDCR_BDRST_Pos)   /*!< 0x00010000 */

+#define RCC_BDCR_BDRST                         RCC_BDCR_BDRST_Msk

+/********************  Bit definition for RCC_CSR register  *******************/

+#define RCC_CSR_LSION_Pos                      (0U)

+#define RCC_CSR_LSION_Msk                      (0x1UL << RCC_CSR_LSION_Pos)    /*!< 0x00000001 */

+#define RCC_CSR_LSION                          RCC_CSR_LSION_Msk

+#define RCC_CSR_LSIRDY_Pos                     (1U)

+#define RCC_CSR_LSIRDY_Msk                     (0x1UL << RCC_CSR_LSIRDY_Pos)   /*!< 0x00000002 */

+#define RCC_CSR_LSIRDY                         RCC_CSR_LSIRDY_Msk

+

+

+/********************  Bit definition for RCC_AHB3ENR register  **************/

+#define RCC_AHB3ENR_MDMAEN_Pos                 (0U)

+#define RCC_AHB3ENR_MDMAEN_Msk                 (0x1UL << RCC_AHB3ENR_MDMAEN_Pos)       /*!< 0x00000001 */

+#define RCC_AHB3ENR_MDMAEN                     RCC_AHB3ENR_MDMAEN_Msk

+#define RCC_AHB3ENR_DMA2DEN_Pos                (4U)

+#define RCC_AHB3ENR_DMA2DEN_Msk                (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos)      /*!< 0x00000010 */

+#define RCC_AHB3ENR_DMA2DEN                    RCC_AHB3ENR_DMA2DEN_Msk

+#define RCC_AHB3ENR_FMCEN_Pos                  (12U)

+#define RCC_AHB3ENR_FMCEN_Msk                  (0x1UL << RCC_AHB3ENR_FMCEN_Pos)        /*!< 0x00001000 */

+#define RCC_AHB3ENR_FMCEN                      RCC_AHB3ENR_FMCEN_Msk

+#define RCC_AHB3ENR_QSPIEN_Pos                 (14U)

+#define RCC_AHB3ENR_QSPIEN_Msk                 (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)       /*!< 0x00004000 */

+#define RCC_AHB3ENR_QSPIEN                     RCC_AHB3ENR_QSPIEN_Msk

+#define RCC_AHB3ENR_SDMMC1EN_Pos               (16U)

+#define RCC_AHB3ENR_SDMMC1EN_Msk               (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos)     /*!< 0x00010000 */

+#define RCC_AHB3ENR_SDMMC1EN                   RCC_AHB3ENR_SDMMC1EN_Msk

+

+/********************  Bit definition for RCC_AHB1ENR register  ***************/

+#define RCC_AHB1ENR_DMA1EN_Pos                 (0U)

+#define RCC_AHB1ENR_DMA1EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)          /*!< 0x00000001 */

+#define RCC_AHB1ENR_DMA1EN                     RCC_AHB1ENR_DMA1EN_Msk

+#define RCC_AHB1ENR_DMA2EN_Pos                 (1U)

+#define RCC_AHB1ENR_DMA2EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)          /*!< 0x00000002 */

+#define RCC_AHB1ENR_DMA2EN                     RCC_AHB1ENR_DMA2EN_Msk

+#define RCC_AHB1ENR_ADC12EN_Pos                (5U)

+#define RCC_AHB1ENR_ADC12EN_Msk                (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)         /*!< 0x00000020 */

+#define RCC_AHB1ENR_ADC12EN                    RCC_AHB1ENR_ADC12EN_Msk

+#define RCC_AHB1ENR_ETH1MACEN_Pos              (15U)

+#define RCC_AHB1ENR_ETH1MACEN_Msk              (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos)       /*!< 0x00008000 */

+#define RCC_AHB1ENR_ETH1MACEN                  RCC_AHB1ENR_ETH1MACEN_Msk

+#define RCC_AHB1ENR_ETH1TXEN_Pos               (16U)

+#define RCC_AHB1ENR_ETH1TXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos)        /*!< 0x00010000 */

+#define RCC_AHB1ENR_ETH1TXEN                   RCC_AHB1ENR_ETH1TXEN_Msk

+#define RCC_AHB1ENR_ETH1RXEN_Pos               (17U)

+#define RCC_AHB1ENR_ETH1RXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos)        /*!< 0x00020000 */

+#define RCC_AHB1ENR_ETH1RXEN                   RCC_AHB1ENR_ETH1RXEN_Msk

+#define RCC_AHB1ENR_USB1OTGHSEN_Pos            (25U)

+#define RCC_AHB1ENR_USB1OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos)     /*!< 0x02000000 */

+#define RCC_AHB1ENR_USB1OTGHSEN                RCC_AHB1ENR_USB1OTGHSEN_Msk

+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos        (26U)

+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */

+#define RCC_AHB1ENR_USB1OTGHSULPIEN            RCC_AHB1ENR_USB1OTGHSULPIEN_Msk

+#define RCC_AHB1ENR_USB2OTGFSEN_Pos            (27U)

+#define RCC_AHB1ENR_USB2OTGFSEN_Msk            (0x1UL << RCC_AHB1ENR_USB2OTGFSEN_Pos)     /*!< 0x08000000 */

+#define RCC_AHB1ENR_USB2OTGFSEN                RCC_AHB1ENR_USB2OTGFSEN_Msk

+#define RCC_AHB1ENR_USB2OTGFSULPIEN_Pos        (28U)

+#define RCC_AHB1ENR_USB2OTGFSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB2OTGFSULPIEN_Pos) /*!< 0x10000000 */

+#define RCC_AHB1ENR_USB2OTGFSULPIEN            RCC_AHB1ENR_USB2OTGFSULPIEN_Msk

+

+/* Legacy define */

+#define RCC_AHB1ENR_USB2OTGHSEN_Pos            RCC_AHB1ENR_USB2OTGFSEN_Pos

+#define RCC_AHB1ENR_USB2OTGHSEN_Msk            RCC_AHB1ENR_USB2OTGFSEN_Msk

+#define RCC_AHB1ENR_USB2OTGHSEN                RCC_AHB1ENR_USB2OTGFSEN

+#define RCC_AHB1ENR_USB2OTGHSULPIEN_Pos        RCC_AHB1ENR_USB2OTGFSULPIEN_Pos

+#define RCC_AHB1ENR_USB2OTGHSULPIEN_Msk        RCC_AHB1ENR_USB2OTGFSULPIEN_Msk

+#define RCC_AHB1ENR_USB2OTGHSULPIEN            RCC_AHB1ENR_USB2OTGFSULPIEN

+

+

+/********************  Bit definition for RCC_AHB2ENR register  ***************/

+#define RCC_AHB2ENR_DCMIEN_Pos                 (0U)

+#define RCC_AHB2ENR_DCMIEN_Msk                 (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)          /*!< 0x00000001 */

+#define RCC_AHB2ENR_DCMIEN                     RCC_AHB2ENR_DCMIEN_Msk

+#define RCC_AHB2ENR_RNGEN_Pos                  (6U)

+#define RCC_AHB2ENR_RNGEN_Msk                  (0x1UL << RCC_AHB2ENR_RNGEN_Pos)           /*!< 0x00000040 */

+#define RCC_AHB2ENR_RNGEN                      RCC_AHB2ENR_RNGEN_Msk

+#define RCC_AHB2ENR_SDMMC2EN_Pos               (9U)

+#define RCC_AHB2ENR_SDMMC2EN_Msk               (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)        /*!< 0x00000200 */

+#define RCC_AHB2ENR_SDMMC2EN                   RCC_AHB2ENR_SDMMC2EN_Msk

+#define RCC_AHB2ENR_SRAM1EN_Pos                (29U)

+#define RCC_AHB2ENR_SRAM1EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos)       /*!< 0x20000000 */

+#define RCC_AHB2ENR_SRAM1EN                    RCC_AHB2ENR_SRAM1EN_Msk

+#define RCC_AHB2ENR_SRAM2EN_Pos                (30U)

+#define RCC_AHB2ENR_SRAM2EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos)       /*!< 0x40000000 */

+#define RCC_AHB2ENR_SRAM2EN                    RCC_AHB2ENR_SRAM2EN_Msk

+#define RCC_AHB2ENR_SRAM3EN_Pos                (31U)

+#define RCC_AHB2ENR_SRAM3EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM3EN_Pos)       /*!< 0x80000000 */

+#define RCC_AHB2ENR_SRAM3EN                    RCC_AHB2ENR_SRAM3EN_Msk

+

+/* Legacy define */

+#define RCC_AHB2ENR_D2SRAM1EN_Pos              RCC_AHB2ENR_SRAM1EN_Pos

+#define RCC_AHB2ENR_D2SRAM1EN_Msk              RCC_AHB2ENR_SRAM1EN_Msk

+#define RCC_AHB2ENR_D2SRAM1EN                  RCC_AHB2ENR_SRAM1EN

+#define RCC_AHB2ENR_D2SRAM2EN_Pos              RCC_AHB2ENR_SRAM2EN_Pos

+#define RCC_AHB2ENR_D2SRAM2EN_Msk              RCC_AHB2ENR_SRAM2EN_Msk

+#define RCC_AHB2ENR_D2SRAM2EN                  RCC_AHB2ENR_SRAM2EN

+#define RCC_AHB2ENR_D2SRAM3EN_Pos              RCC_AHB2ENR_SRAM3EN_Pos

+#define RCC_AHB2ENR_D2SRAM3EN_Msk              RCC_AHB2ENR_SRAM3EN_Msk

+#define RCC_AHB2ENR_D2SRAM3EN                  RCC_AHB2ENR_SRAM3EN

+

+/********************  Bit definition for RCC_AHB4ENR register  ******************/

+#define RCC_AHB4ENR_GPIOAEN_Pos                (0U)

+#define RCC_AHB4ENR_GPIOAEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)         /*!< 0x00000001 */

+#define RCC_AHB4ENR_GPIOAEN                    RCC_AHB4ENR_GPIOAEN_Msk

+#define RCC_AHB4ENR_GPIOBEN_Pos                (1U)

+#define RCC_AHB4ENR_GPIOBEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)         /*!< 0x00000002 */

+#define RCC_AHB4ENR_GPIOBEN                    RCC_AHB4ENR_GPIOBEN_Msk

+#define RCC_AHB4ENR_GPIOCEN_Pos                (2U)

+#define RCC_AHB4ENR_GPIOCEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)         /*!< 0x00000004 */

+#define RCC_AHB4ENR_GPIOCEN                    RCC_AHB4ENR_GPIOCEN_Msk

+#define RCC_AHB4ENR_GPIODEN_Pos                (3U)

+#define RCC_AHB4ENR_GPIODEN_Msk                (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)         /*!< 0x00000008 */

+#define RCC_AHB4ENR_GPIODEN                    RCC_AHB4ENR_GPIODEN_Msk

+#define RCC_AHB4ENR_GPIOEEN_Pos                (4U)

+#define RCC_AHB4ENR_GPIOEEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)         /*!< 0x00000010 */

+#define RCC_AHB4ENR_GPIOEEN                    RCC_AHB4ENR_GPIOEEN_Msk

+#define RCC_AHB4ENR_GPIOFEN_Pos                (5U)

+#define RCC_AHB4ENR_GPIOFEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)         /*!< 0x00000020 */

+#define RCC_AHB4ENR_GPIOFEN                    RCC_AHB4ENR_GPIOFEN_Msk

+#define RCC_AHB4ENR_GPIOGEN_Pos                (6U)

+#define RCC_AHB4ENR_GPIOGEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)         /*!< 0x00000040 */

+#define RCC_AHB4ENR_GPIOGEN                    RCC_AHB4ENR_GPIOGEN_Msk

+#define RCC_AHB4ENR_GPIOHEN_Pos                (7U)

+#define RCC_AHB4ENR_GPIOHEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)         /*!< 0x00000080 */

+#define RCC_AHB4ENR_GPIOHEN                    RCC_AHB4ENR_GPIOHEN_Msk

+#define RCC_AHB4ENR_GPIOIEN_Pos                (8U)

+#define RCC_AHB4ENR_GPIOIEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos)         /*!< 0x00000100 */

+#define RCC_AHB4ENR_GPIOIEN                    RCC_AHB4ENR_GPIOIEN_Msk

+#define RCC_AHB4ENR_GPIOJEN_Pos                (9U)

+#define RCC_AHB4ENR_GPIOJEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos)         /*!< 0x00000200 */

+#define RCC_AHB4ENR_GPIOJEN                    RCC_AHB4ENR_GPIOJEN_Msk

+#define RCC_AHB4ENR_GPIOKEN_Pos                (10U)

+#define RCC_AHB4ENR_GPIOKEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos)         /*!< 0x00000400 */

+#define RCC_AHB4ENR_GPIOKEN                    RCC_AHB4ENR_GPIOKEN_Msk

+#define RCC_AHB4ENR_CRCEN_Pos                  (19U)

+#define RCC_AHB4ENR_CRCEN_Msk                  (0x1UL << RCC_AHB4ENR_CRCEN_Pos)           /*!< 0x00080000 */

+#define RCC_AHB4ENR_CRCEN                      RCC_AHB4ENR_CRCEN_Msk

+#define RCC_AHB4ENR_BDMAEN_Pos                 (21U)

+#define RCC_AHB4ENR_BDMAEN_Msk                 (0x1UL << RCC_AHB4ENR_BDMAEN_Pos)          /*!< 0x00200000 */

+#define RCC_AHB4ENR_BDMAEN                     RCC_AHB4ENR_BDMAEN_Msk

+#define RCC_AHB4ENR_ADC3EN_Pos                 (24U)

+#define RCC_AHB4ENR_ADC3EN_Msk                 (0x1UL << RCC_AHB4ENR_ADC3EN_Pos)          /*!< 0x01000000 */

+#define RCC_AHB4ENR_ADC3EN                     RCC_AHB4ENR_ADC3EN_Msk

+#define RCC_AHB4ENR_HSEMEN_Pos                 (25U)

+#define RCC_AHB4ENR_HSEMEN_Msk                 (0x1UL << RCC_AHB4ENR_HSEMEN_Pos)          /*!< 0x02000000 */

+#define RCC_AHB4ENR_HSEMEN                     RCC_AHB4ENR_HSEMEN_Msk

+#define RCC_AHB4ENR_BKPRAMEN_Pos               (28U)

+#define RCC_AHB4ENR_BKPRAMEN_Msk               (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)        /*!< 0x10000000 */

+#define RCC_AHB4ENR_BKPRAMEN                   RCC_AHB4ENR_BKPRAMEN_Msk

+

+/********************  Bit definition for RCC_APB3ENR register  ******************/

+#define RCC_APB3ENR_WWDG1EN_Pos                (6U)

+#define RCC_APB3ENR_WWDG1EN_Msk                (0x1UL << RCC_APB3ENR_WWDG1EN_Pos) /*!< 0x00000040 */

+#define RCC_APB3ENR_WWDG1EN                    RCC_APB3ENR_WWDG1EN_Msk

+

+/********************  Bit definition for RCC_APB1LENR register  ******************/

+

+#define RCC_APB1LENR_TIM2EN_Pos                (0U)

+#define RCC_APB1LENR_TIM2EN_Msk                (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */

+#define RCC_APB1LENR_TIM2EN                    RCC_APB1LENR_TIM2EN_Msk

+#define RCC_APB1LENR_TIM3EN_Pos                (1U)

+#define RCC_APB1LENR_TIM3EN_Msk                (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */

+#define RCC_APB1LENR_TIM3EN                    RCC_APB1LENR_TIM3EN_Msk

+#define RCC_APB1LENR_TIM4EN_Pos                (2U)

+#define RCC_APB1LENR_TIM4EN_Msk                (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */

+#define RCC_APB1LENR_TIM4EN                    RCC_APB1LENR_TIM4EN_Msk

+#define RCC_APB1LENR_TIM5EN_Pos                (3U)

+#define RCC_APB1LENR_TIM5EN_Msk                (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */

+#define RCC_APB1LENR_TIM5EN                    RCC_APB1LENR_TIM5EN_Msk

+#define RCC_APB1LENR_TIM6EN_Pos                (4U)

+#define RCC_APB1LENR_TIM6EN_Msk                (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */

+#define RCC_APB1LENR_TIM6EN                    RCC_APB1LENR_TIM6EN_Msk

+#define RCC_APB1LENR_TIM7EN_Pos                (5U)

+#define RCC_APB1LENR_TIM7EN_Msk                (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */

+#define RCC_APB1LENR_TIM7EN                    RCC_APB1LENR_TIM7EN_Msk

+#define RCC_APB1LENR_TIM12EN_Pos               (6U)

+#define RCC_APB1LENR_TIM12EN_Msk               (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */

+#define RCC_APB1LENR_TIM12EN                   RCC_APB1LENR_TIM12EN_Msk

+#define RCC_APB1LENR_TIM13EN_Pos               (7U)

+#define RCC_APB1LENR_TIM13EN_Msk               (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */

+#define RCC_APB1LENR_TIM13EN                   RCC_APB1LENR_TIM13EN_Msk

+#define RCC_APB1LENR_TIM14EN_Pos               (8U)

+#define RCC_APB1LENR_TIM14EN_Msk               (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */

+#define RCC_APB1LENR_TIM14EN                   RCC_APB1LENR_TIM14EN_Msk

+#define RCC_APB1LENR_LPTIM1EN_Pos              (9U)

+#define RCC_APB1LENR_LPTIM1EN_Msk              (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */

+#define RCC_APB1LENR_LPTIM1EN                  RCC_APB1LENR_LPTIM1EN_Msk

+

+

+#define RCC_APB1LENR_SPI2EN_Pos                (14U)

+#define RCC_APB1LENR_SPI2EN_Msk                (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */

+#define RCC_APB1LENR_SPI2EN                    RCC_APB1LENR_SPI2EN_Msk

+#define RCC_APB1LENR_SPI3EN_Pos                (15U)

+#define RCC_APB1LENR_SPI3EN_Msk                (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */

+#define RCC_APB1LENR_SPI3EN                    RCC_APB1LENR_SPI3EN_Msk

+#define RCC_APB1LENR_SPDIFRXEN_Pos             (16U)

+#define RCC_APB1LENR_SPDIFRXEN_Msk             (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */

+#define RCC_APB1LENR_SPDIFRXEN                 RCC_APB1LENR_SPDIFRXEN_Msk

+#define RCC_APB1LENR_USART2EN_Pos              (17U)

+#define RCC_APB1LENR_USART2EN_Msk              (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */

+#define RCC_APB1LENR_USART2EN                  RCC_APB1LENR_USART2EN_Msk

+#define RCC_APB1LENR_USART3EN_Pos              (18U)

+#define RCC_APB1LENR_USART3EN_Msk              (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */

+#define RCC_APB1LENR_USART3EN                  RCC_APB1LENR_USART3EN_Msk

+#define RCC_APB1LENR_UART4EN_Pos               (19U)

+#define RCC_APB1LENR_UART4EN_Msk               (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */

+#define RCC_APB1LENR_UART4EN                   RCC_APB1LENR_UART4EN_Msk

+#define RCC_APB1LENR_UART5EN_Pos               (20U)

+#define RCC_APB1LENR_UART5EN_Msk               (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */

+#define RCC_APB1LENR_UART5EN                   RCC_APB1LENR_UART5EN_Msk

+#define RCC_APB1LENR_I2C1EN_Pos                (21U)

+#define RCC_APB1LENR_I2C1EN_Msk                (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */

+#define RCC_APB1LENR_I2C1EN                    RCC_APB1LENR_I2C1EN_Msk

+#define RCC_APB1LENR_I2C2EN_Pos                (22U)

+#define RCC_APB1LENR_I2C2EN_Msk                (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */

+#define RCC_APB1LENR_I2C2EN                    RCC_APB1LENR_I2C2EN_Msk

+#define RCC_APB1LENR_I2C3EN_Pos                (23U)

+#define RCC_APB1LENR_I2C3EN_Msk                (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */

+#define RCC_APB1LENR_I2C3EN                    RCC_APB1LENR_I2C3EN_Msk

+#define RCC_APB1LENR_CECEN_Pos                 (27U)

+#define RCC_APB1LENR_CECEN_Msk                 (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */

+#define RCC_APB1LENR_CECEN                     RCC_APB1LENR_CECEN_Msk

+#define RCC_APB1LENR_DAC12EN_Pos               (29U)

+#define RCC_APB1LENR_DAC12EN_Msk               (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */

+#define RCC_APB1LENR_DAC12EN                   RCC_APB1LENR_DAC12EN_Msk

+#define RCC_APB1LENR_UART7EN_Pos               (30U)

+#define RCC_APB1LENR_UART7EN_Msk               (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */

+#define RCC_APB1LENR_UART7EN                   RCC_APB1LENR_UART7EN_Msk

+#define RCC_APB1LENR_UART8EN_Pos               (31U)

+#define RCC_APB1LENR_UART8EN_Msk               (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */

+#define RCC_APB1LENR_UART8EN                   RCC_APB1LENR_UART8EN_Msk

+

+/* Legacy define */

+#define RCC_APB1LENR_HDMICECEN_Pos             RCC_APB1LENR_CECEN_Pos

+#define RCC_APB1LENR_HDMICECEN_Msk             RCC_APB1LENR_CECEN_Msk

+#define RCC_APB1LENR_HDMICECEN                 RCC_APB1LENR_CECEN

+/********************  Bit definition for RCC_APB1HENR register  ******************/

+#define RCC_APB1HENR_CRSEN_Pos                 (1U)

+#define RCC_APB1HENR_CRSEN_Msk                 (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1HENR_CRSEN                     RCC_APB1HENR_CRSEN_Msk

+#define RCC_APB1HENR_SWPMIEN_Pos               (2U)

+#define RCC_APB1HENR_SWPMIEN_Msk               (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1HENR_SWPMIEN                   RCC_APB1HENR_SWPMIEN_Msk

+#define RCC_APB1HENR_OPAMPEN_Pos               (4U)

+#define RCC_APB1HENR_OPAMPEN_Msk               (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1HENR_OPAMPEN                   RCC_APB1HENR_OPAMPEN_Msk

+#define RCC_APB1HENR_MDIOSEN_Pos               (5U)

+#define RCC_APB1HENR_MDIOSEN_Msk               (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1HENR_MDIOSEN                   RCC_APB1HENR_MDIOSEN_Msk

+#define RCC_APB1HENR_FDCANEN_Pos               (8U)

+#define RCC_APB1HENR_FDCANEN_Msk               (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1HENR_FDCANEN                   RCC_APB1HENR_FDCANEN_Msk

+

+/********************  Bit definition for RCC_APB2ENR register  ******************/

+#define RCC_APB2ENR_TIM1EN_Pos                 (0U)

+#define RCC_APB2ENR_TIM1EN_Msk                 (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */

+#define RCC_APB2ENR_TIM1EN                     RCC_APB2ENR_TIM1EN_Msk

+#define RCC_APB2ENR_TIM8EN_Pos                 (1U)

+#define RCC_APB2ENR_TIM8EN_Msk                 (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */

+#define RCC_APB2ENR_TIM8EN                     RCC_APB2ENR_TIM8EN_Msk

+#define RCC_APB2ENR_USART1EN_Pos               (4U)

+#define RCC_APB2ENR_USART1EN_Msk               (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */

+#define RCC_APB2ENR_USART1EN                   RCC_APB2ENR_USART1EN_Msk

+#define RCC_APB2ENR_USART6EN_Pos               (5U)

+#define RCC_APB2ENR_USART6EN_Msk               (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */

+#define RCC_APB2ENR_USART6EN                   RCC_APB2ENR_USART6EN_Msk

+#define RCC_APB2ENR_SPI1EN_Pos                 (12U)

+#define RCC_APB2ENR_SPI1EN_Msk                 (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */

+#define RCC_APB2ENR_SPI1EN                     RCC_APB2ENR_SPI1EN_Msk

+#define RCC_APB2ENR_SPI4EN_Pos                 (13U)

+#define RCC_APB2ENR_SPI4EN_Msk                 (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */

+#define RCC_APB2ENR_SPI4EN                     RCC_APB2ENR_SPI4EN_Msk

+#define RCC_APB2ENR_TIM15EN_Pos                (16U)

+#define RCC_APB2ENR_TIM15EN_Msk                (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */

+#define RCC_APB2ENR_TIM15EN                    RCC_APB2ENR_TIM15EN_Msk

+#define RCC_APB2ENR_TIM16EN_Pos                (17U)

+#define RCC_APB2ENR_TIM16EN_Msk                (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */

+#define RCC_APB2ENR_TIM16EN                    RCC_APB2ENR_TIM16EN_Msk

+#define RCC_APB2ENR_TIM17EN_Pos                (18U)

+#define RCC_APB2ENR_TIM17EN_Msk                (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */

+#define RCC_APB2ENR_TIM17EN                    RCC_APB2ENR_TIM17EN_Msk

+#define RCC_APB2ENR_SPI5EN_Pos                 (20U)

+#define RCC_APB2ENR_SPI5EN_Msk                 (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */

+#define RCC_APB2ENR_SPI5EN                     RCC_APB2ENR_SPI5EN_Msk

+#define RCC_APB2ENR_SAI1EN_Pos                 (22U)

+#define RCC_APB2ENR_SAI1EN_Msk                 (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */

+#define RCC_APB2ENR_SAI1EN                     RCC_APB2ENR_SAI1EN_Msk

+#define RCC_APB2ENR_SAI2EN_Pos                 (23U)

+#define RCC_APB2ENR_SAI2EN_Msk                 (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */

+#define RCC_APB2ENR_SAI2EN                     RCC_APB2ENR_SAI2EN_Msk

+#define RCC_APB2ENR_SAI3EN_Pos                 (24U)

+#define RCC_APB2ENR_SAI3EN_Msk                 (0x1UL << RCC_APB2ENR_SAI3EN_Pos) /*!< 0x01000000 */

+#define RCC_APB2ENR_SAI3EN                     RCC_APB2ENR_SAI3EN_Msk

+#define RCC_APB2ENR_DFSDM1EN_Pos               (28U)

+#define RCC_APB2ENR_DFSDM1EN_Msk               (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x10000000 */

+#define RCC_APB2ENR_DFSDM1EN                   RCC_APB2ENR_DFSDM1EN_Msk

+#define RCC_APB2ENR_HRTIMEN_Pos                (29U)

+#define RCC_APB2ENR_HRTIMEN_Msk                (0x1UL << RCC_APB2ENR_HRTIMEN_Pos) /*!< 0x20000000 */

+#define RCC_APB2ENR_HRTIMEN                    RCC_APB2ENR_HRTIMEN_Msk

+

+/********************  Bit definition for RCC_APB4ENR register  ******************/

+#define RCC_APB4ENR_SYSCFGEN_Pos               (1U)

+#define RCC_APB4ENR_SYSCFGEN_Msk               (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */

+#define RCC_APB4ENR_SYSCFGEN                   RCC_APB4ENR_SYSCFGEN_Msk

+#define RCC_APB4ENR_LPUART1EN_Pos              (3U)

+#define RCC_APB4ENR_LPUART1EN_Msk              (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */

+#define RCC_APB4ENR_LPUART1EN                  RCC_APB4ENR_LPUART1EN_Msk

+#define RCC_APB4ENR_SPI6EN_Pos                 (5U)

+#define RCC_APB4ENR_SPI6EN_Msk                 (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */

+#define RCC_APB4ENR_SPI6EN                     RCC_APB4ENR_SPI6EN_Msk

+#define RCC_APB4ENR_I2C4EN_Pos                 (7U)

+#define RCC_APB4ENR_I2C4EN_Msk                 (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */

+#define RCC_APB4ENR_I2C4EN                     RCC_APB4ENR_I2C4EN_Msk

+#define RCC_APB4ENR_LPTIM2EN_Pos               (9U)

+#define RCC_APB4ENR_LPTIM2EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */

+#define RCC_APB4ENR_LPTIM2EN                   RCC_APB4ENR_LPTIM2EN_Msk

+#define RCC_APB4ENR_LPTIM3EN_Pos               (10U)

+#define RCC_APB4ENR_LPTIM3EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */

+#define RCC_APB4ENR_LPTIM3EN                   RCC_APB4ENR_LPTIM3EN_Msk

+#define RCC_APB4ENR_LPTIM4EN_Pos               (11U)

+#define RCC_APB4ENR_LPTIM4EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos) /*!< 0x00000800 */

+#define RCC_APB4ENR_LPTIM4EN                   RCC_APB4ENR_LPTIM4EN_Msk

+#define RCC_APB4ENR_LPTIM5EN_Pos               (12U)

+#define RCC_APB4ENR_LPTIM5EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos) /*!< 0x00001000 */

+#define RCC_APB4ENR_LPTIM5EN                   RCC_APB4ENR_LPTIM5EN_Msk

+#define RCC_APB4ENR_COMP12EN_Pos               (14U)

+#define RCC_APB4ENR_COMP12EN_Msk               (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */

+#define RCC_APB4ENR_COMP12EN                   RCC_APB4ENR_COMP12EN_Msk

+#define RCC_APB4ENR_VREFEN_Pos                 (15U)

+#define RCC_APB4ENR_VREFEN_Msk                 (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */

+#define RCC_APB4ENR_VREFEN                     RCC_APB4ENR_VREFEN_Msk

+#define RCC_APB4ENR_RTCAPBEN_Pos               (16U)

+#define RCC_APB4ENR_RTCAPBEN_Msk               (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */

+#define RCC_APB4ENR_RTCAPBEN                   RCC_APB4ENR_RTCAPBEN_Msk

+#define RCC_APB4ENR_SAI4EN_Pos                 (21U)

+#define RCC_APB4ENR_SAI4EN_Msk                 (0x1UL << RCC_APB4ENR_SAI4EN_Pos) /*!< 0x00200000 */

+#define RCC_APB4ENR_SAI4EN                     RCC_APB4ENR_SAI4EN_Msk

+

+

+/********************  Bit definition for RCC_AHB3RSTR register  ***************/

+#define RCC_AHB3RSTR_MDMARST_Pos               (0U)

+#define RCC_AHB3RSTR_MDMARST_Msk               (0x1UL << RCC_AHB3RSTR_MDMARST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB3RSTR_MDMARST                   RCC_AHB3RSTR_MDMARST_Msk

+#define RCC_AHB3RSTR_DMA2DRST_Pos              (4U)

+#define RCC_AHB3RSTR_DMA2DRST_Msk              (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos)     /*!< 0x00000010 */

+#define RCC_AHB3RSTR_DMA2DRST                  RCC_AHB3RSTR_DMA2DRST_Msk

+#define RCC_AHB3RSTR_FMCRST_Pos                (12U)

+#define RCC_AHB3RSTR_FMCRST_Msk                (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)      /*!< 0x00001000 */

+#define RCC_AHB3RSTR_FMCRST                    RCC_AHB3RSTR_FMCRST_Msk

+#define RCC_AHB3RSTR_QSPIRST_Pos               (14U)

+#define RCC_AHB3RSTR_QSPIRST_Msk               (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)     /*!< 0x00004000 */

+#define RCC_AHB3RSTR_QSPIRST                   RCC_AHB3RSTR_QSPIRST_Msk

+#define RCC_AHB3RSTR_SDMMC1RST_Pos             (16U)

+#define RCC_AHB3RSTR_SDMMC1RST_Msk             (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos)   /*!< 0x00010000 */

+#define RCC_AHB3RSTR_SDMMC1RST                 RCC_AHB3RSTR_SDMMC1RST_Msk

+

+

+/********************  Bit definition for RCC_AHB1RSTR register  ***************/

+#define RCC_AHB1RSTR_DMA1RST_Pos               (0U)

+#define RCC_AHB1RSTR_DMA1RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB1RSTR_DMA1RST                   RCC_AHB1RSTR_DMA1RST_Msk

+#define RCC_AHB1RSTR_DMA2RST_Pos               (1U)

+#define RCC_AHB1RSTR_DMA2RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)      /*!< 0x00000002 */

+#define RCC_AHB1RSTR_DMA2RST                   RCC_AHB1RSTR_DMA2RST_Msk

+#define RCC_AHB1RSTR_ADC12RST_Pos              (5U)

+#define RCC_AHB1RSTR_ADC12RST_Msk              (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)     /*!< 0x00000020 */

+#define RCC_AHB1RSTR_ADC12RST                  RCC_AHB1RSTR_ADC12RST_Msk

+#define RCC_AHB1RSTR_ETH1MACRST_Pos            (15U)

+#define RCC_AHB1RSTR_ETH1MACRST_Msk            (0x1UL << RCC_AHB1RSTR_ETH1MACRST_Pos)   /*!< 0x00008000 */

+#define RCC_AHB1RSTR_ETH1MACRST                RCC_AHB1RSTR_ETH1MACRST_Msk

+#define RCC_AHB1RSTR_USB1OTGHSRST_Pos          (25U)

+#define RCC_AHB1RSTR_USB1OTGHSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */

+#define RCC_AHB1RSTR_USB1OTGHSRST              RCC_AHB1RSTR_USB1OTGHSRST_Msk

+#define RCC_AHB1RSTR_USB2OTGFSRST_Pos          (27U)

+#define RCC_AHB1RSTR_USB2OTGFSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB2OTGFSRST_Pos) /*!< 0x08000000 */

+#define RCC_AHB1RSTR_USB2OTGFSRST              RCC_AHB1RSTR_USB2OTGFSRST_Msk

+

+/* Legacy define */

+#define RCC_AHB1RSTR_USB2OTGHSRST_Pos          RCC_AHB1RSTR_USB2OTGFSRST_Pos

+#define RCC_AHB1RSTR_USB2OTGHSRST_Msk          RCC_AHB1RSTR_USB2OTGFSRST_Msk

+#define RCC_AHB1RSTR_USB2OTGHSRST              RCC_AHB1RSTR_USB2OTGFSRST

+

+/********************  Bit definition for RCC_AHB2RSTR register  ***************/

+#define RCC_AHB2RSTR_DCMIRST_Pos               (0U)

+#define RCC_AHB2RSTR_DCMIRST_Msk               (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)       /*!< 0x00000001 */

+#define RCC_AHB2RSTR_DCMIRST                   RCC_AHB2RSTR_DCMIRST_Msk

+#define RCC_AHB2RSTR_RNGRST_Pos                (6U)

+#define RCC_AHB2RSTR_RNGRST_Msk                (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)        /*!< 0x00000040 */

+#define RCC_AHB2RSTR_RNGRST                    RCC_AHB2RSTR_RNGRST_Msk

+#define RCC_AHB2RSTR_SDMMC2RST_Pos             (9U)

+#define RCC_AHB2RSTR_SDMMC2RST_Msk             (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)     /*!< 0x00000200 */

+#define RCC_AHB2RSTR_SDMMC2RST                 RCC_AHB2RSTR_SDMMC2RST_Msk

+

+/********************  Bit definition for RCC_AHB4RSTR register  ******************/

+#define RCC_AHB4RSTR_GPIOARST_Pos              (0U)

+#define RCC_AHB4RSTR_GPIOARST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB4RSTR_GPIOARST                  RCC_AHB4RSTR_GPIOARST_Msk

+#define RCC_AHB4RSTR_GPIOBRST_Pos              (1U)

+#define RCC_AHB4RSTR_GPIOBRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)      /*!< 0x00000002 */

+#define RCC_AHB4RSTR_GPIOBRST                  RCC_AHB4RSTR_GPIOBRST_Msk

+#define RCC_AHB4RSTR_GPIOCRST_Pos              (2U)

+#define RCC_AHB4RSTR_GPIOCRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)      /*!< 0x00000004 */

+#define RCC_AHB4RSTR_GPIOCRST                  RCC_AHB4RSTR_GPIOCRST_Msk

+#define RCC_AHB4RSTR_GPIODRST_Pos              (3U)

+#define RCC_AHB4RSTR_GPIODRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)      /*!< 0x00000008 */

+#define RCC_AHB4RSTR_GPIODRST                  RCC_AHB4RSTR_GPIODRST_Msk

+#define RCC_AHB4RSTR_GPIOERST_Pos              (4U)

+#define RCC_AHB4RSTR_GPIOERST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)      /*!< 0x00000010 */

+#define RCC_AHB4RSTR_GPIOERST                  RCC_AHB4RSTR_GPIOERST_Msk

+#define RCC_AHB4RSTR_GPIOFRST_Pos              (5U)

+#define RCC_AHB4RSTR_GPIOFRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)       /*!< 0x00000020 */

+#define RCC_AHB4RSTR_GPIOFRST                  RCC_AHB4RSTR_GPIOFRST_Msk

+#define RCC_AHB4RSTR_GPIOGRST_Pos              (6U)

+#define RCC_AHB4RSTR_GPIOGRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)       /*!< 0x00000040 */

+#define RCC_AHB4RSTR_GPIOGRST                  RCC_AHB4RSTR_GPIOGRST_Msk

+#define RCC_AHB4RSTR_GPIOHRST_Pos              (7U)

+#define RCC_AHB4RSTR_GPIOHRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)       /*!< 0x00000080 */

+#define RCC_AHB4RSTR_GPIOHRST                  RCC_AHB4RSTR_GPIOHRST_Msk

+#define RCC_AHB4RSTR_GPIOIRST_Pos              (8U)

+#define RCC_AHB4RSTR_GPIOIRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos)       /*!< 0x00000100 */

+#define RCC_AHB4RSTR_GPIOIRST                  RCC_AHB4RSTR_GPIOIRST_Msk

+#define RCC_AHB4RSTR_GPIOJRST_Pos              (9U)

+#define RCC_AHB4RSTR_GPIOJRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos)       /*!< 0x00000200 */

+#define RCC_AHB4RSTR_GPIOJRST                  RCC_AHB4RSTR_GPIOJRST_Msk

+#define RCC_AHB4RSTR_GPIOKRST_Pos              (10U)

+#define RCC_AHB4RSTR_GPIOKRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos)       /*!< 0x00000400 */

+#define RCC_AHB4RSTR_GPIOKRST                  RCC_AHB4RSTR_GPIOKRST_Msk

+#define RCC_AHB4RSTR_CRCRST_Pos                (19U)

+#define RCC_AHB4RSTR_CRCRST_Msk                (0x1UL << RCC_AHB4RSTR_CRCRST_Pos)         /*!< 0x00080000 */

+#define RCC_AHB4RSTR_CRCRST                    RCC_AHB4RSTR_CRCRST_Msk

+#define RCC_AHB4RSTR_BDMARST_Pos               (21U)

+#define RCC_AHB4RSTR_BDMARST_Msk               (0x1UL << RCC_AHB4RSTR_BDMARST_Pos)        /*!< 0x00200000 */

+#define RCC_AHB4RSTR_BDMARST                   RCC_AHB4RSTR_BDMARST_Msk

+#define RCC_AHB4RSTR_ADC3RST_Pos               (24U)

+#define RCC_AHB4RSTR_ADC3RST_Msk               (0x1UL << RCC_AHB4RSTR_ADC3RST_Pos)        /*!< 0x01000000 */

+#define RCC_AHB4RSTR_ADC3RST                   RCC_AHB4RSTR_ADC3RST_Msk

+#define RCC_AHB4RSTR_HSEMRST_Pos               (25U)

+#define RCC_AHB4RSTR_HSEMRST_Msk               (0x1UL << RCC_AHB4RSTR_HSEMRST_Pos)        /*!< 0x02000000 */

+#define RCC_AHB4RSTR_HSEMRST                   RCC_AHB4RSTR_HSEMRST_Msk

+

+

+/********************  Bit definition for RCC_APB3RSTR register  ******************/

+

+/********************  Bit definition for RCC_APB1LRSTR register  ******************/

+

+#define RCC_APB1LRSTR_TIM2RST_Pos              (0U)

+#define RCC_APB1LRSTR_TIM2RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */

+#define RCC_APB1LRSTR_TIM2RST                  RCC_APB1LRSTR_TIM2RST_Msk

+#define RCC_APB1LRSTR_TIM3RST_Pos              (1U)

+#define RCC_APB1LRSTR_TIM3RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */

+#define RCC_APB1LRSTR_TIM3RST                  RCC_APB1LRSTR_TIM3RST_Msk

+#define RCC_APB1LRSTR_TIM4RST_Pos              (2U)

+#define RCC_APB1LRSTR_TIM4RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */

+#define RCC_APB1LRSTR_TIM4RST                  RCC_APB1LRSTR_TIM4RST_Msk

+#define RCC_APB1LRSTR_TIM5RST_Pos              (3U)

+#define RCC_APB1LRSTR_TIM5RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */

+#define RCC_APB1LRSTR_TIM5RST                  RCC_APB1LRSTR_TIM5RST_Msk

+#define RCC_APB1LRSTR_TIM6RST_Pos              (4U)

+#define RCC_APB1LRSTR_TIM6RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */

+#define RCC_APB1LRSTR_TIM6RST                  RCC_APB1LRSTR_TIM6RST_Msk

+#define RCC_APB1LRSTR_TIM7RST_Pos              (5U)

+#define RCC_APB1LRSTR_TIM7RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */

+#define RCC_APB1LRSTR_TIM7RST                  RCC_APB1LRSTR_TIM7RST_Msk

+#define RCC_APB1LRSTR_TIM12RST_Pos             (6U)

+#define RCC_APB1LRSTR_TIM12RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */

+#define RCC_APB1LRSTR_TIM12RST                 RCC_APB1LRSTR_TIM12RST_Msk

+#define RCC_APB1LRSTR_TIM13RST_Pos             (7U)

+#define RCC_APB1LRSTR_TIM13RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */

+#define RCC_APB1LRSTR_TIM13RST                 RCC_APB1LRSTR_TIM13RST_Msk

+#define RCC_APB1LRSTR_TIM14RST_Pos             (8U)

+#define RCC_APB1LRSTR_TIM14RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */

+#define RCC_APB1LRSTR_TIM14RST                 RCC_APB1LRSTR_TIM14RST_Msk

+#define RCC_APB1LRSTR_LPTIM1RST_Pos            (9U)

+#define RCC_APB1LRSTR_LPTIM1RST_Msk            (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */

+#define RCC_APB1LRSTR_LPTIM1RST                RCC_APB1LRSTR_LPTIM1RST_Msk

+#define RCC_APB1LRSTR_SPI2RST_Pos              (14U)

+#define RCC_APB1LRSTR_SPI2RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */

+#define RCC_APB1LRSTR_SPI2RST                  RCC_APB1LRSTR_SPI2RST_Msk

+#define RCC_APB1LRSTR_SPI3RST_Pos              (15U)

+#define RCC_APB1LRSTR_SPI3RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */

+#define RCC_APB1LRSTR_SPI3RST                  RCC_APB1LRSTR_SPI3RST_Msk

+#define RCC_APB1LRSTR_SPDIFRXRST_Pos           (16U)

+#define RCC_APB1LRSTR_SPDIFRXRST_Msk           (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */

+#define RCC_APB1LRSTR_SPDIFRXRST               RCC_APB1LRSTR_SPDIFRXRST_Msk

+#define RCC_APB1LRSTR_USART2RST_Pos            (17U)

+#define RCC_APB1LRSTR_USART2RST_Msk            (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */

+#define RCC_APB1LRSTR_USART2RST                RCC_APB1LRSTR_USART2RST_Msk

+#define RCC_APB1LRSTR_USART3RST_Pos            (18U)

+#define RCC_APB1LRSTR_USART3RST_Msk            (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */

+#define RCC_APB1LRSTR_USART3RST                RCC_APB1LRSTR_USART3RST_Msk

+#define RCC_APB1LRSTR_UART4RST_Pos             (19U)

+#define RCC_APB1LRSTR_UART4RST_Msk             (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */

+#define RCC_APB1LRSTR_UART4RST                 RCC_APB1LRSTR_UART4RST_Msk

+#define RCC_APB1LRSTR_UART5RST_Pos             (20U)

+#define RCC_APB1LRSTR_UART5RST_Msk             (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */

+#define RCC_APB1LRSTR_UART5RST                 RCC_APB1LRSTR_UART5RST_Msk

+#define RCC_APB1LRSTR_I2C1RST_Pos              (21U)

+#define RCC_APB1LRSTR_I2C1RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */

+#define RCC_APB1LRSTR_I2C1RST                  RCC_APB1LRSTR_I2C1RST_Msk

+#define RCC_APB1LRSTR_I2C2RST_Pos              (22U)

+#define RCC_APB1LRSTR_I2C2RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */

+#define RCC_APB1LRSTR_I2C2RST                  RCC_APB1LRSTR_I2C2RST_Msk

+#define RCC_APB1LRSTR_I2C3RST_Pos              (23U)

+#define RCC_APB1LRSTR_I2C3RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */

+#define RCC_APB1LRSTR_I2C3RST                  RCC_APB1LRSTR_I2C3RST_Msk

+#define RCC_APB1LRSTR_CECRST_Pos               (27U)

+#define RCC_APB1LRSTR_CECRST_Msk               (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */

+#define RCC_APB1LRSTR_CECRST                   RCC_APB1LRSTR_CECRST_Msk

+#define RCC_APB1LRSTR_DAC12RST_Pos             (29U)

+#define RCC_APB1LRSTR_DAC12RST_Msk             (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */

+#define RCC_APB1LRSTR_DAC12RST                 RCC_APB1LRSTR_DAC12RST_Msk

+#define RCC_APB1LRSTR_UART7RST_Pos             (30U)

+#define RCC_APB1LRSTR_UART7RST_Msk             (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */

+#define RCC_APB1LRSTR_UART7RST                 RCC_APB1LRSTR_UART7RST_Msk

+#define RCC_APB1LRSTR_UART8RST_Pos             (31U)

+#define RCC_APB1LRSTR_UART8RST_Msk             (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */

+#define RCC_APB1LRSTR_UART8RST                 RCC_APB1LRSTR_UART8RST_Msk

+

+/* Legacy define */

+#define RCC_APB1LRSTR_HDMICECRST_Pos           RCC_APB1LRSTR_CECRST_Pos

+#define RCC_APB1LRSTR_HDMICECRST_Msk           RCC_APB1LRSTR_CECRST_Msk

+#define RCC_APB1LRSTR_HDMICECRST               RCC_APB1LRSTR_CECRST

+/********************  Bit definition for RCC_APB1HRSTR register  ******************/

+#define RCC_APB1HRSTR_CRSRST_Pos               (1U)

+#define RCC_APB1HRSTR_CRSRST_Msk               (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */

+#define RCC_APB1HRSTR_CRSRST                   RCC_APB1HRSTR_CRSRST_Msk

+#define RCC_APB1HRSTR_SWPMIRST_Pos             (2U)

+#define RCC_APB1HRSTR_SWPMIRST_Msk             (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */

+#define RCC_APB1HRSTR_SWPMIRST                 RCC_APB1HRSTR_SWPMIRST_Msk

+#define RCC_APB1HRSTR_OPAMPRST_Pos             (4U)

+#define RCC_APB1HRSTR_OPAMPRST_Msk             (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */

+#define RCC_APB1HRSTR_OPAMPRST                 RCC_APB1HRSTR_OPAMPRST_Msk

+#define RCC_APB1HRSTR_MDIOSRST_Pos             (5U)

+#define RCC_APB1HRSTR_MDIOSRST_Msk             (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */

+#define RCC_APB1HRSTR_MDIOSRST                 RCC_APB1HRSTR_MDIOSRST_Msk

+#define RCC_APB1HRSTR_FDCANRST_Pos             (8U)

+#define RCC_APB1HRSTR_FDCANRST_Msk             (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */

+#define RCC_APB1HRSTR_FDCANRST                 RCC_APB1HRSTR_FDCANRST_Msk

+

+/********************  Bit definition for RCC_APB2RSTR register  ******************/

+#define RCC_APB2RSTR_TIM1RST_Pos               (0U)

+#define RCC_APB2RSTR_TIM1RST_Msk               (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */

+#define RCC_APB2RSTR_TIM1RST                   RCC_APB2RSTR_TIM1RST_Msk

+#define RCC_APB2RSTR_TIM8RST_Pos               (1U)

+#define RCC_APB2RSTR_TIM8RST_Msk               (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */

+#define RCC_APB2RSTR_TIM8RST                   RCC_APB2RSTR_TIM8RST_Msk

+#define RCC_APB2RSTR_USART1RST_Pos             (4U)

+#define RCC_APB2RSTR_USART1RST_Msk             (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */

+#define RCC_APB2RSTR_USART1RST                 RCC_APB2RSTR_USART1RST_Msk

+#define RCC_APB2RSTR_USART6RST_Pos             (5U)

+#define RCC_APB2RSTR_USART6RST_Msk             (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */

+#define RCC_APB2RSTR_USART6RST                 RCC_APB2RSTR_USART6RST_Msk

+#define RCC_APB2RSTR_SPI1RST_Pos               (12U)

+#define RCC_APB2RSTR_SPI1RST_Msk               (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */

+#define RCC_APB2RSTR_SPI1RST                   RCC_APB2RSTR_SPI1RST_Msk

+#define RCC_APB2RSTR_SPI4RST_Pos               (13U)

+#define RCC_APB2RSTR_SPI4RST_Msk               (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */

+#define RCC_APB2RSTR_SPI4RST                   RCC_APB2RSTR_SPI4RST_Msk

+#define RCC_APB2RSTR_TIM15RST_Pos              (16U)

+#define RCC_APB2RSTR_TIM15RST_Msk              (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */

+#define RCC_APB2RSTR_TIM15RST                  RCC_APB2RSTR_TIM15RST_Msk

+#define RCC_APB2RSTR_TIM16RST_Pos              (17U)

+#define RCC_APB2RSTR_TIM16RST_Msk              (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */

+#define RCC_APB2RSTR_TIM16RST                  RCC_APB2RSTR_TIM16RST_Msk

+#define RCC_APB2RSTR_TIM17RST_Pos              (18U)

+#define RCC_APB2RSTR_TIM17RST_Msk              (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */

+#define RCC_APB2RSTR_TIM17RST                  RCC_APB2RSTR_TIM17RST_Msk

+#define RCC_APB2RSTR_SPI5RST_Pos               (20U)

+#define RCC_APB2RSTR_SPI5RST_Msk               (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */

+#define RCC_APB2RSTR_SPI5RST                   RCC_APB2RSTR_SPI5RST_Msk

+#define RCC_APB2RSTR_SAI1RST_Pos               (22U)

+#define RCC_APB2RSTR_SAI1RST_Msk               (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */

+#define RCC_APB2RSTR_SAI1RST                   RCC_APB2RSTR_SAI1RST_Msk

+#define RCC_APB2RSTR_SAI2RST_Pos               (23U)

+#define RCC_APB2RSTR_SAI2RST_Msk               (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */

+#define RCC_APB2RSTR_SAI2RST                   RCC_APB2RSTR_SAI2RST_Msk

+#define RCC_APB2RSTR_SAI3RST_Pos               (24U)

+#define RCC_APB2RSTR_SAI3RST_Msk               (0x1UL << RCC_APB2RSTR_SAI3RST_Pos) /*!< 0x01000000 */

+#define RCC_APB2RSTR_SAI3RST                   RCC_APB2RSTR_SAI3RST_Msk

+#define RCC_APB2RSTR_DFSDM1RST_Pos             (28U)

+#define RCC_APB2RSTR_DFSDM1RST_Msk             (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */

+#define RCC_APB2RSTR_DFSDM1RST                 RCC_APB2RSTR_DFSDM1RST_Msk

+#define RCC_APB2RSTR_HRTIMRST_Pos              (29U)

+#define RCC_APB2RSTR_HRTIMRST_Msk              (0x1UL << RCC_APB2RSTR_HRTIMRST_Pos) /*!< 0x20000000 */

+#define RCC_APB2RSTR_HRTIMRST                  RCC_APB2RSTR_HRTIMRST_Msk

+

+/********************  Bit definition for RCC_APB4RSTR register  ******************/

+#define RCC_APB4RSTR_SYSCFGRST_Pos             (1U)

+#define RCC_APB4RSTR_SYSCFGRST_Msk             (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */

+#define RCC_APB4RSTR_SYSCFGRST                 RCC_APB4RSTR_SYSCFGRST_Msk

+#define RCC_APB4RSTR_LPUART1RST_Pos            (3U)

+#define RCC_APB4RSTR_LPUART1RST_Msk            (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */

+#define RCC_APB4RSTR_LPUART1RST                RCC_APB4RSTR_LPUART1RST_Msk

+#define RCC_APB4RSTR_SPI6RST_Pos               (5U)

+#define RCC_APB4RSTR_SPI6RST_Msk               (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */

+#define RCC_APB4RSTR_SPI6RST                   RCC_APB4RSTR_SPI6RST_Msk

+#define RCC_APB4RSTR_I2C4RST_Pos               (7U)

+#define RCC_APB4RSTR_I2C4RST_Msk               (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */

+#define RCC_APB4RSTR_I2C4RST                   RCC_APB4RSTR_I2C4RST_Msk

+#define RCC_APB4RSTR_LPTIM2RST_Pos             (9U)

+#define RCC_APB4RSTR_LPTIM2RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */

+#define RCC_APB4RSTR_LPTIM2RST                 RCC_APB4RSTR_LPTIM2RST_Msk

+#define RCC_APB4RSTR_LPTIM3RST_Pos             (10U)

+#define RCC_APB4RSTR_LPTIM3RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */

+#define RCC_APB4RSTR_LPTIM3RST                 RCC_APB4RSTR_LPTIM3RST_Msk

+#define RCC_APB4RSTR_LPTIM4RST_Pos             (11U)

+#define RCC_APB4RSTR_LPTIM4RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos) /*!< 0x00000800 */

+#define RCC_APB4RSTR_LPTIM4RST                 RCC_APB4RSTR_LPTIM4RST_Msk

+#define RCC_APB4RSTR_LPTIM5RST_Pos             (12U)

+#define RCC_APB4RSTR_LPTIM5RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos) /*!< 0x00001000 */

+#define RCC_APB4RSTR_LPTIM5RST                 RCC_APB4RSTR_LPTIM5RST_Msk

+#define RCC_APB4RSTR_COMP12RST_Pos             (14U)

+#define RCC_APB4RSTR_COMP12RST_Msk             (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */

+#define RCC_APB4RSTR_COMP12RST                 RCC_APB4RSTR_COMP12RST_Msk

+#define RCC_APB4RSTR_VREFRST_Pos               (15U)

+#define RCC_APB4RSTR_VREFRST_Msk               (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */

+#define RCC_APB4RSTR_VREFRST                   RCC_APB4RSTR_VREFRST_Msk

+#define RCC_APB4RSTR_SAI4RST_Pos               (21U)

+#define RCC_APB4RSTR_SAI4RST_Msk               (0x1UL << RCC_APB4RSTR_SAI4RST_Pos) /*!< 0x00200000 */

+#define RCC_APB4RSTR_SAI4RST                   RCC_APB4RSTR_SAI4RST_Msk

+

+

+/********************  Bit definition for RCC_GCR register  ********************/

+#define RCC_GCR_WW1RSC_Pos                     (0U)

+#define RCC_GCR_WW1RSC_Msk                     (0x1UL << RCC_GCR_WW1RSC_Pos)   /*!< 0x00000001 */

+#define RCC_GCR_WW1RSC                         RCC_GCR_WW1RSC_Msk

+

+/********************  Bit definition for RCC_D3AMR register  ********************/

+#define RCC_D3AMR_BDMAAMEN_Pos                 (0U)

+#define RCC_D3AMR_BDMAAMEN_Msk                 (0x1UL << RCC_D3AMR_BDMAAMEN_Pos) /*!< 0x00000001 */

+#define RCC_D3AMR_BDMAAMEN                     RCC_D3AMR_BDMAAMEN_Msk

+#define RCC_D3AMR_LPUART1AMEN_Pos              (3U)

+#define RCC_D3AMR_LPUART1AMEN_Msk              (0x1UL << RCC_D3AMR_LPUART1AMEN_Pos) /*!< 0x00000008 */

+#define RCC_D3AMR_LPUART1AMEN                  RCC_D3AMR_LPUART1AMEN_Msk

+#define RCC_D3AMR_SPI6AMEN_Pos                 (5U)

+#define RCC_D3AMR_SPI6AMEN_Msk                 (0x1UL << RCC_D3AMR_SPI6AMEN_Pos) /*!< 0x00000020 */

+#define RCC_D3AMR_SPI6AMEN                     RCC_D3AMR_SPI6AMEN_Msk

+#define RCC_D3AMR_I2C4AMEN_Pos                 (7U)

+#define RCC_D3AMR_I2C4AMEN_Msk                 (0x1UL << RCC_D3AMR_I2C4AMEN_Pos) /*!< 0x00000080 */

+#define RCC_D3AMR_I2C4AMEN                     RCC_D3AMR_I2C4AMEN_Msk

+#define RCC_D3AMR_LPTIM2AMEN_Pos               (9U)

+#define RCC_D3AMR_LPTIM2AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */

+#define RCC_D3AMR_LPTIM2AMEN                   RCC_D3AMR_LPTIM2AMEN_Msk

+#define RCC_D3AMR_LPTIM3AMEN_Pos               (10U)

+#define RCC_D3AMR_LPTIM3AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */

+#define RCC_D3AMR_LPTIM3AMEN                   RCC_D3AMR_LPTIM3AMEN_Msk

+#define RCC_D3AMR_LPTIM4AMEN_Pos               (11U)

+#define RCC_D3AMR_LPTIM4AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM4AMEN_Pos) /*!< 0x00000800 */

+#define RCC_D3AMR_LPTIM4AMEN                   RCC_D3AMR_LPTIM4AMEN_Msk

+#define RCC_D3AMR_LPTIM5AMEN_Pos               (12U)

+#define RCC_D3AMR_LPTIM5AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM5AMEN_Pos) /*!< 0x00001000 */

+#define RCC_D3AMR_LPTIM5AMEN                   RCC_D3AMR_LPTIM5AMEN_Msk

+#define RCC_D3AMR_COMP12AMEN_Pos               (14U)

+#define RCC_D3AMR_COMP12AMEN_Msk               (0x1UL << RCC_D3AMR_COMP12AMEN_Pos) /*!< 0x00004000 */

+#define RCC_D3AMR_COMP12AMEN                   RCC_D3AMR_COMP12AMEN_Msk

+#define RCC_D3AMR_VREFAMEN_Pos                 (15U)

+#define RCC_D3AMR_VREFAMEN_Msk                 (0x1UL << RCC_D3AMR_VREFAMEN_Pos) /*!< 0x00008000 */

+#define RCC_D3AMR_VREFAMEN                     RCC_D3AMR_VREFAMEN_Msk

+#define RCC_D3AMR_RTCAMEN_Pos                  (16U)

+#define RCC_D3AMR_RTCAMEN_Msk                  (0x1UL << RCC_D3AMR_RTCAMEN_Pos) /*!< 0x00010000 */

+#define RCC_D3AMR_RTCAMEN                      RCC_D3AMR_RTCAMEN_Msk

+#define RCC_D3AMR_CRCAMEN_Pos                  (19U)

+#define RCC_D3AMR_CRCAMEN_Msk                  (0x1UL << RCC_D3AMR_CRCAMEN_Pos) /*!< 0x00080000 */

+#define RCC_D3AMR_CRCAMEN                      RCC_D3AMR_CRCAMEN_Msk

+#define RCC_D3AMR_SAI4AMEN_Pos                 (21U)

+#define RCC_D3AMR_SAI4AMEN_Msk                 (0x1UL << RCC_D3AMR_SAI4AMEN_Pos) /*!< 0x00200000 */

+#define RCC_D3AMR_SAI4AMEN                     RCC_D3AMR_SAI4AMEN_Msk

+#define RCC_D3AMR_ADC3AMEN_Pos                 (24U)

+#define RCC_D3AMR_ADC3AMEN_Msk                 (0x1UL << RCC_D3AMR_ADC3AMEN_Pos) /*!< 0x01000000 */

+#define RCC_D3AMR_ADC3AMEN                     RCC_D3AMR_ADC3AMEN_Msk

+

+

+#define RCC_D3AMR_BKPRAMAMEN_Pos               (28U)

+#define RCC_D3AMR_BKPRAMAMEN_Msk               (0x1UL << RCC_D3AMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */

+#define RCC_D3AMR_BKPRAMAMEN                   RCC_D3AMR_BKPRAMAMEN_Msk

+#define RCC_D3AMR_SRAM4AMEN_Pos                (29U)

+#define RCC_D3AMR_SRAM4AMEN_Msk                (0x1UL << RCC_D3AMR_SRAM4AMEN_Pos) /*!< 0x20000000 */

+#define RCC_D3AMR_SRAM4AMEN                    RCC_D3AMR_SRAM4AMEN_Msk

+/********************  Bit definition for RCC_AHB3LPENR register  **************/

+#define RCC_AHB3LPENR_MDMALPEN_Pos             (0U)

+#define RCC_AHB3LPENR_MDMALPEN_Msk             (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos)         /*!< 0x00000001 */

+#define RCC_AHB3LPENR_MDMALPEN                 RCC_AHB3LPENR_MDMALPEN_Msk

+#define RCC_AHB3LPENR_DMA2DLPEN_Pos            (4U)

+#define RCC_AHB3LPENR_DMA2DLPEN_Msk            (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos)        /*!< 0x00000010 */

+#define RCC_AHB3LPENR_DMA2DLPEN                RCC_AHB3LPENR_DMA2DLPEN_Msk

+#define RCC_AHB3LPENR_FLASHLPEN_Pos            (8U)

+#define RCC_AHB3LPENR_FLASHLPEN_Msk            (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos)        /*!< 0x00000100 */

+#define RCC_AHB3LPENR_FLASHLPEN                RCC_AHB3LPENR_FLASHLPEN_Msk

+#define RCC_AHB3LPENR_FMCLPEN_Pos              (12U)

+#define RCC_AHB3LPENR_FMCLPEN_Msk              (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)          /*!< 0x00001000 */

+#define RCC_AHB3LPENR_FMCLPEN                  RCC_AHB3LPENR_FMCLPEN_Msk

+#define RCC_AHB3LPENR_QSPILPEN_Pos             (14U)

+#define RCC_AHB3LPENR_QSPILPEN_Msk             (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos)         /*!< 0x00004000 */

+#define RCC_AHB3LPENR_QSPILPEN                 RCC_AHB3LPENR_QSPILPEN_Msk

+#define RCC_AHB3LPENR_SDMMC1LPEN_Pos           (16U)

+#define RCC_AHB3LPENR_SDMMC1LPEN_Msk           (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos)       /*!< 0x00010000 */

+#define RCC_AHB3LPENR_SDMMC1LPEN               RCC_AHB3LPENR_SDMMC1LPEN_Msk

+#define RCC_AHB3LPENR_DTCM1LPEN_Pos            (28U)

+#define RCC_AHB3LPENR_DTCM1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos)        /*!< 0x10000000 */

+#define RCC_AHB3LPENR_DTCM1LPEN                RCC_AHB3LPENR_DTCM1LPEN_Msk

+#define RCC_AHB3LPENR_DTCM2LPEN_Pos            (29U)

+#define RCC_AHB3LPENR_DTCM2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos)        /*!< 0x20000000 */

+#define RCC_AHB3LPENR_DTCM2LPEN                RCC_AHB3LPENR_DTCM2LPEN_Msk

+#define RCC_AHB3LPENR_ITCMLPEN_Pos             (30U)

+#define RCC_AHB3LPENR_ITCMLPEN_Msk             (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos)         /*!< 0x40000000 */

+#define RCC_AHB3LPENR_ITCMLPEN                 RCC_AHB3LPENR_ITCMLPEN_Msk

+#define RCC_AHB3LPENR_AXISRAMLPEN_Pos          (31U)

+#define RCC_AHB3LPENR_AXISRAMLPEN_Msk          (0x1UL << RCC_AHB3LPENR_AXISRAMLPEN_Pos)      /*!< 0x80000000 */

+#define RCC_AHB3LPENR_AXISRAMLPEN              RCC_AHB3LPENR_AXISRAMLPEN_Msk

+

+

+/********************  Bit definition for RCC_AHB1LPENR register  ***************/

+#define RCC_AHB1LPENR_DMA1LPEN_Pos             (0U)

+#define RCC_AHB1LPENR_DMA1LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB1LPENR_DMA1LPEN                 RCC_AHB1LPENR_DMA1LPEN_Msk

+#define RCC_AHB1LPENR_DMA2LPEN_Pos             (1U)

+#define RCC_AHB1LPENR_DMA2LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */

+#define RCC_AHB1LPENR_DMA2LPEN                 RCC_AHB1LPENR_DMA2LPEN_Msk

+#define RCC_AHB1LPENR_ADC12LPEN_Pos            (5U)

+#define RCC_AHB1LPENR_ADC12LPEN_Msk            (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB1LPENR_ADC12LPEN                RCC_AHB1LPENR_ADC12LPEN_Msk

+#define RCC_AHB1LPENR_ETH1MACLPEN_Pos          (15U)

+#define RCC_AHB1LPENR_ETH1MACLPEN_Msk          (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) /*!< 0x00008000 */

+#define RCC_AHB1LPENR_ETH1MACLPEN              RCC_AHB1LPENR_ETH1MACLPEN_Msk

+#define RCC_AHB1LPENR_ETH1TXLPEN_Pos           (16U)

+#define RCC_AHB1LPENR_ETH1TXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00010000 */

+#define RCC_AHB1LPENR_ETH1TXLPEN               RCC_AHB1LPENR_ETH1TXLPEN_Msk

+#define RCC_AHB1LPENR_ETH1RXLPEN_Pos           (17U)

+#define RCC_AHB1LPENR_ETH1RXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00020000 */

+#define RCC_AHB1LPENR_ETH1RXLPEN               RCC_AHB1LPENR_ETH1RXLPEN_Msk

+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos        (25U)

+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */

+#define RCC_AHB1LPENR_USB1OTGHSLPEN            RCC_AHB1LPENR_USB1OTGHSLPEN_Msk

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos    (26U)

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN        RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGFSLPEN_Pos        (27U)

+#define RCC_AHB1LPENR_USB2OTGFSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB2OTGFSLPEN_Pos) /*!< 0x08000000 */

+#define RCC_AHB1LPENR_USB2OTGFSLPEN            RCC_AHB1LPENR_USB2OTGFSLPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos    (28U)

+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos) /*!< 0x10000000 */

+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN        RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk

+

+/* Legacy define */

+#define RCC_AHB1LPENR_USB2OTGHSLPEN_Pos        RCC_AHB1LPENR_USB2OTGFSLPEN_Pos

+#define RCC_AHB1LPENR_USB2OTGHSLPEN_Msk        RCC_AHB1LPENR_USB2OTGFSLPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGHSLPEN            RCC_AHB1LPENR_USB2OTGFSLPEN

+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Pos    RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos

+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Msk    RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN        RCC_AHB1LPENR_USB2OTGFSULPILPEN

+

+/********************  Bit definition for RCC_AHB2LPENR register  ***************/

+#define RCC_AHB2LPENR_DCMILPEN_Pos             (0U)

+#define RCC_AHB2LPENR_DCMILPEN_Msk             (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB2LPENR_DCMILPEN                 RCC_AHB2LPENR_DCMILPEN_Msk

+#define RCC_AHB2LPENR_RNGLPEN_Pos              (6U)

+#define RCC_AHB2LPENR_RNGLPEN_Msk              (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */

+#define RCC_AHB2LPENR_RNGLPEN                  RCC_AHB2LPENR_RNGLPEN_Msk

+#define RCC_AHB2LPENR_SDMMC2LPEN_Pos           (9U)

+#define RCC_AHB2LPENR_SDMMC2LPEN_Msk           (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */

+#define RCC_AHB2LPENR_SDMMC2LPEN               RCC_AHB2LPENR_SDMMC2LPEN_Msk

+#define RCC_AHB2LPENR_SRAM1LPEN_Pos          (29U)

+#define RCC_AHB2LPENR_SRAM1LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos) /*!< 0x20000000 */

+#define RCC_AHB2LPENR_SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN_Msk

+#define RCC_AHB2LPENR_SRAM2LPEN_Pos          (30U)

+#define RCC_AHB2LPENR_SRAM2LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */

+#define RCC_AHB2LPENR_SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN_Msk

+#define RCC_AHB2LPENR_SRAM3LPEN_Pos          (31U)

+#define RCC_AHB2LPENR_SRAM3LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM3LPEN_Pos) /*!< 0x80000000 */

+#define RCC_AHB2LPENR_SRAM3LPEN              RCC_AHB2LPENR_SRAM3LPEN_Msk

+

+/* Legacy define */

+#define RCC_AHB2LPENR_D2SRAM1LPEN_Pos          RCC_AHB2LPENR_SRAM1LPEN_Pos

+#define RCC_AHB2LPENR_D2SRAM1LPEN_Msk          RCC_AHB2LPENR_SRAM1LPEN_Msk

+#define RCC_AHB2LPENR_D2SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN

+#define RCC_AHB2LPENR_D2SRAM2LPEN_Pos          RCC_AHB2LPENR_SRAM2LPEN_Pos

+#define RCC_AHB2LPENR_D2SRAM2LPEN_Msk          RCC_AHB2LPENR_SRAM2LPEN_Msk

+#define RCC_AHB2LPENR_D2SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN

+#define RCC_AHB2LPENR_D2SRAM3LPEN_Pos          RCC_AHB2LPENR_SRAM3LPEN_Pos

+#define RCC_AHB2LPENR_D2SRAM3LPEN_Msk          RCC_AHB2LPENR_SRAM3LPEN_Msk

+#define RCC_AHB2LPENR_D2SRAM3LPEN              RCC_AHB2LPENR_SRAM3LPEN

+

+/********************  Bit definition for RCC_AHB4LPENR register  ******************/

+#define RCC_AHB4LPENR_GPIOALPEN_Pos            (0U)

+#define RCC_AHB4LPENR_GPIOALPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB4LPENR_GPIOALPEN                RCC_AHB4LPENR_GPIOALPEN_Msk

+#define RCC_AHB4LPENR_GPIOBLPEN_Pos            (1U)

+#define RCC_AHB4LPENR_GPIOBLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */

+#define RCC_AHB4LPENR_GPIOBLPEN                RCC_AHB4LPENR_GPIOBLPEN_Msk

+#define RCC_AHB4LPENR_GPIOCLPEN_Pos            (2U)

+#define RCC_AHB4LPENR_GPIOCLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */

+#define RCC_AHB4LPENR_GPIOCLPEN                RCC_AHB4LPENR_GPIOCLPEN_Msk

+#define RCC_AHB4LPENR_GPIODLPEN_Pos            (3U)

+#define RCC_AHB4LPENR_GPIODLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */

+#define RCC_AHB4LPENR_GPIODLPEN                RCC_AHB4LPENR_GPIODLPEN_Msk

+#define RCC_AHB4LPENR_GPIOELPEN_Pos            (4U)

+#define RCC_AHB4LPENR_GPIOELPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */

+#define RCC_AHB4LPENR_GPIOELPEN                RCC_AHB4LPENR_GPIOELPEN_Msk

+#define RCC_AHB4LPENR_GPIOFLPEN_Pos            (5U)

+#define RCC_AHB4LPENR_GPIOFLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB4LPENR_GPIOFLPEN                RCC_AHB4LPENR_GPIOFLPEN_Msk

+#define RCC_AHB4LPENR_GPIOGLPEN_Pos            (6U)

+#define RCC_AHB4LPENR_GPIOGLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */

+#define RCC_AHB4LPENR_GPIOGLPEN                RCC_AHB4LPENR_GPIOGLPEN_Msk

+#define RCC_AHB4LPENR_GPIOHLPEN_Pos            (7U)

+#define RCC_AHB4LPENR_GPIOHLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */

+#define RCC_AHB4LPENR_GPIOHLPEN                RCC_AHB4LPENR_GPIOHLPEN_Msk

+#define RCC_AHB4LPENR_GPIOILPEN_Pos            (8U)

+#define RCC_AHB4LPENR_GPIOILPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */

+#define RCC_AHB4LPENR_GPIOILPEN                RCC_AHB4LPENR_GPIOILPEN_Msk

+#define RCC_AHB4LPENR_GPIOJLPEN_Pos            (9U)

+#define RCC_AHB4LPENR_GPIOJLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */

+#define RCC_AHB4LPENR_GPIOJLPEN                RCC_AHB4LPENR_GPIOJLPEN_Msk

+#define RCC_AHB4LPENR_GPIOKLPEN_Pos            (10U)

+#define RCC_AHB4LPENR_GPIOKLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */

+#define RCC_AHB4LPENR_GPIOKLPEN                RCC_AHB4LPENR_GPIOKLPEN_Msk

+#define RCC_AHB4LPENR_CRCLPEN_Pos              (19U)

+#define RCC_AHB4LPENR_CRCLPEN_Msk              (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */

+#define RCC_AHB4LPENR_CRCLPEN                  RCC_AHB4LPENR_CRCLPEN_Msk

+#define RCC_AHB4LPENR_BDMALPEN_Pos             (21U)

+#define RCC_AHB4LPENR_BDMALPEN_Msk             (0x1UL << RCC_AHB4LPENR_BDMALPEN_Pos) /*!< 0x00200000 */

+#define RCC_AHB4LPENR_BDMALPEN                 RCC_AHB4LPENR_BDMALPEN_Msk

+#define RCC_AHB4LPENR_ADC3LPEN_Pos             (24U)

+#define RCC_AHB4LPENR_ADC3LPEN_Msk             (0x1UL << RCC_AHB4LPENR_ADC3LPEN_Pos) /*!< 0x01000000 */

+#define RCC_AHB4LPENR_ADC3LPEN                 RCC_AHB4LPENR_ADC3LPEN_Msk

+#define RCC_AHB4LPENR_BKPRAMLPEN_Pos           (28U)

+#define RCC_AHB4LPENR_BKPRAMLPEN_Msk           (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */

+#define RCC_AHB4LPENR_BKPRAMLPEN               RCC_AHB4LPENR_BKPRAMLPEN_Msk

+#define RCC_AHB4LPENR_SRAM4LPEN_Pos            (29U)

+#define RCC_AHB4LPENR_SRAM4LPEN_Msk            (0x1UL << RCC_AHB4LPENR_SRAM4LPEN_Pos) /*!< 0x20000000 */

+#define RCC_AHB4LPENR_SRAM4LPEN                RCC_AHB4LPENR_SRAM4LPEN_Msk

+

+/* Legacy define */

+#define RCC_AHB4LPENR_D3SRAM1LPEN_Pos          RCC_AHB4LPENR_SRAM4LPEN_Pos

+#define RCC_AHB4LPENR_D3SRAM1LPEN_Msk          RCC_AHB4LPENR_SRAM4LPEN_Msk

+#define RCC_AHB4LPENR_D3SRAM1LPEN              RCC_AHB4LPENR_SRAM4LPEN

+/********************  Bit definition for RCC_APB3LPENR register  ******************/

+#define RCC_APB3LPENR_WWDG1LPEN_Pos            (6U)

+#define RCC_APB3LPENR_WWDG1LPEN_Msk            (0x1UL << RCC_APB3LPENR_WWDG1LPEN_Pos) /*!< 0x00000040 */

+#define RCC_APB3LPENR_WWDG1LPEN                RCC_APB3LPENR_WWDG1LPEN_Msk

+

+/********************  Bit definition for RCC_APB1LLPENR register  ******************/

+

+#define RCC_APB1LLPENR_TIM2LPEN_Pos            (0U)

+#define RCC_APB1LLPENR_TIM2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */

+#define RCC_APB1LLPENR_TIM2LPEN                RCC_APB1LLPENR_TIM2LPEN_Msk

+#define RCC_APB1LLPENR_TIM3LPEN_Pos            (1U)

+#define RCC_APB1LLPENR_TIM3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1LLPENR_TIM3LPEN                RCC_APB1LLPENR_TIM3LPEN_Msk

+#define RCC_APB1LLPENR_TIM4LPEN_Pos            (2U)

+#define RCC_APB1LLPENR_TIM4LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1LLPENR_TIM4LPEN                RCC_APB1LLPENR_TIM4LPEN_Msk

+#define RCC_APB1LLPENR_TIM5LPEN_Pos            (3U)

+#define RCC_APB1LLPENR_TIM5LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB1LLPENR_TIM5LPEN                RCC_APB1LLPENR_TIM5LPEN_Msk

+#define RCC_APB1LLPENR_TIM6LPEN_Pos            (4U)

+#define RCC_APB1LLPENR_TIM6LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1LLPENR_TIM6LPEN                RCC_APB1LLPENR_TIM6LPEN_Msk

+#define RCC_APB1LLPENR_TIM7LPEN_Pos            (5U)

+#define RCC_APB1LLPENR_TIM7LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1LLPENR_TIM7LPEN                RCC_APB1LLPENR_TIM7LPEN_Msk

+#define RCC_APB1LLPENR_TIM12LPEN_Pos           (6U)

+#define RCC_APB1LLPENR_TIM12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */

+#define RCC_APB1LLPENR_TIM12LPEN               RCC_APB1LLPENR_TIM12LPEN_Msk

+#define RCC_APB1LLPENR_TIM13LPEN_Pos           (7U)

+#define RCC_APB1LLPENR_TIM13LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB1LLPENR_TIM13LPEN               RCC_APB1LLPENR_TIM13LPEN_Msk

+#define RCC_APB1LLPENR_TIM14LPEN_Pos           (8U)

+#define RCC_APB1LLPENR_TIM14LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1LLPENR_TIM14LPEN               RCC_APB1LLPENR_TIM14LPEN_Msk

+#define RCC_APB1LLPENR_LPTIM1LPEN_Pos          (9U)

+#define RCC_APB1LLPENR_LPTIM1LPEN_Msk          (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */

+#define RCC_APB1LLPENR_LPTIM1LPEN              RCC_APB1LLPENR_LPTIM1LPEN_Msk

+

+

+#define RCC_APB1LLPENR_SPI2LPEN_Pos            (14U)

+#define RCC_APB1LLPENR_SPI2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */

+#define RCC_APB1LLPENR_SPI2LPEN                RCC_APB1LLPENR_SPI2LPEN_Msk

+#define RCC_APB1LLPENR_SPI3LPEN_Pos            (15U)

+#define RCC_APB1LLPENR_SPI3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */

+#define RCC_APB1LLPENR_SPI3LPEN                RCC_APB1LLPENR_SPI3LPEN_Msk

+#define RCC_APB1LLPENR_SPDIFRXLPEN_Pos         (16U)

+#define RCC_APB1LLPENR_SPDIFRXLPEN_Msk         (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB1LLPENR_SPDIFRXLPEN             RCC_APB1LLPENR_SPDIFRXLPEN_Msk

+#define RCC_APB1LLPENR_USART2LPEN_Pos          (17U)

+#define RCC_APB1LLPENR_USART2LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */

+#define RCC_APB1LLPENR_USART2LPEN              RCC_APB1LLPENR_USART2LPEN_Msk

+#define RCC_APB1LLPENR_USART3LPEN_Pos          (18U)

+#define RCC_APB1LLPENR_USART3LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */

+#define RCC_APB1LLPENR_USART3LPEN              RCC_APB1LLPENR_USART3LPEN_Msk

+#define RCC_APB1LLPENR_UART4LPEN_Pos           (19U)

+#define RCC_APB1LLPENR_UART4LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */

+#define RCC_APB1LLPENR_UART4LPEN               RCC_APB1LLPENR_UART4LPEN_Msk

+#define RCC_APB1LLPENR_UART5LPEN_Pos           (20U)

+#define RCC_APB1LLPENR_UART5LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */

+#define RCC_APB1LLPENR_UART5LPEN               RCC_APB1LLPENR_UART5LPEN_Msk

+#define RCC_APB1LLPENR_I2C1LPEN_Pos            (21U)

+#define RCC_APB1LLPENR_I2C1LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */

+#define RCC_APB1LLPENR_I2C1LPEN                RCC_APB1LLPENR_I2C1LPEN_Msk

+#define RCC_APB1LLPENR_I2C2LPEN_Pos            (22U)

+#define RCC_APB1LLPENR_I2C2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */

+#define RCC_APB1LLPENR_I2C2LPEN                RCC_APB1LLPENR_I2C2LPEN_Msk

+#define RCC_APB1LLPENR_I2C3LPEN_Pos            (23U)

+#define RCC_APB1LLPENR_I2C3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */

+#define RCC_APB1LLPENR_I2C3LPEN                RCC_APB1LLPENR_I2C3LPEN_Msk

+#define RCC_APB1LLPENR_CECLPEN_Pos             (27U)

+#define RCC_APB1LLPENR_CECLPEN_Msk             (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */

+#define RCC_APB1LLPENR_CECLPEN                 RCC_APB1LLPENR_CECLPEN_Msk

+#define RCC_APB1LLPENR_DAC12LPEN_Pos           (29U)

+#define RCC_APB1LLPENR_DAC12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */

+#define RCC_APB1LLPENR_DAC12LPEN               RCC_APB1LLPENR_DAC12LPEN_Msk

+#define RCC_APB1LLPENR_UART7LPEN_Pos           (30U)

+#define RCC_APB1LLPENR_UART7LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */

+#define RCC_APB1LLPENR_UART7LPEN               RCC_APB1LLPENR_UART7LPEN_Msk

+#define RCC_APB1LLPENR_UART8LPEN_Pos           (31U)

+#define RCC_APB1LLPENR_UART8LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */

+#define RCC_APB1LLPENR_UART8LPEN               RCC_APB1LLPENR_UART8LPEN_Msk

+

+/* Legacy define */

+#define RCC_APB1LLPENR_HDMICECEN_Pos           RCC_APB1LLPENR_CECLPEN_Pos

+#define RCC_APB1LLPENR_HDMICECEN_Msk           RCC_APB1LLPENR_CECLPEN_Msk

+#define RCC_APB1LLPENR_HDMICECEN               RCC_APB1LLPENR_CECLPEN

+/********************  Bit definition for RCC_APB1HLPENR register  ******************/

+#define RCC_APB1HLPENR_CRSLPEN_Pos             (1U)

+#define RCC_APB1HLPENR_CRSLPEN_Msk             (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1HLPENR_CRSLPEN                 RCC_APB1HLPENR_CRSLPEN_Msk

+#define RCC_APB1HLPENR_SWPMILPEN_Pos           (2U)

+#define RCC_APB1HLPENR_SWPMILPEN_Msk           (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1HLPENR_SWPMILPEN               RCC_APB1HLPENR_SWPMILPEN_Msk

+#define RCC_APB1HLPENR_OPAMPLPEN_Pos           (4U)

+#define RCC_APB1HLPENR_OPAMPLPEN_Msk           (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1HLPENR_OPAMPLPEN               RCC_APB1HLPENR_OPAMPLPEN_Msk

+#define RCC_APB1HLPENR_MDIOSLPEN_Pos           (5U)

+#define RCC_APB1HLPENR_MDIOSLPEN_Msk           (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1HLPENR_MDIOSLPEN               RCC_APB1HLPENR_MDIOSLPEN_Msk

+#define RCC_APB1HLPENR_FDCANLPEN_Pos           (8U)

+#define RCC_APB1HLPENR_FDCANLPEN_Msk           (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1HLPENR_FDCANLPEN               RCC_APB1HLPENR_FDCANLPEN_Msk

+

+/********************  Bit definition for RCC_APB2LPENR register  ******************/

+#define RCC_APB2LPENR_TIM1LPEN_Pos             (0U)

+#define RCC_APB2LPENR_TIM1LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */

+#define RCC_APB2LPENR_TIM1LPEN                 RCC_APB2LPENR_TIM1LPEN_Msk

+#define RCC_APB2LPENR_TIM8LPEN_Pos             (1U)

+#define RCC_APB2LPENR_TIM8LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB2LPENR_TIM8LPEN                 RCC_APB2LPENR_TIM8LPEN_Msk

+#define RCC_APB2LPENR_USART1LPEN_Pos           (4U)

+#define RCC_APB2LPENR_USART1LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB2LPENR_USART1LPEN               RCC_APB2LPENR_USART1LPEN_Msk

+#define RCC_APB2LPENR_USART6LPEN_Pos           (5U)

+#define RCC_APB2LPENR_USART6LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB2LPENR_USART6LPEN               RCC_APB2LPENR_USART6LPEN_Msk

+#define RCC_APB2LPENR_SPI1LPEN_Pos             (12U)

+#define RCC_APB2LPENR_SPI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */

+#define RCC_APB2LPENR_SPI1LPEN                 RCC_APB2LPENR_SPI1LPEN_Msk

+#define RCC_APB2LPENR_SPI4LPEN_Pos             (13U)

+#define RCC_APB2LPENR_SPI4LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */

+#define RCC_APB2LPENR_SPI4LPEN                 RCC_APB2LPENR_SPI4LPEN_Msk

+#define RCC_APB2LPENR_TIM15LPEN_Pos            (16U)

+#define RCC_APB2LPENR_TIM15LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB2LPENR_TIM15LPEN                RCC_APB2LPENR_TIM15LPEN_Msk

+#define RCC_APB2LPENR_TIM16LPEN_Pos            (17U)

+#define RCC_APB2LPENR_TIM16LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */

+#define RCC_APB2LPENR_TIM16LPEN                RCC_APB2LPENR_TIM16LPEN_Msk

+#define RCC_APB2LPENR_TIM17LPEN_Pos            (18U)

+#define RCC_APB2LPENR_TIM17LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */

+#define RCC_APB2LPENR_TIM17LPEN                RCC_APB2LPENR_TIM17LPEN_Msk

+#define RCC_APB2LPENR_SPI5LPEN_Pos             (20U)

+#define RCC_APB2LPENR_SPI5LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */

+#define RCC_APB2LPENR_SPI5LPEN                 RCC_APB2LPENR_SPI5LPEN_Msk

+#define RCC_APB2LPENR_SAI1LPEN_Pos             (22U)

+#define RCC_APB2LPENR_SAI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */

+#define RCC_APB2LPENR_SAI1LPEN                 RCC_APB2LPENR_SAI1LPEN_Msk

+#define RCC_APB2LPENR_SAI2LPEN_Pos             (23U)

+#define RCC_APB2LPENR_SAI2LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */

+#define RCC_APB2LPENR_SAI2LPEN                 RCC_APB2LPENR_SAI2LPEN_Msk

+#define RCC_APB2LPENR_SAI3LPEN_Pos             (24U)

+#define RCC_APB2LPENR_SAI3LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI3LPEN_Pos) /*!< 0x01000000 */

+#define RCC_APB2LPENR_SAI3LPEN                 RCC_APB2LPENR_SAI3LPEN_Msk

+#define RCC_APB2LPENR_DFSDM1LPEN_Pos           (28U)

+#define RCC_APB2LPENR_DFSDM1LPEN_Msk           (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x10000000 */

+#define RCC_APB2LPENR_DFSDM1LPEN               RCC_APB2LPENR_DFSDM1LPEN_Msk

+#define RCC_APB2LPENR_HRTIMLPEN_Pos            (29U)

+#define RCC_APB2LPENR_HRTIMLPEN_Msk            (0x1UL << RCC_APB2LPENR_HRTIMLPEN_Pos) /*!< 0x20000000 */

+#define RCC_APB2LPENR_HRTIMLPEN                RCC_APB2LPENR_HRTIMLPEN_Msk

+

+/********************  Bit definition for RCC_APB4LPENR register  ******************/

+#define RCC_APB4LPENR_SYSCFGLPEN_Pos           (1U)

+#define RCC_APB4LPENR_SYSCFGLPEN_Msk           (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB4LPENR_SYSCFGLPEN               RCC_APB4LPENR_SYSCFGLPEN_Msk

+#define RCC_APB4LPENR_LPUART1LPEN_Pos          (3U)

+#define RCC_APB4LPENR_LPUART1LPEN_Msk          (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB4LPENR_LPUART1LPEN              RCC_APB4LPENR_LPUART1LPEN_Msk

+#define RCC_APB4LPENR_SPI6LPEN_Pos             (5U)

+#define RCC_APB4LPENR_SPI6LPEN_Msk             (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB4LPENR_SPI6LPEN                 RCC_APB4LPENR_SPI6LPEN_Msk

+#define RCC_APB4LPENR_I2C4LPEN_Pos             (7U)

+#define RCC_APB4LPENR_I2C4LPEN_Msk             (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB4LPENR_I2C4LPEN                 RCC_APB4LPENR_I2C4LPEN_Msk

+#define RCC_APB4LPENR_LPTIM2LPEN_Pos           (9U)

+#define RCC_APB4LPENR_LPTIM2LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */

+#define RCC_APB4LPENR_LPTIM2LPEN               RCC_APB4LPENR_LPTIM2LPEN_Msk

+#define RCC_APB4LPENR_LPTIM3LPEN_Pos           (10U)

+#define RCC_APB4LPENR_LPTIM3LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */

+#define RCC_APB4LPENR_LPTIM3LPEN               RCC_APB4LPENR_LPTIM3LPEN_Msk

+#define RCC_APB4LPENR_LPTIM4LPEN_Pos           (11U)

+#define RCC_APB4LPENR_LPTIM4LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) /*!< 0x00000800 */

+#define RCC_APB4LPENR_LPTIM4LPEN               RCC_APB4LPENR_LPTIM4LPEN_Msk

+#define RCC_APB4LPENR_LPTIM5LPEN_Pos           (12U)

+#define RCC_APB4LPENR_LPTIM5LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) /*!< 0x00001000 */

+#define RCC_APB4LPENR_LPTIM5LPEN               RCC_APB4LPENR_LPTIM5LPEN_Msk

+#define RCC_APB4LPENR_COMP12LPEN_Pos           (14U)

+#define RCC_APB4LPENR_COMP12LPEN_Msk           (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */

+#define RCC_APB4LPENR_COMP12LPEN               RCC_APB4LPENR_COMP12LPEN_Msk

+#define RCC_APB4LPENR_VREFLPEN_Pos             (15U)

+#define RCC_APB4LPENR_VREFLPEN_Msk             (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */

+#define RCC_APB4LPENR_VREFLPEN                 RCC_APB4LPENR_VREFLPEN_Msk

+#define RCC_APB4LPENR_RTCAPBLPEN_Pos           (16U)

+#define RCC_APB4LPENR_RTCAPBLPEN_Msk           (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB4LPENR_RTCAPBLPEN               RCC_APB4LPENR_RTCAPBLPEN_Msk

+#define RCC_APB4LPENR_SAI4LPEN_Pos             (21U)

+#define RCC_APB4LPENR_SAI4LPEN_Msk             (0x1UL << RCC_APB4LPENR_SAI4LPEN_Pos) /*!< 0x00200000 */

+#define RCC_APB4LPENR_SAI4LPEN                 RCC_APB4LPENR_SAI4LPEN_Msk

+

+

+/********************  Bit definition for RCC_RSR register  *******************/

+#define RCC_RSR_RMVF_Pos                       (16U)

+#define RCC_RSR_RMVF_Msk                       (0x1UL << RCC_RSR_RMVF_Pos)     /*!< 0x00010000 */

+#define RCC_RSR_RMVF                           RCC_RSR_RMVF_Msk

+#define RCC_RSR_CPURSTF_Pos                    (17U)

+#define RCC_RSR_CPURSTF_Msk                    (0x1UL << RCC_RSR_CPURSTF_Pos)  /*!< 0x00020000 */

+#define RCC_RSR_CPURSTF                        RCC_RSR_CPURSTF_Msk

+#define RCC_RSR_D1RSTF_Pos                     (19U)

+#define RCC_RSR_D1RSTF_Msk                     (0x1UL << RCC_RSR_D1RSTF_Pos)   /*!< 0x00080000 */

+#define RCC_RSR_D1RSTF                         RCC_RSR_D1RSTF_Msk

+#define RCC_RSR_D2RSTF_Pos                     (20U)

+#define RCC_RSR_D2RSTF_Msk                     (0x1UL << RCC_RSR_D2RSTF_Pos)   /*!< 0x00100000 */

+#define RCC_RSR_D2RSTF                         RCC_RSR_D2RSTF_Msk

+#define RCC_RSR_BORRSTF_Pos                    (21U)

+#define RCC_RSR_BORRSTF_Msk                    (0x1UL << RCC_RSR_BORRSTF_Pos)  /*!< 0x00200000 */

+#define RCC_RSR_BORRSTF                        RCC_RSR_BORRSTF_Msk

+#define RCC_RSR_PINRSTF_Pos                    (22U)

+#define RCC_RSR_PINRSTF_Msk                    (0x1UL << RCC_RSR_PINRSTF_Pos)  /*!< 0x00400000 */

+#define RCC_RSR_PINRSTF                        RCC_RSR_PINRSTF_Msk

+#define RCC_RSR_PORRSTF_Pos                    (23U)

+#define RCC_RSR_PORRSTF_Msk                    (0x1UL << RCC_RSR_PORRSTF_Pos)  /*!< 0x00800000 */

+#define RCC_RSR_PORRSTF                        RCC_RSR_PORRSTF_Msk

+#define RCC_RSR_SFTRSTF_Pos                    (24U)

+#define RCC_RSR_SFTRSTF_Msk                    (0x1UL << RCC_RSR_SFTRSTF_Pos)  /*!< 0x01000000 */

+#define RCC_RSR_SFTRSTF                        RCC_RSR_SFTRSTF_Msk

+#define RCC_RSR_IWDG1RSTF_Pos                  (26U)

+#define RCC_RSR_IWDG1RSTF_Msk                  (0x1UL << RCC_RSR_IWDG1RSTF_Pos) /*!< 0x04000000 */

+#define RCC_RSR_IWDG1RSTF                      RCC_RSR_IWDG1RSTF_Msk

+#define RCC_RSR_WWDG1RSTF_Pos                  (28U)

+#define RCC_RSR_WWDG1RSTF_Msk                  (0x1UL << RCC_RSR_WWDG1RSTF_Pos) /*!< 0x10000000 */

+#define RCC_RSR_WWDG1RSTF                      RCC_RSR_WWDG1RSTF_Msk

+

+#define RCC_RSR_LPWRRSTF_Pos                   (30U)

+#define RCC_RSR_LPWRRSTF_Msk                   (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */

+#define RCC_RSR_LPWRRSTF                       RCC_RSR_LPWRRSTF_Msk

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    RNG                                     */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for RNG_CR register  *******************/

+#define RNG_CR_RNGEN_Pos    (2U)

+#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */

+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk

+#define RNG_CR_IE_Pos       (3U)

+#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */

+#define RNG_CR_IE           RNG_CR_IE_Msk

+#define RNG_CR_CED_Pos      (5U)

+#define RNG_CR_CED_Msk      (0x1UL << RNG_CR_CED_Pos)                          /*!< 0x00000020 */

+#define RNG_CR_CED          RNG_CR_CED_Msk

+

+/********************  Bits definition for RNG_SR register  *******************/

+#define RNG_SR_DRDY_Pos     (0U)

+#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */

+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk

+#define RNG_SR_CECS_Pos     (1U)

+#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */

+#define RNG_SR_CECS         RNG_SR_CECS_Msk

+#define RNG_SR_SECS_Pos     (2U)

+#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */

+#define RNG_SR_SECS         RNG_SR_SECS_Msk

+#define RNG_SR_CEIS_Pos     (5U)

+#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */

+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk

+#define RNG_SR_SEIS_Pos     (6U)

+#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */

+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                           Real-Time Clock (RTC)                            */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for RTC_TR register  *******************/

+#define RTC_TR_PM_Pos                  (22U)

+#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */

+#define RTC_TR_PM                      RTC_TR_PM_Msk

+#define RTC_TR_HT_Pos                  (20U)

+#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */

+#define RTC_TR_HT                      RTC_TR_HT_Msk

+#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */

+#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */

+#define RTC_TR_HU_Pos                  (16U)

+#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */

+#define RTC_TR_HU                      RTC_TR_HU_Msk

+#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */

+#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */

+#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */

+#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */

+#define RTC_TR_MNT_Pos                 (12U)

+#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */

+#define RTC_TR_MNT                     RTC_TR_MNT_Msk

+#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */

+#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */

+#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */

+#define RTC_TR_MNU_Pos                 (8U)

+#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */

+#define RTC_TR_MNU                     RTC_TR_MNU_Msk

+#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */

+#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */

+#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */

+#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */

+#define RTC_TR_ST_Pos                  (4U)

+#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */

+#define RTC_TR_ST                      RTC_TR_ST_Msk

+#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */

+#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */

+#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */

+#define RTC_TR_SU_Pos                  (0U)

+#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */

+#define RTC_TR_SU                      RTC_TR_SU_Msk

+#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */

+#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */

+#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */

+#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_DR register  *******************/

+#define RTC_DR_YT_Pos                  (20U)

+#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */

+#define RTC_DR_YT                      RTC_DR_YT_Msk

+#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */

+#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */

+#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */

+#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */

+#define RTC_DR_YU_Pos                  (16U)

+#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */

+#define RTC_DR_YU                      RTC_DR_YU_Msk

+#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */

+#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */

+#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */

+#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */

+#define RTC_DR_WDU_Pos                 (13U)

+#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */

+#define RTC_DR_WDU                     RTC_DR_WDU_Msk

+#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */

+#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */

+#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */

+#define RTC_DR_MT_Pos                  (12U)

+#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */

+#define RTC_DR_MT                      RTC_DR_MT_Msk

+#define RTC_DR_MU_Pos                  (8U)

+#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */

+#define RTC_DR_MU                      RTC_DR_MU_Msk

+#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */

+#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */

+#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */

+#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */

+#define RTC_DR_DT_Pos                  (4U)

+#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */

+#define RTC_DR_DT                      RTC_DR_DT_Msk

+#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */

+#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */

+#define RTC_DR_DU_Pos                  (0U)

+#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */

+#define RTC_DR_DU                      RTC_DR_DU_Msk

+#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */

+#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */

+#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */

+#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_CR register  *******************/

+#define RTC_CR_ITSE_Pos                (24U)

+#define RTC_CR_ITSE_Msk                (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */

+#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk

+#define RTC_CR_COE_Pos                 (23U)

+#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */

+#define RTC_CR_COE                     RTC_CR_COE_Msk

+#define RTC_CR_OSEL_Pos                (21U)

+#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */

+#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk

+#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */

+#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */

+#define RTC_CR_POL_Pos                 (20U)

+#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */

+#define RTC_CR_POL                     RTC_CR_POL_Msk

+#define RTC_CR_COSEL_Pos               (19U)

+#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */

+#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk

+#define RTC_CR_BKP_Pos                 (18U)

+#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */

+#define RTC_CR_BKP                     RTC_CR_BKP_Msk

+#define RTC_CR_SUB1H_Pos               (17U)

+#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */

+#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk

+#define RTC_CR_ADD1H_Pos               (16U)

+#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */

+#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk

+#define RTC_CR_TSIE_Pos                (15U)

+#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */

+#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk

+#define RTC_CR_WUTIE_Pos               (14U)

+#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */

+#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk

+#define RTC_CR_ALRBIE_Pos              (13U)

+#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */

+#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk

+#define RTC_CR_ALRAIE_Pos              (12U)

+#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */

+#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk

+#define RTC_CR_TSE_Pos                 (11U)

+#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */

+#define RTC_CR_TSE                     RTC_CR_TSE_Msk

+#define RTC_CR_WUTE_Pos                (10U)

+#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */

+#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk

+#define RTC_CR_ALRBE_Pos               (9U)

+#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */

+#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk

+#define RTC_CR_ALRAE_Pos               (8U)

+#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */

+#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk

+#define RTC_CR_FMT_Pos                 (6U)

+#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */

+#define RTC_CR_FMT                     RTC_CR_FMT_Msk

+#define RTC_CR_BYPSHAD_Pos             (5U)

+#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */

+#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk

+#define RTC_CR_REFCKON_Pos             (4U)

+#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */

+#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk

+#define RTC_CR_TSEDGE_Pos              (3U)

+#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */

+#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk

+#define RTC_CR_WUCKSEL_Pos             (0U)

+#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */

+#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk

+#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */

+#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */

+#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */

+

+/********************  Bits definition for RTC_ISR register  ******************/

+#define RTC_ISR_ITSF_Pos               (17U)

+#define RTC_ISR_ITSF_Msk               (0x1UL << RTC_ISR_ITSF_Pos)             /*!< 0x00020000 */

+#define RTC_ISR_ITSF                   RTC_ISR_ITSF_Msk

+#define RTC_ISR_RECALPF_Pos            (16U)

+#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)          /*!< 0x00010000 */

+#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk

+#define RTC_ISR_TAMP3F_Pos             (15U)

+#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)           /*!< 0x00008000 */

+#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk

+#define RTC_ISR_TAMP2F_Pos             (14U)

+#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)           /*!< 0x00004000 */

+#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk

+#define RTC_ISR_TAMP1F_Pos             (13U)

+#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)           /*!< 0x00002000 */

+#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk

+#define RTC_ISR_TSOVF_Pos              (12U)

+#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)            /*!< 0x00001000 */

+#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk

+#define RTC_ISR_TSF_Pos                (11U)

+#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)              /*!< 0x00000800 */

+#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk

+#define RTC_ISR_WUTF_Pos               (10U)

+#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)             /*!< 0x00000400 */

+#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk

+#define RTC_ISR_ALRBF_Pos              (9U)

+#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)            /*!< 0x00000200 */

+#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk

+#define RTC_ISR_ALRAF_Pos              (8U)

+#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)            /*!< 0x00000100 */

+#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk

+#define RTC_ISR_INIT_Pos               (7U)

+#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)             /*!< 0x00000080 */

+#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk

+#define RTC_ISR_INITF_Pos              (6U)

+#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)            /*!< 0x00000040 */

+#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk

+#define RTC_ISR_RSF_Pos                (5U)

+#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)              /*!< 0x00000020 */

+#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk

+#define RTC_ISR_INITS_Pos              (4U)

+#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)            /*!< 0x00000010 */

+#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk

+#define RTC_ISR_SHPF_Pos               (3U)

+#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)             /*!< 0x00000008 */

+#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk

+#define RTC_ISR_WUTWF_Pos              (2U)

+#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)            /*!< 0x00000004 */

+#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk

+#define RTC_ISR_ALRBWF_Pos             (1U)

+#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)           /*!< 0x00000002 */

+#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk

+#define RTC_ISR_ALRAWF_Pos             (0U)

+#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)           /*!< 0x00000001 */

+#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk

+

+/********************  Bits definition for RTC_PRER register  *****************/

+#define RTC_PRER_PREDIV_A_Pos          (16U)

+#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */

+#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk

+#define RTC_PRER_PREDIV_S_Pos          (0U)

+#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */

+#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk

+

+/********************  Bits definition for RTC_WUTR register  *****************/

+#define RTC_WUTR_WUT_Pos               (0U)

+#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */

+#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk

+

+/********************  Bits definition for RTC_ALRMAR register  ***************/

+#define RTC_ALRMAR_MSK4_Pos            (31U)

+#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */

+#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk

+#define RTC_ALRMAR_WDSEL_Pos           (30U)

+#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */

+#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk

+#define RTC_ALRMAR_DT_Pos              (28U)

+#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */

+#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk

+#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */

+#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */

+#define RTC_ALRMAR_DU_Pos              (24U)

+#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */

+#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk

+#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */

+#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */

+#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */

+#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */

+#define RTC_ALRMAR_MSK3_Pos            (23U)

+#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */

+#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk

+#define RTC_ALRMAR_PM_Pos              (22U)

+#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */

+#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk

+#define RTC_ALRMAR_HT_Pos              (20U)

+#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */

+#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk

+#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */

+#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */

+#define RTC_ALRMAR_HU_Pos              (16U)

+#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */

+#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk

+#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */

+#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */

+#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */

+#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */

+#define RTC_ALRMAR_MSK2_Pos            (15U)

+#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */

+#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk

+#define RTC_ALRMAR_MNT_Pos             (12U)

+#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */

+#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk

+#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */

+#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */

+#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */

+#define RTC_ALRMAR_MNU_Pos             (8U)

+#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */

+#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk

+#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */

+#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */

+#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */

+#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */

+#define RTC_ALRMAR_MSK1_Pos            (7U)

+#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */

+#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk

+#define RTC_ALRMAR_ST_Pos              (4U)

+#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */

+#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk

+#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */

+#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */

+#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */

+#define RTC_ALRMAR_SU_Pos              (0U)

+#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */

+#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk

+#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */

+#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */

+#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */

+#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_ALRMBR register  ***************/

+#define RTC_ALRMBR_MSK4_Pos            (31U)

+#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */

+#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk

+#define RTC_ALRMBR_WDSEL_Pos           (30U)

+#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */

+#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk

+#define RTC_ALRMBR_DT_Pos              (28U)

+#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */

+#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk

+#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */

+#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */

+#define RTC_ALRMBR_DU_Pos              (24U)

+#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */

+#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk

+#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */

+#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */

+#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */

+#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */

+#define RTC_ALRMBR_MSK3_Pos            (23U)

+#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */

+#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk

+#define RTC_ALRMBR_PM_Pos              (22U)

+#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */

+#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk

+#define RTC_ALRMBR_HT_Pos              (20U)

+#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */

+#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk

+#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */

+#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */

+#define RTC_ALRMBR_HU_Pos              (16U)

+#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */

+#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk

+#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */

+#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */

+#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */

+#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */

+#define RTC_ALRMBR_MSK2_Pos            (15U)

+#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */

+#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk

+#define RTC_ALRMBR_MNT_Pos             (12U)

+#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */

+#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk

+#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */

+#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */

+#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */

+#define RTC_ALRMBR_MNU_Pos             (8U)

+#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */

+#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk

+#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */

+#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */

+#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */

+#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */

+#define RTC_ALRMBR_MSK1_Pos            (7U)

+#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */

+#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk

+#define RTC_ALRMBR_ST_Pos              (4U)

+#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */

+#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk

+#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */

+#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */

+#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */

+#define RTC_ALRMBR_SU_Pos              (0U)

+#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */

+#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk

+#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */

+#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */

+#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */

+#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_WPR register  ******************/

+#define RTC_WPR_KEY_Pos                (0U)

+#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */

+#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk

+

+/********************  Bits definition for RTC_SSR register  ******************/

+#define RTC_SSR_SS_Pos                 (0U)

+#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)            /*!< 0x0000FFFF */

+#define RTC_SSR_SS                     RTC_SSR_SS_Msk

+

+/********************  Bits definition for RTC_SHIFTR register  ***************/

+#define RTC_SHIFTR_SUBFS_Pos           (0U)

+#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */

+#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk

+#define RTC_SHIFTR_ADD1S_Pos           (31U)

+#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */

+#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk

+

+/********************  Bits definition for RTC_TSTR register  *****************/

+#define RTC_TSTR_PM_Pos                (22U)

+#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */

+#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk

+#define RTC_TSTR_HT_Pos                (20U)

+#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */

+#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk

+#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */

+#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */

+#define RTC_TSTR_HU_Pos                (16U)

+#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */

+#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk

+#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */

+#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */

+#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */

+#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */

+#define RTC_TSTR_MNT_Pos               (12U)

+#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */

+#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk

+#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */

+#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */

+#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */

+#define RTC_TSTR_MNU_Pos               (8U)

+#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */

+#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk

+#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */

+#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */

+#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */

+#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */

+#define RTC_TSTR_ST_Pos                (4U)

+#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */

+#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk

+#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */

+#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */

+#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */

+#define RTC_TSTR_SU_Pos                (0U)

+#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */

+#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk

+#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */

+#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */

+#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */

+#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_TSDR register  *****************/

+#define RTC_TSDR_WDU_Pos               (13U)

+#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */

+#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk

+#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */

+#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */

+#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */

+#define RTC_TSDR_MT_Pos                (12U)

+#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */

+#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk

+#define RTC_TSDR_MU_Pos                (8U)

+#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */

+#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk

+#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */

+#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */

+#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */

+#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */

+#define RTC_TSDR_DT_Pos                (4U)

+#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */

+#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk

+#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */

+#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */

+#define RTC_TSDR_DU_Pos                (0U)

+#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */

+#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk

+#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */

+#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */

+#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */

+#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_TSSSR register  ****************/

+#define RTC_TSSSR_SS_Pos               (0U)

+#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)          /*!< 0x0000FFFF */

+#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk

+

+/********************  Bits definition for RTC_CALR register  *****************/

+#define RTC_CALR_CALP_Pos              (15U)

+#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */

+#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk

+#define RTC_CALR_CALW8_Pos             (14U)

+#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */

+#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk

+#define RTC_CALR_CALW16_Pos            (13U)

+#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */

+#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk

+#define RTC_CALR_CALM_Pos              (0U)

+#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */

+#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk

+#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */

+#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */

+#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */

+#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */

+#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */

+#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */

+#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */

+#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */

+#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */

+

+/********************  Bits definition for RTC_TAMPCR register  ***************/

+#define RTC_TAMPCR_TAMP3MF_Pos         (24U)

+#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)       /*!< 0x01000000 */

+#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk

+#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)

+#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)  /*!< 0x00800000 */

+#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk

+#define RTC_TAMPCR_TAMP3IE_Pos         (22U)

+#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)       /*!< 0x00400000 */

+#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk

+#define RTC_TAMPCR_TAMP2MF_Pos         (21U)

+#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)       /*!< 0x00200000 */

+#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk

+#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)

+#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)  /*!< 0x00100000 */

+#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk

+#define RTC_TAMPCR_TAMP2IE_Pos         (19U)

+#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)       /*!< 0x00080000 */

+#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk

+#define RTC_TAMPCR_TAMP1MF_Pos         (18U)

+#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)       /*!< 0x00040000 */

+#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk

+#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)

+#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)  /*!< 0x00020000 */

+#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk

+#define RTC_TAMPCR_TAMP1IE_Pos         (16U)

+#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)       /*!< 0x00010000 */

+#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk

+#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)

+#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)     /*!< 0x00008000 */

+#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk

+#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)

+#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)      /*!< 0x00006000 */

+#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk

+#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */

+#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */

+#define RTC_TAMPCR_TAMPFLT_Pos         (11U)

+#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)       /*!< 0x00001800 */

+#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk

+#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */

+#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */

+#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)

+#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)      /*!< 0x00000700 */

+#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk

+#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */

+#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */

+#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */

+#define RTC_TAMPCR_TAMPTS_Pos          (7U)

+#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)        /*!< 0x00000080 */

+#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk

+#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)

+#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)      /*!< 0x00000040 */

+#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk

+#define RTC_TAMPCR_TAMP3E_Pos          (5U)

+#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)        /*!< 0x00000020 */

+#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk

+#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)

+#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)      /*!< 0x00000010 */

+#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk

+#define RTC_TAMPCR_TAMP2E_Pos          (3U)

+#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)        /*!< 0x00000008 */

+#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk

+#define RTC_TAMPCR_TAMPIE_Pos          (2U)

+#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)        /*!< 0x00000004 */

+#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk

+#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)

+#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)      /*!< 0x00000002 */

+#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk

+#define RTC_TAMPCR_TAMP1E_Pos          (0U)

+#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)        /*!< 0x00000001 */

+#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk

+

+/********************  Bits definition for RTC_ALRMASSR register  *************/

+#define RTC_ALRMASSR_MASKSS_Pos        (24U)

+#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x0F000000 */

+#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk

+#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */

+#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */

+#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */

+#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */

+#define RTC_ALRMASSR_SS_Pos            (0U)

+#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */

+#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk

+

+/********************  Bits definition for RTC_ALRMBSSR register  *************/

+#define RTC_ALRMBSSR_MASKSS_Pos        (24U)

+#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x0F000000 */

+#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk

+#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */

+#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */

+#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */

+#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */

+#define RTC_ALRMBSSR_SS_Pos            (0U)

+#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */

+#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk

+

+/********************  Bits definition for RTC_OR register  *******************/

+#define RTC_OR_OUT_RMP_Pos             (1U)

+#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)           /*!< 0x00000002 */

+#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk

+#define RTC_OR_ALARMOUTTYPE_Pos        (0U)

+#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)      /*!< 0x00000001 */

+#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk

+

+/********************  Bits definition for RTC_BKP0R register  ****************/

+#define RTC_BKP0R_Pos                  (0U)

+#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP0R                      RTC_BKP0R_Msk

+

+/********************  Bits definition for RTC_BKP1R register  ****************/

+#define RTC_BKP1R_Pos                  (0U)

+#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP1R                      RTC_BKP1R_Msk

+

+/********************  Bits definition for RTC_BKP2R register  ****************/

+#define RTC_BKP2R_Pos                  (0U)

+#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP2R                      RTC_BKP2R_Msk

+

+/********************  Bits definition for RTC_BKP3R register  ****************/

+#define RTC_BKP3R_Pos                  (0U)

+#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP3R                      RTC_BKP3R_Msk

+

+/********************  Bits definition for RTC_BKP4R register  ****************/

+#define RTC_BKP4R_Pos                  (0U)

+#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP4R                      RTC_BKP4R_Msk

+

+/********************  Bits definition for RTC_BKP5R register  ****************/

+#define RTC_BKP5R_Pos                  (0U)

+#define RTC_BKP5R_Msk                  (0xFFFFFFFFUL << RTC_BKP5R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP5R                      RTC_BKP5R_Msk

+

+/********************  Bits definition for RTC_BKP6R register  ****************/

+#define RTC_BKP6R_Pos                  (0U)

+#define RTC_BKP6R_Msk                  (0xFFFFFFFFUL << RTC_BKP6R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP6R                      RTC_BKP6R_Msk

+

+/********************  Bits definition for RTC_BKP7R register  ****************/

+#define RTC_BKP7R_Pos                  (0U)

+#define RTC_BKP7R_Msk                  (0xFFFFFFFFUL << RTC_BKP7R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP7R                      RTC_BKP7R_Msk

+

+/********************  Bits definition for RTC_BKP8R register  ****************/

+#define RTC_BKP8R_Pos                  (0U)

+#define RTC_BKP8R_Msk                  (0xFFFFFFFFUL << RTC_BKP8R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP8R                      RTC_BKP8R_Msk

+

+/********************  Bits definition for RTC_BKP9R register  ****************/

+#define RTC_BKP9R_Pos                  (0U)

+#define RTC_BKP9R_Msk                  (0xFFFFFFFFUL << RTC_BKP9R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP9R                      RTC_BKP9R_Msk

+

+/********************  Bits definition for RTC_BKP10R register  ***************/

+#define RTC_BKP10R_Pos                 (0U)

+#define RTC_BKP10R_Msk                 (0xFFFFFFFFUL << RTC_BKP10R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP10R                     RTC_BKP10R_Msk

+

+/********************  Bits definition for RTC_BKP11R register  ***************/

+#define RTC_BKP11R_Pos                 (0U)

+#define RTC_BKP11R_Msk                 (0xFFFFFFFFUL << RTC_BKP11R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP11R                     RTC_BKP11R_Msk

+

+/********************  Bits definition for RTC_BKP12R register  ***************/

+#define RTC_BKP12R_Pos                 (0U)

+#define RTC_BKP12R_Msk                 (0xFFFFFFFFUL << RTC_BKP12R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP12R                     RTC_BKP12R_Msk

+

+/********************  Bits definition for RTC_BKP13R register  ***************/

+#define RTC_BKP13R_Pos                 (0U)

+#define RTC_BKP13R_Msk                 (0xFFFFFFFFUL << RTC_BKP13R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP13R                     RTC_BKP13R_Msk

+

+/********************  Bits definition for RTC_BKP14R register  ***************/

+#define RTC_BKP14R_Pos                 (0U)

+#define RTC_BKP14R_Msk                 (0xFFFFFFFFUL << RTC_BKP14R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP14R                     RTC_BKP14R_Msk

+

+/********************  Bits definition for RTC_BKP15R register  ***************/

+#define RTC_BKP15R_Pos                 (0U)

+#define RTC_BKP15R_Msk                 (0xFFFFFFFFUL << RTC_BKP15R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP15R                     RTC_BKP15R_Msk

+

+/********************  Bits definition for RTC_BKP16R register  ***************/

+#define RTC_BKP16R_Pos                 (0U)

+#define RTC_BKP16R_Msk                 (0xFFFFFFFFUL << RTC_BKP16R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP16R                     RTC_BKP16R_Msk

+

+/********************  Bits definition for RTC_BKP17R register  ***************/

+#define RTC_BKP17R_Pos                 (0U)

+#define RTC_BKP17R_Msk                 (0xFFFFFFFFUL << RTC_BKP17R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP17R                     RTC_BKP17R_Msk

+

+/********************  Bits definition for RTC_BKP18R register  ***************/

+#define RTC_BKP18R_Pos                 (0U)

+#define RTC_BKP18R_Msk                 (0xFFFFFFFFUL << RTC_BKP18R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP18R                     RTC_BKP18R_Msk

+

+/********************  Bits definition for RTC_BKP19R register  ***************/

+#define RTC_BKP19R_Pos                 (0U)

+#define RTC_BKP19R_Msk                 (0xFFFFFFFFUL << RTC_BKP19R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP19R                     RTC_BKP19R_Msk

+

+/********************  Bits definition for RTC_BKP20R register  ***************/

+#define RTC_BKP20R_Pos                 (0U)

+#define RTC_BKP20R_Msk                 (0xFFFFFFFFUL << RTC_BKP20R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP20R                     RTC_BKP20R_Msk

+

+/********************  Bits definition for RTC_BKP21R register  ***************/

+#define RTC_BKP21R_Pos                 (0U)

+#define RTC_BKP21R_Msk                 (0xFFFFFFFFUL << RTC_BKP21R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP21R                     RTC_BKP21R_Msk

+

+/********************  Bits definition for RTC_BKP22R register  ***************/

+#define RTC_BKP22R_Pos                 (0U)

+#define RTC_BKP22R_Msk                 (0xFFFFFFFFUL << RTC_BKP22R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP22R                     RTC_BKP22R_Msk

+

+/********************  Bits definition for RTC_BKP23R register  ***************/

+#define RTC_BKP23R_Pos                 (0U)

+#define RTC_BKP23R_Msk                 (0xFFFFFFFFUL << RTC_BKP23R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP23R                     RTC_BKP23R_Msk

+

+/********************  Bits definition for RTC_BKP24R register  ***************/

+#define RTC_BKP24R_Pos                 (0U)

+#define RTC_BKP24R_Msk                 (0xFFFFFFFFUL << RTC_BKP24R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP24R                     RTC_BKP24R_Msk

+

+/********************  Bits definition for RTC_BKP25R register  ***************/

+#define RTC_BKP25R_Pos                 (0U)

+#define RTC_BKP25R_Msk                 (0xFFFFFFFFUL << RTC_BKP25R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP25R                     RTC_BKP25R_Msk

+

+/********************  Bits definition for RTC_BKP26R register  ***************/

+#define RTC_BKP26R_Pos                 (0U)

+#define RTC_BKP26R_Msk                 (0xFFFFFFFFUL << RTC_BKP26R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP26R                     RTC_BKP26R_Msk

+

+/********************  Bits definition for RTC_BKP27R register  ***************/

+#define RTC_BKP27R_Pos                 (0U)

+#define RTC_BKP27R_Msk                 (0xFFFFFFFFUL << RTC_BKP27R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP27R                     RTC_BKP27R_Msk

+

+/********************  Bits definition for RTC_BKP28R register  ***************/

+#define RTC_BKP28R_Pos                 (0U)

+#define RTC_BKP28R_Msk                 (0xFFFFFFFFUL << RTC_BKP28R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP28R                     RTC_BKP28R_Msk

+

+/********************  Bits definition for RTC_BKP29R register  ***************/

+#define RTC_BKP29R_Pos                 (0U)

+#define RTC_BKP29R_Msk                 (0xFFFFFFFFUL << RTC_BKP29R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP29R                     RTC_BKP29R_Msk

+

+/********************  Bits definition for RTC_BKP30R register  ***************/

+#define RTC_BKP30R_Pos                 (0U)

+#define RTC_BKP30R_Msk                 (0xFFFFFFFFUL << RTC_BKP30R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP30R                     RTC_BKP30R_Msk

+

+/********************  Bits definition for RTC_BKP31R register  ***************/

+#define RTC_BKP31R_Pos                 (0U)

+#define RTC_BKP31R_Msk                 (0xFFFFFFFFUL << RTC_BKP31R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP31R                     RTC_BKP31R_Msk

+

+/******************** Number of backup registers ******************************/

+#define RTC_BKP_NUMBER_Pos             (5U)

+#define RTC_BKP_NUMBER_Msk             (0x1UL << RTC_BKP_NUMBER_Pos)           /*!< 0x00000020 */

+#define RTC_BKP_NUMBER                 RTC_BKP_NUMBER_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                              SPDIF-RX Interface                            */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for SPDIF_CR register  ******************/

+#define SPDIFRX_CR_SPDIFEN_Pos      (0U)

+#define SPDIFRX_CR_SPDIFEN_Msk      (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)          /*!< 0x00000003 */

+#define SPDIFRX_CR_SPDIFEN          SPDIFRX_CR_SPDIFEN_Msk                     /*!<Peripheral Block Enable                      */

+#define SPDIFRX_CR_RXDMAEN_Pos      (2U)

+#define SPDIFRX_CR_RXDMAEN_Msk      (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)          /*!< 0x00000004 */

+#define SPDIFRX_CR_RXDMAEN          SPDIFRX_CR_RXDMAEN_Msk                     /*!<Receiver DMA Enable for data flow            */

+#define SPDIFRX_CR_RXSTEO_Pos       (3U)

+#define SPDIFRX_CR_RXSTEO_Msk       (0x1UL << SPDIFRX_CR_RXSTEO_Pos)           /*!< 0x00000008 */

+#define SPDIFRX_CR_RXSTEO           SPDIFRX_CR_RXSTEO_Msk                      /*!<Stereo Mode                                  */

+#define SPDIFRX_CR_DRFMT_Pos        (4U)

+#define SPDIFRX_CR_DRFMT_Msk        (0x3UL << SPDIFRX_CR_DRFMT_Pos)            /*!< 0x00000030 */

+#define SPDIFRX_CR_DRFMT            SPDIFRX_CR_DRFMT_Msk                       /*!<RX Data format                               */

+#define SPDIFRX_CR_PMSK_Pos         (6U)

+#define SPDIFRX_CR_PMSK_Msk         (0x1UL << SPDIFRX_CR_PMSK_Pos)             /*!< 0x00000040 */

+#define SPDIFRX_CR_PMSK             SPDIFRX_CR_PMSK_Msk                        /*!<Mask Parity error bit                        */

+#define SPDIFRX_CR_VMSK_Pos         (7U)

+#define SPDIFRX_CR_VMSK_Msk         (0x1UL << SPDIFRX_CR_VMSK_Pos)             /*!< 0x00000080 */

+#define SPDIFRX_CR_VMSK             SPDIFRX_CR_VMSK_Msk                        /*!<Mask of Validity bit                         */

+#define SPDIFRX_CR_CUMSK_Pos        (8U)

+#define SPDIFRX_CR_CUMSK_Msk        (0x1UL << SPDIFRX_CR_CUMSK_Pos)            /*!< 0x00000100 */

+#define SPDIFRX_CR_CUMSK            SPDIFRX_CR_CUMSK_Msk                       /*!<Mask of channel status and user bits         */

+#define SPDIFRX_CR_PTMSK_Pos        (9U)

+#define SPDIFRX_CR_PTMSK_Msk        (0x1UL << SPDIFRX_CR_PTMSK_Pos)            /*!< 0x00000200 */

+#define SPDIFRX_CR_PTMSK            SPDIFRX_CR_PTMSK_Msk                       /*!<Mask of Preamble Type bits                   */

+#define SPDIFRX_CR_CBDMAEN_Pos      (10U)

+#define SPDIFRX_CR_CBDMAEN_Msk      (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)          /*!< 0x00000400 */

+#define SPDIFRX_CR_CBDMAEN          SPDIFRX_CR_CBDMAEN_Msk                     /*!<Control Buffer DMA ENable for control flow   */

+#define SPDIFRX_CR_CHSEL_Pos        (11U)

+#define SPDIFRX_CR_CHSEL_Msk        (0x1UL << SPDIFRX_CR_CHSEL_Pos)            /*!< 0x00000800 */

+#define SPDIFRX_CR_CHSEL            SPDIFRX_CR_CHSEL_Msk                       /*!<Channel Selection                            */

+#define SPDIFRX_CR_NBTR_Pos         (12U)

+#define SPDIFRX_CR_NBTR_Msk         (0x3UL << SPDIFRX_CR_NBTR_Pos)             /*!< 0x00003000 */

+#define SPDIFRX_CR_NBTR             SPDIFRX_CR_NBTR_Msk                        /*!<Maximum allowed re-tries during synchronization phase */

+#define SPDIFRX_CR_WFA_Pos          (14U)

+#define SPDIFRX_CR_WFA_Msk          (0x1UL << SPDIFRX_CR_WFA_Pos)              /*!< 0x00004000 */

+#define SPDIFRX_CR_WFA              SPDIFRX_CR_WFA_Msk                         /*!<Wait For Activity     */

+#define SPDIFRX_CR_INSEL_Pos        (16U)

+#define SPDIFRX_CR_INSEL_Msk        (0x7UL << SPDIFRX_CR_INSEL_Pos)            /*!< 0x00070000 */

+#define SPDIFRX_CR_INSEL            SPDIFRX_CR_INSEL_Msk                       /*!<SPDIF input selection */

+#define SPDIFRX_CR_CKSEN_Pos        (20U)

+#define SPDIFRX_CR_CKSEN_Msk        (0x1UL << SPDIFRX_CR_CKSEN_Pos)            /*!< 0x00100000 */

+#define SPDIFRX_CR_CKSEN            SPDIFRX_CR_CKSEN_Msk                       /*!<Symbol Clock Enable */

+#define SPDIFRX_CR_CKSBKPEN_Pos     (21U)

+#define SPDIFRX_CR_CKSBKPEN_Msk     (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)         /*!< 0x00200000 */

+#define SPDIFRX_CR_CKSBKPEN         SPDIFRX_CR_CKSBKPEN_Msk                    /*!<Backup Symbol Clock Enable */

+

+/*******************  Bit definition for SPDIFRX_IMR register  *******************/

+#define SPDIFRX_IMR_RXNEIE_Pos      (0U)

+#define SPDIFRX_IMR_RXNEIE_Msk      (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)          /*!< 0x00000001 */

+#define SPDIFRX_IMR_RXNEIE          SPDIFRX_IMR_RXNEIE_Msk                     /*!<RXNE interrupt enable                              */

+#define SPDIFRX_IMR_CSRNEIE_Pos     (1U)

+#define SPDIFRX_IMR_CSRNEIE_Msk     (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)         /*!< 0x00000002 */

+#define SPDIFRX_IMR_CSRNEIE         SPDIFRX_IMR_CSRNEIE_Msk                    /*!<Control Buffer Ready Interrupt Enable              */

+#define SPDIFRX_IMR_PERRIE_Pos      (2U)

+#define SPDIFRX_IMR_PERRIE_Msk      (0x1UL << SPDIFRX_IMR_PERRIE_Pos)          /*!< 0x00000004 */

+#define SPDIFRX_IMR_PERRIE          SPDIFRX_IMR_PERRIE_Msk                     /*!<Parity error interrupt enable                      */

+#define SPDIFRX_IMR_OVRIE_Pos       (3U)

+#define SPDIFRX_IMR_OVRIE_Msk       (0x1UL << SPDIFRX_IMR_OVRIE_Pos)           /*!< 0x00000008 */

+#define SPDIFRX_IMR_OVRIE           SPDIFRX_IMR_OVRIE_Msk                      /*!<Overrun error Interrupt Enable                     */

+#define SPDIFRX_IMR_SBLKIE_Pos      (4U)

+#define SPDIFRX_IMR_SBLKIE_Msk      (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)          /*!< 0x00000010 */

+#define SPDIFRX_IMR_SBLKIE          SPDIFRX_IMR_SBLKIE_Msk                     /*!<Synchronization Block Detected Interrupt Enable    */

+#define SPDIFRX_IMR_SYNCDIE_Pos     (5U)

+#define SPDIFRX_IMR_SYNCDIE_Msk     (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)         /*!< 0x00000020 */

+#define SPDIFRX_IMR_SYNCDIE         SPDIFRX_IMR_SYNCDIE_Msk                    /*!<Synchronization Done                               */

+#define SPDIFRX_IMR_IFEIE_Pos       (6U)

+#define SPDIFRX_IMR_IFEIE_Msk       (0x1UL << SPDIFRX_IMR_IFEIE_Pos)           /*!< 0x00000040 */

+#define SPDIFRX_IMR_IFEIE           SPDIFRX_IMR_IFEIE_Msk                      /*!<Serial Interface Error Interrupt Enable            */

+

+/*******************  Bit definition for SPDIFRX_SR register  *******************/

+#define SPDIFRX_SR_RXNE_Pos         (0U)

+#define SPDIFRX_SR_RXNE_Msk         (0x1UL << SPDIFRX_SR_RXNE_Pos)             /*!< 0x00000001 */

+#define SPDIFRX_SR_RXNE             SPDIFRX_SR_RXNE_Msk                        /*!<Read data register not empty                          */

+#define SPDIFRX_SR_CSRNE_Pos        (1U)

+#define SPDIFRX_SR_CSRNE_Msk        (0x1UL << SPDIFRX_SR_CSRNE_Pos)            /*!< 0x00000002 */

+#define SPDIFRX_SR_CSRNE            SPDIFRX_SR_CSRNE_Msk                       /*!<The Control Buffer register is not empty              */

+#define SPDIFRX_SR_PERR_Pos         (2U)

+#define SPDIFRX_SR_PERR_Msk         (0x1UL << SPDIFRX_SR_PERR_Pos)             /*!< 0x00000004 */

+#define SPDIFRX_SR_PERR             SPDIFRX_SR_PERR_Msk                        /*!<Parity error                                          */

+#define SPDIFRX_SR_OVR_Pos          (3U)

+#define SPDIFRX_SR_OVR_Msk          (0x1UL << SPDIFRX_SR_OVR_Pos)              /*!< 0x00000008 */

+#define SPDIFRX_SR_OVR              SPDIFRX_SR_OVR_Msk                         /*!<Overrun error                                         */

+#define SPDIFRX_SR_SBD_Pos          (4U)

+#define SPDIFRX_SR_SBD_Msk          (0x1UL << SPDIFRX_SR_SBD_Pos)              /*!< 0x00000010 */

+#define SPDIFRX_SR_SBD              SPDIFRX_SR_SBD_Msk                         /*!<Synchronization Block Detected                        */

+#define SPDIFRX_SR_SYNCD_Pos        (5U)

+#define SPDIFRX_SR_SYNCD_Msk        (0x1UL << SPDIFRX_SR_SYNCD_Pos)            /*!< 0x00000020 */

+#define SPDIFRX_SR_SYNCD            SPDIFRX_SR_SYNCD_Msk                       /*!<Synchronization Done                                  */

+#define SPDIFRX_SR_FERR_Pos         (6U)

+#define SPDIFRX_SR_FERR_Msk         (0x1UL << SPDIFRX_SR_FERR_Pos)             /*!< 0x00000040 */

+#define SPDIFRX_SR_FERR             SPDIFRX_SR_FERR_Msk                        /*!<Framing error                                         */

+#define SPDIFRX_SR_SERR_Pos         (7U)

+#define SPDIFRX_SR_SERR_Msk         (0x1UL << SPDIFRX_SR_SERR_Pos)             /*!< 0x00000080 */

+#define SPDIFRX_SR_SERR             SPDIFRX_SR_SERR_Msk                        /*!<Synchronization error                                 */

+#define SPDIFRX_SR_TERR_Pos         (8U)

+#define SPDIFRX_SR_TERR_Msk         (0x1UL << SPDIFRX_SR_TERR_Pos)             /*!< 0x00000100 */

+#define SPDIFRX_SR_TERR             SPDIFRX_SR_TERR_Msk                        /*!<Time-out error                                        */

+#define SPDIFRX_SR_WIDTH5_Pos       (16U)

+#define SPDIFRX_SR_WIDTH5_Msk       (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)        /*!< 0x7FFF0000 */

+#define SPDIFRX_SR_WIDTH5           SPDIFRX_SR_WIDTH5_Msk                      /*!<Duration of 5 symbols counted with spdif_clk          */

+

+/*******************  Bit definition for SPDIFRX_IFCR register  *******************/

+#define SPDIFRX_IFCR_PERRCF_Pos     (2U)

+#define SPDIFRX_IFCR_PERRCF_Msk     (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)         /*!< 0x00000004 */

+#define SPDIFRX_IFCR_PERRCF         SPDIFRX_IFCR_PERRCF_Msk                    /*!<Clears the Parity error flag                         */

+#define SPDIFRX_IFCR_OVRCF_Pos      (3U)

+#define SPDIFRX_IFCR_OVRCF_Msk      (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)          /*!< 0x00000008 */

+#define SPDIFRX_IFCR_OVRCF          SPDIFRX_IFCR_OVRCF_Msk                     /*!<Clears the Overrun error flag                        */

+#define SPDIFRX_IFCR_SBDCF_Pos      (4U)

+#define SPDIFRX_IFCR_SBDCF_Msk      (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)          /*!< 0x00000010 */

+#define SPDIFRX_IFCR_SBDCF          SPDIFRX_IFCR_SBDCF_Msk                     /*!<Clears the Synchronization Block Detected flag       */

+#define SPDIFRX_IFCR_SYNCDCF_Pos    (5U)

+#define SPDIFRX_IFCR_SYNCDCF_Msk    (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)        /*!< 0x00000020 */

+#define SPDIFRX_IFCR_SYNCDCF        SPDIFRX_IFCR_SYNCDCF_Msk                   /*!<Clears the Synchronization Done flag                 */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/

+#define SPDIFRX_DR0_DR_Pos          (0U)

+#define SPDIFRX_DR0_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)         /*!< 0x00FFFFFF */

+#define SPDIFRX_DR0_DR              SPDIFRX_DR0_DR_Msk                         /*!<Data value            */

+#define SPDIFRX_DR0_PE_Pos          (24U)

+#define SPDIFRX_DR0_PE_Msk          (0x1UL << SPDIFRX_DR0_PE_Pos)              /*!< 0x01000000 */

+#define SPDIFRX_DR0_PE              SPDIFRX_DR0_PE_Msk                         /*!<Parity Error bit      */

+#define SPDIFRX_DR0_V_Pos           (25U)

+#define SPDIFRX_DR0_V_Msk           (0x1UL << SPDIFRX_DR0_V_Pos)               /*!< 0x02000000 */

+#define SPDIFRX_DR0_V               SPDIFRX_DR0_V_Msk                          /*!<Validity bit          */

+#define SPDIFRX_DR0_U_Pos           (26U)

+#define SPDIFRX_DR0_U_Msk           (0x1UL << SPDIFRX_DR0_U_Pos)               /*!< 0x04000000 */

+#define SPDIFRX_DR0_U               SPDIFRX_DR0_U_Msk                          /*!<User bit              */

+#define SPDIFRX_DR0_C_Pos           (27U)

+#define SPDIFRX_DR0_C_Msk           (0x1UL << SPDIFRX_DR0_C_Pos)               /*!< 0x08000000 */

+#define SPDIFRX_DR0_C               SPDIFRX_DR0_C_Msk                          /*!<Channel Status bit    */

+#define SPDIFRX_DR0_PT_Pos          (28U)

+#define SPDIFRX_DR0_PT_Msk          (0x3UL << SPDIFRX_DR0_PT_Pos)              /*!< 0x30000000 */

+#define SPDIFRX_DR0_PT              SPDIFRX_DR0_PT_Msk                         /*!<Preamble Type         */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/

+#define SPDIFRX_DR1_DR_Pos          (8U)

+#define SPDIFRX_DR1_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)         /*!< 0xFFFFFF00 */

+#define SPDIFRX_DR1_DR              SPDIFRX_DR1_DR_Msk                         /*!<Data value            */

+#define SPDIFRX_DR1_PT_Pos          (4U)

+#define SPDIFRX_DR1_PT_Msk          (0x3UL << SPDIFRX_DR1_PT_Pos)              /*!< 0x00000030 */

+#define SPDIFRX_DR1_PT              SPDIFRX_DR1_PT_Msk                         /*!<Preamble Type         */

+#define SPDIFRX_DR1_C_Pos           (3U)

+#define SPDIFRX_DR1_C_Msk           (0x1UL << SPDIFRX_DR1_C_Pos)               /*!< 0x00000008 */

+#define SPDIFRX_DR1_C               SPDIFRX_DR1_C_Msk                          /*!<Channel Status bit    */

+#define SPDIFRX_DR1_U_Pos           (2U)

+#define SPDIFRX_DR1_U_Msk           (0x1UL << SPDIFRX_DR1_U_Pos)               /*!< 0x00000004 */

+#define SPDIFRX_DR1_U               SPDIFRX_DR1_U_Msk                          /*!<User bit              */

+#define SPDIFRX_DR1_V_Pos           (1U)

+#define SPDIFRX_DR1_V_Msk           (0x1UL << SPDIFRX_DR1_V_Pos)               /*!< 0x00000002 */

+#define SPDIFRX_DR1_V               SPDIFRX_DR1_V_Msk                          /*!<Validity bit          */

+#define SPDIFRX_DR1_PE_Pos          (0U)

+#define SPDIFRX_DR1_PE_Msk          (0x1UL << SPDIFRX_DR1_PE_Pos)              /*!< 0x00000001 */

+#define SPDIFRX_DR1_PE              SPDIFRX_DR1_PE_Msk                         /*!<Parity Error bit      */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/

+#define SPDIFRX_DR1_DRNL1_Pos       (16U)

+#define SPDIFRX_DR1_DRNL1_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)        /*!< 0xFFFF0000 */

+#define SPDIFRX_DR1_DRNL1           SPDIFRX_DR1_DRNL1_Msk                      /*!<Data value Channel B      */

+#define SPDIFRX_DR1_DRNL2_Pos       (0U)

+#define SPDIFRX_DR1_DRNL2_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)        /*!< 0x0000FFFF */

+#define SPDIFRX_DR1_DRNL2           SPDIFRX_DR1_DRNL2_Msk                      /*!<Data value Channel A      */

+

+/*******************  Bit definition for SPDIFRX_CSR register   *******************/

+#define SPDIFRX_CSR_USR_Pos         (0U)

+#define SPDIFRX_CSR_USR_Msk         (0xFFFFUL << SPDIFRX_CSR_USR_Pos)          /*!< 0x0000FFFF */

+#define SPDIFRX_CSR_USR             SPDIFRX_CSR_USR_Msk                        /*!<User data information           */

+#define SPDIFRX_CSR_CS_Pos          (16U)

+#define SPDIFRX_CSR_CS_Msk          (0xFFUL << SPDIFRX_CSR_CS_Pos)             /*!< 0x00FF0000 */

+#define SPDIFRX_CSR_CS              SPDIFRX_CSR_CS_Msk                         /*!<Channel A status information    */

+#define SPDIFRX_CSR_SOB_Pos         (24U)

+#define SPDIFRX_CSR_SOB_Msk         (0x1UL << SPDIFRX_CSR_SOB_Pos)             /*!< 0x01000000 */

+#define SPDIFRX_CSR_SOB             SPDIFRX_CSR_SOB_Msk                        /*!<Start Of Block                  */

+

+/*******************  Bit definition for SPDIFRX_DIR register    *******************/

+#define SPDIFRX_DIR_THI_Pos         (0U)

+#define SPDIFRX_DIR_THI_Msk         (0x1FFFUL << SPDIFRX_DIR_THI_Pos)          /*!< 0x00001FFF */

+#define SPDIFRX_DIR_THI             SPDIFRX_DIR_THI_Msk                        /*!<Threshold LOW      */

+#define SPDIFRX_DIR_TLO_Pos         (16U)

+#define SPDIFRX_DIR_TLO_Msk         (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)          /*!< 0x1FFF0000 */

+#define SPDIFRX_DIR_TLO             SPDIFRX_DIR_TLO_Msk                        /*!<Threshold HIGH     */

+

+/*******************  Bit definition for SPDIFRX_VERR register    *******************/

+#define SPDIFRX_VERR_MINREV_Pos     (0U)

+#define SPDIFRX_VERR_MINREV_Msk     (0xFUL << SPDIFRX_VERR_MINREV_Pos)         /*!< 0x0000000F */

+#define SPDIFRX_VERR_MINREV         SPDIFRX_VERR_MINREV_Msk                    /*!<SPDIFRX Minor revision     */

+#define SPDIFRX_VERR_MAJREV_Pos     (4U)

+#define SPDIFRX_VERR_MAJREV_Msk     (0xFUL << SPDIFRX_VERR_MAJREV_Pos)         /*!< 0x000000F0 */

+#define SPDIFRX_VERR_MAJREV         SPDIFRX_VERR_MAJREV_Msk                    /*!<SPDIFRX Major revision     */

+

+/*******************  Bit definition for SPDIFRX_IDR register    *******************/

+#define SPDIFRX_IDR_ID_Pos          (0U)

+#define SPDIFRX_IDR_ID_Msk          (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos)       /*!< 0xFFFFFFFF */

+#define SPDIFRX_IDR_ID              SPDIFRX_IDR_ID_Msk                         /*!<SPDIFRX identifier     */

+

+/*******************  Bit definition for SPDIFRX_SIDR register    *******************/

+#define SPDIFRX_SIDR_SID_Pos        (0U)

+#define SPDIFRX_SIDR_SID_Msk        (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos)     /*!< 0xFFFFFFFF */

+#define SPDIFRX_SIDR_SID            SPDIFRX_SIDR_SID_Msk                       /*!<Size of the memory region allocated to SPDIFRX registers */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          Serial Audio Interface                            */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  SAI VERSION  ********************************/

+#define SAI_VER_V2_X

+

+/********************  Bit definition for SAI_GCR register  *******************/

+#define SAI_GCR_SYNCIN_Pos         (0U)

+#define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000003 */

+#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */

+#define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */

+#define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */

+

+#define SAI_GCR_SYNCOUT_Pos        (4U)

+#define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000030 */

+#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */

+#define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */

+#define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */

+

+/*******************  Bit definition for SAI_xCR1 register  *******************/

+#define SAI_xCR1_MODE_Pos          (0U)

+#define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */

+#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */

+#define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */

+#define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */

+

+#define SAI_xCR1_PRTCFG_Pos        (2U)

+#define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */

+#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */

+#define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */

+#define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */

+

+#define SAI_xCR1_DS_Pos            (5U)

+#define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */

+#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */

+#define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */

+#define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */

+#define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */

+

+#define SAI_xCR1_LSBFIRST_Pos      (8U)

+#define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */

+#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */

+#define SAI_xCR1_CKSTR_Pos         (9U)

+#define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */

+#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */

+

+#define SAI_xCR1_SYNCEN_Pos        (10U)

+#define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */

+#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */

+#define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */

+#define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */

+

+#define SAI_xCR1_MONO_Pos          (12U)

+#define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */

+#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */

+#define SAI_xCR1_OUTDRIV_Pos       (13U)

+#define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */

+#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */

+#define SAI_xCR1_SAIEN_Pos         (16U)

+#define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */

+#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */

+#define SAI_xCR1_DMAEN_Pos         (17U)

+#define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */

+#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */

+#define SAI_xCR1_NODIV_Pos         (19U)

+#define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */

+#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */

+

+#define SAI_xCR1_MCKDIV_Pos        (20U)

+#define SAI_xCR1_MCKDIV_Msk        (0x3FUL << SAI_xCR1_MCKDIV_Pos)             /*!< 0x03F00000 */

+#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[5:0] (Master ClocK Divider)  */

+#define SAI_xCR1_MCKDIV_0          (0x01UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00100000 */

+#define SAI_xCR1_MCKDIV_1          (0x02UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00200000 */

+#define SAI_xCR1_MCKDIV_2          (0x04UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00400000 */

+#define SAI_xCR1_MCKDIV_3          (0x08UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00800000 */

+#define SAI_xCR1_MCKDIV_4          (0x10UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x01000000 */

+#define SAI_xCR1_MCKDIV_5          (0x20UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x02000000 */

+

+#define SAI_xCR1_MCKEN_Pos         (27U)

+#define SAI_xCR1_MCKEN_Msk         (0x1UL << SAI_xCR1_MCKEN_Pos)               /*!< 0x08000000 */

+#define SAI_xCR1_MCKEN             SAI_xCR1_MCKEN_Msk                          /*!<Master ClocK enable */

+

+#define SAI_xCR1_OSR_Pos           (26U)

+#define SAI_xCR1_OSR_Msk           (0x1UL << SAI_xCR1_OSR_Pos)                 /*!< 0x04000000 */

+#define SAI_xCR1_OSR               SAI_xCR1_OSR_Msk                            /*!<OverSampling Ratio for master clock  */

+

+/* Legacy define */

+#define  SAI_xCR1_NOMCK               SAI_xCR1_NODIV

+

+/*******************  Bit definition for SAI_xCR2 register  *******************/

+#define SAI_xCR2_FTH_Pos           (0U)

+#define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */

+#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */

+#define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */

+#define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */

+#define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */

+

+#define SAI_xCR2_FFLUSH_Pos        (3U)

+#define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */

+#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */

+#define SAI_xCR2_TRIS_Pos          (4U)

+#define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */

+#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */

+#define SAI_xCR2_MUTE_Pos          (5U)

+#define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */

+#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */

+#define SAI_xCR2_MUTEVAL_Pos       (6U)

+#define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */

+#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */

+

+#define SAI_xCR2_MUTECNT_Pos       (7U)

+#define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */

+#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */

+#define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */

+#define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */

+#define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */

+#define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */

+#define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */

+#define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */

+

+#define SAI_xCR2_CPL_Pos           (13U)

+#define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */

+#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */

+

+#define SAI_xCR2_COMP_Pos          (14U)

+#define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */

+#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */

+#define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */

+#define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */

+

+/******************  Bit definition for SAI_xFRCR register  *******************/

+#define SAI_xFRCR_FRL_Pos          (0U)

+#define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */

+#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](FRame Length)  */

+#define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */

+#define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */

+#define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */

+#define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */

+#define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */

+#define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */

+#define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */

+#define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */

+

+#define SAI_xFRCR_FSALL_Pos        (8U)

+#define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */

+#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FSALL[6:0] (Frame Synchronization Active Level Length)  */

+#define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */

+#define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */

+#define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */

+#define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */

+#define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */

+#define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */

+#define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */

+

+#define SAI_xFRCR_FSDEF_Pos        (16U)

+#define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */

+#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!<Frame Synchronization Definition  */

+#define SAI_xFRCR_FSPOL_Pos        (17U)

+#define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */

+#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */

+#define SAI_xFRCR_FSOFF_Pos        (18U)

+#define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */

+#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */

+

+/* Legacy define */

+#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL

+

+/******************  Bit definition for SAI_xSLOTR register  *******************/

+#define SAI_xSLOTR_FBOFF_Pos       (0U)

+#define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */

+#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FBOFF[4:0](First Bit Offset)  */

+#define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */

+#define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */

+#define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */

+#define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */

+#define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */

+

+#define SAI_xSLOTR_SLOTSZ_Pos      (6U)

+#define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */

+#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */

+#define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */

+#define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */

+

+#define SAI_xSLOTR_NBSLOT_Pos      (8U)

+#define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */

+#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */

+#define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */

+#define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */

+#define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */

+#define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */

+

+#define SAI_xSLOTR_SLOTEN_Pos      (16U)

+#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */

+#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */

+

+/*******************  Bit definition for SAI_xIMR register  *******************/

+#define SAI_xIMR_OVRUDRIE_Pos      (0U)

+#define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */

+#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */

+#define SAI_xIMR_MUTEDETIE_Pos     (1U)

+#define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */

+#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */

+#define SAI_xIMR_WCKCFGIE_Pos      (2U)

+#define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */

+#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */

+#define SAI_xIMR_FREQIE_Pos        (3U)

+#define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */

+#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */

+#define SAI_xIMR_CNRDYIE_Pos       (4U)

+#define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */

+#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */

+#define SAI_xIMR_AFSDETIE_Pos      (5U)

+#define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */

+#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */

+#define SAI_xIMR_LFSDETIE_Pos      (6U)

+#define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */

+#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */

+

+/********************  Bit definition for SAI_xSR register  *******************/

+#define SAI_xSR_OVRUDR_Pos         (0U)

+#define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */

+#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */

+#define SAI_xSR_MUTEDET_Pos        (1U)

+#define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */

+#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */

+#define SAI_xSR_WCKCFG_Pos         (2U)

+#define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */

+#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */

+#define SAI_xSR_FREQ_Pos           (3U)

+#define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */

+#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */

+#define SAI_xSR_CNRDY_Pos          (4U)

+#define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */

+#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */

+#define SAI_xSR_AFSDET_Pos         (5U)

+#define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */

+#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */

+#define SAI_xSR_LFSDET_Pos         (6U)

+#define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */

+#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */

+

+#define SAI_xSR_FLVL_Pos           (16U)

+#define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */

+#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */

+#define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */

+#define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */

+#define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */

+

+/******************  Bit definition for SAI_xCLRFR register  ******************/

+#define SAI_xCLRFR_COVRUDR_Pos     (0U)

+#define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */

+#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */

+#define SAI_xCLRFR_CMUTEDET_Pos    (1U)

+#define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */

+#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */

+#define SAI_xCLRFR_CWCKCFG_Pos     (2U)

+#define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */

+#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */

+#define SAI_xCLRFR_CFREQ_Pos       (3U)

+#define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */

+#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */

+#define SAI_xCLRFR_CCNRDY_Pos      (4U)

+#define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */

+#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */

+#define SAI_xCLRFR_CAFSDET_Pos     (5U)

+#define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */

+#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */

+#define SAI_xCLRFR_CLFSDET_Pos     (6U)

+#define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */

+#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */

+

+/******************  Bit definition for SAI_xDR register  *********************/

+#define SAI_xDR_DATA_Pos           (0U)

+#define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */

+#define SAI_xDR_DATA               SAI_xDR_DATA_Msk

+

+/*******************  Bit definition for SAI_PDMCR register  ******************/

+#define SAI_PDMCR_PDMEN_Pos        (0U)

+#define SAI_PDMCR_PDMEN_Msk        (0x1UL << SAI_PDMCR_PDMEN_Pos)              /*!< 0x00000001 */

+#define SAI_PDMCR_PDMEN            SAI_PDMCR_PDMEN_Msk                         /*!<PDM Enable                                          */

+

+#define SAI_PDMCR_MICNBR_Pos       (4U)

+#define SAI_PDMCR_MICNBR_Msk       (0x3UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000030 */

+#define SAI_PDMCR_MICNBR           SAI_PDMCR_MICNBR_Msk                        /*!<Number of microphones                               */

+#define SAI_PDMCR_MICNBR_0         (0x1UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000010 */

+#define SAI_PDMCR_MICNBR_1         (0x2UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000020 */

+

+#define SAI_PDMCR_CKEN1_Pos        (8U)

+#define SAI_PDMCR_CKEN1_Msk        (0x1UL << SAI_PDMCR_CKEN1_Pos)              /*!< 0x00000100 */

+#define SAI_PDMCR_CKEN1            SAI_PDMCR_CKEN1_Msk                         /*!<Clock enable of bitstream clock number 1            */

+#define SAI_PDMCR_CKEN2_Pos        (9U)

+#define SAI_PDMCR_CKEN2_Msk        (0x1UL << SAI_PDMCR_CKEN2_Pos)              /*!< 0x00000200 */

+#define SAI_PDMCR_CKEN2            SAI_PDMCR_CKEN2_Msk                         /*!<Clock enable of bitstream clock number 2            */

+#define SAI_PDMCR_CKEN3_Pos        (10U)

+#define SAI_PDMCR_CKEN3_Msk        (0x1UL << SAI_PDMCR_CKEN3_Pos)              /*!< 0x00000400 */

+#define SAI_PDMCR_CKEN3            SAI_PDMCR_CKEN3_Msk                         /*!<Clock enable of bitstream clock number 3            */

+#define SAI_PDMCR_CKEN4_Pos        (11U)

+#define SAI_PDMCR_CKEN4_Msk        (0x1UL << SAI_PDMCR_CKEN4_Pos)              /*!< 0x00000800 */

+#define SAI_PDMCR_CKEN4            SAI_PDMCR_CKEN4_Msk                         /*!<Clock enable of bitstream clock number 4            */

+

+/******************  Bit definition for SAI_PDMDLY register  ******************/

+#define SAI_PDMDLY_DLYM1L_Pos      (0U)

+#define SAI_PDMDLY_DLYM1L_Msk      (0x7UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000007 */

+#define SAI_PDMDLY_DLYM1L          SAI_PDMDLY_DLYM1L_Msk                       /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */

+#define SAI_PDMDLY_DLYM1L_0        (0x1UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000001 */

+#define SAI_PDMDLY_DLYM1L_1        (0x2UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000002 */

+#define SAI_PDMDLY_DLYM1L_2        (0x4UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000004 */

+

+#define SAI_PDMDLY_DLYM1R_Pos      (4U)

+#define SAI_PDMDLY_DLYM1R_Msk      (0x7UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000070 */

+#define SAI_PDMDLY_DLYM1R          SAI_PDMDLY_DLYM1R_Msk                       /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */

+#define SAI_PDMDLY_DLYM1R_0        (0x1UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000010 */

+#define SAI_PDMDLY_DLYM1R_1        (0x2UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000020 */

+#define SAI_PDMDLY_DLYM1R_2        (0x4UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000040 */

+

+#define SAI_PDMDLY_DLYM2L_Pos      (8U)

+#define SAI_PDMDLY_DLYM2L_Msk      (0x7UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000700 */

+#define SAI_PDMDLY_DLYM2L          SAI_PDMDLY_DLYM2L_Msk                       /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */

+#define SAI_PDMDLY_DLYM2L_0        (0x1UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000100 */

+#define SAI_PDMDLY_DLYM2L_1        (0x2UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000200 */

+#define SAI_PDMDLY_DLYM2L_2        (0x4UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000400 */

+

+#define SAI_PDMDLY_DLYM2R_Pos      (12U)

+#define SAI_PDMDLY_DLYM2R_Msk      (0x7UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00007000 */

+#define SAI_PDMDLY_DLYM2R          SAI_PDMDLY_DLYM2R_Msk                       /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/

+#define SAI_PDMDLY_DLYM2R_0        (0x1UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00001000 */

+#define SAI_PDMDLY_DLYM2R_1        (0x2UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00002000 */

+#define SAI_PDMDLY_DLYM2R_2        (0x4UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00004000 */

+

+#define SAI_PDMDLY_DLYM3L_Pos      (16U)

+#define SAI_PDMDLY_DLYM3L_Msk      (0x7UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00070000 */

+#define SAI_PDMDLY_DLYM3L          SAI_PDMDLY_DLYM3L_Msk                       /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/

+#define SAI_PDMDLY_DLYM3L_0        (0x1UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00010000 */

+#define SAI_PDMDLY_DLYM3L_1        (0x2UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00020000 */

+#define SAI_PDMDLY_DLYM3L_2        (0x4UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00040000 */

+

+#define SAI_PDMDLY_DLYM3R_Pos      (20U)

+#define SAI_PDMDLY_DLYM3R_Msk      (0x7UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00700000 */

+#define SAI_PDMDLY_DLYM3R          SAI_PDMDLY_DLYM3R_Msk                       /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/

+#define SAI_PDMDLY_DLYM3R_0        (0x1UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00100000 */

+#define SAI_PDMDLY_DLYM3R_1        (0x2UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00200000 */

+#define SAI_PDMDLY_DLYM3R_2        (0x4UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00400000 */

+

+#define SAI_PDMDLY_DLYM4L_Pos      (24U)

+#define SAI_PDMDLY_DLYM4L_Msk      (0x7UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x07000000 */

+#define SAI_PDMDLY_DLYM4L          SAI_PDMDLY_DLYM4L_Msk                       /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/

+#define SAI_PDMDLY_DLYM4L_0        (0x1UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x01000000 */

+#define SAI_PDMDLY_DLYM4L_1        (0x2UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x02000000 */

+#define SAI_PDMDLY_DLYM4L_2        (0x4UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x04000000 */

+

+#define SAI_PDMDLY_DLYM4R_Pos      (28U)

+#define SAI_PDMDLY_DLYM4R_Msk      (0x7UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x70000000 */

+#define SAI_PDMDLY_DLYM4R          SAI_PDMDLY_DLYM4R_Msk                       /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/

+#define SAI_PDMDLY_DLYM4R_0        (0x1UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x10000000 */

+#define SAI_PDMDLY_DLYM4R_1        (0x2UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x20000000 */

+#define SAI_PDMDLY_DLYM4R_2        (0x4UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x40000000 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           SDMMC Interface                                  */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for SDMMC_POWER register  ******************/

+#define SDMMC_POWER_PWRCTRL_Pos          (0U)

+#define SDMMC_POWER_PWRCTRL_Msk          (0x3UL << SDMMC_POWER_PWRCTRL_Pos)    /*!< 0x00000003 */

+#define SDMMC_POWER_PWRCTRL              SDMMC_POWER_PWRCTRL_Msk               /*!<PWRCTRL[1:0] bits (Power supply control bits) */

+#define SDMMC_POWER_PWRCTRL_0            (0x1UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000001 */

+#define SDMMC_POWER_PWRCTRL_1            (0x2UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000002 */

+#define SDMMC_POWER_VSWITCH_Pos          (2U)

+#define SDMMC_POWER_VSWITCH_Msk          (0x1UL << SDMMC_POWER_VSWITCH_Pos)    /*!< 0x00000004 */

+#define SDMMC_POWER_VSWITCH              SDMMC_POWER_VSWITCH_Msk               /*!<Voltage switch sequence start */

+#define SDMMC_POWER_VSWITCHEN_Pos        (3U)

+#define SDMMC_POWER_VSWITCHEN_Msk        (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)  /*!< 0x00000008 */

+#define SDMMC_POWER_VSWITCHEN            SDMMC_POWER_VSWITCHEN_Msk             /*!<Voltage switch procedure enable */

+#define SDMMC_POWER_DIRPOL_Pos           (4U)

+#define SDMMC_POWER_DIRPOL_Msk           (0x1UL << SDMMC_POWER_DIRPOL_Pos)     /*!< 0x00000010 */

+#define SDMMC_POWER_DIRPOL               SDMMC_POWER_DIRPOL_Msk                /*!<Data and Command direction signals polarity selection */

+

+/******************  Bit definition for SDMMC_CLKCR register  ******************/

+#define SDMMC_CLKCR_CLKDIV_Pos           (0U)

+#define SDMMC_CLKCR_CLKDIV_Msk           (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)   /*!< 0x000003FF */

+#define SDMMC_CLKCR_CLKDIV               SDMMC_CLKCR_CLKDIV_Msk                /*!<Clock divide factor             */

+#define SDMMC_CLKCR_PWRSAV_Pos           (12U)

+#define SDMMC_CLKCR_PWRSAV_Msk           (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)     /*!< 0x00001000 */

+#define SDMMC_CLKCR_PWRSAV               SDMMC_CLKCR_PWRSAV_Msk                /*!<Power saving configuration bit  */

+

+#define SDMMC_CLKCR_WIDBUS_Pos           (14U)

+#define SDMMC_CLKCR_WIDBUS_Msk           (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)     /*!< 0x0000C000 */

+#define SDMMC_CLKCR_WIDBUS               SDMMC_CLKCR_WIDBUS_Msk                /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */

+#define SDMMC_CLKCR_WIDBUS_0             (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00004000 */

+#define SDMMC_CLKCR_WIDBUS_1             (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00008000 */

+

+#define SDMMC_CLKCR_NEGEDGE_Pos          (16U)

+#define SDMMC_CLKCR_NEGEDGE_Msk          (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)    /*!< 0x00010000 */

+#define SDMMC_CLKCR_NEGEDGE              SDMMC_CLKCR_NEGEDGE_Msk               /*!<SDMMC_CK dephasing selection bit */

+#define SDMMC_CLKCR_HWFC_EN_Pos          (17U)

+#define SDMMC_CLKCR_HWFC_EN_Msk          (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)    /*!< 0x00020000 */

+#define SDMMC_CLKCR_HWFC_EN              SDMMC_CLKCR_HWFC_EN_Msk               /*!<HW Flow Control enable           */

+#define SDMMC_CLKCR_DDR_Pos              (18U)

+#define SDMMC_CLKCR_DDR_Msk              (0x1UL << SDMMC_CLKCR_DDR_Pos)        /*!< 0x00040000 */

+#define SDMMC_CLKCR_DDR                  SDMMC_CLKCR_DDR_Msk                   /*!<Data rate signaling selection    */

+#define SDMMC_CLKCR_BUSSPEED_Pos         (19U)

+#define SDMMC_CLKCR_BUSSPEED_Msk         (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)   /*!< 0x00080000 */

+#define SDMMC_CLKCR_BUSSPEED             SDMMC_CLKCR_BUSSPEED_Msk              /*!<Bus speed mode selection         */

+#define SDMMC_CLKCR_SELCLKRX_Pos         (20U)

+#define SDMMC_CLKCR_SELCLKRX_Msk         (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)   /*!< 0x00300000 */

+#define SDMMC_CLKCR_SELCLKRX             SDMMC_CLKCR_SELCLKRX_Msk              /*!<SELCLKRX[1:0] bits (Receive clock selection) */

+#define SDMMC_CLKCR_SELCLKRX_0           (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00100000 */

+#define SDMMC_CLKCR_SELCLKRX_1           (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00200000 */

+

+/*******************  Bit definition for SDMMC_ARG register  *******************/

+#define SDMMC_ARG_CMDARG_Pos             (0U)

+#define SDMMC_ARG_CMDARG_Msk             (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_ARG_CMDARG                 SDMMC_ARG_CMDARG_Msk                  /*!<Command argument */

+

+/*******************  Bit definition for SDMMC_CMD register  *******************/

+#define SDMMC_CMD_CMDINDEX_Pos           (0U)

+#define SDMMC_CMD_CMDINDEX_Msk           (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)    /*!< 0x0000003F */

+#define SDMMC_CMD_CMDINDEX               SDMMC_CMD_CMDINDEX_Msk                /*!<Command Index                               */

+#define SDMMC_CMD_CMDTRANS_Pos           (6U)

+#define SDMMC_CMD_CMDTRANS_Msk           (0x1UL << SDMMC_CMD_CMDTRANS_Pos)     /*!< 0x00000040 */

+#define SDMMC_CMD_CMDTRANS               SDMMC_CMD_CMDTRANS_Msk                /*!<CPSM Treats command as a Data Transfer      */

+#define SDMMC_CMD_CMDSTOP_Pos            (7U)

+#define SDMMC_CMD_CMDSTOP_Msk            (0x1UL << SDMMC_CMD_CMDSTOP_Pos)      /*!< 0x00000080 */

+#define SDMMC_CMD_CMDSTOP                SDMMC_CMD_CMDSTOP_Msk                 /*!<CPSM Treats command as a Stop               */

+

+#define SDMMC_CMD_WAITRESP_Pos           (8U)

+#define SDMMC_CMD_WAITRESP_Msk           (0x3UL << SDMMC_CMD_WAITRESP_Pos)     /*!< 0x00000300 */

+#define SDMMC_CMD_WAITRESP               SDMMC_CMD_WAITRESP_Msk                /*!<WAITRESP[1:0] bits (Wait for response bits) */

+#define SDMMC_CMD_WAITRESP_0             (0x1UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000100 */

+#define SDMMC_CMD_WAITRESP_1             (0x2UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000200 */

+

+#define SDMMC_CMD_WAITINT_Pos            (10U)

+#define SDMMC_CMD_WAITINT_Msk            (0x1UL << SDMMC_CMD_WAITINT_Pos)      /*!< 0x00000400 */

+#define SDMMC_CMD_WAITINT                SDMMC_CMD_WAITINT_Msk                 /*!<CPSM Waits for Interrupt Request                               */

+#define SDMMC_CMD_WAITPEND_Pos           (11U)

+#define SDMMC_CMD_WAITPEND_Msk           (0x1UL << SDMMC_CMD_WAITPEND_Pos)     /*!< 0x00000800 */

+#define SDMMC_CMD_WAITPEND               SDMMC_CMD_WAITPEND_Msk                /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */

+#define SDMMC_CMD_CPSMEN_Pos             (12U)

+#define SDMMC_CMD_CPSMEN_Msk             (0x1UL << SDMMC_CMD_CPSMEN_Pos)       /*!< 0x00001000 */

+#define SDMMC_CMD_CPSMEN                 SDMMC_CMD_CPSMEN_Msk                  /*!<Command path state machine (CPSM) Enable bit                   */

+#define SDMMC_CMD_DTHOLD_Pos             (13U)

+#define SDMMC_CMD_DTHOLD_Msk             (0x1UL << SDMMC_CMD_DTHOLD_Pos)       /*!< 0x00002000 */

+#define SDMMC_CMD_DTHOLD                 SDMMC_CMD_DTHOLD_Msk                  /*!<Hold new data block transmission and reception in the DPSM     */

+#define SDMMC_CMD_BOOTMODE_Pos           (14U)

+#define SDMMC_CMD_BOOTMODE_Msk           (0x1UL << SDMMC_CMD_BOOTMODE_Pos)     /*!< 0x00004000 */

+#define SDMMC_CMD_BOOTMODE               SDMMC_CMD_BOOTMODE_Msk                /*!<Boot mode                                                      */

+#define SDMMC_CMD_BOOTEN_Pos             (15U)

+#define SDMMC_CMD_BOOTEN_Msk             (0x1UL << SDMMC_CMD_BOOTEN_Pos)       /*!< 0x00008000 */

+#define SDMMC_CMD_BOOTEN                 SDMMC_CMD_BOOTEN_Msk                  /*!<Enable Boot mode procedure                                     */

+#define SDMMC_CMD_CMDSUSPEND_Pos         (16U)

+#define SDMMC_CMD_CMDSUSPEND_Msk         (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)   /*!< 0x00010000 */

+#define SDMMC_CMD_CMDSUSPEND             SDMMC_CMD_CMDSUSPEND_Msk              /*!<CPSM Treats command as a Suspend or Resume command             */

+

+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/

+#define SDMMC_RESPCMD_RESPCMD_Pos        (0U)

+#define SDMMC_RESPCMD_RESPCMD_Msk        (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */

+#define SDMMC_RESPCMD_RESPCMD            SDMMC_RESPCMD_RESPCMD_Msk             /*!<Response command index */

+

+/******************  Bit definition for SDMMC_RESP0 register  ******************/

+#define SDMMC_RESP0_CARDSTATUS0_Pos      (0U)

+#define SDMMC_RESP0_CARDSTATUS0_Msk      (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP0_CARDSTATUS0          SDMMC_RESP0_CARDSTATUS0_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP1 register  ******************/

+#define SDMMC_RESP1_CARDSTATUS1_Pos      (0U)

+#define SDMMC_RESP1_CARDSTATUS1_Msk      (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP1_CARDSTATUS1          SDMMC_RESP1_CARDSTATUS1_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP2 register  ******************/

+#define SDMMC_RESP2_CARDSTATUS2_Pos      (0U)

+#define SDMMC_RESP2_CARDSTATUS2_Msk      (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP2_CARDSTATUS2          SDMMC_RESP2_CARDSTATUS2_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP3 register  ******************/

+#define SDMMC_RESP3_CARDSTATUS3_Pos      (0U)

+#define SDMMC_RESP3_CARDSTATUS3_Msk      (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP3_CARDSTATUS3          SDMMC_RESP3_CARDSTATUS3_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP4 register  ******************/

+#define SDMMC_RESP4_CARDSTATUS4_Pos      (0U)

+#define SDMMC_RESP4_CARDSTATUS4_Msk      (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP4_CARDSTATUS4          SDMMC_RESP4_CARDSTATUS4_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_DTIMER register  *****************/

+#define SDMMC_DTIMER_DATATIME_Pos        (0U)

+#define SDMMC_DTIMER_DATATIME_Msk        (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_DTIMER_DATATIME            SDMMC_DTIMER_DATATIME_Msk             /*!<Data timeout period. */

+

+/******************  Bit definition for SDMMC_DLEN register  *******************/

+#define SDMMC_DLEN_DATALENGTH_Pos        (0U)

+#define SDMMC_DLEN_DATALENGTH_Msk        (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_DLEN_DATALENGTH            SDMMC_DLEN_DATALENGTH_Msk             /*!<Data length value    */

+

+/******************  Bit definition for SDMMC_DCTRL register  ******************/

+#define SDMMC_DCTRL_DTEN_Pos             (0U)

+#define SDMMC_DCTRL_DTEN_Msk             (0x1UL << SDMMC_DCTRL_DTEN_Pos)       /*!< 0x00000001 */

+#define SDMMC_DCTRL_DTEN                 SDMMC_DCTRL_DTEN_Msk                  /*!<Data transfer enabled bit                */

+#define SDMMC_DCTRL_DTDIR_Pos            (1U)

+#define SDMMC_DCTRL_DTDIR_Msk            (0x1UL << SDMMC_DCTRL_DTDIR_Pos)      /*!< 0x00000002 */

+#define SDMMC_DCTRL_DTDIR                SDMMC_DCTRL_DTDIR_Msk                 /*!<Data transfer direction selection        */

+#define SDMMC_DCTRL_DTMODE_Pos           (2U)

+#define SDMMC_DCTRL_DTMODE_Msk           (0x3UL << SDMMC_DCTRL_DTMODE_Pos)     /*!< 0x0000000C */

+#define SDMMC_DCTRL_DTMODE               SDMMC_DCTRL_DTMODE_Msk                /*!<DTMODE[1:0] Data transfer mode selection */

+#define SDMMC_DCTRL_DTMODE_0             (0x1UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000004 */

+#define SDMMC_DCTRL_DTMODE_1             (0x2UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000008 */

+

+#define SDMMC_DCTRL_DBLOCKSIZE_Pos       (4U)

+#define SDMMC_DCTRL_DBLOCKSIZE_Msk       (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */

+#define SDMMC_DCTRL_DBLOCKSIZE           SDMMC_DCTRL_DBLOCKSIZE_Msk            /*!<DBLOCKSIZE[3:0] bits (Data block size) */

+#define SDMMC_DCTRL_DBLOCKSIZE_0         (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000010 */

+#define SDMMC_DCTRL_DBLOCKSIZE_1         (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000020 */

+#define SDMMC_DCTRL_DBLOCKSIZE_2         (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000040 */

+#define SDMMC_DCTRL_DBLOCKSIZE_3         (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000080 */

+

+#define SDMMC_DCTRL_RWSTART_Pos          (8U)

+#define SDMMC_DCTRL_RWSTART_Msk          (0x1UL << SDMMC_DCTRL_RWSTART_Pos)    /*!< 0x00000100 */

+#define SDMMC_DCTRL_RWSTART              SDMMC_DCTRL_RWSTART_Msk               /*!<Read wait start                                 */

+#define SDMMC_DCTRL_RWSTOP_Pos           (9U)

+#define SDMMC_DCTRL_RWSTOP_Msk           (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)     /*!< 0x00000200 */

+#define SDMMC_DCTRL_RWSTOP               SDMMC_DCTRL_RWSTOP_Msk                /*!<Read wait stop                                  */

+#define SDMMC_DCTRL_RWMOD_Pos            (10U)

+#define SDMMC_DCTRL_RWMOD_Msk            (0x1UL << SDMMC_DCTRL_RWMOD_Pos)      /*!< 0x00000400 */

+#define SDMMC_DCTRL_RWMOD                SDMMC_DCTRL_RWMOD_Msk                 /*!<Read wait mode                                  */

+#define SDMMC_DCTRL_SDIOEN_Pos           (11U)

+#define SDMMC_DCTRL_SDIOEN_Msk           (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)     /*!< 0x00000800 */

+#define SDMMC_DCTRL_SDIOEN               SDMMC_DCTRL_SDIOEN_Msk                /*!<SD I/O enable functions                         */

+#define SDMMC_DCTRL_BOOTACKEN_Pos        (12U)

+#define SDMMC_DCTRL_BOOTACKEN_Msk        (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)  /*!< 0x00001000 */

+#define SDMMC_DCTRL_BOOTACKEN            SDMMC_DCTRL_BOOTACKEN_Msk             /*!<Enable the reception of the Boot Acknowledgment */

+#define SDMMC_DCTRL_FIFORST_Pos          (13U)

+#define SDMMC_DCTRL_FIFORST_Msk          (0x1UL << SDMMC_DCTRL_FIFORST_Pos)    /*!< 0x00002000 */

+#define SDMMC_DCTRL_FIFORST              SDMMC_DCTRL_FIFORST_Msk               /*!<FIFO reset                                      */

+

+/******************  Bit definition for SDMMC_DCOUNT register  *****************/

+#define SDMMC_DCOUNT_DATACOUNT_Pos       (0U)

+#define SDMMC_DCOUNT_DATACOUNT_Msk       (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_DCOUNT_DATACOUNT           SDMMC_DCOUNT_DATACOUNT_Msk            /*!<Data count value */

+

+/******************  Bit definition for SDMMC_STA register  ********************/

+#define SDMMC_STA_CCRCFAIL_Pos           (0U)

+#define SDMMC_STA_CCRCFAIL_Msk           (0x1UL << SDMMC_STA_CCRCFAIL_Pos)     /*!< 0x00000001 */

+#define SDMMC_STA_CCRCFAIL               SDMMC_STA_CCRCFAIL_Msk                /*!<Command response received (CRC check failed)  */

+#define SDMMC_STA_DCRCFAIL_Pos           (1U)

+#define SDMMC_STA_DCRCFAIL_Msk           (0x1UL << SDMMC_STA_DCRCFAIL_Pos)     /*!< 0x00000002 */

+#define SDMMC_STA_DCRCFAIL               SDMMC_STA_DCRCFAIL_Msk                /*!<Data block sent/received (CRC check failed)   */

+#define SDMMC_STA_CTIMEOUT_Pos           (2U)

+#define SDMMC_STA_CTIMEOUT_Msk           (0x1UL << SDMMC_STA_CTIMEOUT_Pos)     /*!< 0x00000004 */

+#define SDMMC_STA_CTIMEOUT               SDMMC_STA_CTIMEOUT_Msk                /*!<Command response timeout                      */

+#define SDMMC_STA_DTIMEOUT_Pos           (3U)

+#define SDMMC_STA_DTIMEOUT_Msk           (0x1UL << SDMMC_STA_DTIMEOUT_Pos)     /*!< 0x00000008 */

+#define SDMMC_STA_DTIMEOUT               SDMMC_STA_DTIMEOUT_Msk                /*!<Data timeout                                  */

+#define SDMMC_STA_TXUNDERR_Pos           (4U)

+#define SDMMC_STA_TXUNDERR_Msk           (0x1UL << SDMMC_STA_TXUNDERR_Pos)     /*!< 0x00000010 */

+#define SDMMC_STA_TXUNDERR               SDMMC_STA_TXUNDERR_Msk                /*!<Transmit FIFO underrun error                  */

+#define SDMMC_STA_RXOVERR_Pos            (5U)

+#define SDMMC_STA_RXOVERR_Msk            (0x1UL << SDMMC_STA_RXOVERR_Pos)      /*!< 0x00000020 */

+#define SDMMC_STA_RXOVERR                SDMMC_STA_RXOVERR_Msk                 /*!<Received FIFO overrun error                   */

+#define SDMMC_STA_CMDREND_Pos            (6U)

+#define SDMMC_STA_CMDREND_Msk            (0x1UL << SDMMC_STA_CMDREND_Pos)      /*!< 0x00000040 */

+#define SDMMC_STA_CMDREND                SDMMC_STA_CMDREND_Msk                 /*!<Command response received (CRC check passed)  */

+#define SDMMC_STA_CMDSENT_Pos            (7U)

+#define SDMMC_STA_CMDSENT_Msk            (0x1UL << SDMMC_STA_CMDSENT_Pos)      /*!< 0x00000080 */

+#define SDMMC_STA_CMDSENT                SDMMC_STA_CMDSENT_Msk                 /*!<Command sent (no response required)           */

+#define SDMMC_STA_DATAEND_Pos            (8U)

+#define SDMMC_STA_DATAEND_Msk            (0x1UL << SDMMC_STA_DATAEND_Pos)      /*!< 0x00000100 */

+#define SDMMC_STA_DATAEND                SDMMC_STA_DATAEND_Msk                 /*!<Data end (data counter, SDIDCOUNT, is zero)   */

+#define SDMMC_STA_DHOLD_Pos              (9U)

+#define SDMMC_STA_DHOLD_Msk              (0x1UL << SDMMC_STA_DHOLD_Pos)        /*!< 0x00000200 */

+#define SDMMC_STA_DHOLD                  SDMMC_STA_DHOLD_Msk                   /*!<Data transfer Hold                                                      */

+#define SDMMC_STA_DBCKEND_Pos            (10U)

+#define SDMMC_STA_DBCKEND_Msk            (0x1UL << SDMMC_STA_DBCKEND_Pos)      /*!< 0x00000400 */

+#define SDMMC_STA_DBCKEND                SDMMC_STA_DBCKEND_Msk                 /*!<Data block sent/received (CRC check passed)   */

+#define SDMMC_STA_DABORT_Pos             (11U)

+#define SDMMC_STA_DABORT_Msk             (0x1UL << SDMMC_STA_DABORT_Pos)       /*!< 0x00000800 */

+#define SDMMC_STA_DABORT                 SDMMC_STA_DABORT_Msk                  /*!<Data transfer aborted by CMD12                                          */

+#define SDMMC_STA_DPSMACT_Pos            (12U)

+#define SDMMC_STA_DPSMACT_Msk            (0x1UL << SDMMC_STA_DPSMACT_Pos)      /*!< 0x00001000 */

+#define SDMMC_STA_DPSMACT                SDMMC_STA_DPSMACT_Msk                 /*!<Data path state machine active                                       */

+#define SDMMC_STA_CPSMACT_Pos            (13U)

+#define SDMMC_STA_CPSMACT_Msk            (0x1UL << SDMMC_STA_CPSMACT_Pos)      /*!< 0x00002000 */

+#define SDMMC_STA_CPSMACT                SDMMC_STA_CPSMACT_Msk                 /*!<Command path state machine active                                          */

+#define SDMMC_STA_TXFIFOHE_Pos           (14U)

+#define SDMMC_STA_TXFIFOHE_Msk           (0x1UL << SDMMC_STA_TXFIFOHE_Pos)     /*!< 0x00004000 */

+#define SDMMC_STA_TXFIFOHE               SDMMC_STA_TXFIFOHE_Msk                /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */

+#define SDMMC_STA_RXFIFOHF_Pos           (15U)

+#define SDMMC_STA_RXFIFOHF_Msk           (0x1UL << SDMMC_STA_RXFIFOHF_Pos)     /*!< 0x00008000 */

+#define SDMMC_STA_RXFIFOHF               SDMMC_STA_RXFIFOHF_Msk                /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */

+#define SDMMC_STA_TXFIFOF_Pos            (16U)

+#define SDMMC_STA_TXFIFOF_Msk            (0x1UL << SDMMC_STA_TXFIFOF_Pos)      /*!< 0x00010000 */

+#define SDMMC_STA_TXFIFOF                SDMMC_STA_TXFIFOF_Msk                 /*!<Transmit FIFO full                            */

+#define SDMMC_STA_RXFIFOF_Pos            (17U)

+#define SDMMC_STA_RXFIFOF_Msk            (0x1UL << SDMMC_STA_RXFIFOF_Pos)      /*!< 0x00020000 */

+#define SDMMC_STA_RXFIFOF                SDMMC_STA_RXFIFOF_Msk                 /*!<Receive FIFO full                             */

+#define SDMMC_STA_TXFIFOE_Pos            (18U)

+#define SDMMC_STA_TXFIFOE_Msk            (0x1UL << SDMMC_STA_TXFIFOE_Pos)      /*!< 0x00040000 */

+#define SDMMC_STA_TXFIFOE                SDMMC_STA_TXFIFOE_Msk                 /*!<Transmit FIFO empty                           */

+#define SDMMC_STA_RXFIFOE_Pos            (19U)

+#define SDMMC_STA_RXFIFOE_Msk            (0x1UL << SDMMC_STA_RXFIFOE_Pos)      /*!< 0x00080000 */

+#define SDMMC_STA_RXFIFOE                SDMMC_STA_RXFIFOE_Msk                 /*!<Receive FIFO empty                            */

+#define SDMMC_STA_BUSYD0_Pos             (20U)

+#define SDMMC_STA_BUSYD0_Msk             (0x1UL << SDMMC_STA_BUSYD0_Pos)       /*!< 0x00100000 */

+#define SDMMC_STA_BUSYD0                 SDMMC_STA_BUSYD0_Msk                  /*!<Inverted value of SDMMC_D0 line (Busy)                                  */

+#define SDMMC_STA_BUSYD0END_Pos          (21U)

+#define SDMMC_STA_BUSYD0END_Msk          (0x1UL << SDMMC_STA_BUSYD0END_Pos)    /*!< 0x00200000 */

+#define SDMMC_STA_BUSYD0END              SDMMC_STA_BUSYD0END_Msk               /*!<End of SDMMC_D0 Busy following a CMD response detected                  */

+#define SDMMC_STA_SDIOIT_Pos             (22U)

+#define SDMMC_STA_SDIOIT_Msk             (0x1UL << SDMMC_STA_SDIOIT_Pos)       /*!< 0x00400000 */

+#define SDMMC_STA_SDIOIT                 SDMMC_STA_SDIOIT_Msk                  /*!<SDIO interrupt received                                                 */

+#define SDMMC_STA_ACKFAIL_Pos            (23U)

+#define SDMMC_STA_ACKFAIL_Msk            (0x1UL << SDMMC_STA_ACKFAIL_Pos)      /*!< 0x00800000 */

+#define SDMMC_STA_ACKFAIL                SDMMC_STA_ACKFAIL_Msk                 /*!<Boot Acknowledgment received (BootAck check fail)                       */

+#define SDMMC_STA_ACKTIMEOUT_Pos         (24U)

+#define SDMMC_STA_ACKTIMEOUT_Msk         (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)   /*!< 0x01000000 */

+#define SDMMC_STA_ACKTIMEOUT             SDMMC_STA_ACKTIMEOUT_Msk              /*!<Boot Acknowledgment timeout                                             */

+#define SDMMC_STA_VSWEND_Pos             (25U)

+#define SDMMC_STA_VSWEND_Msk             (0x1UL << SDMMC_STA_VSWEND_Pos)       /*!< 0x02000000 */

+#define SDMMC_STA_VSWEND                 SDMMC_STA_VSWEND_Msk                  /*!<Voltage switch critical timing section completion                       */

+#define SDMMC_STA_CKSTOP_Pos             (26U)

+#define SDMMC_STA_CKSTOP_Msk             (0x1UL << SDMMC_STA_CKSTOP_Pos)       /*!< 0x04000000 */

+#define SDMMC_STA_CKSTOP                 SDMMC_STA_CKSTOP_Msk                  /*!<SDMMC_CK stopped in Voltage switch procedure                            */

+#define SDMMC_STA_IDMATE_Pos             (27U)

+#define SDMMC_STA_IDMATE_Msk             (0x1UL << SDMMC_STA_IDMATE_Pos)       /*!< 0x08000000 */

+#define SDMMC_STA_IDMATE                 SDMMC_STA_IDMATE_Msk                  /*!<IDMA transfer error                                                     */

+#define SDMMC_STA_IDMABTC_Pos            (28U)

+#define SDMMC_STA_IDMABTC_Msk            (0x1UL << SDMMC_STA_IDMABTC_Pos)      /*!< 0x10000000 */

+#define SDMMC_STA_IDMABTC                SDMMC_STA_IDMABTC_Msk                 /*!<IDMA buffer transfer complete                                           */

+

+/*******************  Bit definition for SDMMC_ICR register  *******************/

+#define SDMMC_ICR_CCRCFAILC_Pos          (0U)

+#define SDMMC_ICR_CCRCFAILC_Msk          (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)    /*!< 0x00000001 */

+#define SDMMC_ICR_CCRCFAILC              SDMMC_ICR_CCRCFAILC_Msk               /*!<CCRCFAIL flag clear bit */

+#define SDMMC_ICR_DCRCFAILC_Pos          (1U)

+#define SDMMC_ICR_DCRCFAILC_Msk          (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)    /*!< 0x00000002 */

+#define SDMMC_ICR_DCRCFAILC              SDMMC_ICR_DCRCFAILC_Msk               /*!<DCRCFAIL flag clear bit */

+#define SDMMC_ICR_CTIMEOUTC_Pos          (2U)

+#define SDMMC_ICR_CTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)    /*!< 0x00000004 */

+#define SDMMC_ICR_CTIMEOUTC              SDMMC_ICR_CTIMEOUTC_Msk               /*!<CTIMEOUT flag clear bit */

+#define SDMMC_ICR_DTIMEOUTC_Pos          (3U)

+#define SDMMC_ICR_DTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)    /*!< 0x00000008 */

+#define SDMMC_ICR_DTIMEOUTC              SDMMC_ICR_DTIMEOUTC_Msk               /*!<DTIMEOUT flag clear bit */

+#define SDMMC_ICR_TXUNDERRC_Pos          (4U)

+#define SDMMC_ICR_TXUNDERRC_Msk          (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)    /*!< 0x00000010 */

+#define SDMMC_ICR_TXUNDERRC              SDMMC_ICR_TXUNDERRC_Msk               /*!<TXUNDERR flag clear bit */

+#define SDMMC_ICR_RXOVERRC_Pos           (5U)

+#define SDMMC_ICR_RXOVERRC_Msk           (0x1UL << SDMMC_ICR_RXOVERRC_Pos)     /*!< 0x00000020 */

+#define SDMMC_ICR_RXOVERRC               SDMMC_ICR_RXOVERRC_Msk                /*!<RXOVERR flag clear bit  */

+#define SDMMC_ICR_CMDRENDC_Pos           (6U)

+#define SDMMC_ICR_CMDRENDC_Msk           (0x1UL << SDMMC_ICR_CMDRENDC_Pos)     /*!< 0x00000040 */

+#define SDMMC_ICR_CMDRENDC               SDMMC_ICR_CMDRENDC_Msk                /*!<CMDREND flag clear bit  */

+#define SDMMC_ICR_CMDSENTC_Pos           (7U)

+#define SDMMC_ICR_CMDSENTC_Msk           (0x1UL << SDMMC_ICR_CMDSENTC_Pos)     /*!< 0x00000080 */

+#define SDMMC_ICR_CMDSENTC               SDMMC_ICR_CMDSENTC_Msk                /*!<CMDSENT flag clear bit  */

+#define SDMMC_ICR_DATAENDC_Pos           (8U)

+#define SDMMC_ICR_DATAENDC_Msk           (0x1UL << SDMMC_ICR_DATAENDC_Pos)     /*!< 0x00000100 */

+#define SDMMC_ICR_DATAENDC               SDMMC_ICR_DATAENDC_Msk                /*!<DATAEND flag clear bit  */

+#define SDMMC_ICR_DHOLDC_Pos             (9U)

+#define SDMMC_ICR_DHOLDC_Msk             (0x1UL << SDMMC_ICR_DHOLDC_Pos)       /*!< 0x00000200 */

+#define SDMMC_ICR_DHOLDC                 SDMMC_ICR_DHOLDC_Msk                  /*!<DHOLD flag clear bit       */

+#define SDMMC_ICR_DBCKENDC_Pos           (10U)

+#define SDMMC_ICR_DBCKENDC_Msk           (0x1UL << SDMMC_ICR_DBCKENDC_Pos)     /*!< 0x00000400 */

+#define SDMMC_ICR_DBCKENDC               SDMMC_ICR_DBCKENDC_Msk                /*!<DBCKEND flag clear bit  */

+#define SDMMC_ICR_DABORTC_Pos            (11U)

+#define SDMMC_ICR_DABORTC_Msk            (0x1UL << SDMMC_ICR_DABORTC_Pos)      /*!< 0x00000800 */

+#define SDMMC_ICR_DABORTC                SDMMC_ICR_DABORTC_Msk                 /*!<DABORTC flag clear bit     */

+#define SDMMC_ICR_BUSYD0ENDC_Pos         (21U)

+#define SDMMC_ICR_BUSYD0ENDC_Msk         (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)   /*!< 0x00200000 */

+#define SDMMC_ICR_BUSYD0ENDC             SDMMC_ICR_BUSYD0ENDC_Msk              /*!<BUSYD0ENDC flag clear bit  */

+#define SDMMC_ICR_SDIOITC_Pos            (22U)

+#define SDMMC_ICR_SDIOITC_Msk            (0x1UL << SDMMC_ICR_SDIOITC_Pos)      /*!< 0x00400000 */

+#define SDMMC_ICR_SDIOITC                SDMMC_ICR_SDIOITC_Msk                 /*!<SDIOIT flag clear bit      */

+#define SDMMC_ICR_ACKFAILC_Pos           (23U)

+#define SDMMC_ICR_ACKFAILC_Msk           (0x1UL << SDMMC_ICR_ACKFAILC_Pos)     /*!< 0x00800000 */

+#define SDMMC_ICR_ACKFAILC               SDMMC_ICR_ACKFAILC_Msk                /*!<ACKFAILC flag clear bit    */

+#define SDMMC_ICR_ACKTIMEOUTC_Pos        (24U)

+#define SDMMC_ICR_ACKTIMEOUTC_Msk        (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)  /*!< 0x01000000 */

+#define SDMMC_ICR_ACKTIMEOUTC            SDMMC_ICR_ACKTIMEOUTC_Msk             /*!<ACKTIMEOUTC flag clear bit */

+#define SDMMC_ICR_VSWENDC_Pos            (25U)

+#define SDMMC_ICR_VSWENDC_Msk            (0x1UL << SDMMC_ICR_VSWENDC_Pos)      /*!< 0x02000000 */

+#define SDMMC_ICR_VSWENDC                SDMMC_ICR_VSWENDC_Msk                 /*!<VSWENDC flag clear bit     */

+#define SDMMC_ICR_CKSTOPC_Pos            (26U)

+#define SDMMC_ICR_CKSTOPC_Msk            (0x1UL << SDMMC_ICR_CKSTOPC_Pos)      /*!< 0x04000000 */

+#define SDMMC_ICR_CKSTOPC                SDMMC_ICR_CKSTOPC_Msk                 /*!<CKSTOPC flag clear bit     */

+#define SDMMC_ICR_IDMATEC_Pos            (27U)

+#define SDMMC_ICR_IDMATEC_Msk            (0x1UL << SDMMC_ICR_IDMATEC_Pos)      /*!< 0x08000000 */

+#define SDMMC_ICR_IDMATEC                SDMMC_ICR_IDMATEC_Msk                 /*!<IDMATEC flag clear bit     */

+#define SDMMC_ICR_IDMABTCC_Pos           (28U)

+#define SDMMC_ICR_IDMABTCC_Msk           (0x1UL << SDMMC_ICR_IDMABTCC_Pos)     /*!< 0x10000000 */

+#define SDMMC_ICR_IDMABTCC               SDMMC_ICR_IDMABTCC_Msk                /*!<IDMABTCC flag clear bit    */

+

+/******************  Bit definition for SDMMC_MASK register  *******************/

+#define SDMMC_MASK_CCRCFAILIE_Pos        (0U)

+#define SDMMC_MASK_CCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)  /*!< 0x00000001 */

+#define SDMMC_MASK_CCRCFAILIE            SDMMC_MASK_CCRCFAILIE_Msk             /*!<Command CRC Fail Interrupt Enable          */

+#define SDMMC_MASK_DCRCFAILIE_Pos        (1U)

+#define SDMMC_MASK_DCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)  /*!< 0x00000002 */

+#define SDMMC_MASK_DCRCFAILIE            SDMMC_MASK_DCRCFAILIE_Msk             /*!<Data CRC Fail Interrupt Enable             */

+#define SDMMC_MASK_CTIMEOUTIE_Pos        (2U)

+#define SDMMC_MASK_CTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)  /*!< 0x00000004 */

+#define SDMMC_MASK_CTIMEOUTIE            SDMMC_MASK_CTIMEOUTIE_Msk             /*!<Command TimeOut Interrupt Enable           */

+#define SDMMC_MASK_DTIMEOUTIE_Pos        (3U)

+#define SDMMC_MASK_DTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)  /*!< 0x00000008 */

+#define SDMMC_MASK_DTIMEOUTIE            SDMMC_MASK_DTIMEOUTIE_Msk             /*!<Data TimeOut Interrupt Enable              */

+#define SDMMC_MASK_TXUNDERRIE_Pos        (4U)

+#define SDMMC_MASK_TXUNDERRIE_Msk        (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)  /*!< 0x00000010 */

+#define SDMMC_MASK_TXUNDERRIE            SDMMC_MASK_TXUNDERRIE_Msk             /*!<Tx FIFO UnderRun Error Interrupt Enable    */

+#define SDMMC_MASK_RXOVERRIE_Pos         (5U)

+#define SDMMC_MASK_RXOVERRIE_Msk         (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)   /*!< 0x00000020 */

+#define SDMMC_MASK_RXOVERRIE             SDMMC_MASK_RXOVERRIE_Msk              /*!<Rx FIFO OverRun Error Interrupt Enable     */

+#define SDMMC_MASK_CMDRENDIE_Pos         (6U)

+#define SDMMC_MASK_CMDRENDIE_Msk         (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)   /*!< 0x00000040 */

+#define SDMMC_MASK_CMDRENDIE             SDMMC_MASK_CMDRENDIE_Msk              /*!<Command Response Received Interrupt Enable */

+#define SDMMC_MASK_CMDSENTIE_Pos         (7U)

+#define SDMMC_MASK_CMDSENTIE_Msk         (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)   /*!< 0x00000080 */

+#define SDMMC_MASK_CMDSENTIE             SDMMC_MASK_CMDSENTIE_Msk              /*!<Command Sent Interrupt Enable              */

+#define SDMMC_MASK_DATAENDIE_Pos         (8U)

+#define SDMMC_MASK_DATAENDIE_Msk         (0x1UL << SDMMC_MASK_DATAENDIE_Pos)   /*!< 0x00000100 */

+#define SDMMC_MASK_DATAENDIE             SDMMC_MASK_DATAENDIE_Msk              /*!<Data End Interrupt Enable                  */

+#define SDMMC_MASK_DHOLDIE_Pos           (9U)

+#define SDMMC_MASK_DHOLDIE_Msk           (0x1UL << SDMMC_MASK_DHOLDIE_Pos)     /*!< 0x00000200 */

+#define SDMMC_MASK_DHOLDIE               SDMMC_MASK_DHOLDIE_Msk                /*!<Data Hold Interrupt Enable                 */

+#define SDMMC_MASK_DBCKENDIE_Pos         (10U)

+#define SDMMC_MASK_DBCKENDIE_Msk         (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)   /*!< 0x00000400 */

+#define SDMMC_MASK_DBCKENDIE             SDMMC_MASK_DBCKENDIE_Msk              /*!<Data Block End Interrupt Enable            */

+#define SDMMC_MASK_DABORTIE_Pos          (11U)

+#define SDMMC_MASK_DABORTIE_Msk          (0x1UL << SDMMC_MASK_DABORTIE_Pos)    /*!< 0x00000800 */

+#define SDMMC_MASK_DABORTIE              SDMMC_MASK_DABORTIE_Msk               /*!<Data transfer aborted interrupt enable     */

+

+#define SDMMC_MASK_TXFIFOHEIE_Pos        (14U)

+#define SDMMC_MASK_TXFIFOHEIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)  /*!< 0x00004000 */

+#define SDMMC_MASK_TXFIFOHEIE            SDMMC_MASK_TXFIFOHEIE_Msk             /*!<Tx FIFO Half Empty interrupt Enable        */

+#define SDMMC_MASK_RXFIFOHFIE_Pos        (15U)

+#define SDMMC_MASK_RXFIFOHFIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)  /*!< 0x00008000 */

+#define SDMMC_MASK_RXFIFOHFIE            SDMMC_MASK_RXFIFOHFIE_Msk             /*!<Rx FIFO Half Full interrupt Enable         */

+

+#define SDMMC_MASK_RXFIFOFIE_Pos         (17U)

+#define SDMMC_MASK_RXFIFOFIE_Msk         (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)   /*!< 0x00020000 */

+#define SDMMC_MASK_RXFIFOFIE             SDMMC_MASK_RXFIFOFIE_Msk              /*!<Rx FIFO Full interrupt Enable              */

+#define SDMMC_MASK_TXFIFOEIE_Pos         (18U)

+#define SDMMC_MASK_TXFIFOEIE_Msk         (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)   /*!< 0x00040000 */

+#define SDMMC_MASK_TXFIFOEIE             SDMMC_MASK_TXFIFOEIE_Msk              /*!<Tx FIFO Empty interrupt Enable             */

+

+#define SDMMC_MASK_BUSYD0ENDIE_Pos       (21U)

+#define SDMMC_MASK_BUSYD0ENDIE_Msk       (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */

+#define SDMMC_MASK_BUSYD0ENDIE           SDMMC_MASK_BUSYD0ENDIE_Msk            /*!<BUSYD0ENDIE interrupt Enable */

+#define SDMMC_MASK_SDIOITIE_Pos           (22U)

+#define SDMMC_MASK_SDIOITIE_Msk           (0x1UL << SDMMC_MASK_SDIOITIE_Pos)     /*!< 0x00400000 */

+#define SDMMC_MASK_SDIOITIE               SDMMC_MASK_SDIOITIE_Msk                /*!<SDMMC Mode Interrupt Received interrupt Enable */

+#define SDMMC_MASK_ACKFAILIE_Pos         (23U)

+#define SDMMC_MASK_ACKFAILIE_Msk         (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)   /*!< 0x00800000 */

+#define SDMMC_MASK_ACKFAILIE             SDMMC_MASK_ACKFAILIE_Msk              /*!<Acknowledgment Fail Interrupt Enable */

+#define SDMMC_MASK_ACKTIMEOUTIE_Pos      (24U)

+#define SDMMC_MASK_ACKTIMEOUTIE_Msk      (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */

+#define SDMMC_MASK_ACKTIMEOUTIE          SDMMC_MASK_ACKTIMEOUTIE_Msk           /*!<Acknowledgment timeout Interrupt Enable */

+#define SDMMC_MASK_VSWENDIE_Pos          (25U)

+#define SDMMC_MASK_VSWENDIE_Msk          (0x1UL << SDMMC_MASK_VSWENDIE_Pos)    /*!< 0x02000000 */

+#define SDMMC_MASK_VSWENDIE              SDMMC_MASK_VSWENDIE_Msk               /*!<Voltage switch critical timing section completion Interrupt Enable */

+#define SDMMC_MASK_CKSTOPIE_Pos          (26U)

+#define SDMMC_MASK_CKSTOPIE_Msk          (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)    /*!< 0x04000000 */

+#define SDMMC_MASK_CKSTOPIE              SDMMC_MASK_CKSTOPIE_Msk               /*!<Voltage Switch clock stopped Interrupt Enable */

+#define SDMMC_MASK_IDMABTCIE_Pos         (28U)

+#define SDMMC_MASK_IDMABTCIE_Msk         (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)   /*!< 0x10000000 */

+#define SDMMC_MASK_IDMABTCIE             SDMMC_MASK_IDMABTCIE_Msk              /*!<IDMA buffer transfer complete Interrupt Enable */

+

+/*****************  Bit definition for SDMMC_ACKTIME register  *****************/

+#define SDMMC_ACKTIME_ACKTIME_Pos        (0U)

+#define SDMMC_ACKTIME_ACKTIME_Msk        (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_ACKTIME_ACKTIME            SDMMC_ACKTIME_ACKTIME_Msk             /*!<Boot acknowledgment timeout period */

+

+/******************  Bit definition for SDMMC_FIFO register  *******************/

+#define SDMMC_FIFO_FIFODATA_Pos          (0U)

+#define SDMMC_FIFO_FIFODATA_Msk          (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_FIFO_FIFODATA              SDMMC_FIFO_FIFODATA_Msk               /*!<Receive and transmit FIFO data */

+

+/******************  Bit definition for SDMMC_IDMACTRL register ****************/

+#define SDMMC_IDMA_IDMAEN_Pos            (0U)

+#define SDMMC_IDMA_IDMAEN_Msk            (0x1UL << SDMMC_IDMA_IDMAEN_Pos)      /*!< 0x00000001 */

+#define SDMMC_IDMA_IDMAEN                SDMMC_IDMA_IDMAEN_Msk                 /*!< Enable the internal DMA of the SDMMC peripheral */

+#define SDMMC_IDMA_IDMABMODE_Pos         (1U)

+#define SDMMC_IDMA_IDMABMODE_Msk         (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)   /*!< 0x00000002 */

+#define SDMMC_IDMA_IDMABMODE             SDMMC_IDMA_IDMABMODE_Msk              /*!< Enable double buffer mode for IDMA */

+#define SDMMC_IDMA_IDMABACT_Pos          (2U)

+#define SDMMC_IDMA_IDMABACT_Msk          (0x1UL << SDMMC_IDMA_IDMABACT_Pos)    /*!< 0x00000004 */

+#define SDMMC_IDMA_IDMABACT              SDMMC_IDMA_IDMABACT_Msk               /*!< Uses buffer 1 when double buffer mode is selected */

+

+/*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/

+#define SDMMC_IDMABSIZE_IDMABNDT_Pos     (5U)

+#define SDMMC_IDMABSIZE_IDMABNDT_Msk     (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */

+#define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */

+

+/*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/

+#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */

+

+/*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/

+#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                        Delay Block Interface (DLYB)                        */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for DLYB_CR register  ********************/

+#define DLYB_CR_DEN_Pos         (0U)

+#define DLYB_CR_DEN_Msk         (0x1UL << DLYB_CR_DEN_Pos)                     /*!< 0x00000001 */

+#define DLYB_CR_DEN             DLYB_CR_DEN_Msk                                /*!<Delay Block enable */

+#define DLYB_CR_SEN_Pos         (1U)

+#define DLYB_CR_SEN_Msk         (0x1UL << DLYB_CR_SEN_Pos)                     /*!< 0x00000002 */

+#define DLYB_CR_SEN             DLYB_CR_SEN_Msk                                /*!<Sampler length enable */

+

+

+/*******************  Bit definition for DLYB_CFGR register  ********************/

+#define DLYB_CFGR_SEL_Pos       (0U)

+#define DLYB_CFGR_SEL_Msk       (0xFUL << DLYB_CFGR_SEL_Pos)                   /*!< 0x0000000F */

+#define DLYB_CFGR_SEL           DLYB_CFGR_SEL_Msk                              /*!<Select the phase for the Output clock[3:0] */

+#define DLYB_CFGR_SEL_0         (0x1UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000001 */

+#define DLYB_CFGR_SEL_1         (0x2UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000002 */

+#define DLYB_CFGR_SEL_2         (0x3UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000003 */

+#define DLYB_CFGR_SEL_3         (0x8UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000008 */

+

+#define DLYB_CFGR_UNIT_Pos      (8U)

+#define DLYB_CFGR_UNIT_Msk      (0x7FUL << DLYB_CFGR_UNIT_Pos)                 /*!< 0x00007F00 */

+#define DLYB_CFGR_UNIT          DLYB_CFGR_UNIT_Msk                             /*!<Delay Defines the delay of a Unit delay cell[6:0] */

+#define DLYB_CFGR_UNIT_0        (0x01UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000100 */

+#define DLYB_CFGR_UNIT_1        (0x02UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000200 */

+#define DLYB_CFGR_UNIT_2        (0x04UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000400 */

+#define DLYB_CFGR_UNIT_3        (0x08UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000800 */

+#define DLYB_CFGR_UNIT_4        (0x10UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00001000 */

+#define DLYB_CFGR_UNIT_5        (0x20UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00002000 */

+#define DLYB_CFGR_UNIT_6        (0x40UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00004000 */

+

+#define DLYB_CFGR_LNG_Pos       (16U)

+#define DLYB_CFGR_LNG_Msk       (0xFFFUL << DLYB_CFGR_LNG_Pos)                 /*!< 0x0FFF0000 */

+#define DLYB_CFGR_LNG           DLYB_CFGR_LNG_Msk                              /*!<Delay line length value[11:0] */

+#define DLYB_CFGR_LNG_0         (0x001UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00010000 */

+#define DLYB_CFGR_LNG_1         (0x002UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00020000 */

+#define DLYB_CFGR_LNG_2         (0x004UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00040000 */

+#define DLYB_CFGR_LNG_3         (0x008UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00080000 */

+#define DLYB_CFGR_LNG_4         (0x010UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00100000 */

+#define DLYB_CFGR_LNG_5         (0x020UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00200000 */

+#define DLYB_CFGR_LNG_6         (0x040UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00400000 */

+#define DLYB_CFGR_LNG_7         (0x080UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00800000 */

+#define DLYB_CFGR_LNG_8         (0x100UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x01000000 */

+#define DLYB_CFGR_LNG_9         (0x200UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x02000000 */

+#define DLYB_CFGR_LNG_10        (0x400UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x04000000 */

+#define DLYB_CFGR_LNG_11        (0x800UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x08000000 */

+

+#define DLYB_CFGR_LNGF_Pos      (31U)

+#define DLYB_CFGR_LNGF_Msk      (0x1UL << DLYB_CFGR_LNGF_Pos)                  /*!< 0x80000000 */

+#define DLYB_CFGR_LNGF          DLYB_CFGR_LNGF_Msk                             /*!<Length valid flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                   Serial Peripheral Interface (SPI/I2S)                    */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for SPI_CR1 register  ********************/

+#define SPI_CR1_SPE_Pos             (0U)

+#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000001 */

+#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<Serial Peripheral Enable                         */

+#define SPI_CR1_MASRX_Pos           (8U)

+#define SPI_CR1_MASRX_Msk           (0x1UL << SPI_CR1_MASRX_Pos)               /*!< 0x00000100 */

+#define SPI_CR1_MASRX               SPI_CR1_MASRX_Msk                          /*!<Master automatic SUSP in Receive mode            */

+#define SPI_CR1_CSTART_Pos          (9U)

+#define SPI_CR1_CSTART_Msk          (0x1UL << SPI_CR1_CSTART_Pos)              /*!< 0x00000200 */

+#define SPI_CR1_CSTART              SPI_CR1_CSTART_Msk                         /*!<Master transfer start                            */

+#define SPI_CR1_CSUSP_Pos           (10U)

+#define SPI_CR1_CSUSP_Msk           (0x1UL << SPI_CR1_CSUSP_Pos)               /*!< 0x00000400 */

+#define SPI_CR1_CSUSP               SPI_CR1_CSUSP_Msk                          /*!<Master SUSPend request                           */

+#define SPI_CR1_HDDIR_Pos           (11U)

+#define SPI_CR1_HDDIR_Msk           (0x1UL << SPI_CR1_HDDIR_Pos)               /*!< 0x00000800 */

+#define SPI_CR1_HDDIR               SPI_CR1_HDDIR_Msk                          /*!<Rx/Tx direction at Half-duplex mode              */

+#define SPI_CR1_SSI_Pos             (12U)

+#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00001000 */

+#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal SS signal input level                   */

+#define SPI_CR1_CRC33_17_Pos        (13U)

+#define SPI_CR1_CRC33_17_Msk        (0x1UL << SPI_CR1_CRC33_17_Pos)            /*!< 0x00002000 */

+#define SPI_CR1_CRC33_17             SPI_CR1_CRC33_17_Msk                      /*!<32-bit CRC polynomial configuration              */

+#define SPI_CR1_RCRCINI_Pos         (14U)

+#define SPI_CR1_RCRCINI_Msk         (0x1UL << SPI_CR1_RCRCINI_Pos)             /*!< 0x00004000 */

+#define SPI_CR1_RCRCINI             SPI_CR1_RCRCINI_Msk                        /*!<CRC init pattern control for receiver            */

+#define SPI_CR1_TCRCINI_Pos         (15U)

+#define SPI_CR1_TCRCINI_Msk         (0x1UL << SPI_CR1_TCRCINI_Pos)             /*!< 0x00008000 */

+#define SPI_CR1_TCRCINI             SPI_CR1_TCRCINI_Msk                        /*!<CRC init pattern control for transmitter         */

+#define SPI_CR1_IOLOCK_Pos          (16U)

+#define SPI_CR1_IOLOCK_Msk          (0x1UL << SPI_CR1_IOLOCK_Pos)              /*!< 0x00010000 */

+#define SPI_CR1_IOLOCK              SPI_CR1_IOLOCK_Msk                         /*!<Locking the AF configuration of associated IOs   */

+

+/*******************  Bit definition for SPI_CR2 register  ********************/

+#define SPI_CR2_TSER_Pos            (16U)

+#define SPI_CR2_TSER_Msk            (0xFFFFUL << SPI_CR2_TSER_Pos)             /*!< 0xFFFF0000 */

+#define SPI_CR2_TSER                SPI_CR2_TSER_Msk                           /*!<Number of data transfer extension                */

+#define SPI_CR2_TSIZE_Pos           (0U)

+#define SPI_CR2_TSIZE_Msk           (0xFFFFUL << SPI_CR2_TSIZE_Pos)            /*!< 0x0000FFFF */

+#define SPI_CR2_TSIZE               SPI_CR2_TSIZE_Msk                          /*!<Number of data at current transfer               */

+

+/*******************  Bit definition for SPI_CFG1 register  ********************/

+#define SPI_CFG1_DSIZE_Pos          (0U)

+#define SPI_CFG1_DSIZE_Msk          (0x1FUL << SPI_CFG1_DSIZE_Pos)             /*!< 0x0000001F */

+#define SPI_CFG1_DSIZE              SPI_CFG1_DSIZE_Msk                         /*!<DSIZE[4:0]: Bits number in single SPI data frame */

+#define SPI_CFG1_DSIZE_0            (0x01UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000001 */

+#define SPI_CFG1_DSIZE_1            (0x02UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000002 */

+#define SPI_CFG1_DSIZE_2            (0x04UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000004 */

+#define SPI_CFG1_DSIZE_3            (0x08UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000008 */

+#define SPI_CFG1_DSIZE_4            (0x10UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000010 */

+

+#define SPI_CFG1_FTHLV_Pos          (5U)

+#define SPI_CFG1_FTHLV_Msk          (0xFUL << SPI_CFG1_FTHLV_Pos)              /*!< 0x000001E0 */

+#define SPI_CFG1_FTHLV              SPI_CFG1_FTHLV_Msk                         /*!<FTHVL [3:0]: FIFO threshold level*/

+#define SPI_CFG1_FTHLV_0            (0x1UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000020 */

+#define SPI_CFG1_FTHLV_1            (0x2UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000040 */

+#define SPI_CFG1_FTHLV_2            (0x4UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000080 */

+#define SPI_CFG1_FTHLV_3            (0x8UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000100 */

+

+#define SPI_CFG1_UDRCFG_Pos         (9U)

+#define SPI_CFG1_UDRCFG_Msk         (0x3UL << SPI_CFG1_UDRCFG_Pos)             /*!< 0x00000600 */

+#define SPI_CFG1_UDRCFG             SPI_CFG1_UDRCFG_Msk                        /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */

+#define SPI_CFG1_UDRCFG_0           (0x1UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000200 */

+#define SPI_CFG1_UDRCFG_1           (0x2UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000400 */

+

+

+#define SPI_CFG1_UDRDET_Pos         (11U)

+#define SPI_CFG1_UDRDET_Msk         (0x3UL << SPI_CFG1_UDRDET_Pos)             /*!< 0x00001800 */

+#define SPI_CFG1_UDRDET             SPI_CFG1_UDRDET_Msk                        /*!<UDRDET[1:0]: Detection of underrun condition     */

+#define SPI_CFG1_UDRDET_0           (0x1UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00000800 */

+#define SPI_CFG1_UDRDET_1           (0x2UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00001000 */

+

+#define SPI_CFG1_RXDMAEN_Pos        (14U)

+#define SPI_CFG1_RXDMAEN_Msk        (0x1UL << SPI_CFG1_RXDMAEN_Pos)            /*!< 0x00004000 */

+#define SPI_CFG1_RXDMAEN            SPI_CFG1_RXDMAEN_Msk                       /*!<Rx DMA stream enable                */

+#define SPI_CFG1_TXDMAEN_Pos        (15U)

+#define SPI_CFG1_TXDMAEN_Msk        (0x1UL << SPI_CFG1_TXDMAEN_Pos)            /*!< 0x00008000 */

+#define SPI_CFG1_TXDMAEN            SPI_CFG1_TXDMAEN_Msk                       /*!<Tx DMA stream enable                */

+

+#define SPI_CFG1_CRCSIZE_Pos        (16U)

+#define SPI_CFG1_CRCSIZE_Msk        (0x1FUL << SPI_CFG1_CRCSIZE_Pos)           /*!< 0x001F0000 */

+#define SPI_CFG1_CRCSIZE            SPI_CFG1_CRCSIZE_Msk                       /*!<CRCSIZE [4:0]: Length of CRC frame*/

+#define SPI_CFG1_CRCSIZE_0          (0x01UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00010000 */

+#define SPI_CFG1_CRCSIZE_1          (0x02UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00020000 */

+#define SPI_CFG1_CRCSIZE_2          (0x04UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00040000 */

+#define SPI_CFG1_CRCSIZE_3          (0x08UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00080000 */

+#define SPI_CFG1_CRCSIZE_4          (0x10UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00100000 */

+

+#define SPI_CFG1_CRCEN_Pos          (22U)

+#define SPI_CFG1_CRCEN_Msk          (0x1UL << SPI_CFG1_CRCEN_Pos)              /*!< 0x00400000 */

+#define SPI_CFG1_CRCEN              SPI_CFG1_CRCEN_Msk                         /*!<Hardware CRC computation enable */

+

+#define SPI_CFG1_MBR_Pos            (28U)

+#define SPI_CFG1_MBR_Msk            (0x7UL << SPI_CFG1_MBR_Pos)                /*!< 0x70000000 */

+#define SPI_CFG1_MBR                SPI_CFG1_MBR_Msk                           /*!<Master baud rate                */

+#define SPI_CFG1_MBR_0              (0x1UL << SPI_CFG1_MBR_Pos)                 /*!< 0x10000000 */

+#define SPI_CFG1_MBR_1              (0x2UL << SPI_CFG1_MBR_Pos)                 /*!< 0x20000000 */

+#define SPI_CFG1_MBR_2              (0x4UL << SPI_CFG1_MBR_Pos)                 /*!< 0x40000000 */

+

+/*******************  Bit definition for SPI_CFG2 register  ********************/

+#define SPI_CFG2_MSSI_Pos           (0U)

+#define SPI_CFG2_MSSI_Msk           (0xFUL << SPI_CFG2_MSSI_Pos)               /*!< 0x0000000F */

+#define SPI_CFG2_MSSI               SPI_CFG2_MSSI_Msk                          /*!<Master SS Idleness */

+#define SPI_CFG2_MSSI_0             (0x1UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000001 */

+#define SPI_CFG2_MSSI_1             (0x2UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000002 */

+#define SPI_CFG2_MSSI_2             (0x4UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000004 */

+#define SPI_CFG2_MSSI_3             (0x8UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000008 */

+

+#define SPI_CFG2_MIDI_Pos           (4U)

+#define SPI_CFG2_MIDI_Msk           (0xFUL << SPI_CFG2_MIDI_Pos)               /*!< 0x000000F0 */

+#define SPI_CFG2_MIDI               SPI_CFG2_MIDI_Msk                          /*!<Master Inter-Data Idleness */

+#define SPI_CFG2_MIDI_0             (0x1UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000010 */

+#define SPI_CFG2_MIDI_1             (0x2UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000020 */

+#define SPI_CFG2_MIDI_2             (0x4UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000040 */

+#define SPI_CFG2_MIDI_3             (0x8UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000080 */

+

+#define SPI_CFG2_IOSWP_Pos          (15U)

+#define SPI_CFG2_IOSWP_Msk          (0x1UL << SPI_CFG2_IOSWP_Pos)              /*!< 0x00008000 */

+#define SPI_CFG2_IOSWP              SPI_CFG2_IOSWP_Msk                         /*!<Swap functionality of MISO and MOSI pins */

+

+#define SPI_CFG2_COMM_Pos           (17U)

+#define SPI_CFG2_COMM_Msk           (0x3UL << SPI_CFG2_COMM_Pos)               /*!< 0x00060000 */

+#define SPI_CFG2_COMM               SPI_CFG2_COMM_Msk                          /*!<COMM [1:0]: SPI Communication Mode*/

+#define SPI_CFG2_COMM_0             (0x1UL << SPI_CFG2_COMM_Pos)                /*!< 0x00020000 */

+#define SPI_CFG2_COMM_1             (0x2UL << SPI_CFG2_COMM_Pos)                /*!< 0x00040000 */

+

+#define SPI_CFG2_SP_Pos             (19U)

+#define SPI_CFG2_SP_Msk             (0x7UL << SPI_CFG2_SP_Pos)                 /*!< 0x00380000 */

+#define SPI_CFG2_SP                 SPI_CFG2_SP_Msk                            /*!<SP[2:0]: Serial Protocol */

+#define SPI_CFG2_SP_0               (0x1UL << SPI_CFG2_SP_Pos)                  /*!< 0x00080000 */

+#define SPI_CFG2_SP_1               (0x2UL << SPI_CFG2_SP_Pos)                  /*!< 0x00100000 */

+#define SPI_CFG2_SP_2               (0x4UL << SPI_CFG2_SP_Pos)                  /*!< 0x00200000 */

+

+#define SPI_CFG2_MASTER_Pos         (22U)

+#define SPI_CFG2_MASTER_Msk         (0x1UL << SPI_CFG2_MASTER_Pos)             /*!< 0x00400000 */

+#define SPI_CFG2_MASTER             SPI_CFG2_MASTER_Msk                        /*!<SPI Master           */

+#define SPI_CFG2_LSBFRST_Pos        (23U)

+#define SPI_CFG2_LSBFRST_Msk        (0x1UL << SPI_CFG2_LSBFRST_Pos)            /*!< 0x00800000 */

+#define SPI_CFG2_LSBFRST            SPI_CFG2_LSBFRST_Msk                       /*!<Data frame format               */

+#define SPI_CFG2_CPHA_Pos           (24U)

+#define SPI_CFG2_CPHA_Msk           (0x1UL << SPI_CFG2_CPHA_Pos)               /*!< 0x01000000 */

+#define SPI_CFG2_CPHA               SPI_CFG2_CPHA_Msk                          /*!<Clock Phase      */

+#define SPI_CFG2_CPOL_Pos           (25U)

+#define SPI_CFG2_CPOL_Msk           (0x1UL << SPI_CFG2_CPOL_Pos)               /*!< 0x02000000 */

+#define SPI_CFG2_CPOL               SPI_CFG2_CPOL_Msk                          /*!<Clock Polarity   */

+#define SPI_CFG2_SSM_Pos            (26U)

+#define SPI_CFG2_SSM_Msk            (0x1UL << SPI_CFG2_SSM_Pos)                /*!< 0x04000000 */

+#define SPI_CFG2_SSM                SPI_CFG2_SSM_Msk                           /*!<Software slave management */

+

+#define SPI_CFG2_SSIOP_Pos          (28U)

+#define SPI_CFG2_SSIOP_Msk          (0x1UL << SPI_CFG2_SSIOP_Pos)              /*!< 0x10000000 */

+#define SPI_CFG2_SSIOP              SPI_CFG2_SSIOP_Msk                         /*!<SS input/output polarity */

+#define SPI_CFG2_SSOE_Pos           (29U)

+#define SPI_CFG2_SSOE_Msk           (0x1UL << SPI_CFG2_SSOE_Pos)               /*!< 0x20000000 */

+#define SPI_CFG2_SSOE               SPI_CFG2_SSOE_Msk                          /*!<SS output enable */

+#define SPI_CFG2_SSOM_Pos           (30U)

+#define SPI_CFG2_SSOM_Msk           (0x1UL << SPI_CFG2_SSOM_Pos)               /*!< 0x40000000 */

+#define SPI_CFG2_SSOM               SPI_CFG2_SSOM_Msk                          /*!<SS output management in master mode */

+

+#define SPI_CFG2_AFCNTR_Pos         (31U)

+#define SPI_CFG2_AFCNTR_Msk         (0x1UL << SPI_CFG2_AFCNTR_Pos)             /*!< 0x80000000 */

+#define SPI_CFG2_AFCNTR             SPI_CFG2_AFCNTR_Msk                        /*!<Alternate function GPIOs control */

+

+/*******************  Bit definition for SPI_IER register  ********************/

+#define SPI_IER_RXPIE_Pos           (0U)

+#define SPI_IER_RXPIE_Msk           (0x1UL << SPI_IER_RXPIE_Pos)               /*!< 0x00000001 */

+#define SPI_IER_RXPIE               SPI_IER_RXPIE_Msk                          /*!<RXP Interrupt Enable            */

+#define SPI_IER_TXPIE_Pos           (1U)

+#define SPI_IER_TXPIE_Msk           (0x1UL << SPI_IER_TXPIE_Pos)               /*!< 0x00000002 */

+#define SPI_IER_TXPIE               SPI_IER_TXPIE_Msk                          /*!<TXP interrupt enable            */

+#define SPI_IER_DXPIE_Pos           (2U)

+#define SPI_IER_DXPIE_Msk           (0x1UL << SPI_IER_DXPIE_Pos)               /*!< 0x00000004 */

+#define SPI_IER_DXPIE               SPI_IER_DXPIE_Msk                          /*!<DXP interrupt enable            */

+#define SPI_IER_EOTIE_Pos           (3U)

+#define SPI_IER_EOTIE_Msk           (0x1UL << SPI_IER_EOTIE_Pos)               /*!< 0x00000008 */

+#define SPI_IER_EOTIE               SPI_IER_EOTIE_Msk                          /*!<EOT/SUSP/TXC interrupt enable   */

+#define SPI_IER_TXTFIE_Pos          (4U)

+#define SPI_IER_TXTFIE_Msk          (0x1UL << SPI_IER_TXTFIE_Pos)              /*!< 0x00000010 */

+#define SPI_IER_TXTFIE              SPI_IER_TXTFIE_Msk                         /*!<TXTF interrupt enable           */

+#define SPI_IER_UDRIE_Pos           (5U)

+#define SPI_IER_UDRIE_Msk           (0x1UL << SPI_IER_UDRIE_Pos)               /*!< 0x00000020 */

+#define SPI_IER_UDRIE               SPI_IER_UDRIE_Msk                          /*!<UDR interrupt enable            */

+#define SPI_IER_OVRIE_Pos           (6U)

+#define SPI_IER_OVRIE_Msk           (0x1UL << SPI_IER_OVRIE_Pos)               /*!< 0x00000040 */

+#define SPI_IER_OVRIE               SPI_IER_OVRIE_Msk                          /*!<OVR interrupt enable            */

+#define SPI_IER_CRCEIE_Pos          (7U)

+#define SPI_IER_CRCEIE_Msk          (0x1UL << SPI_IER_CRCEIE_Pos)               /*!< 0x00000080 */

+#define SPI_IER_CRCEIE              SPI_IER_CRCEIE_Msk                          /*!<CRCE interrupt enable           */

+#define SPI_IER_TIFREIE_Pos         (8U)

+#define SPI_IER_TIFREIE_Msk         (0x1UL << SPI_IER_TIFREIE_Pos)             /*!< 0x00000100 */

+#define SPI_IER_TIFREIE             SPI_IER_TIFREIE_Msk                        /*!<TI Frame Error interrupt enable */

+#define SPI_IER_MODFIE_Pos          (9U)

+#define SPI_IER_MODFIE_Msk          (0x1UL << SPI_IER_MODFIE_Pos)              /*!< 0x00000200 */

+#define SPI_IER_MODFIE              SPI_IER_MODFIE_Msk                         /*!<MODF interrupt enable           */

+#define SPI_IER_TSERFIE_Pos         (10U)

+#define SPI_IER_TSERFIE_Msk         (0x1UL << SPI_IER_TSERFIE_Pos)              /*!< 0x00000400 */

+#define SPI_IER_TSERFIE             SPI_IER_TSERFIE_Msk                        /*!<TSERF interrupt enable          */

+

+/*******************  Bit definition for SPI_SR register  ********************/

+#define SPI_SR_RXP_Pos              (0U)

+#define SPI_SR_RXP_Msk              (0x1UL << SPI_SR_RXP_Pos)                  /*!< 0x00000001 */

+#define SPI_SR_RXP                  SPI_SR_RXP_Msk                             /*!<Rx-Packet available             */

+#define SPI_SR_TXP_Pos              (1U)

+#define SPI_SR_TXP_Msk              (0x1UL << SPI_SR_TXP_Pos)                  /*!< 0x00000002 */

+#define SPI_SR_TXP                  SPI_SR_TXP_Msk                             /*!<Tx-Packet space available       */

+#define SPI_SR_DXP_Pos              (2U)

+#define SPI_SR_DXP_Msk              (0x1UL << SPI_SR_DXP_Pos)                  /*!< 0x00000004 */

+#define SPI_SR_DXP                  SPI_SR_DXP_Msk                             /*!<Duplex Packet available         */

+#define SPI_SR_EOT_Pos              (3U)

+#define SPI_SR_EOT_Msk              (0x1UL << SPI_SR_EOT_Pos)                  /*!< 0x00000008 */

+#define SPI_SR_EOT                  SPI_SR_EOT_Msk                             /*!<Duplex Packet available         */

+#define SPI_SR_TXTF_Pos             (4U)

+#define SPI_SR_TXTF_Msk             (0x1UL << SPI_SR_TXTF_Pos)                 /*!< 0x00000010 */

+#define SPI_SR_TXTF                 SPI_SR_TXTF_Msk                            /*!<Transmission Transfer Filled    */

+#define SPI_SR_UDR_Pos              (5U)

+#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000020 */

+#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<UDR at Slave transmission       */

+#define SPI_SR_OVR_Pos              (6U)

+#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */

+#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Rx-Packet available             */

+#define SPI_SR_CRCE_Pos             (7U)

+#define SPI_SR_CRCE_Msk             (0x1UL << SPI_SR_CRCE_Pos)                 /*!< 0x00000080 */

+#define SPI_SR_CRCE                 SPI_SR_CRCE_Msk                            /*!<CRC Error Detected              */

+#define SPI_SR_TIFRE_Pos            (8U)

+#define SPI_SR_TIFRE_Msk            (0x1UL << SPI_SR_TIFRE_Pos)                /*!< 0x00000100 */

+#define SPI_SR_TIFRE                SPI_SR_TIFRE_Msk                           /*!<TI frame format error Detected  */

+#define SPI_SR_MODF_Pos             (9U)

+#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000200 */

+#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode Fault Detected             */

+#define SPI_SR_TSERF_Pos            (10U)

+#define SPI_SR_TSERF_Msk            (0x1UL << SPI_SR_TSERF_Pos)                /*!< 0x00000400 */

+#define SPI_SR_TSERF                SPI_SR_TSERF_Msk                           /*!<Number of SPI data to be transacted reloaded     */

+#define SPI_SR_SUSP_Pos             (11U)

+#define SPI_SR_SUSP_Msk             (0x1UL << SPI_SR_SUSP_Pos)                 /*!< 0x00000800 */

+#define SPI_SR_SUSP                 SPI_SR_SUSP_Msk                            /*!<SUSP is set by hardware  */

+#define SPI_SR_TXC_Pos              (12U)

+#define SPI_SR_TXC_Msk              (0x1UL << SPI_SR_TXC_Pos)                  /*!< 0x00001000 */

+#define SPI_SR_TXC                  SPI_SR_TXC_Msk                             /*!<TxFIFO transmission complete */

+#define SPI_SR_RXPLVL_Pos           (13U)

+#define SPI_SR_RXPLVL_Msk           (0x3UL << SPI_SR_RXPLVL_Pos)               /*!< 0x00006000 */

+#define SPI_SR_RXPLVL               SPI_SR_RXPLVL_Msk                          /*!<RxFIFO Packing Level                             */

+#define SPI_SR_RXPLVL_0             (0x1UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00002000 */

+#define SPI_SR_RXPLVL_1             (0x2UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00004000 */

+#define SPI_SR_RXWNE_Pos            (15U)

+#define SPI_SR_RXWNE_Msk            (0x1UL << SPI_SR_RXWNE_Pos)                /*!< 0x00008000 */

+#define SPI_SR_RXWNE                SPI_SR_RXWNE_Msk                           /*!<Rx FIFO Word Not Empty                           */

+#define SPI_SR_CTSIZE_Pos           (16U)

+#define SPI_SR_CTSIZE_Msk           (0xFFFFUL << SPI_SR_CTSIZE_Pos)            /*!< 0xFFFF0000 */

+#define SPI_SR_CTSIZE               SPI_SR_CTSIZE_Msk                          /*!<Number of data frames remaining in TSIZE         */

+

+/*******************  Bit definition for SPI_IFCR register  ********************/

+#define SPI_IFCR_EOTC_Pos           (3U)

+#define SPI_IFCR_EOTC_Msk           (0x1UL << SPI_IFCR_EOTC_Pos)               /*!< 0x00000008 */

+#define SPI_IFCR_EOTC               SPI_IFCR_EOTC_Msk                          /*!<End Of Transfer flag clear              */

+#define SPI_IFCR_TXTFC_Pos          (4U)

+#define SPI_IFCR_TXTFC_Msk          (0x1UL << SPI_IFCR_TXTFC_Pos)              /*!< 0x00000010 */

+#define SPI_IFCR_TXTFC              SPI_IFCR_TXTFC_Msk                         /*!<Transmission Transfer Filled flag clear */

+#define SPI_IFCR_UDRC_Pos           (5U)

+#define SPI_IFCR_UDRC_Msk           (0x1UL << SPI_IFCR_UDRC_Pos)               /*!< 0x00000020 */

+#define SPI_IFCR_UDRC               SPI_IFCR_UDRC_Msk                          /*!<Underrun flag clear                     */

+#define SPI_IFCR_OVRC_Pos           (6U)

+#define SPI_IFCR_OVRC_Msk           (0x1UL << SPI_IFCR_OVRC_Pos)               /*!< 0x00000040 */

+#define SPI_IFCR_OVRC               SPI_IFCR_OVRC_Msk                          /*!<Overrun flag clear                      */

+#define SPI_IFCR_CRCEC_Pos          (7U)

+#define SPI_IFCR_CRCEC_Msk          (0x1UL << SPI_IFCR_CRCEC_Pos)              /*!< 0x00000080 */

+#define SPI_IFCR_CRCEC              SPI_IFCR_CRCEC_Msk                         /*!<CRC Error flag clear                    */

+#define SPI_IFCR_TIFREC_Pos         (8U)

+#define SPI_IFCR_TIFREC_Msk         (0x1UL << SPI_IFCR_TIFREC_Pos)             /*!< 0x00000100 */

+#define SPI_IFCR_TIFREC             SPI_IFCR_TIFREC_Msk                        /*!<TI frame format error flag clear        */

+#define SPI_IFCR_MODFC_Pos          (9U)

+#define SPI_IFCR_MODFC_Msk          (0x1UL << SPI_IFCR_MODFC_Pos)              /*!< 0x00000200 */

+#define SPI_IFCR_MODFC              SPI_IFCR_MODFC_Msk                         /*!<Mode Fault flag clear                   */

+#define SPI_IFCR_TSERFC_Pos         (10U)

+#define SPI_IFCR_TSERFC_Msk         (0x1UL << SPI_IFCR_TSERFC_Pos)             /*!< 0x00000400 */

+#define SPI_IFCR_TSERFC             SPI_IFCR_TSERFC_Msk                        /*!<TSERFC flag clear                       */

+#define SPI_IFCR_SUSPC_Pos          (11U)

+#define SPI_IFCR_SUSPC_Msk          (0x1UL << SPI_IFCR_SUSPC_Pos)              /*!< 0x00000800 */

+#define SPI_IFCR_SUSPC              SPI_IFCR_SUSPC_Msk                         /*!<SUSPend flag clear                      */

+

+/*******************  Bit definition for SPI_TXDR register  ********************/

+#define SPI_TXDR_TXDR_Pos           (0U)

+#define SPI_TXDR_TXDR_Msk           (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)        /*!< 0xFFFFFFFF */

+#define SPI_TXDR_TXDR               SPI_TXDR_TXDR_Msk                          /* Transmit Data Register */

+

+/*******************  Bit definition for SPI_RXDR register  ********************/

+#define SPI_RXDR_RXDR_Pos           (0U)

+#define SPI_RXDR_RXDR_Msk           (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)        /*!< 0xFFFFFFFF */

+#define SPI_RXDR_RXDR               SPI_RXDR_RXDR_Msk                          /* Receive Data Register  */

+

+/*******************  Bit definition for SPI_CRCPOLY register  ********************/

+#define SPI_CRCPOLY_CRCPOLY_Pos     (0U)

+#define SPI_CRCPOLY_CRCPOLY_Msk     (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)  /*!< 0xFFFFFFFF */

+#define SPI_CRCPOLY_CRCPOLY         SPI_CRCPOLY_CRCPOLY_Msk                    /* CRC Polynomial register  */

+

+/*******************  Bit definition for SPI_TXCRC register  ********************/

+#define SPI_TXCRC_TXCRC_Pos         (0U)

+#define SPI_TXCRC_TXCRC_Msk         (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_TXCRC_TXCRC             SPI_TXCRC_TXCRC_Msk                        /* CRCRegister for transmitter */

+

+/*******************  Bit definition for SPI_RXCRC register  ********************/

+#define SPI_RXCRC_RXCRC_Pos         (0U)

+#define SPI_RXCRC_RXCRC_Msk         (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_RXCRC_RXCRC             SPI_RXCRC_RXCRC_Msk                        /* CRCRegister for receiver */

+

+/*******************  Bit definition for SPI_UDRDR register  ********************/

+#define SPI_UDRDR_UDRDR_Pos         (0U)

+#define SPI_UDRDR_UDRDR_Msk         (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_UDRDR_UDRDR             SPI_UDRDR_UDRDR_Msk                        /* Data at slave underrun condition */

+

+/******************  Bit definition for SPI_I2SCFGR register  *****************/

+#define SPI_I2SCFGR_I2SMOD_Pos      (0U)

+#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000001 */

+#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */

+#define SPI_I2SCFGR_I2SCFG_Pos      (1U)

+#define SPI_I2SCFGR_I2SCFG_Msk      (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x0000000E */

+#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[2:0] I2S configuration mode                */

+#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000002 */

+#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000004 */

+#define SPI_I2SCFGR_I2SCFG_2        (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000008 */

+#define SPI_I2SCFGR_I2SSTD_Pos      (4U)

+#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */

+#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] I2S standard selection                */

+#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */

+#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */

+#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)

+#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */

+#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                         */

+#define SPI_I2SCFGR_DATLEN_Pos      (8U)

+#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000300 */

+#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] Data length to be transferred         */

+#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000100 */

+#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000200 */

+#define SPI_I2SCFGR_CHLEN_Pos       (10U)

+#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000400 */

+#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */

+#define SPI_I2SCFGR_CKPOL_Pos       (11U)

+#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000800 */

+#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<Steady state clock polarity                       */

+#define SPI_I2SCFGR_FIXCH_Pos       (12U)

+#define SPI_I2SCFGR_FIXCH_Msk       (0x1UL << SPI_I2SCFGR_FIXCH_Pos)           /*!< 0x00001000 */

+#define SPI_I2SCFGR_FIXCH           SPI_I2SCFGR_FIXCH_Msk                      /*!<Fixed channel length in SLAVE                     */

+#define SPI_I2SCFGR_WSINV_Pos       (13U)

+#define SPI_I2SCFGR_WSINV_Msk       (0x1UL << SPI_I2SCFGR_WSINV_Pos)           /*!< 0x00002000 */

+#define SPI_I2SCFGR_WSINV           SPI_I2SCFGR_WSINV_Msk                      /*!<Word select inversion                             */

+#define SPI_I2SCFGR_DATFMT_Pos      (14U)

+#define SPI_I2SCFGR_DATFMT_Msk      (0x1UL << SPI_I2SCFGR_DATFMT_Pos)          /*!< 0x00004000 */

+#define SPI_I2SCFGR_DATFMT          SPI_I2SCFGR_DATFMT_Msk                     /*!<Data format                                       */

+#define SPI_I2SCFGR_I2SDIV_Pos      (16U)

+#define SPI_I2SCFGR_I2SDIV_Msk      (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)         /*!< 0x00FF0000 */

+#define SPI_I2SCFGR_I2SDIV          SPI_I2SCFGR_I2SDIV_Msk                     /*!<I2S Linear prescaler */

+#define SPI_I2SCFGR_ODD_Pos         (24U)

+#define SPI_I2SCFGR_ODD_Msk         (0x1UL << SPI_I2SCFGR_ODD_Pos)             /*!< 0x01000000 */

+#define SPI_I2SCFGR_ODD             SPI_I2SCFGR_ODD_Msk                        /*!<Odd factor for the prescaler */

+#define SPI_I2SCFGR_MCKOE_Pos       (25U)

+#define SPI_I2SCFGR_MCKOE_Msk       (0x1UL << SPI_I2SCFGR_MCKOE_Pos)           /*!< 0x02000000 */

+#define SPI_I2SCFGR_MCKOE           SPI_I2SCFGR_MCKOE_Msk                      /*!<Master Clock Output Enable */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    QUADSPI                                 */

+/*                                                                            */

+/******************************************************************************/

+/*****************  Bit definition for QUADSPI_CR register  *******************/

+#define QUADSPI_CR_EN_Pos                (0U)

+#define QUADSPI_CR_EN_Msk                (0x1UL << QUADSPI_CR_EN_Pos)          /*!< 0x00000001 */

+#define QUADSPI_CR_EN                    QUADSPI_CR_EN_Msk                     /*!< Enable */

+#define QUADSPI_CR_ABORT_Pos             (1U)

+#define QUADSPI_CR_ABORT_Msk             (0x1UL << QUADSPI_CR_ABORT_Pos)       /*!< 0x00000002 */

+#define QUADSPI_CR_ABORT                 QUADSPI_CR_ABORT_Msk                  /*!< Abort request */

+#define QUADSPI_CR_DMAEN_Pos             (2U)

+#define QUADSPI_CR_DMAEN_Msk             (0x1UL << QUADSPI_CR_DMAEN_Pos)       /*!< 0x00000004 */

+#define QUADSPI_CR_DMAEN                 QUADSPI_CR_DMAEN_Msk                  /*!< DMA Enable */

+#define QUADSPI_CR_TCEN_Pos              (3U)

+#define QUADSPI_CR_TCEN_Msk              (0x1UL << QUADSPI_CR_TCEN_Pos)        /*!< 0x00000008 */

+#define QUADSPI_CR_TCEN                  QUADSPI_CR_TCEN_Msk                   /*!< Timeout Counter Enable */

+#define QUADSPI_CR_SSHIFT_Pos            (4U)

+#define QUADSPI_CR_SSHIFT_Msk            (0x1UL << QUADSPI_CR_SSHIFT_Pos)      /*!< 0x00000010 */

+#define QUADSPI_CR_SSHIFT                QUADSPI_CR_SSHIFT_Msk                 /*!< SSHIFT Sample Shift */

+#define QUADSPI_CR_DFM_Pos               (6U)

+#define QUADSPI_CR_DFM_Msk               (0x1UL << QUADSPI_CR_DFM_Pos)         /*!< 0x00000040 */

+#define QUADSPI_CR_DFM                   QUADSPI_CR_DFM_Msk                    /*!< Dual Flash Mode */

+#define QUADSPI_CR_FSEL_Pos              (7U)

+#define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)        /*!< 0x00000080 */

+#define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select */

+#define QUADSPI_CR_FTHRES_Pos            (8U)

+#define QUADSPI_CR_FTHRES_Msk            (0xFUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000F00 */

+#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level */

+#define QUADSPI_CR_FTHRES_0              (0x1UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */

+#define QUADSPI_CR_FTHRES_1              (0x2UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */

+#define QUADSPI_CR_FTHRES_2              (0x4UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */

+#define QUADSPI_CR_FTHRES_3              (0x8UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */

+#define QUADSPI_CR_TEIE_Pos              (16U)

+#define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)        /*!< 0x00010000 */

+#define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable */

+#define QUADSPI_CR_TCIE_Pos              (17U)

+#define QUADSPI_CR_TCIE_Msk              (0x1UL << QUADSPI_CR_TCIE_Pos)        /*!< 0x00020000 */

+#define QUADSPI_CR_TCIE                  QUADSPI_CR_TCIE_Msk                   /*!< Transfer Complete Interrupt Enable */

+#define QUADSPI_CR_FTIE_Pos              (18U)

+#define QUADSPI_CR_FTIE_Msk              (0x1UL << QUADSPI_CR_FTIE_Pos)        /*!< 0x00040000 */

+#define QUADSPI_CR_FTIE                  QUADSPI_CR_FTIE_Msk                   /*!< FIFO Threshold Interrupt Enable */

+#define QUADSPI_CR_SMIE_Pos              (19U)

+#define QUADSPI_CR_SMIE_Msk              (0x1UL << QUADSPI_CR_SMIE_Pos)        /*!< 0x00080000 */

+#define QUADSPI_CR_SMIE                  QUADSPI_CR_SMIE_Msk                   /*!< Status Match Interrupt Enable */

+#define QUADSPI_CR_TOIE_Pos              (20U)

+#define QUADSPI_CR_TOIE_Msk              (0x1UL << QUADSPI_CR_TOIE_Pos)        /*!< 0x00100000 */

+#define QUADSPI_CR_TOIE                  QUADSPI_CR_TOIE_Msk                   /*!< TimeOut Interrupt Enable */

+#define QUADSPI_CR_APMS_Pos              (22U)

+#define QUADSPI_CR_APMS_Msk              (0x1UL << QUADSPI_CR_APMS_Pos)        /*!< 0x00400000 */

+#define QUADSPI_CR_APMS                  QUADSPI_CR_APMS_Msk                   /*!< Bit 1 */

+#define QUADSPI_CR_PMM_Pos               (23U)

+#define QUADSPI_CR_PMM_Msk               (0x1UL << QUADSPI_CR_PMM_Pos)         /*!< 0x00800000 */

+#define QUADSPI_CR_PMM                   QUADSPI_CR_PMM_Msk                    /*!< Polling Match Mode */

+#define QUADSPI_CR_PRESCALER_Pos         (24U)

+#define QUADSPI_CR_PRESCALER_Msk         (0xFFUL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0xFF000000 */

+#define QUADSPI_CR_PRESCALER             QUADSPI_CR_PRESCALER_Msk              /*!< PRESCALER[7:0] Clock prescaler */

+#define QUADSPI_CR_PRESCALER_0           (0x01UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x01000000 */

+#define QUADSPI_CR_PRESCALER_1           (0x02UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x02000000 */

+#define QUADSPI_CR_PRESCALER_2           (0x04UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x04000000 */

+#define QUADSPI_CR_PRESCALER_3           (0x08UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x08000000 */

+#define QUADSPI_CR_PRESCALER_4           (0x10UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x10000000 */

+#define QUADSPI_CR_PRESCALER_5           (0x20UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x20000000 */

+#define QUADSPI_CR_PRESCALER_6           (0x40UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x40000000 */

+#define QUADSPI_CR_PRESCALER_7           (0x80UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x80000000 */

+

+/*****************  Bit definition for QUADSPI_DCR register  ******************/

+#define QUADSPI_DCR_CKMODE_Pos           (0U)

+#define QUADSPI_DCR_CKMODE_Msk           (0x1UL << QUADSPI_DCR_CKMODE_Pos)     /*!< 0x00000001 */

+#define QUADSPI_DCR_CKMODE               QUADSPI_DCR_CKMODE_Msk                /*!< Mode 0 / Mode 3 */

+#define QUADSPI_DCR_CSHT_Pos             (8U)

+#define QUADSPI_DCR_CSHT_Msk             (0x7UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000700 */

+#define QUADSPI_DCR_CSHT                 QUADSPI_DCR_CSHT_Msk                  /*!< CSHT[2:0]: ChipSelect High Time */

+#define QUADSPI_DCR_CSHT_0               (0x1UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000100 */

+#define QUADSPI_DCR_CSHT_1               (0x2UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000200 */

+#define QUADSPI_DCR_CSHT_2               (0x4UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000400 */

+#define QUADSPI_DCR_FSIZE_Pos            (16U)

+#define QUADSPI_DCR_FSIZE_Msk            (0x1FUL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x001F0000 */

+#define QUADSPI_DCR_FSIZE                QUADSPI_DCR_FSIZE_Msk                 /*!< FSIZE[4:0]: Flash Size */

+#define QUADSPI_DCR_FSIZE_0              (0x01UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00010000 */

+#define QUADSPI_DCR_FSIZE_1              (0x02UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00020000 */

+#define QUADSPI_DCR_FSIZE_2              (0x04UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00040000 */

+#define QUADSPI_DCR_FSIZE_3              (0x08UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00080000 */

+#define QUADSPI_DCR_FSIZE_4              (0x10UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00100000 */

+

+/******************  Bit definition for QUADSPI_SR register  *******************/

+#define QUADSPI_SR_TEF_Pos               (0U)

+#define QUADSPI_SR_TEF_Msk               (0x1UL << QUADSPI_SR_TEF_Pos)         /*!< 0x00000001 */

+#define QUADSPI_SR_TEF                   QUADSPI_SR_TEF_Msk                    /*!< Transfer Error Flag */

+#define QUADSPI_SR_TCF_Pos               (1U)

+#define QUADSPI_SR_TCF_Msk               (0x1UL << QUADSPI_SR_TCF_Pos)         /*!< 0x00000002 */

+#define QUADSPI_SR_TCF                   QUADSPI_SR_TCF_Msk                    /*!< Transfer Complete Flag */

+#define QUADSPI_SR_FTF_Pos               (2U)

+#define QUADSPI_SR_FTF_Msk               (0x1UL << QUADSPI_SR_FTF_Pos)         /*!< 0x00000004 */

+#define QUADSPI_SR_FTF                   QUADSPI_SR_FTF_Msk                    /*!< FIFO Threshlod Flag */

+#define QUADSPI_SR_SMF_Pos               (3U)

+#define QUADSPI_SR_SMF_Msk               (0x1UL << QUADSPI_SR_SMF_Pos)         /*!< 0x00000008 */

+#define QUADSPI_SR_SMF                   QUADSPI_SR_SMF_Msk                    /*!< Status Match Flag */

+#define QUADSPI_SR_TOF_Pos               (4U)

+#define QUADSPI_SR_TOF_Msk               (0x1UL << QUADSPI_SR_TOF_Pos)         /*!< 0x00000010 */

+#define QUADSPI_SR_TOF                   QUADSPI_SR_TOF_Msk                    /*!< Timeout Flag */

+#define QUADSPI_SR_BUSY_Pos              (5U)

+#define QUADSPI_SR_BUSY_Msk              (0x1UL << QUADSPI_SR_BUSY_Pos)        /*!< 0x00000020 */

+#define QUADSPI_SR_BUSY                  QUADSPI_SR_BUSY_Msk                   /*!< Busy */

+#define QUADSPI_SR_FLEVEL_Pos            (8U)

+#define QUADSPI_SR_FLEVEL_Msk            (0x3FUL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00003F00 */

+#define QUADSPI_SR_FLEVEL                QUADSPI_SR_FLEVEL_Msk                 /*!< FIFO Threshlod Flag */

+#define QUADSPI_SR_FLEVEL_0              (0x01UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000100 */

+#define QUADSPI_SR_FLEVEL_1              (0x02UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000200 */

+#define QUADSPI_SR_FLEVEL_2              (0x04UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000400 */

+#define QUADSPI_SR_FLEVEL_3              (0x08UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000800 */

+#define QUADSPI_SR_FLEVEL_4              (0x10UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00001000 */

+#define QUADSPI_SR_FLEVEL_5              (0x20UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00002000 */

+

+/******************  Bit definition for QUADSPI_FCR register  ******************/

+#define QUADSPI_FCR_CTEF_Pos             (0U)

+#define QUADSPI_FCR_CTEF_Msk             (0x1UL << QUADSPI_FCR_CTEF_Pos)       /*!< 0x00000001 */

+#define QUADSPI_FCR_CTEF                 QUADSPI_FCR_CTEF_Msk                  /*!< Clear Transfer Error Flag */

+#define QUADSPI_FCR_CTCF_Pos             (1U)

+#define QUADSPI_FCR_CTCF_Msk             (0x1UL << QUADSPI_FCR_CTCF_Pos)       /*!< 0x00000002 */

+#define QUADSPI_FCR_CTCF                 QUADSPI_FCR_CTCF_Msk                  /*!< Clear Transfer Complete Flag */

+#define QUADSPI_FCR_CSMF_Pos             (3U)

+#define QUADSPI_FCR_CSMF_Msk             (0x1UL << QUADSPI_FCR_CSMF_Pos)       /*!< 0x00000008 */

+#define QUADSPI_FCR_CSMF                 QUADSPI_FCR_CSMF_Msk                  /*!< Clear Status Match Flag */

+#define QUADSPI_FCR_CTOF_Pos             (4U)

+#define QUADSPI_FCR_CTOF_Msk             (0x1UL << QUADSPI_FCR_CTOF_Pos)       /*!< 0x00000010 */

+#define QUADSPI_FCR_CTOF                 QUADSPI_FCR_CTOF_Msk                  /*!< Clear Timeout Flag */

+

+/******************  Bit definition for QUADSPI_DLR register  ******************/

+#define QUADSPI_DLR_DL_Pos               (0U)

+#define QUADSPI_DLR_DL_Msk               (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)  /*!< 0xFFFFFFFF */

+#define QUADSPI_DLR_DL                   QUADSPI_DLR_DL_Msk                    /*!< DL[31:0]: Data Length */

+

+/******************  Bit definition for QUADSPI_CCR register  ******************/

+#define QUADSPI_CCR_INSTRUCTION_Pos      (0U)

+#define QUADSPI_CCR_INSTRUCTION_Msk      (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */

+#define QUADSPI_CCR_INSTRUCTION          QUADSPI_CCR_INSTRUCTION_Msk             /*!< INSTRUCTION[7:0]: Instruction */

+#define QUADSPI_CCR_INSTRUCTION_0        (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */

+#define QUADSPI_CCR_INSTRUCTION_1        (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */

+#define QUADSPI_CCR_INSTRUCTION_2        (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */

+#define QUADSPI_CCR_INSTRUCTION_3        (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */

+#define QUADSPI_CCR_INSTRUCTION_4        (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */

+#define QUADSPI_CCR_INSTRUCTION_5        (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */

+#define QUADSPI_CCR_INSTRUCTION_6        (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */

+#define QUADSPI_CCR_INSTRUCTION_7        (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */

+#define QUADSPI_CCR_IMODE_Pos            (8U)

+#define QUADSPI_CCR_IMODE_Msk            (0x3UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000300 */

+#define QUADSPI_CCR_IMODE                QUADSPI_CCR_IMODE_Msk                   /*!< IMODE[1:0]: Instruction Mode */

+#define QUADSPI_CCR_IMODE_0              (0x1UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000100 */

+#define QUADSPI_CCR_IMODE_1              (0x2UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000200 */

+#define QUADSPI_CCR_ADMODE_Pos           (10U)

+#define QUADSPI_CCR_ADMODE_Msk           (0x3UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000C00 */

+#define QUADSPI_CCR_ADMODE               QUADSPI_CCR_ADMODE_Msk                  /*!< ADMODE[1:0]: Address Mode */

+#define QUADSPI_CCR_ADMODE_0             (0x1UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000400 */

+#define QUADSPI_CCR_ADMODE_1             (0x2UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000800 */

+#define QUADSPI_CCR_ADSIZE_Pos           (12U)

+#define QUADSPI_CCR_ADSIZE_Msk           (0x3UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00003000 */

+#define QUADSPI_CCR_ADSIZE               QUADSPI_CCR_ADSIZE_Msk                  /*!< ADSIZE[1:0]: Address Size */

+#define QUADSPI_CCR_ADSIZE_0             (0x1UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00001000 */

+#define QUADSPI_CCR_ADSIZE_1             (0x2UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00002000 */

+#define QUADSPI_CCR_ABMODE_Pos           (14U)

+#define QUADSPI_CCR_ABMODE_Msk           (0x3UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x0000C000 */

+#define QUADSPI_CCR_ABMODE               QUADSPI_CCR_ABMODE_Msk                  /*!< ABMODE[1:0]: Alternate Bytes Mode */

+#define QUADSPI_CCR_ABMODE_0             (0x1UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00004000 */

+#define QUADSPI_CCR_ABMODE_1             (0x2UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00008000 */

+#define QUADSPI_CCR_ABSIZE_Pos           (16U)

+#define QUADSPI_CCR_ABSIZE_Msk           (0x3UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00030000 */

+#define QUADSPI_CCR_ABSIZE               QUADSPI_CCR_ABSIZE_Msk                  /*!< ABSIZE[1:0]: Instruction Mode */

+#define QUADSPI_CCR_ABSIZE_0             (0x1UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00010000 */

+#define QUADSPI_CCR_ABSIZE_1             (0x2UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00020000 */

+#define QUADSPI_CCR_DCYC_Pos             (18U)

+#define QUADSPI_CCR_DCYC_Msk             (0x1FUL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x007C0000 */

+#define QUADSPI_CCR_DCYC                 QUADSPI_CCR_DCYC_Msk                    /*!< DCYC[4:0]: Dummy Cycles */

+#define QUADSPI_CCR_DCYC_0               (0x01UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00040000 */

+#define QUADSPI_CCR_DCYC_1               (0x02UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00080000 */

+#define QUADSPI_CCR_DCYC_2               (0x04UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00100000 */

+#define QUADSPI_CCR_DCYC_3               (0x08UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00200000 */

+#define QUADSPI_CCR_DCYC_4               (0x10UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00400000 */

+#define QUADSPI_CCR_DMODE_Pos            (24U)

+#define QUADSPI_CCR_DMODE_Msk            (0x3UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x03000000 */

+#define QUADSPI_CCR_DMODE                QUADSPI_CCR_DMODE_Msk                   /*!< DMODE[1:0]: Data Mode */

+#define QUADSPI_CCR_DMODE_0              (0x1UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x01000000 */

+#define QUADSPI_CCR_DMODE_1              (0x2UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x02000000 */

+#define QUADSPI_CCR_FMODE_Pos            (26U)

+#define QUADSPI_CCR_FMODE_Msk            (0x3UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x0C000000 */

+#define QUADSPI_CCR_FMODE                QUADSPI_CCR_FMODE_Msk                   /*!< FMODE[1:0]: Functional Mode */

+#define QUADSPI_CCR_FMODE_0              (0x1UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x04000000 */

+#define QUADSPI_CCR_FMODE_1              (0x2UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x08000000 */

+#define QUADSPI_CCR_SIOO_Pos             (28U)

+#define QUADSPI_CCR_SIOO_Msk             (0x1UL << QUADSPI_CCR_SIOO_Pos)         /*!< 0x10000000 */

+#define QUADSPI_CCR_SIOO                 QUADSPI_CCR_SIOO_Msk                    /*!< SIOO: Send Instruction Only Once Mode */

+#define QUADSPI_CCR_DHHC_Pos             (30U)

+#define QUADSPI_CCR_DHHC_Msk             (0x1UL << QUADSPI_CCR_DHHC_Pos)         /*!< 0x40000000 */

+#define QUADSPI_CCR_DHHC                 QUADSPI_CCR_DHHC_Msk                    /*!< DHHC: DDR hold half cycle */

+#define QUADSPI_CCR_DDRM_Pos             (31U)

+#define QUADSPI_CCR_DDRM_Msk             (0x1UL << QUADSPI_CCR_DDRM_Pos)         /*!< 0x80000000 */

+#define QUADSPI_CCR_DDRM                 QUADSPI_CCR_DDRM_Msk                    /*!< DDRM: Double Data Rate Mode */

+

+/******************  Bit definition for QUADSPI_AR register  *******************/

+#define QUADSPI_AR_ADDRESS_Pos           (0U)

+#define QUADSPI_AR_ADDRESS_Msk           (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_AR_ADDRESS               QUADSPI_AR_ADDRESS_Msk                /*!< ADDRESS[31:0]: Address */

+

+/******************  Bit definition for QUADSPI_ABR register  ******************/

+#define QUADSPI_ABR_ALTERNATE_Pos        (0U)

+#define QUADSPI_ABR_ALTERNATE_Msk        (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_ABR_ALTERNATE            QUADSPI_ABR_ALTERNATE_Msk             /*!< ALTERNATE[31:0]: Alternate Bytes */

+

+/******************  Bit definition for QUADSPI_DR register  *******************/

+#define QUADSPI_DR_DATA_Pos              (0U)

+#define QUADSPI_DR_DATA_Msk              (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_DR_DATA                  QUADSPI_DR_DATA_Msk                   /*!< DATA[31:0]: Data */

+

+/******************  Bit definition for QUADSPI_PSMKR register  ****************/

+#define QUADSPI_PSMKR_MASK_Pos           (0U)

+#define QUADSPI_PSMKR_MASK_Msk           (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_PSMKR_MASK               QUADSPI_PSMKR_MASK_Msk                /*!< MASK[31:0]: Status Mask */

+

+/******************  Bit definition for QUADSPI_PSMAR register  ****************/

+#define QUADSPI_PSMAR_MATCH_Pos          (0U)

+#define QUADSPI_PSMAR_MATCH_Msk          (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_PSMAR_MATCH              QUADSPI_PSMAR_MATCH_Msk               /*!< MATCH[31:0]: Status Match */

+

+/******************  Bit definition for QUADSPI_PIR register  *****************/

+#define QUADSPI_PIR_INTERVAL_Pos         (0U)

+#define QUADSPI_PIR_INTERVAL_Msk         (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */

+#define QUADSPI_PIR_INTERVAL             QUADSPI_PIR_INTERVAL_Msk              /*!< INTERVAL[15:0]: Polling Interval */

+

+/******************  Bit definition for QUADSPI_LPTR register  *****************/

+#define QUADSPI_LPTR_TIMEOUT_Pos         (0U)

+#define QUADSPI_LPTR_TIMEOUT_Msk         (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */

+#define QUADSPI_LPTR_TIMEOUT             QUADSPI_LPTR_TIMEOUT_Msk              /*!< TIMEOUT[15:0]: Timeout period */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                 SYSCFG                                     */

+/*                                                                            */

+/******************************************************************************/

+

+/******************  Bit definition for SYSCFG_PMCR register  ******************/

+#define SYSCFG_PMCR_I2C1_FMP_Pos        (0U)

+#define SYSCFG_PMCR_I2C1_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos)    /*!< 0x00000001 */

+#define SYSCFG_PMCR_I2C1_FMP            SYSCFG_PMCR_I2C1_FMP_Msk               /*!< I2C1 Fast mode plus */

+#define SYSCFG_PMCR_I2C2_FMP_Pos        (1U)

+#define SYSCFG_PMCR_I2C2_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos)    /*!< 0x00000002 */

+#define SYSCFG_PMCR_I2C2_FMP            SYSCFG_PMCR_I2C2_FMP_Msk               /*!< I2C2 Fast mode plus */

+#define SYSCFG_PMCR_I2C3_FMP_Pos        (2U)

+#define SYSCFG_PMCR_I2C3_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos)    /*!< 0x00000004 */

+#define SYSCFG_PMCR_I2C3_FMP            SYSCFG_PMCR_I2C3_FMP_Msk               /*!< I2C3 Fast mode plus */

+#define SYSCFG_PMCR_I2C4_FMP_Pos        (3U)

+#define SYSCFG_PMCR_I2C4_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos)    /*!< 0x00000008 */

+#define SYSCFG_PMCR_I2C4_FMP            SYSCFG_PMCR_I2C4_FMP_Msk               /*!< I2C4 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB6_FMP_Pos     (4U)

+#define SYSCFG_PMCR_I2C_PB6_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */

+#define SYSCFG_PMCR_I2C_PB6_FMP         SYSCFG_PMCR_I2C_PB6_FMP_Msk            /*!< I2C PB6 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB7_FMP_Pos     (5U)

+#define SYSCFG_PMCR_I2C_PB7_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */

+#define SYSCFG_PMCR_I2C_PB7_FMP         SYSCFG_PMCR_I2C_PB7_FMP_Msk            /*!< I2C PB7 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB8_FMP_Pos     (6U)

+#define SYSCFG_PMCR_I2C_PB8_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */

+#define SYSCFG_PMCR_I2C_PB8_FMP         SYSCFG_PMCR_I2C_PB8_FMP_Msk            /*!< I2C PB8 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB9_FMP_Pos     (7U)

+#define SYSCFG_PMCR_I2C_PB9_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */

+#define SYSCFG_PMCR_I2C_PB9_FMP         SYSCFG_PMCR_I2C_PB9_FMP_Msk            /*!< I2C PB9 Fast mode plus */

+#define SYSCFG_PMCR_BOOSTEN_Pos         (8U)

+#define SYSCFG_PMCR_BOOSTEN_Msk         (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos)     /*!< 0x00000100 */

+#define SYSCFG_PMCR_BOOSTEN             SYSCFG_PMCR_BOOSTEN_Msk                /*!< I/O analog switch voltage booster enable */

+

+#define SYSCFG_PMCR_BOOSTVDDSEL_Pos     (9U)

+#define SYSCFG_PMCR_BOOSTVDDSEL_Msk     (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos) /*!< 0x00000200 */

+#define SYSCFG_PMCR_BOOSTVDDSEL         SYSCFG_PMCR_BOOSTVDDSEL_Msk            /*!< Analog switch supply source selection : VDD/VDDA */

+

+#define SYSCFG_PMCR_EPIS_SEL_Pos        (21U)

+#define SYSCFG_PMCR_EPIS_SEL_Msk        (0x7UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00E00000 */

+#define SYSCFG_PMCR_EPIS_SEL            SYSCFG_PMCR_EPIS_SEL_Msk               /*!< Ethernet PHY Interface Selection */

+#define SYSCFG_PMCR_EPIS_SEL_0          (0x1UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00200000 */

+#define SYSCFG_PMCR_EPIS_SEL_1          (0x2UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00400000 */

+#define SYSCFG_PMCR_EPIS_SEL_2          (0x4UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00800000 */

+#define SYSCFG_PMCR_PA0SO_Pos           (24U)

+#define SYSCFG_PMCR_PA0SO_Msk           (0x1UL << SYSCFG_PMCR_PA0SO_Pos)       /*!< 0x01000000 */

+#define SYSCFG_PMCR_PA0SO               SYSCFG_PMCR_PA0SO_Msk                  /*!< PA0 Switch Open */

+#define SYSCFG_PMCR_PA1SO_Pos           (25U)

+#define SYSCFG_PMCR_PA1SO_Msk           (0x1UL << SYSCFG_PMCR_PA1SO_Pos)       /*!< 0x02000000 */

+#define SYSCFG_PMCR_PA1SO               SYSCFG_PMCR_PA1SO_Msk                  /*!< PA1 Switch Open */

+#define SYSCFG_PMCR_PC2SO_Pos           (26U)

+#define SYSCFG_PMCR_PC2SO_Msk           (0x1UL << SYSCFG_PMCR_PC2SO_Pos)       /*!< 0x04000000 */

+#define SYSCFG_PMCR_PC2SO               SYSCFG_PMCR_PC2SO_Msk                  /*!< PC2 Switch Open */

+#define SYSCFG_PMCR_PC3SO_Pos           (27U)

+#define SYSCFG_PMCR_PC3SO_Msk           (0x1UL << SYSCFG_PMCR_PC3SO_Pos)       /*!< 0x08000000 */

+#define SYSCFG_PMCR_PC3SO               SYSCFG_PMCR_PC3SO_Msk                  /*!< PC3 Switch Open */

+

+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/

+#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)

+#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */

+#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)

+#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */

+#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)

+#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000F00 */

+#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */

+#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)

+#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x0000F000 */

+#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */

+/**

+  * @brief   EXTI0 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */

+

+/**

+  * @brief   EXTI1 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */

+/**

+  * @brief   EXTI2 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */

+

+/**

+  * @brief   EXTI3 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/

+#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)

+#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */

+#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)

+#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */

+#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)

+#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000F00 */

+#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */

+#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)

+#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x0000F000 */

+#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */

+/**

+  * @brief   EXTI4 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */

+/**

+  * @brief   EXTI5 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */

+/**

+  * @brief   EXTI6 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */

+

+/**

+  * @brief   EXTI7 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/

+#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)

+#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */

+#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)

+#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */

+#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)

+#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000F00 */

+#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */

+#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)

+#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x0000F000 */

+#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */

+

+/**

+  * @brief   EXTI8 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */

+

+/**

+  * @brief   EXTI9 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */

+

+/**

+  * @brief   EXTI10 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */

+

+/**

+  * @brief   EXTI11 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/

+#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)

+#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x0000000F */

+#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */

+#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)

+#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x000000F0 */

+#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */

+#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)

+#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000F00 */

+#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */

+#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)

+#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x0000F000 */

+#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */

+/**

+  * @brief   EXTI12 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */

+/**

+  * @brief   EXTI13 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */

+/**

+  * @brief   EXTI14 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */

+/**

+  * @brief   EXTI15 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */

+

+/******************  Bit definition for SYSCFG_CFGR register  ******************/

+#define SYSCFG_CFGR_PVDL_Pos            (2U)

+#define SYSCFG_CFGR_PVDL_Msk            (0x1UL << SYSCFG_CFGR_PVDL_Pos)        /*!< 0x00000004 */

+#define SYSCFG_CFGR_PVDL                SYSCFG_CFGR_PVDL_Msk                   /*!<PVD lock enable bit */

+#define SYSCFG_CFGR_FLASHL_Pos          (3U)

+#define SYSCFG_CFGR_FLASHL_Msk          (0x1UL << SYSCFG_CFGR_FLASHL_Pos)      /*!< 0x00000008 */

+#define SYSCFG_CFGR_FLASHL              SYSCFG_CFGR_FLASHL_Msk                 /*!<FLASH double ECC error lock bit */

+#define SYSCFG_CFGR_CM7L_Pos            (6U)

+#define SYSCFG_CFGR_CM7L_Msk            (0x1UL << SYSCFG_CFGR_CM7L_Pos)        /*!< 0x00000040 */

+#define SYSCFG_CFGR_CM7L                SYSCFG_CFGR_CM7L_Msk                   /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */

+#define SYSCFG_CFGR_BKRAML_Pos          (7U)

+#define SYSCFG_CFGR_BKRAML_Msk          (0x1UL << SYSCFG_CFGR_BKRAML_Pos)      /*!< 0x00000080 */

+#define SYSCFG_CFGR_BKRAML              SYSCFG_CFGR_BKRAML_Msk                 /*!<Backup SRAM double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM4L_Pos          (9U)

+#define SYSCFG_CFGR_SRAM4L_Msk          (0x1UL << SYSCFG_CFGR_SRAM4L_Pos)      /*!< 0x00000200 */

+#define SYSCFG_CFGR_SRAM4L              SYSCFG_CFGR_SRAM4L_Msk                 /*!<SRAM4 double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM3L_Pos          (10U)

+#define SYSCFG_CFGR_SRAM3L_Msk          (0x1UL << SYSCFG_CFGR_SRAM3L_Pos)      /*!< 0x00000400 */

+#define SYSCFG_CFGR_SRAM3L              SYSCFG_CFGR_SRAM3L_Msk                 /*!<SRAM3 double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM2L_Pos          (11U)

+#define SYSCFG_CFGR_SRAM2L_Msk          (0x1UL << SYSCFG_CFGR_SRAM2L_Pos)      /*!< 0x00000800 */

+#define SYSCFG_CFGR_SRAM2L              SYSCFG_CFGR_SRAM2L_Msk                 /*!<SRAM2 double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM1L_Pos          (12U)

+#define SYSCFG_CFGR_SRAM1L_Msk          (0x1UL << SYSCFG_CFGR_SRAM1L_Pos)      /*!< 0x00001000 */

+#define SYSCFG_CFGR_SRAM1L              SYSCFG_CFGR_SRAM1L_Msk                 /*!<SRAM1 double ECC error lock bit */

+#define SYSCFG_CFGR_DTCML_Pos           (13U)

+#define SYSCFG_CFGR_DTCML_Msk           (0x1UL << SYSCFG_CFGR_DTCML_Pos)       /*!< 0x00002000 */

+#define SYSCFG_CFGR_DTCML               SYSCFG_CFGR_DTCML_Msk                  /*!<DTCM double ECC error lock bit */

+#define SYSCFG_CFGR_ITCML_Pos           (14U)

+#define SYSCFG_CFGR_ITCML_Msk           (0x1UL << SYSCFG_CFGR_ITCML_Pos)       /*!< 0x00004000 */

+#define SYSCFG_CFGR_ITCML               SYSCFG_CFGR_ITCML_Msk                  /*!<ITCM double ECC error lock bit */

+#define SYSCFG_CFGR_AXISRAML_Pos        (15U)

+#define SYSCFG_CFGR_AXISRAML_Msk        (0x1UL << SYSCFG_CFGR_AXISRAML_Pos)    /*!< 0x00008000 */

+#define SYSCFG_CFGR_AXISRAML            SYSCFG_CFGR_AXISRAML_Msk               /*!<AXISRAM double ECC error lock bit */

+

+/******************  Bit definition for SYSCFG_CCCSR register  ******************/

+#define SYSCFG_CCCSR_EN_Pos             (0U)

+#define SYSCFG_CCCSR_EN_Msk             (0x1UL << SYSCFG_CCCSR_EN_Pos)         /*!< 0x00000001 */

+#define SYSCFG_CCCSR_EN                 SYSCFG_CCCSR_EN_Msk                    /*!< I/O compensation cell enable */

+#define SYSCFG_CCCSR_CS_Pos             (1U)

+#define SYSCFG_CCCSR_CS_Msk             (0x1UL << SYSCFG_CCCSR_CS_Pos)         /*!< 0x00000002 */

+#define SYSCFG_CCCSR_CS                 SYSCFG_CCCSR_CS_Msk                    /*!< I/O compensation cell code selection */

+#define SYSCFG_CCCSR_READY_Pos          (8U)

+#define SYSCFG_CCCSR_READY_Msk          (0x1UL << SYSCFG_CCCSR_READY_Pos)      /*!< 0x00000100 */

+#define SYSCFG_CCCSR_READY              SYSCFG_CCCSR_READY_Msk                 /*!< I/O compensation cell ready flag */

+#define SYSCFG_CCCSR_HSLV_Pos           (16U)

+#define SYSCFG_CCCSR_HSLV_Msk           (0x1UL << SYSCFG_CCCSR_HSLV_Pos)       /*!< 0x00010000 */

+#define SYSCFG_CCCSR_HSLV               SYSCFG_CCCSR_HSLV_Msk                  /*!< High-speed at low-voltage */

+

+/******************  Bit definition for SYSCFG_CCVR register  *******************/

+#define SYSCFG_CCVR_NCV_Pos             (0U)

+#define SYSCFG_CCVR_NCV_Msk             (0xFUL << SYSCFG_CCVR_NCV_Pos)         /*!< 0x0000000F */

+#define SYSCFG_CCVR_NCV                 SYSCFG_CCVR_NCV_Msk                    /*!< NMOS compensation value */

+#define SYSCFG_CCVR_PCV_Pos             (4U)

+#define SYSCFG_CCVR_PCV_Msk             (0xFUL << SYSCFG_CCVR_PCV_Pos)         /*!< 0x000000F0 */

+#define SYSCFG_CCVR_PCV                 SYSCFG_CCVR_PCV_Msk                    /*!< PMOS compensation value */

+

+/******************  Bit definition for SYSCFG_CCCR register  *******************/

+#define SYSCFG_CCCR_NCC_Pos             (0U)

+#define SYSCFG_CCCR_NCC_Msk             (0xFUL << SYSCFG_CCCR_NCC_Pos)         /*!< 0x0000000F */

+#define SYSCFG_CCCR_NCC                 SYSCFG_CCCR_NCC_Msk                    /*!< NMOS compensation code */

+#define SYSCFG_CCCR_PCC_Pos             (4U)

+#define SYSCFG_CCCR_PCC_Msk             (0xFUL << SYSCFG_CCCR_PCC_Pos)         /*!< 0x000000F0 */

+#define SYSCFG_CCCR_PCC                 SYSCFG_CCCR_PCC_Msk                    /*!< PMOS compensation code */

+/******************  Bit definition for SYSCFG_PWRCR register  *******************/

+#define SYSCFG_PWRCR_ODEN_Pos           (0U)

+#define SYSCFG_PWRCR_ODEN_Msk           (0x1UL << SYSCFG_PWRCR_ODEN_Pos)         /*!< 0x00000001 */

+#define SYSCFG_PWRCR_ODEN               SYSCFG_PWRCR_ODEN_Msk                    /*!< PWR overdrive enable */

+

+/******************  Bit definition for SYSCFG_PKGR register  *******************/

+#define SYSCFG_PKGR_PKG_Pos             (0U)

+#define SYSCFG_PKGR_PKG_Msk             (0xFUL << SYSCFG_PKGR_PKG_Pos)         /*!< 0x0000000F */

+#define SYSCFG_PKGR_PKG                 SYSCFG_PKGR_PKG_Msk                    /*!< Package type */

+

+/******************  Bit definition for SYSCFG_UR0 register  *******************/

+#define SYSCFG_UR0_BKS_Pos              (0U)

+#define SYSCFG_UR0_BKS_Msk              (0x1UL << SYSCFG_UR0_BKS_Pos)          /*!< 0x00000001 */

+#define SYSCFG_UR0_BKS                  SYSCFG_UR0_BKS_Msk                     /*!< Bank Swap */

+#define SYSCFG_UR0_RDP_Pos              (16U)

+#define SYSCFG_UR0_RDP_Msk              (0xFFUL << SYSCFG_UR0_RDP_Pos)         /*!< 0x00FF0000 */

+#define SYSCFG_UR0_RDP                  SYSCFG_UR0_RDP_Msk                     /*!< Readout protection */

+

+/******************  Bit definition for SYSCFG_UR2 register  *******************/

+#define SYSCFG_UR2_BORH_Pos             (0U)

+#define SYSCFG_UR2_BORH_Msk             (0x3UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000003 */

+#define SYSCFG_UR2_BORH                 SYSCFG_UR2_BORH_Msk                    /*!< Brown Out Reset High level */

+#define SYSCFG_UR2_BORH_0               (0x1UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000001 */

+#define SYSCFG_UR2_BORH_1               (0x2UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000002 */

+#define SYSCFG_UR2_BOOT_ADD0_Pos        (16U)

+#define SYSCFG_UR2_BOOT_ADD0_Msk        (0xFFFFUL << SYSCFG_UR2_BOOT_ADD0_Pos) /*!< 0xFFFF0000 */

+#define SYSCFG_UR2_BOOT_ADD0            SYSCFG_UR2_BOOT_ADD0_Msk               /*!< Core Boot Address 0 */

+/******************  Bit definition for SYSCFG_UR3 register  *******************/

+#define SYSCFG_UR3_BOOT_ADD1_Pos        (0U)

+#define SYSCFG_UR3_BOOT_ADD1_Msk        (0xFFFFUL << SYSCFG_UR3_BOOT_ADD1_Pos) /*!< 0x0000FFFF */

+#define SYSCFG_UR3_BOOT_ADD1            SYSCFG_UR3_BOOT_ADD1_Msk               /*!< Core Boot Address 1 */

+

+  /******************  Bit definition for SYSCFG_UR4 register  *******************/

+

+#define SYSCFG_UR4_MEPAD_BANK1_Pos      (16U)

+#define SYSCFG_UR4_MEPAD_BANK1_Msk      (0x1UL << SYSCFG_UR4_MEPAD_BANK1_Pos)  /*!< 0x00010000 */

+#define SYSCFG_UR4_MEPAD_BANK1          SYSCFG_UR4_MEPAD_BANK1_Msk             /*!< Mass Erase Protected Area Disabled for bank 1 */

+

+/******************  Bit definition for SYSCFG_UR5 register  *******************/

+#define SYSCFG_UR5_MESAD_BANK1_Pos      (0U)

+#define SYSCFG_UR5_MESAD_BANK1_Msk      (0x1UL << SYSCFG_UR5_MESAD_BANK1_Pos)  /*!< 0x00000001 */

+#define SYSCFG_UR5_MESAD_BANK1          SYSCFG_UR5_MESAD_BANK1_Msk             /*!< Mass erase secured area disabled for bank 1 */

+#define SYSCFG_UR5_WRPN_BANK1_Pos       (16U)

+#define SYSCFG_UR5_WRPN_BANK1_Msk       (0xFFUL << SYSCFG_UR5_WRPN_BANK1_Pos)  /*!< 0x00FF0000 */

+#define SYSCFG_UR5_WRPN_BANK1           SYSCFG_UR5_WRPN_BANK1_Msk              /*!< Write protection for flash bank 1 */

+

+/******************  Bit definition for SYSCFG_UR6 register  *******************/

+#define SYSCFG_UR6_PABEG_BANK1_Pos      (0U)

+#define SYSCFG_UR6_PABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PABEG_BANK1_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR6_PABEG_BANK1          SYSCFG_UR6_PABEG_BANK1_Msk             /*!< Protected area start address for bank 1 */

+#define SYSCFG_UR6_PAEND_BANK1_Pos      (16U)

+#define SYSCFG_UR6_PAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PAEND_BANK1_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR6_PAEND_BANK1          SYSCFG_UR6_PAEND_BANK1_Msk             /*!< Protected area end address for bank 1 */

+

+/******************  Bit definition for SYSCFG_UR7 register  *******************/

+#define SYSCFG_UR7_SABEG_BANK1_Pos      (0U)

+#define SYSCFG_UR7_SABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SABEG_BANK1_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR7_SABEG_BANK1          SYSCFG_UR7_SABEG_BANK1_Msk             /*!< Secured area start address for bank 1 */

+#define SYSCFG_UR7_SAEND_BANK1_Pos      (16U)

+#define SYSCFG_UR7_SAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SAEND_BANK1_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR7_SAEND_BANK1          SYSCFG_UR7_SAEND_BANK1_Msk             /*!< Secured area end address for bank 1 */

+

+/******************  Bit definition for SYSCFG_UR8 register  *******************/

+#define SYSCFG_UR8_MEPAD_BANK2_Pos      (0U)

+#define SYSCFG_UR8_MEPAD_BANK2_Msk      (0x1UL << SYSCFG_UR8_MEPAD_BANK2_Pos)  /*!< 0x00000001 */

+#define SYSCFG_UR8_MEPAD_BANK2          SYSCFG_UR8_MEPAD_BANK2_Msk             /*!< Mass erase Protected area disabled for bank 2 */

+#define SYSCFG_UR8_MESAD_BANK2_Pos      (16U)

+#define SYSCFG_UR8_MESAD_BANK2_Msk      (0x1UL << SYSCFG_UR8_MESAD_BANK2_Pos)  /*!< 0x00010000 */

+#define SYSCFG_UR8_MESAD_BANK2          SYSCFG_UR8_MESAD_BANK2_Msk             /*!< Mass Erase Secured Area Disabled for bank 2 */

+

+/******************  Bit definition for SYSCFG_UR9 register  *******************/

+#define SYSCFG_UR9_WRPN_BANK2_Pos       (0U)

+#define SYSCFG_UR9_WRPN_BANK2_Msk       (0xFFUL << SYSCFG_UR9_WRPN_BANK2_Pos)  /*!< 0x000000FF */

+#define SYSCFG_UR9_WRPN_BANK2           SYSCFG_UR9_WRPN_BANK2_Msk              /*!< Write protection for flash bank 2 */

+#define SYSCFG_UR9_PABEG_BANK2_Pos      (16U)

+#define SYSCFG_UR9_PABEG_BANK2_Msk      (0xFFFUL << SYSCFG_UR9_PABEG_BANK2_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR9_PABEG_BANK2          SYSCFG_UR9_PABEG_BANK2_Msk             /*!< Protected area start address for bank 2 */

+

+/******************  Bit definition for SYSCFG_UR10 register  *******************/

+#define SYSCFG_UR10_PAEND_BANK2_Pos     (0U)

+#define SYSCFG_UR10_PAEND_BANK2_Msk     (0xFFFUL << SYSCFG_UR10_PAEND_BANK2_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR10_PAEND_BANK2         SYSCFG_UR10_PAEND_BANK2_Msk            /*!< Protected area end address for bank 2 */

+#define SYSCFG_UR10_SABEG_BANK2_Pos     (16U)

+#define SYSCFG_UR10_SABEG_BANK2_Msk     (0xFFFUL << SYSCFG_UR10_SABEG_BANK2_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR10_SABEG_BANK2         SYSCFG_UR10_SABEG_BANK2_Msk            /*!< Secured area start address for bank 2 */

+

+/******************  Bit definition for SYSCFG_UR11 register  *******************/

+#define SYSCFG_UR11_SAEND_BANK2_Pos     (0U)

+#define SYSCFG_UR11_SAEND_BANK2_Msk     (0xFFFUL << SYSCFG_UR11_SAEND_BANK2_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR11_SAEND_BANK2         SYSCFG_UR11_SAEND_BANK2_Msk            /*!< Secured area end address for bank 2 */

+#define SYSCFG_UR11_IWDG1M_Pos          (16U)

+#define SYSCFG_UR11_IWDG1M_Msk          (0x1UL << SYSCFG_UR11_IWDG1M_Pos)      /*!< 0x00010000 */

+#define SYSCFG_UR11_IWDG1M              SYSCFG_UR11_IWDG1M_Msk                 /*!< Independent Watchdog 1 mode (SW or HW) */

+

+/******************  Bit definition for SYSCFG_UR12 register  *******************/

+

+#define SYSCFG_UR12_SECURE_Pos          (16U)

+#define SYSCFG_UR12_SECURE_Msk          (0x1UL << SYSCFG_UR12_SECURE_Pos)      /*!< 0x00010000 */

+#define SYSCFG_UR12_SECURE              SYSCFG_UR12_SECURE_Msk                 /*!< Secure mode status */

+

+/******************  Bit definition for SYSCFG_UR13 register  *******************/

+#define SYSCFG_UR13_SDRS_Pos            (0U)

+#define SYSCFG_UR13_SDRS_Msk            (0x3UL << SYSCFG_UR13_SDRS_Pos)        /*!< 0x00000003 */

+#define SYSCFG_UR13_SDRS                SYSCFG_UR13_SDRS_Msk                   /*!< Secured DTCM RAM Size */

+#define SYSCFG_UR13_D1SBRST_Pos         (16U)

+#define SYSCFG_UR13_D1SBRST_Msk         (0x1UL << SYSCFG_UR13_D1SBRST_Pos)     /*!< 0x00010000 */

+#define SYSCFG_UR13_D1SBRST             SYSCFG_UR13_D1SBRST_Msk                /*!< D1 Standby reset */

+

+/******************  Bit definition for SYSCFG_UR14 register  *******************/

+#define SYSCFG_UR14_D1STPRST_Pos        (0U)

+#define SYSCFG_UR14_D1STPRST_Msk        (0x1UL << SYSCFG_UR14_D1STPRST_Pos)    /*!< 0x00000001 */

+#define SYSCFG_UR14_D1STPRST            SYSCFG_UR14_D1STPRST_Msk               /*!< D1 Stop Reset */

+

+/******************  Bit definition for SYSCFG_UR15 register  *******************/

+#define SYSCFG_UR15_FZIWDGSTB_Pos       (16U)

+#define SYSCFG_UR15_FZIWDGSTB_Msk       (0x1UL << SYSCFG_UR15_FZIWDGSTB_Pos)   /*!< 0x00010000 */

+#define SYSCFG_UR15_FZIWDGSTB           SYSCFG_UR15_FZIWDGSTB_Msk              /*!< Freeze independent watchdogs in Standby mode */

+

+/******************  Bit definition for SYSCFG_UR16 register  *******************/

+#define SYSCFG_UR16_FZIWDGSTP_Pos       (0U)

+#define SYSCFG_UR16_FZIWDGSTP_Msk       (0x1UL << SYSCFG_UR16_FZIWDGSTP_Pos)   /*!< 0x00000001 */

+#define SYSCFG_UR16_FZIWDGSTP           SYSCFG_UR16_FZIWDGSTP_Msk              /*!< Freeze independent watchdogs in Stop mode */

+#define SYSCFG_UR16_PKP_Pos             (16U)

+#define SYSCFG_UR16_PKP_Msk             (0x1UL << SYSCFG_UR16_PKP_Pos)         /*!< 0x00010000 */

+#define SYSCFG_UR16_PKP                 SYSCFG_UR16_PKP_Msk                    /*!< Private key programmed */

+

+/******************  Bit definition for SYSCFG_UR17 register  *******************/

+#define SYSCFG_UR17_IOHSLV_Pos          (0U)

+#define SYSCFG_UR17_IOHSLV_Msk          (0x1UL << SYSCFG_UR17_IOHSLV_Pos)      /*!< 0x00000001 */

+#define SYSCFG_UR17_IOHSLV              SYSCFG_UR17_IOHSLV_Msk                 /*!< I/O high speed / low voltage */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    TIM                                     */

+/*                                                                            */

+/******************************************************************************/

+#define TIM_BREAK_INPUT_SUPPORT             /*!<TIM Break input feature */

+

+/*******************  Bit definition for TIM_CR1 register  ********************/

+#define TIM_CR1_CEN_Pos           (0U)

+#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */

+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */

+#define TIM_CR1_UDIS_Pos          (1U)

+#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */

+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */

+#define TIM_CR1_URS_Pos           (2U)

+#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */

+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */

+#define TIM_CR1_OPM_Pos           (3U)

+#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */

+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */

+#define TIM_CR1_DIR_Pos           (4U)

+#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */

+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */

+

+#define TIM_CR1_CMS_Pos           (5U)

+#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */

+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */

+#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */

+#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */

+

+#define TIM_CR1_ARPE_Pos          (7U)

+#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */

+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */

+

+#define TIM_CR1_CKD_Pos           (8U)

+#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */

+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */

+#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */

+#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */

+

+#define TIM_CR1_UIFREMAP_Pos      (11U)

+#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */

+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */

+

+/*******************  Bit definition for TIM_CR2 register  ********************/

+#define TIM_CR2_CCPC_Pos          (0U)

+#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */

+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */

+#define TIM_CR2_CCUS_Pos          (2U)

+#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */

+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */

+#define TIM_CR2_CCDS_Pos          (3U)

+#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */

+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */

+

+#define TIM_CR2_MMS_Pos           (4U)

+#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */

+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */

+#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */

+#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */

+#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */

+

+#define TIM_CR2_TI1S_Pos          (7U)

+#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */

+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */

+#define TIM_CR2_OIS1_Pos          (8U)

+#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */

+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */

+#define TIM_CR2_OIS1N_Pos         (9U)

+#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */

+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */

+#define TIM_CR2_OIS2_Pos          (10U)

+#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */

+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */

+#define TIM_CR2_OIS2N_Pos         (11U)

+#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */

+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */

+#define TIM_CR2_OIS3_Pos          (12U)

+#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */

+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */

+#define TIM_CR2_OIS3N_Pos         (13U)

+#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */

+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */

+#define TIM_CR2_OIS4_Pos          (14U)

+#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */

+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */

+#define TIM_CR2_OIS5_Pos          (16U)

+#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */

+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */

+#define TIM_CR2_OIS6_Pos          (17U)

+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */

+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */

+

+#define TIM_CR2_MMS2_Pos          (20U)

+#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */

+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */

+#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */

+#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */

+#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */

+#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */

+

+/*******************  Bit definition for TIM_SMCR register  *******************/

+#define TIM_SMCR_SMS_Pos          (0U)

+#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */

+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */

+#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */

+#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */

+#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */

+#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */

+

+#define TIM_SMCR_TS_Pos           (4U)

+#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */

+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[4:0] bits (Trigger selection) */

+#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)                /*!< 0x00000010 */

+#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)                /*!< 0x00000020 */

+#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)                /*!< 0x00000040 */

+#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)                /*!< 0x00100000 */

+#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)                /*!< 0x00200000 */

+

+#define TIM_SMCR_MSM_Pos          (7U)

+#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */

+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */

+

+#define TIM_SMCR_ETF_Pos          (8U)

+#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */

+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */

+#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */

+#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */

+#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */

+#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */

+

+#define TIM_SMCR_ETPS_Pos         (12U)

+#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */

+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */

+#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */

+#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */

+

+#define TIM_SMCR_ECE_Pos          (14U)

+#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */

+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */

+#define TIM_SMCR_ETP_Pos          (15U)

+#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */

+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */

+

+/*******************  Bit definition for TIM_DIER register  *******************/

+#define TIM_DIER_UIE_Pos          (0U)

+#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */

+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */

+#define TIM_DIER_CC1IE_Pos        (1U)

+#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */

+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */

+#define TIM_DIER_CC2IE_Pos        (2U)

+#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */

+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */

+#define TIM_DIER_CC3IE_Pos        (3U)

+#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */

+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */

+#define TIM_DIER_CC4IE_Pos        (4U)

+#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */

+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */

+#define TIM_DIER_COMIE_Pos        (5U)

+#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */

+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */

+#define TIM_DIER_TIE_Pos          (6U)

+#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */

+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */

+#define TIM_DIER_BIE_Pos          (7U)

+#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */

+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */

+#define TIM_DIER_UDE_Pos          (8U)

+#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */

+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */

+#define TIM_DIER_CC1DE_Pos        (9U)

+#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */

+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */

+#define TIM_DIER_CC2DE_Pos        (10U)

+#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */

+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */

+#define TIM_DIER_CC3DE_Pos        (11U)

+#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */

+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */

+#define TIM_DIER_CC4DE_Pos        (12U)

+#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */

+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */

+#define TIM_DIER_COMDE_Pos        (13U)

+#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */

+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */

+#define TIM_DIER_TDE_Pos          (14U)

+#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */

+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */

+

+/********************  Bit definition for TIM_SR register  ********************/

+#define TIM_SR_UIF_Pos            (0U)

+#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */

+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */

+#define TIM_SR_CC1IF_Pos          (1U)

+#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */

+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */

+#define TIM_SR_CC2IF_Pos          (2U)

+#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */

+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */

+#define TIM_SR_CC3IF_Pos          (3U)

+#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */

+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */

+#define TIM_SR_CC4IF_Pos          (4U)

+#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */

+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */

+#define TIM_SR_COMIF_Pos          (5U)

+#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */

+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */

+#define TIM_SR_TIF_Pos            (6U)

+#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */

+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */

+#define TIM_SR_BIF_Pos            (7U)

+#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */

+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */

+#define TIM_SR_B2IF_Pos           (8U)

+#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */

+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break2 interrupt Flag */

+#define TIM_SR_CC1OF_Pos          (9U)

+#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */

+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */

+#define TIM_SR_CC2OF_Pos          (10U)

+#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */

+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */

+#define TIM_SR_CC3OF_Pos          (11U)

+#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */

+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */

+#define TIM_SR_CC4OF_Pos          (12U)

+#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */

+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */

+#define TIM_SR_CC5IF_Pos          (16U)

+#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */

+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */

+#define TIM_SR_CC6IF_Pos          (17U)

+#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */

+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */

+#define TIM_SR_SBIF_Pos           (13U)

+#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */

+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!< System Break Flag */

+

+/*******************  Bit definition for TIM_EGR register  ********************/

+#define TIM_EGR_UG_Pos            (0U)

+#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */

+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */

+#define TIM_EGR_CC1G_Pos          (1U)

+#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */

+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */

+#define TIM_EGR_CC2G_Pos          (2U)

+#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */

+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */

+#define TIM_EGR_CC3G_Pos          (3U)

+#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */

+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */

+#define TIM_EGR_CC4G_Pos          (4U)

+#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */

+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */

+#define TIM_EGR_COMG_Pos          (5U)

+#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */

+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */

+#define TIM_EGR_TG_Pos            (6U)

+#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */

+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */

+#define TIM_EGR_BG_Pos            (7U)

+#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */

+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */

+#define TIM_EGR_B2G_Pos           (8U)

+#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */

+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break Generation */

+

+

+/******************  Bit definition for TIM_CCMR1 register  *******************/

+#define TIM_CCMR1_CC1S_Pos        (0U)

+#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */

+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */

+#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */

+#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */

+

+#define TIM_CCMR1_OC1FE_Pos       (2U)

+#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */

+#define TIM_CCMR1_OC1PE_Pos       (3U)

+#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */

+

+#define TIM_CCMR1_OC1M_Pos        (4U)

+#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */

+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */

+#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */

+#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */

+#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */

+#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR1_OC1CE_Pos       (7U)

+#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */

+

+#define TIM_CCMR1_CC2S_Pos        (8U)

+#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */

+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */

+#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */

+#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */

+

+#define TIM_CCMR1_OC2FE_Pos       (10U)

+#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */

+#define TIM_CCMR1_OC2PE_Pos       (11U)

+#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */

+

+#define TIM_CCMR1_OC2M_Pos        (12U)

+#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */

+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */

+#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */

+#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */

+#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */

+#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */

+

+#define TIM_CCMR1_OC2CE_Pos       (15U)

+#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */

+

+/*----------------------------------------------------------------------------*/

+

+#define TIM_CCMR1_IC1PSC_Pos      (2U)

+#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */

+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */

+#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */

+

+#define TIM_CCMR1_IC1F_Pos        (4U)

+#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */

+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */

+#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */

+

+#define TIM_CCMR1_IC2PSC_Pos      (10U)

+#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */

+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */

+#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */

+

+#define TIM_CCMR1_IC2F_Pos        (12U)

+#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */

+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */

+#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */

+

+/******************  Bit definition for TIM_CCMR2 register  *******************/

+#define TIM_CCMR2_CC3S_Pos        (0U)

+#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */

+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */

+#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */

+#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */

+

+#define TIM_CCMR2_OC3FE_Pos       (2U)

+#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */

+#define TIM_CCMR2_OC3PE_Pos       (3U)

+#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */

+

+#define TIM_CCMR2_OC3M_Pos        (4U)

+#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */

+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */

+#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR2_OC3CE_Pos       (7U)

+#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */

+

+#define TIM_CCMR2_CC4S_Pos        (8U)

+#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */

+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */

+#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */

+#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */

+

+#define TIM_CCMR2_OC4FE_Pos       (10U)

+#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */

+#define TIM_CCMR2_OC4PE_Pos       (11U)

+#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */

+

+#define TIM_CCMR2_OC4M_Pos        (12U)

+#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */

+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */

+#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */

+

+#define TIM_CCMR2_OC4CE_Pos       (15U)

+#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */

+

+/*----------------------------------------------------------------------------*/

+

+#define TIM_CCMR2_IC3PSC_Pos      (2U)

+#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */

+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */

+#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */

+

+#define TIM_CCMR2_IC3F_Pos        (4U)

+#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */

+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */

+#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */

+

+#define TIM_CCMR2_IC4PSC_Pos      (10U)

+#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */

+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */

+#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */

+

+#define TIM_CCMR2_IC4F_Pos        (12U)

+#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */

+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */

+#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */

+

+/*******************  Bit definition for TIM_CCER register  *******************/

+#define TIM_CCER_CC1E_Pos         (0U)

+#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */

+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */

+#define TIM_CCER_CC1P_Pos         (1U)

+#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */

+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */

+#define TIM_CCER_CC1NE_Pos        (2U)

+#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */

+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */

+#define TIM_CCER_CC1NP_Pos        (3U)

+#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */

+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */

+#define TIM_CCER_CC2E_Pos         (4U)

+#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */

+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */

+#define TIM_CCER_CC2P_Pos         (5U)

+#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */

+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */

+#define TIM_CCER_CC2NE_Pos        (6U)

+#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */

+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */

+#define TIM_CCER_CC2NP_Pos        (7U)

+#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */

+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */

+#define TIM_CCER_CC3E_Pos         (8U)

+#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */

+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */

+#define TIM_CCER_CC3P_Pos         (9U)

+#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */

+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */

+#define TIM_CCER_CC3NE_Pos        (10U)

+#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */

+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */

+#define TIM_CCER_CC3NP_Pos        (11U)

+#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */

+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */

+#define TIM_CCER_CC4E_Pos         (12U)

+#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */

+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */

+#define TIM_CCER_CC4P_Pos         (13U)

+#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */

+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */

+#define TIM_CCER_CC4NP_Pos        (15U)

+#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */

+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */

+#define TIM_CCER_CC5E_Pos         (16U)

+#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */

+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */

+#define TIM_CCER_CC5P_Pos         (17U)

+#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */

+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */

+#define TIM_CCER_CC6E_Pos         (20U)

+#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */

+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */

+#define TIM_CCER_CC6P_Pos         (21U)

+#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */

+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */

+/*******************  Bit definition for TIM_CNT register  ********************/

+#define TIM_CNT_CNT_Pos           (0U)

+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */

+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */

+#define TIM_CNT_UIFCPY_Pos        (31U)

+#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */

+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy */

+/*******************  Bit definition for TIM_PSC register  ********************/

+#define TIM_PSC_PSC_Pos           (0U)

+#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */

+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */

+

+/*******************  Bit definition for TIM_ARR register  ********************/

+#define TIM_ARR_ARR_Pos           (0U)

+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */

+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */

+

+/*******************  Bit definition for TIM_RCR register  ********************/

+#define TIM_RCR_REP_Pos           (0U)

+#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                  /*!< 0x000000FF */

+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */

+

+/*******************  Bit definition for TIM_CCR1 register  *******************/

+#define TIM_CCR1_CCR1_Pos         (0U)

+#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */

+

+/*******************  Bit definition for TIM_CCR2 register  *******************/

+#define TIM_CCR2_CCR2_Pos         (0U)

+#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */

+

+/*******************  Bit definition for TIM_CCR3 register  *******************/

+#define TIM_CCR3_CCR3_Pos         (0U)

+#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */

+

+/*******************  Bit definition for TIM_CCR4 register  *******************/

+#define TIM_CCR4_CCR4_Pos         (0U)

+#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */

+

+/*******************  Bit definition for TIM_CCR5 register  *******************/

+#define TIM_CCR5_CCR5_Pos         (0U)

+#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */

+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */

+#define TIM_CCR5_GC5C1_Pos        (29U)

+#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */

+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */

+#define TIM_CCR5_GC5C2_Pos        (30U)

+#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */

+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */

+#define TIM_CCR5_GC5C3_Pos        (31U)

+#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */

+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */

+

+/*******************  Bit definition for TIM_CCR6 register  *******************/

+#define TIM_CCR6_CCR6_Pos         (0U)

+#define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */

+

+/*******************  Bit definition for TIM_BDTR register  *******************/

+#define TIM_BDTR_DTG_Pos          (0U)

+#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */

+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */

+#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */

+#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */

+#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */

+#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */

+#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */

+#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */

+#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */

+#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */

+

+#define TIM_BDTR_LOCK_Pos         (8U)

+#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */

+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */

+#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */

+#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */

+

+#define TIM_BDTR_OSSI_Pos         (10U)

+#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */

+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */

+#define TIM_BDTR_OSSR_Pos         (11U)

+#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */

+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */

+#define TIM_BDTR_BKE_Pos          (12U)

+#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */

+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break1 */

+#define TIM_BDTR_BKP_Pos          (13U)

+#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */

+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break1 */

+#define TIM_BDTR_AOE_Pos          (14U)

+#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */

+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */

+#define TIM_BDTR_MOE_Pos          (15U)

+#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */

+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */

+

+#define TIM_BDTR_BKF_Pos          (16U)

+#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */

+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break1 */

+#define TIM_BDTR_BK2F_Pos         (20U)

+#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */

+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break2 */

+

+#define TIM_BDTR_BK2E_Pos         (24U)

+#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */

+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break2 */

+#define TIM_BDTR_BK2P_Pos         (25U)

+#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */

+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */

+

+/*******************  Bit definition for TIM_DCR register  ********************/

+#define TIM_DCR_DBA_Pos           (0U)

+#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */

+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */

+#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */

+#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */

+#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */

+#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */

+#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */

+

+#define TIM_DCR_DBL_Pos           (8U)

+#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */

+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */

+#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */

+#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */

+#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */

+#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */

+#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */

+

+/*******************  Bit definition for TIM_DMAR register  *******************/

+#define TIM_DMAR_DMAB_Pos         (0U)

+#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */

+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */

+

+/******************  Bit definition for TIM_CCMR3 register  *******************/

+#define TIM_CCMR3_OC5FE_Pos       (2U)

+#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */

+#define TIM_CCMR3_OC5PE_Pos       (3U)

+#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */

+

+#define TIM_CCMR3_OC5M_Pos        (4U)

+#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */

+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */

+#define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR3_OC5CE_Pos       (7U)

+#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */

+

+#define TIM_CCMR3_OC6FE_Pos       (10U)

+#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 4 Fast enable */

+#define TIM_CCMR3_OC6PE_Pos       (11U)

+#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */

+

+#define TIM_CCMR3_OC6M_Pos        (12U)

+#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */

+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */

+#define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */

+

+#define TIM_CCMR3_OC6CE_Pos       (15U)

+#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 4 Clear Enable */

+/*******************  Bit definition for TIM1_AF1 register  *********************/

+#define TIM1_AF1_BKINE_Pos        (0U)

+#define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */

+#define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */

+#define TIM1_AF1_BKCMP1E_Pos      (1U)

+#define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */

+#define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM1_AF1_BKCMP2E_Pos      (2U)

+#define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */

+#define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit */

+#define TIM1_AF1_BKDF1BK0E_Pos    (8U)

+#define TIM1_AF1_BKDF1BK0E_Msk    (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)            /*!< 0x00000100 */

+#define TIM1_AF1_BKDF1BK0E        TIM1_AF1_BKDF1BK0E_Msk                       /*!<BKDF1BK0E Break input DFSDM Break 0 */

+#define TIM1_AF1_BKINP_Pos        (9U)

+#define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */

+#define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */

+#define TIM1_AF1_BKCMP1P_Pos      (10U)

+#define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */

+#define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM1_AF1_BKCMP2P_Pos      (11U)

+#define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */

+#define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */

+

+#define TIM1_AF1_ETRSEL_Pos       (14U)

+#define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */

+#define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */

+#define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00004000 */

+#define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00008000 */

+#define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00010000 */

+#define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM1_AF2 register  *********************/

+#define TIM1_AF2_BK2INE_Pos       (0U)

+#define TIM1_AF2_BK2INE_Msk       (0x1UL << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */

+#define TIM1_AF2_BK2INE           TIM1_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */

+#define TIM1_AF2_BK2CMP1E_Pos     (1U)

+#define TIM1_AF2_BK2CMP1E_Msk     (0x1UL << TIM1_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */

+#define TIM1_AF2_BK2CMP1E         TIM1_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */

+#define TIM1_AF2_BK2CMP2E_Pos     (2U)

+#define TIM1_AF2_BK2CMP2E_Msk     (0x1UL << TIM1_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */

+#define TIM1_AF2_BK2CMP2E         TIM1_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */

+#define TIM1_AF2_BK2DFBK1E_Pos    (8U)

+#define TIM1_AF2_BK2DFBK1E_Msk    (0x1UL << TIM1_AF2_BK2DFBK1E_Pos)            /*!< 0x00000100 */

+#define TIM1_AF2_BK2DFBK1E        TIM1_AF2_BK2DFBK1E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 1 */

+#define TIM1_AF2_BK2INP_Pos       (9U)

+#define TIM1_AF2_BK2INP_Msk       (0x1UL << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */

+#define TIM1_AF2_BK2INP           TIM1_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */

+#define TIM1_AF2_BK2CMP1P_Pos     (10U)

+#define TIM1_AF2_BK2CMP1P_Msk     (0x1UL << TIM1_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */

+#define TIM1_AF2_BK2CMP1P         TIM1_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */

+#define TIM1_AF2_BK2CMP2P_Pos     (11U)

+#define TIM1_AF2_BK2CMP2P_Msk     (0x1UL << TIM1_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */

+#define TIM1_AF2_BK2CMP2P         TIM1_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */

+

+/*******************  Bit definition for TIM_TISEL register  *********************/

+#define TIM_TISEL_TI1SEL_Pos      (0U)

+#define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */

+#define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/

+#define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000001 */

+#define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000002 */

+#define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000004 */

+#define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000008 */

+

+#define TIM_TISEL_TI2SEL_Pos      (8U)

+#define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */

+#define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/

+#define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000100 */

+#define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000200 */

+#define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000400 */

+#define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000800 */

+

+#define TIM_TISEL_TI3SEL_Pos      (16U)

+#define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */

+#define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/

+#define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00010000 */

+#define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00020000 */

+#define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00040000 */

+#define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00080000 */

+

+#define TIM_TISEL_TI4SEL_Pos      (24U)

+#define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */

+#define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/

+#define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x01000000 */

+#define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x02000000 */

+#define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x04000000 */

+#define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x08000000 */

+

+/*******************  Bit definition for TIM8_AF1 register  *********************/

+#define TIM8_AF1_BKINE_Pos        (0U)

+#define TIM8_AF1_BKINE_Msk        (0x1UL << TIM8_AF1_BKINE_Pos)                /*!< 0x00000001 */

+#define TIM8_AF1_BKINE            TIM8_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */

+#define TIM8_AF1_BKCMP1E_Pos      (1U)

+#define TIM8_AF1_BKCMP1E_Msk      (0x1UL << TIM8_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */

+#define TIM8_AF1_BKCMP1E          TIM8_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM8_AF1_BKCMP2E_Pos      (2U)

+#define TIM8_AF1_BKCMP2E_Msk      (0x1UL << TIM8_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */

+#define TIM8_AF1_BKCMP2E          TIM8_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM8_AF1_BKDFBK2E_Pos     (8U)

+#define TIM8_AF1_BKDFBK2E_Msk     (0x1UL << TIM8_AF1_BKDFBK2E_Pos)             /*!< 0x00000100 */

+#define TIM8_AF1_BKDFBK2E         TIM8_AF1_BKDFBK2E_Msk                        /*!<BKDFBK2E Break input DFSDM Break 2 */

+#define TIM8_AF1_BKINP_Pos        (9U)

+#define TIM8_AF1_BKINP_Msk        (0x1UL << TIM8_AF1_BKINP_Pos)                /*!< 0x00000200 */

+#define TIM8_AF1_BKINP            TIM8_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */

+#define TIM8_AF1_BKCMP1P_Pos      (10U)

+#define TIM8_AF1_BKCMP1P_Msk      (0x1UL << TIM8_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */

+#define TIM8_AF1_BKCMP1P          TIM8_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM8_AF1_BKCMP2P_Pos      (11U)

+#define TIM8_AF1_BKCMP2P_Msk      (0x1UL << TIM8_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */

+#define TIM8_AF1_BKCMP2P          TIM8_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */

+

+#define TIM8_AF1_ETRSEL_Pos       (14U)

+#define TIM8_AF1_ETRSEL_Msk       (0xFUL << TIM8_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */

+#define TIM8_AF1_ETRSEL           TIM8_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */

+#define TIM8_AF1_ETRSEL_0         (0x1UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00004000 */

+#define TIM8_AF1_ETRSEL_1         (0x2UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00008000 */

+#define TIM8_AF1_ETRSEL_2         (0x4UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00010000 */

+#define TIM8_AF1_ETRSEL_3         (0x8UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00020000 */

+/*******************  Bit definition for TIM8_AF2 register  *********************/

+#define TIM8_AF2_BK2INE_Pos       (0U)

+#define TIM8_AF2_BK2INE_Msk       (0x1UL << TIM8_AF2_BK2INE_Pos)               /*!< 0x00000001 */

+#define TIM8_AF2_BK2INE           TIM8_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */

+#define TIM8_AF2_BK2CMP1E_Pos     (1U)

+#define TIM8_AF2_BK2CMP1E_Msk     (0x1UL << TIM8_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */

+#define TIM8_AF2_BK2CMP1E         TIM8_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */

+#define TIM8_AF2_BK2CMP2E_Pos     (2U)

+#define TIM8_AF2_BK2CMP2E_Msk     (0x1UL << TIM8_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */

+#define TIM8_AF2_BK2CMP2E         TIM8_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */

+#define TIM8_AF2_BK2DFBK3E_Pos    (8U)

+#define TIM8_AF2_BK2DFBK3E_Msk    (0x1UL << TIM8_AF2_BK2DFBK3E_Pos)            /*!< 0x00000100 */

+#define TIM8_AF2_BK2DFBK3E        TIM8_AF2_BK2DFBK3E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 3 */

+#define TIM8_AF2_BK2INP_Pos       (9U)

+#define TIM8_AF2_BK2INP_Msk       (0x1UL << TIM8_AF2_BK2INP_Pos)               /*!< 0x00000200 */

+#define TIM8_AF2_BK2INP           TIM8_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */

+#define TIM8_AF2_BK2CMP1P_Pos     (10U)

+#define TIM8_AF2_BK2CMP1P_Msk     (0x1UL << TIM8_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */

+#define TIM8_AF2_BK2CMP1P         TIM8_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */

+#define TIM8_AF2_BK2CMP2P_Pos     (11U)

+#define TIM8_AF2_BK2CMP2P_Msk     (0x1UL << TIM8_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */

+#define TIM8_AF2_BK2CMP2P         TIM8_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */

+

+/*******************  Bit definition for TIM2_AF1 register  *********************/

+#define TIM2_AF1_ETRSEL_Pos      (14U)

+#define TIM2_AF1_ETRSEL_Msk      (0xFUL << TIM2_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM2_AF1_ETRSEL          TIM2_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */

+#define TIM2_AF1_ETRSEL_0        (0x1UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM2_AF1_ETRSEL_1        (0x2UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM2_AF1_ETRSEL_2        (0x4UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM2_AF1_ETRSEL_3        (0x8UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM3_AF1 register  *********************/

+#define TIM3_AF1_ETRSEL_Pos      (14U)

+#define TIM3_AF1_ETRSEL_Msk      (0xFUL << TIM3_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM3_AF1_ETRSEL          TIM3_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */

+#define TIM3_AF1_ETRSEL_0        (0x1UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM3_AF1_ETRSEL_1        (0x2UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM3_AF1_ETRSEL_2        (0x4UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM3_AF1_ETRSEL_3        (0x8UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM5_AF1 register  *********************/

+#define TIM5_AF1_ETRSEL_Pos      (14U)

+#define TIM5_AF1_ETRSEL_Msk      (0xFUL << TIM5_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM5_AF1_ETRSEL          TIM5_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */

+#define TIM5_AF1_ETRSEL_0        (0x1UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM5_AF1_ETRSEL_1        (0x2UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM5_AF1_ETRSEL_2        (0x4UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM5_AF1_ETRSEL_3        (0x8UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM15_AF1 register  *********************/

+#define TIM15_AF1_BKINE_Pos        (0U)

+#define TIM15_AF1_BKINE_Msk        (0x1UL << TIM15_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM15_AF1_BKINE            TIM15_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM15_AF1_BKCMP1E_Pos      (1U)

+#define TIM15_AF1_BKCMP1E_Msk      (0x1UL << TIM15_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM15_AF1_BKCMP1E          TIM15_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM15_AF1_BKCMP2E_Pos      (2U)

+#define TIM15_AF1_BKCMP2E_Msk      (0x1UL << TIM15_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM15_AF1_BKCMP2E          TIM15_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM15_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM15_AF1_BKDF1BK2E_Msk    (0x1UL << TIM15_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM15_AF1_BKDF1BK2E        TIM15_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[0] enable */

+#define TIM15_AF1_BKINP_Pos        (9U)

+#define TIM15_AF1_BKINP_Msk        (0x1UL << TIM15_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM15_AF1_BKINP            TIM15_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM15_AF1_BKCMP1P_Pos      (10U)

+#define TIM15_AF1_BKCMP1P_Msk      (0x1UL << TIM15_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM15_AF1_BKCMP1P          TIM15_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM15_AF1_BKCMP2P_Pos      (11U)

+#define TIM15_AF1_BKCMP2P_Msk      (0x1UL << TIM15_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM15_AF1_BKCMP2P          TIM15_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/*******************  Bit definition for TIM16_ register  *********************/

+#define TIM16_AF1_BKINE_Pos        (0U)

+#define TIM16_AF1_BKINE_Msk        (0x1UL << TIM16_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM16_AF1_BKINE            TIM16_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM16_AF1_BKCMP1E_Pos      (1U)

+#define TIM16_AF1_BKCMP1E_Msk      (0x1UL << TIM16_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM16_AF1_BKCMP1E          TIM16_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM16_AF1_BKCMP2E_Pos      (2U)

+#define TIM16_AF1_BKCMP2E_Msk      (0x1UL << TIM16_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM16_AF1_BKCMP2E          TIM16_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM16_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM16_AF1_BKDF1BK2E_Msk    (0x1UL << TIM16_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM16_AF1_BKDF1BK2E        TIM16_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[1] enable */

+#define TIM16_AF1_BKINP_Pos        (9U)

+#define TIM16_AF1_BKINP_Msk        (0x1UL << TIM16_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM16_AF1_BKINP            TIM16_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM16_AF1_BKCMP1P_Pos      (10U)

+#define TIM16_AF1_BKCMP1P_Msk      (0x1UL << TIM16_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM16_AF1_BKCMP1P          TIM16_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM16_AF1_BKCMP2P_Pos      (11U)

+#define TIM16_AF1_BKCMP2P_Msk      (0x1UL << TIM16_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM16_AF1_BKCMP2P          TIM16_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/*******************  Bit definition for TIM17_AF1 register  *********************/

+#define TIM17_AF1_BKINE_Pos        (0U)

+#define TIM17_AF1_BKINE_Msk        (0x1UL << TIM17_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM17_AF1_BKINE            TIM17_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM17_AF1_BKCMP1E_Pos      (1U)

+#define TIM17_AF1_BKCMP1E_Msk      (0x1UL << TIM17_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM17_AF1_BKCMP1E          TIM17_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM17_AF1_BKCMP2E_Pos      (2U)

+#define TIM17_AF1_BKCMP2E_Msk      (0x1UL << TIM17_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM17_AF1_BKCMP2E          TIM17_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM17_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM17_AF1_BKDF1BK2E_Msk    (0x1UL << TIM17_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM17_AF1_BKDF1BK2E        TIM17_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[2] enable */

+#define TIM17_AF1_BKINP_Pos        (9U)

+#define TIM17_AF1_BKINP_Msk        (0x1UL << TIM17_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM17_AF1_BKINP            TIM17_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM17_AF1_BKCMP1P_Pos      (10U)

+#define TIM17_AF1_BKCMP1P_Msk      (0x1UL << TIM17_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM17_AF1_BKCMP1P          TIM17_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM17_AF1_BKCMP2P_Pos      (11U)

+#define TIM17_AF1_BKCMP2P_Msk      (0x1UL << TIM17_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM17_AF1_BKCMP2P          TIM17_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Low Power Timer (LPTTIM)                           */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for LPTIM_ISR register  *******************/

+#define LPTIM_ISR_CMPM_Pos          (0U)

+#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */

+#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */

+#define LPTIM_ISR_ARRM_Pos          (1U)

+#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */

+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */

+#define LPTIM_ISR_EXTTRIG_Pos       (2U)

+#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */

+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */

+#define LPTIM_ISR_CMPOK_Pos         (3U)

+#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */

+#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */

+#define LPTIM_ISR_ARROK_Pos         (4U)

+#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */

+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */

+#define LPTIM_ISR_UP_Pos            (5U)

+#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */

+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */

+#define LPTIM_ISR_DOWN_Pos          (6U)

+#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */

+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */

+

+/******************  Bit definition for LPTIM_ICR register  *******************/

+#define LPTIM_ICR_CMPMCF_Pos        (0U)

+#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */

+#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */

+#define LPTIM_ICR_ARRMCF_Pos        (1U)

+#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */

+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */

+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)

+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */

+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */

+#define LPTIM_ICR_CMPOKCF_Pos       (3U)

+#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */

+#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */

+#define LPTIM_ICR_ARROKCF_Pos       (4U)

+#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */

+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */

+#define LPTIM_ICR_UPCF_Pos          (5U)

+#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */

+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */

+#define LPTIM_ICR_DOWNCF_Pos        (6U)

+#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */

+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */

+

+/******************  Bit definition for LPTIM_IER register ********************/

+#define LPTIM_IER_CMPMIE_Pos        (0U)

+#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */

+#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */

+#define LPTIM_IER_ARRMIE_Pos        (1U)

+#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */

+#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */

+#define LPTIM_IER_EXTTRIGIE_Pos     (2U)

+#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */

+#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */

+#define LPTIM_IER_CMPOKIE_Pos       (3U)

+#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */

+#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */

+#define LPTIM_IER_ARROKIE_Pos       (4U)

+#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */

+#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */

+#define LPTIM_IER_UPIE_Pos          (5U)

+#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */

+#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */

+#define LPTIM_IER_DOWNIE_Pos        (6U)

+#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */

+#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */

+

+/******************  Bit definition for LPTIM_CFGR register *******************/

+#define LPTIM_CFGR_CKSEL_Pos        (0U)

+#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */

+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */

+

+#define LPTIM_CFGR_CKPOL_Pos        (1U)

+#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */

+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */

+#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */

+#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */

+

+#define LPTIM_CFGR_CKFLT_Pos        (3U)

+#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */

+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */

+#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */

+#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */

+

+#define LPTIM_CFGR_TRGFLT_Pos       (6U)

+#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */

+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */

+#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */

+#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */

+

+#define LPTIM_CFGR_PRESC_Pos        (9U)

+#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */

+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */

+#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */

+#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */

+#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */

+

+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)

+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */

+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */

+#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */

+#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */

+#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */

+

+#define LPTIM_CFGR_TRIGEN_Pos       (17U)

+#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */

+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */

+#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */

+#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */

+

+#define LPTIM_CFGR_TIMOUT_Pos       (19U)

+#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */

+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */

+#define LPTIM_CFGR_WAVE_Pos         (20U)

+#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */

+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */

+#define LPTIM_CFGR_WAVPOL_Pos       (21U)

+#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */

+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */

+#define LPTIM_CFGR_PRELOAD_Pos      (22U)

+#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */

+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */

+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)

+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */

+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */

+#define LPTIM_CFGR_ENC_Pos          (24U)

+#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */

+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */

+

+/******************  Bit definition for LPTIM_CR register  ********************/

+#define LPTIM_CR_ENABLE_Pos         (0U)

+#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */

+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */

+#define LPTIM_CR_SNGSTRT_Pos        (1U)

+#define LPTIM_CR_SNGSTRT_Msk        (0x40001UL << LPTIM_CR_SNGSTRT_Pos)        /*!< 0x00080002 */

+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */

+#define LPTIM_CR_CNTSTRT_Pos        (2U)

+#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */

+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */

+#define LPTIM_CR_COUNTRST_Pos       (3U)

+#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */

+#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Timer Counter reset in synchronous mode*/

+#define LPTIM_CR_RSTARE_Pos         (4U)

+#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */

+#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Timer Counter reset after read enable (asynchronously)*/

+

+

+/******************  Bit definition for LPTIM_CMP register  *******************/

+#define LPTIM_CMP_CMP_Pos           (0U)

+#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */

+

+/******************  Bit definition for LPTIM_ARR register  *******************/

+#define LPTIM_ARR_ARR_Pos           (0U)

+#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */

+

+/******************  Bit definition for LPTIM_CNT register  *******************/

+#define LPTIM_CNT_CNT_Pos           (0U)

+#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */

+

+/******************  Bit definition for LPTIM_CFGR2 register  *****************/

+#define LPTIM_CFGR2_IN1SEL_Pos      (0U)

+#define LPTIM_CFGR2_IN1SEL_Msk      (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000003 */

+#define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< IN1SEL[1:0] bits (Remap selection) */

+#define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000001 */

+#define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000002 */

+#define LPTIM_CFGR2_IN2SEL_Pos      (4U)

+#define LPTIM_CFGR2_IN2SEL_Msk      (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000030 */

+#define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< IN2SEL[5:4] bits (Remap selection) */

+#define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000010 */

+#define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000020 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      Analog Comparators (COMP)                             */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for COMP_SR register  ********************/

+#define COMP_SR_C1VAL_Pos            (0U)

+#define COMP_SR_C1VAL_Msk            (0x1UL << COMP_SR_C1VAL_Pos)              /*!< 0x00000001 */

+#define COMP_SR_C1VAL                COMP_SR_C1VAL_Msk

+#define COMP_SR_C2VAL_Pos            (1U)

+#define COMP_SR_C2VAL_Msk            (0x1UL << COMP_SR_C2VAL_Pos)              /*!< 0x00000002 */

+#define COMP_SR_C2VAL                COMP_SR_C2VAL_Msk

+#define COMP_SR_C1IF_Pos             (16U)

+#define COMP_SR_C1IF_Msk             (0x1UL << COMP_SR_C1IF_Pos)               /*!< 0x00010000 */

+#define COMP_SR_C1IF                 COMP_SR_C1IF_Msk

+#define COMP_SR_C2IF_Pos             (17U)

+#define COMP_SR_C2IF_Msk             (0x1UL << COMP_SR_C2IF_Pos)               /*!< 0x00020000 */

+#define COMP_SR_C2IF                 COMP_SR_C2IF_Msk

+/*******************  Bit definition for COMP_ICFR register  ********************/

+#define COMP_ICFR_C1IF_Pos           (16U)

+#define COMP_ICFR_C1IF_Msk           (0x1UL << COMP_ICFR_C1IF_Pos)             /*!< 0x00010000 */

+#define COMP_ICFR_C1IF               COMP_ICFR_C1IF_Msk

+#define COMP_ICFR_C2IF_Pos           (17U)

+#define COMP_ICFR_C2IF_Msk           (0x1UL << COMP_ICFR_C2IF_Pos)             /*!< 0x00020000 */

+#define COMP_ICFR_C2IF               COMP_ICFR_C2IF_Msk

+/*******************  Bit definition for COMP_OR register  ********************/

+#define COMP_OR_AFOPA6_Pos           (0U)

+#define COMP_OR_AFOPA6_Msk           (0x1UL << COMP_OR_AFOPA6_Pos)             /*!< 0x00000001 */

+#define COMP_OR_AFOPA6               COMP_OR_AFOPA6_Msk

+#define COMP_OR_AFOPA8_Pos           (1U)

+#define COMP_OR_AFOPA8_Msk           (0x1UL << COMP_OR_AFOPA8_Pos)             /*!< 0x00000002 */

+#define COMP_OR_AFOPA8               COMP_OR_AFOPA8_Msk

+#define COMP_OR_AFOPB12_Pos          (2U)

+#define COMP_OR_AFOPB12_Msk          (0x1UL << COMP_OR_AFOPB12_Pos)            /*!< 0x00000004 */

+#define COMP_OR_AFOPB12              COMP_OR_AFOPB12_Msk

+#define COMP_OR_AFOPE6_Pos           (3U)

+#define COMP_OR_AFOPE6_Msk           (0x1UL << COMP_OR_AFOPE6_Pos)             /*!< 0x00000008 */

+#define COMP_OR_AFOPE6               COMP_OR_AFOPE6_Msk

+#define COMP_OR_AFOPE15_Pos          (4U)

+#define COMP_OR_AFOPE15_Msk          (0x1UL << COMP_OR_AFOPE15_Pos)            /*!< 0x00000010 */

+#define COMP_OR_AFOPE15              COMP_OR_AFOPE15_Msk

+#define COMP_OR_AFOPG2_Pos           (5U)

+#define COMP_OR_AFOPG2_Msk           (0x1UL << COMP_OR_AFOPG2_Pos)             /*!< 0x00000020 */

+#define COMP_OR_AFOPG2               COMP_OR_AFOPG2_Msk

+#define COMP_OR_AFOPG3_Pos           (6U)

+#define COMP_OR_AFOPG3_Msk           (0x1UL << COMP_OR_AFOPG3_Pos)             /*!< 0x00000040 */

+#define COMP_OR_AFOPG3               COMP_OR_AFOPG3_Msk

+#define COMP_OR_AFOPG4_Pos           (7U)

+#define COMP_OR_AFOPG4_Msk           (0x1UL << COMP_OR_AFOPG4_Pos)             /*!< 0x00000080 */

+#define COMP_OR_AFOPG4               COMP_OR_AFOPG4_Msk

+#define COMP_OR_AFOPI1_Pos           (8U)

+#define COMP_OR_AFOPI1_Msk           (0x1UL << COMP_OR_AFOPI1_Pos)             /*!< 0x00000100 */

+#define COMP_OR_AFOPI1               COMP_OR_AFOPI1_Msk

+#define COMP_OR_AFOPI4_Pos           (9U)

+#define COMP_OR_AFOPI4_Msk           (0x1UL << COMP_OR_AFOPI4_Pos)             /*!< 0x00000200 */

+#define COMP_OR_AFOPI4               COMP_OR_AFOPI4_Msk

+#define COMP_OR_AFOPK2_Pos           (10U)

+#define COMP_OR_AFOPK2_Msk           (0x1UL << COMP_OR_AFOPK2_Pos)             /*!< 0x00000400 */

+#define COMP_OR_AFOPK2               COMP_OR_AFOPK2_Msk

+

+/*!< ******************  Bit definition for COMP_CFGRx register  ********************/

+#define COMP_CFGRx_EN_Pos            (0U)

+#define COMP_CFGRx_EN_Msk            (0x1UL << COMP_CFGRx_EN_Pos)              /*!< 0x00000001 */

+#define COMP_CFGRx_EN                COMP_CFGRx_EN_Msk                         /*!< COMPx enable bit                     */

+#define COMP_CFGRx_BRGEN_Pos         (1U)

+#define COMP_CFGRx_BRGEN_Msk         (0x1UL << COMP_CFGRx_BRGEN_Pos)           /*!< 0x00000002 */

+#define COMP_CFGRx_BRGEN             COMP_CFGRx_BRGEN_Msk                      /*!< COMPx Scaler bridge enable           */

+#define COMP_CFGRx_SCALEN_Pos        (2U)

+#define COMP_CFGRx_SCALEN_Msk        (0x1UL << COMP_CFGRx_SCALEN_Pos)          /*!< 0x00000004 */

+#define COMP_CFGRx_SCALEN            COMP_CFGRx_SCALEN_Msk                     /*!< COMPx Voltage scaler enable bit      */

+#define COMP_CFGRx_POLARITY_Pos      (3U)

+#define COMP_CFGRx_POLARITY_Msk      (0x1UL << COMP_CFGRx_POLARITY_Pos)        /*!< 0x00000008 */

+#define COMP_CFGRx_POLARITY          COMP_CFGRx_POLARITY_Msk                   /*!< COMPx  polarity selection bit        */

+#define COMP_CFGRx_WINMODE_Pos       (4U)

+#define COMP_CFGRx_WINMODE_Msk       (0x1UL << COMP_CFGRx_WINMODE_Pos)         /*!< 0x00000010 */

+#define COMP_CFGRx_WINMODE           COMP_CFGRx_WINMODE_Msk                    /*!< COMPx Windows mode selection bit     */

+#define COMP_CFGRx_ITEN_Pos          (6U)

+#define COMP_CFGRx_ITEN_Msk          (0x1UL << COMP_CFGRx_ITEN_Pos)            /*!< 0x00000040 */

+#define COMP_CFGRx_ITEN              COMP_CFGRx_ITEN_Msk                       /*!< COMPx  interrupt enable              */

+#define COMP_CFGRx_HYST_Pos          (8U)

+#define COMP_CFGRx_HYST_Msk          (0x3UL << COMP_CFGRx_HYST_Pos)            /*!< 0x00000300 */

+#define COMP_CFGRx_HYST              COMP_CFGRx_HYST_Msk                       /*!< COMPx  hysteresis selection bits     */

+#define COMP_CFGRx_HYST_0            (0x1UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000100 */

+#define COMP_CFGRx_HYST_1            (0x2UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000200 */

+#define COMP_CFGRx_PWRMODE_Pos       (12U)

+#define COMP_CFGRx_PWRMODE_Msk       (0x3UL << COMP_CFGRx_PWRMODE_Pos)         /*!< 0x00003000 */

+#define COMP_CFGRx_PWRMODE           COMP_CFGRx_PWRMODE_Msk                    /*!< COMPx Power Mode of the comparator   */

+#define COMP_CFGRx_PWRMODE_0         (0x1UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00001000 */

+#define COMP_CFGRx_PWRMODE_1         (0x2UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00002000 */

+#define COMP_CFGRx_INMSEL_Pos        (16U)

+#define COMP_CFGRx_INMSEL_Msk        (0x7UL << COMP_CFGRx_INMSEL_Pos)          /*!< 0x00070000 */

+#define COMP_CFGRx_INMSEL            COMP_CFGRx_INMSEL_Msk                     /*!< COMPx  input minus selection bit  */

+#define COMP_CFGRx_INMSEL_0          (0x1UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00010000 */

+#define COMP_CFGRx_INMSEL_1          (0x2UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00020000 */

+#define COMP_CFGRx_INMSEL_2          (0x4UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00040000 */

+#define COMP_CFGRx_INPSEL_Pos        (20U)

+#define COMP_CFGRx_INPSEL_Msk        (0x1UL << COMP_CFGRx_INPSEL_Pos)          /*!< 0x00100000 */

+#define COMP_CFGRx_INPSEL            COMP_CFGRx_INPSEL_Msk                     /*!< COMPx  input plus selection bit       */

+#define COMP_CFGRx_BLANKING_Pos      (24U)

+#define COMP_CFGRx_BLANKING_Msk      (0xFUL << COMP_CFGRx_BLANKING_Pos)        /*!< 0x0F000000 */

+#define COMP_CFGRx_BLANKING          COMP_CFGRx_BLANKING_Msk                   /*!< COMPx  blanking source selection bits */

+#define COMP_CFGRx_BLANKING_0        (0x1UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x01000000 */

+#define COMP_CFGRx_BLANKING_1        (0x2UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x02000000 */

+#define COMP_CFGRx_BLANKING_2        (0x4UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x04000000 */

+#define COMP_CFGRx_LOCK_Pos          (31U)

+#define COMP_CFGRx_LOCK_Msk          (0x1UL << COMP_CFGRx_LOCK_Pos)            /*!< 0x80000000 */

+#define COMP_CFGRx_LOCK              COMP_CFGRx_LOCK_Msk                       /*!< COMPx Lock Bit                        */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for USART_CR1 register  *******************/

+#define USART_CR1_UE_Pos                (0U)

+#define USART_CR1_UE_Msk                (0x1UL << USART_CR1_UE_Pos)            /*!< 0x00000001 */

+#define USART_CR1_UE                    USART_CR1_UE_Msk                       /*!< USART Enable */

+#define USART_CR1_UESM_Pos              (1U)

+#define USART_CR1_UESM_Msk              (0x1UL << USART_CR1_UESM_Pos)          /*!< 0x00000002 */

+#define USART_CR1_UESM                  USART_CR1_UESM_Msk                     /*!< USART Enable in STOP Mode */

+#define USART_CR1_RE_Pos                (2U)

+#define USART_CR1_RE_Msk                (0x1UL << USART_CR1_RE_Pos)            /*!< 0x00000004 */

+#define USART_CR1_RE                    USART_CR1_RE_Msk                       /*!< Receiver Enable */

+#define USART_CR1_TE_Pos                (3U)

+#define USART_CR1_TE_Msk                (0x1UL << USART_CR1_TE_Pos)            /*!< 0x00000008 */

+#define USART_CR1_TE                    USART_CR1_TE_Msk                       /*!< Transmitter Enable */

+#define USART_CR1_IDLEIE_Pos            (4U)

+#define USART_CR1_IDLEIE_Msk            (0x1UL << USART_CR1_IDLEIE_Pos)        /*!< 0x00000010 */

+#define USART_CR1_IDLEIE                USART_CR1_IDLEIE_Msk                   /*!< IDLE Interrupt Enable */

+#define USART_CR1_RXNEIE_RXFNEIE_Pos    (5U)

+#define USART_CR1_RXNEIE_RXFNEIE_Msk    (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */

+#define USART_CR1_RXNEIE_RXFNEIE        USART_CR1_RXNEIE_RXFNEIE_Msk           /*!< RXNE and RX FIFO Not Empty Interrupt Enable */

+#define USART_CR1_TCIE_Pos              (6U)

+#define USART_CR1_TCIE_Msk              (0x1UL << USART_CR1_TCIE_Pos)          /*!< 0x00000040 */

+#define USART_CR1_TCIE                  USART_CR1_TCIE_Msk                     /*!< Transmission Complete Interrupt Enable */

+#define USART_CR1_TXEIE_TXFNFIE_Pos     (7U)

+#define USART_CR1_TXEIE_TXFNFIE_Msk     (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */

+#define USART_CR1_TXEIE_TXFNFIE         USART_CR1_TXEIE_TXFNFIE_Msk            /*!< TXE and TX FIFO Not Full Interrupt Enable */

+#define USART_CR1_PEIE_Pos              (8U)

+#define USART_CR1_PEIE_Msk              (0x1UL << USART_CR1_PEIE_Pos)          /*!< 0x00000100 */

+#define USART_CR1_PEIE                  USART_CR1_PEIE_Msk                     /*!< PE Interrupt Enable */

+#define USART_CR1_PS_Pos                (9U)

+#define USART_CR1_PS_Msk                (0x1UL << USART_CR1_PS_Pos)            /*!< 0x00000200 */

+#define USART_CR1_PS                    USART_CR1_PS_Msk                       /*!< Parity Selection */

+#define USART_CR1_PCE_Pos               (10U)

+#define USART_CR1_PCE_Msk               (0x1UL << USART_CR1_PCE_Pos)           /*!< 0x00000400 */

+#define USART_CR1_PCE                   USART_CR1_PCE_Msk                      /*!< Parity Control Enable */

+#define USART_CR1_WAKE_Pos              (11U)

+#define USART_CR1_WAKE_Msk              (0x1UL << USART_CR1_WAKE_Pos)          /*!< 0x00000800 */

+#define USART_CR1_WAKE                  USART_CR1_WAKE_Msk                     /*!< Receiver Wakeup method */

+#define USART_CR1_M_Pos                 (12U)

+#define USART_CR1_M_Msk                 (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */

+#define USART_CR1_M                     USART_CR1_M_Msk                        /*!< Word length */

+#define USART_CR1_M0_Pos                (12U)

+#define USART_CR1_M0_Msk                (0x1UL << USART_CR1_M0_Pos)            /*!< 0x00001000 */

+#define USART_CR1_M0                    USART_CR1_M0_Msk                       /*!< Word length - Bit 0 */

+#define USART_CR1_MME_Pos               (13U)

+#define USART_CR1_MME_Msk               (0x1UL << USART_CR1_MME_Pos)           /*!< 0x00002000 */

+#define USART_CR1_MME                   USART_CR1_MME_Msk                      /*!< Mute Mode Enable */

+#define USART_CR1_CMIE_Pos              (14U)

+#define USART_CR1_CMIE_Msk              (0x1UL << USART_CR1_CMIE_Pos)          /*!< 0x00004000 */

+#define USART_CR1_CMIE                  USART_CR1_CMIE_Msk                     /*!< Character match interrupt enable */

+#define USART_CR1_OVER8_Pos             (15U)

+#define USART_CR1_OVER8_Msk             (0x1UL << USART_CR1_OVER8_Pos)         /*!< 0x00008000 */

+#define USART_CR1_OVER8                 USART_CR1_OVER8_Msk                    /*!< Oversampling by 8-bit or 16-bit mode */

+#define USART_CR1_DEDT_Pos              (16U)

+#define USART_CR1_DEDT_Msk              (0x1FUL << USART_CR1_DEDT_Pos)         /*!< 0x001F0000 */

+#define USART_CR1_DEDT                  USART_CR1_DEDT_Msk                     /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */

+#define USART_CR1_DEDT_0                (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */

+#define USART_CR1_DEDT_1                (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */

+#define USART_CR1_DEDT_2                (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */

+#define USART_CR1_DEDT_3                (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */

+#define USART_CR1_DEDT_4                (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */

+#define USART_CR1_DEAT_Pos              (21U)

+#define USART_CR1_DEAT_Msk              (0x1FUL << USART_CR1_DEAT_Pos)         /*!< 0x03E00000 */

+#define USART_CR1_DEAT                  USART_CR1_DEAT_Msk                     /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */

+#define USART_CR1_DEAT_0                (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */

+#define USART_CR1_DEAT_1                (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */

+#define USART_CR1_DEAT_2                (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */

+#define USART_CR1_DEAT_3                (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */

+#define USART_CR1_DEAT_4                (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */

+#define USART_CR1_RTOIE_Pos             (26U)

+#define USART_CR1_RTOIE_Msk             (0x1UL << USART_CR1_RTOIE_Pos)         /*!< 0x04000000 */

+#define USART_CR1_RTOIE                 USART_CR1_RTOIE_Msk                    /*!< Receive Time Out interrupt enable */

+#define USART_CR1_EOBIE_Pos             (27U)

+#define USART_CR1_EOBIE_Msk             (0x1UL << USART_CR1_EOBIE_Pos)         /*!< 0x08000000 */

+#define USART_CR1_EOBIE                 USART_CR1_EOBIE_Msk                    /*!< End of Block interrupt enable */

+#define USART_CR1_M1_Pos                (28U)

+#define USART_CR1_M1_Msk                (0x1UL << USART_CR1_M1_Pos)            /*!< 0x10000000 */

+#define USART_CR1_M1                    USART_CR1_M1_Msk                       /*!< Word length - Bit 1 */

+#define USART_CR1_FIFOEN_Pos            (29U)

+#define USART_CR1_FIFOEN_Msk            (0x1UL << USART_CR1_FIFOEN_Pos)        /*!< 0x20000000 */

+#define USART_CR1_FIFOEN                USART_CR1_FIFOEN_Msk                   /*!< FIFO mode enable */

+#define USART_CR1_TXFEIE_Pos            (30U)

+#define USART_CR1_TXFEIE_Msk            (0x1UL << USART_CR1_TXFEIE_Pos)        /*!< 0x40000000 */

+#define USART_CR1_TXFEIE                USART_CR1_TXFEIE_Msk                   /*!< TXFIFO empty interrupt enable */

+#define USART_CR1_RXFFIE_Pos            (31U)

+#define USART_CR1_RXFFIE_Msk            (0x1UL << USART_CR1_RXFFIE_Pos)        /*!< 0x80000000 */

+#define USART_CR1_RXFFIE                USART_CR1_RXFFIE_Msk                   /*!< RXFIFO Full interrupt enable */

+

+/* Legacy define */

+#define  USART_CR1_RXNEIE  USART_CR1_RXNEIE_RXFNEIE

+#define  USART_CR1_TXEIE   USART_CR1_TXEIE_TXFNFIE

+

+/******************  Bit definition for USART_CR2 register  *******************/

+#define USART_CR2_SLVEN_Pos             (0U)

+#define USART_CR2_SLVEN_Msk             (0x1UL << USART_CR2_SLVEN_Pos)         /*!< 0x00000001 */

+#define USART_CR2_SLVEN                 USART_CR2_SLVEN_Msk                    /*!< Synchronous Slave mode Enable */

+#define USART_CR2_DIS_NSS_Pos           (3U)

+#define USART_CR2_DIS_NSS_Msk           (0x1UL << USART_CR2_DIS_NSS_Pos)       /*!< 0x00000008 */

+#define USART_CR2_DIS_NSS               USART_CR2_DIS_NSS_Msk                  /*!< Negative Slave Select (NSS) pin management */

+#define USART_CR2_ADDM7_Pos             (4U)

+#define USART_CR2_ADDM7_Msk             (0x1UL << USART_CR2_ADDM7_Pos)         /*!< 0x00000010 */

+#define USART_CR2_ADDM7                 USART_CR2_ADDM7_Msk                    /*!< 7-bit or 4-bit Address Detection */

+#define USART_CR2_LBDL_Pos              (5U)

+#define USART_CR2_LBDL_Msk              (0x1UL << USART_CR2_LBDL_Pos)          /*!< 0x00000020 */

+#define USART_CR2_LBDL                  USART_CR2_LBDL_Msk                     /*!< LIN Break Detection Length */

+#define USART_CR2_LBDIE_Pos             (6U)

+#define USART_CR2_LBDIE_Msk             (0x1UL << USART_CR2_LBDIE_Pos)         /*!< 0x00000040 */

+#define USART_CR2_LBDIE                 USART_CR2_LBDIE_Msk                    /*!< LIN Break Detection Interrupt Enable */

+#define USART_CR2_LBCL_Pos              (8U)

+#define USART_CR2_LBCL_Msk              (0x1UL << USART_CR2_LBCL_Pos)          /*!< 0x00000100 */

+#define USART_CR2_LBCL                  USART_CR2_LBCL_Msk                     /*!< Last Bit Clock pulse */

+#define USART_CR2_CPHA_Pos              (9U)

+#define USART_CR2_CPHA_Msk              (0x1UL << USART_CR2_CPHA_Pos)          /*!< 0x00000200 */

+#define USART_CR2_CPHA                  USART_CR2_CPHA_Msk                     /*!< Clock Phase */

+#define USART_CR2_CPOL_Pos              (10U)

+#define USART_CR2_CPOL_Msk              (0x1UL << USART_CR2_CPOL_Pos)          /*!< 0x00000400 */

+#define USART_CR2_CPOL                  USART_CR2_CPOL_Msk                     /*!< Clock Polarity */

+#define USART_CR2_CLKEN_Pos             (11U)

+#define USART_CR2_CLKEN_Msk             (0x1UL << USART_CR2_CLKEN_Pos)         /*!< 0x00000800 */

+#define USART_CR2_CLKEN                 USART_CR2_CLKEN_Msk                    /*!< Clock Enable */

+#define USART_CR2_STOP_Pos              (12U)

+#define USART_CR2_STOP_Msk              (0x3UL << USART_CR2_STOP_Pos)          /*!< 0x00003000 */

+#define USART_CR2_STOP                  USART_CR2_STOP_Msk                     /*!< STOP[1:0] bits (STOP bits) */

+#define USART_CR2_STOP_0                (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */

+#define USART_CR2_STOP_1                (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */

+#define USART_CR2_LINEN_Pos             (14U)

+#define USART_CR2_LINEN_Msk             (0x1UL << USART_CR2_LINEN_Pos)         /*!< 0x00004000 */

+#define USART_CR2_LINEN                 USART_CR2_LINEN_Msk                    /*!< LIN mode enable */

+#define USART_CR2_SWAP_Pos              (15U)

+#define USART_CR2_SWAP_Msk              (0x1UL << USART_CR2_SWAP_Pos)          /*!< 0x00008000 */

+#define USART_CR2_SWAP                  USART_CR2_SWAP_Msk                     /*!< SWAP TX/RX pins */

+#define USART_CR2_RXINV_Pos             (16U)

+#define USART_CR2_RXINV_Msk             (0x1UL << USART_CR2_RXINV_Pos)         /*!< 0x00010000 */

+#define USART_CR2_RXINV                 USART_CR2_RXINV_Msk                    /*!< RX pin active level inversion */

+#define USART_CR2_TXINV_Pos             (17U)

+#define USART_CR2_TXINV_Msk             (0x1UL << USART_CR2_TXINV_Pos)         /*!< 0x00020000 */

+#define USART_CR2_TXINV                 USART_CR2_TXINV_Msk                    /*!< TX pin active level inversion */

+#define USART_CR2_DATAINV_Pos           (18U)

+#define USART_CR2_DATAINV_Msk           (0x1UL << USART_CR2_DATAINV_Pos)       /*!< 0x00040000 */

+#define USART_CR2_DATAINV               USART_CR2_DATAINV_Msk                  /*!< Binary data inversion */

+#define USART_CR2_MSBFIRST_Pos          (19U)

+#define USART_CR2_MSBFIRST_Msk          (0x1UL << USART_CR2_MSBFIRST_Pos)      /*!< 0x00080000 */

+#define USART_CR2_MSBFIRST              USART_CR2_MSBFIRST_Msk                 /*!< Most Significant Bit First */

+#define USART_CR2_ABREN_Pos             (20U)

+#define USART_CR2_ABREN_Msk             (0x1UL << USART_CR2_ABREN_Pos)         /*!< 0x00100000 */

+#define USART_CR2_ABREN                 USART_CR2_ABREN_Msk                    /*!< Auto Baud-Rate Enable*/

+#define USART_CR2_ABRMODE_Pos           (21U)

+#define USART_CR2_ABRMODE_Msk           (0x3UL << USART_CR2_ABRMODE_Pos)       /*!< 0x00600000 */

+#define USART_CR2_ABRMODE               USART_CR2_ABRMODE_Msk                  /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */

+#define USART_CR2_ABRMODE_0             (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */

+#define USART_CR2_ABRMODE_1             (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */

+#define USART_CR2_RTOEN_Pos             (23U)

+#define USART_CR2_RTOEN_Msk             (0x1UL << USART_CR2_RTOEN_Pos)         /*!< 0x00800000 */

+#define USART_CR2_RTOEN                 USART_CR2_RTOEN_Msk                    /*!< Receiver Time-Out enable */

+#define USART_CR2_ADD_Pos               (24U)

+#define USART_CR2_ADD_Msk               (0xFFUL << USART_CR2_ADD_Pos)          /*!< 0xFF000000 */

+#define USART_CR2_ADD                   USART_CR2_ADD_Msk                      /*!< Address of the USART node */

+

+/******************  Bit definition for USART_CR3 register  *******************/

+#define USART_CR3_EIE_Pos               (0U)

+#define USART_CR3_EIE_Msk               (0x1UL << USART_CR3_EIE_Pos)           /*!< 0x00000001 */

+#define USART_CR3_EIE                   USART_CR3_EIE_Msk                      /*!< Error Interrupt Enable */

+#define USART_CR3_IREN_Pos              (1U)

+#define USART_CR3_IREN_Msk              (0x1UL << USART_CR3_IREN_Pos)          /*!< 0x00000002 */

+#define USART_CR3_IREN                  USART_CR3_IREN_Msk                     /*!< IrDA mode Enable */

+#define USART_CR3_IRLP_Pos              (2U)

+#define USART_CR3_IRLP_Msk              (0x1UL << USART_CR3_IRLP_Pos)          /*!< 0x00000004 */

+#define USART_CR3_IRLP                  USART_CR3_IRLP_Msk                     /*!< IrDA Low-Power */

+#define USART_CR3_HDSEL_Pos             (3U)

+#define USART_CR3_HDSEL_Msk             (0x1UL << USART_CR3_HDSEL_Pos)         /*!< 0x00000008 */

+#define USART_CR3_HDSEL                 USART_CR3_HDSEL_Msk                    /*!< Half-Duplex Selection */

+#define USART_CR3_NACK_Pos              (4U)

+#define USART_CR3_NACK_Msk              (0x1UL << USART_CR3_NACK_Pos)          /*!< 0x00000010 */

+#define USART_CR3_NACK                  USART_CR3_NACK_Msk                     /*!< SmartCard NACK enable */

+#define USART_CR3_SCEN_Pos              (5U)

+#define USART_CR3_SCEN_Msk              (0x1UL << USART_CR3_SCEN_Pos)          /*!< 0x00000020 */

+#define USART_CR3_SCEN                  USART_CR3_SCEN_Msk                     /*!< SmartCard mode enable */

+#define USART_CR3_DMAR_Pos              (6U)

+#define USART_CR3_DMAR_Msk              (0x1UL << USART_CR3_DMAR_Pos)          /*!< 0x00000040 */

+#define USART_CR3_DMAR                  USART_CR3_DMAR_Msk                     /*!< DMA Enable Receiver */

+#define USART_CR3_DMAT_Pos              (7U)

+#define USART_CR3_DMAT_Msk              (0x1UL << USART_CR3_DMAT_Pos)          /*!< 0x00000080 */

+#define USART_CR3_DMAT                  USART_CR3_DMAT_Msk                     /*!< DMA Enable Transmitter */

+#define USART_CR3_RTSE_Pos              (8U)

+#define USART_CR3_RTSE_Msk              (0x1UL << USART_CR3_RTSE_Pos)          /*!< 0x00000100 */

+#define USART_CR3_RTSE                  USART_CR3_RTSE_Msk                     /*!< RTS Enable */

+#define USART_CR3_CTSE_Pos              (9U)

+#define USART_CR3_CTSE_Msk              (0x1UL << USART_CR3_CTSE_Pos)          /*!< 0x00000200 */

+#define USART_CR3_CTSE                  USART_CR3_CTSE_Msk                     /*!< CTS Enable */

+#define USART_CR3_CTSIE_Pos             (10U)

+#define USART_CR3_CTSIE_Msk             (0x1UL << USART_CR3_CTSIE_Pos)         /*!< 0x00000400 */

+#define USART_CR3_CTSIE                 USART_CR3_CTSIE_Msk                    /*!< CTS Interrupt Enable */

+#define USART_CR3_ONEBIT_Pos            (11U)

+#define USART_CR3_ONEBIT_Msk            (0x1UL << USART_CR3_ONEBIT_Pos)        /*!< 0x00000800 */

+#define USART_CR3_ONEBIT                USART_CR3_ONEBIT_Msk                   /*!< One sample bit method enable */

+#define USART_CR3_OVRDIS_Pos            (12U)

+#define USART_CR3_OVRDIS_Msk            (0x1UL << USART_CR3_OVRDIS_Pos)        /*!< 0x00001000 */

+#define USART_CR3_OVRDIS                USART_CR3_OVRDIS_Msk                   /*!< Overrun Disable */

+#define USART_CR3_DDRE_Pos              (13U)

+#define USART_CR3_DDRE_Msk              (0x1UL << USART_CR3_DDRE_Pos)          /*!< 0x00002000 */

+#define USART_CR3_DDRE                  USART_CR3_DDRE_Msk                     /*!< DMA Disable on Reception Error */

+#define USART_CR3_DEM_Pos               (14U)

+#define USART_CR3_DEM_Msk               (0x1UL << USART_CR3_DEM_Pos)           /*!< 0x00004000 */

+#define USART_CR3_DEM                   USART_CR3_DEM_Msk                      /*!< Driver Enable Mode */

+#define USART_CR3_DEP_Pos               (15U)

+#define USART_CR3_DEP_Msk               (0x1UL << USART_CR3_DEP_Pos)           /*!< 0x00008000 */

+#define USART_CR3_DEP                   USART_CR3_DEP_Msk                      /*!< Driver Enable Polarity Selection */

+#define USART_CR3_SCARCNT_Pos           (17U)

+#define USART_CR3_SCARCNT_Msk           (0x7UL << USART_CR3_SCARCNT_Pos)       /*!< 0x000E0000 */

+#define USART_CR3_SCARCNT               USART_CR3_SCARCNT_Msk                  /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */

+#define USART_CR3_SCARCNT_0             (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */

+#define USART_CR3_SCARCNT_1             (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */

+#define USART_CR3_SCARCNT_2             (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */

+#define USART_CR3_WUS_Pos               (20U)

+#define USART_CR3_WUS_Msk               (0x3UL << USART_CR3_WUS_Pos)           /*!< 0x00300000 */

+#define USART_CR3_WUS                   USART_CR3_WUS_Msk                      /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */

+#define USART_CR3_WUS_0                 (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */

+#define USART_CR3_WUS_1                 (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */

+#define USART_CR3_WUFIE_Pos             (22U)

+#define USART_CR3_WUFIE_Msk             (0x1UL << USART_CR3_WUFIE_Pos)         /*!< 0x00400000 */

+#define USART_CR3_WUFIE                 USART_CR3_WUFIE_Msk                    /*!< Wake Up Interrupt Enable */

+#define USART_CR3_TXFTIE_Pos            (23U)

+#define USART_CR3_TXFTIE_Msk            (0x1UL << USART_CR3_TXFTIE_Pos)        /*!< 0x00800000 */

+#define USART_CR3_TXFTIE                USART_CR3_TXFTIE_Msk                   /*!< TXFIFO threshold interrupt enable */

+#define USART_CR3_TCBGTIE_Pos           (24U)

+#define USART_CR3_TCBGTIE_Msk           (0x1UL << USART_CR3_TCBGTIE_Pos)       /*!< 0x01000000 */

+#define USART_CR3_TCBGTIE               USART_CR3_TCBGTIE_Msk                  /*!< Transmission Complete before guard time, interrupt enable */

+#define USART_CR3_RXFTCFG_Pos           (25U)

+#define USART_CR3_RXFTCFG_Msk           (0x7UL << USART_CR3_RXFTCFG_Pos)       /*!< 0x0E000000 */

+#define USART_CR3_RXFTCFG               USART_CR3_RXFTCFG_Msk                  /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */

+#define USART_CR3_RXFTCFG_0             (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */

+#define USART_CR3_RXFTCFG_1             (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */

+#define USART_CR3_RXFTCFG_2             (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */

+#define USART_CR3_RXFTIE_Pos            (28U)

+#define USART_CR3_RXFTIE_Msk            (0x1UL << USART_CR3_RXFTIE_Pos)        /*!< 0x10000000 */

+#define USART_CR3_RXFTIE                USART_CR3_RXFTIE_Msk                   /*!< RXFIFO threshold interrupt enable */

+#define USART_CR3_TXFTCFG_Pos           (29U)

+#define USART_CR3_TXFTCFG_Msk           (0x7UL << USART_CR3_TXFTCFG_Pos)       /*!< 0xE0000000 */

+#define USART_CR3_TXFTCFG               USART_CR3_TXFTCFG_Msk                  /*!< TXFIFO [2:0] threshold configuration */

+#define USART_CR3_TXFTCFG_0             (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */

+#define USART_CR3_TXFTCFG_1             (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */

+#define USART_CR3_TXFTCFG_2             (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */

+

+/******************  Bit definition for USART_BRR register  *******************/

+#define USART_BRR_DIV_FRACTION_Pos      (0U)

+#define USART_BRR_DIV_FRACTION_Msk      (0xFUL << USART_BRR_DIV_FRACTION_Pos)  /*!< 0x0000000F */

+#define USART_BRR_DIV_FRACTION          USART_BRR_DIV_FRACTION_Msk             /*!< Fraction of USARTDIV */

+#define USART_BRR_DIV_MANTISSA_Pos      (4U)

+#define USART_BRR_DIV_MANTISSA_Msk      (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */

+#define USART_BRR_DIV_MANTISSA          USART_BRR_DIV_MANTISSA_Msk             /*!< Mantissa of USARTDIV */

+

+/******************  Bit definition for USART_GTPR register  ******************/

+#define USART_GTPR_PSC_Pos              (0U)

+#define USART_GTPR_PSC_Msk              (0xFFUL << USART_GTPR_PSC_Pos)         /*!< 0x000000FF */

+#define USART_GTPR_PSC                  USART_GTPR_PSC_Msk                     /*!< PSC[7:0] bits (Prescaler value) */

+#define USART_GTPR_GT_Pos               (8U)

+#define USART_GTPR_GT_Msk               (0xFFUL << USART_GTPR_GT_Pos)          /*!< 0x0000FF00 */

+#define USART_GTPR_GT                   USART_GTPR_GT_Msk                      /*!< GT[7:0] bits (Guard time value) */

+

+/*******************  Bit definition for USART_RTOR register  *****************/

+#define USART_RTOR_RTO_Pos              (0U)

+#define USART_RTOR_RTO_Msk              (0xFFFFFFUL << USART_RTOR_RTO_Pos)     /*!< 0x00FFFFFF */

+#define USART_RTOR_RTO                  USART_RTOR_RTO_Msk                     /*!< Receiver Time Out Value */

+#define USART_RTOR_BLEN_Pos             (24U)

+#define USART_RTOR_BLEN_Msk             (0xFFUL << USART_RTOR_BLEN_Pos)        /*!< 0xFF000000 */

+#define USART_RTOR_BLEN                 USART_RTOR_BLEN_Msk                    /*!< Block Length */

+

+/*******************  Bit definition for USART_RQR register  ******************/

+#define USART_RQR_ABRRQ_Pos             (0U)

+#define USART_RQR_ABRRQ_Msk             (0x1UL << USART_RQR_ABRRQ_Pos)         /*!< 0x00000001 */

+#define USART_RQR_ABRRQ                 USART_RQR_ABRRQ_Msk                    /*!< Auto-Baud Rate Request */

+#define USART_RQR_SBKRQ_Pos             (1U)

+#define USART_RQR_SBKRQ_Msk             (0x1UL << USART_RQR_SBKRQ_Pos)         /*!< 0x00000002 */

+#define USART_RQR_SBKRQ                 USART_RQR_SBKRQ_Msk                    /*!< Send Break Request */

+#define USART_RQR_MMRQ_Pos              (2U)

+#define USART_RQR_MMRQ_Msk              (0x1UL << USART_RQR_MMRQ_Pos)          /*!< 0x00000004 */

+#define USART_RQR_MMRQ                  USART_RQR_MMRQ_Msk                     /*!< Mute Mode Request */

+#define USART_RQR_RXFRQ_Pos             (3U)

+#define USART_RQR_RXFRQ_Msk             (0x1UL << USART_RQR_RXFRQ_Pos)         /*!< 0x00000008 */

+#define USART_RQR_RXFRQ                 USART_RQR_RXFRQ_Msk                    /*!< Receive Data flush Request */

+#define USART_RQR_TXFRQ_Pos             (4U)

+#define USART_RQR_TXFRQ_Msk             (0x1UL << USART_RQR_TXFRQ_Pos)         /*!< 0x00000010 */

+#define USART_RQR_TXFRQ                 USART_RQR_TXFRQ_Msk                    /*!< Transmit data flush Request */

+

+/*******************  Bit definition for USART_ISR register  ******************/

+#define USART_ISR_PE_Pos                (0U)

+#define USART_ISR_PE_Msk                (0x1UL << USART_ISR_PE_Pos)            /*!< 0x00000001 */

+#define USART_ISR_PE                    USART_ISR_PE_Msk                       /*!< Parity Error */

+#define USART_ISR_FE_Pos                (1U)

+#define USART_ISR_FE_Msk                (0x1UL << USART_ISR_FE_Pos)            /*!< 0x00000002 */

+#define USART_ISR_FE                    USART_ISR_FE_Msk                       /*!< Framing Error */

+#define USART_ISR_NE_Pos                (2U)

+#define USART_ISR_NE_Msk                (0x1UL << USART_ISR_NE_Pos)            /*!< 0x00000004 */

+#define USART_ISR_NE                    USART_ISR_NE_Msk                       /*!< Noise detected Flag */

+#define USART_ISR_ORE_Pos               (3U)

+#define USART_ISR_ORE_Msk               (0x1UL << USART_ISR_ORE_Pos)           /*!< 0x00000008 */

+#define USART_ISR_ORE                   USART_ISR_ORE_Msk                      /*!< OverRun Error */

+#define USART_ISR_IDLE_Pos              (4U)

+#define USART_ISR_IDLE_Msk              (0x1UL << USART_ISR_IDLE_Pos)          /*!< 0x00000010 */

+#define USART_ISR_IDLE                  USART_ISR_IDLE_Msk                     /*!< IDLE line detected */

+#define USART_ISR_RXNE_RXFNE_Pos        (5U)

+#define USART_ISR_RXNE_RXFNE_Msk        (0x1UL << USART_ISR_RXNE_RXFNE_Pos)    /*!< 0x00000020 */

+#define USART_ISR_RXNE_RXFNE            USART_ISR_RXNE_RXFNE_Msk               /*!< Read Data Register or RX FIFO Not Empty */

+#define USART_ISR_TC_Pos                (6U)

+#define USART_ISR_TC_Msk                (0x1UL << USART_ISR_TC_Pos)            /*!< 0x00000040 */

+#define USART_ISR_TC                    USART_ISR_TC_Msk                       /*!< Transmission Complete */

+#define USART_ISR_TXE_TXFNF_Pos         (7U)

+#define USART_ISR_TXE_TXFNF_Msk         (0x1UL << USART_ISR_TXE_TXFNF_Pos)     /*!< 0x00000080 */

+#define USART_ISR_TXE_TXFNF             USART_ISR_TXE_TXFNF_Msk                /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */

+#define USART_ISR_LBDF_Pos              (8U)

+#define USART_ISR_LBDF_Msk              (0x1UL << USART_ISR_LBDF_Pos)          /*!< 0x00000100 */

+#define USART_ISR_LBDF                  USART_ISR_LBDF_Msk                     /*!< LIN Break Detection Flag */

+#define USART_ISR_CTSIF_Pos             (9U)

+#define USART_ISR_CTSIF_Msk             (0x1UL << USART_ISR_CTSIF_Pos)         /*!< 0x00000200 */

+#define USART_ISR_CTSIF                 USART_ISR_CTSIF_Msk                    /*!< CTS interrupt flag */

+#define USART_ISR_CTS_Pos               (10U)

+#define USART_ISR_CTS_Msk               (0x1UL << USART_ISR_CTS_Pos)           /*!< 0x00000400 */

+#define USART_ISR_CTS                   USART_ISR_CTS_Msk                      /*!< CTS flag */

+#define USART_ISR_RTOF_Pos              (11U)

+#define USART_ISR_RTOF_Msk              (0x1UL << USART_ISR_RTOF_Pos)          /*!< 0x00000800 */

+#define USART_ISR_RTOF                  USART_ISR_RTOF_Msk                     /*!< Receiver Time Out */

+#define USART_ISR_EOBF_Pos              (12U)

+#define USART_ISR_EOBF_Msk              (0x1UL << USART_ISR_EOBF_Pos)          /*!< 0x00001000 */

+#define USART_ISR_EOBF                  USART_ISR_EOBF_Msk                     /*!< End Of Block Flag */

+#define USART_ISR_UDR_Pos               (13U)

+#define USART_ISR_UDR_Msk               (0x1UL << USART_ISR_UDR_Pos)           /*!< 0x00002000 */

+#define USART_ISR_UDR                   USART_ISR_UDR_Msk                      /*!< SPI slave underrun error flag */

+#define USART_ISR_ABRE_Pos              (14U)

+#define USART_ISR_ABRE_Msk              (0x1UL << USART_ISR_ABRE_Pos)          /*!< 0x00004000 */

+#define USART_ISR_ABRE                  USART_ISR_ABRE_Msk                     /*!< Auto-Baud Rate Error */

+#define USART_ISR_ABRF_Pos              (15U)

+#define USART_ISR_ABRF_Msk              (0x1UL << USART_ISR_ABRF_Pos)          /*!< 0x00008000 */

+#define USART_ISR_ABRF                  USART_ISR_ABRF_Msk                     /*!< Auto-Baud Rate Flag */

+#define USART_ISR_BUSY_Pos              (16U)

+#define USART_ISR_BUSY_Msk              (0x1UL << USART_ISR_BUSY_Pos)          /*!< 0x00010000 */

+#define USART_ISR_BUSY                  USART_ISR_BUSY_Msk                     /*!< Busy Flag */

+#define USART_ISR_CMF_Pos               (17U)

+#define USART_ISR_CMF_Msk               (0x1UL << USART_ISR_CMF_Pos)           /*!< 0x00020000 */

+#define USART_ISR_CMF                   USART_ISR_CMF_Msk                      /*!< Character Match Flag */

+#define USART_ISR_SBKF_Pos              (18U)

+#define USART_ISR_SBKF_Msk              (0x1UL << USART_ISR_SBKF_Pos)          /*!< 0x00040000 */

+#define USART_ISR_SBKF                  USART_ISR_SBKF_Msk                     /*!< Send Break Flag */

+#define USART_ISR_RWU_Pos               (19U)

+#define USART_ISR_RWU_Msk               (0x1UL << USART_ISR_RWU_Pos)           /*!< 0x00080000 */

+#define USART_ISR_RWU                   USART_ISR_RWU_Msk                      /*!< Receive Wake Up from mute mode Flag */

+#define USART_ISR_WUF_Pos               (20U)

+#define USART_ISR_WUF_Msk               (0x1UL << USART_ISR_WUF_Pos)           /*!< 0x00100000 */

+#define USART_ISR_WUF                   USART_ISR_WUF_Msk                      /*!< Wake Up from stop mode Flag */

+#define USART_ISR_TEACK_Pos             (21U)

+#define USART_ISR_TEACK_Msk             (0x1UL << USART_ISR_TEACK_Pos)         /*!< 0x00200000 */

+#define USART_ISR_TEACK                 USART_ISR_TEACK_Msk                    /*!< Transmit Enable Acknowledge Flag */

+#define USART_ISR_REACK_Pos             (22U)

+#define USART_ISR_REACK_Msk             (0x1UL << USART_ISR_REACK_Pos)         /*!< 0x00400000 */

+#define USART_ISR_REACK                 USART_ISR_REACK_Msk                    /*!< Receive Enable Acknowledge Flag */

+#define USART_ISR_TXFE_Pos              (23U)

+#define USART_ISR_TXFE_Msk              (0x1UL << USART_ISR_TXFE_Pos)          /*!< 0x00800000 */

+#define USART_ISR_TXFE                  USART_ISR_TXFE_Msk                     /*!< TXFIFO Empty */

+#define USART_ISR_RXFF_Pos              (24U)

+#define USART_ISR_RXFF_Msk              (0x1UL << USART_ISR_RXFF_Pos)          /*!< 0x01000000 */

+#define USART_ISR_RXFF                  USART_ISR_RXFF_Msk                     /*!< RXFIFO Full Flag */

+#define USART_ISR_TCBGT_Pos             (25U)

+#define USART_ISR_TCBGT_Msk             (0x1UL << USART_ISR_TCBGT_Pos)         /*!< 0x02000000 */

+#define USART_ISR_TCBGT                 USART_ISR_TCBGT_Msk                    /*!< Transmission complete before guard time Flag */

+#define USART_ISR_RXFT_Pos              (26U)

+#define USART_ISR_RXFT_Msk              (0x1UL << USART_ISR_RXFT_Pos)          /*!< 0x04000000 */

+#define USART_ISR_RXFT                  USART_ISR_RXFT_Msk                     /*!< RXFIFO threshold Flag */

+#define USART_ISR_TXFT_Pos              (27U)

+#define USART_ISR_TXFT_Msk              (0x1UL << USART_ISR_TXFT_Pos)          /*!< 0x08000000 */

+#define USART_ISR_TXFT                  USART_ISR_TXFT_Msk                     /*!< TXFIFO threshold Flag */

+

+/*******************  Bit definition for USART_ICR register  ******************/

+#define USART_ICR_PECF_Pos              (0U)

+#define USART_ICR_PECF_Msk              (0x1UL << USART_ICR_PECF_Pos)          /*!< 0x00000001 */

+#define USART_ICR_PECF                  USART_ICR_PECF_Msk                     /*!< Parity Error Clear Flag */

+#define USART_ICR_FECF_Pos              (1U)

+#define USART_ICR_FECF_Msk              (0x1UL << USART_ICR_FECF_Pos)          /*!< 0x00000002 */

+#define USART_ICR_FECF                  USART_ICR_FECF_Msk                     /*!< Framing Error Clear Flag */

+#define USART_ICR_NECF_Pos              (2U)

+#define USART_ICR_NECF_Msk              (0x1UL << USART_ICR_NECF_Pos)          /*!< 0x00000004 */

+#define USART_ICR_NECF                  USART_ICR_NECF_Msk                     /*!< Noise detected Clear Flag */

+#define USART_ICR_ORECF_Pos             (3U)

+#define USART_ICR_ORECF_Msk             (0x1UL << USART_ICR_ORECF_Pos)         /*!< 0x00000008 */

+#define USART_ICR_ORECF                 USART_ICR_ORECF_Msk                    /*!< OverRun Error Clear Flag */

+#define USART_ICR_IDLECF_Pos            (4U)

+#define USART_ICR_IDLECF_Msk            (0x1UL << USART_ICR_IDLECF_Pos)        /*!< 0x00000010 */

+#define USART_ICR_IDLECF                USART_ICR_IDLECF_Msk                   /*!< IDLE line detected Clear Flag */

+#define USART_ICR_TXFECF_Pos            (5U)

+#define USART_ICR_TXFECF_Msk            (0x1UL << USART_ICR_TXFECF_Pos)        /*!< 0x00000020 */

+#define USART_ICR_TXFECF                USART_ICR_TXFECF_Msk                   /*!< TXFIFO empty clear flag */

+#define USART_ICR_TCCF_Pos              (6U)

+#define USART_ICR_TCCF_Msk              (0x1UL << USART_ICR_TCCF_Pos)          /*!< 0x00000040 */

+#define USART_ICR_TCCF                  USART_ICR_TCCF_Msk                     /*!< Transmission Complete Clear Flag */

+#define USART_ICR_TCBGTCF_Pos           (7U)

+#define USART_ICR_TCBGTCF_Msk           (0x1UL << USART_ICR_TCBGTCF_Pos)       /*!< 0x00000080 */

+#define USART_ICR_TCBGTCF               USART_ICR_TCBGTCF_Msk                  /*!< Transmission complete before guard time Clear Flag */

+#define USART_ICR_LBDCF_Pos             (8U)

+#define USART_ICR_LBDCF_Msk             (0x1UL << USART_ICR_LBDCF_Pos)         /*!< 0x00000100 */

+#define USART_ICR_LBDCF                 USART_ICR_LBDCF_Msk                    /*!< LIN Break Detection Clear Flag */

+#define USART_ICR_CTSCF_Pos             (9U)

+#define USART_ICR_CTSCF_Msk             (0x1UL << USART_ICR_CTSCF_Pos)         /*!< 0x00000200 */

+#define USART_ICR_CTSCF                 USART_ICR_CTSCF_Msk                    /*!< CTS Interrupt Clear Flag */

+#define USART_ICR_RTOCF_Pos             (11U)

+#define USART_ICR_RTOCF_Msk             (0x1UL << USART_ICR_RTOCF_Pos)         /*!< 0x00000800 */

+#define USART_ICR_RTOCF                 USART_ICR_RTOCF_Msk                    /*!< Receiver Time Out Clear Flag */

+#define USART_ICR_EOBCF_Pos             (12U)

+#define USART_ICR_EOBCF_Msk             (0x1UL << USART_ICR_EOBCF_Pos)         /*!< 0x00001000 */

+#define USART_ICR_EOBCF                 USART_ICR_EOBCF_Msk                    /*!< End Of Block Clear Flag */

+#define USART_ICR_UDRCF_Pos             (13U)

+#define USART_ICR_UDRCF_Msk             (0x1UL << USART_ICR_UDRCF_Pos)         /*!< 0x00002000 */

+#define USART_ICR_UDRCF                 USART_ICR_UDRCF_Msk                    /*!< SPI slave underrun clear flag */

+#define USART_ICR_CMCF_Pos              (17U)

+#define USART_ICR_CMCF_Msk              (0x1UL << USART_ICR_CMCF_Pos)          /*!< 0x00020000 */

+#define USART_ICR_CMCF                  USART_ICR_CMCF_Msk                     /*!< Character Match Clear Flag */

+#define USART_ICR_WUCF_Pos              (20U)

+#define USART_ICR_WUCF_Msk              (0x1UL << USART_ICR_WUCF_Pos)          /*!< 0x00100000 */

+#define USART_ICR_WUCF                  USART_ICR_WUCF_Msk                     /*!< Wake Up from stop mode Clear Flag */

+

+/*******************  Bit definition for USART_RDR register  ******************/

+#define USART_RDR_RDR_Pos               (0U)

+#define USART_RDR_RDR_Msk               (0x1FFUL << USART_RDR_RDR_Pos)         /*!< 0x000001FF */

+#define USART_RDR_RDR                   USART_RDR_RDR_Msk                      /*!< RDR[8:0] bits (Receive Data value) */

+

+/*******************  Bit definition for USART_TDR register  ******************/

+#define USART_TDR_TDR_Pos               (0U)

+#define USART_TDR_TDR_Msk               (0x1FFUL << USART_TDR_TDR_Pos)         /*!< 0x000001FF */

+#define USART_TDR_TDR                   USART_TDR_TDR_Msk                      /*!< TDR[8:0] bits (Transmit Data value) */

+

+/*******************  Bit definition for USART_PRESC register  ******************/

+#define USART_PRESC_PRESCALER_Pos       (0U)

+#define USART_PRESC_PRESCALER_Msk       (0xFUL << USART_PRESC_PRESCALER_Pos)   /*!< 0x0000000F */

+#define USART_PRESC_PRESCALER           USART_PRESC_PRESCALER_Msk              /*!< PRESCALER[3:0] bits (Clock prescaler) */

+#define USART_PRESC_PRESCALER_0         (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */

+#define USART_PRESC_PRESCALER_1         (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */

+#define USART_PRESC_PRESCALER_2         (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */

+#define USART_PRESC_PRESCALER_3         (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */

+

+/******************************************************************************/

+/*                                                                            */

+/*           Single Wire Protocol Master Interface (SWPMI)                    */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for SWPMI_CR register   ********************/

+#define SWPMI_CR_RXDMA_Pos       (0U)

+#define SWPMI_CR_RXDMA_Msk       (0x1UL << SWPMI_CR_RXDMA_Pos)                 /*!< 0x00000001 */

+#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */

+#define SWPMI_CR_TXDMA_Pos       (1U)

+#define SWPMI_CR_TXDMA_Msk       (0x1UL << SWPMI_CR_TXDMA_Pos)                 /*!< 0x00000002 */

+#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */

+#define SWPMI_CR_RXMODE_Pos      (2U)

+#define SWPMI_CR_RXMODE_Msk      (0x1UL << SWPMI_CR_RXMODE_Pos)                /*!< 0x00000004 */

+#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */

+#define SWPMI_CR_TXMODE_Pos      (3U)

+#define SWPMI_CR_TXMODE_Msk      (0x1UL << SWPMI_CR_TXMODE_Pos)                /*!< 0x00000008 */

+#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */

+#define SWPMI_CR_LPBK_Pos        (4U)

+#define SWPMI_CR_LPBK_Msk        (0x1UL << SWPMI_CR_LPBK_Pos)                  /*!< 0x00000010 */

+#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */

+#define SWPMI_CR_SWPACT_Pos      (5U)

+#define SWPMI_CR_SWPACT_Msk      (0x1UL << SWPMI_CR_SWPACT_Pos)                /*!< 0x00000020 */

+#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */

+#define SWPMI_CR_DEACT_Pos       (10U)

+#define SWPMI_CR_DEACT_Msk       (0x1UL << SWPMI_CR_DEACT_Pos)                 /*!< 0x00000400 */

+#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */

+#define SWPMI_CR_SWPEN_Pos       (11U)

+#define SWPMI_CR_SWPEN_Msk       (0x1UL << SWPMI_CR_SWPEN_Pos)                 /*!< 0x00000800 */

+#define SWPMI_CR_SWPEN           SWPMI_CR_SWPEN_Msk                            /*!<Single wire protocol master transceiver enable       */

+

+/*******************  Bit definition for SWPMI_BRR register  ********************/

+#define SWPMI_BRR_BR_Pos         (0U)

+#define SWPMI_BRR_BR_Msk         (0xFFUL << SWPMI_BRR_BR_Pos)                  /*!< 0x000000FF */

+#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[7:0] bits (Bitrate prescaler) */

+

+/*******************  Bit definition for SWPMI_ISR register  ********************/

+#define SWPMI_ISR_RXBFF_Pos      (0U)

+#define SWPMI_ISR_RXBFF_Msk      (0x1UL << SWPMI_ISR_RXBFF_Pos)                /*!< 0x00000001 */

+#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */

+#define SWPMI_ISR_TXBEF_Pos      (1U)

+#define SWPMI_ISR_TXBEF_Msk      (0x1UL << SWPMI_ISR_TXBEF_Pos)                /*!< 0x00000002 */

+#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */

+#define SWPMI_ISR_RXBERF_Pos     (2U)

+#define SWPMI_ISR_RXBERF_Msk     (0x1UL << SWPMI_ISR_RXBERF_Pos)               /*!< 0x00000004 */

+#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */

+#define SWPMI_ISR_RXOVRF_Pos     (3U)

+#define SWPMI_ISR_RXOVRF_Msk     (0x1UL << SWPMI_ISR_RXOVRF_Pos)               /*!< 0x00000008 */

+#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */

+#define SWPMI_ISR_TXUNRF_Pos     (4U)

+#define SWPMI_ISR_TXUNRF_Msk     (0x1UL << SWPMI_ISR_TXUNRF_Pos)               /*!< 0x00000010 */

+#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */

+#define SWPMI_ISR_RXNE_Pos       (5U)

+#define SWPMI_ISR_RXNE_Msk       (0x1UL << SWPMI_ISR_RXNE_Pos)                 /*!< 0x00000020 */

+#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */

+#define SWPMI_ISR_TXE_Pos        (6U)

+#define SWPMI_ISR_TXE_Msk        (0x1UL << SWPMI_ISR_TXE_Pos)                  /*!< 0x00000040 */

+#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */

+#define SWPMI_ISR_TCF_Pos        (7U)

+#define SWPMI_ISR_TCF_Msk        (0x1UL << SWPMI_ISR_TCF_Pos)                  /*!< 0x00000080 */

+#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */

+#define SWPMI_ISR_SRF_Pos        (8U)

+#define SWPMI_ISR_SRF_Msk        (0x1UL << SWPMI_ISR_SRF_Pos)                  /*!< 0x00000100 */

+#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */

+#define SWPMI_ISR_SUSP_Pos       (9U)

+#define SWPMI_ISR_SUSP_Msk       (0x1UL << SWPMI_ISR_SUSP_Pos)                 /*!< 0x00000200 */

+#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */

+#define SWPMI_ISR_DEACTF_Pos     (10U)

+#define SWPMI_ISR_DEACTF_Msk     (0x1UL << SWPMI_ISR_DEACTF_Pos)               /*!< 0x00000400 */

+#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */

+#define SWPMI_ISR_RDYF_Pos       (11U)

+#define SWPMI_ISR_RDYF_Msk       (0x1UL << SWPMI_ISR_RDYF_Pos)                 /*!< 0x00000800 */

+#define SWPMI_ISR_RDYF           SWPMI_ISR_RDYF_Msk                            /*!<Transceiver ready flag          */

+

+/*******************  Bit definition for SWPMI_ICR register  ********************/

+#define SWPMI_ICR_CRXBFF_Pos     (0U)

+#define SWPMI_ICR_CRXBFF_Msk     (0x1UL << SWPMI_ICR_CRXBFF_Pos)               /*!< 0x00000001 */

+#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */

+#define SWPMI_ICR_CTXBEF_Pos     (1U)

+#define SWPMI_ICR_CTXBEF_Msk     (0x1UL << SWPMI_ICR_CTXBEF_Pos)               /*!< 0x00000002 */

+#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */

+#define SWPMI_ICR_CRXBERF_Pos    (2U)

+#define SWPMI_ICR_CRXBERF_Msk    (0x1UL << SWPMI_ICR_CRXBERF_Pos)              /*!< 0x00000004 */

+#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */

+#define SWPMI_ICR_CRXOVRF_Pos    (3U)

+#define SWPMI_ICR_CRXOVRF_Msk    (0x1UL << SWPMI_ICR_CRXOVRF_Pos)              /*!< 0x00000008 */

+#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */

+#define SWPMI_ICR_CTXUNRF_Pos    (4U)

+#define SWPMI_ICR_CTXUNRF_Msk    (0x1UL << SWPMI_ICR_CTXUNRF_Pos)              /*!< 0x00000010 */

+#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */

+#define SWPMI_ICR_CTCF_Pos       (7U)

+#define SWPMI_ICR_CTCF_Msk       (0x1UL << SWPMI_ICR_CTCF_Pos)                 /*!< 0x00000080 */

+#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */

+#define SWPMI_ICR_CSRF_Pos       (8U)

+#define SWPMI_ICR_CSRF_Msk       (0x1UL << SWPMI_ICR_CSRF_Pos)                 /*!< 0x00000100 */

+#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */

+#define SWPMI_ICR_CRDYF_Pos      (11U)

+#define SWPMI_ICR_CRDYF_Msk      (0x1UL << SWPMI_ICR_CRDYF_Pos)                /*!< 0x00000800 */

+#define SWPMI_ICR_CRDYF          SWPMI_ICR_CRDYF_Msk                           /*!<Clear transceiver ready flag         */

+

+/*******************  Bit definition for SWPMI_IER register  ********************/

+#define SWPMI_IER_RXBFIE_Pos     (0U)

+#define SWPMI_IER_RXBFIE_Msk     (0x1UL << SWPMI_IER_RXBFIE_Pos)               /*!< 0x00000001 */

+#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */

+#define SWPMI_IER_TXBEIE_Pos     (1U)

+#define SWPMI_IER_TXBEIE_Msk     (0x1UL << SWPMI_IER_TXBEIE_Pos)               /*!< 0x00000002 */

+#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */

+#define SWPMI_IER_RXBERIE_Pos    (2U)

+#define SWPMI_IER_RXBERIE_Msk    (0x1UL << SWPMI_IER_RXBERIE_Pos)              /*!< 0x00000004 */

+#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */

+#define SWPMI_IER_RXOVRIE_Pos    (3U)

+#define SWPMI_IER_RXOVRIE_Msk    (0x1UL << SWPMI_IER_RXOVRIE_Pos)              /*!< 0x00000008 */

+#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */

+#define SWPMI_IER_TXUNRIE_Pos    (4U)

+#define SWPMI_IER_TXUNRIE_Msk    (0x1UL << SWPMI_IER_TXUNRIE_Pos)              /*!< 0x00000010 */

+#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */

+#define SWPMI_IER_RIE_Pos        (5U)

+#define SWPMI_IER_RIE_Msk        (0x1UL << SWPMI_IER_RIE_Pos)                  /*!< 0x00000020 */

+#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */

+#define SWPMI_IER_TIE_Pos        (6U)

+#define SWPMI_IER_TIE_Msk        (0x1UL << SWPMI_IER_TIE_Pos)                  /*!< 0x00000040 */

+#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */

+#define SWPMI_IER_TCIE_Pos       (7U)

+#define SWPMI_IER_TCIE_Msk       (0x1UL << SWPMI_IER_TCIE_Pos)                 /*!< 0x00000080 */

+#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */

+#define SWPMI_IER_SRIE_Pos       (8U)

+#define SWPMI_IER_SRIE_Msk       (0x1UL << SWPMI_IER_SRIE_Pos)                 /*!< 0x00000100 */

+#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */

+#define SWPMI_IER_RDYIE_Pos      (11U)

+#define SWPMI_IER_RDYIE_Msk      (0x1UL << SWPMI_IER_RDYIE_Pos)                /*!< 0x00000800 */

+#define SWPMI_IER_RDYIE          SWPMI_IER_RDYIE_Msk                           /*!<Transceiver ready interrupt enable          */

+

+/*******************  Bit definition for SWPMI_RFL register  ********************/

+#define SWPMI_RFL_RFL_Pos        (0U)

+#define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */

+#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */

+#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */

+

+/*******************  Bit definition for SWPMI_TDR register  ********************/

+#define SWPMI_TDR_TD_Pos         (0U)

+#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)            /*!< 0xFFFFFFFF */

+#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */

+

+/*******************  Bit definition for SWPMI_RDR register  ********************/

+#define SWPMI_RDR_RD_Pos         (0U)

+#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)            /*!< 0xFFFFFFFF */

+#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Recive Data Register           */

+

+

+/*******************  Bit definition for SWPMI_OR register  ********************/

+#define SWPMI_OR_TBYP_Pos        (0U)

+#define SWPMI_OR_TBYP_Msk        (0x1UL << SWPMI_OR_TBYP_Pos)                  /*!< 0x00000001 */

+#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */

+#define SWPMI_OR_CLASS_Pos       (1U)

+#define SWPMI_OR_CLASS_Msk       (0x1UL << SWPMI_OR_CLASS_Pos)                 /*!< 0x00000002 */

+#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP CLASS selection */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            Window WATCHDOG                                 */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for WWDG_CR register  ********************/

+#define WWDG_CR_T_Pos           (0U)

+#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */

+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */

+#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */

+#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */

+#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */

+#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */

+#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */

+#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */

+#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */

+

+#define WWDG_CR_WDGA_Pos        (7U)

+#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */

+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */

+

+/*******************  Bit definition for WWDG_CFR register  *******************/

+#define WWDG_CFR_W_Pos          (0U)

+#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */

+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */

+#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */

+#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */

+#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */

+#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */

+#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */

+#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */

+#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */

+

+#define WWDG_CFR_EWI_Pos        (9U)

+#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */

+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */

+

+#define WWDG_CFR_WDGTB_Pos      (11U)

+#define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */

+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */

+#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000800 */

+#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00001000 */

+#define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00002000 */

+

+/*******************  Bit definition for WWDG_SR register  ********************/

+#define WWDG_SR_EWIF_Pos        (0U)

+#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */

+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                DBG                                         */

+/*                                                                            */

+/******************************************************************************/

+/*********************************  DEVICE ID  ********************************/

+#define STM32H7_DEV_ID           0x450UL

+

+/********************  Bit definition for DBGMCU_IDCODE register  *************/

+#define DBGMCU_IDCODE_DEV_ID_Pos          (0U)

+#define DBGMCU_IDCODE_DEV_ID_Msk          (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */

+#define DBGMCU_IDCODE_DEV_ID              DBGMCU_IDCODE_DEV_ID_Msk

+#define DBGMCU_IDCODE_REV_ID_Pos          (16U)

+#define DBGMCU_IDCODE_REV_ID_Msk          (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */

+#define DBGMCU_IDCODE_REV_ID              DBGMCU_IDCODE_REV_ID_Msk

+

+/********************  Bit definition for DBGMCU_CR register  *****************/

+#define DBGMCU_CR_DBG_SLEEPD1_Pos         (0U)

+#define DBGMCU_CR_DBG_SLEEPD1_Msk         (0x1UL << DBGMCU_CR_DBG_SLEEPD1_Pos) /*!< 0x00000001 */

+#define DBGMCU_CR_DBG_SLEEPD1             DBGMCU_CR_DBG_SLEEPD1_Msk

+#define DBGMCU_CR_DBG_STOPD1_Pos          (1U)

+#define DBGMCU_CR_DBG_STOPD1_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD1_Pos)  /*!< 0x00000002 */

+#define DBGMCU_CR_DBG_STOPD1              DBGMCU_CR_DBG_STOPD1_Msk

+#define DBGMCU_CR_DBG_STANDBYD1_Pos       (2U)

+#define DBGMCU_CR_DBG_STANDBYD1_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos) /*!< 0x00000004 */

+#define DBGMCU_CR_DBG_STANDBYD1           DBGMCU_CR_DBG_STANDBYD1_Msk

+#define DBGMCU_CR_DBG_STOPD3_Pos          (7U)

+#define DBGMCU_CR_DBG_STOPD3_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos)  /*!< 0x00000080 */

+#define DBGMCU_CR_DBG_STOPD3              DBGMCU_CR_DBG_STOPD3_Msk

+#define DBGMCU_CR_DBG_STANDBYD3_Pos       (8U)

+#define DBGMCU_CR_DBG_STANDBYD3_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos) /*!< 0x00000100 */

+#define DBGMCU_CR_DBG_STANDBYD3           DBGMCU_CR_DBG_STANDBYD3_Msk

+#define DBGMCU_CR_DBG_TRACECKEN_Pos       (20U)

+#define DBGMCU_CR_DBG_TRACECKEN_Msk       (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */

+#define DBGMCU_CR_DBG_TRACECKEN           DBGMCU_CR_DBG_TRACECKEN_Msk

+#define DBGMCU_CR_DBG_CKD1EN_Pos          (21U)

+#define DBGMCU_CR_DBG_CKD1EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD1EN_Pos)  /*!< 0x00200000 */

+#define DBGMCU_CR_DBG_CKD1EN              DBGMCU_CR_DBG_CKD1EN_Msk

+#define DBGMCU_CR_DBG_CKD3EN_Pos          (22U)

+#define DBGMCU_CR_DBG_CKD3EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD3EN_Pos)  /*!< 0x00400000 */

+#define DBGMCU_CR_DBG_CKD3EN              DBGMCU_CR_DBG_CKD3EN_Msk

+#define DBGMCU_CR_DBG_TRGOEN_Pos          (28U)

+#define DBGMCU_CR_DBG_TRGOEN_Msk          (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)  /*!< 0x10000000 */

+#define DBGMCU_CR_DBG_TRGOEN              DBGMCU_CR_DBG_TRGOEN_Msk

+

+/********************  Bit definition for APB3FZ1 register  ************/

+#define DBGMCU_APB3FZ1_DBG_WWDG1_Pos      (6U)

+#define DBGMCU_APB3FZ1_DBG_WWDG1_Msk      (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB3FZ1_DBG_WWDG1          DBGMCU_APB3FZ1_DBG_WWDG1_Msk

+/********************  Bit definition for APB1LFZ1 register  ************/

+#define DBGMCU_APB1LFZ1_DBG_TIM2_Pos      (0U)

+#define DBGMCU_APB1LFZ1_DBG_TIM2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB1LFZ1_DBG_TIM2          DBGMCU_APB1LFZ1_DBG_TIM2_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM3_Pos      (1U)

+#define DBGMCU_APB1LFZ1_DBG_TIM3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB1LFZ1_DBG_TIM3          DBGMCU_APB1LFZ1_DBG_TIM3_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM4_Pos      (2U)

+#define DBGMCU_APB1LFZ1_DBG_TIM4_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */

+#define DBGMCU_APB1LFZ1_DBG_TIM4          DBGMCU_APB1LFZ1_DBG_TIM4_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM5_Pos      (3U)

+#define DBGMCU_APB1LFZ1_DBG_TIM5_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */

+#define DBGMCU_APB1LFZ1_DBG_TIM5          DBGMCU_APB1LFZ1_DBG_TIM5_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM6_Pos      (4U)

+#define DBGMCU_APB1LFZ1_DBG_TIM6_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */

+#define DBGMCU_APB1LFZ1_DBG_TIM6          DBGMCU_APB1LFZ1_DBG_TIM6_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM7_Pos      (5U)

+#define DBGMCU_APB1LFZ1_DBG_TIM7_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */

+#define DBGMCU_APB1LFZ1_DBG_TIM7          DBGMCU_APB1LFZ1_DBG_TIM7_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM12_Pos     (6U)

+#define DBGMCU_APB1LFZ1_DBG_TIM12_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB1LFZ1_DBG_TIM12         DBGMCU_APB1LFZ1_DBG_TIM12_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM13_Pos     (7U)

+#define DBGMCU_APB1LFZ1_DBG_TIM13_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB1LFZ1_DBG_TIM13         DBGMCU_APB1LFZ1_DBG_TIM13_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM14_Pos     (8U)

+#define DBGMCU_APB1LFZ1_DBG_TIM14_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */

+#define DBGMCU_APB1LFZ1_DBG_TIM14         DBGMCU_APB1LFZ1_DBG_TIM14_Msk

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos    (9U)

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1        DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C1_Pos      (21U)

+#define DBGMCU_APB1LFZ1_DBG_I2C1_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C1          DBGMCU_APB1LFZ1_DBG_I2C1_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C2_Pos      (22U)

+#define DBGMCU_APB1LFZ1_DBG_I2C2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C2          DBGMCU_APB1LFZ1_DBG_I2C2_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C3_Pos      (23U)

+#define DBGMCU_APB1LFZ1_DBG_I2C3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C3          DBGMCU_APB1LFZ1_DBG_I2C3_Msk

+

+/********************  Bit definition for APB1HFZ1 register  ************/

+#define DBGMCU_APB1HFZ1_DBG_FDCAN_Pos     (8U)

+#define DBGMCU_APB1HFZ1_DBG_FDCAN_Msk     (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_Pos) /*!< 0x00000100 */

+#define DBGMCU_APB1HFZ1_DBG_FDCAN         DBGMCU_APB1HFZ1_DBG_FDCAN_Msk

+/********************  Bit definition for APB2FZ1 register  ************/

+#define DBGMCU_APB2FZ1_DBG_TIM1_Pos       (0U)

+#define DBGMCU_APB2FZ1_DBG_TIM1_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB2FZ1_DBG_TIM1           DBGMCU_APB2FZ1_DBG_TIM1_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM8_Pos       (1U)

+#define DBGMCU_APB2FZ1_DBG_TIM8_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB2FZ1_DBG_TIM8           DBGMCU_APB2FZ1_DBG_TIM8_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM15_Pos      (16U)

+#define DBGMCU_APB2FZ1_DBG_TIM15_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB2FZ1_DBG_TIM15          DBGMCU_APB2FZ1_DBG_TIM15_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM16_Pos      (17U)

+#define DBGMCU_APB2FZ1_DBG_TIM16_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */

+#define DBGMCU_APB2FZ1_DBG_TIM16          DBGMCU_APB2FZ1_DBG_TIM16_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM17_Pos      (18U)

+#define DBGMCU_APB2FZ1_DBG_TIM17_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB2FZ1_DBG_TIM17          DBGMCU_APB2FZ1_DBG_TIM17_Msk

+#define DBGMCU_APB2FZ1_DBG_HRTIM_Pos      (29U)

+#define DBGMCU_APB2FZ1_DBG_HRTIM_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_HRTIM_Pos) /*!< 0x20000000 */

+#define DBGMCU_APB2FZ1_DBG_HRTIM          DBGMCU_APB2FZ1_DBG_HRTIM_Msk

+

+/********************  Bit definition for APB4FZ1 register  ************/

+#define DBGMCU_APB4FZ1_DBG_I2C4_Pos       (7U)

+#define DBGMCU_APB4FZ1_DBG_I2C4_Msk       (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB4FZ1_DBG_I2C4           DBGMCU_APB4FZ1_DBG_I2C4_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos     (9U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM2         DBGMCU_APB4FZ1_DBG_LPTIM2_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos     (10U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM3         DBGMCU_APB4FZ1_DBG_LPTIM3_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM4_Pos     (11U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM4_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos) /*!< 0x00000800 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM4         DBGMCU_APB4FZ1_DBG_LPTIM4_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM5_Pos     (12U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM5_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos) /*!< 0x00001000 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM5         DBGMCU_APB4FZ1_DBG_LPTIM5_Msk

+#define DBGMCU_APB4FZ1_DBG_RTC_Pos        (16U)

+#define DBGMCU_APB4FZ1_DBG_RTC_Msk        (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB4FZ1_DBG_RTC            DBGMCU_APB4FZ1_DBG_RTC_Msk

+#define DBGMCU_APB4FZ1_DBG_IWDG1_Pos      (18U)

+#define DBGMCU_APB4FZ1_DBG_IWDG1_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB4FZ1_DBG_IWDG1          DBGMCU_APB4FZ1_DBG_IWDG1_Msk

+/******************************************************************************/

+/*                                                                            */

+/*                        High Resolution Timer (HRTIM)                       */

+/*                                                                            */

+/******************************************************************************/

+/******************** Master Timer control register ***************************/

+#define HRTIM_MCR_CK_PSC_Pos          (0U)

+#define HRTIM_MCR_CK_PSC_Msk          (0x7UL << HRTIM_MCR_CK_PSC_Pos)          /*!< 0x00000007 */

+#define HRTIM_MCR_CK_PSC              HRTIM_MCR_CK_PSC_Msk                     /*!< Prescaler mask */

+#define HRTIM_MCR_CK_PSC_0            (0x1UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000001 */

+#define HRTIM_MCR_CK_PSC_1            (0x2UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000002 */

+#define HRTIM_MCR_CK_PSC_2            (0x4UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000004 */

+

+#define HRTIM_MCR_CONT_Pos            (3U)

+#define HRTIM_MCR_CONT_Msk            (0x1UL << HRTIM_MCR_CONT_Pos)            /*!< 0x00000008 */

+#define HRTIM_MCR_CONT                HRTIM_MCR_CONT_Msk                       /*!< Continuous mode */

+#define HRTIM_MCR_RETRIG_Pos          (4U)

+#define HRTIM_MCR_RETRIG_Msk          (0x1UL << HRTIM_MCR_RETRIG_Pos)          /*!< 0x00000010 */

+#define HRTIM_MCR_RETRIG              HRTIM_MCR_RETRIG_Msk                     /*!< Rettrigreable mode */

+#define HRTIM_MCR_HALF_Pos            (5U)

+#define HRTIM_MCR_HALF_Msk            (0x1UL << HRTIM_MCR_HALF_Pos)            /*!< 0x00000020 */

+#define HRTIM_MCR_HALF                HRTIM_MCR_HALF_Msk                       /*!< Half mode */

+

+#define HRTIM_MCR_SYNC_IN_Pos         (8U)

+#define HRTIM_MCR_SYNC_IN_Msk         (0x3UL << HRTIM_MCR_SYNC_IN_Pos)         /*!< 0x00000300 */

+#define HRTIM_MCR_SYNC_IN             HRTIM_MCR_SYNC_IN_Msk                    /*!< Synchronization input master */

+#define HRTIM_MCR_SYNC_IN_0           (0x1UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000100 */

+#define HRTIM_MCR_SYNC_IN_1           (0x2UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000200 */

+#define HRTIM_MCR_SYNCRSTM_Pos        (10U)

+#define HRTIM_MCR_SYNCRSTM_Msk        (0x1UL << HRTIM_MCR_SYNCRSTM_Pos)        /*!< 0x00000400 */

+#define HRTIM_MCR_SYNCRSTM            HRTIM_MCR_SYNCRSTM_Msk                   /*!< Synchronization reset master */

+#define HRTIM_MCR_SYNCSTRTM_Pos       (11U)

+#define HRTIM_MCR_SYNCSTRTM_Msk       (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos)       /*!< 0x00000800 */

+#define HRTIM_MCR_SYNCSTRTM           HRTIM_MCR_SYNCSTRTM_Msk                  /*!< Synchronization start master */

+#define HRTIM_MCR_SYNC_OUT_Pos        (12U)

+#define HRTIM_MCR_SYNC_OUT_Msk        (0x3UL << HRTIM_MCR_SYNC_OUT_Pos)        /*!< 0x00003000 */

+#define HRTIM_MCR_SYNC_OUT            HRTIM_MCR_SYNC_OUT_Msk                   /*!< Synchronization output master */

+#define HRTIM_MCR_SYNC_OUT_0          (0x1UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00001000 */

+#define HRTIM_MCR_SYNC_OUT_1          (0x2UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00002000 */

+#define HRTIM_MCR_SYNC_SRC_Pos        (14U)

+#define HRTIM_MCR_SYNC_SRC_Msk        (0x3UL << HRTIM_MCR_SYNC_SRC_Pos)        /*!< 0x0000C000 */

+#define HRTIM_MCR_SYNC_SRC            HRTIM_MCR_SYNC_SRC_Msk                   /*!< Synchronization source */

+#define HRTIM_MCR_SYNC_SRC_0          (0x1UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00004000 */

+#define HRTIM_MCR_SYNC_SRC_1          (0x2UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00008000 */

+

+#define HRTIM_MCR_MCEN_Pos            (16U)

+#define HRTIM_MCR_MCEN_Msk            (0x1UL << HRTIM_MCR_MCEN_Pos)            /*!< 0x00010000 */

+#define HRTIM_MCR_MCEN                HRTIM_MCR_MCEN_Msk                       /*!< Master counter enable */

+#define HRTIM_MCR_TACEN_Pos           (17U)

+#define HRTIM_MCR_TACEN_Msk           (0x1UL << HRTIM_MCR_TACEN_Pos)           /*!< 0x00020000 */

+#define HRTIM_MCR_TACEN               HRTIM_MCR_TACEN_Msk                      /*!< Timer A counter enable */

+#define HRTIM_MCR_TBCEN_Pos           (18U)

+#define HRTIM_MCR_TBCEN_Msk           (0x1UL << HRTIM_MCR_TBCEN_Pos)           /*!< 0x00040000 */

+#define HRTIM_MCR_TBCEN               HRTIM_MCR_TBCEN_Msk                      /*!< Timer B counter enable */

+#define HRTIM_MCR_TCCEN_Pos           (19U)

+#define HRTIM_MCR_TCCEN_Msk           (0x1UL << HRTIM_MCR_TCCEN_Pos)           /*!< 0x00080000 */

+#define HRTIM_MCR_TCCEN               HRTIM_MCR_TCCEN_Msk                      /*!< Timer C counter enable */

+#define HRTIM_MCR_TDCEN_Pos           (20U)

+#define HRTIM_MCR_TDCEN_Msk           (0x1UL << HRTIM_MCR_TDCEN_Pos)           /*!< 0x00100000 */

+#define HRTIM_MCR_TDCEN               HRTIM_MCR_TDCEN_Msk                      /*!< Timer D counter enable */

+#define HRTIM_MCR_TECEN_Pos           (21U)

+#define HRTIM_MCR_TECEN_Msk           (0x1UL << HRTIM_MCR_TECEN_Pos)           /*!< 0x00200000 */

+#define HRTIM_MCR_TECEN               HRTIM_MCR_TECEN_Msk                      /*!< Timer E counter enable */

+

+#define HRTIM_MCR_DACSYNC_Pos         (25U)

+#define HRTIM_MCR_DACSYNC_Msk         (0x3UL << HRTIM_MCR_DACSYNC_Pos)         /*!< 0x06000000 */

+#define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC sychronization mask */

+#define HRTIM_MCR_DACSYNC_0           (0x1UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x02000000 */

+#define HRTIM_MCR_DACSYNC_1           (0x2UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x04000000 */

+

+#define HRTIM_MCR_PREEN_Pos           (27U)

+#define HRTIM_MCR_PREEN_Msk           (0x1UL << HRTIM_MCR_PREEN_Pos)           /*!< 0x08000000 */

+#define HRTIM_MCR_PREEN               HRTIM_MCR_PREEN_Msk                      /*!< Master preload enable */

+#define HRTIM_MCR_MREPU_Pos           (29U)

+#define HRTIM_MCR_MREPU_Msk           (0x1UL << HRTIM_MCR_MREPU_Pos)           /*!< 0x20000000 */

+#define HRTIM_MCR_MREPU               HRTIM_MCR_MREPU_Msk                      /*!< Master repetition update */

+

+#define HRTIM_MCR_BRSTDMA_Pos         (30U)

+#define HRTIM_MCR_BRSTDMA_Msk         (0x3UL << HRTIM_MCR_BRSTDMA_Pos)         /*!< 0xC0000000 */

+#define HRTIM_MCR_BRSTDMA             HRTIM_MCR_BRSTDMA_Msk                    /*!< Burst DMA update */

+#define HRTIM_MCR_BRSTDMA_0           (0x1UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x40000000 */

+#define HRTIM_MCR_BRSTDMA_1           (0x2UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x80000000 */

+

+/******************** Master Timer Interrupt status register ******************/

+#define HRTIM_MISR_MCMP1_Pos          (0U)

+#define HRTIM_MISR_MCMP1_Msk          (0x1UL << HRTIM_MISR_MCMP1_Pos)          /*!< 0x00000001 */

+#define HRTIM_MISR_MCMP1              HRTIM_MISR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag */

+#define HRTIM_MISR_MCMP2_Pos          (1U)

+#define HRTIM_MISR_MCMP2_Msk          (0x1UL << HRTIM_MISR_MCMP2_Pos)          /*!< 0x00000002 */

+#define HRTIM_MISR_MCMP2              HRTIM_MISR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag */

+#define HRTIM_MISR_MCMP3_Pos          (2U)

+#define HRTIM_MISR_MCMP3_Msk          (0x1UL << HRTIM_MISR_MCMP3_Pos)          /*!< 0x00000004 */

+#define HRTIM_MISR_MCMP3              HRTIM_MISR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag */

+#define HRTIM_MISR_MCMP4_Pos          (3U)

+#define HRTIM_MISR_MCMP4_Msk          (0x1UL << HRTIM_MISR_MCMP4_Pos)          /*!< 0x00000008 */

+#define HRTIM_MISR_MCMP4              HRTIM_MISR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag */

+#define HRTIM_MISR_MREP_Pos           (4U)

+#define HRTIM_MISR_MREP_Msk           (0x1UL << HRTIM_MISR_MREP_Pos)           /*!< 0x00000010 */

+#define HRTIM_MISR_MREP               HRTIM_MISR_MREP_Msk                      /*!< Master Repetition interrupt flag */

+#define HRTIM_MISR_SYNC_Pos           (5U)

+#define HRTIM_MISR_SYNC_Msk           (0x1UL << HRTIM_MISR_SYNC_Pos)           /*!< 0x00000020 */

+#define HRTIM_MISR_SYNC               HRTIM_MISR_SYNC_Msk                      /*!< Synchronization input interrupt flag */

+#define HRTIM_MISR_MUPD_Pos           (6U)

+#define HRTIM_MISR_MUPD_Msk           (0x1UL << HRTIM_MISR_MUPD_Pos)           /*!< 0x00000040 */

+#define HRTIM_MISR_MUPD               HRTIM_MISR_MUPD_Msk                      /*!< Master update interrupt flag */

+

+/******************** Master Timer Interrupt clear register *******************/

+#define HRTIM_MICR_MCMP1_Pos          (0U)

+#define HRTIM_MICR_MCMP1_Msk          (0x1UL << HRTIM_MICR_MCMP1_Pos)          /*!< 0x00000001 */

+#define HRTIM_MICR_MCMP1              HRTIM_MICR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag clear */

+#define HRTIM_MICR_MCMP2_Pos          (1U)

+#define HRTIM_MICR_MCMP2_Msk          (0x1UL << HRTIM_MICR_MCMP2_Pos)          /*!< 0x00000002 */

+#define HRTIM_MICR_MCMP2              HRTIM_MICR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag clear */

+#define HRTIM_MICR_MCMP3_Pos          (2U)

+#define HRTIM_MICR_MCMP3_Msk          (0x1UL << HRTIM_MICR_MCMP3_Pos)          /*!< 0x00000004 */

+#define HRTIM_MICR_MCMP3              HRTIM_MICR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag clear */

+#define HRTIM_MICR_MCMP4_Pos          (3U)

+#define HRTIM_MICR_MCMP4_Msk          (0x1UL << HRTIM_MICR_MCMP4_Pos)          /*!< 0x00000008 */

+#define HRTIM_MICR_MCMP4              HRTIM_MICR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag clear */

+#define HRTIM_MICR_MREP_Pos           (4U)

+#define HRTIM_MICR_MREP_Msk           (0x1UL << HRTIM_MICR_MREP_Pos)           /*!< 0x00000010 */

+#define HRTIM_MICR_MREP               HRTIM_MICR_MREP_Msk                      /*!< Master Repetition interrupt flag clear */

+#define HRTIM_MICR_SYNC_Pos           (5U)

+#define HRTIM_MICR_SYNC_Msk           (0x1UL << HRTIM_MICR_SYNC_Pos)           /*!< 0x00000020 */

+#define HRTIM_MICR_SYNC               HRTIM_MICR_SYNC_Msk                      /*!< Synchronization input interrupt flag clear */

+#define HRTIM_MICR_MUPD_Pos           (6U)

+#define HRTIM_MICR_MUPD_Msk           (0x1UL << HRTIM_MICR_MUPD_Pos)           /*!< 0x00000040 */

+#define HRTIM_MICR_MUPD               HRTIM_MICR_MUPD_Msk                      /*!< Master update interrupt flag clear */

+

+/******************** Master Timer DMA/Interrupt enable register **************/

+#define HRTIM_MDIER_MCMP1IE_Pos       (0U)

+#define HRTIM_MDIER_MCMP1IE_Msk       (0x1UL << HRTIM_MDIER_MCMP1IE_Pos)       /*!< 0x00000001 */

+#define HRTIM_MDIER_MCMP1IE           HRTIM_MDIER_MCMP1IE_Msk                  /*!< Master compare 1 interrupt enable */

+#define HRTIM_MDIER_MCMP2IE_Pos       (1U)

+#define HRTIM_MDIER_MCMP2IE_Msk       (0x1UL << HRTIM_MDIER_MCMP2IE_Pos)       /*!< 0x00000002 */

+#define HRTIM_MDIER_MCMP2IE           HRTIM_MDIER_MCMP2IE_Msk                  /*!< Master compare 2 interrupt enable */

+#define HRTIM_MDIER_MCMP3IE_Pos       (2U)

+#define HRTIM_MDIER_MCMP3IE_Msk       (0x1UL << HRTIM_MDIER_MCMP3IE_Pos)       /*!< 0x00000004 */

+#define HRTIM_MDIER_MCMP3IE           HRTIM_MDIER_MCMP3IE_Msk                  /*!< Master compare 3 interrupt enable */

+#define HRTIM_MDIER_MCMP4IE_Pos       (3U)

+#define HRTIM_MDIER_MCMP4IE_Msk       (0x1UL << HRTIM_MDIER_MCMP4IE_Pos)       /*!< 0x00000008 */

+#define HRTIM_MDIER_MCMP4IE           HRTIM_MDIER_MCMP4IE_Msk                  /*!< Master compare 4 interrupt enable */

+#define HRTIM_MDIER_MREPIE_Pos        (4U)

+#define HRTIM_MDIER_MREPIE_Msk        (0x1UL << HRTIM_MDIER_MREPIE_Pos)        /*!< 0x00000010 */

+#define HRTIM_MDIER_MREPIE            HRTIM_MDIER_MREPIE_Msk                   /*!< Master Repetition interrupt enable */

+#define HRTIM_MDIER_SYNCIE_Pos        (5U)

+#define HRTIM_MDIER_SYNCIE_Msk        (0x1UL << HRTIM_MDIER_SYNCIE_Pos)        /*!< 0x00000020 */

+#define HRTIM_MDIER_SYNCIE            HRTIM_MDIER_SYNCIE_Msk                   /*!< Synchronization input interrupt enable */

+#define HRTIM_MDIER_MUPDIE_Pos        (6U)

+#define HRTIM_MDIER_MUPDIE_Msk        (0x1UL << HRTIM_MDIER_MUPDIE_Pos)        /*!< 0x00000040 */

+#define HRTIM_MDIER_MUPDIE            HRTIM_MDIER_MUPDIE_Msk                   /*!< Master update interrupt enable */

+

+#define HRTIM_MDIER_MCMP1DE_Pos       (16U)

+#define HRTIM_MDIER_MCMP1DE_Msk       (0x1UL << HRTIM_MDIER_MCMP1DE_Pos)       /*!< 0x00010000 */

+#define HRTIM_MDIER_MCMP1DE           HRTIM_MDIER_MCMP1DE_Msk                  /*!< Master compare 1 DMA enable */

+#define HRTIM_MDIER_MCMP2DE_Pos       (17U)

+#define HRTIM_MDIER_MCMP2DE_Msk       (0x1UL << HRTIM_MDIER_MCMP2DE_Pos)       /*!< 0x00020000 */

+#define HRTIM_MDIER_MCMP2DE           HRTIM_MDIER_MCMP2DE_Msk                  /*!< Master compare 2 DMA enable */

+#define HRTIM_MDIER_MCMP3DE_Pos       (18U)

+#define HRTIM_MDIER_MCMP3DE_Msk       (0x1UL << HRTIM_MDIER_MCMP3DE_Pos)       /*!< 0x00040000 */

+#define HRTIM_MDIER_MCMP3DE           HRTIM_MDIER_MCMP3DE_Msk                  /*!< Master compare 3 DMA enable */

+#define HRTIM_MDIER_MCMP4DE_Pos       (19U)

+#define HRTIM_MDIER_MCMP4DE_Msk       (0x1UL << HRTIM_MDIER_MCMP4DE_Pos)       /*!< 0x00080000 */

+#define HRTIM_MDIER_MCMP4DE           HRTIM_MDIER_MCMP4DE_Msk                  /*!< Master compare 4 DMA enable */

+#define HRTIM_MDIER_MREPDE_Pos        (20U)

+#define HRTIM_MDIER_MREPDE_Msk        (0x1UL << HRTIM_MDIER_MREPDE_Pos)        /*!< 0x00100000 */

+#define HRTIM_MDIER_MREPDE            HRTIM_MDIER_MREPDE_Msk                   /*!< Master Repetition DMA enable */

+#define HRTIM_MDIER_SYNCDE_Pos        (21U)

+#define HRTIM_MDIER_SYNCDE_Msk        (0x1UL << HRTIM_MDIER_SYNCDE_Pos)        /*!< 0x00200000 */

+#define HRTIM_MDIER_SYNCDE            HRTIM_MDIER_SYNCDE_Msk                   /*!< Synchronization input DMA enable */

+#define HRTIM_MDIER_MUPDDE_Pos        (22U)

+#define HRTIM_MDIER_MUPDDE_Msk        (0x1UL << HRTIM_MDIER_MUPDDE_Pos)        /*!< 0x00400000 */

+#define HRTIM_MDIER_MUPDDE            HRTIM_MDIER_MUPDDE_Msk                   /*!< Master update DMA enable */

+

+/*******************  Bit definition for HRTIM_MCNTR register  ****************/

+#define HRTIM_MCNTR_MCNTR_Pos         (0U)

+#define HRTIM_MCNTR_MCNTR_Msk         (0xFFFFUL << HRTIM_MCNTR_MCNTR_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_MCNTR_MCNTR             HRTIM_MCNTR_MCNTR_Msk                    /*!<Counter Value */

+

+/*******************  Bit definition for HRTIM_MPER register  *****************/

+#define HRTIM_MPER_MPER_Pos           (0U)

+#define HRTIM_MPER_MPER_Msk           (0xFFFFUL << HRTIM_MPER_MPER_Pos)        /*!< 0x0000FFFF */

+#define HRTIM_MPER_MPER               HRTIM_MPER_MPER_Msk                      /*!< Period Value */

+

+/*******************  Bit definition for HRTIM_MREP register  *****************/

+#define HRTIM_MREP_MREP_Pos           (0U)

+#define HRTIM_MREP_MREP_Msk           (0xFFUL << HRTIM_MREP_MREP_Pos)          /*!< 0x000000FF */

+#define HRTIM_MREP_MREP               HRTIM_MREP_MREP_Msk                      /*!<Repetition Value */

+

+/*******************  Bit definition for HRTIM_MCMP1R register  *****************/

+#define HRTIM_MCMP1R_MCMP1R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP1R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP1R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP1R           HRTIM_MCMP1R_MCMP1R_Msk                  /*!<Compare Value */

+

+/*******************  Bit definition for HRTIM_MCMP2R register  *****************/

+#define HRTIM_MCMP1R_MCMP2R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP2R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP2R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP2R           HRTIM_MCMP1R_MCMP2R_Msk                  /*!<Compare Value */

+

+/*******************  Bit definition for HRTIM_MCMP3R register  *****************/

+#define HRTIM_MCMP1R_MCMP3R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP3R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP3R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP3R           HRTIM_MCMP1R_MCMP3R_Msk                  /*!<Compare Value */

+

+/*******************  Bit definition for HRTIM_MCMP4R register  *****************/

+#define HRTIM_MCMP1R_MCMP4R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP4R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP4R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP4R           HRTIM_MCMP1R_MCMP4R_Msk                  /*!<Compare Value */

+

+/******************** Slave control register **********************************/

+#define HRTIM_TIMCR_CK_PSC_Pos        (0U)

+#define HRTIM_TIMCR_CK_PSC_Msk        (0x7UL << HRTIM_TIMCR_CK_PSC_Pos)        /*!< 0x00000007 */

+#define HRTIM_TIMCR_CK_PSC            HRTIM_TIMCR_CK_PSC_Msk                   /*!< Slave prescaler mask*/

+#define HRTIM_TIMCR_CK_PSC_0          (0x1UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000001 */

+#define HRTIM_TIMCR_CK_PSC_1          (0x2UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000002 */

+#define HRTIM_TIMCR_CK_PSC_2          (0x4UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000004 */

+

+#define HRTIM_TIMCR_CONT_Pos          (3U)

+#define HRTIM_TIMCR_CONT_Msk          (0x1UL << HRTIM_TIMCR_CONT_Pos)          /*!< 0x00000008 */

+#define HRTIM_TIMCR_CONT              HRTIM_TIMCR_CONT_Msk                     /*!< Slave continuous mode */

+#define HRTIM_TIMCR_RETRIG_Pos        (4U)

+#define HRTIM_TIMCR_RETRIG_Msk        (0x1UL << HRTIM_TIMCR_RETRIG_Pos)        /*!< 0x00000010 */

+#define HRTIM_TIMCR_RETRIG            HRTIM_TIMCR_RETRIG_Msk                   /*!< Slave Retrigreable mode */

+#define HRTIM_TIMCR_HALF_Pos          (5U)

+#define HRTIM_TIMCR_HALF_Msk          (0x1UL << HRTIM_TIMCR_HALF_Pos)          /*!< 0x00000020 */

+#define HRTIM_TIMCR_HALF              HRTIM_TIMCR_HALF_Msk                     /*!< Slave Half mode */

+#define HRTIM_TIMCR_PSHPLL_Pos        (6U)

+#define HRTIM_TIMCR_PSHPLL_Msk        (0x1UL << HRTIM_TIMCR_PSHPLL_Pos)        /*!< 0x00000040 */

+#define HRTIM_TIMCR_PSHPLL            HRTIM_TIMCR_PSHPLL_Msk                   /*!< Slave push-pull mode */

+

+#define HRTIM_TIMCR_SYNCRST_Pos       (10U)

+#define HRTIM_TIMCR_SYNCRST_Msk       (0x1UL << HRTIM_TIMCR_SYNCRST_Pos)       /*!< 0x00000400 */

+#define HRTIM_TIMCR_SYNCRST           HRTIM_TIMCR_SYNCRST_Msk                  /*!< Slave synchronization resets */

+#define HRTIM_TIMCR_SYNCSTRT_Pos      (11U)

+#define HRTIM_TIMCR_SYNCSTRT_Msk      (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos)      /*!< 0x00000800 */

+#define HRTIM_TIMCR_SYNCSTRT          HRTIM_TIMCR_SYNCSTRT_Msk                 /*!< Slave synchronization starts */

+

+#define HRTIM_TIMCR_DELCMP2_Pos       (12U)

+#define HRTIM_TIMCR_DELCMP2_Msk       (0x3UL << HRTIM_TIMCR_DELCMP2_Pos)       /*!< 0x00003000 */

+#define HRTIM_TIMCR_DELCMP2           HRTIM_TIMCR_DELCMP2_Msk                  /*!< Slave delayed compartor 2 mode mask */

+#define HRTIM_TIMCR_DELCMP2_0         (0x1UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00001000 */

+#define HRTIM_TIMCR_DELCMP2_1         (0x2UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00002000 */

+#define HRTIM_TIMCR_DELCMP4_Pos       (14U)

+#define HRTIM_TIMCR_DELCMP4_Msk       (0x3UL << HRTIM_TIMCR_DELCMP4_Pos)       /*!< 0x0000C000 */

+#define HRTIM_TIMCR_DELCMP4           HRTIM_TIMCR_DELCMP4_Msk                  /*!< Slave delayed compartor 4 mode mask */

+#define HRTIM_TIMCR_DELCMP4_0         (0x1UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00004000 */

+#define HRTIM_TIMCR_DELCMP4_1         (0x2UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00008000 */

+

+#define HRTIM_TIMCR_TREPU_Pos         (17U)

+#define HRTIM_TIMCR_TREPU_Msk         (0x1UL << HRTIM_TIMCR_TREPU_Pos)         /*!< 0x00020000 */

+#define HRTIM_TIMCR_TREPU             HRTIM_TIMCR_TREPU_Msk                    /*!< Slave repetition update */

+#define HRTIM_TIMCR_TRSTU_Pos         (18U)

+#define HRTIM_TIMCR_TRSTU_Msk         (0x1UL << HRTIM_TIMCR_TRSTU_Pos)         /*!< 0x00040000 */

+#define HRTIM_TIMCR_TRSTU             HRTIM_TIMCR_TRSTU_Msk                    /*!< Slave reset update */

+#define HRTIM_TIMCR_TAU_Pos           (19U)

+#define HRTIM_TIMCR_TAU_Msk           (0x1UL << HRTIM_TIMCR_TAU_Pos)           /*!< 0x00080000 */

+#define HRTIM_TIMCR_TAU               HRTIM_TIMCR_TAU_Msk                      /*!< Slave Timer A update reserved for TIM A */

+#define HRTIM_TIMCR_TBU_Pos           (20U)

+#define HRTIM_TIMCR_TBU_Msk           (0x1UL << HRTIM_TIMCR_TBU_Pos)           /*!< 0x00100000 */

+#define HRTIM_TIMCR_TBU               HRTIM_TIMCR_TBU_Msk                      /*!< Slave Timer B update reserved for TIM B */

+#define HRTIM_TIMCR_TCU_Pos           (21U)

+#define HRTIM_TIMCR_TCU_Msk           (0x1UL << HRTIM_TIMCR_TCU_Pos)           /*!< 0x00200000 */

+#define HRTIM_TIMCR_TCU               HRTIM_TIMCR_TCU_Msk                      /*!< Slave Timer C update reserved for TIM C */

+#define HRTIM_TIMCR_TDU_Pos           (22U)

+#define HRTIM_TIMCR_TDU_Msk           (0x1UL << HRTIM_TIMCR_TDU_Pos)           /*!< 0x00400000 */

+#define HRTIM_TIMCR_TDU               HRTIM_TIMCR_TDU_Msk                      /*!< Slave Timer D update reserved for TIM D */

+#define HRTIM_TIMCR_TEU_Pos           (23U)

+#define HRTIM_TIMCR_TEU_Msk           (0x1UL << HRTIM_TIMCR_TEU_Pos)           /*!< 0x00800000 */

+#define HRTIM_TIMCR_TEU               HRTIM_TIMCR_TEU_Msk                      /*!< Slave Timer E update reserved for TIM E */

+#define HRTIM_TIMCR_MSTU_Pos          (24U)

+#define HRTIM_TIMCR_MSTU_Msk          (0x1UL << HRTIM_TIMCR_MSTU_Pos)          /*!< 0x01000000 */

+#define HRTIM_TIMCR_MSTU              HRTIM_TIMCR_MSTU_Msk                     /*!< Master Update */

+

+#define HRTIM_TIMCR_DACSYNC_Pos       (25U)

+#define HRTIM_TIMCR_DACSYNC_Msk       (0x3UL << HRTIM_TIMCR_DACSYNC_Pos)       /*!< 0x06000000 */

+#define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC sychronization mask */

+#define HRTIM_TIMCR_DACSYNC_0         (0x1UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x02000000 */

+#define HRTIM_TIMCR_DACSYNC_1         (0x2UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x04000000 */

+#define HRTIM_TIMCR_PREEN_Pos         (27U)

+#define HRTIM_TIMCR_PREEN_Msk         (0x1UL << HRTIM_TIMCR_PREEN_Pos)         /*!< 0x08000000 */

+#define HRTIM_TIMCR_PREEN             HRTIM_TIMCR_PREEN_Msk                    /*!< Slave preload enable */

+

+#define HRTIM_TIMCR_UPDGAT_Pos        (28U)

+#define HRTIM_TIMCR_UPDGAT_Msk        (0xFUL << HRTIM_TIMCR_UPDGAT_Pos)        /*!< 0xF0000000 */

+#define HRTIM_TIMCR_UPDGAT            HRTIM_TIMCR_UPDGAT_Msk                   /*!< Slave update gating mask */

+#define HRTIM_TIMCR_UPDGAT_0          (0x1UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x10000000 */

+#define HRTIM_TIMCR_UPDGAT_1          (0x2UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x20000000 */

+#define HRTIM_TIMCR_UPDGAT_2          (0x4UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x40000000 */

+#define HRTIM_TIMCR_UPDGAT_3          (0x8UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x80000000 */

+

+/******************** Slave Interrupt status register **************************/

+#define HRTIM_TIMISR_CMP1_Pos         (0U)

+#define HRTIM_TIMISR_CMP1_Msk         (0x1UL << HRTIM_TIMISR_CMP1_Pos)         /*!< 0x00000001 */

+#define HRTIM_TIMISR_CMP1             HRTIM_TIMISR_CMP1_Msk                    /*!< Slave compare 1 interrupt flag */

+#define HRTIM_TIMISR_CMP2_Pos         (1U)

+#define HRTIM_TIMISR_CMP2_Msk         (0x1UL << HRTIM_TIMISR_CMP2_Pos)         /*!< 0x00000002 */

+#define HRTIM_TIMISR_CMP2             HRTIM_TIMISR_CMP2_Msk                    /*!< Slave compare 2 interrupt flag */

+#define HRTIM_TIMISR_CMP3_Pos         (2U)

+#define HRTIM_TIMISR_CMP3_Msk         (0x1UL << HRTIM_TIMISR_CMP3_Pos)         /*!< 0x00000004 */

+#define HRTIM_TIMISR_CMP3             HRTIM_TIMISR_CMP3_Msk                    /*!< Slave compare 3 interrupt flag */

+#define HRTIM_TIMISR_CMP4_Pos         (3U)

+#define HRTIM_TIMISR_CMP4_Msk         (0x1UL << HRTIM_TIMISR_CMP4_Pos)         /*!< 0x00000008 */

+#define HRTIM_TIMISR_CMP4             HRTIM_TIMISR_CMP4_Msk                    /*!< Slave compare 4 interrupt flag */

+#define HRTIM_TIMISR_REP_Pos          (4U)

+#define HRTIM_TIMISR_REP_Msk          (0x1UL << HRTIM_TIMISR_REP_Pos)          /*!< 0x00000010 */

+#define HRTIM_TIMISR_REP              HRTIM_TIMISR_REP_Msk                     /*!< Slave repetition interrupt flag */

+#define HRTIM_TIMISR_UPD_Pos          (6U)

+#define HRTIM_TIMISR_UPD_Msk          (0x1UL << HRTIM_TIMISR_UPD_Pos)          /*!< 0x00000040 */

+#define HRTIM_TIMISR_UPD              HRTIM_TIMISR_UPD_Msk                     /*!< Slave update interrupt flag */

+#define HRTIM_TIMISR_CPT1_Pos         (7U)

+#define HRTIM_TIMISR_CPT1_Msk         (0x1UL << HRTIM_TIMISR_CPT1_Pos)         /*!< 0x00000080 */

+#define HRTIM_TIMISR_CPT1             HRTIM_TIMISR_CPT1_Msk                    /*!< Slave capture 1 interrupt flag */

+#define HRTIM_TIMISR_CPT2_Pos         (8U)

+#define HRTIM_TIMISR_CPT2_Msk         (0x1UL << HRTIM_TIMISR_CPT2_Pos)         /*!< 0x00000100 */

+#define HRTIM_TIMISR_CPT2             HRTIM_TIMISR_CPT2_Msk                    /*!< Slave capture 2 interrupt flag */

+#define HRTIM_TIMISR_SET1_Pos         (9U)

+#define HRTIM_TIMISR_SET1_Msk         (0x1UL << HRTIM_TIMISR_SET1_Pos)         /*!< 0x00000200 */

+#define HRTIM_TIMISR_SET1             HRTIM_TIMISR_SET1_Msk                    /*!< Slave output 1 set interrupt flag */

+#define HRTIM_TIMISR_RST1_Pos         (10U)

+#define HRTIM_TIMISR_RST1_Msk         (0x1UL << HRTIM_TIMISR_RST1_Pos)         /*!< 0x00000400 */

+#define HRTIM_TIMISR_RST1             HRTIM_TIMISR_RST1_Msk                    /*!< Slave output 1 reset interrupt flag */

+#define HRTIM_TIMISR_SET2_Pos         (11U)

+#define HRTIM_TIMISR_SET2_Msk         (0x1UL << HRTIM_TIMISR_SET2_Pos)         /*!< 0x00000800 */

+#define HRTIM_TIMISR_SET2             HRTIM_TIMISR_SET2_Msk                    /*!< Slave output 2 set interrupt flag */

+#define HRTIM_TIMISR_RST2_Pos         (12U)

+#define HRTIM_TIMISR_RST2_Msk         (0x1UL << HRTIM_TIMISR_RST2_Pos)         /*!< 0x00001000 */

+#define HRTIM_TIMISR_RST2             HRTIM_TIMISR_RST2_Msk                    /*!< Slave output 2 reset interrupt flag */

+#define HRTIM_TIMISR_RST_Pos          (13U)

+#define HRTIM_TIMISR_RST_Msk          (0x1UL << HRTIM_TIMISR_RST_Pos)          /*!< 0x00002000 */

+#define HRTIM_TIMISR_RST              HRTIM_TIMISR_RST_Msk                     /*!< Slave reset interrupt flag */

+#define HRTIM_TIMISR_DLYPRT_Pos       (14U)

+#define HRTIM_TIMISR_DLYPRT_Msk       (0x1UL << HRTIM_TIMISR_DLYPRT_Pos)       /*!< 0x00004000 */

+#define HRTIM_TIMISR_DLYPRT           HRTIM_TIMISR_DLYPRT_Msk                  /*!< Slave output 1 delay protection interrupt flag */

+#define HRTIM_TIMISR_CPPSTAT_Pos      (16U)

+#define HRTIM_TIMISR_CPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos)      /*!< 0x00010000 */

+#define HRTIM_TIMISR_CPPSTAT          HRTIM_TIMISR_CPPSTAT_Msk                 /*!< Slave current push-pull flag */

+#define HRTIM_TIMISR_IPPSTAT_Pos      (17U)

+#define HRTIM_TIMISR_IPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos)      /*!< 0x00020000 */

+#define HRTIM_TIMISR_IPPSTAT          HRTIM_TIMISR_IPPSTAT_Msk                 /*!< Slave idle push-pull flag */

+#define HRTIM_TIMISR_O1STAT_Pos       (18U)

+#define HRTIM_TIMISR_O1STAT_Msk       (0x1UL << HRTIM_TIMISR_O1STAT_Pos)       /*!< 0x00040000 */

+#define HRTIM_TIMISR_O1STAT           HRTIM_TIMISR_O1STAT_Msk                  /*!< Slave output 1 state flag */

+#define HRTIM_TIMISR_O2STAT_Pos       (19U)

+#define HRTIM_TIMISR_O2STAT_Msk       (0x1UL << HRTIM_TIMISR_O2STAT_Pos)       /*!< 0x00080000 */

+#define HRTIM_TIMISR_O2STAT           HRTIM_TIMISR_O2STAT_Msk                  /*!< Slave output 2 state flag */

+#define HRTIM_TIMISR_O1CPY_Pos        (20U)

+#define HRTIM_TIMISR_O1CPY_Msk        (0x1UL << HRTIM_TIMISR_O1CPY_Pos)        /*!< 0x00100000 */

+#define HRTIM_TIMISR_O1CPY            HRTIM_TIMISR_O1CPY_Msk                   /*!< Slave output 1 copy flag */

+#define HRTIM_TIMISR_O2CPY_Pos        (21U)

+#define HRTIM_TIMISR_O2CPY_Msk        (0x1UL << HRTIM_TIMISR_O2CPY_Pos)        /*!< 0x00200000 */

+#define HRTIM_TIMISR_O2CPY            HRTIM_TIMISR_O2CPY_Msk                   /*!< Slave output 2 copy flag */

+

+/******************** Slave Interrupt clear register **************************/

+#define HRTIM_TIMICR_CMP1C_Pos        (0U)

+#define HRTIM_TIMICR_CMP1C_Msk        (0x1UL << HRTIM_TIMICR_CMP1C_Pos)        /*!< 0x00000001 */

+#define HRTIM_TIMICR_CMP1C            HRTIM_TIMICR_CMP1C_Msk                   /*!< Slave compare 1 clear flag */

+#define HRTIM_TIMICR_CMP2C_Pos        (1U)

+#define HRTIM_TIMICR_CMP2C_Msk        (0x1UL << HRTIM_TIMICR_CMP2C_Pos)        /*!< 0x00000002 */

+#define HRTIM_TIMICR_CMP2C            HRTIM_TIMICR_CMP2C_Msk                   /*!< Slave compare 2 clear flag */

+#define HRTIM_TIMICR_CMP3C_Pos        (2U)

+#define HRTIM_TIMICR_CMP3C_Msk        (0x1UL << HRTIM_TIMICR_CMP3C_Pos)        /*!< 0x00000004 */

+#define HRTIM_TIMICR_CMP3C            HRTIM_TIMICR_CMP3C_Msk                   /*!< Slave compare 3 clear flag */

+#define HRTIM_TIMICR_CMP4C_Pos        (3U)

+#define HRTIM_TIMICR_CMP4C_Msk        (0x1UL << HRTIM_TIMICR_CMP4C_Pos)        /*!< 0x00000008 */

+#define HRTIM_TIMICR_CMP4C            HRTIM_TIMICR_CMP4C_Msk                   /*!< Slave compare 4 clear flag */

+#define HRTIM_TIMICR_REPC_Pos         (4U)

+#define HRTIM_TIMICR_REPC_Msk         (0x1UL << HRTIM_TIMICR_REPC_Pos)         /*!< 0x00000010 */

+#define HRTIM_TIMICR_REPC             HRTIM_TIMICR_REPC_Msk                    /*!< Slave repetition clear flag */

+#define HRTIM_TIMICR_UPDC_Pos         (6U)

+#define HRTIM_TIMICR_UPDC_Msk         (0x1UL << HRTIM_TIMICR_UPDC_Pos)         /*!< 0x00000040 */

+#define HRTIM_TIMICR_UPDC             HRTIM_TIMICR_UPDC_Msk                    /*!< Slave update clear flag */

+#define HRTIM_TIMICR_CPT1C_Pos        (7U)

+#define HRTIM_TIMICR_CPT1C_Msk        (0x1UL << HRTIM_TIMICR_CPT1C_Pos)        /*!< 0x00000080 */

+#define HRTIM_TIMICR_CPT1C            HRTIM_TIMICR_CPT1C_Msk                   /*!< Slave capture 1 clear flag */

+#define HRTIM_TIMICR_CPT2C_Pos        (8U)

+#define HRTIM_TIMICR_CPT2C_Msk        (0x1UL << HRTIM_TIMICR_CPT2C_Pos)        /*!< 0x00000100 */

+#define HRTIM_TIMICR_CPT2C            HRTIM_TIMICR_CPT2C_Msk                   /*!< Slave capture 2 clear flag */

+#define HRTIM_TIMICR_SET1C_Pos        (9U)

+#define HRTIM_TIMICR_SET1C_Msk        (0x1UL << HRTIM_TIMICR_SET1C_Pos)        /*!< 0x00000200 */

+#define HRTIM_TIMICR_SET1C            HRTIM_TIMICR_SET1C_Msk                   /*!< Slave output 1 set clear flag */

+#define HRTIM_TIMICR_RST1C_Pos        (10U)

+#define HRTIM_TIMICR_RST1C_Msk        (0x1UL << HRTIM_TIMICR_RST1C_Pos)        /*!< 0x00000400 */

+#define HRTIM_TIMICR_RST1C            HRTIM_TIMICR_RST1C_Msk                   /*!< Slave output 1 reset clear flag */

+#define HRTIM_TIMICR_SET2C_Pos        (11U)

+#define HRTIM_TIMICR_SET2C_Msk        (0x1UL << HRTIM_TIMICR_SET2C_Pos)        /*!< 0x00000800 */

+#define HRTIM_TIMICR_SET2C            HRTIM_TIMICR_SET2C_Msk                   /*!< Slave output 2 set clear flag */

+#define HRTIM_TIMICR_RST2C_Pos        (12U)

+#define HRTIM_TIMICR_RST2C_Msk        (0x1UL << HRTIM_TIMICR_RST2C_Pos)        /*!< 0x00001000 */

+#define HRTIM_TIMICR_RST2C            HRTIM_TIMICR_RST2C_Msk                   /*!< Slave output 2 reset clear flag */

+#define HRTIM_TIMICR_RSTC_Pos         (13U)

+#define HRTIM_TIMICR_RSTC_Msk         (0x1UL << HRTIM_TIMICR_RSTC_Pos)         /*!< 0x00002000 */

+#define HRTIM_TIMICR_RSTC             HRTIM_TIMICR_RSTC_Msk                    /*!< Slave reset clear flag */

+#define HRTIM_TIMICR_DLYPRTC_Pos      (14U)

+#define HRTIM_TIMICR_DLYPRTC_Msk      (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos)      /*!< 0x00004000 */

+#define HRTIM_TIMICR_DLYPRTC          HRTIM_TIMICR_DLYPRTC_Msk                 /*!< Slave output 1 delay protection clear flag */

+

+/******************** Slave DMA/Interrupt enable register *********************/

+#define HRTIM_TIMDIER_CMP1IE_Pos      (0U)

+#define HRTIM_TIMDIER_CMP1IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos)      /*!< 0x00000001 */

+#define HRTIM_TIMDIER_CMP1IE          HRTIM_TIMDIER_CMP1IE_Msk                 /*!< Slave compare 1 interrupt enable */

+#define HRTIM_TIMDIER_CMP2IE_Pos      (1U)

+#define HRTIM_TIMDIER_CMP2IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos)      /*!< 0x00000002 */

+#define HRTIM_TIMDIER_CMP2IE          HRTIM_TIMDIER_CMP2IE_Msk                 /*!< Slave compare 2 interrupt enable */

+#define HRTIM_TIMDIER_CMP3IE_Pos      (2U)

+#define HRTIM_TIMDIER_CMP3IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos)      /*!< 0x00000004 */

+#define HRTIM_TIMDIER_CMP3IE          HRTIM_TIMDIER_CMP3IE_Msk                 /*!< Slave compare 3 interrupt enable */

+#define HRTIM_TIMDIER_CMP4IE_Pos      (3U)

+#define HRTIM_TIMDIER_CMP4IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos)      /*!< 0x00000008 */

+#define HRTIM_TIMDIER_CMP4IE          HRTIM_TIMDIER_CMP4IE_Msk                 /*!< Slave compare 4 interrupt enable */

+#define HRTIM_TIMDIER_REPIE_Pos       (4U)

+#define HRTIM_TIMDIER_REPIE_Msk       (0x1UL << HRTIM_TIMDIER_REPIE_Pos)       /*!< 0x00000010 */

+#define HRTIM_TIMDIER_REPIE           HRTIM_TIMDIER_REPIE_Msk                  /*!< Slave repetition interrupt enable */

+#define HRTIM_TIMDIER_UPDIE_Pos       (6U)

+#define HRTIM_TIMDIER_UPDIE_Msk       (0x1UL << HRTIM_TIMDIER_UPDIE_Pos)       /*!< 0x00000040 */

+#define HRTIM_TIMDIER_UPDIE           HRTIM_TIMDIER_UPDIE_Msk                  /*!< Slave update interrupt enable */

+#define HRTIM_TIMDIER_CPT1IE_Pos      (7U)

+#define HRTIM_TIMDIER_CPT1IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos)      /*!< 0x00000080 */

+#define HRTIM_TIMDIER_CPT1IE          HRTIM_TIMDIER_CPT1IE_Msk                 /*!< Slave capture 1 interrupt enable */

+#define HRTIM_TIMDIER_CPT2IE_Pos      (8U)

+#define HRTIM_TIMDIER_CPT2IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos)      /*!< 0x00000100 */

+#define HRTIM_TIMDIER_CPT2IE          HRTIM_TIMDIER_CPT2IE_Msk                 /*!< Slave capture 2 interrupt enable */

+#define HRTIM_TIMDIER_SET1IE_Pos      (9U)

+#define HRTIM_TIMDIER_SET1IE_Msk      (0x1UL << HRTIM_TIMDIER_SET1IE_Pos)      /*!< 0x00000200 */

+#define HRTIM_TIMDIER_SET1IE          HRTIM_TIMDIER_SET1IE_Msk                 /*!< Slave output 1 set interrupt enable */

+#define HRTIM_TIMDIER_RST1IE_Pos      (10U)

+#define HRTIM_TIMDIER_RST1IE_Msk      (0x1UL << HRTIM_TIMDIER_RST1IE_Pos)      /*!< 0x00000400 */

+#define HRTIM_TIMDIER_RST1IE          HRTIM_TIMDIER_RST1IE_Msk                 /*!< Slave output 1 reset interrupt enable */

+#define HRTIM_TIMDIER_SET2IE_Pos      (11U)

+#define HRTIM_TIMDIER_SET2IE_Msk      (0x1UL << HRTIM_TIMDIER_SET2IE_Pos)      /*!< 0x00000800 */

+#define HRTIM_TIMDIER_SET2IE          HRTIM_TIMDIER_SET2IE_Msk                 /*!< Slave output 2 set interrupt enable */

+#define HRTIM_TIMDIER_RST2IE_Pos      (12U)

+#define HRTIM_TIMDIER_RST2IE_Msk      (0x1UL << HRTIM_TIMDIER_RST2IE_Pos)      /*!< 0x00001000 */

+#define HRTIM_TIMDIER_RST2IE          HRTIM_TIMDIER_RST2IE_Msk                 /*!< Slave output 2 reset interrupt enable */

+#define HRTIM_TIMDIER_RSTIE_Pos       (13U)

+#define HRTIM_TIMDIER_RSTIE_Msk       (0x1UL << HRTIM_TIMDIER_RSTIE_Pos)       /*!< 0x00002000 */

+#define HRTIM_TIMDIER_RSTIE           HRTIM_TIMDIER_RSTIE_Msk                  /*!< Slave reset interrupt enable */

+#define HRTIM_TIMDIER_DLYPRTIE_Pos    (14U)

+#define HRTIM_TIMDIER_DLYPRTIE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos)    /*!< 0x00004000 */

+#define HRTIM_TIMDIER_DLYPRTIE        HRTIM_TIMDIER_DLYPRTIE_Msk               /*!< Slave delay protection interrupt enable */

+

+#define HRTIM_TIMDIER_CMP1DE_Pos      (16U)

+#define HRTIM_TIMDIER_CMP1DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos)      /*!< 0x00010000 */

+#define HRTIM_TIMDIER_CMP1DE          HRTIM_TIMDIER_CMP1DE_Msk                 /*!< Slave compare 1 request enable */

+#define HRTIM_TIMDIER_CMP2DE_Pos      (17U)

+#define HRTIM_TIMDIER_CMP2DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos)      /*!< 0x00020000 */

+#define HRTIM_TIMDIER_CMP2DE          HRTIM_TIMDIER_CMP2DE_Msk                 /*!< Slave compare 2 request enable */

+#define HRTIM_TIMDIER_CMP3DE_Pos      (18U)

+#define HRTIM_TIMDIER_CMP3DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos)      /*!< 0x00040000 */

+#define HRTIM_TIMDIER_CMP3DE          HRTIM_TIMDIER_CMP3DE_Msk                 /*!< Slave compare 3 request enable */

+#define HRTIM_TIMDIER_CMP4DE_Pos      (19U)

+#define HRTIM_TIMDIER_CMP4DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos)      /*!< 0x00080000 */

+#define HRTIM_TIMDIER_CMP4DE          HRTIM_TIMDIER_CMP4DE_Msk                 /*!< Slave compare 4 request enable */

+#define HRTIM_TIMDIER_REPDE_Pos       (20U)

+#define HRTIM_TIMDIER_REPDE_Msk       (0x1UL << HRTIM_TIMDIER_REPDE_Pos)       /*!< 0x00100000 */

+#define HRTIM_TIMDIER_REPDE           HRTIM_TIMDIER_REPDE_Msk                  /*!< Slave repetition request enable */

+#define HRTIM_TIMDIER_UPDDE_Pos       (22U)

+#define HRTIM_TIMDIER_UPDDE_Msk       (0x1UL << HRTIM_TIMDIER_UPDDE_Pos)       /*!< 0x00400000 */

+#define HRTIM_TIMDIER_UPDDE           HRTIM_TIMDIER_UPDDE_Msk                  /*!< Slave update request enable */

+#define HRTIM_TIMDIER_CPT1DE_Pos      (23U)

+#define HRTIM_TIMDIER_CPT1DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos)      /*!< 0x00800000 */

+#define HRTIM_TIMDIER_CPT1DE          HRTIM_TIMDIER_CPT1DE_Msk                 /*!< Slave capture 1 request enable */

+#define HRTIM_TIMDIER_CPT2DE_Pos      (24U)

+#define HRTIM_TIMDIER_CPT2DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos)      /*!< 0x01000000 */

+#define HRTIM_TIMDIER_CPT2DE          HRTIM_TIMDIER_CPT2DE_Msk                 /*!< Slave capture 2 request enable */

+#define HRTIM_TIMDIER_SET1DE_Pos      (25U)

+#define HRTIM_TIMDIER_SET1DE_Msk      (0x1UL << HRTIM_TIMDIER_SET1DE_Pos)      /*!< 0x02000000 */

+#define HRTIM_TIMDIER_SET1DE          HRTIM_TIMDIER_SET1DE_Msk                 /*!< Slave output 1 set request enable */

+#define HRTIM_TIMDIER_RST1DE_Pos      (26U)

+#define HRTIM_TIMDIER_RST1DE_Msk      (0x1UL << HRTIM_TIMDIER_RST1DE_Pos)      /*!< 0x04000000 */

+#define HRTIM_TIMDIER_RST1DE          HRTIM_TIMDIER_RST1DE_Msk                 /*!< Slave output 1 reset request enable */

+#define HRTIM_TIMDIER_SET2DE_Pos      (27U)

+#define HRTIM_TIMDIER_SET2DE_Msk      (0x1UL << HRTIM_TIMDIER_SET2DE_Pos)      /*!< 0x08000000 */

+#define HRTIM_TIMDIER_SET2DE          HRTIM_TIMDIER_SET2DE_Msk                 /*!< Slave output 2 set request enable */

+#define HRTIM_TIMDIER_RST2DE_Pos      (28U)

+#define HRTIM_TIMDIER_RST2DE_Msk      (0x1UL << HRTIM_TIMDIER_RST2DE_Pos)      /*!< 0x10000000 */

+#define HRTIM_TIMDIER_RST2DE          HRTIM_TIMDIER_RST2DE_Msk                 /*!< Slave output 2 reset request enable */

+#define HRTIM_TIMDIER_RSTDE_Pos       (29U)

+#define HRTIM_TIMDIER_RSTDE_Msk       (0x1UL << HRTIM_TIMDIER_RSTDE_Pos)       /*!< 0x20000000 */

+#define HRTIM_TIMDIER_RSTDE           HRTIM_TIMDIER_RSTDE_Msk                  /*!< Slave reset request enable */

+#define HRTIM_TIMDIER_DLYPRTDE_Pos    (30U)

+#define HRTIM_TIMDIER_DLYPRTDE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos)    /*!< 0x40000000 */

+#define HRTIM_TIMDIER_DLYPRTDE        HRTIM_TIMDIER_DLYPRTDE_Msk               /*!< Slavedelay protection request enable */

+

+/******************  Bit definition for HRTIM_CNTR register  ****************/

+#define HRTIM_CNTR_CNTR_Pos           (0U)

+#define HRTIM_CNTR_CNTR_Msk           (0xFFFFUL << HRTIM_CNTR_CNTR_Pos)        /*!< 0x0000FFFF */

+#define HRTIM_CNTR_CNTR               HRTIM_CNTR_CNTR_Msk                      /*!< Counter Value */

+

+/*******************  Bit definition for HRTIM_PER register  *****************/

+#define HRTIM_PER_PER_Pos             (0U)

+#define HRTIM_PER_PER_Msk             (0xFFFFUL << HRTIM_PER_PER_Pos)          /*!< 0x0000FFFF */

+#define HRTIM_PER_PER                 HRTIM_PER_PER_Msk                        /*!< Period Value */

+

+/*******************  Bit definition for HRTIM_REP register  *****************/

+#define HRTIM_REP_REP_Pos             (0U)

+#define HRTIM_REP_REP_Msk             (0xFFUL << HRTIM_REP_REP_Pos)            /*!< 0x000000FF */

+#define HRTIM_REP_REP                 HRTIM_REP_REP_Msk                        /*!< Repetition Value */

+

+/*******************  Bit definition for HRTIM_CMP1R register  *****************/

+#define HRTIM_CMP1R_CMP1R_Pos         (0U)

+#define HRTIM_CMP1R_CMP1R_Msk         (0xFFFFUL << HRTIM_CMP1R_CMP1R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP1R_CMP1R             HRTIM_CMP1R_CMP1R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP1CR register  *****************/

+#define HRTIM_CMP1CR_CMP1CR_Pos       (0U)

+#define HRTIM_CMP1CR_CMP1CR_Msk       (0xFFFFFFFFUL << HRTIM_CMP1CR_CMP1CR_Pos) /*!< 0xFFFFFFFF */

+#define HRTIM_CMP1CR_CMP1CR           HRTIM_CMP1CR_CMP1CR_Msk                  /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP2R register  *****************/

+#define HRTIM_CMP2R_CMP2R_Pos         (0U)

+#define HRTIM_CMP2R_CMP2R_Msk         (0xFFFFUL << HRTIM_CMP2R_CMP2R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP2R_CMP2R             HRTIM_CMP2R_CMP2R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP3R register  *****************/

+#define HRTIM_CMP3R_CMP3R_Pos         (0U)

+#define HRTIM_CMP3R_CMP3R_Msk         (0xFFFFUL << HRTIM_CMP3R_CMP3R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP3R_CMP3R             HRTIM_CMP3R_CMP3R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP4R register  *****************/

+#define HRTIM_CMP4R_CMP4R_Pos         (0U)

+#define HRTIM_CMP4R_CMP4R_Msk         (0xFFFFUL << HRTIM_CMP4R_CMP4R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP4R_CMP4R             HRTIM_CMP4R_CMP4R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CPT1R register  ****************/

+#define HRTIM_CPT1R_CPT1R_Pos         (0U)

+#define HRTIM_CPT1R_CPT1R_Msk         (0xFFFFUL << HRTIM_CPT1R_CPT1R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CPT1R_CPT1R             HRTIM_CPT1R_CPT1R_Msk                    /*!< Capture Value */

+

+/*******************  Bit definition for HRTIM_CPT2R register  ****************/

+#define HRTIM_CPT2R_CPT2R_Pos         (0U)

+#define HRTIM_CPT2R_CPT2R_Msk         (0xFFFFUL << HRTIM_CPT2R_CPT2R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CPT2R_CPT2R             HRTIM_CPT2R_CPT2R_Msk                    /*!< Capture Value */

+

+/******************** Bit definition for Slave Deadtime register **************/

+#define HRTIM_DTR_DTR_Pos             (0U)

+#define HRTIM_DTR_DTR_Msk             (0x1FFUL << HRTIM_DTR_DTR_Pos)           /*!< 0x000001FF */

+#define HRTIM_DTR_DTR                 HRTIM_DTR_DTR_Msk                        /*!< Dead time rising value */

+#define HRTIM_DTR_DTR_0               (0x001UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000001 */

+#define HRTIM_DTR_DTR_1               (0x002UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000002 */

+#define HRTIM_DTR_DTR_2               (0x004UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000004 */

+#define HRTIM_DTR_DTR_3               (0x008UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000008 */

+#define HRTIM_DTR_DTR_4               (0x010UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000010 */

+#define HRTIM_DTR_DTR_5               (0x020UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000020 */

+#define HRTIM_DTR_DTR_6               (0x040UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000040 */

+#define HRTIM_DTR_DTR_7               (0x080UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000080 */

+#define HRTIM_DTR_DTR_8               (0x100UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000100 */

+#define HRTIM_DTR_SDTR_Pos            (9U)

+#define HRTIM_DTR_SDTR_Msk            (0x1UL << HRTIM_DTR_SDTR_Pos)            /*!< 0x00000200 */

+#define HRTIM_DTR_SDTR                HRTIM_DTR_SDTR_Msk                       /*!< Sign dead time rising value */

+#define HRTIM_DTR_DTPRSC_Pos          (10U)

+#define HRTIM_DTR_DTPRSC_Msk          (0x7UL << HRTIM_DTR_DTPRSC_Pos)          /*!< 0x00001C00 */

+#define HRTIM_DTR_DTPRSC              HRTIM_DTR_DTPRSC_Msk                     /*!< Dead time prescaler */

+#define HRTIM_DTR_DTPRSC_0            (0x1UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000400 */

+#define HRTIM_DTR_DTPRSC_1            (0x2UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000800 */

+#define HRTIM_DTR_DTPRSC_2            (0x4UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00001000 */

+#define HRTIM_DTR_DTRSLK_Pos          (14U)

+#define HRTIM_DTR_DTRSLK_Msk          (0x1UL << HRTIM_DTR_DTRSLK_Pos)          /*!< 0x00004000 */

+#define HRTIM_DTR_DTRSLK              HRTIM_DTR_DTRSLK_Msk                     /*!< Dead time rising sign lock */

+#define HRTIM_DTR_DTRLK_Pos           (15U)

+#define HRTIM_DTR_DTRLK_Msk           (0x1UL << HRTIM_DTR_DTRLK_Pos)           /*!< 0x00008000 */

+#define HRTIM_DTR_DTRLK               HRTIM_DTR_DTRLK_Msk                      /*!< Dead time rising lock */

+#define HRTIM_DTR_DTF_Pos             (16U)

+#define HRTIM_DTR_DTF_Msk             (0x1FFUL << HRTIM_DTR_DTF_Pos)           /*!< 0x01FF0000 */

+#define HRTIM_DTR_DTF                 HRTIM_DTR_DTF_Msk                        /*!< Dead time falling value */

+#define HRTIM_DTR_DTF_0               (0x001UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00010000 */

+#define HRTIM_DTR_DTF_1               (0x002UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00020000 */

+#define HRTIM_DTR_DTF_2               (0x004UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00040000 */

+#define HRTIM_DTR_DTF_3               (0x008UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00080000 */

+#define HRTIM_DTR_DTF_4               (0x010UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00100000 */

+#define HRTIM_DTR_DTF_5               (0x020UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00200000 */

+#define HRTIM_DTR_DTF_6               (0x040UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00400000 */

+#define HRTIM_DTR_DTF_7               (0x080UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00800000 */

+#define HRTIM_DTR_DTF_8               (0x100UL << HRTIM_DTR_DTF_Pos)            /*!< 0x01000000 */

+#define HRTIM_DTR_SDTF_Pos            (25U)

+#define HRTIM_DTR_SDTF_Msk            (0x1UL << HRTIM_DTR_SDTF_Pos)            /*!< 0x02000000 */

+#define HRTIM_DTR_SDTF                HRTIM_DTR_SDTF_Msk                       /*!< Sign dead time falling value */

+#define HRTIM_DTR_DTFSLK_Pos          (30U)

+#define HRTIM_DTR_DTFSLK_Msk          (0x1UL << HRTIM_DTR_DTFSLK_Pos)          /*!< 0x40000000 */

+#define HRTIM_DTR_DTFSLK              HRTIM_DTR_DTFSLK_Msk                     /*!< Dead time falling sign lock */

+#define HRTIM_DTR_DTFLK_Pos           (31U)

+#define HRTIM_DTR_DTFLK_Msk           (0x1UL << HRTIM_DTR_DTFLK_Pos)           /*!< 0x80000000 */

+#define HRTIM_DTR_DTFLK               HRTIM_DTR_DTFLK_Msk                      /*!< Dead time falling lock */

+

+/**** Bit definition for Slave Output 1 set register **************************/

+#define HRTIM_SET1R_SST_Pos           (0U)

+#define HRTIM_SET1R_SST_Msk           (0x1UL << HRTIM_SET1R_SST_Pos)           /*!< 0x00000001 */

+#define HRTIM_SET1R_SST               HRTIM_SET1R_SST_Msk                      /*!< software set trigger */

+#define HRTIM_SET1R_RESYNC_Pos        (1U)

+#define HRTIM_SET1R_RESYNC_Msk        (0x1UL << HRTIM_SET1R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_SET1R_RESYNC            HRTIM_SET1R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_SET1R_PER_Pos           (2U)

+#define HRTIM_SET1R_PER_Msk           (0x1UL << HRTIM_SET1R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_SET1R_PER               HRTIM_SET1R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_SET1R_CMP1_Pos          (3U)

+#define HRTIM_SET1R_CMP1_Msk          (0x1UL << HRTIM_SET1R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_SET1R_CMP1              HRTIM_SET1R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_SET1R_CMP2_Pos          (4U)

+#define HRTIM_SET1R_CMP2_Msk          (0x1UL << HRTIM_SET1R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_SET1R_CMP2              HRTIM_SET1R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_SET1R_CMP3_Pos          (5U)

+#define HRTIM_SET1R_CMP3_Msk          (0x1UL << HRTIM_SET1R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_SET1R_CMP3              HRTIM_SET1R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_SET1R_CMP4_Pos          (6U)

+#define HRTIM_SET1R_CMP4_Msk          (0x1UL << HRTIM_SET1R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_SET1R_CMP4              HRTIM_SET1R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_SET1R_MSTPER_Pos        (7U)

+#define HRTIM_SET1R_MSTPER_Msk        (0x1UL << HRTIM_SET1R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_SET1R_MSTPER            HRTIM_SET1R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_SET1R_MSTCMP1_Pos       (8U)

+#define HRTIM_SET1R_MSTCMP1_Msk       (0x1UL << HRTIM_SET1R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_SET1R_MSTCMP1           HRTIM_SET1R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_SET1R_MSTCMP2_Pos       (9U)

+#define HRTIM_SET1R_MSTCMP2_Msk       (0x1UL << HRTIM_SET1R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_SET1R_MSTCMP2           HRTIM_SET1R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_SET1R_MSTCMP3_Pos       (10U)

+#define HRTIM_SET1R_MSTCMP3_Msk       (0x1UL << HRTIM_SET1R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_SET1R_MSTCMP3           HRTIM_SET1R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_SET1R_MSTCMP4_Pos       (11U)

+#define HRTIM_SET1R_MSTCMP4_Msk       (0x1UL << HRTIM_SET1R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_SET1R_MSTCMP4           HRTIM_SET1R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_SET1R_TIMEVNT1_Pos      (12U)

+#define HRTIM_SET1R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_SET1R_TIMEVNT1          HRTIM_SET1R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_SET1R_TIMEVNT2_Pos      (13U)

+#define HRTIM_SET1R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_SET1R_TIMEVNT2          HRTIM_SET1R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_SET1R_TIMEVNT3_Pos      (14U)

+#define HRTIM_SET1R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_SET1R_TIMEVNT3          HRTIM_SET1R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_SET1R_TIMEVNT4_Pos      (15U)

+#define HRTIM_SET1R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_SET1R_TIMEVNT4          HRTIM_SET1R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_SET1R_TIMEVNT5_Pos      (16U)

+#define HRTIM_SET1R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_SET1R_TIMEVNT5          HRTIM_SET1R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_SET1R_TIMEVNT6_Pos      (17U)

+#define HRTIM_SET1R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_SET1R_TIMEVNT6          HRTIM_SET1R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_SET1R_TIMEVNT7_Pos      (18U)

+#define HRTIM_SET1R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_SET1R_TIMEVNT7          HRTIM_SET1R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_SET1R_TIMEVNT8_Pos      (19U)

+#define HRTIM_SET1R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_SET1R_TIMEVNT8          HRTIM_SET1R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_SET1R_TIMEVNT9_Pos      (20U)

+#define HRTIM_SET1R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_SET1R_TIMEVNT9          HRTIM_SET1R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_SET1R_EXTVNT1_Pos       (21U)

+#define HRTIM_SET1R_EXTVNT1_Msk       (0x1UL << HRTIM_SET1R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_SET1R_EXTVNT1           HRTIM_SET1R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_SET1R_EXTVNT2_Pos       (22U)

+#define HRTIM_SET1R_EXTVNT2_Msk       (0x1UL << HRTIM_SET1R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_SET1R_EXTVNT2           HRTIM_SET1R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_SET1R_EXTVNT3_Pos       (23U)

+#define HRTIM_SET1R_EXTVNT3_Msk       (0x1UL << HRTIM_SET1R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_SET1R_EXTVNT3           HRTIM_SET1R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_SET1R_EXTVNT4_Pos       (24U)

+#define HRTIM_SET1R_EXTVNT4_Msk       (0x1UL << HRTIM_SET1R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_SET1R_EXTVNT4           HRTIM_SET1R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_SET1R_EXTVNT5_Pos       (25U)

+#define HRTIM_SET1R_EXTVNT5_Msk       (0x1UL << HRTIM_SET1R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_SET1R_EXTVNT5           HRTIM_SET1R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_SET1R_EXTVNT6_Pos       (26U)

+#define HRTIM_SET1R_EXTVNT6_Msk       (0x1UL << HRTIM_SET1R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_SET1R_EXTVNT6           HRTIM_SET1R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_SET1R_EXTVNT7_Pos       (27U)

+#define HRTIM_SET1R_EXTVNT7_Msk       (0x1UL << HRTIM_SET1R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_SET1R_EXTVNT7           HRTIM_SET1R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_SET1R_EXTVNT8_Pos       (28U)

+#define HRTIM_SET1R_EXTVNT8_Msk       (0x1UL << HRTIM_SET1R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_SET1R_EXTVNT8           HRTIM_SET1R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_SET1R_EXTVNT9_Pos       (29U)

+#define HRTIM_SET1R_EXTVNT9_Msk       (0x1UL << HRTIM_SET1R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_SET1R_EXTVNT9           HRTIM_SET1R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_SET1R_EXTVNT10_Pos      (30U)

+#define HRTIM_SET1R_EXTVNT10_Msk      (0x1UL << HRTIM_SET1R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_SET1R_EXTVNT10          HRTIM_SET1R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_SET1R_UPDATE_Pos        (31U)

+#define HRTIM_SET1R_UPDATE_Msk        (0x1UL << HRTIM_SET1R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_SET1R_UPDATE            HRTIM_SET1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+/**** Bit definition for Slave Output 1 reset register ************************/

+#define HRTIM_RST1R_SRT_Pos           (0U)

+#define HRTIM_RST1R_SRT_Msk           (0x1UL << HRTIM_RST1R_SRT_Pos)           /*!< 0x00000001 */

+#define HRTIM_RST1R_SRT               HRTIM_RST1R_SRT_Msk                      /*!< software reset trigger */

+#define HRTIM_RST1R_RESYNC_Pos        (1U)

+#define HRTIM_RST1R_RESYNC_Msk        (0x1UL << HRTIM_RST1R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_RST1R_RESYNC            HRTIM_RST1R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_RST1R_PER_Pos           (2U)

+#define HRTIM_RST1R_PER_Msk           (0x1UL << HRTIM_RST1R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_RST1R_PER               HRTIM_RST1R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_RST1R_CMP1_Pos          (3U)

+#define HRTIM_RST1R_CMP1_Msk          (0x1UL << HRTIM_RST1R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_RST1R_CMP1              HRTIM_RST1R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_RST1R_CMP2_Pos          (4U)

+#define HRTIM_RST1R_CMP2_Msk          (0x1UL << HRTIM_RST1R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_RST1R_CMP2              HRTIM_RST1R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_RST1R_CMP3_Pos          (5U)

+#define HRTIM_RST1R_CMP3_Msk          (0x1UL << HRTIM_RST1R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_RST1R_CMP3              HRTIM_RST1R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_RST1R_CMP4_Pos          (6U)

+#define HRTIM_RST1R_CMP4_Msk          (0x1UL << HRTIM_RST1R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_RST1R_CMP4              HRTIM_RST1R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_RST1R_MSTPER_Pos        (7U)

+#define HRTIM_RST1R_MSTPER_Msk        (0x1UL << HRTIM_RST1R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_RST1R_MSTPER            HRTIM_RST1R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_RST1R_MSTCMP1_Pos       (8U)

+#define HRTIM_RST1R_MSTCMP1_Msk       (0x1UL << HRTIM_RST1R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_RST1R_MSTCMP1           HRTIM_RST1R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_RST1R_MSTCMP2_Pos       (9U)

+#define HRTIM_RST1R_MSTCMP2_Msk       (0x1UL << HRTIM_RST1R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_RST1R_MSTCMP2           HRTIM_RST1R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_RST1R_MSTCMP3_Pos       (10U)

+#define HRTIM_RST1R_MSTCMP3_Msk       (0x1UL << HRTIM_RST1R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_RST1R_MSTCMP3           HRTIM_RST1R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_RST1R_MSTCMP4_Pos       (11U)

+#define HRTIM_RST1R_MSTCMP4_Msk       (0x1UL << HRTIM_RST1R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_RST1R_MSTCMP4           HRTIM_RST1R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_RST1R_TIMEVNT1_Pos      (12U)

+#define HRTIM_RST1R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_RST1R_TIMEVNT1          HRTIM_RST1R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_RST1R_TIMEVNT2_Pos      (13U)

+#define HRTIM_RST1R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_RST1R_TIMEVNT2          HRTIM_RST1R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_RST1R_TIMEVNT3_Pos      (14U)

+#define HRTIM_RST1R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_RST1R_TIMEVNT3          HRTIM_RST1R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_RST1R_TIMEVNT4_Pos      (15U)

+#define HRTIM_RST1R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_RST1R_TIMEVNT4          HRTIM_RST1R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_RST1R_TIMEVNT5_Pos      (16U)

+#define HRTIM_RST1R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_RST1R_TIMEVNT5          HRTIM_RST1R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_RST1R_TIMEVNT6_Pos      (17U)

+#define HRTIM_RST1R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_RST1R_TIMEVNT6          HRTIM_RST1R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_RST1R_TIMEVNT7_Pos      (18U)

+#define HRTIM_RST1R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_RST1R_TIMEVNT7          HRTIM_RST1R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_RST1R_TIMEVNT8_Pos      (19U)

+#define HRTIM_RST1R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_RST1R_TIMEVNT8          HRTIM_RST1R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_RST1R_TIMEVNT9_Pos      (20U)

+#define HRTIM_RST1R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_RST1R_TIMEVNT9          HRTIM_RST1R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_RST1R_EXTVNT1_Pos       (21U)

+#define HRTIM_RST1R_EXTVNT1_Msk       (0x1UL << HRTIM_RST1R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_RST1R_EXTVNT1           HRTIM_RST1R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_RST1R_EXTVNT2_Pos       (22U)

+#define HRTIM_RST1R_EXTVNT2_Msk       (0x1UL << HRTIM_RST1R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_RST1R_EXTVNT2           HRTIM_RST1R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_RST1R_EXTVNT3_Pos       (23U)

+#define HRTIM_RST1R_EXTVNT3_Msk       (0x1UL << HRTIM_RST1R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_RST1R_EXTVNT3           HRTIM_RST1R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_RST1R_EXTVNT4_Pos       (24U)

+#define HRTIM_RST1R_EXTVNT4_Msk       (0x1UL << HRTIM_RST1R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_RST1R_EXTVNT4           HRTIM_RST1R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_RST1R_EXTVNT5_Pos       (25U)

+#define HRTIM_RST1R_EXTVNT5_Msk       (0x1UL << HRTIM_RST1R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_RST1R_EXTVNT5           HRTIM_RST1R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_RST1R_EXTVNT6_Pos       (26U)

+#define HRTIM_RST1R_EXTVNT6_Msk       (0x1UL << HRTIM_RST1R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_RST1R_EXTVNT6           HRTIM_RST1R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_RST1R_EXTVNT7_Pos       (27U)

+#define HRTIM_RST1R_EXTVNT7_Msk       (0x1UL << HRTIM_RST1R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_RST1R_EXTVNT7           HRTIM_RST1R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_RST1R_EXTVNT8_Pos       (28U)

+#define HRTIM_RST1R_EXTVNT8_Msk       (0x1UL << HRTIM_RST1R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_RST1R_EXTVNT8           HRTIM_RST1R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_RST1R_EXTVNT9_Pos       (29U)

+#define HRTIM_RST1R_EXTVNT9_Msk       (0x1UL << HRTIM_RST1R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_RST1R_EXTVNT9           HRTIM_RST1R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_RST1R_EXTVNT10_Pos      (30U)

+#define HRTIM_RST1R_EXTVNT10_Msk      (0x1UL << HRTIM_RST1R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_RST1R_EXTVNT10          HRTIM_RST1R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_RST1R_UPDATE_Pos        (31U)

+#define HRTIM_RST1R_UPDATE_Msk        (0x1UL << HRTIM_RST1R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_RST1R_UPDATE            HRTIM_RST1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+

+/**** Bit definition for Slave Output 2 set register **************************/

+#define HRTIM_SET2R_SST_Pos           (0U)

+#define HRTIM_SET2R_SST_Msk           (0x1UL << HRTIM_SET2R_SST_Pos)           /*!< 0x00000001 */

+#define HRTIM_SET2R_SST               HRTIM_SET2R_SST_Msk                      /*!< software set trigger */

+#define HRTIM_SET2R_RESYNC_Pos        (1U)

+#define HRTIM_SET2R_RESYNC_Msk        (0x1UL << HRTIM_SET2R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_SET2R_RESYNC            HRTIM_SET2R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_SET2R_PER_Pos           (2U)

+#define HRTIM_SET2R_PER_Msk           (0x1UL << HRTIM_SET2R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_SET2R_PER               HRTIM_SET2R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_SET2R_CMP1_Pos          (3U)

+#define HRTIM_SET2R_CMP1_Msk          (0x1UL << HRTIM_SET2R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_SET2R_CMP1              HRTIM_SET2R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_SET2R_CMP2_Pos          (4U)

+#define HRTIM_SET2R_CMP2_Msk          (0x1UL << HRTIM_SET2R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_SET2R_CMP2              HRTIM_SET2R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_SET2R_CMP3_Pos          (5U)

+#define HRTIM_SET2R_CMP3_Msk          (0x1UL << HRTIM_SET2R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_SET2R_CMP3              HRTIM_SET2R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_SET2R_CMP4_Pos          (6U)

+#define HRTIM_SET2R_CMP4_Msk          (0x1UL << HRTIM_SET2R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_SET2R_CMP4              HRTIM_SET2R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_SET2R_MSTPER_Pos        (7U)

+#define HRTIM_SET2R_MSTPER_Msk        (0x1UL << HRTIM_SET2R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_SET2R_MSTPER            HRTIM_SET2R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_SET2R_MSTCMP1_Pos       (8U)

+#define HRTIM_SET2R_MSTCMP1_Msk       (0x1UL << HRTIM_SET2R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_SET2R_MSTCMP1           HRTIM_SET2R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_SET2R_MSTCMP2_Pos       (9U)

+#define HRTIM_SET2R_MSTCMP2_Msk       (0x1UL << HRTIM_SET2R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_SET2R_MSTCMP2           HRTIM_SET2R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_SET2R_MSTCMP3_Pos       (10U)

+#define HRTIM_SET2R_MSTCMP3_Msk       (0x1UL << HRTIM_SET2R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_SET2R_MSTCMP3           HRTIM_SET2R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_SET2R_MSTCMP4_Pos       (11U)

+#define HRTIM_SET2R_MSTCMP4_Msk       (0x1UL << HRTIM_SET2R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_SET2R_MSTCMP4           HRTIM_SET2R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_SET2R_TIMEVNT1_Pos      (12U)

+#define HRTIM_SET2R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_SET2R_TIMEVNT1          HRTIM_SET2R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_SET2R_TIMEVNT2_Pos      (13U)

+#define HRTIM_SET2R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_SET2R_TIMEVNT2          HRTIM_SET2R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_SET2R_TIMEVNT3_Pos      (14U)

+#define HRTIM_SET2R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_SET2R_TIMEVNT3          HRTIM_SET2R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_SET2R_TIMEVNT4_Pos      (15U)

+#define HRTIM_SET2R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_SET2R_TIMEVNT4          HRTIM_SET2R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_SET2R_TIMEVNT5_Pos      (16U)

+#define HRTIM_SET2R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_SET2R_TIMEVNT5          HRTIM_SET2R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_SET2R_TIMEVNT6_Pos      (17U)

+#define HRTIM_SET2R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_SET2R_TIMEVNT6          HRTIM_SET2R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_SET2R_TIMEVNT7_Pos      (18U)

+#define HRTIM_SET2R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_SET2R_TIMEVNT7          HRTIM_SET2R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_SET2R_TIMEVNT8_Pos      (19U)

+#define HRTIM_SET2R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_SET2R_TIMEVNT8          HRTIM_SET2R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_SET2R_TIMEVNT9_Pos      (20U)

+#define HRTIM_SET2R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_SET2R_TIMEVNT9          HRTIM_SET2R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_SET2R_EXTVNT1_Pos       (21U)

+#define HRTIM_SET2R_EXTVNT1_Msk       (0x1UL << HRTIM_SET2R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_SET2R_EXTVNT1           HRTIM_SET2R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_SET2R_EXTVNT2_Pos       (22U)

+#define HRTIM_SET2R_EXTVNT2_Msk       (0x1UL << HRTIM_SET2R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_SET2R_EXTVNT2           HRTIM_SET2R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_SET2R_EXTVNT3_Pos       (23U)

+#define HRTIM_SET2R_EXTVNT3_Msk       (0x1UL << HRTIM_SET2R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_SET2R_EXTVNT3           HRTIM_SET2R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_SET2R_EXTVNT4_Pos       (24U)

+#define HRTIM_SET2R_EXTVNT4_Msk       (0x1UL << HRTIM_SET2R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_SET2R_EXTVNT4           HRTIM_SET2R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_SET2R_EXTVNT5_Pos       (25U)

+#define HRTIM_SET2R_EXTVNT5_Msk       (0x1UL << HRTIM_SET2R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_SET2R_EXTVNT5           HRTIM_SET2R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_SET2R_EXTVNT6_Pos       (26U)

+#define HRTIM_SET2R_EXTVNT6_Msk       (0x1UL << HRTIM_SET2R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_SET2R_EXTVNT6           HRTIM_SET2R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_SET2R_EXTVNT7_Pos       (27U)

+#define HRTIM_SET2R_EXTVNT7_Msk       (0x1UL << HRTIM_SET2R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_SET2R_EXTVNT7           HRTIM_SET2R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_SET2R_EXTVNT8_Pos       (28U)

+#define HRTIM_SET2R_EXTVNT8_Msk       (0x1UL << HRTIM_SET2R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_SET2R_EXTVNT8           HRTIM_SET2R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_SET2R_EXTVNT9_Pos       (29U)

+#define HRTIM_SET2R_EXTVNT9_Msk       (0x1UL << HRTIM_SET2R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_SET2R_EXTVNT9           HRTIM_SET2R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_SET2R_EXTVNT10_Pos      (30U)

+#define HRTIM_SET2R_EXTVNT10_Msk      (0x1UL << HRTIM_SET2R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_SET2R_EXTVNT10          HRTIM_SET2R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_SET2R_UPDATE_Pos        (31U)

+#define HRTIM_SET2R_UPDATE_Msk        (0x1UL << HRTIM_SET2R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_SET2R_UPDATE            HRTIM_SET2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+/**** Bit definition for Slave Output 2 reset register ************************/

+#define HRTIM_RST2R_SRT_Pos           (0U)

+#define HRTIM_RST2R_SRT_Msk           (0x1UL << HRTIM_RST2R_SRT_Pos)           /*!< 0x00000001 */

+#define HRTIM_RST2R_SRT               HRTIM_RST2R_SRT_Msk                      /*!< software reset trigger */

+#define HRTIM_RST2R_RESYNC_Pos        (1U)

+#define HRTIM_RST2R_RESYNC_Msk        (0x1UL << HRTIM_RST2R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_RST2R_RESYNC            HRTIM_RST2R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_RST2R_PER_Pos           (2U)

+#define HRTIM_RST2R_PER_Msk           (0x1UL << HRTIM_RST2R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_RST2R_PER               HRTIM_RST2R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_RST2R_CMP1_Pos          (3U)

+#define HRTIM_RST2R_CMP1_Msk          (0x1UL << HRTIM_RST2R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_RST2R_CMP1              HRTIM_RST2R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_RST2R_CMP2_Pos          (4U)

+#define HRTIM_RST2R_CMP2_Msk          (0x1UL << HRTIM_RST2R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_RST2R_CMP2              HRTIM_RST2R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_RST2R_CMP3_Pos          (5U)

+#define HRTIM_RST2R_CMP3_Msk          (0x1UL << HRTIM_RST2R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_RST2R_CMP3              HRTIM_RST2R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_RST2R_CMP4_Pos          (6U)

+#define HRTIM_RST2R_CMP4_Msk          (0x1UL << HRTIM_RST2R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_RST2R_CMP4              HRTIM_RST2R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_RST2R_MSTPER_Pos        (7U)

+#define HRTIM_RST2R_MSTPER_Msk        (0x1UL << HRTIM_RST2R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_RST2R_MSTPER            HRTIM_RST2R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_RST2R_MSTCMP1_Pos       (8U)

+#define HRTIM_RST2R_MSTCMP1_Msk       (0x1UL << HRTIM_RST2R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_RST2R_MSTCMP1           HRTIM_RST2R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_RST2R_MSTCMP2_Pos       (9U)

+#define HRTIM_RST2R_MSTCMP2_Msk       (0x1UL << HRTIM_RST2R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_RST2R_MSTCMP2           HRTIM_RST2R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_RST2R_MSTCMP3_Pos       (10U)

+#define HRTIM_RST2R_MSTCMP3_Msk       (0x1UL << HRTIM_RST2R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_RST2R_MSTCMP3           HRTIM_RST2R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_RST2R_MSTCMP4_Pos       (11U)

+#define HRTIM_RST2R_MSTCMP4_Msk       (0x1UL << HRTIM_RST2R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_RST2R_MSTCMP4           HRTIM_RST2R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_RST2R_TIMEVNT1_Pos      (12U)

+#define HRTIM_RST2R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_RST2R_TIMEVNT1          HRTIM_RST2R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_RST2R_TIMEVNT2_Pos      (13U)

+#define HRTIM_RST2R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_RST2R_TIMEVNT2          HRTIM_RST2R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_RST2R_TIMEVNT3_Pos      (14U)

+#define HRTIM_RST2R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_RST2R_TIMEVNT3          HRTIM_RST2R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_RST2R_TIMEVNT4_Pos      (15U)

+#define HRTIM_RST2R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_RST2R_TIMEVNT4          HRTIM_RST2R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_RST2R_TIMEVNT5_Pos      (16U)

+#define HRTIM_RST2R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_RST2R_TIMEVNT5          HRTIM_RST2R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_RST2R_TIMEVNT6_Pos      (17U)

+#define HRTIM_RST2R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_RST2R_TIMEVNT6          HRTIM_RST2R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_RST2R_TIMEVNT7_Pos      (18U)

+#define HRTIM_RST2R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_RST2R_TIMEVNT7          HRTIM_RST2R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_RST2R_TIMEVNT8_Pos      (19U)

+#define HRTIM_RST2R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_RST2R_TIMEVNT8          HRTIM_RST2R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_RST2R_TIMEVNT9_Pos      (20U)

+#define HRTIM_RST2R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_RST2R_TIMEVNT9          HRTIM_RST2R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_RST2R_EXTVNT1_Pos       (21U)

+#define HRTIM_RST2R_EXTVNT1_Msk       (0x1UL << HRTIM_RST2R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_RST2R_EXTVNT1           HRTIM_RST2R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_RST2R_EXTVNT2_Pos       (22U)

+#define HRTIM_RST2R_EXTVNT2_Msk       (0x1UL << HRTIM_RST2R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_RST2R_EXTVNT2           HRTIM_RST2R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_RST2R_EXTVNT3_Pos       (23U)

+#define HRTIM_RST2R_EXTVNT3_Msk       (0x1UL << HRTIM_RST2R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_RST2R_EXTVNT3           HRTIM_RST2R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_RST2R_EXTVNT4_Pos       (24U)

+#define HRTIM_RST2R_EXTVNT4_Msk       (0x1UL << HRTIM_RST2R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_RST2R_EXTVNT4           HRTIM_RST2R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_RST2R_EXTVNT5_Pos       (25U)

+#define HRTIM_RST2R_EXTVNT5_Msk       (0x1UL << HRTIM_RST2R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_RST2R_EXTVNT5           HRTIM_RST2R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_RST2R_EXTVNT6_Pos       (26U)

+#define HRTIM_RST2R_EXTVNT6_Msk       (0x1UL << HRTIM_RST2R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_RST2R_EXTVNT6           HRTIM_RST2R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_RST2R_EXTVNT7_Pos       (27U)

+#define HRTIM_RST2R_EXTVNT7_Msk       (0x1UL << HRTIM_RST2R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_RST2R_EXTVNT7           HRTIM_RST2R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_RST2R_EXTVNT8_Pos       (28U)

+#define HRTIM_RST2R_EXTVNT8_Msk       (0x1UL << HRTIM_RST2R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_RST2R_EXTVNT8           HRTIM_RST2R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_RST2R_EXTVNT9_Pos       (29U)

+#define HRTIM_RST2R_EXTVNT9_Msk       (0x1UL << HRTIM_RST2R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_RST2R_EXTVNT9           HRTIM_RST2R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_RST2R_EXTVNT10_Pos      (30U)

+#define HRTIM_RST2R_EXTVNT10_Msk      (0x1UL << HRTIM_RST2R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_RST2R_EXTVNT10          HRTIM_RST2R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_RST2R_UPDATE_Pos        (31U)

+#define HRTIM_RST2R_UPDATE_Msk        (0x1UL << HRTIM_RST2R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_RST2R_UPDATE            HRTIM_RST2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+/**** Bit definition for Slave external event filtering  register 1 ***********/

+#define HRTIM_EEFR1_EE1LTCH_Pos       (0U)

+#define HRTIM_EEFR1_EE1LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos)       /*!< 0x00000001 */

+#define HRTIM_EEFR1_EE1LTCH           HRTIM_EEFR1_EE1LTCH_Msk                  /*!< External Event 1 latch */

+#define HRTIM_EEFR1_EE1FLTR_Pos       (1U)

+#define HRTIM_EEFR1_EE1FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos)       /*!< 0x0000001E */

+#define HRTIM_EEFR1_EE1FLTR           HRTIM_EEFR1_EE1FLTR_Msk                  /*!< External Event 1 filter mask */

+#define HRTIM_EEFR1_EE1FLTR_0         (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000002 */

+#define HRTIM_EEFR1_EE1FLTR_1         (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000004 */

+#define HRTIM_EEFR1_EE1FLTR_2         (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000008 */

+#define HRTIM_EEFR1_EE1FLTR_3         (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000010 */

+

+#define HRTIM_EEFR1_EE2LTCH_Pos       (6U)

+#define HRTIM_EEFR1_EE2LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos)       /*!< 0x00000040 */

+#define HRTIM_EEFR1_EE2LTCH           HRTIM_EEFR1_EE2LTCH_Msk                  /*!< External Event 2 latch */

+#define HRTIM_EEFR1_EE2FLTR_Pos       (7U)

+#define HRTIM_EEFR1_EE2FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos)       /*!< 0x00000780 */

+#define HRTIM_EEFR1_EE2FLTR           HRTIM_EEFR1_EE2FLTR_Msk                  /*!< External Event 2 filter mask */

+#define HRTIM_EEFR1_EE2FLTR_0         (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000080 */

+#define HRTIM_EEFR1_EE2FLTR_1         (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000100 */

+#define HRTIM_EEFR1_EE2FLTR_2         (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000200 */

+#define HRTIM_EEFR1_EE2FLTR_3         (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000400 */

+

+#define HRTIM_EEFR1_EE3LTCH_Pos       (12U)

+#define HRTIM_EEFR1_EE3LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos)       /*!< 0x00001000 */

+#define HRTIM_EEFR1_EE3LTCH           HRTIM_EEFR1_EE3LTCH_Msk                  /*!< External Event 3 latch */

+#define HRTIM_EEFR1_EE3FLTR_Pos       (13U)

+#define HRTIM_EEFR1_EE3FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos)       /*!< 0x0001E000 */

+#define HRTIM_EEFR1_EE3FLTR           HRTIM_EEFR1_EE3FLTR_Msk                  /*!< External Event 3 filter mask */

+#define HRTIM_EEFR1_EE3FLTR_0         (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00002000 */

+#define HRTIM_EEFR1_EE3FLTR_1         (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00004000 */

+#define HRTIM_EEFR1_EE3FLTR_2         (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00008000 */

+#define HRTIM_EEFR1_EE3FLTR_3         (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00010000 */

+

+#define HRTIM_EEFR1_EE4LTCH_Pos       (18U)

+#define HRTIM_EEFR1_EE4LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos)       /*!< 0x00040000 */

+#define HRTIM_EEFR1_EE4LTCH           HRTIM_EEFR1_EE4LTCH_Msk                  /*!< External Event 4 latch */

+#define HRTIM_EEFR1_EE4FLTR_Pos       (19U)

+#define HRTIM_EEFR1_EE4FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos)       /*!< 0x00780000 */

+#define HRTIM_EEFR1_EE4FLTR           HRTIM_EEFR1_EE4FLTR_Msk                  /*!< External Event 4 filter mask */

+#define HRTIM_EEFR1_EE4FLTR_0         (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00080000 */

+#define HRTIM_EEFR1_EE4FLTR_1         (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00100000 */

+#define HRTIM_EEFR1_EE4FLTR_2         (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00200000 */

+#define HRTIM_EEFR1_EE4FLTR_3         (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00400000 */

+

+#define HRTIM_EEFR1_EE5LTCH_Pos       (24U)

+#define HRTIM_EEFR1_EE5LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos)       /*!< 0x01000000 */

+#define HRTIM_EEFR1_EE5LTCH           HRTIM_EEFR1_EE5LTCH_Msk                  /*!< External Event 5 latch */

+#define HRTIM_EEFR1_EE5FLTR_Pos       (25U)

+#define HRTIM_EEFR1_EE5FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos)       /*!< 0x1E000000 */

+#define HRTIM_EEFR1_EE5FLTR           HRTIM_EEFR1_EE5FLTR_Msk                  /*!< External Event 5 filter mask */

+#define HRTIM_EEFR1_EE5FLTR_0         (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x02000000 */

+#define HRTIM_EEFR1_EE5FLTR_1         (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x04000000 */

+#define HRTIM_EEFR1_EE5FLTR_2         (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x08000000 */

+#define HRTIM_EEFR1_EE5FLTR_3         (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x10000000 */

+

+/**** Bit definition for Slave external event filtering  register 2 ***********/

+#define HRTIM_EEFR2_EE6LTCH_Pos       (0U)

+#define HRTIM_EEFR2_EE6LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos)       /*!< 0x00000001 */

+#define HRTIM_EEFR2_EE6LTCH           HRTIM_EEFR2_EE6LTCH_Msk                  /*!< External Event 6 latch */

+#define HRTIM_EEFR2_EE6FLTR_Pos       (1U)

+#define HRTIM_EEFR2_EE6FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos)       /*!< 0x0000001E */

+#define HRTIM_EEFR2_EE6FLTR           HRTIM_EEFR2_EE6FLTR_Msk                  /*!< External Event 6 filter mask */

+#define HRTIM_EEFR2_EE6FLTR_0         (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000002 */

+#define HRTIM_EEFR2_EE6FLTR_1         (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000004 */

+#define HRTIM_EEFR2_EE6FLTR_2         (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000008 */

+#define HRTIM_EEFR2_EE6FLTR_3         (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000010 */

+

+#define HRTIM_EEFR2_EE7LTCH_Pos       (6U)

+#define HRTIM_EEFR2_EE7LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos)       /*!< 0x00000040 */

+#define HRTIM_EEFR2_EE7LTCH           HRTIM_EEFR2_EE7LTCH_Msk                  /*!< External Event 7 latch */

+#define HRTIM_EEFR2_EE7FLTR_Pos       (7U)

+#define HRTIM_EEFR2_EE7FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos)       /*!< 0x00000780 */

+#define HRTIM_EEFR2_EE7FLTR           HRTIM_EEFR2_EE7FLTR_Msk                  /*!< External Event 7 filter mask */

+#define HRTIM_EEFR2_EE7FLTR_0         (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000080 */

+#define HRTIM_EEFR2_EE7FLTR_1         (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000100 */

+#define HRTIM_EEFR2_EE7FLTR_2         (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000200 */

+#define HRTIM_EEFR2_EE7FLTR_3         (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000400 */

+

+#define HRTIM_EEFR2_EE8LTCH_Pos       (12U)

+#define HRTIM_EEFR2_EE8LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos)       /*!< 0x00001000 */

+#define HRTIM_EEFR2_EE8LTCH           HRTIM_EEFR2_EE8LTCH_Msk                  /*!< External Event 8 latch */

+#define HRTIM_EEFR2_EE8FLTR_Pos       (13U)

+#define HRTIM_EEFR2_EE8FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos)       /*!< 0x0001E000 */

+#define HRTIM_EEFR2_EE8FLTR           HRTIM_EEFR2_EE8FLTR_Msk                  /*!< External Event 8 filter mask */

+#define HRTIM_EEFR2_EE8FLTR_0         (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00002000 */

+#define HRTIM_EEFR2_EE8FLTR_1         (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00004000 */

+#define HRTIM_EEFR2_EE8FLTR_2         (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00008000 */

+#define HRTIM_EEFR2_EE8FLTR_3         (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00010000 */

+

+#define HRTIM_EEFR2_EE9LTCH_Pos       (18U)

+#define HRTIM_EEFR2_EE9LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos)       /*!< 0x00040000 */

+#define HRTIM_EEFR2_EE9LTCH           HRTIM_EEFR2_EE9LTCH_Msk                  /*!< External Event 9 latch */

+#define HRTIM_EEFR2_EE9FLTR_Pos       (19U)

+#define HRTIM_EEFR2_EE9FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos)       /*!< 0x00780000 */

+#define HRTIM_EEFR2_EE9FLTR           HRTIM_EEFR2_EE9FLTR_Msk                  /*!< External Event 9 filter mask */

+#define HRTIM_EEFR2_EE9FLTR_0         (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00080000 */

+#define HRTIM_EEFR2_EE9FLTR_1         (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00100000 */

+#define HRTIM_EEFR2_EE9FLTR_2         (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00200000 */

+#define HRTIM_EEFR2_EE9FLTR_3         (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00400000 */

+

+#define HRTIM_EEFR2_EE10LTCH_Pos      (24U)

+#define HRTIM_EEFR2_EE10LTCH_Msk      (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos)      /*!< 0x01000000 */

+#define HRTIM_EEFR2_EE10LTCH          HRTIM_EEFR2_EE10LTCH_Msk                 /*!< External Event 10 latch */

+#define HRTIM_EEFR2_EE10FLTR_Pos      (25U)

+#define HRTIM_EEFR2_EE10FLTR_Msk      (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos)      /*!< 0x1E000000 */

+#define HRTIM_EEFR2_EE10FLTR          HRTIM_EEFR2_EE10FLTR_Msk                 /*!< External Event 10 filter mask */

+#define HRTIM_EEFR2_EE10FLTR_0        (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x02000000 */

+#define HRTIM_EEFR2_EE10FLTR_1        (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x04000000 */

+#define HRTIM_EEFR2_EE10FLTR_2        (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x08000000 */

+#define HRTIM_EEFR2_EE10FLTR_3        (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x10000000 */

+

+/**** Bit definition for Slave Timer reset register ***************************/

+#define HRTIM_RSTR_UPDATE_Pos         (1U)

+#define HRTIM_RSTR_UPDATE_Msk         (0x1UL << HRTIM_RSTR_UPDATE_Pos)         /*!< 0x00000002 */

+#define HRTIM_RSTR_UPDATE             HRTIM_RSTR_UPDATE_Msk                    /*!< Timer update */

+#define HRTIM_RSTR_CMP2_Pos           (2U)

+#define HRTIM_RSTR_CMP2_Msk           (0x1UL << HRTIM_RSTR_CMP2_Pos)           /*!< 0x00000004 */

+#define HRTIM_RSTR_CMP2               HRTIM_RSTR_CMP2_Msk                      /*!< Timer compare2 */

+#define HRTIM_RSTR_CMP4_Pos           (3U)

+#define HRTIM_RSTR_CMP4_Msk           (0x1UL << HRTIM_RSTR_CMP4_Pos)           /*!< 0x00000008 */

+#define HRTIM_RSTR_CMP4               HRTIM_RSTR_CMP4_Msk                      /*!< Timer compare4 */

+

+#define HRTIM_RSTR_MSTPER_Pos         (4U)

+#define HRTIM_RSTR_MSTPER_Msk         (0x1UL << HRTIM_RSTR_MSTPER_Pos)         /*!< 0x00000010 */

+#define HRTIM_RSTR_MSTPER             HRTIM_RSTR_MSTPER_Msk                    /*!< Master period */

+#define HRTIM_RSTR_MSTCMP1_Pos        (5U)

+#define HRTIM_RSTR_MSTCMP1_Msk        (0x1UL << HRTIM_RSTR_MSTCMP1_Pos)        /*!< 0x00000020 */

+#define HRTIM_RSTR_MSTCMP1            HRTIM_RSTR_MSTCMP1_Msk                   /*!< Master compare1 */

+#define HRTIM_RSTR_MSTCMP2_Pos        (6U)

+#define HRTIM_RSTR_MSTCMP2_Msk        (0x1UL << HRTIM_RSTR_MSTCMP2_Pos)        /*!< 0x00000040 */

+#define HRTIM_RSTR_MSTCMP2            HRTIM_RSTR_MSTCMP2_Msk                   /*!< Master compare2 */

+#define HRTIM_RSTR_MSTCMP3_Pos        (7U)

+#define HRTIM_RSTR_MSTCMP3_Msk        (0x1UL << HRTIM_RSTR_MSTCMP3_Pos)        /*!< 0x00000080 */

+#define HRTIM_RSTR_MSTCMP3            HRTIM_RSTR_MSTCMP3_Msk                   /*!< Master compare3 */

+#define HRTIM_RSTR_MSTCMP4_Pos        (8U)

+#define HRTIM_RSTR_MSTCMP4_Msk        (0x1UL << HRTIM_RSTR_MSTCMP4_Pos)        /*!< 0x00000100 */

+#define HRTIM_RSTR_MSTCMP4            HRTIM_RSTR_MSTCMP4_Msk                   /*!< Master compare4 */

+

+#define HRTIM_RSTR_EXTEVNT1_Pos       (9U)

+#define HRTIM_RSTR_EXTEVNT1_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos)       /*!< 0x00000200 */

+#define HRTIM_RSTR_EXTEVNT1           HRTIM_RSTR_EXTEVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_RSTR_EXTEVNT2_Pos       (10U)

+#define HRTIM_RSTR_EXTEVNT2_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos)       /*!< 0x00000400 */

+#define HRTIM_RSTR_EXTEVNT2           HRTIM_RSTR_EXTEVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_RSTR_EXTEVNT3_Pos       (11U)

+#define HRTIM_RSTR_EXTEVNT3_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos)       /*!< 0x00000800 */

+#define HRTIM_RSTR_EXTEVNT3           HRTIM_RSTR_EXTEVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_RSTR_EXTEVNT4_Pos       (12U)

+#define HRTIM_RSTR_EXTEVNT4_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos)       /*!< 0x00001000 */

+#define HRTIM_RSTR_EXTEVNT4           HRTIM_RSTR_EXTEVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_RSTR_EXTEVNT5_Pos       (13U)

+#define HRTIM_RSTR_EXTEVNT5_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos)       /*!< 0x00002000 */

+#define HRTIM_RSTR_EXTEVNT5           HRTIM_RSTR_EXTEVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_RSTR_EXTEVNT6_Pos       (14U)

+#define HRTIM_RSTR_EXTEVNT6_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos)       /*!< 0x00004000 */

+#define HRTIM_RSTR_EXTEVNT6           HRTIM_RSTR_EXTEVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_RSTR_EXTEVNT7_Pos       (15U)

+#define HRTIM_RSTR_EXTEVNT7_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos)       /*!< 0x00008000 */

+#define HRTIM_RSTR_EXTEVNT7           HRTIM_RSTR_EXTEVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_RSTR_EXTEVNT8_Pos       (16U)

+#define HRTIM_RSTR_EXTEVNT8_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos)       /*!< 0x00010000 */

+#define HRTIM_RSTR_EXTEVNT8           HRTIM_RSTR_EXTEVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_RSTR_EXTEVNT9_Pos       (17U)

+#define HRTIM_RSTR_EXTEVNT9_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos)       /*!< 0x00020000 */

+#define HRTIM_RSTR_EXTEVNT9           HRTIM_RSTR_EXTEVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_RSTR_EXTEVNT10_Pos      (18U)

+#define HRTIM_RSTR_EXTEVNT10_Msk      (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos)      /*!< 0x00040000 */

+#define HRTIM_RSTR_EXTEVNT10          HRTIM_RSTR_EXTEVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_RSTR_TIMBCMP1_Pos       (19U)

+#define HRTIM_RSTR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos)       /*!< 0x00080000 */

+#define HRTIM_RSTR_TIMBCMP1           HRTIM_RSTR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */

+#define HRTIM_RSTR_TIMBCMP2_Pos       (20U)

+#define HRTIM_RSTR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos)       /*!< 0x00100000 */

+#define HRTIM_RSTR_TIMBCMP2           HRTIM_RSTR_TIMBCMP2_Msk                  /*!< Timer B compare 2 */

+#define HRTIM_RSTR_TIMBCMP4_Pos       (21U)

+#define HRTIM_RSTR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos)       /*!< 0x00200000 */

+#define HRTIM_RSTR_TIMBCMP4           HRTIM_RSTR_TIMBCMP4_Msk                  /*!< Timer B compare 4 */

+

+#define HRTIM_RSTR_TIMCCMP1_Pos       (22U)

+#define HRTIM_RSTR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos)       /*!< 0x00400000 */

+#define HRTIM_RSTR_TIMCCMP1           HRTIM_RSTR_TIMCCMP1_Msk                  /*!< Timer C compare 1 */

+#define HRTIM_RSTR_TIMCCMP2_Pos       (23U)

+#define HRTIM_RSTR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos)       /*!< 0x00800000 */

+#define HRTIM_RSTR_TIMCCMP2           HRTIM_RSTR_TIMCCMP2_Msk                  /*!< Timer C compare 2 */

+#define HRTIM_RSTR_TIMCCMP4_Pos       (24U)

+#define HRTIM_RSTR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos)       /*!< 0x01000000 */

+#define HRTIM_RSTR_TIMCCMP4           HRTIM_RSTR_TIMCCMP4_Msk                  /*!< Timer C compare 4 */

+

+#define HRTIM_RSTR_TIMDCMP1_Pos       (25U)

+#define HRTIM_RSTR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos)       /*!< 0x02000000 */

+#define HRTIM_RSTR_TIMDCMP1           HRTIM_RSTR_TIMDCMP1_Msk                  /*!< Timer D compare 1 */

+#define HRTIM_RSTR_TIMDCMP2_Pos       (26U)

+#define HRTIM_RSTR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos)       /*!< 0x04000000 */

+#define HRTIM_RSTR_TIMDCMP2           HRTIM_RSTR_TIMDCMP2_Msk                  /*!< Timer D compare 2 */

+#define HRTIM_RSTR_TIMDCMP4_Pos       (27U)

+#define HRTIM_RSTR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos)       /*!< 0x08000000 */

+#define HRTIM_RSTR_TIMDCMP4           HRTIM_RSTR_TIMDCMP4_Msk                  /*!< Timer D compare 4 */

+

+#define HRTIM_RSTR_TIMECMP1_Pos       (28U)

+#define HRTIM_RSTR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTR_TIMECMP1_Pos)       /*!< 0x10000000 */

+#define HRTIM_RSTR_TIMECMP1           HRTIM_RSTR_TIMECMP1_Msk                  /*!< Timer E compare 1 */

+#define HRTIM_RSTR_TIMECMP2_Pos       (29U)

+#define HRTIM_RSTR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTR_TIMECMP2_Pos)       /*!< 0x20000000 */

+#define HRTIM_RSTR_TIMECMP2           HRTIM_RSTR_TIMECMP2_Msk                  /*!< Timer E compare 2 */

+#define HRTIM_RSTR_TIMECMP4_Pos       (30U)

+#define HRTIM_RSTR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTR_TIMECMP4_Pos)       /*!< 0x40000000 */

+#define HRTIM_RSTR_TIMECMP4           HRTIM_RSTR_TIMECMP4_Msk                  /*!< Timer E compare 4 */

+

+/**** Bit definition for Slave Timer Chopper register *************************/

+#define HRTIM_CHPR_CARFRQ_Pos         (0U)

+#define HRTIM_CHPR_CARFRQ_Msk         (0xFUL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x0000000F */

+#define HRTIM_CHPR_CARFRQ             HRTIM_CHPR_CARFRQ_Msk                    /*!< Timer carrier frequency value */

+#define HRTIM_CHPR_CARFRQ_0           (0x1UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000001 */

+#define HRTIM_CHPR_CARFRQ_1           (0x2UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000002 */

+#define HRTIM_CHPR_CARFRQ_2           (0x4UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000004 */

+#define HRTIM_CHPR_CARFRQ_3           (0x8UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000008 */

+

+#define HRTIM_CHPR_CARDTY_Pos         (4U)

+#define HRTIM_CHPR_CARDTY_Msk         (0x7UL << HRTIM_CHPR_CARDTY_Pos)         /*!< 0x00000070 */

+#define HRTIM_CHPR_CARDTY             HRTIM_CHPR_CARDTY_Msk                    /*!< Timer chopper duty cycle value */

+#define HRTIM_CHPR_CARDTY_0           (0x1UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000010 */

+#define HRTIM_CHPR_CARDTY_1           (0x2UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000020 */

+#define HRTIM_CHPR_CARDTY_2           (0x4UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000040 */

+

+#define HRTIM_CHPR_STRPW_Pos          (7U)

+#define HRTIM_CHPR_STRPW_Msk          (0xFUL << HRTIM_CHPR_STRPW_Pos)          /*!< 0x00000780 */

+#define HRTIM_CHPR_STRPW              HRTIM_CHPR_STRPW_Msk                     /*!< Timer start pulse width value */

+#define HRTIM_CHPR_STRPW_0            (0x1UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000080 */

+#define HRTIM_CHPR_STRPW_1            (0x2UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000100 */

+#define HRTIM_CHPR_STRPW_2            (0x4UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000200 */

+#define HRTIM_CHPR_STRPW_3            (0x8UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000400 */

+

+/**** Bit definition for Slave Timer Capture 1 control register ***************/

+#define HRTIM_CPT1CR_SWCPT_Pos        (0U)

+#define HRTIM_CPT1CR_SWCPT_Msk        (0x1UL << HRTIM_CPT1CR_SWCPT_Pos)        /*!< 0x00000001 */

+#define HRTIM_CPT1CR_SWCPT            HRTIM_CPT1CR_SWCPT_Msk                   /*!< Software capture */

+#define HRTIM_CPT1CR_UPDCPT_Pos       (1U)

+#define HRTIM_CPT1CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos)       /*!< 0x00000002 */

+#define HRTIM_CPT1CR_UPDCPT           HRTIM_CPT1CR_UPDCPT_Msk                  /*!< Update capture */

+#define HRTIM_CPT1CR_EXEV1CPT_Pos     (2U)

+#define HRTIM_CPT1CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos)     /*!< 0x00000004 */

+#define HRTIM_CPT1CR_EXEV1CPT         HRTIM_CPT1CR_EXEV1CPT_Msk                /*!< External event 1 capture */

+#define HRTIM_CPT1CR_EXEV2CPT_Pos     (3U)

+#define HRTIM_CPT1CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos)     /*!< 0x00000008 */

+#define HRTIM_CPT1CR_EXEV2CPT         HRTIM_CPT1CR_EXEV2CPT_Msk                /*!< External event 2 capture */

+#define HRTIM_CPT1CR_EXEV3CPT_Pos     (4U)

+#define HRTIM_CPT1CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos)     /*!< 0x00000010 */

+#define HRTIM_CPT1CR_EXEV3CPT         HRTIM_CPT1CR_EXEV3CPT_Msk                /*!< External event 3 capture */

+#define HRTIM_CPT1CR_EXEV4CPT_Pos     (5U)

+#define HRTIM_CPT1CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos)     /*!< 0x00000020 */

+#define HRTIM_CPT1CR_EXEV4CPT         HRTIM_CPT1CR_EXEV4CPT_Msk                /*!< External event 4 capture */

+#define HRTIM_CPT1CR_EXEV5CPT_Pos     (6U)

+#define HRTIM_CPT1CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos)     /*!< 0x00000040 */

+#define HRTIM_CPT1CR_EXEV5CPT         HRTIM_CPT1CR_EXEV5CPT_Msk                /*!< External event 5 capture */

+#define HRTIM_CPT1CR_EXEV6CPT_Pos     (7U)

+#define HRTIM_CPT1CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos)     /*!< 0x00000080 */

+#define HRTIM_CPT1CR_EXEV6CPT         HRTIM_CPT1CR_EXEV6CPT_Msk                /*!< External event 6 capture */

+#define HRTIM_CPT1CR_EXEV7CPT_Pos     (8U)

+#define HRTIM_CPT1CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos)     /*!< 0x00000100 */

+#define HRTIM_CPT1CR_EXEV7CPT         HRTIM_CPT1CR_EXEV7CPT_Msk                /*!< External event 7 capture */

+#define HRTIM_CPT1CR_EXEV8CPT_Pos     (9U)

+#define HRTIM_CPT1CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos)     /*!< 0x00000200 */

+#define HRTIM_CPT1CR_EXEV8CPT         HRTIM_CPT1CR_EXEV8CPT_Msk                /*!< External event 8 capture */

+#define HRTIM_CPT1CR_EXEV9CPT_Pos     (10U)

+#define HRTIM_CPT1CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos)     /*!< 0x00000400 */

+#define HRTIM_CPT1CR_EXEV9CPT         HRTIM_CPT1CR_EXEV9CPT_Msk                /*!< External event 9 capture */

+#define HRTIM_CPT1CR_EXEV10CPT_Pos    (11U)

+#define HRTIM_CPT1CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos)    /*!< 0x00000800 */

+#define HRTIM_CPT1CR_EXEV10CPT        HRTIM_CPT1CR_EXEV10CPT_Msk               /*!< External event 10 capture */

+

+#define HRTIM_CPT1CR_TA1SET_Pos       (12U)

+#define HRTIM_CPT1CR_TA1SET_Msk       (0x1UL << HRTIM_CPT1CR_TA1SET_Pos)       /*!< 0x00001000 */

+#define HRTIM_CPT1CR_TA1SET           HRTIM_CPT1CR_TA1SET_Msk                  /*!< Timer A output 1 set */

+#define HRTIM_CPT1CR_TA1RST_Pos       (13U)

+#define HRTIM_CPT1CR_TA1RST_Msk       (0x1UL << HRTIM_CPT1CR_TA1RST_Pos)       /*!< 0x00002000 */

+#define HRTIM_CPT1CR_TA1RST           HRTIM_CPT1CR_TA1RST_Msk                  /*!< Timer A output 1 reset */

+#define HRTIM_CPT1CR_TIMACMP1_Pos     (14U)

+#define HRTIM_CPT1CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos)     /*!< 0x00004000 */

+#define HRTIM_CPT1CR_TIMACMP1         HRTIM_CPT1CR_TIMACMP1_Msk                /*!< Timer A compare 1 */

+#define HRTIM_CPT1CR_TIMACMP2_Pos     (15U)

+#define HRTIM_CPT1CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos)     /*!< 0x00008000 */

+#define HRTIM_CPT1CR_TIMACMP2         HRTIM_CPT1CR_TIMACMP2_Msk                /*!< Timer A compare 2 */

+

+#define HRTIM_CPT1CR_TB1SET_Pos       (16U)

+#define HRTIM_CPT1CR_TB1SET_Msk       (0x1UL << HRTIM_CPT1CR_TB1SET_Pos)       /*!< 0x00010000 */

+#define HRTIM_CPT1CR_TB1SET           HRTIM_CPT1CR_TB1SET_Msk                  /*!< Timer B output 1 set */

+#define HRTIM_CPT1CR_TB1RST_Pos       (17U)

+#define HRTIM_CPT1CR_TB1RST_Msk       (0x1UL << HRTIM_CPT1CR_TB1RST_Pos)       /*!< 0x00020000 */

+#define HRTIM_CPT1CR_TB1RST           HRTIM_CPT1CR_TB1RST_Msk                  /*!< Timer B output 1 reset */

+#define HRTIM_CPT1CR_TIMBCMP1_Pos     (18U)

+#define HRTIM_CPT1CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos)     /*!< 0x00040000 */

+#define HRTIM_CPT1CR_TIMBCMP1         HRTIM_CPT1CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */

+#define HRTIM_CPT1CR_TIMBCMP2_Pos     (19U)

+#define HRTIM_CPT1CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos)     /*!< 0x00080000 */

+#define HRTIM_CPT1CR_TIMBCMP2         HRTIM_CPT1CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */

+

+#define HRTIM_CPT1CR_TC1SET_Pos       (20U)

+#define HRTIM_CPT1CR_TC1SET_Msk       (0x1UL << HRTIM_CPT1CR_TC1SET_Pos)       /*!< 0x00100000 */

+#define HRTIM_CPT1CR_TC1SET           HRTIM_CPT1CR_TC1SET_Msk                  /*!< Timer C output 1 set */

+#define HRTIM_CPT1CR_TC1RST_Pos       (21U)

+#define HRTIM_CPT1CR_TC1RST_Msk       (0x1UL << HRTIM_CPT1CR_TC1RST_Pos)       /*!< 0x00200000 */

+#define HRTIM_CPT1CR_TC1RST           HRTIM_CPT1CR_TC1RST_Msk                  /*!< Timer C output 1 reset */

+#define HRTIM_CPT1CR_TIMCCMP1_Pos     (22U)

+#define HRTIM_CPT1CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos)     /*!< 0x00400000 */

+#define HRTIM_CPT1CR_TIMCCMP1         HRTIM_CPT1CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */

+#define HRTIM_CPT1CR_TIMCCMP2_Pos     (23U)

+#define HRTIM_CPT1CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos)     /*!< 0x00800000 */

+#define HRTIM_CPT1CR_TIMCCMP2         HRTIM_CPT1CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */

+

+#define HRTIM_CPT1CR_TD1SET_Pos       (24U)

+#define HRTIM_CPT1CR_TD1SET_Msk       (0x1UL << HRTIM_CPT1CR_TD1SET_Pos)       /*!< 0x01000000 */

+#define HRTIM_CPT1CR_TD1SET           HRTIM_CPT1CR_TD1SET_Msk                  /*!< Timer D output 1 set */

+#define HRTIM_CPT1CR_TD1RST_Pos       (25U)

+#define HRTIM_CPT1CR_TD1RST_Msk       (0x1UL << HRTIM_CPT1CR_TD1RST_Pos)       /*!< 0x02000000 */

+#define HRTIM_CPT1CR_TD1RST           HRTIM_CPT1CR_TD1RST_Msk                  /*!< Timer D output 1 reset */

+#define HRTIM_CPT1CR_TIMDCMP1_Pos     (26U)

+#define HRTIM_CPT1CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos)     /*!< 0x04000000 */

+#define HRTIM_CPT1CR_TIMDCMP1         HRTIM_CPT1CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */

+#define HRTIM_CPT1CR_TIMDCMP2_Pos     (27U)

+#define HRTIM_CPT1CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos)     /*!< 0x08000000 */

+#define HRTIM_CPT1CR_TIMDCMP2         HRTIM_CPT1CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */

+

+#define HRTIM_CPT1CR_TE1SET_Pos       (28U)

+#define HRTIM_CPT1CR_TE1SET_Msk       (0x1UL << HRTIM_CPT1CR_TE1SET_Pos)       /*!< 0x10000000 */

+#define HRTIM_CPT1CR_TE1SET           HRTIM_CPT1CR_TE1SET_Msk                  /*!< Timer E output 1 set */

+#define HRTIM_CPT1CR_TE1RST_Pos       (29U)

+#define HRTIM_CPT1CR_TE1RST_Msk       (0x1UL << HRTIM_CPT1CR_TE1RST_Pos)       /*!< 0x20000000 */

+#define HRTIM_CPT1CR_TE1RST           HRTIM_CPT1CR_TE1RST_Msk                  /*!< Timer E output 1 reset */

+#define HRTIM_CPT1CR_TIMECMP1_Pos     (30U)

+#define HRTIM_CPT1CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos)     /*!< 0x40000000 */

+#define HRTIM_CPT1CR_TIMECMP1         HRTIM_CPT1CR_TIMECMP1_Msk                /*!< Timer E compare 1 */

+#define HRTIM_CPT1CR_TIMECMP2_Pos     (31U)

+#define HRTIM_CPT1CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos)     /*!< 0x80000000 */

+#define HRTIM_CPT1CR_TIMECMP2         HRTIM_CPT1CR_TIMECMP2_Msk                /*!< Timer E compare 2 */

+

+/**** Bit definition for Slave Timer Capture 2 control register ***************/

+#define HRTIM_CPT2CR_SWCPT_Pos        (0U)

+#define HRTIM_CPT2CR_SWCPT_Msk        (0x1UL << HRTIM_CPT2CR_SWCPT_Pos)        /*!< 0x00000001 */

+#define HRTIM_CPT2CR_SWCPT            HRTIM_CPT2CR_SWCPT_Msk                   /*!< Software capture */

+#define HRTIM_CPT2CR_UPDCPT_Pos       (1U)

+#define HRTIM_CPT2CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos)       /*!< 0x00000002 */

+#define HRTIM_CPT2CR_UPDCPT           HRTIM_CPT2CR_UPDCPT_Msk                  /*!< Update capture */

+#define HRTIM_CPT2CR_EXEV1CPT_Pos     (2U)

+#define HRTIM_CPT2CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos)     /*!< 0x00000004 */

+#define HRTIM_CPT2CR_EXEV1CPT         HRTIM_CPT2CR_EXEV1CPT_Msk                /*!< External event 1 capture */

+#define HRTIM_CPT2CR_EXEV2CPT_Pos     (3U)

+#define HRTIM_CPT2CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos)     /*!< 0x00000008 */

+#define HRTIM_CPT2CR_EXEV2CPT         HRTIM_CPT2CR_EXEV2CPT_Msk                /*!< External event 2 capture */

+#define HRTIM_CPT2CR_EXEV3CPT_Pos     (4U)

+#define HRTIM_CPT2CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos)     /*!< 0x00000010 */

+#define HRTIM_CPT2CR_EXEV3CPT         HRTIM_CPT2CR_EXEV3CPT_Msk                /*!< External event 3 capture */

+#define HRTIM_CPT2CR_EXEV4CPT_Pos     (5U)

+#define HRTIM_CPT2CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos)     /*!< 0x00000020 */

+#define HRTIM_CPT2CR_EXEV4CPT         HRTIM_CPT2CR_EXEV4CPT_Msk                /*!< External event 4 capture */

+#define HRTIM_CPT2CR_EXEV5CPT_Pos     (6U)

+#define HRTIM_CPT2CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos)     /*!< 0x00000040 */

+#define HRTIM_CPT2CR_EXEV5CPT         HRTIM_CPT2CR_EXEV5CPT_Msk                /*!< External event 5 capture */

+#define HRTIM_CPT2CR_EXEV6CPT_Pos     (7U)

+#define HRTIM_CPT2CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos)     /*!< 0x00000080 */

+#define HRTIM_CPT2CR_EXEV6CPT         HRTIM_CPT2CR_EXEV6CPT_Msk                /*!< External event 6 capture */

+#define HRTIM_CPT2CR_EXEV7CPT_Pos     (8U)

+#define HRTIM_CPT2CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos)     /*!< 0x00000100 */

+#define HRTIM_CPT2CR_EXEV7CPT         HRTIM_CPT2CR_EXEV7CPT_Msk                /*!< External event 7 capture */

+#define HRTIM_CPT2CR_EXEV8CPT_Pos     (9U)

+#define HRTIM_CPT2CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos)     /*!< 0x00000200 */

+#define HRTIM_CPT2CR_EXEV8CPT         HRTIM_CPT2CR_EXEV8CPT_Msk                /*!< External event 8 capture */

+#define HRTIM_CPT2CR_EXEV9CPT_Pos     (10U)

+#define HRTIM_CPT2CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos)     /*!< 0x00000400 */

+#define HRTIM_CPT2CR_EXEV9CPT         HRTIM_CPT2CR_EXEV9CPT_Msk                /*!< External event 9 capture */

+#define HRTIM_CPT2CR_EXEV10CPT_Pos    (11U)

+#define HRTIM_CPT2CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos)    /*!< 0x00000800 */

+#define HRTIM_CPT2CR_EXEV10CPT        HRTIM_CPT2CR_EXEV10CPT_Msk               /*!< External event 10 capture */

+

+#define HRTIM_CPT2CR_TA1SET_Pos       (12U)

+#define HRTIM_CPT2CR_TA1SET_Msk       (0x1UL << HRTIM_CPT2CR_TA1SET_Pos)       /*!< 0x00001000 */

+#define HRTIM_CPT2CR_TA1SET           HRTIM_CPT2CR_TA1SET_Msk                  /*!< Timer A output 1 set */

+#define HRTIM_CPT2CR_TA1RST_Pos       (13U)

+#define HRTIM_CPT2CR_TA1RST_Msk       (0x1UL << HRTIM_CPT2CR_TA1RST_Pos)       /*!< 0x00002000 */

+#define HRTIM_CPT2CR_TA1RST           HRTIM_CPT2CR_TA1RST_Msk                  /*!< Timer A output 1 reset */

+#define HRTIM_CPT2CR_TIMACMP1_Pos     (14U)

+#define HRTIM_CPT2CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos)     /*!< 0x00004000 */

+#define HRTIM_CPT2CR_TIMACMP1         HRTIM_CPT2CR_TIMACMP1_Msk                /*!< Timer A compare 1 */

+#define HRTIM_CPT2CR_TIMACMP2_Pos     (15U)

+#define HRTIM_CPT2CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos)     /*!< 0x00008000 */

+#define HRTIM_CPT2CR_TIMACMP2         HRTIM_CPT2CR_TIMACMP2_Msk                /*!< Timer A compare 2 */

+

+#define HRTIM_CPT2CR_TB1SET_Pos       (16U)

+#define HRTIM_CPT2CR_TB1SET_Msk       (0x1UL << HRTIM_CPT2CR_TB1SET_Pos)       /*!< 0x00010000 */

+#define HRTIM_CPT2CR_TB1SET           HRTIM_CPT2CR_TB1SET_Msk                  /*!< Timer B output 1 set */

+#define HRTIM_CPT2CR_TB1RST_Pos       (17U)

+#define HRTIM_CPT2CR_TB1RST_Msk       (0x1UL << HRTIM_CPT2CR_TB1RST_Pos)       /*!< 0x00020000 */

+#define HRTIM_CPT2CR_TB1RST           HRTIM_CPT2CR_TB1RST_Msk                  /*!< Timer B output 1 reset */

+#define HRTIM_CPT2CR_TIMBCMP1_Pos     (18U)

+#define HRTIM_CPT2CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos)     /*!< 0x00040000 */

+#define HRTIM_CPT2CR_TIMBCMP1         HRTIM_CPT2CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */

+#define HRTIM_CPT2CR_TIMBCMP2_Pos     (19U)

+#define HRTIM_CPT2CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos)     /*!< 0x00080000 */

+#define HRTIM_CPT2CR_TIMBCMP2         HRTIM_CPT2CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */

+

+#define HRTIM_CPT2CR_TC1SET_Pos       (20U)

+#define HRTIM_CPT2CR_TC1SET_Msk       (0x1UL << HRTIM_CPT2CR_TC1SET_Pos)       /*!< 0x00100000 */

+#define HRTIM_CPT2CR_TC1SET           HRTIM_CPT2CR_TC1SET_Msk                  /*!< Timer C output 1 set */

+#define HRTIM_CPT2CR_TC1RST_Pos       (21U)

+#define HRTIM_CPT2CR_TC1RST_Msk       (0x1UL << HRTIM_CPT2CR_TC1RST_Pos)       /*!< 0x00200000 */

+#define HRTIM_CPT2CR_TC1RST           HRTIM_CPT2CR_TC1RST_Msk                  /*!< Timer C output 1 reset */

+#define HRTIM_CPT2CR_TIMCCMP1_Pos     (22U)

+#define HRTIM_CPT2CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos)     /*!< 0x00400000 */

+#define HRTIM_CPT2CR_TIMCCMP1         HRTIM_CPT2CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */

+#define HRTIM_CPT2CR_TIMCCMP2_Pos     (23U)

+#define HRTIM_CPT2CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos)     /*!< 0x00800000 */

+#define HRTIM_CPT2CR_TIMCCMP2         HRTIM_CPT2CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */

+

+#define HRTIM_CPT2CR_TD1SET_Pos       (24U)

+#define HRTIM_CPT2CR_TD1SET_Msk       (0x1UL << HRTIM_CPT2CR_TD1SET_Pos)       /*!< 0x01000000 */

+#define HRTIM_CPT2CR_TD1SET           HRTIM_CPT2CR_TD1SET_Msk                  /*!< Timer D output 1 set */

+#define HRTIM_CPT2CR_TD1RST_Pos       (25U)

+#define HRTIM_CPT2CR_TD1RST_Msk       (0x1UL << HRTIM_CPT2CR_TD1RST_Pos)       /*!< 0x02000000 */

+#define HRTIM_CPT2CR_TD1RST           HRTIM_CPT2CR_TD1RST_Msk                  /*!< Timer D output 1 reset */

+#define HRTIM_CPT2CR_TIMDCMP1_Pos     (26U)

+#define HRTIM_CPT2CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos)     /*!< 0x04000000 */

+#define HRTIM_CPT2CR_TIMDCMP1         HRTIM_CPT2CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */

+#define HRTIM_CPT2CR_TIMDCMP2_Pos     (27U)

+#define HRTIM_CPT2CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos)     /*!< 0x08000000 */

+#define HRTIM_CPT2CR_TIMDCMP2         HRTIM_CPT2CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */

+

+#define HRTIM_CPT2CR_TE1SET_Pos       (28U)

+#define HRTIM_CPT2CR_TE1SET_Msk       (0x1UL << HRTIM_CPT2CR_TE1SET_Pos)       /*!< 0x10000000 */

+#define HRTIM_CPT2CR_TE1SET           HRTIM_CPT2CR_TE1SET_Msk                  /*!< Timer E output 1 set */

+#define HRTIM_CPT2CR_TE1RST_Pos       (29U)

+#define HRTIM_CPT2CR_TE1RST_Msk       (0x1UL << HRTIM_CPT2CR_TE1RST_Pos)       /*!< 0x20000000 */

+#define HRTIM_CPT2CR_TE1RST           HRTIM_CPT2CR_TE1RST_Msk                  /*!< Timer E output 1 reset */

+#define HRTIM_CPT2CR_TIMECMP1_Pos     (30U)

+#define HRTIM_CPT2CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos)     /*!< 0x40000000 */

+#define HRTIM_CPT2CR_TIMECMP1         HRTIM_CPT2CR_TIMECMP1_Msk                /*!< Timer E compare 1 */

+#define HRTIM_CPT2CR_TIMECMP2_Pos     (31U)

+#define HRTIM_CPT2CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos)     /*!< 0x80000000 */

+#define HRTIM_CPT2CR_TIMECMP2         HRTIM_CPT2CR_TIMECMP2_Msk                /*!< Timer E compare 2 */

+

+/**** Bit definition for Slave Timer Output register **************************/

+#define HRTIM_OUTR_POL1_Pos           (1U)

+#define HRTIM_OUTR_POL1_Msk           (0x1UL << HRTIM_OUTR_POL1_Pos)           /*!< 0x00000002 */

+#define HRTIM_OUTR_POL1               HRTIM_OUTR_POL1_Msk                      /*!< Slave output 1 polarity */

+#define HRTIM_OUTR_IDLM1_Pos          (2U)

+#define HRTIM_OUTR_IDLM1_Msk          (0x1UL << HRTIM_OUTR_IDLM1_Pos)          /*!< 0x00000004 */

+#define HRTIM_OUTR_IDLM1              HRTIM_OUTR_IDLM1_Msk                     /*!< Slave output 1 idle mode */

+#define HRTIM_OUTR_IDLES1_Pos         (3U)

+#define HRTIM_OUTR_IDLES1_Msk         (0x1UL << HRTIM_OUTR_IDLES1_Pos)         /*!< 0x00000008 */

+#define HRTIM_OUTR_IDLES1             HRTIM_OUTR_IDLES1_Msk                    /*!< Slave output 1 idle state */

+#define HRTIM_OUTR_FAULT1_Pos         (4U)

+#define HRTIM_OUTR_FAULT1_Msk         (0x3UL << HRTIM_OUTR_FAULT1_Pos)         /*!< 0x00000030 */

+#define HRTIM_OUTR_FAULT1             HRTIM_OUTR_FAULT1_Msk                    /*!< Slave output 1 fault state */

+#define HRTIM_OUTR_FAULT1_0           (0x1UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000010 */

+#define HRTIM_OUTR_FAULT1_1           (0x2UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000020 */

+#define HRTIM_OUTR_CHP1_Pos           (6U)

+#define HRTIM_OUTR_CHP1_Msk           (0x1UL << HRTIM_OUTR_CHP1_Pos)           /*!< 0x00000040 */

+#define HRTIM_OUTR_CHP1               HRTIM_OUTR_CHP1_Msk                      /*!< Slave output 1 chopper enable */

+#define HRTIM_OUTR_DIDL1_Pos          (7U)

+#define HRTIM_OUTR_DIDL1_Msk          (0x1UL << HRTIM_OUTR_DIDL1_Pos)          /*!< 0x00000080 */

+#define HRTIM_OUTR_DIDL1              HRTIM_OUTR_DIDL1_Msk                     /*!< Slave output 1 dead time idle */

+

+#define HRTIM_OUTR_DTEN_Pos           (8U)

+#define HRTIM_OUTR_DTEN_Msk           (0x1UL << HRTIM_OUTR_DTEN_Pos)           /*!< 0x00000100 */

+#define HRTIM_OUTR_DTEN               HRTIM_OUTR_DTEN_Msk                      /*!< Slave output deadtime enable */

+#define HRTIM_OUTR_DLYPRTEN_Pos       (9U)

+#define HRTIM_OUTR_DLYPRTEN_Msk       (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos)       /*!< 0x00000200 */

+#define HRTIM_OUTR_DLYPRTEN           HRTIM_OUTR_DLYPRTEN_Msk                  /*!< Slave output delay protection enable */

+#define HRTIM_OUTR_DLYPRT_Pos         (10U)

+#define HRTIM_OUTR_DLYPRT_Msk         (0x7UL << HRTIM_OUTR_DLYPRT_Pos)         /*!< 0x00001C00 */

+#define HRTIM_OUTR_DLYPRT             HRTIM_OUTR_DLYPRT_Msk                    /*!< Slave output delay protection */

+#define HRTIM_OUTR_DLYPRT_0           (0x1UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000400 */

+#define HRTIM_OUTR_DLYPRT_1           (0x2UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000800 */

+#define HRTIM_OUTR_DLYPRT_2           (0x4UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00001000 */

+

+#define HRTIM_OUTR_POL2_Pos           (17U)

+#define HRTIM_OUTR_POL2_Msk           (0x1UL << HRTIM_OUTR_POL2_Pos)           /*!< 0x00020000 */

+#define HRTIM_OUTR_POL2               HRTIM_OUTR_POL2_Msk                      /*!< Slave output 2 polarity */

+#define HRTIM_OUTR_IDLM2_Pos          (18U)

+#define HRTIM_OUTR_IDLM2_Msk          (0x1UL << HRTIM_OUTR_IDLM2_Pos)          /*!< 0x00040000 */

+#define HRTIM_OUTR_IDLM2              HRTIM_OUTR_IDLM2_Msk                     /*!< Slave output 2 idle mode */

+#define HRTIM_OUTR_IDLES2_Pos         (19U)

+#define HRTIM_OUTR_IDLES2_Msk         (0x1UL << HRTIM_OUTR_IDLES2_Pos)         /*!< 0x00080000 */

+#define HRTIM_OUTR_IDLES2             HRTIM_OUTR_IDLES2_Msk                    /*!< Slave output 2 idle state */

+#define HRTIM_OUTR_FAULT2_Pos         (20U)

+#define HRTIM_OUTR_FAULT2_Msk         (0x3UL << HRTIM_OUTR_FAULT2_Pos)         /*!< 0x00300000 */

+#define HRTIM_OUTR_FAULT2             HRTIM_OUTR_FAULT2_Msk                    /*!< Slave output 2 fault state */

+#define HRTIM_OUTR_FAULT2_0           (0x1UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00100000 */

+#define HRTIM_OUTR_FAULT2_1           (0x2UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00200000 */

+#define HRTIM_OUTR_CHP2_Pos           (22U)

+#define HRTIM_OUTR_CHP2_Msk           (0x1UL << HRTIM_OUTR_CHP2_Pos)           /*!< 0x00400000 */

+#define HRTIM_OUTR_CHP2               HRTIM_OUTR_CHP2_Msk                      /*!< Slave output 2 chopper enable */

+#define HRTIM_OUTR_DIDL2_Pos          (23U)

+#define HRTIM_OUTR_DIDL2_Msk          (0x1UL << HRTIM_OUTR_DIDL2_Pos)          /*!< 0x00800000 */

+#define HRTIM_OUTR_DIDL2              HRTIM_OUTR_DIDL2_Msk                     /*!< Slave output 2 dead time idle */

+

+/**** Bit definition for Slave Timer Fault register ***************************/

+#define HRTIM_FLTR_FLT1EN_Pos         (0U)

+#define HRTIM_FLTR_FLT1EN_Msk         (0x1UL << HRTIM_FLTR_FLT1EN_Pos)         /*!< 0x00000001 */

+#define HRTIM_FLTR_FLT1EN             HRTIM_FLTR_FLT1EN_Msk                    /*!< Fault 1 enable */

+#define HRTIM_FLTR_FLT2EN_Pos         (1U)

+#define HRTIM_FLTR_FLT2EN_Msk         (0x1UL << HRTIM_FLTR_FLT2EN_Pos)         /*!< 0x00000002 */

+#define HRTIM_FLTR_FLT2EN             HRTIM_FLTR_FLT2EN_Msk                    /*!< Fault 2 enable */

+#define HRTIM_FLTR_FLT3EN_Pos         (2U)

+#define HRTIM_FLTR_FLT3EN_Msk         (0x1UL << HRTIM_FLTR_FLT3EN_Pos)         /*!< 0x00000004 */

+#define HRTIM_FLTR_FLT3EN             HRTIM_FLTR_FLT3EN_Msk                    /*!< Fault 3 enable */

+#define HRTIM_FLTR_FLT4EN_Pos         (3U)

+#define HRTIM_FLTR_FLT4EN_Msk         (0x1UL << HRTIM_FLTR_FLT4EN_Pos)         /*!< 0x00000008 */

+#define HRTIM_FLTR_FLT4EN             HRTIM_FLTR_FLT4EN_Msk                    /*!< Fault 4 enable */

+#define HRTIM_FLTR_FLT5EN_Pos         (4U)

+#define HRTIM_FLTR_FLT5EN_Msk         (0x1UL << HRTIM_FLTR_FLT5EN_Pos)         /*!< 0x00000010 */

+#define HRTIM_FLTR_FLT5EN             HRTIM_FLTR_FLT5EN_Msk                    /*!< Fault 5 enable */

+#define HRTIM_FLTR_FLTLCK_Pos         (31U)

+#define HRTIM_FLTR_FLTLCK_Msk         (0x1UL << HRTIM_FLTR_FLTLCK_Pos)         /*!< 0x80000000 */

+#define HRTIM_FLTR_FLTLCK             HRTIM_FLTR_FLTLCK_Msk                    /*!< Fault sources lock */

+

+/**** Bit definition for Common HRTIM Timer control register 1 ****************/

+#define HRTIM_CR1_MUDIS_Pos           (0U)

+#define HRTIM_CR1_MUDIS_Msk           (0x1UL << HRTIM_CR1_MUDIS_Pos)           /*!< 0x00000001 */

+#define HRTIM_CR1_MUDIS               HRTIM_CR1_MUDIS_Msk                      /*!< Master update disable*/

+#define HRTIM_CR1_TAUDIS_Pos          (1U)

+#define HRTIM_CR1_TAUDIS_Msk          (0x1UL << HRTIM_CR1_TAUDIS_Pos)          /*!< 0x00000002 */

+#define HRTIM_CR1_TAUDIS              HRTIM_CR1_TAUDIS_Msk                     /*!< Timer A update disable*/

+#define HRTIM_CR1_TBUDIS_Pos          (2U)

+#define HRTIM_CR1_TBUDIS_Msk          (0x1UL << HRTIM_CR1_TBUDIS_Pos)          /*!< 0x00000004 */

+#define HRTIM_CR1_TBUDIS              HRTIM_CR1_TBUDIS_Msk                     /*!< Timer B update disable*/

+#define HRTIM_CR1_TCUDIS_Pos          (3U)

+#define HRTIM_CR1_TCUDIS_Msk          (0x1UL << HRTIM_CR1_TCUDIS_Pos)          /*!< 0x00000008 */

+#define HRTIM_CR1_TCUDIS              HRTIM_CR1_TCUDIS_Msk                     /*!< Timer C update disable*/

+#define HRTIM_CR1_TDUDIS_Pos          (4U)

+#define HRTIM_CR1_TDUDIS_Msk          (0x1UL << HRTIM_CR1_TDUDIS_Pos)          /*!< 0x00000010 */

+#define HRTIM_CR1_TDUDIS              HRTIM_CR1_TDUDIS_Msk                     /*!< Timer D update disable*/

+#define HRTIM_CR1_TEUDIS_Pos          (5U)

+#define HRTIM_CR1_TEUDIS_Msk          (0x1UL << HRTIM_CR1_TEUDIS_Pos)          /*!< 0x00000020 */

+#define HRTIM_CR1_TEUDIS              HRTIM_CR1_TEUDIS_Msk                     /*!< Timer E update disable*/

+#define HRTIM_CR1_ADC1USRC_Pos        (16U)

+#define HRTIM_CR1_ADC1USRC_Msk        (0x7UL << HRTIM_CR1_ADC1USRC_Pos)        /*!< 0x00070000 */

+#define HRTIM_CR1_ADC1USRC            HRTIM_CR1_ADC1USRC_Msk                   /*!< ADC Trigger 1 update source */

+#define HRTIM_CR1_ADC1USRC_0          (0x1UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00010000 */

+#define HRTIM_CR1_ADC1USRC_1          (0x2UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00020000 */

+#define HRTIM_CR1_ADC1USRC_2          (0x4UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00040000 */

+#define HRTIM_CR1_ADC2USRC_Pos        (19U)

+#define HRTIM_CR1_ADC2USRC_Msk        (0x7UL << HRTIM_CR1_ADC2USRC_Pos)        /*!< 0x00380000 */

+#define HRTIM_CR1_ADC2USRC            HRTIM_CR1_ADC2USRC_Msk                   /*!< ADC Trigger 2 update source */

+#define HRTIM_CR1_ADC2USRC_0          (0x1UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00080000 */

+#define HRTIM_CR1_ADC2USRC_1          (0x2UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00100000 */

+#define HRTIM_CR1_ADC2USRC_2          (0x4UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00200000 */

+#define HRTIM_CR1_ADC3USRC_Pos        (22U)

+#define HRTIM_CR1_ADC3USRC_Msk        (0x7UL << HRTIM_CR1_ADC3USRC_Pos)        /*!< 0x01C00000 */

+#define HRTIM_CR1_ADC3USRC            HRTIM_CR1_ADC3USRC_Msk                   /*!< ADC Trigger 3 update source */

+#define HRTIM_CR1_ADC3USRC_0          (0x1UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00400000 */

+#define HRTIM_CR1_ADC3USRC_1          (0x2UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00800000 */

+#define HRTIM_CR1_ADC3USRC_2          (0x4UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x01000000 */

+#define HRTIM_CR1_ADC4USRC_Pos        (25U)

+#define HRTIM_CR1_ADC4USRC_Msk        (0x7UL << HRTIM_CR1_ADC4USRC_Pos)        /*!< 0x0E000000 */

+#define HRTIM_CR1_ADC4USRC            HRTIM_CR1_ADC4USRC_Msk                   /*!< ADC Trigger 4 update source */

+#define HRTIM_CR1_ADC4USRC_0          (0x1UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x02000000 */

+#define HRTIM_CR1_ADC4USRC_1          (0x2UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x04000000 */

+#define HRTIM_CR1_ADC4USRC_2          (0x0UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x0800000 */

+

+/**** Bit definition for Common HRTIM Timer control register 2 ****************/

+#define HRTIM_CR2_MSWU_Pos            (0U)

+#define HRTIM_CR2_MSWU_Msk            (0x1UL << HRTIM_CR2_MSWU_Pos)            /*!< 0x00000001 */

+#define HRTIM_CR2_MSWU                HRTIM_CR2_MSWU_Msk                       /*!< Master software update */

+#define HRTIM_CR2_TASWU_Pos           (1U)

+#define HRTIM_CR2_TASWU_Msk           (0x1UL << HRTIM_CR2_TASWU_Pos)           /*!< 0x00000002 */

+#define HRTIM_CR2_TASWU               HRTIM_CR2_TASWU_Msk                      /*!< Timer A software update */

+#define HRTIM_CR2_TBSWU_Pos           (2U)

+#define HRTIM_CR2_TBSWU_Msk           (0x1UL << HRTIM_CR2_TBSWU_Pos)           /*!< 0x00000004 */

+#define HRTIM_CR2_TBSWU               HRTIM_CR2_TBSWU_Msk                      /*!< Timer B software update */

+#define HRTIM_CR2_TCSWU_Pos           (3U)

+#define HRTIM_CR2_TCSWU_Msk           (0x1UL << HRTIM_CR2_TCSWU_Pos)           /*!< 0x00000008 */

+#define HRTIM_CR2_TCSWU               HRTIM_CR2_TCSWU_Msk                      /*!< Timer C software update */

+#define HRTIM_CR2_TDSWU_Pos           (4U)

+#define HRTIM_CR2_TDSWU_Msk           (0x1UL << HRTIM_CR2_TDSWU_Pos)           /*!< 0x00000010 */

+#define HRTIM_CR2_TDSWU               HRTIM_CR2_TDSWU_Msk                      /*!< Timer D software update */

+#define HRTIM_CR2_TESWU_Pos           (5U)

+#define HRTIM_CR2_TESWU_Msk           (0x1UL << HRTIM_CR2_TESWU_Pos)           /*!< 0x00000020 */

+#define HRTIM_CR2_TESWU               HRTIM_CR2_TESWU_Msk                      /*!< Timer E software update */

+#define HRTIM_CR2_MRST_Pos            (8U)

+#define HRTIM_CR2_MRST_Msk            (0x1UL << HRTIM_CR2_MRST_Pos)            /*!< 0x00000100 */

+#define HRTIM_CR2_MRST                HRTIM_CR2_MRST_Msk                       /*!< Master count software reset */

+#define HRTIM_CR2_TARST_Pos           (9U)

+#define HRTIM_CR2_TARST_Msk           (0x1UL << HRTIM_CR2_TARST_Pos)           /*!< 0x00000200 */

+#define HRTIM_CR2_TARST               HRTIM_CR2_TARST_Msk                      /*!< Timer A count software reset */

+#define HRTIM_CR2_TBRST_Pos           (10U)

+#define HRTIM_CR2_TBRST_Msk           (0x1UL << HRTIM_CR2_TBRST_Pos)           /*!< 0x00000400 */

+#define HRTIM_CR2_TBRST               HRTIM_CR2_TBRST_Msk                      /*!< Timer B count software reset */

+#define HRTIM_CR2_TCRST_Pos           (11U)

+#define HRTIM_CR2_TCRST_Msk           (0x1UL << HRTIM_CR2_TCRST_Pos)           /*!< 0x00000800 */

+#define HRTIM_CR2_TCRST               HRTIM_CR2_TCRST_Msk                      /*!< Timer C count software reset */

+#define HRTIM_CR2_TDRST_Pos           (12U)

+#define HRTIM_CR2_TDRST_Msk           (0x1UL << HRTIM_CR2_TDRST_Pos)           /*!< 0x00001000 */

+#define HRTIM_CR2_TDRST               HRTIM_CR2_TDRST_Msk                      /*!< Timer D count software reset */

+#define HRTIM_CR2_TERST_Pos           (13U)

+#define HRTIM_CR2_TERST_Msk           (0x1UL << HRTIM_CR2_TERST_Pos)           /*!< 0x00002000 */

+#define HRTIM_CR2_TERST               HRTIM_CR2_TERST_Msk                      /*!< Timer E count software reset */

+

+/**** Bit definition for Common HRTIM Timer interrupt status register *********/

+#define HRTIM_ISR_FLT1_Pos            (0U)

+#define HRTIM_ISR_FLT1_Msk            (0x1UL << HRTIM_ISR_FLT1_Pos)            /*!< 0x00000001 */

+#define HRTIM_ISR_FLT1                HRTIM_ISR_FLT1_Msk                       /*!< Fault 1 interrupt flag */

+#define HRTIM_ISR_FLT2_Pos            (1U)

+#define HRTIM_ISR_FLT2_Msk            (0x1UL << HRTIM_ISR_FLT2_Pos)            /*!< 0x00000002 */

+#define HRTIM_ISR_FLT2                HRTIM_ISR_FLT2_Msk                       /*!< Fault 2 interrupt flag */

+#define HRTIM_ISR_FLT3_Pos            (2U)

+#define HRTIM_ISR_FLT3_Msk            (0x1UL << HRTIM_ISR_FLT3_Pos)            /*!< 0x00000004 */

+#define HRTIM_ISR_FLT3                HRTIM_ISR_FLT3_Msk                       /*!< Fault 3 interrupt flag */

+#define HRTIM_ISR_FLT4_Pos            (3U)

+#define HRTIM_ISR_FLT4_Msk            (0x1UL << HRTIM_ISR_FLT4_Pos)            /*!< 0x00000008 */

+#define HRTIM_ISR_FLT4                HRTIM_ISR_FLT4_Msk                       /*!< Fault 4 interrupt flag */

+#define HRTIM_ISR_FLT5_Pos            (4U)

+#define HRTIM_ISR_FLT5_Msk            (0x1UL << HRTIM_ISR_FLT5_Pos)            /*!< 0x00000010 */

+#define HRTIM_ISR_FLT5                HRTIM_ISR_FLT5_Msk                       /*!< Fault 5 interrupt flag */

+#define HRTIM_ISR_SYSFLT_Pos          (5U)

+#define HRTIM_ISR_SYSFLT_Msk          (0x1UL << HRTIM_ISR_SYSFLT_Pos)          /*!< 0x00000020 */

+#define HRTIM_ISR_SYSFLT              HRTIM_ISR_SYSFLT_Msk                     /*!< System Fault interrupt flag */

+#define HRTIM_ISR_BMPER_Pos           (17U)

+#define HRTIM_ISR_BMPER_Msk           (0x1UL << HRTIM_ISR_BMPER_Pos)           /*!< 0x00020000 */

+#define HRTIM_ISR_BMPER               HRTIM_ISR_BMPER_Msk                      /*!<  Burst mode period interrupt flag */

+

+/**** Bit definition for Common HRTIM Timer interrupt clear register **********/

+#define HRTIM_ICR_FLT1C_Pos           (0U)

+#define HRTIM_ICR_FLT1C_Msk           (0x1UL << HRTIM_ICR_FLT1C_Pos)           /*!< 0x00000001 */

+#define HRTIM_ICR_FLT1C               HRTIM_ICR_FLT1C_Msk                      /*!< Fault 1 interrupt flag clear */

+#define HRTIM_ICR_FLT2C_Pos           (1U)

+#define HRTIM_ICR_FLT2C_Msk           (0x1UL << HRTIM_ICR_FLT2C_Pos)           /*!< 0x00000002 */

+#define HRTIM_ICR_FLT2C               HRTIM_ICR_FLT2C_Msk                      /*!< Fault 2 interrupt flag clear */

+#define HRTIM_ICR_FLT3C_Pos           (2U)

+#define HRTIM_ICR_FLT3C_Msk           (0x1UL << HRTIM_ICR_FLT3C_Pos)           /*!< 0x00000004 */

+#define HRTIM_ICR_FLT3C               HRTIM_ICR_FLT3C_Msk                      /*!< Fault 3 interrupt flag clear */

+#define HRTIM_ICR_FLT4C_Pos           (3U)

+#define HRTIM_ICR_FLT4C_Msk           (0x1UL << HRTIM_ICR_FLT4C_Pos)           /*!< 0x00000008 */

+#define HRTIM_ICR_FLT4C               HRTIM_ICR_FLT4C_Msk                      /*!< Fault 4 interrupt flag clear */

+#define HRTIM_ICR_FLT5C_Pos           (4U)

+#define HRTIM_ICR_FLT5C_Msk           (0x1UL << HRTIM_ICR_FLT5C_Pos)           /*!< 0x00000010 */

+#define HRTIM_ICR_FLT5C               HRTIM_ICR_FLT5C_Msk                      /*!< Fault 5 interrupt flag clear */

+#define HRTIM_ICR_SYSFLTC_Pos         (5U)

+#define HRTIM_ICR_SYSFLTC_Msk         (0x1UL << HRTIM_ICR_SYSFLTC_Pos)         /*!< 0x00000020 */

+#define HRTIM_ICR_SYSFLTC             HRTIM_ICR_SYSFLTC_Msk                    /*!< System Fault interrupt flag clear */

+#define HRTIM_ICR_BMPERC_Pos          (17U)

+#define HRTIM_ICR_BMPERC_Msk          (0x1UL << HRTIM_ICR_BMPERC_Pos)          /*!< 0x00020000 */

+#define HRTIM_ICR_BMPERC              HRTIM_ICR_BMPERC_Msk                     /*!<  Burst mode period interrupt flag clear */

+

+/**** Bit definition for Common HRTIM Timer interrupt enable register *********/

+#define HRTIM_IER_FLT1_Pos            (0U)

+#define HRTIM_IER_FLT1_Msk            (0x1UL << HRTIM_IER_FLT1_Pos)            /*!< 0x00000001 */

+#define HRTIM_IER_FLT1                HRTIM_IER_FLT1_Msk                       /*!< Fault 1 interrupt enable */

+#define HRTIM_IER_FLT2_Pos            (1U)

+#define HRTIM_IER_FLT2_Msk            (0x1UL << HRTIM_IER_FLT2_Pos)            /*!< 0x00000002 */

+#define HRTIM_IER_FLT2                HRTIM_IER_FLT2_Msk                       /*!< Fault 2 interrupt enable */

+#define HRTIM_IER_FLT3_Pos            (2U)

+#define HRTIM_IER_FLT3_Msk            (0x1UL << HRTIM_IER_FLT3_Pos)            /*!< 0x00000004 */

+#define HRTIM_IER_FLT3                HRTIM_IER_FLT3_Msk                       /*!< Fault 3 interrupt enable */

+#define HRTIM_IER_FLT4_Pos            (3U)

+#define HRTIM_IER_FLT4_Msk            (0x1UL << HRTIM_IER_FLT4_Pos)            /*!< 0x00000008 */

+#define HRTIM_IER_FLT4                HRTIM_IER_FLT4_Msk                       /*!< Fault 4 interrupt enable */

+#define HRTIM_IER_FLT5_Pos            (4U)

+#define HRTIM_IER_FLT5_Msk            (0x1UL << HRTIM_IER_FLT5_Pos)            /*!< 0x00000010 */

+#define HRTIM_IER_FLT5                HRTIM_IER_FLT5_Msk                       /*!< Fault 5 interrupt enable */

+#define HRTIM_IER_SYSFLT_Pos          (5U)

+#define HRTIM_IER_SYSFLT_Msk          (0x1UL << HRTIM_IER_SYSFLT_Pos)          /*!< 0x00000020 */

+#define HRTIM_IER_SYSFLT              HRTIM_IER_SYSFLT_Msk                     /*!< System Fault interrupt enable */

+#define HRTIM_IER_BMPER_Pos           (17U)

+#define HRTIM_IER_BMPER_Msk           (0x1UL << HRTIM_IER_BMPER_Pos)           /*!< 0x00020000 */

+#define HRTIM_IER_BMPER               HRTIM_IER_BMPER_Msk                      /*!<  Burst mode period interrupt enable */

+

+/**** Bit definition for Common HRTIM Timer output enable register ************/

+#define HRTIM_OENR_TA1OEN_Pos         (0U)

+#define HRTIM_OENR_TA1OEN_Msk         (0x1UL << HRTIM_OENR_TA1OEN_Pos)         /*!< 0x00000001 */

+#define HRTIM_OENR_TA1OEN             HRTIM_OENR_TA1OEN_Msk                    /*!< Timer A Output 1 enable */

+#define HRTIM_OENR_TA2OEN_Pos         (1U)

+#define HRTIM_OENR_TA2OEN_Msk         (0x1UL << HRTIM_OENR_TA2OEN_Pos)         /*!< 0x00000002 */

+#define HRTIM_OENR_TA2OEN             HRTIM_OENR_TA2OEN_Msk                    /*!< Timer A Output 2 enable */

+#define HRTIM_OENR_TB1OEN_Pos         (2U)

+#define HRTIM_OENR_TB1OEN_Msk         (0x1UL << HRTIM_OENR_TB1OEN_Pos)         /*!< 0x00000004 */

+#define HRTIM_OENR_TB1OEN             HRTIM_OENR_TB1OEN_Msk                    /*!< Timer B Output 1 enable */

+#define HRTIM_OENR_TB2OEN_Pos         (3U)

+#define HRTIM_OENR_TB2OEN_Msk         (0x1UL << HRTIM_OENR_TB2OEN_Pos)         /*!< 0x00000008 */

+#define HRTIM_OENR_TB2OEN             HRTIM_OENR_TB2OEN_Msk                    /*!< Timer B Output 2 enable */

+#define HRTIM_OENR_TC1OEN_Pos         (4U)

+#define HRTIM_OENR_TC1OEN_Msk         (0x1UL << HRTIM_OENR_TC1OEN_Pos)         /*!< 0x00000010 */

+#define HRTIM_OENR_TC1OEN             HRTIM_OENR_TC1OEN_Msk                    /*!< Timer C Output 1 enable */

+#define HRTIM_OENR_TC2OEN_Pos         (5U)

+#define HRTIM_OENR_TC2OEN_Msk         (0x1UL << HRTIM_OENR_TC2OEN_Pos)         /*!< 0x00000020 */

+#define HRTIM_OENR_TC2OEN             HRTIM_OENR_TC2OEN_Msk                    /*!< Timer C Output 2 enable */

+#define HRTIM_OENR_TD1OEN_Pos         (6U)

+#define HRTIM_OENR_TD1OEN_Msk         (0x1UL << HRTIM_OENR_TD1OEN_Pos)         /*!< 0x00000040 */

+#define HRTIM_OENR_TD1OEN             HRTIM_OENR_TD1OEN_Msk                    /*!< Timer D Output 1 enable */

+#define HRTIM_OENR_TD2OEN_Pos         (7U)

+#define HRTIM_OENR_TD2OEN_Msk         (0x1UL << HRTIM_OENR_TD2OEN_Pos)         /*!< 0x00000080 */

+#define HRTIM_OENR_TD2OEN             HRTIM_OENR_TD2OEN_Msk                    /*!< Timer D Output 2 enable */

+#define HRTIM_OENR_TE1OEN_Pos         (8U)

+#define HRTIM_OENR_TE1OEN_Msk         (0x1UL << HRTIM_OENR_TE1OEN_Pos)         /*!< 0x00000100 */

+#define HRTIM_OENR_TE1OEN             HRTIM_OENR_TE1OEN_Msk                    /*!< Timer E Output 1 enable */

+#define HRTIM_OENR_TE2OEN_Pos         (9U)

+#define HRTIM_OENR_TE2OEN_Msk         (0x1UL << HRTIM_OENR_TE2OEN_Pos)         /*!< 0x00000200 */

+#define HRTIM_OENR_TE2OEN             HRTIM_OENR_TE2OEN_Msk                    /*!< Timer E Output 2 enable */

+

+/**** Bit definition for Common HRTIM Timer output disable register ***********/

+#define HRTIM_ODISR_TA1ODIS_Pos       (0U)

+#define HRTIM_ODISR_TA1ODIS_Msk       (0x1UL << HRTIM_ODISR_TA1ODIS_Pos)       /*!< 0x00000001 */

+#define HRTIM_ODISR_TA1ODIS           HRTIM_ODISR_TA1ODIS_Msk                  /*!< Timer A Output 1 disable */

+#define HRTIM_ODISR_TA2ODIS_Pos       (1U)

+#define HRTIM_ODISR_TA2ODIS_Msk       (0x1UL << HRTIM_ODISR_TA2ODIS_Pos)       /*!< 0x00000002 */

+#define HRTIM_ODISR_TA2ODIS           HRTIM_ODISR_TA2ODIS_Msk                  /*!< Timer A Output 2 disable */

+#define HRTIM_ODISR_TB1ODIS_Pos       (2U)

+#define HRTIM_ODISR_TB1ODIS_Msk       (0x1UL << HRTIM_ODISR_TB1ODIS_Pos)       /*!< 0x00000004 */

+#define HRTIM_ODISR_TB1ODIS           HRTIM_ODISR_TB1ODIS_Msk                  /*!< Timer B Output 1 disable */

+#define HRTIM_ODISR_TB2ODIS_Pos       (3U)

+#define HRTIM_ODISR_TB2ODIS_Msk       (0x1UL << HRTIM_ODISR_TB2ODIS_Pos)       /*!< 0x00000008 */

+#define HRTIM_ODISR_TB2ODIS           HRTIM_ODISR_TB2ODIS_Msk                  /*!< Timer B Output 2 disable */

+#define HRTIM_ODISR_TC1ODIS_Pos       (4U)

+#define HRTIM_ODISR_TC1ODIS_Msk       (0x1UL << HRTIM_ODISR_TC1ODIS_Pos)       /*!< 0x00000010 */

+#define HRTIM_ODISR_TC1ODIS           HRTIM_ODISR_TC1ODIS_Msk                  /*!< Timer C Output 1 disable */

+#define HRTIM_ODISR_TC2ODIS_Pos       (5U)

+#define HRTIM_ODISR_TC2ODIS_Msk       (0x1UL << HRTIM_ODISR_TC2ODIS_Pos)       /*!< 0x00000020 */

+#define HRTIM_ODISR_TC2ODIS           HRTIM_ODISR_TC2ODIS_Msk                  /*!< Timer C Output 2 disable */

+#define HRTIM_ODISR_TD1ODIS_Pos       (6U)

+#define HRTIM_ODISR_TD1ODIS_Msk       (0x1UL << HRTIM_ODISR_TD1ODIS_Pos)       /*!< 0x00000040 */

+#define HRTIM_ODISR_TD1ODIS           HRTIM_ODISR_TD1ODIS_Msk                  /*!< Timer D Output 1 disable */

+#define HRTIM_ODISR_TD2ODIS_Pos       (7U)

+#define HRTIM_ODISR_TD2ODIS_Msk       (0x1UL << HRTIM_ODISR_TD2ODIS_Pos)       /*!< 0x00000080 */

+#define HRTIM_ODISR_TD2ODIS           HRTIM_ODISR_TD2ODIS_Msk                  /*!< Timer D Output 2 disable */

+#define HRTIM_ODISR_TE1ODIS_Pos       (8U)

+#define HRTIM_ODISR_TE1ODIS_Msk       (0x1UL << HRTIM_ODISR_TE1ODIS_Pos)       /*!< 0x00000100 */

+#define HRTIM_ODISR_TE1ODIS           HRTIM_ODISR_TE1ODIS_Msk                  /*!< Timer E Output 1 disable */

+#define HRTIM_ODISR_TE2ODIS_Pos       (9U)

+#define HRTIM_ODISR_TE2ODIS_Msk       (0x1UL << HRTIM_ODISR_TE2ODIS_Pos)       /*!< 0x00000200 */

+#define HRTIM_ODISR_TE2ODIS           HRTIM_ODISR_TE2ODIS_Msk                  /*!< Timer E Output 2 disable */

+

+/**** Bit definition for Common HRTIM Timer output disable status register *****/

+#define HRTIM_ODSR_TA1ODS_Pos         (0U)

+#define HRTIM_ODSR_TA1ODS_Msk         (0x1UL << HRTIM_ODSR_TA1ODS_Pos)         /*!< 0x00000001 */

+#define HRTIM_ODSR_TA1ODS             HRTIM_ODSR_TA1ODS_Msk                    /*!< Timer A Output 1 disable status */

+#define HRTIM_ODSR_TA2ODS_Pos         (1U)

+#define HRTIM_ODSR_TA2ODS_Msk         (0x1UL << HRTIM_ODSR_TA2ODS_Pos)         /*!< 0x00000002 */

+#define HRTIM_ODSR_TA2ODS             HRTIM_ODSR_TA2ODS_Msk                    /*!< Timer A Output 2 disable status */

+#define HRTIM_ODSR_TB1ODS_Pos         (2U)

+#define HRTIM_ODSR_TB1ODS_Msk         (0x1UL << HRTIM_ODSR_TB1ODS_Pos)         /*!< 0x00000004 */

+#define HRTIM_ODSR_TB1ODS             HRTIM_ODSR_TB1ODS_Msk                    /*!< Timer B Output 1 disable status */

+#define HRTIM_ODSR_TB2ODS_Pos         (3U)

+#define HRTIM_ODSR_TB2ODS_Msk         (0x1UL << HRTIM_ODSR_TB2ODS_Pos)         /*!< 0x00000008 */

+#define HRTIM_ODSR_TB2ODS             HRTIM_ODSR_TB2ODS_Msk                    /*!< Timer B Output 2 disable status */

+#define HRTIM_ODSR_TC1ODS_Pos         (4U)

+#define HRTIM_ODSR_TC1ODS_Msk         (0x1UL << HRTIM_ODSR_TC1ODS_Pos)         /*!< 0x00000010 */

+#define HRTIM_ODSR_TC1ODS             HRTIM_ODSR_TC1ODS_Msk                    /*!< Timer C Output 1 disable status */

+#define HRTIM_ODSR_TC2ODS_Pos         (5U)

+#define HRTIM_ODSR_TC2ODS_Msk         (0x1UL << HRTIM_ODSR_TC2ODS_Pos)         /*!< 0x00000020 */

+#define HRTIM_ODSR_TC2ODS             HRTIM_ODSR_TC2ODS_Msk                    /*!< Timer C Output 2 disable status */

+#define HRTIM_ODSR_TD1ODS_Pos         (6U)

+#define HRTIM_ODSR_TD1ODS_Msk         (0x1UL << HRTIM_ODSR_TD1ODS_Pos)         /*!< 0x00000040 */

+#define HRTIM_ODSR_TD1ODS             HRTIM_ODSR_TD1ODS_Msk                    /*!< Timer D Output 1 disable status */

+#define HRTIM_ODSR_TD2ODS_Pos         (7U)

+#define HRTIM_ODSR_TD2ODS_Msk         (0x1UL << HRTIM_ODSR_TD2ODS_Pos)         /*!< 0x00000080 */

+#define HRTIM_ODSR_TD2ODS             HRTIM_ODSR_TD2ODS_Msk                    /*!< Timer D Output 2 disable status */

+#define HRTIM_ODSR_TE1ODS_Pos         (8U)

+#define HRTIM_ODSR_TE1ODS_Msk         (0x1UL << HRTIM_ODSR_TE1ODS_Pos)         /*!< 0x00000100 */

+#define HRTIM_ODSR_TE1ODS             HRTIM_ODSR_TE1ODS_Msk                    /*!< Timer E Output 1 disable status */

+#define HRTIM_ODSR_TE2ODS_Pos         (9U)

+#define HRTIM_ODSR_TE2ODS_Msk         (0x1UL << HRTIM_ODSR_TE2ODS_Pos)         /*!< 0x00000200 */

+#define HRTIM_ODSR_TE2ODS             HRTIM_ODSR_TE2ODS_Msk                    /*!< Timer E Output 2 disable status */

+

+/**** Bit definition for Common HRTIM Timer Burst mode control register ********/

+#define HRTIM_BMCR_BME_Pos            (0U)

+#define HRTIM_BMCR_BME_Msk            (0x1UL << HRTIM_BMCR_BME_Pos)            /*!< 0x00000001 */

+#define HRTIM_BMCR_BME                HRTIM_BMCR_BME_Msk                       /*!< Burst mode enbale */

+#define HRTIM_BMCR_BMOM_Pos           (1U)

+#define HRTIM_BMCR_BMOM_Msk           (0x1UL << HRTIM_BMCR_BMOM_Pos)           /*!< 0x00000002 */

+#define HRTIM_BMCR_BMOM               HRTIM_BMCR_BMOM_Msk                      /*!< Burst mode operating mode */

+#define HRTIM_BMCR_BMCLK_Pos          (2U)

+#define HRTIM_BMCR_BMCLK_Msk          (0xFUL << HRTIM_BMCR_BMCLK_Pos)          /*!< 0x0000003C */

+#define HRTIM_BMCR_BMCLK              HRTIM_BMCR_BMCLK_Msk                     /*!< Burst mode clock source */

+#define HRTIM_BMCR_BMCLK_0            (0x1UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000004 */

+#define HRTIM_BMCR_BMCLK_1            (0x2UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000008 */

+#define HRTIM_BMCR_BMCLK_2            (0x4UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000010 */

+#define HRTIM_BMCR_BMCLK_3            (0x8UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000020 */

+#define HRTIM_BMCR_BMPRSC_Pos         (6U)

+#define HRTIM_BMCR_BMPRSC_Msk         (0xFUL << HRTIM_BMCR_BMPRSC_Pos)         /*!< 0x000003C0 */

+#define HRTIM_BMCR_BMPRSC             HRTIM_BMCR_BMPRSC_Msk                    /*!< Burst mode prescaler */

+#define HRTIM_BMCR_BMPRSC_0           (0x1UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000040 */

+#define HRTIM_BMCR_BMPRSC_1           (0x2UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000080 */

+#define HRTIM_BMCR_BMPRSC_2           (0x4UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000100 */

+#define HRTIM_BMCR_BMPRSC_3           (0x8UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000200 */

+#define HRTIM_BMCR_BMPREN_Pos         (10U)

+#define HRTIM_BMCR_BMPREN_Msk         (0x1UL << HRTIM_BMCR_BMPREN_Pos)         /*!< 0x00000400 */

+#define HRTIM_BMCR_BMPREN             HRTIM_BMCR_BMPREN_Msk                    /*!< Burst mode Preload bit */

+#define HRTIM_BMCR_MTBM_Pos           (16U)

+#define HRTIM_BMCR_MTBM_Msk           (0x1UL << HRTIM_BMCR_MTBM_Pos)           /*!< 0x00010000 */

+#define HRTIM_BMCR_MTBM               HRTIM_BMCR_MTBM_Msk                      /*!< Master Timer Burst mode */

+#define HRTIM_BMCR_TABM_Pos           (17U)

+#define HRTIM_BMCR_TABM_Msk           (0x1UL << HRTIM_BMCR_TABM_Pos)           /*!< 0x00020000 */

+#define HRTIM_BMCR_TABM               HRTIM_BMCR_TABM_Msk                      /*!< Timer A Burst mode */

+#define HRTIM_BMCR_TBBM_Pos           (18U)

+#define HRTIM_BMCR_TBBM_Msk           (0x1UL << HRTIM_BMCR_TBBM_Pos)           /*!< 0x00040000 */

+#define HRTIM_BMCR_TBBM               HRTIM_BMCR_TBBM_Msk                      /*!< Timer B Burst mode */

+#define HRTIM_BMCR_TCBM_Pos           (19U)

+#define HRTIM_BMCR_TCBM_Msk           (0x1UL << HRTIM_BMCR_TCBM_Pos)           /*!< 0x00080000 */

+#define HRTIM_BMCR_TCBM               HRTIM_BMCR_TCBM_Msk                      /*!< Timer C Burst mode */

+#define HRTIM_BMCR_TDBM_Pos           (20U)

+#define HRTIM_BMCR_TDBM_Msk           (0x1UL << HRTIM_BMCR_TDBM_Pos)           /*!< 0x00100000 */

+#define HRTIM_BMCR_TDBM               HRTIM_BMCR_TDBM_Msk                      /*!< Timer D Burst mode */

+#define HRTIM_BMCR_TEBM_Pos           (21U)

+#define HRTIM_BMCR_TEBM_Msk           (0x1UL << HRTIM_BMCR_TEBM_Pos)           /*!< 0x00200000 */

+#define HRTIM_BMCR_TEBM               HRTIM_BMCR_TEBM_Msk                      /*!< Timer E Burst mode */

+#define HRTIM_BMCR_BMSTAT_Pos         (31U)

+#define HRTIM_BMCR_BMSTAT_Msk         (0x1UL << HRTIM_BMCR_BMSTAT_Pos)         /*!< 0x80000000 */

+#define HRTIM_BMCR_BMSTAT             HRTIM_BMCR_BMSTAT_Msk                    /*!< Burst mode status */

+

+/**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/

+#define HRTIM_BMTRGR_SW_Pos           (0U)

+#define HRTIM_BMTRGR_SW_Msk           (0x1UL << HRTIM_BMTRGR_SW_Pos)           /*!< 0x00000001 */

+#define HRTIM_BMTRGR_SW               HRTIM_BMTRGR_SW_Msk                      /*!< Software start */

+#define HRTIM_BMTRGR_MSTRST_Pos       (1U)

+#define HRTIM_BMTRGR_MSTRST_Msk       (0x1UL << HRTIM_BMTRGR_MSTRST_Pos)       /*!< 0x00000002 */

+#define HRTIM_BMTRGR_MSTRST           HRTIM_BMTRGR_MSTRST_Msk                  /*!<  Master reset */

+#define HRTIM_BMTRGR_MSTREP_Pos       (2U)

+#define HRTIM_BMTRGR_MSTREP_Msk       (0x1UL << HRTIM_BMTRGR_MSTREP_Pos)       /*!< 0x00000004 */

+#define HRTIM_BMTRGR_MSTREP           HRTIM_BMTRGR_MSTREP_Msk                  /*!<  Master repetition */

+#define HRTIM_BMTRGR_MSTCMP1_Pos      (3U)

+#define HRTIM_BMTRGR_MSTCMP1_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos)      /*!< 0x00000008 */

+#define HRTIM_BMTRGR_MSTCMP1          HRTIM_BMTRGR_MSTCMP1_Msk                 /*!<  Master compare 1 */

+#define HRTIM_BMTRGR_MSTCMP2_Pos      (4U)

+#define HRTIM_BMTRGR_MSTCMP2_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos)      /*!< 0x00000010 */

+#define HRTIM_BMTRGR_MSTCMP2          HRTIM_BMTRGR_MSTCMP2_Msk                 /*!< Master compare 2  */

+#define HRTIM_BMTRGR_MSTCMP3_Pos      (5U)

+#define HRTIM_BMTRGR_MSTCMP3_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos)      /*!< 0x00000020 */

+#define HRTIM_BMTRGR_MSTCMP3          HRTIM_BMTRGR_MSTCMP3_Msk                 /*!< Master compare 3 */

+#define HRTIM_BMTRGR_MSTCMP4_Pos      (6U)

+#define HRTIM_BMTRGR_MSTCMP4_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos)      /*!< 0x00000040 */

+#define HRTIM_BMTRGR_MSTCMP4          HRTIM_BMTRGR_MSTCMP4_Msk                 /*!< Master compare 4 */

+#define HRTIM_BMTRGR_TARST_Pos        (7U)

+#define HRTIM_BMTRGR_TARST_Msk        (0x1UL << HRTIM_BMTRGR_TARST_Pos)        /*!< 0x00000080 */

+#define HRTIM_BMTRGR_TARST            HRTIM_BMTRGR_TARST_Msk                   /*!< Timer A reset  */

+#define HRTIM_BMTRGR_TAREP_Pos        (8U)

+#define HRTIM_BMTRGR_TAREP_Msk        (0x1UL << HRTIM_BMTRGR_TAREP_Pos)        /*!< 0x00000100 */

+#define HRTIM_BMTRGR_TAREP            HRTIM_BMTRGR_TAREP_Msk                   /*!< Timer A repetition  */

+#define HRTIM_BMTRGR_TACMP1_Pos       (9U)

+#define HRTIM_BMTRGR_TACMP1_Msk       (0x1UL << HRTIM_BMTRGR_TACMP1_Pos)       /*!< 0x00000200 */

+#define HRTIM_BMTRGR_TACMP1           HRTIM_BMTRGR_TACMP1_Msk                  /*!< Timer A compare 1  */

+#define HRTIM_BMTRGR_TACMP2_Pos       (10U)

+#define HRTIM_BMTRGR_TACMP2_Msk       (0x1UL << HRTIM_BMTRGR_TACMP2_Pos)       /*!< 0x00000400 */

+#define HRTIM_BMTRGR_TACMP2           HRTIM_BMTRGR_TACMP2_Msk                  /*!< Timer A compare 2  */

+#define HRTIM_BMTRGR_TBRST_Pos        (11U)

+#define HRTIM_BMTRGR_TBRST_Msk        (0x1UL << HRTIM_BMTRGR_TBRST_Pos)        /*!< 0x00000800 */

+#define HRTIM_BMTRGR_TBRST            HRTIM_BMTRGR_TBRST_Msk                   /*!< Timer B reset  */

+#define HRTIM_BMTRGR_TBREP_Pos        (12U)

+#define HRTIM_BMTRGR_TBREP_Msk        (0x1UL << HRTIM_BMTRGR_TBREP_Pos)        /*!< 0x00001000 */

+#define HRTIM_BMTRGR_TBREP            HRTIM_BMTRGR_TBREP_Msk                   /*!< Timer B repetition  */

+#define HRTIM_BMTRGR_TBCMP1_Pos       (13U)

+#define HRTIM_BMTRGR_TBCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos)       /*!< 0x00002000 */

+#define HRTIM_BMTRGR_TBCMP1           HRTIM_BMTRGR_TBCMP1_Msk                  /*!< Timer B compare 1 */

+#define HRTIM_BMTRGR_TBCMP2_Pos       (14U)

+#define HRTIM_BMTRGR_TBCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos)       /*!< 0x00004000 */

+#define HRTIM_BMTRGR_TBCMP2           HRTIM_BMTRGR_TBCMP2_Msk                  /*!< Timer B compare 2 */

+#define HRTIM_BMTRGR_TCRST_Pos        (15U)

+#define HRTIM_BMTRGR_TCRST_Msk        (0x1UL << HRTIM_BMTRGR_TCRST_Pos)        /*!< 0x00008000 */

+#define HRTIM_BMTRGR_TCRST            HRTIM_BMTRGR_TCRST_Msk                   /*!< Timer C reset  */

+#define HRTIM_BMTRGR_TCREP_Pos        (16U)

+#define HRTIM_BMTRGR_TCREP_Msk        (0x1UL << HRTIM_BMTRGR_TCREP_Pos)        /*!< 0x00010000 */

+#define HRTIM_BMTRGR_TCREP            HRTIM_BMTRGR_TCREP_Msk                   /*!< Timer C repetition */

+#define HRTIM_BMTRGR_TCCMP1_Pos       (17U)

+#define HRTIM_BMTRGR_TCCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos)       /*!< 0x00020000 */

+#define HRTIM_BMTRGR_TCCMP1           HRTIM_BMTRGR_TCCMP1_Msk                  /*!< Timer C compare 1 */

+#define HRTIM_BMTRGR_TCCMP2_Pos       (18U)

+#define HRTIM_BMTRGR_TCCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP2_Pos)       /*!< 0x00040000 */

+#define HRTIM_BMTRGR_TCCMP2           HRTIM_BMTRGR_TCCMP2_Msk                  /*!< Timer C compare 2 */

+#define HRTIM_BMTRGR_TDRST_Pos        (19U)

+#define HRTIM_BMTRGR_TDRST_Msk        (0x1UL << HRTIM_BMTRGR_TDRST_Pos)        /*!< 0x00080000 */

+#define HRTIM_BMTRGR_TDRST            HRTIM_BMTRGR_TDRST_Msk                   /*!< Timer D reset  */

+#define HRTIM_BMTRGR_TDREP_Pos        (20U)

+#define HRTIM_BMTRGR_TDREP_Msk        (0x1UL << HRTIM_BMTRGR_TDREP_Pos)        /*!< 0x00100000 */

+#define HRTIM_BMTRGR_TDREP            HRTIM_BMTRGR_TDREP_Msk                   /*!< Timer D repetition  */

+#define HRTIM_BMTRGR_TDCMP1_Pos       (21U)

+#define HRTIM_BMTRGR_TDCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP1_Pos)       /*!< 0x00200000 */

+#define HRTIM_BMTRGR_TDCMP1           HRTIM_BMTRGR_TDCMP1_Msk                  /*!< Timer D compare 1 */

+#define HRTIM_BMTRGR_TDCMP2_Pos       (22U)

+#define HRTIM_BMTRGR_TDCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos)       /*!< 0x00400000 */

+#define HRTIM_BMTRGR_TDCMP2           HRTIM_BMTRGR_TDCMP2_Msk                  /*!< Timer D compare 2 */

+#define HRTIM_BMTRGR_TERST_Pos        (23U)

+#define HRTIM_BMTRGR_TERST_Msk        (0x1UL << HRTIM_BMTRGR_TERST_Pos)        /*!< 0x00800000 */

+#define HRTIM_BMTRGR_TERST            HRTIM_BMTRGR_TERST_Msk                   /*!< Timer E reset  */

+#define HRTIM_BMTRGR_TEREP_Pos        (24U)

+#define HRTIM_BMTRGR_TEREP_Msk        (0x1UL << HRTIM_BMTRGR_TEREP_Pos)        /*!< 0x01000000 */

+#define HRTIM_BMTRGR_TEREP            HRTIM_BMTRGR_TEREP_Msk                   /*!< Timer E repetition  */

+#define HRTIM_BMTRGR_TECMP1_Pos       (25U)

+#define HRTIM_BMTRGR_TECMP1_Msk       (0x1UL << HRTIM_BMTRGR_TECMP1_Pos)       /*!< 0x02000000 */

+#define HRTIM_BMTRGR_TECMP1           HRTIM_BMTRGR_TECMP1_Msk                  /*!< Timer E compare 1 */

+#define HRTIM_BMTRGR_TECMP2_Pos       (26U)

+#define HRTIM_BMTRGR_TECMP2_Msk       (0x1UL << HRTIM_BMTRGR_TECMP2_Pos)       /*!< 0x04000000 */

+#define HRTIM_BMTRGR_TECMP2           HRTIM_BMTRGR_TECMP2_Msk                  /*!< Timer E compare 2 */

+#define HRTIM_BMTRGR_TAEEV7_Pos       (27U)

+#define HRTIM_BMTRGR_TAEEV7_Msk       (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos)       /*!< 0x08000000 */

+#define HRTIM_BMTRGR_TAEEV7           HRTIM_BMTRGR_TAEEV7_Msk                  /*!< Timer A period following External Event7  */

+#define HRTIM_BMTRGR_TDEEV8_Pos       (28U)

+#define HRTIM_BMTRGR_TDEEV8_Msk       (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos)       /*!< 0x10000000 */

+#define HRTIM_BMTRGR_TDEEV8           HRTIM_BMTRGR_TDEEV8_Msk                  /*!< Timer D period following External Event8  */

+#define HRTIM_BMTRGR_EEV7_Pos         (29U)

+#define HRTIM_BMTRGR_EEV7_Msk         (0x1UL << HRTIM_BMTRGR_EEV7_Pos)         /*!< 0x20000000 */

+#define HRTIM_BMTRGR_EEV7             HRTIM_BMTRGR_EEV7_Msk                    /*!< External Event 7 */

+#define HRTIM_BMTRGR_EEV8_Pos         (30U)

+#define HRTIM_BMTRGR_EEV8_Msk         (0x1UL << HRTIM_BMTRGR_EEV8_Pos)         /*!< 0x40000000 */

+#define HRTIM_BMTRGR_EEV8             HRTIM_BMTRGR_EEV8_Msk                    /*!< External Event 8 */

+#define HRTIM_BMTRGR_OCHPEV_Pos       (31U)

+#define HRTIM_BMTRGR_OCHPEV_Msk       (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos)       /*!< 0x80000000 */

+#define HRTIM_BMTRGR_OCHPEV           HRTIM_BMTRGR_OCHPEV_Msk                  /*!< on-chip Event */

+

+/*******************  Bit definition for HRTIM_BMCMPR register  ***************/

+#define HRTIM_BMCMPR_BMCMPR_Pos       (0U)

+#define HRTIM_BMCMPR_BMCMPR_Msk       (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_BMCMPR_BMCMPR           HRTIM_BMCMPR_BMCMPR_Msk                  /*!<!<Burst Compare Value */

+

+/*******************  Bit definition for HRTIM_BMPER register  ****************/

+#define HRTIM_BMPER_BMPER_Pos         (0U)

+#define HRTIM_BMPER_BMPER_Msk         (0xFFFFUL << HRTIM_BMPER_BMPER_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_BMPER_BMPER             HRTIM_BMPER_BMPER_Msk                    /*!<!<Burst period Value */

+

+/*******************  Bit definition for HRTIM_EECR1 register  ****************/

+#define HRTIM_EECR1_EE1SRC_Pos        (0U)

+#define HRTIM_EECR1_EE1SRC_Msk        (0x3UL << HRTIM_EECR1_EE1SRC_Pos)        /*!< 0x00000003 */

+#define HRTIM_EECR1_EE1SRC            HRTIM_EECR1_EE1SRC_Msk                   /*!< External event 1 source */

+#define HRTIM_EECR1_EE1SRC_0          (0x1UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000001 */

+#define HRTIM_EECR1_EE1SRC_1          (0x2UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000002 */

+#define HRTIM_EECR1_EE1POL_Pos        (2U)

+#define HRTIM_EECR1_EE1POL_Msk        (0x1UL << HRTIM_EECR1_EE1POL_Pos)        /*!< 0x00000004 */

+#define HRTIM_EECR1_EE1POL            HRTIM_EECR1_EE1POL_Msk                   /*!< External event 1 Polarity */

+#define HRTIM_EECR1_EE1SNS_Pos        (3U)

+#define HRTIM_EECR1_EE1SNS_Msk        (0x3UL << HRTIM_EECR1_EE1SNS_Pos)        /*!< 0x00000018 */

+#define HRTIM_EECR1_EE1SNS            HRTIM_EECR1_EE1SNS_Msk                   /*!< External event 1 sensitivity */

+#define HRTIM_EECR1_EE1SNS_0          (0x1UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000008 */

+#define HRTIM_EECR1_EE1SNS_1          (0x2UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000010 */

+#define HRTIM_EECR1_EE1FAST_Pos       (5U)

+#define HRTIM_EECR1_EE1FAST_Msk       (0x1UL << HRTIM_EECR1_EE1FAST_Pos)       /*!< 0x00000020 */

+#define HRTIM_EECR1_EE1FAST           HRTIM_EECR1_EE1FAST_Msk                  /*!< External event 1 Fast mode */

+

+#define HRTIM_EECR1_EE2SRC_Pos        (6U)

+#define HRTIM_EECR1_EE2SRC_Msk        (0x3UL << HRTIM_EECR1_EE2SRC_Pos)        /*!< 0x000000C0 */

+#define HRTIM_EECR1_EE2SRC            HRTIM_EECR1_EE2SRC_Msk                   /*!< External event 2 source */

+#define HRTIM_EECR1_EE2SRC_0          (0x1UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000040 */

+#define HRTIM_EECR1_EE2SRC_1          (0x2UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000080 */

+#define HRTIM_EECR1_EE2POL_Pos        (8U)

+#define HRTIM_EECR1_EE2POL_Msk        (0x1UL << HRTIM_EECR1_EE2POL_Pos)        /*!< 0x00000100 */

+#define HRTIM_EECR1_EE2POL            HRTIM_EECR1_EE2POL_Msk                   /*!< External event 2 Polarity */

+#define HRTIM_EECR1_EE2SNS_Pos        (9U)

+#define HRTIM_EECR1_EE2SNS_Msk        (0x3UL << HRTIM_EECR1_EE2SNS_Pos)        /*!< 0x00000600 */

+#define HRTIM_EECR1_EE2SNS            HRTIM_EECR1_EE2SNS_Msk                   /*!< External event 2 sensitivity */

+#define HRTIM_EECR1_EE2SNS_0          (0x1UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000200 */

+#define HRTIM_EECR1_EE2SNS_1          (0x2UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000400 */

+#define HRTIM_EECR1_EE2FAST_Pos       (11U)

+#define HRTIM_EECR1_EE2FAST_Msk       (0x1UL << HRTIM_EECR1_EE2FAST_Pos)       /*!< 0x00000800 */

+#define HRTIM_EECR1_EE2FAST           HRTIM_EECR1_EE2FAST_Msk                  /*!< External event 2 Fast mode */

+

+#define HRTIM_EECR1_EE3SRC_Pos        (12U)

+#define HRTIM_EECR1_EE3SRC_Msk        (0x3UL << HRTIM_EECR1_EE3SRC_Pos)        /*!< 0x00003000 */

+#define HRTIM_EECR1_EE3SRC            HRTIM_EECR1_EE3SRC_Msk                   /*!< External event 3 source */

+#define HRTIM_EECR1_EE3SRC_0          (0x1UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00001000 */

+#define HRTIM_EECR1_EE3SRC_1          (0x2UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00002000 */

+#define HRTIM_EECR1_EE3POL_Pos        (14U)

+#define HRTIM_EECR1_EE3POL_Msk        (0x1UL << HRTIM_EECR1_EE3POL_Pos)        /*!< 0x00004000 */

+#define HRTIM_EECR1_EE3POL            HRTIM_EECR1_EE3POL_Msk                   /*!< External event 3 Polarity */

+#define HRTIM_EECR1_EE3SNS_Pos        (15U)

+#define HRTIM_EECR1_EE3SNS_Msk        (0x3UL << HRTIM_EECR1_EE3SNS_Pos)        /*!< 0x00018000 */

+#define HRTIM_EECR1_EE3SNS            HRTIM_EECR1_EE3SNS_Msk                   /*!< External event 3 sensitivity */

+#define HRTIM_EECR1_EE3SNS_0          (0x1UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00008000 */

+#define HRTIM_EECR1_EE3SNS_1          (0x2UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00010000 */

+#define HRTIM_EECR1_EE3FAST_Pos       (17U)

+#define HRTIM_EECR1_EE3FAST_Msk       (0x1UL << HRTIM_EECR1_EE3FAST_Pos)       /*!< 0x00020000 */

+#define HRTIM_EECR1_EE3FAST           HRTIM_EECR1_EE3FAST_Msk                  /*!< External event 3 Fast mode */

+

+#define HRTIM_EECR1_EE4SRC_Pos        (18U)

+#define HRTIM_EECR1_EE4SRC_Msk        (0x3UL << HRTIM_EECR1_EE4SRC_Pos)        /*!< 0x000C0000 */

+#define HRTIM_EECR1_EE4SRC            HRTIM_EECR1_EE4SRC_Msk                   /*!< External event 4 source */

+#define HRTIM_EECR1_EE4SRC_0          (0x1UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00040000 */

+#define HRTIM_EECR1_EE4SRC_1          (0x2UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00080000 */

+#define HRTIM_EECR1_EE4POL_Pos        (20U)

+#define HRTIM_EECR1_EE4POL_Msk        (0x1UL << HRTIM_EECR1_EE4POL_Pos)        /*!< 0x00100000 */

+#define HRTIM_EECR1_EE4POL            HRTIM_EECR1_EE4POL_Msk                   /*!< External event 4 Polarity */

+#define HRTIM_EECR1_EE4SNS_Pos        (21U)

+#define HRTIM_EECR1_EE4SNS_Msk        (0x3UL << HRTIM_EECR1_EE4SNS_Pos)        /*!< 0x00600000 */

+#define HRTIM_EECR1_EE4SNS            HRTIM_EECR1_EE4SNS_Msk                   /*!< External event 4 sensitivity */

+#define HRTIM_EECR1_EE4SNS_0          (0x1UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00200000 */

+#define HRTIM_EECR1_EE4SNS_1          (0x2UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00400000 */

+#define HRTIM_EECR1_EE4FAST_Pos       (23U)

+#define HRTIM_EECR1_EE4FAST_Msk       (0x1UL << HRTIM_EECR1_EE4FAST_Pos)       /*!< 0x00800000 */

+#define HRTIM_EECR1_EE4FAST           HRTIM_EECR1_EE4FAST_Msk                  /*!< External event 4 Fast mode */

+

+#define HRTIM_EECR1_EE5SRC_Pos        (24U)

+#define HRTIM_EECR1_EE5SRC_Msk        (0x3UL << HRTIM_EECR1_EE5SRC_Pos)        /*!< 0x03000000 */

+#define HRTIM_EECR1_EE5SRC            HRTIM_EECR1_EE5SRC_Msk                   /*!< External event 5 source */

+#define HRTIM_EECR1_EE5SRC_0          (0x1UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x01000000 */

+#define HRTIM_EECR1_EE5SRC_1          (0x2UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x02000000 */

+#define HRTIM_EECR1_EE5POL_Pos        (26U)

+#define HRTIM_EECR1_EE5POL_Msk        (0x1UL << HRTIM_EECR1_EE5POL_Pos)        /*!< 0x04000000 */

+#define HRTIM_EECR1_EE5POL            HRTIM_EECR1_EE5POL_Msk                   /*!< External event 5 Polarity */

+#define HRTIM_EECR1_EE5SNS_Pos        (27U)

+#define HRTIM_EECR1_EE5SNS_Msk        (0x3UL << HRTIM_EECR1_EE5SNS_Pos)        /*!< 0x18000000 */

+#define HRTIM_EECR1_EE5SNS            HRTIM_EECR1_EE5SNS_Msk                   /*!< External event 5 sensitivity */

+#define HRTIM_EECR1_EE5SNS_0          (0x1UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x08000000 */

+#define HRTIM_EECR1_EE5SNS_1          (0x2UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x10000000 */

+#define HRTIM_EECR1_EE5FAST_Pos       (29U)

+#define HRTIM_EECR1_EE5FAST_Msk       (0x1UL << HRTIM_EECR1_EE5FAST_Pos)       /*!< 0x20000000 */

+#define HRTIM_EECR1_EE5FAST           HRTIM_EECR1_EE5FAST_Msk                  /*!< External event 5 Fast mode */

+

+/*******************  Bit definition for HRTIM_EECR2 register  ****************/

+#define HRTIM_EECR2_EE6SRC_Pos        (0U)

+#define HRTIM_EECR2_EE6SRC_Msk        (0x3UL << HRTIM_EECR2_EE6SRC_Pos)        /*!< 0x00000003 */

+#define HRTIM_EECR2_EE6SRC            HRTIM_EECR2_EE6SRC_Msk                   /*!< External event 6 source */

+#define HRTIM_EECR2_EE6SRC_0          (0x1UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000001 */

+#define HRTIM_EECR2_EE6SRC_1          (0x2UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000002 */

+#define HRTIM_EECR2_EE6POL_Pos        (2U)

+#define HRTIM_EECR2_EE6POL_Msk        (0x1UL << HRTIM_EECR2_EE6POL_Pos)        /*!< 0x00000004 */

+#define HRTIM_EECR2_EE6POL            HRTIM_EECR2_EE6POL_Msk                   /*!< External event 6 Polarity */

+#define HRTIM_EECR2_EE6SNS_Pos        (3U)

+#define HRTIM_EECR2_EE6SNS_Msk        (0x3UL << HRTIM_EECR2_EE6SNS_Pos)        /*!< 0x00000018 */

+#define HRTIM_EECR2_EE6SNS            HRTIM_EECR2_EE6SNS_Msk                   /*!< External event 6 sensitivity */

+#define HRTIM_EECR2_EE6SNS_0          (0x1UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000008 */

+#define HRTIM_EECR2_EE6SNS_1          (0x2UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000010 */

+

+#define HRTIM_EECR2_EE7SRC_Pos        (6U)

+#define HRTIM_EECR2_EE7SRC_Msk        (0x3UL << HRTIM_EECR2_EE7SRC_Pos)        /*!< 0x000000C0 */

+#define HRTIM_EECR2_EE7SRC            HRTIM_EECR2_EE7SRC_Msk                   /*!< External event 7 source */

+#define HRTIM_EECR2_EE7SRC_0          (0x1UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000040 */

+#define HRTIM_EECR2_EE7SRC_1          (0x2UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000080 */

+#define HRTIM_EECR2_EE7POL_Pos        (8U)

+#define HRTIM_EECR2_EE7POL_Msk        (0x1UL << HRTIM_EECR2_EE7POL_Pos)        /*!< 0x00000100 */

+#define HRTIM_EECR2_EE7POL            HRTIM_EECR2_EE7POL_Msk                   /*!< External event 7 Polarity */

+#define HRTIM_EECR2_EE7SNS_Pos        (9U)

+#define HRTIM_EECR2_EE7SNS_Msk        (0x3UL << HRTIM_EECR2_EE7SNS_Pos)        /*!< 0x00000600 */

+#define HRTIM_EECR2_EE7SNS            HRTIM_EECR2_EE7SNS_Msk                   /*!< External event 7 sensitivity */

+#define HRTIM_EECR2_EE7SNS_0          (0x1UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000200 */

+#define HRTIM_EECR2_EE7SNS_1          (0x2UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000400 */

+

+#define HRTIM_EECR2_EE8SRC_Pos        (12U)

+#define HRTIM_EECR2_EE8SRC_Msk        (0x3UL << HRTIM_EECR2_EE8SRC_Pos)        /*!< 0x00003000 */

+#define HRTIM_EECR2_EE8SRC            HRTIM_EECR2_EE8SRC_Msk                   /*!< External event 8 source */

+#define HRTIM_EECR2_EE8SRC_0          (0x1UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00001000 */

+#define HRTIM_EECR2_EE8SRC_1          (0x2UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00002000 */

+#define HRTIM_EECR2_EE8POL_Pos        (14U)

+#define HRTIM_EECR2_EE8POL_Msk        (0x1UL << HRTIM_EECR2_EE8POL_Pos)        /*!< 0x00004000 */

+#define HRTIM_EECR2_EE8POL            HRTIM_EECR2_EE8POL_Msk                   /*!< External event 8 Polarity */

+#define HRTIM_EECR2_EE8SNS_Pos        (15U)

+#define HRTIM_EECR2_EE8SNS_Msk        (0x3UL << HRTIM_EECR2_EE8SNS_Pos)        /*!< 0x00018000 */

+#define HRTIM_EECR2_EE8SNS            HRTIM_EECR2_EE8SNS_Msk                   /*!< External event 8 sensitivity */

+#define HRTIM_EECR2_EE8SNS_0          (0x1UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00008000 */

+#define HRTIM_EECR2_EE8SNS_1          (0x2UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00010000 */

+

+#define HRTIM_EECR2_EE9SRC_Pos        (18U)

+#define HRTIM_EECR2_EE9SRC_Msk        (0x3UL << HRTIM_EECR2_EE9SRC_Pos)        /*!< 0x000C0000 */

+#define HRTIM_EECR2_EE9SRC            HRTIM_EECR2_EE9SRC_Msk                   /*!< External event 9 source */

+#define HRTIM_EECR2_EE9SRC_0          (0x1UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00040000 */

+#define HRTIM_EECR2_EE9SRC_1          (0x2UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00080000 */

+#define HRTIM_EECR2_EE9POL_Pos        (20U)

+#define HRTIM_EECR2_EE9POL_Msk        (0x1UL << HRTIM_EECR2_EE9POL_Pos)        /*!< 0x00100000 */

+#define HRTIM_EECR2_EE9POL            HRTIM_EECR2_EE9POL_Msk                   /*!< External event 9 Polarity */

+#define HRTIM_EECR2_EE9SNS_Pos        (21U)

+#define HRTIM_EECR2_EE9SNS_Msk        (0x3UL << HRTIM_EECR2_EE9SNS_Pos)        /*!< 0x00600000 */

+#define HRTIM_EECR2_EE9SNS            HRTIM_EECR2_EE9SNS_Msk                   /*!< External event 9 sensitivity */

+#define HRTIM_EECR2_EE9SNS_0          (0x1UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00200000 */

+#define HRTIM_EECR2_EE9SNS_1          (0x2UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00400000 */

+

+#define HRTIM_EECR2_EE10SRC_Pos       (24U)

+#define HRTIM_EECR2_EE10SRC_Msk       (0x3UL << HRTIM_EECR2_EE10SRC_Pos)       /*!< 0x03000000 */

+#define HRTIM_EECR2_EE10SRC           HRTIM_EECR2_EE10SRC_Msk                  /*!< External event 10 source */

+#define HRTIM_EECR2_EE10SRC_0         (0x1UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x01000000 */

+#define HRTIM_EECR2_EE10SRC_1         (0x2UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x02000000 */

+#define HRTIM_EECR2_EE10POL_Pos       (26U)

+#define HRTIM_EECR2_EE10POL_Msk       (0x1UL << HRTIM_EECR2_EE10POL_Pos)       /*!< 0x04000000 */

+#define HRTIM_EECR2_EE10POL           HRTIM_EECR2_EE10POL_Msk                  /*!< External event 10 Polarity */

+#define HRTIM_EECR2_EE10SNS_Pos       (27U)

+#define HRTIM_EECR2_EE10SNS_Msk       (0x3UL << HRTIM_EECR2_EE10SNS_Pos)       /*!< 0x18000000 */

+#define HRTIM_EECR2_EE10SNS           HRTIM_EECR2_EE10SNS_Msk                  /*!< External event 10 sensitivity */

+#define HRTIM_EECR2_EE10SNS_0         (0x1UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x08000000 */

+#define HRTIM_EECR2_EE10SNS_1         (0x2UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x10000000 */

+

+/*******************  Bit definition for HRTIM_EECR3 register  ****************/

+#define HRTIM_EECR3_EE6F_Pos          (0U)

+#define HRTIM_EECR3_EE6F_Msk          (0xFUL << HRTIM_EECR3_EE6F_Pos)          /*!< 0x0000000F */

+#define HRTIM_EECR3_EE6F              HRTIM_EECR3_EE6F_Msk                     /*!< External event 6 filter */

+#define HRTIM_EECR3_EE6F_0            (0x1UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000001 */

+#define HRTIM_EECR3_EE6F_1            (0x2UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000002 */

+#define HRTIM_EECR3_EE6F_2            (0x4UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000004 */

+#define HRTIM_EECR3_EE6F_3            (0x8UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000008 */

+#define HRTIM_EECR3_EE7F_Pos          (6U)

+#define HRTIM_EECR3_EE7F_Msk          (0xFUL << HRTIM_EECR3_EE7F_Pos)          /*!< 0x000003C0 */

+#define HRTIM_EECR3_EE7F              HRTIM_EECR3_EE7F_Msk                     /*!< External event 7 filter */

+#define HRTIM_EECR3_EE7F_0            (0x1UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000040 */

+#define HRTIM_EECR3_EE7F_1            (0x2UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000080 */

+#define HRTIM_EECR3_EE7F_2            (0x4UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000100 */

+#define HRTIM_EECR3_EE7F_3            (0x8UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000200 */

+#define HRTIM_EECR3_EE8F_Pos          (12U)

+#define HRTIM_EECR3_EE8F_Msk          (0xFUL << HRTIM_EECR3_EE8F_Pos)          /*!< 0x0000F000 */

+#define HRTIM_EECR3_EE8F              HRTIM_EECR3_EE8F_Msk                     /*!< External event 8 filter */

+#define HRTIM_EECR3_EE8F_0            (0x1UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00001000 */

+#define HRTIM_EECR3_EE8F_1            (0x2UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00002000 */

+#define HRTIM_EECR3_EE8F_2            (0x4UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00004000 */

+#define HRTIM_EECR3_EE8F_3            (0x8UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00008000 */

+#define HRTIM_EECR3_EE9F_Pos          (18U)

+#define HRTIM_EECR3_EE9F_Msk          (0xFUL << HRTIM_EECR3_EE9F_Pos)          /*!< 0x003C0000 */

+#define HRTIM_EECR3_EE9F              HRTIM_EECR3_EE9F_Msk                     /*!< External event 9 filter */

+#define HRTIM_EECR3_EE9F_0            (0x1UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00040000 */

+#define HRTIM_EECR3_EE9F_1            (0x2UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00080000 */

+#define HRTIM_EECR3_EE9F_2            (0x4UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00100000 */

+#define HRTIM_EECR3_EE9F_3            (0x8UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00200000 */

+#define HRTIM_EECR3_EE10F_Pos         (24U)

+#define HRTIM_EECR3_EE10F_Msk         (0xFUL << HRTIM_EECR3_EE10F_Pos)         /*!< 0x0F000000 */

+#define HRTIM_EECR3_EE10F             HRTIM_EECR3_EE10F_Msk                    /*!< External event 10 filter */

+#define HRTIM_EECR3_EE10F_0           (0x1UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x01000000 */

+#define HRTIM_EECR3_EE10F_1           (0x2UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x02000000 */

+#define HRTIM_EECR3_EE10F_2           (0x4UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x04000000 */

+#define HRTIM_EECR3_EE10F_3           (0x8UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x08000000 */

+#define HRTIM_EECR3_EEVSD_Pos         (30U)

+#define HRTIM_EECR3_EEVSD_Msk         (0x3UL << HRTIM_EECR3_EEVSD_Pos)         /*!< 0xC0000000 */

+#define HRTIM_EECR3_EEVSD             HRTIM_EECR3_EEVSD_Msk                    /*!< External event sampling clock division */

+#define HRTIM_EECR3_EEVSD_0           (0x1UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x40000000 */

+#define HRTIM_EECR3_EEVSD_1           (0x2UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x80000000 */

+

+/*******************  Bit definition for HRTIM_ADC1R register  ****************/

+#define HRTIM_ADC1R_AD1MC1_Pos        (0U)

+#define HRTIM_ADC1R_AD1MC1_Msk        (0x1UL << HRTIM_ADC1R_AD1MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC1R_AD1MC1            HRTIM_ADC1R_AD1MC1_Msk                   /*!< ADC Trigger 1 on master compare 1 */

+#define HRTIM_ADC1R_AD1MC2_Pos        (1U)

+#define HRTIM_ADC1R_AD1MC2_Msk        (0x1UL << HRTIM_ADC1R_AD1MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC1R_AD1MC2            HRTIM_ADC1R_AD1MC2_Msk                   /*!< ADC Trigger 1 on master compare 2 */

+#define HRTIM_ADC1R_AD1MC3_Pos        (2U)

+#define HRTIM_ADC1R_AD1MC3_Msk        (0x1UL << HRTIM_ADC1R_AD1MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC1R_AD1MC3            HRTIM_ADC1R_AD1MC3_Msk                   /*!< ADC Trigger 1 on master compare 3 */

+#define HRTIM_ADC1R_AD1MC4_Pos        (3U)

+#define HRTIM_ADC1R_AD1MC4_Msk        (0x1UL << HRTIM_ADC1R_AD1MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC1R_AD1MC4            HRTIM_ADC1R_AD1MC4_Msk                   /*!< ADC Trigger 1 on master compare 4 */

+#define HRTIM_ADC1R_AD1MPER_Pos       (4U)

+#define HRTIM_ADC1R_AD1MPER_Msk       (0x1UL << HRTIM_ADC1R_AD1MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC1R_AD1MPER           HRTIM_ADC1R_AD1MPER_Msk                  /*!< ADC Trigger 1 on master period */

+#define HRTIM_ADC1R_AD1EEV1_Pos       (5U)

+#define HRTIM_ADC1R_AD1EEV1_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC1R_AD1EEV1           HRTIM_ADC1R_AD1EEV1_Msk                  /*!< ADC Trigger 1 on external event 1 */

+#define HRTIM_ADC1R_AD1EEV2_Pos       (6U)

+#define HRTIM_ADC1R_AD1EEV2_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC1R_AD1EEV2           HRTIM_ADC1R_AD1EEV2_Msk                  /*!< ADC Trigger 1 on external event 2 */

+#define HRTIM_ADC1R_AD1EEV3_Pos       (7U)

+#define HRTIM_ADC1R_AD1EEV3_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC1R_AD1EEV3           HRTIM_ADC1R_AD1EEV3_Msk                  /*!< ADC Trigger 1 on external event 3 */

+#define HRTIM_ADC1R_AD1EEV4_Pos       (8U)

+#define HRTIM_ADC1R_AD1EEV4_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC1R_AD1EEV4           HRTIM_ADC1R_AD1EEV4_Msk                  /*!< ADC Trigger 1 on external event 4 */

+#define HRTIM_ADC1R_AD1EEV5_Pos       (9U)

+#define HRTIM_ADC1R_AD1EEV5_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos)       /*!< 0x00000200 */

+#define HRTIM_ADC1R_AD1EEV5           HRTIM_ADC1R_AD1EEV5_Msk                  /*!< ADC Trigger 1 on external event 5 */

+#define HRTIM_ADC1R_AD1TAC2_Pos       (10U)

+#define HRTIM_ADC1R_AD1TAC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC1R_AD1TAC2           HRTIM_ADC1R_AD1TAC2_Msk                  /*!< ADC Trigger 1 on Timer A compare 2 */

+#define HRTIM_ADC1R_AD1TAC3_Pos       (11U)

+#define HRTIM_ADC1R_AD1TAC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC1R_AD1TAC3           HRTIM_ADC1R_AD1TAC3_Msk                  /*!< ADC Trigger 1 on Timer A compare 3 */

+#define HRTIM_ADC1R_AD1TAC4_Pos       (12U)

+#define HRTIM_ADC1R_AD1TAC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC1R_AD1TAC4           HRTIM_ADC1R_AD1TAC4_Msk                  /*!< ADC Trigger 1 on Timer A compare 4 */

+#define HRTIM_ADC1R_AD1TAPER_Pos      (13U)

+#define HRTIM_ADC1R_AD1TAPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC1R_AD1TAPER          HRTIM_ADC1R_AD1TAPER_Msk                 /*!< ADC Trigger 1 on Timer A period */

+#define HRTIM_ADC1R_AD1TARST_Pos      (14U)

+#define HRTIM_ADC1R_AD1TARST_Msk      (0x1UL << HRTIM_ADC1R_AD1TARST_Pos)      /*!< 0x00004000 */

+#define HRTIM_ADC1R_AD1TARST          HRTIM_ADC1R_AD1TARST_Msk                 /*!< ADC Trigger 1 on Timer A reset */

+#define HRTIM_ADC1R_AD1TBC2_Pos       (15U)

+#define HRTIM_ADC1R_AD1TBC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC2_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC1R_AD1TBC2           HRTIM_ADC1R_AD1TBC2_Msk                  /*!< ADC Trigger 1 on Timer B compare 2 */

+#define HRTIM_ADC1R_AD1TBC3_Pos       (16U)

+#define HRTIM_ADC1R_AD1TBC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC1R_AD1TBC3           HRTIM_ADC1R_AD1TBC3_Msk                  /*!< ADC Trigger 1 on Timer B compare 3 */

+#define HRTIM_ADC1R_AD1TBC4_Pos       (17U)

+#define HRTIM_ADC1R_AD1TBC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos)       /*!< 0x00020000 */

+#define HRTIM_ADC1R_AD1TBC4           HRTIM_ADC1R_AD1TBC4_Msk                  /*!< ADC Trigger 1 on Timer B compare 4 */

+#define HRTIM_ADC1R_AD1TBPER_Pos      (18U)

+#define HRTIM_ADC1R_AD1TBPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos)      /*!< 0x00040000 */

+#define HRTIM_ADC1R_AD1TBPER          HRTIM_ADC1R_AD1TBPER_Msk                 /*!< ADC Trigger 1 on Timer B period */

+#define HRTIM_ADC1R_AD1TBRST_Pos      (19U)

+#define HRTIM_ADC1R_AD1TBRST_Msk      (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos)      /*!< 0x00080000 */

+#define HRTIM_ADC1R_AD1TBRST          HRTIM_ADC1R_AD1TBRST_Msk                 /*!< ADC Trigger 1 on Timer B reset */

+#define HRTIM_ADC1R_AD1TCC2_Pos       (20U)

+#define HRTIM_ADC1R_AD1TCC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC2_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC1R_AD1TCC2           HRTIM_ADC1R_AD1TCC2_Msk                  /*!< ADC Trigger 1 on Timer C compare 2 */

+#define HRTIM_ADC1R_AD1TCC3_Pos       (21U)

+#define HRTIM_ADC1R_AD1TCC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos)       /*!< 0x00200000 */

+#define HRTIM_ADC1R_AD1TCC3           HRTIM_ADC1R_AD1TCC3_Msk                  /*!< ADC Trigger 1 on Timer C compare 3 */

+#define HRTIM_ADC1R_AD1TCC4_Pos       (22U)

+#define HRTIM_ADC1R_AD1TCC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos)       /*!< 0x00400000 */

+#define HRTIM_ADC1R_AD1TCC4           HRTIM_ADC1R_AD1TCC4_Msk                  /*!< ADC Trigger 1 on Timer C compare 4 */

+#define HRTIM_ADC1R_AD1TCPER_Pos      (23U)

+#define HRTIM_ADC1R_AD1TCPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos)      /*!< 0x00800000 */

+#define HRTIM_ADC1R_AD1TCPER          HRTIM_ADC1R_AD1TCPER_Msk                 /*!< ADC Trigger 1 on Timer C period */

+#define HRTIM_ADC1R_AD1TDC2_Pos       (24U)

+#define HRTIM_ADC1R_AD1TDC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC2_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC1R_AD1TDC2           HRTIM_ADC1R_AD1TDC2_Msk                  /*!< ADC Trigger 1 on Timer D compare 2 */

+#define HRTIM_ADC1R_AD1TDC3_Pos       (25U)

+#define HRTIM_ADC1R_AD1TDC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC1R_AD1TDC3           HRTIM_ADC1R_AD1TDC3_Msk                  /*!< ADC Trigger 1 on Timer D compare 3 */

+#define HRTIM_ADC1R_AD1TDC4_Pos       (26U)

+#define HRTIM_ADC1R_AD1TDC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos)       /*!< 0x04000000 */

+#define HRTIM_ADC1R_AD1TDC4           HRTIM_ADC1R_AD1TDC4_Msk                  /*!< ADC Trigger 1 on Timer D compare 4 */

+#define HRTIM_ADC1R_AD1TDPER_Pos      (27U)

+#define HRTIM_ADC1R_AD1TDPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC1R_AD1TDPER          HRTIM_ADC1R_AD1TDPER_Msk                 /*!< ADC Trigger 1 on Timer D period */

+#define HRTIM_ADC1R_AD1TEC2_Pos       (28U)

+#define HRTIM_ADC1R_AD1TEC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC1R_AD1TEC2           HRTIM_ADC1R_AD1TEC2_Msk                  /*!< ADC Trigger 1 on Timer E compare 2 */

+#define HRTIM_ADC1R_AD1TEC3_Pos       (29U)

+#define HRTIM_ADC1R_AD1TEC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC1R_AD1TEC3           HRTIM_ADC1R_AD1TEC3_Msk                  /*!< ADC Trigger 1 on Timer E compare 3 */

+#define HRTIM_ADC1R_AD1TEC4_Pos       (30U)

+#define HRTIM_ADC1R_AD1TEC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC1R_AD1TEC4           HRTIM_ADC1R_AD1TEC4_Msk                  /*!< ADC Trigger 1 on Timer E compare 4 */

+#define HRTIM_ADC1R_AD1TEPER_Pos      (31U)

+#define HRTIM_ADC1R_AD1TEPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC1R_AD1TEPER          HRTIM_ADC1R_AD1TEPER_Msk                 /*!< ADC Trigger 1 on Timer E period */

+

+/*******************  Bit definition for HRTIM_ADC2R register  ****************/

+#define HRTIM_ADC2R_AD2MC1_Pos        (0U)

+#define HRTIM_ADC2R_AD2MC1_Msk        (0x1UL << HRTIM_ADC2R_AD2MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC2R_AD2MC1            HRTIM_ADC2R_AD2MC1_Msk                   /*!< ADC Trigger 2 on master compare 1 */

+#define HRTIM_ADC2R_AD2MC2_Pos        (1U)

+#define HRTIM_ADC2R_AD2MC2_Msk        (0x1UL << HRTIM_ADC2R_AD2MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC2R_AD2MC2            HRTIM_ADC2R_AD2MC2_Msk                   /*!< ADC Trigger 2 on master compare 2 */

+#define HRTIM_ADC2R_AD2MC3_Pos        (2U)

+#define HRTIM_ADC2R_AD2MC3_Msk        (0x1UL << HRTIM_ADC2R_AD2MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC2R_AD2MC3            HRTIM_ADC2R_AD2MC3_Msk                   /*!< ADC Trigger 2 on master compare 3 */

+#define HRTIM_ADC2R_AD2MC4_Pos        (3U)

+#define HRTIM_ADC2R_AD2MC4_Msk        (0x1UL << HRTIM_ADC2R_AD2MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC2R_AD2MC4            HRTIM_ADC2R_AD2MC4_Msk                   /*!< ADC Trigger 2 on master compare 4 */

+#define HRTIM_ADC2R_AD2MPER_Pos       (4U)

+#define HRTIM_ADC2R_AD2MPER_Msk       (0x1UL << HRTIM_ADC2R_AD2MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC2R_AD2MPER           HRTIM_ADC2R_AD2MPER_Msk                  /*!< ADC Trigger 2 on master period */

+#define HRTIM_ADC2R_AD2EEV6_Pos       (5U)

+#define HRTIM_ADC2R_AD2EEV6_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC2R_AD2EEV6           HRTIM_ADC2R_AD2EEV6_Msk                  /*!< ADC Trigger 2 on external event 6 */

+#define HRTIM_ADC2R_AD2EEV7_Pos       (6U)

+#define HRTIM_ADC2R_AD2EEV7_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC2R_AD2EEV7           HRTIM_ADC2R_AD2EEV7_Msk                  /*!< ADC Trigger 2 on external event 7 */

+#define HRTIM_ADC2R_AD2EEV8_Pos       (7U)

+#define HRTIM_ADC2R_AD2EEV8_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC2R_AD2EEV8           HRTIM_ADC2R_AD2EEV8_Msk                  /*!< ADC Trigger 2 on external event 8 */

+#define HRTIM_ADC2R_AD2EEV9_Pos       (8U)

+#define HRTIM_ADC2R_AD2EEV9_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC2R_AD2EEV9           HRTIM_ADC2R_AD2EEV9_Msk                  /*!< ADC Trigger 2 on external event 9 */

+#define HRTIM_ADC2R_AD2EEV10_Pos      (9U)

+#define HRTIM_ADC2R_AD2EEV10_Msk      (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos)      /*!< 0x00000200 */

+#define HRTIM_ADC2R_AD2EEV10          HRTIM_ADC2R_AD2EEV10_Msk                 /*!< ADC Trigger 2 on external event 10 */

+#define HRTIM_ADC2R_AD2TAC2_Pos       (10U)

+#define HRTIM_ADC2R_AD2TAC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC2R_AD2TAC2           HRTIM_ADC2R_AD2TAC2_Msk                  /*!< ADC Trigger 2 on Timer A compare 2 */

+#define HRTIM_ADC2R_AD2TAC3_Pos       (11U)

+#define HRTIM_ADC2R_AD2TAC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC2R_AD2TAC3           HRTIM_ADC2R_AD2TAC3_Msk                  /*!< ADC Trigger 2 on Timer A compare 3 */

+#define HRTIM_ADC2R_AD2TAC4_Pos       (12U)

+#define HRTIM_ADC2R_AD2TAC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC2R_AD2TAC4           HRTIM_ADC2R_AD2TAC4_Msk                  /*!< ADC Trigger 2 on Timer A compare 4*/

+#define HRTIM_ADC2R_AD2TAPER_Pos      (13U)

+#define HRTIM_ADC2R_AD2TAPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC2R_AD2TAPER          HRTIM_ADC2R_AD2TAPER_Msk                 /*!< ADC Trigger 2 on Timer A period */

+#define HRTIM_ADC2R_AD2TBC2_Pos       (14U)

+#define HRTIM_ADC2R_AD2TBC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos)       /*!< 0x00004000 */

+#define HRTIM_ADC2R_AD2TBC2           HRTIM_ADC2R_AD2TBC2_Msk                  /*!< ADC Trigger 2 on Timer B compare 2 */

+#define HRTIM_ADC2R_AD2TBC3_Pos       (15U)

+#define HRTIM_ADC2R_AD2TBC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC3_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC2R_AD2TBC3           HRTIM_ADC2R_AD2TBC3_Msk                  /*!< ADC Trigger 2 on Timer B compare 3 */

+#define HRTIM_ADC2R_AD2TBC4_Pos       (16U)

+#define HRTIM_ADC2R_AD2TBC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC2R_AD2TBC4           HRTIM_ADC2R_AD2TBC4_Msk                  /*!< ADC Trigger 2 on Timer B compare 4 */

+#define HRTIM_ADC2R_AD2TBPER_Pos      (17U)

+#define HRTIM_ADC2R_AD2TBPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos)      /*!< 0x00020000 */

+#define HRTIM_ADC2R_AD2TBPER          HRTIM_ADC2R_AD2TBPER_Msk                 /*!< ADC Trigger 2 on Timer B period */

+#define HRTIM_ADC2R_AD2TCC2_Pos       (18U)

+#define HRTIM_ADC2R_AD2TCC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos)       /*!< 0x00040000 */

+#define HRTIM_ADC2R_AD2TCC2           HRTIM_ADC2R_AD2TCC2_Msk                  /*!< ADC Trigger 2 on Timer C compare 2 */

+#define HRTIM_ADC2R_AD2TCC3_Pos       (19U)

+#define HRTIM_ADC2R_AD2TCC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC3_Pos)       /*!< 0x00080000 */

+#define HRTIM_ADC2R_AD2TCC3           HRTIM_ADC2R_AD2TCC3_Msk                  /*!< ADC Trigger 2 on Timer C compare 3 */

+#define HRTIM_ADC2R_AD2TCC4_Pos       (20U)

+#define HRTIM_ADC2R_AD2TCC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC2R_AD2TCC4           HRTIM_ADC2R_AD2TCC4_Msk                  /*!< ADC Trigger 2 on Timer C compare 4 */

+#define HRTIM_ADC2R_AD2TCPER_Pos      (21U)

+#define HRTIM_ADC2R_AD2TCPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos)      /*!< 0x00200000 */

+#define HRTIM_ADC2R_AD2TCPER          HRTIM_ADC2R_AD2TCPER_Msk                 /*!< ADC Trigger 2 on Timer C period */

+#define HRTIM_ADC2R_AD2TCRST_Pos      (22U)

+#define HRTIM_ADC2R_AD2TCRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos)      /*!< 0x00400000 */

+#define HRTIM_ADC2R_AD2TCRST          HRTIM_ADC2R_AD2TCRST_Msk                 /*!< ADC Trigger 2 on Timer C reset */

+#define HRTIM_ADC2R_AD2TDC2_Pos       (23U)

+#define HRTIM_ADC2R_AD2TDC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos)       /*!< 0x00800000 */

+#define HRTIM_ADC2R_AD2TDC2           HRTIM_ADC2R_AD2TDC2_Msk                  /*!< ADC Trigger 2 on Timer D compare 2 */

+#define HRTIM_ADC2R_AD2TDC3_Pos       (24U)

+#define HRTIM_ADC2R_AD2TDC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC3_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC2R_AD2TDC3           HRTIM_ADC2R_AD2TDC3_Msk                  /*!< ADC Trigger 2 on Timer D compare 3 */

+#define HRTIM_ADC2R_AD2TDC4_Pos       (25U)

+#define HRTIM_ADC2R_AD2TDC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC2R_AD2TDC4           HRTIM_ADC2R_AD2TDC4_Msk                  /*!< ADC Trigger 2 on Timer D compare 4*/

+#define HRTIM_ADC2R_AD2TDPER_Pos      (26U)

+#define HRTIM_ADC2R_AD2TDPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos)      /*!< 0x04000000 */

+#define HRTIM_ADC2R_AD2TDPER          HRTIM_ADC2R_AD2TDPER_Msk                 /*!< ADC Trigger 2 on Timer D period */

+#define HRTIM_ADC2R_AD2TDRST_Pos      (27U)

+#define HRTIM_ADC2R_AD2TDRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC2R_AD2TDRST          HRTIM_ADC2R_AD2TDRST_Msk                 /*!< ADC Trigger 2 on Timer D reset */

+#define HRTIM_ADC2R_AD2TEC2_Pos       (28U)

+#define HRTIM_ADC2R_AD2TEC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC2R_AD2TEC2           HRTIM_ADC2R_AD2TEC2_Msk                  /*!< ADC Trigger 2 on Timer E compare 2 */

+#define HRTIM_ADC2R_AD2TEC3_Pos       (29U)

+#define HRTIM_ADC2R_AD2TEC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC2R_AD2TEC3           HRTIM_ADC2R_AD2TEC3_Msk                  /*!< ADC Trigger 2 on Timer E compare 3 */

+#define HRTIM_ADC2R_AD2TEC4_Pos       (30U)

+#define HRTIM_ADC2R_AD2TEC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC2R_AD2TEC4           HRTIM_ADC2R_AD2TEC4_Msk                  /*!< ADC Trigger 2 on Timer E compare 4 */

+#define HRTIM_ADC2R_AD2TERST_Pos      (31U)

+#define HRTIM_ADC2R_AD2TERST_Msk      (0x1UL << HRTIM_ADC2R_AD2TERST_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC2R_AD2TERST          HRTIM_ADC2R_AD2TERST_Msk                 /*!< ADC Trigger 2 on Timer E reset */

+

+/*******************  Bit definition for HRTIM_ADC3R register  ****************/

+#define HRTIM_ADC3R_AD3MC1_Pos        (0U)

+#define HRTIM_ADC3R_AD3MC1_Msk        (0x1UL << HRTIM_ADC3R_AD3MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC3R_AD3MC1            HRTIM_ADC3R_AD3MC1_Msk                   /*!< ADC Trigger 3 on master compare 1 */

+#define HRTIM_ADC3R_AD3MC2_Pos        (1U)

+#define HRTIM_ADC3R_AD3MC2_Msk        (0x1UL << HRTIM_ADC3R_AD3MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC3R_AD3MC2            HRTIM_ADC3R_AD3MC2_Msk                   /*!< ADC Trigger 3 on master compare 2 */

+#define HRTIM_ADC3R_AD3MC3_Pos        (2U)

+#define HRTIM_ADC3R_AD3MC3_Msk        (0x1UL << HRTIM_ADC3R_AD3MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC3R_AD3MC3            HRTIM_ADC3R_AD3MC3_Msk                   /*!< ADC Trigger 3 on master compare 3 */

+#define HRTIM_ADC3R_AD3MC4_Pos        (3U)

+#define HRTIM_ADC3R_AD3MC4_Msk        (0x1UL << HRTIM_ADC3R_AD3MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC3R_AD3MC4            HRTIM_ADC3R_AD3MC4_Msk                   /*!< ADC Trigger 3 on master compare 4 */

+#define HRTIM_ADC3R_AD3MPER_Pos       (4U)

+#define HRTIM_ADC3R_AD3MPER_Msk       (0x1UL << HRTIM_ADC3R_AD3MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC3R_AD3MPER           HRTIM_ADC3R_AD3MPER_Msk                  /*!< ADC Trigger 3 on master period */

+#define HRTIM_ADC3R_AD3EEV1_Pos       (5U)

+#define HRTIM_ADC3R_AD3EEV1_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC3R_AD3EEV1           HRTIM_ADC3R_AD3EEV1_Msk                  /*!< ADC Trigger 3 on external event 1 */

+#define HRTIM_ADC3R_AD3EEV2_Pos       (6U)

+#define HRTIM_ADC3R_AD3EEV2_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC3R_AD3EEV2           HRTIM_ADC3R_AD3EEV2_Msk                  /*!< ADC Trigger 3 on external event 2 */

+#define HRTIM_ADC3R_AD3EEV3_Pos       (7U)

+#define HRTIM_ADC3R_AD3EEV3_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC3R_AD3EEV3           HRTIM_ADC3R_AD3EEV3_Msk                  /*!< ADC Trigger 3 on external event 3 */

+#define HRTIM_ADC3R_AD3EEV4_Pos       (8U)

+#define HRTIM_ADC3R_AD3EEV4_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC3R_AD3EEV4           HRTIM_ADC3R_AD3EEV4_Msk                  /*!< ADC Trigger 3 on external event 4 */

+#define HRTIM_ADC3R_AD3EEV5_Pos       (9U)

+#define HRTIM_ADC3R_AD3EEV5_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos)       /*!< 0x00000200 */

+#define HRTIM_ADC3R_AD3EEV5           HRTIM_ADC3R_AD3EEV5_Msk                  /*!< ADC Trigger 3 on external event 5 */

+#define HRTIM_ADC3R_AD3TAC2_Pos       (10U)

+#define HRTIM_ADC3R_AD3TAC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC3R_AD3TAC2           HRTIM_ADC3R_AD3TAC2_Msk                  /*!< ADC Trigger 3 on Timer A compare 2 */

+#define HRTIM_ADC3R_AD3TAC3_Pos       (11U)

+#define HRTIM_ADC3R_AD3TAC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC3R_AD3TAC3           HRTIM_ADC3R_AD3TAC3_Msk                  /*!< ADC Trigger 3 on Timer A compare 3 */

+#define HRTIM_ADC3R_AD3TAC4_Pos       (12U)

+#define HRTIM_ADC3R_AD3TAC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC3R_AD3TAC4           HRTIM_ADC3R_AD3TAC4_Msk                  /*!< ADC Trigger 3 on Timer A compare 4 */

+#define HRTIM_ADC3R_AD3TAPER_Pos      (13U)

+#define HRTIM_ADC3R_AD3TAPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC3R_AD3TAPER          HRTIM_ADC3R_AD3TAPER_Msk                 /*!< ADC Trigger 3 on Timer A period */

+#define HRTIM_ADC3R_AD3TARST_Pos      (14U)

+#define HRTIM_ADC3R_AD3TARST_Msk      (0x1UL << HRTIM_ADC3R_AD3TARST_Pos)      /*!< 0x00004000 */

+#define HRTIM_ADC3R_AD3TARST          HRTIM_ADC3R_AD3TARST_Msk                 /*!< ADC Trigger 3 on Timer A reset */

+#define HRTIM_ADC3R_AD3TBC2_Pos       (15U)

+#define HRTIM_ADC3R_AD3TBC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC2_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC3R_AD3TBC2           HRTIM_ADC3R_AD3TBC2_Msk                  /*!< ADC Trigger 3 on Timer B compare 2 */

+#define HRTIM_ADC3R_AD3TBC3_Pos       (16U)

+#define HRTIM_ADC3R_AD3TBC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC3R_AD3TBC3           HRTIM_ADC3R_AD3TBC3_Msk                  /*!< ADC Trigger 3 on Timer B compare 3 */

+#define HRTIM_ADC3R_AD3TBC4_Pos       (17U)

+#define HRTIM_ADC3R_AD3TBC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos)       /*!< 0x00020000 */

+#define HRTIM_ADC3R_AD3TBC4           HRTIM_ADC3R_AD3TBC4_Msk                  /*!< ADC Trigger 3 on Timer B compare 4 */

+#define HRTIM_ADC3R_AD3TBPER_Pos      (18U)

+#define HRTIM_ADC3R_AD3TBPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos)      /*!< 0x00040000 */

+#define HRTIM_ADC3R_AD3TBPER          HRTIM_ADC3R_AD3TBPER_Msk                 /*!< ADC Trigger 3 on Timer B period */

+#define HRTIM_ADC3R_AD3TBRST_Pos      (19U)

+#define HRTIM_ADC3R_AD3TBRST_Msk      (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos)      /*!< 0x00080000 */

+#define HRTIM_ADC3R_AD3TBRST          HRTIM_ADC3R_AD3TBRST_Msk                 /*!< ADC Trigger 3 on Timer B reset */

+#define HRTIM_ADC3R_AD3TCC2_Pos       (20U)

+#define HRTIM_ADC3R_AD3TCC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC2_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC3R_AD3TCC2           HRTIM_ADC3R_AD3TCC2_Msk                  /*!< ADC Trigger 3 on Timer C compare 2 */

+#define HRTIM_ADC3R_AD3TCC3_Pos       (21U)

+#define HRTIM_ADC3R_AD3TCC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos)       /*!< 0x00200000 */

+#define HRTIM_ADC3R_AD3TCC3           HRTIM_ADC3R_AD3TCC3_Msk                  /*!< ADC Trigger 3 on Timer C compare 3 */

+#define HRTIM_ADC3R_AD3TCC4_Pos       (22U)

+#define HRTIM_ADC3R_AD3TCC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos)       /*!< 0x00400000 */

+#define HRTIM_ADC3R_AD3TCC4           HRTIM_ADC3R_AD3TCC4_Msk                  /*!< ADC Trigger 3 on Timer C compare 4 */

+#define HRTIM_ADC3R_AD3TCPER_Pos      (23U)

+#define HRTIM_ADC3R_AD3TCPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos)      /*!< 0x00800000 */

+#define HRTIM_ADC3R_AD3TCPER          HRTIM_ADC3R_AD3TCPER_Msk                 /*!< ADC Trigger 3 on Timer C period */

+#define HRTIM_ADC3R_AD3TDC2_Pos       (24U)

+#define HRTIM_ADC3R_AD3TDC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC2_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC3R_AD3TDC2           HRTIM_ADC3R_AD3TDC2_Msk                  /*!< ADC Trigger 3 on Timer D compare 2 */

+#define HRTIM_ADC3R_AD3TDC3_Pos       (25U)

+#define HRTIM_ADC3R_AD3TDC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC3R_AD3TDC3           HRTIM_ADC3R_AD3TDC3_Msk                  /*!< ADC Trigger 3 on Timer D compare 3 */

+#define HRTIM_ADC3R_AD3TDC4_Pos       (26U)

+#define HRTIM_ADC3R_AD3TDC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos)       /*!< 0x04000000 */

+#define HRTIM_ADC3R_AD3TDC4           HRTIM_ADC3R_AD3TDC4_Msk                  /*!< ADC Trigger 3 on Timer D compare 4 */

+#define HRTIM_ADC3R_AD3TDPER_Pos      (27U)

+#define HRTIM_ADC3R_AD3TDPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC3R_AD3TDPER          HRTIM_ADC3R_AD3TDPER_Msk                 /*!< ADC Trigger 3 on Timer D period */

+#define HRTIM_ADC3R_AD3TEC2_Pos       (28U)

+#define HRTIM_ADC3R_AD3TEC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC3R_AD3TEC2           HRTIM_ADC3R_AD3TEC2_Msk                  /*!< ADC Trigger 3 on Timer E compare 2 */

+#define HRTIM_ADC3R_AD3TEC3_Pos       (29U)

+#define HRTIM_ADC3R_AD3TEC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC3R_AD3TEC3           HRTIM_ADC3R_AD3TEC3_Msk                  /*!< ADC Trigger 3 on Timer E compare 3 */

+#define HRTIM_ADC3R_AD3TEC4_Pos       (30U)

+#define HRTIM_ADC3R_AD3TEC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC3R_AD3TEC4           HRTIM_ADC3R_AD3TEC4_Msk                  /*!< ADC Trigger 3 on Timer E compare 4 */

+#define HRTIM_ADC3R_AD3TEPER_Pos      (31U)

+#define HRTIM_ADC3R_AD3TEPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC3R_AD3TEPER          HRTIM_ADC3R_AD3TEPER_Msk                 /*!< ADC Trigger 3 on Timer E period */

+

+/*******************  Bit definition for HRTIM_ADC4R register  ****************/

+#define HRTIM_ADC4R_AD4MC1_Pos        (0U)

+#define HRTIM_ADC4R_AD4MC1_Msk        (0x1UL << HRTIM_ADC4R_AD4MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC4R_AD4MC1            HRTIM_ADC4R_AD4MC1_Msk                   /*!< ADC Trigger 4 on master compare 1 */

+#define HRTIM_ADC4R_AD4MC2_Pos        (1U)

+#define HRTIM_ADC4R_AD4MC2_Msk        (0x1UL << HRTIM_ADC4R_AD4MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC4R_AD4MC2            HRTIM_ADC4R_AD4MC2_Msk                   /*!< ADC Trigger 4 on master compare 2 */

+#define HRTIM_ADC4R_AD4MC3_Pos        (2U)

+#define HRTIM_ADC4R_AD4MC3_Msk        (0x1UL << HRTIM_ADC4R_AD4MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC4R_AD4MC3            HRTIM_ADC4R_AD4MC3_Msk                   /*!< ADC Trigger 4 on master compare 3 */

+#define HRTIM_ADC4R_AD4MC4_Pos        (3U)

+#define HRTIM_ADC4R_AD4MC4_Msk        (0x1UL << HRTIM_ADC4R_AD4MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC4R_AD4MC4            HRTIM_ADC4R_AD4MC4_Msk                   /*!< ADC Trigger 4 on master compare 4 */

+#define HRTIM_ADC4R_AD4MPER_Pos       (4U)

+#define HRTIM_ADC4R_AD4MPER_Msk       (0x1UL << HRTIM_ADC4R_AD4MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC4R_AD4MPER           HRTIM_ADC4R_AD4MPER_Msk                  /*!< ADC Trigger 4 on master period */

+#define HRTIM_ADC4R_AD4EEV6_Pos       (5U)

+#define HRTIM_ADC4R_AD4EEV6_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC4R_AD4EEV6           HRTIM_ADC4R_AD4EEV6_Msk                  /*!< ADC Trigger 4 on external event 6 */

+#define HRTIM_ADC4R_AD4EEV7_Pos       (6U)

+#define HRTIM_ADC4R_AD4EEV7_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC4R_AD4EEV7           HRTIM_ADC4R_AD4EEV7_Msk                  /*!< ADC Trigger 4 on external event 7 */

+#define HRTIM_ADC4R_AD4EEV8_Pos       (7U)

+#define HRTIM_ADC4R_AD4EEV8_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC4R_AD4EEV8           HRTIM_ADC4R_AD4EEV8_Msk                  /*!< ADC Trigger 4 on external event 8 */

+#define HRTIM_ADC4R_AD4EEV9_Pos       (8U)

+#define HRTIM_ADC4R_AD4EEV9_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC4R_AD4EEV9           HRTIM_ADC4R_AD4EEV9_Msk                  /*!< ADC Trigger 4 on external event 9 */

+#define HRTIM_ADC4R_AD4EEV10_Pos      (9U)

+#define HRTIM_ADC4R_AD4EEV10_Msk      (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos)      /*!< 0x00000200 */

+#define HRTIM_ADC4R_AD4EEV10          HRTIM_ADC4R_AD4EEV10_Msk                 /*!< ADC Trigger 4 on external event 10 */

+#define HRTIM_ADC4R_AD4TAC2_Pos       (10U)

+#define HRTIM_ADC4R_AD4TAC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC4R_AD4TAC2           HRTIM_ADC4R_AD4TAC2_Msk                  /*!< ADC Trigger 4 on Timer A compare 2 */

+#define HRTIM_ADC4R_AD4TAC3_Pos       (11U)

+#define HRTIM_ADC4R_AD4TAC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC4R_AD4TAC3           HRTIM_ADC4R_AD4TAC3_Msk                  /*!< ADC Trigger 4 on Timer A compare 3 */

+#define HRTIM_ADC4R_AD4TAC4_Pos       (12U)

+#define HRTIM_ADC4R_AD4TAC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC4R_AD4TAC4           HRTIM_ADC4R_AD4TAC4_Msk                  /*!< ADC Trigger 4 on Timer A compare 4*/

+#define HRTIM_ADC4R_AD4TAPER_Pos      (13U)

+#define HRTIM_ADC4R_AD4TAPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC4R_AD4TAPER          HRTIM_ADC4R_AD4TAPER_Msk                 /*!< ADC Trigger 4 on Timer A period */

+#define HRTIM_ADC4R_AD4TBC2_Pos       (14U)

+#define HRTIM_ADC4R_AD4TBC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos)       /*!< 0x00004000 */

+#define HRTIM_ADC4R_AD4TBC2           HRTIM_ADC4R_AD4TBC2_Msk                  /*!< ADC Trigger 4 on Timer B compare 2 */

+#define HRTIM_ADC4R_AD4TBC3_Pos       (15U)

+#define HRTIM_ADC4R_AD4TBC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC3_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC4R_AD4TBC3           HRTIM_ADC4R_AD4TBC3_Msk                  /*!< ADC Trigger 4 on Timer B compare 3 */

+#define HRTIM_ADC4R_AD4TBC4_Pos       (16U)

+#define HRTIM_ADC4R_AD4TBC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC4R_AD4TBC4           HRTIM_ADC4R_AD4TBC4_Msk                  /*!< ADC Trigger 4 on Timer B compare 4 */

+#define HRTIM_ADC4R_AD4TBPER_Pos      (17U)

+#define HRTIM_ADC4R_AD4TBPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos)      /*!< 0x00020000 */

+#define HRTIM_ADC4R_AD4TBPER          HRTIM_ADC4R_AD4TBPER_Msk                 /*!< ADC Trigger 4 on Timer B period */

+#define HRTIM_ADC4R_AD4TCC2_Pos       (18U)

+#define HRTIM_ADC4R_AD4TCC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos)       /*!< 0x00040000 */

+#define HRTIM_ADC4R_AD4TCC2           HRTIM_ADC4R_AD4TCC2_Msk                  /*!< ADC Trigger 4 on Timer C compare 2 */

+#define HRTIM_ADC4R_AD4TCC3_Pos       (19U)

+#define HRTIM_ADC4R_AD4TCC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC3_Pos)       /*!< 0x00080000 */

+#define HRTIM_ADC4R_AD4TCC3           HRTIM_ADC4R_AD4TCC3_Msk                  /*!< ADC Trigger 4 on Timer C compare 3 */

+#define HRTIM_ADC4R_AD4TCC4_Pos       (20U)

+#define HRTIM_ADC4R_AD4TCC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC4R_AD4TCC4           HRTIM_ADC4R_AD4TCC4_Msk                  /*!< ADC Trigger 4 on Timer C compare 4 */

+#define HRTIM_ADC4R_AD4TCPER_Pos      (21U)

+#define HRTIM_ADC4R_AD4TCPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos)      /*!< 0x00200000 */

+#define HRTIM_ADC4R_AD4TCPER          HRTIM_ADC4R_AD4TCPER_Msk                 /*!< ADC Trigger 4 on Timer C period */

+#define HRTIM_ADC4R_AD4TCRST_Pos      (22U)

+#define HRTIM_ADC4R_AD4TCRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos)      /*!< 0x00400000 */

+#define HRTIM_ADC4R_AD4TCRST          HRTIM_ADC4R_AD4TCRST_Msk                 /*!< ADC Trigger 4 on Timer C reset */

+#define HRTIM_ADC4R_AD4TDC2_Pos       (23U)

+#define HRTIM_ADC4R_AD4TDC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos)       /*!< 0x00800000 */

+#define HRTIM_ADC4R_AD4TDC2           HRTIM_ADC4R_AD4TDC2_Msk                  /*!< ADC Trigger 4 on Timer D compare 2 */

+#define HRTIM_ADC4R_AD4TDC3_Pos       (24U)

+#define HRTIM_ADC4R_AD4TDC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC3_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC4R_AD4TDC3           HRTIM_ADC4R_AD4TDC3_Msk                  /*!< ADC Trigger 4 on Timer D compare 3 */

+#define HRTIM_ADC4R_AD4TDC4_Pos       (25U)

+#define HRTIM_ADC4R_AD4TDC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC4R_AD4TDC4           HRTIM_ADC4R_AD4TDC4_Msk                  /*!< ADC Trigger 4 on Timer D compare 4*/

+#define HRTIM_ADC4R_AD4TDPER_Pos      (26U)

+#define HRTIM_ADC4R_AD4TDPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos)      /*!< 0x04000000 */

+#define HRTIM_ADC4R_AD4TDPER          HRTIM_ADC4R_AD4TDPER_Msk                 /*!< ADC Trigger 4 on Timer D period */

+#define HRTIM_ADC4R_AD4TDRST_Pos      (27U)

+#define HRTIM_ADC4R_AD4TDRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC4R_AD4TDRST          HRTIM_ADC4R_AD4TDRST_Msk                 /*!< ADC Trigger 4 on Timer D reset */

+#define HRTIM_ADC4R_AD4TEC2_Pos       (28U)

+#define HRTIM_ADC4R_AD4TEC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC4R_AD4TEC2           HRTIM_ADC4R_AD4TEC2_Msk                  /*!< ADC Trigger 4 on Timer E compare 2 */

+#define HRTIM_ADC4R_AD4TEC3_Pos       (29U)

+#define HRTIM_ADC4R_AD4TEC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC4R_AD4TEC3           HRTIM_ADC4R_AD4TEC3_Msk                  /*!< ADC Trigger 4 on Timer E compare 3 */

+#define HRTIM_ADC4R_AD4TEC4_Pos       (30U)

+#define HRTIM_ADC4R_AD4TEC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC4R_AD4TEC4           HRTIM_ADC4R_AD4TEC4_Msk                  /*!< ADC Trigger 4 on Timer E compare 4 */

+#define HRTIM_ADC4R_AD4TERST_Pos      (31U)

+#define HRTIM_ADC4R_AD4TERST_Msk      (0x1UL << HRTIM_ADC4R_AD4TERST_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC4R_AD4TERST          HRTIM_ADC4R_AD4TERST_Msk                 /*!< ADC Trigger 4 on Timer E reset */

+

+/*******************  Bit definition for HRTIM_FLTINR1 register  ***************/

+#define HRTIM_FLTINR1_FLT1E_Pos       (0U)

+#define HRTIM_FLTINR1_FLT1E_Msk       (0x1UL << HRTIM_FLTINR1_FLT1E_Pos)       /*!< 0x00000001 */

+#define HRTIM_FLTINR1_FLT1E           HRTIM_FLTINR1_FLT1E_Msk                  /*!< Fault 1 enable */

+#define HRTIM_FLTINR1_FLT1P_Pos       (1U)

+#define HRTIM_FLTINR1_FLT1P_Msk       (0x1UL << HRTIM_FLTINR1_FLT1P_Pos)       /*!< 0x00000002 */

+#define HRTIM_FLTINR1_FLT1P           HRTIM_FLTINR1_FLT1P_Msk                  /*!< Fault 1 polarity */

+#define HRTIM_FLTINR1_FLT1SRC_Pos     (2U)

+#define HRTIM_FLTINR1_FLT1SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT1SRC_Pos)     /*!< 0x00000004 */

+#define HRTIM_FLTINR1_FLT1SRC         HRTIM_FLTINR1_FLT1SRC_Msk                /*!< Fault 1 source */

+#define HRTIM_FLTINR1_FLT1F_Pos       (3U)

+#define HRTIM_FLTINR1_FLT1F_Msk       (0xFUL << HRTIM_FLTINR1_FLT1F_Pos)       /*!< 0x00000078 */

+#define HRTIM_FLTINR1_FLT1F           HRTIM_FLTINR1_FLT1F_Msk                  /*!< Fault 1 filter */

+#define HRTIM_FLTINR1_FLT1F_0         (0x1UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000008 */

+#define HRTIM_FLTINR1_FLT1F_1         (0x2UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000010 */

+#define HRTIM_FLTINR1_FLT1F_2         (0x4UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000020 */

+#define HRTIM_FLTINR1_FLT1F_3         (0x8UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000040 */

+#define HRTIM_FLTINR1_FLT1LCK_Pos     (7U)

+#define HRTIM_FLTINR1_FLT1LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos)     /*!< 0x00000080 */

+#define HRTIM_FLTINR1_FLT1LCK         HRTIM_FLTINR1_FLT1LCK_Msk                /*!< Fault 1 lock */

+

+#define HRTIM_FLTINR1_FLT2E_Pos       (8U)

+#define HRTIM_FLTINR1_FLT2E_Msk       (0x1UL << HRTIM_FLTINR1_FLT2E_Pos)       /*!< 0x00000100 */

+#define HRTIM_FLTINR1_FLT2E           HRTIM_FLTINR1_FLT2E_Msk                  /*!< Fault 2 enable */

+#define HRTIM_FLTINR1_FLT2P_Pos       (9U)

+#define HRTIM_FLTINR1_FLT2P_Msk       (0x1UL << HRTIM_FLTINR1_FLT2P_Pos)       /*!< 0x00000200 */

+#define HRTIM_FLTINR1_FLT2P           HRTIM_FLTINR1_FLT2P_Msk                  /*!< Fault 2 polarity */

+#define HRTIM_FLTINR1_FLT2SRC_Pos     (10U)

+#define HRTIM_FLTINR1_FLT2SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT2SRC_Pos)     /*!< 0x00000400 */

+#define HRTIM_FLTINR1_FLT2SRC         HRTIM_FLTINR1_FLT2SRC_Msk                /*!< Fault 2 source */

+#define HRTIM_FLTINR1_FLT2F_Pos       (11U)

+#define HRTIM_FLTINR1_FLT2F_Msk       (0xFUL << HRTIM_FLTINR1_FLT2F_Pos)       /*!< 0x00007800 */

+#define HRTIM_FLTINR1_FLT2F           HRTIM_FLTINR1_FLT2F_Msk                  /*!< Fault 2 filter */

+#define HRTIM_FLTINR1_FLT2F_0         (0x1UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00000800 */

+#define HRTIM_FLTINR1_FLT2F_1         (0x2UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00001000 */

+#define HRTIM_FLTINR1_FLT2F_2         (0x4UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00002000 */

+#define HRTIM_FLTINR1_FLT2F_3         (0x8UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00004000 */

+#define HRTIM_FLTINR1_FLT2LCK_Pos     (15U)

+#define HRTIM_FLTINR1_FLT2LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos)     /*!< 0x00008000 */

+#define HRTIM_FLTINR1_FLT2LCK         HRTIM_FLTINR1_FLT2LCK_Msk                /*!< Fault 2 lock */

+

+#define HRTIM_FLTINR1_FLT3E_Pos       (16U)

+#define HRTIM_FLTINR1_FLT3E_Msk       (0x1UL << HRTIM_FLTINR1_FLT3E_Pos)       /*!< 0x00010000 */

+#define HRTIM_FLTINR1_FLT3E           HRTIM_FLTINR1_FLT3E_Msk                  /*!< Fault 3 enable */

+#define HRTIM_FLTINR1_FLT3P_Pos       (17U)

+#define HRTIM_FLTINR1_FLT3P_Msk       (0x1UL << HRTIM_FLTINR1_FLT3P_Pos)       /*!< 0x00020000 */

+#define HRTIM_FLTINR1_FLT3P           HRTIM_FLTINR1_FLT3P_Msk                  /*!< Fault 3 polarity */

+#define HRTIM_FLTINR1_FLT3SRC_Pos     (18U)

+#define HRTIM_FLTINR1_FLT3SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT3SRC_Pos)     /*!< 0x00040000 */

+#define HRTIM_FLTINR1_FLT3SRC         HRTIM_FLTINR1_FLT3SRC_Msk                /*!< Fault 3 source */

+#define HRTIM_FLTINR1_FLT3F_Pos       (19U)

+#define HRTIM_FLTINR1_FLT3F_Msk       (0xFUL << HRTIM_FLTINR1_FLT3F_Pos)       /*!< 0x00780000 */

+#define HRTIM_FLTINR1_FLT3F           HRTIM_FLTINR1_FLT3F_Msk                  /*!< Fault 3 filter */

+#define HRTIM_FLTINR1_FLT3F_0         (0x1UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00080000 */

+#define HRTIM_FLTINR1_FLT3F_1         (0x2UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00100000 */

+#define HRTIM_FLTINR1_FLT3F_2         (0x4UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00200000 */

+#define HRTIM_FLTINR1_FLT3F_3         (0x8UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00400000 */

+#define HRTIM_FLTINR1_FLT3LCK_Pos     (23U)

+#define HRTIM_FLTINR1_FLT3LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos)     /*!< 0x00800000 */

+#define HRTIM_FLTINR1_FLT3LCK         HRTIM_FLTINR1_FLT3LCK_Msk                /*!< Fault 3 lock */

+

+#define HRTIM_FLTINR1_FLT4E_Pos       (24U)

+#define HRTIM_FLTINR1_FLT4E_Msk       (0x1UL << HRTIM_FLTINR1_FLT4E_Pos)       /*!< 0x01000000 */

+#define HRTIM_FLTINR1_FLT4E           HRTIM_FLTINR1_FLT4E_Msk                  /*!< Fault 4 enable */

+#define HRTIM_FLTINR1_FLT4P_Pos       (25U)

+#define HRTIM_FLTINR1_FLT4P_Msk       (0x1UL << HRTIM_FLTINR1_FLT4P_Pos)       /*!< 0x02000000 */

+#define HRTIM_FLTINR1_FLT4P           HRTIM_FLTINR1_FLT4P_Msk                  /*!< Fault 4 polarity */

+#define HRTIM_FLTINR1_FLT4SRC_Pos     (26U)

+#define HRTIM_FLTINR1_FLT4SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT4SRC_Pos)     /*!< 0x04000000 */

+#define HRTIM_FLTINR1_FLT4SRC         HRTIM_FLTINR1_FLT4SRC_Msk                /*!< Fault 4 source */

+#define HRTIM_FLTINR1_FLT4F_Pos       (27U)

+#define HRTIM_FLTINR1_FLT4F_Msk       (0xFUL << HRTIM_FLTINR1_FLT4F_Pos)       /*!< 0x78000000 */

+#define HRTIM_FLTINR1_FLT4F           HRTIM_FLTINR1_FLT4F_Msk                  /*!< Fault 4 filter */

+#define HRTIM_FLTINR1_FLT4F_0         (0x1UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x08000000 */

+#define HRTIM_FLTINR1_FLT4F_1         (0x2UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x10000000 */

+#define HRTIM_FLTINR1_FLT4F_2         (0x4UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x20000000 */

+#define HRTIM_FLTINR1_FLT4F_3         (0x8UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x40000000 */

+#define HRTIM_FLTINR1_FLT4LCK_Pos     (31U)

+#define HRTIM_FLTINR1_FLT4LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos)     /*!< 0x80000000 */

+#define HRTIM_FLTINR1_FLT4LCK         HRTIM_FLTINR1_FLT4LCK_Msk                /*!< Fault 4 lock */

+

+/*******************  Bit definition for HRTIM_FLTINR2 register  ***************/

+#define HRTIM_FLTINR2_FLT5E_Pos       (0U)

+#define HRTIM_FLTINR2_FLT5E_Msk       (0x1UL << HRTIM_FLTINR2_FLT5E_Pos)       /*!< 0x00000001 */

+#define HRTIM_FLTINR2_FLT5E           HRTIM_FLTINR2_FLT5E_Msk                  /*!< Fault 5 enable */

+#define HRTIM_FLTINR2_FLT5P_Pos       (1U)

+#define HRTIM_FLTINR2_FLT5P_Msk       (0x1UL << HRTIM_FLTINR2_FLT5P_Pos)       /*!< 0x00000002 */

+#define HRTIM_FLTINR2_FLT5P           HRTIM_FLTINR2_FLT5P_Msk                  /*!< Fault 5 polarity */

+#define HRTIM_FLTINR2_FLT5SRC_Pos     (2U)

+#define HRTIM_FLTINR2_FLT5SRC_Msk     (0x1UL << HRTIM_FLTINR2_FLT5SRC_Pos)     /*!< 0x00000004 */

+#define HRTIM_FLTINR2_FLT5SRC         HRTIM_FLTINR2_FLT5SRC_Msk                /*!< Fault 5 source */

+#define HRTIM_FLTINR2_FLT5F_Pos       (3U)

+#define HRTIM_FLTINR2_FLT5F_Msk       (0xFUL << HRTIM_FLTINR2_FLT5F_Pos)       /*!< 0x00000078 */

+#define HRTIM_FLTINR2_FLT5F           HRTIM_FLTINR2_FLT5F_Msk                  /*!< Fault 5 filter */

+#define HRTIM_FLTINR2_FLT5F_0         (0x1UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000008 */

+#define HRTIM_FLTINR2_FLT5F_1         (0x2UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000010 */

+#define HRTIM_FLTINR2_FLT5F_2         (0x4UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000020 */

+#define HRTIM_FLTINR2_FLT5F_3         (0x8UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000040 */

+#define HRTIM_FLTINR2_FLT5LCK_Pos     (7U)

+#define HRTIM_FLTINR2_FLT5LCK_Msk     (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos)     /*!< 0x00000080 */

+#define HRTIM_FLTINR2_FLT5LCK         HRTIM_FLTINR2_FLT5LCK_Msk                /*!< Fault 5 lock */

+#define HRTIM_FLTINR2_FLTSD_Pos       (24U)

+#define HRTIM_FLTINR2_FLTSD_Msk       (0x3UL << HRTIM_FLTINR2_FLTSD_Pos)       /*!< 0x03000000 */

+#define HRTIM_FLTINR2_FLTSD           HRTIM_FLTINR2_FLTSD_Msk                  /*!< Fault sampling clock division */

+#define HRTIM_FLTINR2_FLTSD_0         (0x1UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x01000000 */

+#define HRTIM_FLTINR2_FLTSD_1         (0x2UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x02000000 */

+

+/*******************  Bit definition for HRTIM_BDMUPR register  ***************/

+#define HRTIM_BDMUPR_MCR_Pos          (0U)

+#define HRTIM_BDMUPR_MCR_Msk          (0x1UL << HRTIM_BDMUPR_MCR_Pos)          /*!< 0x00000001 */

+#define HRTIM_BDMUPR_MCR              HRTIM_BDMUPR_MCR_Msk                     /*!< MCR register update enable */

+#define HRTIM_BDMUPR_MICR_Pos         (1U)

+#define HRTIM_BDMUPR_MICR_Msk         (0x1UL << HRTIM_BDMUPR_MICR_Pos)         /*!< 0x00000002 */

+#define HRTIM_BDMUPR_MICR             HRTIM_BDMUPR_MICR_Msk                    /*!< MICR register update enable */

+#define HRTIM_BDMUPR_MDIER_Pos        (2U)

+#define HRTIM_BDMUPR_MDIER_Msk        (0x1UL << HRTIM_BDMUPR_MDIER_Pos)        /*!< 0x00000004 */

+#define HRTIM_BDMUPR_MDIER            HRTIM_BDMUPR_MDIER_Msk                   /*!< MDIER register update enable */

+#define HRTIM_BDMUPR_MCNT_Pos         (3U)

+#define HRTIM_BDMUPR_MCNT_Msk         (0x1UL << HRTIM_BDMUPR_MCNT_Pos)         /*!< 0x00000008 */

+#define HRTIM_BDMUPR_MCNT             HRTIM_BDMUPR_MCNT_Msk                    /*!< MCNT register update enable */

+#define HRTIM_BDMUPR_MPER_Pos         (4U)

+#define HRTIM_BDMUPR_MPER_Msk         (0x1UL << HRTIM_BDMUPR_MPER_Pos)         /*!< 0x00000010 */

+#define HRTIM_BDMUPR_MPER             HRTIM_BDMUPR_MPER_Msk                    /*!< MPER register update enable */

+#define HRTIM_BDMUPR_MREP_Pos         (5U)

+#define HRTIM_BDMUPR_MREP_Msk         (0x1UL << HRTIM_BDMUPR_MREP_Pos)         /*!< 0x00000020 */

+#define HRTIM_BDMUPR_MREP             HRTIM_BDMUPR_MREP_Msk                    /*!< MREP register update enable */

+#define HRTIM_BDMUPR_MCMP1_Pos        (6U)

+#define HRTIM_BDMUPR_MCMP1_Msk        (0x1UL << HRTIM_BDMUPR_MCMP1_Pos)        /*!< 0x00000040 */

+#define HRTIM_BDMUPR_MCMP1            HRTIM_BDMUPR_MCMP1_Msk                   /*!< MCMP1 register update enable */

+#define HRTIM_BDMUPR_MCMP2_Pos        (7U)

+#define HRTIM_BDMUPR_MCMP2_Msk        (0x1UL << HRTIM_BDMUPR_MCMP2_Pos)        /*!< 0x00000080 */

+#define HRTIM_BDMUPR_MCMP2            HRTIM_BDMUPR_MCMP2_Msk                   /*!< MCMP2 register update enable */

+#define HRTIM_BDMUPR_MCMP3_Pos        (8U)

+#define HRTIM_BDMUPR_MCMP3_Msk        (0x1UL << HRTIM_BDMUPR_MCMP3_Pos)        /*!< 0x00000100 */

+#define HRTIM_BDMUPR_MCMP3            HRTIM_BDMUPR_MCMP3_Msk                   /*!< MCMP3 register update enable */

+#define HRTIM_BDMUPR_MCMP4_Pos        (9U)

+#define HRTIM_BDMUPR_MCMP4_Msk        (0x1UL << HRTIM_BDMUPR_MCMP4_Pos)        /*!< 0x00000200 */

+#define HRTIM_BDMUPR_MCMP4            HRTIM_BDMUPR_MCMP4_Msk                   /*!< MPCMP4 register update enable */

+

+/*******************  Bit definition for HRTIM_BDTUPR register  ***************/

+#define HRTIM_BDTUPR_TIMCR_Pos        (0U)

+#define HRTIM_BDTUPR_TIMCR_Msk        (0x1UL << HRTIM_BDTUPR_TIMCR_Pos)        /*!< 0x00000001 */

+#define HRTIM_BDTUPR_TIMCR            HRTIM_BDTUPR_TIMCR_Msk                   /*!<  TIMCR register update enable */

+#define HRTIM_BDTUPR_TIMICR_Pos       (1U)

+#define HRTIM_BDTUPR_TIMICR_Msk       (0x1UL << HRTIM_BDTUPR_TIMICR_Pos)       /*!< 0x00000002 */

+#define HRTIM_BDTUPR_TIMICR           HRTIM_BDTUPR_TIMICR_Msk                  /*!<  TIMICR register update enable */

+#define HRTIM_BDTUPR_TIMDIER_Pos      (2U)

+#define HRTIM_BDTUPR_TIMDIER_Msk      (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos)      /*!< 0x00000004 */

+#define HRTIM_BDTUPR_TIMDIER          HRTIM_BDTUPR_TIMDIER_Msk                 /*!<  TIMDIER register update enable */

+#define HRTIM_BDTUPR_TIMCNT_Pos       (3U)

+#define HRTIM_BDTUPR_TIMCNT_Msk       (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos)       /*!< 0x00000008 */

+#define HRTIM_BDTUPR_TIMCNT           HRTIM_BDTUPR_TIMCNT_Msk                  /*!<  TIMCNT register update enable */

+#define HRTIM_BDTUPR_TIMPER_Pos       (4U)

+#define HRTIM_BDTUPR_TIMPER_Msk       (0x1UL << HRTIM_BDTUPR_TIMPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_BDTUPR_TIMPER           HRTIM_BDTUPR_TIMPER_Msk                  /*!<  TIMPER register update enable */

+#define HRTIM_BDTUPR_TIMREP_Pos       (5U)

+#define HRTIM_BDTUPR_TIMREP_Msk       (0x1UL << HRTIM_BDTUPR_TIMREP_Pos)       /*!< 0x00000020 */

+#define HRTIM_BDTUPR_TIMREP           HRTIM_BDTUPR_TIMREP_Msk                  /*!<  TIMREP register update enable */

+#define HRTIM_BDTUPR_TIMCMP1_Pos      (6U)

+#define HRTIM_BDTUPR_TIMCMP1_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos)      /*!< 0x00000040 */

+#define HRTIM_BDTUPR_TIMCMP1          HRTIM_BDTUPR_TIMCMP1_Msk                 /*!<  TIMCMP1 register update enable */

+#define HRTIM_BDTUPR_TIMCMP2_Pos      (7U)

+#define HRTIM_BDTUPR_TIMCMP2_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos)      /*!< 0x00000080 */

+#define HRTIM_BDTUPR_TIMCMP2          HRTIM_BDTUPR_TIMCMP2_Msk                 /*!<  TIMCMP2 register update enable */

+#define HRTIM_BDTUPR_TIMCMP3_Pos      (8U)

+#define HRTIM_BDTUPR_TIMCMP3_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos)      /*!< 0x00000100 */

+#define HRTIM_BDTUPR_TIMCMP3          HRTIM_BDTUPR_TIMCMP3_Msk                 /*!<  TIMCMP3 register update enable */

+#define HRTIM_BDTUPR_TIMCMP4_Pos      (9U)

+#define HRTIM_BDTUPR_TIMCMP4_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos)      /*!< 0x00000200 */

+#define HRTIM_BDTUPR_TIMCMP4          HRTIM_BDTUPR_TIMCMP4_Msk                 /*!<  TIMCMP4 register update enable */

+#define HRTIM_BDTUPR_TIMDTR_Pos       (10U)

+#define HRTIM_BDTUPR_TIMDTR_Msk       (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos)       /*!< 0x00000400 */

+#define HRTIM_BDTUPR_TIMDTR           HRTIM_BDTUPR_TIMDTR_Msk                  /*!<  TIMDTR register update enable */

+#define HRTIM_BDTUPR_TIMSET1R_Pos     (11U)

+#define HRTIM_BDTUPR_TIMSET1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos)     /*!< 0x00000800 */

+#define HRTIM_BDTUPR_TIMSET1R         HRTIM_BDTUPR_TIMSET1R_Msk                /*!<  TIMSET1R register update enable */

+#define HRTIM_BDTUPR_TIMRST1R_Pos     (12U)

+#define HRTIM_BDTUPR_TIMRST1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos)     /*!< 0x00001000 */

+#define HRTIM_BDTUPR_TIMRST1R         HRTIM_BDTUPR_TIMRST1R_Msk                /*!<  TIMRST1R register update enable */

+#define HRTIM_BDTUPR_TIMSET2R_Pos     (13U)

+#define HRTIM_BDTUPR_TIMSET2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos)     /*!< 0x00002000 */

+#define HRTIM_BDTUPR_TIMSET2R         HRTIM_BDTUPR_TIMSET2R_Msk                /*!<  TIMSET2R register update enable */

+#define HRTIM_BDTUPR_TIMRST2R_Pos     (14U)

+#define HRTIM_BDTUPR_TIMRST2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos)     /*!< 0x00004000 */

+#define HRTIM_BDTUPR_TIMRST2R         HRTIM_BDTUPR_TIMRST2R_Msk                /*!<  TIMRST2R register update enable */

+#define HRTIM_BDTUPR_TIMEEFR1_Pos     (15U)

+#define HRTIM_BDTUPR_TIMEEFR1_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos)     /*!< 0x00008000 */

+#define HRTIM_BDTUPR_TIMEEFR1         HRTIM_BDTUPR_TIMEEFR1_Msk                /*!<  TIMEEFR1 register update enable */

+#define HRTIM_BDTUPR_TIMEEFR2_Pos     (16U)

+#define HRTIM_BDTUPR_TIMEEFR2_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos)     /*!< 0x00010000 */

+#define HRTIM_BDTUPR_TIMEEFR2         HRTIM_BDTUPR_TIMEEFR2_Msk                /*!<  TIMEEFR2 register update enable */

+#define HRTIM_BDTUPR_TIMRSTR_Pos      (17U)

+#define HRTIM_BDTUPR_TIMRSTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos)      /*!< 0x00020000 */

+#define HRTIM_BDTUPR_TIMRSTR          HRTIM_BDTUPR_TIMRSTR_Msk                 /*!<  TIMRSTR register update enable */

+#define HRTIM_BDTUPR_TIMCHPR_Pos      (18U)

+#define HRTIM_BDTUPR_TIMCHPR_Msk      (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos)      /*!< 0x00040000 */

+#define HRTIM_BDTUPR_TIMCHPR          HRTIM_BDTUPR_TIMCHPR_Msk                 /*!<  TIMCHPR register update enable */

+#define HRTIM_BDTUPR_TIMOUTR_Pos      (19U)

+#define HRTIM_BDTUPR_TIMOUTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos)      /*!< 0x00080000 */

+#define HRTIM_BDTUPR_TIMOUTR          HRTIM_BDTUPR_TIMOUTR_Msk                 /*!<  TIMOUTR register update enable */

+#define HRTIM_BDTUPR_TIMFLTR_Pos      (20U)

+#define HRTIM_BDTUPR_TIMFLTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos)      /*!< 0x00100000 */

+#define HRTIM_BDTUPR_TIMFLTR          HRTIM_BDTUPR_TIMFLTR_Msk                 /*!<  TIMFLTR register update enable */

+

+/*******************  Bit definition for HRTIM_BDMADR register  ***************/

+#define HRTIM_BDMADR_BDMADR_Pos       (0U)

+#define HRTIM_BDMADR_BDMADR_Msk       (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos) /*!< 0xFFFFFFFF */

+#define HRTIM_BDMADR_BDMADR           HRTIM_BDMADR_BDMADR_Msk                  /*!<  Burst DMA Data register */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             RAM ECC monitoring                             */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for RAMECC_IER register  ******************/

+#define RAMECC_IER_GECCDEBWIE_Pos         (3U)

+#define RAMECC_IER_GECCDEBWIE_Msk         (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)  /*!< 0x00000008 */

+#define RAMECC_IER_GECCDEBWIE             RAMECC_IER_GECCDEBWIE_Msk             /*!< Global ECC double error on byte write (BW) interrupt enable */

+#define RAMECC_IER_GECCDEIE_Pos           (2U)

+#define RAMECC_IER_GECCDEIE_Msk           (0x1UL << RAMECC_IER_GECCDEIE_Pos)    /*!< 0x00000004 */

+#define RAMECC_IER_GECCDEIE               RAMECC_IER_GECCDEIE_Msk               /*!< Global ECC double error interrupt enable */

+#define RAMECC_IER_GECCSEIE_Pos           (1U)

+#define RAMECC_IER_GECCSEIE_Msk           (0x1UL << RAMECC_IER_GECCSEIE_Pos)    /*!< 0x00000002 */

+#define RAMECC_IER_GECCSEIE               RAMECC_IER_GECCSEIE_Msk               /*!< Global ECC single error interrupt enable */

+#define RAMECC_IER_GIE_Pos                (0U)

+#define RAMECC_IER_GIE_Msk                (0x1UL << RAMECC_IER_GIE_Pos)         /*!< 0x00000001 */

+#define RAMECC_IER_GIE                    RAMECC_IER_GIE_Msk                    /*!< Global interrupt enable */

+

+/*******************  Bit definition for RAMECC_CR register  ******************/

+#define RAMECC_CR_ECCELEN_Pos             (5U)

+#define RAMECC_CR_ECCELEN_Msk             (0x1UL << RAMECC_CR_ECCELEN_Pos)      /*!< 0x00000020 */

+#define RAMECC_CR_ECCELEN                 RAMECC_CR_ECCELEN_Msk                 /*!< ECC error latching enable */

+#define RAMECC_CR_ECCDEBWIE_Pos           (4U)

+#define RAMECC_CR_ECCDEBWIE_Msk           (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)    /*!< 0x00000010 */

+#define RAMECC_CR_ECCDEBWIE               RAMECC_CR_ECCDEBWIE_Msk               /*!< ECC double error on byte write (BW) interrupt enable */

+#define RAMECC_CR_ECCDEIE_Pos             (3U)

+#define RAMECC_CR_ECCDEIE_Msk             (0x1UL << RAMECC_CR_ECCDEIE_Pos)      /*!< 0x00000008 */

+#define RAMECC_CR_ECCDEIE                 RAMECC_CR_ECCDEIE_Msk                 /*!< ECC double error interrupt enable */

+#define RAMECC_CR_ECCSEIE_Pos             (2U)

+#define RAMECC_CR_ECCSEIE_Msk             (0x1UL << RAMECC_CR_ECCSEIE_Pos)      /*!< 0x00000004 */

+#define RAMECC_CR_ECCSEIE                 RAMECC_CR_ECCSEIE_Msk                 /*!< ECC single error interrupt enable */

+

+/*******************  Bit definition for RAMECC_SR register  ******************/

+#define RAMECC_SR_DEBWDF_Pos             (2U)

+#define RAMECC_SR_DEBWDF_Msk             (0x1UL << RAMECC_SR_DEBWDF_Pos)        /*!< 0x00000004 */

+#define RAMECC_SR_DEBWDF                 RAMECC_SR_DEBWDF_Msk                   /*!< ECC double error on byte write (BW) detected flag */

+#define RAMECC_SR_DEDF_Pos               (1U)

+#define RAMECC_SR_DEDF_Msk               (0x1UL << RAMECC_SR_DEDF_Pos)          /*!< 0x00000002 */

+#define RAMECC_SR_DEDF                   RAMECC_SR_DEDF_Msk                     /*!< ECC double error detected flag */

+#define RAMECC_SR_SEDCF_Pos              (0U)

+#define RAMECC_SR_SEDCF_Msk              (0x1UL << RAMECC_SR_SEDCF_Pos)         /*!< 0x00000001 */

+#define RAMECC_SR_SEDCF                  RAMECC_SR_SEDCF_Msk                    /*!< ECC single error detected and corrected flag */

+

+/******************  Bit definition for RAMECC_FAR register  ******************/

+#define RAMECC_FAR_FADD_Pos              (0U)

+#define RAMECC_FAR_FADD_Msk              (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)  /*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FADD                  RAMECC_FAR_FADD_Msk                    /*!< ECC error failing address */

+

+/******************  Bit definition for RAMECC_FDRL register  *****************/

+#define RAMECC_FAR_FDATAL_Pos            (0U)

+#define RAMECC_FAR_FDATAL_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FDATAL                RAMECC_FAR_FDATAL_Msk                  /*!< ECC error failing address */

+

+/******************  Bit definition for RAMECC_FDRH register  *****************/

+#define RAMECC_FAR_FDATAH_Pos            (0U)

+#define RAMECC_FAR_FDATAH_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FDATAH                RAMECC_FAR_FDATAH_Msk                  /* Failing data high (64-bit memory) */

+

+/*****************  Bit definition for RAMECC_FECR register  ******************/

+#define RAMECC_FECR_FEC_Pos              (0U)

+#define RAMECC_FECR_FEC_Msk              (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)  /*!< 0xFFFFFFFF */

+#define RAMECC_FECR_FEC                  RAMECC_FECR_FEC_Msk                    /*!< Failing error code */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                MDIOS                                        */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for MDIOS_CR register  *******************/

+#define MDIOS_CR_EN_Pos                (0U)

+#define MDIOS_CR_EN_Msk                (0x1UL << MDIOS_CR_EN_Pos)              /*!< 0x00000001 */

+#define MDIOS_CR_EN                    MDIOS_CR_EN_Msk                         /*!<  MDIOS slave peripheral enable */

+#define MDIOS_CR_WRIE_Pos              (1U)

+#define MDIOS_CR_WRIE_Msk              (0x1UL << MDIOS_CR_WRIE_Pos)            /*!< 0x00000002 */

+#define MDIOS_CR_WRIE                  MDIOS_CR_WRIE_Msk                       /*!<  MDIOS slave register write interrupt enable. */

+#define MDIOS_CR_RDIE_Pos              (2U)

+#define MDIOS_CR_RDIE_Msk              (0x1UL << MDIOS_CR_RDIE_Pos)            /*!< 0x00000004 */

+#define MDIOS_CR_RDIE                  MDIOS_CR_RDIE_Msk                       /*!<  MDIOS slave register read interrupt enable. */

+#define MDIOS_CR_EIE_Pos               (3U)

+#define MDIOS_CR_EIE_Msk               (0x1UL << MDIOS_CR_EIE_Pos)             /*!< 0x00000008 */

+#define MDIOS_CR_EIE                   MDIOS_CR_EIE_Msk                        /*!<  MDIOS slave register error interrupt enable. */

+#define MDIOS_CR_DPC_Pos               (7U)

+#define MDIOS_CR_DPC_Msk               (0x1UL << MDIOS_CR_DPC_Pos)             /*!< 0x00000080 */

+#define MDIOS_CR_DPC                   MDIOS_CR_DPC_Msk                        /*!<  MDIOS slave disable preamble check. */

+#define MDIOS_CR_PORT_ADDRESS_Pos      (8U)

+#define MDIOS_CR_PORT_ADDRESS_Msk      (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)   /*!< 0x00001F00 */

+#define MDIOS_CR_PORT_ADDRESS          MDIOS_CR_PORT_ADDRESS_Msk               /*!<  MDIOS slave port address mask. */

+#define MDIOS_CR_PORT_ADDRESS_0        (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000100 */

+#define MDIOS_CR_PORT_ADDRESS_1        (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000200 */

+#define MDIOS_CR_PORT_ADDRESS_2        (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000400 */

+#define MDIOS_CR_PORT_ADDRESS_3        (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000800 */

+#define MDIOS_CR_PORT_ADDRESS_4        (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001000 */

+

+/********************  Bit definition for MDIOS_SR register  *******************/

+#define MDIOS_SR_PERF_Pos              (0U)

+#define MDIOS_SR_PERF_Msk              (0x1UL << MDIOS_SR_PERF_Pos)            /*!< 0x00000001 */

+#define MDIOS_SR_PERF                  MDIOS_SR_PERF_Msk                       /*!<  MDIOS slave turnaround error flag*/

+#define MDIOS_SR_SERF_Pos              (1U)

+#define MDIOS_SR_SERF_Msk              (0x1UL << MDIOS_SR_SERF_Pos)            /*!< 0x00000002 */

+#define MDIOS_SR_SERF                  MDIOS_SR_SERF_Msk                       /*!<  MDIOS slave start error flag */

+#define MDIOS_SR_TERF_Pos              (2U)

+#define MDIOS_SR_TERF_Msk              (0x1UL << MDIOS_SR_TERF_Pos)            /*!< 0x00000004 */

+#define MDIOS_SR_TERF                  MDIOS_SR_TERF_Msk                       /*!<  MDIOS slave preamble error flag */

+

+/********************  Bit definition for MDIOS_CLRFR register  *******************/

+#define MDIOS_SR_CPERF_Pos             (0U)

+#define MDIOS_SR_CPERF_Msk             (0x1UL << MDIOS_SR_CPERF_Pos)           /*!< 0x00000001 */

+#define MDIOS_SR_CPERF                 MDIOS_SR_CPERF_Msk                      /*!<  MDIOS slave Clear the turnaround error flag */

+#define MDIOS_SR_CSERF_Pos             (1U)

+#define MDIOS_SR_CSERF_Msk             (0x1UL << MDIOS_SR_CSERF_Pos)           /*!< 0x00000002 */

+#define MDIOS_SR_CSERF                 MDIOS_SR_CSERF_Msk                      /*!<  MDIOS slave Clear the start error flag */

+#define MDIOS_SR_CTERF_Pos             (2U)

+#define MDIOS_SR_CTERF_Msk             (0x1UL << MDIOS_SR_CTERF_Pos)           /*!< 0x00000004 */

+#define MDIOS_SR_CTERF                 MDIOS_SR_CTERF_Msk                      /*!<  MDIOS slave Clear the preamble error flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                       USB_OTG                              */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/

+#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)

+#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */

+#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */

+#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)

+#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */

+#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */

+#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)

+#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */

+#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */

+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)

+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */

+#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */

+#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)

+#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */

+#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */

+#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)

+#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */

+#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */

+#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)

+#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */

+#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */

+#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)

+#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */

+#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */

+#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)

+#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */

+#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */

+#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)

+#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */

+#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */

+#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)

+#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */

+#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */

+#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)

+#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */

+#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */

+#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)

+#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */

+#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */

+#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)

+#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */

+#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */

+#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)

+#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */

+#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */

+#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)

+#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */

+#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */

+#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)

+#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */

+#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */

+#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)

+#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */

+#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */

+

+/********************  Bit definition forUSB_OTG_HCFG register  ********************/

+

+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)

+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */

+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */

+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)

+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */

+

+/********************  Bit definition forUSB_OTG_DCFG register  ********************/

+

+#define USB_OTG_DCFG_DSPD_Pos                    (0U)

+#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */

+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */

+#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */

+#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)

+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */

+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */

+

+#define USB_OTG_DCFG_DAD_Pos                     (4U)

+#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */

+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */

+#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */

+#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */

+#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */

+#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */

+#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */

+#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */

+#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */

+

+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)

+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */

+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */

+#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */

+#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */

+

+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)

+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */

+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */

+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */

+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */

+

+/********************  Bit definition forUSB_OTG_PCGCR register  ********************/

+#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)

+#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */

+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */

+#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)

+#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */

+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */

+#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)

+#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */

+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */

+

+/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/

+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)

+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */

+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */

+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)

+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */

+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */

+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)

+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */

+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */

+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)

+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */

+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */

+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)

+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */

+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */

+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)

+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */

+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */

+

+/********************  Bit definition forUSB_OTG_DCTL register  ********************/

+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)

+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */

+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */

+#define USB_OTG_DCTL_SDIS_Pos                    (1U)

+#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */

+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */

+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)

+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */

+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */

+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)

+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */

+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */

+

+#define USB_OTG_DCTL_TCTL_Pos                    (4U)

+#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */

+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */

+#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */

+#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */

+#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */

+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)

+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */

+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */

+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)

+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */

+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */

+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)

+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */

+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */

+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)

+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */

+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */

+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)

+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */

+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */

+

+/********************  Bit definition forUSB_OTG_HFIR register  ********************/

+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)

+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */

+

+/********************  Bit definition forUSB_OTG_HFNUM register  ********************/

+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)

+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */

+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)

+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */

+

+/********************  Bit definition forUSB_OTG_DSTS register  ********************/

+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)

+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */

+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */

+

+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)

+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */

+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */

+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */

+#define USB_OTG_DSTS_EERR_Pos                    (3U)

+#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */

+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */

+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)

+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */

+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */

+

+/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/

+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)

+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */

+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */

+

+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)

+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */

+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */

+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */

+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */

+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */

+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */

+#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */

+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)

+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */

+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */

+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)

+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */

+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */

+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)

+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */

+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */

+

+/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/

+

+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)

+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */

+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */

+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */

+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */

+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */

+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)

+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */

+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */

+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)

+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */

+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */

+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)

+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */

+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */

+

+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)

+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */

+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */

+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */

+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */

+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */

+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */

+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)

+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */

+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */

+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)

+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */

+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */

+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)

+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */

+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */

+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)

+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */

+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */

+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)

+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */

+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */

+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)

+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */

+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */

+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)

+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */

+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */

+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)

+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */

+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */

+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)

+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */

+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */

+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)

+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */

+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */

+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)

+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */

+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */

+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)

+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */

+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */

+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)

+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */

+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */

+

+/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/

+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)

+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */

+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */

+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)

+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */

+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */

+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)

+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */

+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */

+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)

+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */

+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */

+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)

+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */

+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */

+

+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)

+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */

+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */

+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */

+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */

+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */

+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */

+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */

+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)

+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */

+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */

+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)

+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */

+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */

+

+/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/

+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)

+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */

+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)

+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */

+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)

+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */

+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)

+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */

+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)

+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */

+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)

+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */

+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)

+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */

+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)

+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */

+

+/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/

+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)

+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */

+

+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)

+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */

+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */

+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */

+

+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)

+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */

+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */

+

+/********************  Bit definition forUSB_OTG_HAINT register  ********************/

+#define USB_OTG_HAINT_HAINT_Pos                  (0U)

+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */

+

+/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/

+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)

+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */

+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)

+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */

+#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)

+#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */

+#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask               */

+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)

+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */

+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)

+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */

+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)

+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */

+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)

+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */

+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)

+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */

+#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)

+#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */

+#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)

+#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask               */

+#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)

+#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask               */

+#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)

+#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                */

+

+/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/

+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)

+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */

+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */

+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)

+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */

+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */

+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)

+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */

+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */

+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)

+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */

+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */

+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)

+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */

+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */

+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)

+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */

+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */

+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)

+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */

+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */

+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)

+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */

+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */

+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)

+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */

+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */

+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)

+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */

+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */

+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)

+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */

+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */

+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)

+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */

+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */

+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)

+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */

+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */

+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)

+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */

+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */

+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)

+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */

+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */

+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)

+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */

+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */

+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)

+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */

+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */

+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)

+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */

+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */

+#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)

+#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */

+#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */

+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)

+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */

+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */

+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)

+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */

+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */

+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)

+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */

+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */

+#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)

+#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */

+#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */

+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)

+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */

+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */

+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)

+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */

+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */

+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)

+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */

+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */

+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)

+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */

+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */

+

+/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/

+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)

+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */

+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */

+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)

+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */

+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */

+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)

+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */

+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */

+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)

+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */

+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */

+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)

+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */

+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */

+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)

+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */

+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */

+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)

+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */

+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */

+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)

+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */

+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */

+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)

+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */

+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */

+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)

+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */

+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */

+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)

+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */

+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */

+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)

+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */

+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */

+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)

+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */

+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */

+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)

+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */

+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */

+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)

+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */

+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */

+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)

+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */

+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */

+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)

+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */

+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */

+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)

+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */

+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */

+#define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)

+#define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */

+#define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */

+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)

+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */

+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */

+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)

+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */

+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */

+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)

+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */

+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */

+#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)

+#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */

+#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */

+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)

+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */

+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */

+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)

+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */

+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */

+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)

+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */

+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */

+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)

+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */

+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */

+

+/********************  Bit definition forUSB_OTG_DAINT register  ********************/

+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)

+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */

+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)

+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */

+

+/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/

+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)

+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */

+

+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/

+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)

+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */

+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */

+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)

+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */

+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */

+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)

+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */

+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */

+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)

+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */

+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */

+

+/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/

+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)

+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */

+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)

+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */

+

+/********************  Bit definition for OTG register  ********************/

+

+#define USB_OTG_CHNUM_Pos                        (0U)

+#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)  /*!< 0x0000000F */

+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */

+#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */

+#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */

+#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */

+#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */

+#define USB_OTG_BCNT_Pos                         (4U)

+#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */

+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */

+

+#define USB_OTG_DPID_Pos                         (15U)

+#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)   /*!< 0x00018000 */

+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */

+#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */

+#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */

+

+#define USB_OTG_PKTSTS_Pos                       (17U)

+#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */

+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */

+#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */

+#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */

+#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */

+#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */

+

+#define USB_OTG_EPNUM_Pos                        (0U)

+#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)  /*!< 0x0000000F */

+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */

+#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */

+#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */

+#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */

+#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */

+

+#define USB_OTG_FRMNUM_Pos                       (21U)

+#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */

+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */

+#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */

+#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */

+#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */

+#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */

+

+/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/

+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)

+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/

+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)

+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */

+

+/********************  Bit definition for OTG register  ********************/

+#define USB_OTG_NPTXFSA_Pos                      (0U)

+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */

+#define USB_OTG_NPTXFD_Pos                       (16U)

+#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */

+#define USB_OTG_TX0FSA_Pos                       (0U)

+#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */

+#define USB_OTG_TX0FD_Pos                        (16U)

+#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */

+

+/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/

+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)

+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */

+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */

+

+/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/

+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)

+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */

+

+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)

+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */

+

+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)

+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/

+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)

+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */

+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */

+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)

+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */

+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */

+

+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)

+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */

+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */

+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */

+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)

+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */

+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */

+

+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)

+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */

+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */

+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)

+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */

+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */

+

+/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */

+

+/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/

+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)

+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */

+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */

+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)

+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */

+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */

+

+/********************  Bit definition forUSB_OTG_GCCFG register  ********************/

+#define USB_OTG_GCCFG_DCDET_Pos                  (0U)

+#define USB_OTG_GCCFG_DCDET_Msk                  (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */

+#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */

+#define USB_OTG_GCCFG_PDET_Pos                   (1U)

+#define USB_OTG_GCCFG_PDET_Msk                   (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */

+#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */

+#define USB_OTG_GCCFG_SDET_Pos                   (2U)

+#define USB_OTG_GCCFG_SDET_Msk                   (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */

+#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */

+#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)

+#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */

+#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */

+#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)

+#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */

+#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */

+#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)

+#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */

+#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */

+#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)

+#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */

+#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/

+#define USB_OTG_GCCFG_PDEN_Pos                   (19U)

+#define USB_OTG_GCCFG_PDEN_Msk                   (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */

+#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/

+#define USB_OTG_GCCFG_SDEN_Pos                   (20U)

+#define USB_OTG_GCCFG_SDEN_Msk                   (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */

+#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */

+#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)

+#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */

+#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */

+

+/********************  Bit definition forUSB_OTG_GPWRDN) register  ********************/

+#define USB_OTG_GPWRDN_ADPMEN_Pos                (0U)

+#define USB_OTG_GPWRDN_ADPMEN_Msk                (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */

+#define USB_OTG_GPWRDN_ADPMEN                    USB_OTG_GPWRDN_ADPMEN_Msk     /*!< ADP module enable */

+#define USB_OTG_GPWRDN_ADPIF_Pos                 (23U)

+#define USB_OTG_GPWRDN_ADPIF_Msk                 (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */

+#define USB_OTG_GPWRDN_ADPIF                     USB_OTG_GPWRDN_ADPIF_Msk      /*!< ADP Interrupt flag */

+

+/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/

+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)

+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */

+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)

+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */

+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */

+

+/********************  Bit definition forUSB_OTG_CID register  ********************/

+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)

+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */

+

+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/

+#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)

+#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */

+#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */

+#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)

+#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */

+#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */

+#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)

+#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */

+#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */

+#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)

+#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */

+#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */

+#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)

+#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */

+#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */

+#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)

+#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */

+#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */

+#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)

+#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */

+#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */

+#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)

+#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */

+#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */

+#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)

+#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */

+#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */

+#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)

+#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */

+#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */

+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)

+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */

+#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */

+#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)

+#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */

+#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */

+#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)

+#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */

+#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */

+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)

+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */

+#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */

+#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)

+#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */

+#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */

+

+/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/

+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)

+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */

+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)

+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */

+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)

+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */

+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)

+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */

+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)

+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */

+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)

+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */

+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)

+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */

+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)

+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */

+

+/********************  Bit definition forUSB_OTG_HPRT register  ********************/

+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)

+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */

+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */

+#define USB_OTG_HPRT_PCDET_Pos                   (1U)

+#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */

+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */

+#define USB_OTG_HPRT_PENA_Pos                    (2U)

+#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */

+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */

+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)

+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */

+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */

+#define USB_OTG_HPRT_POCA_Pos                    (4U)

+#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */

+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */

+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)

+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */

+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */

+#define USB_OTG_HPRT_PRES_Pos                    (6U)

+#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */

+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume   */

+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)

+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */

+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend  */

+#define USB_OTG_HPRT_PRST_Pos                    (8U)

+#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */

+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset    */

+

+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)

+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */

+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */

+#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */

+#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */

+#define USB_OTG_HPRT_PPWR_Pos                    (12U)

+#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */

+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */

+

+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)

+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */

+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */

+#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */

+#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */

+#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */

+#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */

+

+#define USB_OTG_HPRT_PSPD_Pos                    (17U)

+#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */

+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */

+#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */

+#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */

+

+/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/

+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)

+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)

+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)

+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */

+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)

+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */

+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)

+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */

+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)

+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */

+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)

+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)

+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)

+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)

+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */

+

+/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/

+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)

+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */

+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)

+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/

+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)

+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */

+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)

+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */

+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */

+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)

+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */

+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */

+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)

+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */

+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */

+

+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)

+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */

+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */

+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)

+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */

+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */

+

+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)

+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */

+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */

+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */

+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */

+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */

+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */

+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)

+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */

+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */

+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)

+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */

+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */

+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)

+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */

+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)

+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */

+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)

+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */

+

+/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/

+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)

+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */

+

+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)

+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */

+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */

+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */

+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */

+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */

+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */

+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)

+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */

+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */

+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)

+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */

+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */

+

+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)

+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */

+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */

+

+#define USB_OTG_HCCHAR_MC_Pos                    (20U)

+#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */

+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */

+#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */

+#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */

+

+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)

+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */

+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */

+#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */

+#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */

+#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */

+#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */

+#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */

+#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */

+#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */

+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)

+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */

+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)

+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */

+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)

+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */

+

+/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/

+

+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)

+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */

+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */

+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */

+

+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)

+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */

+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */

+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */

+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */

+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */

+

+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)

+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */

+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */

+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */

+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */

+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)

+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */

+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */

+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)

+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */

+

+/********************  Bit definition forUSB_OTG_HCINT register  ********************/

+#define USB_OTG_HCINT_XFRC_Pos                   (0U)

+#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */

+#define USB_OTG_HCINT_CHH_Pos                    (1U)

+#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */

+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)

+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */

+#define USB_OTG_HCINT_STALL_Pos                  (3U)

+#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */

+#define USB_OTG_HCINT_NAK_Pos                    (4U)

+#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */

+#define USB_OTG_HCINT_ACK_Pos                    (5U)

+#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */

+#define USB_OTG_HCINT_NYET_Pos                   (6U)

+#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */

+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */

+#define USB_OTG_HCINT_TXERR_Pos                  (7U)

+#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */

+#define USB_OTG_HCINT_BBERR_Pos                  (8U)

+#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */

+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)

+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */

+#define USB_OTG_HCINT_DTERR_Pos                  (10U)

+#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */

+

+/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/

+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)

+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */

+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)

+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */

+#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)

+#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */

+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)

+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */

+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)

+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */

+#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)

+#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */

+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)

+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */

+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)

+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */

+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */

+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)

+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */

+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)

+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */

+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)

+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */

+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */

+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)

+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */

+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */

+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)

+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */

+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */

+

+/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/

+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)

+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */

+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)

+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */

+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)

+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */

+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)

+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */

+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)

+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */

+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)

+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */

+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)

+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */

+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */

+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)

+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */

+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)

+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */

+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)

+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */

+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)

+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */

+

+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/

+

+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)

+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */

+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)

+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */

+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)

+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */

+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */

+/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/

+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)

+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */

+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)

+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */

+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)

+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */

+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)

+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */

+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */

+#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */

+#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/

+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)

+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */

+

+/********************  Bit definition forUSB_OTG_HCDMA register  ********************/

+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)

+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */

+

+/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/

+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)

+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */

+

+/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/

+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)

+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */

+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)

+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/

+

+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)

+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */

+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)

+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */

+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */

+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)

+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */

+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */

+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)

+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */

+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)

+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */

+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */

+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)

+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */

+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */

+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)

+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */

+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */

+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)

+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */

+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */

+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)

+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */

+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */

+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)

+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */

+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)

+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */

+

+/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/

+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)

+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */

+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)

+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */

+#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)

+#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */

+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)

+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */

+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)

+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */

+#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)

+#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< OUT Status Phase Received interrupt */

+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)

+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */

+#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)

+#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */

+#define USB_OTG_DOEPINT_BERR_Pos                 (12U)

+#define USB_OTG_DOEPINT_BERR_Msk                 (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPINT_BERR                      USB_OTG_DOEPINT_BERR_Msk   /*!< Babble error interrupt */

+#define USB_OTG_DOEPINT_NAK_Pos                  (13U)

+#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */

+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)

+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */

+#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)

+#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */

+#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */

+

+/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/

+

+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)

+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */

+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)

+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */

+

+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)

+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */

+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */

+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */

+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition for PCGCCTL register  ********************/

+#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)

+#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */

+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */

+#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)

+#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */

+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */

+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)

+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */

+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/** @addtogroup Exported_macros

+  * @{

+  */

+

+/******************************* ADC Instances ********************************/

+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \

+                                       ((INSTANCE) == ADC2) || \

+                                       ((INSTANCE) == ADC3))

+

+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)

+

+#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) ||\

+                                          ((INSTANCE) == ADC3_COMMON))

+

+/******************************** COMP Instances ******************************/

+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \

+                                       ((INSTANCE) == COMP2))

+

+#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)

+/******************** COMP Instances with window mode capability **************/

+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)

+

+

+/******************************* CRC Instances ********************************/

+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

+

+/******************************* DAC Instances ********************************/

+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)

+/******************************* DCMI Instances *******************************/

+#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)

+

+/******************************* DELAYBLOCK Instances *******************************/

+#define IS_DLYB_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DLYB_SDMMC1) || \

+                                         ((INSTANCE) == DLYB_SDMMC2) || \

+                                         ((INSTANCE) == DLYB_QUADSPI))

+/****************************** DFSDM Instances *******************************/

+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \

+                                               ((INSTANCE) == DFSDM1_Filter1) || \

+                                               ((INSTANCE) == DFSDM1_Filter2) || \

+                                               ((INSTANCE) == DFSDM1_Filter3))

+

+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \

+                                                 ((INSTANCE) == DFSDM1_Channel1) || \

+                                                 ((INSTANCE) == DFSDM1_Channel2) || \

+                                                 ((INSTANCE) == DFSDM1_Channel3) || \

+                                                 ((INSTANCE) == DFSDM1_Channel4) || \

+                                                 ((INSTANCE) == DFSDM1_Channel5) || \

+                                                 ((INSTANCE) == DFSDM1_Channel6) || \

+                                                 ((INSTANCE) == DFSDM1_Channel7))

+/****************************** RAMECC Instances ******************************/

+#define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC1_Monitor1)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor2)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor3)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor4)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor5)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor1)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor2)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor3)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor4)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor5)   || \

+                                                  ((INSTANCE) == RAMECC3_Monitor1)   || \

+                                                  ((INSTANCE) == RAMECC3_Monitor2))

+

+/******************************** DMA Instances *******************************/

+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \

+                                       ((INSTANCE) == DMA1_Stream1)   || \

+                                       ((INSTANCE) == DMA1_Stream2)   || \

+                                       ((INSTANCE) == DMA1_Stream3)   || \

+                                       ((INSTANCE) == DMA1_Stream4)   || \

+                                       ((INSTANCE) == DMA1_Stream5)   || \

+                                       ((INSTANCE) == DMA1_Stream6)   || \

+                                       ((INSTANCE) == DMA1_Stream7)   || \

+                                       ((INSTANCE) == DMA2_Stream0)   || \

+                                       ((INSTANCE) == DMA2_Stream1)   || \

+                                       ((INSTANCE) == DMA2_Stream2)   || \

+                                       ((INSTANCE) == DMA2_Stream3)   || \

+                                       ((INSTANCE) == DMA2_Stream4)   || \

+                                       ((INSTANCE) == DMA2_Stream5)   || \

+                                       ((INSTANCE) == DMA2_Stream6)   || \

+                                       ((INSTANCE) == DMA2_Stream7)   || \

+                                       ((INSTANCE) == BDMA_Channel0) || \

+                                       ((INSTANCE) == BDMA_Channel1) || \

+                                       ((INSTANCE) == BDMA_Channel2) || \

+                                       ((INSTANCE) == BDMA_Channel3) || \

+                                       ((INSTANCE) == BDMA_Channel4) || \

+                                       ((INSTANCE) == BDMA_Channel5) || \

+                                       ((INSTANCE) == BDMA_Channel6) || \

+                                       ((INSTANCE) == BDMA_Channel7))

+

+/****************************** BDMA CHANNEL Instances ***************************/

+#define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \

+                                            ((INSTANCE) == BDMA_Channel1) || \

+                                            ((INSTANCE) == BDMA_Channel2) || \

+                                            ((INSTANCE) == BDMA_Channel3) || \

+                                            ((INSTANCE) == BDMA_Channel4) || \

+                                            ((INSTANCE) == BDMA_Channel5) || \

+                                            ((INSTANCE) == BDMA_Channel6) || \

+                                            ((INSTANCE) == BDMA_Channel7))

+

+/****************************** DMA DMAMUX ALL Instances ***************************/

+#define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)    || \

+                                               ((INSTANCE) == DMA1_Stream1)    || \

+                                               ((INSTANCE) == DMA1_Stream2)    || \

+                                               ((INSTANCE) == DMA1_Stream3)    || \

+                                               ((INSTANCE) == DMA1_Stream4)    || \

+                                               ((INSTANCE) == DMA1_Stream5)    || \

+                                               ((INSTANCE) == DMA1_Stream6)    || \

+                                               ((INSTANCE) == DMA1_Stream7)    || \

+                                               ((INSTANCE) == DMA2_Stream0)    || \

+                                               ((INSTANCE) == DMA2_Stream1)    || \

+                                               ((INSTANCE) == DMA2_Stream2)    || \

+                                               ((INSTANCE) == DMA2_Stream3)    || \

+                                               ((INSTANCE) == DMA2_Stream4)    || \

+                                               ((INSTANCE) == DMA2_Stream5)    || \

+                                               ((INSTANCE) == DMA2_Stream6)    || \

+                                               ((INSTANCE) == DMA2_Stream7)    || \

+                                               ((INSTANCE) == BDMA_Channel0)   || \

+                                               ((INSTANCE) == BDMA_Channel1)   || \

+                                               ((INSTANCE) == BDMA_Channel2)   || \

+                                               ((INSTANCE) == BDMA_Channel3)   || \

+                                               ((INSTANCE) == BDMA_Channel4)   || \

+                                               ((INSTANCE) == BDMA_Channel5)   || \

+                                               ((INSTANCE) == BDMA_Channel6)   || \

+                                               ((INSTANCE) == BDMA_Channel7))

+

+/****************************** BDMA DMAMUX Instances ***************************/

+#define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == BDMA_Channel0) || \

+                                                    ((INSTANCE) == BDMA_Channel1) || \

+                                                    ((INSTANCE) == BDMA_Channel2) || \

+                                                    ((INSTANCE) == BDMA_Channel3) || \

+                                                    ((INSTANCE) == BDMA_Channel4) || \

+                                                    ((INSTANCE) == BDMA_Channel5) || \

+                                                    ((INSTANCE) == BDMA_Channel6) || \

+                                                    ((INSTANCE) == BDMA_Channel7))

+

+/****************************** DMA STREAM Instances ***************************/

+#define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \

+                                          ((INSTANCE) == DMA1_Stream1)   || \

+                                          ((INSTANCE) == DMA1_Stream2)   || \

+                                          ((INSTANCE) == DMA1_Stream3)   || \

+                                          ((INSTANCE) == DMA1_Stream4)   || \

+                                          ((INSTANCE) == DMA1_Stream5)   || \

+                                          ((INSTANCE) == DMA1_Stream6)   || \

+                                          ((INSTANCE) == DMA1_Stream7)   || \

+                                          ((INSTANCE) == DMA2_Stream0)   || \

+                                          ((INSTANCE) == DMA2_Stream1)   || \

+                                          ((INSTANCE) == DMA2_Stream2)   || \

+                                          ((INSTANCE) == DMA2_Stream3)   || \

+                                          ((INSTANCE) == DMA2_Stream4)   || \

+                                          ((INSTANCE) == DMA2_Stream5)   || \

+                                          ((INSTANCE) == DMA2_Stream6)   || \

+                                          ((INSTANCE) == DMA2_Stream7))

+

+/****************************** DMA DMAMUX Instances ***************************/

+#define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)   || \

+                                                  ((INSTANCE) == DMA1_Stream1)   || \

+                                                  ((INSTANCE) == DMA1_Stream2)   || \

+                                                  ((INSTANCE) == DMA1_Stream3)   || \

+                                                  ((INSTANCE) == DMA1_Stream4)   || \

+                                                  ((INSTANCE) == DMA1_Stream5)   || \

+                                                  ((INSTANCE) == DMA1_Stream6)   || \

+                                                  ((INSTANCE) == DMA1_Stream7)   || \

+                                                  ((INSTANCE) == DMA2_Stream0)   || \

+                                                  ((INSTANCE) == DMA2_Stream1)   || \

+                                                  ((INSTANCE) == DMA2_Stream2)   || \

+                                                  ((INSTANCE) == DMA2_Stream3)   || \

+                                                  ((INSTANCE) == DMA2_Stream4)   || \

+                                                  ((INSTANCE) == DMA2_Stream5)   || \

+                                                  ((INSTANCE) == DMA2_Stream6)   || \

+                                                  ((INSTANCE) == DMA2_Stream7))

+

+/******************************** DMA Request Generator Instances **************/

+#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator1) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator2) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator3) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator4) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator5) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator6) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator7) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator0) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator1) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator2) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator3) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator4) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator5) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator6) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator7))

+

+/******************************* DMA2D Instances *******************************/

+#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)

+

+/******************************** MDMA Request Generator Instances **************/

+#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0)  || \

+                                               ((INSTANCE) == MDMA_Channel1)  || \

+                                               ((INSTANCE) == MDMA_Channel2)  || \

+                                               ((INSTANCE) == MDMA_Channel3)  || \

+                                               ((INSTANCE) == MDMA_Channel4)  || \

+                                               ((INSTANCE) == MDMA_Channel5)  || \

+                                               ((INSTANCE) == MDMA_Channel6)  || \

+                                               ((INSTANCE) == MDMA_Channel7)  || \

+                                               ((INSTANCE) == MDMA_Channel8)  || \

+                                               ((INSTANCE) == MDMA_Channel9)  || \

+                                               ((INSTANCE) == MDMA_Channel10) || \

+                                               ((INSTANCE) == MDMA_Channel11) || \

+                                               ((INSTANCE) == MDMA_Channel12) || \

+                                               ((INSTANCE) == MDMA_Channel13) || \

+                                               ((INSTANCE) == MDMA_Channel14) || \

+                                               ((INSTANCE) == MDMA_Channel15))

+

+/******************************* QUADSPI Instances *******************************/

+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)

+

+/******************************* FDCAN Instances ******************************/

+#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \

+                                             ((__INSTANCE__) == FDCAN2))

+

+#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)

+

+/******************************* GPIO Instances *******************************/

+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \

+                                        ((INSTANCE) == GPIOB) || \

+                                        ((INSTANCE) == GPIOC) || \

+                                        ((INSTANCE) == GPIOD) || \

+                                        ((INSTANCE) == GPIOE) || \

+                                        ((INSTANCE) == GPIOF) || \

+                                        ((INSTANCE) == GPIOG) || \

+                                        ((INSTANCE) == GPIOH) || \

+                                        ((INSTANCE) == GPIOI) || \

+                                        ((INSTANCE) == GPIOJ) || \

+                                        ((INSTANCE) == GPIOK))

+

+/******************************* GPIO AF Instances ****************************/

+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)

+

+/**************************** GPIO Lock Instances *****************************/

+/* On H7, all GPIO Bank support the Lock mechanism */

+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)

+

+/******************************** HSEM Instances *******************************/

+#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)

+#define HSEM_CPU1_COREID         (0x00000003U) /* Semaphore Core CM7 ID */

+#define HSEM_CR_COREID_CPU1      (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)

+#define HSEM_CR_COREID_CURRENT   (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)

+

+#define HSEM_SEMID_MIN     (0U)       /* HSEM ID Min*/

+#define HSEM_SEMID_MAX     (31U)      /* HSEM ID Max */

+

+#define HSEM_PROCESSID_MIN (0U)       /* HSEM Process ID Min */

+#define HSEM_PROCESSID_MAX (255U)     /* HSEM Process ID Max */

+

+#define HSEM_CLEAR_KEY_MIN (0U)       /* HSEM clear Key Min value */

+#define HSEM_CLEAR_KEY_MAX (0xFFFFU)  /* HSEM clear Key Max value */

+

+/******************************** I2C Instances *******************************/

+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

+                                       ((INSTANCE) == I2C2) || \

+                                       ((INSTANCE) == I2C3) || \

+                                       ((INSTANCE) == I2C4))

+/************** I2C Instances : wakeup capability from stop modes *************/

+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)

+

+/****************************** SMBUS Instances *******************************/

+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

+                                         ((INSTANCE) == I2C2) || \

+                                         ((INSTANCE) == I2C3) || \

+                                         ((INSTANCE) == I2C4))

+/******************************** I2S Instances *******************************/

+#define IS_I2S_ALL_INSTANCE(INSTANCE)   (((INSTANCE) == SPI1) || \

+                                         ((INSTANCE) == SPI2) || \

+                                         ((INSTANCE) == SPI3))

+

+

+/******************************* RNG Instances ********************************/

+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)

+

+/****************************** RTC Instances *********************************/

+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)

+

+/****************************** SDMMC Instances *********************************/

+#define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \

+                                           ((_INSTANCE_) == SDMMC2))

+

+/******************************** SMBUS Instances *****************************/

+#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)

+

+/******************************** SPI Instances *******************************/

+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \

+                                       ((INSTANCE) == SPI2) || \

+                                       ((INSTANCE) == SPI3) || \

+                                       ((INSTANCE) == SPI4) || \

+                                       ((INSTANCE) == SPI5) || \

+                                       ((INSTANCE) == SPI6))

+

+#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \

+                                           ((INSTANCE) == SPI2) || \

+                                           ((INSTANCE) == SPI3))

+

+/******************************** SWPMI Instances *****************************/

+#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)

+

+/****************** LPTIM Instances : All supported instances *****************/

+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \

+                                         ((INSTANCE) == LPTIM2) || \

+                                         ((INSTANCE) == LPTIM3) || \

+                                         ((INSTANCE) == LPTIM4) || \

+                                         ((INSTANCE) == LPTIM5))

+

+/****************** LPTIM Instances : supporting encoder interface **************/

+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \

+                                                           ((INSTANCE) == LPTIM2))

+

+/****************** TIM Instances : All supported instances *******************/

+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM6)   || \

+                                         ((INSTANCE) == TIM7)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM13)  || \

+                                         ((INSTANCE) == TIM14)  || \

+                                         ((INSTANCE) == TIM15)  || \

+                                         ((INSTANCE) == TIM16)  || \

+                                         ((INSTANCE) == TIM17))

+

+/************* TIM Instances : at least 1 capture/compare channel *************/

+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM13)  || \

+                                         ((INSTANCE) == TIM14)  || \

+                                         ((INSTANCE) == TIM15)  || \

+                                         ((INSTANCE) == TIM16)  || \

+                                         ((INSTANCE) == TIM17))

+

+/************ TIM Instances : at least 2 capture/compare channels *************/

+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM15))

+

+/************ TIM Instances : at least 3 capture/compare channels *************/

+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8))

+

+/************ TIM Instances : at least 4 capture/compare channels *************/

+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8))

+

+/************ TIM Instances : at least 5 capture/compare channels *************/

+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM8))

+/************ TIM Instances : at least 6 capture/compare channels *************/

+#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM8))

+

+/******************** TIM Instances : Advanced-control timers *****************/

+#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \

+                                                ((__INSTANCE__) == TIM8))

+

+/******************** TIM Instances : Advanced-control timers *****************/

+

+/******************* TIM Instances : Timer input XOR function *****************/

+#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : DMA requests generation (UDE) *************/

+#define IS_TIM_DMA_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM6)   || \

+                                           ((INSTANCE) == TIM7)   || \

+                                           ((INSTANCE) == TIM8)   || \

+                                           ((INSTANCE) == TIM15)  || \

+                                           ((INSTANCE) == TIM16)  || \

+                                           ((INSTANCE) == TIM17))

+

+/************ TIM Instances : DMA requests generation (CCxDE) *****************/

+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15)  || \

+                                            ((INSTANCE) == TIM16)  || \

+                                            ((INSTANCE) == TIM17))

+

+/************ TIM Instances : DMA requests generation (COMDE) *****************/

+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15))

+

+/******************** TIM Instances : DMA burst feature ***********************/

+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8))

+

+/*************** TIM Instances : external trigger reamp input available *******/

+#define IS_TIM_ETR_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : remapping capability **********************/

+#define IS_TIM_REMAP_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \

+                                          ((INSTANCE) == TIM2)  || \

+                                          ((INSTANCE) == TIM3)  || \

+                                          ((INSTANCE) == TIM5)  || \

+                                          ((INSTANCE) == TIM8)  || \

+                                          ((INSTANCE) == TIM16) || \

+                                          ((INSTANCE) == TIM17))

+

+/*************** TIM Instances : external trigger reamp input available *******/

+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                              ((INSTANCE) == TIM2)   || \

+                                              ((INSTANCE) == TIM3)   || \

+                                              ((INSTANCE) == TIM5)   || \

+                                              ((INSTANCE) == TIM8))

+

+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/

+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM6)   || \

+                                            ((INSTANCE) == TIM7)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15))

+

+/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/

+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM8)   || \

+                                           ((INSTANCE) == TIM12))

+

+/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/

+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM8))

+

+/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/

+#define IS_TIM_TISEL_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)   || \

+                                          ((INSTANCE) == TIM2)   || \

+                                          ((INSTANCE) == TIM3)   || \

+                                          ((INSTANCE) == TIM4)   || \

+                                          ((INSTANCE) == TIM5)   || \

+                                          ((INSTANCE) == TIM8)   || \

+                                          ((INSTANCE) == TIM15)  || \

+                                          ((INSTANCE) == TIM16)  || \

+                                          ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting commutation event *************/

+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \

+                                                     ((INSTANCE) == TIM8)    || \

+                                                     ((INSTANCE) == TIM15)   || \

+                                                     ((INSTANCE) == TIM16)   || \

+                                                     ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting encoder interface **************/

+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1)  || \

+                                                      ((__INSTANCE__) == TIM2)      || \

+                                                      ((__INSTANCE__) == TIM3)      || \

+                                                      ((__INSTANCE__) == TIM4)      || \

+                                                      ((__INSTANCE__) == TIM5)      || \

+                                                      ((__INSTANCE__) == TIM8))

+

+/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/

+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                                       ((INSTANCE) == TIM8))

+/******************* TIM Instances : output(s) available **********************/

+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \

+    ((((INSTANCE) == TIM1) &&                  \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4) ||          \

+      ((CHANNEL) == TIM_CHANNEL_5) ||          \

+      ((CHANNEL) == TIM_CHANNEL_6)))           \

+     ||                                        \

+     (((INSTANCE) == TIM2) &&                  \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM3) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1)||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM4) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM5) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM8) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4) ||          \

+      ((CHANNEL) == TIM_CHANNEL_5) ||          \

+      ((CHANNEL) == TIM_CHANNEL_6)))           \

+  ||                                           \

+     (((INSTANCE) == TIM12) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2)))           \

+  ||                                           \

+     (((INSTANCE) == TIM13) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM14) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM15) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+     ((CHANNEL) == TIM_CHANNEL_2)))            \

+  ||                                           \

+     (((INSTANCE) == TIM16) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM17) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1))))

+

+/****************** TIM Instances : supporting the break function *************/

+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\

+      (((INSTANCE) == TIM1)    || \

+      ((INSTANCE) == TIM8)     || \

+       ((INSTANCE) == TIM15)   || \

+       ((INSTANCE) == TIM16)   || \

+       ((INSTANCE) == TIM17))

+

+/************** TIM Instances : supporting Break source selection *************/

+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \

+                                               ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting complementary output(s) ********/

+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \

+   ((((INSTANCE) == TIM1) &&                    \

+     (((CHANNEL) == TIM_CHANNEL_1) ||           \

+      ((CHANNEL) == TIM_CHANNEL_2) ||           \

+      ((CHANNEL) == TIM_CHANNEL_3)))            \

+ ||                                             \

+      (((INSTANCE) == TIM8) &&                  \

+      (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||           \

+      ((CHANNEL) == TIM_CHANNEL_3)))            \

+    ||                                          \

+    (((INSTANCE) == TIM15) &&                   \

+      ((CHANNEL) == TIM_CHANNEL_1))             \

+    ||                                          \

+    (((INSTANCE) == TIM16) &&                   \

+     ((CHANNEL) == TIM_CHANNEL_1))              \

+    ||                                          \

+    (((INSTANCE) == TIM17) &&                   \

+     ((CHANNEL) == TIM_CHANNEL_1)))

+

+/****************** TIM Instances : supporting counting mode selection ********/

+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting repetition counter *************/

+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15)   || \

+   ((INSTANCE) == TIM16)   || \

+   ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting synchronization ****************/

+#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\

+    (((__INSTANCE__) == TIM1)    || \

+     ((__INSTANCE__) == TIM2)    || \

+     ((__INSTANCE__) == TIM3)    || \

+     ((__INSTANCE__) == TIM4)    || \

+     ((__INSTANCE__) == TIM5)    || \

+     ((__INSTANCE__) == TIM6)    || \

+     ((__INSTANCE__) == TIM8)    || \

+     ((__INSTANCE__) == TIM12)   || \

+     ((__INSTANCE__) == TIM15))

+

+/****************** TIM Instances : supporting clock division *****************/

+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15)   || \

+   ((INSTANCE) == TIM16)   || \

+   ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting external clock mode 1 for ETRF input */

+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting external clock mode 2 **********/

+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\

+ (((INSTANCE) == TIM1)     || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/

+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/

+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : supporting OCxREF clear *******************/

+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3))

+

+/****************** TIM Instances : TIM_32B_COUNTER ***************************/

+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM5))

+

+/****************** TIM Instances : TIM_BKIN2 ***************************/

+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting Hall sensor interface **********/

+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)  || \

+                                                             ((__INSTANCE__) == TIM2)  || \

+                                                             ((__INSTANCE__) == TIM3)  || \

+                                                             ((__INSTANCE__) == TIM4)  || \

+                                                             ((__INSTANCE__) == TIM5)  || \

+                                                             ((__INSTANCE__) == TIM15) || \

+                                                             ((__INSTANCE__) == TIM8))

+

+/****************************** HRTIM Instances *******************************/

+#define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))

+

+/******************** USART Instances : Synchronous mode **********************/

+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                     ((INSTANCE) == USART2) || \

+                                     ((INSTANCE) == USART3) || \

+                                     ((INSTANCE) == USART6))

+

+/******************** USART Instances : SPI slave mode ************************/

+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                              ((INSTANCE) == USART2) || \

+                                              ((INSTANCE) == USART3) || \

+                                              ((INSTANCE) == USART6))

+

+/******************** UART Instances : Asynchronous mode **********************/

+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                    ((INSTANCE) == USART2) || \

+                                    ((INSTANCE) == USART3) || \

+                                    ((INSTANCE) == UART4)  || \

+                                    ((INSTANCE) == UART5)  || \

+                                    ((INSTANCE) == USART6) || \

+                                    ((INSTANCE) == UART7)  || \

+                                    ((INSTANCE) == UART8))

+

+/******************** UART Instances : FIFO mode.******************************/

+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                         ((INSTANCE) == USART2) || \

+                                         ((INSTANCE) == USART3) || \

+                                         ((INSTANCE) == UART4)  || \

+                                         ((INSTANCE) == UART5)  || \

+                                         ((INSTANCE) == USART6) || \

+                                         ((INSTANCE) == UART7)  || \

+                                         ((INSTANCE) == UART8))

+

+/****************** UART Instances : Auto Baud Rate detection *****************/

+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                            ((INSTANCE) == USART2) || \

+                                                            ((INSTANCE) == USART3) || \

+                                                            ((INSTANCE) == UART4)  || \

+                                                            ((INSTANCE) == UART5)  || \

+                                                            ((INSTANCE) == USART6) || \

+                                                            ((INSTANCE) == UART7)  || \

+                                                            ((INSTANCE) == UART8))

+

+/*********************** UART Instances : Driver Enable ***********************/

+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                  ((INSTANCE) == USART2) || \

+                                                  ((INSTANCE) == USART3) || \

+                                                  ((INSTANCE) == UART4)  || \

+                                                  ((INSTANCE) == UART5)  || \

+                                                  ((INSTANCE) == USART6) || \

+                                                  ((INSTANCE) == UART7)  || \

+                                                  ((INSTANCE) == UART8)  || \

+                                                  ((INSTANCE) == LPUART1))

+

+/********************* UART Instances : Half-Duplex mode **********************/

+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                               ((INSTANCE) == USART2) || \

+                                               ((INSTANCE) == USART3) || \

+                                               ((INSTANCE) == UART4)  || \

+                                               ((INSTANCE) == UART5)  || \

+                                               ((INSTANCE) == USART6) || \

+                                               ((INSTANCE) == UART7)  || \

+                                               ((INSTANCE) == UART8)  || \

+                                               ((INSTANCE) == LPUART1))

+

+/******************* UART Instances : Hardware Flow control *******************/

+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                           ((INSTANCE) == USART2) || \

+                                           ((INSTANCE) == USART3) || \

+                                           ((INSTANCE) == UART4)  || \

+                                           ((INSTANCE) == UART5)  || \

+                                           ((INSTANCE) == USART6) || \

+                                           ((INSTANCE) == UART7)  || \

+                                           ((INSTANCE) == UART8)  || \

+                                           ((INSTANCE) == LPUART1))

+

+/************************* UART Instances : LIN mode **************************/

+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                        ((INSTANCE) == USART2) || \

+                                        ((INSTANCE) == USART3) || \

+                                        ((INSTANCE) == UART4)  || \

+                                        ((INSTANCE) == UART5)  || \

+                                        ((INSTANCE) == USART6) || \

+                                        ((INSTANCE) == UART7)  || \

+                                        ((INSTANCE) == UART8))

+

+/****************** UART Instances : Wake-up from Stop mode *******************/

+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                    ((INSTANCE) == USART2) || \

+                                                    ((INSTANCE) == USART3) || \

+                                                    ((INSTANCE) == UART4)  || \

+                                                    ((INSTANCE) == UART5)  || \

+                                                    ((INSTANCE) == USART6) || \

+                                                    ((INSTANCE) == UART7)  || \

+                                                    ((INSTANCE) == UART8)  || \

+                                                    ((INSTANCE) == LPUART1))

+

+/************************* UART Instances : IRDA mode *************************/

+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                    ((INSTANCE) == USART2) || \

+                                    ((INSTANCE) == USART3) || \

+                                    ((INSTANCE) == UART4)  || \

+                                    ((INSTANCE) == UART5)  || \

+                                    ((INSTANCE) == USART6) || \

+                                    ((INSTANCE) == UART7)  || \

+                                    ((INSTANCE) == UART8))

+

+/********************* USART Instances : Smard card mode **********************/

+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                         ((INSTANCE) == USART2) || \

+                                         ((INSTANCE) == USART3) || \

+                                         ((INSTANCE) == USART6))

+

+/****************************** LPUART Instance *******************************/

+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)

+

+/****************************** IWDG Instances ********************************/

+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG1)

+/****************************** USB Instances ********************************/

+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)

+

+/****************************** WWDG Instances ********************************/

+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG1)

+/****************************** MDIOS Instances ********************************/

+#define IS_MDIOS_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == MDIOS)

+

+/****************************** CEC Instances *********************************/

+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)

+

+/****************************** SAI Instances ********************************/

+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \

+                    ((INSTANCE) == SAI1_Block_B) || \

+                     ((INSTANCE) == SAI2_Block_A) || \

+                     ((INSTANCE) == SAI2_Block_B) || \

+                     ((INSTANCE) == SAI3_Block_A) || \

+                     ((INSTANCE) == SAI3_Block_B) || \

+                     ((INSTANCE) == SAI4_Block_A) || \

+                     ((INSTANCE) == SAI4_Block_B))

+

+/****************************** SPDIFRX Instances ********************************/

+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)

+

+/****************************** OPAMP Instances *******************************/

+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \

+                                         ((INSTANCE) == OPAMP2))

+

+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)

+

+/*********************** USB OTG PCD Instances ********************************/

+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \

+                                        ((INSTANCE) == USB_OTG_HS))

+

+/*********************** USB OTG HCD Instances ********************************/

+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \

+                                       ((INSTANCE) == USB_OTG_HS))

+

+/******************************************************************************/

+/*  For a painless codes migration between the STM32H7xx device product       */

+/*  lines, or with STM32F7xx devices the aliases defined below are put        */

+/*   in place to overcome the differences in the interrupt handlers and IRQn  */

+/*   definitions. No need to update developed interrupt code when moving      */

+/*  across product lines within the same STM32H7 Family                       */

+/******************************************************************************/

+

+/* Aliases for __IRQn */

+#define  HASH_RNG_IRQn                  RNG_IRQn

+#define  TIM1_BRK_TIM9_IRQn             TIM1_BRK_IRQn

+#define  TIM1_UP_TIM10_IRQn             TIM1_UP_IRQn

+#define  TIM1_TRG_COM_TIM11_IRQn        TIM1_TRG_COM_IRQn

+#define  PVD_IRQn                       PVD_AVD_IRQn

+

+

+

+/* Aliases for __IRQHandler */

+#define  HASH_RNG_IRQHandler           RNG_IRQHandler

+#define TIM1_BRK_TIM9_IRQHandler       TIM1_BRK_IRQHandler

+#define TIM1_UP_TIM9_IRQHandler        TIM1_UP_IRQHandler

+#define TIM1_TRG_COM_TIM11_IRQHandler  TIM1_TRG_COM_IRQHandler

+#define PVD_IRQHandler                 PVD_AVD_IRQHandler

+

+/* Aliases for COMP __IRQHandler */

+#define COMP_IRQHandler                COMP1_IRQHandler

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif /* __cplusplus */

+

+#endif /* STM32H742xx_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h743xx.h b/bsps/arm/stm32h7/include/stm32h743xx.h
new file mode 100644
index 0000000000..cdcde7d97c
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h743xx.h
@@ -0,0 +1,26288 @@
+/**

+  ******************************************************************************

+  * @file    stm32h743xx.h

+  * @author  MCD Application Team

+  * @brief   CMSIS STM32H743xx Device Peripheral Access Layer Header File.

+  *

+  *          This file contains:

+  *           - Data structures and the address mapping for all peripherals

+  *           - Peripheral's registers declarations and bits definition

+  *           - Macros to access peripheral's registers hardware

+  *

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/** @addtogroup CMSIS_Device

+  * @{

+  */

+

+/** @addtogroup stm32h743xx

+  * @{

+  */

+

+#ifndef STM32H743xx_H

+#define STM32H743xx_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif /* __cplusplus */

+

+/** @addtogroup Peripheral_interrupt_number_definition

+  * @{

+  */

+

+/**

+ * @brief STM32H7XX Interrupt Number Definition, according to the selected device

+ *        in @ref Library_configuration_section

+ */

+typedef enum

+{

+/******  Cortex-M Processor Exceptions Numbers *****************************************************************/

+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */

+  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */

+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */

+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */

+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */

+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M SV Call Interrupt                                     */

+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M Debug Monitor Interrupt                               */

+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M Pend SV Interrupt                                     */

+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M System Tick Interrupt                                 */

+/******  STM32 specific Interrupt Numbers **********************************************************************/

+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)                   */

+  PVD_AVD_IRQn                = 1,      /*!< PVD/AVD through EXTI Line detection Interrupt                     */

+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */

+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */

+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */

+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */

+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */

+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */

+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */

+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */

+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */

+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */

+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */

+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */

+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */

+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */

+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */

+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */

+  ADC_IRQn                    = 18,     /*!< ADC1 and  ADC2 global Interrupts                                  */

+  FDCAN1_IT0_IRQn             = 19,     /*!< FDCAN1 Interrupt line 0                                           */

+  FDCAN2_IT0_IRQn             = 20,     /*!< FDCAN2 Interrupt line 0                                           */

+  FDCAN1_IT1_IRQn             = 21,     /*!< FDCAN1 Interrupt line 1                                           */

+  FDCAN2_IT1_IRQn             = 22,     /*!< FDCAN2 Interrupt line 1                                           */

+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */

+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                              */

+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                             */

+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt                            */

+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */

+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */

+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */

+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */

+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */

+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */

+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */

+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */

+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */

+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */

+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */

+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */

+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */

+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */

+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */

+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */

+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */

+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */

+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */

+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */

+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */

+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */

+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */

+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */

+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */

+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */

+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */

+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */

+  DMA2_Stream0_IRQn           = 56,     /*!<   DMA2 Stream 0 global Interrupt                                  */

+  DMA2_Stream1_IRQn           = 57,     /*!<   DMA2 Stream 1 global Interrupt                                  */

+  DMA2_Stream2_IRQn           = 58,     /*!<   DMA2 Stream 2 global Interrupt                                  */

+  DMA2_Stream3_IRQn           = 59,     /*!<   DMA2 Stream 3 global Interrupt                                  */

+  DMA2_Stream4_IRQn           = 60,     /*!<   DMA2 Stream 4 global Interrupt                                  */

+  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */

+  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */

+  FDCAN_CAL_IRQn              = 63,     /*!< FDCAN Calibration unit Interrupt                                  */

+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */

+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */

+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */

+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */

+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */

+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */

+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */

+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */

+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */

+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */

+  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */

+  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */

+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */

+  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */

+  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */

+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */

+  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */

+  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */

+  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */

+  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */

+  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */

+  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */

+  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */

+  QUADSPI_IRQn                = 92,     /*!< Quad SPI global interrupt                                         */

+  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */

+  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */

+  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */

+  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */

+  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */

+  OTG_FS_EP1_OUT_IRQn         = 98,     /*!< USB OTG HS2 global interrupt                                      */

+  OTG_FS_EP1_IN_IRQn          = 99,     /*!< USB OTG HS2 End Point 1 Out global interrupt                      */

+  OTG_FS_WKUP_IRQn            = 100,    /*!< USB OTG HS2 End Point 1 In global interrupt                       */

+  OTG_FS_IRQn                 = 101,    /*!< USB OTG HS2 Wakeup through EXTI interrupt                         */

+  DMAMUX1_OVR_IRQn            = 102,    /*!<DMAMUX1 Overrun interrupt                                          */

+  HRTIM1_Master_IRQn          = 103,    /*!< HRTIM Master Timer global Interrupts                              */

+  HRTIM1_TIMA_IRQn            = 104,    /*!< HRTIM Timer A global Interrupt                                    */

+  HRTIM1_TIMB_IRQn            = 105,    /*!< HRTIM Timer B global Interrupt                                    */

+  HRTIM1_TIMC_IRQn            = 106,    /*!< HRTIM Timer C global Interrupt                                    */

+  HRTIM1_TIMD_IRQn            = 107,    /*!< HRTIM Timer D global Interrupt                                    */

+  HRTIM1_TIME_IRQn            = 108,    /*!< HRTIM Timer E global Interrupt                                    */

+  HRTIM1_FLT_IRQn             = 109,    /*!< HRTIM Fault global Interrupt                                      */

+  DFSDM1_FLT0_IRQn            = 110,    /*!<DFSDM Filter1 Interrupt                                            */

+  DFSDM1_FLT1_IRQn            = 111,    /*!<DFSDM Filter2 Interrupt                                            */

+  DFSDM1_FLT2_IRQn            = 112,    /*!<DFSDM Filter3 Interrupt                                            */

+  DFSDM1_FLT3_IRQn            = 113,    /*!<DFSDM Filter4 Interrupt                                            */

+  SAI3_IRQn                   = 114,    /*!< SAI3 global Interrupt                                             */

+  SWPMI1_IRQn                 = 115,    /*!< Serial Wire Interface 1 global interrupt                          */

+  TIM15_IRQn                  = 116,    /*!< TIM15 global Interrupt                                            */

+  TIM16_IRQn                  = 117,    /*!< TIM16 global Interrupt                                            */

+  TIM17_IRQn                  = 118,    /*!< TIM17 global Interrupt                                            */

+  MDIOS_WKUP_IRQn             = 119,    /*!< MDIOS Wakeup  Interrupt                                           */

+  MDIOS_IRQn                  = 120,    /*!< MDIOS global Interrupt                                            */

+  JPEG_IRQn                   = 121,    /*!< JPEG global Interrupt                                             */

+  MDMA_IRQn                   = 122,    /*!< MDMA global Interrupt                                             */

+  SDMMC2_IRQn                 = 124,    /*!< SDMMC2 global Interrupt                                           */

+  HSEM1_IRQn                  = 125,    /*!< HSEM1 global Interrupt                                            */

+  ADC3_IRQn                   = 127,    /*!< ADC3 global Interrupt                                             */

+  DMAMUX2_OVR_IRQn            = 128,    /*!<DMAMUX2 Overrun interrupt                                          */

+  BDMA_Channel0_IRQn          = 129,    /*!< BDMA Channel 0 global Interrupt                                   */

+  BDMA_Channel1_IRQn          = 130,    /*!< BDMA Channel 1 global Interrupt                                   */

+  BDMA_Channel2_IRQn          = 131,    /*!< BDMA Channel 2 global Interrupt                                   */

+  BDMA_Channel3_IRQn          = 132,    /*!< BDMA Channel 3 global Interrupt                                   */

+  BDMA_Channel4_IRQn          = 133,    /*!< BDMA Channel 4 global Interrupt                                   */

+  BDMA_Channel5_IRQn          = 134,    /*!< BDMA Channel 5 global Interrupt                                   */

+  BDMA_Channel6_IRQn          = 135,    /*!< BDMA Channel 6 global Interrupt                                   */

+  BDMA_Channel7_IRQn          = 136,    /*!< BDMA Channel 7 global Interrupt                                   */

+  COMP_IRQn                   = 137 ,   /*!< COMP global Interrupt                                             */

+  LPTIM2_IRQn                 = 138,    /*!< LP TIM2 global interrupt                                          */

+  LPTIM3_IRQn                 = 139,    /*!< LP TIM3 global interrupt                                          */

+  LPTIM4_IRQn                 = 140,    /*!< LP TIM4 global interrupt                                          */

+  LPTIM5_IRQn                 = 141,    /*!< LP TIM5 global interrupt                                          */

+  LPUART1_IRQn                = 142,    /*!< LP UART1 interrupt                                                */

+  CRS_IRQn                    = 144,    /*!< Clock Recovery Global Interrupt                                   */

+  ECC_IRQn                    = 145,    /*!< ECC diagnostic Global Interrupt                                   */

+  SAI4_IRQn                   = 146,    /*!< SAI4 global interrupt                                             */

+  WAKEUP_PIN_IRQn             = 149,    /*!< Interrupt for all 6 wake-up pins                                  */

+} IRQn_Type;

+

+/**

+  * @}

+  */

+

+/** @addtogroup Configuration_section_for_CMSIS

+  * @{

+  */

+

+

+

+

+/**

+  * @brief Configuration of the Cortex-M7 Processor and Core Peripherals

+   */

+#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */

+#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */

+#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */

+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */

+#define __FPU_PRESENT             1       /*!< FPU present                                   */

+#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */

+#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */

+#include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */

+

+/**

+  * @}

+  */

+

+

+

+

+#include "system_stm32h7xx.h"

+#include <stdint.h>

+

+/** @addtogroup Peripheral_registers_structures

+  * @{

+  */

+

+/**

+  * @brief Analog to Digital Converter

+  */

+

+typedef struct

+{

+  __IO uint32_t ISR;              /*!< ADC Interrupt and Status Register,                          Address offset: 0x00 */

+  __IO uint32_t IER;              /*!< ADC Interrupt Enable Register,                              Address offset: 0x04 */

+  __IO uint32_t CR;               /*!< ADC control register,                                       Address offset: 0x08 */

+  __IO uint32_t CFGR;             /*!< ADC Configuration register,                                 Address offset: 0x0C */

+  __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                               Address offset: 0x10 */

+  __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                                 Address offset: 0x14 */

+  __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                                 Address offset: 0x18 */

+  __IO uint32_t PCSEL;            /*!< ADC pre-channel selection,                                  Address offset: 0x1C */

+  __IO uint32_t LTR1;             /*!< ADC watchdog Lower threshold register 1,                    Address offset: 0x20 */

+  __IO uint32_t HTR1;             /*!< ADC watchdog higher threshold register 1,                   Address offset: 0x24 */

+  uint32_t      RESERVED1;        /*!< Reserved, 0x028                                                                  */

+  uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                                  */

+  __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                            Address offset: 0x30 */

+  __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                            Address offset: 0x34 */

+  __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                            Address offset: 0x38 */

+  __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                            Address offset: 0x3C */

+  __IO uint32_t DR;               /*!< ADC regular data register,                                  Address offset: 0x40 */

+  uint32_t      RESERVED3;        /*!< Reserved, 0x044                                                                  */

+  uint32_t      RESERVED4;        /*!< Reserved, 0x048                                                                  */

+  __IO uint32_t JSQR;             /*!< ADC injected sequence register,                             Address offset: 0x4C */

+  uint32_t      RESERVED5[4];     /*!< Reserved, 0x050 - 0x05C                                                          */

+  __IO uint32_t OFR1;             /*!< ADC offset register 1,                                      Address offset: 0x60 */

+  __IO uint32_t OFR2;             /*!< ADC offset register 2,                                      Address offset: 0x64 */

+  __IO uint32_t OFR3;             /*!< ADC offset register 3,                                      Address offset: 0x68 */

+  __IO uint32_t OFR4;             /*!< ADC offset register 4,                                      Address offset: 0x6C */

+  uint32_t      RESERVED6[4];     /*!< Reserved, 0x070 - 0x07C                                                          */

+  __IO uint32_t JDR1;             /*!< ADC injected data register 1,                               Address offset: 0x80 */

+  __IO uint32_t JDR2;             /*!< ADC injected data register 2,                               Address offset: 0x84 */

+  __IO uint32_t JDR3;             /*!< ADC injected data register 3,                               Address offset: 0x88 */

+  __IO uint32_t JDR4;             /*!< ADC injected data register 4,                               Address offset: 0x8C */

+  uint32_t      RESERVED7[4];     /*!< Reserved, 0x090 - 0x09C                                                          */

+  __IO uint32_t AWD2CR;           /*!< ADC  Analog Watchdog 2 Configuration Register,              Address offset: 0xA0 */

+  __IO uint32_t AWD3CR;           /*!< ADC  Analog Watchdog 3 Configuration Register,              Address offset: 0xA4 */

+  uint32_t      RESERVED8;        /*!< Reserved, 0x0A8                                                                  */

+  uint32_t      RESERVED9;        /*!< Reserved, 0x0AC                                                                  */

+  __IO uint32_t LTR2;             /*!< ADC watchdog Lower threshold register 2,                    Address offset: 0xB0 */

+  __IO uint32_t HTR2;             /*!< ADC watchdog Higher threshold register 2,                   Address offset: 0xB4 */

+  __IO uint32_t LTR3;             /*!< ADC watchdog Lower threshold register 3,                    Address offset: 0xB8 */

+  __IO uint32_t HTR3;             /*!< ADC watchdog Higher threshold register 3,                   Address offset: 0xBC */

+  __IO uint32_t DIFSEL;           /*!< ADC  Differential Mode Selection Register,                  Address offset: 0xC0 */

+  __IO uint32_t CALFACT;          /*!< ADC  Calibration Factors,                                   Address offset: 0xC4 */

+  __IO uint32_t CALFACT2;         /*!< ADC  Linearity Calibration Factors,                         Address offset: 0xC8 */

+} ADC_TypeDef;

+

+

+typedef struct

+{

+__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */

+uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */

+__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */

+__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */

+__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */

+

+} ADC_Common_TypeDef;

+

+

+/**

+  * @brief VREFBUF

+  */

+

+typedef struct

+{

+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */

+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */

+} VREFBUF_TypeDef;

+

+

+/**

+  * @brief FD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */

+  __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */

+  __IO uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */

+  __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */

+  __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */

+  __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */

+  __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */

+  __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */

+  __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */

+  __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */

+  __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */

+  __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */

+  __IO uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */

+  __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */

+  __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */

+  __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */

+  __IO uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */

+  __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */

+  __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */

+  __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */

+  __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */

+  __IO uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */

+  __IO uint32_t GFC;          /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */

+  __IO uint32_t SIDFC;        /*!< FDCAN Standard ID Filter Configuration register,                 Address offset: 0x084 */

+  __IO uint32_t XIDFC;        /*!< FDCAN Extended ID Filter Configuration register,                 Address offset: 0x088 */

+  __IO uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */

+  __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x090 */

+  __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x094 */

+  __IO uint32_t NDAT1;        /*!< FDCAN New Data 1 register,                                       Address offset: 0x098 */

+  __IO uint32_t NDAT2;        /*!< FDCAN New Data 2 register,                                       Address offset: 0x09C */

+  __IO uint32_t RXF0C;        /*!< FDCAN Rx FIFO 0 Configuration register,                          Address offset: 0x0A0 */

+  __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x0A4 */

+  __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x0A8 */

+  __IO uint32_t RXBC;         /*!< FDCAN Rx Buffer Configuration register,                          Address offset: 0x0AC */

+  __IO uint32_t RXF1C;        /*!< FDCAN Rx FIFO 1 Configuration register,                          Address offset: 0x0B0 */

+  __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x0B4 */

+  __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x0B8 */

+  __IO uint32_t RXESC;        /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register,        Address offset: 0x0BC */

+  __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */

+  __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */

+  __IO uint32_t TXESC;        /*!< FDCAN Tx Buffer Element Size Configuration register,             Address offset: 0x0C8 */

+  __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0CC */

+  __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0D0 */

+  __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D4 */

+  __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D8 */

+  __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0DC */

+  __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0E0 */

+  __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */

+  __IO uint32_t RESERVED6[2]; /*!< Reserved,                                                                0x0E8 - 0x0EC */

+  __IO uint32_t TXEFC;        /*!< FDCAN Tx Event FIFO Configuration register,                      Address offset: 0x0F0 */

+  __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0F4 */

+  __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0F8 */

+  __IO uint32_t RESERVED7;    /*!< Reserved,                                                                        0x0FC */

+} FDCAN_GlobalTypeDef;

+

+/**

+  * @brief TTFD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t TTTMC;          /*!< TT Trigger Memory Configuration register,    Address offset: 0x100 */

+  __IO uint32_t TTRMC;          /*!< TT Reference Message Configuration register, Address offset: 0x104 */

+  __IO uint32_t TTOCF;          /*!< TT Operation Configuration register,         Address offset: 0x108 */

+  __IO uint32_t TTMLM;          /*!< TT Matrix Limits register,                   Address offset: 0x10C */

+  __IO uint32_t TURCF;          /*!< TUR Configuration register,                  Address offset: 0x110 */

+  __IO uint32_t TTOCN;          /*!< TT Operation Control register,               Address offset: 0x114 */

+  __IO uint32_t TTGTP;          /*!< TT Global Time Preset register,              Address offset: 0x118 */

+  __IO uint32_t TTTMK;          /*!< TT Time Mark register,                       Address offset: 0x11C */

+  __IO uint32_t TTIR;           /*!< TT Interrupt register,                       Address offset: 0x120 */

+  __IO uint32_t TTIE;           /*!< TT Interrupt Enable register,                Address offset: 0x124 */

+  __IO uint32_t TTILS;          /*!< TT Interrupt Line Select register,           Address offset: 0x128 */

+  __IO uint32_t TTOST;          /*!< TT Operation Status register,                Address offset: 0x12C */

+  __IO uint32_t TURNA;          /*!< TT TUR Numerator Actual register,            Address offset: 0x130 */

+  __IO uint32_t TTLGT;          /*!< TT Local and Global Time register,           Address offset: 0x134 */

+  __IO uint32_t TTCTC;          /*!< TT Cycle Time and Count register,            Address offset: 0x138 */

+  __IO uint32_t TTCPT;          /*!< TT Capture Time register,                    Address offset: 0x13C */

+  __IO uint32_t TTCSM;          /*!< TT Cycle Sync Mark register,                 Address offset: 0x140 */

+  __IO uint32_t RESERVED1[111]; /*!< Reserved,                                            0x144 - 0x2FC */

+  __IO uint32_t TTTS;           /*!< TT Trigger Select register,                  Address offset: 0x300 */

+} TTCAN_TypeDef;

+

+/**

+  * @brief FD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t CREL;  /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */

+  __IO uint32_t CCFG;  /*!< Calibration Configuration register,           Address offset: 0x04 */

+  __IO uint32_t CSTAT; /*!< Calibration Status register,                  Address offset: 0x08 */

+  __IO uint32_t CWD;   /*!< Calibration Watchdog register,                Address offset: 0x0C */

+  __IO uint32_t IR;    /*!< CCU Interrupt register,                       Address offset: 0x10 */

+  __IO uint32_t IE;    /*!< CCU Interrupt Enable register,                Address offset: 0x14 */

+} FDCAN_ClockCalibrationUnit_TypeDef;

+

+

+/**

+  * @brief Consumer Electronics Control

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;           /*!< CEC control register,              Address offset:0x00 */

+  __IO uint32_t CFGR;         /*!< CEC configuration register,        Address offset:0x04 */

+  __IO uint32_t TXDR;         /*!< CEC Tx data register ,             Address offset:0x08 */

+  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,              Address offset:0x0C */

+  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register, Address offset:0x10 */

+  __IO uint32_t IER;          /*!< CEC interrupt enable register,     Address offset:0x14 */

+}CEC_TypeDef;

+

+/**

+  * @brief CRC calculation unit

+  */

+

+typedef struct

+{

+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */

+  __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */

+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */

+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */

+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */

+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */

+} CRC_TypeDef;

+

+

+/**

+  * @brief Clock Recovery System

+  */

+typedef struct

+{

+__IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */

+__IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */

+__IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */

+__IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */

+} CRS_TypeDef;

+

+

+/**

+  * @brief Digital to Analog Converter

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */

+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */

+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */

+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */

+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */

+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */

+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */

+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */

+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */

+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */

+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */

+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */

+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */

+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */

+  __IO uint32_t CCR;      /*!< DAC calibration control register,                        Address offset: 0x38 */

+  __IO uint32_t MCR;      /*!< DAC mode control register,                               Address offset: 0x3C */

+  __IO uint32_t SHSR1;    /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */

+  __IO uint32_t SHSR2;    /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */

+  __IO uint32_t SHHR;     /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */

+  __IO uint32_t SHRR;     /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */

+} DAC_TypeDef;

+

+/**

+  * @brief DFSDM module registers

+  */

+typedef struct

+{

+  __IO uint32_t FLTCR1;          /*!< DFSDM control register1,                          Address offset: 0x100 */

+  __IO uint32_t FLTCR2;          /*!< DFSDM control register2,                          Address offset: 0x104 */

+  __IO uint32_t FLTISR;          /*!< DFSDM interrupt and status register,              Address offset: 0x108 */

+  __IO uint32_t FLTICR;          /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */

+  __IO uint32_t FLTJCHGR;        /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */

+  __IO uint32_t FLTFCR;          /*!< DFSDM filter control register,                    Address offset: 0x114 */

+  __IO uint32_t FLTJDATAR;       /*!< DFSDM data register for injected group,           Address offset: 0x118 */

+  __IO uint32_t FLTRDATAR;       /*!< DFSDM data register for regular group,            Address offset: 0x11C */

+  __IO uint32_t FLTAWHTR;        /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */

+  __IO uint32_t FLTAWLTR;        /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */

+  __IO uint32_t FLTAWSR;         /*!< DFSDM analog watchdog status register             Address offset: 0x128 */

+  __IO uint32_t FLTAWCFR;        /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */

+  __IO uint32_t FLTEXMAX;        /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */

+  __IO uint32_t FLTEXMIN;        /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */

+  __IO uint32_t FLTCNVTIMR;      /*!< DFSDM conversion timer,                           Address offset: 0x138 */

+} DFSDM_Filter_TypeDef;

+

+/**

+  * @brief DFSDM channel configuration registers

+  */

+typedef struct

+{

+  __IO uint32_t CHCFGR1;      /*!< DFSDM channel configuration register1,            Address offset: 0x00 */

+  __IO uint32_t CHCFGR2;      /*!< DFSDM channel configuration register2,            Address offset: 0x04 */

+  __IO uint32_t CHAWSCDR;     /*!< DFSDM channel analog watchdog and

+                                   short circuit detector register,                  Address offset: 0x08 */

+  __IO uint32_t CHWDATAR;     /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */

+  __IO uint32_t CHDATINR;     /*!< DFSDM channel data input register,                Address offset: 0x10 */

+} DFSDM_Channel_TypeDef;

+

+/**

+  * @brief Debug MCU

+  */

+typedef struct

+{

+  __IO uint32_t IDCODE;        /*!< MCU device ID code,                     Address offset: 0x00 */

+  __IO uint32_t CR;            /*!< Debug MCU configuration register,       Address offset: 0x04 */

+  uint32_t RESERVED4[11];      /*!< Reserved,                             Address offset: 0x08 */

+  __IO uint32_t APB3FZ1;     /*!< Debug MCU APB3FZ1 freeze register,    Address offset: 0x34 */

+  uint32_t RESERVED5;          /*!< Reserved,                             Address offset: 0x38 */

+  __IO uint32_t APB1LFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x3C */

+  uint32_t RESERVED6;          /*!< Reserved,                             Address offset: 0x40 */

+  __IO uint32_t APB1HFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x44 */

+  uint32_t RESERVED7;          /*!< Reserved,                             Address offset: 0x48 */

+  __IO uint32_t APB2FZ1;     /*!< Debug MCU APB2FZ1 freeze register,    Address offset: 0x4C */

+  uint32_t RESERVED8;          /*!< Reserved,                             Address offset: 0x50 */

+  __IO uint32_t APB4FZ1;     /*!< Debug MCU APB4FZ1 freeze register,    Address offset: 0x54 */

+}DBGMCU_TypeDef;

+/**

+  * @brief DCMI

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */

+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */

+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */

+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */

+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */

+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */

+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */

+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */

+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */

+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */

+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */

+} DCMI_TypeDef;

+

+/**

+  * @brief DMA Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */

+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */

+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */

+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */

+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */

+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */

+} DMA_Stream_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */

+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */

+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */

+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */

+} DMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CCR;          /*!< DMA channel x configuration register          */

+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register         */

+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register     */

+  __IO uint32_t CM0AR;        /*!< DMA channel x memory 0 address register       */

+  __IO uint32_t CM1AR;        /*!< DMA channel x memory 1 address register       */

+} BDMA_Channel_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */

+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */

+} BDMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CCR;        /*!< DMA Multiplexer Channel x Control Register   */

+}DMAMUX_Channel_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CSR;      /*!< DMA Channel Status Register     */

+  __IO uint32_t  CFR;      /*!< DMA Channel Clear Flag Register */

+}DMAMUX_ChannelStatus_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  RGCR;        /*!< DMA Request Generator x Control Register   */

+}DMAMUX_RequestGen_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  RGSR;        /*!< DMA Request Generator Status Register       */

+  __IO uint32_t  RGCFR;       /*!< DMA Request Generator Clear Flag Register   */

+}DMAMUX_RequestGenStatus_TypeDef;

+

+/**

+  * @brief MDMA Controller

+  */

+typedef struct

+{

+  __IO uint32_t  GISR0;   /*!< MDMA Global Interrupt/Status Register 0,          Address offset: 0x00 */

+}MDMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CISR;      /*!< MDMA channel x interrupt/status register,             Address offset: 0x40 */

+  __IO uint32_t  CIFCR;     /*!< MDMA channel x interrupt flag clear register,         Address offset: 0x44 */

+  __IO uint32_t  CESR;      /*!< MDMA Channel x error status register,                 Address offset: 0x48 */

+  __IO uint32_t  CCR;       /*!< MDMA channel x control register,                      Address offset: 0x4C */

+  __IO uint32_t  CTCR;      /*!< MDMA channel x Transfer Configuration register,       Address offset: 0x50 */

+  __IO uint32_t  CBNDTR;    /*!< MDMA Channel x block number of data register,         Address offset: 0x54 */

+  __IO uint32_t  CSAR;      /*!< MDMA channel x source address register,               Address offset: 0x58 */

+  __IO uint32_t  CDAR;      /*!< MDMA channel x destination address register,          Address offset: 0x5C */

+  __IO uint32_t  CBRUR;     /*!< MDMA channel x Block Repeat address Update register,  Address offset: 0x60 */

+  __IO uint32_t  CLAR;      /*!< MDMA channel x Link Address register,                 Address offset: 0x64 */

+  __IO uint32_t  CTBR;      /*!< MDMA channel x Trigger and Bus selection Register,    Address offset: 0x68 */

+  uint32_t       RESERVED0; /*!< Reserved, 0x68                                                             */

+  __IO uint32_t  CMAR;      /*!< MDMA channel x Mask address register,                 Address offset: 0x70 */

+  __IO uint32_t  CMDR;      /*!< MDMA channel x Mask Data register,                    Address offset: 0x74 */

+}MDMA_Channel_TypeDef;

+

+/**

+  * @brief DMA2D Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */

+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */

+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */

+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */

+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */

+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */

+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */

+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */

+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */

+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */

+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */

+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */

+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */

+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */

+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */

+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */

+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */

+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */

+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */

+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */

+  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */

+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */

+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */

+} DMA2D_TypeDef;

+

+

+/**

+  * @brief Ethernet MAC

+  */

+typedef struct

+{

+  __IO uint32_t MACCR;

+  __IO uint32_t MACECR;

+  __IO uint32_t MACPFR;

+  __IO uint32_t MACWTR;

+  __IO uint32_t MACHT0R;

+  __IO uint32_t MACHT1R;

+  uint32_t      RESERVED1[14];

+  __IO uint32_t MACVTR;

+  uint32_t      RESERVED2;

+  __IO uint32_t MACVHTR;

+  uint32_t      RESERVED3;

+  __IO uint32_t MACVIR;

+  __IO uint32_t MACIVIR;

+  uint32_t      RESERVED4[2];

+  __IO uint32_t MACTFCR;

+  uint32_t      RESERVED5[7];

+  __IO uint32_t MACRFCR;

+  uint32_t      RESERVED6[7];

+  __IO uint32_t MACISR;

+  __IO uint32_t MACIER;

+  __IO uint32_t MACRXTXSR;

+  uint32_t      RESERVED7;

+  __IO uint32_t MACPCSR;

+  __IO uint32_t MACRWKPFR;

+  uint32_t      RESERVED8[2];

+  __IO uint32_t MACLCSR;

+  __IO uint32_t MACLTCR;

+  __IO uint32_t MACLETR;

+  __IO uint32_t MAC1USTCR;

+  uint32_t      RESERVED9[12];

+  __IO uint32_t MACVR;

+  __IO uint32_t MACDR;

+  uint32_t      RESERVED10;

+  __IO uint32_t MACHWF0R;

+  __IO uint32_t MACHWF1R;

+  __IO uint32_t MACHWF2R;

+  uint32_t      RESERVED11[54];

+  __IO uint32_t MACMDIOAR;

+  __IO uint32_t MACMDIODR;

+  uint32_t      RESERVED12[2];

+  __IO uint32_t MACARPAR;

+  uint32_t      RESERVED13[59];

+  __IO uint32_t MACA0HR;

+  __IO uint32_t MACA0LR;

+  __IO uint32_t MACA1HR;

+  __IO uint32_t MACA1LR;

+  __IO uint32_t MACA2HR;

+  __IO uint32_t MACA2LR;

+  __IO uint32_t MACA3HR;

+  __IO uint32_t MACA3LR;

+  uint32_t      RESERVED14[248];

+  __IO uint32_t MMCCR;

+  __IO uint32_t MMCRIR;

+  __IO uint32_t MMCTIR;

+  __IO uint32_t MMCRIMR;

+  __IO uint32_t MMCTIMR;

+  uint32_t      RESERVED15[14];

+  __IO uint32_t MMCTSCGPR;

+  __IO uint32_t MMCTMCGPR;

+  uint32_t      RESERVED16[5];

+  __IO uint32_t MMCTPCGR;

+  uint32_t      RESERVED17[10];

+  __IO uint32_t MMCRCRCEPR;

+  __IO uint32_t MMCRAEPR;

+  uint32_t      RESERVED18[10];

+  __IO uint32_t MMCRUPGR;

+  uint32_t      RESERVED19[9];

+  __IO uint32_t MMCTLPIMSTR;

+  __IO uint32_t MMCTLPITCR;

+  __IO uint32_t MMCRLPIMSTR;

+  __IO uint32_t MMCRLPITCR;

+  uint32_t      RESERVED20[65];

+  __IO uint32_t MACL3L4C0R;

+  __IO uint32_t MACL4A0R;

+  uint32_t      RESERVED21[2];

+  __IO uint32_t MACL3A0R0R;

+  __IO uint32_t MACL3A1R0R;

+  __IO uint32_t MACL3A2R0R;

+  __IO uint32_t MACL3A3R0R;

+  uint32_t      RESERVED22[4];

+  __IO uint32_t MACL3L4C1R;

+  __IO uint32_t MACL4A1R;

+  uint32_t      RESERVED23[2];

+  __IO uint32_t MACL3A0R1R;

+  __IO uint32_t MACL3A1R1R;

+  __IO uint32_t MACL3A2R1R;

+  __IO uint32_t MACL3A3R1R;

+  uint32_t      RESERVED24[108];

+  __IO uint32_t MACTSCR;

+  __IO uint32_t MACSSIR;

+  __IO uint32_t MACSTSR;

+  __IO uint32_t MACSTNR;

+  __IO uint32_t MACSTSUR;

+  __IO uint32_t MACSTNUR;

+  __IO uint32_t MACTSAR;

+  uint32_t      RESERVED25;

+  __IO uint32_t MACTSSR;

+  uint32_t      RESERVED26[3];

+  __IO uint32_t MACTTSSNR;

+  __IO uint32_t MACTTSSSR;

+  uint32_t      RESERVED27[2];

+  __IO uint32_t MACACR;

+  uint32_t      RESERVED28;

+  __IO uint32_t MACATSNR;

+  __IO uint32_t MACATSSR;

+  __IO uint32_t MACTSIACR;

+  __IO uint32_t MACTSEACR;

+  __IO uint32_t MACTSICNR;

+  __IO uint32_t MACTSECNR;

+  uint32_t      RESERVED29[4];

+  __IO uint32_t MACPPSCR;

+  uint32_t      RESERVED30[3];

+  __IO uint32_t MACPPSTTSR;

+  __IO uint32_t MACPPSTTNR;

+  __IO uint32_t MACPPSIR;

+  __IO uint32_t MACPPSWR;

+  uint32_t      RESERVED31[12];

+  __IO uint32_t MACPOCR;

+  __IO uint32_t MACSPI0R;

+  __IO uint32_t MACSPI1R;

+  __IO uint32_t MACSPI2R;

+  __IO uint32_t MACLMIR;

+  uint32_t      RESERVED32[11];

+  __IO uint32_t MTLOMR;

+  uint32_t      RESERVED33[7];

+  __IO uint32_t MTLISR;

+  uint32_t      RESERVED34[55];

+  __IO uint32_t MTLTQOMR;

+  __IO uint32_t MTLTQUR;

+  __IO uint32_t MTLTQDR;

+  uint32_t      RESERVED35[8];

+  __IO uint32_t MTLQICSR;

+  __IO uint32_t MTLRQOMR;

+  __IO uint32_t MTLRQMPOCR;

+  __IO uint32_t MTLRQDR;

+  uint32_t      RESERVED36[177];

+  __IO uint32_t DMAMR;

+  __IO uint32_t DMASBMR;

+  __IO uint32_t DMAISR;

+  __IO uint32_t DMADSR;

+  uint32_t      RESERVED37[60];

+  __IO uint32_t DMACCR;

+  __IO uint32_t DMACTCR;

+  __IO uint32_t DMACRCR;

+  uint32_t      RESERVED38[2];

+  __IO uint32_t DMACTDLAR;

+  uint32_t      RESERVED39;

+  __IO uint32_t DMACRDLAR;

+  __IO uint32_t DMACTDTPR;

+  uint32_t      RESERVED40;

+  __IO uint32_t DMACRDTPR;

+  __IO uint32_t DMACTDRLR;

+  __IO uint32_t DMACRDRLR;

+  __IO uint32_t DMACIER;

+  __IO uint32_t DMACRIWTR;

+__IO uint32_t DMACSFCSR;

+  uint32_t      RESERVED41;

+  __IO uint32_t DMACCATDR;

+  uint32_t      RESERVED42;

+  __IO uint32_t DMACCARDR;

+  uint32_t      RESERVED43;

+  __IO uint32_t DMACCATBR;

+  uint32_t      RESERVED44;

+  __IO uint32_t DMACCARBR;

+  __IO uint32_t DMACSR;

+uint32_t      RESERVED45[2];

+__IO uint32_t DMACMFCR;

+}ETH_TypeDef;

+/**

+  * @brief External Interrupt/Event Controller

+  */

+

+typedef struct

+{

+__IO uint32_t RTSR1;               /*!< EXTI Rising trigger selection register,          Address offset: 0x00 */

+__IO uint32_t FTSR1;               /*!< EXTI Falling trigger selection register,         Address offset: 0x04 */

+__IO uint32_t SWIER1;              /*!< EXTI Software interrupt event register,          Address offset: 0x08 */

+__IO uint32_t D3PMR1;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */

+__IO uint32_t D3PCR1L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L)     Address offset: 0x10 */

+__IO uint32_t D3PCR1H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H)   Address offset: 0x14 */

+uint32_t      RESERVED1[2];        /*!< Reserved,                                        0x18 to 0x1C         */

+__IO uint32_t RTSR2;               /*!< EXTI Rising trigger selection register,          Address offset: 0x20 */

+__IO uint32_t FTSR2;               /*!< EXTI Falling trigger selection register,         Address offset: 0x24 */

+__IO uint32_t SWIER2;              /*!< EXTI Software interrupt event register,          Address offset: 0x28 */

+__IO uint32_t D3PMR2;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */

+__IO uint32_t D3PCR2L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L)  Address offset: 0x30 */

+__IO uint32_t D3PCR2H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */

+uint32_t      RESERVED2[2];        /*!< Reserved,                                        0x38 to 0x3C         */

+__IO uint32_t RTSR3;               /*!< EXTI Rising trigger selection register,          Address offset: 0x40 */

+__IO uint32_t FTSR3;               /*!< EXTI Falling trigger selection register,         Address offset: 0x44 */

+__IO uint32_t SWIER3;              /*!< EXTI Software interrupt event register,          Address offset: 0x48 */

+__IO uint32_t D3PMR3;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */

+__IO uint32_t D3PCR3L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */

+__IO uint32_t D3PCR3H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */

+uint32_t      RESERVED3[10];       /*!< Reserved,                                        0x58 to 0x7C         */

+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                    Address offset: 0x80 */

+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                        Address offset: 0x84 */

+__IO uint32_t PR1;                 /*!< EXTI Pending register,                           Address offset: 0x88 */

+uint32_t      RESERVED4;           /*!< Reserved,                                        0x8C                 */

+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                    Address offset: 0x90 */

+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                        Address offset: 0x94 */

+__IO uint32_t PR2;                 /*!< EXTI Pending register,                           Address offset: 0x98 */

+uint32_t      RESERVED5;           /*!< Reserved,                                        0x9C                 */

+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                    Address offset: 0xA0 */

+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                        Address offset: 0xA4 */

+__IO uint32_t PR3;                 /*!< EXTI Pending register,                           Address offset: 0xA8 */

+}EXTI_TypeDef;

+

+typedef struct

+{

+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                Address offset: 0x00 */

+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                    Address offset: 0x04 */

+__IO uint32_t PR1;                 /*!< EXTI Pending register,                       Address offset: 0x08 */

+uint32_t      RESERVED1;           /*!< Reserved, 0x0C                                                    */

+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                Address offset: 0x10 */

+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                    Address offset: 0x14 */

+__IO uint32_t PR2;                 /*!< EXTI Pending register,                       Address offset: 0x18 */

+uint32_t      RESERVED2;           /*!< Reserved, 0x1C                                                    */

+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                Address offset: 0x20 */

+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                    Address offset: 0x24 */

+__IO uint32_t PR3;                 /*!< EXTI Pending register,                       Address offset: 0x28 */

+}EXTI_Core_TypeDef;

+

+

+/**

+  * @brief FLASH Registers

+  */

+

+typedef struct

+{

+  __IO uint32_t ACR;             /*!< FLASH access control register,                            Address offset: 0x00  */

+  __IO uint32_t KEYR1;           /*!< Flash Key Register for bank1,                             Address offset: 0x04  */

+  __IO uint32_t OPTKEYR;         /*!< Flash Option Key Register,                                Address offset: 0x08  */

+  __IO uint32_t CR1;             /*!< Flash Control Register for bank1,                         Address offset: 0x0C  */

+  __IO uint32_t SR1;             /*!< Flash Status Register for bank1,                          Address offset: 0x10  */

+  __IO uint32_t CCR1;            /*!< Flash Control Register for bank1,                         Address offset: 0x14  */

+  __IO uint32_t OPTCR;           /*!< Flash Option Control Register,                            Address offset: 0x18  */

+  __IO uint32_t OPTSR_CUR;       /*!< Flash Option Status Current Register,                     Address offset: 0x1C  */

+  __IO uint32_t OPTSR_PRG;       /*!< Flash Option Status to Program Register,                  Address offset: 0x20  */

+  __IO uint32_t OPTCCR;          /*!< Flash Option Clear Control Register,                      Address offset: 0x24  */

+  __IO uint32_t PRAR_CUR1;       /*!< Flash Current Protection Address Register for bank1,      Address offset: 0x28  */

+  __IO uint32_t PRAR_PRG1;       /*!< Flash Protection Address to Program Register for bank1,   Address offset: 0x2C  */

+  __IO uint32_t SCAR_CUR1;       /*!< Flash Current Secure Address Register for bank1,          Address offset: 0x30  */

+  __IO uint32_t SCAR_PRG1;       /*!< Flash Secure Address to Program Register for bank1,       Address offset: 0x34  */

+  __IO uint32_t WPSN_CUR1;       /*!< Flash Current Write Protection Register on bank1,         Address offset: 0x38  */

+  __IO uint32_t WPSN_PRG1;       /*!< Flash Write Protection to Program Register on bank1,      Address offset: 0x3C  */

+  __IO uint32_t BOOT_CUR;        /*!< Flash Current Boot Address for Pelican Core Register,     Address offset: 0x40  */

+  __IO uint32_t BOOT_PRG;        /*!< Flash Boot Address to Program for Pelican Core Register,  Address offset: 0x44  */

+  uint32_t      RESERVED0[2];    /*!< Reserved, 0x48 to 0x4C                                                          */

+  __IO uint32_t CRCCR1;          /*!< Flash CRC Control register For Bank1 Register ,           Address offset: 0x50  */

+  __IO uint32_t CRCSADD1;        /*!< Flash CRC Start Address Register for Bank1 ,              Address offset: 0x54  */

+  __IO uint32_t CRCEADD1;        /*!< Flash CRC End Address Register for Bank1 ,                Address offset: 0x58  */

+  __IO uint32_t CRCDATA;         /*!< Flash CRC Data Register for Bank1 ,                       Address offset: 0x5C  */

+  __IO uint32_t ECC_FA1;         /*!< Flash ECC Fail Address For Bank1 Register ,               Address offset: 0x60  */

+  uint32_t      RESERVED1[40];   /*!< Reserved, 0x64 to 0x100                                                         */

+  __IO uint32_t KEYR2;           /*!< Flash Key Register for bank2,                             Address offset: 0x104 */

+  uint32_t      RESERVED2;       /*!< Reserved, 0x108                                                                 */

+  __IO uint32_t CR2;             /*!< Flash Control Register for bank2,                         Address offset: 0x10C */

+  __IO uint32_t SR2;             /*!< Flash Status Register for bank2,                          Address offset: 0x110 */

+  __IO uint32_t CCR2;            /*!< Flash Status Register for bank2,                          Address offset: 0x114 */

+  uint32_t      RESERVED3[4];    /*!< Reserved, 0x118 to 0x124                                                        */

+  __IO uint32_t PRAR_CUR2;       /*!< Flash Current Protection Address Register for bank2,      Address offset: 0x128 */

+  __IO uint32_t PRAR_PRG2;       /*!< Flash Protection Address to Program Register for bank2,   Address offset: 0x12C */

+  __IO uint32_t SCAR_CUR2;       /*!< Flash Current Secure Address Register for bank2,          Address offset: 0x130 */

+  __IO uint32_t SCAR_PRG2;       /*!< Flash Secure Address Register for bank2,                  Address offset: 0x134 */

+  __IO uint32_t WPSN_CUR2;       /*!< Flash Current Write Protection Register on bank2,         Address offset: 0x138 */

+  __IO uint32_t WPSN_PRG2;       /*!< Flash Write Protection to Program Register on bank2,      Address offset: 0x13C */

+  uint32_t      RESERVED4[4];    /*!< Reserved, 0x140 to 0x14C                                                        */

+  __IO uint32_t CRCCR2;          /*!< Flash CRC Control register For Bank2 Register ,           Address offset: 0x150 */

+  __IO uint32_t CRCSADD2;        /*!< Flash CRC Start Address Register for Bank2 ,              Address offset: 0x154 */

+  __IO uint32_t CRCEADD2;        /*!< Flash CRC End Address Register for Bank2 ,                Address offset: 0x158 */

+  __IO uint32_t CRCDATA2;        /*!< Flash CRC Data Register for Bank2 ,                       Address offset: 0x15C */

+  __IO uint32_t ECC_FA2;         /*!< Flash ECC Fail Address For Bank2 Register ,               Address offset: 0x160 */

+} FLASH_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */

+} FMC_Bank1_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank1E

+  */

+

+typedef struct

+{

+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */

+} FMC_Bank1E_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank2

+  */

+

+typedef struct

+{

+  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */

+  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */

+  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */

+  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */

+  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */

+  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */

+} FMC_Bank2_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank3

+  */

+

+typedef struct

+{

+  __IO uint32_t PCR;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */

+  __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */

+  __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */

+  __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */

+  uint32_t      RESERVED;  /*!< Reserved, 0x90                                                            */

+  __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */

+} FMC_Bank3_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank5 and 6

+  */

+

+

+typedef struct

+{

+  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */

+  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */

+  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */

+  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */

+  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */

+} FMC_Bank5_6_TypeDef;

+

+/**

+  * @brief General Purpose I/O

+  */

+

+typedef struct

+{

+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */

+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */

+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */

+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */

+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */

+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */

+  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset,               Address offset: 0x18      */

+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */

+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */

+} GPIO_TypeDef;

+

+/**

+  * @brief Operational Amplifier (OPAMP)

+  */

+

+typedef struct

+{

+  __IO uint32_t CSR;          /*!< OPAMP control/status register,                      Address offset: 0x00 */

+  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,     Address offset: 0x04 */

+  __IO uint32_t HSOTR;        /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */

+} OPAMP_TypeDef;

+

+/**

+  * @brief System configuration controller

+  */

+

+typedef struct

+{

+ uint32_t RESERVED1;           /*!< Reserved,                                           Address offset: 0x00        */

+ __IO uint32_t PMCR;           /*!< SYSCFG peripheral mode configuration register,      Address offset: 0x04        */

+ __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration registers,  Address offset: 0x08-0x14   */

+ __IO uint32_t CFGR;           /*!< SYSCFG configuration registers,                     Address offset: 0x18        */

+ uint32_t RESERVED2;           /*!< Reserved,                                           Address offset: 0x1C        */

+ __IO uint32_t CCCSR;          /*!< SYSCFG compensation cell control/status register,   Address offset: 0x20        */

+ __IO uint32_t CCVR;           /*!< SYSCFG compensation cell value register,            Address offset: 0x24        */

+ __IO uint32_t CCCR;           /*!< SYSCFG compensation cell code register,             Address offset: 0x28        */

+ __IO uint32_t PWRCR;          /*!< PWR control register,                               Address offset: 0x2C        */

+  uint32_t     RESERVED3[61];  /*!< Reserved, 0x30-0x120                                                            */

+  __IO uint32_t PKGR;          /*!< SYSCFG package register,                            Address offset: 0x124       */

+  uint32_t     RESERVED4[118]; /*!< Reserved, 0x128-0x2FC                                                           */

+ __IO uint32_t UR0;            /*!< SYSCFG user register 0,                             Address offset: 0x300       */

+ __IO uint32_t UR1;            /*!< SYSCFG user register 1,                             Address offset: 0x304       */

+ __IO uint32_t UR2;            /*!< SYSCFG user register 2,                             Address offset: 0x308       */

+ __IO uint32_t UR3;            /*!< SYSCFG user register 3,                             Address offset: 0x30C       */

+ __IO uint32_t UR4;            /*!< SYSCFG user register 4,                             Address offset: 0x310       */

+ __IO uint32_t UR5;            /*!< SYSCFG user register 5,                             Address offset: 0x314       */

+ __IO uint32_t UR6;            /*!< SYSCFG user register 6,                             Address offset: 0x318       */

+ __IO uint32_t UR7;            /*!< SYSCFG user register 7,                             Address offset: 0x31C       */

+ __IO uint32_t UR8;            /*!< SYSCFG user register 8,                             Address offset: 0x320       */

+ __IO uint32_t UR9;            /*!< SYSCFG user register 9,                             Address offset: 0x324       */

+ __IO uint32_t UR10;           /*!< SYSCFG user register 10,                            Address offset: 0x328       */

+ __IO uint32_t UR11;           /*!< SYSCFG user register 11,                            Address offset: 0x32C       */

+ __IO uint32_t UR12;           /*!< SYSCFG user register 12,                            Address offset: 0x330       */

+ __IO uint32_t UR13;           /*!< SYSCFG user register 13,                            Address offset: 0x334       */

+ __IO uint32_t UR14;           /*!< SYSCFG user register 14,                            Address offset: 0x338       */

+ __IO uint32_t UR15;           /*!< SYSCFG user register 15,                            Address offset: 0x33C       */

+ __IO uint32_t UR16;           /*!< SYSCFG user register 16,                            Address offset: 0x340       */

+ __IO uint32_t UR17;           /*!< SYSCFG user register 17,                            Address offset: 0x344       */

+

+} SYSCFG_TypeDef;

+

+/**

+  * @brief Inter-integrated Circuit Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */

+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */

+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */

+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */

+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */

+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */

+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */

+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */

+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */

+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */

+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */

+} I2C_TypeDef;

+

+/**

+  * @brief Independent WATCHDOG

+  */

+

+typedef struct

+{

+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */

+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */

+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */

+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */

+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */

+} IWDG_TypeDef;

+

+

+/**

+  * @brief JPEG Codec

+  */

+typedef struct

+{

+  __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */

+  __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */

+  __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */

+  __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */

+  __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */

+  __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */

+  __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */

+  __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */

+  uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */

+  __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */

+  __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */

+  __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */

+  uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */

+  __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */

+  __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */

+  uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */

+  __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */

+  __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */

+  __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */

+  __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */

+  __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */

+  __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */

+  __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */

+  __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */

+  uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */

+  __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0,                 Address offset: 500h-65Ch */

+  __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1,                 Address offset: 660h-7BCh */

+  __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encodor, DC Huffman table 0,                 Address offset: 7C0h-7DCh */

+  __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encodor, DC Huffman table 1,                 Address offset: 7E0h-7FCh */

+

+} JPEG_TypeDef;

+

+/**

+  * @brief LCD-TFT Display Controller

+  */

+

+typedef struct

+{

+  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04                                                       */

+  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */

+  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */

+  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */

+  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */

+  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */

+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20                                                       */

+  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */

+  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28                                                            */

+  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */

+  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30                                                            */

+  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */

+  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */

+  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */

+  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */

+  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */

+  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */

+} LTDC_TypeDef;

+

+/**

+  * @brief LCD-TFT Display layer x Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */

+  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */

+  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */

+  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */

+  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */

+  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */

+  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */

+  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */

+  uint32_t      RESERVED0[2];  /*!< Reserved */

+  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */

+  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */

+  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */

+  uint32_t      RESERVED1[3];  /*!< Reserved */

+  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */

+

+} LTDC_Layer_TypeDef;

+

+/**

+  * @brief Power Control

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;       /*!< PWR power control register 1,            Address offset: 0x00 */

+  __IO uint32_t CSR1;      /*!< PWR power control status register 1,     Address offset: 0x04 */

+  __IO uint32_t CR2;       /*!< PWR power control register 2,            Address offset: 0x08 */

+  __IO uint32_t CR3;       /*!< PWR power control register 3,            Address offset: 0x0C */

+  __IO uint32_t CPUCR;     /*!< PWR CPU control register,                Address offset: 0x10 */

+       uint32_t RESERVED0; /*!< Reserved,                                Address offset: 0x14 */

+  __IO uint32_t D3CR;      /*!< PWR D3 domain control register,          Address offset: 0x18 */

+       uint32_t RESERVED1; /*!< Reserved,                                Address offset: 0x1C */

+  __IO uint32_t WKUPCR;    /*!< PWR wakeup clear register,               Address offset: 0x20 */

+  __IO uint32_t WKUPFR;    /*!< PWR wakeup flag register,                Address offset: 0x24 */

+  __IO uint32_t WKUPEPR;   /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */

+} PWR_TypeDef;

+

+/**

+  * @brief Reset and Clock Control

+  */

+

+typedef struct

+{

+ __IO uint32_t CR;             /*!< RCC clock control register,                                              Address offset: 0x00  */

+ __IO uint32_t HSICFGR;        /*!< HSI Clock Calibration Register,                                          Address offset: 0x04  */

+ __IO uint32_t CRRCR;          /*!< Clock Recovery RC  Register,                                             Address offset: 0x08  */

+ __IO uint32_t CSICFGR;        /*!< CSI Clock Calibration Register,                                          Address offset: 0x0C  */

+ __IO uint32_t CFGR;           /*!< RCC clock configuration register,                                        Address offset: 0x10  */

+ uint32_t     RESERVED1;       /*!< Reserved,                                                                Address offset: 0x14  */

+ __IO uint32_t D1CFGR;         /*!< RCC Domain 1 configuration register,                                     Address offset: 0x18  */

+ __IO uint32_t D2CFGR;         /*!< RCC Domain 2 configuration register,                                     Address offset: 0x1C  */

+ __IO uint32_t D3CFGR;         /*!< RCC Domain 3 configuration register,                                     Address offset: 0x20  */

+ uint32_t     RESERVED2;       /*!< Reserved,                                                                Address offset: 0x24  */

+ __IO uint32_t PLLCKSELR;      /*!< RCC PLLs Clock Source Selection Register,                                Address offset: 0x28  */

+ __IO uint32_t PLLCFGR;        /*!< RCC PLLs  Configuration Register,                                        Address offset: 0x2C  */

+ __IO uint32_t PLL1DIVR;       /*!< RCC PLL1 Dividers Configuration Register,                                Address offset: 0x30  */

+ __IO uint32_t PLL1FRACR;      /*!< RCC PLL1 Fractional Divider Configuration Register,                      Address offset: 0x34  */

+ __IO uint32_t PLL2DIVR;       /*!< RCC PLL2 Dividers Configuration Register,                                Address offset: 0x38  */

+ __IO uint32_t PLL2FRACR;      /*!< RCC PLL2 Fractional Divider Configuration Register,                      Address offset: 0x3C  */

+ __IO uint32_t PLL3DIVR;       /*!< RCC PLL3 Dividers Configuration Register,                                Address offset: 0x40  */

+ __IO uint32_t PLL3FRACR;      /*!< RCC PLL3 Fractional Divider Configuration Register,                      Address offset: 0x44  */

+ uint32_t      RESERVED3;      /*!< Reserved,                                                                Address offset: 0x48  */

+ __IO uint32_t  D1CCIPR;       /*!< RCC Domain 1 Kernel Clock Configuration Register                         Address offset: 0x4C  */

+ __IO uint32_t  D2CCIP1R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x50  */

+ __IO uint32_t  D2CCIP2R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x54  */

+ __IO uint32_t  D3CCIPR;       /*!< RCC Domain 3 Kernel Clock Configuration Register                         Address offset: 0x58  */

+ uint32_t      RESERVED4;      /*!< Reserved,                                                                Address offset: 0x5C  */

+ __IO uint32_t  CIER;          /*!< RCC Clock Source Interrupt Enable Register                               Address offset: 0x60  */

+ __IO uint32_t  CIFR;          /*!< RCC Clock Source Interrupt Flag Register                                 Address offset: 0x64  */

+ __IO uint32_t  CICR;          /*!< RCC Clock Source Interrupt Clear Register                                Address offset: 0x68  */

+ uint32_t     RESERVED5;       /*!< Reserved,                                                                Address offset: 0x6C  */

+ __IO uint32_t  BDCR;          /*!< RCC Vswitch Backup Domain Control Register,                              Address offset: 0x70  */

+ __IO uint32_t  CSR;           /*!< RCC clock control & status register,                                     Address offset: 0x74  */

+ uint32_t     RESERVED6;       /*!< Reserved,                                                                Address offset: 0x78  */

+ __IO uint32_t AHB3RSTR;       /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x7C  */

+ __IO uint32_t AHB1RSTR;       /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x80  */

+ __IO uint32_t AHB2RSTR;       /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x84  */

+ __IO uint32_t AHB4RSTR;       /*!< RCC AHB4 peripheral reset register,                                      Address offset: 0x88  */

+ __IO uint32_t APB3RSTR;       /*!< RCC APB3 peripheral reset register,                                      Address offset: 0x8C  */

+ __IO uint32_t APB1LRSTR;      /*!< RCC APB1 peripheral reset Low Word register,                             Address offset: 0x90  */

+ __IO uint32_t APB1HRSTR;      /*!< RCC APB1 peripheral reset High Word register,                            Address offset: 0x94  */

+ __IO uint32_t APB2RSTR;       /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x98  */

+ __IO uint32_t APB4RSTR;       /*!< RCC APB4 peripheral reset register,                                      Address offset: 0x9C  */

+ __IO uint32_t GCR;            /*!< RCC RCC Global Control  Register,                                        Address offset: 0xA0  */

+ uint32_t     RESERVED8;       /*!< Reserved,                                                                Address offset: 0xA4  */

+ __IO uint32_t D3AMR;          /*!< RCC Domain 3 Autonomous Mode Register,                                   Address offset: 0xA8  */

+ uint32_t     RESERVED11[9];    /*!< Reserved, 0xAC-0xCC                                                      Address offset: 0xAC  */

+ __IO uint32_t RSR;            /*!< RCC Reset status register,                                               Address offset: 0xD0  */

+ __IO uint32_t AHB3ENR;        /*!< RCC AHB3 peripheral clock  register,                                     Address offset: 0xD4  */

+ __IO uint32_t AHB1ENR;        /*!< RCC AHB1 peripheral clock  register,                                     Address offset: 0xD8  */

+ __IO uint32_t AHB2ENR;        /*!< RCC AHB2 peripheral clock  register,                                     Address offset: 0xDC  */

+ __IO uint32_t AHB4ENR;        /*!< RCC AHB4 peripheral clock  register,                                     Address offset: 0xE0  */

+ __IO uint32_t APB3ENR;        /*!< RCC APB3 peripheral clock  register,                                     Address offset: 0xE4  */

+ __IO uint32_t APB1LENR;       /*!< RCC APB1 peripheral clock  Low Word register,                            Address offset: 0xE8  */

+ __IO uint32_t APB1HENR;       /*!< RCC APB1 peripheral clock  High Word register,                           Address offset: 0xEC  */

+ __IO uint32_t APB2ENR;        /*!< RCC APB2 peripheral clock  register,                                     Address offset: 0xF0  */

+ __IO uint32_t APB4ENR;        /*!< RCC APB4 peripheral clock  register,                                     Address offset: 0xF4  */

+ uint32_t      RESERVED12;      /*!< Reserved,                                                                Address offset: 0xF8  */

+ __IO uint32_t AHB3LPENR;      /*!< RCC AHB3 peripheral sleep clock  register,                               Address offset: 0xFC  */

+ __IO uint32_t AHB1LPENR;      /*!< RCC AHB1 peripheral sleep clock  register,                               Address offset: 0x100 */

+ __IO uint32_t AHB2LPENR;      /*!< RCC AHB2 peripheral sleep clock  register,                               Address offset: 0x104 */

+ __IO uint32_t AHB4LPENR;      /*!< RCC AHB4 peripheral sleep clock  register,                               Address offset: 0x108 */

+ __IO uint32_t APB3LPENR;      /*!< RCC APB3 peripheral sleep clock  register,                               Address offset: 0x10C */

+ __IO uint32_t APB1LLPENR;     /*!< RCC APB1 peripheral sleep clock  Low Word register,                      Address offset: 0x110 */

+ __IO uint32_t APB1HLPENR;     /*!< RCC APB1 peripheral sleep clock  High Word register,                     Address offset: 0x114 */

+ __IO uint32_t APB2LPENR;      /*!< RCC APB2 peripheral sleep clock  register,                               Address offset: 0x118 */

+ __IO uint32_t APB4LPENR;      /*!< RCC APB4 peripheral sleep clock  register,                               Address offset: 0x11C */

+ uint32_t     RESERVED13[4];   /*!< Reserved, 0x120-0x12C                                                    Address offset: 0x120 */

+

+} RCC_TypeDef;

+

+

+/**

+  * @brief Real-Time Clock

+  */

+typedef struct

+{

+  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */

+  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */

+  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */

+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */

+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */

+  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */

+       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */

+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */

+  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */

+  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */

+  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */

+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */

+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */

+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */

+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */

+  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */

+  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */

+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */

+  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */

+  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset: 0x4C */

+  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */

+  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */

+  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */

+  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */

+  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */

+  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */

+  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */

+  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */

+  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */

+  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */

+  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */

+  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */

+  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */

+  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */

+  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */

+  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */

+  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */

+  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */

+  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */

+  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */

+  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */

+  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */

+  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */

+  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */

+  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */

+  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */

+  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */

+  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */

+  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */

+  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */

+  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */

+  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */

+} RTC_TypeDef;

+

+/**

+  * @brief Serial Audio Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t GCR;           /*!< SAI global configuration register, Address offset: 0x00 */

+  uint32_t      RESERVED0[16]; /*!< Reserved, 0x04 - 0x43                                   */

+  __IO uint32_t PDMCR;         /*!< SAI PDM control register,          Address offset: 0x44 */

+  __IO uint32_t PDMDLY;        /*!< SAI PDM delay register,            Address offset: 0x48 */

+} SAI_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */

+  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */

+  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */

+  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */

+  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */

+  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */

+  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */

+  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */

+} SAI_Block_TypeDef;

+

+/**

+  * @brief SPDIF-RX Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */

+  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */

+  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */

+  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */

+  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */

+  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */

+  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */

+  uint32_t        RESERVED2;    /*!< Reserved,  0x1A                                          */

+} SPDIFRX_TypeDef;

+

+

+/**

+  * @brief Secure digital input/output Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t POWER;          /*!< SDMMC power control register,             Address offset: 0x00  */

+  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,             Address offset: 0x04  */

+  __IO uint32_t ARG;            /*!< SDMMC argument register,                  Address offset: 0x08  */

+  __IO uint32_t CMD;            /*!< SDMMC command register,                   Address offset: 0x0C  */

+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register,          Address offset: 0x10  */

+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                Address offset: 0x14  */

+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                Address offset: 0x18  */

+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                Address offset: 0x1C  */

+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                Address offset: 0x20  */

+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                Address offset: 0x24  */

+  __IO uint32_t DLEN;           /*!< SDMMC data length register,               Address offset: 0x28  */

+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,              Address offset: 0x2C  */

+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,              Address offset: 0x30  */

+  __I uint32_t  STA;            /*!< SDMMC status register,                    Address offset: 0x34  */

+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,           Address offset: 0x38  */

+  __IO uint32_t MASK;           /*!< SDMMC mask register,                      Address offset: 0x3C  */

+  __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,     Address offset: 0x40  */

+  uint32_t      RESERVED0[3];   /*!< Reserved, 0x44 - 0x4C - 0x4C                                    */

+  __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,               Address offset: 0x50  */

+  __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,           Address offset: 0x54  */

+  __IO uint32_t IDMABASE0;      /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58  */

+  __IO uint32_t IDMABASE1;      /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C  */

+  uint32_t      RESERVED1[8];   /*!< Reserved, 0x60-0x7C                                             */

+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,                 Address offset: 0x80  */

+  uint32_t      RESERVED2[222]; /*!< Reserved, 0x84-0x3F8                                            */

+  __IO uint32_t IPVR;           /*!< SDMMC data FIFO register,                 Address offset: 0x3FC */

+} SDMMC_TypeDef;

+

+

+/**

+  * @brief Delay Block DLYB

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;          /*!< DELAY BLOCK control register,  Address offset: 0x00 */

+  __IO uint32_t CFGR;        /*!< DELAY BLOCK configuration register,  Address offset: 0x04 */

+} DLYB_TypeDef;

+

+/**

+  * @brief HW Semaphore HSEM

+  */

+

+typedef struct

+{

+  __IO uint32_t R[32];      /*!< 2-step write lock and read back registers,     Address offset: 00h-7Ch  */

+  __IO uint32_t RLR[32];    /*!< 1-step read lock registers,                    Address offset: 80h-FCh  */

+  __IO uint32_t C1IER;      /*!< HSEM Interrupt enable register ,             Address offset: 100h     */

+  __IO uint32_t C1ICR;      /*!< HSEM Interrupt clear register ,              Address offset: 104h     */

+  __IO uint32_t C1ISR;      /*!< HSEM Interrupt Status register ,             Address offset: 108h     */

+  __IO uint32_t C1MISR;     /*!< HSEM Interrupt Masked Status register ,      Address offset: 10Ch     */

+  uint32_t  Reserved[12];   /* Reserved                                       Address offset: 110h-13Ch  */

+  __IO uint32_t CR;         /*!< HSEM Semaphore clear register ,                Address offset: 140h      */

+  __IO uint32_t KEYR;       /*!< HSEM Semaphore clear key register ,            Address offset: 144h      */

+

+} HSEM_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t IER;        /*!< HSEM interrupt enable register ,                Address offset:   0h     */

+  __IO uint32_t ICR;        /*!< HSEM interrupt clear register ,                 Address offset:   4h     */

+  __IO uint32_t ISR;        /*!< HSEM interrupt status register ,                Address offset:   8h     */

+  __IO uint32_t MISR;       /*!< HSEM masked interrupt status register ,         Address offset:   Ch     */

+} HSEM_Common_TypeDef;

+

+/**

+  * @brief Serial Peripheral Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */

+  __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */

+  __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */

+  __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */

+  __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */

+  __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */

+  __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */

+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */

+  __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */

+  uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */

+  __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */

+  uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */

+  __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */

+  __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */

+  __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */

+  __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */

+  __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */

+

+} SPI_TypeDef;

+/**

+  * @brief QUAD Serial Peripheral Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */

+  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */

+  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */

+  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */

+  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */

+  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */

+  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */

+  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */

+  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */

+  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */

+  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */

+  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */

+  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */

+} QUADSPI_TypeDef;

+

+/**

+  * @brief TIM

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */

+  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */

+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */

+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */

+  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */

+  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */

+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */

+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */

+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */

+  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */

+  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */

+  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */

+  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */

+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */

+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */

+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */

+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */

+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */

+  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */

+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */

+  uint32_t      RESERVED1;   /*!< Reserved, 0x50                                                 */

+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */

+  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */

+  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */

+  __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */

+  __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */

+  __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x68 */

+} TIM_TypeDef;

+

+/**

+  * @brief LPTIMIMER

+  */

+typedef struct

+{

+  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,         Address offset: 0x00 */

+  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,              Address offset: 0x04 */

+  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,             Address offset: 0x08 */

+  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                Address offset: 0x0C */

+  __IO uint32_t CR;       /*!< LPTIM Control register,                      Address offset: 0x10 */

+  __IO uint32_t CMP;      /*!< LPTIM Compare register,                      Address offset: 0x14 */

+  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                   Address offset: 0x18 */

+  __IO uint32_t CNT;      /*!< LPTIM Counter register,                      Address offset: 0x1C */

+  uint32_t  RESERVED1;    /*!< Reserved, 0x20                                                    */

+  __IO uint32_t CFGR2;    /*!< LPTIM Configuration register,                Address offset: 0x24 */

+} LPTIM_TypeDef;

+

+/**

+  * @brief Comparator

+  */

+typedef struct

+{

+  __IO uint32_t SR;        /*!< Comparator status register,                    Address offset: 0x00 */

+  __IO uint32_t ICFR;      /*!< Comparator interrupt clear flag register,       Address offset: 0x04 */

+  __IO uint32_t OR;        /*!< Comparator option register,                  Address offset: 0x08 */

+} COMPOPT_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CFGR;      /*!< Comparator configuration register  ,           Address offset: 0x00 */

+} COMP_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CFGR;       /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */

+} COMP_Common_TypeDef;

+/**

+  * @brief Universal Synchronous Asynchronous Receiver Transmitter

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */

+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */

+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */

+  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */

+  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */

+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */

+  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */

+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */

+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */

+  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */

+  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */

+  __IO uint32_t PRESC;  /*!< USART clock Prescaler register,           Address offset: 0x2C */

+} USART_TypeDef;

+

+/**

+  * @brief Single Wire Protocol Master Interface SPWMI

+  */

+typedef struct

+{

+  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */

+  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */

+    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */

+  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */

+  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */

+  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */

+  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */

+  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */

+  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */

+  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */

+} SWPMI_TypeDef;

+

+/**

+  * @brief Window WATCHDOG

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */

+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */

+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */

+} WWDG_TypeDef;

+

+

+/**

+  * @brief RAM_ECC_Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t CR;           /*!< RAMECC monitor configuration register          */

+  __IO uint32_t SR;           /*!< RAMECC monitor status register                 */

+  __IO uint32_t FAR;          /*!< RAMECC monitor failing address register        */

+  __IO uint32_t FDRL;         /*!< RAMECC monitor failing data low register       */

+  __IO uint32_t FDRH;         /*!< RAMECC monitor failing data high register      */

+  __IO uint32_t FECR;         /*!< RAMECC monitor failing ECC error code register */

+} RAMECC_MonitorTypeDef;

+

+typedef struct

+{

+  __IO uint32_t IER;          /*!< RAMECC interrupt enable register */

+} RAMECC_TypeDef;

+/**

+  * @}

+  */

+

+

+

+/**

+  * @brief High resolution Timer (HRTIM)

+  */

+/* HRTIM master registers definition */

+typedef struct

+{

+  __IO uint32_t MCR;            /*!< HRTIM Master Timer control register,                     Address offset: 0x00 */

+  __IO uint32_t MISR;           /*!< HRTIM Master Timer interrupt status register,            Address offset: 0x04 */

+  __IO uint32_t MICR;           /*!< HRTIM Master Timer interupt clear register,              Address offset: 0x08 */

+  __IO uint32_t MDIER;          /*!< HRTIM Master Timer DMA/interrupt enable register         Address offset: 0x0C */

+  __IO uint32_t MCNTR;          /*!< HRTIM Master Timer counter register,                     Address offset: 0x10 */

+  __IO uint32_t MPER;           /*!< HRTIM Master Timer period register,                      Address offset: 0x14 */

+  __IO uint32_t MREP;           /*!< HRTIM Master Timer repetition register,                  Address offset: 0x18 */

+  __IO uint32_t MCMP1R;         /*!< HRTIM Master Timer compare 1 register,                   Address offset: 0x1C */

+  uint32_t      RESERVED0;     /*!< Reserved,                                                                 0x20 */

+  __IO uint32_t MCMP2R;         /*!< HRTIM Master Timer compare 2 register,                   Address offset: 0x24 */

+  __IO uint32_t MCMP3R;         /*!< HRTIM Master Timer compare 3 register,                   Address offset: 0x28 */

+  __IO uint32_t MCMP4R;         /*!< HRTIM Master Timer compare 4 register,                   Address offset: 0x2C */

+  uint32_t      RESERVED1[20];  /*!< Reserved,                                                          0x30..0x7C */

+}HRTIM_Master_TypeDef;

+

+/* HRTIM Timer A to E registers definition */

+typedef struct

+{

+  __IO uint32_t TIMxCR;     /*!< HRTIM Timerx control register,                              Address offset: 0x00 */

+  __IO uint32_t TIMxISR;    /*!< HRTIM Timerx interrupt status register,                     Address offset: 0x04 */

+  __IO uint32_t TIMxICR;    /*!< HRTIM Timerx interrupt clear register,                      Address offset: 0x08 */

+  __IO uint32_t TIMxDIER;   /*!< HRTIM Timerx DMA/interrupt enable register,                 Address offset: 0x0C */

+  __IO uint32_t CNTxR;      /*!< HRTIM Timerx counter register,                              Address offset: 0x10 */

+  __IO uint32_t PERxR;      /*!< HRTIM Timerx period register,                               Address offset: 0x14 */

+  __IO uint32_t REPxR;      /*!< HRTIM Timerx repetition register,                           Address offset: 0x18 */

+  __IO uint32_t CMP1xR;     /*!< HRTIM Timerx compare 1 register,                            Address offset: 0x1C */

+  __IO uint32_t CMP1CxR;    /*!< HRTIM Timerx compare 1 compound register,                   Address offset: 0x20 */

+  __IO uint32_t CMP2xR;     /*!< HRTIM Timerx compare 2 register,                            Address offset: 0x24 */

+  __IO uint32_t CMP3xR;     /*!< HRTIM Timerx compare 3 register,                            Address offset: 0x28 */

+  __IO uint32_t CMP4xR;     /*!< HRTIM Timerx compare 4 register,                            Address offset: 0x2C */

+  __IO uint32_t CPT1xR;     /*!< HRTIM Timerx capture 1 register,                            Address offset: 0x30 */

+  __IO uint32_t CPT2xR;     /*!< HRTIM Timerx capture 2 register,                            Address offset: 0x34 */

+  __IO uint32_t DTxR;       /*!< HRTIM Timerx dead time register,                            Address offset: 0x38 */

+  __IO uint32_t SETx1R;     /*!< HRTIM Timerx output 1 set register,                         Address offset: 0x3C */

+  __IO uint32_t RSTx1R;     /*!< HRTIM Timerx output 1 reset register,                       Address offset: 0x40 */

+  __IO uint32_t SETx2R;     /*!< HRTIM Timerx output 2 set register,                         Address offset: 0x44 */

+  __IO uint32_t RSTx2R;     /*!< HRTIM Timerx output 2 reset register,                       Address offset: 0x48 */

+  __IO uint32_t EEFxR1;     /*!< HRTIM Timerx external event filtering 1 register,           Address offset: 0x4C */

+  __IO uint32_t EEFxR2;     /*!< HRTIM Timerx external event filtering 2 register,           Address offset: 0x50 */

+  __IO uint32_t RSTxR;      /*!< HRTIM Timerx Reset register,                                Address offset: 0x54 */

+  __IO uint32_t CHPxR;      /*!< HRTIM Timerx Chopper register,                              Address offset: 0x58 */

+  __IO uint32_t CPT1xCR;    /*!< HRTIM Timerx Capture 1 register,                            Address offset: 0x5C */

+  __IO uint32_t CPT2xCR;    /*!< HRTIM Timerx Capture 2 register,                            Address offset: 0x60 */

+  __IO uint32_t OUTxR;      /*!< HRTIM Timerx Output register,                               Address offset: 0x64 */

+  __IO uint32_t FLTxR;      /*!< HRTIM Timerx Fault register,                                Address offset: 0x68 */

+  uint32_t      RESERVED0[5];  /*!< Reserved,                                                          0x6C..0x7C */

+}HRTIM_Timerx_TypeDef;

+

+/* HRTIM common register definition */

+typedef struct

+{

+  __IO uint32_t CR1;        /*!< HRTIM control register1,                                    Address offset: 0x00 */

+  __IO uint32_t CR2;        /*!< HRTIM control register2,                                    Address offset: 0x04 */

+  __IO uint32_t ISR;        /*!< HRTIM interrupt status register,                            Address offset: 0x08 */

+  __IO uint32_t ICR;        /*!< HRTIM interrupt clear register,                             Address offset: 0x0C */

+  __IO uint32_t IER;        /*!< HRTIM interrupt enable register,                            Address offset: 0x10 */

+  __IO uint32_t OENR;       /*!< HRTIM Output enable register,                               Address offset: 0x14 */

+  __IO uint32_t ODISR;      /*!< HRTIM Output disable register,                              Address offset: 0x18 */

+  __IO uint32_t ODSR;       /*!< HRTIM Output disable status register,                       Address offset: 0x1C */

+  __IO uint32_t BMCR;       /*!< HRTIM Burst mode control register,                          Address offset: 0x20 */

+  __IO uint32_t BMTRGR;     /*!< HRTIM Busrt mode trigger register,                          Address offset: 0x24 */

+  __IO uint32_t BMCMPR;     /*!< HRTIM Burst mode compare register,                          Address offset: 0x28 */

+  __IO uint32_t BMPER;      /*!< HRTIM Burst mode period register,                           Address offset: 0x2C */

+  __IO uint32_t EECR1;      /*!< HRTIM Timer external event control register1,               Address offset: 0x30 */

+  __IO uint32_t EECR2;      /*!< HRTIM Timer external event control register2,               Address offset: 0x34 */

+  __IO uint32_t EECR3;      /*!< HRTIM Timer external event control register3,               Address offset: 0x38 */

+  __IO uint32_t ADC1R;      /*!< HRTIM ADC Trigger 1 register,                               Address offset: 0x3C */

+  __IO uint32_t ADC2R;      /*!< HRTIM ADC Trigger 2 register,                               Address offset: 0x40 */

+  __IO uint32_t ADC3R;      /*!< HRTIM ADC Trigger 3 register,                               Address offset: 0x44 */

+  __IO uint32_t ADC4R;      /*!< HRTIM ADC Trigger 4 register,                               Address offset: 0x48 */

+  __IO uint32_t RESERVED0;  /*!< Reserved,                                                   Address offset: 0x4C */

+  __IO uint32_t FLTINR1;    /*!< HRTIM Fault input register1,                                Address offset: 0x50 */

+  __IO uint32_t FLTINR2;    /*!< HRTIM Fault input register2,                                Address offset: 0x54 */

+  __IO uint32_t BDMUPR;     /*!< HRTIM Burst DMA Master Timer update register,               Address offset: 0x58 */

+  __IO uint32_t BDTAUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x5C */

+  __IO uint32_t BDTBUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x60 */

+  __IO uint32_t BDTCUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x64 */

+  __IO uint32_t BDTDUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x68 */

+  __IO uint32_t BDTEUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x6C */

+  __IO uint32_t BDMADR;     /*!< HRTIM Burst DMA Master Data register,                       Address offset: 0x70 */

+}HRTIM_Common_TypeDef;

+

+/* HRTIM  register definition */

+typedef struct {

+  HRTIM_Master_TypeDef sMasterRegs;

+  HRTIM_Timerx_TypeDef sTimerxRegs[5];

+  uint32_t             RESERVED0[32];

+  HRTIM_Common_TypeDef sCommonRegs;

+}HRTIM_TypeDef;

+/**

+  * @brief RNG

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */

+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */

+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */

+} RNG_TypeDef;

+

+/**

+  * @brief MDIOS

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;

+  __IO uint32_t WRFR;

+  __IO uint32_t CWRFR;

+  __IO uint32_t RDFR;

+  __IO uint32_t CRDFR;

+  __IO uint32_t SR;

+  __IO uint32_t CLRFR;

+  uint32_t RESERVED[57];

+  __IO uint32_t DINR0;

+  __IO uint32_t DINR1;

+  __IO uint32_t DINR2;

+  __IO uint32_t DINR3;

+  __IO uint32_t DINR4;

+  __IO uint32_t DINR5;

+  __IO uint32_t DINR6;

+  __IO uint32_t DINR7;

+  __IO uint32_t DINR8;

+  __IO uint32_t DINR9;

+  __IO uint32_t DINR10;

+  __IO uint32_t DINR11;

+  __IO uint32_t DINR12;

+  __IO uint32_t DINR13;

+  __IO uint32_t DINR14;

+  __IO uint32_t DINR15;

+  __IO uint32_t DINR16;

+  __IO uint32_t DINR17;

+  __IO uint32_t DINR18;

+  __IO uint32_t DINR19;

+  __IO uint32_t DINR20;

+  __IO uint32_t DINR21;

+  __IO uint32_t DINR22;

+  __IO uint32_t DINR23;

+  __IO uint32_t DINR24;

+  __IO uint32_t DINR25;

+  __IO uint32_t DINR26;

+  __IO uint32_t DINR27;

+  __IO uint32_t DINR28;

+  __IO uint32_t DINR29;

+  __IO uint32_t DINR30;

+  __IO uint32_t DINR31;

+  __IO uint32_t DOUTR0;

+  __IO uint32_t DOUTR1;

+  __IO uint32_t DOUTR2;

+  __IO uint32_t DOUTR3;

+  __IO uint32_t DOUTR4;

+  __IO uint32_t DOUTR5;

+  __IO uint32_t DOUTR6;

+  __IO uint32_t DOUTR7;

+  __IO uint32_t DOUTR8;

+  __IO uint32_t DOUTR9;

+  __IO uint32_t DOUTR10;

+  __IO uint32_t DOUTR11;

+  __IO uint32_t DOUTR12;

+  __IO uint32_t DOUTR13;

+  __IO uint32_t DOUTR14;

+  __IO uint32_t DOUTR15;

+  __IO uint32_t DOUTR16;

+  __IO uint32_t DOUTR17;

+  __IO uint32_t DOUTR18;

+  __IO uint32_t DOUTR19;

+  __IO uint32_t DOUTR20;

+  __IO uint32_t DOUTR21;

+  __IO uint32_t DOUTR22;

+  __IO uint32_t DOUTR23;

+  __IO uint32_t DOUTR24;

+  __IO uint32_t DOUTR25;

+  __IO uint32_t DOUTR26;

+  __IO uint32_t DOUTR27;

+  __IO uint32_t DOUTR28;

+  __IO uint32_t DOUTR29;

+  __IO uint32_t DOUTR30;

+  __IO uint32_t DOUTR31;

+} MDIOS_TypeDef;

+

+

+/**

+  * @brief USB_OTG_Core_Registers

+  */

+typedef struct

+{

+ __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */

+  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */

+  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */

+  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */

+  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */

+  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */

+  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */

+  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */

+  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */

+  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */

+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */

+  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */

+  uint32_t Reserved30[2];             /*!< Reserved                                     030h */

+  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */

+  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */

+  __IO uint32_t GSNPSID;              /* USB_OTG core ID                                040h*/

+  __IO uint32_t GHWCFG1;              /* User HW config1                                044h*/

+  __IO uint32_t GHWCFG2;              /* User HW config2                                048h*/

+  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */

+  uint32_t  Reserved6;                /*!< Reserved                                     050h */

+  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */

+  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */

+  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */

+   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */

+    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */

+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */

+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */

+} USB_OTG_GlobalTypeDef;

+

+

+/**

+  * @brief USB_OTG_device_Registers

+  */

+typedef struct

+{

+  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */

+  __IO uint32_t DCTL;            /*!< dev Control Register         804h */

+  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */

+  uint32_t Reserved0C;           /*!< Reserved                     80Ch */

+  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */

+  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */

+  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */

+  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */

+  uint32_t  Reserved20;          /*!< Reserved                     820h */

+  uint32_t Reserved9;            /*!< Reserved                     824h */

+  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */

+  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */

+  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */

+  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */

+  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */

+  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */

+  uint32_t Reserved40;           /*!< dedicated EP mask            840h */

+  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */

+  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */

+  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */

+} USB_OTG_DeviceTypeDef;

+

+

+/**

+  * @brief USB_OTG_IN_Endpoint-Specific_Register

+  */

+typedef struct

+{

+  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */

+  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */

+  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */

+  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */

+  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */

+  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */

+  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */

+  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */

+} USB_OTG_INEndpointTypeDef;

+

+

+/**

+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */

+  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */

+  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */

+  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */

+  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */

+  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */

+  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */

+} USB_OTG_OUTEndpointTypeDef;

+

+

+/**

+  * @brief USB_OTG_Host_Mode_Register_Structures

+  */

+typedef struct

+{

+  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */

+  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */

+  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */

+  uint32_t Reserved40C;           /*!< Reserved                             40Ch */

+  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */

+  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */

+  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */

+} USB_OTG_HostTypeDef;

+

+/**

+  * @brief USB_OTG_Host_Channel_Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */

+  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */

+  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */

+  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */

+  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */

+  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */

+  uint32_t Reserved[2];           /*!< Reserved                                      */

+} USB_OTG_HostChannelTypeDef;

+/**

+  * @}

+  */

+

+

+/** @addtogroup Peripheral_memory_map

+  * @{

+  */

+#define D1_ITCMRAM_BASE           (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM  */

+#define D1_ITCMICP_BASE           (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM         */

+#define D1_DTCMRAM_BASE           (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM                            */

+#define D1_AXIFLASH_BASE          (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI                */

+#define D1_AXIICP_BASE            (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI          */

+#define D1_AXISRAM_BASE           (0x24000000UL) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI                */

+

+#define D2_AXISRAM_BASE           (0x10000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI                */

+#define D2_AHBSRAM_BASE           (0x30000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge    */

+

+#define D3_BKPSRAM_BASE           (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge                                */

+#define D3_SRAM_BASE              (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge                               */

+

+#define PERIPH_BASE               (0x40000000UL) /*!< Base address of : AHB/APB Peripherals                                                   */

+#define QSPI_BASE                 (0x90000000UL) /*!< Base address of : QSPI memories  accessible over AXI                                    */

+

+#define FLASH_BANK1_BASE          (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI                          */

+#define FLASH_BANK2_BASE          (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI                          */

+#define FLASH_END                 (0x081FFFFFUL) /*!< FLASH end address                                                                       */

+

+/* Legacy define */

+#define FLASH_BASE                FLASH_BANK1_BASE

+

+/*!< Device electronic signature memory map */

+#define UID_BASE                  (0x1FF1E800UL)            /*!< Unique device ID register base address */

+#define FLASHSIZE_BASE            (0x1FF1E880UL)            /*!< FLASH Size register base address */

+

+

+/*!< Peripheral memory map */

+#define D2_APB1PERIPH_BASE        PERIPH_BASE

+#define D2_APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)

+#define D2_AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)

+#define D2_AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)

+

+#define D1_APB1PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)

+#define D1_AHB1PERIPH_BASE       (PERIPH_BASE + 0x12000000UL)

+

+#define D3_APB1PERIPH_BASE       (PERIPH_BASE + 0x18000000UL)

+#define D3_AHB1PERIPH_BASE       (PERIPH_BASE + 0x18020000UL)

+

+/*!< Legacy Peripheral memory map */

+#define APB1PERIPH_BASE        PERIPH_BASE

+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)

+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)

+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)

+

+

+/*!< D1_AHB1PERIPH peripherals */

+

+#define MDMA_BASE             (D1_AHB1PERIPH_BASE + 0x0000UL)

+#define DMA2D_BASE            (D1_AHB1PERIPH_BASE + 0x1000UL)

+#define JPGDEC_BASE           (D1_AHB1PERIPH_BASE + 0x3000UL)

+#define FLASH_R_BASE          (D1_AHB1PERIPH_BASE + 0x2000UL)

+#define FMC_R_BASE            (D1_AHB1PERIPH_BASE + 0x4000UL)

+#define QSPI_R_BASE           (D1_AHB1PERIPH_BASE + 0x5000UL)

+#define DLYB_QSPI_BASE        (D1_AHB1PERIPH_BASE + 0x6000UL)

+#define SDMMC1_BASE           (D1_AHB1PERIPH_BASE + 0x7000UL)

+#define DLYB_SDMMC1_BASE      (D1_AHB1PERIPH_BASE + 0x8000UL)

+#define RAMECC1_BASE          (D1_AHB1PERIPH_BASE + 0x9000UL)

+

+/*!< D2_AHB1PERIPH peripherals */

+

+#define DMA1_BASE               (D2_AHB1PERIPH_BASE + 0x0000UL)

+#define DMA2_BASE               (D2_AHB1PERIPH_BASE + 0x0400UL)

+#define DMAMUX1_BASE            (D2_AHB1PERIPH_BASE + 0x0800UL)

+#define ADC1_BASE               (D2_AHB1PERIPH_BASE + 0x2000UL)

+#define ADC2_BASE               (D2_AHB1PERIPH_BASE + 0x2100UL)

+#define ADC12_COMMON_BASE       (D2_AHB1PERIPH_BASE + 0x2300UL)

+#define ETH_BASE                (D2_AHB1PERIPH_BASE + 0x8000UL)

+#define ETH_MAC_BASE            (ETH_BASE)

+

+/*!< USB registers base address */

+#define USB1_OTG_HS_PERIPH_BASE              (0x40040000UL)

+#define USB2_OTG_FS_PERIPH_BASE              (0x40080000UL)

+#define USB_OTG_GLOBAL_BASE                  (0x000UL)

+#define USB_OTG_DEVICE_BASE                  (0x800UL)

+#define USB_OTG_IN_ENDPOINT_BASE             (0x900UL)

+#define USB_OTG_OUT_ENDPOINT_BASE            (0xB00UL)

+#define USB_OTG_EP_REG_SIZE                  (0x20UL)

+#define USB_OTG_HOST_BASE                    (0x400UL)

+#define USB_OTG_HOST_PORT_BASE               (0x440UL)

+#define USB_OTG_HOST_CHANNEL_BASE            (0x500UL)

+#define USB_OTG_HOST_CHANNEL_SIZE            (0x20UL)

+#define USB_OTG_PCGCCTL_BASE                 (0xE00UL)

+#define USB_OTG_FIFO_BASE                    (0x1000UL)

+#define USB_OTG_FIFO_SIZE                    (0x1000UL)

+

+/*!< D2_AHB2PERIPH peripherals */

+

+#define DCMI_BASE              (D2_AHB2PERIPH_BASE + 0x0000UL)

+#define RNG_BASE               (D2_AHB2PERIPH_BASE + 0x1800UL)

+#define SDMMC2_BASE            (D2_AHB2PERIPH_BASE + 0x2400UL)

+#define DLYB_SDMMC2_BASE       (D2_AHB2PERIPH_BASE + 0x2800UL)

+#define RAMECC2_BASE           (D2_AHB2PERIPH_BASE + 0x3000UL)

+

+/*!< D3_AHB1PERIPH peripherals */

+#define GPIOA_BASE            (D3_AHB1PERIPH_BASE + 0x0000UL)

+#define GPIOB_BASE            (D3_AHB1PERIPH_BASE + 0x0400UL)

+#define GPIOC_BASE            (D3_AHB1PERIPH_BASE + 0x0800UL)

+#define GPIOD_BASE            (D3_AHB1PERIPH_BASE + 0x0C00UL)

+#define GPIOE_BASE            (D3_AHB1PERIPH_BASE + 0x1000UL)

+#define GPIOF_BASE            (D3_AHB1PERIPH_BASE + 0x1400UL)

+#define GPIOG_BASE            (D3_AHB1PERIPH_BASE + 0x1800UL)

+#define GPIOH_BASE            (D3_AHB1PERIPH_BASE + 0x1C00UL)

+#define GPIOI_BASE            (D3_AHB1PERIPH_BASE + 0x2000UL)

+#define GPIOJ_BASE            (D3_AHB1PERIPH_BASE + 0x2400UL)

+#define GPIOK_BASE            (D3_AHB1PERIPH_BASE + 0x2800UL)

+#define RCC_BASE              (D3_AHB1PERIPH_BASE + 0x4400UL)

+#define PWR_BASE              (D3_AHB1PERIPH_BASE + 0x4800UL)

+#define CRC_BASE              (D3_AHB1PERIPH_BASE + 0x4C00UL)

+#define BDMA_BASE             (D3_AHB1PERIPH_BASE + 0x5400UL)

+#define DMAMUX2_BASE          (D3_AHB1PERIPH_BASE + 0x5800UL)

+#define ADC3_BASE             (D3_AHB1PERIPH_BASE + 0x6000UL)

+#define ADC3_COMMON_BASE      (D3_AHB1PERIPH_BASE + 0x6300UL)

+#define HSEM_BASE             (D3_AHB1PERIPH_BASE + 0x6400UL)

+#define RAMECC3_BASE          (D3_AHB1PERIPH_BASE + 0x7000UL)

+

+/*!< D1_APB1PERIPH peripherals */

+#define LTDC_BASE             (D1_APB1PERIPH_BASE + 0x1000UL)

+#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84UL)

+#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104UL)

+#define WWDG1_BASE            (D1_APB1PERIPH_BASE + 0x3000UL)

+

+/*!< D2_APB1PERIPH peripherals */

+#define TIM2_BASE             (D2_APB1PERIPH_BASE + 0x0000UL)

+#define TIM3_BASE             (D2_APB1PERIPH_BASE + 0x0400UL)

+#define TIM4_BASE             (D2_APB1PERIPH_BASE + 0x0800UL)

+#define TIM5_BASE             (D2_APB1PERIPH_BASE + 0x0C00UL)

+#define TIM6_BASE             (D2_APB1PERIPH_BASE + 0x1000UL)

+#define TIM7_BASE             (D2_APB1PERIPH_BASE + 0x1400UL)

+#define TIM12_BASE            (D2_APB1PERIPH_BASE + 0x1800UL)

+#define TIM13_BASE            (D2_APB1PERIPH_BASE + 0x1C00UL)

+#define TIM14_BASE            (D2_APB1PERIPH_BASE + 0x2000UL)

+#define LPTIM1_BASE           (D2_APB1PERIPH_BASE + 0x2400UL)

+

+

+#define SPI2_BASE             (D2_APB1PERIPH_BASE + 0x3800UL)

+#define SPI3_BASE             (D2_APB1PERIPH_BASE + 0x3C00UL)

+#define SPDIFRX_BASE          (D2_APB1PERIPH_BASE + 0x4000UL)

+#define USART2_BASE           (D2_APB1PERIPH_BASE + 0x4400UL)

+#define USART3_BASE           (D2_APB1PERIPH_BASE + 0x4800UL)

+#define UART4_BASE            (D2_APB1PERIPH_BASE + 0x4C00UL)

+#define UART5_BASE            (D2_APB1PERIPH_BASE + 0x5000UL)

+#define I2C1_BASE             (D2_APB1PERIPH_BASE + 0x5400UL)

+#define I2C2_BASE             (D2_APB1PERIPH_BASE + 0x5800UL)

+#define I2C3_BASE             (D2_APB1PERIPH_BASE + 0x5C00UL)

+#define CEC_BASE              (D2_APB1PERIPH_BASE + 0x6C00UL)

+#define DAC1_BASE             (D2_APB1PERIPH_BASE + 0x7400UL)

+#define UART7_BASE            (D2_APB1PERIPH_BASE + 0x7800UL)

+#define UART8_BASE            (D2_APB1PERIPH_BASE + 0x7C00UL)

+#define CRS_BASE              (D2_APB1PERIPH_BASE + 0x8400UL)

+#define SWPMI1_BASE           (D2_APB1PERIPH_BASE + 0x8800UL)

+#define OPAMP_BASE            (D2_APB1PERIPH_BASE + 0x9000UL)

+#define OPAMP1_BASE           (D2_APB1PERIPH_BASE + 0x9000UL)

+#define OPAMP2_BASE           (D2_APB1PERIPH_BASE + 0x9010UL)

+#define MDIOS_BASE            (D2_APB1PERIPH_BASE + 0x9400UL)

+#define FDCAN1_BASE           (D2_APB1PERIPH_BASE + 0xA000UL)

+#define FDCAN2_BASE           (D2_APB1PERIPH_BASE + 0xA400UL)

+#define FDCAN_CCU_BASE        (D2_APB1PERIPH_BASE + 0xA800UL)

+#define SRAMCAN_BASE          (D2_APB1PERIPH_BASE + 0xAC00UL)

+

+/*!< D2_APB2PERIPH peripherals */

+

+#define TIM1_BASE             (D2_APB2PERIPH_BASE + 0x0000UL)

+#define TIM8_BASE             (D2_APB2PERIPH_BASE + 0x0400UL)

+#define USART1_BASE           (D2_APB2PERIPH_BASE + 0x1000UL)

+#define USART6_BASE           (D2_APB2PERIPH_BASE + 0x1400UL)

+#define SPI1_BASE             (D2_APB2PERIPH_BASE + 0x3000UL)

+#define SPI4_BASE             (D2_APB2PERIPH_BASE + 0x3400UL)

+#define TIM15_BASE            (D2_APB2PERIPH_BASE + 0x4000UL)

+#define TIM16_BASE            (D2_APB2PERIPH_BASE + 0x4400UL)

+#define TIM17_BASE            (D2_APB2PERIPH_BASE + 0x4800UL)

+#define SPI5_BASE             (D2_APB2PERIPH_BASE + 0x5000UL)

+#define SAI1_BASE             (D2_APB2PERIPH_BASE + 0x5800UL)

+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)

+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)

+#define SAI2_BASE             (D2_APB2PERIPH_BASE + 0x5C00UL)

+#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004UL)

+#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024UL)

+#define SAI3_BASE             (D2_APB2PERIPH_BASE + 0x6000UL)

+#define SAI3_Block_A_BASE     (SAI3_BASE + 0x004UL)

+#define SAI3_Block_B_BASE     (SAI3_BASE + 0x024UL)

+#define DFSDM1_BASE           (D2_APB2PERIPH_BASE + 0x7000UL)

+#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00UL)

+#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20UL)

+#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40UL)

+#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60UL)

+#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80UL)

+#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0UL)

+#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0UL)

+#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0UL)

+#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)

+#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)

+#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)

+#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)

+#define HRTIM1_BASE           (D2_APB2PERIPH_BASE + 0x7400UL)

+#define HRTIM1_TIMA_BASE      (HRTIM1_BASE + 0x00000080UL)

+#define HRTIM1_TIMB_BASE      (HRTIM1_BASE + 0x00000100UL)

+#define HRTIM1_TIMC_BASE      (HRTIM1_BASE + 0x00000180UL)

+#define HRTIM1_TIMD_BASE      (HRTIM1_BASE + 0x00000200UL)

+#define HRTIM1_TIME_BASE      (HRTIM1_BASE + 0x00000280UL)

+#define HRTIM1_COMMON_BASE    (HRTIM1_BASE + 0x00000380UL)

+

+

+/*!< D3_APB1PERIPH peripherals */

+#define EXTI_BASE             (D3_APB1PERIPH_BASE + 0x0000UL)

+#define EXTI_D1_BASE          (EXTI_BASE + 0x0080UL)

+#define EXTI_D2_BASE          (EXTI_BASE + 0x00C0UL)

+#define SYSCFG_BASE           (D3_APB1PERIPH_BASE + 0x0400UL)

+#define LPUART1_BASE          (D3_APB1PERIPH_BASE + 0x0C00UL)

+#define SPI6_BASE             (D3_APB1PERIPH_BASE + 0x1400UL)

+#define I2C4_BASE             (D3_APB1PERIPH_BASE + 0x1C00UL)

+#define LPTIM2_BASE           (D3_APB1PERIPH_BASE + 0x2400UL)

+#define LPTIM3_BASE           (D3_APB1PERIPH_BASE + 0x2800UL)

+#define LPTIM4_BASE           (D3_APB1PERIPH_BASE + 0x2C00UL)

+#define LPTIM5_BASE           (D3_APB1PERIPH_BASE + 0x3000UL)

+#define COMP12_BASE           (D3_APB1PERIPH_BASE + 0x3800UL)

+#define COMP1_BASE            (COMP12_BASE + 0x0CUL)

+#define COMP2_BASE            (COMP12_BASE + 0x10UL)

+#define VREFBUF_BASE          (D3_APB1PERIPH_BASE + 0x3C00UL)

+#define RTC_BASE              (D3_APB1PERIPH_BASE + 0x4000UL)

+#define IWDG1_BASE            (D3_APB1PERIPH_BASE + 0x4800UL)

+

+

+#define SAI4_BASE             (D3_APB1PERIPH_BASE + 0x5400UL)

+#define SAI4_Block_A_BASE     (SAI4_BASE + 0x004UL)

+#define SAI4_Block_B_BASE     (SAI4_BASE + 0x024UL)

+

+

+

+

+#define BDMA_Channel0_BASE    (BDMA_BASE + 0x0008UL)

+#define BDMA_Channel1_BASE    (BDMA_BASE + 0x001CUL)

+#define BDMA_Channel2_BASE    (BDMA_BASE + 0x0030UL)

+#define BDMA_Channel3_BASE    (BDMA_BASE + 0x0044UL)

+#define BDMA_Channel4_BASE    (BDMA_BASE + 0x0058UL)

+#define BDMA_Channel5_BASE    (BDMA_BASE + 0x006CUL)

+#define BDMA_Channel6_BASE    (BDMA_BASE + 0x0080UL)

+#define BDMA_Channel7_BASE    (BDMA_BASE + 0x0094UL)

+

+#define DMAMUX2_Channel0_BASE    (DMAMUX2_BASE)

+#define DMAMUX2_Channel1_BASE    (DMAMUX2_BASE + 0x0004UL)

+#define DMAMUX2_Channel2_BASE    (DMAMUX2_BASE + 0x0008UL)

+#define DMAMUX2_Channel3_BASE    (DMAMUX2_BASE + 0x000CUL)

+#define DMAMUX2_Channel4_BASE    (DMAMUX2_BASE + 0x0010UL)

+#define DMAMUX2_Channel5_BASE    (DMAMUX2_BASE + 0x0014UL)

+#define DMAMUX2_Channel6_BASE    (DMAMUX2_BASE + 0x0018UL)

+#define DMAMUX2_Channel7_BASE    (DMAMUX2_BASE + 0x001CUL)

+

+#define DMAMUX2_RequestGenerator0_BASE  (DMAMUX2_BASE + 0x0100UL)

+#define DMAMUX2_RequestGenerator1_BASE  (DMAMUX2_BASE + 0x0104UL)

+#define DMAMUX2_RequestGenerator2_BASE  (DMAMUX2_BASE + 0x0108UL)

+#define DMAMUX2_RequestGenerator3_BASE  (DMAMUX2_BASE + 0x010CUL)

+#define DMAMUX2_RequestGenerator4_BASE  (DMAMUX2_BASE + 0x0110UL)

+#define DMAMUX2_RequestGenerator5_BASE  (DMAMUX2_BASE + 0x0114UL)

+#define DMAMUX2_RequestGenerator6_BASE  (DMAMUX2_BASE + 0x0118UL)

+#define DMAMUX2_RequestGenerator7_BASE  (DMAMUX2_BASE + 0x011CUL)

+

+#define DMAMUX2_ChannelStatus_BASE      (DMAMUX2_BASE + 0x0080UL)

+#define DMAMUX2_RequestGenStatus_BASE   (DMAMUX2_BASE + 0x0140UL)

+

+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)

+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)

+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)

+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)

+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)

+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)

+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)

+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)

+

+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)

+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)

+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)

+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)

+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)

+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)

+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)

+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)

+

+#define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)

+#define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)

+#define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)

+#define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)

+#define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)

+#define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)

+#define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0018UL)

+#define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x001CUL)

+#define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0020UL)

+#define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x0024UL)

+#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)

+#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)

+#define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)

+#define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)

+#define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)

+#define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)

+

+#define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)

+#define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)

+#define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)

+#define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)

+#define DMAMUX1_RequestGenerator4_BASE  (DMAMUX1_BASE + 0x0110UL)

+#define DMAMUX1_RequestGenerator5_BASE  (DMAMUX1_BASE + 0x0114UL)

+#define DMAMUX1_RequestGenerator6_BASE  (DMAMUX1_BASE + 0x0118UL)

+#define DMAMUX1_RequestGenerator7_BASE  (DMAMUX1_BASE + 0x011CUL)

+

+#define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)

+#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)

+

+/*!< FMC Banks registers base  address */

+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)

+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)

+#define FMC_Bank2_R_BASE      (FMC_R_BASE + 0x0060UL)

+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)

+#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)

+

+/* Debug MCU registers base address */

+#define DBGMCU_BASE           (0x5C001000UL)

+

+#define MDMA_Channel0_BASE    (MDMA_BASE + 0x00000040UL)

+#define MDMA_Channel1_BASE    (MDMA_BASE + 0x00000080UL)

+#define MDMA_Channel2_BASE    (MDMA_BASE + 0x000000C0UL)

+#define MDMA_Channel3_BASE    (MDMA_BASE + 0x00000100UL)

+#define MDMA_Channel4_BASE    (MDMA_BASE + 0x00000140UL)

+#define MDMA_Channel5_BASE    (MDMA_BASE + 0x00000180UL)

+#define MDMA_Channel6_BASE    (MDMA_BASE + 0x000001C0UL)

+#define MDMA_Channel7_BASE    (MDMA_BASE + 0x00000200UL)

+#define MDMA_Channel8_BASE    (MDMA_BASE + 0x00000240UL)

+#define MDMA_Channel9_BASE    (MDMA_BASE + 0x00000280UL)

+#define MDMA_Channel10_BASE   (MDMA_BASE + 0x000002C0UL)

+#define MDMA_Channel11_BASE   (MDMA_BASE + 0x00000300UL)

+#define MDMA_Channel12_BASE   (MDMA_BASE + 0x00000340UL)

+#define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)

+#define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)

+#define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)

+

+#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)

+#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)

+#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)

+#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)

+#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)

+

+#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)

+#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)

+#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)

+#define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL)

+#define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL)

+

+#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)

+#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)

+

+

+/**

+  * @}

+  */

+

+/** @addtogroup Peripheral_declaration

+  * @{

+  */

+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)

+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)

+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)

+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)

+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)

+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)

+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)

+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)

+#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)

+#define RTC                 ((RTC_TypeDef *) RTC_BASE)

+#define WWDG1               ((WWDG_TypeDef *) WWDG1_BASE)

+

+

+#define IWDG1               ((IWDG_TypeDef *) IWDG1_BASE)

+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)

+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)

+#define SPI4                ((SPI_TypeDef *) SPI4_BASE)

+#define SPI5                ((SPI_TypeDef *) SPI5_BASE)

+#define SPI6                ((SPI_TypeDef *) SPI6_BASE)

+#define USART2              ((USART_TypeDef *) USART2_BASE)

+#define USART3              ((USART_TypeDef *) USART3_BASE)

+#define USART6              ((USART_TypeDef *) USART6_BASE)

+#define UART7               ((USART_TypeDef *) UART7_BASE)

+#define UART8               ((USART_TypeDef *) UART8_BASE)

+#define CRS                 ((CRS_TypeDef *) CRS_BASE)

+#define UART4               ((USART_TypeDef *) UART4_BASE)

+#define UART5               ((USART_TypeDef *) UART5_BASE)

+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)

+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)

+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)

+#define I2C4                ((I2C_TypeDef *) I2C4_BASE)

+#define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

+#define FDCAN2              ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

+#define FDCAN_CCU           ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

+#define CEC                 ((CEC_TypeDef *) CEC_BASE)

+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)

+#define PWR                 ((PWR_TypeDef *) PWR_BASE)

+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)

+#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)

+#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)

+#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)

+#define LPTIM3              ((LPTIM_TypeDef *) LPTIM3_BASE)

+#define LPTIM4              ((LPTIM_TypeDef *) LPTIM4_BASE)

+#define LPTIM5              ((LPTIM_TypeDef *) LPTIM5_BASE)

+

+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)

+#define COMP12              ((COMPOPT_TypeDef *) COMP12_BASE)

+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)

+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)

+#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)

+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)

+#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)

+#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)

+

+

+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)

+#define EXTI_D1             ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

+#define EXTI_D2             ((EXTI_Core_TypeDef *) EXTI_D2_BASE)

+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)

+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)

+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)

+#define USART1              ((USART_TypeDef *) USART1_BASE)

+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)

+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)

+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)

+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)

+#define HRTIM1              ((HRTIM_TypeDef *) HRTIM1_BASE)

+#define HRTIM1_TIMA         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)

+#define HRTIM1_TIMB         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)

+#define HRTIM1_TIMC         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)

+#define HRTIM1_TIMD         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)

+#define HRTIM1_TIME         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)

+#define HRTIM1_COMMON       ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)

+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)

+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

+#define SAI2                ((SAI_TypeDef *) SAI2_BASE)

+#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)

+#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)

+#define SAI3                ((SAI_TypeDef *) SAI3_BASE)

+#define SAI3_Block_A        ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)

+#define SAI3_Block_B        ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)

+#define SAI4                ((SAI_TypeDef *) SAI4_BASE)

+#define SAI4_Block_A        ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)

+#define SAI4_Block_B        ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)

+

+#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

+#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

+#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

+#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

+#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

+#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

+#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

+#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

+#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

+#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

+#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

+#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

+#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

+#define DMA2D               ((DMA2D_TypeDef *) DMA2D_BASE)

+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)

+#define RCC                 ((RCC_TypeDef *) RCC_BASE)

+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)

+#define CRC                 ((CRC_TypeDef *) CRC_BASE)

+

+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)

+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)

+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)

+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)

+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)

+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)

+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)

+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)

+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)

+#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)

+#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)

+

+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)

+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)

+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)

+#define ADC3_COMMON         ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)

+#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

+

+#define RNG                 ((RNG_TypeDef *) RNG_BASE)

+#define SDMMC2              ((SDMMC_TypeDef *) SDMMC2_BASE)

+#define DLYB_SDMMC2         ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

+

+#define BDMA                ((BDMA_TypeDef *) BDMA_BASE)

+#define BDMA_Channel0       ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)

+#define BDMA_Channel1       ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)

+#define BDMA_Channel2       ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)

+#define BDMA_Channel3       ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)

+#define BDMA_Channel4       ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)

+#define BDMA_Channel5       ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)

+#define BDMA_Channel6       ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)

+#define BDMA_Channel7       ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)

+

+#define RAMECC1              ((RAMECC_TypeDef *)RAMECC1_BASE)

+#define RAMECC1_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)

+#define RAMECC1_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)

+#define RAMECC1_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)

+#define RAMECC1_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)

+#define RAMECC1_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)

+

+#define RAMECC2              ((RAMECC_TypeDef *)RAMECC2_BASE)

+#define RAMECC2_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)

+#define RAMECC2_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)

+#define RAMECC2_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)

+#define RAMECC2_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)

+#define RAMECC2_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)

+

+#define RAMECC3              ((RAMECC_TypeDef *)RAMECC3_BASE)

+#define RAMECC3_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)

+#define RAMECC3_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)

+

+#define DMAMUX2                ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

+#define DMAMUX2_Channel0       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

+#define DMAMUX2_Channel1       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

+#define DMAMUX2_Channel2       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

+#define DMAMUX2_Channel3       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

+#define DMAMUX2_Channel4       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

+#define DMAMUX2_Channel5       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

+#define DMAMUX2_Channel6       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

+#define DMAMUX2_Channel7       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

+

+

+#define DMAMUX2_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

+#define DMAMUX2_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

+#define DMAMUX2_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

+#define DMAMUX2_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

+#define DMAMUX2_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

+#define DMAMUX2_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

+#define DMAMUX2_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

+#define DMAMUX2_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

+

+#define DMAMUX2_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

+#define DMAMUX2_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

+

+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)

+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

+

+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)

+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

+

+

+#define DMAMUX1              ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

+#define DMAMUX1_Channel0     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

+#define DMAMUX1_Channel1     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

+#define DMAMUX1_Channel2     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

+#define DMAMUX1_Channel3     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

+#define DMAMUX1_Channel4     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

+#define DMAMUX1_Channel5     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

+#define DMAMUX1_Channel6     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

+#define DMAMUX1_Channel7     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

+#define DMAMUX1_Channel8     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

+#define DMAMUX1_Channel9     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

+#define DMAMUX1_Channel10    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

+#define DMAMUX1_Channel11    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

+#define DMAMUX1_Channel12    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

+#define DMAMUX1_Channel13    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

+#define DMAMUX1_Channel14    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

+#define DMAMUX1_Channel15    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

+

+#define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

+#define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

+#define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

+#define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

+#define DMAMUX1_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

+#define DMAMUX1_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

+#define DMAMUX1_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

+#define DMAMUX1_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

+

+#define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *)    DMAMUX1_ChannelStatus_BASE)

+#define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

+

+

+#define FMC_Bank1_R           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

+#define FMC_Bank1E_R          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

+#define FMC_Bank2_R           ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

+#define FMC_Bank3_R           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

+#define FMC_Bank5_6_R         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

+

+

+#define QUADSPI               ((QUADSPI_TypeDef *) QSPI_R_BASE)

+#define DLYB_QUADSPI          ((DLYB_TypeDef *) DLYB_QSPI_BASE)

+#define SDMMC1                ((SDMMC_TypeDef *) SDMMC1_BASE)

+#define DLYB_SDMMC1           ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

+

+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)

+

+#define JPEG                ((JPEG_TypeDef *) JPGDEC_BASE)

+#define HSEM                ((HSEM_TypeDef *) HSEM_BASE)

+#define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

+

+#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)

+#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

+#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

+

+#define MDIOS               ((MDIOS_TypeDef *) MDIOS_BASE)

+

+#define ETH                 ((ETH_TypeDef *)ETH_BASE)

+#define MDMA                ((MDMA_TypeDef *)MDMA_BASE)

+#define MDMA_Channel0       ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

+#define MDMA_Channel1       ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

+#define MDMA_Channel2       ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

+#define MDMA_Channel3       ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

+#define MDMA_Channel4       ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

+#define MDMA_Channel5       ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

+#define MDMA_Channel6       ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

+#define MDMA_Channel7       ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

+#define MDMA_Channel8       ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

+#define MDMA_Channel9       ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

+#define MDMA_Channel10      ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

+#define MDMA_Channel11      ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

+#define MDMA_Channel12      ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

+#define MDMA_Channel13      ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

+#define MDMA_Channel14      ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

+#define MDMA_Channel15      ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

+

+

+#define USB1_OTG_HS         ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

+#define USB2_OTG_FS         ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)

+

+/* Legacy defines */

+#define USB_OTG_HS                   USB1_OTG_HS

+#define USB_OTG_HS_PERIPH_BASE       USB1_OTG_HS_PERIPH_BASE

+#define USB_OTG_FS                   USB2_OTG_FS

+#define USB_OTG_FS_PERIPH_BASE       USB2_OTG_FS_PERIPH_BASE

+

+/**

+  * @}

+  */

+

+/** @addtogroup Exported_constants

+  * @{

+  */

+

+  /** @addtogroup Peripheral_Registers_Bits_Definition

+  * @{

+  */

+

+/******************************************************************************/

+/*                         Peripheral Registers_Bits_Definition               */

+/******************************************************************************/

+

+/******************************************************************************/

+/*                                                                            */

+/*                        Analog to Digital Converter                         */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  ADC VERSION  ********************************/

+#define ADC_VER_V5_X

+/********************  Bit definition for ADC_ISR register  ********************/

+#define ADC_ISR_ADRDY_Pos                 (0U)

+#define ADC_ISR_ADRDY_Msk                 (0x1UL << ADC_ISR_ADRDY_Pos)         /*!< 0x00000001 */

+#define ADC_ISR_ADRDY                     ADC_ISR_ADRDY_Msk                    /*!< ADC Ready (ADRDY) flag  */

+#define ADC_ISR_EOSMP_Pos                 (1U)

+#define ADC_ISR_EOSMP_Msk                 (0x1UL << ADC_ISR_EOSMP_Pos)         /*!< 0x00000002 */

+#define ADC_ISR_EOSMP                     ADC_ISR_EOSMP_Msk                    /*!< ADC End of Sampling flag */

+#define ADC_ISR_EOC_Pos                   (2U)

+#define ADC_ISR_EOC_Msk                   (0x1UL << ADC_ISR_EOC_Pos)           /*!< 0x00000004 */

+#define ADC_ISR_EOC                       ADC_ISR_EOC_Msk                      /*!< ADC End of Regular Conversion flag */

+#define ADC_ISR_EOS_Pos                   (3U)

+#define ADC_ISR_EOS_Msk                   (0x1UL << ADC_ISR_EOS_Pos)           /*!< 0x00000008 */

+#define ADC_ISR_EOS                       ADC_ISR_EOS_Msk                      /*!< ADC End of Regular sequence of Conversions flag */

+#define ADC_ISR_OVR_Pos                   (4U)

+#define ADC_ISR_OVR_Msk                   (0x1UL << ADC_ISR_OVR_Pos)           /*!< 0x00000010 */

+#define ADC_ISR_OVR                       ADC_ISR_OVR_Msk                      /*!< ADC overrun flag */

+#define ADC_ISR_JEOC_Pos                  (5U)

+#define ADC_ISR_JEOC_Msk                  (0x1UL << ADC_ISR_JEOC_Pos)          /*!< 0x00000020 */

+#define ADC_ISR_JEOC                      ADC_ISR_JEOC_Msk                     /*!< ADC End of Injected Conversion flag */

+#define ADC_ISR_JEOS_Pos                  (6U)

+#define ADC_ISR_JEOS_Msk                  (0x1UL << ADC_ISR_JEOS_Pos)          /*!< 0x00000040 */

+#define ADC_ISR_JEOS                      ADC_ISR_JEOS_Msk                     /*!< ADC End of Injected sequence of Conversions flag */

+#define ADC_ISR_AWD1_Pos                  (7U)

+#define ADC_ISR_AWD1_Msk                  (0x1UL << ADC_ISR_AWD1_Pos)          /*!< 0x00000080 */

+#define ADC_ISR_AWD1                      ADC_ISR_AWD1_Msk                     /*!< ADC Analog watchdog 1 flag */

+#define ADC_ISR_AWD2_Pos                  (8U)

+#define ADC_ISR_AWD2_Msk                  (0x1UL << ADC_ISR_AWD2_Pos)          /*!< 0x00000100 */

+#define ADC_ISR_AWD2                      ADC_ISR_AWD2_Msk                     /*!< ADC Analog watchdog 2 flag */

+#define ADC_ISR_AWD3_Pos                  (9U)

+#define ADC_ISR_AWD3_Msk                  (0x1UL << ADC_ISR_AWD3_Pos)          /*!< 0x00000200 */

+#define ADC_ISR_AWD3                      ADC_ISR_AWD3_Msk                     /*!< ADC Analog watchdog 3 flag */

+#define ADC_ISR_JQOVF_Pos                 (10U)

+#define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */

+#define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */

+

+/********************  Bit definition for ADC_IER register  ********************/

+#define ADC_IER_ADRDYIE_Pos               (0U)

+#define ADC_IER_ADRDYIE_Msk               (0x1UL << ADC_IER_ADRDYIE_Pos)       /*!< 0x00000001 */

+#define ADC_IER_ADRDYIE                   ADC_IER_ADRDYIE_Msk                  /*!< ADC Ready (ADRDY) interrupt source */

+#define ADC_IER_EOSMPIE_Pos               (1U)

+#define ADC_IER_EOSMPIE_Msk               (0x1UL << ADC_IER_EOSMPIE_Pos)       /*!< 0x00000002 */

+#define ADC_IER_EOSMPIE                   ADC_IER_EOSMPIE_Msk                  /*!< ADC End of Sampling interrupt source */

+#define ADC_IER_EOCIE_Pos                 (2U)

+#define ADC_IER_EOCIE_Msk                 (0x1UL << ADC_IER_EOCIE_Pos)         /*!< 0x00000004 */

+#define ADC_IER_EOCIE                     ADC_IER_EOCIE_Msk                    /*!< ADC End of Regular Conversion interrupt source */

+#define ADC_IER_EOSIE_Pos                 (3U)

+#define ADC_IER_EOSIE_Msk                 (0x1UL << ADC_IER_EOSIE_Pos)         /*!< 0x00000008 */

+#define ADC_IER_EOSIE                     ADC_IER_EOSIE_Msk                    /*!< ADC End of Regular sequence of Conversions interrupt source */

+#define ADC_IER_OVRIE_Pos                 (4U)

+#define ADC_IER_OVRIE_Msk                 (0x1UL << ADC_IER_OVRIE_Pos)         /*!< 0x00000010 */

+#define ADC_IER_OVRIE                     ADC_IER_OVRIE_Msk                    /*!< ADC overrun interrupt source */

+#define ADC_IER_JEOCIE_Pos                (5U)

+#define ADC_IER_JEOCIE_Msk                (0x1UL << ADC_IER_JEOCIE_Pos)        /*!< 0x00000020 */

+#define ADC_IER_JEOCIE                    ADC_IER_JEOCIE_Msk                   /*!< ADC End of Injected Conversion interrupt source */

+#define ADC_IER_JEOSIE_Pos                (6U)

+#define ADC_IER_JEOSIE_Msk                (0x1UL << ADC_IER_JEOSIE_Pos)        /*!< 0x00000040 */

+#define ADC_IER_JEOSIE                    ADC_IER_JEOSIE_Msk                   /*!< ADC End of Injected sequence of Conversions interrupt source */

+#define ADC_IER_AWD1IE_Pos                (7U)

+#define ADC_IER_AWD1IE_Msk                (0x1UL << ADC_IER_AWD1IE_Pos)        /*!< 0x00000080 */

+#define ADC_IER_AWD1IE                    ADC_IER_AWD1IE_Msk                   /*!< ADC Analog watchdog 1 interrupt source */

+#define ADC_IER_AWD2IE_Pos                (8U)

+#define ADC_IER_AWD2IE_Msk                (0x1UL << ADC_IER_AWD2IE_Pos)        /*!< 0x00000100 */

+#define ADC_IER_AWD2IE                    ADC_IER_AWD2IE_Msk                   /*!< ADC Analog watchdog 2 interrupt source */

+#define ADC_IER_AWD3IE_Pos                (9U)

+#define ADC_IER_AWD3IE_Msk                (0x1UL << ADC_IER_AWD3IE_Pos)        /*!< 0x00000200 */

+#define ADC_IER_AWD3IE                    ADC_IER_AWD3IE_Msk                   /*!< ADC Analog watchdog 3 interrupt source */

+#define ADC_IER_JQOVFIE_Pos               (10U)

+#define ADC_IER_JQOVFIE_Msk               (0x1UL << ADC_IER_JQOVFIE_Pos)       /*!< 0x00000400 */

+#define ADC_IER_JQOVFIE                   ADC_IER_JQOVFIE_Msk                  /*!< ADC Injected Context Queue Overflow interrupt source */

+

+/********************  Bit definition for ADC_CR register  ********************/

+#define ADC_CR_ADEN_Pos                   (0U)

+#define ADC_CR_ADEN_Msk                   (0x1UL << ADC_CR_ADEN_Pos)           /*!< 0x00000001 */

+#define ADC_CR_ADEN                       ADC_CR_ADEN_Msk                      /*!< ADC Enable control */

+#define ADC_CR_ADDIS_Pos                  (1U)

+#define ADC_CR_ADDIS_Msk                  (0x1UL << ADC_CR_ADDIS_Pos)          /*!< 0x00000002 */

+#define ADC_CR_ADDIS                      ADC_CR_ADDIS_Msk                     /*!< ADC Disable command */

+#define ADC_CR_ADSTART_Pos                (2U)

+#define ADC_CR_ADSTART_Msk                (0x1UL << ADC_CR_ADSTART_Pos)        /*!< 0x00000004 */

+#define ADC_CR_ADSTART                    ADC_CR_ADSTART_Msk                   /*!< ADC Start of Regular conversion */

+#define ADC_CR_JADSTART_Pos               (3U)

+#define ADC_CR_JADSTART_Msk               (0x1UL << ADC_CR_JADSTART_Pos)       /*!< 0x00000008 */

+#define ADC_CR_JADSTART                   ADC_CR_JADSTART_Msk                  /*!< ADC Start of injected conversion */

+#define ADC_CR_ADSTP_Pos                  (4U)

+#define ADC_CR_ADSTP_Msk                  (0x1UL << ADC_CR_ADSTP_Pos)          /*!< 0x00000010 */

+#define ADC_CR_ADSTP                      ADC_CR_ADSTP_Msk                     /*!< ADC Stop of Regular conversion */

+#define ADC_CR_JADSTP_Pos                 (5U)

+#define ADC_CR_JADSTP_Msk                 (0x1UL << ADC_CR_JADSTP_Pos)         /*!< 0x00000020 */

+#define ADC_CR_JADSTP                     ADC_CR_JADSTP_Msk                    /*!< ADC Stop of injected conversion */

+#define ADC_CR_BOOST_Pos                  (8U)

+#define ADC_CR_BOOST_Msk                  (0x3UL << ADC_CR_BOOST_Pos)          /*!< 0x00000300 */

+#define ADC_CR_BOOST                      ADC_CR_BOOST_Msk                     /*!< ADC Boost Mode configuration */

+#define ADC_CR_BOOST_0                    (0x1UL << ADC_CR_BOOST_Pos)           /*!< 0x00000100 */

+#define ADC_CR_BOOST_1                    (0x2UL << ADC_CR_BOOST_Pos)           /*!< 0x00000200 */

+#define ADC_CR_ADCALLIN_Pos               (16U)

+#define ADC_CR_ADCALLIN_Msk               (0x1UL << ADC_CR_ADCALLIN_Pos)       /*!< 0x00010000 */

+#define ADC_CR_ADCALLIN                   ADC_CR_ADCALLIN_Msk                  /*!< ADC Linearity calibration */

+#define ADC_CR_LINCALRDYW1_Pos            (22U)

+#define ADC_CR_LINCALRDYW1_Msk            (0x1UL << ADC_CR_LINCALRDYW1_Pos)    /*!< 0x00400000 */

+#define ADC_CR_LINCALRDYW1                ADC_CR_LINCALRDYW1_Msk               /*!< ADC Linearity calibration ready Word 1 */

+#define ADC_CR_LINCALRDYW2_Pos            (23U)

+#define ADC_CR_LINCALRDYW2_Msk            (0x1UL << ADC_CR_LINCALRDYW2_Pos)    /*!< 0x00800000 */

+#define ADC_CR_LINCALRDYW2                ADC_CR_LINCALRDYW2_Msk               /*!< ADC Linearity calibration ready Word 2 */

+#define ADC_CR_LINCALRDYW3_Pos            (24U)

+#define ADC_CR_LINCALRDYW3_Msk            (0x1UL << ADC_CR_LINCALRDYW3_Pos)    /*!< 0x01000000 */

+#define ADC_CR_LINCALRDYW3                ADC_CR_LINCALRDYW3_Msk               /*!< ADC Linearity calibration ready Word 3 */

+#define ADC_CR_LINCALRDYW4_Pos            (25U)

+#define ADC_CR_LINCALRDYW4_Msk            (0x1UL << ADC_CR_LINCALRDYW4_Pos)    /*!< 0x02000000 */

+#define ADC_CR_LINCALRDYW4                ADC_CR_LINCALRDYW4_Msk               /*!< ADC Linearity calibration ready Word 4 */

+#define ADC_CR_LINCALRDYW5_Pos            (26U)

+#define ADC_CR_LINCALRDYW5_Msk            (0x1UL << ADC_CR_LINCALRDYW5_Pos)    /*!< 0x04000000 */

+#define ADC_CR_LINCALRDYW5                ADC_CR_LINCALRDYW5_Msk               /*!< ADC Linearity calibration ready Word 5 */

+#define ADC_CR_LINCALRDYW6_Pos            (27U)

+#define ADC_CR_LINCALRDYW6_Msk            (0x1UL << ADC_CR_LINCALRDYW6_Pos)    /*!< 0x08000000 */

+#define ADC_CR_LINCALRDYW6                ADC_CR_LINCALRDYW6_Msk               /*!< ADC Linearity calibration ready Word 6 */

+#define ADC_CR_ADVREGEN_Pos               (28U)

+#define ADC_CR_ADVREGEN_Msk               (0x1UL << ADC_CR_ADVREGEN_Pos)       /*!< 0x10000000 */

+#define ADC_CR_ADVREGEN                   ADC_CR_ADVREGEN_Msk                  /*!< ADC Voltage regulator Enable */

+#define ADC_CR_DEEPPWD_Pos                (29U)

+#define ADC_CR_DEEPPWD_Msk                (0x1UL << ADC_CR_DEEPPWD_Pos)        /*!< 0x20000000 */

+#define ADC_CR_DEEPPWD                    ADC_CR_DEEPPWD_Msk                   /*!< ADC Deep power down Enable */

+#define ADC_CR_ADCALDIF_Pos               (30U)

+#define ADC_CR_ADCALDIF_Msk               (0x1UL << ADC_CR_ADCALDIF_Pos)       /*!< 0x40000000 */

+#define ADC_CR_ADCALDIF                   ADC_CR_ADCALDIF_Msk                  /*!< ADC Differential Mode for calibration */

+#define ADC_CR_ADCAL_Pos                  (31U)

+#define ADC_CR_ADCAL_Msk                  (0x1UL << ADC_CR_ADCAL_Pos)          /*!< 0x80000000 */

+#define ADC_CR_ADCAL                      ADC_CR_ADCAL_Msk                     /*!< ADC Calibration */

+

+/********************  Bit definition for ADC_CFGR register  ********************/

+#define ADC_CFGR_DMNGT_Pos                (0U)

+#define ADC_CFGR_DMNGT_Msk                (0x3UL << ADC_CFGR_DMNGT_Pos)        /*!< 0x00000003 */

+#define ADC_CFGR_DMNGT                    ADC_CFGR_DMNGT_Msk                   /*!< ADC Data Management configuration */

+#define ADC_CFGR_DMNGT_0                  (0x1UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000001 */

+#define ADC_CFGR_DMNGT_1                  (0x2UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000002 */

+

+#define ADC_CFGR_RES_Pos                  (2U)

+#define ADC_CFGR_RES_Msk                  (0x7UL << ADC_CFGR_RES_Pos)          /*!< 0x0000001C */

+#define ADC_CFGR_RES                      ADC_CFGR_RES_Msk                     /*!< ADC Data resolution */

+#define ADC_CFGR_RES_0                    (0x1UL << ADC_CFGR_RES_Pos)           /*!< 0x00000004 */

+#define ADC_CFGR_RES_1                    (0x2UL << ADC_CFGR_RES_Pos)           /*!< 0x00000008 */

+#define ADC_CFGR_RES_2                    (0x4UL << ADC_CFGR_RES_Pos)           /*!< 0x00000010 */

+

+#define ADC_CFGR_EXTSEL_Pos               (5U)

+#define ADC_CFGR_EXTSEL_Msk               (0x1FUL << ADC_CFGR_EXTSEL_Pos)      /*!< 0x000003E0 */

+#define ADC_CFGR_EXTSEL                   ADC_CFGR_EXTSEL_Msk                  /*!< ADC External trigger selection for regular group */

+#define ADC_CFGR_EXTSEL_0                 (0x01UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000020 */

+#define ADC_CFGR_EXTSEL_1                 (0x02UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000040 */

+#define ADC_CFGR_EXTSEL_2                 (0x04UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000080 */

+#define ADC_CFGR_EXTSEL_3                 (0x08UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000100 */

+#define ADC_CFGR_EXTSEL_4                 (0x10UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000200 */

+

+#define ADC_CFGR_EXTEN_Pos                (10U)

+#define ADC_CFGR_EXTEN_Msk                (0x3UL << ADC_CFGR_EXTEN_Pos)        /*!< 0x00000C00 */

+#define ADC_CFGR_EXTEN                    ADC_CFGR_EXTEN_Msk                   /*!< ADC External trigger enable and polarity selection for regular channels */

+#define ADC_CFGR_EXTEN_0                  (0x1UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000400 */

+#define ADC_CFGR_EXTEN_1                  (0x2UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000800 */

+

+#define ADC_CFGR_OVRMOD_Pos               (12U)

+#define ADC_CFGR_OVRMOD_Msk               (0x1UL << ADC_CFGR_OVRMOD_Pos)       /*!< 0x00001000 */

+#define ADC_CFGR_OVRMOD                   ADC_CFGR_OVRMOD_Msk                  /*!< ADC overrun mode */

+#define ADC_CFGR_CONT_Pos                 (13U)

+#define ADC_CFGR_CONT_Msk                 (0x1UL << ADC_CFGR_CONT_Pos)         /*!< 0x00002000 */

+#define ADC_CFGR_CONT                     ADC_CFGR_CONT_Msk                    /*!< ADC Single/continuous conversion mode for regular conversion */

+#define ADC_CFGR_AUTDLY_Pos               (14U)

+#define ADC_CFGR_AUTDLY_Msk               (0x1UL << ADC_CFGR_AUTDLY_Pos)       /*!< 0x00004000 */

+#define ADC_CFGR_AUTDLY                   ADC_CFGR_AUTDLY_Msk                  /*!< ADC Delayed conversion mode */

+

+#define ADC_CFGR_DISCEN_Pos               (16U)

+#define ADC_CFGR_DISCEN_Msk               (0x1UL << ADC_CFGR_DISCEN_Pos)       /*!< 0x00010000 */

+#define ADC_CFGR_DISCEN                   ADC_CFGR_DISCEN_Msk                  /*!< ADC Discontinuous mode for regular channels */

+

+#define ADC_CFGR_DISCNUM_Pos              (17U)

+#define ADC_CFGR_DISCNUM_Msk              (0x7UL << ADC_CFGR_DISCNUM_Pos)      /*!< 0x000E0000 */

+#define ADC_CFGR_DISCNUM                  ADC_CFGR_DISCNUM_Msk                 /*!< ADC Discontinuous mode channel count */

+#define ADC_CFGR_DISCNUM_0                (0x1UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00020000 */

+#define ADC_CFGR_DISCNUM_1                (0x2UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00040000 */

+#define ADC_CFGR_DISCNUM_2                (0x4UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00080000 */

+

+#define ADC_CFGR_JDISCEN_Pos              (20U)

+#define ADC_CFGR_JDISCEN_Msk              (0x1UL << ADC_CFGR_JDISCEN_Pos)      /*!< 0x00100000 */

+#define ADC_CFGR_JDISCEN                  ADC_CFGR_JDISCEN_Msk                 /*!< ADC Discontinuous mode on injected channels */

+#define ADC_CFGR_JQM_Pos                  (21U)

+#define ADC_CFGR_JQM_Msk                  (0x1UL << ADC_CFGR_JQM_Pos)          /*!< 0x00200000 */

+#define ADC_CFGR_JQM                      ADC_CFGR_JQM_Msk                     /*!< ADC JSQR Queue mode */

+#define ADC_CFGR_AWD1SGL_Pos              (22U)

+#define ADC_CFGR_AWD1SGL_Msk              (0x1UL << ADC_CFGR_AWD1SGL_Pos)      /*!< 0x00400000 */

+#define ADC_CFGR_AWD1SGL                  ADC_CFGR_AWD1SGL_Msk                 /*!< Enable the watchdog 1 on a single channel or on all channels */

+#define ADC_CFGR_AWD1EN_Pos               (23U)

+#define ADC_CFGR_AWD1EN_Msk               (0x1UL << ADC_CFGR_AWD1EN_Pos)       /*!< 0x00800000 */

+#define ADC_CFGR_AWD1EN                   ADC_CFGR_AWD1EN_Msk                  /*!< ADC Analog watchdog 1 enable on regular Channels */

+#define ADC_CFGR_JAWD1EN_Pos              (24U)

+#define ADC_CFGR_JAWD1EN_Msk              (0x1UL << ADC_CFGR_JAWD1EN_Pos)      /*!< 0x01000000 */

+#define ADC_CFGR_JAWD1EN                  ADC_CFGR_JAWD1EN_Msk                 /*!< ADC Analog watchdog 1 enable on injected Channels */

+#define ADC_CFGR_JAUTO_Pos                (25U)

+#define ADC_CFGR_JAUTO_Msk                (0x1UL << ADC_CFGR_JAUTO_Pos)        /*!< 0x02000000 */

+#define ADC_CFGR_JAUTO                    ADC_CFGR_JAUTO_Msk                   /*!< ADC Automatic injected group conversion */

+

+#define ADC_CFGR_AWD1CH_Pos               (26U)

+#define ADC_CFGR_AWD1CH_Msk               (0x1FUL << ADC_CFGR_AWD1CH_Pos)      /*!< 0x7C000000 */

+#define ADC_CFGR_AWD1CH                   ADC_CFGR_AWD1CH_Msk                  /*!< ADC Analog watchdog 1 Channel selection */

+#define ADC_CFGR_AWD1CH_0                 (0x01UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x04000000 */

+#define ADC_CFGR_AWD1CH_1                 (0x02UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x08000000 */

+#define ADC_CFGR_AWD1CH_2                 (0x04UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x10000000 */

+#define ADC_CFGR_AWD1CH_3                 (0x08UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x20000000 */

+#define ADC_CFGR_AWD1CH_4                 (0x10UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x40000000 */

+

+#define ADC_CFGR_JQDIS_Pos                (31U)

+#define ADC_CFGR_JQDIS_Msk                (0x1UL << ADC_CFGR_JQDIS_Pos)        /*!< 0x80000000 */

+#define ADC_CFGR_JQDIS                    ADC_CFGR_JQDIS_Msk                   /*!< ADC Injected queue disable */

+

+/********************  Bit definition for ADC_CFGR2 register  ********************/

+#define ADC_CFGR2_ROVSE_Pos               (0U)

+#define ADC_CFGR2_ROVSE_Msk               (0x1UL << ADC_CFGR2_ROVSE_Pos)       /*!< 0x00000001 */

+#define ADC_CFGR2_ROVSE                   ADC_CFGR2_ROVSE_Msk                  /*!< ADC Regular group oversampler enable */

+#define ADC_CFGR2_JOVSE_Pos               (1U)

+#define ADC_CFGR2_JOVSE_Msk               (0x1UL << ADC_CFGR2_JOVSE_Pos)       /*!< 0x00000002 */

+#define ADC_CFGR2_JOVSE                   ADC_CFGR2_JOVSE_Msk                  /*!< ADC Injected group oversampler enable */

+

+#define ADC_CFGR2_OVSS_Pos                (5U)

+#define ADC_CFGR2_OVSS_Msk                (0xFUL << ADC_CFGR2_OVSS_Pos)        /*!< 0x000001E0 */

+#define ADC_CFGR2_OVSS                    ADC_CFGR2_OVSS_Msk                   /*!< ADC Regular Oversampling shift */

+#define ADC_CFGR2_OVSS_0                  (0x1UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000020 */

+#define ADC_CFGR2_OVSS_1                  (0x2UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000040 */

+#define ADC_CFGR2_OVSS_2                  (0x4UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000080 */

+#define ADC_CFGR2_OVSS_3                  (0x8UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000100 */

+

+#define ADC_CFGR2_TROVS_Pos               (9U)

+#define ADC_CFGR2_TROVS_Msk               (0x1UL << ADC_CFGR2_TROVS_Pos)       /*!< 0x00000200 */

+#define ADC_CFGR2_TROVS                   ADC_CFGR2_TROVS_Msk                  /*!< ADC Triggered regular Oversampling */

+#define ADC_CFGR2_ROVSM_Pos               (10U)

+#define ADC_CFGR2_ROVSM_Msk               (0x1UL << ADC_CFGR2_ROVSM_Pos)       /*!< 0x00000400 */

+#define ADC_CFGR2_ROVSM                   ADC_CFGR2_ROVSM_Msk                  /*!< ADC Regular oversampling mode */

+

+#define ADC_CFGR2_RSHIFT1_Pos             (11U)

+#define ADC_CFGR2_RSHIFT1_Msk             (0x1UL << ADC_CFGR2_RSHIFT1_Pos)     /*!< 0x00000800 */

+#define ADC_CFGR2_RSHIFT1                 ADC_CFGR2_RSHIFT1_Msk                /*!< ADC Right-shift data after Offset 1 correction */

+#define ADC_CFGR2_RSHIFT2_Pos             (12U)

+#define ADC_CFGR2_RSHIFT2_Msk             (0x1UL << ADC_CFGR2_RSHIFT2_Pos)     /*!< 0x00001000 */

+#define ADC_CFGR2_RSHIFT2                 ADC_CFGR2_RSHIFT2_Msk                /*!< ADC Right-shift data after Offset 2 correction */

+#define ADC_CFGR2_RSHIFT3_Pos             (13U)

+#define ADC_CFGR2_RSHIFT3_Msk             (0x1UL << ADC_CFGR2_RSHIFT3_Pos)     /*!< 0x00002000 */

+#define ADC_CFGR2_RSHIFT3                 ADC_CFGR2_RSHIFT3_Msk                /*!< ADC Right-shift data after Offset 3 correction */

+#define ADC_CFGR2_RSHIFT4_Pos             (14U)

+#define ADC_CFGR2_RSHIFT4_Msk             (0x1UL << ADC_CFGR2_RSHIFT4_Pos)     /*!< 0x00004000 */

+#define ADC_CFGR2_RSHIFT4                 ADC_CFGR2_RSHIFT4_Msk                /*!< ADC Right-shift data after Offset 4 correction */

+

+#define ADC_CFGR2_OVSR_Pos                (16U)

+#define ADC_CFGR2_OVSR_Msk                (0x3FFUL << ADC_CFGR2_OVSR_Pos)      /*!< 0x03FF0000 */

+#define ADC_CFGR2_OVSR                    ADC_CFGR2_OVSR_Msk                   /*!< ADC oversampling Ratio */

+#define ADC_CFGR2_OVSR_0                  (0x001UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00010000 */

+#define ADC_CFGR2_OVSR_1                  (0x002UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00020000 */

+#define ADC_CFGR2_OVSR_2                  (0x004UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00040000 */

+#define ADC_CFGR2_OVSR_3                  (0x008UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00080000 */

+#define ADC_CFGR2_OVSR_4                  (0x010UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00100000 */

+#define ADC_CFGR2_OVSR_5                  (0x020UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00200000 */

+#define ADC_CFGR2_OVSR_6                  (0x040UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00400000 */

+#define ADC_CFGR2_OVSR_7                  (0x080UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00800000 */

+#define ADC_CFGR2_OVSR_8                  (0x100UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x01000000 */

+#define ADC_CFGR2_OVSR_9                  (0x200UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x02000000 */

+

+#define ADC_CFGR2_LSHIFT_Pos              (28U)

+#define ADC_CFGR2_LSHIFT_Msk              (0xFUL << ADC_CFGR2_LSHIFT_Pos)      /*!< 0xF0000000 */

+#define ADC_CFGR2_LSHIFT                  ADC_CFGR2_LSHIFT_Msk                 /*!< ADC Left shift factor */

+#define ADC_CFGR2_LSHIFT_0                (0x1UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x10000000 */

+#define ADC_CFGR2_LSHIFT_1                (0x2UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x20000000 */

+#define ADC_CFGR2_LSHIFT_2                (0x4UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x40000000 */

+#define ADC_CFGR2_LSHIFT_3                (0x8UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_SMPR1 register  ********************/

+#define ADC_SMPR1_SMP0_Pos                (0U)

+#define ADC_SMPR1_SMP0_Msk                (0x7UL << ADC_SMPR1_SMP0_Pos)        /*!< 0x00000007 */

+#define ADC_SMPR1_SMP0                    ADC_SMPR1_SMP0_Msk                   /*!< ADC Channel 0 Sampling time selection  */

+#define ADC_SMPR1_SMP0_0                  (0x1UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000001 */

+#define ADC_SMPR1_SMP0_1                  (0x2UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000002 */

+#define ADC_SMPR1_SMP0_2                  (0x4UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000004 */

+

+#define ADC_SMPR1_SMP1_Pos                (3U)

+#define ADC_SMPR1_SMP1_Msk                (0x7UL << ADC_SMPR1_SMP1_Pos)        /*!< 0x00000038 */

+#define ADC_SMPR1_SMP1                    ADC_SMPR1_SMP1_Msk                   /*!< ADC Channel 1 Sampling time selection  */

+#define ADC_SMPR1_SMP1_0                  (0x1UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000008 */

+#define ADC_SMPR1_SMP1_1                  (0x2UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000010 */

+#define ADC_SMPR1_SMP1_2                  (0x4UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000020 */

+

+#define ADC_SMPR1_SMP2_Pos                (6U)

+#define ADC_SMPR1_SMP2_Msk                (0x7UL << ADC_SMPR1_SMP2_Pos)        /*!< 0x000001C0 */

+#define ADC_SMPR1_SMP2                    ADC_SMPR1_SMP2_Msk                   /*!< ADC Channel 2 Sampling time selection  */

+#define ADC_SMPR1_SMP2_0                  (0x1UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000040 */

+#define ADC_SMPR1_SMP2_1                  (0x2UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000080 */

+#define ADC_SMPR1_SMP2_2                  (0x4UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000100 */

+

+#define ADC_SMPR1_SMP3_Pos                (9U)

+#define ADC_SMPR1_SMP3_Msk                (0x7UL << ADC_SMPR1_SMP3_Pos)        /*!< 0x00000E00 */

+#define ADC_SMPR1_SMP3                    ADC_SMPR1_SMP3_Msk                   /*!< ADC Channel 3 Sampling time selection  */

+#define ADC_SMPR1_SMP3_0                  (0x1UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000200 */

+#define ADC_SMPR1_SMP3_1                  (0x2UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000400 */

+#define ADC_SMPR1_SMP3_2                  (0x4UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000800 */

+

+#define ADC_SMPR1_SMP4_Pos                (12U)

+#define ADC_SMPR1_SMP4_Msk                (0x7UL << ADC_SMPR1_SMP4_Pos)        /*!< 0x00007000 */

+#define ADC_SMPR1_SMP4                    ADC_SMPR1_SMP4_Msk                   /*!< ADC Channel 4 Sampling time selection  */

+#define ADC_SMPR1_SMP4_0                  (0x1UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00001000 */

+#define ADC_SMPR1_SMP4_1                  (0x2UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00002000 */

+#define ADC_SMPR1_SMP4_2                  (0x4UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00004000 */

+

+#define ADC_SMPR1_SMP5_Pos                (15U)

+#define ADC_SMPR1_SMP5_Msk                (0x7UL << ADC_SMPR1_SMP5_Pos)        /*!< 0x00038000 */

+#define ADC_SMPR1_SMP5                    ADC_SMPR1_SMP5_Msk                   /*!< ADC Channel 5 Sampling time selection  */

+#define ADC_SMPR1_SMP5_0                  (0x1UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00008000 */

+#define ADC_SMPR1_SMP5_1                  (0x2UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00010000 */

+#define ADC_SMPR1_SMP5_2                  (0x4UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00020000 */

+

+#define ADC_SMPR1_SMP6_Pos                (18U)

+#define ADC_SMPR1_SMP6_Msk                (0x7UL << ADC_SMPR1_SMP6_Pos)        /*!< 0x001C0000 */

+#define ADC_SMPR1_SMP6                    ADC_SMPR1_SMP6_Msk                   /*!< ADC Channel 6 Sampling time selection  */

+#define ADC_SMPR1_SMP6_0                  (0x1UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00040000 */

+#define ADC_SMPR1_SMP6_1                  (0x2UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00080000 */

+#define ADC_SMPR1_SMP6_2                  (0x4UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00100000 */

+

+#define ADC_SMPR1_SMP7_Pos                (21U)

+#define ADC_SMPR1_SMP7_Msk                (0x7UL << ADC_SMPR1_SMP7_Pos)        /*!< 0x00E00000 */

+#define ADC_SMPR1_SMP7                    ADC_SMPR1_SMP7_Msk                   /*!< ADC Channel 7 Sampling time selection  */

+#define ADC_SMPR1_SMP7_0                  (0x1UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00200000 */

+#define ADC_SMPR1_SMP7_1                  (0x2UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00400000 */

+#define ADC_SMPR1_SMP7_2                  (0x4UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00800000 */

+

+#define ADC_SMPR1_SMP8_Pos                (24U)

+#define ADC_SMPR1_SMP8_Msk                (0x7UL << ADC_SMPR1_SMP8_Pos)        /*!< 0x07000000 */

+#define ADC_SMPR1_SMP8                    ADC_SMPR1_SMP8_Msk                   /*!< ADC Channel 8 Sampling time selection  */

+#define ADC_SMPR1_SMP8_0                  (0x1UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x01000000 */

+#define ADC_SMPR1_SMP8_1                  (0x2UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x02000000 */

+#define ADC_SMPR1_SMP8_2                  (0x4UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x04000000 */

+

+#define ADC_SMPR1_SMP9_Pos                (27U)

+#define ADC_SMPR1_SMP9_Msk                (0x7UL << ADC_SMPR1_SMP9_Pos)        /*!< 0x38000000 */

+#define ADC_SMPR1_SMP9                    ADC_SMPR1_SMP9_Msk                   /*!< ADC Channel 9 Sampling time selection  */

+#define ADC_SMPR1_SMP9_0                  (0x1UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x08000000 */

+#define ADC_SMPR1_SMP9_1                  (0x2UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x10000000 */

+#define ADC_SMPR1_SMP9_2                  (0x4UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x20000000 */

+

+/********************  Bit definition for ADC_SMPR2 register  ********************/

+#define ADC_SMPR2_SMP10_Pos               (0U)

+#define ADC_SMPR2_SMP10_Msk               (0x7UL << ADC_SMPR2_SMP10_Pos)       /*!< 0x00000007 */

+#define ADC_SMPR2_SMP10                   ADC_SMPR2_SMP10_Msk                  /*!< ADC Channel 10 Sampling time selection  */

+#define ADC_SMPR2_SMP10_0                 (0x1UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000001 */

+#define ADC_SMPR2_SMP10_1                 (0x2UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000002 */

+#define ADC_SMPR2_SMP10_2                 (0x4UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000004 */

+

+#define ADC_SMPR2_SMP11_Pos               (3U)

+#define ADC_SMPR2_SMP11_Msk               (0x7UL << ADC_SMPR2_SMP11_Pos)       /*!< 0x00000038 */

+#define ADC_SMPR2_SMP11                   ADC_SMPR2_SMP11_Msk                  /*!< ADC Channel 11 Sampling time selection  */

+#define ADC_SMPR2_SMP11_0                 (0x1UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000008 */

+#define ADC_SMPR2_SMP11_1                 (0x2UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000010 */

+#define ADC_SMPR2_SMP11_2                 (0x4UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000020 */

+

+#define ADC_SMPR2_SMP12_Pos               (6U)

+#define ADC_SMPR2_SMP12_Msk               (0x7UL << ADC_SMPR2_SMP12_Pos)       /*!< 0x000001C0 */

+#define ADC_SMPR2_SMP12                   ADC_SMPR2_SMP12_Msk                  /*!< ADC Channel 12 Sampling time selection  */

+#define ADC_SMPR2_SMP12_0                 (0x1UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000040 */

+#define ADC_SMPR2_SMP12_1                 (0x2UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000080 */

+#define ADC_SMPR2_SMP12_2                 (0x4UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000100 */

+

+#define ADC_SMPR2_SMP13_Pos               (9U)

+#define ADC_SMPR2_SMP13_Msk               (0x7UL << ADC_SMPR2_SMP13_Pos)       /*!< 0x00000E00 */

+#define ADC_SMPR2_SMP13                   ADC_SMPR2_SMP13_Msk                  /*!< ADC Channel 13 Sampling time selection  */

+#define ADC_SMPR2_SMP13_0                 (0x1UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000200 */

+#define ADC_SMPR2_SMP13_1                 (0x2UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000400 */

+#define ADC_SMPR2_SMP13_2                 (0x4UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000800 */

+

+#define ADC_SMPR2_SMP14_Pos               (12U)

+#define ADC_SMPR2_SMP14_Msk               (0x7UL << ADC_SMPR2_SMP14_Pos)       /*!< 0x00007000 */

+#define ADC_SMPR2_SMP14                   ADC_SMPR2_SMP14_Msk                  /*!< ADC Channel 14 Sampling time selection  */

+#define ADC_SMPR2_SMP14_0                 (0x1UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00001000 */

+#define ADC_SMPR2_SMP14_1                 (0x2UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00002000 */

+#define ADC_SMPR2_SMP14_2                 (0x4UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00004000 */

+

+#define ADC_SMPR2_SMP15_Pos               (15U)

+#define ADC_SMPR2_SMP15_Msk               (0x7UL << ADC_SMPR2_SMP15_Pos)       /*!< 0x00038000 */

+#define ADC_SMPR2_SMP15                   ADC_SMPR2_SMP15_Msk                  /*!< ADC Channel 15 Sampling time selection  */

+#define ADC_SMPR2_SMP15_0                 (0x1UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00008000 */

+#define ADC_SMPR2_SMP15_1                 (0x2UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00010000 */

+#define ADC_SMPR2_SMP15_2                 (0x4UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00020000 */

+

+#define ADC_SMPR2_SMP16_Pos               (18U)

+#define ADC_SMPR2_SMP16_Msk               (0x7UL << ADC_SMPR2_SMP16_Pos)       /*!< 0x001C0000 */

+#define ADC_SMPR2_SMP16                   ADC_SMPR2_SMP16_Msk                  /*!< ADC Channel 16 Sampling time selection  */

+#define ADC_SMPR2_SMP16_0                 (0x1UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00040000 */

+#define ADC_SMPR2_SMP16_1                 (0x2UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00080000 */

+#define ADC_SMPR2_SMP16_2                 (0x4UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00100000 */

+

+#define ADC_SMPR2_SMP17_Pos               (21U)

+#define ADC_SMPR2_SMP17_Msk               (0x7UL << ADC_SMPR2_SMP17_Pos)       /*!< 0x00E00000 */

+#define ADC_SMPR2_SMP17                   ADC_SMPR2_SMP17_Msk                  /*!< ADC Channel 17 Sampling time selection  */

+#define ADC_SMPR2_SMP17_0                 (0x1UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00200000 */

+#define ADC_SMPR2_SMP17_1                 (0x2UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00400000 */

+#define ADC_SMPR2_SMP17_2                 (0x4UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00800000 */

+

+#define ADC_SMPR2_SMP18_Pos               (24U)

+#define ADC_SMPR2_SMP18_Msk               (0x7UL << ADC_SMPR2_SMP18_Pos)       /*!< 0x07000000 */

+#define ADC_SMPR2_SMP18                   ADC_SMPR2_SMP18_Msk                  /*!< ADC Channel 18 Sampling time selection  */

+#define ADC_SMPR2_SMP18_0                 (0x1UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x01000000 */

+#define ADC_SMPR2_SMP18_1                 (0x2UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x02000000 */

+#define ADC_SMPR2_SMP18_2                 (0x4UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x04000000 */

+

+#define ADC_SMPR2_SMP19_Pos               (27U)

+#define ADC_SMPR2_SMP19_Msk               (0x7UL << ADC_SMPR2_SMP19_Pos)       /*!< 0x38000000 */

+#define ADC_SMPR2_SMP19                   ADC_SMPR2_SMP19_Msk                  /*!< ADC Channel 19 Sampling time selection  */

+#define ADC_SMPR2_SMP19_0                 (0x1UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x08000000 */

+#define ADC_SMPR2_SMP19_1                 (0x2UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x10000000 */

+#define ADC_SMPR2_SMP19_2                 (0x4UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x20000000 */

+

+/********************  Bit definition for ADC_PCSEL register  ********************/

+#define ADC_PCSEL_PCSEL_Pos               (0U)

+#define ADC_PCSEL_PCSEL_Msk               (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)   /*!< 0x000FFFFF */

+#define ADC_PCSEL_PCSEL                   ADC_PCSEL_PCSEL_Msk                  /*!< ADC pre channel selection */

+#define ADC_PCSEL_PCSEL_0                 (0x00001UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */

+#define ADC_PCSEL_PCSEL_1                 (0x00002UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */

+#define ADC_PCSEL_PCSEL_2                 (0x00004UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */

+#define ADC_PCSEL_PCSEL_3                 (0x00008UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */

+#define ADC_PCSEL_PCSEL_4                 (0x00010UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */

+#define ADC_PCSEL_PCSEL_5                 (0x00020UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */

+#define ADC_PCSEL_PCSEL_6                 (0x00040UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */

+#define ADC_PCSEL_PCSEL_7                 (0x00080UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */

+#define ADC_PCSEL_PCSEL_8                 (0x00100UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */

+#define ADC_PCSEL_PCSEL_9                 (0x00200UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */

+#define ADC_PCSEL_PCSEL_10                (0x00400UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */

+#define ADC_PCSEL_PCSEL_11                (0x00800UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */

+#define ADC_PCSEL_PCSEL_12                (0x01000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */

+#define ADC_PCSEL_PCSEL_13                (0x02000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */

+#define ADC_PCSEL_PCSEL_14                (0x04000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */

+#define ADC_PCSEL_PCSEL_15                (0x08000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */

+#define ADC_PCSEL_PCSEL_16                (0x10000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */

+#define ADC_PCSEL_PCSEL_17                (0x20000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */

+#define ADC_PCSEL_PCSEL_18                (0x40000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */

+#define ADC_PCSEL_PCSEL_19                (0x80000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00080000 */

+

+/*****************  Bit definition for ADC_LTR1, 2, 3 registers *****************/

+#define ADC_LTR_LT_Pos                    (0U)

+#define ADC_LTR_LT_Msk                    (0x3FFFFFFUL << ADC_LTR_LT_Pos)      /*!< 0x03FFFFFF */

+#define ADC_LTR_LT                        ADC_LTR_LT_Msk                       /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */

+

+/*****************  Bit definition for ADC_HTR1, 2, 3 registers  ****************/

+#define ADC_HTR_HT_Pos                    (0U)

+#define ADC_HTR_HT_Msk                    (0x3FFFFFFUL << ADC_HTR_HT_Pos)      /*!< 0x03FFFFFF */

+#define ADC_HTR_HT                        ADC_HTR_HT_Msk                       /*!< ADC Analog watchdog 1,2 and 3 higher threshold */

+

+

+/********************  Bit definition for ADC_SQR1 register  ********************/

+#define ADC_SQR1_L_Pos                    (0U)

+#define ADC_SQR1_L_Msk                    (0xFUL << ADC_SQR1_L_Pos)            /*!< 0x0000000F */

+#define ADC_SQR1_L                        ADC_SQR1_L_Msk                       /*!< ADC regular channel sequence lenght */

+#define ADC_SQR1_L_0                      (0x1UL << ADC_SQR1_L_Pos)             /*!< 0x00000001 */

+#define ADC_SQR1_L_1                      (0x2UL << ADC_SQR1_L_Pos)             /*!< 0x00000002 */

+#define ADC_SQR1_L_2                      (0x4UL << ADC_SQR1_L_Pos)             /*!< 0x00000004 */

+#define ADC_SQR1_L_3                      (0x8UL << ADC_SQR1_L_Pos)             /*!< 0x00000008 */

+

+#define ADC_SQR1_SQ1_Pos                  (6U)

+#define ADC_SQR1_SQ1_Msk                  (0x1FUL << ADC_SQR1_SQ1_Pos)         /*!< 0x000007C0 */

+#define ADC_SQR1_SQ1                      ADC_SQR1_SQ1_Msk                     /*!< ADC 1st conversion in regular sequence */

+#define ADC_SQR1_SQ1_0                    (0x01UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000040 */

+#define ADC_SQR1_SQ1_1                    (0x02UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000080 */

+#define ADC_SQR1_SQ1_2                    (0x04UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000100 */

+#define ADC_SQR1_SQ1_3                    (0x08UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000200 */

+#define ADC_SQR1_SQ1_4                    (0x10UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000400 */

+

+#define ADC_SQR1_SQ2_Pos                  (12U)

+#define ADC_SQR1_SQ2_Msk                  (0x1FUL << ADC_SQR1_SQ2_Pos)         /*!< 0x0001F000 */

+#define ADC_SQR1_SQ2                      ADC_SQR1_SQ2_Msk                     /*!< ADC 2nd conversion in regular sequence */

+#define ADC_SQR1_SQ2_0                    (0x01UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00001000 */

+#define ADC_SQR1_SQ2_1                    (0x02UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00002000 */

+#define ADC_SQR1_SQ2_2                    (0x04UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00004000 */

+#define ADC_SQR1_SQ2_3                    (0x08UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00008000 */

+#define ADC_SQR1_SQ2_4                    (0x10UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00010000 */

+

+#define ADC_SQR1_SQ3_Pos                  (18U)

+#define ADC_SQR1_SQ3_Msk                  (0x1FUL << ADC_SQR1_SQ3_Pos)         /*!< 0x007C0000 */

+#define ADC_SQR1_SQ3                      ADC_SQR1_SQ3_Msk                     /*!< ADC 3rd conversion in regular sequence */

+#define ADC_SQR1_SQ3_0                    (0x01UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00040000 */

+#define ADC_SQR1_SQ3_1                    (0x02UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00080000 */

+#define ADC_SQR1_SQ3_2                    (0x04UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00100000 */

+#define ADC_SQR1_SQ3_3                    (0x08UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00200000 */

+#define ADC_SQR1_SQ3_4                    (0x10UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00400000 */

+

+#define ADC_SQR1_SQ4_Pos                  (24U)

+#define ADC_SQR1_SQ4_Msk                  (0x1FUL << ADC_SQR1_SQ4_Pos)         /*!< 0x1F000000 */

+#define ADC_SQR1_SQ4                      ADC_SQR1_SQ4_Msk                     /*!< ADC 4th conversion in regular sequence */

+#define ADC_SQR1_SQ4_0                    (0x01UL << ADC_SQR1_SQ4_Pos)          /*!< 0x01000000 */

+#define ADC_SQR1_SQ4_1                    (0x02UL << ADC_SQR1_SQ4_Pos)          /*!< 0x02000000 */

+#define ADC_SQR1_SQ4_2                    (0x04UL << ADC_SQR1_SQ4_Pos)          /*!< 0x04000000 */

+#define ADC_SQR1_SQ4_3                    (0x08UL << ADC_SQR1_SQ4_Pos)          /*!< 0x08000000 */

+#define ADC_SQR1_SQ4_4                    (0x10UL << ADC_SQR1_SQ4_Pos)          /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR2 register  ********************/

+#define ADC_SQR2_SQ5_Pos                  (0U)

+#define ADC_SQR2_SQ5_Msk                  (0x1FUL << ADC_SQR2_SQ5_Pos)         /*!< 0x0000001F */

+#define ADC_SQR2_SQ5                      ADC_SQR2_SQ5_Msk                     /*!< ADC 5th conversion in regular sequence */

+#define ADC_SQR2_SQ5_0                    (0x01UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000001 */

+#define ADC_SQR2_SQ5_1                    (0x02UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000002 */

+#define ADC_SQR2_SQ5_2                    (0x04UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000004 */

+#define ADC_SQR2_SQ5_3                    (0x08UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000008 */

+#define ADC_SQR2_SQ5_4                    (0x10UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000010 */

+

+#define ADC_SQR2_SQ6_Pos                  (6U)

+#define ADC_SQR2_SQ6_Msk                  (0x1FUL << ADC_SQR2_SQ6_Pos)         /*!< 0x000007C0 */

+#define ADC_SQR2_SQ6                      ADC_SQR2_SQ6_Msk                     /*!< ADC 6th conversion in regular sequence */

+#define ADC_SQR2_SQ6_0                    (0x01UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000040 */

+#define ADC_SQR2_SQ6_1                    (0x02UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000080 */

+#define ADC_SQR2_SQ6_2                    (0x04UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000100 */

+#define ADC_SQR2_SQ6_3                    (0x08UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000200 */

+#define ADC_SQR2_SQ6_4                    (0x10UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000400 */

+

+#define ADC_SQR2_SQ7_Pos                  (12U)

+#define ADC_SQR2_SQ7_Msk                  (0x1FUL << ADC_SQR2_SQ7_Pos)         /*!< 0x0001F000 */

+#define ADC_SQR2_SQ7                      ADC_SQR2_SQ7_Msk                     /*!< ADC 7th conversion in regular sequence */

+#define ADC_SQR2_SQ7_0                    (0x01UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00001000 */

+#define ADC_SQR2_SQ7_1                    (0x02UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00002000 */

+#define ADC_SQR2_SQ7_2                    (0x04UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00004000 */

+#define ADC_SQR2_SQ7_3                    (0x08UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00008000 */

+#define ADC_SQR2_SQ7_4                    (0x10UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00010000 */

+

+#define ADC_SQR2_SQ8_Pos                  (18U)

+#define ADC_SQR2_SQ8_Msk                  (0x1FUL << ADC_SQR2_SQ8_Pos)         /*!< 0x007C0000 */

+#define ADC_SQR2_SQ8                      ADC_SQR2_SQ8_Msk                     /*!< ADC 8th conversion in regular sequence */

+#define ADC_SQR2_SQ8_0                    (0x01UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00040000 */

+#define ADC_SQR2_SQ8_1                    (0x02UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00080000 */

+#define ADC_SQR2_SQ8_2                    (0x04UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00100000 */

+#define ADC_SQR2_SQ8_3                    (0x08UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00200000 */

+#define ADC_SQR2_SQ8_4                    (0x10UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00400000 */

+

+#define ADC_SQR2_SQ9_Pos                  (24U)

+#define ADC_SQR2_SQ9_Msk                  (0x1FUL << ADC_SQR2_SQ9_Pos)         /*!< 0x1F000000 */

+#define ADC_SQR2_SQ9                      ADC_SQR2_SQ9_Msk                     /*!< ADC 9th conversion in regular sequence */

+#define ADC_SQR2_SQ9_0                    (0x01UL << ADC_SQR2_SQ9_Pos)          /*!< 0x01000000 */

+#define ADC_SQR2_SQ9_1                    (0x02UL << ADC_SQR2_SQ9_Pos)          /*!< 0x02000000 */

+#define ADC_SQR2_SQ9_2                    (0x04UL << ADC_SQR2_SQ9_Pos)          /*!< 0x04000000 */

+#define ADC_SQR2_SQ9_3                    (0x08UL << ADC_SQR2_SQ9_Pos)          /*!< 0x08000000 */

+#define ADC_SQR2_SQ9_4                    (0x10UL << ADC_SQR2_SQ9_Pos)          /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR3 register  ********************/

+#define ADC_SQR3_SQ10_Pos                 (0U)

+#define ADC_SQR3_SQ10_Msk                 (0x1FUL << ADC_SQR3_SQ10_Pos)        /*!< 0x0000001F */

+#define ADC_SQR3_SQ10                     ADC_SQR3_SQ10_Msk                    /*!< ADC 10th conversion in regular sequence */

+#define ADC_SQR3_SQ10_0                   (0x01UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000001 */

+#define ADC_SQR3_SQ10_1                   (0x02UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000002 */

+#define ADC_SQR3_SQ10_2                   (0x04UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000004 */

+#define ADC_SQR3_SQ10_3                   (0x08UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000008 */

+#define ADC_SQR3_SQ10_4                   (0x10UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000010 */

+

+#define ADC_SQR3_SQ11_Pos                 (6U)

+#define ADC_SQR3_SQ11_Msk                 (0x1FUL << ADC_SQR3_SQ11_Pos)        /*!< 0x000007C0 */

+#define ADC_SQR3_SQ11                     ADC_SQR3_SQ11_Msk                    /*!< ADC 11th conversion in regular sequence */

+#define ADC_SQR3_SQ11_0                   (0x01UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000040 */

+#define ADC_SQR3_SQ11_1                   (0x02UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000080 */

+#define ADC_SQR3_SQ11_2                   (0x04UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000100 */

+#define ADC_SQR3_SQ11_3                   (0x08UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000200 */

+#define ADC_SQR3_SQ11_4                   (0x10UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000400 */

+

+#define ADC_SQR3_SQ12_Pos                 (12U)

+#define ADC_SQR3_SQ12_Msk                 (0x1FUL << ADC_SQR3_SQ12_Pos)        /*!< 0x0001F000 */

+#define ADC_SQR3_SQ12                     ADC_SQR3_SQ12_Msk                    /*!< ADC 12th conversion in regular sequence */

+#define ADC_SQR3_SQ12_0                   (0x01UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00001000 */

+#define ADC_SQR3_SQ12_1                   (0x02UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00002000 */

+#define ADC_SQR3_SQ12_2                   (0x04UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00004000 */

+#define ADC_SQR3_SQ12_3                   (0x08UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00008000 */

+#define ADC_SQR3_SQ12_4                   (0x10UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00010000 */

+

+#define ADC_SQR3_SQ13_Pos                 (18U)

+#define ADC_SQR3_SQ13_Msk                 (0x1FUL << ADC_SQR3_SQ13_Pos)        /*!< 0x007C0000 */

+#define ADC_SQR3_SQ13                     ADC_SQR3_SQ13_Msk                    /*!< ADC 13th conversion in regular sequence */

+#define ADC_SQR3_SQ13_0                   (0x01UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00040000 */

+#define ADC_SQR3_SQ13_1                   (0x02UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00080000 */

+#define ADC_SQR3_SQ13_2                   (0x04UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00100000 */

+#define ADC_SQR3_SQ13_3                   (0x08UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00200000 */

+#define ADC_SQR3_SQ13_4                   (0x10UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00400000 */

+

+#define ADC_SQR3_SQ14_Pos                 (24U)

+#define ADC_SQR3_SQ14_Msk                 (0x1FUL << ADC_SQR3_SQ14_Pos)        /*!< 0x1F000000 */

+#define ADC_SQR3_SQ14                     ADC_SQR3_SQ14_Msk                    /*!< ADC 14th conversion in regular sequence */

+#define ADC_SQR3_SQ14_0                   (0x01UL << ADC_SQR3_SQ14_Pos)         /*!< 0x01000000 */

+#define ADC_SQR3_SQ14_1                   (0x02UL << ADC_SQR3_SQ14_Pos)         /*!< 0x02000000 */

+#define ADC_SQR3_SQ14_2                   (0x04UL << ADC_SQR3_SQ14_Pos)         /*!< 0x04000000 */

+#define ADC_SQR3_SQ14_3                   (0x08UL << ADC_SQR3_SQ14_Pos)         /*!< 0x08000000 */

+#define ADC_SQR3_SQ14_4                   (0x10UL << ADC_SQR3_SQ14_Pos)         /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR4 register  ********************/

+#define ADC_SQR4_SQ15_Pos                 (0U)

+#define ADC_SQR4_SQ15_Msk                 (0x1FUL << ADC_SQR4_SQ15_Pos)        /*!< 0x0000001F */

+#define ADC_SQR4_SQ15                     ADC_SQR4_SQ15_Msk                    /*!< ADC 15th conversion in regular sequence */

+#define ADC_SQR4_SQ15_0                   (0x01UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000001 */

+#define ADC_SQR4_SQ15_1                   (0x02UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000002 */

+#define ADC_SQR4_SQ15_2                   (0x04UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000004 */

+#define ADC_SQR4_SQ15_3                   (0x08UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000008 */

+#define ADC_SQR4_SQ15_4                   (0x10UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000010 */

+

+#define ADC_SQR4_SQ16_Pos                 (6U)

+#define ADC_SQR4_SQ16_Msk                 (0x1FUL << ADC_SQR4_SQ16_Pos)        /*!< 0x000007C0 */

+#define ADC_SQR4_SQ16                     ADC_SQR4_SQ16_Msk                    /*!< ADC 16th conversion in regular sequence */

+#define ADC_SQR4_SQ16_0                   (0x01UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000040 */

+#define ADC_SQR4_SQ16_1                   (0x02UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000080 */

+#define ADC_SQR4_SQ16_2                   (0x04UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000100 */

+#define ADC_SQR4_SQ16_3                   (0x08UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000200 */

+#define ADC_SQR4_SQ16_4                   (0x10UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000400 */

+/********************  Bit definition for ADC_DR register  ********************/

+#define ADC_DR_RDATA_Pos                  (0U)

+#define ADC_DR_RDATA_Msk                  (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)   /*!< 0xFFFFFFFF */

+#define ADC_DR_RDATA                      ADC_DR_RDATA_Msk                     /*!< ADC regular Data converted */

+

+/********************  Bit definition for ADC_JSQR register  ********************/

+#define ADC_JSQR_JL_Pos                   (0U)

+#define ADC_JSQR_JL_Msk                   (0x3UL << ADC_JSQR_JL_Pos)           /*!< 0x00000003 */

+#define ADC_JSQR_JL                       ADC_JSQR_JL_Msk                      /*!< ADC injected channel sequence length */

+#define ADC_JSQR_JL_0                     (0x1UL << ADC_JSQR_JL_Pos)           /*!< 0x00000001 */

+#define ADC_JSQR_JL_1                     (0x2UL << ADC_JSQR_JL_Pos)           /*!< 0x00000002 */

+

+#define ADC_JSQR_JEXTSEL_Pos              (2U)

+#define ADC_JSQR_JEXTSEL_Msk              (0x1FUL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x0000007C */

+#define ADC_JSQR_JEXTSEL                  ADC_JSQR_JEXTSEL_Msk                 /*!< ADC external trigger selection for injected group */

+#define ADC_JSQR_JEXTSEL_0                (0x01UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000004 */

+#define ADC_JSQR_JEXTSEL_1                (0x02UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000008 */

+#define ADC_JSQR_JEXTSEL_2                (0x04UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000010 */

+#define ADC_JSQR_JEXTSEL_3                (0x08UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000020 */

+#define ADC_JSQR_JEXTSEL_4                (0x10UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000040 */

+

+#define ADC_JSQR_JEXTEN_Pos               (7U)

+#define ADC_JSQR_JEXTEN_Msk               (0x3UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000180 */

+#define ADC_JSQR_JEXTEN                   ADC_JSQR_JEXTEN_Msk                  /*!< ADC external trigger enable and polarity selection for injected channels */

+#define ADC_JSQR_JEXTEN_0                 (0x1UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000080 */

+#define ADC_JSQR_JEXTEN_1                 (0x2UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000100 */

+

+#define ADC_JSQR_JSQ1_Pos                 (9U)

+#define ADC_JSQR_JSQ1_Msk                 (0x1FUL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00003E00 */

+#define ADC_JSQR_JSQ1                     ADC_JSQR_JSQ1_Msk                    /*!< ADC 1st conversion in injected sequence */

+#define ADC_JSQR_JSQ1_0                   (0x01UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000200 */

+#define ADC_JSQR_JSQ1_1                   (0x02UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000400 */

+#define ADC_JSQR_JSQ1_2                   (0x04UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000800 */

+#define ADC_JSQR_JSQ1_3                   (0x08UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00001000 */

+#define ADC_JSQR_JSQ1_4                   (0x10UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00002000 */

+

+#define ADC_JSQR_JSQ2_Pos                 (15U)

+#define ADC_JSQR_JSQ2_Msk                 (0x1FUL << ADC_JSQR_JSQ2_Pos)        /*!< 0x000F8000 */

+#define ADC_JSQR_JSQ2                     ADC_JSQR_JSQ2_Msk                    /*!< ADC 2nd conversion in injected sequence */

+#define ADC_JSQR_JSQ2_0                   (0x01UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00008000 */

+#define ADC_JSQR_JSQ2_1                   (0x02UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00010000 */

+#define ADC_JSQR_JSQ2_2                   (0x04UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00020000 */

+#define ADC_JSQR_JSQ2_3                   (0x08UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00040000 */

+#define ADC_JSQR_JSQ2_4                   (0x10UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00080000 */

+

+#define ADC_JSQR_JSQ3_Pos                 (21U)

+#define ADC_JSQR_JSQ3_Msk                 (0x1FUL << ADC_JSQR_JSQ3_Pos)        /*!< 0x03E00000 */

+#define ADC_JSQR_JSQ3                     ADC_JSQR_JSQ3_Msk                    /*!< ADC 3rd conversion in injected sequence */

+#define ADC_JSQR_JSQ3_0                   (0x01UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00200000 */

+#define ADC_JSQR_JSQ3_1                   (0x02UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00400000 */

+#define ADC_JSQR_JSQ3_2                   (0x04UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00800000 */

+#define ADC_JSQR_JSQ3_3                   (0x08UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x01000000 */

+#define ADC_JSQR_JSQ3_4                   (0x10UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x02000000 */

+

+#define ADC_JSQR_JSQ4_Pos                 (27U)

+#define ADC_JSQR_JSQ4_Msk                 (0x1FUL << ADC_JSQR_JSQ4_Pos)        /*!< 0xF8000000 */

+#define ADC_JSQR_JSQ4                     ADC_JSQR_JSQ4_Msk                    /*!< ADC 4th conversion in injected sequence */

+#define ADC_JSQR_JSQ4_0                   (0x01UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x08000000 */

+#define ADC_JSQR_JSQ4_1                   (0x02UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x10000000 */

+#define ADC_JSQR_JSQ4_2                   (0x04UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x20000000 */

+#define ADC_JSQR_JSQ4_3                   (0x08UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x40000000 */

+#define ADC_JSQR_JSQ4_4                   (0x10UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_OFR1 register  ********************/

+#define ADC_OFR1_OFFSET1_Pos              (0U)

+#define ADC_OFR1_OFFSET1_Msk              (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR1_OFFSET1                  ADC_OFR1_OFFSET1_Msk                  /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */

+#define ADC_OFR1_OFFSET1_0                (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */

+#define ADC_OFR1_OFFSET1_1                (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */

+#define ADC_OFR1_OFFSET1_2                (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */

+#define ADC_OFR1_OFFSET1_3                (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */

+#define ADC_OFR1_OFFSET1_4                (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */

+#define ADC_OFR1_OFFSET1_5                (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */

+#define ADC_OFR1_OFFSET1_6                (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */

+#define ADC_OFR1_OFFSET1_7                (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */

+#define ADC_OFR1_OFFSET1_8                (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */

+#define ADC_OFR1_OFFSET1_9                (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */

+#define ADC_OFR1_OFFSET1_10               (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */

+#define ADC_OFR1_OFFSET1_11               (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */

+#define ADC_OFR1_OFFSET1_12               (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */

+#define ADC_OFR1_OFFSET1_13               (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */

+#define ADC_OFR1_OFFSET1_14               (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */

+#define ADC_OFR1_OFFSET1_15               (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */

+#define ADC_OFR1_OFFSET1_16               (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */

+#define ADC_OFR1_OFFSET1_17               (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */

+#define ADC_OFR1_OFFSET1_18               (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */

+#define ADC_OFR1_OFFSET1_19               (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */

+#define ADC_OFR1_OFFSET1_20               (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */

+#define ADC_OFR1_OFFSET1_21               (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */

+#define ADC_OFR1_OFFSET1_22               (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */

+#define ADC_OFR1_OFFSET1_23               (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */

+#define ADC_OFR1_OFFSET1_24               (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */

+#define ADC_OFR1_OFFSET1_25               (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR1_OFFSET1_CH_Pos           (26U)

+#define ADC_OFR1_OFFSET1_CH_Msk           (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR1_OFFSET1_CH               ADC_OFR1_OFFSET1_CH_Msk               /*!< ADC Channel selection for the data offset 1 */

+#define ADC_OFR1_OFFSET1_CH_0             (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR1_OFFSET1_CH_1             (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR1_OFFSET1_CH_2             (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR1_OFFSET1_CH_3             (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR1_OFFSET1_CH_4             (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR1_SSATE_Pos                (31U)

+#define ADC_OFR1_SSATE_Msk                (0x1UL << ADC_OFR1_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR1_SSATE                    ADC_OFR1_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR2 register  ********************/

+#define ADC_OFR2_OFFSET2_Pos              (0U)

+#define ADC_OFR2_OFFSET2_Msk              (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR2_OFFSET2                  ADC_OFR2_OFFSET2_Msk                  /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */

+#define ADC_OFR2_OFFSET2_0                (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */

+#define ADC_OFR2_OFFSET2_1                (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */

+#define ADC_OFR2_OFFSET2_2                (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */

+#define ADC_OFR2_OFFSET2_3                (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */

+#define ADC_OFR2_OFFSET2_4                (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */

+#define ADC_OFR2_OFFSET2_5                (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */

+#define ADC_OFR2_OFFSET2_6                (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */

+#define ADC_OFR2_OFFSET2_7                (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */

+#define ADC_OFR2_OFFSET2_8                (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */

+#define ADC_OFR2_OFFSET2_9                (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */

+#define ADC_OFR2_OFFSET2_10               (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */

+#define ADC_OFR2_OFFSET2_11               (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */

+#define ADC_OFR2_OFFSET2_12               (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */

+#define ADC_OFR2_OFFSET2_13               (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */

+#define ADC_OFR2_OFFSET2_14               (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */

+#define ADC_OFR2_OFFSET2_15               (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */

+#define ADC_OFR2_OFFSET2_16               (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */

+#define ADC_OFR2_OFFSET2_17               (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */

+#define ADC_OFR2_OFFSET2_18               (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */

+#define ADC_OFR2_OFFSET2_19               (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */

+#define ADC_OFR2_OFFSET2_20               (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */

+#define ADC_OFR2_OFFSET2_21               (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */

+#define ADC_OFR2_OFFSET2_22               (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */

+#define ADC_OFR2_OFFSET2_23               (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */

+#define ADC_OFR2_OFFSET2_24               (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */

+#define ADC_OFR2_OFFSET2_25               (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR2_OFFSET2_CH_Pos           (26U)

+#define ADC_OFR2_OFFSET2_CH_Msk           (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR2_OFFSET2_CH               ADC_OFR2_OFFSET2_CH_Msk               /*!< ADC Channel selection for the data offset 2 */

+#define ADC_OFR2_OFFSET2_CH_0             (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR2_OFFSET2_CH_1             (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR2_OFFSET2_CH_2             (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR2_OFFSET2_CH_3             (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR2_OFFSET2_CH_4             (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR2_SSATE_Pos                (31U)

+#define ADC_OFR2_SSATE_Msk                (0x1UL << ADC_OFR2_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR2_SSATE                    ADC_OFR2_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR3 register  ********************/

+#define ADC_OFR3_OFFSET3_Pos              (0U)

+#define ADC_OFR3_OFFSET3_Msk              (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR3_OFFSET3                  ADC_OFR3_OFFSET3_Msk                  /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */

+#define ADC_OFR3_OFFSET3_0                (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */

+#define ADC_OFR3_OFFSET3_1                (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */

+#define ADC_OFR3_OFFSET3_2                (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */

+#define ADC_OFR3_OFFSET3_3                (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */

+#define ADC_OFR3_OFFSET3_4                (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */

+#define ADC_OFR3_OFFSET3_5                (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */

+#define ADC_OFR3_OFFSET3_6                (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */

+#define ADC_OFR3_OFFSET3_7                (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */

+#define ADC_OFR3_OFFSET3_8                (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */

+#define ADC_OFR3_OFFSET3_9                (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */

+#define ADC_OFR3_OFFSET3_10               (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */

+#define ADC_OFR3_OFFSET3_11               (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */

+#define ADC_OFR3_OFFSET3_12               (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */

+#define ADC_OFR3_OFFSET3_13               (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */

+#define ADC_OFR3_OFFSET3_14               (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */

+#define ADC_OFR3_OFFSET3_15               (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */

+#define ADC_OFR3_OFFSET3_16               (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */

+#define ADC_OFR3_OFFSET3_17               (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */

+#define ADC_OFR3_OFFSET3_18               (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */

+#define ADC_OFR3_OFFSET3_19               (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */

+#define ADC_OFR3_OFFSET3_20               (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */

+#define ADC_OFR3_OFFSET3_21               (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */

+#define ADC_OFR3_OFFSET3_22               (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */

+#define ADC_OFR3_OFFSET3_23               (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */

+#define ADC_OFR3_OFFSET3_24               (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */

+#define ADC_OFR3_OFFSET3_25               (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR3_OFFSET3_CH_Pos           (26U)

+#define ADC_OFR3_OFFSET3_CH_Msk           (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR3_OFFSET3_CH               ADC_OFR3_OFFSET3_CH_Msk               /*!< ADC Channel selection for the data offset 3 */

+#define ADC_OFR3_OFFSET3_CH_0             (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR3_OFFSET3_CH_1             (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR3_OFFSET3_CH_2             (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR3_OFFSET3_CH_3             (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR3_OFFSET3_CH_4             (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR3_SSATE_Pos                (31U)

+#define ADC_OFR3_SSATE_Msk                (0x1UL << ADC_OFR3_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR3_SSATE                    ADC_OFR3_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR4 register  ********************/

+#define ADC_OFR4_OFFSET4_Pos              (0U)

+#define ADC_OFR4_OFFSET4_Msk              (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR4_OFFSET4                  ADC_OFR4_OFFSET4_Msk                  /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */

+#define ADC_OFR4_OFFSET4_0                (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */

+#define ADC_OFR4_OFFSET4_1                (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */

+#define ADC_OFR4_OFFSET4_2                (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */

+#define ADC_OFR4_OFFSET4_3                (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */

+#define ADC_OFR4_OFFSET4_4                (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */

+#define ADC_OFR4_OFFSET4_5                (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */

+#define ADC_OFR4_OFFSET4_6                (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */

+#define ADC_OFR4_OFFSET4_7                (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */

+#define ADC_OFR4_OFFSET4_8                (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */

+#define ADC_OFR4_OFFSET4_9                (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */

+#define ADC_OFR4_OFFSET4_10               (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */

+#define ADC_OFR4_OFFSET4_11               (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */

+#define ADC_OFR4_OFFSET4_12               (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */

+#define ADC_OFR4_OFFSET4_13               (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */

+#define ADC_OFR4_OFFSET4_14               (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */

+#define ADC_OFR4_OFFSET4_15               (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */

+#define ADC_OFR4_OFFSET4_16               (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */

+#define ADC_OFR4_OFFSET4_17               (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */

+#define ADC_OFR4_OFFSET4_18               (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */

+#define ADC_OFR4_OFFSET4_19               (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */

+#define ADC_OFR4_OFFSET4_20               (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */

+#define ADC_OFR4_OFFSET4_21               (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */

+#define ADC_OFR4_OFFSET4_22               (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */

+#define ADC_OFR4_OFFSET4_23               (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */

+#define ADC_OFR4_OFFSET4_24               (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */

+#define ADC_OFR4_OFFSET4_25               (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR4_OFFSET4_CH_Pos           (26U)

+#define ADC_OFR4_OFFSET4_CH_Msk           (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR4_OFFSET4_CH               ADC_OFR4_OFFSET4_CH_Msk               /*!< ADC Channel selection for the data offset 4 */

+#define ADC_OFR4_OFFSET4_CH_0             (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR4_OFFSET4_CH_1             (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR4_OFFSET4_CH_2             (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR4_OFFSET4_CH_3             (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR4_OFFSET4_CH_4             (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR4_SSATE_Pos                (31U)

+#define ADC_OFR4_SSATE_Msk                (0x1UL << ADC_OFR4_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR4_SSATE                    ADC_OFR4_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_JDR1 register  ********************/

+#define ADC_JDR1_JDATA_Pos                (0U)

+#define ADC_JDR1_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR1_JDATA                    ADC_JDR1_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR1_JDATA_0                  (0x00000001UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR1_JDATA_1                  (0x00000002UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR1_JDATA_2                  (0x00000004UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR1_JDATA_3                  (0x00000008UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR1_JDATA_4                  (0x00000010UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR1_JDATA_5                  (0x00000020UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR1_JDATA_6                  (0x00000040UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR1_JDATA_7                  (0x00000080UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR1_JDATA_8                  (0x00000100UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR1_JDATA_9                  (0x00000200UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR1_JDATA_10                 (0x00000400UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR1_JDATA_11                 (0x00000800UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR1_JDATA_12                 (0x00001000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR1_JDATA_13                 (0x00002000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR1_JDATA_14                 (0x00004000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR1_JDATA_15                 (0x00008000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR1_JDATA_16                 (0x00010000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR1_JDATA_17                 (0x00020000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR1_JDATA_18                 (0x00040000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR1_JDATA_19                 (0x00080000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR1_JDATA_20                 (0x00100000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR1_JDATA_21                 (0x00200000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR1_JDATA_22                 (0x00400000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR1_JDATA_23                 (0x00800000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR1_JDATA_24                 (0x01000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR1_JDATA_25                 (0x02000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR1_JDATA_26                 (0x04000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR1_JDATA_27                 (0x08000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR1_JDATA_28                 (0x10000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR1_JDATA_29                 (0x20000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR1_JDATA_30                 (0x40000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR1_JDATA_31                 (0x80000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR2 register  ********************/

+#define ADC_JDR2_JDATA_Pos                (0U)

+#define ADC_JDR2_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR2_JDATA                    ADC_JDR2_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR2_JDATA_0                  (0x00000001UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR2_JDATA_1                  (0x00000002UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR2_JDATA_2                  (0x00000004UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR2_JDATA_3                  (0x00000008UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR2_JDATA_4                  (0x00000010UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR2_JDATA_5                  (0x00000020UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR2_JDATA_6                  (0x00000040UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR2_JDATA_7                  (0x00000080UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR2_JDATA_8                  (0x00000100UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR2_JDATA_9                  (0x00000200UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR2_JDATA_10                 (0x00000400UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR2_JDATA_11                 (0x00000800UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR2_JDATA_12                 (0x00001000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR2_JDATA_13                 (0x00002000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR2_JDATA_14                 (0x00004000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR2_JDATA_15                 (0x00008000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR2_JDATA_16                 (0x00010000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR2_JDATA_17                 (0x00020000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR2_JDATA_18                 (0x00040000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR2_JDATA_19                 (0x00080000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR2_JDATA_20                 (0x00100000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR2_JDATA_21                 (0x00200000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR2_JDATA_22                 (0x00400000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR2_JDATA_23                 (0x00800000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR2_JDATA_24                 (0x01000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR2_JDATA_25                 (0x02000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR2_JDATA_26                 (0x04000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR2_JDATA_27                 (0x08000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR2_JDATA_28                 (0x10000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR2_JDATA_29                 (0x20000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR2_JDATA_30                 (0x40000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR2_JDATA_31                 (0x80000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR3 register  ********************/

+#define ADC_JDR3_JDATA_Pos                (0U)

+#define ADC_JDR3_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR3_JDATA                    ADC_JDR3_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR3_JDATA_0                  (0x00000001UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR3_JDATA_1                  (0x00000002UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR3_JDATA_2                  (0x00000004UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR3_JDATA_3                  (0x00000008UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR3_JDATA_4                  (0x00000010UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR3_JDATA_5                  (0x00000020UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR3_JDATA_6                  (0x00000040UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR3_JDATA_7                  (0x00000080UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR3_JDATA_8                  (0x00000100UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR3_JDATA_9                  (0x00000200UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR3_JDATA_10                 (0x00000400UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR3_JDATA_11                 (0x00000800UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR3_JDATA_12                 (0x00001000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR3_JDATA_13                 (0x00002000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR3_JDATA_14                 (0x00004000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR3_JDATA_15                 (0x00008000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR3_JDATA_16                 (0x00010000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR3_JDATA_17                 (0x00020000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR3_JDATA_18                 (0x00040000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR3_JDATA_19                 (0x00080000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR3_JDATA_20                 (0x00100000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR3_JDATA_21                 (0x00200000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR3_JDATA_22                 (0x00400000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR3_JDATA_23                 (0x00800000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR3_JDATA_24                 (0x01000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR3_JDATA_25                 (0x02000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR3_JDATA_26                 (0x04000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR3_JDATA_27                 (0x08000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR3_JDATA_28                 (0x10000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR3_JDATA_29                 (0x20000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR3_JDATA_30                 (0x40000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR3_JDATA_31                 (0x80000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR4 register  ********************/

+#define ADC_JDR4_JDATA_Pos                (0U)

+#define ADC_JDR4_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR4_JDATA                    ADC_JDR4_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR4_JDATA_0                  (0x00000001UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR4_JDATA_1                  (0x00000002UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR4_JDATA_2                  (0x00000004UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR4_JDATA_3                  (0x00000008UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR4_JDATA_4                  (0x00000010UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR4_JDATA_5                  (0x00000020UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR4_JDATA_6                  (0x00000040UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR4_JDATA_7                  (0x00000080UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR4_JDATA_8                  (0x00000100UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR4_JDATA_9                  (0x00000200UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR4_JDATA_10                 (0x00000400UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR4_JDATA_11                 (0x00000800UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR4_JDATA_12                 (0x00001000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR4_JDATA_13                 (0x00002000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR4_JDATA_14                 (0x00004000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR4_JDATA_15                 (0x00008000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR4_JDATA_16                 (0x00010000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR4_JDATA_17                 (0x00020000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR4_JDATA_18                 (0x00040000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR4_JDATA_19                 (0x00080000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR4_JDATA_20                 (0x00100000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR4_JDATA_21                 (0x00200000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR4_JDATA_22                 (0x00400000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR4_JDATA_23                 (0x00800000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR4_JDATA_24                 (0x01000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR4_JDATA_25                 (0x02000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR4_JDATA_26                 (0x04000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR4_JDATA_27                 (0x08000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR4_JDATA_28                 (0x10000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR4_JDATA_29                 (0x20000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR4_JDATA_30                 (0x40000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR4_JDATA_31                 (0x80000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_AWD2CR register  ********************/

+#define ADC_AWD2CR_AWD2CH_Pos             (0U)

+#define ADC_AWD2CR_AWD2CH_Msk             (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x000FFFFF */

+#define ADC_AWD2CR_AWD2CH                 ADC_AWD2CR_AWD2CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */

+#define ADC_AWD2CR_AWD2CH_0               (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000001 */

+#define ADC_AWD2CR_AWD2CH_1               (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000002 */

+#define ADC_AWD2CR_AWD2CH_2               (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000004 */

+#define ADC_AWD2CR_AWD2CH_3               (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000008 */

+#define ADC_AWD2CR_AWD2CH_4               (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000010 */

+#define ADC_AWD2CR_AWD2CH_5               (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000020 */

+#define ADC_AWD2CR_AWD2CH_6               (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000040 */

+#define ADC_AWD2CR_AWD2CH_7               (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000080 */

+#define ADC_AWD2CR_AWD2CH_8               (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000100 */

+#define ADC_AWD2CR_AWD2CH_9               (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000200 */

+#define ADC_AWD2CR_AWD2CH_10              (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000400 */

+#define ADC_AWD2CR_AWD2CH_11              (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000800 */

+#define ADC_AWD2CR_AWD2CH_12              (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00001000 */

+#define ADC_AWD2CR_AWD2CH_13              (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00002000 */

+#define ADC_AWD2CR_AWD2CH_14              (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00004000 */

+#define ADC_AWD2CR_AWD2CH_15              (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00008000 */

+#define ADC_AWD2CR_AWD2CH_16              (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00010000 */

+#define ADC_AWD2CR_AWD2CH_17              (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00020000 */

+#define ADC_AWD2CR_AWD2CH_18              (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */

+#define ADC_AWD2CR_AWD2CH_19              (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_AWD3CR register  ********************/

+#define ADC_AWD3CR_AWD3CH_Pos             (0U)

+#define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x000FFFFF */

+#define ADC_AWD3CR_AWD3CH                 ADC_AWD3CR_AWD3CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */

+#define ADC_AWD3CR_AWD3CH_0               (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000001 */

+#define ADC_AWD3CR_AWD3CH_1               (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000002 */

+#define ADC_AWD3CR_AWD3CH_2               (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000004 */

+#define ADC_AWD3CR_AWD3CH_3               (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000008 */

+#define ADC_AWD3CR_AWD3CH_4               (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000010 */

+#define ADC_AWD3CR_AWD3CH_5               (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000020 */

+#define ADC_AWD3CR_AWD3CH_6               (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000040 */

+#define ADC_AWD3CR_AWD3CH_7               (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000080 */

+#define ADC_AWD3CR_AWD3CH_8               (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000100 */

+#define ADC_AWD3CR_AWD3CH_9               (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000200 */

+#define ADC_AWD3CR_AWD3CH_10              (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000400 */

+#define ADC_AWD3CR_AWD3CH_11              (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000800 */

+#define ADC_AWD3CR_AWD3CH_12              (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00001000 */

+#define ADC_AWD3CR_AWD3CH_13              (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00002000 */

+#define ADC_AWD3CR_AWD3CH_14              (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00004000 */

+#define ADC_AWD3CR_AWD3CH_15              (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00008000 */

+#define ADC_AWD3CR_AWD3CH_16              (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00010000 */

+#define ADC_AWD3CR_AWD3CH_17              (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00020000 */

+#define ADC_AWD3CR_AWD3CH_18              (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */

+#define ADC_AWD3CR_AWD3CH_19              (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_DIFSEL register  ********************/

+#define ADC_DIFSEL_DIFSEL_Pos             (0U)

+#define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */

+#define ADC_DIFSEL_DIFSEL                 ADC_DIFSEL_DIFSEL_Msk                 /*!< ADC differential modes for channels 1 to 18 */

+#define ADC_DIFSEL_DIFSEL_0               (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000001 */

+#define ADC_DIFSEL_DIFSEL_1               (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000002 */

+#define ADC_DIFSEL_DIFSEL_2               (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000004 */

+#define ADC_DIFSEL_DIFSEL_3               (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000008 */

+#define ADC_DIFSEL_DIFSEL_4               (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000010 */

+#define ADC_DIFSEL_DIFSEL_5               (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000020 */

+#define ADC_DIFSEL_DIFSEL_6               (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000040 */

+#define ADC_DIFSEL_DIFSEL_7               (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000080 */

+#define ADC_DIFSEL_DIFSEL_8               (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000100 */

+#define ADC_DIFSEL_DIFSEL_9               (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000200 */

+#define ADC_DIFSEL_DIFSEL_10              (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000400 */

+#define ADC_DIFSEL_DIFSEL_11              (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000800 */

+#define ADC_DIFSEL_DIFSEL_12              (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00001000 */

+#define ADC_DIFSEL_DIFSEL_13              (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00002000 */

+#define ADC_DIFSEL_DIFSEL_14              (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00004000 */

+#define ADC_DIFSEL_DIFSEL_15              (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00008000 */

+#define ADC_DIFSEL_DIFSEL_16              (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00010000 */

+#define ADC_DIFSEL_DIFSEL_17              (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00020000 */

+#define ADC_DIFSEL_DIFSEL_18              (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00040000 */

+#define ADC_DIFSEL_DIFSEL_19              (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_CALFACT register  ********************/

+#define ADC_CALFACT_CALFACT_S_Pos         (0U)

+#define ADC_CALFACT_CALFACT_S_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */

+#define ADC_CALFACT_CALFACT_S             ADC_CALFACT_CALFACT_S_Msk              /*!< ADC calibration factors in single-ended mode */

+#define ADC_CALFACT_CALFACT_S_0           (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */

+#define ADC_CALFACT_CALFACT_S_1           (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */

+#define ADC_CALFACT_CALFACT_S_2           (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */

+#define ADC_CALFACT_CALFACT_S_3           (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */

+#define ADC_CALFACT_CALFACT_S_4           (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */

+#define ADC_CALFACT_CALFACT_S_5           (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */

+#define ADC_CALFACT_CALFACT_S_6           (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */

+#define ADC_CALFACT_CALFACT_S_7           (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */

+#define ADC_CALFACT_CALFACT_S_8           (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */

+#define ADC_CALFACT_CALFACT_S_9           (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */

+#define ADC_CALFACT_CALFACT_S_10          (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */

+#define ADC_CALFACT_CALFACT_D_Pos         (16U)

+#define ADC_CALFACT_CALFACT_D_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */

+#define ADC_CALFACT_CALFACT_D             ADC_CALFACT_CALFACT_D_Msk              /*!< ADC calibration factors in differential mode */

+#define ADC_CALFACT_CALFACT_D_0           (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */

+#define ADC_CALFACT_CALFACT_D_1           (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */

+#define ADC_CALFACT_CALFACT_D_2           (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */

+#define ADC_CALFACT_CALFACT_D_3           (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */

+#define ADC_CALFACT_CALFACT_D_4           (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */

+#define ADC_CALFACT_CALFACT_D_5           (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */

+#define ADC_CALFACT_CALFACT_D_6           (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */

+#define ADC_CALFACT_CALFACT_D_7           (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */

+#define ADC_CALFACT_CALFACT_D_8           (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */

+#define ADC_CALFACT_CALFACT_D_9           (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */

+#define ADC_CALFACT_CALFACT_D_10          (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */

+

+/********************  Bit definition for ADC_CALFACT2 register  ********************/

+#define ADC_CALFACT2_LINCALFACT_Pos       (0U)

+#define ADC_CALFACT2_LINCALFACT_Msk       (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */

+#define ADC_CALFACT2_LINCALFACT           ADC_CALFACT2_LINCALFACT_Msk                   /*!< ADC Linearity calibration factors */

+#define ADC_CALFACT2_LINCALFACT_0         (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */

+#define ADC_CALFACT2_LINCALFACT_1         (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */

+#define ADC_CALFACT2_LINCALFACT_2         (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */

+#define ADC_CALFACT2_LINCALFACT_3         (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */

+#define ADC_CALFACT2_LINCALFACT_4         (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */

+#define ADC_CALFACT2_LINCALFACT_5         (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */

+#define ADC_CALFACT2_LINCALFACT_6         (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */

+#define ADC_CALFACT2_LINCALFACT_7         (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */

+#define ADC_CALFACT2_LINCALFACT_8         (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */

+#define ADC_CALFACT2_LINCALFACT_9         (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */

+#define ADC_CALFACT2_LINCALFACT_10        (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */

+#define ADC_CALFACT2_LINCALFACT_11        (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */

+#define ADC_CALFACT2_LINCALFACT_12        (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */

+#define ADC_CALFACT2_LINCALFACT_13        (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */

+#define ADC_CALFACT2_LINCALFACT_14        (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */

+#define ADC_CALFACT2_LINCALFACT_15        (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */

+#define ADC_CALFACT2_LINCALFACT_16        (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */

+#define ADC_CALFACT2_LINCALFACT_17        (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */

+#define ADC_CALFACT2_LINCALFACT_18        (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */

+#define ADC_CALFACT2_LINCALFACT_19        (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */

+#define ADC_CALFACT2_LINCALFACT_20        (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */

+#define ADC_CALFACT2_LINCALFACT_21        (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */

+#define ADC_CALFACT2_LINCALFACT_22        (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */

+#define ADC_CALFACT2_LINCALFACT_23        (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */

+#define ADC_CALFACT2_LINCALFACT_24        (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */

+#define ADC_CALFACT2_LINCALFACT_25        (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */

+#define ADC_CALFACT2_LINCALFACT_26        (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */

+#define ADC_CALFACT2_LINCALFACT_27        (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */

+#define ADC_CALFACT2_LINCALFACT_28        (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */

+#define ADC_CALFACT2_LINCALFACT_29        (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */

+

+/*************************  ADC Common registers  *****************************/

+/********************  Bit definition for ADC_CSR register  ********************/

+#define ADC_CSR_ADRDY_MST_Pos             (0U)

+#define ADC_CSR_ADRDY_MST_Msk             (0x1UL << ADC_CSR_ADRDY_MST_Pos)     /*!< 0x00000001 */

+#define ADC_CSR_ADRDY_MST                 ADC_CSR_ADRDY_MST_Msk                /*!< Master ADC ready */

+#define ADC_CSR_EOSMP_MST_Pos             (1U)

+#define ADC_CSR_EOSMP_MST_Msk             (0x1UL << ADC_CSR_EOSMP_MST_Pos)     /*!< 0x00000002 */

+#define ADC_CSR_EOSMP_MST                 ADC_CSR_EOSMP_MST_Msk                /*!< End of sampling phase flag of the master ADC */

+#define ADC_CSR_EOC_MST_Pos               (2U)

+#define ADC_CSR_EOC_MST_Msk               (0x1UL << ADC_CSR_EOC_MST_Pos)       /*!< 0x00000004 */

+#define ADC_CSR_EOC_MST                   ADC_CSR_EOC_MST_Msk                  /*!< End of regular conversion of the master ADC */

+#define ADC_CSR_EOS_MST_Pos               (3U)

+#define ADC_CSR_EOS_MST_Msk               (0x1UL << ADC_CSR_EOS_MST_Pos)       /*!< 0x00000008 */

+#define ADC_CSR_EOS_MST                   ADC_CSR_EOS_MST_Msk                  /*!< End of regular sequence flag of the master ADC */

+#define ADC_CSR_OVR_MST_Pos               (4U)

+#define ADC_CSR_OVR_MST_Msk               (0x1UL << ADC_CSR_OVR_MST_Pos)       /*!< 0x00000010 */

+#define ADC_CSR_OVR_MST                   ADC_CSR_OVR_MST_Msk                  /*!< Overrun flag of the master ADC */

+#define ADC_CSR_JEOC_MST_Pos              (5U)

+#define ADC_CSR_JEOC_MST_Msk              (0x1UL << ADC_CSR_JEOC_MST_Pos)      /*!< 0x00000020 */

+#define ADC_CSR_JEOC_MST                  ADC_CSR_JEOC_MST_Msk                 /*!< End of injected conversion of the master ADC */

+#define ADC_CSR_JEOS_MST_Pos              (6U)

+#define ADC_CSR_JEOS_MST_Msk              (0x1UL << ADC_CSR_JEOS_MST_Pos)      /*!< 0x00000040 */

+#define ADC_CSR_JEOS_MST                  ADC_CSR_JEOS_MST_Msk                 /*!< End of injected sequence flag of the master ADC */

+#define ADC_CSR_AWD1_MST_Pos              (7U)

+#define ADC_CSR_AWD1_MST_Msk              (0x1UL << ADC_CSR_AWD1_MST_Pos)      /*!< 0x00000080 */

+#define ADC_CSR_AWD1_MST                  ADC_CSR_AWD1_MST_Msk                 /*!< Analog watchdog 1 flag of the master ADC */

+#define ADC_CSR_AWD2_MST_Pos              (8U)

+#define ADC_CSR_AWD2_MST_Msk              (0x1UL << ADC_CSR_AWD2_MST_Pos)      /*!< 0x00000100 */

+#define ADC_CSR_AWD2_MST                  ADC_CSR_AWD2_MST_Msk                 /*!< Analog watchdog 2 flag of the master ADC */

+#define ADC_CSR_AWD3_MST_Pos              (9U)

+#define ADC_CSR_AWD3_MST_Msk              (0x1UL << ADC_CSR_AWD3_MST_Pos)      /*!< 0x00000200 */

+#define ADC_CSR_AWD3_MST                  ADC_CSR_AWD3_MST_Msk                 /*!< Analog watchdog 3 flag of the master ADC */

+#define ADC_CSR_JQOVF_MST_Pos             (10U)

+#define ADC_CSR_JQOVF_MST_Msk             (0x1UL << ADC_CSR_JQOVF_MST_Pos)     /*!< 0x00000400 */

+#define ADC_CSR_JQOVF_MST                 ADC_CSR_JQOVF_MST_Msk                /*!< Injected context queue overflow flag of the master ADC */

+#define ADC_CSR_ADRDY_SLV_Pos             (16U)

+#define ADC_CSR_ADRDY_SLV_Msk             (0x1UL << ADC_CSR_ADRDY_SLV_Pos)     /*!< 0x00010000 */

+#define ADC_CSR_ADRDY_SLV                 ADC_CSR_ADRDY_SLV_Msk                /*!< Slave ADC ready */

+#define ADC_CSR_EOSMP_SLV_Pos             (17U)

+#define ADC_CSR_EOSMP_SLV_Msk             (0x1UL << ADC_CSR_EOSMP_SLV_Pos)     /*!< 0x00020000 */

+#define ADC_CSR_EOSMP_SLV                 ADC_CSR_EOSMP_SLV_Msk                /*!< End of sampling phase flag of the slave ADC */

+#define ADC_CSR_EOC_SLV_Pos               (18U)

+#define ADC_CSR_EOC_SLV_Msk               (0x1UL << ADC_CSR_EOC_SLV_Pos)       /*!< 0x00040000 */

+#define ADC_CSR_EOC_SLV                   ADC_CSR_EOC_SLV_Msk                  /*!< End of regular conversion of the slave ADC */

+#define ADC_CSR_EOS_SLV_Pos               (19U)

+#define ADC_CSR_EOS_SLV_Msk               (0x1UL << ADC_CSR_EOS_SLV_Pos)       /*!< 0x00080000 */

+#define ADC_CSR_EOS_SLV                   ADC_CSR_EOS_SLV_Msk                  /*!< End of regular sequence flag of the slave ADC */

+#define ADC_CSR_OVR_SLV_Pos               (20U)

+#define ADC_CSR_OVR_SLV_Msk               (0x1UL << ADC_CSR_OVR_SLV_Pos)       /*!< 0x00100000 */

+#define ADC_CSR_OVR_SLV                   ADC_CSR_OVR_SLV_Msk                  /*!< Overrun flag of the slave ADC */

+#define ADC_CSR_JEOC_SLV_Pos              (21U)

+#define ADC_CSR_JEOC_SLV_Msk              (0x1UL << ADC_CSR_JEOC_SLV_Pos)      /*!< 0x00200000 */

+#define ADC_CSR_JEOC_SLV                  ADC_CSR_JEOC_SLV_Msk                 /*!< End of injected conversion of the slave ADC */

+#define ADC_CSR_JEOS_SLV_Pos              (22U)

+#define ADC_CSR_JEOS_SLV_Msk              (0x1UL << ADC_CSR_JEOS_SLV_Pos)      /*!< 0x00400000 */

+#define ADC_CSR_JEOS_SLV                  ADC_CSR_JEOS_SLV_Msk                 /*!< End of injected sequence flag of the slave ADC */

+#define ADC_CSR_AWD1_SLV_Pos              (23U)

+#define ADC_CSR_AWD1_SLV_Msk              (0x1UL << ADC_CSR_AWD1_SLV_Pos)      /*!< 0x00800000 */

+#define ADC_CSR_AWD1_SLV                  ADC_CSR_AWD1_SLV_Msk                 /*!< Analog watchdog 1 flag of the slave ADC */

+#define ADC_CSR_AWD2_SLV_Pos              (24U)

+#define ADC_CSR_AWD2_SLV_Msk              (0x1UL << ADC_CSR_AWD2_SLV_Pos)      /*!< 0x01000000 */

+#define ADC_CSR_AWD2_SLV                  ADC_CSR_AWD2_SLV_Msk                 /*!< Analog watchdog 2 flag of the slave ADC */

+#define ADC_CSR_AWD3_SLV_Pos              (25U)

+#define ADC_CSR_AWD3_SLV_Msk              (0x1UL << ADC_CSR_AWD3_SLV_Pos)      /*!< 0x02000000 */

+#define ADC_CSR_AWD3_SLV                  ADC_CSR_AWD3_SLV_Msk                 /*!< Analog watchdog 3 flag of the slave ADC */

+#define ADC_CSR_JQOVF_SLV_Pos             (26U)

+#define ADC_CSR_JQOVF_SLV_Msk             (0x1UL << ADC_CSR_JQOVF_SLV_Pos)     /*!< 0x04000000 */

+#define ADC_CSR_JQOVF_SLV                 ADC_CSR_JQOVF_SLV_Msk                /*!< Injected context queue overflow flag of the slave ADC */

+

+/********************  Bit definition for ADC_CCR register  ********************/

+#define ADC_CCR_DUAL_Pos                  (0U)

+#define ADC_CCR_DUAL_Msk                  (0x1FUL << ADC_CCR_DUAL_Pos)          /*!< 0x0000001F */

+#define ADC_CCR_DUAL                      ADC_CCR_DUAL_Msk                      /*!< Dual ADC mode selection */

+#define ADC_CCR_DUAL_0                    (0x01UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000001 */

+#define ADC_CCR_DUAL_1                    (0x02UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000002 */

+#define ADC_CCR_DUAL_2                    (0x04UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000004 */

+#define ADC_CCR_DUAL_3                    (0x08UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000008 */

+#define ADC_CCR_DUAL_4                    (0x10UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000010 */

+

+#define ADC_CCR_DELAY_Pos                 (8U)

+#define ADC_CCR_DELAY_Msk                 (0xFUL << ADC_CCR_DELAY_Pos)          /*!< 0x00000F00 */

+#define ADC_CCR_DELAY                     ADC_CCR_DELAY_Msk                     /*!< Delay between 2 sampling phases */

+#define ADC_CCR_DELAY_0                   (0x1UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000100 */

+#define ADC_CCR_DELAY_1                   (0x2UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000200 */

+#define ADC_CCR_DELAY_2                   (0x4UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000400 */

+#define ADC_CCR_DELAY_3                   (0x8UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000800 */

+

+

+#define ADC_CCR_DAMDF_Pos                 (14U)

+#define ADC_CCR_DAMDF_Msk                 (0x3UL << ADC_CCR_DAMDF_Pos)          /*!< 0x0000C000 */

+#define ADC_CCR_DAMDF                     ADC_CCR_DAMDF_Msk                     /*!< Dual ADC mode Data format */

+#define ADC_CCR_DAMDF_0                   (0x1UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00004000 */

+#define ADC_CCR_DAMDF_1                   (0x2UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00008000 */

+

+#define ADC_CCR_CKMODE_Pos                (16U)

+#define ADC_CCR_CKMODE_Msk                (0x3UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00030000 */

+#define ADC_CCR_CKMODE                    ADC_CCR_CKMODE_Msk                    /*!< ADC clock mode */

+#define ADC_CCR_CKMODE_0                  (0x1UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00010000 */

+#define ADC_CCR_CKMODE_1                  (0x2UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00020000 */

+

+#define ADC_CCR_PRESC_Pos                 (18U)

+#define ADC_CCR_PRESC_Msk                 (0xFUL << ADC_CCR_PRESC_Pos)          /*!< 0x003C0000 */

+#define ADC_CCR_PRESC                     ADC_CCR_PRESC_Msk                     /*!< ADC prescaler */

+#define ADC_CCR_PRESC_0                   (0x1UL << ADC_CCR_PRESC_Pos)          /*!< 0x00040000 */

+#define ADC_CCR_PRESC_1                   (0x2UL << ADC_CCR_PRESC_Pos)          /*!< 0x00080000 */

+#define ADC_CCR_PRESC_2                   (0x4UL << ADC_CCR_PRESC_Pos)          /*!< 0x00100000 */

+#define ADC_CCR_PRESC_3                   (0x8UL << ADC_CCR_PRESC_Pos)          /*!< 0x00200000 */

+

+#define ADC_CCR_VREFEN_Pos                (22U)

+#define ADC_CCR_VREFEN_Msk                (0x1UL << ADC_CCR_VREFEN_Pos)         /*!< 0x00400000 */

+#define ADC_CCR_VREFEN                    ADC_CCR_VREFEN_Msk                    /*!< VREFINT enable */

+#define ADC_CCR_TSEN_Pos                  (23U)

+#define ADC_CCR_TSEN_Msk                  (0x1UL << ADC_CCR_TSEN_Pos)           /*!< 0x00800000 */

+#define ADC_CCR_TSEN                      ADC_CCR_TSEN_Msk                      /*!< Temperature sensor enable */

+#define ADC_CCR_VBATEN_Pos                (24U)

+#define ADC_CCR_VBATEN_Msk                (0x1UL << ADC_CCR_VBATEN_Pos)         /*!< 0x01000000 */

+#define ADC_CCR_VBATEN                    ADC_CCR_VBATEN_Msk                    /*!< VBAT enable */

+

+/********************  Bit definition for ADC_CDR register  *******************/

+#define ADC_CDR_RDATA_MST_Pos             (0U)

+#define ADC_CDR_RDATA_MST_Msk             (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)   /*!< 0x0000FFFF */

+#define ADC_CDR_RDATA_MST                 ADC_CDR_RDATA_MST_Msk                 /*!< ADC multimode master group regular conversion data */

+

+#define ADC_CDR_RDATA_SLV_Pos             (16U)

+#define ADC_CDR_RDATA_SLV_Msk             (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)   /*!< 0xFFFF0000 */

+#define ADC_CDR_RDATA_SLV                 ADC_CDR_RDATA_SLV_Msk                 /*!< ADC multimode slave group regular conversion data */

+

+/********************  Bit definition for ADC_CDR2 register  ******************/

+#define ADC_CDR2_RDATA_ALT_Pos            (0U)

+#define ADC_CDR2_RDATA_ALT_Msk            (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */

+#define ADC_CDR2_RDATA_ALT                ADC_CDR2_RDATA_ALT_Msk                   /*!< Regular data of the master/slave alternated ADCs */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                   VREFBUF                                  */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for VREFBUF_CSR register  ****************/

+#define VREFBUF_CSR_ENVR_Pos        (0U)

+#define VREFBUF_CSR_ENVR_Msk        (0x1UL << VREFBUF_CSR_ENVR_Pos)            /*!< 0x00000001 */

+#define VREFBUF_CSR_ENVR            VREFBUF_CSR_ENVR_Msk                       /*!<Voltage reference buffer enable */

+#define VREFBUF_CSR_HIZ_Pos         (1U)

+#define VREFBUF_CSR_HIZ_Msk         (0x1UL << VREFBUF_CSR_HIZ_Pos)             /*!< 0x00000002 */

+#define VREFBUF_CSR_HIZ             VREFBUF_CSR_HIZ_Msk                        /*!<High impedance mode             */

+#define VREFBUF_CSR_VRR_Pos         (3U)

+#define VREFBUF_CSR_VRR_Msk         (0x1UL << VREFBUF_CSR_VRR_Pos)             /*!< 0x00000008 */

+#define VREFBUF_CSR_VRR             VREFBUF_CSR_VRR_Msk                        /*!<Voltage reference buffer ready  */

+#define VREFBUF_CSR_VRS_Pos         (4U)

+#define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */

+#define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */

+

+#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */

+#define VREFBUF_CSR_VRS_OUT2_Pos    (4U)

+#define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */

+#define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */

+#define VREFBUF_CSR_VRS_OUT3_Pos    (5U)

+#define VREFBUF_CSR_VRS_OUT3_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)        /*!< 0x00000020 */

+#define VREFBUF_CSR_VRS_OUT3        VREFBUF_CSR_VRS_OUT3_Msk                   /*!<Voltage reference VREF_OUT3     */

+#define VREFBUF_CSR_VRS_OUT4_Pos    (4U)

+#define VREFBUF_CSR_VRS_OUT4_Msk    (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)        /*!< 0x00000030 */

+#define VREFBUF_CSR_VRS_OUT4        VREFBUF_CSR_VRS_OUT4_Msk                   /*!<Voltage reference VREF_OUT4     */

+

+/*******************  Bit definition for VREFBUF_CCR register  ****************/

+#define VREFBUF_CCR_TRIM_Pos        (0U)

+#define VREFBUF_CCR_TRIM_Msk        (0x3FUL << VREFBUF_CCR_TRIM_Pos)           /*!< 0x0000003F */

+#define VREFBUF_CCR_TRIM            VREFBUF_CCR_TRIM_Msk                       /*!<TRIM[5:0] bits (Trimming code)  */

+

+/******************************************************************************/

+/*                                                                            */

+/*                 Flexible Datarate Controller Area Network                  */

+/*                                                                            */

+/******************************************************************************/

+/*!<FDCAN control and status registers */

+/*****************  Bit definition for FDCAN_CREL register  *******************/

+#define FDCAN_CREL_DAY_Pos        (0U)

+#define FDCAN_CREL_DAY_Msk        (0xFFUL << FDCAN_CREL_DAY_Pos)               /*!< 0x000000FF */

+#define FDCAN_CREL_DAY            FDCAN_CREL_DAY_Msk                           /*!<Timestamp Day                           */

+#define FDCAN_CREL_MON_Pos        (8U)

+#define FDCAN_CREL_MON_Msk        (0xFFUL << FDCAN_CREL_MON_Pos)               /*!< 0x0000FF00 */

+#define FDCAN_CREL_MON            FDCAN_CREL_MON_Msk                           /*!<Timestamp Month                         */

+#define FDCAN_CREL_YEAR_Pos       (16U)

+#define FDCAN_CREL_YEAR_Msk       (0xFUL << FDCAN_CREL_YEAR_Pos)               /*!< 0x000F0000 */

+#define FDCAN_CREL_YEAR           FDCAN_CREL_YEAR_Msk                          /*!<Timestamp Year                          */

+#define FDCAN_CREL_SUBSTEP_Pos    (20U)

+#define FDCAN_CREL_SUBSTEP_Msk    (0xFUL << FDCAN_CREL_SUBSTEP_Pos)            /*!< 0x00F00000 */

+#define FDCAN_CREL_SUBSTEP        FDCAN_CREL_SUBSTEP_Msk                       /*!<Sub-step of Core release                */

+#define FDCAN_CREL_STEP_Pos       (24U)

+#define FDCAN_CREL_STEP_Msk       (0xFUL << FDCAN_CREL_STEP_Pos)               /*!< 0x0F000000 */

+#define FDCAN_CREL_STEP           FDCAN_CREL_STEP_Msk                          /*!<Step of Core release                    */

+#define FDCAN_CREL_REL_Pos        (28U)

+#define FDCAN_CREL_REL_Msk        (0xFUL << FDCAN_CREL_REL_Pos)                /*!< 0xF0000000 */

+#define FDCAN_CREL_REL            FDCAN_CREL_REL_Msk                           /*!<Core release                            */

+

+/*****************  Bit definition for FDCAN_ENDN register  *******************/

+#define FDCAN_ENDN_ETV_Pos        (0U)

+#define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endiannes Test Value                    */

+

+/*****************  Bit definition for FDCAN_DBTP register  *******************/

+#define FDCAN_DBTP_DSJW_Pos       (0U)

+#define FDCAN_DBTP_DSJW_Msk       (0xFUL << FDCAN_DBTP_DSJW_Pos)               /*!< 0x0000000F */

+#define FDCAN_DBTP_DSJW           FDCAN_DBTP_DSJW_Msk                          /*!<Synchronization Jump Width              */

+#define FDCAN_DBTP_DTSEG2_Pos     (4U)

+#define FDCAN_DBTP_DTSEG2_Msk     (0xFUL << FDCAN_DBTP_DTSEG2_Pos)             /*!< 0x000000F0 */

+#define FDCAN_DBTP_DTSEG2         FDCAN_DBTP_DTSEG2_Msk                        /*!<Data time segment after sample point    */

+#define FDCAN_DBTP_DTSEG1_Pos     (8U)

+#define FDCAN_DBTP_DTSEG1_Msk     (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)            /*!< 0x00001F00 */

+#define FDCAN_DBTP_DTSEG1         FDCAN_DBTP_DTSEG1_Msk                        /*!<Data time segment before sample point   */

+#define FDCAN_DBTP_DBRP_Pos       (16U)

+#define FDCAN_DBTP_DBRP_Msk       (0x1FUL << FDCAN_DBTP_DBRP_Pos)              /*!< 0x001F0000 */

+#define FDCAN_DBTP_DBRP           FDCAN_DBTP_DBRP_Msk                          /*!<Data BIt Rate Prescaler                 */

+#define FDCAN_DBTP_TDC_Pos        (23U)

+#define FDCAN_DBTP_TDC_Msk        (0x1UL << FDCAN_DBTP_TDC_Pos)                /*!< 0x00800000 */

+#define FDCAN_DBTP_TDC            FDCAN_DBTP_TDC_Msk                           /*!<Transceiver Delay Compensation          */

+

+/*****************  Bit definition for FDCAN_TEST register  *******************/

+#define FDCAN_TEST_LBCK_Pos       (4U)

+#define FDCAN_TEST_LBCK_Msk       (0x1UL << FDCAN_TEST_LBCK_Pos)               /*!< 0x00000010 */

+#define FDCAN_TEST_LBCK           FDCAN_TEST_LBCK_Msk                          /*!<Loop Back mode                           */

+#define FDCAN_TEST_TX_Pos         (5U)

+#define FDCAN_TEST_TX_Msk         (0x3UL << FDCAN_TEST_TX_Pos)                 /*!< 0x00000060 */

+#define FDCAN_TEST_TX             FDCAN_TEST_TX_Msk                            /*!<Control of Transmit Pin                  */

+#define FDCAN_TEST_RX_Pos         (7U)

+#define FDCAN_TEST_RX_Msk         (0x1UL << FDCAN_TEST_RX_Pos)                 /*!< 0x00000080 */

+#define FDCAN_TEST_RX             FDCAN_TEST_RX_Msk                            /*!<Receive Pin                              */

+

+/*****************  Bit definition for FDCAN_RWD register  ********************/

+#define FDCAN_RWD_WDC_Pos         (0U)

+#define FDCAN_RWD_WDC_Msk         (0xFFUL << FDCAN_RWD_WDC_Pos)                /*!< 0x000000FF */

+#define FDCAN_RWD_WDC             FDCAN_RWD_WDC_Msk                            /*!<Watchdog configuration                   */

+#define FDCAN_RWD_WDV_Pos         (8U)

+#define FDCAN_RWD_WDV_Msk         (0xFFUL << FDCAN_RWD_WDV_Pos)                /*!< 0x0000FF00 */

+#define FDCAN_RWD_WDV             FDCAN_RWD_WDV_Msk                            /*!<Watchdog value                           */

+

+/*****************  Bit definition for FDCAN_CCCR register  ********************/

+#define FDCAN_CCCR_INIT_Pos       (0U)

+#define FDCAN_CCCR_INIT_Msk       (0x1UL << FDCAN_CCCR_INIT_Pos)               /*!< 0x00000001 */

+#define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!<Initialization                           */

+#define FDCAN_CCCR_CCE_Pos        (1U)

+#define FDCAN_CCCR_CCE_Msk        (0x1UL << FDCAN_CCCR_CCE_Pos)                /*!< 0x00000002 */

+#define FDCAN_CCCR_CCE            FDCAN_CCCR_CCE_Msk                           /*!<Configuration Change Enable              */

+#define FDCAN_CCCR_ASM_Pos        (2U)

+#define FDCAN_CCCR_ASM_Msk        (0x1UL << FDCAN_CCCR_ASM_Pos)                /*!< 0x00000004 */

+#define FDCAN_CCCR_ASM            FDCAN_CCCR_ASM_Msk                           /*!<ASM Restricted Operation Mode            */

+#define FDCAN_CCCR_CSA_Pos        (3U)

+#define FDCAN_CCCR_CSA_Msk        (0x1UL << FDCAN_CCCR_CSA_Pos)                /*!< 0x00000008 */

+#define FDCAN_CCCR_CSA            FDCAN_CCCR_CSA_Msk                           /*!<Clock Stop Acknowledge                   */

+#define FDCAN_CCCR_CSR_Pos        (4U)

+#define FDCAN_CCCR_CSR_Msk        (0x1UL << FDCAN_CCCR_CSR_Pos)                /*!< 0x00000010 */

+#define FDCAN_CCCR_CSR            FDCAN_CCCR_CSR_Msk                           /*!<Clock Stop Request                       */

+#define FDCAN_CCCR_MON_Pos        (5U)

+#define FDCAN_CCCR_MON_Msk        (0x1UL << FDCAN_CCCR_MON_Pos)                /*!< 0x00000020 */

+#define FDCAN_CCCR_MON            FDCAN_CCCR_MON_Msk                           /*!<Bus Monitoring Mode                      */

+#define FDCAN_CCCR_DAR_Pos        (6U)

+#define FDCAN_CCCR_DAR_Msk        (0x1UL << FDCAN_CCCR_DAR_Pos)                /*!< 0x00000040 */

+#define FDCAN_CCCR_DAR            FDCAN_CCCR_DAR_Msk                           /*!<Disable Automatic Retransmission         */

+#define FDCAN_CCCR_TEST_Pos       (7U)

+#define FDCAN_CCCR_TEST_Msk       (0x1UL << FDCAN_CCCR_TEST_Pos)               /*!< 0x00000080 */

+#define FDCAN_CCCR_TEST           FDCAN_CCCR_TEST_Msk                          /*!<Test Mode Enable                         */

+#define FDCAN_CCCR_FDOE_Pos       (8U)

+#define FDCAN_CCCR_FDOE_Msk       (0x1UL << FDCAN_CCCR_FDOE_Pos)               /*!< 0x00000100 */

+#define FDCAN_CCCR_FDOE           FDCAN_CCCR_FDOE_Msk                          /*!<FD Operation Enable                      */

+#define FDCAN_CCCR_BRSE_Pos       (9U)

+#define FDCAN_CCCR_BRSE_Msk       (0x1UL << FDCAN_CCCR_BRSE_Pos)               /*!< 0x00000200 */

+#define FDCAN_CCCR_BRSE           FDCAN_CCCR_BRSE_Msk                          /*!<FDCAN Bit Rate Switching                 */

+#define FDCAN_CCCR_PXHD_Pos       (12U)

+#define FDCAN_CCCR_PXHD_Msk       (0x1UL << FDCAN_CCCR_PXHD_Pos)               /*!< 0x00001000 */

+#define FDCAN_CCCR_PXHD           FDCAN_CCCR_PXHD_Msk                          /*!<Protocol Exception Handling Disable      */

+#define FDCAN_CCCR_EFBI_Pos       (13U)

+#define FDCAN_CCCR_EFBI_Msk       (0x1UL << FDCAN_CCCR_EFBI_Pos)               /*!< 0x00002000 */

+#define FDCAN_CCCR_EFBI           FDCAN_CCCR_EFBI_Msk                          /*!<Edge Filtering during Bus Integration    */

+#define FDCAN_CCCR_TXP_Pos        (14U)

+#define FDCAN_CCCR_TXP_Msk        (0x1UL << FDCAN_CCCR_TXP_Pos)                /*!< 0x00004000 */

+#define FDCAN_CCCR_TXP            FDCAN_CCCR_TXP_Msk                           /*!<Two CAN bit times Pause                  */

+#define FDCAN_CCCR_NISO_Pos       (15U)

+#define FDCAN_CCCR_NISO_Msk       (0x1UL << FDCAN_CCCR_NISO_Pos)               /*!< 0x00008000 */

+#define FDCAN_CCCR_NISO           FDCAN_CCCR_NISO_Msk                          /*!<Non ISO Operation                        */

+

+/*****************  Bit definition for FDCAN_NBTP register  ********************/

+#define FDCAN_NBTP_NTSEG2_Pos     (0U)

+#define FDCAN_NBTP_NTSEG2_Msk     (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)            /*!< 0x0000007F */

+#define FDCAN_NBTP_NTSEG2         FDCAN_NBTP_NTSEG2_Msk                        /*!<Nominal Time segment after sample point  */

+#define FDCAN_NBTP_NTSEG1_Pos     (8U)

+#define FDCAN_NBTP_NTSEG1_Msk     (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)            /*!< 0x0000FF00 */

+#define FDCAN_NBTP_NTSEG1         FDCAN_NBTP_NTSEG1_Msk                        /*!<Nominal Time segment before sample point */

+#define FDCAN_NBTP_NBRP_Pos       (16U)

+#define FDCAN_NBTP_NBRP_Msk       (0x1FFUL << FDCAN_NBTP_NBRP_Pos)             /*!< 0x01FF0000 */

+#define FDCAN_NBTP_NBRP           FDCAN_NBTP_NBRP_Msk                          /*!<Bit Rate Prescaler                       */

+#define FDCAN_NBTP_NSJW_Pos       (25U)

+#define FDCAN_NBTP_NSJW_Msk       (0x7FUL << FDCAN_NBTP_NSJW_Pos)              /*!< 0xFE000000 */

+#define FDCAN_NBTP_NSJW           FDCAN_NBTP_NSJW_Msk                          /*!<Nominal (Re)Synchronization Jump Width   */

+

+/*****************  Bit definition for FDCAN_TSCC register  ********************/

+#define FDCAN_TSCC_TSS_Pos        (0U)

+#define FDCAN_TSCC_TSS_Msk        (0x3UL << FDCAN_TSCC_TSS_Pos)                /*!< 0x00000003 */

+#define FDCAN_TSCC_TSS            FDCAN_TSCC_TSS_Msk                           /*!<Timestamp Select                         */

+#define FDCAN_TSCC_TCP_Pos        (16U)

+#define FDCAN_TSCC_TCP_Msk        (0xFUL << FDCAN_TSCC_TCP_Pos)                /*!< 0x000F0000 */

+#define FDCAN_TSCC_TCP            FDCAN_TSCC_TCP_Msk                           /*!<Timestamp Counter Prescaler              */

+

+/*****************  Bit definition for FDCAN_TSCV register  ********************/

+#define FDCAN_TSCV_TSC_Pos        (0U)

+#define FDCAN_TSCV_TSC_Msk        (0xFFFFUL << FDCAN_TSCV_TSC_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TSCV_TSC            FDCAN_TSCV_TSC_Msk                           /*!<Timestamp Counter                        */

+

+/*****************  Bit definition for FDCAN_TOCC register  ********************/

+#define FDCAN_TOCC_ETOC_Pos       (0U)

+#define FDCAN_TOCC_ETOC_Msk       (0x1UL << FDCAN_TOCC_ETOC_Pos)               /*!< 0x00000001 */

+#define FDCAN_TOCC_ETOC           FDCAN_TOCC_ETOC_Msk                          /*!<Enable Timeout Counter                   */

+#define FDCAN_TOCC_TOS_Pos        (1U)

+#define FDCAN_TOCC_TOS_Msk        (0x3UL << FDCAN_TOCC_TOS_Pos)                /*!< 0x00000006 */

+#define FDCAN_TOCC_TOS            FDCAN_TOCC_TOS_Msk                           /*!<Timeout Select                           */

+#define FDCAN_TOCC_TOP_Pos        (16U)

+#define FDCAN_TOCC_TOP_Msk        (0xFFFFUL << FDCAN_TOCC_TOP_Pos)             /*!< 0xFFFF0000 */

+#define FDCAN_TOCC_TOP            FDCAN_TOCC_TOP_Msk                           /*!<Timeout Period                           */

+

+/*****************  Bit definition for FDCAN_TOCV register  ********************/

+#define FDCAN_TOCV_TOC_Pos        (0U)

+#define FDCAN_TOCV_TOC_Msk        (0xFFFFUL << FDCAN_TOCV_TOC_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TOCV_TOC            FDCAN_TOCV_TOC_Msk                           /*!<Timeout Counter                          */

+

+/*****************  Bit definition for FDCAN_ECR register  *********************/

+#define FDCAN_ECR_TEC_Pos         (0U)

+#define FDCAN_ECR_TEC_Msk         (0xFUL << FDCAN_ECR_TEC_Pos)                 /*!< 0x0000000F */

+#define FDCAN_ECR_TEC             FDCAN_ECR_TEC_Msk                            /*!<Transmit Error Counter                   */

+#define FDCAN_ECR_REC_Pos         (8U)

+#define FDCAN_ECR_REC_Msk         (0x7FUL << FDCAN_ECR_REC_Pos)                /*!< 0x00007F00 */

+#define FDCAN_ECR_REC             FDCAN_ECR_REC_Msk                            /*!<Receive Error Counter                    */

+#define FDCAN_ECR_RP_Pos          (15U)

+#define FDCAN_ECR_RP_Msk          (0x1UL << FDCAN_ECR_RP_Pos)                  /*!< 0x00008000 */

+#define FDCAN_ECR_RP              FDCAN_ECR_RP_Msk                             /*!<Receive Error Passive                    */

+#define FDCAN_ECR_CEL_Pos         (16U)

+#define FDCAN_ECR_CEL_Msk         (0xFFUL << FDCAN_ECR_CEL_Pos)                /*!< 0x00FF0000 */

+#define FDCAN_ECR_CEL             FDCAN_ECR_CEL_Msk                            /*!<CAN Error Logging                        */

+

+/*****************  Bit definition for FDCAN_PSR register  *********************/

+#define FDCAN_PSR_LEC_Pos         (0U)

+#define FDCAN_PSR_LEC_Msk         (0x7UL << FDCAN_PSR_LEC_Pos)                 /*!< 0x00000007 */

+#define FDCAN_PSR_LEC             FDCAN_PSR_LEC_Msk                            /*!<Last Error Code                          */

+#define FDCAN_PSR_ACT_Pos         (3U)

+#define FDCAN_PSR_ACT_Msk         (0x3UL << FDCAN_PSR_ACT_Pos)                 /*!< 0x00000018 */

+#define FDCAN_PSR_ACT             FDCAN_PSR_ACT_Msk                            /*!<Activity                                 */

+#define FDCAN_PSR_EP_Pos          (5U)

+#define FDCAN_PSR_EP_Msk          (0x1UL << FDCAN_PSR_EP_Pos)                  /*!< 0x00000020 */

+#define FDCAN_PSR_EP              FDCAN_PSR_EP_Msk                             /*!<Error Passive                            */

+#define FDCAN_PSR_EW_Pos          (6U)

+#define FDCAN_PSR_EW_Msk          (0x1UL << FDCAN_PSR_EW_Pos)                  /*!< 0x00000040 */

+#define FDCAN_PSR_EW              FDCAN_PSR_EW_Msk                             /*!<Warning Status                           */

+#define FDCAN_PSR_BO_Pos          (7U)

+#define FDCAN_PSR_BO_Msk          (0x1UL << FDCAN_PSR_BO_Pos)                  /*!< 0x00000080 */

+#define FDCAN_PSR_BO              FDCAN_PSR_BO_Msk                             /*!<Bus_Off Status                           */

+#define FDCAN_PSR_DLEC_Pos        (8U)

+#define FDCAN_PSR_DLEC_Msk        (0x7UL << FDCAN_PSR_DLEC_Pos)                /*!< 0x00000700 */

+#define FDCAN_PSR_DLEC            FDCAN_PSR_DLEC_Msk                           /*!<Data Last Error Code                     */

+#define FDCAN_PSR_RESI_Pos        (11U)

+#define FDCAN_PSR_RESI_Msk        (0x1UL << FDCAN_PSR_RESI_Pos)                /*!< 0x00000800 */

+#define FDCAN_PSR_RESI            FDCAN_PSR_RESI_Msk                           /*!<ESI flag of last received FDCAN Message  */

+#define FDCAN_PSR_RBRS_Pos        (12U)

+#define FDCAN_PSR_RBRS_Msk        (0x1UL << FDCAN_PSR_RBRS_Pos)                /*!< 0x00001000 */

+#define FDCAN_PSR_RBRS            FDCAN_PSR_RBRS_Msk                           /*!<BRS flag of last received FDCAN Message  */

+#define FDCAN_PSR_REDL_Pos        (13U)

+#define FDCAN_PSR_REDL_Msk        (0x1UL << FDCAN_PSR_REDL_Pos)                /*!< 0x00002000 */

+#define FDCAN_PSR_REDL            FDCAN_PSR_REDL_Msk                           /*!<Received FDCAN Message                   */

+#define FDCAN_PSR_PXE_Pos         (14U)

+#define FDCAN_PSR_PXE_Msk         (0x1UL << FDCAN_PSR_PXE_Pos)                 /*!< 0x00004000 */

+#define FDCAN_PSR_PXE             FDCAN_PSR_PXE_Msk                            /*!<Protocol Exception Event                 */

+#define FDCAN_PSR_TDCV_Pos        (16U)

+#define FDCAN_PSR_TDCV_Msk        (0x7FUL << FDCAN_PSR_TDCV_Pos)               /*!< 0x007F0000 */

+#define FDCAN_PSR_TDCV            FDCAN_PSR_TDCV_Msk                           /*!<Transmitter Delay Compensation Value     */

+

+/*****************  Bit definition for FDCAN_TDCR register  ********************/

+#define FDCAN_TDCR_TDCF_Pos       (0U)

+#define FDCAN_TDCR_TDCF_Msk       (0x7FUL << FDCAN_TDCR_TDCF_Pos)              /*!< 0x0000007F */

+#define FDCAN_TDCR_TDCF           FDCAN_TDCR_TDCF_Msk                          /*!<Transmitter Delay Compensation Filter    */

+#define FDCAN_TDCR_TDCO_Pos       (8U)

+#define FDCAN_TDCR_TDCO_Msk       (0x7FUL << FDCAN_TDCR_TDCO_Pos)              /*!< 0x00007F00 */

+#define FDCAN_TDCR_TDCO           FDCAN_TDCR_TDCO_Msk                          /*!<Transmitter Delay Compensation Offset    */

+

+/*****************  Bit definition for FDCAN_IR register  **********************/

+#define FDCAN_IR_RF0N_Pos         (0U)

+#define FDCAN_IR_RF0N_Msk         (0x1UL << FDCAN_IR_RF0N_Pos)                 /*!< 0x00000001 */

+#define FDCAN_IR_RF0N             FDCAN_IR_RF0N_Msk                            /*!<Rx FIFO 0 New Message                    */

+#define FDCAN_IR_RF0W_Pos         (1U)

+#define FDCAN_IR_RF0W_Msk         (0x1UL << FDCAN_IR_RF0W_Pos)                 /*!< 0x00000002 */

+#define FDCAN_IR_RF0W             FDCAN_IR_RF0W_Msk                            /*!<Rx FIFO 0 Watermark Reached              */

+#define FDCAN_IR_RF0F_Pos         (2U)

+#define FDCAN_IR_RF0F_Msk         (0x1UL << FDCAN_IR_RF0F_Pos)                 /*!< 0x00000004 */

+#define FDCAN_IR_RF0F             FDCAN_IR_RF0F_Msk                            /*!<Rx FIFO 0 Full                           */

+#define FDCAN_IR_RF0L_Pos         (3U)

+#define FDCAN_IR_RF0L_Msk         (0x1UL << FDCAN_IR_RF0L_Pos)                 /*!< 0x00000008 */

+#define FDCAN_IR_RF0L             FDCAN_IR_RF0L_Msk                            /*!<Rx FIFO 0 Message Lost                   */

+#define FDCAN_IR_RF1N_Pos         (4U)

+#define FDCAN_IR_RF1N_Msk         (0x1UL << FDCAN_IR_RF1N_Pos)                 /*!< 0x00000010 */

+#define FDCAN_IR_RF1N             FDCAN_IR_RF1N_Msk                            /*!<Rx FIFO 1 New Message                    */

+#define FDCAN_IR_RF1W_Pos         (5U)

+#define FDCAN_IR_RF1W_Msk         (0x1UL << FDCAN_IR_RF1W_Pos)                 /*!< 0x00000020 */

+#define FDCAN_IR_RF1W             FDCAN_IR_RF1W_Msk                            /*!<Rx FIFO 1 Watermark Reached              */

+#define FDCAN_IR_RF1F_Pos         (6U)

+#define FDCAN_IR_RF1F_Msk         (0x1UL << FDCAN_IR_RF1F_Pos)                 /*!< 0x00000040 */

+#define FDCAN_IR_RF1F             FDCAN_IR_RF1F_Msk                            /*!<Rx FIFO 1 Full                           */

+#define FDCAN_IR_RF1L_Pos         (7U)

+#define FDCAN_IR_RF1L_Msk         (0x1UL << FDCAN_IR_RF1L_Pos)                 /*!< 0x00000080 */

+#define FDCAN_IR_RF1L             FDCAN_IR_RF1L_Msk                            /*!<Rx FIFO 1 Message Lost                   */

+#define FDCAN_IR_HPM_Pos          (8U)

+#define FDCAN_IR_HPM_Msk          (0x1UL << FDCAN_IR_HPM_Pos)                  /*!< 0x00000100 */

+#define FDCAN_IR_HPM              FDCAN_IR_HPM_Msk                             /*!<High Priority Message                    */

+#define FDCAN_IR_TC_Pos           (9U)

+#define FDCAN_IR_TC_Msk           (0x1UL << FDCAN_IR_TC_Pos)                   /*!< 0x00000200 */

+#define FDCAN_IR_TC               FDCAN_IR_TC_Msk                              /*!<Transmission Completed                   */

+#define FDCAN_IR_TCF_Pos          (10U)

+#define FDCAN_IR_TCF_Msk          (0x1UL << FDCAN_IR_TCF_Pos)                  /*!< 0x00000400 */

+#define FDCAN_IR_TCF              FDCAN_IR_TCF_Msk                             /*!<Transmission Cancellation Finished       */

+#define FDCAN_IR_TFE_Pos          (11U)

+#define FDCAN_IR_TFE_Msk          (0x1UL << FDCAN_IR_TFE_Pos)                  /*!< 0x00000800 */

+#define FDCAN_IR_TFE              FDCAN_IR_TFE_Msk                             /*!<Tx FIFO Empty                            */

+#define FDCAN_IR_TEFN_Pos         (12U)

+#define FDCAN_IR_TEFN_Msk         (0x1UL << FDCAN_IR_TEFN_Pos)                 /*!< 0x00001000 */

+#define FDCAN_IR_TEFN             FDCAN_IR_TEFN_Msk                            /*!<Tx Event FIFO New Entry                  */

+#define FDCAN_IR_TEFW_Pos         (13U)

+#define FDCAN_IR_TEFW_Msk         (0x1UL << FDCAN_IR_TEFW_Pos)                 /*!< 0x00002000 */

+#define FDCAN_IR_TEFW             FDCAN_IR_TEFW_Msk                            /*!<Tx Event FIFO Watermark Reached          */

+#define FDCAN_IR_TEFF_Pos         (14U)

+#define FDCAN_IR_TEFF_Msk         (0x1UL << FDCAN_IR_TEFF_Pos)                 /*!< 0x00004000 */

+#define FDCAN_IR_TEFF             FDCAN_IR_TEFF_Msk                            /*!<Tx Event FIFO Full                       */

+#define FDCAN_IR_TEFL_Pos         (15U)

+#define FDCAN_IR_TEFL_Msk         (0x1UL << FDCAN_IR_TEFL_Pos)                 /*!< 0x00008000 */

+#define FDCAN_IR_TEFL             FDCAN_IR_TEFL_Msk                            /*!<Tx Event FIFO Element Lost               */

+#define FDCAN_IR_TSW_Pos          (16U)

+#define FDCAN_IR_TSW_Msk          (0x1UL << FDCAN_IR_TSW_Pos)                  /*!< 0x00010000 */

+#define FDCAN_IR_TSW              FDCAN_IR_TSW_Msk                             /*!<Timestamp Wraparound                     */

+#define FDCAN_IR_MRAF_Pos         (17U)

+#define FDCAN_IR_MRAF_Msk         (0x1UL << FDCAN_IR_MRAF_Pos)                 /*!< 0x00020000 */

+#define FDCAN_IR_MRAF             FDCAN_IR_MRAF_Msk                            /*!<Message RAM Access Failure               */

+#define FDCAN_IR_TOO_Pos          (18U)

+#define FDCAN_IR_TOO_Msk          (0x1UL << FDCAN_IR_TOO_Pos)                  /*!< 0x00040000 */

+#define FDCAN_IR_TOO              FDCAN_IR_TOO_Msk                             /*!<Timeout Occurred                         */

+#define FDCAN_IR_DRX_Pos          (19U)

+#define FDCAN_IR_DRX_Msk          (0x1UL << FDCAN_IR_DRX_Pos)                  /*!< 0x00080000 */

+#define FDCAN_IR_DRX              FDCAN_IR_DRX_Msk                             /*!<Message stored to Dedicated Rx Buffer    */

+#define FDCAN_IR_ELO_Pos          (22U)

+#define FDCAN_IR_ELO_Msk          (0x1UL << FDCAN_IR_ELO_Pos)                  /*!< 0x00400000 */

+#define FDCAN_IR_ELO              FDCAN_IR_ELO_Msk                             /*!<Error Logging Overflow                   */

+#define FDCAN_IR_EP_Pos           (23U)

+#define FDCAN_IR_EP_Msk           (0x1UL << FDCAN_IR_EP_Pos)                   /*!< 0x00800000 */

+#define FDCAN_IR_EP               FDCAN_IR_EP_Msk                              /*!<Error Passive                            */

+#define FDCAN_IR_EW_Pos           (24U)

+#define FDCAN_IR_EW_Msk           (0x1UL << FDCAN_IR_EW_Pos)                   /*!< 0x01000000 */

+#define FDCAN_IR_EW               FDCAN_IR_EW_Msk                              /*!<Warning Status                           */

+#define FDCAN_IR_BO_Pos           (25U)

+#define FDCAN_IR_BO_Msk           (0x1UL << FDCAN_IR_BO_Pos)                   /*!< 0x02000000 */

+#define FDCAN_IR_BO               FDCAN_IR_BO_Msk                              /*!<Bus_Off Status                           */

+#define FDCAN_IR_WDI_Pos          (26U)

+#define FDCAN_IR_WDI_Msk          (0x1UL << FDCAN_IR_WDI_Pos)                  /*!< 0x04000000 */

+#define FDCAN_IR_WDI              FDCAN_IR_WDI_Msk                             /*!<Watchdog Interrupt                       */

+#define FDCAN_IR_PEA_Pos          (27U)

+#define FDCAN_IR_PEA_Msk          (0x1UL << FDCAN_IR_PEA_Pos)                  /*!< 0x08000000 */

+#define FDCAN_IR_PEA              FDCAN_IR_PEA_Msk                             /*!<Protocol Error in Arbitration Phase      */

+#define FDCAN_IR_PED_Pos          (28U)

+#define FDCAN_IR_PED_Msk          (0x1UL << FDCAN_IR_PED_Pos)                  /*!< 0x10000000 */

+#define FDCAN_IR_PED              FDCAN_IR_PED_Msk                             /*!<Protocol Error in Data Phase             */

+#define FDCAN_IR_ARA_Pos          (29U)

+#define FDCAN_IR_ARA_Msk          (0x1UL << FDCAN_IR_ARA_Pos)                  /*!< 0x20000000 */

+#define FDCAN_IR_ARA              FDCAN_IR_ARA_Msk                             /*!<Access to Reserved Address               */

+

+/*****************  Bit definition for FDCAN_IE register  **********************/

+#define FDCAN_IE_RF0NE_Pos        (0U)

+#define FDCAN_IE_RF0NE_Msk        (0x1UL << FDCAN_IE_RF0NE_Pos)                /*!< 0x00000001 */

+#define FDCAN_IE_RF0NE            FDCAN_IE_RF0NE_Msk                           /*!<Rx FIFO 0 New Message Enable                 */

+#define FDCAN_IE_RF0WE_Pos        (1U)

+#define FDCAN_IE_RF0WE_Msk        (0x1UL << FDCAN_IE_RF0WE_Pos)                /*!< 0x00000002 */

+#define FDCAN_IE_RF0WE            FDCAN_IE_RF0WE_Msk                           /*!<Rx FIFO 0 Watermark Reached Enable           */

+#define FDCAN_IE_RF0FE_Pos        (2U)

+#define FDCAN_IE_RF0FE_Msk        (0x1UL << FDCAN_IE_RF0FE_Pos)                /*!< 0x00000004 */

+#define FDCAN_IE_RF0FE            FDCAN_IE_RF0FE_Msk                           /*!<Rx FIFO 0 Full Enable                        */

+#define FDCAN_IE_RF0LE_Pos        (3U)

+#define FDCAN_IE_RF0LE_Msk        (0x1UL << FDCAN_IE_RF0LE_Pos)                /*!< 0x00000008 */

+#define FDCAN_IE_RF0LE            FDCAN_IE_RF0LE_Msk                           /*!<Rx FIFO 0 Message Lost Enable                */

+#define FDCAN_IE_RF1NE_Pos        (4U)

+#define FDCAN_IE_RF1NE_Msk        (0x1UL << FDCAN_IE_RF1NE_Pos)                /*!< 0x00000010 */

+#define FDCAN_IE_RF1NE            FDCAN_IE_RF1NE_Msk                           /*!<Rx FIFO 1 New Message Enable                 */

+#define FDCAN_IE_RF1WE_Pos        (5U)

+#define FDCAN_IE_RF1WE_Msk        (0x1UL << FDCAN_IE_RF1WE_Pos)                /*!< 0x00000020 */

+#define FDCAN_IE_RF1WE            FDCAN_IE_RF1WE_Msk                           /*!<Rx FIFO 1 Watermark Reached Enable           */

+#define FDCAN_IE_RF1FE_Pos        (6U)

+#define FDCAN_IE_RF1FE_Msk        (0x1UL << FDCAN_IE_RF1FE_Pos)                /*!< 0x00000040 */

+#define FDCAN_IE_RF1FE            FDCAN_IE_RF1FE_Msk                           /*!<Rx FIFO 1 Full Enable                        */

+#define FDCAN_IE_RF1LE_Pos        (7U)

+#define FDCAN_IE_RF1LE_Msk        (0x1UL << FDCAN_IE_RF1LE_Pos)                /*!< 0x00000080 */

+#define FDCAN_IE_RF1LE            FDCAN_IE_RF1LE_Msk                           /*!<Rx FIFO 1 Message Lost Enable                */

+#define FDCAN_IE_HPME_Pos         (8U)

+#define FDCAN_IE_HPME_Msk         (0x1UL << FDCAN_IE_HPME_Pos)                 /*!< 0x00000100 */

+#define FDCAN_IE_HPME             FDCAN_IE_HPME_Msk                            /*!<High Priority Message Enable                 */

+#define FDCAN_IE_TCE_Pos          (9U)

+#define FDCAN_IE_TCE_Msk          (0x1UL << FDCAN_IE_TCE_Pos)                  /*!< 0x00000200 */

+#define FDCAN_IE_TCE              FDCAN_IE_TCE_Msk                             /*!<Transmission Completed Enable                */

+#define FDCAN_IE_TCFE_Pos         (10U)

+#define FDCAN_IE_TCFE_Msk         (0x1UL << FDCAN_IE_TCFE_Pos)                 /*!< 0x00000400 */

+#define FDCAN_IE_TCFE             FDCAN_IE_TCFE_Msk                            /*!<Transmission Cancellation Finished Enable    */

+#define FDCAN_IE_TFEE_Pos         (11U)

+#define FDCAN_IE_TFEE_Msk         (0x1UL << FDCAN_IE_TFEE_Pos)                 /*!< 0x00000800 */

+#define FDCAN_IE_TFEE             FDCAN_IE_TFEE_Msk                            /*!<Tx FIFO Empty Enable                         */

+#define FDCAN_IE_TEFNE_Pos        (12U)

+#define FDCAN_IE_TEFNE_Msk        (0x1UL << FDCAN_IE_TEFNE_Pos)                /*!< 0x00001000 */

+#define FDCAN_IE_TEFNE            FDCAN_IE_TEFNE_Msk                           /*!<Tx Event FIFO New Entry Enable               */

+#define FDCAN_IE_TEFWE_Pos        (13U)

+#define FDCAN_IE_TEFWE_Msk        (0x1UL << FDCAN_IE_TEFWE_Pos)                /*!< 0x00002000 */

+#define FDCAN_IE_TEFWE            FDCAN_IE_TEFWE_Msk                           /*!<Tx Event FIFO Watermark Reached Enable       */

+#define FDCAN_IE_TEFFE_Pos        (14U)

+#define FDCAN_IE_TEFFE_Msk        (0x1UL << FDCAN_IE_TEFFE_Pos)                /*!< 0x00004000 */

+#define FDCAN_IE_TEFFE            FDCAN_IE_TEFFE_Msk                           /*!<Tx Event FIFO Full Enable                    */

+#define FDCAN_IE_TEFLE_Pos        (15U)

+#define FDCAN_IE_TEFLE_Msk        (0x1UL << FDCAN_IE_TEFLE_Pos)                /*!< 0x00008000 */

+#define FDCAN_IE_TEFLE            FDCAN_IE_TEFLE_Msk                           /*!<Tx Event FIFO Element Lost Enable            */

+#define FDCAN_IE_TSWE_Pos         (16U)

+#define FDCAN_IE_TSWE_Msk         (0x1UL << FDCAN_IE_TSWE_Pos)                 /*!< 0x00010000 */

+#define FDCAN_IE_TSWE             FDCAN_IE_TSWE_Msk                            /*!<Timestamp Wraparound Enable                  */

+#define FDCAN_IE_MRAFE_Pos        (17U)

+#define FDCAN_IE_MRAFE_Msk        (0x1UL << FDCAN_IE_MRAFE_Pos)                /*!< 0x00020000 */

+#define FDCAN_IE_MRAFE            FDCAN_IE_MRAFE_Msk                           /*!<Message RAM Access Failure Enable            */

+#define FDCAN_IE_TOOE_Pos         (18U)

+#define FDCAN_IE_TOOE_Msk         (0x1UL << FDCAN_IE_TOOE_Pos)                 /*!< 0x00040000 */

+#define FDCAN_IE_TOOE             FDCAN_IE_TOOE_Msk                            /*!<Timeout Occurred Enable                      */

+#define FDCAN_IE_DRXE_Pos         (19U)

+#define FDCAN_IE_DRXE_Msk         (0x1UL << FDCAN_IE_DRXE_Pos)                 /*!< 0x00080000 */

+#define FDCAN_IE_DRXE             FDCAN_IE_DRXE_Msk                            /*!<Message stored to Dedicated Rx Buffer Enable */

+#define FDCAN_IE_BECE_Pos         (20U)

+#define FDCAN_IE_BECE_Msk         (0x1UL << FDCAN_IE_BECE_Pos)                 /*!< 0x00100000 */

+#define FDCAN_IE_BECE             FDCAN_IE_BECE_Msk                            /*!<Bit Error Corrected Interrupt Enable         */

+#define FDCAN_IE_BEUE_Pos         (21U)

+#define FDCAN_IE_BEUE_Msk         (0x1UL << FDCAN_IE_BEUE_Pos)                 /*!< 0x00200000 */

+#define FDCAN_IE_BEUE             FDCAN_IE_BEUE_Msk                            /*!<Bit Error Uncorrected Interrupt Enable       */

+#define FDCAN_IE_ELOE_Pos         (22U)

+#define FDCAN_IE_ELOE_Msk         (0x1UL << FDCAN_IE_ELOE_Pos)                 /*!< 0x00400000 */

+#define FDCAN_IE_ELOE             FDCAN_IE_ELOE_Msk                            /*!<Error Logging Overflow Enable                */

+#define FDCAN_IE_EPE_Pos          (23U)

+#define FDCAN_IE_EPE_Msk          (0x1UL << FDCAN_IE_EPE_Pos)                  /*!< 0x00800000 */

+#define FDCAN_IE_EPE              FDCAN_IE_EPE_Msk                             /*!<Error Passive Enable                         */

+#define FDCAN_IE_EWE_Pos          (24U)

+#define FDCAN_IE_EWE_Msk          (0x1UL << FDCAN_IE_EWE_Pos)                  /*!< 0x01000000 */

+#define FDCAN_IE_EWE              FDCAN_IE_EWE_Msk                             /*!<Warning Status Enable                        */

+#define FDCAN_IE_BOE_Pos          (25U)

+#define FDCAN_IE_BOE_Msk          (0x1UL << FDCAN_IE_BOE_Pos)                  /*!< 0x02000000 */

+#define FDCAN_IE_BOE              FDCAN_IE_BOE_Msk                             /*!<Bus_Off Status Enable                        */

+#define FDCAN_IE_WDIE_Pos         (26U)

+#define FDCAN_IE_WDIE_Msk         (0x1UL << FDCAN_IE_WDIE_Pos)                 /*!< 0x04000000 */

+#define FDCAN_IE_WDIE             FDCAN_IE_WDIE_Msk                            /*!<Watchdog Interrupt Enable                    */

+#define FDCAN_IE_PEAE_Pos         (27U)

+#define FDCAN_IE_PEAE_Msk         (0x1UL << FDCAN_IE_PEAE_Pos)                 /*!< 0x08000000 */

+#define FDCAN_IE_PEAE             FDCAN_IE_PEAE_Msk                            /*!<Protocol Error in Arbitration Phase Enable   */

+#define FDCAN_IE_PEDE_Pos         (28U)

+#define FDCAN_IE_PEDE_Msk         (0x1UL << FDCAN_IE_PEDE_Pos)                 /*!< 0x10000000 */

+#define FDCAN_IE_PEDE             FDCAN_IE_PEDE_Msk                            /*!<Protocol Error in Data Phase Enable          */

+#define FDCAN_IE_ARAE_Pos         (29U)

+#define FDCAN_IE_ARAE_Msk         (0x1UL << FDCAN_IE_ARAE_Pos)                 /*!< 0x20000000 */

+#define FDCAN_IE_ARAE             FDCAN_IE_ARAE_Msk                            /*!<Access to Reserved Address Enable            */

+

+/*****************  Bit definition for FDCAN_ILS register  **********************/

+#define FDCAN_ILS_RF0NL_Pos       (0U)

+#define FDCAN_ILS_RF0NL_Msk       (0x1UL << FDCAN_ILS_RF0NL_Pos)               /*!< 0x00000001 */

+#define FDCAN_ILS_RF0NL           FDCAN_ILS_RF0NL_Msk                          /*!<Rx FIFO 0 New Message Line                  */

+#define FDCAN_ILS_RF0WL_Pos       (1U)

+#define FDCAN_ILS_RF0WL_Msk       (0x1UL << FDCAN_ILS_RF0WL_Pos)               /*!< 0x00000002 */

+#define FDCAN_ILS_RF0WL           FDCAN_ILS_RF0WL_Msk                          /*!<Rx FIFO 0 Watermark Reached Line            */

+#define FDCAN_ILS_RF0FL_Pos       (2U)

+#define FDCAN_ILS_RF0FL_Msk       (0x1UL << FDCAN_ILS_RF0FL_Pos)               /*!< 0x00000004 */

+#define FDCAN_ILS_RF0FL           FDCAN_ILS_RF0FL_Msk                          /*!<Rx FIFO 0 Full Line                         */

+#define FDCAN_ILS_RF0LL_Pos       (3U)

+#define FDCAN_ILS_RF0LL_Msk       (0x1UL << FDCAN_ILS_RF0LL_Pos)               /*!< 0x00000008 */

+#define FDCAN_ILS_RF0LL           FDCAN_ILS_RF0LL_Msk                          /*!<Rx FIFO 0 Message Lost Line                 */

+#define FDCAN_ILS_RF1NL_Pos       (4U)

+#define FDCAN_ILS_RF1NL_Msk       (0x1UL << FDCAN_ILS_RF1NL_Pos)               /*!< 0x00000010 */

+#define FDCAN_ILS_RF1NL           FDCAN_ILS_RF1NL_Msk                          /*!<Rx FIFO 1 New Message Line                  */

+#define FDCAN_ILS_RF1WL_Pos       (5U)

+#define FDCAN_ILS_RF1WL_Msk       (0x1UL << FDCAN_ILS_RF1WL_Pos)               /*!< 0x00000020 */

+#define FDCAN_ILS_RF1WL           FDCAN_ILS_RF1WL_Msk                          /*!<Rx FIFO 1 Watermark Reached Line            */

+#define FDCAN_ILS_RF1FL_Pos       (6U)

+#define FDCAN_ILS_RF1FL_Msk       (0x1UL << FDCAN_ILS_RF1FL_Pos)               /*!< 0x00000040 */

+#define FDCAN_ILS_RF1FL           FDCAN_ILS_RF1FL_Msk                          /*!<Rx FIFO 1 Full Line                         */

+#define FDCAN_ILS_RF1LL_Pos       (7U)

+#define FDCAN_ILS_RF1LL_Msk       (0x1UL << FDCAN_ILS_RF1LL_Pos)               /*!< 0x00000080 */

+#define FDCAN_ILS_RF1LL           FDCAN_ILS_RF1LL_Msk                          /*!<Rx FIFO 1 Message Lost Line                 */

+#define FDCAN_ILS_HPML_Pos        (8U)

+#define FDCAN_ILS_HPML_Msk        (0x1UL << FDCAN_ILS_HPML_Pos)                /*!< 0x00000100 */

+#define FDCAN_ILS_HPML            FDCAN_ILS_HPML_Msk                           /*!<High Priority Message Line                  */

+#define FDCAN_ILS_TCL_Pos         (9U)

+#define FDCAN_ILS_TCL_Msk         (0x1UL << FDCAN_ILS_TCL_Pos)                 /*!< 0x00000200 */

+#define FDCAN_ILS_TCL             FDCAN_ILS_TCL_Msk                            /*!<Transmission Completed Line                 */

+#define FDCAN_ILS_TCFL_Pos        (10U)

+#define FDCAN_ILS_TCFL_Msk        (0x1UL << FDCAN_ILS_TCFL_Pos)                /*!< 0x00000400 */

+#define FDCAN_ILS_TCFL            FDCAN_ILS_TCFL_Msk                           /*!<Transmission Cancellation Finished Line     */

+#define FDCAN_ILS_TFEL_Pos        (11U)

+#define FDCAN_ILS_TFEL_Msk        (0x1UL << FDCAN_ILS_TFEL_Pos)                /*!< 0x00000800 */

+#define FDCAN_ILS_TFEL            FDCAN_ILS_TFEL_Msk                           /*!<Tx FIFO Empty Line                          */

+#define FDCAN_ILS_TEFNL_Pos       (12U)

+#define FDCAN_ILS_TEFNL_Msk       (0x1UL << FDCAN_ILS_TEFNL_Pos)               /*!< 0x00001000 */

+#define FDCAN_ILS_TEFNL           FDCAN_ILS_TEFNL_Msk                          /*!<Tx Event FIFO New Entry Line                */

+#define FDCAN_ILS_TEFWL_Pos       (13U)

+#define FDCAN_ILS_TEFWL_Msk       (0x1UL << FDCAN_ILS_TEFWL_Pos)               /*!< 0x00002000 */

+#define FDCAN_ILS_TEFWL           FDCAN_ILS_TEFWL_Msk                          /*!<Tx Event FIFO Watermark Reached Line        */

+#define FDCAN_ILS_TEFFL_Pos       (14U)

+#define FDCAN_ILS_TEFFL_Msk       (0x1UL << FDCAN_ILS_TEFFL_Pos)               /*!< 0x00004000 */

+#define FDCAN_ILS_TEFFL           FDCAN_ILS_TEFFL_Msk                          /*!<Tx Event FIFO Full Line                     */

+#define FDCAN_ILS_TEFLL_Pos       (15U)

+#define FDCAN_ILS_TEFLL_Msk       (0x1UL << FDCAN_ILS_TEFLL_Pos)               /*!< 0x00008000 */

+#define FDCAN_ILS_TEFLL           FDCAN_ILS_TEFLL_Msk                          /*!<Tx Event FIFO Element Lost Line             */

+#define FDCAN_ILS_TSWL_Pos        (16U)

+#define FDCAN_ILS_TSWL_Msk        (0x1UL << FDCAN_ILS_TSWL_Pos)                /*!< 0x00010000 */

+#define FDCAN_ILS_TSWL            FDCAN_ILS_TSWL_Msk                           /*!<Timestamp Wraparound Line                   */

+#define FDCAN_ILS_MRAFE_Pos       (17U)

+#define FDCAN_ILS_MRAFE_Msk       (0x1UL << FDCAN_ILS_MRAFE_Pos)               /*!< 0x00020000 */

+#define FDCAN_ILS_MRAFE           FDCAN_ILS_MRAFE_Msk                          /*!<Message RAM Access Failure Line             */

+#define FDCAN_ILS_TOOE_Pos        (18U)

+#define FDCAN_ILS_TOOE_Msk        (0x1UL << FDCAN_ILS_TOOE_Pos)                /*!< 0x00040000 */

+#define FDCAN_ILS_TOOE            FDCAN_ILS_TOOE_Msk                           /*!<Timeout Occurred Line                       */

+#define FDCAN_ILS_DRXE_Pos        (19U)

+#define FDCAN_ILS_DRXE_Msk        (0x1UL << FDCAN_ILS_DRXE_Pos)                /*!< 0x00080000 */

+#define FDCAN_ILS_DRXE            FDCAN_ILS_DRXE_Msk                           /*!<Message stored to Dedicated Rx Buffer Line  */

+#define FDCAN_ILS_BECE_Pos        (20U)

+#define FDCAN_ILS_BECE_Msk        (0x1UL << FDCAN_ILS_BECE_Pos)                /*!< 0x00100000 */

+#define FDCAN_ILS_BECE            FDCAN_ILS_BECE_Msk                           /*!<Bit Error Corrected Interrupt Line          */

+#define FDCAN_ILS_BEUE_Pos        (21U)

+#define FDCAN_ILS_BEUE_Msk        (0x1UL << FDCAN_ILS_BEUE_Pos)                /*!< 0x00200000 */

+#define FDCAN_ILS_BEUE            FDCAN_ILS_BEUE_Msk                           /*!<Bit Error Uncorrected Interrupt Line        */

+#define FDCAN_ILS_ELOE_Pos        (22U)

+#define FDCAN_ILS_ELOE_Msk        (0x1UL << FDCAN_ILS_ELOE_Pos)                /*!< 0x00400000 */

+#define FDCAN_ILS_ELOE            FDCAN_ILS_ELOE_Msk                           /*!<Error Logging Overflow Line                 */

+#define FDCAN_ILS_EPE_Pos         (23U)

+#define FDCAN_ILS_EPE_Msk         (0x1UL << FDCAN_ILS_EPE_Pos)                 /*!< 0x00800000 */

+#define FDCAN_ILS_EPE             FDCAN_ILS_EPE_Msk                            /*!<Error Passive Line                          */

+#define FDCAN_ILS_EWE_Pos         (24U)

+#define FDCAN_ILS_EWE_Msk         (0x1UL << FDCAN_ILS_EWE_Pos)                 /*!< 0x01000000 */

+#define FDCAN_ILS_EWE             FDCAN_ILS_EWE_Msk                            /*!<Warning Status Line                         */

+#define FDCAN_ILS_BOE_Pos         (25U)

+#define FDCAN_ILS_BOE_Msk         (0x1UL << FDCAN_ILS_BOE_Pos)                 /*!< 0x02000000 */

+#define FDCAN_ILS_BOE             FDCAN_ILS_BOE_Msk                            /*!<Bus_Off Status Line                         */

+#define FDCAN_ILS_WDIE_Pos        (26U)

+#define FDCAN_ILS_WDIE_Msk        (0x1UL << FDCAN_ILS_WDIE_Pos)                /*!< 0x04000000 */

+#define FDCAN_ILS_WDIE            FDCAN_ILS_WDIE_Msk                           /*!<Watchdog Interrupt Line                     */

+#define FDCAN_ILS_PEAE_Pos        (27U)

+#define FDCAN_ILS_PEAE_Msk        (0x1UL << FDCAN_ILS_PEAE_Pos)                /*!< 0x08000000 */

+#define FDCAN_ILS_PEAE            FDCAN_ILS_PEAE_Msk                           /*!<Protocol Error in Arbitration Phase Line    */

+#define FDCAN_ILS_PEDE_Pos        (28U)

+#define FDCAN_ILS_PEDE_Msk        (0x1UL << FDCAN_ILS_PEDE_Pos)                /*!< 0x10000000 */

+#define FDCAN_ILS_PEDE            FDCAN_ILS_PEDE_Msk                           /*!<Protocol Error in Data Phase Line           */

+#define FDCAN_ILS_ARAE_Pos        (29U)

+#define FDCAN_ILS_ARAE_Msk        (0x1UL << FDCAN_ILS_ARAE_Pos)                /*!< 0x20000000 */

+#define FDCAN_ILS_ARAE            FDCAN_ILS_ARAE_Msk                           /*!<Access to Reserved Address Line             */

+

+/*****************  Bit definition for FDCAN_ILE register  **********************/

+#define FDCAN_ILE_EINT0_Pos       (0U)

+#define FDCAN_ILE_EINT0_Msk       (0x1UL << FDCAN_ILE_EINT0_Pos)               /*!< 0x00000001 */

+#define FDCAN_ILE_EINT0           FDCAN_ILE_EINT0_Msk                          /*!<Enable Interrupt Line 0                   */

+#define FDCAN_ILE_EINT1_Pos       (1U)

+#define FDCAN_ILE_EINT1_Msk       (0x1UL << FDCAN_ILE_EINT1_Pos)               /*!< 0x00000002 */

+#define FDCAN_ILE_EINT1           FDCAN_ILE_EINT1_Msk                          /*!<Enable Interrupt Line 1                   */

+

+/*****************  Bit definition for FDCAN_GFC register  **********************/

+#define FDCAN_GFC_RRFE_Pos        (0U)

+#define FDCAN_GFC_RRFE_Msk        (0x1UL << FDCAN_GFC_RRFE_Pos)                /*!< 0x00000001 */

+#define FDCAN_GFC_RRFE            FDCAN_GFC_RRFE_Msk                           /*!<Reject Remote Frames Extended             */

+#define FDCAN_GFC_RRFS_Pos        (1U)

+#define FDCAN_GFC_RRFS_Msk        (0x1UL << FDCAN_GFC_RRFS_Pos)                /*!< 0x00000002 */

+#define FDCAN_GFC_RRFS            FDCAN_GFC_RRFS_Msk                           /*!<Reject Remote Frames Standard             */

+#define FDCAN_GFC_ANFE_Pos        (2U)

+#define FDCAN_GFC_ANFE_Msk        (0x3UL << FDCAN_GFC_ANFE_Pos)                /*!< 0x0000000C */

+#define FDCAN_GFC_ANFE            FDCAN_GFC_ANFE_Msk                           /*!<Accept Non-matching Frames Extended       */

+#define FDCAN_GFC_ANFS_Pos        (4U)

+#define FDCAN_GFC_ANFS_Msk        (0x3UL << FDCAN_GFC_ANFS_Pos)                /*!< 0x00000030 */

+#define FDCAN_GFC_ANFS            FDCAN_GFC_ANFS_Msk                           /*!<Accept Non-matching Frames Standard       */

+

+/*****************  Bit definition for FDCAN_SIDFC register  ********************/

+#define FDCAN_SIDFC_FLSSA_Pos     (2U)

+#define FDCAN_SIDFC_FLSSA_Msk     (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)          /*!< 0x0000FFFC */

+#define FDCAN_SIDFC_FLSSA         FDCAN_SIDFC_FLSSA_Msk                        /*!<Filter List Standard Start Address        */

+#define FDCAN_SIDFC_LSS_Pos       (16U)

+#define FDCAN_SIDFC_LSS_Msk       (0xFFUL << FDCAN_SIDFC_LSS_Pos)              /*!< 0x00FF0000 */

+#define FDCAN_SIDFC_LSS           FDCAN_SIDFC_LSS_Msk                          /*!<List Size Standard                        */

+

+/*****************  Bit definition for FDCAN_XIDFC register  ********************/

+#define FDCAN_XIDFC_FLESA_Pos     (2U)

+#define FDCAN_XIDFC_FLESA_Msk     (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)          /*!< 0x0000FFFC */

+#define FDCAN_XIDFC_FLESA         FDCAN_XIDFC_FLESA_Msk                        /*!<Filter List Standard Start Address        */

+#define FDCAN_XIDFC_LSE_Pos       (16U)

+#define FDCAN_XIDFC_LSE_Msk       (0x7FUL << FDCAN_XIDFC_LSE_Pos)              /*!< 0x007F0000 */

+#define FDCAN_XIDFC_LSE           FDCAN_XIDFC_LSE_Msk                          /*!<List Size Extended                        */

+

+/*****************  Bit definition for FDCAN_XIDAM register  ********************/

+#define FDCAN_XIDAM_EIDM_Pos      (0U)

+#define FDCAN_XIDAM_EIDM_Msk      (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)       /*!< 0x1FFFFFFF */

+#define FDCAN_XIDAM_EIDM          FDCAN_XIDAM_EIDM_Msk                         /*!<Extended ID Mask                          */

+

+/*****************  Bit definition for FDCAN_HPMS register  *********************/

+#define FDCAN_HPMS_BIDX_Pos       (0U)

+#define FDCAN_HPMS_BIDX_Msk       (0x3FUL << FDCAN_HPMS_BIDX_Pos)              /*!< 0x0000003F */

+#define FDCAN_HPMS_BIDX           FDCAN_HPMS_BIDX_Msk                          /*!<Buffer Index                              */

+#define FDCAN_HPMS_MSI_Pos        (6U)

+#define FDCAN_HPMS_MSI_Msk        (0x3UL << FDCAN_HPMS_MSI_Pos)                /*!< 0x000000C0 */

+#define FDCAN_HPMS_MSI            FDCAN_HPMS_MSI_Msk                           /*!<Message Storage Indicator                 */

+#define FDCAN_HPMS_FIDX_Pos       (8U)

+#define FDCAN_HPMS_FIDX_Msk       (0x7FUL << FDCAN_HPMS_FIDX_Pos)              /*!< 0x00007F00 */

+#define FDCAN_HPMS_FIDX           FDCAN_HPMS_FIDX_Msk                          /*!<Filter Index                              */

+#define FDCAN_HPMS_FLST_Pos       (15U)

+#define FDCAN_HPMS_FLST_Msk       (0x1UL << FDCAN_HPMS_FLST_Pos)               /*!< 0x00008000 */

+#define FDCAN_HPMS_FLST           FDCAN_HPMS_FLST_Msk                          /*!<Filter List                               */

+

+/*****************  Bit definition for FDCAN_NDAT1 register  ********************/

+#define FDCAN_NDAT1_ND0_Pos       (0U)

+#define FDCAN_NDAT1_ND0_Msk       (0x1UL << FDCAN_NDAT1_ND0_Pos)               /*!< 0x00000001 */

+#define FDCAN_NDAT1_ND0           FDCAN_NDAT1_ND0_Msk                          /*!<New Data flag of Rx Buffer 0              */

+#define FDCAN_NDAT1_ND1_Pos       (1U)

+#define FDCAN_NDAT1_ND1_Msk       (0x1UL << FDCAN_NDAT1_ND1_Pos)               /*!< 0x00000002 */

+#define FDCAN_NDAT1_ND1           FDCAN_NDAT1_ND1_Msk                          /*!<New Data flag of Rx Buffer 1              */

+#define FDCAN_NDAT1_ND2_Pos       (2U)

+#define FDCAN_NDAT1_ND2_Msk       (0x1UL << FDCAN_NDAT1_ND2_Pos)               /*!< 0x00000004 */

+#define FDCAN_NDAT1_ND2           FDCAN_NDAT1_ND2_Msk                          /*!<New Data flag of Rx Buffer 2              */

+#define FDCAN_NDAT1_ND3_Pos       (3U)

+#define FDCAN_NDAT1_ND3_Msk       (0x1UL << FDCAN_NDAT1_ND3_Pos)               /*!< 0x00000008 */

+#define FDCAN_NDAT1_ND3           FDCAN_NDAT1_ND3_Msk                          /*!<New Data flag of Rx Buffer 3              */

+#define FDCAN_NDAT1_ND4_Pos       (4U)

+#define FDCAN_NDAT1_ND4_Msk       (0x1UL << FDCAN_NDAT1_ND4_Pos)               /*!< 0x00000010 */

+#define FDCAN_NDAT1_ND4           FDCAN_NDAT1_ND4_Msk                          /*!<New Data flag of Rx Buffer 4              */

+#define FDCAN_NDAT1_ND5_Pos       (5U)

+#define FDCAN_NDAT1_ND5_Msk       (0x1UL << FDCAN_NDAT1_ND5_Pos)               /*!< 0x00000020 */

+#define FDCAN_NDAT1_ND5           FDCAN_NDAT1_ND5_Msk                          /*!<New Data flag of Rx Buffer 5              */

+#define FDCAN_NDAT1_ND6_Pos       (6U)

+#define FDCAN_NDAT1_ND6_Msk       (0x1UL << FDCAN_NDAT1_ND6_Pos)               /*!< 0x00000040 */

+#define FDCAN_NDAT1_ND6           FDCAN_NDAT1_ND6_Msk                          /*!<New Data flag of Rx Buffer 6              */

+#define FDCAN_NDAT1_ND7_Pos       (7U)

+#define FDCAN_NDAT1_ND7_Msk       (0x1UL << FDCAN_NDAT1_ND7_Pos)               /*!< 0x00000080 */

+#define FDCAN_NDAT1_ND7           FDCAN_NDAT1_ND7_Msk                          /*!<New Data flag of Rx Buffer 7              */

+#define FDCAN_NDAT1_ND8_Pos       (8U)

+#define FDCAN_NDAT1_ND8_Msk       (0x1UL << FDCAN_NDAT1_ND8_Pos)               /*!< 0x00000100 */

+#define FDCAN_NDAT1_ND8           FDCAN_NDAT1_ND8_Msk                          /*!<New Data flag of Rx Buffer 8              */

+#define FDCAN_NDAT1_ND9_Pos       (9U)

+#define FDCAN_NDAT1_ND9_Msk       (0x1UL << FDCAN_NDAT1_ND9_Pos)               /*!< 0x00000200 */

+#define FDCAN_NDAT1_ND9           FDCAN_NDAT1_ND9_Msk                          /*!<New Data flag of Rx Buffer 9              */

+#define FDCAN_NDAT1_ND10_Pos      (10U)

+#define FDCAN_NDAT1_ND10_Msk      (0x1UL << FDCAN_NDAT1_ND10_Pos)              /*!< 0x00000400 */

+#define FDCAN_NDAT1_ND10          FDCAN_NDAT1_ND10_Msk                         /*!<New Data flag of Rx Buffer 10             */

+#define FDCAN_NDAT1_ND11_Pos      (11U)

+#define FDCAN_NDAT1_ND11_Msk      (0x1UL << FDCAN_NDAT1_ND11_Pos)              /*!< 0x00000800 */

+#define FDCAN_NDAT1_ND11          FDCAN_NDAT1_ND11_Msk                         /*!<New Data flag of Rx Buffer 11             */

+#define FDCAN_NDAT1_ND12_Pos      (12U)

+#define FDCAN_NDAT1_ND12_Msk      (0x1UL << FDCAN_NDAT1_ND12_Pos)              /*!< 0x00001000 */

+#define FDCAN_NDAT1_ND12          FDCAN_NDAT1_ND12_Msk                         /*!<New Data flag of Rx Buffer 12             */

+#define FDCAN_NDAT1_ND13_Pos      (13U)

+#define FDCAN_NDAT1_ND13_Msk      (0x1UL << FDCAN_NDAT1_ND13_Pos)              /*!< 0x00002000 */

+#define FDCAN_NDAT1_ND13          FDCAN_NDAT1_ND13_Msk                         /*!<New Data flag of Rx Buffer 13             */

+#define FDCAN_NDAT1_ND14_Pos      (14U)

+#define FDCAN_NDAT1_ND14_Msk      (0x1UL << FDCAN_NDAT1_ND14_Pos)              /*!< 0x00004000 */

+#define FDCAN_NDAT1_ND14          FDCAN_NDAT1_ND14_Msk                         /*!<New Data flag of Rx Buffer 14             */

+#define FDCAN_NDAT1_ND15_Pos      (15U)

+#define FDCAN_NDAT1_ND15_Msk      (0x1UL << FDCAN_NDAT1_ND15_Pos)              /*!< 0x00008000 */

+#define FDCAN_NDAT1_ND15          FDCAN_NDAT1_ND15_Msk                         /*!<New Data flag of Rx Buffer 15             */

+#define FDCAN_NDAT1_ND16_Pos      (16U)

+#define FDCAN_NDAT1_ND16_Msk      (0x1UL << FDCAN_NDAT1_ND16_Pos)              /*!< 0x00010000 */

+#define FDCAN_NDAT1_ND16          FDCAN_NDAT1_ND16_Msk                         /*!<New Data flag of Rx Buffer 16             */

+#define FDCAN_NDAT1_ND17_Pos      (17U)

+#define FDCAN_NDAT1_ND17_Msk      (0x1UL << FDCAN_NDAT1_ND17_Pos)              /*!< 0x00020000 */

+#define FDCAN_NDAT1_ND17          FDCAN_NDAT1_ND17_Msk                         /*!<New Data flag of Rx Buffer 17             */

+#define FDCAN_NDAT1_ND18_Pos      (18U)

+#define FDCAN_NDAT1_ND18_Msk      (0x1UL << FDCAN_NDAT1_ND18_Pos)              /*!< 0x00040000 */

+#define FDCAN_NDAT1_ND18          FDCAN_NDAT1_ND18_Msk                         /*!<New Data flag of Rx Buffer 18             */

+#define FDCAN_NDAT1_ND19_Pos      (19U)

+#define FDCAN_NDAT1_ND19_Msk      (0x1UL << FDCAN_NDAT1_ND19_Pos)              /*!< 0x00080000 */

+#define FDCAN_NDAT1_ND19          FDCAN_NDAT1_ND19_Msk                         /*!<New Data flag of Rx Buffer 19             */

+#define FDCAN_NDAT1_ND20_Pos      (20U)

+#define FDCAN_NDAT1_ND20_Msk      (0x1UL << FDCAN_NDAT1_ND20_Pos)              /*!< 0x00100000 */

+#define FDCAN_NDAT1_ND20          FDCAN_NDAT1_ND20_Msk                         /*!<New Data flag of Rx Buffer 20             */

+#define FDCAN_NDAT1_ND21_Pos      (21U)

+#define FDCAN_NDAT1_ND21_Msk      (0x1UL << FDCAN_NDAT1_ND21_Pos)              /*!< 0x00200000 */

+#define FDCAN_NDAT1_ND21          FDCAN_NDAT1_ND21_Msk                         /*!<New Data flag of Rx Buffer 21             */

+#define FDCAN_NDAT1_ND22_Pos      (22U)

+#define FDCAN_NDAT1_ND22_Msk      (0x1UL << FDCAN_NDAT1_ND22_Pos)              /*!< 0x00400000 */

+#define FDCAN_NDAT1_ND22          FDCAN_NDAT1_ND22_Msk                         /*!<New Data flag of Rx Buffer 22             */

+#define FDCAN_NDAT1_ND23_Pos      (23U)

+#define FDCAN_NDAT1_ND23_Msk      (0x1UL << FDCAN_NDAT1_ND23_Pos)              /*!< 0x00800000 */

+#define FDCAN_NDAT1_ND23          FDCAN_NDAT1_ND23_Msk                         /*!<New Data flag of Rx Buffer 23             */

+#define FDCAN_NDAT1_ND24_Pos      (24U)

+#define FDCAN_NDAT1_ND24_Msk      (0x1UL << FDCAN_NDAT1_ND24_Pos)              /*!< 0x01000000 */

+#define FDCAN_NDAT1_ND24          FDCAN_NDAT1_ND24_Msk                         /*!<New Data flag of Rx Buffer 24             */

+#define FDCAN_NDAT1_ND25_Pos      (25U)

+#define FDCAN_NDAT1_ND25_Msk      (0x1UL << FDCAN_NDAT1_ND25_Pos)              /*!< 0x02000000 */

+#define FDCAN_NDAT1_ND25          FDCAN_NDAT1_ND25_Msk                         /*!<New Data flag of Rx Buffer 25             */

+#define FDCAN_NDAT1_ND26_Pos      (26U)

+#define FDCAN_NDAT1_ND26_Msk      (0x1UL << FDCAN_NDAT1_ND26_Pos)              /*!< 0x04000000 */

+#define FDCAN_NDAT1_ND26          FDCAN_NDAT1_ND26_Msk                         /*!<New Data flag of Rx Buffer 26             */

+#define FDCAN_NDAT1_ND27_Pos      (27U)

+#define FDCAN_NDAT1_ND27_Msk      (0x1UL << FDCAN_NDAT1_ND27_Pos)              /*!< 0x08000000 */

+#define FDCAN_NDAT1_ND27          FDCAN_NDAT1_ND27_Msk                         /*!<New Data flag of Rx Buffer 27             */

+#define FDCAN_NDAT1_ND28_Pos      (28U)

+#define FDCAN_NDAT1_ND28_Msk      (0x1UL << FDCAN_NDAT1_ND28_Pos)              /*!< 0x10000000 */

+#define FDCAN_NDAT1_ND28          FDCAN_NDAT1_ND28_Msk                         /*!<New Data flag of Rx Buffer 28             */

+#define FDCAN_NDAT1_ND29_Pos      (29U)

+#define FDCAN_NDAT1_ND29_Msk      (0x1UL << FDCAN_NDAT1_ND29_Pos)              /*!< 0x20000000 */

+#define FDCAN_NDAT1_ND29          FDCAN_NDAT1_ND29_Msk                         /*!<New Data flag of Rx Buffer 29             */

+#define FDCAN_NDAT1_ND30_Pos      (30U)

+#define FDCAN_NDAT1_ND30_Msk      (0x1UL << FDCAN_NDAT1_ND30_Pos)              /*!< 0x40000000 */

+#define FDCAN_NDAT1_ND30          FDCAN_NDAT1_ND30_Msk                         /*!<New Data flag of Rx Buffer 30             */

+#define FDCAN_NDAT1_ND31_Pos      (31U)

+#define FDCAN_NDAT1_ND31_Msk      (0x1UL << FDCAN_NDAT1_ND31_Pos)              /*!< 0x80000000 */

+#define FDCAN_NDAT1_ND31          FDCAN_NDAT1_ND31_Msk                         /*!<New Data flag of Rx Buffer 31             */

+

+/*****************  Bit definition for FDCAN_NDAT2 register  ********************/

+#define FDCAN_NDAT2_ND32_Pos      (0U)

+#define FDCAN_NDAT2_ND32_Msk      (0x1UL << FDCAN_NDAT2_ND32_Pos)              /*!< 0x00000001 */

+#define FDCAN_NDAT2_ND32          FDCAN_NDAT2_ND32_Msk                         /*!<New Data flag of Rx Buffer 32             */

+#define FDCAN_NDAT2_ND33_Pos      (1U)

+#define FDCAN_NDAT2_ND33_Msk      (0x1UL << FDCAN_NDAT2_ND33_Pos)              /*!< 0x00000002 */

+#define FDCAN_NDAT2_ND33          FDCAN_NDAT2_ND33_Msk                         /*!<New Data flag of Rx Buffer 33             */

+#define FDCAN_NDAT2_ND34_Pos      (2U)

+#define FDCAN_NDAT2_ND34_Msk      (0x1UL << FDCAN_NDAT2_ND34_Pos)              /*!< 0x00000004 */

+#define FDCAN_NDAT2_ND34          FDCAN_NDAT2_ND34_Msk                         /*!<New Data flag of Rx Buffer 34             */

+#define FDCAN_NDAT2_ND35_Pos      (3U)

+#define FDCAN_NDAT2_ND35_Msk      (0x1UL << FDCAN_NDAT2_ND35_Pos)              /*!< 0x00000008 */

+#define FDCAN_NDAT2_ND35          FDCAN_NDAT2_ND35_Msk                         /*!<New Data flag of Rx Buffer 35             */

+#define FDCAN_NDAT2_ND36_Pos      (4U)

+#define FDCAN_NDAT2_ND36_Msk      (0x1UL << FDCAN_NDAT2_ND36_Pos)              /*!< 0x00000010 */

+#define FDCAN_NDAT2_ND36          FDCAN_NDAT2_ND36_Msk                         /*!<New Data flag of Rx Buffer 36             */

+#define FDCAN_NDAT2_ND37_Pos      (5U)

+#define FDCAN_NDAT2_ND37_Msk      (0x1UL << FDCAN_NDAT2_ND37_Pos)              /*!< 0x00000020 */

+#define FDCAN_NDAT2_ND37          FDCAN_NDAT2_ND37_Msk                         /*!<New Data flag of Rx Buffer 37             */

+#define FDCAN_NDAT2_ND38_Pos      (6U)

+#define FDCAN_NDAT2_ND38_Msk      (0x1UL << FDCAN_NDAT2_ND38_Pos)              /*!< 0x00000040 */

+#define FDCAN_NDAT2_ND38          FDCAN_NDAT2_ND38_Msk                         /*!<New Data flag of Rx Buffer 38             */

+#define FDCAN_NDAT2_ND39_Pos      (7U)

+#define FDCAN_NDAT2_ND39_Msk      (0x1UL << FDCAN_NDAT2_ND39_Pos)              /*!< 0x00000080 */

+#define FDCAN_NDAT2_ND39          FDCAN_NDAT2_ND39_Msk                         /*!<New Data flag of Rx Buffer 39             */

+#define FDCAN_NDAT2_ND40_Pos      (8U)

+#define FDCAN_NDAT2_ND40_Msk      (0x1UL << FDCAN_NDAT2_ND40_Pos)              /*!< 0x00000100 */

+#define FDCAN_NDAT2_ND40          FDCAN_NDAT2_ND40_Msk                         /*!<New Data flag of Rx Buffer 40             */

+#define FDCAN_NDAT2_ND41_Pos      (9U)

+#define FDCAN_NDAT2_ND41_Msk      (0x1UL << FDCAN_NDAT2_ND41_Pos)              /*!< 0x00000200 */

+#define FDCAN_NDAT2_ND41          FDCAN_NDAT2_ND41_Msk                         /*!<New Data flag of Rx Buffer 41             */

+#define FDCAN_NDAT2_ND42_Pos      (10U)

+#define FDCAN_NDAT2_ND42_Msk      (0x1UL << FDCAN_NDAT2_ND42_Pos)              /*!< 0x00000400 */

+#define FDCAN_NDAT2_ND42          FDCAN_NDAT2_ND42_Msk                         /*!<New Data flag of Rx Buffer 42             */

+#define FDCAN_NDAT2_ND43_Pos      (11U)

+#define FDCAN_NDAT2_ND43_Msk      (0x1UL << FDCAN_NDAT2_ND43_Pos)              /*!< 0x00000800 */

+#define FDCAN_NDAT2_ND43          FDCAN_NDAT2_ND43_Msk                         /*!<New Data flag of Rx Buffer 43             */

+#define FDCAN_NDAT2_ND44_Pos      (12U)

+#define FDCAN_NDAT2_ND44_Msk      (0x1UL << FDCAN_NDAT2_ND44_Pos)              /*!< 0x00001000 */

+#define FDCAN_NDAT2_ND44          FDCAN_NDAT2_ND44_Msk                         /*!<New Data flag of Rx Buffer 44             */

+#define FDCAN_NDAT2_ND45_Pos      (13U)

+#define FDCAN_NDAT2_ND45_Msk      (0x1UL << FDCAN_NDAT2_ND45_Pos)              /*!< 0x00002000 */

+#define FDCAN_NDAT2_ND45          FDCAN_NDAT2_ND45_Msk                         /*!<New Data flag of Rx Buffer 45             */

+#define FDCAN_NDAT2_ND46_Pos      (14U)

+#define FDCAN_NDAT2_ND46_Msk      (0x1UL << FDCAN_NDAT2_ND46_Pos)              /*!< 0x00004000 */

+#define FDCAN_NDAT2_ND46          FDCAN_NDAT2_ND46_Msk                         /*!<New Data flag of Rx Buffer 46             */

+#define FDCAN_NDAT2_ND47_Pos      (15U)

+#define FDCAN_NDAT2_ND47_Msk      (0x1UL << FDCAN_NDAT2_ND47_Pos)              /*!< 0x00008000 */

+#define FDCAN_NDAT2_ND47          FDCAN_NDAT2_ND47_Msk                         /*!<New Data flag of Rx Buffer 47             */

+#define FDCAN_NDAT2_ND48_Pos      (16U)

+#define FDCAN_NDAT2_ND48_Msk      (0x1UL << FDCAN_NDAT2_ND48_Pos)              /*!< 0x00010000 */

+#define FDCAN_NDAT2_ND48          FDCAN_NDAT2_ND48_Msk                         /*!<New Data flag of Rx Buffer 48             */

+#define FDCAN_NDAT2_ND49_Pos      (17U)

+#define FDCAN_NDAT2_ND49_Msk      (0x1UL << FDCAN_NDAT2_ND49_Pos)              /*!< 0x00020000 */

+#define FDCAN_NDAT2_ND49          FDCAN_NDAT2_ND49_Msk                         /*!<New Data flag of Rx Buffer 49             */

+#define FDCAN_NDAT2_ND50_Pos      (18U)

+#define FDCAN_NDAT2_ND50_Msk      (0x1UL << FDCAN_NDAT2_ND50_Pos)              /*!< 0x00040000 */

+#define FDCAN_NDAT2_ND50          FDCAN_NDAT2_ND50_Msk                         /*!<New Data flag of Rx Buffer 50             */

+#define FDCAN_NDAT2_ND51_Pos      (19U)

+#define FDCAN_NDAT2_ND51_Msk      (0x1UL << FDCAN_NDAT2_ND51_Pos)              /*!< 0x00080000 */

+#define FDCAN_NDAT2_ND51          FDCAN_NDAT2_ND51_Msk                         /*!<New Data flag of Rx Buffer 51             */

+#define FDCAN_NDAT2_ND52_Pos      (20U)

+#define FDCAN_NDAT2_ND52_Msk      (0x1UL << FDCAN_NDAT2_ND52_Pos)              /*!< 0x00100000 */

+#define FDCAN_NDAT2_ND52          FDCAN_NDAT2_ND52_Msk                         /*!<New Data flag of Rx Buffer 52             */

+#define FDCAN_NDAT2_ND53_Pos      (21U)

+#define FDCAN_NDAT2_ND53_Msk      (0x1UL << FDCAN_NDAT2_ND53_Pos)              /*!< 0x00200000 */

+#define FDCAN_NDAT2_ND53          FDCAN_NDAT2_ND53_Msk                         /*!<New Data flag of Rx Buffer 53             */

+#define FDCAN_NDAT2_ND54_Pos      (22U)

+#define FDCAN_NDAT2_ND54_Msk      (0x1UL << FDCAN_NDAT2_ND54_Pos)              /*!< 0x00400000 */

+#define FDCAN_NDAT2_ND54          FDCAN_NDAT2_ND54_Msk                         /*!<New Data flag of Rx Buffer 54             */

+#define FDCAN_NDAT2_ND55_Pos      (23U)

+#define FDCAN_NDAT2_ND55_Msk      (0x1UL << FDCAN_NDAT2_ND55_Pos)              /*!< 0x00800000 */

+#define FDCAN_NDAT2_ND55          FDCAN_NDAT2_ND55_Msk                         /*!<New Data flag of Rx Buffer 55             */

+#define FDCAN_NDAT2_ND56_Pos      (24U)

+#define FDCAN_NDAT2_ND56_Msk      (0x1UL << FDCAN_NDAT2_ND56_Pos)              /*!< 0x01000000 */

+#define FDCAN_NDAT2_ND56          FDCAN_NDAT2_ND56_Msk                         /*!<New Data flag of Rx Buffer 56             */

+#define FDCAN_NDAT2_ND57_Pos      (25U)

+#define FDCAN_NDAT2_ND57_Msk      (0x1UL << FDCAN_NDAT2_ND57_Pos)              /*!< 0x02000000 */

+#define FDCAN_NDAT2_ND57          FDCAN_NDAT2_ND57_Msk                         /*!<New Data flag of Rx Buffer 57             */

+#define FDCAN_NDAT2_ND58_Pos      (26U)

+#define FDCAN_NDAT2_ND58_Msk      (0x1UL << FDCAN_NDAT2_ND58_Pos)              /*!< 0x04000000 */

+#define FDCAN_NDAT2_ND58          FDCAN_NDAT2_ND58_Msk                         /*!<New Data flag of Rx Buffer 58             */

+#define FDCAN_NDAT2_ND59_Pos      (27U)

+#define FDCAN_NDAT2_ND59_Msk      (0x1UL << FDCAN_NDAT2_ND59_Pos)              /*!< 0x08000000 */

+#define FDCAN_NDAT2_ND59          FDCAN_NDAT2_ND59_Msk                         /*!<New Data flag of Rx Buffer 59             */

+#define FDCAN_NDAT2_ND60_Pos      (28U)

+#define FDCAN_NDAT2_ND60_Msk      (0x1UL << FDCAN_NDAT2_ND60_Pos)              /*!< 0x10000000 */

+#define FDCAN_NDAT2_ND60          FDCAN_NDAT2_ND60_Msk                         /*!<New Data flag of Rx Buffer 60             */

+#define FDCAN_NDAT2_ND61_Pos      (29U)

+#define FDCAN_NDAT2_ND61_Msk      (0x1UL << FDCAN_NDAT2_ND61_Pos)              /*!< 0x20000000 */

+#define FDCAN_NDAT2_ND61          FDCAN_NDAT2_ND61_Msk                         /*!<New Data flag of Rx Buffer 61             */

+#define FDCAN_NDAT2_ND62_Pos      (30U)

+#define FDCAN_NDAT2_ND62_Msk      (0x1UL << FDCAN_NDAT2_ND62_Pos)              /*!< 0x40000000 */

+#define FDCAN_NDAT2_ND62          FDCAN_NDAT2_ND62_Msk                         /*!<New Data flag of Rx Buffer 62             */

+#define FDCAN_NDAT2_ND63_Pos      (31U)

+#define FDCAN_NDAT2_ND63_Msk      (0x1UL << FDCAN_NDAT2_ND63_Pos)              /*!< 0x80000000 */

+#define FDCAN_NDAT2_ND63          FDCAN_NDAT2_ND63_Msk                         /*!<New Data flag of Rx Buffer 63             */

+

+/*****************  Bit definition for FDCAN_RXF0C register  ********************/

+#define FDCAN_RXF0C_F0SA_Pos      (2U)

+#define FDCAN_RXF0C_F0SA_Msk      (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_RXF0C_F0SA          FDCAN_RXF0C_F0SA_Msk                         /*!<Rx FIFO 0 Start Address                   */

+#define FDCAN_RXF0C_F0S_Pos       (16U)

+#define FDCAN_RXF0C_F0S_Msk       (0x7FUL << FDCAN_RXF0C_F0S_Pos)              /*!< 0x007F0000 */

+#define FDCAN_RXF0C_F0S           FDCAN_RXF0C_F0S_Msk                          /*!<Number of Rx FIFO 0 elements              */

+#define FDCAN_RXF0C_F0WM_Pos      (24U)

+#define FDCAN_RXF0C_F0WM_Msk      (0x7FUL << FDCAN_RXF0C_F0WM_Pos)             /*!< 0x7F000000 */

+#define FDCAN_RXF0C_F0WM          FDCAN_RXF0C_F0WM_Msk                         /*!<FIFO 0 Watermark                          */

+#define FDCAN_RXF0C_F0OM_Pos      (31U)

+#define FDCAN_RXF0C_F0OM_Msk      (0x1UL << FDCAN_RXF0C_F0OM_Pos)              /*!< 0x80000000 */

+#define FDCAN_RXF0C_F0OM          FDCAN_RXF0C_F0OM_Msk                         /*!<FIFO 0 Operation Mode                     */

+

+/*****************  Bit definition for FDCAN_RXF0S register  ********************/

+#define FDCAN_RXF0S_F0FL_Pos      (0U)

+#define FDCAN_RXF0S_F0FL_Msk      (0x7FUL << FDCAN_RXF0S_F0FL_Pos)             /*!< 0x0000007F */

+#define FDCAN_RXF0S_F0FL          FDCAN_RXF0S_F0FL_Msk                         /*!<Rx FIFO 0 Fill Level                      */

+#define FDCAN_RXF0S_F0GI_Pos      (8U)

+#define FDCAN_RXF0S_F0GI_Msk      (0x3FUL << FDCAN_RXF0S_F0GI_Pos)             /*!< 0x00003F00 */

+#define FDCAN_RXF0S_F0GI          FDCAN_RXF0S_F0GI_Msk                         /*!<Rx FIFO 0 Get Index                       */

+#define FDCAN_RXF0S_F0PI_Pos      (16U)

+#define FDCAN_RXF0S_F0PI_Msk      (0x3FUL << FDCAN_RXF0S_F0PI_Pos)             /*!< 0x003F0000 */

+#define FDCAN_RXF0S_F0PI          FDCAN_RXF0S_F0PI_Msk                         /*!<Rx FIFO 0 Put Index                       */

+#define FDCAN_RXF0S_F0F_Pos       (24U)

+#define FDCAN_RXF0S_F0F_Msk       (0x1UL << FDCAN_RXF0S_F0F_Pos)               /*!< 0x01000000 */

+#define FDCAN_RXF0S_F0F           FDCAN_RXF0S_F0F_Msk                          /*!<Rx FIFO 0 Full                            */

+#define FDCAN_RXF0S_RF0L_Pos      (25U)

+#define FDCAN_RXF0S_RF0L_Msk      (0x1UL << FDCAN_RXF0S_RF0L_Pos)              /*!< 0x02000000 */

+#define FDCAN_RXF0S_RF0L          FDCAN_RXF0S_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                    */

+

+/*****************  Bit definition for FDCAN_RXF0A register  ********************/

+#define FDCAN_RXF0A_F0AI_Pos      (0U)

+#define FDCAN_RXF0A_F0AI_Msk      (0x3FUL << FDCAN_RXF0A_F0AI_Pos)             /*!< 0x0000003F */

+#define FDCAN_RXF0A_F0AI          FDCAN_RXF0A_F0AI_Msk                         /*!<Rx FIFO 0 Acknowledge Index               */

+

+/*****************  Bit definition for FDCAN_RXBC register  ********************/

+#define FDCAN_RXBC_RBSA_Pos       (2U)

+#define FDCAN_RXBC_RBSA_Msk       (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)            /*!< 0x0000FFFC */

+#define FDCAN_RXBC_RBSA           FDCAN_RXBC_RBSA_Msk                          /*!<Rx Buffer Start Address                   */

+

+/*****************  Bit definition for FDCAN_RXF1C register  ********************/

+#define FDCAN_RXF1C_F1SA_Pos      (2U)

+#define FDCAN_RXF1C_F1SA_Msk      (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_RXF1C_F1SA          FDCAN_RXF1C_F1SA_Msk                         /*!<Rx FIFO 1 Start Address                   */

+#define FDCAN_RXF1C_F1S_Pos       (16U)

+#define FDCAN_RXF1C_F1S_Msk       (0x7FUL << FDCAN_RXF1C_F1S_Pos)              /*!< 0x007F0000 */

+#define FDCAN_RXF1C_F1S           FDCAN_RXF1C_F1S_Msk                          /*!<Number of Rx FIFO 1 elements              */

+#define FDCAN_RXF1C_F1WM_Pos      (24U)

+#define FDCAN_RXF1C_F1WM_Msk      (0x7FUL << FDCAN_RXF1C_F1WM_Pos)             /*!< 0x7F000000 */

+#define FDCAN_RXF1C_F1WM          FDCAN_RXF1C_F1WM_Msk                         /*!<Rx FIFO 1 Watermark                       */

+#define FDCAN_RXF1C_F1OM_Pos      (31U)

+#define FDCAN_RXF1C_F1OM_Msk      (0x1UL << FDCAN_RXF1C_F1OM_Pos)              /*!< 0x80000000 */

+#define FDCAN_RXF1C_F1OM          FDCAN_RXF1C_F1OM_Msk                         /*!<FIFO 1 Operation Mode                     */

+

+/*****************  Bit definition for FDCAN_RXF1S register  ********************/

+#define FDCAN_RXF1S_F1FL_Pos      (0U)

+#define FDCAN_RXF1S_F1FL_Msk      (0x7FUL << FDCAN_RXF1S_F1FL_Pos)             /*!< 0x0000007F */

+#define FDCAN_RXF1S_F1FL          FDCAN_RXF1S_F1FL_Msk                         /*!<Rx FIFO 1 Fill Level                      */

+#define FDCAN_RXF1S_F1GI_Pos      (8U)

+#define FDCAN_RXF1S_F1GI_Msk      (0x3FUL << FDCAN_RXF1S_F1GI_Pos)             /*!< 0x00003F00 */

+#define FDCAN_RXF1S_F1GI          FDCAN_RXF1S_F1GI_Msk                         /*!<Rx FIFO 1 Get Index                       */

+#define FDCAN_RXF1S_F1PI_Pos      (16U)

+#define FDCAN_RXF1S_F1PI_Msk      (0x3FUL << FDCAN_RXF1S_F1PI_Pos)             /*!< 0x003F0000 */

+#define FDCAN_RXF1S_F1PI          FDCAN_RXF1S_F1PI_Msk                         /*!<Rx FIFO 1 Put Index                       */

+#define FDCAN_RXF1S_F1F_Pos       (24U)

+#define FDCAN_RXF1S_F1F_Msk       (0x1UL << FDCAN_RXF1S_F1F_Pos)               /*!< 0x01000000 */

+#define FDCAN_RXF1S_F1F           FDCAN_RXF1S_F1F_Msk                          /*!<Rx FIFO 1 Full                            */

+#define FDCAN_RXF1S_RF1L_Pos      (25U)

+#define FDCAN_RXF1S_RF1L_Msk      (0x1UL << FDCAN_RXF1S_RF1L_Pos)              /*!< 0x02000000 */

+#define FDCAN_RXF1S_RF1L          FDCAN_RXF1S_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                    */

+

+/*****************  Bit definition for FDCAN_RXF1A register  ********************/

+#define FDCAN_RXF1A_F1AI_Pos      (0U)

+#define FDCAN_RXF1A_F1AI_Msk      (0x3FUL << FDCAN_RXF1A_F1AI_Pos)             /*!< 0x0000003F */

+#define FDCAN_RXF1A_F1AI          FDCAN_RXF1A_F1AI_Msk                         /*!<Rx FIFO 1 Acknowledge Index               */

+

+/*****************  Bit definition for FDCAN_RXESC register  ********************/

+#define FDCAN_RXESC_F0DS_Pos      (0U)

+#define FDCAN_RXESC_F0DS_Msk      (0x7UL << FDCAN_RXESC_F0DS_Pos)              /*!< 0x00000007 */

+#define FDCAN_RXESC_F0DS          FDCAN_RXESC_F0DS_Msk                         /*!<Rx FIFO 1 Data Field Size                 */

+#define FDCAN_RXESC_F1DS_Pos      (4U)

+#define FDCAN_RXESC_F1DS_Msk      (0x7UL << FDCAN_RXESC_F1DS_Pos)              /*!< 0x00000070 */

+#define FDCAN_RXESC_F1DS          FDCAN_RXESC_F1DS_Msk                         /*!<Rx FIFO 0 Data Field Size                 */

+#define FDCAN_RXESC_RBDS_Pos      (8U)

+#define FDCAN_RXESC_RBDS_Msk      (0x7UL << FDCAN_RXESC_RBDS_Pos)              /*!< 0x00000700 */

+#define FDCAN_RXESC_RBDS          FDCAN_RXESC_RBDS_Msk                         /*!<Rx Buffer Data Field Size                 */

+

+/*****************  Bit definition for FDCAN_TXBC register  *********************/

+#define FDCAN_TXBC_TBSA_Pos       (2U)

+#define FDCAN_TXBC_TBSA_Msk       (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)            /*!< 0x0000FFFC */

+#define FDCAN_TXBC_TBSA           FDCAN_TXBC_TBSA_Msk                          /*!<Tx Buffers Start Address                  */

+#define FDCAN_TXBC_NDTB_Pos       (16U)

+#define FDCAN_TXBC_NDTB_Msk       (0x3FUL << FDCAN_TXBC_NDTB_Pos)              /*!< 0x003F0000 */

+#define FDCAN_TXBC_NDTB           FDCAN_TXBC_NDTB_Msk                          /*!<Number of Dedicated Transmit Buffers      */

+#define FDCAN_TXBC_TFQS_Pos       (24U)

+#define FDCAN_TXBC_TFQS_Msk       (0x3FUL << FDCAN_TXBC_TFQS_Pos)              /*!< 0x3F000000 */

+#define FDCAN_TXBC_TFQS           FDCAN_TXBC_TFQS_Msk                          /*!<Transmit FIFO/Queue Size                  */

+#define FDCAN_TXBC_TFQM_Pos       (30U)

+#define FDCAN_TXBC_TFQM_Msk       (0x1UL << FDCAN_TXBC_TFQM_Pos)               /*!< 0x40000000 */

+#define FDCAN_TXBC_TFQM           FDCAN_TXBC_TFQM_Msk                          /*!<Tx FIFO/Queue Mode                        */

+

+/*****************  Bit definition for FDCAN_TXFQS register  *********************/

+#define FDCAN_TXFQS_TFFL_Pos      (0U)

+#define FDCAN_TXFQS_TFFL_Msk      (0x3FUL << FDCAN_TXFQS_TFFL_Pos)             /*!< 0x0000003F */

+#define FDCAN_TXFQS_TFFL          FDCAN_TXFQS_TFFL_Msk                         /*!<Tx FIFO Free Level                        */

+#define FDCAN_TXFQS_TFGI_Pos      (8U)

+#define FDCAN_TXFQS_TFGI_Msk      (0x1FUL << FDCAN_TXFQS_TFGI_Pos)             /*!< 0x00001F00 */

+#define FDCAN_TXFQS_TFGI          FDCAN_TXFQS_TFGI_Msk                         /*!<Tx FIFO Get Index                         */

+#define FDCAN_TXFQS_TFQPI_Pos     (16U)

+#define FDCAN_TXFQS_TFQPI_Msk     (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)            /*!< 0x001F0000 */

+#define FDCAN_TXFQS_TFQPI         FDCAN_TXFQS_TFQPI_Msk                        /*!<Tx FIFO/Queue Put Index                   */

+#define FDCAN_TXFQS_TFQF_Pos      (21U)

+#define FDCAN_TXFQS_TFQF_Msk      (0x1UL << FDCAN_TXFQS_TFQF_Pos)              /*!< 0x00200000 */

+#define FDCAN_TXFQS_TFQF          FDCAN_TXFQS_TFQF_Msk                         /*!<Tx FIFO/Queue Full                        */

+

+/*****************  Bit definition for FDCAN_TXESC register  *********************/

+#define FDCAN_TXESC_TBDS_Pos      (0U)

+#define FDCAN_TXESC_TBDS_Msk      (0x7UL << FDCAN_TXESC_TBDS_Pos)              /*!< 0x00000007 */

+#define FDCAN_TXESC_TBDS          FDCAN_TXESC_TBDS_Msk                         /*!<Tx Buffer Data Field Size                 */

+

+/*****************  Bit definition for FDCAN_TXBRP register  *********************/

+#define FDCAN_TXBRP_TRP_Pos       (0U)

+#define FDCAN_TXBRP_TRP_Msk       (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)        /*!< 0xFFFFFFFF */

+#define FDCAN_TXBRP_TRP           FDCAN_TXBRP_TRP_Msk                          /*!<Transmission Request Pending              */

+

+/*****************  Bit definition for FDCAN_TXBAR register  *********************/

+#define FDCAN_TXBAR_AR_Pos        (0U)

+#define FDCAN_TXBAR_AR_Msk        (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBAR_AR            FDCAN_TXBAR_AR_Msk                           /*!<Add Request                               */

+

+/*****************  Bit definition for FDCAN_TXBCR register  *********************/

+#define FDCAN_TXBCR_CR_Pos        (0U)

+#define FDCAN_TXBCR_CR_Msk        (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCR_CR            FDCAN_TXBCR_CR_Msk                           /*!<Cancellation Request                      */

+

+/*****************  Bit definition for FDCAN_TXBTO register  *********************/

+#define FDCAN_TXBTO_TO_Pos        (0U)

+#define FDCAN_TXBTO_TO_Msk        (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBTO_TO            FDCAN_TXBTO_TO_Msk                           /*!<Transmission Occurred                     */

+

+/*****************  Bit definition for FDCAN_TXBCF register  *********************/

+#define FDCAN_TXBCF_CF_Pos        (0U)

+#define FDCAN_TXBCF_CF_Msk        (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCF_CF            FDCAN_TXBCF_CF_Msk                           /*!<Cancellation Finished                     */

+

+/*****************  Bit definition for FDCAN_TXBTIE register  ********************/

+#define FDCAN_TXBTIE_TIE_Pos      (0U)

+#define FDCAN_TXBTIE_TIE_Msk      (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)       /*!< 0xFFFFFFFF */

+#define FDCAN_TXBTIE_TIE          FDCAN_TXBTIE_TIE_Msk                         /*!<Transmission Interrupt Enable             */

+

+/*****************  Bit definition for FDCAN_ TXBCIE register  *******************/

+#define FDCAN_TXBCIE_CFIE_Pos     (0U)

+#define FDCAN_TXBCIE_CFIE_Msk     (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)      /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCIE_CFIE         FDCAN_TXBCIE_CFIE_Msk                        /*!<Cancellation Finished Interrupt Enable    */

+

+/*****************  Bit definition for FDCAN_TXEFC register  *********************/

+#define FDCAN_TXEFC_EFSA_Pos      (2U)

+#define FDCAN_TXEFC_EFSA_Msk      (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_TXEFC_EFSA          FDCAN_TXEFC_EFSA_Msk                         /*!<Event FIFO Start Address                  */

+#define FDCAN_TXEFC_EFS_Pos       (16U)

+#define FDCAN_TXEFC_EFS_Msk       (0x3FUL << FDCAN_TXEFC_EFS_Pos)              /*!< 0x003F0000 */

+#define FDCAN_TXEFC_EFS           FDCAN_TXEFC_EFS_Msk                          /*!<Event FIFO Size                           */

+#define FDCAN_TXEFC_EFWM_Pos      (24U)

+#define FDCAN_TXEFC_EFWM_Msk      (0x3FUL << FDCAN_TXEFC_EFWM_Pos)             /*!< 0x3F000000 */

+#define FDCAN_TXEFC_EFWM          FDCAN_TXEFC_EFWM_Msk                         /*!<Event FIFO Watermark                      */

+

+/*****************  Bit definition for FDCAN_TXEFS register  *********************/

+#define FDCAN_TXEFS_EFFL_Pos      (0U)

+#define FDCAN_TXEFS_EFFL_Msk      (0x3FUL << FDCAN_TXEFS_EFFL_Pos)             /*!< 0x0000003F */

+#define FDCAN_TXEFS_EFFL          FDCAN_TXEFS_EFFL_Msk                         /*!<Event FIFO Fill Level                     */

+#define FDCAN_TXEFS_EFGI_Pos      (8U)

+#define FDCAN_TXEFS_EFGI_Msk      (0x1FUL << FDCAN_TXEFS_EFGI_Pos)             /*!< 0x00001F00 */

+#define FDCAN_TXEFS_EFGI          FDCAN_TXEFS_EFGI_Msk                         /*!<Event FIFO Get Index                      */

+#define FDCAN_TXEFS_EFPI_Pos      (16U)

+#define FDCAN_TXEFS_EFPI_Msk      (0x1FUL << FDCAN_TXEFS_EFPI_Pos)             /*!< 0x001F0000 */

+#define FDCAN_TXEFS_EFPI          FDCAN_TXEFS_EFPI_Msk                         /*!<Event FIFO Put Index                      */

+#define FDCAN_TXEFS_EFF_Pos       (24U)

+#define FDCAN_TXEFS_EFF_Msk       (0x1UL << FDCAN_TXEFS_EFF_Pos)               /*!< 0x01000000 */

+#define FDCAN_TXEFS_EFF           FDCAN_TXEFS_EFF_Msk                          /*!<Event FIFO Full                           */

+#define FDCAN_TXEFS_TEFL_Pos      (25U)

+#define FDCAN_TXEFS_TEFL_Msk      (0x1UL << FDCAN_TXEFS_TEFL_Pos)              /*!< 0x02000000 */

+#define FDCAN_TXEFS_TEFL          FDCAN_TXEFS_TEFL_Msk                         /*!<Tx Event FIFO Element Lost                */

+

+/*****************  Bit definition for FDCAN_TXEFA register  *********************/

+#define FDCAN_TXEFA_EFAI_Pos      (0U)

+#define FDCAN_TXEFA_EFAI_Msk      (0x1FUL << FDCAN_TXEFA_EFAI_Pos)             /*!< 0x0000001F */

+#define FDCAN_TXEFA_EFAI          FDCAN_TXEFA_EFAI_Msk                         /*!<Event FIFO Acknowledge Index              */

+

+/*****************  Bit definition for FDCAN_TTTMC register  *********************/

+#define FDCAN_TTTMC_TMSA_Pos      (2U)

+#define FDCAN_TTTMC_TMSA_Msk      (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_TTTMC_TMSA          FDCAN_TTTMC_TMSA_Msk                         /*!<Trigger Memory Start Address              */

+#define FDCAN_TTTMC_TME_Pos       (16U)

+#define FDCAN_TTTMC_TME_Msk       (0x7FUL << FDCAN_TTTMC_TME_Pos)              /*!< 0x007F0000 */

+#define FDCAN_TTTMC_TME           FDCAN_TTTMC_TME_Msk                          /*!<Trigger Memory Elements                   */

+

+/*****************  Bit definition for FDCAN_TTRMC register  *********************/

+#define FDCAN_TTRMC_RID_Pos       (0U)

+#define FDCAN_TTRMC_RID_Msk       (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)        /*!< 0x1FFFFFFF */

+#define FDCAN_TTRMC_RID           FDCAN_TTRMC_RID_Msk                          /*!<Reference Identifier                      */

+#define FDCAN_TTRMC_XTD_Pos       (30U)

+#define FDCAN_TTRMC_XTD_Msk       (0x1UL << FDCAN_TTRMC_XTD_Pos)               /*!< 0x40000000 */

+#define FDCAN_TTRMC_XTD           FDCAN_TTRMC_XTD_Msk                          /*!< Extended Identifier                      */

+#define FDCAN_TTRMC_RMPS_Pos      (31U)

+#define FDCAN_TTRMC_RMPS_Msk      (0x1UL << FDCAN_TTRMC_RMPS_Pos)              /*!< 0x80000000 */

+#define FDCAN_TTRMC_RMPS          FDCAN_TTRMC_RMPS_Msk                         /*!<Reference Message Payload Select          */

+

+/*****************  Bit definition for FDCAN_TTOCF register  *********************/

+#define FDCAN_TTOCF_OM_Pos        (0U)

+#define FDCAN_TTOCF_OM_Msk        (0x3UL << FDCAN_TTOCF_OM_Pos)                /*!< 0x00000003 */

+#define FDCAN_TTOCF_OM            FDCAN_TTOCF_OM_Msk                           /*!<Operation Mode                            */

+#define FDCAN_TTOCF_GEN_Pos       (3U)

+#define FDCAN_TTOCF_GEN_Msk       (0x1UL << FDCAN_TTOCF_GEN_Pos)               /*!< 0x00000008 */

+#define FDCAN_TTOCF_GEN           FDCAN_TTOCF_GEN_Msk                          /*!<Gap Enable                                */

+#define FDCAN_TTOCF_TM_Pos        (4U)

+#define FDCAN_TTOCF_TM_Msk        (0x1UL << FDCAN_TTOCF_TM_Pos)                /*!< 0x00000010 */

+#define FDCAN_TTOCF_TM            FDCAN_TTOCF_TM_Msk                           /*!<Time Master                               */

+#define FDCAN_TTOCF_LDSDL_Pos     (5U)

+#define FDCAN_TTOCF_LDSDL_Msk     (0x7UL << FDCAN_TTOCF_LDSDL_Pos)             /*!< 0x000000E0 */

+#define FDCAN_TTOCF_LDSDL         FDCAN_TTOCF_LDSDL_Msk                        /*!<LD of Synchronization Deviation Limit     */

+#define FDCAN_TTOCF_IRTO_Pos      (8U)

+#define FDCAN_TTOCF_IRTO_Msk      (0x7FUL << FDCAN_TTOCF_IRTO_Pos)             /*!< 0x00007F00 */

+#define FDCAN_TTOCF_IRTO          FDCAN_TTOCF_IRTO_Msk                         /*!<Initial Reference Trigger Offset          */

+#define FDCAN_TTOCF_EECS_Pos      (15U)

+#define FDCAN_TTOCF_EECS_Msk      (0x1UL << FDCAN_TTOCF_EECS_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTOCF_EECS          FDCAN_TTOCF_EECS_Msk                         /*!<Enable External Clock Synchronization     */

+#define FDCAN_TTOCF_AWL_Pos       (16U)

+#define FDCAN_TTOCF_AWL_Msk       (0xFFUL << FDCAN_TTOCF_AWL_Pos)              /*!< 0x00FF0000 */

+#define FDCAN_TTOCF_AWL           FDCAN_TTOCF_AWL_Msk                          /*!<Application Watchdog Limit                */

+#define FDCAN_TTOCF_EGTF_Pos      (24U)

+#define FDCAN_TTOCF_EGTF_Msk      (0x1UL << FDCAN_TTOCF_EGTF_Pos)              /*!< 0x01000000 */

+#define FDCAN_TTOCF_EGTF          FDCAN_TTOCF_EGTF_Msk                         /*!<Enable Global Time Filtering              */

+#define FDCAN_TTOCF_ECC_Pos       (25U)

+#define FDCAN_TTOCF_ECC_Msk       (0x1UL << FDCAN_TTOCF_ECC_Pos)               /*!< 0x02000000 */

+#define FDCAN_TTOCF_ECC           FDCAN_TTOCF_ECC_Msk                          /*!<Enable Clock Calibration                  */

+#define FDCAN_TTOCF_EVTP_Pos      (26U)

+#define FDCAN_TTOCF_EVTP_Msk      (0x1UL << FDCAN_TTOCF_EVTP_Pos)              /*!< 0x04000000 */

+#define FDCAN_TTOCF_EVTP          FDCAN_TTOCF_EVTP_Msk                         /*!<Event Trigger Polarity                    */

+

+/*****************  Bit definition for FDCAN_TTMLM register  *********************/

+#define FDCAN_TTMLM_CCM_Pos       (0U)

+#define FDCAN_TTMLM_CCM_Msk       (0x3FUL << FDCAN_TTMLM_CCM_Pos)              /*!< 0x0000003F */

+#define FDCAN_TTMLM_CCM           FDCAN_TTMLM_CCM_Msk                          /*!<Cycle Count Max                           */

+#define FDCAN_TTMLM_CSS_Pos       (6U)

+#define FDCAN_TTMLM_CSS_Msk       (0x3UL << FDCAN_TTMLM_CSS_Pos)               /*!< 0x000000C0 */

+#define FDCAN_TTMLM_CSS           FDCAN_TTMLM_CSS_Msk                          /*!<Cycle Start Synchronization               */

+#define FDCAN_TTMLM_TXEW_Pos      (8U)

+#define FDCAN_TTMLM_TXEW_Msk      (0xFUL << FDCAN_TTMLM_TXEW_Pos)              /*!< 0x00000F00 */

+#define FDCAN_TTMLM_TXEW          FDCAN_TTMLM_TXEW_Msk                         /*!<Tx Enable Window                          */

+#define FDCAN_TTMLM_ENTT_Pos      (16U)

+#define FDCAN_TTMLM_ENTT_Msk      (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)            /*!< 0x0FFF0000 */

+#define FDCAN_TTMLM_ENTT          FDCAN_TTMLM_ENTT_Msk                         /*!<Expected Number of Tx Triggers            */

+

+/*****************  Bit definition for FDCAN_TURCF register  *********************/

+#define FDCAN_TURCF_NCL_Pos       (0U)

+#define FDCAN_TURCF_NCL_Msk       (0xFFFFUL << FDCAN_TURCF_NCL_Pos)            /*!< 0x0000FFFF */

+#define FDCAN_TURCF_NCL           FDCAN_TURCF_NCL_Msk                          /*!<Numerator Configuration Low               */

+#define FDCAN_TURCF_DC_Pos        (16U)

+#define FDCAN_TURCF_DC_Msk        (0x3FFFUL << FDCAN_TURCF_DC_Pos)             /*!< 0x3FFF0000 */

+#define FDCAN_TURCF_DC            FDCAN_TURCF_DC_Msk                           /*!<Denominator Configuration                 */

+#define FDCAN_TURCF_ELT_Pos       (31U)

+#define FDCAN_TURCF_ELT_Msk       (0x1UL << FDCAN_TURCF_ELT_Pos)               /*!< 0x80000000 */

+#define FDCAN_TURCF_ELT           FDCAN_TURCF_ELT_Msk                          /*!<Enable Local Time                         */

+

+/*****************  Bit definition for FDCAN_TTOCN register  ********************/

+#define FDCAN_TTOCN_SGT_Pos       (0U)

+#define FDCAN_TTOCN_SGT_Msk       (0x1UL << FDCAN_TTOCN_SGT_Pos)               /*!< 0x00000001 */

+#define FDCAN_TTOCN_SGT           FDCAN_TTOCN_SGT_Msk                          /*!<Set Global time                           */

+#define FDCAN_TTOCN_ECS_Pos       (1U)

+#define FDCAN_TTOCN_ECS_Msk       (0x1UL << FDCAN_TTOCN_ECS_Pos)               /*!< 0x00000002 */

+#define FDCAN_TTOCN_ECS           FDCAN_TTOCN_ECS_Msk                          /*!<External Clock Synchronization            */

+#define FDCAN_TTOCN_SWP_Pos       (2U)

+#define FDCAN_TTOCN_SWP_Msk       (0x1UL << FDCAN_TTOCN_SWP_Pos)               /*!< 0x00000004 */

+#define FDCAN_TTOCN_SWP           FDCAN_TTOCN_SWP_Msk                          /*!<Stop Watch Polarity                       */

+#define FDCAN_TTOCN_SWS_Pos       (3U)

+#define FDCAN_TTOCN_SWS_Msk       (0x3UL << FDCAN_TTOCN_SWS_Pos)               /*!< 0x00000018 */

+#define FDCAN_TTOCN_SWS           FDCAN_TTOCN_SWS_Msk                          /*!<Stop Watch Source                         */

+#define FDCAN_TTOCN_RTIE_Pos      (5U)

+#define FDCAN_TTOCN_RTIE_Msk      (0x1UL << FDCAN_TTOCN_RTIE_Pos)              /*!< 0x00000020 */

+#define FDCAN_TTOCN_RTIE          FDCAN_TTOCN_RTIE_Msk                         /*!<Register Time Mark Interrupt Pulse Enable */

+#define FDCAN_TTOCN_TMC_Pos       (6U)

+#define FDCAN_TTOCN_TMC_Msk       (0x3UL << FDCAN_TTOCN_TMC_Pos)               /*!< 0x000000C0 */

+#define FDCAN_TTOCN_TMC           FDCAN_TTOCN_TMC_Msk                          /*!<Register Time Mark Compare                */

+#define FDCAN_TTOCN_TTIE_Pos      (8U)

+#define FDCAN_TTOCN_TTIE_Msk      (0x1UL << FDCAN_TTOCN_TTIE_Pos)              /*!< 0x00000100 */

+#define FDCAN_TTOCN_TTIE          FDCAN_TTOCN_TTIE_Msk                         /*!<Trigger Time Mark Interrupt Pulse Enable  */

+#define FDCAN_TTOCN_GCS_Pos       (9U)

+#define FDCAN_TTOCN_GCS_Msk       (0x1UL << FDCAN_TTOCN_GCS_Pos)               /*!< 0x00000200 */

+#define FDCAN_TTOCN_GCS           FDCAN_TTOCN_GCS_Msk                          /*!<Gap Control Select                        */

+#define FDCAN_TTOCN_FGP_Pos       (10U)

+#define FDCAN_TTOCN_FGP_Msk       (0x1UL << FDCAN_TTOCN_FGP_Pos)               /*!< 0x00000400 */

+#define FDCAN_TTOCN_FGP           FDCAN_TTOCN_FGP_Msk                          /*!<Finish Gap                                */

+#define FDCAN_TTOCN_TMG_Pos       (11U)

+#define FDCAN_TTOCN_TMG_Msk       (0x1UL << FDCAN_TTOCN_TMG_Pos)               /*!< 0x00000800 */

+#define FDCAN_TTOCN_TMG           FDCAN_TTOCN_TMG_Msk                          /*!<Time Mark Gap                             */

+#define FDCAN_TTOCN_NIG_Pos       (12U)

+#define FDCAN_TTOCN_NIG_Msk       (0x1UL << FDCAN_TTOCN_NIG_Pos)               /*!< 0x00001000 */

+#define FDCAN_TTOCN_NIG           FDCAN_TTOCN_NIG_Msk                          /*!<Next is Gap                               */

+#define FDCAN_TTOCN_ESCN_Pos      (13U)

+#define FDCAN_TTOCN_ESCN_Msk      (0x1UL << FDCAN_TTOCN_ESCN_Pos)              /*!< 0x00002000 */

+#define FDCAN_TTOCN_ESCN          FDCAN_TTOCN_ESCN_Msk                         /*!<External Synchronization Control          */

+#define FDCAN_TTOCN_LCKC_Pos      (15U)

+#define FDCAN_TTOCN_LCKC_Msk      (0x1UL << FDCAN_TTOCN_LCKC_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTOCN_LCKC          FDCAN_TTOCN_LCKC_Msk                         /*!<TT Operation Control Register Locked      */

+

+/*****************  Bit definition for FDCAN_TTGTP register  ********************/

+#define FDCAN_TTGTP_TP_Pos        (0U)

+#define FDCAN_TTGTP_TP_Msk        (0xFFFFUL << FDCAN_TTGTP_TP_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTGTP_TP            FDCAN_TTGTP_TP_Msk                           /*!<Time Preset                               */

+#define FDCAN_TTGTP_CTP_Pos       (16U)

+#define FDCAN_TTGTP_CTP_Msk       (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)            /*!< 0xFFFF0000 */

+#define FDCAN_TTGTP_CTP           FDCAN_TTGTP_CTP_Msk                          /*!<Cycle Time Target Phase                   */

+

+/*****************  Bit definition for FDCAN_TTTMK register  ********************/

+#define FDCAN_TTTMK_TM_Pos        (0U)

+#define FDCAN_TTTMK_TM_Msk        (0xFFFFUL << FDCAN_TTTMK_TM_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTTMK_TM            FDCAN_TTTMK_TM_Msk                           /*!<Time Mark                                 */

+#define FDCAN_TTTMK_TICC_Pos      (16U)

+#define FDCAN_TTTMK_TICC_Msk      (0x7FUL << FDCAN_TTTMK_TICC_Pos)             /*!< 0x007F0000 */

+#define FDCAN_TTTMK_TICC          FDCAN_TTTMK_TICC_Msk                         /*!<Time Mark Cycle Code                      */

+#define FDCAN_TTTMK_LCKM_Pos      (31U)

+#define FDCAN_TTTMK_LCKM_Msk      (0x1UL << FDCAN_TTTMK_LCKM_Pos)              /*!< 0x80000000 */

+#define FDCAN_TTTMK_LCKM          FDCAN_TTTMK_LCKM_Msk                         /*!<TT Time Mark Register Locked              */

+

+/*****************  Bit definition for FDCAN_TTIR register  ********************/

+#define FDCAN_TTIR_SBC_Pos        (0U)

+#define FDCAN_TTIR_SBC_Msk        (0x1UL << FDCAN_TTIR_SBC_Pos)                /*!< 0x00000001 */

+#define FDCAN_TTIR_SBC            FDCAN_TTIR_SBC_Msk                           /*!<Start of Basic Cycle                      */

+#define FDCAN_TTIR_SMC_Pos        (1U)

+#define FDCAN_TTIR_SMC_Msk        (0x1UL << FDCAN_TTIR_SMC_Pos)                /*!< 0x00000002 */

+#define FDCAN_TTIR_SMC            FDCAN_TTIR_SMC_Msk                           /*!<Start of Matrix Cycle                     */

+#define FDCAN_TTIR_CSM_Pos        (2U)

+#define FDCAN_TTIR_CSM_Msk        (0x1UL << FDCAN_TTIR_CSM_Pos)                /*!< 0x00000004 */

+#define FDCAN_TTIR_CSM            FDCAN_TTIR_CSM_Msk                           /*!<Change of Synchronization Mode            */

+#define FDCAN_TTIR_SOG_Pos        (3U)

+#define FDCAN_TTIR_SOG_Msk        (0x1UL << FDCAN_TTIR_SOG_Pos)                /*!< 0x00000008 */

+#define FDCAN_TTIR_SOG            FDCAN_TTIR_SOG_Msk                           /*!<Start of Gap                              */

+#define FDCAN_TTIR_RTMI_Pos       (4U)

+#define FDCAN_TTIR_RTMI_Msk       (0x1UL << FDCAN_TTIR_RTMI_Pos)               /*!< 0x00000010 */

+#define FDCAN_TTIR_RTMI           FDCAN_TTIR_RTMI_Msk                          /*!<Register Time Mark Interrupt              */

+#define FDCAN_TTIR_TTMI_Pos       (5U)

+#define FDCAN_TTIR_TTMI_Msk       (0x1UL << FDCAN_TTIR_TTMI_Pos)               /*!< 0x00000020 */

+#define FDCAN_TTIR_TTMI           FDCAN_TTIR_TTMI_Msk                          /*!<Trigger Time Mark Event Internal          */

+#define FDCAN_TTIR_SWE_Pos        (6U)

+#define FDCAN_TTIR_SWE_Msk        (0x1UL << FDCAN_TTIR_SWE_Pos)                /*!< 0x00000040 */

+#define FDCAN_TTIR_SWE            FDCAN_TTIR_SWE_Msk                           /*!<Stop Watch Event                          */

+#define FDCAN_TTIR_GTW_Pos        (7U)

+#define FDCAN_TTIR_GTW_Msk        (0x1UL << FDCAN_TTIR_GTW_Pos)                /*!< 0x00000080 */

+#define FDCAN_TTIR_GTW            FDCAN_TTIR_GTW_Msk                           /*!<Global Time Wrap                          */

+#define FDCAN_TTIR_GTD_Pos        (8U)

+#define FDCAN_TTIR_GTD_Msk        (0x1UL << FDCAN_TTIR_GTD_Pos)                /*!< 0x00000100 */

+#define FDCAN_TTIR_GTD            FDCAN_TTIR_GTD_Msk                           /*!<Global Time Discontinuity                 */

+#define FDCAN_TTIR_GTE_Pos        (9U)

+#define FDCAN_TTIR_GTE_Msk        (0x1UL << FDCAN_TTIR_GTE_Pos)                /*!< 0x00000200 */

+#define FDCAN_TTIR_GTE            FDCAN_TTIR_GTE_Msk                           /*!<Global Time Error                         */

+#define FDCAN_TTIR_TXU_Pos        (10U)

+#define FDCAN_TTIR_TXU_Msk        (0x1UL << FDCAN_TTIR_TXU_Pos)                /*!< 0x00000400 */

+#define FDCAN_TTIR_TXU            FDCAN_TTIR_TXU_Msk                           /*!<Tx Count Underflow                        */

+#define FDCAN_TTIR_TXO_Pos        (11U)

+#define FDCAN_TTIR_TXO_Msk        (0x1UL << FDCAN_TTIR_TXO_Pos)                /*!< 0x00000800 */

+#define FDCAN_TTIR_TXO            FDCAN_TTIR_TXO_Msk                           /*!<Tx Count Overflow                         */

+#define FDCAN_TTIR_SE1_Pos        (12U)

+#define FDCAN_TTIR_SE1_Msk        (0x1UL << FDCAN_TTIR_SE1_Pos)                /*!< 0x00001000 */

+#define FDCAN_TTIR_SE1            FDCAN_TTIR_SE1_Msk                           /*!<Scheduling Error 1                        */

+#define FDCAN_TTIR_SE2_Pos        (13U)

+#define FDCAN_TTIR_SE2_Msk        (0x1UL << FDCAN_TTIR_SE2_Pos)                /*!< 0x00002000 */

+#define FDCAN_TTIR_SE2            FDCAN_TTIR_SE2_Msk                           /*!<Scheduling Error 2                        */

+#define FDCAN_TTIR_ELC_Pos        (14U)

+#define FDCAN_TTIR_ELC_Msk        (0x1UL << FDCAN_TTIR_ELC_Pos)                /*!< 0x00004000 */

+#define FDCAN_TTIR_ELC            FDCAN_TTIR_ELC_Msk                           /*!<Error Level Changed                       */

+#define FDCAN_TTIR_IWT_Pos        (15U)

+#define FDCAN_TTIR_IWT_Msk        (0x1UL << FDCAN_TTIR_IWT_Pos)                /*!< 0x00008000 */

+#define FDCAN_TTIR_IWT            FDCAN_TTIR_IWT_Msk                           /*!<Initialization Watch Trigger              */

+#define FDCAN_TTIR_WT_Pos         (16U)

+#define FDCAN_TTIR_WT_Msk         (0x1UL << FDCAN_TTIR_WT_Pos)                 /*!< 0x00010000 */

+#define FDCAN_TTIR_WT             FDCAN_TTIR_WT_Msk                            /*!<Watch Trigger                             */

+#define FDCAN_TTIR_AW_Pos         (17U)

+#define FDCAN_TTIR_AW_Msk         (0x1UL << FDCAN_TTIR_AW_Pos)                 /*!< 0x00020000 */

+#define FDCAN_TTIR_AW             FDCAN_TTIR_AW_Msk                            /*!<Application Watchdog                      */

+#define FDCAN_TTIR_CER_Pos        (18U)

+#define FDCAN_TTIR_CER_Msk        (0x1UL << FDCAN_TTIR_CER_Pos)                /*!< 0x00040000 */

+#define FDCAN_TTIR_CER            FDCAN_TTIR_CER_Msk                           /*!<Configuration Error                       */

+

+/*****************  Bit definition for FDCAN_TTIE register  ********************/

+#define FDCAN_TTIE_SBCE_Pos       (0U)

+#define FDCAN_TTIE_SBCE_Msk       (0x1UL << FDCAN_TTIE_SBCE_Pos)               /*!< 0x00000001 */

+#define FDCAN_TTIE_SBCE           FDCAN_TTIE_SBCE_Msk                          /*!<Start of Basic Cycle Interrupt Enable             */

+#define FDCAN_TTIE_SMCE_Pos       (1U)

+#define FDCAN_TTIE_SMCE_Msk       (0x1UL << FDCAN_TTIE_SMCE_Pos)               /*!< 0x00000002 */

+#define FDCAN_TTIE_SMCE           FDCAN_TTIE_SMCE_Msk                          /*!<Start of Matrix Cycle Interrupt Enable            */

+#define FDCAN_TTIE_CSME_Pos       (2U)

+#define FDCAN_TTIE_CSME_Msk       (0x1UL << FDCAN_TTIE_CSME_Pos)               /*!< 0x00000004 */

+#define FDCAN_TTIE_CSME           FDCAN_TTIE_CSME_Msk                          /*!<Change of Synchronization Mode Interrupt Enable   */

+#define FDCAN_TTIE_SOGE_Pos       (3U)

+#define FDCAN_TTIE_SOGE_Msk       (0x1UL << FDCAN_TTIE_SOGE_Pos)               /*!< 0x00000008 */

+#define FDCAN_TTIE_SOGE           FDCAN_TTIE_SOGE_Msk                          /*!<Start of Gap Interrupt Enable                     */

+#define FDCAN_TTIE_RTMIE_Pos      (4U)

+#define FDCAN_TTIE_RTMIE_Msk      (0x1UL << FDCAN_TTIE_RTMIE_Pos)              /*!< 0x00000010 */

+#define FDCAN_TTIE_RTMIE          FDCAN_TTIE_RTMIE_Msk                         /*!<Register Time Mark Interrupt Interrupt Enable     */

+#define FDCAN_TTIE_TTMIE_Pos      (5U)

+#define FDCAN_TTIE_TTMIE_Msk      (0x1UL << FDCAN_TTIE_TTMIE_Pos)              /*!< 0x00000020 */

+#define FDCAN_TTIE_TTMIE          FDCAN_TTIE_TTMIE_Msk                         /*!<Trigger Time Mark Event Internal Interrupt Enable */

+#define FDCAN_TTIE_SWEE_Pos       (6U)

+#define FDCAN_TTIE_SWEE_Msk       (0x1UL << FDCAN_TTIE_SWEE_Pos)               /*!< 0x00000040 */

+#define FDCAN_TTIE_SWEE           FDCAN_TTIE_SWEE_Msk                          /*!<Stop Watch Event Interrupt Enable                 */

+#define FDCAN_TTIE_GTWE_Pos       (7U)

+#define FDCAN_TTIE_GTWE_Msk       (0x1UL << FDCAN_TTIE_GTWE_Pos)               /*!< 0x00000080 */

+#define FDCAN_TTIE_GTWE           FDCAN_TTIE_GTWE_Msk                          /*!<Global Time Wrap Interrupt Enable                 */

+#define FDCAN_TTIE_GTDE_Pos       (8U)

+#define FDCAN_TTIE_GTDE_Msk       (0x1UL << FDCAN_TTIE_GTDE_Pos)               /*!< 0x00000100 */

+#define FDCAN_TTIE_GTDE           FDCAN_TTIE_GTDE_Msk                          /*!<Global Time Discontinuity Interrupt Enable        */

+#define FDCAN_TTIE_GTEE_Pos       (9U)

+#define FDCAN_TTIE_GTEE_Msk       (0x1UL << FDCAN_TTIE_GTEE_Pos)               /*!< 0x00000200 */

+#define FDCAN_TTIE_GTEE           FDCAN_TTIE_GTEE_Msk                          /*!<Global Time Error Interrupt Enable                */

+#define FDCAN_TTIE_TXUE_Pos       (10U)

+#define FDCAN_TTIE_TXUE_Msk       (0x1UL << FDCAN_TTIE_TXUE_Pos)               /*!< 0x00000400 */

+#define FDCAN_TTIE_TXUE           FDCAN_TTIE_TXUE_Msk                          /*!<Tx Count Underflow Interrupt Enable               */

+#define FDCAN_TTIE_TXOE_Pos       (11U)

+#define FDCAN_TTIE_TXOE_Msk       (0x1UL << FDCAN_TTIE_TXOE_Pos)               /*!< 0x00000800 */

+#define FDCAN_TTIE_TXOE           FDCAN_TTIE_TXOE_Msk                          /*!<Tx Count Overflow Interrupt Enable                */

+#define FDCAN_TTIE_SE1E_Pos       (12U)

+#define FDCAN_TTIE_SE1E_Msk       (0x1UL << FDCAN_TTIE_SE1E_Pos)               /*!< 0x00001000 */

+#define FDCAN_TTIE_SE1E           FDCAN_TTIE_SE1E_Msk                          /*!<Scheduling Error 1 Interrupt Enable               */

+#define FDCAN_TTIE_SE2E_Pos       (13U)

+#define FDCAN_TTIE_SE2E_Msk       (0x1UL << FDCAN_TTIE_SE2E_Pos)               /*!< 0x00002000 */

+#define FDCAN_TTIE_SE2E           FDCAN_TTIE_SE2E_Msk                          /*!<Scheduling Error 2 Interrupt Enable               */

+#define FDCAN_TTIE_ELCE_Pos       (14U)

+#define FDCAN_TTIE_ELCE_Msk       (0x1UL << FDCAN_TTIE_ELCE_Pos)               /*!< 0x00004000 */

+#define FDCAN_TTIE_ELCE           FDCAN_TTIE_ELCE_Msk                          /*!<Error Level Changed Interrupt Enable              */

+#define FDCAN_TTIE_IWTE_Pos       (15U)

+#define FDCAN_TTIE_IWTE_Msk       (0x1UL << FDCAN_TTIE_IWTE_Pos)               /*!< 0x00008000 */

+#define FDCAN_TTIE_IWTE           FDCAN_TTIE_IWTE_Msk                          /*!<Initialization Watch Trigger Interrupt Enable     */

+#define FDCAN_TTIE_WTE_Pos        (16U)

+#define FDCAN_TTIE_WTE_Msk        (0x1UL << FDCAN_TTIE_WTE_Pos)                /*!< 0x00010000 */

+#define FDCAN_TTIE_WTE            FDCAN_TTIE_WTE_Msk                           /*!<Watch Trigger Interrupt Enable                    */

+#define FDCAN_TTIE_AWE_Pos        (17U)

+#define FDCAN_TTIE_AWE_Msk        (0x1UL << FDCAN_TTIE_AWE_Pos)                /*!< 0x00020000 */

+#define FDCAN_TTIE_AWE            FDCAN_TTIE_AWE_Msk                           /*!<Application Watchdog Interrupt Enable             */

+#define FDCAN_TTIE_CERE_Pos       (18U)

+#define FDCAN_TTIE_CERE_Msk       (0x1UL << FDCAN_TTIE_CERE_Pos)               /*!< 0x00040000 */

+#define FDCAN_TTIE_CERE           FDCAN_TTIE_CERE_Msk                          /*!<Configuration Error Interrupt Enable              */

+

+/*****************  Bit definition for FDCAN_TTILS register  ********************/

+#define FDCAN_TTILS_SBCS_Pos      (0U)

+#define FDCAN_TTILS_SBCS_Msk      (0x1UL << FDCAN_TTILS_SBCS_Pos)              /*!< 0x00000001 */

+#define FDCAN_TTILS_SBCS          FDCAN_TTILS_SBCS_Msk                         /*!<Start of Basic Cycle Interrupt Line               */

+#define FDCAN_TTILS_SMCS_Pos      (1U)

+#define FDCAN_TTILS_SMCS_Msk      (0x1UL << FDCAN_TTILS_SMCS_Pos)              /*!< 0x00000002 */

+#define FDCAN_TTILS_SMCS          FDCAN_TTILS_SMCS_Msk                         /*!<Start of Matrix Cycle Interrupt Line              */

+#define FDCAN_TTILS_CSMS_Pos      (2U)

+#define FDCAN_TTILS_CSMS_Msk      (0x1UL << FDCAN_TTILS_CSMS_Pos)              /*!< 0x00000004 */

+#define FDCAN_TTILS_CSMS          FDCAN_TTILS_CSMS_Msk                         /*!<Change of Synchronization Mode Interrupt Line     */

+#define FDCAN_TTILS_SOGS_Pos      (3U)

+#define FDCAN_TTILS_SOGS_Msk      (0x1UL << FDCAN_TTILS_SOGS_Pos)              /*!< 0x00000008 */

+#define FDCAN_TTILS_SOGS          FDCAN_TTILS_SOGS_Msk                         /*!<Start of Gap Interrupt Line                       */

+#define FDCAN_TTILS_RTMIS_Pos     (4U)

+#define FDCAN_TTILS_RTMIS_Msk     (0x1UL << FDCAN_TTILS_RTMIS_Pos)             /*!< 0x00000010 */

+#define FDCAN_TTILS_RTMIS         FDCAN_TTILS_RTMIS_Msk                        /*!<Register Time Mark Interrupt Interrupt Line       */

+#define FDCAN_TTILS_TTMIS_Pos     (5U)

+#define FDCAN_TTILS_TTMIS_Msk     (0x1UL << FDCAN_TTILS_TTMIS_Pos)             /*!< 0x00000020 */

+#define FDCAN_TTILS_TTMIS         FDCAN_TTILS_TTMIS_Msk                        /*!<Trigger Time Mark Event Internal Interrupt Line   */

+#define FDCAN_TTILS_SWES_Pos      (6U)

+#define FDCAN_TTILS_SWES_Msk      (0x1UL << FDCAN_TTILS_SWES_Pos)              /*!< 0x00000040 */

+#define FDCAN_TTILS_SWES          FDCAN_TTILS_SWES_Msk                         /*!<Stop Watch Event Interrupt Line                   */

+#define FDCAN_TTILS_GTWS_Pos      (7U)

+#define FDCAN_TTILS_GTWS_Msk      (0x1UL << FDCAN_TTILS_GTWS_Pos)              /*!< 0x00000080 */

+#define FDCAN_TTILS_GTWS          FDCAN_TTILS_GTWS_Msk                         /*!<Global Time Wrap Interrupt Line                   */

+#define FDCAN_TTILS_GTDS_Pos      (8U)

+#define FDCAN_TTILS_GTDS_Msk      (0x1UL << FDCAN_TTILS_GTDS_Pos)              /*!< 0x00000100 */

+#define FDCAN_TTILS_GTDS          FDCAN_TTILS_GTDS_Msk                         /*!<Global Time Discontinuity Interrupt Line          */

+#define FDCAN_TTILS_GTES_Pos      (9U)

+#define FDCAN_TTILS_GTES_Msk      (0x1UL << FDCAN_TTILS_GTES_Pos)              /*!< 0x00000200 */

+#define FDCAN_TTILS_GTES          FDCAN_TTILS_GTES_Msk                         /*!<Global Time Error Interrupt Line                  */

+#define FDCAN_TTILS_TXUS_Pos      (10U)

+#define FDCAN_TTILS_TXUS_Msk      (0x1UL << FDCAN_TTILS_TXUS_Pos)              /*!< 0x00000400 */

+#define FDCAN_TTILS_TXUS          FDCAN_TTILS_TXUS_Msk                         /*!<Tx Count Underflow Interrupt Line                 */

+#define FDCAN_TTILS_TXOS_Pos      (11U)

+#define FDCAN_TTILS_TXOS_Msk      (0x1UL << FDCAN_TTILS_TXOS_Pos)              /*!< 0x00000800 */

+#define FDCAN_TTILS_TXOS          FDCAN_TTILS_TXOS_Msk                         /*!<Tx Count Overflow Interrupt Line                  */

+#define FDCAN_TTILS_SE1S_Pos      (12U)

+#define FDCAN_TTILS_SE1S_Msk      (0x1UL << FDCAN_TTILS_SE1S_Pos)              /*!< 0x00001000 */

+#define FDCAN_TTILS_SE1S          FDCAN_TTILS_SE1S_Msk                         /*!<Scheduling Error 1 Interrupt Line                 */

+#define FDCAN_TTILS_SE2S_Pos      (13U)

+#define FDCAN_TTILS_SE2S_Msk      (0x1UL << FDCAN_TTILS_SE2S_Pos)              /*!< 0x00002000 */

+#define FDCAN_TTILS_SE2S          FDCAN_TTILS_SE2S_Msk                         /*!<Scheduling Error 2 Interrupt Line                 */

+#define FDCAN_TTILS_ELCS_Pos      (14U)

+#define FDCAN_TTILS_ELCS_Msk      (0x1UL << FDCAN_TTILS_ELCS_Pos)              /*!< 0x00004000 */

+#define FDCAN_TTILS_ELCS          FDCAN_TTILS_ELCS_Msk                         /*!<Error Level Changed Interrupt Line                */

+#define FDCAN_TTILS_IWTS_Pos      (15U)

+#define FDCAN_TTILS_IWTS_Msk      (0x1UL << FDCAN_TTILS_IWTS_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTILS_IWTS          FDCAN_TTILS_IWTS_Msk                         /*!<Initialization Watch Trigger Interrupt Line       */

+#define FDCAN_TTILS_WTS_Pos       (16U)

+#define FDCAN_TTILS_WTS_Msk       (0x1UL << FDCAN_TTILS_WTS_Pos)               /*!< 0x00010000 */

+#define FDCAN_TTILS_WTS           FDCAN_TTILS_WTS_Msk                          /*!<Watch Trigger Interrupt Line                      */

+#define FDCAN_TTILS_AWS_Pos       (17U)

+#define FDCAN_TTILS_AWS_Msk       (0x1UL << FDCAN_TTILS_AWS_Pos)               /*!< 0x00020000 */

+#define FDCAN_TTILS_AWS           FDCAN_TTILS_AWS_Msk                          /*!<Application Watchdog Interrupt Line               */

+#define FDCAN_TTILS_CERS_Pos      (18U)

+#define FDCAN_TTILS_CERS_Msk      (0x1UL << FDCAN_TTILS_CERS_Pos)              /*!< 0x00040000 */

+#define FDCAN_TTILS_CERS          FDCAN_TTILS_CERS_Msk                         /*!<Configuration Error Interrupt Line                */

+

+/*****************  Bit definition for FDCAN_TTOST register  ********************/

+#define FDCAN_TTOST_EL_Pos        (0U)

+#define FDCAN_TTOST_EL_Msk        (0x3UL << FDCAN_TTOST_EL_Pos)                /*!< 0x00000003 */

+#define FDCAN_TTOST_EL            FDCAN_TTOST_EL_Msk                           /*!<Error Level                              */

+#define FDCAN_TTOST_MS_Pos        (2U)

+#define FDCAN_TTOST_MS_Msk        (0x3UL << FDCAN_TTOST_MS_Pos)                /*!< 0x0000000C */

+#define FDCAN_TTOST_MS            FDCAN_TTOST_MS_Msk                           /*!<Master State                             */

+#define FDCAN_TTOST_SYS_Pos       (4U)

+#define FDCAN_TTOST_SYS_Msk       (0x3UL << FDCAN_TTOST_SYS_Pos)               /*!< 0x00000030 */

+#define FDCAN_TTOST_SYS           FDCAN_TTOST_SYS_Msk                          /*!<Synchronization State                    */

+#define FDCAN_TTOST_QGTP_Pos      (6U)

+#define FDCAN_TTOST_QGTP_Msk      (0x1UL << FDCAN_TTOST_QGTP_Pos)              /*!< 0x00000040 */

+#define FDCAN_TTOST_QGTP          FDCAN_TTOST_QGTP_Msk                         /*!<Quality of Global Time Phase             */

+#define FDCAN_TTOST_QCS_Pos       (7U)

+#define FDCAN_TTOST_QCS_Msk       (0x1UL << FDCAN_TTOST_QCS_Pos)               /*!< 0x00000080 */

+#define FDCAN_TTOST_QCS           FDCAN_TTOST_QCS_Msk                          /*!<Quality of Clock Speed                   */

+#define FDCAN_TTOST_RTO_Pos       (8U)

+#define FDCAN_TTOST_RTO_Msk       (0xFFUL << FDCAN_TTOST_RTO_Pos)              /*!< 0x0000FF00 */

+#define FDCAN_TTOST_RTO           FDCAN_TTOST_RTO_Msk                          /*!<Reference Trigger Offset                 */

+#define FDCAN_TTOST_WGTD_Pos      (22U)

+#define FDCAN_TTOST_WGTD_Msk      (0x1UL << FDCAN_TTOST_WGTD_Pos)              /*!< 0x00400000 */

+#define FDCAN_TTOST_WGTD          FDCAN_TTOST_WGTD_Msk                         /*!<Wait for Global Time Discontinuity       */

+#define FDCAN_TTOST_GFI_Pos       (23U)

+#define FDCAN_TTOST_GFI_Msk       (0x1UL << FDCAN_TTOST_GFI_Pos)               /*!< 0x00800000 */

+#define FDCAN_TTOST_GFI           FDCAN_TTOST_GFI_Msk                          /*!<Gap Finished Indicator                   */

+#define FDCAN_TTOST_TMP_Pos       (24U)

+#define FDCAN_TTOST_TMP_Msk       (0x7UL << FDCAN_TTOST_TMP_Pos)               /*!< 0x07000000 */

+#define FDCAN_TTOST_TMP           FDCAN_TTOST_TMP_Msk                          /*!<Time Master Priority                     */

+#define FDCAN_TTOST_GSI_Pos       (27U)

+#define FDCAN_TTOST_GSI_Msk       (0x1UL << FDCAN_TTOST_GSI_Pos)               /*!< 0x08000000 */

+#define FDCAN_TTOST_GSI           FDCAN_TTOST_GSI_Msk                          /*!<Gap Started Indicator                    */

+#define FDCAN_TTOST_WFE_Pos       (28U)

+#define FDCAN_TTOST_WFE_Msk       (0x1UL << FDCAN_TTOST_WFE_Pos)               /*!< 0x10000000 */

+#define FDCAN_TTOST_WFE           FDCAN_TTOST_WFE_Msk                          /*!<Wait for Event                           */

+#define FDCAN_TTOST_AWE_Pos       (29U)

+#define FDCAN_TTOST_AWE_Msk       (0x1UL << FDCAN_TTOST_AWE_Pos)               /*!< 0x20000000 */

+#define FDCAN_TTOST_AWE           FDCAN_TTOST_AWE_Msk                          /*!<Application Watchdog Event               */

+#define FDCAN_TTOST_WECS_Pos      (30U)

+#define FDCAN_TTOST_WECS_Msk      (0x1UL << FDCAN_TTOST_WECS_Pos)              /*!< 0x40000000 */

+#define FDCAN_TTOST_WECS          FDCAN_TTOST_WECS_Msk                         /*!<Wait for External Clock Synchronization  */

+#define FDCAN_TTOST_SPL_Pos       (31U)

+#define FDCAN_TTOST_SPL_Msk       (0x1UL << FDCAN_TTOST_SPL_Pos)               /*!< 0x80000000 */

+#define FDCAN_TTOST_SPL           FDCAN_TTOST_SPL_Msk                          /*!<Schedule Phase Lock                      */

+

+/*****************  Bit definition for FDCAN_TURNA register  ********************/

+#define FDCAN_TURNA_NAV_Pos       (0U)

+#define FDCAN_TURNA_NAV_Msk       (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)           /*!< 0x0003FFFF */

+#define FDCAN_TURNA_NAV           FDCAN_TURNA_NAV_Msk                          /*!<Numerator Actual Value                   */

+

+/*****************  Bit definition for FDCAN_TTLGT register  ********************/

+#define FDCAN_TTLGT_LT_Pos        (0U)

+#define FDCAN_TTLGT_LT_Msk        (0xFFFFUL << FDCAN_TTLGT_LT_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTLGT_LT            FDCAN_TTLGT_LT_Msk                           /*!<Local Time                               */

+#define FDCAN_TTLGT_GT_Pos        (16U)

+#define FDCAN_TTLGT_GT_Msk        (0xFFFFUL << FDCAN_TTLGT_GT_Pos)             /*!< 0xFFFF0000 */

+#define FDCAN_TTLGT_GT            FDCAN_TTLGT_GT_Msk                           /*!<Global Time                              */

+

+/*****************  Bit definition for FDCAN_TTCTC register  ********************/

+#define FDCAN_TTCTC_CT_Pos        (0U)

+#define FDCAN_TTCTC_CT_Msk        (0xFFFFUL << FDCAN_TTCTC_CT_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTCTC_CT            FDCAN_TTCTC_CT_Msk                           /*!<Cycle Time                               */

+#define FDCAN_TTCTC_CC_Pos        (16U)

+#define FDCAN_TTCTC_CC_Msk        (0x3FUL << FDCAN_TTCTC_CC_Pos)               /*!< 0x003F0000 */

+#define FDCAN_TTCTC_CC            FDCAN_TTCTC_CC_Msk                           /*!<Cycle Count                              */

+

+/*****************  Bit definition for FDCAN_TTCPT register  ********************/

+#define FDCAN_TTCPT_CCV_Pos       (0U)

+#define FDCAN_TTCPT_CCV_Msk       (0x3FUL << FDCAN_TTCPT_CCV_Pos)              /*!< 0x0000003F */

+#define FDCAN_TTCPT_CCV           FDCAN_TTCPT_CCV_Msk                          /*!<Cycle Count Value                        */

+#define FDCAN_TTCPT_SWV_Pos       (16U)

+#define FDCAN_TTCPT_SWV_Msk       (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)            /*!< 0xFFFF0000 */

+#define FDCAN_TTCPT_SWV           FDCAN_TTCPT_SWV_Msk                          /*!<Stop Watch Value                         */

+

+/*****************  Bit definition for FDCAN_TTCSM register  ********************/

+#define FDCAN_TTCSM_CSM_Pos       (0U)

+#define FDCAN_TTCSM_CSM_Msk       (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)            /*!< 0x0000FFFF */

+#define FDCAN_TTCSM_CSM           FDCAN_TTCSM_CSM_Msk                          /*!<Cycle Sync Mark                          */

+

+/*****************  Bit definition for FDCAN_TTTS register  *********************/

+#define FDCAN_TTTS_SWTSEL_Pos     (0U)

+#define FDCAN_TTTS_SWTSEL_Msk     (0x3UL << FDCAN_TTTS_SWTSEL_Pos)             /*!< 0x00000003 */

+#define FDCAN_TTTS_SWTSEL         FDCAN_TTTS_SWTSEL_Msk                        /*!<Stop watch trigger input selection       */

+#define FDCAN_TTTS_EVTSEL_Pos     (4U)

+#define FDCAN_TTTS_EVTSEL_Msk     (0x3UL << FDCAN_TTTS_EVTSEL_Pos)             /*!< 0x00000030 */

+#define FDCAN_TTTS_EVTSEL         FDCAN_TTTS_EVTSEL_Msk                        /*!<Event trigger input selection            */

+

+/********************************************************************************/

+/*                                                                              */

+/*                      FDCANCCU (Clock Calibration unit)                       */

+/*                                                                              */

+/********************************************************************************/

+

+/*****************  Bit definition for FDCANCCU_CREL register  ******************/

+#define FDCANCCU_CREL_DAY_Pos        (0U)

+#define FDCANCCU_CREL_DAY_Msk        (0xFFUL << FDCANCCU_CREL_DAY_Pos)         /*!< 0x000000FF */

+#define FDCANCCU_CREL_DAY            FDCANCCU_CREL_DAY_Msk                     /*!<Timestamp Day                           */

+#define FDCANCCU_CREL_MON_Pos        (8U)

+#define FDCANCCU_CREL_MON_Msk        (0xFFUL << FDCANCCU_CREL_MON_Pos)         /*!< 0x0000FF00 */

+#define FDCANCCU_CREL_MON            FDCANCCU_CREL_MON_Msk                     /*!<Timestamp Month                         */

+#define FDCANCCU_CREL_YEAR_Pos       (16U)

+#define FDCANCCU_CREL_YEAR_Msk       (0xFUL << FDCANCCU_CREL_YEAR_Pos)         /*!< 0x000F0000 */

+#define FDCANCCU_CREL_YEAR           FDCANCCU_CREL_YEAR_Msk                    /*!<Timestamp Year                          */

+#define FDCANCCU_CREL_SUBSTEP_Pos    (20U)

+#define FDCANCCU_CREL_SUBSTEP_Msk    (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)      /*!< 0x00F00000 */

+#define FDCANCCU_CREL_SUBSTEP        FDCANCCU_CREL_SUBSTEP_Msk                 /*!<Sub-step of Core release                */

+#define FDCANCCU_CREL_STEP_Pos       (24U)

+#define FDCANCCU_CREL_STEP_Msk       (0xFUL << FDCANCCU_CREL_STEP_Pos)         /*!< 0x0F000000 */

+#define FDCANCCU_CREL_STEP           FDCANCCU_CREL_STEP_Msk                    /*!<Step of Core release                    */

+#define FDCANCCU_CREL_REL_Pos        (28U)

+#define FDCANCCU_CREL_REL_Msk        (0xFUL << FDCANCCU_CREL_REL_Pos)          /*!< 0xF0000000 */

+#define FDCANCCU_CREL_REL            FDCANCCU_CREL_REL_Msk                     /*!<Core release                            */

+

+/*****************  Bit definition for FDCANCCU_CCFG register  ******************/

+#define FDCANCCU_CCFG_TQBT_Pos       (0U)

+#define FDCANCCU_CCFG_TQBT_Msk       (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)        /*!< 0x0000001F */

+#define FDCANCCU_CCFG_TQBT           FDCANCCU_CCFG_TQBT_Msk                    /*!<Time Quanta per Bit Time                */

+#define FDCANCCU_CCFG_BCC_Pos        (6U)

+#define FDCANCCU_CCFG_BCC_Msk        (0x1UL << FDCANCCU_CCFG_BCC_Pos)          /*!< 0x00000040 */

+#define FDCANCCU_CCFG_BCC            FDCANCCU_CCFG_BCC_Msk                     /*!<Bypass Clock Calibration                */

+#define FDCANCCU_CCFG_CFL_Pos        (7U)

+#define FDCANCCU_CCFG_CFL_Msk        (0x1UL << FDCANCCU_CCFG_CFL_Pos)          /*!< 0x00000080 */

+#define FDCANCCU_CCFG_CFL            FDCANCCU_CCFG_CFL_Msk                     /*!<Calibration Field Length                */

+#define FDCANCCU_CCFG_OCPM_Pos       (8U)

+#define FDCANCCU_CCFG_OCPM_Msk       (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)        /*!< 0x0000FF00 */

+#define FDCANCCU_CCFG_OCPM           FDCANCCU_CCFG_OCPM_Msk                    /*!<Oscillator Clock Periods Minimum        */

+#define FDCANCCU_CCFG_CDIV_Pos       (16U)

+#define FDCANCCU_CCFG_CDIV_Msk       (0xFUL << FDCANCCU_CCFG_CDIV_Pos)         /*!< 0x000F0000 */

+#define FDCANCCU_CCFG_CDIV           FDCANCCU_CCFG_CDIV_Msk                    /*!<Clock Divider                           */

+#define FDCANCCU_CCFG_SWR_Pos        (31U)

+#define FDCANCCU_CCFG_SWR_Msk        (0x1UL << FDCANCCU_CCFG_SWR_Pos)          /*!< 0x80000000 */

+#define FDCANCCU_CCFG_SWR            FDCANCCU_CCFG_SWR_Msk                     /*!<Software Reset                          */

+

+/*****************  Bit definition for FDCANCCU_CSTAT register  *****************/

+#define FDCANCCU_CSTAT_OCPC_Pos      (0U)

+#define FDCANCCU_CSTAT_OCPC_Msk      (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)    /*!< 0x0003FFFF */

+#define FDCANCCU_CSTAT_OCPC          FDCANCCU_CSTAT_OCPC_Msk                   /*!<Oscillator Clock Period Counter        */

+#define FDCANCCU_CSTAT_TQC_Pos       (18U)

+#define FDCANCCU_CSTAT_TQC_Msk       (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)       /*!< 0x1FFC0000 */

+#define FDCANCCU_CSTAT_TQC           FDCANCCU_CSTAT_TQC_Msk                    /*!<Time Quanta Counter                    */

+#define FDCANCCU_CSTAT_CALS_Pos      (30U)

+#define FDCANCCU_CSTAT_CALS_Msk      (0x3UL << FDCANCCU_CSTAT_CALS_Pos)        /*!< 0xC0000000 */

+#define FDCANCCU_CSTAT_CALS          FDCANCCU_CSTAT_CALS_Msk                   /*!<Calibration State                      */

+

+/******************  Bit definition for FDCANCCU_CWD register  ******************/

+#define FDCANCCU_CWD_WDC_Pos         (0U)

+#define FDCANCCU_CWD_WDC_Msk         (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)        /*!< 0x0000FFFF */

+#define FDCANCCU_CWD_WDC             FDCANCCU_CWD_WDC_Msk                      /*!<Watchdog Configuration                 */

+#define FDCANCCU_CWD_WDV_Pos         (16U)

+#define FDCANCCU_CWD_WDV_Msk         (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)        /*!< 0xFFFF0000 */

+#define FDCANCCU_CWD_WDV             FDCANCCU_CWD_WDV_Msk                      /*!<Watchdog Value                         */

+

+/******************  Bit definition for FDCANCCU_IR register  *******************/

+#define FDCANCCU_IR_CWE_Pos          (0U)

+#define FDCANCCU_IR_CWE_Msk          (0x1UL << FDCANCCU_IR_CWE_Pos)            /*!< 0x00000001 */

+#define FDCANCCU_IR_CWE              FDCANCCU_IR_CWE_Msk                       /*!<Calibration Watchdog Event             */

+#define FDCANCCU_IR_CSC_Pos          (1U)

+#define FDCANCCU_IR_CSC_Msk          (0x1UL << FDCANCCU_IR_CSC_Pos)            /*!< 0x00000002 */

+#define FDCANCCU_IR_CSC              FDCANCCU_IR_CSC_Msk                       /*!<Calibration State Changed              */

+

+/******************  Bit definition for FDCANCCU_IE register  *******************/

+#define FDCANCCU_IE_CWEE_Pos         (0U)

+#define FDCANCCU_IE_CWEE_Msk         (0x1UL << FDCANCCU_IE_CWEE_Pos)           /*!< 0x00000001 */

+#define FDCANCCU_IE_CWEE             FDCANCCU_IE_CWEE_Msk                      /*!<Calibration Watchdog Event Enable      */

+#define FDCANCCU_IE_CSCE_Pos         (1U)

+#define FDCANCCU_IE_CSCE_Msk         (0x1UL << FDCANCCU_IE_CSCE_Pos)           /*!< 0x00000002 */

+#define FDCANCCU_IE_CSCE             FDCANCCU_IE_CSCE_Msk                      /*!<Calibration State Changed Enable       */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          HDMI-CEC (CEC)                                    */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for CEC_CR register  *********************/

+#define CEC_CR_CECEN_Pos         (0U)

+#define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                   /*!< 0x00000001 */

+#define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                                */

+#define CEC_CR_TXSOM_Pos         (1U)

+#define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                   /*!< 0x00000002 */

+#define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message                   */

+#define CEC_CR_TXEOM_Pos         (2U)

+#define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                   /*!< 0x00000004 */

+#define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message                     */

+

+/*******************  Bit definition for CEC_CFGR register  *******************/

+#define CEC_CFGR_SFT_Pos         (0U)

+#define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                   /*!< 0x00000007 */

+#define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time                      */

+#define CEC_CFGR_RXTOL_Pos       (3U)

+#define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                 /*!< 0x00000008 */

+#define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                             */

+#define CEC_CFGR_BRESTP_Pos      (4U)

+#define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                /*!< 0x00000010 */

+#define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                               */

+#define CEC_CFGR_BREGEN_Pos      (5U)

+#define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                /*!< 0x00000020 */

+#define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation           */

+#define CEC_CFGR_LBPEGEN_Pos     (6U)

+#define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)               /*!< 0x00000040 */

+#define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error generation      */

+#define CEC_CFGR_SFTOPT_Pos      (8U)

+#define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                /*!< 0x00000100 */

+#define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional             */

+#define CEC_CFGR_BRDNOGEN_Pos    (7U)

+#define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)              /*!< 0x00000080 */

+#define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No error generation         */

+#define CEC_CFGR_OAR_Pos         (16U)

+#define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                /*!< 0x7FFF0000 */

+#define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                           */

+#define CEC_CFGR_LSTN_Pos        (31U)

+#define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                  /*!< 0x80000000 */

+#define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                           */

+

+/*******************  Bit definition for CEC_TXDR register  *******************/

+#define CEC_TXDR_TXD_Pos         (0U)

+#define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                  /*!< 0x000000FF */

+#define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                               */

+

+/*******************  Bit definition for CEC_RXDR register  *******************/

+#define CEC_RXDR_RXD_Pos         (0U)

+#define CEC_RXDR_RXD_Msk         (0xFFUL << CEC_RXDR_RXD_Pos)                  /*!< 0x000000FF */

+#define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                              /*!< CEC Rx Data                               */

+

+/*******************  Bit definition for CEC_ISR register  ********************/

+#define CEC_ISR_RXBR_Pos         (0U)

+#define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                   /*!< 0x00000001 */

+#define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                      */

+#define CEC_ISR_RXEND_Pos        (1U)

+#define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                  /*!< 0x00000002 */

+#define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                      */

+#define CEC_ISR_RXOVR_Pos        (2U)

+#define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                  /*!< 0x00000004 */

+#define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                            */

+#define CEC_ISR_BRE_Pos          (3U)

+#define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                    /*!< 0x00000008 */

+#define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                   */

+#define CEC_ISR_SBPE_Pos         (4U)

+#define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                   /*!< 0x00000010 */

+#define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error             */

+#define CEC_ISR_LBPE_Pos         (5U)

+#define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                   /*!< 0x00000020 */

+#define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error              */

+#define CEC_ISR_RXACKE_Pos       (6U)

+#define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                 /*!< 0x00000040 */

+#define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge                */

+#define CEC_ISR_ARBLST_Pos       (7U)

+#define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                 /*!< 0x00000080 */

+#define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                      */

+#define CEC_ISR_TXBR_Pos         (8U)

+#define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                   /*!< 0x00000100 */

+#define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                       */

+#define CEC_ISR_TXEND_Pos        (9U)

+#define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                  /*!< 0x00000200 */

+#define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                   */

+#define CEC_ISR_TXUDR_Pos        (10U)

+#define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                  /*!< 0x00000400 */

+#define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                    */

+#define CEC_ISR_TXERR_Pos        (11U)

+#define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                  /*!< 0x00000800 */

+#define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                              */

+#define CEC_ISR_TXACKE_Pos       (12U)

+#define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                 /*!< 0x00001000 */

+#define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge                */

+

+/*******************  Bit definition for CEC_IER register  ********************/

+#define CEC_IER_RXBRIE_Pos       (0U)

+#define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                 /*!< 0x00000001 */

+#define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable            */

+#define CEC_IER_RXENDIE_Pos      (1U)

+#define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                /*!< 0x00000002 */

+#define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable            */

+#define CEC_IER_RXOVRIE_Pos      (2U)

+#define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                /*!< 0x00000004 */

+#define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable                  */

+#define CEC_IER_BREIE_Pos        (3U)

+#define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                  /*!< 0x00000008 */

+#define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable         */

+#define CEC_IER_SBPEIE_Pos       (4U)

+#define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                 /*!< 0x00000010 */

+#define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable   */

+#define CEC_IER_LBPEIE_Pos       (5U)

+#define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                 /*!< 0x00000020 */

+#define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable    */

+#define CEC_IER_RXACKEIE_Pos     (6U)

+#define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)               /*!< 0x00000040 */

+#define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable      */

+#define CEC_IER_ARBLSTIE_Pos     (7U)

+#define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)               /*!< 0x00000080 */

+#define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable            */

+#define CEC_IER_TXBRIE_Pos       (8U)

+#define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                 /*!< 0x00000100 */

+#define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable            */

+#define CEC_IER_TXENDIE_Pos      (9U)

+#define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                /*!< 0x00000200 */

+#define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable         */

+#define CEC_IER_TXUDRIE_Pos      (10U)

+#define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                /*!< 0x00000400 */

+#define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable          */

+#define CEC_IER_TXERRIE_Pos      (11U)

+#define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                /*!< 0x00000800 */

+#define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                    */

+#define CEC_IER_TXACKEIE_Pos     (12U)

+#define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)               /*!< 0x00001000 */

+#define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable      */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          CRC calculation unit                              */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for CRC_DR register  *********************/

+#define CRC_DR_DR_Pos            (0U)

+#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */

+#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */

+

+/*******************  Bit definition for CRC_IDR register  ********************/

+#define CRC_IDR_IDR_Pos          (0U)

+#define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */

+#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */

+

+/********************  Bit definition for CRC_CR register  ********************/

+#define CRC_CR_RESET_Pos         (0U)

+#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */

+#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */

+#define CRC_CR_POLYSIZE_Pos      (3U)

+#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */

+#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */

+#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */

+#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */

+#define CRC_CR_REV_IN_Pos        (5U)

+#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */

+#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */

+#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */

+#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */

+#define CRC_CR_REV_OUT_Pos       (7U)

+#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */

+#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */

+

+/*******************  Bit definition for CRC_INIT register  *******************/

+#define CRC_INIT_INIT_Pos        (0U)

+#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */

+#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */

+

+/*******************  Bit definition for CRC_POL register  ********************/

+#define CRC_POL_POL_Pos          (0U)

+#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */

+#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          CRS Clock Recovery System                         */

+/******************************************************************************/

+

+/*******************  Bit definition for CRS_CR register  *********************/

+#define CRS_CR_SYNCOKIE_Pos       (0U)

+#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */

+#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */

+#define CRS_CR_SYNCWARNIE_Pos     (1U)

+#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */

+#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */

+#define CRS_CR_ERRIE_Pos          (2U)

+#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */

+#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */

+#define CRS_CR_ESYNCIE_Pos        (3U)

+#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */

+#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */

+#define CRS_CR_CEN_Pos            (5U)

+#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */

+#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */

+#define CRS_CR_AUTOTRIMEN_Pos     (6U)

+#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */

+#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */

+#define CRS_CR_SWSYNC_Pos         (7U)

+#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */

+#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */

+#define CRS_CR_TRIM_Pos           (8U)

+#define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00003F00 */

+#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */

+

+/*******************  Bit definition for CRS_CFGR register  *********************/

+#define CRS_CFGR_RELOAD_Pos       (0U)

+#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */

+#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */

+#define CRS_CFGR_FELIM_Pos        (16U)

+#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */

+#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */

+

+#define CRS_CFGR_SYNCDIV_Pos      (24U)

+#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */

+#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */

+#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */

+#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */

+#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */

+

+#define CRS_CFGR_SYNCSRC_Pos      (28U)

+#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */

+#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */

+#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */

+#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */

+

+#define CRS_CFGR_SYNCPOL_Pos      (31U)

+#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */

+#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */

+

+/*******************  Bit definition for CRS_ISR register  *********************/

+#define CRS_ISR_SYNCOKF_Pos       (0U)

+#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */

+#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */

+#define CRS_ISR_SYNCWARNF_Pos     (1U)

+#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */

+#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */

+#define CRS_ISR_ERRF_Pos          (2U)

+#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */

+#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */

+#define CRS_ISR_ESYNCF_Pos        (3U)

+#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */

+#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */

+#define CRS_ISR_SYNCERR_Pos       (8U)

+#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */

+#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */

+#define CRS_ISR_SYNCMISS_Pos      (9U)

+#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */

+#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */

+#define CRS_ISR_TRIMOVF_Pos       (10U)

+#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */

+#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */

+#define CRS_ISR_FEDIR_Pos         (15U)

+#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */

+#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */

+#define CRS_ISR_FECAP_Pos         (16U)

+#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */

+#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */

+

+/*******************  Bit definition for CRS_ICR register  *********************/

+#define CRS_ICR_SYNCOKC_Pos       (0U)

+#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */

+#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */

+#define CRS_ICR_SYNCWARNC_Pos     (1U)

+#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */

+#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */

+#define CRS_ICR_ERRC_Pos          (2U)

+#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */

+#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */

+#define CRS_ICR_ESYNCC_Pos        (3U)

+#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */

+#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      Digital to Analog Converter                           */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for DAC_CR register  ********************/

+#define DAC_CR_EN1_Pos              (0U)

+#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */

+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */

+#define DAC_CR_TEN1_Pos             (1U)

+#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */

+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */

+

+#define DAC_CR_TSEL1_Pos            (2U)

+#define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */

+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */

+#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000004 */

+#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */

+#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */

+#define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */

+

+

+#define DAC_CR_WAVE1_Pos            (6U)

+#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */

+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */

+#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */

+#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */

+

+#define DAC_CR_MAMP1_Pos            (8U)

+#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */

+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */

+#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */

+#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */

+#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */

+#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */

+

+#define DAC_CR_DMAEN1_Pos           (12U)

+#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */

+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */

+#define DAC_CR_DMAUDRIE1_Pos        (13U)

+#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */

+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/

+#define DAC_CR_CEN1_Pos             (14U)

+#define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */

+#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/

+

+#define DAC_CR_EN2_Pos              (16U)

+#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */

+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */

+#define DAC_CR_TEN2_Pos             (17U)

+#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */

+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */

+

+#define DAC_CR_TSEL2_Pos            (18U)

+#define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */

+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */

+#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00040000 */

+#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */

+#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */

+#define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */

+

+

+#define DAC_CR_WAVE2_Pos            (22U)

+#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */

+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */

+#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */

+#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */

+

+#define DAC_CR_MAMP2_Pos            (24U)

+#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */

+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */

+#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */

+#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */

+#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */

+#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */

+

+#define DAC_CR_DMAEN2_Pos           (28U)

+#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */

+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */

+#define DAC_CR_DMAUDRIE2_Pos        (29U)

+#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */

+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/

+#define DAC_CR_CEN2_Pos             (30U)

+#define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */

+#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/

+

+/*****************  Bit definition for DAC_SWTRIGR register  ******************/

+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)

+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */

+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */

+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)

+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */

+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */

+

+/*****************  Bit definition for DAC_DHR12R1 register  ******************/

+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)

+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12L1 register  ******************/

+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)

+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8R1 register  ******************/

+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)

+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12R2 register  ******************/

+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)

+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12L2 register  ******************/

+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)

+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8R2 register  ******************/

+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)

+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12RD register  ******************/

+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)

+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */

+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)

+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */

+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12LD register  ******************/

+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)

+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */

+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)

+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */

+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8RD register  ******************/

+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)

+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */

+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)

+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */

+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */

+

+/*******************  Bit definition for DAC_DOR1 register  *******************/

+#define DAC_DOR1_DACC1DOR_Pos       (0U)

+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */

+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */

+

+/*******************  Bit definition for DAC_DOR2 register  *******************/

+#define DAC_DOR2_DACC2DOR_Pos       (0U)

+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */

+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */

+

+/********************  Bit definition for DAC_SR register  ********************/

+#define DAC_SR_DMAUDR1_Pos          (13U)

+#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */

+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */

+#define DAC_SR_CAL_FLAG1_Pos        (14U)

+#define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */

+#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */

+#define DAC_SR_BWST1_Pos            (15U)

+#define DAC_SR_BWST1_Msk            (0x4001UL << DAC_SR_BWST1_Pos)             /*!< 0x20008000 */

+#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */

+

+#define DAC_SR_DMAUDR2_Pos          (29U)

+#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */

+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */

+#define DAC_SR_CAL_FLAG2_Pos        (30U)

+#define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */

+#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */

+#define DAC_SR_BWST2_Pos            (31U)

+#define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */

+#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */

+

+/*******************  Bit definition for DAC_CCR register  ********************/

+#define DAC_CCR_OTRIM1_Pos          (0U)

+#define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */

+#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */

+#define DAC_CCR_OTRIM2_Pos          (16U)

+#define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */

+#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */

+

+/*******************  Bit definition for DAC_MCR register  *******************/

+#define DAC_MCR_MODE1_Pos           (0U)

+#define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */

+#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */

+#define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */

+#define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */

+#define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */

+

+#define DAC_MCR_MODE2_Pos           (16U)

+#define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */

+#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */

+#define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */

+#define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */

+#define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */

+

+/******************  Bit definition for DAC_SHSR1 register  ******************/

+#define DAC_SHSR1_TSAMPLE1_Pos      (0U)

+#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */

+#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */

+

+/******************  Bit definition for DAC_SHSR2 register  ******************/

+#define DAC_SHSR2_TSAMPLE2_Pos      (0U)

+#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */

+#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */

+

+/******************  Bit definition for DAC_SHHR register  ******************/

+#define DAC_SHHR_THOLD1_Pos         (0U)

+#define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */

+#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */

+#define DAC_SHHR_THOLD2_Pos         (16U)

+#define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */

+#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */

+

+/******************  Bit definition for DAC_SHRR register  ******************/

+#define DAC_SHRR_TREFRESH1_Pos      (0U)

+#define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */

+#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */

+#define DAC_SHRR_TREFRESH2_Pos      (16U)

+#define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */

+#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    DCMI                                    */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DCMI_CR register  ******************/

+#define DCMI_CR_CAPTURE_Pos        (0U)

+#define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)              /*!< 0x00000001 */

+#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk

+#define DCMI_CR_CM_Pos             (1U)

+#define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                   /*!< 0x00000002 */

+#define DCMI_CR_CM                 DCMI_CR_CM_Msk

+#define DCMI_CR_CROP_Pos           (2U)

+#define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                 /*!< 0x00000004 */

+#define DCMI_CR_CROP               DCMI_CR_CROP_Msk

+#define DCMI_CR_JPEG_Pos           (3U)

+#define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                 /*!< 0x00000008 */

+#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk

+#define DCMI_CR_ESS_Pos            (4U)

+#define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                  /*!< 0x00000010 */

+#define DCMI_CR_ESS                DCMI_CR_ESS_Msk

+#define DCMI_CR_PCKPOL_Pos         (5U)

+#define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)               /*!< 0x00000020 */

+#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk

+#define DCMI_CR_HSPOL_Pos          (6U)

+#define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                /*!< 0x00000040 */

+#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk

+#define DCMI_CR_VSPOL_Pos          (7U)

+#define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */

+#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk

+#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)

+#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)

+#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)

+#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)

+#define DCMI_CR_CRE_Pos            (12U)

+#define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */

+#define DCMI_CR_CRE                DCMI_CR_CRE_Msk

+#define DCMI_CR_ENABLE_Pos         (14U)

+#define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)               /*!< 0x00004000 */

+#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk

+#define DCMI_CR_BSM_Pos            (16U)

+#define DCMI_CR_BSM_Msk            (0x3UL << DCMI_CR_BSM_Pos)                  /*!< 0x00030000 */

+#define DCMI_CR_BSM                DCMI_CR_BSM_Msk

+#define DCMI_CR_BSM_0              (0x1UL << DCMI_CR_BSM_Pos)                   /*!< 0x00010000 */

+#define DCMI_CR_BSM_1              (0x2UL << DCMI_CR_BSM_Pos)                   /*!< 0x00020000 */

+#define DCMI_CR_OEBS_Pos           (18U)

+#define DCMI_CR_OEBS_Msk           (0x1UL << DCMI_CR_OEBS_Pos)                 /*!< 0x00040000 */

+#define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk

+#define DCMI_CR_LSM_Pos            (19U)

+#define DCMI_CR_LSM_Msk            (0x1UL << DCMI_CR_LSM_Pos)                  /*!< 0x00080000 */

+#define DCMI_CR_LSM                DCMI_CR_LSM_Msk

+#define DCMI_CR_OELS_Pos           (20U)

+#define DCMI_CR_OELS_Msk           (0x1UL << DCMI_CR_OELS_Pos)                 /*!< 0x00100000 */

+#define DCMI_CR_OELS               DCMI_CR_OELS_Msk

+

+/********************  Bits definition for DCMI_SR register  ******************/

+#define DCMI_SR_HSYNC_Pos          (0U)

+#define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                /*!< 0x00000001 */

+#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk

+#define DCMI_SR_VSYNC_Pos          (1U)

+#define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                /*!< 0x00000002 */

+#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk

+#define DCMI_SR_FNE_Pos            (2U)

+#define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                  /*!< 0x00000004 */

+#define DCMI_SR_FNE                DCMI_SR_FNE_Msk

+

+/********************  Bits definition for DCMI_RIS register   ****************/

+#define DCMI_RIS_FRAME_RIS_Pos     (0U)

+#define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)           /*!< 0x00000001 */

+#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk

+#define DCMI_RIS_OVR_RIS_Pos       (1U)

+#define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)             /*!< 0x00000002 */

+#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk

+#define DCMI_RIS_ERR_RIS_Pos       (2U)

+#define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)             /*!< 0x00000004 */

+#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk

+#define DCMI_RIS_VSYNC_RIS_Pos     (3U)

+#define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)           /*!< 0x00000008 */

+#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk

+#define DCMI_RIS_LINE_RIS_Pos      (4U)

+#define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)            /*!< 0x00000010 */

+#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk

+

+/********************  Bits definition for DCMI_IER register  *****************/

+#define DCMI_IER_FRAME_IE_Pos      (0U)

+#define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)            /*!< 0x00000001 */

+#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk

+#define DCMI_IER_OVR_IE_Pos        (1U)

+#define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)              /*!< 0x00000002 */

+#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk

+#define DCMI_IER_ERR_IE_Pos        (2U)

+#define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)              /*!< 0x00000004 */

+#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk

+#define DCMI_IER_VSYNC_IE_Pos      (3U)

+#define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)            /*!< 0x00000008 */

+#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk

+#define DCMI_IER_LINE_IE_Pos       (4U)

+#define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)             /*!< 0x00000010 */

+#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk

+

+

+/********************  Bits definition for DCMI_MIS register  *****************/

+#define DCMI_MIS_FRAME_MIS_Pos     (0U)

+#define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)           /*!< 0x00000001 */

+#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk

+#define DCMI_MIS_OVR_MIS_Pos       (1U)

+#define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)             /*!< 0x00000002 */

+#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk

+#define DCMI_MIS_ERR_MIS_Pos       (2U)

+#define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)             /*!< 0x00000004 */

+#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk

+#define DCMI_MIS_VSYNC_MIS_Pos     (3U)

+#define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)           /*!< 0x00000008 */

+#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk

+#define DCMI_MIS_LINE_MIS_Pos      (4U)

+#define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)            /*!< 0x00000010 */

+#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk

+

+

+/********************  Bits definition for DCMI_ICR register  *****************/

+#define DCMI_ICR_FRAME_ISC_Pos     (0U)

+#define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)           /*!< 0x00000001 */

+#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk

+#define DCMI_ICR_OVR_ISC_Pos       (1U)

+#define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)             /*!< 0x00000002 */

+#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk

+#define DCMI_ICR_ERR_ISC_Pos       (2U)

+#define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)             /*!< 0x00000004 */

+#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk

+#define DCMI_ICR_VSYNC_ISC_Pos     (3U)

+#define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)           /*!< 0x00000008 */

+#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk

+#define DCMI_ICR_LINE_ISC_Pos      (4U)

+#define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)            /*!< 0x00000010 */

+#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk

+

+

+/********************  Bits definition for DCMI_ESCR register  ******************/

+#define DCMI_ESCR_FSC_Pos          (0U)

+#define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)               /*!< 0x000000FF */

+#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk

+#define DCMI_ESCR_LSC_Pos          (8U)

+#define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)               /*!< 0x0000FF00 */

+#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk

+#define DCMI_ESCR_LEC_Pos          (16U)

+#define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)               /*!< 0x00FF0000 */

+#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk

+#define DCMI_ESCR_FEC_Pos          (24U)

+#define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)               /*!< 0xFF000000 */

+#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk

+

+/********************  Bits definition for DCMI_ESUR register  ******************/

+#define DCMI_ESUR_FSU_Pos          (0U)

+#define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)               /*!< 0x000000FF */

+#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk

+#define DCMI_ESUR_LSU_Pos          (8U)

+#define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)               /*!< 0x0000FF00 */

+#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk

+#define DCMI_ESUR_LEU_Pos          (16U)

+#define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)               /*!< 0x00FF0000 */

+#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk

+#define DCMI_ESUR_FEU_Pos          (24U)

+#define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)               /*!< 0xFF000000 */

+#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk

+

+/********************  Bits definition for DCMI_CWSTRT register  ******************/

+#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)

+#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)       /*!< 0x00003FFF */

+#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk

+#define DCMI_CWSTRT_VST_Pos        (16U)

+#define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)           /*!< 0x1FFF0000 */

+#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk

+

+/********************  Bits definition for DCMI_CWSIZE register  ******************/

+#define DCMI_CWSIZE_CAPCNT_Pos     (0U)

+#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)        /*!< 0x00003FFF */

+#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk

+#define DCMI_CWSIZE_VLINE_Pos      (16U)

+#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)         /*!< 0x3FFF0000 */

+#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk

+

+/********************  Bits definition for DCMI_DR register  ******************/

+#define DCMI_DR_BYTE0_Pos          (0U)

+#define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)               /*!< 0x000000FF */

+#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk

+#define DCMI_DR_BYTE1_Pos          (8U)

+#define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)               /*!< 0x0000FF00 */

+#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk

+#define DCMI_DR_BYTE2_Pos          (16U)

+#define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)               /*!< 0x00FF0000 */

+#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk

+#define DCMI_DR_BYTE3_Pos          (24U)

+#define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)               /*!< 0xFF000000 */

+#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                 Digital Filter for Sigma Delta Modulators                  */

+/*                                                                            */

+/******************************************************************************/

+

+/****************   DFSDM channel configuration registers  ********************/

+

+/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/

+#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)

+#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)   /*!< 0x80000000 */

+#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */

+#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)

+#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)  /*!< 0x40000000 */

+#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */

+#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)

+#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */

+#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */

+#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)

+#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x0000C000 */

+#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */

+#define DFSDM_CHCFGR1_DATPACK_1         (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */

+#define DFSDM_CHCFGR1_DATPACK_0         (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */

+#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)

+#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00003000 */

+#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */

+#define DFSDM_CHCFGR1_DATMPX_1          (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */

+#define DFSDM_CHCFGR1_DATMPX_0          (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */

+#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)

+#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)   /*!< 0x00000100 */

+#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */

+#define DFSDM_CHCFGR1_CHEN_Pos          (7U)

+#define DFSDM_CHCFGR1_CHEN_Msk          (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)      /*!< 0x00000080 */

+#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */

+#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)

+#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)    /*!< 0x00000040 */

+#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */

+#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)

+#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)     /*!< 0x00000020 */

+#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */

+#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)

+#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x0000000C */

+#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */

+#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */

+#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */

+#define DFSDM_CHCFGR1_SITP_Pos          (0U)

+#define DFSDM_CHCFGR1_SITP_Msk          (0x3UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000003 */

+#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */

+#define DFSDM_CHCFGR1_SITP_1            (0x2UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */

+#define DFSDM_CHCFGR1_SITP_0            (0x1UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */

+

+/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/

+#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)

+#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */

+#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)

+#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)    /*!< 0x000000F8 */

+#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */

+

+/******************  Bit definition for DFSDM_CHAWSCDR register *****************/

+#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)

+#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00C00000 */

+#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */

+#define DFSDM_CHAWSCDR_AWFORD_1         (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */

+#define DFSDM_CHAWSCDR_AWFORD_0         (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */

+#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)

+#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)  /*!< 0x001F0000 */

+#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */

+#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)

+#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)    /*!< 0x0000F000 */

+#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */

+#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)

+#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)    /*!< 0x000000FF */

+#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */

+

+/****************  Bit definition for DFSDM_CHWDATR register *******************/

+#define DFSDM_CHWDATR_WDATA_Pos         (0U)

+#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)  /*!< 0x0000FFFF */

+#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */

+

+/****************  Bit definition for DFSDM_CHDATINR register *****************/

+#define DFSDM_CHDATINR_INDAT0_Pos       (0U)

+#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */

+#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */

+#define DFSDM_CHDATINR_INDAT1_Pos       (16U)

+#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */

+#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */

+

+/************************   DFSDM module registers  ****************************/

+

+/********************  Bit definition for DFSDM_FLTCR1 register *******************/

+#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)

+#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)     /*!< 0x40000000 */

+#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */

+#define DFSDM_FLTCR1_FAST_Pos           (29U)

+#define DFSDM_FLTCR1_FAST_Msk           (0x1UL << DFSDM_FLTCR1_FAST_Pos)       /*!< 0x20000000 */

+#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */

+#define DFSDM_FLTCR1_RCH_Pos            (24U)

+#define DFSDM_FLTCR1_RCH_Msk            (0x7UL << DFSDM_FLTCR1_RCH_Pos)        /*!< 0x07000000 */

+#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */

+#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)

+#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)     /*!< 0x00200000 */

+#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */

+#define DFSDM_FLTCR1_RSYNC_Pos          (19U)

+#define DFSDM_FLTCR1_RSYNC_Msk          (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)      /*!< 0x00080000 */

+#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */

+#define DFSDM_FLTCR1_RCONT_Pos          (18U)

+#define DFSDM_FLTCR1_RCONT_Msk          (0x1UL << DFSDM_FLTCR1_RCONT_Pos)      /*!< 0x00040000 */

+#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */

+#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)

+#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)   /*!< 0x00020000 */

+#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */

+#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)

+#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00006000 */

+#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */

+#define DFSDM_FLTCR1_JEXTEN_1           (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */

+#define DFSDM_FLTCR1_JEXTEN_0           (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */

+#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)

+#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)   /*!< 0x00001F00 */

+#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */

+#define DFSDM_FLTCR1_JEXTSEL_0          (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000100 */

+#define DFSDM_FLTCR1_JEXTSEL_1          (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000200 */

+#define DFSDM_FLTCR1_JEXTSEL_2          (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000400 */

+#define DFSDM_FLTCR1_JEXTSEL_3          (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000800 */

+#define DFSDM_FLTCR1_JEXTSEL_4          (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00001000 */

+

+#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)

+#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)     /*!< 0x00000020 */

+#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */

+#define DFSDM_FLTCR1_JSCAN_Pos          (4U)

+#define DFSDM_FLTCR1_JSCAN_Msk          (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)      /*!< 0x00000010 */

+#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */

+#define DFSDM_FLTCR1_JSYNC_Pos          (3U)

+#define DFSDM_FLTCR1_JSYNC_Msk          (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)      /*!< 0x00000008 */

+#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */

+#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)

+#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)   /*!< 0x00000002 */

+#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */

+#define DFSDM_FLTCR1_DFEN_Pos           (0U)

+#define DFSDM_FLTCR1_DFEN_Msk           (0x1UL << DFSDM_FLTCR1_DFEN_Pos)       /*!< 0x00000001 */

+#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */

+

+/********************  Bit definition for DFSDM_FLTCR2 register *******************/

+#define DFSDM_FLTCR2_AWDCH_Pos          (16U)

+#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)     /*!< 0x00FF0000 */

+#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */

+#define DFSDM_FLTCR2_EXCH_Pos           (8U)

+#define DFSDM_FLTCR2_EXCH_Msk           (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)      /*!< 0x0000FF00 */

+#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */

+#define DFSDM_FLTCR2_CKABIE_Pos         (6U)

+#define DFSDM_FLTCR2_CKABIE_Msk         (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)     /*!< 0x00000040 */

+#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */

+#define DFSDM_FLTCR2_SCDIE_Pos          (5U)

+#define DFSDM_FLTCR2_SCDIE_Msk          (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)      /*!< 0x00000020 */

+#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */

+#define DFSDM_FLTCR2_AWDIE_Pos          (4U)

+#define DFSDM_FLTCR2_AWDIE_Msk          (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)      /*!< 0x00000010 */

+#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */

+#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)

+#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)     /*!< 0x00000008 */

+#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */

+#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)

+#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)     /*!< 0x00000004 */

+#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */

+#define DFSDM_FLTCR2_REOCIE_Pos         (1U)

+#define DFSDM_FLTCR2_REOCIE_Msk         (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)     /*!< 0x00000002 */

+#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */

+#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)

+#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)     /*!< 0x00000001 */

+#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */

+

+/********************  Bit definition for DFSDM_FLTISR register *******************/

+#define DFSDM_FLTISR_SCDF_Pos           (24U)

+#define DFSDM_FLTISR_SCDF_Msk           (0xFFUL << DFSDM_FLTISR_SCDF_Pos)      /*!< 0xFF000000 */

+#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */

+#define DFSDM_FLTISR_CKABF_Pos          (16U)

+#define DFSDM_FLTISR_CKABF_Msk          (0xFFUL << DFSDM_FLTISR_CKABF_Pos)     /*!< 0x00FF0000 */

+#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */

+#define DFSDM_FLTISR_RCIP_Pos           (14U)

+#define DFSDM_FLTISR_RCIP_Msk           (0x1UL << DFSDM_FLTISR_RCIP_Pos)       /*!< 0x00004000 */

+#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */

+#define DFSDM_FLTISR_JCIP_Pos           (13U)

+#define DFSDM_FLTISR_JCIP_Msk           (0x1UL << DFSDM_FLTISR_JCIP_Pos)       /*!< 0x00002000 */

+#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */

+#define DFSDM_FLTISR_AWDF_Pos           (4U)

+#define DFSDM_FLTISR_AWDF_Msk           (0x1UL << DFSDM_FLTISR_AWDF_Pos)       /*!< 0x00000010 */

+#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */

+#define DFSDM_FLTISR_ROVRF_Pos          (3U)

+#define DFSDM_FLTISR_ROVRF_Msk          (0x1UL << DFSDM_FLTISR_ROVRF_Pos)      /*!< 0x00000008 */

+#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */

+#define DFSDM_FLTISR_JOVRF_Pos          (2U)

+#define DFSDM_FLTISR_JOVRF_Msk          (0x1UL << DFSDM_FLTISR_JOVRF_Pos)      /*!< 0x00000004 */

+#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */

+#define DFSDM_FLTISR_REOCF_Pos          (1U)

+#define DFSDM_FLTISR_REOCF_Msk          (0x1UL << DFSDM_FLTISR_REOCF_Pos)      /*!< 0x00000002 */

+#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */

+#define DFSDM_FLTISR_JEOCF_Pos          (0U)

+#define DFSDM_FLTISR_JEOCF_Msk          (0x1UL << DFSDM_FLTISR_JEOCF_Pos)      /*!< 0x00000001 */

+#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */

+

+/********************  Bit definition for DFSDM_FLTICR register *******************/

+#define DFSDM_FLTICR_CLRSCDF_Pos        (24U)

+#define DFSDM_FLTICR_CLRSCDF_Msk        (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)   /*!< 0xFF000000 */

+#define DFSDM_FLTICR_CLRSCDF            DFSDM_FLTICR_CLRSCDF_Msk               /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */

+#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)

+#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)  /*!< 0x00FF0000 */

+#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */

+#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)

+#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)   /*!< 0x00000008 */

+#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */

+#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)

+#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)   /*!< 0x00000004 */

+#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */

+

+/*******************  Bit definition for DFSDM_FLTJCHGR register ******************/

+#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)

+#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)    /*!< 0x000000FF */

+#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */

+

+/********************  Bit definition for DFSDM_FLTFCR register *******************/

+#define DFSDM_FLTFCR_FORD_Pos           (29U)

+#define DFSDM_FLTFCR_FORD_Msk           (0x7UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0xE0000000 */

+#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */

+#define DFSDM_FLTFCR_FORD_2             (0x4UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */

+#define DFSDM_FLTFCR_FORD_1             (0x2UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */

+#define DFSDM_FLTFCR_FORD_0             (0x1UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */

+#define DFSDM_FLTFCR_FOSR_Pos           (16U)

+#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)     /*!< 0x03FF0000 */

+#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */

+#define DFSDM_FLTFCR_IOSR_Pos           (0U)

+#define DFSDM_FLTFCR_IOSR_Msk           (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)      /*!< 0x000000FF */

+#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */

+

+/******************  Bit definition for DFSDM_FLTJDATAR register *****************/

+#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)

+#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */

+#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)

+#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */

+#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */

+

+/******************  Bit definition for DFSDM_FLTRDATAR register *****************/

+#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)

+#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */

+#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)

+#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)   /*!< 0x00000010 */

+#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */

+#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)

+#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */

+#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */

+

+/******************  Bit definition for DFSDM_FLTAWHTR register ******************/

+#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)

+#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */

+#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)

+#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)    /*!< 0x0000000F */

+#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */

+

+/******************  Bit definition for DFSDM_FLTAWLTR register ******************/

+#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)

+#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWHT[23:0] Analog watchdog low threshold */

+#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)

+#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)    /*!< 0x0000000F */

+#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */

+

+/******************  Bit definition for DFSDM_FLTAWSR register ******************/

+#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)

+#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)    /*!< 0x0000FF00 */

+#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */

+#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)

+#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)    /*!< 0x000000FF */

+#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */

+

+/******************  Bit definition for DFSDM_FLTAWCFR) register *****************/

+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)

+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */

+#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */

+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)

+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */

+#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */

+

+/******************  Bit definition for DFSDM_FLTEXMAX register ******************/

+#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)

+#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */

+#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)

+#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)  /*!< 0x00000007 */

+#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */

+

+/******************  Bit definition for DFSDM_FLTEXMIN register ******************/

+#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)

+#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */

+#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)

+#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)  /*!< 0x00000007 */

+#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */

+

+/******************  Bit definition for DFSDM_FLTCNVTIMR register ******************/

+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)

+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */

+#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           BDMA Controller                                  */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for BDMA_ISR register  ********************/

+#define BDMA_ISR_GIF0_Pos       (0U)

+#define BDMA_ISR_GIF0_Msk       (0x1UL << BDMA_ISR_GIF0_Pos)                   /*!< 0x00000001 */

+#define BDMA_ISR_GIF0           BDMA_ISR_GIF0_Msk                              /*!< Channel 0 Global interrupt flag */

+#define BDMA_ISR_TCIF0_Pos      (1U)

+#define BDMA_ISR_TCIF0_Msk      (0x1UL << BDMA_ISR_TCIF0_Pos)                  /*!< 0x00000002 */

+#define BDMA_ISR_TCIF0          BDMA_ISR_TCIF0_Msk                             /*!< Channel 0 Transfer Complete flag */

+#define BDMA_ISR_HTIF0_Pos      (2U)

+#define BDMA_ISR_HTIF0_Msk      (0x1UL << BDMA_ISR_HTIF0_Pos)                  /*!< 0x00000004 */

+#define BDMA_ISR_HTIF0          BDMA_ISR_HTIF0_Msk                             /*!< Channel 0 Half Transfer flag */

+#define BDMA_ISR_TEIF0_Pos      (3U)

+#define BDMA_ISR_TEIF0_Msk      (0x1UL << BDMA_ISR_TEIF0_Pos)                  /*!< 0x00000008 */

+#define BDMA_ISR_TEIF0          BDMA_ISR_TEIF0_Msk                             /*!< Channel 0 Transfer Error flag */

+#define BDMA_ISR_GIF1_Pos       (4U)

+#define BDMA_ISR_GIF1_Msk       (0x1UL << BDMA_ISR_GIF1_Pos)                   /*!< 0x00000010 */

+#define BDMA_ISR_GIF1           BDMA_ISR_GIF1_Msk                              /*!< Channel 1 Global interrupt flag */

+#define BDMA_ISR_TCIF1_Pos      (5U)

+#define BDMA_ISR_TCIF1_Msk      (0x1UL << BDMA_ISR_TCIF1_Pos)                  /*!< 0x00000020 */

+#define BDMA_ISR_TCIF1          BDMA_ISR_TCIF1_Msk                             /*!< Channel 1 Transfer Complete flag */

+#define BDMA_ISR_HTIF1_Pos      (6U)

+#define BDMA_ISR_HTIF1_Msk      (0x1UL << BDMA_ISR_HTIF1_Pos)                  /*!< 0x00000040 */

+#define BDMA_ISR_HTIF1          BDMA_ISR_HTIF1_Msk                             /*!< Channel 1 Half Transfer flag */

+#define BDMA_ISR_TEIF1_Pos      (7U)

+#define BDMA_ISR_TEIF1_Msk      (0x1UL << BDMA_ISR_TEIF1_Pos)                  /*!< 0x00000080 */

+#define BDMA_ISR_TEIF1          BDMA_ISR_TEIF1_Msk                             /*!< Channel 1 Transfer Error flag */

+#define BDMA_ISR_GIF2_Pos       (8U)

+#define BDMA_ISR_GIF2_Msk       (0x1UL << BDMA_ISR_GIF2_Pos)                   /*!< 0x00000100 */

+#define BDMA_ISR_GIF2           BDMA_ISR_GIF2_Msk                              /*!< Channel 2 Global interrupt flag */

+#define BDMA_ISR_TCIF2_Pos      (9U)

+#define BDMA_ISR_TCIF2_Msk      (0x1UL << BDMA_ISR_TCIF2_Pos)                  /*!< 0x00000200 */

+#define BDMA_ISR_TCIF2          BDMA_ISR_TCIF2_Msk                             /*!< Channel 2 Transfer Complete flag */

+#define BDMA_ISR_HTIF2_Pos      (10U)

+#define BDMA_ISR_HTIF2_Msk      (0x1UL << BDMA_ISR_HTIF2_Pos)                  /*!< 0x00000400 */

+#define BDMA_ISR_HTIF2          BDMA_ISR_HTIF2_Msk                             /*!< Channel 2 Half Transfer flag */

+#define BDMA_ISR_TEIF2_Pos      (11U)

+#define BDMA_ISR_TEIF2_Msk      (0x1UL << BDMA_ISR_TEIF2_Pos)                  /*!< 0x00000800 */

+#define BDMA_ISR_TEIF2          BDMA_ISR_TEIF2_Msk                             /*!< Channel 2 Transfer Error flag */

+#define BDMA_ISR_GIF3_Pos       (12U)

+#define BDMA_ISR_GIF3_Msk       (0x1UL << BDMA_ISR_GIF3_Pos)                   /*!< 0x00001000 */

+#define BDMA_ISR_GIF3           BDMA_ISR_GIF3_Msk                              /*!< Channel 3 Global interrupt flag */

+#define BDMA_ISR_TCIF3_Pos      (13U)

+#define BDMA_ISR_TCIF3_Msk      (0x1UL << BDMA_ISR_TCIF3_Pos)                  /*!< 0x00002000 */

+#define BDMA_ISR_TCIF3          BDMA_ISR_TCIF3_Msk                             /*!< Channel 3 Transfer Complete flag */

+#define BDMA_ISR_HTIF3_Pos      (14U)

+#define BDMA_ISR_HTIF3_Msk      (0x1UL << BDMA_ISR_HTIF3_Pos)                  /*!< 0x00004000 */

+#define BDMA_ISR_HTIF3          BDMA_ISR_HTIF3_Msk                             /*!< Channel 3 Half Transfer flag */

+#define BDMA_ISR_TEIF3_Pos      (15U)

+#define BDMA_ISR_TEIF3_Msk      (0x1UL << BDMA_ISR_TEIF3_Pos)                  /*!< 0x00008000 */

+#define BDMA_ISR_TEIF3          BDMA_ISR_TEIF3_Msk                             /*!< Channel 3 Transfer Error flag */

+#define BDMA_ISR_GIF4_Pos       (16U)

+#define BDMA_ISR_GIF4_Msk       (0x1UL << BDMA_ISR_GIF4_Pos)                   /*!< 0x00010000 */

+#define BDMA_ISR_GIF4           BDMA_ISR_GIF4_Msk                              /*!< Channel 4 Global interrupt flag */

+#define BDMA_ISR_TCIF4_Pos      (17U)

+#define BDMA_ISR_TCIF4_Msk      (0x1UL << BDMA_ISR_TCIF4_Pos)                  /*!< 0x00020000 */

+#define BDMA_ISR_TCIF4          BDMA_ISR_TCIF4_Msk                             /*!< Channel 4 Transfer Complete flag */

+#define BDMA_ISR_HTIF4_Pos      (18U)

+#define BDMA_ISR_HTIF4_Msk      (0x1UL << BDMA_ISR_HTIF4_Pos)                  /*!< 0x00040000 */

+#define BDMA_ISR_HTIF4          BDMA_ISR_HTIF4_Msk                             /*!< Channel 4 Half Transfer flag */

+#define BDMA_ISR_TEIF4_Pos      (19U)

+#define BDMA_ISR_TEIF4_Msk      (0x1UL << BDMA_ISR_TEIF4_Pos)                  /*!< 0x00080000 */

+#define BDMA_ISR_TEIF4          BDMA_ISR_TEIF4_Msk                             /*!< Channel 4 Transfer Error flag */

+#define BDMA_ISR_GIF5_Pos       (20U)

+#define BDMA_ISR_GIF5_Msk       (0x1UL << BDMA_ISR_GIF5_Pos)                   /*!< 0x00100000 */

+#define BDMA_ISR_GIF5           BDMA_ISR_GIF5_Msk                              /*!< Channel 5 Global interrupt flag */

+#define BDMA_ISR_TCIF5_Pos      (21U)

+#define BDMA_ISR_TCIF5_Msk      (0x1UL << BDMA_ISR_TCIF5_Pos)                  /*!< 0x00200000 */

+#define BDMA_ISR_TCIF5          BDMA_ISR_TCIF5_Msk                             /*!< Channel 5 Transfer Complete flag */

+#define BDMA_ISR_HTIF5_Pos      (22U)

+#define BDMA_ISR_HTIF5_Msk      (0x1UL << BDMA_ISR_HTIF5_Pos)                  /*!< 0x00400000 */

+#define BDMA_ISR_HTIF5          BDMA_ISR_HTIF5_Msk                             /*!< Channel 5 Half Transfer flag */

+#define BDMA_ISR_TEIF5_Pos      (23U)

+#define BDMA_ISR_TEIF5_Msk      (0x1UL << BDMA_ISR_TEIF5_Pos)                  /*!< 0x00800000 */

+#define BDMA_ISR_TEIF5          BDMA_ISR_TEIF5_Msk                             /*!< Channel 5 Transfer Error flag */

+#define BDMA_ISR_GIF6_Pos       (24U)

+#define BDMA_ISR_GIF6_Msk       (0x1UL << BDMA_ISR_GIF6_Pos)                   /*!< 0x01000000 */

+#define BDMA_ISR_GIF6           BDMA_ISR_GIF6_Msk                              /*!< Channel 6 Global interrupt flag */

+#define BDMA_ISR_TCIF6_Pos      (25U)

+#define BDMA_ISR_TCIF6_Msk      (0x1UL << BDMA_ISR_TCIF6_Pos)                  /*!< 0x02000000 */

+#define BDMA_ISR_TCIF6          BDMA_ISR_TCIF6_Msk                             /*!< Channel 6 Transfer Complete flag */

+#define BDMA_ISR_HTIF6_Pos      (26U)

+#define BDMA_ISR_HTIF6_Msk      (0x1UL << BDMA_ISR_HTIF6_Pos)                  /*!< 0x04000000 */

+#define BDMA_ISR_HTIF6          BDMA_ISR_HTIF6_Msk                             /*!< Channel 6 Half Transfer flag */

+#define BDMA_ISR_TEIF6_Pos      (27U)

+#define BDMA_ISR_TEIF6_Msk      (0x1UL << BDMA_ISR_TEIF6_Pos)                  /*!< 0x08000000 */

+#define BDMA_ISR_TEIF6          BDMA_ISR_TEIF6_Msk                             /*!< Channel 6 Transfer Error flag */

+#define BDMA_ISR_GIF7_Pos       (28U)

+#define BDMA_ISR_GIF7_Msk       (0x1UL << BDMA_ISR_GIF7_Pos)                   /*!< 0x10000000 */

+#define BDMA_ISR_GIF7           BDMA_ISR_GIF7_Msk                              /*!< Channel 7 Global interrupt flag */

+#define BDMA_ISR_TCIF7_Pos      (29U)

+#define BDMA_ISR_TCIF7_Msk      (0x1UL << BDMA_ISR_TCIF7_Pos)                  /*!< 0x20000000 */

+#define BDMA_ISR_TCIF7          BDMA_ISR_TCIF7_Msk                             /*!< Channel 7 Transfer Complete flag */

+#define BDMA_ISR_HTIF7_Pos      (30U)

+#define BDMA_ISR_HTIF7_Msk      (0x1UL << BDMA_ISR_HTIF7_Pos)                  /*!< 0x40000000 */

+#define BDMA_ISR_HTIF7          BDMA_ISR_HTIF7_Msk                             /*!< Channel 7 Half Transfer flag */

+#define BDMA_ISR_TEIF7_Pos      (31U)

+#define BDMA_ISR_TEIF7_Msk      (0x1UL << BDMA_ISR_TEIF7_Pos)                  /*!< 0x80000000 */

+#define BDMA_ISR_TEIF7          BDMA_ISR_TEIF7_Msk                             /*!< Channel 7 Transfer Error flag */

+

+/*******************  Bit definition for BDMA_IFCR register  *******************/

+#define BDMA_IFCR_CGIF0_Pos     (0U)

+#define BDMA_IFCR_CGIF0_Msk     (0x1UL << BDMA_IFCR_CGIF0_Pos)                 /*!< 0x00000001 */

+#define BDMA_IFCR_CGIF0         BDMA_IFCR_CGIF0_Msk                            /*!< Channel 0 Global interrupt clearr */

+#define BDMA_IFCR_CTCIF0_Pos    (1U)

+#define BDMA_IFCR_CTCIF0_Msk    (0x1UL << BDMA_IFCR_CTCIF0_Pos)                /*!< 0x00000002 */

+#define BDMA_IFCR_CTCIF0        BDMA_IFCR_CTCIF0_Msk                           /*!< Channel 0 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF0_Pos    (2U)

+#define BDMA_IFCR_CHTIF0_Msk    (0x1UL << BDMA_IFCR_CHTIF0_Pos)                /*!< 0x00000004 */

+#define BDMA_IFCR_CHTIF0        BDMA_IFCR_CHTIF0_Msk                           /*!< Channel 0 Half Transfer clear */

+#define BDMA_IFCR_CTEIF0_Pos    (3U)

+#define BDMA_IFCR_CTEIF0_Msk    (0x1UL << BDMA_IFCR_CTEIF0_Pos)                /*!< 0x00000008 */

+#define BDMA_IFCR_CTEIF0        BDMA_IFCR_CTEIF0_Msk                           /*!< Channel 0 Transfer Error clear */

+#define BDMA_IFCR_CGIF1_Pos     (4U)

+#define BDMA_IFCR_CGIF1_Msk     (0x1UL << BDMA_IFCR_CGIF1_Pos)                 /*!< 0x00000010 */

+#define BDMA_IFCR_CGIF1         BDMA_IFCR_CGIF1_Msk                            /*!< Channel 1 Global interrupt clear */

+#define BDMA_IFCR_CTCIF1_Pos    (5U)

+#define BDMA_IFCR_CTCIF1_Msk    (0x1UL << BDMA_IFCR_CTCIF1_Pos)                /*!< 0x00000020 */

+#define BDMA_IFCR_CTCIF1        BDMA_IFCR_CTCIF1_Msk                           /*!< Channel 1 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF1_Pos    (6U)

+#define BDMA_IFCR_CHTIF1_Msk    (0x1UL << BDMA_IFCR_CHTIF1_Pos)                /*!< 0x00000040 */

+#define BDMA_IFCR_CHTIF1        BDMA_IFCR_CHTIF1_Msk                           /*!< Channel 1 Half Transfer clear */

+#define BDMA_IFCR_CTEIF1_Pos    (7U)

+#define BDMA_IFCR_CTEIF1_Msk    (0x1UL << BDMA_IFCR_CTEIF1_Pos)                /*!< 0x00000080 */

+#define BDMA_IFCR_CTEIF1        BDMA_IFCR_CTEIF1_Msk                           /*!< Channel 1 Transfer Error clear */

+#define BDMA_IFCR_CGIF2_Pos     (8U)

+#define BDMA_IFCR_CGIF2_Msk     (0x1UL << BDMA_IFCR_CGIF2_Pos)                 /*!< 0x00000100 */

+#define BDMA_IFCR_CGIF2         BDMA_IFCR_CGIF2_Msk                            /*!< Channel 2 Global interrupt clear */

+#define BDMA_IFCR_CTCIF2_Pos    (9U)

+#define BDMA_IFCR_CTCIF2_Msk    (0x1UL << BDMA_IFCR_CTCIF2_Pos)                /*!< 0x00000200 */

+#define BDMA_IFCR_CTCIF2        BDMA_IFCR_CTCIF2_Msk                           /*!< Channel 2 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF2_Pos    (10U)

+#define BDMA_IFCR_CHTIF2_Msk    (0x1UL << BDMA_IFCR_CHTIF2_Pos)                /*!< 0x00000400 */

+#define BDMA_IFCR_CHTIF2        BDMA_IFCR_CHTIF2_Msk                           /*!< Channel 2 Half Transfer clear */

+#define BDMA_IFCR_CTEIF2_Pos    (11U)

+#define BDMA_IFCR_CTEIF2_Msk    (0x1UL << BDMA_IFCR_CTEIF2_Pos)                /*!< 0x00000800 */

+#define BDMA_IFCR_CTEIF2        BDMA_IFCR_CTEIF2_Msk                           /*!< Channel 2 Transfer Error clear */

+#define BDMA_IFCR_CGIF3_Pos     (12U)

+#define BDMA_IFCR_CGIF3_Msk     (0x1UL << BDMA_IFCR_CGIF3_Pos)                 /*!< 0x00001000 */

+#define BDMA_IFCR_CGIF3         BDMA_IFCR_CGIF3_Msk                            /*!< Channel 3 Global interrupt clear */

+#define BDMA_IFCR_CTCIF3_Pos    (13U)

+#define BDMA_IFCR_CTCIF3_Msk    (0x1UL << BDMA_IFCR_CTCIF3_Pos)                /*!< 0x00002000 */

+#define BDMA_IFCR_CTCIF3        BDMA_IFCR_CTCIF3_Msk                           /*!< Channel 3 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF3_Pos    (14U)

+#define BDMA_IFCR_CHTIF3_Msk    (0x1UL << BDMA_IFCR_CHTIF3_Pos)                /*!< 0x00004000 */

+#define BDMA_IFCR_CHTIF3        BDMA_IFCR_CHTIF3_Msk                           /*!< Channel 3 Half Transfer clear */

+#define BDMA_IFCR_CTEIF3_Pos    (15U)

+#define BDMA_IFCR_CTEIF3_Msk    (0x1UL << BDMA_IFCR_CTEIF3_Pos)                /*!< 0x00008000 */

+#define BDMA_IFCR_CTEIF3        BDMA_IFCR_CTEIF3_Msk                           /*!< Channel 3 Transfer Error clear */

+#define BDMA_IFCR_CGIF4_Pos     (16U)

+#define BDMA_IFCR_CGIF4_Msk     (0x1UL << BDMA_IFCR_CGIF4_Pos)                 /*!< 0x00010000 */

+#define BDMA_IFCR_CGIF4         BDMA_IFCR_CGIF4_Msk                            /*!< Channel 4 Global interrupt clear */

+#define BDMA_IFCR_CTCIF4_Pos    (17U)

+#define BDMA_IFCR_CTCIF4_Msk    (0x1UL << BDMA_IFCR_CTCIF4_Pos)                /*!< 0x00020000 */

+#define BDMA_IFCR_CTCIF4        BDMA_IFCR_CTCIF4_Msk                           /*!< Channel 4 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF4_Pos    (18U)

+#define BDMA_IFCR_CHTIF4_Msk    (0x1UL << BDMA_IFCR_CHTIF4_Pos)                /*!< 0x00040000 */

+#define BDMA_IFCR_CHTIF4        BDMA_IFCR_CHTIF4_Msk                           /*!< Channel 4 Half Transfer clear */

+#define BDMA_IFCR_CTEIF4_Pos    (19U)

+#define BDMA_IFCR_CTEIF4_Msk    (0x1UL << BDMA_IFCR_CTEIF4_Pos)                /*!< 0x00080000 */

+#define BDMA_IFCR_CTEIF4        BDMA_IFCR_CTEIF4_Msk                           /*!< Channel 4 Transfer Error clear */

+#define BDMA_IFCR_CGIF5_Pos     (20U)

+#define BDMA_IFCR_CGIF5_Msk     (0x1UL << BDMA_IFCR_CGIF5_Pos)                 /*!< 0x00100000 */

+#define BDMA_IFCR_CGIF5         BDMA_IFCR_CGIF5_Msk                            /*!< Channel 5 Global interrupt clear */

+#define BDMA_IFCR_CTCIF5_Pos    (21U)

+#define BDMA_IFCR_CTCIF5_Msk    (0x1UL << BDMA_IFCR_CTCIF5_Pos)                /*!< 0x00200000 */

+#define BDMA_IFCR_CTCIF5        BDMA_IFCR_CTCIF5_Msk                           /*!< Channel 5 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF5_Pos    (22U)

+#define BDMA_IFCR_CHTIF5_Msk    (0x1UL << BDMA_IFCR_CHTIF5_Pos)                /*!< 0x00400000 */

+#define BDMA_IFCR_CHTIF5        BDMA_IFCR_CHTIF5_Msk                           /*!< Channel 5 Half Transfer clear */

+#define BDMA_IFCR_CTEIF5_Pos    (23U)

+#define BDMA_IFCR_CTEIF5_Msk    (0x1UL << BDMA_IFCR_CTEIF5_Pos)                /*!< 0x00800000 */

+#define BDMA_IFCR_CTEIF5        BDMA_IFCR_CTEIF5_Msk                           /*!< Channel 5 Transfer Error clear */

+#define BDMA_IFCR_CGIF6_Pos     (24U)

+#define BDMA_IFCR_CGIF6_Msk     (0x1UL << BDMA_IFCR_CGIF6_Pos)                 /*!< 0x01000000 */

+#define BDMA_IFCR_CGIF6         BDMA_IFCR_CGIF6_Msk                            /*!< Channel 6 Global interrupt clear */

+#define BDMA_IFCR_CTCIF6_Pos    (25U)

+#define BDMA_IFCR_CTCIF6_Msk    (0x1UL << BDMA_IFCR_CTCIF6_Pos)                /*!< 0x02000000 */

+#define BDMA_IFCR_CTCIF6        BDMA_IFCR_CTCIF6_Msk                           /*!< Channel 6 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF6_Pos    (26U)

+#define BDMA_IFCR_CHTIF6_Msk    (0x1UL << BDMA_IFCR_CHTIF6_Pos)                /*!< 0x04000000 */

+#define BDMA_IFCR_CHTIF6        BDMA_IFCR_CHTIF6_Msk                           /*!< Channel 6 Half Transfer clear */

+#define BDMA_IFCR_CTEIF6_Pos    (27U)

+#define BDMA_IFCR_CTEIF6_Msk    (0x1UL << BDMA_IFCR_CTEIF6_Pos)                /*!< 0x08000000 */

+#define BDMA_IFCR_CTEIF6        BDMA_IFCR_CTEIF6_Msk                           /*!< Channel 6 Transfer Error clear */

+#define BDMA_IFCR_CGIF7_Pos     (28U)

+#define BDMA_IFCR_CGIF7_Msk     (0x1UL << BDMA_IFCR_CGIF7_Pos)                 /*!< 0x10000000 */

+#define BDMA_IFCR_CGIF7         BDMA_IFCR_CGIF7_Msk                            /*!< Channel 7 Global interrupt clear */

+#define BDMA_IFCR_CTCIF7_Pos    (29U)

+#define BDMA_IFCR_CTCIF7_Msk    (0x1UL << BDMA_IFCR_CTCIF7_Pos)                /*!< 0x20000000 */

+#define BDMA_IFCR_CTCIF7        BDMA_IFCR_CTCIF7_Msk                           /*!< Channel 7 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF7_Pos    (30U)

+#define BDMA_IFCR_CHTIF7_Msk    (0x1UL << BDMA_IFCR_CHTIF7_Pos)                /*!< 0x40000000 */

+#define BDMA_IFCR_CHTIF7        BDMA_IFCR_CHTIF7_Msk                           /*!< Channel 7 Half Transfer clear */

+#define BDMA_IFCR_CTEIF7_Pos    (31U)

+#define BDMA_IFCR_CTEIF7_Msk    (0x1UL << BDMA_IFCR_CTEIF7_Pos)                /*!< 0x80000000 */

+#define BDMA_IFCR_CTEIF7        BDMA_IFCR_CTEIF7_Msk                           /*!< Channel 7 Transfer Error clear */

+

+/*******************  Bit definition for BDMA_CCR register  ********************/

+#define BDMA_CCR_EN_Pos         (0U)

+#define BDMA_CCR_EN_Msk         (0x1UL << BDMA_CCR_EN_Pos)                     /*!< 0x00000001 */

+#define BDMA_CCR_EN             BDMA_CCR_EN_Msk                                /*!< Channel enable                      */

+#define BDMA_CCR_TCIE_Pos       (1U)

+#define BDMA_CCR_TCIE_Msk       (0x1UL << BDMA_CCR_TCIE_Pos)                   /*!< 0x00000002 */

+#define BDMA_CCR_TCIE           BDMA_CCR_TCIE_Msk                              /*!< Transfer complete interrupt enable  */

+#define BDMA_CCR_HTIE_Pos       (2U)

+#define BDMA_CCR_HTIE_Msk       (0x1UL << BDMA_CCR_HTIE_Pos)                   /*!< 0x00000004 */

+#define BDMA_CCR_HTIE           BDMA_CCR_HTIE_Msk                              /*!< Half Transfer interrupt enable      */

+#define BDMA_CCR_TEIE_Pos       (3U)

+#define BDMA_CCR_TEIE_Msk       (0x1UL << BDMA_CCR_TEIE_Pos)                   /*!< 0x00000008 */

+#define BDMA_CCR_TEIE           BDMA_CCR_TEIE_Msk                              /*!< Transfer error interrupt enable     */

+#define BDMA_CCR_DIR_Pos        (4U)

+#define BDMA_CCR_DIR_Msk        (0x1UL << BDMA_CCR_DIR_Pos)                    /*!< 0x00000010 */

+#define BDMA_CCR_DIR            BDMA_CCR_DIR_Msk                               /*!< Data transfer direction             */

+#define BDMA_CCR_CIRC_Pos       (5U)

+#define BDMA_CCR_CIRC_Msk       (0x1UL << BDMA_CCR_CIRC_Pos)                   /*!< 0x00000020 */

+#define BDMA_CCR_CIRC           BDMA_CCR_CIRC_Msk                              /*!< Circular mode                       */

+#define BDMA_CCR_PINC_Pos       (6U)

+#define BDMA_CCR_PINC_Msk       (0x1UL << BDMA_CCR_PINC_Pos)                   /*!< 0x00000040 */

+#define BDMA_CCR_PINC           BDMA_CCR_PINC_Msk                              /*!< Peripheral increment mode           */

+#define BDMA_CCR_MINC_Pos       (7U)

+#define BDMA_CCR_MINC_Msk       (0x1UL << BDMA_CCR_MINC_Pos)                   /*!< 0x00000080 */

+#define BDMA_CCR_MINC           BDMA_CCR_MINC_Msk                              /*!< Memory increment mode               */

+

+#define BDMA_CCR_PSIZE_Pos      (8U)

+#define BDMA_CCR_PSIZE_Msk      (0x3UL << BDMA_CCR_PSIZE_Pos)                  /*!< 0x00000300 */

+#define BDMA_CCR_PSIZE          BDMA_CCR_PSIZE_Msk                             /*!< PSIZE[1:0] bits (Peripheral size)   */

+#define BDMA_CCR_PSIZE_0        (0x1UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000100 */

+#define BDMA_CCR_PSIZE_1        (0x2UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000200 */

+

+#define BDMA_CCR_MSIZE_Pos      (10U)

+#define BDMA_CCR_MSIZE_Msk      (0x3UL << BDMA_CCR_MSIZE_Pos)                  /*!< 0x00000C00 */

+#define BDMA_CCR_MSIZE          BDMA_CCR_MSIZE_Msk                             /*!< MSIZE[1:0] bits (Memory size)       */

+#define BDMA_CCR_MSIZE_0        (0x1UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000400 */

+#define BDMA_CCR_MSIZE_1        (0x2UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000800 */

+

+#define BDMA_CCR_PL_Pos         (12U)

+#define BDMA_CCR_PL_Msk         (0x3UL << BDMA_CCR_PL_Pos)                     /*!< 0x00003000 */

+#define BDMA_CCR_PL             BDMA_CCR_PL_Msk                                /*!< PL[1:0] bits(Channel Priority level)*/

+#define BDMA_CCR_PL_0           (0x1UL << BDMA_CCR_PL_Pos)                      /*!< 0x00001000 */

+#define BDMA_CCR_PL_1           (0x2UL << BDMA_CCR_PL_Pos)                      /*!< 0x00002000 */

+

+#define BDMA_CCR_MEM2MEM_Pos    (14U)

+#define BDMA_CCR_MEM2MEM_Msk    (0x1UL << BDMA_CCR_MEM2MEM_Pos)                /*!< 0x00004000 */

+#define BDMA_CCR_MEM2MEM        BDMA_CCR_MEM2MEM_Msk                           /*!< Memory to memory mode               */

+#define BDMA_CCR_DBM_Pos        (15U)

+#define BDMA_CCR_DBM_Msk        (0x1UL << BDMA_CCR_DBM_Pos)                    /*!< 0x0000A000 */

+#define BDMA_CCR_DBM            BDMA_CCR_DBM_Msk                               /*!< Memory to memory mode               */

+#define BDMA_CCR_CT_Pos         (16U)

+#define BDMA_CCR_CT_Msk         (0x1UL << BDMA_CCR_CT_Pos)                     /*!< 0x00010000 */

+#define BDMA_CCR_CT             BDMA_CCR_CT_Msk                                /*!< Memory to memory mode               */

+

+/******************  Bit definition for BDMA_CNDTR register  *******************/

+#define BDMA_CNDTR_NDT_Pos      (0U)

+#define BDMA_CNDTR_NDT_Msk      (0xFFFFUL << BDMA_CNDTR_NDT_Pos)               /*!< 0x0000FFFF */

+#define BDMA_CNDTR_NDT          BDMA_CNDTR_NDT_Msk                             /*!< Number of data to Transfer          */

+

+/******************  Bit definition for BDMA_CPAR register  ********************/

+#define BDMA_CPAR_PA_Pos        (0U)

+#define BDMA_CPAR_PA_Msk        (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CPAR_PA            BDMA_CPAR_PA_Msk                               /*!< Peripheral Address                  */

+

+/******************  Bit definition for BDMA_CM0AR register  ********************/

+#define BDMA_CM0AR_MA_Pos        (0U)

+#define BDMA_CM0AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CM0AR_MA            BDMA_CM0AR_MA_Msk                               /*!< Memory Address                      */

+

+/******************  Bit definition for BDMA_CM1AR register  ********************/

+#define BDMA_CM1AR_MA_Pos        (0U)

+#define BDMA_CM1AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CM1AR_MA            BDMA_CM1AR_MA_Msk                               /*!< Memory Address                      */

+

+/******************************************************************************/

+/*                                                                            */

+/*                Ethernet MAC Registers bits definitions                     */

+/*                                                                            */

+/******************************************************************************/

+/* Bit definition for Ethernet MAC Configuration Register register */

+#define ETH_MACCR_ARP_Pos                             (31U)

+#define ETH_MACCR_ARP_Msk                             (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */

+#define ETH_MACCR_ARP                                 ETH_MACCR_ARP_Msk        /* ARP Offload Enable */

+#define ETH_MACCR_SARC_Pos                            (28U)

+#define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */

+#define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */

+#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */

+#define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)

+#define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */

+#define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */

+#define ETH_MACCR_SARC_INSADDR1_Pos                   (29U)

+#define ETH_MACCR_SARC_INSADDR1_Msk                   (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */

+#define ETH_MACCR_SARC_INSADDR1                       ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */

+#define ETH_MACCR_SARC_REPADDR0_Pos                   (28U)

+#define ETH_MACCR_SARC_REPADDR0_Msk                   (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */

+#define ETH_MACCR_SARC_REPADDR0                       ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */

+#define ETH_MACCR_SARC_REPADDR1_Pos                   (28U)

+#define ETH_MACCR_SARC_REPADDR1_Msk                   (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */

+#define ETH_MACCR_SARC_REPADDR1                       ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */

+#define ETH_MACCR_IPC_Pos                             (27U)

+#define ETH_MACCR_IPC_Msk                             (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */

+#define ETH_MACCR_IPC                                 ETH_MACCR_IPC_Msk        /* Checksum Offload */

+#define ETH_MACCR_IPG_Pos                             (24U)

+#define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */

+#define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */

+#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */

+#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */

+#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */

+#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */

+#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */

+#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */

+#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */

+#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */

+#define ETH_MACCR_GPSLCE_Pos                          (23U)

+#define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */

+#define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */

+#define ETH_MACCR_S2KP_Pos                            (22U)

+#define ETH_MACCR_S2KP_Msk                            (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */

+#define ETH_MACCR_S2KP                                ETH_MACCR_S2KP_Msk       /* IEEE 802.3as Support for 2K Packets */

+#define ETH_MACCR_CST_Pos                             (21U)

+#define ETH_MACCR_CST_Msk                             (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */

+#define ETH_MACCR_CST                                 ETH_MACCR_CST_Msk        /* CRC stripping for Type packets */

+#define ETH_MACCR_ACS_Pos                             (20U)

+#define ETH_MACCR_ACS_Msk                             (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */

+#define ETH_MACCR_ACS                                 ETH_MACCR_ACS_Msk        /* Automatic Pad or CRC Stripping */

+#define ETH_MACCR_WD_Pos                              (19U)

+#define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */

+#define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */

+#define ETH_MACCR_JD_Pos                              (17U)

+#define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */

+#define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */

+#define ETH_MACCR_JE_Pos                              (16U)

+#define ETH_MACCR_JE_Msk                              (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */

+#define ETH_MACCR_JE                                  ETH_MACCR_JE_Msk         /* Jumbo Packet Enable */

+#define ETH_MACCR_FES_Pos                             (14U)

+#define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */

+#define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */

+#define ETH_MACCR_DM_Pos                              (13U)

+#define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */

+#define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */

+#define ETH_MACCR_LM_Pos                              (12U)

+#define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */

+#define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */

+#define ETH_MACCR_ECRSFD_Pos                          (11U)

+#define ETH_MACCR_ECRSFD_Msk                          (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */

+#define ETH_MACCR_ECRSFD                              ETH_MACCR_ECRSFD_Msk     /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */

+#define ETH_MACCR_DO_Pos                              (10U)

+#define ETH_MACCR_DO_Msk                              (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */

+#define ETH_MACCR_DO                                  ETH_MACCR_DO_Msk         /* Disable Receive own  */

+#define ETH_MACCR_DCRS_Pos                            (9U)

+#define ETH_MACCR_DCRS_Msk                            (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */

+#define ETH_MACCR_DCRS                                ETH_MACCR_DCRS_Msk       /* Disable Carrier Sense During Transmission */

+#define ETH_MACCR_DR_Pos                              (8U)

+#define ETH_MACCR_DR_Msk                              (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */

+#define ETH_MACCR_DR                                  ETH_MACCR_DR_Msk         /* Disable Retry */

+#define ETH_MACCR_BL_Pos                              (5U)

+#define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */

+#define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit mask */

+#define ETH_MACCR_BL_10                               (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */

+#define ETH_MACCR_BL_8                                (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */

+#define ETH_MACCR_BL_4                                (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */

+#define ETH_MACCR_BL_1                                (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */

+#define ETH_MACCR_DC_Pos                              (4U)

+#define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */

+#define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */

+#define ETH_MACCR_PRELEN_Pos                          (2U)

+#define ETH_MACCR_PRELEN_Msk                          (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */

+#define ETH_MACCR_PRELEN                              ETH_MACCR_PRELEN_Msk     /* Preamble Length for Transmit packets */

+#define ETH_MACCR_PRELEN_7                            (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */

+#define ETH_MACCR_PRELEN_5                            (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */

+#define ETH_MACCR_PRELEN_3                            (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */

+#define ETH_MACCR_TE_Pos                              (1U)

+#define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */

+#define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */

+#define ETH_MACCR_RE_Pos                              (0U)

+#define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */

+#define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */

+

+/* Bit definition for Ethernet MAC Extended Configuration Register register */

+#define ETH_MACECR_EIPG_Pos                           (25U)

+#define ETH_MACECR_EIPG_Msk                           (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */

+#define ETH_MACECR_EIPG                               ETH_MACECR_EIPG_Msk      /* Extended Inter-Packet Gap */

+#define ETH_MACECR_EIPGEN_Pos                         (24U)

+#define ETH_MACECR_EIPGEN_Msk                         (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */

+#define ETH_MACECR_EIPGEN                             ETH_MACECR_EIPGEN_Msk    /* Extended Inter-Packet Gap Enable */

+#define ETH_MACECR_USP_Pos                            (18U)

+#define ETH_MACECR_USP_Msk                            (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */

+#define ETH_MACECR_USP                                ETH_MACECR_USP_Msk       /* Unicast Slow Protocol Packet Detect */

+#define ETH_MACECR_SPEN_Pos                           (17U)

+#define ETH_MACECR_SPEN_Msk                           (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */

+#define ETH_MACECR_SPEN                               ETH_MACECR_SPEN_Msk      /* Slow Protocol Detection Enable */

+#define ETH_MACECR_DCRCC_Pos                          (16U)

+#define ETH_MACECR_DCRCC_Msk                          (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */

+#define ETH_MACECR_DCRCC                              ETH_MACECR_DCRCC_Msk     /* Disable CRC Checking for Received Packets */

+#define ETH_MACECR_GPSL_Pos                           (0U)

+#define ETH_MACECR_GPSL_Msk                           (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */

+#define ETH_MACECR_GPSL                               ETH_MACECR_GPSL_Msk      /* Giant Packet Size Limit */

+

+/* Bit definition for Ethernet MAC Packet Filter Register */

+#define ETH_MACPFR_RA_Pos                             (31U)

+#define ETH_MACPFR_RA_Msk                             (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */

+#define ETH_MACPFR_RA                                 ETH_MACPFR_RA_Msk        /* Receive all */

+#define ETH_MACPFR_DNTU_Pos                           (21U)

+#define ETH_MACPFR_DNTU_Msk                           (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */

+#define ETH_MACPFR_DNTU                               ETH_MACPFR_DNTU_Msk      /* Drop Non-TCP/UDP over IP Packets */

+#define ETH_MACPFR_IPFE_Pos                           (20U)

+#define ETH_MACPFR_IPFE_Msk                           (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */

+#define ETH_MACPFR_IPFE                               ETH_MACPFR_IPFE_Msk      /* Layer 3 and Layer 4 Filter Enable */

+#define ETH_MACPFR_VTFE_Pos                           (16U)

+#define ETH_MACPFR_VTFE_Msk                           (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */

+#define ETH_MACPFR_VTFE                               ETH_MACPFR_VTFE_Msk      /* VLAN Tag Filter Enable */

+#define ETH_MACPFR_HPF_Pos                            (10U)

+#define ETH_MACPFR_HPF_Msk                            (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */

+#define ETH_MACPFR_HPF                                ETH_MACPFR_HPF_Msk       /* Hash or perfect filter */

+#define ETH_MACPFR_SAF_Pos                            (9U)

+#define ETH_MACPFR_SAF_Msk                            (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */

+#define ETH_MACPFR_SAF                                ETH_MACPFR_SAF_Msk       /* Source address filter enable */

+#define ETH_MACPFR_SAIF_Pos                           (8U)

+#define ETH_MACPFR_SAIF_Msk                           (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */

+#define ETH_MACPFR_SAIF                               ETH_MACPFR_SAIF_Msk      /* SA inverse filtering */

+#define ETH_MACPFR_PCF_Pos                            (6U)

+#define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */

+#define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */

+#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */

+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)

+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */

+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */

+#define ETH_MACPFR_PCF_FORWARDALL_Pos                 (7U)

+#define ETH_MACPFR_PCF_FORWARDALL_Msk                 (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */

+#define ETH_MACPFR_PCF_FORWARDALL                     ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */

+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos    (6U)

+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk    (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */

+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER        ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */

+#define ETH_MACPFR_DBF_Pos                            (5U)

+#define ETH_MACPFR_DBF_Msk                            (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */

+#define ETH_MACPFR_DBF                                ETH_MACPFR_DBF_Msk       /* Disable Broadcast Packets */

+#define ETH_MACPFR_PM_Pos                             (4U)

+#define ETH_MACPFR_PM_Msk                             (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */

+#define ETH_MACPFR_PM                                 ETH_MACPFR_PM_Msk        /* Pass all mutlicast */

+#define ETH_MACPFR_DAIF_Pos                           (3U)

+#define ETH_MACPFR_DAIF_Msk                           (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */

+#define ETH_MACPFR_DAIF                               ETH_MACPFR_DAIF_Msk      /* DA Inverse filtering */

+#define ETH_MACPFR_HMC_Pos                            (2U)

+#define ETH_MACPFR_HMC_Msk                            (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */

+#define ETH_MACPFR_HMC                                ETH_MACPFR_HMC_Msk       /* Hash multicast */

+#define ETH_MACPFR_HUC_Pos                            (1U)

+#define ETH_MACPFR_HUC_Msk                            (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */

+#define ETH_MACPFR_HUC                                ETH_MACPFR_HUC_Msk       /* Hash unicast */

+#define ETH_MACPFR_PR_Pos                             (0U)

+#define ETH_MACPFR_PR_Msk                             (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */

+#define ETH_MACPFR_PR                                 ETH_MACPFR_PR_Msk        /* Promiscuous mode */

+

+/* Bit definition for Ethernet MAC Watchdog Timeout Register */

+#define ETH_MACWTR_PWE_Pos                            (8U)

+#define ETH_MACWTR_PWE_Msk                            (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */

+#define ETH_MACWTR_PWE                                ETH_MACWTR_PWE_Msk       /* Programmable Watchdog Enable */

+#define ETH_MACWTR_WTO_Pos                            (0U)

+#define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */

+#define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */

+#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/

+#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */

+#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */

+#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */

+#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */

+#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */

+#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */

+#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */

+#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */

+#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */

+#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */

+#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */

+#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */

+#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */

+#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */

+

+/* Bit definition for Ethernet MAC Hash Table High Register */

+#define ETH_MACHTHR_HTH_Pos                           (0U)

+#define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */

+

+/* Bit definition for Ethernet MAC Hash Table Low Register */

+#define ETH_MACHTLR_HTL_Pos                           (0U)

+#define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */

+

+/* Bit definition for Ethernet MAC VLAN Tag Register */

+#define ETH_MACVTR_EIVLRXS_Pos                        (31U)

+#define ETH_MACVTR_EIVLRXS_Msk                        (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */

+#define ETH_MACVTR_EIVLRXS                            ETH_MACVTR_EIVLRXS_Msk   /* Enable Inner VLAN Tag in Rx Status */

+#define ETH_MACVTR_EIVLS_Pos                          (28U)

+#define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */

+#define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */

+#define ETH_MACVTR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */

+#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)

+#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */

+#define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */

+#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos             (29U)

+#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk             (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */

+#define ETH_MACVTR_EIVLS_STRIPIFFAILS                 ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */

+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos              (28U)

+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk              (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */

+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP                  ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */

+#define ETH_MACVTR_ERIVLT_Pos                         (27U)

+#define ETH_MACVTR_ERIVLT_Msk                         (0x1UL << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */

+#define ETH_MACVTR_ERIVLT                             ETH_MACVTR_ERIVLT_Msk    /* Enable Inner VLAN Tag */

+#define ETH_MACVTR_EDVLP_Pos                          (26U)

+#define ETH_MACVTR_EDVLP_Msk                          (0x1UL << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */

+#define ETH_MACVTR_EDVLP                              ETH_MACVTR_EDVLP_Msk     /* Enable Double VLAN Processing */

+#define ETH_MACVTR_VTHM_Pos                           (25U)

+#define ETH_MACVTR_VTHM_Msk                           (0x1UL << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */

+#define ETH_MACVTR_VTHM                               ETH_MACVTR_VTHM_Msk      /* VLAN Tag Hash Table Match Enable */

+#define ETH_MACVTR_EVLRXS_Pos                         (24U)

+#define ETH_MACVTR_EVLRXS_Msk                         (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */

+#define ETH_MACVTR_EVLRXS                             ETH_MACVTR_EVLRXS_Msk    /* Enable VLAN Tag in Rx status */

+#define ETH_MACVTR_EVLS_Pos                           (21U)

+#define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */

+#define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */

+#define ETH_MACVTR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */

+#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)

+#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */

+#define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */

+#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos              (22U)

+#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk              (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */

+#define ETH_MACVTR_EVLS_STRIPIFFAILS                  ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */

+#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos               (21U)

+#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk               (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */

+#define ETH_MACVTR_EVLS_ALWAYSSTRIP                   ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */

+#define ETH_MACVTR_DOVLTC_Pos                         (20U)

+#define ETH_MACVTR_DOVLTC_Msk                         (0x1UL << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */

+#define ETH_MACVTR_DOVLTC                             ETH_MACVTR_DOVLTC_Msk    /* Disable VLAN Type Check */

+#define ETH_MACVTR_ERSVLM_Pos                         (19U)

+#define ETH_MACVTR_ERSVLM_Msk                         (0x1UL << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */

+#define ETH_MACVTR_ERSVLM                             ETH_MACVTR_ERSVLM_Msk    /* Enable Receive S-VLAN Match */

+#define ETH_MACVTR_ESVL_Pos                           (18U)

+#define ETH_MACVTR_ESVL_Msk                           (0x1UL << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */

+#define ETH_MACVTR_ESVL                               ETH_MACVTR_ESVL_Msk      /* Enable S-VLAN */

+#define ETH_MACVTR_VTIM_Pos                           (17U)

+#define ETH_MACVTR_VTIM_Msk                           (0x1UL << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */

+#define ETH_MACVTR_VTIM                               ETH_MACVTR_VTIM_Msk      /* VLAN Tag Inverse Match Enable */

+#define ETH_MACVTR_ETV_Pos                            (16U)

+#define ETH_MACVTR_ETV_Msk                            (0x1UL << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */

+#define ETH_MACVTR_ETV                                ETH_MACVTR_ETV_Msk       /* Enable 12-Bit VLAN Tag Comparison */

+#define ETH_MACVTR_VL_Pos                             (0U)

+#define ETH_MACVTR_VL_Msk                             (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */

+#define ETH_MACVTR_VL                                 ETH_MACVTR_VL_Msk        /* VLAN Tag Identifier for Receive Packets */

+#define ETH_MACVTR_VL_UP_Pos                          (13U)

+#define ETH_MACVTR_VL_UP_Msk                          (0x7UL << ETH_MACVTR_VL_UP_Pos) /*!< 0x0000E000 */

+#define ETH_MACVTR_VL_UP                              ETH_MACVTR_VL_UP_Msk     /* User Priority */

+#define ETH_MACVTR_VL_CFIDEI_Pos                      (12U)

+#define ETH_MACVTR_VL_CFIDEI_Msk                      (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos) /*!< 0x00001000 */

+#define ETH_MACVTR_VL_CFIDEI                          ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */

+#define ETH_MACVTR_VL_VID_Pos                         (0U)

+#define ETH_MACVTR_VL_VID_Msk                         (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */

+#define ETH_MACVTR_VL_VID                             ETH_MACVTR_VL_VID_Msk    /* VLAN Identifier field of VLAN tag */

+

+/* Bit definition for Ethernet MAC VLAN Hash Table Register */

+#define ETH_MACVHTR_VLHT_Pos                          (0U)

+#define ETH_MACVHTR_VLHT_Msk                          (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACVHTR_VLHT                              ETH_MACVHTR_VLHT_Msk     /* VLAN Hash Table */

+

+/* Bit definition for Ethernet MAC VLAN Incl Register */

+#define ETH_MACVIR_VLTI_Pos                           (20U)

+#define ETH_MACVIR_VLTI_Msk                           (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */

+#define ETH_MACVIR_VLTI                               ETH_MACVIR_VLTI_Msk      /* VLAN Tag Input */

+#define ETH_MACVIR_CSVL_Pos                           (19U)

+#define ETH_MACVIR_CSVL_Msk                           (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */

+#define ETH_MACVIR_CSVL                               ETH_MACVIR_CSVL_Msk      /* C-VLAN or S-VLAN */

+#define ETH_MACVIR_VLP_Pos                            (18U)

+#define ETH_MACVIR_VLP_Msk                            (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */

+#define ETH_MACVIR_VLP                                ETH_MACVIR_VLP_Msk       /* VLAN Priority Control */

+#define ETH_MACVIR_VLC_Pos                            (16U)

+#define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */

+#define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */

+#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */

+#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)

+#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */

+#define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */

+#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos              (17U)

+#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */

+#define ETH_MACVIR_VLC_VLANTAGINSERT                  ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */

+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos             (16U)

+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk             (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */

+#define ETH_MACVIR_VLC_VLANTAGREPLACE                 ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */

+#define ETH_MACVIR_VLT_Pos                            (0U)

+#define ETH_MACVIR_VLT_Msk                            (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACVIR_VLT                                ETH_MACVIR_VLT_Msk       /* VLAN Tag for Transmit Packets */

+#define ETH_MACVIR_VLT_UP_Pos                         (13U)

+#define ETH_MACVIR_VLT_UP_Msk                         (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */

+#define ETH_MACVIR_VLT_UP                             ETH_MACVIR_VLT_UP_Msk    /* User Priority */

+#define ETH_MACVIR_VLT_CFIDEI_Pos                     (12U)

+#define ETH_MACVIR_VLT_CFIDEI_Msk                     (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */

+#define ETH_MACVIR_VLT_CFIDEI                         ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */

+#define ETH_MACVIR_VLT_VID_Pos                        (0U)

+#define ETH_MACVIR_VLT_VID_Msk                        (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */

+#define ETH_MACVIR_VLT_VID                            ETH_MACVIR_VLT_VID_Msk   /* VLAN Identifier field of VLAN tag */

+

+/* Bit definition for Ethernet MAC Inner_VLAN Incl Register */

+#define ETH_MACIVIR_VLTI_Pos                          (20U)

+#define ETH_MACIVIR_VLTI_Msk                          (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */

+#define ETH_MACIVIR_VLTI                              ETH_MACIVIR_VLTI_Msk     /* VLAN Tag Input */

+#define ETH_MACIVIR_CSVL_Pos                          (19U)

+#define ETH_MACIVIR_CSVL_Msk                          (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */

+#define ETH_MACIVIR_CSVL                              ETH_MACIVIR_CSVL_Msk     /* C-VLAN or S-VLAN */

+#define ETH_MACIVIR_VLP_Pos                           (18U)

+#define ETH_MACIVIR_VLP_Msk                           (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */

+#define ETH_MACIVIR_VLP                               ETH_MACIVIR_VLP_Msk      /* VLAN Priority Control */

+#define ETH_MACIVIR_VLC_Pos                           (16U)

+#define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */

+#define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */

+#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */

+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)

+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */

+#define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */

+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos             (17U)

+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */

+#define ETH_MACIVIR_VLC_VLANTAGINSERT                 ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */

+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos            (16U)

+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk            (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */

+#define ETH_MACIVIR_VLC_VLANTAGREPLACE                ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */

+#define ETH_MACIVIR_VLT_Pos                           (0U)

+#define ETH_MACIVIR_VLT_Msk                           (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACIVIR_VLT                               ETH_MACIVIR_VLT_Msk      /* VLAN Tag for Transmit Packets */

+#define ETH_MACIVIR_VLT_UP_Pos                        (13U)

+#define ETH_MACIVIR_VLT_UP_Msk                        (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */

+#define ETH_MACIVIR_VLT_UP                            ETH_MACIVIR_VLT_UP_Msk   /* User Priority */

+#define ETH_MACIVIR_VLT_CFIDEI_Pos                    (12U)

+#define ETH_MACIVIR_VLT_CFIDEI_Msk                    (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */

+#define ETH_MACIVIR_VLT_CFIDEI                        ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */

+#define ETH_MACIVIR_VLT_VID_Pos                       (0U)

+#define ETH_MACIVIR_VLT_VID_Msk                       (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */

+#define ETH_MACIVIR_VLT_VID                           ETH_MACIVIR_VLT_VID_Msk  /* VLAN Identifier field of VLAN tag */

+

+/* Bit definition for Ethernet MAC Tx Flow Ctrl Register */

+#define ETH_MACTFCR_PT_Pos                            (16U)

+#define ETH_MACTFCR_PT_Msk                            (0xFFFFUL << ETH_MACTFCR_PT_Pos) /*!< 0xFFFF0000 */

+#define ETH_MACTFCR_PT                                ETH_MACTFCR_PT_Msk       /* Pause Time */

+#define ETH_MACTFCR_DZPQ_Pos                          (7U)

+#define ETH_MACTFCR_DZPQ_Msk                          (0x1UL << ETH_MACTFCR_DZPQ_Pos) /*!< 0x00000080 */

+#define ETH_MACTFCR_DZPQ                              ETH_MACTFCR_DZPQ_Msk     /* Disable Zero-Quanta Pause */

+#define ETH_MACTFCR_PLT_Pos                           (4U)

+#define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */

+#define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */

+#define ETH_MACTFCR_PLT_MINUS4                        ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */

+#define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)

+#define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */

+#define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */

+#define ETH_MACTFCR_PLT_MINUS36_Pos                   (5U)

+#define ETH_MACTFCR_PLT_MINUS36_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */

+#define ETH_MACTFCR_PLT_MINUS36                       ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */

+#define ETH_MACTFCR_PLT_MINUS144_Pos                  (4U)

+#define ETH_MACTFCR_PLT_MINUS144_Msk                  (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */

+#define ETH_MACTFCR_PLT_MINUS144                      ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */

+#define ETH_MACTFCR_PLT_MINUS256_Pos                  (6U)

+#define ETH_MACTFCR_PLT_MINUS256_Msk                  (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */

+#define ETH_MACTFCR_PLT_MINUS256                      ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */

+#define ETH_MACTFCR_PLT_MINUS512_Pos                  (4U)

+#define ETH_MACTFCR_PLT_MINUS512_Msk                  (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */

+#define ETH_MACTFCR_PLT_MINUS512                      ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */

+#define ETH_MACTFCR_TFE_Pos                           (1U)

+#define ETH_MACTFCR_TFE_Msk                           (0x1UL << ETH_MACTFCR_TFE_Pos) /*!< 0x00000002 */

+#define ETH_MACTFCR_TFE                               ETH_MACTFCR_TFE_Msk      /* Transmit Flow Control Enable */

+#define ETH_MACTFCR_FCB_Pos                           (0U)

+#define ETH_MACTFCR_FCB_Msk                           (0x1UL << ETH_MACTFCR_FCB_Pos) /*!< 0x00000001 */

+#define ETH_MACTFCR_FCB                               ETH_MACTFCR_FCB_Msk      /* Flow Control Busy or Backpressure Activate */

+

+/* Bit definition for Ethernet MAC Rx Flow Ctrl Register */

+#define ETH_MACRFCR_UP_Pos                            (1U)

+#define ETH_MACRFCR_UP_Msk                            (0x1UL << ETH_MACRFCR_UP_Pos) /*!< 0x00000002 */

+#define ETH_MACRFCR_UP                                ETH_MACRFCR_UP_Msk       /* Unicast Pause Packet Detect */

+#define ETH_MACRFCR_RFE_Pos                           (0U)

+#define ETH_MACRFCR_RFE_Msk                           (0x1UL << ETH_MACRFCR_RFE_Pos) /*!< 0x00000001 */

+#define ETH_MACRFCR_RFE                               ETH_MACRFCR_RFE_Msk      /* Receive Flow Control Enable */

+

+/* Bit definition for Ethernet MAC Interrupt Status Register */

+#define ETH_MACISR_RXSTSIS_Pos                        (14U)

+#define ETH_MACISR_RXSTSIS_Msk                        (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */

+#define ETH_MACISR_RXSTSIS                            ETH_MACISR_RXSTSIS_Msk   /* Receive Status Interrupt */

+#define ETH_MACISR_TXSTSIS_Pos                        (13U)

+#define ETH_MACISR_TXSTSIS_Msk                        (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */

+#define ETH_MACISR_TXSTSIS                            ETH_MACISR_TXSTSIS_Msk   /* Transmit Status Interrupt */

+#define ETH_MACISR_TSIS_Pos                           (12U)

+#define ETH_MACISR_TSIS_Msk                           (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */

+#define ETH_MACISR_TSIS                               ETH_MACISR_TSIS_Msk      /* Timestamp Interrupt Status */

+#define ETH_MACISR_MMCTXIS_Pos                        (10U)

+#define ETH_MACISR_MMCTXIS_Msk                        (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */

+#define ETH_MACISR_MMCTXIS                            ETH_MACISR_MMCTXIS_Msk   /* MMC Transmit Interrupt Status */

+#define ETH_MACISR_MMCRXIS_Pos                        (9U)

+#define ETH_MACISR_MMCRXIS_Msk                        (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */

+#define ETH_MACISR_MMCRXIS                            ETH_MACISR_MMCRXIS_Msk   /* MMC Receive Interrupt Status */

+#define ETH_MACISR_MMCIS_Pos                          (8U)

+#define ETH_MACISR_MMCIS_Msk                          (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */

+#define ETH_MACISR_MMCIS                              ETH_MACISR_MMCIS_Msk     /* MMC Interrupt Status */

+#define ETH_MACISR_LPIIS_Pos                          (5U)

+#define ETH_MACISR_LPIIS_Msk                          (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */

+#define ETH_MACISR_LPIIS                              ETH_MACISR_LPIIS_Msk     /* LPI Interrupt Status */

+#define ETH_MACISR_PMTIS_Pos                          (4U)

+#define ETH_MACISR_PMTIS_Msk                          (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */

+#define ETH_MACISR_PMTIS                              ETH_MACISR_PMTIS_Msk     /* PMT Interrupt Status */

+#define ETH_MACISR_PHYIS_Pos                          (3U)

+#define ETH_MACISR_PHYIS_Msk                          (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */

+#define ETH_MACISR_PHYIS                              ETH_MACISR_PHYIS_Msk     /* PHY Interrupt */

+

+/* Bit definition for Ethernet MAC Interrupt Enable Register */

+#define ETH_MACIER_RXSTSIE_Pos                        (14U)

+#define ETH_MACIER_RXSTSIE_Msk                        (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */

+#define ETH_MACIER_RXSTSIE                            ETH_MACIER_RXSTSIE_Msk   /* Receive Status Interrupt Enable */

+#define ETH_MACIER_TXSTSIE_Pos                        (13U)

+#define ETH_MACIER_TXSTSIE_Msk                        (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */

+#define ETH_MACIER_TXSTSIE                            ETH_MACIER_TXSTSIE_Msk   /* Transmit Status Interrupt Enable */

+#define ETH_MACIER_TSIE_Pos                           (12U)

+#define ETH_MACIER_TSIE_Msk                           (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */

+#define ETH_MACIER_TSIE                               ETH_MACIER_TSIE_Msk      /* Timestamp Interrupt Enable */

+#define ETH_MACIER_LPIIE_Pos                          (5U)

+#define ETH_MACIER_LPIIE_Msk                          (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */

+#define ETH_MACIER_LPIIE                              ETH_MACIER_LPIIE_Msk     /* LPI Interrupt Enable */

+#define ETH_MACIER_PMTIE_Pos                          (4U)

+#define ETH_MACIER_PMTIE_Msk                          (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */

+#define ETH_MACIER_PMTIE                              ETH_MACIER_PMTIE_Msk     /* PMT Interrupt Enable */

+#define ETH_MACIER_PHYIE_Pos                          (3U)

+#define ETH_MACIER_PHYIE_Msk                          (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */

+#define ETH_MACIER_PHYIE                              ETH_MACIER_PHYIE_Msk     /* PHY Interrupt Enable */

+

+/* Bit definition for Ethernet MAC Rx Tx Status Register */

+#define ETH_MACRXTXSR_RWT_Pos                         (8U)

+#define ETH_MACRXTXSR_RWT_Msk                         (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */

+#define ETH_MACRXTXSR_RWT                             ETH_MACRXTXSR_RWT_Msk    /* Receive Watchdog Timeout */

+#define ETH_MACRXTXSR_EXCOL_Pos                       (5U)

+#define ETH_MACRXTXSR_EXCOL_Msk                       (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */

+#define ETH_MACRXTXSR_EXCOL                           ETH_MACRXTXSR_EXCOL_Msk  /* Excessive Collisions */

+#define ETH_MACRXTXSR_LCOL_Pos                        (4U)

+#define ETH_MACRXTXSR_LCOL_Msk                        (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */

+#define ETH_MACRXTXSR_LCOL                            ETH_MACRXTXSR_LCOL_Msk   /* Late Collision */

+#define ETH_MACRXTXSR_EXDEF_Pos                       (3U)

+#define ETH_MACRXTXSR_EXDEF_Msk                       (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */

+#define ETH_MACRXTXSR_EXDEF                           ETH_MACRXTXSR_EXDEF_Msk  /* Excessive Deferral */

+#define ETH_MACRXTXSR_LCARR_Pos                       (2U)

+#define ETH_MACRXTXSR_LCARR_Msk                       (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */

+#define ETH_MACRXTXSR_LCARR                           ETH_MACRXTXSR_LCARR_Msk  /* Loss of Carrier */

+#define ETH_MACRXTXSR_NCARR_Pos                       (1U)

+#define ETH_MACRXTXSR_NCARR_Msk                       (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */

+#define ETH_MACRXTXSR_NCARR                           ETH_MACRXTXSR_NCARR_Msk  /* No Carrier */

+#define ETH_MACRXTXSR_TJT_Pos                         (0U)

+#define ETH_MACRXTXSR_TJT_Msk                         (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */

+#define ETH_MACRXTXSR_TJT                             ETH_MACRXTXSR_TJT_Msk    /* Transmit Jabber Timeout */

+

+/* Bit definition for Ethernet MAC PMT Control Status Register */

+#define ETH_MACPCSR_RWKFILTRST_Pos                    (31U)

+#define ETH_MACPCSR_RWKFILTRST_Msk                    (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */

+#define ETH_MACPCSR_RWKFILTRST                        ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */

+#define ETH_MACPCSR_RWKPTR_Pos                        (24U)

+#define ETH_MACPCSR_RWKPTR_Msk                        (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */

+#define ETH_MACPCSR_RWKPTR                            ETH_MACPCSR_RWKPTR_Msk   /* Remote Wake-up FIFO Pointer */

+#define ETH_MACPCSR_RWKPFE_Pos                        (10U)

+#define ETH_MACPCSR_RWKPFE_Msk                        (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */

+#define ETH_MACPCSR_RWKPFE                            ETH_MACPCSR_RWKPFE_Msk   /* Remote Wake-up Packet Forwarding Enable */

+#define ETH_MACPCSR_GLBLUCAST_Pos                     (9U)

+#define ETH_MACPCSR_GLBLUCAST_Msk                     (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */

+#define ETH_MACPCSR_GLBLUCAST                         ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */

+#define ETH_MACPCSR_RWKPRCVD_Pos                      (6U)

+#define ETH_MACPCSR_RWKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */

+#define ETH_MACPCSR_RWKPRCVD                          ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */

+#define ETH_MACPCSR_MGKPRCVD_Pos                      (5U)

+#define ETH_MACPCSR_MGKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */

+#define ETH_MACPCSR_MGKPRCVD                          ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */

+#define ETH_MACPCSR_RWKPKTEN_Pos                      (2U)

+#define ETH_MACPCSR_RWKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */

+#define ETH_MACPCSR_RWKPKTEN                          ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */

+#define ETH_MACPCSR_MGKPKTEN_Pos                      (1U)

+#define ETH_MACPCSR_MGKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */

+#define ETH_MACPCSR_MGKPKTEN                          ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */

+#define ETH_MACPCSR_PWRDWN_Pos                        (0U)

+#define ETH_MACPCSR_PWRDWN_Msk                        (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */

+#define ETH_MACPCSR_PWRDWN                            ETH_MACPCSR_PWRDWN_Msk   /* Power Down */

+

+/* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */

+#define ETH_MACRWUPFR_D_Pos                           (0U)

+#define ETH_MACRWUPFR_D_Msk                           (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACRWUPFR_D                               ETH_MACRWUPFR_D_Msk      /* Wake-up Packet filter register data */

+

+/* Bit definition for Ethernet MAC LPI Control Status Register */

+#define ETH_MACLCSR_LPITCSE_Pos                       (21U)

+#define ETH_MACLCSR_LPITCSE_Msk                       (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */

+#define ETH_MACLCSR_LPITCSE                           ETH_MACLCSR_LPITCSE_Msk  /* LPI Tx Clock Stop Enable */

+#define ETH_MACLCSR_LPITE_Pos                         (20U)

+#define ETH_MACLCSR_LPITE_Msk                         (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */

+#define ETH_MACLCSR_LPITE                             ETH_MACLCSR_LPITE_Msk    /* LPI Timer Enable */

+#define ETH_MACLCSR_LPITXA_Pos                        (19U)

+#define ETH_MACLCSR_LPITXA_Msk                        (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */

+#define ETH_MACLCSR_LPITXA                            ETH_MACLCSR_LPITXA_Msk   /* LPI Tx Automate */

+#define ETH_MACLCSR_PLS_Pos                           (17U)

+#define ETH_MACLCSR_PLS_Msk                           (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */

+#define ETH_MACLCSR_PLS                               ETH_MACLCSR_PLS_Msk      /* PHY Link Status */

+#define ETH_MACLCSR_LPIEN_Pos                         (16U)

+#define ETH_MACLCSR_LPIEN_Msk                         (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */

+#define ETH_MACLCSR_LPIEN                             ETH_MACLCSR_LPIEN_Msk    /* LPI Enable */

+#define ETH_MACLCSR_RLPIST_Pos                        (9U)

+#define ETH_MACLCSR_RLPIST_Msk                        (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */

+#define ETH_MACLCSR_RLPIST                            ETH_MACLCSR_RLPIST_Msk   /* Receive LPI State */

+#define ETH_MACLCSR_TLPIST_Pos                        (8U)

+#define ETH_MACLCSR_TLPIST_Msk                        (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */

+#define ETH_MACLCSR_TLPIST                            ETH_MACLCSR_TLPIST_Msk   /* Transmit LPI State */

+#define ETH_MACLCSR_RLPIEX_Pos                        (3U)

+#define ETH_MACLCSR_RLPIEX_Msk                        (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */

+#define ETH_MACLCSR_RLPIEX                            ETH_MACLCSR_RLPIEX_Msk   /* Receive LPI Exit */

+#define ETH_MACLCSR_RLPIEN_Pos                        (2U)

+#define ETH_MACLCSR_RLPIEN_Msk                        (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */

+#define ETH_MACLCSR_RLPIEN                            ETH_MACLCSR_RLPIEN_Msk   /* Receive LPI Entry */

+#define ETH_MACLCSR_TLPIEX_Pos                        (1U)

+#define ETH_MACLCSR_TLPIEX_Msk                        (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */

+#define ETH_MACLCSR_TLPIEX                            ETH_MACLCSR_TLPIEX_Msk   /* Transmit LPI Exit */

+#define ETH_MACLCSR_TLPIEN_Pos                        (0U)

+#define ETH_MACLCSR_TLPIEN_Msk                        (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */

+#define ETH_MACLCSR_TLPIEN                            ETH_MACLCSR_TLPIEN_Msk   /* Transmit LPI Entry */

+

+/* Bit definition for Ethernet MAC LPI Timers Control Register */

+#define ETH_MACLTCR_LST_Pos                           (16U)

+#define ETH_MACLTCR_LST_Msk                           (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */

+#define ETH_MACLTCR_LST                               ETH_MACLTCR_LST_Msk      /* LPI LS TIMER */

+#define ETH_MACLTCR_TWT_Pos                           (0U)

+#define ETH_MACLTCR_TWT_Msk                           (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACLTCR_TWT                               ETH_MACLTCR_TWT_Msk      /* LPI TW TIMER */

+

+/* Bit definition for Ethernet MAC LPI Entry Timer Register */

+#define ETH_MACLETR_LPIET_Pos                         (0U)

+#define ETH_MACLETR_LPIET_Msk                         (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */

+#define ETH_MACLETR_LPIET                             ETH_MACLETR_LPIET_Msk    /* LPI Entry Timer */

+

+/* Bit definition for Ethernet MAC 1US Tic Counter Register */

+#define ETH_MAC1USTCR_TIC1USCNTR_Pos                  (0U)

+#define ETH_MAC1USTCR_TIC1USCNTR_Msk                  (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */

+#define ETH_MAC1USTCR_TIC1USCNTR                      ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */

+

+/* Bit definition for Ethernet MAC Version Register */

+#define ETH_MACVR_USERVER_Pos                         (8U)

+#define ETH_MACVR_USERVER_Msk                         (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */

+#define ETH_MACVR_USERVER                             ETH_MACVR_USERVER_Msk    /* User-defined Version */

+#define ETH_MACVR_SNPSVER_Pos                         (0U)

+#define ETH_MACVR_SNPSVER_Msk                         (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */

+#define ETH_MACVR_SNPSVER                             ETH_MACVR_SNPSVER_Msk    /* Synopsys-defined Version */

+

+/* Bit definition for Ethernet MAC Debug Register */

+#define ETH_MACDR_TFCSTS_Pos                          (17U)

+#define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */

+#define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */

+#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */

+#define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)

+#define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */

+#define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */

+#define ETH_MACDR_TFCSTS_GENERATEPCP_Pos              (18U)

+#define ETH_MACDR_TFCSTS_GENERATEPCP_Msk              (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */

+#define ETH_MACDR_TFCSTS_GENERATEPCP                  ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */

+#define ETH_MACDR_TFCSTS_TRASFERIP_Pos                (17U)

+#define ETH_MACDR_TFCSTS_TRASFERIP_Msk                (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */

+#define ETH_MACDR_TFCSTS_TRASFERIP                    ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */

+#define ETH_MACDR_TPESTS_Pos                          (16U)

+#define ETH_MACDR_TPESTS_Msk                          (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */

+#define ETH_MACDR_TPESTS                              ETH_MACDR_TPESTS_Msk     /* MAC Receive Packet Controller FIFO Status */

+#define ETH_MACDR_RFCFCSTS_Pos                        (1U)

+#define ETH_MACDR_RFCFCSTS_Msk                        (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */

+#define ETH_MACDR_RFCFCSTS                            ETH_MACDR_RFCFCSTS_Msk   /* MAC MII Transmit Protocol Engine Status */

+#define ETH_MACDR_RPESTS_Pos                          (0U)

+#define ETH_MACDR_RPESTS_Msk                          (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */

+#define ETH_MACDR_RPESTS                              ETH_MACDR_RPESTS_Msk     /* MAC MII Receive Protocol Engine Status */

+

+/* Bit definition for Ethernet MAC HW Feature0 Register */

+#define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)

+#define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */

+#define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */

+#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */

+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)

+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */

+#define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */

+#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos             (28U)

+#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk             (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos) /*!< 0x70000000 */

+#define ETH_MACHWF0R_ACTPHYSEL_REVMII                 ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */

+#define ETH_MACHWF0R_SAVLANINS_Pos                    (27U)

+#define ETH_MACHWF0R_SAVLANINS_Msk                    (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */

+#define ETH_MACHWF0R_SAVLANINS                        ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */

+#define ETH_MACHWF0R_TSSTSSEL_Pos                     (25U)

+#define ETH_MACHWF0R_TSSTSSEL_Msk                     (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */

+#define ETH_MACHWF0R_TSSTSSEL                         ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */

+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos            (25U)

+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */

+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL                ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */

+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos            (26U)

+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */

+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL                ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */

+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos                (25U)

+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk                (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */

+#define ETH_MACHWF0R_TSSTSSEL_BOTH                    ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */

+#define ETH_MACHWF0R_MACADR64SEL_Pos                  (24U)

+#define ETH_MACHWF0R_MACADR64SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */

+#define ETH_MACHWF0R_MACADR64SEL                      ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */

+#define ETH_MACHWF0R_MACADR32SEL_Pos                  (23U)

+#define ETH_MACHWF0R_MACADR32SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */

+#define ETH_MACHWF0R_MACADR32SEL                      ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */

+#define ETH_MACHWF0R_ADDMACADRSEL_Pos                 (18U)

+#define ETH_MACHWF0R_ADDMACADRSEL_Msk                 (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */

+#define ETH_MACHWF0R_ADDMACADRSEL                     ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */

+#define ETH_MACHWF0R_RXCOESEL_Pos                     (16U)

+#define ETH_MACHWF0R_RXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */

+#define ETH_MACHWF0R_RXCOESEL                         ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */

+#define ETH_MACHWF0R_TXCOESEL_Pos                     (14U)

+#define ETH_MACHWF0R_TXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */

+#define ETH_MACHWF0R_TXCOESEL                         ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */

+#define ETH_MACHWF0R_EEESEL_Pos                       (13U)

+#define ETH_MACHWF0R_EEESEL_Msk                       (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */

+#define ETH_MACHWF0R_EEESEL                           ETH_MACHWF0R_EEESEL_Msk  /* Energy Efficient Ethernet Enabled */

+#define ETH_MACHWF0R_TSSEL_Pos                        (12U)

+#define ETH_MACHWF0R_TSSEL_Msk                        (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */

+#define ETH_MACHWF0R_TSSEL                            ETH_MACHWF0R_TSSEL_Msk   /* IEEE 1588-2008 Timestamp Enabled */

+#define ETH_MACHWF0R_ARPOFFSEL_Pos                    (9U)

+#define ETH_MACHWF0R_ARPOFFSEL_Msk                    (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */

+#define ETH_MACHWF0R_ARPOFFSEL                        ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */

+#define ETH_MACHWF0R_MMCSEL_Pos                       (8U)

+#define ETH_MACHWF0R_MMCSEL_Msk                       (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */

+#define ETH_MACHWF0R_MMCSEL                           ETH_MACHWF0R_MMCSEL_Msk  /* RMON Module Enable */

+#define ETH_MACHWF0R_MGKSEL_Pos                       (7U)

+#define ETH_MACHWF0R_MGKSEL_Msk                       (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */

+#define ETH_MACHWF0R_MGKSEL                           ETH_MACHWF0R_MGKSEL_Msk  /* PMT Magic Packet Enable */

+#define ETH_MACHWF0R_RWKSEL_Pos                       (6U)

+#define ETH_MACHWF0R_RWKSEL_Msk                       (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */

+#define ETH_MACHWF0R_RWKSEL                           ETH_MACHWF0R_RWKSEL_Msk  /* PMT Remote Wake-up Packet Enable */

+#define ETH_MACHWF0R_SMASEL_Pos                       (5U)

+#define ETH_MACHWF0R_SMASEL_Msk                       (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */

+#define ETH_MACHWF0R_SMASEL                           ETH_MACHWF0R_SMASEL_Msk  /* SMA (MDIO) Interface */

+#define ETH_MACHWF0R_VLHASH_Pos                       (4U)

+#define ETH_MACHWF0R_VLHASH_Msk                       (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */

+#define ETH_MACHWF0R_VLHASH                           ETH_MACHWF0R_VLHASH_Msk  /* VLAN Hash Filter Selected */

+#define ETH_MACHWF0R_PCSSEL_Pos                       (3U)

+#define ETH_MACHWF0R_PCSSEL_Msk                       (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */

+#define ETH_MACHWF0R_PCSSEL                           ETH_MACHWF0R_PCSSEL_Msk  /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */

+#define ETH_MACHWF0R_HDSEL_Pos                        (2U)

+#define ETH_MACHWF0R_HDSEL_Msk                        (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */

+#define ETH_MACHWF0R_HDSEL                            ETH_MACHWF0R_HDSEL_Msk   /* Half-duplex Support */

+#define ETH_MACHWF0R_GMIISEL_Pos                      (1U)

+#define ETH_MACHWF0R_GMIISEL_Msk                      (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */

+#define ETH_MACHWF0R_GMIISEL                          ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */

+#define ETH_MACHWF0R_MIISEL_Pos                       (0U)

+#define ETH_MACHWF0R_MIISEL_Msk                       (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */

+#define ETH_MACHWF0R_MIISEL                           ETH_MACHWF0R_MIISEL_Msk  /* 10 or 100 Mbps Support */

+

+/* Bit definition for Ethernet MAC HW Feature1 Register */

+#define ETH_MACHWF1R_L3L4FNUM_Pos                     (27U)

+#define ETH_MACHWF1R_L3L4FNUM_Msk                     (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */

+#define ETH_MACHWF1R_L3L4FNUM                         ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */

+#define ETH_MACHWF1R_HASHTBLSZ_Pos                    (24U)

+#define ETH_MACHWF1R_HASHTBLSZ_Msk                    (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */

+#define ETH_MACHWF1R_HASHTBLSZ                        ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */

+#define ETH_MACHWF1R_AVSEL_Pos                        (20U)

+#define ETH_MACHWF1R_AVSEL_Msk                        (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */

+#define ETH_MACHWF1R_AVSEL                            ETH_MACHWF1R_AVSEL_Msk   /* AV Feature Enabled */

+#define ETH_MACHWF1R_DBGMEMA_Pos                      (19U)

+#define ETH_MACHWF1R_DBGMEMA_Msk                      (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */

+#define ETH_MACHWF1R_DBGMEMA                          ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */

+#define ETH_MACHWF1R_TSOEN_Pos                        (18U)

+#define ETH_MACHWF1R_TSOEN_Msk                        (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */

+#define ETH_MACHWF1R_TSOEN                            ETH_MACHWF1R_TSOEN_Msk   /* TCP Segmentation Offload Enable */

+#define ETH_MACHWF1R_SPHEN_Pos                        (17U)

+#define ETH_MACHWF1R_SPHEN_Msk                        (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */

+#define ETH_MACHWF1R_SPHEN                            ETH_MACHWF1R_SPHEN_Msk   /* Split Header Feature Enable */

+#define ETH_MACHWF1R_DCBEN_Pos                        (16U)

+#define ETH_MACHWF1R_DCBEN_Msk                        (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */

+#define ETH_MACHWF1R_DCBEN                            ETH_MACHWF1R_DCBEN_Msk   /* DCB Feature Enable */

+#define ETH_MACHWF1R_ADDR64_Pos                       (14U)

+#define ETH_MACHWF1R_ADDR64_Msk                       (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */

+#define ETH_MACHWF1R_ADDR64                           ETH_MACHWF1R_ADDR64_Msk  /* Address Width */

+#define ETH_MACHWF1R_ADDR64_32                        (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */

+#define ETH_MACHWF1R_ADDR64_40                        (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */

+#define ETH_MACHWF1R_ADDR64_48                        (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */

+#define ETH_MACHWF1R_ADVTHWORD_Pos                    (13U)

+#define ETH_MACHWF1R_ADVTHWORD_Msk                    (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */

+#define ETH_MACHWF1R_ADVTHWORD                        ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */

+#define ETH_MACHWF1R_PTOEN_Pos                        (12U)

+#define ETH_MACHWF1R_PTOEN_Msk                        (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */

+#define ETH_MACHWF1R_PTOEN                            ETH_MACHWF1R_PTOEN_Msk   /* PTP Offload Enable */

+#define ETH_MACHWF1R_OSTEN_Pos                        (11U)

+#define ETH_MACHWF1R_OSTEN_Msk                        (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */

+#define ETH_MACHWF1R_OSTEN                            ETH_MACHWF1R_OSTEN_Msk   /* One-Step Timestamping Enable */

+#define ETH_MACHWF1R_TXFIFOSIZE_Pos                   (6U)

+#define ETH_MACHWF1R_TXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */

+#define ETH_MACHWF1R_TXFIFOSIZE                       ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */

+#define ETH_MACHWF1R_RXFIFOSIZE_Pos                   (0U)

+#define ETH_MACHWF1R_RXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */

+#define ETH_MACHWF1R_RXFIFOSIZE                       ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */

+

+/* Bit definition for Ethernet MAC HW Feature2 Register */

+#define ETH_MACHWF2R_AUXSNAPNUM_Pos                   (28U)

+#define ETH_MACHWF2R_AUXSNAPNUM_Msk                   (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */

+#define ETH_MACHWF2R_AUXSNAPNUM                       ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */

+#define ETH_MACHWF2R_PPSOUTNUM_Pos                    (24U)

+#define ETH_MACHWF2R_PPSOUTNUM_Msk                    (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */

+#define ETH_MACHWF2R_PPSOUTNUM                        ETH_MACHWF2R_PPSOUTNUM_Msk /*  Number of PPS Outputs */

+#define ETH_MACHWF2R_TXCHCNT_Pos                      (18U)

+#define ETH_MACHWF2R_TXCHCNT_Msk                      (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */

+#define ETH_MACHWF2R_TXCHCNT                          ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */

+#define ETH_MACHWF2R_RXCHCNT_Pos                      (13U)

+#define ETH_MACHWF2R_RXCHCNT_Msk                      (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000E000 */

+#define ETH_MACHWF2R_RXCHCNT                          ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */

+#define ETH_MACHWF2R_TXQCNT_Pos                       (6U)

+#define ETH_MACHWF2R_TXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */

+#define ETH_MACHWF2R_TXQCNT                           ETH_MACHWF2R_TXQCNT_Msk  /* Number of MTL Transmit Queues */

+#define ETH_MACHWF2R_RXQCNT_Pos                       (0U)

+#define ETH_MACHWF2R_RXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */

+#define ETH_MACHWF2R_RXQCNT                           ETH_MACHWF2R_RXQCNT_Msk  /* Number of MTL Receive Queues */

+

+/* Bit definition for Ethernet MAC MDIO Address Register */

+#define ETH_MACMDIOAR_PSE_Pos                         (27U)

+#define ETH_MACMDIOAR_PSE_Msk                         (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */

+#define ETH_MACMDIOAR_PSE                             ETH_MACMDIOAR_PSE_Msk    /* Preamble Suppression Enable */

+#define ETH_MACMDIOAR_BTB_Pos                         (26U)

+#define ETH_MACMDIOAR_BTB_Msk                         (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */

+#define ETH_MACMDIOAR_BTB                             ETH_MACMDIOAR_BTB_Msk    /* Back to Back transactions */

+#define ETH_MACMDIOAR_PA_Pos                          (21U)

+#define ETH_MACMDIOAR_PA_Msk                          (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */

+#define ETH_MACMDIOAR_PA                              ETH_MACMDIOAR_PA_Msk     /* Physical Layer Address */

+#define ETH_MACMDIOAR_RDA_Pos                         (16U)

+#define ETH_MACMDIOAR_RDA_Msk                         (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */

+#define ETH_MACMDIOAR_RDA                             ETH_MACMDIOAR_RDA_Msk    /* Register/Device Address */

+#define ETH_MACMDIOAR_NTC_Pos                         (12U)

+#define ETH_MACMDIOAR_NTC_Msk                         (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */

+#define ETH_MACMDIOAR_NTC                             ETH_MACMDIOAR_NTC_Msk    /* Number of Trailing Clocks */

+#define ETH_MACMDIOAR_CR_Pos                          (8U)

+#define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */

+#define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */

+#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */

+#define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)

+#define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */

+#define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */

+#define ETH_MACMDIOAR_CR_DIV16_Pos                    (9U)

+#define ETH_MACMDIOAR_CR_DIV16_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */

+#define ETH_MACMDIOAR_CR_DIV16                        ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */

+#define ETH_MACMDIOAR_CR_DIV26_Pos                    (8U)

+#define ETH_MACMDIOAR_CR_DIV26_Msk                    (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */

+#define ETH_MACMDIOAR_CR_DIV26                        ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */

+#define ETH_MACMDIOAR_CR_DIV102_Pos                   (10U)

+#define ETH_MACMDIOAR_CR_DIV102_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */

+#define ETH_MACMDIOAR_CR_DIV102                       ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */

+#define ETH_MACMDIOAR_CR_DIV124_Pos                   (8U)

+#define ETH_MACMDIOAR_CR_DIV124_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */

+#define ETH_MACMDIOAR_CR_DIV124                       ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */

+#define ETH_MACMDIOAR_CR_DIV4AR_Pos                   (11U)

+#define ETH_MACMDIOAR_CR_DIV4AR_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */

+#define ETH_MACMDIOAR_CR_DIV4AR                       ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV6AR_Pos                   (8U)

+#define ETH_MACMDIOAR_CR_DIV6AR_Msk                   (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */

+#define ETH_MACMDIOAR_CR_DIV6AR                       ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV8AR_Pos                   (9U)

+#define ETH_MACMDIOAR_CR_DIV8AR_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */

+#define ETH_MACMDIOAR_CR_DIV8AR                       ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV10AR_Pos                  (8U)

+#define ETH_MACMDIOAR_CR_DIV10AR_Msk                  (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */

+#define ETH_MACMDIOAR_CR_DIV10AR                      ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV12AR_Pos                  (10U)

+#define ETH_MACMDIOAR_CR_DIV12AR_Msk                  (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */

+#define ETH_MACMDIOAR_CR_DIV12AR                      ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV14AR_Pos                  (8U)

+#define ETH_MACMDIOAR_CR_DIV14AR_Msk                  (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */

+#define ETH_MACMDIOAR_CR_DIV14AR                      ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV16AR_Pos                  (9U)

+#define ETH_MACMDIOAR_CR_DIV16AR_Msk                  (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */

+#define ETH_MACMDIOAR_CR_DIV16AR                      ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV18AR_Pos                  (8U)

+#define ETH_MACMDIOAR_CR_DIV18AR_Msk                  (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */

+#define ETH_MACMDIOAR_CR_DIV18AR                      ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_SKAP_Pos                        (4U)

+#define ETH_MACMDIOAR_SKAP_Msk                        (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */

+#define ETH_MACMDIOAR_SKAP                            ETH_MACMDIOAR_SKAP_Msk   /* Skip Address Packet */

+#define ETH_MACMDIOAR_MOC_Pos                         (2U)

+#define ETH_MACMDIOAR_MOC_Msk                         (0x3UL << ETH_MACMDIOAR_MOC_Pos) /*!< 0x0000000C */

+#define ETH_MACMDIOAR_MOC                             ETH_MACMDIOAR_MOC_Msk    /* MII Operation Command */

+#define ETH_MACMDIOAR_MOC_WR_Pos                      (2U)

+#define ETH_MACMDIOAR_MOC_WR_Msk                      (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos) /*!< 0x00000004 */

+#define ETH_MACMDIOAR_MOC_WR                          ETH_MACMDIOAR_MOC_WR_Msk /* Write */

+#define ETH_MACMDIOAR_MOC_PRDIA_Pos                   (3U)

+#define ETH_MACMDIOAR_MOC_PRDIA_Msk                   (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos) /*!< 0x00000008 */

+#define ETH_MACMDIOAR_MOC_PRDIA                       ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */

+#define ETH_MACMDIOAR_MOC_RD_Pos                      (2U)

+#define ETH_MACMDIOAR_MOC_RD_Msk                      (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos) /*!< 0x0000000C */

+#define ETH_MACMDIOAR_MOC_RD                          ETH_MACMDIOAR_MOC_RD_Msk /* Read */

+#define ETH_MACMDIOAR_C45E_Pos                        (1U)

+#define ETH_MACMDIOAR_C45E_Msk                        (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */

+#define ETH_MACMDIOAR_C45E                            ETH_MACMDIOAR_C45E_Msk   /* Clause 45 PHY Enable */

+#define ETH_MACMDIOAR_MB_Pos                          (0U)

+#define ETH_MACMDIOAR_MB_Msk                          (0x1UL << ETH_MACMDIOAR_MB_Pos) /*!< 0x00000001 */

+#define ETH_MACMDIOAR_MB                              ETH_MACMDIOAR_MB_Msk     /* MII Busy */

+

+/* Bit definition for Ethernet MAC MDIO Data Register */

+#define ETH_MACMDIODR_RA_Pos                          (16U)

+#define ETH_MACMDIODR_RA_Msk                          (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */

+#define ETH_MACMDIODR_RA                              ETH_MACMDIODR_RA_Msk     /* Register Address */

+#define ETH_MACMDIODR_MD_Pos                          (0U)

+#define ETH_MACMDIODR_MD_Msk                          (0xFFFFUL << ETH_MACMDIODR_MD_Pos) /*!< 0x0000FFFF */

+#define ETH_MACMDIODR_MD                              ETH_MACMDIODR_MD_Msk     /* MII Data */

+

+/* Bit definition for Ethernet ARP Address Register */

+#define ETH_MACARPAR_ARPPA_Pos                         (0U)

+#define ETH_MACARPAR_ARPPA_Msk                         (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACARPAR_ARPPA                             ETH_MACARPAR_ARPPA_Msk     /* ARP Protocol Address */

+

+/* Bit definition for Ethernet MAC Address 0 High Register */

+#define ETH_MACA0HR_AE_Pos                            (31U)

+#define ETH_MACA0HR_AE_Msk                            (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA0HR_AE                                ETH_MACA0HR_AE_Msk /* Address Enable*/

+#define ETH_MACA0HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA0HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA0HR_ADDRHI                            ETH_MACA0HR_ADDRHI_Msk   /* MAC Address 0*/

+

+/* Bit definition for Ethernet MAC Address 0 Low Register */

+#define ETH_MACA0LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA0LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA0LR_ADDRLO                            ETH_MACA0LR_ADDRLO_Msk   /* MAC Address 0*/

+

+/* Bit definition for Ethernet MAC Address 1 High Register */

+#define ETH_MACA1HR_AE_Pos                            (31U)

+#define ETH_MACA1HR_AE_Msk                            (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk /* Address Enable*/

+#define ETH_MACA1HR_SA_Pos                            (30U)

+#define ETH_MACA1HR_SA_Msk                            (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk /* Source Address */

+#define ETH_MACA1HR_MBC_Pos                           (24U)

+#define ETH_MACA1HR_MBC_Msk                           (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk /* Mask Byte Control */

+#define ETH_MACA1HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA1HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA1HR_ADDRHI                            ETH_MACA1HR_ADDRHI_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 1 Low Register */

+#define ETH_MACA1LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA1LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA1LR_ADDRLO                            ETH_MACA1LR_ADDRLO_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 2 High Register */

+#define ETH_MACA2HR_AE_Pos                            (31U)

+#define ETH_MACA2HR_AE_Msk                            (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk /* Address Enable*/

+#define ETH_MACA2HR_SA_Pos                            (30U)

+#define ETH_MACA2HR_SA_Msk                            (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk /* Source Address */

+#define ETH_MACA2HR_MBC_Pos                           (24U)

+#define ETH_MACA2HR_MBC_Msk                           (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk /* Mask Byte Control */

+#define ETH_MACA2HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA2HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA2HR_ADDRHI                            ETH_MACA2HR_ADDRHI_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 2 Low Register */

+#define ETH_MACA2LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA2LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA2LR_ADDRLO                            ETH_MACA2LR_ADDRLO_Msk   /* MAC Address 2*/

+

+/* Bit definition for Ethernet MAC Address 3 High Register */

+#define ETH_MACA3HR_AE_Pos                            (31U)

+#define ETH_MACA3HR_AE_Msk                            (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk /* Address Enable*/

+#define ETH_MACA3HR_SA_Pos                            (30U)

+#define ETH_MACA3HR_SA_Msk                            (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk /* Source Address */

+#define ETH_MACA3HR_MBC_Pos                           (24U)

+#define ETH_MACA3HR_MBC_Msk                           (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk /* Mask Byte Control */

+#define ETH_MACA3HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA3HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA3HR_ADDRHI                            ETH_MACA3HR_ADDRHI_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 3 Low Register */

+#define ETH_MACA3LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA3LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA3LR_ADDRLO                            ETH_MACA3LR_ADDRLO_Msk   /* MAC Address 3*/

+

+/* Bit definition for Ethernet MAC Address High Register */

+#define ETH_MACAHR_AE_Pos                             (31U)

+#define ETH_MACAHR_AE_Msk                             (0x1UL << ETH_MACAHR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACAHR_AE                                 ETH_MACAHR_AE_Msk        /* Address enable */

+#define ETH_MACAHR_SA_Pos                             (30U)

+#define ETH_MACAHR_SA_Msk                             (0x1UL << ETH_MACAHR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACAHR_SA                                 ETH_MACAHR_SA_Msk        /* Source address */

+#define ETH_MACAHR_MBC_Pos                            (24U)

+#define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */

+#define ETH_MACAHR_MBC_HBITS15_8                      ((uint32_t)0x20000000)   /* Mask MAC Address high reg bits [15:8] */

+#define ETH_MACAHR_MBC_HBITS7_0                       ((uint32_t)0x10000000)   /* Mask MAC Address high reg bits [7:0] */

+#define ETH_MACAHR_MBC_LBITS31_24                     ((uint32_t)0x08000000)   /* Mask MAC Address low reg bits [31:24] */

+#define ETH_MACAHR_MBC_LBITS23_16                     ((uint32_t)0x04000000)   /* Mask MAC Address low reg bits [23:16] */

+#define ETH_MACAHR_MBC_LBITS15_8                      ((uint32_t)0x02000000)   /* Mask MAC Address low reg bits [15:8] */

+#define ETH_MACAHR_MBC_LBITS7_0                       ((uint32_t)0x01000000)   /* Mask MAC Address low reg bits [7:0] */

+#define ETH_MACAHR_MACAH_Pos                          (0U)

+#define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */

+#define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */

+

+/* Bit definition for Ethernet MAC Address Low Register */

+#define ETH_MACALR_MACAL_Pos                          (0U)

+#define ETH_MACALR_MACAL_Msk                          (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACALR_MACAL                              ETH_MACALR_MACAL_Msk     /* MAC address low */

+

+/* Bit definition for Ethernet MMC Control Register */

+#define ETH_MMCCR_UCDBC_Pos                           (8U)

+#define ETH_MMCCR_UCDBC_Msk                           (0x1UL << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */

+#define ETH_MMCCR_UCDBC                               ETH_MMCCR_UCDBC_Msk  /* Update MMC Counters for Dropped Broadcast Packets */

+#define ETH_MMCCR_CNTPRSTLVL_Pos                      (5U)

+#define ETH_MMCCR_CNTPRSTLVL_Msk                      (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */

+#define ETH_MMCCR_CNTPRSTLVL                          ETH_MMCCR_CNTPRSTLVL_Msk  /* Full-Half Preset */

+#define ETH_MMCCR_CNTPRST_Pos                         (4U)

+#define ETH_MMCCR_CNTPRST_Msk                         (0x1UL << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */

+#define ETH_MMCCR_CNTPRST                             ETH_MMCCR_CNTPRST_Msk  /* Counters Reset */

+#define ETH_MMCCR_CNTFREEZ_Pos                        (3U)

+#define ETH_MMCCR_CNTFREEZ_Msk                        (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */

+#define ETH_MMCCR_CNTFREEZ                            ETH_MMCCR_CNTFREEZ_Msk  /* MMC Counter Freeze */

+#define ETH_MMCCR_RSTONRD_Pos                         (2U)

+#define ETH_MMCCR_RSTONRD_Msk                         (0x1UL << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */

+#define ETH_MMCCR_RSTONRD                             ETH_MMCCR_RSTONRD_Msk  /* Reset On Read */

+#define ETH_MMCCR_CNTSTOPRO_Pos                       (1U)

+#define ETH_MMCCR_CNTSTOPRO_Msk                       (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */

+#define ETH_MMCCR_CNTSTOPRO                           ETH_MMCCR_CNTSTOPRO_Msk  /* Counter Stop Rollover */

+#define ETH_MMCCR_CNTRST_Pos                          (0U)

+#define ETH_MMCCR_CNTRST_Msk                          (0x1UL << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */

+#define ETH_MMCCR_CNTRST                              ETH_MMCCR_CNTRST_Msk  /* Counters Reset */

+

+/* Bit definition for Ethernet MMC Rx Interrupt Register */

+#define ETH_MMCRIR_RXLPITRCIS_Pos                     (27U)

+#define ETH_MMCRIR_RXLPITRCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) /*!< 0x08000000 */

+#define ETH_MMCRIR_RXLPITRCIS                         ETH_MMCRIR_RXLPITRCIS_Msk  /* MMC Receive LPI transition counter interrupt status */

+#define ETH_MMCRIR_RXLPIUSCIS_Pos                     (26U)

+#define ETH_MMCRIR_RXLPIUSCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */

+#define ETH_MMCRIR_RXLPIUSCIS                         ETH_MMCRIR_RXLPIUSCIS_Msk  /* MMC Receive LPI microsecond counter interrupt status */

+#define ETH_MMCRIR_RXUCGPIS_Pos                       (17U)

+#define ETH_MMCRIR_RXUCGPIS_Msk                       (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) /*!< 0x00020000 */

+#define ETH_MMCRIR_RXUCGPIS                           ETH_MMCRIR_RXUCGPIS_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Status */

+#define ETH_MMCRIR_RXALGNERPIS_Pos                    (6U)

+#define ETH_MMCRIR_RXALGNERPIS_Msk                    (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) /*!< 0x00000040 */

+#define ETH_MMCRIR_RXALGNERPIS                        ETH_MMCRIR_RXALGNERPIS_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Status */

+#define ETH_MMCRIR_RXCRCERPIS_Pos                     (5U)

+#define ETH_MMCRIR_RXCRCERPIS_Msk                     (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) /*!< 0x00000020 */

+#define ETH_MMCRIR_RXCRCERPIS                         ETH_MMCRIR_RXCRCERPIS_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Status */

+

+/* Bit definition for Ethernet MMC Tx Interrupt Register */

+#define ETH_MMCTIR_TXLPITRCIS_Pos                     (27U)

+#define ETH_MMCTIR_TXLPITRCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) /*!< 0x08000000 */

+#define ETH_MMCTIR_TXLPITRCIS                         ETH_MMCTIR_TXLPITRCIS_Msk  /* MMC Transmit LPI transition counter interrupt status */

+#define ETH_MMCTIR_TXLPIUSCIS_Pos                     (26U)

+#define ETH_MMCTIR_TXLPIUSCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */

+#define ETH_MMCTIR_TXLPIUSCIS                         ETH_MMCTIR_TXLPIUSCIS_Msk  /* MMC Transmit LPI microsecond counter interrupt status */

+#define ETH_MMCTIR_TXGPKTIS_Pos                       (21U)

+#define ETH_MMCTIR_TXGPKTIS_Msk                       (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) /*!< 0x00200000 */

+#define ETH_MMCTIR_TXGPKTIS                           ETH_MMCTIR_TXGPKTIS_Msk  /* MMC Transmit Good Packet Counter Interrupt Status */

+#define ETH_MMCTIR_TXMCOLGPIS_Pos                     (15U)

+#define ETH_MMCTIR_TXMCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */

+#define ETH_MMCTIR_TXMCOLGPIS                         ETH_MMCTIR_TXMCOLGPIS_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */

+#define ETH_MMCTIR_TXSCOLGPIS_Pos                     (14U)

+#define ETH_MMCTIR_TXSCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */

+#define ETH_MMCTIR_TXSCOLGPIS                         ETH_MMCTIR_TXSCOLGPIS_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */

+

+/* Bit definition for Ethernet MMC Rx interrupt Mask register */

+#define ETH_MMCRIMR_RXLPITRCIM_Pos                    (27U)

+#define ETH_MMCRIMR_RXLPITRCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */

+#define ETH_MMCRIMR_RXLPITRCIM                        ETH_MMCRIMR_RXLPITRCIM_Msk  /* MMC Receive LPI transition counter interrupt Mask */

+#define ETH_MMCRIMR_RXLPIUSCIM_Pos                    (26U)

+#define ETH_MMCRIMR_RXLPIUSCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */

+#define ETH_MMCRIMR_RXLPIUSCIM                        ETH_MMCRIMR_RXLPIUSCIM_Msk  /* MMC Receive LPI microsecond counter interrupt Mask */

+#define ETH_MMCRIMR_RXUCGPIM_Pos                      (17U)

+#define ETH_MMCRIMR_RXUCGPIM_Msk                      (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) /*!< 0x00020000 */

+#define ETH_MMCRIMR_RXUCGPIM                          ETH_MMCRIMR_RXUCGPIM_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Mask */

+#define ETH_MMCRIMR_RXALGNERPIM_Pos                   (6U)

+#define ETH_MMCRIMR_RXALGNERPIM_Msk                   (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */

+#define ETH_MMCRIMR_RXALGNERPIM                       ETH_MMCRIMR_RXALGNERPIM_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Mask */

+#define ETH_MMCRIMR_RXCRCERPIM_Pos                    (5U)

+#define ETH_MMCRIMR_RXCRCERPIM_Msk                    (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */

+#define ETH_MMCRIMR_RXCRCERPIM                        ETH_MMCRIMR_RXCRCERPIM_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Mask */

+

+/* Bit definition for Ethernet MMC Tx Interrupt Mask Register */

+#define ETH_MMCTIMR_TXLPITRCIM_Pos                    (27U)

+#define ETH_MMCTIMR_TXLPITRCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */

+#define ETH_MMCTIMR_TXLPITRCIM                        ETH_MMCTIMR_TXLPITRCIM_Msk  /* MMC Transmit LPI transition counter interrupt Mask*/

+#define ETH_MMCTIMR_TXLPIUSCIM_Pos                    (26U)

+#define ETH_MMCTIMR_TXLPIUSCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */

+#define ETH_MMCTIMR_TXLPIUSCIM                        ETH_MMCTIMR_TXLPIUSCIM_Msk  /* MMC Transmit LPI microsecond counter interrupt Mask*/

+#define ETH_MMCTIMR_TXGPKTIM_Pos                      (21U)

+#define ETH_MMCTIMR_TXGPKTIM_Msk                      (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) /*!< 0x00200000 */

+#define ETH_MMCTIMR_TXGPKTIM                          ETH_MMCTIMR_TXGPKTIM_Msk  /* MMC Transmit Good Packet Counter Interrupt Mask*/

+#define ETH_MMCTIMR_TXMCOLGPIM_Pos                    (15U)

+#define ETH_MMCTIMR_TXMCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */

+#define ETH_MMCTIMR_TXMCOLGPIM                        ETH_MMCTIMR_TXMCOLGPIM_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */

+#define ETH_MMCTIMR_TXSCOLGPIM_Pos                    (14U)

+#define ETH_MMCTIMR_TXSCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */

+#define ETH_MMCTIMR_TXSCOLGPIM                        ETH_MMCTIMR_TXSCOLGPIM_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */

+

+/* Bit definition for Ethernet MMC Tx Single Collision Good Packets Register */

+#define ETH_MMCTSCGPR_TXSNGLCOLG_Pos                  (0U)

+#define ETH_MMCTSCGPR_TXSNGLCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTSCGPR_TXSNGLCOLG                      ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */

+

+/* Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register */

+#define ETH_MMCTMCGPR_TXMULTCOLG_Pos                  (0U)

+#define ETH_MMCTMCGPR_TXMULTCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTMCGPR_TXMULTCOLG                      ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */

+

+/* Bit definition for Ethernet MMC Tx Packet Count Good Register */

+#define ETH_MMCTPCGR_TXPKTG_Pos                       (0U)

+#define ETH_MMCTPCGR_TXPKTG_msk                       (0xFFFFFFFFUL <<  ETH_MMCTPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTPCGR_TXPKTG                           ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */

+

+/* Bit definition for Ethernet MMC Rx CRC Error Packets Register */

+#define ETH_MMCRCRCEPR_RXCRCERR_Pos                   (0U)

+#define ETH_MMCRCRCEPR_RXCRCERR_msk                   (0xFFFFFFFFUL <<  ETH_MMCRCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRCRCEPR_RXCRCERR                       ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */

+

+/* Bit definition for Ethernet MMC Rx alignment error packets register */

+#define ETH_MMCRAEPR_RXALGNERR_Pos                    (0U)

+#define ETH_MMCRAEPR_RXALGNERR_msk                    (0xFFFFFFFFUL <<  ETH_MMCRAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRAEPR_RXALGNERR                        ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */

+

+/* Bit definition for Ethernet MMC Rx Unicast Packets Good Register */

+#define ETH_MMCRUPGR_RXUCASTG_Pos                     (0U)

+#define ETH_MMCRUPGR_RXUCASTG_msk                     (0xFFFFFFFFUL <<  ETH_MMCRUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRUPGR_RXUCASTG                         ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */

+

+/* Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register */

+#define ETH_MMCTLPIMSTR_TXLPIUSC_Pos                  (0U)

+#define ETH_MMCTLPIMSTR_TXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCTLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTLPIMSTR_TXLPIUSC                      ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */

+

+/* Bit definition for Ethernet MMC Tx LPI Transition Counter Register */

+#define ETH_MMCTLPITCR_TXLPITRC_Pos                   (0U)

+#define ETH_MMCTLPITCR_TXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCTLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTLPITCR_TXLPITRC                       ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */

+

+/* Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register */

+#define ETH_MMCRLPIMSTR_RXLPIUSC_Pos                  (0U)

+#define ETH_MMCRLPIMSTR_RXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCRLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRLPIMSTR_RXLPIUSC                      ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */

+

+/* Bit definition for Ethernet MMC Rx LPI Transition Counter Register */

+#define ETH_MMCRLPITCR_RXLPITRC_Pos                   (0U)

+#define ETH_MMCRLPITCR_RXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCRLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRLPITCR_RXLPITRC                       ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */

+

+/* Bit definition for Ethernet MAC L3 L4 Control Register */

+#define ETH_MACL3L4CR_L4DPIM_Pos                      (21U)

+#define ETH_MACL3L4CR_L4DPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos) /*!< 0x00200000 */

+#define ETH_MACL3L4CR_L4DPIM                          ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */

+#define ETH_MACL3L4CR_L4DPM_Pos                       (20U)

+#define ETH_MACL3L4CR_L4DPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4DPM_Pos) /*!< 0x00100000 */

+#define ETH_MACL3L4CR_L4DPM                           ETH_MACL3L4CR_L4DPM_Msk  /* Layer 4 Destination Port Match Enable */

+#define ETH_MACL3L4CR_L4SPIM_Pos                      (19U)

+#define ETH_MACL3L4CR_L4SPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos) /*!< 0x00080000 */

+#define ETH_MACL3L4CR_L4SPIM                          ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */

+#define ETH_MACL3L4CR_L4SPM_Pos                       (18U)

+#define ETH_MACL3L4CR_L4SPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4SPM_Pos) /*!< 0x00040000 */

+#define ETH_MACL3L4CR_L4SPM                           ETH_MACL3L4CR_L4SPM_Msk  /* Layer 4 Source Port Match Enable */

+#define ETH_MACL3L4CR_L4PEN_Pos                       (16U)

+#define ETH_MACL3L4CR_L4PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L4PEN_Pos) /*!< 0x00010000 */

+#define ETH_MACL3L4CR_L4PEN                           ETH_MACL3L4CR_L4PEN_Msk  /* Layer 4 Protocol Enable */

+#define ETH_MACL3L4CR_L3HDBM_Pos                      (11U)

+#define ETH_MACL3L4CR_L3HDBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos) /*!< 0x0000F800 */

+#define ETH_MACL3L4CR_L3HDBM                          ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */

+#define ETH_MACL3L4CR_L3HSBM_Pos                      (6U)

+#define ETH_MACL3L4CR_L3HSBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos) /*!< 0x000007C0 */

+#define ETH_MACL3L4CR_L3HSBM                          ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */

+#define ETH_MACL3L4CR_L3DAIM_Pos                      (5U)

+#define ETH_MACL3L4CR_L3DAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos) /*!< 0x00000020 */

+#define ETH_MACL3L4CR_L3DAIM                          ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */

+#define ETH_MACL3L4CR_L3DAM_Pos                       (4U)

+#define ETH_MACL3L4CR_L3DAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3DAM_Pos) /*!< 0x00000010 */

+#define ETH_MACL3L4CR_L3DAM                           ETH_MACL3L4CR_L3DAM_Msk  /* Layer 3 IP DA Match Enable */

+#define ETH_MACL3L4CR_L3SAIM_Pos                      (3U)

+#define ETH_MACL3L4CR_L3SAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos) /*!< 0x00000008 */

+#define ETH_MACL3L4CR_L3SAIM                          ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */

+#define ETH_MACL3L4CR_L3SAM_Pos                       (2U)

+#define ETH_MACL3L4CR_L3SAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3SAM_Pos) /*!< 0x00000004 */

+#define ETH_MACL3L4CR_L3SAM                           ETH_MACL3L4CR_L3SAM_Msk  /* Layer 3 IP SA Match Enable*/

+#define ETH_MACL3L4CR_L3PEN_Pos                       (0U)

+#define ETH_MACL3L4CR_L3PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L3PEN_Pos) /*!< 0x00000001 */

+#define ETH_MACL3L4CR_L3PEN                           ETH_MACL3L4CR_L3PEN_Msk  /* Layer 3 Protocol Enable */

+

+/* Bit definition for Ethernet MAC L4 Address Register */

+#define ETH_MACL4AR_L4DP_Pos                          (16U)

+#define ETH_MACL4AR_L4DP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4DP_Pos) /*!< 0xFFFF0000 */

+#define ETH_MACL4AR_L4DP                              ETH_MACL4AR_L4DP_Msk     /* Layer 4 Destination Port Number Field */

+#define ETH_MACL4AR_L4SP_Pos                          (0U)

+#define ETH_MACL4AR_L4SP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4SP_Pos) /*!< 0x0000FFFF */

+#define ETH_MACL4AR_L4SP                              ETH_MACL4AR_L4SP_Msk     /* Layer 4 Source Port Number Field */

+

+/* Bit definition for Ethernet MAC L3 Address0 Register */

+#define ETH_MACL3A0R_L3A0_Pos                         (0U)

+#define ETH_MACL3A0R_L3A0_Msk                         (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A0R_L3A0                             ETH_MACL3A0R_L3A0_Msk    /* Layer 3 Address 0 Field */

+

+/* Bit definition for Ethernet MAC L4 Address1 Register */

+#define ETH_MACL3A1R_L3A1_Pos                         (0U)

+#define ETH_MACL3A1R_L3A1_Msk                         (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A1R_L3A1                             ETH_MACL3A1R_L3A1_Msk    /* Layer 3 Address 1 Field */

+

+/* Bit definition for Ethernet MAC L4 Address2 Register */

+#define ETH_MACL3A2R_L3A2_Pos                         (0U)

+#define ETH_MACL3A2R_L3A2_Msk                         (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A2R_L3A2                             ETH_MACL3A2R_L3A2_Msk    /* Layer 3 Address 2 Field */

+

+/* Bit definition for Ethernet MAC L4 Address3 Register */

+#define ETH_MACL3A3R_L3A3_Pos                         (0U)

+#define ETH_MACL3A3R_L3A3_Msk                         (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A3R_L3A3                             ETH_MACL3A3R_L3A3_Msk    /* Layer 3 Address 3 Field */

+

+/* Bit definition for Ethernet MAC Timestamp Control Register */

+#define ETH_MACTSCR_TXTSSTSM_Pos                      (24U)

+#define ETH_MACTSCR_TXTSSTSM_Msk                      (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */

+#define ETH_MACTSCR_TXTSSTSM                          ETH_MACTSCR_TXTSSTSM_Msk  /* Transmit Timestamp Status Mode */

+#define ETH_MACTSCR_CSC_Pos                           (19U)

+#define ETH_MACTSCR_CSC_Msk                           (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */

+#define ETH_MACTSCR_CSC                               ETH_MACTSCR_CSC_Msk  /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */

+#define ETH_MACTSCR_TSENMACADDR_Pos                   (18U)

+#define ETH_MACTSCR_TSENMACADDR_Msk                   (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */

+#define ETH_MACTSCR_TSENMACADDR                       ETH_MACTSCR_TSENMACADDR_Msk  /* Enable MAC Address for PTP Packet Filtering */

+#define ETH_MACTSCR_SNAPTYPSEL_Pos                    (16U)

+#define ETH_MACTSCR_SNAPTYPSEL_Msk                    (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */

+#define ETH_MACTSCR_SNAPTYPSEL                        ETH_MACTSCR_SNAPTYPSEL_Msk  /* Select PTP packets for Taking Snapshots */

+#define ETH_MACTSCR_TSMSTRENA_Pos                     (15U)

+#define ETH_MACTSCR_TSMSTRENA_Msk                     (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */

+#define ETH_MACTSCR_TSMSTRENA                         ETH_MACTSCR_TSMSTRENA_Msk  /* Enable Snapshot for Messages Relevant to Master */

+#define ETH_MACTSCR_TSEVNTENA_Pos                     (14U)

+#define ETH_MACTSCR_TSEVNTENA_Msk                     (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */

+#define ETH_MACTSCR_TSEVNTENA                         ETH_MACTSCR_TSEVNTENA_Msk  /* Enable Timestamp Snapshot for Event Messages */

+#define ETH_MACTSCR_TSIPV4ENA_Pos                     (13U)

+#define ETH_MACTSCR_TSIPV4ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */

+#define ETH_MACTSCR_TSIPV4ENA                         ETH_MACTSCR_TSIPV4ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv4-UDP */

+#define ETH_MACTSCR_TSIPV6ENA_Pos                     (12U)

+#define ETH_MACTSCR_TSIPV6ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */

+#define ETH_MACTSCR_TSIPV6ENA                         ETH_MACTSCR_TSIPV6ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv6-UDP */

+#define ETH_MACTSCR_TSIPENA_Pos                       (11U)

+#define ETH_MACTSCR_TSIPENA_Msk                       (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */

+#define ETH_MACTSCR_TSIPENA                           ETH_MACTSCR_TSIPENA_Msk  /* Enable Processing of PTP over Ethernet Packets */

+#define ETH_MACTSCR_TSVER2ENA_Pos                     (10U)

+#define ETH_MACTSCR_TSVER2ENA_Msk                     (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */

+#define ETH_MACTSCR_TSVER2ENA                         ETH_MACTSCR_TSVER2ENA_Msk  /* Enable PTP Packet Processing for Version 2 Format */

+#define ETH_MACTSCR_TSCTRLSSR_Pos                     (9U)

+#define ETH_MACTSCR_TSCTRLSSR_Msk                     (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */

+#define ETH_MACTSCR_TSCTRLSSR                         ETH_MACTSCR_TSCTRLSSR_Msk  /* Timestamp Digital or Binary Rollover Control */

+#define ETH_MACTSCR_TSENALL_Pos                       (8U)

+#define ETH_MACTSCR_TSENALL_Msk                       (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */

+#define ETH_MACTSCR_TSENALL                           ETH_MACTSCR_TSENALL_Msk  /* Enable Timestamp for All Packets */

+#define ETH_MACTSCR_TSADDREG_Pos                      (5U)

+#define ETH_MACTSCR_TSADDREG_Msk                      (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */

+#define ETH_MACTSCR_TSADDREG                          ETH_MACTSCR_TSADDREG_Msk  /* Update Addend Register */

+#define ETH_MACTSCR_TSUPDT_Pos                        (3U)

+#define ETH_MACTSCR_TSUPDT_Msk                        (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */

+#define ETH_MACTSCR_TSUPDT                            ETH_MACTSCR_TSUPDT_Msk  /* Update Timestamp */

+#define ETH_MACTSCR_TSINIT_Pos                        (2U)

+#define ETH_MACTSCR_TSINIT_Msk                        (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */

+#define ETH_MACTSCR_TSINIT                             ETH_MACTSCR_TSINIT_Msk  /* Initialize Timestamp */

+#define ETH_MACTSCR_TSCFUPDT_Pos                      (1U)

+#define ETH_MACTSCR_TSCFUPDT_Msk                      (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */

+#define ETH_MACTSCR_TSCFUPDT                          ETH_MACTSCR_TSCFUPDT_Msk  /* Fine or Coarse Timestamp Update*/

+#define ETH_MACTSCR_TSENA_Pos                         (0U)

+#define ETH_MACTSCR_TSENA_Msk                         (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */

+#define ETH_MACTSCR_TSENA                             ETH_MACTSCR_TSENA_Msk  /* Enable Timestamp */

+

+/* Bit definition for Ethernet MAC Sub-second Increment Register */

+#define ETH_MACMACSSIR_SSINC_Pos                      (16U)

+#define ETH_MACMACSSIR_SSINC_Msk                      (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) /*!< 0x0000FF00 */

+#define ETH_MACMACSSIR_SSINC                          ETH_MACMACSSIR_SSINC_Msk  /* Sub-second Increment Value */

+#define ETH_MACMACSSIR_SNSINC_Pos                     (8U)

+#define ETH_MACMACSSIR_SNSINC_Msk                     (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos) /*!< 0x000000FF */

+#define ETH_MACMACSSIR_SNSINC                         ETH_MACMACSSIR_SNSINC_Msk  /* Sub-nanosecond Increment Value */

+

+/* Bit definition for Ethernet MAC System Time Seconds Register */

+#define ETH_MACSTSR_TSS_Pos                           (0U)

+#define ETH_MACSTSR_TSS_Msk                           (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSTSR_TSS                               ETH_MACSTSR_TSS_Msk  /* Timestamp Second */

+

+/* Bit definition for Ethernet MAC System Time Nanoseconds Register */

+#define ETH_MACSTNR_TSSS_Pos                          (0U)

+#define ETH_MACSTNR_TSSS_Msk                          (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACSTNR_TSSS                              ETH_MACSTNR_TSSS_Msk  /* Timestamp Sub-seconds */

+

+/* Bit definition for Ethernet MAC System Time Seconds Update Register */

+#define ETH_MACSTSUR_TSS_Pos                          (0U)

+#define ETH_MACSTSUR_TSS_Msk                          (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSTSUR_TSS                              ETH_MACSTSUR_TSS_Msk  /* Timestamp Seconds */

+

+/* Bit definition for Ethernet MAC System Time Nanoseconds Update Register */

+#define ETH_MACSTNUR_ADDSUB_Pos                       (31U)

+#define ETH_MACSTNUR_ADDSUB_Msk                       (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */

+#define ETH_MACSTNUR_ADDSUB                           ETH_MACSTNUR_ADDSUB_Msk  /* Add or Subtract Time */

+#define ETH_MACSTNUR_TSSS_Pos                         (0U)

+#define ETH_MACSTNUR_TSSS_Msk                         (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACSTNUR_TSSS                             ETH_MACSTNUR_TSSS_Msk  /* Timestamp Sub-seconds */

+

+/* Bit definition for Ethernet MAC Timestamp Addend Register */

+#define ETH_MACTSAR_TSAR_Pos                          (0U)

+#define ETH_MACTSAR_TSAR_Msk                          (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSAR_TSAR                              ETH_MACTSAR_TSAR_Msk  /* Timestamp Addend Register */

+

+/* Bit definition for Ethernet MAC Timestamp Status Register */

+#define ETH_MACTSSR_ATSNS_Pos                         (25U)

+#define ETH_MACTSSR_ATSNS_Msk                         (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */

+#define ETH_MACTSSR_ATSNS                             ETH_MACTSSR_ATSNS_Msk  /* Number of Auxiliary Timestamp Snapshots */

+#define ETH_MACTSSR_ATSSTM_Pos                        (24U)

+#define ETH_MACTSSR_ATSSTM_Msk                        (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */

+#define ETH_MACTSSR_ATSSTM                            ETH_MACTSSR_ATSSTM_Msk  /* Auxiliary Timestamp Snapshot Trigger Missed */

+#define ETH_MACTSSR_ATSSTN_Pos                        (16U)

+#define ETH_MACTSSR_ATSSTN_Msk                        (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */

+#define ETH_MACTSSR_ATSSTN                            ETH_MACTSSR_ATSSTN_Msk  /* Auxiliary Timestamp Snapshot Trigger Identifier */

+#define ETH_MACTSSR_TXTSSIS_Pos                       (15U)

+#define ETH_MACTSSR_TXTSSIS_Msk                       (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */

+#define ETH_MACTSSR_TXTSSIS                           ETH_MACTSSR_TXTSSIS_Msk  /* Tx Timestamp Status Interrupt Status */

+#define ETH_MACTSSR_TSTRGTERR0_Pos                    (3U)

+#define ETH_MACTSSR_TSTRGTERR0_Msk                    (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */

+#define ETH_MACTSSR_TSTRGTERR0                        ETH_MACTSSR_TSTRGTERR0_Msk  /* Timestamp Target Time Error */

+#define ETH_MACTSSR_AUXTSTRIG_Pos                     (2U)

+#define ETH_MACTSSR_AUXTSTRIG_Msk                     (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */

+#define ETH_MACTSSR_AUXTSTRIG                         ETH_MACTSSR_AUXTSTRIG_Msk  /* Auxiliary Timestamp Trigger Snapshot*/

+#define ETH_MACTSSR_TSTARGT0_Pos                      (1U)

+#define ETH_MACTSSR_TSTARGT0_Msk                      (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */

+#define ETH_MACTSSR_TSTARGT0                          ETH_MACTSSR_TSTARGT0_Msk  /* Timestamp Target Time Reached */

+#define ETH_MACTSSR_TSSOVF_Pos                        (0U)

+#define ETH_MACTSSR_TSSOVF_Msk                        (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */

+#define ETH_MACTSSR_TSSOVF                            ETH_MACTSSR_TSSOVF_Msk  /* Timestamp Seconds Overflow */

+

+/* Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register */

+#define ETH_MACTTSSNR_TXTSSMIS_Pos                    (31U)

+#define ETH_MACTTSSNR_TXTSSMIS_Msk                    (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */

+#define ETH_MACTTSSNR_TXTSSMIS                        ETH_MACTTSSNR_TXTSSMIS_Msk  /* Transmit Timestamp Status Missed */

+#define ETH_MACTTSSNR_TXTSSLO_Pos                     (0U)

+#define ETH_MACTTSSNR_TXTSSLO_Msk                     (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACTTSSNR_TXTSSLO                         ETH_MACTTSSNR_TXTSSLO_Msk  /* Transmit Timestamp Status Low */

+

+/* Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register */

+#define ETH_MACTTSSSR_TXTSSHI_Pos                     (0U)

+#define ETH_MACTTSSSR_TXTSSHI_Msk                     (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTTSSSR_TXTSSHI                         ETH_MACTTSSSR_TXTSSHI_Msk  /* Transmit Timestamp Status High */

+

+/* Bit definition for Ethernet MAC Auxiliary Control Register*/

+#define ETH_MACACR_ATSEN3_Pos                         (7U)

+#define ETH_MACACR_ATSEN3_Msk                         (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */

+#define ETH_MACACR_ATSEN3                             ETH_MACACR_ATSEN3_Msk  /* Auxiliary Snapshot 3 Enable */

+#define ETH_MACACR_ATSEN2_Pos                         (6U)

+#define ETH_MACACR_ATSEN2_Msk                         (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */

+#define ETH_MACACR_ATSEN2                             ETH_MACACR_ATSEN2_Msk  /* Auxiliary Snapshot 2 Enable */

+#define ETH_MACACR_ATSEN1_Pos                         (5U)

+#define ETH_MACACR_ATSEN1_Msk                         (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */

+#define ETH_MACACR_ATSEN1                             ETH_MACACR_ATSEN1_Msk  /* Auxiliary Snapshot 1 Enable */

+#define ETH_MACACR_ATSEN0_Pos                         (4U)

+#define ETH_MACACR_ATSEN0_Msk                         (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */

+#define ETH_MACACR_ATSEN0                             ETH_MACACR_ATSEN0_Msk  /* Auxiliary Snapshot 0 Enable */

+#define ETH_MACACR_ATSFC_Pos                          (0U)

+#define ETH_MACACR_ATSFC_Msk                          (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */

+#define ETH_MACACR_ATSFC                              ETH_MACACR_ATSFC_Msk  /* Auxiliary Snapshot FIFO Clear */

+

+/* Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register */

+#define ETH_MACATSNR_AUXTSLO_Pos                      (0U)

+#define ETH_MACATSNR_AUXTSLO_Msk                      (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACATSNR_AUXTSLO                          ETH_MACATSNR_AUXTSLO_Msk  /* Auxiliary Timestamp */

+

+/* Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register */

+#define ETH_MACATSSR_AUXTSHI_Pos                      (0U)

+#define ETH_MACATSSR_AUXTSHI_Msk                      (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACATSSR_AUXTSHI                          ETH_MACATSSR_AUXTSHI_Msk  /* Auxiliary Timestamp */

+

+/* Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register */

+#define ETH_MACTSIACR_OSTIAC_Pos                      (0U)

+#define ETH_MACTSIACR_OSTIAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSIACR_OSTIAC                          ETH_MACTSIACR_OSTIAC_Msk  /* One-Step Timestamp Ingress Asymmetry Correction */

+

+/* Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction Register */

+#define ETH_MACTSEACR_OSTEAC_Pos                      (0U)

+#define ETH_MACTSEACR_OSTEAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSEACR_OSTEAC                          ETH_MACTSEACR_OSTEAC_Msk  /* One-Step Timestamp Egress Asymmetry Correction */

+

+/* Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond Register */

+#define ETH_MACTSICNR_TSIC_Pos                        (0U)

+#define ETH_MACTSICNR_TSIC_Msk                        (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSICNR_TSIC                            ETH_MACTSICNR_TSIC_Msk  /* Timestamp Ingress Correction */

+

+/* Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond Register */

+#define ETH_MACTSECNR_TSEC_Pos                        (0U)

+#define ETH_MACTSECNR_TSEC_Msk                        (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSECNR_TSEC                            ETH_MACTSECNR_TSEC_Msk  /* Timestamp Egress Correction */

+

+/* Bit definition for Ethernet MAC PPS Control Register */

+#define ETH_MACPPSCR_TRGTMODSEL0_Pos                  (5U)

+#define ETH_MACPPSCR_TRGTMODSEL0_Msk                  (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */

+#define ETH_MACPPSCR_TRGTMODSEL0                      ETH_MACPPSCR_TRGTMODSEL0_Msk  /* Target Time Register Mode for PPS Output */

+#define ETH_MACPPSCR_PPSEN0_Pos                       (4U)

+#define ETH_MACPPSCR_PPSEN0_Msk                       (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */

+#define ETH_MACPPSCR_PPSEN0                           ETH_MACPPSCR_PPSEN0_Msk  /* Flexible PPS Output Mode Enable */

+#define ETH_MACPPSCR_PPSCTRL_Pos                      (0U)

+#define ETH_MACPPSCR_PPSCTRL_Msk                      (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */

+#define ETH_MACPPSCR_PPSCTRL                          ETH_MACPPSCR_PPSCTRL_Msk  /* PPS Output Frequency Control */

+

+/* Bit definition for Ethernet MAC PPS Target Time Seconds Register */

+#define ETH_MACPPSTTSR_TSTRH0_Pos                     (0U)

+#define ETH_MACPPSTTSR_TSTRH0_Msk                     (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACPPSTTSR_TSTRH0                         ETH_MACPPSTTSR_TSTRH0_Msk  /* PPS Target Time Seconds Register */

+

+/* Bit definition for Ethernet MAC PPS Target Time Nanoseconds Register */

+#define ETH_MACPPSTTNR_TRGTBUSY0_Pos                  (31U)

+#define ETH_MACPPSTTNR_TRGTBUSY0_Msk                  (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos) /*!< 0x80000000 */

+#define ETH_MACPPSTTNR_TRGTBUSY0                      ETH_MACPPSTTNR_TRGTBUSY0_Msk  /* PPS Target Time Register Busy */

+#define ETH_MACPPSTTNR_TTSL0_Pos                      (0U)

+#define ETH_MACPPSTTNR_TTSL0_Msk                      (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACPPSTTNR_TTSL0                          ETH_MACPPSTTNR_TTSL0_Msk  /* Target Time Low for PPS Register */

+

+/* Bit definition for Ethernet MAC PPS Interval Register */

+#define ETH_MACPPSIR_PPSINT0_Pos                      (0U)

+#define ETH_MACPPSIR_PPSINT0_Msk                      (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACPPSIR_PPSINT0                          ETH_MACPPSIR_PPSINT0_Msk  /* PPS Output Signal Interval */

+

+/* Bit definition for Ethernet MAC PPS Width Register */

+#define ETH_MACPPSWR_PPSWIDTH0_Pos                    (0U)

+#define ETH_MACPPSWR_PPSWIDTH0_Msk                    (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACPPSWR_PPSWIDTH0                        ETH_MACPPSWR_PPSWIDTH0_Msk  /* PPS Output Signal Width */

+

+/* Bit definition for Ethernet MAC PTP Offload Control Register */

+#define ETH_MACPOCR_DN_Pos                            (8U)

+#define ETH_MACPOCR_DN_Msk                            (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */

+#define ETH_MACPOCR_DN                                ETH_MACPOCR_DN_Msk  /* Domain Number */

+#define ETH_MACPOCR_DRRDIS_Pos                        (6U)

+#define ETH_MACPOCR_DRRDIS_Msk                        (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */

+#define ETH_MACPOCR_DRRDIS                            ETH_MACPOCR_DRRDIS_Msk  /* Disable PTO Delay Request/Response response generation */

+#define ETH_MACPOCR_APDREQTRIG_Pos                    (5U)

+#define ETH_MACPOCR_APDREQTRIG_Msk                    (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */

+#define ETH_MACPOCR_APDREQTRIG                        ETH_MACPOCR_APDREQTRIG_Msk  /* Automatic PTP Pdelay_Req message Trigger */

+#define ETH_MACPOCR_ASYNCTRIG_Pos                     (4U)

+#define ETH_MACPOCR_ASYNCTRIG_Msk                     (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */

+#define ETH_MACPOCR_ASYNCTRIG                         ETH_MACPOCR_ASYNCTRIG_Msk  /* Automatic PTP SYNC message Trigger */

+#define ETH_MACPOCR_APDREQEN_Pos                      (2U)

+#define ETH_MACPOCR_APDREQEN_Msk                      (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */

+#define ETH_MACPOCR_APDREQEN                          ETH_MACPOCR_APDREQEN_Msk  /* Automatic PTP Pdelay_Req message Enable */

+#define ETH_MACPOCR_ASYNCEN_Pos                       (1U)

+#define ETH_MACPOCR_ASYNCEN_Msk                       (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */

+#define ETH_MACPOCR_ASYNCEN                           ETH_MACPOCR_ASYNCEN_Msk  /* Automatic PTP SYNC message Enable */

+#define ETH_MACPOCR_PTOEN_Pos                         (0U)

+#define ETH_MACPOCR_PTOEN_Msk                         (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */

+#define ETH_MACPOCR_PTOEN                             ETH_MACPOCR_PTOEN_Msk  /* PTP Offload Enable */

+

+/* Bit definition for Ethernet MAC PTP Source Port Identity 0 Register */

+#define ETH_MACSPI0R_SPI0_Pos                         (0U)

+#define ETH_MACSPI0R_SPI0_Msk                         (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSPI0R_SPI0                             ETH_MACSPI0R_SPI0_Msk  /* Source Port Identity 0 */

+

+/* Bit definition for Ethernet MAC PTP Source Port Identity 1 Register */

+#define ETH_MACSPI1R_SPI1_Pos                         (0U)

+#define ETH_MACSPI1R_SPI1_Msk                         (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSPI1R_SPI1                             ETH_MACSPI1R_SPI1_Msk  /* Source Port Identity 1 */

+

+/* Bit definition for Ethernet MAC PTP Source Port Identity 2 Register */

+#define ETH_MACSPI2R_SPI2_Pos                         (0U)

+#define ETH_MACSPI2R_SPI2_Msk                         (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */

+#define ETH_MACSPI2R_SPI2                             ETH_MACSPI2R_SPI2_Msk  /* Source Port Identity 2 */

+

+/* Bit definition for Ethernet MAC Log Message Interval Register */

+#define ETH_MACLMIR_LMPDRI_Pos                        (24U)

+#define ETH_MACLMIR_LMPDRI_Msk                        (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */

+#define ETH_MACLMIR_LMPDRI                             ETH_MACLMIR_LMPDRI_Msk  /* Log Min Pdelay_Req Interval */

+#define ETH_MACLMIR_DRSYNCR_Pos                       (8U)

+#define ETH_MACLMIR_DRSYNCR_Msk                       (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */

+#define ETH_MACLMIR_DRSYNCR                           ETH_MACLMIR_DRSYNCR_Msk  /* Delay_Req to SYNC Ratio */

+#define ETH_MACLMIR_LSI_Pos                           (0U)

+#define ETH_MACLMIR_LSI_Msk                           (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */

+#define ETH_MACLMIR_LSI                               ETH_MACLMIR_LSI_Msk  /* Log Sync Interval */

+

+/* Bit definition for Ethernet MTL Operation Mode Register */

+#define ETH_MTLOMR_CNTCLR_Pos                         (9U)

+#define ETH_MTLOMR_CNTCLR_Msk                         (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */

+#define ETH_MTLOMR_CNTCLR                             ETH_MTLOMR_CNTCLR_Msk    /* Counters Reset */

+#define ETH_MTLOMR_CNTPRST_Pos                        (8U)

+#define ETH_MTLOMR_CNTPRST_Msk                        (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */

+#define ETH_MTLOMR_CNTPRST                            ETH_MTLOMR_CNTPRST_Msk   /* Counters Preset */

+#define ETH_MTLOMR_DTXSTS_Pos                         (1U)

+#define ETH_MTLOMR_DTXSTS_Msk                         (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */

+#define ETH_MTLOMR_DTXSTS                             ETH_MTLOMR_DTXSTS_Msk  /* Drop Transmit Status */

+

+/* Bit definition for Ethernet MTL Interrupt Status Register */

+#define ETH_MTLISR_MACIS_Pos                          (16U)

+#define ETH_MTLISR_MACIS_Msk                          (0x1UL << ETH_MTLISR_MACIS_Pos) /*!< 0x00010000 */

+#define ETH_MTLISR_MACIS                              ETH_MTLISR_MACIS_Msk     /* MAC Interrupt Status */

+#define ETH_MTLISR_QIS_Pos                            (0U)

+#define ETH_MTLISR_QIS_Msk                            (0x1UL << ETH_MTLISR_QIS_Pos) /*!< 0x00000001 */

+#define ETH_MTLISR_QIS                                ETH_MTLISR_QIS_Msk       /* Queue Interrupt status */

+

+/* Bit definition for Ethernet MTL Tx Queue Operation Mode Register */

+#define ETH_MTLTQOMR_TTC_Pos                          (4U)

+#define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */

+#define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */

+#define ETH_MTLTQOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */

+#define ETH_MTLTQOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */

+#define ETH_MTLTQOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */

+#define ETH_MTLTQOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */

+#define ETH_MTLTQOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */

+#define ETH_MTLTQOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */

+#define ETH_MTLTQOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */

+#define ETH_MTLTQOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */

+#define ETH_MTLTQOMR_TSF_Pos                          (1U)

+#define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */

+#define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */

+#define ETH_MTLTQOMR_FTQ_Pos                          (0U)

+#define ETH_MTLTQOMR_FTQ_Msk                          (0x1UL << ETH_MTLTQOMR_FTQ_Pos) /*!< 0x00000001 */

+#define ETH_MTLTQOMR_FTQ                              ETH_MTLTQOMR_FTQ_Msk     /* Flush Transmit Queue */

+

+/* Bit definition for Ethernet MTL Tx Queue Underflow Register */

+#define ETH_MTLTQUR_UFCNTOVF_Pos                      (11U)

+#define ETH_MTLTQUR_UFCNTOVF_Msk                      (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos) /*!< 0x00000800 */

+#define ETH_MTLTQUR_UFCNTOVF                          ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */

+#define ETH_MTLTQUR_UFPKTCNT_Pos                      (0U)

+#define ETH_MTLTQUR_UFPKTCNT_Msk                      (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos) /*!< 0x000007FF */

+#define ETH_MTLTQUR_UFPKTCNT                          ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */

+

+/* Bit definition for Ethernet MTL Tx Queue Debug Register */

+#define ETH_MTLTQDR_STXSTSF_Pos                       (20U)

+#define ETH_MTLTQDR_STXSTSF_Msk                       (0x7UL << ETH_MTLTQDR_STXSTSF_Pos) /*!< 0x00700000 */

+#define ETH_MTLTQDR_STXSTSF                           ETH_MTLTQDR_STXSTSF_Msk  /* Number of Status Words in the Tx Status FIFO of Queue */

+#define ETH_MTLTQDR_PTXQ_Pos                          (16U)

+#define ETH_MTLTQDR_PTXQ_Msk                          (0x7UL << ETH_MTLTQDR_PTXQ_Pos) /*!< 0x00070000 */

+#define ETH_MTLTQDR_PTXQ                              ETH_MTLTQDR_PTXQ_Msk     /* Number of Packets in the Transmit Queue */

+#define ETH_MTLTQDR_TXSTSFSTS_Pos                     (5U)

+#define ETH_MTLTQDR_TXSTSFSTS_Msk                     (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos) /*!< 0x00000020 */

+#define ETH_MTLTQDR_TXSTSFSTS                         ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */

+#define ETH_MTLTQDR_TXQSTS_Pos                        (4U)

+#define ETH_MTLTQDR_TXQSTS_Msk                        (0x1UL << ETH_MTLTQDR_TXQSTS_Pos) /*!< 0x00000010 */

+#define ETH_MTLTQDR_TXQSTS                            ETH_MTLTQDR_TXQSTS_Msk   /* MTL Tx Queue Not Empty Status */

+#define ETH_MTLTQDR_TWCSTS_Pos                        (3U)

+#define ETH_MTLTQDR_TWCSTS_Msk                        (0x1UL << ETH_MTLTQDR_TWCSTS_Pos) /*!< 0x00000008 */

+#define ETH_MTLTQDR_TWCSTS                            ETH_MTLTQDR_TWCSTS_Msk   /* MTL Tx Queue Write Controller Status */

+#define ETH_MTLTQDR_TRCSTS_Pos                        (1U)

+#define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */

+#define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */

+#define ETH_MTLTQDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */

+#define ETH_MTLTQDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */

+#define ETH_MTLTQDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */

+#define ETH_MTLTQDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */

+#define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)

+#define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */

+#define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */

+

+/* Bit definition for Ethernet MTL Queue Interrupt Control Status Register */

+#define ETH_MTLQICSR_RXOIE_Pos                        (24U)

+#define ETH_MTLQICSR_RXOIE_Msk                        (0x1UL << ETH_MTLQICSR_RXOIE_Pos) /*!< 0x01000000 */

+#define ETH_MTLQICSR_RXOIE                            ETH_MTLQICSR_RXOIE_Msk   /* Receive Queue Overflow Interrupt Enable */

+#define ETH_MTLQICSR_RXOVFIS_Pos                      (16U)

+#define ETH_MTLQICSR_RXOVFIS_Msk                      (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos) /*!< 0x00010000 */

+#define ETH_MTLQICSR_RXOVFIS                          ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */

+#define ETH_MTLQICSR_TXUIE_Pos                        (8U)

+#define ETH_MTLQICSR_TXUIE_Msk                        (0x1UL << ETH_MTLQICSR_TXUIE_Pos) /*!< 0x00000100 */

+#define ETH_MTLQICSR_TXUIE                            ETH_MTLQICSR_TXUIE_Msk   /* Transmit Queue Underflow Interrupt Enable */

+#define ETH_MTLQICSR_TXUNFIS_Pos                      (0U)

+#define ETH_MTLQICSR_TXUNFIS_Msk                      (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos) /*!< 0x00000001 */

+#define ETH_MTLQICSR_TXUNFIS                          ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */

+

+/* Bit definition for Ethernet MTL Rx Queue Operation Mode Register */

+#define ETH_MTLRQOMR_RQS_Pos                          (20U)

+#define ETH_MTLRQOMR_RQS_Msk                          (0x7UL << ETH_MTLRQOMR_RQS_Pos) /*!< 0x00700000 */

+#define ETH_MTLRQOMR_RQS                              ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */

+#define ETH_MTLRQOMR_RFD_Pos                          (14U)

+#define ETH_MTLRQOMR_RFD_Msk                          (0x7UL << ETH_MTLRQOMR_RFD_Pos) /*!< 0x0001C000 */

+#define ETH_MTLRQOMR_RFD                              ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */

+#define ETH_MTLRQOMR_RFA_Pos                          (8U)

+#define ETH_MTLRQOMR_RFA_Msk                          (0x7UL << ETH_MTLRQOMR_RFA_Pos) /*!< 0x00000700 */

+#define ETH_MTLRQOMR_RFA                              ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */

+#define ETH_MTLRQOMR_EHFC_Pos                         (7U)

+#define ETH_MTLRQOMR_EHFC_Msk                         (0x1UL << ETH_MTLRQOMR_EHFC_Pos) /*!< 0x00000080 */

+#define ETH_MTLRQOMR_EHFC                             ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */

+#define ETH_MTLRQOMR_DISTCPEF_Pos                     (6U)

+#define ETH_MTLRQOMR_DISTCPEF_Msk                     (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos) /*!< 0x00000040 */

+#define ETH_MTLRQOMR_DISTCPEF                         ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */

+#define ETH_MTLRQOMR_RSF_Pos                          (5U)

+#define ETH_MTLRQOMR_RSF_Msk                          (0x1UL << ETH_MTLRQOMR_RSF_Pos) /*!< 0x00000020 */

+#define ETH_MTLRQOMR_RSF                              ETH_MTLRQOMR_RSF_Msk     /* Receive Queue Store and Forward */

+#define ETH_MTLRQOMR_FEP_Pos                          (4U)

+#define ETH_MTLRQOMR_FEP_Msk                          (0x1UL << ETH_MTLRQOMR_FEP_Pos) /*!< 0x00000010 */

+#define ETH_MTLRQOMR_FEP                              ETH_MTLRQOMR_FEP_Msk     /* Forward Error Packets */

+#define ETH_MTLRQOMR_FUP_Pos                          (3U)

+#define ETH_MTLRQOMR_FUP_Msk                          (0x1UL << ETH_MTLRQOMR_FUP_Pos) /*!< 0x00000008 */

+#define ETH_MTLRQOMR_FUP                              ETH_MTLRQOMR_FUP_Msk     /* Forward Undersized Good Packets */

+#define ETH_MTLRQOMR_RTC_Pos                          (0U)

+#define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */

+#define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */

+#define ETH_MTLRQOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */

+#define ETH_MTLRQOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */

+#define ETH_MTLRQOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */

+#define ETH_MTLRQOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */

+

+/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */

+#define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)

+#define ETH_MTLRQMPOCR_MISCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */

+#define ETH_MTLRQMPOCR_MISCNTOVF                      ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */

+#define ETH_MTLRQMPOCR_MISPKTCNT_Pos                  (16U)

+#define ETH_MTLRQMPOCR_MISPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */

+#define ETH_MTLRQMPOCR_MISPKTCNT                      ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */

+#define ETH_MTLRQMPOCR_OVFCNTOVF_Pos                  (11U)

+#define ETH_MTLRQMPOCR_OVFCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */

+#define ETH_MTLRQMPOCR_OVFCNTOVF                      ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */

+#define ETH_MTLRQMPOCR_OVFPKTCNT_Pos                  (0U)

+#define ETH_MTLRQMPOCR_OVFPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */

+#define ETH_MTLRQMPOCR_OVFPKTCNT                      ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */

+

+/* Bit definition for Ethernet MTL Rx Queue Debug Register */

+#define ETH_MTLRQDR_PRXQ_Pos                          (16U)

+#define ETH_MTLRQDR_PRXQ_Msk                          (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos) /*!< 0x3FFF0000 */

+#define ETH_MTLRQDR_PRXQ                              ETH_MTLRQDR_PRXQ_Msk     /* Number of Packets in Receive Queue */

+#define ETH_MTLRQDR_RXQSTS_Pos                        (4U)

+#define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */

+#define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */

+#define ETH_MTLRQDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */

+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)

+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */

+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */

+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos         (5U)

+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */

+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD             ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */

+#define ETH_MTLRQDR_RXQSTS_FULL_Pos                   (4U)

+#define ETH_MTLRQDR_RXQSTS_FULL_Msk                   (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */

+#define ETH_MTLRQDR_RXQSTS_FULL                       ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */

+#define ETH_MTLRQDR_RRCSTS_Pos                        (1U)

+#define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */

+#define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */

+#define ETH_MTLRQDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */

+#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)

+#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */

+#define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */

+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos          (2U)

+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk          (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */

+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS              ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */

+#define ETH_MTLRQDR_RRCSTS_FLUSHING_Pos               (1U)

+#define ETH_MTLRQDR_RRCSTS_FLUSHING_Msk               (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */

+#define ETH_MTLRQDR_RRCSTS_FLUSHING                   ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */

+#define ETH_MTLRQDR_RWCSTS_Pos                        (0U)

+#define ETH_MTLRQDR_RWCSTS_Msk                        (0x1UL << ETH_MTLRQDR_RWCSTS_Pos) /*!< 0x00000001 */

+#define ETH_MTLRQDR_RWCSTS                            ETH_MTLRQDR_RWCSTS_Msk   /* MTL Rx Queue Write Controller Active Status */

+

+/* Bit definition for Ethernet MTL Rx Queue Control Register */

+#define ETH_MTLRQCR_RQPA_Pos                          (3U)

+#define ETH_MTLRQCR_RQPA_Msk                          (0x1UL << ETH_MTLRQCR_RQPA_Pos) /*!< 0x00000008 */

+#define ETH_MTLRQCR_RQPA                              ETH_MTLRQCR_RQPA_Msk     /* Receive Queue Packet Arbitration */

+#define ETH_MTLRQCR_RQW_Pos                           (0U)

+#define ETH_MTLRQCR_RQW_Msk                           (0x7UL << ETH_MTLRQCR_RQW_Pos) /*!< 0x00000007 */

+#define ETH_MTLRQCR_RQW                               ETH_MTLRQCR_RQW_Msk      /* Receive Queue Weight */

+

+/* Bit definition for Ethernet DMA Mode Register */

+#define ETH_DMAMR_INTM_Pos                            (16U)

+#define ETH_DMAMR_INTM_Msk                            (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */

+#define ETH_DMAMR_INTM                                ETH_DMAMR_INTM_Msk       /* This field defines the interrupt mode */

+#define ETH_DMAMR_INTM_0                              (0x0UL << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */

+#define ETH_DMAMR_INTM_1                              (0x1UL << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */

+#define ETH_DMAMR_INTM_2                              (0x2UL << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */

+#define ETH_DMAMR_PR_Pos                              (12U)

+#define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */

+#define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */

+#define ETH_DMAMR_PR_1_1                              ((uint32_t)0x00000000)   /* The priority ratio is 1:1 */

+#define ETH_DMAMR_PR_2_1                              ((uint32_t)0x00001000)   /* The priority ratio is 2:1 */

+#define ETH_DMAMR_PR_3_1                              ((uint32_t)0x00002000)   /* The priority ratio is 3:1 */

+#define ETH_DMAMR_PR_4_1                              ((uint32_t)0x00003000)   /* The priority ratio is 4:1 */

+#define ETH_DMAMR_PR_5_1                              ((uint32_t)0x00004000)   /* The priority ratio is 5:1 */

+#define ETH_DMAMR_PR_6_1                              ((uint32_t)0x00005000)   /* The priority ratio is 6:1 */

+#define ETH_DMAMR_PR_7_1                              ((uint32_t)0x00006000)   /* The priority ratio is 7:1 */

+#define ETH_DMAMR_PR_8_1                              ((uint32_t)0x00007000)   /* The priority ratio is 8:1 */

+#define ETH_DMAMR_TXPR_Pos                            (11U)

+#define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */

+#define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */

+#define ETH_DMAMR_DA_Pos                              (1U)

+#define ETH_DMAMR_DA_Msk                              (0x1UL << ETH_DMAMR_DA_Pos) /*!< 0x00000002 */

+#define ETH_DMAMR_DA                                  ETH_DMAMR_DA_Msk         /* DMA Tx or Rx Arbitration Scheme */

+#define ETH_DMAMR_SWR_Pos                             (0U)

+#define ETH_DMAMR_SWR_Msk                             (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */

+#define ETH_DMAMR_SWR                                 ETH_DMAMR_SWR_Msk        /* Software Reset */

+

+/* Bit definition for Ethernet DMA SysBus Mode Register */

+#define ETH_DMASBMR_RB_Pos                            (15U)

+#define ETH_DMASBMR_RB_Msk                            (0x1UL << ETH_DMASBMR_RB_Pos) /*!< 0x00008000 */

+#define ETH_DMASBMR_RB                                ETH_DMASBMR_RB_Msk       /* Rebuild INCRx Burst */

+#define ETH_DMASBMR_MB_Pos                            (14U)

+#define ETH_DMASBMR_MB_Msk                            (0x1UL << ETH_DMASBMR_MB_Pos) /*!< 0x00004000 */

+#define ETH_DMASBMR_MB                                ETH_DMASBMR_MB_Msk       /* Mixed Burst */

+#define ETH_DMASBMR_AAL_Pos                           (12U)

+#define ETH_DMASBMR_AAL_Msk                           (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */

+#define ETH_DMASBMR_AAL                               ETH_DMASBMR_AAL_Msk      /* Address-Aligned Beats */

+#define ETH_DMASBMR_FB_Pos                            (0U)

+#define ETH_DMASBMR_FB_Msk                            (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */

+#define ETH_DMASBMR_FB                                ETH_DMASBMR_FB_Msk       /* Fixed Burst Length */

+

+/* Bit definition for Ethernet DMA Interrupt Status Register */

+#define ETH_DMAISR_MACIS_Pos                          (17U)

+#define ETH_DMAISR_MACIS_Msk                          (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */

+#define ETH_DMAISR_MACIS                              ETH_DMAISR_MACIS_Msk     /* MAC Interrupt Status */

+#define ETH_DMAISR_MTLIS_Pos                          (16U)

+#define ETH_DMAISR_MTLIS_Msk                          (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */

+#define ETH_DMAISR_MTLIS                              ETH_DMAISR_MTLIS_Msk     /* MAC Interrupt Status */

+#define ETH_DMAISR_DMACIS_Pos                         (0U)

+#define ETH_DMAISR_DMACIS_Msk                         (0x1UL << ETH_DMAISR_DMACIS_Pos) /*!< 0x00000001 */

+#define ETH_DMAISR_DMACIS                             ETH_DMAISR_DMACIS_Msk    /* DMA Channel Interrupt Status */

+

+/* Bit definition for Ethernet DMA Debug Status Register */

+#define ETH_DMADSR_TPS_Pos                            (12U)

+#define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */

+#define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */

+#define ETH_DMADSR_TPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */

+#define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)

+#define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */

+#define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */

+#define ETH_DMADSR_TPS_WAITING_Pos                    (13U)

+#define ETH_DMADSR_TPS_WAITING_Msk                    (0x1UL << ETH_DMADSR_TPS_WAITING_Pos) /*!< 0x00002000 */

+#define ETH_DMADSR_TPS_WAITING                        ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */

+#define ETH_DMADSR_TPS_READING_Pos                    (12U)

+#define ETH_DMADSR_TPS_READING_Msk                    (0x3UL << ETH_DMADSR_TPS_READING_Pos) /*!< 0x00003000 */

+#define ETH_DMADSR_TPS_READING                        ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */

+#define ETH_DMADSR_TPS_TIMESTAMP_WR_Pos               (14U)

+#define ETH_DMADSR_TPS_TIMESTAMP_WR_Msk               (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos) /*!< 0x00004000 */

+#define ETH_DMADSR_TPS_TIMESTAMP_WR                   ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */

+#define ETH_DMADSR_TPS_SUSPENDED_Pos                  (13U)

+#define ETH_DMADSR_TPS_SUSPENDED_Msk                  (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos) /*!< 0x00006000 */

+#define ETH_DMADSR_TPS_SUSPENDED                      ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */

+#define ETH_DMADSR_TPS_CLOSING_Pos                    (12U)

+#define ETH_DMADSR_TPS_CLOSING_Msk                    (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos) /*!< 0x00007000 */

+#define ETH_DMADSR_TPS_CLOSING                        ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */

+#define ETH_DMADSR_RPS_Pos                            (8U)

+#define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */

+#define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */

+#define ETH_DMADSR_RPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */

+#define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)

+#define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */

+#define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */

+#define ETH_DMADSR_RPS_WAITING_Pos                    (12U)

+#define ETH_DMADSR_RPS_WAITING_Msk                    (0x3UL << ETH_DMADSR_RPS_WAITING_Pos) /*!< 0x00003000 */

+#define ETH_DMADSR_RPS_WAITING                        ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */

+#define ETH_DMADSR_RPS_SUSPENDED_Pos                  (14U)

+#define ETH_DMADSR_RPS_SUSPENDED_Msk                  (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos) /*!< 0x00004000 */

+#define ETH_DMADSR_RPS_SUSPENDED                      ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */

+#define ETH_DMADSR_RPS_CLOSING_Pos                    (12U)

+#define ETH_DMADSR_RPS_CLOSING_Msk                    (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos) /*!< 0x00005000 */

+#define ETH_DMADSR_RPS_CLOSING                        ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */

+#define ETH_DMADSR_RPS_TIMESTAMP_WR_Pos               (13U)

+#define ETH_DMADSR_RPS_TIMESTAMP_WR_Msk               (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos) /*!< 0x00006000 */

+#define ETH_DMADSR_RPS_TIMESTAMP_WR                   ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */

+#define ETH_DMADSR_RPS_TRANSFERRING_Pos               (12U)

+#define ETH_DMADSR_RPS_TRANSFERRING_Msk               (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos) /*!< 0x00007000 */

+#define ETH_DMADSR_RPS_TRANSFERRING                   ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */

+

+/* Bit definition for Ethernet DMA Channel Control Register */

+#define ETH_DMACCR_DSL_Pos                            (18U)

+#define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */

+#define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */

+#define ETH_DMACCR_DSL_0BIT                           ((uint32_t)0x00000000)

+#define ETH_DMACCR_DSL_32BIT                          ((uint32_t)0x00040000)

+#define ETH_DMACCR_DSL_64BIT                          ((uint32_t)0x00080000)

+#define ETH_DMACCR_DSL_128BIT                         ((uint32_t)0x00100000)

+#define ETH_DMACCR_8PBL                               ((uint32_t)0x00010000)   /* 8xPBL mode */

+#define ETH_DMACCR_MSS_Pos                            (0U)

+#define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */

+#define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */

+

+/* Bit definition for Ethernet DMA Channel Tx Control Register */

+#define ETH_DMACTCR_TPBL_Pos                          (16U)

+#define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */

+#define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */

+#define ETH_DMACTCR_TPBL_1PBL                         ((uint32_t)0x00010000)   /* Transmit Programmable Burst Length 1 */

+#define ETH_DMACTCR_TPBL_2PBL                         ((uint32_t)0x00020000)   /* Transmit Programmable Burst Length 2 */

+#define ETH_DMACTCR_TPBL_4PBL                         ((uint32_t)0x00040000)   /* Transmit Programmable Burst Length 4 */

+#define ETH_DMACTCR_TPBL_8PBL                         ((uint32_t)0x00080000)   /* Transmit Programmable Burst Length 8 */

+#define ETH_DMACTCR_TPBL_16PBL                        ((uint32_t)0x00100000)   /* Transmit Programmable Burst Length 16 */

+#define ETH_DMACTCR_TPBL_32PBL                        ((uint32_t)0x00200000)   /* Transmit Programmable Burst Length 32 */

+#define ETH_DMACTCR_TSE_Pos                           (12U)

+#define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */

+#define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */

+#define ETH_DMACTCR_OSP_Pos                           (4U)

+#define ETH_DMACTCR_OSP_Msk                           (0x1UL << ETH_DMACTCR_OSP_Pos) /*!< 0x00000010 */

+#define ETH_DMACTCR_OSP                               ETH_DMACTCR_OSP_Msk      /* Operate on Second Packet */

+#define ETH_DMACTCR_ST_Pos                            (0U)

+#define ETH_DMACTCR_ST_Msk                            (0x1UL << ETH_DMACTCR_ST_Pos) /*!< 0x00000001 */

+#define ETH_DMACTCR_ST                                ETH_DMACTCR_ST_Msk       /* Start or Stop Transmission Command */

+

+/* Bit definition for Ethernet DMA Channel Rx Control Register */

+#define ETH_DMACRCR_RPF_Pos                           (31U)

+#define ETH_DMACRCR_RPF_Msk                           (0x1UL << ETH_DMACRCR_RPF_Pos) /*!< 0x80000000 */

+#define ETH_DMACRCR_RPF                               ETH_DMACRCR_RPF_Msk      /* Rx Packet Flush */

+#define ETH_DMACRCR_RPBL_Pos                          (16U)

+#define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */

+#define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */

+#define ETH_DMACRCR_RPBL_1PBL                         ((uint32_t)0x00010000)   /* Receive Programmable Burst Length 1 */

+#define ETH_DMACRCR_RPBL_2PBL                         ((uint32_t)0x00020000)   /* Receive Programmable Burst Length 2 */

+#define ETH_DMACRCR_RPBL_4PBL                         ((uint32_t)0x00040000)   /* Receive Programmable Burst Length 4 */

+#define ETH_DMACRCR_RPBL_8PBL                         ((uint32_t)0x00080000)   /* Receive Programmable Burst Length 8 */

+#define ETH_DMACRCR_RPBL_16PBL                        ((uint32_t)0x00100000)   /* Receive Programmable Burst Length 16 */

+#define ETH_DMACRCR_RPBL_32PBL                        ((uint32_t)0x00200000)   /* Receive Programmable Burst Length 32 */

+#define ETH_DMACRCR_RBSZ_Pos                          (1U)

+#define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */

+#define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */

+#define ETH_DMACRCR_SR_Pos                            (0U)

+#define ETH_DMACRCR_SR_Msk                            (0x1UL << ETH_DMACRCR_SR_Pos) /*!< 0x00000001 */

+#define ETH_DMACRCR_SR                                ETH_DMACRCR_SR_Msk       /* Start or Stop Receive */

+

+/* Bit definition for Ethernet DMA CH Tx Desc List Address Register */

+#define ETH_DMACTDLAR_TDESLA_Pos                      (2U)

+#define ETH_DMACTDLAR_TDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACTDLAR_TDESLA                          ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */

+

+/* Bit definition for Ethernet DMA CH Rx Desc List Address Register */

+#define ETH_DMACRDLAR_RDESLA_Pos                      (2U)

+#define ETH_DMACRDLAR_RDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACRDLAR_RDESLA                          ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */

+

+/* Bit definition for Ethernet DMA CH Tx Desc Tail Pointer Register */

+#define ETH_DMACTDTPR_TDT_Pos                         (2U)

+#define ETH_DMACTDTPR_TDT_Msk                         (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACTDTPR_TDT                             ETH_DMACTDTPR_TDT_Msk    /* Transmit Descriptor Tail Pointer */

+

+/* Bit definition for Ethernet DMA CH Rx Desc Tail Pointer Register */

+#define ETH_DMACRDTPR_RDT_Pos                         (2U)

+#define ETH_DMACRDTPR_RDT_Msk                         (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACRDTPR_RDT                             ETH_DMACRDTPR_RDT_Msk    /* Receive Descriptor Tail Pointer */

+

+/* Bit definition for Ethernet DMA CH Tx Desc Ring Length Register */

+#define ETH_DMACTDRLR_TDRL_Pos                        (0U)

+#define ETH_DMACTDRLR_TDRL_Msk                        (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos) /*!< 0x000003FF */

+#define ETH_DMACTDRLR_TDRL                            ETH_DMACTDRLR_TDRL_Msk   /* Transmit Descriptor Ring Length */

+

+/* Bit definition for Ethernet DMA CH Rx Desc Ring Length Register */

+#define ETH_DMACRDRLR_RDRL_Pos                        (0U)

+#define ETH_DMACRDRLR_RDRL_Msk                        (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos) /*!< 0x000003FF */

+#define ETH_DMACRDRLR_RDRL                            ETH_DMACRDRLR_RDRL_Msk   /* Receive Descriptor Ring Length */

+

+/* Bit definition for Ethernet DMA Channel Interrupt Enable Register */

+#define ETH_DMACIER_NIE_Pos                           (15U)

+#define ETH_DMACIER_NIE_Msk                           (0x1UL << ETH_DMACIER_NIE_Pos) /*!< 0x00008000 */

+#define ETH_DMACIER_NIE                               ETH_DMACIER_NIE_Msk      /* Normal Interrupt Summary Enable */

+#define ETH_DMACIER_AIE_Pos                           (14U)

+#define ETH_DMACIER_AIE_Msk                           (0x1UL << ETH_DMACIER_AIE_Pos) /*!< 0x00004000 */

+#define ETH_DMACIER_AIE                               ETH_DMACIER_AIE_Msk      /* Abnormal Interrupt Summary Enable */

+#define ETH_DMACIER_CDEE_Pos                          (13U)

+#define ETH_DMACIER_CDEE_Msk                          (0x1UL << ETH_DMACIER_CDEE_Pos) /*!< 0x00002000 */

+#define ETH_DMACIER_CDEE                              ETH_DMACIER_CDEE_Msk     /* Context Descriptor Error Enable */

+#define ETH_DMACIER_FBEE_Pos                          (12U)

+#define ETH_DMACIER_FBEE_Msk                          (0x1UL << ETH_DMACIER_FBEE_Pos) /*!< 0x00001000 */

+#define ETH_DMACIER_FBEE                              ETH_DMACIER_FBEE_Msk     /* Fatal Bus Error Enable */

+#define ETH_DMACIER_ERIE_Pos                          (11U)

+#define ETH_DMACIER_ERIE_Msk                          (0x1UL << ETH_DMACIER_ERIE_Pos) /*!< 0x00000800 */

+#define ETH_DMACIER_ERIE                              ETH_DMACIER_ERIE_Msk     /* Early Receive Interrupt Enable */

+#define ETH_DMACIER_ETIE_Pos                          (10U)

+#define ETH_DMACIER_ETIE_Msk                          (0x1UL << ETH_DMACIER_ETIE_Pos) /*!< 0x00000400 */

+#define ETH_DMACIER_ETIE                              ETH_DMACIER_ETIE_Msk     /* Early Transmit Interrupt Enable */

+#define ETH_DMACIER_RWTE_Pos                          (9U)

+#define ETH_DMACIER_RWTE_Msk                          (0x1UL << ETH_DMACIER_RWTE_Pos) /*!< 0x00000200 */

+#define ETH_DMACIER_RWTE                              ETH_DMACIER_RWTE_Msk     /* Receive Watchdog Timeout Enable */

+#define ETH_DMACIER_RSE_Pos                           (8U)

+#define ETH_DMACIER_RSE_Msk                           (0x1UL << ETH_DMACIER_RSE_Pos) /*!< 0x00000100 */

+#define ETH_DMACIER_RSE                               ETH_DMACIER_RSE_Msk      /* Receive Stopped Enable */

+#define ETH_DMACIER_RBUE_Pos                          (7U)

+#define ETH_DMACIER_RBUE_Msk                          (0x1UL << ETH_DMACIER_RBUE_Pos) /*!< 0x00000080 */

+#define ETH_DMACIER_RBUE                              ETH_DMACIER_RBUE_Msk     /* Receive Buffer Unavailable Enable */

+#define ETH_DMACIER_RIE_Pos                           (6U)

+#define ETH_DMACIER_RIE_Msk                           (0x1UL << ETH_DMACIER_RIE_Pos) /*!< 0x00000040 */

+#define ETH_DMACIER_RIE                               ETH_DMACIER_RIE_Msk      /* Receive Interrupt Enable */

+#define ETH_DMACIER_TBUE_Pos                          (2U)

+#define ETH_DMACIER_TBUE_Msk                          (0x1UL << ETH_DMACIER_TBUE_Pos) /*!< 0x00000004 */

+#define ETH_DMACIER_TBUE                              ETH_DMACIER_TBUE_Msk     /* Transmit Buffer Unavailable Enable */

+#define ETH_DMACIER_TXSE_Pos                          (1U)

+#define ETH_DMACIER_TXSE_Msk                          (0x1UL << ETH_DMACIER_TXSE_Pos) /*!< 0x00000002 */

+#define ETH_DMACIER_TXSE                              ETH_DMACIER_TXSE_Msk     /* Transmit Stopped Enable */

+#define ETH_DMACIER_TIE_Pos                           (0U)

+#define ETH_DMACIER_TIE_Msk                           (0x1UL << ETH_DMACIER_TIE_Pos) /*!< 0x00000001 */

+#define ETH_DMACIER_TIE                               ETH_DMACIER_TIE_Msk      /* Transmit Interrupt Enable */

+

+/* Bit definition for Ethernet DMA Channel Rx Interrupt Watchdog Timer Register */

+#define ETH_DMACRIWTR_RWT_Pos                         (0U)

+#define ETH_DMACRIWTR_RWT_Msk                         (0xFFUL << ETH_DMACRIWTR_RWT_Pos) /*!< 0x000000FF */

+#define ETH_DMACRIWTR_RWT                             ETH_DMACRIWTR_RWT_Msk    /* Receive Interrupt Watchdog Timer Count */

+

+/* Bit definition for Ethernet DMA Channel Current App Tx Desc Register */

+#define ETH_DMACCATDR_CURTDESAPTR_Pos                 (0U)

+#define ETH_DMACCATDR_CURTDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCATDR_CURTDESAPTR                     ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Current App Rx Desc Register */

+#define ETH_DMACCARDR_CURRDESAPTR_Pos                 (0U)

+#define ETH_DMACCARDR_CURRDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCARDR_CURRDESAPTR                     ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Current App Tx Buffer Register */

+#define ETH_DMACCATBR_CURTBUFAPTR_Pos                 (0U)

+#define ETH_DMACCATBR_CURTBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCATBR_CURTBUFAPTR                     ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Current App Rx Buffer Register */

+#define ETH_DMACCARBR_CURRBUFAPTR_Pos                 (0U)

+#define ETH_DMACCARBR_CURRBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCARBR_CURRBUFAPTR                     ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Status Register */

+#define ETH_DMACSR_REB_Pos                            (19U)

+#define ETH_DMACSR_REB_Msk                            (0x7UL << ETH_DMACSR_REB_Pos) /*!< 0x00380000 */

+#define ETH_DMACSR_REB                                ETH_DMACSR_REB_Msk       /* Rx DMA Error Bits */

+#define ETH_DMACSR_TEB_Pos                            (16U)

+#define ETH_DMACSR_TEB_Msk                            (0x7UL << ETH_DMACSR_TEB_Pos) /*!< 0x00070000 */

+#define ETH_DMACSR_TEB                                ETH_DMACSR_TEB_Msk       /* Tx DMA Error Bits */

+#define ETH_DMACSR_NIS_Pos                            (15U)

+#define ETH_DMACSR_NIS_Msk                            (0x1UL << ETH_DMACSR_NIS_Pos) /*!< 0x00008000 */

+#define ETH_DMACSR_NIS                                ETH_DMACSR_NIS_Msk       /* Normal Interrupt Summary */

+#define ETH_DMACSR_AIS_Pos                            (14U)

+#define ETH_DMACSR_AIS_Msk                            (0x1UL << ETH_DMACSR_AIS_Pos) /*!< 0x00004000 */

+#define ETH_DMACSR_AIS                                ETH_DMACSR_AIS_Msk       /* Abnormal Interrupt Summary */

+#define ETH_DMACSR_CDE_Pos                            (13U)

+#define ETH_DMACSR_CDE_Msk                            (0x1UL << ETH_DMACSR_CDE_Pos) /*!< 0x00002000 */

+#define ETH_DMACSR_CDE                                ETH_DMACSR_CDE_Msk       /* Context Descriptor Error */

+#define ETH_DMACSR_FBE_Pos                            (12U)

+#define ETH_DMACSR_FBE_Msk                            (0x1UL << ETH_DMACSR_FBE_Pos) /*!< 0x00001000 */

+#define ETH_DMACSR_FBE                                ETH_DMACSR_FBE_Msk       /* Fatal Bus Error */

+#define ETH_DMACSR_ERI_Pos                            (11U)

+#define ETH_DMACSR_ERI_Msk                            (0x1UL << ETH_DMACSR_ERI_Pos) /*!< 0x00000800 */

+#define ETH_DMACSR_ERI                                ETH_DMACSR_ERI_Msk       /* Early Receive Interrupt */

+#define ETH_DMACSR_ETI_Pos                            (10U)

+#define ETH_DMACSR_ETI_Msk                            (0x1UL << ETH_DMACSR_ETI_Pos) /*!< 0x00000400 */

+#define ETH_DMACSR_ETI                                ETH_DMACSR_ETI_Msk       /* Early Transmit Interrupt */

+#define ETH_DMACSR_RWT_Pos                            (9U)

+#define ETH_DMACSR_RWT_Msk                            (0x1UL << ETH_DMACSR_RWT_Pos) /*!< 0x00000200 */

+#define ETH_DMACSR_RWT                                ETH_DMACSR_RWT_Msk       /* Receive Watchdog Timeout */

+#define ETH_DMACSR_RPS_Pos                            (8U)

+#define ETH_DMACSR_RPS_Msk                            (0x1UL << ETH_DMACSR_RPS_Pos) /*!< 0x00000100 */

+#define ETH_DMACSR_RPS                                ETH_DMACSR_RPS_Msk       /* Receive Process Stopped */

+#define ETH_DMACSR_RBU_Pos                            (7U)

+#define ETH_DMACSR_RBU_Msk                            (0x1UL << ETH_DMACSR_RBU_Pos) /*!< 0x00000080 */

+#define ETH_DMACSR_RBU                                ETH_DMACSR_RBU_Msk       /* Receive Buffer Unavailable */

+#define ETH_DMACSR_RI_Pos                             (6U)

+#define ETH_DMACSR_RI_Msk                             (0x1UL << ETH_DMACSR_RI_Pos) /*!< 0x00000040 */

+#define ETH_DMACSR_RI                                 ETH_DMACSR_RI_Msk        /* Receive Interrupt */

+#define ETH_DMACSR_TBU_Pos                            (2U)

+#define ETH_DMACSR_TBU_Msk                            (0x1UL << ETH_DMACSR_TBU_Pos) /*!< 0x00000004 */

+#define ETH_DMACSR_TBU                                ETH_DMACSR_TBU_Msk       /* Transmit Buffer Unavailable */

+#define ETH_DMACSR_TPS_Pos                            (1U)

+#define ETH_DMACSR_TPS_Msk                            (0x1UL << ETH_DMACSR_TPS_Pos) /*!< 0x00000002 */

+#define ETH_DMACSR_TPS                                ETH_DMACSR_TPS_Msk       /* Transmit Process Stopped */

+#define ETH_DMACSR_TI_Pos                             (0U)

+#define ETH_DMACSR_TI_Msk                             (0x1UL << ETH_DMACSR_TI_Pos) /*!< 0x00000001 */

+#define ETH_DMACSR_TI                                 ETH_DMACSR_TI_Msk        /* Transmit Interrupt */

+

+/* Bit definition for Ethernet DMA Channel missed frame count register */

+#define ETH_DMACMFCR_MFCO_Pos                         (15U)

+#define ETH_DMACMFCR_MFCO_Msk                         (0x1UL << ETH_DMACMFCR_MFCO_Pos) /*!< 0x00008000 */

+#define ETH_DMACMFCR_MFCO                             ETH_DMACMFCR_MFCO_Msk    /* Overflow status of the MFC Counter */

+#define ETH_DMACMFCR_MFC_Pos                          (0U)

+#define ETH_DMACMFCR_MFC_Msk                          (0x7FFUL << ETH_DMACMFCR_MFC_Pos) /*!< 0x000007FF */

+#define ETH_DMACMFCR_MFC                              ETH_DMACMFCR_MFC_Msk     /* The number of packet counters dropped by the DMA */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             DMA Controller                                 */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DMA_SxCR register  *****************/

+#define DMA_SxCR_MBURST_Pos      (23U)

+#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                /*!< 0x01800000 */

+#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk                           /*!< Memory burst transfer configuration */

+#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */

+#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */

+#define DMA_SxCR_PBURST_Pos      (21U)

+#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                /*!< 0x00600000 */

+#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk                           /*!< Peripheral burst transfer configuration */

+#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */

+#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */

+#define DMA_SxCR_TRBUFF_Pos      (20U)

+#define DMA_SxCR_TRBUFF_Msk      (0x1UL << DMA_SxCR_TRBUFF_Pos)                 /*!< 0x00100000 */

+#define DMA_SxCR_TRBUFF          DMA_SxCR_TRBUFF_Msk                            /*!< bufferable transfers enabled/disable */

+#define DMA_SxCR_CT_Pos          (19U)

+#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                    /*!< 0x00080000 */

+#define DMA_SxCR_CT              DMA_SxCR_CT_Msk                               /*!< Current target (only in double buffer mode) */

+#define DMA_SxCR_DBM_Pos         (18U)

+#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                   /*!< 0x00040000 */

+#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk                              /*!< Double buffer mode */

+#define DMA_SxCR_PL_Pos          (16U)

+#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                    /*!< 0x00030000 */

+#define DMA_SxCR_PL              DMA_SxCR_PL_Msk                               /*!< Priority level */

+#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */

+#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */

+#define DMA_SxCR_PINCOS_Pos      (15U)

+#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                /*!< 0x00008000 */

+#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk                           /*!< Peripheral increment offset size */

+#define DMA_SxCR_MSIZE_Pos       (13U)

+#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                 /*!< 0x00006000 */

+#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk                            /*!< Memory data size */

+#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */

+#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */

+#define DMA_SxCR_PSIZE_Pos       (11U)

+#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                 /*!< 0x00001800 */

+#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk                            /*< Peripheral data size */

+#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */

+#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */

+#define DMA_SxCR_MINC_Pos        (10U)

+#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                  /*!< 0x00000400 */

+#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk                             /*!< Memory increment mode */

+#define DMA_SxCR_PINC_Pos        (9U)

+#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                  /*!< 0x00000200 */

+#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk                             /*!< Peripheral increment mode */

+#define DMA_SxCR_CIRC_Pos        (8U)

+#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                  /*!< 0x00000100 */

+#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk                             /*!< Circular mode */

+#define DMA_SxCR_DIR_Pos         (6U)

+#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                   /*!< 0x000000C0 */

+#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk                              /*!< Data transfer direction */

+#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */

+#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */

+#define DMA_SxCR_PFCTRL_Pos      (5U)

+#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                /*!< 0x00000020 */

+#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk                           /*!< Peripheral flow controller */

+#define DMA_SxCR_TCIE_Pos        (4U)

+#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                  /*!< 0x00000010 */

+#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk                             /*!< Transfer complete interrupt enable */

+#define DMA_SxCR_HTIE_Pos        (3U)

+#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                  /*!< 0x00000008 */

+#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk                             /*!< Half transfer interrupt enable */

+#define DMA_SxCR_TEIE_Pos        (2U)

+#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                  /*!< 0x00000004 */

+#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk                             /*!< Transfer error interrupt enable */

+#define DMA_SxCR_DMEIE_Pos       (1U)

+#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                 /*!< 0x00000002 */

+#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk                            /*!< Direct mode error interrupt enable */

+#define DMA_SxCR_EN_Pos          (0U)

+#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                    /*!< 0x00000001 */

+#define DMA_SxCR_EN              DMA_SxCR_EN_Msk                               /*!< Stream enable / flag stream ready when read low */

+

+/********************  Bits definition for DMA_SxCNDTR register  **************/

+#define DMA_SxNDT_Pos            (0U)

+#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                   /*!< 0x0000FFFF */

+#define DMA_SxNDT                DMA_SxNDT_Msk                                 /*!< Number of data items to transfer */

+#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */

+#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */

+#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */

+#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */

+#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */

+#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */

+#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */

+#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */

+#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */

+#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */

+#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */

+#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */

+#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */

+#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */

+#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */

+#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */

+

+/********************  Bits definition for DMA_SxFCR register  ****************/

+#define DMA_SxFCR_FEIE_Pos       (7U)

+#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                 /*!< 0x00000080 */

+#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk                            /*!< FIFO error interrupt enable */

+#define DMA_SxFCR_FS_Pos         (3U)

+#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                   /*!< 0x00000038 */

+#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk                              /*!< FIFO status */

+#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */

+#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */

+#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */

+#define DMA_SxFCR_DMDIS_Pos      (2U)

+#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                /*!< 0x00000004 */

+#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk                           /*!< Direct mode disable */

+#define DMA_SxFCR_FTH_Pos        (0U)

+#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                  /*!< 0x00000003 */

+#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk                             /*!< FIFO threshold selection */

+#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */

+#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */

+

+/********************  Bits definition for DMA_LISR register  *****************/

+#define DMA_LISR_TCIF3_Pos       (27U)

+#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                 /*!< 0x08000000 */

+#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk                            /*!<  Stream 3 transfer complete interrupt flag */

+#define DMA_LISR_HTIF3_Pos       (26U)

+#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                 /*!< 0x04000000 */

+#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk                            /*!<  Stream 3 half transfer interrupt flag */

+#define DMA_LISR_TEIF3_Pos       (25U)

+#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                 /*!< 0x02000000 */

+#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk                            /*!<  Stream 3 transfer error interrupt flag */

+#define DMA_LISR_DMEIF3_Pos      (24U)

+#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                /*!< 0x01000000 */

+#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk                           /*!<  Stream 3 direct mode error interrupt flag */

+#define DMA_LISR_FEIF3_Pos       (22U)

+#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                 /*!< 0x00400000 */

+#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk                            /*!<  Stream 3 FIFO error interrupt flag */

+#define DMA_LISR_TCIF2_Pos       (21U)

+#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                 /*!< 0x00200000 */

+#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk                            /*!<  Stream 2 transfer complete interrupt flag */

+#define DMA_LISR_HTIF2_Pos       (20U)

+#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                 /*!< 0x00100000 */

+#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk                            /*!<  Stream 2 half transfer interrupt flag */

+#define DMA_LISR_TEIF2_Pos       (19U)

+#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                 /*!< 0x00080000 */

+#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk                            /*!<  Stream 2 transfer error interrupt flag */

+#define DMA_LISR_DMEIF2_Pos      (18U)

+#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                /*!< 0x00040000 */

+#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk                           /*!<  Stream 2 direct mode error interrupt flag */

+#define DMA_LISR_FEIF2_Pos       (16U)

+#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                 /*!< 0x00010000 */

+#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk                            /*!<  Stream 2 FIFO error interrupt flag */

+#define DMA_LISR_TCIF1_Pos       (11U)

+#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                 /*!< 0x00000800 */

+#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk                            /*!<  Stream 1 transfer complete interrupt flag */

+#define DMA_LISR_HTIF1_Pos       (10U)

+#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                 /*!< 0x00000400 */

+#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk                            /*!<  Stream 1 half transfer interrupt flag */

+#define DMA_LISR_TEIF1_Pos       (9U)

+#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                 /*!< 0x00000200 */

+#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk                            /*!<  Stream 1 transfer error interrupt flag */

+#define DMA_LISR_DMEIF1_Pos      (8U)

+#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                /*!< 0x00000100 */

+#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk                           /*!<  Stream 1 direct mode error interrupt flag */

+#define DMA_LISR_FEIF1_Pos       (6U)

+#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                 /*!< 0x00000040 */

+#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk                            /*!<  Stream 1 FIFO error interrupt flag */

+#define DMA_LISR_TCIF0_Pos       (5U)

+#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                 /*!< 0x00000020 */

+#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk                            /*!<  Stream 0 transfer complete interrupt flag */

+#define DMA_LISR_HTIF0_Pos       (4U)

+#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                 /*!< 0x00000010 */

+#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk                            /*!<  Stream 0 half transfer interrupt flag */

+#define DMA_LISR_TEIF0_Pos       (3U)

+#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                 /*!< 0x00000008 */

+#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk                            /*!<  Stream 0 transfer error interrupt flag */

+#define DMA_LISR_DMEIF0_Pos      (2U)

+#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                /*!< 0x00000004 */

+#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk                           /*!<  Stream 0 direct mode error interrupt flag */

+#define DMA_LISR_FEIF0_Pos       (0U)

+#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                 /*!< 0x00000001 */

+#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk                            /*!<  Stream 0 FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_HISR register  *****************/

+#define DMA_HISR_TCIF7_Pos       (27U)

+#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                 /*!< 0x08000000 */

+#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk                            /*!<  Stream 7 transfer complete interrupt flag */

+#define DMA_HISR_HTIF7_Pos       (26U)

+#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                 /*!< 0x04000000 */

+#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk                            /*!<  Stream 7 half transfer interrupt flag */

+#define DMA_HISR_TEIF7_Pos       (25U)

+#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                 /*!< 0x02000000 */

+#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk                            /*!<  Stream 7 transfer error interrupt flag */

+#define DMA_HISR_DMEIF7_Pos      (24U)

+#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                /*!< 0x01000000 */

+#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk                           /*!<  Stream 7 direct mode error interrupt flag */

+#define DMA_HISR_FEIF7_Pos       (22U)

+#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                 /*!< 0x00400000 */

+#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk                            /*!<  Stream 7 FIFO error interrupt flag */

+#define DMA_HISR_TCIF6_Pos       (21U)

+#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                 /*!< 0x00200000 */

+#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk                            /*!<  Stream 6 transfer complete interrupt flag */

+#define DMA_HISR_HTIF6_Pos       (20U)

+#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                 /*!< 0x00100000 */

+#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk                            /*!<  Stream 6 half transfer interrupt flag */

+#define DMA_HISR_TEIF6_Pos       (19U)

+#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                 /*!< 0x00080000 */

+#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk                            /*!<  Stream 6 transfer error interrupt flag */

+#define DMA_HISR_DMEIF6_Pos      (18U)

+#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                /*!< 0x00040000 */

+#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk                           /*!<  Stream 6 direct mode error interrupt flag */

+#define DMA_HISR_FEIF6_Pos       (16U)

+#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                 /*!< 0x00010000 */

+#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk                            /*!<  Stream 6 FIFO error interrupt flag */

+#define DMA_HISR_TCIF5_Pos       (11U)

+#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                 /*!< 0x00000800 */

+#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk                            /*!<  Stream 5 transfer complete interrupt flag */

+#define DMA_HISR_HTIF5_Pos       (10U)

+#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                 /*!< 0x00000400 */

+#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk                            /*!<  Stream 5 half transfer interrupt flag */

+#define DMA_HISR_TEIF5_Pos       (9U)

+#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                 /*!< 0x00000200 */

+#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk                            /*!<  Stream 5 transfer error interrupt flag */

+#define DMA_HISR_DMEIF5_Pos      (8U)

+#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                /*!< 0x00000100 */

+#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk                           /*!<  Stream 5 direct mode error interrupt flag */

+#define DMA_HISR_FEIF5_Pos       (6U)

+#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                 /*!< 0x00000040 */

+#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk                            /*!<  Stream 5 FIFO error interrupt flag */

+#define DMA_HISR_TCIF4_Pos       (5U)

+#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                 /*!< 0x00000020 */

+#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk                            /*!<  Stream 4 transfer complete interrupt flag */

+#define DMA_HISR_HTIF4_Pos       (4U)

+#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                 /*!< 0x00000010 */

+#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk                            /*!<  Stream 4 half transfer interrupt flag */

+#define DMA_HISR_TEIF4_Pos       (3U)

+#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                 /*!< 0x00000008 */

+#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk                            /*!<  Stream 4 transfer error interrupt flag */

+#define DMA_HISR_DMEIF4_Pos      (2U)

+#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                /*!< 0x00000004 */

+#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk                           /*!<  Stream 4 direct mode error interrupt flag */

+#define DMA_HISR_FEIF4_Pos       (0U)

+#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                 /*!< 0x00000001 */

+#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk                            /*!<  Stream 4 FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_LIFCR register  ****************/

+#define DMA_LIFCR_CTCIF3_Pos     (27U)

+#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)               /*!< 0x08000000 */

+#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk                          /*!<  Stream 3 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF3_Pos     (26U)

+#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)               /*!< 0x04000000 */

+#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk                          /*!<  Stream 3 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF3_Pos     (25U)

+#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)               /*!< 0x02000000 */

+#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk                          /*!<  Stream 3 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF3_Pos    (24U)

+#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)              /*!< 0x01000000 */

+#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk                         /*!<  Stream 3 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF3_Pos     (22U)

+#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)               /*!< 0x00400000 */

+#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk                          /*!<  Stream 3 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF2_Pos     (21U)

+#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)               /*!< 0x00200000 */

+#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk                          /*!<  Stream 2 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF2_Pos     (20U)

+#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)               /*!< 0x00100000 */

+#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk                          /*!<  Stream 2 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF2_Pos     (19U)

+#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)               /*!< 0x00080000 */

+#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk                          /*!<  Stream 2 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF2_Pos    (18U)

+#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)              /*!< 0x00040000 */

+#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk                         /*!<  Stream 2 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF2_Pos     (16U)

+#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)               /*!< 0x00010000 */

+#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk                          /*!<  Stream 2 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF1_Pos     (11U)

+#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)               /*!< 0x00000800 */

+#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk                          /*!<  Stream 1 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF1_Pos     (10U)

+#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)               /*!< 0x00000400 */

+#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk                          /*!<  Stream 1 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF1_Pos     (9U)

+#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)               /*!< 0x00000200 */

+#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk                          /*!<  Stream 1 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF1_Pos    (8U)

+#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)              /*!< 0x00000100 */

+#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk                         /*!<  Stream 1 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF1_Pos     (6U)

+#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)               /*!< 0x00000040 */

+#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk                          /*!<  Stream 1 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF0_Pos     (5U)

+#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)               /*!< 0x00000020 */

+#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk                          /*!<  Stream 0 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF0_Pos     (4U)

+#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)               /*!< 0x00000010 */

+#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk                          /*!<  Stream 0 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF0_Pos     (3U)

+#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)               /*!< 0x00000008 */

+#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk                          /*!<  Stream 0 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF0_Pos    (2U)

+#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)              /*!< 0x00000004 */

+#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk                         /*!<  Stream 0 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF0_Pos     (0U)

+#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)               /*!< 0x00000001 */

+#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk                          /*!<  Stream 0 clear FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_HIFCR  register  ****************/

+#define DMA_HIFCR_CTCIF7_Pos     (27U)

+#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)               /*!< 0x08000000 */

+#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk                          /*!<  Stream 7 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF7_Pos     (26U)

+#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)               /*!< 0x04000000 */

+#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk                          /*!<  Stream 7 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF7_Pos     (25U)

+#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)               /*!< 0x02000000 */

+#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk                          /*!<  Stream 7 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF7_Pos    (24U)

+#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)              /*!< 0x01000000 */

+#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk                         /*!<  Stream 7 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF7_Pos     (22U)

+#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)               /*!< 0x00400000 */

+#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk                          /*!<  Stream 7 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF6_Pos     (21U)

+#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)               /*!< 0x00200000 */

+#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk                          /*!<  Stream 6 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF6_Pos     (20U)

+#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)               /*!< 0x00100000 */

+#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk                          /*!<  Stream 6 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF6_Pos     (19U)

+#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)               /*!< 0x00080000 */

+#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk                          /*!<  Stream 6 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF6_Pos    (18U)

+#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)              /*!< 0x00040000 */

+#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk                         /*!<  Stream 6 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF6_Pos     (16U)

+#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)               /*!< 0x00010000 */

+#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk                          /*!<  Stream 6 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF5_Pos     (11U)

+#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)               /*!< 0x00000800 */

+#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk                          /*!<  Stream 5 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF5_Pos     (10U)

+#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)               /*!< 0x00000400 */

+#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk                          /*!<  Stream 5 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF5_Pos     (9U)

+#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)               /*!< 0x00000200 */

+#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk                          /*!<  Stream 5 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF5_Pos    (8U)

+#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)              /*!< 0x00000100 */

+#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk                         /*!<  Stream 5 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF5_Pos     (6U)

+#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)               /*!< 0x00000040 */

+#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk                          /*!<  Stream 5 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF4_Pos     (5U)

+#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)               /*!< 0x00000020 */

+#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk                          /*!<  Stream 4 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF4_Pos     (4U)

+#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)               /*!< 0x00000010 */

+#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk                          /*!<  Stream 4 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF4_Pos     (3U)

+#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)               /*!< 0x00000008 */

+#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk                          /*!<  Stream 4 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF4_Pos    (2U)

+#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)              /*!< 0x00000004 */

+#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk                         /*!<  Stream 4 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF4_Pos     (0U)

+#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)               /*!< 0x00000001 */

+#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk                          /*!<  Stream 4 clear FIFO error interrupt flag */

+

+/******************  Bit definition for DMA_SxPAR register  ********************/

+#define DMA_SxPAR_PA_Pos         (0U)

+#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)            /*!< 0xFFFFFFFF */

+#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */

+

+/******************  Bit definition for DMA_SxM0AR register  ********************/

+#define DMA_SxM0AR_M0A_Pos       (0U)

+#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)          /*!< 0xFFFFFFFF */

+#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory 0 Address */

+

+/******************  Bit definition for DMA_SxM1AR register  ********************/

+#define DMA_SxM1AR_M1A_Pos       (0U)

+#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)          /*!< 0xFFFFFFFF */

+#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory 1 Address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             DMAMUX Controller                              */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DMAMUX_CxCR register  **************/

+#define DMAMUX_CxCR_DMAREQ_ID_Pos      (0U)

+#define DMAMUX_CxCR_DMAREQ_ID_Msk      (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)   /*!< 0x000000FF */

+#define DMAMUX_CxCR_DMAREQ_ID          DMAMUX_CxCR_DMAREQ_ID_Msk               /*!<  DMA request identification */

+#define DMAMUX_CxCR_DMAREQ_ID_0        (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000001 */

+#define DMAMUX_CxCR_DMAREQ_ID_1        (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000002 */

+#define DMAMUX_CxCR_DMAREQ_ID_2        (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000004 */

+#define DMAMUX_CxCR_DMAREQ_ID_3        (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000008 */

+#define DMAMUX_CxCR_DMAREQ_ID_4        (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000010 */

+#define DMAMUX_CxCR_DMAREQ_ID_5        (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000020 */

+#define DMAMUX_CxCR_DMAREQ_ID_6        (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000040 */

+#define DMAMUX_CxCR_DMAREQ_ID_7        (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000080 */

+#define DMAMUX_CxCR_SOIE_Pos           (8U)

+#define DMAMUX_CxCR_SOIE_Msk           (0x1UL << DMAMUX_CxCR_SOIE_Pos)         /*!< 0x00000100 */

+#define DMAMUX_CxCR_SOIE               DMAMUX_CxCR_SOIE_Msk                    /*!<  Synchronization overrun interrupt enable */

+#define DMAMUX_CxCR_EGE_Pos            (9U)

+#define DMAMUX_CxCR_EGE_Msk            (0x1UL << DMAMUX_CxCR_EGE_Pos)          /*!< 0x00000200 */

+#define DMAMUX_CxCR_EGE                DMAMUX_CxCR_EGE_Msk                     /*!<  Event generation enable */

+#define DMAMUX_CxCR_SE_Pos             (16U)

+#define DMAMUX_CxCR_SE_Msk             (0x1UL << DMAMUX_CxCR_SE_Pos)           /*!< 0x00010000 */

+#define DMAMUX_CxCR_SE                 DMAMUX_CxCR_SE_Msk                      /*!<  Synchronization enable */

+#define DMAMUX_CxCR_SPOL_Pos           (17U)

+#define DMAMUX_CxCR_SPOL_Msk           (0x3UL << DMAMUX_CxCR_SPOL_Pos)         /*!< 0x00060000 */

+#define DMAMUX_CxCR_SPOL               DMAMUX_CxCR_SPOL_Msk                    /*!<  Synchronization polarity */

+#define DMAMUX_CxCR_SPOL_0             (0x1UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00020000 */

+#define DMAMUX_CxCR_SPOL_1             (0x2UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00040000 */

+#define DMAMUX_CxCR_NBREQ_Pos          (19U)

+#define DMAMUX_CxCR_NBREQ_Msk          (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)       /*!< 0x00F80000 */

+#define DMAMUX_CxCR_NBREQ              DMAMUX_CxCR_NBREQ_Msk                   /*!<  Number of DMA requests minus 1 to forward */

+#define DMAMUX_CxCR_NBREQ_0            (0x01UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00080000 */

+#define DMAMUX_CxCR_NBREQ_1            (0x02UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00100000 */

+#define DMAMUX_CxCR_NBREQ_2            (0x04UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00200000 */

+#define DMAMUX_CxCR_NBREQ_3            (0x08UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00400000 */

+#define DMAMUX_CxCR_NBREQ_4            (0x10UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00800000 */

+#define DMAMUX_CxCR_SYNC_ID_Pos        (24U)

+#define DMAMUX_CxCR_SYNC_ID_Msk        (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)     /*!< 0x1F000000 */

+#define DMAMUX_CxCR_SYNC_ID            DMAMUX_CxCR_SYNC_ID_Msk                 /*!<  Synchronization identification */

+#define DMAMUX_CxCR_SYNC_ID_0          (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x01000000 */

+#define DMAMUX_CxCR_SYNC_ID_1          (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x02000000 */

+#define DMAMUX_CxCR_SYNC_ID_2          (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x04000000 */

+#define DMAMUX_CxCR_SYNC_ID_3          (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x08000000 */

+#define DMAMUX_CxCR_SYNC_ID_4          (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x10000000 */

+

+/********************  Bits definition for DMAMUX_CSR register  **************/

+#define DMAMUX_CSR_SOF0_Pos            (0U)

+#define DMAMUX_CSR_SOF0_Msk            (0x1UL << DMAMUX_CSR_SOF0_Pos)          /*!< 0x00000001 */

+#define DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0_Msk                     /*!< Channel 0 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF1_Pos            (1U)

+#define DMAMUX_CSR_SOF1_Msk            (0x1UL << DMAMUX_CSR_SOF1_Pos)          /*!< 0x00000002 */

+#define DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1_Msk                     /*!< Channel 1 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF2_Pos            (2U)

+#define DMAMUX_CSR_SOF2_Msk            (0x1UL << DMAMUX_CSR_SOF2_Pos)          /*!< 0x00000004 */

+#define DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2_Msk                     /*!< Channel 2 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF3_Pos            (3U)

+#define DMAMUX_CSR_SOF3_Msk            (0x1UL << DMAMUX_CSR_SOF3_Pos)          /*!< 0x00000008 */

+#define DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3_Msk                     /*!< Channel 3 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF4_Pos            (4U)

+#define DMAMUX_CSR_SOF4_Msk            (0x1UL << DMAMUX_CSR_SOF4_Pos)          /*!< 0x00000010 */

+#define DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4_Msk                     /*!< Channel 4 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF5_Pos            (5U)

+#define DMAMUX_CSR_SOF5_Msk            (0x1UL << DMAMUX_CSR_SOF5_Pos)          /*!< 0x00000020 */

+#define DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5_Msk                     /*!< Channel 5 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF6_Pos            (6U)

+#define DMAMUX_CSR_SOF6_Msk            (0x1UL << DMAMUX_CSR_SOF6_Pos)          /*!< 0x00000040 */

+#define DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6_Msk                     /*!< Channel 6 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF7_Pos            (7U)

+#define DMAMUX_CSR_SOF7_Msk            (0x1UL << DMAMUX_CSR_SOF7_Pos)          /*!< 0x00000080 */

+#define DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7_Msk                     /*!< Channel 7 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF8_Pos            (8U)

+#define DMAMUX_CSR_SOF8_Msk            (0x1UL << DMAMUX_CSR_SOF8_Pos)          /*!< 0x00000100 */

+#define DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8_Msk                     /*!< Channel 8 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF9_Pos            (9U)

+#define DMAMUX_CSR_SOF9_Msk            (0x1UL << DMAMUX_CSR_SOF9_Pos)          /*!< 0x00000200 */

+#define DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9_Msk                     /*!< Channel 9 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF10_Pos           (10U)

+#define DMAMUX_CSR_SOF10_Msk           (0x1UL << DMAMUX_CSR_SOF10_Pos)         /*!< 0x00000400 */

+#define DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10_Msk                    /*!< Channel 10 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF11_Pos           (11U)

+#define DMAMUX_CSR_SOF11_Msk           (0x1UL << DMAMUX_CSR_SOF11_Pos)         /*!< 0x00000800 */

+#define DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11_Msk                    /*!< Channel 11 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF12_Pos           (12U)

+#define DMAMUX_CSR_SOF12_Msk           (0x1UL << DMAMUX_CSR_SOF12_Pos)         /*!< 0x00001000 */

+#define DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12_Msk                    /*!< Channel 12 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF13_Pos           (13U)

+#define DMAMUX_CSR_SOF13_Msk           (0x1UL << DMAMUX_CSR_SOF13_Pos)         /*!< 0x00002000 */

+#define DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13_Msk                    /*!< Channel 13 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF14_Pos           (14U)

+#define DMAMUX_CSR_SOF14_Msk           (0x1UL << DMAMUX_CSR_SOF14_Pos)         /*!< 0x00004000 */

+#define DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14_Msk                    /*!< Channel 14 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF15_Pos           (15U)

+#define DMAMUX_CSR_SOF15_Msk           (0x1UL << DMAMUX_CSR_SOF15_Pos)         /*!< 0x00008000 */

+#define DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15_Msk                    /*!< Channel 15 Synchronization overrun event flag */

+

+/********************  Bits definition for DMAMUX_CFR register  **************/

+#define DMAMUX_CFR_CSOF0_Pos           (0U)

+#define DMAMUX_CFR_CSOF0_Msk           (0x1UL << DMAMUX_CFR_CSOF0_Pos)         /*!< 0x00000001 */

+#define DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0_Msk                    /*!< Channel 0 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF1_Pos           (1U)

+#define DMAMUX_CFR_CSOF1_Msk           (0x1UL << DMAMUX_CFR_CSOF1_Pos)         /*!< 0x00000002 */

+#define DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1_Msk                    /*!< Channel 1 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF2_Pos           (2U)

+#define DMAMUX_CFR_CSOF2_Msk           (0x1UL << DMAMUX_CFR_CSOF2_Pos)         /*!< 0x00000004 */

+#define DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2_Msk                    /*!< Channel 2 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF3_Pos           (3U)

+#define DMAMUX_CFR_CSOF3_Msk           (0x1UL << DMAMUX_CFR_CSOF3_Pos)         /*!< 0x00000008 */

+#define DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3_Msk                    /*!< Channel 3 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF4_Pos           (4U)

+#define DMAMUX_CFR_CSOF4_Msk           (0x1UL << DMAMUX_CFR_CSOF4_Pos)         /*!< 0x00000010 */

+#define DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4_Msk                    /*!< Channel 4 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF5_Pos           (5U)

+#define DMAMUX_CFR_CSOF5_Msk           (0x1UL << DMAMUX_CFR_CSOF5_Pos)         /*!< 0x00000020 */

+#define DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5_Msk                    /*!< Channel 5 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF6_Pos           (6U)

+#define DMAMUX_CFR_CSOF6_Msk           (0x1UL << DMAMUX_CFR_CSOF6_Pos)         /*!< 0x00000040 */

+#define DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6_Msk                    /*!< Channel 6 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF7_Pos           (7U)

+#define DMAMUX_CFR_CSOF7_Msk           (0x1UL << DMAMUX_CFR_CSOF7_Pos)         /*!< 0x00000080 */

+#define DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7_Msk                    /*!< Channel 7 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF8_Pos           (8U)

+#define DMAMUX_CFR_CSOF8_Msk           (0x1UL << DMAMUX_CFR_CSOF8_Pos)         /*!< 0x00000100 */

+#define DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8_Msk                    /*!< Channel 8 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF9_Pos           (9U)

+#define DMAMUX_CFR_CSOF9_Msk           (0x1UL << DMAMUX_CFR_CSOF9_Pos)         /*!< 0x00000200 */

+#define DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9_Msk                    /*!< Channel 9 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF10_Pos          (10U)

+#define DMAMUX_CFR_CSOF10_Msk          (0x1UL << DMAMUX_CFR_CSOF10_Pos)        /*!< 0x00000400 */

+#define DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10_Msk                   /*!< Channel 10 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF11_Pos          (11U)

+#define DMAMUX_CFR_CSOF11_Msk          (0x1UL << DMAMUX_CFR_CSOF11_Pos)        /*!< 0x00000800 */

+#define DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11_Msk                   /*!< Channel 11 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF12_Pos          (12U)

+#define DMAMUX_CFR_CSOF12_Msk          (0x1UL << DMAMUX_CFR_CSOF12_Pos)        /*!< 0x00001000 */

+#define DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12_Msk                   /*!< Channel 12 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF13_Pos          (13U)

+#define DMAMUX_CFR_CSOF13_Msk          (0x1UL << DMAMUX_CFR_CSOF13_Pos)        /*!< 0x00002000 */

+#define DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13_Msk                   /*!< Channel 13 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF14_Pos          (14U)

+#define DMAMUX_CFR_CSOF14_Msk          (0x1UL << DMAMUX_CFR_CSOF14_Pos)        /*!< 0x00004000 */

+#define DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14_Msk                   /*!< Channel 14 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF15_Pos          (15U)

+#define DMAMUX_CFR_CSOF15_Msk          (0x1UL << DMAMUX_CFR_CSOF15_Pos)        /*!< 0x00008000 */

+#define DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15_Msk                   /*!< Channel 15 Clear synchronization overrun event flag */

+

+/********************  Bits definition for DMAMUX_RGxCR register  ************/

+#define DMAMUX_RGxCR_SIG_ID_Pos        (0U)

+#define DMAMUX_RGxCR_SIG_ID_Msk        (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)     /*!< 0x0000001F */

+#define DMAMUX_RGxCR_SIG_ID            DMAMUX_RGxCR_SIG_ID_Msk                 /*!< Signal identification */

+#define DMAMUX_RGxCR_SIG_ID_0          (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000001 */

+#define DMAMUX_RGxCR_SIG_ID_1          (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000002 */

+#define DMAMUX_RGxCR_SIG_ID_2          (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000004 */

+#define DMAMUX_RGxCR_SIG_ID_3          (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000008 */

+#define DMAMUX_RGxCR_SIG_ID_4          (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000010 */

+#define DMAMUX_RGxCR_OIE_Pos           (8U)

+#define DMAMUX_RGxCR_OIE_Msk           (0x1UL << DMAMUX_RGxCR_OIE_Pos)         /*!< 0x00000100 */

+#define DMAMUX_RGxCR_OIE               DMAMUX_RGxCR_OIE_Msk                    /*!< Trigger overrun interrupt enable */

+#define DMAMUX_RGxCR_GE_Pos            (16U)

+#define DMAMUX_RGxCR_GE_Msk            (0x1UL << DMAMUX_RGxCR_GE_Pos)          /*!< 0x00010000 */

+#define DMAMUX_RGxCR_GE                DMAMUX_RGxCR_GE_Msk                     /*!< DMA request generator enable */

+#define DMAMUX_RGxCR_GPOL_Pos          (17U)

+#define DMAMUX_RGxCR_GPOL_Msk          (0x3UL << DMAMUX_RGxCR_GPOL_Pos)        /*!< 0x00060000 */

+#define DMAMUX_RGxCR_GPOL              DMAMUX_RGxCR_GPOL_Msk                   /*!< DMA request generator trigger polarity */

+#define DMAMUX_RGxCR_GPOL_0            (0x1UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00020000 */

+#define DMAMUX_RGxCR_GPOL_1            (0x2UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00040000 */

+#define DMAMUX_RGxCR_GNBREQ_Pos        (19U)

+#define DMAMUX_RGxCR_GNBREQ_Msk        (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)     /*!< 0x00F80000 */

+#define DMAMUX_RGxCR_GNBREQ            DMAMUX_RGxCR_GNBREQ_Msk                 /*!< Number of DMA requests to be generated */

+#define DMAMUX_RGxCR_GNBREQ_0          (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00080000 */

+#define DMAMUX_RGxCR_GNBREQ_1          (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00100000 */

+#define DMAMUX_RGxCR_GNBREQ_2          (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00200000 */

+#define DMAMUX_RGxCR_GNBREQ_3          (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00400000 */

+#define DMAMUX_RGxCR_GNBREQ_4          (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00800000 */

+

+/********************  Bits definition for DMAMUX_RGSR register  **************/

+#define DMAMUX_RGSR_OF0_Pos            (0U)

+#define DMAMUX_RGSR_OF0_Msk            (0x1UL << DMAMUX_RGSR_OF0_Pos)          /*!< 0x00000001 */

+#define DMAMUX_RGSR_OF0                DMAMUX_RGSR_OF0_Msk                     /*!< Request generator channel 0 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF1_Pos            (1U)

+#define DMAMUX_RGSR_OF1_Msk            (0x1UL << DMAMUX_RGSR_OF1_Pos)          /*!< 0x00000002 */

+#define DMAMUX_RGSR_OF1                DMAMUX_RGSR_OF1_Msk                     /*!< Request generator channel 1 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF2_Pos            (2U)

+#define DMAMUX_RGSR_OF2_Msk            (0x1UL << DMAMUX_RGSR_OF2_Pos)          /*!< 0x00000004 */

+#define DMAMUX_RGSR_OF2                DMAMUX_RGSR_OF2_Msk                     /*!< Request generator channel 2 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF3_Pos            (3U)

+#define DMAMUX_RGSR_OF3_Msk            (0x1UL << DMAMUX_RGSR_OF3_Pos)          /*!< 0x00000008 */

+#define DMAMUX_RGSR_OF3                DMAMUX_RGSR_OF3_Msk                     /*!< Request generator channel 3 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF4_Pos            (4U)

+#define DMAMUX_RGSR_OF4_Msk            (0x1UL << DMAMUX_RGSR_OF4_Pos)          /*!< 0x00000010 */

+#define DMAMUX_RGSR_OF4                DMAMUX_RGSR_OF4_Msk                     /*!< Request generator channel 4 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF5_Pos            (5U)

+#define DMAMUX_RGSR_OF5_Msk            (0x1UL << DMAMUX_RGSR_OF5_Pos)          /*!< 0x00000020 */

+#define DMAMUX_RGSR_OF5                DMAMUX_RGSR_OF5_Msk                     /*!< Request generator channel 5 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF6_Pos            (6U)

+#define DMAMUX_RGSR_OF6_Msk            (0x1UL << DMAMUX_RGSR_OF6_Pos)          /*!< 0x00000040 */

+#define DMAMUX_RGSR_OF6                DMAMUX_RGSR_OF6_Msk                     /*!< Request generator channel 6 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF7_Pos            (7U)

+#define DMAMUX_RGSR_OF7_Msk            (0x1UL << DMAMUX_RGSR_OF7_Pos)          /*!< 0x00000080 */

+#define DMAMUX_RGSR_OF7                DMAMUX_RGSR_OF7_Msk                     /*!< Request generator channel 7 Trigger overrun event flag */

+

+/********************  Bits definition for DMAMUX_RGCFR register  **************/

+#define DMAMUX_RGCFR_COF0_Pos          (0U)

+#define DMAMUX_RGCFR_COF0_Msk          (0x1UL << DMAMUX_RGCFR_COF0_Pos)        /*!< 0x00000001 */

+#define DMAMUX_RGCFR_COF0              DMAMUX_RGCFR_COF0_Msk                   /*!< Request generator channel 0 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF1_Pos          (1U)

+#define DMAMUX_RGCFR_COF1_Msk          (0x1UL << DMAMUX_RGCFR_COF1_Pos)        /*!< 0x00000002 */

+#define DMAMUX_RGCFR_COF1              DMAMUX_RGCFR_COF1_Msk                   /*!< Request generator channel 1 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF2_Pos          (2U)

+#define DMAMUX_RGCFR_COF2_Msk          (0x1UL << DMAMUX_RGCFR_COF2_Pos)        /*!< 0x00000004 */

+#define DMAMUX_RGCFR_COF2              DMAMUX_RGCFR_COF2_Msk                   /*!< Request generator channel 2 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF3_Pos          (3U)

+#define DMAMUX_RGCFR_COF3_Msk          (0x1UL << DMAMUX_RGCFR_COF3_Pos)        /*!< 0x00000008 */

+#define DMAMUX_RGCFR_COF3              DMAMUX_RGCFR_COF3_Msk                   /*!< Request generator channel 3 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF4_Pos          (4U)

+#define DMAMUX_RGCFR_COF4_Msk          (0x1UL << DMAMUX_RGCFR_COF4_Pos)        /*!< 0x00000010 */

+#define DMAMUX_RGCFR_COF4              DMAMUX_RGCFR_COF4_Msk                   /*!< Request generator channel 4 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF5_Pos          (5U)

+#define DMAMUX_RGCFR_COF5_Msk          (0x1UL << DMAMUX_RGCFR_COF5_Pos)        /*!< 0x00000020 */

+#define DMAMUX_RGCFR_COF5              DMAMUX_RGCFR_COF5_Msk                   /*!< Request generator channel 5 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF6_Pos          (6U)

+#define DMAMUX_RGCFR_COF6_Msk          (0x1UL << DMAMUX_RGCFR_COF6_Pos)        /*!< 0x00000040 */

+#define DMAMUX_RGCFR_COF6              DMAMUX_RGCFR_COF6_Msk                   /*!< Request generator channel 6 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF7_Pos          (7U)

+#define DMAMUX_RGCFR_COF7_Msk          (0x1UL << DMAMUX_RGCFR_COF7_Pos)        /*!< 0x00000080 */

+#define DMAMUX_RGCFR_COF7              DMAMUX_RGCFR_COF7_Msk                   /*!< Request generator channel 7 Clear trigger overrun event flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         AHB Master DMA2D Controller (DMA2D)                */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for DMA2D_CR register  ******************/

+

+#define DMA2D_CR_START_Pos         (0U)

+#define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)               /*!< 0x00000001 */

+#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer                          */

+#define DMA2D_CR_SUSP_Pos          (1U)

+#define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                /*!< 0x00000002 */

+#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer                        */

+#define DMA2D_CR_ABORT_Pos         (2U)

+#define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)               /*!< 0x00000004 */

+#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer                          */

+#define DMA2D_CR_LOM_Pos           (6U)

+#define DMA2D_CR_LOM_Msk           (0x1UL << DMA2D_CR_LOM_Pos)                 /*!< 0x00000040 */

+#define DMA2D_CR_LOM               DMA2D_CR_LOM_Msk                            /*!< Line Offset Mode                         */

+#define DMA2D_CR_TEIE_Pos          (8U)

+#define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                /*!< 0x00000100 */

+#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable         */

+#define DMA2D_CR_TCIE_Pos          (9U)

+#define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                /*!< 0x00000200 */

+#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable      */

+#define DMA2D_CR_TWIE_Pos          (10U)

+#define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                /*!< 0x00000400 */

+#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable     */

+#define DMA2D_CR_CAEIE_Pos         (11U)

+#define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)               /*!< 0x00000800 */

+#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable      */

+#define DMA2D_CR_CTCIE_Pos         (12U)

+#define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)               /*!< 0x00001000 */

+#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */

+#define DMA2D_CR_CEIE_Pos          (13U)

+#define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                /*!< 0x00002000 */

+#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable    */

+#define DMA2D_CR_MODE_Pos          (16U)

+#define DMA2D_CR_MODE_Msk          (0x7UL << DMA2D_CR_MODE_Pos)                /*!< 0x00070000 */

+#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[2:0]                         */

+#define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */

+#define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */

+#define DMA2D_CR_MODE_2            (0x4UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00040000 */

+

+/********************  Bit definition for DMA2D_ISR register  *****************/

+

+#define DMA2D_ISR_TEIF_Pos         (0U)

+#define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)               /*!< 0x00000001 */

+#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag         */

+#define DMA2D_ISR_TCIF_Pos         (1U)

+#define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)               /*!< 0x00000002 */

+#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag      */

+#define DMA2D_ISR_TWIF_Pos         (2U)

+#define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)               /*!< 0x00000004 */

+#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag     */

+#define DMA2D_ISR_CAEIF_Pos        (3U)

+#define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)              /*!< 0x00000008 */

+#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag      */

+#define DMA2D_ISR_CTCIF_Pos        (4U)

+#define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)              /*!< 0x00000010 */

+#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */

+#define DMA2D_ISR_CEIF_Pos         (5U)

+#define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)               /*!< 0x00000020 */

+#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag    */

+

+/********************  Bit definition for DMA2D_IFCR register  ****************/

+

+#define DMA2D_IFCR_CTEIF_Pos       (0U)

+#define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)             /*!< 0x00000001 */

+#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */

+#define DMA2D_IFCR_CTCIF_Pos       (1U)

+#define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)             /*!< 0x00000002 */

+#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */

+#define DMA2D_IFCR_CTWIF_Pos       (2U)

+#define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)             /*!< 0x00000004 */

+#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */

+#define DMA2D_IFCR_CAECIF_Pos      (3U)

+#define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)            /*!< 0x00000008 */

+#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */

+#define DMA2D_IFCR_CCTCIF_Pos      (4U)

+#define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)            /*!< 0x00000010 */

+#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */

+#define DMA2D_IFCR_CCEIF_Pos       (5U)

+#define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)             /*!< 0x00000020 */

+#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */

+

+/********************  Bit definition for DMA2D_FGMAR register  ***************/

+

+#define DMA2D_FGMAR_MA_Pos         (0U)

+#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)        /*!< 0xFFFFFFFF */

+#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Foreground Memory Address */

+

+/********************  Bit definition for DMA2D_FGOR register  ****************/

+

+#define DMA2D_FGOR_LO_Pos          (0U)

+#define DMA2D_FGOR_LO_Msk          (0xFFFFUL << DMA2D_FGOR_LO_Pos)             /*!< 0x0000FFFF */

+#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */

+

+/********************  Bit definition for DMA2D_BGMAR register  ***************/

+

+#define DMA2D_BGMAR_MA_Pos         (0U)

+#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)        /*!< 0xFFFFFFFF */

+#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Background Memory Address */

+

+/********************  Bit definition for DMA2D_BGOR register  ****************/

+

+#define DMA2D_BGOR_LO_Pos          (0U)

+#define DMA2D_BGOR_LO_Msk          (0xFFFFUL << DMA2D_BGOR_LO_Pos)             /*!< 0x0000FFFF */

+#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */

+

+/********************  Bit definition for DMA2D_FGPFCCR register  *************/

+

+#define DMA2D_FGPFCCR_CM_Pos       (0U)

+#define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x0000000F */

+#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */

+#define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */

+#define DMA2D_FGPFCCR_CCM_Pos      (4U)

+#define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)            /*!< 0x00000010 */

+#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */

+#define DMA2D_FGPFCCR_START_Pos    (5U)

+#define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)          /*!< 0x00000020 */

+#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */

+#define DMA2D_FGPFCCR_CS_Pos       (8U)

+#define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)            /*!< 0x0000FF00 */

+#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */

+#define DMA2D_FGPFCCR_AM_Pos       (16U)

+#define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00030000 */

+#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */

+#define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */

+#define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */

+#define DMA2D_FGPFCCR_CSS_Pos      (18U)

+#define DMA2D_FGPFCCR_CSS_Msk      (0x3UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x000C0000 */

+#define DMA2D_FGPFCCR_CSS          DMA2D_FGPFCCR_CSS_Msk                       /* !< Chroma Sub-Sampling */

+#define DMA2D_FGPFCCR_CSS_0        (0x1UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00040000 */

+#define DMA2D_FGPFCCR_CSS_1        (0x2UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00080000 */

+#define DMA2D_FGPFCCR_AI_Pos       (20U)

+#define DMA2D_FGPFCCR_AI_Msk       (0x1UL << DMA2D_FGPFCCR_AI_Pos)             /*!< 0x00100000 */

+#define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Foreground Input Alpha Inverted */

+#define DMA2D_FGPFCCR_RBS_Pos      (21U)

+#define DMA2D_FGPFCCR_RBS_Msk      (0x1UL << DMA2D_FGPFCCR_RBS_Pos)            /*!< 0x00200000 */

+#define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Foreground Input Red Blue Swap */

+#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)

+#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */

+#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */

+

+/********************  Bit definition for DMA2D_FGCOLR register  **************/

+

+#define DMA2D_FGCOLR_BLUE_Pos      (0U)

+#define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)           /*!< 0x000000FF */

+#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Foreground Blue Value */

+#define DMA2D_FGCOLR_GREEN_Pos     (8U)

+#define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */

+#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Foreground Green Value */

+#define DMA2D_FGCOLR_RED_Pos       (16U)

+#define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)            /*!< 0x00FF0000 */

+#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Foreground Red Value */

+

+/********************  Bit definition for DMA2D_BGPFCCR register  *************/

+

+#define DMA2D_BGPFCCR_CM_Pos       (0U)

+#define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x0000000F */

+#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */

+#define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_BGPFCCR_CM_3         (0x8UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000008 */

+#define DMA2D_BGPFCCR_CCM_Pos      (4U)

+#define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)            /*!< 0x00000010 */

+#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */

+#define DMA2D_BGPFCCR_START_Pos    (5U)

+#define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)          /*!< 0x00000020 */

+#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */

+#define DMA2D_BGPFCCR_CS_Pos       (8U)

+#define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)            /*!< 0x0000FF00 */

+#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */

+#define DMA2D_BGPFCCR_AM_Pos       (16U)

+#define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00030000 */

+#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */

+#define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */

+#define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */

+#define DMA2D_BGPFCCR_AI_Pos       (20U)

+#define DMA2D_BGPFCCR_AI_Msk       (0x1UL << DMA2D_BGPFCCR_AI_Pos)             /*!< 0x00100000 */

+#define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< background Input Alpha Inverted */

+#define DMA2D_BGPFCCR_RBS_Pos      (21U)

+#define DMA2D_BGPFCCR_RBS_Msk      (0x1UL << DMA2D_BGPFCCR_RBS_Pos)            /*!< 0x00200000 */

+#define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Background Input Red Blue Swap */

+#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)

+#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */

+#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */

+

+/********************  Bit definition for DMA2D_BGCOLR register  **************/

+

+#define DMA2D_BGCOLR_BLUE_Pos      (0U)

+#define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)           /*!< 0x000000FF */

+#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Background Blue Value */

+#define DMA2D_BGCOLR_GREEN_Pos     (8U)

+#define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */

+#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Background Green Value */

+#define DMA2D_BGCOLR_RED_Pos       (16U)

+#define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)            /*!< 0x00FF0000 */

+#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Background Red Value */

+

+/********************  Bit definition for DMA2D_FGCMAR register  **************/

+

+#define DMA2D_FGCMAR_MA_Pos        (0U)

+#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */

+#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Foreground CLUT Memory Address */

+

+/********************  Bit definition for DMA2D_BGCMAR register  **************/

+

+#define DMA2D_BGCMAR_MA_Pos        (0U)

+#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */

+#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Background CLUT Memory Address */

+

+/********************  Bit definition for DMA2D_OPFCCR register  **************/

+

+#define DMA2D_OPFCCR_CM_Pos        (0U)

+#define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000007 */

+#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Output Color mode CM[2:0] */

+#define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_OPFCCR_SB_Pos        (8U)

+#define DMA2D_OPFCCR_SB_Msk        (0x1UL << DMA2D_OPFCCR_SB_Pos)              /*!< 0x00000100 */

+#define DMA2D_OPFCCR_SB            DMA2D_OPFCCR_SB_Msk                         /*!< Swap Bytes */

+#define DMA2D_OPFCCR_AI_Pos        (20U)

+#define DMA2D_OPFCCR_AI_Msk        (0x1UL << DMA2D_OPFCCR_AI_Pos)              /*!< 0x00100000 */

+#define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Output Alpha Inverted */

+#define DMA2D_OPFCCR_RBS_Pos       (21U)

+#define DMA2D_OPFCCR_RBS_Msk       (0x1UL << DMA2D_OPFCCR_RBS_Pos)             /*!< 0x00200000 */

+#define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Output Red Blue Swap */

+

+/********************  Bit definition for DMA2D_OCOLR register  ***************/

+

+/*!<Mode_ARGB8888/RGB888 */

+

+#define DMA2D_OCOLR_BLUE_1_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_1_Msk     (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos)            /*0x000000FFU*/

+#define DMA2D_OCOLR_BLUE_1         DMA2D_OCOLR_BLUE_1_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_1_Pos    (8U)

+#define DMA2D_OCOLR_GREEN_1_Msk    (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos)            /*0x0000FF00U)*/

+#define DMA2D_OCOLR_GREEN_1        DMA2D_OCOLR_GREEN_1_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_1_Pos      (16U)

+#define DMA2D_OCOLR_RED_1_Msk      (0xFFUL << DMA2D_OCOLR_RED_1_Pos)            /*0x00FF0000U */

+#define DMA2D_OCOLR_RED_1          DMA2D_OCOLR_RED_1_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_1_Pos    (24U)

+#define DMA2D_OCOLR_ALPHA_1_Msk    (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos)          /*0xFF000000U*/

+#define DMA2D_OCOLR_ALPHA_1        DMA2D_OCOLR_ALPHA_1_Msk                     /*!< Output Alpha Channel Value */

+

+/*!<Mode_RGB565 */

+#define DMA2D_OCOLR_BLUE_2_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_2_Msk     (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos)            /*0x0000001FU*/

+#define DMA2D_OCOLR_BLUE_2         DMA2D_OCOLR_BLUE_2_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_2_Pos    (5U)

+#define DMA2D_OCOLR_GREEN_2_Msk    (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos)          /* 0x000007E0U */

+#define DMA2D_OCOLR_GREEN_2        DMA2D_OCOLR_GREEN_2_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_2_Pos      (11U)

+#define DMA2D_OCOLR_RED_2_Msk      (0xF8UL<<DMA2D_OCOLR_RED_2_Pos)              /*0x0000F800U*/

+#define DMA2D_OCOLR_RED_2          DMA2D_OCOLR_RED_2_Msk                       /*!< Output Red Value */

+

+/*!<Mode_ARGB1555 */

+#define DMA2D_OCOLR_BLUE_3_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_3_Msk     (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos)           /*0x0000001FU*/

+#define DMA2D_OCOLR_BLUE_3         DMA2D_OCOLR_BLUE_3_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_3_Pos    (5U)

+#define DMA2D_OCOLR_GREEN_3_Msk    (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos)          /*0x000003E0U*/

+#define DMA2D_OCOLR_GREEN_3        DMA2D_OCOLR_GREEN_3_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_3_Pos      (10U)

+#define DMA2D_OCOLR_RED_3_Msk      (0x7CUL << DMA2D_OCOLR_RED_3_Pos)            /* 0x00007C00U*/

+#define DMA2D_OCOLR_RED_3          DMA2D_OCOLR_RED_3_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_3_Pos    (15U)

+#define DMA2D_OCOLR_ALPHA_3_Msk    (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos)           /*0x00008000U*/

+#define DMA2D_OCOLR_ALPHA_3        DMA2D_OCOLR_ALPHA_3_Msk                     /*!< Output Alpha Channel Value */

+

+/*!<Mode_ARGB4444 */

+#define DMA2D_OCOLR_BLUE_4_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_4_Msk     (0xFUL << DMA2D_OCOLR_BLUE_4_Pos)            /*0x0000000FU*/

+#define DMA2D_OCOLR_BLUE_4         DMA2D_OCOLR_BLUE_4_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_4_Pos    (4U)

+#define DMA2D_OCOLR_GREEN_4_Msk    (0xFUL << DMA2D_OCOLR_GREEN_4_Pos)           /*0x000000F0U*/

+#define DMA2D_OCOLR_GREEN_4        DMA2D_OCOLR_GREEN_4_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_4_Pos      (8U)

+#define DMA2D_OCOLR_RED_4_Msk      (0xFUL << DMA2D_OCOLR_RED_4_Pos)             /*0x00000F00U*/

+#define DMA2D_OCOLR_RED_4          DMA2D_OCOLR_RED_4_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_4_Pos    (12U)

+#define DMA2D_OCOLR_ALPHA_4_Msk    (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos)            /*0x0000F000U*/

+#define DMA2D_OCOLR_ALPHA_4        DMA2D_OCOLR_ALPHA_4_Msk                     /*!< Output Alpha Channel Value */

+

+/********************  Bit definition for DMA2D_OMAR register  ****************/

+

+#define DMA2D_OMAR_MA_Pos          (0U)

+#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)         /*!< 0xFFFFFFFF */

+#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Output Memory Address */

+

+/********************  Bit definition for DMA2D_OOR register  *****************/

+

+#define DMA2D_OOR_LO_Pos           (0U)

+#define DMA2D_OOR_LO_Msk           (0xFFFFUL << DMA2D_OOR_LO_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Output Line Offset */

+

+/********************  Bit definition for DMA2D_NLR register  *****************/

+

+#define DMA2D_NLR_NL_Pos           (0U)

+#define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */

+#define DMA2D_NLR_PL_Pos           (16U)

+#define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)              /*!< 0x3FFF0000 */

+#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */

+

+/********************  Bit definition for DMA2D_LWR register  *****************/

+

+#define DMA2D_LWR_LW_Pos           (0U)

+#define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */

+

+/********************  Bit definition for DMA2D_AMTCR register  ***************/

+

+#define DMA2D_AMTCR_EN_Pos         (0U)

+#define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)               /*!< 0x00000001 */

+#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */

+#define DMA2D_AMTCR_DT_Pos         (8U)

+#define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)              /*!< 0x0000FF00 */

+#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */

+

+

+/********************  Bit definition for DMA2D_FGCLUT register  **************/

+

+/********************  Bit definition for DMA2D_BGCLUT register  **************/

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                    External Interrupt/Event Controller                     */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for EXTI_RTSR1 register  *******************/

+#define EXTI_RTSR1_TR_Pos          (0U)

+#define EXTI_RTSR1_TR_Msk          (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)           /*!< 0x003FFFFF */

+#define EXTI_RTSR1_TR              EXTI_RTSR1_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR1_TR0_Pos         (0U)

+#define EXTI_RTSR1_TR0_Msk         (0x1UL << EXTI_RTSR1_TR0_Pos)               /*!< 0x00000001 */

+#define EXTI_RTSR1_TR0             EXTI_RTSR1_TR0_Msk                          /*!< Rising trigger event configuration bit of line 0 */

+#define EXTI_RTSR1_TR1_Pos         (1U)

+#define EXTI_RTSR1_TR1_Msk         (0x1UL << EXTI_RTSR1_TR1_Pos)               /*!< 0x00000002 */

+#define EXTI_RTSR1_TR1             EXTI_RTSR1_TR1_Msk                          /*!< Rising trigger event configuration bit of line 1 */

+#define EXTI_RTSR1_TR2_Pos         (2U)

+#define EXTI_RTSR1_TR2_Msk         (0x1UL << EXTI_RTSR1_TR2_Pos)               /*!< 0x00000004 */

+#define EXTI_RTSR1_TR2             EXTI_RTSR1_TR2_Msk                          /*!< Rising trigger event configuration bit of line 2 */

+#define EXTI_RTSR1_TR3_Pos         (3U)

+#define EXTI_RTSR1_TR3_Msk         (0x1UL << EXTI_RTSR1_TR3_Pos)               /*!< 0x00000008 */

+#define EXTI_RTSR1_TR3             EXTI_RTSR1_TR3_Msk                          /*!< Rising trigger event configuration bit of line 3 */

+#define EXTI_RTSR1_TR4_Pos         (4U)

+#define EXTI_RTSR1_TR4_Msk         (0x1UL << EXTI_RTSR1_TR4_Pos)               /*!< 0x00000010 */

+#define EXTI_RTSR1_TR4             EXTI_RTSR1_TR4_Msk                          /*!< Rising trigger event configuration bit of line 4 */

+#define EXTI_RTSR1_TR5_Pos         (5U)

+#define EXTI_RTSR1_TR5_Msk         (0x1UL << EXTI_RTSR1_TR5_Pos)               /*!< 0x00000020 */

+#define EXTI_RTSR1_TR5             EXTI_RTSR1_TR5_Msk                          /*!< Rising trigger event configuration bit of line 5 */

+#define EXTI_RTSR1_TR6_Pos         (6U)

+#define EXTI_RTSR1_TR6_Msk         (0x1UL << EXTI_RTSR1_TR6_Pos)               /*!< 0x00000040 */

+#define EXTI_RTSR1_TR6             EXTI_RTSR1_TR6_Msk                          /*!< Rising trigger event configuration bit of line 6 */

+#define EXTI_RTSR1_TR7_Pos         (7U)

+#define EXTI_RTSR1_TR7_Msk         (0x1UL << EXTI_RTSR1_TR7_Pos)               /*!< 0x00000080 */

+#define EXTI_RTSR1_TR7             EXTI_RTSR1_TR7_Msk                          /*!< Rising trigger event configuration bit of line 7 */

+#define EXTI_RTSR1_TR8_Pos         (8U)

+#define EXTI_RTSR1_TR8_Msk         (0x1UL << EXTI_RTSR1_TR8_Pos)               /*!< 0x00000100 */

+#define EXTI_RTSR1_TR8             EXTI_RTSR1_TR8_Msk                          /*!< Rising trigger event configuration bit of line 8 */

+#define EXTI_RTSR1_TR9_Pos         (9U)

+#define EXTI_RTSR1_TR9_Msk         (0x1UL << EXTI_RTSR1_TR9_Pos)               /*!< 0x00000200 */

+#define EXTI_RTSR1_TR9             EXTI_RTSR1_TR9_Msk                          /*!< Rising trigger event configuration bit of line 9 */

+#define EXTI_RTSR1_TR10_Pos        (10U)

+#define EXTI_RTSR1_TR10_Msk        (0x1UL << EXTI_RTSR1_TR10_Pos)              /*!< 0x00000400 */

+#define EXTI_RTSR1_TR10            EXTI_RTSR1_TR10_Msk                         /*!< Rising trigger event configuration bit of line 10 */

+#define EXTI_RTSR1_TR11_Pos        (11U)

+#define EXTI_RTSR1_TR11_Msk        (0x1UL << EXTI_RTSR1_TR11_Pos)              /*!< 0x00000800 */

+#define EXTI_RTSR1_TR11            EXTI_RTSR1_TR11_Msk                         /*!< Rising trigger event configuration bit of line 11 */

+#define EXTI_RTSR1_TR12_Pos        (12U)

+#define EXTI_RTSR1_TR12_Msk        (0x1UL << EXTI_RTSR1_TR12_Pos)              /*!< 0x00001000 */

+#define EXTI_RTSR1_TR12            EXTI_RTSR1_TR12_Msk                         /*!< Rising trigger event configuration bit of line 12 */

+#define EXTI_RTSR1_TR13_Pos        (13U)

+#define EXTI_RTSR1_TR13_Msk        (0x1UL << EXTI_RTSR1_TR13_Pos)              /*!< 0x00002000 */

+#define EXTI_RTSR1_TR13            EXTI_RTSR1_TR13_Msk                         /*!< Rising trigger event configuration bit of line 13 */

+#define EXTI_RTSR1_TR14_Pos        (14U)

+#define EXTI_RTSR1_TR14_Msk        (0x1UL << EXTI_RTSR1_TR14_Pos)              /*!< 0x00004000 */

+#define EXTI_RTSR1_TR14            EXTI_RTSR1_TR14_Msk                         /*!< Rising trigger event configuration bit of line 14 */

+#define EXTI_RTSR1_TR15_Pos        (15U)

+#define EXTI_RTSR1_TR15_Msk        (0x1UL << EXTI_RTSR1_TR15_Pos)              /*!< 0x00008000 */

+#define EXTI_RTSR1_TR15            EXTI_RTSR1_TR15_Msk                         /*!< Rising trigger event configuration bit of line 15 */

+#define EXTI_RTSR1_TR16_Pos        (16U)

+#define EXTI_RTSR1_TR16_Msk        (0x1UL << EXTI_RTSR1_TR16_Pos)              /*!< 0x00010000 */

+#define EXTI_RTSR1_TR16            EXTI_RTSR1_TR16_Msk                         /*!< Rising trigger event configuration bit of line 16 */

+#define EXTI_RTSR1_TR17_Pos        (17U)

+#define EXTI_RTSR1_TR17_Msk        (0x1UL << EXTI_RTSR1_TR17_Pos)              /*!< 0x00020000 */

+#define EXTI_RTSR1_TR17            EXTI_RTSR1_TR17_Msk                         /*!< Rising trigger event configuration bit of line 17 */

+#define EXTI_RTSR1_TR18_Pos        (18U)

+#define EXTI_RTSR1_TR18_Msk        (0x1UL << EXTI_RTSR1_TR18_Pos)              /*!< 0x00040000 */

+#define EXTI_RTSR1_TR18            EXTI_RTSR1_TR18_Msk                         /*!< Rising trigger event configuration bit of line 18 */

+#define EXTI_RTSR1_TR19_Pos        (19U)

+#define EXTI_RTSR1_TR19_Msk        (0x1UL << EXTI_RTSR1_TR19_Pos)              /*!< 0x00080000 */

+#define EXTI_RTSR1_TR19            EXTI_RTSR1_TR19_Msk                         /*!< Rising trigger event configuration bit of line 19 */

+#define EXTI_RTSR1_TR20_Pos        (20U)

+#define EXTI_RTSR1_TR20_Msk        (0x1UL << EXTI_RTSR1_TR20_Pos)              /*!< 0x00100000 */

+#define EXTI_RTSR1_TR20            EXTI_RTSR1_TR20_Msk                         /*!< Rising trigger event configuration bit of line 20 */

+#define EXTI_RTSR1_TR21_Pos        (21U)

+#define EXTI_RTSR1_TR21_Msk        (0x1UL << EXTI_RTSR1_TR21_Pos)              /*!< 0x00200000 */

+#define EXTI_RTSR1_TR21            EXTI_RTSR1_TR21_Msk                         /*!< Rising trigger event configuration bit of line 21 */

+

+/******************  Bit definition for EXTI_FTSR1 register  *******************/

+#define EXTI_FTSR1_TR_Pos          (0U)

+#define EXTI_FTSR1_TR_Msk          (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)           /*!< 0x003FFFFF */

+#define EXTI_FTSR1_TR              EXTI_FTSR1_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR1_TR0_Pos         (0U)

+#define EXTI_FTSR1_TR0_Msk         (0x1UL << EXTI_FTSR1_TR0_Pos)               /*!< 0x00000001 */

+#define EXTI_FTSR1_TR0             EXTI_FTSR1_TR0_Msk                          /*!< Falling trigger event configuration bit of line 0 */

+#define EXTI_FTSR1_TR1_Pos         (1U)

+#define EXTI_FTSR1_TR1_Msk         (0x1UL << EXTI_FTSR1_TR1_Pos)               /*!< 0x00000002 */

+#define EXTI_FTSR1_TR1             EXTI_FTSR1_TR1_Msk                          /*!< Falling trigger event configuration bit of line 1 */

+#define EXTI_FTSR1_TR2_Pos         (2U)

+#define EXTI_FTSR1_TR2_Msk         (0x1UL << EXTI_FTSR1_TR2_Pos)               /*!< 0x00000004 */

+#define EXTI_FTSR1_TR2             EXTI_FTSR1_TR2_Msk                          /*!< Falling trigger event configuration bit of line 2 */

+#define EXTI_FTSR1_TR3_Pos         (3U)

+#define EXTI_FTSR1_TR3_Msk         (0x1UL << EXTI_FTSR1_TR3_Pos)               /*!< 0x00000008 */

+#define EXTI_FTSR1_TR3             EXTI_FTSR1_TR3_Msk                          /*!< Falling trigger event configuration bit of line 3 */

+#define EXTI_FTSR1_TR4_Pos         (4U)

+#define EXTI_FTSR1_TR4_Msk         (0x1UL << EXTI_FTSR1_TR4_Pos)               /*!< 0x00000010 */

+#define EXTI_FTSR1_TR4             EXTI_FTSR1_TR4_Msk                          /*!< Falling trigger event configuration bit of line 4 */

+#define EXTI_FTSR1_TR5_Pos         (5U)

+#define EXTI_FTSR1_TR5_Msk         (0x1UL << EXTI_FTSR1_TR5_Pos)               /*!< 0x00000020 */

+#define EXTI_FTSR1_TR5             EXTI_FTSR1_TR5_Msk                          /*!< Falling trigger event configuration bit of line 5 */

+#define EXTI_FTSR1_TR6_Pos         (6U)

+#define EXTI_FTSR1_TR6_Msk         (0x1UL << EXTI_FTSR1_TR6_Pos)               /*!< 0x00000040 */

+#define EXTI_FTSR1_TR6             EXTI_FTSR1_TR6_Msk                          /*!< Falling trigger event configuration bit of line 6 */

+#define EXTI_FTSR1_TR7_Pos         (7U)

+#define EXTI_FTSR1_TR7_Msk         (0x1UL << EXTI_FTSR1_TR7_Pos)               /*!< 0x00000080 */

+#define EXTI_FTSR1_TR7             EXTI_FTSR1_TR7_Msk                          /*!< Falling trigger event configuration bit of line 7 */

+#define EXTI_FTSR1_TR8_Pos         (8U)

+#define EXTI_FTSR1_TR8_Msk         (0x1UL << EXTI_FTSR1_TR8_Pos)               /*!< 0x00000100 */

+#define EXTI_FTSR1_TR8             EXTI_FTSR1_TR8_Msk                          /*!< Falling trigger event configuration bit of line 8 */

+#define EXTI_FTSR1_TR9_Pos         (9U)

+#define EXTI_FTSR1_TR9_Msk         (0x1UL << EXTI_FTSR1_TR9_Pos)               /*!< 0x00000200 */

+#define EXTI_FTSR1_TR9             EXTI_FTSR1_TR9_Msk                          /*!< Falling trigger event configuration bit of line 9 */

+#define EXTI_FTSR1_TR10_Pos        (10U)

+#define EXTI_FTSR1_TR10_Msk        (0x1UL << EXTI_FTSR1_TR10_Pos)              /*!< 0x00000400 */

+#define EXTI_FTSR1_TR10            EXTI_FTSR1_TR10_Msk                         /*!< Falling trigger event configuration bit of line 10 */

+#define EXTI_FTSR1_TR11_Pos        (11U)

+#define EXTI_FTSR1_TR11_Msk        (0x1UL << EXTI_FTSR1_TR11_Pos)              /*!< 0x00000800 */

+#define EXTI_FTSR1_TR11            EXTI_FTSR1_TR11_Msk                         /*!< Falling trigger event configuration bit of line 11 */

+#define EXTI_FTSR1_TR12_Pos        (12U)

+#define EXTI_FTSR1_TR12_Msk        (0x1UL << EXTI_FTSR1_TR12_Pos)              /*!< 0x00001000 */

+#define EXTI_FTSR1_TR12            EXTI_FTSR1_TR12_Msk                         /*!< Falling trigger event configuration bit of line 12 */

+#define EXTI_FTSR1_TR13_Pos        (13U)

+#define EXTI_FTSR1_TR13_Msk        (0x1UL << EXTI_FTSR1_TR13_Pos)              /*!< 0x00002000 */

+#define EXTI_FTSR1_TR13            EXTI_FTSR1_TR13_Msk                         /*!< Falling trigger event configuration bit of line 13 */

+#define EXTI_FTSR1_TR14_Pos        (14U)

+#define EXTI_FTSR1_TR14_Msk        (0x1UL << EXTI_FTSR1_TR14_Pos)              /*!< 0x00004000 */

+#define EXTI_FTSR1_TR14            EXTI_FTSR1_TR14_Msk                         /*!< Falling trigger event configuration bit of line 14 */

+#define EXTI_FTSR1_TR15_Pos        (15U)

+#define EXTI_FTSR1_TR15_Msk        (0x1UL << EXTI_FTSR1_TR15_Pos)              /*!< 0x00008000 */

+#define EXTI_FTSR1_TR15            EXTI_FTSR1_TR15_Msk                         /*!< Falling trigger event configuration bit of line 15 */

+#define EXTI_FTSR1_TR16_Pos        (16U)

+#define EXTI_FTSR1_TR16_Msk        (0x1UL << EXTI_FTSR1_TR16_Pos)              /*!< 0x00010000 */

+#define EXTI_FTSR1_TR16            EXTI_FTSR1_TR16_Msk                         /*!< Falling trigger event configuration bit of line 16 */

+#define EXTI_FTSR1_TR17_Pos        (17U)

+#define EXTI_FTSR1_TR17_Msk        (0x1UL << EXTI_FTSR1_TR17_Pos)              /*!< 0x00020000 */

+#define EXTI_FTSR1_TR17            EXTI_FTSR1_TR17_Msk                         /*!< Falling trigger event configuration bit of line 17 */

+#define EXTI_FTSR1_TR18_Pos        (18U)

+#define EXTI_FTSR1_TR18_Msk        (0x1UL << EXTI_FTSR1_TR18_Pos)              /*!< 0x00040000 */

+#define EXTI_FTSR1_TR18            EXTI_FTSR1_TR18_Msk                         /*!< Falling trigger event configuration bit of line 18 */

+#define EXTI_FTSR1_TR19_Pos        (19U)

+#define EXTI_FTSR1_TR19_Msk        (0x1UL << EXTI_FTSR1_TR19_Pos)              /*!< 0x00080000 */

+#define EXTI_FTSR1_TR19            EXTI_FTSR1_TR19_Msk                         /*!< Falling trigger event configuration bit of line 19 */

+#define EXTI_FTSR1_TR20_Pos        (20U)

+#define EXTI_FTSR1_TR20_Msk        (0x1UL << EXTI_FTSR1_TR20_Pos)              /*!< 0x00100000 */

+#define EXTI_FTSR1_TR20            EXTI_FTSR1_TR20_Msk                         /*!< Falling trigger event configuration bit of line 20 */

+#define EXTI_FTSR1_TR21_Pos        (21U)

+#define EXTI_FTSR1_TR21_Msk        (0x1UL << EXTI_FTSR1_TR21_Pos)              /*!< 0x00200000 */

+#define EXTI_FTSR1_TR21            EXTI_FTSR1_TR21_Msk                         /*!< Falling trigger event configuration bit of line 21 */

+

+/******************  Bit definition for EXTI_SWIER1 register  ******************/

+#define EXTI_SWIER1_SWIER0_Pos     (0U)

+#define EXTI_SWIER1_SWIER0_Msk     (0x1UL << EXTI_SWIER1_SWIER0_Pos)           /*!< 0x00000001 */

+#define EXTI_SWIER1_SWIER0         EXTI_SWIER1_SWIER0_Msk                      /*!< Software Interrupt on line 0 */

+#define EXTI_SWIER1_SWIER1_Pos     (1U)

+#define EXTI_SWIER1_SWIER1_Msk     (0x1UL << EXTI_SWIER1_SWIER1_Pos)           /*!< 0x00000002 */

+#define EXTI_SWIER1_SWIER1         EXTI_SWIER1_SWIER1_Msk                      /*!< Software Interrupt on line 1 */

+#define EXTI_SWIER1_SWIER2_Pos     (2U)

+#define EXTI_SWIER1_SWIER2_Msk     (0x1UL << EXTI_SWIER1_SWIER2_Pos)           /*!< 0x00000004 */

+#define EXTI_SWIER1_SWIER2         EXTI_SWIER1_SWIER2_Msk                      /*!< Software Interrupt on line 2 */

+#define EXTI_SWIER1_SWIER3_Pos     (3U)

+#define EXTI_SWIER1_SWIER3_Msk     (0x1UL << EXTI_SWIER1_SWIER3_Pos)           /*!< 0x00000008 */

+#define EXTI_SWIER1_SWIER3         EXTI_SWIER1_SWIER3_Msk                      /*!< Software Interrupt on line 3 */

+#define EXTI_SWIER1_SWIER4_Pos     (4U)

+#define EXTI_SWIER1_SWIER4_Msk     (0x1UL << EXTI_SWIER1_SWIER4_Pos)           /*!< 0x00000010 */

+#define EXTI_SWIER1_SWIER4         EXTI_SWIER1_SWIER4_Msk                      /*!< Software Interrupt on line 4 */

+#define EXTI_SWIER1_SWIER5_Pos     (5U)

+#define EXTI_SWIER1_SWIER5_Msk     (0x1UL << EXTI_SWIER1_SWIER5_Pos)           /*!< 0x00000020 */

+#define EXTI_SWIER1_SWIER5         EXTI_SWIER1_SWIER5_Msk                      /*!< Software Interrupt on line 5 */

+#define EXTI_SWIER1_SWIER6_Pos     (6U)

+#define EXTI_SWIER1_SWIER6_Msk     (0x1UL << EXTI_SWIER1_SWIER6_Pos)           /*!< 0x00000040 */

+#define EXTI_SWIER1_SWIER6         EXTI_SWIER1_SWIER6_Msk                      /*!< Software Interrupt on line 6 */

+#define EXTI_SWIER1_SWIER7_Pos     (7U)

+#define EXTI_SWIER1_SWIER7_Msk     (0x1UL << EXTI_SWIER1_SWIER7_Pos)           /*!< 0x00000080 */

+#define EXTI_SWIER1_SWIER7         EXTI_SWIER1_SWIER7_Msk                      /*!< Software Interrupt on line 7 */

+#define EXTI_SWIER1_SWIER8_Pos     (8U)

+#define EXTI_SWIER1_SWIER8_Msk     (0x1UL << EXTI_SWIER1_SWIER8_Pos)           /*!< 0x00000100 */

+#define EXTI_SWIER1_SWIER8         EXTI_SWIER1_SWIER8_Msk                      /*!< Software Interrupt on line 8 */

+#define EXTI_SWIER1_SWIER9_Pos     (9U)

+#define EXTI_SWIER1_SWIER9_Msk     (0x1UL << EXTI_SWIER1_SWIER9_Pos)           /*!< 0x00000200 */

+#define EXTI_SWIER1_SWIER9         EXTI_SWIER1_SWIER9_Msk                      /*!< Software Interrupt on line 9 */

+#define EXTI_SWIER1_SWIER10_Pos    (10U)

+#define EXTI_SWIER1_SWIER10_Msk    (0x1UL << EXTI_SWIER1_SWIER10_Pos)          /*!< 0x00000400 */

+#define EXTI_SWIER1_SWIER10        EXTI_SWIER1_SWIER10_Msk                     /*!< Software Interrupt on line 10 */

+#define EXTI_SWIER1_SWIER11_Pos    (11U)

+#define EXTI_SWIER1_SWIER11_Msk    (0x1UL << EXTI_SWIER1_SWIER11_Pos)          /*!< 0x00000800 */

+#define EXTI_SWIER1_SWIER11        EXTI_SWIER1_SWIER11_Msk                     /*!< Software Interrupt on line 11 */

+#define EXTI_SWIER1_SWIER12_Pos    (12U)

+#define EXTI_SWIER1_SWIER12_Msk    (0x1UL << EXTI_SWIER1_SWIER12_Pos)          /*!< 0x00001000 */

+#define EXTI_SWIER1_SWIER12        EXTI_SWIER1_SWIER12_Msk                     /*!< Software Interrupt on line 12 */

+#define EXTI_SWIER1_SWIER13_Pos    (13U)

+#define EXTI_SWIER1_SWIER13_Msk    (0x1UL << EXTI_SWIER1_SWIER13_Pos)          /*!< 0x00002000 */

+#define EXTI_SWIER1_SWIER13        EXTI_SWIER1_SWIER13_Msk                     /*!< Software Interrupt on line 13 */

+#define EXTI_SWIER1_SWIER14_Pos    (14U)

+#define EXTI_SWIER1_SWIER14_Msk    (0x1UL << EXTI_SWIER1_SWIER14_Pos)          /*!< 0x00004000 */

+#define EXTI_SWIER1_SWIER14        EXTI_SWIER1_SWIER14_Msk                     /*!< Software Interrupt on line 14 */

+#define EXTI_SWIER1_SWIER15_Pos    (15U)

+#define EXTI_SWIER1_SWIER15_Msk    (0x1UL << EXTI_SWIER1_SWIER15_Pos)          /*!< 0x00008000 */

+#define EXTI_SWIER1_SWIER15        EXTI_SWIER1_SWIER15_Msk                     /*!< Software Interrupt on line 15 */

+#define EXTI_SWIER1_SWIER16_Pos    (16U)

+#define EXTI_SWIER1_SWIER16_Msk    (0x1UL << EXTI_SWIER1_SWIER16_Pos)          /*!< 0x00010000 */

+#define EXTI_SWIER1_SWIER16        EXTI_SWIER1_SWIER16_Msk                     /*!< Software Interrupt on line 16 */

+#define EXTI_SWIER1_SWIER17_Pos    (17U)

+#define EXTI_SWIER1_SWIER17_Msk    (0x1UL << EXTI_SWIER1_SWIER17_Pos)          /*!< 0x00020000 */

+#define EXTI_SWIER1_SWIER17        EXTI_SWIER1_SWIER17_Msk                     /*!< Software Interrupt on line 17 */

+#define EXTI_SWIER1_SWIER18_Pos    (18U)

+#define EXTI_SWIER1_SWIER18_Msk    (0x1UL << EXTI_SWIER1_SWIER18_Pos)          /*!< 0x00040000 */

+#define EXTI_SWIER1_SWIER18        EXTI_SWIER1_SWIER18_Msk                     /*!< Software Interrupt on line 18 */

+#define EXTI_SWIER1_SWIER19_Pos    (19U)

+#define EXTI_SWIER1_SWIER19_Msk    (0x1UL << EXTI_SWIER1_SWIER19_Pos)          /*!< 0x00080000 */

+#define EXTI_SWIER1_SWIER19        EXTI_SWIER1_SWIER19_Msk                     /*!< Software Interrupt on line 19 */

+#define EXTI_SWIER1_SWIER20_Pos    (20U)

+#define EXTI_SWIER1_SWIER20_Msk    (0x1UL << EXTI_SWIER1_SWIER20_Pos)          /*!< 0x00100000 */

+#define EXTI_SWIER1_SWIER20        EXTI_SWIER1_SWIER20_Msk                     /*!< Software Interrupt on line 20 */

+#define EXTI_SWIER1_SWIER21_Pos    (21U)

+#define EXTI_SWIER1_SWIER21_Msk    (0x1UL << EXTI_SWIER1_SWIER21_Pos)          /*!< 0x00200000 */

+#define EXTI_SWIER1_SWIER21        EXTI_SWIER1_SWIER21_Msk                     /*!< Software Interrupt on line 21 */

+

+/******************  Bit definition for EXTI_D3PMR1 register  ******************/

+#define EXTI_D3PMR1_MR0_Pos        (0U)

+#define EXTI_D3PMR1_MR0_Msk        (0x1UL << EXTI_D3PMR1_MR0_Pos)              /*!< 0x00000001 */

+#define EXTI_D3PMR1_MR0            EXTI_D3PMR1_MR0_Msk                         /*!< Pending Mask Event for line 0  */

+#define EXTI_D3PMR1_MR1_Pos        (1U)

+#define EXTI_D3PMR1_MR1_Msk        (0x1UL << EXTI_D3PMR1_MR1_Pos)              /*!< 0x00000002 */

+#define EXTI_D3PMR1_MR1            EXTI_D3PMR1_MR1_Msk                         /*!< Pending Mask Event for line 1  */

+#define EXTI_D3PMR1_MR2_Pos        (2U)

+#define EXTI_D3PMR1_MR2_Msk        (0x1UL << EXTI_D3PMR1_MR2_Pos)              /*!< 0x00000004 */

+#define EXTI_D3PMR1_MR2            EXTI_D3PMR1_MR2_Msk                         /*!< Pending Mask Event for line 2  */

+#define EXTI_D3PMR1_MR3_Pos        (3U)

+#define EXTI_D3PMR1_MR3_Msk        (0x1UL << EXTI_D3PMR1_MR3_Pos)              /*!< 0x00000008 */

+#define EXTI_D3PMR1_MR3            EXTI_D3PMR1_MR3_Msk                         /*!< Pending Mask Event for line 3  */

+#define EXTI_D3PMR1_MR4_Pos        (4U)

+#define EXTI_D3PMR1_MR4_Msk        (0x1UL << EXTI_D3PMR1_MR4_Pos)              /*!< 0x00000010 */

+#define EXTI_D3PMR1_MR4            EXTI_D3PMR1_MR4_Msk                         /*!< Pending Mask Event for line 4  */

+#define EXTI_D3PMR1_MR5_Pos        (5U)

+#define EXTI_D3PMR1_MR5_Msk        (0x1UL << EXTI_D3PMR1_MR5_Pos)              /*!< 0x00000020 */

+#define EXTI_D3PMR1_MR5            EXTI_D3PMR1_MR5_Msk                         /*!< Pending Mask Event for line 5  */

+#define EXTI_D3PMR1_MR6_Pos        (6U)

+#define EXTI_D3PMR1_MR6_Msk        (0x1UL << EXTI_D3PMR1_MR6_Pos)              /*!< 0x00000040 */

+#define EXTI_D3PMR1_MR6            EXTI_D3PMR1_MR6_Msk                         /*!< Pending Mask Event for line 6  */

+#define EXTI_D3PMR1_MR7_Pos        (7U)

+#define EXTI_D3PMR1_MR7_Msk        (0x1UL << EXTI_D3PMR1_MR7_Pos)              /*!< 0x00000080 */

+#define EXTI_D3PMR1_MR7            EXTI_D3PMR1_MR7_Msk                         /*!< Pending Mask Event for line 7  */

+#define EXTI_D3PMR1_MR8_Pos        (8U)

+#define EXTI_D3PMR1_MR8_Msk        (0x1UL << EXTI_D3PMR1_MR8_Pos)              /*!< 0x00000100 */

+#define EXTI_D3PMR1_MR8            EXTI_D3PMR1_MR8_Msk                         /*!< Pending Mask Event for line 8  */

+#define EXTI_D3PMR1_MR9_Pos        (9U)

+#define EXTI_D3PMR1_MR9_Msk        (0x1UL << EXTI_D3PMR1_MR9_Pos)              /*!< 0x00000200 */

+#define EXTI_D3PMR1_MR9            EXTI_D3PMR1_MR9_Msk                         /*!< Pending Mask Event for line 9  */

+#define EXTI_D3PMR1_MR10_Pos       (10U)

+#define EXTI_D3PMR1_MR10_Msk       (0x1UL << EXTI_D3PMR1_MR10_Pos)             /*!< 0x00000400 */

+#define EXTI_D3PMR1_MR10           EXTI_D3PMR1_MR10_Msk                        /*!< Pending Mask Event for line 10 */

+#define EXTI_D3PMR1_MR11_Pos       (11U)

+#define EXTI_D3PMR1_MR11_Msk       (0x1UL << EXTI_D3PMR1_MR11_Pos)             /*!< 0x00000800 */

+#define EXTI_D3PMR1_MR11           EXTI_D3PMR1_MR11_Msk                        /*!< Pending Mask Event for line 11 */

+#define EXTI_D3PMR1_MR12_Pos       (12U)

+#define EXTI_D3PMR1_MR12_Msk       (0x1UL << EXTI_D3PMR1_MR12_Pos)             /*!< 0x00001000 */

+#define EXTI_D3PMR1_MR12           EXTI_D3PMR1_MR12_Msk                        /*!< Pending Mask Event for line 12 */

+#define EXTI_D3PMR1_MR13_Pos       (13U)

+#define EXTI_D3PMR1_MR13_Msk       (0x1UL << EXTI_D3PMR1_MR13_Pos)             /*!< 0x00002000 */

+#define EXTI_D3PMR1_MR13           EXTI_D3PMR1_MR13_Msk                        /*!< Pending Mask Event for line 13 */

+#define EXTI_D3PMR1_MR14_Pos       (14U)

+#define EXTI_D3PMR1_MR14_Msk       (0x1UL << EXTI_D3PMR1_MR14_Pos)             /*!< 0x00004000 */

+#define EXTI_D3PMR1_MR14           EXTI_D3PMR1_MR14_Msk                        /*!< Pending Mask Event for line 14 */

+#define EXTI_D3PMR1_MR15_Pos       (15U)

+#define EXTI_D3PMR1_MR15_Msk       (0x1UL << EXTI_D3PMR1_MR15_Pos)             /*!< 0x00008000 */

+#define EXTI_D3PMR1_MR15           EXTI_D3PMR1_MR15_Msk                        /*!< Pending Mask Event for line 15 */

+#define EXTI_D3PMR1_MR19_Pos       (19U)

+#define EXTI_D3PMR1_MR19_Msk       (0x1UL << EXTI_D3PMR1_MR19_Pos)             /*!< 0x00080000 */

+#define EXTI_D3PMR1_MR19           EXTI_D3PMR1_MR19_Msk                        /*!< Pending Mask Event for line 19 */

+#define EXTI_D3PMR1_MR20_Pos       (20U)

+#define EXTI_D3PMR1_MR20_Msk       (0x1UL << EXTI_D3PMR1_MR20_Pos)             /*!< 0x00100000 */

+#define EXTI_D3PMR1_MR20           EXTI_D3PMR1_MR20_Msk                        /*!< Pending Mask Event for line 20 */

+#define EXTI_D3PMR1_MR21_Pos       (21U)

+#define EXTI_D3PMR1_MR21_Msk       (0x1UL << EXTI_D3PMR1_MR21_Pos)             /*!< 0x00200000 */

+#define EXTI_D3PMR1_MR21           EXTI_D3PMR1_MR21_Msk                        /*!< Pending Mask Event for line 21 */

+#define EXTI_D3PMR1_MR25_Pos       (24U)

+#define EXTI_D3PMR1_MR25_Msk       (0x1UL << EXTI_D3PMR1_MR25_Pos)             /*!< 0x01000000 */

+#define EXTI_D3PMR1_MR25           EXTI_D3PMR1_MR25_Msk                        /*!< Pending Mask Event for line 25 */

+

+/*******************  Bit definition for EXTI_D3PCR1L register  ****************/

+#define EXTI_D3PCR1L_PCS0_Pos       (0U)

+#define EXTI_D3PCR1L_PCS0_Msk       (0x3UL << EXTI_D3PCR1L_PCS0_Pos)           /*!< 0x00000003 */

+#define EXTI_D3PCR1L_PCS0           EXTI_D3PCR1L_PCS0_Msk                      /*!< D3 Pending request clear input signal selection on line 0 */

+#define EXTI_D3PCR1L_PCS1_Pos       (2U)

+#define EXTI_D3PCR1L_PCS1_Msk       (0x3UL << EXTI_D3PCR1L_PCS1_Pos)           /*!< 0x000000C0 */

+#define EXTI_D3PCR1L_PCS1           EXTI_D3PCR1L_PCS1_Msk                      /*!< D3 Pending request clear input signal selection on line 1 */

+#define EXTI_D3PCR1L_PCS2_Pos       (4U)

+#define EXTI_D3PCR1L_PCS2_Msk       (0x3UL << EXTI_D3PCR1L_PCS2_Pos)           /*!< 0x00000030 */

+#define EXTI_D3PCR1L_PCS2           EXTI_D3PCR1L_PCS2_Msk                      /*!< D3 Pending request clear input signal selection on line 2 */

+#define EXTI_D3PCR1L_PCS3_Pos       (6U)

+#define EXTI_D3PCR1L_PCS3_Msk       (0x3UL << EXTI_D3PCR1L_PCS3_Pos)           /*!< 0x000000C0 */

+#define EXTI_D3PCR1L_PCS3           EXTI_D3PCR1L_PCS3_Msk                      /*!< D3 Pending request clear input signal selection on line 3 */

+#define EXTI_D3PCR1L_PCS4_Pos       (8U)

+#define EXTI_D3PCR1L_PCS4_Msk       (0x3UL << EXTI_D3PCR1L_PCS4_Pos)           /*!< 0x00000300 */

+#define EXTI_D3PCR1L_PCS4           EXTI_D3PCR1L_PCS4_Msk                      /*!< D3 Pending request clear input signal selection on line 4 */

+#define EXTI_D3PCR1L_PCS5_Pos       (10U)

+#define EXTI_D3PCR1L_PCS5_Msk       (0x3UL << EXTI_D3PCR1L_PCS5_Pos)           /*!< 0x00000C00 */

+#define EXTI_D3PCR1L_PCS5           EXTI_D3PCR1L_PCS5_Msk                      /*!< D3 Pending request clear input signal selection on line 5 */

+#define EXTI_D3PCR1L_PCS6_Pos       (12U)

+#define EXTI_D3PCR1L_PCS6_Msk       (0x3UL << EXTI_D3PCR1L_PCS6_Pos)           /*!< 0x00003000 */

+#define EXTI_D3PCR1L_PCS6           EXTI_D3PCR1L_PCS6_Msk                      /*!< D3 Pending request clear input signal selection on line 6 */

+#define EXTI_D3PCR1L_PCS7_Pos       (14U)

+#define EXTI_D3PCR1L_PCS7_Msk       (0x3UL << EXTI_D3PCR1L_PCS7_Pos)           /*!< 0x0000C000 */

+#define EXTI_D3PCR1L_PCS7           EXTI_D3PCR1L_PCS7_Msk                      /*!< D3 Pending request clear input signal selection on line 7 */

+#define EXTI_D3PCR1L_PCS8_Pos       (16U)

+#define EXTI_D3PCR1L_PCS8_Msk       (0x3UL << EXTI_D3PCR1L_PCS8_Pos)           /*!< 0x00030000 */

+#define EXTI_D3PCR1L_PCS8           EXTI_D3PCR1L_PCS8_Msk                      /*!< D3 Pending request clear input signal selection on line 8 */

+#define EXTI_D3PCR1L_PCS9_Pos       (18U)

+#define EXTI_D3PCR1L_PCS9_Msk       (0x3UL << EXTI_D3PCR1L_PCS9_Pos)           /*!< 0x000C0000 */

+#define EXTI_D3PCR1L_PCS9           EXTI_D3PCR1L_PCS9_Msk                      /*!< D3 Pending request clear input signal selection on line 9 */

+#define EXTI_D3PCR1L_PCS10_Pos      (20U)

+#define EXTI_D3PCR1L_PCS10_Msk      (0x3UL << EXTI_D3PCR1L_PCS10_Pos)          /*!< 0x00300000 */

+#define EXTI_D3PCR1L_PCS10          EXTI_D3PCR1L_PCS10_Msk                     /*!< D3 Pending request clear input signal selection on line 10*/

+#define EXTI_D3PCR1L_PCS11_Pos      (22U)

+#define EXTI_D3PCR1L_PCS11_Msk      (0x3UL << EXTI_D3PCR1L_PCS11_Pos)          /*!< 0x00C00000 */

+#define EXTI_D3PCR1L_PCS11          EXTI_D3PCR1L_PCS11_Msk                     /*!< D3 Pending request clear input signal selection on line 11*/

+#define EXTI_D3PCR1L_PCS12_Pos      (24U)

+#define EXTI_D3PCR1L_PCS12_Msk      (0x3UL << EXTI_D3PCR1L_PCS12_Pos)          /*!< 0x03000000 */

+#define EXTI_D3PCR1L_PCS12          EXTI_D3PCR1L_PCS12_Msk                     /*!< D3 Pending request clear input signal selection on line 12*/

+#define EXTI_D3PCR1L_PCS13_Pos      (26U)

+#define EXTI_D3PCR1L_PCS13_Msk      (0x3UL << EXTI_D3PCR1L_PCS13_Pos)          /*!< 0x0C000000 */

+#define EXTI_D3PCR1L_PCS13          EXTI_D3PCR1L_PCS13_Msk                     /*!< D3 Pending request clear input signal selection on line 13*/

+#define EXTI_D3PCR1L_PCS14_Pos      (28U)

+#define EXTI_D3PCR1L_PCS14_Msk      (0x3UL << EXTI_D3PCR1L_PCS14_Pos)          /*!< 0x30000000 */

+#define EXTI_D3PCR1L_PCS14          EXTI_D3PCR1L_PCS14_Msk                     /*!< D3 Pending request clear input signal selection on line 14*/

+#define EXTI_D3PCR1L_PCS15_Pos      (30U)

+#define EXTI_D3PCR1L_PCS15_Msk      (0x3UL << EXTI_D3PCR1L_PCS15_Pos)          /*!< 0xC0000000 */

+#define EXTI_D3PCR1L_PCS15          EXTI_D3PCR1L_PCS15_Msk                     /*!< D3 Pending request clear input signal selection on line 15*/

+

+/*******************  Bit definition for EXTI_D3PCR1H register  ****************/

+#define EXTI_D3PCR1H_PCS19_Pos       (6U)

+#define EXTI_D3PCR1H_PCS19_Msk       (0x3UL << EXTI_D3PCR1H_PCS19_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR1H_PCS19           EXTI_D3PCR1H_PCS19_Msk                    /*!< D3 Pending request clear input signal selection on line 19 */

+#define EXTI_D3PCR1H_PCS20_Pos       (8U)

+#define EXTI_D3PCR1H_PCS20_Msk       (0x3UL << EXTI_D3PCR1H_PCS20_Pos)         /*!< 0x00000300 */

+#define EXTI_D3PCR1H_PCS20           EXTI_D3PCR1H_PCS20_Msk                    /*!< D3 Pending request clear input signal selection on line 20 */

+#define EXTI_D3PCR1H_PCS21_Pos       (10U)

+#define EXTI_D3PCR1H_PCS21_Msk       (0x3UL << EXTI_D3PCR1H_PCS21_Pos)         /*!< 0x00000C00 */

+#define EXTI_D3PCR1H_PCS21           EXTI_D3PCR1H_PCS21_Msk                    /*!< D3 Pending request clear input signal selection on line 21 */

+#define EXTI_D3PCR1H_PCS25_Pos       (18U)

+#define EXTI_D3PCR1H_PCS25_Msk       (0x3UL << EXTI_D3PCR1H_PCS25_Pos)         /*!< 0x000C0000 */

+#define EXTI_D3PCR1H_PCS25           EXTI_D3PCR1H_PCS25_Msk                    /*!< D3 Pending request clear input signal selection on line 25 */

+

+/******************  Bit definition for EXTI_RTSR2 register  *******************/

+#define EXTI_RTSR2_TR_Pos          (17U)

+#define EXTI_RTSR2_TR_Msk          (0x5UL << EXTI_RTSR2_TR_Pos)                /*!< 0x000A0000 */

+#define EXTI_RTSR2_TR              EXTI_RTSR2_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR2_TR49_Pos        (17U)

+#define EXTI_RTSR2_TR49_Msk        (0x1UL << EXTI_RTSR2_TR49_Pos)              /*!< 0x00020000 */

+#define EXTI_RTSR2_TR49            EXTI_RTSR2_TR49_Msk                         /*!< Rising trigger event configuration bit of line 49 */

+#define EXTI_RTSR2_TR51_Pos        (19U)

+#define EXTI_RTSR2_TR51_Msk        (0x1UL << EXTI_RTSR2_TR51_Pos)              /*!< 0x00080000 */

+#define EXTI_RTSR2_TR51            EXTI_RTSR2_TR51_Msk                         /*!< Rising trigger event configuration bit of line 51 */

+

+/******************  Bit definition for EXTI_FTSR2 register  *******************/

+#define EXTI_FTSR2_TR_Pos          (17U)

+#define EXTI_FTSR2_TR_Msk          (0x5UL << EXTI_FTSR2_TR_Pos)                /*!< 0x000A0000 */

+#define EXTI_FTSR2_TR              EXTI_FTSR2_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR2_TR49_Pos        (17U)

+#define EXTI_FTSR2_TR49_Msk        (0x1UL << EXTI_FTSR2_TR49_Pos)              /*!< 0x00020000 */

+#define EXTI_FTSR2_TR49            EXTI_FTSR2_TR49_Msk                         /*!< Falling trigger event configuration bit of line 49 */

+#define EXTI_FTSR2_TR51_Pos        (19U)

+#define EXTI_FTSR2_TR51_Msk        (0x1UL << EXTI_FTSR2_TR51_Pos)              /*!< 0x00080000 */

+#define EXTI_FTSR2_TR51            EXTI_FTSR2_TR51_Msk                         /*!< Falling trigger event configuration bit of line 51 */

+

+/******************  Bit definition for EXTI_SWIER2 register  ******************/

+#define EXTI_SWIER2_SWIER49_Pos    (17U)

+#define EXTI_SWIER2_SWIER49_Msk    (0x1UL << EXTI_SWIER2_SWIER49_Pos)          /*!< 0x00020000 */

+#define EXTI_SWIER2_SWIER49        EXTI_SWIER2_SWIER49_Msk                     /*!< Software Interrupt on line 49 */

+#define EXTI_SWIER2_SWIER51_Pos    (19U)

+#define EXTI_SWIER2_SWIER51_Msk    (0x1UL << EXTI_SWIER2_SWIER51_Pos)          /*!< 0x00080000 */

+#define EXTI_SWIER2_SWIER51        EXTI_SWIER2_SWIER51_Msk                     /*!< Software Interrupt on line 51 */

+

+/******************  Bit definition for EXTI_D3PMR2 register  ******************/

+#define EXTI_D3PMR2_MR34_Pos       (2U)

+#define EXTI_D3PMR2_MR34_Msk       (0x1UL << EXTI_D3PMR2_MR34_Pos)             /*!< 0x00000004 */

+#define EXTI_D3PMR2_MR34           EXTI_D3PMR2_MR34_Msk                        /*!< Pending Mask Event for line 34  */

+#define EXTI_D3PMR2_MR35_Pos       (3U)

+#define EXTI_D3PMR2_MR35_Msk       (0x1UL << EXTI_D3PMR2_MR35_Pos)             /*!< 0x00000008 */

+#define EXTI_D3PMR2_MR35           EXTI_D3PMR2_MR35_Msk                        /*!< Pending Mask Event for line 35  */

+#define EXTI_D3PMR2_MR41_Pos       (9U)

+#define EXTI_D3PMR2_MR41_Msk       (0x1UL << EXTI_D3PMR2_MR41_Pos)             /*!< 0x00000200 */

+#define EXTI_D3PMR2_MR41           EXTI_D3PMR2_MR41_Msk                        /*!< Pending Mask Event for line 41  */

+#define EXTI_D3PMR2_MR48_Pos       (16U)

+#define EXTI_D3PMR2_MR48_Msk       (0x1UL << EXTI_D3PMR2_MR48_Pos)             /*!< 0x00010000 */

+#define EXTI_D3PMR2_MR48           EXTI_D3PMR2_MR48_Msk                        /*!< Pending Mask Event for line 48  */

+#define EXTI_D3PMR2_MR49_Pos       (17U)

+#define EXTI_D3PMR2_MR49_Msk       (0x1UL << EXTI_D3PMR2_MR49_Pos)             /*!< 0x00020000 */

+#define EXTI_D3PMR2_MR49           EXTI_D3PMR2_MR49_Msk                        /*!< Pending Mask Event for line 49  */

+#define EXTI_D3PMR2_MR50_Pos       (18U)

+#define EXTI_D3PMR2_MR50_Msk       (0x1UL << EXTI_D3PMR2_MR50_Pos)             /*!< 0x00040000 */

+#define EXTI_D3PMR2_MR50           EXTI_D3PMR2_MR50_Msk                        /*!< Pending Mask Event for line 50  */

+#define EXTI_D3PMR2_MR51_Pos       (19U)

+#define EXTI_D3PMR2_MR51_Msk       (0x1UL << EXTI_D3PMR2_MR51_Pos)             /*!< 0x00080000 */

+#define EXTI_D3PMR2_MR51           EXTI_D3PMR2_MR51_Msk                        /*!< Pending Mask Event for line 51  */

+#define EXTI_D3PMR2_MR52_Pos       (20U)

+#define EXTI_D3PMR2_MR52_Msk       (0x1UL << EXTI_D3PMR2_MR52_Pos)             /*!< 0x00100000 */

+#define EXTI_D3PMR2_MR52           EXTI_D3PMR2_MR52_Msk                        /*!< Pending Mask Event for line 52  */

+#define EXTI_D3PMR2_MR53_Pos       (21U)

+#define EXTI_D3PMR2_MR53_Msk       (0x1UL << EXTI_D3PMR2_MR53_Pos)             /*!< 0x00200000 */

+#define EXTI_D3PMR2_MR53           EXTI_D3PMR2_MR53_Msk                        /*!< Pending Mask Event for line 53  */

+/*******************  Bit definition for EXTI_D3PCR2L register  ****************/

+#define EXTI_D3PCR2L_PCS34_Pos       (4U)

+#define EXTI_D3PCR2L_PCS34_Msk       (0x3UL << EXTI_D3PCR2L_PCS34_Pos)         /*!< 0x00000030 */

+#define EXTI_D3PCR2L_PCS34           EXTI_D3PCR2L_PCS34_Msk                    /*!< D3 Pending request clear input signal selection on line 34 */

+#define EXTI_D3PCR2L_PCS35_Pos       (6U)

+#define EXTI_D3PCR2L_PCS35_Msk       (0x3UL << EXTI_D3PCR2L_PCS35_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR2L_PCS35           EXTI_D3PCR2L_PCS35_Msk                    /*!< D3 Pending request clear input signal selection on line 35 */

+#define EXTI_D3PCR2L_PCS41_Pos       (18U)

+#define EXTI_D3PCR2L_PCS41_Msk       (0x3UL << EXTI_D3PCR2L_PCS41_Pos)         /*!< 0x000C0000 */

+#define EXTI_D3PCR2L_PCS41           EXTI_D3PCR2L_PCS41_Msk                    /*!< D3 Pending request clear input signal selection on line 41 */

+

+

+/*******************  Bit definition for EXTI_D3PCR2H register  ****************/

+#define EXTI_D3PCR2H_PCS48_Pos       (0U)

+#define EXTI_D3PCR2H_PCS48_Msk       (0x3UL << EXTI_D3PCR2H_PCS48_Pos)         /*!< 0x00000003 */

+#define EXTI_D3PCR2H_PCS48           EXTI_D3PCR2H_PCS48_Msk                    /*!< D3 Pending request clear input signal selection on line 48 */

+#define EXTI_D3PCR2H_PCS49_Pos       (2U)

+#define EXTI_D3PCR2H_PCS49_Msk       (0x3UL << EXTI_D3PCR2H_PCS49_Pos)         /*!< 0x0000000C */

+#define EXTI_D3PCR2H_PCS49           EXTI_D3PCR2H_PCS49_Msk                    /*!< D3 Pending request clear input signal selection on line 49 */

+#define EXTI_D3PCR2H_PCS50_Pos       (4U)

+#define EXTI_D3PCR2H_PCS50_Msk       (0x3UL << EXTI_D3PCR2H_PCS50_Pos)         /*!< 0x00000030 */

+#define EXTI_D3PCR2H_PCS50           EXTI_D3PCR2H_PCS50_Msk                    /*!< D3 Pending request clear input signal selection on line 50 */

+#define EXTI_D3PCR2H_PCS51_Pos       (6U)

+#define EXTI_D3PCR2H_PCS51_Msk       (0x3UL << EXTI_D3PCR2H_PCS51_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR2H_PCS51           EXTI_D3PCR2H_PCS51_Msk                    /*!< D3 Pending request clear input signal selection on line 51 */

+#define EXTI_D3PCR2H_PCS52_Pos       (8U)

+#define EXTI_D3PCR2H_PCS52_Msk       (0x3UL << EXTI_D3PCR2H_PCS52_Pos)         /*!< 0x00000300 */

+#define EXTI_D3PCR2H_PCS52           EXTI_D3PCR2H_PCS52_Msk                    /*!< D3 Pending request clear input signal selection on line 52 */

+#define EXTI_D3PCR2H_PCS53_Pos       (10U)

+#define EXTI_D3PCR2H_PCS53_Msk       (0x3UL << EXTI_D3PCR2H_PCS53_Pos)         /*!< 0x00000C00 */

+#define EXTI_D3PCR2H_PCS53           EXTI_D3PCR2H_PCS53_Msk                    /*!< D3 Pending request clear input signal selection on line 53 */

+/******************  Bit definition for EXTI_RTSR3 register  *******************/

+#define EXTI_RTSR3_TR_Pos          (18U)

+#define EXTI_RTSR3_TR_Msk          (0x1DUL << EXTI_RTSR3_TR_Pos)               /*!< 0x00740000 */

+#define EXTI_RTSR3_TR              EXTI_RTSR3_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR3_TR82_Pos        (18U)

+#define EXTI_RTSR3_TR82_Msk        (0x1UL << EXTI_RTSR3_TR82_Pos)              /*!< 0x00040000 */

+#define EXTI_RTSR3_TR82            EXTI_RTSR3_TR82_Msk                         /*!< Rising trigger event configuration bit of line 82 */

+#define EXTI_RTSR3_TR84_Pos        (20U)

+#define EXTI_RTSR3_TR84_Msk        (0x1UL << EXTI_RTSR3_TR84_Pos)              /*!< 0x00100000 */

+#define EXTI_RTSR3_TR84            EXTI_RTSR3_TR84_Msk                         /*!< Rising trigger event configuration bit of line 84 */

+#define EXTI_RTSR3_TR85_Pos        (21U)

+#define EXTI_RTSR3_TR85_Msk        (0x1UL << EXTI_RTSR3_TR85_Pos)              /*!< 0x00200000 */

+#define EXTI_RTSR3_TR85            EXTI_RTSR3_TR85_Msk                         /*!< Rising trigger event configuration bit of line 85 */

+#define EXTI_RTSR3_TR86_Pos        (22U)

+#define EXTI_RTSR3_TR86_Msk        (0x1UL << EXTI_RTSR3_TR86_Pos)              /*!< 0x00400000 */

+#define EXTI_RTSR3_TR86            EXTI_RTSR3_TR86_Msk                         /*!< Rising trigger event configuration bit of line 86 */

+

+/******************  Bit definition for EXTI_FTSR3 register  *******************/

+#define EXTI_FTSR3_TR_Pos          (18U)

+#define EXTI_FTSR3_TR_Msk          (0x1DUL << EXTI_FTSR3_TR_Pos)               /*!< 0x00740000 */

+#define EXTI_FTSR3_TR              EXTI_FTSR3_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR3_TR82_Pos        (18U)

+#define EXTI_FTSR3_TR82_Msk        (0x1UL << EXTI_FTSR3_TR82_Pos)              /*!< 0x00040000 */

+#define EXTI_FTSR3_TR82            EXTI_FTSR3_TR82_Msk                         /*!< Falling trigger event configuration bit of line 82 */

+#define EXTI_FTSR3_TR84_Pos        (20U)

+#define EXTI_FTSR3_TR84_Msk        (0x1UL << EXTI_FTSR3_TR84_Pos)              /*!< 0x00100000 */

+#define EXTI_FTSR3_TR84            EXTI_FTSR3_TR84_Msk                         /*!< Falling trigger event configuration bit of line 84 */

+#define EXTI_FTSR3_TR85_Pos        (21U)

+#define EXTI_FTSR3_TR85_Msk        (0x1UL << EXTI_FTSR3_TR85_Pos)              /*!< 0x00200000 */

+#define EXTI_FTSR3_TR85            EXTI_FTSR3_TR85_Msk                         /*!< Falling trigger event configuration bit of line 85 */

+#define EXTI_FTSR3_TR86_Pos        (22U)

+#define EXTI_FTSR3_TR86_Msk        (0x1UL << EXTI_FTSR3_TR86_Pos)              /*!< 0x00400000 */

+#define EXTI_FTSR3_TR86            EXTI_FTSR3_TR86_Msk                         /*!< Falling trigger event configuration bit of line 86 */

+

+/******************  Bit definition for EXTI_SWIER3 register  ******************/

+#define EXTI_SWIER3_SWI_Pos        (18U)

+#define EXTI_SWIER3_SWI_Msk        (0x1DUL << EXTI_SWIER3_SWI_Pos)             /*!< 0x00740000 */

+#define EXTI_SWIER3_SWI            EXTI_SWIER3_SWI_Msk                         /*!< Software Interrupt event bit */

+#define EXTI_SWIER3_SWIER82_Pos    (18U)

+#define EXTI_SWIER3_SWIER82_Msk    (0x1UL << EXTI_SWIER3_SWIER82_Pos)          /*!< 0x00040000 */

+#define EXTI_SWIER3_SWIER82        EXTI_SWIER3_SWIER82_Msk                     /*!< Software Interrupt on line 82 */

+#define EXTI_SWIER3_SWIER84_Pos    (20U)

+#define EXTI_SWIER3_SWIER84_Msk    (0x1UL << EXTI_SWIER3_SWIER84_Pos)          /*!< 0x00100000 */

+#define EXTI_SWIER3_SWIER84        EXTI_SWIER3_SWIER84_Msk                     /*!< Software Interrupt on line 84 */

+#define EXTI_SWIER3_SWIER85_Pos    (21U)

+#define EXTI_SWIER3_SWIER85_Msk    (0x1UL << EXTI_SWIER3_SWIER85_Pos)          /*!< 0x00200000 */

+#define EXTI_SWIER3_SWIER85        EXTI_SWIER3_SWIER85_Msk                     /*!< Software Interrupt on line 85 */

+#define EXTI_SWIER3_SWIER86_Pos    (22U)

+#define EXTI_SWIER3_SWIER86_Msk    (0x1UL << EXTI_SWIER3_SWIER86_Pos)          /*!< 0x00400000 */

+#define EXTI_SWIER3_SWIER86        EXTI_SWIER3_SWIER86_Msk                     /*!< Software Interrupt on line 86 */

+

+/*******************  Bit definition for EXTI_IMR1 register  *******************/

+#define EXTI_IMR1_IM_Pos           (0U)

+#define EXTI_IMR1_IM_Msk           (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)          /*!< 0xFFFFFFFF */

+#define EXTI_IMR1_IM               EXTI_IMR1_IM_Msk                            /*!< Interrupt Mask */

+#define EXTI_IMR1_IM0_Pos          (0U)

+#define EXTI_IMR1_IM0_Msk          (0x1UL << EXTI_IMR1_IM0_Pos)                /*!< 0x00000001 */

+#define EXTI_IMR1_IM0              EXTI_IMR1_IM0_Msk                           /*!< Interrupt Mask on line 0 */

+#define EXTI_IMR1_IM1_Pos          (1U)

+#define EXTI_IMR1_IM1_Msk          (0x1UL << EXTI_IMR1_IM1_Pos)                /*!< 0x00000002 */

+#define EXTI_IMR1_IM1              EXTI_IMR1_IM1_Msk                           /*!< Interrupt Mask on line 1 */

+#define EXTI_IMR1_IM2_Pos          (2U)

+#define EXTI_IMR1_IM2_Msk          (0x1UL << EXTI_IMR1_IM2_Pos)                /*!< 0x00000004 */

+#define EXTI_IMR1_IM2              EXTI_IMR1_IM2_Msk                           /*!< Interrupt Mask on line 2 */

+#define EXTI_IMR1_IM3_Pos          (3U)

+#define EXTI_IMR1_IM3_Msk          (0x1UL << EXTI_IMR1_IM3_Pos)                /*!< 0x00000008 */

+#define EXTI_IMR1_IM3              EXTI_IMR1_IM3_Msk                           /*!< Interrupt Mask on line 3 */

+#define EXTI_IMR1_IM4_Pos          (4U)

+#define EXTI_IMR1_IM4_Msk          (0x1UL << EXTI_IMR1_IM4_Pos)                /*!< 0x00000010 */

+#define EXTI_IMR1_IM4              EXTI_IMR1_IM4_Msk                           /*!< Interrupt Mask on line 4 */

+#define EXTI_IMR1_IM5_Pos          (5U)

+#define EXTI_IMR1_IM5_Msk          (0x1UL << EXTI_IMR1_IM5_Pos)                /*!< 0x00000020 */

+#define EXTI_IMR1_IM5              EXTI_IMR1_IM5_Msk                           /*!< Interrupt Mask on line 5 */

+#define EXTI_IMR1_IM6_Pos          (6U)

+#define EXTI_IMR1_IM6_Msk          (0x1UL << EXTI_IMR1_IM6_Pos)                /*!< 0x00000040 */

+#define EXTI_IMR1_IM6              EXTI_IMR1_IM6_Msk                           /*!< Interrupt Mask on line 6 */

+#define EXTI_IMR1_IM7_Pos          (7U)

+#define EXTI_IMR1_IM7_Msk          (0x1UL << EXTI_IMR1_IM7_Pos)                /*!< 0x00000080 */

+#define EXTI_IMR1_IM7              EXTI_IMR1_IM7_Msk                           /*!< Interrupt Mask on line 7 */

+#define EXTI_IMR1_IM8_Pos          (8U)

+#define EXTI_IMR1_IM8_Msk          (0x1UL << EXTI_IMR1_IM8_Pos)                /*!< 0x00000100 */

+#define EXTI_IMR1_IM8              EXTI_IMR1_IM8_Msk                           /*!< Interrupt Mask on line 8 */

+#define EXTI_IMR1_IM9_Pos          (9U)

+#define EXTI_IMR1_IM9_Msk          (0x1UL << EXTI_IMR1_IM9_Pos)                /*!< 0x00000200 */

+#define EXTI_IMR1_IM9              EXTI_IMR1_IM9_Msk                           /*!< Interrupt Mask on line 9 */

+#define EXTI_IMR1_IM10_Pos         (10U)

+#define EXTI_IMR1_IM10_Msk         (0x1UL << EXTI_IMR1_IM10_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR1_IM10             EXTI_IMR1_IM10_Msk                          /*!< Interrupt Mask on line 10 */

+#define EXTI_IMR1_IM11_Pos         (11U)

+#define EXTI_IMR1_IM11_Msk         (0x1UL << EXTI_IMR1_IM11_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR1_IM11             EXTI_IMR1_IM11_Msk                          /*!< Interrupt Mask on line 11 */

+#define EXTI_IMR1_IM12_Pos         (12U)

+#define EXTI_IMR1_IM12_Msk         (0x1UL << EXTI_IMR1_IM12_Pos)               /*!< 0x00001000 */

+#define EXTI_IMR1_IM12             EXTI_IMR1_IM12_Msk                          /*!< Interrupt Mask on line 12 */

+#define EXTI_IMR1_IM13_Pos         (13U)

+#define EXTI_IMR1_IM13_Msk         (0x1UL << EXTI_IMR1_IM13_Pos)               /*!< 0x00002000 */

+#define EXTI_IMR1_IM13             EXTI_IMR1_IM13_Msk                          /*!< Interrupt Mask on line 13 */

+#define EXTI_IMR1_IM14_Pos         (14U)

+#define EXTI_IMR1_IM14_Msk         (0x1UL << EXTI_IMR1_IM14_Pos)               /*!< 0x00004000 */

+#define EXTI_IMR1_IM14             EXTI_IMR1_IM14_Msk                          /*!< Interrupt Mask on line 14 */

+#define EXTI_IMR1_IM15_Pos         (15U)

+#define EXTI_IMR1_IM15_Msk         (0x1UL << EXTI_IMR1_IM15_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR1_IM15             EXTI_IMR1_IM15_Msk                          /*!< Interrupt Mask on line 15 */

+#define EXTI_IMR1_IM16_Pos         (16U)

+#define EXTI_IMR1_IM16_Msk         (0x1UL << EXTI_IMR1_IM16_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR1_IM16             EXTI_IMR1_IM16_Msk                          /*!< Interrupt Mask on line 16 */

+#define EXTI_IMR1_IM17_Pos         (17U)

+#define EXTI_IMR1_IM17_Msk         (0x1UL << EXTI_IMR1_IM17_Pos)               /*!< 0x00020000 */

+#define EXTI_IMR1_IM17             EXTI_IMR1_IM17_Msk                          /*!< Interrupt Mask on line 17 */

+#define EXTI_IMR1_IM18_Pos         (18U)

+#define EXTI_IMR1_IM18_Msk         (0x1UL << EXTI_IMR1_IM18_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR1_IM18             EXTI_IMR1_IM18_Msk                          /*!< Interrupt Mask on line 18 */

+#define EXTI_IMR1_IM19_Pos         (19U)

+#define EXTI_IMR1_IM19_Msk         (0x1UL << EXTI_IMR1_IM19_Pos)               /*!< 0x00080000 */

+#define EXTI_IMR1_IM19             EXTI_IMR1_IM19_Msk                          /*!< Interrupt Mask on line 19 */

+#define EXTI_IMR1_IM20_Pos         (20U)

+#define EXTI_IMR1_IM20_Msk         (0x1UL << EXTI_IMR1_IM20_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR1_IM20             EXTI_IMR1_IM20_Msk                          /*!< Interrupt Mask on line 20 */

+#define EXTI_IMR1_IM21_Pos         (21U)

+#define EXTI_IMR1_IM21_Msk         (0x1UL << EXTI_IMR1_IM21_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR1_IM21             EXTI_IMR1_IM21_Msk                          /*!< Interrupt Mask on line 21 */

+#define EXTI_IMR1_IM22_Pos         (22U)

+#define EXTI_IMR1_IM22_Msk         (0x1UL << EXTI_IMR1_IM22_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR1_IM22             EXTI_IMR1_IM22_Msk                          /*!< Interrupt Mask on line 22 */

+#define EXTI_IMR1_IM23_Pos         (23U)

+#define EXTI_IMR1_IM23_Msk         (0x1UL << EXTI_IMR1_IM23_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR1_IM23             EXTI_IMR1_IM23_Msk                          /*!< Interrupt Mask on line 23 */

+#define EXTI_IMR1_IM24_Pos         (24U)

+#define EXTI_IMR1_IM24_Msk         (0x1UL << EXTI_IMR1_IM24_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR1_IM24             EXTI_IMR1_IM24_Msk                          /*!< Interrupt Mask on line 24 */

+#define EXTI_IMR1_IM25_Pos         (25U)

+#define EXTI_IMR1_IM25_Msk         (0x1UL << EXTI_IMR1_IM25_Pos)               /*!< 0x02000000 */

+#define EXTI_IMR1_IM25             EXTI_IMR1_IM25_Msk                          /*!< Interrupt Mask on line 25 */

+#define EXTI_IMR1_IM26_Pos         (26U)

+#define EXTI_IMR1_IM26_Msk         (0x1UL << EXTI_IMR1_IM26_Pos)               /*!< 0x04000000 */

+#define EXTI_IMR1_IM26             EXTI_IMR1_IM26_Msk                          /*!< Interrupt Mask on line 26 */

+#define EXTI_IMR1_IM27_Pos         (27U)

+#define EXTI_IMR1_IM27_Msk         (0x1UL << EXTI_IMR1_IM27_Pos)               /*!< 0x08000000 */

+#define EXTI_IMR1_IM27             EXTI_IMR1_IM27_Msk                          /*!< Interrupt Mask on line 27 */

+#define EXTI_IMR1_IM28_Pos         (28U)

+#define EXTI_IMR1_IM28_Msk         (0x1UL << EXTI_IMR1_IM28_Pos)               /*!< 0x10000000 */

+#define EXTI_IMR1_IM28             EXTI_IMR1_IM28_Msk                          /*!< Interrupt Mask on line 28 */

+#define EXTI_IMR1_IM29_Pos         (29U)

+#define EXTI_IMR1_IM29_Msk         (0x1UL << EXTI_IMR1_IM29_Pos)               /*!< 0x20000000 */

+#define EXTI_IMR1_IM29             EXTI_IMR1_IM29_Msk                          /*!< Interrupt Mask on line 29 */

+#define EXTI_IMR1_IM30_Pos         (30U)

+#define EXTI_IMR1_IM30_Msk         (0x1UL << EXTI_IMR1_IM30_Pos)               /*!< 0x40000000 */

+#define EXTI_IMR1_IM30             EXTI_IMR1_IM30_Msk                          /*!< Interrupt Mask on line 30 */

+#define EXTI_IMR1_IM31_Pos         (31U)

+#define EXTI_IMR1_IM31_Msk         (0x1UL << EXTI_IMR1_IM31_Pos)               /*!< 0x80000000 */

+#define EXTI_IMR1_IM31             EXTI_IMR1_IM31_Msk                          /*!< Interrupt Mask on line 31 */

+

+/*******************  Bit definition for EXTI_EMR1 register  *******************/

+#define EXTI_EMR1_EM_Pos           (0U)

+#define EXTI_EMR1_EM_Msk           (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)          /*!< 0xFFFFFFFF */

+#define EXTI_EMR1_EM               EXTI_EMR1_EM_Msk                            /*!< Event Mask */

+#define EXTI_EMR1_EM0_Pos          (0U)

+#define EXTI_EMR1_EM0_Msk          (0x1UL << EXTI_EMR1_EM0_Pos)                /*!< 0x00000001 */

+#define EXTI_EMR1_EM0              EXTI_EMR1_EM0_Msk                           /*!< Event Mask on line 0 */

+#define EXTI_EMR1_EM1_Pos          (1U)

+#define EXTI_EMR1_EM1_Msk          (0x1UL << EXTI_EMR1_EM1_Pos)                /*!< 0x00000002 */

+#define EXTI_EMR1_EM1              EXTI_EMR1_EM1_Msk                           /*!< Event Mask on line 1 */

+#define EXTI_EMR1_EM2_Pos          (2U)

+#define EXTI_EMR1_EM2_Msk          (0x1UL << EXTI_EMR1_EM2_Pos)                /*!< 0x00000004 */

+#define EXTI_EMR1_EM2              EXTI_EMR1_EM2_Msk                           /*!< Event Mask on line 2 */

+#define EXTI_EMR1_EM3_Pos          (3U)

+#define EXTI_EMR1_EM3_Msk          (0x1UL << EXTI_EMR1_EM3_Pos)                /*!< 0x00000008 */

+#define EXTI_EMR1_EM3              EXTI_EMR1_EM3_Msk                           /*!< Event Mask on line 3 */

+#define EXTI_EMR1_EM4_Pos          (4U)

+#define EXTI_EMR1_EM4_Msk          (0x1UL << EXTI_EMR1_EM4_Pos)                /*!< 0x00000010 */

+#define EXTI_EMR1_EM4              EXTI_EMR1_EM4_Msk                           /*!< Event Mask on line 4 */

+#define EXTI_EMR1_EM5_Pos          (5U)

+#define EXTI_EMR1_EM5_Msk          (0x1UL << EXTI_EMR1_EM5_Pos)                /*!< 0x00000020 */

+#define EXTI_EMR1_EM5              EXTI_EMR1_EM5_Msk                           /*!< Event Mask on line 5 */

+#define EXTI_EMR1_EM6_Pos          (6U)

+#define EXTI_EMR1_EM6_Msk          (0x1UL << EXTI_EMR1_EM6_Pos)                /*!< 0x00000040 */

+#define EXTI_EMR1_EM6              EXTI_EMR1_EM6_Msk                           /*!< Event Mask on line 6 */

+#define EXTI_EMR1_EM7_Pos          (7U)

+#define EXTI_EMR1_EM7_Msk          (0x1UL << EXTI_EMR1_EM7_Pos)                /*!< 0x00000080 */

+#define EXTI_EMR1_EM7              EXTI_EMR1_EM7_Msk                           /*!< Event Mask on line 7 */

+#define EXTI_EMR1_EM8_Pos          (8U)

+#define EXTI_EMR1_EM8_Msk          (0x1UL << EXTI_EMR1_EM8_Pos)                /*!< 0x00000100 */

+#define EXTI_EMR1_EM8              EXTI_EMR1_EM8_Msk                           /*!< Event Mask on line 8 */

+#define EXTI_EMR1_EM9_Pos          (9U)

+#define EXTI_EMR1_EM9_Msk          (0x1UL << EXTI_EMR1_EM9_Pos)                /*!< 0x00000200 */

+#define EXTI_EMR1_EM9              EXTI_EMR1_EM9_Msk                           /*!< Event Mask on line 9 */

+#define EXTI_EMR1_EM10_Pos         (10U)

+#define EXTI_EMR1_EM10_Msk         (0x1UL << EXTI_EMR1_EM10_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR1_EM10             EXTI_EMR1_EM10_Msk                          /*!< Event Mask on line 10 */

+#define EXTI_EMR1_EM11_Pos         (11U)

+#define EXTI_EMR1_EM11_Msk         (0x1UL << EXTI_EMR1_EM11_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR1_EM11             EXTI_EMR1_EM11_Msk                          /*!< Event Mask on line 11 */

+#define EXTI_EMR1_EM12_Pos         (12U)

+#define EXTI_EMR1_EM12_Msk         (0x1UL << EXTI_EMR1_EM12_Pos)               /*!< 0x00001000 */

+#define EXTI_EMR1_EM12             EXTI_EMR1_EM12_Msk                          /*!< Event Mask on line 12 */

+#define EXTI_EMR1_EM13_Pos         (13U)

+#define EXTI_EMR1_EM13_Msk         (0x1UL << EXTI_EMR1_EM13_Pos)               /*!< 0x00002000 */

+#define EXTI_EMR1_EM13             EXTI_EMR1_EM13_Msk                          /*!< Event Mask on line 13 */

+#define EXTI_EMR1_EM14_Pos         (14U)

+#define EXTI_EMR1_EM14_Msk         (0x1UL << EXTI_EMR1_EM14_Pos)               /*!< 0x00004000 */

+#define EXTI_EMR1_EM14             EXTI_EMR1_EM14_Msk                          /*!< Event Mask on line 14 */

+#define EXTI_EMR1_EM15_Pos         (15U)

+#define EXTI_EMR1_EM15_Msk         (0x1UL << EXTI_EMR1_EM15_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR1_EM15             EXTI_EMR1_EM15_Msk                          /*!< Event Mask on line 15 */

+#define EXTI_EMR1_EM16_Pos         (16U)

+#define EXTI_EMR1_EM16_Msk         (0x1UL << EXTI_EMR1_EM16_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR1_EM16             EXTI_EMR1_EM16_Msk                          /*!< Event Mask on line 16 */

+#define EXTI_EMR1_EM17_Pos         (17U)

+#define EXTI_EMR1_EM17_Msk         (0x1UL << EXTI_EMR1_EM17_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR1_EM17             EXTI_EMR1_EM17_Msk                          /*!< Event Mask on line 17 */

+#define EXTI_EMR1_EM18_Pos         (18U)

+#define EXTI_EMR1_EM18_Msk         (0x1UL << EXTI_EMR1_EM18_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR1_EM18             EXTI_EMR1_EM18_Msk                          /*!< Event Mask on line 18 */

+#define EXTI_EMR1_EM20_Pos         (20U)

+#define EXTI_EMR1_EM20_Msk         (0x1UL << EXTI_EMR1_EM20_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR1_EM20             EXTI_EMR1_EM20_Msk                          /*!< Event Mask on line 20 */

+#define EXTI_EMR1_EM21_Pos         (21U)

+#define EXTI_EMR1_EM21_Msk         (0x1UL << EXTI_EMR1_EM21_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR1_EM21             EXTI_EMR1_EM21_Msk                          /*!< Event Mask on line 21 */

+#define EXTI_EMR1_EM22_Pos         (22U)

+#define EXTI_EMR1_EM22_Msk         (0x1UL << EXTI_EMR1_EM22_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR1_EM22             EXTI_EMR1_EM22_Msk                          /*!< Event Mask on line 22 */

+#define EXTI_EMR1_EM23_Pos         (23U)

+#define EXTI_EMR1_EM23_Msk         (0x1UL << EXTI_EMR1_EM23_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR1_EM23             EXTI_EMR1_EM23_Msk                          /*!< Event Mask on line 23 */

+#define EXTI_EMR1_EM24_Pos         (24U)

+#define EXTI_EMR1_EM24_Msk         (0x1UL << EXTI_EMR1_EM24_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR1_EM24             EXTI_EMR1_EM24_Msk                          /*!< Event Mask on line 24 */

+#define EXTI_EMR1_EM25_Pos         (25U)

+#define EXTI_EMR1_EM25_Msk         (0x1UL << EXTI_EMR1_EM25_Pos)               /*!< 0x02000000 */

+#define EXTI_EMR1_EM25             EXTI_EMR1_EM25_Msk                          /*!< Event Mask on line 25 */

+#define EXTI_EMR1_EM26_Pos         (26U)

+#define EXTI_EMR1_EM26_Msk         (0x1UL << EXTI_EMR1_EM26_Pos)               /*!< 0x04000000 */

+#define EXTI_EMR1_EM26             EXTI_EMR1_EM26_Msk                          /*!< Event Mask on line 26 */

+#define EXTI_EMR1_EM27_Pos         (27U)

+#define EXTI_EMR1_EM27_Msk         (0x1UL << EXTI_EMR1_EM27_Pos)               /*!< 0x08000000 */

+#define EXTI_EMR1_EM27             EXTI_EMR1_EM27_Msk                          /*!< Event Mask on line 27 */

+#define EXTI_EMR1_EM28_Pos         (28U)

+#define EXTI_EMR1_EM28_Msk         (0x1UL << EXTI_EMR1_EM28_Pos)               /*!< 0x10000000 */

+#define EXTI_EMR1_EM28             EXTI_EMR1_EM28_Msk                          /*!< Event Mask on line 28 */

+#define EXTI_EMR1_EM29_Pos         (29U)

+#define EXTI_EMR1_EM29_Msk         (0x1UL << EXTI_EMR1_EM29_Pos)               /*!< 0x20000000 */

+#define EXTI_EMR1_EM29             EXTI_EMR1_EM29_Msk                          /*!< Event Mask on line 29 */

+#define EXTI_EMR1_EM30_Pos         (30U)

+#define EXTI_EMR1_EM30_Msk         (0x1UL << EXTI_EMR1_EM30_Pos)               /*!< 0x40000000 */

+#define EXTI_EMR1_EM30             EXTI_EMR1_EM30_Msk                          /*!< Event Mask on line 30 */

+#define EXTI_EMR1_EM31_Pos         (31U)

+#define EXTI_EMR1_EM31_Msk         (0x1UL << EXTI_EMR1_EM31_Pos)               /*!< 0x80000000 */

+#define EXTI_EMR1_EM31             EXTI_EMR1_EM31_Msk                          /*!< Event Mask on line 31 */

+

+/*******************  Bit definition for EXTI_PR1 register  ********************/

+#define EXTI_PR1_PR_Pos            (0U)

+#define EXTI_PR1_PR_Msk            (0x3FFFFFUL << EXTI_PR1_PR_Pos)             /*!< 0x003FFFFF */

+#define EXTI_PR1_PR                EXTI_PR1_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR1_PR0_Pos           (0U)

+#define EXTI_PR1_PR0_Msk           (0x1UL << EXTI_PR1_PR0_Pos)                 /*!< 0x00000001 */

+#define EXTI_PR1_PR0               EXTI_PR1_PR0_Msk                            /*!< Pending bit for line 0 */

+#define EXTI_PR1_PR1_Pos           (1U)

+#define EXTI_PR1_PR1_Msk           (0x1UL << EXTI_PR1_PR1_Pos)                 /*!< 0x00000002 */

+#define EXTI_PR1_PR1               EXTI_PR1_PR1_Msk                            /*!< Pending bit for line 1 */

+#define EXTI_PR1_PR2_Pos           (2U)

+#define EXTI_PR1_PR2_Msk           (0x1UL << EXTI_PR1_PR2_Pos)                 /*!< 0x00000004 */

+#define EXTI_PR1_PR2               EXTI_PR1_PR2_Msk                            /*!< Pending bit for line 2 */

+#define EXTI_PR1_PR3_Pos           (3U)

+#define EXTI_PR1_PR3_Msk           (0x1UL << EXTI_PR1_PR3_Pos)                 /*!< 0x00000008 */

+#define EXTI_PR1_PR3               EXTI_PR1_PR3_Msk                            /*!< Pending bit for line 3 */

+#define EXTI_PR1_PR4_Pos           (4U)

+#define EXTI_PR1_PR4_Msk           (0x1UL << EXTI_PR1_PR4_Pos)                 /*!< 0x00000010 */

+#define EXTI_PR1_PR4               EXTI_PR1_PR4_Msk                            /*!< Pending bit for line 4 */

+#define EXTI_PR1_PR5_Pos           (5U)

+#define EXTI_PR1_PR5_Msk           (0x1UL << EXTI_PR1_PR5_Pos)                 /*!< 0x00000020 */

+#define EXTI_PR1_PR5               EXTI_PR1_PR5_Msk                            /*!< Pending bit for line 5 */

+#define EXTI_PR1_PR6_Pos           (6U)

+#define EXTI_PR1_PR6_Msk           (0x1UL << EXTI_PR1_PR6_Pos)                 /*!< 0x00000040 */

+#define EXTI_PR1_PR6               EXTI_PR1_PR6_Msk                            /*!< Pending bit for line 6 */

+#define EXTI_PR1_PR7_Pos           (7U)

+#define EXTI_PR1_PR7_Msk           (0x1UL << EXTI_PR1_PR7_Pos)                 /*!< 0x00000080 */

+#define EXTI_PR1_PR7               EXTI_PR1_PR7_Msk                            /*!< Pending bit for line 7 */

+#define EXTI_PR1_PR8_Pos           (8U)

+#define EXTI_PR1_PR8_Msk           (0x1UL << EXTI_PR1_PR8_Pos)                 /*!< 0x00000100 */

+#define EXTI_PR1_PR8               EXTI_PR1_PR8_Msk                            /*!< Pending bit for line 8 */

+#define EXTI_PR1_PR9_Pos           (9U)

+#define EXTI_PR1_PR9_Msk           (0x1UL << EXTI_PR1_PR9_Pos)                 /*!< 0x00000200 */

+#define EXTI_PR1_PR9               EXTI_PR1_PR9_Msk                            /*!< Pending bit for line 9 */

+#define EXTI_PR1_PR10_Pos          (10U)

+#define EXTI_PR1_PR10_Msk          (0x1UL << EXTI_PR1_PR10_Pos)                /*!< 0x00000400 */

+#define EXTI_PR1_PR10              EXTI_PR1_PR10_Msk                           /*!< Pending bit for line 10 */

+#define EXTI_PR1_PR11_Pos          (11U)

+#define EXTI_PR1_PR11_Msk          (0x1UL << EXTI_PR1_PR11_Pos)                /*!< 0x00000800 */

+#define EXTI_PR1_PR11              EXTI_PR1_PR11_Msk                           /*!< Pending bit for line 11 */

+#define EXTI_PR1_PR12_Pos          (12U)

+#define EXTI_PR1_PR12_Msk          (0x1UL << EXTI_PR1_PR12_Pos)                /*!< 0x00001000 */

+#define EXTI_PR1_PR12              EXTI_PR1_PR12_Msk                           /*!< Pending bit for line 12 */

+#define EXTI_PR1_PR13_Pos          (13U)

+#define EXTI_PR1_PR13_Msk          (0x1UL << EXTI_PR1_PR13_Pos)                /*!< 0x00002000 */

+#define EXTI_PR1_PR13              EXTI_PR1_PR13_Msk                           /*!< Pending bit for line 13 */

+#define EXTI_PR1_PR14_Pos          (14U)

+#define EXTI_PR1_PR14_Msk          (0x1UL << EXTI_PR1_PR14_Pos)                /*!< 0x00004000 */

+#define EXTI_PR1_PR14              EXTI_PR1_PR14_Msk                           /*!< Pending bit for line 14 */

+#define EXTI_PR1_PR15_Pos          (15U)

+#define EXTI_PR1_PR15_Msk          (0x1UL << EXTI_PR1_PR15_Pos)                /*!< 0x00008000 */

+#define EXTI_PR1_PR15              EXTI_PR1_PR15_Msk                           /*!< Pending bit for line 15 */

+#define EXTI_PR1_PR16_Pos          (16U)

+#define EXTI_PR1_PR16_Msk          (0x1UL << EXTI_PR1_PR16_Pos)                /*!< 0x00010000 */

+#define EXTI_PR1_PR16              EXTI_PR1_PR16_Msk                           /*!< Pending bit for line 16 */

+#define EXTI_PR1_PR17_Pos          (17U)

+#define EXTI_PR1_PR17_Msk          (0x1UL << EXTI_PR1_PR17_Pos)                /*!< 0x00020000 */

+#define EXTI_PR1_PR17              EXTI_PR1_PR17_Msk                           /*!< Pending bit for line 17 */

+#define EXTI_PR1_PR18_Pos          (18U)

+#define EXTI_PR1_PR18_Msk          (0x1UL << EXTI_PR1_PR18_Pos)                /*!< 0x00040000 */

+#define EXTI_PR1_PR18              EXTI_PR1_PR18_Msk                           /*!< Pending bit for line 18 */

+#define EXTI_PR1_PR19_Pos          (19U)

+#define EXTI_PR1_PR19_Msk          (0x1UL << EXTI_PR1_PR19_Pos)                /*!< 0x00080000 */

+#define EXTI_PR1_PR19              EXTI_PR1_PR19_Msk                           /*!< Pending bit for line 19 */

+#define EXTI_PR1_PR20_Pos          (20U)

+#define EXTI_PR1_PR20_Msk          (0x1UL << EXTI_PR1_PR20_Pos)                /*!< 0x00100000 */

+#define EXTI_PR1_PR20              EXTI_PR1_PR20_Msk                           /*!< Pending bit for line 20 */

+#define EXTI_PR1_PR21_Pos          (21U)

+#define EXTI_PR1_PR21_Msk          (0x1UL << EXTI_PR1_PR21_Pos)                /*!< 0x00200000 */

+#define EXTI_PR1_PR21              EXTI_PR1_PR21_Msk                           /*!< Pending bit for line 21 */

+

+/*******************  Bit definition for EXTI_IMR2 register  *******************/

+#define EXTI_IMR2_IM_Pos           (0U)

+#define EXTI_IMR2_IM_Msk           (0xFFFFDFFFUL << EXTI_IMR2_IM_Pos)          /*!< 0xFFFFDFFF */

+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            /*!< Interrupt Mask */

+#define EXTI_IMR2_IM32_Pos         (0U)

+#define EXTI_IMR2_IM32_Msk         (0x1UL << EXTI_IMR2_IM32_Pos)               /*!< 0x00000001 */

+#define EXTI_IMR2_IM32             EXTI_IMR2_IM32_Msk                          /*!< Interrupt Mask on line 32 */

+#define EXTI_IMR2_IM33_Pos         (1U)

+#define EXTI_IMR2_IM33_Msk         (0x1UL << EXTI_IMR2_IM33_Pos)               /*!< 0x00000002 */

+#define EXTI_IMR2_IM33             EXTI_IMR2_IM33_Msk                          /*!< Interrupt Mask on line 33 */

+#define EXTI_IMR2_IM34_Pos         (2U)

+#define EXTI_IMR2_IM34_Msk         (0x1UL << EXTI_IMR2_IM34_Pos)               /*!< 0x00000004 */

+#define EXTI_IMR2_IM34             EXTI_IMR2_IM34_Msk                          /*!< Interrupt Mask on line 34 */

+#define EXTI_IMR2_IM35_Pos         (3U)

+#define EXTI_IMR2_IM35_Msk         (0x1UL << EXTI_IMR2_IM35_Pos)               /*!< 0x00000008 */

+#define EXTI_IMR2_IM35             EXTI_IMR2_IM35_Msk                          /*!< Interrupt Mask on line 35 */

+#define EXTI_IMR2_IM36_Pos         (4U)

+#define EXTI_IMR2_IM36_Msk         (0x1UL << EXTI_IMR2_IM36_Pos)               /*!< 0x00000010 */

+#define EXTI_IMR2_IM36             EXTI_IMR2_IM36_Msk                          /*!< Interrupt Mask on line 36 */

+#define EXTI_IMR2_IM37_Pos         (5U)

+#define EXTI_IMR2_IM37_Msk         (0x1UL << EXTI_IMR2_IM37_Pos)               /*!< 0x00000020 */

+#define EXTI_IMR2_IM37             EXTI_IMR2_IM37_Msk                          /*!< Interrupt Mask on line 37 */

+#define EXTI_IMR2_IM38_Pos         (6U)

+#define EXTI_IMR2_IM38_Msk         (0x1UL << EXTI_IMR2_IM38_Pos)               /*!< 0x00000040 */

+#define EXTI_IMR2_IM38             EXTI_IMR2_IM38_Msk                          /*!< Interrupt Mask on line 38 */

+#define EXTI_IMR2_IM39_Pos         (7U)

+#define EXTI_IMR2_IM39_Msk         (0x1UL << EXTI_IMR2_IM39_Pos)               /*!< 0x00000080 */

+#define EXTI_IMR2_IM39             EXTI_IMR2_IM39_Msk                          /*!< Interrupt Mask on line 39 */

+#define EXTI_IMR2_IM40_Pos         (8U)

+#define EXTI_IMR2_IM40_Msk         (0x1UL << EXTI_IMR2_IM40_Pos)               /*!< 0x00000100 */

+#define EXTI_IMR2_IM40             EXTI_IMR2_IM40_Msk                          /*!< Interrupt Mask on line 40 */

+#define EXTI_IMR2_IM41_Pos         (9U)

+#define EXTI_IMR2_IM41_Msk         (0x1UL << EXTI_IMR2_IM41_Pos)               /*!< 0x00000200 */

+#define EXTI_IMR2_IM41             EXTI_IMR2_IM41_Msk                          /*!< Interrupt Mask on line 41 */

+#define EXTI_IMR2_IM42_Pos         (10U)

+#define EXTI_IMR2_IM42_Msk         (0x1UL << EXTI_IMR2_IM42_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR2_IM42             EXTI_IMR2_IM42_Msk                          /*!< Interrupt Mask on line 42 */

+#define EXTI_IMR2_IM43_Pos         (11U)

+#define EXTI_IMR2_IM43_Msk         (0x1UL << EXTI_IMR2_IM43_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR2_IM43             EXTI_IMR2_IM43_Msk                          /*!< Interrupt Mask on line 43 */

+#define EXTI_IMR2_IM44_Pos         (12U)

+#define EXTI_IMR2_IM44_Msk         (0x1UL << EXTI_IMR2_IM44_Pos)               /*!< 0x00001000 */

+#define EXTI_IMR2_IM44             EXTI_IMR2_IM44_Msk                          /*!< Interrupt Mask on line 44 */

+#define EXTI_IMR2_IM46_Pos         (14U)

+#define EXTI_IMR2_IM46_Msk         (0x1UL << EXTI_IMR2_IM46_Pos)               /*!< 0x00004000 */

+#define EXTI_IMR2_IM46             EXTI_IMR2_IM46_Msk                          /*!< Interrupt Mask on line 46 */

+#define EXTI_IMR2_IM47_Pos         (15U)

+#define EXTI_IMR2_IM47_Msk         (0x1UL << EXTI_IMR2_IM47_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR2_IM47             EXTI_IMR2_IM47_Msk                          /*!< Interrupt Mask on line 47 */

+#define EXTI_IMR2_IM48_Pos         (16U)

+#define EXTI_IMR2_IM48_Msk         (0x1UL << EXTI_IMR2_IM48_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR2_IM48             EXTI_IMR2_IM48_Msk                          /*!< Interrupt Mask on line 48 */

+#define EXTI_IMR2_IM49_Pos         (17U)

+#define EXTI_IMR2_IM49_Msk         (0x1UL << EXTI_IMR2_IM49_Pos)               /*!< 0x00020000 */

+#define EXTI_IMR2_IM49             EXTI_IMR2_IM49_Msk                          /*!< Interrupt Mask on line 49 */

+#define EXTI_IMR2_IM50_Pos         (18U)

+#define EXTI_IMR2_IM50_Msk         (0x1UL << EXTI_IMR2_IM50_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR2_IM50             EXTI_IMR2_IM50_Msk                          /*!< Interrupt Mask on line 50 */

+#define EXTI_IMR2_IM51_Pos         (19U)

+#define EXTI_IMR2_IM51_Msk         (0x1UL << EXTI_IMR2_IM51_Pos)               /*!< 0x00080000 */

+#define EXTI_IMR2_IM51             EXTI_IMR2_IM51_Msk                          /*!< Interrupt Mask on line 51 */

+#define EXTI_IMR2_IM52_Pos         (20U)

+#define EXTI_IMR2_IM52_Msk         (0x1UL << EXTI_IMR2_IM52_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR2_IM52             EXTI_IMR2_IM52_Msk                          /*!< Interrupt Mask on line 52 */

+#define EXTI_IMR2_IM53_Pos         (21U)

+#define EXTI_IMR2_IM53_Msk         (0x1UL << EXTI_IMR2_IM53_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR2_IM53             EXTI_IMR2_IM53_Msk                          /*!< Interrupt Mask on line 53 */

+#define EXTI_IMR2_IM54_Pos         (22U)

+#define EXTI_IMR2_IM54_Msk         (0x1UL << EXTI_IMR2_IM54_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR2_IM54             EXTI_IMR2_IM54_Msk                          /*!< Interrupt Mask on line 54 */

+#define EXTI_IMR2_IM55_Pos         (23U)

+#define EXTI_IMR2_IM55_Msk         (0x1UL << EXTI_IMR2_IM55_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR2_IM55             EXTI_IMR2_IM55_Msk                          /*!< Interrupt Mask on line 55 */

+#define EXTI_IMR2_IM56_Pos         (24U)

+#define EXTI_IMR2_IM56_Msk         (0x1UL << EXTI_IMR2_IM56_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR2_IM56             EXTI_IMR2_IM56_Msk                          /*!< Interrupt Mask on line 56 */

+#define EXTI_IMR2_IM57_Pos         (25U)

+#define EXTI_IMR2_IM57_Msk         (0x1UL << EXTI_IMR2_IM57_Pos)               /*!< 0x02000000 */

+#define EXTI_IMR2_IM57             EXTI_IMR2_IM57_Msk                          /*!< Interrupt Mask on line 57 */

+#define EXTI_IMR2_IM58_Pos         (26U)

+#define EXTI_IMR2_IM58_Msk         (0x1UL << EXTI_IMR2_IM58_Pos)               /*!< 0x04000000 */

+#define EXTI_IMR2_IM58             EXTI_IMR2_IM58_Msk                          /*!< Interrupt Mask on line 58 */

+#define EXTI_IMR2_IM59_Pos         (27U)

+#define EXTI_IMR2_IM59_Msk         (0x1UL << EXTI_IMR2_IM59_Pos)               /*!< 0x08000000 */

+#define EXTI_IMR2_IM59             EXTI_IMR2_IM59_Msk                          /*!< Interrupt Mask on line 59 */

+#define EXTI_IMR2_IM60_Pos         (28U)

+#define EXTI_IMR2_IM60_Msk         (0x1UL << EXTI_IMR2_IM60_Pos)               /*!< 0x10000000 */

+#define EXTI_IMR2_IM60             EXTI_IMR2_IM60_Msk                          /*!< Interrupt Mask on line 60 */

+#define EXTI_IMR2_IM61_Pos         (29U)

+#define EXTI_IMR2_IM61_Msk         (0x1UL << EXTI_IMR2_IM61_Pos)               /*!< 0x20000000 */

+#define EXTI_IMR2_IM61             EXTI_IMR2_IM61_Msk                          /*!< Interrupt Mask on line 61 */

+#define EXTI_IMR2_IM62_Pos         (30U)

+#define EXTI_IMR2_IM62_Msk         (0x1UL << EXTI_IMR2_IM62_Pos)               /*!< 0x40000000 */

+#define EXTI_IMR2_IM62             EXTI_IMR2_IM62_Msk                          /*!< Interrupt Mask on line 62 */

+#define EXTI_IMR2_IM63_Pos         (31U)

+#define EXTI_IMR2_IM63_Msk         (0x1UL << EXTI_IMR2_IM63_Pos)               /*!< 0x80000000 */

+#define EXTI_IMR2_IM63             EXTI_IMR2_IM63_Msk                          /*!< Interrupt Mask on line 63 */

+

+/*******************  Bit definition for EXTI_EMR2 register  *******************/

+#define EXTI_EMR2_EM_Pos           (0U)

+#define EXTI_EMR2_EM_Msk           (0xFFFFDFFFUL << EXTI_EMR2_EM_Pos)          /*!< 0xFFFFDFFF */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            /*!< Event Mask */

+#define EXTI_EMR2_EM32_Pos         (0U)

+#define EXTI_EMR2_EM32_Msk         (0x1UL << EXTI_EMR2_EM32_Pos)               /*!< 0x00000001 */

+#define EXTI_EMR2_EM32             EXTI_EMR2_EM32_Msk                          /*!< Event Mask on line 32*/

+#define EXTI_EMR2_EM33_Pos         (1U)

+#define EXTI_EMR2_EM33_Msk         (0x1UL << EXTI_EMR2_EM33_Pos)               /*!< 0x00000002 */

+#define EXTI_EMR2_EM33             EXTI_EMR2_EM33_Msk                          /*!< Event Mask on line 33*/

+#define EXTI_EMR2_EM34_Pos         (2U)

+#define EXTI_EMR2_EM34_Msk         (0x1UL << EXTI_EMR2_EM34_Pos)               /*!< 0x00000004 */

+#define EXTI_EMR2_EM34             EXTI_EMR2_EM34_Msk                          /*!< Event Mask on line 34*/

+#define EXTI_EMR2_EM35_Pos         (3U)

+#define EXTI_EMR2_EM35_Msk         (0x1UL << EXTI_EMR2_EM35_Pos)               /*!< 0x00000008 */

+#define EXTI_EMR2_EM35             EXTI_EMR2_EM35_Msk                          /*!< Event Mask on line 35*/

+#define EXTI_EMR2_EM36_Pos         (4U)

+#define EXTI_EMR2_EM36_Msk         (0x1UL << EXTI_EMR2_EM36_Pos)               /*!< 0x00000010 */

+#define EXTI_EMR2_EM36             EXTI_EMR2_EM36_Msk                          /*!< Event Mask on line 36*/

+#define EXTI_EMR2_EM37_Pos         (5U)

+#define EXTI_EMR2_EM37_Msk         (0x1UL << EXTI_EMR2_EM37_Pos)               /*!< 0x00000020 */

+#define EXTI_EMR2_EM37             EXTI_EMR2_EM37_Msk                          /*!< Event Mask on line 37*/

+#define EXTI_EMR2_EM38_Pos         (6U)

+#define EXTI_EMR2_EM38_Msk         (0x1UL << EXTI_EMR2_EM38_Pos)               /*!< 0x00000040 */

+#define EXTI_EMR2_EM38             EXTI_EMR2_EM38_Msk                          /*!< Event Mask on line 38*/

+#define EXTI_EMR2_EM39_Pos         (7U)

+#define EXTI_EMR2_EM39_Msk         (0x1UL << EXTI_EMR2_EM39_Pos)               /*!< 0x00000080 */

+#define EXTI_EMR2_EM39             EXTI_EMR2_EM39_Msk                          /*!< Event Mask on line 39*/

+#define EXTI_EMR2_EM40_Pos         (8U)

+#define EXTI_EMR2_EM40_Msk         (0x1UL << EXTI_EMR2_EM40_Pos)               /*!< 0x00000100 */

+#define EXTI_EMR2_EM40             EXTI_EMR2_EM40_Msk                          /*!< Event Mask on line 40*/

+#define EXTI_EMR2_EM41_Pos         (9U)

+#define EXTI_EMR2_EM41_Msk         (0x1UL << EXTI_EMR2_EM41_Pos)               /*!< 0x00000200 */

+#define EXTI_EMR2_EM41             EXTI_EMR2_EM41_Msk                          /*!< Event Mask on line 41*/

+#define EXTI_EMR2_EM42_Pos         (10U)

+#define EXTI_EMR2_EM42_Msk         (0x1UL << EXTI_EMR2_EM42_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR2_EM42             EXTI_EMR2_EM42_Msk                          /*!< Event Mask on line 42 */

+#define EXTI_EMR2_EM43_Pos         (11U)

+#define EXTI_EMR2_EM43_Msk         (0x1UL << EXTI_EMR2_EM43_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR2_EM43             EXTI_EMR2_EM43_Msk                          /*!< Event Mask on line 43 */

+#define EXTI_EMR2_EM44_Pos         (12U)

+#define EXTI_EMR2_EM44_Msk         (0x1UL << EXTI_EMR2_EM44_Pos)               /*!< 0x00001000 */

+#define EXTI_EMR2_EM44             EXTI_EMR2_EM44_Msk                          /*!< Event Mask on line 44 */

+#define EXTI_EMR2_EM46_Pos         (14U)

+#define EXTI_EMR2_EM46_Msk         (0x1UL << EXTI_EMR2_EM46_Pos)               /*!< 0x00004000 */

+#define EXTI_EMR2_EM46             EXTI_EMR2_EM46_Msk                          /*!< Event Mask on line 46 */

+#define EXTI_EMR2_EM47_Pos         (15U)

+#define EXTI_EMR2_EM47_Msk         (0x1UL << EXTI_EMR2_EM47_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR2_EM47             EXTI_EMR2_EM47_Msk                          /*!< Event Mask on line 47 */

+#define EXTI_EMR2_EM48_Pos         (16U)

+#define EXTI_EMR2_EM48_Msk         (0x1UL << EXTI_EMR2_EM48_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR2_EM48             EXTI_EMR2_EM48_Msk                          /*!< Event Mask on line 48 */

+#define EXTI_EMR2_EM49_Pos         (17U)

+#define EXTI_EMR2_EM49_Msk         (0x1UL << EXTI_EMR2_EM49_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR2_EM49             EXTI_EMR2_EM49_Msk                          /*!< Event Mask on line 49 */

+#define EXTI_EMR2_EM50_Pos         (18U)

+#define EXTI_EMR2_EM50_Msk         (0x1UL << EXTI_EMR2_EM50_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR2_EM50             EXTI_EMR2_EM50_Msk                          /*!< Event Mask on line 50 */

+#define EXTI_EMR2_EM51_Pos         (19U)

+#define EXTI_EMR2_EM51_Msk         (0x1UL << EXTI_EMR2_EM51_Pos)               /*!< 0x00080000 */

+#define EXTI_EMR2_EM51             EXTI_EMR2_EM51_Msk                          /*!< Event Mask on line 51 */

+#define EXTI_EMR2_EM52_Pos         (20U)

+#define EXTI_EMR2_EM52_Msk         (0x1UL << EXTI_EMR2_EM52_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR2_EM52             EXTI_EMR2_EM52_Msk                          /*!< Event Mask on line 52 */

+#define EXTI_EMR2_EM53_Pos         (21U)

+#define EXTI_EMR2_EM53_Msk         (0x1UL << EXTI_EMR2_EM53_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR2_EM53             EXTI_EMR2_EM53_Msk                          /*!< Event Mask on line 53 */

+#define EXTI_EMR2_EM54_Pos         (22U)

+#define EXTI_EMR2_EM54_Msk         (0x1UL << EXTI_EMR2_EM54_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR2_EM54             EXTI_EMR2_EM54_Msk                          /*!< Event Mask on line 54 */

+#define EXTI_EMR2_EM55_Pos         (23U)

+#define EXTI_EMR2_EM55_Msk         (0x1UL << EXTI_EMR2_EM55_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR2_EM55             EXTI_EMR2_EM55_Msk                          /*!< Event Mask on line 55 */

+#define EXTI_EMR2_EM56_Pos         (24U)

+#define EXTI_EMR2_EM56_Msk         (0x1UL << EXTI_EMR2_EM56_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR2_EM56             EXTI_EMR2_EM56_Msk                          /*!< Event Mask on line 56 */

+#define EXTI_EMR2_EM57_Pos         (25U)

+#define EXTI_EMR2_EM57_Msk         (0x1UL << EXTI_EMR2_EM57_Pos)               /*!< 0x02000000 */

+#define EXTI_EMR2_EM57             EXTI_EMR2_EM57_Msk                          /*!< Event Mask on line 57 */

+#define EXTI_EMR2_EM58_Pos         (26U)

+#define EXTI_EMR2_EM58_Msk         (0x1UL << EXTI_EMR2_EM58_Pos)               /*!< 0x04000000 */

+#define EXTI_EMR2_EM58             EXTI_EMR2_EM58_Msk                          /*!< Event Mask on line 58 */

+#define EXTI_EMR2_EM59_Pos         (27U)

+#define EXTI_EMR2_EM59_Msk         (0x1UL << EXTI_EMR2_EM59_Pos)               /*!< 0x08000000 */

+#define EXTI_EMR2_EM59             EXTI_EMR2_EM59_Msk                          /*!< Event Mask on line 59 */

+#define EXTI_EMR2_EM60_Pos         (28U)

+#define EXTI_EMR2_EM60_Msk         (0x1UL << EXTI_EMR2_EM60_Pos)               /*!< 0x10000000 */

+#define EXTI_EMR2_EM60             EXTI_EMR2_EM60_Msk                          /*!< Event Mask on line 60 */

+#define EXTI_EMR2_EM61_Pos         (29U)

+#define EXTI_EMR2_EM61_Msk         (0x1UL << EXTI_EMR2_EM61_Pos)               /*!< 0x20000000 */

+#define EXTI_EMR2_EM61             EXTI_EMR2_EM61_Msk                          /*!< Event Mask on line 61 */

+#define EXTI_EMR2_EM62_Pos         (30U)

+#define EXTI_EMR2_EM62_Msk         (0x1UL << EXTI_EMR2_EM62_Pos)               /*!< 0x40000000 */

+#define EXTI_EMR2_EM62             EXTI_EMR2_EM62_Msk                          /*!< Event Mask on line 62 */

+#define EXTI_EMR2_EM63_Pos         (31U)

+#define EXTI_EMR2_EM63_Msk         (0x1UL << EXTI_EMR2_EM63_Pos)               /*!< 0x80000000 */

+#define EXTI_EMR2_EM63             EXTI_EMR2_EM63_Msk                          /*!< Event Mask on line 63 */

+

+/*******************  Bit definition for EXTI_PR2 register  ********************/

+#define EXTI_PR2_PR_Pos            (17U)

+#define EXTI_PR2_PR_Msk            (0x5UL << EXTI_PR2_PR_Pos)                  /*!< 0x000A0000 */

+#define EXTI_PR2_PR                EXTI_PR2_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR2_PR49_Pos          (17U)

+#define EXTI_PR2_PR49_Msk          (0x1UL << EXTI_PR2_PR49_Pos)                /*!< 0x00020000 */

+#define EXTI_PR2_PR49              EXTI_PR2_PR49_Msk                           /*!< Pending bit for line 49 */

+#define EXTI_PR2_PR51_Pos          (19U)

+#define EXTI_PR2_PR51_Msk          (0x1UL << EXTI_PR2_PR51_Pos)                /*!< 0x00080000 */

+#define EXTI_PR2_PR51              EXTI_PR2_PR51_Msk                           /*!< Pending bit for line 51 */

+

+/*******************  Bit definition for EXTI_IMR3 register  *******************/

+#define EXTI_IMR3_IM_Pos           (0U)

+#define EXTI_IMR3_IM_Msk           (0x00F5FFFFUL << EXTI_IMR3_IM_Pos)          /*!< 0x00F5FFFF */

+#define EXTI_IMR3_IM               EXTI_IMR3_IM_Msk                            /*!< Interrupt Mask */

+#define EXTI_IMR3_IM64_Pos         (0U)

+#define EXTI_IMR3_IM64_Msk         (0x1UL << EXTI_IMR3_IM64_Pos)               /*!< 0x00000001 */

+#define EXTI_IMR3_IM64             EXTI_IMR3_IM64_Msk                          /*!< Interrupt Mask on line 64 */

+#define EXTI_IMR3_IM65_Pos         (1U)

+#define EXTI_IMR3_IM65_Msk         (0x1UL << EXTI_IMR3_IM65_Pos)               /*!< 0x00000002 */

+#define EXTI_IMR3_IM65             EXTI_IMR3_IM65_Msk                          /*!< Interrupt Mask on line 65 */

+#define EXTI_IMR3_IM66_Pos         (2U)

+#define EXTI_IMR3_IM66_Msk         (0x1UL << EXTI_IMR3_IM66_Pos)               /*!< 0x00000004 */

+#define EXTI_IMR3_IM66             EXTI_IMR3_IM66_Msk                          /*!< Interrupt Mask on line 66 */

+#define EXTI_IMR3_IM67_Pos         (3U)

+#define EXTI_IMR3_IM67_Msk         (0x1UL << EXTI_IMR3_IM67_Pos)               /*!< 0x00000008 */

+#define EXTI_IMR3_IM67             EXTI_IMR3_IM67_Msk                          /*!< Interrupt Mask on line 67 */

+#define EXTI_IMR3_IM68_Pos         (4U)

+#define EXTI_IMR3_IM68_Msk         (0x1UL << EXTI_IMR3_IM68_Pos)               /*!< 0x00000010 */

+#define EXTI_IMR3_IM68             EXTI_IMR3_IM68_Msk                          /*!< Interrupt Mask on line 68 */

+#define EXTI_IMR3_IM69_Pos         (5U)

+#define EXTI_IMR3_IM69_Msk         (0x1UL << EXTI_IMR3_IM69_Pos)               /*!< 0x00000020 */

+#define EXTI_IMR3_IM69             EXTI_IMR3_IM69_Msk                          /*!< Interrupt Mask on line 69 */

+#define EXTI_IMR3_IM70_Pos         (6U)

+#define EXTI_IMR3_IM70_Msk         (0x1UL << EXTI_IMR3_IM70_Pos)               /*!< 0x00000040 */

+#define EXTI_IMR3_IM70             EXTI_IMR3_IM70_Msk                          /*!< Interrupt Mask on line 70 */

+#define EXTI_IMR3_IM71_Pos         (7U)

+#define EXTI_IMR3_IM71_Msk         (0x1UL << EXTI_IMR3_IM71_Pos)               /*!< 0x00000080 */

+#define EXTI_IMR3_IM71             EXTI_IMR3_IM71_Msk                          /*!< Interrupt Mask on line 71 */

+#define EXTI_IMR3_IM72_Pos         (8U)

+#define EXTI_IMR3_IM72_Msk         (0x1UL << EXTI_IMR3_IM72_Pos)               /*!< 0x00000100 */

+#define EXTI_IMR3_IM72             EXTI_IMR3_IM72_Msk                          /*!< Interrupt Mask on line 72 */

+#define EXTI_IMR3_IM73_Pos         (9U)

+#define EXTI_IMR3_IM73_Msk         (0x1UL << EXTI_IMR3_IM73_Pos)               /*!< 0x00000200 */

+#define EXTI_IMR3_IM73             EXTI_IMR3_IM73_Msk                          /*!< Interrupt Mask on line 73 */

+#define EXTI_IMR3_IM74_Pos         (10U)

+#define EXTI_IMR3_IM74_Msk         (0x1UL << EXTI_IMR3_IM74_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR3_IM74             EXTI_IMR3_IM74_Msk                          /*!< Interrupt Mask on line 74 */

+#define EXTI_IMR3_IM75_Pos         (11U)

+#define EXTI_IMR3_IM75_Msk         (0x1UL << EXTI_IMR3_IM75_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR3_IM75             EXTI_IMR3_IM75_Msk                          /*!< Interrupt Mask on line 75 */

+#define EXTI_IMR3_IM76_Pos         (12U)

+#define EXTI_IMR3_IM76_Msk         (0x1UL << EXTI_IMR3_IM76_Pos)               /*!< 0x00001000 */

+#define EXTI_IMR3_IM76             EXTI_IMR3_IM76_Msk                          /*!< Interrupt Mask on line 76 */

+#define EXTI_IMR3_IM77_Pos         (13U)

+#define EXTI_IMR3_IM77_Msk         (0x1UL << EXTI_IMR3_IM77_Pos)               /*!< 0x00002000 */

+#define EXTI_IMR3_IM77             EXTI_IMR3_IM77_Msk                          /*!< Interrupt Mask on line 77 */

+#define EXTI_IMR3_IM78_Pos         (14U)

+#define EXTI_IMR3_IM78_Msk         (0x1UL << EXTI_IMR3_IM78_Pos)               /*!< 0x00004000 */

+#define EXTI_IMR3_IM78             EXTI_IMR3_IM78_Msk                          /*!< Interrupt Mask on line 78 */

+#define EXTI_IMR3_IM79_Pos         (15U)

+#define EXTI_IMR3_IM79_Msk         (0x1UL << EXTI_IMR3_IM79_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR3_IM79             EXTI_IMR3_IM79_Msk                          /*!< Interrupt Mask on line 79 */

+#define EXTI_IMR3_IM80_Pos         (16U)

+#define EXTI_IMR3_IM80_Msk         (0x1UL << EXTI_IMR3_IM80_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR3_IM80             EXTI_IMR3_IM80_Msk                          /*!< Interrupt Mask on line 80 */

+#define EXTI_IMR3_IM82_Pos         (18U)

+#define EXTI_IMR3_IM82_Msk         (0x1UL << EXTI_IMR3_IM82_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR3_IM82             EXTI_IMR3_IM82_Msk                          /*!< Interrupt Mask on line 82 */

+#define EXTI_IMR3_IM84_Pos         (20U)

+#define EXTI_IMR3_IM84_Msk         (0x1UL << EXTI_IMR3_IM84_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR3_IM84             EXTI_IMR3_IM84_Msk                          /*!< Interrupt Mask on line 84 */

+#define EXTI_IMR3_IM85_Pos         (21U)

+#define EXTI_IMR3_IM85_Msk         (0x1UL << EXTI_IMR3_IM85_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR3_IM85             EXTI_IMR3_IM85_Msk                          /*!< Interrupt Mask on line 85 */

+#define EXTI_IMR3_IM86_Pos         (22U)

+#define EXTI_IMR3_IM86_Msk         (0x1UL << EXTI_IMR3_IM86_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR3_IM86             EXTI_IMR3_IM86_Msk                          /*!< Interrupt Mask on line 86 */

+#define EXTI_IMR3_IM87_Pos         (23U)

+#define EXTI_IMR3_IM87_Msk         (0x1UL << EXTI_IMR3_IM87_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR3_IM87             EXTI_IMR3_IM87_Msk                          /*!< Interrupt Mask on line 87 */

+

+

+/*******************  Bit definition for EXTI_EMR3 register  *******************/

+#define EXTI_EMR3_EM_Pos           (0U)

+#define EXTI_EMR3_EM_Msk           (0x00F5FFFFUL << EXTI_EMR3_EM_Pos)          /*!< 0x00F5FFFF */

+#define EXTI_EMR3_EM               EXTI_EMR3_EM_Msk                            /*!< Event Mask           */

+#define EXTI_EMR3_EM64_Pos         (0U)

+#define EXTI_EMR3_EM64_Msk         (0x1UL << EXTI_EMR3_EM64_Pos)               /*!< 0x00000001 */

+#define EXTI_EMR3_EM64             EXTI_EMR3_EM64_Msk                          /*!< Event Mask on line 64*/

+#define EXTI_EMR3_EM65_Pos         (1U)

+#define EXTI_EMR3_EM65_Msk         (0x1UL << EXTI_EMR3_EM65_Pos)               /*!< 0x00000002 */

+#define EXTI_EMR3_EM65             EXTI_EMR3_EM65_Msk                          /*!< Event Mask on line 65*/

+#define EXTI_EMR3_EM66_Pos         (2U)

+#define EXTI_EMR3_EM66_Msk         (0x1UL << EXTI_EMR3_EM66_Pos)               /*!< 0x00000004 */

+#define EXTI_EMR3_EM66             EXTI_EMR3_EM66_Msk                          /*!< Event Mask on line 66*/

+#define EXTI_EMR3_EM67_Pos         (3U)

+#define EXTI_EMR3_EM67_Msk         (0x1UL << EXTI_EMR3_EM67_Pos)               /*!< 0x00000008 */

+#define EXTI_EMR3_EM67             EXTI_EMR3_EM67_Msk                          /*!< Event Mask on line 67*/

+#define EXTI_EMR3_EM68_Pos         (4U)

+#define EXTI_EMR3_EM68_Msk         (0x1UL << EXTI_EMR3_EM68_Pos)               /*!< 0x00000010 */

+#define EXTI_EMR3_EM68             EXTI_EMR3_EM68_Msk                          /*!< Event Mask on line 68*/

+#define EXTI_EMR3_EM69_Pos         (5U)

+#define EXTI_EMR3_EM69_Msk         (0x1UL << EXTI_EMR3_EM69_Pos)               /*!< 0x00000020 */

+#define EXTI_EMR3_EM69             EXTI_EMR3_EM69_Msk                          /*!< Event Mask on line 69*/

+#define EXTI_EMR3_EM70_Pos         (6U)

+#define EXTI_EMR3_EM70_Msk         (0x1UL << EXTI_EMR3_EM70_Pos)               /*!< 0x00000040 */

+#define EXTI_EMR3_EM70             EXTI_EMR3_EM70_Msk                          /*!< Event Mask on line 70*/

+#define EXTI_EMR3_EM71_Pos         (7U)

+#define EXTI_EMR3_EM71_Msk         (0x1UL << EXTI_EMR3_EM71_Pos)               /*!< 0x00000080 */

+#define EXTI_EMR3_EM71             EXTI_EMR3_EM71_Msk                          /*!< Event Mask on line 71*/

+#define EXTI_EMR3_EM72_Pos         (8U)

+#define EXTI_EMR3_EM72_Msk         (0x1UL << EXTI_EMR3_EM72_Pos)               /*!< 0x00000100 */

+#define EXTI_EMR3_EM72             EXTI_EMR3_EM72_Msk                          /*!< Event Mask on line 72*/

+#define EXTI_EMR3_EM73_Pos         (9U)

+#define EXTI_EMR3_EM73_Msk         (0x1UL << EXTI_EMR3_EM73_Pos)               /*!< 0x00000200 */

+#define EXTI_EMR3_EM73             EXTI_EMR3_EM73_Msk                          /*!< Event Mask on line 73*/

+#define EXTI_EMR3_EM74_Pos         (10U)

+#define EXTI_EMR3_EM74_Msk         (0x1UL << EXTI_EMR3_EM74_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR3_EM74             EXTI_EMR3_EM74_Msk                          /*!< Event Mask on line 74 */

+#define EXTI_EMR3_EM75_Pos         (11U)

+#define EXTI_EMR3_EM75_Msk         (0x1UL << EXTI_EMR3_EM75_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR3_EM75             EXTI_EMR3_EM75_Msk                          /*!< Event Mask on line 75 */

+#define EXTI_EMR3_EM76_Pos         (12U)

+#define EXTI_EMR3_EM76_Msk         (0x1UL << EXTI_EMR3_EM76_Pos)               /*!< 0x00001000 */

+#define EXTI_EMR3_EM76             EXTI_EMR3_EM76_Msk                          /*!< Event Mask on line 76 */

+#define EXTI_EMR3_EM77_Pos         (13U)

+#define EXTI_EMR3_EM77_Msk         (0x1UL << EXTI_EMR3_EM77_Pos)               /*!< 0x00002000 */

+#define EXTI_EMR3_EM77             EXTI_EMR3_EM77_Msk                          /*!< Event Mask on line 77 */

+#define EXTI_EMR3_EM78_Pos         (14U)

+#define EXTI_EMR3_EM78_Msk         (0x1UL << EXTI_EMR3_EM78_Pos)               /*!< 0x00004000 */

+#define EXTI_EMR3_EM78             EXTI_EMR3_EM78_Msk                          /*!< Event Mask on line 78 */

+#define EXTI_EMR3_EM79_Pos         (15U)

+#define EXTI_EMR3_EM79_Msk         (0x1UL << EXTI_EMR3_EM79_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR3_EM79             EXTI_EMR3_EM79_Msk                          /*!< Event Mask on line 79 */

+#define EXTI_EMR3_EM80_Pos         (16U)

+#define EXTI_EMR3_EM80_Msk         (0x1UL << EXTI_EMR3_EM80_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR3_EM80             EXTI_EMR3_EM80_Msk                          /*!< Event Mask on line 80 */

+#define EXTI_EMR3_EM81_Pos         (17U)

+#define EXTI_EMR3_EM81_Msk         (0x1UL << EXTI_EMR3_EM81_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR3_EM81             EXTI_EMR3_EM81_Msk                          /*!< Event Mask on line 81 */

+#define EXTI_EMR3_EM82_Pos         (18U)

+#define EXTI_EMR3_EM82_Msk         (0x1UL << EXTI_EMR3_EM82_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR3_EM82             EXTI_EMR3_EM82_Msk                          /*!< Event Mask on line 82 */

+#define EXTI_EMR3_EM84_Pos         (20U)

+#define EXTI_EMR3_EM84_Msk         (0x1UL << EXTI_EMR3_EM84_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR3_EM84             EXTI_EMR3_EM84_Msk                          /*!< Event Mask on line 84 */

+#define EXTI_EMR3_EM85_Pos         (21U)

+#define EXTI_EMR3_EM85_Msk         (0x1UL << EXTI_EMR3_EM85_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR3_EM85             EXTI_EMR3_EM85_Msk                          /*!< Event Mask on line 85 */

+#define EXTI_EMR3_EM86_Pos         (22U)

+#define EXTI_EMR3_EM86_Msk         (0x1UL << EXTI_EMR3_EM86_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR3_EM86             EXTI_EMR3_EM86_Msk                          /*!< Event Mask on line 86 */

+#define EXTI_EMR3_EM87_Pos         (23U)

+#define EXTI_EMR3_EM87_Msk         (0x1UL << EXTI_EMR3_EM87_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR3_EM87             EXTI_EMR3_EM87_Msk                          /*!< Event Mask on line 87 */

+

+/*******************  Bit definition for EXTI_PR3 register  ********************/

+#define EXTI_PR3_PR_Pos            (18U)

+#define EXTI_PR3_PR_Msk            (0x1DUL << EXTI_PR3_PR_Pos)                 /*!< 0x00740000 */

+#define EXTI_PR3_PR                EXTI_PR3_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR3_PR82_Pos          (18U)

+#define EXTI_PR3_PR82_Msk          (0x1UL << EXTI_PR3_PR82_Pos)                /*!< 0x00040000 */

+#define EXTI_PR3_PR82              EXTI_PR3_PR82_Msk                           /*!< Pending bit for line 82 */

+#define EXTI_PR3_PR84_Pos          (20U)

+#define EXTI_PR3_PR84_Msk          (0x1UL << EXTI_PR3_PR84_Pos)                /*!< 0x00100000 */

+#define EXTI_PR3_PR84              EXTI_PR3_PR84_Msk                           /*!< Pending bit for line 84 */

+#define EXTI_PR3_PR85_Pos          (21U)

+#define EXTI_PR3_PR85_Msk          (0x1UL << EXTI_PR3_PR85_Pos)                /*!< 0x00200000 */

+#define EXTI_PR3_PR85              EXTI_PR3_PR85_Msk                           /*!< Pending bit for line 85 */

+#define EXTI_PR3_PR86_Pos          (22U)

+#define EXTI_PR3_PR86_Msk          (0x1UL << EXTI_PR3_PR86_Pos)                /*!< 0x00400000 */

+#define EXTI_PR3_PR86              EXTI_PR3_PR86_Msk                           /*!< Pending bit for line 86 */

+/******************************************************************************/

+/*                                                                            */

+/*                                    FLASH                                   */

+/*                                                                            */

+/******************************************************************************/

+/*

+* @brief FLASH Global Defines

+*/

+#define FLASH_SECTOR_TOTAL                   8U                    /* 8 sectors */

+#define FLASH_SIZE                           0x200000UL            /* 2 MB   */

+#define FLASH_BANK_SIZE                      (FLASH_SIZE >> 1)     /* 1 MB   */

+#define FLASH_SECTOR_SIZE                    0x00020000UL          /* 128 KB */

+#define FLASH_LATENCY_DEFAULT                FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */

+#define FLASH_NB_32BITWORD_IN_FLASHWORD      8U                    /* 256 bits */

+#define DUAL_BANK                                                  /* Dual-bank Flash */

+

+/*******************  Bits definition for FLASH_ACR register  **********************/

+#define FLASH_ACR_LATENCY_Pos                (0U)

+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */

+#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */

+#define FLASH_ACR_LATENCY_0WS                (0x00000000UL)

+#define FLASH_ACR_LATENCY_1WS                (0x00000001UL)

+#define FLASH_ACR_LATENCY_2WS                (0x00000002UL)

+#define FLASH_ACR_LATENCY_3WS                (0x00000003UL)

+#define FLASH_ACR_LATENCY_4WS                (0x00000004UL)

+#define FLASH_ACR_LATENCY_5WS                (0x00000005UL)

+#define FLASH_ACR_LATENCY_6WS                (0x00000006UL)

+#define FLASH_ACR_LATENCY_7WS                (0x00000007UL)

+#define FLASH_ACR_LATENCY_8WS                (0x00000008UL)

+#define FLASH_ACR_LATENCY_9WS                (0x00000009UL)

+#define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)

+#define FLASH_ACR_LATENCY_11WS               (0x0000000BUL)

+#define FLASH_ACR_LATENCY_12WS               (0x0000000CUL)

+#define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)

+#define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)

+#define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)

+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)

+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */

+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */

+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */

+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */

+

+/*******************  Bits definition for FLASH_CR register  ***********************/

+#define FLASH_CR_LOCK_Pos                    (0U)

+#define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */

+#define FLASH_CR_LOCK                        FLASH_CR_LOCK_Msk                 /*!< Configuration lock bit */

+#define FLASH_CR_PG_Pos                      (1U)

+#define FLASH_CR_PG_Msk                      (0x1UL << FLASH_CR_PG_Pos)        /*!< 0x00000002 */

+#define FLASH_CR_PG                          FLASH_CR_PG_Msk                   /*!< Internal buffer control bit */

+#define FLASH_CR_SER_Pos                     (2U)

+#define FLASH_CR_SER_Msk                     (0x1UL << FLASH_CR_SER_Pos)       /*!< 0x00000004 */

+#define FLASH_CR_SER                         FLASH_CR_SER_Msk                  /*!< Sector erase request */

+#define FLASH_CR_BER_Pos                     (3U)

+#define FLASH_CR_BER_Msk                     (0x1UL << FLASH_CR_BER_Pos)       /*!< 0x00000008 */

+#define FLASH_CR_BER                         FLASH_CR_BER_Msk                  /*!< Bank erase request */

+#define FLASH_CR_PSIZE_Pos                   (4U)

+#define FLASH_CR_PSIZE_Msk                   (0x3UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000030 */

+#define FLASH_CR_PSIZE                       FLASH_CR_PSIZE_Msk                /*!< Program size */

+#define FLASH_CR_PSIZE_0                     (0x1UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000010 */

+#define FLASH_CR_PSIZE_1                     (0x2UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000020 */

+#define FLASH_CR_FW_Pos                      (6U)

+#define FLASH_CR_FW_Msk                      (0x1UL << FLASH_CR_FW_Pos)        /*!< 0x00000040 */

+#define FLASH_CR_FW                          FLASH_CR_FW_Msk                   /*!< Write forcing control bit */

+#define FLASH_CR_START_Pos                   (7U)

+#define FLASH_CR_START_Msk                   (0x1UL << FLASH_CR_START_Pos)     /*!< 0x00000080 */

+#define FLASH_CR_START                       FLASH_CR_START_Msk                /*!< Erase start control bit */

+#define FLASH_CR_SNB_Pos                     (8U)

+#define FLASH_CR_SNB_Msk                     (0x7UL << FLASH_CR_SNB_Pos)       /*!< 0x00000700 */

+#define FLASH_CR_SNB                         FLASH_CR_SNB_Msk                  /*!< Sector erase selection number */

+#define FLASH_CR_SNB_0                       (0x1UL << FLASH_CR_SNB_Pos)       /*!< 0x00000100 */

+#define FLASH_CR_SNB_1                       (0x2UL << FLASH_CR_SNB_Pos)       /*!< 0x00000200 */

+#define FLASH_CR_SNB_2                       (0x4UL << FLASH_CR_SNB_Pos)       /*!< 0x00000400 */

+#define FLASH_CR_CRC_EN_Pos                  (15U)

+#define FLASH_CR_CRC_EN_Msk                  (0x1UL << FLASH_CR_CRC_EN_Pos)    /*!< 0x00008000 */

+#define FLASH_CR_CRC_EN                      FLASH_CR_CRC_EN_Msk               /*!< CRC control bit */

+#define FLASH_CR_EOPIE_Pos                   (16U)

+#define FLASH_CR_EOPIE_Msk                   (0x1UL << FLASH_CR_EOPIE_Pos)     /*!< 0x00010000 */

+#define FLASH_CR_EOPIE                       FLASH_CR_EOPIE_Msk                /*!< End-of-program interrupt control bit */

+#define FLASH_CR_WRPERRIE_Pos                (17U)

+#define FLASH_CR_WRPERRIE_Msk                (0x1UL << FLASH_CR_WRPERRIE_Pos)  /*!< 0x00020000 */

+#define FLASH_CR_WRPERRIE                    FLASH_CR_WRPERRIE_Msk             /*!< Write protection error interrupt enable bit */

+#define FLASH_CR_PGSERRIE_Pos                (18U)

+#define FLASH_CR_PGSERRIE_Msk                (0x1UL << FLASH_CR_PGSERRIE_Pos)  /*!< 0x00040000 */

+#define FLASH_CR_PGSERRIE                    FLASH_CR_PGSERRIE_Msk             /*!< Programming sequence error interrupt enable bit */

+#define FLASH_CR_STRBERRIE_Pos               (19U)

+#define FLASH_CR_STRBERRIE_Msk               (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */

+#define FLASH_CR_STRBERRIE                   FLASH_CR_STRBERRIE_Msk            /*!< Strobe error interrupt enable bit */

+#define FLASH_CR_INCERRIE_Pos                (21U)

+#define FLASH_CR_INCERRIE_Msk                (0x1UL << FLASH_CR_INCERRIE_Pos)  /*!< 0x00200000 */

+#define FLASH_CR_INCERRIE                    FLASH_CR_INCERRIE_Msk             /*!< Inconsistency error interrupt enable bit */

+#define FLASH_CR_OPERRIE_Pos                 (22U)

+#define FLASH_CR_OPERRIE_Msk                 (0x1UL << FLASH_CR_OPERRIE_Pos)   /*!< 0x00400000 */

+#define FLASH_CR_OPERRIE                     FLASH_CR_OPERRIE_Msk              /*!< Write/erase error interrupt enable bit */

+#define FLASH_CR_RDPERRIE_Pos                (23U)

+#define FLASH_CR_RDPERRIE_Msk                (0x1UL << FLASH_CR_RDPERRIE_Pos)  /*!< 0x00800000 */

+#define FLASH_CR_RDPERRIE                    FLASH_CR_RDPERRIE_Msk             /*!< Read protection error interrupt enable bit */

+#define FLASH_CR_RDSERRIE_Pos                (24U)

+#define FLASH_CR_RDSERRIE_Msk                (0x1UL << FLASH_CR_RDSERRIE_Pos)  /*!< 0x01000000 */

+#define FLASH_CR_RDSERRIE                    FLASH_CR_RDSERRIE_Msk             /*!< Secure error interrupt enable bit */

+#define FLASH_CR_SNECCERRIE_Pos              (25U)

+#define FLASH_CR_SNECCERRIE_Msk              (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */

+#define FLASH_CR_SNECCERRIE                  FLASH_CR_SNECCERRIE_Msk            /*!< ECC single correction error interrupt enable bit */

+#define FLASH_CR_DBECCERRIE_Pos              (26U)

+#define FLASH_CR_DBECCERRIE_Msk              (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */

+#define FLASH_CR_DBECCERRIE                  FLASH_CR_DBECCERRIE_Msk            /*!< ECC double detection error interrupt enable bit */

+#define FLASH_CR_CRCENDIE_Pos                (27U)

+#define FLASH_CR_CRCENDIE_Msk                (0x1UL << FLASH_CR_CRCENDIE_Pos)  /*!< 0x08000000 */

+#define FLASH_CR_CRCENDIE                    FLASH_CR_CRCENDIE_Msk             /*!< CRC end of calculation interrupt enable bit */

+#define FLASH_CR_CRCRDERRIE_Pos              (28U)

+#define FLASH_CR_CRCRDERRIE_Msk              (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */

+#define FLASH_CR_CRCRDERRIE                  FLASH_CR_CRCRDERRIE_Msk            /*!< CRC read error interrupt enable bit */

+

+/*******************  Bits definition for FLASH_SR register  ***********************/

+#define FLASH_SR_BSY_Pos                     (0U)

+#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)       /*!< 0x00000001 */

+#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy flag */

+#define FLASH_SR_WBNE_Pos                    (1U)

+#define FLASH_SR_WBNE_Msk                    (0x1UL << FLASH_SR_WBNE_Pos)      /*!< 0x00000002 */

+#define FLASH_SR_WBNE                        FLASH_SR_WBNE_Msk                 /*!< Write buffer not empty flag */

+#define FLASH_SR_QW_Pos                      (2U)

+#define FLASH_SR_QW_Msk                      (0x1UL << FLASH_SR_QW_Pos)        /*!< 0x00000004 */

+#define FLASH_SR_QW                          FLASH_SR_QW_Msk                   /*!< Wait queue flag */

+#define FLASH_SR_CRC_BUSY_Pos                (3U)

+#define FLASH_SR_CRC_BUSY_Msk                (0x1UL << FLASH_SR_CRC_BUSY_Pos)  /*!< 0x00000008 */

+#define FLASH_SR_CRC_BUSY                    FLASH_SR_CRC_BUSY_Msk             /*!< CRC busy flag */

+#define FLASH_SR_EOP_Pos                     (16U)

+#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)       /*!< 0x00010000 */

+#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End-of-program flag */

+#define FLASH_SR_WRPERR_Pos                  (17U)

+#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)    /*!< 0x00020000 */

+#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protection error flag */

+#define FLASH_SR_PGSERR_Pos                  (18U)

+#define FLASH_SR_PGSERR_Msk                  (0x1UL << FLASH_SR_PGSERR_Pos)    /*!< 0x00040000 */

+#define FLASH_SR_PGSERR                      FLASH_SR_PGSERR_Msk               /*!< Programming sequence error flag */

+#define FLASH_SR_STRBERR_Pos                 (19U)

+#define FLASH_SR_STRBERR_Msk                 (0x1UL << FLASH_SR_STRBERR_Pos)   /*!< 0x00080000 */

+#define FLASH_SR_STRBERR                     FLASH_SR_STRBERR_Msk              /*!< Strobe error flag */

+#define FLASH_SR_INCERR_Pos                  (21U)

+#define FLASH_SR_INCERR_Msk                  (0x1UL << FLASH_SR_INCERR_Pos)    /*!< 0x00200000 */

+#define FLASH_SR_INCERR                      FLASH_SR_INCERR_Msk               /*!< Inconsistency error flag */

+#define FLASH_SR_OPERR_Pos                   (22U)

+#define FLASH_SR_OPERR_Msk                   (0x1UL << FLASH_SR_OPERR_Pos)     /*!< 0x00400000 */

+#define FLASH_SR_OPERR                       FLASH_SR_OPERR_Msk                /*!< Write/erase error flag */

+#define FLASH_SR_RDPERR_Pos                  (23U)

+#define FLASH_SR_RDPERR_Msk                  (0x1UL << FLASH_SR_RDPERR_Pos)    /*!< 0x00800000 */

+#define FLASH_SR_RDPERR                      FLASH_SR_RDPERR_Msk               /*!< Read protection error flag */

+#define FLASH_SR_RDSERR_Pos                  (24U)

+#define FLASH_SR_RDSERR_Msk                  (0x1UL << FLASH_SR_RDSERR_Pos)    /*!< 0x01000000 */

+#define FLASH_SR_RDSERR                      FLASH_SR_RDSERR_Msk               /*!< Secure error flag */

+#define FLASH_SR_SNECCERR_Pos                (25U)

+#define FLASH_SR_SNECCERR_Msk                (0x1UL << FLASH_SR_SNECCERR_Pos)  /*!< 0x02000000 */

+#define FLASH_SR_SNECCERR                    FLASH_SR_SNECCERR_Msk             /*!< Single correction error flag */

+#define FLASH_SR_DBECCERR_Pos                (26U)

+#define FLASH_SR_DBECCERR_Msk                (0x1UL << FLASH_SR_DBECCERR_Pos)  /*!< 0x04000000 */

+#define FLASH_SR_DBECCERR                    FLASH_SR_DBECCERR_Msk             /*!< ECC double detection error flag */

+#define FLASH_SR_CRCEND_Pos                  (27U)

+#define FLASH_SR_CRCEND_Msk                  (0x1UL << FLASH_SR_CRCEND_Pos)    /*!< 0x08000000 */

+#define FLASH_SR_CRCEND                      FLASH_SR_CRCEND_Msk               /*!< CRC end of calculation flag */

+#define FLASH_SR_CRCRDERR_Pos                (28U)

+#define FLASH_SR_CRCRDERR_Msk                (0x1UL << FLASH_SR_CRCRDERR_Pos)  /*!< 0x10000000 */

+#define FLASH_SR_CRCRDERR                    FLASH_SR_CRCRDERR_Msk             /*!< CRC read error flag */

+

+/*******************  Bits definition for FLASH_CCR register  *******************/

+#define FLASH_CCR_CLR_EOP_Pos                (16U)

+#define FLASH_CCR_CLR_EOP_Msk                (0x1UL << FLASH_CCR_CLR_EOP_Pos)  /*!< 0x00010000 */

+#define FLASH_CCR_CLR_EOP                    FLASH_CCR_CLR_EOP_Msk             /*!< EOP flag clear bit */

+#define FLASH_CCR_CLR_WRPERR_Pos             (17U)

+#define FLASH_CCR_CLR_WRPERR_Msk             (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */

+#define FLASH_CCR_CLR_WRPERR                 FLASH_CCR_CLR_WRPERR_Msk            /*!< WRPERR flag clear bit */

+#define FLASH_CCR_CLR_PGSERR_Pos             (18U)

+#define FLASH_CCR_CLR_PGSERR_Msk             (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */

+#define FLASH_CCR_CLR_PGSERR                 FLASH_CCR_CLR_PGSERR_Msk            /*!< PGSERR flag clear bit */

+#define FLASH_CCR_CLR_STRBERR_Pos            (19U)

+#define FLASH_CCR_CLR_STRBERR_Msk            (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */

+#define FLASH_CCR_CLR_STRBERR                FLASH_CCR_CLR_STRBERR_Msk            /*!< STRBERR flag clear bit */

+#define FLASH_CCR_CLR_INCERR_Pos             (21U)

+#define FLASH_CCR_CLR_INCERR_Msk             (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */

+#define FLASH_CCR_CLR_INCERR                 FLASH_CCR_CLR_INCERR_Msk            /*!< INCERR flag clear bit */

+#define FLASH_CCR_CLR_OPERR_Pos              (22U)

+#define FLASH_CCR_CLR_OPERR_Msk              (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */

+#define FLASH_CCR_CLR_OPERR                  FLASH_CCR_CLR_OPERR_Msk            /*!< OPERR flag clear bit */

+#define FLASH_CCR_CLR_RDPERR_Pos             (23U)

+#define FLASH_CCR_CLR_RDPERR_Msk             (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */

+#define FLASH_CCR_CLR_RDPERR                 FLASH_CCR_CLR_RDPERR_Msk            /*!< RDPERR flag clear bit */

+#define FLASH_CCR_CLR_RDSERR_Pos             (24U)

+#define FLASH_CCR_CLR_RDSERR_Msk             (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */

+#define FLASH_CCR_CLR_RDSERR                 FLASH_CCR_CLR_RDSERR_Msk            /*!< RDSERR flag clear bit */

+#define FLASH_CCR_CLR_SNECCERR_Pos           (25U)

+#define FLASH_CCR_CLR_SNECCERR_Msk           (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */

+#define FLASH_CCR_CLR_SNECCERR               FLASH_CCR_CLR_SNECCERR_Msk            /*!< SNECCERR flag clear bit */

+#define FLASH_CCR_CLR_DBECCERR_Pos           (26U)

+#define FLASH_CCR_CLR_DBECCERR_Msk           (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */

+#define FLASH_CCR_CLR_DBECCERR               FLASH_CCR_CLR_DBECCERR_Msk            /*!< DBECCERR flag clear bit */

+#define FLASH_CCR_CLR_CRCEND_Pos             (27U)

+#define FLASH_CCR_CLR_CRCEND_Msk             (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */

+#define FLASH_CCR_CLR_CRCEND                 FLASH_CCR_CLR_CRCEND_Msk            /*!< CRCEND flag clear bit */

+#define FLASH_CCR_CLR_CRCRDERR_Pos           (28U)

+#define FLASH_CCR_CLR_CRCRDERR_Msk           (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */

+#define FLASH_CCR_CLR_CRCRDERR               FLASH_CCR_CLR_CRCRDERR_Msk            /*!< CRCRDERR flag clear bit */

+

+/*******************  Bits definition for FLASH_OPTCR register  *******************/

+#define FLASH_OPTCR_OPTLOCK_Pos              (0U)

+#define FLASH_OPTCR_OPTLOCK_Msk              (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)  /*!< 0x00000001 */

+#define FLASH_OPTCR_OPTLOCK                  FLASH_OPTCR_OPTLOCK_Msk             /*!< FLASH_OPTCR lock option configuration bit */

+#define FLASH_OPTCR_OPTSTART_Pos             (1U)

+#define FLASH_OPTCR_OPTSTART_Msk             (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */

+#define FLASH_OPTCR_OPTSTART                 FLASH_OPTCR_OPTSTART_Msk            /*!< Option byte start change option configuration bit */

+#define FLASH_OPTCR_MER_Pos                  (4U)

+#define FLASH_OPTCR_MER_Msk                  (0x1UL << FLASH_OPTCR_MER_Pos)      /*!< 0x00000010 */

+#define FLASH_OPTCR_MER                      FLASH_OPTCR_MER_Msk                 /*!< Mass erase request */

+#define FLASH_OPTCR_OPTCHANGEERRIE_Pos       (30U)

+#define FLASH_OPTCR_OPTCHANGEERRIE_Msk       (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */

+#define FLASH_OPTCR_OPTCHANGEERRIE           FLASH_OPTCR_OPTCHANGEERRIE_Msk            /*!< Option byte change error interrupt enable bit */

+#define FLASH_OPTCR_SWAP_BANK_Pos            (31U)

+#define FLASH_OPTCR_SWAP_BANK_Msk            (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */

+#define FLASH_OPTCR_SWAP_BANK                FLASH_OPTCR_SWAP_BANK_Msk            /*!< Bank swapping option configuration bit */

+

+/*******************  Bits definition for FLASH_OPTSR register  ***************/

+#define FLASH_OPTSR_OPT_BUSY_Pos             (0U)

+#define FLASH_OPTSR_OPT_BUSY_Msk             (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */

+#define FLASH_OPTSR_OPT_BUSY                 FLASH_OPTSR_OPT_BUSY_Msk            /*!< Option byte change ongoing flag */

+#define FLASH_OPTSR_BOR_LEV_Pos              (2U)

+#define FLASH_OPTSR_BOR_LEV_Msk              (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */

+#define FLASH_OPTSR_BOR_LEV                  FLASH_OPTSR_BOR_LEV_Msk            /*!< Brownout level option status bit */

+#define FLASH_OPTSR_BOR_LEV_0                (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */

+#define FLASH_OPTSR_BOR_LEV_1                (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */

+#define FLASH_OPTSR_IWDG1_SW_Pos             (4U)

+#define FLASH_OPTSR_IWDG1_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */

+#define FLASH_OPTSR_IWDG1_SW                 FLASH_OPTSR_IWDG1_SW_Msk            /*!< IWDG1 control mode option status bit */

+#define FLASH_OPTSR_NRST_STOP_D1_Pos         (6U)

+#define FLASH_OPTSR_NRST_STOP_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */

+#define FLASH_OPTSR_NRST_STOP_D1             FLASH_OPTSR_NRST_STOP_D1_Msk            /*!< D1 domain DStop entry reset option status bit */

+#define FLASH_OPTSR_NRST_STBY_D1_Pos         (7U)

+#define FLASH_OPTSR_NRST_STBY_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */

+#define FLASH_OPTSR_NRST_STBY_D1             FLASH_OPTSR_NRST_STBY_D1_Msk            /*!< D1 domain DStandby entry reset option status bit */

+#define FLASH_OPTSR_RDP_Pos                  (8U)

+#define FLASH_OPTSR_RDP_Msk                  (0xFFUL << FLASH_OPTSR_RDP_Pos)   /*!< 0x0000FF00 */

+#define FLASH_OPTSR_RDP                      FLASH_OPTSR_RDP_Msk               /*!< Readout protection level option status byte */

+#define FLASH_OPTSR_FZ_IWDG_STOP_Pos         (17U)

+#define FLASH_OPTSR_FZ_IWDG_STOP_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */

+#define FLASH_OPTSR_FZ_IWDG_STOP             FLASH_OPTSR_FZ_IWDG_STOP_Msk            /*!< IWDG Stop mode freeze option status bit */

+#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos         (18U)

+#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */

+#define FLASH_OPTSR_FZ_IWDG_SDBY             FLASH_OPTSR_FZ_IWDG_SDBY_Msk            /*!< IWDG Standby mode freeze option status bit */

+#define FLASH_OPTSR_ST_RAM_SIZE_Pos          (19U)

+#define FLASH_OPTSR_ST_RAM_SIZE_Msk          (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */

+#define FLASH_OPTSR_ST_RAM_SIZE              FLASH_OPTSR_ST_RAM_SIZE_Msk            /*!< ST RAM size option status */

+#define FLASH_OPTSR_ST_RAM_SIZE_0            (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */

+#define FLASH_OPTSR_ST_RAM_SIZE_1            (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */

+#define FLASH_OPTSR_SECURITY_Pos             (21U)

+#define FLASH_OPTSR_SECURITY_Msk             (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */

+#define FLASH_OPTSR_SECURITY                 FLASH_OPTSR_SECURITY_Msk            /*!< Security enable option status bit */

+#define FLASH_OPTSR_IO_HSLV_Pos              (29U)

+#define FLASH_OPTSR_IO_HSLV_Msk              (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */

+#define FLASH_OPTSR_IO_HSLV                  FLASH_OPTSR_IO_HSLV_Msk            /*!< I/O high-speed at low-voltage status bit */

+#define FLASH_OPTSR_OPTCHANGEERR_Pos         (30U)

+#define FLASH_OPTSR_OPTCHANGEERR_Msk         (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */

+#define FLASH_OPTSR_OPTCHANGEERR             FLASH_OPTSR_OPTCHANGEERR_Msk            /*!< Option byte change error flag */

+#define FLASH_OPTSR_SWAP_BANK_OPT_Pos        (31U)

+#define FLASH_OPTSR_SWAP_BANK_OPT_Msk        (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */

+#define FLASH_OPTSR_SWAP_BANK_OPT            FLASH_OPTSR_SWAP_BANK_OPT_Msk            /*!< Bank swapping option status bit */

+

+/*******************  Bits definition for FLASH_OPTCCR register  *******************/

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos    (30U)

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk    (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR        FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk            /*!< OPTCHANGEERR reset bit */

+

+/*******************  Bits definition for FLASH_PRAR register  *********************/

+#define FLASH_PRAR_PROT_AREA_START_Pos       (0U)

+#define FLASH_PRAR_PROT_AREA_START_Msk       (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */

+#define FLASH_PRAR_PROT_AREA_START           FLASH_PRAR_PROT_AREA_START_Msk              /*!< PCROP area start status bits */

+#define FLASH_PRAR_PROT_AREA_END_Pos         (16U)

+#define FLASH_PRAR_PROT_AREA_END_Msk         (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */

+#define FLASH_PRAR_PROT_AREA_END             FLASH_PRAR_PROT_AREA_END_Msk              /*!< PCROP area end status bits */

+#define FLASH_PRAR_DMEP_Pos                  (31U)

+#define FLASH_PRAR_DMEP_Msk                  (0x1UL << FLASH_PRAR_DMEP_Pos)    /*!< 0x80000000 */

+#define FLASH_PRAR_DMEP                      FLASH_PRAR_DMEP_Msk               /*!< PCROP protected erase enable option status bit */

+

+/*******************  Bits definition for FLASH_SCAR register  *********************/

+#define FLASH_SCAR_SEC_AREA_START_Pos        (0U)

+#define FLASH_SCAR_SEC_AREA_START_Msk        (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */

+#define FLASH_SCAR_SEC_AREA_START            FLASH_SCAR_SEC_AREA_START_Msk              /*!< Secure-only area start status bits */

+#define FLASH_SCAR_SEC_AREA_END_Pos          (16U)

+#define FLASH_SCAR_SEC_AREA_END_Msk          (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */

+#define FLASH_SCAR_SEC_AREA_END              FLASH_SCAR_SEC_AREA_END_Msk              /*!< Secure-only area end status bits */

+#define FLASH_SCAR_DMES_Pos                  (31U)

+#define FLASH_SCAR_DMES_Msk                  (0x1UL << FLASH_SCAR_DMES_Pos)    /*!< 0x80000000 */

+#define FLASH_SCAR_DMES                      FLASH_SCAR_DMES_Msk               /*!< Secure access protected erase enable option status bit */

+

+/*******************  Bits definition for FLASH_WPSN register  *********************/

+#define FLASH_WPSN_WRPSN_Pos                 (0U)

+#define FLASH_WPSN_WRPSN_Msk                 (0xFFUL << FLASH_WPSN_WRPSN_Pos)  /*!< 0x000000FF */

+#define FLASH_WPSN_WRPSN                     FLASH_WPSN_WRPSN_Msk              /*!< Sector write protection option status byte */

+

+/*******************  Bits definition for FLASH_BOOT_CUR register  ****************/

+#define FLASH_BOOT_ADD0_Pos                  (0U)

+#define FLASH_BOOT_ADD0_Msk                  (0xFFFFUL << FLASH_BOOT_ADD0_Pos) /*!< 0x0000FFFF */

+#define FLASH_BOOT_ADD0                      FLASH_BOOT_ADD0_Msk               /*!< Arm Cortex-M7 boot address 0 */

+#define FLASH_BOOT_ADD1_Pos                  (16U)

+#define FLASH_BOOT_ADD1_Msk                  (0xFFFFUL << FLASH_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */

+#define FLASH_BOOT_ADD1                      FLASH_BOOT_ADD1_Msk               /*!< Arm Cortex-M7 boot address 1 */

+

+

+/*******************  Bits definition for FLASH_CRCCR register  ********************/

+#define FLASH_CRCCR_CRC_SECT_Pos             (0U)

+#define FLASH_CRCCR_CRC_SECT_Msk             (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */

+#define FLASH_CRCCR_CRC_SECT                 FLASH_CRCCR_CRC_SECT_Msk            /*!< CRC sector number */

+#define FLASH_CRCCR_CRC_BY_SECT_Pos          (8U)

+#define FLASH_CRCCR_CRC_BY_SECT_Msk          (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */

+#define FLASH_CRCCR_CRC_BY_SECT              FLASH_CRCCR_CRC_BY_SECT_Msk            /*!< CRC sector mode select bit */

+#define FLASH_CRCCR_ADD_SECT_Pos             (9U)

+#define FLASH_CRCCR_ADD_SECT_Msk             (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */

+#define FLASH_CRCCR_ADD_SECT                 FLASH_CRCCR_ADD_SECT_Msk            /*!< CRC sector select bit */

+#define FLASH_CRCCR_CLEAN_SECT_Pos           (10U)

+#define FLASH_CRCCR_CLEAN_SECT_Msk           (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */

+#define FLASH_CRCCR_CLEAN_SECT               FLASH_CRCCR_CLEAN_SECT_Msk            /*!< CRC sector list clear bit */

+#define FLASH_CRCCR_START_CRC_Pos            (16U)

+#define FLASH_CRCCR_START_CRC_Msk            (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */

+#define FLASH_CRCCR_START_CRC                FLASH_CRCCR_START_CRC_Msk            /*!< CRC start bit */

+#define FLASH_CRCCR_CLEAN_CRC_Pos            (17U)

+#define FLASH_CRCCR_CLEAN_CRC_Msk            (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */

+#define FLASH_CRCCR_CLEAN_CRC                FLASH_CRCCR_CLEAN_CRC_Msk            /*!< CRC clear bit */

+#define FLASH_CRCCR_CRC_BURST_Pos            (20U)

+#define FLASH_CRCCR_CRC_BURST_Msk            (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */

+#define FLASH_CRCCR_CRC_BURST                FLASH_CRCCR_CRC_BURST_Msk            /*!< CRC burst size */

+#define FLASH_CRCCR_CRC_BURST_0              (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */

+#define FLASH_CRCCR_CRC_BURST_1              (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */

+#define FLASH_CRCCR_ALL_BANK_Pos             (22U)

+#define FLASH_CRCCR_ALL_BANK_Msk             (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */

+#define FLASH_CRCCR_ALL_BANK                 FLASH_CRCCR_ALL_BANK_Msk            /*!< CRC select bit */

+

+/*******************  Bits definition for FLASH_CRCSADD register  ****************/

+#define FLASH_CRCSADD_CRC_START_ADDR_Pos     (0U)

+#define FLASH_CRCSADD_CRC_START_ADDR_Msk     (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCSADD_CRC_START_ADDR         FLASH_CRCSADD_CRC_START_ADDR_Msk                   /*!< CRC start address */

+

+/*******************  Bits definition for FLASH_CRCEADD register  ****************/

+#define FLASH_CRCEADD_CRC_END_ADDR_Pos       (0U)

+#define FLASH_CRCEADD_CRC_END_ADDR_Msk       (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCEADD_CRC_END_ADDR           FLASH_CRCEADD_CRC_END_ADDR_Msk                   /*!< CRC end address */

+

+/*******************  Bits definition for FLASH_CRCDATA register  ***************/

+#define FLASH_CRCDATA_CRC_DATA_Pos           (0U)

+#define FLASH_CRCDATA_CRC_DATA_Msk           (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCDATA_CRC_DATA               FLASH_CRCDATA_CRC_DATA_Msk                   /*!< CRC result */

+

+/*******************  Bits definition for FLASH_ECC_FA register  *******************/

+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos       (0U)

+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk       (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */

+#define FLASH_ECC_FA_FAIL_ECC_ADDR           FLASH_ECC_FA_FAIL_ECC_ADDR_Msk               /*!< ECC error address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          Flexible Memory Controller                        */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for FMC_BCR1 register  *******************/

+#define FMC_BCR1_CCLKEN_Pos        (20U)

+#define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */

+#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continous clock enable     */

+#define FMC_BCR1_WFDIS_Pos         (21U)

+#define FMC_BCR1_WFDIS_Msk         (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */

+#define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */

+

+#define FMC_BCR1_BMAP_Pos          (24U)

+#define FMC_BCR1_BMAP_Msk          (0x3UL << FMC_BCR1_BMAP_Pos)                /*!< 0x03000000 */

+#define FMC_BCR1_BMAP              FMC_BCR1_BMAP_Msk                           /*!<BMAP[1:0] FMC bank mapping */

+#define FMC_BCR1_BMAP_0            (0x1UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x01000000 */

+#define FMC_BCR1_BMAP_1            (0x2UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x02000000 */

+

+#define FMC_BCR1_FMCEN_Pos         (31U)

+#define FMC_BCR1_FMCEN_Msk         (0x1UL << FMC_BCR1_FMCEN_Pos)               /*!< 0x80000000 */

+#define FMC_BCR1_FMCEN             FMC_BCR1_FMCEN_Msk                          /*!<FMC controller Enable */

+/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/

+#define FMC_BCRx_MBKEN_Pos         (0U)

+#define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */

+#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */

+#define FMC_BCRx_MUXEN_Pos         (1U)

+#define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */

+#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */

+

+#define FMC_BCRx_MTYP_Pos          (2U)

+#define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */

+#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */

+#define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000004 */

+#define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000008 */

+

+#define FMC_BCRx_MWID_Pos          (4U)

+#define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */

+#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */

+#define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000010 */

+#define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000020 */

+

+#define FMC_BCRx_FACCEN_Pos        (6U)

+#define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */

+#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */

+#define FMC_BCRx_BURSTEN_Pos       (8U)

+#define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */

+#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */

+#define FMC_BCRx_WAITPOL_Pos       (9U)

+#define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */

+#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */

+#define FMC_BCRx_WAITCFG_Pos       (11U)

+#define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */

+#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */

+#define FMC_BCRx_WREN_Pos          (12U)

+#define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */

+#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */

+#define FMC_BCRx_WAITEN_Pos        (13U)

+#define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */

+#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */

+#define FMC_BCRx_EXTMOD_Pos        (14U)

+#define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */

+#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */

+#define FMC_BCRx_ASYNCWAIT_Pos     (15U)

+#define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */

+#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */

+

+#define FMC_BCRx_CPSIZE_Pos        (16U)

+#define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */

+#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<PSIZE[2:0] bits CRAM Page Size */

+#define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00010000 */

+#define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00020000 */

+#define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00040000 */

+

+#define FMC_BCRx_CBURSTRW_Pos      (19U)

+#define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */

+#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */

+

+/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/

+#define FMC_BTRx_ADDSET_Pos        (0U)

+#define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */

+#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */

+#define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000001 */

+#define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000002 */

+#define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000004 */

+#define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000008 */

+

+#define FMC_BTRx_ADDHLD_Pos        (4U)

+#define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */

+#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */

+#define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000010 */

+#define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000020 */

+#define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000040 */

+#define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000080 */

+

+#define FMC_BTRx_DATAST_Pos        (8U)

+#define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */

+#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */

+#define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000100 */

+#define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000200 */

+#define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000400 */

+#define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000800 */

+#define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00001000 */

+#define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00002000 */

+#define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00004000 */

+#define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00008000 */

+

+#define FMC_BTRx_BUSTURN_Pos       (16U)

+#define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */

+#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */

+#define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00010000 */

+#define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00020000 */

+#define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00040000 */

+#define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00080000 */

+

+#define FMC_BTRx_CLKDIV_Pos        (20U)

+#define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */

+#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */

+#define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00100000 */

+#define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00200000 */

+#define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00400000 */

+#define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00800000 */

+

+#define FMC_BTRx_DATLAT_Pos        (24U)

+#define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */

+#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */

+#define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x01000000 */

+#define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x02000000 */

+#define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x04000000 */

+#define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x08000000 */

+

+#define FMC_BTRx_ACCMOD_Pos        (28U)

+#define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */

+#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */

+#define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x10000000 */

+#define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x20000000 */

+

+/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/

+#define FMC_BWTRx_ADDSET_Pos       (0U)

+#define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */

+#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */

+#define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000001 */

+#define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000002 */

+#define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000004 */

+#define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000008 */

+

+#define FMC_BWTRx_ADDHLD_Pos       (4U)

+#define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */

+#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */

+#define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000010 */

+#define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000020 */

+#define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000040 */

+#define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000080 */

+

+#define FMC_BWTRx_DATAST_Pos       (8U)

+#define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */

+#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */

+#define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000100 */

+#define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000200 */

+#define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000400 */

+#define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000800 */

+#define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00001000 */

+#define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00002000 */

+#define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00004000 */

+#define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00008000 */

+

+#define FMC_BWTRx_BUSTURN_Pos      (16U)

+#define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */

+#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */

+#define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00010000 */

+#define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00020000 */

+#define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00040000 */

+#define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00080000 */

+

+#define FMC_BWTRx_ACCMOD_Pos       (28U)

+#define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */

+#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */

+#define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x10000000 */

+#define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x20000000 */

+

+/******************  Bit definition for FMC_PCR register  *******************/

+#define FMC_PCR_PWAITEN_Pos        (1U)

+#define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */

+#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */

+#define FMC_PCR_PBKEN_Pos          (2U)

+#define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */

+#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */

+

+#define FMC_PCR_PWID_Pos           (4U)

+#define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */

+#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */

+#define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */

+#define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */

+

+#define FMC_PCR_ECCEN_Pos          (6U)

+#define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */

+#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */

+

+#define FMC_PCR_TCLR_Pos           (9U)

+#define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */

+#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */

+#define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */

+#define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */

+#define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */

+#define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */

+

+#define FMC_PCR_TAR_Pos            (13U)

+#define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */

+#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */

+#define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */

+#define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */

+#define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */

+#define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */

+

+#define FMC_PCR_ECCPS_Pos          (17U)

+#define FMC_PCR_ECCPS_Msk          (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */

+#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */

+#define FMC_PCR_ECCPS_0            (0x1UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */

+#define FMC_PCR_ECCPS_1            (0x2UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */

+#define FMC_PCR_ECCPS_2            (0x4UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */

+

+/*******************  Bit definition for FMC_SR register  *******************/

+#define FMC_SR_IRS_Pos             (0U)

+#define FMC_SR_IRS_Msk             (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */

+#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */

+#define FMC_SR_ILS_Pos             (1U)

+#define FMC_SR_ILS_Msk             (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */

+#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */

+#define FMC_SR_IFS_Pos             (2U)

+#define FMC_SR_IFS_Msk             (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */

+#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */

+#define FMC_SR_IREN_Pos            (3U)

+#define FMC_SR_IREN_Msk            (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */

+#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */

+#define FMC_SR_ILEN_Pos            (4U)

+#define FMC_SR_ILEN_Msk            (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */

+#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */

+#define FMC_SR_IFEN_Pos            (5U)

+#define FMC_SR_IFEN_Msk            (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */

+#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */

+#define FMC_SR_FEMPT_Pos           (6U)

+#define FMC_SR_FEMPT_Msk           (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */

+#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */

+

+/******************  Bit definition for FMC_PMEM register  ******************/

+#define FMC_PMEM_MEMSET_Pos       (0U)

+#define FMC_PMEM_MEMSET_Msk       (0xFFUL << FMC_PMEM_MEMSET_Pos)            /*!< 0x000000FF */

+#define FMC_PMEM_MEMSET           FMC_PMEM_MEMSET_Msk                        /*!<MEMSET[7:0] bits (Common memory setup time) */

+#define FMC_PMEM_MEMSET_0         (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */

+#define FMC_PMEM_MEMSET_1         (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */

+#define FMC_PMEM_MEMSET_2         (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */

+#define FMC_PMEM_MEMSET_3         (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */

+#define FMC_PMEM_MEMSET_4         (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */

+#define FMC_PMEM_MEMSET_5         (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */

+#define FMC_PMEM_MEMSET_6         (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */

+#define FMC_PMEM_MEMSET_7         (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */

+

+#define FMC_PMEM_MEMWAIT_Pos      (8U)

+#define FMC_PMEM_MEMWAIT_Msk      (0xFFUL << FMC_PMEM_MEMWAIT_Pos)           /*!< 0x0000FF00 */

+#define FMC_PMEM_MEMWAIT          FMC_PMEM_MEMWAIT_Msk                       /*!<MEMWAIT[7:0] bits (Common memory wait time) */

+#define FMC_PMEM_MEMWAIT_0        (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */

+#define FMC_PMEM_MEMWAIT_1        (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */

+#define FMC_PMEM_MEMWAIT_2        (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */

+#define FMC_PMEM_MEMWAIT_3        (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */

+#define FMC_PMEM_MEMWAIT_4        (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */

+#define FMC_PMEM_MEMWAIT_5        (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */

+#define FMC_PMEM_MEMWAIT_6        (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */

+#define FMC_PMEM_MEMWAIT_7        (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */

+

+#define FMC_PMEM_MEMHOLD_Pos      (16U)

+#define FMC_PMEM_MEMHOLD_Msk      (0xFFUL << FMC_PMEM_MEMHOLD_Pos)           /*!< 0x00FF0000 */

+#define FMC_PMEM_MEMHOLD          FMC_PMEM_MEMHOLD_Msk                       /*!<MEMHOLD[7:0] bits (Common memory hold time) */

+#define FMC_PMEM_MEMHOLD_0        (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */

+#define FMC_PMEM_MEMHOLD_1        (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */

+#define FMC_PMEM_MEMHOLD_2        (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */

+#define FMC_PMEM_MEMHOLD_3        (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */

+#define FMC_PMEM_MEMHOLD_4        (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */

+#define FMC_PMEM_MEMHOLD_5        (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */

+#define FMC_PMEM_MEMHOLD_6        (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */

+#define FMC_PMEM_MEMHOLD_7        (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */

+

+#define FMC_PMEM_MEMHIZ_Pos       (24U)

+#define FMC_PMEM_MEMHIZ_Msk       (0xFFUL << FMC_PMEM_MEMHIZ_Pos)            /*!< 0xFF000000 */

+#define FMC_PMEM_MEMHIZ           FMC_PMEM_MEMHIZ_Msk                        /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */

+#define FMC_PMEM_MEMHIZ_0         (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */

+#define FMC_PMEM_MEMHIZ_1         (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */

+#define FMC_PMEM_MEMHIZ_2         (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */

+#define FMC_PMEM_MEMHIZ_3         (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */

+#define FMC_PMEM_MEMHIZ_4         (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */

+#define FMC_PMEM_MEMHIZ_5         (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */

+#define FMC_PMEM_MEMHIZ_6         (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */

+#define FMC_PMEM_MEMHIZ_7         (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */

+

+/******************  Bit definition for FMC_PATT register  ******************/

+#define FMC_PATT_ATTSET_Pos       (0U)

+#define FMC_PATT_ATTSET_Msk       (0xFFUL << FMC_PATT_ATTSET_Pos)            /*!< 0x000000FF */

+#define FMC_PATT_ATTSET           FMC_PATT_ATTSET_Msk                        /*!<ATTSET[7:0] bits (Attribute memory setup time) */

+#define FMC_PATT_ATTSET_0         (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */

+#define FMC_PATT_ATTSET_1         (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */

+#define FMC_PATT_ATTSET_2         (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */

+#define FMC_PATT_ATTSET_3         (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */

+#define FMC_PATT_ATTSET_4         (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */

+#define FMC_PATT_ATTSET_5         (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */

+#define FMC_PATT_ATTSET_6         (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */

+#define FMC_PATT_ATTSET_7         (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */

+

+#define FMC_PATT_ATTWAIT_Pos      (8U)

+#define FMC_PATT_ATTWAIT_Msk      (0xFFUL << FMC_PATT_ATTWAIT_Pos)           /*!< 0x0000FF00 */

+#define FMC_PATT_ATTWAIT          FMC_PATT_ATTWAIT_Msk                       /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */

+#define FMC_PATT_ATTWAIT_0        (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */

+#define FMC_PATT_ATTWAIT_1        (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */

+#define FMC_PATT_ATTWAIT_2        (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */

+#define FMC_PATT_ATTWAIT_3        (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */

+#define FMC_PATT_ATTWAIT_4        (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */

+#define FMC_PATT_ATTWAIT_5        (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */

+#define FMC_PATT_ATTWAIT_6        (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */

+#define FMC_PATT_ATTWAIT_7        (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */

+

+#define FMC_PATT_ATTHOLD_Pos      (16U)

+#define FMC_PATT_ATTHOLD_Msk      (0xFFUL << FMC_PATT_ATTHOLD_Pos)           /*!< 0x00FF0000 */

+#define FMC_PATT_ATTHOLD          FMC_PATT_ATTHOLD_Msk                       /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */

+#define FMC_PATT_ATTHOLD_0        (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */

+#define FMC_PATT_ATTHOLD_1        (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */

+#define FMC_PATT_ATTHOLD_2        (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */

+#define FMC_PATT_ATTHOLD_3        (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */

+#define FMC_PATT_ATTHOLD_4        (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */

+#define FMC_PATT_ATTHOLD_5        (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */

+#define FMC_PATT_ATTHOLD_6        (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */

+#define FMC_PATT_ATTHOLD_7        (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */

+

+#define FMC_PATT_ATTHIZ_Pos       (24U)

+#define FMC_PATT_ATTHIZ_Msk       (0xFFUL << FMC_PATT_ATTHIZ_Pos)            /*!< 0xFF000000 */

+#define FMC_PATT_ATTHIZ           FMC_PATT_ATTHIZ_Msk                        /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */

+#define FMC_PATT_ATTHIZ_0         (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */

+#define FMC_PATT_ATTHIZ_1         (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */

+#define FMC_PATT_ATTHIZ_2         (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */

+#define FMC_PATT_ATTHIZ_3         (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */

+#define FMC_PATT_ATTHIZ_4         (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */

+#define FMC_PATT_ATTHIZ_5         (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */

+#define FMC_PATT_ATTHIZ_6         (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */

+#define FMC_PATT_ATTHIZ_7         (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */

+

+/******************  Bit definition for FMC_ECCR3 register  ******************/

+#define FMC_ECCR3_ECC3_Pos         (0U)

+#define FMC_ECCR3_ECC3_Msk         (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)        /*!< 0xFFFFFFFF */

+#define FMC_ECCR3_ECC3             FMC_ECCR3_ECC3_Msk                          /*!<ECC result */

+

+/******************  Bit definition for FMC_SDCRx registers (x=1..4)  *********/

+#define FMC_SDCRx_NC_Pos           (0U)

+#define FMC_SDCRx_NC_Msk           (0x3UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000003 */

+#define FMC_SDCRx_NC               FMC_SDCRx_NC_Msk                            /*!<NC[1:0] bits (Number of column bits) */

+#define FMC_SDCRx_NC_0             (0x1UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000001 */

+#define FMC_SDCRx_NC_1             (0x2UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000002 */

+

+#define FMC_SDCRx_NR_Pos           (2U)

+#define FMC_SDCRx_NR_Msk           (0x3UL << FMC_SDCRx_NR_Pos)                 /*!< 0x0000000C */

+#define FMC_SDCRx_NR               FMC_SDCRx_NR_Msk                            /*!<NR[1:0] bits (Number of row bits) */

+#define FMC_SDCRx_NR_0             (0x1UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000004 */

+#define FMC_SDCRx_NR_1             (0x2UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000008 */

+

+#define FMC_SDCRx_MWID_Pos         (4U)

+#define FMC_SDCRx_MWID_Msk         (0x3UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000030 */

+#define FMC_SDCRx_MWID             FMC_SDCRx_MWID_Msk                          /*!<NR[1:0] bits (Number of row bits) */

+#define FMC_SDCRx_MWID_0           (0x1UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000010 */

+#define FMC_SDCRx_MWID_1           (0x2UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000020 */

+

+#define FMC_SDCRx_NB_Pos           (6U)

+#define FMC_SDCRx_NB_Msk           (0x1UL << FMC_SDCRx_NB_Pos)                 /*!< 0x00000040 */

+#define FMC_SDCRx_NB               FMC_SDCRx_NB_Msk                            /*!<Number of internal bank */

+

+#define FMC_SDCRx_CAS_Pos          (7U)

+#define FMC_SDCRx_CAS_Msk          (0x3UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000180 */

+#define FMC_SDCRx_CAS              FMC_SDCRx_CAS_Msk                           /*!<CAS[1:0] bits (CAS latency) */

+#define FMC_SDCRx_CAS_0            (0x1UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000080 */

+#define FMC_SDCRx_CAS_1            (0x2UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000100 */

+

+#define FMC_SDCRx_WP_Pos           (9U)

+#define FMC_SDCRx_WP_Msk           (0x1UL << FMC_SDCRx_WP_Pos)                 /*!< 0x00000200 */

+#define FMC_SDCRx_WP               FMC_SDCRx_WP_Msk                            /*!<Write protection */

+

+#define FMC_SDCRx_SDCLK_Pos        (10U)

+#define FMC_SDCRx_SDCLK_Msk        (0x3UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000C00 */

+#define FMC_SDCRx_SDCLK            FMC_SDCRx_SDCLK_Msk                         /*!<SDRAM clock configuration */

+#define FMC_SDCRx_SDCLK_0          (0x1UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000400 */

+#define FMC_SDCRx_SDCLK_1          (0x2UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000800 */

+

+#define FMC_SDCRx_RBURST_Pos       (12U)

+#define FMC_SDCRx_RBURST_Msk       (0x1UL << FMC_SDCRx_RBURST_Pos)             /*!< 0x00001000 */

+#define FMC_SDCRx_RBURST           FMC_SDCRx_RBURST_Msk                        /*!<Read burst */

+

+#define FMC_SDCRx_RPIPE_Pos        (13U)

+#define FMC_SDCRx_RPIPE_Msk        (0x3UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00006000 */

+#define FMC_SDCRx_RPIPE            FMC_SDCRx_RPIPE_Msk                         /*!<Write protection */

+#define FMC_SDCRx_RPIPE_0          (0x1UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00002000 */

+#define FMC_SDCRx_RPIPE_1          (0x2UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00004000 */

+

+/******************  Bit definition for FMC_SDTRx(1,2) register  ******************/

+#define FMC_SDTRx_TMRD_Pos         (0U)

+#define FMC_SDTRx_TMRD_Msk         (0xFUL << FMC_SDTRx_TMRD_Pos)               /*!< 0x0000000F */

+#define FMC_SDTRx_TMRD             FMC_SDTRx_TMRD_Msk                          /*!<TMRD[3:0] bits (Load mode register to active) */

+#define FMC_SDTRx_TMRD_0           (0x1UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000001 */

+#define FMC_SDTRx_TMRD_1           (0x2UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000002 */

+#define FMC_SDTRx_TMRD_2           (0x4UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000004 */

+#define FMC_SDTRx_TMRD_3           (0x8UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000008 */

+

+#define FMC_SDTRx_TXSR_Pos         (4U)

+#define FMC_SDTRx_TXSR_Msk         (0xFUL << FMC_SDTRx_TXSR_Pos)               /*!< 0x000000F0 */

+#define FMC_SDTRx_TXSR             FMC_SDTRx_TXSR_Msk                          /*!<TXSR[3:0] bits (Exit self refresh) */

+#define FMC_SDTRx_TXSR_0           (0x1UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000010 */

+#define FMC_SDTRx_TXSR_1           (0x2UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000020 */

+#define FMC_SDTRx_TXSR_2           (0x4UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000040 */

+#define FMC_SDTRx_TXSR_3           (0x8UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000080 */

+

+#define FMC_SDTRx_TRAS_Pos         (8U)

+#define FMC_SDTRx_TRAS_Msk         (0xFUL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000F00 */

+#define FMC_SDTRx_TRAS             FMC_SDTRx_TRAS_Msk                          /*!<TRAS[3:0] bits (Self refresh time) */

+#define FMC_SDTRx_TRAS_0           (0x1UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000100 */

+#define FMC_SDTRx_TRAS_1           (0x2UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000200 */

+#define FMC_SDTRx_TRAS_2           (0x4UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000400 */

+#define FMC_SDTRx_TRAS_3           (0x8UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000800 */

+

+#define FMC_SDTRx_TRC_Pos          (12U)

+#define FMC_SDTRx_TRC_Msk          (0xFUL << FMC_SDTRx_TRC_Pos)                /*!< 0x0000F000 */

+#define FMC_SDTRx_TRC              FMC_SDTRx_TRC_Msk                           /*!<TRC[2:0] bits (Row cycle delay) */

+#define FMC_SDTRx_TRC_0            (0x1UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00001000 */

+#define FMC_SDTRx_TRC_1            (0x2UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00002000 */

+#define FMC_SDTRx_TRC_2            (0x4UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00004000 */

+

+#define FMC_SDTRx_TWR_Pos          (16U)

+#define FMC_SDTRx_TWR_Msk          (0xFUL << FMC_SDTRx_TWR_Pos)                /*!< 0x000F0000 */

+#define FMC_SDTRx_TWR              FMC_SDTRx_TWR_Msk                           /*!<TRC[2:0] bits (Write recovery delay) */

+#define FMC_SDTRx_TWR_0            (0x1UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00010000 */

+#define FMC_SDTRx_TWR_1            (0x2UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00020000 */

+#define FMC_SDTRx_TWR_2            (0x4UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00040000 */

+

+#define FMC_SDTRx_TRP_Pos          (20U)

+#define FMC_SDTRx_TRP_Msk          (0xFUL << FMC_SDTRx_TRP_Pos)                /*!< 0x00F00000 */

+#define FMC_SDTRx_TRP              FMC_SDTRx_TRP_Msk                           /*!<TRP[2:0] bits (Row precharge delay) */

+#define FMC_SDTRx_TRP_0            (0x1UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00100000 */

+#define FMC_SDTRx_TRP_1            (0x2UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00200000 */

+#define FMC_SDTRx_TRP_2            (0x4UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00400000 */

+

+#define FMC_SDTRx_TRCD_Pos         (24U)

+#define FMC_SDTRx_TRCD_Msk         (0xFUL << FMC_SDTRx_TRCD_Pos)               /*!< 0x0F000000 */

+#define FMC_SDTRx_TRCD             FMC_SDTRx_TRCD_Msk                          /*!<TRP[2:0] bits (Row to column delay) */

+#define FMC_SDTRx_TRCD_0           (0x1UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x01000000 */

+#define FMC_SDTRx_TRCD_1           (0x2UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x02000000 */

+#define FMC_SDTRx_TRCD_2           (0x4UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x04000000 */

+

+/******************  Bit definition for FMC_SDCMR register  ******************/

+#define FMC_SDCMR_MODE_Pos         (0U)

+#define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */

+#define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */

+#define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */

+#define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */

+#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */

+

+#define FMC_SDCMR_CTB2_Pos         (3U)

+#define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */

+#define FMC_SDCMR_CTB2             FMC_SDCMR_CTB2_Msk                          /*!<Command target 2 */

+

+#define FMC_SDCMR_CTB1_Pos         (4U)

+#define FMC_SDCMR_CTB1_Msk         (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */

+#define FMC_SDCMR_CTB1             FMC_SDCMR_CTB1_Msk                          /*!<Command target 1 */

+

+#define FMC_SDCMR_NRFS_Pos         (5U)

+#define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */

+#define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!<NRFS[3:0] bits (Number of auto-refresh) */

+#define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000020 */

+#define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000040 */

+#define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000080 */

+#define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000100 */

+

+#define FMC_SDCMR_MRD_Pos          (9U)

+#define FMC_SDCMR_MRD_Msk          (0x1FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */

+#define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!<MRD[12:0] bits (Mode register definition) */

+

+/******************  Bit definition for FMC_SDRTR register  ******************/

+#define FMC_SDRTR_CRE_Pos          (0U)

+#define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */

+#define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!<Clear refresh error flag */

+

+#define FMC_SDRTR_COUNT_Pos        (1U)

+#define FMC_SDRTR_COUNT_Msk        (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */

+#define FMC_SDRTR_COUNT            FMC_SDRTR_COUNT_Msk                         /*!<COUNT[12:0] bits (Refresh timer count) */

+

+#define FMC_SDRTR_REIE_Pos         (14U)

+#define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */

+#define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!<RES interupt enable */

+

+/******************  Bit definition for FMC_SDSR register  ******************/

+#define FMC_SDSR_RE_Pos            (0U)

+#define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */

+#define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!<Refresh error flag */

+

+#define FMC_SDSR_MODES1_Pos        (1U)

+#define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */

+#define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!<MODES1[1:0]bits (Status mode for bank 1) */

+#define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000002 */

+#define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000004 */

+

+#define FMC_SDSR_MODES2_Pos        (3U)

+#define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */

+#define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!<MODES2[1:0]bits (Status mode for bank 2) */

+#define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000008 */

+#define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000010 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            General Purpose I/O                             */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bits definition for GPIO_MODER register  *****************/

+#define GPIO_MODER_MODE0_Pos           (0U)

+#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */

+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk

+#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */

+#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */

+

+#define GPIO_MODER_MODE1_Pos           (2U)

+#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */

+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk

+#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */

+#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */

+

+#define GPIO_MODER_MODE2_Pos           (4U)

+#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */

+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk

+#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */

+#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */

+

+#define GPIO_MODER_MODE3_Pos           (6U)

+#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */

+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk

+#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */

+#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */

+

+#define GPIO_MODER_MODE4_Pos           (8U)

+#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */

+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk

+#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */

+#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */

+

+#define GPIO_MODER_MODE5_Pos           (10U)

+#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */

+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk

+#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */

+#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */

+

+#define GPIO_MODER_MODE6_Pos           (12U)

+#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */

+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk

+#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */

+#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */

+

+#define GPIO_MODER_MODE7_Pos           (14U)

+#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */

+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk

+#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */

+#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */

+

+#define GPIO_MODER_MODE8_Pos           (16U)

+#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */

+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk

+#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */

+#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */

+

+#define GPIO_MODER_MODE9_Pos           (18U)

+#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */

+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk

+#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */

+#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */

+

+#define GPIO_MODER_MODE10_Pos          (20U)

+#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */

+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk

+#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */

+#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */

+

+#define GPIO_MODER_MODE11_Pos          (22U)

+#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */

+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk

+#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */

+#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */

+

+#define GPIO_MODER_MODE12_Pos          (24U)

+#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */

+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk

+#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */

+#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */

+

+#define GPIO_MODER_MODE13_Pos          (26U)

+#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */

+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk

+#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */

+#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */

+

+#define GPIO_MODER_MODE14_Pos          (28U)

+#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */

+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk

+#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */

+#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */

+

+#define GPIO_MODER_MODE15_Pos          (30U)

+#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */

+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk

+#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */

+#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_OTYPER register  ****************/

+#define GPIO_OTYPER_OT0_Pos            (0U)

+#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */

+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk

+#define GPIO_OTYPER_OT1_Pos            (1U)

+#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */

+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk

+#define GPIO_OTYPER_OT2_Pos            (2U)

+#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */

+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk

+#define GPIO_OTYPER_OT3_Pos            (3U)

+#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */

+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk

+#define GPIO_OTYPER_OT4_Pos            (4U)

+#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */

+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk

+#define GPIO_OTYPER_OT5_Pos            (5U)

+#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */

+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk

+#define GPIO_OTYPER_OT6_Pos            (6U)

+#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */

+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk

+#define GPIO_OTYPER_OT7_Pos            (7U)

+#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */

+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk

+#define GPIO_OTYPER_OT8_Pos            (8U)

+#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */

+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk

+#define GPIO_OTYPER_OT9_Pos            (9U)

+#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */

+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk

+#define GPIO_OTYPER_OT10_Pos           (10U)

+#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */

+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk

+#define GPIO_OTYPER_OT11_Pos           (11U)

+#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */

+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk

+#define GPIO_OTYPER_OT12_Pos           (12U)

+#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */

+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk

+#define GPIO_OTYPER_OT13_Pos           (13U)

+#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */

+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk

+#define GPIO_OTYPER_OT14_Pos           (14U)

+#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */

+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk

+#define GPIO_OTYPER_OT15_Pos           (15U)

+#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */

+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk

+

+/******************  Bits definition for GPIO_OSPEEDR register  ***************/

+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)

+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */

+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk

+#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */

+#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */

+

+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)

+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */

+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk

+#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */

+#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */

+

+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)

+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */

+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk

+#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */

+#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */

+

+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)

+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */

+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk

+#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */

+#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */

+

+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)

+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */

+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk

+#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */

+#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */

+

+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)

+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */

+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk

+#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */

+#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */

+

+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)

+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */

+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk

+#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */

+#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */

+

+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)

+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */

+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk

+#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */

+#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */

+

+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)

+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */

+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk

+#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */

+#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */

+

+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)

+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */

+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk

+#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */

+#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */

+

+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)

+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */

+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk

+#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */

+#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */

+

+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)

+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */

+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk

+#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */

+#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */

+

+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)

+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */

+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk

+#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */

+#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */

+

+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)

+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */

+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk

+#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */

+#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */

+

+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)

+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */

+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk

+#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */

+#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */

+

+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)

+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */

+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk

+#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */

+#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_PUPDR register  *****************/

+#define GPIO_PUPDR_PUPD0_Pos           (0U)

+#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */

+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk

+#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */

+#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */

+

+#define GPIO_PUPDR_PUPD1_Pos           (2U)

+#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */

+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk

+#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */

+#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */

+

+#define GPIO_PUPDR_PUPD2_Pos           (4U)

+#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */

+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk

+#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */

+#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */

+

+#define GPIO_PUPDR_PUPD3_Pos           (6U)

+#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */

+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk

+#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */

+#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */

+

+#define GPIO_PUPDR_PUPD4_Pos           (8U)

+#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */

+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk

+#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */

+#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */

+

+#define GPIO_PUPDR_PUPD5_Pos           (10U)

+#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */

+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk

+#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */

+#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */

+

+#define GPIO_PUPDR_PUPD6_Pos           (12U)

+#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */

+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk

+#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */

+#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */

+

+#define GPIO_PUPDR_PUPD7_Pos           (14U)

+#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */

+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk

+#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */

+#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */

+

+#define GPIO_PUPDR_PUPD8_Pos           (16U)

+#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */

+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk

+#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */

+#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */

+

+#define GPIO_PUPDR_PUPD9_Pos           (18U)

+#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */

+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk

+#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */

+#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */

+

+#define GPIO_PUPDR_PUPD10_Pos          (20U)

+#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */

+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk

+#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */

+#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */

+

+#define GPIO_PUPDR_PUPD11_Pos          (22U)

+#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */

+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk

+#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */

+#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */

+

+#define GPIO_PUPDR_PUPD12_Pos          (24U)

+#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */

+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk

+#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */

+#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */

+

+#define GPIO_PUPDR_PUPD13_Pos          (26U)

+#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */

+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk

+#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */

+#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */

+

+#define GPIO_PUPDR_PUPD14_Pos          (28U)

+#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */

+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk

+#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */

+#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */

+

+#define GPIO_PUPDR_PUPD15_Pos          (30U)

+#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */

+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk

+#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */

+#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_IDR register  *******************/

+#define GPIO_IDR_ID0_Pos               (0U)

+#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */

+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk

+#define GPIO_IDR_ID1_Pos               (1U)

+#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */

+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk

+#define GPIO_IDR_ID2_Pos               (2U)

+#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */

+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk

+#define GPIO_IDR_ID3_Pos               (3U)

+#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */

+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk

+#define GPIO_IDR_ID4_Pos               (4U)

+#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */

+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk

+#define GPIO_IDR_ID5_Pos               (5U)

+#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */

+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk

+#define GPIO_IDR_ID6_Pos               (6U)

+#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */

+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk

+#define GPIO_IDR_ID7_Pos               (7U)

+#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */

+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk

+#define GPIO_IDR_ID8_Pos               (8U)

+#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */

+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk

+#define GPIO_IDR_ID9_Pos               (9U)

+#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */

+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk

+#define GPIO_IDR_ID10_Pos              (10U)

+#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */

+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk

+#define GPIO_IDR_ID11_Pos              (11U)

+#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */

+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk

+#define GPIO_IDR_ID12_Pos              (12U)

+#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */

+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk

+#define GPIO_IDR_ID13_Pos              (13U)

+#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */

+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk

+#define GPIO_IDR_ID14_Pos              (14U)

+#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */

+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk

+#define GPIO_IDR_ID15_Pos              (15U)

+#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */

+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk

+

+/******************  Bits definition for GPIO_ODR register  *******************/

+#define GPIO_ODR_OD0_Pos               (0U)

+#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */

+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk

+#define GPIO_ODR_OD1_Pos               (1U)

+#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */

+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk

+#define GPIO_ODR_OD2_Pos               (2U)

+#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */

+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk

+#define GPIO_ODR_OD3_Pos               (3U)

+#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */

+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk

+#define GPIO_ODR_OD4_Pos               (4U)

+#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */

+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk

+#define GPIO_ODR_OD5_Pos               (5U)

+#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */

+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk

+#define GPIO_ODR_OD6_Pos               (6U)

+#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */

+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk

+#define GPIO_ODR_OD7_Pos               (7U)

+#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */

+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk

+#define GPIO_ODR_OD8_Pos               (8U)

+#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */

+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk

+#define GPIO_ODR_OD9_Pos               (9U)

+#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */

+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk

+#define GPIO_ODR_OD10_Pos              (10U)

+#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */

+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk

+#define GPIO_ODR_OD11_Pos              (11U)

+#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */

+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk

+#define GPIO_ODR_OD12_Pos              (12U)

+#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */

+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk

+#define GPIO_ODR_OD13_Pos              (13U)

+#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */

+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk

+#define GPIO_ODR_OD14_Pos              (14U)

+#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */

+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk

+#define GPIO_ODR_OD15_Pos              (15U)

+#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */

+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk

+

+/******************  Bits definition for GPIO_BSRR register  ******************/

+#define GPIO_BSRR_BS0_Pos              (0U)

+#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */

+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk

+#define GPIO_BSRR_BS1_Pos              (1U)

+#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */

+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk

+#define GPIO_BSRR_BS2_Pos              (2U)

+#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */

+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk

+#define GPIO_BSRR_BS3_Pos              (3U)

+#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */

+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk

+#define GPIO_BSRR_BS4_Pos              (4U)

+#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */

+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk

+#define GPIO_BSRR_BS5_Pos              (5U)

+#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */

+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk

+#define GPIO_BSRR_BS6_Pos              (6U)

+#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */

+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk

+#define GPIO_BSRR_BS7_Pos              (7U)

+#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */

+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk

+#define GPIO_BSRR_BS8_Pos              (8U)

+#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */

+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk

+#define GPIO_BSRR_BS9_Pos              (9U)

+#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */

+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk

+#define GPIO_BSRR_BS10_Pos             (10U)

+#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */

+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk

+#define GPIO_BSRR_BS11_Pos             (11U)

+#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */

+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk

+#define GPIO_BSRR_BS12_Pos             (12U)

+#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */

+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk

+#define GPIO_BSRR_BS13_Pos             (13U)

+#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */

+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk

+#define GPIO_BSRR_BS14_Pos             (14U)

+#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */

+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk

+#define GPIO_BSRR_BS15_Pos             (15U)

+#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */

+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk

+#define GPIO_BSRR_BR0_Pos              (16U)

+#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */

+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk

+#define GPIO_BSRR_BR1_Pos              (17U)

+#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */

+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk

+#define GPIO_BSRR_BR2_Pos              (18U)

+#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */

+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk

+#define GPIO_BSRR_BR3_Pos              (19U)

+#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */

+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk

+#define GPIO_BSRR_BR4_Pos              (20U)

+#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */

+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk

+#define GPIO_BSRR_BR5_Pos              (21U)

+#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */

+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk

+#define GPIO_BSRR_BR6_Pos              (22U)

+#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */

+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk

+#define GPIO_BSRR_BR7_Pos              (23U)

+#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */

+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk

+#define GPIO_BSRR_BR8_Pos              (24U)

+#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */

+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk

+#define GPIO_BSRR_BR9_Pos              (25U)

+#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */

+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk

+#define GPIO_BSRR_BR10_Pos             (26U)

+#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */

+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk

+#define GPIO_BSRR_BR11_Pos             (27U)

+#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */

+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk

+#define GPIO_BSRR_BR12_Pos             (28U)

+#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */

+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk

+#define GPIO_BSRR_BR13_Pos             (29U)

+#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */

+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk

+#define GPIO_BSRR_BR14_Pos             (30U)

+#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */

+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk

+#define GPIO_BSRR_BR15_Pos             (31U)

+#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */

+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk

+

+/****************** Bit definition for GPIO_LCKR register *********************/

+#define GPIO_LCKR_LCK0_Pos             (0U)

+#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */

+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk

+#define GPIO_LCKR_LCK1_Pos             (1U)

+#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */

+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk

+#define GPIO_LCKR_LCK2_Pos             (2U)

+#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */

+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk

+#define GPIO_LCKR_LCK3_Pos             (3U)

+#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */

+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk

+#define GPIO_LCKR_LCK4_Pos             (4U)

+#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */

+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk

+#define GPIO_LCKR_LCK5_Pos             (5U)

+#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */

+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk

+#define GPIO_LCKR_LCK6_Pos             (6U)

+#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */

+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk

+#define GPIO_LCKR_LCK7_Pos             (7U)

+#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */

+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk

+#define GPIO_LCKR_LCK8_Pos             (8U)

+#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */

+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk

+#define GPIO_LCKR_LCK9_Pos             (9U)

+#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */

+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk

+#define GPIO_LCKR_LCK10_Pos            (10U)

+#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */

+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk

+#define GPIO_LCKR_LCK11_Pos            (11U)

+#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */

+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk

+#define GPIO_LCKR_LCK12_Pos            (12U)

+#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */

+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk

+#define GPIO_LCKR_LCK13_Pos            (13U)

+#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */

+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk

+#define GPIO_LCKR_LCK14_Pos            (14U)

+#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */

+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk

+#define GPIO_LCKR_LCK15_Pos            (15U)

+#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */

+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk

+#define GPIO_LCKR_LCKK_Pos             (16U)

+#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */

+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk

+

+/****************** Bit definition for GPIO_AFRL register  ********************/

+#define GPIO_AFRL_AFSEL0_Pos           (0U)

+#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */

+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk

+#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */

+#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */

+#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */

+#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */

+#define GPIO_AFRL_AFSEL1_Pos           (4U)

+#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */

+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk

+#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */

+#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */

+#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */

+#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */

+#define GPIO_AFRL_AFSEL2_Pos           (8U)

+#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */

+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk

+#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */

+#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */

+#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */

+#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */

+#define GPIO_AFRL_AFSEL3_Pos           (12U)

+#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */

+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk

+#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */

+#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */

+#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */

+#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */

+#define GPIO_AFRL_AFSEL4_Pos           (16U)

+#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */

+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk

+#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */

+#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */

+#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */

+#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */

+#define GPIO_AFRL_AFSEL5_Pos           (20U)

+#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */

+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk

+#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */

+#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */

+#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */

+#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */

+#define GPIO_AFRL_AFSEL6_Pos           (24U)

+#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */

+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk

+#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */

+#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */

+#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */

+#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */

+#define GPIO_AFRL_AFSEL7_Pos           (28U)

+#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */

+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk

+#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */

+#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */

+#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */

+#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */

+

+/* Legacy defines */

+#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0

+#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1

+#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2

+#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3

+#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4

+#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5

+#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6

+#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7

+

+/****************** Bit definition for GPIO_AFRH register  ********************/

+#define GPIO_AFRH_AFSEL8_Pos           (0U)

+#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */

+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk

+#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */

+#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */

+#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */

+#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */

+#define GPIO_AFRH_AFSEL9_Pos           (4U)

+#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */

+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk

+#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */

+#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */

+#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */

+#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */

+#define GPIO_AFRH_AFSEL10_Pos          (8U)

+#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */

+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk

+#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */

+#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */

+#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */

+#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */

+#define GPIO_AFRH_AFSEL11_Pos          (12U)

+#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */

+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk

+#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */

+#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */

+#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */

+#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */

+#define GPIO_AFRH_AFSEL12_Pos          (16U)

+#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */

+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk

+#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */

+#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */

+#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */

+#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */

+#define GPIO_AFRH_AFSEL13_Pos          (20U)

+#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */

+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk

+#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */

+#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */

+#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */

+#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */

+#define GPIO_AFRH_AFSEL14_Pos          (24U)

+#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */

+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk

+#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */

+#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */

+#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */

+#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */

+#define GPIO_AFRH_AFSEL15_Pos          (28U)

+#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */

+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk

+#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */

+#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */

+#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */

+#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */

+

+/* Legacy defines */

+#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8

+#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9

+#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10

+#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11

+#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12

+#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13

+#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14

+#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15

+

+/******************************************************************************/

+/*                                                                            */

+/*                        HSEM HW Semaphore                                   */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for HSEM_R register  ********************/

+#define HSEM_R_PROCID_Pos         (0U)

+#define HSEM_R_PROCID_Msk         (0xFFUL << HSEM_R_PROCID_Pos)                /*!< 0x000000FF */

+#define HSEM_R_PROCID             HSEM_R_PROCID_Msk                            /*!<Semaphore ProcessID */

+#define HSEM_R_COREID_Pos         (8U)

+#define HSEM_R_COREID_Msk         (0xFFUL << HSEM_R_COREID_Pos)                /*!< 0x0000FF00 */

+#define HSEM_R_COREID             HSEM_R_COREID_Msk                            /*!<Semaphore CoreID.   */

+#define HSEM_R_LOCK_Pos           (31U)

+#define HSEM_R_LOCK_Msk           (0x1UL << HSEM_R_LOCK_Pos)                   /*!< 0x80000000 */

+#define HSEM_R_LOCK               HSEM_R_LOCK_Msk                              /*!<Lock indication.    */

+

+/********************  Bit definition for HSEM_RLR register  ******************/

+#define HSEM_RLR_PROCID_Pos       (0U)

+#define HSEM_RLR_PROCID_Msk       (0xFFUL << HSEM_RLR_PROCID_Pos)              /*!< 0x000000FF */

+#define HSEM_RLR_PROCID           HSEM_RLR_PROCID_Msk                          /*!<Semaphore ProcessID */

+#define HSEM_RLR_COREID_Pos       (8U)

+#define HSEM_RLR_COREID_Msk       (0xFFUL << HSEM_RLR_COREID_Pos)              /*!< 0x0000FF00 */

+#define HSEM_RLR_COREID           HSEM_RLR_COREID_Msk                          /*!<Semaphore CoreID.   */

+#define HSEM_RLR_LOCK_Pos         (31U)

+#define HSEM_RLR_LOCK_Msk         (0x1UL << HSEM_RLR_LOCK_Pos)                 /*!< 0x80000000 */

+#define HSEM_RLR_LOCK             HSEM_RLR_LOCK_Msk                            /*!<Lock indication.    */

+

+/********************  Bit definition for HSEM_C1IER register  *****************/

+#define HSEM_C1IER_ISE0_Pos       (0U)

+#define HSEM_C1IER_ISE0_Msk       (0x1UL << HSEM_C1IER_ISE0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1IER_ISE0           HSEM_C1IER_ISE0_Msk                          /*!<semaphore 0 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE1_Pos       (1U)

+#define HSEM_C1IER_ISE1_Msk       (0x1UL << HSEM_C1IER_ISE1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1IER_ISE1           HSEM_C1IER_ISE1_Msk                          /*!<semaphore 1 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE2_Pos       (2U)

+#define HSEM_C1IER_ISE2_Msk       (0x1UL << HSEM_C1IER_ISE2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1IER_ISE2           HSEM_C1IER_ISE2_Msk                          /*!<semaphore 2 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE3_Pos       (3U)

+#define HSEM_C1IER_ISE3_Msk       (0x1UL << HSEM_C1IER_ISE3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1IER_ISE3           HSEM_C1IER_ISE3_Msk                          /*!<semaphore 3 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE4_Pos       (4U)

+#define HSEM_C1IER_ISE4_Msk       (0x1UL << HSEM_C1IER_ISE4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1IER_ISE4           HSEM_C1IER_ISE4_Msk                          /*!<semaphore 4 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE5_Pos       (5U)

+#define HSEM_C1IER_ISE5_Msk       (0x1UL << HSEM_C1IER_ISE5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1IER_ISE5           HSEM_C1IER_ISE5_Msk                          /*!<semaphore 5 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE6_Pos       (6U)

+#define HSEM_C1IER_ISE6_Msk       (0x1UL << HSEM_C1IER_ISE6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1IER_ISE6           HSEM_C1IER_ISE6_Msk                          /*!<semaphore 6 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE7_Pos       (7U)

+#define HSEM_C1IER_ISE7_Msk       (0x1UL << HSEM_C1IER_ISE7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1IER_ISE7           HSEM_C1IER_ISE7_Msk                          /*!<semaphore 7 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE8_Pos       (8U)

+#define HSEM_C1IER_ISE8_Msk       (0x1UL << HSEM_C1IER_ISE8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1IER_ISE8           HSEM_C1IER_ISE8_Msk                          /*!<semaphore 8 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE9_Pos       (9U)

+#define HSEM_C1IER_ISE9_Msk       (0x1UL << HSEM_C1IER_ISE9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1IER_ISE9           HSEM_C1IER_ISE9_Msk                          /*!<semaphore 9 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE10_Pos      (10U)

+#define HSEM_C1IER_ISE10_Msk      (0x1UL << HSEM_C1IER_ISE10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1IER_ISE10          HSEM_C1IER_ISE10_Msk                         /*!<semaphore 10 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE11_Pos      (11U)

+#define HSEM_C1IER_ISE11_Msk      (0x1UL << HSEM_C1IER_ISE11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1IER_ISE11          HSEM_C1IER_ISE11_Msk                         /*!<semaphore 11 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE12_Pos      (12U)

+#define HSEM_C1IER_ISE12_Msk      (0x1UL << HSEM_C1IER_ISE12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1IER_ISE12          HSEM_C1IER_ISE12_Msk                         /*!<semaphore 12 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE13_Pos      (13U)

+#define HSEM_C1IER_ISE13_Msk      (0x1UL << HSEM_C1IER_ISE13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1IER_ISE13          HSEM_C1IER_ISE13_Msk                         /*!<semaphore 13 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE14_Pos      (14U)

+#define HSEM_C1IER_ISE14_Msk      (0x1UL << HSEM_C1IER_ISE14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1IER_ISE14          HSEM_C1IER_ISE14_Msk                         /*!<semaphore 14 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE15_Pos      (15U)

+#define HSEM_C1IER_ISE15_Msk      (0x1UL << HSEM_C1IER_ISE15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1IER_ISE15          HSEM_C1IER_ISE15_Msk                         /*!<semaphore 15 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE16_Pos      (16U)

+#define HSEM_C1IER_ISE16_Msk      (0x1UL << HSEM_C1IER_ISE16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1IER_ISE16          HSEM_C1IER_ISE16_Msk                         /*!<semaphore 16 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE17_Pos      (17U)

+#define HSEM_C1IER_ISE17_Msk      (0x1UL << HSEM_C1IER_ISE17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1IER_ISE17          HSEM_C1IER_ISE17_Msk                         /*!<semaphore 17 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE18_Pos      (18U)

+#define HSEM_C1IER_ISE18_Msk      (0x1UL << HSEM_C1IER_ISE18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1IER_ISE18          HSEM_C1IER_ISE18_Msk                         /*!<semaphore 18 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE19_Pos      (19U)

+#define HSEM_C1IER_ISE19_Msk      (0x1UL << HSEM_C1IER_ISE19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1IER_ISE19          HSEM_C1IER_ISE19_Msk                         /*!<semaphore 19 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE20_Pos      (20U)

+#define HSEM_C1IER_ISE20_Msk      (0x1UL << HSEM_C1IER_ISE20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1IER_ISE20          HSEM_C1IER_ISE20_Msk                         /*!<semaphore 20 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE21_Pos      (21U)

+#define HSEM_C1IER_ISE21_Msk      (0x1UL << HSEM_C1IER_ISE21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1IER_ISE21          HSEM_C1IER_ISE21_Msk                         /*!<semaphore 21 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE22_Pos      (22U)

+#define HSEM_C1IER_ISE22_Msk      (0x1UL << HSEM_C1IER_ISE22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1IER_ISE22          HSEM_C1IER_ISE22_Msk                         /*!<semaphore 22 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE23_Pos      (23U)

+#define HSEM_C1IER_ISE23_Msk      (0x1UL << HSEM_C1IER_ISE23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1IER_ISE23          HSEM_C1IER_ISE23_Msk                         /*!<semaphore 23 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE24_Pos      (24U)

+#define HSEM_C1IER_ISE24_Msk      (0x1UL << HSEM_C1IER_ISE24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1IER_ISE24          HSEM_C1IER_ISE24_Msk                         /*!<semaphore 24 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE25_Pos      (25U)

+#define HSEM_C1IER_ISE25_Msk      (0x1UL << HSEM_C1IER_ISE25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1IER_ISE25          HSEM_C1IER_ISE25_Msk                         /*!<semaphore 25 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE26_Pos      (26U)

+#define HSEM_C1IER_ISE26_Msk      (0x1UL << HSEM_C1IER_ISE26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1IER_ISE26          HSEM_C1IER_ISE26_Msk                         /*!<semaphore 26 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE27_Pos      (27U)

+#define HSEM_C1IER_ISE27_Msk      (0x1UL << HSEM_C1IER_ISE27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1IER_ISE27          HSEM_C1IER_ISE27_Msk                         /*!<semaphore 27 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE28_Pos      (28U)

+#define HSEM_C1IER_ISE28_Msk      (0x1UL << HSEM_C1IER_ISE28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1IER_ISE28          HSEM_C1IER_ISE28_Msk                         /*!<semaphore 28 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE29_Pos      (29U)

+#define HSEM_C1IER_ISE29_Msk      (0x1UL << HSEM_C1IER_ISE29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1IER_ISE29          HSEM_C1IER_ISE29_Msk                         /*!<semaphore 29 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE30_Pos      (30U)

+#define HSEM_C1IER_ISE30_Msk      (0x1UL << HSEM_C1IER_ISE30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1IER_ISE30          HSEM_C1IER_ISE30_Msk                         /*!<semaphore 30 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE31_Pos      (31U)

+#define HSEM_C1IER_ISE31_Msk      (0x1UL << HSEM_C1IER_ISE31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1IER_ISE31          HSEM_C1IER_ISE31_Msk                         /*!<semaphore 31 interrupt 0 enable bit. */

+

+/********************  Bit definition for HSEM_C1ICR register  *****************/

+#define HSEM_C1ICR_ISC0_Pos       (0U)

+#define HSEM_C1ICR_ISC0_Msk       (0x1UL << HSEM_C1ICR_ISC0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1ICR_ISC0           HSEM_C1ICR_ISC0_Msk                          /*!<semaphore 0 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC1_Pos       (1U)

+#define HSEM_C1ICR_ISC1_Msk       (0x1UL << HSEM_C1ICR_ISC1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1ICR_ISC1           HSEM_C1ICR_ISC1_Msk                          /*!<semaphore 1 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC2_Pos       (2U)

+#define HSEM_C1ICR_ISC2_Msk       (0x1UL << HSEM_C1ICR_ISC2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1ICR_ISC2           HSEM_C1ICR_ISC2_Msk                          /*!<semaphore 2 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC3_Pos       (3U)

+#define HSEM_C1ICR_ISC3_Msk       (0x1UL << HSEM_C1ICR_ISC3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1ICR_ISC3           HSEM_C1ICR_ISC3_Msk                          /*!<semaphore 3 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC4_Pos       (4U)

+#define HSEM_C1ICR_ISC4_Msk       (0x1UL << HSEM_C1ICR_ISC4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1ICR_ISC4           HSEM_C1ICR_ISC4_Msk                          /*!<semaphore 4 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC5_Pos       (5U)

+#define HSEM_C1ICR_ISC5_Msk       (0x1UL << HSEM_C1ICR_ISC5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1ICR_ISC5           HSEM_C1ICR_ISC5_Msk                          /*!<semaphore 5 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC6_Pos       (6U)

+#define HSEM_C1ICR_ISC6_Msk       (0x1UL << HSEM_C1ICR_ISC6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1ICR_ISC6           HSEM_C1ICR_ISC6_Msk                          /*!<semaphore 6 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC7_Pos       (7U)

+#define HSEM_C1ICR_ISC7_Msk       (0x1UL << HSEM_C1ICR_ISC7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1ICR_ISC7           HSEM_C1ICR_ISC7_Msk                          /*!<semaphore 7 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC8_Pos       (8U)

+#define HSEM_C1ICR_ISC8_Msk       (0x1UL << HSEM_C1ICR_ISC8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1ICR_ISC8           HSEM_C1ICR_ISC8_Msk                          /*!<semaphore 8 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC9_Pos       (9U)

+#define HSEM_C1ICR_ISC9_Msk       (0x1UL << HSEM_C1ICR_ISC9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1ICR_ISC9           HSEM_C1ICR_ISC9_Msk                          /*!<semaphore 9 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC10_Pos      (10U)

+#define HSEM_C1ICR_ISC10_Msk      (0x1UL << HSEM_C1ICR_ISC10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1ICR_ISC10          HSEM_C1ICR_ISC10_Msk                         /*!<semaphore 10 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC11_Pos      (11U)

+#define HSEM_C1ICR_ISC11_Msk      (0x1UL << HSEM_C1ICR_ISC11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1ICR_ISC11          HSEM_C1ICR_ISC11_Msk                         /*!<semaphore 11 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC12_Pos      (12U)

+#define HSEM_C1ICR_ISC12_Msk      (0x1UL << HSEM_C1ICR_ISC12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1ICR_ISC12          HSEM_C1ICR_ISC12_Msk                         /*!<semaphore 12 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC13_Pos      (13U)

+#define HSEM_C1ICR_ISC13_Msk      (0x1UL << HSEM_C1ICR_ISC13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1ICR_ISC13          HSEM_C1ICR_ISC13_Msk                         /*!<semaphore 13 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC14_Pos      (14U)

+#define HSEM_C1ICR_ISC14_Msk      (0x1UL << HSEM_C1ICR_ISC14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1ICR_ISC14          HSEM_C1ICR_ISC14_Msk                         /*!<semaphore 14 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC15_Pos      (15U)

+#define HSEM_C1ICR_ISC15_Msk      (0x1UL << HSEM_C1ICR_ISC15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1ICR_ISC15          HSEM_C1ICR_ISC15_Msk                         /*!<semaphore 15 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC16_Pos      (16U)

+#define HSEM_C1ICR_ISC16_Msk      (0x1UL << HSEM_C1ICR_ISC16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1ICR_ISC16          HSEM_C1ICR_ISC16_Msk                         /*!<semaphore 16 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC17_Pos      (17U)

+#define HSEM_C1ICR_ISC17_Msk      (0x1UL << HSEM_C1ICR_ISC17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1ICR_ISC17          HSEM_C1ICR_ISC17_Msk                         /*!<semaphore 17 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC18_Pos      (18U)

+#define HSEM_C1ICR_ISC18_Msk      (0x1UL << HSEM_C1ICR_ISC18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1ICR_ISC18          HSEM_C1ICR_ISC18_Msk                         /*!<semaphore 18 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC19_Pos      (19U)

+#define HSEM_C1ICR_ISC19_Msk      (0x1UL << HSEM_C1ICR_ISC19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1ICR_ISC19          HSEM_C1ICR_ISC19_Msk                         /*!<semaphore 19 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC20_Pos      (20U)

+#define HSEM_C1ICR_ISC20_Msk      (0x1UL << HSEM_C1ICR_ISC20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1ICR_ISC20          HSEM_C1ICR_ISC20_Msk                         /*!<semaphore 20 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC21_Pos      (21U)

+#define HSEM_C1ICR_ISC21_Msk      (0x1UL << HSEM_C1ICR_ISC21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1ICR_ISC21          HSEM_C1ICR_ISC21_Msk                         /*!<semaphore 21 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC22_Pos      (22U)

+#define HSEM_C1ICR_ISC22_Msk      (0x1UL << HSEM_C1ICR_ISC22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1ICR_ISC22          HSEM_C1ICR_ISC22_Msk                         /*!<semaphore 22 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC23_Pos      (23U)

+#define HSEM_C1ICR_ISC23_Msk      (0x1UL << HSEM_C1ICR_ISC23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1ICR_ISC23          HSEM_C1ICR_ISC23_Msk                         /*!<semaphore 23 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC24_Pos      (24U)

+#define HSEM_C1ICR_ISC24_Msk      (0x1UL << HSEM_C1ICR_ISC24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1ICR_ISC24          HSEM_C1ICR_ISC24_Msk                         /*!<semaphore 24 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC25_Pos      (25U)

+#define HSEM_C1ICR_ISC25_Msk      (0x1UL << HSEM_C1ICR_ISC25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1ICR_ISC25          HSEM_C1ICR_ISC25_Msk                         /*!<semaphore 25 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC26_Pos      (26U)

+#define HSEM_C1ICR_ISC26_Msk      (0x1UL << HSEM_C1ICR_ISC26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1ICR_ISC26          HSEM_C1ICR_ISC26_Msk                         /*!<semaphore 26 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC27_Pos      (27U)

+#define HSEM_C1ICR_ISC27_Msk      (0x1UL << HSEM_C1ICR_ISC27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1ICR_ISC27          HSEM_C1ICR_ISC27_Msk                         /*!<semaphore 27 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC28_Pos      (28U)

+#define HSEM_C1ICR_ISC28_Msk      (0x1UL << HSEM_C1ICR_ISC28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1ICR_ISC28          HSEM_C1ICR_ISC28_Msk                         /*!<semaphore 28 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC29_Pos      (29U)

+#define HSEM_C1ICR_ISC29_Msk      (0x1UL << HSEM_C1ICR_ISC29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1ICR_ISC29          HSEM_C1ICR_ISC29_Msk                         /*!<semaphore 29 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC30_Pos      (30U)

+#define HSEM_C1ICR_ISC30_Msk      (0x1UL << HSEM_C1ICR_ISC30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1ICR_ISC30          HSEM_C1ICR_ISC30_Msk                         /*!<semaphore 30 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC31_Pos      (31U)

+#define HSEM_C1ICR_ISC31_Msk      (0x1UL << HSEM_C1ICR_ISC31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1ICR_ISC31          HSEM_C1ICR_ISC31_Msk                         /*!<semaphore 31 interrupt 0 clear bit. */

+

+/********************  Bit definition for HSEM_C1ISR register  *****************/

+#define HSEM_C1ISR_ISF0_Pos       (0U)

+#define HSEM_C1ISR_ISF0_Msk       (0x1UL << HSEM_C1ISR_ISF0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1ISR_ISF0           HSEM_C1ISR_ISF0_Msk                          /*!<semaphore 0 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF1_Pos       (1U)

+#define HSEM_C1ISR_ISF1_Msk       (0x1UL << HSEM_C1ISR_ISF1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1ISR_ISF1           HSEM_C1ISR_ISF1_Msk                          /*!<semaphore 1 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF2_Pos       (2U)

+#define HSEM_C1ISR_ISF2_Msk       (0x1UL << HSEM_C1ISR_ISF2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1ISR_ISF2           HSEM_C1ISR_ISF2_Msk                          /*!<semaphore 2 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF3_Pos       (3U)

+#define HSEM_C1ISR_ISF3_Msk       (0x1UL << HSEM_C1ISR_ISF3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1ISR_ISF3           HSEM_C1ISR_ISF3_Msk                          /*!<semaphore 3 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF4_Pos       (4U)

+#define HSEM_C1ISR_ISF4_Msk       (0x1UL << HSEM_C1ISR_ISF4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1ISR_ISF4           HSEM_C1ISR_ISF4_Msk                          /*!<semaphore 4 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF5_Pos       (5U)

+#define HSEM_C1ISR_ISF5_Msk       (0x1UL << HSEM_C1ISR_ISF5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1ISR_ISF5           HSEM_C1ISR_ISF5_Msk                          /*!<semaphore 5 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF6_Pos       (6U)

+#define HSEM_C1ISR_ISF6_Msk       (0x1UL << HSEM_C1ISR_ISF6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1ISR_ISF6           HSEM_C1ISR_ISF6_Msk                          /*!<semaphore 6 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF7_Pos       (7U)

+#define HSEM_C1ISR_ISF7_Msk       (0x1UL << HSEM_C1ISR_ISF7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1ISR_ISF7           HSEM_C1ISR_ISF7_Msk                          /*!<semaphore 7 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF8_Pos       (8U)

+#define HSEM_C1ISR_ISF8_Msk       (0x1UL << HSEM_C1ISR_ISF8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1ISR_ISF8           HSEM_C1ISR_ISF8_Msk                          /*!<semaphore 8 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF9_Pos       (9U)

+#define HSEM_C1ISR_ISF9_Msk       (0x1UL << HSEM_C1ISR_ISF9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1ISR_ISF9           HSEM_C1ISR_ISF9_Msk                          /*!<semaphore 9 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF10_Pos      (10U)

+#define HSEM_C1ISR_ISF10_Msk      (0x1UL << HSEM_C1ISR_ISF10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1ISR_ISF10          HSEM_C1ISR_ISF10_Msk                         /*!<semaphore 10 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF11_Pos      (11U)

+#define HSEM_C1ISR_ISF11_Msk      (0x1UL << HSEM_C1ISR_ISF11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1ISR_ISF11          HSEM_C1ISR_ISF11_Msk                         /*!<semaphore 11 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF12_Pos      (12U)

+#define HSEM_C1ISR_ISF12_Msk      (0x1UL << HSEM_C1ISR_ISF12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1ISR_ISF12          HSEM_C1ISR_ISF12_Msk                         /*!<semaphore 12 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF13_Pos      (13U)

+#define HSEM_C1ISR_ISF13_Msk      (0x1UL << HSEM_C1ISR_ISF13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1ISR_ISF13          HSEM_C1ISR_ISF13_Msk                         /*!<semaphore 13 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF14_Pos      (14U)

+#define HSEM_C1ISR_ISF14_Msk      (0x1UL << HSEM_C1ISR_ISF14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1ISR_ISF14          HSEM_C1ISR_ISF14_Msk                         /*!<semaphore 14 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF15_Pos      (15U)

+#define HSEM_C1ISR_ISF15_Msk      (0x1UL << HSEM_C1ISR_ISF15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1ISR_ISF15          HSEM_C1ISR_ISF15_Msk                         /*!<semaphore 15 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF16_Pos      (16U)

+#define HSEM_C1ISR_ISF16_Msk      (0x1UL << HSEM_C1ISR_ISF16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1ISR_ISF16          HSEM_C1ISR_ISF16_Msk                         /*!<semaphore 16 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF17_Pos      (17U)

+#define HSEM_C1ISR_ISF17_Msk      (0x1UL << HSEM_C1ISR_ISF17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1ISR_ISF17          HSEM_C1ISR_ISF17_Msk                         /*!<semaphore 17 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF18_Pos      (18U)

+#define HSEM_C1ISR_ISF18_Msk      (0x1UL << HSEM_C1ISR_ISF18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1ISR_ISF18          HSEM_C1ISR_ISF18_Msk                         /*!<semaphore 18 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF19_Pos      (19U)

+#define HSEM_C1ISR_ISF19_Msk      (0x1UL << HSEM_C1ISR_ISF19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1ISR_ISF19          HSEM_C1ISR_ISF19_Msk                         /*!<semaphore 19 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF20_Pos      (20U)

+#define HSEM_C1ISR_ISF20_Msk      (0x1UL << HSEM_C1ISR_ISF20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1ISR_ISF20          HSEM_C1ISR_ISF20_Msk                         /*!<semaphore 20 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF21_Pos      (21U)

+#define HSEM_C1ISR_ISF21_Msk      (0x1UL << HSEM_C1ISR_ISF21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1ISR_ISF21          HSEM_C1ISR_ISF21_Msk                         /*!<semaphore 21 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF22_Pos      (22U)

+#define HSEM_C1ISR_ISF22_Msk      (0x1UL << HSEM_C1ISR_ISF22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1ISR_ISF22          HSEM_C1ISR_ISF22_Msk                         /*!<semaphore 22 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF23_Pos      (23U)

+#define HSEM_C1ISR_ISF23_Msk      (0x1UL << HSEM_C1ISR_ISF23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1ISR_ISF23          HSEM_C1ISR_ISF23_Msk                         /*!<semaphore 23 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF24_Pos      (24U)

+#define HSEM_C1ISR_ISF24_Msk      (0x1UL << HSEM_C1ISR_ISF24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1ISR_ISF24          HSEM_C1ISR_ISF24_Msk                         /*!<semaphore 24 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF25_Pos      (25U)

+#define HSEM_C1ISR_ISF25_Msk      (0x1UL << HSEM_C1ISR_ISF25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1ISR_ISF25          HSEM_C1ISR_ISF25_Msk                         /*!<semaphore 25 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF26_Pos      (26U)

+#define HSEM_C1ISR_ISF26_Msk      (0x1UL << HSEM_C1ISR_ISF26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1ISR_ISF26          HSEM_C1ISR_ISF26_Msk                         /*!<semaphore 26 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF27_Pos      (27U)

+#define HSEM_C1ISR_ISF27_Msk      (0x1UL << HSEM_C1ISR_ISF27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1ISR_ISF27          HSEM_C1ISR_ISF27_Msk                         /*!<semaphore 27 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF28_Pos      (28U)

+#define HSEM_C1ISR_ISF28_Msk      (0x1UL << HSEM_C1ISR_ISF28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1ISR_ISF28          HSEM_C1ISR_ISF28_Msk                         /*!<semaphore 28 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF29_Pos      (29U)

+#define HSEM_C1ISR_ISF29_Msk      (0x1UL << HSEM_C1ISR_ISF29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1ISR_ISF29          HSEM_C1ISR_ISF29_Msk                         /*!<semaphore 29 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF30_Pos      (30U)

+#define HSEM_C1ISR_ISF30_Msk      (0x1UL << HSEM_C1ISR_ISF30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1ISR_ISF30          HSEM_C1ISR_ISF30_Msk                         /*!<semaphore 30 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF31_Pos      (31U)

+#define HSEM_C1ISR_ISF31_Msk      (0x1UL << HSEM_C1ISR_ISF31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1ISR_ISF31          HSEM_C1ISR_ISF31_Msk                         /*!<semaphore 31 interrupt 0 status bit. */

+

+/********************  Bit definition for HSEM_C1MISR register  *****************/

+#define HSEM_C1MISR_MISF0_Pos     (0U)

+#define HSEM_C1MISR_MISF0_Msk     (0x1UL << HSEM_C1MISR_MISF0_Pos)             /*!< 0x00000001 */

+#define HSEM_C1MISR_MISF0         HSEM_C1MISR_MISF0_Msk                        /*!<semaphore 0 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF1_Pos     (1U)

+#define HSEM_C1MISR_MISF1_Msk     (0x1UL << HSEM_C1MISR_MISF1_Pos)             /*!< 0x00000002 */

+#define HSEM_C1MISR_MISF1         HSEM_C1MISR_MISF1_Msk                        /*!<semaphore 1 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF2_Pos     (2U)

+#define HSEM_C1MISR_MISF2_Msk     (0x1UL << HSEM_C1MISR_MISF2_Pos)             /*!< 0x00000004 */

+#define HSEM_C1MISR_MISF2         HSEM_C1MISR_MISF2_Msk                        /*!<semaphore 2 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF3_Pos     (3U)

+#define HSEM_C1MISR_MISF3_Msk     (0x1UL << HSEM_C1MISR_MISF3_Pos)             /*!< 0x00000008 */

+#define HSEM_C1MISR_MISF3         HSEM_C1MISR_MISF3_Msk                        /*!<semaphore 3 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF4_Pos     (4U)

+#define HSEM_C1MISR_MISF4_Msk     (0x1UL << HSEM_C1MISR_MISF4_Pos)             /*!< 0x00000010 */

+#define HSEM_C1MISR_MISF4         HSEM_C1MISR_MISF4_Msk                        /*!<semaphore 4 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF5_Pos     (5U)

+#define HSEM_C1MISR_MISF5_Msk     (0x1UL << HSEM_C1MISR_MISF5_Pos)             /*!< 0x00000020 */

+#define HSEM_C1MISR_MISF5         HSEM_C1MISR_MISF5_Msk                        /*!<semaphore 5 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF6_Pos     (6U)

+#define HSEM_C1MISR_MISF6_Msk     (0x1UL << HSEM_C1MISR_MISF6_Pos)             /*!< 0x00000040 */

+#define HSEM_C1MISR_MISF6         HSEM_C1MISR_MISF6_Msk                        /*!<semaphore 6 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF7_Pos     (7U)

+#define HSEM_C1MISR_MISF7_Msk     (0x1UL << HSEM_C1MISR_MISF7_Pos)             /*!< 0x00000080 */

+#define HSEM_C1MISR_MISF7         HSEM_C1MISR_MISF7_Msk                        /*!<semaphore 7 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF8_Pos     (8U)

+#define HSEM_C1MISR_MISF8_Msk     (0x1UL << HSEM_C1MISR_MISF8_Pos)             /*!< 0x00000100 */

+#define HSEM_C1MISR_MISF8         HSEM_C1MISR_MISF8_Msk                        /*!<semaphore 8 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF9_Pos     (9U)

+#define HSEM_C1MISR_MISF9_Msk     (0x1UL << HSEM_C1MISR_MISF9_Pos)             /*!< 0x00000200 */

+#define HSEM_C1MISR_MISF9         HSEM_C1MISR_MISF9_Msk                        /*!<semaphore 9 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF10_Pos    (10U)

+#define HSEM_C1MISR_MISF10_Msk    (0x1UL << HSEM_C1MISR_MISF10_Pos)            /*!< 0x00000400 */

+#define HSEM_C1MISR_MISF10        HSEM_C1MISR_MISF10_Msk                       /*!<semaphore 10 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF11_Pos    (11U)

+#define HSEM_C1MISR_MISF11_Msk    (0x1UL << HSEM_C1MISR_MISF11_Pos)            /*!< 0x00000800 */

+#define HSEM_C1MISR_MISF11        HSEM_C1MISR_MISF11_Msk                       /*!<semaphore 11 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF12_Pos    (12U)

+#define HSEM_C1MISR_MISF12_Msk    (0x1UL << HSEM_C1MISR_MISF12_Pos)            /*!< 0x00001000 */

+#define HSEM_C1MISR_MISF12        HSEM_C1MISR_MISF12_Msk                       /*!<semaphore 12 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF13_Pos    (13U)

+#define HSEM_C1MISR_MISF13_Msk    (0x1UL << HSEM_C1MISR_MISF13_Pos)            /*!< 0x00002000 */

+#define HSEM_C1MISR_MISF13        HSEM_C1MISR_MISF13_Msk                       /*!<semaphore 13 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF14_Pos    (14U)

+#define HSEM_C1MISR_MISF14_Msk    (0x1UL << HSEM_C1MISR_MISF14_Pos)            /*!< 0x00004000 */

+#define HSEM_C1MISR_MISF14        HSEM_C1MISR_MISF14_Msk                       /*!<semaphore 14 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF15_Pos    (15U)

+#define HSEM_C1MISR_MISF15_Msk    (0x1UL << HSEM_C1MISR_MISF15_Pos)            /*!< 0x00008000 */

+#define HSEM_C1MISR_MISF15        HSEM_C1MISR_MISF15_Msk                       /*!<semaphore 15 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF16_Pos    (16U)

+#define HSEM_C1MISR_MISF16_Msk    (0x1UL << HSEM_C1MISR_MISF16_Pos)            /*!< 0x00010000 */

+#define HSEM_C1MISR_MISF16        HSEM_C1MISR_MISF16_Msk                       /*!<semaphore 16 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF17_Pos    (17U)

+#define HSEM_C1MISR_MISF17_Msk    (0x1UL << HSEM_C1MISR_MISF17_Pos)            /*!< 0x00020000 */

+#define HSEM_C1MISR_MISF17        HSEM_C1MISR_MISF17_Msk                       /*!<semaphore 17 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF18_Pos    (18U)

+#define HSEM_C1MISR_MISF18_Msk    (0x1UL << HSEM_C1MISR_MISF18_Pos)            /*!< 0x00040000 */

+#define HSEM_C1MISR_MISF18        HSEM_C1MISR_MISF18_Msk                       /*!<semaphore 18 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF19_Pos    (19U)

+#define HSEM_C1MISR_MISF19_Msk    (0x1UL << HSEM_C1MISR_MISF19_Pos)            /*!< 0x00080000 */

+#define HSEM_C1MISR_MISF19        HSEM_C1MISR_MISF19_Msk                       /*!<semaphore 19 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF20_Pos    (20U)

+#define HSEM_C1MISR_MISF20_Msk    (0x1UL << HSEM_C1MISR_MISF20_Pos)            /*!< 0x00100000 */

+#define HSEM_C1MISR_MISF20        HSEM_C1MISR_MISF20_Msk                       /*!<semaphore 20 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF21_Pos    (21U)

+#define HSEM_C1MISR_MISF21_Msk    (0x1UL << HSEM_C1MISR_MISF21_Pos)            /*!< 0x00200000 */

+#define HSEM_C1MISR_MISF21        HSEM_C1MISR_MISF21_Msk                       /*!<semaphore 21 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF22_Pos    (22U)

+#define HSEM_C1MISR_MISF22_Msk    (0x1UL << HSEM_C1MISR_MISF22_Pos)            /*!< 0x00400000 */

+#define HSEM_C1MISR_MISF22        HSEM_C1MISR_MISF22_Msk                       /*!<semaphore 22 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF23_Pos    (23U)

+#define HSEM_C1MISR_MISF23_Msk    (0x1UL << HSEM_C1MISR_MISF23_Pos)            /*!< 0x00800000 */

+#define HSEM_C1MISR_MISF23        HSEM_C1MISR_MISF23_Msk                       /*!<semaphore 23 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF24_Pos    (24U)

+#define HSEM_C1MISR_MISF24_Msk    (0x1UL << HSEM_C1MISR_MISF24_Pos)            /*!< 0x01000000 */

+#define HSEM_C1MISR_MISF24        HSEM_C1MISR_MISF24_Msk                       /*!<semaphore 24 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF25_Pos    (25U)

+#define HSEM_C1MISR_MISF25_Msk    (0x1UL << HSEM_C1MISR_MISF25_Pos)            /*!< 0x02000000 */

+#define HSEM_C1MISR_MISF25        HSEM_C1MISR_MISF25_Msk                       /*!<semaphore 25 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF26_Pos    (26U)

+#define HSEM_C1MISR_MISF26_Msk    (0x1UL << HSEM_C1MISR_MISF26_Pos)            /*!< 0x04000000 */

+#define HSEM_C1MISR_MISF26        HSEM_C1MISR_MISF26_Msk                       /*!<semaphore 26 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF27_Pos    (27U)

+#define HSEM_C1MISR_MISF27_Msk    (0x1UL << HSEM_C1MISR_MISF27_Pos)            /*!< 0x08000000 */

+#define HSEM_C1MISR_MISF27        HSEM_C1MISR_MISF27_Msk                       /*!<semaphore 27 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF28_Pos    (28U)

+#define HSEM_C1MISR_MISF28_Msk    (0x1UL << HSEM_C1MISR_MISF28_Pos)            /*!< 0x10000000 */

+#define HSEM_C1MISR_MISF28        HSEM_C1MISR_MISF28_Msk                       /*!<semaphore 28 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF29_Pos    (29U)

+#define HSEM_C1MISR_MISF29_Msk    (0x1UL << HSEM_C1MISR_MISF29_Pos)            /*!< 0x20000000 */

+#define HSEM_C1MISR_MISF29        HSEM_C1MISR_MISF29_Msk                       /*!<semaphore 29 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF30_Pos    (30U)

+#define HSEM_C1MISR_MISF30_Msk    (0x1UL << HSEM_C1MISR_MISF30_Pos)            /*!< 0x40000000 */

+#define HSEM_C1MISR_MISF30        HSEM_C1MISR_MISF30_Msk                       /*!<semaphore 30 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF31_Pos    (31U)

+#define HSEM_C1MISR_MISF31_Msk    (0x1UL << HSEM_C1MISR_MISF31_Pos)            /*!< 0x80000000 */

+#define HSEM_C1MISR_MISF31        HSEM_C1MISR_MISF31_Msk                       /*!<semaphore 31 interrupt 0 masked status bit. */

+

+/********************  Bit definition for HSEM_CR register  *****************/

+#define HSEM_CR_COREID_Pos        (8U)

+#define HSEM_CR_COREID_Msk        (0xFFUL << HSEM_CR_COREID_Pos)               /*!< 0x0000FF00 */

+#define HSEM_CR_COREID            HSEM_CR_COREID_Msk                           /*!<CoreID of semaphores to be cleared. */

+#define HSEM_CR_KEY_Pos           (16U)

+#define HSEM_CR_KEY_Msk           (0xFFFFUL << HSEM_CR_KEY_Pos)                /*!< 0xFFFF0000 */

+#define HSEM_CR_KEY               HSEM_CR_KEY_Msk                              /*!<semaphores clear key. */

+

+/********************  Bit definition for HSEM_KEYR register  *****************/

+#define HSEM_KEYR_KEY_Pos         (16U)

+#define HSEM_KEYR_KEY_Msk         (0xFFFFUL << HSEM_KEYR_KEY_Pos)              /*!< 0xFFFF0000 */

+#define HSEM_KEYR_KEY             HSEM_KEYR_KEY_Msk                            /*!<semaphores clear key. */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      Inter-integrated Circuit Interface (I2C)              */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for I2C_CR1 register  *******************/

+#define I2C_CR1_PE_Pos               (0U)

+#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */

+#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */

+#define I2C_CR1_TXIE_Pos             (1U)

+#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */

+#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */

+#define I2C_CR1_RXIE_Pos             (2U)

+#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */

+#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */

+#define I2C_CR1_ADDRIE_Pos           (3U)

+#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */

+#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */

+#define I2C_CR1_NACKIE_Pos           (4U)

+#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */

+#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */

+#define I2C_CR1_STOPIE_Pos           (5U)

+#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */

+#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */

+#define I2C_CR1_TCIE_Pos             (6U)

+#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */

+#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */

+#define I2C_CR1_ERRIE_Pos            (7U)

+#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */

+#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */

+#define I2C_CR1_DNF_Pos              (8U)

+#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */

+#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */

+#define I2C_CR1_ANFOFF_Pos           (12U)

+#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */

+#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */

+#define I2C_CR1_TXDMAEN_Pos          (14U)

+#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */

+#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */

+#define I2C_CR1_RXDMAEN_Pos          (15U)

+#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */

+#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */

+#define I2C_CR1_SBC_Pos              (16U)

+#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */

+#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */

+#define I2C_CR1_NOSTRETCH_Pos        (17U)

+#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */

+#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */

+#define I2C_CR1_WUPEN_Pos            (18U)

+#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */

+#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */

+#define I2C_CR1_GCEN_Pos             (19U)

+#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */

+#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */

+#define I2C_CR1_SMBHEN_Pos           (20U)

+#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */

+#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */

+#define I2C_CR1_SMBDEN_Pos           (21U)

+#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */

+#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */

+#define I2C_CR1_ALERTEN_Pos          (22U)

+#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */

+#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */

+#define I2C_CR1_PECEN_Pos            (23U)

+#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */

+#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */

+

+/******************  Bit definition for I2C_CR2 register  ********************/

+#define I2C_CR2_SADD_Pos             (0U)

+#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */

+#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */

+#define I2C_CR2_RD_WRN_Pos           (10U)

+#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */

+#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */

+#define I2C_CR2_ADD10_Pos            (11U)

+#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */

+#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */

+#define I2C_CR2_HEAD10R_Pos          (12U)

+#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */

+#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */

+#define I2C_CR2_START_Pos            (13U)

+#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */

+#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */

+#define I2C_CR2_STOP_Pos             (14U)

+#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */

+#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */

+#define I2C_CR2_NACK_Pos             (15U)

+#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */

+#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */

+#define I2C_CR2_NBYTES_Pos           (16U)

+#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */

+#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */

+#define I2C_CR2_RELOAD_Pos           (24U)

+#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */

+#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */

+#define I2C_CR2_AUTOEND_Pos          (25U)

+#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */

+#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */

+#define I2C_CR2_PECBYTE_Pos          (26U)

+#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */

+#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */

+

+/*******************  Bit definition for I2C_OAR1 register  ******************/

+#define I2C_OAR1_OA1_Pos             (0U)

+#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */

+#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */

+#define I2C_OAR1_OA1MODE_Pos         (10U)

+#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */

+#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */

+#define I2C_OAR1_OA1EN_Pos           (15U)

+#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */

+#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */

+

+/*******************  Bit definition for I2C_OAR2 register  ******************/

+#define I2C_OAR2_OA2_Pos             (1U)

+#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */

+#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */

+#define I2C_OAR2_OA2MSK_Pos          (8U)

+#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */

+#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */

+#define I2C_OAR2_OA2NOMASK           0x00000000UL                              /*!< No mask */

+#define I2C_OAR2_OA2MASK01_Pos       (8U)

+#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */

+#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared */

+#define I2C_OAR2_OA2MASK02_Pos       (9U)

+#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */

+#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */

+#define I2C_OAR2_OA2MASK03_Pos       (8U)

+#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */

+#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */

+#define I2C_OAR2_OA2MASK04_Pos       (10U)

+#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */

+#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */

+#define I2C_OAR2_OA2MASK05_Pos       (8U)

+#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */

+#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */

+#define I2C_OAR2_OA2MASK06_Pos       (9U)

+#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */

+#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared */

+#define I2C_OAR2_OA2MASK07_Pos       (8U)

+#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */

+#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done */

+#define I2C_OAR2_OA2EN_Pos           (15U)

+#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */

+#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */

+

+/*******************  Bit definition for I2C_TIMINGR register *******************/

+#define I2C_TIMINGR_SCLL_Pos         (0U)

+#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */

+#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */

+#define I2C_TIMINGR_SCLH_Pos         (8U)

+#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */

+#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */

+#define I2C_TIMINGR_SDADEL_Pos       (16U)

+#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */

+#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */

+#define I2C_TIMINGR_SCLDEL_Pos       (20U)

+#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */

+#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */

+#define I2C_TIMINGR_PRESC_Pos        (28U)

+#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */

+#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */

+

+/******************* Bit definition for I2C_TIMEOUTR register *******************/

+#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)

+#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */

+#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */

+#define I2C_TIMEOUTR_TIDLE_Pos       (12U)

+#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */

+#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */

+#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)

+#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */

+#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */

+#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)

+#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */

+#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/

+#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)

+#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */

+#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */

+

+/******************  Bit definition for I2C_ISR register  *********************/

+#define I2C_ISR_TXE_Pos              (0U)

+#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */

+#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */

+#define I2C_ISR_TXIS_Pos             (1U)

+#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */

+#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */

+#define I2C_ISR_RXNE_Pos             (2U)

+#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */

+#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */

+#define I2C_ISR_ADDR_Pos             (3U)

+#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */

+#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/

+#define I2C_ISR_NACKF_Pos            (4U)

+#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */

+#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */

+#define I2C_ISR_STOPF_Pos            (5U)

+#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */

+#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */

+#define I2C_ISR_TC_Pos               (6U)

+#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */

+#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */

+#define I2C_ISR_TCR_Pos              (7U)

+#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */

+#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */

+#define I2C_ISR_BERR_Pos             (8U)

+#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */

+#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */

+#define I2C_ISR_ARLO_Pos             (9U)

+#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */

+#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */

+#define I2C_ISR_OVR_Pos              (10U)

+#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */

+#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */

+#define I2C_ISR_PECERR_Pos           (11U)

+#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */

+#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */

+#define I2C_ISR_TIMEOUT_Pos          (12U)

+#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */

+#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */

+#define I2C_ISR_ALERT_Pos            (13U)

+#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */

+#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */

+#define I2C_ISR_BUSY_Pos             (15U)

+#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */

+#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */

+#define I2C_ISR_DIR_Pos              (16U)

+#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */

+#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */

+#define I2C_ISR_ADDCODE_Pos          (17U)

+#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */

+#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */

+

+/******************  Bit definition for I2C_ICR register  *********************/

+#define I2C_ICR_ADDRCF_Pos           (3U)

+#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */

+#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */

+#define I2C_ICR_NACKCF_Pos           (4U)

+#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */

+#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */

+#define I2C_ICR_STOPCF_Pos           (5U)

+#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */

+#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */

+#define I2C_ICR_BERRCF_Pos           (8U)

+#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */

+#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */

+#define I2C_ICR_ARLOCF_Pos           (9U)

+#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */

+#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */

+#define I2C_ICR_OVRCF_Pos            (10U)

+#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */

+#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */

+#define I2C_ICR_PECCF_Pos            (11U)

+#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */

+#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */

+#define I2C_ICR_TIMOUTCF_Pos         (12U)

+#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */

+#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */

+#define I2C_ICR_ALERTCF_Pos          (13U)

+#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */

+#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */

+

+/******************  Bit definition for I2C_PECR register  *********************/

+#define I2C_PECR_PEC_Pos             (0U)

+#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */

+#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */

+

+/******************  Bit definition for I2C_RXDR register  *********************/

+#define I2C_RXDR_RXDATA_Pos          (0U)

+#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */

+#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */

+

+/******************  Bit definition for I2C_TXDR register  *********************/

+#define I2C_TXDR_TXDATA_Pos          (0U)

+#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */

+#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           Independent WATCHDOG                             */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for IWDG_KR register  ********************/

+#define IWDG_KR_KEY_Pos      (0U)

+#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */

+#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */

+

+/*******************  Bit definition for IWDG_PR register  ********************/

+#define IWDG_PR_PR_Pos       (0U)

+#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */

+#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */

+#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */

+#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */

+#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */

+

+/*******************  Bit definition for IWDG_RLR register  *******************/

+#define IWDG_RLR_RL_Pos      (0U)

+#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */

+#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */

+

+/*******************  Bit definition for IWDG_SR register  ********************/

+#define IWDG_SR_PVU_Pos      (0U)

+#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */

+#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */

+#define IWDG_SR_RVU_Pos      (1U)

+#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */

+#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */

+#define IWDG_SR_WVU_Pos      (2U)

+#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */

+#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */

+

+/*******************  Bit definition for IWDG_KR register  ********************/

+#define IWDG_WINR_WIN_Pos    (0U)

+#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */

+#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */

+

+/******************************************************************************/

+/*                                                                            */

+/*                        JPEG Encoder/Decoder                                */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for CONFR0 register  ********************/

+#define JPEG_CONFR0_START_Pos           (0U)

+#define JPEG_CONFR0_START_Msk           (0x1UL << JPEG_CONFR0_START_Pos)       /*!< 0x00000001 */

+#define JPEG_CONFR0_START               JPEG_CONFR0_START_Msk                  /*!<Start/Stop bit */

+

+/********************  Bit definition for CONFR1 register  ********************/

+#define JPEG_CONFR1_NF_Pos              (0U)

+#define JPEG_CONFR1_NF_Msk              (0x3UL << JPEG_CONFR1_NF_Pos)          /*!< 0x00000003 */

+#define JPEG_CONFR1_NF                  JPEG_CONFR1_NF_Msk                     /*!<Number of color components */

+#define JPEG_CONFR1_NF_0                (0x1UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000001 */

+#define JPEG_CONFR1_NF_1                (0x2UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000002 */

+#define JPEG_CONFR1_DE_Pos              (3U)

+#define JPEG_CONFR1_DE_Msk              (0x1UL << JPEG_CONFR1_DE_Pos)          /*!< 0x00000008 */

+#define JPEG_CONFR1_DE                  JPEG_CONFR1_DE_Msk                     /*!<Decoding Enable */

+#define JPEG_CONFR1_COLORSPACE_Pos      (4U)

+#define JPEG_CONFR1_COLORSPACE_Msk      (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)  /*!< 0x00000030 */

+#define JPEG_CONFR1_COLORSPACE          JPEG_CONFR1_COLORSPACE_Msk             /*!<Color Space */

+#define JPEG_CONFR1_COLORSPACE_0        (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000010 */

+#define JPEG_CONFR1_COLORSPACE_1        (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000020 */

+#define JPEG_CONFR1_NS_Pos              (6U)

+#define JPEG_CONFR1_NS_Msk              (0x3UL << JPEG_CONFR1_NS_Pos)          /*!< 0x000000C0 */

+#define JPEG_CONFR1_NS                  JPEG_CONFR1_NS_Msk                     /*!<Number of components for Scan */

+#define JPEG_CONFR1_NS_0                (0x1UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR1_NS_1                (0x2UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR1_HDR_Pos             (8U)

+#define JPEG_CONFR1_HDR_Msk             (0x1UL << JPEG_CONFR1_HDR_Pos)         /*!< 0x00000100 */

+#define JPEG_CONFR1_HDR                 JPEG_CONFR1_HDR_Msk                    /*!<Header Processing On/Off */

+#define JPEG_CONFR1_YSIZE_Pos           (16U)

+#define JPEG_CONFR1_YSIZE_Msk           (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)    /*!< 0xFFFF0000 */

+#define JPEG_CONFR1_YSIZE               JPEG_CONFR1_YSIZE_Msk                  /*!<Number of lines in source image */

+

+/********************  Bit definition for CONFR2 register  ********************/

+#define JPEG_CONFR2_NMCU_Pos            (0U)

+#define JPEG_CONFR2_NMCU_Msk            (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)  /*!< 0x03FFFFFF */

+#define JPEG_CONFR2_NMCU                JPEG_CONFR2_NMCU_Msk                   /*!<Number of MCU units minus 1 to encode */

+

+/********************  Bit definition for CONFR3 register  ********************/

+#define JPEG_CONFR3_XSIZE_Pos           (16U)

+#define JPEG_CONFR3_XSIZE_Msk           (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)    /*!< 0xFFFF0000 */

+#define JPEG_CONFR3_XSIZE               JPEG_CONFR3_XSIZE_Msk                  /*!<Number of pixels per line */

+

+/********************  Bit definition for CONFR4 register  ********************/

+#define JPEG_CONFR4_HD_Pos              (0U)

+#define JPEG_CONFR4_HD_Msk              (0x1UL << JPEG_CONFR4_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR4_HD                  JPEG_CONFR4_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR4_HA_Pos              (1U)

+#define JPEG_CONFR4_HA_Msk              (0x1UL << JPEG_CONFR4_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR4_HA                  JPEG_CONFR4_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR4_QT_Pos              (2U)

+#define JPEG_CONFR4_QT_Msk              (0x3UL << JPEG_CONFR4_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR4_QT                  JPEG_CONFR4_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR4_QT_0                (0x1UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR4_QT_1                (0x2UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR4_NB_Pos              (4U)

+#define JPEG_CONFR4_NB_Msk              (0xFUL << JPEG_CONFR4_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR4_NB                  JPEG_CONFR4_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR4_NB_0                (0x1UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR4_NB_1                (0x2UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR4_NB_2                (0x4UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR4_NB_3                (0x8UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR4_VSF_Pos             (8U)

+#define JPEG_CONFR4_VSF_Msk             (0xFUL << JPEG_CONFR4_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR4_VSF                 JPEG_CONFR4_VSF_Msk                    /*!<Vertical sampling factor for component 1 */

+#define JPEG_CONFR4_VSF_0               (0x1UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR4_VSF_1               (0x2UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR4_VSF_2               (0x4UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR4_VSF_3               (0x8UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR4_HSF_Pos             (12U)

+#define JPEG_CONFR4_HSF_Msk             (0xFUL << JPEG_CONFR4_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR4_HSF                 JPEG_CONFR4_HSF_Msk                    /*!<Horizontal sampling factor for component 1 */

+#define JPEG_CONFR4_HSF_0               (0x1UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR4_HSF_1               (0x2UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR4_HSF_2               (0x4UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR4_HSF_3               (0x8UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR5 register  ********************/

+#define JPEG_CONFR5_HD_Pos              (0U)

+#define JPEG_CONFR5_HD_Msk              (0x1UL << JPEG_CONFR5_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR5_HD                  JPEG_CONFR5_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR5_HA_Pos              (1U)

+#define JPEG_CONFR5_HA_Msk              (0x1UL << JPEG_CONFR5_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR5_HA                  JPEG_CONFR5_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR5_QT_Pos              (2U)

+#define JPEG_CONFR5_QT_Msk              (0x3UL << JPEG_CONFR5_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR5_QT                  JPEG_CONFR5_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR5_QT_0                (0x1UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR5_QT_1                (0x2UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR5_NB_Pos              (4U)

+#define JPEG_CONFR5_NB_Msk              (0xFUL << JPEG_CONFR5_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR5_NB                  JPEG_CONFR5_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR5_NB_0                (0x1UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR5_NB_1                (0x2UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR5_NB_2                (0x4UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR5_NB_3                (0x8UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR5_VSF_Pos             (8U)

+#define JPEG_CONFR5_VSF_Msk             (0xFUL << JPEG_CONFR5_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR5_VSF                 JPEG_CONFR5_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR5_VSF_0               (0x1UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR5_VSF_1               (0x2UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR5_VSF_2               (0x4UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR5_VSF_3               (0x8UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR5_HSF_Pos             (12U)

+#define JPEG_CONFR5_HSF_Msk             (0xFUL << JPEG_CONFR5_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR5_HSF                 JPEG_CONFR5_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR5_HSF_0               (0x1UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR5_HSF_1               (0x2UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR5_HSF_2               (0x4UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR5_HSF_3               (0x8UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR6 register  ********************/

+#define JPEG_CONFR6_HD_Pos              (0U)

+#define JPEG_CONFR6_HD_Msk              (0x1UL << JPEG_CONFR6_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR6_HD                  JPEG_CONFR6_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR6_HA_Pos              (1U)

+#define JPEG_CONFR6_HA_Msk              (0x1UL << JPEG_CONFR6_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR6_HA                  JPEG_CONFR6_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR6_QT_Pos              (2U)

+#define JPEG_CONFR6_QT_Msk              (0x3UL << JPEG_CONFR6_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR6_QT                  JPEG_CONFR6_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR6_QT_0                (0x1UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR6_QT_1                (0x2UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR6_NB_Pos              (4U)

+#define JPEG_CONFR6_NB_Msk              (0xFUL << JPEG_CONFR6_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR6_NB                  JPEG_CONFR6_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR6_NB_0                (0x1UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR6_NB_1                (0x2UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR6_NB_2                (0x4UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR6_NB_3                (0x8UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR6_VSF_Pos             (8U)

+#define JPEG_CONFR6_VSF_Msk             (0xFUL << JPEG_CONFR6_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR6_VSF                 JPEG_CONFR6_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR6_VSF_0               (0x1UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR6_VSF_1               (0x2UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR6_VSF_2               (0x4UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR6_VSF_3               (0x8UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR6_HSF_Pos             (12U)

+#define JPEG_CONFR6_HSF_Msk             (0xFUL << JPEG_CONFR6_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR6_HSF                 JPEG_CONFR6_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR6_HSF_0               (0x1UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR6_HSF_1               (0x2UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR6_HSF_2               (0x4UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR6_HSF_3               (0x8UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR7 register  ********************/

+#define JPEG_CONFR7_HD_Pos              (0U)

+#define JPEG_CONFR7_HD_Msk              (0x1UL << JPEG_CONFR7_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR7_HD                  JPEG_CONFR7_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR7_HA_Pos              (1U)

+#define JPEG_CONFR7_HA_Msk              (0x1UL << JPEG_CONFR7_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR7_HA                  JPEG_CONFR7_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR7_QT_Pos              (2U)

+#define JPEG_CONFR7_QT_Msk              (0x3UL << JPEG_CONFR7_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR7_QT                  JPEG_CONFR7_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR7_QT_0                (0x1UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR7_QT_1                (0x2UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR7_NB_Pos              (4U)

+#define JPEG_CONFR7_NB_Msk              (0xFUL << JPEG_CONFR7_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR7_NB                  JPEG_CONFR7_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR7_NB_0                (0x1UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR7_NB_1                (0x2UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR7_NB_2                (0x4UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR7_NB_3                (0x8UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR7_VSF_Pos             (8U)

+#define JPEG_CONFR7_VSF_Msk             (0xFUL << JPEG_CONFR7_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR7_VSF                 JPEG_CONFR7_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR7_VSF_0               (0x1UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR7_VSF_1               (0x2UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR7_VSF_2               (0x4UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR7_VSF_3               (0x8UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR7_HSF_Pos             (12U)

+#define JPEG_CONFR7_HSF_Msk             (0xFUL << JPEG_CONFR7_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR7_HSF                 JPEG_CONFR7_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR7_HSF_0               (0x1UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR7_HSF_1               (0x2UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR7_HSF_2               (0x4UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR7_HSF_3               (0x8UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CR register  ********************/

+#define JPEG_CR_JCEN_Pos                (0U)

+#define JPEG_CR_JCEN_Msk                (0x1UL << JPEG_CR_JCEN_Pos)            /*!< 0x00000001 */

+#define JPEG_CR_JCEN                    JPEG_CR_JCEN_Msk                       /*!<Enable the JPEG Codec Core */

+#define JPEG_CR_IFTIE_Pos               (1U)

+#define JPEG_CR_IFTIE_Msk               (0x1UL << JPEG_CR_IFTIE_Pos)           /*!< 0x00000002 */

+#define JPEG_CR_IFTIE                   JPEG_CR_IFTIE_Msk                      /*!<Input FIFO Threshold Interrupt Enable */

+#define JPEG_CR_IFNFIE_Pos              (2U)

+#define JPEG_CR_IFNFIE_Msk              (0x1UL << JPEG_CR_IFNFIE_Pos)          /*!< 0x00000004 */

+#define JPEG_CR_IFNFIE                  JPEG_CR_IFNFIE_Msk                     /*!<Input FIFO Not Full Interrupt Enable */

+#define JPEG_CR_OFTIE_Pos               (3U)

+#define JPEG_CR_OFTIE_Msk               (0x1UL << JPEG_CR_OFTIE_Pos)           /*!< 0x00000008 */

+#define JPEG_CR_OFTIE                   JPEG_CR_OFTIE_Msk                      /*!<Output FIFO Threshold Interrupt Enable */

+#define JPEG_CR_OFNEIE_Pos              (4U)

+#define JPEG_CR_OFNEIE_Msk              (0x1UL << JPEG_CR_OFNEIE_Pos)          /*!< 0x00000010 */

+#define JPEG_CR_OFNEIE                  JPEG_CR_OFNEIE_Msk                     /*!<Output FIFO Not Empty Interrupt Enable */

+#define JPEG_CR_EOCIE_Pos               (5U)

+#define JPEG_CR_EOCIE_Msk               (0x1UL << JPEG_CR_EOCIE_Pos)           /*!< 0x00000020 */

+#define JPEG_CR_EOCIE                   JPEG_CR_EOCIE_Msk                      /*!<End of Conversion Interrupt Enable */

+#define JPEG_CR_HPDIE_Pos               (6U)

+#define JPEG_CR_HPDIE_Msk               (0x1UL << JPEG_CR_HPDIE_Pos)           /*!< 0x00000040 */

+#define JPEG_CR_HPDIE                   JPEG_CR_HPDIE_Msk                      /*!<Header Parsing Done Interrupt Enable */

+#define JPEG_CR_IFF_Pos                 (13U)

+#define JPEG_CR_IFF_Msk                 (0x1UL << JPEG_CR_IFF_Pos)             /*!< 0x00002000 */

+#define JPEG_CR_IFF                     JPEG_CR_IFF_Msk                        /*!<Flush the input FIFO */

+#define JPEG_CR_OFF_Pos                 (14U)

+#define JPEG_CR_OFF_Msk                 (0x1UL << JPEG_CR_OFF_Pos)             /*!< 0x00004000 */

+#define JPEG_CR_OFF                     JPEG_CR_OFF_Msk                        /*!<Flush the output FIFO */

+

+/********************  Bit definition for SR register  ********************/

+#define JPEG_SR_IFTF_Pos                (1U)

+#define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */

+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is bellow its threshold flag */

+#define JPEG_SR_IFNFF_Pos               (2U)

+#define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */

+#define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */

+#define JPEG_SR_OFTF_Pos                (3U)

+#define JPEG_SR_OFTF_Msk                (0x1UL << JPEG_SR_OFTF_Pos)            /*!< 0x00000008 */

+#define JPEG_SR_OFTF                    JPEG_SR_OFTF_Msk                       /*!<Output FIFO is not empty and has reach its threshold */

+#define JPEG_SR_OFNEF_Pos               (4U)

+#define JPEG_SR_OFNEF_Msk               (0x1UL << JPEG_SR_OFNEF_Pos)           /*!< 0x00000010 */

+#define JPEG_SR_OFNEF                   JPEG_SR_OFNEF_Msk                      /*!<Output FIFO is not empty, a data is available */

+#define JPEG_SR_EOCF_Pos                (5U)

+#define JPEG_SR_EOCF_Msk                (0x1UL << JPEG_SR_EOCF_Pos)            /*!< 0x00000020 */

+#define JPEG_SR_EOCF                    JPEG_SR_EOCF_Msk                       /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */

+#define JPEG_SR_HPDF_Pos                (6U)

+#define JPEG_SR_HPDF_Msk                (0x1UL << JPEG_SR_HPDF_Pos)            /*!< 0x00000040 */

+#define JPEG_SR_HPDF                    JPEG_SR_HPDF_Msk                       /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */

+#define JPEG_SR_COF_Pos                 (7U)

+#define JPEG_SR_COF_Msk                 (0x1UL << JPEG_SR_COF_Pos)             /*!< 0x00000080 */

+#define JPEG_SR_COF                     JPEG_SR_COF_Msk                        /*!<JPEG Codec operation on going flag */

+

+/********************  Bit definition for CFR register  ********************/

+#define JPEG_CFR_CEOCF_Pos              (4U)

+#define JPEG_CFR_CEOCF_Msk              (0x1UL << JPEG_CFR_CEOCF_Pos)          /*!< 0x00000010 */

+#define JPEG_CFR_CEOCF                  JPEG_CFR_CEOCF_Msk                     /*!<Clear End of Conversion Flag */

+#define JPEG_CFR_CHPDF_Pos              (5U)

+#define JPEG_CFR_CHPDF_Msk              (0x1UL << JPEG_CFR_CHPDF_Pos)          /*!< 0x00000020 */

+#define JPEG_CFR_CHPDF                  JPEG_CFR_CHPDF_Msk                     /*!<Clear Header Parsing Done Flag */

+

+/********************  Bit definition for DIR register  ********************/

+#define JPEG_DIR_DATAIN_Pos             (0U)

+#define JPEG_DIR_DATAIN_Msk             (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)  /*!< 0xFFFFFFFF */

+#define JPEG_DIR_DATAIN                 JPEG_DIR_DATAIN_Msk                    /*!<Data Input FIFO */

+

+/********************  Bit definition for DOR register  ********************/

+#define JPEG_DOR_DATAOUT_Pos            (0U)

+#define JPEG_DOR_DATAOUT_Msk            (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */

+#define JPEG_DOR_DATAOUT                JPEG_DOR_DATAOUT_Msk                   /*!<Data Output FIFO */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      LCD-TFT Display Controller (LTDC)                     */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for LTDC_SSCR register  *****************/

+

+#define LTDC_SSCR_VSH_Pos            (0U)

+#define LTDC_SSCR_VSH_Msk            (0x7FFUL << LTDC_SSCR_VSH_Pos)            /*!< 0x000007FF */

+#define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height  */

+#define LTDC_SSCR_HSW_Pos            (16U)

+#define LTDC_SSCR_HSW_Msk            (0xFFFUL << LTDC_SSCR_HSW_Pos)            /*!< 0x0FFF0000 */

+#define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */

+

+/********************  Bit definition for LTDC_BPCR register  *****************/

+

+#define LTDC_BPCR_AVBP_Pos           (0U)

+#define LTDC_BPCR_AVBP_Msk           (0x7FFUL << LTDC_BPCR_AVBP_Pos)           /*!< 0x000007FF */

+#define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch   */

+#define LTDC_BPCR_AHBP_Pos           (16U)

+#define LTDC_BPCR_AHBP_Msk           (0xFFFUL << LTDC_BPCR_AHBP_Pos)           /*!< 0x0FFF0000 */

+#define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */

+

+/********************  Bit definition for LTDC_AWCR register  *****************/

+

+#define LTDC_AWCR_AAH_Pos            (0U)

+#define LTDC_AWCR_AAH_Msk            (0x7FFUL << LTDC_AWCR_AAH_Pos)            /*!< 0x000007FF */

+#define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active heigh */

+#define LTDC_AWCR_AAW_Pos            (16U)

+#define LTDC_AWCR_AAW_Msk            (0xFFFUL << LTDC_AWCR_AAW_Pos)            /*!< 0x0FFF0000 */

+#define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */

+

+/********************  Bit definition for LTDC_TWCR register  *****************/

+

+#define LTDC_TWCR_TOTALH_Pos         (0U)

+#define LTDC_TWCR_TOTALH_Msk         (0x7FFUL << LTDC_TWCR_TOTALH_Pos)         /*!< 0x000007FF */

+#define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total Heigh */

+#define LTDC_TWCR_TOTALW_Pos         (16U)

+#define LTDC_TWCR_TOTALW_Msk         (0xFFFUL << LTDC_TWCR_TOTALW_Pos)         /*!< 0x0FFF0000 */

+#define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */

+

+/********************  Bit definition for LTDC_GCR register  ******************/

+

+#define LTDC_GCR_LTDCEN_Pos          (0U)

+#define LTDC_GCR_LTDCEN_Msk          (0x1UL << LTDC_GCR_LTDCEN_Pos)            /*!< 0x00000001 */

+#define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit       */

+#define LTDC_GCR_DBW_Pos             (4U)

+#define LTDC_GCR_DBW_Msk             (0x7UL << LTDC_GCR_DBW_Pos)               /*!< 0x00000070 */

+#define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width                   */

+#define LTDC_GCR_DGW_Pos             (8U)

+#define LTDC_GCR_DGW_Msk             (0x7UL << LTDC_GCR_DGW_Pos)               /*!< 0x00000700 */

+#define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width                  */

+#define LTDC_GCR_DRW_Pos             (12U)

+#define LTDC_GCR_DRW_Msk             (0x7UL << LTDC_GCR_DRW_Pos)               /*!< 0x00007000 */

+#define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width                    */

+#define LTDC_GCR_DEN_Pos             (16U)

+#define LTDC_GCR_DEN_Msk             (0x1UL << LTDC_GCR_DEN_Pos)               /*!< 0x00010000 */

+#define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable                       */

+#define LTDC_GCR_PCPOL_Pos           (28U)

+#define LTDC_GCR_PCPOL_Msk           (0x1UL << LTDC_GCR_PCPOL_Pos)             /*!< 0x10000000 */

+#define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity                */

+#define LTDC_GCR_DEPOL_Pos           (29U)

+#define LTDC_GCR_DEPOL_Msk           (0x1UL << LTDC_GCR_DEPOL_Pos)             /*!< 0x20000000 */

+#define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity                */

+#define LTDC_GCR_VSPOL_Pos           (30U)

+#define LTDC_GCR_VSPOL_Msk           (0x1UL << LTDC_GCR_VSPOL_Pos)             /*!< 0x40000000 */

+#define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity   */

+#define LTDC_GCR_HSPOL_Pos           (31U)

+#define LTDC_GCR_HSPOL_Msk           (0x1UL << LTDC_GCR_HSPOL_Pos)             /*!< 0x80000000 */

+#define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */

+

+

+/********************  Bit definition for LTDC_SRCR register  *****************/

+

+#define LTDC_SRCR_IMR_Pos            (0U)

+#define LTDC_SRCR_IMR_Msk            (0x1UL << LTDC_SRCR_IMR_Pos)              /*!< 0x00000001 */

+#define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload         */

+#define LTDC_SRCR_VBR_Pos            (1U)

+#define LTDC_SRCR_VBR_Msk            (0x1UL << LTDC_SRCR_VBR_Pos)              /*!< 0x00000002 */

+#define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */

+

+/********************  Bit definition for LTDC_BCCR register  *****************/

+

+#define LTDC_BCCR_BCBLUE_Pos         (0U)

+#define LTDC_BCCR_BCBLUE_Msk         (0xFFUL << LTDC_BCCR_BCBLUE_Pos)          /*!< 0x000000FF */

+#define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value  */

+#define LTDC_BCCR_BCGREEN_Pos        (8U)

+#define LTDC_BCCR_BCGREEN_Msk        (0xFFUL << LTDC_BCCR_BCGREEN_Pos)         /*!< 0x0000FF00 */

+#define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */

+#define LTDC_BCCR_BCRED_Pos          (16U)

+#define LTDC_BCCR_BCRED_Msk          (0xFFUL << LTDC_BCCR_BCRED_Pos)           /*!< 0x00FF0000 */

+#define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value   */

+

+/********************  Bit definition for LTDC_IER register  ******************/

+

+#define LTDC_IER_LIE_Pos             (0U)

+#define LTDC_IER_LIE_Msk             (0x1UL << LTDC_IER_LIE_Pos)               /*!< 0x00000001 */

+#define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable            */

+#define LTDC_IER_FUIE_Pos            (1U)

+#define LTDC_IER_FUIE_Msk            (0x1UL << LTDC_IER_FUIE_Pos)              /*!< 0x00000002 */

+#define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable   */

+#define LTDC_IER_TERRIE_Pos          (2U)

+#define LTDC_IER_TERRIE_Msk          (0x1UL << LTDC_IER_TERRIE_Pos)            /*!< 0x00000004 */

+#define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable  */

+#define LTDC_IER_RRIE_Pos            (3U)

+#define LTDC_IER_RRIE_Msk            (0x1UL << LTDC_IER_RRIE_Pos)              /*!< 0x00000008 */

+#define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */

+

+/********************  Bit definition for LTDC_ISR register  ******************/

+

+#define LTDC_ISR_LIF_Pos             (0U)

+#define LTDC_ISR_LIF_Msk             (0x1UL << LTDC_ISR_LIF_Pos)               /*!< 0x00000001 */

+#define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */

+#define LTDC_ISR_FUIF_Pos            (1U)

+#define LTDC_ISR_FUIF_Msk            (0x1UL << LTDC_ISR_FUIF_Pos)              /*!< 0x00000002 */

+#define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */

+#define LTDC_ISR_TERRIF_Pos          (2U)

+#define LTDC_ISR_TERRIF_Msk          (0x1UL << LTDC_ISR_TERRIF_Pos)            /*!< 0x00000004 */

+#define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */

+#define LTDC_ISR_RRIF_Pos            (3U)

+#define LTDC_ISR_RRIF_Msk            (0x1UL << LTDC_ISR_RRIF_Pos)              /*!< 0x00000008 */

+#define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */

+

+/********************  Bit definition for LTDC_ICR register  ******************/

+

+#define LTDC_ICR_CLIF_Pos            (0U)

+#define LTDC_ICR_CLIF_Msk            (0x1UL << LTDC_ICR_CLIF_Pos)              /*!< 0x00000001 */

+#define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */

+#define LTDC_ICR_CFUIF_Pos           (1U)

+#define LTDC_ICR_CFUIF_Msk           (0x1UL << LTDC_ICR_CFUIF_Pos)             /*!< 0x00000002 */

+#define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */

+#define LTDC_ICR_CTERRIF_Pos         (2U)

+#define LTDC_ICR_CTERRIF_Msk         (0x1UL << LTDC_ICR_CTERRIF_Pos)           /*!< 0x00000004 */

+#define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */

+#define LTDC_ICR_CRRIF_Pos           (3U)

+#define LTDC_ICR_CRRIF_Msk           (0x1UL << LTDC_ICR_CRRIF_Pos)             /*!< 0x00000008 */

+#define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */

+

+/********************  Bit definition for LTDC_LIPCR register  ****************/

+

+#define LTDC_LIPCR_LIPOS_Pos         (0U)

+#define LTDC_LIPCR_LIPOS_Msk         (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)         /*!< 0x000007FF */

+#define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */

+

+/********************  Bit definition for LTDC_CPSR register  *****************/

+

+#define LTDC_CPSR_CYPOS_Pos          (0U)

+#define LTDC_CPSR_CYPOS_Msk          (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)         /*!< 0x0000FFFF */

+#define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */

+#define LTDC_CPSR_CXPOS_Pos          (16U)

+#define LTDC_CPSR_CXPOS_Msk          (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)         /*!< 0xFFFF0000 */

+#define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */

+

+/********************  Bit definition for LTDC_CDSR register  *****************/

+

+#define LTDC_CDSR_VDES_Pos           (0U)

+#define LTDC_CDSR_VDES_Msk           (0x1UL << LTDC_CDSR_VDES_Pos)             /*!< 0x00000001 */

+#define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status       */

+#define LTDC_CDSR_HDES_Pos           (1U)

+#define LTDC_CDSR_HDES_Msk           (0x1UL << LTDC_CDSR_HDES_Pos)             /*!< 0x00000002 */

+#define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status     */

+#define LTDC_CDSR_VSYNCS_Pos         (2U)

+#define LTDC_CDSR_VSYNCS_Msk         (0x1UL << LTDC_CDSR_VSYNCS_Pos)           /*!< 0x00000004 */

+#define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status   */

+#define LTDC_CDSR_HSYNCS_Pos         (3U)

+#define LTDC_CDSR_HSYNCS_Msk         (0x1UL << LTDC_CDSR_HSYNCS_Pos)           /*!< 0x00000008 */

+#define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */

+

+/********************  Bit definition for LTDC_LxCR register  *****************/

+

+#define LTDC_LxCR_LEN_Pos            (0U)

+#define LTDC_LxCR_LEN_Msk            (0x1UL << LTDC_LxCR_LEN_Pos)              /*!< 0x00000001 */

+#define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable              */

+#define LTDC_LxCR_COLKEN_Pos         (1U)

+#define LTDC_LxCR_COLKEN_Msk         (0x1UL << LTDC_LxCR_COLKEN_Pos)           /*!< 0x00000002 */

+#define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable       */

+#define LTDC_LxCR_CLUTEN_Pos         (4U)

+#define LTDC_LxCR_CLUTEN_Msk         (0x1UL << LTDC_LxCR_CLUTEN_Pos)           /*!< 0x00000010 */

+#define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */

+

+/********************  Bit definition for LTDC_LxWHPCR register  **************/

+

+#define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)

+#define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)     /*!< 0x00000FFF */

+#define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */

+#define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)

+#define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)    /*!< 0xFFFF0000 */

+#define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position  */

+

+/********************  Bit definition for LTDC_LxWVPCR register  **************/

+

+#define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)

+#define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)     /*!< 0x00000FFF */

+#define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */

+#define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)

+#define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)    /*!< 0xFFFF0000 */

+#define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position  */

+

+/********************  Bit definition for LTDC_LxCKCR register  ***************/

+

+#define LTDC_LxCKCR_CKBLUE_Pos       (0U)

+#define LTDC_LxCKCR_CKBLUE_Msk       (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value  */

+#define LTDC_LxCKCR_CKGREEN_Pos      (8U)

+#define LTDC_LxCKCR_CKGREEN_Msk      (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */

+#define LTDC_LxCKCR_CKRED_Pos        (16U)

+#define LTDC_LxCKCR_CKRED_Msk        (0xFFUL << LTDC_LxCKCR_CKRED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value   */

+

+/********************  Bit definition for LTDC_LxPFCR register  ***************/

+

+#define LTDC_LxPFCR_PF_Pos           (0U)

+#define LTDC_LxPFCR_PF_Msk           (0x7UL << LTDC_LxPFCR_PF_Pos)             /*!< 0x00000007 */

+#define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */

+

+/********************  Bit definition for LTDC_LxCACR register  ***************/

+

+#define LTDC_LxCACR_CONSTA_Pos       (0U)

+#define LTDC_LxCACR_CONSTA_Msk       (0xFFUL << LTDC_LxCACR_CONSTA_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */

+

+/********************  Bit definition for LTDC_LxDCCR register  ***************/

+

+#define LTDC_LxDCCR_DCBLUE_Pos       (0U)

+#define LTDC_LxDCCR_DCBLUE_Msk       (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue  */

+#define LTDC_LxDCCR_DCGREEN_Pos      (8U)

+#define LTDC_LxDCCR_DCGREEN_Msk      (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */

+#define LTDC_LxDCCR_DCRED_Pos        (16U)

+#define LTDC_LxDCCR_DCRED_Msk        (0xFFUL << LTDC_LxDCCR_DCRED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red   */

+#define LTDC_LxDCCR_DCALPHA_Pos      (24U)

+#define LTDC_LxDCCR_DCALPHA_Msk      (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)       /*!< 0xFF000000 */

+#define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */

+

+/********************  Bit definition for LTDC_LxBFCR register  ***************/

+

+#define LTDC_LxBFCR_BF2_Pos          (0U)

+#define LTDC_LxBFCR_BF2_Msk          (0x7UL << LTDC_LxBFCR_BF2_Pos)            /*!< 0x00000007 */

+#define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */

+#define LTDC_LxBFCR_BF1_Pos          (8U)

+#define LTDC_LxBFCR_BF1_Msk          (0x7UL << LTDC_LxBFCR_BF1_Pos)            /*!< 0x00000700 */

+#define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */

+

+/********************  Bit definition for LTDC_LxCFBAR register  **************/

+

+#define LTDC_LxCFBAR_CFBADD_Pos      (0U)

+#define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */

+#define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */

+

+/********************  Bit definition for LTDC_LxCFBLR register  **************/

+

+#define LTDC_LxCFBLR_CFBLL_Pos       (0U)

+#define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)      /*!< 0x00001FFF */

+#define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length    */

+#define LTDC_LxCFBLR_CFBP_Pos        (16U)

+#define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)       /*!< 0x1FFF0000 */

+#define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */

+

+/********************  Bit definition for LTDC_LxCFBLNR register  *************/

+

+#define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)

+#define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)    /*!< 0x000007FF */

+#define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */

+

+/********************  Bit definition for LTDC_LxCLUTWR register  *************/

+

+#define LTDC_LxCLUTWR_BLUE_Pos       (0U)

+#define LTDC_LxCLUTWR_BLUE_Msk       (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value   */

+#define LTDC_LxCLUTWR_GREEN_Pos      (8U)

+#define LTDC_LxCLUTWR_GREEN_Msk      (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value  */

+#define LTDC_LxCLUTWR_RED_Pos        (16U)

+#define LTDC_LxCLUTWR_RED_Msk        (0xFFUL << LTDC_LxCLUTWR_RED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value    */

+#define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)

+#define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)     /*!< 0xFF000000 */

+#define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                     MDMA                                   */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for MDMA_GISR0 register  ****************/

+#define MDMA_GISR0_GIF0_Pos       (0U)

+#define MDMA_GISR0_GIF0_Msk       (0x1UL << MDMA_GISR0_GIF0_Pos)               /*!< 0x00000001 */

+#define MDMA_GISR0_GIF0           MDMA_GISR0_GIF0_Msk                          /*!< Channel 0 global interrupt flag */

+#define MDMA_GISR0_GIF1_Pos       (1U)

+#define MDMA_GISR0_GIF1_Msk       (0x1UL << MDMA_GISR0_GIF1_Pos)               /*!< 0x00000002 */

+#define MDMA_GISR0_GIF1           MDMA_GISR0_GIF1_Msk                          /*!< Channel 1 global interrupt flag */

+#define MDMA_GISR0_GIF2_Pos       (2U)

+#define MDMA_GISR0_GIF2_Msk       (0x1UL << MDMA_GISR0_GIF2_Pos)               /*!< 0x00000004 */

+#define MDMA_GISR0_GIF2           MDMA_GISR0_GIF2_Msk                          /*!< Channel 2 global interrupt flag */

+#define MDMA_GISR0_GIF3_Pos       (3U)

+#define MDMA_GISR0_GIF3_Msk       (0x1UL << MDMA_GISR0_GIF3_Pos)               /*!< 0x00000008 */

+#define MDMA_GISR0_GIF3           MDMA_GISR0_GIF3_Msk                          /*!< Channel 3 global interrupt flag */

+#define MDMA_GISR0_GIF4_Pos       (4U)

+#define MDMA_GISR0_GIF4_Msk       (0x1UL << MDMA_GISR0_GIF4_Pos)               /*!< 0x00000010 */

+#define MDMA_GISR0_GIF4           MDMA_GISR0_GIF4_Msk                          /*!< Channel 4 global interrupt flag */

+#define MDMA_GISR0_GIF5_Pos       (5U)

+#define MDMA_GISR0_GIF5_Msk       (0x1UL << MDMA_GISR0_GIF5_Pos)               /*!< 0x00000020 */

+#define MDMA_GISR0_GIF5           MDMA_GISR0_GIF5_Msk                          /*!< Channel 5 global interrupt flag */

+#define MDMA_GISR0_GIF6_Pos       (6U)

+#define MDMA_GISR0_GIF6_Msk       (0x1UL << MDMA_GISR0_GIF6_Pos)               /*!< 0x00000040 */

+#define MDMA_GISR0_GIF6           MDMA_GISR0_GIF6_Msk                          /*!< Channel 6 global interrupt flag */

+#define MDMA_GISR0_GIF7_Pos       (7U)

+#define MDMA_GISR0_GIF7_Msk       (0x1UL << MDMA_GISR0_GIF7_Pos)               /*!< 0x00000080 */

+#define MDMA_GISR0_GIF7           MDMA_GISR0_GIF7_Msk                          /*!< Channel 7 global interrupt flag */

+#define MDMA_GISR0_GIF8_Pos       (8U)

+#define MDMA_GISR0_GIF8_Msk       (0x1UL << MDMA_GISR0_GIF8_Pos)               /*!< 0x00000100 */

+#define MDMA_GISR0_GIF8           MDMA_GISR0_GIF8_Msk                          /*!< Channel 8 global interrupt flag */

+#define MDMA_GISR0_GIF9_Pos       (9U)

+#define MDMA_GISR0_GIF9_Msk       (0x1UL << MDMA_GISR0_GIF9_Pos)               /*!< 0x00000200 */

+#define MDMA_GISR0_GIF9           MDMA_GISR0_GIF9_Msk                          /*!< Channel 9 global interrupt flag */

+#define MDMA_GISR0_GIF10_Pos      (10U)

+#define MDMA_GISR0_GIF10_Msk      (0x1UL << MDMA_GISR0_GIF10_Pos)              /*!< 0x00000400 */

+#define MDMA_GISR0_GIF10          MDMA_GISR0_GIF10_Msk                         /*!< Channel 10 global interrupt flag */

+#define MDMA_GISR0_GIF11_Pos      (11U)

+#define MDMA_GISR0_GIF11_Msk      (0x1UL << MDMA_GISR0_GIF11_Pos)              /*!< 0x00000800 */

+#define MDMA_GISR0_GIF11          MDMA_GISR0_GIF11_Msk                         /*!< Channel 11 global interrupt flag */

+#define MDMA_GISR0_GIF12_Pos      (12U)

+#define MDMA_GISR0_GIF12_Msk      (0x1UL << MDMA_GISR0_GIF12_Pos)              /*!< 0x00001000 */

+#define MDMA_GISR0_GIF12          MDMA_GISR0_GIF12_Msk                         /*!< Channel 12 global interrupt flag */

+#define MDMA_GISR0_GIF13_Pos      (13U)

+#define MDMA_GISR0_GIF13_Msk      (0x1UL << MDMA_GISR0_GIF13_Pos)              /*!< 0x00002000 */

+#define MDMA_GISR0_GIF13          MDMA_GISR0_GIF13_Msk                         /*!< Channel 13 global interrupt flag */

+#define MDMA_GISR0_GIF14_Pos      (14U)

+#define MDMA_GISR0_GIF14_Msk      (0x1UL << MDMA_GISR0_GIF14_Pos)              /*!< 0x00004000 */

+#define MDMA_GISR0_GIF14          MDMA_GISR0_GIF14_Msk                         /*!< Channel 14 global interrupt flag */

+#define MDMA_GISR0_GIF15_Pos      (15U)

+#define MDMA_GISR0_GIF15_Msk      (0x1UL << MDMA_GISR0_GIF15_Pos)              /*!< 0x00008000 */

+#define MDMA_GISR0_GIF15          MDMA_GISR0_GIF15_Msk                         /*!< Channel 15 global interrupt flag */

+

+/********************  Bit definition for MDMA_CxISR register  ****************/

+#define MDMA_CISR_TEIF_Pos        (0U)

+#define MDMA_CISR_TEIF_Msk        (0x1UL << MDMA_CISR_TEIF_Pos)                /*!< 0x00000001 */

+#define MDMA_CISR_TEIF            MDMA_CISR_TEIF_Msk                           /*!< Channel x transfer error interrupt flag */

+#define MDMA_CISR_CTCIF_Pos       (1U)

+#define MDMA_CISR_CTCIF_Msk       (0x1UL << MDMA_CISR_CTCIF_Pos)               /*!< 0x00000002 */

+#define MDMA_CISR_CTCIF           MDMA_CISR_CTCIF_Msk                          /*!< Channel x Channel Transfer Complete interrupt flag */

+#define MDMA_CISR_BRTIF_Pos       (2U)

+#define MDMA_CISR_BRTIF_Msk       (0x1UL << MDMA_CISR_BRTIF_Pos)               /*!< 0x00000004 */

+#define MDMA_CISR_BRTIF           MDMA_CISR_BRTIF_Msk                          /*!< Channel x block repeat transfer complete interrupt flag */

+#define MDMA_CISR_BTIF_Pos        (3U)

+#define MDMA_CISR_BTIF_Msk        (0x1UL << MDMA_CISR_BTIF_Pos)                /*!< 0x00000008 */

+#define MDMA_CISR_BTIF            MDMA_CISR_BTIF_Msk                           /*!< Channel x block transfer complete interrupt flag */

+#define MDMA_CISR_TCIF_Pos        (4U)

+#define MDMA_CISR_TCIF_Msk        (0x1UL << MDMA_CISR_TCIF_Pos)                /*!< 0x00000010 */

+#define MDMA_CISR_TCIF            MDMA_CISR_TCIF_Msk                           /*!< Channel x buffer transfer complete interrupt flag */

+#define MDMA_CISR_CRQA_Pos        (16U)

+#define MDMA_CISR_CRQA_Msk        (0x1UL << MDMA_CISR_CRQA_Pos)                /*!< 0x00010000 */

+#define MDMA_CISR_CRQA            MDMA_CISR_CRQA_Msk                           /*!< Channel x ReQest Active flag */

+

+/********************  Bit definition for MDMA_CxIFCR register  ****************/

+#define MDMA_CIFCR_CTEIF_Pos      (0U)

+#define MDMA_CIFCR_CTEIF_Msk      (0x1UL << MDMA_CIFCR_CTEIF_Pos)              /*!< 0x00000001 */

+#define MDMA_CIFCR_CTEIF          MDMA_CIFCR_CTEIF_Msk                         /*!< Channel x clear transfer error interrupt flag */

+#define MDMA_CIFCR_CCTCIF_Pos     (1U)

+#define MDMA_CIFCR_CCTCIF_Msk     (0x1UL << MDMA_CIFCR_CCTCIF_Pos)             /*!< 0x00000002 */

+#define MDMA_CIFCR_CCTCIF         MDMA_CIFCR_CCTCIF_Msk                        /*!< Clear Channel transfer complete interrupt flag for channel x */

+#define MDMA_CIFCR_CBRTIF_Pos     (2U)

+#define MDMA_CIFCR_CBRTIF_Msk     (0x1UL << MDMA_CIFCR_CBRTIF_Pos)             /*!< 0x00000004 */

+#define MDMA_CIFCR_CBRTIF         MDMA_CIFCR_CBRTIF_Msk                        /*!< Channel x clear block repeat transfer complete interrupt flag */

+#define MDMA_CIFCR_CBTIF_Pos      (3U)

+#define MDMA_CIFCR_CBTIF_Msk      (0x1UL << MDMA_CIFCR_CBTIF_Pos)              /*!< 0x00000008 */

+#define MDMA_CIFCR_CBTIF          MDMA_CIFCR_CBTIF_Msk                         /*!< Channel x Clear block transfer complete interrupt flag */

+#define MDMA_CIFCR_CLTCIF_Pos     (4U)

+#define MDMA_CIFCR_CLTCIF_Msk     (0x1UL << MDMA_CIFCR_CLTCIF_Pos)             /*!< 0x00000010 */

+#define MDMA_CIFCR_CLTCIF         MDMA_CIFCR_CLTCIF_Msk                        /*!< CLear Transfer buffer Complete Interrupt Flag for channel */

+

+/********************  Bit definition for MDMA_CxESR register  ****************/

+#define MDMA_CESR_TEA_Pos         (0U)

+#define MDMA_CESR_TEA_Msk         (0x7FUL << MDMA_CESR_TEA_Pos)                /*!< 0x0000007F */

+#define MDMA_CESR_TEA             MDMA_CESR_TEA_Msk                            /*!< Transfer Error Address */

+#define MDMA_CESR_TED_Pos         (7U)

+#define MDMA_CESR_TED_Msk         (0x1UL << MDMA_CESR_TED_Pos)                 /*!< 0x00000080 */

+#define MDMA_CESR_TED             MDMA_CESR_TED_Msk                            /*!< Transfer Error Direction */

+#define MDMA_CESR_TELD_Pos        (8U)

+#define MDMA_CESR_TELD_Msk        (0x1UL << MDMA_CESR_TELD_Pos)                /*!< 0x00000100 */

+#define MDMA_CESR_TELD            MDMA_CESR_TELD_Msk                           /*!< Transfer Error Link Data */

+#define MDMA_CESR_TEMD_Pos        (9U)

+#define MDMA_CESR_TEMD_Msk        (0x1UL << MDMA_CESR_TEMD_Pos)                /*!< 0x00000200 */

+#define MDMA_CESR_TEMD            MDMA_CESR_TEMD_Msk                           /*!< Transfer Error Mask Data */

+#define MDMA_CESR_ASE_Pos         (10U)

+#define MDMA_CESR_ASE_Msk         (0x1UL << MDMA_CESR_ASE_Pos)                 /*!< 0x00000400 */

+#define MDMA_CESR_ASE             MDMA_CESR_ASE_Msk                            /*!< Address/Size Error       */

+#define MDMA_CESR_BSE_Pos         (11U)

+#define MDMA_CESR_BSE_Msk         (0x1UL << MDMA_CESR_BSE_Pos)                 /*!< 0x00000800 */

+#define MDMA_CESR_BSE             MDMA_CESR_BSE_Msk                            /*!< Block Size Error         */

+

+/********************  Bit definition for MDMA_CxCR register  ****************/

+#define MDMA_CCR_EN_Pos           (0U)

+#define MDMA_CCR_EN_Msk           (0x1UL << MDMA_CCR_EN_Pos)                   /*!< 0x00000001 */

+#define MDMA_CCR_EN               MDMA_CCR_EN_Msk                              /*!< Channel enable / flag channel ready when read low */

+#define MDMA_CCR_TEIE_Pos         (1U)

+#define MDMA_CCR_TEIE_Msk         (0x1UL << MDMA_CCR_TEIE_Pos)                 /*!< 0x00000002 */

+#define MDMA_CCR_TEIE             MDMA_CCR_TEIE_Msk                            /*!< Transfer error interrupt enable */

+#define MDMA_CCR_CTCIE_Pos        (2U)

+#define MDMA_CCR_CTCIE_Msk        (0x1UL << MDMA_CCR_CTCIE_Pos)                /*!< 0x00000004 */

+#define MDMA_CCR_CTCIE            MDMA_CCR_CTCIE_Msk                           /*!< Channel Transfer Complete interrupt enable */

+#define MDMA_CCR_BRTIE_Pos        (3U)

+#define MDMA_CCR_BRTIE_Msk        (0x1UL << MDMA_CCR_BRTIE_Pos)                /*!< 0x00000008 */

+#define MDMA_CCR_BRTIE            MDMA_CCR_BRTIE_Msk                           /*!< Block Repeat transfer interrupt enable */

+#define MDMA_CCR_BTIE_Pos         (4U)

+#define MDMA_CCR_BTIE_Msk         (0x1UL << MDMA_CCR_BTIE_Pos)                 /*!< 0x00000010 */

+#define MDMA_CCR_BTIE             MDMA_CCR_BTIE_Msk                            /*!< Block Transfer interrupt enable */

+#define MDMA_CCR_TCIE_Pos         (5U)

+#define MDMA_CCR_TCIE_Msk         (0x1UL << MDMA_CCR_TCIE_Pos)                 /*!< 0x00000020 */

+#define MDMA_CCR_TCIE             MDMA_CCR_TCIE_Msk                            /*!< buffer Transfer Complete interrupt enable */

+#define MDMA_CCR_PL_Pos           (6U)

+#define MDMA_CCR_PL_Msk           (0x3UL << MDMA_CCR_PL_Pos)                   /*!< 0x000000C0 */

+#define MDMA_CCR_PL               MDMA_CCR_PL_Msk                              /*!< Priority level */

+#define MDMA_CCR_PL_0             (0x1UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000040 */

+#define MDMA_CCR_PL_1             (0x2UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000080 */

+#define MDMA_CCR_BEX_Pos          (12U)

+#define MDMA_CCR_BEX_Msk          (0x1UL << MDMA_CCR_BEX_Pos)                  /*!< 0x00001000 */

+#define MDMA_CCR_BEX              MDMA_CCR_BEX_Msk                             /*!< Byte Endianess eXchange */

+#define MDMA_CCR_HEX_Pos          (13U)

+#define MDMA_CCR_HEX_Msk          (0x1UL << MDMA_CCR_HEX_Pos)                  /*!< 0x00002000 */

+#define MDMA_CCR_HEX              MDMA_CCR_HEX_Msk                             /*!< Half word Endianess eXchange */

+#define MDMA_CCR_WEX_Pos          (14U)

+#define MDMA_CCR_WEX_Msk          (0x1UL << MDMA_CCR_WEX_Pos)                  /*!< 0x00004000 */

+#define MDMA_CCR_WEX              MDMA_CCR_WEX_Msk                             /*!< Word Endianess eXchange */

+#define MDMA_CCR_SWRQ_Pos         (16U)

+#define MDMA_CCR_SWRQ_Msk         (0x1UL << MDMA_CCR_SWRQ_Pos)                 /*!< 0x00010000 */

+#define MDMA_CCR_SWRQ             MDMA_CCR_SWRQ_Msk                            /*!< SW ReQuest */

+

+/********************  Bit definition for MDMA_CxTCR register  ****************/

+#define MDMA_CTCR_SINC_Pos        (0U)

+#define MDMA_CTCR_SINC_Msk        (0x3UL << MDMA_CTCR_SINC_Pos)                /*!< 0x00000003 */

+#define MDMA_CTCR_SINC            MDMA_CTCR_SINC_Msk                           /*!< Source increment mode */

+#define MDMA_CTCR_SINC_0          (0x1UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000001 */

+#define MDMA_CTCR_SINC_1          (0x2UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000002 */

+#define MDMA_CTCR_DINC_Pos        (2U)

+#define MDMA_CTCR_DINC_Msk        (0x3UL << MDMA_CTCR_DINC_Pos)                /*!< 0x0000000C */

+#define MDMA_CTCR_DINC            MDMA_CTCR_DINC_Msk                           /*!< Source increment mode */

+#define MDMA_CTCR_DINC_0          (0x1UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000004 */

+#define MDMA_CTCR_DINC_1          (0x2UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000008 */

+#define MDMA_CTCR_SSIZE_Pos       (4U)

+#define MDMA_CTCR_SSIZE_Msk       (0x3UL << MDMA_CTCR_SSIZE_Pos)               /*!< 0x00000030 */

+#define MDMA_CTCR_SSIZE           MDMA_CTCR_SSIZE_Msk                          /*!< Source data size */

+#define MDMA_CTCR_SSIZE_0         (0x1UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000010 */

+#define MDMA_CTCR_SSIZE_1         (0x2UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000020 */

+#define MDMA_CTCR_DSIZE_Pos       (6U)

+#define MDMA_CTCR_DSIZE_Msk       (0x3UL << MDMA_CTCR_DSIZE_Pos)               /*!< 0x000000C0 */

+#define MDMA_CTCR_DSIZE           MDMA_CTCR_DSIZE_Msk                          /*!< Destination data size */

+#define MDMA_CTCR_DSIZE_0         (0x1UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000040 */

+#define MDMA_CTCR_DSIZE_1         (0x2UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000080 */

+#define MDMA_CTCR_SINCOS_Pos      (8U)

+#define MDMA_CTCR_SINCOS_Msk      (0x3UL << MDMA_CTCR_SINCOS_Pos)              /*!< 0x00000300 */

+#define MDMA_CTCR_SINCOS          MDMA_CTCR_SINCOS_Msk                         /*!< Source increment offset size */

+#define MDMA_CTCR_SINCOS_0        (0x1UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000100 */

+#define MDMA_CTCR_SINCOS_1        (0x2UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000200 */

+#define MDMA_CTCR_DINCOS_Pos      (10U)

+#define MDMA_CTCR_DINCOS_Msk      (0x3UL << MDMA_CTCR_DINCOS_Pos)              /*!< 0x00000C00 */

+#define MDMA_CTCR_DINCOS          MDMA_CTCR_DINCOS_Msk                         /*!< Destination increment offset size */

+#define MDMA_CTCR_DINCOS_0        (0x1UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000400 */

+#define MDMA_CTCR_DINCOS_1        (0x2UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000800 */

+#define MDMA_CTCR_SBURST_Pos      (12U)

+#define MDMA_CTCR_SBURST_Msk      (0x7UL << MDMA_CTCR_SBURST_Pos)              /*!< 0x00007000 */

+#define MDMA_CTCR_SBURST          MDMA_CTCR_SBURST_Msk                         /*!< Source burst transfer configuration */

+#define MDMA_CTCR_SBURST_0        (0x1UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00001000 */

+#define MDMA_CTCR_SBURST_1        (0x2UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00002000 */

+#define MDMA_CTCR_SBURST_2        (0x4UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00004000 */

+#define MDMA_CTCR_DBURST_Pos      (15U)

+#define MDMA_CTCR_DBURST_Msk      (0x7UL << MDMA_CTCR_DBURST_Pos)              /*!< 0x00038000 */

+#define MDMA_CTCR_DBURST          MDMA_CTCR_DBURST_Msk                         /*!< Destination burst transfer configuration */

+#define MDMA_CTCR_DBURST_0        (0x1UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00008000 */

+#define MDMA_CTCR_DBURST_1        (0x2UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00010000 */

+#define MDMA_CTCR_DBURST_2        (0x4UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00020000 */

+#define MDMA_CTCR_TLEN_Pos        (18U)

+#define MDMA_CTCR_TLEN_Msk        (0x7FUL << MDMA_CTCR_TLEN_Pos)               /*!< 0x01FC0000 */

+#define MDMA_CTCR_TLEN            MDMA_CTCR_TLEN_Msk                           /*!< buffer Transfer Length (number of bytes - 1) */

+#define MDMA_CTCR_PKE_Pos         (25U)

+#define MDMA_CTCR_PKE_Msk         (0x1UL << MDMA_CTCR_PKE_Pos)                 /*!< 0x02000000 */

+#define MDMA_CTCR_PKE             MDMA_CTCR_PKE_Msk                            /*!< PacK Enable */

+#define MDMA_CTCR_PAM_Pos         (26U)

+#define MDMA_CTCR_PAM_Msk         (0x3UL << MDMA_CTCR_PAM_Pos)                 /*!< 0x0C000000 */

+#define MDMA_CTCR_PAM             MDMA_CTCR_PAM_Msk                            /*!< Padding/Alignement Mode */

+#define MDMA_CTCR_PAM_0           (0x1UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x4000000 */

+#define MDMA_CTCR_PAM_1           (0x2UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x8000000 */

+#define MDMA_CTCR_TRGM_Pos        (28U)

+#define MDMA_CTCR_TRGM_Msk        (0x3UL << MDMA_CTCR_TRGM_Pos)                /*!< 0x30000000 */

+#define MDMA_CTCR_TRGM            MDMA_CTCR_TRGM_Msk                           /*!< Trigger Mode */

+#define MDMA_CTCR_TRGM_0          (0x1UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x10000000 */

+#define MDMA_CTCR_TRGM_1          (0x2UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x20000000 */

+#define MDMA_CTCR_SWRM_Pos        (30U)

+#define MDMA_CTCR_SWRM_Msk        (0x1UL << MDMA_CTCR_SWRM_Pos)                /*!< 0x40000000 */

+#define MDMA_CTCR_SWRM            MDMA_CTCR_SWRM_Msk                           /*!< SW Request Mode */

+#define MDMA_CTCR_BWM_Pos         (31U)

+#define MDMA_CTCR_BWM_Msk         (0x1UL << MDMA_CTCR_BWM_Pos)                 /*!< 0x80000000 */

+#define MDMA_CTCR_BWM             MDMA_CTCR_BWM_Msk                            /*!< Bufferable Write Mode */

+

+/********************  Bit definition for MDMA_CxBNDTR register  ****************/

+#define MDMA_CBNDTR_BNDT_Pos      (0U)

+#define MDMA_CBNDTR_BNDT_Msk      (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos)          /*!< 0x0001FFFF */

+#define MDMA_CBNDTR_BNDT          MDMA_CBNDTR_BNDT_Msk                         /*!< Block Number of data bytes to transfer */

+#define MDMA_CBNDTR_BRSUM_Pos     (18U)

+#define MDMA_CBNDTR_BRSUM_Msk     (0x1UL << MDMA_CBNDTR_BRSUM_Pos)             /*!< 0x00040000 */

+#define MDMA_CBNDTR_BRSUM         MDMA_CBNDTR_BRSUM_Msk                        /*!< Block Repeat Source address Update Mode */

+#define MDMA_CBNDTR_BRDUM_Pos     (19U)

+#define MDMA_CBNDTR_BRDUM_Msk     (0x1UL << MDMA_CBNDTR_BRDUM_Pos)             /*!< 0x00080000 */

+#define MDMA_CBNDTR_BRDUM         MDMA_CBNDTR_BRDUM_Msk                        /*!< Block Repeat Destination address Update Mode */

+#define MDMA_CBNDTR_BRC_Pos       (20U)

+#define MDMA_CBNDTR_BRC_Msk       (0xFFFUL << MDMA_CBNDTR_BRC_Pos)             /*!< 0xFFF00000 */

+#define MDMA_CBNDTR_BRC           MDMA_CBNDTR_BRC_Msk                          /*!< Block Repeat Count */

+

+/********************  Bit definition for MDMA_CxSAR register  ****************/

+#define MDMA_CSAR_SAR_Pos         (0U)

+#define MDMA_CSAR_SAR_Msk         (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CSAR_SAR             MDMA_CSAR_SAR_Msk                            /*!< Source address */

+

+/********************  Bit definition for MDMA_CxDAR register  ****************/

+#define MDMA_CDAR_DAR_Pos         (0U)

+#define MDMA_CDAR_DAR_Msk         (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CDAR_DAR             MDMA_CDAR_DAR_Msk                            /*!< Destination address */

+

+/********************  Bit definition for MDMA_CxBRUR  ************************/

+#define MDMA_CBRUR_SUV_Pos        (0U)

+#define MDMA_CBRUR_SUV_Msk        (0xFFFFUL << MDMA_CBRUR_SUV_Pos)             /*!< 0x0000FFFF */

+#define MDMA_CBRUR_SUV            MDMA_CBRUR_SUV_Msk                           /*!< Source address Update Value */

+#define MDMA_CBRUR_DUV_Pos        (16U)

+#define MDMA_CBRUR_DUV_Msk        (0xFFFFUL << MDMA_CBRUR_DUV_Pos)             /*!< 0xFFFF0000 */

+#define MDMA_CBRUR_DUV            MDMA_CBRUR_DUV_Msk                           /*!< Destination address Update Value */

+

+/********************  Bit definition for MDMA_CxLAR  *************************/

+#define MDMA_CLAR_LAR_Pos         (0U)

+#define MDMA_CLAR_LAR_Msk         (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CLAR_LAR             MDMA_CLAR_LAR_Msk                            /*!< Link Address Register */

+

+/********************  Bit definition for MDMA_CxTBR)  ************************/

+#define MDMA_CTBR_TSEL_Pos        (0U)

+#define MDMA_CTBR_TSEL_Msk        (0xFFUL << MDMA_CTBR_TSEL_Pos)               /*!< 0x000000FF */

+#define MDMA_CTBR_TSEL            MDMA_CTBR_TSEL_Msk                           /*!< Trigger SELection */

+#define MDMA_CTBR_SBUS_Pos        (16U)

+#define MDMA_CTBR_SBUS_Msk        (0x1UL << MDMA_CTBR_SBUS_Pos)                /*!< 0x00010000 */

+#define MDMA_CTBR_SBUS            MDMA_CTBR_SBUS_Msk                           /*!< Source BUS select */

+#define MDMA_CTBR_DBUS_Pos        (17U)

+#define MDMA_CTBR_DBUS_Msk        (0x1UL << MDMA_CTBR_DBUS_Pos)                /*!< 0x00020000 */

+#define MDMA_CTBR_DBUS            MDMA_CTBR_DBUS_Msk                           /*!< Destination BUS select */

+

+/********************  Bit definition for MDMA_CxMAR)  ************************/

+#define MDMA_CMAR_MAR_Pos         (0U)

+#define MDMA_CMAR_MAR_Msk         (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CMAR_MAR             MDMA_CMAR_MAR_Msk                            /*!< Mask address */

+

+/********************  Bit definition for MDMA_CxMDR)  ************************/

+#define MDMA_CMDR_MDR_Pos         (0U)

+#define MDMA_CMDR_MDR_Msk         (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CMDR_MDR             MDMA_CMDR_MDR_Msk                            /*!< Mask Data */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Operational Amplifier (OPAMP)                      */

+/*                                                                            */

+/******************************************************************************/

+/*********************  Bit definition for OPAMPx_CSR register  ***************/

+#define OPAMP_CSR_OPAMPxEN_Pos           (0U)

+#define OPAMP_CSR_OPAMPxEN_Msk           (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)     /*!< 0x00000001 */

+#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */

+#define OPAMP_CSR_FORCEVP_Pos            (1U)

+#define OPAMP_CSR_FORCEVP_Msk            (0x1UL << OPAMP_CSR_FORCEVP_Pos)      /*!< 0x00000002 */

+#define OPAMP_CSR_FORCEVP                OPAMP_CSR_FORCEVP_Msk                 /*!< Force internal reference on VP */

+

+#define OPAMP_CSR_VPSEL_Pos              (2U)

+#define OPAMP_CSR_VPSEL_Msk              (0x3UL << OPAMP_CSR_VPSEL_Pos)        /*!< 0x0000000C */

+#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */

+#define OPAMP_CSR_VPSEL_0                (0x1UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000004 */

+#define OPAMP_CSR_VPSEL_1                (0x2UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000008 */

+

+#define OPAMP_CSR_VMSEL_Pos              (5U)

+#define OPAMP_CSR_VMSEL_Msk              (0x3UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000060 */

+#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */

+#define OPAMP_CSR_VMSEL_0                (0x1UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000020 */

+#define OPAMP_CSR_VMSEL_1                (0x2UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000040 */

+

+#define OPAMP_CSR_OPAHSM_Pos             (8U)

+#define OPAMP_CSR_OPAHSM_Msk             (0x1UL << OPAMP_CSR_OPAHSM_Pos)       /*!< 0x00000100 */

+#define OPAMP_CSR_OPAHSM                 OPAMP_CSR_OPAHSM_Msk                  /*!< Operational amplifier high speed mode */

+#define OPAMP_CSR_CALON_Pos              (11U)

+#define OPAMP_CSR_CALON_Msk              (0x1UL << OPAMP_CSR_CALON_Pos)        /*!< 0x00000800 */

+#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */

+

+#define OPAMP_CSR_CALSEL_Pos             (12U)

+#define OPAMP_CSR_CALSEL_Msk             (0x3UL << OPAMP_CSR_CALSEL_Pos)       /*!< 0x00003000 */

+#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */

+#define OPAMP_CSR_CALSEL_0               (0x1UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00001000 */

+#define OPAMP_CSR_CALSEL_1               (0x2UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */

+

+#define OPAMP_CSR_PGGAIN_Pos             (14U)

+#define OPAMP_CSR_PGGAIN_Msk             (0xFUL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x0003C000 */

+#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */

+#define OPAMP_CSR_PGGAIN_0               (0x1UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00004000 */

+#define OPAMP_CSR_PGGAIN_1               (0x2UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00008000 */

+#define OPAMP_CSR_PGGAIN_2               (0x4UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00010000 */

+#define OPAMP_CSR_PGGAIN_3               (0x8UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00020000 */

+

+#define OPAMP_CSR_USERTRIM_Pos           (18U)

+#define OPAMP_CSR_USERTRIM_Msk           (0x1UL << OPAMP_CSR_USERTRIM_Pos)     /*!< 0x00040000 */

+#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */

+#define OPAMP_CSR_TSTREF_Pos             (29U)

+#define OPAMP_CSR_TSTREF_Msk             (0x1UL << OPAMP_CSR_TSTREF_Pos)       /*!< 0x20000000 */

+#define OPAMP_CSR_TSTREF                 OPAMP_CSR_TSTREF_Msk                  /*!< OpAmp calibration reference voltage output control */

+#define OPAMP_CSR_CALOUT_Pos             (30U)

+#define OPAMP_CSR_CALOUT_Msk             (0x1UL << OPAMP_CSR_CALOUT_Pos)       /*!< 0x40000000 */

+#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier calibration output */

+

+/*********************  Bit definition for OPAMP1_CSR register  ***************/

+#define OPAMP1_CSR_OPAEN_Pos              (0U)

+#define OPAMP1_CSR_OPAEN_Msk              (0x1UL << OPAMP1_CSR_OPAEN_Pos)      /*!< 0x00000001 */

+#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */

+#define OPAMP1_CSR_FORCEVP_Pos            (1U)

+#define OPAMP1_CSR_FORCEVP_Msk            (0x1UL << OPAMP1_CSR_FORCEVP_Pos)    /*!< 0x00000002 */

+#define OPAMP1_CSR_FORCEVP                OPAMP1_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */

+

+#define OPAMP1_CSR_VPSEL_Pos              (2U)

+#define OPAMP1_CSR_VPSEL_Msk              (0x3UL << OPAMP1_CSR_VPSEL_Pos)      /*!< 0x0000000C */

+#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */

+#define OPAMP1_CSR_VPSEL_0                (0x1UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000004 */

+#define OPAMP1_CSR_VPSEL_1                (0x2UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000008 */

+

+#define OPAMP1_CSR_VMSEL_Pos              (5U)

+#define OPAMP1_CSR_VMSEL_Msk              (0x3UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000060 */

+#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */

+#define OPAMP1_CSR_VMSEL_0                (0x1UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000020 */

+#define OPAMP1_CSR_VMSEL_1                (0x2UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000040 */

+

+#define OPAMP1_CSR_OPAHSM_Pos             (8U)

+#define OPAMP1_CSR_OPAHSM_Msk             (0x1UL << OPAMP1_CSR_OPAHSM_Pos)     /*!< 0x00000100 */

+#define OPAMP1_CSR_OPAHSM                 OPAMP1_CSR_OPAHSM_Msk                /*!< Operational amplifier1 high speed mode */

+#define OPAMP1_CSR_CALON_Pos              (11U)

+#define OPAMP1_CSR_CALON_Msk              (0x1UL << OPAMP1_CSR_CALON_Pos)      /*!< 0x00000800 */

+#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */

+

+#define OPAMP1_CSR_CALSEL_Pos             (12U)

+#define OPAMP1_CSR_CALSEL_Msk             (0x3UL << OPAMP1_CSR_CALSEL_Pos)     /*!< 0x00003000 */

+#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */

+#define OPAMP1_CSR_CALSEL_0               (0x1UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00001000 */

+#define OPAMP1_CSR_CALSEL_1               (0x2UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */

+

+#define OPAMP1_CSR_PGGAIN_Pos             (14U)

+#define OPAMP1_CSR_PGGAIN_Msk             (0xFUL << OPAMP1_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */

+#define OPAMP1_CSR_PGGAIN                 OPAMP1_CSR_PGGAIN_Msk                /*!< Operational amplifier1 Programmable amplifier gain value */

+#define OPAMP1_CSR_PGGAIN_0               (0x1UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00004000 */

+#define OPAMP1_CSR_PGGAIN_1               (0x2UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00008000 */

+#define OPAMP1_CSR_PGGAIN_2               (0x4UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00010000 */

+#define OPAMP1_CSR_PGGAIN_3               (0x8UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00020000 */

+

+#define OPAMP1_CSR_USERTRIM_Pos           (18U)

+#define OPAMP1_CSR_USERTRIM_Msk           (0x1UL << OPAMP1_CSR_USERTRIM_Pos)   /*!< 0x00040000 */

+#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */

+#define OPAMP1_CSR_TSTREF_Pos             (29U)

+#define OPAMP1_CSR_TSTREF_Msk             (0x1UL << OPAMP1_CSR_TSTREF_Pos)     /*!< 0x20000000 */

+#define OPAMP1_CSR_TSTREF                 OPAMP1_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */

+#define OPAMP1_CSR_CALOUT_Pos             (30U)

+#define OPAMP1_CSR_CALOUT_Msk             (0x1UL << OPAMP1_CSR_CALOUT_Pos)     /*!< 0x40000000 */

+#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */

+

+/*********************  Bit definition for OPAMP2_CSR register  ***************/

+#define OPAMP2_CSR_OPAEN_Pos              (0U)

+#define OPAMP2_CSR_OPAEN_Msk              (0x1UL << OPAMP2_CSR_OPAEN_Pos)      /*!< 0x00000001 */

+#define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */

+#define OPAMP2_CSR_FORCEVP_Pos            (1U)

+#define OPAMP2_CSR_FORCEVP_Msk            (0x1UL << OPAMP2_CSR_FORCEVP_Pos)    /*!< 0x00000002 */

+#define OPAMP2_CSR_FORCEVP                OPAMP2_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */

+

+#define OPAMP2_CSR_VPSEL_Pos              (2U)

+#define OPAMP2_CSR_VPSEL_Msk              (0x3UL << OPAMP2_CSR_VPSEL_Pos)      /*!< 0x0000000C */

+#define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */

+#define OPAMP2_CSR_VPSEL_0                (0x1UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000004 */

+#define OPAMP2_CSR_VPSEL_1                (0x2UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000008 */

+

+#define OPAMP2_CSR_VMSEL_Pos              (5U)

+#define OPAMP2_CSR_VMSEL_Msk              (0x3UL << OPAMP2_CSR_VMSEL_Pos)      /*!< 0x00000060 */

+#define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */

+#define OPAMP2_CSR_VMSEL_0                (0x1UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000020 */

+#define OPAMP2_CSR_VMSEL_1                (0x2UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000040 */

+

+#define OPAMP2_CSR_OPAHSM_Pos             (8U)

+#define OPAMP2_CSR_OPAHSM_Msk             (0x1UL << OPAMP2_CSR_OPAHSM_Pos)     /*!< 0x00000100 */

+#define OPAMP2_CSR_OPAHSM                 OPAMP2_CSR_OPAHSM_Msk                /*!< Operational amplifier2 high speed mode */

+#define OPAMP2_CSR_CALON_Pos              (11U)

+#define OPAMP2_CSR_CALON_Msk              (0x1UL << OPAMP2_CSR_CALON_Pos)      /*!< 0x00000800 */

+#define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */

+

+#define OPAMP2_CSR_CALSEL_Pos             (12U)

+#define OPAMP2_CSR_CALSEL_Msk             (0x3UL << OPAMP2_CSR_CALSEL_Pos)     /*!< 0x00003000 */

+#define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */

+#define OPAMP2_CSR_CALSEL_0               (0x1UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00001000 */

+#define OPAMP2_CSR_CALSEL_1               (0x2UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */

+

+#define OPAMP2_CSR_PGGAIN_Pos             (14U)

+#define OPAMP2_CSR_PGGAIN_Msk             (0xFUL << OPAMP2_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */

+#define OPAMP2_CSR_PGGAIN                 OPAMP2_CSR_PGGAIN_Msk                /*!< Operational amplifier2 Programmable amplifier gain value */

+#define OPAMP2_CSR_PGGAIN_0               (0x1UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00004000 */

+#define OPAMP2_CSR_PGGAIN_1               (0x2UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00008000 */

+#define OPAMP2_CSR_PGGAIN_2               (0x4UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00010000 */

+#define OPAMP2_CSR_PGGAIN_3               (0x8UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00020000 */

+

+#define OPAMP2_CSR_USERTRIM_Pos           (18U)

+#define OPAMP2_CSR_USERTRIM_Msk           (0x1UL << OPAMP2_CSR_USERTRIM_Pos)   /*!< 0x00040000 */

+#define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */

+#define OPAMP2_CSR_TSTREF_Pos             (29U)

+#define OPAMP2_CSR_TSTREF_Msk             (0x1UL << OPAMP2_CSR_TSTREF_Pos)     /*!< 0x20000000 */

+#define OPAMP2_CSR_TSTREF                 OPAMP2_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */

+#define OPAMP2_CSR_CALOUT_Pos             (30U)

+#define OPAMP2_CSR_CALOUT_Msk             (0x1UL << OPAMP2_CSR_CALOUT_Pos)     /*!< 0x40000000 */

+#define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */

+

+/*******************  Bit definition for OPAMP_OTR register  ******************/

+#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */

+#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP1_OTR register  ******************/

+#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */

+#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP2_OTR register  ******************/

+#define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */

+#define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP_HSOTR register  ****************/

+#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP_HSOTR_TRIMHSOFFSETN        OPAMP_HSOTR_TRIMHSOFFSETN_Msk         /*!< Trim for NMOS differential pairs */

+#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP_HSOTR_TRIMHSOFFSETP        OPAMP_HSOTR_TRIMHSOFFSETP_Msk         /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP1_HSOTR register  ****************/

+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP1_HSOTR_TRIMHSOFFSETN        OPAMP1_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */

+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP1_HSOTR_TRIMHSOFFSETP        OPAMP1_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP2_HSOTR register  ****************/

+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP2_HSOTR_TRIMHSOFFSETN        OPAMP2_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */

+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP2_HSOTR_TRIMHSOFFSETP        OPAMP2_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             Power Control                                  */

+/*                                                                            */

+/******************************************************************************/

+/*************************  NUMBER OF POWER DOMAINS  **************************/

+#define POWER_DOMAINS_NUMBER           3U                                      /*!< 3 Domains */

+

+/********************  Bit definition for PWR_CR1 register  *******************/

+#define PWR_CR1_ALS_Pos                (17U)

+#define PWR_CR1_ALS_Msk                (0x3UL << PWR_CR1_ALS_Pos)              /*!< 0x00060000 */

+#define PWR_CR1_ALS                    PWR_CR1_ALS_Msk                         /*!< Analog Voltage Detector level selection */

+#define PWR_CR1_ALS_0                  (0x1UL << PWR_CR1_ALS_Pos)              /*!< 0x00020000 */

+#define PWR_CR1_ALS_1                  (0x2UL << PWR_CR1_ALS_Pos)              /*!< 0x00040000 */

+#define PWR_CR1_AVDEN_Pos              (16U)

+#define PWR_CR1_AVDEN_Msk              (0x1UL << PWR_CR1_AVDEN_Pos)            /*!< 0x00010000 */

+#define PWR_CR1_AVDEN                  PWR_CR1_AVDEN_Msk                       /*!< Analog Voltage Detector Enable */

+#define PWR_CR1_SVOS_Pos               (14U)

+#define PWR_CR1_SVOS_Msk               (0x3UL << PWR_CR1_SVOS_Pos)             /*!< 0x0000C000 */

+#define PWR_CR1_SVOS                   PWR_CR1_SVOS_Msk                        /*!< System STOP mode Voltage Scaling selection */

+#define PWR_CR1_SVOS_0                 (0x1UL << PWR_CR1_SVOS_Pos)             /*!< 0x00004000 */

+#define PWR_CR1_SVOS_1                 (0x2UL << PWR_CR1_SVOS_Pos)             /*!< 0x00008000 */

+#define PWR_CR1_FLPS_Pos               (9U)

+#define PWR_CR1_FLPS_Msk               (0x1UL << PWR_CR1_FLPS_Pos)             /*!< 0x00000200 */

+#define PWR_CR1_FLPS                   PWR_CR1_FLPS_Msk                        /*!< Flash low power mode in DSTOP */

+#define PWR_CR1_DBP_Pos                (8U)

+#define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */

+#define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable Back-up domain Protection */

+#define PWR_CR1_PLS_Pos                (5U)

+#define PWR_CR1_PLS_Msk                (0x7UL << PWR_CR1_PLS_Pos)              /*!< 0x000000E0 */

+#define PWR_CR1_PLS                    PWR_CR1_PLS_Msk                         /*!< Programmable Voltage Detector level selection */

+#define PWR_CR1_PLS_0                  (0x1UL << PWR_CR1_PLS_Pos)              /*!< 0x00000020 */

+#define PWR_CR1_PLS_1                  (0x2UL << PWR_CR1_PLS_Pos)              /*!< 0x00000040 */

+#define PWR_CR1_PLS_2                  (0x4UL << PWR_CR1_PLS_Pos)              /*!< 0x00000080 */

+#define PWR_CR1_PVDEN_Pos              (4U)

+#define PWR_CR1_PVDEN_Msk              (0x1UL << PWR_CR1_PVDEN_Pos)            /*!< 0x00000010 */

+#define PWR_CR1_PVDEN                  PWR_CR1_PVDEN_Msk                       /*!< Programmable Voltage detector enable */

+#define PWR_CR1_LPDS_Pos               (0U)

+#define PWR_CR1_LPDS_Msk               (0x1UL << PWR_CR1_LPDS_Pos)             /*!< 0x00000001 */

+#define PWR_CR1_LPDS                   PWR_CR1_LPDS_Msk                        /*!< Low Power Deepsleep with SVOS3 */

+

+/*!< PVD level configuration */

+#define PWR_CR1_PLS_LEV0               (0UL)                                   /*!< PVD level 0 */

+#define PWR_CR1_PLS_LEV1_Pos           (5U)

+#define PWR_CR1_PLS_LEV1_Msk           (0x1UL << PWR_CR1_PLS_LEV1_Pos)         /*!< 0x00000020 */

+#define PWR_CR1_PLS_LEV1               PWR_CR1_PLS_LEV1_Msk                    /*!< PVD level 1 */

+#define PWR_CR1_PLS_LEV2_Pos           (6U)

+#define PWR_CR1_PLS_LEV2_Msk           (0x1UL << PWR_CR1_PLS_LEV2_Pos)         /*!< 0x00000040 */

+#define PWR_CR1_PLS_LEV2               PWR_CR1_PLS_LEV2_Msk                    /*!< PVD level 2 */

+#define PWR_CR1_PLS_LEV3_Pos           (5U)

+#define PWR_CR1_PLS_LEV3_Msk           (0x3UL << PWR_CR1_PLS_LEV3_Pos)         /*!< 0x00000060 */

+#define PWR_CR1_PLS_LEV3               PWR_CR1_PLS_LEV3_Msk                    /*!< PVD level 3 */

+#define PWR_CR1_PLS_LEV4_Pos           (7U)

+#define PWR_CR1_PLS_LEV4_Msk           (0x1UL << PWR_CR1_PLS_LEV4_Pos)         /*!< 0x00000080 */

+#define PWR_CR1_PLS_LEV4               PWR_CR1_PLS_LEV4_Msk                    /*!< PVD level 4 */

+#define PWR_CR1_PLS_LEV5_Pos           (5U)

+#define PWR_CR1_PLS_LEV5_Msk           (0x5UL << PWR_CR1_PLS_LEV5_Pos)         /*!< 0x000000A0 */

+#define PWR_CR1_PLS_LEV5               PWR_CR1_PLS_LEV5_Msk                    /*!< PVD level 5 */

+#define PWR_CR1_PLS_LEV6_Pos           (6U)

+#define PWR_CR1_PLS_LEV6_Msk           (0x3UL << PWR_CR1_PLS_LEV6_Pos)         /*!< 0x000000C0 */

+#define PWR_CR1_PLS_LEV6               PWR_CR1_PLS_LEV6_Msk                    /*!< PVD level 6 */

+#define PWR_CR1_PLS_LEV7_Pos           (5U)

+#define PWR_CR1_PLS_LEV7_Msk           (0x7UL << PWR_CR1_PLS_LEV7_Pos)         /*!< 0x000000E0 */

+#define PWR_CR1_PLS_LEV7               PWR_CR1_PLS_LEV7_Msk                    /*!< PVD level 7 */

+

+/*!< AVD level configuration */

+#define PWR_CR1_ALS_LEV0               (0UL)                                   /*!< AVD level 0 */

+#define PWR_CR1_ALS_LEV1_Pos           (17U)

+#define PWR_CR1_ALS_LEV1_Msk           (0x1UL << PWR_CR1_ALS_LEV1_Pos)         /*!< 0x00020000 */

+#define PWR_CR1_ALS_LEV1               PWR_CR1_ALS_LEV1_Msk                    /*!< AVD level 1 */

+#define PWR_CR1_ALS_LEV2_Pos           (18U)

+#define PWR_CR1_ALS_LEV2_Msk           (0x1UL << PWR_CR1_ALS_LEV2_Pos)         /*!< 0x00040000 */

+#define PWR_CR1_ALS_LEV2               PWR_CR1_ALS_LEV2_Msk                    /*!< AVD level 2 */

+#define PWR_CR1_ALS_LEV3_Pos           (17U)

+#define PWR_CR1_ALS_LEV3_Msk           (0x3UL << PWR_CR1_ALS_LEV3_Pos)         /*!< 0x00060000 */

+#define PWR_CR1_ALS_LEV3               PWR_CR1_ALS_LEV3_Msk                    /*!< AVD level 3 */

+

+/********************  Bit definition for PWR_CSR1 register  ******************/

+#define PWR_CSR1_AVDO_Pos              (16U)

+#define PWR_CSR1_AVDO_Msk              (0x1UL << PWR_CSR1_AVDO_Pos)            /*!< 0x00010000 */

+#define PWR_CSR1_AVDO                  PWR_CSR1_AVDO_Msk                       /*!< Analog Voltage Detect Output */

+#define PWR_CSR1_ACTVOS_Pos            (14U)

+#define PWR_CSR1_ACTVOS_Msk            (0x3UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x0000C000 */

+#define PWR_CSR1_ACTVOS                PWR_CSR1_ACTVOS_Msk                     /*!< Current actual used VOS for VDD11 Voltage Scaling */

+#define PWR_CSR1_ACTVOS_0              (0x1UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00004000 */

+#define PWR_CSR1_ACTVOS_1              (0x2UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00008000 */

+#define PWR_CSR1_ACTVOSRDY_Pos         (13U)

+#define PWR_CSR1_ACTVOSRDY_Msk         (0x1UL << PWR_CSR1_ACTVOSRDY_Pos)       /*!< 0x00002000 */

+#define PWR_CSR1_ACTVOSRDY             PWR_CSR1_ACTVOSRDY_Msk                  /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling  */

+#define PWR_CSR1_PVDO_Pos              (4U)

+#define PWR_CSR1_PVDO_Msk              (0x1UL << PWR_CSR1_PVDO_Pos)            /*!< 0x00000010 */

+#define PWR_CSR1_PVDO                  PWR_CSR1_PVDO_Msk                       /*!< Programmable Voltage Detect Output */

+

+/********************  Bit definition for PWR_CR2 register  *******************/

+#define PWR_CR2_TEMPH_Pos              (23U)

+#define PWR_CR2_TEMPH_Msk              (0x1UL << PWR_CR2_TEMPH_Pos)            /*!< 0x00800000 */

+#define PWR_CR2_TEMPH                  PWR_CR2_TEMPH_Msk                       /*!< Monitored temperature level above high threshold */

+#define PWR_CR2_TEMPL_Pos              (22U)

+#define PWR_CR2_TEMPL_Msk              (0x1UL << PWR_CR2_TEMPL_Pos)            /*!< 0x00400000 */

+#define PWR_CR2_TEMPL                  PWR_CR2_TEMPL_Msk                       /*!< Monitored temperature level above low threshold */

+#define PWR_CR2_VBATH_Pos              (21U)

+#define PWR_CR2_VBATH_Msk              (0x1UL << PWR_CR2_VBATH_Pos)            /*!< 0x00200000 */

+#define PWR_CR2_VBATH                  PWR_CR2_VBATH_Msk                       /*!< Monitored VBAT level above high threshold */

+#define PWR_CR2_VBATL_Pos              (20U)

+#define PWR_CR2_VBATL_Msk              (0x1UL << PWR_CR2_VBATL_Pos)            /*!< 0x00100000 */

+#define PWR_CR2_VBATL                  PWR_CR2_VBATL_Msk                       /*!< Monitored VBAT level above low threshold */

+#define PWR_CR2_BRRDY_Pos              (16U)

+#define PWR_CR2_BRRDY_Msk              (0x1UL << PWR_CR2_BRRDY_Pos)            /*!< 0x00010000 */

+#define PWR_CR2_BRRDY                  PWR_CR2_BRRDY_Msk                       /*!< Backup regulator ready */

+#define PWR_CR2_MONEN_Pos              (4U)

+#define PWR_CR2_MONEN_Msk              (0x1UL << PWR_CR2_MONEN_Pos)            /*!< 0x00000010 */

+#define PWR_CR2_MONEN                  PWR_CR2_MONEN_Msk                       /*!< VBAT and temperature monitoring enable */

+#define PWR_CR2_BREN_Pos               (0U)

+#define PWR_CR2_BREN_Msk               (0x1UL << PWR_CR2_BREN_Pos)             /*!< 0x00000001 */

+#define PWR_CR2_BREN                   PWR_CR2_BREN_Msk                        /*!< Backup regulator enable */

+

+/********************  Bit definition for PWR_CR3 register  *******************/

+#define PWR_CR3_USB33RDY_Pos           (26U)

+#define PWR_CR3_USB33RDY_Msk           (0x1UL << PWR_CR3_USB33RDY_Pos)         /*!< 0x04000000 */

+#define PWR_CR3_USB33RDY               PWR_CR3_USB33RDY_Msk                    /*!< USB supply ready */

+#define PWR_CR3_USBREGEN_Pos           (25U)

+#define PWR_CR3_USBREGEN_Msk           (0x1UL << PWR_CR3_USBREGEN_Pos)         /*!< 0x02000000 */

+#define PWR_CR3_USBREGEN               PWR_CR3_USBREGEN_Msk                    /*!< USB regulator enable */

+#define PWR_CR3_USB33DEN_Pos           (24U)

+#define PWR_CR3_USB33DEN_Msk           (0x1UL << PWR_CR3_USB33DEN_Pos)         /*!< 0x01000000 */

+#define PWR_CR3_USB33DEN               PWR_CR3_USB33DEN_Msk                    /*!< VDD33_USB voltage level detector enable */

+#define PWR_CR3_VBRS_Pos               (9U)

+#define PWR_CR3_VBRS_Msk               (0x1UL << PWR_CR3_VBRS_Pos)             /*!< 0x00000200 */

+#define PWR_CR3_VBRS                   PWR_CR3_VBRS_Msk                        /*!< VBAT charging resistor selection */

+#define PWR_CR3_VBE_Pos                (8U)

+#define PWR_CR3_VBE_Msk                (0x1UL << PWR_CR3_VBE_Pos)              /*!< 0x00000100 */

+#define PWR_CR3_VBE                    PWR_CR3_VBE_Msk                         /*!< VBAT charging enable */

+#define PWR_CR3_SCUEN_Pos              (2U)

+#define PWR_CR3_SCUEN_Msk              (0x1UL << PWR_CR3_SCUEN_Pos)            /*!< 0x00000004 */

+#define PWR_CR3_SCUEN                  PWR_CR3_SCUEN_Msk                       /*!< Supply configuration update enable */

+#define PWR_CR3_LDOEN_Pos              (1U)

+#define PWR_CR3_LDOEN_Msk              (0x1UL << PWR_CR3_LDOEN_Pos)            /*!< 0x00000002 */

+#define PWR_CR3_LDOEN                  PWR_CR3_LDOEN_Msk                       /*!< Low Drop Output regulator enable */

+#define PWR_CR3_BYPASS_Pos             (0U)

+#define PWR_CR3_BYPASS_Msk             (0x1UL << PWR_CR3_BYPASS_Pos)           /*!< 0x00000001 */

+#define PWR_CR3_BYPASS                 PWR_CR3_BYPASS_Msk                      /*!< Power Management Unit bypass */

+

+/********************  Bit definition for PWR_CPUCR register  *****************/

+#define PWR_CPUCR_RUN_D3_Pos           (11U)

+#define PWR_CPUCR_RUN_D3_Msk           (0x1UL << PWR_CPUCR_RUN_D3_Pos)         /*!< 0x00000800 */

+#define PWR_CPUCR_RUN_D3               PWR_CPUCR_RUN_D3_Msk                    /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */

+#define PWR_CPUCR_CSSF_Pos             (9U)

+#define PWR_CPUCR_CSSF_Msk             (0x1UL << PWR_CPUCR_CSSF_Pos)           /*!< 0x00000200 */

+#define PWR_CPUCR_CSSF                 PWR_CPUCR_CSSF_Msk                      /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */

+#define PWR_CPUCR_SBF_D2_Pos           (8U)

+#define PWR_CPUCR_SBF_D2_Msk           (0x1UL << PWR_CPUCR_SBF_D2_Pos)         /*!< 0x00000100 */

+#define PWR_CPUCR_SBF_D2               PWR_CPUCR_SBF_D2_Msk                    /*!< D2 domain DSTANDBY Flag */

+#define PWR_CPUCR_SBF_D1_Pos           (7U)

+#define PWR_CPUCR_SBF_D1_Msk           (0x1UL << PWR_CPUCR_SBF_D1_Pos)         /*!< 0x00000080 */

+#define PWR_CPUCR_SBF_D1               PWR_CPUCR_SBF_D1_Msk                    /*!< D1 domain DSTANDBY Flag */

+#define PWR_CPUCR_SBF_Pos              (6U)

+#define PWR_CPUCR_SBF_Msk              (0x1UL << PWR_CPUCR_SBF_Pos)            /*!< 0x00000040 */

+#define PWR_CPUCR_SBF                  PWR_CPUCR_SBF_Msk                       /*!< System STANDBY Flag */

+#define PWR_CPUCR_STOPF_Pos            (5U)

+#define PWR_CPUCR_STOPF_Msk            (0x1UL << PWR_CPUCR_STOPF_Pos)          /*!< 0x00000020 */

+#define PWR_CPUCR_STOPF                PWR_CPUCR_STOPF_Msk                     /*!< STOP Flag */

+#define PWR_CPUCR_PDDS_D3_Pos          (2U)

+#define PWR_CPUCR_PDDS_D3_Msk          (0x1UL << PWR_CPUCR_PDDS_D3_Pos)        /*!< 0x00000004 */

+#define PWR_CPUCR_PDDS_D3              PWR_CPUCR_PDDS_D3_Msk                   /*!< System D3 domain Power Down Deepsleep */

+#define PWR_CPUCR_PDDS_D2_Pos          (1U)

+#define PWR_CPUCR_PDDS_D2_Msk          (0x1UL << PWR_CPUCR_PDDS_D2_Pos)        /*!< 0x00000002 */

+#define PWR_CPUCR_PDDS_D2              PWR_CPUCR_PDDS_D2_Msk                   /*!< D2 domain Power Down Deepsleep */

+#define PWR_CPUCR_PDDS_D1_Pos          (0U)

+#define PWR_CPUCR_PDDS_D1_Msk          (0x1UL << PWR_CPUCR_PDDS_D1_Pos)        /*!< 0x00000001 */

+#define PWR_CPUCR_PDDS_D1              PWR_CPUCR_PDDS_D1_Msk                   /*!< D1 domain Power Down Deepsleep selection */

+

+

+/********************  Bit definition for PWR_D3CR register  ******************/

+#define PWR_D3CR_VOS_Pos               (14U)

+#define PWR_D3CR_VOS_Msk               (0x3UL << PWR_D3CR_VOS_Pos)             /*!< 0x0000C000 */

+#define PWR_D3CR_VOS                   PWR_D3CR_VOS_Msk                        /*!< Voltage Scaling selection according performance */

+#define PWR_D3CR_VOS_0                 (0x1UL << PWR_D3CR_VOS_Pos)             /*!< 0x00004000 */

+#define PWR_D3CR_VOS_1                 (0x2UL << PWR_D3CR_VOS_Pos)             /*!< 0x00008000 */

+#define PWR_D3CR_VOSRDY_Pos            (13U)

+#define PWR_D3CR_VOSRDY_Msk            (0x1UL << PWR_D3CR_VOSRDY_Pos)          /*!< 0x00002000 */

+#define PWR_D3CR_VOSRDY                PWR_D3CR_VOSRDY_Msk                     /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */

+

+/******************  Bit definition for PWR_WKUPCR register  ******************/

+#define PWR_WKUPCR_WKUPC6_Pos          (5U)

+#define PWR_WKUPCR_WKUPC6_Msk          (0x1UL << PWR_WKUPCR_WKUPC6_Pos)        /*!< 0x00000020 */

+#define PWR_WKUPCR_WKUPC6              PWR_WKUPCR_WKUPC6_Msk                   /*!< Clear Wakeup Pin Flag 6 */

+#define PWR_WKUPCR_WKUPC5_Pos          (4U)

+#define PWR_WKUPCR_WKUPC5_Msk          (0x1UL << PWR_WKUPCR_WKUPC5_Pos)        /*!< 0x00000010 */

+#define PWR_WKUPCR_WKUPC5              PWR_WKUPCR_WKUPC5_Msk                   /*!< Clear Wakeup Pin Flag 5 */

+#define PWR_WKUPCR_WKUPC4_Pos          (3U)

+#define PWR_WKUPCR_WKUPC4_Msk          (0x1UL << PWR_WKUPCR_WKUPC4_Pos)        /*!< 0x00000008 */

+#define PWR_WKUPCR_WKUPC4              PWR_WKUPCR_WKUPC4_Msk                   /*!< Clear Wakeup Pin Flag 4 */

+#define PWR_WKUPCR_WKUPC3_Pos          (2U)

+#define PWR_WKUPCR_WKUPC3_Msk          (0x1UL << PWR_WKUPCR_WKUPC3_Pos)        /*!< 0x00000004 */

+#define PWR_WKUPCR_WKUPC3              PWR_WKUPCR_WKUPC3_Msk                   /*!< Clear Wakeup Pin Flag 3 */

+#define PWR_WKUPCR_WKUPC2_Pos          (1U)

+#define PWR_WKUPCR_WKUPC2_Msk          (0x1UL << PWR_WKUPCR_WKUPC2_Pos)        /*!< 0x00000002 */

+#define PWR_WKUPCR_WKUPC2              PWR_WKUPCR_WKUPC2_Msk                   /*!< Clear Wakeup Pin Flag 2 */

+#define PWR_WKUPCR_WKUPC1_Pos          (0U)

+#define PWR_WKUPCR_WKUPC1_Msk          (0x1UL << PWR_WKUPCR_WKUPC1_Pos)        /*!< 0x00000001 */

+#define PWR_WKUPCR_WKUPC1              PWR_WKUPCR_WKUPC1_Msk                   /*!< Clear Wakeup Pin Flag 1 */

+

+/********************  Bit definition for PWR_WKUPFR register  ****************/

+#define PWR_WKUPFR_WKUPF6_Pos          (5U)

+#define PWR_WKUPFR_WKUPF6_Msk          (0x1UL << PWR_WKUPFR_WKUPF6_Pos)        /*!< 0x00000020 */

+#define PWR_WKUPFR_WKUPF6              PWR_WKUPFR_WKUPF6_Msk                   /*!< Wakeup Pin Flag 6 */

+#define PWR_WKUPFR_WKUPF5_Pos          (4U)

+#define PWR_WKUPFR_WKUPF5_Msk          (0x1UL << PWR_WKUPFR_WKUPF5_Pos)        /*!< 0x00000010 */

+#define PWR_WKUPFR_WKUPF5              PWR_WKUPFR_WKUPF5_Msk                   /*!< Wakeup Pin Flag 5 */

+#define PWR_WKUPFR_WKUPF4_Pos          (3U)

+#define PWR_WKUPFR_WKUPF4_Msk          (0x1UL << PWR_WKUPFR_WKUPF4_Pos)        /*!< 0x00000008 */

+#define PWR_WKUPFR_WKUPF4              PWR_WKUPFR_WKUPF4_Msk                   /*!< Wakeup Pin Flag 4 */

+#define PWR_WKUPFR_WKUPF3_Pos          (2U)

+#define PWR_WKUPFR_WKUPF3_Msk          (0x1UL << PWR_WKUPFR_WKUPF3_Pos)        /*!< 0x00000004 */

+#define PWR_WKUPFR_WKUPF3              PWR_WKUPFR_WKUPF3_Msk                   /*!< Wakeup Pin Flag 3 */

+#define PWR_WKUPFR_WKUPF2_Pos          (1U)

+#define PWR_WKUPFR_WKUPF2_Msk          (0x1UL << PWR_WKUPFR_WKUPF2_Pos)        /*!< 0x00000002 */

+#define PWR_WKUPFR_WKUPF2              PWR_WKUPFR_WKUPF2_Msk                   /*!< Wakeup Pin Flag 2 */

+#define PWR_WKUPFR_WKUPF1_Pos          (0U)

+#define PWR_WKUPFR_WKUPF1_Msk          (0x1UL << PWR_WKUPFR_WKUPF1_Pos)        /*!< 0x00000001 */

+#define PWR_WKUPFR_WKUPF1              PWR_WKUPFR_WKUPF1_Msk                   /*!< Wakeup Pin Flag 1 */

+

+/******************  Bit definition for PWR_WKUPEPR register  *****************/

+#define PWR_WKUPEPR_WKUPPUPD6_Pos      (26U)

+#define PWR_WKUPEPR_WKUPPUPD6_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x0C000000 */

+#define PWR_WKUPEPR_WKUPPUPD6          PWR_WKUPEPR_WKUPPUPD6_Msk               /*!< Wakeup Pin pull configuration for WKUP6 */

+#define PWR_WKUPEPR_WKUPPUPD6_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x04000000 */

+#define PWR_WKUPEPR_WKUPPUPD6_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x08000000 */

+#define PWR_WKUPEPR_WKUPPUPD5_Pos      (24U)

+#define PWR_WKUPEPR_WKUPPUPD5_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x03000000 */

+#define PWR_WKUPEPR_WKUPPUPD5          PWR_WKUPEPR_WKUPPUPD5_Msk               /*!< Wakeup Pin pull configuration for WKUP5 */

+#define PWR_WKUPEPR_WKUPPUPD5_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x01000000 */

+#define PWR_WKUPEPR_WKUPPUPD5_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x02000000 */

+#define PWR_WKUPEPR_WKUPPUPD4_Pos      (22U)

+#define PWR_WKUPEPR_WKUPPUPD4_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00C00000 */

+#define PWR_WKUPEPR_WKUPPUPD4          PWR_WKUPEPR_WKUPPUPD4_Msk               /*!< Wakeup Pin pull configuration for WKUP4 */

+#define PWR_WKUPEPR_WKUPPUPD4_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00400000 */

+#define PWR_WKUPEPR_WKUPPUPD4_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00800000 */

+#define PWR_WKUPEPR_WKUPPUPD3_Pos      (20U)

+#define PWR_WKUPEPR_WKUPPUPD3_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00300000 */

+#define PWR_WKUPEPR_WKUPPUPD3          PWR_WKUPEPR_WKUPPUPD3_Msk               /*!< Wakeup Pin pull configuration for WKUP3 */

+#define PWR_WKUPEPR_WKUPPUPD3_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00100000 */

+#define PWR_WKUPEPR_WKUPPUPD3_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00200000 */

+#define PWR_WKUPEPR_WKUPPUPD2_Pos      (18U)

+#define PWR_WKUPEPR_WKUPPUPD2_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x000C0000 */

+#define PWR_WKUPEPR_WKUPPUPD2          PWR_WKUPEPR_WKUPPUPD2_Msk               /*!< Wakeup Pin pull configuration for WKUP2 */

+#define PWR_WKUPEPR_WKUPPUPD2_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00040000 */

+#define PWR_WKUPEPR_WKUPPUPD2_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00080000 */

+#define PWR_WKUPEPR_WKUPPUPD1_Pos      (16U)

+#define PWR_WKUPEPR_WKUPPUPD1_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00030000 */

+#define PWR_WKUPEPR_WKUPPUPD1          PWR_WKUPEPR_WKUPPUPD1_Msk               /*!< Wakeup Pin pull configuration for WKUP1 */

+#define PWR_WKUPEPR_WKUPPUPD1_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00010000 */

+#define PWR_WKUPEPR_WKUPPUPD1_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00020000 */

+#define PWR_WKUPEPR_WKUPP6_Pos         (13U)

+#define PWR_WKUPEPR_WKUPP6_Msk         (0x1UL << PWR_WKUPEPR_WKUPP6_Pos)       /*!< 0x00002000 */

+#define PWR_WKUPEPR_WKUPP6             PWR_WKUPEPR_WKUPP6_Msk                  /*!< Wakeup Pin Polarity for WKUP6 */

+#define PWR_WKUPEPR_WKUPP5_Pos         (12U)

+#define PWR_WKUPEPR_WKUPP5_Msk         (0x1UL << PWR_WKUPEPR_WKUPP5_Pos)       /*!< 0x00001000 */

+#define PWR_WKUPEPR_WKUPP5             PWR_WKUPEPR_WKUPP5_Msk                  /*!< Wakeup Pin Polarity for WKUP5 */

+#define PWR_WKUPEPR_WKUPP4_Pos         (11U)

+#define PWR_WKUPEPR_WKUPP4_Msk         (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)       /*!< 0x00000800 */

+#define PWR_WKUPEPR_WKUPP4             PWR_WKUPEPR_WKUPP4_Msk                  /*!< Wakeup Pin Polarity for WKUP4 */

+#define PWR_WKUPEPR_WKUPP3_Pos         (10U)

+#define PWR_WKUPEPR_WKUPP3_Msk         (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)       /*!< 0x00000400 */

+#define PWR_WKUPEPR_WKUPP3             PWR_WKUPEPR_WKUPP3_Msk                  /*!< Wakeup Pin Polarity for WKUP3 */

+#define PWR_WKUPEPR_WKUPP2_Pos         (9U)

+#define PWR_WKUPEPR_WKUPP2_Msk         (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)       /*!< 0x00000200 */

+#define PWR_WKUPEPR_WKUPP2             PWR_WKUPEPR_WKUPP2_Msk                  /*!< Wakeup Pin Polarity for WKUP2 */

+#define PWR_WKUPEPR_WKUPP1_Pos         (8U)

+#define PWR_WKUPEPR_WKUPP1_Msk         (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)       /*!< 0x00000100 */

+#define PWR_WKUPEPR_WKUPP1             PWR_WKUPEPR_WKUPP1_Msk                  /*!< Wakeup Pin Polarity for WKUP1 */

+#define PWR_WKUPEPR_WKUPEN6_Pos        (5U)

+#define PWR_WKUPEPR_WKUPEN6_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos)      /*!< 0x00000020 */

+#define PWR_WKUPEPR_WKUPEN6            PWR_WKUPEPR_WKUPEN6_Msk                 /*!< Enable Wakeup Pin WKUP6 */

+#define PWR_WKUPEPR_WKUPEN5_Pos        (4U)

+#define PWR_WKUPEPR_WKUPEN5_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos)      /*!< 0x00000010 */

+#define PWR_WKUPEPR_WKUPEN5            PWR_WKUPEPR_WKUPEN5_Msk                 /*!< Enable Wakeup Pin WKUP5 */

+#define PWR_WKUPEPR_WKUPEN4_Pos        (3U)

+#define PWR_WKUPEPR_WKUPEN4_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)      /*!< 0x00000008 */

+#define PWR_WKUPEPR_WKUPEN4            PWR_WKUPEPR_WKUPEN4_Msk                 /*!< Enable Wakeup Pin WKUP4 */

+#define PWR_WKUPEPR_WKUPEN3_Pos        (2U)

+#define PWR_WKUPEPR_WKUPEN3_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)      /*!< 0x00000004 */

+#define PWR_WKUPEPR_WKUPEN3            PWR_WKUPEPR_WKUPEN3_Msk                 /*!< Enable Wakeup Pin WKUP3 */

+#define PWR_WKUPEPR_WKUPEN2_Pos        (1U)

+#define PWR_WKUPEPR_WKUPEN2_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)      /*!< 0x00000002 */

+#define PWR_WKUPEPR_WKUPEN2            PWR_WKUPEPR_WKUPEN2_Msk                 /*!< Enable Wakeup Pin WKUP2 */

+#define PWR_WKUPEPR_WKUPEN1_Pos        (0U)

+#define PWR_WKUPEPR_WKUPEN1_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)      /*!< 0x00000001 */

+#define PWR_WKUPEPR_WKUPEN1            PWR_WKUPEPR_WKUPEN1_Msk                 /*!< Enable Wakeup Pin WKUP1 */

+#define PWR_WKUPEPR_WKUPEN_Pos         (0U)

+#define PWR_WKUPEPR_WKUPEN_Msk         (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos)      /*!< 0x0000003F */

+#define PWR_WKUPEPR_WKUPEN             PWR_WKUPEPR_WKUPEN_Msk                  /*!< Enable all Wakeup Pin */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Reset and Clock Control                            */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  RCC VERSION  ********************************/

+#define RCC_VER_X

+

+/********************  Bit definition for RCC_CR register  ********************/

+#define RCC_CR_HSION_Pos                       (0U)

+#define RCC_CR_HSION_Msk                       (0x1UL << RCC_CR_HSION_Pos)     /*!< 0x00000001 */

+#define RCC_CR_HSION                           RCC_CR_HSION_Msk                /*!< Internal High Speed clock enable */

+#define RCC_CR_HSIKERON_Pos                    (1U)

+#define RCC_CR_HSIKERON_Msk                    (0x1UL << RCC_CR_HSIKERON_Pos)  /*!< 0x00000002 */

+#define RCC_CR_HSIKERON                        RCC_CR_HSIKERON_Msk             /*!< Internal High Speed clock enable for some IPs Kernel */

+#define RCC_CR_HSIRDY_Pos                      (2U)

+#define RCC_CR_HSIRDY_Msk                      (0x1UL << RCC_CR_HSIRDY_Pos)    /*!< 0x00000004 */

+#define RCC_CR_HSIRDY                          RCC_CR_HSIRDY_Msk               /*!< Internal High Speed clock ready flag */

+#define RCC_CR_HSIDIV_Pos                      (3U)

+#define RCC_CR_HSIDIV_Msk                      (0x3UL << RCC_CR_HSIDIV_Pos)    /*!< 0x00000018 */

+#define RCC_CR_HSIDIV                          RCC_CR_HSIDIV_Msk               /*!< Internal High Speed clock divider selection */

+#define RCC_CR_HSIDIV_1                        (0x0UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000000 */

+#define RCC_CR_HSIDIV_2                        (0x1UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000008 */

+#define RCC_CR_HSIDIV_4                        (0x2UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000010 */

+#define RCC_CR_HSIDIV_8                        (0x3UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000018 */

+

+#define RCC_CR_HSIDIVF_Pos                     (5U)

+#define RCC_CR_HSIDIVF_Msk                     (0x1UL << RCC_CR_HSIDIVF_Pos)   /*!< 0x00000020 */

+#define RCC_CR_HSIDIVF                         RCC_CR_HSIDIVF_Msk              /*!< HSI Divider flag */

+#define RCC_CR_CSION_Pos                       (7U)

+#define RCC_CR_CSION_Msk                       (0x1UL << RCC_CR_CSION_Pos)     /*!< 0x00000080 */

+#define RCC_CR_CSION                           RCC_CR_CSION_Msk                /*!< The Internal RC 4MHz oscillator clock enable */

+#define RCC_CR_CSIRDY_Pos                      (8U)

+#define RCC_CR_CSIRDY_Msk                      (0x1UL << RCC_CR_CSIRDY_Pos)    /*!< 0x00000100 */

+#define RCC_CR_CSIRDY                          RCC_CR_CSIRDY_Msk               /*!< The Internal RC 4MHz oscillator clock ready */

+#define RCC_CR_CSIKERON_Pos                    (9U)

+#define RCC_CR_CSIKERON_Msk                    (0x1UL << RCC_CR_CSIKERON_Pos)  /*!< 0x00000200 */

+#define RCC_CR_CSIKERON                        RCC_CR_CSIKERON_Msk             /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */

+#define RCC_CR_HSI48ON_Pos                     (12U)

+#define RCC_CR_HSI48ON_Msk                     (0x1UL << RCC_CR_HSI48ON_Pos)   /*!< 0x00001000 */

+#define RCC_CR_HSI48ON                         RCC_CR_HSI48ON_Msk              /*!< HSI48 clock enable clock enable  */

+#define RCC_CR_HSI48RDY_Pos                    (13U)

+#define RCC_CR_HSI48RDY_Msk                    (0x1UL << RCC_CR_HSI48RDY_Pos)  /*!< 0x00002000 */

+#define RCC_CR_HSI48RDY                        RCC_CR_HSI48RDY_Msk             /*!< HSI48 clock ready */

+

+#define RCC_CR_D1CKRDY_Pos                     (14U)

+#define RCC_CR_D1CKRDY_Msk                     (0x1UL << RCC_CR_D1CKRDY_Pos)   /*!< 0x00004000 */

+#define RCC_CR_D1CKRDY                         RCC_CR_D1CKRDY_Msk              /*!< D1 domain clocks ready flag  */

+#define RCC_CR_D2CKRDY_Pos                     (15U)

+#define RCC_CR_D2CKRDY_Msk                     (0x1UL << RCC_CR_D2CKRDY_Pos)   /*!< 0x00008000 */

+#define RCC_CR_D2CKRDY                         RCC_CR_D2CKRDY_Msk              /*!< D2 domain clocks ready flag */

+

+#define RCC_CR_HSEON_Pos                       (16U)

+#define RCC_CR_HSEON_Msk                       (0x1UL << RCC_CR_HSEON_Pos)     /*!< 0x00010000 */

+#define RCC_CR_HSEON                           RCC_CR_HSEON_Msk                /*!< External High Speed clock enable */

+#define RCC_CR_HSERDY_Pos                      (17U)

+#define RCC_CR_HSERDY_Msk                      (0x1UL << RCC_CR_HSERDY_Pos)    /*!< 0x00020000 */

+#define RCC_CR_HSERDY                          RCC_CR_HSERDY_Msk               /*!< External High Speed clock ready */

+#define RCC_CR_HSEBYP_Pos                      (18U)

+#define RCC_CR_HSEBYP_Msk                      (0x1UL << RCC_CR_HSEBYP_Pos)    /*!< 0x00040000 */

+#define RCC_CR_HSEBYP                          RCC_CR_HSEBYP_Msk               /*!< External High Speed clock Bypass */

+#define RCC_CR_CSSHSEON_Pos                    (19U)

+#define RCC_CR_CSSHSEON_Msk                    (0x1UL << RCC_CR_CSSHSEON_Pos)  /*!< 0x00080000 */

+#define RCC_CR_CSSHSEON                        RCC_CR_CSSHSEON_Msk             /*!< HSE Clock security System enable */

+

+

+#define RCC_CR_PLL1ON_Pos                      (24U)

+#define RCC_CR_PLL1ON_Msk                      (0x1UL << RCC_CR_PLL1ON_Pos)    /*!< 0x01000000 */

+#define RCC_CR_PLL1ON                          RCC_CR_PLL1ON_Msk               /*!< System PLL1 clock enable */

+#define RCC_CR_PLL1RDY_Pos                     (25U)

+#define RCC_CR_PLL1RDY_Msk                     (0x1UL << RCC_CR_PLL1RDY_Pos)   /*!< 0x02000000 */

+#define RCC_CR_PLL1RDY                         RCC_CR_PLL1RDY_Msk              /*!< System PLL1 clock ready */

+#define RCC_CR_PLL2ON_Pos                      (26U)

+#define RCC_CR_PLL2ON_Msk                      (0x1UL << RCC_CR_PLL2ON_Pos)    /*!< 0x04000000 */

+#define RCC_CR_PLL2ON                          RCC_CR_PLL2ON_Msk               /*!< System PLL2 clock enable */

+#define RCC_CR_PLL2RDY_Pos                     (27U)

+#define RCC_CR_PLL2RDY_Msk                     (0x1UL << RCC_CR_PLL2RDY_Pos)   /*!< 0x08000000 */

+#define RCC_CR_PLL2RDY                         RCC_CR_PLL2RDY_Msk              /*!< System PLL2 clock ready */

+#define RCC_CR_PLL3ON_Pos                      (28U)

+#define RCC_CR_PLL3ON_Msk                      (0x1UL << RCC_CR_PLL3ON_Pos)    /*!< 0x10000000 */

+#define RCC_CR_PLL3ON                          RCC_CR_PLL3ON_Msk               /*!< System PLL3 clock enable */

+#define RCC_CR_PLL3RDY_Pos                     (29U)

+#define RCC_CR_PLL3RDY_Msk                     (0x1UL << RCC_CR_PLL3RDY_Pos)   /*!< 0x20000000 */

+#define RCC_CR_PLL3RDY                         RCC_CR_PLL3RDY_Msk              /*!< System PLL3 clock ready */

+

+/*Legacy */

+#define RCC_CR_PLLON_Pos                       (24U)

+#define RCC_CR_PLLON_Msk                       (0x1UL << RCC_CR_PLLON_Pos)     /*!< 0x01000000 */

+#define RCC_CR_PLLON                           RCC_CR_PLLON_Msk                /*!< System PLL clock enable */

+#define RCC_CR_PLLRDY_Pos                      (25U)

+#define RCC_CR_PLLRDY_Msk                      (0x1UL << RCC_CR_PLLRDY_Pos)    /*!< 0x02000000 */

+#define RCC_CR_PLLRDY                          RCC_CR_PLLRDY_Msk               /*!< System PLL clock ready */

+

+/********************  Bit definition for RCC_HSICFGR register  ***************/

+/*!< HSICAL configuration */

+#define RCC_HSICFGR_HSICAL_Pos                 (0U)

+#define RCC_HSICFGR_HSICAL_Msk                 (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */

+#define RCC_HSICFGR_HSICAL                     RCC_HSICFGR_HSICAL_Msk          /*!< HSICAL[11:0] bits */

+#define RCC_HSICFGR_HSICAL_0                   (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */

+#define RCC_HSICFGR_HSICAL_1                   (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */

+#define RCC_HSICFGR_HSICAL_2                   (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */

+#define RCC_HSICFGR_HSICAL_3                   (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */

+#define RCC_HSICFGR_HSICAL_4                   (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */

+#define RCC_HSICFGR_HSICAL_5                   (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */

+#define RCC_HSICFGR_HSICAL_6                   (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */

+#define RCC_HSICFGR_HSICAL_7                   (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */

+#define RCC_HSICFGR_HSICAL_8                   (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */

+#define RCC_HSICFGR_HSICAL_9                   (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */

+#define RCC_HSICFGR_HSICAL_10                  (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */

+#define RCC_HSICFGR_HSICAL_11                  (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */

+

+/*!< HSITRIM configuration */

+#define RCC_HSICFGR_HSITRIM_Pos                (24U)

+#define RCC_HSICFGR_HSITRIM_Msk                (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */

+#define RCC_HSICFGR_HSITRIM                    RCC_HSICFGR_HSITRIM_Msk         /*!< HSITRIM[6:0] bits */

+#define RCC_HSICFGR_HSITRIM_0                  (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */

+#define RCC_HSICFGR_HSITRIM_1                  (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */

+#define RCC_HSICFGR_HSITRIM_2                  (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */

+#define RCC_HSICFGR_HSITRIM_3                  (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */

+#define RCC_HSICFGR_HSITRIM_4                  (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */

+#define RCC_HSICFGR_HSITRIM_5                  (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */

+#define RCC_HSICFGR_HSITRIM_6                  (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */

+

+

+/********************  Bit definition for RCC_CRRCR register  *****************/

+

+/*!< HSI48CAL configuration */

+#define RCC_CRRCR_HSI48CAL_Pos                 (0U)

+#define RCC_CRRCR_HSI48CAL_Msk                 (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */

+#define RCC_CRRCR_HSI48CAL                     RCC_CRRCR_HSI48CAL_Msk          /*!< HSI48CAL[9:0] bits */

+#define RCC_CRRCR_HSI48CAL_0                   (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */

+#define RCC_CRRCR_HSI48CAL_1                   (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */

+#define RCC_CRRCR_HSI48CAL_2                   (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */

+#define RCC_CRRCR_HSI48CAL_3                   (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */

+#define RCC_CRRCR_HSI48CAL_4                   (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */

+#define RCC_CRRCR_HSI48CAL_5                   (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */

+#define RCC_CRRCR_HSI48CAL_6                   (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */

+#define RCC_CRRCR_HSI48CAL_7                   (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */

+#define RCC_CRRCR_HSI48CAL_8                   (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */

+#define RCC_CRRCR_HSI48CAL_9                   (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */

+

+

+/********************  Bit definition for RCC_CSICFGR register  *****************/

+/*!< CSICAL configuration */

+#define RCC_CSICFGR_CSICAL_Pos                 (0U)

+#define RCC_CSICFGR_CSICAL_Msk                 (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */

+#define RCC_CSICFGR_CSICAL                     RCC_CSICFGR_CSICAL_Msk          /*!< CSICAL[7:0] bits */

+#define RCC_CSICFGR_CSICAL_0                   (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */

+#define RCC_CSICFGR_CSICAL_1                   (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */

+#define RCC_CSICFGR_CSICAL_2                   (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */

+#define RCC_CSICFGR_CSICAL_3                   (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */

+#define RCC_CSICFGR_CSICAL_4                   (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */

+#define RCC_CSICFGR_CSICAL_5                   (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */

+#define RCC_CSICFGR_CSICAL_6                   (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */

+#define RCC_CSICFGR_CSICAL_7                   (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */

+

+/*!< CSITRIM configuration */

+#define RCC_CSICFGR_CSITRIM_Pos                (24U)

+#define RCC_CSICFGR_CSITRIM_Msk                (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */

+#define RCC_CSICFGR_CSITRIM                    RCC_CSICFGR_CSITRIM_Msk         /*!< CSITRIM[5:0] bits */

+#define RCC_CSICFGR_CSITRIM_0                  (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */

+#define RCC_CSICFGR_CSITRIM_1                  (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */

+#define RCC_CSICFGR_CSITRIM_2                  (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */

+#define RCC_CSICFGR_CSITRIM_3                  (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */

+#define RCC_CSICFGR_CSITRIM_4                  (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */

+#define RCC_CSICFGR_CSITRIM_5                  (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */

+

+/********************  Bit definition for RCC_CFGR register  ******************/

+/*!< SW configuration */

+#define RCC_CFGR_SW_Pos                        (0U)

+#define RCC_CFGR_SW_Msk                        (0x7UL << RCC_CFGR_SW_Pos)           /*!< 0x00000007 */

+#define RCC_CFGR_SW                            RCC_CFGR_SW_Msk                     /*!< SW[2:0] bits (System clock Switch) */

+#define RCC_CFGR_SW_0                          (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */

+#define RCC_CFGR_SW_1                          (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */

+#define RCC_CFGR_SW_2                          (0x4UL << RCC_CFGR_SW_Pos)           /*!< 0x00000004 */

+

+#define RCC_CFGR_SW_HSI                        (0x00000000UL)                       /*!< HSI selection as system clock */

+#define RCC_CFGR_SW_CSI                        (0x00000001UL)                       /*!< CSI selection as system clock */

+#define RCC_CFGR_SW_HSE                        (0x00000002UL)                       /*!< HSE selection as system clock */

+#define RCC_CFGR_SW_PLL1                       (0x00000003UL)                       /*!< PLL1 selection as system clock */

+

+/*!< SWS configuration */

+#define RCC_CFGR_SWS_Pos                       (3U)

+#define RCC_CFGR_SWS_Msk                       (0x7UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000038 */

+#define RCC_CFGR_SWS                           RCC_CFGR_SWS_Msk                    /*!< SWS[2:0] bits (System Clock Switch Status) */

+#define RCC_CFGR_SWS_0                         (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */

+#define RCC_CFGR_SWS_1                         (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000010 */

+#define RCC_CFGR_SWS_2                         (0x4UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000020 */

+

+#define RCC_CFGR_SWS_HSI                       (0x00000000UL)                       /*!< HSI used as system clock */

+#define RCC_CFGR_SWS_CSI                       (0x00000008UL)                       /*!< CSI used as system clock */

+#define RCC_CFGR_SWS_HSE                       (0x00000010UL)                       /*!< HSE used as system clock */

+#define RCC_CFGR_SWS_PLL1                      (0x00000018UL)                       /*!< PLL1 used as system clock */

+

+#define RCC_CFGR_STOPWUCK_Pos                  (6U)

+#define RCC_CFGR_STOPWUCK_Msk                  (0x1UL << RCC_CFGR_STOPWUCK_Pos)     /*!< 0x00000040 */

+#define RCC_CFGR_STOPWUCK                      RCC_CFGR_STOPWUCK_Msk                /*!< Wake Up from stop and CSS backup clock selection */

+

+#define RCC_CFGR_STOPKERWUCK_Pos               (7U)

+#define RCC_CFGR_STOPKERWUCK_Msk               (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)  /*!< 0x00000080 */

+#define RCC_CFGR_STOPKERWUCK                   RCC_CFGR_STOPKERWUCK_Msk             /*!< Kernel Clock Selection after a Wake Up from STOP */

+

+/*!< RTCPRE configuration */

+#define RCC_CFGR_RTCPRE_Pos                    (8U)

+#define RCC_CFGR_RTCPRE_Msk                    (0x3FUL << RCC_CFGR_RTCPRE_Pos)

+#define RCC_CFGR_RTCPRE                        RCC_CFGR_RTCPRE_Msk                  /*!< 0x00003F00 */

+#define RCC_CFGR_RTCPRE_0                      (0x1UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000100 */

+#define RCC_CFGR_RTCPRE_1                      (0x2UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000200 */

+#define RCC_CFGR_RTCPRE_2                      (0x4UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000400 */

+#define RCC_CFGR_RTCPRE_3                      (0x8UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000800 */

+#define RCC_CFGR_RTCPRE_4                      (0x10UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00001000 */

+#define RCC_CFGR_RTCPRE_5                      (0x20UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00002000 */

+

+/*!< HRTIMSEL configuration */

+#define RCC_CFGR_HRTIMSEL_Pos                  (14U)

+#define RCC_CFGR_HRTIMSEL_Msk                  (0x1UL << RCC_CFGR_HRTIMSEL_Pos)

+#define RCC_CFGR_HRTIMSEL                      RCC_CFGR_HRTIMSEL_Msk                /*!< 0x00004000 */

+

+/*!< TIMPRE configuration */

+#define RCC_CFGR_TIMPRE_Pos                    (15U)

+#define RCC_CFGR_TIMPRE_Msk                    (0x1UL << RCC_CFGR_TIMPRE_Pos)

+#define RCC_CFGR_TIMPRE                        RCC_CFGR_TIMPRE_Msk                  /*!< 0x00008000 */

+

+/*!< MCO1 configuration */

+#define RCC_CFGR_MCO1_Pos                      (22U)

+#define RCC_CFGR_MCO1_Msk                      (0x7UL << RCC_CFGR_MCO1_Pos)

+#define RCC_CFGR_MCO1                          RCC_CFGR_MCO1_Msk                       /*!< 0x01C00000 */

+#define RCC_CFGR_MCO1_0                        (0x1UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00400000 */

+#define RCC_CFGR_MCO1_1                        (0x2UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00800000 */

+#define RCC_CFGR_MCO1_2                        (0x4UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x01000000 */

+

+#define RCC_CFGR_MCO1PRE_Pos                   (18U)

+#define RCC_CFGR_MCO1PRE_Msk                   (0xFUL << RCC_CFGR_MCO1PRE_Pos)

+#define RCC_CFGR_MCO1PRE                       RCC_CFGR_MCO1PRE_Msk                    /*!< 0x003C0000 */

+#define RCC_CFGR_MCO1PRE_0                     (0x1UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00040000 */

+#define RCC_CFGR_MCO1PRE_1                     (0x2UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00080000 */

+#define RCC_CFGR_MCO1PRE_2                     (0x4UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00100000 */

+#define RCC_CFGR_MCO1PRE_3                     (0x8UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00200000 */

+

+#define RCC_CFGR_MCO2PRE_Pos                   (25U)

+#define RCC_CFGR_MCO2PRE_Msk                   (0xFUL << RCC_CFGR_MCO2PRE_Pos)

+#define RCC_CFGR_MCO2PRE                       RCC_CFGR_MCO2PRE_Msk                    /*!< 0x1E000000 */

+#define RCC_CFGR_MCO2PRE_0                     (0x1UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x02000000 */

+#define RCC_CFGR_MCO2PRE_1                     (0x2UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x04000000 */

+#define RCC_CFGR_MCO2PRE_2                     (0x4UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x08000000 */

+#define RCC_CFGR_MCO2PRE_3                     (0x8UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x10000000 */

+

+#define RCC_CFGR_MCO2_Pos                      (29U)

+#define RCC_CFGR_MCO2_Msk                      (0x7UL << RCC_CFGR_MCO2_Pos)

+#define RCC_CFGR_MCO2                          RCC_CFGR_MCO2_Msk                       /*!< 0xE0000000 */

+#define RCC_CFGR_MCO2_0                        (0x1UL << RCC_CFGR_MCO2_Pos)             /*!< 0x20000000 */

+#define RCC_CFGR_MCO2_1                        (0x2UL << RCC_CFGR_MCO2_Pos)             /*!< 0x40000000 */

+#define RCC_CFGR_MCO2_2                        (0x4UL << RCC_CFGR_MCO2_Pos)             /*!< 0x80000000 */

+

+/********************  Bit definition for RCC_D1CFGR register  ******************/

+/*!< D1HPRE configuration */

+#define RCC_D1CFGR_HPRE_Pos                    (0U)

+#define RCC_D1CFGR_HPRE_Msk                    (0xFUL << RCC_D1CFGR_HPRE_Pos)  /*!< 0x0000000F */

+#define RCC_D1CFGR_HPRE                        RCC_D1CFGR_HPRE_Msk             /*!< HPRE[3:0] bits (AHB3 prescaler) */

+#define RCC_D1CFGR_HPRE_0                      (0x1UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000001 */

+#define RCC_D1CFGR_HPRE_1                      (0x2UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000002 */

+#define RCC_D1CFGR_HPRE_2                      (0x4UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000004 */

+#define RCC_D1CFGR_HPRE_3                      (0x8UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000008 */

+

+

+#define RCC_D1CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)          /*!< AHB3 Clock not divided */

+#define RCC_D1CFGR_HPRE_DIV2_Pos               (3U)

+#define RCC_D1CFGR_HPRE_DIV2_Msk               (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */

+#define RCC_D1CFGR_HPRE_DIV2                   RCC_D1CFGR_HPRE_DIV2_Msk        /*!< AHB3 Clock divided by 2 */

+#define RCC_D1CFGR_HPRE_DIV4_Pos               (0U)

+#define RCC_D1CFGR_HPRE_DIV4_Msk               (0x9UL << RCC_D1CFGR_HPRE_DIV4_Pos) /*!< 0x00000009 */

+#define RCC_D1CFGR_HPRE_DIV4                   RCC_D1CFGR_HPRE_DIV4_Msk        /*!< AHB3 Clock divided by 4 */

+#define RCC_D1CFGR_HPRE_DIV8_Pos               (1U)

+#define RCC_D1CFGR_HPRE_DIV8_Msk               (0x5UL << RCC_D1CFGR_HPRE_DIV8_Pos) /*!< 0x0000000A */

+#define RCC_D1CFGR_HPRE_DIV8                   RCC_D1CFGR_HPRE_DIV8_Msk        /*!< AHB3 Clock divided by 8 */

+#define RCC_D1CFGR_HPRE_DIV16_Pos              (0U)

+#define RCC_D1CFGR_HPRE_DIV16_Msk              (0xBUL << RCC_D1CFGR_HPRE_DIV16_Pos) /*!< 0x0000000B */

+#define RCC_D1CFGR_HPRE_DIV16                  RCC_D1CFGR_HPRE_DIV16_Msk       /*!< AHB3 Clock divided by 16 */

+#define RCC_D1CFGR_HPRE_DIV64_Pos              (2U)

+#define RCC_D1CFGR_HPRE_DIV64_Msk              (0x3UL << RCC_D1CFGR_HPRE_DIV64_Pos) /*!< 0x0000000C */

+#define RCC_D1CFGR_HPRE_DIV64                  RCC_D1CFGR_HPRE_DIV64_Msk       /*!< AHB3 Clock divided by 64 */

+#define RCC_D1CFGR_HPRE_DIV128_Pos             (0U)

+#define RCC_D1CFGR_HPRE_DIV128_Msk             (0xDUL << RCC_D1CFGR_HPRE_DIV128_Pos) /*!< 0x0000000D */

+#define RCC_D1CFGR_HPRE_DIV128                 RCC_D1CFGR_HPRE_DIV128_Msk      /*!< AHB3 Clock divided by 128 */

+#define RCC_D1CFGR_HPRE_DIV256_Pos             (1U)

+#define RCC_D1CFGR_HPRE_DIV256_Msk             (0x7UL << RCC_D1CFGR_HPRE_DIV256_Pos) /*!< 0x0000000E */

+#define RCC_D1CFGR_HPRE_DIV256                 RCC_D1CFGR_HPRE_DIV256_Msk      /*!< AHB3 Clock divided by 256 */

+#define RCC_D1CFGR_HPRE_DIV512_Pos             (0U)

+#define RCC_D1CFGR_HPRE_DIV512_Msk             (0xFUL << RCC_D1CFGR_HPRE_DIV512_Pos) /*!< 0x0000000F */

+#define RCC_D1CFGR_HPRE_DIV512                 RCC_D1CFGR_HPRE_DIV512_Msk      /*!< AHB3 Clock divided by 512 */

+

+/*!< D1PPRE configuration */

+#define RCC_D1CFGR_D1PPRE_Pos                  (4U)

+#define RCC_D1CFGR_D1PPRE_Msk                  (0x7UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000070 */

+#define RCC_D1CFGR_D1PPRE                      RCC_D1CFGR_D1PPRE_Msk           /*!< D1PRE[2:0] bits (APB3 prescaler) */

+#define RCC_D1CFGR_D1PPRE_0                    (0x1UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000010 */

+#define RCC_D1CFGR_D1PPRE_1                    (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */

+#define RCC_D1CFGR_D1PPRE_2                    (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */

+

+#define RCC_D1CFGR_D1PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB3 clock not divided */

+#define RCC_D1CFGR_D1PPRE_DIV2_Pos             (6U)

+#define RCC_D1CFGR_D1PPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_D1CFGR_D1PPRE_DIV2                 RCC_D1CFGR_D1PPRE_DIV2_Msk      /*!< APB3 clock divided by 2 */

+#define RCC_D1CFGR_D1PPRE_DIV4_Pos             (4U)

+#define RCC_D1CFGR_D1PPRE_DIV4_Msk             (0x5UL << RCC_D1CFGR_D1PPRE_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_D1CFGR_D1PPRE_DIV4                 RCC_D1CFGR_D1PPRE_DIV4_Msk      /*!< APB3 clock divided by 4 */

+#define RCC_D1CFGR_D1PPRE_DIV8_Pos             (5U)

+#define RCC_D1CFGR_D1PPRE_DIV8_Msk             (0x3UL << RCC_D1CFGR_D1PPRE_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_D1CFGR_D1PPRE_DIV8                 RCC_D1CFGR_D1PPRE_DIV8_Msk      /*!< APB3 clock divided by 8 */

+#define RCC_D1CFGR_D1PPRE_DIV16_Pos            (4U)

+#define RCC_D1CFGR_D1PPRE_DIV16_Msk            (0x7UL << RCC_D1CFGR_D1PPRE_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_D1CFGR_D1PPRE_DIV16                RCC_D1CFGR_D1PPRE_DIV16_Msk     /*!< APB3 clock divided by 16 */

+

+#define RCC_D1CFGR_D1CPRE_Pos                  (8U)

+#define RCC_D1CFGR_D1CPRE_Msk                  (0xFUL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000F00 */

+#define RCC_D1CFGR_D1CPRE                      RCC_D1CFGR_D1CPRE_Msk           /*!< D1CPRE[2:0] bits (Domain 1 Core prescaler) */

+#define RCC_D1CFGR_D1CPRE_0                    (0x1UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000100 */

+#define RCC_D1CFGR_D1CPRE_1                    (0x2UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000200 */

+#define RCC_D1CFGR_D1CPRE_2                    (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */

+#define RCC_D1CFGR_D1CPRE_3                    (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */

+

+#define RCC_D1CFGR_D1CPRE_DIV1                 ((uint32_t)0x00000000)          /*!< Domain 1 Core clock not divided */

+#define RCC_D1CFGR_D1CPRE_DIV2_Pos             (11U)

+#define RCC_D1CFGR_D1CPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */

+#define RCC_D1CFGR_D1CPRE_DIV2                 RCC_D1CFGR_D1CPRE_DIV2_Msk      /*!< Domain 1 Core clock divided by 2 */

+#define RCC_D1CFGR_D1CPRE_DIV4_Pos             (8U)

+#define RCC_D1CFGR_D1CPRE_DIV4_Msk             (0x9UL << RCC_D1CFGR_D1CPRE_DIV4_Pos) /*!< 0x00000900 */

+#define RCC_D1CFGR_D1CPRE_DIV4                 RCC_D1CFGR_D1CPRE_DIV4_Msk      /*!< Domain 1 Core clock divided by 4 */

+#define RCC_D1CFGR_D1CPRE_DIV8_Pos             (9U)

+#define RCC_D1CFGR_D1CPRE_DIV8_Msk             (0x5UL << RCC_D1CFGR_D1CPRE_DIV8_Pos) /*!< 0x00000A00 */

+#define RCC_D1CFGR_D1CPRE_DIV8                 RCC_D1CFGR_D1CPRE_DIV8_Msk      /*!< Domain 1 Core clock divided by 8 */

+#define RCC_D1CFGR_D1CPRE_DIV16_Pos            (8U)

+#define RCC_D1CFGR_D1CPRE_DIV16_Msk            (0xBUL << RCC_D1CFGR_D1CPRE_DIV16_Pos) /*!< 0x00000B00 */

+#define RCC_D1CFGR_D1CPRE_DIV16                RCC_D1CFGR_D1CPRE_DIV16_Msk     /*!< Domain 1 Core clock divided by 16 */

+#define RCC_D1CFGR_D1CPRE_DIV64_Pos            (10U)

+#define RCC_D1CFGR_D1CPRE_DIV64_Msk            (0x3UL << RCC_D1CFGR_D1CPRE_DIV64_Pos) /*!< 0x00000C00 */

+#define RCC_D1CFGR_D1CPRE_DIV64                RCC_D1CFGR_D1CPRE_DIV64_Msk     /*!< Domain 1 Core clock divided by 64 */

+#define RCC_D1CFGR_D1CPRE_DIV128_Pos           (8U)

+#define RCC_D1CFGR_D1CPRE_DIV128_Msk           (0xDUL << RCC_D1CFGR_D1CPRE_DIV128_Pos) /*!< 0x00000D00 */

+#define RCC_D1CFGR_D1CPRE_DIV128               RCC_D1CFGR_D1CPRE_DIV128_Msk    /*!< Domain 1 Core clock divided by 128 */

+#define RCC_D1CFGR_D1CPRE_DIV256_Pos           (9U)

+#define RCC_D1CFGR_D1CPRE_DIV256_Msk           (0x7UL << RCC_D1CFGR_D1CPRE_DIV256_Pos) /*!< 0x00000E00 */

+#define RCC_D1CFGR_D1CPRE_DIV256               RCC_D1CFGR_D1CPRE_DIV256_Msk    /*!< Domain 1 Core clock divided by 256 */

+#define RCC_D1CFGR_D1CPRE_DIV512_Pos           (8U)

+#define RCC_D1CFGR_D1CPRE_DIV512_Msk           (0xFUL << RCC_D1CFGR_D1CPRE_DIV512_Pos) /*!< 0x00000F00 */

+#define RCC_D1CFGR_D1CPRE_DIV512               RCC_D1CFGR_D1CPRE_DIV512_Msk    /*!< Domain 1 Core clock divided by 512 */

+

+/********************  Bit definition for RCC_D2CFGR register  ******************/

+/*!< D2PPRE1 configuration */

+#define RCC_D2CFGR_D2PPRE1_Pos                 (4U)

+#define RCC_D2CFGR_D2PPRE1_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000070 */

+#define RCC_D2CFGR_D2PPRE1                     RCC_D2CFGR_D2PPRE1_Msk          /*!< D1PPRE1[2:0] bits (APB1 prescaler) */

+#define RCC_D2CFGR_D2PPRE1_0                   (0x1UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000010 */

+#define RCC_D2CFGR_D2PPRE1_1                   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */

+#define RCC_D2CFGR_D2PPRE1_2                   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */

+

+#define RCC_D2CFGR_D2PPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */

+#define RCC_D2CFGR_D2PPRE1_DIV2_Pos            (6U)

+#define RCC_D2CFGR_D2PPRE1_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_D2CFGR_D2PPRE1_DIV2                RCC_D2CFGR_D2PPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */

+#define RCC_D2CFGR_D2PPRE1_DIV4_Pos            (4U)

+#define RCC_D2CFGR_D2PPRE1_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE1_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_D2CFGR_D2PPRE1_DIV4                RCC_D2CFGR_D2PPRE1_DIV4_Msk     /*!< APB1 clock divided by 4 */

+#define RCC_D2CFGR_D2PPRE1_DIV8_Pos            (5U)

+#define RCC_D2CFGR_D2PPRE1_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE1_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_D2CFGR_D2PPRE1_DIV8                RCC_D2CFGR_D2PPRE1_DIV8_Msk     /*!< APB1 clock divided by 8 */

+#define RCC_D2CFGR_D2PPRE1_DIV16_Pos           (4U)

+#define RCC_D2CFGR_D2PPRE1_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE1_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_D2CFGR_D2PPRE1_DIV16               RCC_D2CFGR_D2PPRE1_DIV16_Msk    /*!< APB1 clock divided by 16 */

+

+/*!< D2PPRE2 configuration */

+#define RCC_D2CFGR_D2PPRE2_Pos                 (8U)

+#define RCC_D2CFGR_D2PPRE2_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000700 */

+#define RCC_D2CFGR_D2PPRE2                     RCC_D2CFGR_D2PPRE2_Msk          /*!< D2PPRE2[2:0] bits (APB2 prescaler) */

+#define RCC_D2CFGR_D2PPRE2_0                   (0x1UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000100 */

+#define RCC_D2CFGR_D2PPRE2_1                   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */

+#define RCC_D2CFGR_D2PPRE2_2                   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */

+

+#define RCC_D2CFGR_D2PPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */

+#define RCC_D2CFGR_D2PPRE2_DIV2_Pos            (10U)

+#define RCC_D2CFGR_D2PPRE2_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */

+#define RCC_D2CFGR_D2PPRE2_DIV2                RCC_D2CFGR_D2PPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */

+#define RCC_D2CFGR_D2PPRE2_DIV4_Pos            (8U)

+#define RCC_D2CFGR_D2PPRE2_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE2_DIV4_Pos) /*!< 0x00000500 */

+#define RCC_D2CFGR_D2PPRE2_DIV4                RCC_D2CFGR_D2PPRE2_DIV4_Msk     /*!< APB2 clock divided by 4 */

+#define RCC_D2CFGR_D2PPRE2_DIV8_Pos            (9U)

+#define RCC_D2CFGR_D2PPRE2_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE2_DIV8_Pos) /*!< 0x00000600 */

+#define RCC_D2CFGR_D2PPRE2_DIV8                RCC_D2CFGR_D2PPRE2_DIV8_Msk     /*!< APB2 clock divided by 8 */

+#define RCC_D2CFGR_D2PPRE2_DIV16_Pos           (8U)

+#define RCC_D2CFGR_D2PPRE2_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE2_DIV16_Pos) /*!< 0x00000700 */

+#define RCC_D2CFGR_D2PPRE2_DIV16               RCC_D2CFGR_D2PPRE2_DIV16_Msk    /*!< APB2 clock divided by 16 */

+

+/********************  Bit definition for RCC_D3CFGR register  ******************/

+/*!< D3PPRE configuration */

+#define RCC_D3CFGR_D3PPRE_Pos                  (4U)

+#define RCC_D3CFGR_D3PPRE_Msk                  (0x7UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000070 */

+#define RCC_D3CFGR_D3PPRE                      RCC_D3CFGR_D3PPRE_Msk           /*!< D3PPRE1[2:0] bits (APB4 prescaler) */

+#define RCC_D3CFGR_D3PPRE_0                    (0x1UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000010 */

+#define RCC_D3CFGR_D3PPRE_1                    (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */

+#define RCC_D3CFGR_D3PPRE_2                    (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */

+

+#define RCC_D3CFGR_D3PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */

+#define RCC_D3CFGR_D3PPRE_DIV2_Pos             (6U)

+#define RCC_D3CFGR_D3PPRE_DIV2_Msk             (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_D3CFGR_D3PPRE_DIV2                 RCC_D3CFGR_D3PPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */

+#define RCC_D3CFGR_D3PPRE_DIV4_Pos             (4U)

+#define RCC_D3CFGR_D3PPRE_DIV4_Msk             (0x5UL << RCC_D3CFGR_D3PPRE_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_D3CFGR_D3PPRE_DIV4                 RCC_D3CFGR_D3PPRE_DIV4_Msk      /*!< APB4 clock divided by 4 */

+#define RCC_D3CFGR_D3PPRE_DIV8_Pos             (5U)

+#define RCC_D3CFGR_D3PPRE_DIV8_Msk             (0x3UL << RCC_D3CFGR_D3PPRE_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_D3CFGR_D3PPRE_DIV8                 RCC_D3CFGR_D3PPRE_DIV8_Msk      /*!< APB4 clock divided by 8 */

+#define RCC_D3CFGR_D3PPRE_DIV16_Pos            (4U)

+#define RCC_D3CFGR_D3PPRE_DIV16_Msk            (0x7UL << RCC_D3CFGR_D3PPRE_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_D3CFGR_D3PPRE_DIV16                RCC_D3CFGR_D3PPRE_DIV16_Msk     /*!< APB4 clock divided by 16 */

+

+/********************  Bit definition for RCC_PLLCKSELR register  *************/

+

+#define RCC_PLLCKSELR_PLLSRC_Pos               (0U)

+#define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */

+#define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk

+

+#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)

+#define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */

+#define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_HSE_Pos           (1U)

+#define RCC_PLLCKSELR_PLLSRC_HSE_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */

+#define RCC_PLLCKSELR_PLLSRC_HSE               RCC_PLLCKSELR_PLLSRC_HSE_Msk    /*!< HSE source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_NONE_Pos          (0U)

+#define RCC_PLLCKSELR_PLLSRC_NONE_Msk          (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */

+#define RCC_PLLCKSELR_PLLSRC_NONE              RCC_PLLCKSELR_PLLSRC_NONE_Msk   /*!< No source clock selected  */

+

+#define RCC_PLLCKSELR_DIVM1_Pos                (4U)

+#define RCC_PLLCKSELR_DIVM1_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */

+#define RCC_PLLCKSELR_DIVM1                    RCC_PLLCKSELR_DIVM1_Msk

+#define RCC_PLLCKSELR_DIVM1_0                  (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */

+#define RCC_PLLCKSELR_DIVM1_1                  (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */

+#define RCC_PLLCKSELR_DIVM1_2                  (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */

+#define RCC_PLLCKSELR_DIVM1_3                  (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */

+#define RCC_PLLCKSELR_DIVM1_4                  (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */

+#define RCC_PLLCKSELR_DIVM1_5                  (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */

+

+#define RCC_PLLCKSELR_DIVM2_Pos                (12U)

+#define RCC_PLLCKSELR_DIVM2_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */

+#define RCC_PLLCKSELR_DIVM2                    RCC_PLLCKSELR_DIVM2_Msk

+#define RCC_PLLCKSELR_DIVM2_0                  (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */

+#define RCC_PLLCKSELR_DIVM2_1                  (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */

+#define RCC_PLLCKSELR_DIVM2_2                  (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */

+#define RCC_PLLCKSELR_DIVM2_3                  (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */

+#define RCC_PLLCKSELR_DIVM2_4                  (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */

+#define RCC_PLLCKSELR_DIVM2_5                  (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */

+

+#define RCC_PLLCKSELR_DIVM3_Pos                (20U)

+#define RCC_PLLCKSELR_DIVM3_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */

+#define RCC_PLLCKSELR_DIVM3                    RCC_PLLCKSELR_DIVM3_Msk

+#define RCC_PLLCKSELR_DIVM3_0                  (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */

+#define RCC_PLLCKSELR_DIVM3_1                  (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */

+#define RCC_PLLCKSELR_DIVM3_2                  (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */

+#define RCC_PLLCKSELR_DIVM3_3                  (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */

+#define RCC_PLLCKSELR_DIVM3_4                  (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */

+#define RCC_PLLCKSELR_DIVM3_5                  (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */

+

+/********************  Bit definition for RCC_PLLCFGR register  ***************/

+

+#define RCC_PLLCFGR_PLL1FRACEN_Pos             (0U)

+#define RCC_PLLCFGR_PLL1FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */

+#define RCC_PLLCFGR_PLL1FRACEN                 RCC_PLLCFGR_PLL1FRACEN_Msk

+#define RCC_PLLCFGR_PLL1VCOSEL_Pos             (1U)

+#define RCC_PLLCFGR_PLL1VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */

+#define RCC_PLLCFGR_PLL1VCOSEL                 RCC_PLLCFGR_PLL1VCOSEL_Msk

+#define RCC_PLLCFGR_PLL1RGE_Pos                (2U)

+#define RCC_PLLCFGR_PLL1RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */

+#define RCC_PLLCFGR_PLL1RGE                    RCC_PLLCFGR_PLL1RGE_Msk

+#define RCC_PLLCFGR_PLL1RGE_0                  (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL1RGE_1                  (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */

+#define RCC_PLLCFGR_PLL1RGE_2                  (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */

+#define RCC_PLLCFGR_PLL1RGE_3                  (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */

+

+#define RCC_PLLCFGR_PLL2FRACEN_Pos             (4U)

+#define RCC_PLLCFGR_PLL2FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */

+#define RCC_PLLCFGR_PLL2FRACEN                 RCC_PLLCFGR_PLL2FRACEN_Msk

+#define RCC_PLLCFGR_PLL2VCOSEL_Pos             (5U)

+#define RCC_PLLCFGR_PLL2VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */

+#define RCC_PLLCFGR_PLL2VCOSEL                 RCC_PLLCFGR_PLL2VCOSEL_Msk

+#define RCC_PLLCFGR_PLL2RGE_Pos                (6U)

+#define RCC_PLLCFGR_PLL2RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */

+#define RCC_PLLCFGR_PLL2RGE                    RCC_PLLCFGR_PLL2RGE_Msk

+#define RCC_PLLCFGR_PLL2RGE_0                  (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL2RGE_1                  (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */

+#define RCC_PLLCFGR_PLL2RGE_2                  (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */

+#define RCC_PLLCFGR_PLL2RGE_3                  (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */

+

+#define RCC_PLLCFGR_PLL3FRACEN_Pos             (8U)

+#define RCC_PLLCFGR_PLL3FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */

+#define RCC_PLLCFGR_PLL3FRACEN                 RCC_PLLCFGR_PLL3FRACEN_Msk

+#define RCC_PLLCFGR_PLL3VCOSEL_Pos             (9U)

+#define RCC_PLLCFGR_PLL3VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */

+#define RCC_PLLCFGR_PLL3VCOSEL                 RCC_PLLCFGR_PLL3VCOSEL_Msk

+#define RCC_PLLCFGR_PLL3RGE_Pos                (10U)

+#define RCC_PLLCFGR_PLL3RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */

+#define RCC_PLLCFGR_PLL3RGE                    RCC_PLLCFGR_PLL3RGE_Msk

+#define RCC_PLLCFGR_PLL3RGE_0                  (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL3RGE_1                  (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */

+#define RCC_PLLCFGR_PLL3RGE_2                  (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */

+#define RCC_PLLCFGR_PLL3RGE_3                  (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */

+

+#define RCC_PLLCFGR_DIVP1EN_Pos                (16U)

+#define RCC_PLLCFGR_DIVP1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */

+#define RCC_PLLCFGR_DIVP1EN                    RCC_PLLCFGR_DIVP1EN_Msk

+#define RCC_PLLCFGR_DIVQ1EN_Pos                (17U)

+#define RCC_PLLCFGR_DIVQ1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */

+#define RCC_PLLCFGR_DIVQ1EN                    RCC_PLLCFGR_DIVQ1EN_Msk

+#define RCC_PLLCFGR_DIVR1EN_Pos                (18U)

+#define RCC_PLLCFGR_DIVR1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */

+#define RCC_PLLCFGR_DIVR1EN                    RCC_PLLCFGR_DIVR1EN_Msk

+

+#define RCC_PLLCFGR_DIVP2EN_Pos                (19U)

+#define RCC_PLLCFGR_DIVP2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */

+#define RCC_PLLCFGR_DIVP2EN                    RCC_PLLCFGR_DIVP2EN_Msk

+#define RCC_PLLCFGR_DIVQ2EN_Pos                (20U)

+#define RCC_PLLCFGR_DIVQ2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */

+#define RCC_PLLCFGR_DIVQ2EN                    RCC_PLLCFGR_DIVQ2EN_Msk

+#define RCC_PLLCFGR_DIVR2EN_Pos                (21U)

+#define RCC_PLLCFGR_DIVR2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */

+#define RCC_PLLCFGR_DIVR2EN                    RCC_PLLCFGR_DIVR2EN_Msk

+

+#define RCC_PLLCFGR_DIVP3EN_Pos                (22U)

+#define RCC_PLLCFGR_DIVP3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */

+#define RCC_PLLCFGR_DIVP3EN                    RCC_PLLCFGR_DIVP3EN_Msk

+#define RCC_PLLCFGR_DIVQ3EN_Pos                (23U)

+#define RCC_PLLCFGR_DIVQ3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */

+#define RCC_PLLCFGR_DIVQ3EN                    RCC_PLLCFGR_DIVQ3EN_Msk

+#define RCC_PLLCFGR_DIVR3EN_Pos                (24U)

+#define RCC_PLLCFGR_DIVR3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */

+#define RCC_PLLCFGR_DIVR3EN                    RCC_PLLCFGR_DIVR3EN_Msk

+

+

+/********************  Bit definition for RCC_PLL1DIVR register  ***************/

+#define RCC_PLL1DIVR_N1_Pos                    (0U)

+#define RCC_PLL1DIVR_N1_Msk                    (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */

+#define RCC_PLL1DIVR_N1                        RCC_PLL1DIVR_N1_Msk

+#define RCC_PLL1DIVR_P1_Pos                    (9U)

+#define RCC_PLL1DIVR_P1_Msk                    (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL1DIVR_P1                        RCC_PLL1DIVR_P1_Msk

+#define RCC_PLL1DIVR_Q1_Pos                    (16U)

+#define RCC_PLL1DIVR_Q1_Msk                    (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */

+#define RCC_PLL1DIVR_Q1                        RCC_PLL1DIVR_Q1_Msk

+#define RCC_PLL1DIVR_R1_Pos                    (24U)

+#define RCC_PLL1DIVR_R1_Msk                    (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */

+#define RCC_PLL1DIVR_R1                        RCC_PLL1DIVR_R1_Msk

+

+/********************  Bit definition for RCC_PLL1FRACR register  ***************/

+#define RCC_PLL1FRACR_FRACN1_Pos               (3U)

+#define RCC_PLL1FRACR_FRACN1_Msk               (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL1FRACR_FRACN1                   RCC_PLL1FRACR_FRACN1_Msk

+

+/********************  Bit definition for RCC_PLL2DIVR register  ***************/

+#define RCC_PLL2DIVR_N2_Pos                    (0U)

+#define RCC_PLL2DIVR_N2_Msk                    (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */

+#define RCC_PLL2DIVR_N2                        RCC_PLL2DIVR_N2_Msk

+#define RCC_PLL2DIVR_P2_Pos                    (9U)

+#define RCC_PLL2DIVR_P2_Msk                    (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL2DIVR_P2                        RCC_PLL2DIVR_P2_Msk

+#define RCC_PLL2DIVR_Q2_Pos                    (16U)

+#define RCC_PLL2DIVR_Q2_Msk                    (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */

+#define RCC_PLL2DIVR_Q2                        RCC_PLL2DIVR_Q2_Msk

+#define RCC_PLL2DIVR_R2_Pos                    (24U)

+#define RCC_PLL2DIVR_R2_Msk                    (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */

+#define RCC_PLL2DIVR_R2                        RCC_PLL2DIVR_R2_Msk

+

+/********************  Bit definition for RCC_PLL2FRACR register  ***************/

+#define RCC_PLL2FRACR_FRACN2_Pos               (3U)

+#define RCC_PLL2FRACR_FRACN2_Msk               (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL2FRACR_FRACN2                   RCC_PLL2FRACR_FRACN2_Msk

+

+/********************  Bit definition for RCC_PLL3DIVR register  ***************/

+#define RCC_PLL3DIVR_N3_Pos                    (0U)

+#define RCC_PLL3DIVR_N3_Msk                    (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */

+#define RCC_PLL3DIVR_N3                        RCC_PLL3DIVR_N3_Msk

+#define RCC_PLL3DIVR_P3_Pos                    (9U)

+#define RCC_PLL3DIVR_P3_Msk                    (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL3DIVR_P3                        RCC_PLL3DIVR_P3_Msk

+#define RCC_PLL3DIVR_Q3_Pos                    (16U)

+#define RCC_PLL3DIVR_Q3_Msk                    (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */

+#define RCC_PLL3DIVR_Q3                        RCC_PLL3DIVR_Q3_Msk

+#define RCC_PLL3DIVR_R3_Pos                    (24U)

+#define RCC_PLL3DIVR_R3_Msk                    (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */

+#define RCC_PLL3DIVR_R3                        RCC_PLL3DIVR_R3_Msk

+

+/********************  Bit definition for RCC_PLL3FRACR register  ***************/

+#define RCC_PLL3FRACR_FRACN3_Pos               (3U)

+#define RCC_PLL3FRACR_FRACN3_Msk               (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL3FRACR_FRACN3                   RCC_PLL3FRACR_FRACN3_Msk

+

+/********************  Bit definition for RCC_D1CCIPR register  ***************/

+#define RCC_D1CCIPR_FMCSEL_Pos                 (0U)

+#define RCC_D1CCIPR_FMCSEL_Msk                 (0x3UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000003 */

+#define RCC_D1CCIPR_FMCSEL                     RCC_D1CCIPR_FMCSEL_Msk

+#define RCC_D1CCIPR_FMCSEL_0                   (0x1UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000001 */

+#define RCC_D1CCIPR_FMCSEL_1                   (0x2UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000002 */

+#define RCC_D1CCIPR_QSPISEL_Pos                (4U)

+#define RCC_D1CCIPR_QSPISEL_Msk                (0x3UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000030 */

+#define RCC_D1CCIPR_QSPISEL                    RCC_D1CCIPR_QSPISEL_Msk

+#define RCC_D1CCIPR_QSPISEL_0                  (0x1UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000010 */

+#define RCC_D1CCIPR_QSPISEL_1                  (0x2UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000020 */

+#define RCC_D1CCIPR_SDMMCSEL_Pos               (16U)

+#define RCC_D1CCIPR_SDMMCSEL_Msk               (0x1UL << RCC_D1CCIPR_SDMMCSEL_Pos) /*!< 0x00010000 */

+#define RCC_D1CCIPR_SDMMCSEL                   RCC_D1CCIPR_SDMMCSEL_Msk

+#define RCC_D1CCIPR_CKPERSEL_Pos               (28U)

+#define RCC_D1CCIPR_CKPERSEL_Msk               (0x3UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x30000000 */

+#define RCC_D1CCIPR_CKPERSEL                   RCC_D1CCIPR_CKPERSEL_Msk

+#define RCC_D1CCIPR_CKPERSEL_0                 (0x1UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x10000000 */

+#define RCC_D1CCIPR_CKPERSEL_1                 (0x2UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x20000000 */

+

+/********************  Bit definition for RCC_D2CCIP1R register  ***************/

+#define RCC_D2CCIP1R_SAI1SEL_Pos               (0U)

+#define RCC_D2CCIP1R_SAI1SEL_Msk               (0x7UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000007 */

+#define RCC_D2CCIP1R_SAI1SEL                   RCC_D2CCIP1R_SAI1SEL_Msk

+#define RCC_D2CCIP1R_SAI1SEL_0                 (0x1UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000001 */

+#define RCC_D2CCIP1R_SAI1SEL_1                 (0x2UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000002 */

+#define RCC_D2CCIP1R_SAI1SEL_2                 (0x4UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000004 */

+

+#define RCC_D2CCIP1R_SAI23SEL_Pos              (6U)

+#define RCC_D2CCIP1R_SAI23SEL_Msk              (0x7UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x000001C0 */

+#define RCC_D2CCIP1R_SAI23SEL                  RCC_D2CCIP1R_SAI23SEL_Msk

+#define RCC_D2CCIP1R_SAI23SEL_0                (0x1UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000040 */

+#define RCC_D2CCIP1R_SAI23SEL_1                (0x2UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000080 */

+#define RCC_D2CCIP1R_SAI23SEL_2                (0x4UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000100 */

+

+#define RCC_D2CCIP1R_SPI123SEL_Pos             (12U)

+#define RCC_D2CCIP1R_SPI123SEL_Msk             (0x7UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */

+#define RCC_D2CCIP1R_SPI123SEL                 RCC_D2CCIP1R_SPI123SEL_Msk

+#define RCC_D2CCIP1R_SPI123SEL_0               (0x1UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */

+#define RCC_D2CCIP1R_SPI123SEL_1               (0x2UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */

+#define RCC_D2CCIP1R_SPI123SEL_2               (0x4UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */

+

+#define RCC_D2CCIP1R_SPI45SEL_Pos              (16U)

+#define RCC_D2CCIP1R_SPI45SEL_Msk              (0x7UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00070000 */

+#define RCC_D2CCIP1R_SPI45SEL                  RCC_D2CCIP1R_SPI45SEL_Msk

+#define RCC_D2CCIP1R_SPI45SEL_0                (0x1UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00010000 */

+#define RCC_D2CCIP1R_SPI45SEL_1                (0x2UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00020000 */

+#define RCC_D2CCIP1R_SPI45SEL_2                (0x4UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00040000 */

+

+#define RCC_D2CCIP1R_SPDIFSEL_Pos              (20U)

+#define RCC_D2CCIP1R_SPDIFSEL_Msk              (0x3UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00300000 */

+#define RCC_D2CCIP1R_SPDIFSEL                  RCC_D2CCIP1R_SPDIFSEL_Msk

+#define RCC_D2CCIP1R_SPDIFSEL_0                (0x1UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00100000 */

+#define RCC_D2CCIP1R_SPDIFSEL_1                (0x2UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00200000 */

+

+#define RCC_D2CCIP1R_DFSDM1SEL_Pos             (24U)

+#define RCC_D2CCIP1R_DFSDM1SEL_Msk             (0x1UL << RCC_D2CCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */

+#define RCC_D2CCIP1R_DFSDM1SEL                 RCC_D2CCIP1R_DFSDM1SEL_Msk

+

+#define RCC_D2CCIP1R_FDCANSEL_Pos              (28U)

+#define RCC_D2CCIP1R_FDCANSEL_Msk              (0x3UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x30000000 */

+#define RCC_D2CCIP1R_FDCANSEL                  RCC_D2CCIP1R_FDCANSEL_Msk

+#define RCC_D2CCIP1R_FDCANSEL_0                (0x1UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x10000000 */

+#define RCC_D2CCIP1R_FDCANSEL_1                (0x2UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x20000000 */

+

+#define RCC_D2CCIP1R_SWPSEL_Pos                (31U)

+#define RCC_D2CCIP1R_SWPSEL_Msk                (0x1UL << RCC_D2CCIP1R_SWPSEL_Pos) /*!< 0x80000000 */

+#define RCC_D2CCIP1R_SWPSEL                    RCC_D2CCIP1R_SWPSEL_Msk

+

+/********************  Bit definition for RCC_D2CCIP2R register  ***************/

+#define RCC_D2CCIP2R_USART16SEL_Pos            (3U)

+#define RCC_D2CCIP2R_USART16SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000038 */

+#define RCC_D2CCIP2R_USART16SEL                RCC_D2CCIP2R_USART16SEL_Msk

+#define RCC_D2CCIP2R_USART16SEL_0              (0x1UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000008 */

+#define RCC_D2CCIP2R_USART16SEL_1              (0x2UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000010 */

+#define RCC_D2CCIP2R_USART16SEL_2              (0x4UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000020 */

+

+#define RCC_D2CCIP2R_USART28SEL_Pos            (0U)

+#define RCC_D2CCIP2R_USART28SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000007 */

+#define RCC_D2CCIP2R_USART28SEL                RCC_D2CCIP2R_USART28SEL_Msk

+#define RCC_D2CCIP2R_USART28SEL_0              (0x1UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000001 */

+#define RCC_D2CCIP2R_USART28SEL_1              (0x2UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000002 */

+#define RCC_D2CCIP2R_USART28SEL_2              (0x4UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000004 */

+

+#define RCC_D2CCIP2R_RNGSEL_Pos                (8U)

+#define RCC_D2CCIP2R_RNGSEL_Msk                (0x3UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000300 */

+#define RCC_D2CCIP2R_RNGSEL                    RCC_D2CCIP2R_RNGSEL_Msk

+#define RCC_D2CCIP2R_RNGSEL_0                  (0x1UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000100 */

+#define RCC_D2CCIP2R_RNGSEL_1                  (0x2UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000200 */

+

+#define RCC_D2CCIP2R_I2C123SEL_Pos             (12U)

+#define RCC_D2CCIP2R_I2C123SEL_Msk             (0x3UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00003000 */

+#define RCC_D2CCIP2R_I2C123SEL                 RCC_D2CCIP2R_I2C123SEL_Msk

+#define RCC_D2CCIP2R_I2C123SEL_0               (0x1UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00001000 */

+#define RCC_D2CCIP2R_I2C123SEL_1               (0x2UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00002000 */

+

+#define RCC_D2CCIP2R_USBSEL_Pos                (20U)

+#define RCC_D2CCIP2R_USBSEL_Msk                (0x3UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00300000 */

+#define RCC_D2CCIP2R_USBSEL                    RCC_D2CCIP2R_USBSEL_Msk

+#define RCC_D2CCIP2R_USBSEL_0                  (0x1UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00100000 */

+#define RCC_D2CCIP2R_USBSEL_1                  (0x2UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00200000 */

+

+#define RCC_D2CCIP2R_CECSEL_Pos                (22U)

+#define RCC_D2CCIP2R_CECSEL_Msk                (0x3UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00C00000 */

+#define RCC_D2CCIP2R_CECSEL                    RCC_D2CCIP2R_CECSEL_Msk

+#define RCC_D2CCIP2R_CECSEL_0                  (0x1UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00400000 */

+#define RCC_D2CCIP2R_CECSEL_1                  (0x2UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00800000 */

+

+#define RCC_D2CCIP2R_LPTIM1SEL_Pos             (28U)

+#define RCC_D2CCIP2R_LPTIM1SEL_Msk             (0x7UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x70000000 */

+#define RCC_D2CCIP2R_LPTIM1SEL                 RCC_D2CCIP2R_LPTIM1SEL_Msk

+#define RCC_D2CCIP2R_LPTIM1SEL_0               (0x1UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x10000000 */

+#define RCC_D2CCIP2R_LPTIM1SEL_1               (0x2UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x20000000 */

+#define RCC_D2CCIP2R_LPTIM1SEL_2               (0x4UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition for RCC_D3CCIPR register  ***************/

+#define RCC_D3CCIPR_LPUART1SEL_Pos             (0U)

+#define RCC_D3CCIPR_LPUART1SEL_Msk             (0x7UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000007 */

+#define RCC_D3CCIPR_LPUART1SEL                 RCC_D3CCIPR_LPUART1SEL_Msk

+#define RCC_D3CCIPR_LPUART1SEL_0               (0x1UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000001 */

+#define RCC_D3CCIPR_LPUART1SEL_1               (0x2UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000002 */

+#define RCC_D3CCIPR_LPUART1SEL_2               (0x4UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000004 */

+

+#define RCC_D3CCIPR_I2C4SEL_Pos                (8U)

+#define RCC_D3CCIPR_I2C4SEL_Msk                (0x3UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000300 */

+#define RCC_D3CCIPR_I2C4SEL                    RCC_D3CCIPR_I2C4SEL_Msk

+#define RCC_D3CCIPR_I2C4SEL_0                  (0x1UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000100 */

+#define RCC_D3CCIPR_I2C4SEL_1                  (0x2UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000200 */

+

+#define RCC_D3CCIPR_LPTIM2SEL_Pos              (10U)

+#define RCC_D3CCIPR_LPTIM2SEL_Msk              (0x7UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001C00 */

+#define RCC_D3CCIPR_LPTIM2SEL                  RCC_D3CCIPR_LPTIM2SEL_Msk

+#define RCC_D3CCIPR_LPTIM2SEL_0                (0x1UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000400 */

+#define RCC_D3CCIPR_LPTIM2SEL_1                (0x2UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000800 */

+#define RCC_D3CCIPR_LPTIM2SEL_2                (0x4UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001000 */

+

+#define RCC_D3CCIPR_LPTIM345SEL_Pos            (13U)

+#define RCC_D3CCIPR_LPTIM345SEL_Msk            (0x7UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x0000E000 */

+#define RCC_D3CCIPR_LPTIM345SEL                RCC_D3CCIPR_LPTIM345SEL_Msk

+#define RCC_D3CCIPR_LPTIM345SEL_0              (0x1UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00002000 */

+#define RCC_D3CCIPR_LPTIM345SEL_1              (0x2UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00004000 */

+#define RCC_D3CCIPR_LPTIM345SEL_2              (0x4UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00008000 */

+

+#define RCC_D3CCIPR_SAI4ASEL_Pos               (21U)

+#define RCC_D3CCIPR_SAI4ASEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00E00000 */

+#define RCC_D3CCIPR_SAI4ASEL                   RCC_D3CCIPR_SAI4ASEL_Msk

+#define RCC_D3CCIPR_SAI4ASEL_0                 (0x1UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00200000 */

+#define RCC_D3CCIPR_SAI4ASEL_1                 (0x2UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00400000 */

+#define RCC_D3CCIPR_SAI4ASEL_2                 (0x4UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00800000 */

+

+#define RCC_D3CCIPR_SAI4BSEL_Pos               (24U)

+#define RCC_D3CCIPR_SAI4BSEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x07000000 */

+#define RCC_D3CCIPR_SAI4BSEL                   RCC_D3CCIPR_SAI4BSEL_Msk

+#define RCC_D3CCIPR_SAI4BSEL_0                 (0x1UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x01000000 */

+#define RCC_D3CCIPR_SAI4BSEL_1                 (0x2UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x02000000 */

+#define RCC_D3CCIPR_SAI4BSEL_2                 (0x4UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x04000000 */

+

+#define RCC_D3CCIPR_ADCSEL_Pos                 (16U)

+#define RCC_D3CCIPR_ADCSEL_Msk                 (0x3UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00030000 */

+#define RCC_D3CCIPR_ADCSEL                     RCC_D3CCIPR_ADCSEL_Msk

+#define RCC_D3CCIPR_ADCSEL_0                   (0x1UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00010000 */

+#define RCC_D3CCIPR_ADCSEL_1                   (0x2UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00020000 */

+

+#define RCC_D3CCIPR_SPI6SEL_Pos                (28U)

+#define RCC_D3CCIPR_SPI6SEL_Msk                (0x7UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x70000000 */

+#define RCC_D3CCIPR_SPI6SEL                    RCC_D3CCIPR_SPI6SEL_Msk

+#define RCC_D3CCIPR_SPI6SEL_0                  (0x1UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x10000000 */

+#define RCC_D3CCIPR_SPI6SEL_1                  (0x2UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x20000000 */

+#define RCC_D3CCIPR_SPI6SEL_2                  (0x4UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x40000000 */

+/********************  Bit definition for RCC_CIER register  ******************/

+#define RCC_CIER_LSIRDYIE_Pos                  (0U)

+#define RCC_CIER_LSIRDYIE_Msk                  (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */

+#define RCC_CIER_LSIRDYIE                      RCC_CIER_LSIRDYIE_Msk

+#define RCC_CIER_LSERDYIE_Pos                  (1U)

+#define RCC_CIER_LSERDYIE_Msk                  (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */

+#define RCC_CIER_LSERDYIE                      RCC_CIER_LSERDYIE_Msk

+#define RCC_CIER_HSIRDYIE_Pos                  (2U)

+#define RCC_CIER_HSIRDYIE_Msk                  (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */

+#define RCC_CIER_HSIRDYIE                      RCC_CIER_HSIRDYIE_Msk

+#define RCC_CIER_HSERDYIE_Pos                  (3U)

+#define RCC_CIER_HSERDYIE_Msk                  (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */

+#define RCC_CIER_HSERDYIE                      RCC_CIER_HSERDYIE_Msk

+#define RCC_CIER_CSIRDYIE_Pos                  (4U)

+#define RCC_CIER_CSIRDYIE_Msk                  (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */

+#define RCC_CIER_CSIRDYIE                      RCC_CIER_CSIRDYIE_Msk

+#define RCC_CIER_HSI48RDYIE_Pos                (5U)

+#define RCC_CIER_HSI48RDYIE_Msk                (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */

+#define RCC_CIER_HSI48RDYIE                    RCC_CIER_HSI48RDYIE_Msk

+#define RCC_CIER_PLL1RDYIE_Pos                 (6U)

+#define RCC_CIER_PLL1RDYIE_Msk                 (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */

+#define RCC_CIER_PLL1RDYIE                     RCC_CIER_PLL1RDYIE_Msk

+#define RCC_CIER_PLL2RDYIE_Pos                 (7U)

+#define RCC_CIER_PLL2RDYIE_Msk                 (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */

+#define RCC_CIER_PLL2RDYIE                     RCC_CIER_PLL2RDYIE_Msk

+#define RCC_CIER_PLL3RDYIE_Pos                 (8U)

+#define RCC_CIER_PLL3RDYIE_Msk                 (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */

+#define RCC_CIER_PLL3RDYIE                     RCC_CIER_PLL3RDYIE_Msk

+#define RCC_CIER_LSECSSIE_Pos                  (9U)

+#define RCC_CIER_LSECSSIE_Msk                  (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */

+#define RCC_CIER_LSECSSIE                      RCC_CIER_LSECSSIE_Msk

+

+/********************  Bit definition for RCC_CIFR register  ******************/

+#define RCC_CIFR_LSIRDYF_Pos                   (0U)

+#define RCC_CIFR_LSIRDYF_Msk                   (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */

+#define RCC_CIFR_LSIRDYF                       RCC_CIFR_LSIRDYF_Msk

+#define RCC_CIFR_LSERDYF_Pos                   (1U)

+#define RCC_CIFR_LSERDYF_Msk                   (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */

+#define RCC_CIFR_LSERDYF                       RCC_CIFR_LSERDYF_Msk

+#define RCC_CIFR_HSIRDYF_Pos                   (2U)

+#define RCC_CIFR_HSIRDYF_Msk                   (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */

+#define RCC_CIFR_HSIRDYF                       RCC_CIFR_HSIRDYF_Msk

+#define RCC_CIFR_HSERDYF_Pos                   (3U)

+#define RCC_CIFR_HSERDYF_Msk                   (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */

+#define RCC_CIFR_HSERDYF                       RCC_CIFR_HSERDYF_Msk

+#define RCC_CIFR_CSIRDYF_Pos                   (4U)

+#define RCC_CIFR_CSIRDYF_Msk                   (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */

+#define RCC_CIFR_CSIRDYF                       RCC_CIFR_CSIRDYF_Msk

+#define RCC_CIFR_HSI48RDYF_Pos                 (5U)

+#define RCC_CIFR_HSI48RDYF_Msk                 (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */

+#define RCC_CIFR_HSI48RDYF                     RCC_CIFR_HSI48RDYF_Msk

+#define RCC_CIFR_PLLRDYF_Pos                   (6U)

+#define RCC_CIFR_PLLRDYF_Msk                   (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */

+#define RCC_CIFR_PLLRDYF                       RCC_CIFR_PLLRDYF_Msk

+#define RCC_CIFR_PLL2RDYF_Pos                  (7U)

+#define RCC_CIFR_PLL2RDYF_Msk                  (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */

+#define RCC_CIFR_PLL2RDYF                      RCC_CIFR_PLL2RDYF_Msk

+#define RCC_CIFR_PLL3RDYF_Pos                  (8U)

+#define RCC_CIFR_PLL3RDYF_Msk                  (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */

+#define RCC_CIFR_PLL3RDYF                      RCC_CIFR_PLL3RDYF_Msk

+#define RCC_CIFR_LSECSSF_Pos                   (9U)

+#define RCC_CIFR_LSECSSF_Msk                   (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */

+#define RCC_CIFR_LSECSSF                       RCC_CIFR_LSECSSF_Msk

+#define RCC_CIFR_HSECSSF_Pos                   (10U)

+#define RCC_CIFR_HSECSSF_Msk                   (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */

+#define RCC_CIFR_HSECSSF                       RCC_CIFR_HSECSSF_Msk

+

+/********************  Bit definition for RCC_CICR register  ******************/

+#define RCC_CICR_LSIRDYC_Pos                   (0U)

+#define RCC_CICR_LSIRDYC_Msk                   (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */

+#define RCC_CICR_LSIRDYC                       RCC_CICR_LSIRDYC_Msk

+#define RCC_CICR_LSERDYC_Pos                   (1U)

+#define RCC_CICR_LSERDYC_Msk                   (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */

+#define RCC_CICR_LSERDYC                       RCC_CICR_LSERDYC_Msk

+#define RCC_CICR_HSIRDYC_Pos                   (2U)

+#define RCC_CICR_HSIRDYC_Msk                   (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */

+#define RCC_CICR_HSIRDYC                       RCC_CICR_HSIRDYC_Msk

+#define RCC_CICR_HSERDYC_Pos                   (3U)

+#define RCC_CICR_HSERDYC_Msk                   (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */

+#define RCC_CICR_HSERDYC                       RCC_CICR_HSERDYC_Msk

+#define RCC_CICR_CSIRDYC_Pos                   (4U)

+#define RCC_CICR_CSIRDYC_Msk                   (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */

+#define RCC_CICR_CSIRDYC                       RCC_CICR_CSIRDYC_Msk

+#define RCC_CICR_HSI48RDYC_Pos                 (5U)

+#define RCC_CICR_HSI48RDYC_Msk                 (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */

+#define RCC_CICR_HSI48RDYC                     RCC_CICR_HSI48RDYC_Msk

+#define RCC_CICR_PLLRDYC_Pos                   (6U)

+#define RCC_CICR_PLLRDYC_Msk                   (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */

+#define RCC_CICR_PLLRDYC                       RCC_CICR_PLLRDYC_Msk

+#define RCC_CICR_PLL2RDYC_Pos                  (7U)

+#define RCC_CICR_PLL2RDYC_Msk                  (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */

+#define RCC_CICR_PLL2RDYC                      RCC_CICR_PLL2RDYC_Msk

+#define RCC_CICR_PLL3RDYC_Pos                  (8U)

+#define RCC_CICR_PLL3RDYC_Msk                  (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */

+#define RCC_CICR_PLL3RDYC                      RCC_CICR_PLL3RDYC_Msk

+#define RCC_CICR_LSECSSC_Pos                   (9U)

+#define RCC_CICR_LSECSSC_Msk                   (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */

+#define RCC_CICR_LSECSSC                       RCC_CICR_LSECSSC_Msk

+#define RCC_CICR_HSECSSC_Pos                   (10U)

+#define RCC_CICR_HSECSSC_Msk                   (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */

+#define RCC_CICR_HSECSSC                       RCC_CICR_HSECSSC_Msk

+

+/********************  Bit definition for RCC_BDCR register  ******************/

+#define RCC_BDCR_LSEON_Pos                     (0U)

+#define RCC_BDCR_LSEON_Msk                     (0x1UL << RCC_BDCR_LSEON_Pos)   /*!< 0x00000001 */

+#define RCC_BDCR_LSEON                         RCC_BDCR_LSEON_Msk

+#define RCC_BDCR_LSERDY_Pos                    (1U)

+#define RCC_BDCR_LSERDY_Msk                    (0x1UL << RCC_BDCR_LSERDY_Pos)  /*!< 0x00000002 */

+#define RCC_BDCR_LSERDY                        RCC_BDCR_LSERDY_Msk

+#define RCC_BDCR_LSEBYP_Pos                    (2U)

+#define RCC_BDCR_LSEBYP_Msk                    (0x1UL << RCC_BDCR_LSEBYP_Pos)  /*!< 0x00000004 */

+#define RCC_BDCR_LSEBYP                        RCC_BDCR_LSEBYP_Msk

+

+#define RCC_BDCR_LSEDRV_Pos                    (3U)

+#define RCC_BDCR_LSEDRV_Msk                    (0x3UL << RCC_BDCR_LSEDRV_Pos)  /*!< 0x00000018 */

+#define RCC_BDCR_LSEDRV                        RCC_BDCR_LSEDRV_Msk

+#define RCC_BDCR_LSEDRV_0                      (0x1UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000008 */

+#define RCC_BDCR_LSEDRV_1                      (0x2UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000010 */

+

+#define RCC_BDCR_LSECSSON_Pos                  (5U)

+#define RCC_BDCR_LSECSSON_Msk                  (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */

+#define RCC_BDCR_LSECSSON                      RCC_BDCR_LSECSSON_Msk

+#define RCC_BDCR_LSECSSD_Pos                   (6U)

+#define RCC_BDCR_LSECSSD_Msk                   (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */

+#define RCC_BDCR_LSECSSD                       RCC_BDCR_LSECSSD_Msk

+

+#define RCC_BDCR_RTCSEL_Pos                    (8U)

+#define RCC_BDCR_RTCSEL_Msk                    (0x3UL << RCC_BDCR_RTCSEL_Pos)  /*!< 0x00000300 */

+#define RCC_BDCR_RTCSEL                        RCC_BDCR_RTCSEL_Msk

+#define RCC_BDCR_RTCSEL_0                      (0x1UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000100 */

+#define RCC_BDCR_RTCSEL_1                      (0x2UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000200 */

+

+#define RCC_BDCR_RTCEN_Pos                     (15U)

+#define RCC_BDCR_RTCEN_Msk                     (0x1UL << RCC_BDCR_RTCEN_Pos)   /*!< 0x00008000 */

+#define RCC_BDCR_RTCEN                         RCC_BDCR_RTCEN_Msk

+#define RCC_BDCR_BDRST_Pos                     (16U)

+#define RCC_BDCR_BDRST_Msk                     (0x1UL << RCC_BDCR_BDRST_Pos)   /*!< 0x00010000 */

+#define RCC_BDCR_BDRST                         RCC_BDCR_BDRST_Msk

+/********************  Bit definition for RCC_CSR register  *******************/

+#define RCC_CSR_LSION_Pos                      (0U)

+#define RCC_CSR_LSION_Msk                      (0x1UL << RCC_CSR_LSION_Pos)    /*!< 0x00000001 */

+#define RCC_CSR_LSION                          RCC_CSR_LSION_Msk

+#define RCC_CSR_LSIRDY_Pos                     (1U)

+#define RCC_CSR_LSIRDY_Msk                     (0x1UL << RCC_CSR_LSIRDY_Pos)   /*!< 0x00000002 */

+#define RCC_CSR_LSIRDY                         RCC_CSR_LSIRDY_Msk

+

+

+/********************  Bit definition for RCC_AHB3ENR register  **************/

+#define RCC_AHB3ENR_MDMAEN_Pos                 (0U)

+#define RCC_AHB3ENR_MDMAEN_Msk                 (0x1UL << RCC_AHB3ENR_MDMAEN_Pos)       /*!< 0x00000001 */

+#define RCC_AHB3ENR_MDMAEN                     RCC_AHB3ENR_MDMAEN_Msk

+#define RCC_AHB3ENR_DMA2DEN_Pos                (4U)

+#define RCC_AHB3ENR_DMA2DEN_Msk                (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos)      /*!< 0x00000010 */

+#define RCC_AHB3ENR_DMA2DEN                    RCC_AHB3ENR_DMA2DEN_Msk

+#define RCC_AHB3ENR_JPGDECEN_Pos               (5U)

+#define RCC_AHB3ENR_JPGDECEN_Msk               (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos)     /*!< 0x00000020 */

+#define RCC_AHB3ENR_JPGDECEN                   RCC_AHB3ENR_JPGDECEN_Msk

+#define RCC_AHB3ENR_FMCEN_Pos                  (12U)

+#define RCC_AHB3ENR_FMCEN_Msk                  (0x1UL << RCC_AHB3ENR_FMCEN_Pos)        /*!< 0x00001000 */

+#define RCC_AHB3ENR_FMCEN                      RCC_AHB3ENR_FMCEN_Msk

+#define RCC_AHB3ENR_QSPIEN_Pos                 (14U)

+#define RCC_AHB3ENR_QSPIEN_Msk                 (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)       /*!< 0x00004000 */

+#define RCC_AHB3ENR_QSPIEN                     RCC_AHB3ENR_QSPIEN_Msk

+#define RCC_AHB3ENR_SDMMC1EN_Pos               (16U)

+#define RCC_AHB3ENR_SDMMC1EN_Msk               (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos)     /*!< 0x00010000 */

+#define RCC_AHB3ENR_SDMMC1EN                   RCC_AHB3ENR_SDMMC1EN_Msk

+

+/********************  Bit definition for RCC_AHB1ENR register  ***************/

+#define RCC_AHB1ENR_DMA1EN_Pos                 (0U)

+#define RCC_AHB1ENR_DMA1EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)          /*!< 0x00000001 */

+#define RCC_AHB1ENR_DMA1EN                     RCC_AHB1ENR_DMA1EN_Msk

+#define RCC_AHB1ENR_DMA2EN_Pos                 (1U)

+#define RCC_AHB1ENR_DMA2EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)          /*!< 0x00000002 */

+#define RCC_AHB1ENR_DMA2EN                     RCC_AHB1ENR_DMA2EN_Msk

+#define RCC_AHB1ENR_ADC12EN_Pos                (5U)

+#define RCC_AHB1ENR_ADC12EN_Msk                (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)         /*!< 0x00000020 */

+#define RCC_AHB1ENR_ADC12EN                    RCC_AHB1ENR_ADC12EN_Msk

+#define RCC_AHB1ENR_ETH1MACEN_Pos              (15U)

+#define RCC_AHB1ENR_ETH1MACEN_Msk              (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos)       /*!< 0x00008000 */

+#define RCC_AHB1ENR_ETH1MACEN                  RCC_AHB1ENR_ETH1MACEN_Msk

+#define RCC_AHB1ENR_ETH1TXEN_Pos               (16U)

+#define RCC_AHB1ENR_ETH1TXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos)        /*!< 0x00010000 */

+#define RCC_AHB1ENR_ETH1TXEN                   RCC_AHB1ENR_ETH1TXEN_Msk

+#define RCC_AHB1ENR_ETH1RXEN_Pos               (17U)

+#define RCC_AHB1ENR_ETH1RXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos)        /*!< 0x00020000 */

+#define RCC_AHB1ENR_ETH1RXEN                   RCC_AHB1ENR_ETH1RXEN_Msk

+#define RCC_AHB1ENR_USB1OTGHSEN_Pos            (25U)

+#define RCC_AHB1ENR_USB1OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos)     /*!< 0x02000000 */

+#define RCC_AHB1ENR_USB1OTGHSEN                RCC_AHB1ENR_USB1OTGHSEN_Msk

+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos        (26U)

+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */

+#define RCC_AHB1ENR_USB1OTGHSULPIEN            RCC_AHB1ENR_USB1OTGHSULPIEN_Msk

+#define RCC_AHB1ENR_USB2OTGFSEN_Pos            (27U)

+#define RCC_AHB1ENR_USB2OTGFSEN_Msk            (0x1UL << RCC_AHB1ENR_USB2OTGFSEN_Pos)     /*!< 0x08000000 */

+#define RCC_AHB1ENR_USB2OTGFSEN                RCC_AHB1ENR_USB2OTGFSEN_Msk

+#define RCC_AHB1ENR_USB2OTGFSULPIEN_Pos        (28U)

+#define RCC_AHB1ENR_USB2OTGFSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB2OTGFSULPIEN_Pos) /*!< 0x10000000 */

+#define RCC_AHB1ENR_USB2OTGFSULPIEN            RCC_AHB1ENR_USB2OTGFSULPIEN_Msk

+

+/* Legacy define */

+#define RCC_AHB1ENR_USB2OTGHSEN_Pos            RCC_AHB1ENR_USB2OTGFSEN_Pos

+#define RCC_AHB1ENR_USB2OTGHSEN_Msk            RCC_AHB1ENR_USB2OTGFSEN_Msk

+#define RCC_AHB1ENR_USB2OTGHSEN                RCC_AHB1ENR_USB2OTGFSEN

+#define RCC_AHB1ENR_USB2OTGHSULPIEN_Pos        RCC_AHB1ENR_USB2OTGFSULPIEN_Pos

+#define RCC_AHB1ENR_USB2OTGHSULPIEN_Msk        RCC_AHB1ENR_USB2OTGFSULPIEN_Msk

+#define RCC_AHB1ENR_USB2OTGHSULPIEN            RCC_AHB1ENR_USB2OTGFSULPIEN

+

+

+/********************  Bit definition for RCC_AHB2ENR register  ***************/

+#define RCC_AHB2ENR_DCMIEN_Pos                 (0U)

+#define RCC_AHB2ENR_DCMIEN_Msk                 (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)          /*!< 0x00000001 */

+#define RCC_AHB2ENR_DCMIEN                     RCC_AHB2ENR_DCMIEN_Msk

+#define RCC_AHB2ENR_RNGEN_Pos                  (6U)

+#define RCC_AHB2ENR_RNGEN_Msk                  (0x1UL << RCC_AHB2ENR_RNGEN_Pos)           /*!< 0x00000040 */

+#define RCC_AHB2ENR_RNGEN                      RCC_AHB2ENR_RNGEN_Msk

+#define RCC_AHB2ENR_SDMMC2EN_Pos               (9U)

+#define RCC_AHB2ENR_SDMMC2EN_Msk               (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)        /*!< 0x00000200 */

+#define RCC_AHB2ENR_SDMMC2EN                   RCC_AHB2ENR_SDMMC2EN_Msk

+#define RCC_AHB2ENR_SRAM1EN_Pos                (29U)

+#define RCC_AHB2ENR_SRAM1EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos)       /*!< 0x20000000 */

+#define RCC_AHB2ENR_SRAM1EN                    RCC_AHB2ENR_SRAM1EN_Msk

+#define RCC_AHB2ENR_SRAM2EN_Pos                (30U)

+#define RCC_AHB2ENR_SRAM2EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos)       /*!< 0x40000000 */

+#define RCC_AHB2ENR_SRAM2EN                    RCC_AHB2ENR_SRAM2EN_Msk

+#define RCC_AHB2ENR_SRAM3EN_Pos                (31U)

+#define RCC_AHB2ENR_SRAM3EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM3EN_Pos)       /*!< 0x80000000 */

+#define RCC_AHB2ENR_SRAM3EN                    RCC_AHB2ENR_SRAM3EN_Msk

+

+/* Legacy define */

+#define RCC_AHB2ENR_D2SRAM1EN_Pos              RCC_AHB2ENR_SRAM1EN_Pos

+#define RCC_AHB2ENR_D2SRAM1EN_Msk              RCC_AHB2ENR_SRAM1EN_Msk

+#define RCC_AHB2ENR_D2SRAM1EN                  RCC_AHB2ENR_SRAM1EN

+#define RCC_AHB2ENR_D2SRAM2EN_Pos              RCC_AHB2ENR_SRAM2EN_Pos

+#define RCC_AHB2ENR_D2SRAM2EN_Msk              RCC_AHB2ENR_SRAM2EN_Msk

+#define RCC_AHB2ENR_D2SRAM2EN                  RCC_AHB2ENR_SRAM2EN

+#define RCC_AHB2ENR_D2SRAM3EN_Pos              RCC_AHB2ENR_SRAM3EN_Pos

+#define RCC_AHB2ENR_D2SRAM3EN_Msk              RCC_AHB2ENR_SRAM3EN_Msk

+#define RCC_AHB2ENR_D2SRAM3EN                  RCC_AHB2ENR_SRAM3EN

+

+/********************  Bit definition for RCC_AHB4ENR register  ******************/

+#define RCC_AHB4ENR_GPIOAEN_Pos                (0U)

+#define RCC_AHB4ENR_GPIOAEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)         /*!< 0x00000001 */

+#define RCC_AHB4ENR_GPIOAEN                    RCC_AHB4ENR_GPIOAEN_Msk

+#define RCC_AHB4ENR_GPIOBEN_Pos                (1U)

+#define RCC_AHB4ENR_GPIOBEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)         /*!< 0x00000002 */

+#define RCC_AHB4ENR_GPIOBEN                    RCC_AHB4ENR_GPIOBEN_Msk

+#define RCC_AHB4ENR_GPIOCEN_Pos                (2U)

+#define RCC_AHB4ENR_GPIOCEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)         /*!< 0x00000004 */

+#define RCC_AHB4ENR_GPIOCEN                    RCC_AHB4ENR_GPIOCEN_Msk

+#define RCC_AHB4ENR_GPIODEN_Pos                (3U)

+#define RCC_AHB4ENR_GPIODEN_Msk                (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)         /*!< 0x00000008 */

+#define RCC_AHB4ENR_GPIODEN                    RCC_AHB4ENR_GPIODEN_Msk

+#define RCC_AHB4ENR_GPIOEEN_Pos                (4U)

+#define RCC_AHB4ENR_GPIOEEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)         /*!< 0x00000010 */

+#define RCC_AHB4ENR_GPIOEEN                    RCC_AHB4ENR_GPIOEEN_Msk

+#define RCC_AHB4ENR_GPIOFEN_Pos                (5U)

+#define RCC_AHB4ENR_GPIOFEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)         /*!< 0x00000020 */

+#define RCC_AHB4ENR_GPIOFEN                    RCC_AHB4ENR_GPIOFEN_Msk

+#define RCC_AHB4ENR_GPIOGEN_Pos                (6U)

+#define RCC_AHB4ENR_GPIOGEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)         /*!< 0x00000040 */

+#define RCC_AHB4ENR_GPIOGEN                    RCC_AHB4ENR_GPIOGEN_Msk

+#define RCC_AHB4ENR_GPIOHEN_Pos                (7U)

+#define RCC_AHB4ENR_GPIOHEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)         /*!< 0x00000080 */

+#define RCC_AHB4ENR_GPIOHEN                    RCC_AHB4ENR_GPIOHEN_Msk

+#define RCC_AHB4ENR_GPIOIEN_Pos                (8U)

+#define RCC_AHB4ENR_GPIOIEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos)         /*!< 0x00000100 */

+#define RCC_AHB4ENR_GPIOIEN                    RCC_AHB4ENR_GPIOIEN_Msk

+#define RCC_AHB4ENR_GPIOJEN_Pos                (9U)

+#define RCC_AHB4ENR_GPIOJEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos)         /*!< 0x00000200 */

+#define RCC_AHB4ENR_GPIOJEN                    RCC_AHB4ENR_GPIOJEN_Msk

+#define RCC_AHB4ENR_GPIOKEN_Pos                (10U)

+#define RCC_AHB4ENR_GPIOKEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos)         /*!< 0x00000400 */

+#define RCC_AHB4ENR_GPIOKEN                    RCC_AHB4ENR_GPIOKEN_Msk

+#define RCC_AHB4ENR_CRCEN_Pos                  (19U)

+#define RCC_AHB4ENR_CRCEN_Msk                  (0x1UL << RCC_AHB4ENR_CRCEN_Pos)           /*!< 0x00080000 */

+#define RCC_AHB4ENR_CRCEN                      RCC_AHB4ENR_CRCEN_Msk

+#define RCC_AHB4ENR_BDMAEN_Pos                 (21U)

+#define RCC_AHB4ENR_BDMAEN_Msk                 (0x1UL << RCC_AHB4ENR_BDMAEN_Pos)          /*!< 0x00200000 */

+#define RCC_AHB4ENR_BDMAEN                     RCC_AHB4ENR_BDMAEN_Msk

+#define RCC_AHB4ENR_ADC3EN_Pos                 (24U)

+#define RCC_AHB4ENR_ADC3EN_Msk                 (0x1UL << RCC_AHB4ENR_ADC3EN_Pos)          /*!< 0x01000000 */

+#define RCC_AHB4ENR_ADC3EN                     RCC_AHB4ENR_ADC3EN_Msk

+#define RCC_AHB4ENR_HSEMEN_Pos                 (25U)

+#define RCC_AHB4ENR_HSEMEN_Msk                 (0x1UL << RCC_AHB4ENR_HSEMEN_Pos)          /*!< 0x02000000 */

+#define RCC_AHB4ENR_HSEMEN                     RCC_AHB4ENR_HSEMEN_Msk

+#define RCC_AHB4ENR_BKPRAMEN_Pos               (28U)

+#define RCC_AHB4ENR_BKPRAMEN_Msk               (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)        /*!< 0x10000000 */

+#define RCC_AHB4ENR_BKPRAMEN                   RCC_AHB4ENR_BKPRAMEN_Msk

+

+/********************  Bit definition for RCC_APB3ENR register  ******************/

+#define RCC_APB3ENR_LTDCEN_Pos                 (3U)

+#define RCC_APB3ENR_LTDCEN_Msk                 (0x1UL << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */

+#define RCC_APB3ENR_LTDCEN                     RCC_APB3ENR_LTDCEN_Msk

+#define RCC_APB3ENR_WWDG1EN_Pos                (6U)

+#define RCC_APB3ENR_WWDG1EN_Msk                (0x1UL << RCC_APB3ENR_WWDG1EN_Pos) /*!< 0x00000040 */

+#define RCC_APB3ENR_WWDG1EN                    RCC_APB3ENR_WWDG1EN_Msk

+

+/********************  Bit definition for RCC_APB1LENR register  ******************/

+

+#define RCC_APB1LENR_TIM2EN_Pos                (0U)

+#define RCC_APB1LENR_TIM2EN_Msk                (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */

+#define RCC_APB1LENR_TIM2EN                    RCC_APB1LENR_TIM2EN_Msk

+#define RCC_APB1LENR_TIM3EN_Pos                (1U)

+#define RCC_APB1LENR_TIM3EN_Msk                (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */

+#define RCC_APB1LENR_TIM3EN                    RCC_APB1LENR_TIM3EN_Msk

+#define RCC_APB1LENR_TIM4EN_Pos                (2U)

+#define RCC_APB1LENR_TIM4EN_Msk                (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */

+#define RCC_APB1LENR_TIM4EN                    RCC_APB1LENR_TIM4EN_Msk

+#define RCC_APB1LENR_TIM5EN_Pos                (3U)

+#define RCC_APB1LENR_TIM5EN_Msk                (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */

+#define RCC_APB1LENR_TIM5EN                    RCC_APB1LENR_TIM5EN_Msk

+#define RCC_APB1LENR_TIM6EN_Pos                (4U)

+#define RCC_APB1LENR_TIM6EN_Msk                (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */

+#define RCC_APB1LENR_TIM6EN                    RCC_APB1LENR_TIM6EN_Msk

+#define RCC_APB1LENR_TIM7EN_Pos                (5U)

+#define RCC_APB1LENR_TIM7EN_Msk                (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */

+#define RCC_APB1LENR_TIM7EN                    RCC_APB1LENR_TIM7EN_Msk

+#define RCC_APB1LENR_TIM12EN_Pos               (6U)

+#define RCC_APB1LENR_TIM12EN_Msk               (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */

+#define RCC_APB1LENR_TIM12EN                   RCC_APB1LENR_TIM12EN_Msk

+#define RCC_APB1LENR_TIM13EN_Pos               (7U)

+#define RCC_APB1LENR_TIM13EN_Msk               (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */

+#define RCC_APB1LENR_TIM13EN                   RCC_APB1LENR_TIM13EN_Msk

+#define RCC_APB1LENR_TIM14EN_Pos               (8U)

+#define RCC_APB1LENR_TIM14EN_Msk               (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */

+#define RCC_APB1LENR_TIM14EN                   RCC_APB1LENR_TIM14EN_Msk

+#define RCC_APB1LENR_LPTIM1EN_Pos              (9U)

+#define RCC_APB1LENR_LPTIM1EN_Msk              (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */

+#define RCC_APB1LENR_LPTIM1EN                  RCC_APB1LENR_LPTIM1EN_Msk

+

+

+#define RCC_APB1LENR_SPI2EN_Pos                (14U)

+#define RCC_APB1LENR_SPI2EN_Msk                (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */

+#define RCC_APB1LENR_SPI2EN                    RCC_APB1LENR_SPI2EN_Msk

+#define RCC_APB1LENR_SPI3EN_Pos                (15U)

+#define RCC_APB1LENR_SPI3EN_Msk                (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */

+#define RCC_APB1LENR_SPI3EN                    RCC_APB1LENR_SPI3EN_Msk

+#define RCC_APB1LENR_SPDIFRXEN_Pos             (16U)

+#define RCC_APB1LENR_SPDIFRXEN_Msk             (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */

+#define RCC_APB1LENR_SPDIFRXEN                 RCC_APB1LENR_SPDIFRXEN_Msk

+#define RCC_APB1LENR_USART2EN_Pos              (17U)

+#define RCC_APB1LENR_USART2EN_Msk              (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */

+#define RCC_APB1LENR_USART2EN                  RCC_APB1LENR_USART2EN_Msk

+#define RCC_APB1LENR_USART3EN_Pos              (18U)

+#define RCC_APB1LENR_USART3EN_Msk              (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */

+#define RCC_APB1LENR_USART3EN                  RCC_APB1LENR_USART3EN_Msk

+#define RCC_APB1LENR_UART4EN_Pos               (19U)

+#define RCC_APB1LENR_UART4EN_Msk               (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */

+#define RCC_APB1LENR_UART4EN                   RCC_APB1LENR_UART4EN_Msk

+#define RCC_APB1LENR_UART5EN_Pos               (20U)

+#define RCC_APB1LENR_UART5EN_Msk               (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */

+#define RCC_APB1LENR_UART5EN                   RCC_APB1LENR_UART5EN_Msk

+#define RCC_APB1LENR_I2C1EN_Pos                (21U)

+#define RCC_APB1LENR_I2C1EN_Msk                (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */

+#define RCC_APB1LENR_I2C1EN                    RCC_APB1LENR_I2C1EN_Msk

+#define RCC_APB1LENR_I2C2EN_Pos                (22U)

+#define RCC_APB1LENR_I2C2EN_Msk                (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */

+#define RCC_APB1LENR_I2C2EN                    RCC_APB1LENR_I2C2EN_Msk

+#define RCC_APB1LENR_I2C3EN_Pos                (23U)

+#define RCC_APB1LENR_I2C3EN_Msk                (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */

+#define RCC_APB1LENR_I2C3EN                    RCC_APB1LENR_I2C3EN_Msk

+#define RCC_APB1LENR_CECEN_Pos                 (27U)

+#define RCC_APB1LENR_CECEN_Msk                 (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */

+#define RCC_APB1LENR_CECEN                     RCC_APB1LENR_CECEN_Msk

+#define RCC_APB1LENR_DAC12EN_Pos               (29U)

+#define RCC_APB1LENR_DAC12EN_Msk               (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */

+#define RCC_APB1LENR_DAC12EN                   RCC_APB1LENR_DAC12EN_Msk

+#define RCC_APB1LENR_UART7EN_Pos               (30U)

+#define RCC_APB1LENR_UART7EN_Msk               (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */

+#define RCC_APB1LENR_UART7EN                   RCC_APB1LENR_UART7EN_Msk

+#define RCC_APB1LENR_UART8EN_Pos               (31U)

+#define RCC_APB1LENR_UART8EN_Msk               (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */

+#define RCC_APB1LENR_UART8EN                   RCC_APB1LENR_UART8EN_Msk

+

+/* Legacy define */

+#define RCC_APB1LENR_HDMICECEN_Pos             RCC_APB1LENR_CECEN_Pos

+#define RCC_APB1LENR_HDMICECEN_Msk             RCC_APB1LENR_CECEN_Msk

+#define RCC_APB1LENR_HDMICECEN                 RCC_APB1LENR_CECEN

+/********************  Bit definition for RCC_APB1HENR register  ******************/

+#define RCC_APB1HENR_CRSEN_Pos                 (1U)

+#define RCC_APB1HENR_CRSEN_Msk                 (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1HENR_CRSEN                     RCC_APB1HENR_CRSEN_Msk

+#define RCC_APB1HENR_SWPMIEN_Pos               (2U)

+#define RCC_APB1HENR_SWPMIEN_Msk               (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1HENR_SWPMIEN                   RCC_APB1HENR_SWPMIEN_Msk

+#define RCC_APB1HENR_OPAMPEN_Pos               (4U)

+#define RCC_APB1HENR_OPAMPEN_Msk               (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1HENR_OPAMPEN                   RCC_APB1HENR_OPAMPEN_Msk

+#define RCC_APB1HENR_MDIOSEN_Pos               (5U)

+#define RCC_APB1HENR_MDIOSEN_Msk               (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1HENR_MDIOSEN                   RCC_APB1HENR_MDIOSEN_Msk

+#define RCC_APB1HENR_FDCANEN_Pos               (8U)

+#define RCC_APB1HENR_FDCANEN_Msk               (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1HENR_FDCANEN                   RCC_APB1HENR_FDCANEN_Msk

+

+/********************  Bit definition for RCC_APB2ENR register  ******************/

+#define RCC_APB2ENR_TIM1EN_Pos                 (0U)

+#define RCC_APB2ENR_TIM1EN_Msk                 (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */

+#define RCC_APB2ENR_TIM1EN                     RCC_APB2ENR_TIM1EN_Msk

+#define RCC_APB2ENR_TIM8EN_Pos                 (1U)

+#define RCC_APB2ENR_TIM8EN_Msk                 (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */

+#define RCC_APB2ENR_TIM8EN                     RCC_APB2ENR_TIM8EN_Msk

+#define RCC_APB2ENR_USART1EN_Pos               (4U)

+#define RCC_APB2ENR_USART1EN_Msk               (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */

+#define RCC_APB2ENR_USART1EN                   RCC_APB2ENR_USART1EN_Msk

+#define RCC_APB2ENR_USART6EN_Pos               (5U)

+#define RCC_APB2ENR_USART6EN_Msk               (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */

+#define RCC_APB2ENR_USART6EN                   RCC_APB2ENR_USART6EN_Msk

+#define RCC_APB2ENR_SPI1EN_Pos                 (12U)

+#define RCC_APB2ENR_SPI1EN_Msk                 (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */

+#define RCC_APB2ENR_SPI1EN                     RCC_APB2ENR_SPI1EN_Msk

+#define RCC_APB2ENR_SPI4EN_Pos                 (13U)

+#define RCC_APB2ENR_SPI4EN_Msk                 (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */

+#define RCC_APB2ENR_SPI4EN                     RCC_APB2ENR_SPI4EN_Msk

+#define RCC_APB2ENR_TIM15EN_Pos                (16U)

+#define RCC_APB2ENR_TIM15EN_Msk                (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */

+#define RCC_APB2ENR_TIM15EN                    RCC_APB2ENR_TIM15EN_Msk

+#define RCC_APB2ENR_TIM16EN_Pos                (17U)

+#define RCC_APB2ENR_TIM16EN_Msk                (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */

+#define RCC_APB2ENR_TIM16EN                    RCC_APB2ENR_TIM16EN_Msk

+#define RCC_APB2ENR_TIM17EN_Pos                (18U)

+#define RCC_APB2ENR_TIM17EN_Msk                (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */

+#define RCC_APB2ENR_TIM17EN                    RCC_APB2ENR_TIM17EN_Msk

+#define RCC_APB2ENR_SPI5EN_Pos                 (20U)

+#define RCC_APB2ENR_SPI5EN_Msk                 (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */

+#define RCC_APB2ENR_SPI5EN                     RCC_APB2ENR_SPI5EN_Msk

+#define RCC_APB2ENR_SAI1EN_Pos                 (22U)

+#define RCC_APB2ENR_SAI1EN_Msk                 (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */

+#define RCC_APB2ENR_SAI1EN                     RCC_APB2ENR_SAI1EN_Msk

+#define RCC_APB2ENR_SAI2EN_Pos                 (23U)

+#define RCC_APB2ENR_SAI2EN_Msk                 (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */

+#define RCC_APB2ENR_SAI2EN                     RCC_APB2ENR_SAI2EN_Msk

+#define RCC_APB2ENR_SAI3EN_Pos                 (24U)

+#define RCC_APB2ENR_SAI3EN_Msk                 (0x1UL << RCC_APB2ENR_SAI3EN_Pos) /*!< 0x01000000 */

+#define RCC_APB2ENR_SAI3EN                     RCC_APB2ENR_SAI3EN_Msk

+#define RCC_APB2ENR_DFSDM1EN_Pos               (28U)

+#define RCC_APB2ENR_DFSDM1EN_Msk               (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x10000000 */

+#define RCC_APB2ENR_DFSDM1EN                   RCC_APB2ENR_DFSDM1EN_Msk

+#define RCC_APB2ENR_HRTIMEN_Pos                (29U)

+#define RCC_APB2ENR_HRTIMEN_Msk                (0x1UL << RCC_APB2ENR_HRTIMEN_Pos) /*!< 0x20000000 */

+#define RCC_APB2ENR_HRTIMEN                    RCC_APB2ENR_HRTIMEN_Msk

+

+/********************  Bit definition for RCC_APB4ENR register  ******************/

+#define RCC_APB4ENR_SYSCFGEN_Pos               (1U)

+#define RCC_APB4ENR_SYSCFGEN_Msk               (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */

+#define RCC_APB4ENR_SYSCFGEN                   RCC_APB4ENR_SYSCFGEN_Msk

+#define RCC_APB4ENR_LPUART1EN_Pos              (3U)

+#define RCC_APB4ENR_LPUART1EN_Msk              (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */

+#define RCC_APB4ENR_LPUART1EN                  RCC_APB4ENR_LPUART1EN_Msk

+#define RCC_APB4ENR_SPI6EN_Pos                 (5U)

+#define RCC_APB4ENR_SPI6EN_Msk                 (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */

+#define RCC_APB4ENR_SPI6EN                     RCC_APB4ENR_SPI6EN_Msk

+#define RCC_APB4ENR_I2C4EN_Pos                 (7U)

+#define RCC_APB4ENR_I2C4EN_Msk                 (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */

+#define RCC_APB4ENR_I2C4EN                     RCC_APB4ENR_I2C4EN_Msk

+#define RCC_APB4ENR_LPTIM2EN_Pos               (9U)

+#define RCC_APB4ENR_LPTIM2EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */

+#define RCC_APB4ENR_LPTIM2EN                   RCC_APB4ENR_LPTIM2EN_Msk

+#define RCC_APB4ENR_LPTIM3EN_Pos               (10U)

+#define RCC_APB4ENR_LPTIM3EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */

+#define RCC_APB4ENR_LPTIM3EN                   RCC_APB4ENR_LPTIM3EN_Msk

+#define RCC_APB4ENR_LPTIM4EN_Pos               (11U)

+#define RCC_APB4ENR_LPTIM4EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos) /*!< 0x00000800 */

+#define RCC_APB4ENR_LPTIM4EN                   RCC_APB4ENR_LPTIM4EN_Msk

+#define RCC_APB4ENR_LPTIM5EN_Pos               (12U)

+#define RCC_APB4ENR_LPTIM5EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos) /*!< 0x00001000 */

+#define RCC_APB4ENR_LPTIM5EN                   RCC_APB4ENR_LPTIM5EN_Msk

+#define RCC_APB4ENR_COMP12EN_Pos               (14U)

+#define RCC_APB4ENR_COMP12EN_Msk               (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */

+#define RCC_APB4ENR_COMP12EN                   RCC_APB4ENR_COMP12EN_Msk

+#define RCC_APB4ENR_VREFEN_Pos                 (15U)

+#define RCC_APB4ENR_VREFEN_Msk                 (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */

+#define RCC_APB4ENR_VREFEN                     RCC_APB4ENR_VREFEN_Msk

+#define RCC_APB4ENR_RTCAPBEN_Pos               (16U)

+#define RCC_APB4ENR_RTCAPBEN_Msk               (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */

+#define RCC_APB4ENR_RTCAPBEN                   RCC_APB4ENR_RTCAPBEN_Msk

+#define RCC_APB4ENR_SAI4EN_Pos                 (21U)

+#define RCC_APB4ENR_SAI4EN_Msk                 (0x1UL << RCC_APB4ENR_SAI4EN_Pos) /*!< 0x00200000 */

+#define RCC_APB4ENR_SAI4EN                     RCC_APB4ENR_SAI4EN_Msk

+

+

+/********************  Bit definition for RCC_AHB3RSTR register  ***************/

+#define RCC_AHB3RSTR_MDMARST_Pos               (0U)

+#define RCC_AHB3RSTR_MDMARST_Msk               (0x1UL << RCC_AHB3RSTR_MDMARST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB3RSTR_MDMARST                   RCC_AHB3RSTR_MDMARST_Msk

+#define RCC_AHB3RSTR_DMA2DRST_Pos              (4U)

+#define RCC_AHB3RSTR_DMA2DRST_Msk              (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos)     /*!< 0x00000010 */

+#define RCC_AHB3RSTR_DMA2DRST                  RCC_AHB3RSTR_DMA2DRST_Msk

+#define RCC_AHB3RSTR_JPGDECRST_Pos             (5U)

+#define RCC_AHB3RSTR_JPGDECRST_Msk             (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos)    /*!< 0x00000020 */

+#define RCC_AHB3RSTR_JPGDECRST                 RCC_AHB3RSTR_JPGDECRST_Msk

+#define RCC_AHB3RSTR_FMCRST_Pos                (12U)

+#define RCC_AHB3RSTR_FMCRST_Msk                (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)      /*!< 0x00001000 */

+#define RCC_AHB3RSTR_FMCRST                    RCC_AHB3RSTR_FMCRST_Msk

+#define RCC_AHB3RSTR_QSPIRST_Pos               (14U)

+#define RCC_AHB3RSTR_QSPIRST_Msk               (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)     /*!< 0x00004000 */

+#define RCC_AHB3RSTR_QSPIRST                   RCC_AHB3RSTR_QSPIRST_Msk

+#define RCC_AHB3RSTR_SDMMC1RST_Pos             (16U)

+#define RCC_AHB3RSTR_SDMMC1RST_Msk             (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos)   /*!< 0x00010000 */

+#define RCC_AHB3RSTR_SDMMC1RST                 RCC_AHB3RSTR_SDMMC1RST_Msk

+

+

+/********************  Bit definition for RCC_AHB1RSTR register  ***************/

+#define RCC_AHB1RSTR_DMA1RST_Pos               (0U)

+#define RCC_AHB1RSTR_DMA1RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB1RSTR_DMA1RST                   RCC_AHB1RSTR_DMA1RST_Msk

+#define RCC_AHB1RSTR_DMA2RST_Pos               (1U)

+#define RCC_AHB1RSTR_DMA2RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)      /*!< 0x00000002 */

+#define RCC_AHB1RSTR_DMA2RST                   RCC_AHB1RSTR_DMA2RST_Msk

+#define RCC_AHB1RSTR_ADC12RST_Pos              (5U)

+#define RCC_AHB1RSTR_ADC12RST_Msk              (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)     /*!< 0x00000020 */

+#define RCC_AHB1RSTR_ADC12RST                  RCC_AHB1RSTR_ADC12RST_Msk

+#define RCC_AHB1RSTR_ETH1MACRST_Pos            (15U)

+#define RCC_AHB1RSTR_ETH1MACRST_Msk            (0x1UL << RCC_AHB1RSTR_ETH1MACRST_Pos)   /*!< 0x00008000 */

+#define RCC_AHB1RSTR_ETH1MACRST                RCC_AHB1RSTR_ETH1MACRST_Msk

+#define RCC_AHB1RSTR_USB1OTGHSRST_Pos          (25U)

+#define RCC_AHB1RSTR_USB1OTGHSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */

+#define RCC_AHB1RSTR_USB1OTGHSRST              RCC_AHB1RSTR_USB1OTGHSRST_Msk

+#define RCC_AHB1RSTR_USB2OTGFSRST_Pos          (27U)

+#define RCC_AHB1RSTR_USB2OTGFSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB2OTGFSRST_Pos) /*!< 0x08000000 */

+#define RCC_AHB1RSTR_USB2OTGFSRST              RCC_AHB1RSTR_USB2OTGFSRST_Msk

+

+/* Legacy define */

+#define RCC_AHB1RSTR_USB2OTGHSRST_Pos          RCC_AHB1RSTR_USB2OTGFSRST_Pos

+#define RCC_AHB1RSTR_USB2OTGHSRST_Msk          RCC_AHB1RSTR_USB2OTGFSRST_Msk

+#define RCC_AHB1RSTR_USB2OTGHSRST              RCC_AHB1RSTR_USB2OTGFSRST

+

+/********************  Bit definition for RCC_AHB2RSTR register  ***************/

+#define RCC_AHB2RSTR_DCMIRST_Pos               (0U)

+#define RCC_AHB2RSTR_DCMIRST_Msk               (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)       /*!< 0x00000001 */

+#define RCC_AHB2RSTR_DCMIRST                   RCC_AHB2RSTR_DCMIRST_Msk

+#define RCC_AHB2RSTR_RNGRST_Pos                (6U)

+#define RCC_AHB2RSTR_RNGRST_Msk                (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)        /*!< 0x00000040 */

+#define RCC_AHB2RSTR_RNGRST                    RCC_AHB2RSTR_RNGRST_Msk

+#define RCC_AHB2RSTR_SDMMC2RST_Pos             (9U)

+#define RCC_AHB2RSTR_SDMMC2RST_Msk             (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)     /*!< 0x00000200 */

+#define RCC_AHB2RSTR_SDMMC2RST                 RCC_AHB2RSTR_SDMMC2RST_Msk

+

+/********************  Bit definition for RCC_AHB4RSTR register  ******************/

+#define RCC_AHB4RSTR_GPIOARST_Pos              (0U)

+#define RCC_AHB4RSTR_GPIOARST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB4RSTR_GPIOARST                  RCC_AHB4RSTR_GPIOARST_Msk

+#define RCC_AHB4RSTR_GPIOBRST_Pos              (1U)

+#define RCC_AHB4RSTR_GPIOBRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)      /*!< 0x00000002 */

+#define RCC_AHB4RSTR_GPIOBRST                  RCC_AHB4RSTR_GPIOBRST_Msk

+#define RCC_AHB4RSTR_GPIOCRST_Pos              (2U)

+#define RCC_AHB4RSTR_GPIOCRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)      /*!< 0x00000004 */

+#define RCC_AHB4RSTR_GPIOCRST                  RCC_AHB4RSTR_GPIOCRST_Msk

+#define RCC_AHB4RSTR_GPIODRST_Pos              (3U)

+#define RCC_AHB4RSTR_GPIODRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)      /*!< 0x00000008 */

+#define RCC_AHB4RSTR_GPIODRST                  RCC_AHB4RSTR_GPIODRST_Msk

+#define RCC_AHB4RSTR_GPIOERST_Pos              (4U)

+#define RCC_AHB4RSTR_GPIOERST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)      /*!< 0x00000010 */

+#define RCC_AHB4RSTR_GPIOERST                  RCC_AHB4RSTR_GPIOERST_Msk

+#define RCC_AHB4RSTR_GPIOFRST_Pos              (5U)

+#define RCC_AHB4RSTR_GPIOFRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)       /*!< 0x00000020 */

+#define RCC_AHB4RSTR_GPIOFRST                  RCC_AHB4RSTR_GPIOFRST_Msk

+#define RCC_AHB4RSTR_GPIOGRST_Pos              (6U)

+#define RCC_AHB4RSTR_GPIOGRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)       /*!< 0x00000040 */

+#define RCC_AHB4RSTR_GPIOGRST                  RCC_AHB4RSTR_GPIOGRST_Msk

+#define RCC_AHB4RSTR_GPIOHRST_Pos              (7U)

+#define RCC_AHB4RSTR_GPIOHRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)       /*!< 0x00000080 */

+#define RCC_AHB4RSTR_GPIOHRST                  RCC_AHB4RSTR_GPIOHRST_Msk

+#define RCC_AHB4RSTR_GPIOIRST_Pos              (8U)

+#define RCC_AHB4RSTR_GPIOIRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos)       /*!< 0x00000100 */

+#define RCC_AHB4RSTR_GPIOIRST                  RCC_AHB4RSTR_GPIOIRST_Msk

+#define RCC_AHB4RSTR_GPIOJRST_Pos              (9U)

+#define RCC_AHB4RSTR_GPIOJRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos)       /*!< 0x00000200 */

+#define RCC_AHB4RSTR_GPIOJRST                  RCC_AHB4RSTR_GPIOJRST_Msk

+#define RCC_AHB4RSTR_GPIOKRST_Pos              (10U)

+#define RCC_AHB4RSTR_GPIOKRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos)       /*!< 0x00000400 */

+#define RCC_AHB4RSTR_GPIOKRST                  RCC_AHB4RSTR_GPIOKRST_Msk

+#define RCC_AHB4RSTR_CRCRST_Pos                (19U)

+#define RCC_AHB4RSTR_CRCRST_Msk                (0x1UL << RCC_AHB4RSTR_CRCRST_Pos)         /*!< 0x00080000 */

+#define RCC_AHB4RSTR_CRCRST                    RCC_AHB4RSTR_CRCRST_Msk

+#define RCC_AHB4RSTR_BDMARST_Pos               (21U)

+#define RCC_AHB4RSTR_BDMARST_Msk               (0x1UL << RCC_AHB4RSTR_BDMARST_Pos)        /*!< 0x00200000 */

+#define RCC_AHB4RSTR_BDMARST                   RCC_AHB4RSTR_BDMARST_Msk

+#define RCC_AHB4RSTR_ADC3RST_Pos               (24U)

+#define RCC_AHB4RSTR_ADC3RST_Msk               (0x1UL << RCC_AHB4RSTR_ADC3RST_Pos)        /*!< 0x01000000 */

+#define RCC_AHB4RSTR_ADC3RST                   RCC_AHB4RSTR_ADC3RST_Msk

+#define RCC_AHB4RSTR_HSEMRST_Pos               (25U)

+#define RCC_AHB4RSTR_HSEMRST_Msk               (0x1UL << RCC_AHB4RSTR_HSEMRST_Pos)        /*!< 0x02000000 */

+#define RCC_AHB4RSTR_HSEMRST                   RCC_AHB4RSTR_HSEMRST_Msk

+

+

+/********************  Bit definition for RCC_APB3RSTR register  ******************/

+#define RCC_APB3RSTR_LTDCRST_Pos               (3U)

+#define RCC_APB3RSTR_LTDCRST_Msk               (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */

+#define RCC_APB3RSTR_LTDCRST                   RCC_APB3RSTR_LTDCRST_Msk

+

+/********************  Bit definition for RCC_APB1LRSTR register  ******************/

+

+#define RCC_APB1LRSTR_TIM2RST_Pos              (0U)

+#define RCC_APB1LRSTR_TIM2RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */

+#define RCC_APB1LRSTR_TIM2RST                  RCC_APB1LRSTR_TIM2RST_Msk

+#define RCC_APB1LRSTR_TIM3RST_Pos              (1U)

+#define RCC_APB1LRSTR_TIM3RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */

+#define RCC_APB1LRSTR_TIM3RST                  RCC_APB1LRSTR_TIM3RST_Msk

+#define RCC_APB1LRSTR_TIM4RST_Pos              (2U)

+#define RCC_APB1LRSTR_TIM4RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */

+#define RCC_APB1LRSTR_TIM4RST                  RCC_APB1LRSTR_TIM4RST_Msk

+#define RCC_APB1LRSTR_TIM5RST_Pos              (3U)

+#define RCC_APB1LRSTR_TIM5RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */

+#define RCC_APB1LRSTR_TIM5RST                  RCC_APB1LRSTR_TIM5RST_Msk

+#define RCC_APB1LRSTR_TIM6RST_Pos              (4U)

+#define RCC_APB1LRSTR_TIM6RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */

+#define RCC_APB1LRSTR_TIM6RST                  RCC_APB1LRSTR_TIM6RST_Msk

+#define RCC_APB1LRSTR_TIM7RST_Pos              (5U)

+#define RCC_APB1LRSTR_TIM7RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */

+#define RCC_APB1LRSTR_TIM7RST                  RCC_APB1LRSTR_TIM7RST_Msk

+#define RCC_APB1LRSTR_TIM12RST_Pos             (6U)

+#define RCC_APB1LRSTR_TIM12RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */

+#define RCC_APB1LRSTR_TIM12RST                 RCC_APB1LRSTR_TIM12RST_Msk

+#define RCC_APB1LRSTR_TIM13RST_Pos             (7U)

+#define RCC_APB1LRSTR_TIM13RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */

+#define RCC_APB1LRSTR_TIM13RST                 RCC_APB1LRSTR_TIM13RST_Msk

+#define RCC_APB1LRSTR_TIM14RST_Pos             (8U)

+#define RCC_APB1LRSTR_TIM14RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */

+#define RCC_APB1LRSTR_TIM14RST                 RCC_APB1LRSTR_TIM14RST_Msk

+#define RCC_APB1LRSTR_LPTIM1RST_Pos            (9U)

+#define RCC_APB1LRSTR_LPTIM1RST_Msk            (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */

+#define RCC_APB1LRSTR_LPTIM1RST                RCC_APB1LRSTR_LPTIM1RST_Msk

+#define RCC_APB1LRSTR_SPI2RST_Pos              (14U)

+#define RCC_APB1LRSTR_SPI2RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */

+#define RCC_APB1LRSTR_SPI2RST                  RCC_APB1LRSTR_SPI2RST_Msk

+#define RCC_APB1LRSTR_SPI3RST_Pos              (15U)

+#define RCC_APB1LRSTR_SPI3RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */

+#define RCC_APB1LRSTR_SPI3RST                  RCC_APB1LRSTR_SPI3RST_Msk

+#define RCC_APB1LRSTR_SPDIFRXRST_Pos           (16U)

+#define RCC_APB1LRSTR_SPDIFRXRST_Msk           (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */

+#define RCC_APB1LRSTR_SPDIFRXRST               RCC_APB1LRSTR_SPDIFRXRST_Msk

+#define RCC_APB1LRSTR_USART2RST_Pos            (17U)

+#define RCC_APB1LRSTR_USART2RST_Msk            (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */

+#define RCC_APB1LRSTR_USART2RST                RCC_APB1LRSTR_USART2RST_Msk

+#define RCC_APB1LRSTR_USART3RST_Pos            (18U)

+#define RCC_APB1LRSTR_USART3RST_Msk            (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */

+#define RCC_APB1LRSTR_USART3RST                RCC_APB1LRSTR_USART3RST_Msk

+#define RCC_APB1LRSTR_UART4RST_Pos             (19U)

+#define RCC_APB1LRSTR_UART4RST_Msk             (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */

+#define RCC_APB1LRSTR_UART4RST                 RCC_APB1LRSTR_UART4RST_Msk

+#define RCC_APB1LRSTR_UART5RST_Pos             (20U)

+#define RCC_APB1LRSTR_UART5RST_Msk             (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */

+#define RCC_APB1LRSTR_UART5RST                 RCC_APB1LRSTR_UART5RST_Msk

+#define RCC_APB1LRSTR_I2C1RST_Pos              (21U)

+#define RCC_APB1LRSTR_I2C1RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */

+#define RCC_APB1LRSTR_I2C1RST                  RCC_APB1LRSTR_I2C1RST_Msk

+#define RCC_APB1LRSTR_I2C2RST_Pos              (22U)

+#define RCC_APB1LRSTR_I2C2RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */

+#define RCC_APB1LRSTR_I2C2RST                  RCC_APB1LRSTR_I2C2RST_Msk

+#define RCC_APB1LRSTR_I2C3RST_Pos              (23U)

+#define RCC_APB1LRSTR_I2C3RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */

+#define RCC_APB1LRSTR_I2C3RST                  RCC_APB1LRSTR_I2C3RST_Msk

+#define RCC_APB1LRSTR_CECRST_Pos               (27U)

+#define RCC_APB1LRSTR_CECRST_Msk               (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */

+#define RCC_APB1LRSTR_CECRST                   RCC_APB1LRSTR_CECRST_Msk

+#define RCC_APB1LRSTR_DAC12RST_Pos             (29U)

+#define RCC_APB1LRSTR_DAC12RST_Msk             (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */

+#define RCC_APB1LRSTR_DAC12RST                 RCC_APB1LRSTR_DAC12RST_Msk

+#define RCC_APB1LRSTR_UART7RST_Pos             (30U)

+#define RCC_APB1LRSTR_UART7RST_Msk             (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */

+#define RCC_APB1LRSTR_UART7RST                 RCC_APB1LRSTR_UART7RST_Msk

+#define RCC_APB1LRSTR_UART8RST_Pos             (31U)

+#define RCC_APB1LRSTR_UART8RST_Msk             (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */

+#define RCC_APB1LRSTR_UART8RST                 RCC_APB1LRSTR_UART8RST_Msk

+

+/* Legacy define */

+#define RCC_APB1LRSTR_HDMICECRST_Pos           RCC_APB1LRSTR_CECRST_Pos

+#define RCC_APB1LRSTR_HDMICECRST_Msk           RCC_APB1LRSTR_CECRST_Msk

+#define RCC_APB1LRSTR_HDMICECRST               RCC_APB1LRSTR_CECRST

+/********************  Bit definition for RCC_APB1HRSTR register  ******************/

+#define RCC_APB1HRSTR_CRSRST_Pos               (1U)

+#define RCC_APB1HRSTR_CRSRST_Msk               (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */

+#define RCC_APB1HRSTR_CRSRST                   RCC_APB1HRSTR_CRSRST_Msk

+#define RCC_APB1HRSTR_SWPMIRST_Pos             (2U)

+#define RCC_APB1HRSTR_SWPMIRST_Msk             (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */

+#define RCC_APB1HRSTR_SWPMIRST                 RCC_APB1HRSTR_SWPMIRST_Msk

+#define RCC_APB1HRSTR_OPAMPRST_Pos             (4U)

+#define RCC_APB1HRSTR_OPAMPRST_Msk             (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */

+#define RCC_APB1HRSTR_OPAMPRST                 RCC_APB1HRSTR_OPAMPRST_Msk

+#define RCC_APB1HRSTR_MDIOSRST_Pos             (5U)

+#define RCC_APB1HRSTR_MDIOSRST_Msk             (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */

+#define RCC_APB1HRSTR_MDIOSRST                 RCC_APB1HRSTR_MDIOSRST_Msk

+#define RCC_APB1HRSTR_FDCANRST_Pos             (8U)

+#define RCC_APB1HRSTR_FDCANRST_Msk             (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */

+#define RCC_APB1HRSTR_FDCANRST                 RCC_APB1HRSTR_FDCANRST_Msk

+

+/********************  Bit definition for RCC_APB2RSTR register  ******************/

+#define RCC_APB2RSTR_TIM1RST_Pos               (0U)

+#define RCC_APB2RSTR_TIM1RST_Msk               (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */

+#define RCC_APB2RSTR_TIM1RST                   RCC_APB2RSTR_TIM1RST_Msk

+#define RCC_APB2RSTR_TIM8RST_Pos               (1U)

+#define RCC_APB2RSTR_TIM8RST_Msk               (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */

+#define RCC_APB2RSTR_TIM8RST                   RCC_APB2RSTR_TIM8RST_Msk

+#define RCC_APB2RSTR_USART1RST_Pos             (4U)

+#define RCC_APB2RSTR_USART1RST_Msk             (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */

+#define RCC_APB2RSTR_USART1RST                 RCC_APB2RSTR_USART1RST_Msk

+#define RCC_APB2RSTR_USART6RST_Pos             (5U)

+#define RCC_APB2RSTR_USART6RST_Msk             (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */

+#define RCC_APB2RSTR_USART6RST                 RCC_APB2RSTR_USART6RST_Msk

+#define RCC_APB2RSTR_SPI1RST_Pos               (12U)

+#define RCC_APB2RSTR_SPI1RST_Msk               (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */

+#define RCC_APB2RSTR_SPI1RST                   RCC_APB2RSTR_SPI1RST_Msk

+#define RCC_APB2RSTR_SPI4RST_Pos               (13U)

+#define RCC_APB2RSTR_SPI4RST_Msk               (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */

+#define RCC_APB2RSTR_SPI4RST                   RCC_APB2RSTR_SPI4RST_Msk

+#define RCC_APB2RSTR_TIM15RST_Pos              (16U)

+#define RCC_APB2RSTR_TIM15RST_Msk              (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */

+#define RCC_APB2RSTR_TIM15RST                  RCC_APB2RSTR_TIM15RST_Msk

+#define RCC_APB2RSTR_TIM16RST_Pos              (17U)

+#define RCC_APB2RSTR_TIM16RST_Msk              (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */

+#define RCC_APB2RSTR_TIM16RST                  RCC_APB2RSTR_TIM16RST_Msk

+#define RCC_APB2RSTR_TIM17RST_Pos              (18U)

+#define RCC_APB2RSTR_TIM17RST_Msk              (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */

+#define RCC_APB2RSTR_TIM17RST                  RCC_APB2RSTR_TIM17RST_Msk

+#define RCC_APB2RSTR_SPI5RST_Pos               (20U)

+#define RCC_APB2RSTR_SPI5RST_Msk               (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */

+#define RCC_APB2RSTR_SPI5RST                   RCC_APB2RSTR_SPI5RST_Msk

+#define RCC_APB2RSTR_SAI1RST_Pos               (22U)

+#define RCC_APB2RSTR_SAI1RST_Msk               (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */

+#define RCC_APB2RSTR_SAI1RST                   RCC_APB2RSTR_SAI1RST_Msk

+#define RCC_APB2RSTR_SAI2RST_Pos               (23U)

+#define RCC_APB2RSTR_SAI2RST_Msk               (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */

+#define RCC_APB2RSTR_SAI2RST                   RCC_APB2RSTR_SAI2RST_Msk

+#define RCC_APB2RSTR_SAI3RST_Pos               (24U)

+#define RCC_APB2RSTR_SAI3RST_Msk               (0x1UL << RCC_APB2RSTR_SAI3RST_Pos) /*!< 0x01000000 */

+#define RCC_APB2RSTR_SAI3RST                   RCC_APB2RSTR_SAI3RST_Msk

+#define RCC_APB2RSTR_DFSDM1RST_Pos             (28U)

+#define RCC_APB2RSTR_DFSDM1RST_Msk             (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */

+#define RCC_APB2RSTR_DFSDM1RST                 RCC_APB2RSTR_DFSDM1RST_Msk

+#define RCC_APB2RSTR_HRTIMRST_Pos              (29U)

+#define RCC_APB2RSTR_HRTIMRST_Msk              (0x1UL << RCC_APB2RSTR_HRTIMRST_Pos) /*!< 0x20000000 */

+#define RCC_APB2RSTR_HRTIMRST                  RCC_APB2RSTR_HRTIMRST_Msk

+

+/********************  Bit definition for RCC_APB4RSTR register  ******************/

+#define RCC_APB4RSTR_SYSCFGRST_Pos             (1U)

+#define RCC_APB4RSTR_SYSCFGRST_Msk             (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */

+#define RCC_APB4RSTR_SYSCFGRST                 RCC_APB4RSTR_SYSCFGRST_Msk

+#define RCC_APB4RSTR_LPUART1RST_Pos            (3U)

+#define RCC_APB4RSTR_LPUART1RST_Msk            (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */

+#define RCC_APB4RSTR_LPUART1RST                RCC_APB4RSTR_LPUART1RST_Msk

+#define RCC_APB4RSTR_SPI6RST_Pos               (5U)

+#define RCC_APB4RSTR_SPI6RST_Msk               (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */

+#define RCC_APB4RSTR_SPI6RST                   RCC_APB4RSTR_SPI6RST_Msk

+#define RCC_APB4RSTR_I2C4RST_Pos               (7U)

+#define RCC_APB4RSTR_I2C4RST_Msk               (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */

+#define RCC_APB4RSTR_I2C4RST                   RCC_APB4RSTR_I2C4RST_Msk

+#define RCC_APB4RSTR_LPTIM2RST_Pos             (9U)

+#define RCC_APB4RSTR_LPTIM2RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */

+#define RCC_APB4RSTR_LPTIM2RST                 RCC_APB4RSTR_LPTIM2RST_Msk

+#define RCC_APB4RSTR_LPTIM3RST_Pos             (10U)

+#define RCC_APB4RSTR_LPTIM3RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */

+#define RCC_APB4RSTR_LPTIM3RST                 RCC_APB4RSTR_LPTIM3RST_Msk

+#define RCC_APB4RSTR_LPTIM4RST_Pos             (11U)

+#define RCC_APB4RSTR_LPTIM4RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos) /*!< 0x00000800 */

+#define RCC_APB4RSTR_LPTIM4RST                 RCC_APB4RSTR_LPTIM4RST_Msk

+#define RCC_APB4RSTR_LPTIM5RST_Pos             (12U)

+#define RCC_APB4RSTR_LPTIM5RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos) /*!< 0x00001000 */

+#define RCC_APB4RSTR_LPTIM5RST                 RCC_APB4RSTR_LPTIM5RST_Msk

+#define RCC_APB4RSTR_COMP12RST_Pos             (14U)

+#define RCC_APB4RSTR_COMP12RST_Msk             (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */

+#define RCC_APB4RSTR_COMP12RST                 RCC_APB4RSTR_COMP12RST_Msk

+#define RCC_APB4RSTR_VREFRST_Pos               (15U)

+#define RCC_APB4RSTR_VREFRST_Msk               (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */

+#define RCC_APB4RSTR_VREFRST                   RCC_APB4RSTR_VREFRST_Msk

+#define RCC_APB4RSTR_SAI4RST_Pos               (21U)

+#define RCC_APB4RSTR_SAI4RST_Msk               (0x1UL << RCC_APB4RSTR_SAI4RST_Pos) /*!< 0x00200000 */

+#define RCC_APB4RSTR_SAI4RST                   RCC_APB4RSTR_SAI4RST_Msk

+

+

+/********************  Bit definition for RCC_GCR register  ********************/

+#define RCC_GCR_WW1RSC_Pos                     (0U)

+#define RCC_GCR_WW1RSC_Msk                     (0x1UL << RCC_GCR_WW1RSC_Pos)   /*!< 0x00000001 */

+#define RCC_GCR_WW1RSC                         RCC_GCR_WW1RSC_Msk

+

+/********************  Bit definition for RCC_D3AMR register  ********************/

+#define RCC_D3AMR_BDMAAMEN_Pos                 (0U)

+#define RCC_D3AMR_BDMAAMEN_Msk                 (0x1UL << RCC_D3AMR_BDMAAMEN_Pos) /*!< 0x00000001 */

+#define RCC_D3AMR_BDMAAMEN                     RCC_D3AMR_BDMAAMEN_Msk

+#define RCC_D3AMR_LPUART1AMEN_Pos              (3U)

+#define RCC_D3AMR_LPUART1AMEN_Msk              (0x1UL << RCC_D3AMR_LPUART1AMEN_Pos) /*!< 0x00000008 */

+#define RCC_D3AMR_LPUART1AMEN                  RCC_D3AMR_LPUART1AMEN_Msk

+#define RCC_D3AMR_SPI6AMEN_Pos                 (5U)

+#define RCC_D3AMR_SPI6AMEN_Msk                 (0x1UL << RCC_D3AMR_SPI6AMEN_Pos) /*!< 0x00000020 */

+#define RCC_D3AMR_SPI6AMEN                     RCC_D3AMR_SPI6AMEN_Msk

+#define RCC_D3AMR_I2C4AMEN_Pos                 (7U)

+#define RCC_D3AMR_I2C4AMEN_Msk                 (0x1UL << RCC_D3AMR_I2C4AMEN_Pos) /*!< 0x00000080 */

+#define RCC_D3AMR_I2C4AMEN                     RCC_D3AMR_I2C4AMEN_Msk

+#define RCC_D3AMR_LPTIM2AMEN_Pos               (9U)

+#define RCC_D3AMR_LPTIM2AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */

+#define RCC_D3AMR_LPTIM2AMEN                   RCC_D3AMR_LPTIM2AMEN_Msk

+#define RCC_D3AMR_LPTIM3AMEN_Pos               (10U)

+#define RCC_D3AMR_LPTIM3AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */

+#define RCC_D3AMR_LPTIM3AMEN                   RCC_D3AMR_LPTIM3AMEN_Msk

+#define RCC_D3AMR_LPTIM4AMEN_Pos               (11U)

+#define RCC_D3AMR_LPTIM4AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM4AMEN_Pos) /*!< 0x00000800 */

+#define RCC_D3AMR_LPTIM4AMEN                   RCC_D3AMR_LPTIM4AMEN_Msk

+#define RCC_D3AMR_LPTIM5AMEN_Pos               (12U)

+#define RCC_D3AMR_LPTIM5AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM5AMEN_Pos) /*!< 0x00001000 */

+#define RCC_D3AMR_LPTIM5AMEN                   RCC_D3AMR_LPTIM5AMEN_Msk

+#define RCC_D3AMR_COMP12AMEN_Pos               (14U)

+#define RCC_D3AMR_COMP12AMEN_Msk               (0x1UL << RCC_D3AMR_COMP12AMEN_Pos) /*!< 0x00004000 */

+#define RCC_D3AMR_COMP12AMEN                   RCC_D3AMR_COMP12AMEN_Msk

+#define RCC_D3AMR_VREFAMEN_Pos                 (15U)

+#define RCC_D3AMR_VREFAMEN_Msk                 (0x1UL << RCC_D3AMR_VREFAMEN_Pos) /*!< 0x00008000 */

+#define RCC_D3AMR_VREFAMEN                     RCC_D3AMR_VREFAMEN_Msk

+#define RCC_D3AMR_RTCAMEN_Pos                  (16U)

+#define RCC_D3AMR_RTCAMEN_Msk                  (0x1UL << RCC_D3AMR_RTCAMEN_Pos) /*!< 0x00010000 */

+#define RCC_D3AMR_RTCAMEN                      RCC_D3AMR_RTCAMEN_Msk

+#define RCC_D3AMR_CRCAMEN_Pos                  (19U)

+#define RCC_D3AMR_CRCAMEN_Msk                  (0x1UL << RCC_D3AMR_CRCAMEN_Pos) /*!< 0x00080000 */

+#define RCC_D3AMR_CRCAMEN                      RCC_D3AMR_CRCAMEN_Msk

+#define RCC_D3AMR_SAI4AMEN_Pos                 (21U)

+#define RCC_D3AMR_SAI4AMEN_Msk                 (0x1UL << RCC_D3AMR_SAI4AMEN_Pos) /*!< 0x00200000 */

+#define RCC_D3AMR_SAI4AMEN                     RCC_D3AMR_SAI4AMEN_Msk

+#define RCC_D3AMR_ADC3AMEN_Pos                 (24U)

+#define RCC_D3AMR_ADC3AMEN_Msk                 (0x1UL << RCC_D3AMR_ADC3AMEN_Pos) /*!< 0x01000000 */

+#define RCC_D3AMR_ADC3AMEN                     RCC_D3AMR_ADC3AMEN_Msk

+

+

+#define RCC_D3AMR_BKPRAMAMEN_Pos               (28U)

+#define RCC_D3AMR_BKPRAMAMEN_Msk               (0x1UL << RCC_D3AMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */

+#define RCC_D3AMR_BKPRAMAMEN                   RCC_D3AMR_BKPRAMAMEN_Msk

+#define RCC_D3AMR_SRAM4AMEN_Pos                (29U)

+#define RCC_D3AMR_SRAM4AMEN_Msk                (0x1UL << RCC_D3AMR_SRAM4AMEN_Pos) /*!< 0x20000000 */

+#define RCC_D3AMR_SRAM4AMEN                    RCC_D3AMR_SRAM4AMEN_Msk

+/********************  Bit definition for RCC_AHB3LPENR register  **************/

+#define RCC_AHB3LPENR_MDMALPEN_Pos             (0U)

+#define RCC_AHB3LPENR_MDMALPEN_Msk             (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos)         /*!< 0x00000001 */

+#define RCC_AHB3LPENR_MDMALPEN                 RCC_AHB3LPENR_MDMALPEN_Msk

+#define RCC_AHB3LPENR_DMA2DLPEN_Pos            (4U)

+#define RCC_AHB3LPENR_DMA2DLPEN_Msk            (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos)        /*!< 0x00000010 */

+#define RCC_AHB3LPENR_DMA2DLPEN                RCC_AHB3LPENR_DMA2DLPEN_Msk

+#define RCC_AHB3LPENR_JPGDECLPEN_Pos           (5U)

+#define RCC_AHB3LPENR_JPGDECLPEN_Msk           (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos)       /*!< 0x00000020 */

+#define RCC_AHB3LPENR_JPGDECLPEN               RCC_AHB3LPENR_JPGDECLPEN_Msk

+#define RCC_AHB3LPENR_FLASHLPEN_Pos            (8U)

+#define RCC_AHB3LPENR_FLASHLPEN_Msk            (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos)        /*!< 0x00000100 */

+#define RCC_AHB3LPENR_FLASHLPEN                RCC_AHB3LPENR_FLASHLPEN_Msk

+#define RCC_AHB3LPENR_FMCLPEN_Pos              (12U)

+#define RCC_AHB3LPENR_FMCLPEN_Msk              (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)          /*!< 0x00001000 */

+#define RCC_AHB3LPENR_FMCLPEN                  RCC_AHB3LPENR_FMCLPEN_Msk

+#define RCC_AHB3LPENR_QSPILPEN_Pos             (14U)

+#define RCC_AHB3LPENR_QSPILPEN_Msk             (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos)         /*!< 0x00004000 */

+#define RCC_AHB3LPENR_QSPILPEN                 RCC_AHB3LPENR_QSPILPEN_Msk

+#define RCC_AHB3LPENR_SDMMC1LPEN_Pos           (16U)

+#define RCC_AHB3LPENR_SDMMC1LPEN_Msk           (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos)       /*!< 0x00010000 */

+#define RCC_AHB3LPENR_SDMMC1LPEN               RCC_AHB3LPENR_SDMMC1LPEN_Msk

+#define RCC_AHB3LPENR_DTCM1LPEN_Pos            (28U)

+#define RCC_AHB3LPENR_DTCM1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos)        /*!< 0x10000000 */

+#define RCC_AHB3LPENR_DTCM1LPEN                RCC_AHB3LPENR_DTCM1LPEN_Msk

+#define RCC_AHB3LPENR_DTCM2LPEN_Pos            (29U)

+#define RCC_AHB3LPENR_DTCM2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos)        /*!< 0x20000000 */

+#define RCC_AHB3LPENR_DTCM2LPEN                RCC_AHB3LPENR_DTCM2LPEN_Msk

+#define RCC_AHB3LPENR_ITCMLPEN_Pos             (30U)

+#define RCC_AHB3LPENR_ITCMLPEN_Msk             (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos)         /*!< 0x40000000 */

+#define RCC_AHB3LPENR_ITCMLPEN                 RCC_AHB3LPENR_ITCMLPEN_Msk

+#define RCC_AHB3LPENR_AXISRAMLPEN_Pos          (31U)

+#define RCC_AHB3LPENR_AXISRAMLPEN_Msk          (0x1UL << RCC_AHB3LPENR_AXISRAMLPEN_Pos)      /*!< 0x80000000 */

+#define RCC_AHB3LPENR_AXISRAMLPEN              RCC_AHB3LPENR_AXISRAMLPEN_Msk

+

+

+/********************  Bit definition for RCC_AHB1LPENR register  ***************/

+#define RCC_AHB1LPENR_DMA1LPEN_Pos             (0U)

+#define RCC_AHB1LPENR_DMA1LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB1LPENR_DMA1LPEN                 RCC_AHB1LPENR_DMA1LPEN_Msk

+#define RCC_AHB1LPENR_DMA2LPEN_Pos             (1U)

+#define RCC_AHB1LPENR_DMA2LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */

+#define RCC_AHB1LPENR_DMA2LPEN                 RCC_AHB1LPENR_DMA2LPEN_Msk

+#define RCC_AHB1LPENR_ADC12LPEN_Pos            (5U)

+#define RCC_AHB1LPENR_ADC12LPEN_Msk            (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB1LPENR_ADC12LPEN                RCC_AHB1LPENR_ADC12LPEN_Msk

+#define RCC_AHB1LPENR_ETH1MACLPEN_Pos          (15U)

+#define RCC_AHB1LPENR_ETH1MACLPEN_Msk          (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) /*!< 0x00008000 */

+#define RCC_AHB1LPENR_ETH1MACLPEN              RCC_AHB1LPENR_ETH1MACLPEN_Msk

+#define RCC_AHB1LPENR_ETH1TXLPEN_Pos           (16U)

+#define RCC_AHB1LPENR_ETH1TXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00010000 */

+#define RCC_AHB1LPENR_ETH1TXLPEN               RCC_AHB1LPENR_ETH1TXLPEN_Msk

+#define RCC_AHB1LPENR_ETH1RXLPEN_Pos           (17U)

+#define RCC_AHB1LPENR_ETH1RXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00020000 */

+#define RCC_AHB1LPENR_ETH1RXLPEN               RCC_AHB1LPENR_ETH1RXLPEN_Msk

+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos        (25U)

+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */

+#define RCC_AHB1LPENR_USB1OTGHSLPEN            RCC_AHB1LPENR_USB1OTGHSLPEN_Msk

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos    (26U)

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN        RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGFSLPEN_Pos        (27U)

+#define RCC_AHB1LPENR_USB2OTGFSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB2OTGFSLPEN_Pos) /*!< 0x08000000 */

+#define RCC_AHB1LPENR_USB2OTGFSLPEN            RCC_AHB1LPENR_USB2OTGFSLPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos    (28U)

+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos) /*!< 0x10000000 */

+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN        RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk

+

+/* Legacy define */

+#define RCC_AHB1LPENR_USB2OTGHSLPEN_Pos        RCC_AHB1LPENR_USB2OTGFSLPEN_Pos

+#define RCC_AHB1LPENR_USB2OTGHSLPEN_Msk        RCC_AHB1LPENR_USB2OTGFSLPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGHSLPEN            RCC_AHB1LPENR_USB2OTGFSLPEN

+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Pos    RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos

+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Msk    RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN        RCC_AHB1LPENR_USB2OTGFSULPILPEN

+

+/********************  Bit definition for RCC_AHB2LPENR register  ***************/

+#define RCC_AHB2LPENR_DCMILPEN_Pos             (0U)

+#define RCC_AHB2LPENR_DCMILPEN_Msk             (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB2LPENR_DCMILPEN                 RCC_AHB2LPENR_DCMILPEN_Msk

+#define RCC_AHB2LPENR_RNGLPEN_Pos              (6U)

+#define RCC_AHB2LPENR_RNGLPEN_Msk              (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */

+#define RCC_AHB2LPENR_RNGLPEN                  RCC_AHB2LPENR_RNGLPEN_Msk

+#define RCC_AHB2LPENR_SDMMC2LPEN_Pos           (9U)

+#define RCC_AHB2LPENR_SDMMC2LPEN_Msk           (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */

+#define RCC_AHB2LPENR_SDMMC2LPEN               RCC_AHB2LPENR_SDMMC2LPEN_Msk

+#define RCC_AHB2LPENR_SRAM1LPEN_Pos          (29U)

+#define RCC_AHB2LPENR_SRAM1LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos) /*!< 0x20000000 */

+#define RCC_AHB2LPENR_SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN_Msk

+#define RCC_AHB2LPENR_SRAM2LPEN_Pos          (30U)

+#define RCC_AHB2LPENR_SRAM2LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */

+#define RCC_AHB2LPENR_SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN_Msk

+#define RCC_AHB2LPENR_SRAM3LPEN_Pos          (31U)

+#define RCC_AHB2LPENR_SRAM3LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM3LPEN_Pos) /*!< 0x80000000 */

+#define RCC_AHB2LPENR_SRAM3LPEN              RCC_AHB2LPENR_SRAM3LPEN_Msk

+

+/* Legacy define */

+#define RCC_AHB2LPENR_D2SRAM1LPEN_Pos          RCC_AHB2LPENR_SRAM1LPEN_Pos

+#define RCC_AHB2LPENR_D2SRAM1LPEN_Msk          RCC_AHB2LPENR_SRAM1LPEN_Msk

+#define RCC_AHB2LPENR_D2SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN

+#define RCC_AHB2LPENR_D2SRAM2LPEN_Pos          RCC_AHB2LPENR_SRAM2LPEN_Pos

+#define RCC_AHB2LPENR_D2SRAM2LPEN_Msk          RCC_AHB2LPENR_SRAM2LPEN_Msk

+#define RCC_AHB2LPENR_D2SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN

+#define RCC_AHB2LPENR_D2SRAM3LPEN_Pos          RCC_AHB2LPENR_SRAM3LPEN_Pos

+#define RCC_AHB2LPENR_D2SRAM3LPEN_Msk          RCC_AHB2LPENR_SRAM3LPEN_Msk

+#define RCC_AHB2LPENR_D2SRAM3LPEN              RCC_AHB2LPENR_SRAM3LPEN

+

+/********************  Bit definition for RCC_AHB4LPENR register  ******************/

+#define RCC_AHB4LPENR_GPIOALPEN_Pos            (0U)

+#define RCC_AHB4LPENR_GPIOALPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB4LPENR_GPIOALPEN                RCC_AHB4LPENR_GPIOALPEN_Msk

+#define RCC_AHB4LPENR_GPIOBLPEN_Pos            (1U)

+#define RCC_AHB4LPENR_GPIOBLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */

+#define RCC_AHB4LPENR_GPIOBLPEN                RCC_AHB4LPENR_GPIOBLPEN_Msk

+#define RCC_AHB4LPENR_GPIOCLPEN_Pos            (2U)

+#define RCC_AHB4LPENR_GPIOCLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */

+#define RCC_AHB4LPENR_GPIOCLPEN                RCC_AHB4LPENR_GPIOCLPEN_Msk

+#define RCC_AHB4LPENR_GPIODLPEN_Pos            (3U)

+#define RCC_AHB4LPENR_GPIODLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */

+#define RCC_AHB4LPENR_GPIODLPEN                RCC_AHB4LPENR_GPIODLPEN_Msk

+#define RCC_AHB4LPENR_GPIOELPEN_Pos            (4U)

+#define RCC_AHB4LPENR_GPIOELPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */

+#define RCC_AHB4LPENR_GPIOELPEN                RCC_AHB4LPENR_GPIOELPEN_Msk

+#define RCC_AHB4LPENR_GPIOFLPEN_Pos            (5U)

+#define RCC_AHB4LPENR_GPIOFLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB4LPENR_GPIOFLPEN                RCC_AHB4LPENR_GPIOFLPEN_Msk

+#define RCC_AHB4LPENR_GPIOGLPEN_Pos            (6U)

+#define RCC_AHB4LPENR_GPIOGLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */

+#define RCC_AHB4LPENR_GPIOGLPEN                RCC_AHB4LPENR_GPIOGLPEN_Msk

+#define RCC_AHB4LPENR_GPIOHLPEN_Pos            (7U)

+#define RCC_AHB4LPENR_GPIOHLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */

+#define RCC_AHB4LPENR_GPIOHLPEN                RCC_AHB4LPENR_GPIOHLPEN_Msk

+#define RCC_AHB4LPENR_GPIOILPEN_Pos            (8U)

+#define RCC_AHB4LPENR_GPIOILPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */

+#define RCC_AHB4LPENR_GPIOILPEN                RCC_AHB4LPENR_GPIOILPEN_Msk

+#define RCC_AHB4LPENR_GPIOJLPEN_Pos            (9U)

+#define RCC_AHB4LPENR_GPIOJLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */

+#define RCC_AHB4LPENR_GPIOJLPEN                RCC_AHB4LPENR_GPIOJLPEN_Msk

+#define RCC_AHB4LPENR_GPIOKLPEN_Pos            (10U)

+#define RCC_AHB4LPENR_GPIOKLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */

+#define RCC_AHB4LPENR_GPIOKLPEN                RCC_AHB4LPENR_GPIOKLPEN_Msk

+#define RCC_AHB4LPENR_CRCLPEN_Pos              (19U)

+#define RCC_AHB4LPENR_CRCLPEN_Msk              (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */

+#define RCC_AHB4LPENR_CRCLPEN                  RCC_AHB4LPENR_CRCLPEN_Msk

+#define RCC_AHB4LPENR_BDMALPEN_Pos             (21U)

+#define RCC_AHB4LPENR_BDMALPEN_Msk             (0x1UL << RCC_AHB4LPENR_BDMALPEN_Pos) /*!< 0x00200000 */

+#define RCC_AHB4LPENR_BDMALPEN                 RCC_AHB4LPENR_BDMALPEN_Msk

+#define RCC_AHB4LPENR_ADC3LPEN_Pos             (24U)

+#define RCC_AHB4LPENR_ADC3LPEN_Msk             (0x1UL << RCC_AHB4LPENR_ADC3LPEN_Pos) /*!< 0x01000000 */

+#define RCC_AHB4LPENR_ADC3LPEN                 RCC_AHB4LPENR_ADC3LPEN_Msk

+#define RCC_AHB4LPENR_BKPRAMLPEN_Pos           (28U)

+#define RCC_AHB4LPENR_BKPRAMLPEN_Msk           (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */

+#define RCC_AHB4LPENR_BKPRAMLPEN               RCC_AHB4LPENR_BKPRAMLPEN_Msk

+#define RCC_AHB4LPENR_SRAM4LPEN_Pos            (29U)

+#define RCC_AHB4LPENR_SRAM4LPEN_Msk            (0x1UL << RCC_AHB4LPENR_SRAM4LPEN_Pos) /*!< 0x20000000 */

+#define RCC_AHB4LPENR_SRAM4LPEN                RCC_AHB4LPENR_SRAM4LPEN_Msk

+

+/* Legacy define */

+#define RCC_AHB4LPENR_D3SRAM1LPEN_Pos          RCC_AHB4LPENR_SRAM4LPEN_Pos

+#define RCC_AHB4LPENR_D3SRAM1LPEN_Msk          RCC_AHB4LPENR_SRAM4LPEN_Msk

+#define RCC_AHB4LPENR_D3SRAM1LPEN              RCC_AHB4LPENR_SRAM4LPEN

+/********************  Bit definition for RCC_APB3LPENR register  ******************/

+#define RCC_APB3LPENR_LTDCLPEN_Pos             (3U)

+#define RCC_APB3LPENR_LTDCLPEN_Msk             (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB3LPENR_LTDCLPEN                 RCC_APB3LPENR_LTDCLPEN_Msk

+#define RCC_APB3LPENR_WWDG1LPEN_Pos            (6U)

+#define RCC_APB3LPENR_WWDG1LPEN_Msk            (0x1UL << RCC_APB3LPENR_WWDG1LPEN_Pos) /*!< 0x00000040 */

+#define RCC_APB3LPENR_WWDG1LPEN                RCC_APB3LPENR_WWDG1LPEN_Msk

+

+/********************  Bit definition for RCC_APB1LLPENR register  ******************/

+

+#define RCC_APB1LLPENR_TIM2LPEN_Pos            (0U)

+#define RCC_APB1LLPENR_TIM2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */

+#define RCC_APB1LLPENR_TIM2LPEN                RCC_APB1LLPENR_TIM2LPEN_Msk

+#define RCC_APB1LLPENR_TIM3LPEN_Pos            (1U)

+#define RCC_APB1LLPENR_TIM3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1LLPENR_TIM3LPEN                RCC_APB1LLPENR_TIM3LPEN_Msk

+#define RCC_APB1LLPENR_TIM4LPEN_Pos            (2U)

+#define RCC_APB1LLPENR_TIM4LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1LLPENR_TIM4LPEN                RCC_APB1LLPENR_TIM4LPEN_Msk

+#define RCC_APB1LLPENR_TIM5LPEN_Pos            (3U)

+#define RCC_APB1LLPENR_TIM5LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB1LLPENR_TIM5LPEN                RCC_APB1LLPENR_TIM5LPEN_Msk

+#define RCC_APB1LLPENR_TIM6LPEN_Pos            (4U)

+#define RCC_APB1LLPENR_TIM6LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1LLPENR_TIM6LPEN                RCC_APB1LLPENR_TIM6LPEN_Msk

+#define RCC_APB1LLPENR_TIM7LPEN_Pos            (5U)

+#define RCC_APB1LLPENR_TIM7LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1LLPENR_TIM7LPEN                RCC_APB1LLPENR_TIM7LPEN_Msk

+#define RCC_APB1LLPENR_TIM12LPEN_Pos           (6U)

+#define RCC_APB1LLPENR_TIM12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */

+#define RCC_APB1LLPENR_TIM12LPEN               RCC_APB1LLPENR_TIM12LPEN_Msk

+#define RCC_APB1LLPENR_TIM13LPEN_Pos           (7U)

+#define RCC_APB1LLPENR_TIM13LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB1LLPENR_TIM13LPEN               RCC_APB1LLPENR_TIM13LPEN_Msk

+#define RCC_APB1LLPENR_TIM14LPEN_Pos           (8U)

+#define RCC_APB1LLPENR_TIM14LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1LLPENR_TIM14LPEN               RCC_APB1LLPENR_TIM14LPEN_Msk

+#define RCC_APB1LLPENR_LPTIM1LPEN_Pos          (9U)

+#define RCC_APB1LLPENR_LPTIM1LPEN_Msk          (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */

+#define RCC_APB1LLPENR_LPTIM1LPEN              RCC_APB1LLPENR_LPTIM1LPEN_Msk

+

+

+#define RCC_APB1LLPENR_SPI2LPEN_Pos            (14U)

+#define RCC_APB1LLPENR_SPI2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */

+#define RCC_APB1LLPENR_SPI2LPEN                RCC_APB1LLPENR_SPI2LPEN_Msk

+#define RCC_APB1LLPENR_SPI3LPEN_Pos            (15U)

+#define RCC_APB1LLPENR_SPI3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */

+#define RCC_APB1LLPENR_SPI3LPEN                RCC_APB1LLPENR_SPI3LPEN_Msk

+#define RCC_APB1LLPENR_SPDIFRXLPEN_Pos         (16U)

+#define RCC_APB1LLPENR_SPDIFRXLPEN_Msk         (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB1LLPENR_SPDIFRXLPEN             RCC_APB1LLPENR_SPDIFRXLPEN_Msk

+#define RCC_APB1LLPENR_USART2LPEN_Pos          (17U)

+#define RCC_APB1LLPENR_USART2LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */

+#define RCC_APB1LLPENR_USART2LPEN              RCC_APB1LLPENR_USART2LPEN_Msk

+#define RCC_APB1LLPENR_USART3LPEN_Pos          (18U)

+#define RCC_APB1LLPENR_USART3LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */

+#define RCC_APB1LLPENR_USART3LPEN              RCC_APB1LLPENR_USART3LPEN_Msk

+#define RCC_APB1LLPENR_UART4LPEN_Pos           (19U)

+#define RCC_APB1LLPENR_UART4LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */

+#define RCC_APB1LLPENR_UART4LPEN               RCC_APB1LLPENR_UART4LPEN_Msk

+#define RCC_APB1LLPENR_UART5LPEN_Pos           (20U)

+#define RCC_APB1LLPENR_UART5LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */

+#define RCC_APB1LLPENR_UART5LPEN               RCC_APB1LLPENR_UART5LPEN_Msk

+#define RCC_APB1LLPENR_I2C1LPEN_Pos            (21U)

+#define RCC_APB1LLPENR_I2C1LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */

+#define RCC_APB1LLPENR_I2C1LPEN                RCC_APB1LLPENR_I2C1LPEN_Msk

+#define RCC_APB1LLPENR_I2C2LPEN_Pos            (22U)

+#define RCC_APB1LLPENR_I2C2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */

+#define RCC_APB1LLPENR_I2C2LPEN                RCC_APB1LLPENR_I2C2LPEN_Msk

+#define RCC_APB1LLPENR_I2C3LPEN_Pos            (23U)

+#define RCC_APB1LLPENR_I2C3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */

+#define RCC_APB1LLPENR_I2C3LPEN                RCC_APB1LLPENR_I2C3LPEN_Msk

+#define RCC_APB1LLPENR_CECLPEN_Pos             (27U)

+#define RCC_APB1LLPENR_CECLPEN_Msk             (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */

+#define RCC_APB1LLPENR_CECLPEN                 RCC_APB1LLPENR_CECLPEN_Msk

+#define RCC_APB1LLPENR_DAC12LPEN_Pos           (29U)

+#define RCC_APB1LLPENR_DAC12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */

+#define RCC_APB1LLPENR_DAC12LPEN               RCC_APB1LLPENR_DAC12LPEN_Msk

+#define RCC_APB1LLPENR_UART7LPEN_Pos           (30U)

+#define RCC_APB1LLPENR_UART7LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */

+#define RCC_APB1LLPENR_UART7LPEN               RCC_APB1LLPENR_UART7LPEN_Msk

+#define RCC_APB1LLPENR_UART8LPEN_Pos           (31U)

+#define RCC_APB1LLPENR_UART8LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */

+#define RCC_APB1LLPENR_UART8LPEN               RCC_APB1LLPENR_UART8LPEN_Msk

+

+/* Legacy define */

+#define RCC_APB1LLPENR_HDMICECEN_Pos           RCC_APB1LLPENR_CECLPEN_Pos

+#define RCC_APB1LLPENR_HDMICECEN_Msk           RCC_APB1LLPENR_CECLPEN_Msk

+#define RCC_APB1LLPENR_HDMICECEN               RCC_APB1LLPENR_CECLPEN

+/********************  Bit definition for RCC_APB1HLPENR register  ******************/

+#define RCC_APB1HLPENR_CRSLPEN_Pos             (1U)

+#define RCC_APB1HLPENR_CRSLPEN_Msk             (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1HLPENR_CRSLPEN                 RCC_APB1HLPENR_CRSLPEN_Msk

+#define RCC_APB1HLPENR_SWPMILPEN_Pos           (2U)

+#define RCC_APB1HLPENR_SWPMILPEN_Msk           (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1HLPENR_SWPMILPEN               RCC_APB1HLPENR_SWPMILPEN_Msk

+#define RCC_APB1HLPENR_OPAMPLPEN_Pos           (4U)

+#define RCC_APB1HLPENR_OPAMPLPEN_Msk           (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1HLPENR_OPAMPLPEN               RCC_APB1HLPENR_OPAMPLPEN_Msk

+#define RCC_APB1HLPENR_MDIOSLPEN_Pos           (5U)

+#define RCC_APB1HLPENR_MDIOSLPEN_Msk           (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1HLPENR_MDIOSLPEN               RCC_APB1HLPENR_MDIOSLPEN_Msk

+#define RCC_APB1HLPENR_FDCANLPEN_Pos           (8U)

+#define RCC_APB1HLPENR_FDCANLPEN_Msk           (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1HLPENR_FDCANLPEN               RCC_APB1HLPENR_FDCANLPEN_Msk

+

+/********************  Bit definition for RCC_APB2LPENR register  ******************/

+#define RCC_APB2LPENR_TIM1LPEN_Pos             (0U)

+#define RCC_APB2LPENR_TIM1LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */

+#define RCC_APB2LPENR_TIM1LPEN                 RCC_APB2LPENR_TIM1LPEN_Msk

+#define RCC_APB2LPENR_TIM8LPEN_Pos             (1U)

+#define RCC_APB2LPENR_TIM8LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB2LPENR_TIM8LPEN                 RCC_APB2LPENR_TIM8LPEN_Msk

+#define RCC_APB2LPENR_USART1LPEN_Pos           (4U)

+#define RCC_APB2LPENR_USART1LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB2LPENR_USART1LPEN               RCC_APB2LPENR_USART1LPEN_Msk

+#define RCC_APB2LPENR_USART6LPEN_Pos           (5U)

+#define RCC_APB2LPENR_USART6LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB2LPENR_USART6LPEN               RCC_APB2LPENR_USART6LPEN_Msk

+#define RCC_APB2LPENR_SPI1LPEN_Pos             (12U)

+#define RCC_APB2LPENR_SPI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */

+#define RCC_APB2LPENR_SPI1LPEN                 RCC_APB2LPENR_SPI1LPEN_Msk

+#define RCC_APB2LPENR_SPI4LPEN_Pos             (13U)

+#define RCC_APB2LPENR_SPI4LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */

+#define RCC_APB2LPENR_SPI4LPEN                 RCC_APB2LPENR_SPI4LPEN_Msk

+#define RCC_APB2LPENR_TIM15LPEN_Pos            (16U)

+#define RCC_APB2LPENR_TIM15LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB2LPENR_TIM15LPEN                RCC_APB2LPENR_TIM15LPEN_Msk

+#define RCC_APB2LPENR_TIM16LPEN_Pos            (17U)

+#define RCC_APB2LPENR_TIM16LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */

+#define RCC_APB2LPENR_TIM16LPEN                RCC_APB2LPENR_TIM16LPEN_Msk

+#define RCC_APB2LPENR_TIM17LPEN_Pos            (18U)

+#define RCC_APB2LPENR_TIM17LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */

+#define RCC_APB2LPENR_TIM17LPEN                RCC_APB2LPENR_TIM17LPEN_Msk

+#define RCC_APB2LPENR_SPI5LPEN_Pos             (20U)

+#define RCC_APB2LPENR_SPI5LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */

+#define RCC_APB2LPENR_SPI5LPEN                 RCC_APB2LPENR_SPI5LPEN_Msk

+#define RCC_APB2LPENR_SAI1LPEN_Pos             (22U)

+#define RCC_APB2LPENR_SAI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */

+#define RCC_APB2LPENR_SAI1LPEN                 RCC_APB2LPENR_SAI1LPEN_Msk

+#define RCC_APB2LPENR_SAI2LPEN_Pos             (23U)

+#define RCC_APB2LPENR_SAI2LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */

+#define RCC_APB2LPENR_SAI2LPEN                 RCC_APB2LPENR_SAI2LPEN_Msk

+#define RCC_APB2LPENR_SAI3LPEN_Pos             (24U)

+#define RCC_APB2LPENR_SAI3LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI3LPEN_Pos) /*!< 0x01000000 */

+#define RCC_APB2LPENR_SAI3LPEN                 RCC_APB2LPENR_SAI3LPEN_Msk

+#define RCC_APB2LPENR_DFSDM1LPEN_Pos           (28U)

+#define RCC_APB2LPENR_DFSDM1LPEN_Msk           (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x10000000 */

+#define RCC_APB2LPENR_DFSDM1LPEN               RCC_APB2LPENR_DFSDM1LPEN_Msk

+#define RCC_APB2LPENR_HRTIMLPEN_Pos            (29U)

+#define RCC_APB2LPENR_HRTIMLPEN_Msk            (0x1UL << RCC_APB2LPENR_HRTIMLPEN_Pos) /*!< 0x20000000 */

+#define RCC_APB2LPENR_HRTIMLPEN                RCC_APB2LPENR_HRTIMLPEN_Msk

+

+/********************  Bit definition for RCC_APB4LPENR register  ******************/

+#define RCC_APB4LPENR_SYSCFGLPEN_Pos           (1U)

+#define RCC_APB4LPENR_SYSCFGLPEN_Msk           (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB4LPENR_SYSCFGLPEN               RCC_APB4LPENR_SYSCFGLPEN_Msk

+#define RCC_APB4LPENR_LPUART1LPEN_Pos          (3U)

+#define RCC_APB4LPENR_LPUART1LPEN_Msk          (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB4LPENR_LPUART1LPEN              RCC_APB4LPENR_LPUART1LPEN_Msk

+#define RCC_APB4LPENR_SPI6LPEN_Pos             (5U)

+#define RCC_APB4LPENR_SPI6LPEN_Msk             (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB4LPENR_SPI6LPEN                 RCC_APB4LPENR_SPI6LPEN_Msk

+#define RCC_APB4LPENR_I2C4LPEN_Pos             (7U)

+#define RCC_APB4LPENR_I2C4LPEN_Msk             (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB4LPENR_I2C4LPEN                 RCC_APB4LPENR_I2C4LPEN_Msk

+#define RCC_APB4LPENR_LPTIM2LPEN_Pos           (9U)

+#define RCC_APB4LPENR_LPTIM2LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */

+#define RCC_APB4LPENR_LPTIM2LPEN               RCC_APB4LPENR_LPTIM2LPEN_Msk

+#define RCC_APB4LPENR_LPTIM3LPEN_Pos           (10U)

+#define RCC_APB4LPENR_LPTIM3LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */

+#define RCC_APB4LPENR_LPTIM3LPEN               RCC_APB4LPENR_LPTIM3LPEN_Msk

+#define RCC_APB4LPENR_LPTIM4LPEN_Pos           (11U)

+#define RCC_APB4LPENR_LPTIM4LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) /*!< 0x00000800 */

+#define RCC_APB4LPENR_LPTIM4LPEN               RCC_APB4LPENR_LPTIM4LPEN_Msk

+#define RCC_APB4LPENR_LPTIM5LPEN_Pos           (12U)

+#define RCC_APB4LPENR_LPTIM5LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) /*!< 0x00001000 */

+#define RCC_APB4LPENR_LPTIM5LPEN               RCC_APB4LPENR_LPTIM5LPEN_Msk

+#define RCC_APB4LPENR_COMP12LPEN_Pos           (14U)

+#define RCC_APB4LPENR_COMP12LPEN_Msk           (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */

+#define RCC_APB4LPENR_COMP12LPEN               RCC_APB4LPENR_COMP12LPEN_Msk

+#define RCC_APB4LPENR_VREFLPEN_Pos             (15U)

+#define RCC_APB4LPENR_VREFLPEN_Msk             (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */

+#define RCC_APB4LPENR_VREFLPEN                 RCC_APB4LPENR_VREFLPEN_Msk

+#define RCC_APB4LPENR_RTCAPBLPEN_Pos           (16U)

+#define RCC_APB4LPENR_RTCAPBLPEN_Msk           (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB4LPENR_RTCAPBLPEN               RCC_APB4LPENR_RTCAPBLPEN_Msk

+#define RCC_APB4LPENR_SAI4LPEN_Pos             (21U)

+#define RCC_APB4LPENR_SAI4LPEN_Msk             (0x1UL << RCC_APB4LPENR_SAI4LPEN_Pos) /*!< 0x00200000 */

+#define RCC_APB4LPENR_SAI4LPEN                 RCC_APB4LPENR_SAI4LPEN_Msk

+

+

+/********************  Bit definition for RCC_RSR register  *******************/

+#define RCC_RSR_RMVF_Pos                       (16U)

+#define RCC_RSR_RMVF_Msk                       (0x1UL << RCC_RSR_RMVF_Pos)     /*!< 0x00010000 */

+#define RCC_RSR_RMVF                           RCC_RSR_RMVF_Msk

+#define RCC_RSR_CPURSTF_Pos                    (17U)

+#define RCC_RSR_CPURSTF_Msk                    (0x1UL << RCC_RSR_CPURSTF_Pos)  /*!< 0x00020000 */

+#define RCC_RSR_CPURSTF                        RCC_RSR_CPURSTF_Msk

+#define RCC_RSR_D1RSTF_Pos                     (19U)

+#define RCC_RSR_D1RSTF_Msk                     (0x1UL << RCC_RSR_D1RSTF_Pos)   /*!< 0x00080000 */

+#define RCC_RSR_D1RSTF                         RCC_RSR_D1RSTF_Msk

+#define RCC_RSR_D2RSTF_Pos                     (20U)

+#define RCC_RSR_D2RSTF_Msk                     (0x1UL << RCC_RSR_D2RSTF_Pos)   /*!< 0x00100000 */

+#define RCC_RSR_D2RSTF                         RCC_RSR_D2RSTF_Msk

+#define RCC_RSR_BORRSTF_Pos                    (21U)

+#define RCC_RSR_BORRSTF_Msk                    (0x1UL << RCC_RSR_BORRSTF_Pos)  /*!< 0x00200000 */

+#define RCC_RSR_BORRSTF                        RCC_RSR_BORRSTF_Msk

+#define RCC_RSR_PINRSTF_Pos                    (22U)

+#define RCC_RSR_PINRSTF_Msk                    (0x1UL << RCC_RSR_PINRSTF_Pos)  /*!< 0x00400000 */

+#define RCC_RSR_PINRSTF                        RCC_RSR_PINRSTF_Msk

+#define RCC_RSR_PORRSTF_Pos                    (23U)

+#define RCC_RSR_PORRSTF_Msk                    (0x1UL << RCC_RSR_PORRSTF_Pos)  /*!< 0x00800000 */

+#define RCC_RSR_PORRSTF                        RCC_RSR_PORRSTF_Msk

+#define RCC_RSR_SFTRSTF_Pos                    (24U)

+#define RCC_RSR_SFTRSTF_Msk                    (0x1UL << RCC_RSR_SFTRSTF_Pos)  /*!< 0x01000000 */

+#define RCC_RSR_SFTRSTF                        RCC_RSR_SFTRSTF_Msk

+#define RCC_RSR_IWDG1RSTF_Pos                  (26U)

+#define RCC_RSR_IWDG1RSTF_Msk                  (0x1UL << RCC_RSR_IWDG1RSTF_Pos) /*!< 0x04000000 */

+#define RCC_RSR_IWDG1RSTF                      RCC_RSR_IWDG1RSTF_Msk

+#define RCC_RSR_WWDG1RSTF_Pos                  (28U)

+#define RCC_RSR_WWDG1RSTF_Msk                  (0x1UL << RCC_RSR_WWDG1RSTF_Pos) /*!< 0x10000000 */

+#define RCC_RSR_WWDG1RSTF                      RCC_RSR_WWDG1RSTF_Msk

+

+#define RCC_RSR_LPWRRSTF_Pos                   (30U)

+#define RCC_RSR_LPWRRSTF_Msk                   (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */

+#define RCC_RSR_LPWRRSTF                       RCC_RSR_LPWRRSTF_Msk

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    RNG                                     */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for RNG_CR register  *******************/

+#define RNG_CR_RNGEN_Pos    (2U)

+#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */

+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk

+#define RNG_CR_IE_Pos       (3U)

+#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */

+#define RNG_CR_IE           RNG_CR_IE_Msk

+#define RNG_CR_CED_Pos      (5U)

+#define RNG_CR_CED_Msk      (0x1UL << RNG_CR_CED_Pos)                          /*!< 0x00000020 */

+#define RNG_CR_CED          RNG_CR_CED_Msk

+

+/********************  Bits definition for RNG_SR register  *******************/

+#define RNG_SR_DRDY_Pos     (0U)

+#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */

+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk

+#define RNG_SR_CECS_Pos     (1U)

+#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */

+#define RNG_SR_CECS         RNG_SR_CECS_Msk

+#define RNG_SR_SECS_Pos     (2U)

+#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */

+#define RNG_SR_SECS         RNG_SR_SECS_Msk

+#define RNG_SR_CEIS_Pos     (5U)

+#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */

+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk

+#define RNG_SR_SEIS_Pos     (6U)

+#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */

+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                           Real-Time Clock (RTC)                            */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for RTC_TR register  *******************/

+#define RTC_TR_PM_Pos                  (22U)

+#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */

+#define RTC_TR_PM                      RTC_TR_PM_Msk

+#define RTC_TR_HT_Pos                  (20U)

+#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */

+#define RTC_TR_HT                      RTC_TR_HT_Msk

+#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */

+#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */

+#define RTC_TR_HU_Pos                  (16U)

+#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */

+#define RTC_TR_HU                      RTC_TR_HU_Msk

+#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */

+#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */

+#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */

+#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */

+#define RTC_TR_MNT_Pos                 (12U)

+#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */

+#define RTC_TR_MNT                     RTC_TR_MNT_Msk

+#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */

+#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */

+#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */

+#define RTC_TR_MNU_Pos                 (8U)

+#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */

+#define RTC_TR_MNU                     RTC_TR_MNU_Msk

+#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */

+#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */

+#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */

+#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */

+#define RTC_TR_ST_Pos                  (4U)

+#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */

+#define RTC_TR_ST                      RTC_TR_ST_Msk

+#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */

+#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */

+#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */

+#define RTC_TR_SU_Pos                  (0U)

+#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */

+#define RTC_TR_SU                      RTC_TR_SU_Msk

+#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */

+#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */

+#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */

+#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_DR register  *******************/

+#define RTC_DR_YT_Pos                  (20U)

+#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */

+#define RTC_DR_YT                      RTC_DR_YT_Msk

+#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */

+#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */

+#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */

+#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */

+#define RTC_DR_YU_Pos                  (16U)

+#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */

+#define RTC_DR_YU                      RTC_DR_YU_Msk

+#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */

+#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */

+#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */

+#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */

+#define RTC_DR_WDU_Pos                 (13U)

+#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */

+#define RTC_DR_WDU                     RTC_DR_WDU_Msk

+#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */

+#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */

+#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */

+#define RTC_DR_MT_Pos                  (12U)

+#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */

+#define RTC_DR_MT                      RTC_DR_MT_Msk

+#define RTC_DR_MU_Pos                  (8U)

+#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */

+#define RTC_DR_MU                      RTC_DR_MU_Msk

+#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */

+#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */

+#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */

+#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */

+#define RTC_DR_DT_Pos                  (4U)

+#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */

+#define RTC_DR_DT                      RTC_DR_DT_Msk

+#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */

+#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */

+#define RTC_DR_DU_Pos                  (0U)

+#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */

+#define RTC_DR_DU                      RTC_DR_DU_Msk

+#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */

+#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */

+#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */

+#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_CR register  *******************/

+#define RTC_CR_ITSE_Pos                (24U)

+#define RTC_CR_ITSE_Msk                (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */

+#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk

+#define RTC_CR_COE_Pos                 (23U)

+#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */

+#define RTC_CR_COE                     RTC_CR_COE_Msk

+#define RTC_CR_OSEL_Pos                (21U)

+#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */

+#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk

+#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */

+#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */

+#define RTC_CR_POL_Pos                 (20U)

+#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */

+#define RTC_CR_POL                     RTC_CR_POL_Msk

+#define RTC_CR_COSEL_Pos               (19U)

+#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */

+#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk

+#define RTC_CR_BKP_Pos                 (18U)

+#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */

+#define RTC_CR_BKP                     RTC_CR_BKP_Msk

+#define RTC_CR_SUB1H_Pos               (17U)

+#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */

+#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk

+#define RTC_CR_ADD1H_Pos               (16U)

+#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */

+#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk

+#define RTC_CR_TSIE_Pos                (15U)

+#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */

+#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk

+#define RTC_CR_WUTIE_Pos               (14U)

+#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */

+#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk

+#define RTC_CR_ALRBIE_Pos              (13U)

+#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */

+#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk

+#define RTC_CR_ALRAIE_Pos              (12U)

+#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */

+#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk

+#define RTC_CR_TSE_Pos                 (11U)

+#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */

+#define RTC_CR_TSE                     RTC_CR_TSE_Msk

+#define RTC_CR_WUTE_Pos                (10U)

+#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */

+#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk

+#define RTC_CR_ALRBE_Pos               (9U)

+#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */

+#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk

+#define RTC_CR_ALRAE_Pos               (8U)

+#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */

+#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk

+#define RTC_CR_FMT_Pos                 (6U)

+#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */

+#define RTC_CR_FMT                     RTC_CR_FMT_Msk

+#define RTC_CR_BYPSHAD_Pos             (5U)

+#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */

+#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk

+#define RTC_CR_REFCKON_Pos             (4U)

+#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */

+#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk

+#define RTC_CR_TSEDGE_Pos              (3U)

+#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */

+#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk

+#define RTC_CR_WUCKSEL_Pos             (0U)

+#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */

+#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk

+#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */

+#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */

+#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */

+

+/********************  Bits definition for RTC_ISR register  ******************/

+#define RTC_ISR_ITSF_Pos               (17U)

+#define RTC_ISR_ITSF_Msk               (0x1UL << RTC_ISR_ITSF_Pos)             /*!< 0x00020000 */

+#define RTC_ISR_ITSF                   RTC_ISR_ITSF_Msk

+#define RTC_ISR_RECALPF_Pos            (16U)

+#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)          /*!< 0x00010000 */

+#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk

+#define RTC_ISR_TAMP3F_Pos             (15U)

+#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)           /*!< 0x00008000 */

+#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk

+#define RTC_ISR_TAMP2F_Pos             (14U)

+#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)           /*!< 0x00004000 */

+#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk

+#define RTC_ISR_TAMP1F_Pos             (13U)

+#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)           /*!< 0x00002000 */

+#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk

+#define RTC_ISR_TSOVF_Pos              (12U)

+#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)            /*!< 0x00001000 */

+#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk

+#define RTC_ISR_TSF_Pos                (11U)

+#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)              /*!< 0x00000800 */

+#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk

+#define RTC_ISR_WUTF_Pos               (10U)

+#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)             /*!< 0x00000400 */

+#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk

+#define RTC_ISR_ALRBF_Pos              (9U)

+#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)            /*!< 0x00000200 */

+#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk

+#define RTC_ISR_ALRAF_Pos              (8U)

+#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)            /*!< 0x00000100 */

+#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk

+#define RTC_ISR_INIT_Pos               (7U)

+#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)             /*!< 0x00000080 */

+#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk

+#define RTC_ISR_INITF_Pos              (6U)

+#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)            /*!< 0x00000040 */

+#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk

+#define RTC_ISR_RSF_Pos                (5U)

+#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)              /*!< 0x00000020 */

+#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk

+#define RTC_ISR_INITS_Pos              (4U)

+#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)            /*!< 0x00000010 */

+#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk

+#define RTC_ISR_SHPF_Pos               (3U)

+#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)             /*!< 0x00000008 */

+#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk

+#define RTC_ISR_WUTWF_Pos              (2U)

+#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)            /*!< 0x00000004 */

+#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk

+#define RTC_ISR_ALRBWF_Pos             (1U)

+#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)           /*!< 0x00000002 */

+#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk

+#define RTC_ISR_ALRAWF_Pos             (0U)

+#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)           /*!< 0x00000001 */

+#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk

+

+/********************  Bits definition for RTC_PRER register  *****************/

+#define RTC_PRER_PREDIV_A_Pos          (16U)

+#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */

+#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk

+#define RTC_PRER_PREDIV_S_Pos          (0U)

+#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */

+#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk

+

+/********************  Bits definition for RTC_WUTR register  *****************/

+#define RTC_WUTR_WUT_Pos               (0U)

+#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */

+#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk

+

+/********************  Bits definition for RTC_ALRMAR register  ***************/

+#define RTC_ALRMAR_MSK4_Pos            (31U)

+#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */

+#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk

+#define RTC_ALRMAR_WDSEL_Pos           (30U)

+#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */

+#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk

+#define RTC_ALRMAR_DT_Pos              (28U)

+#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */

+#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk

+#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */

+#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */

+#define RTC_ALRMAR_DU_Pos              (24U)

+#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */

+#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk

+#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */

+#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */

+#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */

+#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */

+#define RTC_ALRMAR_MSK3_Pos            (23U)

+#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */

+#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk

+#define RTC_ALRMAR_PM_Pos              (22U)

+#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */

+#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk

+#define RTC_ALRMAR_HT_Pos              (20U)

+#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */

+#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk

+#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */

+#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */

+#define RTC_ALRMAR_HU_Pos              (16U)

+#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */

+#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk

+#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */

+#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */

+#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */

+#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */

+#define RTC_ALRMAR_MSK2_Pos            (15U)

+#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */

+#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk

+#define RTC_ALRMAR_MNT_Pos             (12U)

+#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */

+#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk

+#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */

+#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */

+#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */

+#define RTC_ALRMAR_MNU_Pos             (8U)

+#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */

+#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk

+#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */

+#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */

+#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */

+#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */

+#define RTC_ALRMAR_MSK1_Pos            (7U)

+#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */

+#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk

+#define RTC_ALRMAR_ST_Pos              (4U)

+#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */

+#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk

+#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */

+#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */

+#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */

+#define RTC_ALRMAR_SU_Pos              (0U)

+#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */

+#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk

+#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */

+#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */

+#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */

+#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_ALRMBR register  ***************/

+#define RTC_ALRMBR_MSK4_Pos            (31U)

+#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */

+#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk

+#define RTC_ALRMBR_WDSEL_Pos           (30U)

+#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */

+#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk

+#define RTC_ALRMBR_DT_Pos              (28U)

+#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */

+#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk

+#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */

+#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */

+#define RTC_ALRMBR_DU_Pos              (24U)

+#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */

+#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk

+#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */

+#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */

+#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */

+#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */

+#define RTC_ALRMBR_MSK3_Pos            (23U)

+#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */

+#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk

+#define RTC_ALRMBR_PM_Pos              (22U)

+#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */

+#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk

+#define RTC_ALRMBR_HT_Pos              (20U)

+#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */

+#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk

+#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */

+#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */

+#define RTC_ALRMBR_HU_Pos              (16U)

+#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */

+#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk

+#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */

+#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */

+#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */

+#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */

+#define RTC_ALRMBR_MSK2_Pos            (15U)

+#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */

+#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk

+#define RTC_ALRMBR_MNT_Pos             (12U)

+#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */

+#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk

+#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */

+#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */

+#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */

+#define RTC_ALRMBR_MNU_Pos             (8U)

+#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */

+#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk

+#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */

+#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */

+#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */

+#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */

+#define RTC_ALRMBR_MSK1_Pos            (7U)

+#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */

+#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk

+#define RTC_ALRMBR_ST_Pos              (4U)

+#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */

+#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk

+#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */

+#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */

+#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */

+#define RTC_ALRMBR_SU_Pos              (0U)

+#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */

+#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk

+#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */

+#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */

+#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */

+#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_WPR register  ******************/

+#define RTC_WPR_KEY_Pos                (0U)

+#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */

+#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk

+

+/********************  Bits definition for RTC_SSR register  ******************/

+#define RTC_SSR_SS_Pos                 (0U)

+#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)            /*!< 0x0000FFFF */

+#define RTC_SSR_SS                     RTC_SSR_SS_Msk

+

+/********************  Bits definition for RTC_SHIFTR register  ***************/

+#define RTC_SHIFTR_SUBFS_Pos           (0U)

+#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */

+#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk

+#define RTC_SHIFTR_ADD1S_Pos           (31U)

+#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */

+#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk

+

+/********************  Bits definition for RTC_TSTR register  *****************/

+#define RTC_TSTR_PM_Pos                (22U)

+#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */

+#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk

+#define RTC_TSTR_HT_Pos                (20U)

+#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */

+#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk

+#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */

+#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */

+#define RTC_TSTR_HU_Pos                (16U)

+#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */

+#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk

+#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */

+#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */

+#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */

+#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */

+#define RTC_TSTR_MNT_Pos               (12U)

+#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */

+#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk

+#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */

+#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */

+#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */

+#define RTC_TSTR_MNU_Pos               (8U)

+#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */

+#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk

+#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */

+#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */

+#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */

+#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */

+#define RTC_TSTR_ST_Pos                (4U)

+#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */

+#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk

+#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */

+#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */

+#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */

+#define RTC_TSTR_SU_Pos                (0U)

+#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */

+#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk

+#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */

+#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */

+#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */

+#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_TSDR register  *****************/

+#define RTC_TSDR_WDU_Pos               (13U)

+#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */

+#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk

+#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */

+#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */

+#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */

+#define RTC_TSDR_MT_Pos                (12U)

+#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */

+#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk

+#define RTC_TSDR_MU_Pos                (8U)

+#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */

+#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk

+#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */

+#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */

+#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */

+#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */

+#define RTC_TSDR_DT_Pos                (4U)

+#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */

+#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk

+#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */

+#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */

+#define RTC_TSDR_DU_Pos                (0U)

+#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */

+#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk

+#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */

+#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */

+#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */

+#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_TSSSR register  ****************/

+#define RTC_TSSSR_SS_Pos               (0U)

+#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)          /*!< 0x0000FFFF */

+#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk

+

+/********************  Bits definition for RTC_CALR register  *****************/

+#define RTC_CALR_CALP_Pos              (15U)

+#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */

+#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk

+#define RTC_CALR_CALW8_Pos             (14U)

+#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */

+#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk

+#define RTC_CALR_CALW16_Pos            (13U)

+#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */

+#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk

+#define RTC_CALR_CALM_Pos              (0U)

+#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */

+#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk

+#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */

+#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */

+#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */

+#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */

+#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */

+#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */

+#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */

+#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */

+#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */

+

+/********************  Bits definition for RTC_TAMPCR register  ***************/

+#define RTC_TAMPCR_TAMP3MF_Pos         (24U)

+#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)       /*!< 0x01000000 */

+#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk

+#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)

+#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)  /*!< 0x00800000 */

+#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk

+#define RTC_TAMPCR_TAMP3IE_Pos         (22U)

+#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)       /*!< 0x00400000 */

+#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk

+#define RTC_TAMPCR_TAMP2MF_Pos         (21U)

+#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)       /*!< 0x00200000 */

+#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk

+#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)

+#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)  /*!< 0x00100000 */

+#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk

+#define RTC_TAMPCR_TAMP2IE_Pos         (19U)

+#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)       /*!< 0x00080000 */

+#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk

+#define RTC_TAMPCR_TAMP1MF_Pos         (18U)

+#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)       /*!< 0x00040000 */

+#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk

+#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)

+#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)  /*!< 0x00020000 */

+#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk

+#define RTC_TAMPCR_TAMP1IE_Pos         (16U)

+#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)       /*!< 0x00010000 */

+#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk

+#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)

+#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)     /*!< 0x00008000 */

+#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk

+#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)

+#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)      /*!< 0x00006000 */

+#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk

+#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */

+#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */

+#define RTC_TAMPCR_TAMPFLT_Pos         (11U)

+#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)       /*!< 0x00001800 */

+#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk

+#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */

+#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */

+#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)

+#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)      /*!< 0x00000700 */

+#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk

+#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */

+#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */

+#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */

+#define RTC_TAMPCR_TAMPTS_Pos          (7U)

+#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)        /*!< 0x00000080 */

+#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk

+#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)

+#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)      /*!< 0x00000040 */

+#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk

+#define RTC_TAMPCR_TAMP3E_Pos          (5U)

+#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)        /*!< 0x00000020 */

+#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk

+#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)

+#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)      /*!< 0x00000010 */

+#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk

+#define RTC_TAMPCR_TAMP2E_Pos          (3U)

+#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)        /*!< 0x00000008 */

+#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk

+#define RTC_TAMPCR_TAMPIE_Pos          (2U)

+#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)        /*!< 0x00000004 */

+#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk

+#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)

+#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)      /*!< 0x00000002 */

+#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk

+#define RTC_TAMPCR_TAMP1E_Pos          (0U)

+#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)        /*!< 0x00000001 */

+#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk

+

+/********************  Bits definition for RTC_ALRMASSR register  *************/

+#define RTC_ALRMASSR_MASKSS_Pos        (24U)

+#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x0F000000 */

+#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk

+#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */

+#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */

+#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */

+#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */

+#define RTC_ALRMASSR_SS_Pos            (0U)

+#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */

+#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk

+

+/********************  Bits definition for RTC_ALRMBSSR register  *************/

+#define RTC_ALRMBSSR_MASKSS_Pos        (24U)

+#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x0F000000 */

+#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk

+#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */

+#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */

+#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */

+#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */

+#define RTC_ALRMBSSR_SS_Pos            (0U)

+#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */

+#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk

+

+/********************  Bits definition for RTC_OR register  *******************/

+#define RTC_OR_OUT_RMP_Pos             (1U)

+#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)           /*!< 0x00000002 */

+#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk

+#define RTC_OR_ALARMOUTTYPE_Pos        (0U)

+#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)      /*!< 0x00000001 */

+#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk

+

+/********************  Bits definition for RTC_BKP0R register  ****************/

+#define RTC_BKP0R_Pos                  (0U)

+#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP0R                      RTC_BKP0R_Msk

+

+/********************  Bits definition for RTC_BKP1R register  ****************/

+#define RTC_BKP1R_Pos                  (0U)

+#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP1R                      RTC_BKP1R_Msk

+

+/********************  Bits definition for RTC_BKP2R register  ****************/

+#define RTC_BKP2R_Pos                  (0U)

+#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP2R                      RTC_BKP2R_Msk

+

+/********************  Bits definition for RTC_BKP3R register  ****************/

+#define RTC_BKP3R_Pos                  (0U)

+#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP3R                      RTC_BKP3R_Msk

+

+/********************  Bits definition for RTC_BKP4R register  ****************/

+#define RTC_BKP4R_Pos                  (0U)

+#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP4R                      RTC_BKP4R_Msk

+

+/********************  Bits definition for RTC_BKP5R register  ****************/

+#define RTC_BKP5R_Pos                  (0U)

+#define RTC_BKP5R_Msk                  (0xFFFFFFFFUL << RTC_BKP5R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP5R                      RTC_BKP5R_Msk

+

+/********************  Bits definition for RTC_BKP6R register  ****************/

+#define RTC_BKP6R_Pos                  (0U)

+#define RTC_BKP6R_Msk                  (0xFFFFFFFFUL << RTC_BKP6R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP6R                      RTC_BKP6R_Msk

+

+/********************  Bits definition for RTC_BKP7R register  ****************/

+#define RTC_BKP7R_Pos                  (0U)

+#define RTC_BKP7R_Msk                  (0xFFFFFFFFUL << RTC_BKP7R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP7R                      RTC_BKP7R_Msk

+

+/********************  Bits definition for RTC_BKP8R register  ****************/

+#define RTC_BKP8R_Pos                  (0U)

+#define RTC_BKP8R_Msk                  (0xFFFFFFFFUL << RTC_BKP8R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP8R                      RTC_BKP8R_Msk

+

+/********************  Bits definition for RTC_BKP9R register  ****************/

+#define RTC_BKP9R_Pos                  (0U)

+#define RTC_BKP9R_Msk                  (0xFFFFFFFFUL << RTC_BKP9R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP9R                      RTC_BKP9R_Msk

+

+/********************  Bits definition for RTC_BKP10R register  ***************/

+#define RTC_BKP10R_Pos                 (0U)

+#define RTC_BKP10R_Msk                 (0xFFFFFFFFUL << RTC_BKP10R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP10R                     RTC_BKP10R_Msk

+

+/********************  Bits definition for RTC_BKP11R register  ***************/

+#define RTC_BKP11R_Pos                 (0U)

+#define RTC_BKP11R_Msk                 (0xFFFFFFFFUL << RTC_BKP11R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP11R                     RTC_BKP11R_Msk

+

+/********************  Bits definition for RTC_BKP12R register  ***************/

+#define RTC_BKP12R_Pos                 (0U)

+#define RTC_BKP12R_Msk                 (0xFFFFFFFFUL << RTC_BKP12R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP12R                     RTC_BKP12R_Msk

+

+/********************  Bits definition for RTC_BKP13R register  ***************/

+#define RTC_BKP13R_Pos                 (0U)

+#define RTC_BKP13R_Msk                 (0xFFFFFFFFUL << RTC_BKP13R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP13R                     RTC_BKP13R_Msk

+

+/********************  Bits definition for RTC_BKP14R register  ***************/

+#define RTC_BKP14R_Pos                 (0U)

+#define RTC_BKP14R_Msk                 (0xFFFFFFFFUL << RTC_BKP14R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP14R                     RTC_BKP14R_Msk

+

+/********************  Bits definition for RTC_BKP15R register  ***************/

+#define RTC_BKP15R_Pos                 (0U)

+#define RTC_BKP15R_Msk                 (0xFFFFFFFFUL << RTC_BKP15R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP15R                     RTC_BKP15R_Msk

+

+/********************  Bits definition for RTC_BKP16R register  ***************/

+#define RTC_BKP16R_Pos                 (0U)

+#define RTC_BKP16R_Msk                 (0xFFFFFFFFUL << RTC_BKP16R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP16R                     RTC_BKP16R_Msk

+

+/********************  Bits definition for RTC_BKP17R register  ***************/

+#define RTC_BKP17R_Pos                 (0U)

+#define RTC_BKP17R_Msk                 (0xFFFFFFFFUL << RTC_BKP17R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP17R                     RTC_BKP17R_Msk

+

+/********************  Bits definition for RTC_BKP18R register  ***************/

+#define RTC_BKP18R_Pos                 (0U)

+#define RTC_BKP18R_Msk                 (0xFFFFFFFFUL << RTC_BKP18R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP18R                     RTC_BKP18R_Msk

+

+/********************  Bits definition for RTC_BKP19R register  ***************/

+#define RTC_BKP19R_Pos                 (0U)

+#define RTC_BKP19R_Msk                 (0xFFFFFFFFUL << RTC_BKP19R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP19R                     RTC_BKP19R_Msk

+

+/********************  Bits definition for RTC_BKP20R register  ***************/

+#define RTC_BKP20R_Pos                 (0U)

+#define RTC_BKP20R_Msk                 (0xFFFFFFFFUL << RTC_BKP20R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP20R                     RTC_BKP20R_Msk

+

+/********************  Bits definition for RTC_BKP21R register  ***************/

+#define RTC_BKP21R_Pos                 (0U)

+#define RTC_BKP21R_Msk                 (0xFFFFFFFFUL << RTC_BKP21R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP21R                     RTC_BKP21R_Msk

+

+/********************  Bits definition for RTC_BKP22R register  ***************/

+#define RTC_BKP22R_Pos                 (0U)

+#define RTC_BKP22R_Msk                 (0xFFFFFFFFUL << RTC_BKP22R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP22R                     RTC_BKP22R_Msk

+

+/********************  Bits definition for RTC_BKP23R register  ***************/

+#define RTC_BKP23R_Pos                 (0U)

+#define RTC_BKP23R_Msk                 (0xFFFFFFFFUL << RTC_BKP23R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP23R                     RTC_BKP23R_Msk

+

+/********************  Bits definition for RTC_BKP24R register  ***************/

+#define RTC_BKP24R_Pos                 (0U)

+#define RTC_BKP24R_Msk                 (0xFFFFFFFFUL << RTC_BKP24R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP24R                     RTC_BKP24R_Msk

+

+/********************  Bits definition for RTC_BKP25R register  ***************/

+#define RTC_BKP25R_Pos                 (0U)

+#define RTC_BKP25R_Msk                 (0xFFFFFFFFUL << RTC_BKP25R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP25R                     RTC_BKP25R_Msk

+

+/********************  Bits definition for RTC_BKP26R register  ***************/

+#define RTC_BKP26R_Pos                 (0U)

+#define RTC_BKP26R_Msk                 (0xFFFFFFFFUL << RTC_BKP26R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP26R                     RTC_BKP26R_Msk

+

+/********************  Bits definition for RTC_BKP27R register  ***************/

+#define RTC_BKP27R_Pos                 (0U)

+#define RTC_BKP27R_Msk                 (0xFFFFFFFFUL << RTC_BKP27R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP27R                     RTC_BKP27R_Msk

+

+/********************  Bits definition for RTC_BKP28R register  ***************/

+#define RTC_BKP28R_Pos                 (0U)

+#define RTC_BKP28R_Msk                 (0xFFFFFFFFUL << RTC_BKP28R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP28R                     RTC_BKP28R_Msk

+

+/********************  Bits definition for RTC_BKP29R register  ***************/

+#define RTC_BKP29R_Pos                 (0U)

+#define RTC_BKP29R_Msk                 (0xFFFFFFFFUL << RTC_BKP29R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP29R                     RTC_BKP29R_Msk

+

+/********************  Bits definition for RTC_BKP30R register  ***************/

+#define RTC_BKP30R_Pos                 (0U)

+#define RTC_BKP30R_Msk                 (0xFFFFFFFFUL << RTC_BKP30R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP30R                     RTC_BKP30R_Msk

+

+/********************  Bits definition for RTC_BKP31R register  ***************/

+#define RTC_BKP31R_Pos                 (0U)

+#define RTC_BKP31R_Msk                 (0xFFFFFFFFUL << RTC_BKP31R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP31R                     RTC_BKP31R_Msk

+

+/******************** Number of backup registers ******************************/

+#define RTC_BKP_NUMBER_Pos             (5U)

+#define RTC_BKP_NUMBER_Msk             (0x1UL << RTC_BKP_NUMBER_Pos)           /*!< 0x00000020 */

+#define RTC_BKP_NUMBER                 RTC_BKP_NUMBER_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                              SPDIF-RX Interface                            */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for SPDIF_CR register  ******************/

+#define SPDIFRX_CR_SPDIFEN_Pos      (0U)

+#define SPDIFRX_CR_SPDIFEN_Msk      (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)          /*!< 0x00000003 */

+#define SPDIFRX_CR_SPDIFEN          SPDIFRX_CR_SPDIFEN_Msk                     /*!<Peripheral Block Enable                      */

+#define SPDIFRX_CR_RXDMAEN_Pos      (2U)

+#define SPDIFRX_CR_RXDMAEN_Msk      (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)          /*!< 0x00000004 */

+#define SPDIFRX_CR_RXDMAEN          SPDIFRX_CR_RXDMAEN_Msk                     /*!<Receiver DMA Enable for data flow            */

+#define SPDIFRX_CR_RXSTEO_Pos       (3U)

+#define SPDIFRX_CR_RXSTEO_Msk       (0x1UL << SPDIFRX_CR_RXSTEO_Pos)           /*!< 0x00000008 */

+#define SPDIFRX_CR_RXSTEO           SPDIFRX_CR_RXSTEO_Msk                      /*!<Stereo Mode                                  */

+#define SPDIFRX_CR_DRFMT_Pos        (4U)

+#define SPDIFRX_CR_DRFMT_Msk        (0x3UL << SPDIFRX_CR_DRFMT_Pos)            /*!< 0x00000030 */

+#define SPDIFRX_CR_DRFMT            SPDIFRX_CR_DRFMT_Msk                       /*!<RX Data format                               */

+#define SPDIFRX_CR_PMSK_Pos         (6U)

+#define SPDIFRX_CR_PMSK_Msk         (0x1UL << SPDIFRX_CR_PMSK_Pos)             /*!< 0x00000040 */

+#define SPDIFRX_CR_PMSK             SPDIFRX_CR_PMSK_Msk                        /*!<Mask Parity error bit                        */

+#define SPDIFRX_CR_VMSK_Pos         (7U)

+#define SPDIFRX_CR_VMSK_Msk         (0x1UL << SPDIFRX_CR_VMSK_Pos)             /*!< 0x00000080 */

+#define SPDIFRX_CR_VMSK             SPDIFRX_CR_VMSK_Msk                        /*!<Mask of Validity bit                         */

+#define SPDIFRX_CR_CUMSK_Pos        (8U)

+#define SPDIFRX_CR_CUMSK_Msk        (0x1UL << SPDIFRX_CR_CUMSK_Pos)            /*!< 0x00000100 */

+#define SPDIFRX_CR_CUMSK            SPDIFRX_CR_CUMSK_Msk                       /*!<Mask of channel status and user bits         */

+#define SPDIFRX_CR_PTMSK_Pos        (9U)

+#define SPDIFRX_CR_PTMSK_Msk        (0x1UL << SPDIFRX_CR_PTMSK_Pos)            /*!< 0x00000200 */

+#define SPDIFRX_CR_PTMSK            SPDIFRX_CR_PTMSK_Msk                       /*!<Mask of Preamble Type bits                   */

+#define SPDIFRX_CR_CBDMAEN_Pos      (10U)

+#define SPDIFRX_CR_CBDMAEN_Msk      (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)          /*!< 0x00000400 */

+#define SPDIFRX_CR_CBDMAEN          SPDIFRX_CR_CBDMAEN_Msk                     /*!<Control Buffer DMA ENable for control flow   */

+#define SPDIFRX_CR_CHSEL_Pos        (11U)

+#define SPDIFRX_CR_CHSEL_Msk        (0x1UL << SPDIFRX_CR_CHSEL_Pos)            /*!< 0x00000800 */

+#define SPDIFRX_CR_CHSEL            SPDIFRX_CR_CHSEL_Msk                       /*!<Channel Selection                            */

+#define SPDIFRX_CR_NBTR_Pos         (12U)

+#define SPDIFRX_CR_NBTR_Msk         (0x3UL << SPDIFRX_CR_NBTR_Pos)             /*!< 0x00003000 */

+#define SPDIFRX_CR_NBTR             SPDIFRX_CR_NBTR_Msk                        /*!<Maximum allowed re-tries during synchronization phase */

+#define SPDIFRX_CR_WFA_Pos          (14U)

+#define SPDIFRX_CR_WFA_Msk          (0x1UL << SPDIFRX_CR_WFA_Pos)              /*!< 0x00004000 */

+#define SPDIFRX_CR_WFA              SPDIFRX_CR_WFA_Msk                         /*!<Wait For Activity     */

+#define SPDIFRX_CR_INSEL_Pos        (16U)

+#define SPDIFRX_CR_INSEL_Msk        (0x7UL << SPDIFRX_CR_INSEL_Pos)            /*!< 0x00070000 */

+#define SPDIFRX_CR_INSEL            SPDIFRX_CR_INSEL_Msk                       /*!<SPDIF input selection */

+#define SPDIFRX_CR_CKSEN_Pos        (20U)

+#define SPDIFRX_CR_CKSEN_Msk        (0x1UL << SPDIFRX_CR_CKSEN_Pos)            /*!< 0x00100000 */

+#define SPDIFRX_CR_CKSEN            SPDIFRX_CR_CKSEN_Msk                       /*!<Symbol Clock Enable */

+#define SPDIFRX_CR_CKSBKPEN_Pos     (21U)

+#define SPDIFRX_CR_CKSBKPEN_Msk     (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)         /*!< 0x00200000 */

+#define SPDIFRX_CR_CKSBKPEN         SPDIFRX_CR_CKSBKPEN_Msk                    /*!<Backup Symbol Clock Enable */

+

+/*******************  Bit definition for SPDIFRX_IMR register  *******************/

+#define SPDIFRX_IMR_RXNEIE_Pos      (0U)

+#define SPDIFRX_IMR_RXNEIE_Msk      (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)          /*!< 0x00000001 */

+#define SPDIFRX_IMR_RXNEIE          SPDIFRX_IMR_RXNEIE_Msk                     /*!<RXNE interrupt enable                              */

+#define SPDIFRX_IMR_CSRNEIE_Pos     (1U)

+#define SPDIFRX_IMR_CSRNEIE_Msk     (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)         /*!< 0x00000002 */

+#define SPDIFRX_IMR_CSRNEIE         SPDIFRX_IMR_CSRNEIE_Msk                    /*!<Control Buffer Ready Interrupt Enable              */

+#define SPDIFRX_IMR_PERRIE_Pos      (2U)

+#define SPDIFRX_IMR_PERRIE_Msk      (0x1UL << SPDIFRX_IMR_PERRIE_Pos)          /*!< 0x00000004 */

+#define SPDIFRX_IMR_PERRIE          SPDIFRX_IMR_PERRIE_Msk                     /*!<Parity error interrupt enable                      */

+#define SPDIFRX_IMR_OVRIE_Pos       (3U)

+#define SPDIFRX_IMR_OVRIE_Msk       (0x1UL << SPDIFRX_IMR_OVRIE_Pos)           /*!< 0x00000008 */

+#define SPDIFRX_IMR_OVRIE           SPDIFRX_IMR_OVRIE_Msk                      /*!<Overrun error Interrupt Enable                     */

+#define SPDIFRX_IMR_SBLKIE_Pos      (4U)

+#define SPDIFRX_IMR_SBLKIE_Msk      (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)          /*!< 0x00000010 */

+#define SPDIFRX_IMR_SBLKIE          SPDIFRX_IMR_SBLKIE_Msk                     /*!<Synchronization Block Detected Interrupt Enable    */

+#define SPDIFRX_IMR_SYNCDIE_Pos     (5U)

+#define SPDIFRX_IMR_SYNCDIE_Msk     (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)         /*!< 0x00000020 */

+#define SPDIFRX_IMR_SYNCDIE         SPDIFRX_IMR_SYNCDIE_Msk                    /*!<Synchronization Done                               */

+#define SPDIFRX_IMR_IFEIE_Pos       (6U)

+#define SPDIFRX_IMR_IFEIE_Msk       (0x1UL << SPDIFRX_IMR_IFEIE_Pos)           /*!< 0x00000040 */

+#define SPDIFRX_IMR_IFEIE           SPDIFRX_IMR_IFEIE_Msk                      /*!<Serial Interface Error Interrupt Enable            */

+

+/*******************  Bit definition for SPDIFRX_SR register  *******************/

+#define SPDIFRX_SR_RXNE_Pos         (0U)

+#define SPDIFRX_SR_RXNE_Msk         (0x1UL << SPDIFRX_SR_RXNE_Pos)             /*!< 0x00000001 */

+#define SPDIFRX_SR_RXNE             SPDIFRX_SR_RXNE_Msk                        /*!<Read data register not empty                          */

+#define SPDIFRX_SR_CSRNE_Pos        (1U)

+#define SPDIFRX_SR_CSRNE_Msk        (0x1UL << SPDIFRX_SR_CSRNE_Pos)            /*!< 0x00000002 */

+#define SPDIFRX_SR_CSRNE            SPDIFRX_SR_CSRNE_Msk                       /*!<The Control Buffer register is not empty              */

+#define SPDIFRX_SR_PERR_Pos         (2U)

+#define SPDIFRX_SR_PERR_Msk         (0x1UL << SPDIFRX_SR_PERR_Pos)             /*!< 0x00000004 */

+#define SPDIFRX_SR_PERR             SPDIFRX_SR_PERR_Msk                        /*!<Parity error                                          */

+#define SPDIFRX_SR_OVR_Pos          (3U)

+#define SPDIFRX_SR_OVR_Msk          (0x1UL << SPDIFRX_SR_OVR_Pos)              /*!< 0x00000008 */

+#define SPDIFRX_SR_OVR              SPDIFRX_SR_OVR_Msk                         /*!<Overrun error                                         */

+#define SPDIFRX_SR_SBD_Pos          (4U)

+#define SPDIFRX_SR_SBD_Msk          (0x1UL << SPDIFRX_SR_SBD_Pos)              /*!< 0x00000010 */

+#define SPDIFRX_SR_SBD              SPDIFRX_SR_SBD_Msk                         /*!<Synchronization Block Detected                        */

+#define SPDIFRX_SR_SYNCD_Pos        (5U)

+#define SPDIFRX_SR_SYNCD_Msk        (0x1UL << SPDIFRX_SR_SYNCD_Pos)            /*!< 0x00000020 */

+#define SPDIFRX_SR_SYNCD            SPDIFRX_SR_SYNCD_Msk                       /*!<Synchronization Done                                  */

+#define SPDIFRX_SR_FERR_Pos         (6U)

+#define SPDIFRX_SR_FERR_Msk         (0x1UL << SPDIFRX_SR_FERR_Pos)             /*!< 0x00000040 */

+#define SPDIFRX_SR_FERR             SPDIFRX_SR_FERR_Msk                        /*!<Framing error                                         */

+#define SPDIFRX_SR_SERR_Pos         (7U)

+#define SPDIFRX_SR_SERR_Msk         (0x1UL << SPDIFRX_SR_SERR_Pos)             /*!< 0x00000080 */

+#define SPDIFRX_SR_SERR             SPDIFRX_SR_SERR_Msk                        /*!<Synchronization error                                 */

+#define SPDIFRX_SR_TERR_Pos         (8U)

+#define SPDIFRX_SR_TERR_Msk         (0x1UL << SPDIFRX_SR_TERR_Pos)             /*!< 0x00000100 */

+#define SPDIFRX_SR_TERR             SPDIFRX_SR_TERR_Msk                        /*!<Time-out error                                        */

+#define SPDIFRX_SR_WIDTH5_Pos       (16U)

+#define SPDIFRX_SR_WIDTH5_Msk       (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)        /*!< 0x7FFF0000 */

+#define SPDIFRX_SR_WIDTH5           SPDIFRX_SR_WIDTH5_Msk                      /*!<Duration of 5 symbols counted with spdif_clk          */

+

+/*******************  Bit definition for SPDIFRX_IFCR register  *******************/

+#define SPDIFRX_IFCR_PERRCF_Pos     (2U)

+#define SPDIFRX_IFCR_PERRCF_Msk     (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)         /*!< 0x00000004 */

+#define SPDIFRX_IFCR_PERRCF         SPDIFRX_IFCR_PERRCF_Msk                    /*!<Clears the Parity error flag                         */

+#define SPDIFRX_IFCR_OVRCF_Pos      (3U)

+#define SPDIFRX_IFCR_OVRCF_Msk      (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)          /*!< 0x00000008 */

+#define SPDIFRX_IFCR_OVRCF          SPDIFRX_IFCR_OVRCF_Msk                     /*!<Clears the Overrun error flag                        */

+#define SPDIFRX_IFCR_SBDCF_Pos      (4U)

+#define SPDIFRX_IFCR_SBDCF_Msk      (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)          /*!< 0x00000010 */

+#define SPDIFRX_IFCR_SBDCF          SPDIFRX_IFCR_SBDCF_Msk                     /*!<Clears the Synchronization Block Detected flag       */

+#define SPDIFRX_IFCR_SYNCDCF_Pos    (5U)

+#define SPDIFRX_IFCR_SYNCDCF_Msk    (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)        /*!< 0x00000020 */

+#define SPDIFRX_IFCR_SYNCDCF        SPDIFRX_IFCR_SYNCDCF_Msk                   /*!<Clears the Synchronization Done flag                 */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/

+#define SPDIFRX_DR0_DR_Pos          (0U)

+#define SPDIFRX_DR0_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)         /*!< 0x00FFFFFF */

+#define SPDIFRX_DR0_DR              SPDIFRX_DR0_DR_Msk                         /*!<Data value            */

+#define SPDIFRX_DR0_PE_Pos          (24U)

+#define SPDIFRX_DR0_PE_Msk          (0x1UL << SPDIFRX_DR0_PE_Pos)              /*!< 0x01000000 */

+#define SPDIFRX_DR0_PE              SPDIFRX_DR0_PE_Msk                         /*!<Parity Error bit      */

+#define SPDIFRX_DR0_V_Pos           (25U)

+#define SPDIFRX_DR0_V_Msk           (0x1UL << SPDIFRX_DR0_V_Pos)               /*!< 0x02000000 */

+#define SPDIFRX_DR0_V               SPDIFRX_DR0_V_Msk                          /*!<Validity bit          */

+#define SPDIFRX_DR0_U_Pos           (26U)

+#define SPDIFRX_DR0_U_Msk           (0x1UL << SPDIFRX_DR0_U_Pos)               /*!< 0x04000000 */

+#define SPDIFRX_DR0_U               SPDIFRX_DR0_U_Msk                          /*!<User bit              */

+#define SPDIFRX_DR0_C_Pos           (27U)

+#define SPDIFRX_DR0_C_Msk           (0x1UL << SPDIFRX_DR0_C_Pos)               /*!< 0x08000000 */

+#define SPDIFRX_DR0_C               SPDIFRX_DR0_C_Msk                          /*!<Channel Status bit    */

+#define SPDIFRX_DR0_PT_Pos          (28U)

+#define SPDIFRX_DR0_PT_Msk          (0x3UL << SPDIFRX_DR0_PT_Pos)              /*!< 0x30000000 */

+#define SPDIFRX_DR0_PT              SPDIFRX_DR0_PT_Msk                         /*!<Preamble Type         */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/

+#define SPDIFRX_DR1_DR_Pos          (8U)

+#define SPDIFRX_DR1_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)         /*!< 0xFFFFFF00 */

+#define SPDIFRX_DR1_DR              SPDIFRX_DR1_DR_Msk                         /*!<Data value            */

+#define SPDIFRX_DR1_PT_Pos          (4U)

+#define SPDIFRX_DR1_PT_Msk          (0x3UL << SPDIFRX_DR1_PT_Pos)              /*!< 0x00000030 */

+#define SPDIFRX_DR1_PT              SPDIFRX_DR1_PT_Msk                         /*!<Preamble Type         */

+#define SPDIFRX_DR1_C_Pos           (3U)

+#define SPDIFRX_DR1_C_Msk           (0x1UL << SPDIFRX_DR1_C_Pos)               /*!< 0x00000008 */

+#define SPDIFRX_DR1_C               SPDIFRX_DR1_C_Msk                          /*!<Channel Status bit    */

+#define SPDIFRX_DR1_U_Pos           (2U)

+#define SPDIFRX_DR1_U_Msk           (0x1UL << SPDIFRX_DR1_U_Pos)               /*!< 0x00000004 */

+#define SPDIFRX_DR1_U               SPDIFRX_DR1_U_Msk                          /*!<User bit              */

+#define SPDIFRX_DR1_V_Pos           (1U)

+#define SPDIFRX_DR1_V_Msk           (0x1UL << SPDIFRX_DR1_V_Pos)               /*!< 0x00000002 */

+#define SPDIFRX_DR1_V               SPDIFRX_DR1_V_Msk                          /*!<Validity bit          */

+#define SPDIFRX_DR1_PE_Pos          (0U)

+#define SPDIFRX_DR1_PE_Msk          (0x1UL << SPDIFRX_DR1_PE_Pos)              /*!< 0x00000001 */

+#define SPDIFRX_DR1_PE              SPDIFRX_DR1_PE_Msk                         /*!<Parity Error bit      */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/

+#define SPDIFRX_DR1_DRNL1_Pos       (16U)

+#define SPDIFRX_DR1_DRNL1_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)        /*!< 0xFFFF0000 */

+#define SPDIFRX_DR1_DRNL1           SPDIFRX_DR1_DRNL1_Msk                      /*!<Data value Channel B      */

+#define SPDIFRX_DR1_DRNL2_Pos       (0U)

+#define SPDIFRX_DR1_DRNL2_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)        /*!< 0x0000FFFF */

+#define SPDIFRX_DR1_DRNL2           SPDIFRX_DR1_DRNL2_Msk                      /*!<Data value Channel A      */

+

+/*******************  Bit definition for SPDIFRX_CSR register   *******************/

+#define SPDIFRX_CSR_USR_Pos         (0U)

+#define SPDIFRX_CSR_USR_Msk         (0xFFFFUL << SPDIFRX_CSR_USR_Pos)          /*!< 0x0000FFFF */

+#define SPDIFRX_CSR_USR             SPDIFRX_CSR_USR_Msk                        /*!<User data information           */

+#define SPDIFRX_CSR_CS_Pos          (16U)

+#define SPDIFRX_CSR_CS_Msk          (0xFFUL << SPDIFRX_CSR_CS_Pos)             /*!< 0x00FF0000 */

+#define SPDIFRX_CSR_CS              SPDIFRX_CSR_CS_Msk                         /*!<Channel A status information    */

+#define SPDIFRX_CSR_SOB_Pos         (24U)

+#define SPDIFRX_CSR_SOB_Msk         (0x1UL << SPDIFRX_CSR_SOB_Pos)             /*!< 0x01000000 */

+#define SPDIFRX_CSR_SOB             SPDIFRX_CSR_SOB_Msk                        /*!<Start Of Block                  */

+

+/*******************  Bit definition for SPDIFRX_DIR register    *******************/

+#define SPDIFRX_DIR_THI_Pos         (0U)

+#define SPDIFRX_DIR_THI_Msk         (0x1FFFUL << SPDIFRX_DIR_THI_Pos)          /*!< 0x00001FFF */

+#define SPDIFRX_DIR_THI             SPDIFRX_DIR_THI_Msk                        /*!<Threshold LOW      */

+#define SPDIFRX_DIR_TLO_Pos         (16U)

+#define SPDIFRX_DIR_TLO_Msk         (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)          /*!< 0x1FFF0000 */

+#define SPDIFRX_DIR_TLO             SPDIFRX_DIR_TLO_Msk                        /*!<Threshold HIGH     */

+

+/*******************  Bit definition for SPDIFRX_VERR register    *******************/

+#define SPDIFRX_VERR_MINREV_Pos     (0U)

+#define SPDIFRX_VERR_MINREV_Msk     (0xFUL << SPDIFRX_VERR_MINREV_Pos)         /*!< 0x0000000F */

+#define SPDIFRX_VERR_MINREV         SPDIFRX_VERR_MINREV_Msk                    /*!<SPDIFRX Minor revision     */

+#define SPDIFRX_VERR_MAJREV_Pos     (4U)

+#define SPDIFRX_VERR_MAJREV_Msk     (0xFUL << SPDIFRX_VERR_MAJREV_Pos)         /*!< 0x000000F0 */

+#define SPDIFRX_VERR_MAJREV         SPDIFRX_VERR_MAJREV_Msk                    /*!<SPDIFRX Major revision     */

+

+/*******************  Bit definition for SPDIFRX_IDR register    *******************/

+#define SPDIFRX_IDR_ID_Pos          (0U)

+#define SPDIFRX_IDR_ID_Msk          (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos)       /*!< 0xFFFFFFFF */

+#define SPDIFRX_IDR_ID              SPDIFRX_IDR_ID_Msk                         /*!<SPDIFRX identifier     */

+

+/*******************  Bit definition for SPDIFRX_SIDR register    *******************/

+#define SPDIFRX_SIDR_SID_Pos        (0U)

+#define SPDIFRX_SIDR_SID_Msk        (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos)     /*!< 0xFFFFFFFF */

+#define SPDIFRX_SIDR_SID            SPDIFRX_SIDR_SID_Msk                       /*!<Size of the memory region allocated to SPDIFRX registers */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          Serial Audio Interface                            */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  SAI VERSION  ********************************/

+#define SAI_VER_V2_X

+

+/********************  Bit definition for SAI_GCR register  *******************/

+#define SAI_GCR_SYNCIN_Pos         (0U)

+#define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000003 */

+#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */

+#define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */

+#define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */

+

+#define SAI_GCR_SYNCOUT_Pos        (4U)

+#define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000030 */

+#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */

+#define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */

+#define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */

+

+/*******************  Bit definition for SAI_xCR1 register  *******************/

+#define SAI_xCR1_MODE_Pos          (0U)

+#define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */

+#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */

+#define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */

+#define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */

+

+#define SAI_xCR1_PRTCFG_Pos        (2U)

+#define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */

+#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */

+#define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */

+#define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */

+

+#define SAI_xCR1_DS_Pos            (5U)

+#define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */

+#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */

+#define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */

+#define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */

+#define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */

+

+#define SAI_xCR1_LSBFIRST_Pos      (8U)

+#define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */

+#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */

+#define SAI_xCR1_CKSTR_Pos         (9U)

+#define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */

+#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */

+

+#define SAI_xCR1_SYNCEN_Pos        (10U)

+#define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */

+#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */

+#define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */

+#define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */

+

+#define SAI_xCR1_MONO_Pos          (12U)

+#define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */

+#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */

+#define SAI_xCR1_OUTDRIV_Pos       (13U)

+#define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */

+#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */

+#define SAI_xCR1_SAIEN_Pos         (16U)

+#define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */

+#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */

+#define SAI_xCR1_DMAEN_Pos         (17U)

+#define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */

+#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */

+#define SAI_xCR1_NODIV_Pos         (19U)

+#define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */

+#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */

+

+#define SAI_xCR1_MCKDIV_Pos        (20U)

+#define SAI_xCR1_MCKDIV_Msk        (0x3FUL << SAI_xCR1_MCKDIV_Pos)             /*!< 0x03F00000 */

+#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[5:0] (Master ClocK Divider)  */

+#define SAI_xCR1_MCKDIV_0          (0x01UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00100000 */

+#define SAI_xCR1_MCKDIV_1          (0x02UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00200000 */

+#define SAI_xCR1_MCKDIV_2          (0x04UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00400000 */

+#define SAI_xCR1_MCKDIV_3          (0x08UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00800000 */

+#define SAI_xCR1_MCKDIV_4          (0x10UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x01000000 */

+#define SAI_xCR1_MCKDIV_5          (0x20UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x02000000 */

+

+#define SAI_xCR1_MCKEN_Pos         (27U)

+#define SAI_xCR1_MCKEN_Msk         (0x1UL << SAI_xCR1_MCKEN_Pos)               /*!< 0x08000000 */

+#define SAI_xCR1_MCKEN             SAI_xCR1_MCKEN_Msk                          /*!<Master ClocK enable */

+

+#define SAI_xCR1_OSR_Pos           (26U)

+#define SAI_xCR1_OSR_Msk           (0x1UL << SAI_xCR1_OSR_Pos)                 /*!< 0x04000000 */

+#define SAI_xCR1_OSR               SAI_xCR1_OSR_Msk                            /*!<OverSampling Ratio for master clock  */

+

+/* Legacy define */

+#define  SAI_xCR1_NOMCK               SAI_xCR1_NODIV

+

+/*******************  Bit definition for SAI_xCR2 register  *******************/

+#define SAI_xCR2_FTH_Pos           (0U)

+#define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */

+#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */

+#define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */

+#define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */

+#define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */

+

+#define SAI_xCR2_FFLUSH_Pos        (3U)

+#define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */

+#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */

+#define SAI_xCR2_TRIS_Pos          (4U)

+#define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */

+#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */

+#define SAI_xCR2_MUTE_Pos          (5U)

+#define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */

+#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */

+#define SAI_xCR2_MUTEVAL_Pos       (6U)

+#define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */

+#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */

+

+#define SAI_xCR2_MUTECNT_Pos       (7U)

+#define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */

+#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */

+#define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */

+#define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */

+#define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */

+#define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */

+#define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */

+#define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */

+

+#define SAI_xCR2_CPL_Pos           (13U)

+#define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */

+#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */

+

+#define SAI_xCR2_COMP_Pos          (14U)

+#define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */

+#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */

+#define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */

+#define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */

+

+/******************  Bit definition for SAI_xFRCR register  *******************/

+#define SAI_xFRCR_FRL_Pos          (0U)

+#define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */

+#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](FRame Length)  */

+#define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */

+#define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */

+#define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */

+#define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */

+#define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */

+#define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */

+#define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */

+#define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */

+

+#define SAI_xFRCR_FSALL_Pos        (8U)

+#define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */

+#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FSALL[6:0] (Frame Synchronization Active Level Length)  */

+#define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */

+#define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */

+#define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */

+#define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */

+#define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */

+#define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */

+#define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */

+

+#define SAI_xFRCR_FSDEF_Pos        (16U)

+#define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */

+#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!<Frame Synchronization Definition  */

+#define SAI_xFRCR_FSPOL_Pos        (17U)

+#define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */

+#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */

+#define SAI_xFRCR_FSOFF_Pos        (18U)

+#define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */

+#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */

+

+/* Legacy define */

+#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL

+

+/******************  Bit definition for SAI_xSLOTR register  *******************/

+#define SAI_xSLOTR_FBOFF_Pos       (0U)

+#define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */

+#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FBOFF[4:0](First Bit Offset)  */

+#define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */

+#define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */

+#define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */

+#define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */

+#define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */

+

+#define SAI_xSLOTR_SLOTSZ_Pos      (6U)

+#define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */

+#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */

+#define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */

+#define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */

+

+#define SAI_xSLOTR_NBSLOT_Pos      (8U)

+#define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */

+#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */

+#define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */

+#define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */

+#define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */

+#define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */

+

+#define SAI_xSLOTR_SLOTEN_Pos      (16U)

+#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */

+#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */

+

+/*******************  Bit definition for SAI_xIMR register  *******************/

+#define SAI_xIMR_OVRUDRIE_Pos      (0U)

+#define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */

+#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */

+#define SAI_xIMR_MUTEDETIE_Pos     (1U)

+#define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */

+#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */

+#define SAI_xIMR_WCKCFGIE_Pos      (2U)

+#define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */

+#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */

+#define SAI_xIMR_FREQIE_Pos        (3U)

+#define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */

+#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */

+#define SAI_xIMR_CNRDYIE_Pos       (4U)

+#define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */

+#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */

+#define SAI_xIMR_AFSDETIE_Pos      (5U)

+#define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */

+#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */

+#define SAI_xIMR_LFSDETIE_Pos      (6U)

+#define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */

+#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */

+

+/********************  Bit definition for SAI_xSR register  *******************/

+#define SAI_xSR_OVRUDR_Pos         (0U)

+#define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */

+#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */

+#define SAI_xSR_MUTEDET_Pos        (1U)

+#define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */

+#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */

+#define SAI_xSR_WCKCFG_Pos         (2U)

+#define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */

+#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */

+#define SAI_xSR_FREQ_Pos           (3U)

+#define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */

+#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */

+#define SAI_xSR_CNRDY_Pos          (4U)

+#define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */

+#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */

+#define SAI_xSR_AFSDET_Pos         (5U)

+#define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */

+#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */

+#define SAI_xSR_LFSDET_Pos         (6U)

+#define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */

+#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */

+

+#define SAI_xSR_FLVL_Pos           (16U)

+#define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */

+#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */

+#define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */

+#define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */

+#define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */

+

+/******************  Bit definition for SAI_xCLRFR register  ******************/

+#define SAI_xCLRFR_COVRUDR_Pos     (0U)

+#define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */

+#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */

+#define SAI_xCLRFR_CMUTEDET_Pos    (1U)

+#define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */

+#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */

+#define SAI_xCLRFR_CWCKCFG_Pos     (2U)

+#define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */

+#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */

+#define SAI_xCLRFR_CFREQ_Pos       (3U)

+#define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */

+#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */

+#define SAI_xCLRFR_CCNRDY_Pos      (4U)

+#define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */

+#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */

+#define SAI_xCLRFR_CAFSDET_Pos     (5U)

+#define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */

+#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */

+#define SAI_xCLRFR_CLFSDET_Pos     (6U)

+#define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */

+#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */

+

+/******************  Bit definition for SAI_xDR register  *********************/

+#define SAI_xDR_DATA_Pos           (0U)

+#define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */

+#define SAI_xDR_DATA               SAI_xDR_DATA_Msk

+

+/*******************  Bit definition for SAI_PDMCR register  ******************/

+#define SAI_PDMCR_PDMEN_Pos        (0U)

+#define SAI_PDMCR_PDMEN_Msk        (0x1UL << SAI_PDMCR_PDMEN_Pos)              /*!< 0x00000001 */

+#define SAI_PDMCR_PDMEN            SAI_PDMCR_PDMEN_Msk                         /*!<PDM Enable                                          */

+

+#define SAI_PDMCR_MICNBR_Pos       (4U)

+#define SAI_PDMCR_MICNBR_Msk       (0x3UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000030 */

+#define SAI_PDMCR_MICNBR           SAI_PDMCR_MICNBR_Msk                        /*!<Number of microphones                               */

+#define SAI_PDMCR_MICNBR_0         (0x1UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000010 */

+#define SAI_PDMCR_MICNBR_1         (0x2UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000020 */

+

+#define SAI_PDMCR_CKEN1_Pos        (8U)

+#define SAI_PDMCR_CKEN1_Msk        (0x1UL << SAI_PDMCR_CKEN1_Pos)              /*!< 0x00000100 */

+#define SAI_PDMCR_CKEN1            SAI_PDMCR_CKEN1_Msk                         /*!<Clock enable of bitstream clock number 1            */

+#define SAI_PDMCR_CKEN2_Pos        (9U)

+#define SAI_PDMCR_CKEN2_Msk        (0x1UL << SAI_PDMCR_CKEN2_Pos)              /*!< 0x00000200 */

+#define SAI_PDMCR_CKEN2            SAI_PDMCR_CKEN2_Msk                         /*!<Clock enable of bitstream clock number 2            */

+#define SAI_PDMCR_CKEN3_Pos        (10U)

+#define SAI_PDMCR_CKEN3_Msk        (0x1UL << SAI_PDMCR_CKEN3_Pos)              /*!< 0x00000400 */

+#define SAI_PDMCR_CKEN3            SAI_PDMCR_CKEN3_Msk                         /*!<Clock enable of bitstream clock number 3            */

+#define SAI_PDMCR_CKEN4_Pos        (11U)

+#define SAI_PDMCR_CKEN4_Msk        (0x1UL << SAI_PDMCR_CKEN4_Pos)              /*!< 0x00000800 */

+#define SAI_PDMCR_CKEN4            SAI_PDMCR_CKEN4_Msk                         /*!<Clock enable of bitstream clock number 4            */

+

+/******************  Bit definition for SAI_PDMDLY register  ******************/

+#define SAI_PDMDLY_DLYM1L_Pos      (0U)

+#define SAI_PDMDLY_DLYM1L_Msk      (0x7UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000007 */

+#define SAI_PDMDLY_DLYM1L          SAI_PDMDLY_DLYM1L_Msk                       /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */

+#define SAI_PDMDLY_DLYM1L_0        (0x1UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000001 */

+#define SAI_PDMDLY_DLYM1L_1        (0x2UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000002 */

+#define SAI_PDMDLY_DLYM1L_2        (0x4UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000004 */

+

+#define SAI_PDMDLY_DLYM1R_Pos      (4U)

+#define SAI_PDMDLY_DLYM1R_Msk      (0x7UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000070 */

+#define SAI_PDMDLY_DLYM1R          SAI_PDMDLY_DLYM1R_Msk                       /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */

+#define SAI_PDMDLY_DLYM1R_0        (0x1UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000010 */

+#define SAI_PDMDLY_DLYM1R_1        (0x2UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000020 */

+#define SAI_PDMDLY_DLYM1R_2        (0x4UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000040 */

+

+#define SAI_PDMDLY_DLYM2L_Pos      (8U)

+#define SAI_PDMDLY_DLYM2L_Msk      (0x7UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000700 */

+#define SAI_PDMDLY_DLYM2L          SAI_PDMDLY_DLYM2L_Msk                       /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */

+#define SAI_PDMDLY_DLYM2L_0        (0x1UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000100 */

+#define SAI_PDMDLY_DLYM2L_1        (0x2UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000200 */

+#define SAI_PDMDLY_DLYM2L_2        (0x4UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000400 */

+

+#define SAI_PDMDLY_DLYM2R_Pos      (12U)

+#define SAI_PDMDLY_DLYM2R_Msk      (0x7UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00007000 */

+#define SAI_PDMDLY_DLYM2R          SAI_PDMDLY_DLYM2R_Msk                       /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/

+#define SAI_PDMDLY_DLYM2R_0        (0x1UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00001000 */

+#define SAI_PDMDLY_DLYM2R_1        (0x2UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00002000 */

+#define SAI_PDMDLY_DLYM2R_2        (0x4UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00004000 */

+

+#define SAI_PDMDLY_DLYM3L_Pos      (16U)

+#define SAI_PDMDLY_DLYM3L_Msk      (0x7UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00070000 */

+#define SAI_PDMDLY_DLYM3L          SAI_PDMDLY_DLYM3L_Msk                       /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/

+#define SAI_PDMDLY_DLYM3L_0        (0x1UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00010000 */

+#define SAI_PDMDLY_DLYM3L_1        (0x2UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00020000 */

+#define SAI_PDMDLY_DLYM3L_2        (0x4UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00040000 */

+

+#define SAI_PDMDLY_DLYM3R_Pos      (20U)

+#define SAI_PDMDLY_DLYM3R_Msk      (0x7UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00700000 */

+#define SAI_PDMDLY_DLYM3R          SAI_PDMDLY_DLYM3R_Msk                       /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/

+#define SAI_PDMDLY_DLYM3R_0        (0x1UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00100000 */

+#define SAI_PDMDLY_DLYM3R_1        (0x2UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00200000 */

+#define SAI_PDMDLY_DLYM3R_2        (0x4UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00400000 */

+

+#define SAI_PDMDLY_DLYM4L_Pos      (24U)

+#define SAI_PDMDLY_DLYM4L_Msk      (0x7UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x07000000 */

+#define SAI_PDMDLY_DLYM4L          SAI_PDMDLY_DLYM4L_Msk                       /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/

+#define SAI_PDMDLY_DLYM4L_0        (0x1UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x01000000 */

+#define SAI_PDMDLY_DLYM4L_1        (0x2UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x02000000 */

+#define SAI_PDMDLY_DLYM4L_2        (0x4UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x04000000 */

+

+#define SAI_PDMDLY_DLYM4R_Pos      (28U)

+#define SAI_PDMDLY_DLYM4R_Msk      (0x7UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x70000000 */

+#define SAI_PDMDLY_DLYM4R          SAI_PDMDLY_DLYM4R_Msk                       /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/

+#define SAI_PDMDLY_DLYM4R_0        (0x1UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x10000000 */

+#define SAI_PDMDLY_DLYM4R_1        (0x2UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x20000000 */

+#define SAI_PDMDLY_DLYM4R_2        (0x4UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x40000000 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           SDMMC Interface                                  */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for SDMMC_POWER register  ******************/

+#define SDMMC_POWER_PWRCTRL_Pos          (0U)

+#define SDMMC_POWER_PWRCTRL_Msk          (0x3UL << SDMMC_POWER_PWRCTRL_Pos)    /*!< 0x00000003 */

+#define SDMMC_POWER_PWRCTRL              SDMMC_POWER_PWRCTRL_Msk               /*!<PWRCTRL[1:0] bits (Power supply control bits) */

+#define SDMMC_POWER_PWRCTRL_0            (0x1UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000001 */

+#define SDMMC_POWER_PWRCTRL_1            (0x2UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000002 */

+#define SDMMC_POWER_VSWITCH_Pos          (2U)

+#define SDMMC_POWER_VSWITCH_Msk          (0x1UL << SDMMC_POWER_VSWITCH_Pos)    /*!< 0x00000004 */

+#define SDMMC_POWER_VSWITCH              SDMMC_POWER_VSWITCH_Msk               /*!<Voltage switch sequence start */

+#define SDMMC_POWER_VSWITCHEN_Pos        (3U)

+#define SDMMC_POWER_VSWITCHEN_Msk        (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)  /*!< 0x00000008 */

+#define SDMMC_POWER_VSWITCHEN            SDMMC_POWER_VSWITCHEN_Msk             /*!<Voltage switch procedure enable */

+#define SDMMC_POWER_DIRPOL_Pos           (4U)

+#define SDMMC_POWER_DIRPOL_Msk           (0x1UL << SDMMC_POWER_DIRPOL_Pos)     /*!< 0x00000010 */

+#define SDMMC_POWER_DIRPOL               SDMMC_POWER_DIRPOL_Msk                /*!<Data and Command direction signals polarity selection */

+

+/******************  Bit definition for SDMMC_CLKCR register  ******************/

+#define SDMMC_CLKCR_CLKDIV_Pos           (0U)

+#define SDMMC_CLKCR_CLKDIV_Msk           (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)   /*!< 0x000003FF */

+#define SDMMC_CLKCR_CLKDIV               SDMMC_CLKCR_CLKDIV_Msk                /*!<Clock divide factor             */

+#define SDMMC_CLKCR_PWRSAV_Pos           (12U)

+#define SDMMC_CLKCR_PWRSAV_Msk           (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)     /*!< 0x00001000 */

+#define SDMMC_CLKCR_PWRSAV               SDMMC_CLKCR_PWRSAV_Msk                /*!<Power saving configuration bit  */

+

+#define SDMMC_CLKCR_WIDBUS_Pos           (14U)

+#define SDMMC_CLKCR_WIDBUS_Msk           (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)     /*!< 0x0000C000 */

+#define SDMMC_CLKCR_WIDBUS               SDMMC_CLKCR_WIDBUS_Msk                /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */

+#define SDMMC_CLKCR_WIDBUS_0             (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00004000 */

+#define SDMMC_CLKCR_WIDBUS_1             (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00008000 */

+

+#define SDMMC_CLKCR_NEGEDGE_Pos          (16U)

+#define SDMMC_CLKCR_NEGEDGE_Msk          (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)    /*!< 0x00010000 */

+#define SDMMC_CLKCR_NEGEDGE              SDMMC_CLKCR_NEGEDGE_Msk               /*!<SDMMC_CK dephasing selection bit */

+#define SDMMC_CLKCR_HWFC_EN_Pos          (17U)

+#define SDMMC_CLKCR_HWFC_EN_Msk          (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)    /*!< 0x00020000 */

+#define SDMMC_CLKCR_HWFC_EN              SDMMC_CLKCR_HWFC_EN_Msk               /*!<HW Flow Control enable           */

+#define SDMMC_CLKCR_DDR_Pos              (18U)

+#define SDMMC_CLKCR_DDR_Msk              (0x1UL << SDMMC_CLKCR_DDR_Pos)        /*!< 0x00040000 */

+#define SDMMC_CLKCR_DDR                  SDMMC_CLKCR_DDR_Msk                   /*!<Data rate signaling selection    */

+#define SDMMC_CLKCR_BUSSPEED_Pos         (19U)

+#define SDMMC_CLKCR_BUSSPEED_Msk         (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)   /*!< 0x00080000 */

+#define SDMMC_CLKCR_BUSSPEED             SDMMC_CLKCR_BUSSPEED_Msk              /*!<Bus speed mode selection         */

+#define SDMMC_CLKCR_SELCLKRX_Pos         (20U)

+#define SDMMC_CLKCR_SELCLKRX_Msk         (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)   /*!< 0x00300000 */

+#define SDMMC_CLKCR_SELCLKRX             SDMMC_CLKCR_SELCLKRX_Msk              /*!<SELCLKRX[1:0] bits (Receive clock selection) */

+#define SDMMC_CLKCR_SELCLKRX_0           (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00100000 */

+#define SDMMC_CLKCR_SELCLKRX_1           (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00200000 */

+

+/*******************  Bit definition for SDMMC_ARG register  *******************/

+#define SDMMC_ARG_CMDARG_Pos             (0U)

+#define SDMMC_ARG_CMDARG_Msk             (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_ARG_CMDARG                 SDMMC_ARG_CMDARG_Msk                  /*!<Command argument */

+

+/*******************  Bit definition for SDMMC_CMD register  *******************/

+#define SDMMC_CMD_CMDINDEX_Pos           (0U)

+#define SDMMC_CMD_CMDINDEX_Msk           (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)    /*!< 0x0000003F */

+#define SDMMC_CMD_CMDINDEX               SDMMC_CMD_CMDINDEX_Msk                /*!<Command Index                               */

+#define SDMMC_CMD_CMDTRANS_Pos           (6U)

+#define SDMMC_CMD_CMDTRANS_Msk           (0x1UL << SDMMC_CMD_CMDTRANS_Pos)     /*!< 0x00000040 */

+#define SDMMC_CMD_CMDTRANS               SDMMC_CMD_CMDTRANS_Msk                /*!<CPSM Treats command as a Data Transfer      */

+#define SDMMC_CMD_CMDSTOP_Pos            (7U)

+#define SDMMC_CMD_CMDSTOP_Msk            (0x1UL << SDMMC_CMD_CMDSTOP_Pos)      /*!< 0x00000080 */

+#define SDMMC_CMD_CMDSTOP                SDMMC_CMD_CMDSTOP_Msk                 /*!<CPSM Treats command as a Stop               */

+

+#define SDMMC_CMD_WAITRESP_Pos           (8U)

+#define SDMMC_CMD_WAITRESP_Msk           (0x3UL << SDMMC_CMD_WAITRESP_Pos)     /*!< 0x00000300 */

+#define SDMMC_CMD_WAITRESP               SDMMC_CMD_WAITRESP_Msk                /*!<WAITRESP[1:0] bits (Wait for response bits) */

+#define SDMMC_CMD_WAITRESP_0             (0x1UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000100 */

+#define SDMMC_CMD_WAITRESP_1             (0x2UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000200 */

+

+#define SDMMC_CMD_WAITINT_Pos            (10U)

+#define SDMMC_CMD_WAITINT_Msk            (0x1UL << SDMMC_CMD_WAITINT_Pos)      /*!< 0x00000400 */

+#define SDMMC_CMD_WAITINT                SDMMC_CMD_WAITINT_Msk                 /*!<CPSM Waits for Interrupt Request                               */

+#define SDMMC_CMD_WAITPEND_Pos           (11U)

+#define SDMMC_CMD_WAITPEND_Msk           (0x1UL << SDMMC_CMD_WAITPEND_Pos)     /*!< 0x00000800 */

+#define SDMMC_CMD_WAITPEND               SDMMC_CMD_WAITPEND_Msk                /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */

+#define SDMMC_CMD_CPSMEN_Pos             (12U)

+#define SDMMC_CMD_CPSMEN_Msk             (0x1UL << SDMMC_CMD_CPSMEN_Pos)       /*!< 0x00001000 */

+#define SDMMC_CMD_CPSMEN                 SDMMC_CMD_CPSMEN_Msk                  /*!<Command path state machine (CPSM) Enable bit                   */

+#define SDMMC_CMD_DTHOLD_Pos             (13U)

+#define SDMMC_CMD_DTHOLD_Msk             (0x1UL << SDMMC_CMD_DTHOLD_Pos)       /*!< 0x00002000 */

+#define SDMMC_CMD_DTHOLD                 SDMMC_CMD_DTHOLD_Msk                  /*!<Hold new data block transmission and reception in the DPSM     */

+#define SDMMC_CMD_BOOTMODE_Pos           (14U)

+#define SDMMC_CMD_BOOTMODE_Msk           (0x1UL << SDMMC_CMD_BOOTMODE_Pos)     /*!< 0x00004000 */

+#define SDMMC_CMD_BOOTMODE               SDMMC_CMD_BOOTMODE_Msk                /*!<Boot mode                                                      */

+#define SDMMC_CMD_BOOTEN_Pos             (15U)

+#define SDMMC_CMD_BOOTEN_Msk             (0x1UL << SDMMC_CMD_BOOTEN_Pos)       /*!< 0x00008000 */

+#define SDMMC_CMD_BOOTEN                 SDMMC_CMD_BOOTEN_Msk                  /*!<Enable Boot mode procedure                                     */

+#define SDMMC_CMD_CMDSUSPEND_Pos         (16U)

+#define SDMMC_CMD_CMDSUSPEND_Msk         (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)   /*!< 0x00010000 */

+#define SDMMC_CMD_CMDSUSPEND             SDMMC_CMD_CMDSUSPEND_Msk              /*!<CPSM Treats command as a Suspend or Resume command             */

+

+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/

+#define SDMMC_RESPCMD_RESPCMD_Pos        (0U)

+#define SDMMC_RESPCMD_RESPCMD_Msk        (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */

+#define SDMMC_RESPCMD_RESPCMD            SDMMC_RESPCMD_RESPCMD_Msk             /*!<Response command index */

+

+/******************  Bit definition for SDMMC_RESP0 register  ******************/

+#define SDMMC_RESP0_CARDSTATUS0_Pos      (0U)

+#define SDMMC_RESP0_CARDSTATUS0_Msk      (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP0_CARDSTATUS0          SDMMC_RESP0_CARDSTATUS0_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP1 register  ******************/

+#define SDMMC_RESP1_CARDSTATUS1_Pos      (0U)

+#define SDMMC_RESP1_CARDSTATUS1_Msk      (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP1_CARDSTATUS1          SDMMC_RESP1_CARDSTATUS1_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP2 register  ******************/

+#define SDMMC_RESP2_CARDSTATUS2_Pos      (0U)

+#define SDMMC_RESP2_CARDSTATUS2_Msk      (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP2_CARDSTATUS2          SDMMC_RESP2_CARDSTATUS2_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP3 register  ******************/

+#define SDMMC_RESP3_CARDSTATUS3_Pos      (0U)

+#define SDMMC_RESP3_CARDSTATUS3_Msk      (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP3_CARDSTATUS3          SDMMC_RESP3_CARDSTATUS3_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP4 register  ******************/

+#define SDMMC_RESP4_CARDSTATUS4_Pos      (0U)

+#define SDMMC_RESP4_CARDSTATUS4_Msk      (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP4_CARDSTATUS4          SDMMC_RESP4_CARDSTATUS4_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_DTIMER register  *****************/

+#define SDMMC_DTIMER_DATATIME_Pos        (0U)

+#define SDMMC_DTIMER_DATATIME_Msk        (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_DTIMER_DATATIME            SDMMC_DTIMER_DATATIME_Msk             /*!<Data timeout period. */

+

+/******************  Bit definition for SDMMC_DLEN register  *******************/

+#define SDMMC_DLEN_DATALENGTH_Pos        (0U)

+#define SDMMC_DLEN_DATALENGTH_Msk        (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_DLEN_DATALENGTH            SDMMC_DLEN_DATALENGTH_Msk             /*!<Data length value    */

+

+/******************  Bit definition for SDMMC_DCTRL register  ******************/

+#define SDMMC_DCTRL_DTEN_Pos             (0U)

+#define SDMMC_DCTRL_DTEN_Msk             (0x1UL << SDMMC_DCTRL_DTEN_Pos)       /*!< 0x00000001 */

+#define SDMMC_DCTRL_DTEN                 SDMMC_DCTRL_DTEN_Msk                  /*!<Data transfer enabled bit                */

+#define SDMMC_DCTRL_DTDIR_Pos            (1U)

+#define SDMMC_DCTRL_DTDIR_Msk            (0x1UL << SDMMC_DCTRL_DTDIR_Pos)      /*!< 0x00000002 */

+#define SDMMC_DCTRL_DTDIR                SDMMC_DCTRL_DTDIR_Msk                 /*!<Data transfer direction selection        */

+#define SDMMC_DCTRL_DTMODE_Pos           (2U)

+#define SDMMC_DCTRL_DTMODE_Msk           (0x3UL << SDMMC_DCTRL_DTMODE_Pos)     /*!< 0x0000000C */

+#define SDMMC_DCTRL_DTMODE               SDMMC_DCTRL_DTMODE_Msk                /*!<DTMODE[1:0] Data transfer mode selection */

+#define SDMMC_DCTRL_DTMODE_0             (0x1UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000004 */

+#define SDMMC_DCTRL_DTMODE_1             (0x2UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000008 */

+

+#define SDMMC_DCTRL_DBLOCKSIZE_Pos       (4U)

+#define SDMMC_DCTRL_DBLOCKSIZE_Msk       (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */

+#define SDMMC_DCTRL_DBLOCKSIZE           SDMMC_DCTRL_DBLOCKSIZE_Msk            /*!<DBLOCKSIZE[3:0] bits (Data block size) */

+#define SDMMC_DCTRL_DBLOCKSIZE_0         (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000010 */

+#define SDMMC_DCTRL_DBLOCKSIZE_1         (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000020 */

+#define SDMMC_DCTRL_DBLOCKSIZE_2         (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000040 */

+#define SDMMC_DCTRL_DBLOCKSIZE_3         (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000080 */

+

+#define SDMMC_DCTRL_RWSTART_Pos          (8U)

+#define SDMMC_DCTRL_RWSTART_Msk          (0x1UL << SDMMC_DCTRL_RWSTART_Pos)    /*!< 0x00000100 */

+#define SDMMC_DCTRL_RWSTART              SDMMC_DCTRL_RWSTART_Msk               /*!<Read wait start                                 */

+#define SDMMC_DCTRL_RWSTOP_Pos           (9U)

+#define SDMMC_DCTRL_RWSTOP_Msk           (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)     /*!< 0x00000200 */

+#define SDMMC_DCTRL_RWSTOP               SDMMC_DCTRL_RWSTOP_Msk                /*!<Read wait stop                                  */

+#define SDMMC_DCTRL_RWMOD_Pos            (10U)

+#define SDMMC_DCTRL_RWMOD_Msk            (0x1UL << SDMMC_DCTRL_RWMOD_Pos)      /*!< 0x00000400 */

+#define SDMMC_DCTRL_RWMOD                SDMMC_DCTRL_RWMOD_Msk                 /*!<Read wait mode                                  */

+#define SDMMC_DCTRL_SDIOEN_Pos           (11U)

+#define SDMMC_DCTRL_SDIOEN_Msk           (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)     /*!< 0x00000800 */

+#define SDMMC_DCTRL_SDIOEN               SDMMC_DCTRL_SDIOEN_Msk                /*!<SD I/O enable functions                         */

+#define SDMMC_DCTRL_BOOTACKEN_Pos        (12U)

+#define SDMMC_DCTRL_BOOTACKEN_Msk        (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)  /*!< 0x00001000 */

+#define SDMMC_DCTRL_BOOTACKEN            SDMMC_DCTRL_BOOTACKEN_Msk             /*!<Enable the reception of the Boot Acknowledgment */

+#define SDMMC_DCTRL_FIFORST_Pos          (13U)

+#define SDMMC_DCTRL_FIFORST_Msk          (0x1UL << SDMMC_DCTRL_FIFORST_Pos)    /*!< 0x00002000 */

+#define SDMMC_DCTRL_FIFORST              SDMMC_DCTRL_FIFORST_Msk               /*!<FIFO reset                                      */

+

+/******************  Bit definition for SDMMC_DCOUNT register  *****************/

+#define SDMMC_DCOUNT_DATACOUNT_Pos       (0U)

+#define SDMMC_DCOUNT_DATACOUNT_Msk       (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_DCOUNT_DATACOUNT           SDMMC_DCOUNT_DATACOUNT_Msk            /*!<Data count value */

+

+/******************  Bit definition for SDMMC_STA register  ********************/

+#define SDMMC_STA_CCRCFAIL_Pos           (0U)

+#define SDMMC_STA_CCRCFAIL_Msk           (0x1UL << SDMMC_STA_CCRCFAIL_Pos)     /*!< 0x00000001 */

+#define SDMMC_STA_CCRCFAIL               SDMMC_STA_CCRCFAIL_Msk                /*!<Command response received (CRC check failed)  */

+#define SDMMC_STA_DCRCFAIL_Pos           (1U)

+#define SDMMC_STA_DCRCFAIL_Msk           (0x1UL << SDMMC_STA_DCRCFAIL_Pos)     /*!< 0x00000002 */

+#define SDMMC_STA_DCRCFAIL               SDMMC_STA_DCRCFAIL_Msk                /*!<Data block sent/received (CRC check failed)   */

+#define SDMMC_STA_CTIMEOUT_Pos           (2U)

+#define SDMMC_STA_CTIMEOUT_Msk           (0x1UL << SDMMC_STA_CTIMEOUT_Pos)     /*!< 0x00000004 */

+#define SDMMC_STA_CTIMEOUT               SDMMC_STA_CTIMEOUT_Msk                /*!<Command response timeout                      */

+#define SDMMC_STA_DTIMEOUT_Pos           (3U)

+#define SDMMC_STA_DTIMEOUT_Msk           (0x1UL << SDMMC_STA_DTIMEOUT_Pos)     /*!< 0x00000008 */

+#define SDMMC_STA_DTIMEOUT               SDMMC_STA_DTIMEOUT_Msk                /*!<Data timeout                                  */

+#define SDMMC_STA_TXUNDERR_Pos           (4U)

+#define SDMMC_STA_TXUNDERR_Msk           (0x1UL << SDMMC_STA_TXUNDERR_Pos)     /*!< 0x00000010 */

+#define SDMMC_STA_TXUNDERR               SDMMC_STA_TXUNDERR_Msk                /*!<Transmit FIFO underrun error                  */

+#define SDMMC_STA_RXOVERR_Pos            (5U)

+#define SDMMC_STA_RXOVERR_Msk            (0x1UL << SDMMC_STA_RXOVERR_Pos)      /*!< 0x00000020 */

+#define SDMMC_STA_RXOVERR                SDMMC_STA_RXOVERR_Msk                 /*!<Received FIFO overrun error                   */

+#define SDMMC_STA_CMDREND_Pos            (6U)

+#define SDMMC_STA_CMDREND_Msk            (0x1UL << SDMMC_STA_CMDREND_Pos)      /*!< 0x00000040 */

+#define SDMMC_STA_CMDREND                SDMMC_STA_CMDREND_Msk                 /*!<Command response received (CRC check passed)  */

+#define SDMMC_STA_CMDSENT_Pos            (7U)

+#define SDMMC_STA_CMDSENT_Msk            (0x1UL << SDMMC_STA_CMDSENT_Pos)      /*!< 0x00000080 */

+#define SDMMC_STA_CMDSENT                SDMMC_STA_CMDSENT_Msk                 /*!<Command sent (no response required)           */

+#define SDMMC_STA_DATAEND_Pos            (8U)

+#define SDMMC_STA_DATAEND_Msk            (0x1UL << SDMMC_STA_DATAEND_Pos)      /*!< 0x00000100 */

+#define SDMMC_STA_DATAEND                SDMMC_STA_DATAEND_Msk                 /*!<Data end (data counter, SDIDCOUNT, is zero)   */

+#define SDMMC_STA_DHOLD_Pos              (9U)

+#define SDMMC_STA_DHOLD_Msk              (0x1UL << SDMMC_STA_DHOLD_Pos)        /*!< 0x00000200 */

+#define SDMMC_STA_DHOLD                  SDMMC_STA_DHOLD_Msk                   /*!<Data transfer Hold                                                      */

+#define SDMMC_STA_DBCKEND_Pos            (10U)

+#define SDMMC_STA_DBCKEND_Msk            (0x1UL << SDMMC_STA_DBCKEND_Pos)      /*!< 0x00000400 */

+#define SDMMC_STA_DBCKEND                SDMMC_STA_DBCKEND_Msk                 /*!<Data block sent/received (CRC check passed)   */

+#define SDMMC_STA_DABORT_Pos             (11U)

+#define SDMMC_STA_DABORT_Msk             (0x1UL << SDMMC_STA_DABORT_Pos)       /*!< 0x00000800 */

+#define SDMMC_STA_DABORT                 SDMMC_STA_DABORT_Msk                  /*!<Data transfer aborted by CMD12                                          */

+#define SDMMC_STA_DPSMACT_Pos            (12U)

+#define SDMMC_STA_DPSMACT_Msk            (0x1UL << SDMMC_STA_DPSMACT_Pos)      /*!< 0x00001000 */

+#define SDMMC_STA_DPSMACT                SDMMC_STA_DPSMACT_Msk                 /*!<Data path state machine active                                       */

+#define SDMMC_STA_CPSMACT_Pos            (13U)

+#define SDMMC_STA_CPSMACT_Msk            (0x1UL << SDMMC_STA_CPSMACT_Pos)      /*!< 0x00002000 */

+#define SDMMC_STA_CPSMACT                SDMMC_STA_CPSMACT_Msk                 /*!<Command path state machine active                                          */

+#define SDMMC_STA_TXFIFOHE_Pos           (14U)

+#define SDMMC_STA_TXFIFOHE_Msk           (0x1UL << SDMMC_STA_TXFIFOHE_Pos)     /*!< 0x00004000 */

+#define SDMMC_STA_TXFIFOHE               SDMMC_STA_TXFIFOHE_Msk                /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */

+#define SDMMC_STA_RXFIFOHF_Pos           (15U)

+#define SDMMC_STA_RXFIFOHF_Msk           (0x1UL << SDMMC_STA_RXFIFOHF_Pos)     /*!< 0x00008000 */

+#define SDMMC_STA_RXFIFOHF               SDMMC_STA_RXFIFOHF_Msk                /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */

+#define SDMMC_STA_TXFIFOF_Pos            (16U)

+#define SDMMC_STA_TXFIFOF_Msk            (0x1UL << SDMMC_STA_TXFIFOF_Pos)      /*!< 0x00010000 */

+#define SDMMC_STA_TXFIFOF                SDMMC_STA_TXFIFOF_Msk                 /*!<Transmit FIFO full                            */

+#define SDMMC_STA_RXFIFOF_Pos            (17U)

+#define SDMMC_STA_RXFIFOF_Msk            (0x1UL << SDMMC_STA_RXFIFOF_Pos)      /*!< 0x00020000 */

+#define SDMMC_STA_RXFIFOF                SDMMC_STA_RXFIFOF_Msk                 /*!<Receive FIFO full                             */

+#define SDMMC_STA_TXFIFOE_Pos            (18U)

+#define SDMMC_STA_TXFIFOE_Msk            (0x1UL << SDMMC_STA_TXFIFOE_Pos)      /*!< 0x00040000 */

+#define SDMMC_STA_TXFIFOE                SDMMC_STA_TXFIFOE_Msk                 /*!<Transmit FIFO empty                           */

+#define SDMMC_STA_RXFIFOE_Pos            (19U)

+#define SDMMC_STA_RXFIFOE_Msk            (0x1UL << SDMMC_STA_RXFIFOE_Pos)      /*!< 0x00080000 */

+#define SDMMC_STA_RXFIFOE                SDMMC_STA_RXFIFOE_Msk                 /*!<Receive FIFO empty                            */

+#define SDMMC_STA_BUSYD0_Pos             (20U)

+#define SDMMC_STA_BUSYD0_Msk             (0x1UL << SDMMC_STA_BUSYD0_Pos)       /*!< 0x00100000 */

+#define SDMMC_STA_BUSYD0                 SDMMC_STA_BUSYD0_Msk                  /*!<Inverted value of SDMMC_D0 line (Busy)                                  */

+#define SDMMC_STA_BUSYD0END_Pos          (21U)

+#define SDMMC_STA_BUSYD0END_Msk          (0x1UL << SDMMC_STA_BUSYD0END_Pos)    /*!< 0x00200000 */

+#define SDMMC_STA_BUSYD0END              SDMMC_STA_BUSYD0END_Msk               /*!<End of SDMMC_D0 Busy following a CMD response detected                  */

+#define SDMMC_STA_SDIOIT_Pos             (22U)

+#define SDMMC_STA_SDIOIT_Msk             (0x1UL << SDMMC_STA_SDIOIT_Pos)       /*!< 0x00400000 */

+#define SDMMC_STA_SDIOIT                 SDMMC_STA_SDIOIT_Msk                  /*!<SDIO interrupt received                                                 */

+#define SDMMC_STA_ACKFAIL_Pos            (23U)

+#define SDMMC_STA_ACKFAIL_Msk            (0x1UL << SDMMC_STA_ACKFAIL_Pos)      /*!< 0x00800000 */

+#define SDMMC_STA_ACKFAIL                SDMMC_STA_ACKFAIL_Msk                 /*!<Boot Acknowledgment received (BootAck check fail)                       */

+#define SDMMC_STA_ACKTIMEOUT_Pos         (24U)

+#define SDMMC_STA_ACKTIMEOUT_Msk         (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)   /*!< 0x01000000 */

+#define SDMMC_STA_ACKTIMEOUT             SDMMC_STA_ACKTIMEOUT_Msk              /*!<Boot Acknowledgment timeout                                             */

+#define SDMMC_STA_VSWEND_Pos             (25U)

+#define SDMMC_STA_VSWEND_Msk             (0x1UL << SDMMC_STA_VSWEND_Pos)       /*!< 0x02000000 */

+#define SDMMC_STA_VSWEND                 SDMMC_STA_VSWEND_Msk                  /*!<Voltage switch critical timing section completion                       */

+#define SDMMC_STA_CKSTOP_Pos             (26U)

+#define SDMMC_STA_CKSTOP_Msk             (0x1UL << SDMMC_STA_CKSTOP_Pos)       /*!< 0x04000000 */

+#define SDMMC_STA_CKSTOP                 SDMMC_STA_CKSTOP_Msk                  /*!<SDMMC_CK stopped in Voltage switch procedure                            */

+#define SDMMC_STA_IDMATE_Pos             (27U)

+#define SDMMC_STA_IDMATE_Msk             (0x1UL << SDMMC_STA_IDMATE_Pos)       /*!< 0x08000000 */

+#define SDMMC_STA_IDMATE                 SDMMC_STA_IDMATE_Msk                  /*!<IDMA transfer error                                                     */

+#define SDMMC_STA_IDMABTC_Pos            (28U)

+#define SDMMC_STA_IDMABTC_Msk            (0x1UL << SDMMC_STA_IDMABTC_Pos)      /*!< 0x10000000 */

+#define SDMMC_STA_IDMABTC                SDMMC_STA_IDMABTC_Msk                 /*!<IDMA buffer transfer complete                                           */

+

+/*******************  Bit definition for SDMMC_ICR register  *******************/

+#define SDMMC_ICR_CCRCFAILC_Pos          (0U)

+#define SDMMC_ICR_CCRCFAILC_Msk          (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)    /*!< 0x00000001 */

+#define SDMMC_ICR_CCRCFAILC              SDMMC_ICR_CCRCFAILC_Msk               /*!<CCRCFAIL flag clear bit */

+#define SDMMC_ICR_DCRCFAILC_Pos          (1U)

+#define SDMMC_ICR_DCRCFAILC_Msk          (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)    /*!< 0x00000002 */

+#define SDMMC_ICR_DCRCFAILC              SDMMC_ICR_DCRCFAILC_Msk               /*!<DCRCFAIL flag clear bit */

+#define SDMMC_ICR_CTIMEOUTC_Pos          (2U)

+#define SDMMC_ICR_CTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)    /*!< 0x00000004 */

+#define SDMMC_ICR_CTIMEOUTC              SDMMC_ICR_CTIMEOUTC_Msk               /*!<CTIMEOUT flag clear bit */

+#define SDMMC_ICR_DTIMEOUTC_Pos          (3U)

+#define SDMMC_ICR_DTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)    /*!< 0x00000008 */

+#define SDMMC_ICR_DTIMEOUTC              SDMMC_ICR_DTIMEOUTC_Msk               /*!<DTIMEOUT flag clear bit */

+#define SDMMC_ICR_TXUNDERRC_Pos          (4U)

+#define SDMMC_ICR_TXUNDERRC_Msk          (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)    /*!< 0x00000010 */

+#define SDMMC_ICR_TXUNDERRC              SDMMC_ICR_TXUNDERRC_Msk               /*!<TXUNDERR flag clear bit */

+#define SDMMC_ICR_RXOVERRC_Pos           (5U)

+#define SDMMC_ICR_RXOVERRC_Msk           (0x1UL << SDMMC_ICR_RXOVERRC_Pos)     /*!< 0x00000020 */

+#define SDMMC_ICR_RXOVERRC               SDMMC_ICR_RXOVERRC_Msk                /*!<RXOVERR flag clear bit  */

+#define SDMMC_ICR_CMDRENDC_Pos           (6U)

+#define SDMMC_ICR_CMDRENDC_Msk           (0x1UL << SDMMC_ICR_CMDRENDC_Pos)     /*!< 0x00000040 */

+#define SDMMC_ICR_CMDRENDC               SDMMC_ICR_CMDRENDC_Msk                /*!<CMDREND flag clear bit  */

+#define SDMMC_ICR_CMDSENTC_Pos           (7U)

+#define SDMMC_ICR_CMDSENTC_Msk           (0x1UL << SDMMC_ICR_CMDSENTC_Pos)     /*!< 0x00000080 */

+#define SDMMC_ICR_CMDSENTC               SDMMC_ICR_CMDSENTC_Msk                /*!<CMDSENT flag clear bit  */

+#define SDMMC_ICR_DATAENDC_Pos           (8U)

+#define SDMMC_ICR_DATAENDC_Msk           (0x1UL << SDMMC_ICR_DATAENDC_Pos)     /*!< 0x00000100 */

+#define SDMMC_ICR_DATAENDC               SDMMC_ICR_DATAENDC_Msk                /*!<DATAEND flag clear bit  */

+#define SDMMC_ICR_DHOLDC_Pos             (9U)

+#define SDMMC_ICR_DHOLDC_Msk             (0x1UL << SDMMC_ICR_DHOLDC_Pos)       /*!< 0x00000200 */

+#define SDMMC_ICR_DHOLDC                 SDMMC_ICR_DHOLDC_Msk                  /*!<DHOLD flag clear bit       */

+#define SDMMC_ICR_DBCKENDC_Pos           (10U)

+#define SDMMC_ICR_DBCKENDC_Msk           (0x1UL << SDMMC_ICR_DBCKENDC_Pos)     /*!< 0x00000400 */

+#define SDMMC_ICR_DBCKENDC               SDMMC_ICR_DBCKENDC_Msk                /*!<DBCKEND flag clear bit  */

+#define SDMMC_ICR_DABORTC_Pos            (11U)

+#define SDMMC_ICR_DABORTC_Msk            (0x1UL << SDMMC_ICR_DABORTC_Pos)      /*!< 0x00000800 */

+#define SDMMC_ICR_DABORTC                SDMMC_ICR_DABORTC_Msk                 /*!<DABORTC flag clear bit     */

+#define SDMMC_ICR_BUSYD0ENDC_Pos         (21U)

+#define SDMMC_ICR_BUSYD0ENDC_Msk         (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)   /*!< 0x00200000 */

+#define SDMMC_ICR_BUSYD0ENDC             SDMMC_ICR_BUSYD0ENDC_Msk              /*!<BUSYD0ENDC flag clear bit  */

+#define SDMMC_ICR_SDIOITC_Pos            (22U)

+#define SDMMC_ICR_SDIOITC_Msk            (0x1UL << SDMMC_ICR_SDIOITC_Pos)      /*!< 0x00400000 */

+#define SDMMC_ICR_SDIOITC                SDMMC_ICR_SDIOITC_Msk                 /*!<SDIOIT flag clear bit      */

+#define SDMMC_ICR_ACKFAILC_Pos           (23U)

+#define SDMMC_ICR_ACKFAILC_Msk           (0x1UL << SDMMC_ICR_ACKFAILC_Pos)     /*!< 0x00800000 */

+#define SDMMC_ICR_ACKFAILC               SDMMC_ICR_ACKFAILC_Msk                /*!<ACKFAILC flag clear bit    */

+#define SDMMC_ICR_ACKTIMEOUTC_Pos        (24U)

+#define SDMMC_ICR_ACKTIMEOUTC_Msk        (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)  /*!< 0x01000000 */

+#define SDMMC_ICR_ACKTIMEOUTC            SDMMC_ICR_ACKTIMEOUTC_Msk             /*!<ACKTIMEOUTC flag clear bit */

+#define SDMMC_ICR_VSWENDC_Pos            (25U)

+#define SDMMC_ICR_VSWENDC_Msk            (0x1UL << SDMMC_ICR_VSWENDC_Pos)      /*!< 0x02000000 */

+#define SDMMC_ICR_VSWENDC                SDMMC_ICR_VSWENDC_Msk                 /*!<VSWENDC flag clear bit     */

+#define SDMMC_ICR_CKSTOPC_Pos            (26U)

+#define SDMMC_ICR_CKSTOPC_Msk            (0x1UL << SDMMC_ICR_CKSTOPC_Pos)      /*!< 0x04000000 */

+#define SDMMC_ICR_CKSTOPC                SDMMC_ICR_CKSTOPC_Msk                 /*!<CKSTOPC flag clear bit     */

+#define SDMMC_ICR_IDMATEC_Pos            (27U)

+#define SDMMC_ICR_IDMATEC_Msk            (0x1UL << SDMMC_ICR_IDMATEC_Pos)      /*!< 0x08000000 */

+#define SDMMC_ICR_IDMATEC                SDMMC_ICR_IDMATEC_Msk                 /*!<IDMATEC flag clear bit     */

+#define SDMMC_ICR_IDMABTCC_Pos           (28U)

+#define SDMMC_ICR_IDMABTCC_Msk           (0x1UL << SDMMC_ICR_IDMABTCC_Pos)     /*!< 0x10000000 */

+#define SDMMC_ICR_IDMABTCC               SDMMC_ICR_IDMABTCC_Msk                /*!<IDMABTCC flag clear bit    */

+

+/******************  Bit definition for SDMMC_MASK register  *******************/

+#define SDMMC_MASK_CCRCFAILIE_Pos        (0U)

+#define SDMMC_MASK_CCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)  /*!< 0x00000001 */

+#define SDMMC_MASK_CCRCFAILIE            SDMMC_MASK_CCRCFAILIE_Msk             /*!<Command CRC Fail Interrupt Enable          */

+#define SDMMC_MASK_DCRCFAILIE_Pos        (1U)

+#define SDMMC_MASK_DCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)  /*!< 0x00000002 */

+#define SDMMC_MASK_DCRCFAILIE            SDMMC_MASK_DCRCFAILIE_Msk             /*!<Data CRC Fail Interrupt Enable             */

+#define SDMMC_MASK_CTIMEOUTIE_Pos        (2U)

+#define SDMMC_MASK_CTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)  /*!< 0x00000004 */

+#define SDMMC_MASK_CTIMEOUTIE            SDMMC_MASK_CTIMEOUTIE_Msk             /*!<Command TimeOut Interrupt Enable           */

+#define SDMMC_MASK_DTIMEOUTIE_Pos        (3U)

+#define SDMMC_MASK_DTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)  /*!< 0x00000008 */

+#define SDMMC_MASK_DTIMEOUTIE            SDMMC_MASK_DTIMEOUTIE_Msk             /*!<Data TimeOut Interrupt Enable              */

+#define SDMMC_MASK_TXUNDERRIE_Pos        (4U)

+#define SDMMC_MASK_TXUNDERRIE_Msk        (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)  /*!< 0x00000010 */

+#define SDMMC_MASK_TXUNDERRIE            SDMMC_MASK_TXUNDERRIE_Msk             /*!<Tx FIFO UnderRun Error Interrupt Enable    */

+#define SDMMC_MASK_RXOVERRIE_Pos         (5U)

+#define SDMMC_MASK_RXOVERRIE_Msk         (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)   /*!< 0x00000020 */

+#define SDMMC_MASK_RXOVERRIE             SDMMC_MASK_RXOVERRIE_Msk              /*!<Rx FIFO OverRun Error Interrupt Enable     */

+#define SDMMC_MASK_CMDRENDIE_Pos         (6U)

+#define SDMMC_MASK_CMDRENDIE_Msk         (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)   /*!< 0x00000040 */

+#define SDMMC_MASK_CMDRENDIE             SDMMC_MASK_CMDRENDIE_Msk              /*!<Command Response Received Interrupt Enable */

+#define SDMMC_MASK_CMDSENTIE_Pos         (7U)

+#define SDMMC_MASK_CMDSENTIE_Msk         (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)   /*!< 0x00000080 */

+#define SDMMC_MASK_CMDSENTIE             SDMMC_MASK_CMDSENTIE_Msk              /*!<Command Sent Interrupt Enable              */

+#define SDMMC_MASK_DATAENDIE_Pos         (8U)

+#define SDMMC_MASK_DATAENDIE_Msk         (0x1UL << SDMMC_MASK_DATAENDIE_Pos)   /*!< 0x00000100 */

+#define SDMMC_MASK_DATAENDIE             SDMMC_MASK_DATAENDIE_Msk              /*!<Data End Interrupt Enable                  */

+#define SDMMC_MASK_DHOLDIE_Pos           (9U)

+#define SDMMC_MASK_DHOLDIE_Msk           (0x1UL << SDMMC_MASK_DHOLDIE_Pos)     /*!< 0x00000200 */

+#define SDMMC_MASK_DHOLDIE               SDMMC_MASK_DHOLDIE_Msk                /*!<Data Hold Interrupt Enable                 */

+#define SDMMC_MASK_DBCKENDIE_Pos         (10U)

+#define SDMMC_MASK_DBCKENDIE_Msk         (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)   /*!< 0x00000400 */

+#define SDMMC_MASK_DBCKENDIE             SDMMC_MASK_DBCKENDIE_Msk              /*!<Data Block End Interrupt Enable            */

+#define SDMMC_MASK_DABORTIE_Pos          (11U)

+#define SDMMC_MASK_DABORTIE_Msk          (0x1UL << SDMMC_MASK_DABORTIE_Pos)    /*!< 0x00000800 */

+#define SDMMC_MASK_DABORTIE              SDMMC_MASK_DABORTIE_Msk               /*!<Data transfer aborted interrupt enable     */

+

+#define SDMMC_MASK_TXFIFOHEIE_Pos        (14U)

+#define SDMMC_MASK_TXFIFOHEIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)  /*!< 0x00004000 */

+#define SDMMC_MASK_TXFIFOHEIE            SDMMC_MASK_TXFIFOHEIE_Msk             /*!<Tx FIFO Half Empty interrupt Enable        */

+#define SDMMC_MASK_RXFIFOHFIE_Pos        (15U)

+#define SDMMC_MASK_RXFIFOHFIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)  /*!< 0x00008000 */

+#define SDMMC_MASK_RXFIFOHFIE            SDMMC_MASK_RXFIFOHFIE_Msk             /*!<Rx FIFO Half Full interrupt Enable         */

+

+#define SDMMC_MASK_RXFIFOFIE_Pos         (17U)

+#define SDMMC_MASK_RXFIFOFIE_Msk         (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)   /*!< 0x00020000 */

+#define SDMMC_MASK_RXFIFOFIE             SDMMC_MASK_RXFIFOFIE_Msk              /*!<Rx FIFO Full interrupt Enable              */

+#define SDMMC_MASK_TXFIFOEIE_Pos         (18U)

+#define SDMMC_MASK_TXFIFOEIE_Msk         (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)   /*!< 0x00040000 */

+#define SDMMC_MASK_TXFIFOEIE             SDMMC_MASK_TXFIFOEIE_Msk              /*!<Tx FIFO Empty interrupt Enable             */

+

+#define SDMMC_MASK_BUSYD0ENDIE_Pos       (21U)

+#define SDMMC_MASK_BUSYD0ENDIE_Msk       (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */

+#define SDMMC_MASK_BUSYD0ENDIE           SDMMC_MASK_BUSYD0ENDIE_Msk            /*!<BUSYD0ENDIE interrupt Enable */

+#define SDMMC_MASK_SDIOITIE_Pos           (22U)

+#define SDMMC_MASK_SDIOITIE_Msk           (0x1UL << SDMMC_MASK_SDIOITIE_Pos)     /*!< 0x00400000 */

+#define SDMMC_MASK_SDIOITIE               SDMMC_MASK_SDIOITIE_Msk                /*!<SDMMC Mode Interrupt Received interrupt Enable */

+#define SDMMC_MASK_ACKFAILIE_Pos         (23U)

+#define SDMMC_MASK_ACKFAILIE_Msk         (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)   /*!< 0x00800000 */

+#define SDMMC_MASK_ACKFAILIE             SDMMC_MASK_ACKFAILIE_Msk              /*!<Acknowledgment Fail Interrupt Enable */

+#define SDMMC_MASK_ACKTIMEOUTIE_Pos      (24U)

+#define SDMMC_MASK_ACKTIMEOUTIE_Msk      (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */

+#define SDMMC_MASK_ACKTIMEOUTIE          SDMMC_MASK_ACKTIMEOUTIE_Msk           /*!<Acknowledgment timeout Interrupt Enable */

+#define SDMMC_MASK_VSWENDIE_Pos          (25U)

+#define SDMMC_MASK_VSWENDIE_Msk          (0x1UL << SDMMC_MASK_VSWENDIE_Pos)    /*!< 0x02000000 */

+#define SDMMC_MASK_VSWENDIE              SDMMC_MASK_VSWENDIE_Msk               /*!<Voltage switch critical timing section completion Interrupt Enable */

+#define SDMMC_MASK_CKSTOPIE_Pos          (26U)

+#define SDMMC_MASK_CKSTOPIE_Msk          (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)    /*!< 0x04000000 */

+#define SDMMC_MASK_CKSTOPIE              SDMMC_MASK_CKSTOPIE_Msk               /*!<Voltage Switch clock stopped Interrupt Enable */

+#define SDMMC_MASK_IDMABTCIE_Pos         (28U)

+#define SDMMC_MASK_IDMABTCIE_Msk         (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)   /*!< 0x10000000 */

+#define SDMMC_MASK_IDMABTCIE             SDMMC_MASK_IDMABTCIE_Msk              /*!<IDMA buffer transfer complete Interrupt Enable */

+

+/*****************  Bit definition for SDMMC_ACKTIME register  *****************/

+#define SDMMC_ACKTIME_ACKTIME_Pos        (0U)

+#define SDMMC_ACKTIME_ACKTIME_Msk        (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_ACKTIME_ACKTIME            SDMMC_ACKTIME_ACKTIME_Msk             /*!<Boot acknowledgment timeout period */

+

+/******************  Bit definition for SDMMC_FIFO register  *******************/

+#define SDMMC_FIFO_FIFODATA_Pos          (0U)

+#define SDMMC_FIFO_FIFODATA_Msk          (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_FIFO_FIFODATA              SDMMC_FIFO_FIFODATA_Msk               /*!<Receive and transmit FIFO data */

+

+/******************  Bit definition for SDMMC_IDMACTRL register ****************/

+#define SDMMC_IDMA_IDMAEN_Pos            (0U)

+#define SDMMC_IDMA_IDMAEN_Msk            (0x1UL << SDMMC_IDMA_IDMAEN_Pos)      /*!< 0x00000001 */

+#define SDMMC_IDMA_IDMAEN                SDMMC_IDMA_IDMAEN_Msk                 /*!< Enable the internal DMA of the SDMMC peripheral */

+#define SDMMC_IDMA_IDMABMODE_Pos         (1U)

+#define SDMMC_IDMA_IDMABMODE_Msk         (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)   /*!< 0x00000002 */

+#define SDMMC_IDMA_IDMABMODE             SDMMC_IDMA_IDMABMODE_Msk              /*!< Enable double buffer mode for IDMA */

+#define SDMMC_IDMA_IDMABACT_Pos          (2U)

+#define SDMMC_IDMA_IDMABACT_Msk          (0x1UL << SDMMC_IDMA_IDMABACT_Pos)    /*!< 0x00000004 */

+#define SDMMC_IDMA_IDMABACT              SDMMC_IDMA_IDMABACT_Msk               /*!< Uses buffer 1 when double buffer mode is selected */

+

+/*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/

+#define SDMMC_IDMABSIZE_IDMABNDT_Pos     (5U)

+#define SDMMC_IDMABSIZE_IDMABNDT_Msk     (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */

+#define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */

+

+/*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/

+#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */

+

+/*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/

+#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                        Delay Block Interface (DLYB)                        */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for DLYB_CR register  ********************/

+#define DLYB_CR_DEN_Pos         (0U)

+#define DLYB_CR_DEN_Msk         (0x1UL << DLYB_CR_DEN_Pos)                     /*!< 0x00000001 */

+#define DLYB_CR_DEN             DLYB_CR_DEN_Msk                                /*!<Delay Block enable */

+#define DLYB_CR_SEN_Pos         (1U)

+#define DLYB_CR_SEN_Msk         (0x1UL << DLYB_CR_SEN_Pos)                     /*!< 0x00000002 */

+#define DLYB_CR_SEN             DLYB_CR_SEN_Msk                                /*!<Sampler length enable */

+

+

+/*******************  Bit definition for DLYB_CFGR register  ********************/

+#define DLYB_CFGR_SEL_Pos       (0U)

+#define DLYB_CFGR_SEL_Msk       (0xFUL << DLYB_CFGR_SEL_Pos)                   /*!< 0x0000000F */

+#define DLYB_CFGR_SEL           DLYB_CFGR_SEL_Msk                              /*!<Select the phase for the Output clock[3:0] */

+#define DLYB_CFGR_SEL_0         (0x1UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000001 */

+#define DLYB_CFGR_SEL_1         (0x2UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000002 */

+#define DLYB_CFGR_SEL_2         (0x3UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000003 */

+#define DLYB_CFGR_SEL_3         (0x8UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000008 */

+

+#define DLYB_CFGR_UNIT_Pos      (8U)

+#define DLYB_CFGR_UNIT_Msk      (0x7FUL << DLYB_CFGR_UNIT_Pos)                 /*!< 0x00007F00 */

+#define DLYB_CFGR_UNIT          DLYB_CFGR_UNIT_Msk                             /*!<Delay Defines the delay of a Unit delay cell[6:0] */

+#define DLYB_CFGR_UNIT_0        (0x01UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000100 */

+#define DLYB_CFGR_UNIT_1        (0x02UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000200 */

+#define DLYB_CFGR_UNIT_2        (0x04UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000400 */

+#define DLYB_CFGR_UNIT_3        (0x08UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000800 */

+#define DLYB_CFGR_UNIT_4        (0x10UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00001000 */

+#define DLYB_CFGR_UNIT_5        (0x20UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00002000 */

+#define DLYB_CFGR_UNIT_6        (0x40UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00004000 */

+

+#define DLYB_CFGR_LNG_Pos       (16U)

+#define DLYB_CFGR_LNG_Msk       (0xFFFUL << DLYB_CFGR_LNG_Pos)                 /*!< 0x0FFF0000 */

+#define DLYB_CFGR_LNG           DLYB_CFGR_LNG_Msk                              /*!<Delay line length value[11:0] */

+#define DLYB_CFGR_LNG_0         (0x001UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00010000 */

+#define DLYB_CFGR_LNG_1         (0x002UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00020000 */

+#define DLYB_CFGR_LNG_2         (0x004UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00040000 */

+#define DLYB_CFGR_LNG_3         (0x008UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00080000 */

+#define DLYB_CFGR_LNG_4         (0x010UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00100000 */

+#define DLYB_CFGR_LNG_5         (0x020UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00200000 */

+#define DLYB_CFGR_LNG_6         (0x040UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00400000 */

+#define DLYB_CFGR_LNG_7         (0x080UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00800000 */

+#define DLYB_CFGR_LNG_8         (0x100UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x01000000 */

+#define DLYB_CFGR_LNG_9         (0x200UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x02000000 */

+#define DLYB_CFGR_LNG_10        (0x400UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x04000000 */

+#define DLYB_CFGR_LNG_11        (0x800UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x08000000 */

+

+#define DLYB_CFGR_LNGF_Pos      (31U)

+#define DLYB_CFGR_LNGF_Msk      (0x1UL << DLYB_CFGR_LNGF_Pos)                  /*!< 0x80000000 */

+#define DLYB_CFGR_LNGF          DLYB_CFGR_LNGF_Msk                             /*!<Length valid flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                   Serial Peripheral Interface (SPI/I2S)                    */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for SPI_CR1 register  ********************/

+#define SPI_CR1_SPE_Pos             (0U)

+#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000001 */

+#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<Serial Peripheral Enable                         */

+#define SPI_CR1_MASRX_Pos           (8U)

+#define SPI_CR1_MASRX_Msk           (0x1UL << SPI_CR1_MASRX_Pos)               /*!< 0x00000100 */

+#define SPI_CR1_MASRX               SPI_CR1_MASRX_Msk                          /*!<Master automatic SUSP in Receive mode            */

+#define SPI_CR1_CSTART_Pos          (9U)

+#define SPI_CR1_CSTART_Msk          (0x1UL << SPI_CR1_CSTART_Pos)              /*!< 0x00000200 */

+#define SPI_CR1_CSTART              SPI_CR1_CSTART_Msk                         /*!<Master transfer start                            */

+#define SPI_CR1_CSUSP_Pos           (10U)

+#define SPI_CR1_CSUSP_Msk           (0x1UL << SPI_CR1_CSUSP_Pos)               /*!< 0x00000400 */

+#define SPI_CR1_CSUSP               SPI_CR1_CSUSP_Msk                          /*!<Master SUSPend request                           */

+#define SPI_CR1_HDDIR_Pos           (11U)

+#define SPI_CR1_HDDIR_Msk           (0x1UL << SPI_CR1_HDDIR_Pos)               /*!< 0x00000800 */

+#define SPI_CR1_HDDIR               SPI_CR1_HDDIR_Msk                          /*!<Rx/Tx direction at Half-duplex mode              */

+#define SPI_CR1_SSI_Pos             (12U)

+#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00001000 */

+#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal SS signal input level                   */

+#define SPI_CR1_CRC33_17_Pos        (13U)

+#define SPI_CR1_CRC33_17_Msk        (0x1UL << SPI_CR1_CRC33_17_Pos)            /*!< 0x00002000 */

+#define SPI_CR1_CRC33_17             SPI_CR1_CRC33_17_Msk                      /*!<32-bit CRC polynomial configuration              */

+#define SPI_CR1_RCRCINI_Pos         (14U)

+#define SPI_CR1_RCRCINI_Msk         (0x1UL << SPI_CR1_RCRCINI_Pos)             /*!< 0x00004000 */

+#define SPI_CR1_RCRCINI             SPI_CR1_RCRCINI_Msk                        /*!<CRC init pattern control for receiver            */

+#define SPI_CR1_TCRCINI_Pos         (15U)

+#define SPI_CR1_TCRCINI_Msk         (0x1UL << SPI_CR1_TCRCINI_Pos)             /*!< 0x00008000 */

+#define SPI_CR1_TCRCINI             SPI_CR1_TCRCINI_Msk                        /*!<CRC init pattern control for transmitter         */

+#define SPI_CR1_IOLOCK_Pos          (16U)

+#define SPI_CR1_IOLOCK_Msk          (0x1UL << SPI_CR1_IOLOCK_Pos)              /*!< 0x00010000 */

+#define SPI_CR1_IOLOCK              SPI_CR1_IOLOCK_Msk                         /*!<Locking the AF configuration of associated IOs   */

+

+/*******************  Bit definition for SPI_CR2 register  ********************/

+#define SPI_CR2_TSER_Pos            (16U)

+#define SPI_CR2_TSER_Msk            (0xFFFFUL << SPI_CR2_TSER_Pos)             /*!< 0xFFFF0000 */

+#define SPI_CR2_TSER                SPI_CR2_TSER_Msk                           /*!<Number of data transfer extension                */

+#define SPI_CR2_TSIZE_Pos           (0U)

+#define SPI_CR2_TSIZE_Msk           (0xFFFFUL << SPI_CR2_TSIZE_Pos)            /*!< 0x0000FFFF */

+#define SPI_CR2_TSIZE               SPI_CR2_TSIZE_Msk                          /*!<Number of data at current transfer               */

+

+/*******************  Bit definition for SPI_CFG1 register  ********************/

+#define SPI_CFG1_DSIZE_Pos          (0U)

+#define SPI_CFG1_DSIZE_Msk          (0x1FUL << SPI_CFG1_DSIZE_Pos)             /*!< 0x0000001F */

+#define SPI_CFG1_DSIZE              SPI_CFG1_DSIZE_Msk                         /*!<DSIZE[4:0]: Bits number in single SPI data frame */

+#define SPI_CFG1_DSIZE_0            (0x01UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000001 */

+#define SPI_CFG1_DSIZE_1            (0x02UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000002 */

+#define SPI_CFG1_DSIZE_2            (0x04UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000004 */

+#define SPI_CFG1_DSIZE_3            (0x08UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000008 */

+#define SPI_CFG1_DSIZE_4            (0x10UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000010 */

+

+#define SPI_CFG1_FTHLV_Pos          (5U)

+#define SPI_CFG1_FTHLV_Msk          (0xFUL << SPI_CFG1_FTHLV_Pos)              /*!< 0x000001E0 */

+#define SPI_CFG1_FTHLV              SPI_CFG1_FTHLV_Msk                         /*!<FTHVL [3:0]: FIFO threshold level*/

+#define SPI_CFG1_FTHLV_0            (0x1UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000020 */

+#define SPI_CFG1_FTHLV_1            (0x2UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000040 */

+#define SPI_CFG1_FTHLV_2            (0x4UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000080 */

+#define SPI_CFG1_FTHLV_3            (0x8UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000100 */

+

+#define SPI_CFG1_UDRCFG_Pos         (9U)

+#define SPI_CFG1_UDRCFG_Msk         (0x3UL << SPI_CFG1_UDRCFG_Pos)             /*!< 0x00000600 */

+#define SPI_CFG1_UDRCFG             SPI_CFG1_UDRCFG_Msk                        /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */

+#define SPI_CFG1_UDRCFG_0           (0x1UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000200 */

+#define SPI_CFG1_UDRCFG_1           (0x2UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000400 */

+

+

+#define SPI_CFG1_UDRDET_Pos         (11U)

+#define SPI_CFG1_UDRDET_Msk         (0x3UL << SPI_CFG1_UDRDET_Pos)             /*!< 0x00001800 */

+#define SPI_CFG1_UDRDET             SPI_CFG1_UDRDET_Msk                        /*!<UDRDET[1:0]: Detection of underrun condition     */

+#define SPI_CFG1_UDRDET_0           (0x1UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00000800 */

+#define SPI_CFG1_UDRDET_1           (0x2UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00001000 */

+

+#define SPI_CFG1_RXDMAEN_Pos        (14U)

+#define SPI_CFG1_RXDMAEN_Msk        (0x1UL << SPI_CFG1_RXDMAEN_Pos)            /*!< 0x00004000 */

+#define SPI_CFG1_RXDMAEN            SPI_CFG1_RXDMAEN_Msk                       /*!<Rx DMA stream enable                */

+#define SPI_CFG1_TXDMAEN_Pos        (15U)

+#define SPI_CFG1_TXDMAEN_Msk        (0x1UL << SPI_CFG1_TXDMAEN_Pos)            /*!< 0x00008000 */

+#define SPI_CFG1_TXDMAEN            SPI_CFG1_TXDMAEN_Msk                       /*!<Tx DMA stream enable                */

+

+#define SPI_CFG1_CRCSIZE_Pos        (16U)

+#define SPI_CFG1_CRCSIZE_Msk        (0x1FUL << SPI_CFG1_CRCSIZE_Pos)           /*!< 0x001F0000 */

+#define SPI_CFG1_CRCSIZE            SPI_CFG1_CRCSIZE_Msk                       /*!<CRCSIZE [4:0]: Length of CRC frame*/

+#define SPI_CFG1_CRCSIZE_0          (0x01UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00010000 */

+#define SPI_CFG1_CRCSIZE_1          (0x02UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00020000 */

+#define SPI_CFG1_CRCSIZE_2          (0x04UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00040000 */

+#define SPI_CFG1_CRCSIZE_3          (0x08UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00080000 */

+#define SPI_CFG1_CRCSIZE_4          (0x10UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00100000 */

+

+#define SPI_CFG1_CRCEN_Pos          (22U)

+#define SPI_CFG1_CRCEN_Msk          (0x1UL << SPI_CFG1_CRCEN_Pos)              /*!< 0x00400000 */

+#define SPI_CFG1_CRCEN              SPI_CFG1_CRCEN_Msk                         /*!<Hardware CRC computation enable */

+

+#define SPI_CFG1_MBR_Pos            (28U)

+#define SPI_CFG1_MBR_Msk            (0x7UL << SPI_CFG1_MBR_Pos)                /*!< 0x70000000 */

+#define SPI_CFG1_MBR                SPI_CFG1_MBR_Msk                           /*!<Master baud rate                */

+#define SPI_CFG1_MBR_0              (0x1UL << SPI_CFG1_MBR_Pos)                 /*!< 0x10000000 */

+#define SPI_CFG1_MBR_1              (0x2UL << SPI_CFG1_MBR_Pos)                 /*!< 0x20000000 */

+#define SPI_CFG1_MBR_2              (0x4UL << SPI_CFG1_MBR_Pos)                 /*!< 0x40000000 */

+

+/*******************  Bit definition for SPI_CFG2 register  ********************/

+#define SPI_CFG2_MSSI_Pos           (0U)

+#define SPI_CFG2_MSSI_Msk           (0xFUL << SPI_CFG2_MSSI_Pos)               /*!< 0x0000000F */

+#define SPI_CFG2_MSSI               SPI_CFG2_MSSI_Msk                          /*!<Master SS Idleness */

+#define SPI_CFG2_MSSI_0             (0x1UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000001 */

+#define SPI_CFG2_MSSI_1             (0x2UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000002 */

+#define SPI_CFG2_MSSI_2             (0x4UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000004 */

+#define SPI_CFG2_MSSI_3             (0x8UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000008 */

+

+#define SPI_CFG2_MIDI_Pos           (4U)

+#define SPI_CFG2_MIDI_Msk           (0xFUL << SPI_CFG2_MIDI_Pos)               /*!< 0x000000F0 */

+#define SPI_CFG2_MIDI               SPI_CFG2_MIDI_Msk                          /*!<Master Inter-Data Idleness */

+#define SPI_CFG2_MIDI_0             (0x1UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000010 */

+#define SPI_CFG2_MIDI_1             (0x2UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000020 */

+#define SPI_CFG2_MIDI_2             (0x4UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000040 */

+#define SPI_CFG2_MIDI_3             (0x8UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000080 */

+

+#define SPI_CFG2_IOSWP_Pos          (15U)

+#define SPI_CFG2_IOSWP_Msk          (0x1UL << SPI_CFG2_IOSWP_Pos)              /*!< 0x00008000 */

+#define SPI_CFG2_IOSWP              SPI_CFG2_IOSWP_Msk                         /*!<Swap functionality of MISO and MOSI pins */

+

+#define SPI_CFG2_COMM_Pos           (17U)

+#define SPI_CFG2_COMM_Msk           (0x3UL << SPI_CFG2_COMM_Pos)               /*!< 0x00060000 */

+#define SPI_CFG2_COMM               SPI_CFG2_COMM_Msk                          /*!<COMM [1:0]: SPI Communication Mode*/

+#define SPI_CFG2_COMM_0             (0x1UL << SPI_CFG2_COMM_Pos)                /*!< 0x00020000 */

+#define SPI_CFG2_COMM_1             (0x2UL << SPI_CFG2_COMM_Pos)                /*!< 0x00040000 */

+

+#define SPI_CFG2_SP_Pos             (19U)

+#define SPI_CFG2_SP_Msk             (0x7UL << SPI_CFG2_SP_Pos)                 /*!< 0x00380000 */

+#define SPI_CFG2_SP                 SPI_CFG2_SP_Msk                            /*!<SP[2:0]: Serial Protocol */

+#define SPI_CFG2_SP_0               (0x1UL << SPI_CFG2_SP_Pos)                  /*!< 0x00080000 */

+#define SPI_CFG2_SP_1               (0x2UL << SPI_CFG2_SP_Pos)                  /*!< 0x00100000 */

+#define SPI_CFG2_SP_2               (0x4UL << SPI_CFG2_SP_Pos)                  /*!< 0x00200000 */

+

+#define SPI_CFG2_MASTER_Pos         (22U)

+#define SPI_CFG2_MASTER_Msk         (0x1UL << SPI_CFG2_MASTER_Pos)             /*!< 0x00400000 */

+#define SPI_CFG2_MASTER             SPI_CFG2_MASTER_Msk                        /*!<SPI Master           */

+#define SPI_CFG2_LSBFRST_Pos        (23U)

+#define SPI_CFG2_LSBFRST_Msk        (0x1UL << SPI_CFG2_LSBFRST_Pos)            /*!< 0x00800000 */

+#define SPI_CFG2_LSBFRST            SPI_CFG2_LSBFRST_Msk                       /*!<Data frame format               */

+#define SPI_CFG2_CPHA_Pos           (24U)

+#define SPI_CFG2_CPHA_Msk           (0x1UL << SPI_CFG2_CPHA_Pos)               /*!< 0x01000000 */

+#define SPI_CFG2_CPHA               SPI_CFG2_CPHA_Msk                          /*!<Clock Phase      */

+#define SPI_CFG2_CPOL_Pos           (25U)

+#define SPI_CFG2_CPOL_Msk           (0x1UL << SPI_CFG2_CPOL_Pos)               /*!< 0x02000000 */

+#define SPI_CFG2_CPOL               SPI_CFG2_CPOL_Msk                          /*!<Clock Polarity   */

+#define SPI_CFG2_SSM_Pos            (26U)

+#define SPI_CFG2_SSM_Msk            (0x1UL << SPI_CFG2_SSM_Pos)                /*!< 0x04000000 */

+#define SPI_CFG2_SSM                SPI_CFG2_SSM_Msk                           /*!<Software slave management */

+

+#define SPI_CFG2_SSIOP_Pos          (28U)

+#define SPI_CFG2_SSIOP_Msk          (0x1UL << SPI_CFG2_SSIOP_Pos)              /*!< 0x10000000 */

+#define SPI_CFG2_SSIOP              SPI_CFG2_SSIOP_Msk                         /*!<SS input/output polarity */

+#define SPI_CFG2_SSOE_Pos           (29U)

+#define SPI_CFG2_SSOE_Msk           (0x1UL << SPI_CFG2_SSOE_Pos)               /*!< 0x20000000 */

+#define SPI_CFG2_SSOE               SPI_CFG2_SSOE_Msk                          /*!<SS output enable */

+#define SPI_CFG2_SSOM_Pos           (30U)

+#define SPI_CFG2_SSOM_Msk           (0x1UL << SPI_CFG2_SSOM_Pos)               /*!< 0x40000000 */

+#define SPI_CFG2_SSOM               SPI_CFG2_SSOM_Msk                          /*!<SS output management in master mode */

+

+#define SPI_CFG2_AFCNTR_Pos         (31U)

+#define SPI_CFG2_AFCNTR_Msk         (0x1UL << SPI_CFG2_AFCNTR_Pos)             /*!< 0x80000000 */

+#define SPI_CFG2_AFCNTR             SPI_CFG2_AFCNTR_Msk                        /*!<Alternate function GPIOs control */

+

+/*******************  Bit definition for SPI_IER register  ********************/

+#define SPI_IER_RXPIE_Pos           (0U)

+#define SPI_IER_RXPIE_Msk           (0x1UL << SPI_IER_RXPIE_Pos)               /*!< 0x00000001 */

+#define SPI_IER_RXPIE               SPI_IER_RXPIE_Msk                          /*!<RXP Interrupt Enable            */

+#define SPI_IER_TXPIE_Pos           (1U)

+#define SPI_IER_TXPIE_Msk           (0x1UL << SPI_IER_TXPIE_Pos)               /*!< 0x00000002 */

+#define SPI_IER_TXPIE               SPI_IER_TXPIE_Msk                          /*!<TXP interrupt enable            */

+#define SPI_IER_DXPIE_Pos           (2U)

+#define SPI_IER_DXPIE_Msk           (0x1UL << SPI_IER_DXPIE_Pos)               /*!< 0x00000004 */

+#define SPI_IER_DXPIE               SPI_IER_DXPIE_Msk                          /*!<DXP interrupt enable            */

+#define SPI_IER_EOTIE_Pos           (3U)

+#define SPI_IER_EOTIE_Msk           (0x1UL << SPI_IER_EOTIE_Pos)               /*!< 0x00000008 */

+#define SPI_IER_EOTIE               SPI_IER_EOTIE_Msk                          /*!<EOT/SUSP/TXC interrupt enable   */

+#define SPI_IER_TXTFIE_Pos          (4U)

+#define SPI_IER_TXTFIE_Msk          (0x1UL << SPI_IER_TXTFIE_Pos)              /*!< 0x00000010 */

+#define SPI_IER_TXTFIE              SPI_IER_TXTFIE_Msk                         /*!<TXTF interrupt enable           */

+#define SPI_IER_UDRIE_Pos           (5U)

+#define SPI_IER_UDRIE_Msk           (0x1UL << SPI_IER_UDRIE_Pos)               /*!< 0x00000020 */

+#define SPI_IER_UDRIE               SPI_IER_UDRIE_Msk                          /*!<UDR interrupt enable            */

+#define SPI_IER_OVRIE_Pos           (6U)

+#define SPI_IER_OVRIE_Msk           (0x1UL << SPI_IER_OVRIE_Pos)               /*!< 0x00000040 */

+#define SPI_IER_OVRIE               SPI_IER_OVRIE_Msk                          /*!<OVR interrupt enable            */

+#define SPI_IER_CRCEIE_Pos          (7U)

+#define SPI_IER_CRCEIE_Msk          (0x1UL << SPI_IER_CRCEIE_Pos)               /*!< 0x00000080 */

+#define SPI_IER_CRCEIE              SPI_IER_CRCEIE_Msk                          /*!<CRCE interrupt enable           */

+#define SPI_IER_TIFREIE_Pos         (8U)

+#define SPI_IER_TIFREIE_Msk         (0x1UL << SPI_IER_TIFREIE_Pos)             /*!< 0x00000100 */

+#define SPI_IER_TIFREIE             SPI_IER_TIFREIE_Msk                        /*!<TI Frame Error interrupt enable */

+#define SPI_IER_MODFIE_Pos          (9U)

+#define SPI_IER_MODFIE_Msk          (0x1UL << SPI_IER_MODFIE_Pos)              /*!< 0x00000200 */

+#define SPI_IER_MODFIE              SPI_IER_MODFIE_Msk                         /*!<MODF interrupt enable           */

+#define SPI_IER_TSERFIE_Pos         (10U)

+#define SPI_IER_TSERFIE_Msk         (0x1UL << SPI_IER_TSERFIE_Pos)              /*!< 0x00000400 */

+#define SPI_IER_TSERFIE             SPI_IER_TSERFIE_Msk                        /*!<TSERF interrupt enable          */

+

+/*******************  Bit definition for SPI_SR register  ********************/

+#define SPI_SR_RXP_Pos              (0U)

+#define SPI_SR_RXP_Msk              (0x1UL << SPI_SR_RXP_Pos)                  /*!< 0x00000001 */

+#define SPI_SR_RXP                  SPI_SR_RXP_Msk                             /*!<Rx-Packet available             */

+#define SPI_SR_TXP_Pos              (1U)

+#define SPI_SR_TXP_Msk              (0x1UL << SPI_SR_TXP_Pos)                  /*!< 0x00000002 */

+#define SPI_SR_TXP                  SPI_SR_TXP_Msk                             /*!<Tx-Packet space available       */

+#define SPI_SR_DXP_Pos              (2U)

+#define SPI_SR_DXP_Msk              (0x1UL << SPI_SR_DXP_Pos)                  /*!< 0x00000004 */

+#define SPI_SR_DXP                  SPI_SR_DXP_Msk                             /*!<Duplex Packet available         */

+#define SPI_SR_EOT_Pos              (3U)

+#define SPI_SR_EOT_Msk              (0x1UL << SPI_SR_EOT_Pos)                  /*!< 0x00000008 */

+#define SPI_SR_EOT                  SPI_SR_EOT_Msk                             /*!<Duplex Packet available         */

+#define SPI_SR_TXTF_Pos             (4U)

+#define SPI_SR_TXTF_Msk             (0x1UL << SPI_SR_TXTF_Pos)                 /*!< 0x00000010 */

+#define SPI_SR_TXTF                 SPI_SR_TXTF_Msk                            /*!<Transmission Transfer Filled    */

+#define SPI_SR_UDR_Pos              (5U)

+#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000020 */

+#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<UDR at Slave transmission       */

+#define SPI_SR_OVR_Pos              (6U)

+#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */

+#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Rx-Packet available             */

+#define SPI_SR_CRCE_Pos             (7U)

+#define SPI_SR_CRCE_Msk             (0x1UL << SPI_SR_CRCE_Pos)                 /*!< 0x00000080 */

+#define SPI_SR_CRCE                 SPI_SR_CRCE_Msk                            /*!<CRC Error Detected              */

+#define SPI_SR_TIFRE_Pos            (8U)

+#define SPI_SR_TIFRE_Msk            (0x1UL << SPI_SR_TIFRE_Pos)                /*!< 0x00000100 */

+#define SPI_SR_TIFRE                SPI_SR_TIFRE_Msk                           /*!<TI frame format error Detected  */

+#define SPI_SR_MODF_Pos             (9U)

+#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000200 */

+#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode Fault Detected             */

+#define SPI_SR_TSERF_Pos            (10U)

+#define SPI_SR_TSERF_Msk            (0x1UL << SPI_SR_TSERF_Pos)                /*!< 0x00000400 */

+#define SPI_SR_TSERF                SPI_SR_TSERF_Msk                           /*!<Number of SPI data to be transacted reloaded     */

+#define SPI_SR_SUSP_Pos             (11U)

+#define SPI_SR_SUSP_Msk             (0x1UL << SPI_SR_SUSP_Pos)                 /*!< 0x00000800 */

+#define SPI_SR_SUSP                 SPI_SR_SUSP_Msk                            /*!<SUSP is set by hardware  */

+#define SPI_SR_TXC_Pos              (12U)

+#define SPI_SR_TXC_Msk              (0x1UL << SPI_SR_TXC_Pos)                  /*!< 0x00001000 */

+#define SPI_SR_TXC                  SPI_SR_TXC_Msk                             /*!<TxFIFO transmission complete */

+#define SPI_SR_RXPLVL_Pos           (13U)

+#define SPI_SR_RXPLVL_Msk           (0x3UL << SPI_SR_RXPLVL_Pos)               /*!< 0x00006000 */

+#define SPI_SR_RXPLVL               SPI_SR_RXPLVL_Msk                          /*!<RxFIFO Packing Level                             */

+#define SPI_SR_RXPLVL_0             (0x1UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00002000 */

+#define SPI_SR_RXPLVL_1             (0x2UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00004000 */

+#define SPI_SR_RXWNE_Pos            (15U)

+#define SPI_SR_RXWNE_Msk            (0x1UL << SPI_SR_RXWNE_Pos)                /*!< 0x00008000 */

+#define SPI_SR_RXWNE                SPI_SR_RXWNE_Msk                           /*!<Rx FIFO Word Not Empty                           */

+#define SPI_SR_CTSIZE_Pos           (16U)

+#define SPI_SR_CTSIZE_Msk           (0xFFFFUL << SPI_SR_CTSIZE_Pos)            /*!< 0xFFFF0000 */

+#define SPI_SR_CTSIZE               SPI_SR_CTSIZE_Msk                          /*!<Number of data frames remaining in TSIZE         */

+

+/*******************  Bit definition for SPI_IFCR register  ********************/

+#define SPI_IFCR_EOTC_Pos           (3U)

+#define SPI_IFCR_EOTC_Msk           (0x1UL << SPI_IFCR_EOTC_Pos)               /*!< 0x00000008 */

+#define SPI_IFCR_EOTC               SPI_IFCR_EOTC_Msk                          /*!<End Of Transfer flag clear              */

+#define SPI_IFCR_TXTFC_Pos          (4U)

+#define SPI_IFCR_TXTFC_Msk          (0x1UL << SPI_IFCR_TXTFC_Pos)              /*!< 0x00000010 */

+#define SPI_IFCR_TXTFC              SPI_IFCR_TXTFC_Msk                         /*!<Transmission Transfer Filled flag clear */

+#define SPI_IFCR_UDRC_Pos           (5U)

+#define SPI_IFCR_UDRC_Msk           (0x1UL << SPI_IFCR_UDRC_Pos)               /*!< 0x00000020 */

+#define SPI_IFCR_UDRC               SPI_IFCR_UDRC_Msk                          /*!<Underrun flag clear                     */

+#define SPI_IFCR_OVRC_Pos           (6U)

+#define SPI_IFCR_OVRC_Msk           (0x1UL << SPI_IFCR_OVRC_Pos)               /*!< 0x00000040 */

+#define SPI_IFCR_OVRC               SPI_IFCR_OVRC_Msk                          /*!<Overrun flag clear                      */

+#define SPI_IFCR_CRCEC_Pos          (7U)

+#define SPI_IFCR_CRCEC_Msk          (0x1UL << SPI_IFCR_CRCEC_Pos)              /*!< 0x00000080 */

+#define SPI_IFCR_CRCEC              SPI_IFCR_CRCEC_Msk                         /*!<CRC Error flag clear                    */

+#define SPI_IFCR_TIFREC_Pos         (8U)

+#define SPI_IFCR_TIFREC_Msk         (0x1UL << SPI_IFCR_TIFREC_Pos)             /*!< 0x00000100 */

+#define SPI_IFCR_TIFREC             SPI_IFCR_TIFREC_Msk                        /*!<TI frame format error flag clear        */

+#define SPI_IFCR_MODFC_Pos          (9U)

+#define SPI_IFCR_MODFC_Msk          (0x1UL << SPI_IFCR_MODFC_Pos)              /*!< 0x00000200 */

+#define SPI_IFCR_MODFC              SPI_IFCR_MODFC_Msk                         /*!<Mode Fault flag clear                   */

+#define SPI_IFCR_TSERFC_Pos         (10U)

+#define SPI_IFCR_TSERFC_Msk         (0x1UL << SPI_IFCR_TSERFC_Pos)             /*!< 0x00000400 */

+#define SPI_IFCR_TSERFC             SPI_IFCR_TSERFC_Msk                        /*!<TSERFC flag clear                       */

+#define SPI_IFCR_SUSPC_Pos          (11U)

+#define SPI_IFCR_SUSPC_Msk          (0x1UL << SPI_IFCR_SUSPC_Pos)              /*!< 0x00000800 */

+#define SPI_IFCR_SUSPC              SPI_IFCR_SUSPC_Msk                         /*!<SUSPend flag clear                      */

+

+/*******************  Bit definition for SPI_TXDR register  ********************/

+#define SPI_TXDR_TXDR_Pos           (0U)

+#define SPI_TXDR_TXDR_Msk           (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)        /*!< 0xFFFFFFFF */

+#define SPI_TXDR_TXDR               SPI_TXDR_TXDR_Msk                          /* Transmit Data Register */

+

+/*******************  Bit definition for SPI_RXDR register  ********************/

+#define SPI_RXDR_RXDR_Pos           (0U)

+#define SPI_RXDR_RXDR_Msk           (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)        /*!< 0xFFFFFFFF */

+#define SPI_RXDR_RXDR               SPI_RXDR_RXDR_Msk                          /* Receive Data Register  */

+

+/*******************  Bit definition for SPI_CRCPOLY register  ********************/

+#define SPI_CRCPOLY_CRCPOLY_Pos     (0U)

+#define SPI_CRCPOLY_CRCPOLY_Msk     (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)  /*!< 0xFFFFFFFF */

+#define SPI_CRCPOLY_CRCPOLY         SPI_CRCPOLY_CRCPOLY_Msk                    /* CRC Polynomial register  */

+

+/*******************  Bit definition for SPI_TXCRC register  ********************/

+#define SPI_TXCRC_TXCRC_Pos         (0U)

+#define SPI_TXCRC_TXCRC_Msk         (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_TXCRC_TXCRC             SPI_TXCRC_TXCRC_Msk                        /* CRCRegister for transmitter */

+

+/*******************  Bit definition for SPI_RXCRC register  ********************/

+#define SPI_RXCRC_RXCRC_Pos         (0U)

+#define SPI_RXCRC_RXCRC_Msk         (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_RXCRC_RXCRC             SPI_RXCRC_RXCRC_Msk                        /* CRCRegister for receiver */

+

+/*******************  Bit definition for SPI_UDRDR register  ********************/

+#define SPI_UDRDR_UDRDR_Pos         (0U)

+#define SPI_UDRDR_UDRDR_Msk         (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_UDRDR_UDRDR             SPI_UDRDR_UDRDR_Msk                        /* Data at slave underrun condition */

+

+/******************  Bit definition for SPI_I2SCFGR register  *****************/

+#define SPI_I2SCFGR_I2SMOD_Pos      (0U)

+#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000001 */

+#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */

+#define SPI_I2SCFGR_I2SCFG_Pos      (1U)

+#define SPI_I2SCFGR_I2SCFG_Msk      (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x0000000E */

+#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[2:0] I2S configuration mode                */

+#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000002 */

+#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000004 */

+#define SPI_I2SCFGR_I2SCFG_2        (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000008 */

+#define SPI_I2SCFGR_I2SSTD_Pos      (4U)

+#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */

+#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] I2S standard selection                */

+#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */

+#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */

+#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)

+#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */

+#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                         */

+#define SPI_I2SCFGR_DATLEN_Pos      (8U)

+#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000300 */

+#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] Data length to be transferred         */

+#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000100 */

+#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000200 */

+#define SPI_I2SCFGR_CHLEN_Pos       (10U)

+#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000400 */

+#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */

+#define SPI_I2SCFGR_CKPOL_Pos       (11U)

+#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000800 */

+#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<Steady state clock polarity                       */

+#define SPI_I2SCFGR_FIXCH_Pos       (12U)

+#define SPI_I2SCFGR_FIXCH_Msk       (0x1UL << SPI_I2SCFGR_FIXCH_Pos)           /*!< 0x00001000 */

+#define SPI_I2SCFGR_FIXCH           SPI_I2SCFGR_FIXCH_Msk                      /*!<Fixed channel length in SLAVE                     */

+#define SPI_I2SCFGR_WSINV_Pos       (13U)

+#define SPI_I2SCFGR_WSINV_Msk       (0x1UL << SPI_I2SCFGR_WSINV_Pos)           /*!< 0x00002000 */

+#define SPI_I2SCFGR_WSINV           SPI_I2SCFGR_WSINV_Msk                      /*!<Word select inversion                             */

+#define SPI_I2SCFGR_DATFMT_Pos      (14U)

+#define SPI_I2SCFGR_DATFMT_Msk      (0x1UL << SPI_I2SCFGR_DATFMT_Pos)          /*!< 0x00004000 */

+#define SPI_I2SCFGR_DATFMT          SPI_I2SCFGR_DATFMT_Msk                     /*!<Data format                                       */

+#define SPI_I2SCFGR_I2SDIV_Pos      (16U)

+#define SPI_I2SCFGR_I2SDIV_Msk      (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)         /*!< 0x00FF0000 */

+#define SPI_I2SCFGR_I2SDIV          SPI_I2SCFGR_I2SDIV_Msk                     /*!<I2S Linear prescaler */

+#define SPI_I2SCFGR_ODD_Pos         (24U)

+#define SPI_I2SCFGR_ODD_Msk         (0x1UL << SPI_I2SCFGR_ODD_Pos)             /*!< 0x01000000 */

+#define SPI_I2SCFGR_ODD             SPI_I2SCFGR_ODD_Msk                        /*!<Odd factor for the prescaler */

+#define SPI_I2SCFGR_MCKOE_Pos       (25U)

+#define SPI_I2SCFGR_MCKOE_Msk       (0x1UL << SPI_I2SCFGR_MCKOE_Pos)           /*!< 0x02000000 */

+#define SPI_I2SCFGR_MCKOE           SPI_I2SCFGR_MCKOE_Msk                      /*!<Master Clock Output Enable */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    QUADSPI                                 */

+/*                                                                            */

+/******************************************************************************/

+/*****************  Bit definition for QUADSPI_CR register  *******************/

+#define QUADSPI_CR_EN_Pos                (0U)

+#define QUADSPI_CR_EN_Msk                (0x1UL << QUADSPI_CR_EN_Pos)          /*!< 0x00000001 */

+#define QUADSPI_CR_EN                    QUADSPI_CR_EN_Msk                     /*!< Enable */

+#define QUADSPI_CR_ABORT_Pos             (1U)

+#define QUADSPI_CR_ABORT_Msk             (0x1UL << QUADSPI_CR_ABORT_Pos)       /*!< 0x00000002 */

+#define QUADSPI_CR_ABORT                 QUADSPI_CR_ABORT_Msk                  /*!< Abort request */

+#define QUADSPI_CR_DMAEN_Pos             (2U)

+#define QUADSPI_CR_DMAEN_Msk             (0x1UL << QUADSPI_CR_DMAEN_Pos)       /*!< 0x00000004 */

+#define QUADSPI_CR_DMAEN                 QUADSPI_CR_DMAEN_Msk                  /*!< DMA Enable */

+#define QUADSPI_CR_TCEN_Pos              (3U)

+#define QUADSPI_CR_TCEN_Msk              (0x1UL << QUADSPI_CR_TCEN_Pos)        /*!< 0x00000008 */

+#define QUADSPI_CR_TCEN                  QUADSPI_CR_TCEN_Msk                   /*!< Timeout Counter Enable */

+#define QUADSPI_CR_SSHIFT_Pos            (4U)

+#define QUADSPI_CR_SSHIFT_Msk            (0x1UL << QUADSPI_CR_SSHIFT_Pos)      /*!< 0x00000010 */

+#define QUADSPI_CR_SSHIFT                QUADSPI_CR_SSHIFT_Msk                 /*!< SSHIFT Sample Shift */

+#define QUADSPI_CR_DFM_Pos               (6U)

+#define QUADSPI_CR_DFM_Msk               (0x1UL << QUADSPI_CR_DFM_Pos)         /*!< 0x00000040 */

+#define QUADSPI_CR_DFM                   QUADSPI_CR_DFM_Msk                    /*!< Dual Flash Mode */

+#define QUADSPI_CR_FSEL_Pos              (7U)

+#define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)        /*!< 0x00000080 */

+#define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select */

+#define QUADSPI_CR_FTHRES_Pos            (8U)

+#define QUADSPI_CR_FTHRES_Msk            (0xFUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000F00 */

+#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level */

+#define QUADSPI_CR_FTHRES_0              (0x1UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */

+#define QUADSPI_CR_FTHRES_1              (0x2UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */

+#define QUADSPI_CR_FTHRES_2              (0x4UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */

+#define QUADSPI_CR_FTHRES_3              (0x8UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */

+#define QUADSPI_CR_TEIE_Pos              (16U)

+#define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)        /*!< 0x00010000 */

+#define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable */

+#define QUADSPI_CR_TCIE_Pos              (17U)

+#define QUADSPI_CR_TCIE_Msk              (0x1UL << QUADSPI_CR_TCIE_Pos)        /*!< 0x00020000 */

+#define QUADSPI_CR_TCIE                  QUADSPI_CR_TCIE_Msk                   /*!< Transfer Complete Interrupt Enable */

+#define QUADSPI_CR_FTIE_Pos              (18U)

+#define QUADSPI_CR_FTIE_Msk              (0x1UL << QUADSPI_CR_FTIE_Pos)        /*!< 0x00040000 */

+#define QUADSPI_CR_FTIE                  QUADSPI_CR_FTIE_Msk                   /*!< FIFO Threshold Interrupt Enable */

+#define QUADSPI_CR_SMIE_Pos              (19U)

+#define QUADSPI_CR_SMIE_Msk              (0x1UL << QUADSPI_CR_SMIE_Pos)        /*!< 0x00080000 */

+#define QUADSPI_CR_SMIE                  QUADSPI_CR_SMIE_Msk                   /*!< Status Match Interrupt Enable */

+#define QUADSPI_CR_TOIE_Pos              (20U)

+#define QUADSPI_CR_TOIE_Msk              (0x1UL << QUADSPI_CR_TOIE_Pos)        /*!< 0x00100000 */

+#define QUADSPI_CR_TOIE                  QUADSPI_CR_TOIE_Msk                   /*!< TimeOut Interrupt Enable */

+#define QUADSPI_CR_APMS_Pos              (22U)

+#define QUADSPI_CR_APMS_Msk              (0x1UL << QUADSPI_CR_APMS_Pos)        /*!< 0x00400000 */

+#define QUADSPI_CR_APMS                  QUADSPI_CR_APMS_Msk                   /*!< Bit 1 */

+#define QUADSPI_CR_PMM_Pos               (23U)

+#define QUADSPI_CR_PMM_Msk               (0x1UL << QUADSPI_CR_PMM_Pos)         /*!< 0x00800000 */

+#define QUADSPI_CR_PMM                   QUADSPI_CR_PMM_Msk                    /*!< Polling Match Mode */

+#define QUADSPI_CR_PRESCALER_Pos         (24U)

+#define QUADSPI_CR_PRESCALER_Msk         (0xFFUL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0xFF000000 */

+#define QUADSPI_CR_PRESCALER             QUADSPI_CR_PRESCALER_Msk              /*!< PRESCALER[7:0] Clock prescaler */

+#define QUADSPI_CR_PRESCALER_0           (0x01UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x01000000 */

+#define QUADSPI_CR_PRESCALER_1           (0x02UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x02000000 */

+#define QUADSPI_CR_PRESCALER_2           (0x04UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x04000000 */

+#define QUADSPI_CR_PRESCALER_3           (0x08UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x08000000 */

+#define QUADSPI_CR_PRESCALER_4           (0x10UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x10000000 */

+#define QUADSPI_CR_PRESCALER_5           (0x20UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x20000000 */

+#define QUADSPI_CR_PRESCALER_6           (0x40UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x40000000 */

+#define QUADSPI_CR_PRESCALER_7           (0x80UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x80000000 */

+

+/*****************  Bit definition for QUADSPI_DCR register  ******************/

+#define QUADSPI_DCR_CKMODE_Pos           (0U)

+#define QUADSPI_DCR_CKMODE_Msk           (0x1UL << QUADSPI_DCR_CKMODE_Pos)     /*!< 0x00000001 */

+#define QUADSPI_DCR_CKMODE               QUADSPI_DCR_CKMODE_Msk                /*!< Mode 0 / Mode 3 */

+#define QUADSPI_DCR_CSHT_Pos             (8U)

+#define QUADSPI_DCR_CSHT_Msk             (0x7UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000700 */

+#define QUADSPI_DCR_CSHT                 QUADSPI_DCR_CSHT_Msk                  /*!< CSHT[2:0]: ChipSelect High Time */

+#define QUADSPI_DCR_CSHT_0               (0x1UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000100 */

+#define QUADSPI_DCR_CSHT_1               (0x2UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000200 */

+#define QUADSPI_DCR_CSHT_2               (0x4UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000400 */

+#define QUADSPI_DCR_FSIZE_Pos            (16U)

+#define QUADSPI_DCR_FSIZE_Msk            (0x1FUL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x001F0000 */

+#define QUADSPI_DCR_FSIZE                QUADSPI_DCR_FSIZE_Msk                 /*!< FSIZE[4:0]: Flash Size */

+#define QUADSPI_DCR_FSIZE_0              (0x01UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00010000 */

+#define QUADSPI_DCR_FSIZE_1              (0x02UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00020000 */

+#define QUADSPI_DCR_FSIZE_2              (0x04UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00040000 */

+#define QUADSPI_DCR_FSIZE_3              (0x08UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00080000 */

+#define QUADSPI_DCR_FSIZE_4              (0x10UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00100000 */

+

+/******************  Bit definition for QUADSPI_SR register  *******************/

+#define QUADSPI_SR_TEF_Pos               (0U)

+#define QUADSPI_SR_TEF_Msk               (0x1UL << QUADSPI_SR_TEF_Pos)         /*!< 0x00000001 */

+#define QUADSPI_SR_TEF                   QUADSPI_SR_TEF_Msk                    /*!< Transfer Error Flag */

+#define QUADSPI_SR_TCF_Pos               (1U)

+#define QUADSPI_SR_TCF_Msk               (0x1UL << QUADSPI_SR_TCF_Pos)         /*!< 0x00000002 */

+#define QUADSPI_SR_TCF                   QUADSPI_SR_TCF_Msk                    /*!< Transfer Complete Flag */

+#define QUADSPI_SR_FTF_Pos               (2U)

+#define QUADSPI_SR_FTF_Msk               (0x1UL << QUADSPI_SR_FTF_Pos)         /*!< 0x00000004 */

+#define QUADSPI_SR_FTF                   QUADSPI_SR_FTF_Msk                    /*!< FIFO Threshlod Flag */

+#define QUADSPI_SR_SMF_Pos               (3U)

+#define QUADSPI_SR_SMF_Msk               (0x1UL << QUADSPI_SR_SMF_Pos)         /*!< 0x00000008 */

+#define QUADSPI_SR_SMF                   QUADSPI_SR_SMF_Msk                    /*!< Status Match Flag */

+#define QUADSPI_SR_TOF_Pos               (4U)

+#define QUADSPI_SR_TOF_Msk               (0x1UL << QUADSPI_SR_TOF_Pos)         /*!< 0x00000010 */

+#define QUADSPI_SR_TOF                   QUADSPI_SR_TOF_Msk                    /*!< Timeout Flag */

+#define QUADSPI_SR_BUSY_Pos              (5U)

+#define QUADSPI_SR_BUSY_Msk              (0x1UL << QUADSPI_SR_BUSY_Pos)        /*!< 0x00000020 */

+#define QUADSPI_SR_BUSY                  QUADSPI_SR_BUSY_Msk                   /*!< Busy */

+#define QUADSPI_SR_FLEVEL_Pos            (8U)

+#define QUADSPI_SR_FLEVEL_Msk            (0x3FUL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00003F00 */

+#define QUADSPI_SR_FLEVEL                QUADSPI_SR_FLEVEL_Msk                 /*!< FIFO Threshlod Flag */

+#define QUADSPI_SR_FLEVEL_0              (0x01UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000100 */

+#define QUADSPI_SR_FLEVEL_1              (0x02UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000200 */

+#define QUADSPI_SR_FLEVEL_2              (0x04UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000400 */

+#define QUADSPI_SR_FLEVEL_3              (0x08UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000800 */

+#define QUADSPI_SR_FLEVEL_4              (0x10UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00001000 */

+#define QUADSPI_SR_FLEVEL_5              (0x20UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00002000 */

+

+/******************  Bit definition for QUADSPI_FCR register  ******************/

+#define QUADSPI_FCR_CTEF_Pos             (0U)

+#define QUADSPI_FCR_CTEF_Msk             (0x1UL << QUADSPI_FCR_CTEF_Pos)       /*!< 0x00000001 */

+#define QUADSPI_FCR_CTEF                 QUADSPI_FCR_CTEF_Msk                  /*!< Clear Transfer Error Flag */

+#define QUADSPI_FCR_CTCF_Pos             (1U)

+#define QUADSPI_FCR_CTCF_Msk             (0x1UL << QUADSPI_FCR_CTCF_Pos)       /*!< 0x00000002 */

+#define QUADSPI_FCR_CTCF                 QUADSPI_FCR_CTCF_Msk                  /*!< Clear Transfer Complete Flag */

+#define QUADSPI_FCR_CSMF_Pos             (3U)

+#define QUADSPI_FCR_CSMF_Msk             (0x1UL << QUADSPI_FCR_CSMF_Pos)       /*!< 0x00000008 */

+#define QUADSPI_FCR_CSMF                 QUADSPI_FCR_CSMF_Msk                  /*!< Clear Status Match Flag */

+#define QUADSPI_FCR_CTOF_Pos             (4U)

+#define QUADSPI_FCR_CTOF_Msk             (0x1UL << QUADSPI_FCR_CTOF_Pos)       /*!< 0x00000010 */

+#define QUADSPI_FCR_CTOF                 QUADSPI_FCR_CTOF_Msk                  /*!< Clear Timeout Flag */

+

+/******************  Bit definition for QUADSPI_DLR register  ******************/

+#define QUADSPI_DLR_DL_Pos               (0U)

+#define QUADSPI_DLR_DL_Msk               (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)  /*!< 0xFFFFFFFF */

+#define QUADSPI_DLR_DL                   QUADSPI_DLR_DL_Msk                    /*!< DL[31:0]: Data Length */

+

+/******************  Bit definition for QUADSPI_CCR register  ******************/

+#define QUADSPI_CCR_INSTRUCTION_Pos      (0U)

+#define QUADSPI_CCR_INSTRUCTION_Msk      (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */

+#define QUADSPI_CCR_INSTRUCTION          QUADSPI_CCR_INSTRUCTION_Msk             /*!< INSTRUCTION[7:0]: Instruction */

+#define QUADSPI_CCR_INSTRUCTION_0        (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */

+#define QUADSPI_CCR_INSTRUCTION_1        (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */

+#define QUADSPI_CCR_INSTRUCTION_2        (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */

+#define QUADSPI_CCR_INSTRUCTION_3        (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */

+#define QUADSPI_CCR_INSTRUCTION_4        (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */

+#define QUADSPI_CCR_INSTRUCTION_5        (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */

+#define QUADSPI_CCR_INSTRUCTION_6        (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */

+#define QUADSPI_CCR_INSTRUCTION_7        (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */

+#define QUADSPI_CCR_IMODE_Pos            (8U)

+#define QUADSPI_CCR_IMODE_Msk            (0x3UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000300 */

+#define QUADSPI_CCR_IMODE                QUADSPI_CCR_IMODE_Msk                   /*!< IMODE[1:0]: Instruction Mode */

+#define QUADSPI_CCR_IMODE_0              (0x1UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000100 */

+#define QUADSPI_CCR_IMODE_1              (0x2UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000200 */

+#define QUADSPI_CCR_ADMODE_Pos           (10U)

+#define QUADSPI_CCR_ADMODE_Msk           (0x3UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000C00 */

+#define QUADSPI_CCR_ADMODE               QUADSPI_CCR_ADMODE_Msk                  /*!< ADMODE[1:0]: Address Mode */

+#define QUADSPI_CCR_ADMODE_0             (0x1UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000400 */

+#define QUADSPI_CCR_ADMODE_1             (0x2UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000800 */

+#define QUADSPI_CCR_ADSIZE_Pos           (12U)

+#define QUADSPI_CCR_ADSIZE_Msk           (0x3UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00003000 */

+#define QUADSPI_CCR_ADSIZE               QUADSPI_CCR_ADSIZE_Msk                  /*!< ADSIZE[1:0]: Address Size */

+#define QUADSPI_CCR_ADSIZE_0             (0x1UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00001000 */

+#define QUADSPI_CCR_ADSIZE_1             (0x2UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00002000 */

+#define QUADSPI_CCR_ABMODE_Pos           (14U)

+#define QUADSPI_CCR_ABMODE_Msk           (0x3UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x0000C000 */

+#define QUADSPI_CCR_ABMODE               QUADSPI_CCR_ABMODE_Msk                  /*!< ABMODE[1:0]: Alternate Bytes Mode */

+#define QUADSPI_CCR_ABMODE_0             (0x1UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00004000 */

+#define QUADSPI_CCR_ABMODE_1             (0x2UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00008000 */

+#define QUADSPI_CCR_ABSIZE_Pos           (16U)

+#define QUADSPI_CCR_ABSIZE_Msk           (0x3UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00030000 */

+#define QUADSPI_CCR_ABSIZE               QUADSPI_CCR_ABSIZE_Msk                  /*!< ABSIZE[1:0]: Instruction Mode */

+#define QUADSPI_CCR_ABSIZE_0             (0x1UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00010000 */

+#define QUADSPI_CCR_ABSIZE_1             (0x2UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00020000 */

+#define QUADSPI_CCR_DCYC_Pos             (18U)

+#define QUADSPI_CCR_DCYC_Msk             (0x1FUL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x007C0000 */

+#define QUADSPI_CCR_DCYC                 QUADSPI_CCR_DCYC_Msk                    /*!< DCYC[4:0]: Dummy Cycles */

+#define QUADSPI_CCR_DCYC_0               (0x01UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00040000 */

+#define QUADSPI_CCR_DCYC_1               (0x02UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00080000 */

+#define QUADSPI_CCR_DCYC_2               (0x04UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00100000 */

+#define QUADSPI_CCR_DCYC_3               (0x08UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00200000 */

+#define QUADSPI_CCR_DCYC_4               (0x10UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00400000 */

+#define QUADSPI_CCR_DMODE_Pos            (24U)

+#define QUADSPI_CCR_DMODE_Msk            (0x3UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x03000000 */

+#define QUADSPI_CCR_DMODE                QUADSPI_CCR_DMODE_Msk                   /*!< DMODE[1:0]: Data Mode */

+#define QUADSPI_CCR_DMODE_0              (0x1UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x01000000 */

+#define QUADSPI_CCR_DMODE_1              (0x2UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x02000000 */

+#define QUADSPI_CCR_FMODE_Pos            (26U)

+#define QUADSPI_CCR_FMODE_Msk            (0x3UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x0C000000 */

+#define QUADSPI_CCR_FMODE                QUADSPI_CCR_FMODE_Msk                   /*!< FMODE[1:0]: Functional Mode */

+#define QUADSPI_CCR_FMODE_0              (0x1UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x04000000 */

+#define QUADSPI_CCR_FMODE_1              (0x2UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x08000000 */

+#define QUADSPI_CCR_SIOO_Pos             (28U)

+#define QUADSPI_CCR_SIOO_Msk             (0x1UL << QUADSPI_CCR_SIOO_Pos)         /*!< 0x10000000 */

+#define QUADSPI_CCR_SIOO                 QUADSPI_CCR_SIOO_Msk                    /*!< SIOO: Send Instruction Only Once Mode */

+#define QUADSPI_CCR_DHHC_Pos             (30U)

+#define QUADSPI_CCR_DHHC_Msk             (0x1UL << QUADSPI_CCR_DHHC_Pos)         /*!< 0x40000000 */

+#define QUADSPI_CCR_DHHC                 QUADSPI_CCR_DHHC_Msk                    /*!< DHHC: DDR hold half cycle */

+#define QUADSPI_CCR_DDRM_Pos             (31U)

+#define QUADSPI_CCR_DDRM_Msk             (0x1UL << QUADSPI_CCR_DDRM_Pos)         /*!< 0x80000000 */

+#define QUADSPI_CCR_DDRM                 QUADSPI_CCR_DDRM_Msk                    /*!< DDRM: Double Data Rate Mode */

+

+/******************  Bit definition for QUADSPI_AR register  *******************/

+#define QUADSPI_AR_ADDRESS_Pos           (0U)

+#define QUADSPI_AR_ADDRESS_Msk           (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_AR_ADDRESS               QUADSPI_AR_ADDRESS_Msk                /*!< ADDRESS[31:0]: Address */

+

+/******************  Bit definition for QUADSPI_ABR register  ******************/

+#define QUADSPI_ABR_ALTERNATE_Pos        (0U)

+#define QUADSPI_ABR_ALTERNATE_Msk        (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_ABR_ALTERNATE            QUADSPI_ABR_ALTERNATE_Msk             /*!< ALTERNATE[31:0]: Alternate Bytes */

+

+/******************  Bit definition for QUADSPI_DR register  *******************/

+#define QUADSPI_DR_DATA_Pos              (0U)

+#define QUADSPI_DR_DATA_Msk              (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_DR_DATA                  QUADSPI_DR_DATA_Msk                   /*!< DATA[31:0]: Data */

+

+/******************  Bit definition for QUADSPI_PSMKR register  ****************/

+#define QUADSPI_PSMKR_MASK_Pos           (0U)

+#define QUADSPI_PSMKR_MASK_Msk           (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_PSMKR_MASK               QUADSPI_PSMKR_MASK_Msk                /*!< MASK[31:0]: Status Mask */

+

+/******************  Bit definition for QUADSPI_PSMAR register  ****************/

+#define QUADSPI_PSMAR_MATCH_Pos          (0U)

+#define QUADSPI_PSMAR_MATCH_Msk          (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_PSMAR_MATCH              QUADSPI_PSMAR_MATCH_Msk               /*!< MATCH[31:0]: Status Match */

+

+/******************  Bit definition for QUADSPI_PIR register  *****************/

+#define QUADSPI_PIR_INTERVAL_Pos         (0U)

+#define QUADSPI_PIR_INTERVAL_Msk         (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */

+#define QUADSPI_PIR_INTERVAL             QUADSPI_PIR_INTERVAL_Msk              /*!< INTERVAL[15:0]: Polling Interval */

+

+/******************  Bit definition for QUADSPI_LPTR register  *****************/

+#define QUADSPI_LPTR_TIMEOUT_Pos         (0U)

+#define QUADSPI_LPTR_TIMEOUT_Msk         (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */

+#define QUADSPI_LPTR_TIMEOUT             QUADSPI_LPTR_TIMEOUT_Msk              /*!< TIMEOUT[15:0]: Timeout period */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                 SYSCFG                                     */

+/*                                                                            */

+/******************************************************************************/

+

+/******************  Bit definition for SYSCFG_PMCR register  ******************/

+#define SYSCFG_PMCR_I2C1_FMP_Pos        (0U)

+#define SYSCFG_PMCR_I2C1_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos)    /*!< 0x00000001 */

+#define SYSCFG_PMCR_I2C1_FMP            SYSCFG_PMCR_I2C1_FMP_Msk               /*!< I2C1 Fast mode plus */

+#define SYSCFG_PMCR_I2C2_FMP_Pos        (1U)

+#define SYSCFG_PMCR_I2C2_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos)    /*!< 0x00000002 */

+#define SYSCFG_PMCR_I2C2_FMP            SYSCFG_PMCR_I2C2_FMP_Msk               /*!< I2C2 Fast mode plus */

+#define SYSCFG_PMCR_I2C3_FMP_Pos        (2U)

+#define SYSCFG_PMCR_I2C3_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos)    /*!< 0x00000004 */

+#define SYSCFG_PMCR_I2C3_FMP            SYSCFG_PMCR_I2C3_FMP_Msk               /*!< I2C3 Fast mode plus */

+#define SYSCFG_PMCR_I2C4_FMP_Pos        (3U)

+#define SYSCFG_PMCR_I2C4_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos)    /*!< 0x00000008 */

+#define SYSCFG_PMCR_I2C4_FMP            SYSCFG_PMCR_I2C4_FMP_Msk               /*!< I2C4 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB6_FMP_Pos     (4U)

+#define SYSCFG_PMCR_I2C_PB6_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */

+#define SYSCFG_PMCR_I2C_PB6_FMP         SYSCFG_PMCR_I2C_PB6_FMP_Msk            /*!< I2C PB6 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB7_FMP_Pos     (5U)

+#define SYSCFG_PMCR_I2C_PB7_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */

+#define SYSCFG_PMCR_I2C_PB7_FMP         SYSCFG_PMCR_I2C_PB7_FMP_Msk            /*!< I2C PB7 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB8_FMP_Pos     (6U)

+#define SYSCFG_PMCR_I2C_PB8_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */

+#define SYSCFG_PMCR_I2C_PB8_FMP         SYSCFG_PMCR_I2C_PB8_FMP_Msk            /*!< I2C PB8 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB9_FMP_Pos     (7U)

+#define SYSCFG_PMCR_I2C_PB9_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */

+#define SYSCFG_PMCR_I2C_PB9_FMP         SYSCFG_PMCR_I2C_PB9_FMP_Msk            /*!< I2C PB9 Fast mode plus */

+#define SYSCFG_PMCR_BOOSTEN_Pos         (8U)

+#define SYSCFG_PMCR_BOOSTEN_Msk         (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos)     /*!< 0x00000100 */

+#define SYSCFG_PMCR_BOOSTEN             SYSCFG_PMCR_BOOSTEN_Msk                /*!< I/O analog switch voltage booster enable */

+

+#define SYSCFG_PMCR_BOOSTVDDSEL_Pos     (9U)

+#define SYSCFG_PMCR_BOOSTVDDSEL_Msk     (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos) /*!< 0x00000200 */

+#define SYSCFG_PMCR_BOOSTVDDSEL         SYSCFG_PMCR_BOOSTVDDSEL_Msk            /*!< Analog switch supply source selection : VDD/VDDA */

+

+#define SYSCFG_PMCR_EPIS_SEL_Pos        (21U)

+#define SYSCFG_PMCR_EPIS_SEL_Msk        (0x7UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00E00000 */

+#define SYSCFG_PMCR_EPIS_SEL            SYSCFG_PMCR_EPIS_SEL_Msk               /*!< Ethernet PHY Interface Selection */

+#define SYSCFG_PMCR_EPIS_SEL_0          (0x1UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00200000 */

+#define SYSCFG_PMCR_EPIS_SEL_1          (0x2UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00400000 */

+#define SYSCFG_PMCR_EPIS_SEL_2          (0x4UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00800000 */

+#define SYSCFG_PMCR_PA0SO_Pos           (24U)

+#define SYSCFG_PMCR_PA0SO_Msk           (0x1UL << SYSCFG_PMCR_PA0SO_Pos)       /*!< 0x01000000 */

+#define SYSCFG_PMCR_PA0SO               SYSCFG_PMCR_PA0SO_Msk                  /*!< PA0 Switch Open */

+#define SYSCFG_PMCR_PA1SO_Pos           (25U)

+#define SYSCFG_PMCR_PA1SO_Msk           (0x1UL << SYSCFG_PMCR_PA1SO_Pos)       /*!< 0x02000000 */

+#define SYSCFG_PMCR_PA1SO               SYSCFG_PMCR_PA1SO_Msk                  /*!< PA1 Switch Open */

+#define SYSCFG_PMCR_PC2SO_Pos           (26U)

+#define SYSCFG_PMCR_PC2SO_Msk           (0x1UL << SYSCFG_PMCR_PC2SO_Pos)       /*!< 0x04000000 */

+#define SYSCFG_PMCR_PC2SO               SYSCFG_PMCR_PC2SO_Msk                  /*!< PC2 Switch Open */

+#define SYSCFG_PMCR_PC3SO_Pos           (27U)

+#define SYSCFG_PMCR_PC3SO_Msk           (0x1UL << SYSCFG_PMCR_PC3SO_Pos)       /*!< 0x08000000 */

+#define SYSCFG_PMCR_PC3SO               SYSCFG_PMCR_PC3SO_Msk                  /*!< PC3 Switch Open */

+

+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/

+#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)

+#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */

+#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)

+#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */

+#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)

+#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000F00 */

+#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */

+#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)

+#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x0000F000 */

+#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */

+/**

+  * @brief   EXTI0 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */

+

+/**

+  * @brief   EXTI1 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */

+/**

+  * @brief   EXTI2 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */

+

+/**

+  * @brief   EXTI3 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/

+#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)

+#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */

+#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)

+#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */

+#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)

+#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000F00 */

+#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */

+#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)

+#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x0000F000 */

+#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */

+/**

+  * @brief   EXTI4 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */

+/**

+  * @brief   EXTI5 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */

+/**

+  * @brief   EXTI6 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */

+

+/**

+  * @brief   EXTI7 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/

+#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)

+#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */

+#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)

+#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */

+#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)

+#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000F00 */

+#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */

+#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)

+#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x0000F000 */

+#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */

+

+/**

+  * @brief   EXTI8 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */

+

+/**

+  * @brief   EXTI9 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */

+

+/**

+  * @brief   EXTI10 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */

+

+/**

+  * @brief   EXTI11 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/

+#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)

+#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x0000000F */

+#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */

+#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)

+#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x000000F0 */

+#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */

+#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)

+#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000F00 */

+#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */

+#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)

+#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x0000F000 */

+#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */

+/**

+  * @brief   EXTI12 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */

+/**

+  * @brief   EXTI13 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */

+/**

+  * @brief   EXTI14 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */

+/**

+  * @brief   EXTI15 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */

+

+/******************  Bit definition for SYSCFG_CFGR register  ******************/

+#define SYSCFG_CFGR_PVDL_Pos            (2U)

+#define SYSCFG_CFGR_PVDL_Msk            (0x1UL << SYSCFG_CFGR_PVDL_Pos)        /*!< 0x00000004 */

+#define SYSCFG_CFGR_PVDL                SYSCFG_CFGR_PVDL_Msk                   /*!<PVD lock enable bit */

+#define SYSCFG_CFGR_FLASHL_Pos          (3U)

+#define SYSCFG_CFGR_FLASHL_Msk          (0x1UL << SYSCFG_CFGR_FLASHL_Pos)      /*!< 0x00000008 */

+#define SYSCFG_CFGR_FLASHL              SYSCFG_CFGR_FLASHL_Msk                 /*!<FLASH double ECC error lock bit */

+#define SYSCFG_CFGR_CM7L_Pos            (6U)

+#define SYSCFG_CFGR_CM7L_Msk            (0x1UL << SYSCFG_CFGR_CM7L_Pos)        /*!< 0x00000040 */

+#define SYSCFG_CFGR_CM7L                SYSCFG_CFGR_CM7L_Msk                   /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */

+#define SYSCFG_CFGR_BKRAML_Pos          (7U)

+#define SYSCFG_CFGR_BKRAML_Msk          (0x1UL << SYSCFG_CFGR_BKRAML_Pos)      /*!< 0x00000080 */

+#define SYSCFG_CFGR_BKRAML              SYSCFG_CFGR_BKRAML_Msk                 /*!<Backup SRAM double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM4L_Pos          (9U)

+#define SYSCFG_CFGR_SRAM4L_Msk          (0x1UL << SYSCFG_CFGR_SRAM4L_Pos)      /*!< 0x00000200 */

+#define SYSCFG_CFGR_SRAM4L              SYSCFG_CFGR_SRAM4L_Msk                 /*!<SRAM4 double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM3L_Pos          (10U)

+#define SYSCFG_CFGR_SRAM3L_Msk          (0x1UL << SYSCFG_CFGR_SRAM3L_Pos)      /*!< 0x00000400 */

+#define SYSCFG_CFGR_SRAM3L              SYSCFG_CFGR_SRAM3L_Msk                 /*!<SRAM3 double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM2L_Pos          (11U)

+#define SYSCFG_CFGR_SRAM2L_Msk          (0x1UL << SYSCFG_CFGR_SRAM2L_Pos)      /*!< 0x00000800 */

+#define SYSCFG_CFGR_SRAM2L              SYSCFG_CFGR_SRAM2L_Msk                 /*!<SRAM2 double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM1L_Pos          (12U)

+#define SYSCFG_CFGR_SRAM1L_Msk          (0x1UL << SYSCFG_CFGR_SRAM1L_Pos)      /*!< 0x00001000 */

+#define SYSCFG_CFGR_SRAM1L              SYSCFG_CFGR_SRAM1L_Msk                 /*!<SRAM1 double ECC error lock bit */

+#define SYSCFG_CFGR_DTCML_Pos           (13U)

+#define SYSCFG_CFGR_DTCML_Msk           (0x1UL << SYSCFG_CFGR_DTCML_Pos)       /*!< 0x00002000 */

+#define SYSCFG_CFGR_DTCML               SYSCFG_CFGR_DTCML_Msk                  /*!<DTCM double ECC error lock bit */

+#define SYSCFG_CFGR_ITCML_Pos           (14U)

+#define SYSCFG_CFGR_ITCML_Msk           (0x1UL << SYSCFG_CFGR_ITCML_Pos)       /*!< 0x00004000 */

+#define SYSCFG_CFGR_ITCML               SYSCFG_CFGR_ITCML_Msk                  /*!<ITCM double ECC error lock bit */

+#define SYSCFG_CFGR_AXISRAML_Pos        (15U)

+#define SYSCFG_CFGR_AXISRAML_Msk        (0x1UL << SYSCFG_CFGR_AXISRAML_Pos)    /*!< 0x00008000 */

+#define SYSCFG_CFGR_AXISRAML            SYSCFG_CFGR_AXISRAML_Msk               /*!<AXISRAM double ECC error lock bit */

+

+/******************  Bit definition for SYSCFG_CCCSR register  ******************/

+#define SYSCFG_CCCSR_EN_Pos             (0U)

+#define SYSCFG_CCCSR_EN_Msk             (0x1UL << SYSCFG_CCCSR_EN_Pos)         /*!< 0x00000001 */

+#define SYSCFG_CCCSR_EN                 SYSCFG_CCCSR_EN_Msk                    /*!< I/O compensation cell enable */

+#define SYSCFG_CCCSR_CS_Pos             (1U)

+#define SYSCFG_CCCSR_CS_Msk             (0x1UL << SYSCFG_CCCSR_CS_Pos)         /*!< 0x00000002 */

+#define SYSCFG_CCCSR_CS                 SYSCFG_CCCSR_CS_Msk                    /*!< I/O compensation cell code selection */

+#define SYSCFG_CCCSR_READY_Pos          (8U)

+#define SYSCFG_CCCSR_READY_Msk          (0x1UL << SYSCFG_CCCSR_READY_Pos)      /*!< 0x00000100 */

+#define SYSCFG_CCCSR_READY              SYSCFG_CCCSR_READY_Msk                 /*!< I/O compensation cell ready flag */

+#define SYSCFG_CCCSR_HSLV_Pos           (16U)

+#define SYSCFG_CCCSR_HSLV_Msk           (0x1UL << SYSCFG_CCCSR_HSLV_Pos)       /*!< 0x00010000 */

+#define SYSCFG_CCCSR_HSLV               SYSCFG_CCCSR_HSLV_Msk                  /*!< High-speed at low-voltage */

+

+/******************  Bit definition for SYSCFG_CCVR register  *******************/

+#define SYSCFG_CCVR_NCV_Pos             (0U)

+#define SYSCFG_CCVR_NCV_Msk             (0xFUL << SYSCFG_CCVR_NCV_Pos)         /*!< 0x0000000F */

+#define SYSCFG_CCVR_NCV                 SYSCFG_CCVR_NCV_Msk                    /*!< NMOS compensation value */

+#define SYSCFG_CCVR_PCV_Pos             (4U)

+#define SYSCFG_CCVR_PCV_Msk             (0xFUL << SYSCFG_CCVR_PCV_Pos)         /*!< 0x000000F0 */

+#define SYSCFG_CCVR_PCV                 SYSCFG_CCVR_PCV_Msk                    /*!< PMOS compensation value */

+

+/******************  Bit definition for SYSCFG_CCCR register  *******************/

+#define SYSCFG_CCCR_NCC_Pos             (0U)

+#define SYSCFG_CCCR_NCC_Msk             (0xFUL << SYSCFG_CCCR_NCC_Pos)         /*!< 0x0000000F */

+#define SYSCFG_CCCR_NCC                 SYSCFG_CCCR_NCC_Msk                    /*!< NMOS compensation code */

+#define SYSCFG_CCCR_PCC_Pos             (4U)

+#define SYSCFG_CCCR_PCC_Msk             (0xFUL << SYSCFG_CCCR_PCC_Pos)         /*!< 0x000000F0 */

+#define SYSCFG_CCCR_PCC                 SYSCFG_CCCR_PCC_Msk                    /*!< PMOS compensation code */

+/******************  Bit definition for SYSCFG_PWRCR register  *******************/

+#define SYSCFG_PWRCR_ODEN_Pos           (0U)

+#define SYSCFG_PWRCR_ODEN_Msk           (0x1UL << SYSCFG_PWRCR_ODEN_Pos)         /*!< 0x00000001 */

+#define SYSCFG_PWRCR_ODEN               SYSCFG_PWRCR_ODEN_Msk                    /*!< PWR overdrive enable */

+

+/******************  Bit definition for SYSCFG_PKGR register  *******************/

+#define SYSCFG_PKGR_PKG_Pos             (0U)

+#define SYSCFG_PKGR_PKG_Msk             (0xFUL << SYSCFG_PKGR_PKG_Pos)         /*!< 0x0000000F */

+#define SYSCFG_PKGR_PKG                 SYSCFG_PKGR_PKG_Msk                    /*!< Package type */

+

+/******************  Bit definition for SYSCFG_UR0 register  *******************/

+#define SYSCFG_UR0_BKS_Pos              (0U)

+#define SYSCFG_UR0_BKS_Msk              (0x1UL << SYSCFG_UR0_BKS_Pos)          /*!< 0x00000001 */

+#define SYSCFG_UR0_BKS                  SYSCFG_UR0_BKS_Msk                     /*!< Bank Swap */

+#define SYSCFG_UR0_RDP_Pos              (16U)

+#define SYSCFG_UR0_RDP_Msk              (0xFFUL << SYSCFG_UR0_RDP_Pos)         /*!< 0x00FF0000 */

+#define SYSCFG_UR0_RDP                  SYSCFG_UR0_RDP_Msk                     /*!< Readout protection */

+

+/******************  Bit definition for SYSCFG_UR2 register  *******************/

+#define SYSCFG_UR2_BORH_Pos             (0U)

+#define SYSCFG_UR2_BORH_Msk             (0x3UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000003 */

+#define SYSCFG_UR2_BORH                 SYSCFG_UR2_BORH_Msk                    /*!< Brown Out Reset High level */

+#define SYSCFG_UR2_BORH_0               (0x1UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000001 */

+#define SYSCFG_UR2_BORH_1               (0x2UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000002 */

+#define SYSCFG_UR2_BOOT_ADD0_Pos        (16U)

+#define SYSCFG_UR2_BOOT_ADD0_Msk        (0xFFFFUL << SYSCFG_UR2_BOOT_ADD0_Pos) /*!< 0xFFFF0000 */

+#define SYSCFG_UR2_BOOT_ADD0            SYSCFG_UR2_BOOT_ADD0_Msk               /*!< Core Boot Address 0 */

+/******************  Bit definition for SYSCFG_UR3 register  *******************/

+#define SYSCFG_UR3_BOOT_ADD1_Pos        (0U)

+#define SYSCFG_UR3_BOOT_ADD1_Msk        (0xFFFFUL << SYSCFG_UR3_BOOT_ADD1_Pos) /*!< 0x0000FFFF */

+#define SYSCFG_UR3_BOOT_ADD1            SYSCFG_UR3_BOOT_ADD1_Msk               /*!< Core Boot Address 1 */

+

+  /******************  Bit definition for SYSCFG_UR4 register  *******************/

+

+#define SYSCFG_UR4_MEPAD_BANK1_Pos      (16U)

+#define SYSCFG_UR4_MEPAD_BANK1_Msk      (0x1UL << SYSCFG_UR4_MEPAD_BANK1_Pos)  /*!< 0x00010000 */

+#define SYSCFG_UR4_MEPAD_BANK1          SYSCFG_UR4_MEPAD_BANK1_Msk             /*!< Mass Erase Protected Area Disabled for bank 1 */

+

+/******************  Bit definition for SYSCFG_UR5 register  *******************/

+#define SYSCFG_UR5_MESAD_BANK1_Pos      (0U)

+#define SYSCFG_UR5_MESAD_BANK1_Msk      (0x1UL << SYSCFG_UR5_MESAD_BANK1_Pos)  /*!< 0x00000001 */

+#define SYSCFG_UR5_MESAD_BANK1          SYSCFG_UR5_MESAD_BANK1_Msk             /*!< Mass erase secured area disabled for bank 1 */

+#define SYSCFG_UR5_WRPN_BANK1_Pos       (16U)

+#define SYSCFG_UR5_WRPN_BANK1_Msk       (0xFFUL << SYSCFG_UR5_WRPN_BANK1_Pos)  /*!< 0x00FF0000 */

+#define SYSCFG_UR5_WRPN_BANK1           SYSCFG_UR5_WRPN_BANK1_Msk              /*!< Write protection for flash bank 1 */

+

+/******************  Bit definition for SYSCFG_UR6 register  *******************/

+#define SYSCFG_UR6_PABEG_BANK1_Pos      (0U)

+#define SYSCFG_UR6_PABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PABEG_BANK1_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR6_PABEG_BANK1          SYSCFG_UR6_PABEG_BANK1_Msk             /*!< Protected area start address for bank 1 */

+#define SYSCFG_UR6_PAEND_BANK1_Pos      (16U)

+#define SYSCFG_UR6_PAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PAEND_BANK1_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR6_PAEND_BANK1          SYSCFG_UR6_PAEND_BANK1_Msk             /*!< Protected area end address for bank 1 */

+

+/******************  Bit definition for SYSCFG_UR7 register  *******************/

+#define SYSCFG_UR7_SABEG_BANK1_Pos      (0U)

+#define SYSCFG_UR7_SABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SABEG_BANK1_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR7_SABEG_BANK1          SYSCFG_UR7_SABEG_BANK1_Msk             /*!< Secured area start address for bank 1 */

+#define SYSCFG_UR7_SAEND_BANK1_Pos      (16U)

+#define SYSCFG_UR7_SAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SAEND_BANK1_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR7_SAEND_BANK1          SYSCFG_UR7_SAEND_BANK1_Msk             /*!< Secured area end address for bank 1 */

+

+/******************  Bit definition for SYSCFG_UR8 register  *******************/

+#define SYSCFG_UR8_MEPAD_BANK2_Pos      (0U)

+#define SYSCFG_UR8_MEPAD_BANK2_Msk      (0x1UL << SYSCFG_UR8_MEPAD_BANK2_Pos)  /*!< 0x00000001 */

+#define SYSCFG_UR8_MEPAD_BANK2          SYSCFG_UR8_MEPAD_BANK2_Msk             /*!< Mass erase Protected area disabled for bank 2 */

+#define SYSCFG_UR8_MESAD_BANK2_Pos      (16U)

+#define SYSCFG_UR8_MESAD_BANK2_Msk      (0x1UL << SYSCFG_UR8_MESAD_BANK2_Pos)  /*!< 0x00010000 */

+#define SYSCFG_UR8_MESAD_BANK2          SYSCFG_UR8_MESAD_BANK2_Msk             /*!< Mass Erase Secured Area Disabled for bank 2 */

+

+/******************  Bit definition for SYSCFG_UR9 register  *******************/

+#define SYSCFG_UR9_WRPN_BANK2_Pos       (0U)

+#define SYSCFG_UR9_WRPN_BANK2_Msk       (0xFFUL << SYSCFG_UR9_WRPN_BANK2_Pos)  /*!< 0x000000FF */

+#define SYSCFG_UR9_WRPN_BANK2           SYSCFG_UR9_WRPN_BANK2_Msk              /*!< Write protection for flash bank 2 */

+#define SYSCFG_UR9_PABEG_BANK2_Pos      (16U)

+#define SYSCFG_UR9_PABEG_BANK2_Msk      (0xFFFUL << SYSCFG_UR9_PABEG_BANK2_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR9_PABEG_BANK2          SYSCFG_UR9_PABEG_BANK2_Msk             /*!< Protected area start address for bank 2 */

+

+/******************  Bit definition for SYSCFG_UR10 register  *******************/

+#define SYSCFG_UR10_PAEND_BANK2_Pos     (0U)

+#define SYSCFG_UR10_PAEND_BANK2_Msk     (0xFFFUL << SYSCFG_UR10_PAEND_BANK2_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR10_PAEND_BANK2         SYSCFG_UR10_PAEND_BANK2_Msk            /*!< Protected area end address for bank 2 */

+#define SYSCFG_UR10_SABEG_BANK2_Pos     (16U)

+#define SYSCFG_UR10_SABEG_BANK2_Msk     (0xFFFUL << SYSCFG_UR10_SABEG_BANK2_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR10_SABEG_BANK2         SYSCFG_UR10_SABEG_BANK2_Msk            /*!< Secured area start address for bank 2 */

+

+/******************  Bit definition for SYSCFG_UR11 register  *******************/

+#define SYSCFG_UR11_SAEND_BANK2_Pos     (0U)

+#define SYSCFG_UR11_SAEND_BANK2_Msk     (0xFFFUL << SYSCFG_UR11_SAEND_BANK2_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR11_SAEND_BANK2         SYSCFG_UR11_SAEND_BANK2_Msk            /*!< Secured area end address for bank 2 */

+#define SYSCFG_UR11_IWDG1M_Pos          (16U)

+#define SYSCFG_UR11_IWDG1M_Msk          (0x1UL << SYSCFG_UR11_IWDG1M_Pos)      /*!< 0x00010000 */

+#define SYSCFG_UR11_IWDG1M              SYSCFG_UR11_IWDG1M_Msk                 /*!< Independent Watchdog 1 mode (SW or HW) */

+

+/******************  Bit definition for SYSCFG_UR12 register  *******************/

+

+#define SYSCFG_UR12_SECURE_Pos          (16U)

+#define SYSCFG_UR12_SECURE_Msk          (0x1UL << SYSCFG_UR12_SECURE_Pos)      /*!< 0x00010000 */

+#define SYSCFG_UR12_SECURE              SYSCFG_UR12_SECURE_Msk                 /*!< Secure mode status */

+

+/******************  Bit definition for SYSCFG_UR13 register  *******************/

+#define SYSCFG_UR13_SDRS_Pos            (0U)

+#define SYSCFG_UR13_SDRS_Msk            (0x3UL << SYSCFG_UR13_SDRS_Pos)        /*!< 0x00000003 */

+#define SYSCFG_UR13_SDRS                SYSCFG_UR13_SDRS_Msk                   /*!< Secured DTCM RAM Size */

+#define SYSCFG_UR13_D1SBRST_Pos         (16U)

+#define SYSCFG_UR13_D1SBRST_Msk         (0x1UL << SYSCFG_UR13_D1SBRST_Pos)     /*!< 0x00010000 */

+#define SYSCFG_UR13_D1SBRST             SYSCFG_UR13_D1SBRST_Msk                /*!< D1 Standby reset */

+

+/******************  Bit definition for SYSCFG_UR14 register  *******************/

+#define SYSCFG_UR14_D1STPRST_Pos        (0U)

+#define SYSCFG_UR14_D1STPRST_Msk        (0x1UL << SYSCFG_UR14_D1STPRST_Pos)    /*!< 0x00000001 */

+#define SYSCFG_UR14_D1STPRST            SYSCFG_UR14_D1STPRST_Msk               /*!< D1 Stop Reset */

+

+/******************  Bit definition for SYSCFG_UR15 register  *******************/

+#define SYSCFG_UR15_FZIWDGSTB_Pos       (16U)

+#define SYSCFG_UR15_FZIWDGSTB_Msk       (0x1UL << SYSCFG_UR15_FZIWDGSTB_Pos)   /*!< 0x00010000 */

+#define SYSCFG_UR15_FZIWDGSTB           SYSCFG_UR15_FZIWDGSTB_Msk              /*!< Freeze independent watchdogs in Standby mode */

+

+/******************  Bit definition for SYSCFG_UR16 register  *******************/

+#define SYSCFG_UR16_FZIWDGSTP_Pos       (0U)

+#define SYSCFG_UR16_FZIWDGSTP_Msk       (0x1UL << SYSCFG_UR16_FZIWDGSTP_Pos)   /*!< 0x00000001 */

+#define SYSCFG_UR16_FZIWDGSTP           SYSCFG_UR16_FZIWDGSTP_Msk              /*!< Freeze independent watchdogs in Stop mode */

+#define SYSCFG_UR16_PKP_Pos             (16U)

+#define SYSCFG_UR16_PKP_Msk             (0x1UL << SYSCFG_UR16_PKP_Pos)         /*!< 0x00010000 */

+#define SYSCFG_UR16_PKP                 SYSCFG_UR16_PKP_Msk                    /*!< Private key programmed */

+

+/******************  Bit definition for SYSCFG_UR17 register  *******************/

+#define SYSCFG_UR17_IOHSLV_Pos          (0U)

+#define SYSCFG_UR17_IOHSLV_Msk          (0x1UL << SYSCFG_UR17_IOHSLV_Pos)      /*!< 0x00000001 */

+#define SYSCFG_UR17_IOHSLV              SYSCFG_UR17_IOHSLV_Msk                 /*!< I/O high speed / low voltage */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    TIM                                     */

+/*                                                                            */

+/******************************************************************************/

+#define TIM_BREAK_INPUT_SUPPORT             /*!<TIM Break input feature */

+

+/*******************  Bit definition for TIM_CR1 register  ********************/

+#define TIM_CR1_CEN_Pos           (0U)

+#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */

+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */

+#define TIM_CR1_UDIS_Pos          (1U)

+#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */

+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */

+#define TIM_CR1_URS_Pos           (2U)

+#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */

+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */

+#define TIM_CR1_OPM_Pos           (3U)

+#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */

+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */

+#define TIM_CR1_DIR_Pos           (4U)

+#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */

+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */

+

+#define TIM_CR1_CMS_Pos           (5U)

+#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */

+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */

+#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */

+#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */

+

+#define TIM_CR1_ARPE_Pos          (7U)

+#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */

+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */

+

+#define TIM_CR1_CKD_Pos           (8U)

+#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */

+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */

+#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */

+#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */

+

+#define TIM_CR1_UIFREMAP_Pos      (11U)

+#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */

+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */

+

+/*******************  Bit definition for TIM_CR2 register  ********************/

+#define TIM_CR2_CCPC_Pos          (0U)

+#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */

+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */

+#define TIM_CR2_CCUS_Pos          (2U)

+#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */

+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */

+#define TIM_CR2_CCDS_Pos          (3U)

+#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */

+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */

+

+#define TIM_CR2_MMS_Pos           (4U)

+#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */

+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */

+#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */

+#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */

+#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */

+

+#define TIM_CR2_TI1S_Pos          (7U)

+#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */

+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */

+#define TIM_CR2_OIS1_Pos          (8U)

+#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */

+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */

+#define TIM_CR2_OIS1N_Pos         (9U)

+#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */

+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */

+#define TIM_CR2_OIS2_Pos          (10U)

+#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */

+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */

+#define TIM_CR2_OIS2N_Pos         (11U)

+#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */

+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */

+#define TIM_CR2_OIS3_Pos          (12U)

+#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */

+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */

+#define TIM_CR2_OIS3N_Pos         (13U)

+#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */

+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */

+#define TIM_CR2_OIS4_Pos          (14U)

+#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */

+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */

+#define TIM_CR2_OIS5_Pos          (16U)

+#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */

+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */

+#define TIM_CR2_OIS6_Pos          (17U)

+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */

+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */

+

+#define TIM_CR2_MMS2_Pos          (20U)

+#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */

+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */

+#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */

+#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */

+#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */

+#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */

+

+/*******************  Bit definition for TIM_SMCR register  *******************/

+#define TIM_SMCR_SMS_Pos          (0U)

+#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */

+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */

+#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */

+#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */

+#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */

+#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */

+

+#define TIM_SMCR_TS_Pos           (4U)

+#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */

+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[4:0] bits (Trigger selection) */

+#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)                /*!< 0x00000010 */

+#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)                /*!< 0x00000020 */

+#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)                /*!< 0x00000040 */

+#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)                /*!< 0x00100000 */

+#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)                /*!< 0x00200000 */

+

+#define TIM_SMCR_MSM_Pos          (7U)

+#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */

+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */

+

+#define TIM_SMCR_ETF_Pos          (8U)

+#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */

+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */

+#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */

+#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */

+#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */

+#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */

+

+#define TIM_SMCR_ETPS_Pos         (12U)

+#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */

+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */

+#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */

+#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */

+

+#define TIM_SMCR_ECE_Pos          (14U)

+#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */

+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */

+#define TIM_SMCR_ETP_Pos          (15U)

+#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */

+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */

+

+/*******************  Bit definition for TIM_DIER register  *******************/

+#define TIM_DIER_UIE_Pos          (0U)

+#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */

+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */

+#define TIM_DIER_CC1IE_Pos        (1U)

+#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */

+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */

+#define TIM_DIER_CC2IE_Pos        (2U)

+#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */

+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */

+#define TIM_DIER_CC3IE_Pos        (3U)

+#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */

+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */

+#define TIM_DIER_CC4IE_Pos        (4U)

+#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */

+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */

+#define TIM_DIER_COMIE_Pos        (5U)

+#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */

+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */

+#define TIM_DIER_TIE_Pos          (6U)

+#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */

+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */

+#define TIM_DIER_BIE_Pos          (7U)

+#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */

+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */

+#define TIM_DIER_UDE_Pos          (8U)

+#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */

+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */

+#define TIM_DIER_CC1DE_Pos        (9U)

+#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */

+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */

+#define TIM_DIER_CC2DE_Pos        (10U)

+#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */

+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */

+#define TIM_DIER_CC3DE_Pos        (11U)

+#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */

+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */

+#define TIM_DIER_CC4DE_Pos        (12U)

+#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */

+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */

+#define TIM_DIER_COMDE_Pos        (13U)

+#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */

+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */

+#define TIM_DIER_TDE_Pos          (14U)

+#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */

+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */

+

+/********************  Bit definition for TIM_SR register  ********************/

+#define TIM_SR_UIF_Pos            (0U)

+#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */

+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */

+#define TIM_SR_CC1IF_Pos          (1U)

+#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */

+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */

+#define TIM_SR_CC2IF_Pos          (2U)

+#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */

+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */

+#define TIM_SR_CC3IF_Pos          (3U)

+#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */

+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */

+#define TIM_SR_CC4IF_Pos          (4U)

+#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */

+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */

+#define TIM_SR_COMIF_Pos          (5U)

+#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */

+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */

+#define TIM_SR_TIF_Pos            (6U)

+#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */

+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */

+#define TIM_SR_BIF_Pos            (7U)

+#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */

+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */

+#define TIM_SR_B2IF_Pos           (8U)

+#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */

+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break2 interrupt Flag */

+#define TIM_SR_CC1OF_Pos          (9U)

+#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */

+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */

+#define TIM_SR_CC2OF_Pos          (10U)

+#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */

+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */

+#define TIM_SR_CC3OF_Pos          (11U)

+#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */

+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */

+#define TIM_SR_CC4OF_Pos          (12U)

+#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */

+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */

+#define TIM_SR_CC5IF_Pos          (16U)

+#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */

+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */

+#define TIM_SR_CC6IF_Pos          (17U)

+#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */

+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */

+#define TIM_SR_SBIF_Pos           (13U)

+#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */

+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!< System Break Flag */

+

+/*******************  Bit definition for TIM_EGR register  ********************/

+#define TIM_EGR_UG_Pos            (0U)

+#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */

+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */

+#define TIM_EGR_CC1G_Pos          (1U)

+#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */

+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */

+#define TIM_EGR_CC2G_Pos          (2U)

+#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */

+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */

+#define TIM_EGR_CC3G_Pos          (3U)

+#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */

+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */

+#define TIM_EGR_CC4G_Pos          (4U)

+#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */

+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */

+#define TIM_EGR_COMG_Pos          (5U)

+#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */

+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */

+#define TIM_EGR_TG_Pos            (6U)

+#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */

+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */

+#define TIM_EGR_BG_Pos            (7U)

+#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */

+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */

+#define TIM_EGR_B2G_Pos           (8U)

+#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */

+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break Generation */

+

+

+/******************  Bit definition for TIM_CCMR1 register  *******************/

+#define TIM_CCMR1_CC1S_Pos        (0U)

+#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */

+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */

+#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */

+#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */

+

+#define TIM_CCMR1_OC1FE_Pos       (2U)

+#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */

+#define TIM_CCMR1_OC1PE_Pos       (3U)

+#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */

+

+#define TIM_CCMR1_OC1M_Pos        (4U)

+#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */

+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */

+#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */

+#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */

+#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */

+#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR1_OC1CE_Pos       (7U)

+#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */

+

+#define TIM_CCMR1_CC2S_Pos        (8U)

+#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */

+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */

+#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */

+#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */

+

+#define TIM_CCMR1_OC2FE_Pos       (10U)

+#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */

+#define TIM_CCMR1_OC2PE_Pos       (11U)

+#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */

+

+#define TIM_CCMR1_OC2M_Pos        (12U)

+#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */

+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */

+#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */

+#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */

+#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */

+#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */

+

+#define TIM_CCMR1_OC2CE_Pos       (15U)

+#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */

+

+/*----------------------------------------------------------------------------*/

+

+#define TIM_CCMR1_IC1PSC_Pos      (2U)

+#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */

+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */

+#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */

+

+#define TIM_CCMR1_IC1F_Pos        (4U)

+#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */

+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */

+#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */

+

+#define TIM_CCMR1_IC2PSC_Pos      (10U)

+#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */

+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */

+#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */

+

+#define TIM_CCMR1_IC2F_Pos        (12U)

+#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */

+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */

+#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */

+

+/******************  Bit definition for TIM_CCMR2 register  *******************/

+#define TIM_CCMR2_CC3S_Pos        (0U)

+#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */

+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */

+#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */

+#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */

+

+#define TIM_CCMR2_OC3FE_Pos       (2U)

+#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */

+#define TIM_CCMR2_OC3PE_Pos       (3U)

+#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */

+

+#define TIM_CCMR2_OC3M_Pos        (4U)

+#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */

+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */

+#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR2_OC3CE_Pos       (7U)

+#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */

+

+#define TIM_CCMR2_CC4S_Pos        (8U)

+#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */

+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */

+#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */

+#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */

+

+#define TIM_CCMR2_OC4FE_Pos       (10U)

+#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */

+#define TIM_CCMR2_OC4PE_Pos       (11U)

+#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */

+

+#define TIM_CCMR2_OC4M_Pos        (12U)

+#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */

+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */

+#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */

+

+#define TIM_CCMR2_OC4CE_Pos       (15U)

+#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */

+

+/*----------------------------------------------------------------------------*/

+

+#define TIM_CCMR2_IC3PSC_Pos      (2U)

+#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */

+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */

+#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */

+

+#define TIM_CCMR2_IC3F_Pos        (4U)

+#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */

+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */

+#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */

+

+#define TIM_CCMR2_IC4PSC_Pos      (10U)

+#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */

+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */

+#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */

+

+#define TIM_CCMR2_IC4F_Pos        (12U)

+#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */

+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */

+#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */

+

+/*******************  Bit definition for TIM_CCER register  *******************/

+#define TIM_CCER_CC1E_Pos         (0U)

+#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */

+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */

+#define TIM_CCER_CC1P_Pos         (1U)

+#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */

+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */

+#define TIM_CCER_CC1NE_Pos        (2U)

+#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */

+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */

+#define TIM_CCER_CC1NP_Pos        (3U)

+#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */

+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */

+#define TIM_CCER_CC2E_Pos         (4U)

+#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */

+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */

+#define TIM_CCER_CC2P_Pos         (5U)

+#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */

+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */

+#define TIM_CCER_CC2NE_Pos        (6U)

+#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */

+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */

+#define TIM_CCER_CC2NP_Pos        (7U)

+#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */

+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */

+#define TIM_CCER_CC3E_Pos         (8U)

+#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */

+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */

+#define TIM_CCER_CC3P_Pos         (9U)

+#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */

+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */

+#define TIM_CCER_CC3NE_Pos        (10U)

+#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */

+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */

+#define TIM_CCER_CC3NP_Pos        (11U)

+#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */

+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */

+#define TIM_CCER_CC4E_Pos         (12U)

+#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */

+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */

+#define TIM_CCER_CC4P_Pos         (13U)

+#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */

+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */

+#define TIM_CCER_CC4NP_Pos        (15U)

+#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */

+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */

+#define TIM_CCER_CC5E_Pos         (16U)

+#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */

+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */

+#define TIM_CCER_CC5P_Pos         (17U)

+#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */

+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */

+#define TIM_CCER_CC6E_Pos         (20U)

+#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */

+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */

+#define TIM_CCER_CC6P_Pos         (21U)

+#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */

+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */

+/*******************  Bit definition for TIM_CNT register  ********************/

+#define TIM_CNT_CNT_Pos           (0U)

+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */

+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */

+#define TIM_CNT_UIFCPY_Pos        (31U)

+#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */

+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy */

+/*******************  Bit definition for TIM_PSC register  ********************/

+#define TIM_PSC_PSC_Pos           (0U)

+#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */

+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */

+

+/*******************  Bit definition for TIM_ARR register  ********************/

+#define TIM_ARR_ARR_Pos           (0U)

+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */

+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */

+

+/*******************  Bit definition for TIM_RCR register  ********************/

+#define TIM_RCR_REP_Pos           (0U)

+#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                  /*!< 0x000000FF */

+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */

+

+/*******************  Bit definition for TIM_CCR1 register  *******************/

+#define TIM_CCR1_CCR1_Pos         (0U)

+#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */

+

+/*******************  Bit definition for TIM_CCR2 register  *******************/

+#define TIM_CCR2_CCR2_Pos         (0U)

+#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */

+

+/*******************  Bit definition for TIM_CCR3 register  *******************/

+#define TIM_CCR3_CCR3_Pos         (0U)

+#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */

+

+/*******************  Bit definition for TIM_CCR4 register  *******************/

+#define TIM_CCR4_CCR4_Pos         (0U)

+#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */

+

+/*******************  Bit definition for TIM_CCR5 register  *******************/

+#define TIM_CCR5_CCR5_Pos         (0U)

+#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */

+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */

+#define TIM_CCR5_GC5C1_Pos        (29U)

+#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */

+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */

+#define TIM_CCR5_GC5C2_Pos        (30U)

+#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */

+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */

+#define TIM_CCR5_GC5C3_Pos        (31U)

+#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */

+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */

+

+/*******************  Bit definition for TIM_CCR6 register  *******************/

+#define TIM_CCR6_CCR6_Pos         (0U)

+#define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */

+

+/*******************  Bit definition for TIM_BDTR register  *******************/

+#define TIM_BDTR_DTG_Pos          (0U)

+#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */

+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */

+#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */

+#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */

+#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */

+#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */

+#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */

+#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */

+#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */

+#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */

+

+#define TIM_BDTR_LOCK_Pos         (8U)

+#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */

+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */

+#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */

+#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */

+

+#define TIM_BDTR_OSSI_Pos         (10U)

+#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */

+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */

+#define TIM_BDTR_OSSR_Pos         (11U)

+#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */

+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */

+#define TIM_BDTR_BKE_Pos          (12U)

+#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */

+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break1 */

+#define TIM_BDTR_BKP_Pos          (13U)

+#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */

+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break1 */

+#define TIM_BDTR_AOE_Pos          (14U)

+#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */

+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */

+#define TIM_BDTR_MOE_Pos          (15U)

+#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */

+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */

+

+#define TIM_BDTR_BKF_Pos          (16U)

+#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */

+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break1 */

+#define TIM_BDTR_BK2F_Pos         (20U)

+#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */

+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break2 */

+

+#define TIM_BDTR_BK2E_Pos         (24U)

+#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */

+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break2 */

+#define TIM_BDTR_BK2P_Pos         (25U)

+#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */

+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */

+

+/*******************  Bit definition for TIM_DCR register  ********************/

+#define TIM_DCR_DBA_Pos           (0U)

+#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */

+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */

+#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */

+#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */

+#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */

+#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */

+#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */

+

+#define TIM_DCR_DBL_Pos           (8U)

+#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */

+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */

+#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */

+#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */

+#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */

+#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */

+#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */

+

+/*******************  Bit definition for TIM_DMAR register  *******************/

+#define TIM_DMAR_DMAB_Pos         (0U)

+#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */

+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */

+

+/******************  Bit definition for TIM_CCMR3 register  *******************/

+#define TIM_CCMR3_OC5FE_Pos       (2U)

+#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */

+#define TIM_CCMR3_OC5PE_Pos       (3U)

+#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */

+

+#define TIM_CCMR3_OC5M_Pos        (4U)

+#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */

+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */

+#define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR3_OC5CE_Pos       (7U)

+#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */

+

+#define TIM_CCMR3_OC6FE_Pos       (10U)

+#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 4 Fast enable */

+#define TIM_CCMR3_OC6PE_Pos       (11U)

+#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */

+

+#define TIM_CCMR3_OC6M_Pos        (12U)

+#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */

+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */

+#define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */

+

+#define TIM_CCMR3_OC6CE_Pos       (15U)

+#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 4 Clear Enable */

+/*******************  Bit definition for TIM1_AF1 register  *********************/

+#define TIM1_AF1_BKINE_Pos        (0U)

+#define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */

+#define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */

+#define TIM1_AF1_BKCMP1E_Pos      (1U)

+#define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */

+#define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM1_AF1_BKCMP2E_Pos      (2U)

+#define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */

+#define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit */

+#define TIM1_AF1_BKDF1BK0E_Pos    (8U)

+#define TIM1_AF1_BKDF1BK0E_Msk    (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)            /*!< 0x00000100 */

+#define TIM1_AF1_BKDF1BK0E        TIM1_AF1_BKDF1BK0E_Msk                       /*!<BKDF1BK0E Break input DFSDM Break 0 */

+#define TIM1_AF1_BKINP_Pos        (9U)

+#define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */

+#define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */

+#define TIM1_AF1_BKCMP1P_Pos      (10U)

+#define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */

+#define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM1_AF1_BKCMP2P_Pos      (11U)

+#define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */

+#define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */

+

+#define TIM1_AF1_ETRSEL_Pos       (14U)

+#define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */

+#define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */

+#define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00004000 */

+#define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00008000 */

+#define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00010000 */

+#define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM1_AF2 register  *********************/

+#define TIM1_AF2_BK2INE_Pos       (0U)

+#define TIM1_AF2_BK2INE_Msk       (0x1UL << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */

+#define TIM1_AF2_BK2INE           TIM1_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */

+#define TIM1_AF2_BK2CMP1E_Pos     (1U)

+#define TIM1_AF2_BK2CMP1E_Msk     (0x1UL << TIM1_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */

+#define TIM1_AF2_BK2CMP1E         TIM1_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */

+#define TIM1_AF2_BK2CMP2E_Pos     (2U)

+#define TIM1_AF2_BK2CMP2E_Msk     (0x1UL << TIM1_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */

+#define TIM1_AF2_BK2CMP2E         TIM1_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */

+#define TIM1_AF2_BK2DFBK1E_Pos    (8U)

+#define TIM1_AF2_BK2DFBK1E_Msk    (0x1UL << TIM1_AF2_BK2DFBK1E_Pos)            /*!< 0x00000100 */

+#define TIM1_AF2_BK2DFBK1E        TIM1_AF2_BK2DFBK1E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 1 */

+#define TIM1_AF2_BK2INP_Pos       (9U)

+#define TIM1_AF2_BK2INP_Msk       (0x1UL << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */

+#define TIM1_AF2_BK2INP           TIM1_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */

+#define TIM1_AF2_BK2CMP1P_Pos     (10U)

+#define TIM1_AF2_BK2CMP1P_Msk     (0x1UL << TIM1_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */

+#define TIM1_AF2_BK2CMP1P         TIM1_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */

+#define TIM1_AF2_BK2CMP2P_Pos     (11U)

+#define TIM1_AF2_BK2CMP2P_Msk     (0x1UL << TIM1_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */

+#define TIM1_AF2_BK2CMP2P         TIM1_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */

+

+/*******************  Bit definition for TIM_TISEL register  *********************/

+#define TIM_TISEL_TI1SEL_Pos      (0U)

+#define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */

+#define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/

+#define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000001 */

+#define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000002 */

+#define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000004 */

+#define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000008 */

+

+#define TIM_TISEL_TI2SEL_Pos      (8U)

+#define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */

+#define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/

+#define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000100 */

+#define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000200 */

+#define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000400 */

+#define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000800 */

+

+#define TIM_TISEL_TI3SEL_Pos      (16U)

+#define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */

+#define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/

+#define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00010000 */

+#define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00020000 */

+#define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00040000 */

+#define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00080000 */

+

+#define TIM_TISEL_TI4SEL_Pos      (24U)

+#define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */

+#define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/

+#define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x01000000 */

+#define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x02000000 */

+#define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x04000000 */

+#define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x08000000 */

+

+/*******************  Bit definition for TIM8_AF1 register  *********************/

+#define TIM8_AF1_BKINE_Pos        (0U)

+#define TIM8_AF1_BKINE_Msk        (0x1UL << TIM8_AF1_BKINE_Pos)                /*!< 0x00000001 */

+#define TIM8_AF1_BKINE            TIM8_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */

+#define TIM8_AF1_BKCMP1E_Pos      (1U)

+#define TIM8_AF1_BKCMP1E_Msk      (0x1UL << TIM8_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */

+#define TIM8_AF1_BKCMP1E          TIM8_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM8_AF1_BKCMP2E_Pos      (2U)

+#define TIM8_AF1_BKCMP2E_Msk      (0x1UL << TIM8_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */

+#define TIM8_AF1_BKCMP2E          TIM8_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM8_AF1_BKDFBK2E_Pos     (8U)

+#define TIM8_AF1_BKDFBK2E_Msk     (0x1UL << TIM8_AF1_BKDFBK2E_Pos)             /*!< 0x00000100 */

+#define TIM8_AF1_BKDFBK2E         TIM8_AF1_BKDFBK2E_Msk                        /*!<BKDFBK2E Break input DFSDM Break 2 */

+#define TIM8_AF1_BKINP_Pos        (9U)

+#define TIM8_AF1_BKINP_Msk        (0x1UL << TIM8_AF1_BKINP_Pos)                /*!< 0x00000200 */

+#define TIM8_AF1_BKINP            TIM8_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */

+#define TIM8_AF1_BKCMP1P_Pos      (10U)

+#define TIM8_AF1_BKCMP1P_Msk      (0x1UL << TIM8_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */

+#define TIM8_AF1_BKCMP1P          TIM8_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM8_AF1_BKCMP2P_Pos      (11U)

+#define TIM8_AF1_BKCMP2P_Msk      (0x1UL << TIM8_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */

+#define TIM8_AF1_BKCMP2P          TIM8_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */

+

+#define TIM8_AF1_ETRSEL_Pos       (14U)

+#define TIM8_AF1_ETRSEL_Msk       (0xFUL << TIM8_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */

+#define TIM8_AF1_ETRSEL           TIM8_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */

+#define TIM8_AF1_ETRSEL_0         (0x1UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00004000 */

+#define TIM8_AF1_ETRSEL_1         (0x2UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00008000 */

+#define TIM8_AF1_ETRSEL_2         (0x4UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00010000 */

+#define TIM8_AF1_ETRSEL_3         (0x8UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00020000 */

+/*******************  Bit definition for TIM8_AF2 register  *********************/

+#define TIM8_AF2_BK2INE_Pos       (0U)

+#define TIM8_AF2_BK2INE_Msk       (0x1UL << TIM8_AF2_BK2INE_Pos)               /*!< 0x00000001 */

+#define TIM8_AF2_BK2INE           TIM8_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */

+#define TIM8_AF2_BK2CMP1E_Pos     (1U)

+#define TIM8_AF2_BK2CMP1E_Msk     (0x1UL << TIM8_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */

+#define TIM8_AF2_BK2CMP1E         TIM8_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */

+#define TIM8_AF2_BK2CMP2E_Pos     (2U)

+#define TIM8_AF2_BK2CMP2E_Msk     (0x1UL << TIM8_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */

+#define TIM8_AF2_BK2CMP2E         TIM8_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */

+#define TIM8_AF2_BK2DFBK3E_Pos    (8U)

+#define TIM8_AF2_BK2DFBK3E_Msk    (0x1UL << TIM8_AF2_BK2DFBK3E_Pos)            /*!< 0x00000100 */

+#define TIM8_AF2_BK2DFBK3E        TIM8_AF2_BK2DFBK3E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 3 */

+#define TIM8_AF2_BK2INP_Pos       (9U)

+#define TIM8_AF2_BK2INP_Msk       (0x1UL << TIM8_AF2_BK2INP_Pos)               /*!< 0x00000200 */

+#define TIM8_AF2_BK2INP           TIM8_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */

+#define TIM8_AF2_BK2CMP1P_Pos     (10U)

+#define TIM8_AF2_BK2CMP1P_Msk     (0x1UL << TIM8_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */

+#define TIM8_AF2_BK2CMP1P         TIM8_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */

+#define TIM8_AF2_BK2CMP2P_Pos     (11U)

+#define TIM8_AF2_BK2CMP2P_Msk     (0x1UL << TIM8_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */

+#define TIM8_AF2_BK2CMP2P         TIM8_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */

+

+/*******************  Bit definition for TIM2_AF1 register  *********************/

+#define TIM2_AF1_ETRSEL_Pos      (14U)

+#define TIM2_AF1_ETRSEL_Msk      (0xFUL << TIM2_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM2_AF1_ETRSEL          TIM2_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */

+#define TIM2_AF1_ETRSEL_0        (0x1UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM2_AF1_ETRSEL_1        (0x2UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM2_AF1_ETRSEL_2        (0x4UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM2_AF1_ETRSEL_3        (0x8UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM3_AF1 register  *********************/

+#define TIM3_AF1_ETRSEL_Pos      (14U)

+#define TIM3_AF1_ETRSEL_Msk      (0xFUL << TIM3_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM3_AF1_ETRSEL          TIM3_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */

+#define TIM3_AF1_ETRSEL_0        (0x1UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM3_AF1_ETRSEL_1        (0x2UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM3_AF1_ETRSEL_2        (0x4UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM3_AF1_ETRSEL_3        (0x8UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM5_AF1 register  *********************/

+#define TIM5_AF1_ETRSEL_Pos      (14U)

+#define TIM5_AF1_ETRSEL_Msk      (0xFUL << TIM5_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM5_AF1_ETRSEL          TIM5_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */

+#define TIM5_AF1_ETRSEL_0        (0x1UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM5_AF1_ETRSEL_1        (0x2UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM5_AF1_ETRSEL_2        (0x4UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM5_AF1_ETRSEL_3        (0x8UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM15_AF1 register  *********************/

+#define TIM15_AF1_BKINE_Pos        (0U)

+#define TIM15_AF1_BKINE_Msk        (0x1UL << TIM15_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM15_AF1_BKINE            TIM15_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM15_AF1_BKCMP1E_Pos      (1U)

+#define TIM15_AF1_BKCMP1E_Msk      (0x1UL << TIM15_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM15_AF1_BKCMP1E          TIM15_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM15_AF1_BKCMP2E_Pos      (2U)

+#define TIM15_AF1_BKCMP2E_Msk      (0x1UL << TIM15_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM15_AF1_BKCMP2E          TIM15_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM15_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM15_AF1_BKDF1BK2E_Msk    (0x1UL << TIM15_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM15_AF1_BKDF1BK2E        TIM15_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[0] enable */

+#define TIM15_AF1_BKINP_Pos        (9U)

+#define TIM15_AF1_BKINP_Msk        (0x1UL << TIM15_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM15_AF1_BKINP            TIM15_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM15_AF1_BKCMP1P_Pos      (10U)

+#define TIM15_AF1_BKCMP1P_Msk      (0x1UL << TIM15_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM15_AF1_BKCMP1P          TIM15_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM15_AF1_BKCMP2P_Pos      (11U)

+#define TIM15_AF1_BKCMP2P_Msk      (0x1UL << TIM15_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM15_AF1_BKCMP2P          TIM15_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/*******************  Bit definition for TIM16_ register  *********************/

+#define TIM16_AF1_BKINE_Pos        (0U)

+#define TIM16_AF1_BKINE_Msk        (0x1UL << TIM16_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM16_AF1_BKINE            TIM16_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM16_AF1_BKCMP1E_Pos      (1U)

+#define TIM16_AF1_BKCMP1E_Msk      (0x1UL << TIM16_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM16_AF1_BKCMP1E          TIM16_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM16_AF1_BKCMP2E_Pos      (2U)

+#define TIM16_AF1_BKCMP2E_Msk      (0x1UL << TIM16_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM16_AF1_BKCMP2E          TIM16_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM16_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM16_AF1_BKDF1BK2E_Msk    (0x1UL << TIM16_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM16_AF1_BKDF1BK2E        TIM16_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[1] enable */

+#define TIM16_AF1_BKINP_Pos        (9U)

+#define TIM16_AF1_BKINP_Msk        (0x1UL << TIM16_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM16_AF1_BKINP            TIM16_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM16_AF1_BKCMP1P_Pos      (10U)

+#define TIM16_AF1_BKCMP1P_Msk      (0x1UL << TIM16_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM16_AF1_BKCMP1P          TIM16_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM16_AF1_BKCMP2P_Pos      (11U)

+#define TIM16_AF1_BKCMP2P_Msk      (0x1UL << TIM16_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM16_AF1_BKCMP2P          TIM16_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/*******************  Bit definition for TIM17_AF1 register  *********************/

+#define TIM17_AF1_BKINE_Pos        (0U)

+#define TIM17_AF1_BKINE_Msk        (0x1UL << TIM17_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM17_AF1_BKINE            TIM17_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM17_AF1_BKCMP1E_Pos      (1U)

+#define TIM17_AF1_BKCMP1E_Msk      (0x1UL << TIM17_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM17_AF1_BKCMP1E          TIM17_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM17_AF1_BKCMP2E_Pos      (2U)

+#define TIM17_AF1_BKCMP2E_Msk      (0x1UL << TIM17_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM17_AF1_BKCMP2E          TIM17_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM17_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM17_AF1_BKDF1BK2E_Msk    (0x1UL << TIM17_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM17_AF1_BKDF1BK2E        TIM17_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[2] enable */

+#define TIM17_AF1_BKINP_Pos        (9U)

+#define TIM17_AF1_BKINP_Msk        (0x1UL << TIM17_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM17_AF1_BKINP            TIM17_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM17_AF1_BKCMP1P_Pos      (10U)

+#define TIM17_AF1_BKCMP1P_Msk      (0x1UL << TIM17_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM17_AF1_BKCMP1P          TIM17_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM17_AF1_BKCMP2P_Pos      (11U)

+#define TIM17_AF1_BKCMP2P_Msk      (0x1UL << TIM17_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM17_AF1_BKCMP2P          TIM17_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Low Power Timer (LPTTIM)                           */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for LPTIM_ISR register  *******************/

+#define LPTIM_ISR_CMPM_Pos          (0U)

+#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */

+#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */

+#define LPTIM_ISR_ARRM_Pos          (1U)

+#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */

+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */

+#define LPTIM_ISR_EXTTRIG_Pos       (2U)

+#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */

+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */

+#define LPTIM_ISR_CMPOK_Pos         (3U)

+#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */

+#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */

+#define LPTIM_ISR_ARROK_Pos         (4U)

+#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */

+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */

+#define LPTIM_ISR_UP_Pos            (5U)

+#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */

+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */

+#define LPTIM_ISR_DOWN_Pos          (6U)

+#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */

+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */

+

+/******************  Bit definition for LPTIM_ICR register  *******************/

+#define LPTIM_ICR_CMPMCF_Pos        (0U)

+#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */

+#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */

+#define LPTIM_ICR_ARRMCF_Pos        (1U)

+#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */

+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */

+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)

+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */

+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */

+#define LPTIM_ICR_CMPOKCF_Pos       (3U)

+#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */

+#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */

+#define LPTIM_ICR_ARROKCF_Pos       (4U)

+#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */

+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */

+#define LPTIM_ICR_UPCF_Pos          (5U)

+#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */

+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */

+#define LPTIM_ICR_DOWNCF_Pos        (6U)

+#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */

+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */

+

+/******************  Bit definition for LPTIM_IER register ********************/

+#define LPTIM_IER_CMPMIE_Pos        (0U)

+#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */

+#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */

+#define LPTIM_IER_ARRMIE_Pos        (1U)

+#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */

+#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */

+#define LPTIM_IER_EXTTRIGIE_Pos     (2U)

+#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */

+#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */

+#define LPTIM_IER_CMPOKIE_Pos       (3U)

+#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */

+#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */

+#define LPTIM_IER_ARROKIE_Pos       (4U)

+#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */

+#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */

+#define LPTIM_IER_UPIE_Pos          (5U)

+#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */

+#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */

+#define LPTIM_IER_DOWNIE_Pos        (6U)

+#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */

+#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */

+

+/******************  Bit definition for LPTIM_CFGR register *******************/

+#define LPTIM_CFGR_CKSEL_Pos        (0U)

+#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */

+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */

+

+#define LPTIM_CFGR_CKPOL_Pos        (1U)

+#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */

+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */

+#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */

+#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */

+

+#define LPTIM_CFGR_CKFLT_Pos        (3U)

+#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */

+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */

+#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */

+#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */

+

+#define LPTIM_CFGR_TRGFLT_Pos       (6U)

+#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */

+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */

+#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */

+#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */

+

+#define LPTIM_CFGR_PRESC_Pos        (9U)

+#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */

+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */

+#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */

+#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */

+#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */

+

+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)

+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */

+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */

+#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */

+#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */

+#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */

+

+#define LPTIM_CFGR_TRIGEN_Pos       (17U)

+#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */

+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */

+#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */

+#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */

+

+#define LPTIM_CFGR_TIMOUT_Pos       (19U)

+#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */

+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */

+#define LPTIM_CFGR_WAVE_Pos         (20U)

+#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */

+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */

+#define LPTIM_CFGR_WAVPOL_Pos       (21U)

+#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */

+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */

+#define LPTIM_CFGR_PRELOAD_Pos      (22U)

+#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */

+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */

+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)

+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */

+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */

+#define LPTIM_CFGR_ENC_Pos          (24U)

+#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */

+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */

+

+/******************  Bit definition for LPTIM_CR register  ********************/

+#define LPTIM_CR_ENABLE_Pos         (0U)

+#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */

+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */

+#define LPTIM_CR_SNGSTRT_Pos        (1U)

+#define LPTIM_CR_SNGSTRT_Msk        (0x40001UL << LPTIM_CR_SNGSTRT_Pos)        /*!< 0x00080002 */

+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */

+#define LPTIM_CR_CNTSTRT_Pos        (2U)

+#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */

+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */

+#define LPTIM_CR_COUNTRST_Pos       (3U)

+#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */

+#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Timer Counter reset in synchronous mode*/

+#define LPTIM_CR_RSTARE_Pos         (4U)

+#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */

+#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Timer Counter reset after read enable (asynchronously)*/

+

+

+/******************  Bit definition for LPTIM_CMP register  *******************/

+#define LPTIM_CMP_CMP_Pos           (0U)

+#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */

+

+/******************  Bit definition for LPTIM_ARR register  *******************/

+#define LPTIM_ARR_ARR_Pos           (0U)

+#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */

+

+/******************  Bit definition for LPTIM_CNT register  *******************/

+#define LPTIM_CNT_CNT_Pos           (0U)

+#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */

+

+/******************  Bit definition for LPTIM_CFGR2 register  *****************/

+#define LPTIM_CFGR2_IN1SEL_Pos      (0U)

+#define LPTIM_CFGR2_IN1SEL_Msk      (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000003 */

+#define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< IN1SEL[1:0] bits (Remap selection) */

+#define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000001 */

+#define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000002 */

+#define LPTIM_CFGR2_IN2SEL_Pos      (4U)

+#define LPTIM_CFGR2_IN2SEL_Msk      (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000030 */

+#define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< IN2SEL[5:4] bits (Remap selection) */

+#define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000010 */

+#define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000020 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      Analog Comparators (COMP)                             */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for COMP_SR register  ********************/

+#define COMP_SR_C1VAL_Pos            (0U)

+#define COMP_SR_C1VAL_Msk            (0x1UL << COMP_SR_C1VAL_Pos)              /*!< 0x00000001 */

+#define COMP_SR_C1VAL                COMP_SR_C1VAL_Msk

+#define COMP_SR_C2VAL_Pos            (1U)

+#define COMP_SR_C2VAL_Msk            (0x1UL << COMP_SR_C2VAL_Pos)              /*!< 0x00000002 */

+#define COMP_SR_C2VAL                COMP_SR_C2VAL_Msk

+#define COMP_SR_C1IF_Pos             (16U)

+#define COMP_SR_C1IF_Msk             (0x1UL << COMP_SR_C1IF_Pos)               /*!< 0x00010000 */

+#define COMP_SR_C1IF                 COMP_SR_C1IF_Msk

+#define COMP_SR_C2IF_Pos             (17U)

+#define COMP_SR_C2IF_Msk             (0x1UL << COMP_SR_C2IF_Pos)               /*!< 0x00020000 */

+#define COMP_SR_C2IF                 COMP_SR_C2IF_Msk

+/*******************  Bit definition for COMP_ICFR register  ********************/

+#define COMP_ICFR_C1IF_Pos           (16U)

+#define COMP_ICFR_C1IF_Msk           (0x1UL << COMP_ICFR_C1IF_Pos)             /*!< 0x00010000 */

+#define COMP_ICFR_C1IF               COMP_ICFR_C1IF_Msk

+#define COMP_ICFR_C2IF_Pos           (17U)

+#define COMP_ICFR_C2IF_Msk           (0x1UL << COMP_ICFR_C2IF_Pos)             /*!< 0x00020000 */

+#define COMP_ICFR_C2IF               COMP_ICFR_C2IF_Msk

+/*******************  Bit definition for COMP_OR register  ********************/

+#define COMP_OR_AFOPA6_Pos           (0U)

+#define COMP_OR_AFOPA6_Msk           (0x1UL << COMP_OR_AFOPA6_Pos)             /*!< 0x00000001 */

+#define COMP_OR_AFOPA6               COMP_OR_AFOPA6_Msk

+#define COMP_OR_AFOPA8_Pos           (1U)

+#define COMP_OR_AFOPA8_Msk           (0x1UL << COMP_OR_AFOPA8_Pos)             /*!< 0x00000002 */

+#define COMP_OR_AFOPA8               COMP_OR_AFOPA8_Msk

+#define COMP_OR_AFOPB12_Pos          (2U)

+#define COMP_OR_AFOPB12_Msk          (0x1UL << COMP_OR_AFOPB12_Pos)            /*!< 0x00000004 */

+#define COMP_OR_AFOPB12              COMP_OR_AFOPB12_Msk

+#define COMP_OR_AFOPE6_Pos           (3U)

+#define COMP_OR_AFOPE6_Msk           (0x1UL << COMP_OR_AFOPE6_Pos)             /*!< 0x00000008 */

+#define COMP_OR_AFOPE6               COMP_OR_AFOPE6_Msk

+#define COMP_OR_AFOPE15_Pos          (4U)

+#define COMP_OR_AFOPE15_Msk          (0x1UL << COMP_OR_AFOPE15_Pos)            /*!< 0x00000010 */

+#define COMP_OR_AFOPE15              COMP_OR_AFOPE15_Msk

+#define COMP_OR_AFOPG2_Pos           (5U)

+#define COMP_OR_AFOPG2_Msk           (0x1UL << COMP_OR_AFOPG2_Pos)             /*!< 0x00000020 */

+#define COMP_OR_AFOPG2               COMP_OR_AFOPG2_Msk

+#define COMP_OR_AFOPG3_Pos           (6U)

+#define COMP_OR_AFOPG3_Msk           (0x1UL << COMP_OR_AFOPG3_Pos)             /*!< 0x00000040 */

+#define COMP_OR_AFOPG3               COMP_OR_AFOPG3_Msk

+#define COMP_OR_AFOPG4_Pos           (7U)

+#define COMP_OR_AFOPG4_Msk           (0x1UL << COMP_OR_AFOPG4_Pos)             /*!< 0x00000080 */

+#define COMP_OR_AFOPG4               COMP_OR_AFOPG4_Msk

+#define COMP_OR_AFOPI1_Pos           (8U)

+#define COMP_OR_AFOPI1_Msk           (0x1UL << COMP_OR_AFOPI1_Pos)             /*!< 0x00000100 */

+#define COMP_OR_AFOPI1               COMP_OR_AFOPI1_Msk

+#define COMP_OR_AFOPI4_Pos           (9U)

+#define COMP_OR_AFOPI4_Msk           (0x1UL << COMP_OR_AFOPI4_Pos)             /*!< 0x00000200 */

+#define COMP_OR_AFOPI4               COMP_OR_AFOPI4_Msk

+#define COMP_OR_AFOPK2_Pos           (10U)

+#define COMP_OR_AFOPK2_Msk           (0x1UL << COMP_OR_AFOPK2_Pos)             /*!< 0x00000400 */

+#define COMP_OR_AFOPK2               COMP_OR_AFOPK2_Msk

+

+/*!< ******************  Bit definition for COMP_CFGRx register  ********************/

+#define COMP_CFGRx_EN_Pos            (0U)

+#define COMP_CFGRx_EN_Msk            (0x1UL << COMP_CFGRx_EN_Pos)              /*!< 0x00000001 */

+#define COMP_CFGRx_EN                COMP_CFGRx_EN_Msk                         /*!< COMPx enable bit                     */

+#define COMP_CFGRx_BRGEN_Pos         (1U)

+#define COMP_CFGRx_BRGEN_Msk         (0x1UL << COMP_CFGRx_BRGEN_Pos)           /*!< 0x00000002 */

+#define COMP_CFGRx_BRGEN             COMP_CFGRx_BRGEN_Msk                      /*!< COMPx Scaler bridge enable           */

+#define COMP_CFGRx_SCALEN_Pos        (2U)

+#define COMP_CFGRx_SCALEN_Msk        (0x1UL << COMP_CFGRx_SCALEN_Pos)          /*!< 0x00000004 */

+#define COMP_CFGRx_SCALEN            COMP_CFGRx_SCALEN_Msk                     /*!< COMPx Voltage scaler enable bit      */

+#define COMP_CFGRx_POLARITY_Pos      (3U)

+#define COMP_CFGRx_POLARITY_Msk      (0x1UL << COMP_CFGRx_POLARITY_Pos)        /*!< 0x00000008 */

+#define COMP_CFGRx_POLARITY          COMP_CFGRx_POLARITY_Msk                   /*!< COMPx  polarity selection bit        */

+#define COMP_CFGRx_WINMODE_Pos       (4U)

+#define COMP_CFGRx_WINMODE_Msk       (0x1UL << COMP_CFGRx_WINMODE_Pos)         /*!< 0x00000010 */

+#define COMP_CFGRx_WINMODE           COMP_CFGRx_WINMODE_Msk                    /*!< COMPx Windows mode selection bit     */

+#define COMP_CFGRx_ITEN_Pos          (6U)

+#define COMP_CFGRx_ITEN_Msk          (0x1UL << COMP_CFGRx_ITEN_Pos)            /*!< 0x00000040 */

+#define COMP_CFGRx_ITEN              COMP_CFGRx_ITEN_Msk                       /*!< COMPx  interrupt enable              */

+#define COMP_CFGRx_HYST_Pos          (8U)

+#define COMP_CFGRx_HYST_Msk          (0x3UL << COMP_CFGRx_HYST_Pos)            /*!< 0x00000300 */

+#define COMP_CFGRx_HYST              COMP_CFGRx_HYST_Msk                       /*!< COMPx  hysteresis selection bits     */

+#define COMP_CFGRx_HYST_0            (0x1UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000100 */

+#define COMP_CFGRx_HYST_1            (0x2UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000200 */

+#define COMP_CFGRx_PWRMODE_Pos       (12U)

+#define COMP_CFGRx_PWRMODE_Msk       (0x3UL << COMP_CFGRx_PWRMODE_Pos)         /*!< 0x00003000 */

+#define COMP_CFGRx_PWRMODE           COMP_CFGRx_PWRMODE_Msk                    /*!< COMPx Power Mode of the comparator   */

+#define COMP_CFGRx_PWRMODE_0         (0x1UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00001000 */

+#define COMP_CFGRx_PWRMODE_1         (0x2UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00002000 */

+#define COMP_CFGRx_INMSEL_Pos        (16U)

+#define COMP_CFGRx_INMSEL_Msk        (0x7UL << COMP_CFGRx_INMSEL_Pos)          /*!< 0x00070000 */

+#define COMP_CFGRx_INMSEL            COMP_CFGRx_INMSEL_Msk                     /*!< COMPx  input minus selection bit  */

+#define COMP_CFGRx_INMSEL_0          (0x1UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00010000 */

+#define COMP_CFGRx_INMSEL_1          (0x2UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00020000 */

+#define COMP_CFGRx_INMSEL_2          (0x4UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00040000 */

+#define COMP_CFGRx_INPSEL_Pos        (20U)

+#define COMP_CFGRx_INPSEL_Msk        (0x1UL << COMP_CFGRx_INPSEL_Pos)          /*!< 0x00100000 */

+#define COMP_CFGRx_INPSEL            COMP_CFGRx_INPSEL_Msk                     /*!< COMPx  input plus selection bit       */

+#define COMP_CFGRx_BLANKING_Pos      (24U)

+#define COMP_CFGRx_BLANKING_Msk      (0xFUL << COMP_CFGRx_BLANKING_Pos)        /*!< 0x0F000000 */

+#define COMP_CFGRx_BLANKING          COMP_CFGRx_BLANKING_Msk                   /*!< COMPx  blanking source selection bits */

+#define COMP_CFGRx_BLANKING_0        (0x1UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x01000000 */

+#define COMP_CFGRx_BLANKING_1        (0x2UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x02000000 */

+#define COMP_CFGRx_BLANKING_2        (0x4UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x04000000 */

+#define COMP_CFGRx_LOCK_Pos          (31U)

+#define COMP_CFGRx_LOCK_Msk          (0x1UL << COMP_CFGRx_LOCK_Pos)            /*!< 0x80000000 */

+#define COMP_CFGRx_LOCK              COMP_CFGRx_LOCK_Msk                       /*!< COMPx Lock Bit                        */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for USART_CR1 register  *******************/

+#define USART_CR1_UE_Pos                (0U)

+#define USART_CR1_UE_Msk                (0x1UL << USART_CR1_UE_Pos)            /*!< 0x00000001 */

+#define USART_CR1_UE                    USART_CR1_UE_Msk                       /*!< USART Enable */

+#define USART_CR1_UESM_Pos              (1U)

+#define USART_CR1_UESM_Msk              (0x1UL << USART_CR1_UESM_Pos)          /*!< 0x00000002 */

+#define USART_CR1_UESM                  USART_CR1_UESM_Msk                     /*!< USART Enable in STOP Mode */

+#define USART_CR1_RE_Pos                (2U)

+#define USART_CR1_RE_Msk                (0x1UL << USART_CR1_RE_Pos)            /*!< 0x00000004 */

+#define USART_CR1_RE                    USART_CR1_RE_Msk                       /*!< Receiver Enable */

+#define USART_CR1_TE_Pos                (3U)

+#define USART_CR1_TE_Msk                (0x1UL << USART_CR1_TE_Pos)            /*!< 0x00000008 */

+#define USART_CR1_TE                    USART_CR1_TE_Msk                       /*!< Transmitter Enable */

+#define USART_CR1_IDLEIE_Pos            (4U)

+#define USART_CR1_IDLEIE_Msk            (0x1UL << USART_CR1_IDLEIE_Pos)        /*!< 0x00000010 */

+#define USART_CR1_IDLEIE                USART_CR1_IDLEIE_Msk                   /*!< IDLE Interrupt Enable */

+#define USART_CR1_RXNEIE_RXFNEIE_Pos    (5U)

+#define USART_CR1_RXNEIE_RXFNEIE_Msk    (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */

+#define USART_CR1_RXNEIE_RXFNEIE        USART_CR1_RXNEIE_RXFNEIE_Msk           /*!< RXNE and RX FIFO Not Empty Interrupt Enable */

+#define USART_CR1_TCIE_Pos              (6U)

+#define USART_CR1_TCIE_Msk              (0x1UL << USART_CR1_TCIE_Pos)          /*!< 0x00000040 */

+#define USART_CR1_TCIE                  USART_CR1_TCIE_Msk                     /*!< Transmission Complete Interrupt Enable */

+#define USART_CR1_TXEIE_TXFNFIE_Pos     (7U)

+#define USART_CR1_TXEIE_TXFNFIE_Msk     (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */

+#define USART_CR1_TXEIE_TXFNFIE         USART_CR1_TXEIE_TXFNFIE_Msk            /*!< TXE and TX FIFO Not Full Interrupt Enable */

+#define USART_CR1_PEIE_Pos              (8U)

+#define USART_CR1_PEIE_Msk              (0x1UL << USART_CR1_PEIE_Pos)          /*!< 0x00000100 */

+#define USART_CR1_PEIE                  USART_CR1_PEIE_Msk                     /*!< PE Interrupt Enable */

+#define USART_CR1_PS_Pos                (9U)

+#define USART_CR1_PS_Msk                (0x1UL << USART_CR1_PS_Pos)            /*!< 0x00000200 */

+#define USART_CR1_PS                    USART_CR1_PS_Msk                       /*!< Parity Selection */

+#define USART_CR1_PCE_Pos               (10U)

+#define USART_CR1_PCE_Msk               (0x1UL << USART_CR1_PCE_Pos)           /*!< 0x00000400 */

+#define USART_CR1_PCE                   USART_CR1_PCE_Msk                      /*!< Parity Control Enable */

+#define USART_CR1_WAKE_Pos              (11U)

+#define USART_CR1_WAKE_Msk              (0x1UL << USART_CR1_WAKE_Pos)          /*!< 0x00000800 */

+#define USART_CR1_WAKE                  USART_CR1_WAKE_Msk                     /*!< Receiver Wakeup method */

+#define USART_CR1_M_Pos                 (12U)

+#define USART_CR1_M_Msk                 (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */

+#define USART_CR1_M                     USART_CR1_M_Msk                        /*!< Word length */

+#define USART_CR1_M0_Pos                (12U)

+#define USART_CR1_M0_Msk                (0x1UL << USART_CR1_M0_Pos)            /*!< 0x00001000 */

+#define USART_CR1_M0                    USART_CR1_M0_Msk                       /*!< Word length - Bit 0 */

+#define USART_CR1_MME_Pos               (13U)

+#define USART_CR1_MME_Msk               (0x1UL << USART_CR1_MME_Pos)           /*!< 0x00002000 */

+#define USART_CR1_MME                   USART_CR1_MME_Msk                      /*!< Mute Mode Enable */

+#define USART_CR1_CMIE_Pos              (14U)

+#define USART_CR1_CMIE_Msk              (0x1UL << USART_CR1_CMIE_Pos)          /*!< 0x00004000 */

+#define USART_CR1_CMIE                  USART_CR1_CMIE_Msk                     /*!< Character match interrupt enable */

+#define USART_CR1_OVER8_Pos             (15U)

+#define USART_CR1_OVER8_Msk             (0x1UL << USART_CR1_OVER8_Pos)         /*!< 0x00008000 */

+#define USART_CR1_OVER8                 USART_CR1_OVER8_Msk                    /*!< Oversampling by 8-bit or 16-bit mode */

+#define USART_CR1_DEDT_Pos              (16U)

+#define USART_CR1_DEDT_Msk              (0x1FUL << USART_CR1_DEDT_Pos)         /*!< 0x001F0000 */

+#define USART_CR1_DEDT                  USART_CR1_DEDT_Msk                     /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */

+#define USART_CR1_DEDT_0                (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */

+#define USART_CR1_DEDT_1                (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */

+#define USART_CR1_DEDT_2                (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */

+#define USART_CR1_DEDT_3                (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */

+#define USART_CR1_DEDT_4                (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */

+#define USART_CR1_DEAT_Pos              (21U)

+#define USART_CR1_DEAT_Msk              (0x1FUL << USART_CR1_DEAT_Pos)         /*!< 0x03E00000 */

+#define USART_CR1_DEAT                  USART_CR1_DEAT_Msk                     /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */

+#define USART_CR1_DEAT_0                (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */

+#define USART_CR1_DEAT_1                (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */

+#define USART_CR1_DEAT_2                (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */

+#define USART_CR1_DEAT_3                (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */

+#define USART_CR1_DEAT_4                (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */

+#define USART_CR1_RTOIE_Pos             (26U)

+#define USART_CR1_RTOIE_Msk             (0x1UL << USART_CR1_RTOIE_Pos)         /*!< 0x04000000 */

+#define USART_CR1_RTOIE                 USART_CR1_RTOIE_Msk                    /*!< Receive Time Out interrupt enable */

+#define USART_CR1_EOBIE_Pos             (27U)

+#define USART_CR1_EOBIE_Msk             (0x1UL << USART_CR1_EOBIE_Pos)         /*!< 0x08000000 */

+#define USART_CR1_EOBIE                 USART_CR1_EOBIE_Msk                    /*!< End of Block interrupt enable */

+#define USART_CR1_M1_Pos                (28U)

+#define USART_CR1_M1_Msk                (0x1UL << USART_CR1_M1_Pos)            /*!< 0x10000000 */

+#define USART_CR1_M1                    USART_CR1_M1_Msk                       /*!< Word length - Bit 1 */

+#define USART_CR1_FIFOEN_Pos            (29U)

+#define USART_CR1_FIFOEN_Msk            (0x1UL << USART_CR1_FIFOEN_Pos)        /*!< 0x20000000 */

+#define USART_CR1_FIFOEN                USART_CR1_FIFOEN_Msk                   /*!< FIFO mode enable */

+#define USART_CR1_TXFEIE_Pos            (30U)

+#define USART_CR1_TXFEIE_Msk            (0x1UL << USART_CR1_TXFEIE_Pos)        /*!< 0x40000000 */

+#define USART_CR1_TXFEIE                USART_CR1_TXFEIE_Msk                   /*!< TXFIFO empty interrupt enable */

+#define USART_CR1_RXFFIE_Pos            (31U)

+#define USART_CR1_RXFFIE_Msk            (0x1UL << USART_CR1_RXFFIE_Pos)        /*!< 0x80000000 */

+#define USART_CR1_RXFFIE                USART_CR1_RXFFIE_Msk                   /*!< RXFIFO Full interrupt enable */

+

+/* Legacy define */

+#define  USART_CR1_RXNEIE  USART_CR1_RXNEIE_RXFNEIE

+#define  USART_CR1_TXEIE   USART_CR1_TXEIE_TXFNFIE

+

+/******************  Bit definition for USART_CR2 register  *******************/

+#define USART_CR2_SLVEN_Pos             (0U)

+#define USART_CR2_SLVEN_Msk             (0x1UL << USART_CR2_SLVEN_Pos)         /*!< 0x00000001 */

+#define USART_CR2_SLVEN                 USART_CR2_SLVEN_Msk                    /*!< Synchronous Slave mode Enable */

+#define USART_CR2_DIS_NSS_Pos           (3U)

+#define USART_CR2_DIS_NSS_Msk           (0x1UL << USART_CR2_DIS_NSS_Pos)       /*!< 0x00000008 */

+#define USART_CR2_DIS_NSS               USART_CR2_DIS_NSS_Msk                  /*!< Negative Slave Select (NSS) pin management */

+#define USART_CR2_ADDM7_Pos             (4U)

+#define USART_CR2_ADDM7_Msk             (0x1UL << USART_CR2_ADDM7_Pos)         /*!< 0x00000010 */

+#define USART_CR2_ADDM7                 USART_CR2_ADDM7_Msk                    /*!< 7-bit or 4-bit Address Detection */

+#define USART_CR2_LBDL_Pos              (5U)

+#define USART_CR2_LBDL_Msk              (0x1UL << USART_CR2_LBDL_Pos)          /*!< 0x00000020 */

+#define USART_CR2_LBDL                  USART_CR2_LBDL_Msk                     /*!< LIN Break Detection Length */

+#define USART_CR2_LBDIE_Pos             (6U)

+#define USART_CR2_LBDIE_Msk             (0x1UL << USART_CR2_LBDIE_Pos)         /*!< 0x00000040 */

+#define USART_CR2_LBDIE                 USART_CR2_LBDIE_Msk                    /*!< LIN Break Detection Interrupt Enable */

+#define USART_CR2_LBCL_Pos              (8U)

+#define USART_CR2_LBCL_Msk              (0x1UL << USART_CR2_LBCL_Pos)          /*!< 0x00000100 */

+#define USART_CR2_LBCL                  USART_CR2_LBCL_Msk                     /*!< Last Bit Clock pulse */

+#define USART_CR2_CPHA_Pos              (9U)

+#define USART_CR2_CPHA_Msk              (0x1UL << USART_CR2_CPHA_Pos)          /*!< 0x00000200 */

+#define USART_CR2_CPHA                  USART_CR2_CPHA_Msk                     /*!< Clock Phase */

+#define USART_CR2_CPOL_Pos              (10U)

+#define USART_CR2_CPOL_Msk              (0x1UL << USART_CR2_CPOL_Pos)          /*!< 0x00000400 */

+#define USART_CR2_CPOL                  USART_CR2_CPOL_Msk                     /*!< Clock Polarity */

+#define USART_CR2_CLKEN_Pos             (11U)

+#define USART_CR2_CLKEN_Msk             (0x1UL << USART_CR2_CLKEN_Pos)         /*!< 0x00000800 */

+#define USART_CR2_CLKEN                 USART_CR2_CLKEN_Msk                    /*!< Clock Enable */

+#define USART_CR2_STOP_Pos              (12U)

+#define USART_CR2_STOP_Msk              (0x3UL << USART_CR2_STOP_Pos)          /*!< 0x00003000 */

+#define USART_CR2_STOP                  USART_CR2_STOP_Msk                     /*!< STOP[1:0] bits (STOP bits) */

+#define USART_CR2_STOP_0                (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */

+#define USART_CR2_STOP_1                (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */

+#define USART_CR2_LINEN_Pos             (14U)

+#define USART_CR2_LINEN_Msk             (0x1UL << USART_CR2_LINEN_Pos)         /*!< 0x00004000 */

+#define USART_CR2_LINEN                 USART_CR2_LINEN_Msk                    /*!< LIN mode enable */

+#define USART_CR2_SWAP_Pos              (15U)

+#define USART_CR2_SWAP_Msk              (0x1UL << USART_CR2_SWAP_Pos)          /*!< 0x00008000 */

+#define USART_CR2_SWAP                  USART_CR2_SWAP_Msk                     /*!< SWAP TX/RX pins */

+#define USART_CR2_RXINV_Pos             (16U)

+#define USART_CR2_RXINV_Msk             (0x1UL << USART_CR2_RXINV_Pos)         /*!< 0x00010000 */

+#define USART_CR2_RXINV                 USART_CR2_RXINV_Msk                    /*!< RX pin active level inversion */

+#define USART_CR2_TXINV_Pos             (17U)

+#define USART_CR2_TXINV_Msk             (0x1UL << USART_CR2_TXINV_Pos)         /*!< 0x00020000 */

+#define USART_CR2_TXINV                 USART_CR2_TXINV_Msk                    /*!< TX pin active level inversion */

+#define USART_CR2_DATAINV_Pos           (18U)

+#define USART_CR2_DATAINV_Msk           (0x1UL << USART_CR2_DATAINV_Pos)       /*!< 0x00040000 */

+#define USART_CR2_DATAINV               USART_CR2_DATAINV_Msk                  /*!< Binary data inversion */

+#define USART_CR2_MSBFIRST_Pos          (19U)

+#define USART_CR2_MSBFIRST_Msk          (0x1UL << USART_CR2_MSBFIRST_Pos)      /*!< 0x00080000 */

+#define USART_CR2_MSBFIRST              USART_CR2_MSBFIRST_Msk                 /*!< Most Significant Bit First */

+#define USART_CR2_ABREN_Pos             (20U)

+#define USART_CR2_ABREN_Msk             (0x1UL << USART_CR2_ABREN_Pos)         /*!< 0x00100000 */

+#define USART_CR2_ABREN                 USART_CR2_ABREN_Msk                    /*!< Auto Baud-Rate Enable*/

+#define USART_CR2_ABRMODE_Pos           (21U)

+#define USART_CR2_ABRMODE_Msk           (0x3UL << USART_CR2_ABRMODE_Pos)       /*!< 0x00600000 */

+#define USART_CR2_ABRMODE               USART_CR2_ABRMODE_Msk                  /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */

+#define USART_CR2_ABRMODE_0             (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */

+#define USART_CR2_ABRMODE_1             (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */

+#define USART_CR2_RTOEN_Pos             (23U)

+#define USART_CR2_RTOEN_Msk             (0x1UL << USART_CR2_RTOEN_Pos)         /*!< 0x00800000 */

+#define USART_CR2_RTOEN                 USART_CR2_RTOEN_Msk                    /*!< Receiver Time-Out enable */

+#define USART_CR2_ADD_Pos               (24U)

+#define USART_CR2_ADD_Msk               (0xFFUL << USART_CR2_ADD_Pos)          /*!< 0xFF000000 */

+#define USART_CR2_ADD                   USART_CR2_ADD_Msk                      /*!< Address of the USART node */

+

+/******************  Bit definition for USART_CR3 register  *******************/

+#define USART_CR3_EIE_Pos               (0U)

+#define USART_CR3_EIE_Msk               (0x1UL << USART_CR3_EIE_Pos)           /*!< 0x00000001 */

+#define USART_CR3_EIE                   USART_CR3_EIE_Msk                      /*!< Error Interrupt Enable */

+#define USART_CR3_IREN_Pos              (1U)

+#define USART_CR3_IREN_Msk              (0x1UL << USART_CR3_IREN_Pos)          /*!< 0x00000002 */

+#define USART_CR3_IREN                  USART_CR3_IREN_Msk                     /*!< IrDA mode Enable */

+#define USART_CR3_IRLP_Pos              (2U)

+#define USART_CR3_IRLP_Msk              (0x1UL << USART_CR3_IRLP_Pos)          /*!< 0x00000004 */

+#define USART_CR3_IRLP                  USART_CR3_IRLP_Msk                     /*!< IrDA Low-Power */

+#define USART_CR3_HDSEL_Pos             (3U)

+#define USART_CR3_HDSEL_Msk             (0x1UL << USART_CR3_HDSEL_Pos)         /*!< 0x00000008 */

+#define USART_CR3_HDSEL                 USART_CR3_HDSEL_Msk                    /*!< Half-Duplex Selection */

+#define USART_CR3_NACK_Pos              (4U)

+#define USART_CR3_NACK_Msk              (0x1UL << USART_CR3_NACK_Pos)          /*!< 0x00000010 */

+#define USART_CR3_NACK                  USART_CR3_NACK_Msk                     /*!< SmartCard NACK enable */

+#define USART_CR3_SCEN_Pos              (5U)

+#define USART_CR3_SCEN_Msk              (0x1UL << USART_CR3_SCEN_Pos)          /*!< 0x00000020 */

+#define USART_CR3_SCEN                  USART_CR3_SCEN_Msk                     /*!< SmartCard mode enable */

+#define USART_CR3_DMAR_Pos              (6U)

+#define USART_CR3_DMAR_Msk              (0x1UL << USART_CR3_DMAR_Pos)          /*!< 0x00000040 */

+#define USART_CR3_DMAR                  USART_CR3_DMAR_Msk                     /*!< DMA Enable Receiver */

+#define USART_CR3_DMAT_Pos              (7U)

+#define USART_CR3_DMAT_Msk              (0x1UL << USART_CR3_DMAT_Pos)          /*!< 0x00000080 */

+#define USART_CR3_DMAT                  USART_CR3_DMAT_Msk                     /*!< DMA Enable Transmitter */

+#define USART_CR3_RTSE_Pos              (8U)

+#define USART_CR3_RTSE_Msk              (0x1UL << USART_CR3_RTSE_Pos)          /*!< 0x00000100 */

+#define USART_CR3_RTSE                  USART_CR3_RTSE_Msk                     /*!< RTS Enable */

+#define USART_CR3_CTSE_Pos              (9U)

+#define USART_CR3_CTSE_Msk              (0x1UL << USART_CR3_CTSE_Pos)          /*!< 0x00000200 */

+#define USART_CR3_CTSE                  USART_CR3_CTSE_Msk                     /*!< CTS Enable */

+#define USART_CR3_CTSIE_Pos             (10U)

+#define USART_CR3_CTSIE_Msk             (0x1UL << USART_CR3_CTSIE_Pos)         /*!< 0x00000400 */

+#define USART_CR3_CTSIE                 USART_CR3_CTSIE_Msk                    /*!< CTS Interrupt Enable */

+#define USART_CR3_ONEBIT_Pos            (11U)

+#define USART_CR3_ONEBIT_Msk            (0x1UL << USART_CR3_ONEBIT_Pos)        /*!< 0x00000800 */

+#define USART_CR3_ONEBIT                USART_CR3_ONEBIT_Msk                   /*!< One sample bit method enable */

+#define USART_CR3_OVRDIS_Pos            (12U)

+#define USART_CR3_OVRDIS_Msk            (0x1UL << USART_CR3_OVRDIS_Pos)        /*!< 0x00001000 */

+#define USART_CR3_OVRDIS                USART_CR3_OVRDIS_Msk                   /*!< Overrun Disable */

+#define USART_CR3_DDRE_Pos              (13U)

+#define USART_CR3_DDRE_Msk              (0x1UL << USART_CR3_DDRE_Pos)          /*!< 0x00002000 */

+#define USART_CR3_DDRE                  USART_CR3_DDRE_Msk                     /*!< DMA Disable on Reception Error */

+#define USART_CR3_DEM_Pos               (14U)

+#define USART_CR3_DEM_Msk               (0x1UL << USART_CR3_DEM_Pos)           /*!< 0x00004000 */

+#define USART_CR3_DEM                   USART_CR3_DEM_Msk                      /*!< Driver Enable Mode */

+#define USART_CR3_DEP_Pos               (15U)

+#define USART_CR3_DEP_Msk               (0x1UL << USART_CR3_DEP_Pos)           /*!< 0x00008000 */

+#define USART_CR3_DEP                   USART_CR3_DEP_Msk                      /*!< Driver Enable Polarity Selection */

+#define USART_CR3_SCARCNT_Pos           (17U)

+#define USART_CR3_SCARCNT_Msk           (0x7UL << USART_CR3_SCARCNT_Pos)       /*!< 0x000E0000 */

+#define USART_CR3_SCARCNT               USART_CR3_SCARCNT_Msk                  /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */

+#define USART_CR3_SCARCNT_0             (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */

+#define USART_CR3_SCARCNT_1             (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */

+#define USART_CR3_SCARCNT_2             (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */

+#define USART_CR3_WUS_Pos               (20U)

+#define USART_CR3_WUS_Msk               (0x3UL << USART_CR3_WUS_Pos)           /*!< 0x00300000 */

+#define USART_CR3_WUS                   USART_CR3_WUS_Msk                      /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */

+#define USART_CR3_WUS_0                 (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */

+#define USART_CR3_WUS_1                 (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */

+#define USART_CR3_WUFIE_Pos             (22U)

+#define USART_CR3_WUFIE_Msk             (0x1UL << USART_CR3_WUFIE_Pos)         /*!< 0x00400000 */

+#define USART_CR3_WUFIE                 USART_CR3_WUFIE_Msk                    /*!< Wake Up Interrupt Enable */

+#define USART_CR3_TXFTIE_Pos            (23U)

+#define USART_CR3_TXFTIE_Msk            (0x1UL << USART_CR3_TXFTIE_Pos)        /*!< 0x00800000 */

+#define USART_CR3_TXFTIE                USART_CR3_TXFTIE_Msk                   /*!< TXFIFO threshold interrupt enable */

+#define USART_CR3_TCBGTIE_Pos           (24U)

+#define USART_CR3_TCBGTIE_Msk           (0x1UL << USART_CR3_TCBGTIE_Pos)       /*!< 0x01000000 */

+#define USART_CR3_TCBGTIE               USART_CR3_TCBGTIE_Msk                  /*!< Transmission Complete before guard time, interrupt enable */

+#define USART_CR3_RXFTCFG_Pos           (25U)

+#define USART_CR3_RXFTCFG_Msk           (0x7UL << USART_CR3_RXFTCFG_Pos)       /*!< 0x0E000000 */

+#define USART_CR3_RXFTCFG               USART_CR3_RXFTCFG_Msk                  /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */

+#define USART_CR3_RXFTCFG_0             (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */

+#define USART_CR3_RXFTCFG_1             (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */

+#define USART_CR3_RXFTCFG_2             (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */

+#define USART_CR3_RXFTIE_Pos            (28U)

+#define USART_CR3_RXFTIE_Msk            (0x1UL << USART_CR3_RXFTIE_Pos)        /*!< 0x10000000 */

+#define USART_CR3_RXFTIE                USART_CR3_RXFTIE_Msk                   /*!< RXFIFO threshold interrupt enable */

+#define USART_CR3_TXFTCFG_Pos           (29U)

+#define USART_CR3_TXFTCFG_Msk           (0x7UL << USART_CR3_TXFTCFG_Pos)       /*!< 0xE0000000 */

+#define USART_CR3_TXFTCFG               USART_CR3_TXFTCFG_Msk                  /*!< TXFIFO [2:0] threshold configuration */

+#define USART_CR3_TXFTCFG_0             (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */

+#define USART_CR3_TXFTCFG_1             (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */

+#define USART_CR3_TXFTCFG_2             (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */

+

+/******************  Bit definition for USART_BRR register  *******************/

+#define USART_BRR_DIV_FRACTION_Pos      (0U)

+#define USART_BRR_DIV_FRACTION_Msk      (0xFUL << USART_BRR_DIV_FRACTION_Pos)  /*!< 0x0000000F */

+#define USART_BRR_DIV_FRACTION          USART_BRR_DIV_FRACTION_Msk             /*!< Fraction of USARTDIV */

+#define USART_BRR_DIV_MANTISSA_Pos      (4U)

+#define USART_BRR_DIV_MANTISSA_Msk      (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */

+#define USART_BRR_DIV_MANTISSA          USART_BRR_DIV_MANTISSA_Msk             /*!< Mantissa of USARTDIV */

+

+/******************  Bit definition for USART_GTPR register  ******************/

+#define USART_GTPR_PSC_Pos              (0U)

+#define USART_GTPR_PSC_Msk              (0xFFUL << USART_GTPR_PSC_Pos)         /*!< 0x000000FF */

+#define USART_GTPR_PSC                  USART_GTPR_PSC_Msk                     /*!< PSC[7:0] bits (Prescaler value) */

+#define USART_GTPR_GT_Pos               (8U)

+#define USART_GTPR_GT_Msk               (0xFFUL << USART_GTPR_GT_Pos)          /*!< 0x0000FF00 */

+#define USART_GTPR_GT                   USART_GTPR_GT_Msk                      /*!< GT[7:0] bits (Guard time value) */

+

+/*******************  Bit definition for USART_RTOR register  *****************/

+#define USART_RTOR_RTO_Pos              (0U)

+#define USART_RTOR_RTO_Msk              (0xFFFFFFUL << USART_RTOR_RTO_Pos)     /*!< 0x00FFFFFF */

+#define USART_RTOR_RTO                  USART_RTOR_RTO_Msk                     /*!< Receiver Time Out Value */

+#define USART_RTOR_BLEN_Pos             (24U)

+#define USART_RTOR_BLEN_Msk             (0xFFUL << USART_RTOR_BLEN_Pos)        /*!< 0xFF000000 */

+#define USART_RTOR_BLEN                 USART_RTOR_BLEN_Msk                    /*!< Block Length */

+

+/*******************  Bit definition for USART_RQR register  ******************/

+#define USART_RQR_ABRRQ_Pos             (0U)

+#define USART_RQR_ABRRQ_Msk             (0x1UL << USART_RQR_ABRRQ_Pos)         /*!< 0x00000001 */

+#define USART_RQR_ABRRQ                 USART_RQR_ABRRQ_Msk                    /*!< Auto-Baud Rate Request */

+#define USART_RQR_SBKRQ_Pos             (1U)

+#define USART_RQR_SBKRQ_Msk             (0x1UL << USART_RQR_SBKRQ_Pos)         /*!< 0x00000002 */

+#define USART_RQR_SBKRQ                 USART_RQR_SBKRQ_Msk                    /*!< Send Break Request */

+#define USART_RQR_MMRQ_Pos              (2U)

+#define USART_RQR_MMRQ_Msk              (0x1UL << USART_RQR_MMRQ_Pos)          /*!< 0x00000004 */

+#define USART_RQR_MMRQ                  USART_RQR_MMRQ_Msk                     /*!< Mute Mode Request */

+#define USART_RQR_RXFRQ_Pos             (3U)

+#define USART_RQR_RXFRQ_Msk             (0x1UL << USART_RQR_RXFRQ_Pos)         /*!< 0x00000008 */

+#define USART_RQR_RXFRQ                 USART_RQR_RXFRQ_Msk                    /*!< Receive Data flush Request */

+#define USART_RQR_TXFRQ_Pos             (4U)

+#define USART_RQR_TXFRQ_Msk             (0x1UL << USART_RQR_TXFRQ_Pos)         /*!< 0x00000010 */

+#define USART_RQR_TXFRQ                 USART_RQR_TXFRQ_Msk                    /*!< Transmit data flush Request */

+

+/*******************  Bit definition for USART_ISR register  ******************/

+#define USART_ISR_PE_Pos                (0U)

+#define USART_ISR_PE_Msk                (0x1UL << USART_ISR_PE_Pos)            /*!< 0x00000001 */

+#define USART_ISR_PE                    USART_ISR_PE_Msk                       /*!< Parity Error */

+#define USART_ISR_FE_Pos                (1U)

+#define USART_ISR_FE_Msk                (0x1UL << USART_ISR_FE_Pos)            /*!< 0x00000002 */

+#define USART_ISR_FE                    USART_ISR_FE_Msk                       /*!< Framing Error */

+#define USART_ISR_NE_Pos                (2U)

+#define USART_ISR_NE_Msk                (0x1UL << USART_ISR_NE_Pos)            /*!< 0x00000004 */

+#define USART_ISR_NE                    USART_ISR_NE_Msk                       /*!< Noise detected Flag */

+#define USART_ISR_ORE_Pos               (3U)

+#define USART_ISR_ORE_Msk               (0x1UL << USART_ISR_ORE_Pos)           /*!< 0x00000008 */

+#define USART_ISR_ORE                   USART_ISR_ORE_Msk                      /*!< OverRun Error */

+#define USART_ISR_IDLE_Pos              (4U)

+#define USART_ISR_IDLE_Msk              (0x1UL << USART_ISR_IDLE_Pos)          /*!< 0x00000010 */

+#define USART_ISR_IDLE                  USART_ISR_IDLE_Msk                     /*!< IDLE line detected */

+#define USART_ISR_RXNE_RXFNE_Pos        (5U)

+#define USART_ISR_RXNE_RXFNE_Msk        (0x1UL << USART_ISR_RXNE_RXFNE_Pos)    /*!< 0x00000020 */

+#define USART_ISR_RXNE_RXFNE            USART_ISR_RXNE_RXFNE_Msk               /*!< Read Data Register or RX FIFO Not Empty */

+#define USART_ISR_TC_Pos                (6U)

+#define USART_ISR_TC_Msk                (0x1UL << USART_ISR_TC_Pos)            /*!< 0x00000040 */

+#define USART_ISR_TC                    USART_ISR_TC_Msk                       /*!< Transmission Complete */

+#define USART_ISR_TXE_TXFNF_Pos         (7U)

+#define USART_ISR_TXE_TXFNF_Msk         (0x1UL << USART_ISR_TXE_TXFNF_Pos)     /*!< 0x00000080 */

+#define USART_ISR_TXE_TXFNF             USART_ISR_TXE_TXFNF_Msk                /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */

+#define USART_ISR_LBDF_Pos              (8U)

+#define USART_ISR_LBDF_Msk              (0x1UL << USART_ISR_LBDF_Pos)          /*!< 0x00000100 */

+#define USART_ISR_LBDF                  USART_ISR_LBDF_Msk                     /*!< LIN Break Detection Flag */

+#define USART_ISR_CTSIF_Pos             (9U)

+#define USART_ISR_CTSIF_Msk             (0x1UL << USART_ISR_CTSIF_Pos)         /*!< 0x00000200 */

+#define USART_ISR_CTSIF                 USART_ISR_CTSIF_Msk                    /*!< CTS interrupt flag */

+#define USART_ISR_CTS_Pos               (10U)

+#define USART_ISR_CTS_Msk               (0x1UL << USART_ISR_CTS_Pos)           /*!< 0x00000400 */

+#define USART_ISR_CTS                   USART_ISR_CTS_Msk                      /*!< CTS flag */

+#define USART_ISR_RTOF_Pos              (11U)

+#define USART_ISR_RTOF_Msk              (0x1UL << USART_ISR_RTOF_Pos)          /*!< 0x00000800 */

+#define USART_ISR_RTOF                  USART_ISR_RTOF_Msk                     /*!< Receiver Time Out */

+#define USART_ISR_EOBF_Pos              (12U)

+#define USART_ISR_EOBF_Msk              (0x1UL << USART_ISR_EOBF_Pos)          /*!< 0x00001000 */

+#define USART_ISR_EOBF                  USART_ISR_EOBF_Msk                     /*!< End Of Block Flag */

+#define USART_ISR_UDR_Pos               (13U)

+#define USART_ISR_UDR_Msk               (0x1UL << USART_ISR_UDR_Pos)           /*!< 0x00002000 */

+#define USART_ISR_UDR                   USART_ISR_UDR_Msk                      /*!< SPI slave underrun error flag */

+#define USART_ISR_ABRE_Pos              (14U)

+#define USART_ISR_ABRE_Msk              (0x1UL << USART_ISR_ABRE_Pos)          /*!< 0x00004000 */

+#define USART_ISR_ABRE                  USART_ISR_ABRE_Msk                     /*!< Auto-Baud Rate Error */

+#define USART_ISR_ABRF_Pos              (15U)

+#define USART_ISR_ABRF_Msk              (0x1UL << USART_ISR_ABRF_Pos)          /*!< 0x00008000 */

+#define USART_ISR_ABRF                  USART_ISR_ABRF_Msk                     /*!< Auto-Baud Rate Flag */

+#define USART_ISR_BUSY_Pos              (16U)

+#define USART_ISR_BUSY_Msk              (0x1UL << USART_ISR_BUSY_Pos)          /*!< 0x00010000 */

+#define USART_ISR_BUSY                  USART_ISR_BUSY_Msk                     /*!< Busy Flag */

+#define USART_ISR_CMF_Pos               (17U)

+#define USART_ISR_CMF_Msk               (0x1UL << USART_ISR_CMF_Pos)           /*!< 0x00020000 */

+#define USART_ISR_CMF                   USART_ISR_CMF_Msk                      /*!< Character Match Flag */

+#define USART_ISR_SBKF_Pos              (18U)

+#define USART_ISR_SBKF_Msk              (0x1UL << USART_ISR_SBKF_Pos)          /*!< 0x00040000 */

+#define USART_ISR_SBKF                  USART_ISR_SBKF_Msk                     /*!< Send Break Flag */

+#define USART_ISR_RWU_Pos               (19U)

+#define USART_ISR_RWU_Msk               (0x1UL << USART_ISR_RWU_Pos)           /*!< 0x00080000 */

+#define USART_ISR_RWU                   USART_ISR_RWU_Msk                      /*!< Receive Wake Up from mute mode Flag */

+#define USART_ISR_WUF_Pos               (20U)

+#define USART_ISR_WUF_Msk               (0x1UL << USART_ISR_WUF_Pos)           /*!< 0x00100000 */

+#define USART_ISR_WUF                   USART_ISR_WUF_Msk                      /*!< Wake Up from stop mode Flag */

+#define USART_ISR_TEACK_Pos             (21U)

+#define USART_ISR_TEACK_Msk             (0x1UL << USART_ISR_TEACK_Pos)         /*!< 0x00200000 */

+#define USART_ISR_TEACK                 USART_ISR_TEACK_Msk                    /*!< Transmit Enable Acknowledge Flag */

+#define USART_ISR_REACK_Pos             (22U)

+#define USART_ISR_REACK_Msk             (0x1UL << USART_ISR_REACK_Pos)         /*!< 0x00400000 */

+#define USART_ISR_REACK                 USART_ISR_REACK_Msk                    /*!< Receive Enable Acknowledge Flag */

+#define USART_ISR_TXFE_Pos              (23U)

+#define USART_ISR_TXFE_Msk              (0x1UL << USART_ISR_TXFE_Pos)          /*!< 0x00800000 */

+#define USART_ISR_TXFE                  USART_ISR_TXFE_Msk                     /*!< TXFIFO Empty */

+#define USART_ISR_RXFF_Pos              (24U)

+#define USART_ISR_RXFF_Msk              (0x1UL << USART_ISR_RXFF_Pos)          /*!< 0x01000000 */

+#define USART_ISR_RXFF                  USART_ISR_RXFF_Msk                     /*!< RXFIFO Full Flag */

+#define USART_ISR_TCBGT_Pos             (25U)

+#define USART_ISR_TCBGT_Msk             (0x1UL << USART_ISR_TCBGT_Pos)         /*!< 0x02000000 */

+#define USART_ISR_TCBGT                 USART_ISR_TCBGT_Msk                    /*!< Transmission complete before guard time Flag */

+#define USART_ISR_RXFT_Pos              (26U)

+#define USART_ISR_RXFT_Msk              (0x1UL << USART_ISR_RXFT_Pos)          /*!< 0x04000000 */

+#define USART_ISR_RXFT                  USART_ISR_RXFT_Msk                     /*!< RXFIFO threshold Flag */

+#define USART_ISR_TXFT_Pos              (27U)

+#define USART_ISR_TXFT_Msk              (0x1UL << USART_ISR_TXFT_Pos)          /*!< 0x08000000 */

+#define USART_ISR_TXFT                  USART_ISR_TXFT_Msk                     /*!< TXFIFO threshold Flag */

+

+/*******************  Bit definition for USART_ICR register  ******************/

+#define USART_ICR_PECF_Pos              (0U)

+#define USART_ICR_PECF_Msk              (0x1UL << USART_ICR_PECF_Pos)          /*!< 0x00000001 */

+#define USART_ICR_PECF                  USART_ICR_PECF_Msk                     /*!< Parity Error Clear Flag */

+#define USART_ICR_FECF_Pos              (1U)

+#define USART_ICR_FECF_Msk              (0x1UL << USART_ICR_FECF_Pos)          /*!< 0x00000002 */

+#define USART_ICR_FECF                  USART_ICR_FECF_Msk                     /*!< Framing Error Clear Flag */

+#define USART_ICR_NECF_Pos              (2U)

+#define USART_ICR_NECF_Msk              (0x1UL << USART_ICR_NECF_Pos)          /*!< 0x00000004 */

+#define USART_ICR_NECF                  USART_ICR_NECF_Msk                     /*!< Noise detected Clear Flag */

+#define USART_ICR_ORECF_Pos             (3U)

+#define USART_ICR_ORECF_Msk             (0x1UL << USART_ICR_ORECF_Pos)         /*!< 0x00000008 */

+#define USART_ICR_ORECF                 USART_ICR_ORECF_Msk                    /*!< OverRun Error Clear Flag */

+#define USART_ICR_IDLECF_Pos            (4U)

+#define USART_ICR_IDLECF_Msk            (0x1UL << USART_ICR_IDLECF_Pos)        /*!< 0x00000010 */

+#define USART_ICR_IDLECF                USART_ICR_IDLECF_Msk                   /*!< IDLE line detected Clear Flag */

+#define USART_ICR_TXFECF_Pos            (5U)

+#define USART_ICR_TXFECF_Msk            (0x1UL << USART_ICR_TXFECF_Pos)        /*!< 0x00000020 */

+#define USART_ICR_TXFECF                USART_ICR_TXFECF_Msk                   /*!< TXFIFO empty clear flag */

+#define USART_ICR_TCCF_Pos              (6U)

+#define USART_ICR_TCCF_Msk              (0x1UL << USART_ICR_TCCF_Pos)          /*!< 0x00000040 */

+#define USART_ICR_TCCF                  USART_ICR_TCCF_Msk                     /*!< Transmission Complete Clear Flag */

+#define USART_ICR_TCBGTCF_Pos           (7U)

+#define USART_ICR_TCBGTCF_Msk           (0x1UL << USART_ICR_TCBGTCF_Pos)       /*!< 0x00000080 */

+#define USART_ICR_TCBGTCF               USART_ICR_TCBGTCF_Msk                  /*!< Transmission complete before guard time Clear Flag */

+#define USART_ICR_LBDCF_Pos             (8U)

+#define USART_ICR_LBDCF_Msk             (0x1UL << USART_ICR_LBDCF_Pos)         /*!< 0x00000100 */

+#define USART_ICR_LBDCF                 USART_ICR_LBDCF_Msk                    /*!< LIN Break Detection Clear Flag */

+#define USART_ICR_CTSCF_Pos             (9U)

+#define USART_ICR_CTSCF_Msk             (0x1UL << USART_ICR_CTSCF_Pos)         /*!< 0x00000200 */

+#define USART_ICR_CTSCF                 USART_ICR_CTSCF_Msk                    /*!< CTS Interrupt Clear Flag */

+#define USART_ICR_RTOCF_Pos             (11U)

+#define USART_ICR_RTOCF_Msk             (0x1UL << USART_ICR_RTOCF_Pos)         /*!< 0x00000800 */

+#define USART_ICR_RTOCF                 USART_ICR_RTOCF_Msk                    /*!< Receiver Time Out Clear Flag */

+#define USART_ICR_EOBCF_Pos             (12U)

+#define USART_ICR_EOBCF_Msk             (0x1UL << USART_ICR_EOBCF_Pos)         /*!< 0x00001000 */

+#define USART_ICR_EOBCF                 USART_ICR_EOBCF_Msk                    /*!< End Of Block Clear Flag */

+#define USART_ICR_UDRCF_Pos             (13U)

+#define USART_ICR_UDRCF_Msk             (0x1UL << USART_ICR_UDRCF_Pos)         /*!< 0x00002000 */

+#define USART_ICR_UDRCF                 USART_ICR_UDRCF_Msk                    /*!< SPI slave underrun clear flag */

+#define USART_ICR_CMCF_Pos              (17U)

+#define USART_ICR_CMCF_Msk              (0x1UL << USART_ICR_CMCF_Pos)          /*!< 0x00020000 */

+#define USART_ICR_CMCF                  USART_ICR_CMCF_Msk                     /*!< Character Match Clear Flag */

+#define USART_ICR_WUCF_Pos              (20U)

+#define USART_ICR_WUCF_Msk              (0x1UL << USART_ICR_WUCF_Pos)          /*!< 0x00100000 */

+#define USART_ICR_WUCF                  USART_ICR_WUCF_Msk                     /*!< Wake Up from stop mode Clear Flag */

+

+/*******************  Bit definition for USART_RDR register  ******************/

+#define USART_RDR_RDR_Pos               (0U)

+#define USART_RDR_RDR_Msk               (0x1FFUL << USART_RDR_RDR_Pos)         /*!< 0x000001FF */

+#define USART_RDR_RDR                   USART_RDR_RDR_Msk                      /*!< RDR[8:0] bits (Receive Data value) */

+

+/*******************  Bit definition for USART_TDR register  ******************/

+#define USART_TDR_TDR_Pos               (0U)

+#define USART_TDR_TDR_Msk               (0x1FFUL << USART_TDR_TDR_Pos)         /*!< 0x000001FF */

+#define USART_TDR_TDR                   USART_TDR_TDR_Msk                      /*!< TDR[8:0] bits (Transmit Data value) */

+

+/*******************  Bit definition for USART_PRESC register  ******************/

+#define USART_PRESC_PRESCALER_Pos       (0U)

+#define USART_PRESC_PRESCALER_Msk       (0xFUL << USART_PRESC_PRESCALER_Pos)   /*!< 0x0000000F */

+#define USART_PRESC_PRESCALER           USART_PRESC_PRESCALER_Msk              /*!< PRESCALER[3:0] bits (Clock prescaler) */

+#define USART_PRESC_PRESCALER_0         (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */

+#define USART_PRESC_PRESCALER_1         (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */

+#define USART_PRESC_PRESCALER_2         (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */

+#define USART_PRESC_PRESCALER_3         (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */

+

+/******************************************************************************/

+/*                                                                            */

+/*           Single Wire Protocol Master Interface (SWPMI)                    */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for SWPMI_CR register   ********************/

+#define SWPMI_CR_RXDMA_Pos       (0U)

+#define SWPMI_CR_RXDMA_Msk       (0x1UL << SWPMI_CR_RXDMA_Pos)                 /*!< 0x00000001 */

+#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */

+#define SWPMI_CR_TXDMA_Pos       (1U)

+#define SWPMI_CR_TXDMA_Msk       (0x1UL << SWPMI_CR_TXDMA_Pos)                 /*!< 0x00000002 */

+#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */

+#define SWPMI_CR_RXMODE_Pos      (2U)

+#define SWPMI_CR_RXMODE_Msk      (0x1UL << SWPMI_CR_RXMODE_Pos)                /*!< 0x00000004 */

+#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */

+#define SWPMI_CR_TXMODE_Pos      (3U)

+#define SWPMI_CR_TXMODE_Msk      (0x1UL << SWPMI_CR_TXMODE_Pos)                /*!< 0x00000008 */

+#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */

+#define SWPMI_CR_LPBK_Pos        (4U)

+#define SWPMI_CR_LPBK_Msk        (0x1UL << SWPMI_CR_LPBK_Pos)                  /*!< 0x00000010 */

+#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */

+#define SWPMI_CR_SWPACT_Pos      (5U)

+#define SWPMI_CR_SWPACT_Msk      (0x1UL << SWPMI_CR_SWPACT_Pos)                /*!< 0x00000020 */

+#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */

+#define SWPMI_CR_DEACT_Pos       (10U)

+#define SWPMI_CR_DEACT_Msk       (0x1UL << SWPMI_CR_DEACT_Pos)                 /*!< 0x00000400 */

+#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */

+#define SWPMI_CR_SWPEN_Pos       (11U)

+#define SWPMI_CR_SWPEN_Msk       (0x1UL << SWPMI_CR_SWPEN_Pos)                 /*!< 0x00000800 */

+#define SWPMI_CR_SWPEN           SWPMI_CR_SWPEN_Msk                            /*!<Single wire protocol master transceiver enable       */

+

+/*******************  Bit definition for SWPMI_BRR register  ********************/

+#define SWPMI_BRR_BR_Pos         (0U)

+#define SWPMI_BRR_BR_Msk         (0xFFUL << SWPMI_BRR_BR_Pos)                  /*!< 0x000000FF */

+#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[7:0] bits (Bitrate prescaler) */

+

+/*******************  Bit definition for SWPMI_ISR register  ********************/

+#define SWPMI_ISR_RXBFF_Pos      (0U)

+#define SWPMI_ISR_RXBFF_Msk      (0x1UL << SWPMI_ISR_RXBFF_Pos)                /*!< 0x00000001 */

+#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */

+#define SWPMI_ISR_TXBEF_Pos      (1U)

+#define SWPMI_ISR_TXBEF_Msk      (0x1UL << SWPMI_ISR_TXBEF_Pos)                /*!< 0x00000002 */

+#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */

+#define SWPMI_ISR_RXBERF_Pos     (2U)

+#define SWPMI_ISR_RXBERF_Msk     (0x1UL << SWPMI_ISR_RXBERF_Pos)               /*!< 0x00000004 */

+#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */

+#define SWPMI_ISR_RXOVRF_Pos     (3U)

+#define SWPMI_ISR_RXOVRF_Msk     (0x1UL << SWPMI_ISR_RXOVRF_Pos)               /*!< 0x00000008 */

+#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */

+#define SWPMI_ISR_TXUNRF_Pos     (4U)

+#define SWPMI_ISR_TXUNRF_Msk     (0x1UL << SWPMI_ISR_TXUNRF_Pos)               /*!< 0x00000010 */

+#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */

+#define SWPMI_ISR_RXNE_Pos       (5U)

+#define SWPMI_ISR_RXNE_Msk       (0x1UL << SWPMI_ISR_RXNE_Pos)                 /*!< 0x00000020 */

+#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */

+#define SWPMI_ISR_TXE_Pos        (6U)

+#define SWPMI_ISR_TXE_Msk        (0x1UL << SWPMI_ISR_TXE_Pos)                  /*!< 0x00000040 */

+#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */

+#define SWPMI_ISR_TCF_Pos        (7U)

+#define SWPMI_ISR_TCF_Msk        (0x1UL << SWPMI_ISR_TCF_Pos)                  /*!< 0x00000080 */

+#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */

+#define SWPMI_ISR_SRF_Pos        (8U)

+#define SWPMI_ISR_SRF_Msk        (0x1UL << SWPMI_ISR_SRF_Pos)                  /*!< 0x00000100 */

+#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */

+#define SWPMI_ISR_SUSP_Pos       (9U)

+#define SWPMI_ISR_SUSP_Msk       (0x1UL << SWPMI_ISR_SUSP_Pos)                 /*!< 0x00000200 */

+#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */

+#define SWPMI_ISR_DEACTF_Pos     (10U)

+#define SWPMI_ISR_DEACTF_Msk     (0x1UL << SWPMI_ISR_DEACTF_Pos)               /*!< 0x00000400 */

+#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */

+#define SWPMI_ISR_RDYF_Pos       (11U)

+#define SWPMI_ISR_RDYF_Msk       (0x1UL << SWPMI_ISR_RDYF_Pos)                 /*!< 0x00000800 */

+#define SWPMI_ISR_RDYF           SWPMI_ISR_RDYF_Msk                            /*!<Transceiver ready flag          */

+

+/*******************  Bit definition for SWPMI_ICR register  ********************/

+#define SWPMI_ICR_CRXBFF_Pos     (0U)

+#define SWPMI_ICR_CRXBFF_Msk     (0x1UL << SWPMI_ICR_CRXBFF_Pos)               /*!< 0x00000001 */

+#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */

+#define SWPMI_ICR_CTXBEF_Pos     (1U)

+#define SWPMI_ICR_CTXBEF_Msk     (0x1UL << SWPMI_ICR_CTXBEF_Pos)               /*!< 0x00000002 */

+#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */

+#define SWPMI_ICR_CRXBERF_Pos    (2U)

+#define SWPMI_ICR_CRXBERF_Msk    (0x1UL << SWPMI_ICR_CRXBERF_Pos)              /*!< 0x00000004 */

+#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */

+#define SWPMI_ICR_CRXOVRF_Pos    (3U)

+#define SWPMI_ICR_CRXOVRF_Msk    (0x1UL << SWPMI_ICR_CRXOVRF_Pos)              /*!< 0x00000008 */

+#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */

+#define SWPMI_ICR_CTXUNRF_Pos    (4U)

+#define SWPMI_ICR_CTXUNRF_Msk    (0x1UL << SWPMI_ICR_CTXUNRF_Pos)              /*!< 0x00000010 */

+#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */

+#define SWPMI_ICR_CTCF_Pos       (7U)

+#define SWPMI_ICR_CTCF_Msk       (0x1UL << SWPMI_ICR_CTCF_Pos)                 /*!< 0x00000080 */

+#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */

+#define SWPMI_ICR_CSRF_Pos       (8U)

+#define SWPMI_ICR_CSRF_Msk       (0x1UL << SWPMI_ICR_CSRF_Pos)                 /*!< 0x00000100 */

+#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */

+#define SWPMI_ICR_CRDYF_Pos      (11U)

+#define SWPMI_ICR_CRDYF_Msk      (0x1UL << SWPMI_ICR_CRDYF_Pos)                /*!< 0x00000800 */

+#define SWPMI_ICR_CRDYF          SWPMI_ICR_CRDYF_Msk                           /*!<Clear transceiver ready flag         */

+

+/*******************  Bit definition for SWPMI_IER register  ********************/

+#define SWPMI_IER_RXBFIE_Pos     (0U)

+#define SWPMI_IER_RXBFIE_Msk     (0x1UL << SWPMI_IER_RXBFIE_Pos)               /*!< 0x00000001 */

+#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */

+#define SWPMI_IER_TXBEIE_Pos     (1U)

+#define SWPMI_IER_TXBEIE_Msk     (0x1UL << SWPMI_IER_TXBEIE_Pos)               /*!< 0x00000002 */

+#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */

+#define SWPMI_IER_RXBERIE_Pos    (2U)

+#define SWPMI_IER_RXBERIE_Msk    (0x1UL << SWPMI_IER_RXBERIE_Pos)              /*!< 0x00000004 */

+#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */

+#define SWPMI_IER_RXOVRIE_Pos    (3U)

+#define SWPMI_IER_RXOVRIE_Msk    (0x1UL << SWPMI_IER_RXOVRIE_Pos)              /*!< 0x00000008 */

+#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */

+#define SWPMI_IER_TXUNRIE_Pos    (4U)

+#define SWPMI_IER_TXUNRIE_Msk    (0x1UL << SWPMI_IER_TXUNRIE_Pos)              /*!< 0x00000010 */

+#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */

+#define SWPMI_IER_RIE_Pos        (5U)

+#define SWPMI_IER_RIE_Msk        (0x1UL << SWPMI_IER_RIE_Pos)                  /*!< 0x00000020 */

+#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */

+#define SWPMI_IER_TIE_Pos        (6U)

+#define SWPMI_IER_TIE_Msk        (0x1UL << SWPMI_IER_TIE_Pos)                  /*!< 0x00000040 */

+#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */

+#define SWPMI_IER_TCIE_Pos       (7U)

+#define SWPMI_IER_TCIE_Msk       (0x1UL << SWPMI_IER_TCIE_Pos)                 /*!< 0x00000080 */

+#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */

+#define SWPMI_IER_SRIE_Pos       (8U)

+#define SWPMI_IER_SRIE_Msk       (0x1UL << SWPMI_IER_SRIE_Pos)                 /*!< 0x00000100 */

+#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */

+#define SWPMI_IER_RDYIE_Pos      (11U)

+#define SWPMI_IER_RDYIE_Msk      (0x1UL << SWPMI_IER_RDYIE_Pos)                /*!< 0x00000800 */

+#define SWPMI_IER_RDYIE          SWPMI_IER_RDYIE_Msk                           /*!<Transceiver ready interrupt enable          */

+

+/*******************  Bit definition for SWPMI_RFL register  ********************/

+#define SWPMI_RFL_RFL_Pos        (0U)

+#define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */

+#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */

+#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */

+

+/*******************  Bit definition for SWPMI_TDR register  ********************/

+#define SWPMI_TDR_TD_Pos         (0U)

+#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)            /*!< 0xFFFFFFFF */

+#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */

+

+/*******************  Bit definition for SWPMI_RDR register  ********************/

+#define SWPMI_RDR_RD_Pos         (0U)

+#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)            /*!< 0xFFFFFFFF */

+#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Recive Data Register           */

+

+

+/*******************  Bit definition for SWPMI_OR register  ********************/

+#define SWPMI_OR_TBYP_Pos        (0U)

+#define SWPMI_OR_TBYP_Msk        (0x1UL << SWPMI_OR_TBYP_Pos)                  /*!< 0x00000001 */

+#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */

+#define SWPMI_OR_CLASS_Pos       (1U)

+#define SWPMI_OR_CLASS_Msk       (0x1UL << SWPMI_OR_CLASS_Pos)                 /*!< 0x00000002 */

+#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP CLASS selection */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            Window WATCHDOG                                 */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for WWDG_CR register  ********************/

+#define WWDG_CR_T_Pos           (0U)

+#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */

+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */

+#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */

+#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */

+#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */

+#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */

+#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */

+#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */

+#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */

+

+#define WWDG_CR_WDGA_Pos        (7U)

+#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */

+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */

+

+/*******************  Bit definition for WWDG_CFR register  *******************/

+#define WWDG_CFR_W_Pos          (0U)

+#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */

+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */

+#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */

+#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */

+#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */

+#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */

+#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */

+#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */

+#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */

+

+#define WWDG_CFR_EWI_Pos        (9U)

+#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */

+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */

+

+#define WWDG_CFR_WDGTB_Pos      (11U)

+#define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */

+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */

+#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000800 */

+#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00001000 */

+#define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00002000 */

+

+/*******************  Bit definition for WWDG_SR register  ********************/

+#define WWDG_SR_EWIF_Pos        (0U)

+#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */

+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                DBG                                         */

+/*                                                                            */

+/******************************************************************************/

+/*********************************  DEVICE ID  ********************************/

+#define STM32H7_DEV_ID           0x450UL

+

+/********************  Bit definition for DBGMCU_IDCODE register  *************/

+#define DBGMCU_IDCODE_DEV_ID_Pos          (0U)

+#define DBGMCU_IDCODE_DEV_ID_Msk          (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */

+#define DBGMCU_IDCODE_DEV_ID              DBGMCU_IDCODE_DEV_ID_Msk

+#define DBGMCU_IDCODE_REV_ID_Pos          (16U)

+#define DBGMCU_IDCODE_REV_ID_Msk          (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */

+#define DBGMCU_IDCODE_REV_ID              DBGMCU_IDCODE_REV_ID_Msk

+

+/********************  Bit definition for DBGMCU_CR register  *****************/

+#define DBGMCU_CR_DBG_SLEEPD1_Pos         (0U)

+#define DBGMCU_CR_DBG_SLEEPD1_Msk         (0x1UL << DBGMCU_CR_DBG_SLEEPD1_Pos) /*!< 0x00000001 */

+#define DBGMCU_CR_DBG_SLEEPD1             DBGMCU_CR_DBG_SLEEPD1_Msk

+#define DBGMCU_CR_DBG_STOPD1_Pos          (1U)

+#define DBGMCU_CR_DBG_STOPD1_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD1_Pos)  /*!< 0x00000002 */

+#define DBGMCU_CR_DBG_STOPD1              DBGMCU_CR_DBG_STOPD1_Msk

+#define DBGMCU_CR_DBG_STANDBYD1_Pos       (2U)

+#define DBGMCU_CR_DBG_STANDBYD1_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos) /*!< 0x00000004 */

+#define DBGMCU_CR_DBG_STANDBYD1           DBGMCU_CR_DBG_STANDBYD1_Msk

+#define DBGMCU_CR_DBG_STOPD3_Pos          (7U)

+#define DBGMCU_CR_DBG_STOPD3_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos)  /*!< 0x00000080 */

+#define DBGMCU_CR_DBG_STOPD3              DBGMCU_CR_DBG_STOPD3_Msk

+#define DBGMCU_CR_DBG_STANDBYD3_Pos       (8U)

+#define DBGMCU_CR_DBG_STANDBYD3_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos) /*!< 0x00000100 */

+#define DBGMCU_CR_DBG_STANDBYD3           DBGMCU_CR_DBG_STANDBYD3_Msk

+#define DBGMCU_CR_DBG_TRACECKEN_Pos       (20U)

+#define DBGMCU_CR_DBG_TRACECKEN_Msk       (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */

+#define DBGMCU_CR_DBG_TRACECKEN           DBGMCU_CR_DBG_TRACECKEN_Msk

+#define DBGMCU_CR_DBG_CKD1EN_Pos          (21U)

+#define DBGMCU_CR_DBG_CKD1EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD1EN_Pos)  /*!< 0x00200000 */

+#define DBGMCU_CR_DBG_CKD1EN              DBGMCU_CR_DBG_CKD1EN_Msk

+#define DBGMCU_CR_DBG_CKD3EN_Pos          (22U)

+#define DBGMCU_CR_DBG_CKD3EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD3EN_Pos)  /*!< 0x00400000 */

+#define DBGMCU_CR_DBG_CKD3EN              DBGMCU_CR_DBG_CKD3EN_Msk

+#define DBGMCU_CR_DBG_TRGOEN_Pos          (28U)

+#define DBGMCU_CR_DBG_TRGOEN_Msk          (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)  /*!< 0x10000000 */

+#define DBGMCU_CR_DBG_TRGOEN              DBGMCU_CR_DBG_TRGOEN_Msk

+

+/********************  Bit definition for APB3FZ1 register  ************/

+#define DBGMCU_APB3FZ1_DBG_WWDG1_Pos      (6U)

+#define DBGMCU_APB3FZ1_DBG_WWDG1_Msk      (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB3FZ1_DBG_WWDG1          DBGMCU_APB3FZ1_DBG_WWDG1_Msk

+/********************  Bit definition for APB1LFZ1 register  ************/

+#define DBGMCU_APB1LFZ1_DBG_TIM2_Pos      (0U)

+#define DBGMCU_APB1LFZ1_DBG_TIM2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB1LFZ1_DBG_TIM2          DBGMCU_APB1LFZ1_DBG_TIM2_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM3_Pos      (1U)

+#define DBGMCU_APB1LFZ1_DBG_TIM3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB1LFZ1_DBG_TIM3          DBGMCU_APB1LFZ1_DBG_TIM3_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM4_Pos      (2U)

+#define DBGMCU_APB1LFZ1_DBG_TIM4_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */

+#define DBGMCU_APB1LFZ1_DBG_TIM4          DBGMCU_APB1LFZ1_DBG_TIM4_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM5_Pos      (3U)

+#define DBGMCU_APB1LFZ1_DBG_TIM5_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */

+#define DBGMCU_APB1LFZ1_DBG_TIM5          DBGMCU_APB1LFZ1_DBG_TIM5_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM6_Pos      (4U)

+#define DBGMCU_APB1LFZ1_DBG_TIM6_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */

+#define DBGMCU_APB1LFZ1_DBG_TIM6          DBGMCU_APB1LFZ1_DBG_TIM6_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM7_Pos      (5U)

+#define DBGMCU_APB1LFZ1_DBG_TIM7_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */

+#define DBGMCU_APB1LFZ1_DBG_TIM7          DBGMCU_APB1LFZ1_DBG_TIM7_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM12_Pos     (6U)

+#define DBGMCU_APB1LFZ1_DBG_TIM12_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB1LFZ1_DBG_TIM12         DBGMCU_APB1LFZ1_DBG_TIM12_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM13_Pos     (7U)

+#define DBGMCU_APB1LFZ1_DBG_TIM13_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB1LFZ1_DBG_TIM13         DBGMCU_APB1LFZ1_DBG_TIM13_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM14_Pos     (8U)

+#define DBGMCU_APB1LFZ1_DBG_TIM14_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */

+#define DBGMCU_APB1LFZ1_DBG_TIM14         DBGMCU_APB1LFZ1_DBG_TIM14_Msk

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos    (9U)

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1        DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C1_Pos      (21U)

+#define DBGMCU_APB1LFZ1_DBG_I2C1_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C1          DBGMCU_APB1LFZ1_DBG_I2C1_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C2_Pos      (22U)

+#define DBGMCU_APB1LFZ1_DBG_I2C2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C2          DBGMCU_APB1LFZ1_DBG_I2C2_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C3_Pos      (23U)

+#define DBGMCU_APB1LFZ1_DBG_I2C3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C3          DBGMCU_APB1LFZ1_DBG_I2C3_Msk

+

+/********************  Bit definition for APB1HFZ1 register  ************/

+#define DBGMCU_APB1HFZ1_DBG_FDCAN_Pos     (8U)

+#define DBGMCU_APB1HFZ1_DBG_FDCAN_Msk     (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_Pos) /*!< 0x00000100 */

+#define DBGMCU_APB1HFZ1_DBG_FDCAN         DBGMCU_APB1HFZ1_DBG_FDCAN_Msk

+/********************  Bit definition for APB2FZ1 register  ************/

+#define DBGMCU_APB2FZ1_DBG_TIM1_Pos       (0U)

+#define DBGMCU_APB2FZ1_DBG_TIM1_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB2FZ1_DBG_TIM1           DBGMCU_APB2FZ1_DBG_TIM1_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM8_Pos       (1U)

+#define DBGMCU_APB2FZ1_DBG_TIM8_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB2FZ1_DBG_TIM8           DBGMCU_APB2FZ1_DBG_TIM8_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM15_Pos      (16U)

+#define DBGMCU_APB2FZ1_DBG_TIM15_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB2FZ1_DBG_TIM15          DBGMCU_APB2FZ1_DBG_TIM15_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM16_Pos      (17U)

+#define DBGMCU_APB2FZ1_DBG_TIM16_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */

+#define DBGMCU_APB2FZ1_DBG_TIM16          DBGMCU_APB2FZ1_DBG_TIM16_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM17_Pos      (18U)

+#define DBGMCU_APB2FZ1_DBG_TIM17_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB2FZ1_DBG_TIM17          DBGMCU_APB2FZ1_DBG_TIM17_Msk

+#define DBGMCU_APB2FZ1_DBG_HRTIM_Pos      (29U)

+#define DBGMCU_APB2FZ1_DBG_HRTIM_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_HRTIM_Pos) /*!< 0x20000000 */

+#define DBGMCU_APB2FZ1_DBG_HRTIM          DBGMCU_APB2FZ1_DBG_HRTIM_Msk

+

+/********************  Bit definition for APB4FZ1 register  ************/

+#define DBGMCU_APB4FZ1_DBG_I2C4_Pos       (7U)

+#define DBGMCU_APB4FZ1_DBG_I2C4_Msk       (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB4FZ1_DBG_I2C4           DBGMCU_APB4FZ1_DBG_I2C4_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos     (9U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM2         DBGMCU_APB4FZ1_DBG_LPTIM2_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos     (10U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM3         DBGMCU_APB4FZ1_DBG_LPTIM3_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM4_Pos     (11U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM4_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos) /*!< 0x00000800 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM4         DBGMCU_APB4FZ1_DBG_LPTIM4_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM5_Pos     (12U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM5_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos) /*!< 0x00001000 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM5         DBGMCU_APB4FZ1_DBG_LPTIM5_Msk

+#define DBGMCU_APB4FZ1_DBG_RTC_Pos        (16U)

+#define DBGMCU_APB4FZ1_DBG_RTC_Msk        (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB4FZ1_DBG_RTC            DBGMCU_APB4FZ1_DBG_RTC_Msk

+#define DBGMCU_APB4FZ1_DBG_IWDG1_Pos      (18U)

+#define DBGMCU_APB4FZ1_DBG_IWDG1_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB4FZ1_DBG_IWDG1          DBGMCU_APB4FZ1_DBG_IWDG1_Msk

+/******************************************************************************/

+/*                                                                            */

+/*                        High Resolution Timer (HRTIM)                       */

+/*                                                                            */

+/******************************************************************************/

+/******************** Master Timer control register ***************************/

+#define HRTIM_MCR_CK_PSC_Pos          (0U)

+#define HRTIM_MCR_CK_PSC_Msk          (0x7UL << HRTIM_MCR_CK_PSC_Pos)          /*!< 0x00000007 */

+#define HRTIM_MCR_CK_PSC              HRTIM_MCR_CK_PSC_Msk                     /*!< Prescaler mask */

+#define HRTIM_MCR_CK_PSC_0            (0x1UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000001 */

+#define HRTIM_MCR_CK_PSC_1            (0x2UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000002 */

+#define HRTIM_MCR_CK_PSC_2            (0x4UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000004 */

+

+#define HRTIM_MCR_CONT_Pos            (3U)

+#define HRTIM_MCR_CONT_Msk            (0x1UL << HRTIM_MCR_CONT_Pos)            /*!< 0x00000008 */

+#define HRTIM_MCR_CONT                HRTIM_MCR_CONT_Msk                       /*!< Continuous mode */

+#define HRTIM_MCR_RETRIG_Pos          (4U)

+#define HRTIM_MCR_RETRIG_Msk          (0x1UL << HRTIM_MCR_RETRIG_Pos)          /*!< 0x00000010 */

+#define HRTIM_MCR_RETRIG              HRTIM_MCR_RETRIG_Msk                     /*!< Rettrigreable mode */

+#define HRTIM_MCR_HALF_Pos            (5U)

+#define HRTIM_MCR_HALF_Msk            (0x1UL << HRTIM_MCR_HALF_Pos)            /*!< 0x00000020 */

+#define HRTIM_MCR_HALF                HRTIM_MCR_HALF_Msk                       /*!< Half mode */

+

+#define HRTIM_MCR_SYNC_IN_Pos         (8U)

+#define HRTIM_MCR_SYNC_IN_Msk         (0x3UL << HRTIM_MCR_SYNC_IN_Pos)         /*!< 0x00000300 */

+#define HRTIM_MCR_SYNC_IN             HRTIM_MCR_SYNC_IN_Msk                    /*!< Synchronization input master */

+#define HRTIM_MCR_SYNC_IN_0           (0x1UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000100 */

+#define HRTIM_MCR_SYNC_IN_1           (0x2UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000200 */

+#define HRTIM_MCR_SYNCRSTM_Pos        (10U)

+#define HRTIM_MCR_SYNCRSTM_Msk        (0x1UL << HRTIM_MCR_SYNCRSTM_Pos)        /*!< 0x00000400 */

+#define HRTIM_MCR_SYNCRSTM            HRTIM_MCR_SYNCRSTM_Msk                   /*!< Synchronization reset master */

+#define HRTIM_MCR_SYNCSTRTM_Pos       (11U)

+#define HRTIM_MCR_SYNCSTRTM_Msk       (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos)       /*!< 0x00000800 */

+#define HRTIM_MCR_SYNCSTRTM           HRTIM_MCR_SYNCSTRTM_Msk                  /*!< Synchronization start master */

+#define HRTIM_MCR_SYNC_OUT_Pos        (12U)

+#define HRTIM_MCR_SYNC_OUT_Msk        (0x3UL << HRTIM_MCR_SYNC_OUT_Pos)        /*!< 0x00003000 */

+#define HRTIM_MCR_SYNC_OUT            HRTIM_MCR_SYNC_OUT_Msk                   /*!< Synchronization output master */

+#define HRTIM_MCR_SYNC_OUT_0          (0x1UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00001000 */

+#define HRTIM_MCR_SYNC_OUT_1          (0x2UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00002000 */

+#define HRTIM_MCR_SYNC_SRC_Pos        (14U)

+#define HRTIM_MCR_SYNC_SRC_Msk        (0x3UL << HRTIM_MCR_SYNC_SRC_Pos)        /*!< 0x0000C000 */

+#define HRTIM_MCR_SYNC_SRC            HRTIM_MCR_SYNC_SRC_Msk                   /*!< Synchronization source */

+#define HRTIM_MCR_SYNC_SRC_0          (0x1UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00004000 */

+#define HRTIM_MCR_SYNC_SRC_1          (0x2UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00008000 */

+

+#define HRTIM_MCR_MCEN_Pos            (16U)

+#define HRTIM_MCR_MCEN_Msk            (0x1UL << HRTIM_MCR_MCEN_Pos)            /*!< 0x00010000 */

+#define HRTIM_MCR_MCEN                HRTIM_MCR_MCEN_Msk                       /*!< Master counter enable */

+#define HRTIM_MCR_TACEN_Pos           (17U)

+#define HRTIM_MCR_TACEN_Msk           (0x1UL << HRTIM_MCR_TACEN_Pos)           /*!< 0x00020000 */

+#define HRTIM_MCR_TACEN               HRTIM_MCR_TACEN_Msk                      /*!< Timer A counter enable */

+#define HRTIM_MCR_TBCEN_Pos           (18U)

+#define HRTIM_MCR_TBCEN_Msk           (0x1UL << HRTIM_MCR_TBCEN_Pos)           /*!< 0x00040000 */

+#define HRTIM_MCR_TBCEN               HRTIM_MCR_TBCEN_Msk                      /*!< Timer B counter enable */

+#define HRTIM_MCR_TCCEN_Pos           (19U)

+#define HRTIM_MCR_TCCEN_Msk           (0x1UL << HRTIM_MCR_TCCEN_Pos)           /*!< 0x00080000 */

+#define HRTIM_MCR_TCCEN               HRTIM_MCR_TCCEN_Msk                      /*!< Timer C counter enable */

+#define HRTIM_MCR_TDCEN_Pos           (20U)

+#define HRTIM_MCR_TDCEN_Msk           (0x1UL << HRTIM_MCR_TDCEN_Pos)           /*!< 0x00100000 */

+#define HRTIM_MCR_TDCEN               HRTIM_MCR_TDCEN_Msk                      /*!< Timer D counter enable */

+#define HRTIM_MCR_TECEN_Pos           (21U)

+#define HRTIM_MCR_TECEN_Msk           (0x1UL << HRTIM_MCR_TECEN_Pos)           /*!< 0x00200000 */

+#define HRTIM_MCR_TECEN               HRTIM_MCR_TECEN_Msk                      /*!< Timer E counter enable */

+

+#define HRTIM_MCR_DACSYNC_Pos         (25U)

+#define HRTIM_MCR_DACSYNC_Msk         (0x3UL << HRTIM_MCR_DACSYNC_Pos)         /*!< 0x06000000 */

+#define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC sychronization mask */

+#define HRTIM_MCR_DACSYNC_0           (0x1UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x02000000 */

+#define HRTIM_MCR_DACSYNC_1           (0x2UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x04000000 */

+

+#define HRTIM_MCR_PREEN_Pos           (27U)

+#define HRTIM_MCR_PREEN_Msk           (0x1UL << HRTIM_MCR_PREEN_Pos)           /*!< 0x08000000 */

+#define HRTIM_MCR_PREEN               HRTIM_MCR_PREEN_Msk                      /*!< Master preload enable */

+#define HRTIM_MCR_MREPU_Pos           (29U)

+#define HRTIM_MCR_MREPU_Msk           (0x1UL << HRTIM_MCR_MREPU_Pos)           /*!< 0x20000000 */

+#define HRTIM_MCR_MREPU               HRTIM_MCR_MREPU_Msk                      /*!< Master repetition update */

+

+#define HRTIM_MCR_BRSTDMA_Pos         (30U)

+#define HRTIM_MCR_BRSTDMA_Msk         (0x3UL << HRTIM_MCR_BRSTDMA_Pos)         /*!< 0xC0000000 */

+#define HRTIM_MCR_BRSTDMA             HRTIM_MCR_BRSTDMA_Msk                    /*!< Burst DMA update */

+#define HRTIM_MCR_BRSTDMA_0           (0x1UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x40000000 */

+#define HRTIM_MCR_BRSTDMA_1           (0x2UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x80000000 */

+

+/******************** Master Timer Interrupt status register ******************/

+#define HRTIM_MISR_MCMP1_Pos          (0U)

+#define HRTIM_MISR_MCMP1_Msk          (0x1UL << HRTIM_MISR_MCMP1_Pos)          /*!< 0x00000001 */

+#define HRTIM_MISR_MCMP1              HRTIM_MISR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag */

+#define HRTIM_MISR_MCMP2_Pos          (1U)

+#define HRTIM_MISR_MCMP2_Msk          (0x1UL << HRTIM_MISR_MCMP2_Pos)          /*!< 0x00000002 */

+#define HRTIM_MISR_MCMP2              HRTIM_MISR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag */

+#define HRTIM_MISR_MCMP3_Pos          (2U)

+#define HRTIM_MISR_MCMP3_Msk          (0x1UL << HRTIM_MISR_MCMP3_Pos)          /*!< 0x00000004 */

+#define HRTIM_MISR_MCMP3              HRTIM_MISR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag */

+#define HRTIM_MISR_MCMP4_Pos          (3U)

+#define HRTIM_MISR_MCMP4_Msk          (0x1UL << HRTIM_MISR_MCMP4_Pos)          /*!< 0x00000008 */

+#define HRTIM_MISR_MCMP4              HRTIM_MISR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag */

+#define HRTIM_MISR_MREP_Pos           (4U)

+#define HRTIM_MISR_MREP_Msk           (0x1UL << HRTIM_MISR_MREP_Pos)           /*!< 0x00000010 */

+#define HRTIM_MISR_MREP               HRTIM_MISR_MREP_Msk                      /*!< Master Repetition interrupt flag */

+#define HRTIM_MISR_SYNC_Pos           (5U)

+#define HRTIM_MISR_SYNC_Msk           (0x1UL << HRTIM_MISR_SYNC_Pos)           /*!< 0x00000020 */

+#define HRTIM_MISR_SYNC               HRTIM_MISR_SYNC_Msk                      /*!< Synchronization input interrupt flag */

+#define HRTIM_MISR_MUPD_Pos           (6U)

+#define HRTIM_MISR_MUPD_Msk           (0x1UL << HRTIM_MISR_MUPD_Pos)           /*!< 0x00000040 */

+#define HRTIM_MISR_MUPD               HRTIM_MISR_MUPD_Msk                      /*!< Master update interrupt flag */

+

+/******************** Master Timer Interrupt clear register *******************/

+#define HRTIM_MICR_MCMP1_Pos          (0U)

+#define HRTIM_MICR_MCMP1_Msk          (0x1UL << HRTIM_MICR_MCMP1_Pos)          /*!< 0x00000001 */

+#define HRTIM_MICR_MCMP1              HRTIM_MICR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag clear */

+#define HRTIM_MICR_MCMP2_Pos          (1U)

+#define HRTIM_MICR_MCMP2_Msk          (0x1UL << HRTIM_MICR_MCMP2_Pos)          /*!< 0x00000002 */

+#define HRTIM_MICR_MCMP2              HRTIM_MICR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag clear */

+#define HRTIM_MICR_MCMP3_Pos          (2U)

+#define HRTIM_MICR_MCMP3_Msk          (0x1UL << HRTIM_MICR_MCMP3_Pos)          /*!< 0x00000004 */

+#define HRTIM_MICR_MCMP3              HRTIM_MICR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag clear */

+#define HRTIM_MICR_MCMP4_Pos          (3U)

+#define HRTIM_MICR_MCMP4_Msk          (0x1UL << HRTIM_MICR_MCMP4_Pos)          /*!< 0x00000008 */

+#define HRTIM_MICR_MCMP4              HRTIM_MICR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag clear */

+#define HRTIM_MICR_MREP_Pos           (4U)

+#define HRTIM_MICR_MREP_Msk           (0x1UL << HRTIM_MICR_MREP_Pos)           /*!< 0x00000010 */

+#define HRTIM_MICR_MREP               HRTIM_MICR_MREP_Msk                      /*!< Master Repetition interrupt flag clear */

+#define HRTIM_MICR_SYNC_Pos           (5U)

+#define HRTIM_MICR_SYNC_Msk           (0x1UL << HRTIM_MICR_SYNC_Pos)           /*!< 0x00000020 */

+#define HRTIM_MICR_SYNC               HRTIM_MICR_SYNC_Msk                      /*!< Synchronization input interrupt flag clear */

+#define HRTIM_MICR_MUPD_Pos           (6U)

+#define HRTIM_MICR_MUPD_Msk           (0x1UL << HRTIM_MICR_MUPD_Pos)           /*!< 0x00000040 */

+#define HRTIM_MICR_MUPD               HRTIM_MICR_MUPD_Msk                      /*!< Master update interrupt flag clear */

+

+/******************** Master Timer DMA/Interrupt enable register **************/

+#define HRTIM_MDIER_MCMP1IE_Pos       (0U)

+#define HRTIM_MDIER_MCMP1IE_Msk       (0x1UL << HRTIM_MDIER_MCMP1IE_Pos)       /*!< 0x00000001 */

+#define HRTIM_MDIER_MCMP1IE           HRTIM_MDIER_MCMP1IE_Msk                  /*!< Master compare 1 interrupt enable */

+#define HRTIM_MDIER_MCMP2IE_Pos       (1U)

+#define HRTIM_MDIER_MCMP2IE_Msk       (0x1UL << HRTIM_MDIER_MCMP2IE_Pos)       /*!< 0x00000002 */

+#define HRTIM_MDIER_MCMP2IE           HRTIM_MDIER_MCMP2IE_Msk                  /*!< Master compare 2 interrupt enable */

+#define HRTIM_MDIER_MCMP3IE_Pos       (2U)

+#define HRTIM_MDIER_MCMP3IE_Msk       (0x1UL << HRTIM_MDIER_MCMP3IE_Pos)       /*!< 0x00000004 */

+#define HRTIM_MDIER_MCMP3IE           HRTIM_MDIER_MCMP3IE_Msk                  /*!< Master compare 3 interrupt enable */

+#define HRTIM_MDIER_MCMP4IE_Pos       (3U)

+#define HRTIM_MDIER_MCMP4IE_Msk       (0x1UL << HRTIM_MDIER_MCMP4IE_Pos)       /*!< 0x00000008 */

+#define HRTIM_MDIER_MCMP4IE           HRTIM_MDIER_MCMP4IE_Msk                  /*!< Master compare 4 interrupt enable */

+#define HRTIM_MDIER_MREPIE_Pos        (4U)

+#define HRTIM_MDIER_MREPIE_Msk        (0x1UL << HRTIM_MDIER_MREPIE_Pos)        /*!< 0x00000010 */

+#define HRTIM_MDIER_MREPIE            HRTIM_MDIER_MREPIE_Msk                   /*!< Master Repetition interrupt enable */

+#define HRTIM_MDIER_SYNCIE_Pos        (5U)

+#define HRTIM_MDIER_SYNCIE_Msk        (0x1UL << HRTIM_MDIER_SYNCIE_Pos)        /*!< 0x00000020 */

+#define HRTIM_MDIER_SYNCIE            HRTIM_MDIER_SYNCIE_Msk                   /*!< Synchronization input interrupt enable */

+#define HRTIM_MDIER_MUPDIE_Pos        (6U)

+#define HRTIM_MDIER_MUPDIE_Msk        (0x1UL << HRTIM_MDIER_MUPDIE_Pos)        /*!< 0x00000040 */

+#define HRTIM_MDIER_MUPDIE            HRTIM_MDIER_MUPDIE_Msk                   /*!< Master update interrupt enable */

+

+#define HRTIM_MDIER_MCMP1DE_Pos       (16U)

+#define HRTIM_MDIER_MCMP1DE_Msk       (0x1UL << HRTIM_MDIER_MCMP1DE_Pos)       /*!< 0x00010000 */

+#define HRTIM_MDIER_MCMP1DE           HRTIM_MDIER_MCMP1DE_Msk                  /*!< Master compare 1 DMA enable */

+#define HRTIM_MDIER_MCMP2DE_Pos       (17U)

+#define HRTIM_MDIER_MCMP2DE_Msk       (0x1UL << HRTIM_MDIER_MCMP2DE_Pos)       /*!< 0x00020000 */

+#define HRTIM_MDIER_MCMP2DE           HRTIM_MDIER_MCMP2DE_Msk                  /*!< Master compare 2 DMA enable */

+#define HRTIM_MDIER_MCMP3DE_Pos       (18U)

+#define HRTIM_MDIER_MCMP3DE_Msk       (0x1UL << HRTIM_MDIER_MCMP3DE_Pos)       /*!< 0x00040000 */

+#define HRTIM_MDIER_MCMP3DE           HRTIM_MDIER_MCMP3DE_Msk                  /*!< Master compare 3 DMA enable */

+#define HRTIM_MDIER_MCMP4DE_Pos       (19U)

+#define HRTIM_MDIER_MCMP4DE_Msk       (0x1UL << HRTIM_MDIER_MCMP4DE_Pos)       /*!< 0x00080000 */

+#define HRTIM_MDIER_MCMP4DE           HRTIM_MDIER_MCMP4DE_Msk                  /*!< Master compare 4 DMA enable */

+#define HRTIM_MDIER_MREPDE_Pos        (20U)

+#define HRTIM_MDIER_MREPDE_Msk        (0x1UL << HRTIM_MDIER_MREPDE_Pos)        /*!< 0x00100000 */

+#define HRTIM_MDIER_MREPDE            HRTIM_MDIER_MREPDE_Msk                   /*!< Master Repetition DMA enable */

+#define HRTIM_MDIER_SYNCDE_Pos        (21U)

+#define HRTIM_MDIER_SYNCDE_Msk        (0x1UL << HRTIM_MDIER_SYNCDE_Pos)        /*!< 0x00200000 */

+#define HRTIM_MDIER_SYNCDE            HRTIM_MDIER_SYNCDE_Msk                   /*!< Synchronization input DMA enable */

+#define HRTIM_MDIER_MUPDDE_Pos        (22U)

+#define HRTIM_MDIER_MUPDDE_Msk        (0x1UL << HRTIM_MDIER_MUPDDE_Pos)        /*!< 0x00400000 */

+#define HRTIM_MDIER_MUPDDE            HRTIM_MDIER_MUPDDE_Msk                   /*!< Master update DMA enable */

+

+/*******************  Bit definition for HRTIM_MCNTR register  ****************/

+#define HRTIM_MCNTR_MCNTR_Pos         (0U)

+#define HRTIM_MCNTR_MCNTR_Msk         (0xFFFFUL << HRTIM_MCNTR_MCNTR_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_MCNTR_MCNTR             HRTIM_MCNTR_MCNTR_Msk                    /*!<Counter Value */

+

+/*******************  Bit definition for HRTIM_MPER register  *****************/

+#define HRTIM_MPER_MPER_Pos           (0U)

+#define HRTIM_MPER_MPER_Msk           (0xFFFFUL << HRTIM_MPER_MPER_Pos)        /*!< 0x0000FFFF */

+#define HRTIM_MPER_MPER               HRTIM_MPER_MPER_Msk                      /*!< Period Value */

+

+/*******************  Bit definition for HRTIM_MREP register  *****************/

+#define HRTIM_MREP_MREP_Pos           (0U)

+#define HRTIM_MREP_MREP_Msk           (0xFFUL << HRTIM_MREP_MREP_Pos)          /*!< 0x000000FF */

+#define HRTIM_MREP_MREP               HRTIM_MREP_MREP_Msk                      /*!<Repetition Value */

+

+/*******************  Bit definition for HRTIM_MCMP1R register  *****************/

+#define HRTIM_MCMP1R_MCMP1R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP1R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP1R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP1R           HRTIM_MCMP1R_MCMP1R_Msk                  /*!<Compare Value */

+

+/*******************  Bit definition for HRTIM_MCMP2R register  *****************/

+#define HRTIM_MCMP1R_MCMP2R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP2R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP2R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP2R           HRTIM_MCMP1R_MCMP2R_Msk                  /*!<Compare Value */

+

+/*******************  Bit definition for HRTIM_MCMP3R register  *****************/

+#define HRTIM_MCMP1R_MCMP3R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP3R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP3R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP3R           HRTIM_MCMP1R_MCMP3R_Msk                  /*!<Compare Value */

+

+/*******************  Bit definition for HRTIM_MCMP4R register  *****************/

+#define HRTIM_MCMP1R_MCMP4R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP4R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP4R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP4R           HRTIM_MCMP1R_MCMP4R_Msk                  /*!<Compare Value */

+

+/******************** Slave control register **********************************/

+#define HRTIM_TIMCR_CK_PSC_Pos        (0U)

+#define HRTIM_TIMCR_CK_PSC_Msk        (0x7UL << HRTIM_TIMCR_CK_PSC_Pos)        /*!< 0x00000007 */

+#define HRTIM_TIMCR_CK_PSC            HRTIM_TIMCR_CK_PSC_Msk                   /*!< Slave prescaler mask*/

+#define HRTIM_TIMCR_CK_PSC_0          (0x1UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000001 */

+#define HRTIM_TIMCR_CK_PSC_1          (0x2UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000002 */

+#define HRTIM_TIMCR_CK_PSC_2          (0x4UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000004 */

+

+#define HRTIM_TIMCR_CONT_Pos          (3U)

+#define HRTIM_TIMCR_CONT_Msk          (0x1UL << HRTIM_TIMCR_CONT_Pos)          /*!< 0x00000008 */

+#define HRTIM_TIMCR_CONT              HRTIM_TIMCR_CONT_Msk                     /*!< Slave continuous mode */

+#define HRTIM_TIMCR_RETRIG_Pos        (4U)

+#define HRTIM_TIMCR_RETRIG_Msk        (0x1UL << HRTIM_TIMCR_RETRIG_Pos)        /*!< 0x00000010 */

+#define HRTIM_TIMCR_RETRIG            HRTIM_TIMCR_RETRIG_Msk                   /*!< Slave Retrigreable mode */

+#define HRTIM_TIMCR_HALF_Pos          (5U)

+#define HRTIM_TIMCR_HALF_Msk          (0x1UL << HRTIM_TIMCR_HALF_Pos)          /*!< 0x00000020 */

+#define HRTIM_TIMCR_HALF              HRTIM_TIMCR_HALF_Msk                     /*!< Slave Half mode */

+#define HRTIM_TIMCR_PSHPLL_Pos        (6U)

+#define HRTIM_TIMCR_PSHPLL_Msk        (0x1UL << HRTIM_TIMCR_PSHPLL_Pos)        /*!< 0x00000040 */

+#define HRTIM_TIMCR_PSHPLL            HRTIM_TIMCR_PSHPLL_Msk                   /*!< Slave push-pull mode */

+

+#define HRTIM_TIMCR_SYNCRST_Pos       (10U)

+#define HRTIM_TIMCR_SYNCRST_Msk       (0x1UL << HRTIM_TIMCR_SYNCRST_Pos)       /*!< 0x00000400 */

+#define HRTIM_TIMCR_SYNCRST           HRTIM_TIMCR_SYNCRST_Msk                  /*!< Slave synchronization resets */

+#define HRTIM_TIMCR_SYNCSTRT_Pos      (11U)

+#define HRTIM_TIMCR_SYNCSTRT_Msk      (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos)      /*!< 0x00000800 */

+#define HRTIM_TIMCR_SYNCSTRT          HRTIM_TIMCR_SYNCSTRT_Msk                 /*!< Slave synchronization starts */

+

+#define HRTIM_TIMCR_DELCMP2_Pos       (12U)

+#define HRTIM_TIMCR_DELCMP2_Msk       (0x3UL << HRTIM_TIMCR_DELCMP2_Pos)       /*!< 0x00003000 */

+#define HRTIM_TIMCR_DELCMP2           HRTIM_TIMCR_DELCMP2_Msk                  /*!< Slave delayed compartor 2 mode mask */

+#define HRTIM_TIMCR_DELCMP2_0         (0x1UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00001000 */

+#define HRTIM_TIMCR_DELCMP2_1         (0x2UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00002000 */

+#define HRTIM_TIMCR_DELCMP4_Pos       (14U)

+#define HRTIM_TIMCR_DELCMP4_Msk       (0x3UL << HRTIM_TIMCR_DELCMP4_Pos)       /*!< 0x0000C000 */

+#define HRTIM_TIMCR_DELCMP4           HRTIM_TIMCR_DELCMP4_Msk                  /*!< Slave delayed compartor 4 mode mask */

+#define HRTIM_TIMCR_DELCMP4_0         (0x1UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00004000 */

+#define HRTIM_TIMCR_DELCMP4_1         (0x2UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00008000 */

+

+#define HRTIM_TIMCR_TREPU_Pos         (17U)

+#define HRTIM_TIMCR_TREPU_Msk         (0x1UL << HRTIM_TIMCR_TREPU_Pos)         /*!< 0x00020000 */

+#define HRTIM_TIMCR_TREPU             HRTIM_TIMCR_TREPU_Msk                    /*!< Slave repetition update */

+#define HRTIM_TIMCR_TRSTU_Pos         (18U)

+#define HRTIM_TIMCR_TRSTU_Msk         (0x1UL << HRTIM_TIMCR_TRSTU_Pos)         /*!< 0x00040000 */

+#define HRTIM_TIMCR_TRSTU             HRTIM_TIMCR_TRSTU_Msk                    /*!< Slave reset update */

+#define HRTIM_TIMCR_TAU_Pos           (19U)

+#define HRTIM_TIMCR_TAU_Msk           (0x1UL << HRTIM_TIMCR_TAU_Pos)           /*!< 0x00080000 */

+#define HRTIM_TIMCR_TAU               HRTIM_TIMCR_TAU_Msk                      /*!< Slave Timer A update reserved for TIM A */

+#define HRTIM_TIMCR_TBU_Pos           (20U)

+#define HRTIM_TIMCR_TBU_Msk           (0x1UL << HRTIM_TIMCR_TBU_Pos)           /*!< 0x00100000 */

+#define HRTIM_TIMCR_TBU               HRTIM_TIMCR_TBU_Msk                      /*!< Slave Timer B update reserved for TIM B */

+#define HRTIM_TIMCR_TCU_Pos           (21U)

+#define HRTIM_TIMCR_TCU_Msk           (0x1UL << HRTIM_TIMCR_TCU_Pos)           /*!< 0x00200000 */

+#define HRTIM_TIMCR_TCU               HRTIM_TIMCR_TCU_Msk                      /*!< Slave Timer C update reserved for TIM C */

+#define HRTIM_TIMCR_TDU_Pos           (22U)

+#define HRTIM_TIMCR_TDU_Msk           (0x1UL << HRTIM_TIMCR_TDU_Pos)           /*!< 0x00400000 */

+#define HRTIM_TIMCR_TDU               HRTIM_TIMCR_TDU_Msk                      /*!< Slave Timer D update reserved for TIM D */

+#define HRTIM_TIMCR_TEU_Pos           (23U)

+#define HRTIM_TIMCR_TEU_Msk           (0x1UL << HRTIM_TIMCR_TEU_Pos)           /*!< 0x00800000 */

+#define HRTIM_TIMCR_TEU               HRTIM_TIMCR_TEU_Msk                      /*!< Slave Timer E update reserved for TIM E */

+#define HRTIM_TIMCR_MSTU_Pos          (24U)

+#define HRTIM_TIMCR_MSTU_Msk          (0x1UL << HRTIM_TIMCR_MSTU_Pos)          /*!< 0x01000000 */

+#define HRTIM_TIMCR_MSTU              HRTIM_TIMCR_MSTU_Msk                     /*!< Master Update */

+

+#define HRTIM_TIMCR_DACSYNC_Pos       (25U)

+#define HRTIM_TIMCR_DACSYNC_Msk       (0x3UL << HRTIM_TIMCR_DACSYNC_Pos)       /*!< 0x06000000 */

+#define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC sychronization mask */

+#define HRTIM_TIMCR_DACSYNC_0         (0x1UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x02000000 */

+#define HRTIM_TIMCR_DACSYNC_1         (0x2UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x04000000 */

+#define HRTIM_TIMCR_PREEN_Pos         (27U)

+#define HRTIM_TIMCR_PREEN_Msk         (0x1UL << HRTIM_TIMCR_PREEN_Pos)         /*!< 0x08000000 */

+#define HRTIM_TIMCR_PREEN             HRTIM_TIMCR_PREEN_Msk                    /*!< Slave preload enable */

+

+#define HRTIM_TIMCR_UPDGAT_Pos        (28U)

+#define HRTIM_TIMCR_UPDGAT_Msk        (0xFUL << HRTIM_TIMCR_UPDGAT_Pos)        /*!< 0xF0000000 */

+#define HRTIM_TIMCR_UPDGAT            HRTIM_TIMCR_UPDGAT_Msk                   /*!< Slave update gating mask */

+#define HRTIM_TIMCR_UPDGAT_0          (0x1UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x10000000 */

+#define HRTIM_TIMCR_UPDGAT_1          (0x2UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x20000000 */

+#define HRTIM_TIMCR_UPDGAT_2          (0x4UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x40000000 */

+#define HRTIM_TIMCR_UPDGAT_3          (0x8UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x80000000 */

+

+/******************** Slave Interrupt status register **************************/

+#define HRTIM_TIMISR_CMP1_Pos         (0U)

+#define HRTIM_TIMISR_CMP1_Msk         (0x1UL << HRTIM_TIMISR_CMP1_Pos)         /*!< 0x00000001 */

+#define HRTIM_TIMISR_CMP1             HRTIM_TIMISR_CMP1_Msk                    /*!< Slave compare 1 interrupt flag */

+#define HRTIM_TIMISR_CMP2_Pos         (1U)

+#define HRTIM_TIMISR_CMP2_Msk         (0x1UL << HRTIM_TIMISR_CMP2_Pos)         /*!< 0x00000002 */

+#define HRTIM_TIMISR_CMP2             HRTIM_TIMISR_CMP2_Msk                    /*!< Slave compare 2 interrupt flag */

+#define HRTIM_TIMISR_CMP3_Pos         (2U)

+#define HRTIM_TIMISR_CMP3_Msk         (0x1UL << HRTIM_TIMISR_CMP3_Pos)         /*!< 0x00000004 */

+#define HRTIM_TIMISR_CMP3             HRTIM_TIMISR_CMP3_Msk                    /*!< Slave compare 3 interrupt flag */

+#define HRTIM_TIMISR_CMP4_Pos         (3U)

+#define HRTIM_TIMISR_CMP4_Msk         (0x1UL << HRTIM_TIMISR_CMP4_Pos)         /*!< 0x00000008 */

+#define HRTIM_TIMISR_CMP4             HRTIM_TIMISR_CMP4_Msk                    /*!< Slave compare 4 interrupt flag */

+#define HRTIM_TIMISR_REP_Pos          (4U)

+#define HRTIM_TIMISR_REP_Msk          (0x1UL << HRTIM_TIMISR_REP_Pos)          /*!< 0x00000010 */

+#define HRTIM_TIMISR_REP              HRTIM_TIMISR_REP_Msk                     /*!< Slave repetition interrupt flag */

+#define HRTIM_TIMISR_UPD_Pos          (6U)

+#define HRTIM_TIMISR_UPD_Msk          (0x1UL << HRTIM_TIMISR_UPD_Pos)          /*!< 0x00000040 */

+#define HRTIM_TIMISR_UPD              HRTIM_TIMISR_UPD_Msk                     /*!< Slave update interrupt flag */

+#define HRTIM_TIMISR_CPT1_Pos         (7U)

+#define HRTIM_TIMISR_CPT1_Msk         (0x1UL << HRTIM_TIMISR_CPT1_Pos)         /*!< 0x00000080 */

+#define HRTIM_TIMISR_CPT1             HRTIM_TIMISR_CPT1_Msk                    /*!< Slave capture 1 interrupt flag */

+#define HRTIM_TIMISR_CPT2_Pos         (8U)

+#define HRTIM_TIMISR_CPT2_Msk         (0x1UL << HRTIM_TIMISR_CPT2_Pos)         /*!< 0x00000100 */

+#define HRTIM_TIMISR_CPT2             HRTIM_TIMISR_CPT2_Msk                    /*!< Slave capture 2 interrupt flag */

+#define HRTIM_TIMISR_SET1_Pos         (9U)

+#define HRTIM_TIMISR_SET1_Msk         (0x1UL << HRTIM_TIMISR_SET1_Pos)         /*!< 0x00000200 */

+#define HRTIM_TIMISR_SET1             HRTIM_TIMISR_SET1_Msk                    /*!< Slave output 1 set interrupt flag */

+#define HRTIM_TIMISR_RST1_Pos         (10U)

+#define HRTIM_TIMISR_RST1_Msk         (0x1UL << HRTIM_TIMISR_RST1_Pos)         /*!< 0x00000400 */

+#define HRTIM_TIMISR_RST1             HRTIM_TIMISR_RST1_Msk                    /*!< Slave output 1 reset interrupt flag */

+#define HRTIM_TIMISR_SET2_Pos         (11U)

+#define HRTIM_TIMISR_SET2_Msk         (0x1UL << HRTIM_TIMISR_SET2_Pos)         /*!< 0x00000800 */

+#define HRTIM_TIMISR_SET2             HRTIM_TIMISR_SET2_Msk                    /*!< Slave output 2 set interrupt flag */

+#define HRTIM_TIMISR_RST2_Pos         (12U)

+#define HRTIM_TIMISR_RST2_Msk         (0x1UL << HRTIM_TIMISR_RST2_Pos)         /*!< 0x00001000 */

+#define HRTIM_TIMISR_RST2             HRTIM_TIMISR_RST2_Msk                    /*!< Slave output 2 reset interrupt flag */

+#define HRTIM_TIMISR_RST_Pos          (13U)

+#define HRTIM_TIMISR_RST_Msk          (0x1UL << HRTIM_TIMISR_RST_Pos)          /*!< 0x00002000 */

+#define HRTIM_TIMISR_RST              HRTIM_TIMISR_RST_Msk                     /*!< Slave reset interrupt flag */

+#define HRTIM_TIMISR_DLYPRT_Pos       (14U)

+#define HRTIM_TIMISR_DLYPRT_Msk       (0x1UL << HRTIM_TIMISR_DLYPRT_Pos)       /*!< 0x00004000 */

+#define HRTIM_TIMISR_DLYPRT           HRTIM_TIMISR_DLYPRT_Msk                  /*!< Slave output 1 delay protection interrupt flag */

+#define HRTIM_TIMISR_CPPSTAT_Pos      (16U)

+#define HRTIM_TIMISR_CPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos)      /*!< 0x00010000 */

+#define HRTIM_TIMISR_CPPSTAT          HRTIM_TIMISR_CPPSTAT_Msk                 /*!< Slave current push-pull flag */

+#define HRTIM_TIMISR_IPPSTAT_Pos      (17U)

+#define HRTIM_TIMISR_IPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos)      /*!< 0x00020000 */

+#define HRTIM_TIMISR_IPPSTAT          HRTIM_TIMISR_IPPSTAT_Msk                 /*!< Slave idle push-pull flag */

+#define HRTIM_TIMISR_O1STAT_Pos       (18U)

+#define HRTIM_TIMISR_O1STAT_Msk       (0x1UL << HRTIM_TIMISR_O1STAT_Pos)       /*!< 0x00040000 */

+#define HRTIM_TIMISR_O1STAT           HRTIM_TIMISR_O1STAT_Msk                  /*!< Slave output 1 state flag */

+#define HRTIM_TIMISR_O2STAT_Pos       (19U)

+#define HRTIM_TIMISR_O2STAT_Msk       (0x1UL << HRTIM_TIMISR_O2STAT_Pos)       /*!< 0x00080000 */

+#define HRTIM_TIMISR_O2STAT           HRTIM_TIMISR_O2STAT_Msk                  /*!< Slave output 2 state flag */

+#define HRTIM_TIMISR_O1CPY_Pos        (20U)

+#define HRTIM_TIMISR_O1CPY_Msk        (0x1UL << HRTIM_TIMISR_O1CPY_Pos)        /*!< 0x00100000 */

+#define HRTIM_TIMISR_O1CPY            HRTIM_TIMISR_O1CPY_Msk                   /*!< Slave output 1 copy flag */

+#define HRTIM_TIMISR_O2CPY_Pos        (21U)

+#define HRTIM_TIMISR_O2CPY_Msk        (0x1UL << HRTIM_TIMISR_O2CPY_Pos)        /*!< 0x00200000 */

+#define HRTIM_TIMISR_O2CPY            HRTIM_TIMISR_O2CPY_Msk                   /*!< Slave output 2 copy flag */

+

+/******************** Slave Interrupt clear register **************************/

+#define HRTIM_TIMICR_CMP1C_Pos        (0U)

+#define HRTIM_TIMICR_CMP1C_Msk        (0x1UL << HRTIM_TIMICR_CMP1C_Pos)        /*!< 0x00000001 */

+#define HRTIM_TIMICR_CMP1C            HRTIM_TIMICR_CMP1C_Msk                   /*!< Slave compare 1 clear flag */

+#define HRTIM_TIMICR_CMP2C_Pos        (1U)

+#define HRTIM_TIMICR_CMP2C_Msk        (0x1UL << HRTIM_TIMICR_CMP2C_Pos)        /*!< 0x00000002 */

+#define HRTIM_TIMICR_CMP2C            HRTIM_TIMICR_CMP2C_Msk                   /*!< Slave compare 2 clear flag */

+#define HRTIM_TIMICR_CMP3C_Pos        (2U)

+#define HRTIM_TIMICR_CMP3C_Msk        (0x1UL << HRTIM_TIMICR_CMP3C_Pos)        /*!< 0x00000004 */

+#define HRTIM_TIMICR_CMP3C            HRTIM_TIMICR_CMP3C_Msk                   /*!< Slave compare 3 clear flag */

+#define HRTIM_TIMICR_CMP4C_Pos        (3U)

+#define HRTIM_TIMICR_CMP4C_Msk        (0x1UL << HRTIM_TIMICR_CMP4C_Pos)        /*!< 0x00000008 */

+#define HRTIM_TIMICR_CMP4C            HRTIM_TIMICR_CMP4C_Msk                   /*!< Slave compare 4 clear flag */

+#define HRTIM_TIMICR_REPC_Pos         (4U)

+#define HRTIM_TIMICR_REPC_Msk         (0x1UL << HRTIM_TIMICR_REPC_Pos)         /*!< 0x00000010 */

+#define HRTIM_TIMICR_REPC             HRTIM_TIMICR_REPC_Msk                    /*!< Slave repetition clear flag */

+#define HRTIM_TIMICR_UPDC_Pos         (6U)

+#define HRTIM_TIMICR_UPDC_Msk         (0x1UL << HRTIM_TIMICR_UPDC_Pos)         /*!< 0x00000040 */

+#define HRTIM_TIMICR_UPDC             HRTIM_TIMICR_UPDC_Msk                    /*!< Slave update clear flag */

+#define HRTIM_TIMICR_CPT1C_Pos        (7U)

+#define HRTIM_TIMICR_CPT1C_Msk        (0x1UL << HRTIM_TIMICR_CPT1C_Pos)        /*!< 0x00000080 */

+#define HRTIM_TIMICR_CPT1C            HRTIM_TIMICR_CPT1C_Msk                   /*!< Slave capture 1 clear flag */

+#define HRTIM_TIMICR_CPT2C_Pos        (8U)

+#define HRTIM_TIMICR_CPT2C_Msk        (0x1UL << HRTIM_TIMICR_CPT2C_Pos)        /*!< 0x00000100 */

+#define HRTIM_TIMICR_CPT2C            HRTIM_TIMICR_CPT2C_Msk                   /*!< Slave capture 2 clear flag */

+#define HRTIM_TIMICR_SET1C_Pos        (9U)

+#define HRTIM_TIMICR_SET1C_Msk        (0x1UL << HRTIM_TIMICR_SET1C_Pos)        /*!< 0x00000200 */

+#define HRTIM_TIMICR_SET1C            HRTIM_TIMICR_SET1C_Msk                   /*!< Slave output 1 set clear flag */

+#define HRTIM_TIMICR_RST1C_Pos        (10U)

+#define HRTIM_TIMICR_RST1C_Msk        (0x1UL << HRTIM_TIMICR_RST1C_Pos)        /*!< 0x00000400 */

+#define HRTIM_TIMICR_RST1C            HRTIM_TIMICR_RST1C_Msk                   /*!< Slave output 1 reset clear flag */

+#define HRTIM_TIMICR_SET2C_Pos        (11U)

+#define HRTIM_TIMICR_SET2C_Msk        (0x1UL << HRTIM_TIMICR_SET2C_Pos)        /*!< 0x00000800 */

+#define HRTIM_TIMICR_SET2C            HRTIM_TIMICR_SET2C_Msk                   /*!< Slave output 2 set clear flag */

+#define HRTIM_TIMICR_RST2C_Pos        (12U)

+#define HRTIM_TIMICR_RST2C_Msk        (0x1UL << HRTIM_TIMICR_RST2C_Pos)        /*!< 0x00001000 */

+#define HRTIM_TIMICR_RST2C            HRTIM_TIMICR_RST2C_Msk                   /*!< Slave output 2 reset clear flag */

+#define HRTIM_TIMICR_RSTC_Pos         (13U)

+#define HRTIM_TIMICR_RSTC_Msk         (0x1UL << HRTIM_TIMICR_RSTC_Pos)         /*!< 0x00002000 */

+#define HRTIM_TIMICR_RSTC             HRTIM_TIMICR_RSTC_Msk                    /*!< Slave reset clear flag */

+#define HRTIM_TIMICR_DLYPRTC_Pos      (14U)

+#define HRTIM_TIMICR_DLYPRTC_Msk      (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos)      /*!< 0x00004000 */

+#define HRTIM_TIMICR_DLYPRTC          HRTIM_TIMICR_DLYPRTC_Msk                 /*!< Slave output 1 delay protection clear flag */

+

+/******************** Slave DMA/Interrupt enable register *********************/

+#define HRTIM_TIMDIER_CMP1IE_Pos      (0U)

+#define HRTIM_TIMDIER_CMP1IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos)      /*!< 0x00000001 */

+#define HRTIM_TIMDIER_CMP1IE          HRTIM_TIMDIER_CMP1IE_Msk                 /*!< Slave compare 1 interrupt enable */

+#define HRTIM_TIMDIER_CMP2IE_Pos      (1U)

+#define HRTIM_TIMDIER_CMP2IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos)      /*!< 0x00000002 */

+#define HRTIM_TIMDIER_CMP2IE          HRTIM_TIMDIER_CMP2IE_Msk                 /*!< Slave compare 2 interrupt enable */

+#define HRTIM_TIMDIER_CMP3IE_Pos      (2U)

+#define HRTIM_TIMDIER_CMP3IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos)      /*!< 0x00000004 */

+#define HRTIM_TIMDIER_CMP3IE          HRTIM_TIMDIER_CMP3IE_Msk                 /*!< Slave compare 3 interrupt enable */

+#define HRTIM_TIMDIER_CMP4IE_Pos      (3U)

+#define HRTIM_TIMDIER_CMP4IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos)      /*!< 0x00000008 */

+#define HRTIM_TIMDIER_CMP4IE          HRTIM_TIMDIER_CMP4IE_Msk                 /*!< Slave compare 4 interrupt enable */

+#define HRTIM_TIMDIER_REPIE_Pos       (4U)

+#define HRTIM_TIMDIER_REPIE_Msk       (0x1UL << HRTIM_TIMDIER_REPIE_Pos)       /*!< 0x00000010 */

+#define HRTIM_TIMDIER_REPIE           HRTIM_TIMDIER_REPIE_Msk                  /*!< Slave repetition interrupt enable */

+#define HRTIM_TIMDIER_UPDIE_Pos       (6U)

+#define HRTIM_TIMDIER_UPDIE_Msk       (0x1UL << HRTIM_TIMDIER_UPDIE_Pos)       /*!< 0x00000040 */

+#define HRTIM_TIMDIER_UPDIE           HRTIM_TIMDIER_UPDIE_Msk                  /*!< Slave update interrupt enable */

+#define HRTIM_TIMDIER_CPT1IE_Pos      (7U)

+#define HRTIM_TIMDIER_CPT1IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos)      /*!< 0x00000080 */

+#define HRTIM_TIMDIER_CPT1IE          HRTIM_TIMDIER_CPT1IE_Msk                 /*!< Slave capture 1 interrupt enable */

+#define HRTIM_TIMDIER_CPT2IE_Pos      (8U)

+#define HRTIM_TIMDIER_CPT2IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos)      /*!< 0x00000100 */

+#define HRTIM_TIMDIER_CPT2IE          HRTIM_TIMDIER_CPT2IE_Msk                 /*!< Slave capture 2 interrupt enable */

+#define HRTIM_TIMDIER_SET1IE_Pos      (9U)

+#define HRTIM_TIMDIER_SET1IE_Msk      (0x1UL << HRTIM_TIMDIER_SET1IE_Pos)      /*!< 0x00000200 */

+#define HRTIM_TIMDIER_SET1IE          HRTIM_TIMDIER_SET1IE_Msk                 /*!< Slave output 1 set interrupt enable */

+#define HRTIM_TIMDIER_RST1IE_Pos      (10U)

+#define HRTIM_TIMDIER_RST1IE_Msk      (0x1UL << HRTIM_TIMDIER_RST1IE_Pos)      /*!< 0x00000400 */

+#define HRTIM_TIMDIER_RST1IE          HRTIM_TIMDIER_RST1IE_Msk                 /*!< Slave output 1 reset interrupt enable */

+#define HRTIM_TIMDIER_SET2IE_Pos      (11U)

+#define HRTIM_TIMDIER_SET2IE_Msk      (0x1UL << HRTIM_TIMDIER_SET2IE_Pos)      /*!< 0x00000800 */

+#define HRTIM_TIMDIER_SET2IE          HRTIM_TIMDIER_SET2IE_Msk                 /*!< Slave output 2 set interrupt enable */

+#define HRTIM_TIMDIER_RST2IE_Pos      (12U)

+#define HRTIM_TIMDIER_RST2IE_Msk      (0x1UL << HRTIM_TIMDIER_RST2IE_Pos)      /*!< 0x00001000 */

+#define HRTIM_TIMDIER_RST2IE          HRTIM_TIMDIER_RST2IE_Msk                 /*!< Slave output 2 reset interrupt enable */

+#define HRTIM_TIMDIER_RSTIE_Pos       (13U)

+#define HRTIM_TIMDIER_RSTIE_Msk       (0x1UL << HRTIM_TIMDIER_RSTIE_Pos)       /*!< 0x00002000 */

+#define HRTIM_TIMDIER_RSTIE           HRTIM_TIMDIER_RSTIE_Msk                  /*!< Slave reset interrupt enable */

+#define HRTIM_TIMDIER_DLYPRTIE_Pos    (14U)

+#define HRTIM_TIMDIER_DLYPRTIE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos)    /*!< 0x00004000 */

+#define HRTIM_TIMDIER_DLYPRTIE        HRTIM_TIMDIER_DLYPRTIE_Msk               /*!< Slave delay protection interrupt enable */

+

+#define HRTIM_TIMDIER_CMP1DE_Pos      (16U)

+#define HRTIM_TIMDIER_CMP1DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos)      /*!< 0x00010000 */

+#define HRTIM_TIMDIER_CMP1DE          HRTIM_TIMDIER_CMP1DE_Msk                 /*!< Slave compare 1 request enable */

+#define HRTIM_TIMDIER_CMP2DE_Pos      (17U)

+#define HRTIM_TIMDIER_CMP2DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos)      /*!< 0x00020000 */

+#define HRTIM_TIMDIER_CMP2DE          HRTIM_TIMDIER_CMP2DE_Msk                 /*!< Slave compare 2 request enable */

+#define HRTIM_TIMDIER_CMP3DE_Pos      (18U)

+#define HRTIM_TIMDIER_CMP3DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos)      /*!< 0x00040000 */

+#define HRTIM_TIMDIER_CMP3DE          HRTIM_TIMDIER_CMP3DE_Msk                 /*!< Slave compare 3 request enable */

+#define HRTIM_TIMDIER_CMP4DE_Pos      (19U)

+#define HRTIM_TIMDIER_CMP4DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos)      /*!< 0x00080000 */

+#define HRTIM_TIMDIER_CMP4DE          HRTIM_TIMDIER_CMP4DE_Msk                 /*!< Slave compare 4 request enable */

+#define HRTIM_TIMDIER_REPDE_Pos       (20U)

+#define HRTIM_TIMDIER_REPDE_Msk       (0x1UL << HRTIM_TIMDIER_REPDE_Pos)       /*!< 0x00100000 */

+#define HRTIM_TIMDIER_REPDE           HRTIM_TIMDIER_REPDE_Msk                  /*!< Slave repetition request enable */

+#define HRTIM_TIMDIER_UPDDE_Pos       (22U)

+#define HRTIM_TIMDIER_UPDDE_Msk       (0x1UL << HRTIM_TIMDIER_UPDDE_Pos)       /*!< 0x00400000 */

+#define HRTIM_TIMDIER_UPDDE           HRTIM_TIMDIER_UPDDE_Msk                  /*!< Slave update request enable */

+#define HRTIM_TIMDIER_CPT1DE_Pos      (23U)

+#define HRTIM_TIMDIER_CPT1DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos)      /*!< 0x00800000 */

+#define HRTIM_TIMDIER_CPT1DE          HRTIM_TIMDIER_CPT1DE_Msk                 /*!< Slave capture 1 request enable */

+#define HRTIM_TIMDIER_CPT2DE_Pos      (24U)

+#define HRTIM_TIMDIER_CPT2DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos)      /*!< 0x01000000 */

+#define HRTIM_TIMDIER_CPT2DE          HRTIM_TIMDIER_CPT2DE_Msk                 /*!< Slave capture 2 request enable */

+#define HRTIM_TIMDIER_SET1DE_Pos      (25U)

+#define HRTIM_TIMDIER_SET1DE_Msk      (0x1UL << HRTIM_TIMDIER_SET1DE_Pos)      /*!< 0x02000000 */

+#define HRTIM_TIMDIER_SET1DE          HRTIM_TIMDIER_SET1DE_Msk                 /*!< Slave output 1 set request enable */

+#define HRTIM_TIMDIER_RST1DE_Pos      (26U)

+#define HRTIM_TIMDIER_RST1DE_Msk      (0x1UL << HRTIM_TIMDIER_RST1DE_Pos)      /*!< 0x04000000 */

+#define HRTIM_TIMDIER_RST1DE          HRTIM_TIMDIER_RST1DE_Msk                 /*!< Slave output 1 reset request enable */

+#define HRTIM_TIMDIER_SET2DE_Pos      (27U)

+#define HRTIM_TIMDIER_SET2DE_Msk      (0x1UL << HRTIM_TIMDIER_SET2DE_Pos)      /*!< 0x08000000 */

+#define HRTIM_TIMDIER_SET2DE          HRTIM_TIMDIER_SET2DE_Msk                 /*!< Slave output 2 set request enable */

+#define HRTIM_TIMDIER_RST2DE_Pos      (28U)

+#define HRTIM_TIMDIER_RST2DE_Msk      (0x1UL << HRTIM_TIMDIER_RST2DE_Pos)      /*!< 0x10000000 */

+#define HRTIM_TIMDIER_RST2DE          HRTIM_TIMDIER_RST2DE_Msk                 /*!< Slave output 2 reset request enable */

+#define HRTIM_TIMDIER_RSTDE_Pos       (29U)

+#define HRTIM_TIMDIER_RSTDE_Msk       (0x1UL << HRTIM_TIMDIER_RSTDE_Pos)       /*!< 0x20000000 */

+#define HRTIM_TIMDIER_RSTDE           HRTIM_TIMDIER_RSTDE_Msk                  /*!< Slave reset request enable */

+#define HRTIM_TIMDIER_DLYPRTDE_Pos    (30U)

+#define HRTIM_TIMDIER_DLYPRTDE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos)    /*!< 0x40000000 */

+#define HRTIM_TIMDIER_DLYPRTDE        HRTIM_TIMDIER_DLYPRTDE_Msk               /*!< Slavedelay protection request enable */

+

+/******************  Bit definition for HRTIM_CNTR register  ****************/

+#define HRTIM_CNTR_CNTR_Pos           (0U)

+#define HRTIM_CNTR_CNTR_Msk           (0xFFFFUL << HRTIM_CNTR_CNTR_Pos)        /*!< 0x0000FFFF */

+#define HRTIM_CNTR_CNTR               HRTIM_CNTR_CNTR_Msk                      /*!< Counter Value */

+

+/*******************  Bit definition for HRTIM_PER register  *****************/

+#define HRTIM_PER_PER_Pos             (0U)

+#define HRTIM_PER_PER_Msk             (0xFFFFUL << HRTIM_PER_PER_Pos)          /*!< 0x0000FFFF */

+#define HRTIM_PER_PER                 HRTIM_PER_PER_Msk                        /*!< Period Value */

+

+/*******************  Bit definition for HRTIM_REP register  *****************/

+#define HRTIM_REP_REP_Pos             (0U)

+#define HRTIM_REP_REP_Msk             (0xFFUL << HRTIM_REP_REP_Pos)            /*!< 0x000000FF */

+#define HRTIM_REP_REP                 HRTIM_REP_REP_Msk                        /*!< Repetition Value */

+

+/*******************  Bit definition for HRTIM_CMP1R register  *****************/

+#define HRTIM_CMP1R_CMP1R_Pos         (0U)

+#define HRTIM_CMP1R_CMP1R_Msk         (0xFFFFUL << HRTIM_CMP1R_CMP1R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP1R_CMP1R             HRTIM_CMP1R_CMP1R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP1CR register  *****************/

+#define HRTIM_CMP1CR_CMP1CR_Pos       (0U)

+#define HRTIM_CMP1CR_CMP1CR_Msk       (0xFFFFFFFFUL << HRTIM_CMP1CR_CMP1CR_Pos) /*!< 0xFFFFFFFF */

+#define HRTIM_CMP1CR_CMP1CR           HRTIM_CMP1CR_CMP1CR_Msk                  /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP2R register  *****************/

+#define HRTIM_CMP2R_CMP2R_Pos         (0U)

+#define HRTIM_CMP2R_CMP2R_Msk         (0xFFFFUL << HRTIM_CMP2R_CMP2R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP2R_CMP2R             HRTIM_CMP2R_CMP2R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP3R register  *****************/

+#define HRTIM_CMP3R_CMP3R_Pos         (0U)

+#define HRTIM_CMP3R_CMP3R_Msk         (0xFFFFUL << HRTIM_CMP3R_CMP3R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP3R_CMP3R             HRTIM_CMP3R_CMP3R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP4R register  *****************/

+#define HRTIM_CMP4R_CMP4R_Pos         (0U)

+#define HRTIM_CMP4R_CMP4R_Msk         (0xFFFFUL << HRTIM_CMP4R_CMP4R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP4R_CMP4R             HRTIM_CMP4R_CMP4R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CPT1R register  ****************/

+#define HRTIM_CPT1R_CPT1R_Pos         (0U)

+#define HRTIM_CPT1R_CPT1R_Msk         (0xFFFFUL << HRTIM_CPT1R_CPT1R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CPT1R_CPT1R             HRTIM_CPT1R_CPT1R_Msk                    /*!< Capture Value */

+

+/*******************  Bit definition for HRTIM_CPT2R register  ****************/

+#define HRTIM_CPT2R_CPT2R_Pos         (0U)

+#define HRTIM_CPT2R_CPT2R_Msk         (0xFFFFUL << HRTIM_CPT2R_CPT2R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CPT2R_CPT2R             HRTIM_CPT2R_CPT2R_Msk                    /*!< Capture Value */

+

+/******************** Bit definition for Slave Deadtime register **************/

+#define HRTIM_DTR_DTR_Pos             (0U)

+#define HRTIM_DTR_DTR_Msk             (0x1FFUL << HRTIM_DTR_DTR_Pos)           /*!< 0x000001FF */

+#define HRTIM_DTR_DTR                 HRTIM_DTR_DTR_Msk                        /*!< Dead time rising value */

+#define HRTIM_DTR_DTR_0               (0x001UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000001 */

+#define HRTIM_DTR_DTR_1               (0x002UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000002 */

+#define HRTIM_DTR_DTR_2               (0x004UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000004 */

+#define HRTIM_DTR_DTR_3               (0x008UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000008 */

+#define HRTIM_DTR_DTR_4               (0x010UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000010 */

+#define HRTIM_DTR_DTR_5               (0x020UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000020 */

+#define HRTIM_DTR_DTR_6               (0x040UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000040 */

+#define HRTIM_DTR_DTR_7               (0x080UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000080 */

+#define HRTIM_DTR_DTR_8               (0x100UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000100 */

+#define HRTIM_DTR_SDTR_Pos            (9U)

+#define HRTIM_DTR_SDTR_Msk            (0x1UL << HRTIM_DTR_SDTR_Pos)            /*!< 0x00000200 */

+#define HRTIM_DTR_SDTR                HRTIM_DTR_SDTR_Msk                       /*!< Sign dead time rising value */

+#define HRTIM_DTR_DTPRSC_Pos          (10U)

+#define HRTIM_DTR_DTPRSC_Msk          (0x7UL << HRTIM_DTR_DTPRSC_Pos)          /*!< 0x00001C00 */

+#define HRTIM_DTR_DTPRSC              HRTIM_DTR_DTPRSC_Msk                     /*!< Dead time prescaler */

+#define HRTIM_DTR_DTPRSC_0            (0x1UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000400 */

+#define HRTIM_DTR_DTPRSC_1            (0x2UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000800 */

+#define HRTIM_DTR_DTPRSC_2            (0x4UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00001000 */

+#define HRTIM_DTR_DTRSLK_Pos          (14U)

+#define HRTIM_DTR_DTRSLK_Msk          (0x1UL << HRTIM_DTR_DTRSLK_Pos)          /*!< 0x00004000 */

+#define HRTIM_DTR_DTRSLK              HRTIM_DTR_DTRSLK_Msk                     /*!< Dead time rising sign lock */

+#define HRTIM_DTR_DTRLK_Pos           (15U)

+#define HRTIM_DTR_DTRLK_Msk           (0x1UL << HRTIM_DTR_DTRLK_Pos)           /*!< 0x00008000 */

+#define HRTIM_DTR_DTRLK               HRTIM_DTR_DTRLK_Msk                      /*!< Dead time rising lock */

+#define HRTIM_DTR_DTF_Pos             (16U)

+#define HRTIM_DTR_DTF_Msk             (0x1FFUL << HRTIM_DTR_DTF_Pos)           /*!< 0x01FF0000 */

+#define HRTIM_DTR_DTF                 HRTIM_DTR_DTF_Msk                        /*!< Dead time falling value */

+#define HRTIM_DTR_DTF_0               (0x001UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00010000 */

+#define HRTIM_DTR_DTF_1               (0x002UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00020000 */

+#define HRTIM_DTR_DTF_2               (0x004UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00040000 */

+#define HRTIM_DTR_DTF_3               (0x008UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00080000 */

+#define HRTIM_DTR_DTF_4               (0x010UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00100000 */

+#define HRTIM_DTR_DTF_5               (0x020UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00200000 */

+#define HRTIM_DTR_DTF_6               (0x040UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00400000 */

+#define HRTIM_DTR_DTF_7               (0x080UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00800000 */

+#define HRTIM_DTR_DTF_8               (0x100UL << HRTIM_DTR_DTF_Pos)            /*!< 0x01000000 */

+#define HRTIM_DTR_SDTF_Pos            (25U)

+#define HRTIM_DTR_SDTF_Msk            (0x1UL << HRTIM_DTR_SDTF_Pos)            /*!< 0x02000000 */

+#define HRTIM_DTR_SDTF                HRTIM_DTR_SDTF_Msk                       /*!< Sign dead time falling value */

+#define HRTIM_DTR_DTFSLK_Pos          (30U)

+#define HRTIM_DTR_DTFSLK_Msk          (0x1UL << HRTIM_DTR_DTFSLK_Pos)          /*!< 0x40000000 */

+#define HRTIM_DTR_DTFSLK              HRTIM_DTR_DTFSLK_Msk                     /*!< Dead time falling sign lock */

+#define HRTIM_DTR_DTFLK_Pos           (31U)

+#define HRTIM_DTR_DTFLK_Msk           (0x1UL << HRTIM_DTR_DTFLK_Pos)           /*!< 0x80000000 */

+#define HRTIM_DTR_DTFLK               HRTIM_DTR_DTFLK_Msk                      /*!< Dead time falling lock */

+

+/**** Bit definition for Slave Output 1 set register **************************/

+#define HRTIM_SET1R_SST_Pos           (0U)

+#define HRTIM_SET1R_SST_Msk           (0x1UL << HRTIM_SET1R_SST_Pos)           /*!< 0x00000001 */

+#define HRTIM_SET1R_SST               HRTIM_SET1R_SST_Msk                      /*!< software set trigger */

+#define HRTIM_SET1R_RESYNC_Pos        (1U)

+#define HRTIM_SET1R_RESYNC_Msk        (0x1UL << HRTIM_SET1R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_SET1R_RESYNC            HRTIM_SET1R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_SET1R_PER_Pos           (2U)

+#define HRTIM_SET1R_PER_Msk           (0x1UL << HRTIM_SET1R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_SET1R_PER               HRTIM_SET1R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_SET1R_CMP1_Pos          (3U)

+#define HRTIM_SET1R_CMP1_Msk          (0x1UL << HRTIM_SET1R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_SET1R_CMP1              HRTIM_SET1R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_SET1R_CMP2_Pos          (4U)

+#define HRTIM_SET1R_CMP2_Msk          (0x1UL << HRTIM_SET1R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_SET1R_CMP2              HRTIM_SET1R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_SET1R_CMP3_Pos          (5U)

+#define HRTIM_SET1R_CMP3_Msk          (0x1UL << HRTIM_SET1R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_SET1R_CMP3              HRTIM_SET1R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_SET1R_CMP4_Pos          (6U)

+#define HRTIM_SET1R_CMP4_Msk          (0x1UL << HRTIM_SET1R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_SET1R_CMP4              HRTIM_SET1R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_SET1R_MSTPER_Pos        (7U)

+#define HRTIM_SET1R_MSTPER_Msk        (0x1UL << HRTIM_SET1R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_SET1R_MSTPER            HRTIM_SET1R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_SET1R_MSTCMP1_Pos       (8U)

+#define HRTIM_SET1R_MSTCMP1_Msk       (0x1UL << HRTIM_SET1R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_SET1R_MSTCMP1           HRTIM_SET1R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_SET1R_MSTCMP2_Pos       (9U)

+#define HRTIM_SET1R_MSTCMP2_Msk       (0x1UL << HRTIM_SET1R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_SET1R_MSTCMP2           HRTIM_SET1R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_SET1R_MSTCMP3_Pos       (10U)

+#define HRTIM_SET1R_MSTCMP3_Msk       (0x1UL << HRTIM_SET1R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_SET1R_MSTCMP3           HRTIM_SET1R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_SET1R_MSTCMP4_Pos       (11U)

+#define HRTIM_SET1R_MSTCMP4_Msk       (0x1UL << HRTIM_SET1R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_SET1R_MSTCMP4           HRTIM_SET1R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_SET1R_TIMEVNT1_Pos      (12U)

+#define HRTIM_SET1R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_SET1R_TIMEVNT1          HRTIM_SET1R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_SET1R_TIMEVNT2_Pos      (13U)

+#define HRTIM_SET1R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_SET1R_TIMEVNT2          HRTIM_SET1R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_SET1R_TIMEVNT3_Pos      (14U)

+#define HRTIM_SET1R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_SET1R_TIMEVNT3          HRTIM_SET1R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_SET1R_TIMEVNT4_Pos      (15U)

+#define HRTIM_SET1R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_SET1R_TIMEVNT4          HRTIM_SET1R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_SET1R_TIMEVNT5_Pos      (16U)

+#define HRTIM_SET1R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_SET1R_TIMEVNT5          HRTIM_SET1R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_SET1R_TIMEVNT6_Pos      (17U)

+#define HRTIM_SET1R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_SET1R_TIMEVNT6          HRTIM_SET1R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_SET1R_TIMEVNT7_Pos      (18U)

+#define HRTIM_SET1R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_SET1R_TIMEVNT7          HRTIM_SET1R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_SET1R_TIMEVNT8_Pos      (19U)

+#define HRTIM_SET1R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_SET1R_TIMEVNT8          HRTIM_SET1R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_SET1R_TIMEVNT9_Pos      (20U)

+#define HRTIM_SET1R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_SET1R_TIMEVNT9          HRTIM_SET1R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_SET1R_EXTVNT1_Pos       (21U)

+#define HRTIM_SET1R_EXTVNT1_Msk       (0x1UL << HRTIM_SET1R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_SET1R_EXTVNT1           HRTIM_SET1R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_SET1R_EXTVNT2_Pos       (22U)

+#define HRTIM_SET1R_EXTVNT2_Msk       (0x1UL << HRTIM_SET1R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_SET1R_EXTVNT2           HRTIM_SET1R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_SET1R_EXTVNT3_Pos       (23U)

+#define HRTIM_SET1R_EXTVNT3_Msk       (0x1UL << HRTIM_SET1R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_SET1R_EXTVNT3           HRTIM_SET1R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_SET1R_EXTVNT4_Pos       (24U)

+#define HRTIM_SET1R_EXTVNT4_Msk       (0x1UL << HRTIM_SET1R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_SET1R_EXTVNT4           HRTIM_SET1R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_SET1R_EXTVNT5_Pos       (25U)

+#define HRTIM_SET1R_EXTVNT5_Msk       (0x1UL << HRTIM_SET1R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_SET1R_EXTVNT5           HRTIM_SET1R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_SET1R_EXTVNT6_Pos       (26U)

+#define HRTIM_SET1R_EXTVNT6_Msk       (0x1UL << HRTIM_SET1R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_SET1R_EXTVNT6           HRTIM_SET1R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_SET1R_EXTVNT7_Pos       (27U)

+#define HRTIM_SET1R_EXTVNT7_Msk       (0x1UL << HRTIM_SET1R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_SET1R_EXTVNT7           HRTIM_SET1R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_SET1R_EXTVNT8_Pos       (28U)

+#define HRTIM_SET1R_EXTVNT8_Msk       (0x1UL << HRTIM_SET1R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_SET1R_EXTVNT8           HRTIM_SET1R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_SET1R_EXTVNT9_Pos       (29U)

+#define HRTIM_SET1R_EXTVNT9_Msk       (0x1UL << HRTIM_SET1R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_SET1R_EXTVNT9           HRTIM_SET1R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_SET1R_EXTVNT10_Pos      (30U)

+#define HRTIM_SET1R_EXTVNT10_Msk      (0x1UL << HRTIM_SET1R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_SET1R_EXTVNT10          HRTIM_SET1R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_SET1R_UPDATE_Pos        (31U)

+#define HRTIM_SET1R_UPDATE_Msk        (0x1UL << HRTIM_SET1R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_SET1R_UPDATE            HRTIM_SET1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+/**** Bit definition for Slave Output 1 reset register ************************/

+#define HRTIM_RST1R_SRT_Pos           (0U)

+#define HRTIM_RST1R_SRT_Msk           (0x1UL << HRTIM_RST1R_SRT_Pos)           /*!< 0x00000001 */

+#define HRTIM_RST1R_SRT               HRTIM_RST1R_SRT_Msk                      /*!< software reset trigger */

+#define HRTIM_RST1R_RESYNC_Pos        (1U)

+#define HRTIM_RST1R_RESYNC_Msk        (0x1UL << HRTIM_RST1R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_RST1R_RESYNC            HRTIM_RST1R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_RST1R_PER_Pos           (2U)

+#define HRTIM_RST1R_PER_Msk           (0x1UL << HRTIM_RST1R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_RST1R_PER               HRTIM_RST1R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_RST1R_CMP1_Pos          (3U)

+#define HRTIM_RST1R_CMP1_Msk          (0x1UL << HRTIM_RST1R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_RST1R_CMP1              HRTIM_RST1R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_RST1R_CMP2_Pos          (4U)

+#define HRTIM_RST1R_CMP2_Msk          (0x1UL << HRTIM_RST1R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_RST1R_CMP2              HRTIM_RST1R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_RST1R_CMP3_Pos          (5U)

+#define HRTIM_RST1R_CMP3_Msk          (0x1UL << HRTIM_RST1R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_RST1R_CMP3              HRTIM_RST1R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_RST1R_CMP4_Pos          (6U)

+#define HRTIM_RST1R_CMP4_Msk          (0x1UL << HRTIM_RST1R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_RST1R_CMP4              HRTIM_RST1R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_RST1R_MSTPER_Pos        (7U)

+#define HRTIM_RST1R_MSTPER_Msk        (0x1UL << HRTIM_RST1R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_RST1R_MSTPER            HRTIM_RST1R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_RST1R_MSTCMP1_Pos       (8U)

+#define HRTIM_RST1R_MSTCMP1_Msk       (0x1UL << HRTIM_RST1R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_RST1R_MSTCMP1           HRTIM_RST1R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_RST1R_MSTCMP2_Pos       (9U)

+#define HRTIM_RST1R_MSTCMP2_Msk       (0x1UL << HRTIM_RST1R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_RST1R_MSTCMP2           HRTIM_RST1R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_RST1R_MSTCMP3_Pos       (10U)

+#define HRTIM_RST1R_MSTCMP3_Msk       (0x1UL << HRTIM_RST1R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_RST1R_MSTCMP3           HRTIM_RST1R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_RST1R_MSTCMP4_Pos       (11U)

+#define HRTIM_RST1R_MSTCMP4_Msk       (0x1UL << HRTIM_RST1R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_RST1R_MSTCMP4           HRTIM_RST1R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_RST1R_TIMEVNT1_Pos      (12U)

+#define HRTIM_RST1R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_RST1R_TIMEVNT1          HRTIM_RST1R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_RST1R_TIMEVNT2_Pos      (13U)

+#define HRTIM_RST1R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_RST1R_TIMEVNT2          HRTIM_RST1R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_RST1R_TIMEVNT3_Pos      (14U)

+#define HRTIM_RST1R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_RST1R_TIMEVNT3          HRTIM_RST1R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_RST1R_TIMEVNT4_Pos      (15U)

+#define HRTIM_RST1R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_RST1R_TIMEVNT4          HRTIM_RST1R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_RST1R_TIMEVNT5_Pos      (16U)

+#define HRTIM_RST1R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_RST1R_TIMEVNT5          HRTIM_RST1R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_RST1R_TIMEVNT6_Pos      (17U)

+#define HRTIM_RST1R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_RST1R_TIMEVNT6          HRTIM_RST1R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_RST1R_TIMEVNT7_Pos      (18U)

+#define HRTIM_RST1R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_RST1R_TIMEVNT7          HRTIM_RST1R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_RST1R_TIMEVNT8_Pos      (19U)

+#define HRTIM_RST1R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_RST1R_TIMEVNT8          HRTIM_RST1R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_RST1R_TIMEVNT9_Pos      (20U)

+#define HRTIM_RST1R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_RST1R_TIMEVNT9          HRTIM_RST1R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_RST1R_EXTVNT1_Pos       (21U)

+#define HRTIM_RST1R_EXTVNT1_Msk       (0x1UL << HRTIM_RST1R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_RST1R_EXTVNT1           HRTIM_RST1R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_RST1R_EXTVNT2_Pos       (22U)

+#define HRTIM_RST1R_EXTVNT2_Msk       (0x1UL << HRTIM_RST1R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_RST1R_EXTVNT2           HRTIM_RST1R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_RST1R_EXTVNT3_Pos       (23U)

+#define HRTIM_RST1R_EXTVNT3_Msk       (0x1UL << HRTIM_RST1R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_RST1R_EXTVNT3           HRTIM_RST1R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_RST1R_EXTVNT4_Pos       (24U)

+#define HRTIM_RST1R_EXTVNT4_Msk       (0x1UL << HRTIM_RST1R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_RST1R_EXTVNT4           HRTIM_RST1R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_RST1R_EXTVNT5_Pos       (25U)

+#define HRTIM_RST1R_EXTVNT5_Msk       (0x1UL << HRTIM_RST1R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_RST1R_EXTVNT5           HRTIM_RST1R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_RST1R_EXTVNT6_Pos       (26U)

+#define HRTIM_RST1R_EXTVNT6_Msk       (0x1UL << HRTIM_RST1R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_RST1R_EXTVNT6           HRTIM_RST1R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_RST1R_EXTVNT7_Pos       (27U)

+#define HRTIM_RST1R_EXTVNT7_Msk       (0x1UL << HRTIM_RST1R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_RST1R_EXTVNT7           HRTIM_RST1R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_RST1R_EXTVNT8_Pos       (28U)

+#define HRTIM_RST1R_EXTVNT8_Msk       (0x1UL << HRTIM_RST1R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_RST1R_EXTVNT8           HRTIM_RST1R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_RST1R_EXTVNT9_Pos       (29U)

+#define HRTIM_RST1R_EXTVNT9_Msk       (0x1UL << HRTIM_RST1R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_RST1R_EXTVNT9           HRTIM_RST1R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_RST1R_EXTVNT10_Pos      (30U)

+#define HRTIM_RST1R_EXTVNT10_Msk      (0x1UL << HRTIM_RST1R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_RST1R_EXTVNT10          HRTIM_RST1R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_RST1R_UPDATE_Pos        (31U)

+#define HRTIM_RST1R_UPDATE_Msk        (0x1UL << HRTIM_RST1R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_RST1R_UPDATE            HRTIM_RST1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+

+/**** Bit definition for Slave Output 2 set register **************************/

+#define HRTIM_SET2R_SST_Pos           (0U)

+#define HRTIM_SET2R_SST_Msk           (0x1UL << HRTIM_SET2R_SST_Pos)           /*!< 0x00000001 */

+#define HRTIM_SET2R_SST               HRTIM_SET2R_SST_Msk                      /*!< software set trigger */

+#define HRTIM_SET2R_RESYNC_Pos        (1U)

+#define HRTIM_SET2R_RESYNC_Msk        (0x1UL << HRTIM_SET2R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_SET2R_RESYNC            HRTIM_SET2R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_SET2R_PER_Pos           (2U)

+#define HRTIM_SET2R_PER_Msk           (0x1UL << HRTIM_SET2R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_SET2R_PER               HRTIM_SET2R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_SET2R_CMP1_Pos          (3U)

+#define HRTIM_SET2R_CMP1_Msk          (0x1UL << HRTIM_SET2R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_SET2R_CMP1              HRTIM_SET2R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_SET2R_CMP2_Pos          (4U)

+#define HRTIM_SET2R_CMP2_Msk          (0x1UL << HRTIM_SET2R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_SET2R_CMP2              HRTIM_SET2R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_SET2R_CMP3_Pos          (5U)

+#define HRTIM_SET2R_CMP3_Msk          (0x1UL << HRTIM_SET2R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_SET2R_CMP3              HRTIM_SET2R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_SET2R_CMP4_Pos          (6U)

+#define HRTIM_SET2R_CMP4_Msk          (0x1UL << HRTIM_SET2R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_SET2R_CMP4              HRTIM_SET2R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_SET2R_MSTPER_Pos        (7U)

+#define HRTIM_SET2R_MSTPER_Msk        (0x1UL << HRTIM_SET2R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_SET2R_MSTPER            HRTIM_SET2R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_SET2R_MSTCMP1_Pos       (8U)

+#define HRTIM_SET2R_MSTCMP1_Msk       (0x1UL << HRTIM_SET2R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_SET2R_MSTCMP1           HRTIM_SET2R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_SET2R_MSTCMP2_Pos       (9U)

+#define HRTIM_SET2R_MSTCMP2_Msk       (0x1UL << HRTIM_SET2R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_SET2R_MSTCMP2           HRTIM_SET2R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_SET2R_MSTCMP3_Pos       (10U)

+#define HRTIM_SET2R_MSTCMP3_Msk       (0x1UL << HRTIM_SET2R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_SET2R_MSTCMP3           HRTIM_SET2R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_SET2R_MSTCMP4_Pos       (11U)

+#define HRTIM_SET2R_MSTCMP4_Msk       (0x1UL << HRTIM_SET2R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_SET2R_MSTCMP4           HRTIM_SET2R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_SET2R_TIMEVNT1_Pos      (12U)

+#define HRTIM_SET2R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_SET2R_TIMEVNT1          HRTIM_SET2R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_SET2R_TIMEVNT2_Pos      (13U)

+#define HRTIM_SET2R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_SET2R_TIMEVNT2          HRTIM_SET2R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_SET2R_TIMEVNT3_Pos      (14U)

+#define HRTIM_SET2R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_SET2R_TIMEVNT3          HRTIM_SET2R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_SET2R_TIMEVNT4_Pos      (15U)

+#define HRTIM_SET2R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_SET2R_TIMEVNT4          HRTIM_SET2R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_SET2R_TIMEVNT5_Pos      (16U)

+#define HRTIM_SET2R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_SET2R_TIMEVNT5          HRTIM_SET2R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_SET2R_TIMEVNT6_Pos      (17U)

+#define HRTIM_SET2R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_SET2R_TIMEVNT6          HRTIM_SET2R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_SET2R_TIMEVNT7_Pos      (18U)

+#define HRTIM_SET2R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_SET2R_TIMEVNT7          HRTIM_SET2R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_SET2R_TIMEVNT8_Pos      (19U)

+#define HRTIM_SET2R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_SET2R_TIMEVNT8          HRTIM_SET2R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_SET2R_TIMEVNT9_Pos      (20U)

+#define HRTIM_SET2R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_SET2R_TIMEVNT9          HRTIM_SET2R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_SET2R_EXTVNT1_Pos       (21U)

+#define HRTIM_SET2R_EXTVNT1_Msk       (0x1UL << HRTIM_SET2R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_SET2R_EXTVNT1           HRTIM_SET2R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_SET2R_EXTVNT2_Pos       (22U)

+#define HRTIM_SET2R_EXTVNT2_Msk       (0x1UL << HRTIM_SET2R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_SET2R_EXTVNT2           HRTIM_SET2R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_SET2R_EXTVNT3_Pos       (23U)

+#define HRTIM_SET2R_EXTVNT3_Msk       (0x1UL << HRTIM_SET2R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_SET2R_EXTVNT3           HRTIM_SET2R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_SET2R_EXTVNT4_Pos       (24U)

+#define HRTIM_SET2R_EXTVNT4_Msk       (0x1UL << HRTIM_SET2R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_SET2R_EXTVNT4           HRTIM_SET2R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_SET2R_EXTVNT5_Pos       (25U)

+#define HRTIM_SET2R_EXTVNT5_Msk       (0x1UL << HRTIM_SET2R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_SET2R_EXTVNT5           HRTIM_SET2R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_SET2R_EXTVNT6_Pos       (26U)

+#define HRTIM_SET2R_EXTVNT6_Msk       (0x1UL << HRTIM_SET2R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_SET2R_EXTVNT6           HRTIM_SET2R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_SET2R_EXTVNT7_Pos       (27U)

+#define HRTIM_SET2R_EXTVNT7_Msk       (0x1UL << HRTIM_SET2R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_SET2R_EXTVNT7           HRTIM_SET2R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_SET2R_EXTVNT8_Pos       (28U)

+#define HRTIM_SET2R_EXTVNT8_Msk       (0x1UL << HRTIM_SET2R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_SET2R_EXTVNT8           HRTIM_SET2R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_SET2R_EXTVNT9_Pos       (29U)

+#define HRTIM_SET2R_EXTVNT9_Msk       (0x1UL << HRTIM_SET2R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_SET2R_EXTVNT9           HRTIM_SET2R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_SET2R_EXTVNT10_Pos      (30U)

+#define HRTIM_SET2R_EXTVNT10_Msk      (0x1UL << HRTIM_SET2R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_SET2R_EXTVNT10          HRTIM_SET2R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_SET2R_UPDATE_Pos        (31U)

+#define HRTIM_SET2R_UPDATE_Msk        (0x1UL << HRTIM_SET2R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_SET2R_UPDATE            HRTIM_SET2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+/**** Bit definition for Slave Output 2 reset register ************************/

+#define HRTIM_RST2R_SRT_Pos           (0U)

+#define HRTIM_RST2R_SRT_Msk           (0x1UL << HRTIM_RST2R_SRT_Pos)           /*!< 0x00000001 */

+#define HRTIM_RST2R_SRT               HRTIM_RST2R_SRT_Msk                      /*!< software reset trigger */

+#define HRTIM_RST2R_RESYNC_Pos        (1U)

+#define HRTIM_RST2R_RESYNC_Msk        (0x1UL << HRTIM_RST2R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_RST2R_RESYNC            HRTIM_RST2R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_RST2R_PER_Pos           (2U)

+#define HRTIM_RST2R_PER_Msk           (0x1UL << HRTIM_RST2R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_RST2R_PER               HRTIM_RST2R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_RST2R_CMP1_Pos          (3U)

+#define HRTIM_RST2R_CMP1_Msk          (0x1UL << HRTIM_RST2R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_RST2R_CMP1              HRTIM_RST2R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_RST2R_CMP2_Pos          (4U)

+#define HRTIM_RST2R_CMP2_Msk          (0x1UL << HRTIM_RST2R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_RST2R_CMP2              HRTIM_RST2R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_RST2R_CMP3_Pos          (5U)

+#define HRTIM_RST2R_CMP3_Msk          (0x1UL << HRTIM_RST2R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_RST2R_CMP3              HRTIM_RST2R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_RST2R_CMP4_Pos          (6U)

+#define HRTIM_RST2R_CMP4_Msk          (0x1UL << HRTIM_RST2R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_RST2R_CMP4              HRTIM_RST2R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_RST2R_MSTPER_Pos        (7U)

+#define HRTIM_RST2R_MSTPER_Msk        (0x1UL << HRTIM_RST2R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_RST2R_MSTPER            HRTIM_RST2R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_RST2R_MSTCMP1_Pos       (8U)

+#define HRTIM_RST2R_MSTCMP1_Msk       (0x1UL << HRTIM_RST2R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_RST2R_MSTCMP1           HRTIM_RST2R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_RST2R_MSTCMP2_Pos       (9U)

+#define HRTIM_RST2R_MSTCMP2_Msk       (0x1UL << HRTIM_RST2R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_RST2R_MSTCMP2           HRTIM_RST2R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_RST2R_MSTCMP3_Pos       (10U)

+#define HRTIM_RST2R_MSTCMP3_Msk       (0x1UL << HRTIM_RST2R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_RST2R_MSTCMP3           HRTIM_RST2R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_RST2R_MSTCMP4_Pos       (11U)

+#define HRTIM_RST2R_MSTCMP4_Msk       (0x1UL << HRTIM_RST2R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_RST2R_MSTCMP4           HRTIM_RST2R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_RST2R_TIMEVNT1_Pos      (12U)

+#define HRTIM_RST2R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_RST2R_TIMEVNT1          HRTIM_RST2R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_RST2R_TIMEVNT2_Pos      (13U)

+#define HRTIM_RST2R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_RST2R_TIMEVNT2          HRTIM_RST2R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_RST2R_TIMEVNT3_Pos      (14U)

+#define HRTIM_RST2R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_RST2R_TIMEVNT3          HRTIM_RST2R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_RST2R_TIMEVNT4_Pos      (15U)

+#define HRTIM_RST2R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_RST2R_TIMEVNT4          HRTIM_RST2R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_RST2R_TIMEVNT5_Pos      (16U)

+#define HRTIM_RST2R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_RST2R_TIMEVNT5          HRTIM_RST2R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_RST2R_TIMEVNT6_Pos      (17U)

+#define HRTIM_RST2R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_RST2R_TIMEVNT6          HRTIM_RST2R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_RST2R_TIMEVNT7_Pos      (18U)

+#define HRTIM_RST2R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_RST2R_TIMEVNT7          HRTIM_RST2R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_RST2R_TIMEVNT8_Pos      (19U)

+#define HRTIM_RST2R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_RST2R_TIMEVNT8          HRTIM_RST2R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_RST2R_TIMEVNT9_Pos      (20U)

+#define HRTIM_RST2R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_RST2R_TIMEVNT9          HRTIM_RST2R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_RST2R_EXTVNT1_Pos       (21U)

+#define HRTIM_RST2R_EXTVNT1_Msk       (0x1UL << HRTIM_RST2R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_RST2R_EXTVNT1           HRTIM_RST2R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_RST2R_EXTVNT2_Pos       (22U)

+#define HRTIM_RST2R_EXTVNT2_Msk       (0x1UL << HRTIM_RST2R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_RST2R_EXTVNT2           HRTIM_RST2R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_RST2R_EXTVNT3_Pos       (23U)

+#define HRTIM_RST2R_EXTVNT3_Msk       (0x1UL << HRTIM_RST2R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_RST2R_EXTVNT3           HRTIM_RST2R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_RST2R_EXTVNT4_Pos       (24U)

+#define HRTIM_RST2R_EXTVNT4_Msk       (0x1UL << HRTIM_RST2R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_RST2R_EXTVNT4           HRTIM_RST2R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_RST2R_EXTVNT5_Pos       (25U)

+#define HRTIM_RST2R_EXTVNT5_Msk       (0x1UL << HRTIM_RST2R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_RST2R_EXTVNT5           HRTIM_RST2R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_RST2R_EXTVNT6_Pos       (26U)

+#define HRTIM_RST2R_EXTVNT6_Msk       (0x1UL << HRTIM_RST2R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_RST2R_EXTVNT6           HRTIM_RST2R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_RST2R_EXTVNT7_Pos       (27U)

+#define HRTIM_RST2R_EXTVNT7_Msk       (0x1UL << HRTIM_RST2R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_RST2R_EXTVNT7           HRTIM_RST2R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_RST2R_EXTVNT8_Pos       (28U)

+#define HRTIM_RST2R_EXTVNT8_Msk       (0x1UL << HRTIM_RST2R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_RST2R_EXTVNT8           HRTIM_RST2R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_RST2R_EXTVNT9_Pos       (29U)

+#define HRTIM_RST2R_EXTVNT9_Msk       (0x1UL << HRTIM_RST2R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_RST2R_EXTVNT9           HRTIM_RST2R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_RST2R_EXTVNT10_Pos      (30U)

+#define HRTIM_RST2R_EXTVNT10_Msk      (0x1UL << HRTIM_RST2R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_RST2R_EXTVNT10          HRTIM_RST2R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_RST2R_UPDATE_Pos        (31U)

+#define HRTIM_RST2R_UPDATE_Msk        (0x1UL << HRTIM_RST2R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_RST2R_UPDATE            HRTIM_RST2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+/**** Bit definition for Slave external event filtering  register 1 ***********/

+#define HRTIM_EEFR1_EE1LTCH_Pos       (0U)

+#define HRTIM_EEFR1_EE1LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos)       /*!< 0x00000001 */

+#define HRTIM_EEFR1_EE1LTCH           HRTIM_EEFR1_EE1LTCH_Msk                  /*!< External Event 1 latch */

+#define HRTIM_EEFR1_EE1FLTR_Pos       (1U)

+#define HRTIM_EEFR1_EE1FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos)       /*!< 0x0000001E */

+#define HRTIM_EEFR1_EE1FLTR           HRTIM_EEFR1_EE1FLTR_Msk                  /*!< External Event 1 filter mask */

+#define HRTIM_EEFR1_EE1FLTR_0         (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000002 */

+#define HRTIM_EEFR1_EE1FLTR_1         (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000004 */

+#define HRTIM_EEFR1_EE1FLTR_2         (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000008 */

+#define HRTIM_EEFR1_EE1FLTR_3         (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000010 */

+

+#define HRTIM_EEFR1_EE2LTCH_Pos       (6U)

+#define HRTIM_EEFR1_EE2LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos)       /*!< 0x00000040 */

+#define HRTIM_EEFR1_EE2LTCH           HRTIM_EEFR1_EE2LTCH_Msk                  /*!< External Event 2 latch */

+#define HRTIM_EEFR1_EE2FLTR_Pos       (7U)

+#define HRTIM_EEFR1_EE2FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos)       /*!< 0x00000780 */

+#define HRTIM_EEFR1_EE2FLTR           HRTIM_EEFR1_EE2FLTR_Msk                  /*!< External Event 2 filter mask */

+#define HRTIM_EEFR1_EE2FLTR_0         (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000080 */

+#define HRTIM_EEFR1_EE2FLTR_1         (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000100 */

+#define HRTIM_EEFR1_EE2FLTR_2         (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000200 */

+#define HRTIM_EEFR1_EE2FLTR_3         (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000400 */

+

+#define HRTIM_EEFR1_EE3LTCH_Pos       (12U)

+#define HRTIM_EEFR1_EE3LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos)       /*!< 0x00001000 */

+#define HRTIM_EEFR1_EE3LTCH           HRTIM_EEFR1_EE3LTCH_Msk                  /*!< External Event 3 latch */

+#define HRTIM_EEFR1_EE3FLTR_Pos       (13U)

+#define HRTIM_EEFR1_EE3FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos)       /*!< 0x0001E000 */

+#define HRTIM_EEFR1_EE3FLTR           HRTIM_EEFR1_EE3FLTR_Msk                  /*!< External Event 3 filter mask */

+#define HRTIM_EEFR1_EE3FLTR_0         (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00002000 */

+#define HRTIM_EEFR1_EE3FLTR_1         (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00004000 */

+#define HRTIM_EEFR1_EE3FLTR_2         (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00008000 */

+#define HRTIM_EEFR1_EE3FLTR_3         (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00010000 */

+

+#define HRTIM_EEFR1_EE4LTCH_Pos       (18U)

+#define HRTIM_EEFR1_EE4LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos)       /*!< 0x00040000 */

+#define HRTIM_EEFR1_EE4LTCH           HRTIM_EEFR1_EE4LTCH_Msk                  /*!< External Event 4 latch */

+#define HRTIM_EEFR1_EE4FLTR_Pos       (19U)

+#define HRTIM_EEFR1_EE4FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos)       /*!< 0x00780000 */

+#define HRTIM_EEFR1_EE4FLTR           HRTIM_EEFR1_EE4FLTR_Msk                  /*!< External Event 4 filter mask */

+#define HRTIM_EEFR1_EE4FLTR_0         (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00080000 */

+#define HRTIM_EEFR1_EE4FLTR_1         (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00100000 */

+#define HRTIM_EEFR1_EE4FLTR_2         (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00200000 */

+#define HRTIM_EEFR1_EE4FLTR_3         (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00400000 */

+

+#define HRTIM_EEFR1_EE5LTCH_Pos       (24U)

+#define HRTIM_EEFR1_EE5LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos)       /*!< 0x01000000 */

+#define HRTIM_EEFR1_EE5LTCH           HRTIM_EEFR1_EE5LTCH_Msk                  /*!< External Event 5 latch */

+#define HRTIM_EEFR1_EE5FLTR_Pos       (25U)

+#define HRTIM_EEFR1_EE5FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos)       /*!< 0x1E000000 */

+#define HRTIM_EEFR1_EE5FLTR           HRTIM_EEFR1_EE5FLTR_Msk                  /*!< External Event 5 filter mask */

+#define HRTIM_EEFR1_EE5FLTR_0         (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x02000000 */

+#define HRTIM_EEFR1_EE5FLTR_1         (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x04000000 */

+#define HRTIM_EEFR1_EE5FLTR_2         (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x08000000 */

+#define HRTIM_EEFR1_EE5FLTR_3         (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x10000000 */

+

+/**** Bit definition for Slave external event filtering  register 2 ***********/

+#define HRTIM_EEFR2_EE6LTCH_Pos       (0U)

+#define HRTIM_EEFR2_EE6LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos)       /*!< 0x00000001 */

+#define HRTIM_EEFR2_EE6LTCH           HRTIM_EEFR2_EE6LTCH_Msk                  /*!< External Event 6 latch */

+#define HRTIM_EEFR2_EE6FLTR_Pos       (1U)

+#define HRTIM_EEFR2_EE6FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos)       /*!< 0x0000001E */

+#define HRTIM_EEFR2_EE6FLTR           HRTIM_EEFR2_EE6FLTR_Msk                  /*!< External Event 6 filter mask */

+#define HRTIM_EEFR2_EE6FLTR_0         (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000002 */

+#define HRTIM_EEFR2_EE6FLTR_1         (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000004 */

+#define HRTIM_EEFR2_EE6FLTR_2         (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000008 */

+#define HRTIM_EEFR2_EE6FLTR_3         (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000010 */

+

+#define HRTIM_EEFR2_EE7LTCH_Pos       (6U)

+#define HRTIM_EEFR2_EE7LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos)       /*!< 0x00000040 */

+#define HRTIM_EEFR2_EE7LTCH           HRTIM_EEFR2_EE7LTCH_Msk                  /*!< External Event 7 latch */

+#define HRTIM_EEFR2_EE7FLTR_Pos       (7U)

+#define HRTIM_EEFR2_EE7FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos)       /*!< 0x00000780 */

+#define HRTIM_EEFR2_EE7FLTR           HRTIM_EEFR2_EE7FLTR_Msk                  /*!< External Event 7 filter mask */

+#define HRTIM_EEFR2_EE7FLTR_0         (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000080 */

+#define HRTIM_EEFR2_EE7FLTR_1         (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000100 */

+#define HRTIM_EEFR2_EE7FLTR_2         (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000200 */

+#define HRTIM_EEFR2_EE7FLTR_3         (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000400 */

+

+#define HRTIM_EEFR2_EE8LTCH_Pos       (12U)

+#define HRTIM_EEFR2_EE8LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos)       /*!< 0x00001000 */

+#define HRTIM_EEFR2_EE8LTCH           HRTIM_EEFR2_EE8LTCH_Msk                  /*!< External Event 8 latch */

+#define HRTIM_EEFR2_EE8FLTR_Pos       (13U)

+#define HRTIM_EEFR2_EE8FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos)       /*!< 0x0001E000 */

+#define HRTIM_EEFR2_EE8FLTR           HRTIM_EEFR2_EE8FLTR_Msk                  /*!< External Event 8 filter mask */

+#define HRTIM_EEFR2_EE8FLTR_0         (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00002000 */

+#define HRTIM_EEFR2_EE8FLTR_1         (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00004000 */

+#define HRTIM_EEFR2_EE8FLTR_2         (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00008000 */

+#define HRTIM_EEFR2_EE8FLTR_3         (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00010000 */

+

+#define HRTIM_EEFR2_EE9LTCH_Pos       (18U)

+#define HRTIM_EEFR2_EE9LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos)       /*!< 0x00040000 */

+#define HRTIM_EEFR2_EE9LTCH           HRTIM_EEFR2_EE9LTCH_Msk                  /*!< External Event 9 latch */

+#define HRTIM_EEFR2_EE9FLTR_Pos       (19U)

+#define HRTIM_EEFR2_EE9FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos)       /*!< 0x00780000 */

+#define HRTIM_EEFR2_EE9FLTR           HRTIM_EEFR2_EE9FLTR_Msk                  /*!< External Event 9 filter mask */

+#define HRTIM_EEFR2_EE9FLTR_0         (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00080000 */

+#define HRTIM_EEFR2_EE9FLTR_1         (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00100000 */

+#define HRTIM_EEFR2_EE9FLTR_2         (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00200000 */

+#define HRTIM_EEFR2_EE9FLTR_3         (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00400000 */

+

+#define HRTIM_EEFR2_EE10LTCH_Pos      (24U)

+#define HRTIM_EEFR2_EE10LTCH_Msk      (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos)      /*!< 0x01000000 */

+#define HRTIM_EEFR2_EE10LTCH          HRTIM_EEFR2_EE10LTCH_Msk                 /*!< External Event 10 latch */

+#define HRTIM_EEFR2_EE10FLTR_Pos      (25U)

+#define HRTIM_EEFR2_EE10FLTR_Msk      (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos)      /*!< 0x1E000000 */

+#define HRTIM_EEFR2_EE10FLTR          HRTIM_EEFR2_EE10FLTR_Msk                 /*!< External Event 10 filter mask */

+#define HRTIM_EEFR2_EE10FLTR_0        (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x02000000 */

+#define HRTIM_EEFR2_EE10FLTR_1        (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x04000000 */

+#define HRTIM_EEFR2_EE10FLTR_2        (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x08000000 */

+#define HRTIM_EEFR2_EE10FLTR_3        (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x10000000 */

+

+/**** Bit definition for Slave Timer reset register ***************************/

+#define HRTIM_RSTR_UPDATE_Pos         (1U)

+#define HRTIM_RSTR_UPDATE_Msk         (0x1UL << HRTIM_RSTR_UPDATE_Pos)         /*!< 0x00000002 */

+#define HRTIM_RSTR_UPDATE             HRTIM_RSTR_UPDATE_Msk                    /*!< Timer update */

+#define HRTIM_RSTR_CMP2_Pos           (2U)

+#define HRTIM_RSTR_CMP2_Msk           (0x1UL << HRTIM_RSTR_CMP2_Pos)           /*!< 0x00000004 */

+#define HRTIM_RSTR_CMP2               HRTIM_RSTR_CMP2_Msk                      /*!< Timer compare2 */

+#define HRTIM_RSTR_CMP4_Pos           (3U)

+#define HRTIM_RSTR_CMP4_Msk           (0x1UL << HRTIM_RSTR_CMP4_Pos)           /*!< 0x00000008 */

+#define HRTIM_RSTR_CMP4               HRTIM_RSTR_CMP4_Msk                      /*!< Timer compare4 */

+

+#define HRTIM_RSTR_MSTPER_Pos         (4U)

+#define HRTIM_RSTR_MSTPER_Msk         (0x1UL << HRTIM_RSTR_MSTPER_Pos)         /*!< 0x00000010 */

+#define HRTIM_RSTR_MSTPER             HRTIM_RSTR_MSTPER_Msk                    /*!< Master period */

+#define HRTIM_RSTR_MSTCMP1_Pos        (5U)

+#define HRTIM_RSTR_MSTCMP1_Msk        (0x1UL << HRTIM_RSTR_MSTCMP1_Pos)        /*!< 0x00000020 */

+#define HRTIM_RSTR_MSTCMP1            HRTIM_RSTR_MSTCMP1_Msk                   /*!< Master compare1 */

+#define HRTIM_RSTR_MSTCMP2_Pos        (6U)

+#define HRTIM_RSTR_MSTCMP2_Msk        (0x1UL << HRTIM_RSTR_MSTCMP2_Pos)        /*!< 0x00000040 */

+#define HRTIM_RSTR_MSTCMP2            HRTIM_RSTR_MSTCMP2_Msk                   /*!< Master compare2 */

+#define HRTIM_RSTR_MSTCMP3_Pos        (7U)

+#define HRTIM_RSTR_MSTCMP3_Msk        (0x1UL << HRTIM_RSTR_MSTCMP3_Pos)        /*!< 0x00000080 */

+#define HRTIM_RSTR_MSTCMP3            HRTIM_RSTR_MSTCMP3_Msk                   /*!< Master compare3 */

+#define HRTIM_RSTR_MSTCMP4_Pos        (8U)

+#define HRTIM_RSTR_MSTCMP4_Msk        (0x1UL << HRTIM_RSTR_MSTCMP4_Pos)        /*!< 0x00000100 */

+#define HRTIM_RSTR_MSTCMP4            HRTIM_RSTR_MSTCMP4_Msk                   /*!< Master compare4 */

+

+#define HRTIM_RSTR_EXTEVNT1_Pos       (9U)

+#define HRTIM_RSTR_EXTEVNT1_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos)       /*!< 0x00000200 */

+#define HRTIM_RSTR_EXTEVNT1           HRTIM_RSTR_EXTEVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_RSTR_EXTEVNT2_Pos       (10U)

+#define HRTIM_RSTR_EXTEVNT2_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos)       /*!< 0x00000400 */

+#define HRTIM_RSTR_EXTEVNT2           HRTIM_RSTR_EXTEVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_RSTR_EXTEVNT3_Pos       (11U)

+#define HRTIM_RSTR_EXTEVNT3_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos)       /*!< 0x00000800 */

+#define HRTIM_RSTR_EXTEVNT3           HRTIM_RSTR_EXTEVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_RSTR_EXTEVNT4_Pos       (12U)

+#define HRTIM_RSTR_EXTEVNT4_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos)       /*!< 0x00001000 */

+#define HRTIM_RSTR_EXTEVNT4           HRTIM_RSTR_EXTEVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_RSTR_EXTEVNT5_Pos       (13U)

+#define HRTIM_RSTR_EXTEVNT5_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos)       /*!< 0x00002000 */

+#define HRTIM_RSTR_EXTEVNT5           HRTIM_RSTR_EXTEVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_RSTR_EXTEVNT6_Pos       (14U)

+#define HRTIM_RSTR_EXTEVNT6_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos)       /*!< 0x00004000 */

+#define HRTIM_RSTR_EXTEVNT6           HRTIM_RSTR_EXTEVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_RSTR_EXTEVNT7_Pos       (15U)

+#define HRTIM_RSTR_EXTEVNT7_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos)       /*!< 0x00008000 */

+#define HRTIM_RSTR_EXTEVNT7           HRTIM_RSTR_EXTEVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_RSTR_EXTEVNT8_Pos       (16U)

+#define HRTIM_RSTR_EXTEVNT8_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos)       /*!< 0x00010000 */

+#define HRTIM_RSTR_EXTEVNT8           HRTIM_RSTR_EXTEVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_RSTR_EXTEVNT9_Pos       (17U)

+#define HRTIM_RSTR_EXTEVNT9_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos)       /*!< 0x00020000 */

+#define HRTIM_RSTR_EXTEVNT9           HRTIM_RSTR_EXTEVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_RSTR_EXTEVNT10_Pos      (18U)

+#define HRTIM_RSTR_EXTEVNT10_Msk      (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos)      /*!< 0x00040000 */

+#define HRTIM_RSTR_EXTEVNT10          HRTIM_RSTR_EXTEVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_RSTR_TIMBCMP1_Pos       (19U)

+#define HRTIM_RSTR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos)       /*!< 0x00080000 */

+#define HRTIM_RSTR_TIMBCMP1           HRTIM_RSTR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */

+#define HRTIM_RSTR_TIMBCMP2_Pos       (20U)

+#define HRTIM_RSTR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos)       /*!< 0x00100000 */

+#define HRTIM_RSTR_TIMBCMP2           HRTIM_RSTR_TIMBCMP2_Msk                  /*!< Timer B compare 2 */

+#define HRTIM_RSTR_TIMBCMP4_Pos       (21U)

+#define HRTIM_RSTR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos)       /*!< 0x00200000 */

+#define HRTIM_RSTR_TIMBCMP4           HRTIM_RSTR_TIMBCMP4_Msk                  /*!< Timer B compare 4 */

+

+#define HRTIM_RSTR_TIMCCMP1_Pos       (22U)

+#define HRTIM_RSTR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos)       /*!< 0x00400000 */

+#define HRTIM_RSTR_TIMCCMP1           HRTIM_RSTR_TIMCCMP1_Msk                  /*!< Timer C compare 1 */

+#define HRTIM_RSTR_TIMCCMP2_Pos       (23U)

+#define HRTIM_RSTR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos)       /*!< 0x00800000 */

+#define HRTIM_RSTR_TIMCCMP2           HRTIM_RSTR_TIMCCMP2_Msk                  /*!< Timer C compare 2 */

+#define HRTIM_RSTR_TIMCCMP4_Pos       (24U)

+#define HRTIM_RSTR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos)       /*!< 0x01000000 */

+#define HRTIM_RSTR_TIMCCMP4           HRTIM_RSTR_TIMCCMP4_Msk                  /*!< Timer C compare 4 */

+

+#define HRTIM_RSTR_TIMDCMP1_Pos       (25U)

+#define HRTIM_RSTR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos)       /*!< 0x02000000 */

+#define HRTIM_RSTR_TIMDCMP1           HRTIM_RSTR_TIMDCMP1_Msk                  /*!< Timer D compare 1 */

+#define HRTIM_RSTR_TIMDCMP2_Pos       (26U)

+#define HRTIM_RSTR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos)       /*!< 0x04000000 */

+#define HRTIM_RSTR_TIMDCMP2           HRTIM_RSTR_TIMDCMP2_Msk                  /*!< Timer D compare 2 */

+#define HRTIM_RSTR_TIMDCMP4_Pos       (27U)

+#define HRTIM_RSTR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos)       /*!< 0x08000000 */

+#define HRTIM_RSTR_TIMDCMP4           HRTIM_RSTR_TIMDCMP4_Msk                  /*!< Timer D compare 4 */

+

+#define HRTIM_RSTR_TIMECMP1_Pos       (28U)

+#define HRTIM_RSTR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTR_TIMECMP1_Pos)       /*!< 0x10000000 */

+#define HRTIM_RSTR_TIMECMP1           HRTIM_RSTR_TIMECMP1_Msk                  /*!< Timer E compare 1 */

+#define HRTIM_RSTR_TIMECMP2_Pos       (29U)

+#define HRTIM_RSTR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTR_TIMECMP2_Pos)       /*!< 0x20000000 */

+#define HRTIM_RSTR_TIMECMP2           HRTIM_RSTR_TIMECMP2_Msk                  /*!< Timer E compare 2 */

+#define HRTIM_RSTR_TIMECMP4_Pos       (30U)

+#define HRTIM_RSTR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTR_TIMECMP4_Pos)       /*!< 0x40000000 */

+#define HRTIM_RSTR_TIMECMP4           HRTIM_RSTR_TIMECMP4_Msk                  /*!< Timer E compare 4 */

+

+/**** Bit definition for Slave Timer Chopper register *************************/

+#define HRTIM_CHPR_CARFRQ_Pos         (0U)

+#define HRTIM_CHPR_CARFRQ_Msk         (0xFUL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x0000000F */

+#define HRTIM_CHPR_CARFRQ             HRTIM_CHPR_CARFRQ_Msk                    /*!< Timer carrier frequency value */

+#define HRTIM_CHPR_CARFRQ_0           (0x1UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000001 */

+#define HRTIM_CHPR_CARFRQ_1           (0x2UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000002 */

+#define HRTIM_CHPR_CARFRQ_2           (0x4UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000004 */

+#define HRTIM_CHPR_CARFRQ_3           (0x8UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000008 */

+

+#define HRTIM_CHPR_CARDTY_Pos         (4U)

+#define HRTIM_CHPR_CARDTY_Msk         (0x7UL << HRTIM_CHPR_CARDTY_Pos)         /*!< 0x00000070 */

+#define HRTIM_CHPR_CARDTY             HRTIM_CHPR_CARDTY_Msk                    /*!< Timer chopper duty cycle value */

+#define HRTIM_CHPR_CARDTY_0           (0x1UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000010 */

+#define HRTIM_CHPR_CARDTY_1           (0x2UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000020 */

+#define HRTIM_CHPR_CARDTY_2           (0x4UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000040 */

+

+#define HRTIM_CHPR_STRPW_Pos          (7U)

+#define HRTIM_CHPR_STRPW_Msk          (0xFUL << HRTIM_CHPR_STRPW_Pos)          /*!< 0x00000780 */

+#define HRTIM_CHPR_STRPW              HRTIM_CHPR_STRPW_Msk                     /*!< Timer start pulse width value */

+#define HRTIM_CHPR_STRPW_0            (0x1UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000080 */

+#define HRTIM_CHPR_STRPW_1            (0x2UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000100 */

+#define HRTIM_CHPR_STRPW_2            (0x4UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000200 */

+#define HRTIM_CHPR_STRPW_3            (0x8UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000400 */

+

+/**** Bit definition for Slave Timer Capture 1 control register ***************/

+#define HRTIM_CPT1CR_SWCPT_Pos        (0U)

+#define HRTIM_CPT1CR_SWCPT_Msk        (0x1UL << HRTIM_CPT1CR_SWCPT_Pos)        /*!< 0x00000001 */

+#define HRTIM_CPT1CR_SWCPT            HRTIM_CPT1CR_SWCPT_Msk                   /*!< Software capture */

+#define HRTIM_CPT1CR_UPDCPT_Pos       (1U)

+#define HRTIM_CPT1CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos)       /*!< 0x00000002 */

+#define HRTIM_CPT1CR_UPDCPT           HRTIM_CPT1CR_UPDCPT_Msk                  /*!< Update capture */

+#define HRTIM_CPT1CR_EXEV1CPT_Pos     (2U)

+#define HRTIM_CPT1CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos)     /*!< 0x00000004 */

+#define HRTIM_CPT1CR_EXEV1CPT         HRTIM_CPT1CR_EXEV1CPT_Msk                /*!< External event 1 capture */

+#define HRTIM_CPT1CR_EXEV2CPT_Pos     (3U)

+#define HRTIM_CPT1CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos)     /*!< 0x00000008 */

+#define HRTIM_CPT1CR_EXEV2CPT         HRTIM_CPT1CR_EXEV2CPT_Msk                /*!< External event 2 capture */

+#define HRTIM_CPT1CR_EXEV3CPT_Pos     (4U)

+#define HRTIM_CPT1CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos)     /*!< 0x00000010 */

+#define HRTIM_CPT1CR_EXEV3CPT         HRTIM_CPT1CR_EXEV3CPT_Msk                /*!< External event 3 capture */

+#define HRTIM_CPT1CR_EXEV4CPT_Pos     (5U)

+#define HRTIM_CPT1CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos)     /*!< 0x00000020 */

+#define HRTIM_CPT1CR_EXEV4CPT         HRTIM_CPT1CR_EXEV4CPT_Msk                /*!< External event 4 capture */

+#define HRTIM_CPT1CR_EXEV5CPT_Pos     (6U)

+#define HRTIM_CPT1CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos)     /*!< 0x00000040 */

+#define HRTIM_CPT1CR_EXEV5CPT         HRTIM_CPT1CR_EXEV5CPT_Msk                /*!< External event 5 capture */

+#define HRTIM_CPT1CR_EXEV6CPT_Pos     (7U)

+#define HRTIM_CPT1CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos)     /*!< 0x00000080 */

+#define HRTIM_CPT1CR_EXEV6CPT         HRTIM_CPT1CR_EXEV6CPT_Msk                /*!< External event 6 capture */

+#define HRTIM_CPT1CR_EXEV7CPT_Pos     (8U)

+#define HRTIM_CPT1CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos)     /*!< 0x00000100 */

+#define HRTIM_CPT1CR_EXEV7CPT         HRTIM_CPT1CR_EXEV7CPT_Msk                /*!< External event 7 capture */

+#define HRTIM_CPT1CR_EXEV8CPT_Pos     (9U)

+#define HRTIM_CPT1CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos)     /*!< 0x00000200 */

+#define HRTIM_CPT1CR_EXEV8CPT         HRTIM_CPT1CR_EXEV8CPT_Msk                /*!< External event 8 capture */

+#define HRTIM_CPT1CR_EXEV9CPT_Pos     (10U)

+#define HRTIM_CPT1CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos)     /*!< 0x00000400 */

+#define HRTIM_CPT1CR_EXEV9CPT         HRTIM_CPT1CR_EXEV9CPT_Msk                /*!< External event 9 capture */

+#define HRTIM_CPT1CR_EXEV10CPT_Pos    (11U)

+#define HRTIM_CPT1CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos)    /*!< 0x00000800 */

+#define HRTIM_CPT1CR_EXEV10CPT        HRTIM_CPT1CR_EXEV10CPT_Msk               /*!< External event 10 capture */

+

+#define HRTIM_CPT1CR_TA1SET_Pos       (12U)

+#define HRTIM_CPT1CR_TA1SET_Msk       (0x1UL << HRTIM_CPT1CR_TA1SET_Pos)       /*!< 0x00001000 */

+#define HRTIM_CPT1CR_TA1SET           HRTIM_CPT1CR_TA1SET_Msk                  /*!< Timer A output 1 set */

+#define HRTIM_CPT1CR_TA1RST_Pos       (13U)

+#define HRTIM_CPT1CR_TA1RST_Msk       (0x1UL << HRTIM_CPT1CR_TA1RST_Pos)       /*!< 0x00002000 */

+#define HRTIM_CPT1CR_TA1RST           HRTIM_CPT1CR_TA1RST_Msk                  /*!< Timer A output 1 reset */

+#define HRTIM_CPT1CR_TIMACMP1_Pos     (14U)

+#define HRTIM_CPT1CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos)     /*!< 0x00004000 */

+#define HRTIM_CPT1CR_TIMACMP1         HRTIM_CPT1CR_TIMACMP1_Msk                /*!< Timer A compare 1 */

+#define HRTIM_CPT1CR_TIMACMP2_Pos     (15U)

+#define HRTIM_CPT1CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos)     /*!< 0x00008000 */

+#define HRTIM_CPT1CR_TIMACMP2         HRTIM_CPT1CR_TIMACMP2_Msk                /*!< Timer A compare 2 */

+

+#define HRTIM_CPT1CR_TB1SET_Pos       (16U)

+#define HRTIM_CPT1CR_TB1SET_Msk       (0x1UL << HRTIM_CPT1CR_TB1SET_Pos)       /*!< 0x00010000 */

+#define HRTIM_CPT1CR_TB1SET           HRTIM_CPT1CR_TB1SET_Msk                  /*!< Timer B output 1 set */

+#define HRTIM_CPT1CR_TB1RST_Pos       (17U)

+#define HRTIM_CPT1CR_TB1RST_Msk       (0x1UL << HRTIM_CPT1CR_TB1RST_Pos)       /*!< 0x00020000 */

+#define HRTIM_CPT1CR_TB1RST           HRTIM_CPT1CR_TB1RST_Msk                  /*!< Timer B output 1 reset */

+#define HRTIM_CPT1CR_TIMBCMP1_Pos     (18U)

+#define HRTIM_CPT1CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos)     /*!< 0x00040000 */

+#define HRTIM_CPT1CR_TIMBCMP1         HRTIM_CPT1CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */

+#define HRTIM_CPT1CR_TIMBCMP2_Pos     (19U)

+#define HRTIM_CPT1CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos)     /*!< 0x00080000 */

+#define HRTIM_CPT1CR_TIMBCMP2         HRTIM_CPT1CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */

+

+#define HRTIM_CPT1CR_TC1SET_Pos       (20U)

+#define HRTIM_CPT1CR_TC1SET_Msk       (0x1UL << HRTIM_CPT1CR_TC1SET_Pos)       /*!< 0x00100000 */

+#define HRTIM_CPT1CR_TC1SET           HRTIM_CPT1CR_TC1SET_Msk                  /*!< Timer C output 1 set */

+#define HRTIM_CPT1CR_TC1RST_Pos       (21U)

+#define HRTIM_CPT1CR_TC1RST_Msk       (0x1UL << HRTIM_CPT1CR_TC1RST_Pos)       /*!< 0x00200000 */

+#define HRTIM_CPT1CR_TC1RST           HRTIM_CPT1CR_TC1RST_Msk                  /*!< Timer C output 1 reset */

+#define HRTIM_CPT1CR_TIMCCMP1_Pos     (22U)

+#define HRTIM_CPT1CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos)     /*!< 0x00400000 */

+#define HRTIM_CPT1CR_TIMCCMP1         HRTIM_CPT1CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */

+#define HRTIM_CPT1CR_TIMCCMP2_Pos     (23U)

+#define HRTIM_CPT1CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos)     /*!< 0x00800000 */

+#define HRTIM_CPT1CR_TIMCCMP2         HRTIM_CPT1CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */

+

+#define HRTIM_CPT1CR_TD1SET_Pos       (24U)

+#define HRTIM_CPT1CR_TD1SET_Msk       (0x1UL << HRTIM_CPT1CR_TD1SET_Pos)       /*!< 0x01000000 */

+#define HRTIM_CPT1CR_TD1SET           HRTIM_CPT1CR_TD1SET_Msk                  /*!< Timer D output 1 set */

+#define HRTIM_CPT1CR_TD1RST_Pos       (25U)

+#define HRTIM_CPT1CR_TD1RST_Msk       (0x1UL << HRTIM_CPT1CR_TD1RST_Pos)       /*!< 0x02000000 */

+#define HRTIM_CPT1CR_TD1RST           HRTIM_CPT1CR_TD1RST_Msk                  /*!< Timer D output 1 reset */

+#define HRTIM_CPT1CR_TIMDCMP1_Pos     (26U)

+#define HRTIM_CPT1CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos)     /*!< 0x04000000 */

+#define HRTIM_CPT1CR_TIMDCMP1         HRTIM_CPT1CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */

+#define HRTIM_CPT1CR_TIMDCMP2_Pos     (27U)

+#define HRTIM_CPT1CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos)     /*!< 0x08000000 */

+#define HRTIM_CPT1CR_TIMDCMP2         HRTIM_CPT1CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */

+

+#define HRTIM_CPT1CR_TE1SET_Pos       (28U)

+#define HRTIM_CPT1CR_TE1SET_Msk       (0x1UL << HRTIM_CPT1CR_TE1SET_Pos)       /*!< 0x10000000 */

+#define HRTIM_CPT1CR_TE1SET           HRTIM_CPT1CR_TE1SET_Msk                  /*!< Timer E output 1 set */

+#define HRTIM_CPT1CR_TE1RST_Pos       (29U)

+#define HRTIM_CPT1CR_TE1RST_Msk       (0x1UL << HRTIM_CPT1CR_TE1RST_Pos)       /*!< 0x20000000 */

+#define HRTIM_CPT1CR_TE1RST           HRTIM_CPT1CR_TE1RST_Msk                  /*!< Timer E output 1 reset */

+#define HRTIM_CPT1CR_TIMECMP1_Pos     (30U)

+#define HRTIM_CPT1CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos)     /*!< 0x40000000 */

+#define HRTIM_CPT1CR_TIMECMP1         HRTIM_CPT1CR_TIMECMP1_Msk                /*!< Timer E compare 1 */

+#define HRTIM_CPT1CR_TIMECMP2_Pos     (31U)

+#define HRTIM_CPT1CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos)     /*!< 0x80000000 */

+#define HRTIM_CPT1CR_TIMECMP2         HRTIM_CPT1CR_TIMECMP2_Msk                /*!< Timer E compare 2 */

+

+/**** Bit definition for Slave Timer Capture 2 control register ***************/

+#define HRTIM_CPT2CR_SWCPT_Pos        (0U)

+#define HRTIM_CPT2CR_SWCPT_Msk        (0x1UL << HRTIM_CPT2CR_SWCPT_Pos)        /*!< 0x00000001 */

+#define HRTIM_CPT2CR_SWCPT            HRTIM_CPT2CR_SWCPT_Msk                   /*!< Software capture */

+#define HRTIM_CPT2CR_UPDCPT_Pos       (1U)

+#define HRTIM_CPT2CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos)       /*!< 0x00000002 */

+#define HRTIM_CPT2CR_UPDCPT           HRTIM_CPT2CR_UPDCPT_Msk                  /*!< Update capture */

+#define HRTIM_CPT2CR_EXEV1CPT_Pos     (2U)

+#define HRTIM_CPT2CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos)     /*!< 0x00000004 */

+#define HRTIM_CPT2CR_EXEV1CPT         HRTIM_CPT2CR_EXEV1CPT_Msk                /*!< External event 1 capture */

+#define HRTIM_CPT2CR_EXEV2CPT_Pos     (3U)

+#define HRTIM_CPT2CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos)     /*!< 0x00000008 */

+#define HRTIM_CPT2CR_EXEV2CPT         HRTIM_CPT2CR_EXEV2CPT_Msk                /*!< External event 2 capture */

+#define HRTIM_CPT2CR_EXEV3CPT_Pos     (4U)

+#define HRTIM_CPT2CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos)     /*!< 0x00000010 */

+#define HRTIM_CPT2CR_EXEV3CPT         HRTIM_CPT2CR_EXEV3CPT_Msk                /*!< External event 3 capture */

+#define HRTIM_CPT2CR_EXEV4CPT_Pos     (5U)

+#define HRTIM_CPT2CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos)     /*!< 0x00000020 */

+#define HRTIM_CPT2CR_EXEV4CPT         HRTIM_CPT2CR_EXEV4CPT_Msk                /*!< External event 4 capture */

+#define HRTIM_CPT2CR_EXEV5CPT_Pos     (6U)

+#define HRTIM_CPT2CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos)     /*!< 0x00000040 */

+#define HRTIM_CPT2CR_EXEV5CPT         HRTIM_CPT2CR_EXEV5CPT_Msk                /*!< External event 5 capture */

+#define HRTIM_CPT2CR_EXEV6CPT_Pos     (7U)

+#define HRTIM_CPT2CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos)     /*!< 0x00000080 */

+#define HRTIM_CPT2CR_EXEV6CPT         HRTIM_CPT2CR_EXEV6CPT_Msk                /*!< External event 6 capture */

+#define HRTIM_CPT2CR_EXEV7CPT_Pos     (8U)

+#define HRTIM_CPT2CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos)     /*!< 0x00000100 */

+#define HRTIM_CPT2CR_EXEV7CPT         HRTIM_CPT2CR_EXEV7CPT_Msk                /*!< External event 7 capture */

+#define HRTIM_CPT2CR_EXEV8CPT_Pos     (9U)

+#define HRTIM_CPT2CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos)     /*!< 0x00000200 */

+#define HRTIM_CPT2CR_EXEV8CPT         HRTIM_CPT2CR_EXEV8CPT_Msk                /*!< External event 8 capture */

+#define HRTIM_CPT2CR_EXEV9CPT_Pos     (10U)

+#define HRTIM_CPT2CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos)     /*!< 0x00000400 */

+#define HRTIM_CPT2CR_EXEV9CPT         HRTIM_CPT2CR_EXEV9CPT_Msk                /*!< External event 9 capture */

+#define HRTIM_CPT2CR_EXEV10CPT_Pos    (11U)

+#define HRTIM_CPT2CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos)    /*!< 0x00000800 */

+#define HRTIM_CPT2CR_EXEV10CPT        HRTIM_CPT2CR_EXEV10CPT_Msk               /*!< External event 10 capture */

+

+#define HRTIM_CPT2CR_TA1SET_Pos       (12U)

+#define HRTIM_CPT2CR_TA1SET_Msk       (0x1UL << HRTIM_CPT2CR_TA1SET_Pos)       /*!< 0x00001000 */

+#define HRTIM_CPT2CR_TA1SET           HRTIM_CPT2CR_TA1SET_Msk                  /*!< Timer A output 1 set */

+#define HRTIM_CPT2CR_TA1RST_Pos       (13U)

+#define HRTIM_CPT2CR_TA1RST_Msk       (0x1UL << HRTIM_CPT2CR_TA1RST_Pos)       /*!< 0x00002000 */

+#define HRTIM_CPT2CR_TA1RST           HRTIM_CPT2CR_TA1RST_Msk                  /*!< Timer A output 1 reset */

+#define HRTIM_CPT2CR_TIMACMP1_Pos     (14U)

+#define HRTIM_CPT2CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos)     /*!< 0x00004000 */

+#define HRTIM_CPT2CR_TIMACMP1         HRTIM_CPT2CR_TIMACMP1_Msk                /*!< Timer A compare 1 */

+#define HRTIM_CPT2CR_TIMACMP2_Pos     (15U)

+#define HRTIM_CPT2CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos)     /*!< 0x00008000 */

+#define HRTIM_CPT2CR_TIMACMP2         HRTIM_CPT2CR_TIMACMP2_Msk                /*!< Timer A compare 2 */

+

+#define HRTIM_CPT2CR_TB1SET_Pos       (16U)

+#define HRTIM_CPT2CR_TB1SET_Msk       (0x1UL << HRTIM_CPT2CR_TB1SET_Pos)       /*!< 0x00010000 */

+#define HRTIM_CPT2CR_TB1SET           HRTIM_CPT2CR_TB1SET_Msk                  /*!< Timer B output 1 set */

+#define HRTIM_CPT2CR_TB1RST_Pos       (17U)

+#define HRTIM_CPT2CR_TB1RST_Msk       (0x1UL << HRTIM_CPT2CR_TB1RST_Pos)       /*!< 0x00020000 */

+#define HRTIM_CPT2CR_TB1RST           HRTIM_CPT2CR_TB1RST_Msk                  /*!< Timer B output 1 reset */

+#define HRTIM_CPT2CR_TIMBCMP1_Pos     (18U)

+#define HRTIM_CPT2CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos)     /*!< 0x00040000 */

+#define HRTIM_CPT2CR_TIMBCMP1         HRTIM_CPT2CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */

+#define HRTIM_CPT2CR_TIMBCMP2_Pos     (19U)

+#define HRTIM_CPT2CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos)     /*!< 0x00080000 */

+#define HRTIM_CPT2CR_TIMBCMP2         HRTIM_CPT2CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */

+

+#define HRTIM_CPT2CR_TC1SET_Pos       (20U)

+#define HRTIM_CPT2CR_TC1SET_Msk       (0x1UL << HRTIM_CPT2CR_TC1SET_Pos)       /*!< 0x00100000 */

+#define HRTIM_CPT2CR_TC1SET           HRTIM_CPT2CR_TC1SET_Msk                  /*!< Timer C output 1 set */

+#define HRTIM_CPT2CR_TC1RST_Pos       (21U)

+#define HRTIM_CPT2CR_TC1RST_Msk       (0x1UL << HRTIM_CPT2CR_TC1RST_Pos)       /*!< 0x00200000 */

+#define HRTIM_CPT2CR_TC1RST           HRTIM_CPT2CR_TC1RST_Msk                  /*!< Timer C output 1 reset */

+#define HRTIM_CPT2CR_TIMCCMP1_Pos     (22U)

+#define HRTIM_CPT2CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos)     /*!< 0x00400000 */

+#define HRTIM_CPT2CR_TIMCCMP1         HRTIM_CPT2CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */

+#define HRTIM_CPT2CR_TIMCCMP2_Pos     (23U)

+#define HRTIM_CPT2CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos)     /*!< 0x00800000 */

+#define HRTIM_CPT2CR_TIMCCMP2         HRTIM_CPT2CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */

+

+#define HRTIM_CPT2CR_TD1SET_Pos       (24U)

+#define HRTIM_CPT2CR_TD1SET_Msk       (0x1UL << HRTIM_CPT2CR_TD1SET_Pos)       /*!< 0x01000000 */

+#define HRTIM_CPT2CR_TD1SET           HRTIM_CPT2CR_TD1SET_Msk                  /*!< Timer D output 1 set */

+#define HRTIM_CPT2CR_TD1RST_Pos       (25U)

+#define HRTIM_CPT2CR_TD1RST_Msk       (0x1UL << HRTIM_CPT2CR_TD1RST_Pos)       /*!< 0x02000000 */

+#define HRTIM_CPT2CR_TD1RST           HRTIM_CPT2CR_TD1RST_Msk                  /*!< Timer D output 1 reset */

+#define HRTIM_CPT2CR_TIMDCMP1_Pos     (26U)

+#define HRTIM_CPT2CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos)     /*!< 0x04000000 */

+#define HRTIM_CPT2CR_TIMDCMP1         HRTIM_CPT2CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */

+#define HRTIM_CPT2CR_TIMDCMP2_Pos     (27U)

+#define HRTIM_CPT2CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos)     /*!< 0x08000000 */

+#define HRTIM_CPT2CR_TIMDCMP2         HRTIM_CPT2CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */

+

+#define HRTIM_CPT2CR_TE1SET_Pos       (28U)

+#define HRTIM_CPT2CR_TE1SET_Msk       (0x1UL << HRTIM_CPT2CR_TE1SET_Pos)       /*!< 0x10000000 */

+#define HRTIM_CPT2CR_TE1SET           HRTIM_CPT2CR_TE1SET_Msk                  /*!< Timer E output 1 set */

+#define HRTIM_CPT2CR_TE1RST_Pos       (29U)

+#define HRTIM_CPT2CR_TE1RST_Msk       (0x1UL << HRTIM_CPT2CR_TE1RST_Pos)       /*!< 0x20000000 */

+#define HRTIM_CPT2CR_TE1RST           HRTIM_CPT2CR_TE1RST_Msk                  /*!< Timer E output 1 reset */

+#define HRTIM_CPT2CR_TIMECMP1_Pos     (30U)

+#define HRTIM_CPT2CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos)     /*!< 0x40000000 */

+#define HRTIM_CPT2CR_TIMECMP1         HRTIM_CPT2CR_TIMECMP1_Msk                /*!< Timer E compare 1 */

+#define HRTIM_CPT2CR_TIMECMP2_Pos     (31U)

+#define HRTIM_CPT2CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos)     /*!< 0x80000000 */

+#define HRTIM_CPT2CR_TIMECMP2         HRTIM_CPT2CR_TIMECMP2_Msk                /*!< Timer E compare 2 */

+

+/**** Bit definition for Slave Timer Output register **************************/

+#define HRTIM_OUTR_POL1_Pos           (1U)

+#define HRTIM_OUTR_POL1_Msk           (0x1UL << HRTIM_OUTR_POL1_Pos)           /*!< 0x00000002 */

+#define HRTIM_OUTR_POL1               HRTIM_OUTR_POL1_Msk                      /*!< Slave output 1 polarity */

+#define HRTIM_OUTR_IDLM1_Pos          (2U)

+#define HRTIM_OUTR_IDLM1_Msk          (0x1UL << HRTIM_OUTR_IDLM1_Pos)          /*!< 0x00000004 */

+#define HRTIM_OUTR_IDLM1              HRTIM_OUTR_IDLM1_Msk                     /*!< Slave output 1 idle mode */

+#define HRTIM_OUTR_IDLES1_Pos         (3U)

+#define HRTIM_OUTR_IDLES1_Msk         (0x1UL << HRTIM_OUTR_IDLES1_Pos)         /*!< 0x00000008 */

+#define HRTIM_OUTR_IDLES1             HRTIM_OUTR_IDLES1_Msk                    /*!< Slave output 1 idle state */

+#define HRTIM_OUTR_FAULT1_Pos         (4U)

+#define HRTIM_OUTR_FAULT1_Msk         (0x3UL << HRTIM_OUTR_FAULT1_Pos)         /*!< 0x00000030 */

+#define HRTIM_OUTR_FAULT1             HRTIM_OUTR_FAULT1_Msk                    /*!< Slave output 1 fault state */

+#define HRTIM_OUTR_FAULT1_0           (0x1UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000010 */

+#define HRTIM_OUTR_FAULT1_1           (0x2UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000020 */

+#define HRTIM_OUTR_CHP1_Pos           (6U)

+#define HRTIM_OUTR_CHP1_Msk           (0x1UL << HRTIM_OUTR_CHP1_Pos)           /*!< 0x00000040 */

+#define HRTIM_OUTR_CHP1               HRTIM_OUTR_CHP1_Msk                      /*!< Slave output 1 chopper enable */

+#define HRTIM_OUTR_DIDL1_Pos          (7U)

+#define HRTIM_OUTR_DIDL1_Msk          (0x1UL << HRTIM_OUTR_DIDL1_Pos)          /*!< 0x00000080 */

+#define HRTIM_OUTR_DIDL1              HRTIM_OUTR_DIDL1_Msk                     /*!< Slave output 1 dead time idle */

+

+#define HRTIM_OUTR_DTEN_Pos           (8U)

+#define HRTIM_OUTR_DTEN_Msk           (0x1UL << HRTIM_OUTR_DTEN_Pos)           /*!< 0x00000100 */

+#define HRTIM_OUTR_DTEN               HRTIM_OUTR_DTEN_Msk                      /*!< Slave output deadtime enable */

+#define HRTIM_OUTR_DLYPRTEN_Pos       (9U)

+#define HRTIM_OUTR_DLYPRTEN_Msk       (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos)       /*!< 0x00000200 */

+#define HRTIM_OUTR_DLYPRTEN           HRTIM_OUTR_DLYPRTEN_Msk                  /*!< Slave output delay protection enable */

+#define HRTIM_OUTR_DLYPRT_Pos         (10U)

+#define HRTIM_OUTR_DLYPRT_Msk         (0x7UL << HRTIM_OUTR_DLYPRT_Pos)         /*!< 0x00001C00 */

+#define HRTIM_OUTR_DLYPRT             HRTIM_OUTR_DLYPRT_Msk                    /*!< Slave output delay protection */

+#define HRTIM_OUTR_DLYPRT_0           (0x1UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000400 */

+#define HRTIM_OUTR_DLYPRT_1           (0x2UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000800 */

+#define HRTIM_OUTR_DLYPRT_2           (0x4UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00001000 */

+

+#define HRTIM_OUTR_POL2_Pos           (17U)

+#define HRTIM_OUTR_POL2_Msk           (0x1UL << HRTIM_OUTR_POL2_Pos)           /*!< 0x00020000 */

+#define HRTIM_OUTR_POL2               HRTIM_OUTR_POL2_Msk                      /*!< Slave output 2 polarity */

+#define HRTIM_OUTR_IDLM2_Pos          (18U)

+#define HRTIM_OUTR_IDLM2_Msk          (0x1UL << HRTIM_OUTR_IDLM2_Pos)          /*!< 0x00040000 */

+#define HRTIM_OUTR_IDLM2              HRTIM_OUTR_IDLM2_Msk                     /*!< Slave output 2 idle mode */

+#define HRTIM_OUTR_IDLES2_Pos         (19U)

+#define HRTIM_OUTR_IDLES2_Msk         (0x1UL << HRTIM_OUTR_IDLES2_Pos)         /*!< 0x00080000 */

+#define HRTIM_OUTR_IDLES2             HRTIM_OUTR_IDLES2_Msk                    /*!< Slave output 2 idle state */

+#define HRTIM_OUTR_FAULT2_Pos         (20U)

+#define HRTIM_OUTR_FAULT2_Msk         (0x3UL << HRTIM_OUTR_FAULT2_Pos)         /*!< 0x00300000 */

+#define HRTIM_OUTR_FAULT2             HRTIM_OUTR_FAULT2_Msk                    /*!< Slave output 2 fault state */

+#define HRTIM_OUTR_FAULT2_0           (0x1UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00100000 */

+#define HRTIM_OUTR_FAULT2_1           (0x2UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00200000 */

+#define HRTIM_OUTR_CHP2_Pos           (22U)

+#define HRTIM_OUTR_CHP2_Msk           (0x1UL << HRTIM_OUTR_CHP2_Pos)           /*!< 0x00400000 */

+#define HRTIM_OUTR_CHP2               HRTIM_OUTR_CHP2_Msk                      /*!< Slave output 2 chopper enable */

+#define HRTIM_OUTR_DIDL2_Pos          (23U)

+#define HRTIM_OUTR_DIDL2_Msk          (0x1UL << HRTIM_OUTR_DIDL2_Pos)          /*!< 0x00800000 */

+#define HRTIM_OUTR_DIDL2              HRTIM_OUTR_DIDL2_Msk                     /*!< Slave output 2 dead time idle */

+

+/**** Bit definition for Slave Timer Fault register ***************************/

+#define HRTIM_FLTR_FLT1EN_Pos         (0U)

+#define HRTIM_FLTR_FLT1EN_Msk         (0x1UL << HRTIM_FLTR_FLT1EN_Pos)         /*!< 0x00000001 */

+#define HRTIM_FLTR_FLT1EN             HRTIM_FLTR_FLT1EN_Msk                    /*!< Fault 1 enable */

+#define HRTIM_FLTR_FLT2EN_Pos         (1U)

+#define HRTIM_FLTR_FLT2EN_Msk         (0x1UL << HRTIM_FLTR_FLT2EN_Pos)         /*!< 0x00000002 */

+#define HRTIM_FLTR_FLT2EN             HRTIM_FLTR_FLT2EN_Msk                    /*!< Fault 2 enable */

+#define HRTIM_FLTR_FLT3EN_Pos         (2U)

+#define HRTIM_FLTR_FLT3EN_Msk         (0x1UL << HRTIM_FLTR_FLT3EN_Pos)         /*!< 0x00000004 */

+#define HRTIM_FLTR_FLT3EN             HRTIM_FLTR_FLT3EN_Msk                    /*!< Fault 3 enable */

+#define HRTIM_FLTR_FLT4EN_Pos         (3U)

+#define HRTIM_FLTR_FLT4EN_Msk         (0x1UL << HRTIM_FLTR_FLT4EN_Pos)         /*!< 0x00000008 */

+#define HRTIM_FLTR_FLT4EN             HRTIM_FLTR_FLT4EN_Msk                    /*!< Fault 4 enable */

+#define HRTIM_FLTR_FLT5EN_Pos         (4U)

+#define HRTIM_FLTR_FLT5EN_Msk         (0x1UL << HRTIM_FLTR_FLT5EN_Pos)         /*!< 0x00000010 */

+#define HRTIM_FLTR_FLT5EN             HRTIM_FLTR_FLT5EN_Msk                    /*!< Fault 5 enable */

+#define HRTIM_FLTR_FLTLCK_Pos         (31U)

+#define HRTIM_FLTR_FLTLCK_Msk         (0x1UL << HRTIM_FLTR_FLTLCK_Pos)         /*!< 0x80000000 */

+#define HRTIM_FLTR_FLTLCK             HRTIM_FLTR_FLTLCK_Msk                    /*!< Fault sources lock */

+

+/**** Bit definition for Common HRTIM Timer control register 1 ****************/

+#define HRTIM_CR1_MUDIS_Pos           (0U)

+#define HRTIM_CR1_MUDIS_Msk           (0x1UL << HRTIM_CR1_MUDIS_Pos)           /*!< 0x00000001 */

+#define HRTIM_CR1_MUDIS               HRTIM_CR1_MUDIS_Msk                      /*!< Master update disable*/

+#define HRTIM_CR1_TAUDIS_Pos          (1U)

+#define HRTIM_CR1_TAUDIS_Msk          (0x1UL << HRTIM_CR1_TAUDIS_Pos)          /*!< 0x00000002 */

+#define HRTIM_CR1_TAUDIS              HRTIM_CR1_TAUDIS_Msk                     /*!< Timer A update disable*/

+#define HRTIM_CR1_TBUDIS_Pos          (2U)

+#define HRTIM_CR1_TBUDIS_Msk          (0x1UL << HRTIM_CR1_TBUDIS_Pos)          /*!< 0x00000004 */

+#define HRTIM_CR1_TBUDIS              HRTIM_CR1_TBUDIS_Msk                     /*!< Timer B update disable*/

+#define HRTIM_CR1_TCUDIS_Pos          (3U)

+#define HRTIM_CR1_TCUDIS_Msk          (0x1UL << HRTIM_CR1_TCUDIS_Pos)          /*!< 0x00000008 */

+#define HRTIM_CR1_TCUDIS              HRTIM_CR1_TCUDIS_Msk                     /*!< Timer C update disable*/

+#define HRTIM_CR1_TDUDIS_Pos          (4U)

+#define HRTIM_CR1_TDUDIS_Msk          (0x1UL << HRTIM_CR1_TDUDIS_Pos)          /*!< 0x00000010 */

+#define HRTIM_CR1_TDUDIS              HRTIM_CR1_TDUDIS_Msk                     /*!< Timer D update disable*/

+#define HRTIM_CR1_TEUDIS_Pos          (5U)

+#define HRTIM_CR1_TEUDIS_Msk          (0x1UL << HRTIM_CR1_TEUDIS_Pos)          /*!< 0x00000020 */

+#define HRTIM_CR1_TEUDIS              HRTIM_CR1_TEUDIS_Msk                     /*!< Timer E update disable*/

+#define HRTIM_CR1_ADC1USRC_Pos        (16U)

+#define HRTIM_CR1_ADC1USRC_Msk        (0x7UL << HRTIM_CR1_ADC1USRC_Pos)        /*!< 0x00070000 */

+#define HRTIM_CR1_ADC1USRC            HRTIM_CR1_ADC1USRC_Msk                   /*!< ADC Trigger 1 update source */

+#define HRTIM_CR1_ADC1USRC_0          (0x1UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00010000 */

+#define HRTIM_CR1_ADC1USRC_1          (0x2UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00020000 */

+#define HRTIM_CR1_ADC1USRC_2          (0x4UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00040000 */

+#define HRTIM_CR1_ADC2USRC_Pos        (19U)

+#define HRTIM_CR1_ADC2USRC_Msk        (0x7UL << HRTIM_CR1_ADC2USRC_Pos)        /*!< 0x00380000 */

+#define HRTIM_CR1_ADC2USRC            HRTIM_CR1_ADC2USRC_Msk                   /*!< ADC Trigger 2 update source */

+#define HRTIM_CR1_ADC2USRC_0          (0x1UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00080000 */

+#define HRTIM_CR1_ADC2USRC_1          (0x2UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00100000 */

+#define HRTIM_CR1_ADC2USRC_2          (0x4UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00200000 */

+#define HRTIM_CR1_ADC3USRC_Pos        (22U)

+#define HRTIM_CR1_ADC3USRC_Msk        (0x7UL << HRTIM_CR1_ADC3USRC_Pos)        /*!< 0x01C00000 */

+#define HRTIM_CR1_ADC3USRC            HRTIM_CR1_ADC3USRC_Msk                   /*!< ADC Trigger 3 update source */

+#define HRTIM_CR1_ADC3USRC_0          (0x1UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00400000 */

+#define HRTIM_CR1_ADC3USRC_1          (0x2UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00800000 */

+#define HRTIM_CR1_ADC3USRC_2          (0x4UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x01000000 */

+#define HRTIM_CR1_ADC4USRC_Pos        (25U)

+#define HRTIM_CR1_ADC4USRC_Msk        (0x7UL << HRTIM_CR1_ADC4USRC_Pos)        /*!< 0x0E000000 */

+#define HRTIM_CR1_ADC4USRC            HRTIM_CR1_ADC4USRC_Msk                   /*!< ADC Trigger 4 update source */

+#define HRTIM_CR1_ADC4USRC_0          (0x1UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x02000000 */

+#define HRTIM_CR1_ADC4USRC_1          (0x2UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x04000000 */

+#define HRTIM_CR1_ADC4USRC_2          (0x0UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x0800000 */

+

+/**** Bit definition for Common HRTIM Timer control register 2 ****************/

+#define HRTIM_CR2_MSWU_Pos            (0U)

+#define HRTIM_CR2_MSWU_Msk            (0x1UL << HRTIM_CR2_MSWU_Pos)            /*!< 0x00000001 */

+#define HRTIM_CR2_MSWU                HRTIM_CR2_MSWU_Msk                       /*!< Master software update */

+#define HRTIM_CR2_TASWU_Pos           (1U)

+#define HRTIM_CR2_TASWU_Msk           (0x1UL << HRTIM_CR2_TASWU_Pos)           /*!< 0x00000002 */

+#define HRTIM_CR2_TASWU               HRTIM_CR2_TASWU_Msk                      /*!< Timer A software update */

+#define HRTIM_CR2_TBSWU_Pos           (2U)

+#define HRTIM_CR2_TBSWU_Msk           (0x1UL << HRTIM_CR2_TBSWU_Pos)           /*!< 0x00000004 */

+#define HRTIM_CR2_TBSWU               HRTIM_CR2_TBSWU_Msk                      /*!< Timer B software update */

+#define HRTIM_CR2_TCSWU_Pos           (3U)

+#define HRTIM_CR2_TCSWU_Msk           (0x1UL << HRTIM_CR2_TCSWU_Pos)           /*!< 0x00000008 */

+#define HRTIM_CR2_TCSWU               HRTIM_CR2_TCSWU_Msk                      /*!< Timer C software update */

+#define HRTIM_CR2_TDSWU_Pos           (4U)

+#define HRTIM_CR2_TDSWU_Msk           (0x1UL << HRTIM_CR2_TDSWU_Pos)           /*!< 0x00000010 */

+#define HRTIM_CR2_TDSWU               HRTIM_CR2_TDSWU_Msk                      /*!< Timer D software update */

+#define HRTIM_CR2_TESWU_Pos           (5U)

+#define HRTIM_CR2_TESWU_Msk           (0x1UL << HRTIM_CR2_TESWU_Pos)           /*!< 0x00000020 */

+#define HRTIM_CR2_TESWU               HRTIM_CR2_TESWU_Msk                      /*!< Timer E software update */

+#define HRTIM_CR2_MRST_Pos            (8U)

+#define HRTIM_CR2_MRST_Msk            (0x1UL << HRTIM_CR2_MRST_Pos)            /*!< 0x00000100 */

+#define HRTIM_CR2_MRST                HRTIM_CR2_MRST_Msk                       /*!< Master count software reset */

+#define HRTIM_CR2_TARST_Pos           (9U)

+#define HRTIM_CR2_TARST_Msk           (0x1UL << HRTIM_CR2_TARST_Pos)           /*!< 0x00000200 */

+#define HRTIM_CR2_TARST               HRTIM_CR2_TARST_Msk                      /*!< Timer A count software reset */

+#define HRTIM_CR2_TBRST_Pos           (10U)

+#define HRTIM_CR2_TBRST_Msk           (0x1UL << HRTIM_CR2_TBRST_Pos)           /*!< 0x00000400 */

+#define HRTIM_CR2_TBRST               HRTIM_CR2_TBRST_Msk                      /*!< Timer B count software reset */

+#define HRTIM_CR2_TCRST_Pos           (11U)

+#define HRTIM_CR2_TCRST_Msk           (0x1UL << HRTIM_CR2_TCRST_Pos)           /*!< 0x00000800 */

+#define HRTIM_CR2_TCRST               HRTIM_CR2_TCRST_Msk                      /*!< Timer C count software reset */

+#define HRTIM_CR2_TDRST_Pos           (12U)

+#define HRTIM_CR2_TDRST_Msk           (0x1UL << HRTIM_CR2_TDRST_Pos)           /*!< 0x00001000 */

+#define HRTIM_CR2_TDRST               HRTIM_CR2_TDRST_Msk                      /*!< Timer D count software reset */

+#define HRTIM_CR2_TERST_Pos           (13U)

+#define HRTIM_CR2_TERST_Msk           (0x1UL << HRTIM_CR2_TERST_Pos)           /*!< 0x00002000 */

+#define HRTIM_CR2_TERST               HRTIM_CR2_TERST_Msk                      /*!< Timer E count software reset */

+

+/**** Bit definition for Common HRTIM Timer interrupt status register *********/

+#define HRTIM_ISR_FLT1_Pos            (0U)

+#define HRTIM_ISR_FLT1_Msk            (0x1UL << HRTIM_ISR_FLT1_Pos)            /*!< 0x00000001 */

+#define HRTIM_ISR_FLT1                HRTIM_ISR_FLT1_Msk                       /*!< Fault 1 interrupt flag */

+#define HRTIM_ISR_FLT2_Pos            (1U)

+#define HRTIM_ISR_FLT2_Msk            (0x1UL << HRTIM_ISR_FLT2_Pos)            /*!< 0x00000002 */

+#define HRTIM_ISR_FLT2                HRTIM_ISR_FLT2_Msk                       /*!< Fault 2 interrupt flag */

+#define HRTIM_ISR_FLT3_Pos            (2U)

+#define HRTIM_ISR_FLT3_Msk            (0x1UL << HRTIM_ISR_FLT3_Pos)            /*!< 0x00000004 */

+#define HRTIM_ISR_FLT3                HRTIM_ISR_FLT3_Msk                       /*!< Fault 3 interrupt flag */

+#define HRTIM_ISR_FLT4_Pos            (3U)

+#define HRTIM_ISR_FLT4_Msk            (0x1UL << HRTIM_ISR_FLT4_Pos)            /*!< 0x00000008 */

+#define HRTIM_ISR_FLT4                HRTIM_ISR_FLT4_Msk                       /*!< Fault 4 interrupt flag */

+#define HRTIM_ISR_FLT5_Pos            (4U)

+#define HRTIM_ISR_FLT5_Msk            (0x1UL << HRTIM_ISR_FLT5_Pos)            /*!< 0x00000010 */

+#define HRTIM_ISR_FLT5                HRTIM_ISR_FLT5_Msk                       /*!< Fault 5 interrupt flag */

+#define HRTIM_ISR_SYSFLT_Pos          (5U)

+#define HRTIM_ISR_SYSFLT_Msk          (0x1UL << HRTIM_ISR_SYSFLT_Pos)          /*!< 0x00000020 */

+#define HRTIM_ISR_SYSFLT              HRTIM_ISR_SYSFLT_Msk                     /*!< System Fault interrupt flag */

+#define HRTIM_ISR_BMPER_Pos           (17U)

+#define HRTIM_ISR_BMPER_Msk           (0x1UL << HRTIM_ISR_BMPER_Pos)           /*!< 0x00020000 */

+#define HRTIM_ISR_BMPER               HRTIM_ISR_BMPER_Msk                      /*!<  Burst mode period interrupt flag */

+

+/**** Bit definition for Common HRTIM Timer interrupt clear register **********/

+#define HRTIM_ICR_FLT1C_Pos           (0U)

+#define HRTIM_ICR_FLT1C_Msk           (0x1UL << HRTIM_ICR_FLT1C_Pos)           /*!< 0x00000001 */

+#define HRTIM_ICR_FLT1C               HRTIM_ICR_FLT1C_Msk                      /*!< Fault 1 interrupt flag clear */

+#define HRTIM_ICR_FLT2C_Pos           (1U)

+#define HRTIM_ICR_FLT2C_Msk           (0x1UL << HRTIM_ICR_FLT2C_Pos)           /*!< 0x00000002 */

+#define HRTIM_ICR_FLT2C               HRTIM_ICR_FLT2C_Msk                      /*!< Fault 2 interrupt flag clear */

+#define HRTIM_ICR_FLT3C_Pos           (2U)

+#define HRTIM_ICR_FLT3C_Msk           (0x1UL << HRTIM_ICR_FLT3C_Pos)           /*!< 0x00000004 */

+#define HRTIM_ICR_FLT3C               HRTIM_ICR_FLT3C_Msk                      /*!< Fault 3 interrupt flag clear */

+#define HRTIM_ICR_FLT4C_Pos           (3U)

+#define HRTIM_ICR_FLT4C_Msk           (0x1UL << HRTIM_ICR_FLT4C_Pos)           /*!< 0x00000008 */

+#define HRTIM_ICR_FLT4C               HRTIM_ICR_FLT4C_Msk                      /*!< Fault 4 interrupt flag clear */

+#define HRTIM_ICR_FLT5C_Pos           (4U)

+#define HRTIM_ICR_FLT5C_Msk           (0x1UL << HRTIM_ICR_FLT5C_Pos)           /*!< 0x00000010 */

+#define HRTIM_ICR_FLT5C               HRTIM_ICR_FLT5C_Msk                      /*!< Fault 5 interrupt flag clear */

+#define HRTIM_ICR_SYSFLTC_Pos         (5U)

+#define HRTIM_ICR_SYSFLTC_Msk         (0x1UL << HRTIM_ICR_SYSFLTC_Pos)         /*!< 0x00000020 */

+#define HRTIM_ICR_SYSFLTC             HRTIM_ICR_SYSFLTC_Msk                    /*!< System Fault interrupt flag clear */

+#define HRTIM_ICR_BMPERC_Pos          (17U)

+#define HRTIM_ICR_BMPERC_Msk          (0x1UL << HRTIM_ICR_BMPERC_Pos)          /*!< 0x00020000 */

+#define HRTIM_ICR_BMPERC              HRTIM_ICR_BMPERC_Msk                     /*!<  Burst mode period interrupt flag clear */

+

+/**** Bit definition for Common HRTIM Timer interrupt enable register *********/

+#define HRTIM_IER_FLT1_Pos            (0U)

+#define HRTIM_IER_FLT1_Msk            (0x1UL << HRTIM_IER_FLT1_Pos)            /*!< 0x00000001 */

+#define HRTIM_IER_FLT1                HRTIM_IER_FLT1_Msk                       /*!< Fault 1 interrupt enable */

+#define HRTIM_IER_FLT2_Pos            (1U)

+#define HRTIM_IER_FLT2_Msk            (0x1UL << HRTIM_IER_FLT2_Pos)            /*!< 0x00000002 */

+#define HRTIM_IER_FLT2                HRTIM_IER_FLT2_Msk                       /*!< Fault 2 interrupt enable */

+#define HRTIM_IER_FLT3_Pos            (2U)

+#define HRTIM_IER_FLT3_Msk            (0x1UL << HRTIM_IER_FLT3_Pos)            /*!< 0x00000004 */

+#define HRTIM_IER_FLT3                HRTIM_IER_FLT3_Msk                       /*!< Fault 3 interrupt enable */

+#define HRTIM_IER_FLT4_Pos            (3U)

+#define HRTIM_IER_FLT4_Msk            (0x1UL << HRTIM_IER_FLT4_Pos)            /*!< 0x00000008 */

+#define HRTIM_IER_FLT4                HRTIM_IER_FLT4_Msk                       /*!< Fault 4 interrupt enable */

+#define HRTIM_IER_FLT5_Pos            (4U)

+#define HRTIM_IER_FLT5_Msk            (0x1UL << HRTIM_IER_FLT5_Pos)            /*!< 0x00000010 */

+#define HRTIM_IER_FLT5                HRTIM_IER_FLT5_Msk                       /*!< Fault 5 interrupt enable */

+#define HRTIM_IER_SYSFLT_Pos          (5U)

+#define HRTIM_IER_SYSFLT_Msk          (0x1UL << HRTIM_IER_SYSFLT_Pos)          /*!< 0x00000020 */

+#define HRTIM_IER_SYSFLT              HRTIM_IER_SYSFLT_Msk                     /*!< System Fault interrupt enable */

+#define HRTIM_IER_BMPER_Pos           (17U)

+#define HRTIM_IER_BMPER_Msk           (0x1UL << HRTIM_IER_BMPER_Pos)           /*!< 0x00020000 */

+#define HRTIM_IER_BMPER               HRTIM_IER_BMPER_Msk                      /*!<  Burst mode period interrupt enable */

+

+/**** Bit definition for Common HRTIM Timer output enable register ************/

+#define HRTIM_OENR_TA1OEN_Pos         (0U)

+#define HRTIM_OENR_TA1OEN_Msk         (0x1UL << HRTIM_OENR_TA1OEN_Pos)         /*!< 0x00000001 */

+#define HRTIM_OENR_TA1OEN             HRTIM_OENR_TA1OEN_Msk                    /*!< Timer A Output 1 enable */

+#define HRTIM_OENR_TA2OEN_Pos         (1U)

+#define HRTIM_OENR_TA2OEN_Msk         (0x1UL << HRTIM_OENR_TA2OEN_Pos)         /*!< 0x00000002 */

+#define HRTIM_OENR_TA2OEN             HRTIM_OENR_TA2OEN_Msk                    /*!< Timer A Output 2 enable */

+#define HRTIM_OENR_TB1OEN_Pos         (2U)

+#define HRTIM_OENR_TB1OEN_Msk         (0x1UL << HRTIM_OENR_TB1OEN_Pos)         /*!< 0x00000004 */

+#define HRTIM_OENR_TB1OEN             HRTIM_OENR_TB1OEN_Msk                    /*!< Timer B Output 1 enable */

+#define HRTIM_OENR_TB2OEN_Pos         (3U)

+#define HRTIM_OENR_TB2OEN_Msk         (0x1UL << HRTIM_OENR_TB2OEN_Pos)         /*!< 0x00000008 */

+#define HRTIM_OENR_TB2OEN             HRTIM_OENR_TB2OEN_Msk                    /*!< Timer B Output 2 enable */

+#define HRTIM_OENR_TC1OEN_Pos         (4U)

+#define HRTIM_OENR_TC1OEN_Msk         (0x1UL << HRTIM_OENR_TC1OEN_Pos)         /*!< 0x00000010 */

+#define HRTIM_OENR_TC1OEN             HRTIM_OENR_TC1OEN_Msk                    /*!< Timer C Output 1 enable */

+#define HRTIM_OENR_TC2OEN_Pos         (5U)

+#define HRTIM_OENR_TC2OEN_Msk         (0x1UL << HRTIM_OENR_TC2OEN_Pos)         /*!< 0x00000020 */

+#define HRTIM_OENR_TC2OEN             HRTIM_OENR_TC2OEN_Msk                    /*!< Timer C Output 2 enable */

+#define HRTIM_OENR_TD1OEN_Pos         (6U)

+#define HRTIM_OENR_TD1OEN_Msk         (0x1UL << HRTIM_OENR_TD1OEN_Pos)         /*!< 0x00000040 */

+#define HRTIM_OENR_TD1OEN             HRTIM_OENR_TD1OEN_Msk                    /*!< Timer D Output 1 enable */

+#define HRTIM_OENR_TD2OEN_Pos         (7U)

+#define HRTIM_OENR_TD2OEN_Msk         (0x1UL << HRTIM_OENR_TD2OEN_Pos)         /*!< 0x00000080 */

+#define HRTIM_OENR_TD2OEN             HRTIM_OENR_TD2OEN_Msk                    /*!< Timer D Output 2 enable */

+#define HRTIM_OENR_TE1OEN_Pos         (8U)

+#define HRTIM_OENR_TE1OEN_Msk         (0x1UL << HRTIM_OENR_TE1OEN_Pos)         /*!< 0x00000100 */

+#define HRTIM_OENR_TE1OEN             HRTIM_OENR_TE1OEN_Msk                    /*!< Timer E Output 1 enable */

+#define HRTIM_OENR_TE2OEN_Pos         (9U)

+#define HRTIM_OENR_TE2OEN_Msk         (0x1UL << HRTIM_OENR_TE2OEN_Pos)         /*!< 0x00000200 */

+#define HRTIM_OENR_TE2OEN             HRTIM_OENR_TE2OEN_Msk                    /*!< Timer E Output 2 enable */

+

+/**** Bit definition for Common HRTIM Timer output disable register ***********/

+#define HRTIM_ODISR_TA1ODIS_Pos       (0U)

+#define HRTIM_ODISR_TA1ODIS_Msk       (0x1UL << HRTIM_ODISR_TA1ODIS_Pos)       /*!< 0x00000001 */

+#define HRTIM_ODISR_TA1ODIS           HRTIM_ODISR_TA1ODIS_Msk                  /*!< Timer A Output 1 disable */

+#define HRTIM_ODISR_TA2ODIS_Pos       (1U)

+#define HRTIM_ODISR_TA2ODIS_Msk       (0x1UL << HRTIM_ODISR_TA2ODIS_Pos)       /*!< 0x00000002 */

+#define HRTIM_ODISR_TA2ODIS           HRTIM_ODISR_TA2ODIS_Msk                  /*!< Timer A Output 2 disable */

+#define HRTIM_ODISR_TB1ODIS_Pos       (2U)

+#define HRTIM_ODISR_TB1ODIS_Msk       (0x1UL << HRTIM_ODISR_TB1ODIS_Pos)       /*!< 0x00000004 */

+#define HRTIM_ODISR_TB1ODIS           HRTIM_ODISR_TB1ODIS_Msk                  /*!< Timer B Output 1 disable */

+#define HRTIM_ODISR_TB2ODIS_Pos       (3U)

+#define HRTIM_ODISR_TB2ODIS_Msk       (0x1UL << HRTIM_ODISR_TB2ODIS_Pos)       /*!< 0x00000008 */

+#define HRTIM_ODISR_TB2ODIS           HRTIM_ODISR_TB2ODIS_Msk                  /*!< Timer B Output 2 disable */

+#define HRTIM_ODISR_TC1ODIS_Pos       (4U)

+#define HRTIM_ODISR_TC1ODIS_Msk       (0x1UL << HRTIM_ODISR_TC1ODIS_Pos)       /*!< 0x00000010 */

+#define HRTIM_ODISR_TC1ODIS           HRTIM_ODISR_TC1ODIS_Msk                  /*!< Timer C Output 1 disable */

+#define HRTIM_ODISR_TC2ODIS_Pos       (5U)

+#define HRTIM_ODISR_TC2ODIS_Msk       (0x1UL << HRTIM_ODISR_TC2ODIS_Pos)       /*!< 0x00000020 */

+#define HRTIM_ODISR_TC2ODIS           HRTIM_ODISR_TC2ODIS_Msk                  /*!< Timer C Output 2 disable */

+#define HRTIM_ODISR_TD1ODIS_Pos       (6U)

+#define HRTIM_ODISR_TD1ODIS_Msk       (0x1UL << HRTIM_ODISR_TD1ODIS_Pos)       /*!< 0x00000040 */

+#define HRTIM_ODISR_TD1ODIS           HRTIM_ODISR_TD1ODIS_Msk                  /*!< Timer D Output 1 disable */

+#define HRTIM_ODISR_TD2ODIS_Pos       (7U)

+#define HRTIM_ODISR_TD2ODIS_Msk       (0x1UL << HRTIM_ODISR_TD2ODIS_Pos)       /*!< 0x00000080 */

+#define HRTIM_ODISR_TD2ODIS           HRTIM_ODISR_TD2ODIS_Msk                  /*!< Timer D Output 2 disable */

+#define HRTIM_ODISR_TE1ODIS_Pos       (8U)

+#define HRTIM_ODISR_TE1ODIS_Msk       (0x1UL << HRTIM_ODISR_TE1ODIS_Pos)       /*!< 0x00000100 */

+#define HRTIM_ODISR_TE1ODIS           HRTIM_ODISR_TE1ODIS_Msk                  /*!< Timer E Output 1 disable */

+#define HRTIM_ODISR_TE2ODIS_Pos       (9U)

+#define HRTIM_ODISR_TE2ODIS_Msk       (0x1UL << HRTIM_ODISR_TE2ODIS_Pos)       /*!< 0x00000200 */

+#define HRTIM_ODISR_TE2ODIS           HRTIM_ODISR_TE2ODIS_Msk                  /*!< Timer E Output 2 disable */

+

+/**** Bit definition for Common HRTIM Timer output disable status register *****/

+#define HRTIM_ODSR_TA1ODS_Pos         (0U)

+#define HRTIM_ODSR_TA1ODS_Msk         (0x1UL << HRTIM_ODSR_TA1ODS_Pos)         /*!< 0x00000001 */

+#define HRTIM_ODSR_TA1ODS             HRTIM_ODSR_TA1ODS_Msk                    /*!< Timer A Output 1 disable status */

+#define HRTIM_ODSR_TA2ODS_Pos         (1U)

+#define HRTIM_ODSR_TA2ODS_Msk         (0x1UL << HRTIM_ODSR_TA2ODS_Pos)         /*!< 0x00000002 */

+#define HRTIM_ODSR_TA2ODS             HRTIM_ODSR_TA2ODS_Msk                    /*!< Timer A Output 2 disable status */

+#define HRTIM_ODSR_TB1ODS_Pos         (2U)

+#define HRTIM_ODSR_TB1ODS_Msk         (0x1UL << HRTIM_ODSR_TB1ODS_Pos)         /*!< 0x00000004 */

+#define HRTIM_ODSR_TB1ODS             HRTIM_ODSR_TB1ODS_Msk                    /*!< Timer B Output 1 disable status */

+#define HRTIM_ODSR_TB2ODS_Pos         (3U)

+#define HRTIM_ODSR_TB2ODS_Msk         (0x1UL << HRTIM_ODSR_TB2ODS_Pos)         /*!< 0x00000008 */

+#define HRTIM_ODSR_TB2ODS             HRTIM_ODSR_TB2ODS_Msk                    /*!< Timer B Output 2 disable status */

+#define HRTIM_ODSR_TC1ODS_Pos         (4U)

+#define HRTIM_ODSR_TC1ODS_Msk         (0x1UL << HRTIM_ODSR_TC1ODS_Pos)         /*!< 0x00000010 */

+#define HRTIM_ODSR_TC1ODS             HRTIM_ODSR_TC1ODS_Msk                    /*!< Timer C Output 1 disable status */

+#define HRTIM_ODSR_TC2ODS_Pos         (5U)

+#define HRTIM_ODSR_TC2ODS_Msk         (0x1UL << HRTIM_ODSR_TC2ODS_Pos)         /*!< 0x00000020 */

+#define HRTIM_ODSR_TC2ODS             HRTIM_ODSR_TC2ODS_Msk                    /*!< Timer C Output 2 disable status */

+#define HRTIM_ODSR_TD1ODS_Pos         (6U)

+#define HRTIM_ODSR_TD1ODS_Msk         (0x1UL << HRTIM_ODSR_TD1ODS_Pos)         /*!< 0x00000040 */

+#define HRTIM_ODSR_TD1ODS             HRTIM_ODSR_TD1ODS_Msk                    /*!< Timer D Output 1 disable status */

+#define HRTIM_ODSR_TD2ODS_Pos         (7U)

+#define HRTIM_ODSR_TD2ODS_Msk         (0x1UL << HRTIM_ODSR_TD2ODS_Pos)         /*!< 0x00000080 */

+#define HRTIM_ODSR_TD2ODS             HRTIM_ODSR_TD2ODS_Msk                    /*!< Timer D Output 2 disable status */

+#define HRTIM_ODSR_TE1ODS_Pos         (8U)

+#define HRTIM_ODSR_TE1ODS_Msk         (0x1UL << HRTIM_ODSR_TE1ODS_Pos)         /*!< 0x00000100 */

+#define HRTIM_ODSR_TE1ODS             HRTIM_ODSR_TE1ODS_Msk                    /*!< Timer E Output 1 disable status */

+#define HRTIM_ODSR_TE2ODS_Pos         (9U)

+#define HRTIM_ODSR_TE2ODS_Msk         (0x1UL << HRTIM_ODSR_TE2ODS_Pos)         /*!< 0x00000200 */

+#define HRTIM_ODSR_TE2ODS             HRTIM_ODSR_TE2ODS_Msk                    /*!< Timer E Output 2 disable status */

+

+/**** Bit definition for Common HRTIM Timer Burst mode control register ********/

+#define HRTIM_BMCR_BME_Pos            (0U)

+#define HRTIM_BMCR_BME_Msk            (0x1UL << HRTIM_BMCR_BME_Pos)            /*!< 0x00000001 */

+#define HRTIM_BMCR_BME                HRTIM_BMCR_BME_Msk                       /*!< Burst mode enbale */

+#define HRTIM_BMCR_BMOM_Pos           (1U)

+#define HRTIM_BMCR_BMOM_Msk           (0x1UL << HRTIM_BMCR_BMOM_Pos)           /*!< 0x00000002 */

+#define HRTIM_BMCR_BMOM               HRTIM_BMCR_BMOM_Msk                      /*!< Burst mode operating mode */

+#define HRTIM_BMCR_BMCLK_Pos          (2U)

+#define HRTIM_BMCR_BMCLK_Msk          (0xFUL << HRTIM_BMCR_BMCLK_Pos)          /*!< 0x0000003C */

+#define HRTIM_BMCR_BMCLK              HRTIM_BMCR_BMCLK_Msk                     /*!< Burst mode clock source */

+#define HRTIM_BMCR_BMCLK_0            (0x1UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000004 */

+#define HRTIM_BMCR_BMCLK_1            (0x2UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000008 */

+#define HRTIM_BMCR_BMCLK_2            (0x4UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000010 */

+#define HRTIM_BMCR_BMCLK_3            (0x8UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000020 */

+#define HRTIM_BMCR_BMPRSC_Pos         (6U)

+#define HRTIM_BMCR_BMPRSC_Msk         (0xFUL << HRTIM_BMCR_BMPRSC_Pos)         /*!< 0x000003C0 */

+#define HRTIM_BMCR_BMPRSC             HRTIM_BMCR_BMPRSC_Msk                    /*!< Burst mode prescaler */

+#define HRTIM_BMCR_BMPRSC_0           (0x1UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000040 */

+#define HRTIM_BMCR_BMPRSC_1           (0x2UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000080 */

+#define HRTIM_BMCR_BMPRSC_2           (0x4UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000100 */

+#define HRTIM_BMCR_BMPRSC_3           (0x8UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000200 */

+#define HRTIM_BMCR_BMPREN_Pos         (10U)

+#define HRTIM_BMCR_BMPREN_Msk         (0x1UL << HRTIM_BMCR_BMPREN_Pos)         /*!< 0x00000400 */

+#define HRTIM_BMCR_BMPREN             HRTIM_BMCR_BMPREN_Msk                    /*!< Burst mode Preload bit */

+#define HRTIM_BMCR_MTBM_Pos           (16U)

+#define HRTIM_BMCR_MTBM_Msk           (0x1UL << HRTIM_BMCR_MTBM_Pos)           /*!< 0x00010000 */

+#define HRTIM_BMCR_MTBM               HRTIM_BMCR_MTBM_Msk                      /*!< Master Timer Burst mode */

+#define HRTIM_BMCR_TABM_Pos           (17U)

+#define HRTIM_BMCR_TABM_Msk           (0x1UL << HRTIM_BMCR_TABM_Pos)           /*!< 0x00020000 */

+#define HRTIM_BMCR_TABM               HRTIM_BMCR_TABM_Msk                      /*!< Timer A Burst mode */

+#define HRTIM_BMCR_TBBM_Pos           (18U)

+#define HRTIM_BMCR_TBBM_Msk           (0x1UL << HRTIM_BMCR_TBBM_Pos)           /*!< 0x00040000 */

+#define HRTIM_BMCR_TBBM               HRTIM_BMCR_TBBM_Msk                      /*!< Timer B Burst mode */

+#define HRTIM_BMCR_TCBM_Pos           (19U)

+#define HRTIM_BMCR_TCBM_Msk           (0x1UL << HRTIM_BMCR_TCBM_Pos)           /*!< 0x00080000 */

+#define HRTIM_BMCR_TCBM               HRTIM_BMCR_TCBM_Msk                      /*!< Timer C Burst mode */

+#define HRTIM_BMCR_TDBM_Pos           (20U)

+#define HRTIM_BMCR_TDBM_Msk           (0x1UL << HRTIM_BMCR_TDBM_Pos)           /*!< 0x00100000 */

+#define HRTIM_BMCR_TDBM               HRTIM_BMCR_TDBM_Msk                      /*!< Timer D Burst mode */

+#define HRTIM_BMCR_TEBM_Pos           (21U)

+#define HRTIM_BMCR_TEBM_Msk           (0x1UL << HRTIM_BMCR_TEBM_Pos)           /*!< 0x00200000 */

+#define HRTIM_BMCR_TEBM               HRTIM_BMCR_TEBM_Msk                      /*!< Timer E Burst mode */

+#define HRTIM_BMCR_BMSTAT_Pos         (31U)

+#define HRTIM_BMCR_BMSTAT_Msk         (0x1UL << HRTIM_BMCR_BMSTAT_Pos)         /*!< 0x80000000 */

+#define HRTIM_BMCR_BMSTAT             HRTIM_BMCR_BMSTAT_Msk                    /*!< Burst mode status */

+

+/**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/

+#define HRTIM_BMTRGR_SW_Pos           (0U)

+#define HRTIM_BMTRGR_SW_Msk           (0x1UL << HRTIM_BMTRGR_SW_Pos)           /*!< 0x00000001 */

+#define HRTIM_BMTRGR_SW               HRTIM_BMTRGR_SW_Msk                      /*!< Software start */

+#define HRTIM_BMTRGR_MSTRST_Pos       (1U)

+#define HRTIM_BMTRGR_MSTRST_Msk       (0x1UL << HRTIM_BMTRGR_MSTRST_Pos)       /*!< 0x00000002 */

+#define HRTIM_BMTRGR_MSTRST           HRTIM_BMTRGR_MSTRST_Msk                  /*!<  Master reset */

+#define HRTIM_BMTRGR_MSTREP_Pos       (2U)

+#define HRTIM_BMTRGR_MSTREP_Msk       (0x1UL << HRTIM_BMTRGR_MSTREP_Pos)       /*!< 0x00000004 */

+#define HRTIM_BMTRGR_MSTREP           HRTIM_BMTRGR_MSTREP_Msk                  /*!<  Master repetition */

+#define HRTIM_BMTRGR_MSTCMP1_Pos      (3U)

+#define HRTIM_BMTRGR_MSTCMP1_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos)      /*!< 0x00000008 */

+#define HRTIM_BMTRGR_MSTCMP1          HRTIM_BMTRGR_MSTCMP1_Msk                 /*!<  Master compare 1 */

+#define HRTIM_BMTRGR_MSTCMP2_Pos      (4U)

+#define HRTIM_BMTRGR_MSTCMP2_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos)      /*!< 0x00000010 */

+#define HRTIM_BMTRGR_MSTCMP2          HRTIM_BMTRGR_MSTCMP2_Msk                 /*!< Master compare 2  */

+#define HRTIM_BMTRGR_MSTCMP3_Pos      (5U)

+#define HRTIM_BMTRGR_MSTCMP3_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos)      /*!< 0x00000020 */

+#define HRTIM_BMTRGR_MSTCMP3          HRTIM_BMTRGR_MSTCMP3_Msk                 /*!< Master compare 3 */

+#define HRTIM_BMTRGR_MSTCMP4_Pos      (6U)

+#define HRTIM_BMTRGR_MSTCMP4_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos)      /*!< 0x00000040 */

+#define HRTIM_BMTRGR_MSTCMP4          HRTIM_BMTRGR_MSTCMP4_Msk                 /*!< Master compare 4 */

+#define HRTIM_BMTRGR_TARST_Pos        (7U)

+#define HRTIM_BMTRGR_TARST_Msk        (0x1UL << HRTIM_BMTRGR_TARST_Pos)        /*!< 0x00000080 */

+#define HRTIM_BMTRGR_TARST            HRTIM_BMTRGR_TARST_Msk                   /*!< Timer A reset  */

+#define HRTIM_BMTRGR_TAREP_Pos        (8U)

+#define HRTIM_BMTRGR_TAREP_Msk        (0x1UL << HRTIM_BMTRGR_TAREP_Pos)        /*!< 0x00000100 */

+#define HRTIM_BMTRGR_TAREP            HRTIM_BMTRGR_TAREP_Msk                   /*!< Timer A repetition  */

+#define HRTIM_BMTRGR_TACMP1_Pos       (9U)

+#define HRTIM_BMTRGR_TACMP1_Msk       (0x1UL << HRTIM_BMTRGR_TACMP1_Pos)       /*!< 0x00000200 */

+#define HRTIM_BMTRGR_TACMP1           HRTIM_BMTRGR_TACMP1_Msk                  /*!< Timer A compare 1  */

+#define HRTIM_BMTRGR_TACMP2_Pos       (10U)

+#define HRTIM_BMTRGR_TACMP2_Msk       (0x1UL << HRTIM_BMTRGR_TACMP2_Pos)       /*!< 0x00000400 */

+#define HRTIM_BMTRGR_TACMP2           HRTIM_BMTRGR_TACMP2_Msk                  /*!< Timer A compare 2  */

+#define HRTIM_BMTRGR_TBRST_Pos        (11U)

+#define HRTIM_BMTRGR_TBRST_Msk        (0x1UL << HRTIM_BMTRGR_TBRST_Pos)        /*!< 0x00000800 */

+#define HRTIM_BMTRGR_TBRST            HRTIM_BMTRGR_TBRST_Msk                   /*!< Timer B reset  */

+#define HRTIM_BMTRGR_TBREP_Pos        (12U)

+#define HRTIM_BMTRGR_TBREP_Msk        (0x1UL << HRTIM_BMTRGR_TBREP_Pos)        /*!< 0x00001000 */

+#define HRTIM_BMTRGR_TBREP            HRTIM_BMTRGR_TBREP_Msk                   /*!< Timer B repetition  */

+#define HRTIM_BMTRGR_TBCMP1_Pos       (13U)

+#define HRTIM_BMTRGR_TBCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos)       /*!< 0x00002000 */

+#define HRTIM_BMTRGR_TBCMP1           HRTIM_BMTRGR_TBCMP1_Msk                  /*!< Timer B compare 1 */

+#define HRTIM_BMTRGR_TBCMP2_Pos       (14U)

+#define HRTIM_BMTRGR_TBCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos)       /*!< 0x00004000 */

+#define HRTIM_BMTRGR_TBCMP2           HRTIM_BMTRGR_TBCMP2_Msk                  /*!< Timer B compare 2 */

+#define HRTIM_BMTRGR_TCRST_Pos        (15U)

+#define HRTIM_BMTRGR_TCRST_Msk        (0x1UL << HRTIM_BMTRGR_TCRST_Pos)        /*!< 0x00008000 */

+#define HRTIM_BMTRGR_TCRST            HRTIM_BMTRGR_TCRST_Msk                   /*!< Timer C reset  */

+#define HRTIM_BMTRGR_TCREP_Pos        (16U)

+#define HRTIM_BMTRGR_TCREP_Msk        (0x1UL << HRTIM_BMTRGR_TCREP_Pos)        /*!< 0x00010000 */

+#define HRTIM_BMTRGR_TCREP            HRTIM_BMTRGR_TCREP_Msk                   /*!< Timer C repetition */

+#define HRTIM_BMTRGR_TCCMP1_Pos       (17U)

+#define HRTIM_BMTRGR_TCCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos)       /*!< 0x00020000 */

+#define HRTIM_BMTRGR_TCCMP1           HRTIM_BMTRGR_TCCMP1_Msk                  /*!< Timer C compare 1 */

+#define HRTIM_BMTRGR_TCCMP2_Pos       (18U)

+#define HRTIM_BMTRGR_TCCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP2_Pos)       /*!< 0x00040000 */

+#define HRTIM_BMTRGR_TCCMP2           HRTIM_BMTRGR_TCCMP2_Msk                  /*!< Timer C compare 2 */

+#define HRTIM_BMTRGR_TDRST_Pos        (19U)

+#define HRTIM_BMTRGR_TDRST_Msk        (0x1UL << HRTIM_BMTRGR_TDRST_Pos)        /*!< 0x00080000 */

+#define HRTIM_BMTRGR_TDRST            HRTIM_BMTRGR_TDRST_Msk                   /*!< Timer D reset  */

+#define HRTIM_BMTRGR_TDREP_Pos        (20U)

+#define HRTIM_BMTRGR_TDREP_Msk        (0x1UL << HRTIM_BMTRGR_TDREP_Pos)        /*!< 0x00100000 */

+#define HRTIM_BMTRGR_TDREP            HRTIM_BMTRGR_TDREP_Msk                   /*!< Timer D repetition  */

+#define HRTIM_BMTRGR_TDCMP1_Pos       (21U)

+#define HRTIM_BMTRGR_TDCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP1_Pos)       /*!< 0x00200000 */

+#define HRTIM_BMTRGR_TDCMP1           HRTIM_BMTRGR_TDCMP1_Msk                  /*!< Timer D compare 1 */

+#define HRTIM_BMTRGR_TDCMP2_Pos       (22U)

+#define HRTIM_BMTRGR_TDCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos)       /*!< 0x00400000 */

+#define HRTIM_BMTRGR_TDCMP2           HRTIM_BMTRGR_TDCMP2_Msk                  /*!< Timer D compare 2 */

+#define HRTIM_BMTRGR_TERST_Pos        (23U)

+#define HRTIM_BMTRGR_TERST_Msk        (0x1UL << HRTIM_BMTRGR_TERST_Pos)        /*!< 0x00800000 */

+#define HRTIM_BMTRGR_TERST            HRTIM_BMTRGR_TERST_Msk                   /*!< Timer E reset  */

+#define HRTIM_BMTRGR_TEREP_Pos        (24U)

+#define HRTIM_BMTRGR_TEREP_Msk        (0x1UL << HRTIM_BMTRGR_TEREP_Pos)        /*!< 0x01000000 */

+#define HRTIM_BMTRGR_TEREP            HRTIM_BMTRGR_TEREP_Msk                   /*!< Timer E repetition  */

+#define HRTIM_BMTRGR_TECMP1_Pos       (25U)

+#define HRTIM_BMTRGR_TECMP1_Msk       (0x1UL << HRTIM_BMTRGR_TECMP1_Pos)       /*!< 0x02000000 */

+#define HRTIM_BMTRGR_TECMP1           HRTIM_BMTRGR_TECMP1_Msk                  /*!< Timer E compare 1 */

+#define HRTIM_BMTRGR_TECMP2_Pos       (26U)

+#define HRTIM_BMTRGR_TECMP2_Msk       (0x1UL << HRTIM_BMTRGR_TECMP2_Pos)       /*!< 0x04000000 */

+#define HRTIM_BMTRGR_TECMP2           HRTIM_BMTRGR_TECMP2_Msk                  /*!< Timer E compare 2 */

+#define HRTIM_BMTRGR_TAEEV7_Pos       (27U)

+#define HRTIM_BMTRGR_TAEEV7_Msk       (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos)       /*!< 0x08000000 */

+#define HRTIM_BMTRGR_TAEEV7           HRTIM_BMTRGR_TAEEV7_Msk                  /*!< Timer A period following External Event7  */

+#define HRTIM_BMTRGR_TDEEV8_Pos       (28U)

+#define HRTIM_BMTRGR_TDEEV8_Msk       (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos)       /*!< 0x10000000 */

+#define HRTIM_BMTRGR_TDEEV8           HRTIM_BMTRGR_TDEEV8_Msk                  /*!< Timer D period following External Event8  */

+#define HRTIM_BMTRGR_EEV7_Pos         (29U)

+#define HRTIM_BMTRGR_EEV7_Msk         (0x1UL << HRTIM_BMTRGR_EEV7_Pos)         /*!< 0x20000000 */

+#define HRTIM_BMTRGR_EEV7             HRTIM_BMTRGR_EEV7_Msk                    /*!< External Event 7 */

+#define HRTIM_BMTRGR_EEV8_Pos         (30U)

+#define HRTIM_BMTRGR_EEV8_Msk         (0x1UL << HRTIM_BMTRGR_EEV8_Pos)         /*!< 0x40000000 */

+#define HRTIM_BMTRGR_EEV8             HRTIM_BMTRGR_EEV8_Msk                    /*!< External Event 8 */

+#define HRTIM_BMTRGR_OCHPEV_Pos       (31U)

+#define HRTIM_BMTRGR_OCHPEV_Msk       (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos)       /*!< 0x80000000 */

+#define HRTIM_BMTRGR_OCHPEV           HRTIM_BMTRGR_OCHPEV_Msk                  /*!< on-chip Event */

+

+/*******************  Bit definition for HRTIM_BMCMPR register  ***************/

+#define HRTIM_BMCMPR_BMCMPR_Pos       (0U)

+#define HRTIM_BMCMPR_BMCMPR_Msk       (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_BMCMPR_BMCMPR           HRTIM_BMCMPR_BMCMPR_Msk                  /*!<!<Burst Compare Value */

+

+/*******************  Bit definition for HRTIM_BMPER register  ****************/

+#define HRTIM_BMPER_BMPER_Pos         (0U)

+#define HRTIM_BMPER_BMPER_Msk         (0xFFFFUL << HRTIM_BMPER_BMPER_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_BMPER_BMPER             HRTIM_BMPER_BMPER_Msk                    /*!<!<Burst period Value */

+

+/*******************  Bit definition for HRTIM_EECR1 register  ****************/

+#define HRTIM_EECR1_EE1SRC_Pos        (0U)

+#define HRTIM_EECR1_EE1SRC_Msk        (0x3UL << HRTIM_EECR1_EE1SRC_Pos)        /*!< 0x00000003 */

+#define HRTIM_EECR1_EE1SRC            HRTIM_EECR1_EE1SRC_Msk                   /*!< External event 1 source */

+#define HRTIM_EECR1_EE1SRC_0          (0x1UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000001 */

+#define HRTIM_EECR1_EE1SRC_1          (0x2UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000002 */

+#define HRTIM_EECR1_EE1POL_Pos        (2U)

+#define HRTIM_EECR1_EE1POL_Msk        (0x1UL << HRTIM_EECR1_EE1POL_Pos)        /*!< 0x00000004 */

+#define HRTIM_EECR1_EE1POL            HRTIM_EECR1_EE1POL_Msk                   /*!< External event 1 Polarity */

+#define HRTIM_EECR1_EE1SNS_Pos        (3U)

+#define HRTIM_EECR1_EE1SNS_Msk        (0x3UL << HRTIM_EECR1_EE1SNS_Pos)        /*!< 0x00000018 */

+#define HRTIM_EECR1_EE1SNS            HRTIM_EECR1_EE1SNS_Msk                   /*!< External event 1 sensitivity */

+#define HRTIM_EECR1_EE1SNS_0          (0x1UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000008 */

+#define HRTIM_EECR1_EE1SNS_1          (0x2UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000010 */

+#define HRTIM_EECR1_EE1FAST_Pos       (5U)

+#define HRTIM_EECR1_EE1FAST_Msk       (0x1UL << HRTIM_EECR1_EE1FAST_Pos)       /*!< 0x00000020 */

+#define HRTIM_EECR1_EE1FAST           HRTIM_EECR1_EE1FAST_Msk                  /*!< External event 1 Fast mode */

+

+#define HRTIM_EECR1_EE2SRC_Pos        (6U)

+#define HRTIM_EECR1_EE2SRC_Msk        (0x3UL << HRTIM_EECR1_EE2SRC_Pos)        /*!< 0x000000C0 */

+#define HRTIM_EECR1_EE2SRC            HRTIM_EECR1_EE2SRC_Msk                   /*!< External event 2 source */

+#define HRTIM_EECR1_EE2SRC_0          (0x1UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000040 */

+#define HRTIM_EECR1_EE2SRC_1          (0x2UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000080 */

+#define HRTIM_EECR1_EE2POL_Pos        (8U)

+#define HRTIM_EECR1_EE2POL_Msk        (0x1UL << HRTIM_EECR1_EE2POL_Pos)        /*!< 0x00000100 */

+#define HRTIM_EECR1_EE2POL            HRTIM_EECR1_EE2POL_Msk                   /*!< External event 2 Polarity */

+#define HRTIM_EECR1_EE2SNS_Pos        (9U)

+#define HRTIM_EECR1_EE2SNS_Msk        (0x3UL << HRTIM_EECR1_EE2SNS_Pos)        /*!< 0x00000600 */

+#define HRTIM_EECR1_EE2SNS            HRTIM_EECR1_EE2SNS_Msk                   /*!< External event 2 sensitivity */

+#define HRTIM_EECR1_EE2SNS_0          (0x1UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000200 */

+#define HRTIM_EECR1_EE2SNS_1          (0x2UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000400 */

+#define HRTIM_EECR1_EE2FAST_Pos       (11U)

+#define HRTIM_EECR1_EE2FAST_Msk       (0x1UL << HRTIM_EECR1_EE2FAST_Pos)       /*!< 0x00000800 */

+#define HRTIM_EECR1_EE2FAST           HRTIM_EECR1_EE2FAST_Msk                  /*!< External event 2 Fast mode */

+

+#define HRTIM_EECR1_EE3SRC_Pos        (12U)

+#define HRTIM_EECR1_EE3SRC_Msk        (0x3UL << HRTIM_EECR1_EE3SRC_Pos)        /*!< 0x00003000 */

+#define HRTIM_EECR1_EE3SRC            HRTIM_EECR1_EE3SRC_Msk                   /*!< External event 3 source */

+#define HRTIM_EECR1_EE3SRC_0          (0x1UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00001000 */

+#define HRTIM_EECR1_EE3SRC_1          (0x2UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00002000 */

+#define HRTIM_EECR1_EE3POL_Pos        (14U)

+#define HRTIM_EECR1_EE3POL_Msk        (0x1UL << HRTIM_EECR1_EE3POL_Pos)        /*!< 0x00004000 */

+#define HRTIM_EECR1_EE3POL            HRTIM_EECR1_EE3POL_Msk                   /*!< External event 3 Polarity */

+#define HRTIM_EECR1_EE3SNS_Pos        (15U)

+#define HRTIM_EECR1_EE3SNS_Msk        (0x3UL << HRTIM_EECR1_EE3SNS_Pos)        /*!< 0x00018000 */

+#define HRTIM_EECR1_EE3SNS            HRTIM_EECR1_EE3SNS_Msk                   /*!< External event 3 sensitivity */

+#define HRTIM_EECR1_EE3SNS_0          (0x1UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00008000 */

+#define HRTIM_EECR1_EE3SNS_1          (0x2UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00010000 */

+#define HRTIM_EECR1_EE3FAST_Pos       (17U)

+#define HRTIM_EECR1_EE3FAST_Msk       (0x1UL << HRTIM_EECR1_EE3FAST_Pos)       /*!< 0x00020000 */

+#define HRTIM_EECR1_EE3FAST           HRTIM_EECR1_EE3FAST_Msk                  /*!< External event 3 Fast mode */

+

+#define HRTIM_EECR1_EE4SRC_Pos        (18U)

+#define HRTIM_EECR1_EE4SRC_Msk        (0x3UL << HRTIM_EECR1_EE4SRC_Pos)        /*!< 0x000C0000 */

+#define HRTIM_EECR1_EE4SRC            HRTIM_EECR1_EE4SRC_Msk                   /*!< External event 4 source */

+#define HRTIM_EECR1_EE4SRC_0          (0x1UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00040000 */

+#define HRTIM_EECR1_EE4SRC_1          (0x2UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00080000 */

+#define HRTIM_EECR1_EE4POL_Pos        (20U)

+#define HRTIM_EECR1_EE4POL_Msk        (0x1UL << HRTIM_EECR1_EE4POL_Pos)        /*!< 0x00100000 */

+#define HRTIM_EECR1_EE4POL            HRTIM_EECR1_EE4POL_Msk                   /*!< External event 4 Polarity */

+#define HRTIM_EECR1_EE4SNS_Pos        (21U)

+#define HRTIM_EECR1_EE4SNS_Msk        (0x3UL << HRTIM_EECR1_EE4SNS_Pos)        /*!< 0x00600000 */

+#define HRTIM_EECR1_EE4SNS            HRTIM_EECR1_EE4SNS_Msk                   /*!< External event 4 sensitivity */

+#define HRTIM_EECR1_EE4SNS_0          (0x1UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00200000 */

+#define HRTIM_EECR1_EE4SNS_1          (0x2UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00400000 */

+#define HRTIM_EECR1_EE4FAST_Pos       (23U)

+#define HRTIM_EECR1_EE4FAST_Msk       (0x1UL << HRTIM_EECR1_EE4FAST_Pos)       /*!< 0x00800000 */

+#define HRTIM_EECR1_EE4FAST           HRTIM_EECR1_EE4FAST_Msk                  /*!< External event 4 Fast mode */

+

+#define HRTIM_EECR1_EE5SRC_Pos        (24U)

+#define HRTIM_EECR1_EE5SRC_Msk        (0x3UL << HRTIM_EECR1_EE5SRC_Pos)        /*!< 0x03000000 */

+#define HRTIM_EECR1_EE5SRC            HRTIM_EECR1_EE5SRC_Msk                   /*!< External event 5 source */

+#define HRTIM_EECR1_EE5SRC_0          (0x1UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x01000000 */

+#define HRTIM_EECR1_EE5SRC_1          (0x2UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x02000000 */

+#define HRTIM_EECR1_EE5POL_Pos        (26U)

+#define HRTIM_EECR1_EE5POL_Msk        (0x1UL << HRTIM_EECR1_EE5POL_Pos)        /*!< 0x04000000 */

+#define HRTIM_EECR1_EE5POL            HRTIM_EECR1_EE5POL_Msk                   /*!< External event 5 Polarity */

+#define HRTIM_EECR1_EE5SNS_Pos        (27U)

+#define HRTIM_EECR1_EE5SNS_Msk        (0x3UL << HRTIM_EECR1_EE5SNS_Pos)        /*!< 0x18000000 */

+#define HRTIM_EECR1_EE5SNS            HRTIM_EECR1_EE5SNS_Msk                   /*!< External event 5 sensitivity */

+#define HRTIM_EECR1_EE5SNS_0          (0x1UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x08000000 */

+#define HRTIM_EECR1_EE5SNS_1          (0x2UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x10000000 */

+#define HRTIM_EECR1_EE5FAST_Pos       (29U)

+#define HRTIM_EECR1_EE5FAST_Msk       (0x1UL << HRTIM_EECR1_EE5FAST_Pos)       /*!< 0x20000000 */

+#define HRTIM_EECR1_EE5FAST           HRTIM_EECR1_EE5FAST_Msk                  /*!< External event 5 Fast mode */

+

+/*******************  Bit definition for HRTIM_EECR2 register  ****************/

+#define HRTIM_EECR2_EE6SRC_Pos        (0U)

+#define HRTIM_EECR2_EE6SRC_Msk        (0x3UL << HRTIM_EECR2_EE6SRC_Pos)        /*!< 0x00000003 */

+#define HRTIM_EECR2_EE6SRC            HRTIM_EECR2_EE6SRC_Msk                   /*!< External event 6 source */

+#define HRTIM_EECR2_EE6SRC_0          (0x1UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000001 */

+#define HRTIM_EECR2_EE6SRC_1          (0x2UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000002 */

+#define HRTIM_EECR2_EE6POL_Pos        (2U)

+#define HRTIM_EECR2_EE6POL_Msk        (0x1UL << HRTIM_EECR2_EE6POL_Pos)        /*!< 0x00000004 */

+#define HRTIM_EECR2_EE6POL            HRTIM_EECR2_EE6POL_Msk                   /*!< External event 6 Polarity */

+#define HRTIM_EECR2_EE6SNS_Pos        (3U)

+#define HRTIM_EECR2_EE6SNS_Msk        (0x3UL << HRTIM_EECR2_EE6SNS_Pos)        /*!< 0x00000018 */

+#define HRTIM_EECR2_EE6SNS            HRTIM_EECR2_EE6SNS_Msk                   /*!< External event 6 sensitivity */

+#define HRTIM_EECR2_EE6SNS_0          (0x1UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000008 */

+#define HRTIM_EECR2_EE6SNS_1          (0x2UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000010 */

+

+#define HRTIM_EECR2_EE7SRC_Pos        (6U)

+#define HRTIM_EECR2_EE7SRC_Msk        (0x3UL << HRTIM_EECR2_EE7SRC_Pos)        /*!< 0x000000C0 */

+#define HRTIM_EECR2_EE7SRC            HRTIM_EECR2_EE7SRC_Msk                   /*!< External event 7 source */

+#define HRTIM_EECR2_EE7SRC_0          (0x1UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000040 */

+#define HRTIM_EECR2_EE7SRC_1          (0x2UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000080 */

+#define HRTIM_EECR2_EE7POL_Pos        (8U)

+#define HRTIM_EECR2_EE7POL_Msk        (0x1UL << HRTIM_EECR2_EE7POL_Pos)        /*!< 0x00000100 */

+#define HRTIM_EECR2_EE7POL            HRTIM_EECR2_EE7POL_Msk                   /*!< External event 7 Polarity */

+#define HRTIM_EECR2_EE7SNS_Pos        (9U)

+#define HRTIM_EECR2_EE7SNS_Msk        (0x3UL << HRTIM_EECR2_EE7SNS_Pos)        /*!< 0x00000600 */

+#define HRTIM_EECR2_EE7SNS            HRTIM_EECR2_EE7SNS_Msk                   /*!< External event 7 sensitivity */

+#define HRTIM_EECR2_EE7SNS_0          (0x1UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000200 */

+#define HRTIM_EECR2_EE7SNS_1          (0x2UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000400 */

+

+#define HRTIM_EECR2_EE8SRC_Pos        (12U)

+#define HRTIM_EECR2_EE8SRC_Msk        (0x3UL << HRTIM_EECR2_EE8SRC_Pos)        /*!< 0x00003000 */

+#define HRTIM_EECR2_EE8SRC            HRTIM_EECR2_EE8SRC_Msk                   /*!< External event 8 source */

+#define HRTIM_EECR2_EE8SRC_0          (0x1UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00001000 */

+#define HRTIM_EECR2_EE8SRC_1          (0x2UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00002000 */

+#define HRTIM_EECR2_EE8POL_Pos        (14U)

+#define HRTIM_EECR2_EE8POL_Msk        (0x1UL << HRTIM_EECR2_EE8POL_Pos)        /*!< 0x00004000 */

+#define HRTIM_EECR2_EE8POL            HRTIM_EECR2_EE8POL_Msk                   /*!< External event 8 Polarity */

+#define HRTIM_EECR2_EE8SNS_Pos        (15U)

+#define HRTIM_EECR2_EE8SNS_Msk        (0x3UL << HRTIM_EECR2_EE8SNS_Pos)        /*!< 0x00018000 */

+#define HRTIM_EECR2_EE8SNS            HRTIM_EECR2_EE8SNS_Msk                   /*!< External event 8 sensitivity */

+#define HRTIM_EECR2_EE8SNS_0          (0x1UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00008000 */

+#define HRTIM_EECR2_EE8SNS_1          (0x2UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00010000 */

+

+#define HRTIM_EECR2_EE9SRC_Pos        (18U)

+#define HRTIM_EECR2_EE9SRC_Msk        (0x3UL << HRTIM_EECR2_EE9SRC_Pos)        /*!< 0x000C0000 */

+#define HRTIM_EECR2_EE9SRC            HRTIM_EECR2_EE9SRC_Msk                   /*!< External event 9 source */

+#define HRTIM_EECR2_EE9SRC_0          (0x1UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00040000 */

+#define HRTIM_EECR2_EE9SRC_1          (0x2UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00080000 */

+#define HRTIM_EECR2_EE9POL_Pos        (20U)

+#define HRTIM_EECR2_EE9POL_Msk        (0x1UL << HRTIM_EECR2_EE9POL_Pos)        /*!< 0x00100000 */

+#define HRTIM_EECR2_EE9POL            HRTIM_EECR2_EE9POL_Msk                   /*!< External event 9 Polarity */

+#define HRTIM_EECR2_EE9SNS_Pos        (21U)

+#define HRTIM_EECR2_EE9SNS_Msk        (0x3UL << HRTIM_EECR2_EE9SNS_Pos)        /*!< 0x00600000 */

+#define HRTIM_EECR2_EE9SNS            HRTIM_EECR2_EE9SNS_Msk                   /*!< External event 9 sensitivity */

+#define HRTIM_EECR2_EE9SNS_0          (0x1UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00200000 */

+#define HRTIM_EECR2_EE9SNS_1          (0x2UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00400000 */

+

+#define HRTIM_EECR2_EE10SRC_Pos       (24U)

+#define HRTIM_EECR2_EE10SRC_Msk       (0x3UL << HRTIM_EECR2_EE10SRC_Pos)       /*!< 0x03000000 */

+#define HRTIM_EECR2_EE10SRC           HRTIM_EECR2_EE10SRC_Msk                  /*!< External event 10 source */

+#define HRTIM_EECR2_EE10SRC_0         (0x1UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x01000000 */

+#define HRTIM_EECR2_EE10SRC_1         (0x2UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x02000000 */

+#define HRTIM_EECR2_EE10POL_Pos       (26U)

+#define HRTIM_EECR2_EE10POL_Msk       (0x1UL << HRTIM_EECR2_EE10POL_Pos)       /*!< 0x04000000 */

+#define HRTIM_EECR2_EE10POL           HRTIM_EECR2_EE10POL_Msk                  /*!< External event 10 Polarity */

+#define HRTIM_EECR2_EE10SNS_Pos       (27U)

+#define HRTIM_EECR2_EE10SNS_Msk       (0x3UL << HRTIM_EECR2_EE10SNS_Pos)       /*!< 0x18000000 */

+#define HRTIM_EECR2_EE10SNS           HRTIM_EECR2_EE10SNS_Msk                  /*!< External event 10 sensitivity */

+#define HRTIM_EECR2_EE10SNS_0         (0x1UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x08000000 */

+#define HRTIM_EECR2_EE10SNS_1         (0x2UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x10000000 */

+

+/*******************  Bit definition for HRTIM_EECR3 register  ****************/

+#define HRTIM_EECR3_EE6F_Pos          (0U)

+#define HRTIM_EECR3_EE6F_Msk          (0xFUL << HRTIM_EECR3_EE6F_Pos)          /*!< 0x0000000F */

+#define HRTIM_EECR3_EE6F              HRTIM_EECR3_EE6F_Msk                     /*!< External event 6 filter */

+#define HRTIM_EECR3_EE6F_0            (0x1UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000001 */

+#define HRTIM_EECR3_EE6F_1            (0x2UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000002 */

+#define HRTIM_EECR3_EE6F_2            (0x4UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000004 */

+#define HRTIM_EECR3_EE6F_3            (0x8UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000008 */

+#define HRTIM_EECR3_EE7F_Pos          (6U)

+#define HRTIM_EECR3_EE7F_Msk          (0xFUL << HRTIM_EECR3_EE7F_Pos)          /*!< 0x000003C0 */

+#define HRTIM_EECR3_EE7F              HRTIM_EECR3_EE7F_Msk                     /*!< External event 7 filter */

+#define HRTIM_EECR3_EE7F_0            (0x1UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000040 */

+#define HRTIM_EECR3_EE7F_1            (0x2UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000080 */

+#define HRTIM_EECR3_EE7F_2            (0x4UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000100 */

+#define HRTIM_EECR3_EE7F_3            (0x8UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000200 */

+#define HRTIM_EECR3_EE8F_Pos          (12U)

+#define HRTIM_EECR3_EE8F_Msk          (0xFUL << HRTIM_EECR3_EE8F_Pos)          /*!< 0x0000F000 */

+#define HRTIM_EECR3_EE8F              HRTIM_EECR3_EE8F_Msk                     /*!< External event 8 filter */

+#define HRTIM_EECR3_EE8F_0            (0x1UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00001000 */

+#define HRTIM_EECR3_EE8F_1            (0x2UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00002000 */

+#define HRTIM_EECR3_EE8F_2            (0x4UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00004000 */

+#define HRTIM_EECR3_EE8F_3            (0x8UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00008000 */

+#define HRTIM_EECR3_EE9F_Pos          (18U)

+#define HRTIM_EECR3_EE9F_Msk          (0xFUL << HRTIM_EECR3_EE9F_Pos)          /*!< 0x003C0000 */

+#define HRTIM_EECR3_EE9F              HRTIM_EECR3_EE9F_Msk                     /*!< External event 9 filter */

+#define HRTIM_EECR3_EE9F_0            (0x1UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00040000 */

+#define HRTIM_EECR3_EE9F_1            (0x2UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00080000 */

+#define HRTIM_EECR3_EE9F_2            (0x4UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00100000 */

+#define HRTIM_EECR3_EE9F_3            (0x8UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00200000 */

+#define HRTIM_EECR3_EE10F_Pos         (24U)

+#define HRTIM_EECR3_EE10F_Msk         (0xFUL << HRTIM_EECR3_EE10F_Pos)         /*!< 0x0F000000 */

+#define HRTIM_EECR3_EE10F             HRTIM_EECR3_EE10F_Msk                    /*!< External event 10 filter */

+#define HRTIM_EECR3_EE10F_0           (0x1UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x01000000 */

+#define HRTIM_EECR3_EE10F_1           (0x2UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x02000000 */

+#define HRTIM_EECR3_EE10F_2           (0x4UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x04000000 */

+#define HRTIM_EECR3_EE10F_3           (0x8UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x08000000 */

+#define HRTIM_EECR3_EEVSD_Pos         (30U)

+#define HRTIM_EECR3_EEVSD_Msk         (0x3UL << HRTIM_EECR3_EEVSD_Pos)         /*!< 0xC0000000 */

+#define HRTIM_EECR3_EEVSD             HRTIM_EECR3_EEVSD_Msk                    /*!< External event sampling clock division */

+#define HRTIM_EECR3_EEVSD_0           (0x1UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x40000000 */

+#define HRTIM_EECR3_EEVSD_1           (0x2UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x80000000 */

+

+/*******************  Bit definition for HRTIM_ADC1R register  ****************/

+#define HRTIM_ADC1R_AD1MC1_Pos        (0U)

+#define HRTIM_ADC1R_AD1MC1_Msk        (0x1UL << HRTIM_ADC1R_AD1MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC1R_AD1MC1            HRTIM_ADC1R_AD1MC1_Msk                   /*!< ADC Trigger 1 on master compare 1 */

+#define HRTIM_ADC1R_AD1MC2_Pos        (1U)

+#define HRTIM_ADC1R_AD1MC2_Msk        (0x1UL << HRTIM_ADC1R_AD1MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC1R_AD1MC2            HRTIM_ADC1R_AD1MC2_Msk                   /*!< ADC Trigger 1 on master compare 2 */

+#define HRTIM_ADC1R_AD1MC3_Pos        (2U)

+#define HRTIM_ADC1R_AD1MC3_Msk        (0x1UL << HRTIM_ADC1R_AD1MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC1R_AD1MC3            HRTIM_ADC1R_AD1MC3_Msk                   /*!< ADC Trigger 1 on master compare 3 */

+#define HRTIM_ADC1R_AD1MC4_Pos        (3U)

+#define HRTIM_ADC1R_AD1MC4_Msk        (0x1UL << HRTIM_ADC1R_AD1MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC1R_AD1MC4            HRTIM_ADC1R_AD1MC4_Msk                   /*!< ADC Trigger 1 on master compare 4 */

+#define HRTIM_ADC1R_AD1MPER_Pos       (4U)

+#define HRTIM_ADC1R_AD1MPER_Msk       (0x1UL << HRTIM_ADC1R_AD1MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC1R_AD1MPER           HRTIM_ADC1R_AD1MPER_Msk                  /*!< ADC Trigger 1 on master period */

+#define HRTIM_ADC1R_AD1EEV1_Pos       (5U)

+#define HRTIM_ADC1R_AD1EEV1_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC1R_AD1EEV1           HRTIM_ADC1R_AD1EEV1_Msk                  /*!< ADC Trigger 1 on external event 1 */

+#define HRTIM_ADC1R_AD1EEV2_Pos       (6U)

+#define HRTIM_ADC1R_AD1EEV2_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC1R_AD1EEV2           HRTIM_ADC1R_AD1EEV2_Msk                  /*!< ADC Trigger 1 on external event 2 */

+#define HRTIM_ADC1R_AD1EEV3_Pos       (7U)

+#define HRTIM_ADC1R_AD1EEV3_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC1R_AD1EEV3           HRTIM_ADC1R_AD1EEV3_Msk                  /*!< ADC Trigger 1 on external event 3 */

+#define HRTIM_ADC1R_AD1EEV4_Pos       (8U)

+#define HRTIM_ADC1R_AD1EEV4_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC1R_AD1EEV4           HRTIM_ADC1R_AD1EEV4_Msk                  /*!< ADC Trigger 1 on external event 4 */

+#define HRTIM_ADC1R_AD1EEV5_Pos       (9U)

+#define HRTIM_ADC1R_AD1EEV5_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos)       /*!< 0x00000200 */

+#define HRTIM_ADC1R_AD1EEV5           HRTIM_ADC1R_AD1EEV5_Msk                  /*!< ADC Trigger 1 on external event 5 */

+#define HRTIM_ADC1R_AD1TAC2_Pos       (10U)

+#define HRTIM_ADC1R_AD1TAC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC1R_AD1TAC2           HRTIM_ADC1R_AD1TAC2_Msk                  /*!< ADC Trigger 1 on Timer A compare 2 */

+#define HRTIM_ADC1R_AD1TAC3_Pos       (11U)

+#define HRTIM_ADC1R_AD1TAC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC1R_AD1TAC3           HRTIM_ADC1R_AD1TAC3_Msk                  /*!< ADC Trigger 1 on Timer A compare 3 */

+#define HRTIM_ADC1R_AD1TAC4_Pos       (12U)

+#define HRTIM_ADC1R_AD1TAC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC1R_AD1TAC4           HRTIM_ADC1R_AD1TAC4_Msk                  /*!< ADC Trigger 1 on Timer A compare 4 */

+#define HRTIM_ADC1R_AD1TAPER_Pos      (13U)

+#define HRTIM_ADC1R_AD1TAPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC1R_AD1TAPER          HRTIM_ADC1R_AD1TAPER_Msk                 /*!< ADC Trigger 1 on Timer A period */

+#define HRTIM_ADC1R_AD1TARST_Pos      (14U)

+#define HRTIM_ADC1R_AD1TARST_Msk      (0x1UL << HRTIM_ADC1R_AD1TARST_Pos)      /*!< 0x00004000 */

+#define HRTIM_ADC1R_AD1TARST          HRTIM_ADC1R_AD1TARST_Msk                 /*!< ADC Trigger 1 on Timer A reset */

+#define HRTIM_ADC1R_AD1TBC2_Pos       (15U)

+#define HRTIM_ADC1R_AD1TBC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC2_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC1R_AD1TBC2           HRTIM_ADC1R_AD1TBC2_Msk                  /*!< ADC Trigger 1 on Timer B compare 2 */

+#define HRTIM_ADC1R_AD1TBC3_Pos       (16U)

+#define HRTIM_ADC1R_AD1TBC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC1R_AD1TBC3           HRTIM_ADC1R_AD1TBC3_Msk                  /*!< ADC Trigger 1 on Timer B compare 3 */

+#define HRTIM_ADC1R_AD1TBC4_Pos       (17U)

+#define HRTIM_ADC1R_AD1TBC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos)       /*!< 0x00020000 */

+#define HRTIM_ADC1R_AD1TBC4           HRTIM_ADC1R_AD1TBC4_Msk                  /*!< ADC Trigger 1 on Timer B compare 4 */

+#define HRTIM_ADC1R_AD1TBPER_Pos      (18U)

+#define HRTIM_ADC1R_AD1TBPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos)      /*!< 0x00040000 */

+#define HRTIM_ADC1R_AD1TBPER          HRTIM_ADC1R_AD1TBPER_Msk                 /*!< ADC Trigger 1 on Timer B period */

+#define HRTIM_ADC1R_AD1TBRST_Pos      (19U)

+#define HRTIM_ADC1R_AD1TBRST_Msk      (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos)      /*!< 0x00080000 */

+#define HRTIM_ADC1R_AD1TBRST          HRTIM_ADC1R_AD1TBRST_Msk                 /*!< ADC Trigger 1 on Timer B reset */

+#define HRTIM_ADC1R_AD1TCC2_Pos       (20U)

+#define HRTIM_ADC1R_AD1TCC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC2_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC1R_AD1TCC2           HRTIM_ADC1R_AD1TCC2_Msk                  /*!< ADC Trigger 1 on Timer C compare 2 */

+#define HRTIM_ADC1R_AD1TCC3_Pos       (21U)

+#define HRTIM_ADC1R_AD1TCC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos)       /*!< 0x00200000 */

+#define HRTIM_ADC1R_AD1TCC3           HRTIM_ADC1R_AD1TCC3_Msk                  /*!< ADC Trigger 1 on Timer C compare 3 */

+#define HRTIM_ADC1R_AD1TCC4_Pos       (22U)

+#define HRTIM_ADC1R_AD1TCC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos)       /*!< 0x00400000 */

+#define HRTIM_ADC1R_AD1TCC4           HRTIM_ADC1R_AD1TCC4_Msk                  /*!< ADC Trigger 1 on Timer C compare 4 */

+#define HRTIM_ADC1R_AD1TCPER_Pos      (23U)

+#define HRTIM_ADC1R_AD1TCPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos)      /*!< 0x00800000 */

+#define HRTIM_ADC1R_AD1TCPER          HRTIM_ADC1R_AD1TCPER_Msk                 /*!< ADC Trigger 1 on Timer C period */

+#define HRTIM_ADC1R_AD1TDC2_Pos       (24U)

+#define HRTIM_ADC1R_AD1TDC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC2_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC1R_AD1TDC2           HRTIM_ADC1R_AD1TDC2_Msk                  /*!< ADC Trigger 1 on Timer D compare 2 */

+#define HRTIM_ADC1R_AD1TDC3_Pos       (25U)

+#define HRTIM_ADC1R_AD1TDC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC1R_AD1TDC3           HRTIM_ADC1R_AD1TDC3_Msk                  /*!< ADC Trigger 1 on Timer D compare 3 */

+#define HRTIM_ADC1R_AD1TDC4_Pos       (26U)

+#define HRTIM_ADC1R_AD1TDC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos)       /*!< 0x04000000 */

+#define HRTIM_ADC1R_AD1TDC4           HRTIM_ADC1R_AD1TDC4_Msk                  /*!< ADC Trigger 1 on Timer D compare 4 */

+#define HRTIM_ADC1R_AD1TDPER_Pos      (27U)

+#define HRTIM_ADC1R_AD1TDPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC1R_AD1TDPER          HRTIM_ADC1R_AD1TDPER_Msk                 /*!< ADC Trigger 1 on Timer D period */

+#define HRTIM_ADC1R_AD1TEC2_Pos       (28U)

+#define HRTIM_ADC1R_AD1TEC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC1R_AD1TEC2           HRTIM_ADC1R_AD1TEC2_Msk                  /*!< ADC Trigger 1 on Timer E compare 2 */

+#define HRTIM_ADC1R_AD1TEC3_Pos       (29U)

+#define HRTIM_ADC1R_AD1TEC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC1R_AD1TEC3           HRTIM_ADC1R_AD1TEC3_Msk                  /*!< ADC Trigger 1 on Timer E compare 3 */

+#define HRTIM_ADC1R_AD1TEC4_Pos       (30U)

+#define HRTIM_ADC1R_AD1TEC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC1R_AD1TEC4           HRTIM_ADC1R_AD1TEC4_Msk                  /*!< ADC Trigger 1 on Timer E compare 4 */

+#define HRTIM_ADC1R_AD1TEPER_Pos      (31U)

+#define HRTIM_ADC1R_AD1TEPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC1R_AD1TEPER          HRTIM_ADC1R_AD1TEPER_Msk                 /*!< ADC Trigger 1 on Timer E period */

+

+/*******************  Bit definition for HRTIM_ADC2R register  ****************/

+#define HRTIM_ADC2R_AD2MC1_Pos        (0U)

+#define HRTIM_ADC2R_AD2MC1_Msk        (0x1UL << HRTIM_ADC2R_AD2MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC2R_AD2MC1            HRTIM_ADC2R_AD2MC1_Msk                   /*!< ADC Trigger 2 on master compare 1 */

+#define HRTIM_ADC2R_AD2MC2_Pos        (1U)

+#define HRTIM_ADC2R_AD2MC2_Msk        (0x1UL << HRTIM_ADC2R_AD2MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC2R_AD2MC2            HRTIM_ADC2R_AD2MC2_Msk                   /*!< ADC Trigger 2 on master compare 2 */

+#define HRTIM_ADC2R_AD2MC3_Pos        (2U)

+#define HRTIM_ADC2R_AD2MC3_Msk        (0x1UL << HRTIM_ADC2R_AD2MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC2R_AD2MC3            HRTIM_ADC2R_AD2MC3_Msk                   /*!< ADC Trigger 2 on master compare 3 */

+#define HRTIM_ADC2R_AD2MC4_Pos        (3U)

+#define HRTIM_ADC2R_AD2MC4_Msk        (0x1UL << HRTIM_ADC2R_AD2MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC2R_AD2MC4            HRTIM_ADC2R_AD2MC4_Msk                   /*!< ADC Trigger 2 on master compare 4 */

+#define HRTIM_ADC2R_AD2MPER_Pos       (4U)

+#define HRTIM_ADC2R_AD2MPER_Msk       (0x1UL << HRTIM_ADC2R_AD2MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC2R_AD2MPER           HRTIM_ADC2R_AD2MPER_Msk                  /*!< ADC Trigger 2 on master period */

+#define HRTIM_ADC2R_AD2EEV6_Pos       (5U)

+#define HRTIM_ADC2R_AD2EEV6_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC2R_AD2EEV6           HRTIM_ADC2R_AD2EEV6_Msk                  /*!< ADC Trigger 2 on external event 6 */

+#define HRTIM_ADC2R_AD2EEV7_Pos       (6U)

+#define HRTIM_ADC2R_AD2EEV7_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC2R_AD2EEV7           HRTIM_ADC2R_AD2EEV7_Msk                  /*!< ADC Trigger 2 on external event 7 */

+#define HRTIM_ADC2R_AD2EEV8_Pos       (7U)

+#define HRTIM_ADC2R_AD2EEV8_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC2R_AD2EEV8           HRTIM_ADC2R_AD2EEV8_Msk                  /*!< ADC Trigger 2 on external event 8 */

+#define HRTIM_ADC2R_AD2EEV9_Pos       (8U)

+#define HRTIM_ADC2R_AD2EEV9_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC2R_AD2EEV9           HRTIM_ADC2R_AD2EEV9_Msk                  /*!< ADC Trigger 2 on external event 9 */

+#define HRTIM_ADC2R_AD2EEV10_Pos      (9U)

+#define HRTIM_ADC2R_AD2EEV10_Msk      (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos)      /*!< 0x00000200 */

+#define HRTIM_ADC2R_AD2EEV10          HRTIM_ADC2R_AD2EEV10_Msk                 /*!< ADC Trigger 2 on external event 10 */

+#define HRTIM_ADC2R_AD2TAC2_Pos       (10U)

+#define HRTIM_ADC2R_AD2TAC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC2R_AD2TAC2           HRTIM_ADC2R_AD2TAC2_Msk                  /*!< ADC Trigger 2 on Timer A compare 2 */

+#define HRTIM_ADC2R_AD2TAC3_Pos       (11U)

+#define HRTIM_ADC2R_AD2TAC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC2R_AD2TAC3           HRTIM_ADC2R_AD2TAC3_Msk                  /*!< ADC Trigger 2 on Timer A compare 3 */

+#define HRTIM_ADC2R_AD2TAC4_Pos       (12U)

+#define HRTIM_ADC2R_AD2TAC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC2R_AD2TAC4           HRTIM_ADC2R_AD2TAC4_Msk                  /*!< ADC Trigger 2 on Timer A compare 4*/

+#define HRTIM_ADC2R_AD2TAPER_Pos      (13U)

+#define HRTIM_ADC2R_AD2TAPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC2R_AD2TAPER          HRTIM_ADC2R_AD2TAPER_Msk                 /*!< ADC Trigger 2 on Timer A period */

+#define HRTIM_ADC2R_AD2TBC2_Pos       (14U)

+#define HRTIM_ADC2R_AD2TBC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos)       /*!< 0x00004000 */

+#define HRTIM_ADC2R_AD2TBC2           HRTIM_ADC2R_AD2TBC2_Msk                  /*!< ADC Trigger 2 on Timer B compare 2 */

+#define HRTIM_ADC2R_AD2TBC3_Pos       (15U)

+#define HRTIM_ADC2R_AD2TBC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC3_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC2R_AD2TBC3           HRTIM_ADC2R_AD2TBC3_Msk                  /*!< ADC Trigger 2 on Timer B compare 3 */

+#define HRTIM_ADC2R_AD2TBC4_Pos       (16U)

+#define HRTIM_ADC2R_AD2TBC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC2R_AD2TBC4           HRTIM_ADC2R_AD2TBC4_Msk                  /*!< ADC Trigger 2 on Timer B compare 4 */

+#define HRTIM_ADC2R_AD2TBPER_Pos      (17U)

+#define HRTIM_ADC2R_AD2TBPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos)      /*!< 0x00020000 */

+#define HRTIM_ADC2R_AD2TBPER          HRTIM_ADC2R_AD2TBPER_Msk                 /*!< ADC Trigger 2 on Timer B period */

+#define HRTIM_ADC2R_AD2TCC2_Pos       (18U)

+#define HRTIM_ADC2R_AD2TCC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos)       /*!< 0x00040000 */

+#define HRTIM_ADC2R_AD2TCC2           HRTIM_ADC2R_AD2TCC2_Msk                  /*!< ADC Trigger 2 on Timer C compare 2 */

+#define HRTIM_ADC2R_AD2TCC3_Pos       (19U)

+#define HRTIM_ADC2R_AD2TCC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC3_Pos)       /*!< 0x00080000 */

+#define HRTIM_ADC2R_AD2TCC3           HRTIM_ADC2R_AD2TCC3_Msk                  /*!< ADC Trigger 2 on Timer C compare 3 */

+#define HRTIM_ADC2R_AD2TCC4_Pos       (20U)

+#define HRTIM_ADC2R_AD2TCC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC2R_AD2TCC4           HRTIM_ADC2R_AD2TCC4_Msk                  /*!< ADC Trigger 2 on Timer C compare 4 */

+#define HRTIM_ADC2R_AD2TCPER_Pos      (21U)

+#define HRTIM_ADC2R_AD2TCPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos)      /*!< 0x00200000 */

+#define HRTIM_ADC2R_AD2TCPER          HRTIM_ADC2R_AD2TCPER_Msk                 /*!< ADC Trigger 2 on Timer C period */

+#define HRTIM_ADC2R_AD2TCRST_Pos      (22U)

+#define HRTIM_ADC2R_AD2TCRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos)      /*!< 0x00400000 */

+#define HRTIM_ADC2R_AD2TCRST          HRTIM_ADC2R_AD2TCRST_Msk                 /*!< ADC Trigger 2 on Timer C reset */

+#define HRTIM_ADC2R_AD2TDC2_Pos       (23U)

+#define HRTIM_ADC2R_AD2TDC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos)       /*!< 0x00800000 */

+#define HRTIM_ADC2R_AD2TDC2           HRTIM_ADC2R_AD2TDC2_Msk                  /*!< ADC Trigger 2 on Timer D compare 2 */

+#define HRTIM_ADC2R_AD2TDC3_Pos       (24U)

+#define HRTIM_ADC2R_AD2TDC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC3_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC2R_AD2TDC3           HRTIM_ADC2R_AD2TDC3_Msk                  /*!< ADC Trigger 2 on Timer D compare 3 */

+#define HRTIM_ADC2R_AD2TDC4_Pos       (25U)

+#define HRTIM_ADC2R_AD2TDC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC2R_AD2TDC4           HRTIM_ADC2R_AD2TDC4_Msk                  /*!< ADC Trigger 2 on Timer D compare 4*/

+#define HRTIM_ADC2R_AD2TDPER_Pos      (26U)

+#define HRTIM_ADC2R_AD2TDPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos)      /*!< 0x04000000 */

+#define HRTIM_ADC2R_AD2TDPER          HRTIM_ADC2R_AD2TDPER_Msk                 /*!< ADC Trigger 2 on Timer D period */

+#define HRTIM_ADC2R_AD2TDRST_Pos      (27U)

+#define HRTIM_ADC2R_AD2TDRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC2R_AD2TDRST          HRTIM_ADC2R_AD2TDRST_Msk                 /*!< ADC Trigger 2 on Timer D reset */

+#define HRTIM_ADC2R_AD2TEC2_Pos       (28U)

+#define HRTIM_ADC2R_AD2TEC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC2R_AD2TEC2           HRTIM_ADC2R_AD2TEC2_Msk                  /*!< ADC Trigger 2 on Timer E compare 2 */

+#define HRTIM_ADC2R_AD2TEC3_Pos       (29U)

+#define HRTIM_ADC2R_AD2TEC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC2R_AD2TEC3           HRTIM_ADC2R_AD2TEC3_Msk                  /*!< ADC Trigger 2 on Timer E compare 3 */

+#define HRTIM_ADC2R_AD2TEC4_Pos       (30U)

+#define HRTIM_ADC2R_AD2TEC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC2R_AD2TEC4           HRTIM_ADC2R_AD2TEC4_Msk                  /*!< ADC Trigger 2 on Timer E compare 4 */

+#define HRTIM_ADC2R_AD2TERST_Pos      (31U)

+#define HRTIM_ADC2R_AD2TERST_Msk      (0x1UL << HRTIM_ADC2R_AD2TERST_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC2R_AD2TERST          HRTIM_ADC2R_AD2TERST_Msk                 /*!< ADC Trigger 2 on Timer E reset */

+

+/*******************  Bit definition for HRTIM_ADC3R register  ****************/

+#define HRTIM_ADC3R_AD3MC1_Pos        (0U)

+#define HRTIM_ADC3R_AD3MC1_Msk        (0x1UL << HRTIM_ADC3R_AD3MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC3R_AD3MC1            HRTIM_ADC3R_AD3MC1_Msk                   /*!< ADC Trigger 3 on master compare 1 */

+#define HRTIM_ADC3R_AD3MC2_Pos        (1U)

+#define HRTIM_ADC3R_AD3MC2_Msk        (0x1UL << HRTIM_ADC3R_AD3MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC3R_AD3MC2            HRTIM_ADC3R_AD3MC2_Msk                   /*!< ADC Trigger 3 on master compare 2 */

+#define HRTIM_ADC3R_AD3MC3_Pos        (2U)

+#define HRTIM_ADC3R_AD3MC3_Msk        (0x1UL << HRTIM_ADC3R_AD3MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC3R_AD3MC3            HRTIM_ADC3R_AD3MC3_Msk                   /*!< ADC Trigger 3 on master compare 3 */

+#define HRTIM_ADC3R_AD3MC4_Pos        (3U)

+#define HRTIM_ADC3R_AD3MC4_Msk        (0x1UL << HRTIM_ADC3R_AD3MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC3R_AD3MC4            HRTIM_ADC3R_AD3MC4_Msk                   /*!< ADC Trigger 3 on master compare 4 */

+#define HRTIM_ADC3R_AD3MPER_Pos       (4U)

+#define HRTIM_ADC3R_AD3MPER_Msk       (0x1UL << HRTIM_ADC3R_AD3MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC3R_AD3MPER           HRTIM_ADC3R_AD3MPER_Msk                  /*!< ADC Trigger 3 on master period */

+#define HRTIM_ADC3R_AD3EEV1_Pos       (5U)

+#define HRTIM_ADC3R_AD3EEV1_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC3R_AD3EEV1           HRTIM_ADC3R_AD3EEV1_Msk                  /*!< ADC Trigger 3 on external event 1 */

+#define HRTIM_ADC3R_AD3EEV2_Pos       (6U)

+#define HRTIM_ADC3R_AD3EEV2_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC3R_AD3EEV2           HRTIM_ADC3R_AD3EEV2_Msk                  /*!< ADC Trigger 3 on external event 2 */

+#define HRTIM_ADC3R_AD3EEV3_Pos       (7U)

+#define HRTIM_ADC3R_AD3EEV3_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC3R_AD3EEV3           HRTIM_ADC3R_AD3EEV3_Msk                  /*!< ADC Trigger 3 on external event 3 */

+#define HRTIM_ADC3R_AD3EEV4_Pos       (8U)

+#define HRTIM_ADC3R_AD3EEV4_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC3R_AD3EEV4           HRTIM_ADC3R_AD3EEV4_Msk                  /*!< ADC Trigger 3 on external event 4 */

+#define HRTIM_ADC3R_AD3EEV5_Pos       (9U)

+#define HRTIM_ADC3R_AD3EEV5_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos)       /*!< 0x00000200 */

+#define HRTIM_ADC3R_AD3EEV5           HRTIM_ADC3R_AD3EEV5_Msk                  /*!< ADC Trigger 3 on external event 5 */

+#define HRTIM_ADC3R_AD3TAC2_Pos       (10U)

+#define HRTIM_ADC3R_AD3TAC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC3R_AD3TAC2           HRTIM_ADC3R_AD3TAC2_Msk                  /*!< ADC Trigger 3 on Timer A compare 2 */

+#define HRTIM_ADC3R_AD3TAC3_Pos       (11U)

+#define HRTIM_ADC3R_AD3TAC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC3R_AD3TAC3           HRTIM_ADC3R_AD3TAC3_Msk                  /*!< ADC Trigger 3 on Timer A compare 3 */

+#define HRTIM_ADC3R_AD3TAC4_Pos       (12U)

+#define HRTIM_ADC3R_AD3TAC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC3R_AD3TAC4           HRTIM_ADC3R_AD3TAC4_Msk                  /*!< ADC Trigger 3 on Timer A compare 4 */

+#define HRTIM_ADC3R_AD3TAPER_Pos      (13U)

+#define HRTIM_ADC3R_AD3TAPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC3R_AD3TAPER          HRTIM_ADC3R_AD3TAPER_Msk                 /*!< ADC Trigger 3 on Timer A period */

+#define HRTIM_ADC3R_AD3TARST_Pos      (14U)

+#define HRTIM_ADC3R_AD3TARST_Msk      (0x1UL << HRTIM_ADC3R_AD3TARST_Pos)      /*!< 0x00004000 */

+#define HRTIM_ADC3R_AD3TARST          HRTIM_ADC3R_AD3TARST_Msk                 /*!< ADC Trigger 3 on Timer A reset */

+#define HRTIM_ADC3R_AD3TBC2_Pos       (15U)

+#define HRTIM_ADC3R_AD3TBC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC2_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC3R_AD3TBC2           HRTIM_ADC3R_AD3TBC2_Msk                  /*!< ADC Trigger 3 on Timer B compare 2 */

+#define HRTIM_ADC3R_AD3TBC3_Pos       (16U)

+#define HRTIM_ADC3R_AD3TBC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC3R_AD3TBC3           HRTIM_ADC3R_AD3TBC3_Msk                  /*!< ADC Trigger 3 on Timer B compare 3 */

+#define HRTIM_ADC3R_AD3TBC4_Pos       (17U)

+#define HRTIM_ADC3R_AD3TBC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos)       /*!< 0x00020000 */

+#define HRTIM_ADC3R_AD3TBC4           HRTIM_ADC3R_AD3TBC4_Msk                  /*!< ADC Trigger 3 on Timer B compare 4 */

+#define HRTIM_ADC3R_AD3TBPER_Pos      (18U)

+#define HRTIM_ADC3R_AD3TBPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos)      /*!< 0x00040000 */

+#define HRTIM_ADC3R_AD3TBPER          HRTIM_ADC3R_AD3TBPER_Msk                 /*!< ADC Trigger 3 on Timer B period */

+#define HRTIM_ADC3R_AD3TBRST_Pos      (19U)

+#define HRTIM_ADC3R_AD3TBRST_Msk      (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos)      /*!< 0x00080000 */

+#define HRTIM_ADC3R_AD3TBRST          HRTIM_ADC3R_AD3TBRST_Msk                 /*!< ADC Trigger 3 on Timer B reset */

+#define HRTIM_ADC3R_AD3TCC2_Pos       (20U)

+#define HRTIM_ADC3R_AD3TCC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC2_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC3R_AD3TCC2           HRTIM_ADC3R_AD3TCC2_Msk                  /*!< ADC Trigger 3 on Timer C compare 2 */

+#define HRTIM_ADC3R_AD3TCC3_Pos       (21U)

+#define HRTIM_ADC3R_AD3TCC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos)       /*!< 0x00200000 */

+#define HRTIM_ADC3R_AD3TCC3           HRTIM_ADC3R_AD3TCC3_Msk                  /*!< ADC Trigger 3 on Timer C compare 3 */

+#define HRTIM_ADC3R_AD3TCC4_Pos       (22U)

+#define HRTIM_ADC3R_AD3TCC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos)       /*!< 0x00400000 */

+#define HRTIM_ADC3R_AD3TCC4           HRTIM_ADC3R_AD3TCC4_Msk                  /*!< ADC Trigger 3 on Timer C compare 4 */

+#define HRTIM_ADC3R_AD3TCPER_Pos      (23U)

+#define HRTIM_ADC3R_AD3TCPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos)      /*!< 0x00800000 */

+#define HRTIM_ADC3R_AD3TCPER          HRTIM_ADC3R_AD3TCPER_Msk                 /*!< ADC Trigger 3 on Timer C period */

+#define HRTIM_ADC3R_AD3TDC2_Pos       (24U)

+#define HRTIM_ADC3R_AD3TDC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC2_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC3R_AD3TDC2           HRTIM_ADC3R_AD3TDC2_Msk                  /*!< ADC Trigger 3 on Timer D compare 2 */

+#define HRTIM_ADC3R_AD3TDC3_Pos       (25U)

+#define HRTIM_ADC3R_AD3TDC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC3R_AD3TDC3           HRTIM_ADC3R_AD3TDC3_Msk                  /*!< ADC Trigger 3 on Timer D compare 3 */

+#define HRTIM_ADC3R_AD3TDC4_Pos       (26U)

+#define HRTIM_ADC3R_AD3TDC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos)       /*!< 0x04000000 */

+#define HRTIM_ADC3R_AD3TDC4           HRTIM_ADC3R_AD3TDC4_Msk                  /*!< ADC Trigger 3 on Timer D compare 4 */

+#define HRTIM_ADC3R_AD3TDPER_Pos      (27U)

+#define HRTIM_ADC3R_AD3TDPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC3R_AD3TDPER          HRTIM_ADC3R_AD3TDPER_Msk                 /*!< ADC Trigger 3 on Timer D period */

+#define HRTIM_ADC3R_AD3TEC2_Pos       (28U)

+#define HRTIM_ADC3R_AD3TEC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC3R_AD3TEC2           HRTIM_ADC3R_AD3TEC2_Msk                  /*!< ADC Trigger 3 on Timer E compare 2 */

+#define HRTIM_ADC3R_AD3TEC3_Pos       (29U)

+#define HRTIM_ADC3R_AD3TEC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC3R_AD3TEC3           HRTIM_ADC3R_AD3TEC3_Msk                  /*!< ADC Trigger 3 on Timer E compare 3 */

+#define HRTIM_ADC3R_AD3TEC4_Pos       (30U)

+#define HRTIM_ADC3R_AD3TEC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC3R_AD3TEC4           HRTIM_ADC3R_AD3TEC4_Msk                  /*!< ADC Trigger 3 on Timer E compare 4 */

+#define HRTIM_ADC3R_AD3TEPER_Pos      (31U)

+#define HRTIM_ADC3R_AD3TEPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC3R_AD3TEPER          HRTIM_ADC3R_AD3TEPER_Msk                 /*!< ADC Trigger 3 on Timer E period */

+

+/*******************  Bit definition for HRTIM_ADC4R register  ****************/

+#define HRTIM_ADC4R_AD4MC1_Pos        (0U)

+#define HRTIM_ADC4R_AD4MC1_Msk        (0x1UL << HRTIM_ADC4R_AD4MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC4R_AD4MC1            HRTIM_ADC4R_AD4MC1_Msk                   /*!< ADC Trigger 4 on master compare 1 */

+#define HRTIM_ADC4R_AD4MC2_Pos        (1U)

+#define HRTIM_ADC4R_AD4MC2_Msk        (0x1UL << HRTIM_ADC4R_AD4MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC4R_AD4MC2            HRTIM_ADC4R_AD4MC2_Msk                   /*!< ADC Trigger 4 on master compare 2 */

+#define HRTIM_ADC4R_AD4MC3_Pos        (2U)

+#define HRTIM_ADC4R_AD4MC3_Msk        (0x1UL << HRTIM_ADC4R_AD4MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC4R_AD4MC3            HRTIM_ADC4R_AD4MC3_Msk                   /*!< ADC Trigger 4 on master compare 3 */

+#define HRTIM_ADC4R_AD4MC4_Pos        (3U)

+#define HRTIM_ADC4R_AD4MC4_Msk        (0x1UL << HRTIM_ADC4R_AD4MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC4R_AD4MC4            HRTIM_ADC4R_AD4MC4_Msk                   /*!< ADC Trigger 4 on master compare 4 */

+#define HRTIM_ADC4R_AD4MPER_Pos       (4U)

+#define HRTIM_ADC4R_AD4MPER_Msk       (0x1UL << HRTIM_ADC4R_AD4MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC4R_AD4MPER           HRTIM_ADC4R_AD4MPER_Msk                  /*!< ADC Trigger 4 on master period */

+#define HRTIM_ADC4R_AD4EEV6_Pos       (5U)

+#define HRTIM_ADC4R_AD4EEV6_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC4R_AD4EEV6           HRTIM_ADC4R_AD4EEV6_Msk                  /*!< ADC Trigger 4 on external event 6 */

+#define HRTIM_ADC4R_AD4EEV7_Pos       (6U)

+#define HRTIM_ADC4R_AD4EEV7_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC4R_AD4EEV7           HRTIM_ADC4R_AD4EEV7_Msk                  /*!< ADC Trigger 4 on external event 7 */

+#define HRTIM_ADC4R_AD4EEV8_Pos       (7U)

+#define HRTIM_ADC4R_AD4EEV8_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC4R_AD4EEV8           HRTIM_ADC4R_AD4EEV8_Msk                  /*!< ADC Trigger 4 on external event 8 */

+#define HRTIM_ADC4R_AD4EEV9_Pos       (8U)

+#define HRTIM_ADC4R_AD4EEV9_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC4R_AD4EEV9           HRTIM_ADC4R_AD4EEV9_Msk                  /*!< ADC Trigger 4 on external event 9 */

+#define HRTIM_ADC4R_AD4EEV10_Pos      (9U)

+#define HRTIM_ADC4R_AD4EEV10_Msk      (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos)      /*!< 0x00000200 */

+#define HRTIM_ADC4R_AD4EEV10          HRTIM_ADC4R_AD4EEV10_Msk                 /*!< ADC Trigger 4 on external event 10 */

+#define HRTIM_ADC4R_AD4TAC2_Pos       (10U)

+#define HRTIM_ADC4R_AD4TAC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC4R_AD4TAC2           HRTIM_ADC4R_AD4TAC2_Msk                  /*!< ADC Trigger 4 on Timer A compare 2 */

+#define HRTIM_ADC4R_AD4TAC3_Pos       (11U)

+#define HRTIM_ADC4R_AD4TAC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC4R_AD4TAC3           HRTIM_ADC4R_AD4TAC3_Msk                  /*!< ADC Trigger 4 on Timer A compare 3 */

+#define HRTIM_ADC4R_AD4TAC4_Pos       (12U)

+#define HRTIM_ADC4R_AD4TAC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC4R_AD4TAC4           HRTIM_ADC4R_AD4TAC4_Msk                  /*!< ADC Trigger 4 on Timer A compare 4*/

+#define HRTIM_ADC4R_AD4TAPER_Pos      (13U)

+#define HRTIM_ADC4R_AD4TAPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC4R_AD4TAPER          HRTIM_ADC4R_AD4TAPER_Msk                 /*!< ADC Trigger 4 on Timer A period */

+#define HRTIM_ADC4R_AD4TBC2_Pos       (14U)

+#define HRTIM_ADC4R_AD4TBC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos)       /*!< 0x00004000 */

+#define HRTIM_ADC4R_AD4TBC2           HRTIM_ADC4R_AD4TBC2_Msk                  /*!< ADC Trigger 4 on Timer B compare 2 */

+#define HRTIM_ADC4R_AD4TBC3_Pos       (15U)

+#define HRTIM_ADC4R_AD4TBC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC3_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC4R_AD4TBC3           HRTIM_ADC4R_AD4TBC3_Msk                  /*!< ADC Trigger 4 on Timer B compare 3 */

+#define HRTIM_ADC4R_AD4TBC4_Pos       (16U)

+#define HRTIM_ADC4R_AD4TBC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC4R_AD4TBC4           HRTIM_ADC4R_AD4TBC4_Msk                  /*!< ADC Trigger 4 on Timer B compare 4 */

+#define HRTIM_ADC4R_AD4TBPER_Pos      (17U)

+#define HRTIM_ADC4R_AD4TBPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos)      /*!< 0x00020000 */

+#define HRTIM_ADC4R_AD4TBPER          HRTIM_ADC4R_AD4TBPER_Msk                 /*!< ADC Trigger 4 on Timer B period */

+#define HRTIM_ADC4R_AD4TCC2_Pos       (18U)

+#define HRTIM_ADC4R_AD4TCC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos)       /*!< 0x00040000 */

+#define HRTIM_ADC4R_AD4TCC2           HRTIM_ADC4R_AD4TCC2_Msk                  /*!< ADC Trigger 4 on Timer C compare 2 */

+#define HRTIM_ADC4R_AD4TCC3_Pos       (19U)

+#define HRTIM_ADC4R_AD4TCC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC3_Pos)       /*!< 0x00080000 */

+#define HRTIM_ADC4R_AD4TCC3           HRTIM_ADC4R_AD4TCC3_Msk                  /*!< ADC Trigger 4 on Timer C compare 3 */

+#define HRTIM_ADC4R_AD4TCC4_Pos       (20U)

+#define HRTIM_ADC4R_AD4TCC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC4R_AD4TCC4           HRTIM_ADC4R_AD4TCC4_Msk                  /*!< ADC Trigger 4 on Timer C compare 4 */

+#define HRTIM_ADC4R_AD4TCPER_Pos      (21U)

+#define HRTIM_ADC4R_AD4TCPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos)      /*!< 0x00200000 */

+#define HRTIM_ADC4R_AD4TCPER          HRTIM_ADC4R_AD4TCPER_Msk                 /*!< ADC Trigger 4 on Timer C period */

+#define HRTIM_ADC4R_AD4TCRST_Pos      (22U)

+#define HRTIM_ADC4R_AD4TCRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos)      /*!< 0x00400000 */

+#define HRTIM_ADC4R_AD4TCRST          HRTIM_ADC4R_AD4TCRST_Msk                 /*!< ADC Trigger 4 on Timer C reset */

+#define HRTIM_ADC4R_AD4TDC2_Pos       (23U)

+#define HRTIM_ADC4R_AD4TDC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos)       /*!< 0x00800000 */

+#define HRTIM_ADC4R_AD4TDC2           HRTIM_ADC4R_AD4TDC2_Msk                  /*!< ADC Trigger 4 on Timer D compare 2 */

+#define HRTIM_ADC4R_AD4TDC3_Pos       (24U)

+#define HRTIM_ADC4R_AD4TDC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC3_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC4R_AD4TDC3           HRTIM_ADC4R_AD4TDC3_Msk                  /*!< ADC Trigger 4 on Timer D compare 3 */

+#define HRTIM_ADC4R_AD4TDC4_Pos       (25U)

+#define HRTIM_ADC4R_AD4TDC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC4R_AD4TDC4           HRTIM_ADC4R_AD4TDC4_Msk                  /*!< ADC Trigger 4 on Timer D compare 4*/

+#define HRTIM_ADC4R_AD4TDPER_Pos      (26U)

+#define HRTIM_ADC4R_AD4TDPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos)      /*!< 0x04000000 */

+#define HRTIM_ADC4R_AD4TDPER          HRTIM_ADC4R_AD4TDPER_Msk                 /*!< ADC Trigger 4 on Timer D period */

+#define HRTIM_ADC4R_AD4TDRST_Pos      (27U)

+#define HRTIM_ADC4R_AD4TDRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC4R_AD4TDRST          HRTIM_ADC4R_AD4TDRST_Msk                 /*!< ADC Trigger 4 on Timer D reset */

+#define HRTIM_ADC4R_AD4TEC2_Pos       (28U)

+#define HRTIM_ADC4R_AD4TEC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC4R_AD4TEC2           HRTIM_ADC4R_AD4TEC2_Msk                  /*!< ADC Trigger 4 on Timer E compare 2 */

+#define HRTIM_ADC4R_AD4TEC3_Pos       (29U)

+#define HRTIM_ADC4R_AD4TEC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC4R_AD4TEC3           HRTIM_ADC4R_AD4TEC3_Msk                  /*!< ADC Trigger 4 on Timer E compare 3 */

+#define HRTIM_ADC4R_AD4TEC4_Pos       (30U)

+#define HRTIM_ADC4R_AD4TEC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC4R_AD4TEC4           HRTIM_ADC4R_AD4TEC4_Msk                  /*!< ADC Trigger 4 on Timer E compare 4 */

+#define HRTIM_ADC4R_AD4TERST_Pos      (31U)

+#define HRTIM_ADC4R_AD4TERST_Msk      (0x1UL << HRTIM_ADC4R_AD4TERST_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC4R_AD4TERST          HRTIM_ADC4R_AD4TERST_Msk                 /*!< ADC Trigger 4 on Timer E reset */

+

+/*******************  Bit definition for HRTIM_FLTINR1 register  ***************/

+#define HRTIM_FLTINR1_FLT1E_Pos       (0U)

+#define HRTIM_FLTINR1_FLT1E_Msk       (0x1UL << HRTIM_FLTINR1_FLT1E_Pos)       /*!< 0x00000001 */

+#define HRTIM_FLTINR1_FLT1E           HRTIM_FLTINR1_FLT1E_Msk                  /*!< Fault 1 enable */

+#define HRTIM_FLTINR1_FLT1P_Pos       (1U)

+#define HRTIM_FLTINR1_FLT1P_Msk       (0x1UL << HRTIM_FLTINR1_FLT1P_Pos)       /*!< 0x00000002 */

+#define HRTIM_FLTINR1_FLT1P           HRTIM_FLTINR1_FLT1P_Msk                  /*!< Fault 1 polarity */

+#define HRTIM_FLTINR1_FLT1SRC_Pos     (2U)

+#define HRTIM_FLTINR1_FLT1SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT1SRC_Pos)     /*!< 0x00000004 */

+#define HRTIM_FLTINR1_FLT1SRC         HRTIM_FLTINR1_FLT1SRC_Msk                /*!< Fault 1 source */

+#define HRTIM_FLTINR1_FLT1F_Pos       (3U)

+#define HRTIM_FLTINR1_FLT1F_Msk       (0xFUL << HRTIM_FLTINR1_FLT1F_Pos)       /*!< 0x00000078 */

+#define HRTIM_FLTINR1_FLT1F           HRTIM_FLTINR1_FLT1F_Msk                  /*!< Fault 1 filter */

+#define HRTIM_FLTINR1_FLT1F_0         (0x1UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000008 */

+#define HRTIM_FLTINR1_FLT1F_1         (0x2UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000010 */

+#define HRTIM_FLTINR1_FLT1F_2         (0x4UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000020 */

+#define HRTIM_FLTINR1_FLT1F_3         (0x8UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000040 */

+#define HRTIM_FLTINR1_FLT1LCK_Pos     (7U)

+#define HRTIM_FLTINR1_FLT1LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos)     /*!< 0x00000080 */

+#define HRTIM_FLTINR1_FLT1LCK         HRTIM_FLTINR1_FLT1LCK_Msk                /*!< Fault 1 lock */

+

+#define HRTIM_FLTINR1_FLT2E_Pos       (8U)

+#define HRTIM_FLTINR1_FLT2E_Msk       (0x1UL << HRTIM_FLTINR1_FLT2E_Pos)       /*!< 0x00000100 */

+#define HRTIM_FLTINR1_FLT2E           HRTIM_FLTINR1_FLT2E_Msk                  /*!< Fault 2 enable */

+#define HRTIM_FLTINR1_FLT2P_Pos       (9U)

+#define HRTIM_FLTINR1_FLT2P_Msk       (0x1UL << HRTIM_FLTINR1_FLT2P_Pos)       /*!< 0x00000200 */

+#define HRTIM_FLTINR1_FLT2P           HRTIM_FLTINR1_FLT2P_Msk                  /*!< Fault 2 polarity */

+#define HRTIM_FLTINR1_FLT2SRC_Pos     (10U)

+#define HRTIM_FLTINR1_FLT2SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT2SRC_Pos)     /*!< 0x00000400 */

+#define HRTIM_FLTINR1_FLT2SRC         HRTIM_FLTINR1_FLT2SRC_Msk                /*!< Fault 2 source */

+#define HRTIM_FLTINR1_FLT2F_Pos       (11U)

+#define HRTIM_FLTINR1_FLT2F_Msk       (0xFUL << HRTIM_FLTINR1_FLT2F_Pos)       /*!< 0x00007800 */

+#define HRTIM_FLTINR1_FLT2F           HRTIM_FLTINR1_FLT2F_Msk                  /*!< Fault 2 filter */

+#define HRTIM_FLTINR1_FLT2F_0         (0x1UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00000800 */

+#define HRTIM_FLTINR1_FLT2F_1         (0x2UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00001000 */

+#define HRTIM_FLTINR1_FLT2F_2         (0x4UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00002000 */

+#define HRTIM_FLTINR1_FLT2F_3         (0x8UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00004000 */

+#define HRTIM_FLTINR1_FLT2LCK_Pos     (15U)

+#define HRTIM_FLTINR1_FLT2LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos)     /*!< 0x00008000 */

+#define HRTIM_FLTINR1_FLT2LCK         HRTIM_FLTINR1_FLT2LCK_Msk                /*!< Fault 2 lock */

+

+#define HRTIM_FLTINR1_FLT3E_Pos       (16U)

+#define HRTIM_FLTINR1_FLT3E_Msk       (0x1UL << HRTIM_FLTINR1_FLT3E_Pos)       /*!< 0x00010000 */

+#define HRTIM_FLTINR1_FLT3E           HRTIM_FLTINR1_FLT3E_Msk                  /*!< Fault 3 enable */

+#define HRTIM_FLTINR1_FLT3P_Pos       (17U)

+#define HRTIM_FLTINR1_FLT3P_Msk       (0x1UL << HRTIM_FLTINR1_FLT3P_Pos)       /*!< 0x00020000 */

+#define HRTIM_FLTINR1_FLT3P           HRTIM_FLTINR1_FLT3P_Msk                  /*!< Fault 3 polarity */

+#define HRTIM_FLTINR1_FLT3SRC_Pos     (18U)

+#define HRTIM_FLTINR1_FLT3SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT3SRC_Pos)     /*!< 0x00040000 */

+#define HRTIM_FLTINR1_FLT3SRC         HRTIM_FLTINR1_FLT3SRC_Msk                /*!< Fault 3 source */

+#define HRTIM_FLTINR1_FLT3F_Pos       (19U)

+#define HRTIM_FLTINR1_FLT3F_Msk       (0xFUL << HRTIM_FLTINR1_FLT3F_Pos)       /*!< 0x00780000 */

+#define HRTIM_FLTINR1_FLT3F           HRTIM_FLTINR1_FLT3F_Msk                  /*!< Fault 3 filter */

+#define HRTIM_FLTINR1_FLT3F_0         (0x1UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00080000 */

+#define HRTIM_FLTINR1_FLT3F_1         (0x2UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00100000 */

+#define HRTIM_FLTINR1_FLT3F_2         (0x4UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00200000 */

+#define HRTIM_FLTINR1_FLT3F_3         (0x8UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00400000 */

+#define HRTIM_FLTINR1_FLT3LCK_Pos     (23U)

+#define HRTIM_FLTINR1_FLT3LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos)     /*!< 0x00800000 */

+#define HRTIM_FLTINR1_FLT3LCK         HRTIM_FLTINR1_FLT3LCK_Msk                /*!< Fault 3 lock */

+

+#define HRTIM_FLTINR1_FLT4E_Pos       (24U)

+#define HRTIM_FLTINR1_FLT4E_Msk       (0x1UL << HRTIM_FLTINR1_FLT4E_Pos)       /*!< 0x01000000 */

+#define HRTIM_FLTINR1_FLT4E           HRTIM_FLTINR1_FLT4E_Msk                  /*!< Fault 4 enable */

+#define HRTIM_FLTINR1_FLT4P_Pos       (25U)

+#define HRTIM_FLTINR1_FLT4P_Msk       (0x1UL << HRTIM_FLTINR1_FLT4P_Pos)       /*!< 0x02000000 */

+#define HRTIM_FLTINR1_FLT4P           HRTIM_FLTINR1_FLT4P_Msk                  /*!< Fault 4 polarity */

+#define HRTIM_FLTINR1_FLT4SRC_Pos     (26U)

+#define HRTIM_FLTINR1_FLT4SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT4SRC_Pos)     /*!< 0x04000000 */

+#define HRTIM_FLTINR1_FLT4SRC         HRTIM_FLTINR1_FLT4SRC_Msk                /*!< Fault 4 source */

+#define HRTIM_FLTINR1_FLT4F_Pos       (27U)

+#define HRTIM_FLTINR1_FLT4F_Msk       (0xFUL << HRTIM_FLTINR1_FLT4F_Pos)       /*!< 0x78000000 */

+#define HRTIM_FLTINR1_FLT4F           HRTIM_FLTINR1_FLT4F_Msk                  /*!< Fault 4 filter */

+#define HRTIM_FLTINR1_FLT4F_0         (0x1UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x08000000 */

+#define HRTIM_FLTINR1_FLT4F_1         (0x2UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x10000000 */

+#define HRTIM_FLTINR1_FLT4F_2         (0x4UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x20000000 */

+#define HRTIM_FLTINR1_FLT4F_3         (0x8UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x40000000 */

+#define HRTIM_FLTINR1_FLT4LCK_Pos     (31U)

+#define HRTIM_FLTINR1_FLT4LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos)     /*!< 0x80000000 */

+#define HRTIM_FLTINR1_FLT4LCK         HRTIM_FLTINR1_FLT4LCK_Msk                /*!< Fault 4 lock */

+

+/*******************  Bit definition for HRTIM_FLTINR2 register  ***************/

+#define HRTIM_FLTINR2_FLT5E_Pos       (0U)

+#define HRTIM_FLTINR2_FLT5E_Msk       (0x1UL << HRTIM_FLTINR2_FLT5E_Pos)       /*!< 0x00000001 */

+#define HRTIM_FLTINR2_FLT5E           HRTIM_FLTINR2_FLT5E_Msk                  /*!< Fault 5 enable */

+#define HRTIM_FLTINR2_FLT5P_Pos       (1U)

+#define HRTIM_FLTINR2_FLT5P_Msk       (0x1UL << HRTIM_FLTINR2_FLT5P_Pos)       /*!< 0x00000002 */

+#define HRTIM_FLTINR2_FLT5P           HRTIM_FLTINR2_FLT5P_Msk                  /*!< Fault 5 polarity */

+#define HRTIM_FLTINR2_FLT5SRC_Pos     (2U)

+#define HRTIM_FLTINR2_FLT5SRC_Msk     (0x1UL << HRTIM_FLTINR2_FLT5SRC_Pos)     /*!< 0x00000004 */

+#define HRTIM_FLTINR2_FLT5SRC         HRTIM_FLTINR2_FLT5SRC_Msk                /*!< Fault 5 source */

+#define HRTIM_FLTINR2_FLT5F_Pos       (3U)

+#define HRTIM_FLTINR2_FLT5F_Msk       (0xFUL << HRTIM_FLTINR2_FLT5F_Pos)       /*!< 0x00000078 */

+#define HRTIM_FLTINR2_FLT5F           HRTIM_FLTINR2_FLT5F_Msk                  /*!< Fault 5 filter */

+#define HRTIM_FLTINR2_FLT5F_0         (0x1UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000008 */

+#define HRTIM_FLTINR2_FLT5F_1         (0x2UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000010 */

+#define HRTIM_FLTINR2_FLT5F_2         (0x4UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000020 */

+#define HRTIM_FLTINR2_FLT5F_3         (0x8UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000040 */

+#define HRTIM_FLTINR2_FLT5LCK_Pos     (7U)

+#define HRTIM_FLTINR2_FLT5LCK_Msk     (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos)     /*!< 0x00000080 */

+#define HRTIM_FLTINR2_FLT5LCK         HRTIM_FLTINR2_FLT5LCK_Msk                /*!< Fault 5 lock */

+#define HRTIM_FLTINR2_FLTSD_Pos       (24U)

+#define HRTIM_FLTINR2_FLTSD_Msk       (0x3UL << HRTIM_FLTINR2_FLTSD_Pos)       /*!< 0x03000000 */

+#define HRTIM_FLTINR2_FLTSD           HRTIM_FLTINR2_FLTSD_Msk                  /*!< Fault sampling clock division */

+#define HRTIM_FLTINR2_FLTSD_0         (0x1UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x01000000 */

+#define HRTIM_FLTINR2_FLTSD_1         (0x2UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x02000000 */

+

+/*******************  Bit definition for HRTIM_BDMUPR register  ***************/

+#define HRTIM_BDMUPR_MCR_Pos          (0U)

+#define HRTIM_BDMUPR_MCR_Msk          (0x1UL << HRTIM_BDMUPR_MCR_Pos)          /*!< 0x00000001 */

+#define HRTIM_BDMUPR_MCR              HRTIM_BDMUPR_MCR_Msk                     /*!< MCR register update enable */

+#define HRTIM_BDMUPR_MICR_Pos         (1U)

+#define HRTIM_BDMUPR_MICR_Msk         (0x1UL << HRTIM_BDMUPR_MICR_Pos)         /*!< 0x00000002 */

+#define HRTIM_BDMUPR_MICR             HRTIM_BDMUPR_MICR_Msk                    /*!< MICR register update enable */

+#define HRTIM_BDMUPR_MDIER_Pos        (2U)

+#define HRTIM_BDMUPR_MDIER_Msk        (0x1UL << HRTIM_BDMUPR_MDIER_Pos)        /*!< 0x00000004 */

+#define HRTIM_BDMUPR_MDIER            HRTIM_BDMUPR_MDIER_Msk                   /*!< MDIER register update enable */

+#define HRTIM_BDMUPR_MCNT_Pos         (3U)

+#define HRTIM_BDMUPR_MCNT_Msk         (0x1UL << HRTIM_BDMUPR_MCNT_Pos)         /*!< 0x00000008 */

+#define HRTIM_BDMUPR_MCNT             HRTIM_BDMUPR_MCNT_Msk                    /*!< MCNT register update enable */

+#define HRTIM_BDMUPR_MPER_Pos         (4U)

+#define HRTIM_BDMUPR_MPER_Msk         (0x1UL << HRTIM_BDMUPR_MPER_Pos)         /*!< 0x00000010 */

+#define HRTIM_BDMUPR_MPER             HRTIM_BDMUPR_MPER_Msk                    /*!< MPER register update enable */

+#define HRTIM_BDMUPR_MREP_Pos         (5U)

+#define HRTIM_BDMUPR_MREP_Msk         (0x1UL << HRTIM_BDMUPR_MREP_Pos)         /*!< 0x00000020 */

+#define HRTIM_BDMUPR_MREP             HRTIM_BDMUPR_MREP_Msk                    /*!< MREP register update enable */

+#define HRTIM_BDMUPR_MCMP1_Pos        (6U)

+#define HRTIM_BDMUPR_MCMP1_Msk        (0x1UL << HRTIM_BDMUPR_MCMP1_Pos)        /*!< 0x00000040 */

+#define HRTIM_BDMUPR_MCMP1            HRTIM_BDMUPR_MCMP1_Msk                   /*!< MCMP1 register update enable */

+#define HRTIM_BDMUPR_MCMP2_Pos        (7U)

+#define HRTIM_BDMUPR_MCMP2_Msk        (0x1UL << HRTIM_BDMUPR_MCMP2_Pos)        /*!< 0x00000080 */

+#define HRTIM_BDMUPR_MCMP2            HRTIM_BDMUPR_MCMP2_Msk                   /*!< MCMP2 register update enable */

+#define HRTIM_BDMUPR_MCMP3_Pos        (8U)

+#define HRTIM_BDMUPR_MCMP3_Msk        (0x1UL << HRTIM_BDMUPR_MCMP3_Pos)        /*!< 0x00000100 */

+#define HRTIM_BDMUPR_MCMP3            HRTIM_BDMUPR_MCMP3_Msk                   /*!< MCMP3 register update enable */

+#define HRTIM_BDMUPR_MCMP4_Pos        (9U)

+#define HRTIM_BDMUPR_MCMP4_Msk        (0x1UL << HRTIM_BDMUPR_MCMP4_Pos)        /*!< 0x00000200 */

+#define HRTIM_BDMUPR_MCMP4            HRTIM_BDMUPR_MCMP4_Msk                   /*!< MPCMP4 register update enable */

+

+/*******************  Bit definition for HRTIM_BDTUPR register  ***************/

+#define HRTIM_BDTUPR_TIMCR_Pos        (0U)

+#define HRTIM_BDTUPR_TIMCR_Msk        (0x1UL << HRTIM_BDTUPR_TIMCR_Pos)        /*!< 0x00000001 */

+#define HRTIM_BDTUPR_TIMCR            HRTIM_BDTUPR_TIMCR_Msk                   /*!<  TIMCR register update enable */

+#define HRTIM_BDTUPR_TIMICR_Pos       (1U)

+#define HRTIM_BDTUPR_TIMICR_Msk       (0x1UL << HRTIM_BDTUPR_TIMICR_Pos)       /*!< 0x00000002 */

+#define HRTIM_BDTUPR_TIMICR           HRTIM_BDTUPR_TIMICR_Msk                  /*!<  TIMICR register update enable */

+#define HRTIM_BDTUPR_TIMDIER_Pos      (2U)

+#define HRTIM_BDTUPR_TIMDIER_Msk      (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos)      /*!< 0x00000004 */

+#define HRTIM_BDTUPR_TIMDIER          HRTIM_BDTUPR_TIMDIER_Msk                 /*!<  TIMDIER register update enable */

+#define HRTIM_BDTUPR_TIMCNT_Pos       (3U)

+#define HRTIM_BDTUPR_TIMCNT_Msk       (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos)       /*!< 0x00000008 */

+#define HRTIM_BDTUPR_TIMCNT           HRTIM_BDTUPR_TIMCNT_Msk                  /*!<  TIMCNT register update enable */

+#define HRTIM_BDTUPR_TIMPER_Pos       (4U)

+#define HRTIM_BDTUPR_TIMPER_Msk       (0x1UL << HRTIM_BDTUPR_TIMPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_BDTUPR_TIMPER           HRTIM_BDTUPR_TIMPER_Msk                  /*!<  TIMPER register update enable */

+#define HRTIM_BDTUPR_TIMREP_Pos       (5U)

+#define HRTIM_BDTUPR_TIMREP_Msk       (0x1UL << HRTIM_BDTUPR_TIMREP_Pos)       /*!< 0x00000020 */

+#define HRTIM_BDTUPR_TIMREP           HRTIM_BDTUPR_TIMREP_Msk                  /*!<  TIMREP register update enable */

+#define HRTIM_BDTUPR_TIMCMP1_Pos      (6U)

+#define HRTIM_BDTUPR_TIMCMP1_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos)      /*!< 0x00000040 */

+#define HRTIM_BDTUPR_TIMCMP1          HRTIM_BDTUPR_TIMCMP1_Msk                 /*!<  TIMCMP1 register update enable */

+#define HRTIM_BDTUPR_TIMCMP2_Pos      (7U)

+#define HRTIM_BDTUPR_TIMCMP2_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos)      /*!< 0x00000080 */

+#define HRTIM_BDTUPR_TIMCMP2          HRTIM_BDTUPR_TIMCMP2_Msk                 /*!<  TIMCMP2 register update enable */

+#define HRTIM_BDTUPR_TIMCMP3_Pos      (8U)

+#define HRTIM_BDTUPR_TIMCMP3_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos)      /*!< 0x00000100 */

+#define HRTIM_BDTUPR_TIMCMP3          HRTIM_BDTUPR_TIMCMP3_Msk                 /*!<  TIMCMP3 register update enable */

+#define HRTIM_BDTUPR_TIMCMP4_Pos      (9U)

+#define HRTIM_BDTUPR_TIMCMP4_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos)      /*!< 0x00000200 */

+#define HRTIM_BDTUPR_TIMCMP4          HRTIM_BDTUPR_TIMCMP4_Msk                 /*!<  TIMCMP4 register update enable */

+#define HRTIM_BDTUPR_TIMDTR_Pos       (10U)

+#define HRTIM_BDTUPR_TIMDTR_Msk       (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos)       /*!< 0x00000400 */

+#define HRTIM_BDTUPR_TIMDTR           HRTIM_BDTUPR_TIMDTR_Msk                  /*!<  TIMDTR register update enable */

+#define HRTIM_BDTUPR_TIMSET1R_Pos     (11U)

+#define HRTIM_BDTUPR_TIMSET1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos)     /*!< 0x00000800 */

+#define HRTIM_BDTUPR_TIMSET1R         HRTIM_BDTUPR_TIMSET1R_Msk                /*!<  TIMSET1R register update enable */

+#define HRTIM_BDTUPR_TIMRST1R_Pos     (12U)

+#define HRTIM_BDTUPR_TIMRST1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos)     /*!< 0x00001000 */

+#define HRTIM_BDTUPR_TIMRST1R         HRTIM_BDTUPR_TIMRST1R_Msk                /*!<  TIMRST1R register update enable */

+#define HRTIM_BDTUPR_TIMSET2R_Pos     (13U)

+#define HRTIM_BDTUPR_TIMSET2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos)     /*!< 0x00002000 */

+#define HRTIM_BDTUPR_TIMSET2R         HRTIM_BDTUPR_TIMSET2R_Msk                /*!<  TIMSET2R register update enable */

+#define HRTIM_BDTUPR_TIMRST2R_Pos     (14U)

+#define HRTIM_BDTUPR_TIMRST2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos)     /*!< 0x00004000 */

+#define HRTIM_BDTUPR_TIMRST2R         HRTIM_BDTUPR_TIMRST2R_Msk                /*!<  TIMRST2R register update enable */

+#define HRTIM_BDTUPR_TIMEEFR1_Pos     (15U)

+#define HRTIM_BDTUPR_TIMEEFR1_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos)     /*!< 0x00008000 */

+#define HRTIM_BDTUPR_TIMEEFR1         HRTIM_BDTUPR_TIMEEFR1_Msk                /*!<  TIMEEFR1 register update enable */

+#define HRTIM_BDTUPR_TIMEEFR2_Pos     (16U)

+#define HRTIM_BDTUPR_TIMEEFR2_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos)     /*!< 0x00010000 */

+#define HRTIM_BDTUPR_TIMEEFR2         HRTIM_BDTUPR_TIMEEFR2_Msk                /*!<  TIMEEFR2 register update enable */

+#define HRTIM_BDTUPR_TIMRSTR_Pos      (17U)

+#define HRTIM_BDTUPR_TIMRSTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos)      /*!< 0x00020000 */

+#define HRTIM_BDTUPR_TIMRSTR          HRTIM_BDTUPR_TIMRSTR_Msk                 /*!<  TIMRSTR register update enable */

+#define HRTIM_BDTUPR_TIMCHPR_Pos      (18U)

+#define HRTIM_BDTUPR_TIMCHPR_Msk      (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos)      /*!< 0x00040000 */

+#define HRTIM_BDTUPR_TIMCHPR          HRTIM_BDTUPR_TIMCHPR_Msk                 /*!<  TIMCHPR register update enable */

+#define HRTIM_BDTUPR_TIMOUTR_Pos      (19U)

+#define HRTIM_BDTUPR_TIMOUTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos)      /*!< 0x00080000 */

+#define HRTIM_BDTUPR_TIMOUTR          HRTIM_BDTUPR_TIMOUTR_Msk                 /*!<  TIMOUTR register update enable */

+#define HRTIM_BDTUPR_TIMFLTR_Pos      (20U)

+#define HRTIM_BDTUPR_TIMFLTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos)      /*!< 0x00100000 */

+#define HRTIM_BDTUPR_TIMFLTR          HRTIM_BDTUPR_TIMFLTR_Msk                 /*!<  TIMFLTR register update enable */

+

+/*******************  Bit definition for HRTIM_BDMADR register  ***************/

+#define HRTIM_BDMADR_BDMADR_Pos       (0U)

+#define HRTIM_BDMADR_BDMADR_Msk       (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos) /*!< 0xFFFFFFFF */

+#define HRTIM_BDMADR_BDMADR           HRTIM_BDMADR_BDMADR_Msk                  /*!<  Burst DMA Data register */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             RAM ECC monitoring                             */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for RAMECC_IER register  ******************/

+#define RAMECC_IER_GECCDEBWIE_Pos         (3U)

+#define RAMECC_IER_GECCDEBWIE_Msk         (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)  /*!< 0x00000008 */

+#define RAMECC_IER_GECCDEBWIE             RAMECC_IER_GECCDEBWIE_Msk             /*!< Global ECC double error on byte write (BW) interrupt enable */

+#define RAMECC_IER_GECCDEIE_Pos           (2U)

+#define RAMECC_IER_GECCDEIE_Msk           (0x1UL << RAMECC_IER_GECCDEIE_Pos)    /*!< 0x00000004 */

+#define RAMECC_IER_GECCDEIE               RAMECC_IER_GECCDEIE_Msk               /*!< Global ECC double error interrupt enable */

+#define RAMECC_IER_GECCSEIE_Pos           (1U)

+#define RAMECC_IER_GECCSEIE_Msk           (0x1UL << RAMECC_IER_GECCSEIE_Pos)    /*!< 0x00000002 */

+#define RAMECC_IER_GECCSEIE               RAMECC_IER_GECCSEIE_Msk               /*!< Global ECC single error interrupt enable */

+#define RAMECC_IER_GIE_Pos                (0U)

+#define RAMECC_IER_GIE_Msk                (0x1UL << RAMECC_IER_GIE_Pos)         /*!< 0x00000001 */

+#define RAMECC_IER_GIE                    RAMECC_IER_GIE_Msk                    /*!< Global interrupt enable */

+

+/*******************  Bit definition for RAMECC_CR register  ******************/

+#define RAMECC_CR_ECCELEN_Pos             (5U)

+#define RAMECC_CR_ECCELEN_Msk             (0x1UL << RAMECC_CR_ECCELEN_Pos)      /*!< 0x00000020 */

+#define RAMECC_CR_ECCELEN                 RAMECC_CR_ECCELEN_Msk                 /*!< ECC error latching enable */

+#define RAMECC_CR_ECCDEBWIE_Pos           (4U)

+#define RAMECC_CR_ECCDEBWIE_Msk           (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)    /*!< 0x00000010 */

+#define RAMECC_CR_ECCDEBWIE               RAMECC_CR_ECCDEBWIE_Msk               /*!< ECC double error on byte write (BW) interrupt enable */

+#define RAMECC_CR_ECCDEIE_Pos             (3U)

+#define RAMECC_CR_ECCDEIE_Msk             (0x1UL << RAMECC_CR_ECCDEIE_Pos)      /*!< 0x00000008 */

+#define RAMECC_CR_ECCDEIE                 RAMECC_CR_ECCDEIE_Msk                 /*!< ECC double error interrupt enable */

+#define RAMECC_CR_ECCSEIE_Pos             (2U)

+#define RAMECC_CR_ECCSEIE_Msk             (0x1UL << RAMECC_CR_ECCSEIE_Pos)      /*!< 0x00000004 */

+#define RAMECC_CR_ECCSEIE                 RAMECC_CR_ECCSEIE_Msk                 /*!< ECC single error interrupt enable */

+

+/*******************  Bit definition for RAMECC_SR register  ******************/

+#define RAMECC_SR_DEBWDF_Pos             (2U)

+#define RAMECC_SR_DEBWDF_Msk             (0x1UL << RAMECC_SR_DEBWDF_Pos)        /*!< 0x00000004 */

+#define RAMECC_SR_DEBWDF                 RAMECC_SR_DEBWDF_Msk                   /*!< ECC double error on byte write (BW) detected flag */

+#define RAMECC_SR_DEDF_Pos               (1U)

+#define RAMECC_SR_DEDF_Msk               (0x1UL << RAMECC_SR_DEDF_Pos)          /*!< 0x00000002 */

+#define RAMECC_SR_DEDF                   RAMECC_SR_DEDF_Msk                     /*!< ECC double error detected flag */

+#define RAMECC_SR_SEDCF_Pos              (0U)

+#define RAMECC_SR_SEDCF_Msk              (0x1UL << RAMECC_SR_SEDCF_Pos)         /*!< 0x00000001 */

+#define RAMECC_SR_SEDCF                  RAMECC_SR_SEDCF_Msk                    /*!< ECC single error detected and corrected flag */

+

+/******************  Bit definition for RAMECC_FAR register  ******************/

+#define RAMECC_FAR_FADD_Pos              (0U)

+#define RAMECC_FAR_FADD_Msk              (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)  /*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FADD                  RAMECC_FAR_FADD_Msk                    /*!< ECC error failing address */

+

+/******************  Bit definition for RAMECC_FDRL register  *****************/

+#define RAMECC_FAR_FDATAL_Pos            (0U)

+#define RAMECC_FAR_FDATAL_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FDATAL                RAMECC_FAR_FDATAL_Msk                  /*!< ECC error failing address */

+

+/******************  Bit definition for RAMECC_FDRH register  *****************/

+#define RAMECC_FAR_FDATAH_Pos            (0U)

+#define RAMECC_FAR_FDATAH_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FDATAH                RAMECC_FAR_FDATAH_Msk                  /* Failing data high (64-bit memory) */

+

+/*****************  Bit definition for RAMECC_FECR register  ******************/

+#define RAMECC_FECR_FEC_Pos              (0U)

+#define RAMECC_FECR_FEC_Msk              (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)  /*!< 0xFFFFFFFF */

+#define RAMECC_FECR_FEC                  RAMECC_FECR_FEC_Msk                    /*!< Failing error code */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                MDIOS                                        */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for MDIOS_CR register  *******************/

+#define MDIOS_CR_EN_Pos                (0U)

+#define MDIOS_CR_EN_Msk                (0x1UL << MDIOS_CR_EN_Pos)              /*!< 0x00000001 */

+#define MDIOS_CR_EN                    MDIOS_CR_EN_Msk                         /*!<  MDIOS slave peripheral enable */

+#define MDIOS_CR_WRIE_Pos              (1U)

+#define MDIOS_CR_WRIE_Msk              (0x1UL << MDIOS_CR_WRIE_Pos)            /*!< 0x00000002 */

+#define MDIOS_CR_WRIE                  MDIOS_CR_WRIE_Msk                       /*!<  MDIOS slave register write interrupt enable. */

+#define MDIOS_CR_RDIE_Pos              (2U)

+#define MDIOS_CR_RDIE_Msk              (0x1UL << MDIOS_CR_RDIE_Pos)            /*!< 0x00000004 */

+#define MDIOS_CR_RDIE                  MDIOS_CR_RDIE_Msk                       /*!<  MDIOS slave register read interrupt enable. */

+#define MDIOS_CR_EIE_Pos               (3U)

+#define MDIOS_CR_EIE_Msk               (0x1UL << MDIOS_CR_EIE_Pos)             /*!< 0x00000008 */

+#define MDIOS_CR_EIE                   MDIOS_CR_EIE_Msk                        /*!<  MDIOS slave register error interrupt enable. */

+#define MDIOS_CR_DPC_Pos               (7U)

+#define MDIOS_CR_DPC_Msk               (0x1UL << MDIOS_CR_DPC_Pos)             /*!< 0x00000080 */

+#define MDIOS_CR_DPC                   MDIOS_CR_DPC_Msk                        /*!<  MDIOS slave disable preamble check. */

+#define MDIOS_CR_PORT_ADDRESS_Pos      (8U)

+#define MDIOS_CR_PORT_ADDRESS_Msk      (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)   /*!< 0x00001F00 */

+#define MDIOS_CR_PORT_ADDRESS          MDIOS_CR_PORT_ADDRESS_Msk               /*!<  MDIOS slave port address mask. */

+#define MDIOS_CR_PORT_ADDRESS_0        (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000100 */

+#define MDIOS_CR_PORT_ADDRESS_1        (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000200 */

+#define MDIOS_CR_PORT_ADDRESS_2        (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000400 */

+#define MDIOS_CR_PORT_ADDRESS_3        (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000800 */

+#define MDIOS_CR_PORT_ADDRESS_4        (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001000 */

+

+/********************  Bit definition for MDIOS_SR register  *******************/

+#define MDIOS_SR_PERF_Pos              (0U)

+#define MDIOS_SR_PERF_Msk              (0x1UL << MDIOS_SR_PERF_Pos)            /*!< 0x00000001 */

+#define MDIOS_SR_PERF                  MDIOS_SR_PERF_Msk                       /*!<  MDIOS slave turnaround error flag*/

+#define MDIOS_SR_SERF_Pos              (1U)

+#define MDIOS_SR_SERF_Msk              (0x1UL << MDIOS_SR_SERF_Pos)            /*!< 0x00000002 */

+#define MDIOS_SR_SERF                  MDIOS_SR_SERF_Msk                       /*!<  MDIOS slave start error flag */

+#define MDIOS_SR_TERF_Pos              (2U)

+#define MDIOS_SR_TERF_Msk              (0x1UL << MDIOS_SR_TERF_Pos)            /*!< 0x00000004 */

+#define MDIOS_SR_TERF                  MDIOS_SR_TERF_Msk                       /*!<  MDIOS slave preamble error flag */

+

+/********************  Bit definition for MDIOS_CLRFR register  *******************/

+#define MDIOS_SR_CPERF_Pos             (0U)

+#define MDIOS_SR_CPERF_Msk             (0x1UL << MDIOS_SR_CPERF_Pos)           /*!< 0x00000001 */

+#define MDIOS_SR_CPERF                 MDIOS_SR_CPERF_Msk                      /*!<  MDIOS slave Clear the turnaround error flag */

+#define MDIOS_SR_CSERF_Pos             (1U)

+#define MDIOS_SR_CSERF_Msk             (0x1UL << MDIOS_SR_CSERF_Pos)           /*!< 0x00000002 */

+#define MDIOS_SR_CSERF                 MDIOS_SR_CSERF_Msk                      /*!<  MDIOS slave Clear the start error flag */

+#define MDIOS_SR_CTERF_Pos             (2U)

+#define MDIOS_SR_CTERF_Msk             (0x1UL << MDIOS_SR_CTERF_Pos)           /*!< 0x00000004 */

+#define MDIOS_SR_CTERF                 MDIOS_SR_CTERF_Msk                      /*!<  MDIOS slave Clear the preamble error flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                       USB_OTG                              */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/

+#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)

+#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */

+#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */

+#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)

+#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */

+#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */

+#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)

+#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */

+#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */

+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)

+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */

+#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */

+#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)

+#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */

+#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */

+#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)

+#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */

+#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */

+#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)

+#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */

+#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */

+#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)

+#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */

+#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */

+#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)

+#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */

+#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */

+#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)

+#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */

+#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */

+#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)

+#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */

+#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */

+#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)

+#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */

+#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */

+#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)

+#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */

+#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */

+#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)

+#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */

+#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */

+#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)

+#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */

+#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */

+#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)

+#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */

+#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */

+#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)

+#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */

+#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */

+#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)

+#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */

+#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */

+

+/********************  Bit definition forUSB_OTG_HCFG register  ********************/

+

+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)

+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */

+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */

+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)

+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */

+

+/********************  Bit definition forUSB_OTG_DCFG register  ********************/

+

+#define USB_OTG_DCFG_DSPD_Pos                    (0U)

+#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */

+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */

+#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */

+#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)

+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */

+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */

+

+#define USB_OTG_DCFG_DAD_Pos                     (4U)

+#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */

+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */

+#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */

+#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */

+#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */

+#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */

+#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */

+#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */

+#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */

+

+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)

+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */

+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */

+#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */

+#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */

+

+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)

+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */

+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */

+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */

+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */

+

+/********************  Bit definition forUSB_OTG_PCGCR register  ********************/

+#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)

+#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */

+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */

+#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)

+#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */

+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */

+#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)

+#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */

+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */

+

+/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/

+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)

+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */

+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */

+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)

+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */

+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */

+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)

+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */

+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */

+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)

+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */

+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */

+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)

+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */

+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */

+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)

+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */

+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */

+

+/********************  Bit definition forUSB_OTG_DCTL register  ********************/

+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)

+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */

+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */

+#define USB_OTG_DCTL_SDIS_Pos                    (1U)

+#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */

+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */

+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)

+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */

+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */

+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)

+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */

+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */

+

+#define USB_OTG_DCTL_TCTL_Pos                    (4U)

+#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */

+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */

+#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */

+#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */

+#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */

+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)

+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */

+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */

+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)

+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */

+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */

+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)

+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */

+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */

+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)

+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */

+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */

+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)

+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */

+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */

+

+/********************  Bit definition forUSB_OTG_HFIR register  ********************/

+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)

+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */

+

+/********************  Bit definition forUSB_OTG_HFNUM register  ********************/

+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)

+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */

+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)

+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */

+

+/********************  Bit definition forUSB_OTG_DSTS register  ********************/

+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)

+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */

+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */

+

+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)

+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */

+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */

+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */

+#define USB_OTG_DSTS_EERR_Pos                    (3U)

+#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */

+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */

+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)

+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */

+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */

+

+/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/

+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)

+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */

+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */

+

+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)

+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */

+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */

+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */

+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */

+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */

+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */

+#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */

+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)

+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */

+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */

+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)

+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */

+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */

+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)

+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */

+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */

+

+/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/

+

+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)

+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */

+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */

+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */

+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */

+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */

+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)

+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */

+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */

+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)

+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */

+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */

+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)

+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */

+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */

+

+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)

+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */

+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */

+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */

+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */

+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */

+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */

+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)

+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */

+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */

+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)

+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */

+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */

+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)

+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */

+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */

+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)

+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */

+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */

+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)

+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */

+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */

+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)

+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */

+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */

+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)

+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */

+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */

+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)

+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */

+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */

+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)

+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */

+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */

+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)

+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */

+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */

+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)

+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */

+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */

+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)

+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */

+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */

+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)

+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */

+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */

+

+/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/

+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)

+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */

+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */

+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)

+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */

+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */

+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)

+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */

+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */

+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)

+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */

+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */

+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)

+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */

+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */

+

+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)

+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */

+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */

+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */

+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */

+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */

+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */

+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */

+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)

+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */

+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */

+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)

+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */

+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */

+

+/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/

+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)

+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */

+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)

+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */

+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)

+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */

+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)

+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */

+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)

+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */

+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)

+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */

+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)

+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */

+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)

+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */

+

+/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/

+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)

+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */

+

+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)

+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */

+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */

+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */

+

+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)

+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */

+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */

+

+/********************  Bit definition forUSB_OTG_HAINT register  ********************/

+#define USB_OTG_HAINT_HAINT_Pos                  (0U)

+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */

+

+/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/

+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)

+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */

+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)

+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */

+#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)

+#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */

+#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask               */

+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)

+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */

+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)

+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */

+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)

+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */

+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)

+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */

+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)

+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */

+#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)

+#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */

+#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)

+#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask               */

+#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)

+#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask               */

+#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)

+#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                */

+

+/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/

+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)

+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */

+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */

+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)

+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */

+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */

+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)

+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */

+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */

+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)

+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */

+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */

+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)

+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */

+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */

+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)

+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */

+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */

+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)

+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */

+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */

+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)

+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */

+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */

+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)

+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */

+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */

+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)

+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */

+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */

+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)

+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */

+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */

+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)

+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */

+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */

+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)

+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */

+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */

+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)

+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */

+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */

+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)

+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */

+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */

+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)

+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */

+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */

+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)

+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */

+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */

+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)

+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */

+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */

+#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)

+#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */

+#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */

+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)

+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */

+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */

+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)

+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */

+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */

+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)

+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */

+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */

+#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)

+#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */

+#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */

+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)

+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */

+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */

+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)

+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */

+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */

+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)

+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */

+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */

+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)

+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */

+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */

+

+/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/

+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)

+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */

+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */

+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)

+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */

+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */

+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)

+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */

+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */

+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)

+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */

+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */

+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)

+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */

+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */

+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)

+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */

+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */

+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)

+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */

+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */

+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)

+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */

+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */

+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)

+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */

+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */

+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)

+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */

+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */

+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)

+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */

+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */

+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)

+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */

+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */

+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)

+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */

+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */

+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)

+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */

+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */

+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)

+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */

+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */

+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)

+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */

+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */

+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)

+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */

+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */

+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)

+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */

+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */

+#define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)

+#define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */

+#define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */

+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)

+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */

+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */

+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)

+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */

+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */

+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)

+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */

+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */

+#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)

+#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */

+#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */

+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)

+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */

+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */

+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)

+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */

+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */

+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)

+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */

+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */

+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)

+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */

+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */

+

+/********************  Bit definition forUSB_OTG_DAINT register  ********************/

+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)

+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */

+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)

+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */

+

+/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/

+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)

+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */

+

+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/

+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)

+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */

+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */

+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)

+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */

+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */

+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)

+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */

+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */

+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)

+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */

+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */

+

+/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/

+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)

+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */

+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)

+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */

+

+/********************  Bit definition for OTG register  ********************/

+

+#define USB_OTG_CHNUM_Pos                        (0U)

+#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)  /*!< 0x0000000F */

+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */

+#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */

+#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */

+#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */

+#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */

+#define USB_OTG_BCNT_Pos                         (4U)

+#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */

+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */

+

+#define USB_OTG_DPID_Pos                         (15U)

+#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)   /*!< 0x00018000 */

+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */

+#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */

+#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */

+

+#define USB_OTG_PKTSTS_Pos                       (17U)

+#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */

+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */

+#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */

+#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */

+#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */

+#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */

+

+#define USB_OTG_EPNUM_Pos                        (0U)

+#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)  /*!< 0x0000000F */

+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */

+#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */

+#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */

+#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */

+#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */

+

+#define USB_OTG_FRMNUM_Pos                       (21U)

+#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */

+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */

+#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */

+#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */

+#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */

+#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */

+

+/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/

+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)

+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/

+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)

+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */

+

+/********************  Bit definition for OTG register  ********************/

+#define USB_OTG_NPTXFSA_Pos                      (0U)

+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */

+#define USB_OTG_NPTXFD_Pos                       (16U)

+#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */

+#define USB_OTG_TX0FSA_Pos                       (0U)

+#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */

+#define USB_OTG_TX0FD_Pos                        (16U)

+#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */

+

+/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/

+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)

+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */

+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */

+

+/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/

+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)

+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */

+

+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)

+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */

+

+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)

+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/

+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)

+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */

+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */

+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)

+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */

+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */

+

+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)

+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */

+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */

+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */

+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)

+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */

+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */

+

+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)

+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */

+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */

+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)

+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */

+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */

+

+/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */

+

+/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/

+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)

+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */

+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */

+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)

+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */

+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */

+

+/********************  Bit definition forUSB_OTG_GCCFG register  ********************/

+#define USB_OTG_GCCFG_DCDET_Pos                  (0U)

+#define USB_OTG_GCCFG_DCDET_Msk                  (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */

+#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */

+#define USB_OTG_GCCFG_PDET_Pos                   (1U)

+#define USB_OTG_GCCFG_PDET_Msk                   (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */

+#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */

+#define USB_OTG_GCCFG_SDET_Pos                   (2U)

+#define USB_OTG_GCCFG_SDET_Msk                   (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */

+#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */

+#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)

+#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */

+#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */

+#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)

+#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */

+#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */

+#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)

+#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */

+#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */

+#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)

+#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */

+#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/

+#define USB_OTG_GCCFG_PDEN_Pos                   (19U)

+#define USB_OTG_GCCFG_PDEN_Msk                   (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */

+#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/

+#define USB_OTG_GCCFG_SDEN_Pos                   (20U)

+#define USB_OTG_GCCFG_SDEN_Msk                   (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */

+#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */

+#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)

+#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */

+#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */

+

+/********************  Bit definition forUSB_OTG_GPWRDN) register  ********************/

+#define USB_OTG_GPWRDN_ADPMEN_Pos                (0U)

+#define USB_OTG_GPWRDN_ADPMEN_Msk                (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */

+#define USB_OTG_GPWRDN_ADPMEN                    USB_OTG_GPWRDN_ADPMEN_Msk     /*!< ADP module enable */

+#define USB_OTG_GPWRDN_ADPIF_Pos                 (23U)

+#define USB_OTG_GPWRDN_ADPIF_Msk                 (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */

+#define USB_OTG_GPWRDN_ADPIF                     USB_OTG_GPWRDN_ADPIF_Msk      /*!< ADP Interrupt flag */

+

+/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/

+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)

+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */

+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)

+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */

+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */

+

+/********************  Bit definition forUSB_OTG_CID register  ********************/

+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)

+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */

+

+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/

+#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)

+#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */

+#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */

+#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)

+#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */

+#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */

+#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)

+#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */

+#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */

+#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)

+#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */

+#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */

+#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)

+#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */

+#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */

+#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)

+#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */

+#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */

+#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)

+#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */

+#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */

+#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)

+#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */

+#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */

+#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)

+#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */

+#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */

+#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)

+#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */

+#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */

+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)

+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */

+#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */

+#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)

+#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */

+#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */

+#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)

+#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */

+#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */

+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)

+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */

+#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */

+#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)

+#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */

+#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */

+

+/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/

+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)

+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */

+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)

+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */

+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)

+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */

+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)

+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */

+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)

+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */

+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)

+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */

+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)

+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */

+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)

+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */

+

+/********************  Bit definition forUSB_OTG_HPRT register  ********************/

+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)

+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */

+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */

+#define USB_OTG_HPRT_PCDET_Pos                   (1U)

+#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */

+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */

+#define USB_OTG_HPRT_PENA_Pos                    (2U)

+#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */

+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */

+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)

+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */

+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */

+#define USB_OTG_HPRT_POCA_Pos                    (4U)

+#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */

+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */

+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)

+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */

+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */

+#define USB_OTG_HPRT_PRES_Pos                    (6U)

+#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */

+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume   */

+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)

+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */

+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend  */

+#define USB_OTG_HPRT_PRST_Pos                    (8U)

+#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */

+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset    */

+

+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)

+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */

+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */

+#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */

+#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */

+#define USB_OTG_HPRT_PPWR_Pos                    (12U)

+#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */

+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */

+

+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)

+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */

+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */

+#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */

+#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */

+#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */

+#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */

+

+#define USB_OTG_HPRT_PSPD_Pos                    (17U)

+#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */

+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */

+#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */

+#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */

+

+/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/

+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)

+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)

+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)

+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */

+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)

+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */

+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)

+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */

+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)

+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */

+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)

+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)

+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)

+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)

+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */

+

+/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/

+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)

+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */

+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)

+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/

+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)

+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */

+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)

+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */

+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */

+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)

+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */

+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */

+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)

+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */

+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */

+

+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)

+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */

+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */

+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)

+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */

+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */

+

+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)

+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */

+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */

+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */

+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */

+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */

+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */

+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)

+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */

+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */

+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)

+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */

+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */

+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)

+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */

+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)

+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */

+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)

+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */

+

+/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/

+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)

+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */

+

+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)

+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */

+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */

+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */

+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */

+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */

+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */

+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)

+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */

+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */

+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)

+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */

+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */

+

+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)

+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */

+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */

+

+#define USB_OTG_HCCHAR_MC_Pos                    (20U)

+#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */

+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */

+#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */

+#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */

+

+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)

+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */

+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */

+#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */

+#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */

+#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */

+#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */

+#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */

+#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */

+#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */

+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)

+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */

+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)

+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */

+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)

+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */

+

+/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/

+

+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)

+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */

+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */

+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */

+

+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)

+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */

+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */

+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */

+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */

+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */

+

+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)

+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */

+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */

+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */

+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */

+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)

+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */

+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */

+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)

+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */

+

+/********************  Bit definition forUSB_OTG_HCINT register  ********************/

+#define USB_OTG_HCINT_XFRC_Pos                   (0U)

+#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */

+#define USB_OTG_HCINT_CHH_Pos                    (1U)

+#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */

+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)

+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */

+#define USB_OTG_HCINT_STALL_Pos                  (3U)

+#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */

+#define USB_OTG_HCINT_NAK_Pos                    (4U)

+#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */

+#define USB_OTG_HCINT_ACK_Pos                    (5U)

+#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */

+#define USB_OTG_HCINT_NYET_Pos                   (6U)

+#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */

+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */

+#define USB_OTG_HCINT_TXERR_Pos                  (7U)

+#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */

+#define USB_OTG_HCINT_BBERR_Pos                  (8U)

+#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */

+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)

+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */

+#define USB_OTG_HCINT_DTERR_Pos                  (10U)

+#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */

+

+/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/

+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)

+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */

+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)

+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */

+#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)

+#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */

+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)

+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */

+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)

+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */

+#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)

+#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */

+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)

+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */

+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)

+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */

+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */

+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)

+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */

+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)

+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */

+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)

+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */

+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */

+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)

+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */

+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */

+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)

+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */

+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */

+

+/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/

+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)

+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */

+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)

+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */

+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)

+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */

+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)

+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */

+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)

+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */

+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)

+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */

+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)

+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */

+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */

+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)

+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */

+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)

+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */

+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)

+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */

+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)

+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */

+

+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/

+

+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)

+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */

+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)

+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */

+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)

+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */

+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */

+/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/

+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)

+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */

+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)

+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */

+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)

+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */

+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)

+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */

+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */

+#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */

+#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/

+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)

+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */

+

+/********************  Bit definition forUSB_OTG_HCDMA register  ********************/

+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)

+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */

+

+/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/

+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)

+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */

+

+/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/

+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)

+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */

+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)

+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/

+

+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)

+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */

+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)

+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */

+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */

+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)

+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */

+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */

+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)

+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */

+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)

+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */

+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */

+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)

+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */

+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */

+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)

+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */

+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */

+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)

+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */

+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */

+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)

+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */

+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */

+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)

+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */

+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)

+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */

+

+/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/

+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)

+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */

+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)

+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */

+#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)

+#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */

+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)

+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */

+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)

+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */

+#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)

+#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< OUT Status Phase Received interrupt */

+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)

+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */

+#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)

+#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */

+#define USB_OTG_DOEPINT_BERR_Pos                 (12U)

+#define USB_OTG_DOEPINT_BERR_Msk                 (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPINT_BERR                      USB_OTG_DOEPINT_BERR_Msk   /*!< Babble error interrupt */

+#define USB_OTG_DOEPINT_NAK_Pos                  (13U)

+#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */

+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)

+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */

+#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)

+#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */

+#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */

+

+/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/

+

+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)

+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */

+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)

+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */

+

+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)

+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */

+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */

+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */

+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition for PCGCCTL register  ********************/

+#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)

+#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */

+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */

+#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)

+#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */

+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */

+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)

+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */

+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/** @addtogroup Exported_macros

+  * @{

+  */

+

+/******************************* ADC Instances ********************************/

+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \

+                                       ((INSTANCE) == ADC2) || \

+                                       ((INSTANCE) == ADC3))

+

+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)

+

+#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) ||\

+                                          ((INSTANCE) == ADC3_COMMON))

+

+/******************************** COMP Instances ******************************/

+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \

+                                       ((INSTANCE) == COMP2))

+

+#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)

+/******************** COMP Instances with window mode capability **************/

+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)

+

+

+/******************************* CRC Instances ********************************/

+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

+

+/******************************* DAC Instances ********************************/

+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)

+/******************************* DCMI Instances *******************************/

+#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)

+

+/******************************* DELAYBLOCK Instances *******************************/

+#define IS_DLYB_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DLYB_SDMMC1) || \

+                                         ((INSTANCE) == DLYB_SDMMC2) || \

+                                         ((INSTANCE) == DLYB_QUADSPI))

+/****************************** DFSDM Instances *******************************/

+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \

+                                               ((INSTANCE) == DFSDM1_Filter1) || \

+                                               ((INSTANCE) == DFSDM1_Filter2) || \

+                                               ((INSTANCE) == DFSDM1_Filter3))

+

+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \

+                                                 ((INSTANCE) == DFSDM1_Channel1) || \

+                                                 ((INSTANCE) == DFSDM1_Channel2) || \

+                                                 ((INSTANCE) == DFSDM1_Channel3) || \

+                                                 ((INSTANCE) == DFSDM1_Channel4) || \

+                                                 ((INSTANCE) == DFSDM1_Channel5) || \

+                                                 ((INSTANCE) == DFSDM1_Channel6) || \

+                                                 ((INSTANCE) == DFSDM1_Channel7))

+/****************************** RAMECC Instances ******************************/

+#define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC1_Monitor1)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor2)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor3)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor4)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor5)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor1)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor2)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor3)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor4)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor5)   || \

+                                                  ((INSTANCE) == RAMECC3_Monitor1)   || \

+                                                  ((INSTANCE) == RAMECC3_Monitor2))

+

+/******************************** DMA Instances *******************************/

+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \

+                                       ((INSTANCE) == DMA1_Stream1)   || \

+                                       ((INSTANCE) == DMA1_Stream2)   || \

+                                       ((INSTANCE) == DMA1_Stream3)   || \

+                                       ((INSTANCE) == DMA1_Stream4)   || \

+                                       ((INSTANCE) == DMA1_Stream5)   || \

+                                       ((INSTANCE) == DMA1_Stream6)   || \

+                                       ((INSTANCE) == DMA1_Stream7)   || \

+                                       ((INSTANCE) == DMA2_Stream0)   || \

+                                       ((INSTANCE) == DMA2_Stream1)   || \

+                                       ((INSTANCE) == DMA2_Stream2)   || \

+                                       ((INSTANCE) == DMA2_Stream3)   || \

+                                       ((INSTANCE) == DMA2_Stream4)   || \

+                                       ((INSTANCE) == DMA2_Stream5)   || \

+                                       ((INSTANCE) == DMA2_Stream6)   || \

+                                       ((INSTANCE) == DMA2_Stream7)   || \

+                                       ((INSTANCE) == BDMA_Channel0) || \

+                                       ((INSTANCE) == BDMA_Channel1) || \

+                                       ((INSTANCE) == BDMA_Channel2) || \

+                                       ((INSTANCE) == BDMA_Channel3) || \

+                                       ((INSTANCE) == BDMA_Channel4) || \

+                                       ((INSTANCE) == BDMA_Channel5) || \

+                                       ((INSTANCE) == BDMA_Channel6) || \

+                                       ((INSTANCE) == BDMA_Channel7))

+

+/****************************** BDMA CHANNEL Instances ***************************/

+#define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \

+                                            ((INSTANCE) == BDMA_Channel1) || \

+                                            ((INSTANCE) == BDMA_Channel2) || \

+                                            ((INSTANCE) == BDMA_Channel3) || \

+                                            ((INSTANCE) == BDMA_Channel4) || \

+                                            ((INSTANCE) == BDMA_Channel5) || \

+                                            ((INSTANCE) == BDMA_Channel6) || \

+                                            ((INSTANCE) == BDMA_Channel7))

+

+/****************************** DMA DMAMUX ALL Instances ***************************/

+#define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)    || \

+                                               ((INSTANCE) == DMA1_Stream1)    || \

+                                               ((INSTANCE) == DMA1_Stream2)    || \

+                                               ((INSTANCE) == DMA1_Stream3)    || \

+                                               ((INSTANCE) == DMA1_Stream4)    || \

+                                               ((INSTANCE) == DMA1_Stream5)    || \

+                                               ((INSTANCE) == DMA1_Stream6)    || \

+                                               ((INSTANCE) == DMA1_Stream7)    || \

+                                               ((INSTANCE) == DMA2_Stream0)    || \

+                                               ((INSTANCE) == DMA2_Stream1)    || \

+                                               ((INSTANCE) == DMA2_Stream2)    || \

+                                               ((INSTANCE) == DMA2_Stream3)    || \

+                                               ((INSTANCE) == DMA2_Stream4)    || \

+                                               ((INSTANCE) == DMA2_Stream5)    || \

+                                               ((INSTANCE) == DMA2_Stream6)    || \

+                                               ((INSTANCE) == DMA2_Stream7)    || \

+                                               ((INSTANCE) == BDMA_Channel0)   || \

+                                               ((INSTANCE) == BDMA_Channel1)   || \

+                                               ((INSTANCE) == BDMA_Channel2)   || \

+                                               ((INSTANCE) == BDMA_Channel3)   || \

+                                               ((INSTANCE) == BDMA_Channel4)   || \

+                                               ((INSTANCE) == BDMA_Channel5)   || \

+                                               ((INSTANCE) == BDMA_Channel6)   || \

+                                               ((INSTANCE) == BDMA_Channel7))

+

+/****************************** BDMA DMAMUX Instances ***************************/

+#define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == BDMA_Channel0) || \

+                                                    ((INSTANCE) == BDMA_Channel1) || \

+                                                    ((INSTANCE) == BDMA_Channel2) || \

+                                                    ((INSTANCE) == BDMA_Channel3) || \

+                                                    ((INSTANCE) == BDMA_Channel4) || \

+                                                    ((INSTANCE) == BDMA_Channel5) || \

+                                                    ((INSTANCE) == BDMA_Channel6) || \

+                                                    ((INSTANCE) == BDMA_Channel7))

+

+/****************************** DMA STREAM Instances ***************************/

+#define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \

+                                          ((INSTANCE) == DMA1_Stream1)   || \

+                                          ((INSTANCE) == DMA1_Stream2)   || \

+                                          ((INSTANCE) == DMA1_Stream3)   || \

+                                          ((INSTANCE) == DMA1_Stream4)   || \

+                                          ((INSTANCE) == DMA1_Stream5)   || \

+                                          ((INSTANCE) == DMA1_Stream6)   || \

+                                          ((INSTANCE) == DMA1_Stream7)   || \

+                                          ((INSTANCE) == DMA2_Stream0)   || \

+                                          ((INSTANCE) == DMA2_Stream1)   || \

+                                          ((INSTANCE) == DMA2_Stream2)   || \

+                                          ((INSTANCE) == DMA2_Stream3)   || \

+                                          ((INSTANCE) == DMA2_Stream4)   || \

+                                          ((INSTANCE) == DMA2_Stream5)   || \

+                                          ((INSTANCE) == DMA2_Stream6)   || \

+                                          ((INSTANCE) == DMA2_Stream7))

+

+/****************************** DMA DMAMUX Instances ***************************/

+#define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)   || \

+                                                  ((INSTANCE) == DMA1_Stream1)   || \

+                                                  ((INSTANCE) == DMA1_Stream2)   || \

+                                                  ((INSTANCE) == DMA1_Stream3)   || \

+                                                  ((INSTANCE) == DMA1_Stream4)   || \

+                                                  ((INSTANCE) == DMA1_Stream5)   || \

+                                                  ((INSTANCE) == DMA1_Stream6)   || \

+                                                  ((INSTANCE) == DMA1_Stream7)   || \

+                                                  ((INSTANCE) == DMA2_Stream0)   || \

+                                                  ((INSTANCE) == DMA2_Stream1)   || \

+                                                  ((INSTANCE) == DMA2_Stream2)   || \

+                                                  ((INSTANCE) == DMA2_Stream3)   || \

+                                                  ((INSTANCE) == DMA2_Stream4)   || \

+                                                  ((INSTANCE) == DMA2_Stream5)   || \

+                                                  ((INSTANCE) == DMA2_Stream6)   || \

+                                                  ((INSTANCE) == DMA2_Stream7))

+

+/******************************** DMA Request Generator Instances **************/

+#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator1) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator2) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator3) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator4) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator5) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator6) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator7) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator0) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator1) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator2) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator3) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator4) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator5) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator6) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator7))

+

+/******************************* DMA2D Instances *******************************/

+#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)

+

+/******************************** MDMA Request Generator Instances **************/

+#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0)  || \

+                                               ((INSTANCE) == MDMA_Channel1)  || \

+                                               ((INSTANCE) == MDMA_Channel2)  || \

+                                               ((INSTANCE) == MDMA_Channel3)  || \

+                                               ((INSTANCE) == MDMA_Channel4)  || \

+                                               ((INSTANCE) == MDMA_Channel5)  || \

+                                               ((INSTANCE) == MDMA_Channel6)  || \

+                                               ((INSTANCE) == MDMA_Channel7)  || \

+                                               ((INSTANCE) == MDMA_Channel8)  || \

+                                               ((INSTANCE) == MDMA_Channel9)  || \

+                                               ((INSTANCE) == MDMA_Channel10) || \

+                                               ((INSTANCE) == MDMA_Channel11) || \

+                                               ((INSTANCE) == MDMA_Channel12) || \

+                                               ((INSTANCE) == MDMA_Channel13) || \

+                                               ((INSTANCE) == MDMA_Channel14) || \

+                                               ((INSTANCE) == MDMA_Channel15))

+

+/******************************* QUADSPI Instances *******************************/

+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)

+

+/******************************* FDCAN Instances ******************************/

+#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \

+                                             ((__INSTANCE__) == FDCAN2))

+

+#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)

+

+/******************************* GPIO Instances *******************************/

+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \

+                                        ((INSTANCE) == GPIOB) || \

+                                        ((INSTANCE) == GPIOC) || \

+                                        ((INSTANCE) == GPIOD) || \

+                                        ((INSTANCE) == GPIOE) || \

+                                        ((INSTANCE) == GPIOF) || \

+                                        ((INSTANCE) == GPIOG) || \

+                                        ((INSTANCE) == GPIOH) || \

+                                        ((INSTANCE) == GPIOI) || \

+                                        ((INSTANCE) == GPIOJ) || \

+                                        ((INSTANCE) == GPIOK))

+

+/******************************* GPIO AF Instances ****************************/

+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)

+

+/**************************** GPIO Lock Instances *****************************/

+/* On H7, all GPIO Bank support the Lock mechanism */

+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)

+

+/******************************** HSEM Instances *******************************/

+#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)

+#define HSEM_CPU1_COREID         (0x00000003U) /* Semaphore Core CM7 ID */

+#define HSEM_CR_COREID_CPU1      (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)

+#define HSEM_CR_COREID_CURRENT   (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)

+

+#define HSEM_SEMID_MIN     (0U)       /* HSEM ID Min*/

+#define HSEM_SEMID_MAX     (31U)      /* HSEM ID Max */

+

+#define HSEM_PROCESSID_MIN (0U)       /* HSEM Process ID Min */

+#define HSEM_PROCESSID_MAX (255U)     /* HSEM Process ID Max */

+

+#define HSEM_CLEAR_KEY_MIN (0U)       /* HSEM clear Key Min value */

+#define HSEM_CLEAR_KEY_MAX (0xFFFFU)  /* HSEM clear Key Max value */

+

+/******************************** I2C Instances *******************************/

+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

+                                       ((INSTANCE) == I2C2) || \

+                                       ((INSTANCE) == I2C3) || \

+                                       ((INSTANCE) == I2C4))

+/************** I2C Instances : wakeup capability from stop modes *************/

+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)

+

+/****************************** SMBUS Instances *******************************/

+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

+                                         ((INSTANCE) == I2C2) || \

+                                         ((INSTANCE) == I2C3) || \

+                                         ((INSTANCE) == I2C4))

+/******************************** I2S Instances *******************************/

+#define IS_I2S_ALL_INSTANCE(INSTANCE)   (((INSTANCE) == SPI1) || \

+                                         ((INSTANCE) == SPI2) || \

+                                         ((INSTANCE) == SPI3))

+

+/****************************** LTDC Instances ********************************/

+#define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)

+

+/******************************* RNG Instances ********************************/

+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)

+

+/****************************** RTC Instances *********************************/

+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)

+

+/****************************** SDMMC Instances *********************************/

+#define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \

+                                           ((_INSTANCE_) == SDMMC2))

+

+/******************************** SMBUS Instances *****************************/

+#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)

+

+/******************************** SPI Instances *******************************/

+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \

+                                       ((INSTANCE) == SPI2) || \

+                                       ((INSTANCE) == SPI3) || \

+                                       ((INSTANCE) == SPI4) || \

+                                       ((INSTANCE) == SPI5) || \

+                                       ((INSTANCE) == SPI6))

+

+#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \

+                                           ((INSTANCE) == SPI2) || \

+                                           ((INSTANCE) == SPI3))

+

+/******************************** SWPMI Instances *****************************/

+#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)

+

+/****************** LPTIM Instances : All supported instances *****************/

+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \

+                                         ((INSTANCE) == LPTIM2) || \

+                                         ((INSTANCE) == LPTIM3) || \

+                                         ((INSTANCE) == LPTIM4) || \

+                                         ((INSTANCE) == LPTIM5))

+

+/****************** LPTIM Instances : supporting encoder interface **************/

+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \

+                                                           ((INSTANCE) == LPTIM2))

+

+/****************** TIM Instances : All supported instances *******************/

+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM6)   || \

+                                         ((INSTANCE) == TIM7)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM13)  || \

+                                         ((INSTANCE) == TIM14)  || \

+                                         ((INSTANCE) == TIM15)  || \

+                                         ((INSTANCE) == TIM16)  || \

+                                         ((INSTANCE) == TIM17))

+

+/************* TIM Instances : at least 1 capture/compare channel *************/

+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM13)  || \

+                                         ((INSTANCE) == TIM14)  || \

+                                         ((INSTANCE) == TIM15)  || \

+                                         ((INSTANCE) == TIM16)  || \

+                                         ((INSTANCE) == TIM17))

+

+/************ TIM Instances : at least 2 capture/compare channels *************/

+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM15))

+

+/************ TIM Instances : at least 3 capture/compare channels *************/

+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8))

+

+/************ TIM Instances : at least 4 capture/compare channels *************/

+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8))

+

+/************ TIM Instances : at least 5 capture/compare channels *************/

+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM8))

+/************ TIM Instances : at least 6 capture/compare channels *************/

+#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM8))

+

+/******************** TIM Instances : Advanced-control timers *****************/

+#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \

+                                                ((__INSTANCE__) == TIM8))

+

+/******************** TIM Instances : Advanced-control timers *****************/

+

+/******************* TIM Instances : Timer input XOR function *****************/

+#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : DMA requests generation (UDE) *************/

+#define IS_TIM_DMA_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM6)   || \

+                                           ((INSTANCE) == TIM7)   || \

+                                           ((INSTANCE) == TIM8)   || \

+                                           ((INSTANCE) == TIM15)  || \

+                                           ((INSTANCE) == TIM16)  || \

+                                           ((INSTANCE) == TIM17))

+

+/************ TIM Instances : DMA requests generation (CCxDE) *****************/

+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15)  || \

+                                            ((INSTANCE) == TIM16)  || \

+                                            ((INSTANCE) == TIM17))

+

+/************ TIM Instances : DMA requests generation (COMDE) *****************/

+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15))

+

+/******************** TIM Instances : DMA burst feature ***********************/

+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8))

+

+/*************** TIM Instances : external trigger reamp input available *******/

+#define IS_TIM_ETR_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : remapping capability **********************/

+#define IS_TIM_REMAP_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \

+                                          ((INSTANCE) == TIM2)  || \

+                                          ((INSTANCE) == TIM3)  || \

+                                          ((INSTANCE) == TIM5)  || \

+                                          ((INSTANCE) == TIM8)  || \

+                                          ((INSTANCE) == TIM16) || \

+                                          ((INSTANCE) == TIM17))

+

+/*************** TIM Instances : external trigger reamp input available *******/

+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                              ((INSTANCE) == TIM2)   || \

+                                              ((INSTANCE) == TIM3)   || \

+                                              ((INSTANCE) == TIM5)   || \

+                                              ((INSTANCE) == TIM8))

+

+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/

+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM6)   || \

+                                            ((INSTANCE) == TIM7)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15))

+

+/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/

+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM8)   || \

+                                           ((INSTANCE) == TIM12))

+

+/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/

+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM8))

+

+/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/

+#define IS_TIM_TISEL_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)   || \

+                                          ((INSTANCE) == TIM2)   || \

+                                          ((INSTANCE) == TIM3)   || \

+                                          ((INSTANCE) == TIM4)   || \

+                                          ((INSTANCE) == TIM5)   || \

+                                          ((INSTANCE) == TIM8)   || \

+                                          ((INSTANCE) == TIM15)  || \

+                                          ((INSTANCE) == TIM16)  || \

+                                          ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting commutation event *************/

+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \

+                                                     ((INSTANCE) == TIM8)    || \

+                                                     ((INSTANCE) == TIM15)   || \

+                                                     ((INSTANCE) == TIM16)   || \

+                                                     ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting encoder interface **************/

+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1)  || \

+                                                      ((__INSTANCE__) == TIM2)      || \

+                                                      ((__INSTANCE__) == TIM3)      || \

+                                                      ((__INSTANCE__) == TIM4)      || \

+                                                      ((__INSTANCE__) == TIM5)      || \

+                                                      ((__INSTANCE__) == TIM8))

+

+/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/

+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                                       ((INSTANCE) == TIM8))

+/******************* TIM Instances : output(s) available **********************/

+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \

+    ((((INSTANCE) == TIM1) &&                  \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4) ||          \

+      ((CHANNEL) == TIM_CHANNEL_5) ||          \

+      ((CHANNEL) == TIM_CHANNEL_6)))           \

+     ||                                        \

+     (((INSTANCE) == TIM2) &&                  \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM3) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1)||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM4) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM5) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM8) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4) ||          \

+      ((CHANNEL) == TIM_CHANNEL_5) ||          \

+      ((CHANNEL) == TIM_CHANNEL_6)))           \

+  ||                                           \

+     (((INSTANCE) == TIM12) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2)))           \

+  ||                                           \

+     (((INSTANCE) == TIM13) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM14) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM15) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+     ((CHANNEL) == TIM_CHANNEL_2)))            \

+  ||                                           \

+     (((INSTANCE) == TIM16) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM17) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1))))

+

+/****************** TIM Instances : supporting the break function *************/

+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\

+      (((INSTANCE) == TIM1)    || \

+      ((INSTANCE) == TIM8)     || \

+       ((INSTANCE) == TIM15)   || \

+       ((INSTANCE) == TIM16)   || \

+       ((INSTANCE) == TIM17))

+

+/************** TIM Instances : supporting Break source selection *************/

+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \

+                                               ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting complementary output(s) ********/

+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \

+   ((((INSTANCE) == TIM1) &&                    \

+     (((CHANNEL) == TIM_CHANNEL_1) ||           \

+      ((CHANNEL) == TIM_CHANNEL_2) ||           \

+      ((CHANNEL) == TIM_CHANNEL_3)))            \

+ ||                                             \

+      (((INSTANCE) == TIM8) &&                  \

+      (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||           \

+      ((CHANNEL) == TIM_CHANNEL_3)))            \

+    ||                                          \

+    (((INSTANCE) == TIM15) &&                   \

+      ((CHANNEL) == TIM_CHANNEL_1))             \

+    ||                                          \

+    (((INSTANCE) == TIM16) &&                   \

+     ((CHANNEL) == TIM_CHANNEL_1))              \

+    ||                                          \

+    (((INSTANCE) == TIM17) &&                   \

+     ((CHANNEL) == TIM_CHANNEL_1)))

+

+/****************** TIM Instances : supporting counting mode selection ********/

+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting repetition counter *************/

+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15)   || \

+   ((INSTANCE) == TIM16)   || \

+   ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting synchronization ****************/

+#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\

+    (((__INSTANCE__) == TIM1)    || \

+     ((__INSTANCE__) == TIM2)    || \

+     ((__INSTANCE__) == TIM3)    || \

+     ((__INSTANCE__) == TIM4)    || \

+     ((__INSTANCE__) == TIM5)    || \

+     ((__INSTANCE__) == TIM6)    || \

+     ((__INSTANCE__) == TIM8)    || \

+     ((__INSTANCE__) == TIM12)   || \

+     ((__INSTANCE__) == TIM15))

+

+/****************** TIM Instances : supporting clock division *****************/

+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15)   || \

+   ((INSTANCE) == TIM16)   || \

+   ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting external clock mode 1 for ETRF input */

+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting external clock mode 2 **********/

+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\

+ (((INSTANCE) == TIM1)     || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/

+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/

+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : supporting OCxREF clear *******************/

+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3))

+

+/****************** TIM Instances : TIM_32B_COUNTER ***************************/

+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM5))

+

+/****************** TIM Instances : TIM_BKIN2 ***************************/

+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting Hall sensor interface **********/

+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)  || \

+                                                             ((__INSTANCE__) == TIM2)  || \

+                                                             ((__INSTANCE__) == TIM3)  || \

+                                                             ((__INSTANCE__) == TIM4)  || \

+                                                             ((__INSTANCE__) == TIM5)  || \

+                                                             ((__INSTANCE__) == TIM15) || \

+                                                             ((__INSTANCE__) == TIM8))

+

+/****************************** HRTIM Instances *******************************/

+#define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))

+

+/******************** USART Instances : Synchronous mode **********************/

+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                     ((INSTANCE) == USART2) || \

+                                     ((INSTANCE) == USART3) || \

+                                     ((INSTANCE) == USART6))

+

+/******************** USART Instances : SPI slave mode ************************/

+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                              ((INSTANCE) == USART2) || \

+                                              ((INSTANCE) == USART3) || \

+                                              ((INSTANCE) == USART6))

+

+/******************** UART Instances : Asynchronous mode **********************/

+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                    ((INSTANCE) == USART2) || \

+                                    ((INSTANCE) == USART3) || \

+                                    ((INSTANCE) == UART4)  || \

+                                    ((INSTANCE) == UART5)  || \

+                                    ((INSTANCE) == USART6) || \

+                                    ((INSTANCE) == UART7)  || \

+                                    ((INSTANCE) == UART8))

+

+/******************** UART Instances : FIFO mode.******************************/

+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                         ((INSTANCE) == USART2) || \

+                                         ((INSTANCE) == USART3) || \

+                                         ((INSTANCE) == UART4)  || \

+                                         ((INSTANCE) == UART5)  || \

+                                         ((INSTANCE) == USART6) || \

+                                         ((INSTANCE) == UART7)  || \

+                                         ((INSTANCE) == UART8))

+

+/****************** UART Instances : Auto Baud Rate detection *****************/

+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                            ((INSTANCE) == USART2) || \

+                                                            ((INSTANCE) == USART3) || \

+                                                            ((INSTANCE) == UART4)  || \

+                                                            ((INSTANCE) == UART5)  || \

+                                                            ((INSTANCE) == USART6) || \

+                                                            ((INSTANCE) == UART7)  || \

+                                                            ((INSTANCE) == UART8))

+

+/*********************** UART Instances : Driver Enable ***********************/

+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                  ((INSTANCE) == USART2) || \

+                                                  ((INSTANCE) == USART3) || \

+                                                  ((INSTANCE) == UART4)  || \

+                                                  ((INSTANCE) == UART5)  || \

+                                                  ((INSTANCE) == USART6) || \

+                                                  ((INSTANCE) == UART7)  || \

+                                                  ((INSTANCE) == UART8)  || \

+                                                  ((INSTANCE) == LPUART1))

+

+/********************* UART Instances : Half-Duplex mode **********************/

+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                               ((INSTANCE) == USART2) || \

+                                               ((INSTANCE) == USART3) || \

+                                               ((INSTANCE) == UART4)  || \

+                                               ((INSTANCE) == UART5)  || \

+                                               ((INSTANCE) == USART6) || \

+                                               ((INSTANCE) == UART7)  || \

+                                               ((INSTANCE) == UART8)  || \

+                                               ((INSTANCE) == LPUART1))

+

+/******************* UART Instances : Hardware Flow control *******************/

+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                           ((INSTANCE) == USART2) || \

+                                           ((INSTANCE) == USART3) || \

+                                           ((INSTANCE) == UART4)  || \

+                                           ((INSTANCE) == UART5)  || \

+                                           ((INSTANCE) == USART6) || \

+                                           ((INSTANCE) == UART7)  || \

+                                           ((INSTANCE) == UART8)  || \

+                                           ((INSTANCE) == LPUART1))

+

+/************************* UART Instances : LIN mode **************************/

+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                        ((INSTANCE) == USART2) || \

+                                        ((INSTANCE) == USART3) || \

+                                        ((INSTANCE) == UART4)  || \

+                                        ((INSTANCE) == UART5)  || \

+                                        ((INSTANCE) == USART6) || \

+                                        ((INSTANCE) == UART7)  || \

+                                        ((INSTANCE) == UART8))

+

+/****************** UART Instances : Wake-up from Stop mode *******************/

+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                    ((INSTANCE) == USART2) || \

+                                                    ((INSTANCE) == USART3) || \

+                                                    ((INSTANCE) == UART4)  || \

+                                                    ((INSTANCE) == UART5)  || \

+                                                    ((INSTANCE) == USART6) || \

+                                                    ((INSTANCE) == UART7)  || \

+                                                    ((INSTANCE) == UART8)  || \

+                                                    ((INSTANCE) == LPUART1))

+

+/************************* UART Instances : IRDA mode *************************/

+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                    ((INSTANCE) == USART2) || \

+                                    ((INSTANCE) == USART3) || \

+                                    ((INSTANCE) == UART4)  || \

+                                    ((INSTANCE) == UART5)  || \

+                                    ((INSTANCE) == USART6) || \

+                                    ((INSTANCE) == UART7)  || \

+                                    ((INSTANCE) == UART8))

+

+/********************* USART Instances : Smard card mode **********************/

+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                         ((INSTANCE) == USART2) || \

+                                         ((INSTANCE) == USART3) || \

+                                         ((INSTANCE) == USART6))

+

+/****************************** LPUART Instance *******************************/

+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)

+

+/****************************** IWDG Instances ********************************/

+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG1)

+/****************************** USB Instances ********************************/

+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)

+

+/****************************** WWDG Instances ********************************/

+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG1)

+/****************************** MDIOS Instances ********************************/

+#define IS_MDIOS_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == MDIOS)

+

+/****************************** CEC Instances *********************************/

+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)

+

+/****************************** SAI Instances ********************************/

+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \

+                    ((INSTANCE) == SAI1_Block_B) || \

+                     ((INSTANCE) == SAI2_Block_A) || \

+                     ((INSTANCE) == SAI2_Block_B) || \

+                     ((INSTANCE) == SAI3_Block_A) || \

+                     ((INSTANCE) == SAI3_Block_B) || \

+                     ((INSTANCE) == SAI4_Block_A) || \

+                     ((INSTANCE) == SAI4_Block_B))

+

+/****************************** SPDIFRX Instances ********************************/

+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)

+

+/****************************** OPAMP Instances *******************************/

+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \

+                                         ((INSTANCE) == OPAMP2))

+

+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)

+

+/*********************** USB OTG PCD Instances ********************************/

+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \

+                                        ((INSTANCE) == USB_OTG_HS))

+

+/*********************** USB OTG HCD Instances ********************************/

+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \

+                                       ((INSTANCE) == USB_OTG_HS))

+

+/******************************************************************************/

+/*  For a painless codes migration between the STM32H7xx device product       */

+/*  lines, or with STM32F7xx devices the aliases defined below are put        */

+/*   in place to overcome the differences in the interrupt handlers and IRQn  */

+/*   definitions. No need to update developed interrupt code when moving      */

+/*  across product lines within the same STM32H7 Family                       */

+/******************************************************************************/

+

+/* Aliases for __IRQn */

+#define  HASH_RNG_IRQn                  RNG_IRQn

+#define  TIM1_BRK_TIM9_IRQn             TIM1_BRK_IRQn

+#define  TIM1_UP_TIM10_IRQn             TIM1_UP_IRQn

+#define  TIM1_TRG_COM_TIM11_IRQn        TIM1_TRG_COM_IRQn

+#define  PVD_IRQn                       PVD_AVD_IRQn

+

+

+

+/* Aliases for __IRQHandler */

+#define  HASH_RNG_IRQHandler           RNG_IRQHandler

+#define TIM1_BRK_TIM9_IRQHandler       TIM1_BRK_IRQHandler

+#define TIM1_UP_TIM9_IRQHandler        TIM1_UP_IRQHandler

+#define TIM1_TRG_COM_TIM11_IRQHandler  TIM1_TRG_COM_IRQHandler

+#define PVD_IRQHandler                 PVD_AVD_IRQHandler

+

+/* Aliases for COMP __IRQHandler */

+#define COMP_IRQHandler                COMP1_IRQHandler

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif /* __cplusplus */

+

+#endif /* STM32H743xx_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h745xx.h b/bsps/arm/stm32h7/include/stm32h745xx.h
new file mode 100644
index 0000000000..614dcb0799
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h745xx.h
@@ -0,0 +1,27061 @@
+/**

+  ******************************************************************************

+  * @file    stm32h745xx.h

+  * @author  MCD Application Team

+  * @brief   CMSIS STM32H745xx Device Peripheral Access Layer Header File.

+  *

+  *          This file contains:

+  *           - Data structures and the address mapping for all peripherals

+  *           - Peripheral's registers declarations and bits definition

+  *           - Macros to access peripheral's registers hardware

+  *

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/** @addtogroup CMSIS_Device

+  * @{

+  */

+

+/** @addtogroup stm32h745xx

+  * @{

+  */

+

+#ifndef STM32H745xx_H

+#define STM32H745xx_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif /* __cplusplus */

+

+/** @addtogroup Peripheral_interrupt_number_definition

+  * @{

+  */

+

+/**

+ * @brief STM32H7XX Interrupt Number Definition, according to the selected device

+ *        in @ref Library_configuration_section

+ */

+typedef enum

+{

+/******  Cortex-M Processor Exceptions Numbers *****************************************************************/

+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */

+  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */

+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */

+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */

+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */

+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M SV Call Interrupt                                     */

+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M Debug Monitor Interrupt                               */

+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M Pend SV Interrupt                                     */

+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M System Tick Interrupt                                 */

+/******  STM32 specific Interrupt Numbers **********************************************************************/

+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)                   */

+  PVD_AVD_IRQn                = 1,      /*!< PVD/AVD through EXTI Line detection Interrupt                     */

+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */

+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */

+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */

+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */

+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */

+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */

+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */

+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */

+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */

+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */

+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */

+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */

+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */

+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */

+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */

+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */

+  ADC_IRQn                    = 18,     /*!< ADC1 and  ADC2 global Interrupts                                  */

+  FDCAN1_IT0_IRQn             = 19,     /*!< FDCAN1 Interrupt line 0                                           */

+  FDCAN2_IT0_IRQn             = 20,     /*!< FDCAN2 Interrupt line 0                                           */

+  FDCAN1_IT1_IRQn             = 21,     /*!< FDCAN1 Interrupt line 1                                           */

+  FDCAN2_IT1_IRQn             = 22,     /*!< FDCAN2 Interrupt line 1                                           */

+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */

+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                              */

+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                             */

+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt                            */

+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */

+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */

+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */

+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */

+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */

+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */

+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */

+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */

+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */

+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */

+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */

+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */

+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */

+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */

+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */

+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */

+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */

+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */

+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */

+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */

+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */

+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */

+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */

+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */

+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */

+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */

+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */

+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */

+  DMA2_Stream0_IRQn           = 56,     /*!<   DMA2 Stream 0 global Interrupt                                  */

+  DMA2_Stream1_IRQn           = 57,     /*!<   DMA2 Stream 1 global Interrupt                                  */

+  DMA2_Stream2_IRQn           = 58,     /*!<   DMA2 Stream 2 global Interrupt                                  */

+  DMA2_Stream3_IRQn           = 59,     /*!<   DMA2 Stream 3 global Interrupt                                  */

+  DMA2_Stream4_IRQn           = 60,     /*!<   DMA2 Stream 4 global Interrupt                                  */

+  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */

+  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */

+  FDCAN_CAL_IRQn              = 63,     /*!< FDCAN Calibration unit Interrupt                                  */

+  CM7_SEV_IRQn                = 64,     /*!< CM7 Send event interrupt for CM4                                  */

+  CM4_SEV_IRQn                = 65,     /*!< CM4 Send event interrupt for CM7                                  */

+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */

+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */

+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */

+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */

+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */

+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */

+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */

+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */

+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */

+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */

+  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */

+  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */

+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */

+  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */

+  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */

+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */

+  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */

+  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */

+  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */

+  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */

+  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */

+  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */

+  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */

+  QUADSPI_IRQn                = 92,     /*!< Quad SPI global interrupt                                         */

+  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */

+  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */

+  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */

+  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */

+  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */

+  OTG_FS_EP1_OUT_IRQn         = 98,     /*!< USB OTG HS2 global interrupt                                      */

+  OTG_FS_EP1_IN_IRQn          = 99,     /*!< USB OTG HS2 End Point 1 Out global interrupt                      */

+  OTG_FS_WKUP_IRQn            = 100,    /*!< USB OTG HS2 End Point 1 In global interrupt                       */

+  OTG_FS_IRQn                 = 101,    /*!< USB OTG HS2 Wakeup through EXTI interrupt                         */

+  DMAMUX1_OVR_IRQn            = 102,    /*!<DMAMUX1 Overrun interrupt                                          */

+  HRTIM1_Master_IRQn          = 103,    /*!< HRTIM Master Timer global Interrupts                              */

+  HRTIM1_TIMA_IRQn            = 104,    /*!< HRTIM Timer A global Interrupt                                    */

+  HRTIM1_TIMB_IRQn            = 105,    /*!< HRTIM Timer B global Interrupt                                    */

+  HRTIM1_TIMC_IRQn            = 106,    /*!< HRTIM Timer C global Interrupt                                    */

+  HRTIM1_TIMD_IRQn            = 107,    /*!< HRTIM Timer D global Interrupt                                    */

+  HRTIM1_TIME_IRQn            = 108,    /*!< HRTIM Timer E global Interrupt                                    */

+  HRTIM1_FLT_IRQn             = 109,    /*!< HRTIM Fault global Interrupt                                      */

+  DFSDM1_FLT0_IRQn            = 110,    /*!<DFSDM Filter1 Interrupt                                            */

+  DFSDM1_FLT1_IRQn            = 111,    /*!<DFSDM Filter2 Interrupt                                            */

+  DFSDM1_FLT2_IRQn            = 112,    /*!<DFSDM Filter3 Interrupt                                            */

+  DFSDM1_FLT3_IRQn            = 113,    /*!<DFSDM Filter4 Interrupt                                            */

+  SAI3_IRQn                   = 114,    /*!< SAI3 global Interrupt                                             */

+  SWPMI1_IRQn                 = 115,    /*!< Serial Wire Interface 1 global interrupt                          */

+  TIM15_IRQn                  = 116,    /*!< TIM15 global Interrupt                                            */

+  TIM16_IRQn                  = 117,    /*!< TIM16 global Interrupt                                            */

+  TIM17_IRQn                  = 118,    /*!< TIM17 global Interrupt                                            */

+  MDIOS_WKUP_IRQn             = 119,    /*!< MDIOS Wakeup  Interrupt                                           */

+  MDIOS_IRQn                  = 120,    /*!< MDIOS global Interrupt                                            */

+  JPEG_IRQn                   = 121,    /*!< JPEG global Interrupt                                             */

+  MDMA_IRQn                   = 122,    /*!< MDMA global Interrupt                                             */

+  SDMMC2_IRQn                 = 124,    /*!< SDMMC2 global Interrupt                                           */

+  HSEM1_IRQn                  = 125,    /*!< HSEM1 global Interrupt                                            */

+  HSEM2_IRQn                  = 126,    /*!< HSEM2 global Interrupt                                            */

+  ADC3_IRQn                   = 127,    /*!< ADC3 global Interrupt                                             */

+  DMAMUX2_OVR_IRQn            = 128,    /*!<DMAMUX2 Overrun interrupt                                          */

+  BDMA_Channel0_IRQn          = 129,    /*!< BDMA Channel 0 global Interrupt                                   */

+  BDMA_Channel1_IRQn          = 130,    /*!< BDMA Channel 1 global Interrupt                                   */

+  BDMA_Channel2_IRQn          = 131,    /*!< BDMA Channel 2 global Interrupt                                   */

+  BDMA_Channel3_IRQn          = 132,    /*!< BDMA Channel 3 global Interrupt                                   */

+  BDMA_Channel4_IRQn          = 133,    /*!< BDMA Channel 4 global Interrupt                                   */

+  BDMA_Channel5_IRQn          = 134,    /*!< BDMA Channel 5 global Interrupt                                   */

+  BDMA_Channel6_IRQn          = 135,    /*!< BDMA Channel 6 global Interrupt                                   */

+  BDMA_Channel7_IRQn          = 136,    /*!< BDMA Channel 7 global Interrupt                                   */

+  COMP_IRQn                   = 137 ,   /*!< COMP global Interrupt                                             */

+  LPTIM2_IRQn                 = 138,    /*!< LP TIM2 global interrupt                                          */

+  LPTIM3_IRQn                 = 139,    /*!< LP TIM3 global interrupt                                          */

+  LPTIM4_IRQn                 = 140,    /*!< LP TIM4 global interrupt                                          */

+  LPTIM5_IRQn                 = 141,    /*!< LP TIM5 global interrupt                                          */

+  LPUART1_IRQn                = 142,    /*!< LP UART1 interrupt                                                */

+  WWDG_RST_IRQn               = 143,    /*!<Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */

+  CRS_IRQn                    = 144,    /*!< Clock Recovery Global Interrupt                                   */

+  ECC_IRQn                    = 145,    /*!< ECC diagnostic Global Interrupt                                   */

+  SAI4_IRQn                   = 146,    /*!< SAI4 global interrupt                                             */

+  HOLD_CORE_IRQn              = 148,    /*!< Hold core interrupt                                               */

+  WAKEUP_PIN_IRQn             = 149,    /*!< Interrupt for all 6 wake-up pins                                  */

+} IRQn_Type;

+

+/**

+  * @}

+  */

+

+/** @addtogroup Configuration_section_for_CMSIS

+  * @{

+  */

+#define DUAL_CORE  /*!< Dual core line feature */

+

+#define SMPS       /*!< Switched mode power supply feature */

+

+

+

+/**

+  * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals

+   */

+#ifdef CORE_CM4

+#define __CM4_REV                 0x0001  /*!< Cortex-M4 revision r0p1                       */

+#define __MPU_PRESENT             1       /*!< CM4 provides an MPU                           */

+#define __NVIC_PRIO_BITS          4       /*!< CM4 uses 4 Bits for the Priority Levels       */

+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */

+#define __FPU_PRESENT             1       /*!< FPU present                                   */

+

+#include "core_cm4.h"                     /*!< Cortex-M4 processor and core peripherals      */

+#else  /* CORE_CM7 */

+#ifdef CORE_CM7

+#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */

+#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */

+#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */

+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */

+#define __FPU_PRESENT             1       /*!< FPU present                                   */

+#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */

+#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */

+#include "core_cm7.h"                 /*!< Cortex-M7 processor and core peripherals          */

+#else  /* UNKNOWN_CORE */

+#error Please #define CORE_CM4 or CORE_CM7

+#endif /* CORE_CM7 */

+#endif /* CORE_CM4 */

+

+/**

+  * @}

+  */

+

+

+

+

+

+#include "system_stm32h7xx.h"

+#include <stdint.h>

+

+/** @addtogroup Peripheral_registers_structures

+  * @{

+  */

+

+/**

+  * @brief Analog to Digital Converter

+  */

+

+typedef struct

+{

+  __IO uint32_t ISR;              /*!< ADC Interrupt and Status Register,                          Address offset: 0x00 */

+  __IO uint32_t IER;              /*!< ADC Interrupt Enable Register,                              Address offset: 0x04 */

+  __IO uint32_t CR;               /*!< ADC control register,                                       Address offset: 0x08 */

+  __IO uint32_t CFGR;             /*!< ADC Configuration register,                                 Address offset: 0x0C */

+  __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                               Address offset: 0x10 */

+  __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                                 Address offset: 0x14 */

+  __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                                 Address offset: 0x18 */

+  __IO uint32_t PCSEL;            /*!< ADC pre-channel selection,                                  Address offset: 0x1C */

+  __IO uint32_t LTR1;             /*!< ADC watchdog Lower threshold register 1,                    Address offset: 0x20 */

+  __IO uint32_t HTR1;             /*!< ADC watchdog higher threshold register 1,                   Address offset: 0x24 */

+  uint32_t      RESERVED1;        /*!< Reserved, 0x028                                                                  */

+  uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                                  */

+  __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                            Address offset: 0x30 */

+  __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                            Address offset: 0x34 */

+  __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                            Address offset: 0x38 */

+  __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                            Address offset: 0x3C */

+  __IO uint32_t DR;               /*!< ADC regular data register,                                  Address offset: 0x40 */

+  uint32_t      RESERVED3;        /*!< Reserved, 0x044                                                                  */

+  uint32_t      RESERVED4;        /*!< Reserved, 0x048                                                                  */

+  __IO uint32_t JSQR;             /*!< ADC injected sequence register,                             Address offset: 0x4C */

+  uint32_t      RESERVED5[4];     /*!< Reserved, 0x050 - 0x05C                                                          */

+  __IO uint32_t OFR1;             /*!< ADC offset register 1,                                      Address offset: 0x60 */

+  __IO uint32_t OFR2;             /*!< ADC offset register 2,                                      Address offset: 0x64 */

+  __IO uint32_t OFR3;             /*!< ADC offset register 3,                                      Address offset: 0x68 */

+  __IO uint32_t OFR4;             /*!< ADC offset register 4,                                      Address offset: 0x6C */

+  uint32_t      RESERVED6[4];     /*!< Reserved, 0x070 - 0x07C                                                          */

+  __IO uint32_t JDR1;             /*!< ADC injected data register 1,                               Address offset: 0x80 */

+  __IO uint32_t JDR2;             /*!< ADC injected data register 2,                               Address offset: 0x84 */

+  __IO uint32_t JDR3;             /*!< ADC injected data register 3,                               Address offset: 0x88 */

+  __IO uint32_t JDR4;             /*!< ADC injected data register 4,                               Address offset: 0x8C */

+  uint32_t      RESERVED7[4];     /*!< Reserved, 0x090 - 0x09C                                                          */

+  __IO uint32_t AWD2CR;           /*!< ADC  Analog Watchdog 2 Configuration Register,              Address offset: 0xA0 */

+  __IO uint32_t AWD3CR;           /*!< ADC  Analog Watchdog 3 Configuration Register,              Address offset: 0xA4 */

+  uint32_t      RESERVED8;        /*!< Reserved, 0x0A8                                                                  */

+  uint32_t      RESERVED9;        /*!< Reserved, 0x0AC                                                                  */

+  __IO uint32_t LTR2;             /*!< ADC watchdog Lower threshold register 2,                    Address offset: 0xB0 */

+  __IO uint32_t HTR2;             /*!< ADC watchdog Higher threshold register 2,                   Address offset: 0xB4 */

+  __IO uint32_t LTR3;             /*!< ADC watchdog Lower threshold register 3,                    Address offset: 0xB8 */

+  __IO uint32_t HTR3;             /*!< ADC watchdog Higher threshold register 3,                   Address offset: 0xBC */

+  __IO uint32_t DIFSEL;           /*!< ADC  Differential Mode Selection Register,                  Address offset: 0xC0 */

+  __IO uint32_t CALFACT;          /*!< ADC  Calibration Factors,                                   Address offset: 0xC4 */

+  __IO uint32_t CALFACT2;         /*!< ADC  Linearity Calibration Factors,                         Address offset: 0xC8 */

+} ADC_TypeDef;

+

+

+typedef struct

+{

+__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */

+uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */

+__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */

+__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */

+__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */

+

+} ADC_Common_TypeDef;

+

+/**

+  * @brief ART

+  */

+

+typedef struct

+{

+  __IO uint32_t  CTR;        /*!< ART accelerator - control register */

+}ART_TypeDef;

+

+/**

+  * @brief VREFBUF

+  */

+

+typedef struct

+{

+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */

+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */

+} VREFBUF_TypeDef;

+

+

+/**

+  * @brief FD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */

+  __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */

+  __IO uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */

+  __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */

+  __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */

+  __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */

+  __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */

+  __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */

+  __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */

+  __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */

+  __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */

+  __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */

+  __IO uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */

+  __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */

+  __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */

+  __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */

+  __IO uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */

+  __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */

+  __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */

+  __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */

+  __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */

+  __IO uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */

+  __IO uint32_t GFC;          /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */

+  __IO uint32_t SIDFC;        /*!< FDCAN Standard ID Filter Configuration register,                 Address offset: 0x084 */

+  __IO uint32_t XIDFC;        /*!< FDCAN Extended ID Filter Configuration register,                 Address offset: 0x088 */

+  __IO uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */

+  __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x090 */

+  __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x094 */

+  __IO uint32_t NDAT1;        /*!< FDCAN New Data 1 register,                                       Address offset: 0x098 */

+  __IO uint32_t NDAT2;        /*!< FDCAN New Data 2 register,                                       Address offset: 0x09C */

+  __IO uint32_t RXF0C;        /*!< FDCAN Rx FIFO 0 Configuration register,                          Address offset: 0x0A0 */

+  __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x0A4 */

+  __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x0A8 */

+  __IO uint32_t RXBC;         /*!< FDCAN Rx Buffer Configuration register,                          Address offset: 0x0AC */

+  __IO uint32_t RXF1C;        /*!< FDCAN Rx FIFO 1 Configuration register,                          Address offset: 0x0B0 */

+  __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x0B4 */

+  __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x0B8 */

+  __IO uint32_t RXESC;        /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register,        Address offset: 0x0BC */

+  __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */

+  __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */

+  __IO uint32_t TXESC;        /*!< FDCAN Tx Buffer Element Size Configuration register,             Address offset: 0x0C8 */

+  __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0CC */

+  __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0D0 */

+  __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D4 */

+  __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D8 */

+  __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0DC */

+  __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0E0 */

+  __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */

+  __IO uint32_t RESERVED6[2]; /*!< Reserved,                                                                0x0E8 - 0x0EC */

+  __IO uint32_t TXEFC;        /*!< FDCAN Tx Event FIFO Configuration register,                      Address offset: 0x0F0 */

+  __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0F4 */

+  __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0F8 */

+  __IO uint32_t RESERVED7;    /*!< Reserved,                                                                        0x0FC */

+} FDCAN_GlobalTypeDef;

+

+/**

+  * @brief TTFD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t TTTMC;          /*!< TT Trigger Memory Configuration register,    Address offset: 0x100 */

+  __IO uint32_t TTRMC;          /*!< TT Reference Message Configuration register, Address offset: 0x104 */

+  __IO uint32_t TTOCF;          /*!< TT Operation Configuration register,         Address offset: 0x108 */

+  __IO uint32_t TTMLM;          /*!< TT Matrix Limits register,                   Address offset: 0x10C */

+  __IO uint32_t TURCF;          /*!< TUR Configuration register,                  Address offset: 0x110 */

+  __IO uint32_t TTOCN;          /*!< TT Operation Control register,               Address offset: 0x114 */

+  __IO uint32_t TTGTP;          /*!< TT Global Time Preset register,              Address offset: 0x118 */

+  __IO uint32_t TTTMK;          /*!< TT Time Mark register,                       Address offset: 0x11C */

+  __IO uint32_t TTIR;           /*!< TT Interrupt register,                       Address offset: 0x120 */

+  __IO uint32_t TTIE;           /*!< TT Interrupt Enable register,                Address offset: 0x124 */

+  __IO uint32_t TTILS;          /*!< TT Interrupt Line Select register,           Address offset: 0x128 */

+  __IO uint32_t TTOST;          /*!< TT Operation Status register,                Address offset: 0x12C */

+  __IO uint32_t TURNA;          /*!< TT TUR Numerator Actual register,            Address offset: 0x130 */

+  __IO uint32_t TTLGT;          /*!< TT Local and Global Time register,           Address offset: 0x134 */

+  __IO uint32_t TTCTC;          /*!< TT Cycle Time and Count register,            Address offset: 0x138 */

+  __IO uint32_t TTCPT;          /*!< TT Capture Time register,                    Address offset: 0x13C */

+  __IO uint32_t TTCSM;          /*!< TT Cycle Sync Mark register,                 Address offset: 0x140 */

+  __IO uint32_t RESERVED1[111]; /*!< Reserved,                                            0x144 - 0x2FC */

+  __IO uint32_t TTTS;           /*!< TT Trigger Select register,                  Address offset: 0x300 */

+} TTCAN_TypeDef;

+

+/**

+  * @brief FD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t CREL;  /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */

+  __IO uint32_t CCFG;  /*!< Calibration Configuration register,           Address offset: 0x04 */

+  __IO uint32_t CSTAT; /*!< Calibration Status register,                  Address offset: 0x08 */

+  __IO uint32_t CWD;   /*!< Calibration Watchdog register,                Address offset: 0x0C */

+  __IO uint32_t IR;    /*!< CCU Interrupt register,                       Address offset: 0x10 */

+  __IO uint32_t IE;    /*!< CCU Interrupt Enable register,                Address offset: 0x14 */

+} FDCAN_ClockCalibrationUnit_TypeDef;

+

+

+/**

+  * @brief Consumer Electronics Control

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;           /*!< CEC control register,              Address offset:0x00 */

+  __IO uint32_t CFGR;         /*!< CEC configuration register,        Address offset:0x04 */

+  __IO uint32_t TXDR;         /*!< CEC Tx data register ,             Address offset:0x08 */

+  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,              Address offset:0x0C */

+  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register, Address offset:0x10 */

+  __IO uint32_t IER;          /*!< CEC interrupt enable register,     Address offset:0x14 */

+}CEC_TypeDef;

+

+/**

+  * @brief CRC calculation unit

+  */

+

+typedef struct

+{

+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */

+  __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */

+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */

+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */

+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */

+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */

+} CRC_TypeDef;

+

+

+/**

+  * @brief Clock Recovery System

+  */

+typedef struct

+{

+__IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */

+__IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */

+__IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */

+__IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */

+} CRS_TypeDef;

+

+

+/**

+  * @brief Digital to Analog Converter

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */

+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */

+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */

+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */

+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */

+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */

+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */

+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */

+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */

+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */

+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */

+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */

+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */

+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */

+  __IO uint32_t CCR;      /*!< DAC calibration control register,                        Address offset: 0x38 */

+  __IO uint32_t MCR;      /*!< DAC mode control register,                               Address offset: 0x3C */

+  __IO uint32_t SHSR1;    /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */

+  __IO uint32_t SHSR2;    /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */

+  __IO uint32_t SHHR;     /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */

+  __IO uint32_t SHRR;     /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */

+} DAC_TypeDef;

+

+/**

+  * @brief DFSDM module registers

+  */

+typedef struct

+{

+  __IO uint32_t FLTCR1;          /*!< DFSDM control register1,                          Address offset: 0x100 */

+  __IO uint32_t FLTCR2;          /*!< DFSDM control register2,                          Address offset: 0x104 */

+  __IO uint32_t FLTISR;          /*!< DFSDM interrupt and status register,              Address offset: 0x108 */

+  __IO uint32_t FLTICR;          /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */

+  __IO uint32_t FLTJCHGR;        /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */

+  __IO uint32_t FLTFCR;          /*!< DFSDM filter control register,                    Address offset: 0x114 */

+  __IO uint32_t FLTJDATAR;       /*!< DFSDM data register for injected group,           Address offset: 0x118 */

+  __IO uint32_t FLTRDATAR;       /*!< DFSDM data register for regular group,            Address offset: 0x11C */

+  __IO uint32_t FLTAWHTR;        /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */

+  __IO uint32_t FLTAWLTR;        /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */

+  __IO uint32_t FLTAWSR;         /*!< DFSDM analog watchdog status register             Address offset: 0x128 */

+  __IO uint32_t FLTAWCFR;        /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */

+  __IO uint32_t FLTEXMAX;        /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */

+  __IO uint32_t FLTEXMIN;        /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */

+  __IO uint32_t FLTCNVTIMR;      /*!< DFSDM conversion timer,                           Address offset: 0x138 */

+} DFSDM_Filter_TypeDef;

+

+/**

+  * @brief DFSDM channel configuration registers

+  */

+typedef struct

+{

+  __IO uint32_t CHCFGR1;      /*!< DFSDM channel configuration register1,            Address offset: 0x00 */

+  __IO uint32_t CHCFGR2;      /*!< DFSDM channel configuration register2,            Address offset: 0x04 */

+  __IO uint32_t CHAWSCDR;     /*!< DFSDM channel analog watchdog and

+                                   short circuit detector register,                  Address offset: 0x08 */

+  __IO uint32_t CHWDATAR;     /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */

+  __IO uint32_t CHDATINR;     /*!< DFSDM channel data input register,                Address offset: 0x10 */

+} DFSDM_Channel_TypeDef;

+

+/**

+  * @brief Debug MCU

+  */

+typedef struct

+{

+  __IO uint32_t IDCODE;        /*!< MCU device ID code,                     Address offset: 0x00 */

+  __IO uint32_t CR;            /*!< Debug MCU configuration register,       Address offset: 0x04 */

+  __IO uint32_t  RESERVED4[11]; /*!< Reserved,                               Address offset: 0x08 */

+  __IO uint32_t APB3FZ1;     /*!< Debug MCU APB3FZ1 freeze register,    Address offset: 0x34 */

+  __IO uint32_t APB3FZ2;     /*!< Debug MCU APB3FZ2 freeze register,    Address offset: 0x38 */

+  __IO uint32_t APB1LFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x3C */

+  __IO uint32_t APB1LFZ2;    /*!< Debug MCU APB1LFZ2 freeze register,   Address offset: 0x40 */

+  __IO uint32_t APB1HFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x44 */

+  __IO uint32_t APB1HFZ2;    /*!< Debug MCU APB1LFZ2 freeze register,   Address offset: 0x48 */

+  __IO uint32_t APB2FZ1;     /*!< Debug MCU APB2FZ1 freeze register,    Address offset: 0x4C */

+  __IO uint32_t APB2FZ2;     /*!< Debug MCU APB2FZ2 freeze register,    Address offset: 0x50 */

+  __IO uint32_t APB4FZ1;     /*!< Debug MCU APB4FZ1 freeze register,    Address offset: 0x54 */

+  __IO uint32_t APB4FZ2;     /*!< Debug MCU APB4FZ2 freeze register,    Address offset: 0x58 */

+

+}DBGMCU_TypeDef;

+/**

+  * @brief DCMI

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */

+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */

+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */

+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */

+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */

+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */

+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */

+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */

+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */

+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */

+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */

+} DCMI_TypeDef;

+

+/**

+  * @brief DMA Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */

+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */

+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */

+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */

+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */

+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */

+} DMA_Stream_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */

+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */

+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */

+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */

+} DMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CCR;          /*!< DMA channel x configuration register          */

+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register         */

+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register     */

+  __IO uint32_t CM0AR;        /*!< DMA channel x memory 0 address register       */

+  __IO uint32_t CM1AR;        /*!< DMA channel x memory 1 address register       */

+} BDMA_Channel_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */

+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */

+} BDMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CCR;        /*!< DMA Multiplexer Channel x Control Register   */

+}DMAMUX_Channel_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CSR;      /*!< DMA Channel Status Register     */

+  __IO uint32_t  CFR;      /*!< DMA Channel Clear Flag Register */

+}DMAMUX_ChannelStatus_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  RGCR;        /*!< DMA Request Generator x Control Register   */

+}DMAMUX_RequestGen_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  RGSR;        /*!< DMA Request Generator Status Register       */

+  __IO uint32_t  RGCFR;       /*!< DMA Request Generator Clear Flag Register   */

+}DMAMUX_RequestGenStatus_TypeDef;

+

+/**

+  * @brief MDMA Controller

+  */

+typedef struct

+{

+  __IO uint32_t  GISR0;   /*!< MDMA Global Interrupt/Status Register 0,          Address offset: 0x00 */

+}MDMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CISR;      /*!< MDMA channel x interrupt/status register,             Address offset: 0x40 */

+  __IO uint32_t  CIFCR;     /*!< MDMA channel x interrupt flag clear register,         Address offset: 0x44 */

+  __IO uint32_t  CESR;      /*!< MDMA Channel x error status register,                 Address offset: 0x48 */

+  __IO uint32_t  CCR;       /*!< MDMA channel x control register,                      Address offset: 0x4C */

+  __IO uint32_t  CTCR;      /*!< MDMA channel x Transfer Configuration register,       Address offset: 0x50 */

+  __IO uint32_t  CBNDTR;    /*!< MDMA Channel x block number of data register,         Address offset: 0x54 */

+  __IO uint32_t  CSAR;      /*!< MDMA channel x source address register,               Address offset: 0x58 */

+  __IO uint32_t  CDAR;      /*!< MDMA channel x destination address register,          Address offset: 0x5C */

+  __IO uint32_t  CBRUR;     /*!< MDMA channel x Block Repeat address Update register,  Address offset: 0x60 */

+  __IO uint32_t  CLAR;      /*!< MDMA channel x Link Address register,                 Address offset: 0x64 */

+  __IO uint32_t  CTBR;      /*!< MDMA channel x Trigger and Bus selection Register,    Address offset: 0x68 */

+  uint32_t       RESERVED0; /*!< Reserved, 0x68                                                             */

+  __IO uint32_t  CMAR;      /*!< MDMA channel x Mask address register,                 Address offset: 0x70 */

+  __IO uint32_t  CMDR;      /*!< MDMA channel x Mask Data register,                    Address offset: 0x74 */

+}MDMA_Channel_TypeDef;

+

+/**

+  * @brief DMA2D Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */

+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */

+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */

+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */

+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */

+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */

+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */

+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */

+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */

+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */

+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */

+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */

+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */

+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */

+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */

+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */

+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */

+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */

+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */

+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */

+  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */

+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */

+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */

+} DMA2D_TypeDef;

+

+

+/**

+  * @brief Ethernet MAC

+  */

+typedef struct

+{

+  __IO uint32_t MACCR;

+  __IO uint32_t MACECR;

+  __IO uint32_t MACPFR;

+  __IO uint32_t MACWTR;

+  __IO uint32_t MACHT0R;

+  __IO uint32_t MACHT1R;

+  uint32_t      RESERVED1[14];

+  __IO uint32_t MACVTR;

+  uint32_t      RESERVED2;

+  __IO uint32_t MACVHTR;

+  uint32_t      RESERVED3;

+  __IO uint32_t MACVIR;

+  __IO uint32_t MACIVIR;

+  uint32_t      RESERVED4[2];

+  __IO uint32_t MACTFCR;

+  uint32_t      RESERVED5[7];

+  __IO uint32_t MACRFCR;

+  uint32_t      RESERVED6[7];

+  __IO uint32_t MACISR;

+  __IO uint32_t MACIER;

+  __IO uint32_t MACRXTXSR;

+  uint32_t      RESERVED7;

+  __IO uint32_t MACPCSR;

+  __IO uint32_t MACRWKPFR;

+  uint32_t      RESERVED8[2];

+  __IO uint32_t MACLCSR;

+  __IO uint32_t MACLTCR;

+  __IO uint32_t MACLETR;

+  __IO uint32_t MAC1USTCR;

+  uint32_t      RESERVED9[12];

+  __IO uint32_t MACVR;

+  __IO uint32_t MACDR;

+  uint32_t      RESERVED10;

+  __IO uint32_t MACHWF0R;

+  __IO uint32_t MACHWF1R;

+  __IO uint32_t MACHWF2R;

+  uint32_t      RESERVED11[54];

+  __IO uint32_t MACMDIOAR;

+  __IO uint32_t MACMDIODR;

+  uint32_t      RESERVED12[2];

+  __IO uint32_t MACARPAR;

+  uint32_t      RESERVED13[59];

+  __IO uint32_t MACA0HR;

+  __IO uint32_t MACA0LR;

+  __IO uint32_t MACA1HR;

+  __IO uint32_t MACA1LR;

+  __IO uint32_t MACA2HR;

+  __IO uint32_t MACA2LR;

+  __IO uint32_t MACA3HR;

+  __IO uint32_t MACA3LR;

+  uint32_t      RESERVED14[248];

+  __IO uint32_t MMCCR;

+  __IO uint32_t MMCRIR;

+  __IO uint32_t MMCTIR;

+  __IO uint32_t MMCRIMR;

+  __IO uint32_t MMCTIMR;

+  uint32_t      RESERVED15[14];

+  __IO uint32_t MMCTSCGPR;

+  __IO uint32_t MMCTMCGPR;

+  uint32_t      RESERVED16[5];

+  __IO uint32_t MMCTPCGR;

+  uint32_t      RESERVED17[10];

+  __IO uint32_t MMCRCRCEPR;

+  __IO uint32_t MMCRAEPR;

+  uint32_t      RESERVED18[10];

+  __IO uint32_t MMCRUPGR;

+  uint32_t      RESERVED19[9];

+  __IO uint32_t MMCTLPIMSTR;

+  __IO uint32_t MMCTLPITCR;

+  __IO uint32_t MMCRLPIMSTR;

+  __IO uint32_t MMCRLPITCR;

+  uint32_t      RESERVED20[65];

+  __IO uint32_t MACL3L4C0R;

+  __IO uint32_t MACL4A0R;

+  uint32_t      RESERVED21[2];

+  __IO uint32_t MACL3A0R0R;

+  __IO uint32_t MACL3A1R0R;

+  __IO uint32_t MACL3A2R0R;

+  __IO uint32_t MACL3A3R0R;

+  uint32_t      RESERVED22[4];

+  __IO uint32_t MACL3L4C1R;

+  __IO uint32_t MACL4A1R;

+  uint32_t      RESERVED23[2];

+  __IO uint32_t MACL3A0R1R;

+  __IO uint32_t MACL3A1R1R;

+  __IO uint32_t MACL3A2R1R;

+  __IO uint32_t MACL3A3R1R;

+  uint32_t      RESERVED24[108];

+  __IO uint32_t MACTSCR;

+  __IO uint32_t MACSSIR;

+  __IO uint32_t MACSTSR;

+  __IO uint32_t MACSTNR;

+  __IO uint32_t MACSTSUR;

+  __IO uint32_t MACSTNUR;

+  __IO uint32_t MACTSAR;

+  uint32_t      RESERVED25;

+  __IO uint32_t MACTSSR;

+  uint32_t      RESERVED26[3];

+  __IO uint32_t MACTTSSNR;

+  __IO uint32_t MACTTSSSR;

+  uint32_t      RESERVED27[2];

+  __IO uint32_t MACACR;

+  uint32_t      RESERVED28;

+  __IO uint32_t MACATSNR;

+  __IO uint32_t MACATSSR;

+  __IO uint32_t MACTSIACR;

+  __IO uint32_t MACTSEACR;

+  __IO uint32_t MACTSICNR;

+  __IO uint32_t MACTSECNR;

+  uint32_t      RESERVED29[4];

+  __IO uint32_t MACPPSCR;

+  uint32_t      RESERVED30[3];

+  __IO uint32_t MACPPSTTSR;

+  __IO uint32_t MACPPSTTNR;

+  __IO uint32_t MACPPSIR;

+  __IO uint32_t MACPPSWR;

+  uint32_t      RESERVED31[12];

+  __IO uint32_t MACPOCR;

+  __IO uint32_t MACSPI0R;

+  __IO uint32_t MACSPI1R;

+  __IO uint32_t MACSPI2R;

+  __IO uint32_t MACLMIR;

+  uint32_t      RESERVED32[11];

+  __IO uint32_t MTLOMR;

+  uint32_t      RESERVED33[7];

+  __IO uint32_t MTLISR;

+  uint32_t      RESERVED34[55];

+  __IO uint32_t MTLTQOMR;

+  __IO uint32_t MTLTQUR;

+  __IO uint32_t MTLTQDR;

+  uint32_t      RESERVED35[8];

+  __IO uint32_t MTLQICSR;

+  __IO uint32_t MTLRQOMR;

+  __IO uint32_t MTLRQMPOCR;

+  __IO uint32_t MTLRQDR;

+  uint32_t      RESERVED36[177];

+  __IO uint32_t DMAMR;

+  __IO uint32_t DMASBMR;

+  __IO uint32_t DMAISR;

+  __IO uint32_t DMADSR;

+  uint32_t      RESERVED37[60];

+  __IO uint32_t DMACCR;

+  __IO uint32_t DMACTCR;

+  __IO uint32_t DMACRCR;

+  uint32_t      RESERVED38[2];

+  __IO uint32_t DMACTDLAR;

+  uint32_t      RESERVED39;

+  __IO uint32_t DMACRDLAR;

+  __IO uint32_t DMACTDTPR;

+  uint32_t      RESERVED40;

+  __IO uint32_t DMACRDTPR;

+  __IO uint32_t DMACTDRLR;

+  __IO uint32_t DMACRDRLR;

+  __IO uint32_t DMACIER;

+  __IO uint32_t DMACRIWTR;

+__IO uint32_t DMACSFCSR;

+  uint32_t      RESERVED41;

+  __IO uint32_t DMACCATDR;

+  uint32_t      RESERVED42;

+  __IO uint32_t DMACCARDR;

+  uint32_t      RESERVED43;

+  __IO uint32_t DMACCATBR;

+  uint32_t      RESERVED44;

+  __IO uint32_t DMACCARBR;

+  __IO uint32_t DMACSR;

+uint32_t      RESERVED45[2];

+__IO uint32_t DMACMFCR;

+}ETH_TypeDef;

+/**

+  * @brief External Interrupt/Event Controller

+  */

+

+typedef struct

+{

+__IO uint32_t RTSR1;               /*!< EXTI Rising trigger selection register,          Address offset: 0x00 */

+__IO uint32_t FTSR1;               /*!< EXTI Falling trigger selection register,         Address offset: 0x04 */

+__IO uint32_t SWIER1;              /*!< EXTI Software interrupt event register,          Address offset: 0x08 */

+__IO uint32_t D3PMR1;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */

+__IO uint32_t D3PCR1L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L)     Address offset: 0x10 */

+__IO uint32_t D3PCR1H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H)   Address offset: 0x14 */

+uint32_t      RESERVED1[2];        /*!< Reserved,                                        0x18 to 0x1C         */

+__IO uint32_t RTSR2;               /*!< EXTI Rising trigger selection register,          Address offset: 0x20 */

+__IO uint32_t FTSR2;               /*!< EXTI Falling trigger selection register,         Address offset: 0x24 */

+__IO uint32_t SWIER2;              /*!< EXTI Software interrupt event register,          Address offset: 0x28 */

+__IO uint32_t D3PMR2;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */

+__IO uint32_t D3PCR2L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L)  Address offset: 0x30 */

+__IO uint32_t D3PCR2H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */

+uint32_t      RESERVED2[2];        /*!< Reserved,                                        0x38 to 0x3C         */

+__IO uint32_t RTSR3;               /*!< EXTI Rising trigger selection register,          Address offset: 0x40 */

+__IO uint32_t FTSR3;               /*!< EXTI Falling trigger selection register,         Address offset: 0x44 */

+__IO uint32_t SWIER3;              /*!< EXTI Software interrupt event register,          Address offset: 0x48 */

+__IO uint32_t D3PMR3;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */

+__IO uint32_t D3PCR3L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */

+__IO uint32_t D3PCR3H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */

+uint32_t      RESERVED3[10];       /*!< Reserved,                                        0x58 to 0x7C         */

+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                    Address offset: 0x80 */

+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                        Address offset: 0x84 */

+__IO uint32_t PR1;                 /*!< EXTI Pending register,                           Address offset: 0x88 */

+uint32_t      RESERVED4;           /*!< Reserved,                                        0x8C                 */

+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                    Address offset: 0x90 */

+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                        Address offset: 0x94 */

+__IO uint32_t PR2;                 /*!< EXTI Pending register,                           Address offset: 0x98 */

+uint32_t      RESERVED5;           /*!< Reserved,                                        0x9C                 */

+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                    Address offset: 0xA0 */

+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                        Address offset: 0xA4 */

+__IO uint32_t PR3;                 /*!< EXTI Pending register,                           Address offset: 0xA8 */

+uint32_t      RESERVED6[5];        /*!< Reserved,                                        0xAC to 0xBC         */

+__IO uint32_t C2IMR1;              /*!< EXTI Interrupt mask register,                    Address offset: 0xC0 */

+__IO uint32_t C2EMR1;              /*!< EXTI Event mask register,                        Address offset: 0xC4 */

+__IO uint32_t C2PR1;               /*!< EXTI Pending register,                           Address offset: 0xC8 */

+uint32_t      RESERVED7;           /*!< Reserved,                                        0xCC                 */

+__IO uint32_t C2IMR2;              /*!< EXTI Interrupt mask register,                    Address offset: 0xD0 */

+__IO uint32_t C2EMR2;              /*!< EXTI Event mask register,                        Address offset: 0xD4 */

+__IO uint32_t C2PR2;               /*!< EXTI Pending register,                           Address offset: 0xD8 */

+uint32_t      RESERVED8;           /*!< Reserved,                                        0xDC                 */

+__IO uint32_t C2IMR3;              /*!< EXTI Interrupt mask register,                    Address offset: 0xE0 */

+__IO uint32_t C2EMR3;              /*!< EXTI Event mask register,                        Address offset: 0xE4 */

+__IO uint32_t C2PR3;               /*!< EXTI Pending register,                           Address offset: 0xE8 */

+

+}EXTI_TypeDef;

+

+typedef struct

+{

+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                Address offset: 0x00 */

+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                    Address offset: 0x04 */

+__IO uint32_t PR1;                 /*!< EXTI Pending register,                       Address offset: 0x08 */

+uint32_t      RESERVED1;           /*!< Reserved, 0x0C                                                    */

+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                Address offset: 0x10 */

+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                    Address offset: 0x14 */

+__IO uint32_t PR2;                 /*!< EXTI Pending register,                       Address offset: 0x18 */

+uint32_t      RESERVED2;           /*!< Reserved, 0x1C                                                    */

+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                Address offset: 0x20 */

+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                    Address offset: 0x24 */

+__IO uint32_t PR3;                 /*!< EXTI Pending register,                       Address offset: 0x28 */

+}EXTI_Core_TypeDef;

+

+

+/**

+  * @brief FLASH Registers

+  */

+

+typedef struct

+{

+  __IO uint32_t ACR;             /*!< FLASH access control register,                            Address offset: 0x00  */

+  __IO uint32_t KEYR1;           /*!< Flash Key Register for bank1,                             Address offset: 0x04  */

+  __IO uint32_t OPTKEYR;         /*!< Flash Option Key Register,                                Address offset: 0x08  */

+  __IO uint32_t CR1;             /*!< Flash Control Register for bank1,                         Address offset: 0x0C  */

+  __IO uint32_t SR1;             /*!< Flash Status Register for bank1,                          Address offset: 0x10  */

+  __IO uint32_t CCR1;            /*!< Flash Control Register for bank1,                         Address offset: 0x14  */

+  __IO uint32_t OPTCR;           /*!< Flash Option Control Register,                            Address offset: 0x18  */

+  __IO uint32_t OPTSR_CUR;       /*!< Flash Option Status Current Register,                     Address offset: 0x1C  */

+  __IO uint32_t OPTSR_PRG;       /*!< Flash Option Status to Program Register,                  Address offset: 0x20  */

+  __IO uint32_t OPTCCR;          /*!< Flash Option Clear Control Register,                      Address offset: 0x24  */

+  __IO uint32_t PRAR_CUR1;       /*!< Flash Current Protection Address Register for bank1,      Address offset: 0x28  */

+  __IO uint32_t PRAR_PRG1;       /*!< Flash Protection Address to Program Register for bank1,   Address offset: 0x2C  */

+  __IO uint32_t SCAR_CUR1;       /*!< Flash Current Secure Address Register for bank1,          Address offset: 0x30  */

+  __IO uint32_t SCAR_PRG1;       /*!< Flash Secure Address to Program Register for bank1,       Address offset: 0x34  */

+  __IO uint32_t WPSN_CUR1;       /*!< Flash Current Write Protection Register on bank1,         Address offset: 0x38  */

+  __IO uint32_t WPSN_PRG1;       /*!< Flash Write Protection to Program Register on bank1,      Address offset: 0x3C  */

+  __IO uint32_t BOOT7_CUR;       /*!< Flash Current Boot Address for Pelican Core Register,     Address offset: 0x40  */

+  __IO uint32_t BOOT7_PRG;       /*!< Flash Boot Address to Program for Pelican Core Register,  Address offset: 0x44  */

+  __IO uint32_t BOOT4_CUR;       /*!< Flash Current Boot Address for M4 Core Register,          Address offset: 0x48  */

+  __IO uint32_t BOOT4_PRG;       /*!< Flash Boot Address to Program for M4 Core Register,       Address offset: 0x4C  */

+  __IO uint32_t CRCCR1;          /*!< Flash CRC Control register For Bank1 Register ,           Address offset: 0x50  */

+  __IO uint32_t CRCSADD1;        /*!< Flash CRC Start Address Register for Bank1 ,              Address offset: 0x54  */

+  __IO uint32_t CRCEADD1;        /*!< Flash CRC End Address Register for Bank1 ,                Address offset: 0x58  */

+  __IO uint32_t CRCDATA;         /*!< Flash CRC Data Register for Bank1 ,                       Address offset: 0x5C  */

+  __IO uint32_t ECC_FA1;         /*!< Flash ECC Fail Address For Bank1 Register ,               Address offset: 0x60  */

+  uint32_t      RESERVED1[40];   /*!< Reserved, 0x64 to 0x100                                                         */

+  __IO uint32_t KEYR2;           /*!< Flash Key Register for bank2,                             Address offset: 0x104 */

+  uint32_t      RESERVED2;       /*!< Reserved, 0x108                                                                 */

+  __IO uint32_t CR2;             /*!< Flash Control Register for bank2,                         Address offset: 0x10C */

+  __IO uint32_t SR2;             /*!< Flash Status Register for bank2,                          Address offset: 0x110 */

+  __IO uint32_t CCR2;            /*!< Flash Status Register for bank2,                          Address offset: 0x114 */

+  uint32_t      RESERVED3[4];    /*!< Reserved, 0x118 to 0x124                                                        */

+  __IO uint32_t PRAR_CUR2;       /*!< Flash Current Protection Address Register for bank2,      Address offset: 0x128 */

+  __IO uint32_t PRAR_PRG2;       /*!< Flash Protection Address to Program Register for bank2,   Address offset: 0x12C */

+  __IO uint32_t SCAR_CUR2;       /*!< Flash Current Secure Address Register for bank2,          Address offset: 0x130 */

+  __IO uint32_t SCAR_PRG2;       /*!< Flash Secure Address Register for bank2,                  Address offset: 0x134 */

+  __IO uint32_t WPSN_CUR2;       /*!< Flash Current Write Protection Register on bank2,         Address offset: 0x138 */

+  __IO uint32_t WPSN_PRG2;       /*!< Flash Write Protection to Program Register on bank2,      Address offset: 0x13C */

+  uint32_t      RESERVED4[4];    /*!< Reserved, 0x140 to 0x14C                                                        */

+  __IO uint32_t CRCCR2;          /*!< Flash CRC Control register For Bank2 Register ,           Address offset: 0x150 */

+  __IO uint32_t CRCSADD2;        /*!< Flash CRC Start Address Register for Bank2 ,              Address offset: 0x154 */

+  __IO uint32_t CRCEADD2;        /*!< Flash CRC End Address Register for Bank2 ,                Address offset: 0x158 */

+  __IO uint32_t CRCDATA2;        /*!< Flash CRC Data Register for Bank2 ,                       Address offset: 0x15C */

+  __IO uint32_t ECC_FA2;         /*!< Flash ECC Fail Address For Bank2 Register ,               Address offset: 0x160 */

+} FLASH_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */

+} FMC_Bank1_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank1E

+  */

+

+typedef struct

+{

+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */

+} FMC_Bank1E_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank2

+  */

+

+typedef struct

+{

+  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */

+  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */

+  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */

+  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */

+  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */

+  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */

+} FMC_Bank2_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank3

+  */

+

+typedef struct

+{

+  __IO uint32_t PCR;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */

+  __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */

+  __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */

+  __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */

+  uint32_t      RESERVED;  /*!< Reserved, 0x90                                                            */

+  __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */

+} FMC_Bank3_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank5 and 6

+  */

+

+

+typedef struct

+{

+  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */

+  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */

+  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */

+  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */

+  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */

+} FMC_Bank5_6_TypeDef;

+

+/**

+  * @brief General Purpose I/O

+  */

+

+typedef struct

+{

+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */

+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */

+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */

+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */

+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */

+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */

+  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset,               Address offset: 0x18      */

+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */

+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */

+} GPIO_TypeDef;

+

+/**

+  * @brief Operational Amplifier (OPAMP)

+  */

+

+typedef struct

+{

+  __IO uint32_t CSR;          /*!< OPAMP control/status register,                      Address offset: 0x00 */

+  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,     Address offset: 0x04 */

+  __IO uint32_t HSOTR;        /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */

+} OPAMP_TypeDef;

+

+/**

+  * @brief System configuration controller

+  */

+

+typedef struct

+{

+ uint32_t RESERVED1;           /*!< Reserved,                                           Address offset: 0x00        */

+ __IO uint32_t PMCR;           /*!< SYSCFG peripheral mode configuration register,      Address offset: 0x04        */

+ __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration registers,  Address offset: 0x08-0x14   */

+ __IO uint32_t CFGR;           /*!< SYSCFG configuration registers,                     Address offset: 0x18        */

+ uint32_t RESERVED2;           /*!< Reserved,                                           Address offset: 0x1C        */

+ __IO uint32_t CCCSR;          /*!< SYSCFG compensation cell control/status register,   Address offset: 0x20        */

+ __IO uint32_t CCVR;           /*!< SYSCFG compensation cell value register,            Address offset: 0x24        */

+ __IO uint32_t CCCR;           /*!< SYSCFG compensation cell code register,             Address offset: 0x28        */

+ __IO uint32_t PWRCR;          /*!< PWR control register,                               Address offset: 0x2C        */

+  uint32_t     RESERVED3[61];  /*!< Reserved, 0x30-0x120                                                            */

+  __IO uint32_t PKGR;          /*!< SYSCFG package register,                            Address offset: 0x124       */

+  uint32_t     RESERVED4[118]; /*!< Reserved, 0x128-0x2FC                                                           */

+ __IO uint32_t UR0;            /*!< SYSCFG user register 0,                             Address offset: 0x300       */

+ __IO uint32_t UR1;            /*!< SYSCFG user register 1,                             Address offset: 0x304       */

+ __IO uint32_t UR2;            /*!< SYSCFG user register 2,                             Address offset: 0x308       */

+ __IO uint32_t UR3;            /*!< SYSCFG user register 3,                             Address offset: 0x30C       */

+ __IO uint32_t UR4;            /*!< SYSCFG user register 4,                             Address offset: 0x310       */

+ __IO uint32_t UR5;            /*!< SYSCFG user register 5,                             Address offset: 0x314       */

+ __IO uint32_t UR6;            /*!< SYSCFG user register 6,                             Address offset: 0x318       */

+ __IO uint32_t UR7;            /*!< SYSCFG user register 7,                             Address offset: 0x31C       */

+ __IO uint32_t UR8;            /*!< SYSCFG user register 8,                             Address offset: 0x320       */

+ __IO uint32_t UR9;            /*!< SYSCFG user register 9,                             Address offset: 0x324       */

+ __IO uint32_t UR10;           /*!< SYSCFG user register 10,                            Address offset: 0x328       */

+ __IO uint32_t UR11;           /*!< SYSCFG user register 11,                            Address offset: 0x32C       */

+ __IO uint32_t UR12;           /*!< SYSCFG user register 12,                            Address offset: 0x330       */

+ __IO uint32_t UR13;           /*!< SYSCFG user register 13,                            Address offset: 0x334       */

+ __IO uint32_t UR14;           /*!< SYSCFG user register 14,                            Address offset: 0x338       */

+ __IO uint32_t UR15;           /*!< SYSCFG user register 15,                            Address offset: 0x33C       */

+ __IO uint32_t UR16;           /*!< SYSCFG user register 16,                            Address offset: 0x340       */

+ __IO uint32_t UR17;           /*!< SYSCFG user register 17,                            Address offset: 0x344       */

+

+} SYSCFG_TypeDef;

+

+/**

+  * @brief Inter-integrated Circuit Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */

+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */

+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */

+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */

+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */

+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */

+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */

+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */

+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */

+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */

+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */

+} I2C_TypeDef;

+

+/**

+  * @brief Independent WATCHDOG

+  */

+

+typedef struct

+{

+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */

+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */

+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */

+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */

+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */

+} IWDG_TypeDef;

+

+

+/**

+  * @brief JPEG Codec

+  */

+typedef struct

+{

+  __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */

+  __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */

+  __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */

+  __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */

+  __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */

+  __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */

+  __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */

+  __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */

+  uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */

+  __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */

+  __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */

+  __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */

+  uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */

+  __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */

+  __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */

+  uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */

+  __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */

+  __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */

+  __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */

+  __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */

+  __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */

+  __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */

+  __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */

+  __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */

+  uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */

+  __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0,                 Address offset: 500h-65Ch */

+  __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1,                 Address offset: 660h-7BCh */

+  __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encodor, DC Huffman table 0,                 Address offset: 7C0h-7DCh */

+  __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encodor, DC Huffman table 1,                 Address offset: 7E0h-7FCh */

+

+} JPEG_TypeDef;

+

+/**

+  * @brief LCD-TFT Display Controller

+  */

+

+typedef struct

+{

+  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04                                                       */

+  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */

+  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */

+  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */

+  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */

+  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */

+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20                                                       */

+  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */

+  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28                                                            */

+  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */

+  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30                                                            */

+  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */

+  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */

+  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */

+  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */

+  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */

+  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */

+} LTDC_TypeDef;

+

+/**

+  * @brief LCD-TFT Display layer x Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */

+  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */

+  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */

+  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */

+  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */

+  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */

+  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */

+  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */

+  uint32_t      RESERVED0[2];  /*!< Reserved */

+  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */

+  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */

+  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */

+  uint32_t      RESERVED1[3];  /*!< Reserved */

+  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */

+

+} LTDC_Layer_TypeDef;

+

+/**

+  * @brief Power Control

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;       /*!< PWR power control register 1,            Address offset: 0x00 */

+  __IO uint32_t CSR1;      /*!< PWR power control status register 1,     Address offset: 0x04 */

+  __IO uint32_t CR2;       /*!< PWR power control register 2,            Address offset: 0x08 */

+  __IO uint32_t CR3;       /*!< PWR power control register 3,            Address offset: 0x0C */

+  __IO uint32_t CPUCR;     /*!< PWR CPU control register,                Address offset: 0x10 */

+  __IO uint32_t CPU2CR;    /*!< PWR CPU2 control register,               Address offset: 0x14 */

+  __IO uint32_t D3CR;      /*!< PWR D3 domain control register,          Address offset: 0x18 */

+       uint32_t RESERVED1; /*!< Reserved,                                Address offset: 0x1C */

+  __IO uint32_t WKUPCR;    /*!< PWR wakeup clear register,               Address offset: 0x20 */

+  __IO uint32_t WKUPFR;    /*!< PWR wakeup flag register,                Address offset: 0x24 */

+  __IO uint32_t WKUPEPR;   /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */

+} PWR_TypeDef;

+

+/**

+  * @brief Reset and Clock Control

+  */

+

+typedef struct

+{

+ __IO uint32_t CR;             /*!< RCC clock control register,                                              Address offset: 0x00  */

+ __IO uint32_t HSICFGR;        /*!< HSI Clock Calibration Register,                                          Address offset: 0x04  */

+ __IO uint32_t CRRCR;          /*!< Clock Recovery RC  Register,                                             Address offset: 0x08  */

+ __IO uint32_t CSICFGR;        /*!< CSI Clock Calibration Register,                                          Address offset: 0x0C  */

+ __IO uint32_t CFGR;           /*!< RCC clock configuration register,                                        Address offset: 0x10  */

+ uint32_t     RESERVED1;       /*!< Reserved,                                                                Address offset: 0x14  */

+ __IO uint32_t D1CFGR;         /*!< RCC Domain 1 configuration register,                                     Address offset: 0x18  */

+ __IO uint32_t D2CFGR;         /*!< RCC Domain 2 configuration register,                                     Address offset: 0x1C  */

+ __IO uint32_t D3CFGR;         /*!< RCC Domain 3 configuration register,                                     Address offset: 0x20  */

+ uint32_t     RESERVED2;       /*!< Reserved,                                                                Address offset: 0x24  */

+ __IO uint32_t PLLCKSELR;      /*!< RCC PLLs Clock Source Selection Register,                                Address offset: 0x28  */

+ __IO uint32_t PLLCFGR;        /*!< RCC PLLs  Configuration Register,                                        Address offset: 0x2C  */

+ __IO uint32_t PLL1DIVR;       /*!< RCC PLL1 Dividers Configuration Register,                                Address offset: 0x30  */

+ __IO uint32_t PLL1FRACR;      /*!< RCC PLL1 Fractional Divider Configuration Register,                      Address offset: 0x34  */

+ __IO uint32_t PLL2DIVR;       /*!< RCC PLL2 Dividers Configuration Register,                                Address offset: 0x38  */

+ __IO uint32_t PLL2FRACR;      /*!< RCC PLL2 Fractional Divider Configuration Register,                      Address offset: 0x3C  */

+ __IO uint32_t PLL3DIVR;       /*!< RCC PLL3 Dividers Configuration Register,                                Address offset: 0x40  */

+ __IO uint32_t PLL3FRACR;      /*!< RCC PLL3 Fractional Divider Configuration Register,                      Address offset: 0x44  */

+ uint32_t      RESERVED3;      /*!< Reserved,                                                                Address offset: 0x48  */

+ __IO uint32_t  D1CCIPR;       /*!< RCC Domain 1 Kernel Clock Configuration Register                         Address offset: 0x4C  */

+ __IO uint32_t  D2CCIP1R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x50  */

+ __IO uint32_t  D2CCIP2R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x54  */

+ __IO uint32_t  D3CCIPR;       /*!< RCC Domain 3 Kernel Clock Configuration Register                         Address offset: 0x58  */

+ uint32_t      RESERVED4;      /*!< Reserved,                                                                Address offset: 0x5C  */

+ __IO uint32_t  CIER;          /*!< RCC Clock Source Interrupt Enable Register                               Address offset: 0x60  */

+ __IO uint32_t  CIFR;          /*!< RCC Clock Source Interrupt Flag Register                                 Address offset: 0x64  */

+ __IO uint32_t  CICR;          /*!< RCC Clock Source Interrupt Clear Register                                Address offset: 0x68  */

+ uint32_t     RESERVED5;       /*!< Reserved,                                                                Address offset: 0x6C  */

+ __IO uint32_t  BDCR;          /*!< RCC Vswitch Backup Domain Control Register,                              Address offset: 0x70  */

+ __IO uint32_t  CSR;           /*!< RCC clock control & status register,                                     Address offset: 0x74  */

+ uint32_t     RESERVED6;       /*!< Reserved,                                                                Address offset: 0x78  */

+ __IO uint32_t AHB3RSTR;       /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x7C  */

+ __IO uint32_t AHB1RSTR;       /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x80  */

+ __IO uint32_t AHB2RSTR;       /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x84  */

+ __IO uint32_t AHB4RSTR;       /*!< RCC AHB4 peripheral reset register,                                      Address offset: 0x88  */

+ __IO uint32_t APB3RSTR;       /*!< RCC APB3 peripheral reset register,                                      Address offset: 0x8C  */

+ __IO uint32_t APB1LRSTR;      /*!< RCC APB1 peripheral reset Low Word register,                             Address offset: 0x90  */

+ __IO uint32_t APB1HRSTR;      /*!< RCC APB1 peripheral reset High Word register,                            Address offset: 0x94  */

+ __IO uint32_t APB2RSTR;       /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x98  */

+ __IO uint32_t APB4RSTR;       /*!< RCC APB4 peripheral reset register,                                      Address offset: 0x9C  */

+ __IO uint32_t GCR;            /*!< RCC RCC Global Control  Register,                                        Address offset: 0xA0  */

+ uint32_t     RESERVED8;       /*!< Reserved,                                                                Address offset: 0xA4  */

+ __IO uint32_t D3AMR;          /*!< RCC Domain 3 Autonomous Mode Register,                                   Address offset: 0xA8  */

+ uint32_t     RESERVED11[9];    /*!< Reserved, 0xAC-0xCC                                                      Address offset: 0xAC  */

+ __IO uint32_t RSR;            /*!< RCC Reset status register,                                               Address offset: 0xD0  */

+ __IO uint32_t AHB3ENR;        /*!< RCC AHB3 peripheral clock  register,                                     Address offset: 0xD4  */

+ __IO uint32_t AHB1ENR;        /*!< RCC AHB1 peripheral clock  register,                                     Address offset: 0xD8  */

+ __IO uint32_t AHB2ENR;        /*!< RCC AHB2 peripheral clock  register,                                     Address offset: 0xDC  */

+ __IO uint32_t AHB4ENR;        /*!< RCC AHB4 peripheral clock  register,                                     Address offset: 0xE0  */

+ __IO uint32_t APB3ENR;        /*!< RCC APB3 peripheral clock  register,                                     Address offset: 0xE4  */

+ __IO uint32_t APB1LENR;       /*!< RCC APB1 peripheral clock  Low Word register,                            Address offset: 0xE8  */

+ __IO uint32_t APB1HENR;       /*!< RCC APB1 peripheral clock  High Word register,                           Address offset: 0xEC  */

+ __IO uint32_t APB2ENR;        /*!< RCC APB2 peripheral clock  register,                                     Address offset: 0xF0  */

+ __IO uint32_t APB4ENR;        /*!< RCC APB4 peripheral clock  register,                                     Address offset: 0xF4  */

+ uint32_t      RESERVED12;      /*!< Reserved,                                                                Address offset: 0xF8  */

+ __IO uint32_t AHB3LPENR;      /*!< RCC AHB3 peripheral sleep clock  register,                               Address offset: 0xFC  */

+ __IO uint32_t AHB1LPENR;      /*!< RCC AHB1 peripheral sleep clock  register,                               Address offset: 0x100 */

+ __IO uint32_t AHB2LPENR;      /*!< RCC AHB2 peripheral sleep clock  register,                               Address offset: 0x104 */

+ __IO uint32_t AHB4LPENR;      /*!< RCC AHB4 peripheral sleep clock  register,                               Address offset: 0x108 */

+ __IO uint32_t APB3LPENR;      /*!< RCC APB3 peripheral sleep clock  register,                               Address offset: 0x10C */

+ __IO uint32_t APB1LLPENR;     /*!< RCC APB1 peripheral sleep clock  Low Word register,                      Address offset: 0x110 */

+ __IO uint32_t APB1HLPENR;     /*!< RCC APB1 peripheral sleep clock  High Word register,                     Address offset: 0x114 */

+ __IO uint32_t APB2LPENR;      /*!< RCC APB2 peripheral sleep clock  register,                               Address offset: 0x118 */

+ __IO uint32_t APB4LPENR;      /*!< RCC APB4 peripheral sleep clock  register,                               Address offset: 0x11C */

+ uint32_t     RESERVED13[4];   /*!< Reserved, 0x120-0x12C                                                    Address offset: 0x120 */

+

+} RCC_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t RSR;          /*!< RCC Reset status register,                                               Address offset: 0x00 */

+  __IO uint32_t AHB3ENR;      /*!< RCC AHB3 peripheral clock  register,                            Address offset: 0x04 */

+  __IO uint32_t AHB1ENR;      /*!< RCC AHB1 peripheral clock  register,                            Address offset: 0x08 */

+  __IO uint32_t AHB2ENR;      /*!< RCC AHB2 peripheral clock  register,                            Address offset: 0x0C */

+  __IO uint32_t AHB4ENR;      /*!< RCC AHB4 peripheral clock  register,                            Address offset: 0x10 */

+  __IO uint32_t APB3ENR;      /*!< RCC APB3 peripheral clock  register,                            Address offset: 0x14 */

+  __IO uint32_t APB1LENR;     /*!< RCC APB1 peripheral clock  Low Word register,                   Address offset: 0x18 */

+  __IO uint32_t APB1HENR;     /*!< RCC APB1 peripheral clock  High Word register,                  Address offset: 0x1C */

+  __IO uint32_t APB2ENR;      /*!< RCC APB2 peripheral clock  register,                            Address offset: 0x20 */

+  __IO uint32_t APB4ENR;      /*!< RCC APB4 peripheral clock  register,                            Address offset: 0x24 */

+  uint32_t      RESERVED9;    /*!< Reserved,                                                       Address offset: 0x28 */

+  __IO uint32_t AHB3LPENR;    /*!< RCC AHB3 peripheral sleep clock  register,                      Address offset: 0x3C */

+  __IO uint32_t AHB1LPENR;    /*!< RCC AHB1 peripheral sleep clock  register,                      Address offset: 0x40 */

+  __IO uint32_t AHB2LPENR;    /*!< RCC AHB2 peripheral sleep clock  register,                      Address offset: 0x44 */

+  __IO uint32_t AHB4LPENR;    /*!< RCC AHB4 peripheral sleep clock  register,                      Address offset: 0x48 */

+  __IO uint32_t APB3LPENR;    /*!< RCC APB3 peripheral sleep clock  register,                      Address offset: 0x4C */

+  __IO uint32_t APB1LLPENR;   /*!< RCC APB1 peripheral sleep clock  Low Word register,             Address offset: 0x50 */

+  __IO uint32_t APB1HLPENR;   /*!< RCC APB1 peripheral sleep clock  High Word register,            Address offset: 0x54 */

+  __IO uint32_t APB2LPENR;    /*!< RCC APB2 peripheral sleep clock  register,                      Address offset: 0x58 */

+  __IO uint32_t APB4LPENR;    /*!< RCC APB4 peripheral sleep clock  register,                      Address offset: 0x5C */

+  uint32_t     RESERVED10[4]; /*!< Reserved, 0x60-0x6C                                             Address offset: 0x60 */

+

+} RCC_Core_TypeDef;

+

+/**

+  * @brief Real-Time Clock

+  */

+typedef struct

+{

+  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */

+  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */

+  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */

+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */

+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */

+  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */

+       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */

+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */

+  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */

+  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */

+  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */

+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */

+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */

+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */

+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */

+  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */

+  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */

+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */

+  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */

+  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset: 0x4C */

+  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */

+  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */

+  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */

+  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */

+  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */

+  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */

+  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */

+  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */

+  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */

+  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */

+  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */

+  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */

+  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */

+  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */

+  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */

+  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */

+  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */

+  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */

+  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */

+  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */

+  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */

+  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */

+  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */

+  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */

+  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */

+  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */

+  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */

+  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */

+  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */

+  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */

+  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */

+  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */

+} RTC_TypeDef;

+

+/**

+  * @brief Serial Audio Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t GCR;           /*!< SAI global configuration register, Address offset: 0x00 */

+  uint32_t      RESERVED0[16]; /*!< Reserved, 0x04 - 0x43                                   */

+  __IO uint32_t PDMCR;         /*!< SAI PDM control register,          Address offset: 0x44 */

+  __IO uint32_t PDMDLY;        /*!< SAI PDM delay register,            Address offset: 0x48 */

+} SAI_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */

+  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */

+  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */

+  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */

+  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */

+  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */

+  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */

+  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */

+} SAI_Block_TypeDef;

+

+/**

+  * @brief SPDIF-RX Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */

+  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */

+  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */

+  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */

+  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */

+  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */

+  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */

+  uint32_t        RESERVED2;    /*!< Reserved,  0x1A                                          */

+} SPDIFRX_TypeDef;

+

+

+/**

+  * @brief Secure digital input/output Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t POWER;          /*!< SDMMC power control register,             Address offset: 0x00  */

+  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,             Address offset: 0x04  */

+  __IO uint32_t ARG;            /*!< SDMMC argument register,                  Address offset: 0x08  */

+  __IO uint32_t CMD;            /*!< SDMMC command register,                   Address offset: 0x0C  */

+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register,          Address offset: 0x10  */

+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                Address offset: 0x14  */

+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                Address offset: 0x18  */

+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                Address offset: 0x1C  */

+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                Address offset: 0x20  */

+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                Address offset: 0x24  */

+  __IO uint32_t DLEN;           /*!< SDMMC data length register,               Address offset: 0x28  */

+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,              Address offset: 0x2C  */

+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,              Address offset: 0x30  */

+  __I uint32_t  STA;            /*!< SDMMC status register,                    Address offset: 0x34  */

+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,           Address offset: 0x38  */

+  __IO uint32_t MASK;           /*!< SDMMC mask register,                      Address offset: 0x3C  */

+  __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,     Address offset: 0x40  */

+  uint32_t      RESERVED0[3];   /*!< Reserved, 0x44 - 0x4C - 0x4C                                    */

+  __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,               Address offset: 0x50  */

+  __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,           Address offset: 0x54  */

+  __IO uint32_t IDMABASE0;      /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58  */

+  __IO uint32_t IDMABASE1;      /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C  */

+  uint32_t      RESERVED1[8];   /*!< Reserved, 0x60-0x7C                                             */

+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,                 Address offset: 0x80  */

+  uint32_t      RESERVED2[222]; /*!< Reserved, 0x84-0x3F8                                            */

+  __IO uint32_t IPVR;           /*!< SDMMC data FIFO register,                 Address offset: 0x3FC */

+} SDMMC_TypeDef;

+

+

+/**

+  * @brief Delay Block DLYB

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;          /*!< DELAY BLOCK control register,  Address offset: 0x00 */

+  __IO uint32_t CFGR;        /*!< DELAY BLOCK configuration register,  Address offset: 0x04 */

+} DLYB_TypeDef;

+

+/**

+  * @brief HW Semaphore HSEM

+  */

+

+typedef struct

+{

+  __IO uint32_t R[32];      /*!< 2-step write lock and read back registers,     Address offset: 00h-7Ch  */

+  __IO uint32_t RLR[32];    /*!< 1-step read lock registers,                    Address offset: 80h-FCh  */

+  __IO uint32_t C1IER;      /*!< HSEM Interrupt 0 enable register ,             Address offset: 100h     */

+  __IO uint32_t C1ICR;      /*!< HSEM Interrupt 0 clear register ,              Address offset: 104h     */

+  __IO uint32_t C1ISR;      /*!< HSEM Interrupt 0 Status register ,             Address offset: 108h     */

+  __IO uint32_t C1MISR;     /*!< HSEM Interrupt 0 Masked Status register ,      Address offset: 10Ch     */

+  __IO uint32_t C2IER;      /*!< HSEM Interrupt 1 enable register ,             Address offset: 110h     */

+  __IO uint32_t C2ICR;      /*!< HSEM Interrupt 1 clear register ,              Address offset: 114h     */

+  __IO uint32_t C2ISR;      /*!< HSEM Interrupt 1 Status register ,             Address offset: 118h     */

+  __IO uint32_t C2MISR;     /*!< HSEM Interrupt 1 Masked Status register ,      Address offset: 11Ch     */

+   uint32_t  Reserved[8];   /* Reserved                                         Address offset: 120h-13Ch*/

+  __IO uint32_t CR;         /*!< HSEM Semaphore clear register ,                Address offset: 140h      */

+  __IO uint32_t KEYR;       /*!< HSEM Semaphore clear key register ,            Address offset: 144h      */

+

+} HSEM_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t IER;        /*!< HSEM interrupt enable register ,                Address offset:   0h     */

+  __IO uint32_t ICR;        /*!< HSEM interrupt clear register ,                 Address offset:   4h     */

+  __IO uint32_t ISR;        /*!< HSEM interrupt status register ,                Address offset:   8h     */

+  __IO uint32_t MISR;       /*!< HSEM masked interrupt status register ,         Address offset:   Ch     */

+} HSEM_Common_TypeDef;

+

+/**

+  * @brief Serial Peripheral Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */

+  __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */

+  __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */

+  __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */

+  __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */

+  __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */

+  __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */

+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */

+  __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */

+  uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */

+  __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */

+  uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */

+  __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */

+  __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */

+  __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */

+  __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */

+  __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */

+

+} SPI_TypeDef;

+/**

+  * @brief QUAD Serial Peripheral Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */

+  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */

+  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */

+  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */

+  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */

+  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */

+  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */

+  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */

+  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */

+  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */

+  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */

+  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */

+  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */

+} QUADSPI_TypeDef;

+

+/**

+  * @brief TIM

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */

+  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */

+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */

+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */

+  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */

+  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */

+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */

+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */

+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */

+  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */

+  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */

+  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */

+  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */

+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */

+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */

+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */

+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */

+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */

+  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */

+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */

+  uint32_t      RESERVED1;   /*!< Reserved, 0x50                                                 */

+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */

+  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */

+  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */

+  __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */

+  __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */

+  __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x68 */

+} TIM_TypeDef;

+

+/**

+  * @brief LPTIMIMER

+  */

+typedef struct

+{

+  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,         Address offset: 0x00 */

+  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,              Address offset: 0x04 */

+  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,             Address offset: 0x08 */

+  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                Address offset: 0x0C */

+  __IO uint32_t CR;       /*!< LPTIM Control register,                      Address offset: 0x10 */

+  __IO uint32_t CMP;      /*!< LPTIM Compare register,                      Address offset: 0x14 */

+  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                   Address offset: 0x18 */

+  __IO uint32_t CNT;      /*!< LPTIM Counter register,                      Address offset: 0x1C */

+  uint32_t  RESERVED1;    /*!< Reserved, 0x20                                                    */

+  __IO uint32_t CFGR2;    /*!< LPTIM Configuration register,                Address offset: 0x24 */

+} LPTIM_TypeDef;

+

+/**

+  * @brief Comparator

+  */

+typedef struct

+{

+  __IO uint32_t SR;        /*!< Comparator status register,                    Address offset: 0x00 */

+  __IO uint32_t ICFR;      /*!< Comparator interrupt clear flag register,       Address offset: 0x04 */

+  __IO uint32_t OR;        /*!< Comparator option register,                  Address offset: 0x08 */

+} COMPOPT_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CFGR;      /*!< Comparator configuration register  ,           Address offset: 0x00 */

+} COMP_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CFGR;       /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */

+} COMP_Common_TypeDef;

+/**

+  * @brief Universal Synchronous Asynchronous Receiver Transmitter

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */

+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */

+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */

+  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */

+  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */

+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */

+  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */

+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */

+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */

+  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */

+  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */

+  __IO uint32_t PRESC;  /*!< USART clock Prescaler register,           Address offset: 0x2C */

+} USART_TypeDef;

+

+/**

+  * @brief Single Wire Protocol Master Interface SPWMI

+  */

+typedef struct

+{

+  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */

+  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */

+    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */

+  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */

+  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */

+  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */

+  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */

+  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */

+  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */

+  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */

+} SWPMI_TypeDef;

+

+/**

+  * @brief Window WATCHDOG

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */

+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */

+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */

+} WWDG_TypeDef;

+

+

+/**

+  * @brief RAM_ECC_Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t CR;           /*!< RAMECC monitor configuration register          */

+  __IO uint32_t SR;           /*!< RAMECC monitor status register                 */

+  __IO uint32_t FAR;          /*!< RAMECC monitor failing address register        */

+  __IO uint32_t FDRL;         /*!< RAMECC monitor failing data low register       */

+  __IO uint32_t FDRH;         /*!< RAMECC monitor failing data high register      */

+  __IO uint32_t FECR;         /*!< RAMECC monitor failing ECC error code register */

+} RAMECC_MonitorTypeDef;

+

+typedef struct

+{

+  __IO uint32_t IER;          /*!< RAMECC interrupt enable register */

+} RAMECC_TypeDef;

+/**

+  * @}

+  */

+

+

+

+/**

+  * @brief High resolution Timer (HRTIM)

+  */

+/* HRTIM master registers definition */

+typedef struct

+{

+  __IO uint32_t MCR;            /*!< HRTIM Master Timer control register,                     Address offset: 0x00 */

+  __IO uint32_t MISR;           /*!< HRTIM Master Timer interrupt status register,            Address offset: 0x04 */

+  __IO uint32_t MICR;           /*!< HRTIM Master Timer interupt clear register,              Address offset: 0x08 */

+  __IO uint32_t MDIER;          /*!< HRTIM Master Timer DMA/interrupt enable register         Address offset: 0x0C */

+  __IO uint32_t MCNTR;          /*!< HRTIM Master Timer counter register,                     Address offset: 0x10 */

+  __IO uint32_t MPER;           /*!< HRTIM Master Timer period register,                      Address offset: 0x14 */

+  __IO uint32_t MREP;           /*!< HRTIM Master Timer repetition register,                  Address offset: 0x18 */

+  __IO uint32_t MCMP1R;         /*!< HRTIM Master Timer compare 1 register,                   Address offset: 0x1C */

+  uint32_t      RESERVED0;     /*!< Reserved,                                                                 0x20 */

+  __IO uint32_t MCMP2R;         /*!< HRTIM Master Timer compare 2 register,                   Address offset: 0x24 */

+  __IO uint32_t MCMP3R;         /*!< HRTIM Master Timer compare 3 register,                   Address offset: 0x28 */

+  __IO uint32_t MCMP4R;         /*!< HRTIM Master Timer compare 4 register,                   Address offset: 0x2C */

+  uint32_t      RESERVED1[20];  /*!< Reserved,                                                          0x30..0x7C */

+}HRTIM_Master_TypeDef;

+

+/* HRTIM Timer A to E registers definition */

+typedef struct

+{

+  __IO uint32_t TIMxCR;     /*!< HRTIM Timerx control register,                              Address offset: 0x00 */

+  __IO uint32_t TIMxISR;    /*!< HRTIM Timerx interrupt status register,                     Address offset: 0x04 */

+  __IO uint32_t TIMxICR;    /*!< HRTIM Timerx interrupt clear register,                      Address offset: 0x08 */

+  __IO uint32_t TIMxDIER;   /*!< HRTIM Timerx DMA/interrupt enable register,                 Address offset: 0x0C */

+  __IO uint32_t CNTxR;      /*!< HRTIM Timerx counter register,                              Address offset: 0x10 */

+  __IO uint32_t PERxR;      /*!< HRTIM Timerx period register,                               Address offset: 0x14 */

+  __IO uint32_t REPxR;      /*!< HRTIM Timerx repetition register,                           Address offset: 0x18 */

+  __IO uint32_t CMP1xR;     /*!< HRTIM Timerx compare 1 register,                            Address offset: 0x1C */

+  __IO uint32_t CMP1CxR;    /*!< HRTIM Timerx compare 1 compound register,                   Address offset: 0x20 */

+  __IO uint32_t CMP2xR;     /*!< HRTIM Timerx compare 2 register,                            Address offset: 0x24 */

+  __IO uint32_t CMP3xR;     /*!< HRTIM Timerx compare 3 register,                            Address offset: 0x28 */

+  __IO uint32_t CMP4xR;     /*!< HRTIM Timerx compare 4 register,                            Address offset: 0x2C */

+  __IO uint32_t CPT1xR;     /*!< HRTIM Timerx capture 1 register,                            Address offset: 0x30 */

+  __IO uint32_t CPT2xR;     /*!< HRTIM Timerx capture 2 register,                            Address offset: 0x34 */

+  __IO uint32_t DTxR;       /*!< HRTIM Timerx dead time register,                            Address offset: 0x38 */

+  __IO uint32_t SETx1R;     /*!< HRTIM Timerx output 1 set register,                         Address offset: 0x3C */

+  __IO uint32_t RSTx1R;     /*!< HRTIM Timerx output 1 reset register,                       Address offset: 0x40 */

+  __IO uint32_t SETx2R;     /*!< HRTIM Timerx output 2 set register,                         Address offset: 0x44 */

+  __IO uint32_t RSTx2R;     /*!< HRTIM Timerx output 2 reset register,                       Address offset: 0x48 */

+  __IO uint32_t EEFxR1;     /*!< HRTIM Timerx external event filtering 1 register,           Address offset: 0x4C */

+  __IO uint32_t EEFxR2;     /*!< HRTIM Timerx external event filtering 2 register,           Address offset: 0x50 */

+  __IO uint32_t RSTxR;      /*!< HRTIM Timerx Reset register,                                Address offset: 0x54 */

+  __IO uint32_t CHPxR;      /*!< HRTIM Timerx Chopper register,                              Address offset: 0x58 */

+  __IO uint32_t CPT1xCR;    /*!< HRTIM Timerx Capture 1 register,                            Address offset: 0x5C */

+  __IO uint32_t CPT2xCR;    /*!< HRTIM Timerx Capture 2 register,                            Address offset: 0x60 */

+  __IO uint32_t OUTxR;      /*!< HRTIM Timerx Output register,                               Address offset: 0x64 */

+  __IO uint32_t FLTxR;      /*!< HRTIM Timerx Fault register,                                Address offset: 0x68 */

+  uint32_t      RESERVED0[5];  /*!< Reserved,                                                          0x6C..0x7C */

+}HRTIM_Timerx_TypeDef;

+

+/* HRTIM common register definition */

+typedef struct

+{

+  __IO uint32_t CR1;        /*!< HRTIM control register1,                                    Address offset: 0x00 */

+  __IO uint32_t CR2;        /*!< HRTIM control register2,                                    Address offset: 0x04 */

+  __IO uint32_t ISR;        /*!< HRTIM interrupt status register,                            Address offset: 0x08 */

+  __IO uint32_t ICR;        /*!< HRTIM interrupt clear register,                             Address offset: 0x0C */

+  __IO uint32_t IER;        /*!< HRTIM interrupt enable register,                            Address offset: 0x10 */

+  __IO uint32_t OENR;       /*!< HRTIM Output enable register,                               Address offset: 0x14 */

+  __IO uint32_t ODISR;      /*!< HRTIM Output disable register,                              Address offset: 0x18 */

+  __IO uint32_t ODSR;       /*!< HRTIM Output disable status register,                       Address offset: 0x1C */

+  __IO uint32_t BMCR;       /*!< HRTIM Burst mode control register,                          Address offset: 0x20 */

+  __IO uint32_t BMTRGR;     /*!< HRTIM Busrt mode trigger register,                          Address offset: 0x24 */

+  __IO uint32_t BMCMPR;     /*!< HRTIM Burst mode compare register,                          Address offset: 0x28 */

+  __IO uint32_t BMPER;      /*!< HRTIM Burst mode period register,                           Address offset: 0x2C */

+  __IO uint32_t EECR1;      /*!< HRTIM Timer external event control register1,               Address offset: 0x30 */

+  __IO uint32_t EECR2;      /*!< HRTIM Timer external event control register2,               Address offset: 0x34 */

+  __IO uint32_t EECR3;      /*!< HRTIM Timer external event control register3,               Address offset: 0x38 */

+  __IO uint32_t ADC1R;      /*!< HRTIM ADC Trigger 1 register,                               Address offset: 0x3C */

+  __IO uint32_t ADC2R;      /*!< HRTIM ADC Trigger 2 register,                               Address offset: 0x40 */

+  __IO uint32_t ADC3R;      /*!< HRTIM ADC Trigger 3 register,                               Address offset: 0x44 */

+  __IO uint32_t ADC4R;      /*!< HRTIM ADC Trigger 4 register,                               Address offset: 0x48 */

+  __IO uint32_t RESERVED0;  /*!< Reserved,                                                   Address offset: 0x4C */

+  __IO uint32_t FLTINR1;    /*!< HRTIM Fault input register1,                                Address offset: 0x50 */

+  __IO uint32_t FLTINR2;    /*!< HRTIM Fault input register2,                                Address offset: 0x54 */

+  __IO uint32_t BDMUPR;     /*!< HRTIM Burst DMA Master Timer update register,               Address offset: 0x58 */

+  __IO uint32_t BDTAUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x5C */

+  __IO uint32_t BDTBUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x60 */

+  __IO uint32_t BDTCUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x64 */

+  __IO uint32_t BDTDUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x68 */

+  __IO uint32_t BDTEUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x6C */

+  __IO uint32_t BDMADR;     /*!< HRTIM Burst DMA Master Data register,                       Address offset: 0x70 */

+}HRTIM_Common_TypeDef;

+

+/* HRTIM  register definition */

+typedef struct {

+  HRTIM_Master_TypeDef sMasterRegs;

+  HRTIM_Timerx_TypeDef sTimerxRegs[5];

+  uint32_t             RESERVED0[32];

+  HRTIM_Common_TypeDef sCommonRegs;

+}HRTIM_TypeDef;

+/**

+  * @brief RNG

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */

+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */

+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */

+} RNG_TypeDef;

+

+/**

+  * @brief MDIOS

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;

+  __IO uint32_t WRFR;

+  __IO uint32_t CWRFR;

+  __IO uint32_t RDFR;

+  __IO uint32_t CRDFR;

+  __IO uint32_t SR;

+  __IO uint32_t CLRFR;

+  uint32_t RESERVED[57];

+  __IO uint32_t DINR0;

+  __IO uint32_t DINR1;

+  __IO uint32_t DINR2;

+  __IO uint32_t DINR3;

+  __IO uint32_t DINR4;

+  __IO uint32_t DINR5;

+  __IO uint32_t DINR6;

+  __IO uint32_t DINR7;

+  __IO uint32_t DINR8;

+  __IO uint32_t DINR9;

+  __IO uint32_t DINR10;

+  __IO uint32_t DINR11;

+  __IO uint32_t DINR12;

+  __IO uint32_t DINR13;

+  __IO uint32_t DINR14;

+  __IO uint32_t DINR15;

+  __IO uint32_t DINR16;

+  __IO uint32_t DINR17;

+  __IO uint32_t DINR18;

+  __IO uint32_t DINR19;

+  __IO uint32_t DINR20;

+  __IO uint32_t DINR21;

+  __IO uint32_t DINR22;

+  __IO uint32_t DINR23;

+  __IO uint32_t DINR24;

+  __IO uint32_t DINR25;

+  __IO uint32_t DINR26;

+  __IO uint32_t DINR27;

+  __IO uint32_t DINR28;

+  __IO uint32_t DINR29;

+  __IO uint32_t DINR30;

+  __IO uint32_t DINR31;

+  __IO uint32_t DOUTR0;

+  __IO uint32_t DOUTR1;

+  __IO uint32_t DOUTR2;

+  __IO uint32_t DOUTR3;

+  __IO uint32_t DOUTR4;

+  __IO uint32_t DOUTR5;

+  __IO uint32_t DOUTR6;

+  __IO uint32_t DOUTR7;

+  __IO uint32_t DOUTR8;

+  __IO uint32_t DOUTR9;

+  __IO uint32_t DOUTR10;

+  __IO uint32_t DOUTR11;

+  __IO uint32_t DOUTR12;

+  __IO uint32_t DOUTR13;

+  __IO uint32_t DOUTR14;

+  __IO uint32_t DOUTR15;

+  __IO uint32_t DOUTR16;

+  __IO uint32_t DOUTR17;

+  __IO uint32_t DOUTR18;

+  __IO uint32_t DOUTR19;

+  __IO uint32_t DOUTR20;

+  __IO uint32_t DOUTR21;

+  __IO uint32_t DOUTR22;

+  __IO uint32_t DOUTR23;

+  __IO uint32_t DOUTR24;

+  __IO uint32_t DOUTR25;

+  __IO uint32_t DOUTR26;

+  __IO uint32_t DOUTR27;

+  __IO uint32_t DOUTR28;

+  __IO uint32_t DOUTR29;

+  __IO uint32_t DOUTR30;

+  __IO uint32_t DOUTR31;

+} MDIOS_TypeDef;

+

+

+/**

+  * @brief USB_OTG_Core_Registers

+  */

+typedef struct

+{

+ __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */

+  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */

+  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */

+  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */

+  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */

+  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */

+  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */

+  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */

+  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */

+  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */

+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */

+  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */

+  uint32_t Reserved30[2];             /*!< Reserved                                     030h */

+  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */

+  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */

+  __IO uint32_t GSNPSID;              /* USB_OTG core ID                                040h*/

+  __IO uint32_t GHWCFG1;              /* User HW config1                                044h*/

+  __IO uint32_t GHWCFG2;              /* User HW config2                                048h*/

+  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */

+  uint32_t  Reserved6;                /*!< Reserved                                     050h */

+  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */

+  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */

+  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */

+   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */

+    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */

+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */

+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */

+} USB_OTG_GlobalTypeDef;

+

+

+/**

+  * @brief USB_OTG_device_Registers

+  */

+typedef struct

+{

+  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */

+  __IO uint32_t DCTL;            /*!< dev Control Register         804h */

+  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */

+  uint32_t Reserved0C;           /*!< Reserved                     80Ch */

+  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */

+  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */

+  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */

+  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */

+  uint32_t  Reserved20;          /*!< Reserved                     820h */

+  uint32_t Reserved9;            /*!< Reserved                     824h */

+  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */

+  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */

+  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */

+  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */

+  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */

+  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */

+  uint32_t Reserved40;           /*!< dedicated EP mask            840h */

+  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */

+  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */

+  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */

+} USB_OTG_DeviceTypeDef;

+

+

+/**

+  * @brief USB_OTG_IN_Endpoint-Specific_Register

+  */

+typedef struct

+{

+  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */

+  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */

+  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */

+  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */

+  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */

+  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */

+  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */

+  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */

+} USB_OTG_INEndpointTypeDef;

+

+

+/**

+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */

+  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */

+  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */

+  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */

+  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */

+  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */

+  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */

+} USB_OTG_OUTEndpointTypeDef;

+

+

+/**

+  * @brief USB_OTG_Host_Mode_Register_Structures

+  */

+typedef struct

+{

+  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */

+  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */

+  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */

+  uint32_t Reserved40C;           /*!< Reserved                             40Ch */

+  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */

+  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */

+  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */

+} USB_OTG_HostTypeDef;

+

+/**

+  * @brief USB_OTG_Host_Channel_Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */

+  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */

+  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */

+  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */

+  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */

+  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */

+  uint32_t Reserved[2];           /*!< Reserved                                      */

+} USB_OTG_HostChannelTypeDef;

+/**

+  * @}

+  */

+

+

+/** @addtogroup Peripheral_memory_map

+  * @{

+  */

+#define D1_ITCMRAM_BASE           (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM  */

+#define D1_ITCMICP_BASE           (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM         */

+#define D1_DTCMRAM_BASE           (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM                            */

+#define D1_AXIFLASH_BASE          (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI                */

+#define D1_AXIICP_BASE            (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI          */

+#define D1_AXISRAM_BASE           (0x24000000UL) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI                */

+

+#define D2_AXISRAM_BASE           (0x10000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI                */

+#define D2_AHBSRAM_BASE           (0x30000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge    */

+

+#define D3_BKPSRAM_BASE           (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge                                */

+#define D3_SRAM_BASE              (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge                               */

+

+#define PERIPH_BASE               (0x40000000UL) /*!< Base address of : AHB/APB Peripherals                                                   */

+#define QSPI_BASE                 (0x90000000UL) /*!< Base address of : QSPI memories  accessible over AXI                                    */

+

+#define FLASH_BANK1_BASE          (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI                          */

+#define FLASH_BANK2_BASE          (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI                          */

+#define FLASH_END                 (0x081FFFFFUL) /*!< FLASH end address                                                                       */

+

+/* Legacy define */

+#define FLASH_BASE                FLASH_BANK1_BASE

+

+/*!< Device electronic signature memory map */

+#define UID_BASE                  (0x1FF1E800UL)            /*!< Unique device ID register base address */

+#define FLASHSIZE_BASE            (0x1FF1E880UL)            /*!< FLASH Size register base address */

+

+

+/*!< Peripheral memory map */

+#define D2_APB1PERIPH_BASE        PERIPH_BASE

+#define D2_APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)

+#define D2_AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)

+#define D2_AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)

+

+#define D1_APB1PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)

+#define D1_AHB1PERIPH_BASE       (PERIPH_BASE + 0x12000000UL)

+

+#define D3_APB1PERIPH_BASE       (PERIPH_BASE + 0x18000000UL)

+#define D3_AHB1PERIPH_BASE       (PERIPH_BASE + 0x18020000UL)

+

+/*!< Legacy Peripheral memory map */

+#define APB1PERIPH_BASE        PERIPH_BASE

+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)

+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)

+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)

+

+

+/*!< D1_AHB1PERIPH peripherals */

+

+#define MDMA_BASE             (D1_AHB1PERIPH_BASE + 0x0000UL)

+#define DMA2D_BASE            (D1_AHB1PERIPH_BASE + 0x1000UL)

+#define JPGDEC_BASE           (D1_AHB1PERIPH_BASE + 0x3000UL)

+#define FLASH_R_BASE          (D1_AHB1PERIPH_BASE + 0x2000UL)

+#define FMC_R_BASE            (D1_AHB1PERIPH_BASE + 0x4000UL)

+#define QSPI_R_BASE           (D1_AHB1PERIPH_BASE + 0x5000UL)

+#define DLYB_QSPI_BASE        (D1_AHB1PERIPH_BASE + 0x6000UL)

+#define SDMMC1_BASE           (D1_AHB1PERIPH_BASE + 0x7000UL)

+#define DLYB_SDMMC1_BASE      (D1_AHB1PERIPH_BASE + 0x8000UL)

+#define RAMECC1_BASE          (D1_AHB1PERIPH_BASE + 0x9000UL)

+

+/*!< D2_AHB1PERIPH peripherals */

+

+#define DMA1_BASE               (D2_AHB1PERIPH_BASE + 0x0000UL)

+#define DMA2_BASE               (D2_AHB1PERIPH_BASE + 0x0400UL)

+#define DMAMUX1_BASE            (D2_AHB1PERIPH_BASE + 0x0800UL)

+#define ADC1_BASE               (D2_AHB1PERIPH_BASE + 0x2000UL)

+#define ADC2_BASE               (D2_AHB1PERIPH_BASE + 0x2100UL)

+#define ADC12_COMMON_BASE       (D2_AHB1PERIPH_BASE + 0x2300UL)

+#define ART_BASE                (D2_AHB1PERIPH_BASE + 0x4400UL)

+#define ETH_BASE                (D2_AHB1PERIPH_BASE + 0x8000UL)

+#define ETH_MAC_BASE            (ETH_BASE)

+

+/*!< USB registers base address */

+#define USB1_OTG_HS_PERIPH_BASE              (0x40040000UL)

+#define USB2_OTG_FS_PERIPH_BASE              (0x40080000UL)

+#define USB_OTG_GLOBAL_BASE                  (0x000UL)

+#define USB_OTG_DEVICE_BASE                  (0x800UL)

+#define USB_OTG_IN_ENDPOINT_BASE             (0x900UL)

+#define USB_OTG_OUT_ENDPOINT_BASE            (0xB00UL)

+#define USB_OTG_EP_REG_SIZE                  (0x20UL)

+#define USB_OTG_HOST_BASE                    (0x400UL)

+#define USB_OTG_HOST_PORT_BASE               (0x440UL)

+#define USB_OTG_HOST_CHANNEL_BASE            (0x500UL)

+#define USB_OTG_HOST_CHANNEL_SIZE            (0x20UL)

+#define USB_OTG_PCGCCTL_BASE                 (0xE00UL)

+#define USB_OTG_FIFO_BASE                    (0x1000UL)

+#define USB_OTG_FIFO_SIZE                    (0x1000UL)

+

+/*!< D2_AHB2PERIPH peripherals */

+

+#define DCMI_BASE              (D2_AHB2PERIPH_BASE + 0x0000UL)

+#define RNG_BASE               (D2_AHB2PERIPH_BASE + 0x1800UL)

+#define SDMMC2_BASE            (D2_AHB2PERIPH_BASE + 0x2400UL)

+#define DLYB_SDMMC2_BASE       (D2_AHB2PERIPH_BASE + 0x2800UL)

+#define RAMECC2_BASE           (D2_AHB2PERIPH_BASE + 0x3000UL)

+

+/*!< D3_AHB1PERIPH peripherals */

+#define GPIOA_BASE            (D3_AHB1PERIPH_BASE + 0x0000UL)

+#define GPIOB_BASE            (D3_AHB1PERIPH_BASE + 0x0400UL)

+#define GPIOC_BASE            (D3_AHB1PERIPH_BASE + 0x0800UL)

+#define GPIOD_BASE            (D3_AHB1PERIPH_BASE + 0x0C00UL)

+#define GPIOE_BASE            (D3_AHB1PERIPH_BASE + 0x1000UL)

+#define GPIOF_BASE            (D3_AHB1PERIPH_BASE + 0x1400UL)

+#define GPIOG_BASE            (D3_AHB1PERIPH_BASE + 0x1800UL)

+#define GPIOH_BASE            (D3_AHB1PERIPH_BASE + 0x1C00UL)

+#define GPIOI_BASE            (D3_AHB1PERIPH_BASE + 0x2000UL)

+#define GPIOJ_BASE            (D3_AHB1PERIPH_BASE + 0x2400UL)

+#define GPIOK_BASE            (D3_AHB1PERIPH_BASE + 0x2800UL)

+#define RCC_BASE              (D3_AHB1PERIPH_BASE + 0x4400UL)

+#define RCC_C1_BASE           (RCC_BASE + 0x130UL)

+#define RCC_C2_BASE           (RCC_BASE + 0x190UL)

+#define PWR_BASE              (D3_AHB1PERIPH_BASE + 0x4800UL)

+#define CRC_BASE              (D3_AHB1PERIPH_BASE + 0x4C00UL)

+#define BDMA_BASE             (D3_AHB1PERIPH_BASE + 0x5400UL)

+#define DMAMUX2_BASE          (D3_AHB1PERIPH_BASE + 0x5800UL)

+#define ADC3_BASE             (D3_AHB1PERIPH_BASE + 0x6000UL)

+#define ADC3_COMMON_BASE      (D3_AHB1PERIPH_BASE + 0x6300UL)

+#define HSEM_BASE             (D3_AHB1PERIPH_BASE + 0x6400UL)

+#define RAMECC3_BASE          (D3_AHB1PERIPH_BASE + 0x7000UL)

+

+/*!< D1_APB1PERIPH peripherals */

+#define LTDC_BASE             (D1_APB1PERIPH_BASE + 0x1000UL)

+#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84UL)

+#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104UL)

+#define WWDG1_BASE            (D1_APB1PERIPH_BASE + 0x3000UL)

+

+/*!< D2_APB1PERIPH peripherals */

+#define TIM2_BASE             (D2_APB1PERIPH_BASE + 0x0000UL)

+#define TIM3_BASE             (D2_APB1PERIPH_BASE + 0x0400UL)

+#define TIM4_BASE             (D2_APB1PERIPH_BASE + 0x0800UL)

+#define TIM5_BASE             (D2_APB1PERIPH_BASE + 0x0C00UL)

+#define TIM6_BASE             (D2_APB1PERIPH_BASE + 0x1000UL)

+#define TIM7_BASE             (D2_APB1PERIPH_BASE + 0x1400UL)

+#define TIM12_BASE            (D2_APB1PERIPH_BASE + 0x1800UL)

+#define TIM13_BASE            (D2_APB1PERIPH_BASE + 0x1C00UL)

+#define TIM14_BASE            (D2_APB1PERIPH_BASE + 0x2000UL)

+#define LPTIM1_BASE           (D2_APB1PERIPH_BASE + 0x2400UL)

+

+#define WWDG2_BASE            (D2_APB1PERIPH_BASE + 0x2C00UL)

+

+#define SPI2_BASE             (D2_APB1PERIPH_BASE + 0x3800UL)

+#define SPI3_BASE             (D2_APB1PERIPH_BASE + 0x3C00UL)

+#define SPDIFRX_BASE          (D2_APB1PERIPH_BASE + 0x4000UL)

+#define USART2_BASE           (D2_APB1PERIPH_BASE + 0x4400UL)

+#define USART3_BASE           (D2_APB1PERIPH_BASE + 0x4800UL)

+#define UART4_BASE            (D2_APB1PERIPH_BASE + 0x4C00UL)

+#define UART5_BASE            (D2_APB1PERIPH_BASE + 0x5000UL)

+#define I2C1_BASE             (D2_APB1PERIPH_BASE + 0x5400UL)

+#define I2C2_BASE             (D2_APB1PERIPH_BASE + 0x5800UL)

+#define I2C3_BASE             (D2_APB1PERIPH_BASE + 0x5C00UL)

+#define CEC_BASE              (D2_APB1PERIPH_BASE + 0x6C00UL)

+#define DAC1_BASE             (D2_APB1PERIPH_BASE + 0x7400UL)

+#define UART7_BASE            (D2_APB1PERIPH_BASE + 0x7800UL)

+#define UART8_BASE            (D2_APB1PERIPH_BASE + 0x7C00UL)

+#define CRS_BASE              (D2_APB1PERIPH_BASE + 0x8400UL)

+#define SWPMI1_BASE           (D2_APB1PERIPH_BASE + 0x8800UL)

+#define OPAMP_BASE            (D2_APB1PERIPH_BASE + 0x9000UL)

+#define OPAMP1_BASE           (D2_APB1PERIPH_BASE + 0x9000UL)

+#define OPAMP2_BASE           (D2_APB1PERIPH_BASE + 0x9010UL)

+#define MDIOS_BASE            (D2_APB1PERIPH_BASE + 0x9400UL)

+#define FDCAN1_BASE           (D2_APB1PERIPH_BASE + 0xA000UL)

+#define FDCAN2_BASE           (D2_APB1PERIPH_BASE + 0xA400UL)

+#define FDCAN_CCU_BASE        (D2_APB1PERIPH_BASE + 0xA800UL)

+#define SRAMCAN_BASE          (D2_APB1PERIPH_BASE + 0xAC00UL)

+

+/*!< D2_APB2PERIPH peripherals */

+

+#define TIM1_BASE             (D2_APB2PERIPH_BASE + 0x0000UL)

+#define TIM8_BASE             (D2_APB2PERIPH_BASE + 0x0400UL)

+#define USART1_BASE           (D2_APB2PERIPH_BASE + 0x1000UL)

+#define USART6_BASE           (D2_APB2PERIPH_BASE + 0x1400UL)

+#define SPI1_BASE             (D2_APB2PERIPH_BASE + 0x3000UL)

+#define SPI4_BASE             (D2_APB2PERIPH_BASE + 0x3400UL)

+#define TIM15_BASE            (D2_APB2PERIPH_BASE + 0x4000UL)

+#define TIM16_BASE            (D2_APB2PERIPH_BASE + 0x4400UL)

+#define TIM17_BASE            (D2_APB2PERIPH_BASE + 0x4800UL)

+#define SPI5_BASE             (D2_APB2PERIPH_BASE + 0x5000UL)

+#define SAI1_BASE             (D2_APB2PERIPH_BASE + 0x5800UL)

+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)

+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)

+#define SAI2_BASE             (D2_APB2PERIPH_BASE + 0x5C00UL)

+#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004UL)

+#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024UL)

+#define SAI3_BASE             (D2_APB2PERIPH_BASE + 0x6000UL)

+#define SAI3_Block_A_BASE     (SAI3_BASE + 0x004UL)

+#define SAI3_Block_B_BASE     (SAI3_BASE + 0x024UL)

+#define DFSDM1_BASE           (D2_APB2PERIPH_BASE + 0x7000UL)

+#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00UL)

+#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20UL)

+#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40UL)

+#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60UL)

+#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80UL)

+#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0UL)

+#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0UL)

+#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0UL)

+#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)

+#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)

+#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)

+#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)

+#define HRTIM1_BASE           (D2_APB2PERIPH_BASE + 0x7400UL)

+#define HRTIM1_TIMA_BASE      (HRTIM1_BASE + 0x00000080UL)

+#define HRTIM1_TIMB_BASE      (HRTIM1_BASE + 0x00000100UL)

+#define HRTIM1_TIMC_BASE      (HRTIM1_BASE + 0x00000180UL)

+#define HRTIM1_TIMD_BASE      (HRTIM1_BASE + 0x00000200UL)

+#define HRTIM1_TIME_BASE      (HRTIM1_BASE + 0x00000280UL)

+#define HRTIM1_COMMON_BASE    (HRTIM1_BASE + 0x00000380UL)

+

+

+/*!< D3_APB1PERIPH peripherals */

+#define EXTI_BASE             (D3_APB1PERIPH_BASE + 0x0000UL)

+#define EXTI_D1_BASE          (EXTI_BASE + 0x0080UL)

+#define EXTI_D2_BASE          (EXTI_BASE + 0x00C0UL)

+#define SYSCFG_BASE           (D3_APB1PERIPH_BASE + 0x0400UL)

+#define LPUART1_BASE          (D3_APB1PERIPH_BASE + 0x0C00UL)

+#define SPI6_BASE             (D3_APB1PERIPH_BASE + 0x1400UL)

+#define I2C4_BASE             (D3_APB1PERIPH_BASE + 0x1C00UL)

+#define LPTIM2_BASE           (D3_APB1PERIPH_BASE + 0x2400UL)

+#define LPTIM3_BASE           (D3_APB1PERIPH_BASE + 0x2800UL)

+#define LPTIM4_BASE           (D3_APB1PERIPH_BASE + 0x2C00UL)

+#define LPTIM5_BASE           (D3_APB1PERIPH_BASE + 0x3000UL)

+#define COMP12_BASE           (D3_APB1PERIPH_BASE + 0x3800UL)

+#define COMP1_BASE            (COMP12_BASE + 0x0CUL)

+#define COMP2_BASE            (COMP12_BASE + 0x10UL)

+#define VREFBUF_BASE          (D3_APB1PERIPH_BASE + 0x3C00UL)

+#define RTC_BASE              (D3_APB1PERIPH_BASE + 0x4000UL)

+#define IWDG1_BASE            (D3_APB1PERIPH_BASE + 0x4800UL)

+

+#define IWDG2_BASE            (D3_APB1PERIPH_BASE + 0x4C00UL)

+

+#define SAI4_BASE             (D3_APB1PERIPH_BASE + 0x5400UL)

+#define SAI4_Block_A_BASE     (SAI4_BASE + 0x004UL)

+#define SAI4_Block_B_BASE     (SAI4_BASE + 0x024UL)

+

+

+

+

+#define BDMA_Channel0_BASE    (BDMA_BASE + 0x0008UL)

+#define BDMA_Channel1_BASE    (BDMA_BASE + 0x001CUL)

+#define BDMA_Channel2_BASE    (BDMA_BASE + 0x0030UL)

+#define BDMA_Channel3_BASE    (BDMA_BASE + 0x0044UL)

+#define BDMA_Channel4_BASE    (BDMA_BASE + 0x0058UL)

+#define BDMA_Channel5_BASE    (BDMA_BASE + 0x006CUL)

+#define BDMA_Channel6_BASE    (BDMA_BASE + 0x0080UL)

+#define BDMA_Channel7_BASE    (BDMA_BASE + 0x0094UL)

+

+#define DMAMUX2_Channel0_BASE    (DMAMUX2_BASE)

+#define DMAMUX2_Channel1_BASE    (DMAMUX2_BASE + 0x0004UL)

+#define DMAMUX2_Channel2_BASE    (DMAMUX2_BASE + 0x0008UL)

+#define DMAMUX2_Channel3_BASE    (DMAMUX2_BASE + 0x000CUL)

+#define DMAMUX2_Channel4_BASE    (DMAMUX2_BASE + 0x0010UL)

+#define DMAMUX2_Channel5_BASE    (DMAMUX2_BASE + 0x0014UL)

+#define DMAMUX2_Channel6_BASE    (DMAMUX2_BASE + 0x0018UL)

+#define DMAMUX2_Channel7_BASE    (DMAMUX2_BASE + 0x001CUL)

+

+#define DMAMUX2_RequestGenerator0_BASE  (DMAMUX2_BASE + 0x0100UL)

+#define DMAMUX2_RequestGenerator1_BASE  (DMAMUX2_BASE + 0x0104UL)

+#define DMAMUX2_RequestGenerator2_BASE  (DMAMUX2_BASE + 0x0108UL)

+#define DMAMUX2_RequestGenerator3_BASE  (DMAMUX2_BASE + 0x010CUL)

+#define DMAMUX2_RequestGenerator4_BASE  (DMAMUX2_BASE + 0x0110UL)

+#define DMAMUX2_RequestGenerator5_BASE  (DMAMUX2_BASE + 0x0114UL)

+#define DMAMUX2_RequestGenerator6_BASE  (DMAMUX2_BASE + 0x0118UL)

+#define DMAMUX2_RequestGenerator7_BASE  (DMAMUX2_BASE + 0x011CUL)

+

+#define DMAMUX2_ChannelStatus_BASE      (DMAMUX2_BASE + 0x0080UL)

+#define DMAMUX2_RequestGenStatus_BASE   (DMAMUX2_BASE + 0x0140UL)

+

+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)

+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)

+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)

+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)

+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)

+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)

+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)

+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)

+

+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)

+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)

+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)

+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)

+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)

+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)

+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)

+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)

+

+#define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)

+#define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)

+#define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)

+#define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)

+#define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)

+#define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)

+#define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0018UL)

+#define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x001CUL)

+#define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0020UL)

+#define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x0024UL)

+#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)

+#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)

+#define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)

+#define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)

+#define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)

+#define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)

+

+#define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)

+#define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)

+#define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)

+#define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)

+#define DMAMUX1_RequestGenerator4_BASE  (DMAMUX1_BASE + 0x0110UL)

+#define DMAMUX1_RequestGenerator5_BASE  (DMAMUX1_BASE + 0x0114UL)

+#define DMAMUX1_RequestGenerator6_BASE  (DMAMUX1_BASE + 0x0118UL)

+#define DMAMUX1_RequestGenerator7_BASE  (DMAMUX1_BASE + 0x011CUL)

+

+#define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)

+#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)

+

+/*!< FMC Banks registers base  address */

+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)

+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)

+#define FMC_Bank2_R_BASE      (FMC_R_BASE + 0x0060UL)

+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)

+#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)

+

+/* Debug MCU registers base address */

+#define DBGMCU_BASE           (0x5C001000UL)

+

+#define MDMA_Channel0_BASE    (MDMA_BASE + 0x00000040UL)

+#define MDMA_Channel1_BASE    (MDMA_BASE + 0x00000080UL)

+#define MDMA_Channel2_BASE    (MDMA_BASE + 0x000000C0UL)

+#define MDMA_Channel3_BASE    (MDMA_BASE + 0x00000100UL)

+#define MDMA_Channel4_BASE    (MDMA_BASE + 0x00000140UL)

+#define MDMA_Channel5_BASE    (MDMA_BASE + 0x00000180UL)

+#define MDMA_Channel6_BASE    (MDMA_BASE + 0x000001C0UL)

+#define MDMA_Channel7_BASE    (MDMA_BASE + 0x00000200UL)

+#define MDMA_Channel8_BASE    (MDMA_BASE + 0x00000240UL)

+#define MDMA_Channel9_BASE    (MDMA_BASE + 0x00000280UL)

+#define MDMA_Channel10_BASE   (MDMA_BASE + 0x000002C0UL)

+#define MDMA_Channel11_BASE   (MDMA_BASE + 0x00000300UL)

+#define MDMA_Channel12_BASE   (MDMA_BASE + 0x00000340UL)

+#define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)

+#define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)

+#define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)

+

+#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)

+#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)

+#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)

+#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)

+#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)

+

+#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)

+#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)

+#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)

+#define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL)

+#define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL)

+

+#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)

+#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)

+

+

+/**

+  * @}

+  */

+

+/** @addtogroup Peripheral_declaration

+  * @{

+  */

+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)

+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)

+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)

+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)

+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)

+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)

+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)

+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)

+#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)

+#define RTC                 ((RTC_TypeDef *) RTC_BASE)

+#define WWDG1               ((WWDG_TypeDef *) WWDG1_BASE)

+

+#define WWDG2               ((WWDG_TypeDef *) WWDG2_BASE)

+#define IWDG2               ((IWDG_TypeDef *) IWDG2_BASE)

+

+#define IWDG1               ((IWDG_TypeDef *) IWDG1_BASE)

+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)

+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)

+#define SPI4                ((SPI_TypeDef *) SPI4_BASE)

+#define SPI5                ((SPI_TypeDef *) SPI5_BASE)

+#define SPI6                ((SPI_TypeDef *) SPI6_BASE)

+#define USART2              ((USART_TypeDef *) USART2_BASE)

+#define USART3              ((USART_TypeDef *) USART3_BASE)

+#define USART6              ((USART_TypeDef *) USART6_BASE)

+#define UART7               ((USART_TypeDef *) UART7_BASE)

+#define UART8               ((USART_TypeDef *) UART8_BASE)

+#define CRS                 ((CRS_TypeDef *) CRS_BASE)

+#define UART4               ((USART_TypeDef *) UART4_BASE)

+#define UART5               ((USART_TypeDef *) UART5_BASE)

+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)

+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)

+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)

+#define I2C4                ((I2C_TypeDef *) I2C4_BASE)

+#define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

+#define FDCAN2              ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

+#define FDCAN_CCU           ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

+#define CEC                 ((CEC_TypeDef *) CEC_BASE)

+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)

+#define PWR                 ((PWR_TypeDef *) PWR_BASE)

+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)

+#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)

+#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)

+#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)

+#define LPTIM3              ((LPTIM_TypeDef *) LPTIM3_BASE)

+#define LPTIM4              ((LPTIM_TypeDef *) LPTIM4_BASE)

+#define LPTIM5              ((LPTIM_TypeDef *) LPTIM5_BASE)

+

+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)

+#define COMP12              ((COMPOPT_TypeDef *) COMP12_BASE)

+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)

+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)

+#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)

+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)

+#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)

+#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)

+

+

+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)

+#define EXTI_D1             ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

+#define EXTI_D2             ((EXTI_Core_TypeDef *) EXTI_D2_BASE)

+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)

+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)

+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)

+#define USART1              ((USART_TypeDef *) USART1_BASE)

+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)

+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)

+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)

+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)

+#define HRTIM1              ((HRTIM_TypeDef *) HRTIM1_BASE)

+#define HRTIM1_TIMA         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)

+#define HRTIM1_TIMB         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)

+#define HRTIM1_TIMC         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)

+#define HRTIM1_TIMD         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)

+#define HRTIM1_TIME         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)

+#define HRTIM1_COMMON       ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)

+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)

+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

+#define SAI2                ((SAI_TypeDef *) SAI2_BASE)

+#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)

+#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)

+#define SAI3                ((SAI_TypeDef *) SAI3_BASE)

+#define SAI3_Block_A        ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)

+#define SAI3_Block_B        ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)

+#define SAI4                ((SAI_TypeDef *) SAI4_BASE)

+#define SAI4_Block_A        ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)

+#define SAI4_Block_B        ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)

+

+#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

+#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

+#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

+#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

+#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

+#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

+#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

+#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

+#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

+#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

+#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

+#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

+#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

+#define DMA2D               ((DMA2D_TypeDef *) DMA2D_BASE)

+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)

+#define RCC                 ((RCC_TypeDef *) RCC_BASE)

+#define RCC_C1              ((RCC_Core_TypeDef *) RCC_C1_BASE)

+#define RCC_C2              ((RCC_Core_TypeDef *) RCC_C2_BASE)

+

+#define ART                 ((ART_TypeDef *)  ART_BASE)

+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)

+#define CRC                 ((CRC_TypeDef *) CRC_BASE)

+

+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)

+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)

+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)

+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)

+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)

+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)

+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)

+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)

+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)

+#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)

+#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)

+

+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)

+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)

+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)

+#define ADC3_COMMON         ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)

+#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

+

+#define RNG                 ((RNG_TypeDef *) RNG_BASE)

+#define SDMMC2              ((SDMMC_TypeDef *) SDMMC2_BASE)

+#define DLYB_SDMMC2         ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

+

+#define BDMA                ((BDMA_TypeDef *) BDMA_BASE)

+#define BDMA_Channel0       ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)

+#define BDMA_Channel1       ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)

+#define BDMA_Channel2       ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)

+#define BDMA_Channel3       ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)

+#define BDMA_Channel4       ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)

+#define BDMA_Channel5       ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)

+#define BDMA_Channel6       ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)

+#define BDMA_Channel7       ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)

+

+#define RAMECC1              ((RAMECC_TypeDef *)RAMECC1_BASE)

+#define RAMECC1_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)

+#define RAMECC1_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)

+#define RAMECC1_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)

+#define RAMECC1_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)

+#define RAMECC1_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)

+

+#define RAMECC2              ((RAMECC_TypeDef *)RAMECC2_BASE)

+#define RAMECC2_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)

+#define RAMECC2_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)

+#define RAMECC2_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)

+#define RAMECC2_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)

+#define RAMECC2_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)

+

+#define RAMECC3              ((RAMECC_TypeDef *)RAMECC3_BASE)

+#define RAMECC3_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)

+#define RAMECC3_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)

+

+#define DMAMUX2                ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

+#define DMAMUX2_Channel0       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

+#define DMAMUX2_Channel1       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

+#define DMAMUX2_Channel2       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

+#define DMAMUX2_Channel3       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

+#define DMAMUX2_Channel4       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

+#define DMAMUX2_Channel5       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

+#define DMAMUX2_Channel6       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

+#define DMAMUX2_Channel7       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

+

+

+#define DMAMUX2_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

+#define DMAMUX2_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

+#define DMAMUX2_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

+#define DMAMUX2_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

+#define DMAMUX2_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

+#define DMAMUX2_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

+#define DMAMUX2_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

+#define DMAMUX2_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

+

+#define DMAMUX2_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

+#define DMAMUX2_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

+

+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)

+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

+

+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)

+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

+

+

+#define DMAMUX1              ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

+#define DMAMUX1_Channel0     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

+#define DMAMUX1_Channel1     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

+#define DMAMUX1_Channel2     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

+#define DMAMUX1_Channel3     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

+#define DMAMUX1_Channel4     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

+#define DMAMUX1_Channel5     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

+#define DMAMUX1_Channel6     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

+#define DMAMUX1_Channel7     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

+#define DMAMUX1_Channel8     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

+#define DMAMUX1_Channel9     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

+#define DMAMUX1_Channel10    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

+#define DMAMUX1_Channel11    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

+#define DMAMUX1_Channel12    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

+#define DMAMUX1_Channel13    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

+#define DMAMUX1_Channel14    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

+#define DMAMUX1_Channel15    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

+

+#define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

+#define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

+#define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

+#define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

+#define DMAMUX1_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

+#define DMAMUX1_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

+#define DMAMUX1_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

+#define DMAMUX1_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

+

+#define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *)    DMAMUX1_ChannelStatus_BASE)

+#define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

+

+

+#define FMC_Bank1_R           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

+#define FMC_Bank1E_R          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

+#define FMC_Bank2_R           ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

+#define FMC_Bank3_R           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

+#define FMC_Bank5_6_R         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

+

+

+#define QUADSPI               ((QUADSPI_TypeDef *) QSPI_R_BASE)

+#define DLYB_QUADSPI          ((DLYB_TypeDef *) DLYB_QSPI_BASE)

+#define SDMMC1                ((SDMMC_TypeDef *) SDMMC1_BASE)

+#define DLYB_SDMMC1           ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

+

+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)

+

+#define JPEG                ((JPEG_TypeDef *) JPGDEC_BASE)

+#define HSEM                ((HSEM_TypeDef *) HSEM_BASE)

+#if defined(CORE_CM4)

+#define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x110UL))

+#else  /* CORE_CM7 */

+#define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

+#endif /* CORE_CM4 */

+

+#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)

+#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

+#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

+

+#define MDIOS               ((MDIOS_TypeDef *) MDIOS_BASE)

+

+#define ETH                 ((ETH_TypeDef *)ETH_BASE)

+#define MDMA                ((MDMA_TypeDef *)MDMA_BASE)

+#define MDMA_Channel0       ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

+#define MDMA_Channel1       ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

+#define MDMA_Channel2       ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

+#define MDMA_Channel3       ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

+#define MDMA_Channel4       ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

+#define MDMA_Channel5       ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

+#define MDMA_Channel6       ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

+#define MDMA_Channel7       ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

+#define MDMA_Channel8       ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

+#define MDMA_Channel9       ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

+#define MDMA_Channel10      ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

+#define MDMA_Channel11      ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

+#define MDMA_Channel12      ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

+#define MDMA_Channel13      ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

+#define MDMA_Channel14      ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

+#define MDMA_Channel15      ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

+

+

+#define USB1_OTG_HS         ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

+#define USB2_OTG_FS         ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)

+

+/* Legacy defines */

+#define USB_OTG_HS                   USB1_OTG_HS

+#define USB_OTG_HS_PERIPH_BASE       USB1_OTG_HS_PERIPH_BASE

+#define USB_OTG_FS                   USB2_OTG_FS

+#define USB_OTG_FS_PERIPH_BASE       USB2_OTG_FS_PERIPH_BASE

+

+/**

+  * @}

+  */

+

+/** @addtogroup Exported_constants

+  * @{

+  */

+

+  /** @addtogroup Peripheral_Registers_Bits_Definition

+  * @{

+  */

+

+/******************************************************************************/

+/*                         Peripheral Registers_Bits_Definition               */

+/******************************************************************************/

+

+/******************************************************************************/

+/*                                                                            */

+/*                        Analog to Digital Converter                         */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  ADC VERSION  ********************************/

+#define ADC_VER_V5_X

+/********************  Bit definition for ADC_ISR register  ********************/

+#define ADC_ISR_ADRDY_Pos                 (0U)

+#define ADC_ISR_ADRDY_Msk                 (0x1UL << ADC_ISR_ADRDY_Pos)         /*!< 0x00000001 */

+#define ADC_ISR_ADRDY                     ADC_ISR_ADRDY_Msk                    /*!< ADC Ready (ADRDY) flag  */

+#define ADC_ISR_EOSMP_Pos                 (1U)

+#define ADC_ISR_EOSMP_Msk                 (0x1UL << ADC_ISR_EOSMP_Pos)         /*!< 0x00000002 */

+#define ADC_ISR_EOSMP                     ADC_ISR_EOSMP_Msk                    /*!< ADC End of Sampling flag */

+#define ADC_ISR_EOC_Pos                   (2U)

+#define ADC_ISR_EOC_Msk                   (0x1UL << ADC_ISR_EOC_Pos)           /*!< 0x00000004 */

+#define ADC_ISR_EOC                       ADC_ISR_EOC_Msk                      /*!< ADC End of Regular Conversion flag */

+#define ADC_ISR_EOS_Pos                   (3U)

+#define ADC_ISR_EOS_Msk                   (0x1UL << ADC_ISR_EOS_Pos)           /*!< 0x00000008 */

+#define ADC_ISR_EOS                       ADC_ISR_EOS_Msk                      /*!< ADC End of Regular sequence of Conversions flag */

+#define ADC_ISR_OVR_Pos                   (4U)

+#define ADC_ISR_OVR_Msk                   (0x1UL << ADC_ISR_OVR_Pos)           /*!< 0x00000010 */

+#define ADC_ISR_OVR                       ADC_ISR_OVR_Msk                      /*!< ADC overrun flag */

+#define ADC_ISR_JEOC_Pos                  (5U)

+#define ADC_ISR_JEOC_Msk                  (0x1UL << ADC_ISR_JEOC_Pos)          /*!< 0x00000020 */

+#define ADC_ISR_JEOC                      ADC_ISR_JEOC_Msk                     /*!< ADC End of Injected Conversion flag */

+#define ADC_ISR_JEOS_Pos                  (6U)

+#define ADC_ISR_JEOS_Msk                  (0x1UL << ADC_ISR_JEOS_Pos)          /*!< 0x00000040 */

+#define ADC_ISR_JEOS                      ADC_ISR_JEOS_Msk                     /*!< ADC End of Injected sequence of Conversions flag */

+#define ADC_ISR_AWD1_Pos                  (7U)

+#define ADC_ISR_AWD1_Msk                  (0x1UL << ADC_ISR_AWD1_Pos)          /*!< 0x00000080 */

+#define ADC_ISR_AWD1                      ADC_ISR_AWD1_Msk                     /*!< ADC Analog watchdog 1 flag */

+#define ADC_ISR_AWD2_Pos                  (8U)

+#define ADC_ISR_AWD2_Msk                  (0x1UL << ADC_ISR_AWD2_Pos)          /*!< 0x00000100 */

+#define ADC_ISR_AWD2                      ADC_ISR_AWD2_Msk                     /*!< ADC Analog watchdog 2 flag */

+#define ADC_ISR_AWD3_Pos                  (9U)

+#define ADC_ISR_AWD3_Msk                  (0x1UL << ADC_ISR_AWD3_Pos)          /*!< 0x00000200 */

+#define ADC_ISR_AWD3                      ADC_ISR_AWD3_Msk                     /*!< ADC Analog watchdog 3 flag */

+#define ADC_ISR_JQOVF_Pos                 (10U)

+#define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */

+#define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */

+

+/********************  Bit definition for ADC_IER register  ********************/

+#define ADC_IER_ADRDYIE_Pos               (0U)

+#define ADC_IER_ADRDYIE_Msk               (0x1UL << ADC_IER_ADRDYIE_Pos)       /*!< 0x00000001 */

+#define ADC_IER_ADRDYIE                   ADC_IER_ADRDYIE_Msk                  /*!< ADC Ready (ADRDY) interrupt source */

+#define ADC_IER_EOSMPIE_Pos               (1U)

+#define ADC_IER_EOSMPIE_Msk               (0x1UL << ADC_IER_EOSMPIE_Pos)       /*!< 0x00000002 */

+#define ADC_IER_EOSMPIE                   ADC_IER_EOSMPIE_Msk                  /*!< ADC End of Sampling interrupt source */

+#define ADC_IER_EOCIE_Pos                 (2U)

+#define ADC_IER_EOCIE_Msk                 (0x1UL << ADC_IER_EOCIE_Pos)         /*!< 0x00000004 */

+#define ADC_IER_EOCIE                     ADC_IER_EOCIE_Msk                    /*!< ADC End of Regular Conversion interrupt source */

+#define ADC_IER_EOSIE_Pos                 (3U)

+#define ADC_IER_EOSIE_Msk                 (0x1UL << ADC_IER_EOSIE_Pos)         /*!< 0x00000008 */

+#define ADC_IER_EOSIE                     ADC_IER_EOSIE_Msk                    /*!< ADC End of Regular sequence of Conversions interrupt source */

+#define ADC_IER_OVRIE_Pos                 (4U)

+#define ADC_IER_OVRIE_Msk                 (0x1UL << ADC_IER_OVRIE_Pos)         /*!< 0x00000010 */

+#define ADC_IER_OVRIE                     ADC_IER_OVRIE_Msk                    /*!< ADC overrun interrupt source */

+#define ADC_IER_JEOCIE_Pos                (5U)

+#define ADC_IER_JEOCIE_Msk                (0x1UL << ADC_IER_JEOCIE_Pos)        /*!< 0x00000020 */

+#define ADC_IER_JEOCIE                    ADC_IER_JEOCIE_Msk                   /*!< ADC End of Injected Conversion interrupt source */

+#define ADC_IER_JEOSIE_Pos                (6U)

+#define ADC_IER_JEOSIE_Msk                (0x1UL << ADC_IER_JEOSIE_Pos)        /*!< 0x00000040 */

+#define ADC_IER_JEOSIE                    ADC_IER_JEOSIE_Msk                   /*!< ADC End of Injected sequence of Conversions interrupt source */

+#define ADC_IER_AWD1IE_Pos                (7U)

+#define ADC_IER_AWD1IE_Msk                (0x1UL << ADC_IER_AWD1IE_Pos)        /*!< 0x00000080 */

+#define ADC_IER_AWD1IE                    ADC_IER_AWD1IE_Msk                   /*!< ADC Analog watchdog 1 interrupt source */

+#define ADC_IER_AWD2IE_Pos                (8U)

+#define ADC_IER_AWD2IE_Msk                (0x1UL << ADC_IER_AWD2IE_Pos)        /*!< 0x00000100 */

+#define ADC_IER_AWD2IE                    ADC_IER_AWD2IE_Msk                   /*!< ADC Analog watchdog 2 interrupt source */

+#define ADC_IER_AWD3IE_Pos                (9U)

+#define ADC_IER_AWD3IE_Msk                (0x1UL << ADC_IER_AWD3IE_Pos)        /*!< 0x00000200 */

+#define ADC_IER_AWD3IE                    ADC_IER_AWD3IE_Msk                   /*!< ADC Analog watchdog 3 interrupt source */

+#define ADC_IER_JQOVFIE_Pos               (10U)

+#define ADC_IER_JQOVFIE_Msk               (0x1UL << ADC_IER_JQOVFIE_Pos)       /*!< 0x00000400 */

+#define ADC_IER_JQOVFIE                   ADC_IER_JQOVFIE_Msk                  /*!< ADC Injected Context Queue Overflow interrupt source */

+

+/********************  Bit definition for ADC_CR register  ********************/

+#define ADC_CR_ADEN_Pos                   (0U)

+#define ADC_CR_ADEN_Msk                   (0x1UL << ADC_CR_ADEN_Pos)           /*!< 0x00000001 */

+#define ADC_CR_ADEN                       ADC_CR_ADEN_Msk                      /*!< ADC Enable control */

+#define ADC_CR_ADDIS_Pos                  (1U)

+#define ADC_CR_ADDIS_Msk                  (0x1UL << ADC_CR_ADDIS_Pos)          /*!< 0x00000002 */

+#define ADC_CR_ADDIS                      ADC_CR_ADDIS_Msk                     /*!< ADC Disable command */

+#define ADC_CR_ADSTART_Pos                (2U)

+#define ADC_CR_ADSTART_Msk                (0x1UL << ADC_CR_ADSTART_Pos)        /*!< 0x00000004 */

+#define ADC_CR_ADSTART                    ADC_CR_ADSTART_Msk                   /*!< ADC Start of Regular conversion */

+#define ADC_CR_JADSTART_Pos               (3U)

+#define ADC_CR_JADSTART_Msk               (0x1UL << ADC_CR_JADSTART_Pos)       /*!< 0x00000008 */

+#define ADC_CR_JADSTART                   ADC_CR_JADSTART_Msk                  /*!< ADC Start of injected conversion */

+#define ADC_CR_ADSTP_Pos                  (4U)

+#define ADC_CR_ADSTP_Msk                  (0x1UL << ADC_CR_ADSTP_Pos)          /*!< 0x00000010 */

+#define ADC_CR_ADSTP                      ADC_CR_ADSTP_Msk                     /*!< ADC Stop of Regular conversion */

+#define ADC_CR_JADSTP_Pos                 (5U)

+#define ADC_CR_JADSTP_Msk                 (0x1UL << ADC_CR_JADSTP_Pos)         /*!< 0x00000020 */

+#define ADC_CR_JADSTP                     ADC_CR_JADSTP_Msk                    /*!< ADC Stop of injected conversion */

+#define ADC_CR_BOOST_Pos                  (8U)

+#define ADC_CR_BOOST_Msk                  (0x3UL << ADC_CR_BOOST_Pos)          /*!< 0x00000300 */

+#define ADC_CR_BOOST                      ADC_CR_BOOST_Msk                     /*!< ADC Boost Mode configuration */

+#define ADC_CR_BOOST_0                    (0x1UL << ADC_CR_BOOST_Pos)           /*!< 0x00000100 */

+#define ADC_CR_BOOST_1                    (0x2UL << ADC_CR_BOOST_Pos)           /*!< 0x00000200 */

+#define ADC_CR_ADCALLIN_Pos               (16U)

+#define ADC_CR_ADCALLIN_Msk               (0x1UL << ADC_CR_ADCALLIN_Pos)       /*!< 0x00010000 */

+#define ADC_CR_ADCALLIN                   ADC_CR_ADCALLIN_Msk                  /*!< ADC Linearity calibration */

+#define ADC_CR_LINCALRDYW1_Pos            (22U)

+#define ADC_CR_LINCALRDYW1_Msk            (0x1UL << ADC_CR_LINCALRDYW1_Pos)    /*!< 0x00400000 */

+#define ADC_CR_LINCALRDYW1                ADC_CR_LINCALRDYW1_Msk               /*!< ADC Linearity calibration ready Word 1 */

+#define ADC_CR_LINCALRDYW2_Pos            (23U)

+#define ADC_CR_LINCALRDYW2_Msk            (0x1UL << ADC_CR_LINCALRDYW2_Pos)    /*!< 0x00800000 */

+#define ADC_CR_LINCALRDYW2                ADC_CR_LINCALRDYW2_Msk               /*!< ADC Linearity calibration ready Word 2 */

+#define ADC_CR_LINCALRDYW3_Pos            (24U)

+#define ADC_CR_LINCALRDYW3_Msk            (0x1UL << ADC_CR_LINCALRDYW3_Pos)    /*!< 0x01000000 */

+#define ADC_CR_LINCALRDYW3                ADC_CR_LINCALRDYW3_Msk               /*!< ADC Linearity calibration ready Word 3 */

+#define ADC_CR_LINCALRDYW4_Pos            (25U)

+#define ADC_CR_LINCALRDYW4_Msk            (0x1UL << ADC_CR_LINCALRDYW4_Pos)    /*!< 0x02000000 */

+#define ADC_CR_LINCALRDYW4                ADC_CR_LINCALRDYW4_Msk               /*!< ADC Linearity calibration ready Word 4 */

+#define ADC_CR_LINCALRDYW5_Pos            (26U)

+#define ADC_CR_LINCALRDYW5_Msk            (0x1UL << ADC_CR_LINCALRDYW5_Pos)    /*!< 0x04000000 */

+#define ADC_CR_LINCALRDYW5                ADC_CR_LINCALRDYW5_Msk               /*!< ADC Linearity calibration ready Word 5 */

+#define ADC_CR_LINCALRDYW6_Pos            (27U)

+#define ADC_CR_LINCALRDYW6_Msk            (0x1UL << ADC_CR_LINCALRDYW6_Pos)    /*!< 0x08000000 */

+#define ADC_CR_LINCALRDYW6                ADC_CR_LINCALRDYW6_Msk               /*!< ADC Linearity calibration ready Word 6 */

+#define ADC_CR_ADVREGEN_Pos               (28U)

+#define ADC_CR_ADVREGEN_Msk               (0x1UL << ADC_CR_ADVREGEN_Pos)       /*!< 0x10000000 */

+#define ADC_CR_ADVREGEN                   ADC_CR_ADVREGEN_Msk                  /*!< ADC Voltage regulator Enable */

+#define ADC_CR_DEEPPWD_Pos                (29U)

+#define ADC_CR_DEEPPWD_Msk                (0x1UL << ADC_CR_DEEPPWD_Pos)        /*!< 0x20000000 */

+#define ADC_CR_DEEPPWD                    ADC_CR_DEEPPWD_Msk                   /*!< ADC Deep power down Enable */

+#define ADC_CR_ADCALDIF_Pos               (30U)

+#define ADC_CR_ADCALDIF_Msk               (0x1UL << ADC_CR_ADCALDIF_Pos)       /*!< 0x40000000 */

+#define ADC_CR_ADCALDIF                   ADC_CR_ADCALDIF_Msk                  /*!< ADC Differential Mode for calibration */

+#define ADC_CR_ADCAL_Pos                  (31U)

+#define ADC_CR_ADCAL_Msk                  (0x1UL << ADC_CR_ADCAL_Pos)          /*!< 0x80000000 */

+#define ADC_CR_ADCAL                      ADC_CR_ADCAL_Msk                     /*!< ADC Calibration */

+

+/********************  Bit definition for ADC_CFGR register  ********************/

+#define ADC_CFGR_DMNGT_Pos                (0U)

+#define ADC_CFGR_DMNGT_Msk                (0x3UL << ADC_CFGR_DMNGT_Pos)        /*!< 0x00000003 */

+#define ADC_CFGR_DMNGT                    ADC_CFGR_DMNGT_Msk                   /*!< ADC Data Management configuration */

+#define ADC_CFGR_DMNGT_0                  (0x1UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000001 */

+#define ADC_CFGR_DMNGT_1                  (0x2UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000002 */

+

+#define ADC_CFGR_RES_Pos                  (2U)

+#define ADC_CFGR_RES_Msk                  (0x7UL << ADC_CFGR_RES_Pos)          /*!< 0x0000001C */

+#define ADC_CFGR_RES                      ADC_CFGR_RES_Msk                     /*!< ADC Data resolution */

+#define ADC_CFGR_RES_0                    (0x1UL << ADC_CFGR_RES_Pos)           /*!< 0x00000004 */

+#define ADC_CFGR_RES_1                    (0x2UL << ADC_CFGR_RES_Pos)           /*!< 0x00000008 */

+#define ADC_CFGR_RES_2                    (0x4UL << ADC_CFGR_RES_Pos)           /*!< 0x00000010 */

+

+#define ADC_CFGR_EXTSEL_Pos               (5U)

+#define ADC_CFGR_EXTSEL_Msk               (0x1FUL << ADC_CFGR_EXTSEL_Pos)      /*!< 0x000003E0 */

+#define ADC_CFGR_EXTSEL                   ADC_CFGR_EXTSEL_Msk                  /*!< ADC External trigger selection for regular group */

+#define ADC_CFGR_EXTSEL_0                 (0x01UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000020 */

+#define ADC_CFGR_EXTSEL_1                 (0x02UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000040 */

+#define ADC_CFGR_EXTSEL_2                 (0x04UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000080 */

+#define ADC_CFGR_EXTSEL_3                 (0x08UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000100 */

+#define ADC_CFGR_EXTSEL_4                 (0x10UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000200 */

+

+#define ADC_CFGR_EXTEN_Pos                (10U)

+#define ADC_CFGR_EXTEN_Msk                (0x3UL << ADC_CFGR_EXTEN_Pos)        /*!< 0x00000C00 */

+#define ADC_CFGR_EXTEN                    ADC_CFGR_EXTEN_Msk                   /*!< ADC External trigger enable and polarity selection for regular channels */

+#define ADC_CFGR_EXTEN_0                  (0x1UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000400 */

+#define ADC_CFGR_EXTEN_1                  (0x2UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000800 */

+

+#define ADC_CFGR_OVRMOD_Pos               (12U)

+#define ADC_CFGR_OVRMOD_Msk               (0x1UL << ADC_CFGR_OVRMOD_Pos)       /*!< 0x00001000 */

+#define ADC_CFGR_OVRMOD                   ADC_CFGR_OVRMOD_Msk                  /*!< ADC overrun mode */

+#define ADC_CFGR_CONT_Pos                 (13U)

+#define ADC_CFGR_CONT_Msk                 (0x1UL << ADC_CFGR_CONT_Pos)         /*!< 0x00002000 */

+#define ADC_CFGR_CONT                     ADC_CFGR_CONT_Msk                    /*!< ADC Single/continuous conversion mode for regular conversion */

+#define ADC_CFGR_AUTDLY_Pos               (14U)

+#define ADC_CFGR_AUTDLY_Msk               (0x1UL << ADC_CFGR_AUTDLY_Pos)       /*!< 0x00004000 */

+#define ADC_CFGR_AUTDLY                   ADC_CFGR_AUTDLY_Msk                  /*!< ADC Delayed conversion mode */

+

+#define ADC_CFGR_DISCEN_Pos               (16U)

+#define ADC_CFGR_DISCEN_Msk               (0x1UL << ADC_CFGR_DISCEN_Pos)       /*!< 0x00010000 */

+#define ADC_CFGR_DISCEN                   ADC_CFGR_DISCEN_Msk                  /*!< ADC Discontinuous mode for regular channels */

+

+#define ADC_CFGR_DISCNUM_Pos              (17U)

+#define ADC_CFGR_DISCNUM_Msk              (0x7UL << ADC_CFGR_DISCNUM_Pos)      /*!< 0x000E0000 */

+#define ADC_CFGR_DISCNUM                  ADC_CFGR_DISCNUM_Msk                 /*!< ADC Discontinuous mode channel count */

+#define ADC_CFGR_DISCNUM_0                (0x1UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00020000 */

+#define ADC_CFGR_DISCNUM_1                (0x2UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00040000 */

+#define ADC_CFGR_DISCNUM_2                (0x4UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00080000 */

+

+#define ADC_CFGR_JDISCEN_Pos              (20U)

+#define ADC_CFGR_JDISCEN_Msk              (0x1UL << ADC_CFGR_JDISCEN_Pos)      /*!< 0x00100000 */

+#define ADC_CFGR_JDISCEN                  ADC_CFGR_JDISCEN_Msk                 /*!< ADC Discontinuous mode on injected channels */

+#define ADC_CFGR_JQM_Pos                  (21U)

+#define ADC_CFGR_JQM_Msk                  (0x1UL << ADC_CFGR_JQM_Pos)          /*!< 0x00200000 */

+#define ADC_CFGR_JQM                      ADC_CFGR_JQM_Msk                     /*!< ADC JSQR Queue mode */

+#define ADC_CFGR_AWD1SGL_Pos              (22U)

+#define ADC_CFGR_AWD1SGL_Msk              (0x1UL << ADC_CFGR_AWD1SGL_Pos)      /*!< 0x00400000 */

+#define ADC_CFGR_AWD1SGL                  ADC_CFGR_AWD1SGL_Msk                 /*!< Enable the watchdog 1 on a single channel or on all channels */

+#define ADC_CFGR_AWD1EN_Pos               (23U)

+#define ADC_CFGR_AWD1EN_Msk               (0x1UL << ADC_CFGR_AWD1EN_Pos)       /*!< 0x00800000 */

+#define ADC_CFGR_AWD1EN                   ADC_CFGR_AWD1EN_Msk                  /*!< ADC Analog watchdog 1 enable on regular Channels */

+#define ADC_CFGR_JAWD1EN_Pos              (24U)

+#define ADC_CFGR_JAWD1EN_Msk              (0x1UL << ADC_CFGR_JAWD1EN_Pos)      /*!< 0x01000000 */

+#define ADC_CFGR_JAWD1EN                  ADC_CFGR_JAWD1EN_Msk                 /*!< ADC Analog watchdog 1 enable on injected Channels */

+#define ADC_CFGR_JAUTO_Pos                (25U)

+#define ADC_CFGR_JAUTO_Msk                (0x1UL << ADC_CFGR_JAUTO_Pos)        /*!< 0x02000000 */

+#define ADC_CFGR_JAUTO                    ADC_CFGR_JAUTO_Msk                   /*!< ADC Automatic injected group conversion */

+

+#define ADC_CFGR_AWD1CH_Pos               (26U)

+#define ADC_CFGR_AWD1CH_Msk               (0x1FUL << ADC_CFGR_AWD1CH_Pos)      /*!< 0x7C000000 */

+#define ADC_CFGR_AWD1CH                   ADC_CFGR_AWD1CH_Msk                  /*!< ADC Analog watchdog 1 Channel selection */

+#define ADC_CFGR_AWD1CH_0                 (0x01UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x04000000 */

+#define ADC_CFGR_AWD1CH_1                 (0x02UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x08000000 */

+#define ADC_CFGR_AWD1CH_2                 (0x04UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x10000000 */

+#define ADC_CFGR_AWD1CH_3                 (0x08UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x20000000 */

+#define ADC_CFGR_AWD1CH_4                 (0x10UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x40000000 */

+

+#define ADC_CFGR_JQDIS_Pos                (31U)

+#define ADC_CFGR_JQDIS_Msk                (0x1UL << ADC_CFGR_JQDIS_Pos)        /*!< 0x80000000 */

+#define ADC_CFGR_JQDIS                    ADC_CFGR_JQDIS_Msk                   /*!< ADC Injected queue disable */

+

+/********************  Bit definition for ADC_CFGR2 register  ********************/

+#define ADC_CFGR2_ROVSE_Pos               (0U)

+#define ADC_CFGR2_ROVSE_Msk               (0x1UL << ADC_CFGR2_ROVSE_Pos)       /*!< 0x00000001 */

+#define ADC_CFGR2_ROVSE                   ADC_CFGR2_ROVSE_Msk                  /*!< ADC Regular group oversampler enable */

+#define ADC_CFGR2_JOVSE_Pos               (1U)

+#define ADC_CFGR2_JOVSE_Msk               (0x1UL << ADC_CFGR2_JOVSE_Pos)       /*!< 0x00000002 */

+#define ADC_CFGR2_JOVSE                   ADC_CFGR2_JOVSE_Msk                  /*!< ADC Injected group oversampler enable */

+

+#define ADC_CFGR2_OVSS_Pos                (5U)

+#define ADC_CFGR2_OVSS_Msk                (0xFUL << ADC_CFGR2_OVSS_Pos)        /*!< 0x000001E0 */

+#define ADC_CFGR2_OVSS                    ADC_CFGR2_OVSS_Msk                   /*!< ADC Regular Oversampling shift */

+#define ADC_CFGR2_OVSS_0                  (0x1UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000020 */

+#define ADC_CFGR2_OVSS_1                  (0x2UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000040 */

+#define ADC_CFGR2_OVSS_2                  (0x4UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000080 */

+#define ADC_CFGR2_OVSS_3                  (0x8UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000100 */

+

+#define ADC_CFGR2_TROVS_Pos               (9U)

+#define ADC_CFGR2_TROVS_Msk               (0x1UL << ADC_CFGR2_TROVS_Pos)       /*!< 0x00000200 */

+#define ADC_CFGR2_TROVS                   ADC_CFGR2_TROVS_Msk                  /*!< ADC Triggered regular Oversampling */

+#define ADC_CFGR2_ROVSM_Pos               (10U)

+#define ADC_CFGR2_ROVSM_Msk               (0x1UL << ADC_CFGR2_ROVSM_Pos)       /*!< 0x00000400 */

+#define ADC_CFGR2_ROVSM                   ADC_CFGR2_ROVSM_Msk                  /*!< ADC Regular oversampling mode */

+

+#define ADC_CFGR2_RSHIFT1_Pos             (11U)

+#define ADC_CFGR2_RSHIFT1_Msk             (0x1UL << ADC_CFGR2_RSHIFT1_Pos)     /*!< 0x00000800 */

+#define ADC_CFGR2_RSHIFT1                 ADC_CFGR2_RSHIFT1_Msk                /*!< ADC Right-shift data after Offset 1 correction */

+#define ADC_CFGR2_RSHIFT2_Pos             (12U)

+#define ADC_CFGR2_RSHIFT2_Msk             (0x1UL << ADC_CFGR2_RSHIFT2_Pos)     /*!< 0x00001000 */

+#define ADC_CFGR2_RSHIFT2                 ADC_CFGR2_RSHIFT2_Msk                /*!< ADC Right-shift data after Offset 2 correction */

+#define ADC_CFGR2_RSHIFT3_Pos             (13U)

+#define ADC_CFGR2_RSHIFT3_Msk             (0x1UL << ADC_CFGR2_RSHIFT3_Pos)     /*!< 0x00002000 */

+#define ADC_CFGR2_RSHIFT3                 ADC_CFGR2_RSHIFT3_Msk                /*!< ADC Right-shift data after Offset 3 correction */

+#define ADC_CFGR2_RSHIFT4_Pos             (14U)

+#define ADC_CFGR2_RSHIFT4_Msk             (0x1UL << ADC_CFGR2_RSHIFT4_Pos)     /*!< 0x00004000 */

+#define ADC_CFGR2_RSHIFT4                 ADC_CFGR2_RSHIFT4_Msk                /*!< ADC Right-shift data after Offset 4 correction */

+

+#define ADC_CFGR2_OVSR_Pos                (16U)

+#define ADC_CFGR2_OVSR_Msk                (0x3FFUL << ADC_CFGR2_OVSR_Pos)      /*!< 0x03FF0000 */

+#define ADC_CFGR2_OVSR                    ADC_CFGR2_OVSR_Msk                   /*!< ADC oversampling Ratio */

+#define ADC_CFGR2_OVSR_0                  (0x001UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00010000 */

+#define ADC_CFGR2_OVSR_1                  (0x002UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00020000 */

+#define ADC_CFGR2_OVSR_2                  (0x004UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00040000 */

+#define ADC_CFGR2_OVSR_3                  (0x008UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00080000 */

+#define ADC_CFGR2_OVSR_4                  (0x010UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00100000 */

+#define ADC_CFGR2_OVSR_5                  (0x020UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00200000 */

+#define ADC_CFGR2_OVSR_6                  (0x040UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00400000 */

+#define ADC_CFGR2_OVSR_7                  (0x080UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00800000 */

+#define ADC_CFGR2_OVSR_8                  (0x100UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x01000000 */

+#define ADC_CFGR2_OVSR_9                  (0x200UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x02000000 */

+

+#define ADC_CFGR2_LSHIFT_Pos              (28U)

+#define ADC_CFGR2_LSHIFT_Msk              (0xFUL << ADC_CFGR2_LSHIFT_Pos)      /*!< 0xF0000000 */

+#define ADC_CFGR2_LSHIFT                  ADC_CFGR2_LSHIFT_Msk                 /*!< ADC Left shift factor */

+#define ADC_CFGR2_LSHIFT_0                (0x1UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x10000000 */

+#define ADC_CFGR2_LSHIFT_1                (0x2UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x20000000 */

+#define ADC_CFGR2_LSHIFT_2                (0x4UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x40000000 */

+#define ADC_CFGR2_LSHIFT_3                (0x8UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_SMPR1 register  ********************/

+#define ADC_SMPR1_SMP0_Pos                (0U)

+#define ADC_SMPR1_SMP0_Msk                (0x7UL << ADC_SMPR1_SMP0_Pos)        /*!< 0x00000007 */

+#define ADC_SMPR1_SMP0                    ADC_SMPR1_SMP0_Msk                   /*!< ADC Channel 0 Sampling time selection  */

+#define ADC_SMPR1_SMP0_0                  (0x1UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000001 */

+#define ADC_SMPR1_SMP0_1                  (0x2UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000002 */

+#define ADC_SMPR1_SMP0_2                  (0x4UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000004 */

+

+#define ADC_SMPR1_SMP1_Pos                (3U)

+#define ADC_SMPR1_SMP1_Msk                (0x7UL << ADC_SMPR1_SMP1_Pos)        /*!< 0x00000038 */

+#define ADC_SMPR1_SMP1                    ADC_SMPR1_SMP1_Msk                   /*!< ADC Channel 1 Sampling time selection  */

+#define ADC_SMPR1_SMP1_0                  (0x1UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000008 */

+#define ADC_SMPR1_SMP1_1                  (0x2UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000010 */

+#define ADC_SMPR1_SMP1_2                  (0x4UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000020 */

+

+#define ADC_SMPR1_SMP2_Pos                (6U)

+#define ADC_SMPR1_SMP2_Msk                (0x7UL << ADC_SMPR1_SMP2_Pos)        /*!< 0x000001C0 */

+#define ADC_SMPR1_SMP2                    ADC_SMPR1_SMP2_Msk                   /*!< ADC Channel 2 Sampling time selection  */

+#define ADC_SMPR1_SMP2_0                  (0x1UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000040 */

+#define ADC_SMPR1_SMP2_1                  (0x2UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000080 */

+#define ADC_SMPR1_SMP2_2                  (0x4UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000100 */

+

+#define ADC_SMPR1_SMP3_Pos                (9U)

+#define ADC_SMPR1_SMP3_Msk                (0x7UL << ADC_SMPR1_SMP3_Pos)        /*!< 0x00000E00 */

+#define ADC_SMPR1_SMP3                    ADC_SMPR1_SMP3_Msk                   /*!< ADC Channel 3 Sampling time selection  */

+#define ADC_SMPR1_SMP3_0                  (0x1UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000200 */

+#define ADC_SMPR1_SMP3_1                  (0x2UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000400 */

+#define ADC_SMPR1_SMP3_2                  (0x4UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000800 */

+

+#define ADC_SMPR1_SMP4_Pos                (12U)

+#define ADC_SMPR1_SMP4_Msk                (0x7UL << ADC_SMPR1_SMP4_Pos)        /*!< 0x00007000 */

+#define ADC_SMPR1_SMP4                    ADC_SMPR1_SMP4_Msk                   /*!< ADC Channel 4 Sampling time selection  */

+#define ADC_SMPR1_SMP4_0                  (0x1UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00001000 */

+#define ADC_SMPR1_SMP4_1                  (0x2UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00002000 */

+#define ADC_SMPR1_SMP4_2                  (0x4UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00004000 */

+

+#define ADC_SMPR1_SMP5_Pos                (15U)

+#define ADC_SMPR1_SMP5_Msk                (0x7UL << ADC_SMPR1_SMP5_Pos)        /*!< 0x00038000 */

+#define ADC_SMPR1_SMP5                    ADC_SMPR1_SMP5_Msk                   /*!< ADC Channel 5 Sampling time selection  */

+#define ADC_SMPR1_SMP5_0                  (0x1UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00008000 */

+#define ADC_SMPR1_SMP5_1                  (0x2UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00010000 */

+#define ADC_SMPR1_SMP5_2                  (0x4UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00020000 */

+

+#define ADC_SMPR1_SMP6_Pos                (18U)

+#define ADC_SMPR1_SMP6_Msk                (0x7UL << ADC_SMPR1_SMP6_Pos)        /*!< 0x001C0000 */

+#define ADC_SMPR1_SMP6                    ADC_SMPR1_SMP6_Msk                   /*!< ADC Channel 6 Sampling time selection  */

+#define ADC_SMPR1_SMP6_0                  (0x1UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00040000 */

+#define ADC_SMPR1_SMP6_1                  (0x2UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00080000 */

+#define ADC_SMPR1_SMP6_2                  (0x4UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00100000 */

+

+#define ADC_SMPR1_SMP7_Pos                (21U)

+#define ADC_SMPR1_SMP7_Msk                (0x7UL << ADC_SMPR1_SMP7_Pos)        /*!< 0x00E00000 */

+#define ADC_SMPR1_SMP7                    ADC_SMPR1_SMP7_Msk                   /*!< ADC Channel 7 Sampling time selection  */

+#define ADC_SMPR1_SMP7_0                  (0x1UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00200000 */

+#define ADC_SMPR1_SMP7_1                  (0x2UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00400000 */

+#define ADC_SMPR1_SMP7_2                  (0x4UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00800000 */

+

+#define ADC_SMPR1_SMP8_Pos                (24U)

+#define ADC_SMPR1_SMP8_Msk                (0x7UL << ADC_SMPR1_SMP8_Pos)        /*!< 0x07000000 */

+#define ADC_SMPR1_SMP8                    ADC_SMPR1_SMP8_Msk                   /*!< ADC Channel 8 Sampling time selection  */

+#define ADC_SMPR1_SMP8_0                  (0x1UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x01000000 */

+#define ADC_SMPR1_SMP8_1                  (0x2UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x02000000 */

+#define ADC_SMPR1_SMP8_2                  (0x4UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x04000000 */

+

+#define ADC_SMPR1_SMP9_Pos                (27U)

+#define ADC_SMPR1_SMP9_Msk                (0x7UL << ADC_SMPR1_SMP9_Pos)        /*!< 0x38000000 */

+#define ADC_SMPR1_SMP9                    ADC_SMPR1_SMP9_Msk                   /*!< ADC Channel 9 Sampling time selection  */

+#define ADC_SMPR1_SMP9_0                  (0x1UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x08000000 */

+#define ADC_SMPR1_SMP9_1                  (0x2UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x10000000 */

+#define ADC_SMPR1_SMP9_2                  (0x4UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x20000000 */

+

+/********************  Bit definition for ADC_SMPR2 register  ********************/

+#define ADC_SMPR2_SMP10_Pos               (0U)

+#define ADC_SMPR2_SMP10_Msk               (0x7UL << ADC_SMPR2_SMP10_Pos)       /*!< 0x00000007 */

+#define ADC_SMPR2_SMP10                   ADC_SMPR2_SMP10_Msk                  /*!< ADC Channel 10 Sampling time selection  */

+#define ADC_SMPR2_SMP10_0                 (0x1UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000001 */

+#define ADC_SMPR2_SMP10_1                 (0x2UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000002 */

+#define ADC_SMPR2_SMP10_2                 (0x4UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000004 */

+

+#define ADC_SMPR2_SMP11_Pos               (3U)

+#define ADC_SMPR2_SMP11_Msk               (0x7UL << ADC_SMPR2_SMP11_Pos)       /*!< 0x00000038 */

+#define ADC_SMPR2_SMP11                   ADC_SMPR2_SMP11_Msk                  /*!< ADC Channel 11 Sampling time selection  */

+#define ADC_SMPR2_SMP11_0                 (0x1UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000008 */

+#define ADC_SMPR2_SMP11_1                 (0x2UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000010 */

+#define ADC_SMPR2_SMP11_2                 (0x4UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000020 */

+

+#define ADC_SMPR2_SMP12_Pos               (6U)

+#define ADC_SMPR2_SMP12_Msk               (0x7UL << ADC_SMPR2_SMP12_Pos)       /*!< 0x000001C0 */

+#define ADC_SMPR2_SMP12                   ADC_SMPR2_SMP12_Msk                  /*!< ADC Channel 12 Sampling time selection  */

+#define ADC_SMPR2_SMP12_0                 (0x1UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000040 */

+#define ADC_SMPR2_SMP12_1                 (0x2UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000080 */

+#define ADC_SMPR2_SMP12_2                 (0x4UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000100 */

+

+#define ADC_SMPR2_SMP13_Pos               (9U)

+#define ADC_SMPR2_SMP13_Msk               (0x7UL << ADC_SMPR2_SMP13_Pos)       /*!< 0x00000E00 */

+#define ADC_SMPR2_SMP13                   ADC_SMPR2_SMP13_Msk                  /*!< ADC Channel 13 Sampling time selection  */

+#define ADC_SMPR2_SMP13_0                 (0x1UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000200 */

+#define ADC_SMPR2_SMP13_1                 (0x2UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000400 */

+#define ADC_SMPR2_SMP13_2                 (0x4UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000800 */

+

+#define ADC_SMPR2_SMP14_Pos               (12U)

+#define ADC_SMPR2_SMP14_Msk               (0x7UL << ADC_SMPR2_SMP14_Pos)       /*!< 0x00007000 */

+#define ADC_SMPR2_SMP14                   ADC_SMPR2_SMP14_Msk                  /*!< ADC Channel 14 Sampling time selection  */

+#define ADC_SMPR2_SMP14_0                 (0x1UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00001000 */

+#define ADC_SMPR2_SMP14_1                 (0x2UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00002000 */

+#define ADC_SMPR2_SMP14_2                 (0x4UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00004000 */

+

+#define ADC_SMPR2_SMP15_Pos               (15U)

+#define ADC_SMPR2_SMP15_Msk               (0x7UL << ADC_SMPR2_SMP15_Pos)       /*!< 0x00038000 */

+#define ADC_SMPR2_SMP15                   ADC_SMPR2_SMP15_Msk                  /*!< ADC Channel 15 Sampling time selection  */

+#define ADC_SMPR2_SMP15_0                 (0x1UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00008000 */

+#define ADC_SMPR2_SMP15_1                 (0x2UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00010000 */

+#define ADC_SMPR2_SMP15_2                 (0x4UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00020000 */

+

+#define ADC_SMPR2_SMP16_Pos               (18U)

+#define ADC_SMPR2_SMP16_Msk               (0x7UL << ADC_SMPR2_SMP16_Pos)       /*!< 0x001C0000 */

+#define ADC_SMPR2_SMP16                   ADC_SMPR2_SMP16_Msk                  /*!< ADC Channel 16 Sampling time selection  */

+#define ADC_SMPR2_SMP16_0                 (0x1UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00040000 */

+#define ADC_SMPR2_SMP16_1                 (0x2UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00080000 */

+#define ADC_SMPR2_SMP16_2                 (0x4UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00100000 */

+

+#define ADC_SMPR2_SMP17_Pos               (21U)

+#define ADC_SMPR2_SMP17_Msk               (0x7UL << ADC_SMPR2_SMP17_Pos)       /*!< 0x00E00000 */

+#define ADC_SMPR2_SMP17                   ADC_SMPR2_SMP17_Msk                  /*!< ADC Channel 17 Sampling time selection  */

+#define ADC_SMPR2_SMP17_0                 (0x1UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00200000 */

+#define ADC_SMPR2_SMP17_1                 (0x2UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00400000 */

+#define ADC_SMPR2_SMP17_2                 (0x4UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00800000 */

+

+#define ADC_SMPR2_SMP18_Pos               (24U)

+#define ADC_SMPR2_SMP18_Msk               (0x7UL << ADC_SMPR2_SMP18_Pos)       /*!< 0x07000000 */

+#define ADC_SMPR2_SMP18                   ADC_SMPR2_SMP18_Msk                  /*!< ADC Channel 18 Sampling time selection  */

+#define ADC_SMPR2_SMP18_0                 (0x1UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x01000000 */

+#define ADC_SMPR2_SMP18_1                 (0x2UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x02000000 */

+#define ADC_SMPR2_SMP18_2                 (0x4UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x04000000 */

+

+#define ADC_SMPR2_SMP19_Pos               (27U)

+#define ADC_SMPR2_SMP19_Msk               (0x7UL << ADC_SMPR2_SMP19_Pos)       /*!< 0x38000000 */

+#define ADC_SMPR2_SMP19                   ADC_SMPR2_SMP19_Msk                  /*!< ADC Channel 19 Sampling time selection  */

+#define ADC_SMPR2_SMP19_0                 (0x1UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x08000000 */

+#define ADC_SMPR2_SMP19_1                 (0x2UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x10000000 */

+#define ADC_SMPR2_SMP19_2                 (0x4UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x20000000 */

+

+/********************  Bit definition for ADC_PCSEL register  ********************/

+#define ADC_PCSEL_PCSEL_Pos               (0U)

+#define ADC_PCSEL_PCSEL_Msk               (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)   /*!< 0x000FFFFF */

+#define ADC_PCSEL_PCSEL                   ADC_PCSEL_PCSEL_Msk                  /*!< ADC pre channel selection */

+#define ADC_PCSEL_PCSEL_0                 (0x00001UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */

+#define ADC_PCSEL_PCSEL_1                 (0x00002UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */

+#define ADC_PCSEL_PCSEL_2                 (0x00004UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */

+#define ADC_PCSEL_PCSEL_3                 (0x00008UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */

+#define ADC_PCSEL_PCSEL_4                 (0x00010UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */

+#define ADC_PCSEL_PCSEL_5                 (0x00020UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */

+#define ADC_PCSEL_PCSEL_6                 (0x00040UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */

+#define ADC_PCSEL_PCSEL_7                 (0x00080UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */

+#define ADC_PCSEL_PCSEL_8                 (0x00100UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */

+#define ADC_PCSEL_PCSEL_9                 (0x00200UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */

+#define ADC_PCSEL_PCSEL_10                (0x00400UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */

+#define ADC_PCSEL_PCSEL_11                (0x00800UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */

+#define ADC_PCSEL_PCSEL_12                (0x01000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */

+#define ADC_PCSEL_PCSEL_13                (0x02000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */

+#define ADC_PCSEL_PCSEL_14                (0x04000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */

+#define ADC_PCSEL_PCSEL_15                (0x08000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */

+#define ADC_PCSEL_PCSEL_16                (0x10000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */

+#define ADC_PCSEL_PCSEL_17                (0x20000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */

+#define ADC_PCSEL_PCSEL_18                (0x40000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */

+#define ADC_PCSEL_PCSEL_19                (0x80000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00080000 */

+

+/*****************  Bit definition for ADC_LTR1, 2, 3 registers *****************/

+#define ADC_LTR_LT_Pos                    (0U)

+#define ADC_LTR_LT_Msk                    (0x3FFFFFFUL << ADC_LTR_LT_Pos)      /*!< 0x03FFFFFF */

+#define ADC_LTR_LT                        ADC_LTR_LT_Msk                       /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */

+

+/*****************  Bit definition for ADC_HTR1, 2, 3 registers  ****************/

+#define ADC_HTR_HT_Pos                    (0U)

+#define ADC_HTR_HT_Msk                    (0x3FFFFFFUL << ADC_HTR_HT_Pos)      /*!< 0x03FFFFFF */

+#define ADC_HTR_HT                        ADC_HTR_HT_Msk                       /*!< ADC Analog watchdog 1,2 and 3 higher threshold */

+

+

+/********************  Bit definition for ADC_SQR1 register  ********************/

+#define ADC_SQR1_L_Pos                    (0U)

+#define ADC_SQR1_L_Msk                    (0xFUL << ADC_SQR1_L_Pos)            /*!< 0x0000000F */

+#define ADC_SQR1_L                        ADC_SQR1_L_Msk                       /*!< ADC regular channel sequence lenght */

+#define ADC_SQR1_L_0                      (0x1UL << ADC_SQR1_L_Pos)             /*!< 0x00000001 */

+#define ADC_SQR1_L_1                      (0x2UL << ADC_SQR1_L_Pos)             /*!< 0x00000002 */

+#define ADC_SQR1_L_2                      (0x4UL << ADC_SQR1_L_Pos)             /*!< 0x00000004 */

+#define ADC_SQR1_L_3                      (0x8UL << ADC_SQR1_L_Pos)             /*!< 0x00000008 */

+

+#define ADC_SQR1_SQ1_Pos                  (6U)

+#define ADC_SQR1_SQ1_Msk                  (0x1FUL << ADC_SQR1_SQ1_Pos)         /*!< 0x000007C0 */

+#define ADC_SQR1_SQ1                      ADC_SQR1_SQ1_Msk                     /*!< ADC 1st conversion in regular sequence */

+#define ADC_SQR1_SQ1_0                    (0x01UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000040 */

+#define ADC_SQR1_SQ1_1                    (0x02UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000080 */

+#define ADC_SQR1_SQ1_2                    (0x04UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000100 */

+#define ADC_SQR1_SQ1_3                    (0x08UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000200 */

+#define ADC_SQR1_SQ1_4                    (0x10UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000400 */

+

+#define ADC_SQR1_SQ2_Pos                  (12U)

+#define ADC_SQR1_SQ2_Msk                  (0x1FUL << ADC_SQR1_SQ2_Pos)         /*!< 0x0001F000 */

+#define ADC_SQR1_SQ2                      ADC_SQR1_SQ2_Msk                     /*!< ADC 2nd conversion in regular sequence */

+#define ADC_SQR1_SQ2_0                    (0x01UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00001000 */

+#define ADC_SQR1_SQ2_1                    (0x02UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00002000 */

+#define ADC_SQR1_SQ2_2                    (0x04UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00004000 */

+#define ADC_SQR1_SQ2_3                    (0x08UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00008000 */

+#define ADC_SQR1_SQ2_4                    (0x10UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00010000 */

+

+#define ADC_SQR1_SQ3_Pos                  (18U)

+#define ADC_SQR1_SQ3_Msk                  (0x1FUL << ADC_SQR1_SQ3_Pos)         /*!< 0x007C0000 */

+#define ADC_SQR1_SQ3                      ADC_SQR1_SQ3_Msk                     /*!< ADC 3rd conversion in regular sequence */

+#define ADC_SQR1_SQ3_0                    (0x01UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00040000 */

+#define ADC_SQR1_SQ3_1                    (0x02UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00080000 */

+#define ADC_SQR1_SQ3_2                    (0x04UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00100000 */

+#define ADC_SQR1_SQ3_3                    (0x08UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00200000 */

+#define ADC_SQR1_SQ3_4                    (0x10UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00400000 */

+

+#define ADC_SQR1_SQ4_Pos                  (24U)

+#define ADC_SQR1_SQ4_Msk                  (0x1FUL << ADC_SQR1_SQ4_Pos)         /*!< 0x1F000000 */

+#define ADC_SQR1_SQ4                      ADC_SQR1_SQ4_Msk                     /*!< ADC 4th conversion in regular sequence */

+#define ADC_SQR1_SQ4_0                    (0x01UL << ADC_SQR1_SQ4_Pos)          /*!< 0x01000000 */

+#define ADC_SQR1_SQ4_1                    (0x02UL << ADC_SQR1_SQ4_Pos)          /*!< 0x02000000 */

+#define ADC_SQR1_SQ4_2                    (0x04UL << ADC_SQR1_SQ4_Pos)          /*!< 0x04000000 */

+#define ADC_SQR1_SQ4_3                    (0x08UL << ADC_SQR1_SQ4_Pos)          /*!< 0x08000000 */

+#define ADC_SQR1_SQ4_4                    (0x10UL << ADC_SQR1_SQ4_Pos)          /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR2 register  ********************/

+#define ADC_SQR2_SQ5_Pos                  (0U)

+#define ADC_SQR2_SQ5_Msk                  (0x1FUL << ADC_SQR2_SQ5_Pos)         /*!< 0x0000001F */

+#define ADC_SQR2_SQ5                      ADC_SQR2_SQ5_Msk                     /*!< ADC 5th conversion in regular sequence */

+#define ADC_SQR2_SQ5_0                    (0x01UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000001 */

+#define ADC_SQR2_SQ5_1                    (0x02UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000002 */

+#define ADC_SQR2_SQ5_2                    (0x04UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000004 */

+#define ADC_SQR2_SQ5_3                    (0x08UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000008 */

+#define ADC_SQR2_SQ5_4                    (0x10UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000010 */

+

+#define ADC_SQR2_SQ6_Pos                  (6U)

+#define ADC_SQR2_SQ6_Msk                  (0x1FUL << ADC_SQR2_SQ6_Pos)         /*!< 0x000007C0 */

+#define ADC_SQR2_SQ6                      ADC_SQR2_SQ6_Msk                     /*!< ADC 6th conversion in regular sequence */

+#define ADC_SQR2_SQ6_0                    (0x01UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000040 */

+#define ADC_SQR2_SQ6_1                    (0x02UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000080 */

+#define ADC_SQR2_SQ6_2                    (0x04UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000100 */

+#define ADC_SQR2_SQ6_3                    (0x08UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000200 */

+#define ADC_SQR2_SQ6_4                    (0x10UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000400 */

+

+#define ADC_SQR2_SQ7_Pos                  (12U)

+#define ADC_SQR2_SQ7_Msk                  (0x1FUL << ADC_SQR2_SQ7_Pos)         /*!< 0x0001F000 */

+#define ADC_SQR2_SQ7                      ADC_SQR2_SQ7_Msk                     /*!< ADC 7th conversion in regular sequence */

+#define ADC_SQR2_SQ7_0                    (0x01UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00001000 */

+#define ADC_SQR2_SQ7_1                    (0x02UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00002000 */

+#define ADC_SQR2_SQ7_2                    (0x04UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00004000 */

+#define ADC_SQR2_SQ7_3                    (0x08UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00008000 */

+#define ADC_SQR2_SQ7_4                    (0x10UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00010000 */

+

+#define ADC_SQR2_SQ8_Pos                  (18U)

+#define ADC_SQR2_SQ8_Msk                  (0x1FUL << ADC_SQR2_SQ8_Pos)         /*!< 0x007C0000 */

+#define ADC_SQR2_SQ8                      ADC_SQR2_SQ8_Msk                     /*!< ADC 8th conversion in regular sequence */

+#define ADC_SQR2_SQ8_0                    (0x01UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00040000 */

+#define ADC_SQR2_SQ8_1                    (0x02UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00080000 */

+#define ADC_SQR2_SQ8_2                    (0x04UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00100000 */

+#define ADC_SQR2_SQ8_3                    (0x08UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00200000 */

+#define ADC_SQR2_SQ8_4                    (0x10UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00400000 */

+

+#define ADC_SQR2_SQ9_Pos                  (24U)

+#define ADC_SQR2_SQ9_Msk                  (0x1FUL << ADC_SQR2_SQ9_Pos)         /*!< 0x1F000000 */

+#define ADC_SQR2_SQ9                      ADC_SQR2_SQ9_Msk                     /*!< ADC 9th conversion in regular sequence */

+#define ADC_SQR2_SQ9_0                    (0x01UL << ADC_SQR2_SQ9_Pos)          /*!< 0x01000000 */

+#define ADC_SQR2_SQ9_1                    (0x02UL << ADC_SQR2_SQ9_Pos)          /*!< 0x02000000 */

+#define ADC_SQR2_SQ9_2                    (0x04UL << ADC_SQR2_SQ9_Pos)          /*!< 0x04000000 */

+#define ADC_SQR2_SQ9_3                    (0x08UL << ADC_SQR2_SQ9_Pos)          /*!< 0x08000000 */

+#define ADC_SQR2_SQ9_4                    (0x10UL << ADC_SQR2_SQ9_Pos)          /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR3 register  ********************/

+#define ADC_SQR3_SQ10_Pos                 (0U)

+#define ADC_SQR3_SQ10_Msk                 (0x1FUL << ADC_SQR3_SQ10_Pos)        /*!< 0x0000001F */

+#define ADC_SQR3_SQ10                     ADC_SQR3_SQ10_Msk                    /*!< ADC 10th conversion in regular sequence */

+#define ADC_SQR3_SQ10_0                   (0x01UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000001 */

+#define ADC_SQR3_SQ10_1                   (0x02UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000002 */

+#define ADC_SQR3_SQ10_2                   (0x04UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000004 */

+#define ADC_SQR3_SQ10_3                   (0x08UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000008 */

+#define ADC_SQR3_SQ10_4                   (0x10UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000010 */

+

+#define ADC_SQR3_SQ11_Pos                 (6U)

+#define ADC_SQR3_SQ11_Msk                 (0x1FUL << ADC_SQR3_SQ11_Pos)        /*!< 0x000007C0 */

+#define ADC_SQR3_SQ11                     ADC_SQR3_SQ11_Msk                    /*!< ADC 11th conversion in regular sequence */

+#define ADC_SQR3_SQ11_0                   (0x01UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000040 */

+#define ADC_SQR3_SQ11_1                   (0x02UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000080 */

+#define ADC_SQR3_SQ11_2                   (0x04UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000100 */

+#define ADC_SQR3_SQ11_3                   (0x08UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000200 */

+#define ADC_SQR3_SQ11_4                   (0x10UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000400 */

+

+#define ADC_SQR3_SQ12_Pos                 (12U)

+#define ADC_SQR3_SQ12_Msk                 (0x1FUL << ADC_SQR3_SQ12_Pos)        /*!< 0x0001F000 */

+#define ADC_SQR3_SQ12                     ADC_SQR3_SQ12_Msk                    /*!< ADC 12th conversion in regular sequence */

+#define ADC_SQR3_SQ12_0                   (0x01UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00001000 */

+#define ADC_SQR3_SQ12_1                   (0x02UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00002000 */

+#define ADC_SQR3_SQ12_2                   (0x04UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00004000 */

+#define ADC_SQR3_SQ12_3                   (0x08UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00008000 */

+#define ADC_SQR3_SQ12_4                   (0x10UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00010000 */

+

+#define ADC_SQR3_SQ13_Pos                 (18U)

+#define ADC_SQR3_SQ13_Msk                 (0x1FUL << ADC_SQR3_SQ13_Pos)        /*!< 0x007C0000 */

+#define ADC_SQR3_SQ13                     ADC_SQR3_SQ13_Msk                    /*!< ADC 13th conversion in regular sequence */

+#define ADC_SQR3_SQ13_0                   (0x01UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00040000 */

+#define ADC_SQR3_SQ13_1                   (0x02UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00080000 */

+#define ADC_SQR3_SQ13_2                   (0x04UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00100000 */

+#define ADC_SQR3_SQ13_3                   (0x08UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00200000 */

+#define ADC_SQR3_SQ13_4                   (0x10UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00400000 */

+

+#define ADC_SQR3_SQ14_Pos                 (24U)

+#define ADC_SQR3_SQ14_Msk                 (0x1FUL << ADC_SQR3_SQ14_Pos)        /*!< 0x1F000000 */

+#define ADC_SQR3_SQ14                     ADC_SQR3_SQ14_Msk                    /*!< ADC 14th conversion in regular sequence */

+#define ADC_SQR3_SQ14_0                   (0x01UL << ADC_SQR3_SQ14_Pos)         /*!< 0x01000000 */

+#define ADC_SQR3_SQ14_1                   (0x02UL << ADC_SQR3_SQ14_Pos)         /*!< 0x02000000 */

+#define ADC_SQR3_SQ14_2                   (0x04UL << ADC_SQR3_SQ14_Pos)         /*!< 0x04000000 */

+#define ADC_SQR3_SQ14_3                   (0x08UL << ADC_SQR3_SQ14_Pos)         /*!< 0x08000000 */

+#define ADC_SQR3_SQ14_4                   (0x10UL << ADC_SQR3_SQ14_Pos)         /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR4 register  ********************/

+#define ADC_SQR4_SQ15_Pos                 (0U)

+#define ADC_SQR4_SQ15_Msk                 (0x1FUL << ADC_SQR4_SQ15_Pos)        /*!< 0x0000001F */

+#define ADC_SQR4_SQ15                     ADC_SQR4_SQ15_Msk                    /*!< ADC 15th conversion in regular sequence */

+#define ADC_SQR4_SQ15_0                   (0x01UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000001 */

+#define ADC_SQR4_SQ15_1                   (0x02UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000002 */

+#define ADC_SQR4_SQ15_2                   (0x04UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000004 */

+#define ADC_SQR4_SQ15_3                   (0x08UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000008 */

+#define ADC_SQR4_SQ15_4                   (0x10UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000010 */

+

+#define ADC_SQR4_SQ16_Pos                 (6U)

+#define ADC_SQR4_SQ16_Msk                 (0x1FUL << ADC_SQR4_SQ16_Pos)        /*!< 0x000007C0 */

+#define ADC_SQR4_SQ16                     ADC_SQR4_SQ16_Msk                    /*!< ADC 16th conversion in regular sequence */

+#define ADC_SQR4_SQ16_0                   (0x01UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000040 */

+#define ADC_SQR4_SQ16_1                   (0x02UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000080 */

+#define ADC_SQR4_SQ16_2                   (0x04UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000100 */

+#define ADC_SQR4_SQ16_3                   (0x08UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000200 */

+#define ADC_SQR4_SQ16_4                   (0x10UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000400 */

+/********************  Bit definition for ADC_DR register  ********************/

+#define ADC_DR_RDATA_Pos                  (0U)

+#define ADC_DR_RDATA_Msk                  (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)   /*!< 0xFFFFFFFF */

+#define ADC_DR_RDATA                      ADC_DR_RDATA_Msk                     /*!< ADC regular Data converted */

+

+/********************  Bit definition for ADC_JSQR register  ********************/

+#define ADC_JSQR_JL_Pos                   (0U)

+#define ADC_JSQR_JL_Msk                   (0x3UL << ADC_JSQR_JL_Pos)           /*!< 0x00000003 */

+#define ADC_JSQR_JL                       ADC_JSQR_JL_Msk                      /*!< ADC injected channel sequence length */

+#define ADC_JSQR_JL_0                     (0x1UL << ADC_JSQR_JL_Pos)           /*!< 0x00000001 */

+#define ADC_JSQR_JL_1                     (0x2UL << ADC_JSQR_JL_Pos)           /*!< 0x00000002 */

+

+#define ADC_JSQR_JEXTSEL_Pos              (2U)

+#define ADC_JSQR_JEXTSEL_Msk              (0x1FUL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x0000007C */

+#define ADC_JSQR_JEXTSEL                  ADC_JSQR_JEXTSEL_Msk                 /*!< ADC external trigger selection for injected group */

+#define ADC_JSQR_JEXTSEL_0                (0x01UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000004 */

+#define ADC_JSQR_JEXTSEL_1                (0x02UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000008 */

+#define ADC_JSQR_JEXTSEL_2                (0x04UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000010 */

+#define ADC_JSQR_JEXTSEL_3                (0x08UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000020 */

+#define ADC_JSQR_JEXTSEL_4                (0x10UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000040 */

+

+#define ADC_JSQR_JEXTEN_Pos               (7U)

+#define ADC_JSQR_JEXTEN_Msk               (0x3UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000180 */

+#define ADC_JSQR_JEXTEN                   ADC_JSQR_JEXTEN_Msk                  /*!< ADC external trigger enable and polarity selection for injected channels */

+#define ADC_JSQR_JEXTEN_0                 (0x1UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000080 */

+#define ADC_JSQR_JEXTEN_1                 (0x2UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000100 */

+

+#define ADC_JSQR_JSQ1_Pos                 (9U)

+#define ADC_JSQR_JSQ1_Msk                 (0x1FUL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00003E00 */

+#define ADC_JSQR_JSQ1                     ADC_JSQR_JSQ1_Msk                    /*!< ADC 1st conversion in injected sequence */

+#define ADC_JSQR_JSQ1_0                   (0x01UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000200 */

+#define ADC_JSQR_JSQ1_1                   (0x02UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000400 */

+#define ADC_JSQR_JSQ1_2                   (0x04UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000800 */

+#define ADC_JSQR_JSQ1_3                   (0x08UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00001000 */

+#define ADC_JSQR_JSQ1_4                   (0x10UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00002000 */

+

+#define ADC_JSQR_JSQ2_Pos                 (15U)

+#define ADC_JSQR_JSQ2_Msk                 (0x1FUL << ADC_JSQR_JSQ2_Pos)        /*!< 0x000F8000 */

+#define ADC_JSQR_JSQ2                     ADC_JSQR_JSQ2_Msk                    /*!< ADC 2nd conversion in injected sequence */

+#define ADC_JSQR_JSQ2_0                   (0x01UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00008000 */

+#define ADC_JSQR_JSQ2_1                   (0x02UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00010000 */

+#define ADC_JSQR_JSQ2_2                   (0x04UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00020000 */

+#define ADC_JSQR_JSQ2_3                   (0x08UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00040000 */

+#define ADC_JSQR_JSQ2_4                   (0x10UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00080000 */

+

+#define ADC_JSQR_JSQ3_Pos                 (21U)

+#define ADC_JSQR_JSQ3_Msk                 (0x1FUL << ADC_JSQR_JSQ3_Pos)        /*!< 0x03E00000 */

+#define ADC_JSQR_JSQ3                     ADC_JSQR_JSQ3_Msk                    /*!< ADC 3rd conversion in injected sequence */

+#define ADC_JSQR_JSQ3_0                   (0x01UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00200000 */

+#define ADC_JSQR_JSQ3_1                   (0x02UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00400000 */

+#define ADC_JSQR_JSQ3_2                   (0x04UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00800000 */

+#define ADC_JSQR_JSQ3_3                   (0x08UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x01000000 */

+#define ADC_JSQR_JSQ3_4                   (0x10UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x02000000 */

+

+#define ADC_JSQR_JSQ4_Pos                 (27U)

+#define ADC_JSQR_JSQ4_Msk                 (0x1FUL << ADC_JSQR_JSQ4_Pos)        /*!< 0xF8000000 */

+#define ADC_JSQR_JSQ4                     ADC_JSQR_JSQ4_Msk                    /*!< ADC 4th conversion in injected sequence */

+#define ADC_JSQR_JSQ4_0                   (0x01UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x08000000 */

+#define ADC_JSQR_JSQ4_1                   (0x02UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x10000000 */

+#define ADC_JSQR_JSQ4_2                   (0x04UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x20000000 */

+#define ADC_JSQR_JSQ4_3                   (0x08UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x40000000 */

+#define ADC_JSQR_JSQ4_4                   (0x10UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_OFR1 register  ********************/

+#define ADC_OFR1_OFFSET1_Pos              (0U)

+#define ADC_OFR1_OFFSET1_Msk              (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR1_OFFSET1                  ADC_OFR1_OFFSET1_Msk                  /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */

+#define ADC_OFR1_OFFSET1_0                (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */

+#define ADC_OFR1_OFFSET1_1                (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */

+#define ADC_OFR1_OFFSET1_2                (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */

+#define ADC_OFR1_OFFSET1_3                (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */

+#define ADC_OFR1_OFFSET1_4                (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */

+#define ADC_OFR1_OFFSET1_5                (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */

+#define ADC_OFR1_OFFSET1_6                (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */

+#define ADC_OFR1_OFFSET1_7                (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */

+#define ADC_OFR1_OFFSET1_8                (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */

+#define ADC_OFR1_OFFSET1_9                (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */

+#define ADC_OFR1_OFFSET1_10               (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */

+#define ADC_OFR1_OFFSET1_11               (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */

+#define ADC_OFR1_OFFSET1_12               (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */

+#define ADC_OFR1_OFFSET1_13               (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */

+#define ADC_OFR1_OFFSET1_14               (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */

+#define ADC_OFR1_OFFSET1_15               (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */

+#define ADC_OFR1_OFFSET1_16               (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */

+#define ADC_OFR1_OFFSET1_17               (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */

+#define ADC_OFR1_OFFSET1_18               (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */

+#define ADC_OFR1_OFFSET1_19               (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */

+#define ADC_OFR1_OFFSET1_20               (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */

+#define ADC_OFR1_OFFSET1_21               (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */

+#define ADC_OFR1_OFFSET1_22               (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */

+#define ADC_OFR1_OFFSET1_23               (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */

+#define ADC_OFR1_OFFSET1_24               (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */

+#define ADC_OFR1_OFFSET1_25               (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR1_OFFSET1_CH_Pos           (26U)

+#define ADC_OFR1_OFFSET1_CH_Msk           (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR1_OFFSET1_CH               ADC_OFR1_OFFSET1_CH_Msk               /*!< ADC Channel selection for the data offset 1 */

+#define ADC_OFR1_OFFSET1_CH_0             (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR1_OFFSET1_CH_1             (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR1_OFFSET1_CH_2             (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR1_OFFSET1_CH_3             (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR1_OFFSET1_CH_4             (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR1_SSATE_Pos                (31U)

+#define ADC_OFR1_SSATE_Msk                (0x1UL << ADC_OFR1_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR1_SSATE                    ADC_OFR1_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR2 register  ********************/

+#define ADC_OFR2_OFFSET2_Pos              (0U)

+#define ADC_OFR2_OFFSET2_Msk              (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR2_OFFSET2                  ADC_OFR2_OFFSET2_Msk                  /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */

+#define ADC_OFR2_OFFSET2_0                (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */

+#define ADC_OFR2_OFFSET2_1                (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */

+#define ADC_OFR2_OFFSET2_2                (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */

+#define ADC_OFR2_OFFSET2_3                (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */

+#define ADC_OFR2_OFFSET2_4                (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */

+#define ADC_OFR2_OFFSET2_5                (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */

+#define ADC_OFR2_OFFSET2_6                (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */

+#define ADC_OFR2_OFFSET2_7                (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */

+#define ADC_OFR2_OFFSET2_8                (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */

+#define ADC_OFR2_OFFSET2_9                (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */

+#define ADC_OFR2_OFFSET2_10               (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */

+#define ADC_OFR2_OFFSET2_11               (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */

+#define ADC_OFR2_OFFSET2_12               (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */

+#define ADC_OFR2_OFFSET2_13               (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */

+#define ADC_OFR2_OFFSET2_14               (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */

+#define ADC_OFR2_OFFSET2_15               (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */

+#define ADC_OFR2_OFFSET2_16               (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */

+#define ADC_OFR2_OFFSET2_17               (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */

+#define ADC_OFR2_OFFSET2_18               (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */

+#define ADC_OFR2_OFFSET2_19               (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */

+#define ADC_OFR2_OFFSET2_20               (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */

+#define ADC_OFR2_OFFSET2_21               (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */

+#define ADC_OFR2_OFFSET2_22               (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */

+#define ADC_OFR2_OFFSET2_23               (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */

+#define ADC_OFR2_OFFSET2_24               (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */

+#define ADC_OFR2_OFFSET2_25               (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR2_OFFSET2_CH_Pos           (26U)

+#define ADC_OFR2_OFFSET2_CH_Msk           (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR2_OFFSET2_CH               ADC_OFR2_OFFSET2_CH_Msk               /*!< ADC Channel selection for the data offset 2 */

+#define ADC_OFR2_OFFSET2_CH_0             (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR2_OFFSET2_CH_1             (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR2_OFFSET2_CH_2             (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR2_OFFSET2_CH_3             (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR2_OFFSET2_CH_4             (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR2_SSATE_Pos                (31U)

+#define ADC_OFR2_SSATE_Msk                (0x1UL << ADC_OFR2_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR2_SSATE                    ADC_OFR2_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR3 register  ********************/

+#define ADC_OFR3_OFFSET3_Pos              (0U)

+#define ADC_OFR3_OFFSET3_Msk              (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR3_OFFSET3                  ADC_OFR3_OFFSET3_Msk                  /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */

+#define ADC_OFR3_OFFSET3_0                (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */

+#define ADC_OFR3_OFFSET3_1                (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */

+#define ADC_OFR3_OFFSET3_2                (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */

+#define ADC_OFR3_OFFSET3_3                (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */

+#define ADC_OFR3_OFFSET3_4                (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */

+#define ADC_OFR3_OFFSET3_5                (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */

+#define ADC_OFR3_OFFSET3_6                (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */

+#define ADC_OFR3_OFFSET3_7                (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */

+#define ADC_OFR3_OFFSET3_8                (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */

+#define ADC_OFR3_OFFSET3_9                (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */

+#define ADC_OFR3_OFFSET3_10               (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */

+#define ADC_OFR3_OFFSET3_11               (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */

+#define ADC_OFR3_OFFSET3_12               (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */

+#define ADC_OFR3_OFFSET3_13               (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */

+#define ADC_OFR3_OFFSET3_14               (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */

+#define ADC_OFR3_OFFSET3_15               (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */

+#define ADC_OFR3_OFFSET3_16               (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */

+#define ADC_OFR3_OFFSET3_17               (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */

+#define ADC_OFR3_OFFSET3_18               (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */

+#define ADC_OFR3_OFFSET3_19               (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */

+#define ADC_OFR3_OFFSET3_20               (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */

+#define ADC_OFR3_OFFSET3_21               (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */

+#define ADC_OFR3_OFFSET3_22               (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */

+#define ADC_OFR3_OFFSET3_23               (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */

+#define ADC_OFR3_OFFSET3_24               (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */

+#define ADC_OFR3_OFFSET3_25               (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR3_OFFSET3_CH_Pos           (26U)

+#define ADC_OFR3_OFFSET3_CH_Msk           (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR3_OFFSET3_CH               ADC_OFR3_OFFSET3_CH_Msk               /*!< ADC Channel selection for the data offset 3 */

+#define ADC_OFR3_OFFSET3_CH_0             (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR3_OFFSET3_CH_1             (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR3_OFFSET3_CH_2             (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR3_OFFSET3_CH_3             (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR3_OFFSET3_CH_4             (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR3_SSATE_Pos                (31U)

+#define ADC_OFR3_SSATE_Msk                (0x1UL << ADC_OFR3_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR3_SSATE                    ADC_OFR3_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR4 register  ********************/

+#define ADC_OFR4_OFFSET4_Pos              (0U)

+#define ADC_OFR4_OFFSET4_Msk              (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR4_OFFSET4                  ADC_OFR4_OFFSET4_Msk                  /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */

+#define ADC_OFR4_OFFSET4_0                (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */

+#define ADC_OFR4_OFFSET4_1                (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */

+#define ADC_OFR4_OFFSET4_2                (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */

+#define ADC_OFR4_OFFSET4_3                (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */

+#define ADC_OFR4_OFFSET4_4                (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */

+#define ADC_OFR4_OFFSET4_5                (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */

+#define ADC_OFR4_OFFSET4_6                (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */

+#define ADC_OFR4_OFFSET4_7                (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */

+#define ADC_OFR4_OFFSET4_8                (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */

+#define ADC_OFR4_OFFSET4_9                (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */

+#define ADC_OFR4_OFFSET4_10               (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */

+#define ADC_OFR4_OFFSET4_11               (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */

+#define ADC_OFR4_OFFSET4_12               (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */

+#define ADC_OFR4_OFFSET4_13               (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */

+#define ADC_OFR4_OFFSET4_14               (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */

+#define ADC_OFR4_OFFSET4_15               (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */

+#define ADC_OFR4_OFFSET4_16               (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */

+#define ADC_OFR4_OFFSET4_17               (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */

+#define ADC_OFR4_OFFSET4_18               (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */

+#define ADC_OFR4_OFFSET4_19               (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */

+#define ADC_OFR4_OFFSET4_20               (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */

+#define ADC_OFR4_OFFSET4_21               (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */

+#define ADC_OFR4_OFFSET4_22               (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */

+#define ADC_OFR4_OFFSET4_23               (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */

+#define ADC_OFR4_OFFSET4_24               (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */

+#define ADC_OFR4_OFFSET4_25               (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR4_OFFSET4_CH_Pos           (26U)

+#define ADC_OFR4_OFFSET4_CH_Msk           (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR4_OFFSET4_CH               ADC_OFR4_OFFSET4_CH_Msk               /*!< ADC Channel selection for the data offset 4 */

+#define ADC_OFR4_OFFSET4_CH_0             (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR4_OFFSET4_CH_1             (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR4_OFFSET4_CH_2             (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR4_OFFSET4_CH_3             (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR4_OFFSET4_CH_4             (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR4_SSATE_Pos                (31U)

+#define ADC_OFR4_SSATE_Msk                (0x1UL << ADC_OFR4_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR4_SSATE                    ADC_OFR4_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_JDR1 register  ********************/

+#define ADC_JDR1_JDATA_Pos                (0U)

+#define ADC_JDR1_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR1_JDATA                    ADC_JDR1_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR1_JDATA_0                  (0x00000001UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR1_JDATA_1                  (0x00000002UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR1_JDATA_2                  (0x00000004UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR1_JDATA_3                  (0x00000008UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR1_JDATA_4                  (0x00000010UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR1_JDATA_5                  (0x00000020UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR1_JDATA_6                  (0x00000040UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR1_JDATA_7                  (0x00000080UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR1_JDATA_8                  (0x00000100UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR1_JDATA_9                  (0x00000200UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR1_JDATA_10                 (0x00000400UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR1_JDATA_11                 (0x00000800UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR1_JDATA_12                 (0x00001000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR1_JDATA_13                 (0x00002000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR1_JDATA_14                 (0x00004000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR1_JDATA_15                 (0x00008000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR1_JDATA_16                 (0x00010000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR1_JDATA_17                 (0x00020000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR1_JDATA_18                 (0x00040000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR1_JDATA_19                 (0x00080000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR1_JDATA_20                 (0x00100000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR1_JDATA_21                 (0x00200000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR1_JDATA_22                 (0x00400000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR1_JDATA_23                 (0x00800000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR1_JDATA_24                 (0x01000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR1_JDATA_25                 (0x02000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR1_JDATA_26                 (0x04000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR1_JDATA_27                 (0x08000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR1_JDATA_28                 (0x10000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR1_JDATA_29                 (0x20000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR1_JDATA_30                 (0x40000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR1_JDATA_31                 (0x80000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR2 register  ********************/

+#define ADC_JDR2_JDATA_Pos                (0U)

+#define ADC_JDR2_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR2_JDATA                    ADC_JDR2_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR2_JDATA_0                  (0x00000001UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR2_JDATA_1                  (0x00000002UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR2_JDATA_2                  (0x00000004UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR2_JDATA_3                  (0x00000008UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR2_JDATA_4                  (0x00000010UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR2_JDATA_5                  (0x00000020UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR2_JDATA_6                  (0x00000040UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR2_JDATA_7                  (0x00000080UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR2_JDATA_8                  (0x00000100UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR2_JDATA_9                  (0x00000200UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR2_JDATA_10                 (0x00000400UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR2_JDATA_11                 (0x00000800UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR2_JDATA_12                 (0x00001000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR2_JDATA_13                 (0x00002000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR2_JDATA_14                 (0x00004000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR2_JDATA_15                 (0x00008000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR2_JDATA_16                 (0x00010000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR2_JDATA_17                 (0x00020000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR2_JDATA_18                 (0x00040000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR2_JDATA_19                 (0x00080000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR2_JDATA_20                 (0x00100000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR2_JDATA_21                 (0x00200000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR2_JDATA_22                 (0x00400000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR2_JDATA_23                 (0x00800000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR2_JDATA_24                 (0x01000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR2_JDATA_25                 (0x02000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR2_JDATA_26                 (0x04000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR2_JDATA_27                 (0x08000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR2_JDATA_28                 (0x10000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR2_JDATA_29                 (0x20000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR2_JDATA_30                 (0x40000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR2_JDATA_31                 (0x80000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR3 register  ********************/

+#define ADC_JDR3_JDATA_Pos                (0U)

+#define ADC_JDR3_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR3_JDATA                    ADC_JDR3_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR3_JDATA_0                  (0x00000001UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR3_JDATA_1                  (0x00000002UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR3_JDATA_2                  (0x00000004UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR3_JDATA_3                  (0x00000008UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR3_JDATA_4                  (0x00000010UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR3_JDATA_5                  (0x00000020UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR3_JDATA_6                  (0x00000040UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR3_JDATA_7                  (0x00000080UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR3_JDATA_8                  (0x00000100UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR3_JDATA_9                  (0x00000200UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR3_JDATA_10                 (0x00000400UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR3_JDATA_11                 (0x00000800UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR3_JDATA_12                 (0x00001000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR3_JDATA_13                 (0x00002000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR3_JDATA_14                 (0x00004000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR3_JDATA_15                 (0x00008000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR3_JDATA_16                 (0x00010000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR3_JDATA_17                 (0x00020000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR3_JDATA_18                 (0x00040000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR3_JDATA_19                 (0x00080000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR3_JDATA_20                 (0x00100000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR3_JDATA_21                 (0x00200000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR3_JDATA_22                 (0x00400000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR3_JDATA_23                 (0x00800000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR3_JDATA_24                 (0x01000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR3_JDATA_25                 (0x02000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR3_JDATA_26                 (0x04000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR3_JDATA_27                 (0x08000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR3_JDATA_28                 (0x10000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR3_JDATA_29                 (0x20000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR3_JDATA_30                 (0x40000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR3_JDATA_31                 (0x80000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR4 register  ********************/

+#define ADC_JDR4_JDATA_Pos                (0U)

+#define ADC_JDR4_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR4_JDATA                    ADC_JDR4_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR4_JDATA_0                  (0x00000001UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR4_JDATA_1                  (0x00000002UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR4_JDATA_2                  (0x00000004UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR4_JDATA_3                  (0x00000008UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR4_JDATA_4                  (0x00000010UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR4_JDATA_5                  (0x00000020UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR4_JDATA_6                  (0x00000040UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR4_JDATA_7                  (0x00000080UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR4_JDATA_8                  (0x00000100UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR4_JDATA_9                  (0x00000200UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR4_JDATA_10                 (0x00000400UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR4_JDATA_11                 (0x00000800UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR4_JDATA_12                 (0x00001000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR4_JDATA_13                 (0x00002000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR4_JDATA_14                 (0x00004000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR4_JDATA_15                 (0x00008000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR4_JDATA_16                 (0x00010000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR4_JDATA_17                 (0x00020000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR4_JDATA_18                 (0x00040000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR4_JDATA_19                 (0x00080000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR4_JDATA_20                 (0x00100000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR4_JDATA_21                 (0x00200000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR4_JDATA_22                 (0x00400000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR4_JDATA_23                 (0x00800000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR4_JDATA_24                 (0x01000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR4_JDATA_25                 (0x02000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR4_JDATA_26                 (0x04000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR4_JDATA_27                 (0x08000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR4_JDATA_28                 (0x10000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR4_JDATA_29                 (0x20000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR4_JDATA_30                 (0x40000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR4_JDATA_31                 (0x80000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_AWD2CR register  ********************/

+#define ADC_AWD2CR_AWD2CH_Pos             (0U)

+#define ADC_AWD2CR_AWD2CH_Msk             (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x000FFFFF */

+#define ADC_AWD2CR_AWD2CH                 ADC_AWD2CR_AWD2CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */

+#define ADC_AWD2CR_AWD2CH_0               (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000001 */

+#define ADC_AWD2CR_AWD2CH_1               (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000002 */

+#define ADC_AWD2CR_AWD2CH_2               (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000004 */

+#define ADC_AWD2CR_AWD2CH_3               (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000008 */

+#define ADC_AWD2CR_AWD2CH_4               (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000010 */

+#define ADC_AWD2CR_AWD2CH_5               (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000020 */

+#define ADC_AWD2CR_AWD2CH_6               (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000040 */

+#define ADC_AWD2CR_AWD2CH_7               (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000080 */

+#define ADC_AWD2CR_AWD2CH_8               (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000100 */

+#define ADC_AWD2CR_AWD2CH_9               (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000200 */

+#define ADC_AWD2CR_AWD2CH_10              (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000400 */

+#define ADC_AWD2CR_AWD2CH_11              (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000800 */

+#define ADC_AWD2CR_AWD2CH_12              (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00001000 */

+#define ADC_AWD2CR_AWD2CH_13              (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00002000 */

+#define ADC_AWD2CR_AWD2CH_14              (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00004000 */

+#define ADC_AWD2CR_AWD2CH_15              (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00008000 */

+#define ADC_AWD2CR_AWD2CH_16              (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00010000 */

+#define ADC_AWD2CR_AWD2CH_17              (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00020000 */

+#define ADC_AWD2CR_AWD2CH_18              (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */

+#define ADC_AWD2CR_AWD2CH_19              (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_AWD3CR register  ********************/

+#define ADC_AWD3CR_AWD3CH_Pos             (0U)

+#define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x000FFFFF */

+#define ADC_AWD3CR_AWD3CH                 ADC_AWD3CR_AWD3CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */

+#define ADC_AWD3CR_AWD3CH_0               (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000001 */

+#define ADC_AWD3CR_AWD3CH_1               (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000002 */

+#define ADC_AWD3CR_AWD3CH_2               (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000004 */

+#define ADC_AWD3CR_AWD3CH_3               (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000008 */

+#define ADC_AWD3CR_AWD3CH_4               (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000010 */

+#define ADC_AWD3CR_AWD3CH_5               (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000020 */

+#define ADC_AWD3CR_AWD3CH_6               (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000040 */

+#define ADC_AWD3CR_AWD3CH_7               (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000080 */

+#define ADC_AWD3CR_AWD3CH_8               (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000100 */

+#define ADC_AWD3CR_AWD3CH_9               (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000200 */

+#define ADC_AWD3CR_AWD3CH_10              (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000400 */

+#define ADC_AWD3CR_AWD3CH_11              (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000800 */

+#define ADC_AWD3CR_AWD3CH_12              (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00001000 */

+#define ADC_AWD3CR_AWD3CH_13              (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00002000 */

+#define ADC_AWD3CR_AWD3CH_14              (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00004000 */

+#define ADC_AWD3CR_AWD3CH_15              (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00008000 */

+#define ADC_AWD3CR_AWD3CH_16              (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00010000 */

+#define ADC_AWD3CR_AWD3CH_17              (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00020000 */

+#define ADC_AWD3CR_AWD3CH_18              (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */

+#define ADC_AWD3CR_AWD3CH_19              (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_DIFSEL register  ********************/

+#define ADC_DIFSEL_DIFSEL_Pos             (0U)

+#define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */

+#define ADC_DIFSEL_DIFSEL                 ADC_DIFSEL_DIFSEL_Msk                 /*!< ADC differential modes for channels 1 to 18 */

+#define ADC_DIFSEL_DIFSEL_0               (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000001 */

+#define ADC_DIFSEL_DIFSEL_1               (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000002 */

+#define ADC_DIFSEL_DIFSEL_2               (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000004 */

+#define ADC_DIFSEL_DIFSEL_3               (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000008 */

+#define ADC_DIFSEL_DIFSEL_4               (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000010 */

+#define ADC_DIFSEL_DIFSEL_5               (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000020 */

+#define ADC_DIFSEL_DIFSEL_6               (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000040 */

+#define ADC_DIFSEL_DIFSEL_7               (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000080 */

+#define ADC_DIFSEL_DIFSEL_8               (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000100 */

+#define ADC_DIFSEL_DIFSEL_9               (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000200 */

+#define ADC_DIFSEL_DIFSEL_10              (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000400 */

+#define ADC_DIFSEL_DIFSEL_11              (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000800 */

+#define ADC_DIFSEL_DIFSEL_12              (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00001000 */

+#define ADC_DIFSEL_DIFSEL_13              (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00002000 */

+#define ADC_DIFSEL_DIFSEL_14              (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00004000 */

+#define ADC_DIFSEL_DIFSEL_15              (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00008000 */

+#define ADC_DIFSEL_DIFSEL_16              (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00010000 */

+#define ADC_DIFSEL_DIFSEL_17              (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00020000 */

+#define ADC_DIFSEL_DIFSEL_18              (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00040000 */

+#define ADC_DIFSEL_DIFSEL_19              (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_CALFACT register  ********************/

+#define ADC_CALFACT_CALFACT_S_Pos         (0U)

+#define ADC_CALFACT_CALFACT_S_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */

+#define ADC_CALFACT_CALFACT_S             ADC_CALFACT_CALFACT_S_Msk              /*!< ADC calibration factors in single-ended mode */

+#define ADC_CALFACT_CALFACT_S_0           (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */

+#define ADC_CALFACT_CALFACT_S_1           (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */

+#define ADC_CALFACT_CALFACT_S_2           (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */

+#define ADC_CALFACT_CALFACT_S_3           (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */

+#define ADC_CALFACT_CALFACT_S_4           (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */

+#define ADC_CALFACT_CALFACT_S_5           (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */

+#define ADC_CALFACT_CALFACT_S_6           (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */

+#define ADC_CALFACT_CALFACT_S_7           (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */

+#define ADC_CALFACT_CALFACT_S_8           (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */

+#define ADC_CALFACT_CALFACT_S_9           (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */

+#define ADC_CALFACT_CALFACT_S_10          (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */

+#define ADC_CALFACT_CALFACT_D_Pos         (16U)

+#define ADC_CALFACT_CALFACT_D_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */

+#define ADC_CALFACT_CALFACT_D             ADC_CALFACT_CALFACT_D_Msk              /*!< ADC calibration factors in differential mode */

+#define ADC_CALFACT_CALFACT_D_0           (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */

+#define ADC_CALFACT_CALFACT_D_1           (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */

+#define ADC_CALFACT_CALFACT_D_2           (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */

+#define ADC_CALFACT_CALFACT_D_3           (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */

+#define ADC_CALFACT_CALFACT_D_4           (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */

+#define ADC_CALFACT_CALFACT_D_5           (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */

+#define ADC_CALFACT_CALFACT_D_6           (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */

+#define ADC_CALFACT_CALFACT_D_7           (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */

+#define ADC_CALFACT_CALFACT_D_8           (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */

+#define ADC_CALFACT_CALFACT_D_9           (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */

+#define ADC_CALFACT_CALFACT_D_10          (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */

+

+/********************  Bit definition for ADC_CALFACT2 register  ********************/

+#define ADC_CALFACT2_LINCALFACT_Pos       (0U)

+#define ADC_CALFACT2_LINCALFACT_Msk       (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */

+#define ADC_CALFACT2_LINCALFACT           ADC_CALFACT2_LINCALFACT_Msk                   /*!< ADC Linearity calibration factors */

+#define ADC_CALFACT2_LINCALFACT_0         (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */

+#define ADC_CALFACT2_LINCALFACT_1         (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */

+#define ADC_CALFACT2_LINCALFACT_2         (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */

+#define ADC_CALFACT2_LINCALFACT_3         (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */

+#define ADC_CALFACT2_LINCALFACT_4         (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */

+#define ADC_CALFACT2_LINCALFACT_5         (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */

+#define ADC_CALFACT2_LINCALFACT_6         (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */

+#define ADC_CALFACT2_LINCALFACT_7         (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */

+#define ADC_CALFACT2_LINCALFACT_8         (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */

+#define ADC_CALFACT2_LINCALFACT_9         (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */

+#define ADC_CALFACT2_LINCALFACT_10        (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */

+#define ADC_CALFACT2_LINCALFACT_11        (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */

+#define ADC_CALFACT2_LINCALFACT_12        (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */

+#define ADC_CALFACT2_LINCALFACT_13        (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */

+#define ADC_CALFACT2_LINCALFACT_14        (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */

+#define ADC_CALFACT2_LINCALFACT_15        (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */

+#define ADC_CALFACT2_LINCALFACT_16        (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */

+#define ADC_CALFACT2_LINCALFACT_17        (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */

+#define ADC_CALFACT2_LINCALFACT_18        (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */

+#define ADC_CALFACT2_LINCALFACT_19        (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */

+#define ADC_CALFACT2_LINCALFACT_20        (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */

+#define ADC_CALFACT2_LINCALFACT_21        (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */

+#define ADC_CALFACT2_LINCALFACT_22        (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */

+#define ADC_CALFACT2_LINCALFACT_23        (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */

+#define ADC_CALFACT2_LINCALFACT_24        (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */

+#define ADC_CALFACT2_LINCALFACT_25        (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */

+#define ADC_CALFACT2_LINCALFACT_26        (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */

+#define ADC_CALFACT2_LINCALFACT_27        (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */

+#define ADC_CALFACT2_LINCALFACT_28        (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */

+#define ADC_CALFACT2_LINCALFACT_29        (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */

+

+/*************************  ADC Common registers  *****************************/

+/********************  Bit definition for ADC_CSR register  ********************/

+#define ADC_CSR_ADRDY_MST_Pos             (0U)

+#define ADC_CSR_ADRDY_MST_Msk             (0x1UL << ADC_CSR_ADRDY_MST_Pos)     /*!< 0x00000001 */

+#define ADC_CSR_ADRDY_MST                 ADC_CSR_ADRDY_MST_Msk                /*!< Master ADC ready */

+#define ADC_CSR_EOSMP_MST_Pos             (1U)

+#define ADC_CSR_EOSMP_MST_Msk             (0x1UL << ADC_CSR_EOSMP_MST_Pos)     /*!< 0x00000002 */

+#define ADC_CSR_EOSMP_MST                 ADC_CSR_EOSMP_MST_Msk                /*!< End of sampling phase flag of the master ADC */

+#define ADC_CSR_EOC_MST_Pos               (2U)

+#define ADC_CSR_EOC_MST_Msk               (0x1UL << ADC_CSR_EOC_MST_Pos)       /*!< 0x00000004 */

+#define ADC_CSR_EOC_MST                   ADC_CSR_EOC_MST_Msk                  /*!< End of regular conversion of the master ADC */

+#define ADC_CSR_EOS_MST_Pos               (3U)

+#define ADC_CSR_EOS_MST_Msk               (0x1UL << ADC_CSR_EOS_MST_Pos)       /*!< 0x00000008 */

+#define ADC_CSR_EOS_MST                   ADC_CSR_EOS_MST_Msk                  /*!< End of regular sequence flag of the master ADC */

+#define ADC_CSR_OVR_MST_Pos               (4U)

+#define ADC_CSR_OVR_MST_Msk               (0x1UL << ADC_CSR_OVR_MST_Pos)       /*!< 0x00000010 */

+#define ADC_CSR_OVR_MST                   ADC_CSR_OVR_MST_Msk                  /*!< Overrun flag of the master ADC */

+#define ADC_CSR_JEOC_MST_Pos              (5U)

+#define ADC_CSR_JEOC_MST_Msk              (0x1UL << ADC_CSR_JEOC_MST_Pos)      /*!< 0x00000020 */

+#define ADC_CSR_JEOC_MST                  ADC_CSR_JEOC_MST_Msk                 /*!< End of injected conversion of the master ADC */

+#define ADC_CSR_JEOS_MST_Pos              (6U)

+#define ADC_CSR_JEOS_MST_Msk              (0x1UL << ADC_CSR_JEOS_MST_Pos)      /*!< 0x00000040 */

+#define ADC_CSR_JEOS_MST                  ADC_CSR_JEOS_MST_Msk                 /*!< End of injected sequence flag of the master ADC */

+#define ADC_CSR_AWD1_MST_Pos              (7U)

+#define ADC_CSR_AWD1_MST_Msk              (0x1UL << ADC_CSR_AWD1_MST_Pos)      /*!< 0x00000080 */

+#define ADC_CSR_AWD1_MST                  ADC_CSR_AWD1_MST_Msk                 /*!< Analog watchdog 1 flag of the master ADC */

+#define ADC_CSR_AWD2_MST_Pos              (8U)

+#define ADC_CSR_AWD2_MST_Msk              (0x1UL << ADC_CSR_AWD2_MST_Pos)      /*!< 0x00000100 */

+#define ADC_CSR_AWD2_MST                  ADC_CSR_AWD2_MST_Msk                 /*!< Analog watchdog 2 flag of the master ADC */

+#define ADC_CSR_AWD3_MST_Pos              (9U)

+#define ADC_CSR_AWD3_MST_Msk              (0x1UL << ADC_CSR_AWD3_MST_Pos)      /*!< 0x00000200 */

+#define ADC_CSR_AWD3_MST                  ADC_CSR_AWD3_MST_Msk                 /*!< Analog watchdog 3 flag of the master ADC */

+#define ADC_CSR_JQOVF_MST_Pos             (10U)

+#define ADC_CSR_JQOVF_MST_Msk             (0x1UL << ADC_CSR_JQOVF_MST_Pos)     /*!< 0x00000400 */

+#define ADC_CSR_JQOVF_MST                 ADC_CSR_JQOVF_MST_Msk                /*!< Injected context queue overflow flag of the master ADC */

+#define ADC_CSR_ADRDY_SLV_Pos             (16U)

+#define ADC_CSR_ADRDY_SLV_Msk             (0x1UL << ADC_CSR_ADRDY_SLV_Pos)     /*!< 0x00010000 */

+#define ADC_CSR_ADRDY_SLV                 ADC_CSR_ADRDY_SLV_Msk                /*!< Slave ADC ready */

+#define ADC_CSR_EOSMP_SLV_Pos             (17U)

+#define ADC_CSR_EOSMP_SLV_Msk             (0x1UL << ADC_CSR_EOSMP_SLV_Pos)     /*!< 0x00020000 */

+#define ADC_CSR_EOSMP_SLV                 ADC_CSR_EOSMP_SLV_Msk                /*!< End of sampling phase flag of the slave ADC */

+#define ADC_CSR_EOC_SLV_Pos               (18U)

+#define ADC_CSR_EOC_SLV_Msk               (0x1UL << ADC_CSR_EOC_SLV_Pos)       /*!< 0x00040000 */

+#define ADC_CSR_EOC_SLV                   ADC_CSR_EOC_SLV_Msk                  /*!< End of regular conversion of the slave ADC */

+#define ADC_CSR_EOS_SLV_Pos               (19U)

+#define ADC_CSR_EOS_SLV_Msk               (0x1UL << ADC_CSR_EOS_SLV_Pos)       /*!< 0x00080000 */

+#define ADC_CSR_EOS_SLV                   ADC_CSR_EOS_SLV_Msk                  /*!< End of regular sequence flag of the slave ADC */

+#define ADC_CSR_OVR_SLV_Pos               (20U)

+#define ADC_CSR_OVR_SLV_Msk               (0x1UL << ADC_CSR_OVR_SLV_Pos)       /*!< 0x00100000 */

+#define ADC_CSR_OVR_SLV                   ADC_CSR_OVR_SLV_Msk                  /*!< Overrun flag of the slave ADC */

+#define ADC_CSR_JEOC_SLV_Pos              (21U)

+#define ADC_CSR_JEOC_SLV_Msk              (0x1UL << ADC_CSR_JEOC_SLV_Pos)      /*!< 0x00200000 */

+#define ADC_CSR_JEOC_SLV                  ADC_CSR_JEOC_SLV_Msk                 /*!< End of injected conversion of the slave ADC */

+#define ADC_CSR_JEOS_SLV_Pos              (22U)

+#define ADC_CSR_JEOS_SLV_Msk              (0x1UL << ADC_CSR_JEOS_SLV_Pos)      /*!< 0x00400000 */

+#define ADC_CSR_JEOS_SLV                  ADC_CSR_JEOS_SLV_Msk                 /*!< End of injected sequence flag of the slave ADC */

+#define ADC_CSR_AWD1_SLV_Pos              (23U)

+#define ADC_CSR_AWD1_SLV_Msk              (0x1UL << ADC_CSR_AWD1_SLV_Pos)      /*!< 0x00800000 */

+#define ADC_CSR_AWD1_SLV                  ADC_CSR_AWD1_SLV_Msk                 /*!< Analog watchdog 1 flag of the slave ADC */

+#define ADC_CSR_AWD2_SLV_Pos              (24U)

+#define ADC_CSR_AWD2_SLV_Msk              (0x1UL << ADC_CSR_AWD2_SLV_Pos)      /*!< 0x01000000 */

+#define ADC_CSR_AWD2_SLV                  ADC_CSR_AWD2_SLV_Msk                 /*!< Analog watchdog 2 flag of the slave ADC */

+#define ADC_CSR_AWD3_SLV_Pos              (25U)

+#define ADC_CSR_AWD3_SLV_Msk              (0x1UL << ADC_CSR_AWD3_SLV_Pos)      /*!< 0x02000000 */

+#define ADC_CSR_AWD3_SLV                  ADC_CSR_AWD3_SLV_Msk                 /*!< Analog watchdog 3 flag of the slave ADC */

+#define ADC_CSR_JQOVF_SLV_Pos             (26U)

+#define ADC_CSR_JQOVF_SLV_Msk             (0x1UL << ADC_CSR_JQOVF_SLV_Pos)     /*!< 0x04000000 */

+#define ADC_CSR_JQOVF_SLV                 ADC_CSR_JQOVF_SLV_Msk                /*!< Injected context queue overflow flag of the slave ADC */

+

+/********************  Bit definition for ADC_CCR register  ********************/

+#define ADC_CCR_DUAL_Pos                  (0U)

+#define ADC_CCR_DUAL_Msk                  (0x1FUL << ADC_CCR_DUAL_Pos)          /*!< 0x0000001F */

+#define ADC_CCR_DUAL                      ADC_CCR_DUAL_Msk                      /*!< Dual ADC mode selection */

+#define ADC_CCR_DUAL_0                    (0x01UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000001 */

+#define ADC_CCR_DUAL_1                    (0x02UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000002 */

+#define ADC_CCR_DUAL_2                    (0x04UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000004 */

+#define ADC_CCR_DUAL_3                    (0x08UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000008 */

+#define ADC_CCR_DUAL_4                    (0x10UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000010 */

+

+#define ADC_CCR_DELAY_Pos                 (8U)

+#define ADC_CCR_DELAY_Msk                 (0xFUL << ADC_CCR_DELAY_Pos)          /*!< 0x00000F00 */

+#define ADC_CCR_DELAY                     ADC_CCR_DELAY_Msk                     /*!< Delay between 2 sampling phases */

+#define ADC_CCR_DELAY_0                   (0x1UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000100 */

+#define ADC_CCR_DELAY_1                   (0x2UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000200 */

+#define ADC_CCR_DELAY_2                   (0x4UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000400 */

+#define ADC_CCR_DELAY_3                   (0x8UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000800 */

+

+

+#define ADC_CCR_DAMDF_Pos                 (14U)

+#define ADC_CCR_DAMDF_Msk                 (0x3UL << ADC_CCR_DAMDF_Pos)          /*!< 0x0000C000 */

+#define ADC_CCR_DAMDF                     ADC_CCR_DAMDF_Msk                     /*!< Dual ADC mode Data format */

+#define ADC_CCR_DAMDF_0                   (0x1UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00004000 */

+#define ADC_CCR_DAMDF_1                   (0x2UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00008000 */

+

+#define ADC_CCR_CKMODE_Pos                (16U)

+#define ADC_CCR_CKMODE_Msk                (0x3UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00030000 */

+#define ADC_CCR_CKMODE                    ADC_CCR_CKMODE_Msk                    /*!< ADC clock mode */

+#define ADC_CCR_CKMODE_0                  (0x1UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00010000 */

+#define ADC_CCR_CKMODE_1                  (0x2UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00020000 */

+

+#define ADC_CCR_PRESC_Pos                 (18U)

+#define ADC_CCR_PRESC_Msk                 (0xFUL << ADC_CCR_PRESC_Pos)          /*!< 0x003C0000 */

+#define ADC_CCR_PRESC                     ADC_CCR_PRESC_Msk                     /*!< ADC prescaler */

+#define ADC_CCR_PRESC_0                   (0x1UL << ADC_CCR_PRESC_Pos)          /*!< 0x00040000 */

+#define ADC_CCR_PRESC_1                   (0x2UL << ADC_CCR_PRESC_Pos)          /*!< 0x00080000 */

+#define ADC_CCR_PRESC_2                   (0x4UL << ADC_CCR_PRESC_Pos)          /*!< 0x00100000 */

+#define ADC_CCR_PRESC_3                   (0x8UL << ADC_CCR_PRESC_Pos)          /*!< 0x00200000 */

+

+#define ADC_CCR_VREFEN_Pos                (22U)

+#define ADC_CCR_VREFEN_Msk                (0x1UL << ADC_CCR_VREFEN_Pos)         /*!< 0x00400000 */

+#define ADC_CCR_VREFEN                    ADC_CCR_VREFEN_Msk                    /*!< VREFINT enable */

+#define ADC_CCR_TSEN_Pos                  (23U)

+#define ADC_CCR_TSEN_Msk                  (0x1UL << ADC_CCR_TSEN_Pos)           /*!< 0x00800000 */

+#define ADC_CCR_TSEN                      ADC_CCR_TSEN_Msk                      /*!< Temperature sensor enable */

+#define ADC_CCR_VBATEN_Pos                (24U)

+#define ADC_CCR_VBATEN_Msk                (0x1UL << ADC_CCR_VBATEN_Pos)         /*!< 0x01000000 */

+#define ADC_CCR_VBATEN                    ADC_CCR_VBATEN_Msk                    /*!< VBAT enable */

+

+/********************  Bit definition for ADC_CDR register  *******************/

+#define ADC_CDR_RDATA_MST_Pos             (0U)

+#define ADC_CDR_RDATA_MST_Msk             (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)   /*!< 0x0000FFFF */

+#define ADC_CDR_RDATA_MST                 ADC_CDR_RDATA_MST_Msk                 /*!< ADC multimode master group regular conversion data */

+

+#define ADC_CDR_RDATA_SLV_Pos             (16U)

+#define ADC_CDR_RDATA_SLV_Msk             (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)   /*!< 0xFFFF0000 */

+#define ADC_CDR_RDATA_SLV                 ADC_CDR_RDATA_SLV_Msk                 /*!< ADC multimode slave group regular conversion data */

+

+/********************  Bit definition for ADC_CDR2 register  ******************/

+#define ADC_CDR2_RDATA_ALT_Pos            (0U)

+#define ADC_CDR2_RDATA_ALT_Msk            (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */

+#define ADC_CDR2_RDATA_ALT                ADC_CDR2_RDATA_ALT_Msk                   /*!< Regular data of the master/slave alternated ADCs */

+

+/******************************************************************************/

+/*                                                                            */

+/*                        ART accelerator                                     */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for ART_CTR register  ********************/

+#define ART_CTR_EN_Pos              (0U)

+#define ART_CTR_EN_Msk              (0x1UL << ART_CTR_EN_Pos)                /*!< 0x00000001 */

+#define ART_CTR_EN                  ART_CTR_EN_Msk                           /*!< Cache enable*/

+

+#define ART_CTR_PCACHEADDR_Pos      (8U)

+#define ART_CTR_PCACHEADDR_Msk      (0xFFFUL << ART_CTR_PCACHEADDR_Pos)      /*!< 0x000FFF00 */

+#define ART_CTR_PCACHEADDR          ART_CTR_PCACHEADDR_Msk                   /*!< Cacheable page index */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                   VREFBUF                                  */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for VREFBUF_CSR register  ****************/

+#define VREFBUF_CSR_ENVR_Pos        (0U)

+#define VREFBUF_CSR_ENVR_Msk        (0x1UL << VREFBUF_CSR_ENVR_Pos)            /*!< 0x00000001 */

+#define VREFBUF_CSR_ENVR            VREFBUF_CSR_ENVR_Msk                       /*!<Voltage reference buffer enable */

+#define VREFBUF_CSR_HIZ_Pos         (1U)

+#define VREFBUF_CSR_HIZ_Msk         (0x1UL << VREFBUF_CSR_HIZ_Pos)             /*!< 0x00000002 */

+#define VREFBUF_CSR_HIZ             VREFBUF_CSR_HIZ_Msk                        /*!<High impedance mode             */

+#define VREFBUF_CSR_VRR_Pos         (3U)

+#define VREFBUF_CSR_VRR_Msk         (0x1UL << VREFBUF_CSR_VRR_Pos)             /*!< 0x00000008 */

+#define VREFBUF_CSR_VRR             VREFBUF_CSR_VRR_Msk                        /*!<Voltage reference buffer ready  */

+#define VREFBUF_CSR_VRS_Pos         (4U)

+#define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */

+#define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */

+

+#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */

+#define VREFBUF_CSR_VRS_OUT2_Pos    (4U)

+#define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */

+#define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */

+#define VREFBUF_CSR_VRS_OUT3_Pos    (5U)

+#define VREFBUF_CSR_VRS_OUT3_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)        /*!< 0x00000020 */

+#define VREFBUF_CSR_VRS_OUT3        VREFBUF_CSR_VRS_OUT3_Msk                   /*!<Voltage reference VREF_OUT3     */

+#define VREFBUF_CSR_VRS_OUT4_Pos    (4U)

+#define VREFBUF_CSR_VRS_OUT4_Msk    (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)        /*!< 0x00000030 */

+#define VREFBUF_CSR_VRS_OUT4        VREFBUF_CSR_VRS_OUT4_Msk                   /*!<Voltage reference VREF_OUT4     */

+

+/*******************  Bit definition for VREFBUF_CCR register  ****************/

+#define VREFBUF_CCR_TRIM_Pos        (0U)

+#define VREFBUF_CCR_TRIM_Msk        (0x3FUL << VREFBUF_CCR_TRIM_Pos)           /*!< 0x0000003F */

+#define VREFBUF_CCR_TRIM            VREFBUF_CCR_TRIM_Msk                       /*!<TRIM[5:0] bits (Trimming code)  */

+

+/******************************************************************************/

+/*                                                                            */

+/*                 Flexible Datarate Controller Area Network                  */

+/*                                                                            */

+/******************************************************************************/

+/*!<FDCAN control and status registers */

+/*****************  Bit definition for FDCAN_CREL register  *******************/

+#define FDCAN_CREL_DAY_Pos        (0U)

+#define FDCAN_CREL_DAY_Msk        (0xFFUL << FDCAN_CREL_DAY_Pos)               /*!< 0x000000FF */

+#define FDCAN_CREL_DAY            FDCAN_CREL_DAY_Msk                           /*!<Timestamp Day                           */

+#define FDCAN_CREL_MON_Pos        (8U)

+#define FDCAN_CREL_MON_Msk        (0xFFUL << FDCAN_CREL_MON_Pos)               /*!< 0x0000FF00 */

+#define FDCAN_CREL_MON            FDCAN_CREL_MON_Msk                           /*!<Timestamp Month                         */

+#define FDCAN_CREL_YEAR_Pos       (16U)

+#define FDCAN_CREL_YEAR_Msk       (0xFUL << FDCAN_CREL_YEAR_Pos)               /*!< 0x000F0000 */

+#define FDCAN_CREL_YEAR           FDCAN_CREL_YEAR_Msk                          /*!<Timestamp Year                          */

+#define FDCAN_CREL_SUBSTEP_Pos    (20U)

+#define FDCAN_CREL_SUBSTEP_Msk    (0xFUL << FDCAN_CREL_SUBSTEP_Pos)            /*!< 0x00F00000 */

+#define FDCAN_CREL_SUBSTEP        FDCAN_CREL_SUBSTEP_Msk                       /*!<Sub-step of Core release                */

+#define FDCAN_CREL_STEP_Pos       (24U)

+#define FDCAN_CREL_STEP_Msk       (0xFUL << FDCAN_CREL_STEP_Pos)               /*!< 0x0F000000 */

+#define FDCAN_CREL_STEP           FDCAN_CREL_STEP_Msk                          /*!<Step of Core release                    */

+#define FDCAN_CREL_REL_Pos        (28U)

+#define FDCAN_CREL_REL_Msk        (0xFUL << FDCAN_CREL_REL_Pos)                /*!< 0xF0000000 */

+#define FDCAN_CREL_REL            FDCAN_CREL_REL_Msk                           /*!<Core release                            */

+

+/*****************  Bit definition for FDCAN_ENDN register  *******************/

+#define FDCAN_ENDN_ETV_Pos        (0U)

+#define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endiannes Test Value                    */

+

+/*****************  Bit definition for FDCAN_DBTP register  *******************/

+#define FDCAN_DBTP_DSJW_Pos       (0U)

+#define FDCAN_DBTP_DSJW_Msk       (0xFUL << FDCAN_DBTP_DSJW_Pos)               /*!< 0x0000000F */

+#define FDCAN_DBTP_DSJW           FDCAN_DBTP_DSJW_Msk                          /*!<Synchronization Jump Width              */

+#define FDCAN_DBTP_DTSEG2_Pos     (4U)

+#define FDCAN_DBTP_DTSEG2_Msk     (0xFUL << FDCAN_DBTP_DTSEG2_Pos)             /*!< 0x000000F0 */

+#define FDCAN_DBTP_DTSEG2         FDCAN_DBTP_DTSEG2_Msk                        /*!<Data time segment after sample point    */

+#define FDCAN_DBTP_DTSEG1_Pos     (8U)

+#define FDCAN_DBTP_DTSEG1_Msk     (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)            /*!< 0x00001F00 */

+#define FDCAN_DBTP_DTSEG1         FDCAN_DBTP_DTSEG1_Msk                        /*!<Data time segment before sample point   */

+#define FDCAN_DBTP_DBRP_Pos       (16U)

+#define FDCAN_DBTP_DBRP_Msk       (0x1FUL << FDCAN_DBTP_DBRP_Pos)              /*!< 0x001F0000 */

+#define FDCAN_DBTP_DBRP           FDCAN_DBTP_DBRP_Msk                          /*!<Data BIt Rate Prescaler                 */

+#define FDCAN_DBTP_TDC_Pos        (23U)

+#define FDCAN_DBTP_TDC_Msk        (0x1UL << FDCAN_DBTP_TDC_Pos)                /*!< 0x00800000 */

+#define FDCAN_DBTP_TDC            FDCAN_DBTP_TDC_Msk                           /*!<Transceiver Delay Compensation          */

+

+/*****************  Bit definition for FDCAN_TEST register  *******************/

+#define FDCAN_TEST_LBCK_Pos       (4U)

+#define FDCAN_TEST_LBCK_Msk       (0x1UL << FDCAN_TEST_LBCK_Pos)               /*!< 0x00000010 */

+#define FDCAN_TEST_LBCK           FDCAN_TEST_LBCK_Msk                          /*!<Loop Back mode                           */

+#define FDCAN_TEST_TX_Pos         (5U)

+#define FDCAN_TEST_TX_Msk         (0x3UL << FDCAN_TEST_TX_Pos)                 /*!< 0x00000060 */

+#define FDCAN_TEST_TX             FDCAN_TEST_TX_Msk                            /*!<Control of Transmit Pin                  */

+#define FDCAN_TEST_RX_Pos         (7U)

+#define FDCAN_TEST_RX_Msk         (0x1UL << FDCAN_TEST_RX_Pos)                 /*!< 0x00000080 */

+#define FDCAN_TEST_RX             FDCAN_TEST_RX_Msk                            /*!<Receive Pin                              */

+

+/*****************  Bit definition for FDCAN_RWD register  ********************/

+#define FDCAN_RWD_WDC_Pos         (0U)

+#define FDCAN_RWD_WDC_Msk         (0xFFUL << FDCAN_RWD_WDC_Pos)                /*!< 0x000000FF */

+#define FDCAN_RWD_WDC             FDCAN_RWD_WDC_Msk                            /*!<Watchdog configuration                   */

+#define FDCAN_RWD_WDV_Pos         (8U)

+#define FDCAN_RWD_WDV_Msk         (0xFFUL << FDCAN_RWD_WDV_Pos)                /*!< 0x0000FF00 */

+#define FDCAN_RWD_WDV             FDCAN_RWD_WDV_Msk                            /*!<Watchdog value                           */

+

+/*****************  Bit definition for FDCAN_CCCR register  ********************/

+#define FDCAN_CCCR_INIT_Pos       (0U)

+#define FDCAN_CCCR_INIT_Msk       (0x1UL << FDCAN_CCCR_INIT_Pos)               /*!< 0x00000001 */

+#define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!<Initialization                           */

+#define FDCAN_CCCR_CCE_Pos        (1U)

+#define FDCAN_CCCR_CCE_Msk        (0x1UL << FDCAN_CCCR_CCE_Pos)                /*!< 0x00000002 */

+#define FDCAN_CCCR_CCE            FDCAN_CCCR_CCE_Msk                           /*!<Configuration Change Enable              */

+#define FDCAN_CCCR_ASM_Pos        (2U)

+#define FDCAN_CCCR_ASM_Msk        (0x1UL << FDCAN_CCCR_ASM_Pos)                /*!< 0x00000004 */

+#define FDCAN_CCCR_ASM            FDCAN_CCCR_ASM_Msk                           /*!<ASM Restricted Operation Mode            */

+#define FDCAN_CCCR_CSA_Pos        (3U)

+#define FDCAN_CCCR_CSA_Msk        (0x1UL << FDCAN_CCCR_CSA_Pos)                /*!< 0x00000008 */

+#define FDCAN_CCCR_CSA            FDCAN_CCCR_CSA_Msk                           /*!<Clock Stop Acknowledge                   */

+#define FDCAN_CCCR_CSR_Pos        (4U)

+#define FDCAN_CCCR_CSR_Msk        (0x1UL << FDCAN_CCCR_CSR_Pos)                /*!< 0x00000010 */

+#define FDCAN_CCCR_CSR            FDCAN_CCCR_CSR_Msk                           /*!<Clock Stop Request                       */

+#define FDCAN_CCCR_MON_Pos        (5U)

+#define FDCAN_CCCR_MON_Msk        (0x1UL << FDCAN_CCCR_MON_Pos)                /*!< 0x00000020 */

+#define FDCAN_CCCR_MON            FDCAN_CCCR_MON_Msk                           /*!<Bus Monitoring Mode                      */

+#define FDCAN_CCCR_DAR_Pos        (6U)

+#define FDCAN_CCCR_DAR_Msk        (0x1UL << FDCAN_CCCR_DAR_Pos)                /*!< 0x00000040 */

+#define FDCAN_CCCR_DAR            FDCAN_CCCR_DAR_Msk                           /*!<Disable Automatic Retransmission         */

+#define FDCAN_CCCR_TEST_Pos       (7U)

+#define FDCAN_CCCR_TEST_Msk       (0x1UL << FDCAN_CCCR_TEST_Pos)               /*!< 0x00000080 */

+#define FDCAN_CCCR_TEST           FDCAN_CCCR_TEST_Msk                          /*!<Test Mode Enable                         */

+#define FDCAN_CCCR_FDOE_Pos       (8U)

+#define FDCAN_CCCR_FDOE_Msk       (0x1UL << FDCAN_CCCR_FDOE_Pos)               /*!< 0x00000100 */

+#define FDCAN_CCCR_FDOE           FDCAN_CCCR_FDOE_Msk                          /*!<FD Operation Enable                      */

+#define FDCAN_CCCR_BRSE_Pos       (9U)

+#define FDCAN_CCCR_BRSE_Msk       (0x1UL << FDCAN_CCCR_BRSE_Pos)               /*!< 0x00000200 */

+#define FDCAN_CCCR_BRSE           FDCAN_CCCR_BRSE_Msk                          /*!<FDCAN Bit Rate Switching                 */

+#define FDCAN_CCCR_PXHD_Pos       (12U)

+#define FDCAN_CCCR_PXHD_Msk       (0x1UL << FDCAN_CCCR_PXHD_Pos)               /*!< 0x00001000 */

+#define FDCAN_CCCR_PXHD           FDCAN_CCCR_PXHD_Msk                          /*!<Protocol Exception Handling Disable      */

+#define FDCAN_CCCR_EFBI_Pos       (13U)

+#define FDCAN_CCCR_EFBI_Msk       (0x1UL << FDCAN_CCCR_EFBI_Pos)               /*!< 0x00002000 */

+#define FDCAN_CCCR_EFBI           FDCAN_CCCR_EFBI_Msk                          /*!<Edge Filtering during Bus Integration    */

+#define FDCAN_CCCR_TXP_Pos        (14U)

+#define FDCAN_CCCR_TXP_Msk        (0x1UL << FDCAN_CCCR_TXP_Pos)                /*!< 0x00004000 */

+#define FDCAN_CCCR_TXP            FDCAN_CCCR_TXP_Msk                           /*!<Two CAN bit times Pause                  */

+#define FDCAN_CCCR_NISO_Pos       (15U)

+#define FDCAN_CCCR_NISO_Msk       (0x1UL << FDCAN_CCCR_NISO_Pos)               /*!< 0x00008000 */

+#define FDCAN_CCCR_NISO           FDCAN_CCCR_NISO_Msk                          /*!<Non ISO Operation                        */

+

+/*****************  Bit definition for FDCAN_NBTP register  ********************/

+#define FDCAN_NBTP_NTSEG2_Pos     (0U)

+#define FDCAN_NBTP_NTSEG2_Msk     (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)            /*!< 0x0000007F */

+#define FDCAN_NBTP_NTSEG2         FDCAN_NBTP_NTSEG2_Msk                        /*!<Nominal Time segment after sample point  */

+#define FDCAN_NBTP_NTSEG1_Pos     (8U)

+#define FDCAN_NBTP_NTSEG1_Msk     (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)            /*!< 0x0000FF00 */

+#define FDCAN_NBTP_NTSEG1         FDCAN_NBTP_NTSEG1_Msk                        /*!<Nominal Time segment before sample point */

+#define FDCAN_NBTP_NBRP_Pos       (16U)

+#define FDCAN_NBTP_NBRP_Msk       (0x1FFUL << FDCAN_NBTP_NBRP_Pos)             /*!< 0x01FF0000 */

+#define FDCAN_NBTP_NBRP           FDCAN_NBTP_NBRP_Msk                          /*!<Bit Rate Prescaler                       */

+#define FDCAN_NBTP_NSJW_Pos       (25U)

+#define FDCAN_NBTP_NSJW_Msk       (0x7FUL << FDCAN_NBTP_NSJW_Pos)              /*!< 0xFE000000 */

+#define FDCAN_NBTP_NSJW           FDCAN_NBTP_NSJW_Msk                          /*!<Nominal (Re)Synchronization Jump Width   */

+

+/*****************  Bit definition for FDCAN_TSCC register  ********************/

+#define FDCAN_TSCC_TSS_Pos        (0U)

+#define FDCAN_TSCC_TSS_Msk        (0x3UL << FDCAN_TSCC_TSS_Pos)                /*!< 0x00000003 */

+#define FDCAN_TSCC_TSS            FDCAN_TSCC_TSS_Msk                           /*!<Timestamp Select                         */

+#define FDCAN_TSCC_TCP_Pos        (16U)

+#define FDCAN_TSCC_TCP_Msk        (0xFUL << FDCAN_TSCC_TCP_Pos)                /*!< 0x000F0000 */

+#define FDCAN_TSCC_TCP            FDCAN_TSCC_TCP_Msk                           /*!<Timestamp Counter Prescaler              */

+

+/*****************  Bit definition for FDCAN_TSCV register  ********************/

+#define FDCAN_TSCV_TSC_Pos        (0U)

+#define FDCAN_TSCV_TSC_Msk        (0xFFFFUL << FDCAN_TSCV_TSC_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TSCV_TSC            FDCAN_TSCV_TSC_Msk                           /*!<Timestamp Counter                        */

+

+/*****************  Bit definition for FDCAN_TOCC register  ********************/

+#define FDCAN_TOCC_ETOC_Pos       (0U)

+#define FDCAN_TOCC_ETOC_Msk       (0x1UL << FDCAN_TOCC_ETOC_Pos)               /*!< 0x00000001 */

+#define FDCAN_TOCC_ETOC           FDCAN_TOCC_ETOC_Msk                          /*!<Enable Timeout Counter                   */

+#define FDCAN_TOCC_TOS_Pos        (1U)

+#define FDCAN_TOCC_TOS_Msk        (0x3UL << FDCAN_TOCC_TOS_Pos)                /*!< 0x00000006 */

+#define FDCAN_TOCC_TOS            FDCAN_TOCC_TOS_Msk                           /*!<Timeout Select                           */

+#define FDCAN_TOCC_TOP_Pos        (16U)

+#define FDCAN_TOCC_TOP_Msk        (0xFFFFUL << FDCAN_TOCC_TOP_Pos)             /*!< 0xFFFF0000 */

+#define FDCAN_TOCC_TOP            FDCAN_TOCC_TOP_Msk                           /*!<Timeout Period                           */

+

+/*****************  Bit definition for FDCAN_TOCV register  ********************/

+#define FDCAN_TOCV_TOC_Pos        (0U)

+#define FDCAN_TOCV_TOC_Msk        (0xFFFFUL << FDCAN_TOCV_TOC_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TOCV_TOC            FDCAN_TOCV_TOC_Msk                           /*!<Timeout Counter                          */

+

+/*****************  Bit definition for FDCAN_ECR register  *********************/

+#define FDCAN_ECR_TEC_Pos         (0U)

+#define FDCAN_ECR_TEC_Msk         (0xFUL << FDCAN_ECR_TEC_Pos)                 /*!< 0x0000000F */

+#define FDCAN_ECR_TEC             FDCAN_ECR_TEC_Msk                            /*!<Transmit Error Counter                   */

+#define FDCAN_ECR_REC_Pos         (8U)

+#define FDCAN_ECR_REC_Msk         (0x7FUL << FDCAN_ECR_REC_Pos)                /*!< 0x00007F00 */

+#define FDCAN_ECR_REC             FDCAN_ECR_REC_Msk                            /*!<Receive Error Counter                    */

+#define FDCAN_ECR_RP_Pos          (15U)

+#define FDCAN_ECR_RP_Msk          (0x1UL << FDCAN_ECR_RP_Pos)                  /*!< 0x00008000 */

+#define FDCAN_ECR_RP              FDCAN_ECR_RP_Msk                             /*!<Receive Error Passive                    */

+#define FDCAN_ECR_CEL_Pos         (16U)

+#define FDCAN_ECR_CEL_Msk         (0xFFUL << FDCAN_ECR_CEL_Pos)                /*!< 0x00FF0000 */

+#define FDCAN_ECR_CEL             FDCAN_ECR_CEL_Msk                            /*!<CAN Error Logging                        */

+

+/*****************  Bit definition for FDCAN_PSR register  *********************/

+#define FDCAN_PSR_LEC_Pos         (0U)

+#define FDCAN_PSR_LEC_Msk         (0x7UL << FDCAN_PSR_LEC_Pos)                 /*!< 0x00000007 */

+#define FDCAN_PSR_LEC             FDCAN_PSR_LEC_Msk                            /*!<Last Error Code                          */

+#define FDCAN_PSR_ACT_Pos         (3U)

+#define FDCAN_PSR_ACT_Msk         (0x3UL << FDCAN_PSR_ACT_Pos)                 /*!< 0x00000018 */

+#define FDCAN_PSR_ACT             FDCAN_PSR_ACT_Msk                            /*!<Activity                                 */

+#define FDCAN_PSR_EP_Pos          (5U)

+#define FDCAN_PSR_EP_Msk          (0x1UL << FDCAN_PSR_EP_Pos)                  /*!< 0x00000020 */

+#define FDCAN_PSR_EP              FDCAN_PSR_EP_Msk                             /*!<Error Passive                            */

+#define FDCAN_PSR_EW_Pos          (6U)

+#define FDCAN_PSR_EW_Msk          (0x1UL << FDCAN_PSR_EW_Pos)                  /*!< 0x00000040 */

+#define FDCAN_PSR_EW              FDCAN_PSR_EW_Msk                             /*!<Warning Status                           */

+#define FDCAN_PSR_BO_Pos          (7U)

+#define FDCAN_PSR_BO_Msk          (0x1UL << FDCAN_PSR_BO_Pos)                  /*!< 0x00000080 */

+#define FDCAN_PSR_BO              FDCAN_PSR_BO_Msk                             /*!<Bus_Off Status                           */

+#define FDCAN_PSR_DLEC_Pos        (8U)

+#define FDCAN_PSR_DLEC_Msk        (0x7UL << FDCAN_PSR_DLEC_Pos)                /*!< 0x00000700 */

+#define FDCAN_PSR_DLEC            FDCAN_PSR_DLEC_Msk                           /*!<Data Last Error Code                     */

+#define FDCAN_PSR_RESI_Pos        (11U)

+#define FDCAN_PSR_RESI_Msk        (0x1UL << FDCAN_PSR_RESI_Pos)                /*!< 0x00000800 */

+#define FDCAN_PSR_RESI            FDCAN_PSR_RESI_Msk                           /*!<ESI flag of last received FDCAN Message  */

+#define FDCAN_PSR_RBRS_Pos        (12U)

+#define FDCAN_PSR_RBRS_Msk        (0x1UL << FDCAN_PSR_RBRS_Pos)                /*!< 0x00001000 */

+#define FDCAN_PSR_RBRS            FDCAN_PSR_RBRS_Msk                           /*!<BRS flag of last received FDCAN Message  */

+#define FDCAN_PSR_REDL_Pos        (13U)

+#define FDCAN_PSR_REDL_Msk        (0x1UL << FDCAN_PSR_REDL_Pos)                /*!< 0x00002000 */

+#define FDCAN_PSR_REDL            FDCAN_PSR_REDL_Msk                           /*!<Received FDCAN Message                   */

+#define FDCAN_PSR_PXE_Pos         (14U)

+#define FDCAN_PSR_PXE_Msk         (0x1UL << FDCAN_PSR_PXE_Pos)                 /*!< 0x00004000 */

+#define FDCAN_PSR_PXE             FDCAN_PSR_PXE_Msk                            /*!<Protocol Exception Event                 */

+#define FDCAN_PSR_TDCV_Pos        (16U)

+#define FDCAN_PSR_TDCV_Msk        (0x7FUL << FDCAN_PSR_TDCV_Pos)               /*!< 0x007F0000 */

+#define FDCAN_PSR_TDCV            FDCAN_PSR_TDCV_Msk                           /*!<Transmitter Delay Compensation Value     */

+

+/*****************  Bit definition for FDCAN_TDCR register  ********************/

+#define FDCAN_TDCR_TDCF_Pos       (0U)

+#define FDCAN_TDCR_TDCF_Msk       (0x7FUL << FDCAN_TDCR_TDCF_Pos)              /*!< 0x0000007F */

+#define FDCAN_TDCR_TDCF           FDCAN_TDCR_TDCF_Msk                          /*!<Transmitter Delay Compensation Filter    */

+#define FDCAN_TDCR_TDCO_Pos       (8U)

+#define FDCAN_TDCR_TDCO_Msk       (0x7FUL << FDCAN_TDCR_TDCO_Pos)              /*!< 0x00007F00 */

+#define FDCAN_TDCR_TDCO           FDCAN_TDCR_TDCO_Msk                          /*!<Transmitter Delay Compensation Offset    */

+

+/*****************  Bit definition for FDCAN_IR register  **********************/

+#define FDCAN_IR_RF0N_Pos         (0U)

+#define FDCAN_IR_RF0N_Msk         (0x1UL << FDCAN_IR_RF0N_Pos)                 /*!< 0x00000001 */

+#define FDCAN_IR_RF0N             FDCAN_IR_RF0N_Msk                            /*!<Rx FIFO 0 New Message                    */

+#define FDCAN_IR_RF0W_Pos         (1U)

+#define FDCAN_IR_RF0W_Msk         (0x1UL << FDCAN_IR_RF0W_Pos)                 /*!< 0x00000002 */

+#define FDCAN_IR_RF0W             FDCAN_IR_RF0W_Msk                            /*!<Rx FIFO 0 Watermark Reached              */

+#define FDCAN_IR_RF0F_Pos         (2U)

+#define FDCAN_IR_RF0F_Msk         (0x1UL << FDCAN_IR_RF0F_Pos)                 /*!< 0x00000004 */

+#define FDCAN_IR_RF0F             FDCAN_IR_RF0F_Msk                            /*!<Rx FIFO 0 Full                           */

+#define FDCAN_IR_RF0L_Pos         (3U)

+#define FDCAN_IR_RF0L_Msk         (0x1UL << FDCAN_IR_RF0L_Pos)                 /*!< 0x00000008 */

+#define FDCAN_IR_RF0L             FDCAN_IR_RF0L_Msk                            /*!<Rx FIFO 0 Message Lost                   */

+#define FDCAN_IR_RF1N_Pos         (4U)

+#define FDCAN_IR_RF1N_Msk         (0x1UL << FDCAN_IR_RF1N_Pos)                 /*!< 0x00000010 */

+#define FDCAN_IR_RF1N             FDCAN_IR_RF1N_Msk                            /*!<Rx FIFO 1 New Message                    */

+#define FDCAN_IR_RF1W_Pos         (5U)

+#define FDCAN_IR_RF1W_Msk         (0x1UL << FDCAN_IR_RF1W_Pos)                 /*!< 0x00000020 */

+#define FDCAN_IR_RF1W             FDCAN_IR_RF1W_Msk                            /*!<Rx FIFO 1 Watermark Reached              */

+#define FDCAN_IR_RF1F_Pos         (6U)

+#define FDCAN_IR_RF1F_Msk         (0x1UL << FDCAN_IR_RF1F_Pos)                 /*!< 0x00000040 */

+#define FDCAN_IR_RF1F             FDCAN_IR_RF1F_Msk                            /*!<Rx FIFO 1 Full                           */

+#define FDCAN_IR_RF1L_Pos         (7U)

+#define FDCAN_IR_RF1L_Msk         (0x1UL << FDCAN_IR_RF1L_Pos)                 /*!< 0x00000080 */

+#define FDCAN_IR_RF1L             FDCAN_IR_RF1L_Msk                            /*!<Rx FIFO 1 Message Lost                   */

+#define FDCAN_IR_HPM_Pos          (8U)

+#define FDCAN_IR_HPM_Msk          (0x1UL << FDCAN_IR_HPM_Pos)                  /*!< 0x00000100 */

+#define FDCAN_IR_HPM              FDCAN_IR_HPM_Msk                             /*!<High Priority Message                    */

+#define FDCAN_IR_TC_Pos           (9U)

+#define FDCAN_IR_TC_Msk           (0x1UL << FDCAN_IR_TC_Pos)                   /*!< 0x00000200 */

+#define FDCAN_IR_TC               FDCAN_IR_TC_Msk                              /*!<Transmission Completed                   */

+#define FDCAN_IR_TCF_Pos          (10U)

+#define FDCAN_IR_TCF_Msk          (0x1UL << FDCAN_IR_TCF_Pos)                  /*!< 0x00000400 */

+#define FDCAN_IR_TCF              FDCAN_IR_TCF_Msk                             /*!<Transmission Cancellation Finished       */

+#define FDCAN_IR_TFE_Pos          (11U)

+#define FDCAN_IR_TFE_Msk          (0x1UL << FDCAN_IR_TFE_Pos)                  /*!< 0x00000800 */

+#define FDCAN_IR_TFE              FDCAN_IR_TFE_Msk                             /*!<Tx FIFO Empty                            */

+#define FDCAN_IR_TEFN_Pos         (12U)

+#define FDCAN_IR_TEFN_Msk         (0x1UL << FDCAN_IR_TEFN_Pos)                 /*!< 0x00001000 */

+#define FDCAN_IR_TEFN             FDCAN_IR_TEFN_Msk                            /*!<Tx Event FIFO New Entry                  */

+#define FDCAN_IR_TEFW_Pos         (13U)

+#define FDCAN_IR_TEFW_Msk         (0x1UL << FDCAN_IR_TEFW_Pos)                 /*!< 0x00002000 */

+#define FDCAN_IR_TEFW             FDCAN_IR_TEFW_Msk                            /*!<Tx Event FIFO Watermark Reached          */

+#define FDCAN_IR_TEFF_Pos         (14U)

+#define FDCAN_IR_TEFF_Msk         (0x1UL << FDCAN_IR_TEFF_Pos)                 /*!< 0x00004000 */

+#define FDCAN_IR_TEFF             FDCAN_IR_TEFF_Msk                            /*!<Tx Event FIFO Full                       */

+#define FDCAN_IR_TEFL_Pos         (15U)

+#define FDCAN_IR_TEFL_Msk         (0x1UL << FDCAN_IR_TEFL_Pos)                 /*!< 0x00008000 */

+#define FDCAN_IR_TEFL             FDCAN_IR_TEFL_Msk                            /*!<Tx Event FIFO Element Lost               */

+#define FDCAN_IR_TSW_Pos          (16U)

+#define FDCAN_IR_TSW_Msk          (0x1UL << FDCAN_IR_TSW_Pos)                  /*!< 0x00010000 */

+#define FDCAN_IR_TSW              FDCAN_IR_TSW_Msk                             /*!<Timestamp Wraparound                     */

+#define FDCAN_IR_MRAF_Pos         (17U)

+#define FDCAN_IR_MRAF_Msk         (0x1UL << FDCAN_IR_MRAF_Pos)                 /*!< 0x00020000 */

+#define FDCAN_IR_MRAF             FDCAN_IR_MRAF_Msk                            /*!<Message RAM Access Failure               */

+#define FDCAN_IR_TOO_Pos          (18U)

+#define FDCAN_IR_TOO_Msk          (0x1UL << FDCAN_IR_TOO_Pos)                  /*!< 0x00040000 */

+#define FDCAN_IR_TOO              FDCAN_IR_TOO_Msk                             /*!<Timeout Occurred                         */

+#define FDCAN_IR_DRX_Pos          (19U)

+#define FDCAN_IR_DRX_Msk          (0x1UL << FDCAN_IR_DRX_Pos)                  /*!< 0x00080000 */

+#define FDCAN_IR_DRX              FDCAN_IR_DRX_Msk                             /*!<Message stored to Dedicated Rx Buffer    */

+#define FDCAN_IR_ELO_Pos          (22U)

+#define FDCAN_IR_ELO_Msk          (0x1UL << FDCAN_IR_ELO_Pos)                  /*!< 0x00400000 */

+#define FDCAN_IR_ELO              FDCAN_IR_ELO_Msk                             /*!<Error Logging Overflow                   */

+#define FDCAN_IR_EP_Pos           (23U)

+#define FDCAN_IR_EP_Msk           (0x1UL << FDCAN_IR_EP_Pos)                   /*!< 0x00800000 */

+#define FDCAN_IR_EP               FDCAN_IR_EP_Msk                              /*!<Error Passive                            */

+#define FDCAN_IR_EW_Pos           (24U)

+#define FDCAN_IR_EW_Msk           (0x1UL << FDCAN_IR_EW_Pos)                   /*!< 0x01000000 */

+#define FDCAN_IR_EW               FDCAN_IR_EW_Msk                              /*!<Warning Status                           */

+#define FDCAN_IR_BO_Pos           (25U)

+#define FDCAN_IR_BO_Msk           (0x1UL << FDCAN_IR_BO_Pos)                   /*!< 0x02000000 */

+#define FDCAN_IR_BO               FDCAN_IR_BO_Msk                              /*!<Bus_Off Status                           */

+#define FDCAN_IR_WDI_Pos          (26U)

+#define FDCAN_IR_WDI_Msk          (0x1UL << FDCAN_IR_WDI_Pos)                  /*!< 0x04000000 */

+#define FDCAN_IR_WDI              FDCAN_IR_WDI_Msk                             /*!<Watchdog Interrupt                       */

+#define FDCAN_IR_PEA_Pos          (27U)

+#define FDCAN_IR_PEA_Msk          (0x1UL << FDCAN_IR_PEA_Pos)                  /*!< 0x08000000 */

+#define FDCAN_IR_PEA              FDCAN_IR_PEA_Msk                             /*!<Protocol Error in Arbitration Phase      */

+#define FDCAN_IR_PED_Pos          (28U)

+#define FDCAN_IR_PED_Msk          (0x1UL << FDCAN_IR_PED_Pos)                  /*!< 0x10000000 */

+#define FDCAN_IR_PED              FDCAN_IR_PED_Msk                             /*!<Protocol Error in Data Phase             */

+#define FDCAN_IR_ARA_Pos          (29U)

+#define FDCAN_IR_ARA_Msk          (0x1UL << FDCAN_IR_ARA_Pos)                  /*!< 0x20000000 */

+#define FDCAN_IR_ARA              FDCAN_IR_ARA_Msk                             /*!<Access to Reserved Address               */

+

+/*****************  Bit definition for FDCAN_IE register  **********************/

+#define FDCAN_IE_RF0NE_Pos        (0U)

+#define FDCAN_IE_RF0NE_Msk        (0x1UL << FDCAN_IE_RF0NE_Pos)                /*!< 0x00000001 */

+#define FDCAN_IE_RF0NE            FDCAN_IE_RF0NE_Msk                           /*!<Rx FIFO 0 New Message Enable                 */

+#define FDCAN_IE_RF0WE_Pos        (1U)

+#define FDCAN_IE_RF0WE_Msk        (0x1UL << FDCAN_IE_RF0WE_Pos)                /*!< 0x00000002 */

+#define FDCAN_IE_RF0WE            FDCAN_IE_RF0WE_Msk                           /*!<Rx FIFO 0 Watermark Reached Enable           */

+#define FDCAN_IE_RF0FE_Pos        (2U)

+#define FDCAN_IE_RF0FE_Msk        (0x1UL << FDCAN_IE_RF0FE_Pos)                /*!< 0x00000004 */

+#define FDCAN_IE_RF0FE            FDCAN_IE_RF0FE_Msk                           /*!<Rx FIFO 0 Full Enable                        */

+#define FDCAN_IE_RF0LE_Pos        (3U)

+#define FDCAN_IE_RF0LE_Msk        (0x1UL << FDCAN_IE_RF0LE_Pos)                /*!< 0x00000008 */

+#define FDCAN_IE_RF0LE            FDCAN_IE_RF0LE_Msk                           /*!<Rx FIFO 0 Message Lost Enable                */

+#define FDCAN_IE_RF1NE_Pos        (4U)

+#define FDCAN_IE_RF1NE_Msk        (0x1UL << FDCAN_IE_RF1NE_Pos)                /*!< 0x00000010 */

+#define FDCAN_IE_RF1NE            FDCAN_IE_RF1NE_Msk                           /*!<Rx FIFO 1 New Message Enable                 */

+#define FDCAN_IE_RF1WE_Pos        (5U)

+#define FDCAN_IE_RF1WE_Msk        (0x1UL << FDCAN_IE_RF1WE_Pos)                /*!< 0x00000020 */

+#define FDCAN_IE_RF1WE            FDCAN_IE_RF1WE_Msk                           /*!<Rx FIFO 1 Watermark Reached Enable           */

+#define FDCAN_IE_RF1FE_Pos        (6U)

+#define FDCAN_IE_RF1FE_Msk        (0x1UL << FDCAN_IE_RF1FE_Pos)                /*!< 0x00000040 */

+#define FDCAN_IE_RF1FE            FDCAN_IE_RF1FE_Msk                           /*!<Rx FIFO 1 Full Enable                        */

+#define FDCAN_IE_RF1LE_Pos        (7U)

+#define FDCAN_IE_RF1LE_Msk        (0x1UL << FDCAN_IE_RF1LE_Pos)                /*!< 0x00000080 */

+#define FDCAN_IE_RF1LE            FDCAN_IE_RF1LE_Msk                           /*!<Rx FIFO 1 Message Lost Enable                */

+#define FDCAN_IE_HPME_Pos         (8U)

+#define FDCAN_IE_HPME_Msk         (0x1UL << FDCAN_IE_HPME_Pos)                 /*!< 0x00000100 */

+#define FDCAN_IE_HPME             FDCAN_IE_HPME_Msk                            /*!<High Priority Message Enable                 */

+#define FDCAN_IE_TCE_Pos          (9U)

+#define FDCAN_IE_TCE_Msk          (0x1UL << FDCAN_IE_TCE_Pos)                  /*!< 0x00000200 */

+#define FDCAN_IE_TCE              FDCAN_IE_TCE_Msk                             /*!<Transmission Completed Enable                */

+#define FDCAN_IE_TCFE_Pos         (10U)

+#define FDCAN_IE_TCFE_Msk         (0x1UL << FDCAN_IE_TCFE_Pos)                 /*!< 0x00000400 */

+#define FDCAN_IE_TCFE             FDCAN_IE_TCFE_Msk                            /*!<Transmission Cancellation Finished Enable    */

+#define FDCAN_IE_TFEE_Pos         (11U)

+#define FDCAN_IE_TFEE_Msk         (0x1UL << FDCAN_IE_TFEE_Pos)                 /*!< 0x00000800 */

+#define FDCAN_IE_TFEE             FDCAN_IE_TFEE_Msk                            /*!<Tx FIFO Empty Enable                         */

+#define FDCAN_IE_TEFNE_Pos        (12U)

+#define FDCAN_IE_TEFNE_Msk        (0x1UL << FDCAN_IE_TEFNE_Pos)                /*!< 0x00001000 */

+#define FDCAN_IE_TEFNE            FDCAN_IE_TEFNE_Msk                           /*!<Tx Event FIFO New Entry Enable               */

+#define FDCAN_IE_TEFWE_Pos        (13U)

+#define FDCAN_IE_TEFWE_Msk        (0x1UL << FDCAN_IE_TEFWE_Pos)                /*!< 0x00002000 */

+#define FDCAN_IE_TEFWE            FDCAN_IE_TEFWE_Msk                           /*!<Tx Event FIFO Watermark Reached Enable       */

+#define FDCAN_IE_TEFFE_Pos        (14U)

+#define FDCAN_IE_TEFFE_Msk        (0x1UL << FDCAN_IE_TEFFE_Pos)                /*!< 0x00004000 */

+#define FDCAN_IE_TEFFE            FDCAN_IE_TEFFE_Msk                           /*!<Tx Event FIFO Full Enable                    */

+#define FDCAN_IE_TEFLE_Pos        (15U)

+#define FDCAN_IE_TEFLE_Msk        (0x1UL << FDCAN_IE_TEFLE_Pos)                /*!< 0x00008000 */

+#define FDCAN_IE_TEFLE            FDCAN_IE_TEFLE_Msk                           /*!<Tx Event FIFO Element Lost Enable            */

+#define FDCAN_IE_TSWE_Pos         (16U)

+#define FDCAN_IE_TSWE_Msk         (0x1UL << FDCAN_IE_TSWE_Pos)                 /*!< 0x00010000 */

+#define FDCAN_IE_TSWE             FDCAN_IE_TSWE_Msk                            /*!<Timestamp Wraparound Enable                  */

+#define FDCAN_IE_MRAFE_Pos        (17U)

+#define FDCAN_IE_MRAFE_Msk        (0x1UL << FDCAN_IE_MRAFE_Pos)                /*!< 0x00020000 */

+#define FDCAN_IE_MRAFE            FDCAN_IE_MRAFE_Msk                           /*!<Message RAM Access Failure Enable            */

+#define FDCAN_IE_TOOE_Pos         (18U)

+#define FDCAN_IE_TOOE_Msk         (0x1UL << FDCAN_IE_TOOE_Pos)                 /*!< 0x00040000 */

+#define FDCAN_IE_TOOE             FDCAN_IE_TOOE_Msk                            /*!<Timeout Occurred Enable                      */

+#define FDCAN_IE_DRXE_Pos         (19U)

+#define FDCAN_IE_DRXE_Msk         (0x1UL << FDCAN_IE_DRXE_Pos)                 /*!< 0x00080000 */

+#define FDCAN_IE_DRXE             FDCAN_IE_DRXE_Msk                            /*!<Message stored to Dedicated Rx Buffer Enable */

+#define FDCAN_IE_BECE_Pos         (20U)

+#define FDCAN_IE_BECE_Msk         (0x1UL << FDCAN_IE_BECE_Pos)                 /*!< 0x00100000 */

+#define FDCAN_IE_BECE             FDCAN_IE_BECE_Msk                            /*!<Bit Error Corrected Interrupt Enable         */

+#define FDCAN_IE_BEUE_Pos         (21U)

+#define FDCAN_IE_BEUE_Msk         (0x1UL << FDCAN_IE_BEUE_Pos)                 /*!< 0x00200000 */

+#define FDCAN_IE_BEUE             FDCAN_IE_BEUE_Msk                            /*!<Bit Error Uncorrected Interrupt Enable       */

+#define FDCAN_IE_ELOE_Pos         (22U)

+#define FDCAN_IE_ELOE_Msk         (0x1UL << FDCAN_IE_ELOE_Pos)                 /*!< 0x00400000 */

+#define FDCAN_IE_ELOE             FDCAN_IE_ELOE_Msk                            /*!<Error Logging Overflow Enable                */

+#define FDCAN_IE_EPE_Pos          (23U)

+#define FDCAN_IE_EPE_Msk          (0x1UL << FDCAN_IE_EPE_Pos)                  /*!< 0x00800000 */

+#define FDCAN_IE_EPE              FDCAN_IE_EPE_Msk                             /*!<Error Passive Enable                         */

+#define FDCAN_IE_EWE_Pos          (24U)

+#define FDCAN_IE_EWE_Msk          (0x1UL << FDCAN_IE_EWE_Pos)                  /*!< 0x01000000 */

+#define FDCAN_IE_EWE              FDCAN_IE_EWE_Msk                             /*!<Warning Status Enable                        */

+#define FDCAN_IE_BOE_Pos          (25U)

+#define FDCAN_IE_BOE_Msk          (0x1UL << FDCAN_IE_BOE_Pos)                  /*!< 0x02000000 */

+#define FDCAN_IE_BOE              FDCAN_IE_BOE_Msk                             /*!<Bus_Off Status Enable                        */

+#define FDCAN_IE_WDIE_Pos         (26U)

+#define FDCAN_IE_WDIE_Msk         (0x1UL << FDCAN_IE_WDIE_Pos)                 /*!< 0x04000000 */

+#define FDCAN_IE_WDIE             FDCAN_IE_WDIE_Msk                            /*!<Watchdog Interrupt Enable                    */

+#define FDCAN_IE_PEAE_Pos         (27U)

+#define FDCAN_IE_PEAE_Msk         (0x1UL << FDCAN_IE_PEAE_Pos)                 /*!< 0x08000000 */

+#define FDCAN_IE_PEAE             FDCAN_IE_PEAE_Msk                            /*!<Protocol Error in Arbitration Phase Enable   */

+#define FDCAN_IE_PEDE_Pos         (28U)

+#define FDCAN_IE_PEDE_Msk         (0x1UL << FDCAN_IE_PEDE_Pos)                 /*!< 0x10000000 */

+#define FDCAN_IE_PEDE             FDCAN_IE_PEDE_Msk                            /*!<Protocol Error in Data Phase Enable          */

+#define FDCAN_IE_ARAE_Pos         (29U)

+#define FDCAN_IE_ARAE_Msk         (0x1UL << FDCAN_IE_ARAE_Pos)                 /*!< 0x20000000 */

+#define FDCAN_IE_ARAE             FDCAN_IE_ARAE_Msk                            /*!<Access to Reserved Address Enable            */

+

+/*****************  Bit definition for FDCAN_ILS register  **********************/

+#define FDCAN_ILS_RF0NL_Pos       (0U)

+#define FDCAN_ILS_RF0NL_Msk       (0x1UL << FDCAN_ILS_RF0NL_Pos)               /*!< 0x00000001 */

+#define FDCAN_ILS_RF0NL           FDCAN_ILS_RF0NL_Msk                          /*!<Rx FIFO 0 New Message Line                  */

+#define FDCAN_ILS_RF0WL_Pos       (1U)

+#define FDCAN_ILS_RF0WL_Msk       (0x1UL << FDCAN_ILS_RF0WL_Pos)               /*!< 0x00000002 */

+#define FDCAN_ILS_RF0WL           FDCAN_ILS_RF0WL_Msk                          /*!<Rx FIFO 0 Watermark Reached Line            */

+#define FDCAN_ILS_RF0FL_Pos       (2U)

+#define FDCAN_ILS_RF0FL_Msk       (0x1UL << FDCAN_ILS_RF0FL_Pos)               /*!< 0x00000004 */

+#define FDCAN_ILS_RF0FL           FDCAN_ILS_RF0FL_Msk                          /*!<Rx FIFO 0 Full Line                         */

+#define FDCAN_ILS_RF0LL_Pos       (3U)

+#define FDCAN_ILS_RF0LL_Msk       (0x1UL << FDCAN_ILS_RF0LL_Pos)               /*!< 0x00000008 */

+#define FDCAN_ILS_RF0LL           FDCAN_ILS_RF0LL_Msk                          /*!<Rx FIFO 0 Message Lost Line                 */

+#define FDCAN_ILS_RF1NL_Pos       (4U)

+#define FDCAN_ILS_RF1NL_Msk       (0x1UL << FDCAN_ILS_RF1NL_Pos)               /*!< 0x00000010 */

+#define FDCAN_ILS_RF1NL           FDCAN_ILS_RF1NL_Msk                          /*!<Rx FIFO 1 New Message Line                  */

+#define FDCAN_ILS_RF1WL_Pos       (5U)

+#define FDCAN_ILS_RF1WL_Msk       (0x1UL << FDCAN_ILS_RF1WL_Pos)               /*!< 0x00000020 */

+#define FDCAN_ILS_RF1WL           FDCAN_ILS_RF1WL_Msk                          /*!<Rx FIFO 1 Watermark Reached Line            */

+#define FDCAN_ILS_RF1FL_Pos       (6U)

+#define FDCAN_ILS_RF1FL_Msk       (0x1UL << FDCAN_ILS_RF1FL_Pos)               /*!< 0x00000040 */

+#define FDCAN_ILS_RF1FL           FDCAN_ILS_RF1FL_Msk                          /*!<Rx FIFO 1 Full Line                         */

+#define FDCAN_ILS_RF1LL_Pos       (7U)

+#define FDCAN_ILS_RF1LL_Msk       (0x1UL << FDCAN_ILS_RF1LL_Pos)               /*!< 0x00000080 */

+#define FDCAN_ILS_RF1LL           FDCAN_ILS_RF1LL_Msk                          /*!<Rx FIFO 1 Message Lost Line                 */

+#define FDCAN_ILS_HPML_Pos        (8U)

+#define FDCAN_ILS_HPML_Msk        (0x1UL << FDCAN_ILS_HPML_Pos)                /*!< 0x00000100 */

+#define FDCAN_ILS_HPML            FDCAN_ILS_HPML_Msk                           /*!<High Priority Message Line                  */

+#define FDCAN_ILS_TCL_Pos         (9U)

+#define FDCAN_ILS_TCL_Msk         (0x1UL << FDCAN_ILS_TCL_Pos)                 /*!< 0x00000200 */

+#define FDCAN_ILS_TCL             FDCAN_ILS_TCL_Msk                            /*!<Transmission Completed Line                 */

+#define FDCAN_ILS_TCFL_Pos        (10U)

+#define FDCAN_ILS_TCFL_Msk        (0x1UL << FDCAN_ILS_TCFL_Pos)                /*!< 0x00000400 */

+#define FDCAN_ILS_TCFL            FDCAN_ILS_TCFL_Msk                           /*!<Transmission Cancellation Finished Line     */

+#define FDCAN_ILS_TFEL_Pos        (11U)

+#define FDCAN_ILS_TFEL_Msk        (0x1UL << FDCAN_ILS_TFEL_Pos)                /*!< 0x00000800 */

+#define FDCAN_ILS_TFEL            FDCAN_ILS_TFEL_Msk                           /*!<Tx FIFO Empty Line                          */

+#define FDCAN_ILS_TEFNL_Pos       (12U)

+#define FDCAN_ILS_TEFNL_Msk       (0x1UL << FDCAN_ILS_TEFNL_Pos)               /*!< 0x00001000 */

+#define FDCAN_ILS_TEFNL           FDCAN_ILS_TEFNL_Msk                          /*!<Tx Event FIFO New Entry Line                */

+#define FDCAN_ILS_TEFWL_Pos       (13U)

+#define FDCAN_ILS_TEFWL_Msk       (0x1UL << FDCAN_ILS_TEFWL_Pos)               /*!< 0x00002000 */

+#define FDCAN_ILS_TEFWL           FDCAN_ILS_TEFWL_Msk                          /*!<Tx Event FIFO Watermark Reached Line        */

+#define FDCAN_ILS_TEFFL_Pos       (14U)

+#define FDCAN_ILS_TEFFL_Msk       (0x1UL << FDCAN_ILS_TEFFL_Pos)               /*!< 0x00004000 */

+#define FDCAN_ILS_TEFFL           FDCAN_ILS_TEFFL_Msk                          /*!<Tx Event FIFO Full Line                     */

+#define FDCAN_ILS_TEFLL_Pos       (15U)

+#define FDCAN_ILS_TEFLL_Msk       (0x1UL << FDCAN_ILS_TEFLL_Pos)               /*!< 0x00008000 */

+#define FDCAN_ILS_TEFLL           FDCAN_ILS_TEFLL_Msk                          /*!<Tx Event FIFO Element Lost Line             */

+#define FDCAN_ILS_TSWL_Pos        (16U)

+#define FDCAN_ILS_TSWL_Msk        (0x1UL << FDCAN_ILS_TSWL_Pos)                /*!< 0x00010000 */

+#define FDCAN_ILS_TSWL            FDCAN_ILS_TSWL_Msk                           /*!<Timestamp Wraparound Line                   */

+#define FDCAN_ILS_MRAFE_Pos       (17U)

+#define FDCAN_ILS_MRAFE_Msk       (0x1UL << FDCAN_ILS_MRAFE_Pos)               /*!< 0x00020000 */

+#define FDCAN_ILS_MRAFE           FDCAN_ILS_MRAFE_Msk                          /*!<Message RAM Access Failure Line             */

+#define FDCAN_ILS_TOOE_Pos        (18U)

+#define FDCAN_ILS_TOOE_Msk        (0x1UL << FDCAN_ILS_TOOE_Pos)                /*!< 0x00040000 */

+#define FDCAN_ILS_TOOE            FDCAN_ILS_TOOE_Msk                           /*!<Timeout Occurred Line                       */

+#define FDCAN_ILS_DRXE_Pos        (19U)

+#define FDCAN_ILS_DRXE_Msk        (0x1UL << FDCAN_ILS_DRXE_Pos)                /*!< 0x00080000 */

+#define FDCAN_ILS_DRXE            FDCAN_ILS_DRXE_Msk                           /*!<Message stored to Dedicated Rx Buffer Line  */

+#define FDCAN_ILS_BECE_Pos        (20U)

+#define FDCAN_ILS_BECE_Msk        (0x1UL << FDCAN_ILS_BECE_Pos)                /*!< 0x00100000 */

+#define FDCAN_ILS_BECE            FDCAN_ILS_BECE_Msk                           /*!<Bit Error Corrected Interrupt Line          */

+#define FDCAN_ILS_BEUE_Pos        (21U)

+#define FDCAN_ILS_BEUE_Msk        (0x1UL << FDCAN_ILS_BEUE_Pos)                /*!< 0x00200000 */

+#define FDCAN_ILS_BEUE            FDCAN_ILS_BEUE_Msk                           /*!<Bit Error Uncorrected Interrupt Line        */

+#define FDCAN_ILS_ELOE_Pos        (22U)

+#define FDCAN_ILS_ELOE_Msk        (0x1UL << FDCAN_ILS_ELOE_Pos)                /*!< 0x00400000 */

+#define FDCAN_ILS_ELOE            FDCAN_ILS_ELOE_Msk                           /*!<Error Logging Overflow Line                 */

+#define FDCAN_ILS_EPE_Pos         (23U)

+#define FDCAN_ILS_EPE_Msk         (0x1UL << FDCAN_ILS_EPE_Pos)                 /*!< 0x00800000 */

+#define FDCAN_ILS_EPE             FDCAN_ILS_EPE_Msk                            /*!<Error Passive Line                          */

+#define FDCAN_ILS_EWE_Pos         (24U)

+#define FDCAN_ILS_EWE_Msk         (0x1UL << FDCAN_ILS_EWE_Pos)                 /*!< 0x01000000 */

+#define FDCAN_ILS_EWE             FDCAN_ILS_EWE_Msk                            /*!<Warning Status Line                         */

+#define FDCAN_ILS_BOE_Pos         (25U)

+#define FDCAN_ILS_BOE_Msk         (0x1UL << FDCAN_ILS_BOE_Pos)                 /*!< 0x02000000 */

+#define FDCAN_ILS_BOE             FDCAN_ILS_BOE_Msk                            /*!<Bus_Off Status Line                         */

+#define FDCAN_ILS_WDIE_Pos        (26U)

+#define FDCAN_ILS_WDIE_Msk        (0x1UL << FDCAN_ILS_WDIE_Pos)                /*!< 0x04000000 */

+#define FDCAN_ILS_WDIE            FDCAN_ILS_WDIE_Msk                           /*!<Watchdog Interrupt Line                     */

+#define FDCAN_ILS_PEAE_Pos        (27U)

+#define FDCAN_ILS_PEAE_Msk        (0x1UL << FDCAN_ILS_PEAE_Pos)                /*!< 0x08000000 */

+#define FDCAN_ILS_PEAE            FDCAN_ILS_PEAE_Msk                           /*!<Protocol Error in Arbitration Phase Line    */

+#define FDCAN_ILS_PEDE_Pos        (28U)

+#define FDCAN_ILS_PEDE_Msk        (0x1UL << FDCAN_ILS_PEDE_Pos)                /*!< 0x10000000 */

+#define FDCAN_ILS_PEDE            FDCAN_ILS_PEDE_Msk                           /*!<Protocol Error in Data Phase Line           */

+#define FDCAN_ILS_ARAE_Pos        (29U)

+#define FDCAN_ILS_ARAE_Msk        (0x1UL << FDCAN_ILS_ARAE_Pos)                /*!< 0x20000000 */

+#define FDCAN_ILS_ARAE            FDCAN_ILS_ARAE_Msk                           /*!<Access to Reserved Address Line             */

+

+/*****************  Bit definition for FDCAN_ILE register  **********************/

+#define FDCAN_ILE_EINT0_Pos       (0U)

+#define FDCAN_ILE_EINT0_Msk       (0x1UL << FDCAN_ILE_EINT0_Pos)               /*!< 0x00000001 */

+#define FDCAN_ILE_EINT0           FDCAN_ILE_EINT0_Msk                          /*!<Enable Interrupt Line 0                   */

+#define FDCAN_ILE_EINT1_Pos       (1U)

+#define FDCAN_ILE_EINT1_Msk       (0x1UL << FDCAN_ILE_EINT1_Pos)               /*!< 0x00000002 */

+#define FDCAN_ILE_EINT1           FDCAN_ILE_EINT1_Msk                          /*!<Enable Interrupt Line 1                   */

+

+/*****************  Bit definition for FDCAN_GFC register  **********************/

+#define FDCAN_GFC_RRFE_Pos        (0U)

+#define FDCAN_GFC_RRFE_Msk        (0x1UL << FDCAN_GFC_RRFE_Pos)                /*!< 0x00000001 */

+#define FDCAN_GFC_RRFE            FDCAN_GFC_RRFE_Msk                           /*!<Reject Remote Frames Extended             */

+#define FDCAN_GFC_RRFS_Pos        (1U)

+#define FDCAN_GFC_RRFS_Msk        (0x1UL << FDCAN_GFC_RRFS_Pos)                /*!< 0x00000002 */

+#define FDCAN_GFC_RRFS            FDCAN_GFC_RRFS_Msk                           /*!<Reject Remote Frames Standard             */

+#define FDCAN_GFC_ANFE_Pos        (2U)

+#define FDCAN_GFC_ANFE_Msk        (0x3UL << FDCAN_GFC_ANFE_Pos)                /*!< 0x0000000C */

+#define FDCAN_GFC_ANFE            FDCAN_GFC_ANFE_Msk                           /*!<Accept Non-matching Frames Extended       */

+#define FDCAN_GFC_ANFS_Pos        (4U)

+#define FDCAN_GFC_ANFS_Msk        (0x3UL << FDCAN_GFC_ANFS_Pos)                /*!< 0x00000030 */

+#define FDCAN_GFC_ANFS            FDCAN_GFC_ANFS_Msk                           /*!<Accept Non-matching Frames Standard       */

+

+/*****************  Bit definition for FDCAN_SIDFC register  ********************/

+#define FDCAN_SIDFC_FLSSA_Pos     (2U)

+#define FDCAN_SIDFC_FLSSA_Msk     (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)          /*!< 0x0000FFFC */

+#define FDCAN_SIDFC_FLSSA         FDCAN_SIDFC_FLSSA_Msk                        /*!<Filter List Standard Start Address        */

+#define FDCAN_SIDFC_LSS_Pos       (16U)

+#define FDCAN_SIDFC_LSS_Msk       (0xFFUL << FDCAN_SIDFC_LSS_Pos)              /*!< 0x00FF0000 */

+#define FDCAN_SIDFC_LSS           FDCAN_SIDFC_LSS_Msk                          /*!<List Size Standard                        */

+

+/*****************  Bit definition for FDCAN_XIDFC register  ********************/

+#define FDCAN_XIDFC_FLESA_Pos     (2U)

+#define FDCAN_XIDFC_FLESA_Msk     (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)          /*!< 0x0000FFFC */

+#define FDCAN_XIDFC_FLESA         FDCAN_XIDFC_FLESA_Msk                        /*!<Filter List Standard Start Address        */

+#define FDCAN_XIDFC_LSE_Pos       (16U)

+#define FDCAN_XIDFC_LSE_Msk       (0x7FUL << FDCAN_XIDFC_LSE_Pos)              /*!< 0x007F0000 */

+#define FDCAN_XIDFC_LSE           FDCAN_XIDFC_LSE_Msk                          /*!<List Size Extended                        */

+

+/*****************  Bit definition for FDCAN_XIDAM register  ********************/

+#define FDCAN_XIDAM_EIDM_Pos      (0U)

+#define FDCAN_XIDAM_EIDM_Msk      (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)       /*!< 0x1FFFFFFF */

+#define FDCAN_XIDAM_EIDM          FDCAN_XIDAM_EIDM_Msk                         /*!<Extended ID Mask                          */

+

+/*****************  Bit definition for FDCAN_HPMS register  *********************/

+#define FDCAN_HPMS_BIDX_Pos       (0U)

+#define FDCAN_HPMS_BIDX_Msk       (0x3FUL << FDCAN_HPMS_BIDX_Pos)              /*!< 0x0000003F */

+#define FDCAN_HPMS_BIDX           FDCAN_HPMS_BIDX_Msk                          /*!<Buffer Index                              */

+#define FDCAN_HPMS_MSI_Pos        (6U)

+#define FDCAN_HPMS_MSI_Msk        (0x3UL << FDCAN_HPMS_MSI_Pos)                /*!< 0x000000C0 */

+#define FDCAN_HPMS_MSI            FDCAN_HPMS_MSI_Msk                           /*!<Message Storage Indicator                 */

+#define FDCAN_HPMS_FIDX_Pos       (8U)

+#define FDCAN_HPMS_FIDX_Msk       (0x7FUL << FDCAN_HPMS_FIDX_Pos)              /*!< 0x00007F00 */

+#define FDCAN_HPMS_FIDX           FDCAN_HPMS_FIDX_Msk                          /*!<Filter Index                              */

+#define FDCAN_HPMS_FLST_Pos       (15U)

+#define FDCAN_HPMS_FLST_Msk       (0x1UL << FDCAN_HPMS_FLST_Pos)               /*!< 0x00008000 */

+#define FDCAN_HPMS_FLST           FDCAN_HPMS_FLST_Msk                          /*!<Filter List                               */

+

+/*****************  Bit definition for FDCAN_NDAT1 register  ********************/

+#define FDCAN_NDAT1_ND0_Pos       (0U)

+#define FDCAN_NDAT1_ND0_Msk       (0x1UL << FDCAN_NDAT1_ND0_Pos)               /*!< 0x00000001 */

+#define FDCAN_NDAT1_ND0           FDCAN_NDAT1_ND0_Msk                          /*!<New Data flag of Rx Buffer 0              */

+#define FDCAN_NDAT1_ND1_Pos       (1U)

+#define FDCAN_NDAT1_ND1_Msk       (0x1UL << FDCAN_NDAT1_ND1_Pos)               /*!< 0x00000002 */

+#define FDCAN_NDAT1_ND1           FDCAN_NDAT1_ND1_Msk                          /*!<New Data flag of Rx Buffer 1              */

+#define FDCAN_NDAT1_ND2_Pos       (2U)

+#define FDCAN_NDAT1_ND2_Msk       (0x1UL << FDCAN_NDAT1_ND2_Pos)               /*!< 0x00000004 */

+#define FDCAN_NDAT1_ND2           FDCAN_NDAT1_ND2_Msk                          /*!<New Data flag of Rx Buffer 2              */

+#define FDCAN_NDAT1_ND3_Pos       (3U)

+#define FDCAN_NDAT1_ND3_Msk       (0x1UL << FDCAN_NDAT1_ND3_Pos)               /*!< 0x00000008 */

+#define FDCAN_NDAT1_ND3           FDCAN_NDAT1_ND3_Msk                          /*!<New Data flag of Rx Buffer 3              */

+#define FDCAN_NDAT1_ND4_Pos       (4U)

+#define FDCAN_NDAT1_ND4_Msk       (0x1UL << FDCAN_NDAT1_ND4_Pos)               /*!< 0x00000010 */

+#define FDCAN_NDAT1_ND4           FDCAN_NDAT1_ND4_Msk                          /*!<New Data flag of Rx Buffer 4              */

+#define FDCAN_NDAT1_ND5_Pos       (5U)

+#define FDCAN_NDAT1_ND5_Msk       (0x1UL << FDCAN_NDAT1_ND5_Pos)               /*!< 0x00000020 */

+#define FDCAN_NDAT1_ND5           FDCAN_NDAT1_ND5_Msk                          /*!<New Data flag of Rx Buffer 5              */

+#define FDCAN_NDAT1_ND6_Pos       (6U)

+#define FDCAN_NDAT1_ND6_Msk       (0x1UL << FDCAN_NDAT1_ND6_Pos)               /*!< 0x00000040 */

+#define FDCAN_NDAT1_ND6           FDCAN_NDAT1_ND6_Msk                          /*!<New Data flag of Rx Buffer 6              */

+#define FDCAN_NDAT1_ND7_Pos       (7U)

+#define FDCAN_NDAT1_ND7_Msk       (0x1UL << FDCAN_NDAT1_ND7_Pos)               /*!< 0x00000080 */

+#define FDCAN_NDAT1_ND7           FDCAN_NDAT1_ND7_Msk                          /*!<New Data flag of Rx Buffer 7              */

+#define FDCAN_NDAT1_ND8_Pos       (8U)

+#define FDCAN_NDAT1_ND8_Msk       (0x1UL << FDCAN_NDAT1_ND8_Pos)               /*!< 0x00000100 */

+#define FDCAN_NDAT1_ND8           FDCAN_NDAT1_ND8_Msk                          /*!<New Data flag of Rx Buffer 8              */

+#define FDCAN_NDAT1_ND9_Pos       (9U)

+#define FDCAN_NDAT1_ND9_Msk       (0x1UL << FDCAN_NDAT1_ND9_Pos)               /*!< 0x00000200 */

+#define FDCAN_NDAT1_ND9           FDCAN_NDAT1_ND9_Msk                          /*!<New Data flag of Rx Buffer 9              */

+#define FDCAN_NDAT1_ND10_Pos      (10U)

+#define FDCAN_NDAT1_ND10_Msk      (0x1UL << FDCAN_NDAT1_ND10_Pos)              /*!< 0x00000400 */

+#define FDCAN_NDAT1_ND10          FDCAN_NDAT1_ND10_Msk                         /*!<New Data flag of Rx Buffer 10             */

+#define FDCAN_NDAT1_ND11_Pos      (11U)

+#define FDCAN_NDAT1_ND11_Msk      (0x1UL << FDCAN_NDAT1_ND11_Pos)              /*!< 0x00000800 */

+#define FDCAN_NDAT1_ND11          FDCAN_NDAT1_ND11_Msk                         /*!<New Data flag of Rx Buffer 11             */

+#define FDCAN_NDAT1_ND12_Pos      (12U)

+#define FDCAN_NDAT1_ND12_Msk      (0x1UL << FDCAN_NDAT1_ND12_Pos)              /*!< 0x00001000 */

+#define FDCAN_NDAT1_ND12          FDCAN_NDAT1_ND12_Msk                         /*!<New Data flag of Rx Buffer 12             */

+#define FDCAN_NDAT1_ND13_Pos      (13U)

+#define FDCAN_NDAT1_ND13_Msk      (0x1UL << FDCAN_NDAT1_ND13_Pos)              /*!< 0x00002000 */

+#define FDCAN_NDAT1_ND13          FDCAN_NDAT1_ND13_Msk                         /*!<New Data flag of Rx Buffer 13             */

+#define FDCAN_NDAT1_ND14_Pos      (14U)

+#define FDCAN_NDAT1_ND14_Msk      (0x1UL << FDCAN_NDAT1_ND14_Pos)              /*!< 0x00004000 */

+#define FDCAN_NDAT1_ND14          FDCAN_NDAT1_ND14_Msk                         /*!<New Data flag of Rx Buffer 14             */

+#define FDCAN_NDAT1_ND15_Pos      (15U)

+#define FDCAN_NDAT1_ND15_Msk      (0x1UL << FDCAN_NDAT1_ND15_Pos)              /*!< 0x00008000 */

+#define FDCAN_NDAT1_ND15          FDCAN_NDAT1_ND15_Msk                         /*!<New Data flag of Rx Buffer 15             */

+#define FDCAN_NDAT1_ND16_Pos      (16U)

+#define FDCAN_NDAT1_ND16_Msk      (0x1UL << FDCAN_NDAT1_ND16_Pos)              /*!< 0x00010000 */

+#define FDCAN_NDAT1_ND16          FDCAN_NDAT1_ND16_Msk                         /*!<New Data flag of Rx Buffer 16             */

+#define FDCAN_NDAT1_ND17_Pos      (17U)

+#define FDCAN_NDAT1_ND17_Msk      (0x1UL << FDCAN_NDAT1_ND17_Pos)              /*!< 0x00020000 */

+#define FDCAN_NDAT1_ND17          FDCAN_NDAT1_ND17_Msk                         /*!<New Data flag of Rx Buffer 17             */

+#define FDCAN_NDAT1_ND18_Pos      (18U)

+#define FDCAN_NDAT1_ND18_Msk      (0x1UL << FDCAN_NDAT1_ND18_Pos)              /*!< 0x00040000 */

+#define FDCAN_NDAT1_ND18          FDCAN_NDAT1_ND18_Msk                         /*!<New Data flag of Rx Buffer 18             */

+#define FDCAN_NDAT1_ND19_Pos      (19U)

+#define FDCAN_NDAT1_ND19_Msk      (0x1UL << FDCAN_NDAT1_ND19_Pos)              /*!< 0x00080000 */

+#define FDCAN_NDAT1_ND19          FDCAN_NDAT1_ND19_Msk                         /*!<New Data flag of Rx Buffer 19             */

+#define FDCAN_NDAT1_ND20_Pos      (20U)

+#define FDCAN_NDAT1_ND20_Msk      (0x1UL << FDCAN_NDAT1_ND20_Pos)              /*!< 0x00100000 */

+#define FDCAN_NDAT1_ND20          FDCAN_NDAT1_ND20_Msk                         /*!<New Data flag of Rx Buffer 20             */

+#define FDCAN_NDAT1_ND21_Pos      (21U)

+#define FDCAN_NDAT1_ND21_Msk      (0x1UL << FDCAN_NDAT1_ND21_Pos)              /*!< 0x00200000 */

+#define FDCAN_NDAT1_ND21          FDCAN_NDAT1_ND21_Msk                         /*!<New Data flag of Rx Buffer 21             */

+#define FDCAN_NDAT1_ND22_Pos      (22U)

+#define FDCAN_NDAT1_ND22_Msk      (0x1UL << FDCAN_NDAT1_ND22_Pos)              /*!< 0x00400000 */

+#define FDCAN_NDAT1_ND22          FDCAN_NDAT1_ND22_Msk                         /*!<New Data flag of Rx Buffer 22             */

+#define FDCAN_NDAT1_ND23_Pos      (23U)

+#define FDCAN_NDAT1_ND23_Msk      (0x1UL << FDCAN_NDAT1_ND23_Pos)              /*!< 0x00800000 */

+#define FDCAN_NDAT1_ND23          FDCAN_NDAT1_ND23_Msk                         /*!<New Data flag of Rx Buffer 23             */

+#define FDCAN_NDAT1_ND24_Pos      (24U)

+#define FDCAN_NDAT1_ND24_Msk      (0x1UL << FDCAN_NDAT1_ND24_Pos)              /*!< 0x01000000 */

+#define FDCAN_NDAT1_ND24          FDCAN_NDAT1_ND24_Msk                         /*!<New Data flag of Rx Buffer 24             */

+#define FDCAN_NDAT1_ND25_Pos      (25U)

+#define FDCAN_NDAT1_ND25_Msk      (0x1UL << FDCAN_NDAT1_ND25_Pos)              /*!< 0x02000000 */

+#define FDCAN_NDAT1_ND25          FDCAN_NDAT1_ND25_Msk                         /*!<New Data flag of Rx Buffer 25             */

+#define FDCAN_NDAT1_ND26_Pos      (26U)

+#define FDCAN_NDAT1_ND26_Msk      (0x1UL << FDCAN_NDAT1_ND26_Pos)              /*!< 0x04000000 */

+#define FDCAN_NDAT1_ND26          FDCAN_NDAT1_ND26_Msk                         /*!<New Data flag of Rx Buffer 26             */

+#define FDCAN_NDAT1_ND27_Pos      (27U)

+#define FDCAN_NDAT1_ND27_Msk      (0x1UL << FDCAN_NDAT1_ND27_Pos)              /*!< 0x08000000 */

+#define FDCAN_NDAT1_ND27          FDCAN_NDAT1_ND27_Msk                         /*!<New Data flag of Rx Buffer 27             */

+#define FDCAN_NDAT1_ND28_Pos      (28U)

+#define FDCAN_NDAT1_ND28_Msk      (0x1UL << FDCAN_NDAT1_ND28_Pos)              /*!< 0x10000000 */

+#define FDCAN_NDAT1_ND28          FDCAN_NDAT1_ND28_Msk                         /*!<New Data flag of Rx Buffer 28             */

+#define FDCAN_NDAT1_ND29_Pos      (29U)

+#define FDCAN_NDAT1_ND29_Msk      (0x1UL << FDCAN_NDAT1_ND29_Pos)              /*!< 0x20000000 */

+#define FDCAN_NDAT1_ND29          FDCAN_NDAT1_ND29_Msk                         /*!<New Data flag of Rx Buffer 29             */

+#define FDCAN_NDAT1_ND30_Pos      (30U)

+#define FDCAN_NDAT1_ND30_Msk      (0x1UL << FDCAN_NDAT1_ND30_Pos)              /*!< 0x40000000 */

+#define FDCAN_NDAT1_ND30          FDCAN_NDAT1_ND30_Msk                         /*!<New Data flag of Rx Buffer 30             */

+#define FDCAN_NDAT1_ND31_Pos      (31U)

+#define FDCAN_NDAT1_ND31_Msk      (0x1UL << FDCAN_NDAT1_ND31_Pos)              /*!< 0x80000000 */

+#define FDCAN_NDAT1_ND31          FDCAN_NDAT1_ND31_Msk                         /*!<New Data flag of Rx Buffer 31             */

+

+/*****************  Bit definition for FDCAN_NDAT2 register  ********************/

+#define FDCAN_NDAT2_ND32_Pos      (0U)

+#define FDCAN_NDAT2_ND32_Msk      (0x1UL << FDCAN_NDAT2_ND32_Pos)              /*!< 0x00000001 */

+#define FDCAN_NDAT2_ND32          FDCAN_NDAT2_ND32_Msk                         /*!<New Data flag of Rx Buffer 32             */

+#define FDCAN_NDAT2_ND33_Pos      (1U)

+#define FDCAN_NDAT2_ND33_Msk      (0x1UL << FDCAN_NDAT2_ND33_Pos)              /*!< 0x00000002 */

+#define FDCAN_NDAT2_ND33          FDCAN_NDAT2_ND33_Msk                         /*!<New Data flag of Rx Buffer 33             */

+#define FDCAN_NDAT2_ND34_Pos      (2U)

+#define FDCAN_NDAT2_ND34_Msk      (0x1UL << FDCAN_NDAT2_ND34_Pos)              /*!< 0x00000004 */

+#define FDCAN_NDAT2_ND34          FDCAN_NDAT2_ND34_Msk                         /*!<New Data flag of Rx Buffer 34             */

+#define FDCAN_NDAT2_ND35_Pos      (3U)

+#define FDCAN_NDAT2_ND35_Msk      (0x1UL << FDCAN_NDAT2_ND35_Pos)              /*!< 0x00000008 */

+#define FDCAN_NDAT2_ND35          FDCAN_NDAT2_ND35_Msk                         /*!<New Data flag of Rx Buffer 35             */

+#define FDCAN_NDAT2_ND36_Pos      (4U)

+#define FDCAN_NDAT2_ND36_Msk      (0x1UL << FDCAN_NDAT2_ND36_Pos)              /*!< 0x00000010 */

+#define FDCAN_NDAT2_ND36          FDCAN_NDAT2_ND36_Msk                         /*!<New Data flag of Rx Buffer 36             */

+#define FDCAN_NDAT2_ND37_Pos      (5U)

+#define FDCAN_NDAT2_ND37_Msk      (0x1UL << FDCAN_NDAT2_ND37_Pos)              /*!< 0x00000020 */

+#define FDCAN_NDAT2_ND37          FDCAN_NDAT2_ND37_Msk                         /*!<New Data flag of Rx Buffer 37             */

+#define FDCAN_NDAT2_ND38_Pos      (6U)

+#define FDCAN_NDAT2_ND38_Msk      (0x1UL << FDCAN_NDAT2_ND38_Pos)              /*!< 0x00000040 */

+#define FDCAN_NDAT2_ND38          FDCAN_NDAT2_ND38_Msk                         /*!<New Data flag of Rx Buffer 38             */

+#define FDCAN_NDAT2_ND39_Pos      (7U)

+#define FDCAN_NDAT2_ND39_Msk      (0x1UL << FDCAN_NDAT2_ND39_Pos)              /*!< 0x00000080 */

+#define FDCAN_NDAT2_ND39          FDCAN_NDAT2_ND39_Msk                         /*!<New Data flag of Rx Buffer 39             */

+#define FDCAN_NDAT2_ND40_Pos      (8U)

+#define FDCAN_NDAT2_ND40_Msk      (0x1UL << FDCAN_NDAT2_ND40_Pos)              /*!< 0x00000100 */

+#define FDCAN_NDAT2_ND40          FDCAN_NDAT2_ND40_Msk                         /*!<New Data flag of Rx Buffer 40             */

+#define FDCAN_NDAT2_ND41_Pos      (9U)

+#define FDCAN_NDAT2_ND41_Msk      (0x1UL << FDCAN_NDAT2_ND41_Pos)              /*!< 0x00000200 */

+#define FDCAN_NDAT2_ND41          FDCAN_NDAT2_ND41_Msk                         /*!<New Data flag of Rx Buffer 41             */

+#define FDCAN_NDAT2_ND42_Pos      (10U)

+#define FDCAN_NDAT2_ND42_Msk      (0x1UL << FDCAN_NDAT2_ND42_Pos)              /*!< 0x00000400 */

+#define FDCAN_NDAT2_ND42          FDCAN_NDAT2_ND42_Msk                         /*!<New Data flag of Rx Buffer 42             */

+#define FDCAN_NDAT2_ND43_Pos      (11U)

+#define FDCAN_NDAT2_ND43_Msk      (0x1UL << FDCAN_NDAT2_ND43_Pos)              /*!< 0x00000800 */

+#define FDCAN_NDAT2_ND43          FDCAN_NDAT2_ND43_Msk                         /*!<New Data flag of Rx Buffer 43             */

+#define FDCAN_NDAT2_ND44_Pos      (12U)

+#define FDCAN_NDAT2_ND44_Msk      (0x1UL << FDCAN_NDAT2_ND44_Pos)              /*!< 0x00001000 */

+#define FDCAN_NDAT2_ND44          FDCAN_NDAT2_ND44_Msk                         /*!<New Data flag of Rx Buffer 44             */

+#define FDCAN_NDAT2_ND45_Pos      (13U)

+#define FDCAN_NDAT2_ND45_Msk      (0x1UL << FDCAN_NDAT2_ND45_Pos)              /*!< 0x00002000 */

+#define FDCAN_NDAT2_ND45          FDCAN_NDAT2_ND45_Msk                         /*!<New Data flag of Rx Buffer 45             */

+#define FDCAN_NDAT2_ND46_Pos      (14U)

+#define FDCAN_NDAT2_ND46_Msk      (0x1UL << FDCAN_NDAT2_ND46_Pos)              /*!< 0x00004000 */

+#define FDCAN_NDAT2_ND46          FDCAN_NDAT2_ND46_Msk                         /*!<New Data flag of Rx Buffer 46             */

+#define FDCAN_NDAT2_ND47_Pos      (15U)

+#define FDCAN_NDAT2_ND47_Msk      (0x1UL << FDCAN_NDAT2_ND47_Pos)              /*!< 0x00008000 */

+#define FDCAN_NDAT2_ND47          FDCAN_NDAT2_ND47_Msk                         /*!<New Data flag of Rx Buffer 47             */

+#define FDCAN_NDAT2_ND48_Pos      (16U)

+#define FDCAN_NDAT2_ND48_Msk      (0x1UL << FDCAN_NDAT2_ND48_Pos)              /*!< 0x00010000 */

+#define FDCAN_NDAT2_ND48          FDCAN_NDAT2_ND48_Msk                         /*!<New Data flag of Rx Buffer 48             */

+#define FDCAN_NDAT2_ND49_Pos      (17U)

+#define FDCAN_NDAT2_ND49_Msk      (0x1UL << FDCAN_NDAT2_ND49_Pos)              /*!< 0x00020000 */

+#define FDCAN_NDAT2_ND49          FDCAN_NDAT2_ND49_Msk                         /*!<New Data flag of Rx Buffer 49             */

+#define FDCAN_NDAT2_ND50_Pos      (18U)

+#define FDCAN_NDAT2_ND50_Msk      (0x1UL << FDCAN_NDAT2_ND50_Pos)              /*!< 0x00040000 */

+#define FDCAN_NDAT2_ND50          FDCAN_NDAT2_ND50_Msk                         /*!<New Data flag of Rx Buffer 50             */

+#define FDCAN_NDAT2_ND51_Pos      (19U)

+#define FDCAN_NDAT2_ND51_Msk      (0x1UL << FDCAN_NDAT2_ND51_Pos)              /*!< 0x00080000 */

+#define FDCAN_NDAT2_ND51          FDCAN_NDAT2_ND51_Msk                         /*!<New Data flag of Rx Buffer 51             */

+#define FDCAN_NDAT2_ND52_Pos      (20U)

+#define FDCAN_NDAT2_ND52_Msk      (0x1UL << FDCAN_NDAT2_ND52_Pos)              /*!< 0x00100000 */

+#define FDCAN_NDAT2_ND52          FDCAN_NDAT2_ND52_Msk                         /*!<New Data flag of Rx Buffer 52             */

+#define FDCAN_NDAT2_ND53_Pos      (21U)

+#define FDCAN_NDAT2_ND53_Msk      (0x1UL << FDCAN_NDAT2_ND53_Pos)              /*!< 0x00200000 */

+#define FDCAN_NDAT2_ND53          FDCAN_NDAT2_ND53_Msk                         /*!<New Data flag of Rx Buffer 53             */

+#define FDCAN_NDAT2_ND54_Pos      (22U)

+#define FDCAN_NDAT2_ND54_Msk      (0x1UL << FDCAN_NDAT2_ND54_Pos)              /*!< 0x00400000 */

+#define FDCAN_NDAT2_ND54          FDCAN_NDAT2_ND54_Msk                         /*!<New Data flag of Rx Buffer 54             */

+#define FDCAN_NDAT2_ND55_Pos      (23U)

+#define FDCAN_NDAT2_ND55_Msk      (0x1UL << FDCAN_NDAT2_ND55_Pos)              /*!< 0x00800000 */

+#define FDCAN_NDAT2_ND55          FDCAN_NDAT2_ND55_Msk                         /*!<New Data flag of Rx Buffer 55             */

+#define FDCAN_NDAT2_ND56_Pos      (24U)

+#define FDCAN_NDAT2_ND56_Msk      (0x1UL << FDCAN_NDAT2_ND56_Pos)              /*!< 0x01000000 */

+#define FDCAN_NDAT2_ND56          FDCAN_NDAT2_ND56_Msk                         /*!<New Data flag of Rx Buffer 56             */

+#define FDCAN_NDAT2_ND57_Pos      (25U)

+#define FDCAN_NDAT2_ND57_Msk      (0x1UL << FDCAN_NDAT2_ND57_Pos)              /*!< 0x02000000 */

+#define FDCAN_NDAT2_ND57          FDCAN_NDAT2_ND57_Msk                         /*!<New Data flag of Rx Buffer 57             */

+#define FDCAN_NDAT2_ND58_Pos      (26U)

+#define FDCAN_NDAT2_ND58_Msk      (0x1UL << FDCAN_NDAT2_ND58_Pos)              /*!< 0x04000000 */

+#define FDCAN_NDAT2_ND58          FDCAN_NDAT2_ND58_Msk                         /*!<New Data flag of Rx Buffer 58             */

+#define FDCAN_NDAT2_ND59_Pos      (27U)

+#define FDCAN_NDAT2_ND59_Msk      (0x1UL << FDCAN_NDAT2_ND59_Pos)              /*!< 0x08000000 */

+#define FDCAN_NDAT2_ND59          FDCAN_NDAT2_ND59_Msk                         /*!<New Data flag of Rx Buffer 59             */

+#define FDCAN_NDAT2_ND60_Pos      (28U)

+#define FDCAN_NDAT2_ND60_Msk      (0x1UL << FDCAN_NDAT2_ND60_Pos)              /*!< 0x10000000 */

+#define FDCAN_NDAT2_ND60          FDCAN_NDAT2_ND60_Msk                         /*!<New Data flag of Rx Buffer 60             */

+#define FDCAN_NDAT2_ND61_Pos      (29U)

+#define FDCAN_NDAT2_ND61_Msk      (0x1UL << FDCAN_NDAT2_ND61_Pos)              /*!< 0x20000000 */

+#define FDCAN_NDAT2_ND61          FDCAN_NDAT2_ND61_Msk                         /*!<New Data flag of Rx Buffer 61             */

+#define FDCAN_NDAT2_ND62_Pos      (30U)

+#define FDCAN_NDAT2_ND62_Msk      (0x1UL << FDCAN_NDAT2_ND62_Pos)              /*!< 0x40000000 */

+#define FDCAN_NDAT2_ND62          FDCAN_NDAT2_ND62_Msk                         /*!<New Data flag of Rx Buffer 62             */

+#define FDCAN_NDAT2_ND63_Pos      (31U)

+#define FDCAN_NDAT2_ND63_Msk      (0x1UL << FDCAN_NDAT2_ND63_Pos)              /*!< 0x80000000 */

+#define FDCAN_NDAT2_ND63          FDCAN_NDAT2_ND63_Msk                         /*!<New Data flag of Rx Buffer 63             */

+

+/*****************  Bit definition for FDCAN_RXF0C register  ********************/

+#define FDCAN_RXF0C_F0SA_Pos      (2U)

+#define FDCAN_RXF0C_F0SA_Msk      (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_RXF0C_F0SA          FDCAN_RXF0C_F0SA_Msk                         /*!<Rx FIFO 0 Start Address                   */

+#define FDCAN_RXF0C_F0S_Pos       (16U)

+#define FDCAN_RXF0C_F0S_Msk       (0x7FUL << FDCAN_RXF0C_F0S_Pos)              /*!< 0x007F0000 */

+#define FDCAN_RXF0C_F0S           FDCAN_RXF0C_F0S_Msk                          /*!<Number of Rx FIFO 0 elements              */

+#define FDCAN_RXF0C_F0WM_Pos      (24U)

+#define FDCAN_RXF0C_F0WM_Msk      (0x7FUL << FDCAN_RXF0C_F0WM_Pos)             /*!< 0x7F000000 */

+#define FDCAN_RXF0C_F0WM          FDCAN_RXF0C_F0WM_Msk                         /*!<FIFO 0 Watermark                          */

+#define FDCAN_RXF0C_F0OM_Pos      (31U)

+#define FDCAN_RXF0C_F0OM_Msk      (0x1UL << FDCAN_RXF0C_F0OM_Pos)              /*!< 0x80000000 */

+#define FDCAN_RXF0C_F0OM          FDCAN_RXF0C_F0OM_Msk                         /*!<FIFO 0 Operation Mode                     */

+

+/*****************  Bit definition for FDCAN_RXF0S register  ********************/

+#define FDCAN_RXF0S_F0FL_Pos      (0U)

+#define FDCAN_RXF0S_F0FL_Msk      (0x7FUL << FDCAN_RXF0S_F0FL_Pos)             /*!< 0x0000007F */

+#define FDCAN_RXF0S_F0FL          FDCAN_RXF0S_F0FL_Msk                         /*!<Rx FIFO 0 Fill Level                      */

+#define FDCAN_RXF0S_F0GI_Pos      (8U)

+#define FDCAN_RXF0S_F0GI_Msk      (0x3FUL << FDCAN_RXF0S_F0GI_Pos)             /*!< 0x00003F00 */

+#define FDCAN_RXF0S_F0GI          FDCAN_RXF0S_F0GI_Msk                         /*!<Rx FIFO 0 Get Index                       */

+#define FDCAN_RXF0S_F0PI_Pos      (16U)

+#define FDCAN_RXF0S_F0PI_Msk      (0x3FUL << FDCAN_RXF0S_F0PI_Pos)             /*!< 0x003F0000 */

+#define FDCAN_RXF0S_F0PI          FDCAN_RXF0S_F0PI_Msk                         /*!<Rx FIFO 0 Put Index                       */

+#define FDCAN_RXF0S_F0F_Pos       (24U)

+#define FDCAN_RXF0S_F0F_Msk       (0x1UL << FDCAN_RXF0S_F0F_Pos)               /*!< 0x01000000 */

+#define FDCAN_RXF0S_F0F           FDCAN_RXF0S_F0F_Msk                          /*!<Rx FIFO 0 Full                            */

+#define FDCAN_RXF0S_RF0L_Pos      (25U)

+#define FDCAN_RXF0S_RF0L_Msk      (0x1UL << FDCAN_RXF0S_RF0L_Pos)              /*!< 0x02000000 */

+#define FDCAN_RXF0S_RF0L          FDCAN_RXF0S_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                    */

+

+/*****************  Bit definition for FDCAN_RXF0A register  ********************/

+#define FDCAN_RXF0A_F0AI_Pos      (0U)

+#define FDCAN_RXF0A_F0AI_Msk      (0x3FUL << FDCAN_RXF0A_F0AI_Pos)             /*!< 0x0000003F */

+#define FDCAN_RXF0A_F0AI          FDCAN_RXF0A_F0AI_Msk                         /*!<Rx FIFO 0 Acknowledge Index               */

+

+/*****************  Bit definition for FDCAN_RXBC register  ********************/

+#define FDCAN_RXBC_RBSA_Pos       (2U)

+#define FDCAN_RXBC_RBSA_Msk       (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)            /*!< 0x0000FFFC */

+#define FDCAN_RXBC_RBSA           FDCAN_RXBC_RBSA_Msk                          /*!<Rx Buffer Start Address                   */

+

+/*****************  Bit definition for FDCAN_RXF1C register  ********************/

+#define FDCAN_RXF1C_F1SA_Pos      (2U)

+#define FDCAN_RXF1C_F1SA_Msk      (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_RXF1C_F1SA          FDCAN_RXF1C_F1SA_Msk                         /*!<Rx FIFO 1 Start Address                   */

+#define FDCAN_RXF1C_F1S_Pos       (16U)

+#define FDCAN_RXF1C_F1S_Msk       (0x7FUL << FDCAN_RXF1C_F1S_Pos)              /*!< 0x007F0000 */

+#define FDCAN_RXF1C_F1S           FDCAN_RXF1C_F1S_Msk                          /*!<Number of Rx FIFO 1 elements              */

+#define FDCAN_RXF1C_F1WM_Pos      (24U)

+#define FDCAN_RXF1C_F1WM_Msk      (0x7FUL << FDCAN_RXF1C_F1WM_Pos)             /*!< 0x7F000000 */

+#define FDCAN_RXF1C_F1WM          FDCAN_RXF1C_F1WM_Msk                         /*!<Rx FIFO 1 Watermark                       */

+#define FDCAN_RXF1C_F1OM_Pos      (31U)

+#define FDCAN_RXF1C_F1OM_Msk      (0x1UL << FDCAN_RXF1C_F1OM_Pos)              /*!< 0x80000000 */

+#define FDCAN_RXF1C_F1OM          FDCAN_RXF1C_F1OM_Msk                         /*!<FIFO 1 Operation Mode                     */

+

+/*****************  Bit definition for FDCAN_RXF1S register  ********************/

+#define FDCAN_RXF1S_F1FL_Pos      (0U)

+#define FDCAN_RXF1S_F1FL_Msk      (0x7FUL << FDCAN_RXF1S_F1FL_Pos)             /*!< 0x0000007F */

+#define FDCAN_RXF1S_F1FL          FDCAN_RXF1S_F1FL_Msk                         /*!<Rx FIFO 1 Fill Level                      */

+#define FDCAN_RXF1S_F1GI_Pos      (8U)

+#define FDCAN_RXF1S_F1GI_Msk      (0x3FUL << FDCAN_RXF1S_F1GI_Pos)             /*!< 0x00003F00 */

+#define FDCAN_RXF1S_F1GI          FDCAN_RXF1S_F1GI_Msk                         /*!<Rx FIFO 1 Get Index                       */

+#define FDCAN_RXF1S_F1PI_Pos      (16U)

+#define FDCAN_RXF1S_F1PI_Msk      (0x3FUL << FDCAN_RXF1S_F1PI_Pos)             /*!< 0x003F0000 */

+#define FDCAN_RXF1S_F1PI          FDCAN_RXF1S_F1PI_Msk                         /*!<Rx FIFO 1 Put Index                       */

+#define FDCAN_RXF1S_F1F_Pos       (24U)

+#define FDCAN_RXF1S_F1F_Msk       (0x1UL << FDCAN_RXF1S_F1F_Pos)               /*!< 0x01000000 */

+#define FDCAN_RXF1S_F1F           FDCAN_RXF1S_F1F_Msk                          /*!<Rx FIFO 1 Full                            */

+#define FDCAN_RXF1S_RF1L_Pos      (25U)

+#define FDCAN_RXF1S_RF1L_Msk      (0x1UL << FDCAN_RXF1S_RF1L_Pos)              /*!< 0x02000000 */

+#define FDCAN_RXF1S_RF1L          FDCAN_RXF1S_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                    */

+

+/*****************  Bit definition for FDCAN_RXF1A register  ********************/

+#define FDCAN_RXF1A_F1AI_Pos      (0U)

+#define FDCAN_RXF1A_F1AI_Msk      (0x3FUL << FDCAN_RXF1A_F1AI_Pos)             /*!< 0x0000003F */

+#define FDCAN_RXF1A_F1AI          FDCAN_RXF1A_F1AI_Msk                         /*!<Rx FIFO 1 Acknowledge Index               */

+

+/*****************  Bit definition for FDCAN_RXESC register  ********************/

+#define FDCAN_RXESC_F0DS_Pos      (0U)

+#define FDCAN_RXESC_F0DS_Msk      (0x7UL << FDCAN_RXESC_F0DS_Pos)              /*!< 0x00000007 */

+#define FDCAN_RXESC_F0DS          FDCAN_RXESC_F0DS_Msk                         /*!<Rx FIFO 1 Data Field Size                 */

+#define FDCAN_RXESC_F1DS_Pos      (4U)

+#define FDCAN_RXESC_F1DS_Msk      (0x7UL << FDCAN_RXESC_F1DS_Pos)              /*!< 0x00000070 */

+#define FDCAN_RXESC_F1DS          FDCAN_RXESC_F1DS_Msk                         /*!<Rx FIFO 0 Data Field Size                 */

+#define FDCAN_RXESC_RBDS_Pos      (8U)

+#define FDCAN_RXESC_RBDS_Msk      (0x7UL << FDCAN_RXESC_RBDS_Pos)              /*!< 0x00000700 */

+#define FDCAN_RXESC_RBDS          FDCAN_RXESC_RBDS_Msk                         /*!<Rx Buffer Data Field Size                 */

+

+/*****************  Bit definition for FDCAN_TXBC register  *********************/

+#define FDCAN_TXBC_TBSA_Pos       (2U)

+#define FDCAN_TXBC_TBSA_Msk       (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)            /*!< 0x0000FFFC */

+#define FDCAN_TXBC_TBSA           FDCAN_TXBC_TBSA_Msk                          /*!<Tx Buffers Start Address                  */

+#define FDCAN_TXBC_NDTB_Pos       (16U)

+#define FDCAN_TXBC_NDTB_Msk       (0x3FUL << FDCAN_TXBC_NDTB_Pos)              /*!< 0x003F0000 */

+#define FDCAN_TXBC_NDTB           FDCAN_TXBC_NDTB_Msk                          /*!<Number of Dedicated Transmit Buffers      */

+#define FDCAN_TXBC_TFQS_Pos       (24U)

+#define FDCAN_TXBC_TFQS_Msk       (0x3FUL << FDCAN_TXBC_TFQS_Pos)              /*!< 0x3F000000 */

+#define FDCAN_TXBC_TFQS           FDCAN_TXBC_TFQS_Msk                          /*!<Transmit FIFO/Queue Size                  */

+#define FDCAN_TXBC_TFQM_Pos       (30U)

+#define FDCAN_TXBC_TFQM_Msk       (0x1UL << FDCAN_TXBC_TFQM_Pos)               /*!< 0x40000000 */

+#define FDCAN_TXBC_TFQM           FDCAN_TXBC_TFQM_Msk                          /*!<Tx FIFO/Queue Mode                        */

+

+/*****************  Bit definition for FDCAN_TXFQS register  *********************/

+#define FDCAN_TXFQS_TFFL_Pos      (0U)

+#define FDCAN_TXFQS_TFFL_Msk      (0x3FUL << FDCAN_TXFQS_TFFL_Pos)             /*!< 0x0000003F */

+#define FDCAN_TXFQS_TFFL          FDCAN_TXFQS_TFFL_Msk                         /*!<Tx FIFO Free Level                        */

+#define FDCAN_TXFQS_TFGI_Pos      (8U)

+#define FDCAN_TXFQS_TFGI_Msk      (0x1FUL << FDCAN_TXFQS_TFGI_Pos)             /*!< 0x00001F00 */

+#define FDCAN_TXFQS_TFGI          FDCAN_TXFQS_TFGI_Msk                         /*!<Tx FIFO Get Index                         */

+#define FDCAN_TXFQS_TFQPI_Pos     (16U)

+#define FDCAN_TXFQS_TFQPI_Msk     (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)            /*!< 0x001F0000 */

+#define FDCAN_TXFQS_TFQPI         FDCAN_TXFQS_TFQPI_Msk                        /*!<Tx FIFO/Queue Put Index                   */

+#define FDCAN_TXFQS_TFQF_Pos      (21U)

+#define FDCAN_TXFQS_TFQF_Msk      (0x1UL << FDCAN_TXFQS_TFQF_Pos)              /*!< 0x00200000 */

+#define FDCAN_TXFQS_TFQF          FDCAN_TXFQS_TFQF_Msk                         /*!<Tx FIFO/Queue Full                        */

+

+/*****************  Bit definition for FDCAN_TXESC register  *********************/

+#define FDCAN_TXESC_TBDS_Pos      (0U)

+#define FDCAN_TXESC_TBDS_Msk      (0x7UL << FDCAN_TXESC_TBDS_Pos)              /*!< 0x00000007 */

+#define FDCAN_TXESC_TBDS          FDCAN_TXESC_TBDS_Msk                         /*!<Tx Buffer Data Field Size                 */

+

+/*****************  Bit definition for FDCAN_TXBRP register  *********************/

+#define FDCAN_TXBRP_TRP_Pos       (0U)

+#define FDCAN_TXBRP_TRP_Msk       (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)        /*!< 0xFFFFFFFF */

+#define FDCAN_TXBRP_TRP           FDCAN_TXBRP_TRP_Msk                          /*!<Transmission Request Pending              */

+

+/*****************  Bit definition for FDCAN_TXBAR register  *********************/

+#define FDCAN_TXBAR_AR_Pos        (0U)

+#define FDCAN_TXBAR_AR_Msk        (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBAR_AR            FDCAN_TXBAR_AR_Msk                           /*!<Add Request                               */

+

+/*****************  Bit definition for FDCAN_TXBCR register  *********************/

+#define FDCAN_TXBCR_CR_Pos        (0U)

+#define FDCAN_TXBCR_CR_Msk        (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCR_CR            FDCAN_TXBCR_CR_Msk                           /*!<Cancellation Request                      */

+

+/*****************  Bit definition for FDCAN_TXBTO register  *********************/

+#define FDCAN_TXBTO_TO_Pos        (0U)

+#define FDCAN_TXBTO_TO_Msk        (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBTO_TO            FDCAN_TXBTO_TO_Msk                           /*!<Transmission Occurred                     */

+

+/*****************  Bit definition for FDCAN_TXBCF register  *********************/

+#define FDCAN_TXBCF_CF_Pos        (0U)

+#define FDCAN_TXBCF_CF_Msk        (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCF_CF            FDCAN_TXBCF_CF_Msk                           /*!<Cancellation Finished                     */

+

+/*****************  Bit definition for FDCAN_TXBTIE register  ********************/

+#define FDCAN_TXBTIE_TIE_Pos      (0U)

+#define FDCAN_TXBTIE_TIE_Msk      (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)       /*!< 0xFFFFFFFF */

+#define FDCAN_TXBTIE_TIE          FDCAN_TXBTIE_TIE_Msk                         /*!<Transmission Interrupt Enable             */

+

+/*****************  Bit definition for FDCAN_ TXBCIE register  *******************/

+#define FDCAN_TXBCIE_CFIE_Pos     (0U)

+#define FDCAN_TXBCIE_CFIE_Msk     (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)      /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCIE_CFIE         FDCAN_TXBCIE_CFIE_Msk                        /*!<Cancellation Finished Interrupt Enable    */

+

+/*****************  Bit definition for FDCAN_TXEFC register  *********************/

+#define FDCAN_TXEFC_EFSA_Pos      (2U)

+#define FDCAN_TXEFC_EFSA_Msk      (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_TXEFC_EFSA          FDCAN_TXEFC_EFSA_Msk                         /*!<Event FIFO Start Address                  */

+#define FDCAN_TXEFC_EFS_Pos       (16U)

+#define FDCAN_TXEFC_EFS_Msk       (0x3FUL << FDCAN_TXEFC_EFS_Pos)              /*!< 0x003F0000 */

+#define FDCAN_TXEFC_EFS           FDCAN_TXEFC_EFS_Msk                          /*!<Event FIFO Size                           */

+#define FDCAN_TXEFC_EFWM_Pos      (24U)

+#define FDCAN_TXEFC_EFWM_Msk      (0x3FUL << FDCAN_TXEFC_EFWM_Pos)             /*!< 0x3F000000 */

+#define FDCAN_TXEFC_EFWM          FDCAN_TXEFC_EFWM_Msk                         /*!<Event FIFO Watermark                      */

+

+/*****************  Bit definition for FDCAN_TXEFS register  *********************/

+#define FDCAN_TXEFS_EFFL_Pos      (0U)

+#define FDCAN_TXEFS_EFFL_Msk      (0x3FUL << FDCAN_TXEFS_EFFL_Pos)             /*!< 0x0000003F */

+#define FDCAN_TXEFS_EFFL          FDCAN_TXEFS_EFFL_Msk                         /*!<Event FIFO Fill Level                     */

+#define FDCAN_TXEFS_EFGI_Pos      (8U)

+#define FDCAN_TXEFS_EFGI_Msk      (0x1FUL << FDCAN_TXEFS_EFGI_Pos)             /*!< 0x00001F00 */

+#define FDCAN_TXEFS_EFGI          FDCAN_TXEFS_EFGI_Msk                         /*!<Event FIFO Get Index                      */

+#define FDCAN_TXEFS_EFPI_Pos      (16U)

+#define FDCAN_TXEFS_EFPI_Msk      (0x1FUL << FDCAN_TXEFS_EFPI_Pos)             /*!< 0x001F0000 */

+#define FDCAN_TXEFS_EFPI          FDCAN_TXEFS_EFPI_Msk                         /*!<Event FIFO Put Index                      */

+#define FDCAN_TXEFS_EFF_Pos       (24U)

+#define FDCAN_TXEFS_EFF_Msk       (0x1UL << FDCAN_TXEFS_EFF_Pos)               /*!< 0x01000000 */

+#define FDCAN_TXEFS_EFF           FDCAN_TXEFS_EFF_Msk                          /*!<Event FIFO Full                           */

+#define FDCAN_TXEFS_TEFL_Pos      (25U)

+#define FDCAN_TXEFS_TEFL_Msk      (0x1UL << FDCAN_TXEFS_TEFL_Pos)              /*!< 0x02000000 */

+#define FDCAN_TXEFS_TEFL          FDCAN_TXEFS_TEFL_Msk                         /*!<Tx Event FIFO Element Lost                */

+

+/*****************  Bit definition for FDCAN_TXEFA register  *********************/

+#define FDCAN_TXEFA_EFAI_Pos      (0U)

+#define FDCAN_TXEFA_EFAI_Msk      (0x1FUL << FDCAN_TXEFA_EFAI_Pos)             /*!< 0x0000001F */

+#define FDCAN_TXEFA_EFAI          FDCAN_TXEFA_EFAI_Msk                         /*!<Event FIFO Acknowledge Index              */

+

+/*****************  Bit definition for FDCAN_TTTMC register  *********************/

+#define FDCAN_TTTMC_TMSA_Pos      (2U)

+#define FDCAN_TTTMC_TMSA_Msk      (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_TTTMC_TMSA          FDCAN_TTTMC_TMSA_Msk                         /*!<Trigger Memory Start Address              */

+#define FDCAN_TTTMC_TME_Pos       (16U)

+#define FDCAN_TTTMC_TME_Msk       (0x7FUL << FDCAN_TTTMC_TME_Pos)              /*!< 0x007F0000 */

+#define FDCAN_TTTMC_TME           FDCAN_TTTMC_TME_Msk                          /*!<Trigger Memory Elements                   */

+

+/*****************  Bit definition for FDCAN_TTRMC register  *********************/

+#define FDCAN_TTRMC_RID_Pos       (0U)

+#define FDCAN_TTRMC_RID_Msk       (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)        /*!< 0x1FFFFFFF */

+#define FDCAN_TTRMC_RID           FDCAN_TTRMC_RID_Msk                          /*!<Reference Identifier                      */

+#define FDCAN_TTRMC_XTD_Pos       (30U)

+#define FDCAN_TTRMC_XTD_Msk       (0x1UL << FDCAN_TTRMC_XTD_Pos)               /*!< 0x40000000 */

+#define FDCAN_TTRMC_XTD           FDCAN_TTRMC_XTD_Msk                          /*!< Extended Identifier                      */

+#define FDCAN_TTRMC_RMPS_Pos      (31U)

+#define FDCAN_TTRMC_RMPS_Msk      (0x1UL << FDCAN_TTRMC_RMPS_Pos)              /*!< 0x80000000 */

+#define FDCAN_TTRMC_RMPS          FDCAN_TTRMC_RMPS_Msk                         /*!<Reference Message Payload Select          */

+

+/*****************  Bit definition for FDCAN_TTOCF register  *********************/

+#define FDCAN_TTOCF_OM_Pos        (0U)

+#define FDCAN_TTOCF_OM_Msk        (0x3UL << FDCAN_TTOCF_OM_Pos)                /*!< 0x00000003 */

+#define FDCAN_TTOCF_OM            FDCAN_TTOCF_OM_Msk                           /*!<Operation Mode                            */

+#define FDCAN_TTOCF_GEN_Pos       (3U)

+#define FDCAN_TTOCF_GEN_Msk       (0x1UL << FDCAN_TTOCF_GEN_Pos)               /*!< 0x00000008 */

+#define FDCAN_TTOCF_GEN           FDCAN_TTOCF_GEN_Msk                          /*!<Gap Enable                                */

+#define FDCAN_TTOCF_TM_Pos        (4U)

+#define FDCAN_TTOCF_TM_Msk        (0x1UL << FDCAN_TTOCF_TM_Pos)                /*!< 0x00000010 */

+#define FDCAN_TTOCF_TM            FDCAN_TTOCF_TM_Msk                           /*!<Time Master                               */

+#define FDCAN_TTOCF_LDSDL_Pos     (5U)

+#define FDCAN_TTOCF_LDSDL_Msk     (0x7UL << FDCAN_TTOCF_LDSDL_Pos)             /*!< 0x000000E0 */

+#define FDCAN_TTOCF_LDSDL         FDCAN_TTOCF_LDSDL_Msk                        /*!<LD of Synchronization Deviation Limit     */

+#define FDCAN_TTOCF_IRTO_Pos      (8U)

+#define FDCAN_TTOCF_IRTO_Msk      (0x7FUL << FDCAN_TTOCF_IRTO_Pos)             /*!< 0x00007F00 */

+#define FDCAN_TTOCF_IRTO          FDCAN_TTOCF_IRTO_Msk                         /*!<Initial Reference Trigger Offset          */

+#define FDCAN_TTOCF_EECS_Pos      (15U)

+#define FDCAN_TTOCF_EECS_Msk      (0x1UL << FDCAN_TTOCF_EECS_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTOCF_EECS          FDCAN_TTOCF_EECS_Msk                         /*!<Enable External Clock Synchronization     */

+#define FDCAN_TTOCF_AWL_Pos       (16U)

+#define FDCAN_TTOCF_AWL_Msk       (0xFFUL << FDCAN_TTOCF_AWL_Pos)              /*!< 0x00FF0000 */

+#define FDCAN_TTOCF_AWL           FDCAN_TTOCF_AWL_Msk                          /*!<Application Watchdog Limit                */

+#define FDCAN_TTOCF_EGTF_Pos      (24U)

+#define FDCAN_TTOCF_EGTF_Msk      (0x1UL << FDCAN_TTOCF_EGTF_Pos)              /*!< 0x01000000 */

+#define FDCAN_TTOCF_EGTF          FDCAN_TTOCF_EGTF_Msk                         /*!<Enable Global Time Filtering              */

+#define FDCAN_TTOCF_ECC_Pos       (25U)

+#define FDCAN_TTOCF_ECC_Msk       (0x1UL << FDCAN_TTOCF_ECC_Pos)               /*!< 0x02000000 */

+#define FDCAN_TTOCF_ECC           FDCAN_TTOCF_ECC_Msk                          /*!<Enable Clock Calibration                  */

+#define FDCAN_TTOCF_EVTP_Pos      (26U)

+#define FDCAN_TTOCF_EVTP_Msk      (0x1UL << FDCAN_TTOCF_EVTP_Pos)              /*!< 0x04000000 */

+#define FDCAN_TTOCF_EVTP          FDCAN_TTOCF_EVTP_Msk                         /*!<Event Trigger Polarity                    */

+

+/*****************  Bit definition for FDCAN_TTMLM register  *********************/

+#define FDCAN_TTMLM_CCM_Pos       (0U)

+#define FDCAN_TTMLM_CCM_Msk       (0x3FUL << FDCAN_TTMLM_CCM_Pos)              /*!< 0x0000003F */

+#define FDCAN_TTMLM_CCM           FDCAN_TTMLM_CCM_Msk                          /*!<Cycle Count Max                           */

+#define FDCAN_TTMLM_CSS_Pos       (6U)

+#define FDCAN_TTMLM_CSS_Msk       (0x3UL << FDCAN_TTMLM_CSS_Pos)               /*!< 0x000000C0 */

+#define FDCAN_TTMLM_CSS           FDCAN_TTMLM_CSS_Msk                          /*!<Cycle Start Synchronization               */

+#define FDCAN_TTMLM_TXEW_Pos      (8U)

+#define FDCAN_TTMLM_TXEW_Msk      (0xFUL << FDCAN_TTMLM_TXEW_Pos)              /*!< 0x00000F00 */

+#define FDCAN_TTMLM_TXEW          FDCAN_TTMLM_TXEW_Msk                         /*!<Tx Enable Window                          */

+#define FDCAN_TTMLM_ENTT_Pos      (16U)

+#define FDCAN_TTMLM_ENTT_Msk      (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)            /*!< 0x0FFF0000 */

+#define FDCAN_TTMLM_ENTT          FDCAN_TTMLM_ENTT_Msk                         /*!<Expected Number of Tx Triggers            */

+

+/*****************  Bit definition for FDCAN_TURCF register  *********************/

+#define FDCAN_TURCF_NCL_Pos       (0U)

+#define FDCAN_TURCF_NCL_Msk       (0xFFFFUL << FDCAN_TURCF_NCL_Pos)            /*!< 0x0000FFFF */

+#define FDCAN_TURCF_NCL           FDCAN_TURCF_NCL_Msk                          /*!<Numerator Configuration Low               */

+#define FDCAN_TURCF_DC_Pos        (16U)

+#define FDCAN_TURCF_DC_Msk        (0x3FFFUL << FDCAN_TURCF_DC_Pos)             /*!< 0x3FFF0000 */

+#define FDCAN_TURCF_DC            FDCAN_TURCF_DC_Msk                           /*!<Denominator Configuration                 */

+#define FDCAN_TURCF_ELT_Pos       (31U)

+#define FDCAN_TURCF_ELT_Msk       (0x1UL << FDCAN_TURCF_ELT_Pos)               /*!< 0x80000000 */

+#define FDCAN_TURCF_ELT           FDCAN_TURCF_ELT_Msk                          /*!<Enable Local Time                         */

+

+/*****************  Bit definition for FDCAN_TTOCN register  ********************/

+#define FDCAN_TTOCN_SGT_Pos       (0U)

+#define FDCAN_TTOCN_SGT_Msk       (0x1UL << FDCAN_TTOCN_SGT_Pos)               /*!< 0x00000001 */

+#define FDCAN_TTOCN_SGT           FDCAN_TTOCN_SGT_Msk                          /*!<Set Global time                           */

+#define FDCAN_TTOCN_ECS_Pos       (1U)

+#define FDCAN_TTOCN_ECS_Msk       (0x1UL << FDCAN_TTOCN_ECS_Pos)               /*!< 0x00000002 */

+#define FDCAN_TTOCN_ECS           FDCAN_TTOCN_ECS_Msk                          /*!<External Clock Synchronization            */

+#define FDCAN_TTOCN_SWP_Pos       (2U)

+#define FDCAN_TTOCN_SWP_Msk       (0x1UL << FDCAN_TTOCN_SWP_Pos)               /*!< 0x00000004 */

+#define FDCAN_TTOCN_SWP           FDCAN_TTOCN_SWP_Msk                          /*!<Stop Watch Polarity                       */

+#define FDCAN_TTOCN_SWS_Pos       (3U)

+#define FDCAN_TTOCN_SWS_Msk       (0x3UL << FDCAN_TTOCN_SWS_Pos)               /*!< 0x00000018 */

+#define FDCAN_TTOCN_SWS           FDCAN_TTOCN_SWS_Msk                          /*!<Stop Watch Source                         */

+#define FDCAN_TTOCN_RTIE_Pos      (5U)

+#define FDCAN_TTOCN_RTIE_Msk      (0x1UL << FDCAN_TTOCN_RTIE_Pos)              /*!< 0x00000020 */

+#define FDCAN_TTOCN_RTIE          FDCAN_TTOCN_RTIE_Msk                         /*!<Register Time Mark Interrupt Pulse Enable */

+#define FDCAN_TTOCN_TMC_Pos       (6U)

+#define FDCAN_TTOCN_TMC_Msk       (0x3UL << FDCAN_TTOCN_TMC_Pos)               /*!< 0x000000C0 */

+#define FDCAN_TTOCN_TMC           FDCAN_TTOCN_TMC_Msk                          /*!<Register Time Mark Compare                */

+#define FDCAN_TTOCN_TTIE_Pos      (8U)

+#define FDCAN_TTOCN_TTIE_Msk      (0x1UL << FDCAN_TTOCN_TTIE_Pos)              /*!< 0x00000100 */

+#define FDCAN_TTOCN_TTIE          FDCAN_TTOCN_TTIE_Msk                         /*!<Trigger Time Mark Interrupt Pulse Enable  */

+#define FDCAN_TTOCN_GCS_Pos       (9U)

+#define FDCAN_TTOCN_GCS_Msk       (0x1UL << FDCAN_TTOCN_GCS_Pos)               /*!< 0x00000200 */

+#define FDCAN_TTOCN_GCS           FDCAN_TTOCN_GCS_Msk                          /*!<Gap Control Select                        */

+#define FDCAN_TTOCN_FGP_Pos       (10U)

+#define FDCAN_TTOCN_FGP_Msk       (0x1UL << FDCAN_TTOCN_FGP_Pos)               /*!< 0x00000400 */

+#define FDCAN_TTOCN_FGP           FDCAN_TTOCN_FGP_Msk                          /*!<Finish Gap                                */

+#define FDCAN_TTOCN_TMG_Pos       (11U)

+#define FDCAN_TTOCN_TMG_Msk       (0x1UL << FDCAN_TTOCN_TMG_Pos)               /*!< 0x00000800 */

+#define FDCAN_TTOCN_TMG           FDCAN_TTOCN_TMG_Msk                          /*!<Time Mark Gap                             */

+#define FDCAN_TTOCN_NIG_Pos       (12U)

+#define FDCAN_TTOCN_NIG_Msk       (0x1UL << FDCAN_TTOCN_NIG_Pos)               /*!< 0x00001000 */

+#define FDCAN_TTOCN_NIG           FDCAN_TTOCN_NIG_Msk                          /*!<Next is Gap                               */

+#define FDCAN_TTOCN_ESCN_Pos      (13U)

+#define FDCAN_TTOCN_ESCN_Msk      (0x1UL << FDCAN_TTOCN_ESCN_Pos)              /*!< 0x00002000 */

+#define FDCAN_TTOCN_ESCN          FDCAN_TTOCN_ESCN_Msk                         /*!<External Synchronization Control          */

+#define FDCAN_TTOCN_LCKC_Pos      (15U)

+#define FDCAN_TTOCN_LCKC_Msk      (0x1UL << FDCAN_TTOCN_LCKC_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTOCN_LCKC          FDCAN_TTOCN_LCKC_Msk                         /*!<TT Operation Control Register Locked      */

+

+/*****************  Bit definition for FDCAN_TTGTP register  ********************/

+#define FDCAN_TTGTP_TP_Pos        (0U)

+#define FDCAN_TTGTP_TP_Msk        (0xFFFFUL << FDCAN_TTGTP_TP_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTGTP_TP            FDCAN_TTGTP_TP_Msk                           /*!<Time Preset                               */

+#define FDCAN_TTGTP_CTP_Pos       (16U)

+#define FDCAN_TTGTP_CTP_Msk       (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)            /*!< 0xFFFF0000 */

+#define FDCAN_TTGTP_CTP           FDCAN_TTGTP_CTP_Msk                          /*!<Cycle Time Target Phase                   */

+

+/*****************  Bit definition for FDCAN_TTTMK register  ********************/

+#define FDCAN_TTTMK_TM_Pos        (0U)

+#define FDCAN_TTTMK_TM_Msk        (0xFFFFUL << FDCAN_TTTMK_TM_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTTMK_TM            FDCAN_TTTMK_TM_Msk                           /*!<Time Mark                                 */

+#define FDCAN_TTTMK_TICC_Pos      (16U)

+#define FDCAN_TTTMK_TICC_Msk      (0x7FUL << FDCAN_TTTMK_TICC_Pos)             /*!< 0x007F0000 */

+#define FDCAN_TTTMK_TICC          FDCAN_TTTMK_TICC_Msk                         /*!<Time Mark Cycle Code                      */

+#define FDCAN_TTTMK_LCKM_Pos      (31U)

+#define FDCAN_TTTMK_LCKM_Msk      (0x1UL << FDCAN_TTTMK_LCKM_Pos)              /*!< 0x80000000 */

+#define FDCAN_TTTMK_LCKM          FDCAN_TTTMK_LCKM_Msk                         /*!<TT Time Mark Register Locked              */

+

+/*****************  Bit definition for FDCAN_TTIR register  ********************/

+#define FDCAN_TTIR_SBC_Pos        (0U)

+#define FDCAN_TTIR_SBC_Msk        (0x1UL << FDCAN_TTIR_SBC_Pos)                /*!< 0x00000001 */

+#define FDCAN_TTIR_SBC            FDCAN_TTIR_SBC_Msk                           /*!<Start of Basic Cycle                      */

+#define FDCAN_TTIR_SMC_Pos        (1U)

+#define FDCAN_TTIR_SMC_Msk        (0x1UL << FDCAN_TTIR_SMC_Pos)                /*!< 0x00000002 */

+#define FDCAN_TTIR_SMC            FDCAN_TTIR_SMC_Msk                           /*!<Start of Matrix Cycle                     */

+#define FDCAN_TTIR_CSM_Pos        (2U)

+#define FDCAN_TTIR_CSM_Msk        (0x1UL << FDCAN_TTIR_CSM_Pos)                /*!< 0x00000004 */

+#define FDCAN_TTIR_CSM            FDCAN_TTIR_CSM_Msk                           /*!<Change of Synchronization Mode            */

+#define FDCAN_TTIR_SOG_Pos        (3U)

+#define FDCAN_TTIR_SOG_Msk        (0x1UL << FDCAN_TTIR_SOG_Pos)                /*!< 0x00000008 */

+#define FDCAN_TTIR_SOG            FDCAN_TTIR_SOG_Msk                           /*!<Start of Gap                              */

+#define FDCAN_TTIR_RTMI_Pos       (4U)

+#define FDCAN_TTIR_RTMI_Msk       (0x1UL << FDCAN_TTIR_RTMI_Pos)               /*!< 0x00000010 */

+#define FDCAN_TTIR_RTMI           FDCAN_TTIR_RTMI_Msk                          /*!<Register Time Mark Interrupt              */

+#define FDCAN_TTIR_TTMI_Pos       (5U)

+#define FDCAN_TTIR_TTMI_Msk       (0x1UL << FDCAN_TTIR_TTMI_Pos)               /*!< 0x00000020 */

+#define FDCAN_TTIR_TTMI           FDCAN_TTIR_TTMI_Msk                          /*!<Trigger Time Mark Event Internal          */

+#define FDCAN_TTIR_SWE_Pos        (6U)

+#define FDCAN_TTIR_SWE_Msk        (0x1UL << FDCAN_TTIR_SWE_Pos)                /*!< 0x00000040 */

+#define FDCAN_TTIR_SWE            FDCAN_TTIR_SWE_Msk                           /*!<Stop Watch Event                          */

+#define FDCAN_TTIR_GTW_Pos        (7U)

+#define FDCAN_TTIR_GTW_Msk        (0x1UL << FDCAN_TTIR_GTW_Pos)                /*!< 0x00000080 */

+#define FDCAN_TTIR_GTW            FDCAN_TTIR_GTW_Msk                           /*!<Global Time Wrap                          */

+#define FDCAN_TTIR_GTD_Pos        (8U)

+#define FDCAN_TTIR_GTD_Msk        (0x1UL << FDCAN_TTIR_GTD_Pos)                /*!< 0x00000100 */

+#define FDCAN_TTIR_GTD            FDCAN_TTIR_GTD_Msk                           /*!<Global Time Discontinuity                 */

+#define FDCAN_TTIR_GTE_Pos        (9U)

+#define FDCAN_TTIR_GTE_Msk        (0x1UL << FDCAN_TTIR_GTE_Pos)                /*!< 0x00000200 */

+#define FDCAN_TTIR_GTE            FDCAN_TTIR_GTE_Msk                           /*!<Global Time Error                         */

+#define FDCAN_TTIR_TXU_Pos        (10U)

+#define FDCAN_TTIR_TXU_Msk        (0x1UL << FDCAN_TTIR_TXU_Pos)                /*!< 0x00000400 */

+#define FDCAN_TTIR_TXU            FDCAN_TTIR_TXU_Msk                           /*!<Tx Count Underflow                        */

+#define FDCAN_TTIR_TXO_Pos        (11U)

+#define FDCAN_TTIR_TXO_Msk        (0x1UL << FDCAN_TTIR_TXO_Pos)                /*!< 0x00000800 */

+#define FDCAN_TTIR_TXO            FDCAN_TTIR_TXO_Msk                           /*!<Tx Count Overflow                         */

+#define FDCAN_TTIR_SE1_Pos        (12U)

+#define FDCAN_TTIR_SE1_Msk        (0x1UL << FDCAN_TTIR_SE1_Pos)                /*!< 0x00001000 */

+#define FDCAN_TTIR_SE1            FDCAN_TTIR_SE1_Msk                           /*!<Scheduling Error 1                        */

+#define FDCAN_TTIR_SE2_Pos        (13U)

+#define FDCAN_TTIR_SE2_Msk        (0x1UL << FDCAN_TTIR_SE2_Pos)                /*!< 0x00002000 */

+#define FDCAN_TTIR_SE2            FDCAN_TTIR_SE2_Msk                           /*!<Scheduling Error 2                        */

+#define FDCAN_TTIR_ELC_Pos        (14U)

+#define FDCAN_TTIR_ELC_Msk        (0x1UL << FDCAN_TTIR_ELC_Pos)                /*!< 0x00004000 */

+#define FDCAN_TTIR_ELC            FDCAN_TTIR_ELC_Msk                           /*!<Error Level Changed                       */

+#define FDCAN_TTIR_IWT_Pos        (15U)

+#define FDCAN_TTIR_IWT_Msk        (0x1UL << FDCAN_TTIR_IWT_Pos)                /*!< 0x00008000 */

+#define FDCAN_TTIR_IWT            FDCAN_TTIR_IWT_Msk                           /*!<Initialization Watch Trigger              */

+#define FDCAN_TTIR_WT_Pos         (16U)

+#define FDCAN_TTIR_WT_Msk         (0x1UL << FDCAN_TTIR_WT_Pos)                 /*!< 0x00010000 */

+#define FDCAN_TTIR_WT             FDCAN_TTIR_WT_Msk                            /*!<Watch Trigger                             */

+#define FDCAN_TTIR_AW_Pos         (17U)

+#define FDCAN_TTIR_AW_Msk         (0x1UL << FDCAN_TTIR_AW_Pos)                 /*!< 0x00020000 */

+#define FDCAN_TTIR_AW             FDCAN_TTIR_AW_Msk                            /*!<Application Watchdog                      */

+#define FDCAN_TTIR_CER_Pos        (18U)

+#define FDCAN_TTIR_CER_Msk        (0x1UL << FDCAN_TTIR_CER_Pos)                /*!< 0x00040000 */

+#define FDCAN_TTIR_CER            FDCAN_TTIR_CER_Msk                           /*!<Configuration Error                       */

+

+/*****************  Bit definition for FDCAN_TTIE register  ********************/

+#define FDCAN_TTIE_SBCE_Pos       (0U)

+#define FDCAN_TTIE_SBCE_Msk       (0x1UL << FDCAN_TTIE_SBCE_Pos)               /*!< 0x00000001 */

+#define FDCAN_TTIE_SBCE           FDCAN_TTIE_SBCE_Msk                          /*!<Start of Basic Cycle Interrupt Enable             */

+#define FDCAN_TTIE_SMCE_Pos       (1U)

+#define FDCAN_TTIE_SMCE_Msk       (0x1UL << FDCAN_TTIE_SMCE_Pos)               /*!< 0x00000002 */

+#define FDCAN_TTIE_SMCE           FDCAN_TTIE_SMCE_Msk                          /*!<Start of Matrix Cycle Interrupt Enable            */

+#define FDCAN_TTIE_CSME_Pos       (2U)

+#define FDCAN_TTIE_CSME_Msk       (0x1UL << FDCAN_TTIE_CSME_Pos)               /*!< 0x00000004 */

+#define FDCAN_TTIE_CSME           FDCAN_TTIE_CSME_Msk                          /*!<Change of Synchronization Mode Interrupt Enable   */

+#define FDCAN_TTIE_SOGE_Pos       (3U)

+#define FDCAN_TTIE_SOGE_Msk       (0x1UL << FDCAN_TTIE_SOGE_Pos)               /*!< 0x00000008 */

+#define FDCAN_TTIE_SOGE           FDCAN_TTIE_SOGE_Msk                          /*!<Start of Gap Interrupt Enable                     */

+#define FDCAN_TTIE_RTMIE_Pos      (4U)

+#define FDCAN_TTIE_RTMIE_Msk      (0x1UL << FDCAN_TTIE_RTMIE_Pos)              /*!< 0x00000010 */

+#define FDCAN_TTIE_RTMIE          FDCAN_TTIE_RTMIE_Msk                         /*!<Register Time Mark Interrupt Interrupt Enable     */

+#define FDCAN_TTIE_TTMIE_Pos      (5U)

+#define FDCAN_TTIE_TTMIE_Msk      (0x1UL << FDCAN_TTIE_TTMIE_Pos)              /*!< 0x00000020 */

+#define FDCAN_TTIE_TTMIE          FDCAN_TTIE_TTMIE_Msk                         /*!<Trigger Time Mark Event Internal Interrupt Enable */

+#define FDCAN_TTIE_SWEE_Pos       (6U)

+#define FDCAN_TTIE_SWEE_Msk       (0x1UL << FDCAN_TTIE_SWEE_Pos)               /*!< 0x00000040 */

+#define FDCAN_TTIE_SWEE           FDCAN_TTIE_SWEE_Msk                          /*!<Stop Watch Event Interrupt Enable                 */

+#define FDCAN_TTIE_GTWE_Pos       (7U)

+#define FDCAN_TTIE_GTWE_Msk       (0x1UL << FDCAN_TTIE_GTWE_Pos)               /*!< 0x00000080 */

+#define FDCAN_TTIE_GTWE           FDCAN_TTIE_GTWE_Msk                          /*!<Global Time Wrap Interrupt Enable                 */

+#define FDCAN_TTIE_GTDE_Pos       (8U)

+#define FDCAN_TTIE_GTDE_Msk       (0x1UL << FDCAN_TTIE_GTDE_Pos)               /*!< 0x00000100 */

+#define FDCAN_TTIE_GTDE           FDCAN_TTIE_GTDE_Msk                          /*!<Global Time Discontinuity Interrupt Enable        */

+#define FDCAN_TTIE_GTEE_Pos       (9U)

+#define FDCAN_TTIE_GTEE_Msk       (0x1UL << FDCAN_TTIE_GTEE_Pos)               /*!< 0x00000200 */

+#define FDCAN_TTIE_GTEE           FDCAN_TTIE_GTEE_Msk                          /*!<Global Time Error Interrupt Enable                */

+#define FDCAN_TTIE_TXUE_Pos       (10U)

+#define FDCAN_TTIE_TXUE_Msk       (0x1UL << FDCAN_TTIE_TXUE_Pos)               /*!< 0x00000400 */

+#define FDCAN_TTIE_TXUE           FDCAN_TTIE_TXUE_Msk                          /*!<Tx Count Underflow Interrupt Enable               */

+#define FDCAN_TTIE_TXOE_Pos       (11U)

+#define FDCAN_TTIE_TXOE_Msk       (0x1UL << FDCAN_TTIE_TXOE_Pos)               /*!< 0x00000800 */

+#define FDCAN_TTIE_TXOE           FDCAN_TTIE_TXOE_Msk                          /*!<Tx Count Overflow Interrupt Enable                */

+#define FDCAN_TTIE_SE1E_Pos       (12U)

+#define FDCAN_TTIE_SE1E_Msk       (0x1UL << FDCAN_TTIE_SE1E_Pos)               /*!< 0x00001000 */

+#define FDCAN_TTIE_SE1E           FDCAN_TTIE_SE1E_Msk                          /*!<Scheduling Error 1 Interrupt Enable               */

+#define FDCAN_TTIE_SE2E_Pos       (13U)

+#define FDCAN_TTIE_SE2E_Msk       (0x1UL << FDCAN_TTIE_SE2E_Pos)               /*!< 0x00002000 */

+#define FDCAN_TTIE_SE2E           FDCAN_TTIE_SE2E_Msk                          /*!<Scheduling Error 2 Interrupt Enable               */

+#define FDCAN_TTIE_ELCE_Pos       (14U)

+#define FDCAN_TTIE_ELCE_Msk       (0x1UL << FDCAN_TTIE_ELCE_Pos)               /*!< 0x00004000 */

+#define FDCAN_TTIE_ELCE           FDCAN_TTIE_ELCE_Msk                          /*!<Error Level Changed Interrupt Enable              */

+#define FDCAN_TTIE_IWTE_Pos       (15U)

+#define FDCAN_TTIE_IWTE_Msk       (0x1UL << FDCAN_TTIE_IWTE_Pos)               /*!< 0x00008000 */

+#define FDCAN_TTIE_IWTE           FDCAN_TTIE_IWTE_Msk                          /*!<Initialization Watch Trigger Interrupt Enable     */

+#define FDCAN_TTIE_WTE_Pos        (16U)

+#define FDCAN_TTIE_WTE_Msk        (0x1UL << FDCAN_TTIE_WTE_Pos)                /*!< 0x00010000 */

+#define FDCAN_TTIE_WTE            FDCAN_TTIE_WTE_Msk                           /*!<Watch Trigger Interrupt Enable                    */

+#define FDCAN_TTIE_AWE_Pos        (17U)

+#define FDCAN_TTIE_AWE_Msk        (0x1UL << FDCAN_TTIE_AWE_Pos)                /*!< 0x00020000 */

+#define FDCAN_TTIE_AWE            FDCAN_TTIE_AWE_Msk                           /*!<Application Watchdog Interrupt Enable             */

+#define FDCAN_TTIE_CERE_Pos       (18U)

+#define FDCAN_TTIE_CERE_Msk       (0x1UL << FDCAN_TTIE_CERE_Pos)               /*!< 0x00040000 */

+#define FDCAN_TTIE_CERE           FDCAN_TTIE_CERE_Msk                          /*!<Configuration Error Interrupt Enable              */

+

+/*****************  Bit definition for FDCAN_TTILS register  ********************/

+#define FDCAN_TTILS_SBCS_Pos      (0U)

+#define FDCAN_TTILS_SBCS_Msk      (0x1UL << FDCAN_TTILS_SBCS_Pos)              /*!< 0x00000001 */

+#define FDCAN_TTILS_SBCS          FDCAN_TTILS_SBCS_Msk                         /*!<Start of Basic Cycle Interrupt Line               */

+#define FDCAN_TTILS_SMCS_Pos      (1U)

+#define FDCAN_TTILS_SMCS_Msk      (0x1UL << FDCAN_TTILS_SMCS_Pos)              /*!< 0x00000002 */

+#define FDCAN_TTILS_SMCS          FDCAN_TTILS_SMCS_Msk                         /*!<Start of Matrix Cycle Interrupt Line              */

+#define FDCAN_TTILS_CSMS_Pos      (2U)

+#define FDCAN_TTILS_CSMS_Msk      (0x1UL << FDCAN_TTILS_CSMS_Pos)              /*!< 0x00000004 */

+#define FDCAN_TTILS_CSMS          FDCAN_TTILS_CSMS_Msk                         /*!<Change of Synchronization Mode Interrupt Line     */

+#define FDCAN_TTILS_SOGS_Pos      (3U)

+#define FDCAN_TTILS_SOGS_Msk      (0x1UL << FDCAN_TTILS_SOGS_Pos)              /*!< 0x00000008 */

+#define FDCAN_TTILS_SOGS          FDCAN_TTILS_SOGS_Msk                         /*!<Start of Gap Interrupt Line                       */

+#define FDCAN_TTILS_RTMIS_Pos     (4U)

+#define FDCAN_TTILS_RTMIS_Msk     (0x1UL << FDCAN_TTILS_RTMIS_Pos)             /*!< 0x00000010 */

+#define FDCAN_TTILS_RTMIS         FDCAN_TTILS_RTMIS_Msk                        /*!<Register Time Mark Interrupt Interrupt Line       */

+#define FDCAN_TTILS_TTMIS_Pos     (5U)

+#define FDCAN_TTILS_TTMIS_Msk     (0x1UL << FDCAN_TTILS_TTMIS_Pos)             /*!< 0x00000020 */

+#define FDCAN_TTILS_TTMIS         FDCAN_TTILS_TTMIS_Msk                        /*!<Trigger Time Mark Event Internal Interrupt Line   */

+#define FDCAN_TTILS_SWES_Pos      (6U)

+#define FDCAN_TTILS_SWES_Msk      (0x1UL << FDCAN_TTILS_SWES_Pos)              /*!< 0x00000040 */

+#define FDCAN_TTILS_SWES          FDCAN_TTILS_SWES_Msk                         /*!<Stop Watch Event Interrupt Line                   */

+#define FDCAN_TTILS_GTWS_Pos      (7U)

+#define FDCAN_TTILS_GTWS_Msk      (0x1UL << FDCAN_TTILS_GTWS_Pos)              /*!< 0x00000080 */

+#define FDCAN_TTILS_GTWS          FDCAN_TTILS_GTWS_Msk                         /*!<Global Time Wrap Interrupt Line                   */

+#define FDCAN_TTILS_GTDS_Pos      (8U)

+#define FDCAN_TTILS_GTDS_Msk      (0x1UL << FDCAN_TTILS_GTDS_Pos)              /*!< 0x00000100 */

+#define FDCAN_TTILS_GTDS          FDCAN_TTILS_GTDS_Msk                         /*!<Global Time Discontinuity Interrupt Line          */

+#define FDCAN_TTILS_GTES_Pos      (9U)

+#define FDCAN_TTILS_GTES_Msk      (0x1UL << FDCAN_TTILS_GTES_Pos)              /*!< 0x00000200 */

+#define FDCAN_TTILS_GTES          FDCAN_TTILS_GTES_Msk                         /*!<Global Time Error Interrupt Line                  */

+#define FDCAN_TTILS_TXUS_Pos      (10U)

+#define FDCAN_TTILS_TXUS_Msk      (0x1UL << FDCAN_TTILS_TXUS_Pos)              /*!< 0x00000400 */

+#define FDCAN_TTILS_TXUS          FDCAN_TTILS_TXUS_Msk                         /*!<Tx Count Underflow Interrupt Line                 */

+#define FDCAN_TTILS_TXOS_Pos      (11U)

+#define FDCAN_TTILS_TXOS_Msk      (0x1UL << FDCAN_TTILS_TXOS_Pos)              /*!< 0x00000800 */

+#define FDCAN_TTILS_TXOS          FDCAN_TTILS_TXOS_Msk                         /*!<Tx Count Overflow Interrupt Line                  */

+#define FDCAN_TTILS_SE1S_Pos      (12U)

+#define FDCAN_TTILS_SE1S_Msk      (0x1UL << FDCAN_TTILS_SE1S_Pos)              /*!< 0x00001000 */

+#define FDCAN_TTILS_SE1S          FDCAN_TTILS_SE1S_Msk                         /*!<Scheduling Error 1 Interrupt Line                 */

+#define FDCAN_TTILS_SE2S_Pos      (13U)

+#define FDCAN_TTILS_SE2S_Msk      (0x1UL << FDCAN_TTILS_SE2S_Pos)              /*!< 0x00002000 */

+#define FDCAN_TTILS_SE2S          FDCAN_TTILS_SE2S_Msk                         /*!<Scheduling Error 2 Interrupt Line                 */

+#define FDCAN_TTILS_ELCS_Pos      (14U)

+#define FDCAN_TTILS_ELCS_Msk      (0x1UL << FDCAN_TTILS_ELCS_Pos)              /*!< 0x00004000 */

+#define FDCAN_TTILS_ELCS          FDCAN_TTILS_ELCS_Msk                         /*!<Error Level Changed Interrupt Line                */

+#define FDCAN_TTILS_IWTS_Pos      (15U)

+#define FDCAN_TTILS_IWTS_Msk      (0x1UL << FDCAN_TTILS_IWTS_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTILS_IWTS          FDCAN_TTILS_IWTS_Msk                         /*!<Initialization Watch Trigger Interrupt Line       */

+#define FDCAN_TTILS_WTS_Pos       (16U)

+#define FDCAN_TTILS_WTS_Msk       (0x1UL << FDCAN_TTILS_WTS_Pos)               /*!< 0x00010000 */

+#define FDCAN_TTILS_WTS           FDCAN_TTILS_WTS_Msk                          /*!<Watch Trigger Interrupt Line                      */

+#define FDCAN_TTILS_AWS_Pos       (17U)

+#define FDCAN_TTILS_AWS_Msk       (0x1UL << FDCAN_TTILS_AWS_Pos)               /*!< 0x00020000 */

+#define FDCAN_TTILS_AWS           FDCAN_TTILS_AWS_Msk                          /*!<Application Watchdog Interrupt Line               */

+#define FDCAN_TTILS_CERS_Pos      (18U)

+#define FDCAN_TTILS_CERS_Msk      (0x1UL << FDCAN_TTILS_CERS_Pos)              /*!< 0x00040000 */

+#define FDCAN_TTILS_CERS          FDCAN_TTILS_CERS_Msk                         /*!<Configuration Error Interrupt Line                */

+

+/*****************  Bit definition for FDCAN_TTOST register  ********************/

+#define FDCAN_TTOST_EL_Pos        (0U)

+#define FDCAN_TTOST_EL_Msk        (0x3UL << FDCAN_TTOST_EL_Pos)                /*!< 0x00000003 */

+#define FDCAN_TTOST_EL            FDCAN_TTOST_EL_Msk                           /*!<Error Level                              */

+#define FDCAN_TTOST_MS_Pos        (2U)

+#define FDCAN_TTOST_MS_Msk        (0x3UL << FDCAN_TTOST_MS_Pos)                /*!< 0x0000000C */

+#define FDCAN_TTOST_MS            FDCAN_TTOST_MS_Msk                           /*!<Master State                             */

+#define FDCAN_TTOST_SYS_Pos       (4U)

+#define FDCAN_TTOST_SYS_Msk       (0x3UL << FDCAN_TTOST_SYS_Pos)               /*!< 0x00000030 */

+#define FDCAN_TTOST_SYS           FDCAN_TTOST_SYS_Msk                          /*!<Synchronization State                    */

+#define FDCAN_TTOST_QGTP_Pos      (6U)

+#define FDCAN_TTOST_QGTP_Msk      (0x1UL << FDCAN_TTOST_QGTP_Pos)              /*!< 0x00000040 */

+#define FDCAN_TTOST_QGTP          FDCAN_TTOST_QGTP_Msk                         /*!<Quality of Global Time Phase             */

+#define FDCAN_TTOST_QCS_Pos       (7U)

+#define FDCAN_TTOST_QCS_Msk       (0x1UL << FDCAN_TTOST_QCS_Pos)               /*!< 0x00000080 */

+#define FDCAN_TTOST_QCS           FDCAN_TTOST_QCS_Msk                          /*!<Quality of Clock Speed                   */

+#define FDCAN_TTOST_RTO_Pos       (8U)

+#define FDCAN_TTOST_RTO_Msk       (0xFFUL << FDCAN_TTOST_RTO_Pos)              /*!< 0x0000FF00 */

+#define FDCAN_TTOST_RTO           FDCAN_TTOST_RTO_Msk                          /*!<Reference Trigger Offset                 */

+#define FDCAN_TTOST_WGTD_Pos      (22U)

+#define FDCAN_TTOST_WGTD_Msk      (0x1UL << FDCAN_TTOST_WGTD_Pos)              /*!< 0x00400000 */

+#define FDCAN_TTOST_WGTD          FDCAN_TTOST_WGTD_Msk                         /*!<Wait for Global Time Discontinuity       */

+#define FDCAN_TTOST_GFI_Pos       (23U)

+#define FDCAN_TTOST_GFI_Msk       (0x1UL << FDCAN_TTOST_GFI_Pos)               /*!< 0x00800000 */

+#define FDCAN_TTOST_GFI           FDCAN_TTOST_GFI_Msk                          /*!<Gap Finished Indicator                   */

+#define FDCAN_TTOST_TMP_Pos       (24U)

+#define FDCAN_TTOST_TMP_Msk       (0x7UL << FDCAN_TTOST_TMP_Pos)               /*!< 0x07000000 */

+#define FDCAN_TTOST_TMP           FDCAN_TTOST_TMP_Msk                          /*!<Time Master Priority                     */

+#define FDCAN_TTOST_GSI_Pos       (27U)

+#define FDCAN_TTOST_GSI_Msk       (0x1UL << FDCAN_TTOST_GSI_Pos)               /*!< 0x08000000 */

+#define FDCAN_TTOST_GSI           FDCAN_TTOST_GSI_Msk                          /*!<Gap Started Indicator                    */

+#define FDCAN_TTOST_WFE_Pos       (28U)

+#define FDCAN_TTOST_WFE_Msk       (0x1UL << FDCAN_TTOST_WFE_Pos)               /*!< 0x10000000 */

+#define FDCAN_TTOST_WFE           FDCAN_TTOST_WFE_Msk                          /*!<Wait for Event                           */

+#define FDCAN_TTOST_AWE_Pos       (29U)

+#define FDCAN_TTOST_AWE_Msk       (0x1UL << FDCAN_TTOST_AWE_Pos)               /*!< 0x20000000 */

+#define FDCAN_TTOST_AWE           FDCAN_TTOST_AWE_Msk                          /*!<Application Watchdog Event               */

+#define FDCAN_TTOST_WECS_Pos      (30U)

+#define FDCAN_TTOST_WECS_Msk      (0x1UL << FDCAN_TTOST_WECS_Pos)              /*!< 0x40000000 */

+#define FDCAN_TTOST_WECS          FDCAN_TTOST_WECS_Msk                         /*!<Wait for External Clock Synchronization  */

+#define FDCAN_TTOST_SPL_Pos       (31U)

+#define FDCAN_TTOST_SPL_Msk       (0x1UL << FDCAN_TTOST_SPL_Pos)               /*!< 0x80000000 */

+#define FDCAN_TTOST_SPL           FDCAN_TTOST_SPL_Msk                          /*!<Schedule Phase Lock                      */

+

+/*****************  Bit definition for FDCAN_TURNA register  ********************/

+#define FDCAN_TURNA_NAV_Pos       (0U)

+#define FDCAN_TURNA_NAV_Msk       (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)           /*!< 0x0003FFFF */

+#define FDCAN_TURNA_NAV           FDCAN_TURNA_NAV_Msk                          /*!<Numerator Actual Value                   */

+

+/*****************  Bit definition for FDCAN_TTLGT register  ********************/

+#define FDCAN_TTLGT_LT_Pos        (0U)

+#define FDCAN_TTLGT_LT_Msk        (0xFFFFUL << FDCAN_TTLGT_LT_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTLGT_LT            FDCAN_TTLGT_LT_Msk                           /*!<Local Time                               */

+#define FDCAN_TTLGT_GT_Pos        (16U)

+#define FDCAN_TTLGT_GT_Msk        (0xFFFFUL << FDCAN_TTLGT_GT_Pos)             /*!< 0xFFFF0000 */

+#define FDCAN_TTLGT_GT            FDCAN_TTLGT_GT_Msk                           /*!<Global Time                              */

+

+/*****************  Bit definition for FDCAN_TTCTC register  ********************/

+#define FDCAN_TTCTC_CT_Pos        (0U)

+#define FDCAN_TTCTC_CT_Msk        (0xFFFFUL << FDCAN_TTCTC_CT_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTCTC_CT            FDCAN_TTCTC_CT_Msk                           /*!<Cycle Time                               */

+#define FDCAN_TTCTC_CC_Pos        (16U)

+#define FDCAN_TTCTC_CC_Msk        (0x3FUL << FDCAN_TTCTC_CC_Pos)               /*!< 0x003F0000 */

+#define FDCAN_TTCTC_CC            FDCAN_TTCTC_CC_Msk                           /*!<Cycle Count                              */

+

+/*****************  Bit definition for FDCAN_TTCPT register  ********************/

+#define FDCAN_TTCPT_CCV_Pos       (0U)

+#define FDCAN_TTCPT_CCV_Msk       (0x3FUL << FDCAN_TTCPT_CCV_Pos)              /*!< 0x0000003F */

+#define FDCAN_TTCPT_CCV           FDCAN_TTCPT_CCV_Msk                          /*!<Cycle Count Value                        */

+#define FDCAN_TTCPT_SWV_Pos       (16U)

+#define FDCAN_TTCPT_SWV_Msk       (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)            /*!< 0xFFFF0000 */

+#define FDCAN_TTCPT_SWV           FDCAN_TTCPT_SWV_Msk                          /*!<Stop Watch Value                         */

+

+/*****************  Bit definition for FDCAN_TTCSM register  ********************/

+#define FDCAN_TTCSM_CSM_Pos       (0U)

+#define FDCAN_TTCSM_CSM_Msk       (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)            /*!< 0x0000FFFF */

+#define FDCAN_TTCSM_CSM           FDCAN_TTCSM_CSM_Msk                          /*!<Cycle Sync Mark                          */

+

+/*****************  Bit definition for FDCAN_TTTS register  *********************/

+#define FDCAN_TTTS_SWTSEL_Pos     (0U)

+#define FDCAN_TTTS_SWTSEL_Msk     (0x3UL << FDCAN_TTTS_SWTSEL_Pos)             /*!< 0x00000003 */

+#define FDCAN_TTTS_SWTSEL         FDCAN_TTTS_SWTSEL_Msk                        /*!<Stop watch trigger input selection       */

+#define FDCAN_TTTS_EVTSEL_Pos     (4U)

+#define FDCAN_TTTS_EVTSEL_Msk     (0x3UL << FDCAN_TTTS_EVTSEL_Pos)             /*!< 0x00000030 */

+#define FDCAN_TTTS_EVTSEL         FDCAN_TTTS_EVTSEL_Msk                        /*!<Event trigger input selection            */

+

+/********************************************************************************/

+/*                                                                              */

+/*                      FDCANCCU (Clock Calibration unit)                       */

+/*                                                                              */

+/********************************************************************************/

+

+/*****************  Bit definition for FDCANCCU_CREL register  ******************/

+#define FDCANCCU_CREL_DAY_Pos        (0U)

+#define FDCANCCU_CREL_DAY_Msk        (0xFFUL << FDCANCCU_CREL_DAY_Pos)         /*!< 0x000000FF */

+#define FDCANCCU_CREL_DAY            FDCANCCU_CREL_DAY_Msk                     /*!<Timestamp Day                           */

+#define FDCANCCU_CREL_MON_Pos        (8U)

+#define FDCANCCU_CREL_MON_Msk        (0xFFUL << FDCANCCU_CREL_MON_Pos)         /*!< 0x0000FF00 */

+#define FDCANCCU_CREL_MON            FDCANCCU_CREL_MON_Msk                     /*!<Timestamp Month                         */

+#define FDCANCCU_CREL_YEAR_Pos       (16U)

+#define FDCANCCU_CREL_YEAR_Msk       (0xFUL << FDCANCCU_CREL_YEAR_Pos)         /*!< 0x000F0000 */

+#define FDCANCCU_CREL_YEAR           FDCANCCU_CREL_YEAR_Msk                    /*!<Timestamp Year                          */

+#define FDCANCCU_CREL_SUBSTEP_Pos    (20U)

+#define FDCANCCU_CREL_SUBSTEP_Msk    (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)      /*!< 0x00F00000 */

+#define FDCANCCU_CREL_SUBSTEP        FDCANCCU_CREL_SUBSTEP_Msk                 /*!<Sub-step of Core release                */

+#define FDCANCCU_CREL_STEP_Pos       (24U)

+#define FDCANCCU_CREL_STEP_Msk       (0xFUL << FDCANCCU_CREL_STEP_Pos)         /*!< 0x0F000000 */

+#define FDCANCCU_CREL_STEP           FDCANCCU_CREL_STEP_Msk                    /*!<Step of Core release                    */

+#define FDCANCCU_CREL_REL_Pos        (28U)

+#define FDCANCCU_CREL_REL_Msk        (0xFUL << FDCANCCU_CREL_REL_Pos)          /*!< 0xF0000000 */

+#define FDCANCCU_CREL_REL            FDCANCCU_CREL_REL_Msk                     /*!<Core release                            */

+

+/*****************  Bit definition for FDCANCCU_CCFG register  ******************/

+#define FDCANCCU_CCFG_TQBT_Pos       (0U)

+#define FDCANCCU_CCFG_TQBT_Msk       (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)        /*!< 0x0000001F */

+#define FDCANCCU_CCFG_TQBT           FDCANCCU_CCFG_TQBT_Msk                    /*!<Time Quanta per Bit Time                */

+#define FDCANCCU_CCFG_BCC_Pos        (6U)

+#define FDCANCCU_CCFG_BCC_Msk        (0x1UL << FDCANCCU_CCFG_BCC_Pos)          /*!< 0x00000040 */

+#define FDCANCCU_CCFG_BCC            FDCANCCU_CCFG_BCC_Msk                     /*!<Bypass Clock Calibration                */

+#define FDCANCCU_CCFG_CFL_Pos        (7U)

+#define FDCANCCU_CCFG_CFL_Msk        (0x1UL << FDCANCCU_CCFG_CFL_Pos)          /*!< 0x00000080 */

+#define FDCANCCU_CCFG_CFL            FDCANCCU_CCFG_CFL_Msk                     /*!<Calibration Field Length                */

+#define FDCANCCU_CCFG_OCPM_Pos       (8U)

+#define FDCANCCU_CCFG_OCPM_Msk       (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)        /*!< 0x0000FF00 */

+#define FDCANCCU_CCFG_OCPM           FDCANCCU_CCFG_OCPM_Msk                    /*!<Oscillator Clock Periods Minimum        */

+#define FDCANCCU_CCFG_CDIV_Pos       (16U)

+#define FDCANCCU_CCFG_CDIV_Msk       (0xFUL << FDCANCCU_CCFG_CDIV_Pos)         /*!< 0x000F0000 */

+#define FDCANCCU_CCFG_CDIV           FDCANCCU_CCFG_CDIV_Msk                    /*!<Clock Divider                           */

+#define FDCANCCU_CCFG_SWR_Pos        (31U)

+#define FDCANCCU_CCFG_SWR_Msk        (0x1UL << FDCANCCU_CCFG_SWR_Pos)          /*!< 0x80000000 */

+#define FDCANCCU_CCFG_SWR            FDCANCCU_CCFG_SWR_Msk                     /*!<Software Reset                          */

+

+/*****************  Bit definition for FDCANCCU_CSTAT register  *****************/

+#define FDCANCCU_CSTAT_OCPC_Pos      (0U)

+#define FDCANCCU_CSTAT_OCPC_Msk      (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)    /*!< 0x0003FFFF */

+#define FDCANCCU_CSTAT_OCPC          FDCANCCU_CSTAT_OCPC_Msk                   /*!<Oscillator Clock Period Counter        */

+#define FDCANCCU_CSTAT_TQC_Pos       (18U)

+#define FDCANCCU_CSTAT_TQC_Msk       (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)       /*!< 0x1FFC0000 */

+#define FDCANCCU_CSTAT_TQC           FDCANCCU_CSTAT_TQC_Msk                    /*!<Time Quanta Counter                    */

+#define FDCANCCU_CSTAT_CALS_Pos      (30U)

+#define FDCANCCU_CSTAT_CALS_Msk      (0x3UL << FDCANCCU_CSTAT_CALS_Pos)        /*!< 0xC0000000 */

+#define FDCANCCU_CSTAT_CALS          FDCANCCU_CSTAT_CALS_Msk                   /*!<Calibration State                      */

+

+/******************  Bit definition for FDCANCCU_CWD register  ******************/

+#define FDCANCCU_CWD_WDC_Pos         (0U)

+#define FDCANCCU_CWD_WDC_Msk         (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)        /*!< 0x0000FFFF */

+#define FDCANCCU_CWD_WDC             FDCANCCU_CWD_WDC_Msk                      /*!<Watchdog Configuration                 */

+#define FDCANCCU_CWD_WDV_Pos         (16U)

+#define FDCANCCU_CWD_WDV_Msk         (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)        /*!< 0xFFFF0000 */

+#define FDCANCCU_CWD_WDV             FDCANCCU_CWD_WDV_Msk                      /*!<Watchdog Value                         */

+

+/******************  Bit definition for FDCANCCU_IR register  *******************/

+#define FDCANCCU_IR_CWE_Pos          (0U)

+#define FDCANCCU_IR_CWE_Msk          (0x1UL << FDCANCCU_IR_CWE_Pos)            /*!< 0x00000001 */

+#define FDCANCCU_IR_CWE              FDCANCCU_IR_CWE_Msk                       /*!<Calibration Watchdog Event             */

+#define FDCANCCU_IR_CSC_Pos          (1U)

+#define FDCANCCU_IR_CSC_Msk          (0x1UL << FDCANCCU_IR_CSC_Pos)            /*!< 0x00000002 */

+#define FDCANCCU_IR_CSC              FDCANCCU_IR_CSC_Msk                       /*!<Calibration State Changed              */

+

+/******************  Bit definition for FDCANCCU_IE register  *******************/

+#define FDCANCCU_IE_CWEE_Pos         (0U)

+#define FDCANCCU_IE_CWEE_Msk         (0x1UL << FDCANCCU_IE_CWEE_Pos)           /*!< 0x00000001 */

+#define FDCANCCU_IE_CWEE             FDCANCCU_IE_CWEE_Msk                      /*!<Calibration Watchdog Event Enable      */

+#define FDCANCCU_IE_CSCE_Pos         (1U)

+#define FDCANCCU_IE_CSCE_Msk         (0x1UL << FDCANCCU_IE_CSCE_Pos)           /*!< 0x00000002 */

+#define FDCANCCU_IE_CSCE             FDCANCCU_IE_CSCE_Msk                      /*!<Calibration State Changed Enable       */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          HDMI-CEC (CEC)                                    */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for CEC_CR register  *********************/

+#define CEC_CR_CECEN_Pos         (0U)

+#define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                   /*!< 0x00000001 */

+#define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                                */

+#define CEC_CR_TXSOM_Pos         (1U)

+#define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                   /*!< 0x00000002 */

+#define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message                   */

+#define CEC_CR_TXEOM_Pos         (2U)

+#define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                   /*!< 0x00000004 */

+#define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message                     */

+

+/*******************  Bit definition for CEC_CFGR register  *******************/

+#define CEC_CFGR_SFT_Pos         (0U)

+#define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                   /*!< 0x00000007 */

+#define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time                      */

+#define CEC_CFGR_RXTOL_Pos       (3U)

+#define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                 /*!< 0x00000008 */

+#define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                             */

+#define CEC_CFGR_BRESTP_Pos      (4U)

+#define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                /*!< 0x00000010 */

+#define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                               */

+#define CEC_CFGR_BREGEN_Pos      (5U)

+#define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                /*!< 0x00000020 */

+#define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation           */

+#define CEC_CFGR_LBPEGEN_Pos     (6U)

+#define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)               /*!< 0x00000040 */

+#define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error generation      */

+#define CEC_CFGR_SFTOPT_Pos      (8U)

+#define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                /*!< 0x00000100 */

+#define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional             */

+#define CEC_CFGR_BRDNOGEN_Pos    (7U)

+#define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)              /*!< 0x00000080 */

+#define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No error generation         */

+#define CEC_CFGR_OAR_Pos         (16U)

+#define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                /*!< 0x7FFF0000 */

+#define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                           */

+#define CEC_CFGR_LSTN_Pos        (31U)

+#define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                  /*!< 0x80000000 */

+#define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                           */

+

+/*******************  Bit definition for CEC_TXDR register  *******************/

+#define CEC_TXDR_TXD_Pos         (0U)

+#define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                  /*!< 0x000000FF */

+#define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                               */

+

+/*******************  Bit definition for CEC_RXDR register  *******************/

+#define CEC_RXDR_RXD_Pos         (0U)

+#define CEC_RXDR_RXD_Msk         (0xFFUL << CEC_RXDR_RXD_Pos)                  /*!< 0x000000FF */

+#define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                              /*!< CEC Rx Data                               */

+

+/*******************  Bit definition for CEC_ISR register  ********************/

+#define CEC_ISR_RXBR_Pos         (0U)

+#define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                   /*!< 0x00000001 */

+#define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                      */

+#define CEC_ISR_RXEND_Pos        (1U)

+#define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                  /*!< 0x00000002 */

+#define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                      */

+#define CEC_ISR_RXOVR_Pos        (2U)

+#define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                  /*!< 0x00000004 */

+#define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                            */

+#define CEC_ISR_BRE_Pos          (3U)

+#define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                    /*!< 0x00000008 */

+#define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                   */

+#define CEC_ISR_SBPE_Pos         (4U)

+#define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                   /*!< 0x00000010 */

+#define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error             */

+#define CEC_ISR_LBPE_Pos         (5U)

+#define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                   /*!< 0x00000020 */

+#define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error              */

+#define CEC_ISR_RXACKE_Pos       (6U)

+#define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                 /*!< 0x00000040 */

+#define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge                */

+#define CEC_ISR_ARBLST_Pos       (7U)

+#define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                 /*!< 0x00000080 */

+#define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                      */

+#define CEC_ISR_TXBR_Pos         (8U)

+#define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                   /*!< 0x00000100 */

+#define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                       */

+#define CEC_ISR_TXEND_Pos        (9U)

+#define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                  /*!< 0x00000200 */

+#define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                   */

+#define CEC_ISR_TXUDR_Pos        (10U)

+#define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                  /*!< 0x00000400 */

+#define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                    */

+#define CEC_ISR_TXERR_Pos        (11U)

+#define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                  /*!< 0x00000800 */

+#define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                              */

+#define CEC_ISR_TXACKE_Pos       (12U)

+#define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                 /*!< 0x00001000 */

+#define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge                */

+

+/*******************  Bit definition for CEC_IER register  ********************/

+#define CEC_IER_RXBRIE_Pos       (0U)

+#define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                 /*!< 0x00000001 */

+#define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable            */

+#define CEC_IER_RXENDIE_Pos      (1U)

+#define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                /*!< 0x00000002 */

+#define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable            */

+#define CEC_IER_RXOVRIE_Pos      (2U)

+#define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                /*!< 0x00000004 */

+#define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable                  */

+#define CEC_IER_BREIE_Pos        (3U)

+#define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                  /*!< 0x00000008 */

+#define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable         */

+#define CEC_IER_SBPEIE_Pos       (4U)

+#define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                 /*!< 0x00000010 */

+#define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable   */

+#define CEC_IER_LBPEIE_Pos       (5U)

+#define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                 /*!< 0x00000020 */

+#define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable    */

+#define CEC_IER_RXACKEIE_Pos     (6U)

+#define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)               /*!< 0x00000040 */

+#define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable      */

+#define CEC_IER_ARBLSTIE_Pos     (7U)

+#define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)               /*!< 0x00000080 */

+#define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable            */

+#define CEC_IER_TXBRIE_Pos       (8U)

+#define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                 /*!< 0x00000100 */

+#define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable            */

+#define CEC_IER_TXENDIE_Pos      (9U)

+#define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                /*!< 0x00000200 */

+#define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable         */

+#define CEC_IER_TXUDRIE_Pos      (10U)

+#define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                /*!< 0x00000400 */

+#define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable          */

+#define CEC_IER_TXERRIE_Pos      (11U)

+#define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                /*!< 0x00000800 */

+#define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                    */

+#define CEC_IER_TXACKEIE_Pos     (12U)

+#define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)               /*!< 0x00001000 */

+#define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable      */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          CRC calculation unit                              */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for CRC_DR register  *********************/

+#define CRC_DR_DR_Pos            (0U)

+#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */

+#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */

+

+/*******************  Bit definition for CRC_IDR register  ********************/

+#define CRC_IDR_IDR_Pos          (0U)

+#define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */

+#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */

+

+/********************  Bit definition for CRC_CR register  ********************/

+#define CRC_CR_RESET_Pos         (0U)

+#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */

+#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */

+#define CRC_CR_POLYSIZE_Pos      (3U)

+#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */

+#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */

+#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */

+#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */

+#define CRC_CR_REV_IN_Pos        (5U)

+#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */

+#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */

+#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */

+#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */

+#define CRC_CR_REV_OUT_Pos       (7U)

+#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */

+#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */

+

+/*******************  Bit definition for CRC_INIT register  *******************/

+#define CRC_INIT_INIT_Pos        (0U)

+#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */

+#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */

+

+/*******************  Bit definition for CRC_POL register  ********************/

+#define CRC_POL_POL_Pos          (0U)

+#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */

+#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          CRS Clock Recovery System                         */

+/******************************************************************************/

+

+/*******************  Bit definition for CRS_CR register  *********************/

+#define CRS_CR_SYNCOKIE_Pos       (0U)

+#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */

+#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */

+#define CRS_CR_SYNCWARNIE_Pos     (1U)

+#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */

+#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */

+#define CRS_CR_ERRIE_Pos          (2U)

+#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */

+#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */

+#define CRS_CR_ESYNCIE_Pos        (3U)

+#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */

+#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */

+#define CRS_CR_CEN_Pos            (5U)

+#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */

+#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */

+#define CRS_CR_AUTOTRIMEN_Pos     (6U)

+#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */

+#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */

+#define CRS_CR_SWSYNC_Pos         (7U)

+#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */

+#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */

+#define CRS_CR_TRIM_Pos           (8U)

+#define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00003F00 */

+#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */

+

+/*******************  Bit definition for CRS_CFGR register  *********************/

+#define CRS_CFGR_RELOAD_Pos       (0U)

+#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */

+#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */

+#define CRS_CFGR_FELIM_Pos        (16U)

+#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */

+#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */

+

+#define CRS_CFGR_SYNCDIV_Pos      (24U)

+#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */

+#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */

+#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */

+#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */

+#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */

+

+#define CRS_CFGR_SYNCSRC_Pos      (28U)

+#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */

+#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */

+#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */

+#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */

+

+#define CRS_CFGR_SYNCPOL_Pos      (31U)

+#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */

+#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */

+

+/*******************  Bit definition for CRS_ISR register  *********************/

+#define CRS_ISR_SYNCOKF_Pos       (0U)

+#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */

+#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */

+#define CRS_ISR_SYNCWARNF_Pos     (1U)

+#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */

+#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */

+#define CRS_ISR_ERRF_Pos          (2U)

+#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */

+#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */

+#define CRS_ISR_ESYNCF_Pos        (3U)

+#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */

+#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */

+#define CRS_ISR_SYNCERR_Pos       (8U)

+#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */

+#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */

+#define CRS_ISR_SYNCMISS_Pos      (9U)

+#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */

+#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */

+#define CRS_ISR_TRIMOVF_Pos       (10U)

+#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */

+#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */

+#define CRS_ISR_FEDIR_Pos         (15U)

+#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */

+#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */

+#define CRS_ISR_FECAP_Pos         (16U)

+#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */

+#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */

+

+/*******************  Bit definition for CRS_ICR register  *********************/

+#define CRS_ICR_SYNCOKC_Pos       (0U)

+#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */

+#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */

+#define CRS_ICR_SYNCWARNC_Pos     (1U)

+#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */

+#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */

+#define CRS_ICR_ERRC_Pos          (2U)

+#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */

+#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */

+#define CRS_ICR_ESYNCC_Pos        (3U)

+#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */

+#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      Digital to Analog Converter                           */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for DAC_CR register  ********************/

+#define DAC_CR_EN1_Pos              (0U)

+#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */

+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */

+#define DAC_CR_TEN1_Pos             (1U)

+#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */

+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */

+

+#define DAC_CR_TSEL1_Pos            (2U)

+#define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */

+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */

+#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000004 */

+#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */

+#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */

+#define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */

+

+

+#define DAC_CR_WAVE1_Pos            (6U)

+#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */

+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */

+#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */

+#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */

+

+#define DAC_CR_MAMP1_Pos            (8U)

+#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */

+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */

+#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */

+#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */

+#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */

+#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */

+

+#define DAC_CR_DMAEN1_Pos           (12U)

+#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */

+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */

+#define DAC_CR_DMAUDRIE1_Pos        (13U)

+#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */

+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/

+#define DAC_CR_CEN1_Pos             (14U)

+#define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */

+#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/

+

+#define DAC_CR_EN2_Pos              (16U)

+#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */

+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */

+#define DAC_CR_TEN2_Pos             (17U)

+#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */

+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */

+

+#define DAC_CR_TSEL2_Pos            (18U)

+#define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */

+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */

+#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00040000 */

+#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */

+#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */

+#define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */

+

+

+#define DAC_CR_WAVE2_Pos            (22U)

+#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */

+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */

+#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */

+#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */

+

+#define DAC_CR_MAMP2_Pos            (24U)

+#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */

+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */

+#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */

+#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */

+#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */

+#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */

+

+#define DAC_CR_DMAEN2_Pos           (28U)

+#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */

+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */

+#define DAC_CR_DMAUDRIE2_Pos        (29U)

+#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */

+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/

+#define DAC_CR_CEN2_Pos             (30U)

+#define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */

+#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/

+

+/*****************  Bit definition for DAC_SWTRIGR register  ******************/

+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)

+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */

+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */

+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)

+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */

+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */

+

+/*****************  Bit definition for DAC_DHR12R1 register  ******************/

+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)

+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12L1 register  ******************/

+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)

+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8R1 register  ******************/

+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)

+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12R2 register  ******************/

+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)

+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12L2 register  ******************/

+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)

+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8R2 register  ******************/

+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)

+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12RD register  ******************/

+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)

+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */

+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)

+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */

+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12LD register  ******************/

+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)

+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */

+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)

+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */

+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8RD register  ******************/

+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)

+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */

+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)

+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */

+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */

+

+/*******************  Bit definition for DAC_DOR1 register  *******************/

+#define DAC_DOR1_DACC1DOR_Pos       (0U)

+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */

+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */

+

+/*******************  Bit definition for DAC_DOR2 register  *******************/

+#define DAC_DOR2_DACC2DOR_Pos       (0U)

+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */

+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */

+

+/********************  Bit definition for DAC_SR register  ********************/

+#define DAC_SR_DMAUDR1_Pos          (13U)

+#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */

+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */

+#define DAC_SR_CAL_FLAG1_Pos        (14U)

+#define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */

+#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */

+#define DAC_SR_BWST1_Pos            (15U)

+#define DAC_SR_BWST1_Msk            (0x4001UL << DAC_SR_BWST1_Pos)             /*!< 0x20008000 */

+#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */

+

+#define DAC_SR_DMAUDR2_Pos          (29U)

+#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */

+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */

+#define DAC_SR_CAL_FLAG2_Pos        (30U)

+#define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */

+#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */

+#define DAC_SR_BWST2_Pos            (31U)

+#define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */

+#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */

+

+/*******************  Bit definition for DAC_CCR register  ********************/

+#define DAC_CCR_OTRIM1_Pos          (0U)

+#define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */

+#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */

+#define DAC_CCR_OTRIM2_Pos          (16U)

+#define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */

+#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */

+

+/*******************  Bit definition for DAC_MCR register  *******************/

+#define DAC_MCR_MODE1_Pos           (0U)

+#define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */

+#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */

+#define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */

+#define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */

+#define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */

+

+#define DAC_MCR_MODE2_Pos           (16U)

+#define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */

+#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */

+#define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */

+#define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */

+#define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */

+

+/******************  Bit definition for DAC_SHSR1 register  ******************/

+#define DAC_SHSR1_TSAMPLE1_Pos      (0U)

+#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */

+#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */

+

+/******************  Bit definition for DAC_SHSR2 register  ******************/

+#define DAC_SHSR2_TSAMPLE2_Pos      (0U)

+#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */

+#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */

+

+/******************  Bit definition for DAC_SHHR register  ******************/

+#define DAC_SHHR_THOLD1_Pos         (0U)

+#define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */

+#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */

+#define DAC_SHHR_THOLD2_Pos         (16U)

+#define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */

+#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */

+

+/******************  Bit definition for DAC_SHRR register  ******************/

+#define DAC_SHRR_TREFRESH1_Pos      (0U)

+#define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */

+#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */

+#define DAC_SHRR_TREFRESH2_Pos      (16U)

+#define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */

+#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    DCMI                                    */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DCMI_CR register  ******************/

+#define DCMI_CR_CAPTURE_Pos        (0U)

+#define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)              /*!< 0x00000001 */

+#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk

+#define DCMI_CR_CM_Pos             (1U)

+#define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                   /*!< 0x00000002 */

+#define DCMI_CR_CM                 DCMI_CR_CM_Msk

+#define DCMI_CR_CROP_Pos           (2U)

+#define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                 /*!< 0x00000004 */

+#define DCMI_CR_CROP               DCMI_CR_CROP_Msk

+#define DCMI_CR_JPEG_Pos           (3U)

+#define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                 /*!< 0x00000008 */

+#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk

+#define DCMI_CR_ESS_Pos            (4U)

+#define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                  /*!< 0x00000010 */

+#define DCMI_CR_ESS                DCMI_CR_ESS_Msk

+#define DCMI_CR_PCKPOL_Pos         (5U)

+#define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)               /*!< 0x00000020 */

+#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk

+#define DCMI_CR_HSPOL_Pos          (6U)

+#define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                /*!< 0x00000040 */

+#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk

+#define DCMI_CR_VSPOL_Pos          (7U)

+#define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */

+#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk

+#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)

+#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)

+#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)

+#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)

+#define DCMI_CR_CRE_Pos            (12U)

+#define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */

+#define DCMI_CR_CRE                DCMI_CR_CRE_Msk

+#define DCMI_CR_ENABLE_Pos         (14U)

+#define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)               /*!< 0x00004000 */

+#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk

+#define DCMI_CR_BSM_Pos            (16U)

+#define DCMI_CR_BSM_Msk            (0x3UL << DCMI_CR_BSM_Pos)                  /*!< 0x00030000 */

+#define DCMI_CR_BSM                DCMI_CR_BSM_Msk

+#define DCMI_CR_BSM_0              (0x1UL << DCMI_CR_BSM_Pos)                   /*!< 0x00010000 */

+#define DCMI_CR_BSM_1              (0x2UL << DCMI_CR_BSM_Pos)                   /*!< 0x00020000 */

+#define DCMI_CR_OEBS_Pos           (18U)

+#define DCMI_CR_OEBS_Msk           (0x1UL << DCMI_CR_OEBS_Pos)                 /*!< 0x00040000 */

+#define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk

+#define DCMI_CR_LSM_Pos            (19U)

+#define DCMI_CR_LSM_Msk            (0x1UL << DCMI_CR_LSM_Pos)                  /*!< 0x00080000 */

+#define DCMI_CR_LSM                DCMI_CR_LSM_Msk

+#define DCMI_CR_OELS_Pos           (20U)

+#define DCMI_CR_OELS_Msk           (0x1UL << DCMI_CR_OELS_Pos)                 /*!< 0x00100000 */

+#define DCMI_CR_OELS               DCMI_CR_OELS_Msk

+

+/********************  Bits definition for DCMI_SR register  ******************/

+#define DCMI_SR_HSYNC_Pos          (0U)

+#define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                /*!< 0x00000001 */

+#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk

+#define DCMI_SR_VSYNC_Pos          (1U)

+#define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                /*!< 0x00000002 */

+#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk

+#define DCMI_SR_FNE_Pos            (2U)

+#define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                  /*!< 0x00000004 */

+#define DCMI_SR_FNE                DCMI_SR_FNE_Msk

+

+/********************  Bits definition for DCMI_RIS register   ****************/

+#define DCMI_RIS_FRAME_RIS_Pos     (0U)

+#define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)           /*!< 0x00000001 */

+#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk

+#define DCMI_RIS_OVR_RIS_Pos       (1U)

+#define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)             /*!< 0x00000002 */

+#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk

+#define DCMI_RIS_ERR_RIS_Pos       (2U)

+#define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)             /*!< 0x00000004 */

+#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk

+#define DCMI_RIS_VSYNC_RIS_Pos     (3U)

+#define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)           /*!< 0x00000008 */

+#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk

+#define DCMI_RIS_LINE_RIS_Pos      (4U)

+#define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)            /*!< 0x00000010 */

+#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk

+

+/********************  Bits definition for DCMI_IER register  *****************/

+#define DCMI_IER_FRAME_IE_Pos      (0U)

+#define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)            /*!< 0x00000001 */

+#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk

+#define DCMI_IER_OVR_IE_Pos        (1U)

+#define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)              /*!< 0x00000002 */

+#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk

+#define DCMI_IER_ERR_IE_Pos        (2U)

+#define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)              /*!< 0x00000004 */

+#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk

+#define DCMI_IER_VSYNC_IE_Pos      (3U)

+#define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)            /*!< 0x00000008 */

+#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk

+#define DCMI_IER_LINE_IE_Pos       (4U)

+#define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)             /*!< 0x00000010 */

+#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk

+

+

+/********************  Bits definition for DCMI_MIS register  *****************/

+#define DCMI_MIS_FRAME_MIS_Pos     (0U)

+#define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)           /*!< 0x00000001 */

+#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk

+#define DCMI_MIS_OVR_MIS_Pos       (1U)

+#define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)             /*!< 0x00000002 */

+#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk

+#define DCMI_MIS_ERR_MIS_Pos       (2U)

+#define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)             /*!< 0x00000004 */

+#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk

+#define DCMI_MIS_VSYNC_MIS_Pos     (3U)

+#define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)           /*!< 0x00000008 */

+#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk

+#define DCMI_MIS_LINE_MIS_Pos      (4U)

+#define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)            /*!< 0x00000010 */

+#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk

+

+

+/********************  Bits definition for DCMI_ICR register  *****************/

+#define DCMI_ICR_FRAME_ISC_Pos     (0U)

+#define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)           /*!< 0x00000001 */

+#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk

+#define DCMI_ICR_OVR_ISC_Pos       (1U)

+#define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)             /*!< 0x00000002 */

+#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk

+#define DCMI_ICR_ERR_ISC_Pos       (2U)

+#define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)             /*!< 0x00000004 */

+#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk

+#define DCMI_ICR_VSYNC_ISC_Pos     (3U)

+#define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)           /*!< 0x00000008 */

+#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk

+#define DCMI_ICR_LINE_ISC_Pos      (4U)

+#define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)            /*!< 0x00000010 */

+#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk

+

+

+/********************  Bits definition for DCMI_ESCR register  ******************/

+#define DCMI_ESCR_FSC_Pos          (0U)

+#define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)               /*!< 0x000000FF */

+#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk

+#define DCMI_ESCR_LSC_Pos          (8U)

+#define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)               /*!< 0x0000FF00 */

+#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk

+#define DCMI_ESCR_LEC_Pos          (16U)

+#define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)               /*!< 0x00FF0000 */

+#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk

+#define DCMI_ESCR_FEC_Pos          (24U)

+#define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)               /*!< 0xFF000000 */

+#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk

+

+/********************  Bits definition for DCMI_ESUR register  ******************/

+#define DCMI_ESUR_FSU_Pos          (0U)

+#define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)               /*!< 0x000000FF */

+#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk

+#define DCMI_ESUR_LSU_Pos          (8U)

+#define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)               /*!< 0x0000FF00 */

+#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk

+#define DCMI_ESUR_LEU_Pos          (16U)

+#define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)               /*!< 0x00FF0000 */

+#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk

+#define DCMI_ESUR_FEU_Pos          (24U)

+#define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)               /*!< 0xFF000000 */

+#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk

+

+/********************  Bits definition for DCMI_CWSTRT register  ******************/

+#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)

+#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)       /*!< 0x00003FFF */

+#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk

+#define DCMI_CWSTRT_VST_Pos        (16U)

+#define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)           /*!< 0x1FFF0000 */

+#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk

+

+/********************  Bits definition for DCMI_CWSIZE register  ******************/

+#define DCMI_CWSIZE_CAPCNT_Pos     (0U)

+#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)        /*!< 0x00003FFF */

+#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk

+#define DCMI_CWSIZE_VLINE_Pos      (16U)

+#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)         /*!< 0x3FFF0000 */

+#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk

+

+/********************  Bits definition for DCMI_DR register  ******************/

+#define DCMI_DR_BYTE0_Pos          (0U)

+#define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)               /*!< 0x000000FF */

+#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk

+#define DCMI_DR_BYTE1_Pos          (8U)

+#define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)               /*!< 0x0000FF00 */

+#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk

+#define DCMI_DR_BYTE2_Pos          (16U)

+#define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)               /*!< 0x00FF0000 */

+#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk

+#define DCMI_DR_BYTE3_Pos          (24U)

+#define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)               /*!< 0xFF000000 */

+#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                 Digital Filter for Sigma Delta Modulators                  */

+/*                                                                            */

+/******************************************************************************/

+

+/****************   DFSDM channel configuration registers  ********************/

+

+/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/

+#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)

+#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)   /*!< 0x80000000 */

+#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */

+#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)

+#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)  /*!< 0x40000000 */

+#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */

+#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)

+#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */

+#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */

+#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)

+#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x0000C000 */

+#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */

+#define DFSDM_CHCFGR1_DATPACK_1         (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */

+#define DFSDM_CHCFGR1_DATPACK_0         (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */

+#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)

+#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00003000 */

+#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */

+#define DFSDM_CHCFGR1_DATMPX_1          (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */

+#define DFSDM_CHCFGR1_DATMPX_0          (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */

+#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)

+#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)   /*!< 0x00000100 */

+#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */

+#define DFSDM_CHCFGR1_CHEN_Pos          (7U)

+#define DFSDM_CHCFGR1_CHEN_Msk          (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)      /*!< 0x00000080 */

+#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */

+#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)

+#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)    /*!< 0x00000040 */

+#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */

+#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)

+#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)     /*!< 0x00000020 */

+#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */

+#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)

+#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x0000000C */

+#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */

+#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */

+#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */

+#define DFSDM_CHCFGR1_SITP_Pos          (0U)

+#define DFSDM_CHCFGR1_SITP_Msk          (0x3UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000003 */

+#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */

+#define DFSDM_CHCFGR1_SITP_1            (0x2UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */

+#define DFSDM_CHCFGR1_SITP_0            (0x1UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */

+

+/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/

+#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)

+#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */

+#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)

+#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)    /*!< 0x000000F8 */

+#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */

+

+/******************  Bit definition for DFSDM_CHAWSCDR register *****************/

+#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)

+#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00C00000 */

+#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */

+#define DFSDM_CHAWSCDR_AWFORD_1         (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */

+#define DFSDM_CHAWSCDR_AWFORD_0         (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */

+#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)

+#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)  /*!< 0x001F0000 */

+#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */

+#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)

+#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)    /*!< 0x0000F000 */

+#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */

+#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)

+#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)    /*!< 0x000000FF */

+#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */

+

+/****************  Bit definition for DFSDM_CHWDATR register *******************/

+#define DFSDM_CHWDATR_WDATA_Pos         (0U)

+#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)  /*!< 0x0000FFFF */

+#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */

+

+/****************  Bit definition for DFSDM_CHDATINR register *****************/

+#define DFSDM_CHDATINR_INDAT0_Pos       (0U)

+#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */

+#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */

+#define DFSDM_CHDATINR_INDAT1_Pos       (16U)

+#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */

+#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */

+

+/************************   DFSDM module registers  ****************************/

+

+/********************  Bit definition for DFSDM_FLTCR1 register *******************/

+#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)

+#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)     /*!< 0x40000000 */

+#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */

+#define DFSDM_FLTCR1_FAST_Pos           (29U)

+#define DFSDM_FLTCR1_FAST_Msk           (0x1UL << DFSDM_FLTCR1_FAST_Pos)       /*!< 0x20000000 */

+#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */

+#define DFSDM_FLTCR1_RCH_Pos            (24U)

+#define DFSDM_FLTCR1_RCH_Msk            (0x7UL << DFSDM_FLTCR1_RCH_Pos)        /*!< 0x07000000 */

+#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */

+#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)

+#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)     /*!< 0x00200000 */

+#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */

+#define DFSDM_FLTCR1_RSYNC_Pos          (19U)

+#define DFSDM_FLTCR1_RSYNC_Msk          (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)      /*!< 0x00080000 */

+#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */

+#define DFSDM_FLTCR1_RCONT_Pos          (18U)

+#define DFSDM_FLTCR1_RCONT_Msk          (0x1UL << DFSDM_FLTCR1_RCONT_Pos)      /*!< 0x00040000 */

+#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */

+#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)

+#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)   /*!< 0x00020000 */

+#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */

+#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)

+#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00006000 */

+#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */

+#define DFSDM_FLTCR1_JEXTEN_1           (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */

+#define DFSDM_FLTCR1_JEXTEN_0           (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */

+#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)

+#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)   /*!< 0x00001F00 */

+#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */

+#define DFSDM_FLTCR1_JEXTSEL_0          (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000100 */

+#define DFSDM_FLTCR1_JEXTSEL_1          (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000200 */

+#define DFSDM_FLTCR1_JEXTSEL_2          (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000400 */

+#define DFSDM_FLTCR1_JEXTSEL_3          (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000800 */

+#define DFSDM_FLTCR1_JEXTSEL_4          (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00001000 */

+

+#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)

+#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)     /*!< 0x00000020 */

+#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */

+#define DFSDM_FLTCR1_JSCAN_Pos          (4U)

+#define DFSDM_FLTCR1_JSCAN_Msk          (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)      /*!< 0x00000010 */

+#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */

+#define DFSDM_FLTCR1_JSYNC_Pos          (3U)

+#define DFSDM_FLTCR1_JSYNC_Msk          (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)      /*!< 0x00000008 */

+#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */

+#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)

+#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)   /*!< 0x00000002 */

+#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */

+#define DFSDM_FLTCR1_DFEN_Pos           (0U)

+#define DFSDM_FLTCR1_DFEN_Msk           (0x1UL << DFSDM_FLTCR1_DFEN_Pos)       /*!< 0x00000001 */

+#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */

+

+/********************  Bit definition for DFSDM_FLTCR2 register *******************/

+#define DFSDM_FLTCR2_AWDCH_Pos          (16U)

+#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)     /*!< 0x00FF0000 */

+#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */

+#define DFSDM_FLTCR2_EXCH_Pos           (8U)

+#define DFSDM_FLTCR2_EXCH_Msk           (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)      /*!< 0x0000FF00 */

+#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */

+#define DFSDM_FLTCR2_CKABIE_Pos         (6U)

+#define DFSDM_FLTCR2_CKABIE_Msk         (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)     /*!< 0x00000040 */

+#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */

+#define DFSDM_FLTCR2_SCDIE_Pos          (5U)

+#define DFSDM_FLTCR2_SCDIE_Msk          (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)      /*!< 0x00000020 */

+#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */

+#define DFSDM_FLTCR2_AWDIE_Pos          (4U)

+#define DFSDM_FLTCR2_AWDIE_Msk          (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)      /*!< 0x00000010 */

+#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */

+#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)

+#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)     /*!< 0x00000008 */

+#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */

+#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)

+#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)     /*!< 0x00000004 */

+#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */

+#define DFSDM_FLTCR2_REOCIE_Pos         (1U)

+#define DFSDM_FLTCR2_REOCIE_Msk         (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)     /*!< 0x00000002 */

+#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */

+#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)

+#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)     /*!< 0x00000001 */

+#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */

+

+/********************  Bit definition for DFSDM_FLTISR register *******************/

+#define DFSDM_FLTISR_SCDF_Pos           (24U)

+#define DFSDM_FLTISR_SCDF_Msk           (0xFFUL << DFSDM_FLTISR_SCDF_Pos)      /*!< 0xFF000000 */

+#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */

+#define DFSDM_FLTISR_CKABF_Pos          (16U)

+#define DFSDM_FLTISR_CKABF_Msk          (0xFFUL << DFSDM_FLTISR_CKABF_Pos)     /*!< 0x00FF0000 */

+#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */

+#define DFSDM_FLTISR_RCIP_Pos           (14U)

+#define DFSDM_FLTISR_RCIP_Msk           (0x1UL << DFSDM_FLTISR_RCIP_Pos)       /*!< 0x00004000 */

+#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */

+#define DFSDM_FLTISR_JCIP_Pos           (13U)

+#define DFSDM_FLTISR_JCIP_Msk           (0x1UL << DFSDM_FLTISR_JCIP_Pos)       /*!< 0x00002000 */

+#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */

+#define DFSDM_FLTISR_AWDF_Pos           (4U)

+#define DFSDM_FLTISR_AWDF_Msk           (0x1UL << DFSDM_FLTISR_AWDF_Pos)       /*!< 0x00000010 */

+#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */

+#define DFSDM_FLTISR_ROVRF_Pos          (3U)

+#define DFSDM_FLTISR_ROVRF_Msk          (0x1UL << DFSDM_FLTISR_ROVRF_Pos)      /*!< 0x00000008 */

+#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */

+#define DFSDM_FLTISR_JOVRF_Pos          (2U)

+#define DFSDM_FLTISR_JOVRF_Msk          (0x1UL << DFSDM_FLTISR_JOVRF_Pos)      /*!< 0x00000004 */

+#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */

+#define DFSDM_FLTISR_REOCF_Pos          (1U)

+#define DFSDM_FLTISR_REOCF_Msk          (0x1UL << DFSDM_FLTISR_REOCF_Pos)      /*!< 0x00000002 */

+#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */

+#define DFSDM_FLTISR_JEOCF_Pos          (0U)

+#define DFSDM_FLTISR_JEOCF_Msk          (0x1UL << DFSDM_FLTISR_JEOCF_Pos)      /*!< 0x00000001 */

+#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */

+

+/********************  Bit definition for DFSDM_FLTICR register *******************/

+#define DFSDM_FLTICR_CLRSCDF_Pos        (24U)

+#define DFSDM_FLTICR_CLRSCDF_Msk        (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)   /*!< 0xFF000000 */

+#define DFSDM_FLTICR_CLRSCDF            DFSDM_FLTICR_CLRSCDF_Msk               /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */

+#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)

+#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)  /*!< 0x00FF0000 */

+#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */

+#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)

+#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)   /*!< 0x00000008 */

+#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */

+#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)

+#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)   /*!< 0x00000004 */

+#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */

+

+/*******************  Bit definition for DFSDM_FLTJCHGR register ******************/

+#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)

+#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)    /*!< 0x000000FF */

+#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */

+

+/********************  Bit definition for DFSDM_FLTFCR register *******************/

+#define DFSDM_FLTFCR_FORD_Pos           (29U)

+#define DFSDM_FLTFCR_FORD_Msk           (0x7UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0xE0000000 */

+#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */

+#define DFSDM_FLTFCR_FORD_2             (0x4UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */

+#define DFSDM_FLTFCR_FORD_1             (0x2UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */

+#define DFSDM_FLTFCR_FORD_0             (0x1UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */

+#define DFSDM_FLTFCR_FOSR_Pos           (16U)

+#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)     /*!< 0x03FF0000 */

+#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */

+#define DFSDM_FLTFCR_IOSR_Pos           (0U)

+#define DFSDM_FLTFCR_IOSR_Msk           (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)      /*!< 0x000000FF */

+#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */

+

+/******************  Bit definition for DFSDM_FLTJDATAR register *****************/

+#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)

+#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */

+#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)

+#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */

+#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */

+

+/******************  Bit definition for DFSDM_FLTRDATAR register *****************/

+#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)

+#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */

+#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)

+#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)   /*!< 0x00000010 */

+#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */

+#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)

+#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */

+#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */

+

+/******************  Bit definition for DFSDM_FLTAWHTR register ******************/

+#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)

+#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */

+#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)

+#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)    /*!< 0x0000000F */

+#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */

+

+/******************  Bit definition for DFSDM_FLTAWLTR register ******************/

+#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)

+#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWHT[23:0] Analog watchdog low threshold */

+#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)

+#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)    /*!< 0x0000000F */

+#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */

+

+/******************  Bit definition for DFSDM_FLTAWSR register ******************/

+#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)

+#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)    /*!< 0x0000FF00 */

+#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */

+#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)

+#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)    /*!< 0x000000FF */

+#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */

+

+/******************  Bit definition for DFSDM_FLTAWCFR) register *****************/

+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)

+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */

+#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */

+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)

+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */

+#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */

+

+/******************  Bit definition for DFSDM_FLTEXMAX register ******************/

+#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)

+#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */

+#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)

+#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)  /*!< 0x00000007 */

+#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */

+

+/******************  Bit definition for DFSDM_FLTEXMIN register ******************/

+#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)

+#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */

+#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)

+#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)  /*!< 0x00000007 */

+#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */

+

+/******************  Bit definition for DFSDM_FLTCNVTIMR register ******************/

+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)

+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */

+#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           BDMA Controller                                  */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for BDMA_ISR register  ********************/

+#define BDMA_ISR_GIF0_Pos       (0U)

+#define BDMA_ISR_GIF0_Msk       (0x1UL << BDMA_ISR_GIF0_Pos)                   /*!< 0x00000001 */

+#define BDMA_ISR_GIF0           BDMA_ISR_GIF0_Msk                              /*!< Channel 0 Global interrupt flag */

+#define BDMA_ISR_TCIF0_Pos      (1U)

+#define BDMA_ISR_TCIF0_Msk      (0x1UL << BDMA_ISR_TCIF0_Pos)                  /*!< 0x00000002 */

+#define BDMA_ISR_TCIF0          BDMA_ISR_TCIF0_Msk                             /*!< Channel 0 Transfer Complete flag */

+#define BDMA_ISR_HTIF0_Pos      (2U)

+#define BDMA_ISR_HTIF0_Msk      (0x1UL << BDMA_ISR_HTIF0_Pos)                  /*!< 0x00000004 */

+#define BDMA_ISR_HTIF0          BDMA_ISR_HTIF0_Msk                             /*!< Channel 0 Half Transfer flag */

+#define BDMA_ISR_TEIF0_Pos      (3U)

+#define BDMA_ISR_TEIF0_Msk      (0x1UL << BDMA_ISR_TEIF0_Pos)                  /*!< 0x00000008 */

+#define BDMA_ISR_TEIF0          BDMA_ISR_TEIF0_Msk                             /*!< Channel 0 Transfer Error flag */

+#define BDMA_ISR_GIF1_Pos       (4U)

+#define BDMA_ISR_GIF1_Msk       (0x1UL << BDMA_ISR_GIF1_Pos)                   /*!< 0x00000010 */

+#define BDMA_ISR_GIF1           BDMA_ISR_GIF1_Msk                              /*!< Channel 1 Global interrupt flag */

+#define BDMA_ISR_TCIF1_Pos      (5U)

+#define BDMA_ISR_TCIF1_Msk      (0x1UL << BDMA_ISR_TCIF1_Pos)                  /*!< 0x00000020 */

+#define BDMA_ISR_TCIF1          BDMA_ISR_TCIF1_Msk                             /*!< Channel 1 Transfer Complete flag */

+#define BDMA_ISR_HTIF1_Pos      (6U)

+#define BDMA_ISR_HTIF1_Msk      (0x1UL << BDMA_ISR_HTIF1_Pos)                  /*!< 0x00000040 */

+#define BDMA_ISR_HTIF1          BDMA_ISR_HTIF1_Msk                             /*!< Channel 1 Half Transfer flag */

+#define BDMA_ISR_TEIF1_Pos      (7U)

+#define BDMA_ISR_TEIF1_Msk      (0x1UL << BDMA_ISR_TEIF1_Pos)                  /*!< 0x00000080 */

+#define BDMA_ISR_TEIF1          BDMA_ISR_TEIF1_Msk                             /*!< Channel 1 Transfer Error flag */

+#define BDMA_ISR_GIF2_Pos       (8U)

+#define BDMA_ISR_GIF2_Msk       (0x1UL << BDMA_ISR_GIF2_Pos)                   /*!< 0x00000100 */

+#define BDMA_ISR_GIF2           BDMA_ISR_GIF2_Msk                              /*!< Channel 2 Global interrupt flag */

+#define BDMA_ISR_TCIF2_Pos      (9U)

+#define BDMA_ISR_TCIF2_Msk      (0x1UL << BDMA_ISR_TCIF2_Pos)                  /*!< 0x00000200 */

+#define BDMA_ISR_TCIF2          BDMA_ISR_TCIF2_Msk                             /*!< Channel 2 Transfer Complete flag */

+#define BDMA_ISR_HTIF2_Pos      (10U)

+#define BDMA_ISR_HTIF2_Msk      (0x1UL << BDMA_ISR_HTIF2_Pos)                  /*!< 0x00000400 */

+#define BDMA_ISR_HTIF2          BDMA_ISR_HTIF2_Msk                             /*!< Channel 2 Half Transfer flag */

+#define BDMA_ISR_TEIF2_Pos      (11U)

+#define BDMA_ISR_TEIF2_Msk      (0x1UL << BDMA_ISR_TEIF2_Pos)                  /*!< 0x00000800 */

+#define BDMA_ISR_TEIF2          BDMA_ISR_TEIF2_Msk                             /*!< Channel 2 Transfer Error flag */

+#define BDMA_ISR_GIF3_Pos       (12U)

+#define BDMA_ISR_GIF3_Msk       (0x1UL << BDMA_ISR_GIF3_Pos)                   /*!< 0x00001000 */

+#define BDMA_ISR_GIF3           BDMA_ISR_GIF3_Msk                              /*!< Channel 3 Global interrupt flag */

+#define BDMA_ISR_TCIF3_Pos      (13U)

+#define BDMA_ISR_TCIF3_Msk      (0x1UL << BDMA_ISR_TCIF3_Pos)                  /*!< 0x00002000 */

+#define BDMA_ISR_TCIF3          BDMA_ISR_TCIF3_Msk                             /*!< Channel 3 Transfer Complete flag */

+#define BDMA_ISR_HTIF3_Pos      (14U)

+#define BDMA_ISR_HTIF3_Msk      (0x1UL << BDMA_ISR_HTIF3_Pos)                  /*!< 0x00004000 */

+#define BDMA_ISR_HTIF3          BDMA_ISR_HTIF3_Msk                             /*!< Channel 3 Half Transfer flag */

+#define BDMA_ISR_TEIF3_Pos      (15U)

+#define BDMA_ISR_TEIF3_Msk      (0x1UL << BDMA_ISR_TEIF3_Pos)                  /*!< 0x00008000 */

+#define BDMA_ISR_TEIF3          BDMA_ISR_TEIF3_Msk                             /*!< Channel 3 Transfer Error flag */

+#define BDMA_ISR_GIF4_Pos       (16U)

+#define BDMA_ISR_GIF4_Msk       (0x1UL << BDMA_ISR_GIF4_Pos)                   /*!< 0x00010000 */

+#define BDMA_ISR_GIF4           BDMA_ISR_GIF4_Msk                              /*!< Channel 4 Global interrupt flag */

+#define BDMA_ISR_TCIF4_Pos      (17U)

+#define BDMA_ISR_TCIF4_Msk      (0x1UL << BDMA_ISR_TCIF4_Pos)                  /*!< 0x00020000 */

+#define BDMA_ISR_TCIF4          BDMA_ISR_TCIF4_Msk                             /*!< Channel 4 Transfer Complete flag */

+#define BDMA_ISR_HTIF4_Pos      (18U)

+#define BDMA_ISR_HTIF4_Msk      (0x1UL << BDMA_ISR_HTIF4_Pos)                  /*!< 0x00040000 */

+#define BDMA_ISR_HTIF4          BDMA_ISR_HTIF4_Msk                             /*!< Channel 4 Half Transfer flag */

+#define BDMA_ISR_TEIF4_Pos      (19U)

+#define BDMA_ISR_TEIF4_Msk      (0x1UL << BDMA_ISR_TEIF4_Pos)                  /*!< 0x00080000 */

+#define BDMA_ISR_TEIF4          BDMA_ISR_TEIF4_Msk                             /*!< Channel 4 Transfer Error flag */

+#define BDMA_ISR_GIF5_Pos       (20U)

+#define BDMA_ISR_GIF5_Msk       (0x1UL << BDMA_ISR_GIF5_Pos)                   /*!< 0x00100000 */

+#define BDMA_ISR_GIF5           BDMA_ISR_GIF5_Msk                              /*!< Channel 5 Global interrupt flag */

+#define BDMA_ISR_TCIF5_Pos      (21U)

+#define BDMA_ISR_TCIF5_Msk      (0x1UL << BDMA_ISR_TCIF5_Pos)                  /*!< 0x00200000 */

+#define BDMA_ISR_TCIF5          BDMA_ISR_TCIF5_Msk                             /*!< Channel 5 Transfer Complete flag */

+#define BDMA_ISR_HTIF5_Pos      (22U)

+#define BDMA_ISR_HTIF5_Msk      (0x1UL << BDMA_ISR_HTIF5_Pos)                  /*!< 0x00400000 */

+#define BDMA_ISR_HTIF5          BDMA_ISR_HTIF5_Msk                             /*!< Channel 5 Half Transfer flag */

+#define BDMA_ISR_TEIF5_Pos      (23U)

+#define BDMA_ISR_TEIF5_Msk      (0x1UL << BDMA_ISR_TEIF5_Pos)                  /*!< 0x00800000 */

+#define BDMA_ISR_TEIF5          BDMA_ISR_TEIF5_Msk                             /*!< Channel 5 Transfer Error flag */

+#define BDMA_ISR_GIF6_Pos       (24U)

+#define BDMA_ISR_GIF6_Msk       (0x1UL << BDMA_ISR_GIF6_Pos)                   /*!< 0x01000000 */

+#define BDMA_ISR_GIF6           BDMA_ISR_GIF6_Msk                              /*!< Channel 6 Global interrupt flag */

+#define BDMA_ISR_TCIF6_Pos      (25U)

+#define BDMA_ISR_TCIF6_Msk      (0x1UL << BDMA_ISR_TCIF6_Pos)                  /*!< 0x02000000 */

+#define BDMA_ISR_TCIF6          BDMA_ISR_TCIF6_Msk                             /*!< Channel 6 Transfer Complete flag */

+#define BDMA_ISR_HTIF6_Pos      (26U)

+#define BDMA_ISR_HTIF6_Msk      (0x1UL << BDMA_ISR_HTIF6_Pos)                  /*!< 0x04000000 */

+#define BDMA_ISR_HTIF6          BDMA_ISR_HTIF6_Msk                             /*!< Channel 6 Half Transfer flag */

+#define BDMA_ISR_TEIF6_Pos      (27U)

+#define BDMA_ISR_TEIF6_Msk      (0x1UL << BDMA_ISR_TEIF6_Pos)                  /*!< 0x08000000 */

+#define BDMA_ISR_TEIF6          BDMA_ISR_TEIF6_Msk                             /*!< Channel 6 Transfer Error flag */

+#define BDMA_ISR_GIF7_Pos       (28U)

+#define BDMA_ISR_GIF7_Msk       (0x1UL << BDMA_ISR_GIF7_Pos)                   /*!< 0x10000000 */

+#define BDMA_ISR_GIF7           BDMA_ISR_GIF7_Msk                              /*!< Channel 7 Global interrupt flag */

+#define BDMA_ISR_TCIF7_Pos      (29U)

+#define BDMA_ISR_TCIF7_Msk      (0x1UL << BDMA_ISR_TCIF7_Pos)                  /*!< 0x20000000 */

+#define BDMA_ISR_TCIF7          BDMA_ISR_TCIF7_Msk                             /*!< Channel 7 Transfer Complete flag */

+#define BDMA_ISR_HTIF7_Pos      (30U)

+#define BDMA_ISR_HTIF7_Msk      (0x1UL << BDMA_ISR_HTIF7_Pos)                  /*!< 0x40000000 */

+#define BDMA_ISR_HTIF7          BDMA_ISR_HTIF7_Msk                             /*!< Channel 7 Half Transfer flag */

+#define BDMA_ISR_TEIF7_Pos      (31U)

+#define BDMA_ISR_TEIF7_Msk      (0x1UL << BDMA_ISR_TEIF7_Pos)                  /*!< 0x80000000 */

+#define BDMA_ISR_TEIF7          BDMA_ISR_TEIF7_Msk                             /*!< Channel 7 Transfer Error flag */

+

+/*******************  Bit definition for BDMA_IFCR register  *******************/

+#define BDMA_IFCR_CGIF0_Pos     (0U)

+#define BDMA_IFCR_CGIF0_Msk     (0x1UL << BDMA_IFCR_CGIF0_Pos)                 /*!< 0x00000001 */

+#define BDMA_IFCR_CGIF0         BDMA_IFCR_CGIF0_Msk                            /*!< Channel 0 Global interrupt clearr */

+#define BDMA_IFCR_CTCIF0_Pos    (1U)

+#define BDMA_IFCR_CTCIF0_Msk    (0x1UL << BDMA_IFCR_CTCIF0_Pos)                /*!< 0x00000002 */

+#define BDMA_IFCR_CTCIF0        BDMA_IFCR_CTCIF0_Msk                           /*!< Channel 0 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF0_Pos    (2U)

+#define BDMA_IFCR_CHTIF0_Msk    (0x1UL << BDMA_IFCR_CHTIF0_Pos)                /*!< 0x00000004 */

+#define BDMA_IFCR_CHTIF0        BDMA_IFCR_CHTIF0_Msk                           /*!< Channel 0 Half Transfer clear */

+#define BDMA_IFCR_CTEIF0_Pos    (3U)

+#define BDMA_IFCR_CTEIF0_Msk    (0x1UL << BDMA_IFCR_CTEIF0_Pos)                /*!< 0x00000008 */

+#define BDMA_IFCR_CTEIF0        BDMA_IFCR_CTEIF0_Msk                           /*!< Channel 0 Transfer Error clear */

+#define BDMA_IFCR_CGIF1_Pos     (4U)

+#define BDMA_IFCR_CGIF1_Msk     (0x1UL << BDMA_IFCR_CGIF1_Pos)                 /*!< 0x00000010 */

+#define BDMA_IFCR_CGIF1         BDMA_IFCR_CGIF1_Msk                            /*!< Channel 1 Global interrupt clear */

+#define BDMA_IFCR_CTCIF1_Pos    (5U)

+#define BDMA_IFCR_CTCIF1_Msk    (0x1UL << BDMA_IFCR_CTCIF1_Pos)                /*!< 0x00000020 */

+#define BDMA_IFCR_CTCIF1        BDMA_IFCR_CTCIF1_Msk                           /*!< Channel 1 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF1_Pos    (6U)

+#define BDMA_IFCR_CHTIF1_Msk    (0x1UL << BDMA_IFCR_CHTIF1_Pos)                /*!< 0x00000040 */

+#define BDMA_IFCR_CHTIF1        BDMA_IFCR_CHTIF1_Msk                           /*!< Channel 1 Half Transfer clear */

+#define BDMA_IFCR_CTEIF1_Pos    (7U)

+#define BDMA_IFCR_CTEIF1_Msk    (0x1UL << BDMA_IFCR_CTEIF1_Pos)                /*!< 0x00000080 */

+#define BDMA_IFCR_CTEIF1        BDMA_IFCR_CTEIF1_Msk                           /*!< Channel 1 Transfer Error clear */

+#define BDMA_IFCR_CGIF2_Pos     (8U)

+#define BDMA_IFCR_CGIF2_Msk     (0x1UL << BDMA_IFCR_CGIF2_Pos)                 /*!< 0x00000100 */

+#define BDMA_IFCR_CGIF2         BDMA_IFCR_CGIF2_Msk                            /*!< Channel 2 Global interrupt clear */

+#define BDMA_IFCR_CTCIF2_Pos    (9U)

+#define BDMA_IFCR_CTCIF2_Msk    (0x1UL << BDMA_IFCR_CTCIF2_Pos)                /*!< 0x00000200 */

+#define BDMA_IFCR_CTCIF2        BDMA_IFCR_CTCIF2_Msk                           /*!< Channel 2 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF2_Pos    (10U)

+#define BDMA_IFCR_CHTIF2_Msk    (0x1UL << BDMA_IFCR_CHTIF2_Pos)                /*!< 0x00000400 */

+#define BDMA_IFCR_CHTIF2        BDMA_IFCR_CHTIF2_Msk                           /*!< Channel 2 Half Transfer clear */

+#define BDMA_IFCR_CTEIF2_Pos    (11U)

+#define BDMA_IFCR_CTEIF2_Msk    (0x1UL << BDMA_IFCR_CTEIF2_Pos)                /*!< 0x00000800 */

+#define BDMA_IFCR_CTEIF2        BDMA_IFCR_CTEIF2_Msk                           /*!< Channel 2 Transfer Error clear */

+#define BDMA_IFCR_CGIF3_Pos     (12U)

+#define BDMA_IFCR_CGIF3_Msk     (0x1UL << BDMA_IFCR_CGIF3_Pos)                 /*!< 0x00001000 */

+#define BDMA_IFCR_CGIF3         BDMA_IFCR_CGIF3_Msk                            /*!< Channel 3 Global interrupt clear */

+#define BDMA_IFCR_CTCIF3_Pos    (13U)

+#define BDMA_IFCR_CTCIF3_Msk    (0x1UL << BDMA_IFCR_CTCIF3_Pos)                /*!< 0x00002000 */

+#define BDMA_IFCR_CTCIF3        BDMA_IFCR_CTCIF3_Msk                           /*!< Channel 3 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF3_Pos    (14U)

+#define BDMA_IFCR_CHTIF3_Msk    (0x1UL << BDMA_IFCR_CHTIF3_Pos)                /*!< 0x00004000 */

+#define BDMA_IFCR_CHTIF3        BDMA_IFCR_CHTIF3_Msk                           /*!< Channel 3 Half Transfer clear */

+#define BDMA_IFCR_CTEIF3_Pos    (15U)

+#define BDMA_IFCR_CTEIF3_Msk    (0x1UL << BDMA_IFCR_CTEIF3_Pos)                /*!< 0x00008000 */

+#define BDMA_IFCR_CTEIF3        BDMA_IFCR_CTEIF3_Msk                           /*!< Channel 3 Transfer Error clear */

+#define BDMA_IFCR_CGIF4_Pos     (16U)

+#define BDMA_IFCR_CGIF4_Msk     (0x1UL << BDMA_IFCR_CGIF4_Pos)                 /*!< 0x00010000 */

+#define BDMA_IFCR_CGIF4         BDMA_IFCR_CGIF4_Msk                            /*!< Channel 4 Global interrupt clear */

+#define BDMA_IFCR_CTCIF4_Pos    (17U)

+#define BDMA_IFCR_CTCIF4_Msk    (0x1UL << BDMA_IFCR_CTCIF4_Pos)                /*!< 0x00020000 */

+#define BDMA_IFCR_CTCIF4        BDMA_IFCR_CTCIF4_Msk                           /*!< Channel 4 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF4_Pos    (18U)

+#define BDMA_IFCR_CHTIF4_Msk    (0x1UL << BDMA_IFCR_CHTIF4_Pos)                /*!< 0x00040000 */

+#define BDMA_IFCR_CHTIF4        BDMA_IFCR_CHTIF4_Msk                           /*!< Channel 4 Half Transfer clear */

+#define BDMA_IFCR_CTEIF4_Pos    (19U)

+#define BDMA_IFCR_CTEIF4_Msk    (0x1UL << BDMA_IFCR_CTEIF4_Pos)                /*!< 0x00080000 */

+#define BDMA_IFCR_CTEIF4        BDMA_IFCR_CTEIF4_Msk                           /*!< Channel 4 Transfer Error clear */

+#define BDMA_IFCR_CGIF5_Pos     (20U)

+#define BDMA_IFCR_CGIF5_Msk     (0x1UL << BDMA_IFCR_CGIF5_Pos)                 /*!< 0x00100000 */

+#define BDMA_IFCR_CGIF5         BDMA_IFCR_CGIF5_Msk                            /*!< Channel 5 Global interrupt clear */

+#define BDMA_IFCR_CTCIF5_Pos    (21U)

+#define BDMA_IFCR_CTCIF5_Msk    (0x1UL << BDMA_IFCR_CTCIF5_Pos)                /*!< 0x00200000 */

+#define BDMA_IFCR_CTCIF5        BDMA_IFCR_CTCIF5_Msk                           /*!< Channel 5 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF5_Pos    (22U)

+#define BDMA_IFCR_CHTIF5_Msk    (0x1UL << BDMA_IFCR_CHTIF5_Pos)                /*!< 0x00400000 */

+#define BDMA_IFCR_CHTIF5        BDMA_IFCR_CHTIF5_Msk                           /*!< Channel 5 Half Transfer clear */

+#define BDMA_IFCR_CTEIF5_Pos    (23U)

+#define BDMA_IFCR_CTEIF5_Msk    (0x1UL << BDMA_IFCR_CTEIF5_Pos)                /*!< 0x00800000 */

+#define BDMA_IFCR_CTEIF5        BDMA_IFCR_CTEIF5_Msk                           /*!< Channel 5 Transfer Error clear */

+#define BDMA_IFCR_CGIF6_Pos     (24U)

+#define BDMA_IFCR_CGIF6_Msk     (0x1UL << BDMA_IFCR_CGIF6_Pos)                 /*!< 0x01000000 */

+#define BDMA_IFCR_CGIF6         BDMA_IFCR_CGIF6_Msk                            /*!< Channel 6 Global interrupt clear */

+#define BDMA_IFCR_CTCIF6_Pos    (25U)

+#define BDMA_IFCR_CTCIF6_Msk    (0x1UL << BDMA_IFCR_CTCIF6_Pos)                /*!< 0x02000000 */

+#define BDMA_IFCR_CTCIF6        BDMA_IFCR_CTCIF6_Msk                           /*!< Channel 6 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF6_Pos    (26U)

+#define BDMA_IFCR_CHTIF6_Msk    (0x1UL << BDMA_IFCR_CHTIF6_Pos)                /*!< 0x04000000 */

+#define BDMA_IFCR_CHTIF6        BDMA_IFCR_CHTIF6_Msk                           /*!< Channel 6 Half Transfer clear */

+#define BDMA_IFCR_CTEIF6_Pos    (27U)

+#define BDMA_IFCR_CTEIF6_Msk    (0x1UL << BDMA_IFCR_CTEIF6_Pos)                /*!< 0x08000000 */

+#define BDMA_IFCR_CTEIF6        BDMA_IFCR_CTEIF6_Msk                           /*!< Channel 6 Transfer Error clear */

+#define BDMA_IFCR_CGIF7_Pos     (28U)

+#define BDMA_IFCR_CGIF7_Msk     (0x1UL << BDMA_IFCR_CGIF7_Pos)                 /*!< 0x10000000 */

+#define BDMA_IFCR_CGIF7         BDMA_IFCR_CGIF7_Msk                            /*!< Channel 7 Global interrupt clear */

+#define BDMA_IFCR_CTCIF7_Pos    (29U)

+#define BDMA_IFCR_CTCIF7_Msk    (0x1UL << BDMA_IFCR_CTCIF7_Pos)                /*!< 0x20000000 */

+#define BDMA_IFCR_CTCIF7        BDMA_IFCR_CTCIF7_Msk                           /*!< Channel 7 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF7_Pos    (30U)

+#define BDMA_IFCR_CHTIF7_Msk    (0x1UL << BDMA_IFCR_CHTIF7_Pos)                /*!< 0x40000000 */

+#define BDMA_IFCR_CHTIF7        BDMA_IFCR_CHTIF7_Msk                           /*!< Channel 7 Half Transfer clear */

+#define BDMA_IFCR_CTEIF7_Pos    (31U)

+#define BDMA_IFCR_CTEIF7_Msk    (0x1UL << BDMA_IFCR_CTEIF7_Pos)                /*!< 0x80000000 */

+#define BDMA_IFCR_CTEIF7        BDMA_IFCR_CTEIF7_Msk                           /*!< Channel 7 Transfer Error clear */

+

+/*******************  Bit definition for BDMA_CCR register  ********************/

+#define BDMA_CCR_EN_Pos         (0U)

+#define BDMA_CCR_EN_Msk         (0x1UL << BDMA_CCR_EN_Pos)                     /*!< 0x00000001 */

+#define BDMA_CCR_EN             BDMA_CCR_EN_Msk                                /*!< Channel enable                      */

+#define BDMA_CCR_TCIE_Pos       (1U)

+#define BDMA_CCR_TCIE_Msk       (0x1UL << BDMA_CCR_TCIE_Pos)                   /*!< 0x00000002 */

+#define BDMA_CCR_TCIE           BDMA_CCR_TCIE_Msk                              /*!< Transfer complete interrupt enable  */

+#define BDMA_CCR_HTIE_Pos       (2U)

+#define BDMA_CCR_HTIE_Msk       (0x1UL << BDMA_CCR_HTIE_Pos)                   /*!< 0x00000004 */

+#define BDMA_CCR_HTIE           BDMA_CCR_HTIE_Msk                              /*!< Half Transfer interrupt enable      */

+#define BDMA_CCR_TEIE_Pos       (3U)

+#define BDMA_CCR_TEIE_Msk       (0x1UL << BDMA_CCR_TEIE_Pos)                   /*!< 0x00000008 */

+#define BDMA_CCR_TEIE           BDMA_CCR_TEIE_Msk                              /*!< Transfer error interrupt enable     */

+#define BDMA_CCR_DIR_Pos        (4U)

+#define BDMA_CCR_DIR_Msk        (0x1UL << BDMA_CCR_DIR_Pos)                    /*!< 0x00000010 */

+#define BDMA_CCR_DIR            BDMA_CCR_DIR_Msk                               /*!< Data transfer direction             */

+#define BDMA_CCR_CIRC_Pos       (5U)

+#define BDMA_CCR_CIRC_Msk       (0x1UL << BDMA_CCR_CIRC_Pos)                   /*!< 0x00000020 */

+#define BDMA_CCR_CIRC           BDMA_CCR_CIRC_Msk                              /*!< Circular mode                       */

+#define BDMA_CCR_PINC_Pos       (6U)

+#define BDMA_CCR_PINC_Msk       (0x1UL << BDMA_CCR_PINC_Pos)                   /*!< 0x00000040 */

+#define BDMA_CCR_PINC           BDMA_CCR_PINC_Msk                              /*!< Peripheral increment mode           */

+#define BDMA_CCR_MINC_Pos       (7U)

+#define BDMA_CCR_MINC_Msk       (0x1UL << BDMA_CCR_MINC_Pos)                   /*!< 0x00000080 */

+#define BDMA_CCR_MINC           BDMA_CCR_MINC_Msk                              /*!< Memory increment mode               */

+

+#define BDMA_CCR_PSIZE_Pos      (8U)

+#define BDMA_CCR_PSIZE_Msk      (0x3UL << BDMA_CCR_PSIZE_Pos)                  /*!< 0x00000300 */

+#define BDMA_CCR_PSIZE          BDMA_CCR_PSIZE_Msk                             /*!< PSIZE[1:0] bits (Peripheral size)   */

+#define BDMA_CCR_PSIZE_0        (0x1UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000100 */

+#define BDMA_CCR_PSIZE_1        (0x2UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000200 */

+

+#define BDMA_CCR_MSIZE_Pos      (10U)

+#define BDMA_CCR_MSIZE_Msk      (0x3UL << BDMA_CCR_MSIZE_Pos)                  /*!< 0x00000C00 */

+#define BDMA_CCR_MSIZE          BDMA_CCR_MSIZE_Msk                             /*!< MSIZE[1:0] bits (Memory size)       */

+#define BDMA_CCR_MSIZE_0        (0x1UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000400 */

+#define BDMA_CCR_MSIZE_1        (0x2UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000800 */

+

+#define BDMA_CCR_PL_Pos         (12U)

+#define BDMA_CCR_PL_Msk         (0x3UL << BDMA_CCR_PL_Pos)                     /*!< 0x00003000 */

+#define BDMA_CCR_PL             BDMA_CCR_PL_Msk                                /*!< PL[1:0] bits(Channel Priority level)*/

+#define BDMA_CCR_PL_0           (0x1UL << BDMA_CCR_PL_Pos)                      /*!< 0x00001000 */

+#define BDMA_CCR_PL_1           (0x2UL << BDMA_CCR_PL_Pos)                      /*!< 0x00002000 */

+

+#define BDMA_CCR_MEM2MEM_Pos    (14U)

+#define BDMA_CCR_MEM2MEM_Msk    (0x1UL << BDMA_CCR_MEM2MEM_Pos)                /*!< 0x00004000 */

+#define BDMA_CCR_MEM2MEM        BDMA_CCR_MEM2MEM_Msk                           /*!< Memory to memory mode               */

+#define BDMA_CCR_DBM_Pos        (15U)

+#define BDMA_CCR_DBM_Msk        (0x1UL << BDMA_CCR_DBM_Pos)                    /*!< 0x0000A000 */

+#define BDMA_CCR_DBM            BDMA_CCR_DBM_Msk                               /*!< Memory to memory mode               */

+#define BDMA_CCR_CT_Pos         (16U)

+#define BDMA_CCR_CT_Msk         (0x1UL << BDMA_CCR_CT_Pos)                     /*!< 0x00010000 */

+#define BDMA_CCR_CT             BDMA_CCR_CT_Msk                                /*!< Memory to memory mode               */

+

+/******************  Bit definition for BDMA_CNDTR register  *******************/

+#define BDMA_CNDTR_NDT_Pos      (0U)

+#define BDMA_CNDTR_NDT_Msk      (0xFFFFUL << BDMA_CNDTR_NDT_Pos)               /*!< 0x0000FFFF */

+#define BDMA_CNDTR_NDT          BDMA_CNDTR_NDT_Msk                             /*!< Number of data to Transfer          */

+

+/******************  Bit definition for BDMA_CPAR register  ********************/

+#define BDMA_CPAR_PA_Pos        (0U)

+#define BDMA_CPAR_PA_Msk        (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CPAR_PA            BDMA_CPAR_PA_Msk                               /*!< Peripheral Address                  */

+

+/******************  Bit definition for BDMA_CM0AR register  ********************/

+#define BDMA_CM0AR_MA_Pos        (0U)

+#define BDMA_CM0AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CM0AR_MA            BDMA_CM0AR_MA_Msk                               /*!< Memory Address                      */

+

+/******************  Bit definition for BDMA_CM1AR register  ********************/

+#define BDMA_CM1AR_MA_Pos        (0U)

+#define BDMA_CM1AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CM1AR_MA            BDMA_CM1AR_MA_Msk                               /*!< Memory Address                      */

+

+/******************************************************************************/

+/*                                                                            */

+/*                Ethernet MAC Registers bits definitions                     */

+/*                                                                            */

+/******************************************************************************/

+/* Bit definition for Ethernet MAC Configuration Register register */

+#define ETH_MACCR_ARP_Pos                             (31U)

+#define ETH_MACCR_ARP_Msk                             (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */

+#define ETH_MACCR_ARP                                 ETH_MACCR_ARP_Msk        /* ARP Offload Enable */

+#define ETH_MACCR_SARC_Pos                            (28U)

+#define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */

+#define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */

+#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */

+#define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)

+#define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */

+#define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */

+#define ETH_MACCR_SARC_INSADDR1_Pos                   (29U)

+#define ETH_MACCR_SARC_INSADDR1_Msk                   (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */

+#define ETH_MACCR_SARC_INSADDR1                       ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */

+#define ETH_MACCR_SARC_REPADDR0_Pos                   (28U)

+#define ETH_MACCR_SARC_REPADDR0_Msk                   (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */

+#define ETH_MACCR_SARC_REPADDR0                       ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */

+#define ETH_MACCR_SARC_REPADDR1_Pos                   (28U)

+#define ETH_MACCR_SARC_REPADDR1_Msk                   (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */

+#define ETH_MACCR_SARC_REPADDR1                       ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */

+#define ETH_MACCR_IPC_Pos                             (27U)

+#define ETH_MACCR_IPC_Msk                             (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */

+#define ETH_MACCR_IPC                                 ETH_MACCR_IPC_Msk        /* Checksum Offload */

+#define ETH_MACCR_IPG_Pos                             (24U)

+#define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */

+#define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */

+#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */

+#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */

+#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */

+#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */

+#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */

+#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */

+#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */

+#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */

+#define ETH_MACCR_GPSLCE_Pos                          (23U)

+#define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */

+#define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */

+#define ETH_MACCR_S2KP_Pos                            (22U)

+#define ETH_MACCR_S2KP_Msk                            (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */

+#define ETH_MACCR_S2KP                                ETH_MACCR_S2KP_Msk       /* IEEE 802.3as Support for 2K Packets */

+#define ETH_MACCR_CST_Pos                             (21U)

+#define ETH_MACCR_CST_Msk                             (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */

+#define ETH_MACCR_CST                                 ETH_MACCR_CST_Msk        /* CRC stripping for Type packets */

+#define ETH_MACCR_ACS_Pos                             (20U)

+#define ETH_MACCR_ACS_Msk                             (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */

+#define ETH_MACCR_ACS                                 ETH_MACCR_ACS_Msk        /* Automatic Pad or CRC Stripping */

+#define ETH_MACCR_WD_Pos                              (19U)

+#define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */

+#define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */

+#define ETH_MACCR_JD_Pos                              (17U)

+#define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */

+#define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */

+#define ETH_MACCR_JE_Pos                              (16U)

+#define ETH_MACCR_JE_Msk                              (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */

+#define ETH_MACCR_JE                                  ETH_MACCR_JE_Msk         /* Jumbo Packet Enable */

+#define ETH_MACCR_FES_Pos                             (14U)

+#define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */

+#define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */

+#define ETH_MACCR_DM_Pos                              (13U)

+#define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */

+#define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */

+#define ETH_MACCR_LM_Pos                              (12U)

+#define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */

+#define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */

+#define ETH_MACCR_ECRSFD_Pos                          (11U)

+#define ETH_MACCR_ECRSFD_Msk                          (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */

+#define ETH_MACCR_ECRSFD                              ETH_MACCR_ECRSFD_Msk     /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */

+#define ETH_MACCR_DO_Pos                              (10U)

+#define ETH_MACCR_DO_Msk                              (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */

+#define ETH_MACCR_DO                                  ETH_MACCR_DO_Msk         /* Disable Receive own  */

+#define ETH_MACCR_DCRS_Pos                            (9U)

+#define ETH_MACCR_DCRS_Msk                            (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */

+#define ETH_MACCR_DCRS                                ETH_MACCR_DCRS_Msk       /* Disable Carrier Sense During Transmission */

+#define ETH_MACCR_DR_Pos                              (8U)

+#define ETH_MACCR_DR_Msk                              (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */

+#define ETH_MACCR_DR                                  ETH_MACCR_DR_Msk         /* Disable Retry */

+#define ETH_MACCR_BL_Pos                              (5U)

+#define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */

+#define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit mask */

+#define ETH_MACCR_BL_10                               (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */

+#define ETH_MACCR_BL_8                                (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */

+#define ETH_MACCR_BL_4                                (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */

+#define ETH_MACCR_BL_1                                (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */

+#define ETH_MACCR_DC_Pos                              (4U)

+#define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */

+#define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */

+#define ETH_MACCR_PRELEN_Pos                          (2U)

+#define ETH_MACCR_PRELEN_Msk                          (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */

+#define ETH_MACCR_PRELEN                              ETH_MACCR_PRELEN_Msk     /* Preamble Length for Transmit packets */

+#define ETH_MACCR_PRELEN_7                            (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */

+#define ETH_MACCR_PRELEN_5                            (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */

+#define ETH_MACCR_PRELEN_3                            (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */

+#define ETH_MACCR_TE_Pos                              (1U)

+#define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */

+#define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */

+#define ETH_MACCR_RE_Pos                              (0U)

+#define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */

+#define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */

+

+/* Bit definition for Ethernet MAC Extended Configuration Register register */

+#define ETH_MACECR_EIPG_Pos                           (25U)

+#define ETH_MACECR_EIPG_Msk                           (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */

+#define ETH_MACECR_EIPG                               ETH_MACECR_EIPG_Msk      /* Extended Inter-Packet Gap */

+#define ETH_MACECR_EIPGEN_Pos                         (24U)

+#define ETH_MACECR_EIPGEN_Msk                         (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */

+#define ETH_MACECR_EIPGEN                             ETH_MACECR_EIPGEN_Msk    /* Extended Inter-Packet Gap Enable */

+#define ETH_MACECR_USP_Pos                            (18U)

+#define ETH_MACECR_USP_Msk                            (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */

+#define ETH_MACECR_USP                                ETH_MACECR_USP_Msk       /* Unicast Slow Protocol Packet Detect */

+#define ETH_MACECR_SPEN_Pos                           (17U)

+#define ETH_MACECR_SPEN_Msk                           (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */

+#define ETH_MACECR_SPEN                               ETH_MACECR_SPEN_Msk      /* Slow Protocol Detection Enable */

+#define ETH_MACECR_DCRCC_Pos                          (16U)

+#define ETH_MACECR_DCRCC_Msk                          (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */

+#define ETH_MACECR_DCRCC                              ETH_MACECR_DCRCC_Msk     /* Disable CRC Checking for Received Packets */

+#define ETH_MACECR_GPSL_Pos                           (0U)

+#define ETH_MACECR_GPSL_Msk                           (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */

+#define ETH_MACECR_GPSL                               ETH_MACECR_GPSL_Msk      /* Giant Packet Size Limit */

+

+/* Bit definition for Ethernet MAC Packet Filter Register */

+#define ETH_MACPFR_RA_Pos                             (31U)

+#define ETH_MACPFR_RA_Msk                             (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */

+#define ETH_MACPFR_RA                                 ETH_MACPFR_RA_Msk        /* Receive all */

+#define ETH_MACPFR_DNTU_Pos                           (21U)

+#define ETH_MACPFR_DNTU_Msk                           (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */

+#define ETH_MACPFR_DNTU                               ETH_MACPFR_DNTU_Msk      /* Drop Non-TCP/UDP over IP Packets */

+#define ETH_MACPFR_IPFE_Pos                           (20U)

+#define ETH_MACPFR_IPFE_Msk                           (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */

+#define ETH_MACPFR_IPFE                               ETH_MACPFR_IPFE_Msk      /* Layer 3 and Layer 4 Filter Enable */

+#define ETH_MACPFR_VTFE_Pos                           (16U)

+#define ETH_MACPFR_VTFE_Msk                           (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */

+#define ETH_MACPFR_VTFE                               ETH_MACPFR_VTFE_Msk      /* VLAN Tag Filter Enable */

+#define ETH_MACPFR_HPF_Pos                            (10U)

+#define ETH_MACPFR_HPF_Msk                            (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */

+#define ETH_MACPFR_HPF                                ETH_MACPFR_HPF_Msk       /* Hash or perfect filter */

+#define ETH_MACPFR_SAF_Pos                            (9U)

+#define ETH_MACPFR_SAF_Msk                            (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */

+#define ETH_MACPFR_SAF                                ETH_MACPFR_SAF_Msk       /* Source address filter enable */

+#define ETH_MACPFR_SAIF_Pos                           (8U)

+#define ETH_MACPFR_SAIF_Msk                           (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */

+#define ETH_MACPFR_SAIF                               ETH_MACPFR_SAIF_Msk      /* SA inverse filtering */

+#define ETH_MACPFR_PCF_Pos                            (6U)

+#define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */

+#define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */

+#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */

+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)

+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */

+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */

+#define ETH_MACPFR_PCF_FORWARDALL_Pos                 (7U)

+#define ETH_MACPFR_PCF_FORWARDALL_Msk                 (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */

+#define ETH_MACPFR_PCF_FORWARDALL                     ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */

+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos    (6U)

+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk    (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */

+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER        ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */

+#define ETH_MACPFR_DBF_Pos                            (5U)

+#define ETH_MACPFR_DBF_Msk                            (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */

+#define ETH_MACPFR_DBF                                ETH_MACPFR_DBF_Msk       /* Disable Broadcast Packets */

+#define ETH_MACPFR_PM_Pos                             (4U)

+#define ETH_MACPFR_PM_Msk                             (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */

+#define ETH_MACPFR_PM                                 ETH_MACPFR_PM_Msk        /* Pass all mutlicast */

+#define ETH_MACPFR_DAIF_Pos                           (3U)

+#define ETH_MACPFR_DAIF_Msk                           (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */

+#define ETH_MACPFR_DAIF                               ETH_MACPFR_DAIF_Msk      /* DA Inverse filtering */

+#define ETH_MACPFR_HMC_Pos                            (2U)

+#define ETH_MACPFR_HMC_Msk                            (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */

+#define ETH_MACPFR_HMC                                ETH_MACPFR_HMC_Msk       /* Hash multicast */

+#define ETH_MACPFR_HUC_Pos                            (1U)

+#define ETH_MACPFR_HUC_Msk                            (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */

+#define ETH_MACPFR_HUC                                ETH_MACPFR_HUC_Msk       /* Hash unicast */

+#define ETH_MACPFR_PR_Pos                             (0U)

+#define ETH_MACPFR_PR_Msk                             (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */

+#define ETH_MACPFR_PR                                 ETH_MACPFR_PR_Msk        /* Promiscuous mode */

+

+/* Bit definition for Ethernet MAC Watchdog Timeout Register */

+#define ETH_MACWTR_PWE_Pos                            (8U)

+#define ETH_MACWTR_PWE_Msk                            (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */

+#define ETH_MACWTR_PWE                                ETH_MACWTR_PWE_Msk       /* Programmable Watchdog Enable */

+#define ETH_MACWTR_WTO_Pos                            (0U)

+#define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */

+#define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */

+#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/

+#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */

+#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */

+#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */

+#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */

+#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */

+#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */

+#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */

+#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */

+#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */

+#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */

+#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */

+#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */

+#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */

+#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */

+

+/* Bit definition for Ethernet MAC Hash Table High Register */

+#define ETH_MACHTHR_HTH_Pos                           (0U)

+#define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */

+

+/* Bit definition for Ethernet MAC Hash Table Low Register */

+#define ETH_MACHTLR_HTL_Pos                           (0U)

+#define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */

+

+/* Bit definition for Ethernet MAC VLAN Tag Register */

+#define ETH_MACVTR_EIVLRXS_Pos                        (31U)

+#define ETH_MACVTR_EIVLRXS_Msk                        (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */

+#define ETH_MACVTR_EIVLRXS                            ETH_MACVTR_EIVLRXS_Msk   /* Enable Inner VLAN Tag in Rx Status */

+#define ETH_MACVTR_EIVLS_Pos                          (28U)

+#define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */

+#define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */

+#define ETH_MACVTR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */

+#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)

+#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */

+#define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */

+#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos             (29U)

+#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk             (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */

+#define ETH_MACVTR_EIVLS_STRIPIFFAILS                 ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */

+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos              (28U)

+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk              (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */

+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP                  ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */

+#define ETH_MACVTR_ERIVLT_Pos                         (27U)

+#define ETH_MACVTR_ERIVLT_Msk                         (0x1UL << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */

+#define ETH_MACVTR_ERIVLT                             ETH_MACVTR_ERIVLT_Msk    /* Enable Inner VLAN Tag */

+#define ETH_MACVTR_EDVLP_Pos                          (26U)

+#define ETH_MACVTR_EDVLP_Msk                          (0x1UL << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */

+#define ETH_MACVTR_EDVLP                              ETH_MACVTR_EDVLP_Msk     /* Enable Double VLAN Processing */

+#define ETH_MACVTR_VTHM_Pos                           (25U)

+#define ETH_MACVTR_VTHM_Msk                           (0x1UL << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */

+#define ETH_MACVTR_VTHM                               ETH_MACVTR_VTHM_Msk      /* VLAN Tag Hash Table Match Enable */

+#define ETH_MACVTR_EVLRXS_Pos                         (24U)

+#define ETH_MACVTR_EVLRXS_Msk                         (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */

+#define ETH_MACVTR_EVLRXS                             ETH_MACVTR_EVLRXS_Msk    /* Enable VLAN Tag in Rx status */

+#define ETH_MACVTR_EVLS_Pos                           (21U)

+#define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */

+#define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */

+#define ETH_MACVTR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */

+#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)

+#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */

+#define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */

+#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos              (22U)

+#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk              (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */

+#define ETH_MACVTR_EVLS_STRIPIFFAILS                  ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */

+#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos               (21U)

+#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk               (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */

+#define ETH_MACVTR_EVLS_ALWAYSSTRIP                   ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */

+#define ETH_MACVTR_DOVLTC_Pos                         (20U)

+#define ETH_MACVTR_DOVLTC_Msk                         (0x1UL << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */

+#define ETH_MACVTR_DOVLTC                             ETH_MACVTR_DOVLTC_Msk    /* Disable VLAN Type Check */

+#define ETH_MACVTR_ERSVLM_Pos                         (19U)

+#define ETH_MACVTR_ERSVLM_Msk                         (0x1UL << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */

+#define ETH_MACVTR_ERSVLM                             ETH_MACVTR_ERSVLM_Msk    /* Enable Receive S-VLAN Match */

+#define ETH_MACVTR_ESVL_Pos                           (18U)

+#define ETH_MACVTR_ESVL_Msk                           (0x1UL << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */

+#define ETH_MACVTR_ESVL                               ETH_MACVTR_ESVL_Msk      /* Enable S-VLAN */

+#define ETH_MACVTR_VTIM_Pos                           (17U)

+#define ETH_MACVTR_VTIM_Msk                           (0x1UL << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */

+#define ETH_MACVTR_VTIM                               ETH_MACVTR_VTIM_Msk      /* VLAN Tag Inverse Match Enable */

+#define ETH_MACVTR_ETV_Pos                            (16U)

+#define ETH_MACVTR_ETV_Msk                            (0x1UL << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */

+#define ETH_MACVTR_ETV                                ETH_MACVTR_ETV_Msk       /* Enable 12-Bit VLAN Tag Comparison */

+#define ETH_MACVTR_VL_Pos                             (0U)

+#define ETH_MACVTR_VL_Msk                             (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */

+#define ETH_MACVTR_VL                                 ETH_MACVTR_VL_Msk        /* VLAN Tag Identifier for Receive Packets */

+#define ETH_MACVTR_VL_UP_Pos                          (13U)

+#define ETH_MACVTR_VL_UP_Msk                          (0x7UL << ETH_MACVTR_VL_UP_Pos) /*!< 0x0000E000 */

+#define ETH_MACVTR_VL_UP                              ETH_MACVTR_VL_UP_Msk     /* User Priority */

+#define ETH_MACVTR_VL_CFIDEI_Pos                      (12U)

+#define ETH_MACVTR_VL_CFIDEI_Msk                      (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos) /*!< 0x00001000 */

+#define ETH_MACVTR_VL_CFIDEI                          ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */

+#define ETH_MACVTR_VL_VID_Pos                         (0U)

+#define ETH_MACVTR_VL_VID_Msk                         (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */

+#define ETH_MACVTR_VL_VID                             ETH_MACVTR_VL_VID_Msk    /* VLAN Identifier field of VLAN tag */

+

+/* Bit definition for Ethernet MAC VLAN Hash Table Register */

+#define ETH_MACVHTR_VLHT_Pos                          (0U)

+#define ETH_MACVHTR_VLHT_Msk                          (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACVHTR_VLHT                              ETH_MACVHTR_VLHT_Msk     /* VLAN Hash Table */

+

+/* Bit definition for Ethernet MAC VLAN Incl Register */

+#define ETH_MACVIR_VLTI_Pos                           (20U)

+#define ETH_MACVIR_VLTI_Msk                           (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */

+#define ETH_MACVIR_VLTI                               ETH_MACVIR_VLTI_Msk      /* VLAN Tag Input */

+#define ETH_MACVIR_CSVL_Pos                           (19U)

+#define ETH_MACVIR_CSVL_Msk                           (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */

+#define ETH_MACVIR_CSVL                               ETH_MACVIR_CSVL_Msk      /* C-VLAN or S-VLAN */

+#define ETH_MACVIR_VLP_Pos                            (18U)

+#define ETH_MACVIR_VLP_Msk                            (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */

+#define ETH_MACVIR_VLP                                ETH_MACVIR_VLP_Msk       /* VLAN Priority Control */

+#define ETH_MACVIR_VLC_Pos                            (16U)

+#define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */

+#define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */

+#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */

+#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)

+#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */

+#define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */

+#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos              (17U)

+#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */

+#define ETH_MACVIR_VLC_VLANTAGINSERT                  ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */

+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos             (16U)

+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk             (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */

+#define ETH_MACVIR_VLC_VLANTAGREPLACE                 ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */

+#define ETH_MACVIR_VLT_Pos                            (0U)

+#define ETH_MACVIR_VLT_Msk                            (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACVIR_VLT                                ETH_MACVIR_VLT_Msk       /* VLAN Tag for Transmit Packets */

+#define ETH_MACVIR_VLT_UP_Pos                         (13U)

+#define ETH_MACVIR_VLT_UP_Msk                         (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */

+#define ETH_MACVIR_VLT_UP                             ETH_MACVIR_VLT_UP_Msk    /* User Priority */

+#define ETH_MACVIR_VLT_CFIDEI_Pos                     (12U)

+#define ETH_MACVIR_VLT_CFIDEI_Msk                     (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */

+#define ETH_MACVIR_VLT_CFIDEI                         ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */

+#define ETH_MACVIR_VLT_VID_Pos                        (0U)

+#define ETH_MACVIR_VLT_VID_Msk                        (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */

+#define ETH_MACVIR_VLT_VID                            ETH_MACVIR_VLT_VID_Msk   /* VLAN Identifier field of VLAN tag */

+

+/* Bit definition for Ethernet MAC Inner_VLAN Incl Register */

+#define ETH_MACIVIR_VLTI_Pos                          (20U)

+#define ETH_MACIVIR_VLTI_Msk                          (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */

+#define ETH_MACIVIR_VLTI                              ETH_MACIVIR_VLTI_Msk     /* VLAN Tag Input */

+#define ETH_MACIVIR_CSVL_Pos                          (19U)

+#define ETH_MACIVIR_CSVL_Msk                          (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */

+#define ETH_MACIVIR_CSVL                              ETH_MACIVIR_CSVL_Msk     /* C-VLAN or S-VLAN */

+#define ETH_MACIVIR_VLP_Pos                           (18U)

+#define ETH_MACIVIR_VLP_Msk                           (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */

+#define ETH_MACIVIR_VLP                               ETH_MACIVIR_VLP_Msk      /* VLAN Priority Control */

+#define ETH_MACIVIR_VLC_Pos                           (16U)

+#define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */

+#define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */

+#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */

+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)

+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */

+#define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */

+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos             (17U)

+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */

+#define ETH_MACIVIR_VLC_VLANTAGINSERT                 ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */

+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos            (16U)

+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk            (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */

+#define ETH_MACIVIR_VLC_VLANTAGREPLACE                ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */

+#define ETH_MACIVIR_VLT_Pos                           (0U)

+#define ETH_MACIVIR_VLT_Msk                           (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACIVIR_VLT                               ETH_MACIVIR_VLT_Msk      /* VLAN Tag for Transmit Packets */

+#define ETH_MACIVIR_VLT_UP_Pos                        (13U)

+#define ETH_MACIVIR_VLT_UP_Msk                        (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */

+#define ETH_MACIVIR_VLT_UP                            ETH_MACIVIR_VLT_UP_Msk   /* User Priority */

+#define ETH_MACIVIR_VLT_CFIDEI_Pos                    (12U)

+#define ETH_MACIVIR_VLT_CFIDEI_Msk                    (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */

+#define ETH_MACIVIR_VLT_CFIDEI                        ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */

+#define ETH_MACIVIR_VLT_VID_Pos                       (0U)

+#define ETH_MACIVIR_VLT_VID_Msk                       (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */

+#define ETH_MACIVIR_VLT_VID                           ETH_MACIVIR_VLT_VID_Msk  /* VLAN Identifier field of VLAN tag */

+

+/* Bit definition for Ethernet MAC Tx Flow Ctrl Register */

+#define ETH_MACTFCR_PT_Pos                            (16U)

+#define ETH_MACTFCR_PT_Msk                            (0xFFFFUL << ETH_MACTFCR_PT_Pos) /*!< 0xFFFF0000 */

+#define ETH_MACTFCR_PT                                ETH_MACTFCR_PT_Msk       /* Pause Time */

+#define ETH_MACTFCR_DZPQ_Pos                          (7U)

+#define ETH_MACTFCR_DZPQ_Msk                          (0x1UL << ETH_MACTFCR_DZPQ_Pos) /*!< 0x00000080 */

+#define ETH_MACTFCR_DZPQ                              ETH_MACTFCR_DZPQ_Msk     /* Disable Zero-Quanta Pause */

+#define ETH_MACTFCR_PLT_Pos                           (4U)

+#define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */

+#define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */

+#define ETH_MACTFCR_PLT_MINUS4                        ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */

+#define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)

+#define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */

+#define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */

+#define ETH_MACTFCR_PLT_MINUS36_Pos                   (5U)

+#define ETH_MACTFCR_PLT_MINUS36_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */

+#define ETH_MACTFCR_PLT_MINUS36                       ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */

+#define ETH_MACTFCR_PLT_MINUS144_Pos                  (4U)

+#define ETH_MACTFCR_PLT_MINUS144_Msk                  (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */

+#define ETH_MACTFCR_PLT_MINUS144                      ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */

+#define ETH_MACTFCR_PLT_MINUS256_Pos                  (6U)

+#define ETH_MACTFCR_PLT_MINUS256_Msk                  (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */

+#define ETH_MACTFCR_PLT_MINUS256                      ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */

+#define ETH_MACTFCR_PLT_MINUS512_Pos                  (4U)

+#define ETH_MACTFCR_PLT_MINUS512_Msk                  (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */

+#define ETH_MACTFCR_PLT_MINUS512                      ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */

+#define ETH_MACTFCR_TFE_Pos                           (1U)

+#define ETH_MACTFCR_TFE_Msk                           (0x1UL << ETH_MACTFCR_TFE_Pos) /*!< 0x00000002 */

+#define ETH_MACTFCR_TFE                               ETH_MACTFCR_TFE_Msk      /* Transmit Flow Control Enable */

+#define ETH_MACTFCR_FCB_Pos                           (0U)

+#define ETH_MACTFCR_FCB_Msk                           (0x1UL << ETH_MACTFCR_FCB_Pos) /*!< 0x00000001 */

+#define ETH_MACTFCR_FCB                               ETH_MACTFCR_FCB_Msk      /* Flow Control Busy or Backpressure Activate */

+

+/* Bit definition for Ethernet MAC Rx Flow Ctrl Register */

+#define ETH_MACRFCR_UP_Pos                            (1U)

+#define ETH_MACRFCR_UP_Msk                            (0x1UL << ETH_MACRFCR_UP_Pos) /*!< 0x00000002 */

+#define ETH_MACRFCR_UP                                ETH_MACRFCR_UP_Msk       /* Unicast Pause Packet Detect */

+#define ETH_MACRFCR_RFE_Pos                           (0U)

+#define ETH_MACRFCR_RFE_Msk                           (0x1UL << ETH_MACRFCR_RFE_Pos) /*!< 0x00000001 */

+#define ETH_MACRFCR_RFE                               ETH_MACRFCR_RFE_Msk      /* Receive Flow Control Enable */

+

+/* Bit definition for Ethernet MAC Interrupt Status Register */

+#define ETH_MACISR_RXSTSIS_Pos                        (14U)

+#define ETH_MACISR_RXSTSIS_Msk                        (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */

+#define ETH_MACISR_RXSTSIS                            ETH_MACISR_RXSTSIS_Msk   /* Receive Status Interrupt */

+#define ETH_MACISR_TXSTSIS_Pos                        (13U)

+#define ETH_MACISR_TXSTSIS_Msk                        (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */

+#define ETH_MACISR_TXSTSIS                            ETH_MACISR_TXSTSIS_Msk   /* Transmit Status Interrupt */

+#define ETH_MACISR_TSIS_Pos                           (12U)

+#define ETH_MACISR_TSIS_Msk                           (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */

+#define ETH_MACISR_TSIS                               ETH_MACISR_TSIS_Msk      /* Timestamp Interrupt Status */

+#define ETH_MACISR_MMCTXIS_Pos                        (10U)

+#define ETH_MACISR_MMCTXIS_Msk                        (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */

+#define ETH_MACISR_MMCTXIS                            ETH_MACISR_MMCTXIS_Msk   /* MMC Transmit Interrupt Status */

+#define ETH_MACISR_MMCRXIS_Pos                        (9U)

+#define ETH_MACISR_MMCRXIS_Msk                        (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */

+#define ETH_MACISR_MMCRXIS                            ETH_MACISR_MMCRXIS_Msk   /* MMC Receive Interrupt Status */

+#define ETH_MACISR_MMCIS_Pos                          (8U)

+#define ETH_MACISR_MMCIS_Msk                          (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */

+#define ETH_MACISR_MMCIS                              ETH_MACISR_MMCIS_Msk     /* MMC Interrupt Status */

+#define ETH_MACISR_LPIIS_Pos                          (5U)

+#define ETH_MACISR_LPIIS_Msk                          (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */

+#define ETH_MACISR_LPIIS                              ETH_MACISR_LPIIS_Msk     /* LPI Interrupt Status */

+#define ETH_MACISR_PMTIS_Pos                          (4U)

+#define ETH_MACISR_PMTIS_Msk                          (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */

+#define ETH_MACISR_PMTIS                              ETH_MACISR_PMTIS_Msk     /* PMT Interrupt Status */

+#define ETH_MACISR_PHYIS_Pos                          (3U)

+#define ETH_MACISR_PHYIS_Msk                          (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */

+#define ETH_MACISR_PHYIS                              ETH_MACISR_PHYIS_Msk     /* PHY Interrupt */

+

+/* Bit definition for Ethernet MAC Interrupt Enable Register */

+#define ETH_MACIER_RXSTSIE_Pos                        (14U)

+#define ETH_MACIER_RXSTSIE_Msk                        (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */

+#define ETH_MACIER_RXSTSIE                            ETH_MACIER_RXSTSIE_Msk   /* Receive Status Interrupt Enable */

+#define ETH_MACIER_TXSTSIE_Pos                        (13U)

+#define ETH_MACIER_TXSTSIE_Msk                        (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */

+#define ETH_MACIER_TXSTSIE                            ETH_MACIER_TXSTSIE_Msk   /* Transmit Status Interrupt Enable */

+#define ETH_MACIER_TSIE_Pos                           (12U)

+#define ETH_MACIER_TSIE_Msk                           (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */

+#define ETH_MACIER_TSIE                               ETH_MACIER_TSIE_Msk      /* Timestamp Interrupt Enable */

+#define ETH_MACIER_LPIIE_Pos                          (5U)

+#define ETH_MACIER_LPIIE_Msk                          (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */

+#define ETH_MACIER_LPIIE                              ETH_MACIER_LPIIE_Msk     /* LPI Interrupt Enable */

+#define ETH_MACIER_PMTIE_Pos                          (4U)

+#define ETH_MACIER_PMTIE_Msk                          (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */

+#define ETH_MACIER_PMTIE                              ETH_MACIER_PMTIE_Msk     /* PMT Interrupt Enable */

+#define ETH_MACIER_PHYIE_Pos                          (3U)

+#define ETH_MACIER_PHYIE_Msk                          (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */

+#define ETH_MACIER_PHYIE                              ETH_MACIER_PHYIE_Msk     /* PHY Interrupt Enable */

+

+/* Bit definition for Ethernet MAC Rx Tx Status Register */

+#define ETH_MACRXTXSR_RWT_Pos                         (8U)

+#define ETH_MACRXTXSR_RWT_Msk                         (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */

+#define ETH_MACRXTXSR_RWT                             ETH_MACRXTXSR_RWT_Msk    /* Receive Watchdog Timeout */

+#define ETH_MACRXTXSR_EXCOL_Pos                       (5U)

+#define ETH_MACRXTXSR_EXCOL_Msk                       (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */

+#define ETH_MACRXTXSR_EXCOL                           ETH_MACRXTXSR_EXCOL_Msk  /* Excessive Collisions */

+#define ETH_MACRXTXSR_LCOL_Pos                        (4U)

+#define ETH_MACRXTXSR_LCOL_Msk                        (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */

+#define ETH_MACRXTXSR_LCOL                            ETH_MACRXTXSR_LCOL_Msk   /* Late Collision */

+#define ETH_MACRXTXSR_EXDEF_Pos                       (3U)

+#define ETH_MACRXTXSR_EXDEF_Msk                       (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */

+#define ETH_MACRXTXSR_EXDEF                           ETH_MACRXTXSR_EXDEF_Msk  /* Excessive Deferral */

+#define ETH_MACRXTXSR_LCARR_Pos                       (2U)

+#define ETH_MACRXTXSR_LCARR_Msk                       (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */

+#define ETH_MACRXTXSR_LCARR                           ETH_MACRXTXSR_LCARR_Msk  /* Loss of Carrier */

+#define ETH_MACRXTXSR_NCARR_Pos                       (1U)

+#define ETH_MACRXTXSR_NCARR_Msk                       (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */

+#define ETH_MACRXTXSR_NCARR                           ETH_MACRXTXSR_NCARR_Msk  /* No Carrier */

+#define ETH_MACRXTXSR_TJT_Pos                         (0U)

+#define ETH_MACRXTXSR_TJT_Msk                         (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */

+#define ETH_MACRXTXSR_TJT                             ETH_MACRXTXSR_TJT_Msk    /* Transmit Jabber Timeout */

+

+/* Bit definition for Ethernet MAC PMT Control Status Register */

+#define ETH_MACPCSR_RWKFILTRST_Pos                    (31U)

+#define ETH_MACPCSR_RWKFILTRST_Msk                    (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */

+#define ETH_MACPCSR_RWKFILTRST                        ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */

+#define ETH_MACPCSR_RWKPTR_Pos                        (24U)

+#define ETH_MACPCSR_RWKPTR_Msk                        (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */

+#define ETH_MACPCSR_RWKPTR                            ETH_MACPCSR_RWKPTR_Msk   /* Remote Wake-up FIFO Pointer */

+#define ETH_MACPCSR_RWKPFE_Pos                        (10U)

+#define ETH_MACPCSR_RWKPFE_Msk                        (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */

+#define ETH_MACPCSR_RWKPFE                            ETH_MACPCSR_RWKPFE_Msk   /* Remote Wake-up Packet Forwarding Enable */

+#define ETH_MACPCSR_GLBLUCAST_Pos                     (9U)

+#define ETH_MACPCSR_GLBLUCAST_Msk                     (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */

+#define ETH_MACPCSR_GLBLUCAST                         ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */

+#define ETH_MACPCSR_RWKPRCVD_Pos                      (6U)

+#define ETH_MACPCSR_RWKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */

+#define ETH_MACPCSR_RWKPRCVD                          ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */

+#define ETH_MACPCSR_MGKPRCVD_Pos                      (5U)

+#define ETH_MACPCSR_MGKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */

+#define ETH_MACPCSR_MGKPRCVD                          ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */

+#define ETH_MACPCSR_RWKPKTEN_Pos                      (2U)

+#define ETH_MACPCSR_RWKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */

+#define ETH_MACPCSR_RWKPKTEN                          ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */

+#define ETH_MACPCSR_MGKPKTEN_Pos                      (1U)

+#define ETH_MACPCSR_MGKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */

+#define ETH_MACPCSR_MGKPKTEN                          ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */

+#define ETH_MACPCSR_PWRDWN_Pos                        (0U)

+#define ETH_MACPCSR_PWRDWN_Msk                        (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */

+#define ETH_MACPCSR_PWRDWN                            ETH_MACPCSR_PWRDWN_Msk   /* Power Down */

+

+/* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */

+#define ETH_MACRWUPFR_D_Pos                           (0U)

+#define ETH_MACRWUPFR_D_Msk                           (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACRWUPFR_D                               ETH_MACRWUPFR_D_Msk      /* Wake-up Packet filter register data */

+

+/* Bit definition for Ethernet MAC LPI Control Status Register */

+#define ETH_MACLCSR_LPITCSE_Pos                       (21U)

+#define ETH_MACLCSR_LPITCSE_Msk                       (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */

+#define ETH_MACLCSR_LPITCSE                           ETH_MACLCSR_LPITCSE_Msk  /* LPI Tx Clock Stop Enable */

+#define ETH_MACLCSR_LPITE_Pos                         (20U)

+#define ETH_MACLCSR_LPITE_Msk                         (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */

+#define ETH_MACLCSR_LPITE                             ETH_MACLCSR_LPITE_Msk    /* LPI Timer Enable */

+#define ETH_MACLCSR_LPITXA_Pos                        (19U)

+#define ETH_MACLCSR_LPITXA_Msk                        (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */

+#define ETH_MACLCSR_LPITXA                            ETH_MACLCSR_LPITXA_Msk   /* LPI Tx Automate */

+#define ETH_MACLCSR_PLS_Pos                           (17U)

+#define ETH_MACLCSR_PLS_Msk                           (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */

+#define ETH_MACLCSR_PLS                               ETH_MACLCSR_PLS_Msk      /* PHY Link Status */

+#define ETH_MACLCSR_LPIEN_Pos                         (16U)

+#define ETH_MACLCSR_LPIEN_Msk                         (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */

+#define ETH_MACLCSR_LPIEN                             ETH_MACLCSR_LPIEN_Msk    /* LPI Enable */

+#define ETH_MACLCSR_RLPIST_Pos                        (9U)

+#define ETH_MACLCSR_RLPIST_Msk                        (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */

+#define ETH_MACLCSR_RLPIST                            ETH_MACLCSR_RLPIST_Msk   /* Receive LPI State */

+#define ETH_MACLCSR_TLPIST_Pos                        (8U)

+#define ETH_MACLCSR_TLPIST_Msk                        (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */

+#define ETH_MACLCSR_TLPIST                            ETH_MACLCSR_TLPIST_Msk   /* Transmit LPI State */

+#define ETH_MACLCSR_RLPIEX_Pos                        (3U)

+#define ETH_MACLCSR_RLPIEX_Msk                        (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */

+#define ETH_MACLCSR_RLPIEX                            ETH_MACLCSR_RLPIEX_Msk   /* Receive LPI Exit */

+#define ETH_MACLCSR_RLPIEN_Pos                        (2U)

+#define ETH_MACLCSR_RLPIEN_Msk                        (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */

+#define ETH_MACLCSR_RLPIEN                            ETH_MACLCSR_RLPIEN_Msk   /* Receive LPI Entry */

+#define ETH_MACLCSR_TLPIEX_Pos                        (1U)

+#define ETH_MACLCSR_TLPIEX_Msk                        (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */

+#define ETH_MACLCSR_TLPIEX                            ETH_MACLCSR_TLPIEX_Msk   /* Transmit LPI Exit */

+#define ETH_MACLCSR_TLPIEN_Pos                        (0U)

+#define ETH_MACLCSR_TLPIEN_Msk                        (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */

+#define ETH_MACLCSR_TLPIEN                            ETH_MACLCSR_TLPIEN_Msk   /* Transmit LPI Entry */

+

+/* Bit definition for Ethernet MAC LPI Timers Control Register */

+#define ETH_MACLTCR_LST_Pos                           (16U)

+#define ETH_MACLTCR_LST_Msk                           (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */

+#define ETH_MACLTCR_LST                               ETH_MACLTCR_LST_Msk      /* LPI LS TIMER */

+#define ETH_MACLTCR_TWT_Pos                           (0U)

+#define ETH_MACLTCR_TWT_Msk                           (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACLTCR_TWT                               ETH_MACLTCR_TWT_Msk      /* LPI TW TIMER */

+

+/* Bit definition for Ethernet MAC LPI Entry Timer Register */

+#define ETH_MACLETR_LPIET_Pos                         (0U)

+#define ETH_MACLETR_LPIET_Msk                         (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */

+#define ETH_MACLETR_LPIET                             ETH_MACLETR_LPIET_Msk    /* LPI Entry Timer */

+

+/* Bit definition for Ethernet MAC 1US Tic Counter Register */

+#define ETH_MAC1USTCR_TIC1USCNTR_Pos                  (0U)

+#define ETH_MAC1USTCR_TIC1USCNTR_Msk                  (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */

+#define ETH_MAC1USTCR_TIC1USCNTR                      ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */

+

+/* Bit definition for Ethernet MAC Version Register */

+#define ETH_MACVR_USERVER_Pos                         (8U)

+#define ETH_MACVR_USERVER_Msk                         (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */

+#define ETH_MACVR_USERVER                             ETH_MACVR_USERVER_Msk    /* User-defined Version */

+#define ETH_MACVR_SNPSVER_Pos                         (0U)

+#define ETH_MACVR_SNPSVER_Msk                         (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */

+#define ETH_MACVR_SNPSVER                             ETH_MACVR_SNPSVER_Msk    /* Synopsys-defined Version */

+

+/* Bit definition for Ethernet MAC Debug Register */

+#define ETH_MACDR_TFCSTS_Pos                          (17U)

+#define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */

+#define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */

+#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */

+#define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)

+#define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */

+#define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */

+#define ETH_MACDR_TFCSTS_GENERATEPCP_Pos              (18U)

+#define ETH_MACDR_TFCSTS_GENERATEPCP_Msk              (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */

+#define ETH_MACDR_TFCSTS_GENERATEPCP                  ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */

+#define ETH_MACDR_TFCSTS_TRASFERIP_Pos                (17U)

+#define ETH_MACDR_TFCSTS_TRASFERIP_Msk                (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */

+#define ETH_MACDR_TFCSTS_TRASFERIP                    ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */

+#define ETH_MACDR_TPESTS_Pos                          (16U)

+#define ETH_MACDR_TPESTS_Msk                          (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */

+#define ETH_MACDR_TPESTS                              ETH_MACDR_TPESTS_Msk     /* MAC Receive Packet Controller FIFO Status */

+#define ETH_MACDR_RFCFCSTS_Pos                        (1U)

+#define ETH_MACDR_RFCFCSTS_Msk                        (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */

+#define ETH_MACDR_RFCFCSTS                            ETH_MACDR_RFCFCSTS_Msk   /* MAC MII Transmit Protocol Engine Status */

+#define ETH_MACDR_RPESTS_Pos                          (0U)

+#define ETH_MACDR_RPESTS_Msk                          (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */

+#define ETH_MACDR_RPESTS                              ETH_MACDR_RPESTS_Msk     /* MAC MII Receive Protocol Engine Status */

+

+/* Bit definition for Ethernet MAC HW Feature0 Register */

+#define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)

+#define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */

+#define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */

+#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */

+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)

+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */

+#define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */

+#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos             (28U)

+#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk             (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos) /*!< 0x70000000 */

+#define ETH_MACHWF0R_ACTPHYSEL_REVMII                 ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */

+#define ETH_MACHWF0R_SAVLANINS_Pos                    (27U)

+#define ETH_MACHWF0R_SAVLANINS_Msk                    (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */

+#define ETH_MACHWF0R_SAVLANINS                        ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */

+#define ETH_MACHWF0R_TSSTSSEL_Pos                     (25U)

+#define ETH_MACHWF0R_TSSTSSEL_Msk                     (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */

+#define ETH_MACHWF0R_TSSTSSEL                         ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */

+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos            (25U)

+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */

+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL                ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */

+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos            (26U)

+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */

+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL                ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */

+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos                (25U)

+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk                (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */

+#define ETH_MACHWF0R_TSSTSSEL_BOTH                    ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */

+#define ETH_MACHWF0R_MACADR64SEL_Pos                  (24U)

+#define ETH_MACHWF0R_MACADR64SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */

+#define ETH_MACHWF0R_MACADR64SEL                      ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */

+#define ETH_MACHWF0R_MACADR32SEL_Pos                  (23U)

+#define ETH_MACHWF0R_MACADR32SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */

+#define ETH_MACHWF0R_MACADR32SEL                      ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */

+#define ETH_MACHWF0R_ADDMACADRSEL_Pos                 (18U)

+#define ETH_MACHWF0R_ADDMACADRSEL_Msk                 (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */

+#define ETH_MACHWF0R_ADDMACADRSEL                     ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */

+#define ETH_MACHWF0R_RXCOESEL_Pos                     (16U)

+#define ETH_MACHWF0R_RXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */

+#define ETH_MACHWF0R_RXCOESEL                         ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */

+#define ETH_MACHWF0R_TXCOESEL_Pos                     (14U)

+#define ETH_MACHWF0R_TXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */

+#define ETH_MACHWF0R_TXCOESEL                         ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */

+#define ETH_MACHWF0R_EEESEL_Pos                       (13U)

+#define ETH_MACHWF0R_EEESEL_Msk                       (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */

+#define ETH_MACHWF0R_EEESEL                           ETH_MACHWF0R_EEESEL_Msk  /* Energy Efficient Ethernet Enabled */

+#define ETH_MACHWF0R_TSSEL_Pos                        (12U)

+#define ETH_MACHWF0R_TSSEL_Msk                        (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */

+#define ETH_MACHWF0R_TSSEL                            ETH_MACHWF0R_TSSEL_Msk   /* IEEE 1588-2008 Timestamp Enabled */

+#define ETH_MACHWF0R_ARPOFFSEL_Pos                    (9U)

+#define ETH_MACHWF0R_ARPOFFSEL_Msk                    (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */

+#define ETH_MACHWF0R_ARPOFFSEL                        ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */

+#define ETH_MACHWF0R_MMCSEL_Pos                       (8U)

+#define ETH_MACHWF0R_MMCSEL_Msk                       (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */

+#define ETH_MACHWF0R_MMCSEL                           ETH_MACHWF0R_MMCSEL_Msk  /* RMON Module Enable */

+#define ETH_MACHWF0R_MGKSEL_Pos                       (7U)

+#define ETH_MACHWF0R_MGKSEL_Msk                       (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */

+#define ETH_MACHWF0R_MGKSEL                           ETH_MACHWF0R_MGKSEL_Msk  /* PMT Magic Packet Enable */

+#define ETH_MACHWF0R_RWKSEL_Pos                       (6U)

+#define ETH_MACHWF0R_RWKSEL_Msk                       (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */

+#define ETH_MACHWF0R_RWKSEL                           ETH_MACHWF0R_RWKSEL_Msk  /* PMT Remote Wake-up Packet Enable */

+#define ETH_MACHWF0R_SMASEL_Pos                       (5U)

+#define ETH_MACHWF0R_SMASEL_Msk                       (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */

+#define ETH_MACHWF0R_SMASEL                           ETH_MACHWF0R_SMASEL_Msk  /* SMA (MDIO) Interface */

+#define ETH_MACHWF0R_VLHASH_Pos                       (4U)

+#define ETH_MACHWF0R_VLHASH_Msk                       (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */

+#define ETH_MACHWF0R_VLHASH                           ETH_MACHWF0R_VLHASH_Msk  /* VLAN Hash Filter Selected */

+#define ETH_MACHWF0R_PCSSEL_Pos                       (3U)

+#define ETH_MACHWF0R_PCSSEL_Msk                       (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */

+#define ETH_MACHWF0R_PCSSEL                           ETH_MACHWF0R_PCSSEL_Msk  /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */

+#define ETH_MACHWF0R_HDSEL_Pos                        (2U)

+#define ETH_MACHWF0R_HDSEL_Msk                        (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */

+#define ETH_MACHWF0R_HDSEL                            ETH_MACHWF0R_HDSEL_Msk   /* Half-duplex Support */

+#define ETH_MACHWF0R_GMIISEL_Pos                      (1U)

+#define ETH_MACHWF0R_GMIISEL_Msk                      (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */

+#define ETH_MACHWF0R_GMIISEL                          ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */

+#define ETH_MACHWF0R_MIISEL_Pos                       (0U)

+#define ETH_MACHWF0R_MIISEL_Msk                       (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */

+#define ETH_MACHWF0R_MIISEL                           ETH_MACHWF0R_MIISEL_Msk  /* 10 or 100 Mbps Support */

+

+/* Bit definition for Ethernet MAC HW Feature1 Register */

+#define ETH_MACHWF1R_L3L4FNUM_Pos                     (27U)

+#define ETH_MACHWF1R_L3L4FNUM_Msk                     (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */

+#define ETH_MACHWF1R_L3L4FNUM                         ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */

+#define ETH_MACHWF1R_HASHTBLSZ_Pos                    (24U)

+#define ETH_MACHWF1R_HASHTBLSZ_Msk                    (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */

+#define ETH_MACHWF1R_HASHTBLSZ                        ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */

+#define ETH_MACHWF1R_AVSEL_Pos                        (20U)

+#define ETH_MACHWF1R_AVSEL_Msk                        (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */

+#define ETH_MACHWF1R_AVSEL                            ETH_MACHWF1R_AVSEL_Msk   /* AV Feature Enabled */

+#define ETH_MACHWF1R_DBGMEMA_Pos                      (19U)

+#define ETH_MACHWF1R_DBGMEMA_Msk                      (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */

+#define ETH_MACHWF1R_DBGMEMA                          ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */

+#define ETH_MACHWF1R_TSOEN_Pos                        (18U)

+#define ETH_MACHWF1R_TSOEN_Msk                        (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */

+#define ETH_MACHWF1R_TSOEN                            ETH_MACHWF1R_TSOEN_Msk   /* TCP Segmentation Offload Enable */

+#define ETH_MACHWF1R_SPHEN_Pos                        (17U)

+#define ETH_MACHWF1R_SPHEN_Msk                        (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */

+#define ETH_MACHWF1R_SPHEN                            ETH_MACHWF1R_SPHEN_Msk   /* Split Header Feature Enable */

+#define ETH_MACHWF1R_DCBEN_Pos                        (16U)

+#define ETH_MACHWF1R_DCBEN_Msk                        (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */

+#define ETH_MACHWF1R_DCBEN                            ETH_MACHWF1R_DCBEN_Msk   /* DCB Feature Enable */

+#define ETH_MACHWF1R_ADDR64_Pos                       (14U)

+#define ETH_MACHWF1R_ADDR64_Msk                       (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */

+#define ETH_MACHWF1R_ADDR64                           ETH_MACHWF1R_ADDR64_Msk  /* Address Width */

+#define ETH_MACHWF1R_ADDR64_32                        (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */

+#define ETH_MACHWF1R_ADDR64_40                        (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */

+#define ETH_MACHWF1R_ADDR64_48                        (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */

+#define ETH_MACHWF1R_ADVTHWORD_Pos                    (13U)

+#define ETH_MACHWF1R_ADVTHWORD_Msk                    (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */

+#define ETH_MACHWF1R_ADVTHWORD                        ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */

+#define ETH_MACHWF1R_PTOEN_Pos                        (12U)

+#define ETH_MACHWF1R_PTOEN_Msk                        (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */

+#define ETH_MACHWF1R_PTOEN                            ETH_MACHWF1R_PTOEN_Msk   /* PTP Offload Enable */

+#define ETH_MACHWF1R_OSTEN_Pos                        (11U)

+#define ETH_MACHWF1R_OSTEN_Msk                        (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */

+#define ETH_MACHWF1R_OSTEN                            ETH_MACHWF1R_OSTEN_Msk   /* One-Step Timestamping Enable */

+#define ETH_MACHWF1R_TXFIFOSIZE_Pos                   (6U)

+#define ETH_MACHWF1R_TXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */

+#define ETH_MACHWF1R_TXFIFOSIZE                       ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */

+#define ETH_MACHWF1R_RXFIFOSIZE_Pos                   (0U)

+#define ETH_MACHWF1R_RXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */

+#define ETH_MACHWF1R_RXFIFOSIZE                       ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */

+

+/* Bit definition for Ethernet MAC HW Feature2 Register */

+#define ETH_MACHWF2R_AUXSNAPNUM_Pos                   (28U)

+#define ETH_MACHWF2R_AUXSNAPNUM_Msk                   (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */

+#define ETH_MACHWF2R_AUXSNAPNUM                       ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */

+#define ETH_MACHWF2R_PPSOUTNUM_Pos                    (24U)

+#define ETH_MACHWF2R_PPSOUTNUM_Msk                    (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */

+#define ETH_MACHWF2R_PPSOUTNUM                        ETH_MACHWF2R_PPSOUTNUM_Msk /*  Number of PPS Outputs */

+#define ETH_MACHWF2R_TXCHCNT_Pos                      (18U)

+#define ETH_MACHWF2R_TXCHCNT_Msk                      (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */

+#define ETH_MACHWF2R_TXCHCNT                          ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */

+#define ETH_MACHWF2R_RXCHCNT_Pos                      (13U)

+#define ETH_MACHWF2R_RXCHCNT_Msk                      (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000E000 */

+#define ETH_MACHWF2R_RXCHCNT                          ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */

+#define ETH_MACHWF2R_TXQCNT_Pos                       (6U)

+#define ETH_MACHWF2R_TXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */

+#define ETH_MACHWF2R_TXQCNT                           ETH_MACHWF2R_TXQCNT_Msk  /* Number of MTL Transmit Queues */

+#define ETH_MACHWF2R_RXQCNT_Pos                       (0U)

+#define ETH_MACHWF2R_RXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */

+#define ETH_MACHWF2R_RXQCNT                           ETH_MACHWF2R_RXQCNT_Msk  /* Number of MTL Receive Queues */

+

+/* Bit definition for Ethernet MAC MDIO Address Register */

+#define ETH_MACMDIOAR_PSE_Pos                         (27U)

+#define ETH_MACMDIOAR_PSE_Msk                         (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */

+#define ETH_MACMDIOAR_PSE                             ETH_MACMDIOAR_PSE_Msk    /* Preamble Suppression Enable */

+#define ETH_MACMDIOAR_BTB_Pos                         (26U)

+#define ETH_MACMDIOAR_BTB_Msk                         (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */

+#define ETH_MACMDIOAR_BTB                             ETH_MACMDIOAR_BTB_Msk    /* Back to Back transactions */

+#define ETH_MACMDIOAR_PA_Pos                          (21U)

+#define ETH_MACMDIOAR_PA_Msk                          (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */

+#define ETH_MACMDIOAR_PA                              ETH_MACMDIOAR_PA_Msk     /* Physical Layer Address */

+#define ETH_MACMDIOAR_RDA_Pos                         (16U)

+#define ETH_MACMDIOAR_RDA_Msk                         (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */

+#define ETH_MACMDIOAR_RDA                             ETH_MACMDIOAR_RDA_Msk    /* Register/Device Address */

+#define ETH_MACMDIOAR_NTC_Pos                         (12U)

+#define ETH_MACMDIOAR_NTC_Msk                         (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */

+#define ETH_MACMDIOAR_NTC                             ETH_MACMDIOAR_NTC_Msk    /* Number of Trailing Clocks */

+#define ETH_MACMDIOAR_CR_Pos                          (8U)

+#define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */

+#define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */

+#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */

+#define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)

+#define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */

+#define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */

+#define ETH_MACMDIOAR_CR_DIV16_Pos                    (9U)

+#define ETH_MACMDIOAR_CR_DIV16_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */

+#define ETH_MACMDIOAR_CR_DIV16                        ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */

+#define ETH_MACMDIOAR_CR_DIV26_Pos                    (8U)

+#define ETH_MACMDIOAR_CR_DIV26_Msk                    (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */

+#define ETH_MACMDIOAR_CR_DIV26                        ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */

+#define ETH_MACMDIOAR_CR_DIV102_Pos                   (10U)

+#define ETH_MACMDIOAR_CR_DIV102_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */

+#define ETH_MACMDIOAR_CR_DIV102                       ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */

+#define ETH_MACMDIOAR_CR_DIV124_Pos                   (8U)

+#define ETH_MACMDIOAR_CR_DIV124_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */

+#define ETH_MACMDIOAR_CR_DIV124                       ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */

+#define ETH_MACMDIOAR_CR_DIV4AR_Pos                   (11U)

+#define ETH_MACMDIOAR_CR_DIV4AR_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */

+#define ETH_MACMDIOAR_CR_DIV4AR                       ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV6AR_Pos                   (8U)

+#define ETH_MACMDIOAR_CR_DIV6AR_Msk                   (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */

+#define ETH_MACMDIOAR_CR_DIV6AR                       ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV8AR_Pos                   (9U)

+#define ETH_MACMDIOAR_CR_DIV8AR_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */

+#define ETH_MACMDIOAR_CR_DIV8AR                       ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV10AR_Pos                  (8U)

+#define ETH_MACMDIOAR_CR_DIV10AR_Msk                  (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */

+#define ETH_MACMDIOAR_CR_DIV10AR                      ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV12AR_Pos                  (10U)

+#define ETH_MACMDIOAR_CR_DIV12AR_Msk                  (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */

+#define ETH_MACMDIOAR_CR_DIV12AR                      ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV14AR_Pos                  (8U)

+#define ETH_MACMDIOAR_CR_DIV14AR_Msk                  (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */

+#define ETH_MACMDIOAR_CR_DIV14AR                      ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV16AR_Pos                  (9U)

+#define ETH_MACMDIOAR_CR_DIV16AR_Msk                  (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */

+#define ETH_MACMDIOAR_CR_DIV16AR                      ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV18AR_Pos                  (8U)

+#define ETH_MACMDIOAR_CR_DIV18AR_Msk                  (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */

+#define ETH_MACMDIOAR_CR_DIV18AR                      ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_SKAP_Pos                        (4U)

+#define ETH_MACMDIOAR_SKAP_Msk                        (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */

+#define ETH_MACMDIOAR_SKAP                            ETH_MACMDIOAR_SKAP_Msk   /* Skip Address Packet */

+#define ETH_MACMDIOAR_MOC_Pos                         (2U)

+#define ETH_MACMDIOAR_MOC_Msk                         (0x3UL << ETH_MACMDIOAR_MOC_Pos) /*!< 0x0000000C */

+#define ETH_MACMDIOAR_MOC                             ETH_MACMDIOAR_MOC_Msk    /* MII Operation Command */

+#define ETH_MACMDIOAR_MOC_WR_Pos                      (2U)

+#define ETH_MACMDIOAR_MOC_WR_Msk                      (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos) /*!< 0x00000004 */

+#define ETH_MACMDIOAR_MOC_WR                          ETH_MACMDIOAR_MOC_WR_Msk /* Write */

+#define ETH_MACMDIOAR_MOC_PRDIA_Pos                   (3U)

+#define ETH_MACMDIOAR_MOC_PRDIA_Msk                   (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos) /*!< 0x00000008 */

+#define ETH_MACMDIOAR_MOC_PRDIA                       ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */

+#define ETH_MACMDIOAR_MOC_RD_Pos                      (2U)

+#define ETH_MACMDIOAR_MOC_RD_Msk                      (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos) /*!< 0x0000000C */

+#define ETH_MACMDIOAR_MOC_RD                          ETH_MACMDIOAR_MOC_RD_Msk /* Read */

+#define ETH_MACMDIOAR_C45E_Pos                        (1U)

+#define ETH_MACMDIOAR_C45E_Msk                        (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */

+#define ETH_MACMDIOAR_C45E                            ETH_MACMDIOAR_C45E_Msk   /* Clause 45 PHY Enable */

+#define ETH_MACMDIOAR_MB_Pos                          (0U)

+#define ETH_MACMDIOAR_MB_Msk                          (0x1UL << ETH_MACMDIOAR_MB_Pos) /*!< 0x00000001 */

+#define ETH_MACMDIOAR_MB                              ETH_MACMDIOAR_MB_Msk     /* MII Busy */

+

+/* Bit definition for Ethernet MAC MDIO Data Register */

+#define ETH_MACMDIODR_RA_Pos                          (16U)

+#define ETH_MACMDIODR_RA_Msk                          (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */

+#define ETH_MACMDIODR_RA                              ETH_MACMDIODR_RA_Msk     /* Register Address */

+#define ETH_MACMDIODR_MD_Pos                          (0U)

+#define ETH_MACMDIODR_MD_Msk                          (0xFFFFUL << ETH_MACMDIODR_MD_Pos) /*!< 0x0000FFFF */

+#define ETH_MACMDIODR_MD                              ETH_MACMDIODR_MD_Msk     /* MII Data */

+

+/* Bit definition for Ethernet ARP Address Register */

+#define ETH_MACARPAR_ARPPA_Pos                         (0U)

+#define ETH_MACARPAR_ARPPA_Msk                         (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACARPAR_ARPPA                             ETH_MACARPAR_ARPPA_Msk     /* ARP Protocol Address */

+

+/* Bit definition for Ethernet MAC Address 0 High Register */

+#define ETH_MACA0HR_AE_Pos                            (31U)

+#define ETH_MACA0HR_AE_Msk                            (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA0HR_AE                                ETH_MACA0HR_AE_Msk /* Address Enable*/

+#define ETH_MACA0HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA0HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA0HR_ADDRHI                            ETH_MACA0HR_ADDRHI_Msk   /* MAC Address 0*/

+

+/* Bit definition for Ethernet MAC Address 0 Low Register */

+#define ETH_MACA0LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA0LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA0LR_ADDRLO                            ETH_MACA0LR_ADDRLO_Msk   /* MAC Address 0*/

+

+/* Bit definition for Ethernet MAC Address 1 High Register */

+#define ETH_MACA1HR_AE_Pos                            (31U)

+#define ETH_MACA1HR_AE_Msk                            (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk /* Address Enable*/

+#define ETH_MACA1HR_SA_Pos                            (30U)

+#define ETH_MACA1HR_SA_Msk                            (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk /* Source Address */

+#define ETH_MACA1HR_MBC_Pos                           (24U)

+#define ETH_MACA1HR_MBC_Msk                           (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk /* Mask Byte Control */

+#define ETH_MACA1HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA1HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA1HR_ADDRHI                            ETH_MACA1HR_ADDRHI_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 1 Low Register */

+#define ETH_MACA1LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA1LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA1LR_ADDRLO                            ETH_MACA1LR_ADDRLO_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 2 High Register */

+#define ETH_MACA2HR_AE_Pos                            (31U)

+#define ETH_MACA2HR_AE_Msk                            (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk /* Address Enable*/

+#define ETH_MACA2HR_SA_Pos                            (30U)

+#define ETH_MACA2HR_SA_Msk                            (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk /* Source Address */

+#define ETH_MACA2HR_MBC_Pos                           (24U)

+#define ETH_MACA2HR_MBC_Msk                           (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk /* Mask Byte Control */

+#define ETH_MACA2HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA2HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA2HR_ADDRHI                            ETH_MACA2HR_ADDRHI_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 2 Low Register */

+#define ETH_MACA2LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA2LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA2LR_ADDRLO                            ETH_MACA2LR_ADDRLO_Msk   /* MAC Address 2*/

+

+/* Bit definition for Ethernet MAC Address 3 High Register */

+#define ETH_MACA3HR_AE_Pos                            (31U)

+#define ETH_MACA3HR_AE_Msk                            (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk /* Address Enable*/

+#define ETH_MACA3HR_SA_Pos                            (30U)

+#define ETH_MACA3HR_SA_Msk                            (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk /* Source Address */

+#define ETH_MACA3HR_MBC_Pos                           (24U)

+#define ETH_MACA3HR_MBC_Msk                           (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk /* Mask Byte Control */

+#define ETH_MACA3HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA3HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA3HR_ADDRHI                            ETH_MACA3HR_ADDRHI_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 3 Low Register */

+#define ETH_MACA3LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA3LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA3LR_ADDRLO                            ETH_MACA3LR_ADDRLO_Msk   /* MAC Address 3*/

+

+/* Bit definition for Ethernet MAC Address High Register */

+#define ETH_MACAHR_AE_Pos                             (31U)

+#define ETH_MACAHR_AE_Msk                             (0x1UL << ETH_MACAHR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACAHR_AE                                 ETH_MACAHR_AE_Msk        /* Address enable */

+#define ETH_MACAHR_SA_Pos                             (30U)

+#define ETH_MACAHR_SA_Msk                             (0x1UL << ETH_MACAHR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACAHR_SA                                 ETH_MACAHR_SA_Msk        /* Source address */

+#define ETH_MACAHR_MBC_Pos                            (24U)

+#define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */

+#define ETH_MACAHR_MBC_HBITS15_8                      ((uint32_t)0x20000000)   /* Mask MAC Address high reg bits [15:8] */

+#define ETH_MACAHR_MBC_HBITS7_0                       ((uint32_t)0x10000000)   /* Mask MAC Address high reg bits [7:0] */

+#define ETH_MACAHR_MBC_LBITS31_24                     ((uint32_t)0x08000000)   /* Mask MAC Address low reg bits [31:24] */

+#define ETH_MACAHR_MBC_LBITS23_16                     ((uint32_t)0x04000000)   /* Mask MAC Address low reg bits [23:16] */

+#define ETH_MACAHR_MBC_LBITS15_8                      ((uint32_t)0x02000000)   /* Mask MAC Address low reg bits [15:8] */

+#define ETH_MACAHR_MBC_LBITS7_0                       ((uint32_t)0x01000000)   /* Mask MAC Address low reg bits [7:0] */

+#define ETH_MACAHR_MACAH_Pos                          (0U)

+#define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */

+#define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */

+

+/* Bit definition for Ethernet MAC Address Low Register */

+#define ETH_MACALR_MACAL_Pos                          (0U)

+#define ETH_MACALR_MACAL_Msk                          (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACALR_MACAL                              ETH_MACALR_MACAL_Msk     /* MAC address low */

+

+/* Bit definition for Ethernet MMC Control Register */

+#define ETH_MMCCR_UCDBC_Pos                           (8U)

+#define ETH_MMCCR_UCDBC_Msk                           (0x1UL << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */

+#define ETH_MMCCR_UCDBC                               ETH_MMCCR_UCDBC_Msk  /* Update MMC Counters for Dropped Broadcast Packets */

+#define ETH_MMCCR_CNTPRSTLVL_Pos                      (5U)

+#define ETH_MMCCR_CNTPRSTLVL_Msk                      (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */

+#define ETH_MMCCR_CNTPRSTLVL                          ETH_MMCCR_CNTPRSTLVL_Msk  /* Full-Half Preset */

+#define ETH_MMCCR_CNTPRST_Pos                         (4U)

+#define ETH_MMCCR_CNTPRST_Msk                         (0x1UL << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */

+#define ETH_MMCCR_CNTPRST                             ETH_MMCCR_CNTPRST_Msk  /* Counters Reset */

+#define ETH_MMCCR_CNTFREEZ_Pos                        (3U)

+#define ETH_MMCCR_CNTFREEZ_Msk                        (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */

+#define ETH_MMCCR_CNTFREEZ                            ETH_MMCCR_CNTFREEZ_Msk  /* MMC Counter Freeze */

+#define ETH_MMCCR_RSTONRD_Pos                         (2U)

+#define ETH_MMCCR_RSTONRD_Msk                         (0x1UL << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */

+#define ETH_MMCCR_RSTONRD                             ETH_MMCCR_RSTONRD_Msk  /* Reset On Read */

+#define ETH_MMCCR_CNTSTOPRO_Pos                       (1U)

+#define ETH_MMCCR_CNTSTOPRO_Msk                       (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */

+#define ETH_MMCCR_CNTSTOPRO                           ETH_MMCCR_CNTSTOPRO_Msk  /* Counter Stop Rollover */

+#define ETH_MMCCR_CNTRST_Pos                          (0U)

+#define ETH_MMCCR_CNTRST_Msk                          (0x1UL << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */

+#define ETH_MMCCR_CNTRST                              ETH_MMCCR_CNTRST_Msk  /* Counters Reset */

+

+/* Bit definition for Ethernet MMC Rx Interrupt Register */

+#define ETH_MMCRIR_RXLPITRCIS_Pos                     (27U)

+#define ETH_MMCRIR_RXLPITRCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) /*!< 0x08000000 */

+#define ETH_MMCRIR_RXLPITRCIS                         ETH_MMCRIR_RXLPITRCIS_Msk  /* MMC Receive LPI transition counter interrupt status */

+#define ETH_MMCRIR_RXLPIUSCIS_Pos                     (26U)

+#define ETH_MMCRIR_RXLPIUSCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */

+#define ETH_MMCRIR_RXLPIUSCIS                         ETH_MMCRIR_RXLPIUSCIS_Msk  /* MMC Receive LPI microsecond counter interrupt status */

+#define ETH_MMCRIR_RXUCGPIS_Pos                       (17U)

+#define ETH_MMCRIR_RXUCGPIS_Msk                       (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) /*!< 0x00020000 */

+#define ETH_MMCRIR_RXUCGPIS                           ETH_MMCRIR_RXUCGPIS_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Status */

+#define ETH_MMCRIR_RXALGNERPIS_Pos                    (6U)

+#define ETH_MMCRIR_RXALGNERPIS_Msk                    (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) /*!< 0x00000040 */

+#define ETH_MMCRIR_RXALGNERPIS                        ETH_MMCRIR_RXALGNERPIS_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Status */

+#define ETH_MMCRIR_RXCRCERPIS_Pos                     (5U)

+#define ETH_MMCRIR_RXCRCERPIS_Msk                     (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) /*!< 0x00000020 */

+#define ETH_MMCRIR_RXCRCERPIS                         ETH_MMCRIR_RXCRCERPIS_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Status */

+

+/* Bit definition for Ethernet MMC Tx Interrupt Register */

+#define ETH_MMCTIR_TXLPITRCIS_Pos                     (27U)

+#define ETH_MMCTIR_TXLPITRCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) /*!< 0x08000000 */

+#define ETH_MMCTIR_TXLPITRCIS                         ETH_MMCTIR_TXLPITRCIS_Msk  /* MMC Transmit LPI transition counter interrupt status */

+#define ETH_MMCTIR_TXLPIUSCIS_Pos                     (26U)

+#define ETH_MMCTIR_TXLPIUSCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */

+#define ETH_MMCTIR_TXLPIUSCIS                         ETH_MMCTIR_TXLPIUSCIS_Msk  /* MMC Transmit LPI microsecond counter interrupt status */

+#define ETH_MMCTIR_TXGPKTIS_Pos                       (21U)

+#define ETH_MMCTIR_TXGPKTIS_Msk                       (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) /*!< 0x00200000 */

+#define ETH_MMCTIR_TXGPKTIS                           ETH_MMCTIR_TXGPKTIS_Msk  /* MMC Transmit Good Packet Counter Interrupt Status */

+#define ETH_MMCTIR_TXMCOLGPIS_Pos                     (15U)

+#define ETH_MMCTIR_TXMCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */

+#define ETH_MMCTIR_TXMCOLGPIS                         ETH_MMCTIR_TXMCOLGPIS_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */

+#define ETH_MMCTIR_TXSCOLGPIS_Pos                     (14U)

+#define ETH_MMCTIR_TXSCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */

+#define ETH_MMCTIR_TXSCOLGPIS                         ETH_MMCTIR_TXSCOLGPIS_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */

+

+/* Bit definition for Ethernet MMC Rx interrupt Mask register */

+#define ETH_MMCRIMR_RXLPITRCIM_Pos                    (27U)

+#define ETH_MMCRIMR_RXLPITRCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */

+#define ETH_MMCRIMR_RXLPITRCIM                        ETH_MMCRIMR_RXLPITRCIM_Msk  /* MMC Receive LPI transition counter interrupt Mask */

+#define ETH_MMCRIMR_RXLPIUSCIM_Pos                    (26U)

+#define ETH_MMCRIMR_RXLPIUSCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */

+#define ETH_MMCRIMR_RXLPIUSCIM                        ETH_MMCRIMR_RXLPIUSCIM_Msk  /* MMC Receive LPI microsecond counter interrupt Mask */

+#define ETH_MMCRIMR_RXUCGPIM_Pos                      (17U)

+#define ETH_MMCRIMR_RXUCGPIM_Msk                      (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) /*!< 0x00020000 */

+#define ETH_MMCRIMR_RXUCGPIM                          ETH_MMCRIMR_RXUCGPIM_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Mask */

+#define ETH_MMCRIMR_RXALGNERPIM_Pos                   (6U)

+#define ETH_MMCRIMR_RXALGNERPIM_Msk                   (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */

+#define ETH_MMCRIMR_RXALGNERPIM                       ETH_MMCRIMR_RXALGNERPIM_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Mask */

+#define ETH_MMCRIMR_RXCRCERPIM_Pos                    (5U)

+#define ETH_MMCRIMR_RXCRCERPIM_Msk                    (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */

+#define ETH_MMCRIMR_RXCRCERPIM                        ETH_MMCRIMR_RXCRCERPIM_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Mask */

+

+/* Bit definition for Ethernet MMC Tx Interrupt Mask Register */

+#define ETH_MMCTIMR_TXLPITRCIM_Pos                    (27U)

+#define ETH_MMCTIMR_TXLPITRCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */

+#define ETH_MMCTIMR_TXLPITRCIM                        ETH_MMCTIMR_TXLPITRCIM_Msk  /* MMC Transmit LPI transition counter interrupt Mask*/

+#define ETH_MMCTIMR_TXLPIUSCIM_Pos                    (26U)

+#define ETH_MMCTIMR_TXLPIUSCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */

+#define ETH_MMCTIMR_TXLPIUSCIM                        ETH_MMCTIMR_TXLPIUSCIM_Msk  /* MMC Transmit LPI microsecond counter interrupt Mask*/

+#define ETH_MMCTIMR_TXGPKTIM_Pos                      (21U)

+#define ETH_MMCTIMR_TXGPKTIM_Msk                      (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) /*!< 0x00200000 */

+#define ETH_MMCTIMR_TXGPKTIM                          ETH_MMCTIMR_TXGPKTIM_Msk  /* MMC Transmit Good Packet Counter Interrupt Mask*/

+#define ETH_MMCTIMR_TXMCOLGPIM_Pos                    (15U)

+#define ETH_MMCTIMR_TXMCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */

+#define ETH_MMCTIMR_TXMCOLGPIM                        ETH_MMCTIMR_TXMCOLGPIM_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */

+#define ETH_MMCTIMR_TXSCOLGPIM_Pos                    (14U)

+#define ETH_MMCTIMR_TXSCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */

+#define ETH_MMCTIMR_TXSCOLGPIM                        ETH_MMCTIMR_TXSCOLGPIM_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */

+

+/* Bit definition for Ethernet MMC Tx Single Collision Good Packets Register */

+#define ETH_MMCTSCGPR_TXSNGLCOLG_Pos                  (0U)

+#define ETH_MMCTSCGPR_TXSNGLCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTSCGPR_TXSNGLCOLG                      ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */

+

+/* Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register */

+#define ETH_MMCTMCGPR_TXMULTCOLG_Pos                  (0U)

+#define ETH_MMCTMCGPR_TXMULTCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTMCGPR_TXMULTCOLG                      ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */

+

+/* Bit definition for Ethernet MMC Tx Packet Count Good Register */

+#define ETH_MMCTPCGR_TXPKTG_Pos                       (0U)

+#define ETH_MMCTPCGR_TXPKTG_msk                       (0xFFFFFFFFUL <<  ETH_MMCTPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTPCGR_TXPKTG                           ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */

+

+/* Bit definition for Ethernet MMC Rx CRC Error Packets Register */

+#define ETH_MMCRCRCEPR_RXCRCERR_Pos                   (0U)

+#define ETH_MMCRCRCEPR_RXCRCERR_msk                   (0xFFFFFFFFUL <<  ETH_MMCRCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRCRCEPR_RXCRCERR                       ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */

+

+/* Bit definition for Ethernet MMC Rx alignment error packets register */

+#define ETH_MMCRAEPR_RXALGNERR_Pos                    (0U)

+#define ETH_MMCRAEPR_RXALGNERR_msk                    (0xFFFFFFFFUL <<  ETH_MMCRAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRAEPR_RXALGNERR                        ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */

+

+/* Bit definition for Ethernet MMC Rx Unicast Packets Good Register */

+#define ETH_MMCRUPGR_RXUCASTG_Pos                     (0U)

+#define ETH_MMCRUPGR_RXUCASTG_msk                     (0xFFFFFFFFUL <<  ETH_MMCRUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRUPGR_RXUCASTG                         ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */

+

+/* Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register */

+#define ETH_MMCTLPIMSTR_TXLPIUSC_Pos                  (0U)

+#define ETH_MMCTLPIMSTR_TXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCTLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTLPIMSTR_TXLPIUSC                      ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */

+

+/* Bit definition for Ethernet MMC Tx LPI Transition Counter Register */

+#define ETH_MMCTLPITCR_TXLPITRC_Pos                   (0U)

+#define ETH_MMCTLPITCR_TXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCTLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTLPITCR_TXLPITRC                       ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */

+

+/* Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register */

+#define ETH_MMCRLPIMSTR_RXLPIUSC_Pos                  (0U)

+#define ETH_MMCRLPIMSTR_RXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCRLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRLPIMSTR_RXLPIUSC                      ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */

+

+/* Bit definition for Ethernet MMC Rx LPI Transition Counter Register */

+#define ETH_MMCRLPITCR_RXLPITRC_Pos                   (0U)

+#define ETH_MMCRLPITCR_RXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCRLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRLPITCR_RXLPITRC                       ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */

+

+/* Bit definition for Ethernet MAC L3 L4 Control Register */

+#define ETH_MACL3L4CR_L4DPIM_Pos                      (21U)

+#define ETH_MACL3L4CR_L4DPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos) /*!< 0x00200000 */

+#define ETH_MACL3L4CR_L4DPIM                          ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */

+#define ETH_MACL3L4CR_L4DPM_Pos                       (20U)

+#define ETH_MACL3L4CR_L4DPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4DPM_Pos) /*!< 0x00100000 */

+#define ETH_MACL3L4CR_L4DPM                           ETH_MACL3L4CR_L4DPM_Msk  /* Layer 4 Destination Port Match Enable */

+#define ETH_MACL3L4CR_L4SPIM_Pos                      (19U)

+#define ETH_MACL3L4CR_L4SPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos) /*!< 0x00080000 */

+#define ETH_MACL3L4CR_L4SPIM                          ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */

+#define ETH_MACL3L4CR_L4SPM_Pos                       (18U)

+#define ETH_MACL3L4CR_L4SPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4SPM_Pos) /*!< 0x00040000 */

+#define ETH_MACL3L4CR_L4SPM                           ETH_MACL3L4CR_L4SPM_Msk  /* Layer 4 Source Port Match Enable */

+#define ETH_MACL3L4CR_L4PEN_Pos                       (16U)

+#define ETH_MACL3L4CR_L4PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L4PEN_Pos) /*!< 0x00010000 */

+#define ETH_MACL3L4CR_L4PEN                           ETH_MACL3L4CR_L4PEN_Msk  /* Layer 4 Protocol Enable */

+#define ETH_MACL3L4CR_L3HDBM_Pos                      (11U)

+#define ETH_MACL3L4CR_L3HDBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos) /*!< 0x0000F800 */

+#define ETH_MACL3L4CR_L3HDBM                          ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */

+#define ETH_MACL3L4CR_L3HSBM_Pos                      (6U)

+#define ETH_MACL3L4CR_L3HSBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos) /*!< 0x000007C0 */

+#define ETH_MACL3L4CR_L3HSBM                          ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */

+#define ETH_MACL3L4CR_L3DAIM_Pos                      (5U)

+#define ETH_MACL3L4CR_L3DAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos) /*!< 0x00000020 */

+#define ETH_MACL3L4CR_L3DAIM                          ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */

+#define ETH_MACL3L4CR_L3DAM_Pos                       (4U)

+#define ETH_MACL3L4CR_L3DAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3DAM_Pos) /*!< 0x00000010 */

+#define ETH_MACL3L4CR_L3DAM                           ETH_MACL3L4CR_L3DAM_Msk  /* Layer 3 IP DA Match Enable */

+#define ETH_MACL3L4CR_L3SAIM_Pos                      (3U)

+#define ETH_MACL3L4CR_L3SAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos) /*!< 0x00000008 */

+#define ETH_MACL3L4CR_L3SAIM                          ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */

+#define ETH_MACL3L4CR_L3SAM_Pos                       (2U)

+#define ETH_MACL3L4CR_L3SAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3SAM_Pos) /*!< 0x00000004 */

+#define ETH_MACL3L4CR_L3SAM                           ETH_MACL3L4CR_L3SAM_Msk  /* Layer 3 IP SA Match Enable*/

+#define ETH_MACL3L4CR_L3PEN_Pos                       (0U)

+#define ETH_MACL3L4CR_L3PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L3PEN_Pos) /*!< 0x00000001 */

+#define ETH_MACL3L4CR_L3PEN                           ETH_MACL3L4CR_L3PEN_Msk  /* Layer 3 Protocol Enable */

+

+/* Bit definition for Ethernet MAC L4 Address Register */

+#define ETH_MACL4AR_L4DP_Pos                          (16U)

+#define ETH_MACL4AR_L4DP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4DP_Pos) /*!< 0xFFFF0000 */

+#define ETH_MACL4AR_L4DP                              ETH_MACL4AR_L4DP_Msk     /* Layer 4 Destination Port Number Field */

+#define ETH_MACL4AR_L4SP_Pos                          (0U)

+#define ETH_MACL4AR_L4SP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4SP_Pos) /*!< 0x0000FFFF */

+#define ETH_MACL4AR_L4SP                              ETH_MACL4AR_L4SP_Msk     /* Layer 4 Source Port Number Field */

+

+/* Bit definition for Ethernet MAC L3 Address0 Register */

+#define ETH_MACL3A0R_L3A0_Pos                         (0U)

+#define ETH_MACL3A0R_L3A0_Msk                         (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A0R_L3A0                             ETH_MACL3A0R_L3A0_Msk    /* Layer 3 Address 0 Field */

+

+/* Bit definition for Ethernet MAC L4 Address1 Register */

+#define ETH_MACL3A1R_L3A1_Pos                         (0U)

+#define ETH_MACL3A1R_L3A1_Msk                         (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A1R_L3A1                             ETH_MACL3A1R_L3A1_Msk    /* Layer 3 Address 1 Field */

+

+/* Bit definition for Ethernet MAC L4 Address2 Register */

+#define ETH_MACL3A2R_L3A2_Pos                         (0U)

+#define ETH_MACL3A2R_L3A2_Msk                         (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A2R_L3A2                             ETH_MACL3A2R_L3A2_Msk    /* Layer 3 Address 2 Field */

+

+/* Bit definition for Ethernet MAC L4 Address3 Register */

+#define ETH_MACL3A3R_L3A3_Pos                         (0U)

+#define ETH_MACL3A3R_L3A3_Msk                         (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A3R_L3A3                             ETH_MACL3A3R_L3A3_Msk    /* Layer 3 Address 3 Field */

+

+/* Bit definition for Ethernet MAC Timestamp Control Register */

+#define ETH_MACTSCR_TXTSSTSM_Pos                      (24U)

+#define ETH_MACTSCR_TXTSSTSM_Msk                      (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */

+#define ETH_MACTSCR_TXTSSTSM                          ETH_MACTSCR_TXTSSTSM_Msk  /* Transmit Timestamp Status Mode */

+#define ETH_MACTSCR_CSC_Pos                           (19U)

+#define ETH_MACTSCR_CSC_Msk                           (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */

+#define ETH_MACTSCR_CSC                               ETH_MACTSCR_CSC_Msk  /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */

+#define ETH_MACTSCR_TSENMACADDR_Pos                   (18U)

+#define ETH_MACTSCR_TSENMACADDR_Msk                   (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */

+#define ETH_MACTSCR_TSENMACADDR                       ETH_MACTSCR_TSENMACADDR_Msk  /* Enable MAC Address for PTP Packet Filtering */

+#define ETH_MACTSCR_SNAPTYPSEL_Pos                    (16U)

+#define ETH_MACTSCR_SNAPTYPSEL_Msk                    (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */

+#define ETH_MACTSCR_SNAPTYPSEL                        ETH_MACTSCR_SNAPTYPSEL_Msk  /* Select PTP packets for Taking Snapshots */

+#define ETH_MACTSCR_TSMSTRENA_Pos                     (15U)

+#define ETH_MACTSCR_TSMSTRENA_Msk                     (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */

+#define ETH_MACTSCR_TSMSTRENA                         ETH_MACTSCR_TSMSTRENA_Msk  /* Enable Snapshot for Messages Relevant to Master */

+#define ETH_MACTSCR_TSEVNTENA_Pos                     (14U)

+#define ETH_MACTSCR_TSEVNTENA_Msk                     (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */

+#define ETH_MACTSCR_TSEVNTENA                         ETH_MACTSCR_TSEVNTENA_Msk  /* Enable Timestamp Snapshot for Event Messages */

+#define ETH_MACTSCR_TSIPV4ENA_Pos                     (13U)

+#define ETH_MACTSCR_TSIPV4ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */

+#define ETH_MACTSCR_TSIPV4ENA                         ETH_MACTSCR_TSIPV4ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv4-UDP */

+#define ETH_MACTSCR_TSIPV6ENA_Pos                     (12U)

+#define ETH_MACTSCR_TSIPV6ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */

+#define ETH_MACTSCR_TSIPV6ENA                         ETH_MACTSCR_TSIPV6ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv6-UDP */

+#define ETH_MACTSCR_TSIPENA_Pos                       (11U)

+#define ETH_MACTSCR_TSIPENA_Msk                       (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */

+#define ETH_MACTSCR_TSIPENA                           ETH_MACTSCR_TSIPENA_Msk  /* Enable Processing of PTP over Ethernet Packets */

+#define ETH_MACTSCR_TSVER2ENA_Pos                     (10U)

+#define ETH_MACTSCR_TSVER2ENA_Msk                     (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */

+#define ETH_MACTSCR_TSVER2ENA                         ETH_MACTSCR_TSVER2ENA_Msk  /* Enable PTP Packet Processing for Version 2 Format */

+#define ETH_MACTSCR_TSCTRLSSR_Pos                     (9U)

+#define ETH_MACTSCR_TSCTRLSSR_Msk                     (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */

+#define ETH_MACTSCR_TSCTRLSSR                         ETH_MACTSCR_TSCTRLSSR_Msk  /* Timestamp Digital or Binary Rollover Control */

+#define ETH_MACTSCR_TSENALL_Pos                       (8U)

+#define ETH_MACTSCR_TSENALL_Msk                       (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */

+#define ETH_MACTSCR_TSENALL                           ETH_MACTSCR_TSENALL_Msk  /* Enable Timestamp for All Packets */

+#define ETH_MACTSCR_TSADDREG_Pos                      (5U)

+#define ETH_MACTSCR_TSADDREG_Msk                      (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */

+#define ETH_MACTSCR_TSADDREG                          ETH_MACTSCR_TSADDREG_Msk  /* Update Addend Register */

+#define ETH_MACTSCR_TSUPDT_Pos                        (3U)

+#define ETH_MACTSCR_TSUPDT_Msk                        (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */

+#define ETH_MACTSCR_TSUPDT                            ETH_MACTSCR_TSUPDT_Msk  /* Update Timestamp */

+#define ETH_MACTSCR_TSINIT_Pos                        (2U)

+#define ETH_MACTSCR_TSINIT_Msk                        (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */

+#define ETH_MACTSCR_TSINIT                             ETH_MACTSCR_TSINIT_Msk  /* Initialize Timestamp */

+#define ETH_MACTSCR_TSCFUPDT_Pos                      (1U)

+#define ETH_MACTSCR_TSCFUPDT_Msk                      (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */

+#define ETH_MACTSCR_TSCFUPDT                          ETH_MACTSCR_TSCFUPDT_Msk  /* Fine or Coarse Timestamp Update*/

+#define ETH_MACTSCR_TSENA_Pos                         (0U)

+#define ETH_MACTSCR_TSENA_Msk                         (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */

+#define ETH_MACTSCR_TSENA                             ETH_MACTSCR_TSENA_Msk  /* Enable Timestamp */

+

+/* Bit definition for Ethernet MAC Sub-second Increment Register */

+#define ETH_MACMACSSIR_SSINC_Pos                      (16U)

+#define ETH_MACMACSSIR_SSINC_Msk                      (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) /*!< 0x0000FF00 */

+#define ETH_MACMACSSIR_SSINC                          ETH_MACMACSSIR_SSINC_Msk  /* Sub-second Increment Value */

+#define ETH_MACMACSSIR_SNSINC_Pos                     (8U)

+#define ETH_MACMACSSIR_SNSINC_Msk                     (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos) /*!< 0x000000FF */

+#define ETH_MACMACSSIR_SNSINC                         ETH_MACMACSSIR_SNSINC_Msk  /* Sub-nanosecond Increment Value */

+

+/* Bit definition for Ethernet MAC System Time Seconds Register */

+#define ETH_MACSTSR_TSS_Pos                           (0U)

+#define ETH_MACSTSR_TSS_Msk                           (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSTSR_TSS                               ETH_MACSTSR_TSS_Msk  /* Timestamp Second */

+

+/* Bit definition for Ethernet MAC System Time Nanoseconds Register */

+#define ETH_MACSTNR_TSSS_Pos                          (0U)

+#define ETH_MACSTNR_TSSS_Msk                          (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACSTNR_TSSS                              ETH_MACSTNR_TSSS_Msk  /* Timestamp Sub-seconds */

+

+/* Bit definition for Ethernet MAC System Time Seconds Update Register */

+#define ETH_MACSTSUR_TSS_Pos                          (0U)

+#define ETH_MACSTSUR_TSS_Msk                          (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSTSUR_TSS                              ETH_MACSTSUR_TSS_Msk  /* Timestamp Seconds */

+

+/* Bit definition for Ethernet MAC System Time Nanoseconds Update Register */

+#define ETH_MACSTNUR_ADDSUB_Pos                       (31U)

+#define ETH_MACSTNUR_ADDSUB_Msk                       (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */

+#define ETH_MACSTNUR_ADDSUB                           ETH_MACSTNUR_ADDSUB_Msk  /* Add or Subtract Time */

+#define ETH_MACSTNUR_TSSS_Pos                         (0U)

+#define ETH_MACSTNUR_TSSS_Msk                         (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACSTNUR_TSSS                             ETH_MACSTNUR_TSSS_Msk  /* Timestamp Sub-seconds */

+

+/* Bit definition for Ethernet MAC Timestamp Addend Register */

+#define ETH_MACTSAR_TSAR_Pos                          (0U)

+#define ETH_MACTSAR_TSAR_Msk                          (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSAR_TSAR                              ETH_MACTSAR_TSAR_Msk  /* Timestamp Addend Register */

+

+/* Bit definition for Ethernet MAC Timestamp Status Register */

+#define ETH_MACTSSR_ATSNS_Pos                         (25U)

+#define ETH_MACTSSR_ATSNS_Msk                         (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */

+#define ETH_MACTSSR_ATSNS                             ETH_MACTSSR_ATSNS_Msk  /* Number of Auxiliary Timestamp Snapshots */

+#define ETH_MACTSSR_ATSSTM_Pos                        (24U)

+#define ETH_MACTSSR_ATSSTM_Msk                        (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */

+#define ETH_MACTSSR_ATSSTM                            ETH_MACTSSR_ATSSTM_Msk  /* Auxiliary Timestamp Snapshot Trigger Missed */

+#define ETH_MACTSSR_ATSSTN_Pos                        (16U)

+#define ETH_MACTSSR_ATSSTN_Msk                        (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */

+#define ETH_MACTSSR_ATSSTN                            ETH_MACTSSR_ATSSTN_Msk  /* Auxiliary Timestamp Snapshot Trigger Identifier */

+#define ETH_MACTSSR_TXTSSIS_Pos                       (15U)

+#define ETH_MACTSSR_TXTSSIS_Msk                       (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */

+#define ETH_MACTSSR_TXTSSIS                           ETH_MACTSSR_TXTSSIS_Msk  /* Tx Timestamp Status Interrupt Status */

+#define ETH_MACTSSR_TSTRGTERR0_Pos                    (3U)

+#define ETH_MACTSSR_TSTRGTERR0_Msk                    (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */

+#define ETH_MACTSSR_TSTRGTERR0                        ETH_MACTSSR_TSTRGTERR0_Msk  /* Timestamp Target Time Error */

+#define ETH_MACTSSR_AUXTSTRIG_Pos                     (2U)

+#define ETH_MACTSSR_AUXTSTRIG_Msk                     (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */

+#define ETH_MACTSSR_AUXTSTRIG                         ETH_MACTSSR_AUXTSTRIG_Msk  /* Auxiliary Timestamp Trigger Snapshot*/

+#define ETH_MACTSSR_TSTARGT0_Pos                      (1U)

+#define ETH_MACTSSR_TSTARGT0_Msk                      (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */

+#define ETH_MACTSSR_TSTARGT0                          ETH_MACTSSR_TSTARGT0_Msk  /* Timestamp Target Time Reached */

+#define ETH_MACTSSR_TSSOVF_Pos                        (0U)

+#define ETH_MACTSSR_TSSOVF_Msk                        (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */

+#define ETH_MACTSSR_TSSOVF                            ETH_MACTSSR_TSSOVF_Msk  /* Timestamp Seconds Overflow */

+

+/* Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register */

+#define ETH_MACTTSSNR_TXTSSMIS_Pos                    (31U)

+#define ETH_MACTTSSNR_TXTSSMIS_Msk                    (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */

+#define ETH_MACTTSSNR_TXTSSMIS                        ETH_MACTTSSNR_TXTSSMIS_Msk  /* Transmit Timestamp Status Missed */

+#define ETH_MACTTSSNR_TXTSSLO_Pos                     (0U)

+#define ETH_MACTTSSNR_TXTSSLO_Msk                     (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACTTSSNR_TXTSSLO                         ETH_MACTTSSNR_TXTSSLO_Msk  /* Transmit Timestamp Status Low */

+

+/* Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register */

+#define ETH_MACTTSSSR_TXTSSHI_Pos                     (0U)

+#define ETH_MACTTSSSR_TXTSSHI_Msk                     (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTTSSSR_TXTSSHI                         ETH_MACTTSSSR_TXTSSHI_Msk  /* Transmit Timestamp Status High */

+

+/* Bit definition for Ethernet MAC Auxiliary Control Register*/

+#define ETH_MACACR_ATSEN3_Pos                         (7U)

+#define ETH_MACACR_ATSEN3_Msk                         (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */

+#define ETH_MACACR_ATSEN3                             ETH_MACACR_ATSEN3_Msk  /* Auxiliary Snapshot 3 Enable */

+#define ETH_MACACR_ATSEN2_Pos                         (6U)

+#define ETH_MACACR_ATSEN2_Msk                         (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */

+#define ETH_MACACR_ATSEN2                             ETH_MACACR_ATSEN2_Msk  /* Auxiliary Snapshot 2 Enable */

+#define ETH_MACACR_ATSEN1_Pos                         (5U)

+#define ETH_MACACR_ATSEN1_Msk                         (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */

+#define ETH_MACACR_ATSEN1                             ETH_MACACR_ATSEN1_Msk  /* Auxiliary Snapshot 1 Enable */

+#define ETH_MACACR_ATSEN0_Pos                         (4U)

+#define ETH_MACACR_ATSEN0_Msk                         (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */

+#define ETH_MACACR_ATSEN0                             ETH_MACACR_ATSEN0_Msk  /* Auxiliary Snapshot 0 Enable */

+#define ETH_MACACR_ATSFC_Pos                          (0U)

+#define ETH_MACACR_ATSFC_Msk                          (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */

+#define ETH_MACACR_ATSFC                              ETH_MACACR_ATSFC_Msk  /* Auxiliary Snapshot FIFO Clear */

+

+/* Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register */

+#define ETH_MACATSNR_AUXTSLO_Pos                      (0U)

+#define ETH_MACATSNR_AUXTSLO_Msk                      (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACATSNR_AUXTSLO                          ETH_MACATSNR_AUXTSLO_Msk  /* Auxiliary Timestamp */

+

+/* Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register */

+#define ETH_MACATSSR_AUXTSHI_Pos                      (0U)

+#define ETH_MACATSSR_AUXTSHI_Msk                      (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACATSSR_AUXTSHI                          ETH_MACATSSR_AUXTSHI_Msk  /* Auxiliary Timestamp */

+

+/* Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register */

+#define ETH_MACTSIACR_OSTIAC_Pos                      (0U)

+#define ETH_MACTSIACR_OSTIAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSIACR_OSTIAC                          ETH_MACTSIACR_OSTIAC_Msk  /* One-Step Timestamp Ingress Asymmetry Correction */

+

+/* Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction Register */

+#define ETH_MACTSEACR_OSTEAC_Pos                      (0U)

+#define ETH_MACTSEACR_OSTEAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSEACR_OSTEAC                          ETH_MACTSEACR_OSTEAC_Msk  /* One-Step Timestamp Egress Asymmetry Correction */

+

+/* Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond Register */

+#define ETH_MACTSICNR_TSIC_Pos                        (0U)

+#define ETH_MACTSICNR_TSIC_Msk                        (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSICNR_TSIC                            ETH_MACTSICNR_TSIC_Msk  /* Timestamp Ingress Correction */

+

+/* Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond Register */

+#define ETH_MACTSECNR_TSEC_Pos                        (0U)

+#define ETH_MACTSECNR_TSEC_Msk                        (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSECNR_TSEC                            ETH_MACTSECNR_TSEC_Msk  /* Timestamp Egress Correction */

+

+/* Bit definition for Ethernet MAC PPS Control Register */

+#define ETH_MACPPSCR_TRGTMODSEL0_Pos                  (5U)

+#define ETH_MACPPSCR_TRGTMODSEL0_Msk                  (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */

+#define ETH_MACPPSCR_TRGTMODSEL0                      ETH_MACPPSCR_TRGTMODSEL0_Msk  /* Target Time Register Mode for PPS Output */

+#define ETH_MACPPSCR_PPSEN0_Pos                       (4U)

+#define ETH_MACPPSCR_PPSEN0_Msk                       (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */

+#define ETH_MACPPSCR_PPSEN0                           ETH_MACPPSCR_PPSEN0_Msk  /* Flexible PPS Output Mode Enable */

+#define ETH_MACPPSCR_PPSCTRL_Pos                      (0U)

+#define ETH_MACPPSCR_PPSCTRL_Msk                      (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */

+#define ETH_MACPPSCR_PPSCTRL                          ETH_MACPPSCR_PPSCTRL_Msk  /* PPS Output Frequency Control */

+

+/* Bit definition for Ethernet MAC PPS Target Time Seconds Register */

+#define ETH_MACPPSTTSR_TSTRH0_Pos                     (0U)

+#define ETH_MACPPSTTSR_TSTRH0_Msk                     (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACPPSTTSR_TSTRH0                         ETH_MACPPSTTSR_TSTRH0_Msk  /* PPS Target Time Seconds Register */

+

+/* Bit definition for Ethernet MAC PPS Target Time Nanoseconds Register */

+#define ETH_MACPPSTTNR_TRGTBUSY0_Pos                  (31U)

+#define ETH_MACPPSTTNR_TRGTBUSY0_Msk                  (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos) /*!< 0x80000000 */

+#define ETH_MACPPSTTNR_TRGTBUSY0                      ETH_MACPPSTTNR_TRGTBUSY0_Msk  /* PPS Target Time Register Busy */

+#define ETH_MACPPSTTNR_TTSL0_Pos                      (0U)

+#define ETH_MACPPSTTNR_TTSL0_Msk                      (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACPPSTTNR_TTSL0                          ETH_MACPPSTTNR_TTSL0_Msk  /* Target Time Low for PPS Register */

+

+/* Bit definition for Ethernet MAC PPS Interval Register */

+#define ETH_MACPPSIR_PPSINT0_Pos                      (0U)

+#define ETH_MACPPSIR_PPSINT0_Msk                      (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACPPSIR_PPSINT0                          ETH_MACPPSIR_PPSINT0_Msk  /* PPS Output Signal Interval */

+

+/* Bit definition for Ethernet MAC PPS Width Register */

+#define ETH_MACPPSWR_PPSWIDTH0_Pos                    (0U)

+#define ETH_MACPPSWR_PPSWIDTH0_Msk                    (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACPPSWR_PPSWIDTH0                        ETH_MACPPSWR_PPSWIDTH0_Msk  /* PPS Output Signal Width */

+

+/* Bit definition for Ethernet MAC PTP Offload Control Register */

+#define ETH_MACPOCR_DN_Pos                            (8U)

+#define ETH_MACPOCR_DN_Msk                            (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */

+#define ETH_MACPOCR_DN                                ETH_MACPOCR_DN_Msk  /* Domain Number */

+#define ETH_MACPOCR_DRRDIS_Pos                        (6U)

+#define ETH_MACPOCR_DRRDIS_Msk                        (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */

+#define ETH_MACPOCR_DRRDIS                            ETH_MACPOCR_DRRDIS_Msk  /* Disable PTO Delay Request/Response response generation */

+#define ETH_MACPOCR_APDREQTRIG_Pos                    (5U)

+#define ETH_MACPOCR_APDREQTRIG_Msk                    (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */

+#define ETH_MACPOCR_APDREQTRIG                        ETH_MACPOCR_APDREQTRIG_Msk  /* Automatic PTP Pdelay_Req message Trigger */

+#define ETH_MACPOCR_ASYNCTRIG_Pos                     (4U)

+#define ETH_MACPOCR_ASYNCTRIG_Msk                     (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */

+#define ETH_MACPOCR_ASYNCTRIG                         ETH_MACPOCR_ASYNCTRIG_Msk  /* Automatic PTP SYNC message Trigger */

+#define ETH_MACPOCR_APDREQEN_Pos                      (2U)

+#define ETH_MACPOCR_APDREQEN_Msk                      (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */

+#define ETH_MACPOCR_APDREQEN                          ETH_MACPOCR_APDREQEN_Msk  /* Automatic PTP Pdelay_Req message Enable */

+#define ETH_MACPOCR_ASYNCEN_Pos                       (1U)

+#define ETH_MACPOCR_ASYNCEN_Msk                       (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */

+#define ETH_MACPOCR_ASYNCEN                           ETH_MACPOCR_ASYNCEN_Msk  /* Automatic PTP SYNC message Enable */

+#define ETH_MACPOCR_PTOEN_Pos                         (0U)

+#define ETH_MACPOCR_PTOEN_Msk                         (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */

+#define ETH_MACPOCR_PTOEN                             ETH_MACPOCR_PTOEN_Msk  /* PTP Offload Enable */

+

+/* Bit definition for Ethernet MAC PTP Source Port Identity 0 Register */

+#define ETH_MACSPI0R_SPI0_Pos                         (0U)

+#define ETH_MACSPI0R_SPI0_Msk                         (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSPI0R_SPI0                             ETH_MACSPI0R_SPI0_Msk  /* Source Port Identity 0 */

+

+/* Bit definition for Ethernet MAC PTP Source Port Identity 1 Register */

+#define ETH_MACSPI1R_SPI1_Pos                         (0U)

+#define ETH_MACSPI1R_SPI1_Msk                         (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSPI1R_SPI1                             ETH_MACSPI1R_SPI1_Msk  /* Source Port Identity 1 */

+

+/* Bit definition for Ethernet MAC PTP Source Port Identity 2 Register */

+#define ETH_MACSPI2R_SPI2_Pos                         (0U)

+#define ETH_MACSPI2R_SPI2_Msk                         (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */

+#define ETH_MACSPI2R_SPI2                             ETH_MACSPI2R_SPI2_Msk  /* Source Port Identity 2 */

+

+/* Bit definition for Ethernet MAC Log Message Interval Register */

+#define ETH_MACLMIR_LMPDRI_Pos                        (24U)

+#define ETH_MACLMIR_LMPDRI_Msk                        (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */

+#define ETH_MACLMIR_LMPDRI                             ETH_MACLMIR_LMPDRI_Msk  /* Log Min Pdelay_Req Interval */

+#define ETH_MACLMIR_DRSYNCR_Pos                       (8U)

+#define ETH_MACLMIR_DRSYNCR_Msk                       (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */

+#define ETH_MACLMIR_DRSYNCR                           ETH_MACLMIR_DRSYNCR_Msk  /* Delay_Req to SYNC Ratio */

+#define ETH_MACLMIR_LSI_Pos                           (0U)

+#define ETH_MACLMIR_LSI_Msk                           (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */

+#define ETH_MACLMIR_LSI                               ETH_MACLMIR_LSI_Msk  /* Log Sync Interval */

+

+/* Bit definition for Ethernet MTL Operation Mode Register */

+#define ETH_MTLOMR_CNTCLR_Pos                         (9U)

+#define ETH_MTLOMR_CNTCLR_Msk                         (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */

+#define ETH_MTLOMR_CNTCLR                             ETH_MTLOMR_CNTCLR_Msk    /* Counters Reset */

+#define ETH_MTLOMR_CNTPRST_Pos                        (8U)

+#define ETH_MTLOMR_CNTPRST_Msk                        (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */

+#define ETH_MTLOMR_CNTPRST                            ETH_MTLOMR_CNTPRST_Msk   /* Counters Preset */

+#define ETH_MTLOMR_DTXSTS_Pos                         (1U)

+#define ETH_MTLOMR_DTXSTS_Msk                         (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */

+#define ETH_MTLOMR_DTXSTS                             ETH_MTLOMR_DTXSTS_Msk  /* Drop Transmit Status */

+

+/* Bit definition for Ethernet MTL Interrupt Status Register */

+#define ETH_MTLISR_MACIS_Pos                          (16U)

+#define ETH_MTLISR_MACIS_Msk                          (0x1UL << ETH_MTLISR_MACIS_Pos) /*!< 0x00010000 */

+#define ETH_MTLISR_MACIS                              ETH_MTLISR_MACIS_Msk     /* MAC Interrupt Status */

+#define ETH_MTLISR_QIS_Pos                            (0U)

+#define ETH_MTLISR_QIS_Msk                            (0x1UL << ETH_MTLISR_QIS_Pos) /*!< 0x00000001 */

+#define ETH_MTLISR_QIS                                ETH_MTLISR_QIS_Msk       /* Queue Interrupt status */

+

+/* Bit definition for Ethernet MTL Tx Queue Operation Mode Register */

+#define ETH_MTLTQOMR_TTC_Pos                          (4U)

+#define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */

+#define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */

+#define ETH_MTLTQOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */

+#define ETH_MTLTQOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */

+#define ETH_MTLTQOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */

+#define ETH_MTLTQOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */

+#define ETH_MTLTQOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */

+#define ETH_MTLTQOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */

+#define ETH_MTLTQOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */

+#define ETH_MTLTQOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */

+#define ETH_MTLTQOMR_TSF_Pos                          (1U)

+#define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */

+#define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */

+#define ETH_MTLTQOMR_FTQ_Pos                          (0U)

+#define ETH_MTLTQOMR_FTQ_Msk                          (0x1UL << ETH_MTLTQOMR_FTQ_Pos) /*!< 0x00000001 */

+#define ETH_MTLTQOMR_FTQ                              ETH_MTLTQOMR_FTQ_Msk     /* Flush Transmit Queue */

+

+/* Bit definition for Ethernet MTL Tx Queue Underflow Register */

+#define ETH_MTLTQUR_UFCNTOVF_Pos                      (11U)

+#define ETH_MTLTQUR_UFCNTOVF_Msk                      (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos) /*!< 0x00000800 */

+#define ETH_MTLTQUR_UFCNTOVF                          ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */

+#define ETH_MTLTQUR_UFPKTCNT_Pos                      (0U)

+#define ETH_MTLTQUR_UFPKTCNT_Msk                      (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos) /*!< 0x000007FF */

+#define ETH_MTLTQUR_UFPKTCNT                          ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */

+

+/* Bit definition for Ethernet MTL Tx Queue Debug Register */

+#define ETH_MTLTQDR_STXSTSF_Pos                       (20U)

+#define ETH_MTLTQDR_STXSTSF_Msk                       (0x7UL << ETH_MTLTQDR_STXSTSF_Pos) /*!< 0x00700000 */

+#define ETH_MTLTQDR_STXSTSF                           ETH_MTLTQDR_STXSTSF_Msk  /* Number of Status Words in the Tx Status FIFO of Queue */

+#define ETH_MTLTQDR_PTXQ_Pos                          (16U)

+#define ETH_MTLTQDR_PTXQ_Msk                          (0x7UL << ETH_MTLTQDR_PTXQ_Pos) /*!< 0x00070000 */

+#define ETH_MTLTQDR_PTXQ                              ETH_MTLTQDR_PTXQ_Msk     /* Number of Packets in the Transmit Queue */

+#define ETH_MTLTQDR_TXSTSFSTS_Pos                     (5U)

+#define ETH_MTLTQDR_TXSTSFSTS_Msk                     (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos) /*!< 0x00000020 */

+#define ETH_MTLTQDR_TXSTSFSTS                         ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */

+#define ETH_MTLTQDR_TXQSTS_Pos                        (4U)

+#define ETH_MTLTQDR_TXQSTS_Msk                        (0x1UL << ETH_MTLTQDR_TXQSTS_Pos) /*!< 0x00000010 */

+#define ETH_MTLTQDR_TXQSTS                            ETH_MTLTQDR_TXQSTS_Msk   /* MTL Tx Queue Not Empty Status */

+#define ETH_MTLTQDR_TWCSTS_Pos                        (3U)

+#define ETH_MTLTQDR_TWCSTS_Msk                        (0x1UL << ETH_MTLTQDR_TWCSTS_Pos) /*!< 0x00000008 */

+#define ETH_MTLTQDR_TWCSTS                            ETH_MTLTQDR_TWCSTS_Msk   /* MTL Tx Queue Write Controller Status */

+#define ETH_MTLTQDR_TRCSTS_Pos                        (1U)

+#define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */

+#define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */

+#define ETH_MTLTQDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */

+#define ETH_MTLTQDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */

+#define ETH_MTLTQDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */

+#define ETH_MTLTQDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */

+#define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)

+#define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */

+#define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */

+

+/* Bit definition for Ethernet MTL Queue Interrupt Control Status Register */

+#define ETH_MTLQICSR_RXOIE_Pos                        (24U)

+#define ETH_MTLQICSR_RXOIE_Msk                        (0x1UL << ETH_MTLQICSR_RXOIE_Pos) /*!< 0x01000000 */

+#define ETH_MTLQICSR_RXOIE                            ETH_MTLQICSR_RXOIE_Msk   /* Receive Queue Overflow Interrupt Enable */

+#define ETH_MTLQICSR_RXOVFIS_Pos                      (16U)

+#define ETH_MTLQICSR_RXOVFIS_Msk                      (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos) /*!< 0x00010000 */

+#define ETH_MTLQICSR_RXOVFIS                          ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */

+#define ETH_MTLQICSR_TXUIE_Pos                        (8U)

+#define ETH_MTLQICSR_TXUIE_Msk                        (0x1UL << ETH_MTLQICSR_TXUIE_Pos) /*!< 0x00000100 */

+#define ETH_MTLQICSR_TXUIE                            ETH_MTLQICSR_TXUIE_Msk   /* Transmit Queue Underflow Interrupt Enable */

+#define ETH_MTLQICSR_TXUNFIS_Pos                      (0U)

+#define ETH_MTLQICSR_TXUNFIS_Msk                      (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos) /*!< 0x00000001 */

+#define ETH_MTLQICSR_TXUNFIS                          ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */

+

+/* Bit definition for Ethernet MTL Rx Queue Operation Mode Register */

+#define ETH_MTLRQOMR_RQS_Pos                          (20U)

+#define ETH_MTLRQOMR_RQS_Msk                          (0x7UL << ETH_MTLRQOMR_RQS_Pos) /*!< 0x00700000 */

+#define ETH_MTLRQOMR_RQS                              ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */

+#define ETH_MTLRQOMR_RFD_Pos                          (14U)

+#define ETH_MTLRQOMR_RFD_Msk                          (0x7UL << ETH_MTLRQOMR_RFD_Pos) /*!< 0x0001C000 */

+#define ETH_MTLRQOMR_RFD                              ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */

+#define ETH_MTLRQOMR_RFA_Pos                          (8U)

+#define ETH_MTLRQOMR_RFA_Msk                          (0x7UL << ETH_MTLRQOMR_RFA_Pos) /*!< 0x00000700 */

+#define ETH_MTLRQOMR_RFA                              ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */

+#define ETH_MTLRQOMR_EHFC_Pos                         (7U)

+#define ETH_MTLRQOMR_EHFC_Msk                         (0x1UL << ETH_MTLRQOMR_EHFC_Pos) /*!< 0x00000080 */

+#define ETH_MTLRQOMR_EHFC                             ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */

+#define ETH_MTLRQOMR_DISTCPEF_Pos                     (6U)

+#define ETH_MTLRQOMR_DISTCPEF_Msk                     (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos) /*!< 0x00000040 */

+#define ETH_MTLRQOMR_DISTCPEF                         ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */

+#define ETH_MTLRQOMR_RSF_Pos                          (5U)

+#define ETH_MTLRQOMR_RSF_Msk                          (0x1UL << ETH_MTLRQOMR_RSF_Pos) /*!< 0x00000020 */

+#define ETH_MTLRQOMR_RSF                              ETH_MTLRQOMR_RSF_Msk     /* Receive Queue Store and Forward */

+#define ETH_MTLRQOMR_FEP_Pos                          (4U)

+#define ETH_MTLRQOMR_FEP_Msk                          (0x1UL << ETH_MTLRQOMR_FEP_Pos) /*!< 0x00000010 */

+#define ETH_MTLRQOMR_FEP                              ETH_MTLRQOMR_FEP_Msk     /* Forward Error Packets */

+#define ETH_MTLRQOMR_FUP_Pos                          (3U)

+#define ETH_MTLRQOMR_FUP_Msk                          (0x1UL << ETH_MTLRQOMR_FUP_Pos) /*!< 0x00000008 */

+#define ETH_MTLRQOMR_FUP                              ETH_MTLRQOMR_FUP_Msk     /* Forward Undersized Good Packets */

+#define ETH_MTLRQOMR_RTC_Pos                          (0U)

+#define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */

+#define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */

+#define ETH_MTLRQOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */

+#define ETH_MTLRQOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */

+#define ETH_MTLRQOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */

+#define ETH_MTLRQOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */

+

+/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */

+#define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)

+#define ETH_MTLRQMPOCR_MISCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */

+#define ETH_MTLRQMPOCR_MISCNTOVF                      ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */

+#define ETH_MTLRQMPOCR_MISPKTCNT_Pos                  (16U)

+#define ETH_MTLRQMPOCR_MISPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */

+#define ETH_MTLRQMPOCR_MISPKTCNT                      ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */

+#define ETH_MTLRQMPOCR_OVFCNTOVF_Pos                  (11U)

+#define ETH_MTLRQMPOCR_OVFCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */

+#define ETH_MTLRQMPOCR_OVFCNTOVF                      ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */

+#define ETH_MTLRQMPOCR_OVFPKTCNT_Pos                  (0U)

+#define ETH_MTLRQMPOCR_OVFPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */

+#define ETH_MTLRQMPOCR_OVFPKTCNT                      ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */

+

+/* Bit definition for Ethernet MTL Rx Queue Debug Register */

+#define ETH_MTLRQDR_PRXQ_Pos                          (16U)

+#define ETH_MTLRQDR_PRXQ_Msk                          (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos) /*!< 0x3FFF0000 */

+#define ETH_MTLRQDR_PRXQ                              ETH_MTLRQDR_PRXQ_Msk     /* Number of Packets in Receive Queue */

+#define ETH_MTLRQDR_RXQSTS_Pos                        (4U)

+#define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */

+#define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */

+#define ETH_MTLRQDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */

+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)

+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */

+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */

+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos         (5U)

+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */

+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD             ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */

+#define ETH_MTLRQDR_RXQSTS_FULL_Pos                   (4U)

+#define ETH_MTLRQDR_RXQSTS_FULL_Msk                   (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */

+#define ETH_MTLRQDR_RXQSTS_FULL                       ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */

+#define ETH_MTLRQDR_RRCSTS_Pos                        (1U)

+#define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */

+#define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */

+#define ETH_MTLRQDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */

+#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)

+#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */

+#define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */

+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos          (2U)

+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk          (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */

+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS              ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */

+#define ETH_MTLRQDR_RRCSTS_FLUSHING_Pos               (1U)

+#define ETH_MTLRQDR_RRCSTS_FLUSHING_Msk               (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */

+#define ETH_MTLRQDR_RRCSTS_FLUSHING                   ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */

+#define ETH_MTLRQDR_RWCSTS_Pos                        (0U)

+#define ETH_MTLRQDR_RWCSTS_Msk                        (0x1UL << ETH_MTLRQDR_RWCSTS_Pos) /*!< 0x00000001 */

+#define ETH_MTLRQDR_RWCSTS                            ETH_MTLRQDR_RWCSTS_Msk   /* MTL Rx Queue Write Controller Active Status */

+

+/* Bit definition for Ethernet MTL Rx Queue Control Register */

+#define ETH_MTLRQCR_RQPA_Pos                          (3U)

+#define ETH_MTLRQCR_RQPA_Msk                          (0x1UL << ETH_MTLRQCR_RQPA_Pos) /*!< 0x00000008 */

+#define ETH_MTLRQCR_RQPA                              ETH_MTLRQCR_RQPA_Msk     /* Receive Queue Packet Arbitration */

+#define ETH_MTLRQCR_RQW_Pos                           (0U)

+#define ETH_MTLRQCR_RQW_Msk                           (0x7UL << ETH_MTLRQCR_RQW_Pos) /*!< 0x00000007 */

+#define ETH_MTLRQCR_RQW                               ETH_MTLRQCR_RQW_Msk      /* Receive Queue Weight */

+

+/* Bit definition for Ethernet DMA Mode Register */

+#define ETH_DMAMR_INTM_Pos                            (16U)

+#define ETH_DMAMR_INTM_Msk                            (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */

+#define ETH_DMAMR_INTM                                ETH_DMAMR_INTM_Msk       /* This field defines the interrupt mode */

+#define ETH_DMAMR_INTM_0                              (0x0UL << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */

+#define ETH_DMAMR_INTM_1                              (0x1UL << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */

+#define ETH_DMAMR_INTM_2                              (0x2UL << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */

+#define ETH_DMAMR_PR_Pos                              (12U)

+#define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */

+#define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */

+#define ETH_DMAMR_PR_1_1                              ((uint32_t)0x00000000)   /* The priority ratio is 1:1 */

+#define ETH_DMAMR_PR_2_1                              ((uint32_t)0x00001000)   /* The priority ratio is 2:1 */

+#define ETH_DMAMR_PR_3_1                              ((uint32_t)0x00002000)   /* The priority ratio is 3:1 */

+#define ETH_DMAMR_PR_4_1                              ((uint32_t)0x00003000)   /* The priority ratio is 4:1 */

+#define ETH_DMAMR_PR_5_1                              ((uint32_t)0x00004000)   /* The priority ratio is 5:1 */

+#define ETH_DMAMR_PR_6_1                              ((uint32_t)0x00005000)   /* The priority ratio is 6:1 */

+#define ETH_DMAMR_PR_7_1                              ((uint32_t)0x00006000)   /* The priority ratio is 7:1 */

+#define ETH_DMAMR_PR_8_1                              ((uint32_t)0x00007000)   /* The priority ratio is 8:1 */

+#define ETH_DMAMR_TXPR_Pos                            (11U)

+#define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */

+#define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */

+#define ETH_DMAMR_DA_Pos                              (1U)

+#define ETH_DMAMR_DA_Msk                              (0x1UL << ETH_DMAMR_DA_Pos) /*!< 0x00000002 */

+#define ETH_DMAMR_DA                                  ETH_DMAMR_DA_Msk         /* DMA Tx or Rx Arbitration Scheme */

+#define ETH_DMAMR_SWR_Pos                             (0U)

+#define ETH_DMAMR_SWR_Msk                             (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */

+#define ETH_DMAMR_SWR                                 ETH_DMAMR_SWR_Msk        /* Software Reset */

+

+/* Bit definition for Ethernet DMA SysBus Mode Register */

+#define ETH_DMASBMR_RB_Pos                            (15U)

+#define ETH_DMASBMR_RB_Msk                            (0x1UL << ETH_DMASBMR_RB_Pos) /*!< 0x00008000 */

+#define ETH_DMASBMR_RB                                ETH_DMASBMR_RB_Msk       /* Rebuild INCRx Burst */

+#define ETH_DMASBMR_MB_Pos                            (14U)

+#define ETH_DMASBMR_MB_Msk                            (0x1UL << ETH_DMASBMR_MB_Pos) /*!< 0x00004000 */

+#define ETH_DMASBMR_MB                                ETH_DMASBMR_MB_Msk       /* Mixed Burst */

+#define ETH_DMASBMR_AAL_Pos                           (12U)

+#define ETH_DMASBMR_AAL_Msk                           (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */

+#define ETH_DMASBMR_AAL                               ETH_DMASBMR_AAL_Msk      /* Address-Aligned Beats */

+#define ETH_DMASBMR_FB_Pos                            (0U)

+#define ETH_DMASBMR_FB_Msk                            (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */

+#define ETH_DMASBMR_FB                                ETH_DMASBMR_FB_Msk       /* Fixed Burst Length */

+

+/* Bit definition for Ethernet DMA Interrupt Status Register */

+#define ETH_DMAISR_MACIS_Pos                          (17U)

+#define ETH_DMAISR_MACIS_Msk                          (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */

+#define ETH_DMAISR_MACIS                              ETH_DMAISR_MACIS_Msk     /* MAC Interrupt Status */

+#define ETH_DMAISR_MTLIS_Pos                          (16U)

+#define ETH_DMAISR_MTLIS_Msk                          (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */

+#define ETH_DMAISR_MTLIS                              ETH_DMAISR_MTLIS_Msk     /* MAC Interrupt Status */

+#define ETH_DMAISR_DMACIS_Pos                         (0U)

+#define ETH_DMAISR_DMACIS_Msk                         (0x1UL << ETH_DMAISR_DMACIS_Pos) /*!< 0x00000001 */

+#define ETH_DMAISR_DMACIS                             ETH_DMAISR_DMACIS_Msk    /* DMA Channel Interrupt Status */

+

+/* Bit definition for Ethernet DMA Debug Status Register */

+#define ETH_DMADSR_TPS_Pos                            (12U)

+#define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */

+#define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */

+#define ETH_DMADSR_TPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */

+#define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)

+#define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */

+#define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */

+#define ETH_DMADSR_TPS_WAITING_Pos                    (13U)

+#define ETH_DMADSR_TPS_WAITING_Msk                    (0x1UL << ETH_DMADSR_TPS_WAITING_Pos) /*!< 0x00002000 */

+#define ETH_DMADSR_TPS_WAITING                        ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */

+#define ETH_DMADSR_TPS_READING_Pos                    (12U)

+#define ETH_DMADSR_TPS_READING_Msk                    (0x3UL << ETH_DMADSR_TPS_READING_Pos) /*!< 0x00003000 */

+#define ETH_DMADSR_TPS_READING                        ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */

+#define ETH_DMADSR_TPS_TIMESTAMP_WR_Pos               (14U)

+#define ETH_DMADSR_TPS_TIMESTAMP_WR_Msk               (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos) /*!< 0x00004000 */

+#define ETH_DMADSR_TPS_TIMESTAMP_WR                   ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */

+#define ETH_DMADSR_TPS_SUSPENDED_Pos                  (13U)

+#define ETH_DMADSR_TPS_SUSPENDED_Msk                  (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos) /*!< 0x00006000 */

+#define ETH_DMADSR_TPS_SUSPENDED                      ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */

+#define ETH_DMADSR_TPS_CLOSING_Pos                    (12U)

+#define ETH_DMADSR_TPS_CLOSING_Msk                    (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos) /*!< 0x00007000 */

+#define ETH_DMADSR_TPS_CLOSING                        ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */

+#define ETH_DMADSR_RPS_Pos                            (8U)

+#define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */

+#define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */

+#define ETH_DMADSR_RPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */

+#define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)

+#define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */

+#define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */

+#define ETH_DMADSR_RPS_WAITING_Pos                    (12U)

+#define ETH_DMADSR_RPS_WAITING_Msk                    (0x3UL << ETH_DMADSR_RPS_WAITING_Pos) /*!< 0x00003000 */

+#define ETH_DMADSR_RPS_WAITING                        ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */

+#define ETH_DMADSR_RPS_SUSPENDED_Pos                  (14U)

+#define ETH_DMADSR_RPS_SUSPENDED_Msk                  (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos) /*!< 0x00004000 */

+#define ETH_DMADSR_RPS_SUSPENDED                      ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */

+#define ETH_DMADSR_RPS_CLOSING_Pos                    (12U)

+#define ETH_DMADSR_RPS_CLOSING_Msk                    (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos) /*!< 0x00005000 */

+#define ETH_DMADSR_RPS_CLOSING                        ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */

+#define ETH_DMADSR_RPS_TIMESTAMP_WR_Pos               (13U)

+#define ETH_DMADSR_RPS_TIMESTAMP_WR_Msk               (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos) /*!< 0x00006000 */

+#define ETH_DMADSR_RPS_TIMESTAMP_WR                   ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */

+#define ETH_DMADSR_RPS_TRANSFERRING_Pos               (12U)

+#define ETH_DMADSR_RPS_TRANSFERRING_Msk               (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos) /*!< 0x00007000 */

+#define ETH_DMADSR_RPS_TRANSFERRING                   ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */

+

+/* Bit definition for Ethernet DMA Channel Control Register */

+#define ETH_DMACCR_DSL_Pos                            (18U)

+#define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */

+#define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */

+#define ETH_DMACCR_DSL_0BIT                           ((uint32_t)0x00000000)

+#define ETH_DMACCR_DSL_32BIT                          ((uint32_t)0x00040000)

+#define ETH_DMACCR_DSL_64BIT                          ((uint32_t)0x00080000)

+#define ETH_DMACCR_DSL_128BIT                         ((uint32_t)0x00100000)

+#define ETH_DMACCR_8PBL                               ((uint32_t)0x00010000)   /* 8xPBL mode */

+#define ETH_DMACCR_MSS_Pos                            (0U)

+#define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */

+#define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */

+

+/* Bit definition for Ethernet DMA Channel Tx Control Register */

+#define ETH_DMACTCR_TPBL_Pos                          (16U)

+#define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */

+#define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */

+#define ETH_DMACTCR_TPBL_1PBL                         ((uint32_t)0x00010000)   /* Transmit Programmable Burst Length 1 */

+#define ETH_DMACTCR_TPBL_2PBL                         ((uint32_t)0x00020000)   /* Transmit Programmable Burst Length 2 */

+#define ETH_DMACTCR_TPBL_4PBL                         ((uint32_t)0x00040000)   /* Transmit Programmable Burst Length 4 */

+#define ETH_DMACTCR_TPBL_8PBL                         ((uint32_t)0x00080000)   /* Transmit Programmable Burst Length 8 */

+#define ETH_DMACTCR_TPBL_16PBL                        ((uint32_t)0x00100000)   /* Transmit Programmable Burst Length 16 */

+#define ETH_DMACTCR_TPBL_32PBL                        ((uint32_t)0x00200000)   /* Transmit Programmable Burst Length 32 */

+#define ETH_DMACTCR_TSE_Pos                           (12U)

+#define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */

+#define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */

+#define ETH_DMACTCR_OSP_Pos                           (4U)

+#define ETH_DMACTCR_OSP_Msk                           (0x1UL << ETH_DMACTCR_OSP_Pos) /*!< 0x00000010 */

+#define ETH_DMACTCR_OSP                               ETH_DMACTCR_OSP_Msk      /* Operate on Second Packet */

+#define ETH_DMACTCR_ST_Pos                            (0U)

+#define ETH_DMACTCR_ST_Msk                            (0x1UL << ETH_DMACTCR_ST_Pos) /*!< 0x00000001 */

+#define ETH_DMACTCR_ST                                ETH_DMACTCR_ST_Msk       /* Start or Stop Transmission Command */

+

+/* Bit definition for Ethernet DMA Channel Rx Control Register */

+#define ETH_DMACRCR_RPF_Pos                           (31U)

+#define ETH_DMACRCR_RPF_Msk                           (0x1UL << ETH_DMACRCR_RPF_Pos) /*!< 0x80000000 */

+#define ETH_DMACRCR_RPF                               ETH_DMACRCR_RPF_Msk      /* Rx Packet Flush */

+#define ETH_DMACRCR_RPBL_Pos                          (16U)

+#define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */

+#define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */

+#define ETH_DMACRCR_RPBL_1PBL                         ((uint32_t)0x00010000)   /* Receive Programmable Burst Length 1 */

+#define ETH_DMACRCR_RPBL_2PBL                         ((uint32_t)0x00020000)   /* Receive Programmable Burst Length 2 */

+#define ETH_DMACRCR_RPBL_4PBL                         ((uint32_t)0x00040000)   /* Receive Programmable Burst Length 4 */

+#define ETH_DMACRCR_RPBL_8PBL                         ((uint32_t)0x00080000)   /* Receive Programmable Burst Length 8 */

+#define ETH_DMACRCR_RPBL_16PBL                        ((uint32_t)0x00100000)   /* Receive Programmable Burst Length 16 */

+#define ETH_DMACRCR_RPBL_32PBL                        ((uint32_t)0x00200000)   /* Receive Programmable Burst Length 32 */

+#define ETH_DMACRCR_RBSZ_Pos                          (1U)

+#define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */

+#define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */

+#define ETH_DMACRCR_SR_Pos                            (0U)

+#define ETH_DMACRCR_SR_Msk                            (0x1UL << ETH_DMACRCR_SR_Pos) /*!< 0x00000001 */

+#define ETH_DMACRCR_SR                                ETH_DMACRCR_SR_Msk       /* Start or Stop Receive */

+

+/* Bit definition for Ethernet DMA CH Tx Desc List Address Register */

+#define ETH_DMACTDLAR_TDESLA_Pos                      (2U)

+#define ETH_DMACTDLAR_TDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACTDLAR_TDESLA                          ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */

+

+/* Bit definition for Ethernet DMA CH Rx Desc List Address Register */

+#define ETH_DMACRDLAR_RDESLA_Pos                      (2U)

+#define ETH_DMACRDLAR_RDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACRDLAR_RDESLA                          ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */

+

+/* Bit definition for Ethernet DMA CH Tx Desc Tail Pointer Register */

+#define ETH_DMACTDTPR_TDT_Pos                         (2U)

+#define ETH_DMACTDTPR_TDT_Msk                         (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACTDTPR_TDT                             ETH_DMACTDTPR_TDT_Msk    /* Transmit Descriptor Tail Pointer */

+

+/* Bit definition for Ethernet DMA CH Rx Desc Tail Pointer Register */

+#define ETH_DMACRDTPR_RDT_Pos                         (2U)

+#define ETH_DMACRDTPR_RDT_Msk                         (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACRDTPR_RDT                             ETH_DMACRDTPR_RDT_Msk    /* Receive Descriptor Tail Pointer */

+

+/* Bit definition for Ethernet DMA CH Tx Desc Ring Length Register */

+#define ETH_DMACTDRLR_TDRL_Pos                        (0U)

+#define ETH_DMACTDRLR_TDRL_Msk                        (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos) /*!< 0x000003FF */

+#define ETH_DMACTDRLR_TDRL                            ETH_DMACTDRLR_TDRL_Msk   /* Transmit Descriptor Ring Length */

+

+/* Bit definition for Ethernet DMA CH Rx Desc Ring Length Register */

+#define ETH_DMACRDRLR_RDRL_Pos                        (0U)

+#define ETH_DMACRDRLR_RDRL_Msk                        (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos) /*!< 0x000003FF */

+#define ETH_DMACRDRLR_RDRL                            ETH_DMACRDRLR_RDRL_Msk   /* Receive Descriptor Ring Length */

+

+/* Bit definition for Ethernet DMA Channel Interrupt Enable Register */

+#define ETH_DMACIER_NIE_Pos                           (15U)

+#define ETH_DMACIER_NIE_Msk                           (0x1UL << ETH_DMACIER_NIE_Pos) /*!< 0x00008000 */

+#define ETH_DMACIER_NIE                               ETH_DMACIER_NIE_Msk      /* Normal Interrupt Summary Enable */

+#define ETH_DMACIER_AIE_Pos                           (14U)

+#define ETH_DMACIER_AIE_Msk                           (0x1UL << ETH_DMACIER_AIE_Pos) /*!< 0x00004000 */

+#define ETH_DMACIER_AIE                               ETH_DMACIER_AIE_Msk      /* Abnormal Interrupt Summary Enable */

+#define ETH_DMACIER_CDEE_Pos                          (13U)

+#define ETH_DMACIER_CDEE_Msk                          (0x1UL << ETH_DMACIER_CDEE_Pos) /*!< 0x00002000 */

+#define ETH_DMACIER_CDEE                              ETH_DMACIER_CDEE_Msk     /* Context Descriptor Error Enable */

+#define ETH_DMACIER_FBEE_Pos                          (12U)

+#define ETH_DMACIER_FBEE_Msk                          (0x1UL << ETH_DMACIER_FBEE_Pos) /*!< 0x00001000 */

+#define ETH_DMACIER_FBEE                              ETH_DMACIER_FBEE_Msk     /* Fatal Bus Error Enable */

+#define ETH_DMACIER_ERIE_Pos                          (11U)

+#define ETH_DMACIER_ERIE_Msk                          (0x1UL << ETH_DMACIER_ERIE_Pos) /*!< 0x00000800 */

+#define ETH_DMACIER_ERIE                              ETH_DMACIER_ERIE_Msk     /* Early Receive Interrupt Enable */

+#define ETH_DMACIER_ETIE_Pos                          (10U)

+#define ETH_DMACIER_ETIE_Msk                          (0x1UL << ETH_DMACIER_ETIE_Pos) /*!< 0x00000400 */

+#define ETH_DMACIER_ETIE                              ETH_DMACIER_ETIE_Msk     /* Early Transmit Interrupt Enable */

+#define ETH_DMACIER_RWTE_Pos                          (9U)

+#define ETH_DMACIER_RWTE_Msk                          (0x1UL << ETH_DMACIER_RWTE_Pos) /*!< 0x00000200 */

+#define ETH_DMACIER_RWTE                              ETH_DMACIER_RWTE_Msk     /* Receive Watchdog Timeout Enable */

+#define ETH_DMACIER_RSE_Pos                           (8U)

+#define ETH_DMACIER_RSE_Msk                           (0x1UL << ETH_DMACIER_RSE_Pos) /*!< 0x00000100 */

+#define ETH_DMACIER_RSE                               ETH_DMACIER_RSE_Msk      /* Receive Stopped Enable */

+#define ETH_DMACIER_RBUE_Pos                          (7U)

+#define ETH_DMACIER_RBUE_Msk                          (0x1UL << ETH_DMACIER_RBUE_Pos) /*!< 0x00000080 */

+#define ETH_DMACIER_RBUE                              ETH_DMACIER_RBUE_Msk     /* Receive Buffer Unavailable Enable */

+#define ETH_DMACIER_RIE_Pos                           (6U)

+#define ETH_DMACIER_RIE_Msk                           (0x1UL << ETH_DMACIER_RIE_Pos) /*!< 0x00000040 */

+#define ETH_DMACIER_RIE                               ETH_DMACIER_RIE_Msk      /* Receive Interrupt Enable */

+#define ETH_DMACIER_TBUE_Pos                          (2U)

+#define ETH_DMACIER_TBUE_Msk                          (0x1UL << ETH_DMACIER_TBUE_Pos) /*!< 0x00000004 */

+#define ETH_DMACIER_TBUE                              ETH_DMACIER_TBUE_Msk     /* Transmit Buffer Unavailable Enable */

+#define ETH_DMACIER_TXSE_Pos                          (1U)

+#define ETH_DMACIER_TXSE_Msk                          (0x1UL << ETH_DMACIER_TXSE_Pos) /*!< 0x00000002 */

+#define ETH_DMACIER_TXSE                              ETH_DMACIER_TXSE_Msk     /* Transmit Stopped Enable */

+#define ETH_DMACIER_TIE_Pos                           (0U)

+#define ETH_DMACIER_TIE_Msk                           (0x1UL << ETH_DMACIER_TIE_Pos) /*!< 0x00000001 */

+#define ETH_DMACIER_TIE                               ETH_DMACIER_TIE_Msk      /* Transmit Interrupt Enable */

+

+/* Bit definition for Ethernet DMA Channel Rx Interrupt Watchdog Timer Register */

+#define ETH_DMACRIWTR_RWT_Pos                         (0U)

+#define ETH_DMACRIWTR_RWT_Msk                         (0xFFUL << ETH_DMACRIWTR_RWT_Pos) /*!< 0x000000FF */

+#define ETH_DMACRIWTR_RWT                             ETH_DMACRIWTR_RWT_Msk    /* Receive Interrupt Watchdog Timer Count */

+

+/* Bit definition for Ethernet DMA Channel Current App Tx Desc Register */

+#define ETH_DMACCATDR_CURTDESAPTR_Pos                 (0U)

+#define ETH_DMACCATDR_CURTDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCATDR_CURTDESAPTR                     ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Current App Rx Desc Register */

+#define ETH_DMACCARDR_CURRDESAPTR_Pos                 (0U)

+#define ETH_DMACCARDR_CURRDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCARDR_CURRDESAPTR                     ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Current App Tx Buffer Register */

+#define ETH_DMACCATBR_CURTBUFAPTR_Pos                 (0U)

+#define ETH_DMACCATBR_CURTBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCATBR_CURTBUFAPTR                     ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Current App Rx Buffer Register */

+#define ETH_DMACCARBR_CURRBUFAPTR_Pos                 (0U)

+#define ETH_DMACCARBR_CURRBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCARBR_CURRBUFAPTR                     ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Status Register */

+#define ETH_DMACSR_REB_Pos                            (19U)

+#define ETH_DMACSR_REB_Msk                            (0x7UL << ETH_DMACSR_REB_Pos) /*!< 0x00380000 */

+#define ETH_DMACSR_REB                                ETH_DMACSR_REB_Msk       /* Rx DMA Error Bits */

+#define ETH_DMACSR_TEB_Pos                            (16U)

+#define ETH_DMACSR_TEB_Msk                            (0x7UL << ETH_DMACSR_TEB_Pos) /*!< 0x00070000 */

+#define ETH_DMACSR_TEB                                ETH_DMACSR_TEB_Msk       /* Tx DMA Error Bits */

+#define ETH_DMACSR_NIS_Pos                            (15U)

+#define ETH_DMACSR_NIS_Msk                            (0x1UL << ETH_DMACSR_NIS_Pos) /*!< 0x00008000 */

+#define ETH_DMACSR_NIS                                ETH_DMACSR_NIS_Msk       /* Normal Interrupt Summary */

+#define ETH_DMACSR_AIS_Pos                            (14U)

+#define ETH_DMACSR_AIS_Msk                            (0x1UL << ETH_DMACSR_AIS_Pos) /*!< 0x00004000 */

+#define ETH_DMACSR_AIS                                ETH_DMACSR_AIS_Msk       /* Abnormal Interrupt Summary */

+#define ETH_DMACSR_CDE_Pos                            (13U)

+#define ETH_DMACSR_CDE_Msk                            (0x1UL << ETH_DMACSR_CDE_Pos) /*!< 0x00002000 */

+#define ETH_DMACSR_CDE                                ETH_DMACSR_CDE_Msk       /* Context Descriptor Error */

+#define ETH_DMACSR_FBE_Pos                            (12U)

+#define ETH_DMACSR_FBE_Msk                            (0x1UL << ETH_DMACSR_FBE_Pos) /*!< 0x00001000 */

+#define ETH_DMACSR_FBE                                ETH_DMACSR_FBE_Msk       /* Fatal Bus Error */

+#define ETH_DMACSR_ERI_Pos                            (11U)

+#define ETH_DMACSR_ERI_Msk                            (0x1UL << ETH_DMACSR_ERI_Pos) /*!< 0x00000800 */

+#define ETH_DMACSR_ERI                                ETH_DMACSR_ERI_Msk       /* Early Receive Interrupt */

+#define ETH_DMACSR_ETI_Pos                            (10U)

+#define ETH_DMACSR_ETI_Msk                            (0x1UL << ETH_DMACSR_ETI_Pos) /*!< 0x00000400 */

+#define ETH_DMACSR_ETI                                ETH_DMACSR_ETI_Msk       /* Early Transmit Interrupt */

+#define ETH_DMACSR_RWT_Pos                            (9U)

+#define ETH_DMACSR_RWT_Msk                            (0x1UL << ETH_DMACSR_RWT_Pos) /*!< 0x00000200 */

+#define ETH_DMACSR_RWT                                ETH_DMACSR_RWT_Msk       /* Receive Watchdog Timeout */

+#define ETH_DMACSR_RPS_Pos                            (8U)

+#define ETH_DMACSR_RPS_Msk                            (0x1UL << ETH_DMACSR_RPS_Pos) /*!< 0x00000100 */

+#define ETH_DMACSR_RPS                                ETH_DMACSR_RPS_Msk       /* Receive Process Stopped */

+#define ETH_DMACSR_RBU_Pos                            (7U)

+#define ETH_DMACSR_RBU_Msk                            (0x1UL << ETH_DMACSR_RBU_Pos) /*!< 0x00000080 */

+#define ETH_DMACSR_RBU                                ETH_DMACSR_RBU_Msk       /* Receive Buffer Unavailable */

+#define ETH_DMACSR_RI_Pos                             (6U)

+#define ETH_DMACSR_RI_Msk                             (0x1UL << ETH_DMACSR_RI_Pos) /*!< 0x00000040 */

+#define ETH_DMACSR_RI                                 ETH_DMACSR_RI_Msk        /* Receive Interrupt */

+#define ETH_DMACSR_TBU_Pos                            (2U)

+#define ETH_DMACSR_TBU_Msk                            (0x1UL << ETH_DMACSR_TBU_Pos) /*!< 0x00000004 */

+#define ETH_DMACSR_TBU                                ETH_DMACSR_TBU_Msk       /* Transmit Buffer Unavailable */

+#define ETH_DMACSR_TPS_Pos                            (1U)

+#define ETH_DMACSR_TPS_Msk                            (0x1UL << ETH_DMACSR_TPS_Pos) /*!< 0x00000002 */

+#define ETH_DMACSR_TPS                                ETH_DMACSR_TPS_Msk       /* Transmit Process Stopped */

+#define ETH_DMACSR_TI_Pos                             (0U)

+#define ETH_DMACSR_TI_Msk                             (0x1UL << ETH_DMACSR_TI_Pos) /*!< 0x00000001 */

+#define ETH_DMACSR_TI                                 ETH_DMACSR_TI_Msk        /* Transmit Interrupt */

+

+/* Bit definition for Ethernet DMA Channel missed frame count register */

+#define ETH_DMACMFCR_MFCO_Pos                         (15U)

+#define ETH_DMACMFCR_MFCO_Msk                         (0x1UL << ETH_DMACMFCR_MFCO_Pos) /*!< 0x00008000 */

+#define ETH_DMACMFCR_MFCO                             ETH_DMACMFCR_MFCO_Msk    /* Overflow status of the MFC Counter */

+#define ETH_DMACMFCR_MFC_Pos                          (0U)

+#define ETH_DMACMFCR_MFC_Msk                          (0x7FFUL << ETH_DMACMFCR_MFC_Pos) /*!< 0x000007FF */

+#define ETH_DMACMFCR_MFC                              ETH_DMACMFCR_MFC_Msk     /* The number of packet counters dropped by the DMA */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             DMA Controller                                 */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DMA_SxCR register  *****************/

+#define DMA_SxCR_MBURST_Pos      (23U)

+#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                /*!< 0x01800000 */

+#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk                           /*!< Memory burst transfer configuration */

+#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */

+#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */

+#define DMA_SxCR_PBURST_Pos      (21U)

+#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                /*!< 0x00600000 */

+#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk                           /*!< Peripheral burst transfer configuration */

+#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */

+#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */

+#define DMA_SxCR_TRBUFF_Pos      (20U)

+#define DMA_SxCR_TRBUFF_Msk      (0x1UL << DMA_SxCR_TRBUFF_Pos)                 /*!< 0x00100000 */

+#define DMA_SxCR_TRBUFF          DMA_SxCR_TRBUFF_Msk                            /*!< bufferable transfers enabled/disable */

+#define DMA_SxCR_CT_Pos          (19U)

+#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                    /*!< 0x00080000 */

+#define DMA_SxCR_CT              DMA_SxCR_CT_Msk                               /*!< Current target (only in double buffer mode) */

+#define DMA_SxCR_DBM_Pos         (18U)

+#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                   /*!< 0x00040000 */

+#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk                              /*!< Double buffer mode */

+#define DMA_SxCR_PL_Pos          (16U)

+#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                    /*!< 0x00030000 */

+#define DMA_SxCR_PL              DMA_SxCR_PL_Msk                               /*!< Priority level */

+#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */

+#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */

+#define DMA_SxCR_PINCOS_Pos      (15U)

+#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                /*!< 0x00008000 */

+#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk                           /*!< Peripheral increment offset size */

+#define DMA_SxCR_MSIZE_Pos       (13U)

+#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                 /*!< 0x00006000 */

+#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk                            /*!< Memory data size */

+#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */

+#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */

+#define DMA_SxCR_PSIZE_Pos       (11U)

+#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                 /*!< 0x00001800 */

+#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk                            /*< Peripheral data size */

+#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */

+#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */

+#define DMA_SxCR_MINC_Pos        (10U)

+#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                  /*!< 0x00000400 */

+#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk                             /*!< Memory increment mode */

+#define DMA_SxCR_PINC_Pos        (9U)

+#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                  /*!< 0x00000200 */

+#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk                             /*!< Peripheral increment mode */

+#define DMA_SxCR_CIRC_Pos        (8U)

+#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                  /*!< 0x00000100 */

+#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk                             /*!< Circular mode */

+#define DMA_SxCR_DIR_Pos         (6U)

+#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                   /*!< 0x000000C0 */

+#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk                              /*!< Data transfer direction */

+#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */

+#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */

+#define DMA_SxCR_PFCTRL_Pos      (5U)

+#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                /*!< 0x00000020 */

+#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk                           /*!< Peripheral flow controller */

+#define DMA_SxCR_TCIE_Pos        (4U)

+#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                  /*!< 0x00000010 */

+#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk                             /*!< Transfer complete interrupt enable */

+#define DMA_SxCR_HTIE_Pos        (3U)

+#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                  /*!< 0x00000008 */

+#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk                             /*!< Half transfer interrupt enable */

+#define DMA_SxCR_TEIE_Pos        (2U)

+#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                  /*!< 0x00000004 */

+#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk                             /*!< Transfer error interrupt enable */

+#define DMA_SxCR_DMEIE_Pos       (1U)

+#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                 /*!< 0x00000002 */

+#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk                            /*!< Direct mode error interrupt enable */

+#define DMA_SxCR_EN_Pos          (0U)

+#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                    /*!< 0x00000001 */

+#define DMA_SxCR_EN              DMA_SxCR_EN_Msk                               /*!< Stream enable / flag stream ready when read low */

+

+/********************  Bits definition for DMA_SxCNDTR register  **************/

+#define DMA_SxNDT_Pos            (0U)

+#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                   /*!< 0x0000FFFF */

+#define DMA_SxNDT                DMA_SxNDT_Msk                                 /*!< Number of data items to transfer */

+#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */

+#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */

+#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */

+#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */

+#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */

+#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */

+#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */

+#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */

+#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */

+#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */

+#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */

+#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */

+#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */

+#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */

+#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */

+#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */

+

+/********************  Bits definition for DMA_SxFCR register  ****************/

+#define DMA_SxFCR_FEIE_Pos       (7U)

+#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                 /*!< 0x00000080 */

+#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk                            /*!< FIFO error interrupt enable */

+#define DMA_SxFCR_FS_Pos         (3U)

+#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                   /*!< 0x00000038 */

+#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk                              /*!< FIFO status */

+#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */

+#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */

+#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */

+#define DMA_SxFCR_DMDIS_Pos      (2U)

+#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                /*!< 0x00000004 */

+#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk                           /*!< Direct mode disable */

+#define DMA_SxFCR_FTH_Pos        (0U)

+#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                  /*!< 0x00000003 */

+#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk                             /*!< FIFO threshold selection */

+#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */

+#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */

+

+/********************  Bits definition for DMA_LISR register  *****************/

+#define DMA_LISR_TCIF3_Pos       (27U)

+#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                 /*!< 0x08000000 */

+#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk                            /*!<  Stream 3 transfer complete interrupt flag */

+#define DMA_LISR_HTIF3_Pos       (26U)

+#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                 /*!< 0x04000000 */

+#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk                            /*!<  Stream 3 half transfer interrupt flag */

+#define DMA_LISR_TEIF3_Pos       (25U)

+#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                 /*!< 0x02000000 */

+#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk                            /*!<  Stream 3 transfer error interrupt flag */

+#define DMA_LISR_DMEIF3_Pos      (24U)

+#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                /*!< 0x01000000 */

+#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk                           /*!<  Stream 3 direct mode error interrupt flag */

+#define DMA_LISR_FEIF3_Pos       (22U)

+#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                 /*!< 0x00400000 */

+#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk                            /*!<  Stream 3 FIFO error interrupt flag */

+#define DMA_LISR_TCIF2_Pos       (21U)

+#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                 /*!< 0x00200000 */

+#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk                            /*!<  Stream 2 transfer complete interrupt flag */

+#define DMA_LISR_HTIF2_Pos       (20U)

+#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                 /*!< 0x00100000 */

+#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk                            /*!<  Stream 2 half transfer interrupt flag */

+#define DMA_LISR_TEIF2_Pos       (19U)

+#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                 /*!< 0x00080000 */

+#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk                            /*!<  Stream 2 transfer error interrupt flag */

+#define DMA_LISR_DMEIF2_Pos      (18U)

+#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                /*!< 0x00040000 */

+#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk                           /*!<  Stream 2 direct mode error interrupt flag */

+#define DMA_LISR_FEIF2_Pos       (16U)

+#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                 /*!< 0x00010000 */

+#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk                            /*!<  Stream 2 FIFO error interrupt flag */

+#define DMA_LISR_TCIF1_Pos       (11U)

+#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                 /*!< 0x00000800 */

+#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk                            /*!<  Stream 1 transfer complete interrupt flag */

+#define DMA_LISR_HTIF1_Pos       (10U)

+#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                 /*!< 0x00000400 */

+#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk                            /*!<  Stream 1 half transfer interrupt flag */

+#define DMA_LISR_TEIF1_Pos       (9U)

+#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                 /*!< 0x00000200 */

+#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk                            /*!<  Stream 1 transfer error interrupt flag */

+#define DMA_LISR_DMEIF1_Pos      (8U)

+#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                /*!< 0x00000100 */

+#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk                           /*!<  Stream 1 direct mode error interrupt flag */

+#define DMA_LISR_FEIF1_Pos       (6U)

+#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                 /*!< 0x00000040 */

+#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk                            /*!<  Stream 1 FIFO error interrupt flag */

+#define DMA_LISR_TCIF0_Pos       (5U)

+#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                 /*!< 0x00000020 */

+#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk                            /*!<  Stream 0 transfer complete interrupt flag */

+#define DMA_LISR_HTIF0_Pos       (4U)

+#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                 /*!< 0x00000010 */

+#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk                            /*!<  Stream 0 half transfer interrupt flag */

+#define DMA_LISR_TEIF0_Pos       (3U)

+#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                 /*!< 0x00000008 */

+#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk                            /*!<  Stream 0 transfer error interrupt flag */

+#define DMA_LISR_DMEIF0_Pos      (2U)

+#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                /*!< 0x00000004 */

+#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk                           /*!<  Stream 0 direct mode error interrupt flag */

+#define DMA_LISR_FEIF0_Pos       (0U)

+#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                 /*!< 0x00000001 */

+#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk                            /*!<  Stream 0 FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_HISR register  *****************/

+#define DMA_HISR_TCIF7_Pos       (27U)

+#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                 /*!< 0x08000000 */

+#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk                            /*!<  Stream 7 transfer complete interrupt flag */

+#define DMA_HISR_HTIF7_Pos       (26U)

+#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                 /*!< 0x04000000 */

+#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk                            /*!<  Stream 7 half transfer interrupt flag */

+#define DMA_HISR_TEIF7_Pos       (25U)

+#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                 /*!< 0x02000000 */

+#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk                            /*!<  Stream 7 transfer error interrupt flag */

+#define DMA_HISR_DMEIF7_Pos      (24U)

+#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                /*!< 0x01000000 */

+#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk                           /*!<  Stream 7 direct mode error interrupt flag */

+#define DMA_HISR_FEIF7_Pos       (22U)

+#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                 /*!< 0x00400000 */

+#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk                            /*!<  Stream 7 FIFO error interrupt flag */

+#define DMA_HISR_TCIF6_Pos       (21U)

+#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                 /*!< 0x00200000 */

+#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk                            /*!<  Stream 6 transfer complete interrupt flag */

+#define DMA_HISR_HTIF6_Pos       (20U)

+#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                 /*!< 0x00100000 */

+#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk                            /*!<  Stream 6 half transfer interrupt flag */

+#define DMA_HISR_TEIF6_Pos       (19U)

+#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                 /*!< 0x00080000 */

+#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk                            /*!<  Stream 6 transfer error interrupt flag */

+#define DMA_HISR_DMEIF6_Pos      (18U)

+#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                /*!< 0x00040000 */

+#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk                           /*!<  Stream 6 direct mode error interrupt flag */

+#define DMA_HISR_FEIF6_Pos       (16U)

+#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                 /*!< 0x00010000 */

+#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk                            /*!<  Stream 6 FIFO error interrupt flag */

+#define DMA_HISR_TCIF5_Pos       (11U)

+#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                 /*!< 0x00000800 */

+#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk                            /*!<  Stream 5 transfer complete interrupt flag */

+#define DMA_HISR_HTIF5_Pos       (10U)

+#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                 /*!< 0x00000400 */

+#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk                            /*!<  Stream 5 half transfer interrupt flag */

+#define DMA_HISR_TEIF5_Pos       (9U)

+#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                 /*!< 0x00000200 */

+#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk                            /*!<  Stream 5 transfer error interrupt flag */

+#define DMA_HISR_DMEIF5_Pos      (8U)

+#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                /*!< 0x00000100 */

+#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk                           /*!<  Stream 5 direct mode error interrupt flag */

+#define DMA_HISR_FEIF5_Pos       (6U)

+#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                 /*!< 0x00000040 */

+#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk                            /*!<  Stream 5 FIFO error interrupt flag */

+#define DMA_HISR_TCIF4_Pos       (5U)

+#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                 /*!< 0x00000020 */

+#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk                            /*!<  Stream 4 transfer complete interrupt flag */

+#define DMA_HISR_HTIF4_Pos       (4U)

+#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                 /*!< 0x00000010 */

+#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk                            /*!<  Stream 4 half transfer interrupt flag */

+#define DMA_HISR_TEIF4_Pos       (3U)

+#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                 /*!< 0x00000008 */

+#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk                            /*!<  Stream 4 transfer error interrupt flag */

+#define DMA_HISR_DMEIF4_Pos      (2U)

+#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                /*!< 0x00000004 */

+#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk                           /*!<  Stream 4 direct mode error interrupt flag */

+#define DMA_HISR_FEIF4_Pos       (0U)

+#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                 /*!< 0x00000001 */

+#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk                            /*!<  Stream 4 FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_LIFCR register  ****************/

+#define DMA_LIFCR_CTCIF3_Pos     (27U)

+#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)               /*!< 0x08000000 */

+#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk                          /*!<  Stream 3 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF3_Pos     (26U)

+#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)               /*!< 0x04000000 */

+#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk                          /*!<  Stream 3 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF3_Pos     (25U)

+#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)               /*!< 0x02000000 */

+#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk                          /*!<  Stream 3 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF3_Pos    (24U)

+#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)              /*!< 0x01000000 */

+#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk                         /*!<  Stream 3 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF3_Pos     (22U)

+#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)               /*!< 0x00400000 */

+#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk                          /*!<  Stream 3 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF2_Pos     (21U)

+#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)               /*!< 0x00200000 */

+#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk                          /*!<  Stream 2 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF2_Pos     (20U)

+#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)               /*!< 0x00100000 */

+#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk                          /*!<  Stream 2 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF2_Pos     (19U)

+#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)               /*!< 0x00080000 */

+#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk                          /*!<  Stream 2 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF2_Pos    (18U)

+#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)              /*!< 0x00040000 */

+#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk                         /*!<  Stream 2 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF2_Pos     (16U)

+#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)               /*!< 0x00010000 */

+#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk                          /*!<  Stream 2 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF1_Pos     (11U)

+#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)               /*!< 0x00000800 */

+#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk                          /*!<  Stream 1 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF1_Pos     (10U)

+#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)               /*!< 0x00000400 */

+#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk                          /*!<  Stream 1 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF1_Pos     (9U)

+#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)               /*!< 0x00000200 */

+#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk                          /*!<  Stream 1 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF1_Pos    (8U)

+#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)              /*!< 0x00000100 */

+#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk                         /*!<  Stream 1 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF1_Pos     (6U)

+#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)               /*!< 0x00000040 */

+#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk                          /*!<  Stream 1 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF0_Pos     (5U)

+#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)               /*!< 0x00000020 */

+#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk                          /*!<  Stream 0 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF0_Pos     (4U)

+#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)               /*!< 0x00000010 */

+#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk                          /*!<  Stream 0 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF0_Pos     (3U)

+#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)               /*!< 0x00000008 */

+#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk                          /*!<  Stream 0 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF0_Pos    (2U)

+#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)              /*!< 0x00000004 */

+#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk                         /*!<  Stream 0 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF0_Pos     (0U)

+#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)               /*!< 0x00000001 */

+#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk                          /*!<  Stream 0 clear FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_HIFCR  register  ****************/

+#define DMA_HIFCR_CTCIF7_Pos     (27U)

+#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)               /*!< 0x08000000 */

+#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk                          /*!<  Stream 7 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF7_Pos     (26U)

+#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)               /*!< 0x04000000 */

+#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk                          /*!<  Stream 7 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF7_Pos     (25U)

+#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)               /*!< 0x02000000 */

+#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk                          /*!<  Stream 7 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF7_Pos    (24U)

+#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)              /*!< 0x01000000 */

+#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk                         /*!<  Stream 7 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF7_Pos     (22U)

+#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)               /*!< 0x00400000 */

+#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk                          /*!<  Stream 7 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF6_Pos     (21U)

+#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)               /*!< 0x00200000 */

+#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk                          /*!<  Stream 6 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF6_Pos     (20U)

+#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)               /*!< 0x00100000 */

+#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk                          /*!<  Stream 6 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF6_Pos     (19U)

+#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)               /*!< 0x00080000 */

+#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk                          /*!<  Stream 6 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF6_Pos    (18U)

+#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)              /*!< 0x00040000 */

+#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk                         /*!<  Stream 6 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF6_Pos     (16U)

+#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)               /*!< 0x00010000 */

+#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk                          /*!<  Stream 6 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF5_Pos     (11U)

+#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)               /*!< 0x00000800 */

+#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk                          /*!<  Stream 5 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF5_Pos     (10U)

+#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)               /*!< 0x00000400 */

+#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk                          /*!<  Stream 5 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF5_Pos     (9U)

+#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)               /*!< 0x00000200 */

+#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk                          /*!<  Stream 5 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF5_Pos    (8U)

+#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)              /*!< 0x00000100 */

+#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk                         /*!<  Stream 5 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF5_Pos     (6U)

+#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)               /*!< 0x00000040 */

+#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk                          /*!<  Stream 5 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF4_Pos     (5U)

+#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)               /*!< 0x00000020 */

+#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk                          /*!<  Stream 4 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF4_Pos     (4U)

+#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)               /*!< 0x00000010 */

+#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk                          /*!<  Stream 4 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF4_Pos     (3U)

+#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)               /*!< 0x00000008 */

+#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk                          /*!<  Stream 4 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF4_Pos    (2U)

+#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)              /*!< 0x00000004 */

+#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk                         /*!<  Stream 4 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF4_Pos     (0U)

+#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)               /*!< 0x00000001 */

+#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk                          /*!<  Stream 4 clear FIFO error interrupt flag */

+

+/******************  Bit definition for DMA_SxPAR register  ********************/

+#define DMA_SxPAR_PA_Pos         (0U)

+#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)            /*!< 0xFFFFFFFF */

+#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */

+

+/******************  Bit definition for DMA_SxM0AR register  ********************/

+#define DMA_SxM0AR_M0A_Pos       (0U)

+#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)          /*!< 0xFFFFFFFF */

+#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory 0 Address */

+

+/******************  Bit definition for DMA_SxM1AR register  ********************/

+#define DMA_SxM1AR_M1A_Pos       (0U)

+#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)          /*!< 0xFFFFFFFF */

+#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory 1 Address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             DMAMUX Controller                              */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DMAMUX_CxCR register  **************/

+#define DMAMUX_CxCR_DMAREQ_ID_Pos      (0U)

+#define DMAMUX_CxCR_DMAREQ_ID_Msk      (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)   /*!< 0x000000FF */

+#define DMAMUX_CxCR_DMAREQ_ID          DMAMUX_CxCR_DMAREQ_ID_Msk               /*!<  DMA request identification */

+#define DMAMUX_CxCR_DMAREQ_ID_0        (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000001 */

+#define DMAMUX_CxCR_DMAREQ_ID_1        (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000002 */

+#define DMAMUX_CxCR_DMAREQ_ID_2        (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000004 */

+#define DMAMUX_CxCR_DMAREQ_ID_3        (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000008 */

+#define DMAMUX_CxCR_DMAREQ_ID_4        (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000010 */

+#define DMAMUX_CxCR_DMAREQ_ID_5        (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000020 */

+#define DMAMUX_CxCR_DMAREQ_ID_6        (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000040 */

+#define DMAMUX_CxCR_DMAREQ_ID_7        (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000080 */

+#define DMAMUX_CxCR_SOIE_Pos           (8U)

+#define DMAMUX_CxCR_SOIE_Msk           (0x1UL << DMAMUX_CxCR_SOIE_Pos)         /*!< 0x00000100 */

+#define DMAMUX_CxCR_SOIE               DMAMUX_CxCR_SOIE_Msk                    /*!<  Synchronization overrun interrupt enable */

+#define DMAMUX_CxCR_EGE_Pos            (9U)

+#define DMAMUX_CxCR_EGE_Msk            (0x1UL << DMAMUX_CxCR_EGE_Pos)          /*!< 0x00000200 */

+#define DMAMUX_CxCR_EGE                DMAMUX_CxCR_EGE_Msk                     /*!<  Event generation enable */

+#define DMAMUX_CxCR_SE_Pos             (16U)

+#define DMAMUX_CxCR_SE_Msk             (0x1UL << DMAMUX_CxCR_SE_Pos)           /*!< 0x00010000 */

+#define DMAMUX_CxCR_SE                 DMAMUX_CxCR_SE_Msk                      /*!<  Synchronization enable */

+#define DMAMUX_CxCR_SPOL_Pos           (17U)

+#define DMAMUX_CxCR_SPOL_Msk           (0x3UL << DMAMUX_CxCR_SPOL_Pos)         /*!< 0x00060000 */

+#define DMAMUX_CxCR_SPOL               DMAMUX_CxCR_SPOL_Msk                    /*!<  Synchronization polarity */

+#define DMAMUX_CxCR_SPOL_0             (0x1UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00020000 */

+#define DMAMUX_CxCR_SPOL_1             (0x2UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00040000 */

+#define DMAMUX_CxCR_NBREQ_Pos          (19U)

+#define DMAMUX_CxCR_NBREQ_Msk          (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)       /*!< 0x00F80000 */

+#define DMAMUX_CxCR_NBREQ              DMAMUX_CxCR_NBREQ_Msk                   /*!<  Number of DMA requests minus 1 to forward */

+#define DMAMUX_CxCR_NBREQ_0            (0x01UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00080000 */

+#define DMAMUX_CxCR_NBREQ_1            (0x02UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00100000 */

+#define DMAMUX_CxCR_NBREQ_2            (0x04UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00200000 */

+#define DMAMUX_CxCR_NBREQ_3            (0x08UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00400000 */

+#define DMAMUX_CxCR_NBREQ_4            (0x10UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00800000 */

+#define DMAMUX_CxCR_SYNC_ID_Pos        (24U)

+#define DMAMUX_CxCR_SYNC_ID_Msk        (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)     /*!< 0x1F000000 */

+#define DMAMUX_CxCR_SYNC_ID            DMAMUX_CxCR_SYNC_ID_Msk                 /*!<  Synchronization identification */

+#define DMAMUX_CxCR_SYNC_ID_0          (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x01000000 */

+#define DMAMUX_CxCR_SYNC_ID_1          (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x02000000 */

+#define DMAMUX_CxCR_SYNC_ID_2          (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x04000000 */

+#define DMAMUX_CxCR_SYNC_ID_3          (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x08000000 */

+#define DMAMUX_CxCR_SYNC_ID_4          (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x10000000 */

+

+/********************  Bits definition for DMAMUX_CSR register  **************/

+#define DMAMUX_CSR_SOF0_Pos            (0U)

+#define DMAMUX_CSR_SOF0_Msk            (0x1UL << DMAMUX_CSR_SOF0_Pos)          /*!< 0x00000001 */

+#define DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0_Msk                     /*!< Channel 0 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF1_Pos            (1U)

+#define DMAMUX_CSR_SOF1_Msk            (0x1UL << DMAMUX_CSR_SOF1_Pos)          /*!< 0x00000002 */

+#define DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1_Msk                     /*!< Channel 1 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF2_Pos            (2U)

+#define DMAMUX_CSR_SOF2_Msk            (0x1UL << DMAMUX_CSR_SOF2_Pos)          /*!< 0x00000004 */

+#define DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2_Msk                     /*!< Channel 2 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF3_Pos            (3U)

+#define DMAMUX_CSR_SOF3_Msk            (0x1UL << DMAMUX_CSR_SOF3_Pos)          /*!< 0x00000008 */

+#define DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3_Msk                     /*!< Channel 3 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF4_Pos            (4U)

+#define DMAMUX_CSR_SOF4_Msk            (0x1UL << DMAMUX_CSR_SOF4_Pos)          /*!< 0x00000010 */

+#define DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4_Msk                     /*!< Channel 4 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF5_Pos            (5U)

+#define DMAMUX_CSR_SOF5_Msk            (0x1UL << DMAMUX_CSR_SOF5_Pos)          /*!< 0x00000020 */

+#define DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5_Msk                     /*!< Channel 5 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF6_Pos            (6U)

+#define DMAMUX_CSR_SOF6_Msk            (0x1UL << DMAMUX_CSR_SOF6_Pos)          /*!< 0x00000040 */

+#define DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6_Msk                     /*!< Channel 6 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF7_Pos            (7U)

+#define DMAMUX_CSR_SOF7_Msk            (0x1UL << DMAMUX_CSR_SOF7_Pos)          /*!< 0x00000080 */

+#define DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7_Msk                     /*!< Channel 7 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF8_Pos            (8U)

+#define DMAMUX_CSR_SOF8_Msk            (0x1UL << DMAMUX_CSR_SOF8_Pos)          /*!< 0x00000100 */

+#define DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8_Msk                     /*!< Channel 8 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF9_Pos            (9U)

+#define DMAMUX_CSR_SOF9_Msk            (0x1UL << DMAMUX_CSR_SOF9_Pos)          /*!< 0x00000200 */

+#define DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9_Msk                     /*!< Channel 9 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF10_Pos           (10U)

+#define DMAMUX_CSR_SOF10_Msk           (0x1UL << DMAMUX_CSR_SOF10_Pos)         /*!< 0x00000400 */

+#define DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10_Msk                    /*!< Channel 10 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF11_Pos           (11U)

+#define DMAMUX_CSR_SOF11_Msk           (0x1UL << DMAMUX_CSR_SOF11_Pos)         /*!< 0x00000800 */

+#define DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11_Msk                    /*!< Channel 11 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF12_Pos           (12U)

+#define DMAMUX_CSR_SOF12_Msk           (0x1UL << DMAMUX_CSR_SOF12_Pos)         /*!< 0x00001000 */

+#define DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12_Msk                    /*!< Channel 12 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF13_Pos           (13U)

+#define DMAMUX_CSR_SOF13_Msk           (0x1UL << DMAMUX_CSR_SOF13_Pos)         /*!< 0x00002000 */

+#define DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13_Msk                    /*!< Channel 13 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF14_Pos           (14U)

+#define DMAMUX_CSR_SOF14_Msk           (0x1UL << DMAMUX_CSR_SOF14_Pos)         /*!< 0x00004000 */

+#define DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14_Msk                    /*!< Channel 14 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF15_Pos           (15U)

+#define DMAMUX_CSR_SOF15_Msk           (0x1UL << DMAMUX_CSR_SOF15_Pos)         /*!< 0x00008000 */

+#define DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15_Msk                    /*!< Channel 15 Synchronization overrun event flag */

+

+/********************  Bits definition for DMAMUX_CFR register  **************/

+#define DMAMUX_CFR_CSOF0_Pos           (0U)

+#define DMAMUX_CFR_CSOF0_Msk           (0x1UL << DMAMUX_CFR_CSOF0_Pos)         /*!< 0x00000001 */

+#define DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0_Msk                    /*!< Channel 0 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF1_Pos           (1U)

+#define DMAMUX_CFR_CSOF1_Msk           (0x1UL << DMAMUX_CFR_CSOF1_Pos)         /*!< 0x00000002 */

+#define DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1_Msk                    /*!< Channel 1 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF2_Pos           (2U)

+#define DMAMUX_CFR_CSOF2_Msk           (0x1UL << DMAMUX_CFR_CSOF2_Pos)         /*!< 0x00000004 */

+#define DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2_Msk                    /*!< Channel 2 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF3_Pos           (3U)

+#define DMAMUX_CFR_CSOF3_Msk           (0x1UL << DMAMUX_CFR_CSOF3_Pos)         /*!< 0x00000008 */

+#define DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3_Msk                    /*!< Channel 3 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF4_Pos           (4U)

+#define DMAMUX_CFR_CSOF4_Msk           (0x1UL << DMAMUX_CFR_CSOF4_Pos)         /*!< 0x00000010 */

+#define DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4_Msk                    /*!< Channel 4 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF5_Pos           (5U)

+#define DMAMUX_CFR_CSOF5_Msk           (0x1UL << DMAMUX_CFR_CSOF5_Pos)         /*!< 0x00000020 */

+#define DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5_Msk                    /*!< Channel 5 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF6_Pos           (6U)

+#define DMAMUX_CFR_CSOF6_Msk           (0x1UL << DMAMUX_CFR_CSOF6_Pos)         /*!< 0x00000040 */

+#define DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6_Msk                    /*!< Channel 6 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF7_Pos           (7U)

+#define DMAMUX_CFR_CSOF7_Msk           (0x1UL << DMAMUX_CFR_CSOF7_Pos)         /*!< 0x00000080 */

+#define DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7_Msk                    /*!< Channel 7 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF8_Pos           (8U)

+#define DMAMUX_CFR_CSOF8_Msk           (0x1UL << DMAMUX_CFR_CSOF8_Pos)         /*!< 0x00000100 */

+#define DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8_Msk                    /*!< Channel 8 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF9_Pos           (9U)

+#define DMAMUX_CFR_CSOF9_Msk           (0x1UL << DMAMUX_CFR_CSOF9_Pos)         /*!< 0x00000200 */

+#define DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9_Msk                    /*!< Channel 9 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF10_Pos          (10U)

+#define DMAMUX_CFR_CSOF10_Msk          (0x1UL << DMAMUX_CFR_CSOF10_Pos)        /*!< 0x00000400 */

+#define DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10_Msk                   /*!< Channel 10 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF11_Pos          (11U)

+#define DMAMUX_CFR_CSOF11_Msk          (0x1UL << DMAMUX_CFR_CSOF11_Pos)        /*!< 0x00000800 */

+#define DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11_Msk                   /*!< Channel 11 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF12_Pos          (12U)

+#define DMAMUX_CFR_CSOF12_Msk          (0x1UL << DMAMUX_CFR_CSOF12_Pos)        /*!< 0x00001000 */

+#define DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12_Msk                   /*!< Channel 12 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF13_Pos          (13U)

+#define DMAMUX_CFR_CSOF13_Msk          (0x1UL << DMAMUX_CFR_CSOF13_Pos)        /*!< 0x00002000 */

+#define DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13_Msk                   /*!< Channel 13 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF14_Pos          (14U)

+#define DMAMUX_CFR_CSOF14_Msk          (0x1UL << DMAMUX_CFR_CSOF14_Pos)        /*!< 0x00004000 */

+#define DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14_Msk                   /*!< Channel 14 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF15_Pos          (15U)

+#define DMAMUX_CFR_CSOF15_Msk          (0x1UL << DMAMUX_CFR_CSOF15_Pos)        /*!< 0x00008000 */

+#define DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15_Msk                   /*!< Channel 15 Clear synchronization overrun event flag */

+

+/********************  Bits definition for DMAMUX_RGxCR register  ************/

+#define DMAMUX_RGxCR_SIG_ID_Pos        (0U)

+#define DMAMUX_RGxCR_SIG_ID_Msk        (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)     /*!< 0x0000001F */

+#define DMAMUX_RGxCR_SIG_ID            DMAMUX_RGxCR_SIG_ID_Msk                 /*!< Signal identification */

+#define DMAMUX_RGxCR_SIG_ID_0          (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000001 */

+#define DMAMUX_RGxCR_SIG_ID_1          (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000002 */

+#define DMAMUX_RGxCR_SIG_ID_2          (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000004 */

+#define DMAMUX_RGxCR_SIG_ID_3          (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000008 */

+#define DMAMUX_RGxCR_SIG_ID_4          (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000010 */

+#define DMAMUX_RGxCR_OIE_Pos           (8U)

+#define DMAMUX_RGxCR_OIE_Msk           (0x1UL << DMAMUX_RGxCR_OIE_Pos)         /*!< 0x00000100 */

+#define DMAMUX_RGxCR_OIE               DMAMUX_RGxCR_OIE_Msk                    /*!< Trigger overrun interrupt enable */

+#define DMAMUX_RGxCR_GE_Pos            (16U)

+#define DMAMUX_RGxCR_GE_Msk            (0x1UL << DMAMUX_RGxCR_GE_Pos)          /*!< 0x00010000 */

+#define DMAMUX_RGxCR_GE                DMAMUX_RGxCR_GE_Msk                     /*!< DMA request generator enable */

+#define DMAMUX_RGxCR_GPOL_Pos          (17U)

+#define DMAMUX_RGxCR_GPOL_Msk          (0x3UL << DMAMUX_RGxCR_GPOL_Pos)        /*!< 0x00060000 */

+#define DMAMUX_RGxCR_GPOL              DMAMUX_RGxCR_GPOL_Msk                   /*!< DMA request generator trigger polarity */

+#define DMAMUX_RGxCR_GPOL_0            (0x1UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00020000 */

+#define DMAMUX_RGxCR_GPOL_1            (0x2UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00040000 */

+#define DMAMUX_RGxCR_GNBREQ_Pos        (19U)

+#define DMAMUX_RGxCR_GNBREQ_Msk        (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)     /*!< 0x00F80000 */

+#define DMAMUX_RGxCR_GNBREQ            DMAMUX_RGxCR_GNBREQ_Msk                 /*!< Number of DMA requests to be generated */

+#define DMAMUX_RGxCR_GNBREQ_0          (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00080000 */

+#define DMAMUX_RGxCR_GNBREQ_1          (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00100000 */

+#define DMAMUX_RGxCR_GNBREQ_2          (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00200000 */

+#define DMAMUX_RGxCR_GNBREQ_3          (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00400000 */

+#define DMAMUX_RGxCR_GNBREQ_4          (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00800000 */

+

+/********************  Bits definition for DMAMUX_RGSR register  **************/

+#define DMAMUX_RGSR_OF0_Pos            (0U)

+#define DMAMUX_RGSR_OF0_Msk            (0x1UL << DMAMUX_RGSR_OF0_Pos)          /*!< 0x00000001 */

+#define DMAMUX_RGSR_OF0                DMAMUX_RGSR_OF0_Msk                     /*!< Request generator channel 0 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF1_Pos            (1U)

+#define DMAMUX_RGSR_OF1_Msk            (0x1UL << DMAMUX_RGSR_OF1_Pos)          /*!< 0x00000002 */

+#define DMAMUX_RGSR_OF1                DMAMUX_RGSR_OF1_Msk                     /*!< Request generator channel 1 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF2_Pos            (2U)

+#define DMAMUX_RGSR_OF2_Msk            (0x1UL << DMAMUX_RGSR_OF2_Pos)          /*!< 0x00000004 */

+#define DMAMUX_RGSR_OF2                DMAMUX_RGSR_OF2_Msk                     /*!< Request generator channel 2 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF3_Pos            (3U)

+#define DMAMUX_RGSR_OF3_Msk            (0x1UL << DMAMUX_RGSR_OF3_Pos)          /*!< 0x00000008 */

+#define DMAMUX_RGSR_OF3                DMAMUX_RGSR_OF3_Msk                     /*!< Request generator channel 3 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF4_Pos            (4U)

+#define DMAMUX_RGSR_OF4_Msk            (0x1UL << DMAMUX_RGSR_OF4_Pos)          /*!< 0x00000010 */

+#define DMAMUX_RGSR_OF4                DMAMUX_RGSR_OF4_Msk                     /*!< Request generator channel 4 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF5_Pos            (5U)

+#define DMAMUX_RGSR_OF5_Msk            (0x1UL << DMAMUX_RGSR_OF5_Pos)          /*!< 0x00000020 */

+#define DMAMUX_RGSR_OF5                DMAMUX_RGSR_OF5_Msk                     /*!< Request generator channel 5 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF6_Pos            (6U)

+#define DMAMUX_RGSR_OF6_Msk            (0x1UL << DMAMUX_RGSR_OF6_Pos)          /*!< 0x00000040 */

+#define DMAMUX_RGSR_OF6                DMAMUX_RGSR_OF6_Msk                     /*!< Request generator channel 6 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF7_Pos            (7U)

+#define DMAMUX_RGSR_OF7_Msk            (0x1UL << DMAMUX_RGSR_OF7_Pos)          /*!< 0x00000080 */

+#define DMAMUX_RGSR_OF7                DMAMUX_RGSR_OF7_Msk                     /*!< Request generator channel 7 Trigger overrun event flag */

+

+/********************  Bits definition for DMAMUX_RGCFR register  **************/

+#define DMAMUX_RGCFR_COF0_Pos          (0U)

+#define DMAMUX_RGCFR_COF0_Msk          (0x1UL << DMAMUX_RGCFR_COF0_Pos)        /*!< 0x00000001 */

+#define DMAMUX_RGCFR_COF0              DMAMUX_RGCFR_COF0_Msk                   /*!< Request generator channel 0 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF1_Pos          (1U)

+#define DMAMUX_RGCFR_COF1_Msk          (0x1UL << DMAMUX_RGCFR_COF1_Pos)        /*!< 0x00000002 */

+#define DMAMUX_RGCFR_COF1              DMAMUX_RGCFR_COF1_Msk                   /*!< Request generator channel 1 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF2_Pos          (2U)

+#define DMAMUX_RGCFR_COF2_Msk          (0x1UL << DMAMUX_RGCFR_COF2_Pos)        /*!< 0x00000004 */

+#define DMAMUX_RGCFR_COF2              DMAMUX_RGCFR_COF2_Msk                   /*!< Request generator channel 2 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF3_Pos          (3U)

+#define DMAMUX_RGCFR_COF3_Msk          (0x1UL << DMAMUX_RGCFR_COF3_Pos)        /*!< 0x00000008 */

+#define DMAMUX_RGCFR_COF3              DMAMUX_RGCFR_COF3_Msk                   /*!< Request generator channel 3 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF4_Pos          (4U)

+#define DMAMUX_RGCFR_COF4_Msk          (0x1UL << DMAMUX_RGCFR_COF4_Pos)        /*!< 0x00000010 */

+#define DMAMUX_RGCFR_COF4              DMAMUX_RGCFR_COF4_Msk                   /*!< Request generator channel 4 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF5_Pos          (5U)

+#define DMAMUX_RGCFR_COF5_Msk          (0x1UL << DMAMUX_RGCFR_COF5_Pos)        /*!< 0x00000020 */

+#define DMAMUX_RGCFR_COF5              DMAMUX_RGCFR_COF5_Msk                   /*!< Request generator channel 5 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF6_Pos          (6U)

+#define DMAMUX_RGCFR_COF6_Msk          (0x1UL << DMAMUX_RGCFR_COF6_Pos)        /*!< 0x00000040 */

+#define DMAMUX_RGCFR_COF6              DMAMUX_RGCFR_COF6_Msk                   /*!< Request generator channel 6 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF7_Pos          (7U)

+#define DMAMUX_RGCFR_COF7_Msk          (0x1UL << DMAMUX_RGCFR_COF7_Pos)        /*!< 0x00000080 */

+#define DMAMUX_RGCFR_COF7              DMAMUX_RGCFR_COF7_Msk                   /*!< Request generator channel 7 Clear trigger overrun event flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         AHB Master DMA2D Controller (DMA2D)                */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for DMA2D_CR register  ******************/

+

+#define DMA2D_CR_START_Pos         (0U)

+#define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)               /*!< 0x00000001 */

+#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer                          */

+#define DMA2D_CR_SUSP_Pos          (1U)

+#define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                /*!< 0x00000002 */

+#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer                        */

+#define DMA2D_CR_ABORT_Pos         (2U)

+#define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)               /*!< 0x00000004 */

+#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer                          */

+#define DMA2D_CR_LOM_Pos           (6U)

+#define DMA2D_CR_LOM_Msk           (0x1UL << DMA2D_CR_LOM_Pos)                 /*!< 0x00000040 */

+#define DMA2D_CR_LOM               DMA2D_CR_LOM_Msk                            /*!< Line Offset Mode                         */

+#define DMA2D_CR_TEIE_Pos          (8U)

+#define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                /*!< 0x00000100 */

+#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable         */

+#define DMA2D_CR_TCIE_Pos          (9U)

+#define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                /*!< 0x00000200 */

+#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable      */

+#define DMA2D_CR_TWIE_Pos          (10U)

+#define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                /*!< 0x00000400 */

+#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable     */

+#define DMA2D_CR_CAEIE_Pos         (11U)

+#define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)               /*!< 0x00000800 */

+#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable      */

+#define DMA2D_CR_CTCIE_Pos         (12U)

+#define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)               /*!< 0x00001000 */

+#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */

+#define DMA2D_CR_CEIE_Pos          (13U)

+#define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                /*!< 0x00002000 */

+#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable    */

+#define DMA2D_CR_MODE_Pos          (16U)

+#define DMA2D_CR_MODE_Msk          (0x7UL << DMA2D_CR_MODE_Pos)                /*!< 0x00070000 */

+#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[2:0]                         */

+#define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */

+#define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */

+#define DMA2D_CR_MODE_2            (0x4UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00040000 */

+

+/********************  Bit definition for DMA2D_ISR register  *****************/

+

+#define DMA2D_ISR_TEIF_Pos         (0U)

+#define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)               /*!< 0x00000001 */

+#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag         */

+#define DMA2D_ISR_TCIF_Pos         (1U)

+#define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)               /*!< 0x00000002 */

+#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag      */

+#define DMA2D_ISR_TWIF_Pos         (2U)

+#define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)               /*!< 0x00000004 */

+#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag     */

+#define DMA2D_ISR_CAEIF_Pos        (3U)

+#define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)              /*!< 0x00000008 */

+#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag      */

+#define DMA2D_ISR_CTCIF_Pos        (4U)

+#define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)              /*!< 0x00000010 */

+#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */

+#define DMA2D_ISR_CEIF_Pos         (5U)

+#define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)               /*!< 0x00000020 */

+#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag    */

+

+/********************  Bit definition for DMA2D_IFCR register  ****************/

+

+#define DMA2D_IFCR_CTEIF_Pos       (0U)

+#define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)             /*!< 0x00000001 */

+#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */

+#define DMA2D_IFCR_CTCIF_Pos       (1U)

+#define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)             /*!< 0x00000002 */

+#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */

+#define DMA2D_IFCR_CTWIF_Pos       (2U)

+#define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)             /*!< 0x00000004 */

+#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */

+#define DMA2D_IFCR_CAECIF_Pos      (3U)

+#define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)            /*!< 0x00000008 */

+#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */

+#define DMA2D_IFCR_CCTCIF_Pos      (4U)

+#define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)            /*!< 0x00000010 */

+#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */

+#define DMA2D_IFCR_CCEIF_Pos       (5U)

+#define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)             /*!< 0x00000020 */

+#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */

+

+/********************  Bit definition for DMA2D_FGMAR register  ***************/

+

+#define DMA2D_FGMAR_MA_Pos         (0U)

+#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)        /*!< 0xFFFFFFFF */

+#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Foreground Memory Address */

+

+/********************  Bit definition for DMA2D_FGOR register  ****************/

+

+#define DMA2D_FGOR_LO_Pos          (0U)

+#define DMA2D_FGOR_LO_Msk          (0xFFFFUL << DMA2D_FGOR_LO_Pos)             /*!< 0x0000FFFF */

+#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */

+

+/********************  Bit definition for DMA2D_BGMAR register  ***************/

+

+#define DMA2D_BGMAR_MA_Pos         (0U)

+#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)        /*!< 0xFFFFFFFF */

+#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Background Memory Address */

+

+/********************  Bit definition for DMA2D_BGOR register  ****************/

+

+#define DMA2D_BGOR_LO_Pos          (0U)

+#define DMA2D_BGOR_LO_Msk          (0xFFFFUL << DMA2D_BGOR_LO_Pos)             /*!< 0x0000FFFF */

+#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */

+

+/********************  Bit definition for DMA2D_FGPFCCR register  *************/

+

+#define DMA2D_FGPFCCR_CM_Pos       (0U)

+#define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x0000000F */

+#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */

+#define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */

+#define DMA2D_FGPFCCR_CCM_Pos      (4U)

+#define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)            /*!< 0x00000010 */

+#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */

+#define DMA2D_FGPFCCR_START_Pos    (5U)

+#define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)          /*!< 0x00000020 */

+#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */

+#define DMA2D_FGPFCCR_CS_Pos       (8U)

+#define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)            /*!< 0x0000FF00 */

+#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */

+#define DMA2D_FGPFCCR_AM_Pos       (16U)

+#define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00030000 */

+#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */

+#define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */

+#define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */

+#define DMA2D_FGPFCCR_CSS_Pos      (18U)

+#define DMA2D_FGPFCCR_CSS_Msk      (0x3UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x000C0000 */

+#define DMA2D_FGPFCCR_CSS          DMA2D_FGPFCCR_CSS_Msk                       /* !< Chroma Sub-Sampling */

+#define DMA2D_FGPFCCR_CSS_0        (0x1UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00040000 */

+#define DMA2D_FGPFCCR_CSS_1        (0x2UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00080000 */

+#define DMA2D_FGPFCCR_AI_Pos       (20U)

+#define DMA2D_FGPFCCR_AI_Msk       (0x1UL << DMA2D_FGPFCCR_AI_Pos)             /*!< 0x00100000 */

+#define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Foreground Input Alpha Inverted */

+#define DMA2D_FGPFCCR_RBS_Pos      (21U)

+#define DMA2D_FGPFCCR_RBS_Msk      (0x1UL << DMA2D_FGPFCCR_RBS_Pos)            /*!< 0x00200000 */

+#define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Foreground Input Red Blue Swap */

+#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)

+#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */

+#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */

+

+/********************  Bit definition for DMA2D_FGCOLR register  **************/

+

+#define DMA2D_FGCOLR_BLUE_Pos      (0U)

+#define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)           /*!< 0x000000FF */

+#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Foreground Blue Value */

+#define DMA2D_FGCOLR_GREEN_Pos     (8U)

+#define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */

+#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Foreground Green Value */

+#define DMA2D_FGCOLR_RED_Pos       (16U)

+#define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)            /*!< 0x00FF0000 */

+#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Foreground Red Value */

+

+/********************  Bit definition for DMA2D_BGPFCCR register  *************/

+

+#define DMA2D_BGPFCCR_CM_Pos       (0U)

+#define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x0000000F */

+#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */

+#define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_BGPFCCR_CM_3         (0x8UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000008 */

+#define DMA2D_BGPFCCR_CCM_Pos      (4U)

+#define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)            /*!< 0x00000010 */

+#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */

+#define DMA2D_BGPFCCR_START_Pos    (5U)

+#define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)          /*!< 0x00000020 */

+#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */

+#define DMA2D_BGPFCCR_CS_Pos       (8U)

+#define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)            /*!< 0x0000FF00 */

+#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */

+#define DMA2D_BGPFCCR_AM_Pos       (16U)

+#define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00030000 */

+#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */

+#define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */

+#define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */

+#define DMA2D_BGPFCCR_AI_Pos       (20U)

+#define DMA2D_BGPFCCR_AI_Msk       (0x1UL << DMA2D_BGPFCCR_AI_Pos)             /*!< 0x00100000 */

+#define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< background Input Alpha Inverted */

+#define DMA2D_BGPFCCR_RBS_Pos      (21U)

+#define DMA2D_BGPFCCR_RBS_Msk      (0x1UL << DMA2D_BGPFCCR_RBS_Pos)            /*!< 0x00200000 */

+#define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Background Input Red Blue Swap */

+#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)

+#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */

+#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */

+

+/********************  Bit definition for DMA2D_BGCOLR register  **************/

+

+#define DMA2D_BGCOLR_BLUE_Pos      (0U)

+#define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)           /*!< 0x000000FF */

+#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Background Blue Value */

+#define DMA2D_BGCOLR_GREEN_Pos     (8U)

+#define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */

+#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Background Green Value */

+#define DMA2D_BGCOLR_RED_Pos       (16U)

+#define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)            /*!< 0x00FF0000 */

+#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Background Red Value */

+

+/********************  Bit definition for DMA2D_FGCMAR register  **************/

+

+#define DMA2D_FGCMAR_MA_Pos        (0U)

+#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */

+#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Foreground CLUT Memory Address */

+

+/********************  Bit definition for DMA2D_BGCMAR register  **************/

+

+#define DMA2D_BGCMAR_MA_Pos        (0U)

+#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */

+#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Background CLUT Memory Address */

+

+/********************  Bit definition for DMA2D_OPFCCR register  **************/

+

+#define DMA2D_OPFCCR_CM_Pos        (0U)

+#define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000007 */

+#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Output Color mode CM[2:0] */

+#define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_OPFCCR_SB_Pos        (8U)

+#define DMA2D_OPFCCR_SB_Msk        (0x1UL << DMA2D_OPFCCR_SB_Pos)              /*!< 0x00000100 */

+#define DMA2D_OPFCCR_SB            DMA2D_OPFCCR_SB_Msk                         /*!< Swap Bytes */

+#define DMA2D_OPFCCR_AI_Pos        (20U)

+#define DMA2D_OPFCCR_AI_Msk        (0x1UL << DMA2D_OPFCCR_AI_Pos)              /*!< 0x00100000 */

+#define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Output Alpha Inverted */

+#define DMA2D_OPFCCR_RBS_Pos       (21U)

+#define DMA2D_OPFCCR_RBS_Msk       (0x1UL << DMA2D_OPFCCR_RBS_Pos)             /*!< 0x00200000 */

+#define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Output Red Blue Swap */

+

+/********************  Bit definition for DMA2D_OCOLR register  ***************/

+

+/*!<Mode_ARGB8888/RGB888 */

+

+#define DMA2D_OCOLR_BLUE_1_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_1_Msk     (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos)            /*0x000000FFU*/

+#define DMA2D_OCOLR_BLUE_1         DMA2D_OCOLR_BLUE_1_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_1_Pos    (8U)

+#define DMA2D_OCOLR_GREEN_1_Msk    (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos)            /*0x0000FF00U)*/

+#define DMA2D_OCOLR_GREEN_1        DMA2D_OCOLR_GREEN_1_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_1_Pos      (16U)

+#define DMA2D_OCOLR_RED_1_Msk      (0xFFUL << DMA2D_OCOLR_RED_1_Pos)            /*0x00FF0000U */

+#define DMA2D_OCOLR_RED_1          DMA2D_OCOLR_RED_1_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_1_Pos    (24U)

+#define DMA2D_OCOLR_ALPHA_1_Msk    (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos)          /*0xFF000000U*/

+#define DMA2D_OCOLR_ALPHA_1        DMA2D_OCOLR_ALPHA_1_Msk                     /*!< Output Alpha Channel Value */

+

+/*!<Mode_RGB565 */

+#define DMA2D_OCOLR_BLUE_2_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_2_Msk     (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos)            /*0x0000001FU*/

+#define DMA2D_OCOLR_BLUE_2         DMA2D_OCOLR_BLUE_2_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_2_Pos    (5U)

+#define DMA2D_OCOLR_GREEN_2_Msk    (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos)          /* 0x000007E0U */

+#define DMA2D_OCOLR_GREEN_2        DMA2D_OCOLR_GREEN_2_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_2_Pos      (11U)

+#define DMA2D_OCOLR_RED_2_Msk      (0xF8UL<<DMA2D_OCOLR_RED_2_Pos)              /*0x0000F800U*/

+#define DMA2D_OCOLR_RED_2          DMA2D_OCOLR_RED_2_Msk                       /*!< Output Red Value */

+

+/*!<Mode_ARGB1555 */

+#define DMA2D_OCOLR_BLUE_3_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_3_Msk     (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos)           /*0x0000001FU*/

+#define DMA2D_OCOLR_BLUE_3         DMA2D_OCOLR_BLUE_3_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_3_Pos    (5U)

+#define DMA2D_OCOLR_GREEN_3_Msk    (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos)          /*0x000003E0U*/

+#define DMA2D_OCOLR_GREEN_3        DMA2D_OCOLR_GREEN_3_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_3_Pos      (10U)

+#define DMA2D_OCOLR_RED_3_Msk      (0x7CUL << DMA2D_OCOLR_RED_3_Pos)            /* 0x00007C00U*/

+#define DMA2D_OCOLR_RED_3          DMA2D_OCOLR_RED_3_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_3_Pos    (15U)

+#define DMA2D_OCOLR_ALPHA_3_Msk    (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos)           /*0x00008000U*/

+#define DMA2D_OCOLR_ALPHA_3        DMA2D_OCOLR_ALPHA_3_Msk                     /*!< Output Alpha Channel Value */

+

+/*!<Mode_ARGB4444 */

+#define DMA2D_OCOLR_BLUE_4_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_4_Msk     (0xFUL << DMA2D_OCOLR_BLUE_4_Pos)            /*0x0000000FU*/

+#define DMA2D_OCOLR_BLUE_4         DMA2D_OCOLR_BLUE_4_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_4_Pos    (4U)

+#define DMA2D_OCOLR_GREEN_4_Msk    (0xFUL << DMA2D_OCOLR_GREEN_4_Pos)           /*0x000000F0U*/

+#define DMA2D_OCOLR_GREEN_4        DMA2D_OCOLR_GREEN_4_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_4_Pos      (8U)

+#define DMA2D_OCOLR_RED_4_Msk      (0xFUL << DMA2D_OCOLR_RED_4_Pos)             /*0x00000F00U*/

+#define DMA2D_OCOLR_RED_4          DMA2D_OCOLR_RED_4_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_4_Pos    (12U)

+#define DMA2D_OCOLR_ALPHA_4_Msk    (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos)            /*0x0000F000U*/

+#define DMA2D_OCOLR_ALPHA_4        DMA2D_OCOLR_ALPHA_4_Msk                     /*!< Output Alpha Channel Value */

+

+/********************  Bit definition for DMA2D_OMAR register  ****************/

+

+#define DMA2D_OMAR_MA_Pos          (0U)

+#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)         /*!< 0xFFFFFFFF */

+#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Output Memory Address */

+

+/********************  Bit definition for DMA2D_OOR register  *****************/

+

+#define DMA2D_OOR_LO_Pos           (0U)

+#define DMA2D_OOR_LO_Msk           (0xFFFFUL << DMA2D_OOR_LO_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Output Line Offset */

+

+/********************  Bit definition for DMA2D_NLR register  *****************/

+

+#define DMA2D_NLR_NL_Pos           (0U)

+#define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */

+#define DMA2D_NLR_PL_Pos           (16U)

+#define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)              /*!< 0x3FFF0000 */

+#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */

+

+/********************  Bit definition for DMA2D_LWR register  *****************/

+

+#define DMA2D_LWR_LW_Pos           (0U)

+#define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */

+

+/********************  Bit definition for DMA2D_AMTCR register  ***************/

+

+#define DMA2D_AMTCR_EN_Pos         (0U)

+#define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)               /*!< 0x00000001 */

+#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */

+#define DMA2D_AMTCR_DT_Pos         (8U)

+#define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)              /*!< 0x0000FF00 */

+#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */

+

+

+/********************  Bit definition for DMA2D_FGCLUT register  **************/

+

+/********************  Bit definition for DMA2D_BGCLUT register  **************/

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                    External Interrupt/Event Controller                     */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for EXTI_RTSR1 register  *******************/

+#define EXTI_RTSR1_TR_Pos          (0U)

+#define EXTI_RTSR1_TR_Msk          (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)           /*!< 0x003FFFFF */

+#define EXTI_RTSR1_TR              EXTI_RTSR1_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR1_TR0_Pos         (0U)

+#define EXTI_RTSR1_TR0_Msk         (0x1UL << EXTI_RTSR1_TR0_Pos)               /*!< 0x00000001 */

+#define EXTI_RTSR1_TR0             EXTI_RTSR1_TR0_Msk                          /*!< Rising trigger event configuration bit of line 0 */

+#define EXTI_RTSR1_TR1_Pos         (1U)

+#define EXTI_RTSR1_TR1_Msk         (0x1UL << EXTI_RTSR1_TR1_Pos)               /*!< 0x00000002 */

+#define EXTI_RTSR1_TR1             EXTI_RTSR1_TR1_Msk                          /*!< Rising trigger event configuration bit of line 1 */

+#define EXTI_RTSR1_TR2_Pos         (2U)

+#define EXTI_RTSR1_TR2_Msk         (0x1UL << EXTI_RTSR1_TR2_Pos)               /*!< 0x00000004 */

+#define EXTI_RTSR1_TR2             EXTI_RTSR1_TR2_Msk                          /*!< Rising trigger event configuration bit of line 2 */

+#define EXTI_RTSR1_TR3_Pos         (3U)

+#define EXTI_RTSR1_TR3_Msk         (0x1UL << EXTI_RTSR1_TR3_Pos)               /*!< 0x00000008 */

+#define EXTI_RTSR1_TR3             EXTI_RTSR1_TR3_Msk                          /*!< Rising trigger event configuration bit of line 3 */

+#define EXTI_RTSR1_TR4_Pos         (4U)

+#define EXTI_RTSR1_TR4_Msk         (0x1UL << EXTI_RTSR1_TR4_Pos)               /*!< 0x00000010 */

+#define EXTI_RTSR1_TR4             EXTI_RTSR1_TR4_Msk                          /*!< Rising trigger event configuration bit of line 4 */

+#define EXTI_RTSR1_TR5_Pos         (5U)

+#define EXTI_RTSR1_TR5_Msk         (0x1UL << EXTI_RTSR1_TR5_Pos)               /*!< 0x00000020 */

+#define EXTI_RTSR1_TR5             EXTI_RTSR1_TR5_Msk                          /*!< Rising trigger event configuration bit of line 5 */

+#define EXTI_RTSR1_TR6_Pos         (6U)

+#define EXTI_RTSR1_TR6_Msk         (0x1UL << EXTI_RTSR1_TR6_Pos)               /*!< 0x00000040 */

+#define EXTI_RTSR1_TR6             EXTI_RTSR1_TR6_Msk                          /*!< Rising trigger event configuration bit of line 6 */

+#define EXTI_RTSR1_TR7_Pos         (7U)

+#define EXTI_RTSR1_TR7_Msk         (0x1UL << EXTI_RTSR1_TR7_Pos)               /*!< 0x00000080 */

+#define EXTI_RTSR1_TR7             EXTI_RTSR1_TR7_Msk                          /*!< Rising trigger event configuration bit of line 7 */

+#define EXTI_RTSR1_TR8_Pos         (8U)

+#define EXTI_RTSR1_TR8_Msk         (0x1UL << EXTI_RTSR1_TR8_Pos)               /*!< 0x00000100 */

+#define EXTI_RTSR1_TR8             EXTI_RTSR1_TR8_Msk                          /*!< Rising trigger event configuration bit of line 8 */

+#define EXTI_RTSR1_TR9_Pos         (9U)

+#define EXTI_RTSR1_TR9_Msk         (0x1UL << EXTI_RTSR1_TR9_Pos)               /*!< 0x00000200 */

+#define EXTI_RTSR1_TR9             EXTI_RTSR1_TR9_Msk                          /*!< Rising trigger event configuration bit of line 9 */

+#define EXTI_RTSR1_TR10_Pos        (10U)

+#define EXTI_RTSR1_TR10_Msk        (0x1UL << EXTI_RTSR1_TR10_Pos)              /*!< 0x00000400 */

+#define EXTI_RTSR1_TR10            EXTI_RTSR1_TR10_Msk                         /*!< Rising trigger event configuration bit of line 10 */

+#define EXTI_RTSR1_TR11_Pos        (11U)

+#define EXTI_RTSR1_TR11_Msk        (0x1UL << EXTI_RTSR1_TR11_Pos)              /*!< 0x00000800 */

+#define EXTI_RTSR1_TR11            EXTI_RTSR1_TR11_Msk                         /*!< Rising trigger event configuration bit of line 11 */

+#define EXTI_RTSR1_TR12_Pos        (12U)

+#define EXTI_RTSR1_TR12_Msk        (0x1UL << EXTI_RTSR1_TR12_Pos)              /*!< 0x00001000 */

+#define EXTI_RTSR1_TR12            EXTI_RTSR1_TR12_Msk                         /*!< Rising trigger event configuration bit of line 12 */

+#define EXTI_RTSR1_TR13_Pos        (13U)

+#define EXTI_RTSR1_TR13_Msk        (0x1UL << EXTI_RTSR1_TR13_Pos)              /*!< 0x00002000 */

+#define EXTI_RTSR1_TR13            EXTI_RTSR1_TR13_Msk                         /*!< Rising trigger event configuration bit of line 13 */

+#define EXTI_RTSR1_TR14_Pos        (14U)

+#define EXTI_RTSR1_TR14_Msk        (0x1UL << EXTI_RTSR1_TR14_Pos)              /*!< 0x00004000 */

+#define EXTI_RTSR1_TR14            EXTI_RTSR1_TR14_Msk                         /*!< Rising trigger event configuration bit of line 14 */

+#define EXTI_RTSR1_TR15_Pos        (15U)

+#define EXTI_RTSR1_TR15_Msk        (0x1UL << EXTI_RTSR1_TR15_Pos)              /*!< 0x00008000 */

+#define EXTI_RTSR1_TR15            EXTI_RTSR1_TR15_Msk                         /*!< Rising trigger event configuration bit of line 15 */

+#define EXTI_RTSR1_TR16_Pos        (16U)

+#define EXTI_RTSR1_TR16_Msk        (0x1UL << EXTI_RTSR1_TR16_Pos)              /*!< 0x00010000 */

+#define EXTI_RTSR1_TR16            EXTI_RTSR1_TR16_Msk                         /*!< Rising trigger event configuration bit of line 16 */

+#define EXTI_RTSR1_TR17_Pos        (17U)

+#define EXTI_RTSR1_TR17_Msk        (0x1UL << EXTI_RTSR1_TR17_Pos)              /*!< 0x00020000 */

+#define EXTI_RTSR1_TR17            EXTI_RTSR1_TR17_Msk                         /*!< Rising trigger event configuration bit of line 17 */

+#define EXTI_RTSR1_TR18_Pos        (18U)

+#define EXTI_RTSR1_TR18_Msk        (0x1UL << EXTI_RTSR1_TR18_Pos)              /*!< 0x00040000 */

+#define EXTI_RTSR1_TR18            EXTI_RTSR1_TR18_Msk                         /*!< Rising trigger event configuration bit of line 18 */

+#define EXTI_RTSR1_TR19_Pos        (19U)

+#define EXTI_RTSR1_TR19_Msk        (0x1UL << EXTI_RTSR1_TR19_Pos)              /*!< 0x00080000 */

+#define EXTI_RTSR1_TR19            EXTI_RTSR1_TR19_Msk                         /*!< Rising trigger event configuration bit of line 19 */

+#define EXTI_RTSR1_TR20_Pos        (20U)

+#define EXTI_RTSR1_TR20_Msk        (0x1UL << EXTI_RTSR1_TR20_Pos)              /*!< 0x00100000 */

+#define EXTI_RTSR1_TR20            EXTI_RTSR1_TR20_Msk                         /*!< Rising trigger event configuration bit of line 20 */

+#define EXTI_RTSR1_TR21_Pos        (21U)

+#define EXTI_RTSR1_TR21_Msk        (0x1UL << EXTI_RTSR1_TR21_Pos)              /*!< 0x00200000 */

+#define EXTI_RTSR1_TR21            EXTI_RTSR1_TR21_Msk                         /*!< Rising trigger event configuration bit of line 21 */

+

+/******************  Bit definition for EXTI_FTSR1 register  *******************/

+#define EXTI_FTSR1_TR_Pos          (0U)

+#define EXTI_FTSR1_TR_Msk          (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)           /*!< 0x003FFFFF */

+#define EXTI_FTSR1_TR              EXTI_FTSR1_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR1_TR0_Pos         (0U)

+#define EXTI_FTSR1_TR0_Msk         (0x1UL << EXTI_FTSR1_TR0_Pos)               /*!< 0x00000001 */

+#define EXTI_FTSR1_TR0             EXTI_FTSR1_TR0_Msk                          /*!< Falling trigger event configuration bit of line 0 */

+#define EXTI_FTSR1_TR1_Pos         (1U)

+#define EXTI_FTSR1_TR1_Msk         (0x1UL << EXTI_FTSR1_TR1_Pos)               /*!< 0x00000002 */

+#define EXTI_FTSR1_TR1             EXTI_FTSR1_TR1_Msk                          /*!< Falling trigger event configuration bit of line 1 */

+#define EXTI_FTSR1_TR2_Pos         (2U)

+#define EXTI_FTSR1_TR2_Msk         (0x1UL << EXTI_FTSR1_TR2_Pos)               /*!< 0x00000004 */

+#define EXTI_FTSR1_TR2             EXTI_FTSR1_TR2_Msk                          /*!< Falling trigger event configuration bit of line 2 */

+#define EXTI_FTSR1_TR3_Pos         (3U)

+#define EXTI_FTSR1_TR3_Msk         (0x1UL << EXTI_FTSR1_TR3_Pos)               /*!< 0x00000008 */

+#define EXTI_FTSR1_TR3             EXTI_FTSR1_TR3_Msk                          /*!< Falling trigger event configuration bit of line 3 */

+#define EXTI_FTSR1_TR4_Pos         (4U)

+#define EXTI_FTSR1_TR4_Msk         (0x1UL << EXTI_FTSR1_TR4_Pos)               /*!< 0x00000010 */

+#define EXTI_FTSR1_TR4             EXTI_FTSR1_TR4_Msk                          /*!< Falling trigger event configuration bit of line 4 */

+#define EXTI_FTSR1_TR5_Pos         (5U)

+#define EXTI_FTSR1_TR5_Msk         (0x1UL << EXTI_FTSR1_TR5_Pos)               /*!< 0x00000020 */

+#define EXTI_FTSR1_TR5             EXTI_FTSR1_TR5_Msk                          /*!< Falling trigger event configuration bit of line 5 */

+#define EXTI_FTSR1_TR6_Pos         (6U)

+#define EXTI_FTSR1_TR6_Msk         (0x1UL << EXTI_FTSR1_TR6_Pos)               /*!< 0x00000040 */

+#define EXTI_FTSR1_TR6             EXTI_FTSR1_TR6_Msk                          /*!< Falling trigger event configuration bit of line 6 */

+#define EXTI_FTSR1_TR7_Pos         (7U)

+#define EXTI_FTSR1_TR7_Msk         (0x1UL << EXTI_FTSR1_TR7_Pos)               /*!< 0x00000080 */

+#define EXTI_FTSR1_TR7             EXTI_FTSR1_TR7_Msk                          /*!< Falling trigger event configuration bit of line 7 */

+#define EXTI_FTSR1_TR8_Pos         (8U)

+#define EXTI_FTSR1_TR8_Msk         (0x1UL << EXTI_FTSR1_TR8_Pos)               /*!< 0x00000100 */

+#define EXTI_FTSR1_TR8             EXTI_FTSR1_TR8_Msk                          /*!< Falling trigger event configuration bit of line 8 */

+#define EXTI_FTSR1_TR9_Pos         (9U)

+#define EXTI_FTSR1_TR9_Msk         (0x1UL << EXTI_FTSR1_TR9_Pos)               /*!< 0x00000200 */

+#define EXTI_FTSR1_TR9             EXTI_FTSR1_TR9_Msk                          /*!< Falling trigger event configuration bit of line 9 */

+#define EXTI_FTSR1_TR10_Pos        (10U)

+#define EXTI_FTSR1_TR10_Msk        (0x1UL << EXTI_FTSR1_TR10_Pos)              /*!< 0x00000400 */

+#define EXTI_FTSR1_TR10            EXTI_FTSR1_TR10_Msk                         /*!< Falling trigger event configuration bit of line 10 */

+#define EXTI_FTSR1_TR11_Pos        (11U)

+#define EXTI_FTSR1_TR11_Msk        (0x1UL << EXTI_FTSR1_TR11_Pos)              /*!< 0x00000800 */

+#define EXTI_FTSR1_TR11            EXTI_FTSR1_TR11_Msk                         /*!< Falling trigger event configuration bit of line 11 */

+#define EXTI_FTSR1_TR12_Pos        (12U)

+#define EXTI_FTSR1_TR12_Msk        (0x1UL << EXTI_FTSR1_TR12_Pos)              /*!< 0x00001000 */

+#define EXTI_FTSR1_TR12            EXTI_FTSR1_TR12_Msk                         /*!< Falling trigger event configuration bit of line 12 */

+#define EXTI_FTSR1_TR13_Pos        (13U)

+#define EXTI_FTSR1_TR13_Msk        (0x1UL << EXTI_FTSR1_TR13_Pos)              /*!< 0x00002000 */

+#define EXTI_FTSR1_TR13            EXTI_FTSR1_TR13_Msk                         /*!< Falling trigger event configuration bit of line 13 */

+#define EXTI_FTSR1_TR14_Pos        (14U)

+#define EXTI_FTSR1_TR14_Msk        (0x1UL << EXTI_FTSR1_TR14_Pos)              /*!< 0x00004000 */

+#define EXTI_FTSR1_TR14            EXTI_FTSR1_TR14_Msk                         /*!< Falling trigger event configuration bit of line 14 */

+#define EXTI_FTSR1_TR15_Pos        (15U)

+#define EXTI_FTSR1_TR15_Msk        (0x1UL << EXTI_FTSR1_TR15_Pos)              /*!< 0x00008000 */

+#define EXTI_FTSR1_TR15            EXTI_FTSR1_TR15_Msk                         /*!< Falling trigger event configuration bit of line 15 */

+#define EXTI_FTSR1_TR16_Pos        (16U)

+#define EXTI_FTSR1_TR16_Msk        (0x1UL << EXTI_FTSR1_TR16_Pos)              /*!< 0x00010000 */

+#define EXTI_FTSR1_TR16            EXTI_FTSR1_TR16_Msk                         /*!< Falling trigger event configuration bit of line 16 */

+#define EXTI_FTSR1_TR17_Pos        (17U)

+#define EXTI_FTSR1_TR17_Msk        (0x1UL << EXTI_FTSR1_TR17_Pos)              /*!< 0x00020000 */

+#define EXTI_FTSR1_TR17            EXTI_FTSR1_TR17_Msk                         /*!< Falling trigger event configuration bit of line 17 */

+#define EXTI_FTSR1_TR18_Pos        (18U)

+#define EXTI_FTSR1_TR18_Msk        (0x1UL << EXTI_FTSR1_TR18_Pos)              /*!< 0x00040000 */

+#define EXTI_FTSR1_TR18            EXTI_FTSR1_TR18_Msk                         /*!< Falling trigger event configuration bit of line 18 */

+#define EXTI_FTSR1_TR19_Pos        (19U)

+#define EXTI_FTSR1_TR19_Msk        (0x1UL << EXTI_FTSR1_TR19_Pos)              /*!< 0x00080000 */

+#define EXTI_FTSR1_TR19            EXTI_FTSR1_TR19_Msk                         /*!< Falling trigger event configuration bit of line 19 */

+#define EXTI_FTSR1_TR20_Pos        (20U)

+#define EXTI_FTSR1_TR20_Msk        (0x1UL << EXTI_FTSR1_TR20_Pos)              /*!< 0x00100000 */

+#define EXTI_FTSR1_TR20            EXTI_FTSR1_TR20_Msk                         /*!< Falling trigger event configuration bit of line 20 */

+#define EXTI_FTSR1_TR21_Pos        (21U)

+#define EXTI_FTSR1_TR21_Msk        (0x1UL << EXTI_FTSR1_TR21_Pos)              /*!< 0x00200000 */

+#define EXTI_FTSR1_TR21            EXTI_FTSR1_TR21_Msk                         /*!< Falling trigger event configuration bit of line 21 */

+

+/******************  Bit definition for EXTI_SWIER1 register  ******************/

+#define EXTI_SWIER1_SWIER0_Pos     (0U)

+#define EXTI_SWIER1_SWIER0_Msk     (0x1UL << EXTI_SWIER1_SWIER0_Pos)           /*!< 0x00000001 */

+#define EXTI_SWIER1_SWIER0         EXTI_SWIER1_SWIER0_Msk                      /*!< Software Interrupt on line 0 */

+#define EXTI_SWIER1_SWIER1_Pos     (1U)

+#define EXTI_SWIER1_SWIER1_Msk     (0x1UL << EXTI_SWIER1_SWIER1_Pos)           /*!< 0x00000002 */

+#define EXTI_SWIER1_SWIER1         EXTI_SWIER1_SWIER1_Msk                      /*!< Software Interrupt on line 1 */

+#define EXTI_SWIER1_SWIER2_Pos     (2U)

+#define EXTI_SWIER1_SWIER2_Msk     (0x1UL << EXTI_SWIER1_SWIER2_Pos)           /*!< 0x00000004 */

+#define EXTI_SWIER1_SWIER2         EXTI_SWIER1_SWIER2_Msk                      /*!< Software Interrupt on line 2 */

+#define EXTI_SWIER1_SWIER3_Pos     (3U)

+#define EXTI_SWIER1_SWIER3_Msk     (0x1UL << EXTI_SWIER1_SWIER3_Pos)           /*!< 0x00000008 */

+#define EXTI_SWIER1_SWIER3         EXTI_SWIER1_SWIER3_Msk                      /*!< Software Interrupt on line 3 */

+#define EXTI_SWIER1_SWIER4_Pos     (4U)

+#define EXTI_SWIER1_SWIER4_Msk     (0x1UL << EXTI_SWIER1_SWIER4_Pos)           /*!< 0x00000010 */

+#define EXTI_SWIER1_SWIER4         EXTI_SWIER1_SWIER4_Msk                      /*!< Software Interrupt on line 4 */

+#define EXTI_SWIER1_SWIER5_Pos     (5U)

+#define EXTI_SWIER1_SWIER5_Msk     (0x1UL << EXTI_SWIER1_SWIER5_Pos)           /*!< 0x00000020 */

+#define EXTI_SWIER1_SWIER5         EXTI_SWIER1_SWIER5_Msk                      /*!< Software Interrupt on line 5 */

+#define EXTI_SWIER1_SWIER6_Pos     (6U)

+#define EXTI_SWIER1_SWIER6_Msk     (0x1UL << EXTI_SWIER1_SWIER6_Pos)           /*!< 0x00000040 */

+#define EXTI_SWIER1_SWIER6         EXTI_SWIER1_SWIER6_Msk                      /*!< Software Interrupt on line 6 */

+#define EXTI_SWIER1_SWIER7_Pos     (7U)

+#define EXTI_SWIER1_SWIER7_Msk     (0x1UL << EXTI_SWIER1_SWIER7_Pos)           /*!< 0x00000080 */

+#define EXTI_SWIER1_SWIER7         EXTI_SWIER1_SWIER7_Msk                      /*!< Software Interrupt on line 7 */

+#define EXTI_SWIER1_SWIER8_Pos     (8U)

+#define EXTI_SWIER1_SWIER8_Msk     (0x1UL << EXTI_SWIER1_SWIER8_Pos)           /*!< 0x00000100 */

+#define EXTI_SWIER1_SWIER8         EXTI_SWIER1_SWIER8_Msk                      /*!< Software Interrupt on line 8 */

+#define EXTI_SWIER1_SWIER9_Pos     (9U)

+#define EXTI_SWIER1_SWIER9_Msk     (0x1UL << EXTI_SWIER1_SWIER9_Pos)           /*!< 0x00000200 */

+#define EXTI_SWIER1_SWIER9         EXTI_SWIER1_SWIER9_Msk                      /*!< Software Interrupt on line 9 */

+#define EXTI_SWIER1_SWIER10_Pos    (10U)

+#define EXTI_SWIER1_SWIER10_Msk    (0x1UL << EXTI_SWIER1_SWIER10_Pos)          /*!< 0x00000400 */

+#define EXTI_SWIER1_SWIER10        EXTI_SWIER1_SWIER10_Msk                     /*!< Software Interrupt on line 10 */

+#define EXTI_SWIER1_SWIER11_Pos    (11U)

+#define EXTI_SWIER1_SWIER11_Msk    (0x1UL << EXTI_SWIER1_SWIER11_Pos)          /*!< 0x00000800 */

+#define EXTI_SWIER1_SWIER11        EXTI_SWIER1_SWIER11_Msk                     /*!< Software Interrupt on line 11 */

+#define EXTI_SWIER1_SWIER12_Pos    (12U)

+#define EXTI_SWIER1_SWIER12_Msk    (0x1UL << EXTI_SWIER1_SWIER12_Pos)          /*!< 0x00001000 */

+#define EXTI_SWIER1_SWIER12        EXTI_SWIER1_SWIER12_Msk                     /*!< Software Interrupt on line 12 */

+#define EXTI_SWIER1_SWIER13_Pos    (13U)

+#define EXTI_SWIER1_SWIER13_Msk    (0x1UL << EXTI_SWIER1_SWIER13_Pos)          /*!< 0x00002000 */

+#define EXTI_SWIER1_SWIER13        EXTI_SWIER1_SWIER13_Msk                     /*!< Software Interrupt on line 13 */

+#define EXTI_SWIER1_SWIER14_Pos    (14U)

+#define EXTI_SWIER1_SWIER14_Msk    (0x1UL << EXTI_SWIER1_SWIER14_Pos)          /*!< 0x00004000 */

+#define EXTI_SWIER1_SWIER14        EXTI_SWIER1_SWIER14_Msk                     /*!< Software Interrupt on line 14 */

+#define EXTI_SWIER1_SWIER15_Pos    (15U)

+#define EXTI_SWIER1_SWIER15_Msk    (0x1UL << EXTI_SWIER1_SWIER15_Pos)          /*!< 0x00008000 */

+#define EXTI_SWIER1_SWIER15        EXTI_SWIER1_SWIER15_Msk                     /*!< Software Interrupt on line 15 */

+#define EXTI_SWIER1_SWIER16_Pos    (16U)

+#define EXTI_SWIER1_SWIER16_Msk    (0x1UL << EXTI_SWIER1_SWIER16_Pos)          /*!< 0x00010000 */

+#define EXTI_SWIER1_SWIER16        EXTI_SWIER1_SWIER16_Msk                     /*!< Software Interrupt on line 16 */

+#define EXTI_SWIER1_SWIER17_Pos    (17U)

+#define EXTI_SWIER1_SWIER17_Msk    (0x1UL << EXTI_SWIER1_SWIER17_Pos)          /*!< 0x00020000 */

+#define EXTI_SWIER1_SWIER17        EXTI_SWIER1_SWIER17_Msk                     /*!< Software Interrupt on line 17 */

+#define EXTI_SWIER1_SWIER18_Pos    (18U)

+#define EXTI_SWIER1_SWIER18_Msk    (0x1UL << EXTI_SWIER1_SWIER18_Pos)          /*!< 0x00040000 */

+#define EXTI_SWIER1_SWIER18        EXTI_SWIER1_SWIER18_Msk                     /*!< Software Interrupt on line 18 */

+#define EXTI_SWIER1_SWIER19_Pos    (19U)

+#define EXTI_SWIER1_SWIER19_Msk    (0x1UL << EXTI_SWIER1_SWIER19_Pos)          /*!< 0x00080000 */

+#define EXTI_SWIER1_SWIER19        EXTI_SWIER1_SWIER19_Msk                     /*!< Software Interrupt on line 19 */

+#define EXTI_SWIER1_SWIER20_Pos    (20U)

+#define EXTI_SWIER1_SWIER20_Msk    (0x1UL << EXTI_SWIER1_SWIER20_Pos)          /*!< 0x00100000 */

+#define EXTI_SWIER1_SWIER20        EXTI_SWIER1_SWIER20_Msk                     /*!< Software Interrupt on line 20 */

+#define EXTI_SWIER1_SWIER21_Pos    (21U)

+#define EXTI_SWIER1_SWIER21_Msk    (0x1UL << EXTI_SWIER1_SWIER21_Pos)          /*!< 0x00200000 */

+#define EXTI_SWIER1_SWIER21        EXTI_SWIER1_SWIER21_Msk                     /*!< Software Interrupt on line 21 */

+

+/******************  Bit definition for EXTI_D3PMR1 register  ******************/

+#define EXTI_D3PMR1_MR0_Pos        (0U)

+#define EXTI_D3PMR1_MR0_Msk        (0x1UL << EXTI_D3PMR1_MR0_Pos)              /*!< 0x00000001 */

+#define EXTI_D3PMR1_MR0            EXTI_D3PMR1_MR0_Msk                         /*!< Pending Mask Event for line 0  */

+#define EXTI_D3PMR1_MR1_Pos        (1U)

+#define EXTI_D3PMR1_MR1_Msk        (0x1UL << EXTI_D3PMR1_MR1_Pos)              /*!< 0x00000002 */

+#define EXTI_D3PMR1_MR1            EXTI_D3PMR1_MR1_Msk                         /*!< Pending Mask Event for line 1  */

+#define EXTI_D3PMR1_MR2_Pos        (2U)

+#define EXTI_D3PMR1_MR2_Msk        (0x1UL << EXTI_D3PMR1_MR2_Pos)              /*!< 0x00000004 */

+#define EXTI_D3PMR1_MR2            EXTI_D3PMR1_MR2_Msk                         /*!< Pending Mask Event for line 2  */

+#define EXTI_D3PMR1_MR3_Pos        (3U)

+#define EXTI_D3PMR1_MR3_Msk        (0x1UL << EXTI_D3PMR1_MR3_Pos)              /*!< 0x00000008 */

+#define EXTI_D3PMR1_MR3            EXTI_D3PMR1_MR3_Msk                         /*!< Pending Mask Event for line 3  */

+#define EXTI_D3PMR1_MR4_Pos        (4U)

+#define EXTI_D3PMR1_MR4_Msk        (0x1UL << EXTI_D3PMR1_MR4_Pos)              /*!< 0x00000010 */

+#define EXTI_D3PMR1_MR4            EXTI_D3PMR1_MR4_Msk                         /*!< Pending Mask Event for line 4  */

+#define EXTI_D3PMR1_MR5_Pos        (5U)

+#define EXTI_D3PMR1_MR5_Msk        (0x1UL << EXTI_D3PMR1_MR5_Pos)              /*!< 0x00000020 */

+#define EXTI_D3PMR1_MR5            EXTI_D3PMR1_MR5_Msk                         /*!< Pending Mask Event for line 5  */

+#define EXTI_D3PMR1_MR6_Pos        (6U)

+#define EXTI_D3PMR1_MR6_Msk        (0x1UL << EXTI_D3PMR1_MR6_Pos)              /*!< 0x00000040 */

+#define EXTI_D3PMR1_MR6            EXTI_D3PMR1_MR6_Msk                         /*!< Pending Mask Event for line 6  */

+#define EXTI_D3PMR1_MR7_Pos        (7U)

+#define EXTI_D3PMR1_MR7_Msk        (0x1UL << EXTI_D3PMR1_MR7_Pos)              /*!< 0x00000080 */

+#define EXTI_D3PMR1_MR7            EXTI_D3PMR1_MR7_Msk                         /*!< Pending Mask Event for line 7  */

+#define EXTI_D3PMR1_MR8_Pos        (8U)

+#define EXTI_D3PMR1_MR8_Msk        (0x1UL << EXTI_D3PMR1_MR8_Pos)              /*!< 0x00000100 */

+#define EXTI_D3PMR1_MR8            EXTI_D3PMR1_MR8_Msk                         /*!< Pending Mask Event for line 8  */

+#define EXTI_D3PMR1_MR9_Pos        (9U)

+#define EXTI_D3PMR1_MR9_Msk        (0x1UL << EXTI_D3PMR1_MR9_Pos)              /*!< 0x00000200 */

+#define EXTI_D3PMR1_MR9            EXTI_D3PMR1_MR9_Msk                         /*!< Pending Mask Event for line 9  */

+#define EXTI_D3PMR1_MR10_Pos       (10U)

+#define EXTI_D3PMR1_MR10_Msk       (0x1UL << EXTI_D3PMR1_MR10_Pos)             /*!< 0x00000400 */

+#define EXTI_D3PMR1_MR10           EXTI_D3PMR1_MR10_Msk                        /*!< Pending Mask Event for line 10 */

+#define EXTI_D3PMR1_MR11_Pos       (11U)

+#define EXTI_D3PMR1_MR11_Msk       (0x1UL << EXTI_D3PMR1_MR11_Pos)             /*!< 0x00000800 */

+#define EXTI_D3PMR1_MR11           EXTI_D3PMR1_MR11_Msk                        /*!< Pending Mask Event for line 11 */

+#define EXTI_D3PMR1_MR12_Pos       (12U)

+#define EXTI_D3PMR1_MR12_Msk       (0x1UL << EXTI_D3PMR1_MR12_Pos)             /*!< 0x00001000 */

+#define EXTI_D3PMR1_MR12           EXTI_D3PMR1_MR12_Msk                        /*!< Pending Mask Event for line 12 */

+#define EXTI_D3PMR1_MR13_Pos       (13U)

+#define EXTI_D3PMR1_MR13_Msk       (0x1UL << EXTI_D3PMR1_MR13_Pos)             /*!< 0x00002000 */

+#define EXTI_D3PMR1_MR13           EXTI_D3PMR1_MR13_Msk                        /*!< Pending Mask Event for line 13 */

+#define EXTI_D3PMR1_MR14_Pos       (14U)

+#define EXTI_D3PMR1_MR14_Msk       (0x1UL << EXTI_D3PMR1_MR14_Pos)             /*!< 0x00004000 */

+#define EXTI_D3PMR1_MR14           EXTI_D3PMR1_MR14_Msk                        /*!< Pending Mask Event for line 14 */

+#define EXTI_D3PMR1_MR15_Pos       (15U)

+#define EXTI_D3PMR1_MR15_Msk       (0x1UL << EXTI_D3PMR1_MR15_Pos)             /*!< 0x00008000 */

+#define EXTI_D3PMR1_MR15           EXTI_D3PMR1_MR15_Msk                        /*!< Pending Mask Event for line 15 */

+#define EXTI_D3PMR1_MR19_Pos       (19U)

+#define EXTI_D3PMR1_MR19_Msk       (0x1UL << EXTI_D3PMR1_MR19_Pos)             /*!< 0x00080000 */

+#define EXTI_D3PMR1_MR19           EXTI_D3PMR1_MR19_Msk                        /*!< Pending Mask Event for line 19 */

+#define EXTI_D3PMR1_MR20_Pos       (20U)

+#define EXTI_D3PMR1_MR20_Msk       (0x1UL << EXTI_D3PMR1_MR20_Pos)             /*!< 0x00100000 */

+#define EXTI_D3PMR1_MR20           EXTI_D3PMR1_MR20_Msk                        /*!< Pending Mask Event for line 20 */

+#define EXTI_D3PMR1_MR21_Pos       (21U)

+#define EXTI_D3PMR1_MR21_Msk       (0x1UL << EXTI_D3PMR1_MR21_Pos)             /*!< 0x00200000 */

+#define EXTI_D3PMR1_MR21           EXTI_D3PMR1_MR21_Msk                        /*!< Pending Mask Event for line 21 */

+#define EXTI_D3PMR1_MR25_Pos       (24U)

+#define EXTI_D3PMR1_MR25_Msk       (0x1UL << EXTI_D3PMR1_MR25_Pos)             /*!< 0x01000000 */

+#define EXTI_D3PMR1_MR25           EXTI_D3PMR1_MR25_Msk                        /*!< Pending Mask Event for line 25 */

+

+/*******************  Bit definition for EXTI_D3PCR1L register  ****************/

+#define EXTI_D3PCR1L_PCS0_Pos       (0U)

+#define EXTI_D3PCR1L_PCS0_Msk       (0x3UL << EXTI_D3PCR1L_PCS0_Pos)           /*!< 0x00000003 */

+#define EXTI_D3PCR1L_PCS0           EXTI_D3PCR1L_PCS0_Msk                      /*!< D3 Pending request clear input signal selection on line 0 */

+#define EXTI_D3PCR1L_PCS1_Pos       (2U)

+#define EXTI_D3PCR1L_PCS1_Msk       (0x3UL << EXTI_D3PCR1L_PCS1_Pos)           /*!< 0x000000C0 */

+#define EXTI_D3PCR1L_PCS1           EXTI_D3PCR1L_PCS1_Msk                      /*!< D3 Pending request clear input signal selection on line 1 */

+#define EXTI_D3PCR1L_PCS2_Pos       (4U)

+#define EXTI_D3PCR1L_PCS2_Msk       (0x3UL << EXTI_D3PCR1L_PCS2_Pos)           /*!< 0x00000030 */

+#define EXTI_D3PCR1L_PCS2           EXTI_D3PCR1L_PCS2_Msk                      /*!< D3 Pending request clear input signal selection on line 2 */

+#define EXTI_D3PCR1L_PCS3_Pos       (6U)

+#define EXTI_D3PCR1L_PCS3_Msk       (0x3UL << EXTI_D3PCR1L_PCS3_Pos)           /*!< 0x000000C0 */

+#define EXTI_D3PCR1L_PCS3           EXTI_D3PCR1L_PCS3_Msk                      /*!< D3 Pending request clear input signal selection on line 3 */

+#define EXTI_D3PCR1L_PCS4_Pos       (8U)

+#define EXTI_D3PCR1L_PCS4_Msk       (0x3UL << EXTI_D3PCR1L_PCS4_Pos)           /*!< 0x00000300 */

+#define EXTI_D3PCR1L_PCS4           EXTI_D3PCR1L_PCS4_Msk                      /*!< D3 Pending request clear input signal selection on line 4 */

+#define EXTI_D3PCR1L_PCS5_Pos       (10U)

+#define EXTI_D3PCR1L_PCS5_Msk       (0x3UL << EXTI_D3PCR1L_PCS5_Pos)           /*!< 0x00000C00 */

+#define EXTI_D3PCR1L_PCS5           EXTI_D3PCR1L_PCS5_Msk                      /*!< D3 Pending request clear input signal selection on line 5 */

+#define EXTI_D3PCR1L_PCS6_Pos       (12U)

+#define EXTI_D3PCR1L_PCS6_Msk       (0x3UL << EXTI_D3PCR1L_PCS6_Pos)           /*!< 0x00003000 */

+#define EXTI_D3PCR1L_PCS6           EXTI_D3PCR1L_PCS6_Msk                      /*!< D3 Pending request clear input signal selection on line 6 */

+#define EXTI_D3PCR1L_PCS7_Pos       (14U)

+#define EXTI_D3PCR1L_PCS7_Msk       (0x3UL << EXTI_D3PCR1L_PCS7_Pos)           /*!< 0x0000C000 */

+#define EXTI_D3PCR1L_PCS7           EXTI_D3PCR1L_PCS7_Msk                      /*!< D3 Pending request clear input signal selection on line 7 */

+#define EXTI_D3PCR1L_PCS8_Pos       (16U)

+#define EXTI_D3PCR1L_PCS8_Msk       (0x3UL << EXTI_D3PCR1L_PCS8_Pos)           /*!< 0x00030000 */

+#define EXTI_D3PCR1L_PCS8           EXTI_D3PCR1L_PCS8_Msk                      /*!< D3 Pending request clear input signal selection on line 8 */

+#define EXTI_D3PCR1L_PCS9_Pos       (18U)

+#define EXTI_D3PCR1L_PCS9_Msk       (0x3UL << EXTI_D3PCR1L_PCS9_Pos)           /*!< 0x000C0000 */

+#define EXTI_D3PCR1L_PCS9           EXTI_D3PCR1L_PCS9_Msk                      /*!< D3 Pending request clear input signal selection on line 9 */

+#define EXTI_D3PCR1L_PCS10_Pos      (20U)

+#define EXTI_D3PCR1L_PCS10_Msk      (0x3UL << EXTI_D3PCR1L_PCS10_Pos)          /*!< 0x00300000 */

+#define EXTI_D3PCR1L_PCS10          EXTI_D3PCR1L_PCS10_Msk                     /*!< D3 Pending request clear input signal selection on line 10*/

+#define EXTI_D3PCR1L_PCS11_Pos      (22U)

+#define EXTI_D3PCR1L_PCS11_Msk      (0x3UL << EXTI_D3PCR1L_PCS11_Pos)          /*!< 0x00C00000 */

+#define EXTI_D3PCR1L_PCS11          EXTI_D3PCR1L_PCS11_Msk                     /*!< D3 Pending request clear input signal selection on line 11*/

+#define EXTI_D3PCR1L_PCS12_Pos      (24U)

+#define EXTI_D3PCR1L_PCS12_Msk      (0x3UL << EXTI_D3PCR1L_PCS12_Pos)          /*!< 0x03000000 */

+#define EXTI_D3PCR1L_PCS12          EXTI_D3PCR1L_PCS12_Msk                     /*!< D3 Pending request clear input signal selection on line 12*/

+#define EXTI_D3PCR1L_PCS13_Pos      (26U)

+#define EXTI_D3PCR1L_PCS13_Msk      (0x3UL << EXTI_D3PCR1L_PCS13_Pos)          /*!< 0x0C000000 */

+#define EXTI_D3PCR1L_PCS13          EXTI_D3PCR1L_PCS13_Msk                     /*!< D3 Pending request clear input signal selection on line 13*/

+#define EXTI_D3PCR1L_PCS14_Pos      (28U)

+#define EXTI_D3PCR1L_PCS14_Msk      (0x3UL << EXTI_D3PCR1L_PCS14_Pos)          /*!< 0x30000000 */

+#define EXTI_D3PCR1L_PCS14          EXTI_D3PCR1L_PCS14_Msk                     /*!< D3 Pending request clear input signal selection on line 14*/

+#define EXTI_D3PCR1L_PCS15_Pos      (30U)

+#define EXTI_D3PCR1L_PCS15_Msk      (0x3UL << EXTI_D3PCR1L_PCS15_Pos)          /*!< 0xC0000000 */

+#define EXTI_D3PCR1L_PCS15          EXTI_D3PCR1L_PCS15_Msk                     /*!< D3 Pending request clear input signal selection on line 15*/

+

+/*******************  Bit definition for EXTI_D3PCR1H register  ****************/

+#define EXTI_D3PCR1H_PCS19_Pos       (6U)

+#define EXTI_D3PCR1H_PCS19_Msk       (0x3UL << EXTI_D3PCR1H_PCS19_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR1H_PCS19           EXTI_D3PCR1H_PCS19_Msk                    /*!< D3 Pending request clear input signal selection on line 19 */

+#define EXTI_D3PCR1H_PCS20_Pos       (8U)

+#define EXTI_D3PCR1H_PCS20_Msk       (0x3UL << EXTI_D3PCR1H_PCS20_Pos)         /*!< 0x00000300 */

+#define EXTI_D3PCR1H_PCS20           EXTI_D3PCR1H_PCS20_Msk                    /*!< D3 Pending request clear input signal selection on line 20 */

+#define EXTI_D3PCR1H_PCS21_Pos       (10U)

+#define EXTI_D3PCR1H_PCS21_Msk       (0x3UL << EXTI_D3PCR1H_PCS21_Pos)         /*!< 0x00000C00 */

+#define EXTI_D3PCR1H_PCS21           EXTI_D3PCR1H_PCS21_Msk                    /*!< D3 Pending request clear input signal selection on line 21 */

+#define EXTI_D3PCR1H_PCS25_Pos       (18U)

+#define EXTI_D3PCR1H_PCS25_Msk       (0x3UL << EXTI_D3PCR1H_PCS25_Pos)         /*!< 0x000C0000 */

+#define EXTI_D3PCR1H_PCS25           EXTI_D3PCR1H_PCS25_Msk                    /*!< D3 Pending request clear input signal selection on line 25 */

+

+/******************  Bit definition for EXTI_RTSR2 register  *******************/

+#define EXTI_RTSR2_TR_Pos          (17U)

+#define EXTI_RTSR2_TR_Msk          (0x5UL << EXTI_RTSR2_TR_Pos)                /*!< 0x000A0000 */

+#define EXTI_RTSR2_TR              EXTI_RTSR2_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR2_TR49_Pos        (17U)

+#define EXTI_RTSR2_TR49_Msk        (0x1UL << EXTI_RTSR2_TR49_Pos)              /*!< 0x00020000 */

+#define EXTI_RTSR2_TR49            EXTI_RTSR2_TR49_Msk                         /*!< Rising trigger event configuration bit of line 49 */

+#define EXTI_RTSR2_TR51_Pos        (19U)

+#define EXTI_RTSR2_TR51_Msk        (0x1UL << EXTI_RTSR2_TR51_Pos)              /*!< 0x00080000 */

+#define EXTI_RTSR2_TR51            EXTI_RTSR2_TR51_Msk                         /*!< Rising trigger event configuration bit of line 51 */

+

+/******************  Bit definition for EXTI_FTSR2 register  *******************/

+#define EXTI_FTSR2_TR_Pos          (17U)

+#define EXTI_FTSR2_TR_Msk          (0x5UL << EXTI_FTSR2_TR_Pos)                /*!< 0x000A0000 */

+#define EXTI_FTSR2_TR              EXTI_FTSR2_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR2_TR49_Pos        (17U)

+#define EXTI_FTSR2_TR49_Msk        (0x1UL << EXTI_FTSR2_TR49_Pos)              /*!< 0x00020000 */

+#define EXTI_FTSR2_TR49            EXTI_FTSR2_TR49_Msk                         /*!< Falling trigger event configuration bit of line 49 */

+#define EXTI_FTSR2_TR51_Pos        (19U)

+#define EXTI_FTSR2_TR51_Msk        (0x1UL << EXTI_FTSR2_TR51_Pos)              /*!< 0x00080000 */

+#define EXTI_FTSR2_TR51            EXTI_FTSR2_TR51_Msk                         /*!< Falling trigger event configuration bit of line 51 */

+

+/******************  Bit definition for EXTI_SWIER2 register  ******************/

+#define EXTI_SWIER2_SWIER49_Pos    (17U)

+#define EXTI_SWIER2_SWIER49_Msk    (0x1UL << EXTI_SWIER2_SWIER49_Pos)          /*!< 0x00020000 */

+#define EXTI_SWIER2_SWIER49        EXTI_SWIER2_SWIER49_Msk                     /*!< Software Interrupt on line 49 */

+#define EXTI_SWIER2_SWIER51_Pos    (19U)

+#define EXTI_SWIER2_SWIER51_Msk    (0x1UL << EXTI_SWIER2_SWIER51_Pos)          /*!< 0x00080000 */

+#define EXTI_SWIER2_SWIER51        EXTI_SWIER2_SWIER51_Msk                     /*!< Software Interrupt on line 51 */

+

+/******************  Bit definition for EXTI_D3PMR2 register  ******************/

+#define EXTI_D3PMR2_MR34_Pos       (2U)

+#define EXTI_D3PMR2_MR34_Msk       (0x1UL << EXTI_D3PMR2_MR34_Pos)             /*!< 0x00000004 */

+#define EXTI_D3PMR2_MR34           EXTI_D3PMR2_MR34_Msk                        /*!< Pending Mask Event for line 34  */

+#define EXTI_D3PMR2_MR35_Pos       (3U)

+#define EXTI_D3PMR2_MR35_Msk       (0x1UL << EXTI_D3PMR2_MR35_Pos)             /*!< 0x00000008 */

+#define EXTI_D3PMR2_MR35           EXTI_D3PMR2_MR35_Msk                        /*!< Pending Mask Event for line 35  */

+#define EXTI_D3PMR2_MR41_Pos       (9U)

+#define EXTI_D3PMR2_MR41_Msk       (0x1UL << EXTI_D3PMR2_MR41_Pos)             /*!< 0x00000200 */

+#define EXTI_D3PMR2_MR41           EXTI_D3PMR2_MR41_Msk                        /*!< Pending Mask Event for line 41  */

+#define EXTI_D3PMR2_MR48_Pos       (16U)

+#define EXTI_D3PMR2_MR48_Msk       (0x1UL << EXTI_D3PMR2_MR48_Pos)             /*!< 0x00010000 */

+#define EXTI_D3PMR2_MR48           EXTI_D3PMR2_MR48_Msk                        /*!< Pending Mask Event for line 48  */

+#define EXTI_D3PMR2_MR49_Pos       (17U)

+#define EXTI_D3PMR2_MR49_Msk       (0x1UL << EXTI_D3PMR2_MR49_Pos)             /*!< 0x00020000 */

+#define EXTI_D3PMR2_MR49           EXTI_D3PMR2_MR49_Msk                        /*!< Pending Mask Event for line 49  */

+#define EXTI_D3PMR2_MR50_Pos       (18U)

+#define EXTI_D3PMR2_MR50_Msk       (0x1UL << EXTI_D3PMR2_MR50_Pos)             /*!< 0x00040000 */

+#define EXTI_D3PMR2_MR50           EXTI_D3PMR2_MR50_Msk                        /*!< Pending Mask Event for line 50  */

+#define EXTI_D3PMR2_MR51_Pos       (19U)

+#define EXTI_D3PMR2_MR51_Msk       (0x1UL << EXTI_D3PMR2_MR51_Pos)             /*!< 0x00080000 */

+#define EXTI_D3PMR2_MR51           EXTI_D3PMR2_MR51_Msk                        /*!< Pending Mask Event for line 51  */

+#define EXTI_D3PMR2_MR52_Pos       (20U)

+#define EXTI_D3PMR2_MR52_Msk       (0x1UL << EXTI_D3PMR2_MR52_Pos)             /*!< 0x00100000 */

+#define EXTI_D3PMR2_MR52           EXTI_D3PMR2_MR52_Msk                        /*!< Pending Mask Event for line 52  */

+#define EXTI_D3PMR2_MR53_Pos       (21U)

+#define EXTI_D3PMR2_MR53_Msk       (0x1UL << EXTI_D3PMR2_MR53_Pos)             /*!< 0x00200000 */

+#define EXTI_D3PMR2_MR53           EXTI_D3PMR2_MR53_Msk                        /*!< Pending Mask Event for line 53  */

+/*******************  Bit definition for EXTI_D3PCR2L register  ****************/

+#define EXTI_D3PCR2L_PCS34_Pos       (4U)

+#define EXTI_D3PCR2L_PCS34_Msk       (0x3UL << EXTI_D3PCR2L_PCS34_Pos)         /*!< 0x00000030 */

+#define EXTI_D3PCR2L_PCS34           EXTI_D3PCR2L_PCS34_Msk                    /*!< D3 Pending request clear input signal selection on line 34 */

+#define EXTI_D3PCR2L_PCS35_Pos       (6U)

+#define EXTI_D3PCR2L_PCS35_Msk       (0x3UL << EXTI_D3PCR2L_PCS35_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR2L_PCS35           EXTI_D3PCR2L_PCS35_Msk                    /*!< D3 Pending request clear input signal selection on line 35 */

+#define EXTI_D3PCR2L_PCS41_Pos       (18U)

+#define EXTI_D3PCR2L_PCS41_Msk       (0x3UL << EXTI_D3PCR2L_PCS41_Pos)         /*!< 0x000C0000 */

+#define EXTI_D3PCR2L_PCS41           EXTI_D3PCR2L_PCS41_Msk                    /*!< D3 Pending request clear input signal selection on line 41 */

+

+

+/*******************  Bit definition for EXTI_D3PCR2H register  ****************/

+#define EXTI_D3PCR2H_PCS48_Pos       (0U)

+#define EXTI_D3PCR2H_PCS48_Msk       (0x3UL << EXTI_D3PCR2H_PCS48_Pos)         /*!< 0x00000003 */

+#define EXTI_D3PCR2H_PCS48           EXTI_D3PCR2H_PCS48_Msk                    /*!< D3 Pending request clear input signal selection on line 48 */

+#define EXTI_D3PCR2H_PCS49_Pos       (2U)

+#define EXTI_D3PCR2H_PCS49_Msk       (0x3UL << EXTI_D3PCR2H_PCS49_Pos)         /*!< 0x0000000C */

+#define EXTI_D3PCR2H_PCS49           EXTI_D3PCR2H_PCS49_Msk                    /*!< D3 Pending request clear input signal selection on line 49 */

+#define EXTI_D3PCR2H_PCS50_Pos       (4U)

+#define EXTI_D3PCR2H_PCS50_Msk       (0x3UL << EXTI_D3PCR2H_PCS50_Pos)         /*!< 0x00000030 */

+#define EXTI_D3PCR2H_PCS50           EXTI_D3PCR2H_PCS50_Msk                    /*!< D3 Pending request clear input signal selection on line 50 */

+#define EXTI_D3PCR2H_PCS51_Pos       (6U)

+#define EXTI_D3PCR2H_PCS51_Msk       (0x3UL << EXTI_D3PCR2H_PCS51_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR2H_PCS51           EXTI_D3PCR2H_PCS51_Msk                    /*!< D3 Pending request clear input signal selection on line 51 */

+#define EXTI_D3PCR2H_PCS52_Pos       (8U)

+#define EXTI_D3PCR2H_PCS52_Msk       (0x3UL << EXTI_D3PCR2H_PCS52_Pos)         /*!< 0x00000300 */

+#define EXTI_D3PCR2H_PCS52           EXTI_D3PCR2H_PCS52_Msk                    /*!< D3 Pending request clear input signal selection on line 52 */

+#define EXTI_D3PCR2H_PCS53_Pos       (10U)

+#define EXTI_D3PCR2H_PCS53_Msk       (0x3UL << EXTI_D3PCR2H_PCS53_Pos)         /*!< 0x00000C00 */

+#define EXTI_D3PCR2H_PCS53           EXTI_D3PCR2H_PCS53_Msk                    /*!< D3 Pending request clear input signal selection on line 53 */

+/******************  Bit definition for EXTI_RTSR3 register  *******************/

+#define EXTI_RTSR3_TR_Pos          (18U)

+#define EXTI_RTSR3_TR_Msk          (0x1DUL << EXTI_RTSR3_TR_Pos)               /*!< 0x00740000 */

+#define EXTI_RTSR3_TR              EXTI_RTSR3_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR3_TR82_Pos        (18U)

+#define EXTI_RTSR3_TR82_Msk        (0x1UL << EXTI_RTSR3_TR82_Pos)              /*!< 0x00040000 */

+#define EXTI_RTSR3_TR82            EXTI_RTSR3_TR82_Msk                         /*!< Rising trigger event configuration bit of line 82 */

+#define EXTI_RTSR3_TR84_Pos        (20U)

+#define EXTI_RTSR3_TR84_Msk        (0x1UL << EXTI_RTSR3_TR84_Pos)              /*!< 0x00100000 */

+#define EXTI_RTSR3_TR84            EXTI_RTSR3_TR84_Msk                         /*!< Rising trigger event configuration bit of line 84 */

+#define EXTI_RTSR3_TR85_Pos        (21U)

+#define EXTI_RTSR3_TR85_Msk        (0x1UL << EXTI_RTSR3_TR85_Pos)              /*!< 0x00200000 */

+#define EXTI_RTSR3_TR85            EXTI_RTSR3_TR85_Msk                         /*!< Rising trigger event configuration bit of line 85 */

+#define EXTI_RTSR3_TR86_Pos        (22U)

+#define EXTI_RTSR3_TR86_Msk        (0x1UL << EXTI_RTSR3_TR86_Pos)              /*!< 0x00400000 */

+#define EXTI_RTSR3_TR86            EXTI_RTSR3_TR86_Msk                         /*!< Rising trigger event configuration bit of line 86 */

+

+/******************  Bit definition for EXTI_FTSR3 register  *******************/

+#define EXTI_FTSR3_TR_Pos          (18U)

+#define EXTI_FTSR3_TR_Msk          (0x1DUL << EXTI_FTSR3_TR_Pos)               /*!< 0x00740000 */

+#define EXTI_FTSR3_TR              EXTI_FTSR3_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR3_TR82_Pos        (18U)

+#define EXTI_FTSR3_TR82_Msk        (0x1UL << EXTI_FTSR3_TR82_Pos)              /*!< 0x00040000 */

+#define EXTI_FTSR3_TR82            EXTI_FTSR3_TR82_Msk                         /*!< Falling trigger event configuration bit of line 82 */

+#define EXTI_FTSR3_TR84_Pos        (20U)

+#define EXTI_FTSR3_TR84_Msk        (0x1UL << EXTI_FTSR3_TR84_Pos)              /*!< 0x00100000 */

+#define EXTI_FTSR3_TR84            EXTI_FTSR3_TR84_Msk                         /*!< Falling trigger event configuration bit of line 84 */

+#define EXTI_FTSR3_TR85_Pos        (21U)

+#define EXTI_FTSR3_TR85_Msk        (0x1UL << EXTI_FTSR3_TR85_Pos)              /*!< 0x00200000 */

+#define EXTI_FTSR3_TR85            EXTI_FTSR3_TR85_Msk                         /*!< Falling trigger event configuration bit of line 85 */

+#define EXTI_FTSR3_TR86_Pos        (22U)

+#define EXTI_FTSR3_TR86_Msk        (0x1UL << EXTI_FTSR3_TR86_Pos)              /*!< 0x00400000 */

+#define EXTI_FTSR3_TR86            EXTI_FTSR3_TR86_Msk                         /*!< Falling trigger event configuration bit of line 86 */

+

+/******************  Bit definition for EXTI_SWIER3 register  ******************/

+#define EXTI_SWIER3_SWI_Pos        (18U)

+#define EXTI_SWIER3_SWI_Msk        (0x1DUL << EXTI_SWIER3_SWI_Pos)             /*!< 0x00740000 */

+#define EXTI_SWIER3_SWI            EXTI_SWIER3_SWI_Msk                         /*!< Software Interrupt event bit */

+#define EXTI_SWIER3_SWIER82_Pos    (18U)

+#define EXTI_SWIER3_SWIER82_Msk    (0x1UL << EXTI_SWIER3_SWIER82_Pos)          /*!< 0x00040000 */

+#define EXTI_SWIER3_SWIER82        EXTI_SWIER3_SWIER82_Msk                     /*!< Software Interrupt on line 82 */

+#define EXTI_SWIER3_SWIER84_Pos    (20U)

+#define EXTI_SWIER3_SWIER84_Msk    (0x1UL << EXTI_SWIER3_SWIER84_Pos)          /*!< 0x00100000 */

+#define EXTI_SWIER3_SWIER84        EXTI_SWIER3_SWIER84_Msk                     /*!< Software Interrupt on line 84 */

+#define EXTI_SWIER3_SWIER85_Pos    (21U)

+#define EXTI_SWIER3_SWIER85_Msk    (0x1UL << EXTI_SWIER3_SWIER85_Pos)          /*!< 0x00200000 */

+#define EXTI_SWIER3_SWIER85        EXTI_SWIER3_SWIER85_Msk                     /*!< Software Interrupt on line 85 */

+#define EXTI_SWIER3_SWIER86_Pos    (22U)

+#define EXTI_SWIER3_SWIER86_Msk    (0x1UL << EXTI_SWIER3_SWIER86_Pos)          /*!< 0x00400000 */

+#define EXTI_SWIER3_SWIER86        EXTI_SWIER3_SWIER86_Msk                     /*!< Software Interrupt on line 86 */

+

+/*******************  Bit definition for EXTI_IMR1 register  *******************/

+#define EXTI_IMR1_IM_Pos           (0U)

+#define EXTI_IMR1_IM_Msk           (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)          /*!< 0xFFFFFFFF */

+#define EXTI_IMR1_IM               EXTI_IMR1_IM_Msk                            /*!< Interrupt Mask */

+#define EXTI_IMR1_IM0_Pos          (0U)

+#define EXTI_IMR1_IM0_Msk          (0x1UL << EXTI_IMR1_IM0_Pos)                /*!< 0x00000001 */

+#define EXTI_IMR1_IM0              EXTI_IMR1_IM0_Msk                           /*!< Interrupt Mask on line 0 */

+#define EXTI_IMR1_IM1_Pos          (1U)

+#define EXTI_IMR1_IM1_Msk          (0x1UL << EXTI_IMR1_IM1_Pos)                /*!< 0x00000002 */

+#define EXTI_IMR1_IM1              EXTI_IMR1_IM1_Msk                           /*!< Interrupt Mask on line 1 */

+#define EXTI_IMR1_IM2_Pos          (2U)

+#define EXTI_IMR1_IM2_Msk          (0x1UL << EXTI_IMR1_IM2_Pos)                /*!< 0x00000004 */

+#define EXTI_IMR1_IM2              EXTI_IMR1_IM2_Msk                           /*!< Interrupt Mask on line 2 */

+#define EXTI_IMR1_IM3_Pos          (3U)

+#define EXTI_IMR1_IM3_Msk          (0x1UL << EXTI_IMR1_IM3_Pos)                /*!< 0x00000008 */

+#define EXTI_IMR1_IM3              EXTI_IMR1_IM3_Msk                           /*!< Interrupt Mask on line 3 */

+#define EXTI_IMR1_IM4_Pos          (4U)

+#define EXTI_IMR1_IM4_Msk          (0x1UL << EXTI_IMR1_IM4_Pos)                /*!< 0x00000010 */

+#define EXTI_IMR1_IM4              EXTI_IMR1_IM4_Msk                           /*!< Interrupt Mask on line 4 */

+#define EXTI_IMR1_IM5_Pos          (5U)

+#define EXTI_IMR1_IM5_Msk          (0x1UL << EXTI_IMR1_IM5_Pos)                /*!< 0x00000020 */

+#define EXTI_IMR1_IM5              EXTI_IMR1_IM5_Msk                           /*!< Interrupt Mask on line 5 */

+#define EXTI_IMR1_IM6_Pos          (6U)

+#define EXTI_IMR1_IM6_Msk          (0x1UL << EXTI_IMR1_IM6_Pos)                /*!< 0x00000040 */

+#define EXTI_IMR1_IM6              EXTI_IMR1_IM6_Msk                           /*!< Interrupt Mask on line 6 */

+#define EXTI_IMR1_IM7_Pos          (7U)

+#define EXTI_IMR1_IM7_Msk          (0x1UL << EXTI_IMR1_IM7_Pos)                /*!< 0x00000080 */

+#define EXTI_IMR1_IM7              EXTI_IMR1_IM7_Msk                           /*!< Interrupt Mask on line 7 */

+#define EXTI_IMR1_IM8_Pos          (8U)

+#define EXTI_IMR1_IM8_Msk          (0x1UL << EXTI_IMR1_IM8_Pos)                /*!< 0x00000100 */

+#define EXTI_IMR1_IM8              EXTI_IMR1_IM8_Msk                           /*!< Interrupt Mask on line 8 */

+#define EXTI_IMR1_IM9_Pos          (9U)

+#define EXTI_IMR1_IM9_Msk          (0x1UL << EXTI_IMR1_IM9_Pos)                /*!< 0x00000200 */

+#define EXTI_IMR1_IM9              EXTI_IMR1_IM9_Msk                           /*!< Interrupt Mask on line 9 */

+#define EXTI_IMR1_IM10_Pos         (10U)

+#define EXTI_IMR1_IM10_Msk         (0x1UL << EXTI_IMR1_IM10_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR1_IM10             EXTI_IMR1_IM10_Msk                          /*!< Interrupt Mask on line 10 */

+#define EXTI_IMR1_IM11_Pos         (11U)

+#define EXTI_IMR1_IM11_Msk         (0x1UL << EXTI_IMR1_IM11_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR1_IM11             EXTI_IMR1_IM11_Msk                          /*!< Interrupt Mask on line 11 */

+#define EXTI_IMR1_IM12_Pos         (12U)

+#define EXTI_IMR1_IM12_Msk         (0x1UL << EXTI_IMR1_IM12_Pos)               /*!< 0x00001000 */

+#define EXTI_IMR1_IM12             EXTI_IMR1_IM12_Msk                          /*!< Interrupt Mask on line 12 */

+#define EXTI_IMR1_IM13_Pos         (13U)

+#define EXTI_IMR1_IM13_Msk         (0x1UL << EXTI_IMR1_IM13_Pos)               /*!< 0x00002000 */

+#define EXTI_IMR1_IM13             EXTI_IMR1_IM13_Msk                          /*!< Interrupt Mask on line 13 */

+#define EXTI_IMR1_IM14_Pos         (14U)

+#define EXTI_IMR1_IM14_Msk         (0x1UL << EXTI_IMR1_IM14_Pos)               /*!< 0x00004000 */

+#define EXTI_IMR1_IM14             EXTI_IMR1_IM14_Msk                          /*!< Interrupt Mask on line 14 */

+#define EXTI_IMR1_IM15_Pos         (15U)

+#define EXTI_IMR1_IM15_Msk         (0x1UL << EXTI_IMR1_IM15_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR1_IM15             EXTI_IMR1_IM15_Msk                          /*!< Interrupt Mask on line 15 */

+#define EXTI_IMR1_IM16_Pos         (16U)

+#define EXTI_IMR1_IM16_Msk         (0x1UL << EXTI_IMR1_IM16_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR1_IM16             EXTI_IMR1_IM16_Msk                          /*!< Interrupt Mask on line 16 */

+#define EXTI_IMR1_IM17_Pos         (17U)

+#define EXTI_IMR1_IM17_Msk         (0x1UL << EXTI_IMR1_IM17_Pos)               /*!< 0x00020000 */

+#define EXTI_IMR1_IM17             EXTI_IMR1_IM17_Msk                          /*!< Interrupt Mask on line 17 */

+#define EXTI_IMR1_IM18_Pos         (18U)

+#define EXTI_IMR1_IM18_Msk         (0x1UL << EXTI_IMR1_IM18_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR1_IM18             EXTI_IMR1_IM18_Msk                          /*!< Interrupt Mask on line 18 */

+#define EXTI_IMR1_IM19_Pos         (19U)

+#define EXTI_IMR1_IM19_Msk         (0x1UL << EXTI_IMR1_IM19_Pos)               /*!< 0x00080000 */

+#define EXTI_IMR1_IM19             EXTI_IMR1_IM19_Msk                          /*!< Interrupt Mask on line 19 */

+#define EXTI_IMR1_IM20_Pos         (20U)

+#define EXTI_IMR1_IM20_Msk         (0x1UL << EXTI_IMR1_IM20_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR1_IM20             EXTI_IMR1_IM20_Msk                          /*!< Interrupt Mask on line 20 */

+#define EXTI_IMR1_IM21_Pos         (21U)

+#define EXTI_IMR1_IM21_Msk         (0x1UL << EXTI_IMR1_IM21_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR1_IM21             EXTI_IMR1_IM21_Msk                          /*!< Interrupt Mask on line 21 */

+#define EXTI_IMR1_IM22_Pos         (22U)

+#define EXTI_IMR1_IM22_Msk         (0x1UL << EXTI_IMR1_IM22_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR1_IM22             EXTI_IMR1_IM22_Msk                          /*!< Interrupt Mask on line 22 */

+#define EXTI_IMR1_IM23_Pos         (23U)

+#define EXTI_IMR1_IM23_Msk         (0x1UL << EXTI_IMR1_IM23_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR1_IM23             EXTI_IMR1_IM23_Msk                          /*!< Interrupt Mask on line 23 */

+#define EXTI_IMR1_IM24_Pos         (24U)

+#define EXTI_IMR1_IM24_Msk         (0x1UL << EXTI_IMR1_IM24_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR1_IM24             EXTI_IMR1_IM24_Msk                          /*!< Interrupt Mask on line 24 */

+#define EXTI_IMR1_IM25_Pos         (25U)

+#define EXTI_IMR1_IM25_Msk         (0x1UL << EXTI_IMR1_IM25_Pos)               /*!< 0x02000000 */

+#define EXTI_IMR1_IM25             EXTI_IMR1_IM25_Msk                          /*!< Interrupt Mask on line 25 */

+#define EXTI_IMR1_IM26_Pos         (26U)

+#define EXTI_IMR1_IM26_Msk         (0x1UL << EXTI_IMR1_IM26_Pos)               /*!< 0x04000000 */

+#define EXTI_IMR1_IM26             EXTI_IMR1_IM26_Msk                          /*!< Interrupt Mask on line 26 */

+#define EXTI_IMR1_IM27_Pos         (27U)

+#define EXTI_IMR1_IM27_Msk         (0x1UL << EXTI_IMR1_IM27_Pos)               /*!< 0x08000000 */

+#define EXTI_IMR1_IM27             EXTI_IMR1_IM27_Msk                          /*!< Interrupt Mask on line 27 */

+#define EXTI_IMR1_IM28_Pos         (28U)

+#define EXTI_IMR1_IM28_Msk         (0x1UL << EXTI_IMR1_IM28_Pos)               /*!< 0x10000000 */

+#define EXTI_IMR1_IM28             EXTI_IMR1_IM28_Msk                          /*!< Interrupt Mask on line 28 */

+#define EXTI_IMR1_IM29_Pos         (29U)

+#define EXTI_IMR1_IM29_Msk         (0x1UL << EXTI_IMR1_IM29_Pos)               /*!< 0x20000000 */

+#define EXTI_IMR1_IM29             EXTI_IMR1_IM29_Msk                          /*!< Interrupt Mask on line 29 */

+#define EXTI_IMR1_IM30_Pos         (30U)

+#define EXTI_IMR1_IM30_Msk         (0x1UL << EXTI_IMR1_IM30_Pos)               /*!< 0x40000000 */

+#define EXTI_IMR1_IM30             EXTI_IMR1_IM30_Msk                          /*!< Interrupt Mask on line 30 */

+#define EXTI_IMR1_IM31_Pos         (31U)

+#define EXTI_IMR1_IM31_Msk         (0x1UL << EXTI_IMR1_IM31_Pos)               /*!< 0x80000000 */

+#define EXTI_IMR1_IM31             EXTI_IMR1_IM31_Msk                          /*!< Interrupt Mask on line 31 */

+

+/*******************  Bit definition for EXTI_EMR1 register  *******************/

+#define EXTI_EMR1_EM_Pos           (0U)

+#define EXTI_EMR1_EM_Msk           (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)          /*!< 0xFFFFFFFF */

+#define EXTI_EMR1_EM               EXTI_EMR1_EM_Msk                            /*!< Event Mask */

+#define EXTI_EMR1_EM0_Pos          (0U)

+#define EXTI_EMR1_EM0_Msk          (0x1UL << EXTI_EMR1_EM0_Pos)                /*!< 0x00000001 */

+#define EXTI_EMR1_EM0              EXTI_EMR1_EM0_Msk                           /*!< Event Mask on line 0 */

+#define EXTI_EMR1_EM1_Pos          (1U)

+#define EXTI_EMR1_EM1_Msk          (0x1UL << EXTI_EMR1_EM1_Pos)                /*!< 0x00000002 */

+#define EXTI_EMR1_EM1              EXTI_EMR1_EM1_Msk                           /*!< Event Mask on line 1 */

+#define EXTI_EMR1_EM2_Pos          (2U)

+#define EXTI_EMR1_EM2_Msk          (0x1UL << EXTI_EMR1_EM2_Pos)                /*!< 0x00000004 */

+#define EXTI_EMR1_EM2              EXTI_EMR1_EM2_Msk                           /*!< Event Mask on line 2 */

+#define EXTI_EMR1_EM3_Pos          (3U)

+#define EXTI_EMR1_EM3_Msk          (0x1UL << EXTI_EMR1_EM3_Pos)                /*!< 0x00000008 */

+#define EXTI_EMR1_EM3              EXTI_EMR1_EM3_Msk                           /*!< Event Mask on line 3 */

+#define EXTI_EMR1_EM4_Pos          (4U)

+#define EXTI_EMR1_EM4_Msk          (0x1UL << EXTI_EMR1_EM4_Pos)                /*!< 0x00000010 */

+#define EXTI_EMR1_EM4              EXTI_EMR1_EM4_Msk                           /*!< Event Mask on line 4 */

+#define EXTI_EMR1_EM5_Pos          (5U)

+#define EXTI_EMR1_EM5_Msk          (0x1UL << EXTI_EMR1_EM5_Pos)                /*!< 0x00000020 */

+#define EXTI_EMR1_EM5              EXTI_EMR1_EM5_Msk                           /*!< Event Mask on line 5 */

+#define EXTI_EMR1_EM6_Pos          (6U)

+#define EXTI_EMR1_EM6_Msk          (0x1UL << EXTI_EMR1_EM6_Pos)                /*!< 0x00000040 */

+#define EXTI_EMR1_EM6              EXTI_EMR1_EM6_Msk                           /*!< Event Mask on line 6 */

+#define EXTI_EMR1_EM7_Pos          (7U)

+#define EXTI_EMR1_EM7_Msk          (0x1UL << EXTI_EMR1_EM7_Pos)                /*!< 0x00000080 */

+#define EXTI_EMR1_EM7              EXTI_EMR1_EM7_Msk                           /*!< Event Mask on line 7 */

+#define EXTI_EMR1_EM8_Pos          (8U)

+#define EXTI_EMR1_EM8_Msk          (0x1UL << EXTI_EMR1_EM8_Pos)                /*!< 0x00000100 */

+#define EXTI_EMR1_EM8              EXTI_EMR1_EM8_Msk                           /*!< Event Mask on line 8 */

+#define EXTI_EMR1_EM9_Pos          (9U)

+#define EXTI_EMR1_EM9_Msk          (0x1UL << EXTI_EMR1_EM9_Pos)                /*!< 0x00000200 */

+#define EXTI_EMR1_EM9              EXTI_EMR1_EM9_Msk                           /*!< Event Mask on line 9 */

+#define EXTI_EMR1_EM10_Pos         (10U)

+#define EXTI_EMR1_EM10_Msk         (0x1UL << EXTI_EMR1_EM10_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR1_EM10             EXTI_EMR1_EM10_Msk                          /*!< Event Mask on line 10 */

+#define EXTI_EMR1_EM11_Pos         (11U)

+#define EXTI_EMR1_EM11_Msk         (0x1UL << EXTI_EMR1_EM11_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR1_EM11             EXTI_EMR1_EM11_Msk                          /*!< Event Mask on line 11 */

+#define EXTI_EMR1_EM12_Pos         (12U)

+#define EXTI_EMR1_EM12_Msk         (0x1UL << EXTI_EMR1_EM12_Pos)               /*!< 0x00001000 */

+#define EXTI_EMR1_EM12             EXTI_EMR1_EM12_Msk                          /*!< Event Mask on line 12 */

+#define EXTI_EMR1_EM13_Pos         (13U)

+#define EXTI_EMR1_EM13_Msk         (0x1UL << EXTI_EMR1_EM13_Pos)               /*!< 0x00002000 */

+#define EXTI_EMR1_EM13             EXTI_EMR1_EM13_Msk                          /*!< Event Mask on line 13 */

+#define EXTI_EMR1_EM14_Pos         (14U)

+#define EXTI_EMR1_EM14_Msk         (0x1UL << EXTI_EMR1_EM14_Pos)               /*!< 0x00004000 */

+#define EXTI_EMR1_EM14             EXTI_EMR1_EM14_Msk                          /*!< Event Mask on line 14 */

+#define EXTI_EMR1_EM15_Pos         (15U)

+#define EXTI_EMR1_EM15_Msk         (0x1UL << EXTI_EMR1_EM15_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR1_EM15             EXTI_EMR1_EM15_Msk                          /*!< Event Mask on line 15 */

+#define EXTI_EMR1_EM16_Pos         (16U)

+#define EXTI_EMR1_EM16_Msk         (0x1UL << EXTI_EMR1_EM16_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR1_EM16             EXTI_EMR1_EM16_Msk                          /*!< Event Mask on line 16 */

+#define EXTI_EMR1_EM17_Pos         (17U)

+#define EXTI_EMR1_EM17_Msk         (0x1UL << EXTI_EMR1_EM17_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR1_EM17             EXTI_EMR1_EM17_Msk                          /*!< Event Mask on line 17 */

+#define EXTI_EMR1_EM18_Pos         (18U)

+#define EXTI_EMR1_EM18_Msk         (0x1UL << EXTI_EMR1_EM18_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR1_EM18             EXTI_EMR1_EM18_Msk                          /*!< Event Mask on line 18 */

+#define EXTI_EMR1_EM20_Pos         (20U)

+#define EXTI_EMR1_EM20_Msk         (0x1UL << EXTI_EMR1_EM20_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR1_EM20             EXTI_EMR1_EM20_Msk                          /*!< Event Mask on line 20 */

+#define EXTI_EMR1_EM21_Pos         (21U)

+#define EXTI_EMR1_EM21_Msk         (0x1UL << EXTI_EMR1_EM21_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR1_EM21             EXTI_EMR1_EM21_Msk                          /*!< Event Mask on line 21 */

+#define EXTI_EMR1_EM22_Pos         (22U)

+#define EXTI_EMR1_EM22_Msk         (0x1UL << EXTI_EMR1_EM22_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR1_EM22             EXTI_EMR1_EM22_Msk                          /*!< Event Mask on line 22 */

+#define EXTI_EMR1_EM23_Pos         (23U)

+#define EXTI_EMR1_EM23_Msk         (0x1UL << EXTI_EMR1_EM23_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR1_EM23             EXTI_EMR1_EM23_Msk                          /*!< Event Mask on line 23 */

+#define EXTI_EMR1_EM24_Pos         (24U)

+#define EXTI_EMR1_EM24_Msk         (0x1UL << EXTI_EMR1_EM24_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR1_EM24             EXTI_EMR1_EM24_Msk                          /*!< Event Mask on line 24 */

+#define EXTI_EMR1_EM25_Pos         (25U)

+#define EXTI_EMR1_EM25_Msk         (0x1UL << EXTI_EMR1_EM25_Pos)               /*!< 0x02000000 */

+#define EXTI_EMR1_EM25             EXTI_EMR1_EM25_Msk                          /*!< Event Mask on line 25 */

+#define EXTI_EMR1_EM26_Pos         (26U)

+#define EXTI_EMR1_EM26_Msk         (0x1UL << EXTI_EMR1_EM26_Pos)               /*!< 0x04000000 */

+#define EXTI_EMR1_EM26             EXTI_EMR1_EM26_Msk                          /*!< Event Mask on line 26 */

+#define EXTI_EMR1_EM27_Pos         (27U)

+#define EXTI_EMR1_EM27_Msk         (0x1UL << EXTI_EMR1_EM27_Pos)               /*!< 0x08000000 */

+#define EXTI_EMR1_EM27             EXTI_EMR1_EM27_Msk                          /*!< Event Mask on line 27 */

+#define EXTI_EMR1_EM28_Pos         (28U)

+#define EXTI_EMR1_EM28_Msk         (0x1UL << EXTI_EMR1_EM28_Pos)               /*!< 0x10000000 */

+#define EXTI_EMR1_EM28             EXTI_EMR1_EM28_Msk                          /*!< Event Mask on line 28 */

+#define EXTI_EMR1_EM29_Pos         (29U)

+#define EXTI_EMR1_EM29_Msk         (0x1UL << EXTI_EMR1_EM29_Pos)               /*!< 0x20000000 */

+#define EXTI_EMR1_EM29             EXTI_EMR1_EM29_Msk                          /*!< Event Mask on line 29 */

+#define EXTI_EMR1_EM30_Pos         (30U)

+#define EXTI_EMR1_EM30_Msk         (0x1UL << EXTI_EMR1_EM30_Pos)               /*!< 0x40000000 */

+#define EXTI_EMR1_EM30             EXTI_EMR1_EM30_Msk                          /*!< Event Mask on line 30 */

+#define EXTI_EMR1_EM31_Pos         (31U)

+#define EXTI_EMR1_EM31_Msk         (0x1UL << EXTI_EMR1_EM31_Pos)               /*!< 0x80000000 */

+#define EXTI_EMR1_EM31             EXTI_EMR1_EM31_Msk                          /*!< Event Mask on line 31 */

+

+/*******************  Bit definition for EXTI_PR1 register  ********************/

+#define EXTI_PR1_PR_Pos            (0U)

+#define EXTI_PR1_PR_Msk            (0x3FFFFFUL << EXTI_PR1_PR_Pos)             /*!< 0x003FFFFF */

+#define EXTI_PR1_PR                EXTI_PR1_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR1_PR0_Pos           (0U)

+#define EXTI_PR1_PR0_Msk           (0x1UL << EXTI_PR1_PR0_Pos)                 /*!< 0x00000001 */

+#define EXTI_PR1_PR0               EXTI_PR1_PR0_Msk                            /*!< Pending bit for line 0 */

+#define EXTI_PR1_PR1_Pos           (1U)

+#define EXTI_PR1_PR1_Msk           (0x1UL << EXTI_PR1_PR1_Pos)                 /*!< 0x00000002 */

+#define EXTI_PR1_PR1               EXTI_PR1_PR1_Msk                            /*!< Pending bit for line 1 */

+#define EXTI_PR1_PR2_Pos           (2U)

+#define EXTI_PR1_PR2_Msk           (0x1UL << EXTI_PR1_PR2_Pos)                 /*!< 0x00000004 */

+#define EXTI_PR1_PR2               EXTI_PR1_PR2_Msk                            /*!< Pending bit for line 2 */

+#define EXTI_PR1_PR3_Pos           (3U)

+#define EXTI_PR1_PR3_Msk           (0x1UL << EXTI_PR1_PR3_Pos)                 /*!< 0x00000008 */

+#define EXTI_PR1_PR3               EXTI_PR1_PR3_Msk                            /*!< Pending bit for line 3 */

+#define EXTI_PR1_PR4_Pos           (4U)

+#define EXTI_PR1_PR4_Msk           (0x1UL << EXTI_PR1_PR4_Pos)                 /*!< 0x00000010 */

+#define EXTI_PR1_PR4               EXTI_PR1_PR4_Msk                            /*!< Pending bit for line 4 */

+#define EXTI_PR1_PR5_Pos           (5U)

+#define EXTI_PR1_PR5_Msk           (0x1UL << EXTI_PR1_PR5_Pos)                 /*!< 0x00000020 */

+#define EXTI_PR1_PR5               EXTI_PR1_PR5_Msk                            /*!< Pending bit for line 5 */

+#define EXTI_PR1_PR6_Pos           (6U)

+#define EXTI_PR1_PR6_Msk           (0x1UL << EXTI_PR1_PR6_Pos)                 /*!< 0x00000040 */

+#define EXTI_PR1_PR6               EXTI_PR1_PR6_Msk                            /*!< Pending bit for line 6 */

+#define EXTI_PR1_PR7_Pos           (7U)

+#define EXTI_PR1_PR7_Msk           (0x1UL << EXTI_PR1_PR7_Pos)                 /*!< 0x00000080 */

+#define EXTI_PR1_PR7               EXTI_PR1_PR7_Msk                            /*!< Pending bit for line 7 */

+#define EXTI_PR1_PR8_Pos           (8U)

+#define EXTI_PR1_PR8_Msk           (0x1UL << EXTI_PR1_PR8_Pos)                 /*!< 0x00000100 */

+#define EXTI_PR1_PR8               EXTI_PR1_PR8_Msk                            /*!< Pending bit for line 8 */

+#define EXTI_PR1_PR9_Pos           (9U)

+#define EXTI_PR1_PR9_Msk           (0x1UL << EXTI_PR1_PR9_Pos)                 /*!< 0x00000200 */

+#define EXTI_PR1_PR9               EXTI_PR1_PR9_Msk                            /*!< Pending bit for line 9 */

+#define EXTI_PR1_PR10_Pos          (10U)

+#define EXTI_PR1_PR10_Msk          (0x1UL << EXTI_PR1_PR10_Pos)                /*!< 0x00000400 */

+#define EXTI_PR1_PR10              EXTI_PR1_PR10_Msk                           /*!< Pending bit for line 10 */

+#define EXTI_PR1_PR11_Pos          (11U)

+#define EXTI_PR1_PR11_Msk          (0x1UL << EXTI_PR1_PR11_Pos)                /*!< 0x00000800 */

+#define EXTI_PR1_PR11              EXTI_PR1_PR11_Msk                           /*!< Pending bit for line 11 */

+#define EXTI_PR1_PR12_Pos          (12U)

+#define EXTI_PR1_PR12_Msk          (0x1UL << EXTI_PR1_PR12_Pos)                /*!< 0x00001000 */

+#define EXTI_PR1_PR12              EXTI_PR1_PR12_Msk                           /*!< Pending bit for line 12 */

+#define EXTI_PR1_PR13_Pos          (13U)

+#define EXTI_PR1_PR13_Msk          (0x1UL << EXTI_PR1_PR13_Pos)                /*!< 0x00002000 */

+#define EXTI_PR1_PR13              EXTI_PR1_PR13_Msk                           /*!< Pending bit for line 13 */

+#define EXTI_PR1_PR14_Pos          (14U)

+#define EXTI_PR1_PR14_Msk          (0x1UL << EXTI_PR1_PR14_Pos)                /*!< 0x00004000 */

+#define EXTI_PR1_PR14              EXTI_PR1_PR14_Msk                           /*!< Pending bit for line 14 */

+#define EXTI_PR1_PR15_Pos          (15U)

+#define EXTI_PR1_PR15_Msk          (0x1UL << EXTI_PR1_PR15_Pos)                /*!< 0x00008000 */

+#define EXTI_PR1_PR15              EXTI_PR1_PR15_Msk                           /*!< Pending bit for line 15 */

+#define EXTI_PR1_PR16_Pos          (16U)

+#define EXTI_PR1_PR16_Msk          (0x1UL << EXTI_PR1_PR16_Pos)                /*!< 0x00010000 */

+#define EXTI_PR1_PR16              EXTI_PR1_PR16_Msk                           /*!< Pending bit for line 16 */

+#define EXTI_PR1_PR17_Pos          (17U)

+#define EXTI_PR1_PR17_Msk          (0x1UL << EXTI_PR1_PR17_Pos)                /*!< 0x00020000 */

+#define EXTI_PR1_PR17              EXTI_PR1_PR17_Msk                           /*!< Pending bit for line 17 */

+#define EXTI_PR1_PR18_Pos          (18U)

+#define EXTI_PR1_PR18_Msk          (0x1UL << EXTI_PR1_PR18_Pos)                /*!< 0x00040000 */

+#define EXTI_PR1_PR18              EXTI_PR1_PR18_Msk                           /*!< Pending bit for line 18 */

+#define EXTI_PR1_PR19_Pos          (19U)

+#define EXTI_PR1_PR19_Msk          (0x1UL << EXTI_PR1_PR19_Pos)                /*!< 0x00080000 */

+#define EXTI_PR1_PR19              EXTI_PR1_PR19_Msk                           /*!< Pending bit for line 19 */

+#define EXTI_PR1_PR20_Pos          (20U)

+#define EXTI_PR1_PR20_Msk          (0x1UL << EXTI_PR1_PR20_Pos)                /*!< 0x00100000 */

+#define EXTI_PR1_PR20              EXTI_PR1_PR20_Msk                           /*!< Pending bit for line 20 */

+#define EXTI_PR1_PR21_Pos          (21U)

+#define EXTI_PR1_PR21_Msk          (0x1UL << EXTI_PR1_PR21_Pos)                /*!< 0x00200000 */

+#define EXTI_PR1_PR21              EXTI_PR1_PR21_Msk                           /*!< Pending bit for line 21 */

+

+/*******************  Bit definition for EXTI_IMR2 register  *******************/

+#define EXTI_IMR2_IM_Pos           (0U)

+#define EXTI_IMR2_IM_Msk           (0xFFFFDFFFUL << EXTI_IMR2_IM_Pos)          /*!< 0xFFFFDFFF */

+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            /*!< Interrupt Mask */

+#define EXTI_IMR2_IM32_Pos         (0U)

+#define EXTI_IMR2_IM32_Msk         (0x1UL << EXTI_IMR2_IM32_Pos)               /*!< 0x00000001 */

+#define EXTI_IMR2_IM32             EXTI_IMR2_IM32_Msk                          /*!< Interrupt Mask on line 32 */

+#define EXTI_IMR2_IM33_Pos         (1U)

+#define EXTI_IMR2_IM33_Msk         (0x1UL << EXTI_IMR2_IM33_Pos)               /*!< 0x00000002 */

+#define EXTI_IMR2_IM33             EXTI_IMR2_IM33_Msk                          /*!< Interrupt Mask on line 33 */

+#define EXTI_IMR2_IM34_Pos         (2U)

+#define EXTI_IMR2_IM34_Msk         (0x1UL << EXTI_IMR2_IM34_Pos)               /*!< 0x00000004 */

+#define EXTI_IMR2_IM34             EXTI_IMR2_IM34_Msk                          /*!< Interrupt Mask on line 34 */

+#define EXTI_IMR2_IM35_Pos         (3U)

+#define EXTI_IMR2_IM35_Msk         (0x1UL << EXTI_IMR2_IM35_Pos)               /*!< 0x00000008 */

+#define EXTI_IMR2_IM35             EXTI_IMR2_IM35_Msk                          /*!< Interrupt Mask on line 35 */

+#define EXTI_IMR2_IM36_Pos         (4U)

+#define EXTI_IMR2_IM36_Msk         (0x1UL << EXTI_IMR2_IM36_Pos)               /*!< 0x00000010 */

+#define EXTI_IMR2_IM36             EXTI_IMR2_IM36_Msk                          /*!< Interrupt Mask on line 36 */

+#define EXTI_IMR2_IM37_Pos         (5U)

+#define EXTI_IMR2_IM37_Msk         (0x1UL << EXTI_IMR2_IM37_Pos)               /*!< 0x00000020 */

+#define EXTI_IMR2_IM37             EXTI_IMR2_IM37_Msk                          /*!< Interrupt Mask on line 37 */

+#define EXTI_IMR2_IM38_Pos         (6U)

+#define EXTI_IMR2_IM38_Msk         (0x1UL << EXTI_IMR2_IM38_Pos)               /*!< 0x00000040 */

+#define EXTI_IMR2_IM38             EXTI_IMR2_IM38_Msk                          /*!< Interrupt Mask on line 38 */

+#define EXTI_IMR2_IM39_Pos         (7U)

+#define EXTI_IMR2_IM39_Msk         (0x1UL << EXTI_IMR2_IM39_Pos)               /*!< 0x00000080 */

+#define EXTI_IMR2_IM39             EXTI_IMR2_IM39_Msk                          /*!< Interrupt Mask on line 39 */

+#define EXTI_IMR2_IM40_Pos         (8U)

+#define EXTI_IMR2_IM40_Msk         (0x1UL << EXTI_IMR2_IM40_Pos)               /*!< 0x00000100 */

+#define EXTI_IMR2_IM40             EXTI_IMR2_IM40_Msk                          /*!< Interrupt Mask on line 40 */

+#define EXTI_IMR2_IM41_Pos         (9U)

+#define EXTI_IMR2_IM41_Msk         (0x1UL << EXTI_IMR2_IM41_Pos)               /*!< 0x00000200 */

+#define EXTI_IMR2_IM41             EXTI_IMR2_IM41_Msk                          /*!< Interrupt Mask on line 41 */

+#define EXTI_IMR2_IM42_Pos         (10U)

+#define EXTI_IMR2_IM42_Msk         (0x1UL << EXTI_IMR2_IM42_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR2_IM42             EXTI_IMR2_IM42_Msk                          /*!< Interrupt Mask on line 42 */

+#define EXTI_IMR2_IM43_Pos         (11U)

+#define EXTI_IMR2_IM43_Msk         (0x1UL << EXTI_IMR2_IM43_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR2_IM43             EXTI_IMR2_IM43_Msk                          /*!< Interrupt Mask on line 43 */

+#define EXTI_IMR2_IM44_Pos         (12U)

+#define EXTI_IMR2_IM44_Msk         (0x1UL << EXTI_IMR2_IM44_Pos)               /*!< 0x00001000 */

+#define EXTI_IMR2_IM44             EXTI_IMR2_IM44_Msk                          /*!< Interrupt Mask on line 44 */

+#define EXTI_IMR2_IM46_Pos         (14U)

+#define EXTI_IMR2_IM46_Msk         (0x1UL << EXTI_IMR2_IM46_Pos)               /*!< 0x00004000 */

+#define EXTI_IMR2_IM46             EXTI_IMR2_IM46_Msk                          /*!< Interrupt Mask on line 46 */

+#define EXTI_IMR2_IM47_Pos         (15U)

+#define EXTI_IMR2_IM47_Msk         (0x1UL << EXTI_IMR2_IM47_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR2_IM47             EXTI_IMR2_IM47_Msk                          /*!< Interrupt Mask on line 47 */

+#define EXTI_IMR2_IM48_Pos         (16U)

+#define EXTI_IMR2_IM48_Msk         (0x1UL << EXTI_IMR2_IM48_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR2_IM48             EXTI_IMR2_IM48_Msk                          /*!< Interrupt Mask on line 48 */

+#define EXTI_IMR2_IM49_Pos         (17U)

+#define EXTI_IMR2_IM49_Msk         (0x1UL << EXTI_IMR2_IM49_Pos)               /*!< 0x00020000 */

+#define EXTI_IMR2_IM49             EXTI_IMR2_IM49_Msk                          /*!< Interrupt Mask on line 49 */

+#define EXTI_IMR2_IM50_Pos         (18U)

+#define EXTI_IMR2_IM50_Msk         (0x1UL << EXTI_IMR2_IM50_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR2_IM50             EXTI_IMR2_IM50_Msk                          /*!< Interrupt Mask on line 50 */

+#define EXTI_IMR2_IM51_Pos         (19U)

+#define EXTI_IMR2_IM51_Msk         (0x1UL << EXTI_IMR2_IM51_Pos)               /*!< 0x00080000 */

+#define EXTI_IMR2_IM51             EXTI_IMR2_IM51_Msk                          /*!< Interrupt Mask on line 51 */

+#define EXTI_IMR2_IM52_Pos         (20U)

+#define EXTI_IMR2_IM52_Msk         (0x1UL << EXTI_IMR2_IM52_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR2_IM52             EXTI_IMR2_IM52_Msk                          /*!< Interrupt Mask on line 52 */

+#define EXTI_IMR2_IM53_Pos         (21U)

+#define EXTI_IMR2_IM53_Msk         (0x1UL << EXTI_IMR2_IM53_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR2_IM53             EXTI_IMR2_IM53_Msk                          /*!< Interrupt Mask on line 53 */

+#define EXTI_IMR2_IM54_Pos         (22U)

+#define EXTI_IMR2_IM54_Msk         (0x1UL << EXTI_IMR2_IM54_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR2_IM54             EXTI_IMR2_IM54_Msk                          /*!< Interrupt Mask on line 54 */

+#define EXTI_IMR2_IM55_Pos         (23U)

+#define EXTI_IMR2_IM55_Msk         (0x1UL << EXTI_IMR2_IM55_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR2_IM55             EXTI_IMR2_IM55_Msk                          /*!< Interrupt Mask on line 55 */

+#define EXTI_IMR2_IM56_Pos         (24U)

+#define EXTI_IMR2_IM56_Msk         (0x1UL << EXTI_IMR2_IM56_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR2_IM56             EXTI_IMR2_IM56_Msk                          /*!< Interrupt Mask on line 56 */

+#define EXTI_IMR2_IM57_Pos         (25U)

+#define EXTI_IMR2_IM57_Msk         (0x1UL << EXTI_IMR2_IM57_Pos)               /*!< 0x02000000 */

+#define EXTI_IMR2_IM57             EXTI_IMR2_IM57_Msk                          /*!< Interrupt Mask on line 57 */

+#define EXTI_IMR2_IM58_Pos         (26U)

+#define EXTI_IMR2_IM58_Msk         (0x1UL << EXTI_IMR2_IM58_Pos)               /*!< 0x04000000 */

+#define EXTI_IMR2_IM58             EXTI_IMR2_IM58_Msk                          /*!< Interrupt Mask on line 58 */

+#define EXTI_IMR2_IM59_Pos         (27U)

+#define EXTI_IMR2_IM59_Msk         (0x1UL << EXTI_IMR2_IM59_Pos)               /*!< 0x08000000 */

+#define EXTI_IMR2_IM59             EXTI_IMR2_IM59_Msk                          /*!< Interrupt Mask on line 59 */

+#define EXTI_IMR2_IM60_Pos         (28U)

+#define EXTI_IMR2_IM60_Msk         (0x1UL << EXTI_IMR2_IM60_Pos)               /*!< 0x10000000 */

+#define EXTI_IMR2_IM60             EXTI_IMR2_IM60_Msk                          /*!< Interrupt Mask on line 60 */

+#define EXTI_IMR2_IM61_Pos         (29U)

+#define EXTI_IMR2_IM61_Msk         (0x1UL << EXTI_IMR2_IM61_Pos)               /*!< 0x20000000 */

+#define EXTI_IMR2_IM61             EXTI_IMR2_IM61_Msk                          /*!< Interrupt Mask on line 61 */

+#define EXTI_IMR2_IM62_Pos         (30U)

+#define EXTI_IMR2_IM62_Msk         (0x1UL << EXTI_IMR2_IM62_Pos)               /*!< 0x40000000 */

+#define EXTI_IMR2_IM62             EXTI_IMR2_IM62_Msk                          /*!< Interrupt Mask on line 62 */

+#define EXTI_IMR2_IM63_Pos         (31U)

+#define EXTI_IMR2_IM63_Msk         (0x1UL << EXTI_IMR2_IM63_Pos)               /*!< 0x80000000 */

+#define EXTI_IMR2_IM63             EXTI_IMR2_IM63_Msk                          /*!< Interrupt Mask on line 63 */

+

+/*******************  Bit definition for EXTI_EMR2 register  *******************/

+#define EXTI_EMR2_EM_Pos           (0U)

+#define EXTI_EMR2_EM_Msk           (0xFFFFDFFFUL << EXTI_EMR2_EM_Pos)          /*!< 0xFFFFDFFF */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            /*!< Event Mask */

+#define EXTI_EMR2_EM32_Pos         (0U)

+#define EXTI_EMR2_EM32_Msk         (0x1UL << EXTI_EMR2_EM32_Pos)               /*!< 0x00000001 */

+#define EXTI_EMR2_EM32             EXTI_EMR2_EM32_Msk                          /*!< Event Mask on line 32*/

+#define EXTI_EMR2_EM33_Pos         (1U)

+#define EXTI_EMR2_EM33_Msk         (0x1UL << EXTI_EMR2_EM33_Pos)               /*!< 0x00000002 */

+#define EXTI_EMR2_EM33             EXTI_EMR2_EM33_Msk                          /*!< Event Mask on line 33*/

+#define EXTI_EMR2_EM34_Pos         (2U)

+#define EXTI_EMR2_EM34_Msk         (0x1UL << EXTI_EMR2_EM34_Pos)               /*!< 0x00000004 */

+#define EXTI_EMR2_EM34             EXTI_EMR2_EM34_Msk                          /*!< Event Mask on line 34*/

+#define EXTI_EMR2_EM35_Pos         (3U)

+#define EXTI_EMR2_EM35_Msk         (0x1UL << EXTI_EMR2_EM35_Pos)               /*!< 0x00000008 */

+#define EXTI_EMR2_EM35             EXTI_EMR2_EM35_Msk                          /*!< Event Mask on line 35*/

+#define EXTI_EMR2_EM36_Pos         (4U)

+#define EXTI_EMR2_EM36_Msk         (0x1UL << EXTI_EMR2_EM36_Pos)               /*!< 0x00000010 */

+#define EXTI_EMR2_EM36             EXTI_EMR2_EM36_Msk                          /*!< Event Mask on line 36*/

+#define EXTI_EMR2_EM37_Pos         (5U)

+#define EXTI_EMR2_EM37_Msk         (0x1UL << EXTI_EMR2_EM37_Pos)               /*!< 0x00000020 */

+#define EXTI_EMR2_EM37             EXTI_EMR2_EM37_Msk                          /*!< Event Mask on line 37*/

+#define EXTI_EMR2_EM38_Pos         (6U)

+#define EXTI_EMR2_EM38_Msk         (0x1UL << EXTI_EMR2_EM38_Pos)               /*!< 0x00000040 */

+#define EXTI_EMR2_EM38             EXTI_EMR2_EM38_Msk                          /*!< Event Mask on line 38*/

+#define EXTI_EMR2_EM39_Pos         (7U)

+#define EXTI_EMR2_EM39_Msk         (0x1UL << EXTI_EMR2_EM39_Pos)               /*!< 0x00000080 */

+#define EXTI_EMR2_EM39             EXTI_EMR2_EM39_Msk                          /*!< Event Mask on line 39*/

+#define EXTI_EMR2_EM40_Pos         (8U)

+#define EXTI_EMR2_EM40_Msk         (0x1UL << EXTI_EMR2_EM40_Pos)               /*!< 0x00000100 */

+#define EXTI_EMR2_EM40             EXTI_EMR2_EM40_Msk                          /*!< Event Mask on line 40*/

+#define EXTI_EMR2_EM41_Pos         (9U)

+#define EXTI_EMR2_EM41_Msk         (0x1UL << EXTI_EMR2_EM41_Pos)               /*!< 0x00000200 */

+#define EXTI_EMR2_EM41             EXTI_EMR2_EM41_Msk                          /*!< Event Mask on line 41*/

+#define EXTI_EMR2_EM42_Pos         (10U)

+#define EXTI_EMR2_EM42_Msk         (0x1UL << EXTI_EMR2_EM42_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR2_EM42             EXTI_EMR2_EM42_Msk                          /*!< Event Mask on line 42 */

+#define EXTI_EMR2_EM43_Pos         (11U)

+#define EXTI_EMR2_EM43_Msk         (0x1UL << EXTI_EMR2_EM43_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR2_EM43             EXTI_EMR2_EM43_Msk                          /*!< Event Mask on line 43 */

+#define EXTI_EMR2_EM44_Pos         (12U)

+#define EXTI_EMR2_EM44_Msk         (0x1UL << EXTI_EMR2_EM44_Pos)               /*!< 0x00001000 */

+#define EXTI_EMR2_EM44             EXTI_EMR2_EM44_Msk                          /*!< Event Mask on line 44 */

+#define EXTI_EMR2_EM46_Pos         (14U)

+#define EXTI_EMR2_EM46_Msk         (0x1UL << EXTI_EMR2_EM46_Pos)               /*!< 0x00004000 */

+#define EXTI_EMR2_EM46             EXTI_EMR2_EM46_Msk                          /*!< Event Mask on line 46 */

+#define EXTI_EMR2_EM47_Pos         (15U)

+#define EXTI_EMR2_EM47_Msk         (0x1UL << EXTI_EMR2_EM47_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR2_EM47             EXTI_EMR2_EM47_Msk                          /*!< Event Mask on line 47 */

+#define EXTI_EMR2_EM48_Pos         (16U)

+#define EXTI_EMR2_EM48_Msk         (0x1UL << EXTI_EMR2_EM48_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR2_EM48             EXTI_EMR2_EM48_Msk                          /*!< Event Mask on line 48 */

+#define EXTI_EMR2_EM49_Pos         (17U)

+#define EXTI_EMR2_EM49_Msk         (0x1UL << EXTI_EMR2_EM49_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR2_EM49             EXTI_EMR2_EM49_Msk                          /*!< Event Mask on line 49 */

+#define EXTI_EMR2_EM50_Pos         (18U)

+#define EXTI_EMR2_EM50_Msk         (0x1UL << EXTI_EMR2_EM50_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR2_EM50             EXTI_EMR2_EM50_Msk                          /*!< Event Mask on line 50 */

+#define EXTI_EMR2_EM51_Pos         (19U)

+#define EXTI_EMR2_EM51_Msk         (0x1UL << EXTI_EMR2_EM51_Pos)               /*!< 0x00080000 */

+#define EXTI_EMR2_EM51             EXTI_EMR2_EM51_Msk                          /*!< Event Mask on line 51 */

+#define EXTI_EMR2_EM52_Pos         (20U)

+#define EXTI_EMR2_EM52_Msk         (0x1UL << EXTI_EMR2_EM52_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR2_EM52             EXTI_EMR2_EM52_Msk                          /*!< Event Mask on line 52 */

+#define EXTI_EMR2_EM53_Pos         (21U)

+#define EXTI_EMR2_EM53_Msk         (0x1UL << EXTI_EMR2_EM53_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR2_EM53             EXTI_EMR2_EM53_Msk                          /*!< Event Mask on line 53 */

+#define EXTI_EMR2_EM54_Pos         (22U)

+#define EXTI_EMR2_EM54_Msk         (0x1UL << EXTI_EMR2_EM54_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR2_EM54             EXTI_EMR2_EM54_Msk                          /*!< Event Mask on line 54 */

+#define EXTI_EMR2_EM55_Pos         (23U)

+#define EXTI_EMR2_EM55_Msk         (0x1UL << EXTI_EMR2_EM55_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR2_EM55             EXTI_EMR2_EM55_Msk                          /*!< Event Mask on line 55 */

+#define EXTI_EMR2_EM56_Pos         (24U)

+#define EXTI_EMR2_EM56_Msk         (0x1UL << EXTI_EMR2_EM56_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR2_EM56             EXTI_EMR2_EM56_Msk                          /*!< Event Mask on line 56 */

+#define EXTI_EMR2_EM57_Pos         (25U)

+#define EXTI_EMR2_EM57_Msk         (0x1UL << EXTI_EMR2_EM57_Pos)               /*!< 0x02000000 */

+#define EXTI_EMR2_EM57             EXTI_EMR2_EM57_Msk                          /*!< Event Mask on line 57 */

+#define EXTI_EMR2_EM58_Pos         (26U)

+#define EXTI_EMR2_EM58_Msk         (0x1UL << EXTI_EMR2_EM58_Pos)               /*!< 0x04000000 */

+#define EXTI_EMR2_EM58             EXTI_EMR2_EM58_Msk                          /*!< Event Mask on line 58 */

+#define EXTI_EMR2_EM59_Pos         (27U)

+#define EXTI_EMR2_EM59_Msk         (0x1UL << EXTI_EMR2_EM59_Pos)               /*!< 0x08000000 */

+#define EXTI_EMR2_EM59             EXTI_EMR2_EM59_Msk                          /*!< Event Mask on line 59 */

+#define EXTI_EMR2_EM60_Pos         (28U)

+#define EXTI_EMR2_EM60_Msk         (0x1UL << EXTI_EMR2_EM60_Pos)               /*!< 0x10000000 */

+#define EXTI_EMR2_EM60             EXTI_EMR2_EM60_Msk                          /*!< Event Mask on line 60 */

+#define EXTI_EMR2_EM61_Pos         (29U)

+#define EXTI_EMR2_EM61_Msk         (0x1UL << EXTI_EMR2_EM61_Pos)               /*!< 0x20000000 */

+#define EXTI_EMR2_EM61             EXTI_EMR2_EM61_Msk                          /*!< Event Mask on line 61 */

+#define EXTI_EMR2_EM62_Pos         (30U)

+#define EXTI_EMR2_EM62_Msk         (0x1UL << EXTI_EMR2_EM62_Pos)               /*!< 0x40000000 */

+#define EXTI_EMR2_EM62             EXTI_EMR2_EM62_Msk                          /*!< Event Mask on line 62 */

+#define EXTI_EMR2_EM63_Pos         (31U)

+#define EXTI_EMR2_EM63_Msk         (0x1UL << EXTI_EMR2_EM63_Pos)               /*!< 0x80000000 */

+#define EXTI_EMR2_EM63             EXTI_EMR2_EM63_Msk                          /*!< Event Mask on line 63 */

+

+/*******************  Bit definition for EXTI_PR2 register  ********************/

+#define EXTI_PR2_PR_Pos            (17U)

+#define EXTI_PR2_PR_Msk            (0x5UL << EXTI_PR2_PR_Pos)                  /*!< 0x000A0000 */

+#define EXTI_PR2_PR                EXTI_PR2_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR2_PR49_Pos          (17U)

+#define EXTI_PR2_PR49_Msk          (0x1UL << EXTI_PR2_PR49_Pos)                /*!< 0x00020000 */

+#define EXTI_PR2_PR49              EXTI_PR2_PR49_Msk                           /*!< Pending bit for line 49 */

+#define EXTI_PR2_PR51_Pos          (19U)

+#define EXTI_PR2_PR51_Msk          (0x1UL << EXTI_PR2_PR51_Pos)                /*!< 0x00080000 */

+#define EXTI_PR2_PR51              EXTI_PR2_PR51_Msk                           /*!< Pending bit for line 51 */

+

+/*******************  Bit definition for EXTI_IMR3 register  *******************/

+#define EXTI_IMR3_IM_Pos           (0U)

+#define EXTI_IMR3_IM_Msk           (0x00F5FFFFUL << EXTI_IMR3_IM_Pos)          /*!< 0x00F5FFFF */

+#define EXTI_IMR3_IM               EXTI_IMR3_IM_Msk                            /*!< Interrupt Mask */

+#define EXTI_IMR3_IM64_Pos         (0U)

+#define EXTI_IMR3_IM64_Msk         (0x1UL << EXTI_IMR3_IM64_Pos)               /*!< 0x00000001 */

+#define EXTI_IMR3_IM64             EXTI_IMR3_IM64_Msk                          /*!< Interrupt Mask on line 64 */

+#define EXTI_IMR3_IM65_Pos         (1U)

+#define EXTI_IMR3_IM65_Msk         (0x1UL << EXTI_IMR3_IM65_Pos)               /*!< 0x00000002 */

+#define EXTI_IMR3_IM65             EXTI_IMR3_IM65_Msk                          /*!< Interrupt Mask on line 65 */

+#define EXTI_IMR3_IM66_Pos         (2U)

+#define EXTI_IMR3_IM66_Msk         (0x1UL << EXTI_IMR3_IM66_Pos)               /*!< 0x00000004 */

+#define EXTI_IMR3_IM66             EXTI_IMR3_IM66_Msk                          /*!< Interrupt Mask on line 66 */

+#define EXTI_IMR3_IM67_Pos         (3U)

+#define EXTI_IMR3_IM67_Msk         (0x1UL << EXTI_IMR3_IM67_Pos)               /*!< 0x00000008 */

+#define EXTI_IMR3_IM67             EXTI_IMR3_IM67_Msk                          /*!< Interrupt Mask on line 67 */

+#define EXTI_IMR3_IM68_Pos         (4U)

+#define EXTI_IMR3_IM68_Msk         (0x1UL << EXTI_IMR3_IM68_Pos)               /*!< 0x00000010 */

+#define EXTI_IMR3_IM68             EXTI_IMR3_IM68_Msk                          /*!< Interrupt Mask on line 68 */

+#define EXTI_IMR3_IM69_Pos         (5U)

+#define EXTI_IMR3_IM69_Msk         (0x1UL << EXTI_IMR3_IM69_Pos)               /*!< 0x00000020 */

+#define EXTI_IMR3_IM69             EXTI_IMR3_IM69_Msk                          /*!< Interrupt Mask on line 69 */

+#define EXTI_IMR3_IM70_Pos         (6U)

+#define EXTI_IMR3_IM70_Msk         (0x1UL << EXTI_IMR3_IM70_Pos)               /*!< 0x00000040 */

+#define EXTI_IMR3_IM70             EXTI_IMR3_IM70_Msk                          /*!< Interrupt Mask on line 70 */

+#define EXTI_IMR3_IM71_Pos         (7U)

+#define EXTI_IMR3_IM71_Msk         (0x1UL << EXTI_IMR3_IM71_Pos)               /*!< 0x00000080 */

+#define EXTI_IMR3_IM71             EXTI_IMR3_IM71_Msk                          /*!< Interrupt Mask on line 71 */

+#define EXTI_IMR3_IM72_Pos         (8U)

+#define EXTI_IMR3_IM72_Msk         (0x1UL << EXTI_IMR3_IM72_Pos)               /*!< 0x00000100 */

+#define EXTI_IMR3_IM72             EXTI_IMR3_IM72_Msk                          /*!< Interrupt Mask on line 72 */

+#define EXTI_IMR3_IM73_Pos         (9U)

+#define EXTI_IMR3_IM73_Msk         (0x1UL << EXTI_IMR3_IM73_Pos)               /*!< 0x00000200 */

+#define EXTI_IMR3_IM73             EXTI_IMR3_IM73_Msk                          /*!< Interrupt Mask on line 73 */

+#define EXTI_IMR3_IM74_Pos         (10U)

+#define EXTI_IMR3_IM74_Msk         (0x1UL << EXTI_IMR3_IM74_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR3_IM74             EXTI_IMR3_IM74_Msk                          /*!< Interrupt Mask on line 74 */

+#define EXTI_IMR3_IM75_Pos         (11U)

+#define EXTI_IMR3_IM75_Msk         (0x1UL << EXTI_IMR3_IM75_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR3_IM75             EXTI_IMR3_IM75_Msk                          /*!< Interrupt Mask on line 75 */

+#define EXTI_IMR3_IM76_Pos         (12U)

+#define EXTI_IMR3_IM76_Msk         (0x1UL << EXTI_IMR3_IM76_Pos)               /*!< 0x00001000 */

+#define EXTI_IMR3_IM76             EXTI_IMR3_IM76_Msk                          /*!< Interrupt Mask on line 76 */

+#define EXTI_IMR3_IM77_Pos         (13U)

+#define EXTI_IMR3_IM77_Msk         (0x1UL << EXTI_IMR3_IM77_Pos)               /*!< 0x00002000 */

+#define EXTI_IMR3_IM77             EXTI_IMR3_IM77_Msk                          /*!< Interrupt Mask on line 77 */

+#define EXTI_IMR3_IM78_Pos         (14U)

+#define EXTI_IMR3_IM78_Msk         (0x1UL << EXTI_IMR3_IM78_Pos)               /*!< 0x00004000 */

+#define EXTI_IMR3_IM78             EXTI_IMR3_IM78_Msk                          /*!< Interrupt Mask on line 78 */

+#define EXTI_IMR3_IM79_Pos         (15U)

+#define EXTI_IMR3_IM79_Msk         (0x1UL << EXTI_IMR3_IM79_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR3_IM79             EXTI_IMR3_IM79_Msk                          /*!< Interrupt Mask on line 79 */

+#define EXTI_IMR3_IM80_Pos         (16U)

+#define EXTI_IMR3_IM80_Msk         (0x1UL << EXTI_IMR3_IM80_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR3_IM80             EXTI_IMR3_IM80_Msk                          /*!< Interrupt Mask on line 80 */

+#define EXTI_IMR3_IM82_Pos         (18U)

+#define EXTI_IMR3_IM82_Msk         (0x1UL << EXTI_IMR3_IM82_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR3_IM82             EXTI_IMR3_IM82_Msk                          /*!< Interrupt Mask on line 82 */

+#define EXTI_IMR3_IM84_Pos         (20U)

+#define EXTI_IMR3_IM84_Msk         (0x1UL << EXTI_IMR3_IM84_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR3_IM84             EXTI_IMR3_IM84_Msk                          /*!< Interrupt Mask on line 84 */

+#define EXTI_IMR3_IM85_Pos         (21U)

+#define EXTI_IMR3_IM85_Msk         (0x1UL << EXTI_IMR3_IM85_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR3_IM85             EXTI_IMR3_IM85_Msk                          /*!< Interrupt Mask on line 85 */

+#define EXTI_IMR3_IM86_Pos         (22U)

+#define EXTI_IMR3_IM86_Msk         (0x1UL << EXTI_IMR3_IM86_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR3_IM86             EXTI_IMR3_IM86_Msk                          /*!< Interrupt Mask on line 86 */

+#define EXTI_IMR3_IM87_Pos         (23U)

+#define EXTI_IMR3_IM87_Msk         (0x1UL << EXTI_IMR3_IM87_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR3_IM87             EXTI_IMR3_IM87_Msk                          /*!< Interrupt Mask on line 87 */

+

+

+/*******************  Bit definition for EXTI_EMR3 register  *******************/

+#define EXTI_EMR3_EM_Pos           (0U)

+#define EXTI_EMR3_EM_Msk           (0x00F5FFFFUL << EXTI_EMR3_EM_Pos)          /*!< 0x00F5FFFF */

+#define EXTI_EMR3_EM               EXTI_EMR3_EM_Msk                            /*!< Event Mask           */

+#define EXTI_EMR3_EM64_Pos         (0U)

+#define EXTI_EMR3_EM64_Msk         (0x1UL << EXTI_EMR3_EM64_Pos)               /*!< 0x00000001 */

+#define EXTI_EMR3_EM64             EXTI_EMR3_EM64_Msk                          /*!< Event Mask on line 64*/

+#define EXTI_EMR3_EM65_Pos         (1U)

+#define EXTI_EMR3_EM65_Msk         (0x1UL << EXTI_EMR3_EM65_Pos)               /*!< 0x00000002 */

+#define EXTI_EMR3_EM65             EXTI_EMR3_EM65_Msk                          /*!< Event Mask on line 65*/

+#define EXTI_EMR3_EM66_Pos         (2U)

+#define EXTI_EMR3_EM66_Msk         (0x1UL << EXTI_EMR3_EM66_Pos)               /*!< 0x00000004 */

+#define EXTI_EMR3_EM66             EXTI_EMR3_EM66_Msk                          /*!< Event Mask on line 66*/

+#define EXTI_EMR3_EM67_Pos         (3U)

+#define EXTI_EMR3_EM67_Msk         (0x1UL << EXTI_EMR3_EM67_Pos)               /*!< 0x00000008 */

+#define EXTI_EMR3_EM67             EXTI_EMR3_EM67_Msk                          /*!< Event Mask on line 67*/

+#define EXTI_EMR3_EM68_Pos         (4U)

+#define EXTI_EMR3_EM68_Msk         (0x1UL << EXTI_EMR3_EM68_Pos)               /*!< 0x00000010 */

+#define EXTI_EMR3_EM68             EXTI_EMR3_EM68_Msk                          /*!< Event Mask on line 68*/

+#define EXTI_EMR3_EM69_Pos         (5U)

+#define EXTI_EMR3_EM69_Msk         (0x1UL << EXTI_EMR3_EM69_Pos)               /*!< 0x00000020 */

+#define EXTI_EMR3_EM69             EXTI_EMR3_EM69_Msk                          /*!< Event Mask on line 69*/

+#define EXTI_EMR3_EM70_Pos         (6U)

+#define EXTI_EMR3_EM70_Msk         (0x1UL << EXTI_EMR3_EM70_Pos)               /*!< 0x00000040 */

+#define EXTI_EMR3_EM70             EXTI_EMR3_EM70_Msk                          /*!< Event Mask on line 70*/

+#define EXTI_EMR3_EM71_Pos         (7U)

+#define EXTI_EMR3_EM71_Msk         (0x1UL << EXTI_EMR3_EM71_Pos)               /*!< 0x00000080 */

+#define EXTI_EMR3_EM71             EXTI_EMR3_EM71_Msk                          /*!< Event Mask on line 71*/

+#define EXTI_EMR3_EM72_Pos         (8U)

+#define EXTI_EMR3_EM72_Msk         (0x1UL << EXTI_EMR3_EM72_Pos)               /*!< 0x00000100 */

+#define EXTI_EMR3_EM72             EXTI_EMR3_EM72_Msk                          /*!< Event Mask on line 72*/

+#define EXTI_EMR3_EM73_Pos         (9U)

+#define EXTI_EMR3_EM73_Msk         (0x1UL << EXTI_EMR3_EM73_Pos)               /*!< 0x00000200 */

+#define EXTI_EMR3_EM73             EXTI_EMR3_EM73_Msk                          /*!< Event Mask on line 73*/

+#define EXTI_EMR3_EM74_Pos         (10U)

+#define EXTI_EMR3_EM74_Msk         (0x1UL << EXTI_EMR3_EM74_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR3_EM74             EXTI_EMR3_EM74_Msk                          /*!< Event Mask on line 74 */

+#define EXTI_EMR3_EM75_Pos         (11U)

+#define EXTI_EMR3_EM75_Msk         (0x1UL << EXTI_EMR3_EM75_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR3_EM75             EXTI_EMR3_EM75_Msk                          /*!< Event Mask on line 75 */

+#define EXTI_EMR3_EM76_Pos         (12U)

+#define EXTI_EMR3_EM76_Msk         (0x1UL << EXTI_EMR3_EM76_Pos)               /*!< 0x00001000 */

+#define EXTI_EMR3_EM76             EXTI_EMR3_EM76_Msk                          /*!< Event Mask on line 76 */

+#define EXTI_EMR3_EM77_Pos         (13U)

+#define EXTI_EMR3_EM77_Msk         (0x1UL << EXTI_EMR3_EM77_Pos)               /*!< 0x00002000 */

+#define EXTI_EMR3_EM77             EXTI_EMR3_EM77_Msk                          /*!< Event Mask on line 77 */

+#define EXTI_EMR3_EM78_Pos         (14U)

+#define EXTI_EMR3_EM78_Msk         (0x1UL << EXTI_EMR3_EM78_Pos)               /*!< 0x00004000 */

+#define EXTI_EMR3_EM78             EXTI_EMR3_EM78_Msk                          /*!< Event Mask on line 78 */

+#define EXTI_EMR3_EM79_Pos         (15U)

+#define EXTI_EMR3_EM79_Msk         (0x1UL << EXTI_EMR3_EM79_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR3_EM79             EXTI_EMR3_EM79_Msk                          /*!< Event Mask on line 79 */

+#define EXTI_EMR3_EM80_Pos         (16U)

+#define EXTI_EMR3_EM80_Msk         (0x1UL << EXTI_EMR3_EM80_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR3_EM80             EXTI_EMR3_EM80_Msk                          /*!< Event Mask on line 80 */

+#define EXTI_EMR3_EM81_Pos         (17U)

+#define EXTI_EMR3_EM81_Msk         (0x1UL << EXTI_EMR3_EM81_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR3_EM81             EXTI_EMR3_EM81_Msk                          /*!< Event Mask on line 81 */

+#define EXTI_EMR3_EM82_Pos         (18U)

+#define EXTI_EMR3_EM82_Msk         (0x1UL << EXTI_EMR3_EM82_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR3_EM82             EXTI_EMR3_EM82_Msk                          /*!< Event Mask on line 82 */

+#define EXTI_EMR3_EM84_Pos         (20U)

+#define EXTI_EMR3_EM84_Msk         (0x1UL << EXTI_EMR3_EM84_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR3_EM84             EXTI_EMR3_EM84_Msk                          /*!< Event Mask on line 84 */

+#define EXTI_EMR3_EM85_Pos         (21U)

+#define EXTI_EMR3_EM85_Msk         (0x1UL << EXTI_EMR3_EM85_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR3_EM85             EXTI_EMR3_EM85_Msk                          /*!< Event Mask on line 85 */

+#define EXTI_EMR3_EM86_Pos         (22U)

+#define EXTI_EMR3_EM86_Msk         (0x1UL << EXTI_EMR3_EM86_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR3_EM86             EXTI_EMR3_EM86_Msk                          /*!< Event Mask on line 86 */

+#define EXTI_EMR3_EM87_Pos         (23U)

+#define EXTI_EMR3_EM87_Msk         (0x1UL << EXTI_EMR3_EM87_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR3_EM87             EXTI_EMR3_EM87_Msk                          /*!< Event Mask on line 87 */

+

+/*******************  Bit definition for EXTI_PR3 register  ********************/

+#define EXTI_PR3_PR_Pos            (18U)

+#define EXTI_PR3_PR_Msk            (0x1DUL << EXTI_PR3_PR_Pos)                 /*!< 0x00740000 */

+#define EXTI_PR3_PR                EXTI_PR3_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR3_PR82_Pos          (18U)

+#define EXTI_PR3_PR82_Msk          (0x1UL << EXTI_PR3_PR82_Pos)                /*!< 0x00040000 */

+#define EXTI_PR3_PR82              EXTI_PR3_PR82_Msk                           /*!< Pending bit for line 82 */

+#define EXTI_PR3_PR84_Pos          (20U)

+#define EXTI_PR3_PR84_Msk          (0x1UL << EXTI_PR3_PR84_Pos)                /*!< 0x00100000 */

+#define EXTI_PR3_PR84              EXTI_PR3_PR84_Msk                           /*!< Pending bit for line 84 */

+#define EXTI_PR3_PR85_Pos          (21U)

+#define EXTI_PR3_PR85_Msk          (0x1UL << EXTI_PR3_PR85_Pos)                /*!< 0x00200000 */

+#define EXTI_PR3_PR85              EXTI_PR3_PR85_Msk                           /*!< Pending bit for line 85 */

+#define EXTI_PR3_PR86_Pos          (22U)

+#define EXTI_PR3_PR86_Msk          (0x1UL << EXTI_PR3_PR86_Pos)                /*!< 0x00400000 */

+#define EXTI_PR3_PR86              EXTI_PR3_PR86_Msk                           /*!< Pending bit for line 86 */

+/******************************************************************************/

+/*                                                                            */

+/*                                    FLASH                                   */

+/*                                                                            */

+/******************************************************************************/

+/*

+* @brief FLASH Global Defines

+*/

+#define FLASH_SECTOR_TOTAL                   8U                    /* 8 sectors */

+#define FLASH_SIZE                           0x200000UL            /* 2 MB   */

+#define FLASH_BANK_SIZE                      (FLASH_SIZE >> 1)     /* 1 MB   */

+#define FLASH_SECTOR_SIZE                    0x00020000UL          /* 128 KB */

+#define FLASH_LATENCY_DEFAULT                FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */

+#define FLASH_NB_32BITWORD_IN_FLASHWORD      8U                    /* 256 bits */

+#define DUAL_BANK                                                  /* Dual-bank Flash */

+

+/*******************  Bits definition for FLASH_ACR register  **********************/

+#define FLASH_ACR_LATENCY_Pos                (0U)

+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */

+#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */

+#define FLASH_ACR_LATENCY_0WS                (0x00000000UL)

+#define FLASH_ACR_LATENCY_1WS                (0x00000001UL)

+#define FLASH_ACR_LATENCY_2WS                (0x00000002UL)

+#define FLASH_ACR_LATENCY_3WS                (0x00000003UL)

+#define FLASH_ACR_LATENCY_4WS                (0x00000004UL)

+#define FLASH_ACR_LATENCY_5WS                (0x00000005UL)

+#define FLASH_ACR_LATENCY_6WS                (0x00000006UL)

+#define FLASH_ACR_LATENCY_7WS                (0x00000007UL)

+#define FLASH_ACR_LATENCY_8WS                (0x00000008UL)

+#define FLASH_ACR_LATENCY_9WS                (0x00000009UL)

+#define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)

+#define FLASH_ACR_LATENCY_11WS               (0x0000000BUL)

+#define FLASH_ACR_LATENCY_12WS               (0x0000000CUL)

+#define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)

+#define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)

+#define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)

+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)

+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */

+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */

+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */

+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */

+

+/*******************  Bits definition for FLASH_CR register  ***********************/

+#define FLASH_CR_LOCK_Pos                    (0U)

+#define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */

+#define FLASH_CR_LOCK                        FLASH_CR_LOCK_Msk                 /*!< Configuration lock bit */

+#define FLASH_CR_PG_Pos                      (1U)

+#define FLASH_CR_PG_Msk                      (0x1UL << FLASH_CR_PG_Pos)        /*!< 0x00000002 */

+#define FLASH_CR_PG                          FLASH_CR_PG_Msk                   /*!< Internal buffer control bit */

+#define FLASH_CR_SER_Pos                     (2U)

+#define FLASH_CR_SER_Msk                     (0x1UL << FLASH_CR_SER_Pos)       /*!< 0x00000004 */

+#define FLASH_CR_SER                         FLASH_CR_SER_Msk                  /*!< Sector erase request */

+#define FLASH_CR_BER_Pos                     (3U)

+#define FLASH_CR_BER_Msk                     (0x1UL << FLASH_CR_BER_Pos)       /*!< 0x00000008 */

+#define FLASH_CR_BER                         FLASH_CR_BER_Msk                  /*!< Bank erase request */

+#define FLASH_CR_PSIZE_Pos                   (4U)

+#define FLASH_CR_PSIZE_Msk                   (0x3UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000030 */

+#define FLASH_CR_PSIZE                       FLASH_CR_PSIZE_Msk                /*!< Program size */

+#define FLASH_CR_PSIZE_0                     (0x1UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000010 */

+#define FLASH_CR_PSIZE_1                     (0x2UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000020 */

+#define FLASH_CR_FW_Pos                      (6U)

+#define FLASH_CR_FW_Msk                      (0x1UL << FLASH_CR_FW_Pos)        /*!< 0x00000040 */

+#define FLASH_CR_FW                          FLASH_CR_FW_Msk                   /*!< Write forcing control bit */

+#define FLASH_CR_START_Pos                   (7U)

+#define FLASH_CR_START_Msk                   (0x1UL << FLASH_CR_START_Pos)     /*!< 0x00000080 */

+#define FLASH_CR_START                       FLASH_CR_START_Msk                /*!< Erase start control bit */

+#define FLASH_CR_SNB_Pos                     (8U)

+#define FLASH_CR_SNB_Msk                     (0x7UL << FLASH_CR_SNB_Pos)       /*!< 0x00000700 */

+#define FLASH_CR_SNB                         FLASH_CR_SNB_Msk                  /*!< Sector erase selection number */

+#define FLASH_CR_SNB_0                       (0x1UL << FLASH_CR_SNB_Pos)       /*!< 0x00000100 */

+#define FLASH_CR_SNB_1                       (0x2UL << FLASH_CR_SNB_Pos)       /*!< 0x00000200 */

+#define FLASH_CR_SNB_2                       (0x4UL << FLASH_CR_SNB_Pos)       /*!< 0x00000400 */

+#define FLASH_CR_CRC_EN_Pos                  (15U)

+#define FLASH_CR_CRC_EN_Msk                  (0x1UL << FLASH_CR_CRC_EN_Pos)    /*!< 0x00008000 */

+#define FLASH_CR_CRC_EN                      FLASH_CR_CRC_EN_Msk               /*!< CRC control bit */

+#define FLASH_CR_EOPIE_Pos                   (16U)

+#define FLASH_CR_EOPIE_Msk                   (0x1UL << FLASH_CR_EOPIE_Pos)     /*!< 0x00010000 */

+#define FLASH_CR_EOPIE                       FLASH_CR_EOPIE_Msk                /*!< End-of-program interrupt control bit */

+#define FLASH_CR_WRPERRIE_Pos                (17U)

+#define FLASH_CR_WRPERRIE_Msk                (0x1UL << FLASH_CR_WRPERRIE_Pos)  /*!< 0x00020000 */

+#define FLASH_CR_WRPERRIE                    FLASH_CR_WRPERRIE_Msk             /*!< Write protection error interrupt enable bit */

+#define FLASH_CR_PGSERRIE_Pos                (18U)

+#define FLASH_CR_PGSERRIE_Msk                (0x1UL << FLASH_CR_PGSERRIE_Pos)  /*!< 0x00040000 */

+#define FLASH_CR_PGSERRIE                    FLASH_CR_PGSERRIE_Msk             /*!< Programming sequence error interrupt enable bit */

+#define FLASH_CR_STRBERRIE_Pos               (19U)

+#define FLASH_CR_STRBERRIE_Msk               (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */

+#define FLASH_CR_STRBERRIE                   FLASH_CR_STRBERRIE_Msk            /*!< Strobe error interrupt enable bit */

+#define FLASH_CR_INCERRIE_Pos                (21U)

+#define FLASH_CR_INCERRIE_Msk                (0x1UL << FLASH_CR_INCERRIE_Pos)  /*!< 0x00200000 */

+#define FLASH_CR_INCERRIE                    FLASH_CR_INCERRIE_Msk             /*!< Inconsistency error interrupt enable bit */

+#define FLASH_CR_OPERRIE_Pos                 (22U)

+#define FLASH_CR_OPERRIE_Msk                 (0x1UL << FLASH_CR_OPERRIE_Pos)   /*!< 0x00400000 */

+#define FLASH_CR_OPERRIE                     FLASH_CR_OPERRIE_Msk              /*!< Write/erase error interrupt enable bit */

+#define FLASH_CR_RDPERRIE_Pos                (23U)

+#define FLASH_CR_RDPERRIE_Msk                (0x1UL << FLASH_CR_RDPERRIE_Pos)  /*!< 0x00800000 */

+#define FLASH_CR_RDPERRIE                    FLASH_CR_RDPERRIE_Msk             /*!< Read protection error interrupt enable bit */

+#define FLASH_CR_RDSERRIE_Pos                (24U)

+#define FLASH_CR_RDSERRIE_Msk                (0x1UL << FLASH_CR_RDSERRIE_Pos)  /*!< 0x01000000 */

+#define FLASH_CR_RDSERRIE                    FLASH_CR_RDSERRIE_Msk             /*!< Secure error interrupt enable bit */

+#define FLASH_CR_SNECCERRIE_Pos              (25U)

+#define FLASH_CR_SNECCERRIE_Msk              (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */

+#define FLASH_CR_SNECCERRIE                  FLASH_CR_SNECCERRIE_Msk            /*!< ECC single correction error interrupt enable bit */

+#define FLASH_CR_DBECCERRIE_Pos              (26U)

+#define FLASH_CR_DBECCERRIE_Msk              (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */

+#define FLASH_CR_DBECCERRIE                  FLASH_CR_DBECCERRIE_Msk            /*!< ECC double detection error interrupt enable bit */

+#define FLASH_CR_CRCENDIE_Pos                (27U)

+#define FLASH_CR_CRCENDIE_Msk                (0x1UL << FLASH_CR_CRCENDIE_Pos)  /*!< 0x08000000 */

+#define FLASH_CR_CRCENDIE                    FLASH_CR_CRCENDIE_Msk             /*!< CRC end of calculation interrupt enable bit */

+#define FLASH_CR_CRCRDERRIE_Pos              (28U)

+#define FLASH_CR_CRCRDERRIE_Msk              (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */

+#define FLASH_CR_CRCRDERRIE                  FLASH_CR_CRCRDERRIE_Msk            /*!< CRC read error interrupt enable bit */

+

+/*******************  Bits definition for FLASH_SR register  ***********************/

+#define FLASH_SR_BSY_Pos                     (0U)

+#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)       /*!< 0x00000001 */

+#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy flag */

+#define FLASH_SR_WBNE_Pos                    (1U)

+#define FLASH_SR_WBNE_Msk                    (0x1UL << FLASH_SR_WBNE_Pos)      /*!< 0x00000002 */

+#define FLASH_SR_WBNE                        FLASH_SR_WBNE_Msk                 /*!< Write buffer not empty flag */

+#define FLASH_SR_QW_Pos                      (2U)

+#define FLASH_SR_QW_Msk                      (0x1UL << FLASH_SR_QW_Pos)        /*!< 0x00000004 */

+#define FLASH_SR_QW                          FLASH_SR_QW_Msk                   /*!< Wait queue flag */

+#define FLASH_SR_CRC_BUSY_Pos                (3U)

+#define FLASH_SR_CRC_BUSY_Msk                (0x1UL << FLASH_SR_CRC_BUSY_Pos)  /*!< 0x00000008 */

+#define FLASH_SR_CRC_BUSY                    FLASH_SR_CRC_BUSY_Msk             /*!< CRC busy flag */

+#define FLASH_SR_EOP_Pos                     (16U)

+#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)       /*!< 0x00010000 */

+#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End-of-program flag */

+#define FLASH_SR_WRPERR_Pos                  (17U)

+#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)    /*!< 0x00020000 */

+#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protection error flag */

+#define FLASH_SR_PGSERR_Pos                  (18U)

+#define FLASH_SR_PGSERR_Msk                  (0x1UL << FLASH_SR_PGSERR_Pos)    /*!< 0x00040000 */

+#define FLASH_SR_PGSERR                      FLASH_SR_PGSERR_Msk               /*!< Programming sequence error flag */

+#define FLASH_SR_STRBERR_Pos                 (19U)

+#define FLASH_SR_STRBERR_Msk                 (0x1UL << FLASH_SR_STRBERR_Pos)   /*!< 0x00080000 */

+#define FLASH_SR_STRBERR                     FLASH_SR_STRBERR_Msk              /*!< Strobe error flag */

+#define FLASH_SR_INCERR_Pos                  (21U)

+#define FLASH_SR_INCERR_Msk                  (0x1UL << FLASH_SR_INCERR_Pos)    /*!< 0x00200000 */

+#define FLASH_SR_INCERR                      FLASH_SR_INCERR_Msk               /*!< Inconsistency error flag */

+#define FLASH_SR_OPERR_Pos                   (22U)

+#define FLASH_SR_OPERR_Msk                   (0x1UL << FLASH_SR_OPERR_Pos)     /*!< 0x00400000 */

+#define FLASH_SR_OPERR                       FLASH_SR_OPERR_Msk                /*!< Write/erase error flag */

+#define FLASH_SR_RDPERR_Pos                  (23U)

+#define FLASH_SR_RDPERR_Msk                  (0x1UL << FLASH_SR_RDPERR_Pos)    /*!< 0x00800000 */

+#define FLASH_SR_RDPERR                      FLASH_SR_RDPERR_Msk               /*!< Read protection error flag */

+#define FLASH_SR_RDSERR_Pos                  (24U)

+#define FLASH_SR_RDSERR_Msk                  (0x1UL << FLASH_SR_RDSERR_Pos)    /*!< 0x01000000 */

+#define FLASH_SR_RDSERR                      FLASH_SR_RDSERR_Msk               /*!< Secure error flag */

+#define FLASH_SR_SNECCERR_Pos                (25U)

+#define FLASH_SR_SNECCERR_Msk                (0x1UL << FLASH_SR_SNECCERR_Pos)  /*!< 0x02000000 */

+#define FLASH_SR_SNECCERR                    FLASH_SR_SNECCERR_Msk             /*!< Single correction error flag */

+#define FLASH_SR_DBECCERR_Pos                (26U)

+#define FLASH_SR_DBECCERR_Msk                (0x1UL << FLASH_SR_DBECCERR_Pos)  /*!< 0x04000000 */

+#define FLASH_SR_DBECCERR                    FLASH_SR_DBECCERR_Msk             /*!< ECC double detection error flag */

+#define FLASH_SR_CRCEND_Pos                  (27U)

+#define FLASH_SR_CRCEND_Msk                  (0x1UL << FLASH_SR_CRCEND_Pos)    /*!< 0x08000000 */

+#define FLASH_SR_CRCEND                      FLASH_SR_CRCEND_Msk               /*!< CRC end of calculation flag */

+#define FLASH_SR_CRCRDERR_Pos                (28U)

+#define FLASH_SR_CRCRDERR_Msk                (0x1UL << FLASH_SR_CRCRDERR_Pos)  /*!< 0x10000000 */

+#define FLASH_SR_CRCRDERR                    FLASH_SR_CRCRDERR_Msk             /*!< CRC read error flag */

+

+/*******************  Bits definition for FLASH_CCR register  *******************/

+#define FLASH_CCR_CLR_EOP_Pos                (16U)

+#define FLASH_CCR_CLR_EOP_Msk                (0x1UL << FLASH_CCR_CLR_EOP_Pos)  /*!< 0x00010000 */

+#define FLASH_CCR_CLR_EOP                    FLASH_CCR_CLR_EOP_Msk             /*!< EOP flag clear bit */

+#define FLASH_CCR_CLR_WRPERR_Pos             (17U)

+#define FLASH_CCR_CLR_WRPERR_Msk             (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */

+#define FLASH_CCR_CLR_WRPERR                 FLASH_CCR_CLR_WRPERR_Msk            /*!< WRPERR flag clear bit */

+#define FLASH_CCR_CLR_PGSERR_Pos             (18U)

+#define FLASH_CCR_CLR_PGSERR_Msk             (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */

+#define FLASH_CCR_CLR_PGSERR                 FLASH_CCR_CLR_PGSERR_Msk            /*!< PGSERR flag clear bit */

+#define FLASH_CCR_CLR_STRBERR_Pos            (19U)

+#define FLASH_CCR_CLR_STRBERR_Msk            (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */

+#define FLASH_CCR_CLR_STRBERR                FLASH_CCR_CLR_STRBERR_Msk            /*!< STRBERR flag clear bit */

+#define FLASH_CCR_CLR_INCERR_Pos             (21U)

+#define FLASH_CCR_CLR_INCERR_Msk             (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */

+#define FLASH_CCR_CLR_INCERR                 FLASH_CCR_CLR_INCERR_Msk            /*!< INCERR flag clear bit */

+#define FLASH_CCR_CLR_OPERR_Pos              (22U)

+#define FLASH_CCR_CLR_OPERR_Msk              (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */

+#define FLASH_CCR_CLR_OPERR                  FLASH_CCR_CLR_OPERR_Msk            /*!< OPERR flag clear bit */

+#define FLASH_CCR_CLR_RDPERR_Pos             (23U)

+#define FLASH_CCR_CLR_RDPERR_Msk             (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */

+#define FLASH_CCR_CLR_RDPERR                 FLASH_CCR_CLR_RDPERR_Msk            /*!< RDPERR flag clear bit */

+#define FLASH_CCR_CLR_RDSERR_Pos             (24U)

+#define FLASH_CCR_CLR_RDSERR_Msk             (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */

+#define FLASH_CCR_CLR_RDSERR                 FLASH_CCR_CLR_RDSERR_Msk            /*!< RDSERR flag clear bit */

+#define FLASH_CCR_CLR_SNECCERR_Pos           (25U)

+#define FLASH_CCR_CLR_SNECCERR_Msk           (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */

+#define FLASH_CCR_CLR_SNECCERR               FLASH_CCR_CLR_SNECCERR_Msk            /*!< SNECCERR flag clear bit */

+#define FLASH_CCR_CLR_DBECCERR_Pos           (26U)

+#define FLASH_CCR_CLR_DBECCERR_Msk           (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */

+#define FLASH_CCR_CLR_DBECCERR               FLASH_CCR_CLR_DBECCERR_Msk            /*!< DBECCERR flag clear bit */

+#define FLASH_CCR_CLR_CRCEND_Pos             (27U)

+#define FLASH_CCR_CLR_CRCEND_Msk             (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */

+#define FLASH_CCR_CLR_CRCEND                 FLASH_CCR_CLR_CRCEND_Msk            /*!< CRCEND flag clear bit */

+#define FLASH_CCR_CLR_CRCRDERR_Pos           (28U)

+#define FLASH_CCR_CLR_CRCRDERR_Msk           (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */

+#define FLASH_CCR_CLR_CRCRDERR               FLASH_CCR_CLR_CRCRDERR_Msk            /*!< CRCRDERR flag clear bit */

+

+/*******************  Bits definition for FLASH_OPTCR register  *******************/

+#define FLASH_OPTCR_OPTLOCK_Pos              (0U)

+#define FLASH_OPTCR_OPTLOCK_Msk              (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)  /*!< 0x00000001 */

+#define FLASH_OPTCR_OPTLOCK                  FLASH_OPTCR_OPTLOCK_Msk             /*!< FLASH_OPTCR lock option configuration bit */

+#define FLASH_OPTCR_OPTSTART_Pos             (1U)

+#define FLASH_OPTCR_OPTSTART_Msk             (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */

+#define FLASH_OPTCR_OPTSTART                 FLASH_OPTCR_OPTSTART_Msk            /*!< Option byte start change option configuration bit */

+#define FLASH_OPTCR_MER_Pos                  (4U)

+#define FLASH_OPTCR_MER_Msk                  (0x1UL << FLASH_OPTCR_MER_Pos)      /*!< 0x00000010 */

+#define FLASH_OPTCR_MER                      FLASH_OPTCR_MER_Msk                 /*!< Mass erase request */

+#define FLASH_OPTCR_OPTCHANGEERRIE_Pos       (30U)

+#define FLASH_OPTCR_OPTCHANGEERRIE_Msk       (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */

+#define FLASH_OPTCR_OPTCHANGEERRIE           FLASH_OPTCR_OPTCHANGEERRIE_Msk            /*!< Option byte change error interrupt enable bit */

+#define FLASH_OPTCR_SWAP_BANK_Pos            (31U)

+#define FLASH_OPTCR_SWAP_BANK_Msk            (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */

+#define FLASH_OPTCR_SWAP_BANK                FLASH_OPTCR_SWAP_BANK_Msk            /*!< Bank swapping option configuration bit */

+

+/*******************  Bits definition for FLASH_OPTSR register  ***************/

+#define FLASH_OPTSR_OPT_BUSY_Pos             (0U)

+#define FLASH_OPTSR_OPT_BUSY_Msk             (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */

+#define FLASH_OPTSR_OPT_BUSY                 FLASH_OPTSR_OPT_BUSY_Msk            /*!< Option byte change ongoing flag */

+#define FLASH_OPTSR_BOR_LEV_Pos              (2U)

+#define FLASH_OPTSR_BOR_LEV_Msk              (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */

+#define FLASH_OPTSR_BOR_LEV                  FLASH_OPTSR_BOR_LEV_Msk            /*!< Brownout level option status bit */

+#define FLASH_OPTSR_BOR_LEV_0                (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */

+#define FLASH_OPTSR_BOR_LEV_1                (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */

+#define FLASH_OPTSR_IWDG1_SW_Pos             (4U)

+#define FLASH_OPTSR_IWDG1_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */

+#define FLASH_OPTSR_IWDG1_SW                 FLASH_OPTSR_IWDG1_SW_Msk            /*!< IWDG1 control mode option status bit */

+#define FLASH_OPTSR_IWDG2_SW_Pos             (5U)

+#define FLASH_OPTSR_IWDG2_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG2_SW_Pos) /*!< 0x00000020 */

+#define FLASH_OPTSR_IWDG2_SW                 FLASH_OPTSR_IWDG2_SW_Msk            /*!< IWDG2 control mode option status bit */

+#define FLASH_OPTSR_NRST_STOP_D1_Pos         (6U)

+#define FLASH_OPTSR_NRST_STOP_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */

+#define FLASH_OPTSR_NRST_STOP_D1             FLASH_OPTSR_NRST_STOP_D1_Msk            /*!< D1 domain DStop entry reset option status bit */

+#define FLASH_OPTSR_NRST_STBY_D1_Pos         (7U)

+#define FLASH_OPTSR_NRST_STBY_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */

+#define FLASH_OPTSR_NRST_STBY_D1             FLASH_OPTSR_NRST_STBY_D1_Msk            /*!< D1 domain DStandby entry reset option status bit */

+#define FLASH_OPTSR_RDP_Pos                  (8U)

+#define FLASH_OPTSR_RDP_Msk                  (0xFFUL << FLASH_OPTSR_RDP_Pos)   /*!< 0x0000FF00 */

+#define FLASH_OPTSR_RDP                      FLASH_OPTSR_RDP_Msk               /*!< Readout protection level option status byte */

+#define FLASH_OPTSR_FZ_IWDG_STOP_Pos         (17U)

+#define FLASH_OPTSR_FZ_IWDG_STOP_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */

+#define FLASH_OPTSR_FZ_IWDG_STOP             FLASH_OPTSR_FZ_IWDG_STOP_Msk            /*!< IWDG Stop mode freeze option status bit */

+#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos         (18U)

+#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */

+#define FLASH_OPTSR_FZ_IWDG_SDBY             FLASH_OPTSR_FZ_IWDG_SDBY_Msk            /*!< IWDG Standby mode freeze option status bit */

+#define FLASH_OPTSR_ST_RAM_SIZE_Pos          (19U)

+#define FLASH_OPTSR_ST_RAM_SIZE_Msk          (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */

+#define FLASH_OPTSR_ST_RAM_SIZE              FLASH_OPTSR_ST_RAM_SIZE_Msk            /*!< ST RAM size option status */

+#define FLASH_OPTSR_ST_RAM_SIZE_0            (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */

+#define FLASH_OPTSR_ST_RAM_SIZE_1            (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */

+#define FLASH_OPTSR_SECURITY_Pos             (21U)

+#define FLASH_OPTSR_SECURITY_Msk             (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */

+#define FLASH_OPTSR_SECURITY                 FLASH_OPTSR_SECURITY_Msk            /*!< Security enable option status bit */

+#define FLASH_OPTSR_BCM4_Pos                 (22U)

+#define FLASH_OPTSR_BCM4_Msk                 (0x1UL << FLASH_OPTSR_BCM4_Pos)   /*!< 0x00400000 */

+#define FLASH_OPTSR_BCM4                     FLASH_OPTSR_BCM4_Msk              /*!< Arm Cortex-M4 boot option status bit */

+#define FLASH_OPTSR_BCM7_Pos                 (23U)

+#define FLASH_OPTSR_BCM7_Msk                 (0x1UL << FLASH_OPTSR_BCM7_Pos)   /*!< 0x00800000 */

+#define FLASH_OPTSR_BCM7                     FLASH_OPTSR_BCM7_Msk              /*!< Arm Cortex-M7 boot option status bit */

+#define FLASH_OPTSR_NRST_STOP_D2_Pos         (24U)

+#define FLASH_OPTSR_NRST_STOP_D2_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D2_Pos) /*!< 0x01000000 */

+#define FLASH_OPTSR_NRST_STOP_D2             FLASH_OPTSR_NRST_STOP_D2_Msk            /*!< D2 domain DStop entry reset option status bit */

+#define FLASH_OPTSR_NRST_STBY_D2_Pos         (25U)

+#define FLASH_OPTSR_NRST_STBY_D2_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D2_Pos) /*!< 0x02000000 */

+#define FLASH_OPTSR_NRST_STBY_D2             FLASH_OPTSR_NRST_STBY_D2_Msk            /*!< D2 domain DStandby entry reset option status bit */

+#define FLASH_OPTSR_IO_HSLV_Pos              (29U)

+#define FLASH_OPTSR_IO_HSLV_Msk              (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */

+#define FLASH_OPTSR_IO_HSLV                  FLASH_OPTSR_IO_HSLV_Msk            /*!< I/O high-speed at low-voltage status bit */

+#define FLASH_OPTSR_OPTCHANGEERR_Pos         (30U)

+#define FLASH_OPTSR_OPTCHANGEERR_Msk         (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */

+#define FLASH_OPTSR_OPTCHANGEERR             FLASH_OPTSR_OPTCHANGEERR_Msk            /*!< Option byte change error flag */

+#define FLASH_OPTSR_SWAP_BANK_OPT_Pos        (31U)

+#define FLASH_OPTSR_SWAP_BANK_OPT_Msk        (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */

+#define FLASH_OPTSR_SWAP_BANK_OPT            FLASH_OPTSR_SWAP_BANK_OPT_Msk            /*!< Bank swapping option status bit */

+

+/*******************  Bits definition for FLASH_OPTCCR register  *******************/

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos    (30U)

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk    (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR        FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk            /*!< OPTCHANGEERR reset bit */

+

+/*******************  Bits definition for FLASH_PRAR register  *********************/

+#define FLASH_PRAR_PROT_AREA_START_Pos       (0U)

+#define FLASH_PRAR_PROT_AREA_START_Msk       (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */

+#define FLASH_PRAR_PROT_AREA_START           FLASH_PRAR_PROT_AREA_START_Msk              /*!< PCROP area start status bits */

+#define FLASH_PRAR_PROT_AREA_END_Pos         (16U)

+#define FLASH_PRAR_PROT_AREA_END_Msk         (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */

+#define FLASH_PRAR_PROT_AREA_END             FLASH_PRAR_PROT_AREA_END_Msk              /*!< PCROP area end status bits */

+#define FLASH_PRAR_DMEP_Pos                  (31U)

+#define FLASH_PRAR_DMEP_Msk                  (0x1UL << FLASH_PRAR_DMEP_Pos)    /*!< 0x80000000 */

+#define FLASH_PRAR_DMEP                      FLASH_PRAR_DMEP_Msk               /*!< PCROP protected erase enable option status bit */

+

+/*******************  Bits definition for FLASH_SCAR register  *********************/

+#define FLASH_SCAR_SEC_AREA_START_Pos        (0U)

+#define FLASH_SCAR_SEC_AREA_START_Msk        (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */

+#define FLASH_SCAR_SEC_AREA_START            FLASH_SCAR_SEC_AREA_START_Msk              /*!< Secure-only area start status bits */

+#define FLASH_SCAR_SEC_AREA_END_Pos          (16U)

+#define FLASH_SCAR_SEC_AREA_END_Msk          (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */

+#define FLASH_SCAR_SEC_AREA_END              FLASH_SCAR_SEC_AREA_END_Msk              /*!< Secure-only area end status bits */

+#define FLASH_SCAR_DMES_Pos                  (31U)

+#define FLASH_SCAR_DMES_Msk                  (0x1UL << FLASH_SCAR_DMES_Pos)    /*!< 0x80000000 */

+#define FLASH_SCAR_DMES                      FLASH_SCAR_DMES_Msk               /*!< Secure access protected erase enable option status bit */

+

+/*******************  Bits definition for FLASH_WPSN register  *********************/

+#define FLASH_WPSN_WRPSN_Pos                 (0U)

+#define FLASH_WPSN_WRPSN_Msk                 (0xFFUL << FLASH_WPSN_WRPSN_Pos)  /*!< 0x000000FF */

+#define FLASH_WPSN_WRPSN                     FLASH_WPSN_WRPSN_Msk              /*!< Sector write protection option status byte */

+

+/*******************  Bits definition for FLASH_BOOT7_CUR register  ****************/

+#define FLASH_BOOT7_BCM7_ADD0_Pos            (0U)

+#define FLASH_BOOT7_BCM7_ADD0_Msk            (0xFFFFUL << FLASH_BOOT7_BCM7_ADD0_Pos) /*!< 0x0000FFFF */

+#define FLASH_BOOT7_BCM7_ADD0                FLASH_BOOT7_BCM7_ADD0_Msk               /*!< Arm Cortex-M7 boot address 0 */

+#define FLASH_BOOT7_BCM7_ADD1_Pos            (16U)

+#define FLASH_BOOT7_BCM7_ADD1_Msk            (0xFFFFUL << FLASH_BOOT7_BCM7_ADD1_Pos) /*!< 0xFFFF0000 */

+#define FLASH_BOOT7_BCM7_ADD1                FLASH_BOOT7_BCM7_ADD1_Msk               /*!< Arm Cortex-M7 boot address 1 */

+

+/*******************  Bits definition for FLASH_BOOT4 register  ********************/

+#define FLASH_BOOT4_BCM4_ADD0_Pos            (0U)

+#define FLASH_BOOT4_BCM4_ADD0_Msk            (0xFFFFUL << FLASH_BOOT4_BCM4_ADD0_Pos) /*!< 0x0000FFFF */

+#define FLASH_BOOT4_BCM4_ADD0                FLASH_BOOT4_BCM4_ADD0_Msk               /*!< Arm Cortex-M4 boot address 0 */

+#define FLASH_BOOT4_BCM4_ADD1_Pos            (16U)

+#define FLASH_BOOT4_BCM4_ADD1_Msk            (0xFFFFUL << FLASH_BOOT4_BCM4_ADD1_Pos) /*!< 0xFFFF0000 */

+#define FLASH_BOOT4_BCM4_ADD1                FLASH_BOOT4_BCM4_ADD1_Msk               /*!< Arm Cortex-M4 boot address 1 */

+

+/*******************  Bits definition for FLASH_CRCCR register  ********************/

+#define FLASH_CRCCR_CRC_SECT_Pos             (0U)

+#define FLASH_CRCCR_CRC_SECT_Msk             (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */

+#define FLASH_CRCCR_CRC_SECT                 FLASH_CRCCR_CRC_SECT_Msk            /*!< CRC sector number */

+#define FLASH_CRCCR_CRC_BY_SECT_Pos          (8U)

+#define FLASH_CRCCR_CRC_BY_SECT_Msk          (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */

+#define FLASH_CRCCR_CRC_BY_SECT              FLASH_CRCCR_CRC_BY_SECT_Msk            /*!< CRC sector mode select bit */

+#define FLASH_CRCCR_ADD_SECT_Pos             (9U)

+#define FLASH_CRCCR_ADD_SECT_Msk             (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */

+#define FLASH_CRCCR_ADD_SECT                 FLASH_CRCCR_ADD_SECT_Msk            /*!< CRC sector select bit */

+#define FLASH_CRCCR_CLEAN_SECT_Pos           (10U)

+#define FLASH_CRCCR_CLEAN_SECT_Msk           (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */

+#define FLASH_CRCCR_CLEAN_SECT               FLASH_CRCCR_CLEAN_SECT_Msk            /*!< CRC sector list clear bit */

+#define FLASH_CRCCR_START_CRC_Pos            (16U)

+#define FLASH_CRCCR_START_CRC_Msk            (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */

+#define FLASH_CRCCR_START_CRC                FLASH_CRCCR_START_CRC_Msk            /*!< CRC start bit */

+#define FLASH_CRCCR_CLEAN_CRC_Pos            (17U)

+#define FLASH_CRCCR_CLEAN_CRC_Msk            (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */

+#define FLASH_CRCCR_CLEAN_CRC                FLASH_CRCCR_CLEAN_CRC_Msk            /*!< CRC clear bit */

+#define FLASH_CRCCR_CRC_BURST_Pos            (20U)

+#define FLASH_CRCCR_CRC_BURST_Msk            (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */

+#define FLASH_CRCCR_CRC_BURST                FLASH_CRCCR_CRC_BURST_Msk            /*!< CRC burst size */

+#define FLASH_CRCCR_CRC_BURST_0              (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */

+#define FLASH_CRCCR_CRC_BURST_1              (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */

+#define FLASH_CRCCR_ALL_BANK_Pos             (22U)

+#define FLASH_CRCCR_ALL_BANK_Msk             (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */

+#define FLASH_CRCCR_ALL_BANK                 FLASH_CRCCR_ALL_BANK_Msk            /*!< CRC select bit */

+

+/*******************  Bits definition for FLASH_CRCSADD register  ****************/

+#define FLASH_CRCSADD_CRC_START_ADDR_Pos     (0U)

+#define FLASH_CRCSADD_CRC_START_ADDR_Msk     (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCSADD_CRC_START_ADDR         FLASH_CRCSADD_CRC_START_ADDR_Msk                   /*!< CRC start address */

+

+/*******************  Bits definition for FLASH_CRCEADD register  ****************/

+#define FLASH_CRCEADD_CRC_END_ADDR_Pos       (0U)

+#define FLASH_CRCEADD_CRC_END_ADDR_Msk       (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCEADD_CRC_END_ADDR           FLASH_CRCEADD_CRC_END_ADDR_Msk                   /*!< CRC end address */

+

+/*******************  Bits definition for FLASH_CRCDATA register  ***************/

+#define FLASH_CRCDATA_CRC_DATA_Pos           (0U)

+#define FLASH_CRCDATA_CRC_DATA_Msk           (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCDATA_CRC_DATA               FLASH_CRCDATA_CRC_DATA_Msk                   /*!< CRC result */

+

+/*******************  Bits definition for FLASH_ECC_FA register  *******************/

+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos       (0U)

+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk       (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */

+#define FLASH_ECC_FA_FAIL_ECC_ADDR           FLASH_ECC_FA_FAIL_ECC_ADDR_Msk               /*!< ECC error address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          Flexible Memory Controller                        */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for FMC_BCR1 register  *******************/

+#define FMC_BCR1_CCLKEN_Pos        (20U)

+#define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */

+#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continous clock enable     */

+#define FMC_BCR1_WFDIS_Pos         (21U)

+#define FMC_BCR1_WFDIS_Msk         (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */

+#define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */

+

+#define FMC_BCR1_BMAP_Pos          (24U)

+#define FMC_BCR1_BMAP_Msk          (0x3UL << FMC_BCR1_BMAP_Pos)                /*!< 0x03000000 */

+#define FMC_BCR1_BMAP              FMC_BCR1_BMAP_Msk                           /*!<BMAP[1:0] FMC bank mapping */

+#define FMC_BCR1_BMAP_0            (0x1UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x01000000 */

+#define FMC_BCR1_BMAP_1            (0x2UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x02000000 */

+

+#define FMC_BCR1_FMCEN_Pos         (31U)

+#define FMC_BCR1_FMCEN_Msk         (0x1UL << FMC_BCR1_FMCEN_Pos)               /*!< 0x80000000 */

+#define FMC_BCR1_FMCEN             FMC_BCR1_FMCEN_Msk                          /*!<FMC controller Enable */

+/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/

+#define FMC_BCRx_MBKEN_Pos         (0U)

+#define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */

+#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */

+#define FMC_BCRx_MUXEN_Pos         (1U)

+#define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */

+#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */

+

+#define FMC_BCRx_MTYP_Pos          (2U)

+#define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */

+#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */

+#define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000004 */

+#define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000008 */

+

+#define FMC_BCRx_MWID_Pos          (4U)

+#define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */

+#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */

+#define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000010 */

+#define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000020 */

+

+#define FMC_BCRx_FACCEN_Pos        (6U)

+#define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */

+#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */

+#define FMC_BCRx_BURSTEN_Pos       (8U)

+#define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */

+#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */

+#define FMC_BCRx_WAITPOL_Pos       (9U)

+#define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */

+#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */

+#define FMC_BCRx_WAITCFG_Pos       (11U)

+#define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */

+#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */

+#define FMC_BCRx_WREN_Pos          (12U)

+#define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */

+#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */

+#define FMC_BCRx_WAITEN_Pos        (13U)

+#define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */

+#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */

+#define FMC_BCRx_EXTMOD_Pos        (14U)

+#define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */

+#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */

+#define FMC_BCRx_ASYNCWAIT_Pos     (15U)

+#define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */

+#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */

+

+#define FMC_BCRx_CPSIZE_Pos        (16U)

+#define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */

+#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<PSIZE[2:0] bits CRAM Page Size */

+#define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00010000 */

+#define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00020000 */

+#define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00040000 */

+

+#define FMC_BCRx_CBURSTRW_Pos      (19U)

+#define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */

+#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */

+

+/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/

+#define FMC_BTRx_ADDSET_Pos        (0U)

+#define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */

+#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */

+#define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000001 */

+#define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000002 */

+#define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000004 */

+#define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000008 */

+

+#define FMC_BTRx_ADDHLD_Pos        (4U)

+#define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */

+#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */

+#define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000010 */

+#define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000020 */

+#define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000040 */

+#define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000080 */

+

+#define FMC_BTRx_DATAST_Pos        (8U)

+#define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */

+#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */

+#define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000100 */

+#define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000200 */

+#define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000400 */

+#define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000800 */

+#define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00001000 */

+#define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00002000 */

+#define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00004000 */

+#define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00008000 */

+

+#define FMC_BTRx_BUSTURN_Pos       (16U)

+#define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */

+#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */

+#define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00010000 */

+#define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00020000 */

+#define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00040000 */

+#define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00080000 */

+

+#define FMC_BTRx_CLKDIV_Pos        (20U)

+#define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */

+#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */

+#define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00100000 */

+#define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00200000 */

+#define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00400000 */

+#define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00800000 */

+

+#define FMC_BTRx_DATLAT_Pos        (24U)

+#define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */

+#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */

+#define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x01000000 */

+#define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x02000000 */

+#define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x04000000 */

+#define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x08000000 */

+

+#define FMC_BTRx_ACCMOD_Pos        (28U)

+#define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */

+#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */

+#define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x10000000 */

+#define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x20000000 */

+

+/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/

+#define FMC_BWTRx_ADDSET_Pos       (0U)

+#define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */

+#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */

+#define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000001 */

+#define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000002 */

+#define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000004 */

+#define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000008 */

+

+#define FMC_BWTRx_ADDHLD_Pos       (4U)

+#define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */

+#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */

+#define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000010 */

+#define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000020 */

+#define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000040 */

+#define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000080 */

+

+#define FMC_BWTRx_DATAST_Pos       (8U)

+#define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */

+#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */

+#define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000100 */

+#define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000200 */

+#define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000400 */

+#define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000800 */

+#define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00001000 */

+#define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00002000 */

+#define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00004000 */

+#define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00008000 */

+

+#define FMC_BWTRx_BUSTURN_Pos      (16U)

+#define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */

+#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */

+#define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00010000 */

+#define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00020000 */

+#define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00040000 */

+#define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00080000 */

+

+#define FMC_BWTRx_ACCMOD_Pos       (28U)

+#define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */

+#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */

+#define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x10000000 */

+#define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x20000000 */

+

+/******************  Bit definition for FMC_PCR register  *******************/

+#define FMC_PCR_PWAITEN_Pos        (1U)

+#define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */

+#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */

+#define FMC_PCR_PBKEN_Pos          (2U)

+#define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */

+#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */

+

+#define FMC_PCR_PWID_Pos           (4U)

+#define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */

+#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */

+#define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */

+#define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */

+

+#define FMC_PCR_ECCEN_Pos          (6U)

+#define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */

+#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */

+

+#define FMC_PCR_TCLR_Pos           (9U)

+#define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */

+#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */

+#define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */

+#define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */

+#define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */

+#define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */

+

+#define FMC_PCR_TAR_Pos            (13U)

+#define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */

+#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */

+#define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */

+#define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */

+#define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */

+#define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */

+

+#define FMC_PCR_ECCPS_Pos          (17U)

+#define FMC_PCR_ECCPS_Msk          (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */

+#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */

+#define FMC_PCR_ECCPS_0            (0x1UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */

+#define FMC_PCR_ECCPS_1            (0x2UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */

+#define FMC_PCR_ECCPS_2            (0x4UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */

+

+/*******************  Bit definition for FMC_SR register  *******************/

+#define FMC_SR_IRS_Pos             (0U)

+#define FMC_SR_IRS_Msk             (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */

+#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */

+#define FMC_SR_ILS_Pos             (1U)

+#define FMC_SR_ILS_Msk             (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */

+#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */

+#define FMC_SR_IFS_Pos             (2U)

+#define FMC_SR_IFS_Msk             (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */

+#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */

+#define FMC_SR_IREN_Pos            (3U)

+#define FMC_SR_IREN_Msk            (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */

+#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */

+#define FMC_SR_ILEN_Pos            (4U)

+#define FMC_SR_ILEN_Msk            (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */

+#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */

+#define FMC_SR_IFEN_Pos            (5U)

+#define FMC_SR_IFEN_Msk            (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */

+#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */

+#define FMC_SR_FEMPT_Pos           (6U)

+#define FMC_SR_FEMPT_Msk           (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */

+#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */

+

+/******************  Bit definition for FMC_PMEM register  ******************/

+#define FMC_PMEM_MEMSET_Pos       (0U)

+#define FMC_PMEM_MEMSET_Msk       (0xFFUL << FMC_PMEM_MEMSET_Pos)            /*!< 0x000000FF */

+#define FMC_PMEM_MEMSET           FMC_PMEM_MEMSET_Msk                        /*!<MEMSET[7:0] bits (Common memory setup time) */

+#define FMC_PMEM_MEMSET_0         (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */

+#define FMC_PMEM_MEMSET_1         (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */

+#define FMC_PMEM_MEMSET_2         (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */

+#define FMC_PMEM_MEMSET_3         (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */

+#define FMC_PMEM_MEMSET_4         (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */

+#define FMC_PMEM_MEMSET_5         (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */

+#define FMC_PMEM_MEMSET_6         (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */

+#define FMC_PMEM_MEMSET_7         (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */

+

+#define FMC_PMEM_MEMWAIT_Pos      (8U)

+#define FMC_PMEM_MEMWAIT_Msk      (0xFFUL << FMC_PMEM_MEMWAIT_Pos)           /*!< 0x0000FF00 */

+#define FMC_PMEM_MEMWAIT          FMC_PMEM_MEMWAIT_Msk                       /*!<MEMWAIT[7:0] bits (Common memory wait time) */

+#define FMC_PMEM_MEMWAIT_0        (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */

+#define FMC_PMEM_MEMWAIT_1        (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */

+#define FMC_PMEM_MEMWAIT_2        (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */

+#define FMC_PMEM_MEMWAIT_3        (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */

+#define FMC_PMEM_MEMWAIT_4        (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */

+#define FMC_PMEM_MEMWAIT_5        (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */

+#define FMC_PMEM_MEMWAIT_6        (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */

+#define FMC_PMEM_MEMWAIT_7        (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */

+

+#define FMC_PMEM_MEMHOLD_Pos      (16U)

+#define FMC_PMEM_MEMHOLD_Msk      (0xFFUL << FMC_PMEM_MEMHOLD_Pos)           /*!< 0x00FF0000 */

+#define FMC_PMEM_MEMHOLD          FMC_PMEM_MEMHOLD_Msk                       /*!<MEMHOLD[7:0] bits (Common memory hold time) */

+#define FMC_PMEM_MEMHOLD_0        (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */

+#define FMC_PMEM_MEMHOLD_1        (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */

+#define FMC_PMEM_MEMHOLD_2        (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */

+#define FMC_PMEM_MEMHOLD_3        (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */

+#define FMC_PMEM_MEMHOLD_4        (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */

+#define FMC_PMEM_MEMHOLD_5        (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */

+#define FMC_PMEM_MEMHOLD_6        (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */

+#define FMC_PMEM_MEMHOLD_7        (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */

+

+#define FMC_PMEM_MEMHIZ_Pos       (24U)

+#define FMC_PMEM_MEMHIZ_Msk       (0xFFUL << FMC_PMEM_MEMHIZ_Pos)            /*!< 0xFF000000 */

+#define FMC_PMEM_MEMHIZ           FMC_PMEM_MEMHIZ_Msk                        /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */

+#define FMC_PMEM_MEMHIZ_0         (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */

+#define FMC_PMEM_MEMHIZ_1         (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */

+#define FMC_PMEM_MEMHIZ_2         (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */

+#define FMC_PMEM_MEMHIZ_3         (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */

+#define FMC_PMEM_MEMHIZ_4         (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */

+#define FMC_PMEM_MEMHIZ_5         (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */

+#define FMC_PMEM_MEMHIZ_6         (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */

+#define FMC_PMEM_MEMHIZ_7         (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */

+

+/******************  Bit definition for FMC_PATT register  ******************/

+#define FMC_PATT_ATTSET_Pos       (0U)

+#define FMC_PATT_ATTSET_Msk       (0xFFUL << FMC_PATT_ATTSET_Pos)            /*!< 0x000000FF */

+#define FMC_PATT_ATTSET           FMC_PATT_ATTSET_Msk                        /*!<ATTSET[7:0] bits (Attribute memory setup time) */

+#define FMC_PATT_ATTSET_0         (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */

+#define FMC_PATT_ATTSET_1         (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */

+#define FMC_PATT_ATTSET_2         (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */

+#define FMC_PATT_ATTSET_3         (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */

+#define FMC_PATT_ATTSET_4         (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */

+#define FMC_PATT_ATTSET_5         (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */

+#define FMC_PATT_ATTSET_6         (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */

+#define FMC_PATT_ATTSET_7         (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */

+

+#define FMC_PATT_ATTWAIT_Pos      (8U)

+#define FMC_PATT_ATTWAIT_Msk      (0xFFUL << FMC_PATT_ATTWAIT_Pos)           /*!< 0x0000FF00 */

+#define FMC_PATT_ATTWAIT          FMC_PATT_ATTWAIT_Msk                       /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */

+#define FMC_PATT_ATTWAIT_0        (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */

+#define FMC_PATT_ATTWAIT_1        (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */

+#define FMC_PATT_ATTWAIT_2        (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */

+#define FMC_PATT_ATTWAIT_3        (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */

+#define FMC_PATT_ATTWAIT_4        (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */

+#define FMC_PATT_ATTWAIT_5        (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */

+#define FMC_PATT_ATTWAIT_6        (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */

+#define FMC_PATT_ATTWAIT_7        (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */

+

+#define FMC_PATT_ATTHOLD_Pos      (16U)

+#define FMC_PATT_ATTHOLD_Msk      (0xFFUL << FMC_PATT_ATTHOLD_Pos)           /*!< 0x00FF0000 */

+#define FMC_PATT_ATTHOLD          FMC_PATT_ATTHOLD_Msk                       /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */

+#define FMC_PATT_ATTHOLD_0        (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */

+#define FMC_PATT_ATTHOLD_1        (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */

+#define FMC_PATT_ATTHOLD_2        (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */

+#define FMC_PATT_ATTHOLD_3        (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */

+#define FMC_PATT_ATTHOLD_4        (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */

+#define FMC_PATT_ATTHOLD_5        (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */

+#define FMC_PATT_ATTHOLD_6        (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */

+#define FMC_PATT_ATTHOLD_7        (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */

+

+#define FMC_PATT_ATTHIZ_Pos       (24U)

+#define FMC_PATT_ATTHIZ_Msk       (0xFFUL << FMC_PATT_ATTHIZ_Pos)            /*!< 0xFF000000 */

+#define FMC_PATT_ATTHIZ           FMC_PATT_ATTHIZ_Msk                        /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */

+#define FMC_PATT_ATTHIZ_0         (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */

+#define FMC_PATT_ATTHIZ_1         (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */

+#define FMC_PATT_ATTHIZ_2         (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */

+#define FMC_PATT_ATTHIZ_3         (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */

+#define FMC_PATT_ATTHIZ_4         (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */

+#define FMC_PATT_ATTHIZ_5         (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */

+#define FMC_PATT_ATTHIZ_6         (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */

+#define FMC_PATT_ATTHIZ_7         (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */

+

+/******************  Bit definition for FMC_ECCR3 register  ******************/

+#define FMC_ECCR3_ECC3_Pos         (0U)

+#define FMC_ECCR3_ECC3_Msk         (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)        /*!< 0xFFFFFFFF */

+#define FMC_ECCR3_ECC3             FMC_ECCR3_ECC3_Msk                          /*!<ECC result */

+

+/******************  Bit definition for FMC_SDCRx registers (x=1..4)  *********/

+#define FMC_SDCRx_NC_Pos           (0U)

+#define FMC_SDCRx_NC_Msk           (0x3UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000003 */

+#define FMC_SDCRx_NC               FMC_SDCRx_NC_Msk                            /*!<NC[1:0] bits (Number of column bits) */

+#define FMC_SDCRx_NC_0             (0x1UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000001 */

+#define FMC_SDCRx_NC_1             (0x2UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000002 */

+

+#define FMC_SDCRx_NR_Pos           (2U)

+#define FMC_SDCRx_NR_Msk           (0x3UL << FMC_SDCRx_NR_Pos)                 /*!< 0x0000000C */

+#define FMC_SDCRx_NR               FMC_SDCRx_NR_Msk                            /*!<NR[1:0] bits (Number of row bits) */

+#define FMC_SDCRx_NR_0             (0x1UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000004 */

+#define FMC_SDCRx_NR_1             (0x2UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000008 */

+

+#define FMC_SDCRx_MWID_Pos         (4U)

+#define FMC_SDCRx_MWID_Msk         (0x3UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000030 */

+#define FMC_SDCRx_MWID             FMC_SDCRx_MWID_Msk                          /*!<NR[1:0] bits (Number of row bits) */

+#define FMC_SDCRx_MWID_0           (0x1UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000010 */

+#define FMC_SDCRx_MWID_1           (0x2UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000020 */

+

+#define FMC_SDCRx_NB_Pos           (6U)

+#define FMC_SDCRx_NB_Msk           (0x1UL << FMC_SDCRx_NB_Pos)                 /*!< 0x00000040 */

+#define FMC_SDCRx_NB               FMC_SDCRx_NB_Msk                            /*!<Number of internal bank */

+

+#define FMC_SDCRx_CAS_Pos          (7U)

+#define FMC_SDCRx_CAS_Msk          (0x3UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000180 */

+#define FMC_SDCRx_CAS              FMC_SDCRx_CAS_Msk                           /*!<CAS[1:0] bits (CAS latency) */

+#define FMC_SDCRx_CAS_0            (0x1UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000080 */

+#define FMC_SDCRx_CAS_1            (0x2UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000100 */

+

+#define FMC_SDCRx_WP_Pos           (9U)

+#define FMC_SDCRx_WP_Msk           (0x1UL << FMC_SDCRx_WP_Pos)                 /*!< 0x00000200 */

+#define FMC_SDCRx_WP               FMC_SDCRx_WP_Msk                            /*!<Write protection */

+

+#define FMC_SDCRx_SDCLK_Pos        (10U)

+#define FMC_SDCRx_SDCLK_Msk        (0x3UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000C00 */

+#define FMC_SDCRx_SDCLK            FMC_SDCRx_SDCLK_Msk                         /*!<SDRAM clock configuration */

+#define FMC_SDCRx_SDCLK_0          (0x1UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000400 */

+#define FMC_SDCRx_SDCLK_1          (0x2UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000800 */

+

+#define FMC_SDCRx_RBURST_Pos       (12U)

+#define FMC_SDCRx_RBURST_Msk       (0x1UL << FMC_SDCRx_RBURST_Pos)             /*!< 0x00001000 */

+#define FMC_SDCRx_RBURST           FMC_SDCRx_RBURST_Msk                        /*!<Read burst */

+

+#define FMC_SDCRx_RPIPE_Pos        (13U)

+#define FMC_SDCRx_RPIPE_Msk        (0x3UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00006000 */

+#define FMC_SDCRx_RPIPE            FMC_SDCRx_RPIPE_Msk                         /*!<Write protection */

+#define FMC_SDCRx_RPIPE_0          (0x1UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00002000 */

+#define FMC_SDCRx_RPIPE_1          (0x2UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00004000 */

+

+/******************  Bit definition for FMC_SDTRx(1,2) register  ******************/

+#define FMC_SDTRx_TMRD_Pos         (0U)

+#define FMC_SDTRx_TMRD_Msk         (0xFUL << FMC_SDTRx_TMRD_Pos)               /*!< 0x0000000F */

+#define FMC_SDTRx_TMRD             FMC_SDTRx_TMRD_Msk                          /*!<TMRD[3:0] bits (Load mode register to active) */

+#define FMC_SDTRx_TMRD_0           (0x1UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000001 */

+#define FMC_SDTRx_TMRD_1           (0x2UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000002 */

+#define FMC_SDTRx_TMRD_2           (0x4UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000004 */

+#define FMC_SDTRx_TMRD_3           (0x8UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000008 */

+

+#define FMC_SDTRx_TXSR_Pos         (4U)

+#define FMC_SDTRx_TXSR_Msk         (0xFUL << FMC_SDTRx_TXSR_Pos)               /*!< 0x000000F0 */

+#define FMC_SDTRx_TXSR             FMC_SDTRx_TXSR_Msk                          /*!<TXSR[3:0] bits (Exit self refresh) */

+#define FMC_SDTRx_TXSR_0           (0x1UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000010 */

+#define FMC_SDTRx_TXSR_1           (0x2UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000020 */

+#define FMC_SDTRx_TXSR_2           (0x4UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000040 */

+#define FMC_SDTRx_TXSR_3           (0x8UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000080 */

+

+#define FMC_SDTRx_TRAS_Pos         (8U)

+#define FMC_SDTRx_TRAS_Msk         (0xFUL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000F00 */

+#define FMC_SDTRx_TRAS             FMC_SDTRx_TRAS_Msk                          /*!<TRAS[3:0] bits (Self refresh time) */

+#define FMC_SDTRx_TRAS_0           (0x1UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000100 */

+#define FMC_SDTRx_TRAS_1           (0x2UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000200 */

+#define FMC_SDTRx_TRAS_2           (0x4UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000400 */

+#define FMC_SDTRx_TRAS_3           (0x8UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000800 */

+

+#define FMC_SDTRx_TRC_Pos          (12U)

+#define FMC_SDTRx_TRC_Msk          (0xFUL << FMC_SDTRx_TRC_Pos)                /*!< 0x0000F000 */

+#define FMC_SDTRx_TRC              FMC_SDTRx_TRC_Msk                           /*!<TRC[2:0] bits (Row cycle delay) */

+#define FMC_SDTRx_TRC_0            (0x1UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00001000 */

+#define FMC_SDTRx_TRC_1            (0x2UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00002000 */

+#define FMC_SDTRx_TRC_2            (0x4UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00004000 */

+

+#define FMC_SDTRx_TWR_Pos          (16U)

+#define FMC_SDTRx_TWR_Msk          (0xFUL << FMC_SDTRx_TWR_Pos)                /*!< 0x000F0000 */

+#define FMC_SDTRx_TWR              FMC_SDTRx_TWR_Msk                           /*!<TRC[2:0] bits (Write recovery delay) */

+#define FMC_SDTRx_TWR_0            (0x1UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00010000 */

+#define FMC_SDTRx_TWR_1            (0x2UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00020000 */

+#define FMC_SDTRx_TWR_2            (0x4UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00040000 */

+

+#define FMC_SDTRx_TRP_Pos          (20U)

+#define FMC_SDTRx_TRP_Msk          (0xFUL << FMC_SDTRx_TRP_Pos)                /*!< 0x00F00000 */

+#define FMC_SDTRx_TRP              FMC_SDTRx_TRP_Msk                           /*!<TRP[2:0] bits (Row precharge delay) */

+#define FMC_SDTRx_TRP_0            (0x1UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00100000 */

+#define FMC_SDTRx_TRP_1            (0x2UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00200000 */

+#define FMC_SDTRx_TRP_2            (0x4UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00400000 */

+

+#define FMC_SDTRx_TRCD_Pos         (24U)

+#define FMC_SDTRx_TRCD_Msk         (0xFUL << FMC_SDTRx_TRCD_Pos)               /*!< 0x0F000000 */

+#define FMC_SDTRx_TRCD             FMC_SDTRx_TRCD_Msk                          /*!<TRP[2:0] bits (Row to column delay) */

+#define FMC_SDTRx_TRCD_0           (0x1UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x01000000 */

+#define FMC_SDTRx_TRCD_1           (0x2UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x02000000 */

+#define FMC_SDTRx_TRCD_2           (0x4UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x04000000 */

+

+/******************  Bit definition for FMC_SDCMR register  ******************/

+#define FMC_SDCMR_MODE_Pos         (0U)

+#define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */

+#define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */

+#define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */

+#define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */

+#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */

+

+#define FMC_SDCMR_CTB2_Pos         (3U)

+#define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */

+#define FMC_SDCMR_CTB2             FMC_SDCMR_CTB2_Msk                          /*!<Command target 2 */

+

+#define FMC_SDCMR_CTB1_Pos         (4U)

+#define FMC_SDCMR_CTB1_Msk         (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */

+#define FMC_SDCMR_CTB1             FMC_SDCMR_CTB1_Msk                          /*!<Command target 1 */

+

+#define FMC_SDCMR_NRFS_Pos         (5U)

+#define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */

+#define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!<NRFS[3:0] bits (Number of auto-refresh) */

+#define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000020 */

+#define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000040 */

+#define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000080 */

+#define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000100 */

+

+#define FMC_SDCMR_MRD_Pos          (9U)

+#define FMC_SDCMR_MRD_Msk          (0x1FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */

+#define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!<MRD[12:0] bits (Mode register definition) */

+

+/******************  Bit definition for FMC_SDRTR register  ******************/

+#define FMC_SDRTR_CRE_Pos          (0U)

+#define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */

+#define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!<Clear refresh error flag */

+

+#define FMC_SDRTR_COUNT_Pos        (1U)

+#define FMC_SDRTR_COUNT_Msk        (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */

+#define FMC_SDRTR_COUNT            FMC_SDRTR_COUNT_Msk                         /*!<COUNT[12:0] bits (Refresh timer count) */

+

+#define FMC_SDRTR_REIE_Pos         (14U)

+#define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */

+#define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!<RES interupt enable */

+

+/******************  Bit definition for FMC_SDSR register  ******************/

+#define FMC_SDSR_RE_Pos            (0U)

+#define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */

+#define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!<Refresh error flag */

+

+#define FMC_SDSR_MODES1_Pos        (1U)

+#define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */

+#define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!<MODES1[1:0]bits (Status mode for bank 1) */

+#define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000002 */

+#define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000004 */

+

+#define FMC_SDSR_MODES2_Pos        (3U)

+#define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */

+#define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!<MODES2[1:0]bits (Status mode for bank 2) */

+#define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000008 */

+#define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000010 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            General Purpose I/O                             */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bits definition for GPIO_MODER register  *****************/

+#define GPIO_MODER_MODE0_Pos           (0U)

+#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */

+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk

+#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */

+#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */

+

+#define GPIO_MODER_MODE1_Pos           (2U)

+#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */

+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk

+#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */

+#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */

+

+#define GPIO_MODER_MODE2_Pos           (4U)

+#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */

+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk

+#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */

+#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */

+

+#define GPIO_MODER_MODE3_Pos           (6U)

+#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */

+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk

+#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */

+#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */

+

+#define GPIO_MODER_MODE4_Pos           (8U)

+#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */

+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk

+#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */

+#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */

+

+#define GPIO_MODER_MODE5_Pos           (10U)

+#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */

+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk

+#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */

+#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */

+

+#define GPIO_MODER_MODE6_Pos           (12U)

+#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */

+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk

+#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */

+#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */

+

+#define GPIO_MODER_MODE7_Pos           (14U)

+#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */

+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk

+#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */

+#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */

+

+#define GPIO_MODER_MODE8_Pos           (16U)

+#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */

+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk

+#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */

+#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */

+

+#define GPIO_MODER_MODE9_Pos           (18U)

+#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */

+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk

+#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */

+#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */

+

+#define GPIO_MODER_MODE10_Pos          (20U)

+#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */

+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk

+#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */

+#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */

+

+#define GPIO_MODER_MODE11_Pos          (22U)

+#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */

+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk

+#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */

+#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */

+

+#define GPIO_MODER_MODE12_Pos          (24U)

+#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */

+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk

+#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */

+#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */

+

+#define GPIO_MODER_MODE13_Pos          (26U)

+#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */

+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk

+#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */

+#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */

+

+#define GPIO_MODER_MODE14_Pos          (28U)

+#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */

+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk

+#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */

+#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */

+

+#define GPIO_MODER_MODE15_Pos          (30U)

+#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */

+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk

+#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */

+#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_OTYPER register  ****************/

+#define GPIO_OTYPER_OT0_Pos            (0U)

+#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */

+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk

+#define GPIO_OTYPER_OT1_Pos            (1U)

+#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */

+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk

+#define GPIO_OTYPER_OT2_Pos            (2U)

+#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */

+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk

+#define GPIO_OTYPER_OT3_Pos            (3U)

+#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */

+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk

+#define GPIO_OTYPER_OT4_Pos            (4U)

+#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */

+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk

+#define GPIO_OTYPER_OT5_Pos            (5U)

+#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */

+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk

+#define GPIO_OTYPER_OT6_Pos            (6U)

+#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */

+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk

+#define GPIO_OTYPER_OT7_Pos            (7U)

+#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */

+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk

+#define GPIO_OTYPER_OT8_Pos            (8U)

+#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */

+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk

+#define GPIO_OTYPER_OT9_Pos            (9U)

+#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */

+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk

+#define GPIO_OTYPER_OT10_Pos           (10U)

+#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */

+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk

+#define GPIO_OTYPER_OT11_Pos           (11U)

+#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */

+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk

+#define GPIO_OTYPER_OT12_Pos           (12U)

+#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */

+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk

+#define GPIO_OTYPER_OT13_Pos           (13U)

+#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */

+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk

+#define GPIO_OTYPER_OT14_Pos           (14U)

+#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */

+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk

+#define GPIO_OTYPER_OT15_Pos           (15U)

+#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */

+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk

+

+/******************  Bits definition for GPIO_OSPEEDR register  ***************/

+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)

+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */

+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk

+#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */

+#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */

+

+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)

+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */

+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk

+#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */

+#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */

+

+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)

+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */

+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk

+#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */

+#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */

+

+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)

+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */

+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk

+#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */

+#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */

+

+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)

+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */

+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk

+#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */

+#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */

+

+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)

+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */

+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk

+#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */

+#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */

+

+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)

+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */

+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk

+#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */

+#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */

+

+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)

+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */

+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk

+#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */

+#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */

+

+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)

+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */

+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk

+#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */

+#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */

+

+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)

+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */

+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk

+#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */

+#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */

+

+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)

+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */

+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk

+#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */

+#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */

+

+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)

+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */

+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk

+#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */

+#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */

+

+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)

+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */

+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk

+#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */

+#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */

+

+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)

+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */

+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk

+#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */

+#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */

+

+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)

+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */

+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk

+#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */

+#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */

+

+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)

+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */

+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk

+#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */

+#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_PUPDR register  *****************/

+#define GPIO_PUPDR_PUPD0_Pos           (0U)

+#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */

+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk

+#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */

+#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */

+

+#define GPIO_PUPDR_PUPD1_Pos           (2U)

+#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */

+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk

+#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */

+#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */

+

+#define GPIO_PUPDR_PUPD2_Pos           (4U)

+#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */

+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk

+#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */

+#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */

+

+#define GPIO_PUPDR_PUPD3_Pos           (6U)

+#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */

+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk

+#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */

+#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */

+

+#define GPIO_PUPDR_PUPD4_Pos           (8U)

+#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */

+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk

+#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */

+#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */

+

+#define GPIO_PUPDR_PUPD5_Pos           (10U)

+#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */

+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk

+#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */

+#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */

+

+#define GPIO_PUPDR_PUPD6_Pos           (12U)

+#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */

+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk

+#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */

+#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */

+

+#define GPIO_PUPDR_PUPD7_Pos           (14U)

+#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */

+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk

+#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */

+#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */

+

+#define GPIO_PUPDR_PUPD8_Pos           (16U)

+#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */

+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk

+#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */

+#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */

+

+#define GPIO_PUPDR_PUPD9_Pos           (18U)

+#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */

+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk

+#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */

+#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */

+

+#define GPIO_PUPDR_PUPD10_Pos          (20U)

+#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */

+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk

+#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */

+#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */

+

+#define GPIO_PUPDR_PUPD11_Pos          (22U)

+#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */

+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk

+#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */

+#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */

+

+#define GPIO_PUPDR_PUPD12_Pos          (24U)

+#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */

+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk

+#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */

+#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */

+

+#define GPIO_PUPDR_PUPD13_Pos          (26U)

+#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */

+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk

+#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */

+#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */

+

+#define GPIO_PUPDR_PUPD14_Pos          (28U)

+#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */

+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk

+#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */

+#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */

+

+#define GPIO_PUPDR_PUPD15_Pos          (30U)

+#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */

+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk

+#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */

+#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_IDR register  *******************/

+#define GPIO_IDR_ID0_Pos               (0U)

+#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */

+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk

+#define GPIO_IDR_ID1_Pos               (1U)

+#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */

+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk

+#define GPIO_IDR_ID2_Pos               (2U)

+#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */

+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk

+#define GPIO_IDR_ID3_Pos               (3U)

+#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */

+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk

+#define GPIO_IDR_ID4_Pos               (4U)

+#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */

+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk

+#define GPIO_IDR_ID5_Pos               (5U)

+#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */

+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk

+#define GPIO_IDR_ID6_Pos               (6U)

+#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */

+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk

+#define GPIO_IDR_ID7_Pos               (7U)

+#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */

+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk

+#define GPIO_IDR_ID8_Pos               (8U)

+#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */

+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk

+#define GPIO_IDR_ID9_Pos               (9U)

+#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */

+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk

+#define GPIO_IDR_ID10_Pos              (10U)

+#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */

+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk

+#define GPIO_IDR_ID11_Pos              (11U)

+#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */

+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk

+#define GPIO_IDR_ID12_Pos              (12U)

+#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */

+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk

+#define GPIO_IDR_ID13_Pos              (13U)

+#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */

+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk

+#define GPIO_IDR_ID14_Pos              (14U)

+#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */

+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk

+#define GPIO_IDR_ID15_Pos              (15U)

+#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */

+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk

+

+/******************  Bits definition for GPIO_ODR register  *******************/

+#define GPIO_ODR_OD0_Pos               (0U)

+#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */

+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk

+#define GPIO_ODR_OD1_Pos               (1U)

+#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */

+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk

+#define GPIO_ODR_OD2_Pos               (2U)

+#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */

+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk

+#define GPIO_ODR_OD3_Pos               (3U)

+#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */

+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk

+#define GPIO_ODR_OD4_Pos               (4U)

+#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */

+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk

+#define GPIO_ODR_OD5_Pos               (5U)

+#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */

+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk

+#define GPIO_ODR_OD6_Pos               (6U)

+#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */

+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk

+#define GPIO_ODR_OD7_Pos               (7U)

+#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */

+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk

+#define GPIO_ODR_OD8_Pos               (8U)

+#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */

+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk

+#define GPIO_ODR_OD9_Pos               (9U)

+#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */

+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk

+#define GPIO_ODR_OD10_Pos              (10U)

+#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */

+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk

+#define GPIO_ODR_OD11_Pos              (11U)

+#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */

+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk

+#define GPIO_ODR_OD12_Pos              (12U)

+#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */

+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk

+#define GPIO_ODR_OD13_Pos              (13U)

+#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */

+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk

+#define GPIO_ODR_OD14_Pos              (14U)

+#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */

+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk

+#define GPIO_ODR_OD15_Pos              (15U)

+#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */

+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk

+

+/******************  Bits definition for GPIO_BSRR register  ******************/

+#define GPIO_BSRR_BS0_Pos              (0U)

+#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */

+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk

+#define GPIO_BSRR_BS1_Pos              (1U)

+#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */

+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk

+#define GPIO_BSRR_BS2_Pos              (2U)

+#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */

+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk

+#define GPIO_BSRR_BS3_Pos              (3U)

+#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */

+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk

+#define GPIO_BSRR_BS4_Pos              (4U)

+#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */

+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk

+#define GPIO_BSRR_BS5_Pos              (5U)

+#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */

+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk

+#define GPIO_BSRR_BS6_Pos              (6U)

+#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */

+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk

+#define GPIO_BSRR_BS7_Pos              (7U)

+#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */

+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk

+#define GPIO_BSRR_BS8_Pos              (8U)

+#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */

+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk

+#define GPIO_BSRR_BS9_Pos              (9U)

+#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */

+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk

+#define GPIO_BSRR_BS10_Pos             (10U)

+#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */

+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk

+#define GPIO_BSRR_BS11_Pos             (11U)

+#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */

+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk

+#define GPIO_BSRR_BS12_Pos             (12U)

+#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */

+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk

+#define GPIO_BSRR_BS13_Pos             (13U)

+#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */

+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk

+#define GPIO_BSRR_BS14_Pos             (14U)

+#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */

+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk

+#define GPIO_BSRR_BS15_Pos             (15U)

+#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */

+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk

+#define GPIO_BSRR_BR0_Pos              (16U)

+#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */

+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk

+#define GPIO_BSRR_BR1_Pos              (17U)

+#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */

+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk

+#define GPIO_BSRR_BR2_Pos              (18U)

+#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */

+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk

+#define GPIO_BSRR_BR3_Pos              (19U)

+#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */

+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk

+#define GPIO_BSRR_BR4_Pos              (20U)

+#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */

+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk

+#define GPIO_BSRR_BR5_Pos              (21U)

+#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */

+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk

+#define GPIO_BSRR_BR6_Pos              (22U)

+#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */

+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk

+#define GPIO_BSRR_BR7_Pos              (23U)

+#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */

+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk

+#define GPIO_BSRR_BR8_Pos              (24U)

+#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */

+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk

+#define GPIO_BSRR_BR9_Pos              (25U)

+#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */

+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk

+#define GPIO_BSRR_BR10_Pos             (26U)

+#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */

+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk

+#define GPIO_BSRR_BR11_Pos             (27U)

+#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */

+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk

+#define GPIO_BSRR_BR12_Pos             (28U)

+#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */

+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk

+#define GPIO_BSRR_BR13_Pos             (29U)

+#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */

+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk

+#define GPIO_BSRR_BR14_Pos             (30U)

+#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */

+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk

+#define GPIO_BSRR_BR15_Pos             (31U)

+#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */

+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk

+

+/****************** Bit definition for GPIO_LCKR register *********************/

+#define GPIO_LCKR_LCK0_Pos             (0U)

+#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */

+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk

+#define GPIO_LCKR_LCK1_Pos             (1U)

+#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */

+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk

+#define GPIO_LCKR_LCK2_Pos             (2U)

+#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */

+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk

+#define GPIO_LCKR_LCK3_Pos             (3U)

+#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */

+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk

+#define GPIO_LCKR_LCK4_Pos             (4U)

+#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */

+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk

+#define GPIO_LCKR_LCK5_Pos             (5U)

+#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */

+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk

+#define GPIO_LCKR_LCK6_Pos             (6U)

+#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */

+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk

+#define GPIO_LCKR_LCK7_Pos             (7U)

+#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */

+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk

+#define GPIO_LCKR_LCK8_Pos             (8U)

+#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */

+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk

+#define GPIO_LCKR_LCK9_Pos             (9U)

+#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */

+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk

+#define GPIO_LCKR_LCK10_Pos            (10U)

+#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */

+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk

+#define GPIO_LCKR_LCK11_Pos            (11U)

+#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */

+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk

+#define GPIO_LCKR_LCK12_Pos            (12U)

+#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */

+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk

+#define GPIO_LCKR_LCK13_Pos            (13U)

+#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */

+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk

+#define GPIO_LCKR_LCK14_Pos            (14U)

+#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */

+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk

+#define GPIO_LCKR_LCK15_Pos            (15U)

+#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */

+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk

+#define GPIO_LCKR_LCKK_Pos             (16U)

+#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */

+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk

+

+/****************** Bit definition for GPIO_AFRL register  ********************/

+#define GPIO_AFRL_AFSEL0_Pos           (0U)

+#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */

+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk

+#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */

+#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */

+#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */

+#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */

+#define GPIO_AFRL_AFSEL1_Pos           (4U)

+#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */

+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk

+#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */

+#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */

+#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */

+#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */

+#define GPIO_AFRL_AFSEL2_Pos           (8U)

+#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */

+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk

+#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */

+#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */

+#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */

+#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */

+#define GPIO_AFRL_AFSEL3_Pos           (12U)

+#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */

+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk

+#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */

+#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */

+#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */

+#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */

+#define GPIO_AFRL_AFSEL4_Pos           (16U)

+#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */

+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk

+#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */

+#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */

+#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */

+#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */

+#define GPIO_AFRL_AFSEL5_Pos           (20U)

+#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */

+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk

+#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */

+#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */

+#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */

+#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */

+#define GPIO_AFRL_AFSEL6_Pos           (24U)

+#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */

+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk

+#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */

+#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */

+#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */

+#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */

+#define GPIO_AFRL_AFSEL7_Pos           (28U)

+#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */

+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk

+#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */

+#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */

+#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */

+#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */

+

+/* Legacy defines */

+#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0

+#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1

+#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2

+#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3

+#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4

+#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5

+#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6

+#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7

+

+/****************** Bit definition for GPIO_AFRH register  ********************/

+#define GPIO_AFRH_AFSEL8_Pos           (0U)

+#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */

+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk

+#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */

+#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */

+#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */

+#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */

+#define GPIO_AFRH_AFSEL9_Pos           (4U)

+#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */

+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk

+#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */

+#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */

+#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */

+#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */

+#define GPIO_AFRH_AFSEL10_Pos          (8U)

+#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */

+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk

+#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */

+#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */

+#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */

+#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */

+#define GPIO_AFRH_AFSEL11_Pos          (12U)

+#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */

+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk

+#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */

+#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */

+#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */

+#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */

+#define GPIO_AFRH_AFSEL12_Pos          (16U)

+#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */

+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk

+#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */

+#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */

+#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */

+#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */

+#define GPIO_AFRH_AFSEL13_Pos          (20U)

+#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */

+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk

+#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */

+#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */

+#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */

+#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */

+#define GPIO_AFRH_AFSEL14_Pos          (24U)

+#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */

+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk

+#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */

+#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */

+#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */

+#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */

+#define GPIO_AFRH_AFSEL15_Pos          (28U)

+#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */

+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk

+#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */

+#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */

+#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */

+#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */

+

+/* Legacy defines */

+#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8

+#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9

+#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10

+#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11

+#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12

+#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13

+#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14

+#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15

+

+/******************************************************************************/

+/*                                                                            */

+/*                        HSEM HW Semaphore                                   */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for HSEM_R register  ********************/

+#define HSEM_R_PROCID_Pos         (0U)

+#define HSEM_R_PROCID_Msk         (0xFFUL << HSEM_R_PROCID_Pos)                /*!< 0x000000FF */

+#define HSEM_R_PROCID             HSEM_R_PROCID_Msk                            /*!<Semaphore ProcessID */

+#define HSEM_R_COREID_Pos         (8U)

+#define HSEM_R_COREID_Msk         (0xFFUL << HSEM_R_COREID_Pos)                /*!< 0x0000FF00 */

+#define HSEM_R_COREID             HSEM_R_COREID_Msk                            /*!<Semaphore CoreID.   */

+#define HSEM_R_LOCK_Pos           (31U)

+#define HSEM_R_LOCK_Msk           (0x1UL << HSEM_R_LOCK_Pos)                   /*!< 0x80000000 */

+#define HSEM_R_LOCK               HSEM_R_LOCK_Msk                              /*!<Lock indication.    */

+

+/********************  Bit definition for HSEM_RLR register  ******************/

+#define HSEM_RLR_PROCID_Pos       (0U)

+#define HSEM_RLR_PROCID_Msk       (0xFFUL << HSEM_RLR_PROCID_Pos)              /*!< 0x000000FF */

+#define HSEM_RLR_PROCID           HSEM_RLR_PROCID_Msk                          /*!<Semaphore ProcessID */

+#define HSEM_RLR_COREID_Pos       (8U)

+#define HSEM_RLR_COREID_Msk       (0xFFUL << HSEM_RLR_COREID_Pos)              /*!< 0x0000FF00 */

+#define HSEM_RLR_COREID           HSEM_RLR_COREID_Msk                          /*!<Semaphore CoreID.   */

+#define HSEM_RLR_LOCK_Pos         (31U)

+#define HSEM_RLR_LOCK_Msk         (0x1UL << HSEM_RLR_LOCK_Pos)                 /*!< 0x80000000 */

+#define HSEM_RLR_LOCK             HSEM_RLR_LOCK_Msk                            /*!<Lock indication.    */

+

+/********************  Bit definition for HSEM_C1IER register  *****************/

+#define HSEM_C1IER_ISE0_Pos       (0U)

+#define HSEM_C1IER_ISE0_Msk       (0x1UL << HSEM_C1IER_ISE0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1IER_ISE0           HSEM_C1IER_ISE0_Msk                          /*!<semaphore 0 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE1_Pos       (1U)

+#define HSEM_C1IER_ISE1_Msk       (0x1UL << HSEM_C1IER_ISE1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1IER_ISE1           HSEM_C1IER_ISE1_Msk                          /*!<semaphore 1 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE2_Pos       (2U)

+#define HSEM_C1IER_ISE2_Msk       (0x1UL << HSEM_C1IER_ISE2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1IER_ISE2           HSEM_C1IER_ISE2_Msk                          /*!<semaphore 2 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE3_Pos       (3U)

+#define HSEM_C1IER_ISE3_Msk       (0x1UL << HSEM_C1IER_ISE3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1IER_ISE3           HSEM_C1IER_ISE3_Msk                          /*!<semaphore 3 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE4_Pos       (4U)

+#define HSEM_C1IER_ISE4_Msk       (0x1UL << HSEM_C1IER_ISE4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1IER_ISE4           HSEM_C1IER_ISE4_Msk                          /*!<semaphore 4 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE5_Pos       (5U)

+#define HSEM_C1IER_ISE5_Msk       (0x1UL << HSEM_C1IER_ISE5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1IER_ISE5           HSEM_C1IER_ISE5_Msk                          /*!<semaphore 5 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE6_Pos       (6U)

+#define HSEM_C1IER_ISE6_Msk       (0x1UL << HSEM_C1IER_ISE6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1IER_ISE6           HSEM_C1IER_ISE6_Msk                          /*!<semaphore 6 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE7_Pos       (7U)

+#define HSEM_C1IER_ISE7_Msk       (0x1UL << HSEM_C1IER_ISE7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1IER_ISE7           HSEM_C1IER_ISE7_Msk                          /*!<semaphore 7 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE8_Pos       (8U)

+#define HSEM_C1IER_ISE8_Msk       (0x1UL << HSEM_C1IER_ISE8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1IER_ISE8           HSEM_C1IER_ISE8_Msk                          /*!<semaphore 8 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE9_Pos       (9U)

+#define HSEM_C1IER_ISE9_Msk       (0x1UL << HSEM_C1IER_ISE9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1IER_ISE9           HSEM_C1IER_ISE9_Msk                          /*!<semaphore 9 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE10_Pos      (10U)

+#define HSEM_C1IER_ISE10_Msk      (0x1UL << HSEM_C1IER_ISE10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1IER_ISE10          HSEM_C1IER_ISE10_Msk                         /*!<semaphore 10 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE11_Pos      (11U)

+#define HSEM_C1IER_ISE11_Msk      (0x1UL << HSEM_C1IER_ISE11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1IER_ISE11          HSEM_C1IER_ISE11_Msk                         /*!<semaphore 11 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE12_Pos      (12U)

+#define HSEM_C1IER_ISE12_Msk      (0x1UL << HSEM_C1IER_ISE12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1IER_ISE12          HSEM_C1IER_ISE12_Msk                         /*!<semaphore 12 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE13_Pos      (13U)

+#define HSEM_C1IER_ISE13_Msk      (0x1UL << HSEM_C1IER_ISE13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1IER_ISE13          HSEM_C1IER_ISE13_Msk                         /*!<semaphore 13 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE14_Pos      (14U)

+#define HSEM_C1IER_ISE14_Msk      (0x1UL << HSEM_C1IER_ISE14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1IER_ISE14          HSEM_C1IER_ISE14_Msk                         /*!<semaphore 14 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE15_Pos      (15U)

+#define HSEM_C1IER_ISE15_Msk      (0x1UL << HSEM_C1IER_ISE15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1IER_ISE15          HSEM_C1IER_ISE15_Msk                         /*!<semaphore 15 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE16_Pos      (16U)

+#define HSEM_C1IER_ISE16_Msk      (0x1UL << HSEM_C1IER_ISE16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1IER_ISE16          HSEM_C1IER_ISE16_Msk                         /*!<semaphore 16 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE17_Pos      (17U)

+#define HSEM_C1IER_ISE17_Msk      (0x1UL << HSEM_C1IER_ISE17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1IER_ISE17          HSEM_C1IER_ISE17_Msk                         /*!<semaphore 17 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE18_Pos      (18U)

+#define HSEM_C1IER_ISE18_Msk      (0x1UL << HSEM_C1IER_ISE18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1IER_ISE18          HSEM_C1IER_ISE18_Msk                         /*!<semaphore 18 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE19_Pos      (19U)

+#define HSEM_C1IER_ISE19_Msk      (0x1UL << HSEM_C1IER_ISE19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1IER_ISE19          HSEM_C1IER_ISE19_Msk                         /*!<semaphore 19 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE20_Pos      (20U)

+#define HSEM_C1IER_ISE20_Msk      (0x1UL << HSEM_C1IER_ISE20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1IER_ISE20          HSEM_C1IER_ISE20_Msk                         /*!<semaphore 20 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE21_Pos      (21U)

+#define HSEM_C1IER_ISE21_Msk      (0x1UL << HSEM_C1IER_ISE21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1IER_ISE21          HSEM_C1IER_ISE21_Msk                         /*!<semaphore 21 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE22_Pos      (22U)

+#define HSEM_C1IER_ISE22_Msk      (0x1UL << HSEM_C1IER_ISE22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1IER_ISE22          HSEM_C1IER_ISE22_Msk                         /*!<semaphore 22 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE23_Pos      (23U)

+#define HSEM_C1IER_ISE23_Msk      (0x1UL << HSEM_C1IER_ISE23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1IER_ISE23          HSEM_C1IER_ISE23_Msk                         /*!<semaphore 23 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE24_Pos      (24U)

+#define HSEM_C1IER_ISE24_Msk      (0x1UL << HSEM_C1IER_ISE24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1IER_ISE24          HSEM_C1IER_ISE24_Msk                         /*!<semaphore 24 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE25_Pos      (25U)

+#define HSEM_C1IER_ISE25_Msk      (0x1UL << HSEM_C1IER_ISE25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1IER_ISE25          HSEM_C1IER_ISE25_Msk                         /*!<semaphore 25 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE26_Pos      (26U)

+#define HSEM_C1IER_ISE26_Msk      (0x1UL << HSEM_C1IER_ISE26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1IER_ISE26          HSEM_C1IER_ISE26_Msk                         /*!<semaphore 26 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE27_Pos      (27U)

+#define HSEM_C1IER_ISE27_Msk      (0x1UL << HSEM_C1IER_ISE27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1IER_ISE27          HSEM_C1IER_ISE27_Msk                         /*!<semaphore 27 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE28_Pos      (28U)

+#define HSEM_C1IER_ISE28_Msk      (0x1UL << HSEM_C1IER_ISE28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1IER_ISE28          HSEM_C1IER_ISE28_Msk                         /*!<semaphore 28 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE29_Pos      (29U)

+#define HSEM_C1IER_ISE29_Msk      (0x1UL << HSEM_C1IER_ISE29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1IER_ISE29          HSEM_C1IER_ISE29_Msk                         /*!<semaphore 29 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE30_Pos      (30U)

+#define HSEM_C1IER_ISE30_Msk      (0x1UL << HSEM_C1IER_ISE30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1IER_ISE30          HSEM_C1IER_ISE30_Msk                         /*!<semaphore 30 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE31_Pos      (31U)

+#define HSEM_C1IER_ISE31_Msk      (0x1UL << HSEM_C1IER_ISE31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1IER_ISE31          HSEM_C1IER_ISE31_Msk                         /*!<semaphore 31 interrupt 0 enable bit. */

+

+/********************  Bit definition for HSEM_C1ICR register  *****************/

+#define HSEM_C1ICR_ISC0_Pos       (0U)

+#define HSEM_C1ICR_ISC0_Msk       (0x1UL << HSEM_C1ICR_ISC0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1ICR_ISC0           HSEM_C1ICR_ISC0_Msk                          /*!<semaphore 0 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC1_Pos       (1U)

+#define HSEM_C1ICR_ISC1_Msk       (0x1UL << HSEM_C1ICR_ISC1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1ICR_ISC1           HSEM_C1ICR_ISC1_Msk                          /*!<semaphore 1 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC2_Pos       (2U)

+#define HSEM_C1ICR_ISC2_Msk       (0x1UL << HSEM_C1ICR_ISC2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1ICR_ISC2           HSEM_C1ICR_ISC2_Msk                          /*!<semaphore 2 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC3_Pos       (3U)

+#define HSEM_C1ICR_ISC3_Msk       (0x1UL << HSEM_C1ICR_ISC3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1ICR_ISC3           HSEM_C1ICR_ISC3_Msk                          /*!<semaphore 3 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC4_Pos       (4U)

+#define HSEM_C1ICR_ISC4_Msk       (0x1UL << HSEM_C1ICR_ISC4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1ICR_ISC4           HSEM_C1ICR_ISC4_Msk                          /*!<semaphore 4 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC5_Pos       (5U)

+#define HSEM_C1ICR_ISC5_Msk       (0x1UL << HSEM_C1ICR_ISC5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1ICR_ISC5           HSEM_C1ICR_ISC5_Msk                          /*!<semaphore 5 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC6_Pos       (6U)

+#define HSEM_C1ICR_ISC6_Msk       (0x1UL << HSEM_C1ICR_ISC6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1ICR_ISC6           HSEM_C1ICR_ISC6_Msk                          /*!<semaphore 6 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC7_Pos       (7U)

+#define HSEM_C1ICR_ISC7_Msk       (0x1UL << HSEM_C1ICR_ISC7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1ICR_ISC7           HSEM_C1ICR_ISC7_Msk                          /*!<semaphore 7 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC8_Pos       (8U)

+#define HSEM_C1ICR_ISC8_Msk       (0x1UL << HSEM_C1ICR_ISC8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1ICR_ISC8           HSEM_C1ICR_ISC8_Msk                          /*!<semaphore 8 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC9_Pos       (9U)

+#define HSEM_C1ICR_ISC9_Msk       (0x1UL << HSEM_C1ICR_ISC9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1ICR_ISC9           HSEM_C1ICR_ISC9_Msk                          /*!<semaphore 9 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC10_Pos      (10U)

+#define HSEM_C1ICR_ISC10_Msk      (0x1UL << HSEM_C1ICR_ISC10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1ICR_ISC10          HSEM_C1ICR_ISC10_Msk                         /*!<semaphore 10 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC11_Pos      (11U)

+#define HSEM_C1ICR_ISC11_Msk      (0x1UL << HSEM_C1ICR_ISC11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1ICR_ISC11          HSEM_C1ICR_ISC11_Msk                         /*!<semaphore 11 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC12_Pos      (12U)

+#define HSEM_C1ICR_ISC12_Msk      (0x1UL << HSEM_C1ICR_ISC12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1ICR_ISC12          HSEM_C1ICR_ISC12_Msk                         /*!<semaphore 12 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC13_Pos      (13U)

+#define HSEM_C1ICR_ISC13_Msk      (0x1UL << HSEM_C1ICR_ISC13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1ICR_ISC13          HSEM_C1ICR_ISC13_Msk                         /*!<semaphore 13 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC14_Pos      (14U)

+#define HSEM_C1ICR_ISC14_Msk      (0x1UL << HSEM_C1ICR_ISC14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1ICR_ISC14          HSEM_C1ICR_ISC14_Msk                         /*!<semaphore 14 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC15_Pos      (15U)

+#define HSEM_C1ICR_ISC15_Msk      (0x1UL << HSEM_C1ICR_ISC15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1ICR_ISC15          HSEM_C1ICR_ISC15_Msk                         /*!<semaphore 15 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC16_Pos      (16U)

+#define HSEM_C1ICR_ISC16_Msk      (0x1UL << HSEM_C1ICR_ISC16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1ICR_ISC16          HSEM_C1ICR_ISC16_Msk                         /*!<semaphore 16 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC17_Pos      (17U)

+#define HSEM_C1ICR_ISC17_Msk      (0x1UL << HSEM_C1ICR_ISC17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1ICR_ISC17          HSEM_C1ICR_ISC17_Msk                         /*!<semaphore 17 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC18_Pos      (18U)

+#define HSEM_C1ICR_ISC18_Msk      (0x1UL << HSEM_C1ICR_ISC18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1ICR_ISC18          HSEM_C1ICR_ISC18_Msk                         /*!<semaphore 18 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC19_Pos      (19U)

+#define HSEM_C1ICR_ISC19_Msk      (0x1UL << HSEM_C1ICR_ISC19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1ICR_ISC19          HSEM_C1ICR_ISC19_Msk                         /*!<semaphore 19 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC20_Pos      (20U)

+#define HSEM_C1ICR_ISC20_Msk      (0x1UL << HSEM_C1ICR_ISC20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1ICR_ISC20          HSEM_C1ICR_ISC20_Msk                         /*!<semaphore 20 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC21_Pos      (21U)

+#define HSEM_C1ICR_ISC21_Msk      (0x1UL << HSEM_C1ICR_ISC21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1ICR_ISC21          HSEM_C1ICR_ISC21_Msk                         /*!<semaphore 21 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC22_Pos      (22U)

+#define HSEM_C1ICR_ISC22_Msk      (0x1UL << HSEM_C1ICR_ISC22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1ICR_ISC22          HSEM_C1ICR_ISC22_Msk                         /*!<semaphore 22 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC23_Pos      (23U)

+#define HSEM_C1ICR_ISC23_Msk      (0x1UL << HSEM_C1ICR_ISC23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1ICR_ISC23          HSEM_C1ICR_ISC23_Msk                         /*!<semaphore 23 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC24_Pos      (24U)

+#define HSEM_C1ICR_ISC24_Msk      (0x1UL << HSEM_C1ICR_ISC24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1ICR_ISC24          HSEM_C1ICR_ISC24_Msk                         /*!<semaphore 24 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC25_Pos      (25U)

+#define HSEM_C1ICR_ISC25_Msk      (0x1UL << HSEM_C1ICR_ISC25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1ICR_ISC25          HSEM_C1ICR_ISC25_Msk                         /*!<semaphore 25 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC26_Pos      (26U)

+#define HSEM_C1ICR_ISC26_Msk      (0x1UL << HSEM_C1ICR_ISC26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1ICR_ISC26          HSEM_C1ICR_ISC26_Msk                         /*!<semaphore 26 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC27_Pos      (27U)

+#define HSEM_C1ICR_ISC27_Msk      (0x1UL << HSEM_C1ICR_ISC27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1ICR_ISC27          HSEM_C1ICR_ISC27_Msk                         /*!<semaphore 27 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC28_Pos      (28U)

+#define HSEM_C1ICR_ISC28_Msk      (0x1UL << HSEM_C1ICR_ISC28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1ICR_ISC28          HSEM_C1ICR_ISC28_Msk                         /*!<semaphore 28 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC29_Pos      (29U)

+#define HSEM_C1ICR_ISC29_Msk      (0x1UL << HSEM_C1ICR_ISC29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1ICR_ISC29          HSEM_C1ICR_ISC29_Msk                         /*!<semaphore 29 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC30_Pos      (30U)

+#define HSEM_C1ICR_ISC30_Msk      (0x1UL << HSEM_C1ICR_ISC30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1ICR_ISC30          HSEM_C1ICR_ISC30_Msk                         /*!<semaphore 30 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC31_Pos      (31U)

+#define HSEM_C1ICR_ISC31_Msk      (0x1UL << HSEM_C1ICR_ISC31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1ICR_ISC31          HSEM_C1ICR_ISC31_Msk                         /*!<semaphore 31 interrupt 0 clear bit. */

+

+/********************  Bit definition for HSEM_C1ISR register  *****************/

+#define HSEM_C1ISR_ISF0_Pos       (0U)

+#define HSEM_C1ISR_ISF0_Msk       (0x1UL << HSEM_C1ISR_ISF0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1ISR_ISF0           HSEM_C1ISR_ISF0_Msk                          /*!<semaphore 0 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF1_Pos       (1U)

+#define HSEM_C1ISR_ISF1_Msk       (0x1UL << HSEM_C1ISR_ISF1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1ISR_ISF1           HSEM_C1ISR_ISF1_Msk                          /*!<semaphore 1 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF2_Pos       (2U)

+#define HSEM_C1ISR_ISF2_Msk       (0x1UL << HSEM_C1ISR_ISF2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1ISR_ISF2           HSEM_C1ISR_ISF2_Msk                          /*!<semaphore 2 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF3_Pos       (3U)

+#define HSEM_C1ISR_ISF3_Msk       (0x1UL << HSEM_C1ISR_ISF3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1ISR_ISF3           HSEM_C1ISR_ISF3_Msk                          /*!<semaphore 3 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF4_Pos       (4U)

+#define HSEM_C1ISR_ISF4_Msk       (0x1UL << HSEM_C1ISR_ISF4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1ISR_ISF4           HSEM_C1ISR_ISF4_Msk                          /*!<semaphore 4 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF5_Pos       (5U)

+#define HSEM_C1ISR_ISF5_Msk       (0x1UL << HSEM_C1ISR_ISF5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1ISR_ISF5           HSEM_C1ISR_ISF5_Msk                          /*!<semaphore 5 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF6_Pos       (6U)

+#define HSEM_C1ISR_ISF6_Msk       (0x1UL << HSEM_C1ISR_ISF6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1ISR_ISF6           HSEM_C1ISR_ISF6_Msk                          /*!<semaphore 6 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF7_Pos       (7U)

+#define HSEM_C1ISR_ISF7_Msk       (0x1UL << HSEM_C1ISR_ISF7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1ISR_ISF7           HSEM_C1ISR_ISF7_Msk                          /*!<semaphore 7 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF8_Pos       (8U)

+#define HSEM_C1ISR_ISF8_Msk       (0x1UL << HSEM_C1ISR_ISF8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1ISR_ISF8           HSEM_C1ISR_ISF8_Msk                          /*!<semaphore 8 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF9_Pos       (9U)

+#define HSEM_C1ISR_ISF9_Msk       (0x1UL << HSEM_C1ISR_ISF9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1ISR_ISF9           HSEM_C1ISR_ISF9_Msk                          /*!<semaphore 9 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF10_Pos      (10U)

+#define HSEM_C1ISR_ISF10_Msk      (0x1UL << HSEM_C1ISR_ISF10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1ISR_ISF10          HSEM_C1ISR_ISF10_Msk                         /*!<semaphore 10 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF11_Pos      (11U)

+#define HSEM_C1ISR_ISF11_Msk      (0x1UL << HSEM_C1ISR_ISF11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1ISR_ISF11          HSEM_C1ISR_ISF11_Msk                         /*!<semaphore 11 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF12_Pos      (12U)

+#define HSEM_C1ISR_ISF12_Msk      (0x1UL << HSEM_C1ISR_ISF12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1ISR_ISF12          HSEM_C1ISR_ISF12_Msk                         /*!<semaphore 12 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF13_Pos      (13U)

+#define HSEM_C1ISR_ISF13_Msk      (0x1UL << HSEM_C1ISR_ISF13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1ISR_ISF13          HSEM_C1ISR_ISF13_Msk                         /*!<semaphore 13 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF14_Pos      (14U)

+#define HSEM_C1ISR_ISF14_Msk      (0x1UL << HSEM_C1ISR_ISF14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1ISR_ISF14          HSEM_C1ISR_ISF14_Msk                         /*!<semaphore 14 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF15_Pos      (15U)

+#define HSEM_C1ISR_ISF15_Msk      (0x1UL << HSEM_C1ISR_ISF15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1ISR_ISF15          HSEM_C1ISR_ISF15_Msk                         /*!<semaphore 15 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF16_Pos      (16U)

+#define HSEM_C1ISR_ISF16_Msk      (0x1UL << HSEM_C1ISR_ISF16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1ISR_ISF16          HSEM_C1ISR_ISF16_Msk                         /*!<semaphore 16 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF17_Pos      (17U)

+#define HSEM_C1ISR_ISF17_Msk      (0x1UL << HSEM_C1ISR_ISF17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1ISR_ISF17          HSEM_C1ISR_ISF17_Msk                         /*!<semaphore 17 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF18_Pos      (18U)

+#define HSEM_C1ISR_ISF18_Msk      (0x1UL << HSEM_C1ISR_ISF18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1ISR_ISF18          HSEM_C1ISR_ISF18_Msk                         /*!<semaphore 18 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF19_Pos      (19U)

+#define HSEM_C1ISR_ISF19_Msk      (0x1UL << HSEM_C1ISR_ISF19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1ISR_ISF19          HSEM_C1ISR_ISF19_Msk                         /*!<semaphore 19 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF20_Pos      (20U)

+#define HSEM_C1ISR_ISF20_Msk      (0x1UL << HSEM_C1ISR_ISF20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1ISR_ISF20          HSEM_C1ISR_ISF20_Msk                         /*!<semaphore 20 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF21_Pos      (21U)

+#define HSEM_C1ISR_ISF21_Msk      (0x1UL << HSEM_C1ISR_ISF21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1ISR_ISF21          HSEM_C1ISR_ISF21_Msk                         /*!<semaphore 21 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF22_Pos      (22U)

+#define HSEM_C1ISR_ISF22_Msk      (0x1UL << HSEM_C1ISR_ISF22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1ISR_ISF22          HSEM_C1ISR_ISF22_Msk                         /*!<semaphore 22 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF23_Pos      (23U)

+#define HSEM_C1ISR_ISF23_Msk      (0x1UL << HSEM_C1ISR_ISF23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1ISR_ISF23          HSEM_C1ISR_ISF23_Msk                         /*!<semaphore 23 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF24_Pos      (24U)

+#define HSEM_C1ISR_ISF24_Msk      (0x1UL << HSEM_C1ISR_ISF24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1ISR_ISF24          HSEM_C1ISR_ISF24_Msk                         /*!<semaphore 24 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF25_Pos      (25U)

+#define HSEM_C1ISR_ISF25_Msk      (0x1UL << HSEM_C1ISR_ISF25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1ISR_ISF25          HSEM_C1ISR_ISF25_Msk                         /*!<semaphore 25 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF26_Pos      (26U)

+#define HSEM_C1ISR_ISF26_Msk      (0x1UL << HSEM_C1ISR_ISF26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1ISR_ISF26          HSEM_C1ISR_ISF26_Msk                         /*!<semaphore 26 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF27_Pos      (27U)

+#define HSEM_C1ISR_ISF27_Msk      (0x1UL << HSEM_C1ISR_ISF27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1ISR_ISF27          HSEM_C1ISR_ISF27_Msk                         /*!<semaphore 27 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF28_Pos      (28U)

+#define HSEM_C1ISR_ISF28_Msk      (0x1UL << HSEM_C1ISR_ISF28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1ISR_ISF28          HSEM_C1ISR_ISF28_Msk                         /*!<semaphore 28 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF29_Pos      (29U)

+#define HSEM_C1ISR_ISF29_Msk      (0x1UL << HSEM_C1ISR_ISF29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1ISR_ISF29          HSEM_C1ISR_ISF29_Msk                         /*!<semaphore 29 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF30_Pos      (30U)

+#define HSEM_C1ISR_ISF30_Msk      (0x1UL << HSEM_C1ISR_ISF30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1ISR_ISF30          HSEM_C1ISR_ISF30_Msk                         /*!<semaphore 30 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF31_Pos      (31U)

+#define HSEM_C1ISR_ISF31_Msk      (0x1UL << HSEM_C1ISR_ISF31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1ISR_ISF31          HSEM_C1ISR_ISF31_Msk                         /*!<semaphore 31 interrupt 0 status bit. */

+

+/********************  Bit definition for HSEM_C1MISR register  *****************/

+#define HSEM_C1MISR_MISF0_Pos     (0U)

+#define HSEM_C1MISR_MISF0_Msk     (0x1UL << HSEM_C1MISR_MISF0_Pos)             /*!< 0x00000001 */

+#define HSEM_C1MISR_MISF0         HSEM_C1MISR_MISF0_Msk                        /*!<semaphore 0 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF1_Pos     (1U)

+#define HSEM_C1MISR_MISF1_Msk     (0x1UL << HSEM_C1MISR_MISF1_Pos)             /*!< 0x00000002 */

+#define HSEM_C1MISR_MISF1         HSEM_C1MISR_MISF1_Msk                        /*!<semaphore 1 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF2_Pos     (2U)

+#define HSEM_C1MISR_MISF2_Msk     (0x1UL << HSEM_C1MISR_MISF2_Pos)             /*!< 0x00000004 */

+#define HSEM_C1MISR_MISF2         HSEM_C1MISR_MISF2_Msk                        /*!<semaphore 2 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF3_Pos     (3U)

+#define HSEM_C1MISR_MISF3_Msk     (0x1UL << HSEM_C1MISR_MISF3_Pos)             /*!< 0x00000008 */

+#define HSEM_C1MISR_MISF3         HSEM_C1MISR_MISF3_Msk                        /*!<semaphore 3 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF4_Pos     (4U)

+#define HSEM_C1MISR_MISF4_Msk     (0x1UL << HSEM_C1MISR_MISF4_Pos)             /*!< 0x00000010 */

+#define HSEM_C1MISR_MISF4         HSEM_C1MISR_MISF4_Msk                        /*!<semaphore 4 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF5_Pos     (5U)

+#define HSEM_C1MISR_MISF5_Msk     (0x1UL << HSEM_C1MISR_MISF5_Pos)             /*!< 0x00000020 */

+#define HSEM_C1MISR_MISF5         HSEM_C1MISR_MISF5_Msk                        /*!<semaphore 5 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF6_Pos     (6U)

+#define HSEM_C1MISR_MISF6_Msk     (0x1UL << HSEM_C1MISR_MISF6_Pos)             /*!< 0x00000040 */

+#define HSEM_C1MISR_MISF6         HSEM_C1MISR_MISF6_Msk                        /*!<semaphore 6 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF7_Pos     (7U)

+#define HSEM_C1MISR_MISF7_Msk     (0x1UL << HSEM_C1MISR_MISF7_Pos)             /*!< 0x00000080 */

+#define HSEM_C1MISR_MISF7         HSEM_C1MISR_MISF7_Msk                        /*!<semaphore 7 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF8_Pos     (8U)

+#define HSEM_C1MISR_MISF8_Msk     (0x1UL << HSEM_C1MISR_MISF8_Pos)             /*!< 0x00000100 */

+#define HSEM_C1MISR_MISF8         HSEM_C1MISR_MISF8_Msk                        /*!<semaphore 8 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF9_Pos     (9U)

+#define HSEM_C1MISR_MISF9_Msk     (0x1UL << HSEM_C1MISR_MISF9_Pos)             /*!< 0x00000200 */

+#define HSEM_C1MISR_MISF9         HSEM_C1MISR_MISF9_Msk                        /*!<semaphore 9 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF10_Pos    (10U)

+#define HSEM_C1MISR_MISF10_Msk    (0x1UL << HSEM_C1MISR_MISF10_Pos)            /*!< 0x00000400 */

+#define HSEM_C1MISR_MISF10        HSEM_C1MISR_MISF10_Msk                       /*!<semaphore 10 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF11_Pos    (11U)

+#define HSEM_C1MISR_MISF11_Msk    (0x1UL << HSEM_C1MISR_MISF11_Pos)            /*!< 0x00000800 */

+#define HSEM_C1MISR_MISF11        HSEM_C1MISR_MISF11_Msk                       /*!<semaphore 11 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF12_Pos    (12U)

+#define HSEM_C1MISR_MISF12_Msk    (0x1UL << HSEM_C1MISR_MISF12_Pos)            /*!< 0x00001000 */

+#define HSEM_C1MISR_MISF12        HSEM_C1MISR_MISF12_Msk                       /*!<semaphore 12 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF13_Pos    (13U)

+#define HSEM_C1MISR_MISF13_Msk    (0x1UL << HSEM_C1MISR_MISF13_Pos)            /*!< 0x00002000 */

+#define HSEM_C1MISR_MISF13        HSEM_C1MISR_MISF13_Msk                       /*!<semaphore 13 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF14_Pos    (14U)

+#define HSEM_C1MISR_MISF14_Msk    (0x1UL << HSEM_C1MISR_MISF14_Pos)            /*!< 0x00004000 */

+#define HSEM_C1MISR_MISF14        HSEM_C1MISR_MISF14_Msk                       /*!<semaphore 14 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF15_Pos    (15U)

+#define HSEM_C1MISR_MISF15_Msk    (0x1UL << HSEM_C1MISR_MISF15_Pos)            /*!< 0x00008000 */

+#define HSEM_C1MISR_MISF15        HSEM_C1MISR_MISF15_Msk                       /*!<semaphore 15 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF16_Pos    (16U)

+#define HSEM_C1MISR_MISF16_Msk    (0x1UL << HSEM_C1MISR_MISF16_Pos)            /*!< 0x00010000 */

+#define HSEM_C1MISR_MISF16        HSEM_C1MISR_MISF16_Msk                       /*!<semaphore 16 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF17_Pos    (17U)

+#define HSEM_C1MISR_MISF17_Msk    (0x1UL << HSEM_C1MISR_MISF17_Pos)            /*!< 0x00020000 */

+#define HSEM_C1MISR_MISF17        HSEM_C1MISR_MISF17_Msk                       /*!<semaphore 17 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF18_Pos    (18U)

+#define HSEM_C1MISR_MISF18_Msk    (0x1UL << HSEM_C1MISR_MISF18_Pos)            /*!< 0x00040000 */

+#define HSEM_C1MISR_MISF18        HSEM_C1MISR_MISF18_Msk                       /*!<semaphore 18 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF19_Pos    (19U)

+#define HSEM_C1MISR_MISF19_Msk    (0x1UL << HSEM_C1MISR_MISF19_Pos)            /*!< 0x00080000 */

+#define HSEM_C1MISR_MISF19        HSEM_C1MISR_MISF19_Msk                       /*!<semaphore 19 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF20_Pos    (20U)

+#define HSEM_C1MISR_MISF20_Msk    (0x1UL << HSEM_C1MISR_MISF20_Pos)            /*!< 0x00100000 */

+#define HSEM_C1MISR_MISF20        HSEM_C1MISR_MISF20_Msk                       /*!<semaphore 20 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF21_Pos    (21U)

+#define HSEM_C1MISR_MISF21_Msk    (0x1UL << HSEM_C1MISR_MISF21_Pos)            /*!< 0x00200000 */

+#define HSEM_C1MISR_MISF21        HSEM_C1MISR_MISF21_Msk                       /*!<semaphore 21 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF22_Pos    (22U)

+#define HSEM_C1MISR_MISF22_Msk    (0x1UL << HSEM_C1MISR_MISF22_Pos)            /*!< 0x00400000 */

+#define HSEM_C1MISR_MISF22        HSEM_C1MISR_MISF22_Msk                       /*!<semaphore 22 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF23_Pos    (23U)

+#define HSEM_C1MISR_MISF23_Msk    (0x1UL << HSEM_C1MISR_MISF23_Pos)            /*!< 0x00800000 */

+#define HSEM_C1MISR_MISF23        HSEM_C1MISR_MISF23_Msk                       /*!<semaphore 23 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF24_Pos    (24U)

+#define HSEM_C1MISR_MISF24_Msk    (0x1UL << HSEM_C1MISR_MISF24_Pos)            /*!< 0x01000000 */

+#define HSEM_C1MISR_MISF24        HSEM_C1MISR_MISF24_Msk                       /*!<semaphore 24 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF25_Pos    (25U)

+#define HSEM_C1MISR_MISF25_Msk    (0x1UL << HSEM_C1MISR_MISF25_Pos)            /*!< 0x02000000 */

+#define HSEM_C1MISR_MISF25        HSEM_C1MISR_MISF25_Msk                       /*!<semaphore 25 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF26_Pos    (26U)

+#define HSEM_C1MISR_MISF26_Msk    (0x1UL << HSEM_C1MISR_MISF26_Pos)            /*!< 0x04000000 */

+#define HSEM_C1MISR_MISF26        HSEM_C1MISR_MISF26_Msk                       /*!<semaphore 26 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF27_Pos    (27U)

+#define HSEM_C1MISR_MISF27_Msk    (0x1UL << HSEM_C1MISR_MISF27_Pos)            /*!< 0x08000000 */

+#define HSEM_C1MISR_MISF27        HSEM_C1MISR_MISF27_Msk                       /*!<semaphore 27 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF28_Pos    (28U)

+#define HSEM_C1MISR_MISF28_Msk    (0x1UL << HSEM_C1MISR_MISF28_Pos)            /*!< 0x10000000 */

+#define HSEM_C1MISR_MISF28        HSEM_C1MISR_MISF28_Msk                       /*!<semaphore 28 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF29_Pos    (29U)

+#define HSEM_C1MISR_MISF29_Msk    (0x1UL << HSEM_C1MISR_MISF29_Pos)            /*!< 0x20000000 */

+#define HSEM_C1MISR_MISF29        HSEM_C1MISR_MISF29_Msk                       /*!<semaphore 29 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF30_Pos    (30U)

+#define HSEM_C1MISR_MISF30_Msk    (0x1UL << HSEM_C1MISR_MISF30_Pos)            /*!< 0x40000000 */

+#define HSEM_C1MISR_MISF30        HSEM_C1MISR_MISF30_Msk                       /*!<semaphore 30 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF31_Pos    (31U)

+#define HSEM_C1MISR_MISF31_Msk    (0x1UL << HSEM_C1MISR_MISF31_Pos)            /*!< 0x80000000 */

+#define HSEM_C1MISR_MISF31        HSEM_C1MISR_MISF31_Msk                       /*!<semaphore 31 interrupt 0 masked status bit. */

+

+/********************  Bit definition for HSEM_C2IER register  *****************/

+#define HSEM_C2IER_ISE0_Pos       (0U)

+#define HSEM_C2IER_ISE0_Msk       (0x1UL << HSEM_C2IER_ISE0_Pos)               /*!< 0x00000001 */

+#define HSEM_C2IER_ISE0           HSEM_C2IER_ISE0_Msk                          /*!<semaphore 0 , interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE1_Pos       (1U)

+#define HSEM_C2IER_ISE1_Msk       (0x1UL << HSEM_C2IER_ISE1_Pos)               /*!< 0x00000002 */

+#define HSEM_C2IER_ISE1           HSEM_C2IER_ISE1_Msk                          /*!<semaphore 1 , interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE2_Pos       (2U)

+#define HSEM_C2IER_ISE2_Msk       (0x1UL << HSEM_C2IER_ISE2_Pos)               /*!< 0x00000004 */

+#define HSEM_C2IER_ISE2           HSEM_C2IER_ISE2_Msk                          /*!<semaphore 2 , interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE3_Pos       (3U)

+#define HSEM_C2IER_ISE3_Msk       (0x1UL << HSEM_C2IER_ISE3_Pos)               /*!< 0x00000008 */

+#define HSEM_C2IER_ISE3           HSEM_C2IER_ISE3_Msk                          /*!<semaphore 3 , interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE4_Pos       (4U)

+#define HSEM_C2IER_ISE4_Msk       (0x1UL << HSEM_C2IER_ISE4_Pos)               /*!< 0x00000010 */

+#define HSEM_C2IER_ISE4           HSEM_C2IER_ISE4_Msk                          /*!<semaphore 4 , interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE5_Pos       (5U)

+#define HSEM_C2IER_ISE5_Msk       (0x1UL << HSEM_C2IER_ISE5_Pos)               /*!< 0x00000020 */

+#define HSEM_C2IER_ISE5           HSEM_C2IER_ISE5_Msk                          /*!<semaphore 5 interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE6_Pos       (6U)

+#define HSEM_C2IER_ISE6_Msk       (0x1UL << HSEM_C2IER_ISE6_Pos)               /*!< 0x00000040 */

+#define HSEM_C2IER_ISE6           HSEM_C2IER_ISE6_Msk                          /*!<semaphore 6 interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE7_Pos       (7U)

+#define HSEM_C2IER_ISE7_Msk       (0x1UL << HSEM_C2IER_ISE7_Pos)               /*!< 0x00000080 */

+#define HSEM_C2IER_ISE7           HSEM_C2IER_ISE7_Msk                          /*!<semaphore 7 interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE8_Pos       (8U)

+#define HSEM_C2IER_ISE8_Msk       (0x1UL << HSEM_C2IER_ISE8_Pos)               /*!< 0x00000100 */

+#define HSEM_C2IER_ISE8           HSEM_C2IER_ISE8_Msk                          /*!<semaphore 8 interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE9_Pos       (9U)

+#define HSEM_C2IER_ISE9_Msk       (0x1UL << HSEM_C2IER_ISE9_Pos)               /*!< 0x00000200 */

+#define HSEM_C2IER_ISE9           HSEM_C2IER_ISE9_Msk                          /*!<semaphore 9 interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE10_Pos      (10U)

+#define HSEM_C2IER_ISE10_Msk      (0x1UL << HSEM_C2IER_ISE10_Pos)              /*!< 0x00000400 */

+#define HSEM_C2IER_ISE10          HSEM_C2IER_ISE10_Msk                         /*!<semaphore 10 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE11_Pos      (11U)

+#define HSEM_C2IER_ISE11_Msk      (0x1UL << HSEM_C2IER_ISE11_Pos)              /*!< 0x00000800 */

+#define HSEM_C2IER_ISE11          HSEM_C2IER_ISE11_Msk                         /*!<semaphore 11 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE12_Pos      (12U)

+#define HSEM_C2IER_ISE12_Msk      (0x1UL << HSEM_C2IER_ISE12_Pos)              /*!< 0x00001000 */

+#define HSEM_C2IER_ISE12          HSEM_C2IER_ISE12_Msk                         /*!<semaphore 12 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE13_Pos      (13U)

+#define HSEM_C2IER_ISE13_Msk      (0x1UL << HSEM_C2IER_ISE13_Pos)              /*!< 0x00002000 */

+#define HSEM_C2IER_ISE13          HSEM_C2IER_ISE13_Msk                         /*!<semaphore 13 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE14_Pos      (14U)

+#define HSEM_C2IER_ISE14_Msk      (0x1UL << HSEM_C2IER_ISE14_Pos)              /*!< 0x00004000 */

+#define HSEM_C2IER_ISE14          HSEM_C2IER_ISE14_Msk                         /*!<semaphore 14 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE15_Pos      (15U)

+#define HSEM_C2IER_ISE15_Msk      (0x1UL << HSEM_C2IER_ISE15_Pos)              /*!< 0x00008000 */

+#define HSEM_C2IER_ISE15          HSEM_C2IER_ISE15_Msk                         /*!<semaphore 15 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE16_Pos      (16U)

+#define HSEM_C2IER_ISE16_Msk      (0x1UL << HSEM_C2IER_ISE16_Pos)              /*!< 0x00010000 */

+#define HSEM_C2IER_ISE16          HSEM_C2IER_ISE16_Msk                         /*!<semaphore 16 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE17_Pos      (17U)

+#define HSEM_C2IER_ISE17_Msk      (0x1UL << HSEM_C2IER_ISE17_Pos)              /*!< 0x00020000 */

+#define HSEM_C2IER_ISE17          HSEM_C2IER_ISE17_Msk                         /*!<semaphore 17 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE18_Pos      (18U)

+#define HSEM_C2IER_ISE18_Msk      (0x1UL << HSEM_C2IER_ISE18_Pos)              /*!< 0x00040000 */

+#define HSEM_C2IER_ISE18          HSEM_C2IER_ISE18_Msk                         /*!<semaphore 18 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE19_Pos      (19U)

+#define HSEM_C2IER_ISE19_Msk      (0x1UL << HSEM_C2IER_ISE19_Pos)              /*!< 0x00080000 */

+#define HSEM_C2IER_ISE19          HSEM_C2IER_ISE19_Msk                         /*!<semaphore 19 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE20_Pos      (20U)

+#define HSEM_C2IER_ISE20_Msk      (0x1UL << HSEM_C2IER_ISE20_Pos)              /*!< 0x00100000 */

+#define HSEM_C2IER_ISE20          HSEM_C2IER_ISE20_Msk                         /*!<semaphore 20 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE21_Pos      (21U)

+#define HSEM_C2IER_ISE21_Msk      (0x1UL << HSEM_C2IER_ISE21_Pos)              /*!< 0x00200000 */

+#define HSEM_C2IER_ISE21          HSEM_C2IER_ISE21_Msk                         /*!<semaphore 21 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE22_Pos      (22U)

+#define HSEM_C2IER_ISE22_Msk      (0x1UL << HSEM_C2IER_ISE22_Pos)              /*!< 0x00400000 */

+#define HSEM_C2IER_ISE22          HSEM_C2IER_ISE22_Msk                         /*!<semaphore 22 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE23_Pos      (23U)

+#define HSEM_C2IER_ISE23_Msk      (0x1UL << HSEM_C2IER_ISE23_Pos)              /*!< 0x00800000 */

+#define HSEM_C2IER_ISE23          HSEM_C2IER_ISE23_Msk                         /*!<semaphore 23 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE24_Pos      (24U)

+#define HSEM_C2IER_ISE24_Msk      (0x1UL << HSEM_C2IER_ISE24_Pos)              /*!< 0x01000000 */

+#define HSEM_C2IER_ISE24          HSEM_C2IER_ISE24_Msk                         /*!<semaphore 24 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE25_Pos      (25U)

+#define HSEM_C2IER_ISE25_Msk      (0x1UL << HSEM_C2IER_ISE25_Pos)              /*!< 0x02000000 */

+#define HSEM_C2IER_ISE25          HSEM_C2IER_ISE25_Msk                         /*!<semaphore 25 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE26_Pos      (26U)

+#define HSEM_C2IER_ISE26_Msk      (0x1UL << HSEM_C2IER_ISE26_Pos)              /*!< 0x04000000 */

+#define HSEM_C2IER_ISE26          HSEM_C2IER_ISE26_Msk                         /*!<semaphore 26 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE27_Pos      (27U)

+#define HSEM_C2IER_ISE27_Msk      (0x1UL << HSEM_C2IER_ISE27_Pos)              /*!< 0x08000000 */

+#define HSEM_C2IER_ISE27          HSEM_C2IER_ISE27_Msk                         /*!<semaphore 27 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE28_Pos      (28U)

+#define HSEM_C2IER_ISE28_Msk      (0x1UL << HSEM_C2IER_ISE28_Pos)              /*!< 0x10000000 */

+#define HSEM_C2IER_ISE28          HSEM_C2IER_ISE28_Msk                         /*!<semaphore 28 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE29_Pos      (29U)

+#define HSEM_C2IER_ISE29_Msk      (0x1UL << HSEM_C2IER_ISE29_Pos)              /*!< 0x20000000 */

+#define HSEM_C2IER_ISE29          HSEM_C2IER_ISE29_Msk                         /*!<semaphore 29 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE30_Pos      (30U)

+#define HSEM_C2IER_ISE30_Msk      (0x1UL << HSEM_C2IER_ISE30_Pos)              /*!< 0x40000000 */

+#define HSEM_C2IER_ISE30          HSEM_C2IER_ISE30_Msk                         /*!<semaphore 30 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE31_Pos      (31U)

+#define HSEM_C2IER_ISE31_Msk      (0x1UL << HSEM_C2IER_ISE31_Pos)              /*!< 0x80000000 */

+#define HSEM_C2IER_ISE31          HSEM_C2IER_ISE31_Msk                         /*!<semaphore 31 interrupt 1 enable bit. */

+

+/********************  Bit definition for HSEM_C2ICR register  *****************/

+#define HSEM_C2ICR_ISC0_Pos       (0U)

+#define HSEM_C2ICR_ISC0_Msk       (0x1UL << HSEM_C2ICR_ISC0_Pos)               /*!< 0x00000001 */

+#define HSEM_C2ICR_ISC0           HSEM_C2ICR_ISC0_Msk                          /*!<semaphore 0 , interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC1_Pos       (1U)

+#define HSEM_C2ICR_ISC1_Msk       (0x1UL << HSEM_C2ICR_ISC1_Pos)               /*!< 0x00000002 */

+#define HSEM_C2ICR_ISC1           HSEM_C2ICR_ISC1_Msk                          /*!<semaphore 1 , interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC2_Pos       (2U)

+#define HSEM_C2ICR_ISC2_Msk       (0x1UL << HSEM_C2ICR_ISC2_Pos)               /*!< 0x00000004 */

+#define HSEM_C2ICR_ISC2           HSEM_C2ICR_ISC2_Msk                          /*!<semaphore 2 , interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC3_Pos       (3U)

+#define HSEM_C2ICR_ISC3_Msk       (0x1UL << HSEM_C2ICR_ISC3_Pos)               /*!< 0x00000008 */

+#define HSEM_C2ICR_ISC3           HSEM_C2ICR_ISC3_Msk                          /*!<semaphore 3 , interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC4_Pos       (4U)

+#define HSEM_C2ICR_ISC4_Msk       (0x1UL << HSEM_C2ICR_ISC4_Pos)               /*!< 0x00000010 */

+#define HSEM_C2ICR_ISC4           HSEM_C2ICR_ISC4_Msk                          /*!<semaphore 4 , interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC5_Pos       (5U)

+#define HSEM_C2ICR_ISC5_Msk       (0x1UL << HSEM_C2ICR_ISC5_Pos)               /*!< 0x00000020 */

+#define HSEM_C2ICR_ISC5           HSEM_C2ICR_ISC5_Msk                          /*!<semaphore 5 interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC6_Pos       (6U)

+#define HSEM_C2ICR_ISC6_Msk       (0x1UL << HSEM_C2ICR_ISC6_Pos)               /*!< 0x00000040 */

+#define HSEM_C2ICR_ISC6           HSEM_C2ICR_ISC6_Msk                          /*!<semaphore 6 interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC7_Pos       (7U)

+#define HSEM_C2ICR_ISC7_Msk       (0x1UL << HSEM_C2ICR_ISC7_Pos)               /*!< 0x00000080 */

+#define HSEM_C2ICR_ISC7           HSEM_C2ICR_ISC7_Msk                          /*!<semaphore 7 interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC8_Pos       (8U)

+#define HSEM_C2ICR_ISC8_Msk       (0x1UL << HSEM_C2ICR_ISC8_Pos)               /*!< 0x00000100 */

+#define HSEM_C2ICR_ISC8           HSEM_C2ICR_ISC8_Msk                          /*!<semaphore 8 interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC9_Pos       (9U)

+#define HSEM_C2ICR_ISC9_Msk       (0x1UL << HSEM_C2ICR_ISC9_Pos)               /*!< 0x00000200 */

+#define HSEM_C2ICR_ISC9           HSEM_C2ICR_ISC9_Msk                          /*!<semaphore 9 interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC10_Pos      (10U)

+#define HSEM_C2ICR_ISC10_Msk      (0x1UL << HSEM_C2ICR_ISC10_Pos)              /*!< 0x00000400 */

+#define HSEM_C2ICR_ISC10          HSEM_C2ICR_ISC10_Msk                         /*!<semaphore 10 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC11_Pos      (11U)

+#define HSEM_C2ICR_ISC11_Msk      (0x1UL << HSEM_C2ICR_ISC11_Pos)              /*!< 0x00000800 */

+#define HSEM_C2ICR_ISC11          HSEM_C2ICR_ISC11_Msk                         /*!<semaphore 11 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC12_Pos      (12U)

+#define HSEM_C2ICR_ISC12_Msk      (0x1UL << HSEM_C2ICR_ISC12_Pos)              /*!< 0x00001000 */

+#define HSEM_C2ICR_ISC12          HSEM_C2ICR_ISC12_Msk                         /*!<semaphore 12 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC13_Pos      (13U)

+#define HSEM_C2ICR_ISC13_Msk      (0x1UL << HSEM_C2ICR_ISC13_Pos)              /*!< 0x00002000 */

+#define HSEM_C2ICR_ISC13          HSEM_C2ICR_ISC13_Msk                         /*!<semaphore 13 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC14_Pos      (14U)

+#define HSEM_C2ICR_ISC14_Msk      (0x1UL << HSEM_C2ICR_ISC14_Pos)              /*!< 0x00004000 */

+#define HSEM_C2ICR_ISC14          HSEM_C2ICR_ISC14_Msk                         /*!<semaphore 14 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC15_Pos      (15U)

+#define HSEM_C2ICR_ISC15_Msk      (0x1UL << HSEM_C2ICR_ISC15_Pos)              /*!< 0x00008000 */

+#define HSEM_C2ICR_ISC15          HSEM_C2ICR_ISC15_Msk                         /*!<semaphore 15 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC16_Pos      (16U)

+#define HSEM_C2ICR_ISC16_Msk      (0x1UL << HSEM_C2ICR_ISC16_Pos)              /*!< 0x00010000 */

+#define HSEM_C2ICR_ISC16          HSEM_C2ICR_ISC16_Msk                         /*!<semaphore 16 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC17_Pos      (17U)

+#define HSEM_C2ICR_ISC17_Msk      (0x1UL << HSEM_C2ICR_ISC17_Pos)              /*!< 0x00020000 */

+#define HSEM_C2ICR_ISC17          HSEM_C2ICR_ISC17_Msk                         /*!<semaphore 17 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC18_Pos      (18U)

+#define HSEM_C2ICR_ISC18_Msk      (0x1UL << HSEM_C2ICR_ISC18_Pos)              /*!< 0x00040000 */

+#define HSEM_C2ICR_ISC18          HSEM_C2ICR_ISC18_Msk                         /*!<semaphore 18 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC19_Pos      (19U)

+#define HSEM_C2ICR_ISC19_Msk      (0x1UL << HSEM_C2ICR_ISC19_Pos)              /*!< 0x00080000 */

+#define HSEM_C2ICR_ISC19          HSEM_C2ICR_ISC19_Msk                         /*!<semaphore 19 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC20_Pos      (20U)

+#define HSEM_C2ICR_ISC20_Msk      (0x1UL << HSEM_C2ICR_ISC20_Pos)              /*!< 0x00100000 */

+#define HSEM_C2ICR_ISC20          HSEM_C2ICR_ISC20_Msk                         /*!<semaphore 20 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC21_Pos      (21U)

+#define HSEM_C2ICR_ISC21_Msk      (0x1UL << HSEM_C2ICR_ISC21_Pos)              /*!< 0x00200000 */

+#define HSEM_C2ICR_ISC21          HSEM_C2ICR_ISC21_Msk                         /*!<semaphore 21 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC22_Pos      (22U)

+#define HSEM_C2ICR_ISC22_Msk      (0x1UL << HSEM_C2ICR_ISC22_Pos)              /*!< 0x00400000 */

+#define HSEM_C2ICR_ISC22          HSEM_C2ICR_ISC22_Msk                         /*!<semaphore 22 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC23_Pos      (23U)

+#define HSEM_C2ICR_ISC23_Msk      (0x1UL << HSEM_C2ICR_ISC23_Pos)              /*!< 0x00800000 */

+#define HSEM_C2ICR_ISC23          HSEM_C2ICR_ISC23_Msk                         /*!<semaphore 23 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC24_Pos      (24U)

+#define HSEM_C2ICR_ISC24_Msk      (0x1UL << HSEM_C2ICR_ISC24_Pos)              /*!< 0x01000000 */

+#define HSEM_C2ICR_ISC24          HSEM_C2ICR_ISC24_Msk                         /*!<semaphore 24 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC25_Pos      (25U)

+#define HSEM_C2ICR_ISC25_Msk      (0x1UL << HSEM_C2ICR_ISC25_Pos)              /*!< 0x02000000 */

+#define HSEM_C2ICR_ISC25          HSEM_C2ICR_ISC25_Msk                         /*!<semaphore 25 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC26_Pos      (26U)

+#define HSEM_C2ICR_ISC26_Msk      (0x1UL << HSEM_C2ICR_ISC26_Pos)              /*!< 0x04000000 */

+#define HSEM_C2ICR_ISC26          HSEM_C2ICR_ISC26_Msk                         /*!<semaphore 26 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC27_Pos      (27U)

+#define HSEM_C2ICR_ISC27_Msk      (0x1UL << HSEM_C2ICR_ISC27_Pos)              /*!< 0x08000000 */

+#define HSEM_C2ICR_ISC27          HSEM_C2ICR_ISC27_Msk                         /*!<semaphore 27 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC28_Pos      (28U)

+#define HSEM_C2ICR_ISC28_Msk      (0x1UL << HSEM_C2ICR_ISC28_Pos)              /*!< 0x10000000 */

+#define HSEM_C2ICR_ISC28          HSEM_C2ICR_ISC28_Msk                         /*!<semaphore 28 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC29_Pos      (29U)

+#define HSEM_C2ICR_ISC29_Msk      (0x1UL << HSEM_C2ICR_ISC29_Pos)              /*!< 0x20000000 */

+#define HSEM_C2ICR_ISC29          HSEM_C2ICR_ISC29_Msk                         /*!<semaphore 29 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC30_Pos      (30U)

+#define HSEM_C2ICR_ISC30_Msk      (0x1UL << HSEM_C2ICR_ISC30_Pos)              /*!< 0x40000000 */

+#define HSEM_C2ICR_ISC30          HSEM_C2ICR_ISC30_Msk                         /*!<semaphore 30 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC31_Pos      (31U)

+#define HSEM_C2ICR_ISC31_Msk      (0x1UL << HSEM_C2ICR_ISC31_Pos)              /*!< 0x80000000 */

+#define HSEM_C2ICR_ISC31          HSEM_C2ICR_ISC31_Msk                         /*!<semaphore 31 interrupt 1 clear bit. */

+

+/********************  Bit definition for HSEM_C2ISR register  *****************/

+#define HSEM_C2ISR_ISF0_Pos       (0U)

+#define HSEM_C2ISR_ISF0_Msk       (0x1UL << HSEM_C2ISR_ISF0_Pos)               /*!< 0x00000001 */

+#define HSEM_C2ISR_ISF0           HSEM_C2ISR_ISF0_Msk                          /*!<semaphore 0 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF1_Pos       (1U)

+#define HSEM_C2ISR_ISF1_Msk       (0x1UL << HSEM_C2ISR_ISF1_Pos)               /*!< 0x00000002 */

+#define HSEM_C2ISR_ISF1           HSEM_C2ISR_ISF1_Msk                          /*!<semaphore 1 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF2_Pos       (2U)

+#define HSEM_C2ISR_ISF2_Msk       (0x1UL << HSEM_C2ISR_ISF2_Pos)               /*!< 0x00000004 */

+#define HSEM_C2ISR_ISF2           HSEM_C2ISR_ISF2_Msk                          /*!<semaphore 2 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF3_Pos       (3U)

+#define HSEM_C2ISR_ISF3_Msk       (0x1UL << HSEM_C2ISR_ISF3_Pos)               /*!< 0x00000008 */

+#define HSEM_C2ISR_ISF3           HSEM_C2ISR_ISF3_Msk                          /*!<semaphore 3 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF4_Pos       (4U)

+#define HSEM_C2ISR_ISF4_Msk       (0x1UL << HSEM_C2ISR_ISF4_Pos)               /*!< 0x00000010 */

+#define HSEM_C2ISR_ISF4           HSEM_C2ISR_ISF4_Msk                          /*!<semaphore 4 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF5_Pos       (5U)

+#define HSEM_C2ISR_ISF5_Msk       (0x1UL << HSEM_C2ISR_ISF5_Pos)               /*!< 0x00000020 */

+#define HSEM_C2ISR_ISF5           HSEM_C2ISR_ISF5_Msk                          /*!<semaphore 5 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF6_Pos       (6U)

+#define HSEM_C2ISR_ISF6_Msk       (0x1UL << HSEM_C2ISR_ISF6_Pos)               /*!< 0x00000040 */

+#define HSEM_C2ISR_ISF6           HSEM_C2ISR_ISF6_Msk                          /*!<semaphore 6 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF7_Pos       (7U)

+#define HSEM_C2ISR_ISF7_Msk       (0x1UL << HSEM_C2ISR_ISF7_Pos)               /*!< 0x00000080 */

+#define HSEM_C2ISR_ISF7           HSEM_C2ISR_ISF7_Msk                          /*!<semaphore 7 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF8_Pos       (8U)

+#define HSEM_C2ISR_ISF8_Msk       (0x1UL << HSEM_C2ISR_ISF8_Pos)               /*!< 0x00000100 */

+#define HSEM_C2ISR_ISF8           HSEM_C2ISR_ISF8_Msk                          /*!<semaphore 8 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF9_Pos       (9U)

+#define HSEM_C2ISR_ISF9_Msk       (0x1UL << HSEM_C2ISR_ISF9_Pos)               /*!< 0x00000200 */

+#define HSEM_C2ISR_ISF9           HSEM_C2ISR_ISF9_Msk                          /*!<semaphore 9 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF10_Pos      (10U)

+#define HSEM_C2ISR_ISF10_Msk      (0x1UL << HSEM_C2ISR_ISF10_Pos)              /*!< 0x00000400 */

+#define HSEM_C2ISR_ISF10          HSEM_C2ISR_ISF10_Msk                         /*!<semaphore 10 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF11_Pos      (11U)

+#define HSEM_C2ISR_ISF11_Msk      (0x1UL << HSEM_C2ISR_ISF11_Pos)              /*!< 0x00000800 */

+#define HSEM_C2ISR_ISF11          HSEM_C2ISR_ISF11_Msk                         /*!<semaphore 11 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF12_Pos      (12U)

+#define HSEM_C2ISR_ISF12_Msk      (0x1UL << HSEM_C2ISR_ISF12_Pos)              /*!< 0x00001000 */

+#define HSEM_C2ISR_ISF12          HSEM_C2ISR_ISF12_Msk                         /*!<semaphore 12 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF13_Pos      (13U)

+#define HSEM_C2ISR_ISF13_Msk      (0x1UL << HSEM_C2ISR_ISF13_Pos)              /*!< 0x00002000 */

+#define HSEM_C2ISR_ISF13          HSEM_C2ISR_ISF13_Msk                         /*!<semaphore 13 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF14_Pos      (14U)

+#define HSEM_C2ISR_ISF14_Msk      (0x1UL << HSEM_C2ISR_ISF14_Pos)              /*!< 0x00004000 */

+#define HSEM_C2ISR_ISF14          HSEM_C2ISR_ISF14_Msk                         /*!<semaphore 14 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF15_Pos      (15U)

+#define HSEM_C2ISR_ISF15_Msk      (0x1UL << HSEM_C2ISR_ISF15_Pos)              /*!< 0x00008000 */

+#define HSEM_C2ISR_ISF15          HSEM_C2ISR_ISF15_Msk                         /*!<semaphore 15 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF16_Pos      (16U)

+#define HSEM_C2ISR_ISF16_Msk      (0x1UL << HSEM_C2ISR_ISF16_Pos)              /*!< 0x00010000 */

+#define HSEM_C2ISR_ISF16          HSEM_C2ISR_ISF16_Msk                         /*!<semaphore 16 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF17_Pos      (17U)

+#define HSEM_C2ISR_ISF17_Msk      (0x1UL << HSEM_C2ISR_ISF17_Pos)              /*!< 0x00020000 */

+#define HSEM_C2ISR_ISF17          HSEM_C2ISR_ISF17_Msk                         /*!<semaphore 17 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF18_Pos      (18U)

+#define HSEM_C2ISR_ISF18_Msk      (0x1UL << HSEM_C2ISR_ISF18_Pos)              /*!< 0x00040000 */

+#define HSEM_C2ISR_ISF18          HSEM_C2ISR_ISF18_Msk                         /*!<semaphore 18 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF19_Pos      (19U)

+#define HSEM_C2ISR_ISF19_Msk      (0x1UL << HSEM_C2ISR_ISF19_Pos)              /*!< 0x00080000 */

+#define HSEM_C2ISR_ISF19          HSEM_C2ISR_ISF19_Msk                         /*!<semaphore 19 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF20_Pos      (20U)

+#define HSEM_C2ISR_ISF20_Msk      (0x1UL << HSEM_C2ISR_ISF20_Pos)              /*!< 0x00100000 */

+#define HSEM_C2ISR_ISF20          HSEM_C2ISR_ISF20_Msk                         /*!<semaphore 20 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF21_Pos      (21U)

+#define HSEM_C2ISR_ISF21_Msk      (0x1UL << HSEM_C2ISR_ISF21_Pos)              /*!< 0x00200000 */

+#define HSEM_C2ISR_ISF21          HSEM_C2ISR_ISF21_Msk                         /*!<semaphore 21 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF22_Pos      (22U)

+#define HSEM_C2ISR_ISF22_Msk      (0x1UL << HSEM_C2ISR_ISF22_Pos)              /*!< 0x00400000 */

+#define HSEM_C2ISR_ISF22          HSEM_C2ISR_ISF22_Msk                         /*!<semaphore 22 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF23_Pos      (23U)

+#define HSEM_C2ISR_ISF23_Msk      (0x1UL << HSEM_C2ISR_ISF23_Pos)              /*!< 0x00800000 */

+#define HSEM_C2ISR_ISF23          HSEM_C2ISR_ISF23_Msk                         /*!<semaphore 23 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF24_Pos      (24U)

+#define HSEM_C2ISR_ISF24_Msk      (0x1UL << HSEM_C2ISR_ISF24_Pos)              /*!< 0x01000000 */

+#define HSEM_C2ISR_ISF24          HSEM_C2ISR_ISF24_Msk                         /*!<semaphore 24 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF25_Pos      (25U)

+#define HSEM_C2ISR_ISF25_Msk      (0x1UL << HSEM_C2ISR_ISF25_Pos)              /*!< 0x02000000 */

+#define HSEM_C2ISR_ISF25          HSEM_C2ISR_ISF25_Msk                         /*!<semaphore 25 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF26_Pos      (26U)

+#define HSEM_C2ISR_ISF26_Msk      (0x1UL << HSEM_C2ISR_ISF26_Pos)              /*!< 0x04000000 */

+#define HSEM_C2ISR_ISF26          HSEM_C2ISR_ISF26_Msk                         /*!<semaphore 26 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF27_Pos      (27U)

+#define HSEM_C2ISR_ISF27_Msk      (0x1UL << HSEM_C2ISR_ISF27_Pos)              /*!< 0x08000000 */

+#define HSEM_C2ISR_ISF27          HSEM_C2ISR_ISF27_Msk                         /*!<semaphore 27 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF28_Pos      (28U)

+#define HSEM_C2ISR_ISF28_Msk      (0x1UL << HSEM_C2ISR_ISF28_Pos)              /*!< 0x10000000 */

+#define HSEM_C2ISR_ISF28          HSEM_C2ISR_ISF28_Msk                         /*!<semaphore 28 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF29_Pos      (29U)

+#define HSEM_C2ISR_ISF29_Msk      (0x1UL << HSEM_C2ISR_ISF29_Pos)              /*!< 0x20000000 */

+#define HSEM_C2ISR_ISF29          HSEM_C2ISR_ISF29_Msk                         /*!<semaphore 29 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF30_Pos      (30U)

+#define HSEM_C2ISR_ISF30_Msk      (0x1UL << HSEM_C2ISR_ISF30_Pos)              /*!< 0x40000000 */

+#define HSEM_C2ISR_ISF30          HSEM_C2ISR_ISF30_Msk                         /*!<semaphore 30 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF31_Pos      (31U)

+#define HSEM_C2ISR_ISF31_Msk      (0x1UL << HSEM_C2ISR_ISF31_Pos)              /*!< 0x80000000 */

+#define HSEM_C2ISR_ISF31          HSEM_C2ISR_ISF31_Msk                         /*!<semaphore 31 interrupt 1 status bit. */

+

+/********************  Bit definition for HSEM_C2MISR register  *****************/

+#define HSEM_C2MISR_MISF0_Pos     (0U)

+#define HSEM_C2MISR_MISF0_Msk     (0x1UL << HSEM_C2MISR_MISF0_Pos)             /*!< 0x00000001 */

+#define HSEM_C2MISR_MISF0         HSEM_C2MISR_MISF0_Msk                        /*!<semaphore 0 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF1_Pos     (1U)

+#define HSEM_C2MISR_MISF1_Msk     (0x1UL << HSEM_C2MISR_MISF1_Pos)             /*!< 0x00000002 */

+#define HSEM_C2MISR_MISF1         HSEM_C2MISR_MISF1_Msk                        /*!<semaphore 1 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF2_Pos     (2U)

+#define HSEM_C2MISR_MISF2_Msk     (0x1UL << HSEM_C2MISR_MISF2_Pos)             /*!< 0x00000004 */

+#define HSEM_C2MISR_MISF2         HSEM_C2MISR_MISF2_Msk                        /*!<semaphore 2 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF3_Pos     (3U)

+#define HSEM_C2MISR_MISF3_Msk     (0x1UL << HSEM_C2MISR_MISF3_Pos)             /*!< 0x00000008 */

+#define HSEM_C2MISR_MISF3         HSEM_C2MISR_MISF3_Msk                        /*!<semaphore 3 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF4_Pos     (4U)

+#define HSEM_C2MISR_MISF4_Msk     (0x1UL << HSEM_C2MISR_MISF4_Pos)             /*!< 0x00000010 */

+#define HSEM_C2MISR_MISF4         HSEM_C2MISR_MISF4_Msk                        /*!<semaphore 4 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF5_Pos     (5U)

+#define HSEM_C2MISR_MISF5_Msk     (0x1UL << HSEM_C2MISR_MISF5_Pos)             /*!< 0x00000020 */

+#define HSEM_C2MISR_MISF5         HSEM_C2MISR_MISF5_Msk                        /*!<semaphore 5 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF6_Pos     (6U)

+#define HSEM_C2MISR_MISF6_Msk     (0x1UL << HSEM_C2MISR_MISF6_Pos)             /*!< 0x00000040 */

+#define HSEM_C2MISR_MISF6         HSEM_C2MISR_MISF6_Msk                        /*!<semaphore 6 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF7_Pos     (7U)

+#define HSEM_C2MISR_MISF7_Msk     (0x1UL << HSEM_C2MISR_MISF7_Pos)             /*!< 0x00000080 */

+#define HSEM_C2MISR_MISF7         HSEM_C2MISR_MISF7_Msk                        /*!<semaphore 7 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF8_Pos     (8U)

+#define HSEM_C2MISR_MISF8_Msk     (0x1UL << HSEM_C2MISR_MISF8_Pos)             /*!< 0x00000100 */

+#define HSEM_C2MISR_MISF8         HSEM_C2MISR_MISF8_Msk                        /*!<semaphore 8 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF9_Pos     (9U)

+#define HSEM_C2MISR_MISF9_Msk     (0x1UL << HSEM_C2MISR_MISF9_Pos)             /*!< 0x00000200 */

+#define HSEM_C2MISR_MISF9         HSEM_C2MISR_MISF9_Msk                        /*!<semaphore 9 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF10_Pos    (10U)

+#define HSEM_C2MISR_MISF10_Msk    (0x1UL << HSEM_C2MISR_MISF10_Pos)            /*!< 0x00000400 */

+#define HSEM_C2MISR_MISF10        HSEM_C2MISR_MISF10_Msk                       /*!<semaphore 10 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF11_Pos    (11U)

+#define HSEM_C2MISR_MISF11_Msk    (0x1UL << HSEM_C2MISR_MISF11_Pos)            /*!< 0x00000800 */

+#define HSEM_C2MISR_MISF11        HSEM_C2MISR_MISF11_Msk                       /*!<semaphore 11 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF12_Pos    (12U)

+#define HSEM_C2MISR_MISF12_Msk    (0x1UL << HSEM_C2MISR_MISF12_Pos)            /*!< 0x00001000 */

+#define HSEM_C2MISR_MISF12        HSEM_C2MISR_MISF12_Msk                       /*!<semaphore 12 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF13_Pos    (13U)

+#define HSEM_C2MISR_MISF13_Msk    (0x1UL << HSEM_C2MISR_MISF13_Pos)            /*!< 0x00002000 */

+#define HSEM_C2MISR_MISF13        HSEM_C2MISR_MISF13_Msk                       /*!<semaphore 13 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF14_Pos    (14U)

+#define HSEM_C2MISR_MISF14_Msk    (0x1UL << HSEM_C2MISR_MISF14_Pos)            /*!< 0x00004000 */

+#define HSEM_C2MISR_MISF14        HSEM_C2MISR_MISF14_Msk                       /*!<semaphore 14 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF15_Pos    (15U)

+#define HSEM_C2MISR_MISF15_Msk    (0x1UL << HSEM_C2MISR_MISF15_Pos)            /*!< 0x00008000 */

+#define HSEM_C2MISR_MISF15        HSEM_C2MISR_MISF15_Msk                       /*!<semaphore 15 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF16_Pos    (16U)

+#define HSEM_C2MISR_MISF16_Msk    (0x1UL << HSEM_C2MISR_MISF16_Pos)            /*!< 0x00010000 */

+#define HSEM_C2MISR_MISF16        HSEM_C2MISR_MISF16_Msk                       /*!<semaphore 16 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF17_Pos    (17U)

+#define HSEM_C2MISR_MISF17_Msk    (0x1UL << HSEM_C2MISR_MISF17_Pos)            /*!< 0x00020000 */

+#define HSEM_C2MISR_MISF17        HSEM_C2MISR_MISF17_Msk                       /*!<semaphore 17 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF18_Pos    (18U)

+#define HSEM_C2MISR_MISF18_Msk    (0x1UL << HSEM_C2MISR_MISF18_Pos)            /*!< 0x00040000 */

+#define HSEM_C2MISR_MISF18        HSEM_C2MISR_MISF18_Msk                       /*!<semaphore 18 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF19_Pos    (19U)

+#define HSEM_C2MISR_MISF19_Msk    (0x1UL << HSEM_C2MISR_MISF19_Pos)            /*!< 0x00080000 */

+#define HSEM_C2MISR_MISF19        HSEM_C2MISR_MISF19_Msk                       /*!<semaphore 19 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF20_Pos    (20U)

+#define HSEM_C2MISR_MISF20_Msk    (0x1UL << HSEM_C2MISR_MISF20_Pos)            /*!< 0x00100000 */

+#define HSEM_C2MISR_MISF20        HSEM_C2MISR_MISF20_Msk                       /*!<semaphore 20 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF21_Pos    (21U)

+#define HSEM_C2MISR_MISF21_Msk    (0x1UL << HSEM_C2MISR_MISF21_Pos)            /*!< 0x00200000 */

+#define HSEM_C2MISR_MISF21        HSEM_C2MISR_MISF21_Msk                       /*!<semaphore 21 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF22_Pos    (22U)

+#define HSEM_C2MISR_MISF22_Msk    (0x1UL << HSEM_C2MISR_MISF22_Pos)            /*!< 0x00400000 */

+#define HSEM_C2MISR_MISF22        HSEM_C2MISR_MISF22_Msk                       /*!<semaphore 22 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF23_Pos    (23U)

+#define HSEM_C2MISR_MISF23_Msk    (0x1UL << HSEM_C2MISR_MISF23_Pos)            /*!< 0x00800000 */

+#define HSEM_C2MISR_MISF23        HSEM_C2MISR_MISF23_Msk                       /*!<semaphore 23 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF24_Pos    (24U)

+#define HSEM_C2MISR_MISF24_Msk    (0x1UL << HSEM_C2MISR_MISF24_Pos)            /*!< 0x01000000 */

+#define HSEM_C2MISR_MISF24        HSEM_C2MISR_MISF24_Msk                       /*!<semaphore 24 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF25_Pos    (25U)

+#define HSEM_C2MISR_MISF25_Msk    (0x1UL << HSEM_C2MISR_MISF25_Pos)            /*!< 0x02000000 */

+#define HSEM_C2MISR_MISF25        HSEM_C2MISR_MISF25_Msk                       /*!<semaphore 25 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF26_Pos    (26U)

+#define HSEM_C2MISR_MISF26_Msk    (0x1UL << HSEM_C2MISR_MISF26_Pos)            /*!< 0x04000000 */

+#define HSEM_C2MISR_MISF26        HSEM_C2MISR_MISF26_Msk                       /*!<semaphore 26 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF27_Pos    (27U)

+#define HSEM_C2MISR_MISF27_Msk    (0x1UL << HSEM_C2MISR_MISF27_Pos)            /*!< 0x08000000 */

+#define HSEM_C2MISR_MISF27        HSEM_C2MISR_MISF27_Msk                       /*!<semaphore 27 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF28_Pos    (28U)

+#define HSEM_C2MISR_MISF28_Msk    (0x1UL << HSEM_C2MISR_MISF28_Pos)            /*!< 0x10000000 */

+#define HSEM_C2MISR_MISF28        HSEM_C2MISR_MISF28_Msk                       /*!<semaphore 28 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF29_Pos    (29U)

+#define HSEM_C2MISR_MISF29_Msk    (0x1UL << HSEM_C2MISR_MISF29_Pos)            /*!< 0x20000000 */

+#define HSEM_C2MISR_MISF29        HSEM_C2MISR_MISF29_Msk                       /*!<semaphore 29 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF30_Pos    (30U)

+#define HSEM_C2MISR_MISF30_Msk    (0x1UL << HSEM_C2MISR_MISF30_Pos)            /*!< 0x40000000 */

+#define HSEM_C2MISR_MISF30        HSEM_C2MISR_MISF30_Msk                       /*!<semaphore 30 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF31_Pos    (31U)

+#define HSEM_C2MISR_MISF31_Msk    (0x1UL << HSEM_C2MISR_MISF31_Pos)            /*!< 0x80000000 */

+#define HSEM_C2MISR_MISF31        HSEM_C2MISR_MISF31_Msk                       /*!<semaphore 31 interrupt 1 masked status bit. */

+/********************  Bit definition for HSEM_CR register  *****************/

+#define HSEM_CR_COREID_Pos        (8U)

+#define HSEM_CR_COREID_Msk        (0xFFUL << HSEM_CR_COREID_Pos)               /*!< 0x0000FF00 */

+#define HSEM_CR_COREID            HSEM_CR_COREID_Msk                           /*!<CoreID of semaphores to be cleared. */

+#define HSEM_CR_KEY_Pos           (16U)

+#define HSEM_CR_KEY_Msk           (0xFFFFUL << HSEM_CR_KEY_Pos)                /*!< 0xFFFF0000 */

+#define HSEM_CR_KEY               HSEM_CR_KEY_Msk                              /*!<semaphores clear key. */

+

+/********************  Bit definition for HSEM_KEYR register  *****************/

+#define HSEM_KEYR_KEY_Pos         (16U)

+#define HSEM_KEYR_KEY_Msk         (0xFFFFUL << HSEM_KEYR_KEY_Pos)              /*!< 0xFFFF0000 */

+#define HSEM_KEYR_KEY             HSEM_KEYR_KEY_Msk                            /*!<semaphores clear key. */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      Inter-integrated Circuit Interface (I2C)              */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for I2C_CR1 register  *******************/

+#define I2C_CR1_PE_Pos               (0U)

+#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */

+#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */

+#define I2C_CR1_TXIE_Pos             (1U)

+#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */

+#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */

+#define I2C_CR1_RXIE_Pos             (2U)

+#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */

+#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */

+#define I2C_CR1_ADDRIE_Pos           (3U)

+#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */

+#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */

+#define I2C_CR1_NACKIE_Pos           (4U)

+#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */

+#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */

+#define I2C_CR1_STOPIE_Pos           (5U)

+#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */

+#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */

+#define I2C_CR1_TCIE_Pos             (6U)

+#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */

+#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */

+#define I2C_CR1_ERRIE_Pos            (7U)

+#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */

+#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */

+#define I2C_CR1_DNF_Pos              (8U)

+#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */

+#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */

+#define I2C_CR1_ANFOFF_Pos           (12U)

+#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */

+#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */

+#define I2C_CR1_TXDMAEN_Pos          (14U)

+#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */

+#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */

+#define I2C_CR1_RXDMAEN_Pos          (15U)

+#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */

+#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */

+#define I2C_CR1_SBC_Pos              (16U)

+#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */

+#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */

+#define I2C_CR1_NOSTRETCH_Pos        (17U)

+#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */

+#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */

+#define I2C_CR1_WUPEN_Pos            (18U)

+#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */

+#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */

+#define I2C_CR1_GCEN_Pos             (19U)

+#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */

+#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */

+#define I2C_CR1_SMBHEN_Pos           (20U)

+#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */

+#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */

+#define I2C_CR1_SMBDEN_Pos           (21U)

+#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */

+#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */

+#define I2C_CR1_ALERTEN_Pos          (22U)

+#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */

+#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */

+#define I2C_CR1_PECEN_Pos            (23U)

+#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */

+#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */

+

+/******************  Bit definition for I2C_CR2 register  ********************/

+#define I2C_CR2_SADD_Pos             (0U)

+#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */

+#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */

+#define I2C_CR2_RD_WRN_Pos           (10U)

+#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */

+#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */

+#define I2C_CR2_ADD10_Pos            (11U)

+#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */

+#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */

+#define I2C_CR2_HEAD10R_Pos          (12U)

+#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */

+#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */

+#define I2C_CR2_START_Pos            (13U)

+#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */

+#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */

+#define I2C_CR2_STOP_Pos             (14U)

+#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */

+#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */

+#define I2C_CR2_NACK_Pos             (15U)

+#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */

+#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */

+#define I2C_CR2_NBYTES_Pos           (16U)

+#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */

+#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */

+#define I2C_CR2_RELOAD_Pos           (24U)

+#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */

+#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */

+#define I2C_CR2_AUTOEND_Pos          (25U)

+#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */

+#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */

+#define I2C_CR2_PECBYTE_Pos          (26U)

+#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */

+#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */

+

+/*******************  Bit definition for I2C_OAR1 register  ******************/

+#define I2C_OAR1_OA1_Pos             (0U)

+#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */

+#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */

+#define I2C_OAR1_OA1MODE_Pos         (10U)

+#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */

+#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */

+#define I2C_OAR1_OA1EN_Pos           (15U)

+#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */

+#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */

+

+/*******************  Bit definition for I2C_OAR2 register  ******************/

+#define I2C_OAR2_OA2_Pos             (1U)

+#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */

+#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */

+#define I2C_OAR2_OA2MSK_Pos          (8U)

+#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */

+#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */

+#define I2C_OAR2_OA2NOMASK           0x00000000UL                              /*!< No mask */

+#define I2C_OAR2_OA2MASK01_Pos       (8U)

+#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */

+#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared */

+#define I2C_OAR2_OA2MASK02_Pos       (9U)

+#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */

+#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */

+#define I2C_OAR2_OA2MASK03_Pos       (8U)

+#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */

+#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */

+#define I2C_OAR2_OA2MASK04_Pos       (10U)

+#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */

+#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */

+#define I2C_OAR2_OA2MASK05_Pos       (8U)

+#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */

+#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */

+#define I2C_OAR2_OA2MASK06_Pos       (9U)

+#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */

+#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared */

+#define I2C_OAR2_OA2MASK07_Pos       (8U)

+#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */

+#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done */

+#define I2C_OAR2_OA2EN_Pos           (15U)

+#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */

+#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */

+

+/*******************  Bit definition for I2C_TIMINGR register *******************/

+#define I2C_TIMINGR_SCLL_Pos         (0U)

+#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */

+#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */

+#define I2C_TIMINGR_SCLH_Pos         (8U)

+#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */

+#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */

+#define I2C_TIMINGR_SDADEL_Pos       (16U)

+#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */

+#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */

+#define I2C_TIMINGR_SCLDEL_Pos       (20U)

+#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */

+#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */

+#define I2C_TIMINGR_PRESC_Pos        (28U)

+#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */

+#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */

+

+/******************* Bit definition for I2C_TIMEOUTR register *******************/

+#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)

+#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */

+#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */

+#define I2C_TIMEOUTR_TIDLE_Pos       (12U)

+#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */

+#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */

+#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)

+#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */

+#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */

+#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)

+#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */

+#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/

+#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)

+#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */

+#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */

+

+/******************  Bit definition for I2C_ISR register  *********************/

+#define I2C_ISR_TXE_Pos              (0U)

+#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */

+#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */

+#define I2C_ISR_TXIS_Pos             (1U)

+#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */

+#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */

+#define I2C_ISR_RXNE_Pos             (2U)

+#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */

+#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */

+#define I2C_ISR_ADDR_Pos             (3U)

+#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */

+#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/

+#define I2C_ISR_NACKF_Pos            (4U)

+#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */

+#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */

+#define I2C_ISR_STOPF_Pos            (5U)

+#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */

+#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */

+#define I2C_ISR_TC_Pos               (6U)

+#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */

+#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */

+#define I2C_ISR_TCR_Pos              (7U)

+#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */

+#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */

+#define I2C_ISR_BERR_Pos             (8U)

+#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */

+#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */

+#define I2C_ISR_ARLO_Pos             (9U)

+#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */

+#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */

+#define I2C_ISR_OVR_Pos              (10U)

+#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */

+#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */

+#define I2C_ISR_PECERR_Pos           (11U)

+#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */

+#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */

+#define I2C_ISR_TIMEOUT_Pos          (12U)

+#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */

+#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */

+#define I2C_ISR_ALERT_Pos            (13U)

+#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */

+#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */

+#define I2C_ISR_BUSY_Pos             (15U)

+#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */

+#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */

+#define I2C_ISR_DIR_Pos              (16U)

+#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */

+#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */

+#define I2C_ISR_ADDCODE_Pos          (17U)

+#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */

+#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */

+

+/******************  Bit definition for I2C_ICR register  *********************/

+#define I2C_ICR_ADDRCF_Pos           (3U)

+#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */

+#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */

+#define I2C_ICR_NACKCF_Pos           (4U)

+#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */

+#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */

+#define I2C_ICR_STOPCF_Pos           (5U)

+#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */

+#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */

+#define I2C_ICR_BERRCF_Pos           (8U)

+#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */

+#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */

+#define I2C_ICR_ARLOCF_Pos           (9U)

+#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */

+#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */

+#define I2C_ICR_OVRCF_Pos            (10U)

+#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */

+#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */

+#define I2C_ICR_PECCF_Pos            (11U)

+#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */

+#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */

+#define I2C_ICR_TIMOUTCF_Pos         (12U)

+#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */

+#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */

+#define I2C_ICR_ALERTCF_Pos          (13U)

+#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */

+#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */

+

+/******************  Bit definition for I2C_PECR register  *********************/

+#define I2C_PECR_PEC_Pos             (0U)

+#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */

+#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */

+

+/******************  Bit definition for I2C_RXDR register  *********************/

+#define I2C_RXDR_RXDATA_Pos          (0U)

+#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */

+#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */

+

+/******************  Bit definition for I2C_TXDR register  *********************/

+#define I2C_TXDR_TXDATA_Pos          (0U)

+#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */

+#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           Independent WATCHDOG                             */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for IWDG_KR register  ********************/

+#define IWDG_KR_KEY_Pos      (0U)

+#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */

+#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */

+

+/*******************  Bit definition for IWDG_PR register  ********************/

+#define IWDG_PR_PR_Pos       (0U)

+#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */

+#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */

+#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */

+#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */

+#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */

+

+/*******************  Bit definition for IWDG_RLR register  *******************/

+#define IWDG_RLR_RL_Pos      (0U)

+#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */

+#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */

+

+/*******************  Bit definition for IWDG_SR register  ********************/

+#define IWDG_SR_PVU_Pos      (0U)

+#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */

+#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */

+#define IWDG_SR_RVU_Pos      (1U)

+#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */

+#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */

+#define IWDG_SR_WVU_Pos      (2U)

+#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */

+#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */

+

+/*******************  Bit definition for IWDG_KR register  ********************/

+#define IWDG_WINR_WIN_Pos    (0U)

+#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */

+#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */

+

+/******************************************************************************/

+/*                                                                            */

+/*                        JPEG Encoder/Decoder                                */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for CONFR0 register  ********************/

+#define JPEG_CONFR0_START_Pos           (0U)

+#define JPEG_CONFR0_START_Msk           (0x1UL << JPEG_CONFR0_START_Pos)       /*!< 0x00000001 */

+#define JPEG_CONFR0_START               JPEG_CONFR0_START_Msk                  /*!<Start/Stop bit */

+

+/********************  Bit definition for CONFR1 register  ********************/

+#define JPEG_CONFR1_NF_Pos              (0U)

+#define JPEG_CONFR1_NF_Msk              (0x3UL << JPEG_CONFR1_NF_Pos)          /*!< 0x00000003 */

+#define JPEG_CONFR1_NF                  JPEG_CONFR1_NF_Msk                     /*!<Number of color components */

+#define JPEG_CONFR1_NF_0                (0x1UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000001 */

+#define JPEG_CONFR1_NF_1                (0x2UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000002 */

+#define JPEG_CONFR1_DE_Pos              (3U)

+#define JPEG_CONFR1_DE_Msk              (0x1UL << JPEG_CONFR1_DE_Pos)          /*!< 0x00000008 */

+#define JPEG_CONFR1_DE                  JPEG_CONFR1_DE_Msk                     /*!<Decoding Enable */

+#define JPEG_CONFR1_COLORSPACE_Pos      (4U)

+#define JPEG_CONFR1_COLORSPACE_Msk      (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)  /*!< 0x00000030 */

+#define JPEG_CONFR1_COLORSPACE          JPEG_CONFR1_COLORSPACE_Msk             /*!<Color Space */

+#define JPEG_CONFR1_COLORSPACE_0        (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000010 */

+#define JPEG_CONFR1_COLORSPACE_1        (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000020 */

+#define JPEG_CONFR1_NS_Pos              (6U)

+#define JPEG_CONFR1_NS_Msk              (0x3UL << JPEG_CONFR1_NS_Pos)          /*!< 0x000000C0 */

+#define JPEG_CONFR1_NS                  JPEG_CONFR1_NS_Msk                     /*!<Number of components for Scan */

+#define JPEG_CONFR1_NS_0                (0x1UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR1_NS_1                (0x2UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR1_HDR_Pos             (8U)

+#define JPEG_CONFR1_HDR_Msk             (0x1UL << JPEG_CONFR1_HDR_Pos)         /*!< 0x00000100 */

+#define JPEG_CONFR1_HDR                 JPEG_CONFR1_HDR_Msk                    /*!<Header Processing On/Off */

+#define JPEG_CONFR1_YSIZE_Pos           (16U)

+#define JPEG_CONFR1_YSIZE_Msk           (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)    /*!< 0xFFFF0000 */

+#define JPEG_CONFR1_YSIZE               JPEG_CONFR1_YSIZE_Msk                  /*!<Number of lines in source image */

+

+/********************  Bit definition for CONFR2 register  ********************/

+#define JPEG_CONFR2_NMCU_Pos            (0U)

+#define JPEG_CONFR2_NMCU_Msk            (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)  /*!< 0x03FFFFFF */

+#define JPEG_CONFR2_NMCU                JPEG_CONFR2_NMCU_Msk                   /*!<Number of MCU units minus 1 to encode */

+

+/********************  Bit definition for CONFR3 register  ********************/

+#define JPEG_CONFR3_XSIZE_Pos           (16U)

+#define JPEG_CONFR3_XSIZE_Msk           (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)    /*!< 0xFFFF0000 */

+#define JPEG_CONFR3_XSIZE               JPEG_CONFR3_XSIZE_Msk                  /*!<Number of pixels per line */

+

+/********************  Bit definition for CONFR4 register  ********************/

+#define JPEG_CONFR4_HD_Pos              (0U)

+#define JPEG_CONFR4_HD_Msk              (0x1UL << JPEG_CONFR4_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR4_HD                  JPEG_CONFR4_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR4_HA_Pos              (1U)

+#define JPEG_CONFR4_HA_Msk              (0x1UL << JPEG_CONFR4_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR4_HA                  JPEG_CONFR4_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR4_QT_Pos              (2U)

+#define JPEG_CONFR4_QT_Msk              (0x3UL << JPEG_CONFR4_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR4_QT                  JPEG_CONFR4_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR4_QT_0                (0x1UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR4_QT_1                (0x2UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR4_NB_Pos              (4U)

+#define JPEG_CONFR4_NB_Msk              (0xFUL << JPEG_CONFR4_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR4_NB                  JPEG_CONFR4_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR4_NB_0                (0x1UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR4_NB_1                (0x2UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR4_NB_2                (0x4UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR4_NB_3                (0x8UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR4_VSF_Pos             (8U)

+#define JPEG_CONFR4_VSF_Msk             (0xFUL << JPEG_CONFR4_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR4_VSF                 JPEG_CONFR4_VSF_Msk                    /*!<Vertical sampling factor for component 1 */

+#define JPEG_CONFR4_VSF_0               (0x1UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR4_VSF_1               (0x2UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR4_VSF_2               (0x4UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR4_VSF_3               (0x8UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR4_HSF_Pos             (12U)

+#define JPEG_CONFR4_HSF_Msk             (0xFUL << JPEG_CONFR4_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR4_HSF                 JPEG_CONFR4_HSF_Msk                    /*!<Horizontal sampling factor for component 1 */

+#define JPEG_CONFR4_HSF_0               (0x1UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR4_HSF_1               (0x2UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR4_HSF_2               (0x4UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR4_HSF_3               (0x8UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR5 register  ********************/

+#define JPEG_CONFR5_HD_Pos              (0U)

+#define JPEG_CONFR5_HD_Msk              (0x1UL << JPEG_CONFR5_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR5_HD                  JPEG_CONFR5_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR5_HA_Pos              (1U)

+#define JPEG_CONFR5_HA_Msk              (0x1UL << JPEG_CONFR5_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR5_HA                  JPEG_CONFR5_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR5_QT_Pos              (2U)

+#define JPEG_CONFR5_QT_Msk              (0x3UL << JPEG_CONFR5_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR5_QT                  JPEG_CONFR5_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR5_QT_0                (0x1UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR5_QT_1                (0x2UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR5_NB_Pos              (4U)

+#define JPEG_CONFR5_NB_Msk              (0xFUL << JPEG_CONFR5_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR5_NB                  JPEG_CONFR5_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR5_NB_0                (0x1UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR5_NB_1                (0x2UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR5_NB_2                (0x4UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR5_NB_3                (0x8UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR5_VSF_Pos             (8U)

+#define JPEG_CONFR5_VSF_Msk             (0xFUL << JPEG_CONFR5_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR5_VSF                 JPEG_CONFR5_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR5_VSF_0               (0x1UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR5_VSF_1               (0x2UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR5_VSF_2               (0x4UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR5_VSF_3               (0x8UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR5_HSF_Pos             (12U)

+#define JPEG_CONFR5_HSF_Msk             (0xFUL << JPEG_CONFR5_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR5_HSF                 JPEG_CONFR5_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR5_HSF_0               (0x1UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR5_HSF_1               (0x2UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR5_HSF_2               (0x4UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR5_HSF_3               (0x8UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR6 register  ********************/

+#define JPEG_CONFR6_HD_Pos              (0U)

+#define JPEG_CONFR6_HD_Msk              (0x1UL << JPEG_CONFR6_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR6_HD                  JPEG_CONFR6_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR6_HA_Pos              (1U)

+#define JPEG_CONFR6_HA_Msk              (0x1UL << JPEG_CONFR6_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR6_HA                  JPEG_CONFR6_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR6_QT_Pos              (2U)

+#define JPEG_CONFR6_QT_Msk              (0x3UL << JPEG_CONFR6_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR6_QT                  JPEG_CONFR6_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR6_QT_0                (0x1UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR6_QT_1                (0x2UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR6_NB_Pos              (4U)

+#define JPEG_CONFR6_NB_Msk              (0xFUL << JPEG_CONFR6_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR6_NB                  JPEG_CONFR6_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR6_NB_0                (0x1UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR6_NB_1                (0x2UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR6_NB_2                (0x4UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR6_NB_3                (0x8UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR6_VSF_Pos             (8U)

+#define JPEG_CONFR6_VSF_Msk             (0xFUL << JPEG_CONFR6_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR6_VSF                 JPEG_CONFR6_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR6_VSF_0               (0x1UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR6_VSF_1               (0x2UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR6_VSF_2               (0x4UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR6_VSF_3               (0x8UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR6_HSF_Pos             (12U)

+#define JPEG_CONFR6_HSF_Msk             (0xFUL << JPEG_CONFR6_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR6_HSF                 JPEG_CONFR6_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR6_HSF_0               (0x1UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR6_HSF_1               (0x2UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR6_HSF_2               (0x4UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR6_HSF_3               (0x8UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR7 register  ********************/

+#define JPEG_CONFR7_HD_Pos              (0U)

+#define JPEG_CONFR7_HD_Msk              (0x1UL << JPEG_CONFR7_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR7_HD                  JPEG_CONFR7_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR7_HA_Pos              (1U)

+#define JPEG_CONFR7_HA_Msk              (0x1UL << JPEG_CONFR7_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR7_HA                  JPEG_CONFR7_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR7_QT_Pos              (2U)

+#define JPEG_CONFR7_QT_Msk              (0x3UL << JPEG_CONFR7_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR7_QT                  JPEG_CONFR7_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR7_QT_0                (0x1UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR7_QT_1                (0x2UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR7_NB_Pos              (4U)

+#define JPEG_CONFR7_NB_Msk              (0xFUL << JPEG_CONFR7_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR7_NB                  JPEG_CONFR7_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR7_NB_0                (0x1UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR7_NB_1                (0x2UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR7_NB_2                (0x4UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR7_NB_3                (0x8UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR7_VSF_Pos             (8U)

+#define JPEG_CONFR7_VSF_Msk             (0xFUL << JPEG_CONFR7_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR7_VSF                 JPEG_CONFR7_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR7_VSF_0               (0x1UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR7_VSF_1               (0x2UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR7_VSF_2               (0x4UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR7_VSF_3               (0x8UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR7_HSF_Pos             (12U)

+#define JPEG_CONFR7_HSF_Msk             (0xFUL << JPEG_CONFR7_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR7_HSF                 JPEG_CONFR7_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR7_HSF_0               (0x1UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR7_HSF_1               (0x2UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR7_HSF_2               (0x4UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR7_HSF_3               (0x8UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CR register  ********************/

+#define JPEG_CR_JCEN_Pos                (0U)

+#define JPEG_CR_JCEN_Msk                (0x1UL << JPEG_CR_JCEN_Pos)            /*!< 0x00000001 */

+#define JPEG_CR_JCEN                    JPEG_CR_JCEN_Msk                       /*!<Enable the JPEG Codec Core */

+#define JPEG_CR_IFTIE_Pos               (1U)

+#define JPEG_CR_IFTIE_Msk               (0x1UL << JPEG_CR_IFTIE_Pos)           /*!< 0x00000002 */

+#define JPEG_CR_IFTIE                   JPEG_CR_IFTIE_Msk                      /*!<Input FIFO Threshold Interrupt Enable */

+#define JPEG_CR_IFNFIE_Pos              (2U)

+#define JPEG_CR_IFNFIE_Msk              (0x1UL << JPEG_CR_IFNFIE_Pos)          /*!< 0x00000004 */

+#define JPEG_CR_IFNFIE                  JPEG_CR_IFNFIE_Msk                     /*!<Input FIFO Not Full Interrupt Enable */

+#define JPEG_CR_OFTIE_Pos               (3U)

+#define JPEG_CR_OFTIE_Msk               (0x1UL << JPEG_CR_OFTIE_Pos)           /*!< 0x00000008 */

+#define JPEG_CR_OFTIE                   JPEG_CR_OFTIE_Msk                      /*!<Output FIFO Threshold Interrupt Enable */

+#define JPEG_CR_OFNEIE_Pos              (4U)

+#define JPEG_CR_OFNEIE_Msk              (0x1UL << JPEG_CR_OFNEIE_Pos)          /*!< 0x00000010 */

+#define JPEG_CR_OFNEIE                  JPEG_CR_OFNEIE_Msk                     /*!<Output FIFO Not Empty Interrupt Enable */

+#define JPEG_CR_EOCIE_Pos               (5U)

+#define JPEG_CR_EOCIE_Msk               (0x1UL << JPEG_CR_EOCIE_Pos)           /*!< 0x00000020 */

+#define JPEG_CR_EOCIE                   JPEG_CR_EOCIE_Msk                      /*!<End of Conversion Interrupt Enable */

+#define JPEG_CR_HPDIE_Pos               (6U)

+#define JPEG_CR_HPDIE_Msk               (0x1UL << JPEG_CR_HPDIE_Pos)           /*!< 0x00000040 */

+#define JPEG_CR_HPDIE                   JPEG_CR_HPDIE_Msk                      /*!<Header Parsing Done Interrupt Enable */

+#define JPEG_CR_IFF_Pos                 (13U)

+#define JPEG_CR_IFF_Msk                 (0x1UL << JPEG_CR_IFF_Pos)             /*!< 0x00002000 */

+#define JPEG_CR_IFF                     JPEG_CR_IFF_Msk                        /*!<Flush the input FIFO */

+#define JPEG_CR_OFF_Pos                 (14U)

+#define JPEG_CR_OFF_Msk                 (0x1UL << JPEG_CR_OFF_Pos)             /*!< 0x00004000 */

+#define JPEG_CR_OFF                     JPEG_CR_OFF_Msk                        /*!<Flush the output FIFO */

+

+/********************  Bit definition for SR register  ********************/

+#define JPEG_SR_IFTF_Pos                (1U)

+#define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */

+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is bellow its threshold flag */

+#define JPEG_SR_IFNFF_Pos               (2U)

+#define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */

+#define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */

+#define JPEG_SR_OFTF_Pos                (3U)

+#define JPEG_SR_OFTF_Msk                (0x1UL << JPEG_SR_OFTF_Pos)            /*!< 0x00000008 */

+#define JPEG_SR_OFTF                    JPEG_SR_OFTF_Msk                       /*!<Output FIFO is not empty and has reach its threshold */

+#define JPEG_SR_OFNEF_Pos               (4U)

+#define JPEG_SR_OFNEF_Msk               (0x1UL << JPEG_SR_OFNEF_Pos)           /*!< 0x00000010 */

+#define JPEG_SR_OFNEF                   JPEG_SR_OFNEF_Msk                      /*!<Output FIFO is not empty, a data is available */

+#define JPEG_SR_EOCF_Pos                (5U)

+#define JPEG_SR_EOCF_Msk                (0x1UL << JPEG_SR_EOCF_Pos)            /*!< 0x00000020 */

+#define JPEG_SR_EOCF                    JPEG_SR_EOCF_Msk                       /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */

+#define JPEG_SR_HPDF_Pos                (6U)

+#define JPEG_SR_HPDF_Msk                (0x1UL << JPEG_SR_HPDF_Pos)            /*!< 0x00000040 */

+#define JPEG_SR_HPDF                    JPEG_SR_HPDF_Msk                       /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */

+#define JPEG_SR_COF_Pos                 (7U)

+#define JPEG_SR_COF_Msk                 (0x1UL << JPEG_SR_COF_Pos)             /*!< 0x00000080 */

+#define JPEG_SR_COF                     JPEG_SR_COF_Msk                        /*!<JPEG Codec operation on going flag */

+

+/********************  Bit definition for CFR register  ********************/

+#define JPEG_CFR_CEOCF_Pos              (4U)

+#define JPEG_CFR_CEOCF_Msk              (0x1UL << JPEG_CFR_CEOCF_Pos)          /*!< 0x00000010 */

+#define JPEG_CFR_CEOCF                  JPEG_CFR_CEOCF_Msk                     /*!<Clear End of Conversion Flag */

+#define JPEG_CFR_CHPDF_Pos              (5U)

+#define JPEG_CFR_CHPDF_Msk              (0x1UL << JPEG_CFR_CHPDF_Pos)          /*!< 0x00000020 */

+#define JPEG_CFR_CHPDF                  JPEG_CFR_CHPDF_Msk                     /*!<Clear Header Parsing Done Flag */

+

+/********************  Bit definition for DIR register  ********************/

+#define JPEG_DIR_DATAIN_Pos             (0U)

+#define JPEG_DIR_DATAIN_Msk             (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)  /*!< 0xFFFFFFFF */

+#define JPEG_DIR_DATAIN                 JPEG_DIR_DATAIN_Msk                    /*!<Data Input FIFO */

+

+/********************  Bit definition for DOR register  ********************/

+#define JPEG_DOR_DATAOUT_Pos            (0U)

+#define JPEG_DOR_DATAOUT_Msk            (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */

+#define JPEG_DOR_DATAOUT                JPEG_DOR_DATAOUT_Msk                   /*!<Data Output FIFO */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      LCD-TFT Display Controller (LTDC)                     */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for LTDC_SSCR register  *****************/

+

+#define LTDC_SSCR_VSH_Pos            (0U)

+#define LTDC_SSCR_VSH_Msk            (0x7FFUL << LTDC_SSCR_VSH_Pos)            /*!< 0x000007FF */

+#define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height  */

+#define LTDC_SSCR_HSW_Pos            (16U)

+#define LTDC_SSCR_HSW_Msk            (0xFFFUL << LTDC_SSCR_HSW_Pos)            /*!< 0x0FFF0000 */

+#define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */

+

+/********************  Bit definition for LTDC_BPCR register  *****************/

+

+#define LTDC_BPCR_AVBP_Pos           (0U)

+#define LTDC_BPCR_AVBP_Msk           (0x7FFUL << LTDC_BPCR_AVBP_Pos)           /*!< 0x000007FF */

+#define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch   */

+#define LTDC_BPCR_AHBP_Pos           (16U)

+#define LTDC_BPCR_AHBP_Msk           (0xFFFUL << LTDC_BPCR_AHBP_Pos)           /*!< 0x0FFF0000 */

+#define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */

+

+/********************  Bit definition for LTDC_AWCR register  *****************/

+

+#define LTDC_AWCR_AAH_Pos            (0U)

+#define LTDC_AWCR_AAH_Msk            (0x7FFUL << LTDC_AWCR_AAH_Pos)            /*!< 0x000007FF */

+#define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active heigh */

+#define LTDC_AWCR_AAW_Pos            (16U)

+#define LTDC_AWCR_AAW_Msk            (0xFFFUL << LTDC_AWCR_AAW_Pos)            /*!< 0x0FFF0000 */

+#define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */

+

+/********************  Bit definition for LTDC_TWCR register  *****************/

+

+#define LTDC_TWCR_TOTALH_Pos         (0U)

+#define LTDC_TWCR_TOTALH_Msk         (0x7FFUL << LTDC_TWCR_TOTALH_Pos)         /*!< 0x000007FF */

+#define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total Heigh */

+#define LTDC_TWCR_TOTALW_Pos         (16U)

+#define LTDC_TWCR_TOTALW_Msk         (0xFFFUL << LTDC_TWCR_TOTALW_Pos)         /*!< 0x0FFF0000 */

+#define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */

+

+/********************  Bit definition for LTDC_GCR register  ******************/

+

+#define LTDC_GCR_LTDCEN_Pos          (0U)

+#define LTDC_GCR_LTDCEN_Msk          (0x1UL << LTDC_GCR_LTDCEN_Pos)            /*!< 0x00000001 */

+#define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit       */

+#define LTDC_GCR_DBW_Pos             (4U)

+#define LTDC_GCR_DBW_Msk             (0x7UL << LTDC_GCR_DBW_Pos)               /*!< 0x00000070 */

+#define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width                   */

+#define LTDC_GCR_DGW_Pos             (8U)

+#define LTDC_GCR_DGW_Msk             (0x7UL << LTDC_GCR_DGW_Pos)               /*!< 0x00000700 */

+#define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width                  */

+#define LTDC_GCR_DRW_Pos             (12U)

+#define LTDC_GCR_DRW_Msk             (0x7UL << LTDC_GCR_DRW_Pos)               /*!< 0x00007000 */

+#define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width                    */

+#define LTDC_GCR_DEN_Pos             (16U)

+#define LTDC_GCR_DEN_Msk             (0x1UL << LTDC_GCR_DEN_Pos)               /*!< 0x00010000 */

+#define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable                       */

+#define LTDC_GCR_PCPOL_Pos           (28U)

+#define LTDC_GCR_PCPOL_Msk           (0x1UL << LTDC_GCR_PCPOL_Pos)             /*!< 0x10000000 */

+#define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity                */

+#define LTDC_GCR_DEPOL_Pos           (29U)

+#define LTDC_GCR_DEPOL_Msk           (0x1UL << LTDC_GCR_DEPOL_Pos)             /*!< 0x20000000 */

+#define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity                */

+#define LTDC_GCR_VSPOL_Pos           (30U)

+#define LTDC_GCR_VSPOL_Msk           (0x1UL << LTDC_GCR_VSPOL_Pos)             /*!< 0x40000000 */

+#define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity   */

+#define LTDC_GCR_HSPOL_Pos           (31U)

+#define LTDC_GCR_HSPOL_Msk           (0x1UL << LTDC_GCR_HSPOL_Pos)             /*!< 0x80000000 */

+#define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */

+

+

+/********************  Bit definition for LTDC_SRCR register  *****************/

+

+#define LTDC_SRCR_IMR_Pos            (0U)

+#define LTDC_SRCR_IMR_Msk            (0x1UL << LTDC_SRCR_IMR_Pos)              /*!< 0x00000001 */

+#define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload         */

+#define LTDC_SRCR_VBR_Pos            (1U)

+#define LTDC_SRCR_VBR_Msk            (0x1UL << LTDC_SRCR_VBR_Pos)              /*!< 0x00000002 */

+#define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */

+

+/********************  Bit definition for LTDC_BCCR register  *****************/

+

+#define LTDC_BCCR_BCBLUE_Pos         (0U)

+#define LTDC_BCCR_BCBLUE_Msk         (0xFFUL << LTDC_BCCR_BCBLUE_Pos)          /*!< 0x000000FF */

+#define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value  */

+#define LTDC_BCCR_BCGREEN_Pos        (8U)

+#define LTDC_BCCR_BCGREEN_Msk        (0xFFUL << LTDC_BCCR_BCGREEN_Pos)         /*!< 0x0000FF00 */

+#define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */

+#define LTDC_BCCR_BCRED_Pos          (16U)

+#define LTDC_BCCR_BCRED_Msk          (0xFFUL << LTDC_BCCR_BCRED_Pos)           /*!< 0x00FF0000 */

+#define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value   */

+

+/********************  Bit definition for LTDC_IER register  ******************/

+

+#define LTDC_IER_LIE_Pos             (0U)

+#define LTDC_IER_LIE_Msk             (0x1UL << LTDC_IER_LIE_Pos)               /*!< 0x00000001 */

+#define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable            */

+#define LTDC_IER_FUIE_Pos            (1U)

+#define LTDC_IER_FUIE_Msk            (0x1UL << LTDC_IER_FUIE_Pos)              /*!< 0x00000002 */

+#define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable   */

+#define LTDC_IER_TERRIE_Pos          (2U)

+#define LTDC_IER_TERRIE_Msk          (0x1UL << LTDC_IER_TERRIE_Pos)            /*!< 0x00000004 */

+#define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable  */

+#define LTDC_IER_RRIE_Pos            (3U)

+#define LTDC_IER_RRIE_Msk            (0x1UL << LTDC_IER_RRIE_Pos)              /*!< 0x00000008 */

+#define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */

+

+/********************  Bit definition for LTDC_ISR register  ******************/

+

+#define LTDC_ISR_LIF_Pos             (0U)

+#define LTDC_ISR_LIF_Msk             (0x1UL << LTDC_ISR_LIF_Pos)               /*!< 0x00000001 */

+#define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */

+#define LTDC_ISR_FUIF_Pos            (1U)

+#define LTDC_ISR_FUIF_Msk            (0x1UL << LTDC_ISR_FUIF_Pos)              /*!< 0x00000002 */

+#define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */

+#define LTDC_ISR_TERRIF_Pos          (2U)

+#define LTDC_ISR_TERRIF_Msk          (0x1UL << LTDC_ISR_TERRIF_Pos)            /*!< 0x00000004 */

+#define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */

+#define LTDC_ISR_RRIF_Pos            (3U)

+#define LTDC_ISR_RRIF_Msk            (0x1UL << LTDC_ISR_RRIF_Pos)              /*!< 0x00000008 */

+#define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */

+

+/********************  Bit definition for LTDC_ICR register  ******************/

+

+#define LTDC_ICR_CLIF_Pos            (0U)

+#define LTDC_ICR_CLIF_Msk            (0x1UL << LTDC_ICR_CLIF_Pos)              /*!< 0x00000001 */

+#define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */

+#define LTDC_ICR_CFUIF_Pos           (1U)

+#define LTDC_ICR_CFUIF_Msk           (0x1UL << LTDC_ICR_CFUIF_Pos)             /*!< 0x00000002 */

+#define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */

+#define LTDC_ICR_CTERRIF_Pos         (2U)

+#define LTDC_ICR_CTERRIF_Msk         (0x1UL << LTDC_ICR_CTERRIF_Pos)           /*!< 0x00000004 */

+#define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */

+#define LTDC_ICR_CRRIF_Pos           (3U)

+#define LTDC_ICR_CRRIF_Msk           (0x1UL << LTDC_ICR_CRRIF_Pos)             /*!< 0x00000008 */

+#define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */

+

+/********************  Bit definition for LTDC_LIPCR register  ****************/

+

+#define LTDC_LIPCR_LIPOS_Pos         (0U)

+#define LTDC_LIPCR_LIPOS_Msk         (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)         /*!< 0x000007FF */

+#define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */

+

+/********************  Bit definition for LTDC_CPSR register  *****************/

+

+#define LTDC_CPSR_CYPOS_Pos          (0U)

+#define LTDC_CPSR_CYPOS_Msk          (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)         /*!< 0x0000FFFF */

+#define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */

+#define LTDC_CPSR_CXPOS_Pos          (16U)

+#define LTDC_CPSR_CXPOS_Msk          (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)         /*!< 0xFFFF0000 */

+#define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */

+

+/********************  Bit definition for LTDC_CDSR register  *****************/

+

+#define LTDC_CDSR_VDES_Pos           (0U)

+#define LTDC_CDSR_VDES_Msk           (0x1UL << LTDC_CDSR_VDES_Pos)             /*!< 0x00000001 */

+#define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status       */

+#define LTDC_CDSR_HDES_Pos           (1U)

+#define LTDC_CDSR_HDES_Msk           (0x1UL << LTDC_CDSR_HDES_Pos)             /*!< 0x00000002 */

+#define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status     */

+#define LTDC_CDSR_VSYNCS_Pos         (2U)

+#define LTDC_CDSR_VSYNCS_Msk         (0x1UL << LTDC_CDSR_VSYNCS_Pos)           /*!< 0x00000004 */

+#define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status   */

+#define LTDC_CDSR_HSYNCS_Pos         (3U)

+#define LTDC_CDSR_HSYNCS_Msk         (0x1UL << LTDC_CDSR_HSYNCS_Pos)           /*!< 0x00000008 */

+#define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */

+

+/********************  Bit definition for LTDC_LxCR register  *****************/

+

+#define LTDC_LxCR_LEN_Pos            (0U)

+#define LTDC_LxCR_LEN_Msk            (0x1UL << LTDC_LxCR_LEN_Pos)              /*!< 0x00000001 */

+#define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable              */

+#define LTDC_LxCR_COLKEN_Pos         (1U)

+#define LTDC_LxCR_COLKEN_Msk         (0x1UL << LTDC_LxCR_COLKEN_Pos)           /*!< 0x00000002 */

+#define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable       */

+#define LTDC_LxCR_CLUTEN_Pos         (4U)

+#define LTDC_LxCR_CLUTEN_Msk         (0x1UL << LTDC_LxCR_CLUTEN_Pos)           /*!< 0x00000010 */

+#define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */

+

+/********************  Bit definition for LTDC_LxWHPCR register  **************/

+

+#define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)

+#define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)     /*!< 0x00000FFF */

+#define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */

+#define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)

+#define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)    /*!< 0xFFFF0000 */

+#define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position  */

+

+/********************  Bit definition for LTDC_LxWVPCR register  **************/

+

+#define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)

+#define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)     /*!< 0x00000FFF */

+#define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */

+#define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)

+#define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)    /*!< 0xFFFF0000 */

+#define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position  */

+

+/********************  Bit definition for LTDC_LxCKCR register  ***************/

+

+#define LTDC_LxCKCR_CKBLUE_Pos       (0U)

+#define LTDC_LxCKCR_CKBLUE_Msk       (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value  */

+#define LTDC_LxCKCR_CKGREEN_Pos      (8U)

+#define LTDC_LxCKCR_CKGREEN_Msk      (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */

+#define LTDC_LxCKCR_CKRED_Pos        (16U)

+#define LTDC_LxCKCR_CKRED_Msk        (0xFFUL << LTDC_LxCKCR_CKRED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value   */

+

+/********************  Bit definition for LTDC_LxPFCR register  ***************/

+

+#define LTDC_LxPFCR_PF_Pos           (0U)

+#define LTDC_LxPFCR_PF_Msk           (0x7UL << LTDC_LxPFCR_PF_Pos)             /*!< 0x00000007 */

+#define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */

+

+/********************  Bit definition for LTDC_LxCACR register  ***************/

+

+#define LTDC_LxCACR_CONSTA_Pos       (0U)

+#define LTDC_LxCACR_CONSTA_Msk       (0xFFUL << LTDC_LxCACR_CONSTA_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */

+

+/********************  Bit definition for LTDC_LxDCCR register  ***************/

+

+#define LTDC_LxDCCR_DCBLUE_Pos       (0U)

+#define LTDC_LxDCCR_DCBLUE_Msk       (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue  */

+#define LTDC_LxDCCR_DCGREEN_Pos      (8U)

+#define LTDC_LxDCCR_DCGREEN_Msk      (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */

+#define LTDC_LxDCCR_DCRED_Pos        (16U)

+#define LTDC_LxDCCR_DCRED_Msk        (0xFFUL << LTDC_LxDCCR_DCRED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red   */

+#define LTDC_LxDCCR_DCALPHA_Pos      (24U)

+#define LTDC_LxDCCR_DCALPHA_Msk      (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)       /*!< 0xFF000000 */

+#define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */

+

+/********************  Bit definition for LTDC_LxBFCR register  ***************/

+

+#define LTDC_LxBFCR_BF2_Pos          (0U)

+#define LTDC_LxBFCR_BF2_Msk          (0x7UL << LTDC_LxBFCR_BF2_Pos)            /*!< 0x00000007 */

+#define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */

+#define LTDC_LxBFCR_BF1_Pos          (8U)

+#define LTDC_LxBFCR_BF1_Msk          (0x7UL << LTDC_LxBFCR_BF1_Pos)            /*!< 0x00000700 */

+#define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */

+

+/********************  Bit definition for LTDC_LxCFBAR register  **************/

+

+#define LTDC_LxCFBAR_CFBADD_Pos      (0U)

+#define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */

+#define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */

+

+/********************  Bit definition for LTDC_LxCFBLR register  **************/

+

+#define LTDC_LxCFBLR_CFBLL_Pos       (0U)

+#define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)      /*!< 0x00001FFF */

+#define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length    */

+#define LTDC_LxCFBLR_CFBP_Pos        (16U)

+#define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)       /*!< 0x1FFF0000 */

+#define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */

+

+/********************  Bit definition for LTDC_LxCFBLNR register  *************/

+

+#define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)

+#define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)    /*!< 0x000007FF */

+#define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */

+

+/********************  Bit definition for LTDC_LxCLUTWR register  *************/

+

+#define LTDC_LxCLUTWR_BLUE_Pos       (0U)

+#define LTDC_LxCLUTWR_BLUE_Msk       (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value   */

+#define LTDC_LxCLUTWR_GREEN_Pos      (8U)

+#define LTDC_LxCLUTWR_GREEN_Msk      (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value  */

+#define LTDC_LxCLUTWR_RED_Pos        (16U)

+#define LTDC_LxCLUTWR_RED_Msk        (0xFFUL << LTDC_LxCLUTWR_RED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value    */

+#define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)

+#define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)     /*!< 0xFF000000 */

+#define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                     MDMA                                   */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for MDMA_GISR0 register  ****************/

+#define MDMA_GISR0_GIF0_Pos       (0U)

+#define MDMA_GISR0_GIF0_Msk       (0x1UL << MDMA_GISR0_GIF0_Pos)               /*!< 0x00000001 */

+#define MDMA_GISR0_GIF0           MDMA_GISR0_GIF0_Msk                          /*!< Channel 0 global interrupt flag */

+#define MDMA_GISR0_GIF1_Pos       (1U)

+#define MDMA_GISR0_GIF1_Msk       (0x1UL << MDMA_GISR0_GIF1_Pos)               /*!< 0x00000002 */

+#define MDMA_GISR0_GIF1           MDMA_GISR0_GIF1_Msk                          /*!< Channel 1 global interrupt flag */

+#define MDMA_GISR0_GIF2_Pos       (2U)

+#define MDMA_GISR0_GIF2_Msk       (0x1UL << MDMA_GISR0_GIF2_Pos)               /*!< 0x00000004 */

+#define MDMA_GISR0_GIF2           MDMA_GISR0_GIF2_Msk                          /*!< Channel 2 global interrupt flag */

+#define MDMA_GISR0_GIF3_Pos       (3U)

+#define MDMA_GISR0_GIF3_Msk       (0x1UL << MDMA_GISR0_GIF3_Pos)               /*!< 0x00000008 */

+#define MDMA_GISR0_GIF3           MDMA_GISR0_GIF3_Msk                          /*!< Channel 3 global interrupt flag */

+#define MDMA_GISR0_GIF4_Pos       (4U)

+#define MDMA_GISR0_GIF4_Msk       (0x1UL << MDMA_GISR0_GIF4_Pos)               /*!< 0x00000010 */

+#define MDMA_GISR0_GIF4           MDMA_GISR0_GIF4_Msk                          /*!< Channel 4 global interrupt flag */

+#define MDMA_GISR0_GIF5_Pos       (5U)

+#define MDMA_GISR0_GIF5_Msk       (0x1UL << MDMA_GISR0_GIF5_Pos)               /*!< 0x00000020 */

+#define MDMA_GISR0_GIF5           MDMA_GISR0_GIF5_Msk                          /*!< Channel 5 global interrupt flag */

+#define MDMA_GISR0_GIF6_Pos       (6U)

+#define MDMA_GISR0_GIF6_Msk       (0x1UL << MDMA_GISR0_GIF6_Pos)               /*!< 0x00000040 */

+#define MDMA_GISR0_GIF6           MDMA_GISR0_GIF6_Msk                          /*!< Channel 6 global interrupt flag */

+#define MDMA_GISR0_GIF7_Pos       (7U)

+#define MDMA_GISR0_GIF7_Msk       (0x1UL << MDMA_GISR0_GIF7_Pos)               /*!< 0x00000080 */

+#define MDMA_GISR0_GIF7           MDMA_GISR0_GIF7_Msk                          /*!< Channel 7 global interrupt flag */

+#define MDMA_GISR0_GIF8_Pos       (8U)

+#define MDMA_GISR0_GIF8_Msk       (0x1UL << MDMA_GISR0_GIF8_Pos)               /*!< 0x00000100 */

+#define MDMA_GISR0_GIF8           MDMA_GISR0_GIF8_Msk                          /*!< Channel 8 global interrupt flag */

+#define MDMA_GISR0_GIF9_Pos       (9U)

+#define MDMA_GISR0_GIF9_Msk       (0x1UL << MDMA_GISR0_GIF9_Pos)               /*!< 0x00000200 */

+#define MDMA_GISR0_GIF9           MDMA_GISR0_GIF9_Msk                          /*!< Channel 9 global interrupt flag */

+#define MDMA_GISR0_GIF10_Pos      (10U)

+#define MDMA_GISR0_GIF10_Msk      (0x1UL << MDMA_GISR0_GIF10_Pos)              /*!< 0x00000400 */

+#define MDMA_GISR0_GIF10          MDMA_GISR0_GIF10_Msk                         /*!< Channel 10 global interrupt flag */

+#define MDMA_GISR0_GIF11_Pos      (11U)

+#define MDMA_GISR0_GIF11_Msk      (0x1UL << MDMA_GISR0_GIF11_Pos)              /*!< 0x00000800 */

+#define MDMA_GISR0_GIF11          MDMA_GISR0_GIF11_Msk                         /*!< Channel 11 global interrupt flag */

+#define MDMA_GISR0_GIF12_Pos      (12U)

+#define MDMA_GISR0_GIF12_Msk      (0x1UL << MDMA_GISR0_GIF12_Pos)              /*!< 0x00001000 */

+#define MDMA_GISR0_GIF12          MDMA_GISR0_GIF12_Msk                         /*!< Channel 12 global interrupt flag */

+#define MDMA_GISR0_GIF13_Pos      (13U)

+#define MDMA_GISR0_GIF13_Msk      (0x1UL << MDMA_GISR0_GIF13_Pos)              /*!< 0x00002000 */

+#define MDMA_GISR0_GIF13          MDMA_GISR0_GIF13_Msk                         /*!< Channel 13 global interrupt flag */

+#define MDMA_GISR0_GIF14_Pos      (14U)

+#define MDMA_GISR0_GIF14_Msk      (0x1UL << MDMA_GISR0_GIF14_Pos)              /*!< 0x00004000 */

+#define MDMA_GISR0_GIF14          MDMA_GISR0_GIF14_Msk                         /*!< Channel 14 global interrupt flag */

+#define MDMA_GISR0_GIF15_Pos      (15U)

+#define MDMA_GISR0_GIF15_Msk      (0x1UL << MDMA_GISR0_GIF15_Pos)              /*!< 0x00008000 */

+#define MDMA_GISR0_GIF15          MDMA_GISR0_GIF15_Msk                         /*!< Channel 15 global interrupt flag */

+

+/********************  Bit definition for MDMA_CxISR register  ****************/

+#define MDMA_CISR_TEIF_Pos        (0U)

+#define MDMA_CISR_TEIF_Msk        (0x1UL << MDMA_CISR_TEIF_Pos)                /*!< 0x00000001 */

+#define MDMA_CISR_TEIF            MDMA_CISR_TEIF_Msk                           /*!< Channel x transfer error interrupt flag */

+#define MDMA_CISR_CTCIF_Pos       (1U)

+#define MDMA_CISR_CTCIF_Msk       (0x1UL << MDMA_CISR_CTCIF_Pos)               /*!< 0x00000002 */

+#define MDMA_CISR_CTCIF           MDMA_CISR_CTCIF_Msk                          /*!< Channel x Channel Transfer Complete interrupt flag */

+#define MDMA_CISR_BRTIF_Pos       (2U)

+#define MDMA_CISR_BRTIF_Msk       (0x1UL << MDMA_CISR_BRTIF_Pos)               /*!< 0x00000004 */

+#define MDMA_CISR_BRTIF           MDMA_CISR_BRTIF_Msk                          /*!< Channel x block repeat transfer complete interrupt flag */

+#define MDMA_CISR_BTIF_Pos        (3U)

+#define MDMA_CISR_BTIF_Msk        (0x1UL << MDMA_CISR_BTIF_Pos)                /*!< 0x00000008 */

+#define MDMA_CISR_BTIF            MDMA_CISR_BTIF_Msk                           /*!< Channel x block transfer complete interrupt flag */

+#define MDMA_CISR_TCIF_Pos        (4U)

+#define MDMA_CISR_TCIF_Msk        (0x1UL << MDMA_CISR_TCIF_Pos)                /*!< 0x00000010 */

+#define MDMA_CISR_TCIF            MDMA_CISR_TCIF_Msk                           /*!< Channel x buffer transfer complete interrupt flag */

+#define MDMA_CISR_CRQA_Pos        (16U)

+#define MDMA_CISR_CRQA_Msk        (0x1UL << MDMA_CISR_CRQA_Pos)                /*!< 0x00010000 */

+#define MDMA_CISR_CRQA            MDMA_CISR_CRQA_Msk                           /*!< Channel x ReQest Active flag */

+

+/********************  Bit definition for MDMA_CxIFCR register  ****************/

+#define MDMA_CIFCR_CTEIF_Pos      (0U)

+#define MDMA_CIFCR_CTEIF_Msk      (0x1UL << MDMA_CIFCR_CTEIF_Pos)              /*!< 0x00000001 */

+#define MDMA_CIFCR_CTEIF          MDMA_CIFCR_CTEIF_Msk                         /*!< Channel x clear transfer error interrupt flag */

+#define MDMA_CIFCR_CCTCIF_Pos     (1U)

+#define MDMA_CIFCR_CCTCIF_Msk     (0x1UL << MDMA_CIFCR_CCTCIF_Pos)             /*!< 0x00000002 */

+#define MDMA_CIFCR_CCTCIF         MDMA_CIFCR_CCTCIF_Msk                        /*!< Clear Channel transfer complete interrupt flag for channel x */

+#define MDMA_CIFCR_CBRTIF_Pos     (2U)

+#define MDMA_CIFCR_CBRTIF_Msk     (0x1UL << MDMA_CIFCR_CBRTIF_Pos)             /*!< 0x00000004 */

+#define MDMA_CIFCR_CBRTIF         MDMA_CIFCR_CBRTIF_Msk                        /*!< Channel x clear block repeat transfer complete interrupt flag */

+#define MDMA_CIFCR_CBTIF_Pos      (3U)

+#define MDMA_CIFCR_CBTIF_Msk      (0x1UL << MDMA_CIFCR_CBTIF_Pos)              /*!< 0x00000008 */

+#define MDMA_CIFCR_CBTIF          MDMA_CIFCR_CBTIF_Msk                         /*!< Channel x Clear block transfer complete interrupt flag */

+#define MDMA_CIFCR_CLTCIF_Pos     (4U)

+#define MDMA_CIFCR_CLTCIF_Msk     (0x1UL << MDMA_CIFCR_CLTCIF_Pos)             /*!< 0x00000010 */

+#define MDMA_CIFCR_CLTCIF         MDMA_CIFCR_CLTCIF_Msk                        /*!< CLear Transfer buffer Complete Interrupt Flag for channel */

+

+/********************  Bit definition for MDMA_CxESR register  ****************/

+#define MDMA_CESR_TEA_Pos         (0U)

+#define MDMA_CESR_TEA_Msk         (0x7FUL << MDMA_CESR_TEA_Pos)                /*!< 0x0000007F */

+#define MDMA_CESR_TEA             MDMA_CESR_TEA_Msk                            /*!< Transfer Error Address */

+#define MDMA_CESR_TED_Pos         (7U)

+#define MDMA_CESR_TED_Msk         (0x1UL << MDMA_CESR_TED_Pos)                 /*!< 0x00000080 */

+#define MDMA_CESR_TED             MDMA_CESR_TED_Msk                            /*!< Transfer Error Direction */

+#define MDMA_CESR_TELD_Pos        (8U)

+#define MDMA_CESR_TELD_Msk        (0x1UL << MDMA_CESR_TELD_Pos)                /*!< 0x00000100 */

+#define MDMA_CESR_TELD            MDMA_CESR_TELD_Msk                           /*!< Transfer Error Link Data */

+#define MDMA_CESR_TEMD_Pos        (9U)

+#define MDMA_CESR_TEMD_Msk        (0x1UL << MDMA_CESR_TEMD_Pos)                /*!< 0x00000200 */

+#define MDMA_CESR_TEMD            MDMA_CESR_TEMD_Msk                           /*!< Transfer Error Mask Data */

+#define MDMA_CESR_ASE_Pos         (10U)

+#define MDMA_CESR_ASE_Msk         (0x1UL << MDMA_CESR_ASE_Pos)                 /*!< 0x00000400 */

+#define MDMA_CESR_ASE             MDMA_CESR_ASE_Msk                            /*!< Address/Size Error       */

+#define MDMA_CESR_BSE_Pos         (11U)

+#define MDMA_CESR_BSE_Msk         (0x1UL << MDMA_CESR_BSE_Pos)                 /*!< 0x00000800 */

+#define MDMA_CESR_BSE             MDMA_CESR_BSE_Msk                            /*!< Block Size Error         */

+

+/********************  Bit definition for MDMA_CxCR register  ****************/

+#define MDMA_CCR_EN_Pos           (0U)

+#define MDMA_CCR_EN_Msk           (0x1UL << MDMA_CCR_EN_Pos)                   /*!< 0x00000001 */

+#define MDMA_CCR_EN               MDMA_CCR_EN_Msk                              /*!< Channel enable / flag channel ready when read low */

+#define MDMA_CCR_TEIE_Pos         (1U)

+#define MDMA_CCR_TEIE_Msk         (0x1UL << MDMA_CCR_TEIE_Pos)                 /*!< 0x00000002 */

+#define MDMA_CCR_TEIE             MDMA_CCR_TEIE_Msk                            /*!< Transfer error interrupt enable */

+#define MDMA_CCR_CTCIE_Pos        (2U)

+#define MDMA_CCR_CTCIE_Msk        (0x1UL << MDMA_CCR_CTCIE_Pos)                /*!< 0x00000004 */

+#define MDMA_CCR_CTCIE            MDMA_CCR_CTCIE_Msk                           /*!< Channel Transfer Complete interrupt enable */

+#define MDMA_CCR_BRTIE_Pos        (3U)

+#define MDMA_CCR_BRTIE_Msk        (0x1UL << MDMA_CCR_BRTIE_Pos)                /*!< 0x00000008 */

+#define MDMA_CCR_BRTIE            MDMA_CCR_BRTIE_Msk                           /*!< Block Repeat transfer interrupt enable */

+#define MDMA_CCR_BTIE_Pos         (4U)

+#define MDMA_CCR_BTIE_Msk         (0x1UL << MDMA_CCR_BTIE_Pos)                 /*!< 0x00000010 */

+#define MDMA_CCR_BTIE             MDMA_CCR_BTIE_Msk                            /*!< Block Transfer interrupt enable */

+#define MDMA_CCR_TCIE_Pos         (5U)

+#define MDMA_CCR_TCIE_Msk         (0x1UL << MDMA_CCR_TCIE_Pos)                 /*!< 0x00000020 */

+#define MDMA_CCR_TCIE             MDMA_CCR_TCIE_Msk                            /*!< buffer Transfer Complete interrupt enable */

+#define MDMA_CCR_PL_Pos           (6U)

+#define MDMA_CCR_PL_Msk           (0x3UL << MDMA_CCR_PL_Pos)                   /*!< 0x000000C0 */

+#define MDMA_CCR_PL               MDMA_CCR_PL_Msk                              /*!< Priority level */

+#define MDMA_CCR_PL_0             (0x1UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000040 */

+#define MDMA_CCR_PL_1             (0x2UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000080 */

+#define MDMA_CCR_BEX_Pos          (12U)

+#define MDMA_CCR_BEX_Msk          (0x1UL << MDMA_CCR_BEX_Pos)                  /*!< 0x00001000 */

+#define MDMA_CCR_BEX              MDMA_CCR_BEX_Msk                             /*!< Byte Endianess eXchange */

+#define MDMA_CCR_HEX_Pos          (13U)

+#define MDMA_CCR_HEX_Msk          (0x1UL << MDMA_CCR_HEX_Pos)                  /*!< 0x00002000 */

+#define MDMA_CCR_HEX              MDMA_CCR_HEX_Msk                             /*!< Half word Endianess eXchange */

+#define MDMA_CCR_WEX_Pos          (14U)

+#define MDMA_CCR_WEX_Msk          (0x1UL << MDMA_CCR_WEX_Pos)                  /*!< 0x00004000 */

+#define MDMA_CCR_WEX              MDMA_CCR_WEX_Msk                             /*!< Word Endianess eXchange */

+#define MDMA_CCR_SWRQ_Pos         (16U)

+#define MDMA_CCR_SWRQ_Msk         (0x1UL << MDMA_CCR_SWRQ_Pos)                 /*!< 0x00010000 */

+#define MDMA_CCR_SWRQ             MDMA_CCR_SWRQ_Msk                            /*!< SW ReQuest */

+

+/********************  Bit definition for MDMA_CxTCR register  ****************/

+#define MDMA_CTCR_SINC_Pos        (0U)

+#define MDMA_CTCR_SINC_Msk        (0x3UL << MDMA_CTCR_SINC_Pos)                /*!< 0x00000003 */

+#define MDMA_CTCR_SINC            MDMA_CTCR_SINC_Msk                           /*!< Source increment mode */

+#define MDMA_CTCR_SINC_0          (0x1UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000001 */

+#define MDMA_CTCR_SINC_1          (0x2UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000002 */

+#define MDMA_CTCR_DINC_Pos        (2U)

+#define MDMA_CTCR_DINC_Msk        (0x3UL << MDMA_CTCR_DINC_Pos)                /*!< 0x0000000C */

+#define MDMA_CTCR_DINC            MDMA_CTCR_DINC_Msk                           /*!< Source increment mode */

+#define MDMA_CTCR_DINC_0          (0x1UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000004 */

+#define MDMA_CTCR_DINC_1          (0x2UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000008 */

+#define MDMA_CTCR_SSIZE_Pos       (4U)

+#define MDMA_CTCR_SSIZE_Msk       (0x3UL << MDMA_CTCR_SSIZE_Pos)               /*!< 0x00000030 */

+#define MDMA_CTCR_SSIZE           MDMA_CTCR_SSIZE_Msk                          /*!< Source data size */

+#define MDMA_CTCR_SSIZE_0         (0x1UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000010 */

+#define MDMA_CTCR_SSIZE_1         (0x2UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000020 */

+#define MDMA_CTCR_DSIZE_Pos       (6U)

+#define MDMA_CTCR_DSIZE_Msk       (0x3UL << MDMA_CTCR_DSIZE_Pos)               /*!< 0x000000C0 */

+#define MDMA_CTCR_DSIZE           MDMA_CTCR_DSIZE_Msk                          /*!< Destination data size */

+#define MDMA_CTCR_DSIZE_0         (0x1UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000040 */

+#define MDMA_CTCR_DSIZE_1         (0x2UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000080 */

+#define MDMA_CTCR_SINCOS_Pos      (8U)

+#define MDMA_CTCR_SINCOS_Msk      (0x3UL << MDMA_CTCR_SINCOS_Pos)              /*!< 0x00000300 */

+#define MDMA_CTCR_SINCOS          MDMA_CTCR_SINCOS_Msk                         /*!< Source increment offset size */

+#define MDMA_CTCR_SINCOS_0        (0x1UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000100 */

+#define MDMA_CTCR_SINCOS_1        (0x2UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000200 */

+#define MDMA_CTCR_DINCOS_Pos      (10U)

+#define MDMA_CTCR_DINCOS_Msk      (0x3UL << MDMA_CTCR_DINCOS_Pos)              /*!< 0x00000C00 */

+#define MDMA_CTCR_DINCOS          MDMA_CTCR_DINCOS_Msk                         /*!< Destination increment offset size */

+#define MDMA_CTCR_DINCOS_0        (0x1UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000400 */

+#define MDMA_CTCR_DINCOS_1        (0x2UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000800 */

+#define MDMA_CTCR_SBURST_Pos      (12U)

+#define MDMA_CTCR_SBURST_Msk      (0x7UL << MDMA_CTCR_SBURST_Pos)              /*!< 0x00007000 */

+#define MDMA_CTCR_SBURST          MDMA_CTCR_SBURST_Msk                         /*!< Source burst transfer configuration */

+#define MDMA_CTCR_SBURST_0        (0x1UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00001000 */

+#define MDMA_CTCR_SBURST_1        (0x2UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00002000 */

+#define MDMA_CTCR_SBURST_2        (0x4UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00004000 */

+#define MDMA_CTCR_DBURST_Pos      (15U)

+#define MDMA_CTCR_DBURST_Msk      (0x7UL << MDMA_CTCR_DBURST_Pos)              /*!< 0x00038000 */

+#define MDMA_CTCR_DBURST          MDMA_CTCR_DBURST_Msk                         /*!< Destination burst transfer configuration */

+#define MDMA_CTCR_DBURST_0        (0x1UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00008000 */

+#define MDMA_CTCR_DBURST_1        (0x2UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00010000 */

+#define MDMA_CTCR_DBURST_2        (0x4UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00020000 */

+#define MDMA_CTCR_TLEN_Pos        (18U)

+#define MDMA_CTCR_TLEN_Msk        (0x7FUL << MDMA_CTCR_TLEN_Pos)               /*!< 0x01FC0000 */

+#define MDMA_CTCR_TLEN            MDMA_CTCR_TLEN_Msk                           /*!< buffer Transfer Length (number of bytes - 1) */

+#define MDMA_CTCR_PKE_Pos         (25U)

+#define MDMA_CTCR_PKE_Msk         (0x1UL << MDMA_CTCR_PKE_Pos)                 /*!< 0x02000000 */

+#define MDMA_CTCR_PKE             MDMA_CTCR_PKE_Msk                            /*!< PacK Enable */

+#define MDMA_CTCR_PAM_Pos         (26U)

+#define MDMA_CTCR_PAM_Msk         (0x3UL << MDMA_CTCR_PAM_Pos)                 /*!< 0x0C000000 */

+#define MDMA_CTCR_PAM             MDMA_CTCR_PAM_Msk                            /*!< Padding/Alignement Mode */

+#define MDMA_CTCR_PAM_0           (0x1UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x4000000 */

+#define MDMA_CTCR_PAM_1           (0x2UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x8000000 */

+#define MDMA_CTCR_TRGM_Pos        (28U)

+#define MDMA_CTCR_TRGM_Msk        (0x3UL << MDMA_CTCR_TRGM_Pos)                /*!< 0x30000000 */

+#define MDMA_CTCR_TRGM            MDMA_CTCR_TRGM_Msk                           /*!< Trigger Mode */

+#define MDMA_CTCR_TRGM_0          (0x1UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x10000000 */

+#define MDMA_CTCR_TRGM_1          (0x2UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x20000000 */

+#define MDMA_CTCR_SWRM_Pos        (30U)

+#define MDMA_CTCR_SWRM_Msk        (0x1UL << MDMA_CTCR_SWRM_Pos)                /*!< 0x40000000 */

+#define MDMA_CTCR_SWRM            MDMA_CTCR_SWRM_Msk                           /*!< SW Request Mode */

+#define MDMA_CTCR_BWM_Pos         (31U)

+#define MDMA_CTCR_BWM_Msk         (0x1UL << MDMA_CTCR_BWM_Pos)                 /*!< 0x80000000 */

+#define MDMA_CTCR_BWM             MDMA_CTCR_BWM_Msk                            /*!< Bufferable Write Mode */

+

+/********************  Bit definition for MDMA_CxBNDTR register  ****************/

+#define MDMA_CBNDTR_BNDT_Pos      (0U)

+#define MDMA_CBNDTR_BNDT_Msk      (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos)          /*!< 0x0001FFFF */

+#define MDMA_CBNDTR_BNDT          MDMA_CBNDTR_BNDT_Msk                         /*!< Block Number of data bytes to transfer */

+#define MDMA_CBNDTR_BRSUM_Pos     (18U)

+#define MDMA_CBNDTR_BRSUM_Msk     (0x1UL << MDMA_CBNDTR_BRSUM_Pos)             /*!< 0x00040000 */

+#define MDMA_CBNDTR_BRSUM         MDMA_CBNDTR_BRSUM_Msk                        /*!< Block Repeat Source address Update Mode */

+#define MDMA_CBNDTR_BRDUM_Pos     (19U)

+#define MDMA_CBNDTR_BRDUM_Msk     (0x1UL << MDMA_CBNDTR_BRDUM_Pos)             /*!< 0x00080000 */

+#define MDMA_CBNDTR_BRDUM         MDMA_CBNDTR_BRDUM_Msk                        /*!< Block Repeat Destination address Update Mode */

+#define MDMA_CBNDTR_BRC_Pos       (20U)

+#define MDMA_CBNDTR_BRC_Msk       (0xFFFUL << MDMA_CBNDTR_BRC_Pos)             /*!< 0xFFF00000 */

+#define MDMA_CBNDTR_BRC           MDMA_CBNDTR_BRC_Msk                          /*!< Block Repeat Count */

+

+/********************  Bit definition for MDMA_CxSAR register  ****************/

+#define MDMA_CSAR_SAR_Pos         (0U)

+#define MDMA_CSAR_SAR_Msk         (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CSAR_SAR             MDMA_CSAR_SAR_Msk                            /*!< Source address */

+

+/********************  Bit definition for MDMA_CxDAR register  ****************/

+#define MDMA_CDAR_DAR_Pos         (0U)

+#define MDMA_CDAR_DAR_Msk         (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CDAR_DAR             MDMA_CDAR_DAR_Msk                            /*!< Destination address */

+

+/********************  Bit definition for MDMA_CxBRUR  ************************/

+#define MDMA_CBRUR_SUV_Pos        (0U)

+#define MDMA_CBRUR_SUV_Msk        (0xFFFFUL << MDMA_CBRUR_SUV_Pos)             /*!< 0x0000FFFF */

+#define MDMA_CBRUR_SUV            MDMA_CBRUR_SUV_Msk                           /*!< Source address Update Value */

+#define MDMA_CBRUR_DUV_Pos        (16U)

+#define MDMA_CBRUR_DUV_Msk        (0xFFFFUL << MDMA_CBRUR_DUV_Pos)             /*!< 0xFFFF0000 */

+#define MDMA_CBRUR_DUV            MDMA_CBRUR_DUV_Msk                           /*!< Destination address Update Value */

+

+/********************  Bit definition for MDMA_CxLAR  *************************/

+#define MDMA_CLAR_LAR_Pos         (0U)

+#define MDMA_CLAR_LAR_Msk         (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CLAR_LAR             MDMA_CLAR_LAR_Msk                            /*!< Link Address Register */

+

+/********************  Bit definition for MDMA_CxTBR)  ************************/

+#define MDMA_CTBR_TSEL_Pos        (0U)

+#define MDMA_CTBR_TSEL_Msk        (0xFFUL << MDMA_CTBR_TSEL_Pos)               /*!< 0x000000FF */

+#define MDMA_CTBR_TSEL            MDMA_CTBR_TSEL_Msk                           /*!< Trigger SELection */

+#define MDMA_CTBR_SBUS_Pos        (16U)

+#define MDMA_CTBR_SBUS_Msk        (0x1UL << MDMA_CTBR_SBUS_Pos)                /*!< 0x00010000 */

+#define MDMA_CTBR_SBUS            MDMA_CTBR_SBUS_Msk                           /*!< Source BUS select */

+#define MDMA_CTBR_DBUS_Pos        (17U)

+#define MDMA_CTBR_DBUS_Msk        (0x1UL << MDMA_CTBR_DBUS_Pos)                /*!< 0x00020000 */

+#define MDMA_CTBR_DBUS            MDMA_CTBR_DBUS_Msk                           /*!< Destination BUS select */

+

+/********************  Bit definition for MDMA_CxMAR)  ************************/

+#define MDMA_CMAR_MAR_Pos         (0U)

+#define MDMA_CMAR_MAR_Msk         (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CMAR_MAR             MDMA_CMAR_MAR_Msk                            /*!< Mask address */

+

+/********************  Bit definition for MDMA_CxMDR)  ************************/

+#define MDMA_CMDR_MDR_Pos         (0U)

+#define MDMA_CMDR_MDR_Msk         (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CMDR_MDR             MDMA_CMDR_MDR_Msk                            /*!< Mask Data */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Operational Amplifier (OPAMP)                      */

+/*                                                                            */

+/******************************************************************************/

+/*********************  Bit definition for OPAMPx_CSR register  ***************/

+#define OPAMP_CSR_OPAMPxEN_Pos           (0U)

+#define OPAMP_CSR_OPAMPxEN_Msk           (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)     /*!< 0x00000001 */

+#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */

+#define OPAMP_CSR_FORCEVP_Pos            (1U)

+#define OPAMP_CSR_FORCEVP_Msk            (0x1UL << OPAMP_CSR_FORCEVP_Pos)      /*!< 0x00000002 */

+#define OPAMP_CSR_FORCEVP                OPAMP_CSR_FORCEVP_Msk                 /*!< Force internal reference on VP */

+

+#define OPAMP_CSR_VPSEL_Pos              (2U)

+#define OPAMP_CSR_VPSEL_Msk              (0x3UL << OPAMP_CSR_VPSEL_Pos)        /*!< 0x0000000C */

+#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */

+#define OPAMP_CSR_VPSEL_0                (0x1UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000004 */

+#define OPAMP_CSR_VPSEL_1                (0x2UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000008 */

+

+#define OPAMP_CSR_VMSEL_Pos              (5U)

+#define OPAMP_CSR_VMSEL_Msk              (0x3UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000060 */

+#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */

+#define OPAMP_CSR_VMSEL_0                (0x1UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000020 */

+#define OPAMP_CSR_VMSEL_1                (0x2UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000040 */

+

+#define OPAMP_CSR_OPAHSM_Pos             (8U)

+#define OPAMP_CSR_OPAHSM_Msk             (0x1UL << OPAMP_CSR_OPAHSM_Pos)       /*!< 0x00000100 */

+#define OPAMP_CSR_OPAHSM                 OPAMP_CSR_OPAHSM_Msk                  /*!< Operational amplifier high speed mode */

+#define OPAMP_CSR_CALON_Pos              (11U)

+#define OPAMP_CSR_CALON_Msk              (0x1UL << OPAMP_CSR_CALON_Pos)        /*!< 0x00000800 */

+#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */

+

+#define OPAMP_CSR_CALSEL_Pos             (12U)

+#define OPAMP_CSR_CALSEL_Msk             (0x3UL << OPAMP_CSR_CALSEL_Pos)       /*!< 0x00003000 */

+#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */

+#define OPAMP_CSR_CALSEL_0               (0x1UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00001000 */

+#define OPAMP_CSR_CALSEL_1               (0x2UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */

+

+#define OPAMP_CSR_PGGAIN_Pos             (14U)

+#define OPAMP_CSR_PGGAIN_Msk             (0xFUL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x0003C000 */

+#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */

+#define OPAMP_CSR_PGGAIN_0               (0x1UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00004000 */

+#define OPAMP_CSR_PGGAIN_1               (0x2UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00008000 */

+#define OPAMP_CSR_PGGAIN_2               (0x4UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00010000 */

+#define OPAMP_CSR_PGGAIN_3               (0x8UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00020000 */

+

+#define OPAMP_CSR_USERTRIM_Pos           (18U)

+#define OPAMP_CSR_USERTRIM_Msk           (0x1UL << OPAMP_CSR_USERTRIM_Pos)     /*!< 0x00040000 */

+#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */

+#define OPAMP_CSR_TSTREF_Pos             (29U)

+#define OPAMP_CSR_TSTREF_Msk             (0x1UL << OPAMP_CSR_TSTREF_Pos)       /*!< 0x20000000 */

+#define OPAMP_CSR_TSTREF                 OPAMP_CSR_TSTREF_Msk                  /*!< OpAmp calibration reference voltage output control */

+#define OPAMP_CSR_CALOUT_Pos             (30U)

+#define OPAMP_CSR_CALOUT_Msk             (0x1UL << OPAMP_CSR_CALOUT_Pos)       /*!< 0x40000000 */

+#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier calibration output */

+

+/*********************  Bit definition for OPAMP1_CSR register  ***************/

+#define OPAMP1_CSR_OPAEN_Pos              (0U)

+#define OPAMP1_CSR_OPAEN_Msk              (0x1UL << OPAMP1_CSR_OPAEN_Pos)      /*!< 0x00000001 */

+#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */

+#define OPAMP1_CSR_FORCEVP_Pos            (1U)

+#define OPAMP1_CSR_FORCEVP_Msk            (0x1UL << OPAMP1_CSR_FORCEVP_Pos)    /*!< 0x00000002 */

+#define OPAMP1_CSR_FORCEVP                OPAMP1_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */

+

+#define OPAMP1_CSR_VPSEL_Pos              (2U)

+#define OPAMP1_CSR_VPSEL_Msk              (0x3UL << OPAMP1_CSR_VPSEL_Pos)      /*!< 0x0000000C */

+#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */

+#define OPAMP1_CSR_VPSEL_0                (0x1UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000004 */

+#define OPAMP1_CSR_VPSEL_1                (0x2UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000008 */

+

+#define OPAMP1_CSR_VMSEL_Pos              (5U)

+#define OPAMP1_CSR_VMSEL_Msk              (0x3UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000060 */

+#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */

+#define OPAMP1_CSR_VMSEL_0                (0x1UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000020 */

+#define OPAMP1_CSR_VMSEL_1                (0x2UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000040 */

+

+#define OPAMP1_CSR_OPAHSM_Pos             (8U)

+#define OPAMP1_CSR_OPAHSM_Msk             (0x1UL << OPAMP1_CSR_OPAHSM_Pos)     /*!< 0x00000100 */

+#define OPAMP1_CSR_OPAHSM                 OPAMP1_CSR_OPAHSM_Msk                /*!< Operational amplifier1 high speed mode */

+#define OPAMP1_CSR_CALON_Pos              (11U)

+#define OPAMP1_CSR_CALON_Msk              (0x1UL << OPAMP1_CSR_CALON_Pos)      /*!< 0x00000800 */

+#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */

+

+#define OPAMP1_CSR_CALSEL_Pos             (12U)

+#define OPAMP1_CSR_CALSEL_Msk             (0x3UL << OPAMP1_CSR_CALSEL_Pos)     /*!< 0x00003000 */

+#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */

+#define OPAMP1_CSR_CALSEL_0               (0x1UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00001000 */

+#define OPAMP1_CSR_CALSEL_1               (0x2UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */

+

+#define OPAMP1_CSR_PGGAIN_Pos             (14U)

+#define OPAMP1_CSR_PGGAIN_Msk             (0xFUL << OPAMP1_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */

+#define OPAMP1_CSR_PGGAIN                 OPAMP1_CSR_PGGAIN_Msk                /*!< Operational amplifier1 Programmable amplifier gain value */

+#define OPAMP1_CSR_PGGAIN_0               (0x1UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00004000 */

+#define OPAMP1_CSR_PGGAIN_1               (0x2UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00008000 */

+#define OPAMP1_CSR_PGGAIN_2               (0x4UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00010000 */

+#define OPAMP1_CSR_PGGAIN_3               (0x8UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00020000 */

+

+#define OPAMP1_CSR_USERTRIM_Pos           (18U)

+#define OPAMP1_CSR_USERTRIM_Msk           (0x1UL << OPAMP1_CSR_USERTRIM_Pos)   /*!< 0x00040000 */

+#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */

+#define OPAMP1_CSR_TSTREF_Pos             (29U)

+#define OPAMP1_CSR_TSTREF_Msk             (0x1UL << OPAMP1_CSR_TSTREF_Pos)     /*!< 0x20000000 */

+#define OPAMP1_CSR_TSTREF                 OPAMP1_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */

+#define OPAMP1_CSR_CALOUT_Pos             (30U)

+#define OPAMP1_CSR_CALOUT_Msk             (0x1UL << OPAMP1_CSR_CALOUT_Pos)     /*!< 0x40000000 */

+#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */

+

+/*********************  Bit definition for OPAMP2_CSR register  ***************/

+#define OPAMP2_CSR_OPAEN_Pos              (0U)

+#define OPAMP2_CSR_OPAEN_Msk              (0x1UL << OPAMP2_CSR_OPAEN_Pos)      /*!< 0x00000001 */

+#define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */

+#define OPAMP2_CSR_FORCEVP_Pos            (1U)

+#define OPAMP2_CSR_FORCEVP_Msk            (0x1UL << OPAMP2_CSR_FORCEVP_Pos)    /*!< 0x00000002 */

+#define OPAMP2_CSR_FORCEVP                OPAMP2_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */

+

+#define OPAMP2_CSR_VPSEL_Pos              (2U)

+#define OPAMP2_CSR_VPSEL_Msk              (0x3UL << OPAMP2_CSR_VPSEL_Pos)      /*!< 0x0000000C */

+#define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */

+#define OPAMP2_CSR_VPSEL_0                (0x1UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000004 */

+#define OPAMP2_CSR_VPSEL_1                (0x2UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000008 */

+

+#define OPAMP2_CSR_VMSEL_Pos              (5U)

+#define OPAMP2_CSR_VMSEL_Msk              (0x3UL << OPAMP2_CSR_VMSEL_Pos)      /*!< 0x00000060 */

+#define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */

+#define OPAMP2_CSR_VMSEL_0                (0x1UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000020 */

+#define OPAMP2_CSR_VMSEL_1                (0x2UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000040 */

+

+#define OPAMP2_CSR_OPAHSM_Pos             (8U)

+#define OPAMP2_CSR_OPAHSM_Msk             (0x1UL << OPAMP2_CSR_OPAHSM_Pos)     /*!< 0x00000100 */

+#define OPAMP2_CSR_OPAHSM                 OPAMP2_CSR_OPAHSM_Msk                /*!< Operational amplifier2 high speed mode */

+#define OPAMP2_CSR_CALON_Pos              (11U)

+#define OPAMP2_CSR_CALON_Msk              (0x1UL << OPAMP2_CSR_CALON_Pos)      /*!< 0x00000800 */

+#define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */

+

+#define OPAMP2_CSR_CALSEL_Pos             (12U)

+#define OPAMP2_CSR_CALSEL_Msk             (0x3UL << OPAMP2_CSR_CALSEL_Pos)     /*!< 0x00003000 */

+#define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */

+#define OPAMP2_CSR_CALSEL_0               (0x1UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00001000 */

+#define OPAMP2_CSR_CALSEL_1               (0x2UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */

+

+#define OPAMP2_CSR_PGGAIN_Pos             (14U)

+#define OPAMP2_CSR_PGGAIN_Msk             (0xFUL << OPAMP2_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */

+#define OPAMP2_CSR_PGGAIN                 OPAMP2_CSR_PGGAIN_Msk                /*!< Operational amplifier2 Programmable amplifier gain value */

+#define OPAMP2_CSR_PGGAIN_0               (0x1UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00004000 */

+#define OPAMP2_CSR_PGGAIN_1               (0x2UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00008000 */

+#define OPAMP2_CSR_PGGAIN_2               (0x4UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00010000 */

+#define OPAMP2_CSR_PGGAIN_3               (0x8UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00020000 */

+

+#define OPAMP2_CSR_USERTRIM_Pos           (18U)

+#define OPAMP2_CSR_USERTRIM_Msk           (0x1UL << OPAMP2_CSR_USERTRIM_Pos)   /*!< 0x00040000 */

+#define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */

+#define OPAMP2_CSR_TSTREF_Pos             (29U)

+#define OPAMP2_CSR_TSTREF_Msk             (0x1UL << OPAMP2_CSR_TSTREF_Pos)     /*!< 0x20000000 */

+#define OPAMP2_CSR_TSTREF                 OPAMP2_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */

+#define OPAMP2_CSR_CALOUT_Pos             (30U)

+#define OPAMP2_CSR_CALOUT_Msk             (0x1UL << OPAMP2_CSR_CALOUT_Pos)     /*!< 0x40000000 */

+#define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */

+

+/*******************  Bit definition for OPAMP_OTR register  ******************/

+#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */

+#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP1_OTR register  ******************/

+#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */

+#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP2_OTR register  ******************/

+#define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */

+#define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP_HSOTR register  ****************/

+#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP_HSOTR_TRIMHSOFFSETN        OPAMP_HSOTR_TRIMHSOFFSETN_Msk         /*!< Trim for NMOS differential pairs */

+#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP_HSOTR_TRIMHSOFFSETP        OPAMP_HSOTR_TRIMHSOFFSETP_Msk         /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP1_HSOTR register  ****************/

+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP1_HSOTR_TRIMHSOFFSETN        OPAMP1_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */

+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP1_HSOTR_TRIMHSOFFSETP        OPAMP1_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP2_HSOTR register  ****************/

+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP2_HSOTR_TRIMHSOFFSETN        OPAMP2_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */

+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP2_HSOTR_TRIMHSOFFSETP        OPAMP2_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             Power Control                                  */

+/*                                                                            */

+/******************************************************************************/

+/*************************  NUMBER OF POWER DOMAINS  **************************/

+#define POWER_DOMAINS_NUMBER           3U                                      /*!< 3 Domains */

+

+/********************  Bit definition for PWR_CR1 register  *******************/

+#define PWR_CR1_ALS_Pos                (17U)

+#define PWR_CR1_ALS_Msk                (0x3UL << PWR_CR1_ALS_Pos)              /*!< 0x00060000 */

+#define PWR_CR1_ALS                    PWR_CR1_ALS_Msk                         /*!< Analog Voltage Detector level selection */

+#define PWR_CR1_ALS_0                  (0x1UL << PWR_CR1_ALS_Pos)              /*!< 0x00020000 */

+#define PWR_CR1_ALS_1                  (0x2UL << PWR_CR1_ALS_Pos)              /*!< 0x00040000 */

+#define PWR_CR1_AVDEN_Pos              (16U)

+#define PWR_CR1_AVDEN_Msk              (0x1UL << PWR_CR1_AVDEN_Pos)            /*!< 0x00010000 */

+#define PWR_CR1_AVDEN                  PWR_CR1_AVDEN_Msk                       /*!< Analog Voltage Detector Enable */

+#define PWR_CR1_SVOS_Pos               (14U)

+#define PWR_CR1_SVOS_Msk               (0x3UL << PWR_CR1_SVOS_Pos)             /*!< 0x0000C000 */

+#define PWR_CR1_SVOS                   PWR_CR1_SVOS_Msk                        /*!< System STOP mode Voltage Scaling selection */

+#define PWR_CR1_SVOS_0                 (0x1UL << PWR_CR1_SVOS_Pos)             /*!< 0x00004000 */

+#define PWR_CR1_SVOS_1                 (0x2UL << PWR_CR1_SVOS_Pos)             /*!< 0x00008000 */

+#define PWR_CR1_FLPS_Pos               (9U)

+#define PWR_CR1_FLPS_Msk               (0x1UL << PWR_CR1_FLPS_Pos)             /*!< 0x00000200 */

+#define PWR_CR1_FLPS                   PWR_CR1_FLPS_Msk                        /*!< Flash low power mode in DSTOP */

+#define PWR_CR1_DBP_Pos                (8U)

+#define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */

+#define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable Back-up domain Protection */

+#define PWR_CR1_PLS_Pos                (5U)

+#define PWR_CR1_PLS_Msk                (0x7UL << PWR_CR1_PLS_Pos)              /*!< 0x000000E0 */

+#define PWR_CR1_PLS                    PWR_CR1_PLS_Msk                         /*!< Programmable Voltage Detector level selection */

+#define PWR_CR1_PLS_0                  (0x1UL << PWR_CR1_PLS_Pos)              /*!< 0x00000020 */

+#define PWR_CR1_PLS_1                  (0x2UL << PWR_CR1_PLS_Pos)              /*!< 0x00000040 */

+#define PWR_CR1_PLS_2                  (0x4UL << PWR_CR1_PLS_Pos)              /*!< 0x00000080 */

+#define PWR_CR1_PVDEN_Pos              (4U)

+#define PWR_CR1_PVDEN_Msk              (0x1UL << PWR_CR1_PVDEN_Pos)            /*!< 0x00000010 */

+#define PWR_CR1_PVDEN                  PWR_CR1_PVDEN_Msk                       /*!< Programmable Voltage detector enable */

+#define PWR_CR1_LPDS_Pos               (0U)

+#define PWR_CR1_LPDS_Msk               (0x1UL << PWR_CR1_LPDS_Pos)             /*!< 0x00000001 */

+#define PWR_CR1_LPDS                   PWR_CR1_LPDS_Msk                        /*!< Low Power Deepsleep with SVOS3 */

+

+/*!< PVD level configuration */

+#define PWR_CR1_PLS_LEV0               (0UL)                                   /*!< PVD level 0 */

+#define PWR_CR1_PLS_LEV1_Pos           (5U)

+#define PWR_CR1_PLS_LEV1_Msk           (0x1UL << PWR_CR1_PLS_LEV1_Pos)         /*!< 0x00000020 */

+#define PWR_CR1_PLS_LEV1               PWR_CR1_PLS_LEV1_Msk                    /*!< PVD level 1 */

+#define PWR_CR1_PLS_LEV2_Pos           (6U)

+#define PWR_CR1_PLS_LEV2_Msk           (0x1UL << PWR_CR1_PLS_LEV2_Pos)         /*!< 0x00000040 */

+#define PWR_CR1_PLS_LEV2               PWR_CR1_PLS_LEV2_Msk                    /*!< PVD level 2 */

+#define PWR_CR1_PLS_LEV3_Pos           (5U)

+#define PWR_CR1_PLS_LEV3_Msk           (0x3UL << PWR_CR1_PLS_LEV3_Pos)         /*!< 0x00000060 */

+#define PWR_CR1_PLS_LEV3               PWR_CR1_PLS_LEV3_Msk                    /*!< PVD level 3 */

+#define PWR_CR1_PLS_LEV4_Pos           (7U)

+#define PWR_CR1_PLS_LEV4_Msk           (0x1UL << PWR_CR1_PLS_LEV4_Pos)         /*!< 0x00000080 */

+#define PWR_CR1_PLS_LEV4               PWR_CR1_PLS_LEV4_Msk                    /*!< PVD level 4 */

+#define PWR_CR1_PLS_LEV5_Pos           (5U)

+#define PWR_CR1_PLS_LEV5_Msk           (0x5UL << PWR_CR1_PLS_LEV5_Pos)         /*!< 0x000000A0 */

+#define PWR_CR1_PLS_LEV5               PWR_CR1_PLS_LEV5_Msk                    /*!< PVD level 5 */

+#define PWR_CR1_PLS_LEV6_Pos           (6U)

+#define PWR_CR1_PLS_LEV6_Msk           (0x3UL << PWR_CR1_PLS_LEV6_Pos)         /*!< 0x000000C0 */

+#define PWR_CR1_PLS_LEV6               PWR_CR1_PLS_LEV6_Msk                    /*!< PVD level 6 */

+#define PWR_CR1_PLS_LEV7_Pos           (5U)

+#define PWR_CR1_PLS_LEV7_Msk           (0x7UL << PWR_CR1_PLS_LEV7_Pos)         /*!< 0x000000E0 */

+#define PWR_CR1_PLS_LEV7               PWR_CR1_PLS_LEV7_Msk                    /*!< PVD level 7 */

+

+/*!< AVD level configuration */

+#define PWR_CR1_ALS_LEV0               (0UL)                                   /*!< AVD level 0 */

+#define PWR_CR1_ALS_LEV1_Pos           (17U)

+#define PWR_CR1_ALS_LEV1_Msk           (0x1UL << PWR_CR1_ALS_LEV1_Pos)         /*!< 0x00020000 */

+#define PWR_CR1_ALS_LEV1               PWR_CR1_ALS_LEV1_Msk                    /*!< AVD level 1 */

+#define PWR_CR1_ALS_LEV2_Pos           (18U)

+#define PWR_CR1_ALS_LEV2_Msk           (0x1UL << PWR_CR1_ALS_LEV2_Pos)         /*!< 0x00040000 */

+#define PWR_CR1_ALS_LEV2               PWR_CR1_ALS_LEV2_Msk                    /*!< AVD level 2 */

+#define PWR_CR1_ALS_LEV3_Pos           (17U)

+#define PWR_CR1_ALS_LEV3_Msk           (0x3UL << PWR_CR1_ALS_LEV3_Pos)         /*!< 0x00060000 */

+#define PWR_CR1_ALS_LEV3               PWR_CR1_ALS_LEV3_Msk                    /*!< AVD level 3 */

+

+/********************  Bit definition for PWR_CSR1 register  ******************/

+#define PWR_CSR1_AVDO_Pos              (16U)

+#define PWR_CSR1_AVDO_Msk              (0x1UL << PWR_CSR1_AVDO_Pos)            /*!< 0x00010000 */

+#define PWR_CSR1_AVDO                  PWR_CSR1_AVDO_Msk                       /*!< Analog Voltage Detect Output */

+#define PWR_CSR1_ACTVOS_Pos            (14U)

+#define PWR_CSR1_ACTVOS_Msk            (0x3UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x0000C000 */

+#define PWR_CSR1_ACTVOS                PWR_CSR1_ACTVOS_Msk                     /*!< Current actual used VOS for VDD11 Voltage Scaling */

+#define PWR_CSR1_ACTVOS_0              (0x1UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00004000 */

+#define PWR_CSR1_ACTVOS_1              (0x2UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00008000 */

+#define PWR_CSR1_ACTVOSRDY_Pos         (13U)

+#define PWR_CSR1_ACTVOSRDY_Msk         (0x1UL << PWR_CSR1_ACTVOSRDY_Pos)       /*!< 0x00002000 */

+#define PWR_CSR1_ACTVOSRDY             PWR_CSR1_ACTVOSRDY_Msk                  /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling  */

+#define PWR_CSR1_PVDO_Pos              (4U)

+#define PWR_CSR1_PVDO_Msk              (0x1UL << PWR_CSR1_PVDO_Pos)            /*!< 0x00000010 */

+#define PWR_CSR1_PVDO                  PWR_CSR1_PVDO_Msk                       /*!< Programmable Voltage Detect Output */

+

+/********************  Bit definition for PWR_CR2 register  *******************/

+#define PWR_CR2_TEMPH_Pos              (23U)

+#define PWR_CR2_TEMPH_Msk              (0x1UL << PWR_CR2_TEMPH_Pos)            /*!< 0x00800000 */

+#define PWR_CR2_TEMPH                  PWR_CR2_TEMPH_Msk                       /*!< Monitored temperature level above high threshold */

+#define PWR_CR2_TEMPL_Pos              (22U)

+#define PWR_CR2_TEMPL_Msk              (0x1UL << PWR_CR2_TEMPL_Pos)            /*!< 0x00400000 */

+#define PWR_CR2_TEMPL                  PWR_CR2_TEMPL_Msk                       /*!< Monitored temperature level above low threshold */

+#define PWR_CR2_VBATH_Pos              (21U)

+#define PWR_CR2_VBATH_Msk              (0x1UL << PWR_CR2_VBATH_Pos)            /*!< 0x00200000 */

+#define PWR_CR2_VBATH                  PWR_CR2_VBATH_Msk                       /*!< Monitored VBAT level above high threshold */

+#define PWR_CR2_VBATL_Pos              (20U)

+#define PWR_CR2_VBATL_Msk              (0x1UL << PWR_CR2_VBATL_Pos)            /*!< 0x00100000 */

+#define PWR_CR2_VBATL                  PWR_CR2_VBATL_Msk                       /*!< Monitored VBAT level above low threshold */

+#define PWR_CR2_BRRDY_Pos              (16U)

+#define PWR_CR2_BRRDY_Msk              (0x1UL << PWR_CR2_BRRDY_Pos)            /*!< 0x00010000 */

+#define PWR_CR2_BRRDY                  PWR_CR2_BRRDY_Msk                       /*!< Backup regulator ready */

+#define PWR_CR2_MONEN_Pos              (4U)

+#define PWR_CR2_MONEN_Msk              (0x1UL << PWR_CR2_MONEN_Pos)            /*!< 0x00000010 */

+#define PWR_CR2_MONEN                  PWR_CR2_MONEN_Msk                       /*!< VBAT and temperature monitoring enable */

+#define PWR_CR2_BREN_Pos               (0U)

+#define PWR_CR2_BREN_Msk               (0x1UL << PWR_CR2_BREN_Pos)             /*!< 0x00000001 */

+#define PWR_CR2_BREN                   PWR_CR2_BREN_Msk                        /*!< Backup regulator enable */

+

+/********************  Bit definition for PWR_CR3 register  *******************/

+#define PWR_CR3_USB33RDY_Pos           (26U)

+#define PWR_CR3_USB33RDY_Msk           (0x1UL << PWR_CR3_USB33RDY_Pos)         /*!< 0x04000000 */

+#define PWR_CR3_USB33RDY               PWR_CR3_USB33RDY_Msk                    /*!< USB supply ready */

+#define PWR_CR3_USBREGEN_Pos           (25U)

+#define PWR_CR3_USBREGEN_Msk           (0x1UL << PWR_CR3_USBREGEN_Pos)         /*!< 0x02000000 */

+#define PWR_CR3_USBREGEN               PWR_CR3_USBREGEN_Msk                    /*!< USB regulator enable */

+#define PWR_CR3_USB33DEN_Pos           (24U)

+#define PWR_CR3_USB33DEN_Msk           (0x1UL << PWR_CR3_USB33DEN_Pos)         /*!< 0x01000000 */

+#define PWR_CR3_USB33DEN               PWR_CR3_USB33DEN_Msk                    /*!< VDD33_USB voltage level detector enable */

+#define PWR_CR3_SMPSEXTRDY_Pos         (16U)

+#define PWR_CR3_SMPSEXTRDY_Msk         (0x1UL << PWR_CR3_SMPSEXTRDY_Pos)       /*!< 0x00010000 */

+#define PWR_CR3_SMPSEXTRDY             PWR_CR3_SMPSEXTRDY_Msk                  /*!< SMPS External supply ready */

+#define PWR_CR3_VBRS_Pos               (9U)

+#define PWR_CR3_VBRS_Msk               (0x1UL << PWR_CR3_VBRS_Pos)             /*!< 0x00000200 */

+#define PWR_CR3_VBRS                   PWR_CR3_VBRS_Msk                        /*!< VBAT charging resistor selection */

+#define PWR_CR3_VBE_Pos                (8U)

+#define PWR_CR3_VBE_Msk                (0x1UL << PWR_CR3_VBE_Pos)              /*!< 0x00000100 */

+#define PWR_CR3_VBE                    PWR_CR3_VBE_Msk                         /*!< VBAT charging enable */

+#define PWR_CR3_SMPSLEVEL_Pos          (4U)

+#define PWR_CR3_SMPSLEVEL_Msk          (0x3UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000030 */

+#define PWR_CR3_SMPSLEVEL              PWR_CR3_SMPSLEVEL_Msk                   /*!< SMPS output Voltage */

+#define PWR_CR3_SMPSLEVEL_0            (0x1UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000010 */

+#define PWR_CR3_SMPSLEVEL_1            (0x2UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000020 */

+#define PWR_CR3_SMPSEXTHP_Pos          (3U)

+#define PWR_CR3_SMPSEXTHP_Msk          (0x1UL << PWR_CR3_SMPSEXTHP_Pos)        /*!< 0x00000008 */

+#define PWR_CR3_SMPSEXTHP              PWR_CR3_SMPSEXTHP_Msk                   /*!< SMPS forced ON and in High Power MR mode */

+#define PWR_CR3_SMPSEN_Pos             (2U)

+#define PWR_CR3_SMPSEN_Msk             (0x1UL << PWR_CR3_SMPSEN_Pos)           /*!< 0x00000004 */

+#define PWR_CR3_SMPSEN                 PWR_CR3_SMPSEN_Msk                      /*!< SMPS Enable */

+#define PWR_CR3_LDOEN_Pos              (1U)

+#define PWR_CR3_LDOEN_Msk              (0x1UL << PWR_CR3_LDOEN_Pos)            /*!< 0x00000002 */

+#define PWR_CR3_LDOEN                  PWR_CR3_LDOEN_Msk                       /*!< Low Drop Output regulator enable */

+#define PWR_CR3_BYPASS_Pos             (0U)

+#define PWR_CR3_BYPASS_Msk             (0x1UL << PWR_CR3_BYPASS_Pos)           /*!< 0x00000001 */

+#define PWR_CR3_BYPASS                 PWR_CR3_BYPASS_Msk                      /*!< Power Management Unit bypass */

+

+/********************  Bit definition for PWR_CPUCR register  *****************/

+#define PWR_CPUCR_RUN_D3_Pos           (11U)

+#define PWR_CPUCR_RUN_D3_Msk           (0x1UL << PWR_CPUCR_RUN_D3_Pos)         /*!< 0x00000800 */

+#define PWR_CPUCR_RUN_D3               PWR_CPUCR_RUN_D3_Msk                    /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */

+#define PWR_CPUCR_HOLD2_Pos            (10U)

+#define PWR_CPUCR_HOLD2_Msk            (0x1UL << PWR_CPUCR_HOLD2_Pos)          /*!< 0x00000400 */

+#define PWR_CPUCR_HOLD2                PWR_CPUCR_HOLD2_Msk                     /*!< Hold the CPU2 and allocated peripherals when exiting STOP mode */

+#define PWR_CPUCR_CSSF_Pos             (9U)

+#define PWR_CPUCR_CSSF_Msk             (0x1UL << PWR_CPUCR_CSSF_Pos)           /*!< 0x00000200 */

+#define PWR_CPUCR_CSSF                 PWR_CPUCR_CSSF_Msk                      /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */

+#define PWR_CPUCR_SBF_D2_Pos           (8U)

+#define PWR_CPUCR_SBF_D2_Msk           (0x1UL << PWR_CPUCR_SBF_D2_Pos)         /*!< 0x00000100 */

+#define PWR_CPUCR_SBF_D2               PWR_CPUCR_SBF_D2_Msk                    /*!< D2 domain DSTANDBY Flag */

+#define PWR_CPUCR_SBF_D1_Pos           (7U)

+#define PWR_CPUCR_SBF_D1_Msk           (0x1UL << PWR_CPUCR_SBF_D1_Pos)         /*!< 0x00000080 */

+#define PWR_CPUCR_SBF_D1               PWR_CPUCR_SBF_D1_Msk                    /*!< D1 domain DSTANDBY Flag */

+#define PWR_CPUCR_SBF_Pos              (6U)

+#define PWR_CPUCR_SBF_Msk              (0x1UL << PWR_CPUCR_SBF_Pos)            /*!< 0x00000040 */

+#define PWR_CPUCR_SBF                  PWR_CPUCR_SBF_Msk                       /*!< System STANDBY Flag */

+#define PWR_CPUCR_STOPF_Pos            (5U)

+#define PWR_CPUCR_STOPF_Msk            (0x1UL << PWR_CPUCR_STOPF_Pos)          /*!< 0x00000020 */

+#define PWR_CPUCR_STOPF                PWR_CPUCR_STOPF_Msk                     /*!< STOP Flag */

+#define PWR_CPUCR_HOLD2F_Pos           (4U)

+#define PWR_CPUCR_HOLD2F_Msk           (0x1UL << PWR_CPUCR_HOLD2F_Pos)         /*!< 0x00000010 */

+#define PWR_CPUCR_HOLD2F               PWR_CPUCR_HOLD2F_Msk                    /*!< CPU2 in hold wakeup flag */

+#define PWR_CPUCR_PDDS_D3_Pos          (2U)

+#define PWR_CPUCR_PDDS_D3_Msk          (0x1UL << PWR_CPUCR_PDDS_D3_Pos)        /*!< 0x00000004 */

+#define PWR_CPUCR_PDDS_D3              PWR_CPUCR_PDDS_D3_Msk                   /*!< System D3 domain Power Down Deepsleep */

+#define PWR_CPUCR_PDDS_D2_Pos          (1U)

+#define PWR_CPUCR_PDDS_D2_Msk          (0x1UL << PWR_CPUCR_PDDS_D2_Pos)        /*!< 0x00000002 */

+#define PWR_CPUCR_PDDS_D2              PWR_CPUCR_PDDS_D2_Msk                   /*!< D2 domain Power Down Deepsleep */

+#define PWR_CPUCR_PDDS_D1_Pos          (0U)

+#define PWR_CPUCR_PDDS_D1_Msk          (0x1UL << PWR_CPUCR_PDDS_D1_Pos)        /*!< 0x00000001 */

+#define PWR_CPUCR_PDDS_D1              PWR_CPUCR_PDDS_D1_Msk                   /*!< D1 domain Power Down Deepsleep selection */

+

+/********************  Bit definition for PWR_CPU2CR register  ****************/

+#define PWR_CPU2CR_RUN_D3_Pos          (11U)

+#define PWR_CPU2CR_RUN_D3_Msk          (0x1UL << PWR_CPU2CR_RUN_D3_Pos)        /*!< 0x00000800 */

+#define PWR_CPU2CR_RUN_D3              PWR_CPU2CR_RUN_D3_Msk                   /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */

+#define PWR_CPU2CR_HOLD1_Pos           (10U)

+#define PWR_CPU2CR_HOLD1_Msk           (0x1UL << PWR_CPU2CR_HOLD1_Pos)         /*!< 0x00000400 */

+#define PWR_CPU2CR_HOLD1               PWR_CPU2CR_HOLD1_Msk                    /*!< Hold the CPU1 and allocated peripherals when exiting STOP mode */

+#define PWR_CPU2CR_CSSF_Pos            (9U)

+#define PWR_CPU2CR_CSSF_Msk            (0x1UL << PWR_CPU2CR_CSSF_Pos)          /*!< 0x00000200 */

+#define PWR_CPU2CR_CSSF                PWR_CPU2CR_CSSF_Msk                     /*!< Clear D2 domain CPU2 STANDBY, STOP and HOLD flags */

+#define PWR_CPU2CR_SBF_D2_Pos          (8U)

+#define PWR_CPU2CR_SBF_D2_Msk          (0x1UL << PWR_CPU2CR_SBF_D2_Pos)        /*!< 0x00000100 */

+#define PWR_CPU2CR_SBF_D2              PWR_CPU2CR_SBF_D2_Msk                   /*!< D2 domain DSTANDBY Flag */

+#define PWR_CPU2CR_SBF_D1_Pos          (7U)

+#define PWR_CPU2CR_SBF_D1_Msk          (0x1UL << PWR_CPU2CR_SBF_D1_Pos)        /*!< 0x00000080 */

+#define PWR_CPU2CR_SBF_D1              PWR_CPU2CR_SBF_D1_Msk                   /*!< D1 domain DSTANDBY Flag */

+#define PWR_CPU2CR_SBF_Pos             (6U)

+#define PWR_CPU2CR_SBF_Msk             (0x1UL << PWR_CPU2CR_SBF_Pos)           /*!< 0x00000040 */

+#define PWR_CPU2CR_SBF                 PWR_CPU2CR_SBF_Msk                      /*!< System STANDBY Flag */

+#define PWR_CPU2CR_STOPF_Pos           (5U)

+#define PWR_CPU2CR_STOPF_Msk           (0x1UL << PWR_CPU2CR_STOPF_Pos)         /*!< 0x00000020 */

+#define PWR_CPU2CR_STOPF               PWR_CPU2CR_STOPF_Msk                    /*!< STOP Flag */

+#define PWR_CPU2CR_HOLD1F_Pos          (4U)

+#define PWR_CPU2CR_HOLD1F_Msk          (0x1UL << PWR_CPU2CR_HOLD1F_Pos)        /*!< 0x00000010 */

+#define PWR_CPU2CR_HOLD1F              PWR_CPU2CR_HOLD1F_Msk                   /*!< CPU1 in hold wakeup flag */

+#define PWR_CPU2CR_PDDS_D3_Pos         (2U)

+#define PWR_CPU2CR_PDDS_D3_Msk         (0x1UL << PWR_CPU2CR_PDDS_D3_Pos)       /*!< 0x00000004 */

+#define PWR_CPU2CR_PDDS_D3             PWR_CPU2CR_PDDS_D3_Msk                  /*!< System D3 domain Power Down Deepsleep */

+#define PWR_CPU2CR_PDDS_D2_Pos         (1U)

+#define PWR_CPU2CR_PDDS_D2_Msk         (0x1UL << PWR_CPU2CR_PDDS_D2_Pos)       /*!< 0x00000002 */

+#define PWR_CPU2CR_PDDS_D2             PWR_CPU2CR_PDDS_D2_Msk                  /*!< D2 domain Power Down Deepsleep */

+#define PWR_CPU2CR_PDDS_D1_Pos         (0U)

+#define PWR_CPU2CR_PDDS_D1_Msk         (0x1UL << PWR_CPU2CR_PDDS_D1_Pos)       /*!< 0x00000001 */

+#define PWR_CPU2CR_PDDS_D1             PWR_CPU2CR_PDDS_D1_Msk                  /*!< D1 domain Power Down Deepsleep selection */

+

+

+/********************  Bit definition for PWR_D3CR register  ******************/

+#define PWR_D3CR_VOS_Pos               (14U)

+#define PWR_D3CR_VOS_Msk               (0x3UL << PWR_D3CR_VOS_Pos)             /*!< 0x0000C000 */

+#define PWR_D3CR_VOS                   PWR_D3CR_VOS_Msk                        /*!< Voltage Scaling selection according performance */

+#define PWR_D3CR_VOS_0                 (0x1UL << PWR_D3CR_VOS_Pos)             /*!< 0x00004000 */

+#define PWR_D3CR_VOS_1                 (0x2UL << PWR_D3CR_VOS_Pos)             /*!< 0x00008000 */

+#define PWR_D3CR_VOSRDY_Pos            (13U)

+#define PWR_D3CR_VOSRDY_Msk            (0x1UL << PWR_D3CR_VOSRDY_Pos)          /*!< 0x00002000 */

+#define PWR_D3CR_VOSRDY                PWR_D3CR_VOSRDY_Msk                     /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */

+

+/******************  Bit definition for PWR_WKUPCR register  ******************/

+#define PWR_WKUPCR_WKUPC6_Pos          (5U)

+#define PWR_WKUPCR_WKUPC6_Msk          (0x1UL << PWR_WKUPCR_WKUPC6_Pos)        /*!< 0x00000020 */

+#define PWR_WKUPCR_WKUPC6              PWR_WKUPCR_WKUPC6_Msk                   /*!< Clear Wakeup Pin Flag 6 */

+#define PWR_WKUPCR_WKUPC5_Pos          (4U)

+#define PWR_WKUPCR_WKUPC5_Msk          (0x1UL << PWR_WKUPCR_WKUPC5_Pos)        /*!< 0x00000010 */

+#define PWR_WKUPCR_WKUPC5              PWR_WKUPCR_WKUPC5_Msk                   /*!< Clear Wakeup Pin Flag 5 */

+#define PWR_WKUPCR_WKUPC4_Pos          (3U)

+#define PWR_WKUPCR_WKUPC4_Msk          (0x1UL << PWR_WKUPCR_WKUPC4_Pos)        /*!< 0x00000008 */

+#define PWR_WKUPCR_WKUPC4              PWR_WKUPCR_WKUPC4_Msk                   /*!< Clear Wakeup Pin Flag 4 */

+#define PWR_WKUPCR_WKUPC3_Pos          (2U)

+#define PWR_WKUPCR_WKUPC3_Msk          (0x1UL << PWR_WKUPCR_WKUPC3_Pos)        /*!< 0x00000004 */

+#define PWR_WKUPCR_WKUPC3              PWR_WKUPCR_WKUPC3_Msk                   /*!< Clear Wakeup Pin Flag 3 */

+#define PWR_WKUPCR_WKUPC2_Pos          (1U)

+#define PWR_WKUPCR_WKUPC2_Msk          (0x1UL << PWR_WKUPCR_WKUPC2_Pos)        /*!< 0x00000002 */

+#define PWR_WKUPCR_WKUPC2              PWR_WKUPCR_WKUPC2_Msk                   /*!< Clear Wakeup Pin Flag 2 */

+#define PWR_WKUPCR_WKUPC1_Pos          (0U)

+#define PWR_WKUPCR_WKUPC1_Msk          (0x1UL << PWR_WKUPCR_WKUPC1_Pos)        /*!< 0x00000001 */

+#define PWR_WKUPCR_WKUPC1              PWR_WKUPCR_WKUPC1_Msk                   /*!< Clear Wakeup Pin Flag 1 */

+

+/********************  Bit definition for PWR_WKUPFR register  ****************/

+#define PWR_WKUPFR_WKUPF6_Pos          (5U)

+#define PWR_WKUPFR_WKUPF6_Msk          (0x1UL << PWR_WKUPFR_WKUPF6_Pos)        /*!< 0x00000020 */

+#define PWR_WKUPFR_WKUPF6              PWR_WKUPFR_WKUPF6_Msk                   /*!< Wakeup Pin Flag 6 */

+#define PWR_WKUPFR_WKUPF5_Pos          (4U)

+#define PWR_WKUPFR_WKUPF5_Msk          (0x1UL << PWR_WKUPFR_WKUPF5_Pos)        /*!< 0x00000010 */

+#define PWR_WKUPFR_WKUPF5              PWR_WKUPFR_WKUPF5_Msk                   /*!< Wakeup Pin Flag 5 */

+#define PWR_WKUPFR_WKUPF4_Pos          (3U)

+#define PWR_WKUPFR_WKUPF4_Msk          (0x1UL << PWR_WKUPFR_WKUPF4_Pos)        /*!< 0x00000008 */

+#define PWR_WKUPFR_WKUPF4              PWR_WKUPFR_WKUPF4_Msk                   /*!< Wakeup Pin Flag 4 */

+#define PWR_WKUPFR_WKUPF3_Pos          (2U)

+#define PWR_WKUPFR_WKUPF3_Msk          (0x1UL << PWR_WKUPFR_WKUPF3_Pos)        /*!< 0x00000004 */

+#define PWR_WKUPFR_WKUPF3              PWR_WKUPFR_WKUPF3_Msk                   /*!< Wakeup Pin Flag 3 */

+#define PWR_WKUPFR_WKUPF2_Pos          (1U)

+#define PWR_WKUPFR_WKUPF2_Msk          (0x1UL << PWR_WKUPFR_WKUPF2_Pos)        /*!< 0x00000002 */

+#define PWR_WKUPFR_WKUPF2              PWR_WKUPFR_WKUPF2_Msk                   /*!< Wakeup Pin Flag 2 */

+#define PWR_WKUPFR_WKUPF1_Pos          (0U)

+#define PWR_WKUPFR_WKUPF1_Msk          (0x1UL << PWR_WKUPFR_WKUPF1_Pos)        /*!< 0x00000001 */

+#define PWR_WKUPFR_WKUPF1              PWR_WKUPFR_WKUPF1_Msk                   /*!< Wakeup Pin Flag 1 */

+

+/******************  Bit definition for PWR_WKUPEPR register  *****************/

+#define PWR_WKUPEPR_WKUPPUPD6_Pos      (26U)

+#define PWR_WKUPEPR_WKUPPUPD6_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x0C000000 */

+#define PWR_WKUPEPR_WKUPPUPD6          PWR_WKUPEPR_WKUPPUPD6_Msk               /*!< Wakeup Pin pull configuration for WKUP6 */

+#define PWR_WKUPEPR_WKUPPUPD6_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x04000000 */

+#define PWR_WKUPEPR_WKUPPUPD6_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x08000000 */

+#define PWR_WKUPEPR_WKUPPUPD5_Pos      (24U)

+#define PWR_WKUPEPR_WKUPPUPD5_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x03000000 */

+#define PWR_WKUPEPR_WKUPPUPD5          PWR_WKUPEPR_WKUPPUPD5_Msk               /*!< Wakeup Pin pull configuration for WKUP5 */

+#define PWR_WKUPEPR_WKUPPUPD5_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x01000000 */

+#define PWR_WKUPEPR_WKUPPUPD5_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x02000000 */

+#define PWR_WKUPEPR_WKUPPUPD4_Pos      (22U)

+#define PWR_WKUPEPR_WKUPPUPD4_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00C00000 */

+#define PWR_WKUPEPR_WKUPPUPD4          PWR_WKUPEPR_WKUPPUPD4_Msk               /*!< Wakeup Pin pull configuration for WKUP4 */

+#define PWR_WKUPEPR_WKUPPUPD4_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00400000 */

+#define PWR_WKUPEPR_WKUPPUPD4_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00800000 */

+#define PWR_WKUPEPR_WKUPPUPD3_Pos      (20U)

+#define PWR_WKUPEPR_WKUPPUPD3_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00300000 */

+#define PWR_WKUPEPR_WKUPPUPD3          PWR_WKUPEPR_WKUPPUPD3_Msk               /*!< Wakeup Pin pull configuration for WKUP3 */

+#define PWR_WKUPEPR_WKUPPUPD3_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00100000 */

+#define PWR_WKUPEPR_WKUPPUPD3_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00200000 */

+#define PWR_WKUPEPR_WKUPPUPD2_Pos      (18U)

+#define PWR_WKUPEPR_WKUPPUPD2_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x000C0000 */

+#define PWR_WKUPEPR_WKUPPUPD2          PWR_WKUPEPR_WKUPPUPD2_Msk               /*!< Wakeup Pin pull configuration for WKUP2 */

+#define PWR_WKUPEPR_WKUPPUPD2_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00040000 */

+#define PWR_WKUPEPR_WKUPPUPD2_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00080000 */

+#define PWR_WKUPEPR_WKUPPUPD1_Pos      (16U)

+#define PWR_WKUPEPR_WKUPPUPD1_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00030000 */

+#define PWR_WKUPEPR_WKUPPUPD1          PWR_WKUPEPR_WKUPPUPD1_Msk               /*!< Wakeup Pin pull configuration for WKUP1 */

+#define PWR_WKUPEPR_WKUPPUPD1_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00010000 */

+#define PWR_WKUPEPR_WKUPPUPD1_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00020000 */

+#define PWR_WKUPEPR_WKUPP6_Pos         (13U)

+#define PWR_WKUPEPR_WKUPP6_Msk         (0x1UL << PWR_WKUPEPR_WKUPP6_Pos)       /*!< 0x00002000 */

+#define PWR_WKUPEPR_WKUPP6             PWR_WKUPEPR_WKUPP6_Msk                  /*!< Wakeup Pin Polarity for WKUP6 */

+#define PWR_WKUPEPR_WKUPP5_Pos         (12U)

+#define PWR_WKUPEPR_WKUPP5_Msk         (0x1UL << PWR_WKUPEPR_WKUPP5_Pos)       /*!< 0x00001000 */

+#define PWR_WKUPEPR_WKUPP5             PWR_WKUPEPR_WKUPP5_Msk                  /*!< Wakeup Pin Polarity for WKUP5 */

+#define PWR_WKUPEPR_WKUPP4_Pos         (11U)

+#define PWR_WKUPEPR_WKUPP4_Msk         (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)       /*!< 0x00000800 */

+#define PWR_WKUPEPR_WKUPP4             PWR_WKUPEPR_WKUPP4_Msk                  /*!< Wakeup Pin Polarity for WKUP4 */

+#define PWR_WKUPEPR_WKUPP3_Pos         (10U)

+#define PWR_WKUPEPR_WKUPP3_Msk         (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)       /*!< 0x00000400 */

+#define PWR_WKUPEPR_WKUPP3             PWR_WKUPEPR_WKUPP3_Msk                  /*!< Wakeup Pin Polarity for WKUP3 */

+#define PWR_WKUPEPR_WKUPP2_Pos         (9U)

+#define PWR_WKUPEPR_WKUPP2_Msk         (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)       /*!< 0x00000200 */

+#define PWR_WKUPEPR_WKUPP2             PWR_WKUPEPR_WKUPP2_Msk                  /*!< Wakeup Pin Polarity for WKUP2 */

+#define PWR_WKUPEPR_WKUPP1_Pos         (8U)

+#define PWR_WKUPEPR_WKUPP1_Msk         (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)       /*!< 0x00000100 */

+#define PWR_WKUPEPR_WKUPP1             PWR_WKUPEPR_WKUPP1_Msk                  /*!< Wakeup Pin Polarity for WKUP1 */

+#define PWR_WKUPEPR_WKUPEN6_Pos        (5U)

+#define PWR_WKUPEPR_WKUPEN6_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos)      /*!< 0x00000020 */

+#define PWR_WKUPEPR_WKUPEN6            PWR_WKUPEPR_WKUPEN6_Msk                 /*!< Enable Wakeup Pin WKUP6 */

+#define PWR_WKUPEPR_WKUPEN5_Pos        (4U)

+#define PWR_WKUPEPR_WKUPEN5_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos)      /*!< 0x00000010 */

+#define PWR_WKUPEPR_WKUPEN5            PWR_WKUPEPR_WKUPEN5_Msk                 /*!< Enable Wakeup Pin WKUP5 */

+#define PWR_WKUPEPR_WKUPEN4_Pos        (3U)

+#define PWR_WKUPEPR_WKUPEN4_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)      /*!< 0x00000008 */

+#define PWR_WKUPEPR_WKUPEN4            PWR_WKUPEPR_WKUPEN4_Msk                 /*!< Enable Wakeup Pin WKUP4 */

+#define PWR_WKUPEPR_WKUPEN3_Pos        (2U)

+#define PWR_WKUPEPR_WKUPEN3_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)      /*!< 0x00000004 */

+#define PWR_WKUPEPR_WKUPEN3            PWR_WKUPEPR_WKUPEN3_Msk                 /*!< Enable Wakeup Pin WKUP3 */

+#define PWR_WKUPEPR_WKUPEN2_Pos        (1U)

+#define PWR_WKUPEPR_WKUPEN2_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)      /*!< 0x00000002 */

+#define PWR_WKUPEPR_WKUPEN2            PWR_WKUPEPR_WKUPEN2_Msk                 /*!< Enable Wakeup Pin WKUP2 */

+#define PWR_WKUPEPR_WKUPEN1_Pos        (0U)

+#define PWR_WKUPEPR_WKUPEN1_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)      /*!< 0x00000001 */

+#define PWR_WKUPEPR_WKUPEN1            PWR_WKUPEPR_WKUPEN1_Msk                 /*!< Enable Wakeup Pin WKUP1 */

+#define PWR_WKUPEPR_WKUPEN_Pos         (0U)

+#define PWR_WKUPEPR_WKUPEN_Msk         (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos)      /*!< 0x0000003F */

+#define PWR_WKUPEPR_WKUPEN             PWR_WKUPEPR_WKUPEN_Msk                  /*!< Enable all Wakeup Pin */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Reset and Clock Control                            */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  RCC VERSION  ********************************/

+#define RCC_VER_X

+

+/********************  Bit definition for RCC_CR register  ********************/

+#define RCC_CR_HSION_Pos                       (0U)

+#define RCC_CR_HSION_Msk                       (0x1UL << RCC_CR_HSION_Pos)     /*!< 0x00000001 */

+#define RCC_CR_HSION                           RCC_CR_HSION_Msk                /*!< Internal High Speed clock enable */

+#define RCC_CR_HSIKERON_Pos                    (1U)

+#define RCC_CR_HSIKERON_Msk                    (0x1UL << RCC_CR_HSIKERON_Pos)  /*!< 0x00000002 */

+#define RCC_CR_HSIKERON                        RCC_CR_HSIKERON_Msk             /*!< Internal High Speed clock enable for some IPs Kernel */

+#define RCC_CR_HSIRDY_Pos                      (2U)

+#define RCC_CR_HSIRDY_Msk                      (0x1UL << RCC_CR_HSIRDY_Pos)    /*!< 0x00000004 */

+#define RCC_CR_HSIRDY                          RCC_CR_HSIRDY_Msk               /*!< Internal High Speed clock ready flag */

+#define RCC_CR_HSIDIV_Pos                      (3U)

+#define RCC_CR_HSIDIV_Msk                      (0x3UL << RCC_CR_HSIDIV_Pos)    /*!< 0x00000018 */

+#define RCC_CR_HSIDIV                          RCC_CR_HSIDIV_Msk               /*!< Internal High Speed clock divider selection */

+#define RCC_CR_HSIDIV_1                        (0x0UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000000 */

+#define RCC_CR_HSIDIV_2                        (0x1UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000008 */

+#define RCC_CR_HSIDIV_4                        (0x2UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000010 */

+#define RCC_CR_HSIDIV_8                        (0x3UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000018 */

+

+#define RCC_CR_HSIDIVF_Pos                     (5U)

+#define RCC_CR_HSIDIVF_Msk                     (0x1UL << RCC_CR_HSIDIVF_Pos)   /*!< 0x00000020 */

+#define RCC_CR_HSIDIVF                         RCC_CR_HSIDIVF_Msk              /*!< HSI Divider flag */

+#define RCC_CR_CSION_Pos                       (7U)

+#define RCC_CR_CSION_Msk                       (0x1UL << RCC_CR_CSION_Pos)     /*!< 0x00000080 */

+#define RCC_CR_CSION                           RCC_CR_CSION_Msk                /*!< The Internal RC 4MHz oscillator clock enable */

+#define RCC_CR_CSIRDY_Pos                      (8U)

+#define RCC_CR_CSIRDY_Msk                      (0x1UL << RCC_CR_CSIRDY_Pos)    /*!< 0x00000100 */

+#define RCC_CR_CSIRDY                          RCC_CR_CSIRDY_Msk               /*!< The Internal RC 4MHz oscillator clock ready */

+#define RCC_CR_CSIKERON_Pos                    (9U)

+#define RCC_CR_CSIKERON_Msk                    (0x1UL << RCC_CR_CSIKERON_Pos)  /*!< 0x00000200 */

+#define RCC_CR_CSIKERON                        RCC_CR_CSIKERON_Msk             /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */

+#define RCC_CR_HSI48ON_Pos                     (12U)

+#define RCC_CR_HSI48ON_Msk                     (0x1UL << RCC_CR_HSI48ON_Pos)   /*!< 0x00001000 */

+#define RCC_CR_HSI48ON                         RCC_CR_HSI48ON_Msk              /*!< HSI48 clock enable clock enable  */

+#define RCC_CR_HSI48RDY_Pos                    (13U)

+#define RCC_CR_HSI48RDY_Msk                    (0x1UL << RCC_CR_HSI48RDY_Pos)  /*!< 0x00002000 */

+#define RCC_CR_HSI48RDY                        RCC_CR_HSI48RDY_Msk             /*!< HSI48 clock ready */

+

+#define RCC_CR_D1CKRDY_Pos                     (14U)

+#define RCC_CR_D1CKRDY_Msk                     (0x1UL << RCC_CR_D1CKRDY_Pos)   /*!< 0x00004000 */

+#define RCC_CR_D1CKRDY                         RCC_CR_D1CKRDY_Msk              /*!< D1 domain clocks ready flag  */

+#define RCC_CR_D2CKRDY_Pos                     (15U)

+#define RCC_CR_D2CKRDY_Msk                     (0x1UL << RCC_CR_D2CKRDY_Pos)   /*!< 0x00008000 */

+#define RCC_CR_D2CKRDY                         RCC_CR_D2CKRDY_Msk              /*!< D2 domain clocks ready flag */

+

+#define RCC_CR_HSEON_Pos                       (16U)

+#define RCC_CR_HSEON_Msk                       (0x1UL << RCC_CR_HSEON_Pos)     /*!< 0x00010000 */

+#define RCC_CR_HSEON                           RCC_CR_HSEON_Msk                /*!< External High Speed clock enable */

+#define RCC_CR_HSERDY_Pos                      (17U)

+#define RCC_CR_HSERDY_Msk                      (0x1UL << RCC_CR_HSERDY_Pos)    /*!< 0x00020000 */

+#define RCC_CR_HSERDY                          RCC_CR_HSERDY_Msk               /*!< External High Speed clock ready */

+#define RCC_CR_HSEBYP_Pos                      (18U)

+#define RCC_CR_HSEBYP_Msk                      (0x1UL << RCC_CR_HSEBYP_Pos)    /*!< 0x00040000 */

+#define RCC_CR_HSEBYP                          RCC_CR_HSEBYP_Msk               /*!< External High Speed clock Bypass */

+#define RCC_CR_CSSHSEON_Pos                    (19U)

+#define RCC_CR_CSSHSEON_Msk                    (0x1UL << RCC_CR_CSSHSEON_Pos)  /*!< 0x00080000 */

+#define RCC_CR_CSSHSEON                        RCC_CR_CSSHSEON_Msk             /*!< HSE Clock security System enable */

+

+

+#define RCC_CR_PLL1ON_Pos                      (24U)

+#define RCC_CR_PLL1ON_Msk                      (0x1UL << RCC_CR_PLL1ON_Pos)    /*!< 0x01000000 */

+#define RCC_CR_PLL1ON                          RCC_CR_PLL1ON_Msk               /*!< System PLL1 clock enable */

+#define RCC_CR_PLL1RDY_Pos                     (25U)

+#define RCC_CR_PLL1RDY_Msk                     (0x1UL << RCC_CR_PLL1RDY_Pos)   /*!< 0x02000000 */

+#define RCC_CR_PLL1RDY                         RCC_CR_PLL1RDY_Msk              /*!< System PLL1 clock ready */

+#define RCC_CR_PLL2ON_Pos                      (26U)

+#define RCC_CR_PLL2ON_Msk                      (0x1UL << RCC_CR_PLL2ON_Pos)    /*!< 0x04000000 */

+#define RCC_CR_PLL2ON                          RCC_CR_PLL2ON_Msk               /*!< System PLL2 clock enable */

+#define RCC_CR_PLL2RDY_Pos                     (27U)

+#define RCC_CR_PLL2RDY_Msk                     (0x1UL << RCC_CR_PLL2RDY_Pos)   /*!< 0x08000000 */

+#define RCC_CR_PLL2RDY                         RCC_CR_PLL2RDY_Msk              /*!< System PLL2 clock ready */

+#define RCC_CR_PLL3ON_Pos                      (28U)

+#define RCC_CR_PLL3ON_Msk                      (0x1UL << RCC_CR_PLL3ON_Pos)    /*!< 0x10000000 */

+#define RCC_CR_PLL3ON                          RCC_CR_PLL3ON_Msk               /*!< System PLL3 clock enable */

+#define RCC_CR_PLL3RDY_Pos                     (29U)

+#define RCC_CR_PLL3RDY_Msk                     (0x1UL << RCC_CR_PLL3RDY_Pos)   /*!< 0x20000000 */

+#define RCC_CR_PLL3RDY                         RCC_CR_PLL3RDY_Msk              /*!< System PLL3 clock ready */

+

+/*Legacy */

+#define RCC_CR_PLLON_Pos                       (24U)

+#define RCC_CR_PLLON_Msk                       (0x1UL << RCC_CR_PLLON_Pos)     /*!< 0x01000000 */

+#define RCC_CR_PLLON                           RCC_CR_PLLON_Msk                /*!< System PLL clock enable */

+#define RCC_CR_PLLRDY_Pos                      (25U)

+#define RCC_CR_PLLRDY_Msk                      (0x1UL << RCC_CR_PLLRDY_Pos)    /*!< 0x02000000 */

+#define RCC_CR_PLLRDY                          RCC_CR_PLLRDY_Msk               /*!< System PLL clock ready */

+

+/********************  Bit definition for RCC_HSICFGR register  ***************/

+/*!< HSICAL configuration */

+#define RCC_HSICFGR_HSICAL_Pos                 (0U)

+#define RCC_HSICFGR_HSICAL_Msk                 (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */

+#define RCC_HSICFGR_HSICAL                     RCC_HSICFGR_HSICAL_Msk          /*!< HSICAL[11:0] bits */

+#define RCC_HSICFGR_HSICAL_0                   (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */

+#define RCC_HSICFGR_HSICAL_1                   (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */

+#define RCC_HSICFGR_HSICAL_2                   (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */

+#define RCC_HSICFGR_HSICAL_3                   (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */

+#define RCC_HSICFGR_HSICAL_4                   (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */

+#define RCC_HSICFGR_HSICAL_5                   (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */

+#define RCC_HSICFGR_HSICAL_6                   (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */

+#define RCC_HSICFGR_HSICAL_7                   (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */

+#define RCC_HSICFGR_HSICAL_8                   (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */

+#define RCC_HSICFGR_HSICAL_9                   (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */

+#define RCC_HSICFGR_HSICAL_10                  (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */

+#define RCC_HSICFGR_HSICAL_11                  (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */

+

+/*!< HSITRIM configuration */

+#define RCC_HSICFGR_HSITRIM_Pos                (24U)

+#define RCC_HSICFGR_HSITRIM_Msk                (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */

+#define RCC_HSICFGR_HSITRIM                    RCC_HSICFGR_HSITRIM_Msk         /*!< HSITRIM[6:0] bits */

+#define RCC_HSICFGR_HSITRIM_0                  (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */

+#define RCC_HSICFGR_HSITRIM_1                  (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */

+#define RCC_HSICFGR_HSITRIM_2                  (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */

+#define RCC_HSICFGR_HSITRIM_3                  (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */

+#define RCC_HSICFGR_HSITRIM_4                  (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */

+#define RCC_HSICFGR_HSITRIM_5                  (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */

+#define RCC_HSICFGR_HSITRIM_6                  (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */

+

+

+/********************  Bit definition for RCC_CRRCR register  *****************/

+

+/*!< HSI48CAL configuration */

+#define RCC_CRRCR_HSI48CAL_Pos                 (0U)

+#define RCC_CRRCR_HSI48CAL_Msk                 (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */

+#define RCC_CRRCR_HSI48CAL                     RCC_CRRCR_HSI48CAL_Msk          /*!< HSI48CAL[9:0] bits */

+#define RCC_CRRCR_HSI48CAL_0                   (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */

+#define RCC_CRRCR_HSI48CAL_1                   (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */

+#define RCC_CRRCR_HSI48CAL_2                   (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */

+#define RCC_CRRCR_HSI48CAL_3                   (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */

+#define RCC_CRRCR_HSI48CAL_4                   (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */

+#define RCC_CRRCR_HSI48CAL_5                   (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */

+#define RCC_CRRCR_HSI48CAL_6                   (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */

+#define RCC_CRRCR_HSI48CAL_7                   (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */

+#define RCC_CRRCR_HSI48CAL_8                   (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */

+#define RCC_CRRCR_HSI48CAL_9                   (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */

+

+

+/********************  Bit definition for RCC_CSICFGR register  *****************/

+/*!< CSICAL configuration */

+#define RCC_CSICFGR_CSICAL_Pos                 (0U)

+#define RCC_CSICFGR_CSICAL_Msk                 (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */

+#define RCC_CSICFGR_CSICAL                     RCC_CSICFGR_CSICAL_Msk          /*!< CSICAL[7:0] bits */

+#define RCC_CSICFGR_CSICAL_0                   (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */

+#define RCC_CSICFGR_CSICAL_1                   (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */

+#define RCC_CSICFGR_CSICAL_2                   (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */

+#define RCC_CSICFGR_CSICAL_3                   (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */

+#define RCC_CSICFGR_CSICAL_4                   (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */

+#define RCC_CSICFGR_CSICAL_5                   (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */

+#define RCC_CSICFGR_CSICAL_6                   (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */

+#define RCC_CSICFGR_CSICAL_7                   (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */

+

+/*!< CSITRIM configuration */

+#define RCC_CSICFGR_CSITRIM_Pos                (24U)

+#define RCC_CSICFGR_CSITRIM_Msk                (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */

+#define RCC_CSICFGR_CSITRIM                    RCC_CSICFGR_CSITRIM_Msk         /*!< CSITRIM[5:0] bits */

+#define RCC_CSICFGR_CSITRIM_0                  (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */

+#define RCC_CSICFGR_CSITRIM_1                  (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */

+#define RCC_CSICFGR_CSITRIM_2                  (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */

+#define RCC_CSICFGR_CSITRIM_3                  (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */

+#define RCC_CSICFGR_CSITRIM_4                  (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */

+#define RCC_CSICFGR_CSITRIM_5                  (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */

+

+/********************  Bit definition for RCC_CFGR register  ******************/

+/*!< SW configuration */

+#define RCC_CFGR_SW_Pos                        (0U)

+#define RCC_CFGR_SW_Msk                        (0x7UL << RCC_CFGR_SW_Pos)           /*!< 0x00000007 */

+#define RCC_CFGR_SW                            RCC_CFGR_SW_Msk                     /*!< SW[2:0] bits (System clock Switch) */

+#define RCC_CFGR_SW_0                          (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */

+#define RCC_CFGR_SW_1                          (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */

+#define RCC_CFGR_SW_2                          (0x4UL << RCC_CFGR_SW_Pos)           /*!< 0x00000004 */

+

+#define RCC_CFGR_SW_HSI                        (0x00000000UL)                       /*!< HSI selection as system clock */

+#define RCC_CFGR_SW_CSI                        (0x00000001UL)                       /*!< CSI selection as system clock */

+#define RCC_CFGR_SW_HSE                        (0x00000002UL)                       /*!< HSE selection as system clock */

+#define RCC_CFGR_SW_PLL1                       (0x00000003UL)                       /*!< PLL1 selection as system clock */

+

+/*!< SWS configuration */

+#define RCC_CFGR_SWS_Pos                       (3U)

+#define RCC_CFGR_SWS_Msk                       (0x7UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000038 */

+#define RCC_CFGR_SWS                           RCC_CFGR_SWS_Msk                    /*!< SWS[2:0] bits (System Clock Switch Status) */

+#define RCC_CFGR_SWS_0                         (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */

+#define RCC_CFGR_SWS_1                         (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000010 */

+#define RCC_CFGR_SWS_2                         (0x4UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000020 */

+

+#define RCC_CFGR_SWS_HSI                       (0x00000000UL)                       /*!< HSI used as system clock */

+#define RCC_CFGR_SWS_CSI                       (0x00000008UL)                       /*!< CSI used as system clock */

+#define RCC_CFGR_SWS_HSE                       (0x00000010UL)                       /*!< HSE used as system clock */

+#define RCC_CFGR_SWS_PLL1                      (0x00000018UL)                       /*!< PLL1 used as system clock */

+

+#define RCC_CFGR_STOPWUCK_Pos                  (6U)

+#define RCC_CFGR_STOPWUCK_Msk                  (0x1UL << RCC_CFGR_STOPWUCK_Pos)     /*!< 0x00000040 */

+#define RCC_CFGR_STOPWUCK                      RCC_CFGR_STOPWUCK_Msk                /*!< Wake Up from stop and CSS backup clock selection */

+

+#define RCC_CFGR_STOPKERWUCK_Pos               (7U)

+#define RCC_CFGR_STOPKERWUCK_Msk               (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)  /*!< 0x00000080 */

+#define RCC_CFGR_STOPKERWUCK                   RCC_CFGR_STOPKERWUCK_Msk             /*!< Kernel Clock Selection after a Wake Up from STOP */

+

+/*!< RTCPRE configuration */

+#define RCC_CFGR_RTCPRE_Pos                    (8U)

+#define RCC_CFGR_RTCPRE_Msk                    (0x3FUL << RCC_CFGR_RTCPRE_Pos)

+#define RCC_CFGR_RTCPRE                        RCC_CFGR_RTCPRE_Msk                  /*!< 0x00003F00 */

+#define RCC_CFGR_RTCPRE_0                      (0x1UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000100 */

+#define RCC_CFGR_RTCPRE_1                      (0x2UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000200 */

+#define RCC_CFGR_RTCPRE_2                      (0x4UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000400 */

+#define RCC_CFGR_RTCPRE_3                      (0x8UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000800 */

+#define RCC_CFGR_RTCPRE_4                      (0x10UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00001000 */

+#define RCC_CFGR_RTCPRE_5                      (0x20UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00002000 */

+

+/*!< HRTIMSEL configuration */

+#define RCC_CFGR_HRTIMSEL_Pos                  (14U)

+#define RCC_CFGR_HRTIMSEL_Msk                  (0x1UL << RCC_CFGR_HRTIMSEL_Pos)

+#define RCC_CFGR_HRTIMSEL                      RCC_CFGR_HRTIMSEL_Msk                /*!< 0x00004000 */

+

+/*!< TIMPRE configuration */

+#define RCC_CFGR_TIMPRE_Pos                    (15U)

+#define RCC_CFGR_TIMPRE_Msk                    (0x1UL << RCC_CFGR_TIMPRE_Pos)

+#define RCC_CFGR_TIMPRE                        RCC_CFGR_TIMPRE_Msk                  /*!< 0x00008000 */

+

+/*!< MCO1 configuration */

+#define RCC_CFGR_MCO1_Pos                      (22U)

+#define RCC_CFGR_MCO1_Msk                      (0x7UL << RCC_CFGR_MCO1_Pos)

+#define RCC_CFGR_MCO1                          RCC_CFGR_MCO1_Msk                       /*!< 0x01C00000 */

+#define RCC_CFGR_MCO1_0                        (0x1UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00400000 */

+#define RCC_CFGR_MCO1_1                        (0x2UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00800000 */

+#define RCC_CFGR_MCO1_2                        (0x4UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x01000000 */

+

+#define RCC_CFGR_MCO1PRE_Pos                   (18U)

+#define RCC_CFGR_MCO1PRE_Msk                   (0xFUL << RCC_CFGR_MCO1PRE_Pos)

+#define RCC_CFGR_MCO1PRE                       RCC_CFGR_MCO1PRE_Msk                    /*!< 0x003C0000 */

+#define RCC_CFGR_MCO1PRE_0                     (0x1UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00040000 */

+#define RCC_CFGR_MCO1PRE_1                     (0x2UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00080000 */

+#define RCC_CFGR_MCO1PRE_2                     (0x4UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00100000 */

+#define RCC_CFGR_MCO1PRE_3                     (0x8UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00200000 */

+

+#define RCC_CFGR_MCO2PRE_Pos                   (25U)

+#define RCC_CFGR_MCO2PRE_Msk                   (0xFUL << RCC_CFGR_MCO2PRE_Pos)

+#define RCC_CFGR_MCO2PRE                       RCC_CFGR_MCO2PRE_Msk                    /*!< 0x1E000000 */

+#define RCC_CFGR_MCO2PRE_0                     (0x1UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x02000000 */

+#define RCC_CFGR_MCO2PRE_1                     (0x2UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x04000000 */

+#define RCC_CFGR_MCO2PRE_2                     (0x4UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x08000000 */

+#define RCC_CFGR_MCO2PRE_3                     (0x8UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x10000000 */

+

+#define RCC_CFGR_MCO2_Pos                      (29U)

+#define RCC_CFGR_MCO2_Msk                      (0x7UL << RCC_CFGR_MCO2_Pos)

+#define RCC_CFGR_MCO2                          RCC_CFGR_MCO2_Msk                       /*!< 0xE0000000 */

+#define RCC_CFGR_MCO2_0                        (0x1UL << RCC_CFGR_MCO2_Pos)             /*!< 0x20000000 */

+#define RCC_CFGR_MCO2_1                        (0x2UL << RCC_CFGR_MCO2_Pos)             /*!< 0x40000000 */

+#define RCC_CFGR_MCO2_2                        (0x4UL << RCC_CFGR_MCO2_Pos)             /*!< 0x80000000 */

+

+/********************  Bit definition for RCC_D1CFGR register  ******************/

+/*!< D1HPRE configuration */

+#define RCC_D1CFGR_HPRE_Pos                    (0U)

+#define RCC_D1CFGR_HPRE_Msk                    (0xFUL << RCC_D1CFGR_HPRE_Pos)  /*!< 0x0000000F */

+#define RCC_D1CFGR_HPRE                        RCC_D1CFGR_HPRE_Msk             /*!< HPRE[3:0] bits (AHB3 prescaler) */

+#define RCC_D1CFGR_HPRE_0                      (0x1UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000001 */

+#define RCC_D1CFGR_HPRE_1                      (0x2UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000002 */

+#define RCC_D1CFGR_HPRE_2                      (0x4UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000004 */

+#define RCC_D1CFGR_HPRE_3                      (0x8UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000008 */

+

+

+#define RCC_D1CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)          /*!< AHB3 Clock not divided */

+#define RCC_D1CFGR_HPRE_DIV2_Pos               (3U)

+#define RCC_D1CFGR_HPRE_DIV2_Msk               (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */

+#define RCC_D1CFGR_HPRE_DIV2                   RCC_D1CFGR_HPRE_DIV2_Msk        /*!< AHB3 Clock divided by 2 */

+#define RCC_D1CFGR_HPRE_DIV4_Pos               (0U)

+#define RCC_D1CFGR_HPRE_DIV4_Msk               (0x9UL << RCC_D1CFGR_HPRE_DIV4_Pos) /*!< 0x00000009 */

+#define RCC_D1CFGR_HPRE_DIV4                   RCC_D1CFGR_HPRE_DIV4_Msk        /*!< AHB3 Clock divided by 4 */

+#define RCC_D1CFGR_HPRE_DIV8_Pos               (1U)

+#define RCC_D1CFGR_HPRE_DIV8_Msk               (0x5UL << RCC_D1CFGR_HPRE_DIV8_Pos) /*!< 0x0000000A */

+#define RCC_D1CFGR_HPRE_DIV8                   RCC_D1CFGR_HPRE_DIV8_Msk        /*!< AHB3 Clock divided by 8 */

+#define RCC_D1CFGR_HPRE_DIV16_Pos              (0U)

+#define RCC_D1CFGR_HPRE_DIV16_Msk              (0xBUL << RCC_D1CFGR_HPRE_DIV16_Pos) /*!< 0x0000000B */

+#define RCC_D1CFGR_HPRE_DIV16                  RCC_D1CFGR_HPRE_DIV16_Msk       /*!< AHB3 Clock divided by 16 */

+#define RCC_D1CFGR_HPRE_DIV64_Pos              (2U)

+#define RCC_D1CFGR_HPRE_DIV64_Msk              (0x3UL << RCC_D1CFGR_HPRE_DIV64_Pos) /*!< 0x0000000C */

+#define RCC_D1CFGR_HPRE_DIV64                  RCC_D1CFGR_HPRE_DIV64_Msk       /*!< AHB3 Clock divided by 64 */

+#define RCC_D1CFGR_HPRE_DIV128_Pos             (0U)

+#define RCC_D1CFGR_HPRE_DIV128_Msk             (0xDUL << RCC_D1CFGR_HPRE_DIV128_Pos) /*!< 0x0000000D */

+#define RCC_D1CFGR_HPRE_DIV128                 RCC_D1CFGR_HPRE_DIV128_Msk      /*!< AHB3 Clock divided by 128 */

+#define RCC_D1CFGR_HPRE_DIV256_Pos             (1U)

+#define RCC_D1CFGR_HPRE_DIV256_Msk             (0x7UL << RCC_D1CFGR_HPRE_DIV256_Pos) /*!< 0x0000000E */

+#define RCC_D1CFGR_HPRE_DIV256                 RCC_D1CFGR_HPRE_DIV256_Msk      /*!< AHB3 Clock divided by 256 */

+#define RCC_D1CFGR_HPRE_DIV512_Pos             (0U)

+#define RCC_D1CFGR_HPRE_DIV512_Msk             (0xFUL << RCC_D1CFGR_HPRE_DIV512_Pos) /*!< 0x0000000F */

+#define RCC_D1CFGR_HPRE_DIV512                 RCC_D1CFGR_HPRE_DIV512_Msk      /*!< AHB3 Clock divided by 512 */

+

+/*!< D1PPRE configuration */

+#define RCC_D1CFGR_D1PPRE_Pos                  (4U)

+#define RCC_D1CFGR_D1PPRE_Msk                  (0x7UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000070 */

+#define RCC_D1CFGR_D1PPRE                      RCC_D1CFGR_D1PPRE_Msk           /*!< D1PRE[2:0] bits (APB3 prescaler) */

+#define RCC_D1CFGR_D1PPRE_0                    (0x1UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000010 */

+#define RCC_D1CFGR_D1PPRE_1                    (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */

+#define RCC_D1CFGR_D1PPRE_2                    (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */

+

+#define RCC_D1CFGR_D1PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB3 clock not divided */

+#define RCC_D1CFGR_D1PPRE_DIV2_Pos             (6U)

+#define RCC_D1CFGR_D1PPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_D1CFGR_D1PPRE_DIV2                 RCC_D1CFGR_D1PPRE_DIV2_Msk      /*!< APB3 clock divided by 2 */

+#define RCC_D1CFGR_D1PPRE_DIV4_Pos             (4U)

+#define RCC_D1CFGR_D1PPRE_DIV4_Msk             (0x5UL << RCC_D1CFGR_D1PPRE_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_D1CFGR_D1PPRE_DIV4                 RCC_D1CFGR_D1PPRE_DIV4_Msk      /*!< APB3 clock divided by 4 */

+#define RCC_D1CFGR_D1PPRE_DIV8_Pos             (5U)

+#define RCC_D1CFGR_D1PPRE_DIV8_Msk             (0x3UL << RCC_D1CFGR_D1PPRE_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_D1CFGR_D1PPRE_DIV8                 RCC_D1CFGR_D1PPRE_DIV8_Msk      /*!< APB3 clock divided by 8 */

+#define RCC_D1CFGR_D1PPRE_DIV16_Pos            (4U)

+#define RCC_D1CFGR_D1PPRE_DIV16_Msk            (0x7UL << RCC_D1CFGR_D1PPRE_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_D1CFGR_D1PPRE_DIV16                RCC_D1CFGR_D1PPRE_DIV16_Msk     /*!< APB3 clock divided by 16 */

+

+#define RCC_D1CFGR_D1CPRE_Pos                  (8U)

+#define RCC_D1CFGR_D1CPRE_Msk                  (0xFUL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000F00 */

+#define RCC_D1CFGR_D1CPRE                      RCC_D1CFGR_D1CPRE_Msk           /*!< D1CPRE[2:0] bits (Domain 1 Core prescaler) */

+#define RCC_D1CFGR_D1CPRE_0                    (0x1UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000100 */

+#define RCC_D1CFGR_D1CPRE_1                    (0x2UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000200 */

+#define RCC_D1CFGR_D1CPRE_2                    (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */

+#define RCC_D1CFGR_D1CPRE_3                    (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */

+

+#define RCC_D1CFGR_D1CPRE_DIV1                 ((uint32_t)0x00000000)          /*!< Domain 1 Core clock not divided */

+#define RCC_D1CFGR_D1CPRE_DIV2_Pos             (11U)

+#define RCC_D1CFGR_D1CPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */

+#define RCC_D1CFGR_D1CPRE_DIV2                 RCC_D1CFGR_D1CPRE_DIV2_Msk      /*!< Domain 1 Core clock divided by 2 */

+#define RCC_D1CFGR_D1CPRE_DIV4_Pos             (8U)

+#define RCC_D1CFGR_D1CPRE_DIV4_Msk             (0x9UL << RCC_D1CFGR_D1CPRE_DIV4_Pos) /*!< 0x00000900 */

+#define RCC_D1CFGR_D1CPRE_DIV4                 RCC_D1CFGR_D1CPRE_DIV4_Msk      /*!< Domain 1 Core clock divided by 4 */

+#define RCC_D1CFGR_D1CPRE_DIV8_Pos             (9U)

+#define RCC_D1CFGR_D1CPRE_DIV8_Msk             (0x5UL << RCC_D1CFGR_D1CPRE_DIV8_Pos) /*!< 0x00000A00 */

+#define RCC_D1CFGR_D1CPRE_DIV8                 RCC_D1CFGR_D1CPRE_DIV8_Msk      /*!< Domain 1 Core clock divided by 8 */

+#define RCC_D1CFGR_D1CPRE_DIV16_Pos            (8U)

+#define RCC_D1CFGR_D1CPRE_DIV16_Msk            (0xBUL << RCC_D1CFGR_D1CPRE_DIV16_Pos) /*!< 0x00000B00 */

+#define RCC_D1CFGR_D1CPRE_DIV16                RCC_D1CFGR_D1CPRE_DIV16_Msk     /*!< Domain 1 Core clock divided by 16 */

+#define RCC_D1CFGR_D1CPRE_DIV64_Pos            (10U)

+#define RCC_D1CFGR_D1CPRE_DIV64_Msk            (0x3UL << RCC_D1CFGR_D1CPRE_DIV64_Pos) /*!< 0x00000C00 */

+#define RCC_D1CFGR_D1CPRE_DIV64                RCC_D1CFGR_D1CPRE_DIV64_Msk     /*!< Domain 1 Core clock divided by 64 */

+#define RCC_D1CFGR_D1CPRE_DIV128_Pos           (8U)

+#define RCC_D1CFGR_D1CPRE_DIV128_Msk           (0xDUL << RCC_D1CFGR_D1CPRE_DIV128_Pos) /*!< 0x00000D00 */

+#define RCC_D1CFGR_D1CPRE_DIV128               RCC_D1CFGR_D1CPRE_DIV128_Msk    /*!< Domain 1 Core clock divided by 128 */

+#define RCC_D1CFGR_D1CPRE_DIV256_Pos           (9U)

+#define RCC_D1CFGR_D1CPRE_DIV256_Msk           (0x7UL << RCC_D1CFGR_D1CPRE_DIV256_Pos) /*!< 0x00000E00 */

+#define RCC_D1CFGR_D1CPRE_DIV256               RCC_D1CFGR_D1CPRE_DIV256_Msk    /*!< Domain 1 Core clock divided by 256 */

+#define RCC_D1CFGR_D1CPRE_DIV512_Pos           (8U)

+#define RCC_D1CFGR_D1CPRE_DIV512_Msk           (0xFUL << RCC_D1CFGR_D1CPRE_DIV512_Pos) /*!< 0x00000F00 */

+#define RCC_D1CFGR_D1CPRE_DIV512               RCC_D1CFGR_D1CPRE_DIV512_Msk    /*!< Domain 1 Core clock divided by 512 */

+

+/********************  Bit definition for RCC_D2CFGR register  ******************/

+/*!< D2PPRE1 configuration */

+#define RCC_D2CFGR_D2PPRE1_Pos                 (4U)

+#define RCC_D2CFGR_D2PPRE1_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000070 */

+#define RCC_D2CFGR_D2PPRE1                     RCC_D2CFGR_D2PPRE1_Msk          /*!< D1PPRE1[2:0] bits (APB1 prescaler) */

+#define RCC_D2CFGR_D2PPRE1_0                   (0x1UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000010 */

+#define RCC_D2CFGR_D2PPRE1_1                   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */

+#define RCC_D2CFGR_D2PPRE1_2                   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */

+

+#define RCC_D2CFGR_D2PPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */

+#define RCC_D2CFGR_D2PPRE1_DIV2_Pos            (6U)

+#define RCC_D2CFGR_D2PPRE1_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_D2CFGR_D2PPRE1_DIV2                RCC_D2CFGR_D2PPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */

+#define RCC_D2CFGR_D2PPRE1_DIV4_Pos            (4U)

+#define RCC_D2CFGR_D2PPRE1_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE1_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_D2CFGR_D2PPRE1_DIV4                RCC_D2CFGR_D2PPRE1_DIV4_Msk     /*!< APB1 clock divided by 4 */

+#define RCC_D2CFGR_D2PPRE1_DIV8_Pos            (5U)

+#define RCC_D2CFGR_D2PPRE1_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE1_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_D2CFGR_D2PPRE1_DIV8                RCC_D2CFGR_D2PPRE1_DIV8_Msk     /*!< APB1 clock divided by 8 */

+#define RCC_D2CFGR_D2PPRE1_DIV16_Pos           (4U)

+#define RCC_D2CFGR_D2PPRE1_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE1_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_D2CFGR_D2PPRE1_DIV16               RCC_D2CFGR_D2PPRE1_DIV16_Msk    /*!< APB1 clock divided by 16 */

+

+/*!< D2PPRE2 configuration */

+#define RCC_D2CFGR_D2PPRE2_Pos                 (8U)

+#define RCC_D2CFGR_D2PPRE2_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000700 */

+#define RCC_D2CFGR_D2PPRE2                     RCC_D2CFGR_D2PPRE2_Msk          /*!< D2PPRE2[2:0] bits (APB2 prescaler) */

+#define RCC_D2CFGR_D2PPRE2_0                   (0x1UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000100 */

+#define RCC_D2CFGR_D2PPRE2_1                   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */

+#define RCC_D2CFGR_D2PPRE2_2                   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */

+

+#define RCC_D2CFGR_D2PPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */

+#define RCC_D2CFGR_D2PPRE2_DIV2_Pos            (10U)

+#define RCC_D2CFGR_D2PPRE2_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */

+#define RCC_D2CFGR_D2PPRE2_DIV2                RCC_D2CFGR_D2PPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */

+#define RCC_D2CFGR_D2PPRE2_DIV4_Pos            (8U)

+#define RCC_D2CFGR_D2PPRE2_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE2_DIV4_Pos) /*!< 0x00000500 */

+#define RCC_D2CFGR_D2PPRE2_DIV4                RCC_D2CFGR_D2PPRE2_DIV4_Msk     /*!< APB2 clock divided by 4 */

+#define RCC_D2CFGR_D2PPRE2_DIV8_Pos            (9U)

+#define RCC_D2CFGR_D2PPRE2_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE2_DIV8_Pos) /*!< 0x00000600 */

+#define RCC_D2CFGR_D2PPRE2_DIV8                RCC_D2CFGR_D2PPRE2_DIV8_Msk     /*!< APB2 clock divided by 8 */

+#define RCC_D2CFGR_D2PPRE2_DIV16_Pos           (8U)

+#define RCC_D2CFGR_D2PPRE2_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE2_DIV16_Pos) /*!< 0x00000700 */

+#define RCC_D2CFGR_D2PPRE2_DIV16               RCC_D2CFGR_D2PPRE2_DIV16_Msk    /*!< APB2 clock divided by 16 */

+

+/********************  Bit definition for RCC_D3CFGR register  ******************/

+/*!< D3PPRE configuration */

+#define RCC_D3CFGR_D3PPRE_Pos                  (4U)

+#define RCC_D3CFGR_D3PPRE_Msk                  (0x7UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000070 */

+#define RCC_D3CFGR_D3PPRE                      RCC_D3CFGR_D3PPRE_Msk           /*!< D3PPRE1[2:0] bits (APB4 prescaler) */

+#define RCC_D3CFGR_D3PPRE_0                    (0x1UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000010 */

+#define RCC_D3CFGR_D3PPRE_1                    (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */

+#define RCC_D3CFGR_D3PPRE_2                    (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */

+

+#define RCC_D3CFGR_D3PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */

+#define RCC_D3CFGR_D3PPRE_DIV2_Pos             (6U)

+#define RCC_D3CFGR_D3PPRE_DIV2_Msk             (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_D3CFGR_D3PPRE_DIV2                 RCC_D3CFGR_D3PPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */

+#define RCC_D3CFGR_D3PPRE_DIV4_Pos             (4U)

+#define RCC_D3CFGR_D3PPRE_DIV4_Msk             (0x5UL << RCC_D3CFGR_D3PPRE_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_D3CFGR_D3PPRE_DIV4                 RCC_D3CFGR_D3PPRE_DIV4_Msk      /*!< APB4 clock divided by 4 */

+#define RCC_D3CFGR_D3PPRE_DIV8_Pos             (5U)

+#define RCC_D3CFGR_D3PPRE_DIV8_Msk             (0x3UL << RCC_D3CFGR_D3PPRE_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_D3CFGR_D3PPRE_DIV8                 RCC_D3CFGR_D3PPRE_DIV8_Msk      /*!< APB4 clock divided by 8 */

+#define RCC_D3CFGR_D3PPRE_DIV16_Pos            (4U)

+#define RCC_D3CFGR_D3PPRE_DIV16_Msk            (0x7UL << RCC_D3CFGR_D3PPRE_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_D3CFGR_D3PPRE_DIV16                RCC_D3CFGR_D3PPRE_DIV16_Msk     /*!< APB4 clock divided by 16 */

+

+/********************  Bit definition for RCC_PLLCKSELR register  *************/

+

+#define RCC_PLLCKSELR_PLLSRC_Pos               (0U)

+#define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */

+#define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk

+

+#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)

+#define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */

+#define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_HSE_Pos           (1U)

+#define RCC_PLLCKSELR_PLLSRC_HSE_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */

+#define RCC_PLLCKSELR_PLLSRC_HSE               RCC_PLLCKSELR_PLLSRC_HSE_Msk    /*!< HSE source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_NONE_Pos          (0U)

+#define RCC_PLLCKSELR_PLLSRC_NONE_Msk          (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */

+#define RCC_PLLCKSELR_PLLSRC_NONE              RCC_PLLCKSELR_PLLSRC_NONE_Msk   /*!< No source clock selected  */

+

+#define RCC_PLLCKSELR_DIVM1_Pos                (4U)

+#define RCC_PLLCKSELR_DIVM1_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */

+#define RCC_PLLCKSELR_DIVM1                    RCC_PLLCKSELR_DIVM1_Msk

+#define RCC_PLLCKSELR_DIVM1_0                  (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */

+#define RCC_PLLCKSELR_DIVM1_1                  (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */

+#define RCC_PLLCKSELR_DIVM1_2                  (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */

+#define RCC_PLLCKSELR_DIVM1_3                  (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */

+#define RCC_PLLCKSELR_DIVM1_4                  (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */

+#define RCC_PLLCKSELR_DIVM1_5                  (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */

+

+#define RCC_PLLCKSELR_DIVM2_Pos                (12U)

+#define RCC_PLLCKSELR_DIVM2_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */

+#define RCC_PLLCKSELR_DIVM2                    RCC_PLLCKSELR_DIVM2_Msk

+#define RCC_PLLCKSELR_DIVM2_0                  (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */

+#define RCC_PLLCKSELR_DIVM2_1                  (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */

+#define RCC_PLLCKSELR_DIVM2_2                  (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */

+#define RCC_PLLCKSELR_DIVM2_3                  (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */

+#define RCC_PLLCKSELR_DIVM2_4                  (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */

+#define RCC_PLLCKSELR_DIVM2_5                  (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */

+

+#define RCC_PLLCKSELR_DIVM3_Pos                (20U)

+#define RCC_PLLCKSELR_DIVM3_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */

+#define RCC_PLLCKSELR_DIVM3                    RCC_PLLCKSELR_DIVM3_Msk

+#define RCC_PLLCKSELR_DIVM3_0                  (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */

+#define RCC_PLLCKSELR_DIVM3_1                  (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */

+#define RCC_PLLCKSELR_DIVM3_2                  (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */

+#define RCC_PLLCKSELR_DIVM3_3                  (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */

+#define RCC_PLLCKSELR_DIVM3_4                  (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */

+#define RCC_PLLCKSELR_DIVM3_5                  (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */

+

+/********************  Bit definition for RCC_PLLCFGR register  ***************/

+

+#define RCC_PLLCFGR_PLL1FRACEN_Pos             (0U)

+#define RCC_PLLCFGR_PLL1FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */

+#define RCC_PLLCFGR_PLL1FRACEN                 RCC_PLLCFGR_PLL1FRACEN_Msk

+#define RCC_PLLCFGR_PLL1VCOSEL_Pos             (1U)

+#define RCC_PLLCFGR_PLL1VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */

+#define RCC_PLLCFGR_PLL1VCOSEL                 RCC_PLLCFGR_PLL1VCOSEL_Msk

+#define RCC_PLLCFGR_PLL1RGE_Pos                (2U)

+#define RCC_PLLCFGR_PLL1RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */

+#define RCC_PLLCFGR_PLL1RGE                    RCC_PLLCFGR_PLL1RGE_Msk

+#define RCC_PLLCFGR_PLL1RGE_0                  (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL1RGE_1                  (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */

+#define RCC_PLLCFGR_PLL1RGE_2                  (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */

+#define RCC_PLLCFGR_PLL1RGE_3                  (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */

+

+#define RCC_PLLCFGR_PLL2FRACEN_Pos             (4U)

+#define RCC_PLLCFGR_PLL2FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */

+#define RCC_PLLCFGR_PLL2FRACEN                 RCC_PLLCFGR_PLL2FRACEN_Msk

+#define RCC_PLLCFGR_PLL2VCOSEL_Pos             (5U)

+#define RCC_PLLCFGR_PLL2VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */

+#define RCC_PLLCFGR_PLL2VCOSEL                 RCC_PLLCFGR_PLL2VCOSEL_Msk

+#define RCC_PLLCFGR_PLL2RGE_Pos                (6U)

+#define RCC_PLLCFGR_PLL2RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */

+#define RCC_PLLCFGR_PLL2RGE                    RCC_PLLCFGR_PLL2RGE_Msk

+#define RCC_PLLCFGR_PLL2RGE_0                  (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL2RGE_1                  (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */

+#define RCC_PLLCFGR_PLL2RGE_2                  (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */

+#define RCC_PLLCFGR_PLL2RGE_3                  (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */

+

+#define RCC_PLLCFGR_PLL3FRACEN_Pos             (8U)

+#define RCC_PLLCFGR_PLL3FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */

+#define RCC_PLLCFGR_PLL3FRACEN                 RCC_PLLCFGR_PLL3FRACEN_Msk

+#define RCC_PLLCFGR_PLL3VCOSEL_Pos             (9U)

+#define RCC_PLLCFGR_PLL3VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */

+#define RCC_PLLCFGR_PLL3VCOSEL                 RCC_PLLCFGR_PLL3VCOSEL_Msk

+#define RCC_PLLCFGR_PLL3RGE_Pos                (10U)

+#define RCC_PLLCFGR_PLL3RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */

+#define RCC_PLLCFGR_PLL3RGE                    RCC_PLLCFGR_PLL3RGE_Msk

+#define RCC_PLLCFGR_PLL3RGE_0                  (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL3RGE_1                  (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */

+#define RCC_PLLCFGR_PLL3RGE_2                  (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */

+#define RCC_PLLCFGR_PLL3RGE_3                  (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */

+

+#define RCC_PLLCFGR_DIVP1EN_Pos                (16U)

+#define RCC_PLLCFGR_DIVP1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */

+#define RCC_PLLCFGR_DIVP1EN                    RCC_PLLCFGR_DIVP1EN_Msk

+#define RCC_PLLCFGR_DIVQ1EN_Pos                (17U)

+#define RCC_PLLCFGR_DIVQ1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */

+#define RCC_PLLCFGR_DIVQ1EN                    RCC_PLLCFGR_DIVQ1EN_Msk

+#define RCC_PLLCFGR_DIVR1EN_Pos                (18U)

+#define RCC_PLLCFGR_DIVR1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */

+#define RCC_PLLCFGR_DIVR1EN                    RCC_PLLCFGR_DIVR1EN_Msk

+

+#define RCC_PLLCFGR_DIVP2EN_Pos                (19U)

+#define RCC_PLLCFGR_DIVP2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */

+#define RCC_PLLCFGR_DIVP2EN                    RCC_PLLCFGR_DIVP2EN_Msk

+#define RCC_PLLCFGR_DIVQ2EN_Pos                (20U)

+#define RCC_PLLCFGR_DIVQ2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */

+#define RCC_PLLCFGR_DIVQ2EN                    RCC_PLLCFGR_DIVQ2EN_Msk

+#define RCC_PLLCFGR_DIVR2EN_Pos                (21U)

+#define RCC_PLLCFGR_DIVR2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */

+#define RCC_PLLCFGR_DIVR2EN                    RCC_PLLCFGR_DIVR2EN_Msk

+

+#define RCC_PLLCFGR_DIVP3EN_Pos                (22U)

+#define RCC_PLLCFGR_DIVP3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */

+#define RCC_PLLCFGR_DIVP3EN                    RCC_PLLCFGR_DIVP3EN_Msk

+#define RCC_PLLCFGR_DIVQ3EN_Pos                (23U)

+#define RCC_PLLCFGR_DIVQ3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */

+#define RCC_PLLCFGR_DIVQ3EN                    RCC_PLLCFGR_DIVQ3EN_Msk

+#define RCC_PLLCFGR_DIVR3EN_Pos                (24U)

+#define RCC_PLLCFGR_DIVR3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */

+#define RCC_PLLCFGR_DIVR3EN                    RCC_PLLCFGR_DIVR3EN_Msk

+

+

+/********************  Bit definition for RCC_PLL1DIVR register  ***************/

+#define RCC_PLL1DIVR_N1_Pos                    (0U)

+#define RCC_PLL1DIVR_N1_Msk                    (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */

+#define RCC_PLL1DIVR_N1                        RCC_PLL1DIVR_N1_Msk

+#define RCC_PLL1DIVR_P1_Pos                    (9U)

+#define RCC_PLL1DIVR_P1_Msk                    (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL1DIVR_P1                        RCC_PLL1DIVR_P1_Msk

+#define RCC_PLL1DIVR_Q1_Pos                    (16U)

+#define RCC_PLL1DIVR_Q1_Msk                    (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */

+#define RCC_PLL1DIVR_Q1                        RCC_PLL1DIVR_Q1_Msk

+#define RCC_PLL1DIVR_R1_Pos                    (24U)

+#define RCC_PLL1DIVR_R1_Msk                    (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */

+#define RCC_PLL1DIVR_R1                        RCC_PLL1DIVR_R1_Msk

+

+/********************  Bit definition for RCC_PLL1FRACR register  ***************/

+#define RCC_PLL1FRACR_FRACN1_Pos               (3U)

+#define RCC_PLL1FRACR_FRACN1_Msk               (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL1FRACR_FRACN1                   RCC_PLL1FRACR_FRACN1_Msk

+

+/********************  Bit definition for RCC_PLL2DIVR register  ***************/

+#define RCC_PLL2DIVR_N2_Pos                    (0U)

+#define RCC_PLL2DIVR_N2_Msk                    (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */

+#define RCC_PLL2DIVR_N2                        RCC_PLL2DIVR_N2_Msk

+#define RCC_PLL2DIVR_P2_Pos                    (9U)

+#define RCC_PLL2DIVR_P2_Msk                    (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL2DIVR_P2                        RCC_PLL2DIVR_P2_Msk

+#define RCC_PLL2DIVR_Q2_Pos                    (16U)

+#define RCC_PLL2DIVR_Q2_Msk                    (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */

+#define RCC_PLL2DIVR_Q2                        RCC_PLL2DIVR_Q2_Msk

+#define RCC_PLL2DIVR_R2_Pos                    (24U)

+#define RCC_PLL2DIVR_R2_Msk                    (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */

+#define RCC_PLL2DIVR_R2                        RCC_PLL2DIVR_R2_Msk

+

+/********************  Bit definition for RCC_PLL2FRACR register  ***************/

+#define RCC_PLL2FRACR_FRACN2_Pos               (3U)

+#define RCC_PLL2FRACR_FRACN2_Msk               (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL2FRACR_FRACN2                   RCC_PLL2FRACR_FRACN2_Msk

+

+/********************  Bit definition for RCC_PLL3DIVR register  ***************/

+#define RCC_PLL3DIVR_N3_Pos                    (0U)

+#define RCC_PLL3DIVR_N3_Msk                    (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */

+#define RCC_PLL3DIVR_N3                        RCC_PLL3DIVR_N3_Msk

+#define RCC_PLL3DIVR_P3_Pos                    (9U)

+#define RCC_PLL3DIVR_P3_Msk                    (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL3DIVR_P3                        RCC_PLL3DIVR_P3_Msk

+#define RCC_PLL3DIVR_Q3_Pos                    (16U)

+#define RCC_PLL3DIVR_Q3_Msk                    (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */

+#define RCC_PLL3DIVR_Q3                        RCC_PLL3DIVR_Q3_Msk

+#define RCC_PLL3DIVR_R3_Pos                    (24U)

+#define RCC_PLL3DIVR_R3_Msk                    (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */

+#define RCC_PLL3DIVR_R3                        RCC_PLL3DIVR_R3_Msk

+

+/********************  Bit definition for RCC_PLL3FRACR register  ***************/

+#define RCC_PLL3FRACR_FRACN3_Pos               (3U)

+#define RCC_PLL3FRACR_FRACN3_Msk               (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL3FRACR_FRACN3                   RCC_PLL3FRACR_FRACN3_Msk

+

+/********************  Bit definition for RCC_D1CCIPR register  ***************/

+#define RCC_D1CCIPR_FMCSEL_Pos                 (0U)

+#define RCC_D1CCIPR_FMCSEL_Msk                 (0x3UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000003 */

+#define RCC_D1CCIPR_FMCSEL                     RCC_D1CCIPR_FMCSEL_Msk

+#define RCC_D1CCIPR_FMCSEL_0                   (0x1UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000001 */

+#define RCC_D1CCIPR_FMCSEL_1                   (0x2UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000002 */

+#define RCC_D1CCIPR_QSPISEL_Pos                (4U)

+#define RCC_D1CCIPR_QSPISEL_Msk                (0x3UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000030 */

+#define RCC_D1CCIPR_QSPISEL                    RCC_D1CCIPR_QSPISEL_Msk

+#define RCC_D1CCIPR_QSPISEL_0                  (0x1UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000010 */

+#define RCC_D1CCIPR_QSPISEL_1                  (0x2UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000020 */

+#define RCC_D1CCIPR_SDMMCSEL_Pos               (16U)

+#define RCC_D1CCIPR_SDMMCSEL_Msk               (0x1UL << RCC_D1CCIPR_SDMMCSEL_Pos) /*!< 0x00010000 */

+#define RCC_D1CCIPR_SDMMCSEL                   RCC_D1CCIPR_SDMMCSEL_Msk

+#define RCC_D1CCIPR_CKPERSEL_Pos               (28U)

+#define RCC_D1CCIPR_CKPERSEL_Msk               (0x3UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x30000000 */

+#define RCC_D1CCIPR_CKPERSEL                   RCC_D1CCIPR_CKPERSEL_Msk

+#define RCC_D1CCIPR_CKPERSEL_0                 (0x1UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x10000000 */

+#define RCC_D1CCIPR_CKPERSEL_1                 (0x2UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x20000000 */

+

+/********************  Bit definition for RCC_D2CCIP1R register  ***************/

+#define RCC_D2CCIP1R_SAI1SEL_Pos               (0U)

+#define RCC_D2CCIP1R_SAI1SEL_Msk               (0x7UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000007 */

+#define RCC_D2CCIP1R_SAI1SEL                   RCC_D2CCIP1R_SAI1SEL_Msk

+#define RCC_D2CCIP1R_SAI1SEL_0                 (0x1UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000001 */

+#define RCC_D2CCIP1R_SAI1SEL_1                 (0x2UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000002 */

+#define RCC_D2CCIP1R_SAI1SEL_2                 (0x4UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000004 */

+

+#define RCC_D2CCIP1R_SAI23SEL_Pos              (6U)

+#define RCC_D2CCIP1R_SAI23SEL_Msk              (0x7UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x000001C0 */

+#define RCC_D2CCIP1R_SAI23SEL                  RCC_D2CCIP1R_SAI23SEL_Msk

+#define RCC_D2CCIP1R_SAI23SEL_0                (0x1UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000040 */

+#define RCC_D2CCIP1R_SAI23SEL_1                (0x2UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000080 */

+#define RCC_D2CCIP1R_SAI23SEL_2                (0x4UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000100 */

+

+#define RCC_D2CCIP1R_SPI123SEL_Pos             (12U)

+#define RCC_D2CCIP1R_SPI123SEL_Msk             (0x7UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */

+#define RCC_D2CCIP1R_SPI123SEL                 RCC_D2CCIP1R_SPI123SEL_Msk

+#define RCC_D2CCIP1R_SPI123SEL_0               (0x1UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */

+#define RCC_D2CCIP1R_SPI123SEL_1               (0x2UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */

+#define RCC_D2CCIP1R_SPI123SEL_2               (0x4UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */

+

+#define RCC_D2CCIP1R_SPI45SEL_Pos              (16U)

+#define RCC_D2CCIP1R_SPI45SEL_Msk              (0x7UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00070000 */

+#define RCC_D2CCIP1R_SPI45SEL                  RCC_D2CCIP1R_SPI45SEL_Msk

+#define RCC_D2CCIP1R_SPI45SEL_0                (0x1UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00010000 */

+#define RCC_D2CCIP1R_SPI45SEL_1                (0x2UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00020000 */

+#define RCC_D2CCIP1R_SPI45SEL_2                (0x4UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00040000 */

+

+#define RCC_D2CCIP1R_SPDIFSEL_Pos              (20U)

+#define RCC_D2CCIP1R_SPDIFSEL_Msk              (0x3UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00300000 */

+#define RCC_D2CCIP1R_SPDIFSEL                  RCC_D2CCIP1R_SPDIFSEL_Msk

+#define RCC_D2CCIP1R_SPDIFSEL_0                (0x1UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00100000 */

+#define RCC_D2CCIP1R_SPDIFSEL_1                (0x2UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00200000 */

+

+#define RCC_D2CCIP1R_DFSDM1SEL_Pos             (24U)

+#define RCC_D2CCIP1R_DFSDM1SEL_Msk             (0x1UL << RCC_D2CCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */

+#define RCC_D2CCIP1R_DFSDM1SEL                 RCC_D2CCIP1R_DFSDM1SEL_Msk

+

+#define RCC_D2CCIP1R_FDCANSEL_Pos              (28U)

+#define RCC_D2CCIP1R_FDCANSEL_Msk              (0x3UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x30000000 */

+#define RCC_D2CCIP1R_FDCANSEL                  RCC_D2CCIP1R_FDCANSEL_Msk

+#define RCC_D2CCIP1R_FDCANSEL_0                (0x1UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x10000000 */

+#define RCC_D2CCIP1R_FDCANSEL_1                (0x2UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x20000000 */

+

+#define RCC_D2CCIP1R_SWPSEL_Pos                (31U)

+#define RCC_D2CCIP1R_SWPSEL_Msk                (0x1UL << RCC_D2CCIP1R_SWPSEL_Pos) /*!< 0x80000000 */

+#define RCC_D2CCIP1R_SWPSEL                    RCC_D2CCIP1R_SWPSEL_Msk

+

+/********************  Bit definition for RCC_D2CCIP2R register  ***************/

+#define RCC_D2CCIP2R_USART16SEL_Pos            (3U)

+#define RCC_D2CCIP2R_USART16SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000038 */

+#define RCC_D2CCIP2R_USART16SEL                RCC_D2CCIP2R_USART16SEL_Msk

+#define RCC_D2CCIP2R_USART16SEL_0              (0x1UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000008 */

+#define RCC_D2CCIP2R_USART16SEL_1              (0x2UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000010 */

+#define RCC_D2CCIP2R_USART16SEL_2              (0x4UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000020 */

+

+#define RCC_D2CCIP2R_USART28SEL_Pos            (0U)

+#define RCC_D2CCIP2R_USART28SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000007 */

+#define RCC_D2CCIP2R_USART28SEL                RCC_D2CCIP2R_USART28SEL_Msk

+#define RCC_D2CCIP2R_USART28SEL_0              (0x1UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000001 */

+#define RCC_D2CCIP2R_USART28SEL_1              (0x2UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000002 */

+#define RCC_D2CCIP2R_USART28SEL_2              (0x4UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000004 */

+

+#define RCC_D2CCIP2R_RNGSEL_Pos                (8U)

+#define RCC_D2CCIP2R_RNGSEL_Msk                (0x3UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000300 */

+#define RCC_D2CCIP2R_RNGSEL                    RCC_D2CCIP2R_RNGSEL_Msk

+#define RCC_D2CCIP2R_RNGSEL_0                  (0x1UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000100 */

+#define RCC_D2CCIP2R_RNGSEL_1                  (0x2UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000200 */

+

+#define RCC_D2CCIP2R_I2C123SEL_Pos             (12U)

+#define RCC_D2CCIP2R_I2C123SEL_Msk             (0x3UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00003000 */

+#define RCC_D2CCIP2R_I2C123SEL                 RCC_D2CCIP2R_I2C123SEL_Msk

+#define RCC_D2CCIP2R_I2C123SEL_0               (0x1UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00001000 */

+#define RCC_D2CCIP2R_I2C123SEL_1               (0x2UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00002000 */

+

+#define RCC_D2CCIP2R_USBSEL_Pos                (20U)

+#define RCC_D2CCIP2R_USBSEL_Msk                (0x3UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00300000 */

+#define RCC_D2CCIP2R_USBSEL                    RCC_D2CCIP2R_USBSEL_Msk

+#define RCC_D2CCIP2R_USBSEL_0                  (0x1UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00100000 */

+#define RCC_D2CCIP2R_USBSEL_1                  (0x2UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00200000 */

+

+#define RCC_D2CCIP2R_CECSEL_Pos                (22U)

+#define RCC_D2CCIP2R_CECSEL_Msk                (0x3UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00C00000 */

+#define RCC_D2CCIP2R_CECSEL                    RCC_D2CCIP2R_CECSEL_Msk

+#define RCC_D2CCIP2R_CECSEL_0                  (0x1UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00400000 */

+#define RCC_D2CCIP2R_CECSEL_1                  (0x2UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00800000 */

+

+#define RCC_D2CCIP2R_LPTIM1SEL_Pos             (28U)

+#define RCC_D2CCIP2R_LPTIM1SEL_Msk             (0x7UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x70000000 */

+#define RCC_D2CCIP2R_LPTIM1SEL                 RCC_D2CCIP2R_LPTIM1SEL_Msk

+#define RCC_D2CCIP2R_LPTIM1SEL_0               (0x1UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x10000000 */

+#define RCC_D2CCIP2R_LPTIM1SEL_1               (0x2UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x20000000 */

+#define RCC_D2CCIP2R_LPTIM1SEL_2               (0x4UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition for RCC_D3CCIPR register  ***************/

+#define RCC_D3CCIPR_LPUART1SEL_Pos             (0U)

+#define RCC_D3CCIPR_LPUART1SEL_Msk             (0x7UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000007 */

+#define RCC_D3CCIPR_LPUART1SEL                 RCC_D3CCIPR_LPUART1SEL_Msk

+#define RCC_D3CCIPR_LPUART1SEL_0               (0x1UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000001 */

+#define RCC_D3CCIPR_LPUART1SEL_1               (0x2UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000002 */

+#define RCC_D3CCIPR_LPUART1SEL_2               (0x4UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000004 */

+

+#define RCC_D3CCIPR_I2C4SEL_Pos                (8U)

+#define RCC_D3CCIPR_I2C4SEL_Msk                (0x3UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000300 */

+#define RCC_D3CCIPR_I2C4SEL                    RCC_D3CCIPR_I2C4SEL_Msk

+#define RCC_D3CCIPR_I2C4SEL_0                  (0x1UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000100 */

+#define RCC_D3CCIPR_I2C4SEL_1                  (0x2UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000200 */

+

+#define RCC_D3CCIPR_LPTIM2SEL_Pos              (10U)

+#define RCC_D3CCIPR_LPTIM2SEL_Msk              (0x7UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001C00 */

+#define RCC_D3CCIPR_LPTIM2SEL                  RCC_D3CCIPR_LPTIM2SEL_Msk

+#define RCC_D3CCIPR_LPTIM2SEL_0                (0x1UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000400 */

+#define RCC_D3CCIPR_LPTIM2SEL_1                (0x2UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000800 */

+#define RCC_D3CCIPR_LPTIM2SEL_2                (0x4UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001000 */

+

+#define RCC_D3CCIPR_LPTIM345SEL_Pos            (13U)

+#define RCC_D3CCIPR_LPTIM345SEL_Msk            (0x7UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x0000E000 */

+#define RCC_D3CCIPR_LPTIM345SEL                RCC_D3CCIPR_LPTIM345SEL_Msk

+#define RCC_D3CCIPR_LPTIM345SEL_0              (0x1UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00002000 */

+#define RCC_D3CCIPR_LPTIM345SEL_1              (0x2UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00004000 */

+#define RCC_D3CCIPR_LPTIM345SEL_2              (0x4UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00008000 */

+

+#define RCC_D3CCIPR_SAI4ASEL_Pos               (21U)

+#define RCC_D3CCIPR_SAI4ASEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00E00000 */

+#define RCC_D3CCIPR_SAI4ASEL                   RCC_D3CCIPR_SAI4ASEL_Msk

+#define RCC_D3CCIPR_SAI4ASEL_0                 (0x1UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00200000 */

+#define RCC_D3CCIPR_SAI4ASEL_1                 (0x2UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00400000 */

+#define RCC_D3CCIPR_SAI4ASEL_2                 (0x4UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00800000 */

+

+#define RCC_D3CCIPR_SAI4BSEL_Pos               (24U)

+#define RCC_D3CCIPR_SAI4BSEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x07000000 */

+#define RCC_D3CCIPR_SAI4BSEL                   RCC_D3CCIPR_SAI4BSEL_Msk

+#define RCC_D3CCIPR_SAI4BSEL_0                 (0x1UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x01000000 */

+#define RCC_D3CCIPR_SAI4BSEL_1                 (0x2UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x02000000 */

+#define RCC_D3CCIPR_SAI4BSEL_2                 (0x4UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x04000000 */

+

+#define RCC_D3CCIPR_ADCSEL_Pos                 (16U)

+#define RCC_D3CCIPR_ADCSEL_Msk                 (0x3UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00030000 */

+#define RCC_D3CCIPR_ADCSEL                     RCC_D3CCIPR_ADCSEL_Msk

+#define RCC_D3CCIPR_ADCSEL_0                   (0x1UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00010000 */

+#define RCC_D3CCIPR_ADCSEL_1                   (0x2UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00020000 */

+

+#define RCC_D3CCIPR_SPI6SEL_Pos                (28U)

+#define RCC_D3CCIPR_SPI6SEL_Msk                (0x7UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x70000000 */

+#define RCC_D3CCIPR_SPI6SEL                    RCC_D3CCIPR_SPI6SEL_Msk

+#define RCC_D3CCIPR_SPI6SEL_0                  (0x1UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x10000000 */

+#define RCC_D3CCIPR_SPI6SEL_1                  (0x2UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x20000000 */

+#define RCC_D3CCIPR_SPI6SEL_2                  (0x4UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x40000000 */

+/********************  Bit definition for RCC_CIER register  ******************/

+#define RCC_CIER_LSIRDYIE_Pos                  (0U)

+#define RCC_CIER_LSIRDYIE_Msk                  (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */

+#define RCC_CIER_LSIRDYIE                      RCC_CIER_LSIRDYIE_Msk

+#define RCC_CIER_LSERDYIE_Pos                  (1U)

+#define RCC_CIER_LSERDYIE_Msk                  (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */

+#define RCC_CIER_LSERDYIE                      RCC_CIER_LSERDYIE_Msk

+#define RCC_CIER_HSIRDYIE_Pos                  (2U)

+#define RCC_CIER_HSIRDYIE_Msk                  (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */

+#define RCC_CIER_HSIRDYIE                      RCC_CIER_HSIRDYIE_Msk

+#define RCC_CIER_HSERDYIE_Pos                  (3U)

+#define RCC_CIER_HSERDYIE_Msk                  (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */

+#define RCC_CIER_HSERDYIE                      RCC_CIER_HSERDYIE_Msk

+#define RCC_CIER_CSIRDYIE_Pos                  (4U)

+#define RCC_CIER_CSIRDYIE_Msk                  (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */

+#define RCC_CIER_CSIRDYIE                      RCC_CIER_CSIRDYIE_Msk

+#define RCC_CIER_HSI48RDYIE_Pos                (5U)

+#define RCC_CIER_HSI48RDYIE_Msk                (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */

+#define RCC_CIER_HSI48RDYIE                    RCC_CIER_HSI48RDYIE_Msk

+#define RCC_CIER_PLL1RDYIE_Pos                 (6U)

+#define RCC_CIER_PLL1RDYIE_Msk                 (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */

+#define RCC_CIER_PLL1RDYIE                     RCC_CIER_PLL1RDYIE_Msk

+#define RCC_CIER_PLL2RDYIE_Pos                 (7U)

+#define RCC_CIER_PLL2RDYIE_Msk                 (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */

+#define RCC_CIER_PLL2RDYIE                     RCC_CIER_PLL2RDYIE_Msk

+#define RCC_CIER_PLL3RDYIE_Pos                 (8U)

+#define RCC_CIER_PLL3RDYIE_Msk                 (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */

+#define RCC_CIER_PLL3RDYIE                     RCC_CIER_PLL3RDYIE_Msk

+#define RCC_CIER_LSECSSIE_Pos                  (9U)

+#define RCC_CIER_LSECSSIE_Msk                  (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */

+#define RCC_CIER_LSECSSIE                      RCC_CIER_LSECSSIE_Msk

+

+/********************  Bit definition for RCC_CIFR register  ******************/

+#define RCC_CIFR_LSIRDYF_Pos                   (0U)

+#define RCC_CIFR_LSIRDYF_Msk                   (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */

+#define RCC_CIFR_LSIRDYF                       RCC_CIFR_LSIRDYF_Msk

+#define RCC_CIFR_LSERDYF_Pos                   (1U)

+#define RCC_CIFR_LSERDYF_Msk                   (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */

+#define RCC_CIFR_LSERDYF                       RCC_CIFR_LSERDYF_Msk

+#define RCC_CIFR_HSIRDYF_Pos                   (2U)

+#define RCC_CIFR_HSIRDYF_Msk                   (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */

+#define RCC_CIFR_HSIRDYF                       RCC_CIFR_HSIRDYF_Msk

+#define RCC_CIFR_HSERDYF_Pos                   (3U)

+#define RCC_CIFR_HSERDYF_Msk                   (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */

+#define RCC_CIFR_HSERDYF                       RCC_CIFR_HSERDYF_Msk

+#define RCC_CIFR_CSIRDYF_Pos                   (4U)

+#define RCC_CIFR_CSIRDYF_Msk                   (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */

+#define RCC_CIFR_CSIRDYF                       RCC_CIFR_CSIRDYF_Msk

+#define RCC_CIFR_HSI48RDYF_Pos                 (5U)

+#define RCC_CIFR_HSI48RDYF_Msk                 (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */

+#define RCC_CIFR_HSI48RDYF                     RCC_CIFR_HSI48RDYF_Msk

+#define RCC_CIFR_PLLRDYF_Pos                   (6U)

+#define RCC_CIFR_PLLRDYF_Msk                   (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */

+#define RCC_CIFR_PLLRDYF                       RCC_CIFR_PLLRDYF_Msk

+#define RCC_CIFR_PLL2RDYF_Pos                  (7U)

+#define RCC_CIFR_PLL2RDYF_Msk                  (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */

+#define RCC_CIFR_PLL2RDYF                      RCC_CIFR_PLL2RDYF_Msk

+#define RCC_CIFR_PLL3RDYF_Pos                  (8U)

+#define RCC_CIFR_PLL3RDYF_Msk                  (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */

+#define RCC_CIFR_PLL3RDYF                      RCC_CIFR_PLL3RDYF_Msk

+#define RCC_CIFR_LSECSSF_Pos                   (9U)

+#define RCC_CIFR_LSECSSF_Msk                   (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */

+#define RCC_CIFR_LSECSSF                       RCC_CIFR_LSECSSF_Msk

+#define RCC_CIFR_HSECSSF_Pos                   (10U)

+#define RCC_CIFR_HSECSSF_Msk                   (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */

+#define RCC_CIFR_HSECSSF                       RCC_CIFR_HSECSSF_Msk

+

+/********************  Bit definition for RCC_CICR register  ******************/

+#define RCC_CICR_LSIRDYC_Pos                   (0U)

+#define RCC_CICR_LSIRDYC_Msk                   (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */

+#define RCC_CICR_LSIRDYC                       RCC_CICR_LSIRDYC_Msk

+#define RCC_CICR_LSERDYC_Pos                   (1U)

+#define RCC_CICR_LSERDYC_Msk                   (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */

+#define RCC_CICR_LSERDYC                       RCC_CICR_LSERDYC_Msk

+#define RCC_CICR_HSIRDYC_Pos                   (2U)

+#define RCC_CICR_HSIRDYC_Msk                   (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */

+#define RCC_CICR_HSIRDYC                       RCC_CICR_HSIRDYC_Msk

+#define RCC_CICR_HSERDYC_Pos                   (3U)

+#define RCC_CICR_HSERDYC_Msk                   (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */

+#define RCC_CICR_HSERDYC                       RCC_CICR_HSERDYC_Msk

+#define RCC_CICR_CSIRDYC_Pos                   (4U)

+#define RCC_CICR_CSIRDYC_Msk                   (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */

+#define RCC_CICR_CSIRDYC                       RCC_CICR_CSIRDYC_Msk

+#define RCC_CICR_HSI48RDYC_Pos                 (5U)

+#define RCC_CICR_HSI48RDYC_Msk                 (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */

+#define RCC_CICR_HSI48RDYC                     RCC_CICR_HSI48RDYC_Msk

+#define RCC_CICR_PLLRDYC_Pos                   (6U)

+#define RCC_CICR_PLLRDYC_Msk                   (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */

+#define RCC_CICR_PLLRDYC                       RCC_CICR_PLLRDYC_Msk

+#define RCC_CICR_PLL2RDYC_Pos                  (7U)

+#define RCC_CICR_PLL2RDYC_Msk                  (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */

+#define RCC_CICR_PLL2RDYC                      RCC_CICR_PLL2RDYC_Msk

+#define RCC_CICR_PLL3RDYC_Pos                  (8U)

+#define RCC_CICR_PLL3RDYC_Msk                  (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */

+#define RCC_CICR_PLL3RDYC                      RCC_CICR_PLL3RDYC_Msk

+#define RCC_CICR_LSECSSC_Pos                   (9U)

+#define RCC_CICR_LSECSSC_Msk                   (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */

+#define RCC_CICR_LSECSSC                       RCC_CICR_LSECSSC_Msk

+#define RCC_CICR_HSECSSC_Pos                   (10U)

+#define RCC_CICR_HSECSSC_Msk                   (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */

+#define RCC_CICR_HSECSSC                       RCC_CICR_HSECSSC_Msk

+

+/********************  Bit definition for RCC_BDCR register  ******************/

+#define RCC_BDCR_LSEON_Pos                     (0U)

+#define RCC_BDCR_LSEON_Msk                     (0x1UL << RCC_BDCR_LSEON_Pos)   /*!< 0x00000001 */

+#define RCC_BDCR_LSEON                         RCC_BDCR_LSEON_Msk

+#define RCC_BDCR_LSERDY_Pos                    (1U)

+#define RCC_BDCR_LSERDY_Msk                    (0x1UL << RCC_BDCR_LSERDY_Pos)  /*!< 0x00000002 */

+#define RCC_BDCR_LSERDY                        RCC_BDCR_LSERDY_Msk

+#define RCC_BDCR_LSEBYP_Pos                    (2U)

+#define RCC_BDCR_LSEBYP_Msk                    (0x1UL << RCC_BDCR_LSEBYP_Pos)  /*!< 0x00000004 */

+#define RCC_BDCR_LSEBYP                        RCC_BDCR_LSEBYP_Msk

+

+#define RCC_BDCR_LSEDRV_Pos                    (3U)

+#define RCC_BDCR_LSEDRV_Msk                    (0x3UL << RCC_BDCR_LSEDRV_Pos)  /*!< 0x00000018 */

+#define RCC_BDCR_LSEDRV                        RCC_BDCR_LSEDRV_Msk

+#define RCC_BDCR_LSEDRV_0                      (0x1UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000008 */

+#define RCC_BDCR_LSEDRV_1                      (0x2UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000010 */

+

+#define RCC_BDCR_LSECSSON_Pos                  (5U)

+#define RCC_BDCR_LSECSSON_Msk                  (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */

+#define RCC_BDCR_LSECSSON                      RCC_BDCR_LSECSSON_Msk

+#define RCC_BDCR_LSECSSD_Pos                   (6U)

+#define RCC_BDCR_LSECSSD_Msk                   (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */

+#define RCC_BDCR_LSECSSD                       RCC_BDCR_LSECSSD_Msk

+

+#define RCC_BDCR_RTCSEL_Pos                    (8U)

+#define RCC_BDCR_RTCSEL_Msk                    (0x3UL << RCC_BDCR_RTCSEL_Pos)  /*!< 0x00000300 */

+#define RCC_BDCR_RTCSEL                        RCC_BDCR_RTCSEL_Msk

+#define RCC_BDCR_RTCSEL_0                      (0x1UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000100 */

+#define RCC_BDCR_RTCSEL_1                      (0x2UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000200 */

+

+#define RCC_BDCR_RTCEN_Pos                     (15U)

+#define RCC_BDCR_RTCEN_Msk                     (0x1UL << RCC_BDCR_RTCEN_Pos)   /*!< 0x00008000 */

+#define RCC_BDCR_RTCEN                         RCC_BDCR_RTCEN_Msk

+#define RCC_BDCR_BDRST_Pos                     (16U)

+#define RCC_BDCR_BDRST_Msk                     (0x1UL << RCC_BDCR_BDRST_Pos)   /*!< 0x00010000 */

+#define RCC_BDCR_BDRST                         RCC_BDCR_BDRST_Msk

+/********************  Bit definition for RCC_CSR register  *******************/

+#define RCC_CSR_LSION_Pos                      (0U)

+#define RCC_CSR_LSION_Msk                      (0x1UL << RCC_CSR_LSION_Pos)    /*!< 0x00000001 */

+#define RCC_CSR_LSION                          RCC_CSR_LSION_Msk

+#define RCC_CSR_LSIRDY_Pos                     (1U)

+#define RCC_CSR_LSIRDY_Msk                     (0x1UL << RCC_CSR_LSIRDY_Pos)   /*!< 0x00000002 */

+#define RCC_CSR_LSIRDY                         RCC_CSR_LSIRDY_Msk

+

+

+/********************  Bit definition for RCC_AHB3ENR register  **************/

+#define RCC_AHB3ENR_MDMAEN_Pos                 (0U)

+#define RCC_AHB3ENR_MDMAEN_Msk                 (0x1UL << RCC_AHB3ENR_MDMAEN_Pos)       /*!< 0x00000001 */

+#define RCC_AHB3ENR_MDMAEN                     RCC_AHB3ENR_MDMAEN_Msk

+#define RCC_AHB3ENR_DMA2DEN_Pos                (4U)

+#define RCC_AHB3ENR_DMA2DEN_Msk                (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos)      /*!< 0x00000010 */

+#define RCC_AHB3ENR_DMA2DEN                    RCC_AHB3ENR_DMA2DEN_Msk

+#define RCC_AHB3ENR_JPGDECEN_Pos               (5U)

+#define RCC_AHB3ENR_JPGDECEN_Msk               (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos)     /*!< 0x00000020 */

+#define RCC_AHB3ENR_JPGDECEN                   RCC_AHB3ENR_JPGDECEN_Msk

+#define RCC_AHB3ENR_FMCEN_Pos                  (12U)

+#define RCC_AHB3ENR_FMCEN_Msk                  (0x1UL << RCC_AHB3ENR_FMCEN_Pos)        /*!< 0x00001000 */

+#define RCC_AHB3ENR_FMCEN                      RCC_AHB3ENR_FMCEN_Msk

+#define RCC_AHB3ENR_QSPIEN_Pos                 (14U)

+#define RCC_AHB3ENR_QSPIEN_Msk                 (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)       /*!< 0x00004000 */

+#define RCC_AHB3ENR_QSPIEN                     RCC_AHB3ENR_QSPIEN_Msk

+#define RCC_AHB3ENR_SDMMC1EN_Pos               (16U)

+#define RCC_AHB3ENR_SDMMC1EN_Msk               (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos)     /*!< 0x00010000 */

+#define RCC_AHB3ENR_SDMMC1EN                   RCC_AHB3ENR_SDMMC1EN_Msk

+#define RCC_AHB3ENR_FLASHEN_Pos                (8U)

+#define RCC_AHB3ENR_FLASHEN_Msk                (0x1UL << RCC_AHB3ENR_FLASHEN_Pos)      /*!< 0x00000100 */

+#define RCC_AHB3ENR_FLASHEN                    RCC_AHB3ENR_FLASHEN_Msk

+#define RCC_AHB3ENR_DTCM1EN_Pos                (28U)

+#define RCC_AHB3ENR_DTCM1EN_Msk                (0x1UL << RCC_AHB3ENR_DTCM1EN_Pos)      /*!< 0x10000000 */

+#define RCC_AHB3ENR_DTCM1EN                    RCC_AHB3ENR_DTCM1EN_Msk

+#define RCC_AHB3ENR_DTCM2EN_Pos                (29U)

+#define RCC_AHB3ENR_DTCM2EN_Msk                (0x1UL << RCC_AHB3ENR_DTCM2EN_Pos)      /*!< 0x20000000 */

+#define RCC_AHB3ENR_DTCM2EN                    RCC_AHB3ENR_DTCM2EN_Msk

+#define RCC_AHB3ENR_ITCMEN_Pos                 (30U)

+#define RCC_AHB3ENR_ITCMEN_Msk                 (0x1UL << RCC_AHB3ENR_ITCMEN_Pos)       /*!< 0x40000000 */

+#define RCC_AHB3ENR_ITCMEN                     RCC_AHB3ENR_ITCMEN_Msk

+#define RCC_AHB3ENR_AXISRAMEN_Pos              (31U)

+#define RCC_AHB3ENR_AXISRAMEN_Msk              (0x1UL << RCC_AHB3ENR_AXISRAMEN_Pos)    /*!< 0x80000000 */

+#define RCC_AHB3ENR_AXISRAMEN                  RCC_AHB3ENR_AXISRAMEN_Msk

+

+/* Legacy define */

+#define RCC_AHB3ENR_D1SRAM1EN_Pos              RCC_AHB3ENR_AXISRAMEN_Pos

+#define RCC_AHB3ENR_D1SRAM1EN_Msk              RCC_AHB3ENR_AXISRAMEN_Msk

+#define RCC_AHB3ENR_D1SRAM1EN                  RCC_AHB3ENR_AXISRAMEN

+

+/********************  Bit definition for RCC_AHB1ENR register  ***************/

+#define RCC_AHB1ENR_DMA1EN_Pos                 (0U)

+#define RCC_AHB1ENR_DMA1EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)          /*!< 0x00000001 */

+#define RCC_AHB1ENR_DMA1EN                     RCC_AHB1ENR_DMA1EN_Msk

+#define RCC_AHB1ENR_DMA2EN_Pos                 (1U)

+#define RCC_AHB1ENR_DMA2EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)          /*!< 0x00000002 */

+#define RCC_AHB1ENR_DMA2EN                     RCC_AHB1ENR_DMA2EN_Msk

+#define RCC_AHB1ENR_ADC12EN_Pos                (5U)

+#define RCC_AHB1ENR_ADC12EN_Msk                (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)         /*!< 0x00000020 */

+#define RCC_AHB1ENR_ADC12EN                    RCC_AHB1ENR_ADC12EN_Msk

+#define RCC_AHB1ENR_ARTEN_Pos                  (14U)

+#define RCC_AHB1ENR_ARTEN_Msk                  (0x1UL << RCC_AHB1ENR_ARTEN_Pos)           /*!< 0x00004000 */

+#define RCC_AHB1ENR_ARTEN                      RCC_AHB1ENR_ARTEN_Msk

+#define RCC_AHB1ENR_ETH1MACEN_Pos              (15U)

+#define RCC_AHB1ENR_ETH1MACEN_Msk              (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos)       /*!< 0x00008000 */

+#define RCC_AHB1ENR_ETH1MACEN                  RCC_AHB1ENR_ETH1MACEN_Msk

+#define RCC_AHB1ENR_ETH1TXEN_Pos               (16U)

+#define RCC_AHB1ENR_ETH1TXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos)        /*!< 0x00010000 */

+#define RCC_AHB1ENR_ETH1TXEN                   RCC_AHB1ENR_ETH1TXEN_Msk

+#define RCC_AHB1ENR_ETH1RXEN_Pos               (17U)

+#define RCC_AHB1ENR_ETH1RXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos)        /*!< 0x00020000 */

+#define RCC_AHB1ENR_ETH1RXEN                   RCC_AHB1ENR_ETH1RXEN_Msk

+#define RCC_AHB1ENR_USB1OTGHSEN_Pos            (25U)

+#define RCC_AHB1ENR_USB1OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos)     /*!< 0x02000000 */

+#define RCC_AHB1ENR_USB1OTGHSEN                RCC_AHB1ENR_USB1OTGHSEN_Msk

+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos        (26U)

+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */

+#define RCC_AHB1ENR_USB1OTGHSULPIEN            RCC_AHB1ENR_USB1OTGHSULPIEN_Msk

+#define RCC_AHB1ENR_USB2OTGFSEN_Pos            (27U)

+#define RCC_AHB1ENR_USB2OTGFSEN_Msk            (0x1UL << RCC_AHB1ENR_USB2OTGFSEN_Pos)     /*!< 0x08000000 */

+#define RCC_AHB1ENR_USB2OTGFSEN                RCC_AHB1ENR_USB2OTGFSEN_Msk

+#define RCC_AHB1ENR_USB2OTGFSULPIEN_Pos        (28U)

+#define RCC_AHB1ENR_USB2OTGFSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB2OTGFSULPIEN_Pos) /*!< 0x10000000 */

+#define RCC_AHB1ENR_USB2OTGFSULPIEN            RCC_AHB1ENR_USB2OTGFSULPIEN_Msk

+

+/* Legacy define */

+#define RCC_AHB1ENR_USB2OTGHSEN_Pos            RCC_AHB1ENR_USB2OTGFSEN_Pos

+#define RCC_AHB1ENR_USB2OTGHSEN_Msk            RCC_AHB1ENR_USB2OTGFSEN_Msk

+#define RCC_AHB1ENR_USB2OTGHSEN                RCC_AHB1ENR_USB2OTGFSEN

+#define RCC_AHB1ENR_USB2OTGHSULPIEN_Pos        RCC_AHB1ENR_USB2OTGFSULPIEN_Pos

+#define RCC_AHB1ENR_USB2OTGHSULPIEN_Msk        RCC_AHB1ENR_USB2OTGFSULPIEN_Msk

+#define RCC_AHB1ENR_USB2OTGHSULPIEN            RCC_AHB1ENR_USB2OTGFSULPIEN

+

+

+/********************  Bit definition for RCC_AHB2ENR register  ***************/

+#define RCC_AHB2ENR_DCMIEN_Pos                 (0U)

+#define RCC_AHB2ENR_DCMIEN_Msk                 (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)          /*!< 0x00000001 */

+#define RCC_AHB2ENR_DCMIEN                     RCC_AHB2ENR_DCMIEN_Msk

+#define RCC_AHB2ENR_RNGEN_Pos                  (6U)

+#define RCC_AHB2ENR_RNGEN_Msk                  (0x1UL << RCC_AHB2ENR_RNGEN_Pos)           /*!< 0x00000040 */

+#define RCC_AHB2ENR_RNGEN                      RCC_AHB2ENR_RNGEN_Msk

+#define RCC_AHB2ENR_SDMMC2EN_Pos               (9U)

+#define RCC_AHB2ENR_SDMMC2EN_Msk               (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)        /*!< 0x00000200 */

+#define RCC_AHB2ENR_SDMMC2EN                   RCC_AHB2ENR_SDMMC2EN_Msk

+#define RCC_AHB2ENR_SRAM1EN_Pos                (29U)

+#define RCC_AHB2ENR_SRAM1EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos)       /*!< 0x20000000 */

+#define RCC_AHB2ENR_SRAM1EN                    RCC_AHB2ENR_SRAM1EN_Msk

+#define RCC_AHB2ENR_SRAM2EN_Pos                (30U)

+#define RCC_AHB2ENR_SRAM2EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos)       /*!< 0x40000000 */

+#define RCC_AHB2ENR_SRAM2EN                    RCC_AHB2ENR_SRAM2EN_Msk

+#define RCC_AHB2ENR_SRAM3EN_Pos                (31U)

+#define RCC_AHB2ENR_SRAM3EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM3EN_Pos)       /*!< 0x80000000 */

+#define RCC_AHB2ENR_SRAM3EN                    RCC_AHB2ENR_SRAM3EN_Msk

+

+/* Legacy define */

+#define RCC_AHB2ENR_D2SRAM1EN_Pos              RCC_AHB2ENR_SRAM1EN_Pos

+#define RCC_AHB2ENR_D2SRAM1EN_Msk              RCC_AHB2ENR_SRAM1EN_Msk

+#define RCC_AHB2ENR_D2SRAM1EN                  RCC_AHB2ENR_SRAM1EN

+#define RCC_AHB2ENR_D2SRAM2EN_Pos              RCC_AHB2ENR_SRAM2EN_Pos

+#define RCC_AHB2ENR_D2SRAM2EN_Msk              RCC_AHB2ENR_SRAM2EN_Msk

+#define RCC_AHB2ENR_D2SRAM2EN                  RCC_AHB2ENR_SRAM2EN

+#define RCC_AHB2ENR_D2SRAM3EN_Pos              RCC_AHB2ENR_SRAM3EN_Pos

+#define RCC_AHB2ENR_D2SRAM3EN_Msk              RCC_AHB2ENR_SRAM3EN_Msk

+#define RCC_AHB2ENR_D2SRAM3EN                  RCC_AHB2ENR_SRAM3EN

+

+/********************  Bit definition for RCC_AHB4ENR register  ******************/

+#define RCC_AHB4ENR_GPIOAEN_Pos                (0U)

+#define RCC_AHB4ENR_GPIOAEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)         /*!< 0x00000001 */

+#define RCC_AHB4ENR_GPIOAEN                    RCC_AHB4ENR_GPIOAEN_Msk

+#define RCC_AHB4ENR_GPIOBEN_Pos                (1U)

+#define RCC_AHB4ENR_GPIOBEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)         /*!< 0x00000002 */

+#define RCC_AHB4ENR_GPIOBEN                    RCC_AHB4ENR_GPIOBEN_Msk

+#define RCC_AHB4ENR_GPIOCEN_Pos                (2U)

+#define RCC_AHB4ENR_GPIOCEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)         /*!< 0x00000004 */

+#define RCC_AHB4ENR_GPIOCEN                    RCC_AHB4ENR_GPIOCEN_Msk

+#define RCC_AHB4ENR_GPIODEN_Pos                (3U)

+#define RCC_AHB4ENR_GPIODEN_Msk                (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)         /*!< 0x00000008 */

+#define RCC_AHB4ENR_GPIODEN                    RCC_AHB4ENR_GPIODEN_Msk

+#define RCC_AHB4ENR_GPIOEEN_Pos                (4U)

+#define RCC_AHB4ENR_GPIOEEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)         /*!< 0x00000010 */

+#define RCC_AHB4ENR_GPIOEEN                    RCC_AHB4ENR_GPIOEEN_Msk

+#define RCC_AHB4ENR_GPIOFEN_Pos                (5U)

+#define RCC_AHB4ENR_GPIOFEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)         /*!< 0x00000020 */

+#define RCC_AHB4ENR_GPIOFEN                    RCC_AHB4ENR_GPIOFEN_Msk

+#define RCC_AHB4ENR_GPIOGEN_Pos                (6U)

+#define RCC_AHB4ENR_GPIOGEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)         /*!< 0x00000040 */

+#define RCC_AHB4ENR_GPIOGEN                    RCC_AHB4ENR_GPIOGEN_Msk

+#define RCC_AHB4ENR_GPIOHEN_Pos                (7U)

+#define RCC_AHB4ENR_GPIOHEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)         /*!< 0x00000080 */

+#define RCC_AHB4ENR_GPIOHEN                    RCC_AHB4ENR_GPIOHEN_Msk

+#define RCC_AHB4ENR_GPIOIEN_Pos                (8U)

+#define RCC_AHB4ENR_GPIOIEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos)         /*!< 0x00000100 */

+#define RCC_AHB4ENR_GPIOIEN                    RCC_AHB4ENR_GPIOIEN_Msk

+#define RCC_AHB4ENR_GPIOJEN_Pos                (9U)

+#define RCC_AHB4ENR_GPIOJEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos)         /*!< 0x00000200 */

+#define RCC_AHB4ENR_GPIOJEN                    RCC_AHB4ENR_GPIOJEN_Msk

+#define RCC_AHB4ENR_GPIOKEN_Pos                (10U)

+#define RCC_AHB4ENR_GPIOKEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos)         /*!< 0x00000400 */

+#define RCC_AHB4ENR_GPIOKEN                    RCC_AHB4ENR_GPIOKEN_Msk

+#define RCC_AHB4ENR_CRCEN_Pos                  (19U)

+#define RCC_AHB4ENR_CRCEN_Msk                  (0x1UL << RCC_AHB4ENR_CRCEN_Pos)           /*!< 0x00080000 */

+#define RCC_AHB4ENR_CRCEN                      RCC_AHB4ENR_CRCEN_Msk

+#define RCC_AHB4ENR_BDMAEN_Pos                 (21U)

+#define RCC_AHB4ENR_BDMAEN_Msk                 (0x1UL << RCC_AHB4ENR_BDMAEN_Pos)          /*!< 0x00200000 */

+#define RCC_AHB4ENR_BDMAEN                     RCC_AHB4ENR_BDMAEN_Msk

+#define RCC_AHB4ENR_ADC3EN_Pos                 (24U)

+#define RCC_AHB4ENR_ADC3EN_Msk                 (0x1UL << RCC_AHB4ENR_ADC3EN_Pos)          /*!< 0x01000000 */

+#define RCC_AHB4ENR_ADC3EN                     RCC_AHB4ENR_ADC3EN_Msk

+#define RCC_AHB4ENR_HSEMEN_Pos                 (25U)

+#define RCC_AHB4ENR_HSEMEN_Msk                 (0x1UL << RCC_AHB4ENR_HSEMEN_Pos)          /*!< 0x02000000 */

+#define RCC_AHB4ENR_HSEMEN                     RCC_AHB4ENR_HSEMEN_Msk

+#define RCC_AHB4ENR_BKPRAMEN_Pos               (28U)

+#define RCC_AHB4ENR_BKPRAMEN_Msk               (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)        /*!< 0x10000000 */

+#define RCC_AHB4ENR_BKPRAMEN                   RCC_AHB4ENR_BKPRAMEN_Msk

+

+/********************  Bit definition for RCC_APB3ENR register  ******************/

+#define RCC_APB3ENR_LTDCEN_Pos                 (3U)

+#define RCC_APB3ENR_LTDCEN_Msk                 (0x1UL << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */

+#define RCC_APB3ENR_LTDCEN                     RCC_APB3ENR_LTDCEN_Msk

+#define RCC_APB3ENR_WWDG1EN_Pos                (6U)

+#define RCC_APB3ENR_WWDG1EN_Msk                (0x1UL << RCC_APB3ENR_WWDG1EN_Pos) /*!< 0x00000040 */

+#define RCC_APB3ENR_WWDG1EN                    RCC_APB3ENR_WWDG1EN_Msk

+

+/********************  Bit definition for RCC_APB1LENR register  ******************/

+

+#define RCC_APB1LENR_TIM2EN_Pos                (0U)

+#define RCC_APB1LENR_TIM2EN_Msk                (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */

+#define RCC_APB1LENR_TIM2EN                    RCC_APB1LENR_TIM2EN_Msk

+#define RCC_APB1LENR_TIM3EN_Pos                (1U)

+#define RCC_APB1LENR_TIM3EN_Msk                (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */

+#define RCC_APB1LENR_TIM3EN                    RCC_APB1LENR_TIM3EN_Msk

+#define RCC_APB1LENR_TIM4EN_Pos                (2U)

+#define RCC_APB1LENR_TIM4EN_Msk                (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */

+#define RCC_APB1LENR_TIM4EN                    RCC_APB1LENR_TIM4EN_Msk

+#define RCC_APB1LENR_TIM5EN_Pos                (3U)

+#define RCC_APB1LENR_TIM5EN_Msk                (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */

+#define RCC_APB1LENR_TIM5EN                    RCC_APB1LENR_TIM5EN_Msk

+#define RCC_APB1LENR_TIM6EN_Pos                (4U)

+#define RCC_APB1LENR_TIM6EN_Msk                (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */

+#define RCC_APB1LENR_TIM6EN                    RCC_APB1LENR_TIM6EN_Msk

+#define RCC_APB1LENR_TIM7EN_Pos                (5U)

+#define RCC_APB1LENR_TIM7EN_Msk                (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */

+#define RCC_APB1LENR_TIM7EN                    RCC_APB1LENR_TIM7EN_Msk

+#define RCC_APB1LENR_TIM12EN_Pos               (6U)

+#define RCC_APB1LENR_TIM12EN_Msk               (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */

+#define RCC_APB1LENR_TIM12EN                   RCC_APB1LENR_TIM12EN_Msk

+#define RCC_APB1LENR_TIM13EN_Pos               (7U)

+#define RCC_APB1LENR_TIM13EN_Msk               (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */

+#define RCC_APB1LENR_TIM13EN                   RCC_APB1LENR_TIM13EN_Msk

+#define RCC_APB1LENR_TIM14EN_Pos               (8U)

+#define RCC_APB1LENR_TIM14EN_Msk               (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */

+#define RCC_APB1LENR_TIM14EN                   RCC_APB1LENR_TIM14EN_Msk

+#define RCC_APB1LENR_LPTIM1EN_Pos              (9U)

+#define RCC_APB1LENR_LPTIM1EN_Msk              (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */

+#define RCC_APB1LENR_LPTIM1EN                  RCC_APB1LENR_LPTIM1EN_Msk

+

+#define RCC_APB1LENR_WWDG2EN_Pos               (11U)

+#define RCC_APB1LENR_WWDG2EN_Msk               (0x1UL << RCC_APB1LENR_WWDG2EN_Pos) /*!< 0x00000800 */

+#define RCC_APB1LENR_WWDG2EN                   RCC_APB1LENR_WWDG2EN_Msk

+

+#define RCC_APB1LENR_SPI2EN_Pos                (14U)

+#define RCC_APB1LENR_SPI2EN_Msk                (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */

+#define RCC_APB1LENR_SPI2EN                    RCC_APB1LENR_SPI2EN_Msk

+#define RCC_APB1LENR_SPI3EN_Pos                (15U)

+#define RCC_APB1LENR_SPI3EN_Msk                (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */

+#define RCC_APB1LENR_SPI3EN                    RCC_APB1LENR_SPI3EN_Msk

+#define RCC_APB1LENR_SPDIFRXEN_Pos             (16U)

+#define RCC_APB1LENR_SPDIFRXEN_Msk             (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */

+#define RCC_APB1LENR_SPDIFRXEN                 RCC_APB1LENR_SPDIFRXEN_Msk

+#define RCC_APB1LENR_USART2EN_Pos              (17U)

+#define RCC_APB1LENR_USART2EN_Msk              (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */

+#define RCC_APB1LENR_USART2EN                  RCC_APB1LENR_USART2EN_Msk

+#define RCC_APB1LENR_USART3EN_Pos              (18U)

+#define RCC_APB1LENR_USART3EN_Msk              (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */

+#define RCC_APB1LENR_USART3EN                  RCC_APB1LENR_USART3EN_Msk

+#define RCC_APB1LENR_UART4EN_Pos               (19U)

+#define RCC_APB1LENR_UART4EN_Msk               (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */

+#define RCC_APB1LENR_UART4EN                   RCC_APB1LENR_UART4EN_Msk

+#define RCC_APB1LENR_UART5EN_Pos               (20U)

+#define RCC_APB1LENR_UART5EN_Msk               (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */

+#define RCC_APB1LENR_UART5EN                   RCC_APB1LENR_UART5EN_Msk

+#define RCC_APB1LENR_I2C1EN_Pos                (21U)

+#define RCC_APB1LENR_I2C1EN_Msk                (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */

+#define RCC_APB1LENR_I2C1EN                    RCC_APB1LENR_I2C1EN_Msk

+#define RCC_APB1LENR_I2C2EN_Pos                (22U)

+#define RCC_APB1LENR_I2C2EN_Msk                (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */

+#define RCC_APB1LENR_I2C2EN                    RCC_APB1LENR_I2C2EN_Msk

+#define RCC_APB1LENR_I2C3EN_Pos                (23U)

+#define RCC_APB1LENR_I2C3EN_Msk                (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */

+#define RCC_APB1LENR_I2C3EN                    RCC_APB1LENR_I2C3EN_Msk

+#define RCC_APB1LENR_CECEN_Pos                 (27U)

+#define RCC_APB1LENR_CECEN_Msk                 (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */

+#define RCC_APB1LENR_CECEN                     RCC_APB1LENR_CECEN_Msk

+#define RCC_APB1LENR_DAC12EN_Pos               (29U)

+#define RCC_APB1LENR_DAC12EN_Msk               (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */

+#define RCC_APB1LENR_DAC12EN                   RCC_APB1LENR_DAC12EN_Msk

+#define RCC_APB1LENR_UART7EN_Pos               (30U)

+#define RCC_APB1LENR_UART7EN_Msk               (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */

+#define RCC_APB1LENR_UART7EN                   RCC_APB1LENR_UART7EN_Msk

+#define RCC_APB1LENR_UART8EN_Pos               (31U)

+#define RCC_APB1LENR_UART8EN_Msk               (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */

+#define RCC_APB1LENR_UART8EN                   RCC_APB1LENR_UART8EN_Msk

+

+/* Legacy define */

+#define RCC_APB1LENR_HDMICECEN_Pos             RCC_APB1LENR_CECEN_Pos

+#define RCC_APB1LENR_HDMICECEN_Msk             RCC_APB1LENR_CECEN_Msk

+#define RCC_APB1LENR_HDMICECEN                 RCC_APB1LENR_CECEN

+/********************  Bit definition for RCC_APB1HENR register  ******************/

+#define RCC_APB1HENR_CRSEN_Pos                 (1U)

+#define RCC_APB1HENR_CRSEN_Msk                 (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1HENR_CRSEN                     RCC_APB1HENR_CRSEN_Msk

+#define RCC_APB1HENR_SWPMIEN_Pos               (2U)

+#define RCC_APB1HENR_SWPMIEN_Msk               (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1HENR_SWPMIEN                   RCC_APB1HENR_SWPMIEN_Msk

+#define RCC_APB1HENR_OPAMPEN_Pos               (4U)

+#define RCC_APB1HENR_OPAMPEN_Msk               (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1HENR_OPAMPEN                   RCC_APB1HENR_OPAMPEN_Msk

+#define RCC_APB1HENR_MDIOSEN_Pos               (5U)

+#define RCC_APB1HENR_MDIOSEN_Msk               (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1HENR_MDIOSEN                   RCC_APB1HENR_MDIOSEN_Msk

+#define RCC_APB1HENR_FDCANEN_Pos               (8U)

+#define RCC_APB1HENR_FDCANEN_Msk               (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1HENR_FDCANEN                   RCC_APB1HENR_FDCANEN_Msk

+

+/********************  Bit definition for RCC_APB2ENR register  ******************/

+#define RCC_APB2ENR_TIM1EN_Pos                 (0U)

+#define RCC_APB2ENR_TIM1EN_Msk                 (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */

+#define RCC_APB2ENR_TIM1EN                     RCC_APB2ENR_TIM1EN_Msk

+#define RCC_APB2ENR_TIM8EN_Pos                 (1U)

+#define RCC_APB2ENR_TIM8EN_Msk                 (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */

+#define RCC_APB2ENR_TIM8EN                     RCC_APB2ENR_TIM8EN_Msk

+#define RCC_APB2ENR_USART1EN_Pos               (4U)

+#define RCC_APB2ENR_USART1EN_Msk               (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */

+#define RCC_APB2ENR_USART1EN                   RCC_APB2ENR_USART1EN_Msk

+#define RCC_APB2ENR_USART6EN_Pos               (5U)

+#define RCC_APB2ENR_USART6EN_Msk               (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */

+#define RCC_APB2ENR_USART6EN                   RCC_APB2ENR_USART6EN_Msk

+#define RCC_APB2ENR_SPI1EN_Pos                 (12U)

+#define RCC_APB2ENR_SPI1EN_Msk                 (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */

+#define RCC_APB2ENR_SPI1EN                     RCC_APB2ENR_SPI1EN_Msk

+#define RCC_APB2ENR_SPI4EN_Pos                 (13U)

+#define RCC_APB2ENR_SPI4EN_Msk                 (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */

+#define RCC_APB2ENR_SPI4EN                     RCC_APB2ENR_SPI4EN_Msk

+#define RCC_APB2ENR_TIM15EN_Pos                (16U)

+#define RCC_APB2ENR_TIM15EN_Msk                (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */

+#define RCC_APB2ENR_TIM15EN                    RCC_APB2ENR_TIM15EN_Msk

+#define RCC_APB2ENR_TIM16EN_Pos                (17U)

+#define RCC_APB2ENR_TIM16EN_Msk                (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */

+#define RCC_APB2ENR_TIM16EN                    RCC_APB2ENR_TIM16EN_Msk

+#define RCC_APB2ENR_TIM17EN_Pos                (18U)

+#define RCC_APB2ENR_TIM17EN_Msk                (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */

+#define RCC_APB2ENR_TIM17EN                    RCC_APB2ENR_TIM17EN_Msk

+#define RCC_APB2ENR_SPI5EN_Pos                 (20U)

+#define RCC_APB2ENR_SPI5EN_Msk                 (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */

+#define RCC_APB2ENR_SPI5EN                     RCC_APB2ENR_SPI5EN_Msk

+#define RCC_APB2ENR_SAI1EN_Pos                 (22U)

+#define RCC_APB2ENR_SAI1EN_Msk                 (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */

+#define RCC_APB2ENR_SAI1EN                     RCC_APB2ENR_SAI1EN_Msk

+#define RCC_APB2ENR_SAI2EN_Pos                 (23U)

+#define RCC_APB2ENR_SAI2EN_Msk                 (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */

+#define RCC_APB2ENR_SAI2EN                     RCC_APB2ENR_SAI2EN_Msk

+#define RCC_APB2ENR_SAI3EN_Pos                 (24U)

+#define RCC_APB2ENR_SAI3EN_Msk                 (0x1UL << RCC_APB2ENR_SAI3EN_Pos) /*!< 0x01000000 */

+#define RCC_APB2ENR_SAI3EN                     RCC_APB2ENR_SAI3EN_Msk

+#define RCC_APB2ENR_DFSDM1EN_Pos               (28U)

+#define RCC_APB2ENR_DFSDM1EN_Msk               (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x10000000 */

+#define RCC_APB2ENR_DFSDM1EN                   RCC_APB2ENR_DFSDM1EN_Msk

+#define RCC_APB2ENR_HRTIMEN_Pos                (29U)

+#define RCC_APB2ENR_HRTIMEN_Msk                (0x1UL << RCC_APB2ENR_HRTIMEN_Pos) /*!< 0x20000000 */

+#define RCC_APB2ENR_HRTIMEN                    RCC_APB2ENR_HRTIMEN_Msk

+

+/********************  Bit definition for RCC_APB4ENR register  ******************/

+#define RCC_APB4ENR_SYSCFGEN_Pos               (1U)

+#define RCC_APB4ENR_SYSCFGEN_Msk               (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */

+#define RCC_APB4ENR_SYSCFGEN                   RCC_APB4ENR_SYSCFGEN_Msk

+#define RCC_APB4ENR_LPUART1EN_Pos              (3U)

+#define RCC_APB4ENR_LPUART1EN_Msk              (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */

+#define RCC_APB4ENR_LPUART1EN                  RCC_APB4ENR_LPUART1EN_Msk

+#define RCC_APB4ENR_SPI6EN_Pos                 (5U)

+#define RCC_APB4ENR_SPI6EN_Msk                 (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */

+#define RCC_APB4ENR_SPI6EN                     RCC_APB4ENR_SPI6EN_Msk

+#define RCC_APB4ENR_I2C4EN_Pos                 (7U)

+#define RCC_APB4ENR_I2C4EN_Msk                 (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */

+#define RCC_APB4ENR_I2C4EN                     RCC_APB4ENR_I2C4EN_Msk

+#define RCC_APB4ENR_LPTIM2EN_Pos               (9U)

+#define RCC_APB4ENR_LPTIM2EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */

+#define RCC_APB4ENR_LPTIM2EN                   RCC_APB4ENR_LPTIM2EN_Msk

+#define RCC_APB4ENR_LPTIM3EN_Pos               (10U)

+#define RCC_APB4ENR_LPTIM3EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */

+#define RCC_APB4ENR_LPTIM3EN                   RCC_APB4ENR_LPTIM3EN_Msk

+#define RCC_APB4ENR_LPTIM4EN_Pos               (11U)

+#define RCC_APB4ENR_LPTIM4EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos) /*!< 0x00000800 */

+#define RCC_APB4ENR_LPTIM4EN                   RCC_APB4ENR_LPTIM4EN_Msk

+#define RCC_APB4ENR_LPTIM5EN_Pos               (12U)

+#define RCC_APB4ENR_LPTIM5EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos) /*!< 0x00001000 */

+#define RCC_APB4ENR_LPTIM5EN                   RCC_APB4ENR_LPTIM5EN_Msk

+#define RCC_APB4ENR_COMP12EN_Pos               (14U)

+#define RCC_APB4ENR_COMP12EN_Msk               (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */

+#define RCC_APB4ENR_COMP12EN                   RCC_APB4ENR_COMP12EN_Msk

+#define RCC_APB4ENR_VREFEN_Pos                 (15U)

+#define RCC_APB4ENR_VREFEN_Msk                 (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */

+#define RCC_APB4ENR_VREFEN                     RCC_APB4ENR_VREFEN_Msk

+#define RCC_APB4ENR_RTCAPBEN_Pos               (16U)

+#define RCC_APB4ENR_RTCAPBEN_Msk               (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */

+#define RCC_APB4ENR_RTCAPBEN                   RCC_APB4ENR_RTCAPBEN_Msk

+#define RCC_APB4ENR_SAI4EN_Pos                 (21U)

+#define RCC_APB4ENR_SAI4EN_Msk                 (0x1UL << RCC_APB4ENR_SAI4EN_Pos) /*!< 0x00200000 */

+#define RCC_APB4ENR_SAI4EN                     RCC_APB4ENR_SAI4EN_Msk

+

+

+/********************  Bit definition for RCC_AHB3RSTR register  ***************/

+#define RCC_AHB3RSTR_MDMARST_Pos               (0U)

+#define RCC_AHB3RSTR_MDMARST_Msk               (0x1UL << RCC_AHB3RSTR_MDMARST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB3RSTR_MDMARST                   RCC_AHB3RSTR_MDMARST_Msk

+#define RCC_AHB3RSTR_DMA2DRST_Pos              (4U)

+#define RCC_AHB3RSTR_DMA2DRST_Msk              (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos)     /*!< 0x00000010 */

+#define RCC_AHB3RSTR_DMA2DRST                  RCC_AHB3RSTR_DMA2DRST_Msk

+#define RCC_AHB3RSTR_JPGDECRST_Pos             (5U)

+#define RCC_AHB3RSTR_JPGDECRST_Msk             (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos)    /*!< 0x00000020 */

+#define RCC_AHB3RSTR_JPGDECRST                 RCC_AHB3RSTR_JPGDECRST_Msk

+#define RCC_AHB3RSTR_FMCRST_Pos                (12U)

+#define RCC_AHB3RSTR_FMCRST_Msk                (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)      /*!< 0x00001000 */

+#define RCC_AHB3RSTR_FMCRST                    RCC_AHB3RSTR_FMCRST_Msk

+#define RCC_AHB3RSTR_QSPIRST_Pos               (14U)

+#define RCC_AHB3RSTR_QSPIRST_Msk               (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)     /*!< 0x00004000 */

+#define RCC_AHB3RSTR_QSPIRST                   RCC_AHB3RSTR_QSPIRST_Msk

+#define RCC_AHB3RSTR_SDMMC1RST_Pos             (16U)

+#define RCC_AHB3RSTR_SDMMC1RST_Msk             (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos)   /*!< 0x00010000 */

+#define RCC_AHB3RSTR_SDMMC1RST                 RCC_AHB3RSTR_SDMMC1RST_Msk

+

+

+/********************  Bit definition for RCC_AHB1RSTR register  ***************/

+#define RCC_AHB1RSTR_DMA1RST_Pos               (0U)

+#define RCC_AHB1RSTR_DMA1RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB1RSTR_DMA1RST                   RCC_AHB1RSTR_DMA1RST_Msk

+#define RCC_AHB1RSTR_DMA2RST_Pos               (1U)

+#define RCC_AHB1RSTR_DMA2RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)      /*!< 0x00000002 */

+#define RCC_AHB1RSTR_DMA2RST                   RCC_AHB1RSTR_DMA2RST_Msk

+#define RCC_AHB1RSTR_ADC12RST_Pos              (5U)

+#define RCC_AHB1RSTR_ADC12RST_Msk              (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)     /*!< 0x00000020 */

+#define RCC_AHB1RSTR_ADC12RST                  RCC_AHB1RSTR_ADC12RST_Msk

+#define RCC_AHB1RSTR_ARTRST_Pos                (14U)

+#define RCC_AHB1RSTR_ARTRST_Msk                (0x1UL << RCC_AHB1RSTR_ARTRST_Pos)       /*!< 0x00004000 */

+#define RCC_AHB1RSTR_ARTRST                    RCC_AHB1RSTR_ARTRST_Msk

+#define RCC_AHB1RSTR_ETH1MACRST_Pos            (15U)

+#define RCC_AHB1RSTR_ETH1MACRST_Msk            (0x1UL << RCC_AHB1RSTR_ETH1MACRST_Pos)   /*!< 0x00008000 */

+#define RCC_AHB1RSTR_ETH1MACRST                RCC_AHB1RSTR_ETH1MACRST_Msk

+#define RCC_AHB1RSTR_USB1OTGHSRST_Pos          (25U)

+#define RCC_AHB1RSTR_USB1OTGHSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */

+#define RCC_AHB1RSTR_USB1OTGHSRST              RCC_AHB1RSTR_USB1OTGHSRST_Msk

+#define RCC_AHB1RSTR_USB2OTGFSRST_Pos          (27U)

+#define RCC_AHB1RSTR_USB2OTGFSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB2OTGFSRST_Pos) /*!< 0x08000000 */

+#define RCC_AHB1RSTR_USB2OTGFSRST              RCC_AHB1RSTR_USB2OTGFSRST_Msk

+

+/* Legacy define */

+#define RCC_AHB1RSTR_USB2OTGHSRST_Pos          RCC_AHB1RSTR_USB2OTGFSRST_Pos

+#define RCC_AHB1RSTR_USB2OTGHSRST_Msk          RCC_AHB1RSTR_USB2OTGFSRST_Msk

+#define RCC_AHB1RSTR_USB2OTGHSRST              RCC_AHB1RSTR_USB2OTGFSRST

+

+/********************  Bit definition for RCC_AHB2RSTR register  ***************/

+#define RCC_AHB2RSTR_DCMIRST_Pos               (0U)

+#define RCC_AHB2RSTR_DCMIRST_Msk               (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)       /*!< 0x00000001 */

+#define RCC_AHB2RSTR_DCMIRST                   RCC_AHB2RSTR_DCMIRST_Msk

+#define RCC_AHB2RSTR_RNGRST_Pos                (6U)

+#define RCC_AHB2RSTR_RNGRST_Msk                (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)        /*!< 0x00000040 */

+#define RCC_AHB2RSTR_RNGRST                    RCC_AHB2RSTR_RNGRST_Msk

+#define RCC_AHB2RSTR_SDMMC2RST_Pos             (9U)

+#define RCC_AHB2RSTR_SDMMC2RST_Msk             (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)     /*!< 0x00000200 */

+#define RCC_AHB2RSTR_SDMMC2RST                 RCC_AHB2RSTR_SDMMC2RST_Msk

+

+/********************  Bit definition for RCC_AHB4RSTR register  ******************/

+#define RCC_AHB4RSTR_GPIOARST_Pos              (0U)

+#define RCC_AHB4RSTR_GPIOARST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB4RSTR_GPIOARST                  RCC_AHB4RSTR_GPIOARST_Msk

+#define RCC_AHB4RSTR_GPIOBRST_Pos              (1U)

+#define RCC_AHB4RSTR_GPIOBRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)      /*!< 0x00000002 */

+#define RCC_AHB4RSTR_GPIOBRST                  RCC_AHB4RSTR_GPIOBRST_Msk

+#define RCC_AHB4RSTR_GPIOCRST_Pos              (2U)

+#define RCC_AHB4RSTR_GPIOCRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)      /*!< 0x00000004 */

+#define RCC_AHB4RSTR_GPIOCRST                  RCC_AHB4RSTR_GPIOCRST_Msk

+#define RCC_AHB4RSTR_GPIODRST_Pos              (3U)

+#define RCC_AHB4RSTR_GPIODRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)      /*!< 0x00000008 */

+#define RCC_AHB4RSTR_GPIODRST                  RCC_AHB4RSTR_GPIODRST_Msk

+#define RCC_AHB4RSTR_GPIOERST_Pos              (4U)

+#define RCC_AHB4RSTR_GPIOERST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)      /*!< 0x00000010 */

+#define RCC_AHB4RSTR_GPIOERST                  RCC_AHB4RSTR_GPIOERST_Msk

+#define RCC_AHB4RSTR_GPIOFRST_Pos              (5U)

+#define RCC_AHB4RSTR_GPIOFRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)       /*!< 0x00000020 */

+#define RCC_AHB4RSTR_GPIOFRST                  RCC_AHB4RSTR_GPIOFRST_Msk

+#define RCC_AHB4RSTR_GPIOGRST_Pos              (6U)

+#define RCC_AHB4RSTR_GPIOGRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)       /*!< 0x00000040 */

+#define RCC_AHB4RSTR_GPIOGRST                  RCC_AHB4RSTR_GPIOGRST_Msk

+#define RCC_AHB4RSTR_GPIOHRST_Pos              (7U)

+#define RCC_AHB4RSTR_GPIOHRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)       /*!< 0x00000080 */

+#define RCC_AHB4RSTR_GPIOHRST                  RCC_AHB4RSTR_GPIOHRST_Msk

+#define RCC_AHB4RSTR_GPIOIRST_Pos              (8U)

+#define RCC_AHB4RSTR_GPIOIRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos)       /*!< 0x00000100 */

+#define RCC_AHB4RSTR_GPIOIRST                  RCC_AHB4RSTR_GPIOIRST_Msk

+#define RCC_AHB4RSTR_GPIOJRST_Pos              (9U)

+#define RCC_AHB4RSTR_GPIOJRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos)       /*!< 0x00000200 */

+#define RCC_AHB4RSTR_GPIOJRST                  RCC_AHB4RSTR_GPIOJRST_Msk

+#define RCC_AHB4RSTR_GPIOKRST_Pos              (10U)

+#define RCC_AHB4RSTR_GPIOKRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos)       /*!< 0x00000400 */

+#define RCC_AHB4RSTR_GPIOKRST                  RCC_AHB4RSTR_GPIOKRST_Msk

+#define RCC_AHB4RSTR_CRCRST_Pos                (19U)

+#define RCC_AHB4RSTR_CRCRST_Msk                (0x1UL << RCC_AHB4RSTR_CRCRST_Pos)         /*!< 0x00080000 */

+#define RCC_AHB4RSTR_CRCRST                    RCC_AHB4RSTR_CRCRST_Msk

+#define RCC_AHB4RSTR_BDMARST_Pos               (21U)

+#define RCC_AHB4RSTR_BDMARST_Msk               (0x1UL << RCC_AHB4RSTR_BDMARST_Pos)        /*!< 0x00200000 */

+#define RCC_AHB4RSTR_BDMARST                   RCC_AHB4RSTR_BDMARST_Msk

+#define RCC_AHB4RSTR_ADC3RST_Pos               (24U)

+#define RCC_AHB4RSTR_ADC3RST_Msk               (0x1UL << RCC_AHB4RSTR_ADC3RST_Pos)        /*!< 0x01000000 */

+#define RCC_AHB4RSTR_ADC3RST                   RCC_AHB4RSTR_ADC3RST_Msk

+#define RCC_AHB4RSTR_HSEMRST_Pos               (25U)

+#define RCC_AHB4RSTR_HSEMRST_Msk               (0x1UL << RCC_AHB4RSTR_HSEMRST_Pos)        /*!< 0x02000000 */

+#define RCC_AHB4RSTR_HSEMRST                   RCC_AHB4RSTR_HSEMRST_Msk

+

+

+/********************  Bit definition for RCC_APB3RSTR register  ******************/

+#define RCC_APB3RSTR_LTDCRST_Pos               (3U)

+#define RCC_APB3RSTR_LTDCRST_Msk               (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */

+#define RCC_APB3RSTR_LTDCRST                   RCC_APB3RSTR_LTDCRST_Msk

+

+/********************  Bit definition for RCC_APB1LRSTR register  ******************/

+

+#define RCC_APB1LRSTR_TIM2RST_Pos              (0U)

+#define RCC_APB1LRSTR_TIM2RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */

+#define RCC_APB1LRSTR_TIM2RST                  RCC_APB1LRSTR_TIM2RST_Msk

+#define RCC_APB1LRSTR_TIM3RST_Pos              (1U)

+#define RCC_APB1LRSTR_TIM3RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */

+#define RCC_APB1LRSTR_TIM3RST                  RCC_APB1LRSTR_TIM3RST_Msk

+#define RCC_APB1LRSTR_TIM4RST_Pos              (2U)

+#define RCC_APB1LRSTR_TIM4RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */

+#define RCC_APB1LRSTR_TIM4RST                  RCC_APB1LRSTR_TIM4RST_Msk

+#define RCC_APB1LRSTR_TIM5RST_Pos              (3U)

+#define RCC_APB1LRSTR_TIM5RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */

+#define RCC_APB1LRSTR_TIM5RST                  RCC_APB1LRSTR_TIM5RST_Msk

+#define RCC_APB1LRSTR_TIM6RST_Pos              (4U)

+#define RCC_APB1LRSTR_TIM6RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */

+#define RCC_APB1LRSTR_TIM6RST                  RCC_APB1LRSTR_TIM6RST_Msk

+#define RCC_APB1LRSTR_TIM7RST_Pos              (5U)

+#define RCC_APB1LRSTR_TIM7RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */

+#define RCC_APB1LRSTR_TIM7RST                  RCC_APB1LRSTR_TIM7RST_Msk

+#define RCC_APB1LRSTR_TIM12RST_Pos             (6U)

+#define RCC_APB1LRSTR_TIM12RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */

+#define RCC_APB1LRSTR_TIM12RST                 RCC_APB1LRSTR_TIM12RST_Msk

+#define RCC_APB1LRSTR_TIM13RST_Pos             (7U)

+#define RCC_APB1LRSTR_TIM13RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */

+#define RCC_APB1LRSTR_TIM13RST                 RCC_APB1LRSTR_TIM13RST_Msk

+#define RCC_APB1LRSTR_TIM14RST_Pos             (8U)

+#define RCC_APB1LRSTR_TIM14RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */

+#define RCC_APB1LRSTR_TIM14RST                 RCC_APB1LRSTR_TIM14RST_Msk

+#define RCC_APB1LRSTR_LPTIM1RST_Pos            (9U)

+#define RCC_APB1LRSTR_LPTIM1RST_Msk            (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */

+#define RCC_APB1LRSTR_LPTIM1RST                RCC_APB1LRSTR_LPTIM1RST_Msk

+#define RCC_APB1LRSTR_SPI2RST_Pos              (14U)

+#define RCC_APB1LRSTR_SPI2RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */

+#define RCC_APB1LRSTR_SPI2RST                  RCC_APB1LRSTR_SPI2RST_Msk

+#define RCC_APB1LRSTR_SPI3RST_Pos              (15U)

+#define RCC_APB1LRSTR_SPI3RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */

+#define RCC_APB1LRSTR_SPI3RST                  RCC_APB1LRSTR_SPI3RST_Msk

+#define RCC_APB1LRSTR_SPDIFRXRST_Pos           (16U)

+#define RCC_APB1LRSTR_SPDIFRXRST_Msk           (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */

+#define RCC_APB1LRSTR_SPDIFRXRST               RCC_APB1LRSTR_SPDIFRXRST_Msk

+#define RCC_APB1LRSTR_USART2RST_Pos            (17U)

+#define RCC_APB1LRSTR_USART2RST_Msk            (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */

+#define RCC_APB1LRSTR_USART2RST                RCC_APB1LRSTR_USART2RST_Msk

+#define RCC_APB1LRSTR_USART3RST_Pos            (18U)

+#define RCC_APB1LRSTR_USART3RST_Msk            (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */

+#define RCC_APB1LRSTR_USART3RST                RCC_APB1LRSTR_USART3RST_Msk

+#define RCC_APB1LRSTR_UART4RST_Pos             (19U)

+#define RCC_APB1LRSTR_UART4RST_Msk             (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */

+#define RCC_APB1LRSTR_UART4RST                 RCC_APB1LRSTR_UART4RST_Msk

+#define RCC_APB1LRSTR_UART5RST_Pos             (20U)

+#define RCC_APB1LRSTR_UART5RST_Msk             (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */

+#define RCC_APB1LRSTR_UART5RST                 RCC_APB1LRSTR_UART5RST_Msk

+#define RCC_APB1LRSTR_I2C1RST_Pos              (21U)

+#define RCC_APB1LRSTR_I2C1RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */

+#define RCC_APB1LRSTR_I2C1RST                  RCC_APB1LRSTR_I2C1RST_Msk

+#define RCC_APB1LRSTR_I2C2RST_Pos              (22U)

+#define RCC_APB1LRSTR_I2C2RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */

+#define RCC_APB1LRSTR_I2C2RST                  RCC_APB1LRSTR_I2C2RST_Msk

+#define RCC_APB1LRSTR_I2C3RST_Pos              (23U)

+#define RCC_APB1LRSTR_I2C3RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */

+#define RCC_APB1LRSTR_I2C3RST                  RCC_APB1LRSTR_I2C3RST_Msk

+#define RCC_APB1LRSTR_CECRST_Pos               (27U)

+#define RCC_APB1LRSTR_CECRST_Msk               (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */

+#define RCC_APB1LRSTR_CECRST                   RCC_APB1LRSTR_CECRST_Msk

+#define RCC_APB1LRSTR_DAC12RST_Pos             (29U)

+#define RCC_APB1LRSTR_DAC12RST_Msk             (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */

+#define RCC_APB1LRSTR_DAC12RST                 RCC_APB1LRSTR_DAC12RST_Msk

+#define RCC_APB1LRSTR_UART7RST_Pos             (30U)

+#define RCC_APB1LRSTR_UART7RST_Msk             (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */

+#define RCC_APB1LRSTR_UART7RST                 RCC_APB1LRSTR_UART7RST_Msk

+#define RCC_APB1LRSTR_UART8RST_Pos             (31U)

+#define RCC_APB1LRSTR_UART8RST_Msk             (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */

+#define RCC_APB1LRSTR_UART8RST                 RCC_APB1LRSTR_UART8RST_Msk

+

+/* Legacy define */

+#define RCC_APB1LRSTR_HDMICECRST_Pos           RCC_APB1LRSTR_CECRST_Pos

+#define RCC_APB1LRSTR_HDMICECRST_Msk           RCC_APB1LRSTR_CECRST_Msk

+#define RCC_APB1LRSTR_HDMICECRST               RCC_APB1LRSTR_CECRST

+/********************  Bit definition for RCC_APB1HRSTR register  ******************/

+#define RCC_APB1HRSTR_CRSRST_Pos               (1U)

+#define RCC_APB1HRSTR_CRSRST_Msk               (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */

+#define RCC_APB1HRSTR_CRSRST                   RCC_APB1HRSTR_CRSRST_Msk

+#define RCC_APB1HRSTR_SWPMIRST_Pos             (2U)

+#define RCC_APB1HRSTR_SWPMIRST_Msk             (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */

+#define RCC_APB1HRSTR_SWPMIRST                 RCC_APB1HRSTR_SWPMIRST_Msk

+#define RCC_APB1HRSTR_OPAMPRST_Pos             (4U)

+#define RCC_APB1HRSTR_OPAMPRST_Msk             (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */

+#define RCC_APB1HRSTR_OPAMPRST                 RCC_APB1HRSTR_OPAMPRST_Msk

+#define RCC_APB1HRSTR_MDIOSRST_Pos             (5U)

+#define RCC_APB1HRSTR_MDIOSRST_Msk             (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */

+#define RCC_APB1HRSTR_MDIOSRST                 RCC_APB1HRSTR_MDIOSRST_Msk

+#define RCC_APB1HRSTR_FDCANRST_Pos             (8U)

+#define RCC_APB1HRSTR_FDCANRST_Msk             (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */

+#define RCC_APB1HRSTR_FDCANRST                 RCC_APB1HRSTR_FDCANRST_Msk

+

+/********************  Bit definition for RCC_APB2RSTR register  ******************/

+#define RCC_APB2RSTR_TIM1RST_Pos               (0U)

+#define RCC_APB2RSTR_TIM1RST_Msk               (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */

+#define RCC_APB2RSTR_TIM1RST                   RCC_APB2RSTR_TIM1RST_Msk

+#define RCC_APB2RSTR_TIM8RST_Pos               (1U)

+#define RCC_APB2RSTR_TIM8RST_Msk               (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */

+#define RCC_APB2RSTR_TIM8RST                   RCC_APB2RSTR_TIM8RST_Msk

+#define RCC_APB2RSTR_USART1RST_Pos             (4U)

+#define RCC_APB2RSTR_USART1RST_Msk             (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */

+#define RCC_APB2RSTR_USART1RST                 RCC_APB2RSTR_USART1RST_Msk

+#define RCC_APB2RSTR_USART6RST_Pos             (5U)

+#define RCC_APB2RSTR_USART6RST_Msk             (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */

+#define RCC_APB2RSTR_USART6RST                 RCC_APB2RSTR_USART6RST_Msk

+#define RCC_APB2RSTR_SPI1RST_Pos               (12U)

+#define RCC_APB2RSTR_SPI1RST_Msk               (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */

+#define RCC_APB2RSTR_SPI1RST                   RCC_APB2RSTR_SPI1RST_Msk

+#define RCC_APB2RSTR_SPI4RST_Pos               (13U)

+#define RCC_APB2RSTR_SPI4RST_Msk               (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */

+#define RCC_APB2RSTR_SPI4RST                   RCC_APB2RSTR_SPI4RST_Msk

+#define RCC_APB2RSTR_TIM15RST_Pos              (16U)

+#define RCC_APB2RSTR_TIM15RST_Msk              (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */

+#define RCC_APB2RSTR_TIM15RST                  RCC_APB2RSTR_TIM15RST_Msk

+#define RCC_APB2RSTR_TIM16RST_Pos              (17U)

+#define RCC_APB2RSTR_TIM16RST_Msk              (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */

+#define RCC_APB2RSTR_TIM16RST                  RCC_APB2RSTR_TIM16RST_Msk

+#define RCC_APB2RSTR_TIM17RST_Pos              (18U)

+#define RCC_APB2RSTR_TIM17RST_Msk              (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */

+#define RCC_APB2RSTR_TIM17RST                  RCC_APB2RSTR_TIM17RST_Msk

+#define RCC_APB2RSTR_SPI5RST_Pos               (20U)

+#define RCC_APB2RSTR_SPI5RST_Msk               (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */

+#define RCC_APB2RSTR_SPI5RST                   RCC_APB2RSTR_SPI5RST_Msk

+#define RCC_APB2RSTR_SAI1RST_Pos               (22U)

+#define RCC_APB2RSTR_SAI1RST_Msk               (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */

+#define RCC_APB2RSTR_SAI1RST                   RCC_APB2RSTR_SAI1RST_Msk

+#define RCC_APB2RSTR_SAI2RST_Pos               (23U)

+#define RCC_APB2RSTR_SAI2RST_Msk               (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */

+#define RCC_APB2RSTR_SAI2RST                   RCC_APB2RSTR_SAI2RST_Msk

+#define RCC_APB2RSTR_SAI3RST_Pos               (24U)

+#define RCC_APB2RSTR_SAI3RST_Msk               (0x1UL << RCC_APB2RSTR_SAI3RST_Pos) /*!< 0x01000000 */

+#define RCC_APB2RSTR_SAI3RST                   RCC_APB2RSTR_SAI3RST_Msk

+#define RCC_APB2RSTR_DFSDM1RST_Pos             (28U)

+#define RCC_APB2RSTR_DFSDM1RST_Msk             (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */

+#define RCC_APB2RSTR_DFSDM1RST                 RCC_APB2RSTR_DFSDM1RST_Msk

+#define RCC_APB2RSTR_HRTIMRST_Pos              (29U)

+#define RCC_APB2RSTR_HRTIMRST_Msk              (0x1UL << RCC_APB2RSTR_HRTIMRST_Pos) /*!< 0x20000000 */

+#define RCC_APB2RSTR_HRTIMRST                  RCC_APB2RSTR_HRTIMRST_Msk

+

+/********************  Bit definition for RCC_APB4RSTR register  ******************/

+#define RCC_APB4RSTR_SYSCFGRST_Pos             (1U)

+#define RCC_APB4RSTR_SYSCFGRST_Msk             (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */

+#define RCC_APB4RSTR_SYSCFGRST                 RCC_APB4RSTR_SYSCFGRST_Msk

+#define RCC_APB4RSTR_LPUART1RST_Pos            (3U)

+#define RCC_APB4RSTR_LPUART1RST_Msk            (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */

+#define RCC_APB4RSTR_LPUART1RST                RCC_APB4RSTR_LPUART1RST_Msk

+#define RCC_APB4RSTR_SPI6RST_Pos               (5U)

+#define RCC_APB4RSTR_SPI6RST_Msk               (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */

+#define RCC_APB4RSTR_SPI6RST                   RCC_APB4RSTR_SPI6RST_Msk

+#define RCC_APB4RSTR_I2C4RST_Pos               (7U)

+#define RCC_APB4RSTR_I2C4RST_Msk               (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */

+#define RCC_APB4RSTR_I2C4RST                   RCC_APB4RSTR_I2C4RST_Msk

+#define RCC_APB4RSTR_LPTIM2RST_Pos             (9U)

+#define RCC_APB4RSTR_LPTIM2RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */

+#define RCC_APB4RSTR_LPTIM2RST                 RCC_APB4RSTR_LPTIM2RST_Msk

+#define RCC_APB4RSTR_LPTIM3RST_Pos             (10U)

+#define RCC_APB4RSTR_LPTIM3RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */

+#define RCC_APB4RSTR_LPTIM3RST                 RCC_APB4RSTR_LPTIM3RST_Msk

+#define RCC_APB4RSTR_LPTIM4RST_Pos             (11U)

+#define RCC_APB4RSTR_LPTIM4RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos) /*!< 0x00000800 */

+#define RCC_APB4RSTR_LPTIM4RST                 RCC_APB4RSTR_LPTIM4RST_Msk

+#define RCC_APB4RSTR_LPTIM5RST_Pos             (12U)

+#define RCC_APB4RSTR_LPTIM5RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos) /*!< 0x00001000 */

+#define RCC_APB4RSTR_LPTIM5RST                 RCC_APB4RSTR_LPTIM5RST_Msk

+#define RCC_APB4RSTR_COMP12RST_Pos             (14U)

+#define RCC_APB4RSTR_COMP12RST_Msk             (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */

+#define RCC_APB4RSTR_COMP12RST                 RCC_APB4RSTR_COMP12RST_Msk

+#define RCC_APB4RSTR_VREFRST_Pos               (15U)

+#define RCC_APB4RSTR_VREFRST_Msk               (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */

+#define RCC_APB4RSTR_VREFRST                   RCC_APB4RSTR_VREFRST_Msk

+#define RCC_APB4RSTR_SAI4RST_Pos               (21U)

+#define RCC_APB4RSTR_SAI4RST_Msk               (0x1UL << RCC_APB4RSTR_SAI4RST_Pos) /*!< 0x00200000 */

+#define RCC_APB4RSTR_SAI4RST                   RCC_APB4RSTR_SAI4RST_Msk

+

+

+/********************  Bit definition for RCC_GCR register  ********************/

+#define RCC_GCR_WW1RSC_Pos                     (0U)

+#define RCC_GCR_WW1RSC_Msk                     (0x1UL << RCC_GCR_WW1RSC_Pos)   /*!< 0x00000001 */

+#define RCC_GCR_WW1RSC                         RCC_GCR_WW1RSC_Msk

+#define RCC_GCR_WW2RSC_Pos                     (1U)

+#define RCC_GCR_WW2RSC_Msk                     (0x1UL << RCC_GCR_WW2RSC_Pos)   /*!< 0x00000002 */

+#define RCC_GCR_WW2RSC                         RCC_GCR_WW2RSC_Msk

+#define RCC_GCR_BOOT_C1_Pos                    (2U)

+#define RCC_GCR_BOOT_C1_Msk                    (0x1UL << RCC_GCR_BOOT_C1_Pos)  /*!< 0x00000004 */

+#define RCC_GCR_BOOT_C1                        RCC_GCR_BOOT_C1_Msk

+#define RCC_GCR_BOOT_C2_Pos                    (3U)

+#define RCC_GCR_BOOT_C2_Msk                    (0x1UL << RCC_GCR_BOOT_C2_Pos)  /*!< 0x00000008 */

+#define RCC_GCR_BOOT_C2                        RCC_GCR_BOOT_C2_Msk

+

+/********************  Bit definition for RCC_D3AMR register  ********************/

+#define RCC_D3AMR_BDMAAMEN_Pos                 (0U)

+#define RCC_D3AMR_BDMAAMEN_Msk                 (0x1UL << RCC_D3AMR_BDMAAMEN_Pos) /*!< 0x00000001 */

+#define RCC_D3AMR_BDMAAMEN                     RCC_D3AMR_BDMAAMEN_Msk

+#define RCC_D3AMR_LPUART1AMEN_Pos              (3U)

+#define RCC_D3AMR_LPUART1AMEN_Msk              (0x1UL << RCC_D3AMR_LPUART1AMEN_Pos) /*!< 0x00000008 */

+#define RCC_D3AMR_LPUART1AMEN                  RCC_D3AMR_LPUART1AMEN_Msk

+#define RCC_D3AMR_SPI6AMEN_Pos                 (5U)

+#define RCC_D3AMR_SPI6AMEN_Msk                 (0x1UL << RCC_D3AMR_SPI6AMEN_Pos) /*!< 0x00000020 */

+#define RCC_D3AMR_SPI6AMEN                     RCC_D3AMR_SPI6AMEN_Msk

+#define RCC_D3AMR_I2C4AMEN_Pos                 (7U)

+#define RCC_D3AMR_I2C4AMEN_Msk                 (0x1UL << RCC_D3AMR_I2C4AMEN_Pos) /*!< 0x00000080 */

+#define RCC_D3AMR_I2C4AMEN                     RCC_D3AMR_I2C4AMEN_Msk

+#define RCC_D3AMR_LPTIM2AMEN_Pos               (9U)

+#define RCC_D3AMR_LPTIM2AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */

+#define RCC_D3AMR_LPTIM2AMEN                   RCC_D3AMR_LPTIM2AMEN_Msk

+#define RCC_D3AMR_LPTIM3AMEN_Pos               (10U)

+#define RCC_D3AMR_LPTIM3AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */

+#define RCC_D3AMR_LPTIM3AMEN                   RCC_D3AMR_LPTIM3AMEN_Msk

+#define RCC_D3AMR_LPTIM4AMEN_Pos               (11U)

+#define RCC_D3AMR_LPTIM4AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM4AMEN_Pos) /*!< 0x00000800 */

+#define RCC_D3AMR_LPTIM4AMEN                   RCC_D3AMR_LPTIM4AMEN_Msk

+#define RCC_D3AMR_LPTIM5AMEN_Pos               (12U)

+#define RCC_D3AMR_LPTIM5AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM5AMEN_Pos) /*!< 0x00001000 */

+#define RCC_D3AMR_LPTIM5AMEN                   RCC_D3AMR_LPTIM5AMEN_Msk

+#define RCC_D3AMR_COMP12AMEN_Pos               (14U)

+#define RCC_D3AMR_COMP12AMEN_Msk               (0x1UL << RCC_D3AMR_COMP12AMEN_Pos) /*!< 0x00004000 */

+#define RCC_D3AMR_COMP12AMEN                   RCC_D3AMR_COMP12AMEN_Msk

+#define RCC_D3AMR_VREFAMEN_Pos                 (15U)

+#define RCC_D3AMR_VREFAMEN_Msk                 (0x1UL << RCC_D3AMR_VREFAMEN_Pos) /*!< 0x00008000 */

+#define RCC_D3AMR_VREFAMEN                     RCC_D3AMR_VREFAMEN_Msk

+#define RCC_D3AMR_RTCAMEN_Pos                  (16U)

+#define RCC_D3AMR_RTCAMEN_Msk                  (0x1UL << RCC_D3AMR_RTCAMEN_Pos) /*!< 0x00010000 */

+#define RCC_D3AMR_RTCAMEN                      RCC_D3AMR_RTCAMEN_Msk

+#define RCC_D3AMR_CRCAMEN_Pos                  (19U)

+#define RCC_D3AMR_CRCAMEN_Msk                  (0x1UL << RCC_D3AMR_CRCAMEN_Pos) /*!< 0x00080000 */

+#define RCC_D3AMR_CRCAMEN                      RCC_D3AMR_CRCAMEN_Msk

+#define RCC_D3AMR_SAI4AMEN_Pos                 (21U)

+#define RCC_D3AMR_SAI4AMEN_Msk                 (0x1UL << RCC_D3AMR_SAI4AMEN_Pos) /*!< 0x00200000 */

+#define RCC_D3AMR_SAI4AMEN                     RCC_D3AMR_SAI4AMEN_Msk

+#define RCC_D3AMR_ADC3AMEN_Pos                 (24U)

+#define RCC_D3AMR_ADC3AMEN_Msk                 (0x1UL << RCC_D3AMR_ADC3AMEN_Pos) /*!< 0x01000000 */

+#define RCC_D3AMR_ADC3AMEN                     RCC_D3AMR_ADC3AMEN_Msk

+

+

+#define RCC_D3AMR_BKPRAMAMEN_Pos               (28U)

+#define RCC_D3AMR_BKPRAMAMEN_Msk               (0x1UL << RCC_D3AMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */

+#define RCC_D3AMR_BKPRAMAMEN                   RCC_D3AMR_BKPRAMAMEN_Msk

+#define RCC_D3AMR_SRAM4AMEN_Pos                (29U)

+#define RCC_D3AMR_SRAM4AMEN_Msk                (0x1UL << RCC_D3AMR_SRAM4AMEN_Pos) /*!< 0x20000000 */

+#define RCC_D3AMR_SRAM4AMEN                    RCC_D3AMR_SRAM4AMEN_Msk

+/********************  Bit definition for RCC_AHB3LPENR register  **************/

+#define RCC_AHB3LPENR_MDMALPEN_Pos             (0U)

+#define RCC_AHB3LPENR_MDMALPEN_Msk             (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos)         /*!< 0x00000001 */

+#define RCC_AHB3LPENR_MDMALPEN                 RCC_AHB3LPENR_MDMALPEN_Msk

+#define RCC_AHB3LPENR_DMA2DLPEN_Pos            (4U)

+#define RCC_AHB3LPENR_DMA2DLPEN_Msk            (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos)        /*!< 0x00000010 */

+#define RCC_AHB3LPENR_DMA2DLPEN                RCC_AHB3LPENR_DMA2DLPEN_Msk

+#define RCC_AHB3LPENR_JPGDECLPEN_Pos           (5U)

+#define RCC_AHB3LPENR_JPGDECLPEN_Msk           (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos)       /*!< 0x00000020 */

+#define RCC_AHB3LPENR_JPGDECLPEN               RCC_AHB3LPENR_JPGDECLPEN_Msk

+#define RCC_AHB3LPENR_FLASHLPEN_Pos            (8U)

+#define RCC_AHB3LPENR_FLASHLPEN_Msk            (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos)        /*!< 0x00000100 */

+#define RCC_AHB3LPENR_FLASHLPEN                RCC_AHB3LPENR_FLASHLPEN_Msk

+#define RCC_AHB3LPENR_FMCLPEN_Pos              (12U)

+#define RCC_AHB3LPENR_FMCLPEN_Msk              (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)          /*!< 0x00001000 */

+#define RCC_AHB3LPENR_FMCLPEN                  RCC_AHB3LPENR_FMCLPEN_Msk

+#define RCC_AHB3LPENR_QSPILPEN_Pos             (14U)

+#define RCC_AHB3LPENR_QSPILPEN_Msk             (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos)         /*!< 0x00004000 */

+#define RCC_AHB3LPENR_QSPILPEN                 RCC_AHB3LPENR_QSPILPEN_Msk

+#define RCC_AHB3LPENR_SDMMC1LPEN_Pos           (16U)

+#define RCC_AHB3LPENR_SDMMC1LPEN_Msk           (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos)       /*!< 0x00010000 */

+#define RCC_AHB3LPENR_SDMMC1LPEN               RCC_AHB3LPENR_SDMMC1LPEN_Msk

+#define RCC_AHB3LPENR_DTCM1LPEN_Pos            (28U)

+#define RCC_AHB3LPENR_DTCM1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos)        /*!< 0x10000000 */

+#define RCC_AHB3LPENR_DTCM1LPEN                RCC_AHB3LPENR_DTCM1LPEN_Msk

+#define RCC_AHB3LPENR_DTCM2LPEN_Pos            (29U)

+#define RCC_AHB3LPENR_DTCM2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos)        /*!< 0x20000000 */

+#define RCC_AHB3LPENR_DTCM2LPEN                RCC_AHB3LPENR_DTCM2LPEN_Msk

+#define RCC_AHB3LPENR_ITCMLPEN_Pos             (30U)

+#define RCC_AHB3LPENR_ITCMLPEN_Msk             (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos)         /*!< 0x40000000 */

+#define RCC_AHB3LPENR_ITCMLPEN                 RCC_AHB3LPENR_ITCMLPEN_Msk

+#define RCC_AHB3LPENR_AXISRAMLPEN_Pos          (31U)

+#define RCC_AHB3LPENR_AXISRAMLPEN_Msk          (0x1UL << RCC_AHB3LPENR_AXISRAMLPEN_Pos)      /*!< 0x80000000 */

+#define RCC_AHB3LPENR_AXISRAMLPEN              RCC_AHB3LPENR_AXISRAMLPEN_Msk

+

+

+/********************  Bit definition for RCC_AHB1LPENR register  ***************/

+#define RCC_AHB1LPENR_DMA1LPEN_Pos             (0U)

+#define RCC_AHB1LPENR_DMA1LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB1LPENR_DMA1LPEN                 RCC_AHB1LPENR_DMA1LPEN_Msk

+#define RCC_AHB1LPENR_DMA2LPEN_Pos             (1U)

+#define RCC_AHB1LPENR_DMA2LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */

+#define RCC_AHB1LPENR_DMA2LPEN                 RCC_AHB1LPENR_DMA2LPEN_Msk

+#define RCC_AHB1LPENR_ADC12LPEN_Pos            (5U)

+#define RCC_AHB1LPENR_ADC12LPEN_Msk            (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB1LPENR_ADC12LPEN                RCC_AHB1LPENR_ADC12LPEN_Msk

+#define RCC_AHB1LPENR_ARTLPEN_Pos              (14U)

+#define RCC_AHB1LPENR_ARTLPEN_Msk              (0x1UL << RCC_AHB1LPENR_ARTLPEN_Pos) /*!< 0x00004000 */

+#define RCC_AHB1LPENR_ARTLPEN                  RCC_AHB1LPENR_ARTLPEN_Msk

+#define RCC_AHB1LPENR_ETH1MACLPEN_Pos          (15U)

+#define RCC_AHB1LPENR_ETH1MACLPEN_Msk          (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) /*!< 0x00008000 */

+#define RCC_AHB1LPENR_ETH1MACLPEN              RCC_AHB1LPENR_ETH1MACLPEN_Msk

+#define RCC_AHB1LPENR_ETH1TXLPEN_Pos           (16U)

+#define RCC_AHB1LPENR_ETH1TXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00010000 */

+#define RCC_AHB1LPENR_ETH1TXLPEN               RCC_AHB1LPENR_ETH1TXLPEN_Msk

+#define RCC_AHB1LPENR_ETH1RXLPEN_Pos           (17U)

+#define RCC_AHB1LPENR_ETH1RXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00020000 */

+#define RCC_AHB1LPENR_ETH1RXLPEN               RCC_AHB1LPENR_ETH1RXLPEN_Msk

+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos        (25U)

+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */

+#define RCC_AHB1LPENR_USB1OTGHSLPEN            RCC_AHB1LPENR_USB1OTGHSLPEN_Msk

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos    (26U)

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN        RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGFSLPEN_Pos        (27U)

+#define RCC_AHB1LPENR_USB2OTGFSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB2OTGFSLPEN_Pos) /*!< 0x08000000 */

+#define RCC_AHB1LPENR_USB2OTGFSLPEN            RCC_AHB1LPENR_USB2OTGFSLPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos    (28U)

+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos) /*!< 0x10000000 */

+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN        RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk

+

+/* Legacy define */

+#define RCC_AHB1LPENR_USB2OTGHSLPEN_Pos        RCC_AHB1LPENR_USB2OTGFSLPEN_Pos

+#define RCC_AHB1LPENR_USB2OTGHSLPEN_Msk        RCC_AHB1LPENR_USB2OTGFSLPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGHSLPEN            RCC_AHB1LPENR_USB2OTGFSLPEN

+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Pos    RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos

+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Msk    RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN        RCC_AHB1LPENR_USB2OTGFSULPILPEN

+

+/********************  Bit definition for RCC_AHB2LPENR register  ***************/

+#define RCC_AHB2LPENR_DCMILPEN_Pos             (0U)

+#define RCC_AHB2LPENR_DCMILPEN_Msk             (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB2LPENR_DCMILPEN                 RCC_AHB2LPENR_DCMILPEN_Msk

+#define RCC_AHB2LPENR_RNGLPEN_Pos              (6U)

+#define RCC_AHB2LPENR_RNGLPEN_Msk              (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */

+#define RCC_AHB2LPENR_RNGLPEN                  RCC_AHB2LPENR_RNGLPEN_Msk

+#define RCC_AHB2LPENR_SDMMC2LPEN_Pos           (9U)

+#define RCC_AHB2LPENR_SDMMC2LPEN_Msk           (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */

+#define RCC_AHB2LPENR_SDMMC2LPEN               RCC_AHB2LPENR_SDMMC2LPEN_Msk

+#define RCC_AHB2LPENR_SRAM1LPEN_Pos          (29U)

+#define RCC_AHB2LPENR_SRAM1LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos) /*!< 0x20000000 */

+#define RCC_AHB2LPENR_SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN_Msk

+#define RCC_AHB2LPENR_SRAM2LPEN_Pos          (30U)

+#define RCC_AHB2LPENR_SRAM2LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */

+#define RCC_AHB2LPENR_SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN_Msk

+#define RCC_AHB2LPENR_SRAM3LPEN_Pos          (31U)

+#define RCC_AHB2LPENR_SRAM3LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM3LPEN_Pos) /*!< 0x80000000 */

+#define RCC_AHB2LPENR_SRAM3LPEN              RCC_AHB2LPENR_SRAM3LPEN_Msk

+

+/* Legacy define */

+#define RCC_AHB2LPENR_D2SRAM1LPEN_Pos          RCC_AHB2LPENR_SRAM1LPEN_Pos

+#define RCC_AHB2LPENR_D2SRAM1LPEN_Msk          RCC_AHB2LPENR_SRAM1LPEN_Msk

+#define RCC_AHB2LPENR_D2SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN

+#define RCC_AHB2LPENR_D2SRAM2LPEN_Pos          RCC_AHB2LPENR_SRAM2LPEN_Pos

+#define RCC_AHB2LPENR_D2SRAM2LPEN_Msk          RCC_AHB2LPENR_SRAM2LPEN_Msk

+#define RCC_AHB2LPENR_D2SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN

+#define RCC_AHB2LPENR_D2SRAM3LPEN_Pos          RCC_AHB2LPENR_SRAM3LPEN_Pos

+#define RCC_AHB2LPENR_D2SRAM3LPEN_Msk          RCC_AHB2LPENR_SRAM3LPEN_Msk

+#define RCC_AHB2LPENR_D2SRAM3LPEN              RCC_AHB2LPENR_SRAM3LPEN

+

+/********************  Bit definition for RCC_AHB4LPENR register  ******************/

+#define RCC_AHB4LPENR_GPIOALPEN_Pos            (0U)

+#define RCC_AHB4LPENR_GPIOALPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB4LPENR_GPIOALPEN                RCC_AHB4LPENR_GPIOALPEN_Msk

+#define RCC_AHB4LPENR_GPIOBLPEN_Pos            (1U)

+#define RCC_AHB4LPENR_GPIOBLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */

+#define RCC_AHB4LPENR_GPIOBLPEN                RCC_AHB4LPENR_GPIOBLPEN_Msk

+#define RCC_AHB4LPENR_GPIOCLPEN_Pos            (2U)

+#define RCC_AHB4LPENR_GPIOCLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */

+#define RCC_AHB4LPENR_GPIOCLPEN                RCC_AHB4LPENR_GPIOCLPEN_Msk

+#define RCC_AHB4LPENR_GPIODLPEN_Pos            (3U)

+#define RCC_AHB4LPENR_GPIODLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */

+#define RCC_AHB4LPENR_GPIODLPEN                RCC_AHB4LPENR_GPIODLPEN_Msk

+#define RCC_AHB4LPENR_GPIOELPEN_Pos            (4U)

+#define RCC_AHB4LPENR_GPIOELPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */

+#define RCC_AHB4LPENR_GPIOELPEN                RCC_AHB4LPENR_GPIOELPEN_Msk

+#define RCC_AHB4LPENR_GPIOFLPEN_Pos            (5U)

+#define RCC_AHB4LPENR_GPIOFLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB4LPENR_GPIOFLPEN                RCC_AHB4LPENR_GPIOFLPEN_Msk

+#define RCC_AHB4LPENR_GPIOGLPEN_Pos            (6U)

+#define RCC_AHB4LPENR_GPIOGLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */

+#define RCC_AHB4LPENR_GPIOGLPEN                RCC_AHB4LPENR_GPIOGLPEN_Msk

+#define RCC_AHB4LPENR_GPIOHLPEN_Pos            (7U)

+#define RCC_AHB4LPENR_GPIOHLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */

+#define RCC_AHB4LPENR_GPIOHLPEN                RCC_AHB4LPENR_GPIOHLPEN_Msk

+#define RCC_AHB4LPENR_GPIOILPEN_Pos            (8U)

+#define RCC_AHB4LPENR_GPIOILPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */

+#define RCC_AHB4LPENR_GPIOILPEN                RCC_AHB4LPENR_GPIOILPEN_Msk

+#define RCC_AHB4LPENR_GPIOJLPEN_Pos            (9U)

+#define RCC_AHB4LPENR_GPIOJLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */

+#define RCC_AHB4LPENR_GPIOJLPEN                RCC_AHB4LPENR_GPIOJLPEN_Msk

+#define RCC_AHB4LPENR_GPIOKLPEN_Pos            (10U)

+#define RCC_AHB4LPENR_GPIOKLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */

+#define RCC_AHB4LPENR_GPIOKLPEN                RCC_AHB4LPENR_GPIOKLPEN_Msk

+#define RCC_AHB4LPENR_CRCLPEN_Pos              (19U)

+#define RCC_AHB4LPENR_CRCLPEN_Msk              (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */

+#define RCC_AHB4LPENR_CRCLPEN                  RCC_AHB4LPENR_CRCLPEN_Msk

+#define RCC_AHB4LPENR_BDMALPEN_Pos             (21U)

+#define RCC_AHB4LPENR_BDMALPEN_Msk             (0x1UL << RCC_AHB4LPENR_BDMALPEN_Pos) /*!< 0x00200000 */

+#define RCC_AHB4LPENR_BDMALPEN                 RCC_AHB4LPENR_BDMALPEN_Msk

+#define RCC_AHB4LPENR_ADC3LPEN_Pos             (24U)

+#define RCC_AHB4LPENR_ADC3LPEN_Msk             (0x1UL << RCC_AHB4LPENR_ADC3LPEN_Pos) /*!< 0x01000000 */

+#define RCC_AHB4LPENR_ADC3LPEN                 RCC_AHB4LPENR_ADC3LPEN_Msk

+#define RCC_AHB4LPENR_BKPRAMLPEN_Pos           (28U)

+#define RCC_AHB4LPENR_BKPRAMLPEN_Msk           (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */

+#define RCC_AHB4LPENR_BKPRAMLPEN               RCC_AHB4LPENR_BKPRAMLPEN_Msk

+#define RCC_AHB4LPENR_SRAM4LPEN_Pos            (29U)

+#define RCC_AHB4LPENR_SRAM4LPEN_Msk            (0x1UL << RCC_AHB4LPENR_SRAM4LPEN_Pos) /*!< 0x20000000 */

+#define RCC_AHB4LPENR_SRAM4LPEN                RCC_AHB4LPENR_SRAM4LPEN_Msk

+

+/* Legacy define */

+#define RCC_AHB4LPENR_D3SRAM1LPEN_Pos          RCC_AHB4LPENR_SRAM4LPEN_Pos

+#define RCC_AHB4LPENR_D3SRAM1LPEN_Msk          RCC_AHB4LPENR_SRAM4LPEN_Msk

+#define RCC_AHB4LPENR_D3SRAM1LPEN              RCC_AHB4LPENR_SRAM4LPEN

+/********************  Bit definition for RCC_APB3LPENR register  ******************/

+#define RCC_APB3LPENR_LTDCLPEN_Pos             (3U)

+#define RCC_APB3LPENR_LTDCLPEN_Msk             (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB3LPENR_LTDCLPEN                 RCC_APB3LPENR_LTDCLPEN_Msk

+#define RCC_APB3LPENR_WWDG1LPEN_Pos            (6U)

+#define RCC_APB3LPENR_WWDG1LPEN_Msk            (0x1UL << RCC_APB3LPENR_WWDG1LPEN_Pos) /*!< 0x00000040 */

+#define RCC_APB3LPENR_WWDG1LPEN                RCC_APB3LPENR_WWDG1LPEN_Msk

+

+/********************  Bit definition for RCC_APB1LLPENR register  ******************/

+

+#define RCC_APB1LLPENR_TIM2LPEN_Pos            (0U)

+#define RCC_APB1LLPENR_TIM2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */

+#define RCC_APB1LLPENR_TIM2LPEN                RCC_APB1LLPENR_TIM2LPEN_Msk

+#define RCC_APB1LLPENR_TIM3LPEN_Pos            (1U)

+#define RCC_APB1LLPENR_TIM3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1LLPENR_TIM3LPEN                RCC_APB1LLPENR_TIM3LPEN_Msk

+#define RCC_APB1LLPENR_TIM4LPEN_Pos            (2U)

+#define RCC_APB1LLPENR_TIM4LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1LLPENR_TIM4LPEN                RCC_APB1LLPENR_TIM4LPEN_Msk

+#define RCC_APB1LLPENR_TIM5LPEN_Pos            (3U)

+#define RCC_APB1LLPENR_TIM5LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB1LLPENR_TIM5LPEN                RCC_APB1LLPENR_TIM5LPEN_Msk

+#define RCC_APB1LLPENR_TIM6LPEN_Pos            (4U)

+#define RCC_APB1LLPENR_TIM6LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1LLPENR_TIM6LPEN                RCC_APB1LLPENR_TIM6LPEN_Msk

+#define RCC_APB1LLPENR_TIM7LPEN_Pos            (5U)

+#define RCC_APB1LLPENR_TIM7LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1LLPENR_TIM7LPEN                RCC_APB1LLPENR_TIM7LPEN_Msk

+#define RCC_APB1LLPENR_TIM12LPEN_Pos           (6U)

+#define RCC_APB1LLPENR_TIM12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */

+#define RCC_APB1LLPENR_TIM12LPEN               RCC_APB1LLPENR_TIM12LPEN_Msk

+#define RCC_APB1LLPENR_TIM13LPEN_Pos           (7U)

+#define RCC_APB1LLPENR_TIM13LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB1LLPENR_TIM13LPEN               RCC_APB1LLPENR_TIM13LPEN_Msk

+#define RCC_APB1LLPENR_TIM14LPEN_Pos           (8U)

+#define RCC_APB1LLPENR_TIM14LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1LLPENR_TIM14LPEN               RCC_APB1LLPENR_TIM14LPEN_Msk

+#define RCC_APB1LLPENR_LPTIM1LPEN_Pos          (9U)

+#define RCC_APB1LLPENR_LPTIM1LPEN_Msk          (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */

+#define RCC_APB1LLPENR_LPTIM1LPEN              RCC_APB1LLPENR_LPTIM1LPEN_Msk

+

+#define RCC_APB1LLPENR_WWDG2LPEN_Pos           (11U)

+#define RCC_APB1LLPENR_WWDG2LPEN_Msk           (0x1UL << RCC_APB1LLPENR_WWDG2LPEN_Pos) /*!< 0x00000800 */

+#define RCC_APB1LLPENR_WWDG2LPEN               RCC_APB1LLPENR_WWDG2LPEN_Msk

+

+#define RCC_APB1LLPENR_SPI2LPEN_Pos            (14U)

+#define RCC_APB1LLPENR_SPI2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */

+#define RCC_APB1LLPENR_SPI2LPEN                RCC_APB1LLPENR_SPI2LPEN_Msk

+#define RCC_APB1LLPENR_SPI3LPEN_Pos            (15U)

+#define RCC_APB1LLPENR_SPI3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */

+#define RCC_APB1LLPENR_SPI3LPEN                RCC_APB1LLPENR_SPI3LPEN_Msk

+#define RCC_APB1LLPENR_SPDIFRXLPEN_Pos         (16U)

+#define RCC_APB1LLPENR_SPDIFRXLPEN_Msk         (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB1LLPENR_SPDIFRXLPEN             RCC_APB1LLPENR_SPDIFRXLPEN_Msk

+#define RCC_APB1LLPENR_USART2LPEN_Pos          (17U)

+#define RCC_APB1LLPENR_USART2LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */

+#define RCC_APB1LLPENR_USART2LPEN              RCC_APB1LLPENR_USART2LPEN_Msk

+#define RCC_APB1LLPENR_USART3LPEN_Pos          (18U)

+#define RCC_APB1LLPENR_USART3LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */

+#define RCC_APB1LLPENR_USART3LPEN              RCC_APB1LLPENR_USART3LPEN_Msk

+#define RCC_APB1LLPENR_UART4LPEN_Pos           (19U)

+#define RCC_APB1LLPENR_UART4LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */

+#define RCC_APB1LLPENR_UART4LPEN               RCC_APB1LLPENR_UART4LPEN_Msk

+#define RCC_APB1LLPENR_UART5LPEN_Pos           (20U)

+#define RCC_APB1LLPENR_UART5LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */

+#define RCC_APB1LLPENR_UART5LPEN               RCC_APB1LLPENR_UART5LPEN_Msk

+#define RCC_APB1LLPENR_I2C1LPEN_Pos            (21U)

+#define RCC_APB1LLPENR_I2C1LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */

+#define RCC_APB1LLPENR_I2C1LPEN                RCC_APB1LLPENR_I2C1LPEN_Msk

+#define RCC_APB1LLPENR_I2C2LPEN_Pos            (22U)

+#define RCC_APB1LLPENR_I2C2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */

+#define RCC_APB1LLPENR_I2C2LPEN                RCC_APB1LLPENR_I2C2LPEN_Msk

+#define RCC_APB1LLPENR_I2C3LPEN_Pos            (23U)

+#define RCC_APB1LLPENR_I2C3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */

+#define RCC_APB1LLPENR_I2C3LPEN                RCC_APB1LLPENR_I2C3LPEN_Msk

+#define RCC_APB1LLPENR_CECLPEN_Pos             (27U)

+#define RCC_APB1LLPENR_CECLPEN_Msk             (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */

+#define RCC_APB1LLPENR_CECLPEN                 RCC_APB1LLPENR_CECLPEN_Msk

+#define RCC_APB1LLPENR_DAC12LPEN_Pos           (29U)

+#define RCC_APB1LLPENR_DAC12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */

+#define RCC_APB1LLPENR_DAC12LPEN               RCC_APB1LLPENR_DAC12LPEN_Msk

+#define RCC_APB1LLPENR_UART7LPEN_Pos           (30U)

+#define RCC_APB1LLPENR_UART7LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */

+#define RCC_APB1LLPENR_UART7LPEN               RCC_APB1LLPENR_UART7LPEN_Msk

+#define RCC_APB1LLPENR_UART8LPEN_Pos           (31U)

+#define RCC_APB1LLPENR_UART8LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */

+#define RCC_APB1LLPENR_UART8LPEN               RCC_APB1LLPENR_UART8LPEN_Msk

+

+/* Legacy define */

+#define RCC_APB1LLPENR_HDMICECEN_Pos           RCC_APB1LLPENR_CECLPEN_Pos

+#define RCC_APB1LLPENR_HDMICECEN_Msk           RCC_APB1LLPENR_CECLPEN_Msk

+#define RCC_APB1LLPENR_HDMICECEN               RCC_APB1LLPENR_CECLPEN

+/********************  Bit definition for RCC_APB1HLPENR register  ******************/

+#define RCC_APB1HLPENR_CRSLPEN_Pos             (1U)

+#define RCC_APB1HLPENR_CRSLPEN_Msk             (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1HLPENR_CRSLPEN                 RCC_APB1HLPENR_CRSLPEN_Msk

+#define RCC_APB1HLPENR_SWPMILPEN_Pos           (2U)

+#define RCC_APB1HLPENR_SWPMILPEN_Msk           (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1HLPENR_SWPMILPEN               RCC_APB1HLPENR_SWPMILPEN_Msk

+#define RCC_APB1HLPENR_OPAMPLPEN_Pos           (4U)

+#define RCC_APB1HLPENR_OPAMPLPEN_Msk           (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1HLPENR_OPAMPLPEN               RCC_APB1HLPENR_OPAMPLPEN_Msk

+#define RCC_APB1HLPENR_MDIOSLPEN_Pos           (5U)

+#define RCC_APB1HLPENR_MDIOSLPEN_Msk           (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1HLPENR_MDIOSLPEN               RCC_APB1HLPENR_MDIOSLPEN_Msk

+#define RCC_APB1HLPENR_FDCANLPEN_Pos           (8U)

+#define RCC_APB1HLPENR_FDCANLPEN_Msk           (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1HLPENR_FDCANLPEN               RCC_APB1HLPENR_FDCANLPEN_Msk

+

+/********************  Bit definition for RCC_APB2LPENR register  ******************/

+#define RCC_APB2LPENR_TIM1LPEN_Pos             (0U)

+#define RCC_APB2LPENR_TIM1LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */

+#define RCC_APB2LPENR_TIM1LPEN                 RCC_APB2LPENR_TIM1LPEN_Msk

+#define RCC_APB2LPENR_TIM8LPEN_Pos             (1U)

+#define RCC_APB2LPENR_TIM8LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB2LPENR_TIM8LPEN                 RCC_APB2LPENR_TIM8LPEN_Msk

+#define RCC_APB2LPENR_USART1LPEN_Pos           (4U)

+#define RCC_APB2LPENR_USART1LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB2LPENR_USART1LPEN               RCC_APB2LPENR_USART1LPEN_Msk

+#define RCC_APB2LPENR_USART6LPEN_Pos           (5U)

+#define RCC_APB2LPENR_USART6LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB2LPENR_USART6LPEN               RCC_APB2LPENR_USART6LPEN_Msk

+#define RCC_APB2LPENR_SPI1LPEN_Pos             (12U)

+#define RCC_APB2LPENR_SPI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */

+#define RCC_APB2LPENR_SPI1LPEN                 RCC_APB2LPENR_SPI1LPEN_Msk

+#define RCC_APB2LPENR_SPI4LPEN_Pos             (13U)

+#define RCC_APB2LPENR_SPI4LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */

+#define RCC_APB2LPENR_SPI4LPEN                 RCC_APB2LPENR_SPI4LPEN_Msk

+#define RCC_APB2LPENR_TIM15LPEN_Pos            (16U)

+#define RCC_APB2LPENR_TIM15LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB2LPENR_TIM15LPEN                RCC_APB2LPENR_TIM15LPEN_Msk

+#define RCC_APB2LPENR_TIM16LPEN_Pos            (17U)

+#define RCC_APB2LPENR_TIM16LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */

+#define RCC_APB2LPENR_TIM16LPEN                RCC_APB2LPENR_TIM16LPEN_Msk

+#define RCC_APB2LPENR_TIM17LPEN_Pos            (18U)

+#define RCC_APB2LPENR_TIM17LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */

+#define RCC_APB2LPENR_TIM17LPEN                RCC_APB2LPENR_TIM17LPEN_Msk

+#define RCC_APB2LPENR_SPI5LPEN_Pos             (20U)

+#define RCC_APB2LPENR_SPI5LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */

+#define RCC_APB2LPENR_SPI5LPEN                 RCC_APB2LPENR_SPI5LPEN_Msk

+#define RCC_APB2LPENR_SAI1LPEN_Pos             (22U)

+#define RCC_APB2LPENR_SAI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */

+#define RCC_APB2LPENR_SAI1LPEN                 RCC_APB2LPENR_SAI1LPEN_Msk

+#define RCC_APB2LPENR_SAI2LPEN_Pos             (23U)

+#define RCC_APB2LPENR_SAI2LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */

+#define RCC_APB2LPENR_SAI2LPEN                 RCC_APB2LPENR_SAI2LPEN_Msk

+#define RCC_APB2LPENR_SAI3LPEN_Pos             (24U)

+#define RCC_APB2LPENR_SAI3LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI3LPEN_Pos) /*!< 0x01000000 */

+#define RCC_APB2LPENR_SAI3LPEN                 RCC_APB2LPENR_SAI3LPEN_Msk

+#define RCC_APB2LPENR_DFSDM1LPEN_Pos           (28U)

+#define RCC_APB2LPENR_DFSDM1LPEN_Msk           (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x10000000 */

+#define RCC_APB2LPENR_DFSDM1LPEN               RCC_APB2LPENR_DFSDM1LPEN_Msk

+#define RCC_APB2LPENR_HRTIMLPEN_Pos            (29U)

+#define RCC_APB2LPENR_HRTIMLPEN_Msk            (0x1UL << RCC_APB2LPENR_HRTIMLPEN_Pos) /*!< 0x20000000 */

+#define RCC_APB2LPENR_HRTIMLPEN                RCC_APB2LPENR_HRTIMLPEN_Msk

+

+/********************  Bit definition for RCC_APB4LPENR register  ******************/

+#define RCC_APB4LPENR_SYSCFGLPEN_Pos           (1U)

+#define RCC_APB4LPENR_SYSCFGLPEN_Msk           (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB4LPENR_SYSCFGLPEN               RCC_APB4LPENR_SYSCFGLPEN_Msk

+#define RCC_APB4LPENR_LPUART1LPEN_Pos          (3U)

+#define RCC_APB4LPENR_LPUART1LPEN_Msk          (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB4LPENR_LPUART1LPEN              RCC_APB4LPENR_LPUART1LPEN_Msk

+#define RCC_APB4LPENR_SPI6LPEN_Pos             (5U)

+#define RCC_APB4LPENR_SPI6LPEN_Msk             (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB4LPENR_SPI6LPEN                 RCC_APB4LPENR_SPI6LPEN_Msk

+#define RCC_APB4LPENR_I2C4LPEN_Pos             (7U)

+#define RCC_APB4LPENR_I2C4LPEN_Msk             (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB4LPENR_I2C4LPEN                 RCC_APB4LPENR_I2C4LPEN_Msk

+#define RCC_APB4LPENR_LPTIM2LPEN_Pos           (9U)

+#define RCC_APB4LPENR_LPTIM2LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */

+#define RCC_APB4LPENR_LPTIM2LPEN               RCC_APB4LPENR_LPTIM2LPEN_Msk

+#define RCC_APB4LPENR_LPTIM3LPEN_Pos           (10U)

+#define RCC_APB4LPENR_LPTIM3LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */

+#define RCC_APB4LPENR_LPTIM3LPEN               RCC_APB4LPENR_LPTIM3LPEN_Msk

+#define RCC_APB4LPENR_LPTIM4LPEN_Pos           (11U)

+#define RCC_APB4LPENR_LPTIM4LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) /*!< 0x00000800 */

+#define RCC_APB4LPENR_LPTIM4LPEN               RCC_APB4LPENR_LPTIM4LPEN_Msk

+#define RCC_APB4LPENR_LPTIM5LPEN_Pos           (12U)

+#define RCC_APB4LPENR_LPTIM5LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) /*!< 0x00001000 */

+#define RCC_APB4LPENR_LPTIM5LPEN               RCC_APB4LPENR_LPTIM5LPEN_Msk

+#define RCC_APB4LPENR_COMP12LPEN_Pos           (14U)

+#define RCC_APB4LPENR_COMP12LPEN_Msk           (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */

+#define RCC_APB4LPENR_COMP12LPEN               RCC_APB4LPENR_COMP12LPEN_Msk

+#define RCC_APB4LPENR_VREFLPEN_Pos             (15U)

+#define RCC_APB4LPENR_VREFLPEN_Msk             (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */

+#define RCC_APB4LPENR_VREFLPEN                 RCC_APB4LPENR_VREFLPEN_Msk

+#define RCC_APB4LPENR_RTCAPBLPEN_Pos           (16U)

+#define RCC_APB4LPENR_RTCAPBLPEN_Msk           (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB4LPENR_RTCAPBLPEN               RCC_APB4LPENR_RTCAPBLPEN_Msk

+#define RCC_APB4LPENR_SAI4LPEN_Pos             (21U)

+#define RCC_APB4LPENR_SAI4LPEN_Msk             (0x1UL << RCC_APB4LPENR_SAI4LPEN_Pos) /*!< 0x00200000 */

+#define RCC_APB4LPENR_SAI4LPEN                 RCC_APB4LPENR_SAI4LPEN_Msk

+

+

+/********************  Bit definition for RCC_RSR register  *******************/

+#define RCC_RSR_RMVF_Pos                       (16U)

+#define RCC_RSR_RMVF_Msk                       (0x1UL << RCC_RSR_RMVF_Pos)     /*!< 0x00010000 */

+#define RCC_RSR_RMVF                           RCC_RSR_RMVF_Msk

+#define RCC_RSR_C1RSTF_Pos                     (17U)

+#define RCC_RSR_C1RSTF_Msk                     (0x1UL << RCC_RSR_C1RSTF_Pos)   /*!< 0x00020000 */

+#define RCC_RSR_C1RSTF                         RCC_RSR_C1RSTF_Msk

+#define RCC_RSR_D1RSTF_Pos                     (19U)

+#define RCC_RSR_D1RSTF_Msk                     (0x1UL << RCC_RSR_D1RSTF_Pos)   /*!< 0x00080000 */

+#define RCC_RSR_D1RSTF                         RCC_RSR_D1RSTF_Msk

+#define RCC_RSR_D2RSTF_Pos                     (20U)

+#define RCC_RSR_D2RSTF_Msk                     (0x1UL << RCC_RSR_D2RSTF_Pos)   /*!< 0x00100000 */

+#define RCC_RSR_D2RSTF                         RCC_RSR_D2RSTF_Msk

+#define RCC_RSR_BORRSTF_Pos                    (21U)

+#define RCC_RSR_BORRSTF_Msk                    (0x1UL << RCC_RSR_BORRSTF_Pos)  /*!< 0x00200000 */

+#define RCC_RSR_BORRSTF                        RCC_RSR_BORRSTF_Msk

+#define RCC_RSR_PINRSTF_Pos                    (22U)

+#define RCC_RSR_PINRSTF_Msk                    (0x1UL << RCC_RSR_PINRSTF_Pos)  /*!< 0x00400000 */

+#define RCC_RSR_PINRSTF                        RCC_RSR_PINRSTF_Msk

+#define RCC_RSR_PORRSTF_Pos                    (23U)

+#define RCC_RSR_PORRSTF_Msk                    (0x1UL << RCC_RSR_PORRSTF_Pos)  /*!< 0x00800000 */

+#define RCC_RSR_PORRSTF                        RCC_RSR_PORRSTF_Msk

+#define RCC_RSR_SFT1RSTF_Pos                   (24U)

+#define RCC_RSR_SFT1RSTF_Msk                   (0x1UL << RCC_RSR_SFT1RSTF_Pos) /*!< 0x01000000 */

+#define RCC_RSR_SFT1RSTF                       RCC_RSR_SFT1RSTF_Msk

+#define RCC_RSR_IWDG1RSTF_Pos                  (26U)

+#define RCC_RSR_IWDG1RSTF_Msk                  (0x1UL << RCC_RSR_IWDG1RSTF_Pos) /*!< 0x04000000 */

+#define RCC_RSR_IWDG1RSTF                      RCC_RSR_IWDG1RSTF_Msk

+#define RCC_RSR_WWDG1RSTF_Pos                  (28U)

+#define RCC_RSR_WWDG1RSTF_Msk                  (0x1UL << RCC_RSR_WWDG1RSTF_Pos) /*!< 0x10000000 */

+#define RCC_RSR_WWDG1RSTF                      RCC_RSR_WWDG1RSTF_Msk

+

+#define RCC_RSR_WWDG2RSTF_Pos                  (29U)

+#define RCC_RSR_WWDG2RSTF_Msk                  (0x1UL << RCC_RSR_WWDG2RSTF_Pos) /*!< 0x20000000 */

+#define RCC_RSR_WWDG2RSTF                      RCC_RSR_WWDG2RSTF_Msk

+#define RCC_RSR_IWDG2RSTF_Pos                  (27U)

+#define RCC_RSR_IWDG2RSTF_Msk                  (0x1UL << RCC_RSR_IWDG2RSTF_Pos) /*!< 0x08000000 */

+#define RCC_RSR_IWDG2RSTF                      RCC_RSR_IWDG2RSTF_Msk

+#define RCC_RSR_SFT2RSTF_Pos                   (25U)

+#define RCC_RSR_SFT2RSTF_Msk                   (0x1UL << RCC_RSR_SFT2RSTF_Pos) /*!< 0x02000000 */

+#define RCC_RSR_SFT2RSTF                       RCC_RSR_SFT2RSTF_Msk

+#define RCC_RSR_C2RSTF_Pos                     (18U)

+#define RCC_RSR_C2RSTF_Msk                     (0x1UL << RCC_RSR_C2RSTF_Pos)   /*!< 0x00040000 */

+#define RCC_RSR_C2RSTF                         RCC_RSR_C2RSTF_Msk

+#define RCC_RSR_LPWR1RSTF_Pos                  (30U)

+#define RCC_RSR_LPWR1RSTF_Msk                  (0x1UL << RCC_RSR_LPWR1RSTF_Pos) /*!< 0x40000000 */

+#define RCC_RSR_LPWR1RSTF                      RCC_RSR_LPWR1RSTF_Msk

+#define RCC_RSR_LPWR2RSTF_Pos                  (31U)

+#define RCC_RSR_LPWR2RSTF_Msk                  (0x1UL << RCC_RSR_LPWR2RSTF_Pos) /*!< 0x80000000 */

+#define RCC_RSR_LPWR2RSTF                      RCC_RSR_LPWR2RSTF_Msk

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    RNG                                     */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for RNG_CR register  *******************/

+#define RNG_CR_RNGEN_Pos    (2U)

+#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */

+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk

+#define RNG_CR_IE_Pos       (3U)

+#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */

+#define RNG_CR_IE           RNG_CR_IE_Msk

+#define RNG_CR_CED_Pos      (5U)

+#define RNG_CR_CED_Msk      (0x1UL << RNG_CR_CED_Pos)                          /*!< 0x00000020 */

+#define RNG_CR_CED          RNG_CR_CED_Msk

+

+/********************  Bits definition for RNG_SR register  *******************/

+#define RNG_SR_DRDY_Pos     (0U)

+#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */

+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk

+#define RNG_SR_CECS_Pos     (1U)

+#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */

+#define RNG_SR_CECS         RNG_SR_CECS_Msk

+#define RNG_SR_SECS_Pos     (2U)

+#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */

+#define RNG_SR_SECS         RNG_SR_SECS_Msk

+#define RNG_SR_CEIS_Pos     (5U)

+#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */

+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk

+#define RNG_SR_SEIS_Pos     (6U)

+#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */

+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                           Real-Time Clock (RTC)                            */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for RTC_TR register  *******************/

+#define RTC_TR_PM_Pos                  (22U)

+#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */

+#define RTC_TR_PM                      RTC_TR_PM_Msk

+#define RTC_TR_HT_Pos                  (20U)

+#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */

+#define RTC_TR_HT                      RTC_TR_HT_Msk

+#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */

+#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */

+#define RTC_TR_HU_Pos                  (16U)

+#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */

+#define RTC_TR_HU                      RTC_TR_HU_Msk

+#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */

+#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */

+#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */

+#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */

+#define RTC_TR_MNT_Pos                 (12U)

+#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */

+#define RTC_TR_MNT                     RTC_TR_MNT_Msk

+#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */

+#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */

+#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */

+#define RTC_TR_MNU_Pos                 (8U)

+#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */

+#define RTC_TR_MNU                     RTC_TR_MNU_Msk

+#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */

+#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */

+#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */

+#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */

+#define RTC_TR_ST_Pos                  (4U)

+#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */

+#define RTC_TR_ST                      RTC_TR_ST_Msk

+#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */

+#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */

+#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */

+#define RTC_TR_SU_Pos                  (0U)

+#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */

+#define RTC_TR_SU                      RTC_TR_SU_Msk

+#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */

+#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */

+#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */

+#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_DR register  *******************/

+#define RTC_DR_YT_Pos                  (20U)

+#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */

+#define RTC_DR_YT                      RTC_DR_YT_Msk

+#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */

+#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */

+#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */

+#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */

+#define RTC_DR_YU_Pos                  (16U)

+#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */

+#define RTC_DR_YU                      RTC_DR_YU_Msk

+#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */

+#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */

+#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */

+#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */

+#define RTC_DR_WDU_Pos                 (13U)

+#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */

+#define RTC_DR_WDU                     RTC_DR_WDU_Msk

+#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */

+#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */

+#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */

+#define RTC_DR_MT_Pos                  (12U)

+#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */

+#define RTC_DR_MT                      RTC_DR_MT_Msk

+#define RTC_DR_MU_Pos                  (8U)

+#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */

+#define RTC_DR_MU                      RTC_DR_MU_Msk

+#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */

+#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */

+#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */

+#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */

+#define RTC_DR_DT_Pos                  (4U)

+#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */

+#define RTC_DR_DT                      RTC_DR_DT_Msk

+#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */

+#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */

+#define RTC_DR_DU_Pos                  (0U)

+#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */

+#define RTC_DR_DU                      RTC_DR_DU_Msk

+#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */

+#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */

+#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */

+#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_CR register  *******************/

+#define RTC_CR_ITSE_Pos                (24U)

+#define RTC_CR_ITSE_Msk                (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */

+#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk

+#define RTC_CR_COE_Pos                 (23U)

+#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */

+#define RTC_CR_COE                     RTC_CR_COE_Msk

+#define RTC_CR_OSEL_Pos                (21U)

+#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */

+#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk

+#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */

+#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */

+#define RTC_CR_POL_Pos                 (20U)

+#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */

+#define RTC_CR_POL                     RTC_CR_POL_Msk

+#define RTC_CR_COSEL_Pos               (19U)

+#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */

+#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk

+#define RTC_CR_BKP_Pos                 (18U)

+#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */

+#define RTC_CR_BKP                     RTC_CR_BKP_Msk

+#define RTC_CR_SUB1H_Pos               (17U)

+#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */

+#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk

+#define RTC_CR_ADD1H_Pos               (16U)

+#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */

+#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk

+#define RTC_CR_TSIE_Pos                (15U)

+#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */

+#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk

+#define RTC_CR_WUTIE_Pos               (14U)

+#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */

+#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk

+#define RTC_CR_ALRBIE_Pos              (13U)

+#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */

+#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk

+#define RTC_CR_ALRAIE_Pos              (12U)

+#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */

+#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk

+#define RTC_CR_TSE_Pos                 (11U)

+#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */

+#define RTC_CR_TSE                     RTC_CR_TSE_Msk

+#define RTC_CR_WUTE_Pos                (10U)

+#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */

+#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk

+#define RTC_CR_ALRBE_Pos               (9U)

+#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */

+#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk

+#define RTC_CR_ALRAE_Pos               (8U)

+#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */

+#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk

+#define RTC_CR_FMT_Pos                 (6U)

+#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */

+#define RTC_CR_FMT                     RTC_CR_FMT_Msk

+#define RTC_CR_BYPSHAD_Pos             (5U)

+#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */

+#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk

+#define RTC_CR_REFCKON_Pos             (4U)

+#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */

+#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk

+#define RTC_CR_TSEDGE_Pos              (3U)

+#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */

+#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk

+#define RTC_CR_WUCKSEL_Pos             (0U)

+#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */

+#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk

+#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */

+#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */

+#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */

+

+/********************  Bits definition for RTC_ISR register  ******************/

+#define RTC_ISR_ITSF_Pos               (17U)

+#define RTC_ISR_ITSF_Msk               (0x1UL << RTC_ISR_ITSF_Pos)             /*!< 0x00020000 */

+#define RTC_ISR_ITSF                   RTC_ISR_ITSF_Msk

+#define RTC_ISR_RECALPF_Pos            (16U)

+#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)          /*!< 0x00010000 */

+#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk

+#define RTC_ISR_TAMP3F_Pos             (15U)

+#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)           /*!< 0x00008000 */

+#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk

+#define RTC_ISR_TAMP2F_Pos             (14U)

+#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)           /*!< 0x00004000 */

+#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk

+#define RTC_ISR_TAMP1F_Pos             (13U)

+#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)           /*!< 0x00002000 */

+#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk

+#define RTC_ISR_TSOVF_Pos              (12U)

+#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)            /*!< 0x00001000 */

+#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk

+#define RTC_ISR_TSF_Pos                (11U)

+#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)              /*!< 0x00000800 */

+#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk

+#define RTC_ISR_WUTF_Pos               (10U)

+#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)             /*!< 0x00000400 */

+#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk

+#define RTC_ISR_ALRBF_Pos              (9U)

+#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)            /*!< 0x00000200 */

+#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk

+#define RTC_ISR_ALRAF_Pos              (8U)

+#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)            /*!< 0x00000100 */

+#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk

+#define RTC_ISR_INIT_Pos               (7U)

+#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)             /*!< 0x00000080 */

+#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk

+#define RTC_ISR_INITF_Pos              (6U)

+#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)            /*!< 0x00000040 */

+#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk

+#define RTC_ISR_RSF_Pos                (5U)

+#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)              /*!< 0x00000020 */

+#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk

+#define RTC_ISR_INITS_Pos              (4U)

+#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)            /*!< 0x00000010 */

+#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk

+#define RTC_ISR_SHPF_Pos               (3U)

+#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)             /*!< 0x00000008 */

+#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk

+#define RTC_ISR_WUTWF_Pos              (2U)

+#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)            /*!< 0x00000004 */

+#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk

+#define RTC_ISR_ALRBWF_Pos             (1U)

+#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)           /*!< 0x00000002 */

+#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk

+#define RTC_ISR_ALRAWF_Pos             (0U)

+#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)           /*!< 0x00000001 */

+#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk

+

+/********************  Bits definition for RTC_PRER register  *****************/

+#define RTC_PRER_PREDIV_A_Pos          (16U)

+#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */

+#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk

+#define RTC_PRER_PREDIV_S_Pos          (0U)

+#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */

+#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk

+

+/********************  Bits definition for RTC_WUTR register  *****************/

+#define RTC_WUTR_WUT_Pos               (0U)

+#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */

+#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk

+

+/********************  Bits definition for RTC_ALRMAR register  ***************/

+#define RTC_ALRMAR_MSK4_Pos            (31U)

+#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */

+#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk

+#define RTC_ALRMAR_WDSEL_Pos           (30U)

+#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */

+#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk

+#define RTC_ALRMAR_DT_Pos              (28U)

+#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */

+#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk

+#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */

+#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */

+#define RTC_ALRMAR_DU_Pos              (24U)

+#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */

+#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk

+#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */

+#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */

+#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */

+#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */

+#define RTC_ALRMAR_MSK3_Pos            (23U)

+#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */

+#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk

+#define RTC_ALRMAR_PM_Pos              (22U)

+#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */

+#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk

+#define RTC_ALRMAR_HT_Pos              (20U)

+#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */

+#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk

+#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */

+#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */

+#define RTC_ALRMAR_HU_Pos              (16U)

+#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */

+#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk

+#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */

+#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */

+#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */

+#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */

+#define RTC_ALRMAR_MSK2_Pos            (15U)

+#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */

+#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk

+#define RTC_ALRMAR_MNT_Pos             (12U)

+#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */

+#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk

+#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */

+#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */

+#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */

+#define RTC_ALRMAR_MNU_Pos             (8U)

+#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */

+#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk

+#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */

+#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */

+#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */

+#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */

+#define RTC_ALRMAR_MSK1_Pos            (7U)

+#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */

+#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk

+#define RTC_ALRMAR_ST_Pos              (4U)

+#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */

+#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk

+#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */

+#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */

+#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */

+#define RTC_ALRMAR_SU_Pos              (0U)

+#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */

+#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk

+#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */

+#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */

+#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */

+#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_ALRMBR register  ***************/

+#define RTC_ALRMBR_MSK4_Pos            (31U)

+#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */

+#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk

+#define RTC_ALRMBR_WDSEL_Pos           (30U)

+#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */

+#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk

+#define RTC_ALRMBR_DT_Pos              (28U)

+#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */

+#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk

+#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */

+#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */

+#define RTC_ALRMBR_DU_Pos              (24U)

+#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */

+#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk

+#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */

+#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */

+#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */

+#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */

+#define RTC_ALRMBR_MSK3_Pos            (23U)

+#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */

+#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk

+#define RTC_ALRMBR_PM_Pos              (22U)

+#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */

+#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk

+#define RTC_ALRMBR_HT_Pos              (20U)

+#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */

+#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk

+#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */

+#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */

+#define RTC_ALRMBR_HU_Pos              (16U)

+#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */

+#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk

+#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */

+#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */

+#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */

+#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */

+#define RTC_ALRMBR_MSK2_Pos            (15U)

+#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */

+#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk

+#define RTC_ALRMBR_MNT_Pos             (12U)

+#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */

+#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk

+#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */

+#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */

+#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */

+#define RTC_ALRMBR_MNU_Pos             (8U)

+#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */

+#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk

+#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */

+#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */

+#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */

+#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */

+#define RTC_ALRMBR_MSK1_Pos            (7U)

+#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */

+#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk

+#define RTC_ALRMBR_ST_Pos              (4U)

+#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */

+#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk

+#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */

+#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */

+#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */

+#define RTC_ALRMBR_SU_Pos              (0U)

+#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */

+#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk

+#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */

+#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */

+#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */

+#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_WPR register  ******************/

+#define RTC_WPR_KEY_Pos                (0U)

+#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */

+#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk

+

+/********************  Bits definition for RTC_SSR register  ******************/

+#define RTC_SSR_SS_Pos                 (0U)

+#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)            /*!< 0x0000FFFF */

+#define RTC_SSR_SS                     RTC_SSR_SS_Msk

+

+/********************  Bits definition for RTC_SHIFTR register  ***************/

+#define RTC_SHIFTR_SUBFS_Pos           (0U)

+#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */

+#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk

+#define RTC_SHIFTR_ADD1S_Pos           (31U)

+#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */

+#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk

+

+/********************  Bits definition for RTC_TSTR register  *****************/

+#define RTC_TSTR_PM_Pos                (22U)

+#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */

+#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk

+#define RTC_TSTR_HT_Pos                (20U)

+#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */

+#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk

+#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */

+#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */

+#define RTC_TSTR_HU_Pos                (16U)

+#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */

+#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk

+#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */

+#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */

+#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */

+#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */

+#define RTC_TSTR_MNT_Pos               (12U)

+#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */

+#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk

+#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */

+#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */

+#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */

+#define RTC_TSTR_MNU_Pos               (8U)

+#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */

+#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk

+#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */

+#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */

+#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */

+#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */

+#define RTC_TSTR_ST_Pos                (4U)

+#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */

+#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk

+#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */

+#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */

+#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */

+#define RTC_TSTR_SU_Pos                (0U)

+#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */

+#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk

+#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */

+#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */

+#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */

+#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_TSDR register  *****************/

+#define RTC_TSDR_WDU_Pos               (13U)

+#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */

+#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk

+#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */

+#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */

+#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */

+#define RTC_TSDR_MT_Pos                (12U)

+#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */

+#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk

+#define RTC_TSDR_MU_Pos                (8U)

+#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */

+#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk

+#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */

+#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */

+#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */

+#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */

+#define RTC_TSDR_DT_Pos                (4U)

+#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */

+#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk

+#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */

+#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */

+#define RTC_TSDR_DU_Pos                (0U)

+#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */

+#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk

+#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */

+#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */

+#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */

+#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_TSSSR register  ****************/

+#define RTC_TSSSR_SS_Pos               (0U)

+#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)          /*!< 0x0000FFFF */

+#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk

+

+/********************  Bits definition for RTC_CALR register  *****************/

+#define RTC_CALR_CALP_Pos              (15U)

+#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */

+#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk

+#define RTC_CALR_CALW8_Pos             (14U)

+#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */

+#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk

+#define RTC_CALR_CALW16_Pos            (13U)

+#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */

+#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk

+#define RTC_CALR_CALM_Pos              (0U)

+#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */

+#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk

+#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */

+#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */

+#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */

+#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */

+#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */

+#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */

+#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */

+#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */

+#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */

+

+/********************  Bits definition for RTC_TAMPCR register  ***************/

+#define RTC_TAMPCR_TAMP3MF_Pos         (24U)

+#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)       /*!< 0x01000000 */

+#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk

+#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)

+#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)  /*!< 0x00800000 */

+#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk

+#define RTC_TAMPCR_TAMP3IE_Pos         (22U)

+#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)       /*!< 0x00400000 */

+#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk

+#define RTC_TAMPCR_TAMP2MF_Pos         (21U)

+#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)       /*!< 0x00200000 */

+#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk

+#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)

+#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)  /*!< 0x00100000 */

+#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk

+#define RTC_TAMPCR_TAMP2IE_Pos         (19U)

+#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)       /*!< 0x00080000 */

+#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk

+#define RTC_TAMPCR_TAMP1MF_Pos         (18U)

+#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)       /*!< 0x00040000 */

+#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk

+#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)

+#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)  /*!< 0x00020000 */

+#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk

+#define RTC_TAMPCR_TAMP1IE_Pos         (16U)

+#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)       /*!< 0x00010000 */

+#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk

+#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)

+#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)     /*!< 0x00008000 */

+#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk

+#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)

+#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)      /*!< 0x00006000 */

+#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk

+#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */

+#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */

+#define RTC_TAMPCR_TAMPFLT_Pos         (11U)

+#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)       /*!< 0x00001800 */

+#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk

+#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */

+#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */

+#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)

+#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)      /*!< 0x00000700 */

+#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk

+#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */

+#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */

+#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */

+#define RTC_TAMPCR_TAMPTS_Pos          (7U)

+#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)        /*!< 0x00000080 */

+#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk

+#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)

+#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)      /*!< 0x00000040 */

+#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk

+#define RTC_TAMPCR_TAMP3E_Pos          (5U)

+#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)        /*!< 0x00000020 */

+#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk

+#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)

+#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)      /*!< 0x00000010 */

+#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk

+#define RTC_TAMPCR_TAMP2E_Pos          (3U)

+#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)        /*!< 0x00000008 */

+#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk

+#define RTC_TAMPCR_TAMPIE_Pos          (2U)

+#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)        /*!< 0x00000004 */

+#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk

+#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)

+#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)      /*!< 0x00000002 */

+#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk

+#define RTC_TAMPCR_TAMP1E_Pos          (0U)

+#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)        /*!< 0x00000001 */

+#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk

+

+/********************  Bits definition for RTC_ALRMASSR register  *************/

+#define RTC_ALRMASSR_MASKSS_Pos        (24U)

+#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x0F000000 */

+#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk

+#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */

+#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */

+#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */

+#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */

+#define RTC_ALRMASSR_SS_Pos            (0U)

+#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */

+#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk

+

+/********************  Bits definition for RTC_ALRMBSSR register  *************/

+#define RTC_ALRMBSSR_MASKSS_Pos        (24U)

+#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x0F000000 */

+#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk

+#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */

+#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */

+#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */

+#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */

+#define RTC_ALRMBSSR_SS_Pos            (0U)

+#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */

+#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk

+

+/********************  Bits definition for RTC_OR register  *******************/

+#define RTC_OR_OUT_RMP_Pos             (1U)

+#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)           /*!< 0x00000002 */

+#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk

+#define RTC_OR_ALARMOUTTYPE_Pos        (0U)

+#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)      /*!< 0x00000001 */

+#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk

+

+/********************  Bits definition for RTC_BKP0R register  ****************/

+#define RTC_BKP0R_Pos                  (0U)

+#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP0R                      RTC_BKP0R_Msk

+

+/********************  Bits definition for RTC_BKP1R register  ****************/

+#define RTC_BKP1R_Pos                  (0U)

+#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP1R                      RTC_BKP1R_Msk

+

+/********************  Bits definition for RTC_BKP2R register  ****************/

+#define RTC_BKP2R_Pos                  (0U)

+#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP2R                      RTC_BKP2R_Msk

+

+/********************  Bits definition for RTC_BKP3R register  ****************/

+#define RTC_BKP3R_Pos                  (0U)

+#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP3R                      RTC_BKP3R_Msk

+

+/********************  Bits definition for RTC_BKP4R register  ****************/

+#define RTC_BKP4R_Pos                  (0U)

+#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP4R                      RTC_BKP4R_Msk

+

+/********************  Bits definition for RTC_BKP5R register  ****************/

+#define RTC_BKP5R_Pos                  (0U)

+#define RTC_BKP5R_Msk                  (0xFFFFFFFFUL << RTC_BKP5R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP5R                      RTC_BKP5R_Msk

+

+/********************  Bits definition for RTC_BKP6R register  ****************/

+#define RTC_BKP6R_Pos                  (0U)

+#define RTC_BKP6R_Msk                  (0xFFFFFFFFUL << RTC_BKP6R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP6R                      RTC_BKP6R_Msk

+

+/********************  Bits definition for RTC_BKP7R register  ****************/

+#define RTC_BKP7R_Pos                  (0U)

+#define RTC_BKP7R_Msk                  (0xFFFFFFFFUL << RTC_BKP7R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP7R                      RTC_BKP7R_Msk

+

+/********************  Bits definition for RTC_BKP8R register  ****************/

+#define RTC_BKP8R_Pos                  (0U)

+#define RTC_BKP8R_Msk                  (0xFFFFFFFFUL << RTC_BKP8R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP8R                      RTC_BKP8R_Msk

+

+/********************  Bits definition for RTC_BKP9R register  ****************/

+#define RTC_BKP9R_Pos                  (0U)

+#define RTC_BKP9R_Msk                  (0xFFFFFFFFUL << RTC_BKP9R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP9R                      RTC_BKP9R_Msk

+

+/********************  Bits definition for RTC_BKP10R register  ***************/

+#define RTC_BKP10R_Pos                 (0U)

+#define RTC_BKP10R_Msk                 (0xFFFFFFFFUL << RTC_BKP10R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP10R                     RTC_BKP10R_Msk

+

+/********************  Bits definition for RTC_BKP11R register  ***************/

+#define RTC_BKP11R_Pos                 (0U)

+#define RTC_BKP11R_Msk                 (0xFFFFFFFFUL << RTC_BKP11R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP11R                     RTC_BKP11R_Msk

+

+/********************  Bits definition for RTC_BKP12R register  ***************/

+#define RTC_BKP12R_Pos                 (0U)

+#define RTC_BKP12R_Msk                 (0xFFFFFFFFUL << RTC_BKP12R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP12R                     RTC_BKP12R_Msk

+

+/********************  Bits definition for RTC_BKP13R register  ***************/

+#define RTC_BKP13R_Pos                 (0U)

+#define RTC_BKP13R_Msk                 (0xFFFFFFFFUL << RTC_BKP13R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP13R                     RTC_BKP13R_Msk

+

+/********************  Bits definition for RTC_BKP14R register  ***************/

+#define RTC_BKP14R_Pos                 (0U)

+#define RTC_BKP14R_Msk                 (0xFFFFFFFFUL << RTC_BKP14R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP14R                     RTC_BKP14R_Msk

+

+/********************  Bits definition for RTC_BKP15R register  ***************/

+#define RTC_BKP15R_Pos                 (0U)

+#define RTC_BKP15R_Msk                 (0xFFFFFFFFUL << RTC_BKP15R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP15R                     RTC_BKP15R_Msk

+

+/********************  Bits definition for RTC_BKP16R register  ***************/

+#define RTC_BKP16R_Pos                 (0U)

+#define RTC_BKP16R_Msk                 (0xFFFFFFFFUL << RTC_BKP16R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP16R                     RTC_BKP16R_Msk

+

+/********************  Bits definition for RTC_BKP17R register  ***************/

+#define RTC_BKP17R_Pos                 (0U)

+#define RTC_BKP17R_Msk                 (0xFFFFFFFFUL << RTC_BKP17R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP17R                     RTC_BKP17R_Msk

+

+/********************  Bits definition for RTC_BKP18R register  ***************/

+#define RTC_BKP18R_Pos                 (0U)

+#define RTC_BKP18R_Msk                 (0xFFFFFFFFUL << RTC_BKP18R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP18R                     RTC_BKP18R_Msk

+

+/********************  Bits definition for RTC_BKP19R register  ***************/

+#define RTC_BKP19R_Pos                 (0U)

+#define RTC_BKP19R_Msk                 (0xFFFFFFFFUL << RTC_BKP19R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP19R                     RTC_BKP19R_Msk

+

+/********************  Bits definition for RTC_BKP20R register  ***************/

+#define RTC_BKP20R_Pos                 (0U)

+#define RTC_BKP20R_Msk                 (0xFFFFFFFFUL << RTC_BKP20R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP20R                     RTC_BKP20R_Msk

+

+/********************  Bits definition for RTC_BKP21R register  ***************/

+#define RTC_BKP21R_Pos                 (0U)

+#define RTC_BKP21R_Msk                 (0xFFFFFFFFUL << RTC_BKP21R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP21R                     RTC_BKP21R_Msk

+

+/********************  Bits definition for RTC_BKP22R register  ***************/

+#define RTC_BKP22R_Pos                 (0U)

+#define RTC_BKP22R_Msk                 (0xFFFFFFFFUL << RTC_BKP22R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP22R                     RTC_BKP22R_Msk

+

+/********************  Bits definition for RTC_BKP23R register  ***************/

+#define RTC_BKP23R_Pos                 (0U)

+#define RTC_BKP23R_Msk                 (0xFFFFFFFFUL << RTC_BKP23R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP23R                     RTC_BKP23R_Msk

+

+/********************  Bits definition for RTC_BKP24R register  ***************/

+#define RTC_BKP24R_Pos                 (0U)

+#define RTC_BKP24R_Msk                 (0xFFFFFFFFUL << RTC_BKP24R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP24R                     RTC_BKP24R_Msk

+

+/********************  Bits definition for RTC_BKP25R register  ***************/

+#define RTC_BKP25R_Pos                 (0U)

+#define RTC_BKP25R_Msk                 (0xFFFFFFFFUL << RTC_BKP25R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP25R                     RTC_BKP25R_Msk

+

+/********************  Bits definition for RTC_BKP26R register  ***************/

+#define RTC_BKP26R_Pos                 (0U)

+#define RTC_BKP26R_Msk                 (0xFFFFFFFFUL << RTC_BKP26R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP26R                     RTC_BKP26R_Msk

+

+/********************  Bits definition for RTC_BKP27R register  ***************/

+#define RTC_BKP27R_Pos                 (0U)

+#define RTC_BKP27R_Msk                 (0xFFFFFFFFUL << RTC_BKP27R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP27R                     RTC_BKP27R_Msk

+

+/********************  Bits definition for RTC_BKP28R register  ***************/

+#define RTC_BKP28R_Pos                 (0U)

+#define RTC_BKP28R_Msk                 (0xFFFFFFFFUL << RTC_BKP28R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP28R                     RTC_BKP28R_Msk

+

+/********************  Bits definition for RTC_BKP29R register  ***************/

+#define RTC_BKP29R_Pos                 (0U)

+#define RTC_BKP29R_Msk                 (0xFFFFFFFFUL << RTC_BKP29R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP29R                     RTC_BKP29R_Msk

+

+/********************  Bits definition for RTC_BKP30R register  ***************/

+#define RTC_BKP30R_Pos                 (0U)

+#define RTC_BKP30R_Msk                 (0xFFFFFFFFUL << RTC_BKP30R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP30R                     RTC_BKP30R_Msk

+

+/********************  Bits definition for RTC_BKP31R register  ***************/

+#define RTC_BKP31R_Pos                 (0U)

+#define RTC_BKP31R_Msk                 (0xFFFFFFFFUL << RTC_BKP31R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP31R                     RTC_BKP31R_Msk

+

+/******************** Number of backup registers ******************************/

+#define RTC_BKP_NUMBER_Pos             (5U)

+#define RTC_BKP_NUMBER_Msk             (0x1UL << RTC_BKP_NUMBER_Pos)           /*!< 0x00000020 */

+#define RTC_BKP_NUMBER                 RTC_BKP_NUMBER_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                              SPDIF-RX Interface                            */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for SPDIF_CR register  ******************/

+#define SPDIFRX_CR_SPDIFEN_Pos      (0U)

+#define SPDIFRX_CR_SPDIFEN_Msk      (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)          /*!< 0x00000003 */

+#define SPDIFRX_CR_SPDIFEN          SPDIFRX_CR_SPDIFEN_Msk                     /*!<Peripheral Block Enable                      */

+#define SPDIFRX_CR_RXDMAEN_Pos      (2U)

+#define SPDIFRX_CR_RXDMAEN_Msk      (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)          /*!< 0x00000004 */

+#define SPDIFRX_CR_RXDMAEN          SPDIFRX_CR_RXDMAEN_Msk                     /*!<Receiver DMA Enable for data flow            */

+#define SPDIFRX_CR_RXSTEO_Pos       (3U)

+#define SPDIFRX_CR_RXSTEO_Msk       (0x1UL << SPDIFRX_CR_RXSTEO_Pos)           /*!< 0x00000008 */

+#define SPDIFRX_CR_RXSTEO           SPDIFRX_CR_RXSTEO_Msk                      /*!<Stereo Mode                                  */

+#define SPDIFRX_CR_DRFMT_Pos        (4U)

+#define SPDIFRX_CR_DRFMT_Msk        (0x3UL << SPDIFRX_CR_DRFMT_Pos)            /*!< 0x00000030 */

+#define SPDIFRX_CR_DRFMT            SPDIFRX_CR_DRFMT_Msk                       /*!<RX Data format                               */

+#define SPDIFRX_CR_PMSK_Pos         (6U)

+#define SPDIFRX_CR_PMSK_Msk         (0x1UL << SPDIFRX_CR_PMSK_Pos)             /*!< 0x00000040 */

+#define SPDIFRX_CR_PMSK             SPDIFRX_CR_PMSK_Msk                        /*!<Mask Parity error bit                        */

+#define SPDIFRX_CR_VMSK_Pos         (7U)

+#define SPDIFRX_CR_VMSK_Msk         (0x1UL << SPDIFRX_CR_VMSK_Pos)             /*!< 0x00000080 */

+#define SPDIFRX_CR_VMSK             SPDIFRX_CR_VMSK_Msk                        /*!<Mask of Validity bit                         */

+#define SPDIFRX_CR_CUMSK_Pos        (8U)

+#define SPDIFRX_CR_CUMSK_Msk        (0x1UL << SPDIFRX_CR_CUMSK_Pos)            /*!< 0x00000100 */

+#define SPDIFRX_CR_CUMSK            SPDIFRX_CR_CUMSK_Msk                       /*!<Mask of channel status and user bits         */

+#define SPDIFRX_CR_PTMSK_Pos        (9U)

+#define SPDIFRX_CR_PTMSK_Msk        (0x1UL << SPDIFRX_CR_PTMSK_Pos)            /*!< 0x00000200 */

+#define SPDIFRX_CR_PTMSK            SPDIFRX_CR_PTMSK_Msk                       /*!<Mask of Preamble Type bits                   */

+#define SPDIFRX_CR_CBDMAEN_Pos      (10U)

+#define SPDIFRX_CR_CBDMAEN_Msk      (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)          /*!< 0x00000400 */

+#define SPDIFRX_CR_CBDMAEN          SPDIFRX_CR_CBDMAEN_Msk                     /*!<Control Buffer DMA ENable for control flow   */

+#define SPDIFRX_CR_CHSEL_Pos        (11U)

+#define SPDIFRX_CR_CHSEL_Msk        (0x1UL << SPDIFRX_CR_CHSEL_Pos)            /*!< 0x00000800 */

+#define SPDIFRX_CR_CHSEL            SPDIFRX_CR_CHSEL_Msk                       /*!<Channel Selection                            */

+#define SPDIFRX_CR_NBTR_Pos         (12U)

+#define SPDIFRX_CR_NBTR_Msk         (0x3UL << SPDIFRX_CR_NBTR_Pos)             /*!< 0x00003000 */

+#define SPDIFRX_CR_NBTR             SPDIFRX_CR_NBTR_Msk                        /*!<Maximum allowed re-tries during synchronization phase */

+#define SPDIFRX_CR_WFA_Pos          (14U)

+#define SPDIFRX_CR_WFA_Msk          (0x1UL << SPDIFRX_CR_WFA_Pos)              /*!< 0x00004000 */

+#define SPDIFRX_CR_WFA              SPDIFRX_CR_WFA_Msk                         /*!<Wait For Activity     */

+#define SPDIFRX_CR_INSEL_Pos        (16U)

+#define SPDIFRX_CR_INSEL_Msk        (0x7UL << SPDIFRX_CR_INSEL_Pos)            /*!< 0x00070000 */

+#define SPDIFRX_CR_INSEL            SPDIFRX_CR_INSEL_Msk                       /*!<SPDIF input selection */

+#define SPDIFRX_CR_CKSEN_Pos        (20U)

+#define SPDIFRX_CR_CKSEN_Msk        (0x1UL << SPDIFRX_CR_CKSEN_Pos)            /*!< 0x00100000 */

+#define SPDIFRX_CR_CKSEN            SPDIFRX_CR_CKSEN_Msk                       /*!<Symbol Clock Enable */

+#define SPDIFRX_CR_CKSBKPEN_Pos     (21U)

+#define SPDIFRX_CR_CKSBKPEN_Msk     (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)         /*!< 0x00200000 */

+#define SPDIFRX_CR_CKSBKPEN         SPDIFRX_CR_CKSBKPEN_Msk                    /*!<Backup Symbol Clock Enable */

+

+/*******************  Bit definition for SPDIFRX_IMR register  *******************/

+#define SPDIFRX_IMR_RXNEIE_Pos      (0U)

+#define SPDIFRX_IMR_RXNEIE_Msk      (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)          /*!< 0x00000001 */

+#define SPDIFRX_IMR_RXNEIE          SPDIFRX_IMR_RXNEIE_Msk                     /*!<RXNE interrupt enable                              */

+#define SPDIFRX_IMR_CSRNEIE_Pos     (1U)

+#define SPDIFRX_IMR_CSRNEIE_Msk     (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)         /*!< 0x00000002 */

+#define SPDIFRX_IMR_CSRNEIE         SPDIFRX_IMR_CSRNEIE_Msk                    /*!<Control Buffer Ready Interrupt Enable              */

+#define SPDIFRX_IMR_PERRIE_Pos      (2U)

+#define SPDIFRX_IMR_PERRIE_Msk      (0x1UL << SPDIFRX_IMR_PERRIE_Pos)          /*!< 0x00000004 */

+#define SPDIFRX_IMR_PERRIE          SPDIFRX_IMR_PERRIE_Msk                     /*!<Parity error interrupt enable                      */

+#define SPDIFRX_IMR_OVRIE_Pos       (3U)

+#define SPDIFRX_IMR_OVRIE_Msk       (0x1UL << SPDIFRX_IMR_OVRIE_Pos)           /*!< 0x00000008 */

+#define SPDIFRX_IMR_OVRIE           SPDIFRX_IMR_OVRIE_Msk                      /*!<Overrun error Interrupt Enable                     */

+#define SPDIFRX_IMR_SBLKIE_Pos      (4U)

+#define SPDIFRX_IMR_SBLKIE_Msk      (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)          /*!< 0x00000010 */

+#define SPDIFRX_IMR_SBLKIE          SPDIFRX_IMR_SBLKIE_Msk                     /*!<Synchronization Block Detected Interrupt Enable    */

+#define SPDIFRX_IMR_SYNCDIE_Pos     (5U)

+#define SPDIFRX_IMR_SYNCDIE_Msk     (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)         /*!< 0x00000020 */

+#define SPDIFRX_IMR_SYNCDIE         SPDIFRX_IMR_SYNCDIE_Msk                    /*!<Synchronization Done                               */

+#define SPDIFRX_IMR_IFEIE_Pos       (6U)

+#define SPDIFRX_IMR_IFEIE_Msk       (0x1UL << SPDIFRX_IMR_IFEIE_Pos)           /*!< 0x00000040 */

+#define SPDIFRX_IMR_IFEIE           SPDIFRX_IMR_IFEIE_Msk                      /*!<Serial Interface Error Interrupt Enable            */

+

+/*******************  Bit definition for SPDIFRX_SR register  *******************/

+#define SPDIFRX_SR_RXNE_Pos         (0U)

+#define SPDIFRX_SR_RXNE_Msk         (0x1UL << SPDIFRX_SR_RXNE_Pos)             /*!< 0x00000001 */

+#define SPDIFRX_SR_RXNE             SPDIFRX_SR_RXNE_Msk                        /*!<Read data register not empty                          */

+#define SPDIFRX_SR_CSRNE_Pos        (1U)

+#define SPDIFRX_SR_CSRNE_Msk        (0x1UL << SPDIFRX_SR_CSRNE_Pos)            /*!< 0x00000002 */

+#define SPDIFRX_SR_CSRNE            SPDIFRX_SR_CSRNE_Msk                       /*!<The Control Buffer register is not empty              */

+#define SPDIFRX_SR_PERR_Pos         (2U)

+#define SPDIFRX_SR_PERR_Msk         (0x1UL << SPDIFRX_SR_PERR_Pos)             /*!< 0x00000004 */

+#define SPDIFRX_SR_PERR             SPDIFRX_SR_PERR_Msk                        /*!<Parity error                                          */

+#define SPDIFRX_SR_OVR_Pos          (3U)

+#define SPDIFRX_SR_OVR_Msk          (0x1UL << SPDIFRX_SR_OVR_Pos)              /*!< 0x00000008 */

+#define SPDIFRX_SR_OVR              SPDIFRX_SR_OVR_Msk                         /*!<Overrun error                                         */

+#define SPDIFRX_SR_SBD_Pos          (4U)

+#define SPDIFRX_SR_SBD_Msk          (0x1UL << SPDIFRX_SR_SBD_Pos)              /*!< 0x00000010 */

+#define SPDIFRX_SR_SBD              SPDIFRX_SR_SBD_Msk                         /*!<Synchronization Block Detected                        */

+#define SPDIFRX_SR_SYNCD_Pos        (5U)

+#define SPDIFRX_SR_SYNCD_Msk        (0x1UL << SPDIFRX_SR_SYNCD_Pos)            /*!< 0x00000020 */

+#define SPDIFRX_SR_SYNCD            SPDIFRX_SR_SYNCD_Msk                       /*!<Synchronization Done                                  */

+#define SPDIFRX_SR_FERR_Pos         (6U)

+#define SPDIFRX_SR_FERR_Msk         (0x1UL << SPDIFRX_SR_FERR_Pos)             /*!< 0x00000040 */

+#define SPDIFRX_SR_FERR             SPDIFRX_SR_FERR_Msk                        /*!<Framing error                                         */

+#define SPDIFRX_SR_SERR_Pos         (7U)

+#define SPDIFRX_SR_SERR_Msk         (0x1UL << SPDIFRX_SR_SERR_Pos)             /*!< 0x00000080 */

+#define SPDIFRX_SR_SERR             SPDIFRX_SR_SERR_Msk                        /*!<Synchronization error                                 */

+#define SPDIFRX_SR_TERR_Pos         (8U)

+#define SPDIFRX_SR_TERR_Msk         (0x1UL << SPDIFRX_SR_TERR_Pos)             /*!< 0x00000100 */

+#define SPDIFRX_SR_TERR             SPDIFRX_SR_TERR_Msk                        /*!<Time-out error                                        */

+#define SPDIFRX_SR_WIDTH5_Pos       (16U)

+#define SPDIFRX_SR_WIDTH5_Msk       (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)        /*!< 0x7FFF0000 */

+#define SPDIFRX_SR_WIDTH5           SPDIFRX_SR_WIDTH5_Msk                      /*!<Duration of 5 symbols counted with spdif_clk          */

+

+/*******************  Bit definition for SPDIFRX_IFCR register  *******************/

+#define SPDIFRX_IFCR_PERRCF_Pos     (2U)

+#define SPDIFRX_IFCR_PERRCF_Msk     (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)         /*!< 0x00000004 */

+#define SPDIFRX_IFCR_PERRCF         SPDIFRX_IFCR_PERRCF_Msk                    /*!<Clears the Parity error flag                         */

+#define SPDIFRX_IFCR_OVRCF_Pos      (3U)

+#define SPDIFRX_IFCR_OVRCF_Msk      (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)          /*!< 0x00000008 */

+#define SPDIFRX_IFCR_OVRCF          SPDIFRX_IFCR_OVRCF_Msk                     /*!<Clears the Overrun error flag                        */

+#define SPDIFRX_IFCR_SBDCF_Pos      (4U)

+#define SPDIFRX_IFCR_SBDCF_Msk      (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)          /*!< 0x00000010 */

+#define SPDIFRX_IFCR_SBDCF          SPDIFRX_IFCR_SBDCF_Msk                     /*!<Clears the Synchronization Block Detected flag       */

+#define SPDIFRX_IFCR_SYNCDCF_Pos    (5U)

+#define SPDIFRX_IFCR_SYNCDCF_Msk    (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)        /*!< 0x00000020 */

+#define SPDIFRX_IFCR_SYNCDCF        SPDIFRX_IFCR_SYNCDCF_Msk                   /*!<Clears the Synchronization Done flag                 */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/

+#define SPDIFRX_DR0_DR_Pos          (0U)

+#define SPDIFRX_DR0_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)         /*!< 0x00FFFFFF */

+#define SPDIFRX_DR0_DR              SPDIFRX_DR0_DR_Msk                         /*!<Data value            */

+#define SPDIFRX_DR0_PE_Pos          (24U)

+#define SPDIFRX_DR0_PE_Msk          (0x1UL << SPDIFRX_DR0_PE_Pos)              /*!< 0x01000000 */

+#define SPDIFRX_DR0_PE              SPDIFRX_DR0_PE_Msk                         /*!<Parity Error bit      */

+#define SPDIFRX_DR0_V_Pos           (25U)

+#define SPDIFRX_DR0_V_Msk           (0x1UL << SPDIFRX_DR0_V_Pos)               /*!< 0x02000000 */

+#define SPDIFRX_DR0_V               SPDIFRX_DR0_V_Msk                          /*!<Validity bit          */

+#define SPDIFRX_DR0_U_Pos           (26U)

+#define SPDIFRX_DR0_U_Msk           (0x1UL << SPDIFRX_DR0_U_Pos)               /*!< 0x04000000 */

+#define SPDIFRX_DR0_U               SPDIFRX_DR0_U_Msk                          /*!<User bit              */

+#define SPDIFRX_DR0_C_Pos           (27U)

+#define SPDIFRX_DR0_C_Msk           (0x1UL << SPDIFRX_DR0_C_Pos)               /*!< 0x08000000 */

+#define SPDIFRX_DR0_C               SPDIFRX_DR0_C_Msk                          /*!<Channel Status bit    */

+#define SPDIFRX_DR0_PT_Pos          (28U)

+#define SPDIFRX_DR0_PT_Msk          (0x3UL << SPDIFRX_DR0_PT_Pos)              /*!< 0x30000000 */

+#define SPDIFRX_DR0_PT              SPDIFRX_DR0_PT_Msk                         /*!<Preamble Type         */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/

+#define SPDIFRX_DR1_DR_Pos          (8U)

+#define SPDIFRX_DR1_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)         /*!< 0xFFFFFF00 */

+#define SPDIFRX_DR1_DR              SPDIFRX_DR1_DR_Msk                         /*!<Data value            */

+#define SPDIFRX_DR1_PT_Pos          (4U)

+#define SPDIFRX_DR1_PT_Msk          (0x3UL << SPDIFRX_DR1_PT_Pos)              /*!< 0x00000030 */

+#define SPDIFRX_DR1_PT              SPDIFRX_DR1_PT_Msk                         /*!<Preamble Type         */

+#define SPDIFRX_DR1_C_Pos           (3U)

+#define SPDIFRX_DR1_C_Msk           (0x1UL << SPDIFRX_DR1_C_Pos)               /*!< 0x00000008 */

+#define SPDIFRX_DR1_C               SPDIFRX_DR1_C_Msk                          /*!<Channel Status bit    */

+#define SPDIFRX_DR1_U_Pos           (2U)

+#define SPDIFRX_DR1_U_Msk           (0x1UL << SPDIFRX_DR1_U_Pos)               /*!< 0x00000004 */

+#define SPDIFRX_DR1_U               SPDIFRX_DR1_U_Msk                          /*!<User bit              */

+#define SPDIFRX_DR1_V_Pos           (1U)

+#define SPDIFRX_DR1_V_Msk           (0x1UL << SPDIFRX_DR1_V_Pos)               /*!< 0x00000002 */

+#define SPDIFRX_DR1_V               SPDIFRX_DR1_V_Msk                          /*!<Validity bit          */

+#define SPDIFRX_DR1_PE_Pos          (0U)

+#define SPDIFRX_DR1_PE_Msk          (0x1UL << SPDIFRX_DR1_PE_Pos)              /*!< 0x00000001 */

+#define SPDIFRX_DR1_PE              SPDIFRX_DR1_PE_Msk                         /*!<Parity Error bit      */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/

+#define SPDIFRX_DR1_DRNL1_Pos       (16U)

+#define SPDIFRX_DR1_DRNL1_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)        /*!< 0xFFFF0000 */

+#define SPDIFRX_DR1_DRNL1           SPDIFRX_DR1_DRNL1_Msk                      /*!<Data value Channel B      */

+#define SPDIFRX_DR1_DRNL2_Pos       (0U)

+#define SPDIFRX_DR1_DRNL2_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)        /*!< 0x0000FFFF */

+#define SPDIFRX_DR1_DRNL2           SPDIFRX_DR1_DRNL2_Msk                      /*!<Data value Channel A      */

+

+/*******************  Bit definition for SPDIFRX_CSR register   *******************/

+#define SPDIFRX_CSR_USR_Pos         (0U)

+#define SPDIFRX_CSR_USR_Msk         (0xFFFFUL << SPDIFRX_CSR_USR_Pos)          /*!< 0x0000FFFF */

+#define SPDIFRX_CSR_USR             SPDIFRX_CSR_USR_Msk                        /*!<User data information           */

+#define SPDIFRX_CSR_CS_Pos          (16U)

+#define SPDIFRX_CSR_CS_Msk          (0xFFUL << SPDIFRX_CSR_CS_Pos)             /*!< 0x00FF0000 */

+#define SPDIFRX_CSR_CS              SPDIFRX_CSR_CS_Msk                         /*!<Channel A status information    */

+#define SPDIFRX_CSR_SOB_Pos         (24U)

+#define SPDIFRX_CSR_SOB_Msk         (0x1UL << SPDIFRX_CSR_SOB_Pos)             /*!< 0x01000000 */

+#define SPDIFRX_CSR_SOB             SPDIFRX_CSR_SOB_Msk                        /*!<Start Of Block                  */

+

+/*******************  Bit definition for SPDIFRX_DIR register    *******************/

+#define SPDIFRX_DIR_THI_Pos         (0U)

+#define SPDIFRX_DIR_THI_Msk         (0x1FFFUL << SPDIFRX_DIR_THI_Pos)          /*!< 0x00001FFF */

+#define SPDIFRX_DIR_THI             SPDIFRX_DIR_THI_Msk                        /*!<Threshold LOW      */

+#define SPDIFRX_DIR_TLO_Pos         (16U)

+#define SPDIFRX_DIR_TLO_Msk         (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)          /*!< 0x1FFF0000 */

+#define SPDIFRX_DIR_TLO             SPDIFRX_DIR_TLO_Msk                        /*!<Threshold HIGH     */

+

+/*******************  Bit definition for SPDIFRX_VERR register    *******************/

+#define SPDIFRX_VERR_MINREV_Pos     (0U)

+#define SPDIFRX_VERR_MINREV_Msk     (0xFUL << SPDIFRX_VERR_MINREV_Pos)         /*!< 0x0000000F */

+#define SPDIFRX_VERR_MINREV         SPDIFRX_VERR_MINREV_Msk                    /*!<SPDIFRX Minor revision     */

+#define SPDIFRX_VERR_MAJREV_Pos     (4U)

+#define SPDIFRX_VERR_MAJREV_Msk     (0xFUL << SPDIFRX_VERR_MAJREV_Pos)         /*!< 0x000000F0 */

+#define SPDIFRX_VERR_MAJREV         SPDIFRX_VERR_MAJREV_Msk                    /*!<SPDIFRX Major revision     */

+

+/*******************  Bit definition for SPDIFRX_IDR register    *******************/

+#define SPDIFRX_IDR_ID_Pos          (0U)

+#define SPDIFRX_IDR_ID_Msk          (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos)       /*!< 0xFFFFFFFF */

+#define SPDIFRX_IDR_ID              SPDIFRX_IDR_ID_Msk                         /*!<SPDIFRX identifier     */

+

+/*******************  Bit definition for SPDIFRX_SIDR register    *******************/

+#define SPDIFRX_SIDR_SID_Pos        (0U)

+#define SPDIFRX_SIDR_SID_Msk        (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos)     /*!< 0xFFFFFFFF */

+#define SPDIFRX_SIDR_SID            SPDIFRX_SIDR_SID_Msk                       /*!<Size of the memory region allocated to SPDIFRX registers */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          Serial Audio Interface                            */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  SAI VERSION  ********************************/

+#define SAI_VER_V2_X

+

+/********************  Bit definition for SAI_GCR register  *******************/

+#define SAI_GCR_SYNCIN_Pos         (0U)

+#define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000003 */

+#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */

+#define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */

+#define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */

+

+#define SAI_GCR_SYNCOUT_Pos        (4U)

+#define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000030 */

+#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */

+#define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */

+#define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */

+

+/*******************  Bit definition for SAI_xCR1 register  *******************/

+#define SAI_xCR1_MODE_Pos          (0U)

+#define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */

+#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */

+#define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */

+#define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */

+

+#define SAI_xCR1_PRTCFG_Pos        (2U)

+#define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */

+#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */

+#define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */

+#define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */

+

+#define SAI_xCR1_DS_Pos            (5U)

+#define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */

+#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */

+#define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */

+#define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */

+#define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */

+

+#define SAI_xCR1_LSBFIRST_Pos      (8U)

+#define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */

+#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */

+#define SAI_xCR1_CKSTR_Pos         (9U)

+#define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */

+#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */

+

+#define SAI_xCR1_SYNCEN_Pos        (10U)

+#define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */

+#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */

+#define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */

+#define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */

+

+#define SAI_xCR1_MONO_Pos          (12U)

+#define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */

+#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */

+#define SAI_xCR1_OUTDRIV_Pos       (13U)

+#define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */

+#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */

+#define SAI_xCR1_SAIEN_Pos         (16U)

+#define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */

+#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */

+#define SAI_xCR1_DMAEN_Pos         (17U)

+#define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */

+#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */

+#define SAI_xCR1_NODIV_Pos         (19U)

+#define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */

+#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */

+

+#define SAI_xCR1_MCKDIV_Pos        (20U)

+#define SAI_xCR1_MCKDIV_Msk        (0x3FUL << SAI_xCR1_MCKDIV_Pos)             /*!< 0x03F00000 */

+#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[5:0] (Master ClocK Divider)  */

+#define SAI_xCR1_MCKDIV_0          (0x01UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00100000 */

+#define SAI_xCR1_MCKDIV_1          (0x02UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00200000 */

+#define SAI_xCR1_MCKDIV_2          (0x04UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00400000 */

+#define SAI_xCR1_MCKDIV_3          (0x08UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00800000 */

+#define SAI_xCR1_MCKDIV_4          (0x10UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x01000000 */

+#define SAI_xCR1_MCKDIV_5          (0x20UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x02000000 */

+

+#define SAI_xCR1_MCKEN_Pos         (27U)

+#define SAI_xCR1_MCKEN_Msk         (0x1UL << SAI_xCR1_MCKEN_Pos)               /*!< 0x08000000 */

+#define SAI_xCR1_MCKEN             SAI_xCR1_MCKEN_Msk                          /*!<Master ClocK enable */

+

+#define SAI_xCR1_OSR_Pos           (26U)

+#define SAI_xCR1_OSR_Msk           (0x1UL << SAI_xCR1_OSR_Pos)                 /*!< 0x04000000 */

+#define SAI_xCR1_OSR               SAI_xCR1_OSR_Msk                            /*!<OverSampling Ratio for master clock  */

+

+/* Legacy define */

+#define  SAI_xCR1_NOMCK               SAI_xCR1_NODIV

+

+/*******************  Bit definition for SAI_xCR2 register  *******************/

+#define SAI_xCR2_FTH_Pos           (0U)

+#define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */

+#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */

+#define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */

+#define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */

+#define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */

+

+#define SAI_xCR2_FFLUSH_Pos        (3U)

+#define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */

+#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */

+#define SAI_xCR2_TRIS_Pos          (4U)

+#define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */

+#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */

+#define SAI_xCR2_MUTE_Pos          (5U)

+#define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */

+#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */

+#define SAI_xCR2_MUTEVAL_Pos       (6U)

+#define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */

+#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */

+

+#define SAI_xCR2_MUTECNT_Pos       (7U)

+#define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */

+#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */

+#define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */

+#define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */

+#define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */

+#define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */

+#define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */

+#define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */

+

+#define SAI_xCR2_CPL_Pos           (13U)

+#define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */

+#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */

+

+#define SAI_xCR2_COMP_Pos          (14U)

+#define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */

+#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */

+#define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */

+#define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */

+

+/******************  Bit definition for SAI_xFRCR register  *******************/

+#define SAI_xFRCR_FRL_Pos          (0U)

+#define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */

+#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](FRame Length)  */

+#define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */

+#define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */

+#define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */

+#define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */

+#define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */

+#define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */

+#define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */

+#define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */

+

+#define SAI_xFRCR_FSALL_Pos        (8U)

+#define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */

+#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FSALL[6:0] (Frame Synchronization Active Level Length)  */

+#define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */

+#define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */

+#define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */

+#define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */

+#define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */

+#define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */

+#define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */

+

+#define SAI_xFRCR_FSDEF_Pos        (16U)

+#define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */

+#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!<Frame Synchronization Definition  */

+#define SAI_xFRCR_FSPOL_Pos        (17U)

+#define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */

+#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */

+#define SAI_xFRCR_FSOFF_Pos        (18U)

+#define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */

+#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */

+

+/* Legacy define */

+#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL

+

+/******************  Bit definition for SAI_xSLOTR register  *******************/

+#define SAI_xSLOTR_FBOFF_Pos       (0U)

+#define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */

+#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FBOFF[4:0](First Bit Offset)  */

+#define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */

+#define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */

+#define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */

+#define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */

+#define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */

+

+#define SAI_xSLOTR_SLOTSZ_Pos      (6U)

+#define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */

+#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */

+#define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */

+#define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */

+

+#define SAI_xSLOTR_NBSLOT_Pos      (8U)

+#define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */

+#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */

+#define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */

+#define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */

+#define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */

+#define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */

+

+#define SAI_xSLOTR_SLOTEN_Pos      (16U)

+#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */

+#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */

+

+/*******************  Bit definition for SAI_xIMR register  *******************/

+#define SAI_xIMR_OVRUDRIE_Pos      (0U)

+#define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */

+#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */

+#define SAI_xIMR_MUTEDETIE_Pos     (1U)

+#define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */

+#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */

+#define SAI_xIMR_WCKCFGIE_Pos      (2U)

+#define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */

+#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */

+#define SAI_xIMR_FREQIE_Pos        (3U)

+#define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */

+#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */

+#define SAI_xIMR_CNRDYIE_Pos       (4U)

+#define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */

+#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */

+#define SAI_xIMR_AFSDETIE_Pos      (5U)

+#define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */

+#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */

+#define SAI_xIMR_LFSDETIE_Pos      (6U)

+#define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */

+#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */

+

+/********************  Bit definition for SAI_xSR register  *******************/

+#define SAI_xSR_OVRUDR_Pos         (0U)

+#define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */

+#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */

+#define SAI_xSR_MUTEDET_Pos        (1U)

+#define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */

+#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */

+#define SAI_xSR_WCKCFG_Pos         (2U)

+#define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */

+#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */

+#define SAI_xSR_FREQ_Pos           (3U)

+#define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */

+#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */

+#define SAI_xSR_CNRDY_Pos          (4U)

+#define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */

+#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */

+#define SAI_xSR_AFSDET_Pos         (5U)

+#define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */

+#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */

+#define SAI_xSR_LFSDET_Pos         (6U)

+#define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */

+#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */

+

+#define SAI_xSR_FLVL_Pos           (16U)

+#define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */

+#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */

+#define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */

+#define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */

+#define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */

+

+/******************  Bit definition for SAI_xCLRFR register  ******************/

+#define SAI_xCLRFR_COVRUDR_Pos     (0U)

+#define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */

+#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */

+#define SAI_xCLRFR_CMUTEDET_Pos    (1U)

+#define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */

+#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */

+#define SAI_xCLRFR_CWCKCFG_Pos     (2U)

+#define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */

+#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */

+#define SAI_xCLRFR_CFREQ_Pos       (3U)

+#define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */

+#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */

+#define SAI_xCLRFR_CCNRDY_Pos      (4U)

+#define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */

+#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */

+#define SAI_xCLRFR_CAFSDET_Pos     (5U)

+#define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */

+#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */

+#define SAI_xCLRFR_CLFSDET_Pos     (6U)

+#define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */

+#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */

+

+/******************  Bit definition for SAI_xDR register  *********************/

+#define SAI_xDR_DATA_Pos           (0U)

+#define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */

+#define SAI_xDR_DATA               SAI_xDR_DATA_Msk

+

+/*******************  Bit definition for SAI_PDMCR register  ******************/

+#define SAI_PDMCR_PDMEN_Pos        (0U)

+#define SAI_PDMCR_PDMEN_Msk        (0x1UL << SAI_PDMCR_PDMEN_Pos)              /*!< 0x00000001 */

+#define SAI_PDMCR_PDMEN            SAI_PDMCR_PDMEN_Msk                         /*!<PDM Enable                                          */

+

+#define SAI_PDMCR_MICNBR_Pos       (4U)

+#define SAI_PDMCR_MICNBR_Msk       (0x3UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000030 */

+#define SAI_PDMCR_MICNBR           SAI_PDMCR_MICNBR_Msk                        /*!<Number of microphones                               */

+#define SAI_PDMCR_MICNBR_0         (0x1UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000010 */

+#define SAI_PDMCR_MICNBR_1         (0x2UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000020 */

+

+#define SAI_PDMCR_CKEN1_Pos        (8U)

+#define SAI_PDMCR_CKEN1_Msk        (0x1UL << SAI_PDMCR_CKEN1_Pos)              /*!< 0x00000100 */

+#define SAI_PDMCR_CKEN1            SAI_PDMCR_CKEN1_Msk                         /*!<Clock enable of bitstream clock number 1            */

+#define SAI_PDMCR_CKEN2_Pos        (9U)

+#define SAI_PDMCR_CKEN2_Msk        (0x1UL << SAI_PDMCR_CKEN2_Pos)              /*!< 0x00000200 */

+#define SAI_PDMCR_CKEN2            SAI_PDMCR_CKEN2_Msk                         /*!<Clock enable of bitstream clock number 2            */

+#define SAI_PDMCR_CKEN3_Pos        (10U)

+#define SAI_PDMCR_CKEN3_Msk        (0x1UL << SAI_PDMCR_CKEN3_Pos)              /*!< 0x00000400 */

+#define SAI_PDMCR_CKEN3            SAI_PDMCR_CKEN3_Msk                         /*!<Clock enable of bitstream clock number 3            */

+#define SAI_PDMCR_CKEN4_Pos        (11U)

+#define SAI_PDMCR_CKEN4_Msk        (0x1UL << SAI_PDMCR_CKEN4_Pos)              /*!< 0x00000800 */

+#define SAI_PDMCR_CKEN4            SAI_PDMCR_CKEN4_Msk                         /*!<Clock enable of bitstream clock number 4            */

+

+/******************  Bit definition for SAI_PDMDLY register  ******************/

+#define SAI_PDMDLY_DLYM1L_Pos      (0U)

+#define SAI_PDMDLY_DLYM1L_Msk      (0x7UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000007 */

+#define SAI_PDMDLY_DLYM1L          SAI_PDMDLY_DLYM1L_Msk                       /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */

+#define SAI_PDMDLY_DLYM1L_0        (0x1UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000001 */

+#define SAI_PDMDLY_DLYM1L_1        (0x2UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000002 */

+#define SAI_PDMDLY_DLYM1L_2        (0x4UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000004 */

+

+#define SAI_PDMDLY_DLYM1R_Pos      (4U)

+#define SAI_PDMDLY_DLYM1R_Msk      (0x7UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000070 */

+#define SAI_PDMDLY_DLYM1R          SAI_PDMDLY_DLYM1R_Msk                       /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */

+#define SAI_PDMDLY_DLYM1R_0        (0x1UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000010 */

+#define SAI_PDMDLY_DLYM1R_1        (0x2UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000020 */

+#define SAI_PDMDLY_DLYM1R_2        (0x4UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000040 */

+

+#define SAI_PDMDLY_DLYM2L_Pos      (8U)

+#define SAI_PDMDLY_DLYM2L_Msk      (0x7UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000700 */

+#define SAI_PDMDLY_DLYM2L          SAI_PDMDLY_DLYM2L_Msk                       /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */

+#define SAI_PDMDLY_DLYM2L_0        (0x1UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000100 */

+#define SAI_PDMDLY_DLYM2L_1        (0x2UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000200 */

+#define SAI_PDMDLY_DLYM2L_2        (0x4UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000400 */

+

+#define SAI_PDMDLY_DLYM2R_Pos      (12U)

+#define SAI_PDMDLY_DLYM2R_Msk      (0x7UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00007000 */

+#define SAI_PDMDLY_DLYM2R          SAI_PDMDLY_DLYM2R_Msk                       /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/

+#define SAI_PDMDLY_DLYM2R_0        (0x1UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00001000 */

+#define SAI_PDMDLY_DLYM2R_1        (0x2UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00002000 */

+#define SAI_PDMDLY_DLYM2R_2        (0x4UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00004000 */

+

+#define SAI_PDMDLY_DLYM3L_Pos      (16U)

+#define SAI_PDMDLY_DLYM3L_Msk      (0x7UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00070000 */

+#define SAI_PDMDLY_DLYM3L          SAI_PDMDLY_DLYM3L_Msk                       /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/

+#define SAI_PDMDLY_DLYM3L_0        (0x1UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00010000 */

+#define SAI_PDMDLY_DLYM3L_1        (0x2UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00020000 */

+#define SAI_PDMDLY_DLYM3L_2        (0x4UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00040000 */

+

+#define SAI_PDMDLY_DLYM3R_Pos      (20U)

+#define SAI_PDMDLY_DLYM3R_Msk      (0x7UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00700000 */

+#define SAI_PDMDLY_DLYM3R          SAI_PDMDLY_DLYM3R_Msk                       /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/

+#define SAI_PDMDLY_DLYM3R_0        (0x1UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00100000 */

+#define SAI_PDMDLY_DLYM3R_1        (0x2UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00200000 */

+#define SAI_PDMDLY_DLYM3R_2        (0x4UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00400000 */

+

+#define SAI_PDMDLY_DLYM4L_Pos      (24U)

+#define SAI_PDMDLY_DLYM4L_Msk      (0x7UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x07000000 */

+#define SAI_PDMDLY_DLYM4L          SAI_PDMDLY_DLYM4L_Msk                       /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/

+#define SAI_PDMDLY_DLYM4L_0        (0x1UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x01000000 */

+#define SAI_PDMDLY_DLYM4L_1        (0x2UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x02000000 */

+#define SAI_PDMDLY_DLYM4L_2        (0x4UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x04000000 */

+

+#define SAI_PDMDLY_DLYM4R_Pos      (28U)

+#define SAI_PDMDLY_DLYM4R_Msk      (0x7UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x70000000 */

+#define SAI_PDMDLY_DLYM4R          SAI_PDMDLY_DLYM4R_Msk                       /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/

+#define SAI_PDMDLY_DLYM4R_0        (0x1UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x10000000 */

+#define SAI_PDMDLY_DLYM4R_1        (0x2UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x20000000 */

+#define SAI_PDMDLY_DLYM4R_2        (0x4UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x40000000 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           SDMMC Interface                                  */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for SDMMC_POWER register  ******************/

+#define SDMMC_POWER_PWRCTRL_Pos          (0U)

+#define SDMMC_POWER_PWRCTRL_Msk          (0x3UL << SDMMC_POWER_PWRCTRL_Pos)    /*!< 0x00000003 */

+#define SDMMC_POWER_PWRCTRL              SDMMC_POWER_PWRCTRL_Msk               /*!<PWRCTRL[1:0] bits (Power supply control bits) */

+#define SDMMC_POWER_PWRCTRL_0            (0x1UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000001 */

+#define SDMMC_POWER_PWRCTRL_1            (0x2UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000002 */

+#define SDMMC_POWER_VSWITCH_Pos          (2U)

+#define SDMMC_POWER_VSWITCH_Msk          (0x1UL << SDMMC_POWER_VSWITCH_Pos)    /*!< 0x00000004 */

+#define SDMMC_POWER_VSWITCH              SDMMC_POWER_VSWITCH_Msk               /*!<Voltage switch sequence start */

+#define SDMMC_POWER_VSWITCHEN_Pos        (3U)

+#define SDMMC_POWER_VSWITCHEN_Msk        (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)  /*!< 0x00000008 */

+#define SDMMC_POWER_VSWITCHEN            SDMMC_POWER_VSWITCHEN_Msk             /*!<Voltage switch procedure enable */

+#define SDMMC_POWER_DIRPOL_Pos           (4U)

+#define SDMMC_POWER_DIRPOL_Msk           (0x1UL << SDMMC_POWER_DIRPOL_Pos)     /*!< 0x00000010 */

+#define SDMMC_POWER_DIRPOL               SDMMC_POWER_DIRPOL_Msk                /*!<Data and Command direction signals polarity selection */

+

+/******************  Bit definition for SDMMC_CLKCR register  ******************/

+#define SDMMC_CLKCR_CLKDIV_Pos           (0U)

+#define SDMMC_CLKCR_CLKDIV_Msk           (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)   /*!< 0x000003FF */

+#define SDMMC_CLKCR_CLKDIV               SDMMC_CLKCR_CLKDIV_Msk                /*!<Clock divide factor             */

+#define SDMMC_CLKCR_PWRSAV_Pos           (12U)

+#define SDMMC_CLKCR_PWRSAV_Msk           (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)     /*!< 0x00001000 */

+#define SDMMC_CLKCR_PWRSAV               SDMMC_CLKCR_PWRSAV_Msk                /*!<Power saving configuration bit  */

+

+#define SDMMC_CLKCR_WIDBUS_Pos           (14U)

+#define SDMMC_CLKCR_WIDBUS_Msk           (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)     /*!< 0x0000C000 */

+#define SDMMC_CLKCR_WIDBUS               SDMMC_CLKCR_WIDBUS_Msk                /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */

+#define SDMMC_CLKCR_WIDBUS_0             (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00004000 */

+#define SDMMC_CLKCR_WIDBUS_1             (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00008000 */

+

+#define SDMMC_CLKCR_NEGEDGE_Pos          (16U)

+#define SDMMC_CLKCR_NEGEDGE_Msk          (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)    /*!< 0x00010000 */

+#define SDMMC_CLKCR_NEGEDGE              SDMMC_CLKCR_NEGEDGE_Msk               /*!<SDMMC_CK dephasing selection bit */

+#define SDMMC_CLKCR_HWFC_EN_Pos          (17U)

+#define SDMMC_CLKCR_HWFC_EN_Msk          (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)    /*!< 0x00020000 */

+#define SDMMC_CLKCR_HWFC_EN              SDMMC_CLKCR_HWFC_EN_Msk               /*!<HW Flow Control enable           */

+#define SDMMC_CLKCR_DDR_Pos              (18U)

+#define SDMMC_CLKCR_DDR_Msk              (0x1UL << SDMMC_CLKCR_DDR_Pos)        /*!< 0x00040000 */

+#define SDMMC_CLKCR_DDR                  SDMMC_CLKCR_DDR_Msk                   /*!<Data rate signaling selection    */

+#define SDMMC_CLKCR_BUSSPEED_Pos         (19U)

+#define SDMMC_CLKCR_BUSSPEED_Msk         (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)   /*!< 0x00080000 */

+#define SDMMC_CLKCR_BUSSPEED             SDMMC_CLKCR_BUSSPEED_Msk              /*!<Bus speed mode selection         */

+#define SDMMC_CLKCR_SELCLKRX_Pos         (20U)

+#define SDMMC_CLKCR_SELCLKRX_Msk         (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)   /*!< 0x00300000 */

+#define SDMMC_CLKCR_SELCLKRX             SDMMC_CLKCR_SELCLKRX_Msk              /*!<SELCLKRX[1:0] bits (Receive clock selection) */

+#define SDMMC_CLKCR_SELCLKRX_0           (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00100000 */

+#define SDMMC_CLKCR_SELCLKRX_1           (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00200000 */

+

+/*******************  Bit definition for SDMMC_ARG register  *******************/

+#define SDMMC_ARG_CMDARG_Pos             (0U)

+#define SDMMC_ARG_CMDARG_Msk             (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_ARG_CMDARG                 SDMMC_ARG_CMDARG_Msk                  /*!<Command argument */

+

+/*******************  Bit definition for SDMMC_CMD register  *******************/

+#define SDMMC_CMD_CMDINDEX_Pos           (0U)

+#define SDMMC_CMD_CMDINDEX_Msk           (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)    /*!< 0x0000003F */

+#define SDMMC_CMD_CMDINDEX               SDMMC_CMD_CMDINDEX_Msk                /*!<Command Index                               */

+#define SDMMC_CMD_CMDTRANS_Pos           (6U)

+#define SDMMC_CMD_CMDTRANS_Msk           (0x1UL << SDMMC_CMD_CMDTRANS_Pos)     /*!< 0x00000040 */

+#define SDMMC_CMD_CMDTRANS               SDMMC_CMD_CMDTRANS_Msk                /*!<CPSM Treats command as a Data Transfer      */

+#define SDMMC_CMD_CMDSTOP_Pos            (7U)

+#define SDMMC_CMD_CMDSTOP_Msk            (0x1UL << SDMMC_CMD_CMDSTOP_Pos)      /*!< 0x00000080 */

+#define SDMMC_CMD_CMDSTOP                SDMMC_CMD_CMDSTOP_Msk                 /*!<CPSM Treats command as a Stop               */

+

+#define SDMMC_CMD_WAITRESP_Pos           (8U)

+#define SDMMC_CMD_WAITRESP_Msk           (0x3UL << SDMMC_CMD_WAITRESP_Pos)     /*!< 0x00000300 */

+#define SDMMC_CMD_WAITRESP               SDMMC_CMD_WAITRESP_Msk                /*!<WAITRESP[1:0] bits (Wait for response bits) */

+#define SDMMC_CMD_WAITRESP_0             (0x1UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000100 */

+#define SDMMC_CMD_WAITRESP_1             (0x2UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000200 */

+

+#define SDMMC_CMD_WAITINT_Pos            (10U)

+#define SDMMC_CMD_WAITINT_Msk            (0x1UL << SDMMC_CMD_WAITINT_Pos)      /*!< 0x00000400 */

+#define SDMMC_CMD_WAITINT                SDMMC_CMD_WAITINT_Msk                 /*!<CPSM Waits for Interrupt Request                               */

+#define SDMMC_CMD_WAITPEND_Pos           (11U)

+#define SDMMC_CMD_WAITPEND_Msk           (0x1UL << SDMMC_CMD_WAITPEND_Pos)     /*!< 0x00000800 */

+#define SDMMC_CMD_WAITPEND               SDMMC_CMD_WAITPEND_Msk                /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */

+#define SDMMC_CMD_CPSMEN_Pos             (12U)

+#define SDMMC_CMD_CPSMEN_Msk             (0x1UL << SDMMC_CMD_CPSMEN_Pos)       /*!< 0x00001000 */

+#define SDMMC_CMD_CPSMEN                 SDMMC_CMD_CPSMEN_Msk                  /*!<Command path state machine (CPSM) Enable bit                   */

+#define SDMMC_CMD_DTHOLD_Pos             (13U)

+#define SDMMC_CMD_DTHOLD_Msk             (0x1UL << SDMMC_CMD_DTHOLD_Pos)       /*!< 0x00002000 */

+#define SDMMC_CMD_DTHOLD                 SDMMC_CMD_DTHOLD_Msk                  /*!<Hold new data block transmission and reception in the DPSM     */

+#define SDMMC_CMD_BOOTMODE_Pos           (14U)

+#define SDMMC_CMD_BOOTMODE_Msk           (0x1UL << SDMMC_CMD_BOOTMODE_Pos)     /*!< 0x00004000 */

+#define SDMMC_CMD_BOOTMODE               SDMMC_CMD_BOOTMODE_Msk                /*!<Boot mode                                                      */

+#define SDMMC_CMD_BOOTEN_Pos             (15U)

+#define SDMMC_CMD_BOOTEN_Msk             (0x1UL << SDMMC_CMD_BOOTEN_Pos)       /*!< 0x00008000 */

+#define SDMMC_CMD_BOOTEN                 SDMMC_CMD_BOOTEN_Msk                  /*!<Enable Boot mode procedure                                     */

+#define SDMMC_CMD_CMDSUSPEND_Pos         (16U)

+#define SDMMC_CMD_CMDSUSPEND_Msk         (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)   /*!< 0x00010000 */

+#define SDMMC_CMD_CMDSUSPEND             SDMMC_CMD_CMDSUSPEND_Msk              /*!<CPSM Treats command as a Suspend or Resume command             */

+

+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/

+#define SDMMC_RESPCMD_RESPCMD_Pos        (0U)

+#define SDMMC_RESPCMD_RESPCMD_Msk        (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */

+#define SDMMC_RESPCMD_RESPCMD            SDMMC_RESPCMD_RESPCMD_Msk             /*!<Response command index */

+

+/******************  Bit definition for SDMMC_RESP0 register  ******************/

+#define SDMMC_RESP0_CARDSTATUS0_Pos      (0U)

+#define SDMMC_RESP0_CARDSTATUS0_Msk      (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP0_CARDSTATUS0          SDMMC_RESP0_CARDSTATUS0_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP1 register  ******************/

+#define SDMMC_RESP1_CARDSTATUS1_Pos      (0U)

+#define SDMMC_RESP1_CARDSTATUS1_Msk      (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP1_CARDSTATUS1          SDMMC_RESP1_CARDSTATUS1_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP2 register  ******************/

+#define SDMMC_RESP2_CARDSTATUS2_Pos      (0U)

+#define SDMMC_RESP2_CARDSTATUS2_Msk      (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP2_CARDSTATUS2          SDMMC_RESP2_CARDSTATUS2_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP3 register  ******************/

+#define SDMMC_RESP3_CARDSTATUS3_Pos      (0U)

+#define SDMMC_RESP3_CARDSTATUS3_Msk      (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP3_CARDSTATUS3          SDMMC_RESP3_CARDSTATUS3_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP4 register  ******************/

+#define SDMMC_RESP4_CARDSTATUS4_Pos      (0U)

+#define SDMMC_RESP4_CARDSTATUS4_Msk      (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP4_CARDSTATUS4          SDMMC_RESP4_CARDSTATUS4_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_DTIMER register  *****************/

+#define SDMMC_DTIMER_DATATIME_Pos        (0U)

+#define SDMMC_DTIMER_DATATIME_Msk        (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_DTIMER_DATATIME            SDMMC_DTIMER_DATATIME_Msk             /*!<Data timeout period. */

+

+/******************  Bit definition for SDMMC_DLEN register  *******************/

+#define SDMMC_DLEN_DATALENGTH_Pos        (0U)

+#define SDMMC_DLEN_DATALENGTH_Msk        (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_DLEN_DATALENGTH            SDMMC_DLEN_DATALENGTH_Msk             /*!<Data length value    */

+

+/******************  Bit definition for SDMMC_DCTRL register  ******************/

+#define SDMMC_DCTRL_DTEN_Pos             (0U)

+#define SDMMC_DCTRL_DTEN_Msk             (0x1UL << SDMMC_DCTRL_DTEN_Pos)       /*!< 0x00000001 */

+#define SDMMC_DCTRL_DTEN                 SDMMC_DCTRL_DTEN_Msk                  /*!<Data transfer enabled bit                */

+#define SDMMC_DCTRL_DTDIR_Pos            (1U)

+#define SDMMC_DCTRL_DTDIR_Msk            (0x1UL << SDMMC_DCTRL_DTDIR_Pos)      /*!< 0x00000002 */

+#define SDMMC_DCTRL_DTDIR                SDMMC_DCTRL_DTDIR_Msk                 /*!<Data transfer direction selection        */

+#define SDMMC_DCTRL_DTMODE_Pos           (2U)

+#define SDMMC_DCTRL_DTMODE_Msk           (0x3UL << SDMMC_DCTRL_DTMODE_Pos)     /*!< 0x0000000C */

+#define SDMMC_DCTRL_DTMODE               SDMMC_DCTRL_DTMODE_Msk                /*!<DTMODE[1:0] Data transfer mode selection */

+#define SDMMC_DCTRL_DTMODE_0             (0x1UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000004 */

+#define SDMMC_DCTRL_DTMODE_1             (0x2UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000008 */

+

+#define SDMMC_DCTRL_DBLOCKSIZE_Pos       (4U)

+#define SDMMC_DCTRL_DBLOCKSIZE_Msk       (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */

+#define SDMMC_DCTRL_DBLOCKSIZE           SDMMC_DCTRL_DBLOCKSIZE_Msk            /*!<DBLOCKSIZE[3:0] bits (Data block size) */

+#define SDMMC_DCTRL_DBLOCKSIZE_0         (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000010 */

+#define SDMMC_DCTRL_DBLOCKSIZE_1         (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000020 */

+#define SDMMC_DCTRL_DBLOCKSIZE_2         (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000040 */

+#define SDMMC_DCTRL_DBLOCKSIZE_3         (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000080 */

+

+#define SDMMC_DCTRL_RWSTART_Pos          (8U)

+#define SDMMC_DCTRL_RWSTART_Msk          (0x1UL << SDMMC_DCTRL_RWSTART_Pos)    /*!< 0x00000100 */

+#define SDMMC_DCTRL_RWSTART              SDMMC_DCTRL_RWSTART_Msk               /*!<Read wait start                                 */

+#define SDMMC_DCTRL_RWSTOP_Pos           (9U)

+#define SDMMC_DCTRL_RWSTOP_Msk           (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)     /*!< 0x00000200 */

+#define SDMMC_DCTRL_RWSTOP               SDMMC_DCTRL_RWSTOP_Msk                /*!<Read wait stop                                  */

+#define SDMMC_DCTRL_RWMOD_Pos            (10U)

+#define SDMMC_DCTRL_RWMOD_Msk            (0x1UL << SDMMC_DCTRL_RWMOD_Pos)      /*!< 0x00000400 */

+#define SDMMC_DCTRL_RWMOD                SDMMC_DCTRL_RWMOD_Msk                 /*!<Read wait mode                                  */

+#define SDMMC_DCTRL_SDIOEN_Pos           (11U)

+#define SDMMC_DCTRL_SDIOEN_Msk           (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)     /*!< 0x00000800 */

+#define SDMMC_DCTRL_SDIOEN               SDMMC_DCTRL_SDIOEN_Msk                /*!<SD I/O enable functions                         */

+#define SDMMC_DCTRL_BOOTACKEN_Pos        (12U)

+#define SDMMC_DCTRL_BOOTACKEN_Msk        (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)  /*!< 0x00001000 */

+#define SDMMC_DCTRL_BOOTACKEN            SDMMC_DCTRL_BOOTACKEN_Msk             /*!<Enable the reception of the Boot Acknowledgment */

+#define SDMMC_DCTRL_FIFORST_Pos          (13U)

+#define SDMMC_DCTRL_FIFORST_Msk          (0x1UL << SDMMC_DCTRL_FIFORST_Pos)    /*!< 0x00002000 */

+#define SDMMC_DCTRL_FIFORST              SDMMC_DCTRL_FIFORST_Msk               /*!<FIFO reset                                      */

+

+/******************  Bit definition for SDMMC_DCOUNT register  *****************/

+#define SDMMC_DCOUNT_DATACOUNT_Pos       (0U)

+#define SDMMC_DCOUNT_DATACOUNT_Msk       (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_DCOUNT_DATACOUNT           SDMMC_DCOUNT_DATACOUNT_Msk            /*!<Data count value */

+

+/******************  Bit definition for SDMMC_STA register  ********************/

+#define SDMMC_STA_CCRCFAIL_Pos           (0U)

+#define SDMMC_STA_CCRCFAIL_Msk           (0x1UL << SDMMC_STA_CCRCFAIL_Pos)     /*!< 0x00000001 */

+#define SDMMC_STA_CCRCFAIL               SDMMC_STA_CCRCFAIL_Msk                /*!<Command response received (CRC check failed)  */

+#define SDMMC_STA_DCRCFAIL_Pos           (1U)

+#define SDMMC_STA_DCRCFAIL_Msk           (0x1UL << SDMMC_STA_DCRCFAIL_Pos)     /*!< 0x00000002 */

+#define SDMMC_STA_DCRCFAIL               SDMMC_STA_DCRCFAIL_Msk                /*!<Data block sent/received (CRC check failed)   */

+#define SDMMC_STA_CTIMEOUT_Pos           (2U)

+#define SDMMC_STA_CTIMEOUT_Msk           (0x1UL << SDMMC_STA_CTIMEOUT_Pos)     /*!< 0x00000004 */

+#define SDMMC_STA_CTIMEOUT               SDMMC_STA_CTIMEOUT_Msk                /*!<Command response timeout                      */

+#define SDMMC_STA_DTIMEOUT_Pos           (3U)

+#define SDMMC_STA_DTIMEOUT_Msk           (0x1UL << SDMMC_STA_DTIMEOUT_Pos)     /*!< 0x00000008 */

+#define SDMMC_STA_DTIMEOUT               SDMMC_STA_DTIMEOUT_Msk                /*!<Data timeout                                  */

+#define SDMMC_STA_TXUNDERR_Pos           (4U)

+#define SDMMC_STA_TXUNDERR_Msk           (0x1UL << SDMMC_STA_TXUNDERR_Pos)     /*!< 0x00000010 */

+#define SDMMC_STA_TXUNDERR               SDMMC_STA_TXUNDERR_Msk                /*!<Transmit FIFO underrun error                  */

+#define SDMMC_STA_RXOVERR_Pos            (5U)

+#define SDMMC_STA_RXOVERR_Msk            (0x1UL << SDMMC_STA_RXOVERR_Pos)      /*!< 0x00000020 */

+#define SDMMC_STA_RXOVERR                SDMMC_STA_RXOVERR_Msk                 /*!<Received FIFO overrun error                   */

+#define SDMMC_STA_CMDREND_Pos            (6U)

+#define SDMMC_STA_CMDREND_Msk            (0x1UL << SDMMC_STA_CMDREND_Pos)      /*!< 0x00000040 */

+#define SDMMC_STA_CMDREND                SDMMC_STA_CMDREND_Msk                 /*!<Command response received (CRC check passed)  */

+#define SDMMC_STA_CMDSENT_Pos            (7U)

+#define SDMMC_STA_CMDSENT_Msk            (0x1UL << SDMMC_STA_CMDSENT_Pos)      /*!< 0x00000080 */

+#define SDMMC_STA_CMDSENT                SDMMC_STA_CMDSENT_Msk                 /*!<Command sent (no response required)           */

+#define SDMMC_STA_DATAEND_Pos            (8U)

+#define SDMMC_STA_DATAEND_Msk            (0x1UL << SDMMC_STA_DATAEND_Pos)      /*!< 0x00000100 */

+#define SDMMC_STA_DATAEND                SDMMC_STA_DATAEND_Msk                 /*!<Data end (data counter, SDIDCOUNT, is zero)   */

+#define SDMMC_STA_DHOLD_Pos              (9U)

+#define SDMMC_STA_DHOLD_Msk              (0x1UL << SDMMC_STA_DHOLD_Pos)        /*!< 0x00000200 */

+#define SDMMC_STA_DHOLD                  SDMMC_STA_DHOLD_Msk                   /*!<Data transfer Hold                                                      */

+#define SDMMC_STA_DBCKEND_Pos            (10U)

+#define SDMMC_STA_DBCKEND_Msk            (0x1UL << SDMMC_STA_DBCKEND_Pos)      /*!< 0x00000400 */

+#define SDMMC_STA_DBCKEND                SDMMC_STA_DBCKEND_Msk                 /*!<Data block sent/received (CRC check passed)   */

+#define SDMMC_STA_DABORT_Pos             (11U)

+#define SDMMC_STA_DABORT_Msk             (0x1UL << SDMMC_STA_DABORT_Pos)       /*!< 0x00000800 */

+#define SDMMC_STA_DABORT                 SDMMC_STA_DABORT_Msk                  /*!<Data transfer aborted by CMD12                                          */

+#define SDMMC_STA_DPSMACT_Pos            (12U)

+#define SDMMC_STA_DPSMACT_Msk            (0x1UL << SDMMC_STA_DPSMACT_Pos)      /*!< 0x00001000 */

+#define SDMMC_STA_DPSMACT                SDMMC_STA_DPSMACT_Msk                 /*!<Data path state machine active                                       */

+#define SDMMC_STA_CPSMACT_Pos            (13U)

+#define SDMMC_STA_CPSMACT_Msk            (0x1UL << SDMMC_STA_CPSMACT_Pos)      /*!< 0x00002000 */

+#define SDMMC_STA_CPSMACT                SDMMC_STA_CPSMACT_Msk                 /*!<Command path state machine active                                          */

+#define SDMMC_STA_TXFIFOHE_Pos           (14U)

+#define SDMMC_STA_TXFIFOHE_Msk           (0x1UL << SDMMC_STA_TXFIFOHE_Pos)     /*!< 0x00004000 */

+#define SDMMC_STA_TXFIFOHE               SDMMC_STA_TXFIFOHE_Msk                /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */

+#define SDMMC_STA_RXFIFOHF_Pos           (15U)

+#define SDMMC_STA_RXFIFOHF_Msk           (0x1UL << SDMMC_STA_RXFIFOHF_Pos)     /*!< 0x00008000 */

+#define SDMMC_STA_RXFIFOHF               SDMMC_STA_RXFIFOHF_Msk                /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */

+#define SDMMC_STA_TXFIFOF_Pos            (16U)

+#define SDMMC_STA_TXFIFOF_Msk            (0x1UL << SDMMC_STA_TXFIFOF_Pos)      /*!< 0x00010000 */

+#define SDMMC_STA_TXFIFOF                SDMMC_STA_TXFIFOF_Msk                 /*!<Transmit FIFO full                            */

+#define SDMMC_STA_RXFIFOF_Pos            (17U)

+#define SDMMC_STA_RXFIFOF_Msk            (0x1UL << SDMMC_STA_RXFIFOF_Pos)      /*!< 0x00020000 */

+#define SDMMC_STA_RXFIFOF                SDMMC_STA_RXFIFOF_Msk                 /*!<Receive FIFO full                             */

+#define SDMMC_STA_TXFIFOE_Pos            (18U)

+#define SDMMC_STA_TXFIFOE_Msk            (0x1UL << SDMMC_STA_TXFIFOE_Pos)      /*!< 0x00040000 */

+#define SDMMC_STA_TXFIFOE                SDMMC_STA_TXFIFOE_Msk                 /*!<Transmit FIFO empty                           */

+#define SDMMC_STA_RXFIFOE_Pos            (19U)

+#define SDMMC_STA_RXFIFOE_Msk            (0x1UL << SDMMC_STA_RXFIFOE_Pos)      /*!< 0x00080000 */

+#define SDMMC_STA_RXFIFOE                SDMMC_STA_RXFIFOE_Msk                 /*!<Receive FIFO empty                            */

+#define SDMMC_STA_BUSYD0_Pos             (20U)

+#define SDMMC_STA_BUSYD0_Msk             (0x1UL << SDMMC_STA_BUSYD0_Pos)       /*!< 0x00100000 */

+#define SDMMC_STA_BUSYD0                 SDMMC_STA_BUSYD0_Msk                  /*!<Inverted value of SDMMC_D0 line (Busy)                                  */

+#define SDMMC_STA_BUSYD0END_Pos          (21U)

+#define SDMMC_STA_BUSYD0END_Msk          (0x1UL << SDMMC_STA_BUSYD0END_Pos)    /*!< 0x00200000 */

+#define SDMMC_STA_BUSYD0END              SDMMC_STA_BUSYD0END_Msk               /*!<End of SDMMC_D0 Busy following a CMD response detected                  */

+#define SDMMC_STA_SDIOIT_Pos             (22U)

+#define SDMMC_STA_SDIOIT_Msk             (0x1UL << SDMMC_STA_SDIOIT_Pos)       /*!< 0x00400000 */

+#define SDMMC_STA_SDIOIT                 SDMMC_STA_SDIOIT_Msk                  /*!<SDIO interrupt received                                                 */

+#define SDMMC_STA_ACKFAIL_Pos            (23U)

+#define SDMMC_STA_ACKFAIL_Msk            (0x1UL << SDMMC_STA_ACKFAIL_Pos)      /*!< 0x00800000 */

+#define SDMMC_STA_ACKFAIL                SDMMC_STA_ACKFAIL_Msk                 /*!<Boot Acknowledgment received (BootAck check fail)                       */

+#define SDMMC_STA_ACKTIMEOUT_Pos         (24U)

+#define SDMMC_STA_ACKTIMEOUT_Msk         (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)   /*!< 0x01000000 */

+#define SDMMC_STA_ACKTIMEOUT             SDMMC_STA_ACKTIMEOUT_Msk              /*!<Boot Acknowledgment timeout                                             */

+#define SDMMC_STA_VSWEND_Pos             (25U)

+#define SDMMC_STA_VSWEND_Msk             (0x1UL << SDMMC_STA_VSWEND_Pos)       /*!< 0x02000000 */

+#define SDMMC_STA_VSWEND                 SDMMC_STA_VSWEND_Msk                  /*!<Voltage switch critical timing section completion                       */

+#define SDMMC_STA_CKSTOP_Pos             (26U)

+#define SDMMC_STA_CKSTOP_Msk             (0x1UL << SDMMC_STA_CKSTOP_Pos)       /*!< 0x04000000 */

+#define SDMMC_STA_CKSTOP                 SDMMC_STA_CKSTOP_Msk                  /*!<SDMMC_CK stopped in Voltage switch procedure                            */

+#define SDMMC_STA_IDMATE_Pos             (27U)

+#define SDMMC_STA_IDMATE_Msk             (0x1UL << SDMMC_STA_IDMATE_Pos)       /*!< 0x08000000 */

+#define SDMMC_STA_IDMATE                 SDMMC_STA_IDMATE_Msk                  /*!<IDMA transfer error                                                     */

+#define SDMMC_STA_IDMABTC_Pos            (28U)

+#define SDMMC_STA_IDMABTC_Msk            (0x1UL << SDMMC_STA_IDMABTC_Pos)      /*!< 0x10000000 */

+#define SDMMC_STA_IDMABTC                SDMMC_STA_IDMABTC_Msk                 /*!<IDMA buffer transfer complete                                           */

+

+/*******************  Bit definition for SDMMC_ICR register  *******************/

+#define SDMMC_ICR_CCRCFAILC_Pos          (0U)

+#define SDMMC_ICR_CCRCFAILC_Msk          (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)    /*!< 0x00000001 */

+#define SDMMC_ICR_CCRCFAILC              SDMMC_ICR_CCRCFAILC_Msk               /*!<CCRCFAIL flag clear bit */

+#define SDMMC_ICR_DCRCFAILC_Pos          (1U)

+#define SDMMC_ICR_DCRCFAILC_Msk          (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)    /*!< 0x00000002 */

+#define SDMMC_ICR_DCRCFAILC              SDMMC_ICR_DCRCFAILC_Msk               /*!<DCRCFAIL flag clear bit */

+#define SDMMC_ICR_CTIMEOUTC_Pos          (2U)

+#define SDMMC_ICR_CTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)    /*!< 0x00000004 */

+#define SDMMC_ICR_CTIMEOUTC              SDMMC_ICR_CTIMEOUTC_Msk               /*!<CTIMEOUT flag clear bit */

+#define SDMMC_ICR_DTIMEOUTC_Pos          (3U)

+#define SDMMC_ICR_DTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)    /*!< 0x00000008 */

+#define SDMMC_ICR_DTIMEOUTC              SDMMC_ICR_DTIMEOUTC_Msk               /*!<DTIMEOUT flag clear bit */

+#define SDMMC_ICR_TXUNDERRC_Pos          (4U)

+#define SDMMC_ICR_TXUNDERRC_Msk          (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)    /*!< 0x00000010 */

+#define SDMMC_ICR_TXUNDERRC              SDMMC_ICR_TXUNDERRC_Msk               /*!<TXUNDERR flag clear bit */

+#define SDMMC_ICR_RXOVERRC_Pos           (5U)

+#define SDMMC_ICR_RXOVERRC_Msk           (0x1UL << SDMMC_ICR_RXOVERRC_Pos)     /*!< 0x00000020 */

+#define SDMMC_ICR_RXOVERRC               SDMMC_ICR_RXOVERRC_Msk                /*!<RXOVERR flag clear bit  */

+#define SDMMC_ICR_CMDRENDC_Pos           (6U)

+#define SDMMC_ICR_CMDRENDC_Msk           (0x1UL << SDMMC_ICR_CMDRENDC_Pos)     /*!< 0x00000040 */

+#define SDMMC_ICR_CMDRENDC               SDMMC_ICR_CMDRENDC_Msk                /*!<CMDREND flag clear bit  */

+#define SDMMC_ICR_CMDSENTC_Pos           (7U)

+#define SDMMC_ICR_CMDSENTC_Msk           (0x1UL << SDMMC_ICR_CMDSENTC_Pos)     /*!< 0x00000080 */

+#define SDMMC_ICR_CMDSENTC               SDMMC_ICR_CMDSENTC_Msk                /*!<CMDSENT flag clear bit  */

+#define SDMMC_ICR_DATAENDC_Pos           (8U)

+#define SDMMC_ICR_DATAENDC_Msk           (0x1UL << SDMMC_ICR_DATAENDC_Pos)     /*!< 0x00000100 */

+#define SDMMC_ICR_DATAENDC               SDMMC_ICR_DATAENDC_Msk                /*!<DATAEND flag clear bit  */

+#define SDMMC_ICR_DHOLDC_Pos             (9U)

+#define SDMMC_ICR_DHOLDC_Msk             (0x1UL << SDMMC_ICR_DHOLDC_Pos)       /*!< 0x00000200 */

+#define SDMMC_ICR_DHOLDC                 SDMMC_ICR_DHOLDC_Msk                  /*!<DHOLD flag clear bit       */

+#define SDMMC_ICR_DBCKENDC_Pos           (10U)

+#define SDMMC_ICR_DBCKENDC_Msk           (0x1UL << SDMMC_ICR_DBCKENDC_Pos)     /*!< 0x00000400 */

+#define SDMMC_ICR_DBCKENDC               SDMMC_ICR_DBCKENDC_Msk                /*!<DBCKEND flag clear bit  */

+#define SDMMC_ICR_DABORTC_Pos            (11U)

+#define SDMMC_ICR_DABORTC_Msk            (0x1UL << SDMMC_ICR_DABORTC_Pos)      /*!< 0x00000800 */

+#define SDMMC_ICR_DABORTC                SDMMC_ICR_DABORTC_Msk                 /*!<DABORTC flag clear bit     */

+#define SDMMC_ICR_BUSYD0ENDC_Pos         (21U)

+#define SDMMC_ICR_BUSYD0ENDC_Msk         (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)   /*!< 0x00200000 */

+#define SDMMC_ICR_BUSYD0ENDC             SDMMC_ICR_BUSYD0ENDC_Msk              /*!<BUSYD0ENDC flag clear bit  */

+#define SDMMC_ICR_SDIOITC_Pos            (22U)

+#define SDMMC_ICR_SDIOITC_Msk            (0x1UL << SDMMC_ICR_SDIOITC_Pos)      /*!< 0x00400000 */

+#define SDMMC_ICR_SDIOITC                SDMMC_ICR_SDIOITC_Msk                 /*!<SDIOIT flag clear bit      */

+#define SDMMC_ICR_ACKFAILC_Pos           (23U)

+#define SDMMC_ICR_ACKFAILC_Msk           (0x1UL << SDMMC_ICR_ACKFAILC_Pos)     /*!< 0x00800000 */

+#define SDMMC_ICR_ACKFAILC               SDMMC_ICR_ACKFAILC_Msk                /*!<ACKFAILC flag clear bit    */

+#define SDMMC_ICR_ACKTIMEOUTC_Pos        (24U)

+#define SDMMC_ICR_ACKTIMEOUTC_Msk        (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)  /*!< 0x01000000 */

+#define SDMMC_ICR_ACKTIMEOUTC            SDMMC_ICR_ACKTIMEOUTC_Msk             /*!<ACKTIMEOUTC flag clear bit */

+#define SDMMC_ICR_VSWENDC_Pos            (25U)

+#define SDMMC_ICR_VSWENDC_Msk            (0x1UL << SDMMC_ICR_VSWENDC_Pos)      /*!< 0x02000000 */

+#define SDMMC_ICR_VSWENDC                SDMMC_ICR_VSWENDC_Msk                 /*!<VSWENDC flag clear bit     */

+#define SDMMC_ICR_CKSTOPC_Pos            (26U)

+#define SDMMC_ICR_CKSTOPC_Msk            (0x1UL << SDMMC_ICR_CKSTOPC_Pos)      /*!< 0x04000000 */

+#define SDMMC_ICR_CKSTOPC                SDMMC_ICR_CKSTOPC_Msk                 /*!<CKSTOPC flag clear bit     */

+#define SDMMC_ICR_IDMATEC_Pos            (27U)

+#define SDMMC_ICR_IDMATEC_Msk            (0x1UL << SDMMC_ICR_IDMATEC_Pos)      /*!< 0x08000000 */

+#define SDMMC_ICR_IDMATEC                SDMMC_ICR_IDMATEC_Msk                 /*!<IDMATEC flag clear bit     */

+#define SDMMC_ICR_IDMABTCC_Pos           (28U)

+#define SDMMC_ICR_IDMABTCC_Msk           (0x1UL << SDMMC_ICR_IDMABTCC_Pos)     /*!< 0x10000000 */

+#define SDMMC_ICR_IDMABTCC               SDMMC_ICR_IDMABTCC_Msk                /*!<IDMABTCC flag clear bit    */

+

+/******************  Bit definition for SDMMC_MASK register  *******************/

+#define SDMMC_MASK_CCRCFAILIE_Pos        (0U)

+#define SDMMC_MASK_CCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)  /*!< 0x00000001 */

+#define SDMMC_MASK_CCRCFAILIE            SDMMC_MASK_CCRCFAILIE_Msk             /*!<Command CRC Fail Interrupt Enable          */

+#define SDMMC_MASK_DCRCFAILIE_Pos        (1U)

+#define SDMMC_MASK_DCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)  /*!< 0x00000002 */

+#define SDMMC_MASK_DCRCFAILIE            SDMMC_MASK_DCRCFAILIE_Msk             /*!<Data CRC Fail Interrupt Enable             */

+#define SDMMC_MASK_CTIMEOUTIE_Pos        (2U)

+#define SDMMC_MASK_CTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)  /*!< 0x00000004 */

+#define SDMMC_MASK_CTIMEOUTIE            SDMMC_MASK_CTIMEOUTIE_Msk             /*!<Command TimeOut Interrupt Enable           */

+#define SDMMC_MASK_DTIMEOUTIE_Pos        (3U)

+#define SDMMC_MASK_DTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)  /*!< 0x00000008 */

+#define SDMMC_MASK_DTIMEOUTIE            SDMMC_MASK_DTIMEOUTIE_Msk             /*!<Data TimeOut Interrupt Enable              */

+#define SDMMC_MASK_TXUNDERRIE_Pos        (4U)

+#define SDMMC_MASK_TXUNDERRIE_Msk        (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)  /*!< 0x00000010 */

+#define SDMMC_MASK_TXUNDERRIE            SDMMC_MASK_TXUNDERRIE_Msk             /*!<Tx FIFO UnderRun Error Interrupt Enable    */

+#define SDMMC_MASK_RXOVERRIE_Pos         (5U)

+#define SDMMC_MASK_RXOVERRIE_Msk         (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)   /*!< 0x00000020 */

+#define SDMMC_MASK_RXOVERRIE             SDMMC_MASK_RXOVERRIE_Msk              /*!<Rx FIFO OverRun Error Interrupt Enable     */

+#define SDMMC_MASK_CMDRENDIE_Pos         (6U)

+#define SDMMC_MASK_CMDRENDIE_Msk         (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)   /*!< 0x00000040 */

+#define SDMMC_MASK_CMDRENDIE             SDMMC_MASK_CMDRENDIE_Msk              /*!<Command Response Received Interrupt Enable */

+#define SDMMC_MASK_CMDSENTIE_Pos         (7U)

+#define SDMMC_MASK_CMDSENTIE_Msk         (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)   /*!< 0x00000080 */

+#define SDMMC_MASK_CMDSENTIE             SDMMC_MASK_CMDSENTIE_Msk              /*!<Command Sent Interrupt Enable              */

+#define SDMMC_MASK_DATAENDIE_Pos         (8U)

+#define SDMMC_MASK_DATAENDIE_Msk         (0x1UL << SDMMC_MASK_DATAENDIE_Pos)   /*!< 0x00000100 */

+#define SDMMC_MASK_DATAENDIE             SDMMC_MASK_DATAENDIE_Msk              /*!<Data End Interrupt Enable                  */

+#define SDMMC_MASK_DHOLDIE_Pos           (9U)

+#define SDMMC_MASK_DHOLDIE_Msk           (0x1UL << SDMMC_MASK_DHOLDIE_Pos)     /*!< 0x00000200 */

+#define SDMMC_MASK_DHOLDIE               SDMMC_MASK_DHOLDIE_Msk                /*!<Data Hold Interrupt Enable                 */

+#define SDMMC_MASK_DBCKENDIE_Pos         (10U)

+#define SDMMC_MASK_DBCKENDIE_Msk         (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)   /*!< 0x00000400 */

+#define SDMMC_MASK_DBCKENDIE             SDMMC_MASK_DBCKENDIE_Msk              /*!<Data Block End Interrupt Enable            */

+#define SDMMC_MASK_DABORTIE_Pos          (11U)

+#define SDMMC_MASK_DABORTIE_Msk          (0x1UL << SDMMC_MASK_DABORTIE_Pos)    /*!< 0x00000800 */

+#define SDMMC_MASK_DABORTIE              SDMMC_MASK_DABORTIE_Msk               /*!<Data transfer aborted interrupt enable     */

+

+#define SDMMC_MASK_TXFIFOHEIE_Pos        (14U)

+#define SDMMC_MASK_TXFIFOHEIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)  /*!< 0x00004000 */

+#define SDMMC_MASK_TXFIFOHEIE            SDMMC_MASK_TXFIFOHEIE_Msk             /*!<Tx FIFO Half Empty interrupt Enable        */

+#define SDMMC_MASK_RXFIFOHFIE_Pos        (15U)

+#define SDMMC_MASK_RXFIFOHFIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)  /*!< 0x00008000 */

+#define SDMMC_MASK_RXFIFOHFIE            SDMMC_MASK_RXFIFOHFIE_Msk             /*!<Rx FIFO Half Full interrupt Enable         */

+

+#define SDMMC_MASK_RXFIFOFIE_Pos         (17U)

+#define SDMMC_MASK_RXFIFOFIE_Msk         (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)   /*!< 0x00020000 */

+#define SDMMC_MASK_RXFIFOFIE             SDMMC_MASK_RXFIFOFIE_Msk              /*!<Rx FIFO Full interrupt Enable              */

+#define SDMMC_MASK_TXFIFOEIE_Pos         (18U)

+#define SDMMC_MASK_TXFIFOEIE_Msk         (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)   /*!< 0x00040000 */

+#define SDMMC_MASK_TXFIFOEIE             SDMMC_MASK_TXFIFOEIE_Msk              /*!<Tx FIFO Empty interrupt Enable             */

+

+#define SDMMC_MASK_BUSYD0ENDIE_Pos       (21U)

+#define SDMMC_MASK_BUSYD0ENDIE_Msk       (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */

+#define SDMMC_MASK_BUSYD0ENDIE           SDMMC_MASK_BUSYD0ENDIE_Msk            /*!<BUSYD0ENDIE interrupt Enable */

+#define SDMMC_MASK_SDIOITIE_Pos           (22U)

+#define SDMMC_MASK_SDIOITIE_Msk           (0x1UL << SDMMC_MASK_SDIOITIE_Pos)     /*!< 0x00400000 */

+#define SDMMC_MASK_SDIOITIE               SDMMC_MASK_SDIOITIE_Msk                /*!<SDMMC Mode Interrupt Received interrupt Enable */

+#define SDMMC_MASK_ACKFAILIE_Pos         (23U)

+#define SDMMC_MASK_ACKFAILIE_Msk         (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)   /*!< 0x00800000 */

+#define SDMMC_MASK_ACKFAILIE             SDMMC_MASK_ACKFAILIE_Msk              /*!<Acknowledgment Fail Interrupt Enable */

+#define SDMMC_MASK_ACKTIMEOUTIE_Pos      (24U)

+#define SDMMC_MASK_ACKTIMEOUTIE_Msk      (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */

+#define SDMMC_MASK_ACKTIMEOUTIE          SDMMC_MASK_ACKTIMEOUTIE_Msk           /*!<Acknowledgment timeout Interrupt Enable */

+#define SDMMC_MASK_VSWENDIE_Pos          (25U)

+#define SDMMC_MASK_VSWENDIE_Msk          (0x1UL << SDMMC_MASK_VSWENDIE_Pos)    /*!< 0x02000000 */

+#define SDMMC_MASK_VSWENDIE              SDMMC_MASK_VSWENDIE_Msk               /*!<Voltage switch critical timing section completion Interrupt Enable */

+#define SDMMC_MASK_CKSTOPIE_Pos          (26U)

+#define SDMMC_MASK_CKSTOPIE_Msk          (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)    /*!< 0x04000000 */

+#define SDMMC_MASK_CKSTOPIE              SDMMC_MASK_CKSTOPIE_Msk               /*!<Voltage Switch clock stopped Interrupt Enable */

+#define SDMMC_MASK_IDMABTCIE_Pos         (28U)

+#define SDMMC_MASK_IDMABTCIE_Msk         (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)   /*!< 0x10000000 */

+#define SDMMC_MASK_IDMABTCIE             SDMMC_MASK_IDMABTCIE_Msk              /*!<IDMA buffer transfer complete Interrupt Enable */

+

+/*****************  Bit definition for SDMMC_ACKTIME register  *****************/

+#define SDMMC_ACKTIME_ACKTIME_Pos        (0U)

+#define SDMMC_ACKTIME_ACKTIME_Msk        (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_ACKTIME_ACKTIME            SDMMC_ACKTIME_ACKTIME_Msk             /*!<Boot acknowledgment timeout period */

+

+/******************  Bit definition for SDMMC_FIFO register  *******************/

+#define SDMMC_FIFO_FIFODATA_Pos          (0U)

+#define SDMMC_FIFO_FIFODATA_Msk          (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_FIFO_FIFODATA              SDMMC_FIFO_FIFODATA_Msk               /*!<Receive and transmit FIFO data */

+

+/******************  Bit definition for SDMMC_IDMACTRL register ****************/

+#define SDMMC_IDMA_IDMAEN_Pos            (0U)

+#define SDMMC_IDMA_IDMAEN_Msk            (0x1UL << SDMMC_IDMA_IDMAEN_Pos)      /*!< 0x00000001 */

+#define SDMMC_IDMA_IDMAEN                SDMMC_IDMA_IDMAEN_Msk                 /*!< Enable the internal DMA of the SDMMC peripheral */

+#define SDMMC_IDMA_IDMABMODE_Pos         (1U)

+#define SDMMC_IDMA_IDMABMODE_Msk         (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)   /*!< 0x00000002 */

+#define SDMMC_IDMA_IDMABMODE             SDMMC_IDMA_IDMABMODE_Msk              /*!< Enable double buffer mode for IDMA */

+#define SDMMC_IDMA_IDMABACT_Pos          (2U)

+#define SDMMC_IDMA_IDMABACT_Msk          (0x1UL << SDMMC_IDMA_IDMABACT_Pos)    /*!< 0x00000004 */

+#define SDMMC_IDMA_IDMABACT              SDMMC_IDMA_IDMABACT_Msk               /*!< Uses buffer 1 when double buffer mode is selected */

+

+/*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/

+#define SDMMC_IDMABSIZE_IDMABNDT_Pos     (5U)

+#define SDMMC_IDMABSIZE_IDMABNDT_Msk     (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */

+#define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */

+

+/*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/

+#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */

+

+/*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/

+#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                        Delay Block Interface (DLYB)                        */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for DLYB_CR register  ********************/

+#define DLYB_CR_DEN_Pos         (0U)

+#define DLYB_CR_DEN_Msk         (0x1UL << DLYB_CR_DEN_Pos)                     /*!< 0x00000001 */

+#define DLYB_CR_DEN             DLYB_CR_DEN_Msk                                /*!<Delay Block enable */

+#define DLYB_CR_SEN_Pos         (1U)

+#define DLYB_CR_SEN_Msk         (0x1UL << DLYB_CR_SEN_Pos)                     /*!< 0x00000002 */

+#define DLYB_CR_SEN             DLYB_CR_SEN_Msk                                /*!<Sampler length enable */

+

+

+/*******************  Bit definition for DLYB_CFGR register  ********************/

+#define DLYB_CFGR_SEL_Pos       (0U)

+#define DLYB_CFGR_SEL_Msk       (0xFUL << DLYB_CFGR_SEL_Pos)                   /*!< 0x0000000F */

+#define DLYB_CFGR_SEL           DLYB_CFGR_SEL_Msk                              /*!<Select the phase for the Output clock[3:0] */

+#define DLYB_CFGR_SEL_0         (0x1UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000001 */

+#define DLYB_CFGR_SEL_1         (0x2UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000002 */

+#define DLYB_CFGR_SEL_2         (0x3UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000003 */

+#define DLYB_CFGR_SEL_3         (0x8UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000008 */

+

+#define DLYB_CFGR_UNIT_Pos      (8U)

+#define DLYB_CFGR_UNIT_Msk      (0x7FUL << DLYB_CFGR_UNIT_Pos)                 /*!< 0x00007F00 */

+#define DLYB_CFGR_UNIT          DLYB_CFGR_UNIT_Msk                             /*!<Delay Defines the delay of a Unit delay cell[6:0] */

+#define DLYB_CFGR_UNIT_0        (0x01UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000100 */

+#define DLYB_CFGR_UNIT_1        (0x02UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000200 */

+#define DLYB_CFGR_UNIT_2        (0x04UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000400 */

+#define DLYB_CFGR_UNIT_3        (0x08UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000800 */

+#define DLYB_CFGR_UNIT_4        (0x10UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00001000 */

+#define DLYB_CFGR_UNIT_5        (0x20UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00002000 */

+#define DLYB_CFGR_UNIT_6        (0x40UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00004000 */

+

+#define DLYB_CFGR_LNG_Pos       (16U)

+#define DLYB_CFGR_LNG_Msk       (0xFFFUL << DLYB_CFGR_LNG_Pos)                 /*!< 0x0FFF0000 */

+#define DLYB_CFGR_LNG           DLYB_CFGR_LNG_Msk                              /*!<Delay line length value[11:0] */

+#define DLYB_CFGR_LNG_0         (0x001UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00010000 */

+#define DLYB_CFGR_LNG_1         (0x002UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00020000 */

+#define DLYB_CFGR_LNG_2         (0x004UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00040000 */

+#define DLYB_CFGR_LNG_3         (0x008UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00080000 */

+#define DLYB_CFGR_LNG_4         (0x010UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00100000 */

+#define DLYB_CFGR_LNG_5         (0x020UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00200000 */

+#define DLYB_CFGR_LNG_6         (0x040UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00400000 */

+#define DLYB_CFGR_LNG_7         (0x080UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00800000 */

+#define DLYB_CFGR_LNG_8         (0x100UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x01000000 */

+#define DLYB_CFGR_LNG_9         (0x200UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x02000000 */

+#define DLYB_CFGR_LNG_10        (0x400UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x04000000 */

+#define DLYB_CFGR_LNG_11        (0x800UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x08000000 */

+

+#define DLYB_CFGR_LNGF_Pos      (31U)

+#define DLYB_CFGR_LNGF_Msk      (0x1UL << DLYB_CFGR_LNGF_Pos)                  /*!< 0x80000000 */

+#define DLYB_CFGR_LNGF          DLYB_CFGR_LNGF_Msk                             /*!<Length valid flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                   Serial Peripheral Interface (SPI/I2S)                    */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for SPI_CR1 register  ********************/

+#define SPI_CR1_SPE_Pos             (0U)

+#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000001 */

+#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<Serial Peripheral Enable                         */

+#define SPI_CR1_MASRX_Pos           (8U)

+#define SPI_CR1_MASRX_Msk           (0x1UL << SPI_CR1_MASRX_Pos)               /*!< 0x00000100 */

+#define SPI_CR1_MASRX               SPI_CR1_MASRX_Msk                          /*!<Master automatic SUSP in Receive mode            */

+#define SPI_CR1_CSTART_Pos          (9U)

+#define SPI_CR1_CSTART_Msk          (0x1UL << SPI_CR1_CSTART_Pos)              /*!< 0x00000200 */

+#define SPI_CR1_CSTART              SPI_CR1_CSTART_Msk                         /*!<Master transfer start                            */

+#define SPI_CR1_CSUSP_Pos           (10U)

+#define SPI_CR1_CSUSP_Msk           (0x1UL << SPI_CR1_CSUSP_Pos)               /*!< 0x00000400 */

+#define SPI_CR1_CSUSP               SPI_CR1_CSUSP_Msk                          /*!<Master SUSPend request                           */

+#define SPI_CR1_HDDIR_Pos           (11U)

+#define SPI_CR1_HDDIR_Msk           (0x1UL << SPI_CR1_HDDIR_Pos)               /*!< 0x00000800 */

+#define SPI_CR1_HDDIR               SPI_CR1_HDDIR_Msk                          /*!<Rx/Tx direction at Half-duplex mode              */

+#define SPI_CR1_SSI_Pos             (12U)

+#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00001000 */

+#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal SS signal input level                   */

+#define SPI_CR1_CRC33_17_Pos        (13U)

+#define SPI_CR1_CRC33_17_Msk        (0x1UL << SPI_CR1_CRC33_17_Pos)            /*!< 0x00002000 */

+#define SPI_CR1_CRC33_17             SPI_CR1_CRC33_17_Msk                      /*!<32-bit CRC polynomial configuration              */

+#define SPI_CR1_RCRCINI_Pos         (14U)

+#define SPI_CR1_RCRCINI_Msk         (0x1UL << SPI_CR1_RCRCINI_Pos)             /*!< 0x00004000 */

+#define SPI_CR1_RCRCINI             SPI_CR1_RCRCINI_Msk                        /*!<CRC init pattern control for receiver            */

+#define SPI_CR1_TCRCINI_Pos         (15U)

+#define SPI_CR1_TCRCINI_Msk         (0x1UL << SPI_CR1_TCRCINI_Pos)             /*!< 0x00008000 */

+#define SPI_CR1_TCRCINI             SPI_CR1_TCRCINI_Msk                        /*!<CRC init pattern control for transmitter         */

+#define SPI_CR1_IOLOCK_Pos          (16U)

+#define SPI_CR1_IOLOCK_Msk          (0x1UL << SPI_CR1_IOLOCK_Pos)              /*!< 0x00010000 */

+#define SPI_CR1_IOLOCK              SPI_CR1_IOLOCK_Msk                         /*!<Locking the AF configuration of associated IOs   */

+

+/*******************  Bit definition for SPI_CR2 register  ********************/

+#define SPI_CR2_TSER_Pos            (16U)

+#define SPI_CR2_TSER_Msk            (0xFFFFUL << SPI_CR2_TSER_Pos)             /*!< 0xFFFF0000 */

+#define SPI_CR2_TSER                SPI_CR2_TSER_Msk                           /*!<Number of data transfer extension                */

+#define SPI_CR2_TSIZE_Pos           (0U)

+#define SPI_CR2_TSIZE_Msk           (0xFFFFUL << SPI_CR2_TSIZE_Pos)            /*!< 0x0000FFFF */

+#define SPI_CR2_TSIZE               SPI_CR2_TSIZE_Msk                          /*!<Number of data at current transfer               */

+

+/*******************  Bit definition for SPI_CFG1 register  ********************/

+#define SPI_CFG1_DSIZE_Pos          (0U)

+#define SPI_CFG1_DSIZE_Msk          (0x1FUL << SPI_CFG1_DSIZE_Pos)             /*!< 0x0000001F */

+#define SPI_CFG1_DSIZE              SPI_CFG1_DSIZE_Msk                         /*!<DSIZE[4:0]: Bits number in single SPI data frame */

+#define SPI_CFG1_DSIZE_0            (0x01UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000001 */

+#define SPI_CFG1_DSIZE_1            (0x02UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000002 */

+#define SPI_CFG1_DSIZE_2            (0x04UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000004 */

+#define SPI_CFG1_DSIZE_3            (0x08UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000008 */

+#define SPI_CFG1_DSIZE_4            (0x10UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000010 */

+

+#define SPI_CFG1_FTHLV_Pos          (5U)

+#define SPI_CFG1_FTHLV_Msk          (0xFUL << SPI_CFG1_FTHLV_Pos)              /*!< 0x000001E0 */

+#define SPI_CFG1_FTHLV              SPI_CFG1_FTHLV_Msk                         /*!<FTHVL [3:0]: FIFO threshold level*/

+#define SPI_CFG1_FTHLV_0            (0x1UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000020 */

+#define SPI_CFG1_FTHLV_1            (0x2UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000040 */

+#define SPI_CFG1_FTHLV_2            (0x4UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000080 */

+#define SPI_CFG1_FTHLV_3            (0x8UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000100 */

+

+#define SPI_CFG1_UDRCFG_Pos         (9U)

+#define SPI_CFG1_UDRCFG_Msk         (0x3UL << SPI_CFG1_UDRCFG_Pos)             /*!< 0x00000600 */

+#define SPI_CFG1_UDRCFG             SPI_CFG1_UDRCFG_Msk                        /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */

+#define SPI_CFG1_UDRCFG_0           (0x1UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000200 */

+#define SPI_CFG1_UDRCFG_1           (0x2UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000400 */

+

+

+#define SPI_CFG1_UDRDET_Pos         (11U)

+#define SPI_CFG1_UDRDET_Msk         (0x3UL << SPI_CFG1_UDRDET_Pos)             /*!< 0x00001800 */

+#define SPI_CFG1_UDRDET             SPI_CFG1_UDRDET_Msk                        /*!<UDRDET[1:0]: Detection of underrun condition     */

+#define SPI_CFG1_UDRDET_0           (0x1UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00000800 */

+#define SPI_CFG1_UDRDET_1           (0x2UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00001000 */

+

+#define SPI_CFG1_RXDMAEN_Pos        (14U)

+#define SPI_CFG1_RXDMAEN_Msk        (0x1UL << SPI_CFG1_RXDMAEN_Pos)            /*!< 0x00004000 */

+#define SPI_CFG1_RXDMAEN            SPI_CFG1_RXDMAEN_Msk                       /*!<Rx DMA stream enable                */

+#define SPI_CFG1_TXDMAEN_Pos        (15U)

+#define SPI_CFG1_TXDMAEN_Msk        (0x1UL << SPI_CFG1_TXDMAEN_Pos)            /*!< 0x00008000 */

+#define SPI_CFG1_TXDMAEN            SPI_CFG1_TXDMAEN_Msk                       /*!<Tx DMA stream enable                */

+

+#define SPI_CFG1_CRCSIZE_Pos        (16U)

+#define SPI_CFG1_CRCSIZE_Msk        (0x1FUL << SPI_CFG1_CRCSIZE_Pos)           /*!< 0x001F0000 */

+#define SPI_CFG1_CRCSIZE            SPI_CFG1_CRCSIZE_Msk                       /*!<CRCSIZE [4:0]: Length of CRC frame*/

+#define SPI_CFG1_CRCSIZE_0          (0x01UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00010000 */

+#define SPI_CFG1_CRCSIZE_1          (0x02UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00020000 */

+#define SPI_CFG1_CRCSIZE_2          (0x04UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00040000 */

+#define SPI_CFG1_CRCSIZE_3          (0x08UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00080000 */

+#define SPI_CFG1_CRCSIZE_4          (0x10UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00100000 */

+

+#define SPI_CFG1_CRCEN_Pos          (22U)

+#define SPI_CFG1_CRCEN_Msk          (0x1UL << SPI_CFG1_CRCEN_Pos)              /*!< 0x00400000 */

+#define SPI_CFG1_CRCEN              SPI_CFG1_CRCEN_Msk                         /*!<Hardware CRC computation enable */

+

+#define SPI_CFG1_MBR_Pos            (28U)

+#define SPI_CFG1_MBR_Msk            (0x7UL << SPI_CFG1_MBR_Pos)                /*!< 0x70000000 */

+#define SPI_CFG1_MBR                SPI_CFG1_MBR_Msk                           /*!<Master baud rate                */

+#define SPI_CFG1_MBR_0              (0x1UL << SPI_CFG1_MBR_Pos)                 /*!< 0x10000000 */

+#define SPI_CFG1_MBR_1              (0x2UL << SPI_CFG1_MBR_Pos)                 /*!< 0x20000000 */

+#define SPI_CFG1_MBR_2              (0x4UL << SPI_CFG1_MBR_Pos)                 /*!< 0x40000000 */

+

+/*******************  Bit definition for SPI_CFG2 register  ********************/

+#define SPI_CFG2_MSSI_Pos           (0U)

+#define SPI_CFG2_MSSI_Msk           (0xFUL << SPI_CFG2_MSSI_Pos)               /*!< 0x0000000F */

+#define SPI_CFG2_MSSI               SPI_CFG2_MSSI_Msk                          /*!<Master SS Idleness */

+#define SPI_CFG2_MSSI_0             (0x1UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000001 */

+#define SPI_CFG2_MSSI_1             (0x2UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000002 */

+#define SPI_CFG2_MSSI_2             (0x4UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000004 */

+#define SPI_CFG2_MSSI_3             (0x8UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000008 */

+

+#define SPI_CFG2_MIDI_Pos           (4U)

+#define SPI_CFG2_MIDI_Msk           (0xFUL << SPI_CFG2_MIDI_Pos)               /*!< 0x000000F0 */

+#define SPI_CFG2_MIDI               SPI_CFG2_MIDI_Msk                          /*!<Master Inter-Data Idleness */

+#define SPI_CFG2_MIDI_0             (0x1UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000010 */

+#define SPI_CFG2_MIDI_1             (0x2UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000020 */

+#define SPI_CFG2_MIDI_2             (0x4UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000040 */

+#define SPI_CFG2_MIDI_3             (0x8UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000080 */

+

+#define SPI_CFG2_IOSWP_Pos          (15U)

+#define SPI_CFG2_IOSWP_Msk          (0x1UL << SPI_CFG2_IOSWP_Pos)              /*!< 0x00008000 */

+#define SPI_CFG2_IOSWP              SPI_CFG2_IOSWP_Msk                         /*!<Swap functionality of MISO and MOSI pins */

+

+#define SPI_CFG2_COMM_Pos           (17U)

+#define SPI_CFG2_COMM_Msk           (0x3UL << SPI_CFG2_COMM_Pos)               /*!< 0x00060000 */

+#define SPI_CFG2_COMM               SPI_CFG2_COMM_Msk                          /*!<COMM [1:0]: SPI Communication Mode*/

+#define SPI_CFG2_COMM_0             (0x1UL << SPI_CFG2_COMM_Pos)                /*!< 0x00020000 */

+#define SPI_CFG2_COMM_1             (0x2UL << SPI_CFG2_COMM_Pos)                /*!< 0x00040000 */

+

+#define SPI_CFG2_SP_Pos             (19U)

+#define SPI_CFG2_SP_Msk             (0x7UL << SPI_CFG2_SP_Pos)                 /*!< 0x00380000 */

+#define SPI_CFG2_SP                 SPI_CFG2_SP_Msk                            /*!<SP[2:0]: Serial Protocol */

+#define SPI_CFG2_SP_0               (0x1UL << SPI_CFG2_SP_Pos)                  /*!< 0x00080000 */

+#define SPI_CFG2_SP_1               (0x2UL << SPI_CFG2_SP_Pos)                  /*!< 0x00100000 */

+#define SPI_CFG2_SP_2               (0x4UL << SPI_CFG2_SP_Pos)                  /*!< 0x00200000 */

+

+#define SPI_CFG2_MASTER_Pos         (22U)

+#define SPI_CFG2_MASTER_Msk         (0x1UL << SPI_CFG2_MASTER_Pos)             /*!< 0x00400000 */

+#define SPI_CFG2_MASTER             SPI_CFG2_MASTER_Msk                        /*!<SPI Master           */

+#define SPI_CFG2_LSBFRST_Pos        (23U)

+#define SPI_CFG2_LSBFRST_Msk        (0x1UL << SPI_CFG2_LSBFRST_Pos)            /*!< 0x00800000 */

+#define SPI_CFG2_LSBFRST            SPI_CFG2_LSBFRST_Msk                       /*!<Data frame format               */

+#define SPI_CFG2_CPHA_Pos           (24U)

+#define SPI_CFG2_CPHA_Msk           (0x1UL << SPI_CFG2_CPHA_Pos)               /*!< 0x01000000 */

+#define SPI_CFG2_CPHA               SPI_CFG2_CPHA_Msk                          /*!<Clock Phase      */

+#define SPI_CFG2_CPOL_Pos           (25U)

+#define SPI_CFG2_CPOL_Msk           (0x1UL << SPI_CFG2_CPOL_Pos)               /*!< 0x02000000 */

+#define SPI_CFG2_CPOL               SPI_CFG2_CPOL_Msk                          /*!<Clock Polarity   */

+#define SPI_CFG2_SSM_Pos            (26U)

+#define SPI_CFG2_SSM_Msk            (0x1UL << SPI_CFG2_SSM_Pos)                /*!< 0x04000000 */

+#define SPI_CFG2_SSM                SPI_CFG2_SSM_Msk                           /*!<Software slave management */

+

+#define SPI_CFG2_SSIOP_Pos          (28U)

+#define SPI_CFG2_SSIOP_Msk          (0x1UL << SPI_CFG2_SSIOP_Pos)              /*!< 0x10000000 */

+#define SPI_CFG2_SSIOP              SPI_CFG2_SSIOP_Msk                         /*!<SS input/output polarity */

+#define SPI_CFG2_SSOE_Pos           (29U)

+#define SPI_CFG2_SSOE_Msk           (0x1UL << SPI_CFG2_SSOE_Pos)               /*!< 0x20000000 */

+#define SPI_CFG2_SSOE               SPI_CFG2_SSOE_Msk                          /*!<SS output enable */

+#define SPI_CFG2_SSOM_Pos           (30U)

+#define SPI_CFG2_SSOM_Msk           (0x1UL << SPI_CFG2_SSOM_Pos)               /*!< 0x40000000 */

+#define SPI_CFG2_SSOM               SPI_CFG2_SSOM_Msk                          /*!<SS output management in master mode */

+

+#define SPI_CFG2_AFCNTR_Pos         (31U)

+#define SPI_CFG2_AFCNTR_Msk         (0x1UL << SPI_CFG2_AFCNTR_Pos)             /*!< 0x80000000 */

+#define SPI_CFG2_AFCNTR             SPI_CFG2_AFCNTR_Msk                        /*!<Alternate function GPIOs control */

+

+/*******************  Bit definition for SPI_IER register  ********************/

+#define SPI_IER_RXPIE_Pos           (0U)

+#define SPI_IER_RXPIE_Msk           (0x1UL << SPI_IER_RXPIE_Pos)               /*!< 0x00000001 */

+#define SPI_IER_RXPIE               SPI_IER_RXPIE_Msk                          /*!<RXP Interrupt Enable            */

+#define SPI_IER_TXPIE_Pos           (1U)

+#define SPI_IER_TXPIE_Msk           (0x1UL << SPI_IER_TXPIE_Pos)               /*!< 0x00000002 */

+#define SPI_IER_TXPIE               SPI_IER_TXPIE_Msk                          /*!<TXP interrupt enable            */

+#define SPI_IER_DXPIE_Pos           (2U)

+#define SPI_IER_DXPIE_Msk           (0x1UL << SPI_IER_DXPIE_Pos)               /*!< 0x00000004 */

+#define SPI_IER_DXPIE               SPI_IER_DXPIE_Msk                          /*!<DXP interrupt enable            */

+#define SPI_IER_EOTIE_Pos           (3U)

+#define SPI_IER_EOTIE_Msk           (0x1UL << SPI_IER_EOTIE_Pos)               /*!< 0x00000008 */

+#define SPI_IER_EOTIE               SPI_IER_EOTIE_Msk                          /*!<EOT/SUSP/TXC interrupt enable   */

+#define SPI_IER_TXTFIE_Pos          (4U)

+#define SPI_IER_TXTFIE_Msk          (0x1UL << SPI_IER_TXTFIE_Pos)              /*!< 0x00000010 */

+#define SPI_IER_TXTFIE              SPI_IER_TXTFIE_Msk                         /*!<TXTF interrupt enable           */

+#define SPI_IER_UDRIE_Pos           (5U)

+#define SPI_IER_UDRIE_Msk           (0x1UL << SPI_IER_UDRIE_Pos)               /*!< 0x00000020 */

+#define SPI_IER_UDRIE               SPI_IER_UDRIE_Msk                          /*!<UDR interrupt enable            */

+#define SPI_IER_OVRIE_Pos           (6U)

+#define SPI_IER_OVRIE_Msk           (0x1UL << SPI_IER_OVRIE_Pos)               /*!< 0x00000040 */

+#define SPI_IER_OVRIE               SPI_IER_OVRIE_Msk                          /*!<OVR interrupt enable            */

+#define SPI_IER_CRCEIE_Pos          (7U)

+#define SPI_IER_CRCEIE_Msk          (0x1UL << SPI_IER_CRCEIE_Pos)               /*!< 0x00000080 */

+#define SPI_IER_CRCEIE              SPI_IER_CRCEIE_Msk                          /*!<CRCE interrupt enable           */

+#define SPI_IER_TIFREIE_Pos         (8U)

+#define SPI_IER_TIFREIE_Msk         (0x1UL << SPI_IER_TIFREIE_Pos)             /*!< 0x00000100 */

+#define SPI_IER_TIFREIE             SPI_IER_TIFREIE_Msk                        /*!<TI Frame Error interrupt enable */

+#define SPI_IER_MODFIE_Pos          (9U)

+#define SPI_IER_MODFIE_Msk          (0x1UL << SPI_IER_MODFIE_Pos)              /*!< 0x00000200 */

+#define SPI_IER_MODFIE              SPI_IER_MODFIE_Msk                         /*!<MODF interrupt enable           */

+#define SPI_IER_TSERFIE_Pos         (10U)

+#define SPI_IER_TSERFIE_Msk         (0x1UL << SPI_IER_TSERFIE_Pos)              /*!< 0x00000400 */

+#define SPI_IER_TSERFIE             SPI_IER_TSERFIE_Msk                        /*!<TSERF interrupt enable          */

+

+/*******************  Bit definition for SPI_SR register  ********************/

+#define SPI_SR_RXP_Pos              (0U)

+#define SPI_SR_RXP_Msk              (0x1UL << SPI_SR_RXP_Pos)                  /*!< 0x00000001 */

+#define SPI_SR_RXP                  SPI_SR_RXP_Msk                             /*!<Rx-Packet available             */

+#define SPI_SR_TXP_Pos              (1U)

+#define SPI_SR_TXP_Msk              (0x1UL << SPI_SR_TXP_Pos)                  /*!< 0x00000002 */

+#define SPI_SR_TXP                  SPI_SR_TXP_Msk                             /*!<Tx-Packet space available       */

+#define SPI_SR_DXP_Pos              (2U)

+#define SPI_SR_DXP_Msk              (0x1UL << SPI_SR_DXP_Pos)                  /*!< 0x00000004 */

+#define SPI_SR_DXP                  SPI_SR_DXP_Msk                             /*!<Duplex Packet available         */

+#define SPI_SR_EOT_Pos              (3U)

+#define SPI_SR_EOT_Msk              (0x1UL << SPI_SR_EOT_Pos)                  /*!< 0x00000008 */

+#define SPI_SR_EOT                  SPI_SR_EOT_Msk                             /*!<Duplex Packet available         */

+#define SPI_SR_TXTF_Pos             (4U)

+#define SPI_SR_TXTF_Msk             (0x1UL << SPI_SR_TXTF_Pos)                 /*!< 0x00000010 */

+#define SPI_SR_TXTF                 SPI_SR_TXTF_Msk                            /*!<Transmission Transfer Filled    */

+#define SPI_SR_UDR_Pos              (5U)

+#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000020 */

+#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<UDR at Slave transmission       */

+#define SPI_SR_OVR_Pos              (6U)

+#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */

+#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Rx-Packet available             */

+#define SPI_SR_CRCE_Pos             (7U)

+#define SPI_SR_CRCE_Msk             (0x1UL << SPI_SR_CRCE_Pos)                 /*!< 0x00000080 */

+#define SPI_SR_CRCE                 SPI_SR_CRCE_Msk                            /*!<CRC Error Detected              */

+#define SPI_SR_TIFRE_Pos            (8U)

+#define SPI_SR_TIFRE_Msk            (0x1UL << SPI_SR_TIFRE_Pos)                /*!< 0x00000100 */

+#define SPI_SR_TIFRE                SPI_SR_TIFRE_Msk                           /*!<TI frame format error Detected  */

+#define SPI_SR_MODF_Pos             (9U)

+#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000200 */

+#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode Fault Detected             */

+#define SPI_SR_TSERF_Pos            (10U)

+#define SPI_SR_TSERF_Msk            (0x1UL << SPI_SR_TSERF_Pos)                /*!< 0x00000400 */

+#define SPI_SR_TSERF                SPI_SR_TSERF_Msk                           /*!<Number of SPI data to be transacted reloaded     */

+#define SPI_SR_SUSP_Pos             (11U)

+#define SPI_SR_SUSP_Msk             (0x1UL << SPI_SR_SUSP_Pos)                 /*!< 0x00000800 */

+#define SPI_SR_SUSP                 SPI_SR_SUSP_Msk                            /*!<SUSP is set by hardware  */

+#define SPI_SR_TXC_Pos              (12U)

+#define SPI_SR_TXC_Msk              (0x1UL << SPI_SR_TXC_Pos)                  /*!< 0x00001000 */

+#define SPI_SR_TXC                  SPI_SR_TXC_Msk                             /*!<TxFIFO transmission complete */

+#define SPI_SR_RXPLVL_Pos           (13U)

+#define SPI_SR_RXPLVL_Msk           (0x3UL << SPI_SR_RXPLVL_Pos)               /*!< 0x00006000 */

+#define SPI_SR_RXPLVL               SPI_SR_RXPLVL_Msk                          /*!<RxFIFO Packing Level                             */

+#define SPI_SR_RXPLVL_0             (0x1UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00002000 */

+#define SPI_SR_RXPLVL_1             (0x2UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00004000 */

+#define SPI_SR_RXWNE_Pos            (15U)

+#define SPI_SR_RXWNE_Msk            (0x1UL << SPI_SR_RXWNE_Pos)                /*!< 0x00008000 */

+#define SPI_SR_RXWNE                SPI_SR_RXWNE_Msk                           /*!<Rx FIFO Word Not Empty                           */

+#define SPI_SR_CTSIZE_Pos           (16U)

+#define SPI_SR_CTSIZE_Msk           (0xFFFFUL << SPI_SR_CTSIZE_Pos)            /*!< 0xFFFF0000 */

+#define SPI_SR_CTSIZE               SPI_SR_CTSIZE_Msk                          /*!<Number of data frames remaining in TSIZE         */

+

+/*******************  Bit definition for SPI_IFCR register  ********************/

+#define SPI_IFCR_EOTC_Pos           (3U)

+#define SPI_IFCR_EOTC_Msk           (0x1UL << SPI_IFCR_EOTC_Pos)               /*!< 0x00000008 */

+#define SPI_IFCR_EOTC               SPI_IFCR_EOTC_Msk                          /*!<End Of Transfer flag clear              */

+#define SPI_IFCR_TXTFC_Pos          (4U)

+#define SPI_IFCR_TXTFC_Msk          (0x1UL << SPI_IFCR_TXTFC_Pos)              /*!< 0x00000010 */

+#define SPI_IFCR_TXTFC              SPI_IFCR_TXTFC_Msk                         /*!<Transmission Transfer Filled flag clear */

+#define SPI_IFCR_UDRC_Pos           (5U)

+#define SPI_IFCR_UDRC_Msk           (0x1UL << SPI_IFCR_UDRC_Pos)               /*!< 0x00000020 */

+#define SPI_IFCR_UDRC               SPI_IFCR_UDRC_Msk                          /*!<Underrun flag clear                     */

+#define SPI_IFCR_OVRC_Pos           (6U)

+#define SPI_IFCR_OVRC_Msk           (0x1UL << SPI_IFCR_OVRC_Pos)               /*!< 0x00000040 */

+#define SPI_IFCR_OVRC               SPI_IFCR_OVRC_Msk                          /*!<Overrun flag clear                      */

+#define SPI_IFCR_CRCEC_Pos          (7U)

+#define SPI_IFCR_CRCEC_Msk          (0x1UL << SPI_IFCR_CRCEC_Pos)              /*!< 0x00000080 */

+#define SPI_IFCR_CRCEC              SPI_IFCR_CRCEC_Msk                         /*!<CRC Error flag clear                    */

+#define SPI_IFCR_TIFREC_Pos         (8U)

+#define SPI_IFCR_TIFREC_Msk         (0x1UL << SPI_IFCR_TIFREC_Pos)             /*!< 0x00000100 */

+#define SPI_IFCR_TIFREC             SPI_IFCR_TIFREC_Msk                        /*!<TI frame format error flag clear        */

+#define SPI_IFCR_MODFC_Pos          (9U)

+#define SPI_IFCR_MODFC_Msk          (0x1UL << SPI_IFCR_MODFC_Pos)              /*!< 0x00000200 */

+#define SPI_IFCR_MODFC              SPI_IFCR_MODFC_Msk                         /*!<Mode Fault flag clear                   */

+#define SPI_IFCR_TSERFC_Pos         (10U)

+#define SPI_IFCR_TSERFC_Msk         (0x1UL << SPI_IFCR_TSERFC_Pos)             /*!< 0x00000400 */

+#define SPI_IFCR_TSERFC             SPI_IFCR_TSERFC_Msk                        /*!<TSERFC flag clear                       */

+#define SPI_IFCR_SUSPC_Pos          (11U)

+#define SPI_IFCR_SUSPC_Msk          (0x1UL << SPI_IFCR_SUSPC_Pos)              /*!< 0x00000800 */

+#define SPI_IFCR_SUSPC              SPI_IFCR_SUSPC_Msk                         /*!<SUSPend flag clear                      */

+

+/*******************  Bit definition for SPI_TXDR register  ********************/

+#define SPI_TXDR_TXDR_Pos           (0U)

+#define SPI_TXDR_TXDR_Msk           (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)        /*!< 0xFFFFFFFF */

+#define SPI_TXDR_TXDR               SPI_TXDR_TXDR_Msk                          /* Transmit Data Register */

+

+/*******************  Bit definition for SPI_RXDR register  ********************/

+#define SPI_RXDR_RXDR_Pos           (0U)

+#define SPI_RXDR_RXDR_Msk           (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)        /*!< 0xFFFFFFFF */

+#define SPI_RXDR_RXDR               SPI_RXDR_RXDR_Msk                          /* Receive Data Register  */

+

+/*******************  Bit definition for SPI_CRCPOLY register  ********************/

+#define SPI_CRCPOLY_CRCPOLY_Pos     (0U)

+#define SPI_CRCPOLY_CRCPOLY_Msk     (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)  /*!< 0xFFFFFFFF */

+#define SPI_CRCPOLY_CRCPOLY         SPI_CRCPOLY_CRCPOLY_Msk                    /* CRC Polynomial register  */

+

+/*******************  Bit definition for SPI_TXCRC register  ********************/

+#define SPI_TXCRC_TXCRC_Pos         (0U)

+#define SPI_TXCRC_TXCRC_Msk         (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_TXCRC_TXCRC             SPI_TXCRC_TXCRC_Msk                        /* CRCRegister for transmitter */

+

+/*******************  Bit definition for SPI_RXCRC register  ********************/

+#define SPI_RXCRC_RXCRC_Pos         (0U)

+#define SPI_RXCRC_RXCRC_Msk         (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_RXCRC_RXCRC             SPI_RXCRC_RXCRC_Msk                        /* CRCRegister for receiver */

+

+/*******************  Bit definition for SPI_UDRDR register  ********************/

+#define SPI_UDRDR_UDRDR_Pos         (0U)

+#define SPI_UDRDR_UDRDR_Msk         (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_UDRDR_UDRDR             SPI_UDRDR_UDRDR_Msk                        /* Data at slave underrun condition */

+

+/******************  Bit definition for SPI_I2SCFGR register  *****************/

+#define SPI_I2SCFGR_I2SMOD_Pos      (0U)

+#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000001 */

+#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */

+#define SPI_I2SCFGR_I2SCFG_Pos      (1U)

+#define SPI_I2SCFGR_I2SCFG_Msk      (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x0000000E */

+#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[2:0] I2S configuration mode                */

+#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000002 */

+#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000004 */

+#define SPI_I2SCFGR_I2SCFG_2        (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000008 */

+#define SPI_I2SCFGR_I2SSTD_Pos      (4U)

+#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */

+#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] I2S standard selection                */

+#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */

+#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */

+#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)

+#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */

+#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                         */

+#define SPI_I2SCFGR_DATLEN_Pos      (8U)

+#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000300 */

+#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] Data length to be transferred         */

+#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000100 */

+#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000200 */

+#define SPI_I2SCFGR_CHLEN_Pos       (10U)

+#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000400 */

+#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */

+#define SPI_I2SCFGR_CKPOL_Pos       (11U)

+#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000800 */

+#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<Steady state clock polarity                       */

+#define SPI_I2SCFGR_FIXCH_Pos       (12U)

+#define SPI_I2SCFGR_FIXCH_Msk       (0x1UL << SPI_I2SCFGR_FIXCH_Pos)           /*!< 0x00001000 */

+#define SPI_I2SCFGR_FIXCH           SPI_I2SCFGR_FIXCH_Msk                      /*!<Fixed channel length in SLAVE                     */

+#define SPI_I2SCFGR_WSINV_Pos       (13U)

+#define SPI_I2SCFGR_WSINV_Msk       (0x1UL << SPI_I2SCFGR_WSINV_Pos)           /*!< 0x00002000 */

+#define SPI_I2SCFGR_WSINV           SPI_I2SCFGR_WSINV_Msk                      /*!<Word select inversion                             */

+#define SPI_I2SCFGR_DATFMT_Pos      (14U)

+#define SPI_I2SCFGR_DATFMT_Msk      (0x1UL << SPI_I2SCFGR_DATFMT_Pos)          /*!< 0x00004000 */

+#define SPI_I2SCFGR_DATFMT          SPI_I2SCFGR_DATFMT_Msk                     /*!<Data format                                       */

+#define SPI_I2SCFGR_I2SDIV_Pos      (16U)

+#define SPI_I2SCFGR_I2SDIV_Msk      (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)         /*!< 0x00FF0000 */

+#define SPI_I2SCFGR_I2SDIV          SPI_I2SCFGR_I2SDIV_Msk                     /*!<I2S Linear prescaler */

+#define SPI_I2SCFGR_ODD_Pos         (24U)

+#define SPI_I2SCFGR_ODD_Msk         (0x1UL << SPI_I2SCFGR_ODD_Pos)             /*!< 0x01000000 */

+#define SPI_I2SCFGR_ODD             SPI_I2SCFGR_ODD_Msk                        /*!<Odd factor for the prescaler */

+#define SPI_I2SCFGR_MCKOE_Pos       (25U)

+#define SPI_I2SCFGR_MCKOE_Msk       (0x1UL << SPI_I2SCFGR_MCKOE_Pos)           /*!< 0x02000000 */

+#define SPI_I2SCFGR_MCKOE           SPI_I2SCFGR_MCKOE_Msk                      /*!<Master Clock Output Enable */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    QUADSPI                                 */

+/*                                                                            */

+/******************************************************************************/

+/*****************  Bit definition for QUADSPI_CR register  *******************/

+#define QUADSPI_CR_EN_Pos                (0U)

+#define QUADSPI_CR_EN_Msk                (0x1UL << QUADSPI_CR_EN_Pos)          /*!< 0x00000001 */

+#define QUADSPI_CR_EN                    QUADSPI_CR_EN_Msk                     /*!< Enable */

+#define QUADSPI_CR_ABORT_Pos             (1U)

+#define QUADSPI_CR_ABORT_Msk             (0x1UL << QUADSPI_CR_ABORT_Pos)       /*!< 0x00000002 */

+#define QUADSPI_CR_ABORT                 QUADSPI_CR_ABORT_Msk                  /*!< Abort request */

+#define QUADSPI_CR_DMAEN_Pos             (2U)

+#define QUADSPI_CR_DMAEN_Msk             (0x1UL << QUADSPI_CR_DMAEN_Pos)       /*!< 0x00000004 */

+#define QUADSPI_CR_DMAEN                 QUADSPI_CR_DMAEN_Msk                  /*!< DMA Enable */

+#define QUADSPI_CR_TCEN_Pos              (3U)

+#define QUADSPI_CR_TCEN_Msk              (0x1UL << QUADSPI_CR_TCEN_Pos)        /*!< 0x00000008 */

+#define QUADSPI_CR_TCEN                  QUADSPI_CR_TCEN_Msk                   /*!< Timeout Counter Enable */

+#define QUADSPI_CR_SSHIFT_Pos            (4U)

+#define QUADSPI_CR_SSHIFT_Msk            (0x1UL << QUADSPI_CR_SSHIFT_Pos)      /*!< 0x00000010 */

+#define QUADSPI_CR_SSHIFT                QUADSPI_CR_SSHIFT_Msk                 /*!< SSHIFT Sample Shift */

+#define QUADSPI_CR_DFM_Pos               (6U)

+#define QUADSPI_CR_DFM_Msk               (0x1UL << QUADSPI_CR_DFM_Pos)         /*!< 0x00000040 */

+#define QUADSPI_CR_DFM                   QUADSPI_CR_DFM_Msk                    /*!< Dual Flash Mode */

+#define QUADSPI_CR_FSEL_Pos              (7U)

+#define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)        /*!< 0x00000080 */

+#define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select */

+#define QUADSPI_CR_FTHRES_Pos            (8U)

+#define QUADSPI_CR_FTHRES_Msk            (0xFUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000F00 */

+#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level */

+#define QUADSPI_CR_FTHRES_0              (0x1UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */

+#define QUADSPI_CR_FTHRES_1              (0x2UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */

+#define QUADSPI_CR_FTHRES_2              (0x4UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */

+#define QUADSPI_CR_FTHRES_3              (0x8UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */

+#define QUADSPI_CR_TEIE_Pos              (16U)

+#define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)        /*!< 0x00010000 */

+#define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable */

+#define QUADSPI_CR_TCIE_Pos              (17U)

+#define QUADSPI_CR_TCIE_Msk              (0x1UL << QUADSPI_CR_TCIE_Pos)        /*!< 0x00020000 */

+#define QUADSPI_CR_TCIE                  QUADSPI_CR_TCIE_Msk                   /*!< Transfer Complete Interrupt Enable */

+#define QUADSPI_CR_FTIE_Pos              (18U)

+#define QUADSPI_CR_FTIE_Msk              (0x1UL << QUADSPI_CR_FTIE_Pos)        /*!< 0x00040000 */

+#define QUADSPI_CR_FTIE                  QUADSPI_CR_FTIE_Msk                   /*!< FIFO Threshold Interrupt Enable */

+#define QUADSPI_CR_SMIE_Pos              (19U)

+#define QUADSPI_CR_SMIE_Msk              (0x1UL << QUADSPI_CR_SMIE_Pos)        /*!< 0x00080000 */

+#define QUADSPI_CR_SMIE                  QUADSPI_CR_SMIE_Msk                   /*!< Status Match Interrupt Enable */

+#define QUADSPI_CR_TOIE_Pos              (20U)

+#define QUADSPI_CR_TOIE_Msk              (0x1UL << QUADSPI_CR_TOIE_Pos)        /*!< 0x00100000 */

+#define QUADSPI_CR_TOIE                  QUADSPI_CR_TOIE_Msk                   /*!< TimeOut Interrupt Enable */

+#define QUADSPI_CR_APMS_Pos              (22U)

+#define QUADSPI_CR_APMS_Msk              (0x1UL << QUADSPI_CR_APMS_Pos)        /*!< 0x00400000 */

+#define QUADSPI_CR_APMS                  QUADSPI_CR_APMS_Msk                   /*!< Bit 1 */

+#define QUADSPI_CR_PMM_Pos               (23U)

+#define QUADSPI_CR_PMM_Msk               (0x1UL << QUADSPI_CR_PMM_Pos)         /*!< 0x00800000 */

+#define QUADSPI_CR_PMM                   QUADSPI_CR_PMM_Msk                    /*!< Polling Match Mode */

+#define QUADSPI_CR_PRESCALER_Pos         (24U)

+#define QUADSPI_CR_PRESCALER_Msk         (0xFFUL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0xFF000000 */

+#define QUADSPI_CR_PRESCALER             QUADSPI_CR_PRESCALER_Msk              /*!< PRESCALER[7:0] Clock prescaler */

+#define QUADSPI_CR_PRESCALER_0           (0x01UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x01000000 */

+#define QUADSPI_CR_PRESCALER_1           (0x02UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x02000000 */

+#define QUADSPI_CR_PRESCALER_2           (0x04UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x04000000 */

+#define QUADSPI_CR_PRESCALER_3           (0x08UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x08000000 */

+#define QUADSPI_CR_PRESCALER_4           (0x10UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x10000000 */

+#define QUADSPI_CR_PRESCALER_5           (0x20UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x20000000 */

+#define QUADSPI_CR_PRESCALER_6           (0x40UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x40000000 */

+#define QUADSPI_CR_PRESCALER_7           (0x80UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x80000000 */

+

+/*****************  Bit definition for QUADSPI_DCR register  ******************/

+#define QUADSPI_DCR_CKMODE_Pos           (0U)

+#define QUADSPI_DCR_CKMODE_Msk           (0x1UL << QUADSPI_DCR_CKMODE_Pos)     /*!< 0x00000001 */

+#define QUADSPI_DCR_CKMODE               QUADSPI_DCR_CKMODE_Msk                /*!< Mode 0 / Mode 3 */

+#define QUADSPI_DCR_CSHT_Pos             (8U)

+#define QUADSPI_DCR_CSHT_Msk             (0x7UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000700 */

+#define QUADSPI_DCR_CSHT                 QUADSPI_DCR_CSHT_Msk                  /*!< CSHT[2:0]: ChipSelect High Time */

+#define QUADSPI_DCR_CSHT_0               (0x1UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000100 */

+#define QUADSPI_DCR_CSHT_1               (0x2UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000200 */

+#define QUADSPI_DCR_CSHT_2               (0x4UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000400 */

+#define QUADSPI_DCR_FSIZE_Pos            (16U)

+#define QUADSPI_DCR_FSIZE_Msk            (0x1FUL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x001F0000 */

+#define QUADSPI_DCR_FSIZE                QUADSPI_DCR_FSIZE_Msk                 /*!< FSIZE[4:0]: Flash Size */

+#define QUADSPI_DCR_FSIZE_0              (0x01UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00010000 */

+#define QUADSPI_DCR_FSIZE_1              (0x02UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00020000 */

+#define QUADSPI_DCR_FSIZE_2              (0x04UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00040000 */

+#define QUADSPI_DCR_FSIZE_3              (0x08UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00080000 */

+#define QUADSPI_DCR_FSIZE_4              (0x10UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00100000 */

+

+/******************  Bit definition for QUADSPI_SR register  *******************/

+#define QUADSPI_SR_TEF_Pos               (0U)

+#define QUADSPI_SR_TEF_Msk               (0x1UL << QUADSPI_SR_TEF_Pos)         /*!< 0x00000001 */

+#define QUADSPI_SR_TEF                   QUADSPI_SR_TEF_Msk                    /*!< Transfer Error Flag */

+#define QUADSPI_SR_TCF_Pos               (1U)

+#define QUADSPI_SR_TCF_Msk               (0x1UL << QUADSPI_SR_TCF_Pos)         /*!< 0x00000002 */

+#define QUADSPI_SR_TCF                   QUADSPI_SR_TCF_Msk                    /*!< Transfer Complete Flag */

+#define QUADSPI_SR_FTF_Pos               (2U)

+#define QUADSPI_SR_FTF_Msk               (0x1UL << QUADSPI_SR_FTF_Pos)         /*!< 0x00000004 */

+#define QUADSPI_SR_FTF                   QUADSPI_SR_FTF_Msk                    /*!< FIFO Threshlod Flag */

+#define QUADSPI_SR_SMF_Pos               (3U)

+#define QUADSPI_SR_SMF_Msk               (0x1UL << QUADSPI_SR_SMF_Pos)         /*!< 0x00000008 */

+#define QUADSPI_SR_SMF                   QUADSPI_SR_SMF_Msk                    /*!< Status Match Flag */

+#define QUADSPI_SR_TOF_Pos               (4U)

+#define QUADSPI_SR_TOF_Msk               (0x1UL << QUADSPI_SR_TOF_Pos)         /*!< 0x00000010 */

+#define QUADSPI_SR_TOF                   QUADSPI_SR_TOF_Msk                    /*!< Timeout Flag */

+#define QUADSPI_SR_BUSY_Pos              (5U)

+#define QUADSPI_SR_BUSY_Msk              (0x1UL << QUADSPI_SR_BUSY_Pos)        /*!< 0x00000020 */

+#define QUADSPI_SR_BUSY                  QUADSPI_SR_BUSY_Msk                   /*!< Busy */

+#define QUADSPI_SR_FLEVEL_Pos            (8U)

+#define QUADSPI_SR_FLEVEL_Msk            (0x3FUL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00003F00 */

+#define QUADSPI_SR_FLEVEL                QUADSPI_SR_FLEVEL_Msk                 /*!< FIFO Threshlod Flag */

+#define QUADSPI_SR_FLEVEL_0              (0x01UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000100 */

+#define QUADSPI_SR_FLEVEL_1              (0x02UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000200 */

+#define QUADSPI_SR_FLEVEL_2              (0x04UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000400 */

+#define QUADSPI_SR_FLEVEL_3              (0x08UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000800 */

+#define QUADSPI_SR_FLEVEL_4              (0x10UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00001000 */

+#define QUADSPI_SR_FLEVEL_5              (0x20UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00002000 */

+

+/******************  Bit definition for QUADSPI_FCR register  ******************/

+#define QUADSPI_FCR_CTEF_Pos             (0U)

+#define QUADSPI_FCR_CTEF_Msk             (0x1UL << QUADSPI_FCR_CTEF_Pos)       /*!< 0x00000001 */

+#define QUADSPI_FCR_CTEF                 QUADSPI_FCR_CTEF_Msk                  /*!< Clear Transfer Error Flag */

+#define QUADSPI_FCR_CTCF_Pos             (1U)

+#define QUADSPI_FCR_CTCF_Msk             (0x1UL << QUADSPI_FCR_CTCF_Pos)       /*!< 0x00000002 */

+#define QUADSPI_FCR_CTCF                 QUADSPI_FCR_CTCF_Msk                  /*!< Clear Transfer Complete Flag */

+#define QUADSPI_FCR_CSMF_Pos             (3U)

+#define QUADSPI_FCR_CSMF_Msk             (0x1UL << QUADSPI_FCR_CSMF_Pos)       /*!< 0x00000008 */

+#define QUADSPI_FCR_CSMF                 QUADSPI_FCR_CSMF_Msk                  /*!< Clear Status Match Flag */

+#define QUADSPI_FCR_CTOF_Pos             (4U)

+#define QUADSPI_FCR_CTOF_Msk             (0x1UL << QUADSPI_FCR_CTOF_Pos)       /*!< 0x00000010 */

+#define QUADSPI_FCR_CTOF                 QUADSPI_FCR_CTOF_Msk                  /*!< Clear Timeout Flag */

+

+/******************  Bit definition for QUADSPI_DLR register  ******************/

+#define QUADSPI_DLR_DL_Pos               (0U)

+#define QUADSPI_DLR_DL_Msk               (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)  /*!< 0xFFFFFFFF */

+#define QUADSPI_DLR_DL                   QUADSPI_DLR_DL_Msk                    /*!< DL[31:0]: Data Length */

+

+/******************  Bit definition for QUADSPI_CCR register  ******************/

+#define QUADSPI_CCR_INSTRUCTION_Pos      (0U)

+#define QUADSPI_CCR_INSTRUCTION_Msk      (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */

+#define QUADSPI_CCR_INSTRUCTION          QUADSPI_CCR_INSTRUCTION_Msk             /*!< INSTRUCTION[7:0]: Instruction */

+#define QUADSPI_CCR_INSTRUCTION_0        (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */

+#define QUADSPI_CCR_INSTRUCTION_1        (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */

+#define QUADSPI_CCR_INSTRUCTION_2        (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */

+#define QUADSPI_CCR_INSTRUCTION_3        (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */

+#define QUADSPI_CCR_INSTRUCTION_4        (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */

+#define QUADSPI_CCR_INSTRUCTION_5        (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */

+#define QUADSPI_CCR_INSTRUCTION_6        (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */

+#define QUADSPI_CCR_INSTRUCTION_7        (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */

+#define QUADSPI_CCR_IMODE_Pos            (8U)

+#define QUADSPI_CCR_IMODE_Msk            (0x3UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000300 */

+#define QUADSPI_CCR_IMODE                QUADSPI_CCR_IMODE_Msk                   /*!< IMODE[1:0]: Instruction Mode */

+#define QUADSPI_CCR_IMODE_0              (0x1UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000100 */

+#define QUADSPI_CCR_IMODE_1              (0x2UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000200 */

+#define QUADSPI_CCR_ADMODE_Pos           (10U)

+#define QUADSPI_CCR_ADMODE_Msk           (0x3UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000C00 */

+#define QUADSPI_CCR_ADMODE               QUADSPI_CCR_ADMODE_Msk                  /*!< ADMODE[1:0]: Address Mode */

+#define QUADSPI_CCR_ADMODE_0             (0x1UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000400 */

+#define QUADSPI_CCR_ADMODE_1             (0x2UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000800 */

+#define QUADSPI_CCR_ADSIZE_Pos           (12U)

+#define QUADSPI_CCR_ADSIZE_Msk           (0x3UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00003000 */

+#define QUADSPI_CCR_ADSIZE               QUADSPI_CCR_ADSIZE_Msk                  /*!< ADSIZE[1:0]: Address Size */

+#define QUADSPI_CCR_ADSIZE_0             (0x1UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00001000 */

+#define QUADSPI_CCR_ADSIZE_1             (0x2UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00002000 */

+#define QUADSPI_CCR_ABMODE_Pos           (14U)

+#define QUADSPI_CCR_ABMODE_Msk           (0x3UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x0000C000 */

+#define QUADSPI_CCR_ABMODE               QUADSPI_CCR_ABMODE_Msk                  /*!< ABMODE[1:0]: Alternate Bytes Mode */

+#define QUADSPI_CCR_ABMODE_0             (0x1UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00004000 */

+#define QUADSPI_CCR_ABMODE_1             (0x2UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00008000 */

+#define QUADSPI_CCR_ABSIZE_Pos           (16U)

+#define QUADSPI_CCR_ABSIZE_Msk           (0x3UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00030000 */

+#define QUADSPI_CCR_ABSIZE               QUADSPI_CCR_ABSIZE_Msk                  /*!< ABSIZE[1:0]: Instruction Mode */

+#define QUADSPI_CCR_ABSIZE_0             (0x1UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00010000 */

+#define QUADSPI_CCR_ABSIZE_1             (0x2UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00020000 */

+#define QUADSPI_CCR_DCYC_Pos             (18U)

+#define QUADSPI_CCR_DCYC_Msk             (0x1FUL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x007C0000 */

+#define QUADSPI_CCR_DCYC                 QUADSPI_CCR_DCYC_Msk                    /*!< DCYC[4:0]: Dummy Cycles */

+#define QUADSPI_CCR_DCYC_0               (0x01UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00040000 */

+#define QUADSPI_CCR_DCYC_1               (0x02UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00080000 */

+#define QUADSPI_CCR_DCYC_2               (0x04UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00100000 */

+#define QUADSPI_CCR_DCYC_3               (0x08UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00200000 */

+#define QUADSPI_CCR_DCYC_4               (0x10UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00400000 */

+#define QUADSPI_CCR_DMODE_Pos            (24U)

+#define QUADSPI_CCR_DMODE_Msk            (0x3UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x03000000 */

+#define QUADSPI_CCR_DMODE                QUADSPI_CCR_DMODE_Msk                   /*!< DMODE[1:0]: Data Mode */

+#define QUADSPI_CCR_DMODE_0              (0x1UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x01000000 */

+#define QUADSPI_CCR_DMODE_1              (0x2UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x02000000 */

+#define QUADSPI_CCR_FMODE_Pos            (26U)

+#define QUADSPI_CCR_FMODE_Msk            (0x3UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x0C000000 */

+#define QUADSPI_CCR_FMODE                QUADSPI_CCR_FMODE_Msk                   /*!< FMODE[1:0]: Functional Mode */

+#define QUADSPI_CCR_FMODE_0              (0x1UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x04000000 */

+#define QUADSPI_CCR_FMODE_1              (0x2UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x08000000 */

+#define QUADSPI_CCR_SIOO_Pos             (28U)

+#define QUADSPI_CCR_SIOO_Msk             (0x1UL << QUADSPI_CCR_SIOO_Pos)         /*!< 0x10000000 */

+#define QUADSPI_CCR_SIOO                 QUADSPI_CCR_SIOO_Msk                    /*!< SIOO: Send Instruction Only Once Mode */

+#define QUADSPI_CCR_DHHC_Pos             (30U)

+#define QUADSPI_CCR_DHHC_Msk             (0x1UL << QUADSPI_CCR_DHHC_Pos)         /*!< 0x40000000 */

+#define QUADSPI_CCR_DHHC                 QUADSPI_CCR_DHHC_Msk                    /*!< DHHC: DDR hold half cycle */

+#define QUADSPI_CCR_DDRM_Pos             (31U)

+#define QUADSPI_CCR_DDRM_Msk             (0x1UL << QUADSPI_CCR_DDRM_Pos)         /*!< 0x80000000 */

+#define QUADSPI_CCR_DDRM                 QUADSPI_CCR_DDRM_Msk                    /*!< DDRM: Double Data Rate Mode */

+

+/******************  Bit definition for QUADSPI_AR register  *******************/

+#define QUADSPI_AR_ADDRESS_Pos           (0U)

+#define QUADSPI_AR_ADDRESS_Msk           (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_AR_ADDRESS               QUADSPI_AR_ADDRESS_Msk                /*!< ADDRESS[31:0]: Address */

+

+/******************  Bit definition for QUADSPI_ABR register  ******************/

+#define QUADSPI_ABR_ALTERNATE_Pos        (0U)

+#define QUADSPI_ABR_ALTERNATE_Msk        (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_ABR_ALTERNATE            QUADSPI_ABR_ALTERNATE_Msk             /*!< ALTERNATE[31:0]: Alternate Bytes */

+

+/******************  Bit definition for QUADSPI_DR register  *******************/

+#define QUADSPI_DR_DATA_Pos              (0U)

+#define QUADSPI_DR_DATA_Msk              (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_DR_DATA                  QUADSPI_DR_DATA_Msk                   /*!< DATA[31:0]: Data */

+

+/******************  Bit definition for QUADSPI_PSMKR register  ****************/

+#define QUADSPI_PSMKR_MASK_Pos           (0U)

+#define QUADSPI_PSMKR_MASK_Msk           (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_PSMKR_MASK               QUADSPI_PSMKR_MASK_Msk                /*!< MASK[31:0]: Status Mask */

+

+/******************  Bit definition for QUADSPI_PSMAR register  ****************/

+#define QUADSPI_PSMAR_MATCH_Pos          (0U)

+#define QUADSPI_PSMAR_MATCH_Msk          (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_PSMAR_MATCH              QUADSPI_PSMAR_MATCH_Msk               /*!< MATCH[31:0]: Status Match */

+

+/******************  Bit definition for QUADSPI_PIR register  *****************/

+#define QUADSPI_PIR_INTERVAL_Pos         (0U)

+#define QUADSPI_PIR_INTERVAL_Msk         (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */

+#define QUADSPI_PIR_INTERVAL             QUADSPI_PIR_INTERVAL_Msk              /*!< INTERVAL[15:0]: Polling Interval */

+

+/******************  Bit definition for QUADSPI_LPTR register  *****************/

+#define QUADSPI_LPTR_TIMEOUT_Pos         (0U)

+#define QUADSPI_LPTR_TIMEOUT_Msk         (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */

+#define QUADSPI_LPTR_TIMEOUT             QUADSPI_LPTR_TIMEOUT_Msk              /*!< TIMEOUT[15:0]: Timeout period */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                 SYSCFG                                     */

+/*                                                                            */

+/******************************************************************************/

+

+/******************  Bit definition for SYSCFG_PMCR register  ******************/

+#define SYSCFG_PMCR_I2C1_FMP_Pos        (0U)

+#define SYSCFG_PMCR_I2C1_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos)    /*!< 0x00000001 */

+#define SYSCFG_PMCR_I2C1_FMP            SYSCFG_PMCR_I2C1_FMP_Msk               /*!< I2C1 Fast mode plus */

+#define SYSCFG_PMCR_I2C2_FMP_Pos        (1U)

+#define SYSCFG_PMCR_I2C2_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos)    /*!< 0x00000002 */

+#define SYSCFG_PMCR_I2C2_FMP            SYSCFG_PMCR_I2C2_FMP_Msk               /*!< I2C2 Fast mode plus */

+#define SYSCFG_PMCR_I2C3_FMP_Pos        (2U)

+#define SYSCFG_PMCR_I2C3_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos)    /*!< 0x00000004 */

+#define SYSCFG_PMCR_I2C3_FMP            SYSCFG_PMCR_I2C3_FMP_Msk               /*!< I2C3 Fast mode plus */

+#define SYSCFG_PMCR_I2C4_FMP_Pos        (3U)

+#define SYSCFG_PMCR_I2C4_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos)    /*!< 0x00000008 */

+#define SYSCFG_PMCR_I2C4_FMP            SYSCFG_PMCR_I2C4_FMP_Msk               /*!< I2C4 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB6_FMP_Pos     (4U)

+#define SYSCFG_PMCR_I2C_PB6_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */

+#define SYSCFG_PMCR_I2C_PB6_FMP         SYSCFG_PMCR_I2C_PB6_FMP_Msk            /*!< I2C PB6 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB7_FMP_Pos     (5U)

+#define SYSCFG_PMCR_I2C_PB7_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */

+#define SYSCFG_PMCR_I2C_PB7_FMP         SYSCFG_PMCR_I2C_PB7_FMP_Msk            /*!< I2C PB7 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB8_FMP_Pos     (6U)

+#define SYSCFG_PMCR_I2C_PB8_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */

+#define SYSCFG_PMCR_I2C_PB8_FMP         SYSCFG_PMCR_I2C_PB8_FMP_Msk            /*!< I2C PB8 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB9_FMP_Pos     (7U)

+#define SYSCFG_PMCR_I2C_PB9_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */

+#define SYSCFG_PMCR_I2C_PB9_FMP         SYSCFG_PMCR_I2C_PB9_FMP_Msk            /*!< I2C PB9 Fast mode plus */

+#define SYSCFG_PMCR_BOOSTEN_Pos         (8U)

+#define SYSCFG_PMCR_BOOSTEN_Msk         (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos)     /*!< 0x00000100 */

+#define SYSCFG_PMCR_BOOSTEN             SYSCFG_PMCR_BOOSTEN_Msk                /*!< I/O analog switch voltage booster enable */

+

+#define SYSCFG_PMCR_BOOSTVDDSEL_Pos     (9U)

+#define SYSCFG_PMCR_BOOSTVDDSEL_Msk     (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos) /*!< 0x00000200 */

+#define SYSCFG_PMCR_BOOSTVDDSEL         SYSCFG_PMCR_BOOSTVDDSEL_Msk            /*!< Analog switch supply source selection : VDD/VDDA */

+

+#define SYSCFG_PMCR_EPIS_SEL_Pos        (21U)

+#define SYSCFG_PMCR_EPIS_SEL_Msk        (0x7UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00E00000 */

+#define SYSCFG_PMCR_EPIS_SEL            SYSCFG_PMCR_EPIS_SEL_Msk               /*!< Ethernet PHY Interface Selection */

+#define SYSCFG_PMCR_EPIS_SEL_0          (0x1UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00200000 */

+#define SYSCFG_PMCR_EPIS_SEL_1          (0x2UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00400000 */

+#define SYSCFG_PMCR_EPIS_SEL_2          (0x4UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00800000 */

+#define SYSCFG_PMCR_PA0SO_Pos           (24U)

+#define SYSCFG_PMCR_PA0SO_Msk           (0x1UL << SYSCFG_PMCR_PA0SO_Pos)       /*!< 0x01000000 */

+#define SYSCFG_PMCR_PA0SO               SYSCFG_PMCR_PA0SO_Msk                  /*!< PA0 Switch Open */

+#define SYSCFG_PMCR_PA1SO_Pos           (25U)

+#define SYSCFG_PMCR_PA1SO_Msk           (0x1UL << SYSCFG_PMCR_PA1SO_Pos)       /*!< 0x02000000 */

+#define SYSCFG_PMCR_PA1SO               SYSCFG_PMCR_PA1SO_Msk                  /*!< PA1 Switch Open */

+#define SYSCFG_PMCR_PC2SO_Pos           (26U)

+#define SYSCFG_PMCR_PC2SO_Msk           (0x1UL << SYSCFG_PMCR_PC2SO_Pos)       /*!< 0x04000000 */

+#define SYSCFG_PMCR_PC2SO               SYSCFG_PMCR_PC2SO_Msk                  /*!< PC2 Switch Open */

+#define SYSCFG_PMCR_PC3SO_Pos           (27U)

+#define SYSCFG_PMCR_PC3SO_Msk           (0x1UL << SYSCFG_PMCR_PC3SO_Pos)       /*!< 0x08000000 */

+#define SYSCFG_PMCR_PC3SO               SYSCFG_PMCR_PC3SO_Msk                  /*!< PC3 Switch Open */

+

+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/

+#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)

+#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */

+#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)

+#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */

+#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)

+#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000F00 */

+#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */

+#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)

+#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x0000F000 */

+#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */

+/**

+  * @brief   EXTI0 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */

+

+/**

+  * @brief   EXTI1 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */

+/**

+  * @brief   EXTI2 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */

+

+/**

+  * @brief   EXTI3 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/

+#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)

+#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */

+#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)

+#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */

+#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)

+#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000F00 */

+#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */

+#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)

+#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x0000F000 */

+#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */

+/**

+  * @brief   EXTI4 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */

+/**

+  * @brief   EXTI5 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */

+/**

+  * @brief   EXTI6 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */

+

+/**

+  * @brief   EXTI7 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/

+#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)

+#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */

+#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)

+#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */

+#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)

+#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000F00 */

+#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */

+#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)

+#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x0000F000 */

+#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */

+

+/**

+  * @brief   EXTI8 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */

+

+/**

+  * @brief   EXTI9 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */

+

+/**

+  * @brief   EXTI10 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */

+

+/**

+  * @brief   EXTI11 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/

+#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)

+#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x0000000F */

+#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */

+#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)

+#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x000000F0 */

+#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */

+#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)

+#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000F00 */

+#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */

+#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)

+#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x0000F000 */

+#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */

+/**

+  * @brief   EXTI12 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */

+/**

+  * @brief   EXTI13 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */

+/**

+  * @brief   EXTI14 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */

+/**

+  * @brief   EXTI15 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */

+

+/******************  Bit definition for SYSCFG_CFGR register  ******************/

+#define SYSCFG_CFGR_CM4L_Pos            (0U)

+#define SYSCFG_CFGR_CM4L_Msk            (0x1UL << SYSCFG_CFGR_CM4L_Pos)        /*!< 0x00000001 */

+#define SYSCFG_CFGR_CM4L                SYSCFG_CFGR_CM4L_Msk                   /*!<Cortex-M4 LOCKUP (Hardfault) output enable bit */

+#define SYSCFG_CFGR_PVDL_Pos            (2U)

+#define SYSCFG_CFGR_PVDL_Msk            (0x1UL << SYSCFG_CFGR_PVDL_Pos)        /*!< 0x00000004 */

+#define SYSCFG_CFGR_PVDL                SYSCFG_CFGR_PVDL_Msk                   /*!<PVD lock enable bit */

+#define SYSCFG_CFGR_FLASHL_Pos          (3U)

+#define SYSCFG_CFGR_FLASHL_Msk          (0x1UL << SYSCFG_CFGR_FLASHL_Pos)      /*!< 0x00000008 */

+#define SYSCFG_CFGR_FLASHL              SYSCFG_CFGR_FLASHL_Msk                 /*!<FLASH double ECC error lock bit */

+#define SYSCFG_CFGR_CM7L_Pos            (6U)

+#define SYSCFG_CFGR_CM7L_Msk            (0x1UL << SYSCFG_CFGR_CM7L_Pos)        /*!< 0x00000040 */

+#define SYSCFG_CFGR_CM7L                SYSCFG_CFGR_CM7L_Msk                   /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */

+#define SYSCFG_CFGR_BKRAML_Pos          (7U)

+#define SYSCFG_CFGR_BKRAML_Msk          (0x1UL << SYSCFG_CFGR_BKRAML_Pos)      /*!< 0x00000080 */

+#define SYSCFG_CFGR_BKRAML              SYSCFG_CFGR_BKRAML_Msk                 /*!<Backup SRAM double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM4L_Pos          (9U)

+#define SYSCFG_CFGR_SRAM4L_Msk          (0x1UL << SYSCFG_CFGR_SRAM4L_Pos)      /*!< 0x00000200 */

+#define SYSCFG_CFGR_SRAM4L              SYSCFG_CFGR_SRAM4L_Msk                 /*!<SRAM4 double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM3L_Pos          (10U)

+#define SYSCFG_CFGR_SRAM3L_Msk          (0x1UL << SYSCFG_CFGR_SRAM3L_Pos)      /*!< 0x00000400 */

+#define SYSCFG_CFGR_SRAM3L              SYSCFG_CFGR_SRAM3L_Msk                 /*!<SRAM3 double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM2L_Pos          (11U)

+#define SYSCFG_CFGR_SRAM2L_Msk          (0x1UL << SYSCFG_CFGR_SRAM2L_Pos)      /*!< 0x00000800 */

+#define SYSCFG_CFGR_SRAM2L              SYSCFG_CFGR_SRAM2L_Msk                 /*!<SRAM2 double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM1L_Pos          (12U)

+#define SYSCFG_CFGR_SRAM1L_Msk          (0x1UL << SYSCFG_CFGR_SRAM1L_Pos)      /*!< 0x00001000 */

+#define SYSCFG_CFGR_SRAM1L              SYSCFG_CFGR_SRAM1L_Msk                 /*!<SRAM1 double ECC error lock bit */

+#define SYSCFG_CFGR_DTCML_Pos           (13U)

+#define SYSCFG_CFGR_DTCML_Msk           (0x1UL << SYSCFG_CFGR_DTCML_Pos)       /*!< 0x00002000 */

+#define SYSCFG_CFGR_DTCML               SYSCFG_CFGR_DTCML_Msk                  /*!<DTCM double ECC error lock bit */

+#define SYSCFG_CFGR_ITCML_Pos           (14U)

+#define SYSCFG_CFGR_ITCML_Msk           (0x1UL << SYSCFG_CFGR_ITCML_Pos)       /*!< 0x00004000 */

+#define SYSCFG_CFGR_ITCML               SYSCFG_CFGR_ITCML_Msk                  /*!<ITCM double ECC error lock bit */

+#define SYSCFG_CFGR_AXISRAML_Pos        (15U)

+#define SYSCFG_CFGR_AXISRAML_Msk        (0x1UL << SYSCFG_CFGR_AXISRAML_Pos)    /*!< 0x00008000 */

+#define SYSCFG_CFGR_AXISRAML            SYSCFG_CFGR_AXISRAML_Msk               /*!<AXISRAM double ECC error lock bit */

+

+/******************  Bit definition for SYSCFG_CCCSR register  ******************/

+#define SYSCFG_CCCSR_EN_Pos             (0U)

+#define SYSCFG_CCCSR_EN_Msk             (0x1UL << SYSCFG_CCCSR_EN_Pos)         /*!< 0x00000001 */

+#define SYSCFG_CCCSR_EN                 SYSCFG_CCCSR_EN_Msk                    /*!< I/O compensation cell enable */

+#define SYSCFG_CCCSR_CS_Pos             (1U)

+#define SYSCFG_CCCSR_CS_Msk             (0x1UL << SYSCFG_CCCSR_CS_Pos)         /*!< 0x00000002 */

+#define SYSCFG_CCCSR_CS                 SYSCFG_CCCSR_CS_Msk                    /*!< I/O compensation cell code selection */

+#define SYSCFG_CCCSR_READY_Pos          (8U)

+#define SYSCFG_CCCSR_READY_Msk          (0x1UL << SYSCFG_CCCSR_READY_Pos)      /*!< 0x00000100 */

+#define SYSCFG_CCCSR_READY              SYSCFG_CCCSR_READY_Msk                 /*!< I/O compensation cell ready flag */

+#define SYSCFG_CCCSR_HSLV_Pos           (16U)

+#define SYSCFG_CCCSR_HSLV_Msk           (0x1UL << SYSCFG_CCCSR_HSLV_Pos)       /*!< 0x00010000 */

+#define SYSCFG_CCCSR_HSLV               SYSCFG_CCCSR_HSLV_Msk                  /*!< High-speed at low-voltage */

+

+/******************  Bit definition for SYSCFG_CCVR register  *******************/

+#define SYSCFG_CCVR_NCV_Pos             (0U)

+#define SYSCFG_CCVR_NCV_Msk             (0xFUL << SYSCFG_CCVR_NCV_Pos)         /*!< 0x0000000F */

+#define SYSCFG_CCVR_NCV                 SYSCFG_CCVR_NCV_Msk                    /*!< NMOS compensation value */

+#define SYSCFG_CCVR_PCV_Pos             (4U)

+#define SYSCFG_CCVR_PCV_Msk             (0xFUL << SYSCFG_CCVR_PCV_Pos)         /*!< 0x000000F0 */

+#define SYSCFG_CCVR_PCV                 SYSCFG_CCVR_PCV_Msk                    /*!< PMOS compensation value */

+

+/******************  Bit definition for SYSCFG_CCCR register  *******************/

+#define SYSCFG_CCCR_NCC_Pos             (0U)

+#define SYSCFG_CCCR_NCC_Msk             (0xFUL << SYSCFG_CCCR_NCC_Pos)         /*!< 0x0000000F */

+#define SYSCFG_CCCR_NCC                 SYSCFG_CCCR_NCC_Msk                    /*!< NMOS compensation code */

+#define SYSCFG_CCCR_PCC_Pos             (4U)

+#define SYSCFG_CCCR_PCC_Msk             (0xFUL << SYSCFG_CCCR_PCC_Pos)         /*!< 0x000000F0 */

+#define SYSCFG_CCCR_PCC                 SYSCFG_CCCR_PCC_Msk                    /*!< PMOS compensation code */

+/******************  Bit definition for SYSCFG_PWRCR register  *******************/

+#define SYSCFG_PWRCR_ODEN_Pos           (0U)

+#define SYSCFG_PWRCR_ODEN_Msk           (0x1UL << SYSCFG_PWRCR_ODEN_Pos)         /*!< 0x00000001 */

+#define SYSCFG_PWRCR_ODEN               SYSCFG_PWRCR_ODEN_Msk                    /*!< PWR overdrive enable */

+

+/******************  Bit definition for SYSCFG_PKGR register  *******************/

+#define SYSCFG_PKGR_PKG_Pos             (0U)

+#define SYSCFG_PKGR_PKG_Msk             (0xFUL << SYSCFG_PKGR_PKG_Pos)         /*!< 0x0000000F */

+#define SYSCFG_PKGR_PKG                 SYSCFG_PKGR_PKG_Msk                    /*!< Package type */

+

+/******************  Bit definition for SYSCFG_UR0 register  *******************/

+#define SYSCFG_UR0_BKS_Pos              (0U)

+#define SYSCFG_UR0_BKS_Msk              (0x1UL << SYSCFG_UR0_BKS_Pos)          /*!< 0x00000001 */

+#define SYSCFG_UR0_BKS                  SYSCFG_UR0_BKS_Msk                     /*!< Bank Swap */

+#define SYSCFG_UR0_RDP_Pos              (16U)

+#define SYSCFG_UR0_RDP_Msk              (0xFFUL << SYSCFG_UR0_RDP_Pos)         /*!< 0x00FF0000 */

+#define SYSCFG_UR0_RDP                  SYSCFG_UR0_RDP_Msk                     /*!< Readout protection */

+

+/******************  Bit definition for SYSCFG_UR1 register  *******************/

+#define SYSCFG_UR1_BCM4_Pos             (0U)

+#define SYSCFG_UR1_BCM4_Msk             (0x1UL << SYSCFG_UR1_BCM4_Pos)         /*!< 0x00000001 */

+#define SYSCFG_UR1_BCM4                 SYSCFG_UR1_BCM4_Msk                    /*!< Boot Cortex-M4 */

+#define SYSCFG_UR1_BCM7_Pos             (16U)

+#define SYSCFG_UR1_BCM7_Msk             (0x1UL << SYSCFG_UR1_BCM7_Pos)         /*!< 0x00010000 */

+#define SYSCFG_UR1_BCM7                 SYSCFG_UR1_BCM7_Msk                    /*!< Boot Cortex-M7 */

+/******************  Bit definition for SYSCFG_UR2 register  *******************/

+#define SYSCFG_UR2_BORH_Pos             (0U)

+#define SYSCFG_UR2_BORH_Msk             (0x3UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000003 */

+#define SYSCFG_UR2_BORH                 SYSCFG_UR2_BORH_Msk                    /*!< Brown Out Reset High level */

+#define SYSCFG_UR2_BORH_0               (0x1UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000001 */

+#define SYSCFG_UR2_BORH_1               (0x2UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000002 */

+#define SYSCFG_UR2_BCM7_ADD0_Pos        (16U)

+#define SYSCFG_UR2_BCM7_ADD0_Msk        (0xFFFFUL << SYSCFG_UR2_BCM7_ADD0_Pos) /*!< 0xFFFF0000 */

+#define SYSCFG_UR2_BCM7_ADD0            SYSCFG_UR2_BCM7_ADD0_Msk               /*!< Boot Cortex-M7 Address 0 */

+/******************  Bit definition for SYSCFG_UR3 register  *******************/

+#define SYSCFG_UR3_BCM7_ADD1_Pos        (0U)

+#define SYSCFG_UR3_BCM7_ADD1_Msk        (0xFFFFUL << SYSCFG_UR3_BCM7_ADD1_Pos) /*!< 0x0000FFFF */

+#define SYSCFG_UR3_BCM7_ADD1            SYSCFG_UR3_BCM7_ADD1_Msk               /*!< Boot Cortex-M7 Address 1 */

+

+#define SYSCFG_UR3_BCM4_ADD0_Pos        (16U)

+#define SYSCFG_UR3_BCM4_ADD0_Msk        (0xFFFFUL << SYSCFG_UR3_BCM4_ADD0_Pos) /*!< 0xFFFF0000 */

+#define SYSCFG_UR3_BCM4_ADD0            SYSCFG_UR3_BCM4_ADD0_Msk               /*!< Boot Cortex-M4 Address 0 */

+

+/******************  Bit definition for SYSCFG_UR4 register  *******************/

+

+#define SYSCFG_UR4_BCM4_ADD1_Pos        (0U)

+#define SYSCFG_UR4_BCM4_ADD1_Msk        (0xFFFFUL << SYSCFG_UR4_BCM4_ADD1_Pos) /*!< 0x0000FFFF */

+#define SYSCFG_UR4_BCM4_ADD1            SYSCFG_UR4_BCM4_ADD1_Msk               /*!< Boot Cortex-M4 Address 1 */

+

+#define SYSCFG_UR4_MEPAD_BANK1_Pos      (16U)

+#define SYSCFG_UR4_MEPAD_BANK1_Msk      (0x1UL << SYSCFG_UR4_MEPAD_BANK1_Pos)  /*!< 0x00010000 */

+#define SYSCFG_UR4_MEPAD_BANK1          SYSCFG_UR4_MEPAD_BANK1_Msk             /*!< Mass Erase Protected Area Disabled for bank 1 */

+

+/******************  Bit definition for SYSCFG_UR5 register  *******************/

+#define SYSCFG_UR5_MESAD_BANK1_Pos      (0U)

+#define SYSCFG_UR5_MESAD_BANK1_Msk      (0x1UL << SYSCFG_UR5_MESAD_BANK1_Pos)  /*!< 0x00000001 */

+#define SYSCFG_UR5_MESAD_BANK1          SYSCFG_UR5_MESAD_BANK1_Msk             /*!< Mass erase secured area disabled for bank 1 */

+#define SYSCFG_UR5_WRPN_BANK1_Pos       (16U)

+#define SYSCFG_UR5_WRPN_BANK1_Msk       (0xFFUL << SYSCFG_UR5_WRPN_BANK1_Pos)  /*!< 0x00FF0000 */

+#define SYSCFG_UR5_WRPN_BANK1           SYSCFG_UR5_WRPN_BANK1_Msk              /*!< Write protection for flash bank 1 */

+

+/******************  Bit definition for SYSCFG_UR6 register  *******************/

+#define SYSCFG_UR6_PABEG_BANK1_Pos      (0U)

+#define SYSCFG_UR6_PABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PABEG_BANK1_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR6_PABEG_BANK1          SYSCFG_UR6_PABEG_BANK1_Msk             /*!< Protected area start address for bank 1 */

+#define SYSCFG_UR6_PAEND_BANK1_Pos      (16U)

+#define SYSCFG_UR6_PAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PAEND_BANK1_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR6_PAEND_BANK1          SYSCFG_UR6_PAEND_BANK1_Msk             /*!< Protected area end address for bank 1 */

+

+/******************  Bit definition for SYSCFG_UR7 register  *******************/

+#define SYSCFG_UR7_SABEG_BANK1_Pos      (0U)

+#define SYSCFG_UR7_SABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SABEG_BANK1_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR7_SABEG_BANK1          SYSCFG_UR7_SABEG_BANK1_Msk             /*!< Secured area start address for bank 1 */

+#define SYSCFG_UR7_SAEND_BANK1_Pos      (16U)

+#define SYSCFG_UR7_SAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SAEND_BANK1_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR7_SAEND_BANK1          SYSCFG_UR7_SAEND_BANK1_Msk             /*!< Secured area end address for bank 1 */

+

+/******************  Bit definition for SYSCFG_UR8 register  *******************/

+#define SYSCFG_UR8_MEPAD_BANK2_Pos      (0U)

+#define SYSCFG_UR8_MEPAD_BANK2_Msk      (0x1UL << SYSCFG_UR8_MEPAD_BANK2_Pos)  /*!< 0x00000001 */

+#define SYSCFG_UR8_MEPAD_BANK2          SYSCFG_UR8_MEPAD_BANK2_Msk             /*!< Mass erase Protected area disabled for bank 2 */

+#define SYSCFG_UR8_MESAD_BANK2_Pos      (16U)

+#define SYSCFG_UR8_MESAD_BANK2_Msk      (0x1UL << SYSCFG_UR8_MESAD_BANK2_Pos)  /*!< 0x00010000 */

+#define SYSCFG_UR8_MESAD_BANK2          SYSCFG_UR8_MESAD_BANK2_Msk             /*!< Mass Erase Secured Area Disabled for bank 2 */

+

+/******************  Bit definition for SYSCFG_UR9 register  *******************/

+#define SYSCFG_UR9_WRPN_BANK2_Pos       (0U)

+#define SYSCFG_UR9_WRPN_BANK2_Msk       (0xFFUL << SYSCFG_UR9_WRPN_BANK2_Pos)  /*!< 0x000000FF */

+#define SYSCFG_UR9_WRPN_BANK2           SYSCFG_UR9_WRPN_BANK2_Msk              /*!< Write protection for flash bank 2 */

+#define SYSCFG_UR9_PABEG_BANK2_Pos      (16U)

+#define SYSCFG_UR9_PABEG_BANK2_Msk      (0xFFFUL << SYSCFG_UR9_PABEG_BANK2_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR9_PABEG_BANK2          SYSCFG_UR9_PABEG_BANK2_Msk             /*!< Protected area start address for bank 2 */

+

+/******************  Bit definition for SYSCFG_UR10 register  *******************/

+#define SYSCFG_UR10_PAEND_BANK2_Pos     (0U)

+#define SYSCFG_UR10_PAEND_BANK2_Msk     (0xFFFUL << SYSCFG_UR10_PAEND_BANK2_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR10_PAEND_BANK2         SYSCFG_UR10_PAEND_BANK2_Msk            /*!< Protected area end address for bank 2 */

+#define SYSCFG_UR10_SABEG_BANK2_Pos     (16U)

+#define SYSCFG_UR10_SABEG_BANK2_Msk     (0xFFFUL << SYSCFG_UR10_SABEG_BANK2_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR10_SABEG_BANK2         SYSCFG_UR10_SABEG_BANK2_Msk            /*!< Secured area start address for bank 2 */

+

+/******************  Bit definition for SYSCFG_UR11 register  *******************/

+#define SYSCFG_UR11_SAEND_BANK2_Pos     (0U)

+#define SYSCFG_UR11_SAEND_BANK2_Msk     (0xFFFUL << SYSCFG_UR11_SAEND_BANK2_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR11_SAEND_BANK2         SYSCFG_UR11_SAEND_BANK2_Msk            /*!< Secured area end address for bank 2 */

+#define SYSCFG_UR11_IWDG1M_Pos          (16U)

+#define SYSCFG_UR11_IWDG1M_Msk          (0x1UL << SYSCFG_UR11_IWDG1M_Pos)      /*!< 0x00010000 */

+#define SYSCFG_UR11_IWDG1M              SYSCFG_UR11_IWDG1M_Msk                 /*!< Independent Watchdog 1 mode (SW or HW) */

+

+/******************  Bit definition for SYSCFG_UR12 register  *******************/

+#define SYSCFG_UR12_IWDG2M_Pos          (0U)

+#define SYSCFG_UR12_IWDG2M_Msk          (0x1UL << SYSCFG_UR12_IWDG2M_Pos)      /*!< 0x00000001 */

+#define SYSCFG_UR12_IWDG2M              SYSCFG_UR12_IWDG2M_Msk                 /*!< Independent Watchdog 2 mode (SW or HW) */

+

+#define SYSCFG_UR12_SECURE_Pos          (16U)

+#define SYSCFG_UR12_SECURE_Msk          (0x1UL << SYSCFG_UR12_SECURE_Pos)      /*!< 0x00010000 */

+#define SYSCFG_UR12_SECURE              SYSCFG_UR12_SECURE_Msk                 /*!< Secure mode status */

+

+/******************  Bit definition for SYSCFG_UR13 register  *******************/

+#define SYSCFG_UR13_SDRS_Pos            (0U)

+#define SYSCFG_UR13_SDRS_Msk            (0x3UL << SYSCFG_UR13_SDRS_Pos)        /*!< 0x00000003 */

+#define SYSCFG_UR13_SDRS                SYSCFG_UR13_SDRS_Msk                   /*!< Secured DTCM RAM Size */

+#define SYSCFG_UR13_D1SBRST_Pos         (16U)

+#define SYSCFG_UR13_D1SBRST_Msk         (0x1UL << SYSCFG_UR13_D1SBRST_Pos)     /*!< 0x00010000 */

+#define SYSCFG_UR13_D1SBRST             SYSCFG_UR13_D1SBRST_Msk                /*!< D1 Standby reset */

+

+/******************  Bit definition for SYSCFG_UR14 register  *******************/

+#define SYSCFG_UR14_D1STPRST_Pos        (0U)

+#define SYSCFG_UR14_D1STPRST_Msk        (0x1UL << SYSCFG_UR14_D1STPRST_Pos)    /*!< 0x00000001 */

+#define SYSCFG_UR14_D1STPRST            SYSCFG_UR14_D1STPRST_Msk               /*!< D1 Stop Reset */

+#define SYSCFG_UR14_D2SBRST_Pos         (16U)

+#define SYSCFG_UR14_D2SBRST_Msk         (0x1UL << SYSCFG_UR14_D2SBRST_Pos)     /*!< 0x00010000 */

+#define SYSCFG_UR14_D2SBRST             SYSCFG_UR14_D2SBRST_Msk                /*!< D2 Standby Reset */

+

+/******************  Bit definition for SYSCFG_UR15 register  *******************/

+#define SYSCFG_UR15_D2STPRST_Pos        (0U)

+#define SYSCFG_UR15_D2STPRST_Msk        (0x1UL << SYSCFG_UR15_D2STPRST_Pos)    /*!< 0x00000001 */

+#define SYSCFG_UR15_D2STPRST            SYSCFG_UR15_D2STPRST_Msk               /*!< D2 Stop Reset */

+#define SYSCFG_UR15_FZIWDGSTB_Pos       (16U)

+#define SYSCFG_UR15_FZIWDGSTB_Msk       (0x1UL << SYSCFG_UR15_FZIWDGSTB_Pos)   /*!< 0x00010000 */

+#define SYSCFG_UR15_FZIWDGSTB           SYSCFG_UR15_FZIWDGSTB_Msk              /*!< Freeze independent watchdogs in Standby mode */

+

+/******************  Bit definition for SYSCFG_UR16 register  *******************/

+#define SYSCFG_UR16_FZIWDGSTP_Pos       (0U)

+#define SYSCFG_UR16_FZIWDGSTP_Msk       (0x1UL << SYSCFG_UR16_FZIWDGSTP_Pos)   /*!< 0x00000001 */

+#define SYSCFG_UR16_FZIWDGSTP           SYSCFG_UR16_FZIWDGSTP_Msk              /*!< Freeze independent watchdogs in Stop mode */

+#define SYSCFG_UR16_PKP_Pos             (16U)

+#define SYSCFG_UR16_PKP_Msk             (0x1UL << SYSCFG_UR16_PKP_Pos)         /*!< 0x00010000 */

+#define SYSCFG_UR16_PKP                 SYSCFG_UR16_PKP_Msk                    /*!< Private key programmed */

+

+/******************  Bit definition for SYSCFG_UR17 register  *******************/

+#define SYSCFG_UR17_IOHSLV_Pos          (0U)

+#define SYSCFG_UR17_IOHSLV_Msk          (0x1UL << SYSCFG_UR17_IOHSLV_Pos)      /*!< 0x00000001 */

+#define SYSCFG_UR17_IOHSLV              SYSCFG_UR17_IOHSLV_Msk                 /*!< I/O high speed / low voltage */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    TIM                                     */

+/*                                                                            */

+/******************************************************************************/

+#define TIM_BREAK_INPUT_SUPPORT             /*!<TIM Break input feature */

+

+/*******************  Bit definition for TIM_CR1 register  ********************/

+#define TIM_CR1_CEN_Pos           (0U)

+#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */

+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */

+#define TIM_CR1_UDIS_Pos          (1U)

+#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */

+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */

+#define TIM_CR1_URS_Pos           (2U)

+#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */

+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */

+#define TIM_CR1_OPM_Pos           (3U)

+#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */

+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */

+#define TIM_CR1_DIR_Pos           (4U)

+#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */

+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */

+

+#define TIM_CR1_CMS_Pos           (5U)

+#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */

+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */

+#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */

+#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */

+

+#define TIM_CR1_ARPE_Pos          (7U)

+#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */

+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */

+

+#define TIM_CR1_CKD_Pos           (8U)

+#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */

+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */

+#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */

+#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */

+

+#define TIM_CR1_UIFREMAP_Pos      (11U)

+#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */

+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */

+

+/*******************  Bit definition for TIM_CR2 register  ********************/

+#define TIM_CR2_CCPC_Pos          (0U)

+#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */

+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */

+#define TIM_CR2_CCUS_Pos          (2U)

+#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */

+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */

+#define TIM_CR2_CCDS_Pos          (3U)

+#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */

+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */

+

+#define TIM_CR2_MMS_Pos           (4U)

+#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */

+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */

+#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */

+#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */

+#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */

+

+#define TIM_CR2_TI1S_Pos          (7U)

+#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */

+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */

+#define TIM_CR2_OIS1_Pos          (8U)

+#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */

+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */

+#define TIM_CR2_OIS1N_Pos         (9U)

+#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */

+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */

+#define TIM_CR2_OIS2_Pos          (10U)

+#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */

+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */

+#define TIM_CR2_OIS2N_Pos         (11U)

+#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */

+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */

+#define TIM_CR2_OIS3_Pos          (12U)

+#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */

+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */

+#define TIM_CR2_OIS3N_Pos         (13U)

+#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */

+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */

+#define TIM_CR2_OIS4_Pos          (14U)

+#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */

+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */

+#define TIM_CR2_OIS5_Pos          (16U)

+#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */

+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */

+#define TIM_CR2_OIS6_Pos          (17U)

+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */

+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */

+

+#define TIM_CR2_MMS2_Pos          (20U)

+#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */

+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */

+#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */

+#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */

+#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */

+#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */

+

+/*******************  Bit definition for TIM_SMCR register  *******************/

+#define TIM_SMCR_SMS_Pos          (0U)

+#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */

+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */

+#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */

+#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */

+#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */

+#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */

+

+#define TIM_SMCR_TS_Pos           (4U)

+#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */

+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[4:0] bits (Trigger selection) */

+#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)                /*!< 0x00000010 */

+#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)                /*!< 0x00000020 */

+#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)                /*!< 0x00000040 */

+#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)                /*!< 0x00100000 */

+#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)                /*!< 0x00200000 */

+

+#define TIM_SMCR_MSM_Pos          (7U)

+#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */

+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */

+

+#define TIM_SMCR_ETF_Pos          (8U)

+#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */

+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */

+#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */

+#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */

+#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */

+#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */

+

+#define TIM_SMCR_ETPS_Pos         (12U)

+#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */

+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */

+#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */

+#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */

+

+#define TIM_SMCR_ECE_Pos          (14U)

+#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */

+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */

+#define TIM_SMCR_ETP_Pos          (15U)

+#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */

+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */

+

+/*******************  Bit definition for TIM_DIER register  *******************/

+#define TIM_DIER_UIE_Pos          (0U)

+#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */

+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */

+#define TIM_DIER_CC1IE_Pos        (1U)

+#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */

+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */

+#define TIM_DIER_CC2IE_Pos        (2U)

+#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */

+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */

+#define TIM_DIER_CC3IE_Pos        (3U)

+#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */

+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */

+#define TIM_DIER_CC4IE_Pos        (4U)

+#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */

+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */

+#define TIM_DIER_COMIE_Pos        (5U)

+#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */

+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */

+#define TIM_DIER_TIE_Pos          (6U)

+#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */

+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */

+#define TIM_DIER_BIE_Pos          (7U)

+#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */

+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */

+#define TIM_DIER_UDE_Pos          (8U)

+#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */

+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */

+#define TIM_DIER_CC1DE_Pos        (9U)

+#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */

+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */

+#define TIM_DIER_CC2DE_Pos        (10U)

+#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */

+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */

+#define TIM_DIER_CC3DE_Pos        (11U)

+#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */

+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */

+#define TIM_DIER_CC4DE_Pos        (12U)

+#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */

+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */

+#define TIM_DIER_COMDE_Pos        (13U)

+#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */

+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */

+#define TIM_DIER_TDE_Pos          (14U)

+#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */

+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */

+

+/********************  Bit definition for TIM_SR register  ********************/

+#define TIM_SR_UIF_Pos            (0U)

+#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */

+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */

+#define TIM_SR_CC1IF_Pos          (1U)

+#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */

+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */

+#define TIM_SR_CC2IF_Pos          (2U)

+#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */

+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */

+#define TIM_SR_CC3IF_Pos          (3U)

+#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */

+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */

+#define TIM_SR_CC4IF_Pos          (4U)

+#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */

+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */

+#define TIM_SR_COMIF_Pos          (5U)

+#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */

+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */

+#define TIM_SR_TIF_Pos            (6U)

+#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */

+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */

+#define TIM_SR_BIF_Pos            (7U)

+#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */

+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */

+#define TIM_SR_B2IF_Pos           (8U)

+#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */

+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break2 interrupt Flag */

+#define TIM_SR_CC1OF_Pos          (9U)

+#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */

+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */

+#define TIM_SR_CC2OF_Pos          (10U)

+#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */

+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */

+#define TIM_SR_CC3OF_Pos          (11U)

+#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */

+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */

+#define TIM_SR_CC4OF_Pos          (12U)

+#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */

+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */

+#define TIM_SR_CC5IF_Pos          (16U)

+#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */

+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */

+#define TIM_SR_CC6IF_Pos          (17U)

+#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */

+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */

+#define TIM_SR_SBIF_Pos           (13U)

+#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */

+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!< System Break Flag */

+

+/*******************  Bit definition for TIM_EGR register  ********************/

+#define TIM_EGR_UG_Pos            (0U)

+#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */

+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */

+#define TIM_EGR_CC1G_Pos          (1U)

+#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */

+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */

+#define TIM_EGR_CC2G_Pos          (2U)

+#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */

+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */

+#define TIM_EGR_CC3G_Pos          (3U)

+#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */

+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */

+#define TIM_EGR_CC4G_Pos          (4U)

+#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */

+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */

+#define TIM_EGR_COMG_Pos          (5U)

+#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */

+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */

+#define TIM_EGR_TG_Pos            (6U)

+#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */

+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */

+#define TIM_EGR_BG_Pos            (7U)

+#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */

+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */

+#define TIM_EGR_B2G_Pos           (8U)

+#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */

+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break Generation */

+

+

+/******************  Bit definition for TIM_CCMR1 register  *******************/

+#define TIM_CCMR1_CC1S_Pos        (0U)

+#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */

+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */

+#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */

+#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */

+

+#define TIM_CCMR1_OC1FE_Pos       (2U)

+#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */

+#define TIM_CCMR1_OC1PE_Pos       (3U)

+#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */

+

+#define TIM_CCMR1_OC1M_Pos        (4U)

+#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */

+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */

+#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */

+#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */

+#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */

+#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR1_OC1CE_Pos       (7U)

+#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */

+

+#define TIM_CCMR1_CC2S_Pos        (8U)

+#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */

+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */

+#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */

+#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */

+

+#define TIM_CCMR1_OC2FE_Pos       (10U)

+#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */

+#define TIM_CCMR1_OC2PE_Pos       (11U)

+#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */

+

+#define TIM_CCMR1_OC2M_Pos        (12U)

+#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */

+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */

+#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */

+#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */

+#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */

+#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */

+

+#define TIM_CCMR1_OC2CE_Pos       (15U)

+#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */

+

+/*----------------------------------------------------------------------------*/

+

+#define TIM_CCMR1_IC1PSC_Pos      (2U)

+#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */

+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */

+#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */

+

+#define TIM_CCMR1_IC1F_Pos        (4U)

+#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */

+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */

+#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */

+

+#define TIM_CCMR1_IC2PSC_Pos      (10U)

+#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */

+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */

+#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */

+

+#define TIM_CCMR1_IC2F_Pos        (12U)

+#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */

+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */

+#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */

+

+/******************  Bit definition for TIM_CCMR2 register  *******************/

+#define TIM_CCMR2_CC3S_Pos        (0U)

+#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */

+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */

+#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */

+#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */

+

+#define TIM_CCMR2_OC3FE_Pos       (2U)

+#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */

+#define TIM_CCMR2_OC3PE_Pos       (3U)

+#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */

+

+#define TIM_CCMR2_OC3M_Pos        (4U)

+#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */

+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */

+#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR2_OC3CE_Pos       (7U)

+#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */

+

+#define TIM_CCMR2_CC4S_Pos        (8U)

+#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */

+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */

+#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */

+#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */

+

+#define TIM_CCMR2_OC4FE_Pos       (10U)

+#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */

+#define TIM_CCMR2_OC4PE_Pos       (11U)

+#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */

+

+#define TIM_CCMR2_OC4M_Pos        (12U)

+#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */

+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */

+#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */

+

+#define TIM_CCMR2_OC4CE_Pos       (15U)

+#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */

+

+/*----------------------------------------------------------------------------*/

+

+#define TIM_CCMR2_IC3PSC_Pos      (2U)

+#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */

+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */

+#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */

+

+#define TIM_CCMR2_IC3F_Pos        (4U)

+#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */

+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */

+#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */

+

+#define TIM_CCMR2_IC4PSC_Pos      (10U)

+#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */

+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */

+#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */

+

+#define TIM_CCMR2_IC4F_Pos        (12U)

+#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */

+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */

+#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */

+

+/*******************  Bit definition for TIM_CCER register  *******************/

+#define TIM_CCER_CC1E_Pos         (0U)

+#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */

+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */

+#define TIM_CCER_CC1P_Pos         (1U)

+#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */

+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */

+#define TIM_CCER_CC1NE_Pos        (2U)

+#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */

+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */

+#define TIM_CCER_CC1NP_Pos        (3U)

+#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */

+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */

+#define TIM_CCER_CC2E_Pos         (4U)

+#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */

+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */

+#define TIM_CCER_CC2P_Pos         (5U)

+#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */

+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */

+#define TIM_CCER_CC2NE_Pos        (6U)

+#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */

+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */

+#define TIM_CCER_CC2NP_Pos        (7U)

+#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */

+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */

+#define TIM_CCER_CC3E_Pos         (8U)

+#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */

+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */

+#define TIM_CCER_CC3P_Pos         (9U)

+#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */

+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */

+#define TIM_CCER_CC3NE_Pos        (10U)

+#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */

+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */

+#define TIM_CCER_CC3NP_Pos        (11U)

+#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */

+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */

+#define TIM_CCER_CC4E_Pos         (12U)

+#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */

+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */

+#define TIM_CCER_CC4P_Pos         (13U)

+#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */

+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */

+#define TIM_CCER_CC4NP_Pos        (15U)

+#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */

+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */

+#define TIM_CCER_CC5E_Pos         (16U)

+#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */

+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */

+#define TIM_CCER_CC5P_Pos         (17U)

+#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */

+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */

+#define TIM_CCER_CC6E_Pos         (20U)

+#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */

+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */

+#define TIM_CCER_CC6P_Pos         (21U)

+#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */

+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */

+/*******************  Bit definition for TIM_CNT register  ********************/

+#define TIM_CNT_CNT_Pos           (0U)

+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */

+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */

+#define TIM_CNT_UIFCPY_Pos        (31U)

+#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */

+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy */

+/*******************  Bit definition for TIM_PSC register  ********************/

+#define TIM_PSC_PSC_Pos           (0U)

+#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */

+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */

+

+/*******************  Bit definition for TIM_ARR register  ********************/

+#define TIM_ARR_ARR_Pos           (0U)

+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */

+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */

+

+/*******************  Bit definition for TIM_RCR register  ********************/

+#define TIM_RCR_REP_Pos           (0U)

+#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                  /*!< 0x000000FF */

+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */

+

+/*******************  Bit definition for TIM_CCR1 register  *******************/

+#define TIM_CCR1_CCR1_Pos         (0U)

+#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */

+

+/*******************  Bit definition for TIM_CCR2 register  *******************/

+#define TIM_CCR2_CCR2_Pos         (0U)

+#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */

+

+/*******************  Bit definition for TIM_CCR3 register  *******************/

+#define TIM_CCR3_CCR3_Pos         (0U)

+#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */

+

+/*******************  Bit definition for TIM_CCR4 register  *******************/

+#define TIM_CCR4_CCR4_Pos         (0U)

+#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */

+

+/*******************  Bit definition for TIM_CCR5 register  *******************/

+#define TIM_CCR5_CCR5_Pos         (0U)

+#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */

+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */

+#define TIM_CCR5_GC5C1_Pos        (29U)

+#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */

+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */

+#define TIM_CCR5_GC5C2_Pos        (30U)

+#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */

+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */

+#define TIM_CCR5_GC5C3_Pos        (31U)

+#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */

+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */

+

+/*******************  Bit definition for TIM_CCR6 register  *******************/

+#define TIM_CCR6_CCR6_Pos         (0U)

+#define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */

+

+/*******************  Bit definition for TIM_BDTR register  *******************/

+#define TIM_BDTR_DTG_Pos          (0U)

+#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */

+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */

+#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */

+#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */

+#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */

+#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */

+#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */

+#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */

+#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */

+#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */

+

+#define TIM_BDTR_LOCK_Pos         (8U)

+#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */

+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */

+#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */

+#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */

+

+#define TIM_BDTR_OSSI_Pos         (10U)

+#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */

+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */

+#define TIM_BDTR_OSSR_Pos         (11U)

+#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */

+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */

+#define TIM_BDTR_BKE_Pos          (12U)

+#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */

+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break1 */

+#define TIM_BDTR_BKP_Pos          (13U)

+#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */

+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break1 */

+#define TIM_BDTR_AOE_Pos          (14U)

+#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */

+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */

+#define TIM_BDTR_MOE_Pos          (15U)

+#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */

+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */

+

+#define TIM_BDTR_BKF_Pos          (16U)

+#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */

+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break1 */

+#define TIM_BDTR_BK2F_Pos         (20U)

+#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */

+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break2 */

+

+#define TIM_BDTR_BK2E_Pos         (24U)

+#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */

+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break2 */

+#define TIM_BDTR_BK2P_Pos         (25U)

+#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */

+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */

+

+/*******************  Bit definition for TIM_DCR register  ********************/

+#define TIM_DCR_DBA_Pos           (0U)

+#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */

+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */

+#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */

+#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */

+#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */

+#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */

+#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */

+

+#define TIM_DCR_DBL_Pos           (8U)

+#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */

+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */

+#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */

+#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */

+#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */

+#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */

+#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */

+

+/*******************  Bit definition for TIM_DMAR register  *******************/

+#define TIM_DMAR_DMAB_Pos         (0U)

+#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */

+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */

+

+/******************  Bit definition for TIM_CCMR3 register  *******************/

+#define TIM_CCMR3_OC5FE_Pos       (2U)

+#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */

+#define TIM_CCMR3_OC5PE_Pos       (3U)

+#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */

+

+#define TIM_CCMR3_OC5M_Pos        (4U)

+#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */

+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */

+#define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR3_OC5CE_Pos       (7U)

+#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */

+

+#define TIM_CCMR3_OC6FE_Pos       (10U)

+#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 4 Fast enable */

+#define TIM_CCMR3_OC6PE_Pos       (11U)

+#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */

+

+#define TIM_CCMR3_OC6M_Pos        (12U)

+#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */

+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */

+#define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */

+

+#define TIM_CCMR3_OC6CE_Pos       (15U)

+#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 4 Clear Enable */

+/*******************  Bit definition for TIM1_AF1 register  *********************/

+#define TIM1_AF1_BKINE_Pos        (0U)

+#define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */

+#define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */

+#define TIM1_AF1_BKCMP1E_Pos      (1U)

+#define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */

+#define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM1_AF1_BKCMP2E_Pos      (2U)

+#define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */

+#define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit */

+#define TIM1_AF1_BKDF1BK0E_Pos    (8U)

+#define TIM1_AF1_BKDF1BK0E_Msk    (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)            /*!< 0x00000100 */

+#define TIM1_AF1_BKDF1BK0E        TIM1_AF1_BKDF1BK0E_Msk                       /*!<BKDF1BK0E Break input DFSDM Break 0 */

+#define TIM1_AF1_BKINP_Pos        (9U)

+#define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */

+#define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */

+#define TIM1_AF1_BKCMP1P_Pos      (10U)

+#define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */

+#define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM1_AF1_BKCMP2P_Pos      (11U)

+#define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */

+#define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */

+

+#define TIM1_AF1_ETRSEL_Pos       (14U)

+#define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */

+#define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */

+#define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00004000 */

+#define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00008000 */

+#define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00010000 */

+#define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM1_AF2 register  *********************/

+#define TIM1_AF2_BK2INE_Pos       (0U)

+#define TIM1_AF2_BK2INE_Msk       (0x1UL << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */

+#define TIM1_AF2_BK2INE           TIM1_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */

+#define TIM1_AF2_BK2CMP1E_Pos     (1U)

+#define TIM1_AF2_BK2CMP1E_Msk     (0x1UL << TIM1_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */

+#define TIM1_AF2_BK2CMP1E         TIM1_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */

+#define TIM1_AF2_BK2CMP2E_Pos     (2U)

+#define TIM1_AF2_BK2CMP2E_Msk     (0x1UL << TIM1_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */

+#define TIM1_AF2_BK2CMP2E         TIM1_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */

+#define TIM1_AF2_BK2DFBK1E_Pos    (8U)

+#define TIM1_AF2_BK2DFBK1E_Msk    (0x1UL << TIM1_AF2_BK2DFBK1E_Pos)            /*!< 0x00000100 */

+#define TIM1_AF2_BK2DFBK1E        TIM1_AF2_BK2DFBK1E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 1 */

+#define TIM1_AF2_BK2INP_Pos       (9U)

+#define TIM1_AF2_BK2INP_Msk       (0x1UL << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */

+#define TIM1_AF2_BK2INP           TIM1_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */

+#define TIM1_AF2_BK2CMP1P_Pos     (10U)

+#define TIM1_AF2_BK2CMP1P_Msk     (0x1UL << TIM1_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */

+#define TIM1_AF2_BK2CMP1P         TIM1_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */

+#define TIM1_AF2_BK2CMP2P_Pos     (11U)

+#define TIM1_AF2_BK2CMP2P_Msk     (0x1UL << TIM1_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */

+#define TIM1_AF2_BK2CMP2P         TIM1_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */

+

+/*******************  Bit definition for TIM_TISEL register  *********************/

+#define TIM_TISEL_TI1SEL_Pos      (0U)

+#define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */

+#define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/

+#define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000001 */

+#define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000002 */

+#define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000004 */

+#define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000008 */

+

+#define TIM_TISEL_TI2SEL_Pos      (8U)

+#define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */

+#define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/

+#define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000100 */

+#define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000200 */

+#define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000400 */

+#define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000800 */

+

+#define TIM_TISEL_TI3SEL_Pos      (16U)

+#define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */

+#define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/

+#define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00010000 */

+#define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00020000 */

+#define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00040000 */

+#define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00080000 */

+

+#define TIM_TISEL_TI4SEL_Pos      (24U)

+#define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */

+#define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/

+#define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x01000000 */

+#define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x02000000 */

+#define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x04000000 */

+#define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x08000000 */

+

+/*******************  Bit definition for TIM8_AF1 register  *********************/

+#define TIM8_AF1_BKINE_Pos        (0U)

+#define TIM8_AF1_BKINE_Msk        (0x1UL << TIM8_AF1_BKINE_Pos)                /*!< 0x00000001 */

+#define TIM8_AF1_BKINE            TIM8_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */

+#define TIM8_AF1_BKCMP1E_Pos      (1U)

+#define TIM8_AF1_BKCMP1E_Msk      (0x1UL << TIM8_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */

+#define TIM8_AF1_BKCMP1E          TIM8_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM8_AF1_BKCMP2E_Pos      (2U)

+#define TIM8_AF1_BKCMP2E_Msk      (0x1UL << TIM8_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */

+#define TIM8_AF1_BKCMP2E          TIM8_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM8_AF1_BKDFBK2E_Pos     (8U)

+#define TIM8_AF1_BKDFBK2E_Msk     (0x1UL << TIM8_AF1_BKDFBK2E_Pos)             /*!< 0x00000100 */

+#define TIM8_AF1_BKDFBK2E         TIM8_AF1_BKDFBK2E_Msk                        /*!<BKDFBK2E Break input DFSDM Break 2 */

+#define TIM8_AF1_BKINP_Pos        (9U)

+#define TIM8_AF1_BKINP_Msk        (0x1UL << TIM8_AF1_BKINP_Pos)                /*!< 0x00000200 */

+#define TIM8_AF1_BKINP            TIM8_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */

+#define TIM8_AF1_BKCMP1P_Pos      (10U)

+#define TIM8_AF1_BKCMP1P_Msk      (0x1UL << TIM8_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */

+#define TIM8_AF1_BKCMP1P          TIM8_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM8_AF1_BKCMP2P_Pos      (11U)

+#define TIM8_AF1_BKCMP2P_Msk      (0x1UL << TIM8_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */

+#define TIM8_AF1_BKCMP2P          TIM8_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */

+

+#define TIM8_AF1_ETRSEL_Pos       (14U)

+#define TIM8_AF1_ETRSEL_Msk       (0xFUL << TIM8_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */

+#define TIM8_AF1_ETRSEL           TIM8_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */

+#define TIM8_AF1_ETRSEL_0         (0x1UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00004000 */

+#define TIM8_AF1_ETRSEL_1         (0x2UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00008000 */

+#define TIM8_AF1_ETRSEL_2         (0x4UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00010000 */

+#define TIM8_AF1_ETRSEL_3         (0x8UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00020000 */

+/*******************  Bit definition for TIM8_AF2 register  *********************/

+#define TIM8_AF2_BK2INE_Pos       (0U)

+#define TIM8_AF2_BK2INE_Msk       (0x1UL << TIM8_AF2_BK2INE_Pos)               /*!< 0x00000001 */

+#define TIM8_AF2_BK2INE           TIM8_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */

+#define TIM8_AF2_BK2CMP1E_Pos     (1U)

+#define TIM8_AF2_BK2CMP1E_Msk     (0x1UL << TIM8_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */

+#define TIM8_AF2_BK2CMP1E         TIM8_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */

+#define TIM8_AF2_BK2CMP2E_Pos     (2U)

+#define TIM8_AF2_BK2CMP2E_Msk     (0x1UL << TIM8_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */

+#define TIM8_AF2_BK2CMP2E         TIM8_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */

+#define TIM8_AF2_BK2DFBK3E_Pos    (8U)

+#define TIM8_AF2_BK2DFBK3E_Msk    (0x1UL << TIM8_AF2_BK2DFBK3E_Pos)            /*!< 0x00000100 */

+#define TIM8_AF2_BK2DFBK3E        TIM8_AF2_BK2DFBK3E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 3 */

+#define TIM8_AF2_BK2INP_Pos       (9U)

+#define TIM8_AF2_BK2INP_Msk       (0x1UL << TIM8_AF2_BK2INP_Pos)               /*!< 0x00000200 */

+#define TIM8_AF2_BK2INP           TIM8_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */

+#define TIM8_AF2_BK2CMP1P_Pos     (10U)

+#define TIM8_AF2_BK2CMP1P_Msk     (0x1UL << TIM8_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */

+#define TIM8_AF2_BK2CMP1P         TIM8_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */

+#define TIM8_AF2_BK2CMP2P_Pos     (11U)

+#define TIM8_AF2_BK2CMP2P_Msk     (0x1UL << TIM8_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */

+#define TIM8_AF2_BK2CMP2P         TIM8_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */

+

+/*******************  Bit definition for TIM2_AF1 register  *********************/

+#define TIM2_AF1_ETRSEL_Pos      (14U)

+#define TIM2_AF1_ETRSEL_Msk      (0xFUL << TIM2_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM2_AF1_ETRSEL          TIM2_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */

+#define TIM2_AF1_ETRSEL_0        (0x1UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM2_AF1_ETRSEL_1        (0x2UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM2_AF1_ETRSEL_2        (0x4UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM2_AF1_ETRSEL_3        (0x8UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM3_AF1 register  *********************/

+#define TIM3_AF1_ETRSEL_Pos      (14U)

+#define TIM3_AF1_ETRSEL_Msk      (0xFUL << TIM3_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM3_AF1_ETRSEL          TIM3_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */

+#define TIM3_AF1_ETRSEL_0        (0x1UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM3_AF1_ETRSEL_1        (0x2UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM3_AF1_ETRSEL_2        (0x4UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM3_AF1_ETRSEL_3        (0x8UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM5_AF1 register  *********************/

+#define TIM5_AF1_ETRSEL_Pos      (14U)

+#define TIM5_AF1_ETRSEL_Msk      (0xFUL << TIM5_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM5_AF1_ETRSEL          TIM5_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */

+#define TIM5_AF1_ETRSEL_0        (0x1UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM5_AF1_ETRSEL_1        (0x2UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM5_AF1_ETRSEL_2        (0x4UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM5_AF1_ETRSEL_3        (0x8UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM15_AF1 register  *********************/

+#define TIM15_AF1_BKINE_Pos        (0U)

+#define TIM15_AF1_BKINE_Msk        (0x1UL << TIM15_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM15_AF1_BKINE            TIM15_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM15_AF1_BKCMP1E_Pos      (1U)

+#define TIM15_AF1_BKCMP1E_Msk      (0x1UL << TIM15_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM15_AF1_BKCMP1E          TIM15_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM15_AF1_BKCMP2E_Pos      (2U)

+#define TIM15_AF1_BKCMP2E_Msk      (0x1UL << TIM15_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM15_AF1_BKCMP2E          TIM15_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM15_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM15_AF1_BKDF1BK2E_Msk    (0x1UL << TIM15_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM15_AF1_BKDF1BK2E        TIM15_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[0] enable */

+#define TIM15_AF1_BKINP_Pos        (9U)

+#define TIM15_AF1_BKINP_Msk        (0x1UL << TIM15_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM15_AF1_BKINP            TIM15_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM15_AF1_BKCMP1P_Pos      (10U)

+#define TIM15_AF1_BKCMP1P_Msk      (0x1UL << TIM15_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM15_AF1_BKCMP1P          TIM15_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM15_AF1_BKCMP2P_Pos      (11U)

+#define TIM15_AF1_BKCMP2P_Msk      (0x1UL << TIM15_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM15_AF1_BKCMP2P          TIM15_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/*******************  Bit definition for TIM16_ register  *********************/

+#define TIM16_AF1_BKINE_Pos        (0U)

+#define TIM16_AF1_BKINE_Msk        (0x1UL << TIM16_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM16_AF1_BKINE            TIM16_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM16_AF1_BKCMP1E_Pos      (1U)

+#define TIM16_AF1_BKCMP1E_Msk      (0x1UL << TIM16_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM16_AF1_BKCMP1E          TIM16_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM16_AF1_BKCMP2E_Pos      (2U)

+#define TIM16_AF1_BKCMP2E_Msk      (0x1UL << TIM16_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM16_AF1_BKCMP2E          TIM16_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM16_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM16_AF1_BKDF1BK2E_Msk    (0x1UL << TIM16_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM16_AF1_BKDF1BK2E        TIM16_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[1] enable */

+#define TIM16_AF1_BKINP_Pos        (9U)

+#define TIM16_AF1_BKINP_Msk        (0x1UL << TIM16_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM16_AF1_BKINP            TIM16_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM16_AF1_BKCMP1P_Pos      (10U)

+#define TIM16_AF1_BKCMP1P_Msk      (0x1UL << TIM16_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM16_AF1_BKCMP1P          TIM16_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM16_AF1_BKCMP2P_Pos      (11U)

+#define TIM16_AF1_BKCMP2P_Msk      (0x1UL << TIM16_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM16_AF1_BKCMP2P          TIM16_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/*******************  Bit definition for TIM17_AF1 register  *********************/

+#define TIM17_AF1_BKINE_Pos        (0U)

+#define TIM17_AF1_BKINE_Msk        (0x1UL << TIM17_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM17_AF1_BKINE            TIM17_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM17_AF1_BKCMP1E_Pos      (1U)

+#define TIM17_AF1_BKCMP1E_Msk      (0x1UL << TIM17_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM17_AF1_BKCMP1E          TIM17_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM17_AF1_BKCMP2E_Pos      (2U)

+#define TIM17_AF1_BKCMP2E_Msk      (0x1UL << TIM17_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM17_AF1_BKCMP2E          TIM17_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM17_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM17_AF1_BKDF1BK2E_Msk    (0x1UL << TIM17_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM17_AF1_BKDF1BK2E        TIM17_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[2] enable */

+#define TIM17_AF1_BKINP_Pos        (9U)

+#define TIM17_AF1_BKINP_Msk        (0x1UL << TIM17_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM17_AF1_BKINP            TIM17_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM17_AF1_BKCMP1P_Pos      (10U)

+#define TIM17_AF1_BKCMP1P_Msk      (0x1UL << TIM17_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM17_AF1_BKCMP1P          TIM17_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM17_AF1_BKCMP2P_Pos      (11U)

+#define TIM17_AF1_BKCMP2P_Msk      (0x1UL << TIM17_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM17_AF1_BKCMP2P          TIM17_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Low Power Timer (LPTTIM)                           */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for LPTIM_ISR register  *******************/

+#define LPTIM_ISR_CMPM_Pos          (0U)

+#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */

+#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */

+#define LPTIM_ISR_ARRM_Pos          (1U)

+#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */

+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */

+#define LPTIM_ISR_EXTTRIG_Pos       (2U)

+#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */

+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */

+#define LPTIM_ISR_CMPOK_Pos         (3U)

+#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */

+#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */

+#define LPTIM_ISR_ARROK_Pos         (4U)

+#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */

+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */

+#define LPTIM_ISR_UP_Pos            (5U)

+#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */

+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */

+#define LPTIM_ISR_DOWN_Pos          (6U)

+#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */

+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */

+

+/******************  Bit definition for LPTIM_ICR register  *******************/

+#define LPTIM_ICR_CMPMCF_Pos        (0U)

+#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */

+#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */

+#define LPTIM_ICR_ARRMCF_Pos        (1U)

+#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */

+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */

+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)

+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */

+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */

+#define LPTIM_ICR_CMPOKCF_Pos       (3U)

+#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */

+#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */

+#define LPTIM_ICR_ARROKCF_Pos       (4U)

+#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */

+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */

+#define LPTIM_ICR_UPCF_Pos          (5U)

+#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */

+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */

+#define LPTIM_ICR_DOWNCF_Pos        (6U)

+#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */

+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */

+

+/******************  Bit definition for LPTIM_IER register ********************/

+#define LPTIM_IER_CMPMIE_Pos        (0U)

+#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */

+#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */

+#define LPTIM_IER_ARRMIE_Pos        (1U)

+#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */

+#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */

+#define LPTIM_IER_EXTTRIGIE_Pos     (2U)

+#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */

+#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */

+#define LPTIM_IER_CMPOKIE_Pos       (3U)

+#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */

+#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */

+#define LPTIM_IER_ARROKIE_Pos       (4U)

+#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */

+#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */

+#define LPTIM_IER_UPIE_Pos          (5U)

+#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */

+#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */

+#define LPTIM_IER_DOWNIE_Pos        (6U)

+#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */

+#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */

+

+/******************  Bit definition for LPTIM_CFGR register *******************/

+#define LPTIM_CFGR_CKSEL_Pos        (0U)

+#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */

+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */

+

+#define LPTIM_CFGR_CKPOL_Pos        (1U)

+#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */

+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */

+#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */

+#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */

+

+#define LPTIM_CFGR_CKFLT_Pos        (3U)

+#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */

+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */

+#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */

+#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */

+

+#define LPTIM_CFGR_TRGFLT_Pos       (6U)

+#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */

+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */

+#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */

+#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */

+

+#define LPTIM_CFGR_PRESC_Pos        (9U)

+#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */

+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */

+#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */

+#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */

+#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */

+

+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)

+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */

+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */

+#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */

+#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */

+#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */

+

+#define LPTIM_CFGR_TRIGEN_Pos       (17U)

+#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */

+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */

+#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */

+#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */

+

+#define LPTIM_CFGR_TIMOUT_Pos       (19U)

+#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */

+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */

+#define LPTIM_CFGR_WAVE_Pos         (20U)

+#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */

+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */

+#define LPTIM_CFGR_WAVPOL_Pos       (21U)

+#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */

+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */

+#define LPTIM_CFGR_PRELOAD_Pos      (22U)

+#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */

+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */

+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)

+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */

+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */

+#define LPTIM_CFGR_ENC_Pos          (24U)

+#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */

+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */

+

+/******************  Bit definition for LPTIM_CR register  ********************/

+#define LPTIM_CR_ENABLE_Pos         (0U)

+#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */

+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */

+#define LPTIM_CR_SNGSTRT_Pos        (1U)

+#define LPTIM_CR_SNGSTRT_Msk        (0x40001UL << LPTIM_CR_SNGSTRT_Pos)        /*!< 0x00080002 */

+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */

+#define LPTIM_CR_CNTSTRT_Pos        (2U)

+#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */

+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */

+#define LPTIM_CR_COUNTRST_Pos       (3U)

+#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */

+#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Timer Counter reset in synchronous mode*/

+#define LPTIM_CR_RSTARE_Pos         (4U)

+#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */

+#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Timer Counter reset after read enable (asynchronously)*/

+

+

+/******************  Bit definition for LPTIM_CMP register  *******************/

+#define LPTIM_CMP_CMP_Pos           (0U)

+#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */

+

+/******************  Bit definition for LPTIM_ARR register  *******************/

+#define LPTIM_ARR_ARR_Pos           (0U)

+#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */

+

+/******************  Bit definition for LPTIM_CNT register  *******************/

+#define LPTIM_CNT_CNT_Pos           (0U)

+#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */

+

+/******************  Bit definition for LPTIM_CFGR2 register  *****************/

+#define LPTIM_CFGR2_IN1SEL_Pos      (0U)

+#define LPTIM_CFGR2_IN1SEL_Msk      (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000003 */

+#define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< IN1SEL[1:0] bits (Remap selection) */

+#define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000001 */

+#define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000002 */

+#define LPTIM_CFGR2_IN2SEL_Pos      (4U)

+#define LPTIM_CFGR2_IN2SEL_Msk      (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000030 */

+#define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< IN2SEL[5:4] bits (Remap selection) */

+#define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000010 */

+#define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000020 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      Analog Comparators (COMP)                             */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for COMP_SR register  ********************/

+#define COMP_SR_C1VAL_Pos            (0U)

+#define COMP_SR_C1VAL_Msk            (0x1UL << COMP_SR_C1VAL_Pos)              /*!< 0x00000001 */

+#define COMP_SR_C1VAL                COMP_SR_C1VAL_Msk

+#define COMP_SR_C2VAL_Pos            (1U)

+#define COMP_SR_C2VAL_Msk            (0x1UL << COMP_SR_C2VAL_Pos)              /*!< 0x00000002 */

+#define COMP_SR_C2VAL                COMP_SR_C2VAL_Msk

+#define COMP_SR_C1IF_Pos             (16U)

+#define COMP_SR_C1IF_Msk             (0x1UL << COMP_SR_C1IF_Pos)               /*!< 0x00010000 */

+#define COMP_SR_C1IF                 COMP_SR_C1IF_Msk

+#define COMP_SR_C2IF_Pos             (17U)

+#define COMP_SR_C2IF_Msk             (0x1UL << COMP_SR_C2IF_Pos)               /*!< 0x00020000 */

+#define COMP_SR_C2IF                 COMP_SR_C2IF_Msk

+/*******************  Bit definition for COMP_ICFR register  ********************/

+#define COMP_ICFR_C1IF_Pos           (16U)

+#define COMP_ICFR_C1IF_Msk           (0x1UL << COMP_ICFR_C1IF_Pos)             /*!< 0x00010000 */

+#define COMP_ICFR_C1IF               COMP_ICFR_C1IF_Msk

+#define COMP_ICFR_C2IF_Pos           (17U)

+#define COMP_ICFR_C2IF_Msk           (0x1UL << COMP_ICFR_C2IF_Pos)             /*!< 0x00020000 */

+#define COMP_ICFR_C2IF               COMP_ICFR_C2IF_Msk

+/*******************  Bit definition for COMP_OR register  ********************/

+#define COMP_OR_AFOPA6_Pos           (0U)

+#define COMP_OR_AFOPA6_Msk           (0x1UL << COMP_OR_AFOPA6_Pos)             /*!< 0x00000001 */

+#define COMP_OR_AFOPA6               COMP_OR_AFOPA6_Msk

+#define COMP_OR_AFOPA8_Pos           (1U)

+#define COMP_OR_AFOPA8_Msk           (0x1UL << COMP_OR_AFOPA8_Pos)             /*!< 0x00000002 */

+#define COMP_OR_AFOPA8               COMP_OR_AFOPA8_Msk

+#define COMP_OR_AFOPB12_Pos          (2U)

+#define COMP_OR_AFOPB12_Msk          (0x1UL << COMP_OR_AFOPB12_Pos)            /*!< 0x00000004 */

+#define COMP_OR_AFOPB12              COMP_OR_AFOPB12_Msk

+#define COMP_OR_AFOPE6_Pos           (3U)

+#define COMP_OR_AFOPE6_Msk           (0x1UL << COMP_OR_AFOPE6_Pos)             /*!< 0x00000008 */

+#define COMP_OR_AFOPE6               COMP_OR_AFOPE6_Msk

+#define COMP_OR_AFOPE15_Pos          (4U)

+#define COMP_OR_AFOPE15_Msk          (0x1UL << COMP_OR_AFOPE15_Pos)            /*!< 0x00000010 */

+#define COMP_OR_AFOPE15              COMP_OR_AFOPE15_Msk

+#define COMP_OR_AFOPG2_Pos           (5U)

+#define COMP_OR_AFOPG2_Msk           (0x1UL << COMP_OR_AFOPG2_Pos)             /*!< 0x00000020 */

+#define COMP_OR_AFOPG2               COMP_OR_AFOPG2_Msk

+#define COMP_OR_AFOPG3_Pos           (6U)

+#define COMP_OR_AFOPG3_Msk           (0x1UL << COMP_OR_AFOPG3_Pos)             /*!< 0x00000040 */

+#define COMP_OR_AFOPG3               COMP_OR_AFOPG3_Msk

+#define COMP_OR_AFOPG4_Pos           (7U)

+#define COMP_OR_AFOPG4_Msk           (0x1UL << COMP_OR_AFOPG4_Pos)             /*!< 0x00000080 */

+#define COMP_OR_AFOPG4               COMP_OR_AFOPG4_Msk

+#define COMP_OR_AFOPI1_Pos           (8U)

+#define COMP_OR_AFOPI1_Msk           (0x1UL << COMP_OR_AFOPI1_Pos)             /*!< 0x00000100 */

+#define COMP_OR_AFOPI1               COMP_OR_AFOPI1_Msk

+#define COMP_OR_AFOPI4_Pos           (9U)

+#define COMP_OR_AFOPI4_Msk           (0x1UL << COMP_OR_AFOPI4_Pos)             /*!< 0x00000200 */

+#define COMP_OR_AFOPI4               COMP_OR_AFOPI4_Msk

+#define COMP_OR_AFOPK2_Pos           (10U)

+#define COMP_OR_AFOPK2_Msk           (0x1UL << COMP_OR_AFOPK2_Pos)             /*!< 0x00000400 */

+#define COMP_OR_AFOPK2               COMP_OR_AFOPK2_Msk

+

+/*!< ******************  Bit definition for COMP_CFGRx register  ********************/

+#define COMP_CFGRx_EN_Pos            (0U)

+#define COMP_CFGRx_EN_Msk            (0x1UL << COMP_CFGRx_EN_Pos)              /*!< 0x00000001 */

+#define COMP_CFGRx_EN                COMP_CFGRx_EN_Msk                         /*!< COMPx enable bit                     */

+#define COMP_CFGRx_BRGEN_Pos         (1U)

+#define COMP_CFGRx_BRGEN_Msk         (0x1UL << COMP_CFGRx_BRGEN_Pos)           /*!< 0x00000002 */

+#define COMP_CFGRx_BRGEN             COMP_CFGRx_BRGEN_Msk                      /*!< COMPx Scaler bridge enable           */

+#define COMP_CFGRx_SCALEN_Pos        (2U)

+#define COMP_CFGRx_SCALEN_Msk        (0x1UL << COMP_CFGRx_SCALEN_Pos)          /*!< 0x00000004 */

+#define COMP_CFGRx_SCALEN            COMP_CFGRx_SCALEN_Msk                     /*!< COMPx Voltage scaler enable bit      */

+#define COMP_CFGRx_POLARITY_Pos      (3U)

+#define COMP_CFGRx_POLARITY_Msk      (0x1UL << COMP_CFGRx_POLARITY_Pos)        /*!< 0x00000008 */

+#define COMP_CFGRx_POLARITY          COMP_CFGRx_POLARITY_Msk                   /*!< COMPx  polarity selection bit        */

+#define COMP_CFGRx_WINMODE_Pos       (4U)

+#define COMP_CFGRx_WINMODE_Msk       (0x1UL << COMP_CFGRx_WINMODE_Pos)         /*!< 0x00000010 */

+#define COMP_CFGRx_WINMODE           COMP_CFGRx_WINMODE_Msk                    /*!< COMPx Windows mode selection bit     */

+#define COMP_CFGRx_ITEN_Pos          (6U)

+#define COMP_CFGRx_ITEN_Msk          (0x1UL << COMP_CFGRx_ITEN_Pos)            /*!< 0x00000040 */

+#define COMP_CFGRx_ITEN              COMP_CFGRx_ITEN_Msk                       /*!< COMPx  interrupt enable              */

+#define COMP_CFGRx_HYST_Pos          (8U)

+#define COMP_CFGRx_HYST_Msk          (0x3UL << COMP_CFGRx_HYST_Pos)            /*!< 0x00000300 */

+#define COMP_CFGRx_HYST              COMP_CFGRx_HYST_Msk                       /*!< COMPx  hysteresis selection bits     */

+#define COMP_CFGRx_HYST_0            (0x1UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000100 */

+#define COMP_CFGRx_HYST_1            (0x2UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000200 */

+#define COMP_CFGRx_PWRMODE_Pos       (12U)

+#define COMP_CFGRx_PWRMODE_Msk       (0x3UL << COMP_CFGRx_PWRMODE_Pos)         /*!< 0x00003000 */

+#define COMP_CFGRx_PWRMODE           COMP_CFGRx_PWRMODE_Msk                    /*!< COMPx Power Mode of the comparator   */

+#define COMP_CFGRx_PWRMODE_0         (0x1UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00001000 */

+#define COMP_CFGRx_PWRMODE_1         (0x2UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00002000 */

+#define COMP_CFGRx_INMSEL_Pos        (16U)

+#define COMP_CFGRx_INMSEL_Msk        (0x7UL << COMP_CFGRx_INMSEL_Pos)          /*!< 0x00070000 */

+#define COMP_CFGRx_INMSEL            COMP_CFGRx_INMSEL_Msk                     /*!< COMPx  input minus selection bit  */

+#define COMP_CFGRx_INMSEL_0          (0x1UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00010000 */

+#define COMP_CFGRx_INMSEL_1          (0x2UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00020000 */

+#define COMP_CFGRx_INMSEL_2          (0x4UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00040000 */

+#define COMP_CFGRx_INPSEL_Pos        (20U)

+#define COMP_CFGRx_INPSEL_Msk        (0x1UL << COMP_CFGRx_INPSEL_Pos)          /*!< 0x00100000 */

+#define COMP_CFGRx_INPSEL            COMP_CFGRx_INPSEL_Msk                     /*!< COMPx  input plus selection bit       */

+#define COMP_CFGRx_BLANKING_Pos      (24U)

+#define COMP_CFGRx_BLANKING_Msk      (0xFUL << COMP_CFGRx_BLANKING_Pos)        /*!< 0x0F000000 */

+#define COMP_CFGRx_BLANKING          COMP_CFGRx_BLANKING_Msk                   /*!< COMPx  blanking source selection bits */

+#define COMP_CFGRx_BLANKING_0        (0x1UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x01000000 */

+#define COMP_CFGRx_BLANKING_1        (0x2UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x02000000 */

+#define COMP_CFGRx_BLANKING_2        (0x4UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x04000000 */

+#define COMP_CFGRx_LOCK_Pos          (31U)

+#define COMP_CFGRx_LOCK_Msk          (0x1UL << COMP_CFGRx_LOCK_Pos)            /*!< 0x80000000 */

+#define COMP_CFGRx_LOCK              COMP_CFGRx_LOCK_Msk                       /*!< COMPx Lock Bit                        */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for USART_CR1 register  *******************/

+#define USART_CR1_UE_Pos                (0U)

+#define USART_CR1_UE_Msk                (0x1UL << USART_CR1_UE_Pos)            /*!< 0x00000001 */

+#define USART_CR1_UE                    USART_CR1_UE_Msk                       /*!< USART Enable */

+#define USART_CR1_UESM_Pos              (1U)

+#define USART_CR1_UESM_Msk              (0x1UL << USART_CR1_UESM_Pos)          /*!< 0x00000002 */

+#define USART_CR1_UESM                  USART_CR1_UESM_Msk                     /*!< USART Enable in STOP Mode */

+#define USART_CR1_RE_Pos                (2U)

+#define USART_CR1_RE_Msk                (0x1UL << USART_CR1_RE_Pos)            /*!< 0x00000004 */

+#define USART_CR1_RE                    USART_CR1_RE_Msk                       /*!< Receiver Enable */

+#define USART_CR1_TE_Pos                (3U)

+#define USART_CR1_TE_Msk                (0x1UL << USART_CR1_TE_Pos)            /*!< 0x00000008 */

+#define USART_CR1_TE                    USART_CR1_TE_Msk                       /*!< Transmitter Enable */

+#define USART_CR1_IDLEIE_Pos            (4U)

+#define USART_CR1_IDLEIE_Msk            (0x1UL << USART_CR1_IDLEIE_Pos)        /*!< 0x00000010 */

+#define USART_CR1_IDLEIE                USART_CR1_IDLEIE_Msk                   /*!< IDLE Interrupt Enable */

+#define USART_CR1_RXNEIE_RXFNEIE_Pos    (5U)

+#define USART_CR1_RXNEIE_RXFNEIE_Msk    (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */

+#define USART_CR1_RXNEIE_RXFNEIE        USART_CR1_RXNEIE_RXFNEIE_Msk           /*!< RXNE and RX FIFO Not Empty Interrupt Enable */

+#define USART_CR1_TCIE_Pos              (6U)

+#define USART_CR1_TCIE_Msk              (0x1UL << USART_CR1_TCIE_Pos)          /*!< 0x00000040 */

+#define USART_CR1_TCIE                  USART_CR1_TCIE_Msk                     /*!< Transmission Complete Interrupt Enable */

+#define USART_CR1_TXEIE_TXFNFIE_Pos     (7U)

+#define USART_CR1_TXEIE_TXFNFIE_Msk     (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */

+#define USART_CR1_TXEIE_TXFNFIE         USART_CR1_TXEIE_TXFNFIE_Msk            /*!< TXE and TX FIFO Not Full Interrupt Enable */

+#define USART_CR1_PEIE_Pos              (8U)

+#define USART_CR1_PEIE_Msk              (0x1UL << USART_CR1_PEIE_Pos)          /*!< 0x00000100 */

+#define USART_CR1_PEIE                  USART_CR1_PEIE_Msk                     /*!< PE Interrupt Enable */

+#define USART_CR1_PS_Pos                (9U)

+#define USART_CR1_PS_Msk                (0x1UL << USART_CR1_PS_Pos)            /*!< 0x00000200 */

+#define USART_CR1_PS                    USART_CR1_PS_Msk                       /*!< Parity Selection */

+#define USART_CR1_PCE_Pos               (10U)

+#define USART_CR1_PCE_Msk               (0x1UL << USART_CR1_PCE_Pos)           /*!< 0x00000400 */

+#define USART_CR1_PCE                   USART_CR1_PCE_Msk                      /*!< Parity Control Enable */

+#define USART_CR1_WAKE_Pos              (11U)

+#define USART_CR1_WAKE_Msk              (0x1UL << USART_CR1_WAKE_Pos)          /*!< 0x00000800 */

+#define USART_CR1_WAKE                  USART_CR1_WAKE_Msk                     /*!< Receiver Wakeup method */

+#define USART_CR1_M_Pos                 (12U)

+#define USART_CR1_M_Msk                 (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */

+#define USART_CR1_M                     USART_CR1_M_Msk                        /*!< Word length */

+#define USART_CR1_M0_Pos                (12U)

+#define USART_CR1_M0_Msk                (0x1UL << USART_CR1_M0_Pos)            /*!< 0x00001000 */

+#define USART_CR1_M0                    USART_CR1_M0_Msk                       /*!< Word length - Bit 0 */

+#define USART_CR1_MME_Pos               (13U)

+#define USART_CR1_MME_Msk               (0x1UL << USART_CR1_MME_Pos)           /*!< 0x00002000 */

+#define USART_CR1_MME                   USART_CR1_MME_Msk                      /*!< Mute Mode Enable */

+#define USART_CR1_CMIE_Pos              (14U)

+#define USART_CR1_CMIE_Msk              (0x1UL << USART_CR1_CMIE_Pos)          /*!< 0x00004000 */

+#define USART_CR1_CMIE                  USART_CR1_CMIE_Msk                     /*!< Character match interrupt enable */

+#define USART_CR1_OVER8_Pos             (15U)

+#define USART_CR1_OVER8_Msk             (0x1UL << USART_CR1_OVER8_Pos)         /*!< 0x00008000 */

+#define USART_CR1_OVER8                 USART_CR1_OVER8_Msk                    /*!< Oversampling by 8-bit or 16-bit mode */

+#define USART_CR1_DEDT_Pos              (16U)

+#define USART_CR1_DEDT_Msk              (0x1FUL << USART_CR1_DEDT_Pos)         /*!< 0x001F0000 */

+#define USART_CR1_DEDT                  USART_CR1_DEDT_Msk                     /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */

+#define USART_CR1_DEDT_0                (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */

+#define USART_CR1_DEDT_1                (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */

+#define USART_CR1_DEDT_2                (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */

+#define USART_CR1_DEDT_3                (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */

+#define USART_CR1_DEDT_4                (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */

+#define USART_CR1_DEAT_Pos              (21U)

+#define USART_CR1_DEAT_Msk              (0x1FUL << USART_CR1_DEAT_Pos)         /*!< 0x03E00000 */

+#define USART_CR1_DEAT                  USART_CR1_DEAT_Msk                     /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */

+#define USART_CR1_DEAT_0                (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */

+#define USART_CR1_DEAT_1                (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */

+#define USART_CR1_DEAT_2                (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */

+#define USART_CR1_DEAT_3                (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */

+#define USART_CR1_DEAT_4                (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */

+#define USART_CR1_RTOIE_Pos             (26U)

+#define USART_CR1_RTOIE_Msk             (0x1UL << USART_CR1_RTOIE_Pos)         /*!< 0x04000000 */

+#define USART_CR1_RTOIE                 USART_CR1_RTOIE_Msk                    /*!< Receive Time Out interrupt enable */

+#define USART_CR1_EOBIE_Pos             (27U)

+#define USART_CR1_EOBIE_Msk             (0x1UL << USART_CR1_EOBIE_Pos)         /*!< 0x08000000 */

+#define USART_CR1_EOBIE                 USART_CR1_EOBIE_Msk                    /*!< End of Block interrupt enable */

+#define USART_CR1_M1_Pos                (28U)

+#define USART_CR1_M1_Msk                (0x1UL << USART_CR1_M1_Pos)            /*!< 0x10000000 */

+#define USART_CR1_M1                    USART_CR1_M1_Msk                       /*!< Word length - Bit 1 */

+#define USART_CR1_FIFOEN_Pos            (29U)

+#define USART_CR1_FIFOEN_Msk            (0x1UL << USART_CR1_FIFOEN_Pos)        /*!< 0x20000000 */

+#define USART_CR1_FIFOEN                USART_CR1_FIFOEN_Msk                   /*!< FIFO mode enable */

+#define USART_CR1_TXFEIE_Pos            (30U)

+#define USART_CR1_TXFEIE_Msk            (0x1UL << USART_CR1_TXFEIE_Pos)        /*!< 0x40000000 */

+#define USART_CR1_TXFEIE                USART_CR1_TXFEIE_Msk                   /*!< TXFIFO empty interrupt enable */

+#define USART_CR1_RXFFIE_Pos            (31U)

+#define USART_CR1_RXFFIE_Msk            (0x1UL << USART_CR1_RXFFIE_Pos)        /*!< 0x80000000 */

+#define USART_CR1_RXFFIE                USART_CR1_RXFFIE_Msk                   /*!< RXFIFO Full interrupt enable */

+

+/* Legacy define */

+#define  USART_CR1_RXNEIE  USART_CR1_RXNEIE_RXFNEIE

+#define  USART_CR1_TXEIE   USART_CR1_TXEIE_TXFNFIE

+

+/******************  Bit definition for USART_CR2 register  *******************/

+#define USART_CR2_SLVEN_Pos             (0U)

+#define USART_CR2_SLVEN_Msk             (0x1UL << USART_CR2_SLVEN_Pos)         /*!< 0x00000001 */

+#define USART_CR2_SLVEN                 USART_CR2_SLVEN_Msk                    /*!< Synchronous Slave mode Enable */

+#define USART_CR2_DIS_NSS_Pos           (3U)

+#define USART_CR2_DIS_NSS_Msk           (0x1UL << USART_CR2_DIS_NSS_Pos)       /*!< 0x00000008 */

+#define USART_CR2_DIS_NSS               USART_CR2_DIS_NSS_Msk                  /*!< Negative Slave Select (NSS) pin management */

+#define USART_CR2_ADDM7_Pos             (4U)

+#define USART_CR2_ADDM7_Msk             (0x1UL << USART_CR2_ADDM7_Pos)         /*!< 0x00000010 */

+#define USART_CR2_ADDM7                 USART_CR2_ADDM7_Msk                    /*!< 7-bit or 4-bit Address Detection */

+#define USART_CR2_LBDL_Pos              (5U)

+#define USART_CR2_LBDL_Msk              (0x1UL << USART_CR2_LBDL_Pos)          /*!< 0x00000020 */

+#define USART_CR2_LBDL                  USART_CR2_LBDL_Msk                     /*!< LIN Break Detection Length */

+#define USART_CR2_LBDIE_Pos             (6U)

+#define USART_CR2_LBDIE_Msk             (0x1UL << USART_CR2_LBDIE_Pos)         /*!< 0x00000040 */

+#define USART_CR2_LBDIE                 USART_CR2_LBDIE_Msk                    /*!< LIN Break Detection Interrupt Enable */

+#define USART_CR2_LBCL_Pos              (8U)

+#define USART_CR2_LBCL_Msk              (0x1UL << USART_CR2_LBCL_Pos)          /*!< 0x00000100 */

+#define USART_CR2_LBCL                  USART_CR2_LBCL_Msk                     /*!< Last Bit Clock pulse */

+#define USART_CR2_CPHA_Pos              (9U)

+#define USART_CR2_CPHA_Msk              (0x1UL << USART_CR2_CPHA_Pos)          /*!< 0x00000200 */

+#define USART_CR2_CPHA                  USART_CR2_CPHA_Msk                     /*!< Clock Phase */

+#define USART_CR2_CPOL_Pos              (10U)

+#define USART_CR2_CPOL_Msk              (0x1UL << USART_CR2_CPOL_Pos)          /*!< 0x00000400 */

+#define USART_CR2_CPOL                  USART_CR2_CPOL_Msk                     /*!< Clock Polarity */

+#define USART_CR2_CLKEN_Pos             (11U)

+#define USART_CR2_CLKEN_Msk             (0x1UL << USART_CR2_CLKEN_Pos)         /*!< 0x00000800 */

+#define USART_CR2_CLKEN                 USART_CR2_CLKEN_Msk                    /*!< Clock Enable */

+#define USART_CR2_STOP_Pos              (12U)

+#define USART_CR2_STOP_Msk              (0x3UL << USART_CR2_STOP_Pos)          /*!< 0x00003000 */

+#define USART_CR2_STOP                  USART_CR2_STOP_Msk                     /*!< STOP[1:0] bits (STOP bits) */

+#define USART_CR2_STOP_0                (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */

+#define USART_CR2_STOP_1                (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */

+#define USART_CR2_LINEN_Pos             (14U)

+#define USART_CR2_LINEN_Msk             (0x1UL << USART_CR2_LINEN_Pos)         /*!< 0x00004000 */

+#define USART_CR2_LINEN                 USART_CR2_LINEN_Msk                    /*!< LIN mode enable */

+#define USART_CR2_SWAP_Pos              (15U)

+#define USART_CR2_SWAP_Msk              (0x1UL << USART_CR2_SWAP_Pos)          /*!< 0x00008000 */

+#define USART_CR2_SWAP                  USART_CR2_SWAP_Msk                     /*!< SWAP TX/RX pins */

+#define USART_CR2_RXINV_Pos             (16U)

+#define USART_CR2_RXINV_Msk             (0x1UL << USART_CR2_RXINV_Pos)         /*!< 0x00010000 */

+#define USART_CR2_RXINV                 USART_CR2_RXINV_Msk                    /*!< RX pin active level inversion */

+#define USART_CR2_TXINV_Pos             (17U)

+#define USART_CR2_TXINV_Msk             (0x1UL << USART_CR2_TXINV_Pos)         /*!< 0x00020000 */

+#define USART_CR2_TXINV                 USART_CR2_TXINV_Msk                    /*!< TX pin active level inversion */

+#define USART_CR2_DATAINV_Pos           (18U)

+#define USART_CR2_DATAINV_Msk           (0x1UL << USART_CR2_DATAINV_Pos)       /*!< 0x00040000 */

+#define USART_CR2_DATAINV               USART_CR2_DATAINV_Msk                  /*!< Binary data inversion */

+#define USART_CR2_MSBFIRST_Pos          (19U)

+#define USART_CR2_MSBFIRST_Msk          (0x1UL << USART_CR2_MSBFIRST_Pos)      /*!< 0x00080000 */

+#define USART_CR2_MSBFIRST              USART_CR2_MSBFIRST_Msk                 /*!< Most Significant Bit First */

+#define USART_CR2_ABREN_Pos             (20U)

+#define USART_CR2_ABREN_Msk             (0x1UL << USART_CR2_ABREN_Pos)         /*!< 0x00100000 */

+#define USART_CR2_ABREN                 USART_CR2_ABREN_Msk                    /*!< Auto Baud-Rate Enable*/

+#define USART_CR2_ABRMODE_Pos           (21U)

+#define USART_CR2_ABRMODE_Msk           (0x3UL << USART_CR2_ABRMODE_Pos)       /*!< 0x00600000 */

+#define USART_CR2_ABRMODE               USART_CR2_ABRMODE_Msk                  /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */

+#define USART_CR2_ABRMODE_0             (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */

+#define USART_CR2_ABRMODE_1             (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */

+#define USART_CR2_RTOEN_Pos             (23U)

+#define USART_CR2_RTOEN_Msk             (0x1UL << USART_CR2_RTOEN_Pos)         /*!< 0x00800000 */

+#define USART_CR2_RTOEN                 USART_CR2_RTOEN_Msk                    /*!< Receiver Time-Out enable */

+#define USART_CR2_ADD_Pos               (24U)

+#define USART_CR2_ADD_Msk               (0xFFUL << USART_CR2_ADD_Pos)          /*!< 0xFF000000 */

+#define USART_CR2_ADD                   USART_CR2_ADD_Msk                      /*!< Address of the USART node */

+

+/******************  Bit definition for USART_CR3 register  *******************/

+#define USART_CR3_EIE_Pos               (0U)

+#define USART_CR3_EIE_Msk               (0x1UL << USART_CR3_EIE_Pos)           /*!< 0x00000001 */

+#define USART_CR3_EIE                   USART_CR3_EIE_Msk                      /*!< Error Interrupt Enable */

+#define USART_CR3_IREN_Pos              (1U)

+#define USART_CR3_IREN_Msk              (0x1UL << USART_CR3_IREN_Pos)          /*!< 0x00000002 */

+#define USART_CR3_IREN                  USART_CR3_IREN_Msk                     /*!< IrDA mode Enable */

+#define USART_CR3_IRLP_Pos              (2U)

+#define USART_CR3_IRLP_Msk              (0x1UL << USART_CR3_IRLP_Pos)          /*!< 0x00000004 */

+#define USART_CR3_IRLP                  USART_CR3_IRLP_Msk                     /*!< IrDA Low-Power */

+#define USART_CR3_HDSEL_Pos             (3U)

+#define USART_CR3_HDSEL_Msk             (0x1UL << USART_CR3_HDSEL_Pos)         /*!< 0x00000008 */

+#define USART_CR3_HDSEL                 USART_CR3_HDSEL_Msk                    /*!< Half-Duplex Selection */

+#define USART_CR3_NACK_Pos              (4U)

+#define USART_CR3_NACK_Msk              (0x1UL << USART_CR3_NACK_Pos)          /*!< 0x00000010 */

+#define USART_CR3_NACK                  USART_CR3_NACK_Msk                     /*!< SmartCard NACK enable */

+#define USART_CR3_SCEN_Pos              (5U)

+#define USART_CR3_SCEN_Msk              (0x1UL << USART_CR3_SCEN_Pos)          /*!< 0x00000020 */

+#define USART_CR3_SCEN                  USART_CR3_SCEN_Msk                     /*!< SmartCard mode enable */

+#define USART_CR3_DMAR_Pos              (6U)

+#define USART_CR3_DMAR_Msk              (0x1UL << USART_CR3_DMAR_Pos)          /*!< 0x00000040 */

+#define USART_CR3_DMAR                  USART_CR3_DMAR_Msk                     /*!< DMA Enable Receiver */

+#define USART_CR3_DMAT_Pos              (7U)

+#define USART_CR3_DMAT_Msk              (0x1UL << USART_CR3_DMAT_Pos)          /*!< 0x00000080 */

+#define USART_CR3_DMAT                  USART_CR3_DMAT_Msk                     /*!< DMA Enable Transmitter */

+#define USART_CR3_RTSE_Pos              (8U)

+#define USART_CR3_RTSE_Msk              (0x1UL << USART_CR3_RTSE_Pos)          /*!< 0x00000100 */

+#define USART_CR3_RTSE                  USART_CR3_RTSE_Msk                     /*!< RTS Enable */

+#define USART_CR3_CTSE_Pos              (9U)

+#define USART_CR3_CTSE_Msk              (0x1UL << USART_CR3_CTSE_Pos)          /*!< 0x00000200 */

+#define USART_CR3_CTSE                  USART_CR3_CTSE_Msk                     /*!< CTS Enable */

+#define USART_CR3_CTSIE_Pos             (10U)

+#define USART_CR3_CTSIE_Msk             (0x1UL << USART_CR3_CTSIE_Pos)         /*!< 0x00000400 */

+#define USART_CR3_CTSIE                 USART_CR3_CTSIE_Msk                    /*!< CTS Interrupt Enable */

+#define USART_CR3_ONEBIT_Pos            (11U)

+#define USART_CR3_ONEBIT_Msk            (0x1UL << USART_CR3_ONEBIT_Pos)        /*!< 0x00000800 */

+#define USART_CR3_ONEBIT                USART_CR3_ONEBIT_Msk                   /*!< One sample bit method enable */

+#define USART_CR3_OVRDIS_Pos            (12U)

+#define USART_CR3_OVRDIS_Msk            (0x1UL << USART_CR3_OVRDIS_Pos)        /*!< 0x00001000 */

+#define USART_CR3_OVRDIS                USART_CR3_OVRDIS_Msk                   /*!< Overrun Disable */

+#define USART_CR3_DDRE_Pos              (13U)

+#define USART_CR3_DDRE_Msk              (0x1UL << USART_CR3_DDRE_Pos)          /*!< 0x00002000 */

+#define USART_CR3_DDRE                  USART_CR3_DDRE_Msk                     /*!< DMA Disable on Reception Error */

+#define USART_CR3_DEM_Pos               (14U)

+#define USART_CR3_DEM_Msk               (0x1UL << USART_CR3_DEM_Pos)           /*!< 0x00004000 */

+#define USART_CR3_DEM                   USART_CR3_DEM_Msk                      /*!< Driver Enable Mode */

+#define USART_CR3_DEP_Pos               (15U)

+#define USART_CR3_DEP_Msk               (0x1UL << USART_CR3_DEP_Pos)           /*!< 0x00008000 */

+#define USART_CR3_DEP                   USART_CR3_DEP_Msk                      /*!< Driver Enable Polarity Selection */

+#define USART_CR3_SCARCNT_Pos           (17U)

+#define USART_CR3_SCARCNT_Msk           (0x7UL << USART_CR3_SCARCNT_Pos)       /*!< 0x000E0000 */

+#define USART_CR3_SCARCNT               USART_CR3_SCARCNT_Msk                  /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */

+#define USART_CR3_SCARCNT_0             (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */

+#define USART_CR3_SCARCNT_1             (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */

+#define USART_CR3_SCARCNT_2             (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */

+#define USART_CR3_WUS_Pos               (20U)

+#define USART_CR3_WUS_Msk               (0x3UL << USART_CR3_WUS_Pos)           /*!< 0x00300000 */

+#define USART_CR3_WUS                   USART_CR3_WUS_Msk                      /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */

+#define USART_CR3_WUS_0                 (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */

+#define USART_CR3_WUS_1                 (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */

+#define USART_CR3_WUFIE_Pos             (22U)

+#define USART_CR3_WUFIE_Msk             (0x1UL << USART_CR3_WUFIE_Pos)         /*!< 0x00400000 */

+#define USART_CR3_WUFIE                 USART_CR3_WUFIE_Msk                    /*!< Wake Up Interrupt Enable */

+#define USART_CR3_TXFTIE_Pos            (23U)

+#define USART_CR3_TXFTIE_Msk            (0x1UL << USART_CR3_TXFTIE_Pos)        /*!< 0x00800000 */

+#define USART_CR3_TXFTIE                USART_CR3_TXFTIE_Msk                   /*!< TXFIFO threshold interrupt enable */

+#define USART_CR3_TCBGTIE_Pos           (24U)

+#define USART_CR3_TCBGTIE_Msk           (0x1UL << USART_CR3_TCBGTIE_Pos)       /*!< 0x01000000 */

+#define USART_CR3_TCBGTIE               USART_CR3_TCBGTIE_Msk                  /*!< Transmission Complete before guard time, interrupt enable */

+#define USART_CR3_RXFTCFG_Pos           (25U)

+#define USART_CR3_RXFTCFG_Msk           (0x7UL << USART_CR3_RXFTCFG_Pos)       /*!< 0x0E000000 */

+#define USART_CR3_RXFTCFG               USART_CR3_RXFTCFG_Msk                  /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */

+#define USART_CR3_RXFTCFG_0             (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */

+#define USART_CR3_RXFTCFG_1             (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */

+#define USART_CR3_RXFTCFG_2             (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */

+#define USART_CR3_RXFTIE_Pos            (28U)

+#define USART_CR3_RXFTIE_Msk            (0x1UL << USART_CR3_RXFTIE_Pos)        /*!< 0x10000000 */

+#define USART_CR3_RXFTIE                USART_CR3_RXFTIE_Msk                   /*!< RXFIFO threshold interrupt enable */

+#define USART_CR3_TXFTCFG_Pos           (29U)

+#define USART_CR3_TXFTCFG_Msk           (0x7UL << USART_CR3_TXFTCFG_Pos)       /*!< 0xE0000000 */

+#define USART_CR3_TXFTCFG               USART_CR3_TXFTCFG_Msk                  /*!< TXFIFO [2:0] threshold configuration */

+#define USART_CR3_TXFTCFG_0             (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */

+#define USART_CR3_TXFTCFG_1             (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */

+#define USART_CR3_TXFTCFG_2             (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */

+

+/******************  Bit definition for USART_BRR register  *******************/

+#define USART_BRR_DIV_FRACTION_Pos      (0U)

+#define USART_BRR_DIV_FRACTION_Msk      (0xFUL << USART_BRR_DIV_FRACTION_Pos)  /*!< 0x0000000F */

+#define USART_BRR_DIV_FRACTION          USART_BRR_DIV_FRACTION_Msk             /*!< Fraction of USARTDIV */

+#define USART_BRR_DIV_MANTISSA_Pos      (4U)

+#define USART_BRR_DIV_MANTISSA_Msk      (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */

+#define USART_BRR_DIV_MANTISSA          USART_BRR_DIV_MANTISSA_Msk             /*!< Mantissa of USARTDIV */

+

+/******************  Bit definition for USART_GTPR register  ******************/

+#define USART_GTPR_PSC_Pos              (0U)

+#define USART_GTPR_PSC_Msk              (0xFFUL << USART_GTPR_PSC_Pos)         /*!< 0x000000FF */

+#define USART_GTPR_PSC                  USART_GTPR_PSC_Msk                     /*!< PSC[7:0] bits (Prescaler value) */

+#define USART_GTPR_GT_Pos               (8U)

+#define USART_GTPR_GT_Msk               (0xFFUL << USART_GTPR_GT_Pos)          /*!< 0x0000FF00 */

+#define USART_GTPR_GT                   USART_GTPR_GT_Msk                      /*!< GT[7:0] bits (Guard time value) */

+

+/*******************  Bit definition for USART_RTOR register  *****************/

+#define USART_RTOR_RTO_Pos              (0U)

+#define USART_RTOR_RTO_Msk              (0xFFFFFFUL << USART_RTOR_RTO_Pos)     /*!< 0x00FFFFFF */

+#define USART_RTOR_RTO                  USART_RTOR_RTO_Msk                     /*!< Receiver Time Out Value */

+#define USART_RTOR_BLEN_Pos             (24U)

+#define USART_RTOR_BLEN_Msk             (0xFFUL << USART_RTOR_BLEN_Pos)        /*!< 0xFF000000 */

+#define USART_RTOR_BLEN                 USART_RTOR_BLEN_Msk                    /*!< Block Length */

+

+/*******************  Bit definition for USART_RQR register  ******************/

+#define USART_RQR_ABRRQ_Pos             (0U)

+#define USART_RQR_ABRRQ_Msk             (0x1UL << USART_RQR_ABRRQ_Pos)         /*!< 0x00000001 */

+#define USART_RQR_ABRRQ                 USART_RQR_ABRRQ_Msk                    /*!< Auto-Baud Rate Request */

+#define USART_RQR_SBKRQ_Pos             (1U)

+#define USART_RQR_SBKRQ_Msk             (0x1UL << USART_RQR_SBKRQ_Pos)         /*!< 0x00000002 */

+#define USART_RQR_SBKRQ                 USART_RQR_SBKRQ_Msk                    /*!< Send Break Request */

+#define USART_RQR_MMRQ_Pos              (2U)

+#define USART_RQR_MMRQ_Msk              (0x1UL << USART_RQR_MMRQ_Pos)          /*!< 0x00000004 */

+#define USART_RQR_MMRQ                  USART_RQR_MMRQ_Msk                     /*!< Mute Mode Request */

+#define USART_RQR_RXFRQ_Pos             (3U)

+#define USART_RQR_RXFRQ_Msk             (0x1UL << USART_RQR_RXFRQ_Pos)         /*!< 0x00000008 */

+#define USART_RQR_RXFRQ                 USART_RQR_RXFRQ_Msk                    /*!< Receive Data flush Request */

+#define USART_RQR_TXFRQ_Pos             (4U)

+#define USART_RQR_TXFRQ_Msk             (0x1UL << USART_RQR_TXFRQ_Pos)         /*!< 0x00000010 */

+#define USART_RQR_TXFRQ                 USART_RQR_TXFRQ_Msk                    /*!< Transmit data flush Request */

+

+/*******************  Bit definition for USART_ISR register  ******************/

+#define USART_ISR_PE_Pos                (0U)

+#define USART_ISR_PE_Msk                (0x1UL << USART_ISR_PE_Pos)            /*!< 0x00000001 */

+#define USART_ISR_PE                    USART_ISR_PE_Msk                       /*!< Parity Error */

+#define USART_ISR_FE_Pos                (1U)

+#define USART_ISR_FE_Msk                (0x1UL << USART_ISR_FE_Pos)            /*!< 0x00000002 */

+#define USART_ISR_FE                    USART_ISR_FE_Msk                       /*!< Framing Error */

+#define USART_ISR_NE_Pos                (2U)

+#define USART_ISR_NE_Msk                (0x1UL << USART_ISR_NE_Pos)            /*!< 0x00000004 */

+#define USART_ISR_NE                    USART_ISR_NE_Msk                       /*!< Noise detected Flag */

+#define USART_ISR_ORE_Pos               (3U)

+#define USART_ISR_ORE_Msk               (0x1UL << USART_ISR_ORE_Pos)           /*!< 0x00000008 */

+#define USART_ISR_ORE                   USART_ISR_ORE_Msk                      /*!< OverRun Error */

+#define USART_ISR_IDLE_Pos              (4U)

+#define USART_ISR_IDLE_Msk              (0x1UL << USART_ISR_IDLE_Pos)          /*!< 0x00000010 */

+#define USART_ISR_IDLE                  USART_ISR_IDLE_Msk                     /*!< IDLE line detected */

+#define USART_ISR_RXNE_RXFNE_Pos        (5U)

+#define USART_ISR_RXNE_RXFNE_Msk        (0x1UL << USART_ISR_RXNE_RXFNE_Pos)    /*!< 0x00000020 */

+#define USART_ISR_RXNE_RXFNE            USART_ISR_RXNE_RXFNE_Msk               /*!< Read Data Register or RX FIFO Not Empty */

+#define USART_ISR_TC_Pos                (6U)

+#define USART_ISR_TC_Msk                (0x1UL << USART_ISR_TC_Pos)            /*!< 0x00000040 */

+#define USART_ISR_TC                    USART_ISR_TC_Msk                       /*!< Transmission Complete */

+#define USART_ISR_TXE_TXFNF_Pos         (7U)

+#define USART_ISR_TXE_TXFNF_Msk         (0x1UL << USART_ISR_TXE_TXFNF_Pos)     /*!< 0x00000080 */

+#define USART_ISR_TXE_TXFNF             USART_ISR_TXE_TXFNF_Msk                /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */

+#define USART_ISR_LBDF_Pos              (8U)

+#define USART_ISR_LBDF_Msk              (0x1UL << USART_ISR_LBDF_Pos)          /*!< 0x00000100 */

+#define USART_ISR_LBDF                  USART_ISR_LBDF_Msk                     /*!< LIN Break Detection Flag */

+#define USART_ISR_CTSIF_Pos             (9U)

+#define USART_ISR_CTSIF_Msk             (0x1UL << USART_ISR_CTSIF_Pos)         /*!< 0x00000200 */

+#define USART_ISR_CTSIF                 USART_ISR_CTSIF_Msk                    /*!< CTS interrupt flag */

+#define USART_ISR_CTS_Pos               (10U)

+#define USART_ISR_CTS_Msk               (0x1UL << USART_ISR_CTS_Pos)           /*!< 0x00000400 */

+#define USART_ISR_CTS                   USART_ISR_CTS_Msk                      /*!< CTS flag */

+#define USART_ISR_RTOF_Pos              (11U)

+#define USART_ISR_RTOF_Msk              (0x1UL << USART_ISR_RTOF_Pos)          /*!< 0x00000800 */

+#define USART_ISR_RTOF                  USART_ISR_RTOF_Msk                     /*!< Receiver Time Out */

+#define USART_ISR_EOBF_Pos              (12U)

+#define USART_ISR_EOBF_Msk              (0x1UL << USART_ISR_EOBF_Pos)          /*!< 0x00001000 */

+#define USART_ISR_EOBF                  USART_ISR_EOBF_Msk                     /*!< End Of Block Flag */

+#define USART_ISR_UDR_Pos               (13U)

+#define USART_ISR_UDR_Msk               (0x1UL << USART_ISR_UDR_Pos)           /*!< 0x00002000 */

+#define USART_ISR_UDR                   USART_ISR_UDR_Msk                      /*!< SPI slave underrun error flag */

+#define USART_ISR_ABRE_Pos              (14U)

+#define USART_ISR_ABRE_Msk              (0x1UL << USART_ISR_ABRE_Pos)          /*!< 0x00004000 */

+#define USART_ISR_ABRE                  USART_ISR_ABRE_Msk                     /*!< Auto-Baud Rate Error */

+#define USART_ISR_ABRF_Pos              (15U)

+#define USART_ISR_ABRF_Msk              (0x1UL << USART_ISR_ABRF_Pos)          /*!< 0x00008000 */

+#define USART_ISR_ABRF                  USART_ISR_ABRF_Msk                     /*!< Auto-Baud Rate Flag */

+#define USART_ISR_BUSY_Pos              (16U)

+#define USART_ISR_BUSY_Msk              (0x1UL << USART_ISR_BUSY_Pos)          /*!< 0x00010000 */

+#define USART_ISR_BUSY                  USART_ISR_BUSY_Msk                     /*!< Busy Flag */

+#define USART_ISR_CMF_Pos               (17U)

+#define USART_ISR_CMF_Msk               (0x1UL << USART_ISR_CMF_Pos)           /*!< 0x00020000 */

+#define USART_ISR_CMF                   USART_ISR_CMF_Msk                      /*!< Character Match Flag */

+#define USART_ISR_SBKF_Pos              (18U)

+#define USART_ISR_SBKF_Msk              (0x1UL << USART_ISR_SBKF_Pos)          /*!< 0x00040000 */

+#define USART_ISR_SBKF                  USART_ISR_SBKF_Msk                     /*!< Send Break Flag */

+#define USART_ISR_RWU_Pos               (19U)

+#define USART_ISR_RWU_Msk               (0x1UL << USART_ISR_RWU_Pos)           /*!< 0x00080000 */

+#define USART_ISR_RWU                   USART_ISR_RWU_Msk                      /*!< Receive Wake Up from mute mode Flag */

+#define USART_ISR_WUF_Pos               (20U)

+#define USART_ISR_WUF_Msk               (0x1UL << USART_ISR_WUF_Pos)           /*!< 0x00100000 */

+#define USART_ISR_WUF                   USART_ISR_WUF_Msk                      /*!< Wake Up from stop mode Flag */

+#define USART_ISR_TEACK_Pos             (21U)

+#define USART_ISR_TEACK_Msk             (0x1UL << USART_ISR_TEACK_Pos)         /*!< 0x00200000 */

+#define USART_ISR_TEACK                 USART_ISR_TEACK_Msk                    /*!< Transmit Enable Acknowledge Flag */

+#define USART_ISR_REACK_Pos             (22U)

+#define USART_ISR_REACK_Msk             (0x1UL << USART_ISR_REACK_Pos)         /*!< 0x00400000 */

+#define USART_ISR_REACK                 USART_ISR_REACK_Msk                    /*!< Receive Enable Acknowledge Flag */

+#define USART_ISR_TXFE_Pos              (23U)

+#define USART_ISR_TXFE_Msk              (0x1UL << USART_ISR_TXFE_Pos)          /*!< 0x00800000 */

+#define USART_ISR_TXFE                  USART_ISR_TXFE_Msk                     /*!< TXFIFO Empty */

+#define USART_ISR_RXFF_Pos              (24U)

+#define USART_ISR_RXFF_Msk              (0x1UL << USART_ISR_RXFF_Pos)          /*!< 0x01000000 */

+#define USART_ISR_RXFF                  USART_ISR_RXFF_Msk                     /*!< RXFIFO Full Flag */

+#define USART_ISR_TCBGT_Pos             (25U)

+#define USART_ISR_TCBGT_Msk             (0x1UL << USART_ISR_TCBGT_Pos)         /*!< 0x02000000 */

+#define USART_ISR_TCBGT                 USART_ISR_TCBGT_Msk                    /*!< Transmission complete before guard time Flag */

+#define USART_ISR_RXFT_Pos              (26U)

+#define USART_ISR_RXFT_Msk              (0x1UL << USART_ISR_RXFT_Pos)          /*!< 0x04000000 */

+#define USART_ISR_RXFT                  USART_ISR_RXFT_Msk                     /*!< RXFIFO threshold Flag */

+#define USART_ISR_TXFT_Pos              (27U)

+#define USART_ISR_TXFT_Msk              (0x1UL << USART_ISR_TXFT_Pos)          /*!< 0x08000000 */

+#define USART_ISR_TXFT                  USART_ISR_TXFT_Msk                     /*!< TXFIFO threshold Flag */

+

+/*******************  Bit definition for USART_ICR register  ******************/

+#define USART_ICR_PECF_Pos              (0U)

+#define USART_ICR_PECF_Msk              (0x1UL << USART_ICR_PECF_Pos)          /*!< 0x00000001 */

+#define USART_ICR_PECF                  USART_ICR_PECF_Msk                     /*!< Parity Error Clear Flag */

+#define USART_ICR_FECF_Pos              (1U)

+#define USART_ICR_FECF_Msk              (0x1UL << USART_ICR_FECF_Pos)          /*!< 0x00000002 */

+#define USART_ICR_FECF                  USART_ICR_FECF_Msk                     /*!< Framing Error Clear Flag */

+#define USART_ICR_NECF_Pos              (2U)

+#define USART_ICR_NECF_Msk              (0x1UL << USART_ICR_NECF_Pos)          /*!< 0x00000004 */

+#define USART_ICR_NECF                  USART_ICR_NECF_Msk                     /*!< Noise detected Clear Flag */

+#define USART_ICR_ORECF_Pos             (3U)

+#define USART_ICR_ORECF_Msk             (0x1UL << USART_ICR_ORECF_Pos)         /*!< 0x00000008 */

+#define USART_ICR_ORECF                 USART_ICR_ORECF_Msk                    /*!< OverRun Error Clear Flag */

+#define USART_ICR_IDLECF_Pos            (4U)

+#define USART_ICR_IDLECF_Msk            (0x1UL << USART_ICR_IDLECF_Pos)        /*!< 0x00000010 */

+#define USART_ICR_IDLECF                USART_ICR_IDLECF_Msk                   /*!< IDLE line detected Clear Flag */

+#define USART_ICR_TXFECF_Pos            (5U)

+#define USART_ICR_TXFECF_Msk            (0x1UL << USART_ICR_TXFECF_Pos)        /*!< 0x00000020 */

+#define USART_ICR_TXFECF                USART_ICR_TXFECF_Msk                   /*!< TXFIFO empty clear flag */

+#define USART_ICR_TCCF_Pos              (6U)

+#define USART_ICR_TCCF_Msk              (0x1UL << USART_ICR_TCCF_Pos)          /*!< 0x00000040 */

+#define USART_ICR_TCCF                  USART_ICR_TCCF_Msk                     /*!< Transmission Complete Clear Flag */

+#define USART_ICR_TCBGTCF_Pos           (7U)

+#define USART_ICR_TCBGTCF_Msk           (0x1UL << USART_ICR_TCBGTCF_Pos)       /*!< 0x00000080 */

+#define USART_ICR_TCBGTCF               USART_ICR_TCBGTCF_Msk                  /*!< Transmission complete before guard time Clear Flag */

+#define USART_ICR_LBDCF_Pos             (8U)

+#define USART_ICR_LBDCF_Msk             (0x1UL << USART_ICR_LBDCF_Pos)         /*!< 0x00000100 */

+#define USART_ICR_LBDCF                 USART_ICR_LBDCF_Msk                    /*!< LIN Break Detection Clear Flag */

+#define USART_ICR_CTSCF_Pos             (9U)

+#define USART_ICR_CTSCF_Msk             (0x1UL << USART_ICR_CTSCF_Pos)         /*!< 0x00000200 */

+#define USART_ICR_CTSCF                 USART_ICR_CTSCF_Msk                    /*!< CTS Interrupt Clear Flag */

+#define USART_ICR_RTOCF_Pos             (11U)

+#define USART_ICR_RTOCF_Msk             (0x1UL << USART_ICR_RTOCF_Pos)         /*!< 0x00000800 */

+#define USART_ICR_RTOCF                 USART_ICR_RTOCF_Msk                    /*!< Receiver Time Out Clear Flag */

+#define USART_ICR_EOBCF_Pos             (12U)

+#define USART_ICR_EOBCF_Msk             (0x1UL << USART_ICR_EOBCF_Pos)         /*!< 0x00001000 */

+#define USART_ICR_EOBCF                 USART_ICR_EOBCF_Msk                    /*!< End Of Block Clear Flag */

+#define USART_ICR_UDRCF_Pos             (13U)

+#define USART_ICR_UDRCF_Msk             (0x1UL << USART_ICR_UDRCF_Pos)         /*!< 0x00002000 */

+#define USART_ICR_UDRCF                 USART_ICR_UDRCF_Msk                    /*!< SPI slave underrun clear flag */

+#define USART_ICR_CMCF_Pos              (17U)

+#define USART_ICR_CMCF_Msk              (0x1UL << USART_ICR_CMCF_Pos)          /*!< 0x00020000 */

+#define USART_ICR_CMCF                  USART_ICR_CMCF_Msk                     /*!< Character Match Clear Flag */

+#define USART_ICR_WUCF_Pos              (20U)

+#define USART_ICR_WUCF_Msk              (0x1UL << USART_ICR_WUCF_Pos)          /*!< 0x00100000 */

+#define USART_ICR_WUCF                  USART_ICR_WUCF_Msk                     /*!< Wake Up from stop mode Clear Flag */

+

+/*******************  Bit definition for USART_RDR register  ******************/

+#define USART_RDR_RDR_Pos               (0U)

+#define USART_RDR_RDR_Msk               (0x1FFUL << USART_RDR_RDR_Pos)         /*!< 0x000001FF */

+#define USART_RDR_RDR                   USART_RDR_RDR_Msk                      /*!< RDR[8:0] bits (Receive Data value) */

+

+/*******************  Bit definition for USART_TDR register  ******************/

+#define USART_TDR_TDR_Pos               (0U)

+#define USART_TDR_TDR_Msk               (0x1FFUL << USART_TDR_TDR_Pos)         /*!< 0x000001FF */

+#define USART_TDR_TDR                   USART_TDR_TDR_Msk                      /*!< TDR[8:0] bits (Transmit Data value) */

+

+/*******************  Bit definition for USART_PRESC register  ******************/

+#define USART_PRESC_PRESCALER_Pos       (0U)

+#define USART_PRESC_PRESCALER_Msk       (0xFUL << USART_PRESC_PRESCALER_Pos)   /*!< 0x0000000F */

+#define USART_PRESC_PRESCALER           USART_PRESC_PRESCALER_Msk              /*!< PRESCALER[3:0] bits (Clock prescaler) */

+#define USART_PRESC_PRESCALER_0         (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */

+#define USART_PRESC_PRESCALER_1         (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */

+#define USART_PRESC_PRESCALER_2         (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */

+#define USART_PRESC_PRESCALER_3         (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */

+

+/******************************************************************************/

+/*                                                                            */

+/*           Single Wire Protocol Master Interface (SWPMI)                    */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for SWPMI_CR register   ********************/

+#define SWPMI_CR_RXDMA_Pos       (0U)

+#define SWPMI_CR_RXDMA_Msk       (0x1UL << SWPMI_CR_RXDMA_Pos)                 /*!< 0x00000001 */

+#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */

+#define SWPMI_CR_TXDMA_Pos       (1U)

+#define SWPMI_CR_TXDMA_Msk       (0x1UL << SWPMI_CR_TXDMA_Pos)                 /*!< 0x00000002 */

+#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */

+#define SWPMI_CR_RXMODE_Pos      (2U)

+#define SWPMI_CR_RXMODE_Msk      (0x1UL << SWPMI_CR_RXMODE_Pos)                /*!< 0x00000004 */

+#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */

+#define SWPMI_CR_TXMODE_Pos      (3U)

+#define SWPMI_CR_TXMODE_Msk      (0x1UL << SWPMI_CR_TXMODE_Pos)                /*!< 0x00000008 */

+#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */

+#define SWPMI_CR_LPBK_Pos        (4U)

+#define SWPMI_CR_LPBK_Msk        (0x1UL << SWPMI_CR_LPBK_Pos)                  /*!< 0x00000010 */

+#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */

+#define SWPMI_CR_SWPACT_Pos      (5U)

+#define SWPMI_CR_SWPACT_Msk      (0x1UL << SWPMI_CR_SWPACT_Pos)                /*!< 0x00000020 */

+#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */

+#define SWPMI_CR_DEACT_Pos       (10U)

+#define SWPMI_CR_DEACT_Msk       (0x1UL << SWPMI_CR_DEACT_Pos)                 /*!< 0x00000400 */

+#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */

+#define SWPMI_CR_SWPEN_Pos       (11U)

+#define SWPMI_CR_SWPEN_Msk       (0x1UL << SWPMI_CR_SWPEN_Pos)                 /*!< 0x00000800 */

+#define SWPMI_CR_SWPEN           SWPMI_CR_SWPEN_Msk                            /*!<Single wire protocol master transceiver enable       */

+

+/*******************  Bit definition for SWPMI_BRR register  ********************/

+#define SWPMI_BRR_BR_Pos         (0U)

+#define SWPMI_BRR_BR_Msk         (0xFFUL << SWPMI_BRR_BR_Pos)                  /*!< 0x000000FF */

+#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[7:0] bits (Bitrate prescaler) */

+

+/*******************  Bit definition for SWPMI_ISR register  ********************/

+#define SWPMI_ISR_RXBFF_Pos      (0U)

+#define SWPMI_ISR_RXBFF_Msk      (0x1UL << SWPMI_ISR_RXBFF_Pos)                /*!< 0x00000001 */

+#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */

+#define SWPMI_ISR_TXBEF_Pos      (1U)

+#define SWPMI_ISR_TXBEF_Msk      (0x1UL << SWPMI_ISR_TXBEF_Pos)                /*!< 0x00000002 */

+#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */

+#define SWPMI_ISR_RXBERF_Pos     (2U)

+#define SWPMI_ISR_RXBERF_Msk     (0x1UL << SWPMI_ISR_RXBERF_Pos)               /*!< 0x00000004 */

+#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */

+#define SWPMI_ISR_RXOVRF_Pos     (3U)

+#define SWPMI_ISR_RXOVRF_Msk     (0x1UL << SWPMI_ISR_RXOVRF_Pos)               /*!< 0x00000008 */

+#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */

+#define SWPMI_ISR_TXUNRF_Pos     (4U)

+#define SWPMI_ISR_TXUNRF_Msk     (0x1UL << SWPMI_ISR_TXUNRF_Pos)               /*!< 0x00000010 */

+#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */

+#define SWPMI_ISR_RXNE_Pos       (5U)

+#define SWPMI_ISR_RXNE_Msk       (0x1UL << SWPMI_ISR_RXNE_Pos)                 /*!< 0x00000020 */

+#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */

+#define SWPMI_ISR_TXE_Pos        (6U)

+#define SWPMI_ISR_TXE_Msk        (0x1UL << SWPMI_ISR_TXE_Pos)                  /*!< 0x00000040 */

+#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */

+#define SWPMI_ISR_TCF_Pos        (7U)

+#define SWPMI_ISR_TCF_Msk        (0x1UL << SWPMI_ISR_TCF_Pos)                  /*!< 0x00000080 */

+#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */

+#define SWPMI_ISR_SRF_Pos        (8U)

+#define SWPMI_ISR_SRF_Msk        (0x1UL << SWPMI_ISR_SRF_Pos)                  /*!< 0x00000100 */

+#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */

+#define SWPMI_ISR_SUSP_Pos       (9U)

+#define SWPMI_ISR_SUSP_Msk       (0x1UL << SWPMI_ISR_SUSP_Pos)                 /*!< 0x00000200 */

+#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */

+#define SWPMI_ISR_DEACTF_Pos     (10U)

+#define SWPMI_ISR_DEACTF_Msk     (0x1UL << SWPMI_ISR_DEACTF_Pos)               /*!< 0x00000400 */

+#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */

+#define SWPMI_ISR_RDYF_Pos       (11U)

+#define SWPMI_ISR_RDYF_Msk       (0x1UL << SWPMI_ISR_RDYF_Pos)                 /*!< 0x00000800 */

+#define SWPMI_ISR_RDYF           SWPMI_ISR_RDYF_Msk                            /*!<Transceiver ready flag          */

+

+/*******************  Bit definition for SWPMI_ICR register  ********************/

+#define SWPMI_ICR_CRXBFF_Pos     (0U)

+#define SWPMI_ICR_CRXBFF_Msk     (0x1UL << SWPMI_ICR_CRXBFF_Pos)               /*!< 0x00000001 */

+#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */

+#define SWPMI_ICR_CTXBEF_Pos     (1U)

+#define SWPMI_ICR_CTXBEF_Msk     (0x1UL << SWPMI_ICR_CTXBEF_Pos)               /*!< 0x00000002 */

+#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */

+#define SWPMI_ICR_CRXBERF_Pos    (2U)

+#define SWPMI_ICR_CRXBERF_Msk    (0x1UL << SWPMI_ICR_CRXBERF_Pos)              /*!< 0x00000004 */

+#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */

+#define SWPMI_ICR_CRXOVRF_Pos    (3U)

+#define SWPMI_ICR_CRXOVRF_Msk    (0x1UL << SWPMI_ICR_CRXOVRF_Pos)              /*!< 0x00000008 */

+#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */

+#define SWPMI_ICR_CTXUNRF_Pos    (4U)

+#define SWPMI_ICR_CTXUNRF_Msk    (0x1UL << SWPMI_ICR_CTXUNRF_Pos)              /*!< 0x00000010 */

+#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */

+#define SWPMI_ICR_CTCF_Pos       (7U)

+#define SWPMI_ICR_CTCF_Msk       (0x1UL << SWPMI_ICR_CTCF_Pos)                 /*!< 0x00000080 */

+#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */

+#define SWPMI_ICR_CSRF_Pos       (8U)

+#define SWPMI_ICR_CSRF_Msk       (0x1UL << SWPMI_ICR_CSRF_Pos)                 /*!< 0x00000100 */

+#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */

+#define SWPMI_ICR_CRDYF_Pos      (11U)

+#define SWPMI_ICR_CRDYF_Msk      (0x1UL << SWPMI_ICR_CRDYF_Pos)                /*!< 0x00000800 */

+#define SWPMI_ICR_CRDYF          SWPMI_ICR_CRDYF_Msk                           /*!<Clear transceiver ready flag         */

+

+/*******************  Bit definition for SWPMI_IER register  ********************/

+#define SWPMI_IER_RXBFIE_Pos     (0U)

+#define SWPMI_IER_RXBFIE_Msk     (0x1UL << SWPMI_IER_RXBFIE_Pos)               /*!< 0x00000001 */

+#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */

+#define SWPMI_IER_TXBEIE_Pos     (1U)

+#define SWPMI_IER_TXBEIE_Msk     (0x1UL << SWPMI_IER_TXBEIE_Pos)               /*!< 0x00000002 */

+#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */

+#define SWPMI_IER_RXBERIE_Pos    (2U)

+#define SWPMI_IER_RXBERIE_Msk    (0x1UL << SWPMI_IER_RXBERIE_Pos)              /*!< 0x00000004 */

+#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */

+#define SWPMI_IER_RXOVRIE_Pos    (3U)

+#define SWPMI_IER_RXOVRIE_Msk    (0x1UL << SWPMI_IER_RXOVRIE_Pos)              /*!< 0x00000008 */

+#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */

+#define SWPMI_IER_TXUNRIE_Pos    (4U)

+#define SWPMI_IER_TXUNRIE_Msk    (0x1UL << SWPMI_IER_TXUNRIE_Pos)              /*!< 0x00000010 */

+#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */

+#define SWPMI_IER_RIE_Pos        (5U)

+#define SWPMI_IER_RIE_Msk        (0x1UL << SWPMI_IER_RIE_Pos)                  /*!< 0x00000020 */

+#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */

+#define SWPMI_IER_TIE_Pos        (6U)

+#define SWPMI_IER_TIE_Msk        (0x1UL << SWPMI_IER_TIE_Pos)                  /*!< 0x00000040 */

+#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */

+#define SWPMI_IER_TCIE_Pos       (7U)

+#define SWPMI_IER_TCIE_Msk       (0x1UL << SWPMI_IER_TCIE_Pos)                 /*!< 0x00000080 */

+#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */

+#define SWPMI_IER_SRIE_Pos       (8U)

+#define SWPMI_IER_SRIE_Msk       (0x1UL << SWPMI_IER_SRIE_Pos)                 /*!< 0x00000100 */

+#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */

+#define SWPMI_IER_RDYIE_Pos      (11U)

+#define SWPMI_IER_RDYIE_Msk      (0x1UL << SWPMI_IER_RDYIE_Pos)                /*!< 0x00000800 */

+#define SWPMI_IER_RDYIE          SWPMI_IER_RDYIE_Msk                           /*!<Transceiver ready interrupt enable          */

+

+/*******************  Bit definition for SWPMI_RFL register  ********************/

+#define SWPMI_RFL_RFL_Pos        (0U)

+#define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */

+#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */

+#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */

+

+/*******************  Bit definition for SWPMI_TDR register  ********************/

+#define SWPMI_TDR_TD_Pos         (0U)

+#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)            /*!< 0xFFFFFFFF */

+#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */

+

+/*******************  Bit definition for SWPMI_RDR register  ********************/

+#define SWPMI_RDR_RD_Pos         (0U)

+#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)            /*!< 0xFFFFFFFF */

+#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Recive Data Register           */

+

+

+/*******************  Bit definition for SWPMI_OR register  ********************/

+#define SWPMI_OR_TBYP_Pos        (0U)

+#define SWPMI_OR_TBYP_Msk        (0x1UL << SWPMI_OR_TBYP_Pos)                  /*!< 0x00000001 */

+#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */

+#define SWPMI_OR_CLASS_Pos       (1U)

+#define SWPMI_OR_CLASS_Msk       (0x1UL << SWPMI_OR_CLASS_Pos)                 /*!< 0x00000002 */

+#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP CLASS selection */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            Window WATCHDOG                                 */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for WWDG_CR register  ********************/

+#define WWDG_CR_T_Pos           (0U)

+#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */

+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */

+#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */

+#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */

+#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */

+#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */

+#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */

+#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */

+#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */

+

+#define WWDG_CR_WDGA_Pos        (7U)

+#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */

+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */

+

+/*******************  Bit definition for WWDG_CFR register  *******************/

+#define WWDG_CFR_W_Pos          (0U)

+#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */

+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */

+#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */

+#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */

+#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */

+#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */

+#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */

+#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */

+#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */

+

+#define WWDG_CFR_EWI_Pos        (9U)

+#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */

+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */

+

+#define WWDG_CFR_WDGTB_Pos      (11U)

+#define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */

+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */

+#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000800 */

+#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00001000 */

+#define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00002000 */

+

+/*******************  Bit definition for WWDG_SR register  ********************/

+#define WWDG_SR_EWIF_Pos        (0U)

+#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */

+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                DBG                                         */

+/*                                                                            */

+/******************************************************************************/

+/*********************************  DEVICE ID  ********************************/

+#define STM32H7_DEV_ID           0x450UL

+

+/********************  Bit definition for DBGMCU_IDCODE register  *************/

+#define DBGMCU_IDCODE_DEV_ID_Pos          (0U)

+#define DBGMCU_IDCODE_DEV_ID_Msk          (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */

+#define DBGMCU_IDCODE_DEV_ID              DBGMCU_IDCODE_DEV_ID_Msk

+#define DBGMCU_IDCODE_REV_ID_Pos          (16U)

+#define DBGMCU_IDCODE_REV_ID_Msk          (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */

+#define DBGMCU_IDCODE_REV_ID              DBGMCU_IDCODE_REV_ID_Msk

+

+/********************  Bit definition for DBGMCU_CR register  *****************/

+#define DBGMCU_CR_DBG_SLEEPD1_Pos         (0U)

+#define DBGMCU_CR_DBG_SLEEPD1_Msk         (0x1UL << DBGMCU_CR_DBG_SLEEPD1_Pos) /*!< 0x00000001 */

+#define DBGMCU_CR_DBG_SLEEPD1             DBGMCU_CR_DBG_SLEEPD1_Msk

+#define DBGMCU_CR_DBG_STOPD1_Pos          (1U)

+#define DBGMCU_CR_DBG_STOPD1_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD1_Pos)  /*!< 0x00000002 */

+#define DBGMCU_CR_DBG_STOPD1              DBGMCU_CR_DBG_STOPD1_Msk

+#define DBGMCU_CR_DBG_STANDBYD1_Pos       (2U)

+#define DBGMCU_CR_DBG_STANDBYD1_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos) /*!< 0x00000004 */

+#define DBGMCU_CR_DBG_STANDBYD1           DBGMCU_CR_DBG_STANDBYD1_Msk

+#define DBGMCU_CR_DBG_SLEEPD2_Pos         (3U)

+#define DBGMCU_CR_DBG_SLEEPD2_Msk         (0x1UL << DBGMCU_CR_DBG_SLEEPD2_Pos) /*!< 0x00000008 */

+#define DBGMCU_CR_DBG_SLEEPD2             DBGMCU_CR_DBG_SLEEPD2_Msk

+#define DBGMCU_CR_DBG_STOPD2_Pos          (4U)

+#define DBGMCU_CR_DBG_STOPD2_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD2_Pos)  /*!< 0x00000010 */

+#define DBGMCU_CR_DBG_STOPD2              DBGMCU_CR_DBG_STOPD2_Msk

+#define DBGMCU_CR_DBG_STANDBYD2_Pos       (5U)

+#define DBGMCU_CR_DBG_STANDBYD2_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD2_Pos) /*!< 0x00000020 */

+#define DBGMCU_CR_DBG_STANDBYD2           DBGMCU_CR_DBG_STANDBYD2_Msk

+#define DBGMCU_CR_DBG_STOPD3_Pos          (7U)

+#define DBGMCU_CR_DBG_STOPD3_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos)  /*!< 0x00000080 */

+#define DBGMCU_CR_DBG_STOPD3              DBGMCU_CR_DBG_STOPD3_Msk

+#define DBGMCU_CR_DBG_STANDBYD3_Pos       (8U)

+#define DBGMCU_CR_DBG_STANDBYD3_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos) /*!< 0x00000100 */

+#define DBGMCU_CR_DBG_STANDBYD3           DBGMCU_CR_DBG_STANDBYD3_Msk

+#define DBGMCU_CR_DBG_TRACECKEN_Pos       (20U)

+#define DBGMCU_CR_DBG_TRACECKEN_Msk       (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */

+#define DBGMCU_CR_DBG_TRACECKEN           DBGMCU_CR_DBG_TRACECKEN_Msk

+#define DBGMCU_CR_DBG_CKD1EN_Pos          (21U)

+#define DBGMCU_CR_DBG_CKD1EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD1EN_Pos)  /*!< 0x00200000 */

+#define DBGMCU_CR_DBG_CKD1EN              DBGMCU_CR_DBG_CKD1EN_Msk

+#define DBGMCU_CR_DBG_CKD3EN_Pos          (22U)

+#define DBGMCU_CR_DBG_CKD3EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD3EN_Pos)  /*!< 0x00400000 */

+#define DBGMCU_CR_DBG_CKD3EN              DBGMCU_CR_DBG_CKD3EN_Msk

+#define DBGMCU_CR_DBG_TRGOEN_Pos          (28U)

+#define DBGMCU_CR_DBG_TRGOEN_Msk          (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)  /*!< 0x10000000 */

+#define DBGMCU_CR_DBG_TRGOEN              DBGMCU_CR_DBG_TRGOEN_Msk

+

+/********************  Bit definition for APB3FZ1 register  ************/

+#define DBGMCU_APB3FZ1_DBG_WWDG1_Pos      (6U)

+#define DBGMCU_APB3FZ1_DBG_WWDG1_Msk      (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB3FZ1_DBG_WWDG1          DBGMCU_APB3FZ1_DBG_WWDG1_Msk

+/********************  Bit definition for APB3FZ2 register  ************/

+#define DBGMCU_APB3FZ2_DBG_WWDG1_Pos      (6U)

+#define DBGMCU_APB3FZ2_DBG_WWDG1_Msk      (0x1UL << DBGMCU_APB3FZ2_DBG_WWDG1_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB3FZ2_DBG_WWDG1          DBGMCU_APB3FZ2_DBG_WWDG1_Msk

+/********************  Bit definition for APB1LFZ1 register  ************/

+#define DBGMCU_APB1LFZ1_DBG_TIM2_Pos      (0U)

+#define DBGMCU_APB1LFZ1_DBG_TIM2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB1LFZ1_DBG_TIM2          DBGMCU_APB1LFZ1_DBG_TIM2_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM3_Pos      (1U)

+#define DBGMCU_APB1LFZ1_DBG_TIM3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB1LFZ1_DBG_TIM3          DBGMCU_APB1LFZ1_DBG_TIM3_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM4_Pos      (2U)

+#define DBGMCU_APB1LFZ1_DBG_TIM4_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */

+#define DBGMCU_APB1LFZ1_DBG_TIM4          DBGMCU_APB1LFZ1_DBG_TIM4_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM5_Pos      (3U)

+#define DBGMCU_APB1LFZ1_DBG_TIM5_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */

+#define DBGMCU_APB1LFZ1_DBG_TIM5          DBGMCU_APB1LFZ1_DBG_TIM5_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM6_Pos      (4U)

+#define DBGMCU_APB1LFZ1_DBG_TIM6_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */

+#define DBGMCU_APB1LFZ1_DBG_TIM6          DBGMCU_APB1LFZ1_DBG_TIM6_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM7_Pos      (5U)

+#define DBGMCU_APB1LFZ1_DBG_TIM7_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */

+#define DBGMCU_APB1LFZ1_DBG_TIM7          DBGMCU_APB1LFZ1_DBG_TIM7_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM12_Pos     (6U)

+#define DBGMCU_APB1LFZ1_DBG_TIM12_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB1LFZ1_DBG_TIM12         DBGMCU_APB1LFZ1_DBG_TIM12_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM13_Pos     (7U)

+#define DBGMCU_APB1LFZ1_DBG_TIM13_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB1LFZ1_DBG_TIM13         DBGMCU_APB1LFZ1_DBG_TIM13_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM14_Pos     (8U)

+#define DBGMCU_APB1LFZ1_DBG_TIM14_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */

+#define DBGMCU_APB1LFZ1_DBG_TIM14         DBGMCU_APB1LFZ1_DBG_TIM14_Msk

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos    (9U)

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1        DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk

+#define DBGMCU_APB1LFZ1_DBG_WWDG2_Pos     (11U)

+#define DBGMCU_APB1LFZ1_DBG_WWDG2_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_WWDG2_Pos) /*!< 0x00000800 */

+#define DBGMCU_APB1LFZ1_DBG_WWDG2         DBGMCU_APB1LFZ1_DBG_WWDG2_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C1_Pos      (21U)

+#define DBGMCU_APB1LFZ1_DBG_I2C1_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C1          DBGMCU_APB1LFZ1_DBG_I2C1_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C2_Pos      (22U)

+#define DBGMCU_APB1LFZ1_DBG_I2C2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C2          DBGMCU_APB1LFZ1_DBG_I2C2_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C3_Pos      (23U)

+#define DBGMCU_APB1LFZ1_DBG_I2C3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C3          DBGMCU_APB1LFZ1_DBG_I2C3_Msk

+

+/********************  Bit definition for APB1LFZ2 register  ************/

+#define DBGMCU_APB1LFZ2_DBG_TIM2_Pos      (0U)

+#define DBGMCU_APB1LFZ2_DBG_TIM2_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM2_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB1LFZ2_DBG_TIM2          DBGMCU_APB1LFZ2_DBG_TIM2_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM3_Pos      (1U)

+#define DBGMCU_APB1LFZ2_DBG_TIM3_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM3_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB1LFZ2_DBG_TIM3          DBGMCU_APB1LFZ2_DBG_TIM3_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM4_Pos      (2U)

+#define DBGMCU_APB1LFZ2_DBG_TIM4_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM4_Pos) /*!< 0x00000004 */

+#define DBGMCU_APB1LFZ2_DBG_TIM4          DBGMCU_APB1LFZ2_DBG_TIM4_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM5_Pos      (3U)

+#define DBGMCU_APB1LFZ2_DBG_TIM5_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM5_Pos) /*!< 0x00000008 */

+#define DBGMCU_APB1LFZ2_DBG_TIM5          DBGMCU_APB1LFZ2_DBG_TIM5_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM6_Pos      (4U)

+#define DBGMCU_APB1LFZ2_DBG_TIM6_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM6_Pos) /*!< 0x00000010 */

+#define DBGMCU_APB1LFZ2_DBG_TIM6          DBGMCU_APB1LFZ2_DBG_TIM6_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM7_Pos      (5U)

+#define DBGMCU_APB1LFZ2_DBG_TIM7_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM7_Pos) /*!< 0x00000020 */

+#define DBGMCU_APB1LFZ2_DBG_TIM7          DBGMCU_APB1LFZ2_DBG_TIM7_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM12_Pos     (6U)

+#define DBGMCU_APB1LFZ2_DBG_TIM12_Msk     (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM12_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB1LFZ2_DBG_TIM12         DBGMCU_APB1LFZ2_DBG_TIM12_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM13_Pos     (7U)

+#define DBGMCU_APB1LFZ2_DBG_TIM13_Msk     (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM13_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB1LFZ2_DBG_TIM13         DBGMCU_APB1LFZ2_DBG_TIM13_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM14_Pos     (8U)

+#define DBGMCU_APB1LFZ2_DBG_TIM14_Msk     (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM14_Pos) /*!< 0x00000100 */

+#define DBGMCU_APB1LFZ2_DBG_TIM14         DBGMCU_APB1LFZ2_DBG_TIM14_Msk

+#define DBGMCU_APB1LFZ2_DBG_LPTIM1_Pos    (9U)

+#define DBGMCU_APB1LFZ2_DBG_LPTIM1_Msk    (0x1UL << DBGMCU_APB1LFZ2_DBG_LPTIM1_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB1LFZ2_DBG_LPTIM1        DBGMCU_APB1LFZ2_DBG_LPTIM1_Msk

+#define DBGMCU_APB1LFZ2_DBG_WWDG2_Pos     (11U)

+#define DBGMCU_APB1LFZ2_DBG_WWDG2_Msk     (0x1UL << DBGMCU_APB1LFZ2_DBG_WWDG2_Pos) /*!< 0x00000800 */

+#define DBGMCU_APB1LFZ2_DBG_WWDG2         DBGMCU_APB1LFZ2_DBG_WWDG2_Msk

+#define DBGMCU_APB1LFZ2_DBG_I2C1_Pos      (21U)

+#define DBGMCU_APB1LFZ2_DBG_I2C1_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C1_Pos) /*!< 0x00200000 */

+#define DBGMCU_APB1LFZ2_DBG_I2C1          DBGMCU_APB1LFZ2_DBG_I2C1_Msk

+#define DBGMCU_APB1LFZ2_DBG_I2C2_Pos      (22U)

+#define DBGMCU_APB1LFZ2_DBG_I2C2_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C2_Pos) /*!< 0x00400000 */

+#define DBGMCU_APB1LFZ2_DBG_I2C2          DBGMCU_APB1LFZ2_DBG_I2C2_Msk

+#define DBGMCU_APB1LFZ2_DBG_I2C3_Pos      (23U)

+#define DBGMCU_APB1LFZ2_DBG_I2C3_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C3_Pos) /*!< 0x00800000 */

+#define DBGMCU_APB1LFZ2_DBG_I2C3          DBGMCU_APB1LFZ2_DBG_I2C3_Msk

+/********************  Bit definition for APB1HFZ1 register  ************/

+#define DBGMCU_APB1HFZ1_DBG_FDCAN_Pos     (8U)

+#define DBGMCU_APB1HFZ1_DBG_FDCAN_Msk     (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_Pos) /*!< 0x00000100 */

+#define DBGMCU_APB1HFZ1_DBG_FDCAN         DBGMCU_APB1HFZ1_DBG_FDCAN_Msk

+/********************  Bit definition for APB1HFZ2 register  ************/

+#define DBGMCU_APB1HFZ2_DBG_FDCAN_Pos     (8U)

+#define DBGMCU_APB1HFZ2_DBG_FDCAN_Msk     (0x1UL << DBGMCU_APB1HFZ2_DBG_FDCAN_Pos) /*!< 0x00000100 */

+#define DBGMCU_APB1HFZ2_DBG_FDCAN         DBGMCU_APB1HFZ2_DBG_FDCAN_Msk

+

+/********************  Bit definition for APB2FZ1 register  ************/

+#define DBGMCU_APB2FZ1_DBG_TIM1_Pos       (0U)

+#define DBGMCU_APB2FZ1_DBG_TIM1_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB2FZ1_DBG_TIM1           DBGMCU_APB2FZ1_DBG_TIM1_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM8_Pos       (1U)

+#define DBGMCU_APB2FZ1_DBG_TIM8_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB2FZ1_DBG_TIM8           DBGMCU_APB2FZ1_DBG_TIM8_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM15_Pos      (16U)

+#define DBGMCU_APB2FZ1_DBG_TIM15_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB2FZ1_DBG_TIM15          DBGMCU_APB2FZ1_DBG_TIM15_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM16_Pos      (17U)

+#define DBGMCU_APB2FZ1_DBG_TIM16_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */

+#define DBGMCU_APB2FZ1_DBG_TIM16          DBGMCU_APB2FZ1_DBG_TIM16_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM17_Pos      (18U)

+#define DBGMCU_APB2FZ1_DBG_TIM17_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB2FZ1_DBG_TIM17          DBGMCU_APB2FZ1_DBG_TIM17_Msk

+#define DBGMCU_APB2FZ1_DBG_HRTIM_Pos      (29U)

+#define DBGMCU_APB2FZ1_DBG_HRTIM_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_HRTIM_Pos) /*!< 0x20000000 */

+#define DBGMCU_APB2FZ1_DBG_HRTIM          DBGMCU_APB2FZ1_DBG_HRTIM_Msk

+

+/********************  Bit definition for APB2FZ2 register  ************/

+#define DBGMCU_APB2FZ2_DBG_TIM1_Pos       (0U)

+#define DBGMCU_APB2FZ2_DBG_TIM1_Msk       (0x1UL << DBGMCU_APB2FZ2_DBG_TIM1_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB2FZ2_DBG_TIM1           DBGMCU_APB2FZ2_DBG_TIM1_Msk

+#define DBGMCU_APB2FZ2_DBG_TIM8_Pos       (1U)

+#define DBGMCU_APB2FZ2_DBG_TIM8_Msk       (0x1UL << DBGMCU_APB2FZ2_DBG_TIM8_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB2FZ2_DBG_TIM8           DBGMCU_APB2FZ2_DBG_TIM8_Msk

+#define DBGMCU_APB2FZ2_DBG_TIM15_Pos      (16U)

+#define DBGMCU_APB2FZ2_DBG_TIM15_Msk      (0x1UL << DBGMCU_APB2FZ2_DBG_TIM15_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB2FZ2_DBG_TIM15          DBGMCU_APB2FZ2_DBG_TIM15_Msk

+#define DBGMCU_APB2FZ2_DBG_TIM16_Pos      (17U)

+#define DBGMCU_APB2FZ2_DBG_TIM16_Msk      (0x1UL << DBGMCU_APB2FZ2_DBG_TIM16_Pos) /*!< 0x00020000 */

+#define DBGMCU_APB2FZ2_DBG_TIM16          DBGMCU_APB2FZ2_DBG_TIM16_Msk

+#define DBGMCU_APB2FZ2_DBG_TIM17_Pos      (18U)

+#define DBGMCU_APB2FZ2_DBG_TIM17_Msk      (0x1UL << DBGMCU_APB2FZ2_DBG_TIM17_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB2FZ2_DBG_TIM17          DBGMCU_APB2FZ2_DBG_TIM17_Msk

+#define DBGMCU_APB2FZ2_DBG_HRTIM_Pos      (29U)

+#define DBGMCU_APB2FZ2_DBG_HRTIM_Msk      (0x1UL << DBGMCU_APB2FZ2_DBG_HRTIM_Pos) /*!< 0x20000000 */

+#define DBGMCU_APB2FZ2_DBG_HRTIM          DBGMCU_APB2FZ2_DBG_HRTIM_Msk

+/********************  Bit definition for APB4FZ1 register  ************/

+#define DBGMCU_APB4FZ1_DBG_I2C4_Pos       (7U)

+#define DBGMCU_APB4FZ1_DBG_I2C4_Msk       (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB4FZ1_DBG_I2C4           DBGMCU_APB4FZ1_DBG_I2C4_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos     (9U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM2         DBGMCU_APB4FZ1_DBG_LPTIM2_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos     (10U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM3         DBGMCU_APB4FZ1_DBG_LPTIM3_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM4_Pos     (11U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM4_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos) /*!< 0x00000800 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM4         DBGMCU_APB4FZ1_DBG_LPTIM4_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM5_Pos     (12U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM5_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos) /*!< 0x00001000 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM5         DBGMCU_APB4FZ1_DBG_LPTIM5_Msk

+#define DBGMCU_APB4FZ1_DBG_RTC_Pos        (16U)

+#define DBGMCU_APB4FZ1_DBG_RTC_Msk        (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB4FZ1_DBG_RTC            DBGMCU_APB4FZ1_DBG_RTC_Msk

+#define DBGMCU_APB4FZ1_DBG_IWDG1_Pos      (18U)

+#define DBGMCU_APB4FZ1_DBG_IWDG1_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB4FZ1_DBG_IWDG1          DBGMCU_APB4FZ1_DBG_IWDG1_Msk

+#define DBGMCU_APB4FZ1_DBG_IWDG2_Pos      (19U)

+#define DBGMCU_APB4FZ1_DBG_IWDG2_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG2_Pos) /*!< 0x00080000 */

+#define DBGMCU_APB4FZ1_DBG_IWDG2          DBGMCU_APB4FZ1_DBG_IWDG2_Msk

+/********************  Bit definition for APB4FZ2 register  ************/

+#define DBGMCU_APB4FZ2_DBG_I2C4_Pos       (7U)

+#define DBGMCU_APB4FZ2_DBG_I2C4_Msk       (0x1UL << DBGMCU_APB4FZ2_DBG_I2C4_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB4FZ2_DBG_I2C4           DBGMCU_APB4FZ2_DBG_I2C4_Msk

+#define DBGMCU_APB4FZ2_DBG_LPTIM2_Pos     (9U)

+#define DBGMCU_APB4FZ2_DBG_LPTIM2_Msk     (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM2_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB4FZ2_DBG_LPTIM2         DBGMCU_APB4FZ2_DBG_LPTIM2_Msk

+#define DBGMCU_APB4FZ2_DBG_LPTIM3_Pos     (10U)

+#define DBGMCU_APB4FZ2_DBG_LPTIM3_Msk     (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM3_Pos) /*!< 0x00000400 */

+#define DBGMCU_APB4FZ2_DBG_LPTIM3         DBGMCU_APB4FZ2_DBG_LPTIM3_Msk

+#define DBGMCU_APB4FZ2_DBG_LPTIM4_Pos     (11U)

+#define DBGMCU_APB4FZ2_DBG_LPTIM4_Msk     (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM4_Pos) /*!< 0x00000800 */

+#define DBGMCU_APB4FZ2_DBG_LPTIM4         DBGMCU_APB4FZ2_DBG_LPTIM4_Msk

+#define DBGMCU_APB4FZ2_DBG_LPTIM5_Pos     (12U)

+#define DBGMCU_APB4FZ2_DBG_LPTIM5_Msk     (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM5_Pos) /*!< 0x00001000 */

+#define DBGMCU_APB4FZ2_DBG_LPTIM5         DBGMCU_APB4FZ2_DBG_LPTIM5_Msk

+#define DBGMCU_APB4FZ2_DBG_RTC_Pos        (16U)

+#define DBGMCU_APB4FZ2_DBG_RTC_Msk        (0x1UL << DBGMCU_APB4FZ2_DBG_RTC_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB4FZ2_DBG_RTC            DBGMCU_APB4FZ2_DBG_RTC_Msk

+#define DBGMCU_APB4FZ2_DBG_IWDG1_Pos      (18U)

+#define DBGMCU_APB4FZ2_DBG_IWDG1_Msk      (0x1UL << DBGMCU_APB4FZ2_DBG_IWDG1_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB4FZ2_DBG_IWDG1          DBGMCU_APB4FZ2_DBG_IWDG1_Msk

+#define DBGMCU_APB4FZ2_DBG_IWDG2_Pos      (19U)

+#define DBGMCU_APB4FZ2_DBG_IWDG2_Msk      (0x1UL << DBGMCU_APB4FZ2_DBG_IWDG2_Pos) /*!< 0x00080000 */

+#define DBGMCU_APB4FZ2_DBG_IWDG2          DBGMCU_APB4FZ2_DBG_IWDG2_Msk

+/******************************************************************************/

+/*                                                                            */

+/*                        High Resolution Timer (HRTIM)                       */

+/*                                                                            */

+/******************************************************************************/

+/******************** Master Timer control register ***************************/

+#define HRTIM_MCR_CK_PSC_Pos          (0U)

+#define HRTIM_MCR_CK_PSC_Msk          (0x7UL << HRTIM_MCR_CK_PSC_Pos)          /*!< 0x00000007 */

+#define HRTIM_MCR_CK_PSC              HRTIM_MCR_CK_PSC_Msk                     /*!< Prescaler mask */

+#define HRTIM_MCR_CK_PSC_0            (0x1UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000001 */

+#define HRTIM_MCR_CK_PSC_1            (0x2UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000002 */

+#define HRTIM_MCR_CK_PSC_2            (0x4UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000004 */

+

+#define HRTIM_MCR_CONT_Pos            (3U)

+#define HRTIM_MCR_CONT_Msk            (0x1UL << HRTIM_MCR_CONT_Pos)            /*!< 0x00000008 */

+#define HRTIM_MCR_CONT                HRTIM_MCR_CONT_Msk                       /*!< Continuous mode */

+#define HRTIM_MCR_RETRIG_Pos          (4U)

+#define HRTIM_MCR_RETRIG_Msk          (0x1UL << HRTIM_MCR_RETRIG_Pos)          /*!< 0x00000010 */

+#define HRTIM_MCR_RETRIG              HRTIM_MCR_RETRIG_Msk                     /*!< Rettrigreable mode */

+#define HRTIM_MCR_HALF_Pos            (5U)

+#define HRTIM_MCR_HALF_Msk            (0x1UL << HRTIM_MCR_HALF_Pos)            /*!< 0x00000020 */

+#define HRTIM_MCR_HALF                HRTIM_MCR_HALF_Msk                       /*!< Half mode */

+

+#define HRTIM_MCR_SYNC_IN_Pos         (8U)

+#define HRTIM_MCR_SYNC_IN_Msk         (0x3UL << HRTIM_MCR_SYNC_IN_Pos)         /*!< 0x00000300 */

+#define HRTIM_MCR_SYNC_IN             HRTIM_MCR_SYNC_IN_Msk                    /*!< Synchronization input master */

+#define HRTIM_MCR_SYNC_IN_0           (0x1UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000100 */

+#define HRTIM_MCR_SYNC_IN_1           (0x2UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000200 */

+#define HRTIM_MCR_SYNCRSTM_Pos        (10U)

+#define HRTIM_MCR_SYNCRSTM_Msk        (0x1UL << HRTIM_MCR_SYNCRSTM_Pos)        /*!< 0x00000400 */

+#define HRTIM_MCR_SYNCRSTM            HRTIM_MCR_SYNCRSTM_Msk                   /*!< Synchronization reset master */

+#define HRTIM_MCR_SYNCSTRTM_Pos       (11U)

+#define HRTIM_MCR_SYNCSTRTM_Msk       (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos)       /*!< 0x00000800 */

+#define HRTIM_MCR_SYNCSTRTM           HRTIM_MCR_SYNCSTRTM_Msk                  /*!< Synchronization start master */

+#define HRTIM_MCR_SYNC_OUT_Pos        (12U)

+#define HRTIM_MCR_SYNC_OUT_Msk        (0x3UL << HRTIM_MCR_SYNC_OUT_Pos)        /*!< 0x00003000 */

+#define HRTIM_MCR_SYNC_OUT            HRTIM_MCR_SYNC_OUT_Msk                   /*!< Synchronization output master */

+#define HRTIM_MCR_SYNC_OUT_0          (0x1UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00001000 */

+#define HRTIM_MCR_SYNC_OUT_1          (0x2UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00002000 */

+#define HRTIM_MCR_SYNC_SRC_Pos        (14U)

+#define HRTIM_MCR_SYNC_SRC_Msk        (0x3UL << HRTIM_MCR_SYNC_SRC_Pos)        /*!< 0x0000C000 */

+#define HRTIM_MCR_SYNC_SRC            HRTIM_MCR_SYNC_SRC_Msk                   /*!< Synchronization source */

+#define HRTIM_MCR_SYNC_SRC_0          (0x1UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00004000 */

+#define HRTIM_MCR_SYNC_SRC_1          (0x2UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00008000 */

+

+#define HRTIM_MCR_MCEN_Pos            (16U)

+#define HRTIM_MCR_MCEN_Msk            (0x1UL << HRTIM_MCR_MCEN_Pos)            /*!< 0x00010000 */

+#define HRTIM_MCR_MCEN                HRTIM_MCR_MCEN_Msk                       /*!< Master counter enable */

+#define HRTIM_MCR_TACEN_Pos           (17U)

+#define HRTIM_MCR_TACEN_Msk           (0x1UL << HRTIM_MCR_TACEN_Pos)           /*!< 0x00020000 */

+#define HRTIM_MCR_TACEN               HRTIM_MCR_TACEN_Msk                      /*!< Timer A counter enable */

+#define HRTIM_MCR_TBCEN_Pos           (18U)

+#define HRTIM_MCR_TBCEN_Msk           (0x1UL << HRTIM_MCR_TBCEN_Pos)           /*!< 0x00040000 */

+#define HRTIM_MCR_TBCEN               HRTIM_MCR_TBCEN_Msk                      /*!< Timer B counter enable */

+#define HRTIM_MCR_TCCEN_Pos           (19U)

+#define HRTIM_MCR_TCCEN_Msk           (0x1UL << HRTIM_MCR_TCCEN_Pos)           /*!< 0x00080000 */

+#define HRTIM_MCR_TCCEN               HRTIM_MCR_TCCEN_Msk                      /*!< Timer C counter enable */

+#define HRTIM_MCR_TDCEN_Pos           (20U)

+#define HRTIM_MCR_TDCEN_Msk           (0x1UL << HRTIM_MCR_TDCEN_Pos)           /*!< 0x00100000 */

+#define HRTIM_MCR_TDCEN               HRTIM_MCR_TDCEN_Msk                      /*!< Timer D counter enable */

+#define HRTIM_MCR_TECEN_Pos           (21U)

+#define HRTIM_MCR_TECEN_Msk           (0x1UL << HRTIM_MCR_TECEN_Pos)           /*!< 0x00200000 */

+#define HRTIM_MCR_TECEN               HRTIM_MCR_TECEN_Msk                      /*!< Timer E counter enable */

+

+#define HRTIM_MCR_DACSYNC_Pos         (25U)

+#define HRTIM_MCR_DACSYNC_Msk         (0x3UL << HRTIM_MCR_DACSYNC_Pos)         /*!< 0x06000000 */

+#define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC sychronization mask */

+#define HRTIM_MCR_DACSYNC_0           (0x1UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x02000000 */

+#define HRTIM_MCR_DACSYNC_1           (0x2UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x04000000 */

+

+#define HRTIM_MCR_PREEN_Pos           (27U)

+#define HRTIM_MCR_PREEN_Msk           (0x1UL << HRTIM_MCR_PREEN_Pos)           /*!< 0x08000000 */

+#define HRTIM_MCR_PREEN               HRTIM_MCR_PREEN_Msk                      /*!< Master preload enable */

+#define HRTIM_MCR_MREPU_Pos           (29U)

+#define HRTIM_MCR_MREPU_Msk           (0x1UL << HRTIM_MCR_MREPU_Pos)           /*!< 0x20000000 */

+#define HRTIM_MCR_MREPU               HRTIM_MCR_MREPU_Msk                      /*!< Master repetition update */

+

+#define HRTIM_MCR_BRSTDMA_Pos         (30U)

+#define HRTIM_MCR_BRSTDMA_Msk         (0x3UL << HRTIM_MCR_BRSTDMA_Pos)         /*!< 0xC0000000 */

+#define HRTIM_MCR_BRSTDMA             HRTIM_MCR_BRSTDMA_Msk                    /*!< Burst DMA update */

+#define HRTIM_MCR_BRSTDMA_0           (0x1UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x40000000 */

+#define HRTIM_MCR_BRSTDMA_1           (0x2UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x80000000 */

+

+/******************** Master Timer Interrupt status register ******************/

+#define HRTIM_MISR_MCMP1_Pos          (0U)

+#define HRTIM_MISR_MCMP1_Msk          (0x1UL << HRTIM_MISR_MCMP1_Pos)          /*!< 0x00000001 */

+#define HRTIM_MISR_MCMP1              HRTIM_MISR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag */

+#define HRTIM_MISR_MCMP2_Pos          (1U)

+#define HRTIM_MISR_MCMP2_Msk          (0x1UL << HRTIM_MISR_MCMP2_Pos)          /*!< 0x00000002 */

+#define HRTIM_MISR_MCMP2              HRTIM_MISR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag */

+#define HRTIM_MISR_MCMP3_Pos          (2U)

+#define HRTIM_MISR_MCMP3_Msk          (0x1UL << HRTIM_MISR_MCMP3_Pos)          /*!< 0x00000004 */

+#define HRTIM_MISR_MCMP3              HRTIM_MISR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag */

+#define HRTIM_MISR_MCMP4_Pos          (3U)

+#define HRTIM_MISR_MCMP4_Msk          (0x1UL << HRTIM_MISR_MCMP4_Pos)          /*!< 0x00000008 */

+#define HRTIM_MISR_MCMP4              HRTIM_MISR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag */

+#define HRTIM_MISR_MREP_Pos           (4U)

+#define HRTIM_MISR_MREP_Msk           (0x1UL << HRTIM_MISR_MREP_Pos)           /*!< 0x00000010 */

+#define HRTIM_MISR_MREP               HRTIM_MISR_MREP_Msk                      /*!< Master Repetition interrupt flag */

+#define HRTIM_MISR_SYNC_Pos           (5U)

+#define HRTIM_MISR_SYNC_Msk           (0x1UL << HRTIM_MISR_SYNC_Pos)           /*!< 0x00000020 */

+#define HRTIM_MISR_SYNC               HRTIM_MISR_SYNC_Msk                      /*!< Synchronization input interrupt flag */

+#define HRTIM_MISR_MUPD_Pos           (6U)

+#define HRTIM_MISR_MUPD_Msk           (0x1UL << HRTIM_MISR_MUPD_Pos)           /*!< 0x00000040 */

+#define HRTIM_MISR_MUPD               HRTIM_MISR_MUPD_Msk                      /*!< Master update interrupt flag */

+

+/******************** Master Timer Interrupt clear register *******************/

+#define HRTIM_MICR_MCMP1_Pos          (0U)

+#define HRTIM_MICR_MCMP1_Msk          (0x1UL << HRTIM_MICR_MCMP1_Pos)          /*!< 0x00000001 */

+#define HRTIM_MICR_MCMP1              HRTIM_MICR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag clear */

+#define HRTIM_MICR_MCMP2_Pos          (1U)

+#define HRTIM_MICR_MCMP2_Msk          (0x1UL << HRTIM_MICR_MCMP2_Pos)          /*!< 0x00000002 */

+#define HRTIM_MICR_MCMP2              HRTIM_MICR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag clear */

+#define HRTIM_MICR_MCMP3_Pos          (2U)

+#define HRTIM_MICR_MCMP3_Msk          (0x1UL << HRTIM_MICR_MCMP3_Pos)          /*!< 0x00000004 */

+#define HRTIM_MICR_MCMP3              HRTIM_MICR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag clear */

+#define HRTIM_MICR_MCMP4_Pos          (3U)

+#define HRTIM_MICR_MCMP4_Msk          (0x1UL << HRTIM_MICR_MCMP4_Pos)          /*!< 0x00000008 */

+#define HRTIM_MICR_MCMP4              HRTIM_MICR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag clear */

+#define HRTIM_MICR_MREP_Pos           (4U)

+#define HRTIM_MICR_MREP_Msk           (0x1UL << HRTIM_MICR_MREP_Pos)           /*!< 0x00000010 */

+#define HRTIM_MICR_MREP               HRTIM_MICR_MREP_Msk                      /*!< Master Repetition interrupt flag clear */

+#define HRTIM_MICR_SYNC_Pos           (5U)

+#define HRTIM_MICR_SYNC_Msk           (0x1UL << HRTIM_MICR_SYNC_Pos)           /*!< 0x00000020 */

+#define HRTIM_MICR_SYNC               HRTIM_MICR_SYNC_Msk                      /*!< Synchronization input interrupt flag clear */

+#define HRTIM_MICR_MUPD_Pos           (6U)

+#define HRTIM_MICR_MUPD_Msk           (0x1UL << HRTIM_MICR_MUPD_Pos)           /*!< 0x00000040 */

+#define HRTIM_MICR_MUPD               HRTIM_MICR_MUPD_Msk                      /*!< Master update interrupt flag clear */

+

+/******************** Master Timer DMA/Interrupt enable register **************/

+#define HRTIM_MDIER_MCMP1IE_Pos       (0U)

+#define HRTIM_MDIER_MCMP1IE_Msk       (0x1UL << HRTIM_MDIER_MCMP1IE_Pos)       /*!< 0x00000001 */

+#define HRTIM_MDIER_MCMP1IE           HRTIM_MDIER_MCMP1IE_Msk                  /*!< Master compare 1 interrupt enable */

+#define HRTIM_MDIER_MCMP2IE_Pos       (1U)

+#define HRTIM_MDIER_MCMP2IE_Msk       (0x1UL << HRTIM_MDIER_MCMP2IE_Pos)       /*!< 0x00000002 */

+#define HRTIM_MDIER_MCMP2IE           HRTIM_MDIER_MCMP2IE_Msk                  /*!< Master compare 2 interrupt enable */

+#define HRTIM_MDIER_MCMP3IE_Pos       (2U)

+#define HRTIM_MDIER_MCMP3IE_Msk       (0x1UL << HRTIM_MDIER_MCMP3IE_Pos)       /*!< 0x00000004 */

+#define HRTIM_MDIER_MCMP3IE           HRTIM_MDIER_MCMP3IE_Msk                  /*!< Master compare 3 interrupt enable */

+#define HRTIM_MDIER_MCMP4IE_Pos       (3U)

+#define HRTIM_MDIER_MCMP4IE_Msk       (0x1UL << HRTIM_MDIER_MCMP4IE_Pos)       /*!< 0x00000008 */

+#define HRTIM_MDIER_MCMP4IE           HRTIM_MDIER_MCMP4IE_Msk                  /*!< Master compare 4 interrupt enable */

+#define HRTIM_MDIER_MREPIE_Pos        (4U)

+#define HRTIM_MDIER_MREPIE_Msk        (0x1UL << HRTIM_MDIER_MREPIE_Pos)        /*!< 0x00000010 */

+#define HRTIM_MDIER_MREPIE            HRTIM_MDIER_MREPIE_Msk                   /*!< Master Repetition interrupt enable */

+#define HRTIM_MDIER_SYNCIE_Pos        (5U)

+#define HRTIM_MDIER_SYNCIE_Msk        (0x1UL << HRTIM_MDIER_SYNCIE_Pos)        /*!< 0x00000020 */

+#define HRTIM_MDIER_SYNCIE            HRTIM_MDIER_SYNCIE_Msk                   /*!< Synchronization input interrupt enable */

+#define HRTIM_MDIER_MUPDIE_Pos        (6U)

+#define HRTIM_MDIER_MUPDIE_Msk        (0x1UL << HRTIM_MDIER_MUPDIE_Pos)        /*!< 0x00000040 */

+#define HRTIM_MDIER_MUPDIE            HRTIM_MDIER_MUPDIE_Msk                   /*!< Master update interrupt enable */

+

+#define HRTIM_MDIER_MCMP1DE_Pos       (16U)

+#define HRTIM_MDIER_MCMP1DE_Msk       (0x1UL << HRTIM_MDIER_MCMP1DE_Pos)       /*!< 0x00010000 */

+#define HRTIM_MDIER_MCMP1DE           HRTIM_MDIER_MCMP1DE_Msk                  /*!< Master compare 1 DMA enable */

+#define HRTIM_MDIER_MCMP2DE_Pos       (17U)

+#define HRTIM_MDIER_MCMP2DE_Msk       (0x1UL << HRTIM_MDIER_MCMP2DE_Pos)       /*!< 0x00020000 */

+#define HRTIM_MDIER_MCMP2DE           HRTIM_MDIER_MCMP2DE_Msk                  /*!< Master compare 2 DMA enable */

+#define HRTIM_MDIER_MCMP3DE_Pos       (18U)

+#define HRTIM_MDIER_MCMP3DE_Msk       (0x1UL << HRTIM_MDIER_MCMP3DE_Pos)       /*!< 0x00040000 */

+#define HRTIM_MDIER_MCMP3DE           HRTIM_MDIER_MCMP3DE_Msk                  /*!< Master compare 3 DMA enable */

+#define HRTIM_MDIER_MCMP4DE_Pos       (19U)

+#define HRTIM_MDIER_MCMP4DE_Msk       (0x1UL << HRTIM_MDIER_MCMP4DE_Pos)       /*!< 0x00080000 */

+#define HRTIM_MDIER_MCMP4DE           HRTIM_MDIER_MCMP4DE_Msk                  /*!< Master compare 4 DMA enable */

+#define HRTIM_MDIER_MREPDE_Pos        (20U)

+#define HRTIM_MDIER_MREPDE_Msk        (0x1UL << HRTIM_MDIER_MREPDE_Pos)        /*!< 0x00100000 */

+#define HRTIM_MDIER_MREPDE            HRTIM_MDIER_MREPDE_Msk                   /*!< Master Repetition DMA enable */

+#define HRTIM_MDIER_SYNCDE_Pos        (21U)

+#define HRTIM_MDIER_SYNCDE_Msk        (0x1UL << HRTIM_MDIER_SYNCDE_Pos)        /*!< 0x00200000 */

+#define HRTIM_MDIER_SYNCDE            HRTIM_MDIER_SYNCDE_Msk                   /*!< Synchronization input DMA enable */

+#define HRTIM_MDIER_MUPDDE_Pos        (22U)

+#define HRTIM_MDIER_MUPDDE_Msk        (0x1UL << HRTIM_MDIER_MUPDDE_Pos)        /*!< 0x00400000 */

+#define HRTIM_MDIER_MUPDDE            HRTIM_MDIER_MUPDDE_Msk                   /*!< Master update DMA enable */

+

+/*******************  Bit definition for HRTIM_MCNTR register  ****************/

+#define HRTIM_MCNTR_MCNTR_Pos         (0U)

+#define HRTIM_MCNTR_MCNTR_Msk         (0xFFFFUL << HRTIM_MCNTR_MCNTR_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_MCNTR_MCNTR             HRTIM_MCNTR_MCNTR_Msk                    /*!<Counter Value */

+

+/*******************  Bit definition for HRTIM_MPER register  *****************/

+#define HRTIM_MPER_MPER_Pos           (0U)

+#define HRTIM_MPER_MPER_Msk           (0xFFFFUL << HRTIM_MPER_MPER_Pos)        /*!< 0x0000FFFF */

+#define HRTIM_MPER_MPER               HRTIM_MPER_MPER_Msk                      /*!< Period Value */

+

+/*******************  Bit definition for HRTIM_MREP register  *****************/

+#define HRTIM_MREP_MREP_Pos           (0U)

+#define HRTIM_MREP_MREP_Msk           (0xFFUL << HRTIM_MREP_MREP_Pos)          /*!< 0x000000FF */

+#define HRTIM_MREP_MREP               HRTIM_MREP_MREP_Msk                      /*!<Repetition Value */

+

+/*******************  Bit definition for HRTIM_MCMP1R register  *****************/

+#define HRTIM_MCMP1R_MCMP1R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP1R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP1R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP1R           HRTIM_MCMP1R_MCMP1R_Msk                  /*!<Compare Value */

+

+/*******************  Bit definition for HRTIM_MCMP2R register  *****************/

+#define HRTIM_MCMP1R_MCMP2R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP2R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP2R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP2R           HRTIM_MCMP1R_MCMP2R_Msk                  /*!<Compare Value */

+

+/*******************  Bit definition for HRTIM_MCMP3R register  *****************/

+#define HRTIM_MCMP1R_MCMP3R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP3R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP3R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP3R           HRTIM_MCMP1R_MCMP3R_Msk                  /*!<Compare Value */

+

+/*******************  Bit definition for HRTIM_MCMP4R register  *****************/

+#define HRTIM_MCMP1R_MCMP4R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP4R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP4R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP4R           HRTIM_MCMP1R_MCMP4R_Msk                  /*!<Compare Value */

+

+/******************** Slave control register **********************************/

+#define HRTIM_TIMCR_CK_PSC_Pos        (0U)

+#define HRTIM_TIMCR_CK_PSC_Msk        (0x7UL << HRTIM_TIMCR_CK_PSC_Pos)        /*!< 0x00000007 */

+#define HRTIM_TIMCR_CK_PSC            HRTIM_TIMCR_CK_PSC_Msk                   /*!< Slave prescaler mask*/

+#define HRTIM_TIMCR_CK_PSC_0          (0x1UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000001 */

+#define HRTIM_TIMCR_CK_PSC_1          (0x2UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000002 */

+#define HRTIM_TIMCR_CK_PSC_2          (0x4UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000004 */

+

+#define HRTIM_TIMCR_CONT_Pos          (3U)

+#define HRTIM_TIMCR_CONT_Msk          (0x1UL << HRTIM_TIMCR_CONT_Pos)          /*!< 0x00000008 */

+#define HRTIM_TIMCR_CONT              HRTIM_TIMCR_CONT_Msk                     /*!< Slave continuous mode */

+#define HRTIM_TIMCR_RETRIG_Pos        (4U)

+#define HRTIM_TIMCR_RETRIG_Msk        (0x1UL << HRTIM_TIMCR_RETRIG_Pos)        /*!< 0x00000010 */

+#define HRTIM_TIMCR_RETRIG            HRTIM_TIMCR_RETRIG_Msk                   /*!< Slave Retrigreable mode */

+#define HRTIM_TIMCR_HALF_Pos          (5U)

+#define HRTIM_TIMCR_HALF_Msk          (0x1UL << HRTIM_TIMCR_HALF_Pos)          /*!< 0x00000020 */

+#define HRTIM_TIMCR_HALF              HRTIM_TIMCR_HALF_Msk                     /*!< Slave Half mode */

+#define HRTIM_TIMCR_PSHPLL_Pos        (6U)

+#define HRTIM_TIMCR_PSHPLL_Msk        (0x1UL << HRTIM_TIMCR_PSHPLL_Pos)        /*!< 0x00000040 */

+#define HRTIM_TIMCR_PSHPLL            HRTIM_TIMCR_PSHPLL_Msk                   /*!< Slave push-pull mode */

+

+#define HRTIM_TIMCR_SYNCRST_Pos       (10U)

+#define HRTIM_TIMCR_SYNCRST_Msk       (0x1UL << HRTIM_TIMCR_SYNCRST_Pos)       /*!< 0x00000400 */

+#define HRTIM_TIMCR_SYNCRST           HRTIM_TIMCR_SYNCRST_Msk                  /*!< Slave synchronization resets */

+#define HRTIM_TIMCR_SYNCSTRT_Pos      (11U)

+#define HRTIM_TIMCR_SYNCSTRT_Msk      (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos)      /*!< 0x00000800 */

+#define HRTIM_TIMCR_SYNCSTRT          HRTIM_TIMCR_SYNCSTRT_Msk                 /*!< Slave synchronization starts */

+

+#define HRTIM_TIMCR_DELCMP2_Pos       (12U)

+#define HRTIM_TIMCR_DELCMP2_Msk       (0x3UL << HRTIM_TIMCR_DELCMP2_Pos)       /*!< 0x00003000 */

+#define HRTIM_TIMCR_DELCMP2           HRTIM_TIMCR_DELCMP2_Msk                  /*!< Slave delayed compartor 2 mode mask */

+#define HRTIM_TIMCR_DELCMP2_0         (0x1UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00001000 */

+#define HRTIM_TIMCR_DELCMP2_1         (0x2UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00002000 */

+#define HRTIM_TIMCR_DELCMP4_Pos       (14U)

+#define HRTIM_TIMCR_DELCMP4_Msk       (0x3UL << HRTIM_TIMCR_DELCMP4_Pos)       /*!< 0x0000C000 */

+#define HRTIM_TIMCR_DELCMP4           HRTIM_TIMCR_DELCMP4_Msk                  /*!< Slave delayed compartor 4 mode mask */

+#define HRTIM_TIMCR_DELCMP4_0         (0x1UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00004000 */

+#define HRTIM_TIMCR_DELCMP4_1         (0x2UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00008000 */

+

+#define HRTIM_TIMCR_TREPU_Pos         (17U)

+#define HRTIM_TIMCR_TREPU_Msk         (0x1UL << HRTIM_TIMCR_TREPU_Pos)         /*!< 0x00020000 */

+#define HRTIM_TIMCR_TREPU             HRTIM_TIMCR_TREPU_Msk                    /*!< Slave repetition update */

+#define HRTIM_TIMCR_TRSTU_Pos         (18U)

+#define HRTIM_TIMCR_TRSTU_Msk         (0x1UL << HRTIM_TIMCR_TRSTU_Pos)         /*!< 0x00040000 */

+#define HRTIM_TIMCR_TRSTU             HRTIM_TIMCR_TRSTU_Msk                    /*!< Slave reset update */

+#define HRTIM_TIMCR_TAU_Pos           (19U)

+#define HRTIM_TIMCR_TAU_Msk           (0x1UL << HRTIM_TIMCR_TAU_Pos)           /*!< 0x00080000 */

+#define HRTIM_TIMCR_TAU               HRTIM_TIMCR_TAU_Msk                      /*!< Slave Timer A update reserved for TIM A */

+#define HRTIM_TIMCR_TBU_Pos           (20U)

+#define HRTIM_TIMCR_TBU_Msk           (0x1UL << HRTIM_TIMCR_TBU_Pos)           /*!< 0x00100000 */

+#define HRTIM_TIMCR_TBU               HRTIM_TIMCR_TBU_Msk                      /*!< Slave Timer B update reserved for TIM B */

+#define HRTIM_TIMCR_TCU_Pos           (21U)

+#define HRTIM_TIMCR_TCU_Msk           (0x1UL << HRTIM_TIMCR_TCU_Pos)           /*!< 0x00200000 */

+#define HRTIM_TIMCR_TCU               HRTIM_TIMCR_TCU_Msk                      /*!< Slave Timer C update reserved for TIM C */

+#define HRTIM_TIMCR_TDU_Pos           (22U)

+#define HRTIM_TIMCR_TDU_Msk           (0x1UL << HRTIM_TIMCR_TDU_Pos)           /*!< 0x00400000 */

+#define HRTIM_TIMCR_TDU               HRTIM_TIMCR_TDU_Msk                      /*!< Slave Timer D update reserved for TIM D */

+#define HRTIM_TIMCR_TEU_Pos           (23U)

+#define HRTIM_TIMCR_TEU_Msk           (0x1UL << HRTIM_TIMCR_TEU_Pos)           /*!< 0x00800000 */

+#define HRTIM_TIMCR_TEU               HRTIM_TIMCR_TEU_Msk                      /*!< Slave Timer E update reserved for TIM E */

+#define HRTIM_TIMCR_MSTU_Pos          (24U)

+#define HRTIM_TIMCR_MSTU_Msk          (0x1UL << HRTIM_TIMCR_MSTU_Pos)          /*!< 0x01000000 */

+#define HRTIM_TIMCR_MSTU              HRTIM_TIMCR_MSTU_Msk                     /*!< Master Update */

+

+#define HRTIM_TIMCR_DACSYNC_Pos       (25U)

+#define HRTIM_TIMCR_DACSYNC_Msk       (0x3UL << HRTIM_TIMCR_DACSYNC_Pos)       /*!< 0x06000000 */

+#define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC sychronization mask */

+#define HRTIM_TIMCR_DACSYNC_0         (0x1UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x02000000 */

+#define HRTIM_TIMCR_DACSYNC_1         (0x2UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x04000000 */

+#define HRTIM_TIMCR_PREEN_Pos         (27U)

+#define HRTIM_TIMCR_PREEN_Msk         (0x1UL << HRTIM_TIMCR_PREEN_Pos)         /*!< 0x08000000 */

+#define HRTIM_TIMCR_PREEN             HRTIM_TIMCR_PREEN_Msk                    /*!< Slave preload enable */

+

+#define HRTIM_TIMCR_UPDGAT_Pos        (28U)

+#define HRTIM_TIMCR_UPDGAT_Msk        (0xFUL << HRTIM_TIMCR_UPDGAT_Pos)        /*!< 0xF0000000 */

+#define HRTIM_TIMCR_UPDGAT            HRTIM_TIMCR_UPDGAT_Msk                   /*!< Slave update gating mask */

+#define HRTIM_TIMCR_UPDGAT_0          (0x1UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x10000000 */

+#define HRTIM_TIMCR_UPDGAT_1          (0x2UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x20000000 */

+#define HRTIM_TIMCR_UPDGAT_2          (0x4UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x40000000 */

+#define HRTIM_TIMCR_UPDGAT_3          (0x8UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x80000000 */

+

+/******************** Slave Interrupt status register **************************/

+#define HRTIM_TIMISR_CMP1_Pos         (0U)

+#define HRTIM_TIMISR_CMP1_Msk         (0x1UL << HRTIM_TIMISR_CMP1_Pos)         /*!< 0x00000001 */

+#define HRTIM_TIMISR_CMP1             HRTIM_TIMISR_CMP1_Msk                    /*!< Slave compare 1 interrupt flag */

+#define HRTIM_TIMISR_CMP2_Pos         (1U)

+#define HRTIM_TIMISR_CMP2_Msk         (0x1UL << HRTIM_TIMISR_CMP2_Pos)         /*!< 0x00000002 */

+#define HRTIM_TIMISR_CMP2             HRTIM_TIMISR_CMP2_Msk                    /*!< Slave compare 2 interrupt flag */

+#define HRTIM_TIMISR_CMP3_Pos         (2U)

+#define HRTIM_TIMISR_CMP3_Msk         (0x1UL << HRTIM_TIMISR_CMP3_Pos)         /*!< 0x00000004 */

+#define HRTIM_TIMISR_CMP3             HRTIM_TIMISR_CMP3_Msk                    /*!< Slave compare 3 interrupt flag */

+#define HRTIM_TIMISR_CMP4_Pos         (3U)

+#define HRTIM_TIMISR_CMP4_Msk         (0x1UL << HRTIM_TIMISR_CMP4_Pos)         /*!< 0x00000008 */

+#define HRTIM_TIMISR_CMP4             HRTIM_TIMISR_CMP4_Msk                    /*!< Slave compare 4 interrupt flag */

+#define HRTIM_TIMISR_REP_Pos          (4U)

+#define HRTIM_TIMISR_REP_Msk          (0x1UL << HRTIM_TIMISR_REP_Pos)          /*!< 0x00000010 */

+#define HRTIM_TIMISR_REP              HRTIM_TIMISR_REP_Msk                     /*!< Slave repetition interrupt flag */

+#define HRTIM_TIMISR_UPD_Pos          (6U)

+#define HRTIM_TIMISR_UPD_Msk          (0x1UL << HRTIM_TIMISR_UPD_Pos)          /*!< 0x00000040 */

+#define HRTIM_TIMISR_UPD              HRTIM_TIMISR_UPD_Msk                     /*!< Slave update interrupt flag */

+#define HRTIM_TIMISR_CPT1_Pos         (7U)

+#define HRTIM_TIMISR_CPT1_Msk         (0x1UL << HRTIM_TIMISR_CPT1_Pos)         /*!< 0x00000080 */

+#define HRTIM_TIMISR_CPT1             HRTIM_TIMISR_CPT1_Msk                    /*!< Slave capture 1 interrupt flag */

+#define HRTIM_TIMISR_CPT2_Pos         (8U)

+#define HRTIM_TIMISR_CPT2_Msk         (0x1UL << HRTIM_TIMISR_CPT2_Pos)         /*!< 0x00000100 */

+#define HRTIM_TIMISR_CPT2             HRTIM_TIMISR_CPT2_Msk                    /*!< Slave capture 2 interrupt flag */

+#define HRTIM_TIMISR_SET1_Pos         (9U)

+#define HRTIM_TIMISR_SET1_Msk         (0x1UL << HRTIM_TIMISR_SET1_Pos)         /*!< 0x00000200 */

+#define HRTIM_TIMISR_SET1             HRTIM_TIMISR_SET1_Msk                    /*!< Slave output 1 set interrupt flag */

+#define HRTIM_TIMISR_RST1_Pos         (10U)

+#define HRTIM_TIMISR_RST1_Msk         (0x1UL << HRTIM_TIMISR_RST1_Pos)         /*!< 0x00000400 */

+#define HRTIM_TIMISR_RST1             HRTIM_TIMISR_RST1_Msk                    /*!< Slave output 1 reset interrupt flag */

+#define HRTIM_TIMISR_SET2_Pos         (11U)

+#define HRTIM_TIMISR_SET2_Msk         (0x1UL << HRTIM_TIMISR_SET2_Pos)         /*!< 0x00000800 */

+#define HRTIM_TIMISR_SET2             HRTIM_TIMISR_SET2_Msk                    /*!< Slave output 2 set interrupt flag */

+#define HRTIM_TIMISR_RST2_Pos         (12U)

+#define HRTIM_TIMISR_RST2_Msk         (0x1UL << HRTIM_TIMISR_RST2_Pos)         /*!< 0x00001000 */

+#define HRTIM_TIMISR_RST2             HRTIM_TIMISR_RST2_Msk                    /*!< Slave output 2 reset interrupt flag */

+#define HRTIM_TIMISR_RST_Pos          (13U)

+#define HRTIM_TIMISR_RST_Msk          (0x1UL << HRTIM_TIMISR_RST_Pos)          /*!< 0x00002000 */

+#define HRTIM_TIMISR_RST              HRTIM_TIMISR_RST_Msk                     /*!< Slave reset interrupt flag */

+#define HRTIM_TIMISR_DLYPRT_Pos       (14U)

+#define HRTIM_TIMISR_DLYPRT_Msk       (0x1UL << HRTIM_TIMISR_DLYPRT_Pos)       /*!< 0x00004000 */

+#define HRTIM_TIMISR_DLYPRT           HRTIM_TIMISR_DLYPRT_Msk                  /*!< Slave output 1 delay protection interrupt flag */

+#define HRTIM_TIMISR_CPPSTAT_Pos      (16U)

+#define HRTIM_TIMISR_CPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos)      /*!< 0x00010000 */

+#define HRTIM_TIMISR_CPPSTAT          HRTIM_TIMISR_CPPSTAT_Msk                 /*!< Slave current push-pull flag */

+#define HRTIM_TIMISR_IPPSTAT_Pos      (17U)

+#define HRTIM_TIMISR_IPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos)      /*!< 0x00020000 */

+#define HRTIM_TIMISR_IPPSTAT          HRTIM_TIMISR_IPPSTAT_Msk                 /*!< Slave idle push-pull flag */

+#define HRTIM_TIMISR_O1STAT_Pos       (18U)

+#define HRTIM_TIMISR_O1STAT_Msk       (0x1UL << HRTIM_TIMISR_O1STAT_Pos)       /*!< 0x00040000 */

+#define HRTIM_TIMISR_O1STAT           HRTIM_TIMISR_O1STAT_Msk                  /*!< Slave output 1 state flag */

+#define HRTIM_TIMISR_O2STAT_Pos       (19U)

+#define HRTIM_TIMISR_O2STAT_Msk       (0x1UL << HRTIM_TIMISR_O2STAT_Pos)       /*!< 0x00080000 */

+#define HRTIM_TIMISR_O2STAT           HRTIM_TIMISR_O2STAT_Msk                  /*!< Slave output 2 state flag */

+#define HRTIM_TIMISR_O1CPY_Pos        (20U)

+#define HRTIM_TIMISR_O1CPY_Msk        (0x1UL << HRTIM_TIMISR_O1CPY_Pos)        /*!< 0x00100000 */

+#define HRTIM_TIMISR_O1CPY            HRTIM_TIMISR_O1CPY_Msk                   /*!< Slave output 1 copy flag */

+#define HRTIM_TIMISR_O2CPY_Pos        (21U)

+#define HRTIM_TIMISR_O2CPY_Msk        (0x1UL << HRTIM_TIMISR_O2CPY_Pos)        /*!< 0x00200000 */

+#define HRTIM_TIMISR_O2CPY            HRTIM_TIMISR_O2CPY_Msk                   /*!< Slave output 2 copy flag */

+

+/******************** Slave Interrupt clear register **************************/

+#define HRTIM_TIMICR_CMP1C_Pos        (0U)

+#define HRTIM_TIMICR_CMP1C_Msk        (0x1UL << HRTIM_TIMICR_CMP1C_Pos)        /*!< 0x00000001 */

+#define HRTIM_TIMICR_CMP1C            HRTIM_TIMICR_CMP1C_Msk                   /*!< Slave compare 1 clear flag */

+#define HRTIM_TIMICR_CMP2C_Pos        (1U)

+#define HRTIM_TIMICR_CMP2C_Msk        (0x1UL << HRTIM_TIMICR_CMP2C_Pos)        /*!< 0x00000002 */

+#define HRTIM_TIMICR_CMP2C            HRTIM_TIMICR_CMP2C_Msk                   /*!< Slave compare 2 clear flag */

+#define HRTIM_TIMICR_CMP3C_Pos        (2U)

+#define HRTIM_TIMICR_CMP3C_Msk        (0x1UL << HRTIM_TIMICR_CMP3C_Pos)        /*!< 0x00000004 */

+#define HRTIM_TIMICR_CMP3C            HRTIM_TIMICR_CMP3C_Msk                   /*!< Slave compare 3 clear flag */

+#define HRTIM_TIMICR_CMP4C_Pos        (3U)

+#define HRTIM_TIMICR_CMP4C_Msk        (0x1UL << HRTIM_TIMICR_CMP4C_Pos)        /*!< 0x00000008 */

+#define HRTIM_TIMICR_CMP4C            HRTIM_TIMICR_CMP4C_Msk                   /*!< Slave compare 4 clear flag */

+#define HRTIM_TIMICR_REPC_Pos         (4U)

+#define HRTIM_TIMICR_REPC_Msk         (0x1UL << HRTIM_TIMICR_REPC_Pos)         /*!< 0x00000010 */

+#define HRTIM_TIMICR_REPC             HRTIM_TIMICR_REPC_Msk                    /*!< Slave repetition clear flag */

+#define HRTIM_TIMICR_UPDC_Pos         (6U)

+#define HRTIM_TIMICR_UPDC_Msk         (0x1UL << HRTIM_TIMICR_UPDC_Pos)         /*!< 0x00000040 */

+#define HRTIM_TIMICR_UPDC             HRTIM_TIMICR_UPDC_Msk                    /*!< Slave update clear flag */

+#define HRTIM_TIMICR_CPT1C_Pos        (7U)

+#define HRTIM_TIMICR_CPT1C_Msk        (0x1UL << HRTIM_TIMICR_CPT1C_Pos)        /*!< 0x00000080 */

+#define HRTIM_TIMICR_CPT1C            HRTIM_TIMICR_CPT1C_Msk                   /*!< Slave capture 1 clear flag */

+#define HRTIM_TIMICR_CPT2C_Pos        (8U)

+#define HRTIM_TIMICR_CPT2C_Msk        (0x1UL << HRTIM_TIMICR_CPT2C_Pos)        /*!< 0x00000100 */

+#define HRTIM_TIMICR_CPT2C            HRTIM_TIMICR_CPT2C_Msk                   /*!< Slave capture 2 clear flag */

+#define HRTIM_TIMICR_SET1C_Pos        (9U)

+#define HRTIM_TIMICR_SET1C_Msk        (0x1UL << HRTIM_TIMICR_SET1C_Pos)        /*!< 0x00000200 */

+#define HRTIM_TIMICR_SET1C            HRTIM_TIMICR_SET1C_Msk                   /*!< Slave output 1 set clear flag */

+#define HRTIM_TIMICR_RST1C_Pos        (10U)

+#define HRTIM_TIMICR_RST1C_Msk        (0x1UL << HRTIM_TIMICR_RST1C_Pos)        /*!< 0x00000400 */

+#define HRTIM_TIMICR_RST1C            HRTIM_TIMICR_RST1C_Msk                   /*!< Slave output 1 reset clear flag */

+#define HRTIM_TIMICR_SET2C_Pos        (11U)

+#define HRTIM_TIMICR_SET2C_Msk        (0x1UL << HRTIM_TIMICR_SET2C_Pos)        /*!< 0x00000800 */

+#define HRTIM_TIMICR_SET2C            HRTIM_TIMICR_SET2C_Msk                   /*!< Slave output 2 set clear flag */

+#define HRTIM_TIMICR_RST2C_Pos        (12U)

+#define HRTIM_TIMICR_RST2C_Msk        (0x1UL << HRTIM_TIMICR_RST2C_Pos)        /*!< 0x00001000 */

+#define HRTIM_TIMICR_RST2C            HRTIM_TIMICR_RST2C_Msk                   /*!< Slave output 2 reset clear flag */

+#define HRTIM_TIMICR_RSTC_Pos         (13U)

+#define HRTIM_TIMICR_RSTC_Msk         (0x1UL << HRTIM_TIMICR_RSTC_Pos)         /*!< 0x00002000 */

+#define HRTIM_TIMICR_RSTC             HRTIM_TIMICR_RSTC_Msk                    /*!< Slave reset clear flag */

+#define HRTIM_TIMICR_DLYPRTC_Pos      (14U)

+#define HRTIM_TIMICR_DLYPRTC_Msk      (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos)      /*!< 0x00004000 */

+#define HRTIM_TIMICR_DLYPRTC          HRTIM_TIMICR_DLYPRTC_Msk                 /*!< Slave output 1 delay protection clear flag */

+

+/******************** Slave DMA/Interrupt enable register *********************/

+#define HRTIM_TIMDIER_CMP1IE_Pos      (0U)

+#define HRTIM_TIMDIER_CMP1IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos)      /*!< 0x00000001 */

+#define HRTIM_TIMDIER_CMP1IE          HRTIM_TIMDIER_CMP1IE_Msk                 /*!< Slave compare 1 interrupt enable */

+#define HRTIM_TIMDIER_CMP2IE_Pos      (1U)

+#define HRTIM_TIMDIER_CMP2IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos)      /*!< 0x00000002 */

+#define HRTIM_TIMDIER_CMP2IE          HRTIM_TIMDIER_CMP2IE_Msk                 /*!< Slave compare 2 interrupt enable */

+#define HRTIM_TIMDIER_CMP3IE_Pos      (2U)

+#define HRTIM_TIMDIER_CMP3IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos)      /*!< 0x00000004 */

+#define HRTIM_TIMDIER_CMP3IE          HRTIM_TIMDIER_CMP3IE_Msk                 /*!< Slave compare 3 interrupt enable */

+#define HRTIM_TIMDIER_CMP4IE_Pos      (3U)

+#define HRTIM_TIMDIER_CMP4IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos)      /*!< 0x00000008 */

+#define HRTIM_TIMDIER_CMP4IE          HRTIM_TIMDIER_CMP4IE_Msk                 /*!< Slave compare 4 interrupt enable */

+#define HRTIM_TIMDIER_REPIE_Pos       (4U)

+#define HRTIM_TIMDIER_REPIE_Msk       (0x1UL << HRTIM_TIMDIER_REPIE_Pos)       /*!< 0x00000010 */

+#define HRTIM_TIMDIER_REPIE           HRTIM_TIMDIER_REPIE_Msk                  /*!< Slave repetition interrupt enable */

+#define HRTIM_TIMDIER_UPDIE_Pos       (6U)

+#define HRTIM_TIMDIER_UPDIE_Msk       (0x1UL << HRTIM_TIMDIER_UPDIE_Pos)       /*!< 0x00000040 */

+#define HRTIM_TIMDIER_UPDIE           HRTIM_TIMDIER_UPDIE_Msk                  /*!< Slave update interrupt enable */

+#define HRTIM_TIMDIER_CPT1IE_Pos      (7U)

+#define HRTIM_TIMDIER_CPT1IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos)      /*!< 0x00000080 */

+#define HRTIM_TIMDIER_CPT1IE          HRTIM_TIMDIER_CPT1IE_Msk                 /*!< Slave capture 1 interrupt enable */

+#define HRTIM_TIMDIER_CPT2IE_Pos      (8U)

+#define HRTIM_TIMDIER_CPT2IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos)      /*!< 0x00000100 */

+#define HRTIM_TIMDIER_CPT2IE          HRTIM_TIMDIER_CPT2IE_Msk                 /*!< Slave capture 2 interrupt enable */

+#define HRTIM_TIMDIER_SET1IE_Pos      (9U)

+#define HRTIM_TIMDIER_SET1IE_Msk      (0x1UL << HRTIM_TIMDIER_SET1IE_Pos)      /*!< 0x00000200 */

+#define HRTIM_TIMDIER_SET1IE          HRTIM_TIMDIER_SET1IE_Msk                 /*!< Slave output 1 set interrupt enable */

+#define HRTIM_TIMDIER_RST1IE_Pos      (10U)

+#define HRTIM_TIMDIER_RST1IE_Msk      (0x1UL << HRTIM_TIMDIER_RST1IE_Pos)      /*!< 0x00000400 */

+#define HRTIM_TIMDIER_RST1IE          HRTIM_TIMDIER_RST1IE_Msk                 /*!< Slave output 1 reset interrupt enable */

+#define HRTIM_TIMDIER_SET2IE_Pos      (11U)

+#define HRTIM_TIMDIER_SET2IE_Msk      (0x1UL << HRTIM_TIMDIER_SET2IE_Pos)      /*!< 0x00000800 */

+#define HRTIM_TIMDIER_SET2IE          HRTIM_TIMDIER_SET2IE_Msk                 /*!< Slave output 2 set interrupt enable */

+#define HRTIM_TIMDIER_RST2IE_Pos      (12U)

+#define HRTIM_TIMDIER_RST2IE_Msk      (0x1UL << HRTIM_TIMDIER_RST2IE_Pos)      /*!< 0x00001000 */

+#define HRTIM_TIMDIER_RST2IE          HRTIM_TIMDIER_RST2IE_Msk                 /*!< Slave output 2 reset interrupt enable */

+#define HRTIM_TIMDIER_RSTIE_Pos       (13U)

+#define HRTIM_TIMDIER_RSTIE_Msk       (0x1UL << HRTIM_TIMDIER_RSTIE_Pos)       /*!< 0x00002000 */

+#define HRTIM_TIMDIER_RSTIE           HRTIM_TIMDIER_RSTIE_Msk                  /*!< Slave reset interrupt enable */

+#define HRTIM_TIMDIER_DLYPRTIE_Pos    (14U)

+#define HRTIM_TIMDIER_DLYPRTIE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos)    /*!< 0x00004000 */

+#define HRTIM_TIMDIER_DLYPRTIE        HRTIM_TIMDIER_DLYPRTIE_Msk               /*!< Slave delay protection interrupt enable */

+

+#define HRTIM_TIMDIER_CMP1DE_Pos      (16U)

+#define HRTIM_TIMDIER_CMP1DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos)      /*!< 0x00010000 */

+#define HRTIM_TIMDIER_CMP1DE          HRTIM_TIMDIER_CMP1DE_Msk                 /*!< Slave compare 1 request enable */

+#define HRTIM_TIMDIER_CMP2DE_Pos      (17U)

+#define HRTIM_TIMDIER_CMP2DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos)      /*!< 0x00020000 */

+#define HRTIM_TIMDIER_CMP2DE          HRTIM_TIMDIER_CMP2DE_Msk                 /*!< Slave compare 2 request enable */

+#define HRTIM_TIMDIER_CMP3DE_Pos      (18U)

+#define HRTIM_TIMDIER_CMP3DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos)      /*!< 0x00040000 */

+#define HRTIM_TIMDIER_CMP3DE          HRTIM_TIMDIER_CMP3DE_Msk                 /*!< Slave compare 3 request enable */

+#define HRTIM_TIMDIER_CMP4DE_Pos      (19U)

+#define HRTIM_TIMDIER_CMP4DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos)      /*!< 0x00080000 */

+#define HRTIM_TIMDIER_CMP4DE          HRTIM_TIMDIER_CMP4DE_Msk                 /*!< Slave compare 4 request enable */

+#define HRTIM_TIMDIER_REPDE_Pos       (20U)

+#define HRTIM_TIMDIER_REPDE_Msk       (0x1UL << HRTIM_TIMDIER_REPDE_Pos)       /*!< 0x00100000 */

+#define HRTIM_TIMDIER_REPDE           HRTIM_TIMDIER_REPDE_Msk                  /*!< Slave repetition request enable */

+#define HRTIM_TIMDIER_UPDDE_Pos       (22U)

+#define HRTIM_TIMDIER_UPDDE_Msk       (0x1UL << HRTIM_TIMDIER_UPDDE_Pos)       /*!< 0x00400000 */

+#define HRTIM_TIMDIER_UPDDE           HRTIM_TIMDIER_UPDDE_Msk                  /*!< Slave update request enable */

+#define HRTIM_TIMDIER_CPT1DE_Pos      (23U)

+#define HRTIM_TIMDIER_CPT1DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos)      /*!< 0x00800000 */

+#define HRTIM_TIMDIER_CPT1DE          HRTIM_TIMDIER_CPT1DE_Msk                 /*!< Slave capture 1 request enable */

+#define HRTIM_TIMDIER_CPT2DE_Pos      (24U)

+#define HRTIM_TIMDIER_CPT2DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos)      /*!< 0x01000000 */

+#define HRTIM_TIMDIER_CPT2DE          HRTIM_TIMDIER_CPT2DE_Msk                 /*!< Slave capture 2 request enable */

+#define HRTIM_TIMDIER_SET1DE_Pos      (25U)

+#define HRTIM_TIMDIER_SET1DE_Msk      (0x1UL << HRTIM_TIMDIER_SET1DE_Pos)      /*!< 0x02000000 */

+#define HRTIM_TIMDIER_SET1DE          HRTIM_TIMDIER_SET1DE_Msk                 /*!< Slave output 1 set request enable */

+#define HRTIM_TIMDIER_RST1DE_Pos      (26U)

+#define HRTIM_TIMDIER_RST1DE_Msk      (0x1UL << HRTIM_TIMDIER_RST1DE_Pos)      /*!< 0x04000000 */

+#define HRTIM_TIMDIER_RST1DE          HRTIM_TIMDIER_RST1DE_Msk                 /*!< Slave output 1 reset request enable */

+#define HRTIM_TIMDIER_SET2DE_Pos      (27U)

+#define HRTIM_TIMDIER_SET2DE_Msk      (0x1UL << HRTIM_TIMDIER_SET2DE_Pos)      /*!< 0x08000000 */

+#define HRTIM_TIMDIER_SET2DE          HRTIM_TIMDIER_SET2DE_Msk                 /*!< Slave output 2 set request enable */

+#define HRTIM_TIMDIER_RST2DE_Pos      (28U)

+#define HRTIM_TIMDIER_RST2DE_Msk      (0x1UL << HRTIM_TIMDIER_RST2DE_Pos)      /*!< 0x10000000 */

+#define HRTIM_TIMDIER_RST2DE          HRTIM_TIMDIER_RST2DE_Msk                 /*!< Slave output 2 reset request enable */

+#define HRTIM_TIMDIER_RSTDE_Pos       (29U)

+#define HRTIM_TIMDIER_RSTDE_Msk       (0x1UL << HRTIM_TIMDIER_RSTDE_Pos)       /*!< 0x20000000 */

+#define HRTIM_TIMDIER_RSTDE           HRTIM_TIMDIER_RSTDE_Msk                  /*!< Slave reset request enable */

+#define HRTIM_TIMDIER_DLYPRTDE_Pos    (30U)

+#define HRTIM_TIMDIER_DLYPRTDE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos)    /*!< 0x40000000 */

+#define HRTIM_TIMDIER_DLYPRTDE        HRTIM_TIMDIER_DLYPRTDE_Msk               /*!< Slavedelay protection request enable */

+

+/******************  Bit definition for HRTIM_CNTR register  ****************/

+#define HRTIM_CNTR_CNTR_Pos           (0U)

+#define HRTIM_CNTR_CNTR_Msk           (0xFFFFUL << HRTIM_CNTR_CNTR_Pos)        /*!< 0x0000FFFF */

+#define HRTIM_CNTR_CNTR               HRTIM_CNTR_CNTR_Msk                      /*!< Counter Value */

+

+/*******************  Bit definition for HRTIM_PER register  *****************/

+#define HRTIM_PER_PER_Pos             (0U)

+#define HRTIM_PER_PER_Msk             (0xFFFFUL << HRTIM_PER_PER_Pos)          /*!< 0x0000FFFF */

+#define HRTIM_PER_PER                 HRTIM_PER_PER_Msk                        /*!< Period Value */

+

+/*******************  Bit definition for HRTIM_REP register  *****************/

+#define HRTIM_REP_REP_Pos             (0U)

+#define HRTIM_REP_REP_Msk             (0xFFUL << HRTIM_REP_REP_Pos)            /*!< 0x000000FF */

+#define HRTIM_REP_REP                 HRTIM_REP_REP_Msk                        /*!< Repetition Value */

+

+/*******************  Bit definition for HRTIM_CMP1R register  *****************/

+#define HRTIM_CMP1R_CMP1R_Pos         (0U)

+#define HRTIM_CMP1R_CMP1R_Msk         (0xFFFFUL << HRTIM_CMP1R_CMP1R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP1R_CMP1R             HRTIM_CMP1R_CMP1R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP1CR register  *****************/

+#define HRTIM_CMP1CR_CMP1CR_Pos       (0U)

+#define HRTIM_CMP1CR_CMP1CR_Msk       (0xFFFFFFFFUL << HRTIM_CMP1CR_CMP1CR_Pos) /*!< 0xFFFFFFFF */

+#define HRTIM_CMP1CR_CMP1CR           HRTIM_CMP1CR_CMP1CR_Msk                  /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP2R register  *****************/

+#define HRTIM_CMP2R_CMP2R_Pos         (0U)

+#define HRTIM_CMP2R_CMP2R_Msk         (0xFFFFUL << HRTIM_CMP2R_CMP2R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP2R_CMP2R             HRTIM_CMP2R_CMP2R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP3R register  *****************/

+#define HRTIM_CMP3R_CMP3R_Pos         (0U)

+#define HRTIM_CMP3R_CMP3R_Msk         (0xFFFFUL << HRTIM_CMP3R_CMP3R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP3R_CMP3R             HRTIM_CMP3R_CMP3R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP4R register  *****************/

+#define HRTIM_CMP4R_CMP4R_Pos         (0U)

+#define HRTIM_CMP4R_CMP4R_Msk         (0xFFFFUL << HRTIM_CMP4R_CMP4R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP4R_CMP4R             HRTIM_CMP4R_CMP4R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CPT1R register  ****************/

+#define HRTIM_CPT1R_CPT1R_Pos         (0U)

+#define HRTIM_CPT1R_CPT1R_Msk         (0xFFFFUL << HRTIM_CPT1R_CPT1R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CPT1R_CPT1R             HRTIM_CPT1R_CPT1R_Msk                    /*!< Capture Value */

+

+/*******************  Bit definition for HRTIM_CPT2R register  ****************/

+#define HRTIM_CPT2R_CPT2R_Pos         (0U)

+#define HRTIM_CPT2R_CPT2R_Msk         (0xFFFFUL << HRTIM_CPT2R_CPT2R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CPT2R_CPT2R             HRTIM_CPT2R_CPT2R_Msk                    /*!< Capture Value */

+

+/******************** Bit definition for Slave Deadtime register **************/

+#define HRTIM_DTR_DTR_Pos             (0U)

+#define HRTIM_DTR_DTR_Msk             (0x1FFUL << HRTIM_DTR_DTR_Pos)           /*!< 0x000001FF */

+#define HRTIM_DTR_DTR                 HRTIM_DTR_DTR_Msk                        /*!< Dead time rising value */

+#define HRTIM_DTR_DTR_0               (0x001UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000001 */

+#define HRTIM_DTR_DTR_1               (0x002UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000002 */

+#define HRTIM_DTR_DTR_2               (0x004UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000004 */

+#define HRTIM_DTR_DTR_3               (0x008UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000008 */

+#define HRTIM_DTR_DTR_4               (0x010UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000010 */

+#define HRTIM_DTR_DTR_5               (0x020UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000020 */

+#define HRTIM_DTR_DTR_6               (0x040UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000040 */

+#define HRTIM_DTR_DTR_7               (0x080UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000080 */

+#define HRTIM_DTR_DTR_8               (0x100UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000100 */

+#define HRTIM_DTR_SDTR_Pos            (9U)

+#define HRTIM_DTR_SDTR_Msk            (0x1UL << HRTIM_DTR_SDTR_Pos)            /*!< 0x00000200 */

+#define HRTIM_DTR_SDTR                HRTIM_DTR_SDTR_Msk                       /*!< Sign dead time rising value */

+#define HRTIM_DTR_DTPRSC_Pos          (10U)

+#define HRTIM_DTR_DTPRSC_Msk          (0x7UL << HRTIM_DTR_DTPRSC_Pos)          /*!< 0x00001C00 */

+#define HRTIM_DTR_DTPRSC              HRTIM_DTR_DTPRSC_Msk                     /*!< Dead time prescaler */

+#define HRTIM_DTR_DTPRSC_0            (0x1UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000400 */

+#define HRTIM_DTR_DTPRSC_1            (0x2UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000800 */

+#define HRTIM_DTR_DTPRSC_2            (0x4UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00001000 */

+#define HRTIM_DTR_DTRSLK_Pos          (14U)

+#define HRTIM_DTR_DTRSLK_Msk          (0x1UL << HRTIM_DTR_DTRSLK_Pos)          /*!< 0x00004000 */

+#define HRTIM_DTR_DTRSLK              HRTIM_DTR_DTRSLK_Msk                     /*!< Dead time rising sign lock */

+#define HRTIM_DTR_DTRLK_Pos           (15U)

+#define HRTIM_DTR_DTRLK_Msk           (0x1UL << HRTIM_DTR_DTRLK_Pos)           /*!< 0x00008000 */

+#define HRTIM_DTR_DTRLK               HRTIM_DTR_DTRLK_Msk                      /*!< Dead time rising lock */

+#define HRTIM_DTR_DTF_Pos             (16U)

+#define HRTIM_DTR_DTF_Msk             (0x1FFUL << HRTIM_DTR_DTF_Pos)           /*!< 0x01FF0000 */

+#define HRTIM_DTR_DTF                 HRTIM_DTR_DTF_Msk                        /*!< Dead time falling value */

+#define HRTIM_DTR_DTF_0               (0x001UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00010000 */

+#define HRTIM_DTR_DTF_1               (0x002UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00020000 */

+#define HRTIM_DTR_DTF_2               (0x004UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00040000 */

+#define HRTIM_DTR_DTF_3               (0x008UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00080000 */

+#define HRTIM_DTR_DTF_4               (0x010UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00100000 */

+#define HRTIM_DTR_DTF_5               (0x020UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00200000 */

+#define HRTIM_DTR_DTF_6               (0x040UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00400000 */

+#define HRTIM_DTR_DTF_7               (0x080UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00800000 */

+#define HRTIM_DTR_DTF_8               (0x100UL << HRTIM_DTR_DTF_Pos)            /*!< 0x01000000 */

+#define HRTIM_DTR_SDTF_Pos            (25U)

+#define HRTIM_DTR_SDTF_Msk            (0x1UL << HRTIM_DTR_SDTF_Pos)            /*!< 0x02000000 */

+#define HRTIM_DTR_SDTF                HRTIM_DTR_SDTF_Msk                       /*!< Sign dead time falling value */

+#define HRTIM_DTR_DTFSLK_Pos          (30U)

+#define HRTIM_DTR_DTFSLK_Msk          (0x1UL << HRTIM_DTR_DTFSLK_Pos)          /*!< 0x40000000 */

+#define HRTIM_DTR_DTFSLK              HRTIM_DTR_DTFSLK_Msk                     /*!< Dead time falling sign lock */

+#define HRTIM_DTR_DTFLK_Pos           (31U)

+#define HRTIM_DTR_DTFLK_Msk           (0x1UL << HRTIM_DTR_DTFLK_Pos)           /*!< 0x80000000 */

+#define HRTIM_DTR_DTFLK               HRTIM_DTR_DTFLK_Msk                      /*!< Dead time falling lock */

+

+/**** Bit definition for Slave Output 1 set register **************************/

+#define HRTIM_SET1R_SST_Pos           (0U)

+#define HRTIM_SET1R_SST_Msk           (0x1UL << HRTIM_SET1R_SST_Pos)           /*!< 0x00000001 */

+#define HRTIM_SET1R_SST               HRTIM_SET1R_SST_Msk                      /*!< software set trigger */

+#define HRTIM_SET1R_RESYNC_Pos        (1U)

+#define HRTIM_SET1R_RESYNC_Msk        (0x1UL << HRTIM_SET1R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_SET1R_RESYNC            HRTIM_SET1R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_SET1R_PER_Pos           (2U)

+#define HRTIM_SET1R_PER_Msk           (0x1UL << HRTIM_SET1R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_SET1R_PER               HRTIM_SET1R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_SET1R_CMP1_Pos          (3U)

+#define HRTIM_SET1R_CMP1_Msk          (0x1UL << HRTIM_SET1R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_SET1R_CMP1              HRTIM_SET1R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_SET1R_CMP2_Pos          (4U)

+#define HRTIM_SET1R_CMP2_Msk          (0x1UL << HRTIM_SET1R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_SET1R_CMP2              HRTIM_SET1R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_SET1R_CMP3_Pos          (5U)

+#define HRTIM_SET1R_CMP3_Msk          (0x1UL << HRTIM_SET1R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_SET1R_CMP3              HRTIM_SET1R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_SET1R_CMP4_Pos          (6U)

+#define HRTIM_SET1R_CMP4_Msk          (0x1UL << HRTIM_SET1R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_SET1R_CMP4              HRTIM_SET1R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_SET1R_MSTPER_Pos        (7U)

+#define HRTIM_SET1R_MSTPER_Msk        (0x1UL << HRTIM_SET1R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_SET1R_MSTPER            HRTIM_SET1R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_SET1R_MSTCMP1_Pos       (8U)

+#define HRTIM_SET1R_MSTCMP1_Msk       (0x1UL << HRTIM_SET1R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_SET1R_MSTCMP1           HRTIM_SET1R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_SET1R_MSTCMP2_Pos       (9U)

+#define HRTIM_SET1R_MSTCMP2_Msk       (0x1UL << HRTIM_SET1R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_SET1R_MSTCMP2           HRTIM_SET1R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_SET1R_MSTCMP3_Pos       (10U)

+#define HRTIM_SET1R_MSTCMP3_Msk       (0x1UL << HRTIM_SET1R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_SET1R_MSTCMP3           HRTIM_SET1R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_SET1R_MSTCMP4_Pos       (11U)

+#define HRTIM_SET1R_MSTCMP4_Msk       (0x1UL << HRTIM_SET1R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_SET1R_MSTCMP4           HRTIM_SET1R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_SET1R_TIMEVNT1_Pos      (12U)

+#define HRTIM_SET1R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_SET1R_TIMEVNT1          HRTIM_SET1R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_SET1R_TIMEVNT2_Pos      (13U)

+#define HRTIM_SET1R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_SET1R_TIMEVNT2          HRTIM_SET1R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_SET1R_TIMEVNT3_Pos      (14U)

+#define HRTIM_SET1R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_SET1R_TIMEVNT3          HRTIM_SET1R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_SET1R_TIMEVNT4_Pos      (15U)

+#define HRTIM_SET1R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_SET1R_TIMEVNT4          HRTIM_SET1R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_SET1R_TIMEVNT5_Pos      (16U)

+#define HRTIM_SET1R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_SET1R_TIMEVNT5          HRTIM_SET1R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_SET1R_TIMEVNT6_Pos      (17U)

+#define HRTIM_SET1R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_SET1R_TIMEVNT6          HRTIM_SET1R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_SET1R_TIMEVNT7_Pos      (18U)

+#define HRTIM_SET1R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_SET1R_TIMEVNT7          HRTIM_SET1R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_SET1R_TIMEVNT8_Pos      (19U)

+#define HRTIM_SET1R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_SET1R_TIMEVNT8          HRTIM_SET1R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_SET1R_TIMEVNT9_Pos      (20U)

+#define HRTIM_SET1R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_SET1R_TIMEVNT9          HRTIM_SET1R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_SET1R_EXTVNT1_Pos       (21U)

+#define HRTIM_SET1R_EXTVNT1_Msk       (0x1UL << HRTIM_SET1R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_SET1R_EXTVNT1           HRTIM_SET1R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_SET1R_EXTVNT2_Pos       (22U)

+#define HRTIM_SET1R_EXTVNT2_Msk       (0x1UL << HRTIM_SET1R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_SET1R_EXTVNT2           HRTIM_SET1R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_SET1R_EXTVNT3_Pos       (23U)

+#define HRTIM_SET1R_EXTVNT3_Msk       (0x1UL << HRTIM_SET1R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_SET1R_EXTVNT3           HRTIM_SET1R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_SET1R_EXTVNT4_Pos       (24U)

+#define HRTIM_SET1R_EXTVNT4_Msk       (0x1UL << HRTIM_SET1R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_SET1R_EXTVNT4           HRTIM_SET1R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_SET1R_EXTVNT5_Pos       (25U)

+#define HRTIM_SET1R_EXTVNT5_Msk       (0x1UL << HRTIM_SET1R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_SET1R_EXTVNT5           HRTIM_SET1R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_SET1R_EXTVNT6_Pos       (26U)

+#define HRTIM_SET1R_EXTVNT6_Msk       (0x1UL << HRTIM_SET1R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_SET1R_EXTVNT6           HRTIM_SET1R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_SET1R_EXTVNT7_Pos       (27U)

+#define HRTIM_SET1R_EXTVNT7_Msk       (0x1UL << HRTIM_SET1R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_SET1R_EXTVNT7           HRTIM_SET1R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_SET1R_EXTVNT8_Pos       (28U)

+#define HRTIM_SET1R_EXTVNT8_Msk       (0x1UL << HRTIM_SET1R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_SET1R_EXTVNT8           HRTIM_SET1R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_SET1R_EXTVNT9_Pos       (29U)

+#define HRTIM_SET1R_EXTVNT9_Msk       (0x1UL << HRTIM_SET1R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_SET1R_EXTVNT9           HRTIM_SET1R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_SET1R_EXTVNT10_Pos      (30U)

+#define HRTIM_SET1R_EXTVNT10_Msk      (0x1UL << HRTIM_SET1R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_SET1R_EXTVNT10          HRTIM_SET1R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_SET1R_UPDATE_Pos        (31U)

+#define HRTIM_SET1R_UPDATE_Msk        (0x1UL << HRTIM_SET1R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_SET1R_UPDATE            HRTIM_SET1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+/**** Bit definition for Slave Output 1 reset register ************************/

+#define HRTIM_RST1R_SRT_Pos           (0U)

+#define HRTIM_RST1R_SRT_Msk           (0x1UL << HRTIM_RST1R_SRT_Pos)           /*!< 0x00000001 */

+#define HRTIM_RST1R_SRT               HRTIM_RST1R_SRT_Msk                      /*!< software reset trigger */

+#define HRTIM_RST1R_RESYNC_Pos        (1U)

+#define HRTIM_RST1R_RESYNC_Msk        (0x1UL << HRTIM_RST1R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_RST1R_RESYNC            HRTIM_RST1R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_RST1R_PER_Pos           (2U)

+#define HRTIM_RST1R_PER_Msk           (0x1UL << HRTIM_RST1R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_RST1R_PER               HRTIM_RST1R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_RST1R_CMP1_Pos          (3U)

+#define HRTIM_RST1R_CMP1_Msk          (0x1UL << HRTIM_RST1R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_RST1R_CMP1              HRTIM_RST1R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_RST1R_CMP2_Pos          (4U)

+#define HRTIM_RST1R_CMP2_Msk          (0x1UL << HRTIM_RST1R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_RST1R_CMP2              HRTIM_RST1R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_RST1R_CMP3_Pos          (5U)

+#define HRTIM_RST1R_CMP3_Msk          (0x1UL << HRTIM_RST1R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_RST1R_CMP3              HRTIM_RST1R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_RST1R_CMP4_Pos          (6U)

+#define HRTIM_RST1R_CMP4_Msk          (0x1UL << HRTIM_RST1R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_RST1R_CMP4              HRTIM_RST1R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_RST1R_MSTPER_Pos        (7U)

+#define HRTIM_RST1R_MSTPER_Msk        (0x1UL << HRTIM_RST1R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_RST1R_MSTPER            HRTIM_RST1R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_RST1R_MSTCMP1_Pos       (8U)

+#define HRTIM_RST1R_MSTCMP1_Msk       (0x1UL << HRTIM_RST1R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_RST1R_MSTCMP1           HRTIM_RST1R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_RST1R_MSTCMP2_Pos       (9U)

+#define HRTIM_RST1R_MSTCMP2_Msk       (0x1UL << HRTIM_RST1R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_RST1R_MSTCMP2           HRTIM_RST1R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_RST1R_MSTCMP3_Pos       (10U)

+#define HRTIM_RST1R_MSTCMP3_Msk       (0x1UL << HRTIM_RST1R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_RST1R_MSTCMP3           HRTIM_RST1R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_RST1R_MSTCMP4_Pos       (11U)

+#define HRTIM_RST1R_MSTCMP4_Msk       (0x1UL << HRTIM_RST1R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_RST1R_MSTCMP4           HRTIM_RST1R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_RST1R_TIMEVNT1_Pos      (12U)

+#define HRTIM_RST1R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_RST1R_TIMEVNT1          HRTIM_RST1R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_RST1R_TIMEVNT2_Pos      (13U)

+#define HRTIM_RST1R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_RST1R_TIMEVNT2          HRTIM_RST1R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_RST1R_TIMEVNT3_Pos      (14U)

+#define HRTIM_RST1R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_RST1R_TIMEVNT3          HRTIM_RST1R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_RST1R_TIMEVNT4_Pos      (15U)

+#define HRTIM_RST1R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_RST1R_TIMEVNT4          HRTIM_RST1R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_RST1R_TIMEVNT5_Pos      (16U)

+#define HRTIM_RST1R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_RST1R_TIMEVNT5          HRTIM_RST1R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_RST1R_TIMEVNT6_Pos      (17U)

+#define HRTIM_RST1R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_RST1R_TIMEVNT6          HRTIM_RST1R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_RST1R_TIMEVNT7_Pos      (18U)

+#define HRTIM_RST1R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_RST1R_TIMEVNT7          HRTIM_RST1R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_RST1R_TIMEVNT8_Pos      (19U)

+#define HRTIM_RST1R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_RST1R_TIMEVNT8          HRTIM_RST1R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_RST1R_TIMEVNT9_Pos      (20U)

+#define HRTIM_RST1R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_RST1R_TIMEVNT9          HRTIM_RST1R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_RST1R_EXTVNT1_Pos       (21U)

+#define HRTIM_RST1R_EXTVNT1_Msk       (0x1UL << HRTIM_RST1R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_RST1R_EXTVNT1           HRTIM_RST1R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_RST1R_EXTVNT2_Pos       (22U)

+#define HRTIM_RST1R_EXTVNT2_Msk       (0x1UL << HRTIM_RST1R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_RST1R_EXTVNT2           HRTIM_RST1R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_RST1R_EXTVNT3_Pos       (23U)

+#define HRTIM_RST1R_EXTVNT3_Msk       (0x1UL << HRTIM_RST1R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_RST1R_EXTVNT3           HRTIM_RST1R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_RST1R_EXTVNT4_Pos       (24U)

+#define HRTIM_RST1R_EXTVNT4_Msk       (0x1UL << HRTIM_RST1R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_RST1R_EXTVNT4           HRTIM_RST1R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_RST1R_EXTVNT5_Pos       (25U)

+#define HRTIM_RST1R_EXTVNT5_Msk       (0x1UL << HRTIM_RST1R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_RST1R_EXTVNT5           HRTIM_RST1R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_RST1R_EXTVNT6_Pos       (26U)

+#define HRTIM_RST1R_EXTVNT6_Msk       (0x1UL << HRTIM_RST1R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_RST1R_EXTVNT6           HRTIM_RST1R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_RST1R_EXTVNT7_Pos       (27U)

+#define HRTIM_RST1R_EXTVNT7_Msk       (0x1UL << HRTIM_RST1R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_RST1R_EXTVNT7           HRTIM_RST1R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_RST1R_EXTVNT8_Pos       (28U)

+#define HRTIM_RST1R_EXTVNT8_Msk       (0x1UL << HRTIM_RST1R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_RST1R_EXTVNT8           HRTIM_RST1R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_RST1R_EXTVNT9_Pos       (29U)

+#define HRTIM_RST1R_EXTVNT9_Msk       (0x1UL << HRTIM_RST1R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_RST1R_EXTVNT9           HRTIM_RST1R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_RST1R_EXTVNT10_Pos      (30U)

+#define HRTIM_RST1R_EXTVNT10_Msk      (0x1UL << HRTIM_RST1R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_RST1R_EXTVNT10          HRTIM_RST1R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_RST1R_UPDATE_Pos        (31U)

+#define HRTIM_RST1R_UPDATE_Msk        (0x1UL << HRTIM_RST1R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_RST1R_UPDATE            HRTIM_RST1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+

+/**** Bit definition for Slave Output 2 set register **************************/

+#define HRTIM_SET2R_SST_Pos           (0U)

+#define HRTIM_SET2R_SST_Msk           (0x1UL << HRTIM_SET2R_SST_Pos)           /*!< 0x00000001 */

+#define HRTIM_SET2R_SST               HRTIM_SET2R_SST_Msk                      /*!< software set trigger */

+#define HRTIM_SET2R_RESYNC_Pos        (1U)

+#define HRTIM_SET2R_RESYNC_Msk        (0x1UL << HRTIM_SET2R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_SET2R_RESYNC            HRTIM_SET2R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_SET2R_PER_Pos           (2U)

+#define HRTIM_SET2R_PER_Msk           (0x1UL << HRTIM_SET2R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_SET2R_PER               HRTIM_SET2R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_SET2R_CMP1_Pos          (3U)

+#define HRTIM_SET2R_CMP1_Msk          (0x1UL << HRTIM_SET2R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_SET2R_CMP1              HRTIM_SET2R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_SET2R_CMP2_Pos          (4U)

+#define HRTIM_SET2R_CMP2_Msk          (0x1UL << HRTIM_SET2R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_SET2R_CMP2              HRTIM_SET2R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_SET2R_CMP3_Pos          (5U)

+#define HRTIM_SET2R_CMP3_Msk          (0x1UL << HRTIM_SET2R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_SET2R_CMP3              HRTIM_SET2R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_SET2R_CMP4_Pos          (6U)

+#define HRTIM_SET2R_CMP4_Msk          (0x1UL << HRTIM_SET2R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_SET2R_CMP4              HRTIM_SET2R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_SET2R_MSTPER_Pos        (7U)

+#define HRTIM_SET2R_MSTPER_Msk        (0x1UL << HRTIM_SET2R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_SET2R_MSTPER            HRTIM_SET2R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_SET2R_MSTCMP1_Pos       (8U)

+#define HRTIM_SET2R_MSTCMP1_Msk       (0x1UL << HRTIM_SET2R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_SET2R_MSTCMP1           HRTIM_SET2R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_SET2R_MSTCMP2_Pos       (9U)

+#define HRTIM_SET2R_MSTCMP2_Msk       (0x1UL << HRTIM_SET2R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_SET2R_MSTCMP2           HRTIM_SET2R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_SET2R_MSTCMP3_Pos       (10U)

+#define HRTIM_SET2R_MSTCMP3_Msk       (0x1UL << HRTIM_SET2R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_SET2R_MSTCMP3           HRTIM_SET2R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_SET2R_MSTCMP4_Pos       (11U)

+#define HRTIM_SET2R_MSTCMP4_Msk       (0x1UL << HRTIM_SET2R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_SET2R_MSTCMP4           HRTIM_SET2R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_SET2R_TIMEVNT1_Pos      (12U)

+#define HRTIM_SET2R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_SET2R_TIMEVNT1          HRTIM_SET2R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_SET2R_TIMEVNT2_Pos      (13U)

+#define HRTIM_SET2R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_SET2R_TIMEVNT2          HRTIM_SET2R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_SET2R_TIMEVNT3_Pos      (14U)

+#define HRTIM_SET2R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_SET2R_TIMEVNT3          HRTIM_SET2R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_SET2R_TIMEVNT4_Pos      (15U)

+#define HRTIM_SET2R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_SET2R_TIMEVNT4          HRTIM_SET2R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_SET2R_TIMEVNT5_Pos      (16U)

+#define HRTIM_SET2R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_SET2R_TIMEVNT5          HRTIM_SET2R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_SET2R_TIMEVNT6_Pos      (17U)

+#define HRTIM_SET2R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_SET2R_TIMEVNT6          HRTIM_SET2R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_SET2R_TIMEVNT7_Pos      (18U)

+#define HRTIM_SET2R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_SET2R_TIMEVNT7          HRTIM_SET2R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_SET2R_TIMEVNT8_Pos      (19U)

+#define HRTIM_SET2R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_SET2R_TIMEVNT8          HRTIM_SET2R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_SET2R_TIMEVNT9_Pos      (20U)

+#define HRTIM_SET2R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_SET2R_TIMEVNT9          HRTIM_SET2R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_SET2R_EXTVNT1_Pos       (21U)

+#define HRTIM_SET2R_EXTVNT1_Msk       (0x1UL << HRTIM_SET2R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_SET2R_EXTVNT1           HRTIM_SET2R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_SET2R_EXTVNT2_Pos       (22U)

+#define HRTIM_SET2R_EXTVNT2_Msk       (0x1UL << HRTIM_SET2R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_SET2R_EXTVNT2           HRTIM_SET2R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_SET2R_EXTVNT3_Pos       (23U)

+#define HRTIM_SET2R_EXTVNT3_Msk       (0x1UL << HRTIM_SET2R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_SET2R_EXTVNT3           HRTIM_SET2R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_SET2R_EXTVNT4_Pos       (24U)

+#define HRTIM_SET2R_EXTVNT4_Msk       (0x1UL << HRTIM_SET2R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_SET2R_EXTVNT4           HRTIM_SET2R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_SET2R_EXTVNT5_Pos       (25U)

+#define HRTIM_SET2R_EXTVNT5_Msk       (0x1UL << HRTIM_SET2R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_SET2R_EXTVNT5           HRTIM_SET2R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_SET2R_EXTVNT6_Pos       (26U)

+#define HRTIM_SET2R_EXTVNT6_Msk       (0x1UL << HRTIM_SET2R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_SET2R_EXTVNT6           HRTIM_SET2R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_SET2R_EXTVNT7_Pos       (27U)

+#define HRTIM_SET2R_EXTVNT7_Msk       (0x1UL << HRTIM_SET2R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_SET2R_EXTVNT7           HRTIM_SET2R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_SET2R_EXTVNT8_Pos       (28U)

+#define HRTIM_SET2R_EXTVNT8_Msk       (0x1UL << HRTIM_SET2R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_SET2R_EXTVNT8           HRTIM_SET2R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_SET2R_EXTVNT9_Pos       (29U)

+#define HRTIM_SET2R_EXTVNT9_Msk       (0x1UL << HRTIM_SET2R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_SET2R_EXTVNT9           HRTIM_SET2R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_SET2R_EXTVNT10_Pos      (30U)

+#define HRTIM_SET2R_EXTVNT10_Msk      (0x1UL << HRTIM_SET2R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_SET2R_EXTVNT10          HRTIM_SET2R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_SET2R_UPDATE_Pos        (31U)

+#define HRTIM_SET2R_UPDATE_Msk        (0x1UL << HRTIM_SET2R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_SET2R_UPDATE            HRTIM_SET2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+/**** Bit definition for Slave Output 2 reset register ************************/

+#define HRTIM_RST2R_SRT_Pos           (0U)

+#define HRTIM_RST2R_SRT_Msk           (0x1UL << HRTIM_RST2R_SRT_Pos)           /*!< 0x00000001 */

+#define HRTIM_RST2R_SRT               HRTIM_RST2R_SRT_Msk                      /*!< software reset trigger */

+#define HRTIM_RST2R_RESYNC_Pos        (1U)

+#define HRTIM_RST2R_RESYNC_Msk        (0x1UL << HRTIM_RST2R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_RST2R_RESYNC            HRTIM_RST2R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_RST2R_PER_Pos           (2U)

+#define HRTIM_RST2R_PER_Msk           (0x1UL << HRTIM_RST2R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_RST2R_PER               HRTIM_RST2R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_RST2R_CMP1_Pos          (3U)

+#define HRTIM_RST2R_CMP1_Msk          (0x1UL << HRTIM_RST2R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_RST2R_CMP1              HRTIM_RST2R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_RST2R_CMP2_Pos          (4U)

+#define HRTIM_RST2R_CMP2_Msk          (0x1UL << HRTIM_RST2R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_RST2R_CMP2              HRTIM_RST2R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_RST2R_CMP3_Pos          (5U)

+#define HRTIM_RST2R_CMP3_Msk          (0x1UL << HRTIM_RST2R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_RST2R_CMP3              HRTIM_RST2R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_RST2R_CMP4_Pos          (6U)

+#define HRTIM_RST2R_CMP4_Msk          (0x1UL << HRTIM_RST2R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_RST2R_CMP4              HRTIM_RST2R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_RST2R_MSTPER_Pos        (7U)

+#define HRTIM_RST2R_MSTPER_Msk        (0x1UL << HRTIM_RST2R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_RST2R_MSTPER            HRTIM_RST2R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_RST2R_MSTCMP1_Pos       (8U)

+#define HRTIM_RST2R_MSTCMP1_Msk       (0x1UL << HRTIM_RST2R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_RST2R_MSTCMP1           HRTIM_RST2R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_RST2R_MSTCMP2_Pos       (9U)

+#define HRTIM_RST2R_MSTCMP2_Msk       (0x1UL << HRTIM_RST2R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_RST2R_MSTCMP2           HRTIM_RST2R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_RST2R_MSTCMP3_Pos       (10U)

+#define HRTIM_RST2R_MSTCMP3_Msk       (0x1UL << HRTIM_RST2R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_RST2R_MSTCMP3           HRTIM_RST2R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_RST2R_MSTCMP4_Pos       (11U)

+#define HRTIM_RST2R_MSTCMP4_Msk       (0x1UL << HRTIM_RST2R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_RST2R_MSTCMP4           HRTIM_RST2R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_RST2R_TIMEVNT1_Pos      (12U)

+#define HRTIM_RST2R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_RST2R_TIMEVNT1          HRTIM_RST2R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_RST2R_TIMEVNT2_Pos      (13U)

+#define HRTIM_RST2R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_RST2R_TIMEVNT2          HRTIM_RST2R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_RST2R_TIMEVNT3_Pos      (14U)

+#define HRTIM_RST2R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_RST2R_TIMEVNT3          HRTIM_RST2R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_RST2R_TIMEVNT4_Pos      (15U)

+#define HRTIM_RST2R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_RST2R_TIMEVNT4          HRTIM_RST2R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_RST2R_TIMEVNT5_Pos      (16U)

+#define HRTIM_RST2R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_RST2R_TIMEVNT5          HRTIM_RST2R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_RST2R_TIMEVNT6_Pos      (17U)

+#define HRTIM_RST2R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_RST2R_TIMEVNT6          HRTIM_RST2R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_RST2R_TIMEVNT7_Pos      (18U)

+#define HRTIM_RST2R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_RST2R_TIMEVNT7          HRTIM_RST2R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_RST2R_TIMEVNT8_Pos      (19U)

+#define HRTIM_RST2R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_RST2R_TIMEVNT8          HRTIM_RST2R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_RST2R_TIMEVNT9_Pos      (20U)

+#define HRTIM_RST2R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_RST2R_TIMEVNT9          HRTIM_RST2R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_RST2R_EXTVNT1_Pos       (21U)

+#define HRTIM_RST2R_EXTVNT1_Msk       (0x1UL << HRTIM_RST2R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_RST2R_EXTVNT1           HRTIM_RST2R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_RST2R_EXTVNT2_Pos       (22U)

+#define HRTIM_RST2R_EXTVNT2_Msk       (0x1UL << HRTIM_RST2R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_RST2R_EXTVNT2           HRTIM_RST2R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_RST2R_EXTVNT3_Pos       (23U)

+#define HRTIM_RST2R_EXTVNT3_Msk       (0x1UL << HRTIM_RST2R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_RST2R_EXTVNT3           HRTIM_RST2R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_RST2R_EXTVNT4_Pos       (24U)

+#define HRTIM_RST2R_EXTVNT4_Msk       (0x1UL << HRTIM_RST2R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_RST2R_EXTVNT4           HRTIM_RST2R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_RST2R_EXTVNT5_Pos       (25U)

+#define HRTIM_RST2R_EXTVNT5_Msk       (0x1UL << HRTIM_RST2R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_RST2R_EXTVNT5           HRTIM_RST2R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_RST2R_EXTVNT6_Pos       (26U)

+#define HRTIM_RST2R_EXTVNT6_Msk       (0x1UL << HRTIM_RST2R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_RST2R_EXTVNT6           HRTIM_RST2R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_RST2R_EXTVNT7_Pos       (27U)

+#define HRTIM_RST2R_EXTVNT7_Msk       (0x1UL << HRTIM_RST2R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_RST2R_EXTVNT7           HRTIM_RST2R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_RST2R_EXTVNT8_Pos       (28U)

+#define HRTIM_RST2R_EXTVNT8_Msk       (0x1UL << HRTIM_RST2R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_RST2R_EXTVNT8           HRTIM_RST2R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_RST2R_EXTVNT9_Pos       (29U)

+#define HRTIM_RST2R_EXTVNT9_Msk       (0x1UL << HRTIM_RST2R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_RST2R_EXTVNT9           HRTIM_RST2R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_RST2R_EXTVNT10_Pos      (30U)

+#define HRTIM_RST2R_EXTVNT10_Msk      (0x1UL << HRTIM_RST2R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_RST2R_EXTVNT10          HRTIM_RST2R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_RST2R_UPDATE_Pos        (31U)

+#define HRTIM_RST2R_UPDATE_Msk        (0x1UL << HRTIM_RST2R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_RST2R_UPDATE            HRTIM_RST2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+/**** Bit definition for Slave external event filtering  register 1 ***********/

+#define HRTIM_EEFR1_EE1LTCH_Pos       (0U)

+#define HRTIM_EEFR1_EE1LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos)       /*!< 0x00000001 */

+#define HRTIM_EEFR1_EE1LTCH           HRTIM_EEFR1_EE1LTCH_Msk                  /*!< External Event 1 latch */

+#define HRTIM_EEFR1_EE1FLTR_Pos       (1U)

+#define HRTIM_EEFR1_EE1FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos)       /*!< 0x0000001E */

+#define HRTIM_EEFR1_EE1FLTR           HRTIM_EEFR1_EE1FLTR_Msk                  /*!< External Event 1 filter mask */

+#define HRTIM_EEFR1_EE1FLTR_0         (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000002 */

+#define HRTIM_EEFR1_EE1FLTR_1         (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000004 */

+#define HRTIM_EEFR1_EE1FLTR_2         (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000008 */

+#define HRTIM_EEFR1_EE1FLTR_3         (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000010 */

+

+#define HRTIM_EEFR1_EE2LTCH_Pos       (6U)

+#define HRTIM_EEFR1_EE2LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos)       /*!< 0x00000040 */

+#define HRTIM_EEFR1_EE2LTCH           HRTIM_EEFR1_EE2LTCH_Msk                  /*!< External Event 2 latch */

+#define HRTIM_EEFR1_EE2FLTR_Pos       (7U)

+#define HRTIM_EEFR1_EE2FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos)       /*!< 0x00000780 */

+#define HRTIM_EEFR1_EE2FLTR           HRTIM_EEFR1_EE2FLTR_Msk                  /*!< External Event 2 filter mask */

+#define HRTIM_EEFR1_EE2FLTR_0         (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000080 */

+#define HRTIM_EEFR1_EE2FLTR_1         (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000100 */

+#define HRTIM_EEFR1_EE2FLTR_2         (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000200 */

+#define HRTIM_EEFR1_EE2FLTR_3         (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000400 */

+

+#define HRTIM_EEFR1_EE3LTCH_Pos       (12U)

+#define HRTIM_EEFR1_EE3LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos)       /*!< 0x00001000 */

+#define HRTIM_EEFR1_EE3LTCH           HRTIM_EEFR1_EE3LTCH_Msk                  /*!< External Event 3 latch */

+#define HRTIM_EEFR1_EE3FLTR_Pos       (13U)

+#define HRTIM_EEFR1_EE3FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos)       /*!< 0x0001E000 */

+#define HRTIM_EEFR1_EE3FLTR           HRTIM_EEFR1_EE3FLTR_Msk                  /*!< External Event 3 filter mask */

+#define HRTIM_EEFR1_EE3FLTR_0         (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00002000 */

+#define HRTIM_EEFR1_EE3FLTR_1         (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00004000 */

+#define HRTIM_EEFR1_EE3FLTR_2         (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00008000 */

+#define HRTIM_EEFR1_EE3FLTR_3         (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00010000 */

+

+#define HRTIM_EEFR1_EE4LTCH_Pos       (18U)

+#define HRTIM_EEFR1_EE4LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos)       /*!< 0x00040000 */

+#define HRTIM_EEFR1_EE4LTCH           HRTIM_EEFR1_EE4LTCH_Msk                  /*!< External Event 4 latch */

+#define HRTIM_EEFR1_EE4FLTR_Pos       (19U)

+#define HRTIM_EEFR1_EE4FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos)       /*!< 0x00780000 */

+#define HRTIM_EEFR1_EE4FLTR           HRTIM_EEFR1_EE4FLTR_Msk                  /*!< External Event 4 filter mask */

+#define HRTIM_EEFR1_EE4FLTR_0         (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00080000 */

+#define HRTIM_EEFR1_EE4FLTR_1         (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00100000 */

+#define HRTIM_EEFR1_EE4FLTR_2         (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00200000 */

+#define HRTIM_EEFR1_EE4FLTR_3         (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00400000 */

+

+#define HRTIM_EEFR1_EE5LTCH_Pos       (24U)

+#define HRTIM_EEFR1_EE5LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos)       /*!< 0x01000000 */

+#define HRTIM_EEFR1_EE5LTCH           HRTIM_EEFR1_EE5LTCH_Msk                  /*!< External Event 5 latch */

+#define HRTIM_EEFR1_EE5FLTR_Pos       (25U)

+#define HRTIM_EEFR1_EE5FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos)       /*!< 0x1E000000 */

+#define HRTIM_EEFR1_EE5FLTR           HRTIM_EEFR1_EE5FLTR_Msk                  /*!< External Event 5 filter mask */

+#define HRTIM_EEFR1_EE5FLTR_0         (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x02000000 */

+#define HRTIM_EEFR1_EE5FLTR_1         (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x04000000 */

+#define HRTIM_EEFR1_EE5FLTR_2         (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x08000000 */

+#define HRTIM_EEFR1_EE5FLTR_3         (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x10000000 */

+

+/**** Bit definition for Slave external event filtering  register 2 ***********/

+#define HRTIM_EEFR2_EE6LTCH_Pos       (0U)

+#define HRTIM_EEFR2_EE6LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos)       /*!< 0x00000001 */

+#define HRTIM_EEFR2_EE6LTCH           HRTIM_EEFR2_EE6LTCH_Msk                  /*!< External Event 6 latch */

+#define HRTIM_EEFR2_EE6FLTR_Pos       (1U)

+#define HRTIM_EEFR2_EE6FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos)       /*!< 0x0000001E */

+#define HRTIM_EEFR2_EE6FLTR           HRTIM_EEFR2_EE6FLTR_Msk                  /*!< External Event 6 filter mask */

+#define HRTIM_EEFR2_EE6FLTR_0         (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000002 */

+#define HRTIM_EEFR2_EE6FLTR_1         (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000004 */

+#define HRTIM_EEFR2_EE6FLTR_2         (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000008 */

+#define HRTIM_EEFR2_EE6FLTR_3         (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000010 */

+

+#define HRTIM_EEFR2_EE7LTCH_Pos       (6U)

+#define HRTIM_EEFR2_EE7LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos)       /*!< 0x00000040 */

+#define HRTIM_EEFR2_EE7LTCH           HRTIM_EEFR2_EE7LTCH_Msk                  /*!< External Event 7 latch */

+#define HRTIM_EEFR2_EE7FLTR_Pos       (7U)

+#define HRTIM_EEFR2_EE7FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos)       /*!< 0x00000780 */

+#define HRTIM_EEFR2_EE7FLTR           HRTIM_EEFR2_EE7FLTR_Msk                  /*!< External Event 7 filter mask */

+#define HRTIM_EEFR2_EE7FLTR_0         (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000080 */

+#define HRTIM_EEFR2_EE7FLTR_1         (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000100 */

+#define HRTIM_EEFR2_EE7FLTR_2         (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000200 */

+#define HRTIM_EEFR2_EE7FLTR_3         (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000400 */

+

+#define HRTIM_EEFR2_EE8LTCH_Pos       (12U)

+#define HRTIM_EEFR2_EE8LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos)       /*!< 0x00001000 */

+#define HRTIM_EEFR2_EE8LTCH           HRTIM_EEFR2_EE8LTCH_Msk                  /*!< External Event 8 latch */

+#define HRTIM_EEFR2_EE8FLTR_Pos       (13U)

+#define HRTIM_EEFR2_EE8FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos)       /*!< 0x0001E000 */

+#define HRTIM_EEFR2_EE8FLTR           HRTIM_EEFR2_EE8FLTR_Msk                  /*!< External Event 8 filter mask */

+#define HRTIM_EEFR2_EE8FLTR_0         (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00002000 */

+#define HRTIM_EEFR2_EE8FLTR_1         (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00004000 */

+#define HRTIM_EEFR2_EE8FLTR_2         (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00008000 */

+#define HRTIM_EEFR2_EE8FLTR_3         (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00010000 */

+

+#define HRTIM_EEFR2_EE9LTCH_Pos       (18U)

+#define HRTIM_EEFR2_EE9LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos)       /*!< 0x00040000 */

+#define HRTIM_EEFR2_EE9LTCH           HRTIM_EEFR2_EE9LTCH_Msk                  /*!< External Event 9 latch */

+#define HRTIM_EEFR2_EE9FLTR_Pos       (19U)

+#define HRTIM_EEFR2_EE9FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos)       /*!< 0x00780000 */

+#define HRTIM_EEFR2_EE9FLTR           HRTIM_EEFR2_EE9FLTR_Msk                  /*!< External Event 9 filter mask */

+#define HRTIM_EEFR2_EE9FLTR_0         (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00080000 */

+#define HRTIM_EEFR2_EE9FLTR_1         (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00100000 */

+#define HRTIM_EEFR2_EE9FLTR_2         (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00200000 */

+#define HRTIM_EEFR2_EE9FLTR_3         (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00400000 */

+

+#define HRTIM_EEFR2_EE10LTCH_Pos      (24U)

+#define HRTIM_EEFR2_EE10LTCH_Msk      (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos)      /*!< 0x01000000 */

+#define HRTIM_EEFR2_EE10LTCH          HRTIM_EEFR2_EE10LTCH_Msk                 /*!< External Event 10 latch */

+#define HRTIM_EEFR2_EE10FLTR_Pos      (25U)

+#define HRTIM_EEFR2_EE10FLTR_Msk      (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos)      /*!< 0x1E000000 */

+#define HRTIM_EEFR2_EE10FLTR          HRTIM_EEFR2_EE10FLTR_Msk                 /*!< External Event 10 filter mask */

+#define HRTIM_EEFR2_EE10FLTR_0        (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x02000000 */

+#define HRTIM_EEFR2_EE10FLTR_1        (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x04000000 */

+#define HRTIM_EEFR2_EE10FLTR_2        (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x08000000 */

+#define HRTIM_EEFR2_EE10FLTR_3        (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x10000000 */

+

+/**** Bit definition for Slave Timer reset register ***************************/

+#define HRTIM_RSTR_UPDATE_Pos         (1U)

+#define HRTIM_RSTR_UPDATE_Msk         (0x1UL << HRTIM_RSTR_UPDATE_Pos)         /*!< 0x00000002 */

+#define HRTIM_RSTR_UPDATE             HRTIM_RSTR_UPDATE_Msk                    /*!< Timer update */

+#define HRTIM_RSTR_CMP2_Pos           (2U)

+#define HRTIM_RSTR_CMP2_Msk           (0x1UL << HRTIM_RSTR_CMP2_Pos)           /*!< 0x00000004 */

+#define HRTIM_RSTR_CMP2               HRTIM_RSTR_CMP2_Msk                      /*!< Timer compare2 */

+#define HRTIM_RSTR_CMP4_Pos           (3U)

+#define HRTIM_RSTR_CMP4_Msk           (0x1UL << HRTIM_RSTR_CMP4_Pos)           /*!< 0x00000008 */

+#define HRTIM_RSTR_CMP4               HRTIM_RSTR_CMP4_Msk                      /*!< Timer compare4 */

+

+#define HRTIM_RSTR_MSTPER_Pos         (4U)

+#define HRTIM_RSTR_MSTPER_Msk         (0x1UL << HRTIM_RSTR_MSTPER_Pos)         /*!< 0x00000010 */

+#define HRTIM_RSTR_MSTPER             HRTIM_RSTR_MSTPER_Msk                    /*!< Master period */

+#define HRTIM_RSTR_MSTCMP1_Pos        (5U)

+#define HRTIM_RSTR_MSTCMP1_Msk        (0x1UL << HRTIM_RSTR_MSTCMP1_Pos)        /*!< 0x00000020 */

+#define HRTIM_RSTR_MSTCMP1            HRTIM_RSTR_MSTCMP1_Msk                   /*!< Master compare1 */

+#define HRTIM_RSTR_MSTCMP2_Pos        (6U)

+#define HRTIM_RSTR_MSTCMP2_Msk        (0x1UL << HRTIM_RSTR_MSTCMP2_Pos)        /*!< 0x00000040 */

+#define HRTIM_RSTR_MSTCMP2            HRTIM_RSTR_MSTCMP2_Msk                   /*!< Master compare2 */

+#define HRTIM_RSTR_MSTCMP3_Pos        (7U)

+#define HRTIM_RSTR_MSTCMP3_Msk        (0x1UL << HRTIM_RSTR_MSTCMP3_Pos)        /*!< 0x00000080 */

+#define HRTIM_RSTR_MSTCMP3            HRTIM_RSTR_MSTCMP3_Msk                   /*!< Master compare3 */

+#define HRTIM_RSTR_MSTCMP4_Pos        (8U)

+#define HRTIM_RSTR_MSTCMP4_Msk        (0x1UL << HRTIM_RSTR_MSTCMP4_Pos)        /*!< 0x00000100 */

+#define HRTIM_RSTR_MSTCMP4            HRTIM_RSTR_MSTCMP4_Msk                   /*!< Master compare4 */

+

+#define HRTIM_RSTR_EXTEVNT1_Pos       (9U)

+#define HRTIM_RSTR_EXTEVNT1_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos)       /*!< 0x00000200 */

+#define HRTIM_RSTR_EXTEVNT1           HRTIM_RSTR_EXTEVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_RSTR_EXTEVNT2_Pos       (10U)

+#define HRTIM_RSTR_EXTEVNT2_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos)       /*!< 0x00000400 */

+#define HRTIM_RSTR_EXTEVNT2           HRTIM_RSTR_EXTEVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_RSTR_EXTEVNT3_Pos       (11U)

+#define HRTIM_RSTR_EXTEVNT3_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos)       /*!< 0x00000800 */

+#define HRTIM_RSTR_EXTEVNT3           HRTIM_RSTR_EXTEVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_RSTR_EXTEVNT4_Pos       (12U)

+#define HRTIM_RSTR_EXTEVNT4_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos)       /*!< 0x00001000 */

+#define HRTIM_RSTR_EXTEVNT4           HRTIM_RSTR_EXTEVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_RSTR_EXTEVNT5_Pos       (13U)

+#define HRTIM_RSTR_EXTEVNT5_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos)       /*!< 0x00002000 */

+#define HRTIM_RSTR_EXTEVNT5           HRTIM_RSTR_EXTEVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_RSTR_EXTEVNT6_Pos       (14U)

+#define HRTIM_RSTR_EXTEVNT6_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos)       /*!< 0x00004000 */

+#define HRTIM_RSTR_EXTEVNT6           HRTIM_RSTR_EXTEVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_RSTR_EXTEVNT7_Pos       (15U)

+#define HRTIM_RSTR_EXTEVNT7_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos)       /*!< 0x00008000 */

+#define HRTIM_RSTR_EXTEVNT7           HRTIM_RSTR_EXTEVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_RSTR_EXTEVNT8_Pos       (16U)

+#define HRTIM_RSTR_EXTEVNT8_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos)       /*!< 0x00010000 */

+#define HRTIM_RSTR_EXTEVNT8           HRTIM_RSTR_EXTEVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_RSTR_EXTEVNT9_Pos       (17U)

+#define HRTIM_RSTR_EXTEVNT9_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos)       /*!< 0x00020000 */

+#define HRTIM_RSTR_EXTEVNT9           HRTIM_RSTR_EXTEVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_RSTR_EXTEVNT10_Pos      (18U)

+#define HRTIM_RSTR_EXTEVNT10_Msk      (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos)      /*!< 0x00040000 */

+#define HRTIM_RSTR_EXTEVNT10          HRTIM_RSTR_EXTEVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_RSTR_TIMBCMP1_Pos       (19U)

+#define HRTIM_RSTR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos)       /*!< 0x00080000 */

+#define HRTIM_RSTR_TIMBCMP1           HRTIM_RSTR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */

+#define HRTIM_RSTR_TIMBCMP2_Pos       (20U)

+#define HRTIM_RSTR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos)       /*!< 0x00100000 */

+#define HRTIM_RSTR_TIMBCMP2           HRTIM_RSTR_TIMBCMP2_Msk                  /*!< Timer B compare 2 */

+#define HRTIM_RSTR_TIMBCMP4_Pos       (21U)

+#define HRTIM_RSTR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos)       /*!< 0x00200000 */

+#define HRTIM_RSTR_TIMBCMP4           HRTIM_RSTR_TIMBCMP4_Msk                  /*!< Timer B compare 4 */

+

+#define HRTIM_RSTR_TIMCCMP1_Pos       (22U)

+#define HRTIM_RSTR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos)       /*!< 0x00400000 */

+#define HRTIM_RSTR_TIMCCMP1           HRTIM_RSTR_TIMCCMP1_Msk                  /*!< Timer C compare 1 */

+#define HRTIM_RSTR_TIMCCMP2_Pos       (23U)

+#define HRTIM_RSTR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos)       /*!< 0x00800000 */

+#define HRTIM_RSTR_TIMCCMP2           HRTIM_RSTR_TIMCCMP2_Msk                  /*!< Timer C compare 2 */

+#define HRTIM_RSTR_TIMCCMP4_Pos       (24U)

+#define HRTIM_RSTR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos)       /*!< 0x01000000 */

+#define HRTIM_RSTR_TIMCCMP4           HRTIM_RSTR_TIMCCMP4_Msk                  /*!< Timer C compare 4 */

+

+#define HRTIM_RSTR_TIMDCMP1_Pos       (25U)

+#define HRTIM_RSTR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos)       /*!< 0x02000000 */

+#define HRTIM_RSTR_TIMDCMP1           HRTIM_RSTR_TIMDCMP1_Msk                  /*!< Timer D compare 1 */

+#define HRTIM_RSTR_TIMDCMP2_Pos       (26U)

+#define HRTIM_RSTR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos)       /*!< 0x04000000 */

+#define HRTIM_RSTR_TIMDCMP2           HRTIM_RSTR_TIMDCMP2_Msk                  /*!< Timer D compare 2 */

+#define HRTIM_RSTR_TIMDCMP4_Pos       (27U)

+#define HRTIM_RSTR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos)       /*!< 0x08000000 */

+#define HRTIM_RSTR_TIMDCMP4           HRTIM_RSTR_TIMDCMP4_Msk                  /*!< Timer D compare 4 */

+

+#define HRTIM_RSTR_TIMECMP1_Pos       (28U)

+#define HRTIM_RSTR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTR_TIMECMP1_Pos)       /*!< 0x10000000 */

+#define HRTIM_RSTR_TIMECMP1           HRTIM_RSTR_TIMECMP1_Msk                  /*!< Timer E compare 1 */

+#define HRTIM_RSTR_TIMECMP2_Pos       (29U)

+#define HRTIM_RSTR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTR_TIMECMP2_Pos)       /*!< 0x20000000 */

+#define HRTIM_RSTR_TIMECMP2           HRTIM_RSTR_TIMECMP2_Msk                  /*!< Timer E compare 2 */

+#define HRTIM_RSTR_TIMECMP4_Pos       (30U)

+#define HRTIM_RSTR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTR_TIMECMP4_Pos)       /*!< 0x40000000 */

+#define HRTIM_RSTR_TIMECMP4           HRTIM_RSTR_TIMECMP4_Msk                  /*!< Timer E compare 4 */

+

+/**** Bit definition for Slave Timer Chopper register *************************/

+#define HRTIM_CHPR_CARFRQ_Pos         (0U)

+#define HRTIM_CHPR_CARFRQ_Msk         (0xFUL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x0000000F */

+#define HRTIM_CHPR_CARFRQ             HRTIM_CHPR_CARFRQ_Msk                    /*!< Timer carrier frequency value */

+#define HRTIM_CHPR_CARFRQ_0           (0x1UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000001 */

+#define HRTIM_CHPR_CARFRQ_1           (0x2UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000002 */

+#define HRTIM_CHPR_CARFRQ_2           (0x4UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000004 */

+#define HRTIM_CHPR_CARFRQ_3           (0x8UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000008 */

+

+#define HRTIM_CHPR_CARDTY_Pos         (4U)

+#define HRTIM_CHPR_CARDTY_Msk         (0x7UL << HRTIM_CHPR_CARDTY_Pos)         /*!< 0x00000070 */

+#define HRTIM_CHPR_CARDTY             HRTIM_CHPR_CARDTY_Msk                    /*!< Timer chopper duty cycle value */

+#define HRTIM_CHPR_CARDTY_0           (0x1UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000010 */

+#define HRTIM_CHPR_CARDTY_1           (0x2UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000020 */

+#define HRTIM_CHPR_CARDTY_2           (0x4UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000040 */

+

+#define HRTIM_CHPR_STRPW_Pos          (7U)

+#define HRTIM_CHPR_STRPW_Msk          (0xFUL << HRTIM_CHPR_STRPW_Pos)          /*!< 0x00000780 */

+#define HRTIM_CHPR_STRPW              HRTIM_CHPR_STRPW_Msk                     /*!< Timer start pulse width value */

+#define HRTIM_CHPR_STRPW_0            (0x1UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000080 */

+#define HRTIM_CHPR_STRPW_1            (0x2UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000100 */

+#define HRTIM_CHPR_STRPW_2            (0x4UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000200 */

+#define HRTIM_CHPR_STRPW_3            (0x8UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000400 */

+

+/**** Bit definition for Slave Timer Capture 1 control register ***************/

+#define HRTIM_CPT1CR_SWCPT_Pos        (0U)

+#define HRTIM_CPT1CR_SWCPT_Msk        (0x1UL << HRTIM_CPT1CR_SWCPT_Pos)        /*!< 0x00000001 */

+#define HRTIM_CPT1CR_SWCPT            HRTIM_CPT1CR_SWCPT_Msk                   /*!< Software capture */

+#define HRTIM_CPT1CR_UPDCPT_Pos       (1U)

+#define HRTIM_CPT1CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos)       /*!< 0x00000002 */

+#define HRTIM_CPT1CR_UPDCPT           HRTIM_CPT1CR_UPDCPT_Msk                  /*!< Update capture */

+#define HRTIM_CPT1CR_EXEV1CPT_Pos     (2U)

+#define HRTIM_CPT1CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos)     /*!< 0x00000004 */

+#define HRTIM_CPT1CR_EXEV1CPT         HRTIM_CPT1CR_EXEV1CPT_Msk                /*!< External event 1 capture */

+#define HRTIM_CPT1CR_EXEV2CPT_Pos     (3U)

+#define HRTIM_CPT1CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos)     /*!< 0x00000008 */

+#define HRTIM_CPT1CR_EXEV2CPT         HRTIM_CPT1CR_EXEV2CPT_Msk                /*!< External event 2 capture */

+#define HRTIM_CPT1CR_EXEV3CPT_Pos     (4U)

+#define HRTIM_CPT1CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos)     /*!< 0x00000010 */

+#define HRTIM_CPT1CR_EXEV3CPT         HRTIM_CPT1CR_EXEV3CPT_Msk                /*!< External event 3 capture */

+#define HRTIM_CPT1CR_EXEV4CPT_Pos     (5U)

+#define HRTIM_CPT1CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos)     /*!< 0x00000020 */

+#define HRTIM_CPT1CR_EXEV4CPT         HRTIM_CPT1CR_EXEV4CPT_Msk                /*!< External event 4 capture */

+#define HRTIM_CPT1CR_EXEV5CPT_Pos     (6U)

+#define HRTIM_CPT1CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos)     /*!< 0x00000040 */

+#define HRTIM_CPT1CR_EXEV5CPT         HRTIM_CPT1CR_EXEV5CPT_Msk                /*!< External event 5 capture */

+#define HRTIM_CPT1CR_EXEV6CPT_Pos     (7U)

+#define HRTIM_CPT1CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos)     /*!< 0x00000080 */

+#define HRTIM_CPT1CR_EXEV6CPT         HRTIM_CPT1CR_EXEV6CPT_Msk                /*!< External event 6 capture */

+#define HRTIM_CPT1CR_EXEV7CPT_Pos     (8U)

+#define HRTIM_CPT1CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos)     /*!< 0x00000100 */

+#define HRTIM_CPT1CR_EXEV7CPT         HRTIM_CPT1CR_EXEV7CPT_Msk                /*!< External event 7 capture */

+#define HRTIM_CPT1CR_EXEV8CPT_Pos     (9U)

+#define HRTIM_CPT1CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos)     /*!< 0x00000200 */

+#define HRTIM_CPT1CR_EXEV8CPT         HRTIM_CPT1CR_EXEV8CPT_Msk                /*!< External event 8 capture */

+#define HRTIM_CPT1CR_EXEV9CPT_Pos     (10U)

+#define HRTIM_CPT1CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos)     /*!< 0x00000400 */

+#define HRTIM_CPT1CR_EXEV9CPT         HRTIM_CPT1CR_EXEV9CPT_Msk                /*!< External event 9 capture */

+#define HRTIM_CPT1CR_EXEV10CPT_Pos    (11U)

+#define HRTIM_CPT1CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos)    /*!< 0x00000800 */

+#define HRTIM_CPT1CR_EXEV10CPT        HRTIM_CPT1CR_EXEV10CPT_Msk               /*!< External event 10 capture */

+

+#define HRTIM_CPT1CR_TA1SET_Pos       (12U)

+#define HRTIM_CPT1CR_TA1SET_Msk       (0x1UL << HRTIM_CPT1CR_TA1SET_Pos)       /*!< 0x00001000 */

+#define HRTIM_CPT1CR_TA1SET           HRTIM_CPT1CR_TA1SET_Msk                  /*!< Timer A output 1 set */

+#define HRTIM_CPT1CR_TA1RST_Pos       (13U)

+#define HRTIM_CPT1CR_TA1RST_Msk       (0x1UL << HRTIM_CPT1CR_TA1RST_Pos)       /*!< 0x00002000 */

+#define HRTIM_CPT1CR_TA1RST           HRTIM_CPT1CR_TA1RST_Msk                  /*!< Timer A output 1 reset */

+#define HRTIM_CPT1CR_TIMACMP1_Pos     (14U)

+#define HRTIM_CPT1CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos)     /*!< 0x00004000 */

+#define HRTIM_CPT1CR_TIMACMP1         HRTIM_CPT1CR_TIMACMP1_Msk                /*!< Timer A compare 1 */

+#define HRTIM_CPT1CR_TIMACMP2_Pos     (15U)

+#define HRTIM_CPT1CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos)     /*!< 0x00008000 */

+#define HRTIM_CPT1CR_TIMACMP2         HRTIM_CPT1CR_TIMACMP2_Msk                /*!< Timer A compare 2 */

+

+#define HRTIM_CPT1CR_TB1SET_Pos       (16U)

+#define HRTIM_CPT1CR_TB1SET_Msk       (0x1UL << HRTIM_CPT1CR_TB1SET_Pos)       /*!< 0x00010000 */

+#define HRTIM_CPT1CR_TB1SET           HRTIM_CPT1CR_TB1SET_Msk                  /*!< Timer B output 1 set */

+#define HRTIM_CPT1CR_TB1RST_Pos       (17U)

+#define HRTIM_CPT1CR_TB1RST_Msk       (0x1UL << HRTIM_CPT1CR_TB1RST_Pos)       /*!< 0x00020000 */

+#define HRTIM_CPT1CR_TB1RST           HRTIM_CPT1CR_TB1RST_Msk                  /*!< Timer B output 1 reset */

+#define HRTIM_CPT1CR_TIMBCMP1_Pos     (18U)

+#define HRTIM_CPT1CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos)     /*!< 0x00040000 */

+#define HRTIM_CPT1CR_TIMBCMP1         HRTIM_CPT1CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */

+#define HRTIM_CPT1CR_TIMBCMP2_Pos     (19U)

+#define HRTIM_CPT1CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos)     /*!< 0x00080000 */

+#define HRTIM_CPT1CR_TIMBCMP2         HRTIM_CPT1CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */

+

+#define HRTIM_CPT1CR_TC1SET_Pos       (20U)

+#define HRTIM_CPT1CR_TC1SET_Msk       (0x1UL << HRTIM_CPT1CR_TC1SET_Pos)       /*!< 0x00100000 */

+#define HRTIM_CPT1CR_TC1SET           HRTIM_CPT1CR_TC1SET_Msk                  /*!< Timer C output 1 set */

+#define HRTIM_CPT1CR_TC1RST_Pos       (21U)

+#define HRTIM_CPT1CR_TC1RST_Msk       (0x1UL << HRTIM_CPT1CR_TC1RST_Pos)       /*!< 0x00200000 */

+#define HRTIM_CPT1CR_TC1RST           HRTIM_CPT1CR_TC1RST_Msk                  /*!< Timer C output 1 reset */

+#define HRTIM_CPT1CR_TIMCCMP1_Pos     (22U)

+#define HRTIM_CPT1CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos)     /*!< 0x00400000 */

+#define HRTIM_CPT1CR_TIMCCMP1         HRTIM_CPT1CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */

+#define HRTIM_CPT1CR_TIMCCMP2_Pos     (23U)

+#define HRTIM_CPT1CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos)     /*!< 0x00800000 */

+#define HRTIM_CPT1CR_TIMCCMP2         HRTIM_CPT1CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */

+

+#define HRTIM_CPT1CR_TD1SET_Pos       (24U)

+#define HRTIM_CPT1CR_TD1SET_Msk       (0x1UL << HRTIM_CPT1CR_TD1SET_Pos)       /*!< 0x01000000 */

+#define HRTIM_CPT1CR_TD1SET           HRTIM_CPT1CR_TD1SET_Msk                  /*!< Timer D output 1 set */

+#define HRTIM_CPT1CR_TD1RST_Pos       (25U)

+#define HRTIM_CPT1CR_TD1RST_Msk       (0x1UL << HRTIM_CPT1CR_TD1RST_Pos)       /*!< 0x02000000 */

+#define HRTIM_CPT1CR_TD1RST           HRTIM_CPT1CR_TD1RST_Msk                  /*!< Timer D output 1 reset */

+#define HRTIM_CPT1CR_TIMDCMP1_Pos     (26U)

+#define HRTIM_CPT1CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos)     /*!< 0x04000000 */

+#define HRTIM_CPT1CR_TIMDCMP1         HRTIM_CPT1CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */

+#define HRTIM_CPT1CR_TIMDCMP2_Pos     (27U)

+#define HRTIM_CPT1CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos)     /*!< 0x08000000 */

+#define HRTIM_CPT1CR_TIMDCMP2         HRTIM_CPT1CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */

+

+#define HRTIM_CPT1CR_TE1SET_Pos       (28U)

+#define HRTIM_CPT1CR_TE1SET_Msk       (0x1UL << HRTIM_CPT1CR_TE1SET_Pos)       /*!< 0x10000000 */

+#define HRTIM_CPT1CR_TE1SET           HRTIM_CPT1CR_TE1SET_Msk                  /*!< Timer E output 1 set */

+#define HRTIM_CPT1CR_TE1RST_Pos       (29U)

+#define HRTIM_CPT1CR_TE1RST_Msk       (0x1UL << HRTIM_CPT1CR_TE1RST_Pos)       /*!< 0x20000000 */

+#define HRTIM_CPT1CR_TE1RST           HRTIM_CPT1CR_TE1RST_Msk                  /*!< Timer E output 1 reset */

+#define HRTIM_CPT1CR_TIMECMP1_Pos     (30U)

+#define HRTIM_CPT1CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos)     /*!< 0x40000000 */

+#define HRTIM_CPT1CR_TIMECMP1         HRTIM_CPT1CR_TIMECMP1_Msk                /*!< Timer E compare 1 */

+#define HRTIM_CPT1CR_TIMECMP2_Pos     (31U)

+#define HRTIM_CPT1CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos)     /*!< 0x80000000 */

+#define HRTIM_CPT1CR_TIMECMP2         HRTIM_CPT1CR_TIMECMP2_Msk                /*!< Timer E compare 2 */

+

+/**** Bit definition for Slave Timer Capture 2 control register ***************/

+#define HRTIM_CPT2CR_SWCPT_Pos        (0U)

+#define HRTIM_CPT2CR_SWCPT_Msk        (0x1UL << HRTIM_CPT2CR_SWCPT_Pos)        /*!< 0x00000001 */

+#define HRTIM_CPT2CR_SWCPT            HRTIM_CPT2CR_SWCPT_Msk                   /*!< Software capture */

+#define HRTIM_CPT2CR_UPDCPT_Pos       (1U)

+#define HRTIM_CPT2CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos)       /*!< 0x00000002 */

+#define HRTIM_CPT2CR_UPDCPT           HRTIM_CPT2CR_UPDCPT_Msk                  /*!< Update capture */

+#define HRTIM_CPT2CR_EXEV1CPT_Pos     (2U)

+#define HRTIM_CPT2CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos)     /*!< 0x00000004 */

+#define HRTIM_CPT2CR_EXEV1CPT         HRTIM_CPT2CR_EXEV1CPT_Msk                /*!< External event 1 capture */

+#define HRTIM_CPT2CR_EXEV2CPT_Pos     (3U)

+#define HRTIM_CPT2CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos)     /*!< 0x00000008 */

+#define HRTIM_CPT2CR_EXEV2CPT         HRTIM_CPT2CR_EXEV2CPT_Msk                /*!< External event 2 capture */

+#define HRTIM_CPT2CR_EXEV3CPT_Pos     (4U)

+#define HRTIM_CPT2CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos)     /*!< 0x00000010 */

+#define HRTIM_CPT2CR_EXEV3CPT         HRTIM_CPT2CR_EXEV3CPT_Msk                /*!< External event 3 capture */

+#define HRTIM_CPT2CR_EXEV4CPT_Pos     (5U)

+#define HRTIM_CPT2CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos)     /*!< 0x00000020 */

+#define HRTIM_CPT2CR_EXEV4CPT         HRTIM_CPT2CR_EXEV4CPT_Msk                /*!< External event 4 capture */

+#define HRTIM_CPT2CR_EXEV5CPT_Pos     (6U)

+#define HRTIM_CPT2CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos)     /*!< 0x00000040 */

+#define HRTIM_CPT2CR_EXEV5CPT         HRTIM_CPT2CR_EXEV5CPT_Msk                /*!< External event 5 capture */

+#define HRTIM_CPT2CR_EXEV6CPT_Pos     (7U)

+#define HRTIM_CPT2CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos)     /*!< 0x00000080 */

+#define HRTIM_CPT2CR_EXEV6CPT         HRTIM_CPT2CR_EXEV6CPT_Msk                /*!< External event 6 capture */

+#define HRTIM_CPT2CR_EXEV7CPT_Pos     (8U)

+#define HRTIM_CPT2CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos)     /*!< 0x00000100 */

+#define HRTIM_CPT2CR_EXEV7CPT         HRTIM_CPT2CR_EXEV7CPT_Msk                /*!< External event 7 capture */

+#define HRTIM_CPT2CR_EXEV8CPT_Pos     (9U)

+#define HRTIM_CPT2CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos)     /*!< 0x00000200 */

+#define HRTIM_CPT2CR_EXEV8CPT         HRTIM_CPT2CR_EXEV8CPT_Msk                /*!< External event 8 capture */

+#define HRTIM_CPT2CR_EXEV9CPT_Pos     (10U)

+#define HRTIM_CPT2CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos)     /*!< 0x00000400 */

+#define HRTIM_CPT2CR_EXEV9CPT         HRTIM_CPT2CR_EXEV9CPT_Msk                /*!< External event 9 capture */

+#define HRTIM_CPT2CR_EXEV10CPT_Pos    (11U)

+#define HRTIM_CPT2CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos)    /*!< 0x00000800 */

+#define HRTIM_CPT2CR_EXEV10CPT        HRTIM_CPT2CR_EXEV10CPT_Msk               /*!< External event 10 capture */

+

+#define HRTIM_CPT2CR_TA1SET_Pos       (12U)

+#define HRTIM_CPT2CR_TA1SET_Msk       (0x1UL << HRTIM_CPT2CR_TA1SET_Pos)       /*!< 0x00001000 */

+#define HRTIM_CPT2CR_TA1SET           HRTIM_CPT2CR_TA1SET_Msk                  /*!< Timer A output 1 set */

+#define HRTIM_CPT2CR_TA1RST_Pos       (13U)

+#define HRTIM_CPT2CR_TA1RST_Msk       (0x1UL << HRTIM_CPT2CR_TA1RST_Pos)       /*!< 0x00002000 */

+#define HRTIM_CPT2CR_TA1RST           HRTIM_CPT2CR_TA1RST_Msk                  /*!< Timer A output 1 reset */

+#define HRTIM_CPT2CR_TIMACMP1_Pos     (14U)

+#define HRTIM_CPT2CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos)     /*!< 0x00004000 */

+#define HRTIM_CPT2CR_TIMACMP1         HRTIM_CPT2CR_TIMACMP1_Msk                /*!< Timer A compare 1 */

+#define HRTIM_CPT2CR_TIMACMP2_Pos     (15U)

+#define HRTIM_CPT2CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos)     /*!< 0x00008000 */

+#define HRTIM_CPT2CR_TIMACMP2         HRTIM_CPT2CR_TIMACMP2_Msk                /*!< Timer A compare 2 */

+

+#define HRTIM_CPT2CR_TB1SET_Pos       (16U)

+#define HRTIM_CPT2CR_TB1SET_Msk       (0x1UL << HRTIM_CPT2CR_TB1SET_Pos)       /*!< 0x00010000 */

+#define HRTIM_CPT2CR_TB1SET           HRTIM_CPT2CR_TB1SET_Msk                  /*!< Timer B output 1 set */

+#define HRTIM_CPT2CR_TB1RST_Pos       (17U)

+#define HRTIM_CPT2CR_TB1RST_Msk       (0x1UL << HRTIM_CPT2CR_TB1RST_Pos)       /*!< 0x00020000 */

+#define HRTIM_CPT2CR_TB1RST           HRTIM_CPT2CR_TB1RST_Msk                  /*!< Timer B output 1 reset */

+#define HRTIM_CPT2CR_TIMBCMP1_Pos     (18U)

+#define HRTIM_CPT2CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos)     /*!< 0x00040000 */

+#define HRTIM_CPT2CR_TIMBCMP1         HRTIM_CPT2CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */

+#define HRTIM_CPT2CR_TIMBCMP2_Pos     (19U)

+#define HRTIM_CPT2CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos)     /*!< 0x00080000 */

+#define HRTIM_CPT2CR_TIMBCMP2         HRTIM_CPT2CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */

+

+#define HRTIM_CPT2CR_TC1SET_Pos       (20U)

+#define HRTIM_CPT2CR_TC1SET_Msk       (0x1UL << HRTIM_CPT2CR_TC1SET_Pos)       /*!< 0x00100000 */

+#define HRTIM_CPT2CR_TC1SET           HRTIM_CPT2CR_TC1SET_Msk                  /*!< Timer C output 1 set */

+#define HRTIM_CPT2CR_TC1RST_Pos       (21U)

+#define HRTIM_CPT2CR_TC1RST_Msk       (0x1UL << HRTIM_CPT2CR_TC1RST_Pos)       /*!< 0x00200000 */

+#define HRTIM_CPT2CR_TC1RST           HRTIM_CPT2CR_TC1RST_Msk                  /*!< Timer C output 1 reset */

+#define HRTIM_CPT2CR_TIMCCMP1_Pos     (22U)

+#define HRTIM_CPT2CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos)     /*!< 0x00400000 */

+#define HRTIM_CPT2CR_TIMCCMP1         HRTIM_CPT2CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */

+#define HRTIM_CPT2CR_TIMCCMP2_Pos     (23U)

+#define HRTIM_CPT2CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos)     /*!< 0x00800000 */

+#define HRTIM_CPT2CR_TIMCCMP2         HRTIM_CPT2CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */

+

+#define HRTIM_CPT2CR_TD1SET_Pos       (24U)

+#define HRTIM_CPT2CR_TD1SET_Msk       (0x1UL << HRTIM_CPT2CR_TD1SET_Pos)       /*!< 0x01000000 */

+#define HRTIM_CPT2CR_TD1SET           HRTIM_CPT2CR_TD1SET_Msk                  /*!< Timer D output 1 set */

+#define HRTIM_CPT2CR_TD1RST_Pos       (25U)

+#define HRTIM_CPT2CR_TD1RST_Msk       (0x1UL << HRTIM_CPT2CR_TD1RST_Pos)       /*!< 0x02000000 */

+#define HRTIM_CPT2CR_TD1RST           HRTIM_CPT2CR_TD1RST_Msk                  /*!< Timer D output 1 reset */

+#define HRTIM_CPT2CR_TIMDCMP1_Pos     (26U)

+#define HRTIM_CPT2CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos)     /*!< 0x04000000 */

+#define HRTIM_CPT2CR_TIMDCMP1         HRTIM_CPT2CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */

+#define HRTIM_CPT2CR_TIMDCMP2_Pos     (27U)

+#define HRTIM_CPT2CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos)     /*!< 0x08000000 */

+#define HRTIM_CPT2CR_TIMDCMP2         HRTIM_CPT2CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */

+

+#define HRTIM_CPT2CR_TE1SET_Pos       (28U)

+#define HRTIM_CPT2CR_TE1SET_Msk       (0x1UL << HRTIM_CPT2CR_TE1SET_Pos)       /*!< 0x10000000 */

+#define HRTIM_CPT2CR_TE1SET           HRTIM_CPT2CR_TE1SET_Msk                  /*!< Timer E output 1 set */

+#define HRTIM_CPT2CR_TE1RST_Pos       (29U)

+#define HRTIM_CPT2CR_TE1RST_Msk       (0x1UL << HRTIM_CPT2CR_TE1RST_Pos)       /*!< 0x20000000 */

+#define HRTIM_CPT2CR_TE1RST           HRTIM_CPT2CR_TE1RST_Msk                  /*!< Timer E output 1 reset */

+#define HRTIM_CPT2CR_TIMECMP1_Pos     (30U)

+#define HRTIM_CPT2CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos)     /*!< 0x40000000 */

+#define HRTIM_CPT2CR_TIMECMP1         HRTIM_CPT2CR_TIMECMP1_Msk                /*!< Timer E compare 1 */

+#define HRTIM_CPT2CR_TIMECMP2_Pos     (31U)

+#define HRTIM_CPT2CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos)     /*!< 0x80000000 */

+#define HRTIM_CPT2CR_TIMECMP2         HRTIM_CPT2CR_TIMECMP2_Msk                /*!< Timer E compare 2 */

+

+/**** Bit definition for Slave Timer Output register **************************/

+#define HRTIM_OUTR_POL1_Pos           (1U)

+#define HRTIM_OUTR_POL1_Msk           (0x1UL << HRTIM_OUTR_POL1_Pos)           /*!< 0x00000002 */

+#define HRTIM_OUTR_POL1               HRTIM_OUTR_POL1_Msk                      /*!< Slave output 1 polarity */

+#define HRTIM_OUTR_IDLM1_Pos          (2U)

+#define HRTIM_OUTR_IDLM1_Msk          (0x1UL << HRTIM_OUTR_IDLM1_Pos)          /*!< 0x00000004 */

+#define HRTIM_OUTR_IDLM1              HRTIM_OUTR_IDLM1_Msk                     /*!< Slave output 1 idle mode */

+#define HRTIM_OUTR_IDLES1_Pos         (3U)

+#define HRTIM_OUTR_IDLES1_Msk         (0x1UL << HRTIM_OUTR_IDLES1_Pos)         /*!< 0x00000008 */

+#define HRTIM_OUTR_IDLES1             HRTIM_OUTR_IDLES1_Msk                    /*!< Slave output 1 idle state */

+#define HRTIM_OUTR_FAULT1_Pos         (4U)

+#define HRTIM_OUTR_FAULT1_Msk         (0x3UL << HRTIM_OUTR_FAULT1_Pos)         /*!< 0x00000030 */

+#define HRTIM_OUTR_FAULT1             HRTIM_OUTR_FAULT1_Msk                    /*!< Slave output 1 fault state */

+#define HRTIM_OUTR_FAULT1_0           (0x1UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000010 */

+#define HRTIM_OUTR_FAULT1_1           (0x2UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000020 */

+#define HRTIM_OUTR_CHP1_Pos           (6U)

+#define HRTIM_OUTR_CHP1_Msk           (0x1UL << HRTIM_OUTR_CHP1_Pos)           /*!< 0x00000040 */

+#define HRTIM_OUTR_CHP1               HRTIM_OUTR_CHP1_Msk                      /*!< Slave output 1 chopper enable */

+#define HRTIM_OUTR_DIDL1_Pos          (7U)

+#define HRTIM_OUTR_DIDL1_Msk          (0x1UL << HRTIM_OUTR_DIDL1_Pos)          /*!< 0x00000080 */

+#define HRTIM_OUTR_DIDL1              HRTIM_OUTR_DIDL1_Msk                     /*!< Slave output 1 dead time idle */

+

+#define HRTIM_OUTR_DTEN_Pos           (8U)

+#define HRTIM_OUTR_DTEN_Msk           (0x1UL << HRTIM_OUTR_DTEN_Pos)           /*!< 0x00000100 */

+#define HRTIM_OUTR_DTEN               HRTIM_OUTR_DTEN_Msk                      /*!< Slave output deadtime enable */

+#define HRTIM_OUTR_DLYPRTEN_Pos       (9U)

+#define HRTIM_OUTR_DLYPRTEN_Msk       (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos)       /*!< 0x00000200 */

+#define HRTIM_OUTR_DLYPRTEN           HRTIM_OUTR_DLYPRTEN_Msk                  /*!< Slave output delay protection enable */

+#define HRTIM_OUTR_DLYPRT_Pos         (10U)

+#define HRTIM_OUTR_DLYPRT_Msk         (0x7UL << HRTIM_OUTR_DLYPRT_Pos)         /*!< 0x00001C00 */

+#define HRTIM_OUTR_DLYPRT             HRTIM_OUTR_DLYPRT_Msk                    /*!< Slave output delay protection */

+#define HRTIM_OUTR_DLYPRT_0           (0x1UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000400 */

+#define HRTIM_OUTR_DLYPRT_1           (0x2UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000800 */

+#define HRTIM_OUTR_DLYPRT_2           (0x4UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00001000 */

+

+#define HRTIM_OUTR_POL2_Pos           (17U)

+#define HRTIM_OUTR_POL2_Msk           (0x1UL << HRTIM_OUTR_POL2_Pos)           /*!< 0x00020000 */

+#define HRTIM_OUTR_POL2               HRTIM_OUTR_POL2_Msk                      /*!< Slave output 2 polarity */

+#define HRTIM_OUTR_IDLM2_Pos          (18U)

+#define HRTIM_OUTR_IDLM2_Msk          (0x1UL << HRTIM_OUTR_IDLM2_Pos)          /*!< 0x00040000 */

+#define HRTIM_OUTR_IDLM2              HRTIM_OUTR_IDLM2_Msk                     /*!< Slave output 2 idle mode */

+#define HRTIM_OUTR_IDLES2_Pos         (19U)

+#define HRTIM_OUTR_IDLES2_Msk         (0x1UL << HRTIM_OUTR_IDLES2_Pos)         /*!< 0x00080000 */

+#define HRTIM_OUTR_IDLES2             HRTIM_OUTR_IDLES2_Msk                    /*!< Slave output 2 idle state */

+#define HRTIM_OUTR_FAULT2_Pos         (20U)

+#define HRTIM_OUTR_FAULT2_Msk         (0x3UL << HRTIM_OUTR_FAULT2_Pos)         /*!< 0x00300000 */

+#define HRTIM_OUTR_FAULT2             HRTIM_OUTR_FAULT2_Msk                    /*!< Slave output 2 fault state */

+#define HRTIM_OUTR_FAULT2_0           (0x1UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00100000 */

+#define HRTIM_OUTR_FAULT2_1           (0x2UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00200000 */

+#define HRTIM_OUTR_CHP2_Pos           (22U)

+#define HRTIM_OUTR_CHP2_Msk           (0x1UL << HRTIM_OUTR_CHP2_Pos)           /*!< 0x00400000 */

+#define HRTIM_OUTR_CHP2               HRTIM_OUTR_CHP2_Msk                      /*!< Slave output 2 chopper enable */

+#define HRTIM_OUTR_DIDL2_Pos          (23U)

+#define HRTIM_OUTR_DIDL2_Msk          (0x1UL << HRTIM_OUTR_DIDL2_Pos)          /*!< 0x00800000 */

+#define HRTIM_OUTR_DIDL2              HRTIM_OUTR_DIDL2_Msk                     /*!< Slave output 2 dead time idle */

+

+/**** Bit definition for Slave Timer Fault register ***************************/

+#define HRTIM_FLTR_FLT1EN_Pos         (0U)

+#define HRTIM_FLTR_FLT1EN_Msk         (0x1UL << HRTIM_FLTR_FLT1EN_Pos)         /*!< 0x00000001 */

+#define HRTIM_FLTR_FLT1EN             HRTIM_FLTR_FLT1EN_Msk                    /*!< Fault 1 enable */

+#define HRTIM_FLTR_FLT2EN_Pos         (1U)

+#define HRTIM_FLTR_FLT2EN_Msk         (0x1UL << HRTIM_FLTR_FLT2EN_Pos)         /*!< 0x00000002 */

+#define HRTIM_FLTR_FLT2EN             HRTIM_FLTR_FLT2EN_Msk                    /*!< Fault 2 enable */

+#define HRTIM_FLTR_FLT3EN_Pos         (2U)

+#define HRTIM_FLTR_FLT3EN_Msk         (0x1UL << HRTIM_FLTR_FLT3EN_Pos)         /*!< 0x00000004 */

+#define HRTIM_FLTR_FLT3EN             HRTIM_FLTR_FLT3EN_Msk                    /*!< Fault 3 enable */

+#define HRTIM_FLTR_FLT4EN_Pos         (3U)

+#define HRTIM_FLTR_FLT4EN_Msk         (0x1UL << HRTIM_FLTR_FLT4EN_Pos)         /*!< 0x00000008 */

+#define HRTIM_FLTR_FLT4EN             HRTIM_FLTR_FLT4EN_Msk                    /*!< Fault 4 enable */

+#define HRTIM_FLTR_FLT5EN_Pos         (4U)

+#define HRTIM_FLTR_FLT5EN_Msk         (0x1UL << HRTIM_FLTR_FLT5EN_Pos)         /*!< 0x00000010 */

+#define HRTIM_FLTR_FLT5EN             HRTIM_FLTR_FLT5EN_Msk                    /*!< Fault 5 enable */

+#define HRTIM_FLTR_FLTLCK_Pos         (31U)

+#define HRTIM_FLTR_FLTLCK_Msk         (0x1UL << HRTIM_FLTR_FLTLCK_Pos)         /*!< 0x80000000 */

+#define HRTIM_FLTR_FLTLCK             HRTIM_FLTR_FLTLCK_Msk                    /*!< Fault sources lock */

+

+/**** Bit definition for Common HRTIM Timer control register 1 ****************/

+#define HRTIM_CR1_MUDIS_Pos           (0U)

+#define HRTIM_CR1_MUDIS_Msk           (0x1UL << HRTIM_CR1_MUDIS_Pos)           /*!< 0x00000001 */

+#define HRTIM_CR1_MUDIS               HRTIM_CR1_MUDIS_Msk                      /*!< Master update disable*/

+#define HRTIM_CR1_TAUDIS_Pos          (1U)

+#define HRTIM_CR1_TAUDIS_Msk          (0x1UL << HRTIM_CR1_TAUDIS_Pos)          /*!< 0x00000002 */

+#define HRTIM_CR1_TAUDIS              HRTIM_CR1_TAUDIS_Msk                     /*!< Timer A update disable*/

+#define HRTIM_CR1_TBUDIS_Pos          (2U)

+#define HRTIM_CR1_TBUDIS_Msk          (0x1UL << HRTIM_CR1_TBUDIS_Pos)          /*!< 0x00000004 */

+#define HRTIM_CR1_TBUDIS              HRTIM_CR1_TBUDIS_Msk                     /*!< Timer B update disable*/

+#define HRTIM_CR1_TCUDIS_Pos          (3U)

+#define HRTIM_CR1_TCUDIS_Msk          (0x1UL << HRTIM_CR1_TCUDIS_Pos)          /*!< 0x00000008 */

+#define HRTIM_CR1_TCUDIS              HRTIM_CR1_TCUDIS_Msk                     /*!< Timer C update disable*/

+#define HRTIM_CR1_TDUDIS_Pos          (4U)

+#define HRTIM_CR1_TDUDIS_Msk          (0x1UL << HRTIM_CR1_TDUDIS_Pos)          /*!< 0x00000010 */

+#define HRTIM_CR1_TDUDIS              HRTIM_CR1_TDUDIS_Msk                     /*!< Timer D update disable*/

+#define HRTIM_CR1_TEUDIS_Pos          (5U)

+#define HRTIM_CR1_TEUDIS_Msk          (0x1UL << HRTIM_CR1_TEUDIS_Pos)          /*!< 0x00000020 */

+#define HRTIM_CR1_TEUDIS              HRTIM_CR1_TEUDIS_Msk                     /*!< Timer E update disable*/

+#define HRTIM_CR1_ADC1USRC_Pos        (16U)

+#define HRTIM_CR1_ADC1USRC_Msk        (0x7UL << HRTIM_CR1_ADC1USRC_Pos)        /*!< 0x00070000 */

+#define HRTIM_CR1_ADC1USRC            HRTIM_CR1_ADC1USRC_Msk                   /*!< ADC Trigger 1 update source */

+#define HRTIM_CR1_ADC1USRC_0          (0x1UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00010000 */

+#define HRTIM_CR1_ADC1USRC_1          (0x2UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00020000 */

+#define HRTIM_CR1_ADC1USRC_2          (0x4UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00040000 */

+#define HRTIM_CR1_ADC2USRC_Pos        (19U)

+#define HRTIM_CR1_ADC2USRC_Msk        (0x7UL << HRTIM_CR1_ADC2USRC_Pos)        /*!< 0x00380000 */

+#define HRTIM_CR1_ADC2USRC            HRTIM_CR1_ADC2USRC_Msk                   /*!< ADC Trigger 2 update source */

+#define HRTIM_CR1_ADC2USRC_0          (0x1UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00080000 */

+#define HRTIM_CR1_ADC2USRC_1          (0x2UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00100000 */

+#define HRTIM_CR1_ADC2USRC_2          (0x4UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00200000 */

+#define HRTIM_CR1_ADC3USRC_Pos        (22U)

+#define HRTIM_CR1_ADC3USRC_Msk        (0x7UL << HRTIM_CR1_ADC3USRC_Pos)        /*!< 0x01C00000 */

+#define HRTIM_CR1_ADC3USRC            HRTIM_CR1_ADC3USRC_Msk                   /*!< ADC Trigger 3 update source */

+#define HRTIM_CR1_ADC3USRC_0          (0x1UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00400000 */

+#define HRTIM_CR1_ADC3USRC_1          (0x2UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00800000 */

+#define HRTIM_CR1_ADC3USRC_2          (0x4UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x01000000 */

+#define HRTIM_CR1_ADC4USRC_Pos        (25U)

+#define HRTIM_CR1_ADC4USRC_Msk        (0x7UL << HRTIM_CR1_ADC4USRC_Pos)        /*!< 0x0E000000 */

+#define HRTIM_CR1_ADC4USRC            HRTIM_CR1_ADC4USRC_Msk                   /*!< ADC Trigger 4 update source */

+#define HRTIM_CR1_ADC4USRC_0          (0x1UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x02000000 */

+#define HRTIM_CR1_ADC4USRC_1          (0x2UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x04000000 */

+#define HRTIM_CR1_ADC4USRC_2          (0x0UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x0800000 */

+

+/**** Bit definition for Common HRTIM Timer control register 2 ****************/

+#define HRTIM_CR2_MSWU_Pos            (0U)

+#define HRTIM_CR2_MSWU_Msk            (0x1UL << HRTIM_CR2_MSWU_Pos)            /*!< 0x00000001 */

+#define HRTIM_CR2_MSWU                HRTIM_CR2_MSWU_Msk                       /*!< Master software update */

+#define HRTIM_CR2_TASWU_Pos           (1U)

+#define HRTIM_CR2_TASWU_Msk           (0x1UL << HRTIM_CR2_TASWU_Pos)           /*!< 0x00000002 */

+#define HRTIM_CR2_TASWU               HRTIM_CR2_TASWU_Msk                      /*!< Timer A software update */

+#define HRTIM_CR2_TBSWU_Pos           (2U)

+#define HRTIM_CR2_TBSWU_Msk           (0x1UL << HRTIM_CR2_TBSWU_Pos)           /*!< 0x00000004 */

+#define HRTIM_CR2_TBSWU               HRTIM_CR2_TBSWU_Msk                      /*!< Timer B software update */

+#define HRTIM_CR2_TCSWU_Pos           (3U)

+#define HRTIM_CR2_TCSWU_Msk           (0x1UL << HRTIM_CR2_TCSWU_Pos)           /*!< 0x00000008 */

+#define HRTIM_CR2_TCSWU               HRTIM_CR2_TCSWU_Msk                      /*!< Timer C software update */

+#define HRTIM_CR2_TDSWU_Pos           (4U)

+#define HRTIM_CR2_TDSWU_Msk           (0x1UL << HRTIM_CR2_TDSWU_Pos)           /*!< 0x00000010 */

+#define HRTIM_CR2_TDSWU               HRTIM_CR2_TDSWU_Msk                      /*!< Timer D software update */

+#define HRTIM_CR2_TESWU_Pos           (5U)

+#define HRTIM_CR2_TESWU_Msk           (0x1UL << HRTIM_CR2_TESWU_Pos)           /*!< 0x00000020 */

+#define HRTIM_CR2_TESWU               HRTIM_CR2_TESWU_Msk                      /*!< Timer E software update */

+#define HRTIM_CR2_MRST_Pos            (8U)

+#define HRTIM_CR2_MRST_Msk            (0x1UL << HRTIM_CR2_MRST_Pos)            /*!< 0x00000100 */

+#define HRTIM_CR2_MRST                HRTIM_CR2_MRST_Msk                       /*!< Master count software reset */

+#define HRTIM_CR2_TARST_Pos           (9U)

+#define HRTIM_CR2_TARST_Msk           (0x1UL << HRTIM_CR2_TARST_Pos)           /*!< 0x00000200 */

+#define HRTIM_CR2_TARST               HRTIM_CR2_TARST_Msk                      /*!< Timer A count software reset */

+#define HRTIM_CR2_TBRST_Pos           (10U)

+#define HRTIM_CR2_TBRST_Msk           (0x1UL << HRTIM_CR2_TBRST_Pos)           /*!< 0x00000400 */

+#define HRTIM_CR2_TBRST               HRTIM_CR2_TBRST_Msk                      /*!< Timer B count software reset */

+#define HRTIM_CR2_TCRST_Pos           (11U)

+#define HRTIM_CR2_TCRST_Msk           (0x1UL << HRTIM_CR2_TCRST_Pos)           /*!< 0x00000800 */

+#define HRTIM_CR2_TCRST               HRTIM_CR2_TCRST_Msk                      /*!< Timer C count software reset */

+#define HRTIM_CR2_TDRST_Pos           (12U)

+#define HRTIM_CR2_TDRST_Msk           (0x1UL << HRTIM_CR2_TDRST_Pos)           /*!< 0x00001000 */

+#define HRTIM_CR2_TDRST               HRTIM_CR2_TDRST_Msk                      /*!< Timer D count software reset */

+#define HRTIM_CR2_TERST_Pos           (13U)

+#define HRTIM_CR2_TERST_Msk           (0x1UL << HRTIM_CR2_TERST_Pos)           /*!< 0x00002000 */

+#define HRTIM_CR2_TERST               HRTIM_CR2_TERST_Msk                      /*!< Timer E count software reset */

+

+/**** Bit definition for Common HRTIM Timer interrupt status register *********/

+#define HRTIM_ISR_FLT1_Pos            (0U)

+#define HRTIM_ISR_FLT1_Msk            (0x1UL << HRTIM_ISR_FLT1_Pos)            /*!< 0x00000001 */

+#define HRTIM_ISR_FLT1                HRTIM_ISR_FLT1_Msk                       /*!< Fault 1 interrupt flag */

+#define HRTIM_ISR_FLT2_Pos            (1U)

+#define HRTIM_ISR_FLT2_Msk            (0x1UL << HRTIM_ISR_FLT2_Pos)            /*!< 0x00000002 */

+#define HRTIM_ISR_FLT2                HRTIM_ISR_FLT2_Msk                       /*!< Fault 2 interrupt flag */

+#define HRTIM_ISR_FLT3_Pos            (2U)

+#define HRTIM_ISR_FLT3_Msk            (0x1UL << HRTIM_ISR_FLT3_Pos)            /*!< 0x00000004 */

+#define HRTIM_ISR_FLT3                HRTIM_ISR_FLT3_Msk                       /*!< Fault 3 interrupt flag */

+#define HRTIM_ISR_FLT4_Pos            (3U)

+#define HRTIM_ISR_FLT4_Msk            (0x1UL << HRTIM_ISR_FLT4_Pos)            /*!< 0x00000008 */

+#define HRTIM_ISR_FLT4                HRTIM_ISR_FLT4_Msk                       /*!< Fault 4 interrupt flag */

+#define HRTIM_ISR_FLT5_Pos            (4U)

+#define HRTIM_ISR_FLT5_Msk            (0x1UL << HRTIM_ISR_FLT5_Pos)            /*!< 0x00000010 */

+#define HRTIM_ISR_FLT5                HRTIM_ISR_FLT5_Msk                       /*!< Fault 5 interrupt flag */

+#define HRTIM_ISR_SYSFLT_Pos          (5U)

+#define HRTIM_ISR_SYSFLT_Msk          (0x1UL << HRTIM_ISR_SYSFLT_Pos)          /*!< 0x00000020 */

+#define HRTIM_ISR_SYSFLT              HRTIM_ISR_SYSFLT_Msk                     /*!< System Fault interrupt flag */

+#define HRTIM_ISR_BMPER_Pos           (17U)

+#define HRTIM_ISR_BMPER_Msk           (0x1UL << HRTIM_ISR_BMPER_Pos)           /*!< 0x00020000 */

+#define HRTIM_ISR_BMPER               HRTIM_ISR_BMPER_Msk                      /*!<  Burst mode period interrupt flag */

+

+/**** Bit definition for Common HRTIM Timer interrupt clear register **********/

+#define HRTIM_ICR_FLT1C_Pos           (0U)

+#define HRTIM_ICR_FLT1C_Msk           (0x1UL << HRTIM_ICR_FLT1C_Pos)           /*!< 0x00000001 */

+#define HRTIM_ICR_FLT1C               HRTIM_ICR_FLT1C_Msk                      /*!< Fault 1 interrupt flag clear */

+#define HRTIM_ICR_FLT2C_Pos           (1U)

+#define HRTIM_ICR_FLT2C_Msk           (0x1UL << HRTIM_ICR_FLT2C_Pos)           /*!< 0x00000002 */

+#define HRTIM_ICR_FLT2C               HRTIM_ICR_FLT2C_Msk                      /*!< Fault 2 interrupt flag clear */

+#define HRTIM_ICR_FLT3C_Pos           (2U)

+#define HRTIM_ICR_FLT3C_Msk           (0x1UL << HRTIM_ICR_FLT3C_Pos)           /*!< 0x00000004 */

+#define HRTIM_ICR_FLT3C               HRTIM_ICR_FLT3C_Msk                      /*!< Fault 3 interrupt flag clear */

+#define HRTIM_ICR_FLT4C_Pos           (3U)

+#define HRTIM_ICR_FLT4C_Msk           (0x1UL << HRTIM_ICR_FLT4C_Pos)           /*!< 0x00000008 */

+#define HRTIM_ICR_FLT4C               HRTIM_ICR_FLT4C_Msk                      /*!< Fault 4 interrupt flag clear */

+#define HRTIM_ICR_FLT5C_Pos           (4U)

+#define HRTIM_ICR_FLT5C_Msk           (0x1UL << HRTIM_ICR_FLT5C_Pos)           /*!< 0x00000010 */

+#define HRTIM_ICR_FLT5C               HRTIM_ICR_FLT5C_Msk                      /*!< Fault 5 interrupt flag clear */

+#define HRTIM_ICR_SYSFLTC_Pos         (5U)

+#define HRTIM_ICR_SYSFLTC_Msk         (0x1UL << HRTIM_ICR_SYSFLTC_Pos)         /*!< 0x00000020 */

+#define HRTIM_ICR_SYSFLTC             HRTIM_ICR_SYSFLTC_Msk                    /*!< System Fault interrupt flag clear */

+#define HRTIM_ICR_BMPERC_Pos          (17U)

+#define HRTIM_ICR_BMPERC_Msk          (0x1UL << HRTIM_ICR_BMPERC_Pos)          /*!< 0x00020000 */

+#define HRTIM_ICR_BMPERC              HRTIM_ICR_BMPERC_Msk                     /*!<  Burst mode period interrupt flag clear */

+

+/**** Bit definition for Common HRTIM Timer interrupt enable register *********/

+#define HRTIM_IER_FLT1_Pos            (0U)

+#define HRTIM_IER_FLT1_Msk            (0x1UL << HRTIM_IER_FLT1_Pos)            /*!< 0x00000001 */

+#define HRTIM_IER_FLT1                HRTIM_IER_FLT1_Msk                       /*!< Fault 1 interrupt enable */

+#define HRTIM_IER_FLT2_Pos            (1U)

+#define HRTIM_IER_FLT2_Msk            (0x1UL << HRTIM_IER_FLT2_Pos)            /*!< 0x00000002 */

+#define HRTIM_IER_FLT2                HRTIM_IER_FLT2_Msk                       /*!< Fault 2 interrupt enable */

+#define HRTIM_IER_FLT3_Pos            (2U)

+#define HRTIM_IER_FLT3_Msk            (0x1UL << HRTIM_IER_FLT3_Pos)            /*!< 0x00000004 */

+#define HRTIM_IER_FLT3                HRTIM_IER_FLT3_Msk                       /*!< Fault 3 interrupt enable */

+#define HRTIM_IER_FLT4_Pos            (3U)

+#define HRTIM_IER_FLT4_Msk            (0x1UL << HRTIM_IER_FLT4_Pos)            /*!< 0x00000008 */

+#define HRTIM_IER_FLT4                HRTIM_IER_FLT4_Msk                       /*!< Fault 4 interrupt enable */

+#define HRTIM_IER_FLT5_Pos            (4U)

+#define HRTIM_IER_FLT5_Msk            (0x1UL << HRTIM_IER_FLT5_Pos)            /*!< 0x00000010 */

+#define HRTIM_IER_FLT5                HRTIM_IER_FLT5_Msk                       /*!< Fault 5 interrupt enable */

+#define HRTIM_IER_SYSFLT_Pos          (5U)

+#define HRTIM_IER_SYSFLT_Msk          (0x1UL << HRTIM_IER_SYSFLT_Pos)          /*!< 0x00000020 */

+#define HRTIM_IER_SYSFLT              HRTIM_IER_SYSFLT_Msk                     /*!< System Fault interrupt enable */

+#define HRTIM_IER_BMPER_Pos           (17U)

+#define HRTIM_IER_BMPER_Msk           (0x1UL << HRTIM_IER_BMPER_Pos)           /*!< 0x00020000 */

+#define HRTIM_IER_BMPER               HRTIM_IER_BMPER_Msk                      /*!<  Burst mode period interrupt enable */

+

+/**** Bit definition for Common HRTIM Timer output enable register ************/

+#define HRTIM_OENR_TA1OEN_Pos         (0U)

+#define HRTIM_OENR_TA1OEN_Msk         (0x1UL << HRTIM_OENR_TA1OEN_Pos)         /*!< 0x00000001 */

+#define HRTIM_OENR_TA1OEN             HRTIM_OENR_TA1OEN_Msk                    /*!< Timer A Output 1 enable */

+#define HRTIM_OENR_TA2OEN_Pos         (1U)

+#define HRTIM_OENR_TA2OEN_Msk         (0x1UL << HRTIM_OENR_TA2OEN_Pos)         /*!< 0x00000002 */

+#define HRTIM_OENR_TA2OEN             HRTIM_OENR_TA2OEN_Msk                    /*!< Timer A Output 2 enable */

+#define HRTIM_OENR_TB1OEN_Pos         (2U)

+#define HRTIM_OENR_TB1OEN_Msk         (0x1UL << HRTIM_OENR_TB1OEN_Pos)         /*!< 0x00000004 */

+#define HRTIM_OENR_TB1OEN             HRTIM_OENR_TB1OEN_Msk                    /*!< Timer B Output 1 enable */

+#define HRTIM_OENR_TB2OEN_Pos         (3U)

+#define HRTIM_OENR_TB2OEN_Msk         (0x1UL << HRTIM_OENR_TB2OEN_Pos)         /*!< 0x00000008 */

+#define HRTIM_OENR_TB2OEN             HRTIM_OENR_TB2OEN_Msk                    /*!< Timer B Output 2 enable */

+#define HRTIM_OENR_TC1OEN_Pos         (4U)

+#define HRTIM_OENR_TC1OEN_Msk         (0x1UL << HRTIM_OENR_TC1OEN_Pos)         /*!< 0x00000010 */

+#define HRTIM_OENR_TC1OEN             HRTIM_OENR_TC1OEN_Msk                    /*!< Timer C Output 1 enable */

+#define HRTIM_OENR_TC2OEN_Pos         (5U)

+#define HRTIM_OENR_TC2OEN_Msk         (0x1UL << HRTIM_OENR_TC2OEN_Pos)         /*!< 0x00000020 */

+#define HRTIM_OENR_TC2OEN             HRTIM_OENR_TC2OEN_Msk                    /*!< Timer C Output 2 enable */

+#define HRTIM_OENR_TD1OEN_Pos         (6U)

+#define HRTIM_OENR_TD1OEN_Msk         (0x1UL << HRTIM_OENR_TD1OEN_Pos)         /*!< 0x00000040 */

+#define HRTIM_OENR_TD1OEN             HRTIM_OENR_TD1OEN_Msk                    /*!< Timer D Output 1 enable */

+#define HRTIM_OENR_TD2OEN_Pos         (7U)

+#define HRTIM_OENR_TD2OEN_Msk         (0x1UL << HRTIM_OENR_TD2OEN_Pos)         /*!< 0x00000080 */

+#define HRTIM_OENR_TD2OEN             HRTIM_OENR_TD2OEN_Msk                    /*!< Timer D Output 2 enable */

+#define HRTIM_OENR_TE1OEN_Pos         (8U)

+#define HRTIM_OENR_TE1OEN_Msk         (0x1UL << HRTIM_OENR_TE1OEN_Pos)         /*!< 0x00000100 */

+#define HRTIM_OENR_TE1OEN             HRTIM_OENR_TE1OEN_Msk                    /*!< Timer E Output 1 enable */

+#define HRTIM_OENR_TE2OEN_Pos         (9U)

+#define HRTIM_OENR_TE2OEN_Msk         (0x1UL << HRTIM_OENR_TE2OEN_Pos)         /*!< 0x00000200 */

+#define HRTIM_OENR_TE2OEN             HRTIM_OENR_TE2OEN_Msk                    /*!< Timer E Output 2 enable */

+

+/**** Bit definition for Common HRTIM Timer output disable register ***********/

+#define HRTIM_ODISR_TA1ODIS_Pos       (0U)

+#define HRTIM_ODISR_TA1ODIS_Msk       (0x1UL << HRTIM_ODISR_TA1ODIS_Pos)       /*!< 0x00000001 */

+#define HRTIM_ODISR_TA1ODIS           HRTIM_ODISR_TA1ODIS_Msk                  /*!< Timer A Output 1 disable */

+#define HRTIM_ODISR_TA2ODIS_Pos       (1U)

+#define HRTIM_ODISR_TA2ODIS_Msk       (0x1UL << HRTIM_ODISR_TA2ODIS_Pos)       /*!< 0x00000002 */

+#define HRTIM_ODISR_TA2ODIS           HRTIM_ODISR_TA2ODIS_Msk                  /*!< Timer A Output 2 disable */

+#define HRTIM_ODISR_TB1ODIS_Pos       (2U)

+#define HRTIM_ODISR_TB1ODIS_Msk       (0x1UL << HRTIM_ODISR_TB1ODIS_Pos)       /*!< 0x00000004 */

+#define HRTIM_ODISR_TB1ODIS           HRTIM_ODISR_TB1ODIS_Msk                  /*!< Timer B Output 1 disable */

+#define HRTIM_ODISR_TB2ODIS_Pos       (3U)

+#define HRTIM_ODISR_TB2ODIS_Msk       (0x1UL << HRTIM_ODISR_TB2ODIS_Pos)       /*!< 0x00000008 */

+#define HRTIM_ODISR_TB2ODIS           HRTIM_ODISR_TB2ODIS_Msk                  /*!< Timer B Output 2 disable */

+#define HRTIM_ODISR_TC1ODIS_Pos       (4U)

+#define HRTIM_ODISR_TC1ODIS_Msk       (0x1UL << HRTIM_ODISR_TC1ODIS_Pos)       /*!< 0x00000010 */

+#define HRTIM_ODISR_TC1ODIS           HRTIM_ODISR_TC1ODIS_Msk                  /*!< Timer C Output 1 disable */

+#define HRTIM_ODISR_TC2ODIS_Pos       (5U)

+#define HRTIM_ODISR_TC2ODIS_Msk       (0x1UL << HRTIM_ODISR_TC2ODIS_Pos)       /*!< 0x00000020 */

+#define HRTIM_ODISR_TC2ODIS           HRTIM_ODISR_TC2ODIS_Msk                  /*!< Timer C Output 2 disable */

+#define HRTIM_ODISR_TD1ODIS_Pos       (6U)

+#define HRTIM_ODISR_TD1ODIS_Msk       (0x1UL << HRTIM_ODISR_TD1ODIS_Pos)       /*!< 0x00000040 */

+#define HRTIM_ODISR_TD1ODIS           HRTIM_ODISR_TD1ODIS_Msk                  /*!< Timer D Output 1 disable */

+#define HRTIM_ODISR_TD2ODIS_Pos       (7U)

+#define HRTIM_ODISR_TD2ODIS_Msk       (0x1UL << HRTIM_ODISR_TD2ODIS_Pos)       /*!< 0x00000080 */

+#define HRTIM_ODISR_TD2ODIS           HRTIM_ODISR_TD2ODIS_Msk                  /*!< Timer D Output 2 disable */

+#define HRTIM_ODISR_TE1ODIS_Pos       (8U)

+#define HRTIM_ODISR_TE1ODIS_Msk       (0x1UL << HRTIM_ODISR_TE1ODIS_Pos)       /*!< 0x00000100 */

+#define HRTIM_ODISR_TE1ODIS           HRTIM_ODISR_TE1ODIS_Msk                  /*!< Timer E Output 1 disable */

+#define HRTIM_ODISR_TE2ODIS_Pos       (9U)

+#define HRTIM_ODISR_TE2ODIS_Msk       (0x1UL << HRTIM_ODISR_TE2ODIS_Pos)       /*!< 0x00000200 */

+#define HRTIM_ODISR_TE2ODIS           HRTIM_ODISR_TE2ODIS_Msk                  /*!< Timer E Output 2 disable */

+

+/**** Bit definition for Common HRTIM Timer output disable status register *****/

+#define HRTIM_ODSR_TA1ODS_Pos         (0U)

+#define HRTIM_ODSR_TA1ODS_Msk         (0x1UL << HRTIM_ODSR_TA1ODS_Pos)         /*!< 0x00000001 */

+#define HRTIM_ODSR_TA1ODS             HRTIM_ODSR_TA1ODS_Msk                    /*!< Timer A Output 1 disable status */

+#define HRTIM_ODSR_TA2ODS_Pos         (1U)

+#define HRTIM_ODSR_TA2ODS_Msk         (0x1UL << HRTIM_ODSR_TA2ODS_Pos)         /*!< 0x00000002 */

+#define HRTIM_ODSR_TA2ODS             HRTIM_ODSR_TA2ODS_Msk                    /*!< Timer A Output 2 disable status */

+#define HRTIM_ODSR_TB1ODS_Pos         (2U)

+#define HRTIM_ODSR_TB1ODS_Msk         (0x1UL << HRTIM_ODSR_TB1ODS_Pos)         /*!< 0x00000004 */

+#define HRTIM_ODSR_TB1ODS             HRTIM_ODSR_TB1ODS_Msk                    /*!< Timer B Output 1 disable status */

+#define HRTIM_ODSR_TB2ODS_Pos         (3U)

+#define HRTIM_ODSR_TB2ODS_Msk         (0x1UL << HRTIM_ODSR_TB2ODS_Pos)         /*!< 0x00000008 */

+#define HRTIM_ODSR_TB2ODS             HRTIM_ODSR_TB2ODS_Msk                    /*!< Timer B Output 2 disable status */

+#define HRTIM_ODSR_TC1ODS_Pos         (4U)

+#define HRTIM_ODSR_TC1ODS_Msk         (0x1UL << HRTIM_ODSR_TC1ODS_Pos)         /*!< 0x00000010 */

+#define HRTIM_ODSR_TC1ODS             HRTIM_ODSR_TC1ODS_Msk                    /*!< Timer C Output 1 disable status */

+#define HRTIM_ODSR_TC2ODS_Pos         (5U)

+#define HRTIM_ODSR_TC2ODS_Msk         (0x1UL << HRTIM_ODSR_TC2ODS_Pos)         /*!< 0x00000020 */

+#define HRTIM_ODSR_TC2ODS             HRTIM_ODSR_TC2ODS_Msk                    /*!< Timer C Output 2 disable status */

+#define HRTIM_ODSR_TD1ODS_Pos         (6U)

+#define HRTIM_ODSR_TD1ODS_Msk         (0x1UL << HRTIM_ODSR_TD1ODS_Pos)         /*!< 0x00000040 */

+#define HRTIM_ODSR_TD1ODS             HRTIM_ODSR_TD1ODS_Msk                    /*!< Timer D Output 1 disable status */

+#define HRTIM_ODSR_TD2ODS_Pos         (7U)

+#define HRTIM_ODSR_TD2ODS_Msk         (0x1UL << HRTIM_ODSR_TD2ODS_Pos)         /*!< 0x00000080 */

+#define HRTIM_ODSR_TD2ODS             HRTIM_ODSR_TD2ODS_Msk                    /*!< Timer D Output 2 disable status */

+#define HRTIM_ODSR_TE1ODS_Pos         (8U)

+#define HRTIM_ODSR_TE1ODS_Msk         (0x1UL << HRTIM_ODSR_TE1ODS_Pos)         /*!< 0x00000100 */

+#define HRTIM_ODSR_TE1ODS             HRTIM_ODSR_TE1ODS_Msk                    /*!< Timer E Output 1 disable status */

+#define HRTIM_ODSR_TE2ODS_Pos         (9U)

+#define HRTIM_ODSR_TE2ODS_Msk         (0x1UL << HRTIM_ODSR_TE2ODS_Pos)         /*!< 0x00000200 */

+#define HRTIM_ODSR_TE2ODS             HRTIM_ODSR_TE2ODS_Msk                    /*!< Timer E Output 2 disable status */

+

+/**** Bit definition for Common HRTIM Timer Burst mode control register ********/

+#define HRTIM_BMCR_BME_Pos            (0U)

+#define HRTIM_BMCR_BME_Msk            (0x1UL << HRTIM_BMCR_BME_Pos)            /*!< 0x00000001 */

+#define HRTIM_BMCR_BME                HRTIM_BMCR_BME_Msk                       /*!< Burst mode enbale */

+#define HRTIM_BMCR_BMOM_Pos           (1U)

+#define HRTIM_BMCR_BMOM_Msk           (0x1UL << HRTIM_BMCR_BMOM_Pos)           /*!< 0x00000002 */

+#define HRTIM_BMCR_BMOM               HRTIM_BMCR_BMOM_Msk                      /*!< Burst mode operating mode */

+#define HRTIM_BMCR_BMCLK_Pos          (2U)

+#define HRTIM_BMCR_BMCLK_Msk          (0xFUL << HRTIM_BMCR_BMCLK_Pos)          /*!< 0x0000003C */

+#define HRTIM_BMCR_BMCLK              HRTIM_BMCR_BMCLK_Msk                     /*!< Burst mode clock source */

+#define HRTIM_BMCR_BMCLK_0            (0x1UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000004 */

+#define HRTIM_BMCR_BMCLK_1            (0x2UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000008 */

+#define HRTIM_BMCR_BMCLK_2            (0x4UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000010 */

+#define HRTIM_BMCR_BMCLK_3            (0x8UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000020 */

+#define HRTIM_BMCR_BMPRSC_Pos         (6U)

+#define HRTIM_BMCR_BMPRSC_Msk         (0xFUL << HRTIM_BMCR_BMPRSC_Pos)         /*!< 0x000003C0 */

+#define HRTIM_BMCR_BMPRSC             HRTIM_BMCR_BMPRSC_Msk                    /*!< Burst mode prescaler */

+#define HRTIM_BMCR_BMPRSC_0           (0x1UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000040 */

+#define HRTIM_BMCR_BMPRSC_1           (0x2UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000080 */

+#define HRTIM_BMCR_BMPRSC_2           (0x4UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000100 */

+#define HRTIM_BMCR_BMPRSC_3           (0x8UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000200 */

+#define HRTIM_BMCR_BMPREN_Pos         (10U)

+#define HRTIM_BMCR_BMPREN_Msk         (0x1UL << HRTIM_BMCR_BMPREN_Pos)         /*!< 0x00000400 */

+#define HRTIM_BMCR_BMPREN             HRTIM_BMCR_BMPREN_Msk                    /*!< Burst mode Preload bit */

+#define HRTIM_BMCR_MTBM_Pos           (16U)

+#define HRTIM_BMCR_MTBM_Msk           (0x1UL << HRTIM_BMCR_MTBM_Pos)           /*!< 0x00010000 */

+#define HRTIM_BMCR_MTBM               HRTIM_BMCR_MTBM_Msk                      /*!< Master Timer Burst mode */

+#define HRTIM_BMCR_TABM_Pos           (17U)

+#define HRTIM_BMCR_TABM_Msk           (0x1UL << HRTIM_BMCR_TABM_Pos)           /*!< 0x00020000 */

+#define HRTIM_BMCR_TABM               HRTIM_BMCR_TABM_Msk                      /*!< Timer A Burst mode */

+#define HRTIM_BMCR_TBBM_Pos           (18U)

+#define HRTIM_BMCR_TBBM_Msk           (0x1UL << HRTIM_BMCR_TBBM_Pos)           /*!< 0x00040000 */

+#define HRTIM_BMCR_TBBM               HRTIM_BMCR_TBBM_Msk                      /*!< Timer B Burst mode */

+#define HRTIM_BMCR_TCBM_Pos           (19U)

+#define HRTIM_BMCR_TCBM_Msk           (0x1UL << HRTIM_BMCR_TCBM_Pos)           /*!< 0x00080000 */

+#define HRTIM_BMCR_TCBM               HRTIM_BMCR_TCBM_Msk                      /*!< Timer C Burst mode */

+#define HRTIM_BMCR_TDBM_Pos           (20U)

+#define HRTIM_BMCR_TDBM_Msk           (0x1UL << HRTIM_BMCR_TDBM_Pos)           /*!< 0x00100000 */

+#define HRTIM_BMCR_TDBM               HRTIM_BMCR_TDBM_Msk                      /*!< Timer D Burst mode */

+#define HRTIM_BMCR_TEBM_Pos           (21U)

+#define HRTIM_BMCR_TEBM_Msk           (0x1UL << HRTIM_BMCR_TEBM_Pos)           /*!< 0x00200000 */

+#define HRTIM_BMCR_TEBM               HRTIM_BMCR_TEBM_Msk                      /*!< Timer E Burst mode */

+#define HRTIM_BMCR_BMSTAT_Pos         (31U)

+#define HRTIM_BMCR_BMSTAT_Msk         (0x1UL << HRTIM_BMCR_BMSTAT_Pos)         /*!< 0x80000000 */

+#define HRTIM_BMCR_BMSTAT             HRTIM_BMCR_BMSTAT_Msk                    /*!< Burst mode status */

+

+/**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/

+#define HRTIM_BMTRGR_SW_Pos           (0U)

+#define HRTIM_BMTRGR_SW_Msk           (0x1UL << HRTIM_BMTRGR_SW_Pos)           /*!< 0x00000001 */

+#define HRTIM_BMTRGR_SW               HRTIM_BMTRGR_SW_Msk                      /*!< Software start */

+#define HRTIM_BMTRGR_MSTRST_Pos       (1U)

+#define HRTIM_BMTRGR_MSTRST_Msk       (0x1UL << HRTIM_BMTRGR_MSTRST_Pos)       /*!< 0x00000002 */

+#define HRTIM_BMTRGR_MSTRST           HRTIM_BMTRGR_MSTRST_Msk                  /*!<  Master reset */

+#define HRTIM_BMTRGR_MSTREP_Pos       (2U)

+#define HRTIM_BMTRGR_MSTREP_Msk       (0x1UL << HRTIM_BMTRGR_MSTREP_Pos)       /*!< 0x00000004 */

+#define HRTIM_BMTRGR_MSTREP           HRTIM_BMTRGR_MSTREP_Msk                  /*!<  Master repetition */

+#define HRTIM_BMTRGR_MSTCMP1_Pos      (3U)

+#define HRTIM_BMTRGR_MSTCMP1_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos)      /*!< 0x00000008 */

+#define HRTIM_BMTRGR_MSTCMP1          HRTIM_BMTRGR_MSTCMP1_Msk                 /*!<  Master compare 1 */

+#define HRTIM_BMTRGR_MSTCMP2_Pos      (4U)

+#define HRTIM_BMTRGR_MSTCMP2_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos)      /*!< 0x00000010 */

+#define HRTIM_BMTRGR_MSTCMP2          HRTIM_BMTRGR_MSTCMP2_Msk                 /*!< Master compare 2  */

+#define HRTIM_BMTRGR_MSTCMP3_Pos      (5U)

+#define HRTIM_BMTRGR_MSTCMP3_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos)      /*!< 0x00000020 */

+#define HRTIM_BMTRGR_MSTCMP3          HRTIM_BMTRGR_MSTCMP3_Msk                 /*!< Master compare 3 */

+#define HRTIM_BMTRGR_MSTCMP4_Pos      (6U)

+#define HRTIM_BMTRGR_MSTCMP4_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos)      /*!< 0x00000040 */

+#define HRTIM_BMTRGR_MSTCMP4          HRTIM_BMTRGR_MSTCMP4_Msk                 /*!< Master compare 4 */

+#define HRTIM_BMTRGR_TARST_Pos        (7U)

+#define HRTIM_BMTRGR_TARST_Msk        (0x1UL << HRTIM_BMTRGR_TARST_Pos)        /*!< 0x00000080 */

+#define HRTIM_BMTRGR_TARST            HRTIM_BMTRGR_TARST_Msk                   /*!< Timer A reset  */

+#define HRTIM_BMTRGR_TAREP_Pos        (8U)

+#define HRTIM_BMTRGR_TAREP_Msk        (0x1UL << HRTIM_BMTRGR_TAREP_Pos)        /*!< 0x00000100 */

+#define HRTIM_BMTRGR_TAREP            HRTIM_BMTRGR_TAREP_Msk                   /*!< Timer A repetition  */

+#define HRTIM_BMTRGR_TACMP1_Pos       (9U)

+#define HRTIM_BMTRGR_TACMP1_Msk       (0x1UL << HRTIM_BMTRGR_TACMP1_Pos)       /*!< 0x00000200 */

+#define HRTIM_BMTRGR_TACMP1           HRTIM_BMTRGR_TACMP1_Msk                  /*!< Timer A compare 1  */

+#define HRTIM_BMTRGR_TACMP2_Pos       (10U)

+#define HRTIM_BMTRGR_TACMP2_Msk       (0x1UL << HRTIM_BMTRGR_TACMP2_Pos)       /*!< 0x00000400 */

+#define HRTIM_BMTRGR_TACMP2           HRTIM_BMTRGR_TACMP2_Msk                  /*!< Timer A compare 2  */

+#define HRTIM_BMTRGR_TBRST_Pos        (11U)

+#define HRTIM_BMTRGR_TBRST_Msk        (0x1UL << HRTIM_BMTRGR_TBRST_Pos)        /*!< 0x00000800 */

+#define HRTIM_BMTRGR_TBRST            HRTIM_BMTRGR_TBRST_Msk                   /*!< Timer B reset  */

+#define HRTIM_BMTRGR_TBREP_Pos        (12U)

+#define HRTIM_BMTRGR_TBREP_Msk        (0x1UL << HRTIM_BMTRGR_TBREP_Pos)        /*!< 0x00001000 */

+#define HRTIM_BMTRGR_TBREP            HRTIM_BMTRGR_TBREP_Msk                   /*!< Timer B repetition  */

+#define HRTIM_BMTRGR_TBCMP1_Pos       (13U)

+#define HRTIM_BMTRGR_TBCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos)       /*!< 0x00002000 */

+#define HRTIM_BMTRGR_TBCMP1           HRTIM_BMTRGR_TBCMP1_Msk                  /*!< Timer B compare 1 */

+#define HRTIM_BMTRGR_TBCMP2_Pos       (14U)

+#define HRTIM_BMTRGR_TBCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos)       /*!< 0x00004000 */

+#define HRTIM_BMTRGR_TBCMP2           HRTIM_BMTRGR_TBCMP2_Msk                  /*!< Timer B compare 2 */

+#define HRTIM_BMTRGR_TCRST_Pos        (15U)

+#define HRTIM_BMTRGR_TCRST_Msk        (0x1UL << HRTIM_BMTRGR_TCRST_Pos)        /*!< 0x00008000 */

+#define HRTIM_BMTRGR_TCRST            HRTIM_BMTRGR_TCRST_Msk                   /*!< Timer C reset  */

+#define HRTIM_BMTRGR_TCREP_Pos        (16U)

+#define HRTIM_BMTRGR_TCREP_Msk        (0x1UL << HRTIM_BMTRGR_TCREP_Pos)        /*!< 0x00010000 */

+#define HRTIM_BMTRGR_TCREP            HRTIM_BMTRGR_TCREP_Msk                   /*!< Timer C repetition */

+#define HRTIM_BMTRGR_TCCMP1_Pos       (17U)

+#define HRTIM_BMTRGR_TCCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos)       /*!< 0x00020000 */

+#define HRTIM_BMTRGR_TCCMP1           HRTIM_BMTRGR_TCCMP1_Msk                  /*!< Timer C compare 1 */

+#define HRTIM_BMTRGR_TCCMP2_Pos       (18U)

+#define HRTIM_BMTRGR_TCCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP2_Pos)       /*!< 0x00040000 */

+#define HRTIM_BMTRGR_TCCMP2           HRTIM_BMTRGR_TCCMP2_Msk                  /*!< Timer C compare 2 */

+#define HRTIM_BMTRGR_TDRST_Pos        (19U)

+#define HRTIM_BMTRGR_TDRST_Msk        (0x1UL << HRTIM_BMTRGR_TDRST_Pos)        /*!< 0x00080000 */

+#define HRTIM_BMTRGR_TDRST            HRTIM_BMTRGR_TDRST_Msk                   /*!< Timer D reset  */

+#define HRTIM_BMTRGR_TDREP_Pos        (20U)

+#define HRTIM_BMTRGR_TDREP_Msk        (0x1UL << HRTIM_BMTRGR_TDREP_Pos)        /*!< 0x00100000 */

+#define HRTIM_BMTRGR_TDREP            HRTIM_BMTRGR_TDREP_Msk                   /*!< Timer D repetition  */

+#define HRTIM_BMTRGR_TDCMP1_Pos       (21U)

+#define HRTIM_BMTRGR_TDCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP1_Pos)       /*!< 0x00200000 */

+#define HRTIM_BMTRGR_TDCMP1           HRTIM_BMTRGR_TDCMP1_Msk                  /*!< Timer D compare 1 */

+#define HRTIM_BMTRGR_TDCMP2_Pos       (22U)

+#define HRTIM_BMTRGR_TDCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos)       /*!< 0x00400000 */

+#define HRTIM_BMTRGR_TDCMP2           HRTIM_BMTRGR_TDCMP2_Msk                  /*!< Timer D compare 2 */

+#define HRTIM_BMTRGR_TERST_Pos        (23U)

+#define HRTIM_BMTRGR_TERST_Msk        (0x1UL << HRTIM_BMTRGR_TERST_Pos)        /*!< 0x00800000 */

+#define HRTIM_BMTRGR_TERST            HRTIM_BMTRGR_TERST_Msk                   /*!< Timer E reset  */

+#define HRTIM_BMTRGR_TEREP_Pos        (24U)

+#define HRTIM_BMTRGR_TEREP_Msk        (0x1UL << HRTIM_BMTRGR_TEREP_Pos)        /*!< 0x01000000 */

+#define HRTIM_BMTRGR_TEREP            HRTIM_BMTRGR_TEREP_Msk                   /*!< Timer E repetition  */

+#define HRTIM_BMTRGR_TECMP1_Pos       (25U)

+#define HRTIM_BMTRGR_TECMP1_Msk       (0x1UL << HRTIM_BMTRGR_TECMP1_Pos)       /*!< 0x02000000 */

+#define HRTIM_BMTRGR_TECMP1           HRTIM_BMTRGR_TECMP1_Msk                  /*!< Timer E compare 1 */

+#define HRTIM_BMTRGR_TECMP2_Pos       (26U)

+#define HRTIM_BMTRGR_TECMP2_Msk       (0x1UL << HRTIM_BMTRGR_TECMP2_Pos)       /*!< 0x04000000 */

+#define HRTIM_BMTRGR_TECMP2           HRTIM_BMTRGR_TECMP2_Msk                  /*!< Timer E compare 2 */

+#define HRTIM_BMTRGR_TAEEV7_Pos       (27U)

+#define HRTIM_BMTRGR_TAEEV7_Msk       (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos)       /*!< 0x08000000 */

+#define HRTIM_BMTRGR_TAEEV7           HRTIM_BMTRGR_TAEEV7_Msk                  /*!< Timer A period following External Event7  */

+#define HRTIM_BMTRGR_TDEEV8_Pos       (28U)

+#define HRTIM_BMTRGR_TDEEV8_Msk       (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos)       /*!< 0x10000000 */

+#define HRTIM_BMTRGR_TDEEV8           HRTIM_BMTRGR_TDEEV8_Msk                  /*!< Timer D period following External Event8  */

+#define HRTIM_BMTRGR_EEV7_Pos         (29U)

+#define HRTIM_BMTRGR_EEV7_Msk         (0x1UL << HRTIM_BMTRGR_EEV7_Pos)         /*!< 0x20000000 */

+#define HRTIM_BMTRGR_EEV7             HRTIM_BMTRGR_EEV7_Msk                    /*!< External Event 7 */

+#define HRTIM_BMTRGR_EEV8_Pos         (30U)

+#define HRTIM_BMTRGR_EEV8_Msk         (0x1UL << HRTIM_BMTRGR_EEV8_Pos)         /*!< 0x40000000 */

+#define HRTIM_BMTRGR_EEV8             HRTIM_BMTRGR_EEV8_Msk                    /*!< External Event 8 */

+#define HRTIM_BMTRGR_OCHPEV_Pos       (31U)

+#define HRTIM_BMTRGR_OCHPEV_Msk       (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos)       /*!< 0x80000000 */

+#define HRTIM_BMTRGR_OCHPEV           HRTIM_BMTRGR_OCHPEV_Msk                  /*!< on-chip Event */

+

+/*******************  Bit definition for HRTIM_BMCMPR register  ***************/

+#define HRTIM_BMCMPR_BMCMPR_Pos       (0U)

+#define HRTIM_BMCMPR_BMCMPR_Msk       (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_BMCMPR_BMCMPR           HRTIM_BMCMPR_BMCMPR_Msk                  /*!<!<Burst Compare Value */

+

+/*******************  Bit definition for HRTIM_BMPER register  ****************/

+#define HRTIM_BMPER_BMPER_Pos         (0U)

+#define HRTIM_BMPER_BMPER_Msk         (0xFFFFUL << HRTIM_BMPER_BMPER_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_BMPER_BMPER             HRTIM_BMPER_BMPER_Msk                    /*!<!<Burst period Value */

+

+/*******************  Bit definition for HRTIM_EECR1 register  ****************/

+#define HRTIM_EECR1_EE1SRC_Pos        (0U)

+#define HRTIM_EECR1_EE1SRC_Msk        (0x3UL << HRTIM_EECR1_EE1SRC_Pos)        /*!< 0x00000003 */

+#define HRTIM_EECR1_EE1SRC            HRTIM_EECR1_EE1SRC_Msk                   /*!< External event 1 source */

+#define HRTIM_EECR1_EE1SRC_0          (0x1UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000001 */

+#define HRTIM_EECR1_EE1SRC_1          (0x2UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000002 */

+#define HRTIM_EECR1_EE1POL_Pos        (2U)

+#define HRTIM_EECR1_EE1POL_Msk        (0x1UL << HRTIM_EECR1_EE1POL_Pos)        /*!< 0x00000004 */

+#define HRTIM_EECR1_EE1POL            HRTIM_EECR1_EE1POL_Msk                   /*!< External event 1 Polarity */

+#define HRTIM_EECR1_EE1SNS_Pos        (3U)

+#define HRTIM_EECR1_EE1SNS_Msk        (0x3UL << HRTIM_EECR1_EE1SNS_Pos)        /*!< 0x00000018 */

+#define HRTIM_EECR1_EE1SNS            HRTIM_EECR1_EE1SNS_Msk                   /*!< External event 1 sensitivity */

+#define HRTIM_EECR1_EE1SNS_0          (0x1UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000008 */

+#define HRTIM_EECR1_EE1SNS_1          (0x2UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000010 */

+#define HRTIM_EECR1_EE1FAST_Pos       (5U)

+#define HRTIM_EECR1_EE1FAST_Msk       (0x1UL << HRTIM_EECR1_EE1FAST_Pos)       /*!< 0x00000020 */

+#define HRTIM_EECR1_EE1FAST           HRTIM_EECR1_EE1FAST_Msk                  /*!< External event 1 Fast mode */

+

+#define HRTIM_EECR1_EE2SRC_Pos        (6U)

+#define HRTIM_EECR1_EE2SRC_Msk        (0x3UL << HRTIM_EECR1_EE2SRC_Pos)        /*!< 0x000000C0 */

+#define HRTIM_EECR1_EE2SRC            HRTIM_EECR1_EE2SRC_Msk                   /*!< External event 2 source */

+#define HRTIM_EECR1_EE2SRC_0          (0x1UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000040 */

+#define HRTIM_EECR1_EE2SRC_1          (0x2UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000080 */

+#define HRTIM_EECR1_EE2POL_Pos        (8U)

+#define HRTIM_EECR1_EE2POL_Msk        (0x1UL << HRTIM_EECR1_EE2POL_Pos)        /*!< 0x00000100 */

+#define HRTIM_EECR1_EE2POL            HRTIM_EECR1_EE2POL_Msk                   /*!< External event 2 Polarity */

+#define HRTIM_EECR1_EE2SNS_Pos        (9U)

+#define HRTIM_EECR1_EE2SNS_Msk        (0x3UL << HRTIM_EECR1_EE2SNS_Pos)        /*!< 0x00000600 */

+#define HRTIM_EECR1_EE2SNS            HRTIM_EECR1_EE2SNS_Msk                   /*!< External event 2 sensitivity */

+#define HRTIM_EECR1_EE2SNS_0          (0x1UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000200 */

+#define HRTIM_EECR1_EE2SNS_1          (0x2UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000400 */

+#define HRTIM_EECR1_EE2FAST_Pos       (11U)

+#define HRTIM_EECR1_EE2FAST_Msk       (0x1UL << HRTIM_EECR1_EE2FAST_Pos)       /*!< 0x00000800 */

+#define HRTIM_EECR1_EE2FAST           HRTIM_EECR1_EE2FAST_Msk                  /*!< External event 2 Fast mode */

+

+#define HRTIM_EECR1_EE3SRC_Pos        (12U)

+#define HRTIM_EECR1_EE3SRC_Msk        (0x3UL << HRTIM_EECR1_EE3SRC_Pos)        /*!< 0x00003000 */

+#define HRTIM_EECR1_EE3SRC            HRTIM_EECR1_EE3SRC_Msk                   /*!< External event 3 source */

+#define HRTIM_EECR1_EE3SRC_0          (0x1UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00001000 */

+#define HRTIM_EECR1_EE3SRC_1          (0x2UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00002000 */

+#define HRTIM_EECR1_EE3POL_Pos        (14U)

+#define HRTIM_EECR1_EE3POL_Msk        (0x1UL << HRTIM_EECR1_EE3POL_Pos)        /*!< 0x00004000 */

+#define HRTIM_EECR1_EE3POL            HRTIM_EECR1_EE3POL_Msk                   /*!< External event 3 Polarity */

+#define HRTIM_EECR1_EE3SNS_Pos        (15U)

+#define HRTIM_EECR1_EE3SNS_Msk        (0x3UL << HRTIM_EECR1_EE3SNS_Pos)        /*!< 0x00018000 */

+#define HRTIM_EECR1_EE3SNS            HRTIM_EECR1_EE3SNS_Msk                   /*!< External event 3 sensitivity */

+#define HRTIM_EECR1_EE3SNS_0          (0x1UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00008000 */

+#define HRTIM_EECR1_EE3SNS_1          (0x2UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00010000 */

+#define HRTIM_EECR1_EE3FAST_Pos       (17U)

+#define HRTIM_EECR1_EE3FAST_Msk       (0x1UL << HRTIM_EECR1_EE3FAST_Pos)       /*!< 0x00020000 */

+#define HRTIM_EECR1_EE3FAST           HRTIM_EECR1_EE3FAST_Msk                  /*!< External event 3 Fast mode */

+

+#define HRTIM_EECR1_EE4SRC_Pos        (18U)

+#define HRTIM_EECR1_EE4SRC_Msk        (0x3UL << HRTIM_EECR1_EE4SRC_Pos)        /*!< 0x000C0000 */

+#define HRTIM_EECR1_EE4SRC            HRTIM_EECR1_EE4SRC_Msk                   /*!< External event 4 source */

+#define HRTIM_EECR1_EE4SRC_0          (0x1UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00040000 */

+#define HRTIM_EECR1_EE4SRC_1          (0x2UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00080000 */

+#define HRTIM_EECR1_EE4POL_Pos        (20U)

+#define HRTIM_EECR1_EE4POL_Msk        (0x1UL << HRTIM_EECR1_EE4POL_Pos)        /*!< 0x00100000 */

+#define HRTIM_EECR1_EE4POL            HRTIM_EECR1_EE4POL_Msk                   /*!< External event 4 Polarity */

+#define HRTIM_EECR1_EE4SNS_Pos        (21U)

+#define HRTIM_EECR1_EE4SNS_Msk        (0x3UL << HRTIM_EECR1_EE4SNS_Pos)        /*!< 0x00600000 */

+#define HRTIM_EECR1_EE4SNS            HRTIM_EECR1_EE4SNS_Msk                   /*!< External event 4 sensitivity */

+#define HRTIM_EECR1_EE4SNS_0          (0x1UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00200000 */

+#define HRTIM_EECR1_EE4SNS_1          (0x2UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00400000 */

+#define HRTIM_EECR1_EE4FAST_Pos       (23U)

+#define HRTIM_EECR1_EE4FAST_Msk       (0x1UL << HRTIM_EECR1_EE4FAST_Pos)       /*!< 0x00800000 */

+#define HRTIM_EECR1_EE4FAST           HRTIM_EECR1_EE4FAST_Msk                  /*!< External event 4 Fast mode */

+

+#define HRTIM_EECR1_EE5SRC_Pos        (24U)

+#define HRTIM_EECR1_EE5SRC_Msk        (0x3UL << HRTIM_EECR1_EE5SRC_Pos)        /*!< 0x03000000 */

+#define HRTIM_EECR1_EE5SRC            HRTIM_EECR1_EE5SRC_Msk                   /*!< External event 5 source */

+#define HRTIM_EECR1_EE5SRC_0          (0x1UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x01000000 */

+#define HRTIM_EECR1_EE5SRC_1          (0x2UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x02000000 */

+#define HRTIM_EECR1_EE5POL_Pos        (26U)

+#define HRTIM_EECR1_EE5POL_Msk        (0x1UL << HRTIM_EECR1_EE5POL_Pos)        /*!< 0x04000000 */

+#define HRTIM_EECR1_EE5POL            HRTIM_EECR1_EE5POL_Msk                   /*!< External event 5 Polarity */

+#define HRTIM_EECR1_EE5SNS_Pos        (27U)

+#define HRTIM_EECR1_EE5SNS_Msk        (0x3UL << HRTIM_EECR1_EE5SNS_Pos)        /*!< 0x18000000 */

+#define HRTIM_EECR1_EE5SNS            HRTIM_EECR1_EE5SNS_Msk                   /*!< External event 5 sensitivity */

+#define HRTIM_EECR1_EE5SNS_0          (0x1UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x08000000 */

+#define HRTIM_EECR1_EE5SNS_1          (0x2UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x10000000 */

+#define HRTIM_EECR1_EE5FAST_Pos       (29U)

+#define HRTIM_EECR1_EE5FAST_Msk       (0x1UL << HRTIM_EECR1_EE5FAST_Pos)       /*!< 0x20000000 */

+#define HRTIM_EECR1_EE5FAST           HRTIM_EECR1_EE5FAST_Msk                  /*!< External event 5 Fast mode */

+

+/*******************  Bit definition for HRTIM_EECR2 register  ****************/

+#define HRTIM_EECR2_EE6SRC_Pos        (0U)

+#define HRTIM_EECR2_EE6SRC_Msk        (0x3UL << HRTIM_EECR2_EE6SRC_Pos)        /*!< 0x00000003 */

+#define HRTIM_EECR2_EE6SRC            HRTIM_EECR2_EE6SRC_Msk                   /*!< External event 6 source */

+#define HRTIM_EECR2_EE6SRC_0          (0x1UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000001 */

+#define HRTIM_EECR2_EE6SRC_1          (0x2UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000002 */

+#define HRTIM_EECR2_EE6POL_Pos        (2U)

+#define HRTIM_EECR2_EE6POL_Msk        (0x1UL << HRTIM_EECR2_EE6POL_Pos)        /*!< 0x00000004 */

+#define HRTIM_EECR2_EE6POL            HRTIM_EECR2_EE6POL_Msk                   /*!< External event 6 Polarity */

+#define HRTIM_EECR2_EE6SNS_Pos        (3U)

+#define HRTIM_EECR2_EE6SNS_Msk        (0x3UL << HRTIM_EECR2_EE6SNS_Pos)        /*!< 0x00000018 */

+#define HRTIM_EECR2_EE6SNS            HRTIM_EECR2_EE6SNS_Msk                   /*!< External event 6 sensitivity */

+#define HRTIM_EECR2_EE6SNS_0          (0x1UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000008 */

+#define HRTIM_EECR2_EE6SNS_1          (0x2UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000010 */

+

+#define HRTIM_EECR2_EE7SRC_Pos        (6U)

+#define HRTIM_EECR2_EE7SRC_Msk        (0x3UL << HRTIM_EECR2_EE7SRC_Pos)        /*!< 0x000000C0 */

+#define HRTIM_EECR2_EE7SRC            HRTIM_EECR2_EE7SRC_Msk                   /*!< External event 7 source */

+#define HRTIM_EECR2_EE7SRC_0          (0x1UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000040 */

+#define HRTIM_EECR2_EE7SRC_1          (0x2UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000080 */

+#define HRTIM_EECR2_EE7POL_Pos        (8U)

+#define HRTIM_EECR2_EE7POL_Msk        (0x1UL << HRTIM_EECR2_EE7POL_Pos)        /*!< 0x00000100 */

+#define HRTIM_EECR2_EE7POL            HRTIM_EECR2_EE7POL_Msk                   /*!< External event 7 Polarity */

+#define HRTIM_EECR2_EE7SNS_Pos        (9U)

+#define HRTIM_EECR2_EE7SNS_Msk        (0x3UL << HRTIM_EECR2_EE7SNS_Pos)        /*!< 0x00000600 */

+#define HRTIM_EECR2_EE7SNS            HRTIM_EECR2_EE7SNS_Msk                   /*!< External event 7 sensitivity */

+#define HRTIM_EECR2_EE7SNS_0          (0x1UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000200 */

+#define HRTIM_EECR2_EE7SNS_1          (0x2UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000400 */

+

+#define HRTIM_EECR2_EE8SRC_Pos        (12U)

+#define HRTIM_EECR2_EE8SRC_Msk        (0x3UL << HRTIM_EECR2_EE8SRC_Pos)        /*!< 0x00003000 */

+#define HRTIM_EECR2_EE8SRC            HRTIM_EECR2_EE8SRC_Msk                   /*!< External event 8 source */

+#define HRTIM_EECR2_EE8SRC_0          (0x1UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00001000 */

+#define HRTIM_EECR2_EE8SRC_1          (0x2UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00002000 */

+#define HRTIM_EECR2_EE8POL_Pos        (14U)

+#define HRTIM_EECR2_EE8POL_Msk        (0x1UL << HRTIM_EECR2_EE8POL_Pos)        /*!< 0x00004000 */

+#define HRTIM_EECR2_EE8POL            HRTIM_EECR2_EE8POL_Msk                   /*!< External event 8 Polarity */

+#define HRTIM_EECR2_EE8SNS_Pos        (15U)

+#define HRTIM_EECR2_EE8SNS_Msk        (0x3UL << HRTIM_EECR2_EE8SNS_Pos)        /*!< 0x00018000 */

+#define HRTIM_EECR2_EE8SNS            HRTIM_EECR2_EE8SNS_Msk                   /*!< External event 8 sensitivity */

+#define HRTIM_EECR2_EE8SNS_0          (0x1UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00008000 */

+#define HRTIM_EECR2_EE8SNS_1          (0x2UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00010000 */

+

+#define HRTIM_EECR2_EE9SRC_Pos        (18U)

+#define HRTIM_EECR2_EE9SRC_Msk        (0x3UL << HRTIM_EECR2_EE9SRC_Pos)        /*!< 0x000C0000 */

+#define HRTIM_EECR2_EE9SRC            HRTIM_EECR2_EE9SRC_Msk                   /*!< External event 9 source */

+#define HRTIM_EECR2_EE9SRC_0          (0x1UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00040000 */

+#define HRTIM_EECR2_EE9SRC_1          (0x2UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00080000 */

+#define HRTIM_EECR2_EE9POL_Pos        (20U)

+#define HRTIM_EECR2_EE9POL_Msk        (0x1UL << HRTIM_EECR2_EE9POL_Pos)        /*!< 0x00100000 */

+#define HRTIM_EECR2_EE9POL            HRTIM_EECR2_EE9POL_Msk                   /*!< External event 9 Polarity */

+#define HRTIM_EECR2_EE9SNS_Pos        (21U)

+#define HRTIM_EECR2_EE9SNS_Msk        (0x3UL << HRTIM_EECR2_EE9SNS_Pos)        /*!< 0x00600000 */

+#define HRTIM_EECR2_EE9SNS            HRTIM_EECR2_EE9SNS_Msk                   /*!< External event 9 sensitivity */

+#define HRTIM_EECR2_EE9SNS_0          (0x1UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00200000 */

+#define HRTIM_EECR2_EE9SNS_1          (0x2UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00400000 */

+

+#define HRTIM_EECR2_EE10SRC_Pos       (24U)

+#define HRTIM_EECR2_EE10SRC_Msk       (0x3UL << HRTIM_EECR2_EE10SRC_Pos)       /*!< 0x03000000 */

+#define HRTIM_EECR2_EE10SRC           HRTIM_EECR2_EE10SRC_Msk                  /*!< External event 10 source */

+#define HRTIM_EECR2_EE10SRC_0         (0x1UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x01000000 */

+#define HRTIM_EECR2_EE10SRC_1         (0x2UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x02000000 */

+#define HRTIM_EECR2_EE10POL_Pos       (26U)

+#define HRTIM_EECR2_EE10POL_Msk       (0x1UL << HRTIM_EECR2_EE10POL_Pos)       /*!< 0x04000000 */

+#define HRTIM_EECR2_EE10POL           HRTIM_EECR2_EE10POL_Msk                  /*!< External event 10 Polarity */

+#define HRTIM_EECR2_EE10SNS_Pos       (27U)

+#define HRTIM_EECR2_EE10SNS_Msk       (0x3UL << HRTIM_EECR2_EE10SNS_Pos)       /*!< 0x18000000 */

+#define HRTIM_EECR2_EE10SNS           HRTIM_EECR2_EE10SNS_Msk                  /*!< External event 10 sensitivity */

+#define HRTIM_EECR2_EE10SNS_0         (0x1UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x08000000 */

+#define HRTIM_EECR2_EE10SNS_1         (0x2UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x10000000 */

+

+/*******************  Bit definition for HRTIM_EECR3 register  ****************/

+#define HRTIM_EECR3_EE6F_Pos          (0U)

+#define HRTIM_EECR3_EE6F_Msk          (0xFUL << HRTIM_EECR3_EE6F_Pos)          /*!< 0x0000000F */

+#define HRTIM_EECR3_EE6F              HRTIM_EECR3_EE6F_Msk                     /*!< External event 6 filter */

+#define HRTIM_EECR3_EE6F_0            (0x1UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000001 */

+#define HRTIM_EECR3_EE6F_1            (0x2UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000002 */

+#define HRTIM_EECR3_EE6F_2            (0x4UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000004 */

+#define HRTIM_EECR3_EE6F_3            (0x8UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000008 */

+#define HRTIM_EECR3_EE7F_Pos          (6U)

+#define HRTIM_EECR3_EE7F_Msk          (0xFUL << HRTIM_EECR3_EE7F_Pos)          /*!< 0x000003C0 */

+#define HRTIM_EECR3_EE7F              HRTIM_EECR3_EE7F_Msk                     /*!< External event 7 filter */

+#define HRTIM_EECR3_EE7F_0            (0x1UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000040 */

+#define HRTIM_EECR3_EE7F_1            (0x2UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000080 */

+#define HRTIM_EECR3_EE7F_2            (0x4UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000100 */

+#define HRTIM_EECR3_EE7F_3            (0x8UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000200 */

+#define HRTIM_EECR3_EE8F_Pos          (12U)

+#define HRTIM_EECR3_EE8F_Msk          (0xFUL << HRTIM_EECR3_EE8F_Pos)          /*!< 0x0000F000 */

+#define HRTIM_EECR3_EE8F              HRTIM_EECR3_EE8F_Msk                     /*!< External event 8 filter */

+#define HRTIM_EECR3_EE8F_0            (0x1UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00001000 */

+#define HRTIM_EECR3_EE8F_1            (0x2UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00002000 */

+#define HRTIM_EECR3_EE8F_2            (0x4UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00004000 */

+#define HRTIM_EECR3_EE8F_3            (0x8UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00008000 */

+#define HRTIM_EECR3_EE9F_Pos          (18U)

+#define HRTIM_EECR3_EE9F_Msk          (0xFUL << HRTIM_EECR3_EE9F_Pos)          /*!< 0x003C0000 */

+#define HRTIM_EECR3_EE9F              HRTIM_EECR3_EE9F_Msk                     /*!< External event 9 filter */

+#define HRTIM_EECR3_EE9F_0            (0x1UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00040000 */

+#define HRTIM_EECR3_EE9F_1            (0x2UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00080000 */

+#define HRTIM_EECR3_EE9F_2            (0x4UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00100000 */

+#define HRTIM_EECR3_EE9F_3            (0x8UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00200000 */

+#define HRTIM_EECR3_EE10F_Pos         (24U)

+#define HRTIM_EECR3_EE10F_Msk         (0xFUL << HRTIM_EECR3_EE10F_Pos)         /*!< 0x0F000000 */

+#define HRTIM_EECR3_EE10F             HRTIM_EECR3_EE10F_Msk                    /*!< External event 10 filter */

+#define HRTIM_EECR3_EE10F_0           (0x1UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x01000000 */

+#define HRTIM_EECR3_EE10F_1           (0x2UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x02000000 */

+#define HRTIM_EECR3_EE10F_2           (0x4UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x04000000 */

+#define HRTIM_EECR3_EE10F_3           (0x8UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x08000000 */

+#define HRTIM_EECR3_EEVSD_Pos         (30U)

+#define HRTIM_EECR3_EEVSD_Msk         (0x3UL << HRTIM_EECR3_EEVSD_Pos)         /*!< 0xC0000000 */

+#define HRTIM_EECR3_EEVSD             HRTIM_EECR3_EEVSD_Msk                    /*!< External event sampling clock division */

+#define HRTIM_EECR3_EEVSD_0           (0x1UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x40000000 */

+#define HRTIM_EECR3_EEVSD_1           (0x2UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x80000000 */

+

+/*******************  Bit definition for HRTIM_ADC1R register  ****************/

+#define HRTIM_ADC1R_AD1MC1_Pos        (0U)

+#define HRTIM_ADC1R_AD1MC1_Msk        (0x1UL << HRTIM_ADC1R_AD1MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC1R_AD1MC1            HRTIM_ADC1R_AD1MC1_Msk                   /*!< ADC Trigger 1 on master compare 1 */

+#define HRTIM_ADC1R_AD1MC2_Pos        (1U)

+#define HRTIM_ADC1R_AD1MC2_Msk        (0x1UL << HRTIM_ADC1R_AD1MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC1R_AD1MC2            HRTIM_ADC1R_AD1MC2_Msk                   /*!< ADC Trigger 1 on master compare 2 */

+#define HRTIM_ADC1R_AD1MC3_Pos        (2U)

+#define HRTIM_ADC1R_AD1MC3_Msk        (0x1UL << HRTIM_ADC1R_AD1MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC1R_AD1MC3            HRTIM_ADC1R_AD1MC3_Msk                   /*!< ADC Trigger 1 on master compare 3 */

+#define HRTIM_ADC1R_AD1MC4_Pos        (3U)

+#define HRTIM_ADC1R_AD1MC4_Msk        (0x1UL << HRTIM_ADC1R_AD1MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC1R_AD1MC4            HRTIM_ADC1R_AD1MC4_Msk                   /*!< ADC Trigger 1 on master compare 4 */

+#define HRTIM_ADC1R_AD1MPER_Pos       (4U)

+#define HRTIM_ADC1R_AD1MPER_Msk       (0x1UL << HRTIM_ADC1R_AD1MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC1R_AD1MPER           HRTIM_ADC1R_AD1MPER_Msk                  /*!< ADC Trigger 1 on master period */

+#define HRTIM_ADC1R_AD1EEV1_Pos       (5U)

+#define HRTIM_ADC1R_AD1EEV1_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC1R_AD1EEV1           HRTIM_ADC1R_AD1EEV1_Msk                  /*!< ADC Trigger 1 on external event 1 */

+#define HRTIM_ADC1R_AD1EEV2_Pos       (6U)

+#define HRTIM_ADC1R_AD1EEV2_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC1R_AD1EEV2           HRTIM_ADC1R_AD1EEV2_Msk                  /*!< ADC Trigger 1 on external event 2 */

+#define HRTIM_ADC1R_AD1EEV3_Pos       (7U)

+#define HRTIM_ADC1R_AD1EEV3_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC1R_AD1EEV3           HRTIM_ADC1R_AD1EEV3_Msk                  /*!< ADC Trigger 1 on external event 3 */

+#define HRTIM_ADC1R_AD1EEV4_Pos       (8U)

+#define HRTIM_ADC1R_AD1EEV4_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC1R_AD1EEV4           HRTIM_ADC1R_AD1EEV4_Msk                  /*!< ADC Trigger 1 on external event 4 */

+#define HRTIM_ADC1R_AD1EEV5_Pos       (9U)

+#define HRTIM_ADC1R_AD1EEV5_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos)       /*!< 0x00000200 */

+#define HRTIM_ADC1R_AD1EEV5           HRTIM_ADC1R_AD1EEV5_Msk                  /*!< ADC Trigger 1 on external event 5 */

+#define HRTIM_ADC1R_AD1TAC2_Pos       (10U)

+#define HRTIM_ADC1R_AD1TAC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC1R_AD1TAC2           HRTIM_ADC1R_AD1TAC2_Msk                  /*!< ADC Trigger 1 on Timer A compare 2 */

+#define HRTIM_ADC1R_AD1TAC3_Pos       (11U)

+#define HRTIM_ADC1R_AD1TAC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC1R_AD1TAC3           HRTIM_ADC1R_AD1TAC3_Msk                  /*!< ADC Trigger 1 on Timer A compare 3 */

+#define HRTIM_ADC1R_AD1TAC4_Pos       (12U)

+#define HRTIM_ADC1R_AD1TAC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC1R_AD1TAC4           HRTIM_ADC1R_AD1TAC4_Msk                  /*!< ADC Trigger 1 on Timer A compare 4 */

+#define HRTIM_ADC1R_AD1TAPER_Pos      (13U)

+#define HRTIM_ADC1R_AD1TAPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC1R_AD1TAPER          HRTIM_ADC1R_AD1TAPER_Msk                 /*!< ADC Trigger 1 on Timer A period */

+#define HRTIM_ADC1R_AD1TARST_Pos      (14U)

+#define HRTIM_ADC1R_AD1TARST_Msk      (0x1UL << HRTIM_ADC1R_AD1TARST_Pos)      /*!< 0x00004000 */

+#define HRTIM_ADC1R_AD1TARST          HRTIM_ADC1R_AD1TARST_Msk                 /*!< ADC Trigger 1 on Timer A reset */

+#define HRTIM_ADC1R_AD1TBC2_Pos       (15U)

+#define HRTIM_ADC1R_AD1TBC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC2_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC1R_AD1TBC2           HRTIM_ADC1R_AD1TBC2_Msk                  /*!< ADC Trigger 1 on Timer B compare 2 */

+#define HRTIM_ADC1R_AD1TBC3_Pos       (16U)

+#define HRTIM_ADC1R_AD1TBC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC1R_AD1TBC3           HRTIM_ADC1R_AD1TBC3_Msk                  /*!< ADC Trigger 1 on Timer B compare 3 */

+#define HRTIM_ADC1R_AD1TBC4_Pos       (17U)

+#define HRTIM_ADC1R_AD1TBC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos)       /*!< 0x00020000 */

+#define HRTIM_ADC1R_AD1TBC4           HRTIM_ADC1R_AD1TBC4_Msk                  /*!< ADC Trigger 1 on Timer B compare 4 */

+#define HRTIM_ADC1R_AD1TBPER_Pos      (18U)

+#define HRTIM_ADC1R_AD1TBPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos)      /*!< 0x00040000 */

+#define HRTIM_ADC1R_AD1TBPER          HRTIM_ADC1R_AD1TBPER_Msk                 /*!< ADC Trigger 1 on Timer B period */

+#define HRTIM_ADC1R_AD1TBRST_Pos      (19U)

+#define HRTIM_ADC1R_AD1TBRST_Msk      (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos)      /*!< 0x00080000 */

+#define HRTIM_ADC1R_AD1TBRST          HRTIM_ADC1R_AD1TBRST_Msk                 /*!< ADC Trigger 1 on Timer B reset */

+#define HRTIM_ADC1R_AD1TCC2_Pos       (20U)

+#define HRTIM_ADC1R_AD1TCC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC2_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC1R_AD1TCC2           HRTIM_ADC1R_AD1TCC2_Msk                  /*!< ADC Trigger 1 on Timer C compare 2 */

+#define HRTIM_ADC1R_AD1TCC3_Pos       (21U)

+#define HRTIM_ADC1R_AD1TCC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos)       /*!< 0x00200000 */

+#define HRTIM_ADC1R_AD1TCC3           HRTIM_ADC1R_AD1TCC3_Msk                  /*!< ADC Trigger 1 on Timer C compare 3 */

+#define HRTIM_ADC1R_AD1TCC4_Pos       (22U)

+#define HRTIM_ADC1R_AD1TCC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos)       /*!< 0x00400000 */

+#define HRTIM_ADC1R_AD1TCC4           HRTIM_ADC1R_AD1TCC4_Msk                  /*!< ADC Trigger 1 on Timer C compare 4 */

+#define HRTIM_ADC1R_AD1TCPER_Pos      (23U)

+#define HRTIM_ADC1R_AD1TCPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos)      /*!< 0x00800000 */

+#define HRTIM_ADC1R_AD1TCPER          HRTIM_ADC1R_AD1TCPER_Msk                 /*!< ADC Trigger 1 on Timer C period */

+#define HRTIM_ADC1R_AD1TDC2_Pos       (24U)

+#define HRTIM_ADC1R_AD1TDC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC2_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC1R_AD1TDC2           HRTIM_ADC1R_AD1TDC2_Msk                  /*!< ADC Trigger 1 on Timer D compare 2 */

+#define HRTIM_ADC1R_AD1TDC3_Pos       (25U)

+#define HRTIM_ADC1R_AD1TDC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC1R_AD1TDC3           HRTIM_ADC1R_AD1TDC3_Msk                  /*!< ADC Trigger 1 on Timer D compare 3 */

+#define HRTIM_ADC1R_AD1TDC4_Pos       (26U)

+#define HRTIM_ADC1R_AD1TDC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos)       /*!< 0x04000000 */

+#define HRTIM_ADC1R_AD1TDC4           HRTIM_ADC1R_AD1TDC4_Msk                  /*!< ADC Trigger 1 on Timer D compare 4 */

+#define HRTIM_ADC1R_AD1TDPER_Pos      (27U)

+#define HRTIM_ADC1R_AD1TDPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC1R_AD1TDPER          HRTIM_ADC1R_AD1TDPER_Msk                 /*!< ADC Trigger 1 on Timer D period */

+#define HRTIM_ADC1R_AD1TEC2_Pos       (28U)

+#define HRTIM_ADC1R_AD1TEC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC1R_AD1TEC2           HRTIM_ADC1R_AD1TEC2_Msk                  /*!< ADC Trigger 1 on Timer E compare 2 */

+#define HRTIM_ADC1R_AD1TEC3_Pos       (29U)

+#define HRTIM_ADC1R_AD1TEC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC1R_AD1TEC3           HRTIM_ADC1R_AD1TEC3_Msk                  /*!< ADC Trigger 1 on Timer E compare 3 */

+#define HRTIM_ADC1R_AD1TEC4_Pos       (30U)

+#define HRTIM_ADC1R_AD1TEC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC1R_AD1TEC4           HRTIM_ADC1R_AD1TEC4_Msk                  /*!< ADC Trigger 1 on Timer E compare 4 */

+#define HRTIM_ADC1R_AD1TEPER_Pos      (31U)

+#define HRTIM_ADC1R_AD1TEPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC1R_AD1TEPER          HRTIM_ADC1R_AD1TEPER_Msk                 /*!< ADC Trigger 1 on Timer E period */

+

+/*******************  Bit definition for HRTIM_ADC2R register  ****************/

+#define HRTIM_ADC2R_AD2MC1_Pos        (0U)

+#define HRTIM_ADC2R_AD2MC1_Msk        (0x1UL << HRTIM_ADC2R_AD2MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC2R_AD2MC1            HRTIM_ADC2R_AD2MC1_Msk                   /*!< ADC Trigger 2 on master compare 1 */

+#define HRTIM_ADC2R_AD2MC2_Pos        (1U)

+#define HRTIM_ADC2R_AD2MC2_Msk        (0x1UL << HRTIM_ADC2R_AD2MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC2R_AD2MC2            HRTIM_ADC2R_AD2MC2_Msk                   /*!< ADC Trigger 2 on master compare 2 */

+#define HRTIM_ADC2R_AD2MC3_Pos        (2U)

+#define HRTIM_ADC2R_AD2MC3_Msk        (0x1UL << HRTIM_ADC2R_AD2MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC2R_AD2MC3            HRTIM_ADC2R_AD2MC3_Msk                   /*!< ADC Trigger 2 on master compare 3 */

+#define HRTIM_ADC2R_AD2MC4_Pos        (3U)

+#define HRTIM_ADC2R_AD2MC4_Msk        (0x1UL << HRTIM_ADC2R_AD2MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC2R_AD2MC4            HRTIM_ADC2R_AD2MC4_Msk                   /*!< ADC Trigger 2 on master compare 4 */

+#define HRTIM_ADC2R_AD2MPER_Pos       (4U)

+#define HRTIM_ADC2R_AD2MPER_Msk       (0x1UL << HRTIM_ADC2R_AD2MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC2R_AD2MPER           HRTIM_ADC2R_AD2MPER_Msk                  /*!< ADC Trigger 2 on master period */

+#define HRTIM_ADC2R_AD2EEV6_Pos       (5U)

+#define HRTIM_ADC2R_AD2EEV6_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC2R_AD2EEV6           HRTIM_ADC2R_AD2EEV6_Msk                  /*!< ADC Trigger 2 on external event 6 */

+#define HRTIM_ADC2R_AD2EEV7_Pos       (6U)

+#define HRTIM_ADC2R_AD2EEV7_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC2R_AD2EEV7           HRTIM_ADC2R_AD2EEV7_Msk                  /*!< ADC Trigger 2 on external event 7 */

+#define HRTIM_ADC2R_AD2EEV8_Pos       (7U)

+#define HRTIM_ADC2R_AD2EEV8_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC2R_AD2EEV8           HRTIM_ADC2R_AD2EEV8_Msk                  /*!< ADC Trigger 2 on external event 8 */

+#define HRTIM_ADC2R_AD2EEV9_Pos       (8U)

+#define HRTIM_ADC2R_AD2EEV9_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC2R_AD2EEV9           HRTIM_ADC2R_AD2EEV9_Msk                  /*!< ADC Trigger 2 on external event 9 */

+#define HRTIM_ADC2R_AD2EEV10_Pos      (9U)

+#define HRTIM_ADC2R_AD2EEV10_Msk      (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos)      /*!< 0x00000200 */

+#define HRTIM_ADC2R_AD2EEV10          HRTIM_ADC2R_AD2EEV10_Msk                 /*!< ADC Trigger 2 on external event 10 */

+#define HRTIM_ADC2R_AD2TAC2_Pos       (10U)

+#define HRTIM_ADC2R_AD2TAC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC2R_AD2TAC2           HRTIM_ADC2R_AD2TAC2_Msk                  /*!< ADC Trigger 2 on Timer A compare 2 */

+#define HRTIM_ADC2R_AD2TAC3_Pos       (11U)

+#define HRTIM_ADC2R_AD2TAC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC2R_AD2TAC3           HRTIM_ADC2R_AD2TAC3_Msk                  /*!< ADC Trigger 2 on Timer A compare 3 */

+#define HRTIM_ADC2R_AD2TAC4_Pos       (12U)

+#define HRTIM_ADC2R_AD2TAC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC2R_AD2TAC4           HRTIM_ADC2R_AD2TAC4_Msk                  /*!< ADC Trigger 2 on Timer A compare 4*/

+#define HRTIM_ADC2R_AD2TAPER_Pos      (13U)

+#define HRTIM_ADC2R_AD2TAPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC2R_AD2TAPER          HRTIM_ADC2R_AD2TAPER_Msk                 /*!< ADC Trigger 2 on Timer A period */

+#define HRTIM_ADC2R_AD2TBC2_Pos       (14U)

+#define HRTIM_ADC2R_AD2TBC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos)       /*!< 0x00004000 */

+#define HRTIM_ADC2R_AD2TBC2           HRTIM_ADC2R_AD2TBC2_Msk                  /*!< ADC Trigger 2 on Timer B compare 2 */

+#define HRTIM_ADC2R_AD2TBC3_Pos       (15U)

+#define HRTIM_ADC2R_AD2TBC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC3_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC2R_AD2TBC3           HRTIM_ADC2R_AD2TBC3_Msk                  /*!< ADC Trigger 2 on Timer B compare 3 */

+#define HRTIM_ADC2R_AD2TBC4_Pos       (16U)

+#define HRTIM_ADC2R_AD2TBC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC2R_AD2TBC4           HRTIM_ADC2R_AD2TBC4_Msk                  /*!< ADC Trigger 2 on Timer B compare 4 */

+#define HRTIM_ADC2R_AD2TBPER_Pos      (17U)

+#define HRTIM_ADC2R_AD2TBPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos)      /*!< 0x00020000 */

+#define HRTIM_ADC2R_AD2TBPER          HRTIM_ADC2R_AD2TBPER_Msk                 /*!< ADC Trigger 2 on Timer B period */

+#define HRTIM_ADC2R_AD2TCC2_Pos       (18U)

+#define HRTIM_ADC2R_AD2TCC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos)       /*!< 0x00040000 */

+#define HRTIM_ADC2R_AD2TCC2           HRTIM_ADC2R_AD2TCC2_Msk                  /*!< ADC Trigger 2 on Timer C compare 2 */

+#define HRTIM_ADC2R_AD2TCC3_Pos       (19U)

+#define HRTIM_ADC2R_AD2TCC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC3_Pos)       /*!< 0x00080000 */

+#define HRTIM_ADC2R_AD2TCC3           HRTIM_ADC2R_AD2TCC3_Msk                  /*!< ADC Trigger 2 on Timer C compare 3 */

+#define HRTIM_ADC2R_AD2TCC4_Pos       (20U)

+#define HRTIM_ADC2R_AD2TCC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC2R_AD2TCC4           HRTIM_ADC2R_AD2TCC4_Msk                  /*!< ADC Trigger 2 on Timer C compare 4 */

+#define HRTIM_ADC2R_AD2TCPER_Pos      (21U)

+#define HRTIM_ADC2R_AD2TCPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos)      /*!< 0x00200000 */

+#define HRTIM_ADC2R_AD2TCPER          HRTIM_ADC2R_AD2TCPER_Msk                 /*!< ADC Trigger 2 on Timer C period */

+#define HRTIM_ADC2R_AD2TCRST_Pos      (22U)

+#define HRTIM_ADC2R_AD2TCRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos)      /*!< 0x00400000 */

+#define HRTIM_ADC2R_AD2TCRST          HRTIM_ADC2R_AD2TCRST_Msk                 /*!< ADC Trigger 2 on Timer C reset */

+#define HRTIM_ADC2R_AD2TDC2_Pos       (23U)

+#define HRTIM_ADC2R_AD2TDC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos)       /*!< 0x00800000 */

+#define HRTIM_ADC2R_AD2TDC2           HRTIM_ADC2R_AD2TDC2_Msk                  /*!< ADC Trigger 2 on Timer D compare 2 */

+#define HRTIM_ADC2R_AD2TDC3_Pos       (24U)

+#define HRTIM_ADC2R_AD2TDC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC3_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC2R_AD2TDC3           HRTIM_ADC2R_AD2TDC3_Msk                  /*!< ADC Trigger 2 on Timer D compare 3 */

+#define HRTIM_ADC2R_AD2TDC4_Pos       (25U)

+#define HRTIM_ADC2R_AD2TDC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC2R_AD2TDC4           HRTIM_ADC2R_AD2TDC4_Msk                  /*!< ADC Trigger 2 on Timer D compare 4*/

+#define HRTIM_ADC2R_AD2TDPER_Pos      (26U)

+#define HRTIM_ADC2R_AD2TDPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos)      /*!< 0x04000000 */

+#define HRTIM_ADC2R_AD2TDPER          HRTIM_ADC2R_AD2TDPER_Msk                 /*!< ADC Trigger 2 on Timer D period */

+#define HRTIM_ADC2R_AD2TDRST_Pos      (27U)

+#define HRTIM_ADC2R_AD2TDRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC2R_AD2TDRST          HRTIM_ADC2R_AD2TDRST_Msk                 /*!< ADC Trigger 2 on Timer D reset */

+#define HRTIM_ADC2R_AD2TEC2_Pos       (28U)

+#define HRTIM_ADC2R_AD2TEC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC2R_AD2TEC2           HRTIM_ADC2R_AD2TEC2_Msk                  /*!< ADC Trigger 2 on Timer E compare 2 */

+#define HRTIM_ADC2R_AD2TEC3_Pos       (29U)

+#define HRTIM_ADC2R_AD2TEC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC2R_AD2TEC3           HRTIM_ADC2R_AD2TEC3_Msk                  /*!< ADC Trigger 2 on Timer E compare 3 */

+#define HRTIM_ADC2R_AD2TEC4_Pos       (30U)

+#define HRTIM_ADC2R_AD2TEC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC2R_AD2TEC4           HRTIM_ADC2R_AD2TEC4_Msk                  /*!< ADC Trigger 2 on Timer E compare 4 */

+#define HRTIM_ADC2R_AD2TERST_Pos      (31U)

+#define HRTIM_ADC2R_AD2TERST_Msk      (0x1UL << HRTIM_ADC2R_AD2TERST_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC2R_AD2TERST          HRTIM_ADC2R_AD2TERST_Msk                 /*!< ADC Trigger 2 on Timer E reset */

+

+/*******************  Bit definition for HRTIM_ADC3R register  ****************/

+#define HRTIM_ADC3R_AD3MC1_Pos        (0U)

+#define HRTIM_ADC3R_AD3MC1_Msk        (0x1UL << HRTIM_ADC3R_AD3MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC3R_AD3MC1            HRTIM_ADC3R_AD3MC1_Msk                   /*!< ADC Trigger 3 on master compare 1 */

+#define HRTIM_ADC3R_AD3MC2_Pos        (1U)

+#define HRTIM_ADC3R_AD3MC2_Msk        (0x1UL << HRTIM_ADC3R_AD3MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC3R_AD3MC2            HRTIM_ADC3R_AD3MC2_Msk                   /*!< ADC Trigger 3 on master compare 2 */

+#define HRTIM_ADC3R_AD3MC3_Pos        (2U)

+#define HRTIM_ADC3R_AD3MC3_Msk        (0x1UL << HRTIM_ADC3R_AD3MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC3R_AD3MC3            HRTIM_ADC3R_AD3MC3_Msk                   /*!< ADC Trigger 3 on master compare 3 */

+#define HRTIM_ADC3R_AD3MC4_Pos        (3U)

+#define HRTIM_ADC3R_AD3MC4_Msk        (0x1UL << HRTIM_ADC3R_AD3MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC3R_AD3MC4            HRTIM_ADC3R_AD3MC4_Msk                   /*!< ADC Trigger 3 on master compare 4 */

+#define HRTIM_ADC3R_AD3MPER_Pos       (4U)

+#define HRTIM_ADC3R_AD3MPER_Msk       (0x1UL << HRTIM_ADC3R_AD3MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC3R_AD3MPER           HRTIM_ADC3R_AD3MPER_Msk                  /*!< ADC Trigger 3 on master period */

+#define HRTIM_ADC3R_AD3EEV1_Pos       (5U)

+#define HRTIM_ADC3R_AD3EEV1_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC3R_AD3EEV1           HRTIM_ADC3R_AD3EEV1_Msk                  /*!< ADC Trigger 3 on external event 1 */

+#define HRTIM_ADC3R_AD3EEV2_Pos       (6U)

+#define HRTIM_ADC3R_AD3EEV2_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC3R_AD3EEV2           HRTIM_ADC3R_AD3EEV2_Msk                  /*!< ADC Trigger 3 on external event 2 */

+#define HRTIM_ADC3R_AD3EEV3_Pos       (7U)

+#define HRTIM_ADC3R_AD3EEV3_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC3R_AD3EEV3           HRTIM_ADC3R_AD3EEV3_Msk                  /*!< ADC Trigger 3 on external event 3 */

+#define HRTIM_ADC3R_AD3EEV4_Pos       (8U)

+#define HRTIM_ADC3R_AD3EEV4_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC3R_AD3EEV4           HRTIM_ADC3R_AD3EEV4_Msk                  /*!< ADC Trigger 3 on external event 4 */

+#define HRTIM_ADC3R_AD3EEV5_Pos       (9U)

+#define HRTIM_ADC3R_AD3EEV5_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos)       /*!< 0x00000200 */

+#define HRTIM_ADC3R_AD3EEV5           HRTIM_ADC3R_AD3EEV5_Msk                  /*!< ADC Trigger 3 on external event 5 */

+#define HRTIM_ADC3R_AD3TAC2_Pos       (10U)

+#define HRTIM_ADC3R_AD3TAC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC3R_AD3TAC2           HRTIM_ADC3R_AD3TAC2_Msk                  /*!< ADC Trigger 3 on Timer A compare 2 */

+#define HRTIM_ADC3R_AD3TAC3_Pos       (11U)

+#define HRTIM_ADC3R_AD3TAC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC3R_AD3TAC3           HRTIM_ADC3R_AD3TAC3_Msk                  /*!< ADC Trigger 3 on Timer A compare 3 */

+#define HRTIM_ADC3R_AD3TAC4_Pos       (12U)

+#define HRTIM_ADC3R_AD3TAC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC3R_AD3TAC4           HRTIM_ADC3R_AD3TAC4_Msk                  /*!< ADC Trigger 3 on Timer A compare 4 */

+#define HRTIM_ADC3R_AD3TAPER_Pos      (13U)

+#define HRTIM_ADC3R_AD3TAPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC3R_AD3TAPER          HRTIM_ADC3R_AD3TAPER_Msk                 /*!< ADC Trigger 3 on Timer A period */

+#define HRTIM_ADC3R_AD3TARST_Pos      (14U)

+#define HRTIM_ADC3R_AD3TARST_Msk      (0x1UL << HRTIM_ADC3R_AD3TARST_Pos)      /*!< 0x00004000 */

+#define HRTIM_ADC3R_AD3TARST          HRTIM_ADC3R_AD3TARST_Msk                 /*!< ADC Trigger 3 on Timer A reset */

+#define HRTIM_ADC3R_AD3TBC2_Pos       (15U)

+#define HRTIM_ADC3R_AD3TBC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC2_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC3R_AD3TBC2           HRTIM_ADC3R_AD3TBC2_Msk                  /*!< ADC Trigger 3 on Timer B compare 2 */

+#define HRTIM_ADC3R_AD3TBC3_Pos       (16U)

+#define HRTIM_ADC3R_AD3TBC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC3R_AD3TBC3           HRTIM_ADC3R_AD3TBC3_Msk                  /*!< ADC Trigger 3 on Timer B compare 3 */

+#define HRTIM_ADC3R_AD3TBC4_Pos       (17U)

+#define HRTIM_ADC3R_AD3TBC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos)       /*!< 0x00020000 */

+#define HRTIM_ADC3R_AD3TBC4           HRTIM_ADC3R_AD3TBC4_Msk                  /*!< ADC Trigger 3 on Timer B compare 4 */

+#define HRTIM_ADC3R_AD3TBPER_Pos      (18U)

+#define HRTIM_ADC3R_AD3TBPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos)      /*!< 0x00040000 */

+#define HRTIM_ADC3R_AD3TBPER          HRTIM_ADC3R_AD3TBPER_Msk                 /*!< ADC Trigger 3 on Timer B period */

+#define HRTIM_ADC3R_AD3TBRST_Pos      (19U)

+#define HRTIM_ADC3R_AD3TBRST_Msk      (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos)      /*!< 0x00080000 */

+#define HRTIM_ADC3R_AD3TBRST          HRTIM_ADC3R_AD3TBRST_Msk                 /*!< ADC Trigger 3 on Timer B reset */

+#define HRTIM_ADC3R_AD3TCC2_Pos       (20U)

+#define HRTIM_ADC3R_AD3TCC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC2_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC3R_AD3TCC2           HRTIM_ADC3R_AD3TCC2_Msk                  /*!< ADC Trigger 3 on Timer C compare 2 */

+#define HRTIM_ADC3R_AD3TCC3_Pos       (21U)

+#define HRTIM_ADC3R_AD3TCC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos)       /*!< 0x00200000 */

+#define HRTIM_ADC3R_AD3TCC3           HRTIM_ADC3R_AD3TCC3_Msk                  /*!< ADC Trigger 3 on Timer C compare 3 */

+#define HRTIM_ADC3R_AD3TCC4_Pos       (22U)

+#define HRTIM_ADC3R_AD3TCC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos)       /*!< 0x00400000 */

+#define HRTIM_ADC3R_AD3TCC4           HRTIM_ADC3R_AD3TCC4_Msk                  /*!< ADC Trigger 3 on Timer C compare 4 */

+#define HRTIM_ADC3R_AD3TCPER_Pos      (23U)

+#define HRTIM_ADC3R_AD3TCPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos)      /*!< 0x00800000 */

+#define HRTIM_ADC3R_AD3TCPER          HRTIM_ADC3R_AD3TCPER_Msk                 /*!< ADC Trigger 3 on Timer C period */

+#define HRTIM_ADC3R_AD3TDC2_Pos       (24U)

+#define HRTIM_ADC3R_AD3TDC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC2_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC3R_AD3TDC2           HRTIM_ADC3R_AD3TDC2_Msk                  /*!< ADC Trigger 3 on Timer D compare 2 */

+#define HRTIM_ADC3R_AD3TDC3_Pos       (25U)

+#define HRTIM_ADC3R_AD3TDC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC3R_AD3TDC3           HRTIM_ADC3R_AD3TDC3_Msk                  /*!< ADC Trigger 3 on Timer D compare 3 */

+#define HRTIM_ADC3R_AD3TDC4_Pos       (26U)

+#define HRTIM_ADC3R_AD3TDC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos)       /*!< 0x04000000 */

+#define HRTIM_ADC3R_AD3TDC4           HRTIM_ADC3R_AD3TDC4_Msk                  /*!< ADC Trigger 3 on Timer D compare 4 */

+#define HRTIM_ADC3R_AD3TDPER_Pos      (27U)

+#define HRTIM_ADC3R_AD3TDPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC3R_AD3TDPER          HRTIM_ADC3R_AD3TDPER_Msk                 /*!< ADC Trigger 3 on Timer D period */

+#define HRTIM_ADC3R_AD3TEC2_Pos       (28U)

+#define HRTIM_ADC3R_AD3TEC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC3R_AD3TEC2           HRTIM_ADC3R_AD3TEC2_Msk                  /*!< ADC Trigger 3 on Timer E compare 2 */

+#define HRTIM_ADC3R_AD3TEC3_Pos       (29U)

+#define HRTIM_ADC3R_AD3TEC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC3R_AD3TEC3           HRTIM_ADC3R_AD3TEC3_Msk                  /*!< ADC Trigger 3 on Timer E compare 3 */

+#define HRTIM_ADC3R_AD3TEC4_Pos       (30U)

+#define HRTIM_ADC3R_AD3TEC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC3R_AD3TEC4           HRTIM_ADC3R_AD3TEC4_Msk                  /*!< ADC Trigger 3 on Timer E compare 4 */

+#define HRTIM_ADC3R_AD3TEPER_Pos      (31U)

+#define HRTIM_ADC3R_AD3TEPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC3R_AD3TEPER          HRTIM_ADC3R_AD3TEPER_Msk                 /*!< ADC Trigger 3 on Timer E period */

+

+/*******************  Bit definition for HRTIM_ADC4R register  ****************/

+#define HRTIM_ADC4R_AD4MC1_Pos        (0U)

+#define HRTIM_ADC4R_AD4MC1_Msk        (0x1UL << HRTIM_ADC4R_AD4MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC4R_AD4MC1            HRTIM_ADC4R_AD4MC1_Msk                   /*!< ADC Trigger 4 on master compare 1 */

+#define HRTIM_ADC4R_AD4MC2_Pos        (1U)

+#define HRTIM_ADC4R_AD4MC2_Msk        (0x1UL << HRTIM_ADC4R_AD4MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC4R_AD4MC2            HRTIM_ADC4R_AD4MC2_Msk                   /*!< ADC Trigger 4 on master compare 2 */

+#define HRTIM_ADC4R_AD4MC3_Pos        (2U)

+#define HRTIM_ADC4R_AD4MC3_Msk        (0x1UL << HRTIM_ADC4R_AD4MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC4R_AD4MC3            HRTIM_ADC4R_AD4MC3_Msk                   /*!< ADC Trigger 4 on master compare 3 */

+#define HRTIM_ADC4R_AD4MC4_Pos        (3U)

+#define HRTIM_ADC4R_AD4MC4_Msk        (0x1UL << HRTIM_ADC4R_AD4MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC4R_AD4MC4            HRTIM_ADC4R_AD4MC4_Msk                   /*!< ADC Trigger 4 on master compare 4 */

+#define HRTIM_ADC4R_AD4MPER_Pos       (4U)

+#define HRTIM_ADC4R_AD4MPER_Msk       (0x1UL << HRTIM_ADC4R_AD4MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC4R_AD4MPER           HRTIM_ADC4R_AD4MPER_Msk                  /*!< ADC Trigger 4 on master period */

+#define HRTIM_ADC4R_AD4EEV6_Pos       (5U)

+#define HRTIM_ADC4R_AD4EEV6_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC4R_AD4EEV6           HRTIM_ADC4R_AD4EEV6_Msk                  /*!< ADC Trigger 4 on external event 6 */

+#define HRTIM_ADC4R_AD4EEV7_Pos       (6U)

+#define HRTIM_ADC4R_AD4EEV7_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC4R_AD4EEV7           HRTIM_ADC4R_AD4EEV7_Msk                  /*!< ADC Trigger 4 on external event 7 */

+#define HRTIM_ADC4R_AD4EEV8_Pos       (7U)

+#define HRTIM_ADC4R_AD4EEV8_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC4R_AD4EEV8           HRTIM_ADC4R_AD4EEV8_Msk                  /*!< ADC Trigger 4 on external event 8 */

+#define HRTIM_ADC4R_AD4EEV9_Pos       (8U)

+#define HRTIM_ADC4R_AD4EEV9_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC4R_AD4EEV9           HRTIM_ADC4R_AD4EEV9_Msk                  /*!< ADC Trigger 4 on external event 9 */

+#define HRTIM_ADC4R_AD4EEV10_Pos      (9U)

+#define HRTIM_ADC4R_AD4EEV10_Msk      (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos)      /*!< 0x00000200 */

+#define HRTIM_ADC4R_AD4EEV10          HRTIM_ADC4R_AD4EEV10_Msk                 /*!< ADC Trigger 4 on external event 10 */

+#define HRTIM_ADC4R_AD4TAC2_Pos       (10U)

+#define HRTIM_ADC4R_AD4TAC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC4R_AD4TAC2           HRTIM_ADC4R_AD4TAC2_Msk                  /*!< ADC Trigger 4 on Timer A compare 2 */

+#define HRTIM_ADC4R_AD4TAC3_Pos       (11U)

+#define HRTIM_ADC4R_AD4TAC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC4R_AD4TAC3           HRTIM_ADC4R_AD4TAC3_Msk                  /*!< ADC Trigger 4 on Timer A compare 3 */

+#define HRTIM_ADC4R_AD4TAC4_Pos       (12U)

+#define HRTIM_ADC4R_AD4TAC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC4R_AD4TAC4           HRTIM_ADC4R_AD4TAC4_Msk                  /*!< ADC Trigger 4 on Timer A compare 4*/

+#define HRTIM_ADC4R_AD4TAPER_Pos      (13U)

+#define HRTIM_ADC4R_AD4TAPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC4R_AD4TAPER          HRTIM_ADC4R_AD4TAPER_Msk                 /*!< ADC Trigger 4 on Timer A period */

+#define HRTIM_ADC4R_AD4TBC2_Pos       (14U)

+#define HRTIM_ADC4R_AD4TBC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos)       /*!< 0x00004000 */

+#define HRTIM_ADC4R_AD4TBC2           HRTIM_ADC4R_AD4TBC2_Msk                  /*!< ADC Trigger 4 on Timer B compare 2 */

+#define HRTIM_ADC4R_AD4TBC3_Pos       (15U)

+#define HRTIM_ADC4R_AD4TBC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC3_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC4R_AD4TBC3           HRTIM_ADC4R_AD4TBC3_Msk                  /*!< ADC Trigger 4 on Timer B compare 3 */

+#define HRTIM_ADC4R_AD4TBC4_Pos       (16U)

+#define HRTIM_ADC4R_AD4TBC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC4R_AD4TBC4           HRTIM_ADC4R_AD4TBC4_Msk                  /*!< ADC Trigger 4 on Timer B compare 4 */

+#define HRTIM_ADC4R_AD4TBPER_Pos      (17U)

+#define HRTIM_ADC4R_AD4TBPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos)      /*!< 0x00020000 */

+#define HRTIM_ADC4R_AD4TBPER          HRTIM_ADC4R_AD4TBPER_Msk                 /*!< ADC Trigger 4 on Timer B period */

+#define HRTIM_ADC4R_AD4TCC2_Pos       (18U)

+#define HRTIM_ADC4R_AD4TCC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos)       /*!< 0x00040000 */

+#define HRTIM_ADC4R_AD4TCC2           HRTIM_ADC4R_AD4TCC2_Msk                  /*!< ADC Trigger 4 on Timer C compare 2 */

+#define HRTIM_ADC4R_AD4TCC3_Pos       (19U)

+#define HRTIM_ADC4R_AD4TCC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC3_Pos)       /*!< 0x00080000 */

+#define HRTIM_ADC4R_AD4TCC3           HRTIM_ADC4R_AD4TCC3_Msk                  /*!< ADC Trigger 4 on Timer C compare 3 */

+#define HRTIM_ADC4R_AD4TCC4_Pos       (20U)

+#define HRTIM_ADC4R_AD4TCC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC4R_AD4TCC4           HRTIM_ADC4R_AD4TCC4_Msk                  /*!< ADC Trigger 4 on Timer C compare 4 */

+#define HRTIM_ADC4R_AD4TCPER_Pos      (21U)

+#define HRTIM_ADC4R_AD4TCPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos)      /*!< 0x00200000 */

+#define HRTIM_ADC4R_AD4TCPER          HRTIM_ADC4R_AD4TCPER_Msk                 /*!< ADC Trigger 4 on Timer C period */

+#define HRTIM_ADC4R_AD4TCRST_Pos      (22U)

+#define HRTIM_ADC4R_AD4TCRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos)      /*!< 0x00400000 */

+#define HRTIM_ADC4R_AD4TCRST          HRTIM_ADC4R_AD4TCRST_Msk                 /*!< ADC Trigger 4 on Timer C reset */

+#define HRTIM_ADC4R_AD4TDC2_Pos       (23U)

+#define HRTIM_ADC4R_AD4TDC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos)       /*!< 0x00800000 */

+#define HRTIM_ADC4R_AD4TDC2           HRTIM_ADC4R_AD4TDC2_Msk                  /*!< ADC Trigger 4 on Timer D compare 2 */

+#define HRTIM_ADC4R_AD4TDC3_Pos       (24U)

+#define HRTIM_ADC4R_AD4TDC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC3_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC4R_AD4TDC3           HRTIM_ADC4R_AD4TDC3_Msk                  /*!< ADC Trigger 4 on Timer D compare 3 */

+#define HRTIM_ADC4R_AD4TDC4_Pos       (25U)

+#define HRTIM_ADC4R_AD4TDC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC4R_AD4TDC4           HRTIM_ADC4R_AD4TDC4_Msk                  /*!< ADC Trigger 4 on Timer D compare 4*/

+#define HRTIM_ADC4R_AD4TDPER_Pos      (26U)

+#define HRTIM_ADC4R_AD4TDPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos)      /*!< 0x04000000 */

+#define HRTIM_ADC4R_AD4TDPER          HRTIM_ADC4R_AD4TDPER_Msk                 /*!< ADC Trigger 4 on Timer D period */

+#define HRTIM_ADC4R_AD4TDRST_Pos      (27U)

+#define HRTIM_ADC4R_AD4TDRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC4R_AD4TDRST          HRTIM_ADC4R_AD4TDRST_Msk                 /*!< ADC Trigger 4 on Timer D reset */

+#define HRTIM_ADC4R_AD4TEC2_Pos       (28U)

+#define HRTIM_ADC4R_AD4TEC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC4R_AD4TEC2           HRTIM_ADC4R_AD4TEC2_Msk                  /*!< ADC Trigger 4 on Timer E compare 2 */

+#define HRTIM_ADC4R_AD4TEC3_Pos       (29U)

+#define HRTIM_ADC4R_AD4TEC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC4R_AD4TEC3           HRTIM_ADC4R_AD4TEC3_Msk                  /*!< ADC Trigger 4 on Timer E compare 3 */

+#define HRTIM_ADC4R_AD4TEC4_Pos       (30U)

+#define HRTIM_ADC4R_AD4TEC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC4R_AD4TEC4           HRTIM_ADC4R_AD4TEC4_Msk                  /*!< ADC Trigger 4 on Timer E compare 4 */

+#define HRTIM_ADC4R_AD4TERST_Pos      (31U)

+#define HRTIM_ADC4R_AD4TERST_Msk      (0x1UL << HRTIM_ADC4R_AD4TERST_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC4R_AD4TERST          HRTIM_ADC4R_AD4TERST_Msk                 /*!< ADC Trigger 4 on Timer E reset */

+

+/*******************  Bit definition for HRTIM_FLTINR1 register  ***************/

+#define HRTIM_FLTINR1_FLT1E_Pos       (0U)

+#define HRTIM_FLTINR1_FLT1E_Msk       (0x1UL << HRTIM_FLTINR1_FLT1E_Pos)       /*!< 0x00000001 */

+#define HRTIM_FLTINR1_FLT1E           HRTIM_FLTINR1_FLT1E_Msk                  /*!< Fault 1 enable */

+#define HRTIM_FLTINR1_FLT1P_Pos       (1U)

+#define HRTIM_FLTINR1_FLT1P_Msk       (0x1UL << HRTIM_FLTINR1_FLT1P_Pos)       /*!< 0x00000002 */

+#define HRTIM_FLTINR1_FLT1P           HRTIM_FLTINR1_FLT1P_Msk                  /*!< Fault 1 polarity */

+#define HRTIM_FLTINR1_FLT1SRC_Pos     (2U)

+#define HRTIM_FLTINR1_FLT1SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT1SRC_Pos)     /*!< 0x00000004 */

+#define HRTIM_FLTINR1_FLT1SRC         HRTIM_FLTINR1_FLT1SRC_Msk                /*!< Fault 1 source */

+#define HRTIM_FLTINR1_FLT1F_Pos       (3U)

+#define HRTIM_FLTINR1_FLT1F_Msk       (0xFUL << HRTIM_FLTINR1_FLT1F_Pos)       /*!< 0x00000078 */

+#define HRTIM_FLTINR1_FLT1F           HRTIM_FLTINR1_FLT1F_Msk                  /*!< Fault 1 filter */

+#define HRTIM_FLTINR1_FLT1F_0         (0x1UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000008 */

+#define HRTIM_FLTINR1_FLT1F_1         (0x2UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000010 */

+#define HRTIM_FLTINR1_FLT1F_2         (0x4UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000020 */

+#define HRTIM_FLTINR1_FLT1F_3         (0x8UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000040 */

+#define HRTIM_FLTINR1_FLT1LCK_Pos     (7U)

+#define HRTIM_FLTINR1_FLT1LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos)     /*!< 0x00000080 */

+#define HRTIM_FLTINR1_FLT1LCK         HRTIM_FLTINR1_FLT1LCK_Msk                /*!< Fault 1 lock */

+

+#define HRTIM_FLTINR1_FLT2E_Pos       (8U)

+#define HRTIM_FLTINR1_FLT2E_Msk       (0x1UL << HRTIM_FLTINR1_FLT2E_Pos)       /*!< 0x00000100 */

+#define HRTIM_FLTINR1_FLT2E           HRTIM_FLTINR1_FLT2E_Msk                  /*!< Fault 2 enable */

+#define HRTIM_FLTINR1_FLT2P_Pos       (9U)

+#define HRTIM_FLTINR1_FLT2P_Msk       (0x1UL << HRTIM_FLTINR1_FLT2P_Pos)       /*!< 0x00000200 */

+#define HRTIM_FLTINR1_FLT2P           HRTIM_FLTINR1_FLT2P_Msk                  /*!< Fault 2 polarity */

+#define HRTIM_FLTINR1_FLT2SRC_Pos     (10U)

+#define HRTIM_FLTINR1_FLT2SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT2SRC_Pos)     /*!< 0x00000400 */

+#define HRTIM_FLTINR1_FLT2SRC         HRTIM_FLTINR1_FLT2SRC_Msk                /*!< Fault 2 source */

+#define HRTIM_FLTINR1_FLT2F_Pos       (11U)

+#define HRTIM_FLTINR1_FLT2F_Msk       (0xFUL << HRTIM_FLTINR1_FLT2F_Pos)       /*!< 0x00007800 */

+#define HRTIM_FLTINR1_FLT2F           HRTIM_FLTINR1_FLT2F_Msk                  /*!< Fault 2 filter */

+#define HRTIM_FLTINR1_FLT2F_0         (0x1UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00000800 */

+#define HRTIM_FLTINR1_FLT2F_1         (0x2UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00001000 */

+#define HRTIM_FLTINR1_FLT2F_2         (0x4UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00002000 */

+#define HRTIM_FLTINR1_FLT2F_3         (0x8UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00004000 */

+#define HRTIM_FLTINR1_FLT2LCK_Pos     (15U)

+#define HRTIM_FLTINR1_FLT2LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos)     /*!< 0x00008000 */

+#define HRTIM_FLTINR1_FLT2LCK         HRTIM_FLTINR1_FLT2LCK_Msk                /*!< Fault 2 lock */

+

+#define HRTIM_FLTINR1_FLT3E_Pos       (16U)

+#define HRTIM_FLTINR1_FLT3E_Msk       (0x1UL << HRTIM_FLTINR1_FLT3E_Pos)       /*!< 0x00010000 */

+#define HRTIM_FLTINR1_FLT3E           HRTIM_FLTINR1_FLT3E_Msk                  /*!< Fault 3 enable */

+#define HRTIM_FLTINR1_FLT3P_Pos       (17U)

+#define HRTIM_FLTINR1_FLT3P_Msk       (0x1UL << HRTIM_FLTINR1_FLT3P_Pos)       /*!< 0x00020000 */

+#define HRTIM_FLTINR1_FLT3P           HRTIM_FLTINR1_FLT3P_Msk                  /*!< Fault 3 polarity */

+#define HRTIM_FLTINR1_FLT3SRC_Pos     (18U)

+#define HRTIM_FLTINR1_FLT3SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT3SRC_Pos)     /*!< 0x00040000 */

+#define HRTIM_FLTINR1_FLT3SRC         HRTIM_FLTINR1_FLT3SRC_Msk                /*!< Fault 3 source */

+#define HRTIM_FLTINR1_FLT3F_Pos       (19U)

+#define HRTIM_FLTINR1_FLT3F_Msk       (0xFUL << HRTIM_FLTINR1_FLT3F_Pos)       /*!< 0x00780000 */

+#define HRTIM_FLTINR1_FLT3F           HRTIM_FLTINR1_FLT3F_Msk                  /*!< Fault 3 filter */

+#define HRTIM_FLTINR1_FLT3F_0         (0x1UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00080000 */

+#define HRTIM_FLTINR1_FLT3F_1         (0x2UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00100000 */

+#define HRTIM_FLTINR1_FLT3F_2         (0x4UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00200000 */

+#define HRTIM_FLTINR1_FLT3F_3         (0x8UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00400000 */

+#define HRTIM_FLTINR1_FLT3LCK_Pos     (23U)

+#define HRTIM_FLTINR1_FLT3LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos)     /*!< 0x00800000 */

+#define HRTIM_FLTINR1_FLT3LCK         HRTIM_FLTINR1_FLT3LCK_Msk                /*!< Fault 3 lock */

+

+#define HRTIM_FLTINR1_FLT4E_Pos       (24U)

+#define HRTIM_FLTINR1_FLT4E_Msk       (0x1UL << HRTIM_FLTINR1_FLT4E_Pos)       /*!< 0x01000000 */

+#define HRTIM_FLTINR1_FLT4E           HRTIM_FLTINR1_FLT4E_Msk                  /*!< Fault 4 enable */

+#define HRTIM_FLTINR1_FLT4P_Pos       (25U)

+#define HRTIM_FLTINR1_FLT4P_Msk       (0x1UL << HRTIM_FLTINR1_FLT4P_Pos)       /*!< 0x02000000 */

+#define HRTIM_FLTINR1_FLT4P           HRTIM_FLTINR1_FLT4P_Msk                  /*!< Fault 4 polarity */

+#define HRTIM_FLTINR1_FLT4SRC_Pos     (26U)

+#define HRTIM_FLTINR1_FLT4SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT4SRC_Pos)     /*!< 0x04000000 */

+#define HRTIM_FLTINR1_FLT4SRC         HRTIM_FLTINR1_FLT4SRC_Msk                /*!< Fault 4 source */

+#define HRTIM_FLTINR1_FLT4F_Pos       (27U)

+#define HRTIM_FLTINR1_FLT4F_Msk       (0xFUL << HRTIM_FLTINR1_FLT4F_Pos)       /*!< 0x78000000 */

+#define HRTIM_FLTINR1_FLT4F           HRTIM_FLTINR1_FLT4F_Msk                  /*!< Fault 4 filter */

+#define HRTIM_FLTINR1_FLT4F_0         (0x1UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x08000000 */

+#define HRTIM_FLTINR1_FLT4F_1         (0x2UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x10000000 */

+#define HRTIM_FLTINR1_FLT4F_2         (0x4UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x20000000 */

+#define HRTIM_FLTINR1_FLT4F_3         (0x8UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x40000000 */

+#define HRTIM_FLTINR1_FLT4LCK_Pos     (31U)

+#define HRTIM_FLTINR1_FLT4LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos)     /*!< 0x80000000 */

+#define HRTIM_FLTINR1_FLT4LCK         HRTIM_FLTINR1_FLT4LCK_Msk                /*!< Fault 4 lock */

+

+/*******************  Bit definition for HRTIM_FLTINR2 register  ***************/

+#define HRTIM_FLTINR2_FLT5E_Pos       (0U)

+#define HRTIM_FLTINR2_FLT5E_Msk       (0x1UL << HRTIM_FLTINR2_FLT5E_Pos)       /*!< 0x00000001 */

+#define HRTIM_FLTINR2_FLT5E           HRTIM_FLTINR2_FLT5E_Msk                  /*!< Fault 5 enable */

+#define HRTIM_FLTINR2_FLT5P_Pos       (1U)

+#define HRTIM_FLTINR2_FLT5P_Msk       (0x1UL << HRTIM_FLTINR2_FLT5P_Pos)       /*!< 0x00000002 */

+#define HRTIM_FLTINR2_FLT5P           HRTIM_FLTINR2_FLT5P_Msk                  /*!< Fault 5 polarity */

+#define HRTIM_FLTINR2_FLT5SRC_Pos     (2U)

+#define HRTIM_FLTINR2_FLT5SRC_Msk     (0x1UL << HRTIM_FLTINR2_FLT5SRC_Pos)     /*!< 0x00000004 */

+#define HRTIM_FLTINR2_FLT5SRC         HRTIM_FLTINR2_FLT5SRC_Msk                /*!< Fault 5 source */

+#define HRTIM_FLTINR2_FLT5F_Pos       (3U)

+#define HRTIM_FLTINR2_FLT5F_Msk       (0xFUL << HRTIM_FLTINR2_FLT5F_Pos)       /*!< 0x00000078 */

+#define HRTIM_FLTINR2_FLT5F           HRTIM_FLTINR2_FLT5F_Msk                  /*!< Fault 5 filter */

+#define HRTIM_FLTINR2_FLT5F_0         (0x1UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000008 */

+#define HRTIM_FLTINR2_FLT5F_1         (0x2UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000010 */

+#define HRTIM_FLTINR2_FLT5F_2         (0x4UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000020 */

+#define HRTIM_FLTINR2_FLT5F_3         (0x8UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000040 */

+#define HRTIM_FLTINR2_FLT5LCK_Pos     (7U)

+#define HRTIM_FLTINR2_FLT5LCK_Msk     (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos)     /*!< 0x00000080 */

+#define HRTIM_FLTINR2_FLT5LCK         HRTIM_FLTINR2_FLT5LCK_Msk                /*!< Fault 5 lock */

+#define HRTIM_FLTINR2_FLTSD_Pos       (24U)

+#define HRTIM_FLTINR2_FLTSD_Msk       (0x3UL << HRTIM_FLTINR2_FLTSD_Pos)       /*!< 0x03000000 */

+#define HRTIM_FLTINR2_FLTSD           HRTIM_FLTINR2_FLTSD_Msk                  /*!< Fault sampling clock division */

+#define HRTIM_FLTINR2_FLTSD_0         (0x1UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x01000000 */

+#define HRTIM_FLTINR2_FLTSD_1         (0x2UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x02000000 */

+

+/*******************  Bit definition for HRTIM_BDMUPR register  ***************/

+#define HRTIM_BDMUPR_MCR_Pos          (0U)

+#define HRTIM_BDMUPR_MCR_Msk          (0x1UL << HRTIM_BDMUPR_MCR_Pos)          /*!< 0x00000001 */

+#define HRTIM_BDMUPR_MCR              HRTIM_BDMUPR_MCR_Msk                     /*!< MCR register update enable */

+#define HRTIM_BDMUPR_MICR_Pos         (1U)

+#define HRTIM_BDMUPR_MICR_Msk         (0x1UL << HRTIM_BDMUPR_MICR_Pos)         /*!< 0x00000002 */

+#define HRTIM_BDMUPR_MICR             HRTIM_BDMUPR_MICR_Msk                    /*!< MICR register update enable */

+#define HRTIM_BDMUPR_MDIER_Pos        (2U)

+#define HRTIM_BDMUPR_MDIER_Msk        (0x1UL << HRTIM_BDMUPR_MDIER_Pos)        /*!< 0x00000004 */

+#define HRTIM_BDMUPR_MDIER            HRTIM_BDMUPR_MDIER_Msk                   /*!< MDIER register update enable */

+#define HRTIM_BDMUPR_MCNT_Pos         (3U)

+#define HRTIM_BDMUPR_MCNT_Msk         (0x1UL << HRTIM_BDMUPR_MCNT_Pos)         /*!< 0x00000008 */

+#define HRTIM_BDMUPR_MCNT             HRTIM_BDMUPR_MCNT_Msk                    /*!< MCNT register update enable */

+#define HRTIM_BDMUPR_MPER_Pos         (4U)

+#define HRTIM_BDMUPR_MPER_Msk         (0x1UL << HRTIM_BDMUPR_MPER_Pos)         /*!< 0x00000010 */

+#define HRTIM_BDMUPR_MPER             HRTIM_BDMUPR_MPER_Msk                    /*!< MPER register update enable */

+#define HRTIM_BDMUPR_MREP_Pos         (5U)

+#define HRTIM_BDMUPR_MREP_Msk         (0x1UL << HRTIM_BDMUPR_MREP_Pos)         /*!< 0x00000020 */

+#define HRTIM_BDMUPR_MREP             HRTIM_BDMUPR_MREP_Msk                    /*!< MREP register update enable */

+#define HRTIM_BDMUPR_MCMP1_Pos        (6U)

+#define HRTIM_BDMUPR_MCMP1_Msk        (0x1UL << HRTIM_BDMUPR_MCMP1_Pos)        /*!< 0x00000040 */

+#define HRTIM_BDMUPR_MCMP1            HRTIM_BDMUPR_MCMP1_Msk                   /*!< MCMP1 register update enable */

+#define HRTIM_BDMUPR_MCMP2_Pos        (7U)

+#define HRTIM_BDMUPR_MCMP2_Msk        (0x1UL << HRTIM_BDMUPR_MCMP2_Pos)        /*!< 0x00000080 */

+#define HRTIM_BDMUPR_MCMP2            HRTIM_BDMUPR_MCMP2_Msk                   /*!< MCMP2 register update enable */

+#define HRTIM_BDMUPR_MCMP3_Pos        (8U)

+#define HRTIM_BDMUPR_MCMP3_Msk        (0x1UL << HRTIM_BDMUPR_MCMP3_Pos)        /*!< 0x00000100 */

+#define HRTIM_BDMUPR_MCMP3            HRTIM_BDMUPR_MCMP3_Msk                   /*!< MCMP3 register update enable */

+#define HRTIM_BDMUPR_MCMP4_Pos        (9U)

+#define HRTIM_BDMUPR_MCMP4_Msk        (0x1UL << HRTIM_BDMUPR_MCMP4_Pos)        /*!< 0x00000200 */

+#define HRTIM_BDMUPR_MCMP4            HRTIM_BDMUPR_MCMP4_Msk                   /*!< MPCMP4 register update enable */

+

+/*******************  Bit definition for HRTIM_BDTUPR register  ***************/

+#define HRTIM_BDTUPR_TIMCR_Pos        (0U)

+#define HRTIM_BDTUPR_TIMCR_Msk        (0x1UL << HRTIM_BDTUPR_TIMCR_Pos)        /*!< 0x00000001 */

+#define HRTIM_BDTUPR_TIMCR            HRTIM_BDTUPR_TIMCR_Msk                   /*!<  TIMCR register update enable */

+#define HRTIM_BDTUPR_TIMICR_Pos       (1U)

+#define HRTIM_BDTUPR_TIMICR_Msk       (0x1UL << HRTIM_BDTUPR_TIMICR_Pos)       /*!< 0x00000002 */

+#define HRTIM_BDTUPR_TIMICR           HRTIM_BDTUPR_TIMICR_Msk                  /*!<  TIMICR register update enable */

+#define HRTIM_BDTUPR_TIMDIER_Pos      (2U)

+#define HRTIM_BDTUPR_TIMDIER_Msk      (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos)      /*!< 0x00000004 */

+#define HRTIM_BDTUPR_TIMDIER          HRTIM_BDTUPR_TIMDIER_Msk                 /*!<  TIMDIER register update enable */

+#define HRTIM_BDTUPR_TIMCNT_Pos       (3U)

+#define HRTIM_BDTUPR_TIMCNT_Msk       (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos)       /*!< 0x00000008 */

+#define HRTIM_BDTUPR_TIMCNT           HRTIM_BDTUPR_TIMCNT_Msk                  /*!<  TIMCNT register update enable */

+#define HRTIM_BDTUPR_TIMPER_Pos       (4U)

+#define HRTIM_BDTUPR_TIMPER_Msk       (0x1UL << HRTIM_BDTUPR_TIMPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_BDTUPR_TIMPER           HRTIM_BDTUPR_TIMPER_Msk                  /*!<  TIMPER register update enable */

+#define HRTIM_BDTUPR_TIMREP_Pos       (5U)

+#define HRTIM_BDTUPR_TIMREP_Msk       (0x1UL << HRTIM_BDTUPR_TIMREP_Pos)       /*!< 0x00000020 */

+#define HRTIM_BDTUPR_TIMREP           HRTIM_BDTUPR_TIMREP_Msk                  /*!<  TIMREP register update enable */

+#define HRTIM_BDTUPR_TIMCMP1_Pos      (6U)

+#define HRTIM_BDTUPR_TIMCMP1_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos)      /*!< 0x00000040 */

+#define HRTIM_BDTUPR_TIMCMP1          HRTIM_BDTUPR_TIMCMP1_Msk                 /*!<  TIMCMP1 register update enable */

+#define HRTIM_BDTUPR_TIMCMP2_Pos      (7U)

+#define HRTIM_BDTUPR_TIMCMP2_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos)      /*!< 0x00000080 */

+#define HRTIM_BDTUPR_TIMCMP2          HRTIM_BDTUPR_TIMCMP2_Msk                 /*!<  TIMCMP2 register update enable */

+#define HRTIM_BDTUPR_TIMCMP3_Pos      (8U)

+#define HRTIM_BDTUPR_TIMCMP3_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos)      /*!< 0x00000100 */

+#define HRTIM_BDTUPR_TIMCMP3          HRTIM_BDTUPR_TIMCMP3_Msk                 /*!<  TIMCMP3 register update enable */

+#define HRTIM_BDTUPR_TIMCMP4_Pos      (9U)

+#define HRTIM_BDTUPR_TIMCMP4_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos)      /*!< 0x00000200 */

+#define HRTIM_BDTUPR_TIMCMP4          HRTIM_BDTUPR_TIMCMP4_Msk                 /*!<  TIMCMP4 register update enable */

+#define HRTIM_BDTUPR_TIMDTR_Pos       (10U)

+#define HRTIM_BDTUPR_TIMDTR_Msk       (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos)       /*!< 0x00000400 */

+#define HRTIM_BDTUPR_TIMDTR           HRTIM_BDTUPR_TIMDTR_Msk                  /*!<  TIMDTR register update enable */

+#define HRTIM_BDTUPR_TIMSET1R_Pos     (11U)

+#define HRTIM_BDTUPR_TIMSET1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos)     /*!< 0x00000800 */

+#define HRTIM_BDTUPR_TIMSET1R         HRTIM_BDTUPR_TIMSET1R_Msk                /*!<  TIMSET1R register update enable */

+#define HRTIM_BDTUPR_TIMRST1R_Pos     (12U)

+#define HRTIM_BDTUPR_TIMRST1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos)     /*!< 0x00001000 */

+#define HRTIM_BDTUPR_TIMRST1R         HRTIM_BDTUPR_TIMRST1R_Msk                /*!<  TIMRST1R register update enable */

+#define HRTIM_BDTUPR_TIMSET2R_Pos     (13U)

+#define HRTIM_BDTUPR_TIMSET2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos)     /*!< 0x00002000 */

+#define HRTIM_BDTUPR_TIMSET2R         HRTIM_BDTUPR_TIMSET2R_Msk                /*!<  TIMSET2R register update enable */

+#define HRTIM_BDTUPR_TIMRST2R_Pos     (14U)

+#define HRTIM_BDTUPR_TIMRST2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos)     /*!< 0x00004000 */

+#define HRTIM_BDTUPR_TIMRST2R         HRTIM_BDTUPR_TIMRST2R_Msk                /*!<  TIMRST2R register update enable */

+#define HRTIM_BDTUPR_TIMEEFR1_Pos     (15U)

+#define HRTIM_BDTUPR_TIMEEFR1_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos)     /*!< 0x00008000 */

+#define HRTIM_BDTUPR_TIMEEFR1         HRTIM_BDTUPR_TIMEEFR1_Msk                /*!<  TIMEEFR1 register update enable */

+#define HRTIM_BDTUPR_TIMEEFR2_Pos     (16U)

+#define HRTIM_BDTUPR_TIMEEFR2_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos)     /*!< 0x00010000 */

+#define HRTIM_BDTUPR_TIMEEFR2         HRTIM_BDTUPR_TIMEEFR2_Msk                /*!<  TIMEEFR2 register update enable */

+#define HRTIM_BDTUPR_TIMRSTR_Pos      (17U)

+#define HRTIM_BDTUPR_TIMRSTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos)      /*!< 0x00020000 */

+#define HRTIM_BDTUPR_TIMRSTR          HRTIM_BDTUPR_TIMRSTR_Msk                 /*!<  TIMRSTR register update enable */

+#define HRTIM_BDTUPR_TIMCHPR_Pos      (18U)

+#define HRTIM_BDTUPR_TIMCHPR_Msk      (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos)      /*!< 0x00040000 */

+#define HRTIM_BDTUPR_TIMCHPR          HRTIM_BDTUPR_TIMCHPR_Msk                 /*!<  TIMCHPR register update enable */

+#define HRTIM_BDTUPR_TIMOUTR_Pos      (19U)

+#define HRTIM_BDTUPR_TIMOUTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos)      /*!< 0x00080000 */

+#define HRTIM_BDTUPR_TIMOUTR          HRTIM_BDTUPR_TIMOUTR_Msk                 /*!<  TIMOUTR register update enable */

+#define HRTIM_BDTUPR_TIMFLTR_Pos      (20U)

+#define HRTIM_BDTUPR_TIMFLTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos)      /*!< 0x00100000 */

+#define HRTIM_BDTUPR_TIMFLTR          HRTIM_BDTUPR_TIMFLTR_Msk                 /*!<  TIMFLTR register update enable */

+

+/*******************  Bit definition for HRTIM_BDMADR register  ***************/

+#define HRTIM_BDMADR_BDMADR_Pos       (0U)

+#define HRTIM_BDMADR_BDMADR_Msk       (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos) /*!< 0xFFFFFFFF */

+#define HRTIM_BDMADR_BDMADR           HRTIM_BDMADR_BDMADR_Msk                  /*!<  Burst DMA Data register */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             RAM ECC monitoring                             */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for RAMECC_IER register  ******************/

+#define RAMECC_IER_GECCDEBWIE_Pos         (3U)

+#define RAMECC_IER_GECCDEBWIE_Msk         (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)  /*!< 0x00000008 */

+#define RAMECC_IER_GECCDEBWIE             RAMECC_IER_GECCDEBWIE_Msk             /*!< Global ECC double error on byte write (BW) interrupt enable */

+#define RAMECC_IER_GECCDEIE_Pos           (2U)

+#define RAMECC_IER_GECCDEIE_Msk           (0x1UL << RAMECC_IER_GECCDEIE_Pos)    /*!< 0x00000004 */

+#define RAMECC_IER_GECCDEIE               RAMECC_IER_GECCDEIE_Msk               /*!< Global ECC double error interrupt enable */

+#define RAMECC_IER_GECCSEIE_Pos           (1U)

+#define RAMECC_IER_GECCSEIE_Msk           (0x1UL << RAMECC_IER_GECCSEIE_Pos)    /*!< 0x00000002 */

+#define RAMECC_IER_GECCSEIE               RAMECC_IER_GECCSEIE_Msk               /*!< Global ECC single error interrupt enable */

+#define RAMECC_IER_GIE_Pos                (0U)

+#define RAMECC_IER_GIE_Msk                (0x1UL << RAMECC_IER_GIE_Pos)         /*!< 0x00000001 */

+#define RAMECC_IER_GIE                    RAMECC_IER_GIE_Msk                    /*!< Global interrupt enable */

+

+/*******************  Bit definition for RAMECC_CR register  ******************/

+#define RAMECC_CR_ECCELEN_Pos             (5U)

+#define RAMECC_CR_ECCELEN_Msk             (0x1UL << RAMECC_CR_ECCELEN_Pos)      /*!< 0x00000020 */

+#define RAMECC_CR_ECCELEN                 RAMECC_CR_ECCELEN_Msk                 /*!< ECC error latching enable */

+#define RAMECC_CR_ECCDEBWIE_Pos           (4U)

+#define RAMECC_CR_ECCDEBWIE_Msk           (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)    /*!< 0x00000010 */

+#define RAMECC_CR_ECCDEBWIE               RAMECC_CR_ECCDEBWIE_Msk               /*!< ECC double error on byte write (BW) interrupt enable */

+#define RAMECC_CR_ECCDEIE_Pos             (3U)

+#define RAMECC_CR_ECCDEIE_Msk             (0x1UL << RAMECC_CR_ECCDEIE_Pos)      /*!< 0x00000008 */

+#define RAMECC_CR_ECCDEIE                 RAMECC_CR_ECCDEIE_Msk                 /*!< ECC double error interrupt enable */

+#define RAMECC_CR_ECCSEIE_Pos             (2U)

+#define RAMECC_CR_ECCSEIE_Msk             (0x1UL << RAMECC_CR_ECCSEIE_Pos)      /*!< 0x00000004 */

+#define RAMECC_CR_ECCSEIE                 RAMECC_CR_ECCSEIE_Msk                 /*!< ECC single error interrupt enable */

+

+/*******************  Bit definition for RAMECC_SR register  ******************/

+#define RAMECC_SR_DEBWDF_Pos             (2U)

+#define RAMECC_SR_DEBWDF_Msk             (0x1UL << RAMECC_SR_DEBWDF_Pos)        /*!< 0x00000004 */

+#define RAMECC_SR_DEBWDF                 RAMECC_SR_DEBWDF_Msk                   /*!< ECC double error on byte write (BW) detected flag */

+#define RAMECC_SR_DEDF_Pos               (1U)

+#define RAMECC_SR_DEDF_Msk               (0x1UL << RAMECC_SR_DEDF_Pos)          /*!< 0x00000002 */

+#define RAMECC_SR_DEDF                   RAMECC_SR_DEDF_Msk                     /*!< ECC double error detected flag */

+#define RAMECC_SR_SEDCF_Pos              (0U)

+#define RAMECC_SR_SEDCF_Msk              (0x1UL << RAMECC_SR_SEDCF_Pos)         /*!< 0x00000001 */

+#define RAMECC_SR_SEDCF                  RAMECC_SR_SEDCF_Msk                    /*!< ECC single error detected and corrected flag */

+

+/******************  Bit definition for RAMECC_FAR register  ******************/

+#define RAMECC_FAR_FADD_Pos              (0U)

+#define RAMECC_FAR_FADD_Msk              (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)  /*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FADD                  RAMECC_FAR_FADD_Msk                    /*!< ECC error failing address */

+

+/******************  Bit definition for RAMECC_FDRL register  *****************/

+#define RAMECC_FAR_FDATAL_Pos            (0U)

+#define RAMECC_FAR_FDATAL_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FDATAL                RAMECC_FAR_FDATAL_Msk                  /*!< ECC error failing address */

+

+/******************  Bit definition for RAMECC_FDRH register  *****************/

+#define RAMECC_FAR_FDATAH_Pos            (0U)

+#define RAMECC_FAR_FDATAH_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FDATAH                RAMECC_FAR_FDATAH_Msk                  /* Failing data high (64-bit memory) */

+

+/*****************  Bit definition for RAMECC_FECR register  ******************/

+#define RAMECC_FECR_FEC_Pos              (0U)

+#define RAMECC_FECR_FEC_Msk              (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)  /*!< 0xFFFFFFFF */

+#define RAMECC_FECR_FEC                  RAMECC_FECR_FEC_Msk                    /*!< Failing error code */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                MDIOS                                        */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for MDIOS_CR register  *******************/

+#define MDIOS_CR_EN_Pos                (0U)

+#define MDIOS_CR_EN_Msk                (0x1UL << MDIOS_CR_EN_Pos)              /*!< 0x00000001 */

+#define MDIOS_CR_EN                    MDIOS_CR_EN_Msk                         /*!<  MDIOS slave peripheral enable */

+#define MDIOS_CR_WRIE_Pos              (1U)

+#define MDIOS_CR_WRIE_Msk              (0x1UL << MDIOS_CR_WRIE_Pos)            /*!< 0x00000002 */

+#define MDIOS_CR_WRIE                  MDIOS_CR_WRIE_Msk                       /*!<  MDIOS slave register write interrupt enable. */

+#define MDIOS_CR_RDIE_Pos              (2U)

+#define MDIOS_CR_RDIE_Msk              (0x1UL << MDIOS_CR_RDIE_Pos)            /*!< 0x00000004 */

+#define MDIOS_CR_RDIE                  MDIOS_CR_RDIE_Msk                       /*!<  MDIOS slave register read interrupt enable. */

+#define MDIOS_CR_EIE_Pos               (3U)

+#define MDIOS_CR_EIE_Msk               (0x1UL << MDIOS_CR_EIE_Pos)             /*!< 0x00000008 */

+#define MDIOS_CR_EIE                   MDIOS_CR_EIE_Msk                        /*!<  MDIOS slave register error interrupt enable. */

+#define MDIOS_CR_DPC_Pos               (7U)

+#define MDIOS_CR_DPC_Msk               (0x1UL << MDIOS_CR_DPC_Pos)             /*!< 0x00000080 */

+#define MDIOS_CR_DPC                   MDIOS_CR_DPC_Msk                        /*!<  MDIOS slave disable preamble check. */

+#define MDIOS_CR_PORT_ADDRESS_Pos      (8U)

+#define MDIOS_CR_PORT_ADDRESS_Msk      (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)   /*!< 0x00001F00 */

+#define MDIOS_CR_PORT_ADDRESS          MDIOS_CR_PORT_ADDRESS_Msk               /*!<  MDIOS slave port address mask. */

+#define MDIOS_CR_PORT_ADDRESS_0        (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000100 */

+#define MDIOS_CR_PORT_ADDRESS_1        (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000200 */

+#define MDIOS_CR_PORT_ADDRESS_2        (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000400 */

+#define MDIOS_CR_PORT_ADDRESS_3        (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000800 */

+#define MDIOS_CR_PORT_ADDRESS_4        (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001000 */

+

+/********************  Bit definition for MDIOS_SR register  *******************/

+#define MDIOS_SR_PERF_Pos              (0U)

+#define MDIOS_SR_PERF_Msk              (0x1UL << MDIOS_SR_PERF_Pos)            /*!< 0x00000001 */

+#define MDIOS_SR_PERF                  MDIOS_SR_PERF_Msk                       /*!<  MDIOS slave turnaround error flag*/

+#define MDIOS_SR_SERF_Pos              (1U)

+#define MDIOS_SR_SERF_Msk              (0x1UL << MDIOS_SR_SERF_Pos)            /*!< 0x00000002 */

+#define MDIOS_SR_SERF                  MDIOS_SR_SERF_Msk                       /*!<  MDIOS slave start error flag */

+#define MDIOS_SR_TERF_Pos              (2U)

+#define MDIOS_SR_TERF_Msk              (0x1UL << MDIOS_SR_TERF_Pos)            /*!< 0x00000004 */

+#define MDIOS_SR_TERF                  MDIOS_SR_TERF_Msk                       /*!<  MDIOS slave preamble error flag */

+

+/********************  Bit definition for MDIOS_CLRFR register  *******************/

+#define MDIOS_SR_CPERF_Pos             (0U)

+#define MDIOS_SR_CPERF_Msk             (0x1UL << MDIOS_SR_CPERF_Pos)           /*!< 0x00000001 */

+#define MDIOS_SR_CPERF                 MDIOS_SR_CPERF_Msk                      /*!<  MDIOS slave Clear the turnaround error flag */

+#define MDIOS_SR_CSERF_Pos             (1U)

+#define MDIOS_SR_CSERF_Msk             (0x1UL << MDIOS_SR_CSERF_Pos)           /*!< 0x00000002 */

+#define MDIOS_SR_CSERF                 MDIOS_SR_CSERF_Msk                      /*!<  MDIOS slave Clear the start error flag */

+#define MDIOS_SR_CTERF_Pos             (2U)

+#define MDIOS_SR_CTERF_Msk             (0x1UL << MDIOS_SR_CTERF_Pos)           /*!< 0x00000004 */

+#define MDIOS_SR_CTERF                 MDIOS_SR_CTERF_Msk                      /*!<  MDIOS slave Clear the preamble error flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                       USB_OTG                              */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/

+#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)

+#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */

+#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */

+#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)

+#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */

+#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */

+#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)

+#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */

+#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */

+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)

+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */

+#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */

+#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)

+#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */

+#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */

+#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)

+#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */

+#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */

+#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)

+#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */

+#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */

+#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)

+#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */

+#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */

+#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)

+#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */

+#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */

+#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)

+#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */

+#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */

+#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)

+#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */

+#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */

+#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)

+#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */

+#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */

+#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)

+#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */

+#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */

+#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)

+#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */

+#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */

+#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)

+#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */

+#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */

+#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)

+#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */

+#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */

+#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)

+#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */

+#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */

+#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)

+#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */

+#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */

+

+/********************  Bit definition forUSB_OTG_HCFG register  ********************/

+

+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)

+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */

+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */

+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)

+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */

+

+/********************  Bit definition forUSB_OTG_DCFG register  ********************/

+

+#define USB_OTG_DCFG_DSPD_Pos                    (0U)

+#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */

+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */

+#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */

+#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)

+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */

+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */

+

+#define USB_OTG_DCFG_DAD_Pos                     (4U)

+#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */

+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */

+#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */

+#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */

+#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */

+#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */

+#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */

+#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */

+#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */

+

+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)

+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */

+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */

+#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */

+#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */

+

+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)

+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */

+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */

+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */

+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */

+

+/********************  Bit definition forUSB_OTG_PCGCR register  ********************/

+#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)

+#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */

+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */

+#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)

+#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */

+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */

+#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)

+#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */

+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */

+

+/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/

+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)

+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */

+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */

+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)

+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */

+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */

+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)

+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */

+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */

+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)

+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */

+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */

+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)

+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */

+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */

+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)

+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */

+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */

+

+/********************  Bit definition forUSB_OTG_DCTL register  ********************/

+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)

+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */

+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */

+#define USB_OTG_DCTL_SDIS_Pos                    (1U)

+#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */

+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */

+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)

+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */

+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */

+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)

+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */

+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */

+

+#define USB_OTG_DCTL_TCTL_Pos                    (4U)

+#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */

+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */

+#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */

+#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */

+#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */

+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)

+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */

+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */

+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)

+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */

+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */

+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)

+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */

+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */

+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)

+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */

+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */

+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)

+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */

+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */

+

+/********************  Bit definition forUSB_OTG_HFIR register  ********************/

+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)

+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */

+

+/********************  Bit definition forUSB_OTG_HFNUM register  ********************/

+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)

+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */

+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)

+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */

+

+/********************  Bit definition forUSB_OTG_DSTS register  ********************/

+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)

+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */

+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */

+

+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)

+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */

+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */

+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */

+#define USB_OTG_DSTS_EERR_Pos                    (3U)

+#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */

+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */

+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)

+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */

+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */

+

+/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/

+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)

+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */

+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */

+

+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)

+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */

+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */

+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */

+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */

+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */

+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */

+#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */

+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)

+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */

+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */

+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)

+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */

+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */

+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)

+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */

+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */

+

+/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/

+

+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)

+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */

+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */

+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */

+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */

+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */

+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)

+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */

+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */

+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)

+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */

+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */

+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)

+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */

+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */

+

+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)

+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */

+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */

+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */

+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */

+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */

+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */

+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)

+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */

+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */

+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)

+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */

+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */

+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)

+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */

+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */

+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)

+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */

+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */

+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)

+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */

+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */

+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)

+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */

+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */

+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)

+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */

+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */

+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)

+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */

+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */

+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)

+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */

+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */

+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)

+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */

+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */

+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)

+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */

+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */

+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)

+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */

+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */

+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)

+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */

+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */

+

+/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/

+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)

+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */

+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */

+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)

+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */

+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */

+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)

+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */

+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */

+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)

+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */

+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */

+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)

+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */

+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */

+

+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)

+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */

+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */

+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */

+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */

+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */

+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */

+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */

+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)

+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */

+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */

+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)

+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */

+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */

+

+/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/

+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)

+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */

+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)

+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */

+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)

+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */

+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)

+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */

+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)

+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */

+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)

+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */

+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)

+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */

+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)

+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */

+

+/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/

+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)

+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */

+

+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)

+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */

+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */

+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */

+

+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)

+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */

+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */

+

+/********************  Bit definition forUSB_OTG_HAINT register  ********************/

+#define USB_OTG_HAINT_HAINT_Pos                  (0U)

+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */

+

+/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/

+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)

+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */

+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)

+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */

+#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)

+#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */

+#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask               */

+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)

+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */

+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)

+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */

+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)

+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */

+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)

+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */

+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)

+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */

+#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)

+#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */

+#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)

+#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask               */

+#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)

+#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask               */

+#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)

+#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                */

+

+/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/

+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)

+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */

+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */

+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)

+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */

+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */

+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)

+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */

+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */

+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)

+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */

+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */

+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)

+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */

+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */

+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)

+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */

+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */

+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)

+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */

+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */

+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)

+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */

+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */

+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)

+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */

+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */

+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)

+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */

+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */

+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)

+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */

+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */

+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)

+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */

+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */

+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)

+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */

+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */

+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)

+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */

+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */

+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)

+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */

+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */

+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)

+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */

+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */

+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)

+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */

+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */

+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)

+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */

+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */

+#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)

+#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */

+#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */

+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)

+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */

+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */

+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)

+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */

+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */

+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)

+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */

+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */

+#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)

+#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */

+#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */

+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)

+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */

+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */

+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)

+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */

+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */

+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)

+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */

+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */

+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)

+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */

+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */

+

+/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/

+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)

+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */

+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */

+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)

+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */

+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */

+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)

+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */

+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */

+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)

+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */

+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */

+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)

+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */

+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */

+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)

+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */

+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */

+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)

+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */

+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */

+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)

+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */

+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */

+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)

+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */

+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */

+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)

+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */

+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */

+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)

+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */

+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */

+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)

+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */

+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */

+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)

+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */

+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */

+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)

+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */

+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */

+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)

+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */

+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */

+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)

+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */

+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */

+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)

+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */

+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */

+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)

+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */

+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */

+#define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)

+#define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */

+#define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */

+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)

+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */

+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */

+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)

+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */

+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */

+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)

+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */

+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */

+#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)

+#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */

+#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */

+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)

+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */

+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */

+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)

+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */

+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */

+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)

+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */

+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */

+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)

+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */

+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */

+

+/********************  Bit definition forUSB_OTG_DAINT register  ********************/

+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)

+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */

+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)

+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */

+

+/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/

+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)

+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */

+

+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/

+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)

+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */

+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */

+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)

+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */

+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */

+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)

+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */

+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */

+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)

+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */

+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */

+

+/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/

+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)

+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */

+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)

+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */

+

+/********************  Bit definition for OTG register  ********************/

+

+#define USB_OTG_CHNUM_Pos                        (0U)

+#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)  /*!< 0x0000000F */

+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */

+#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */

+#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */

+#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */

+#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */

+#define USB_OTG_BCNT_Pos                         (4U)

+#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */

+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */

+

+#define USB_OTG_DPID_Pos                         (15U)

+#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)   /*!< 0x00018000 */

+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */

+#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */

+#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */

+

+#define USB_OTG_PKTSTS_Pos                       (17U)

+#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */

+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */

+#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */

+#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */

+#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */

+#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */

+

+#define USB_OTG_EPNUM_Pos                        (0U)

+#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)  /*!< 0x0000000F */

+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */

+#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */

+#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */

+#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */

+#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */

+

+#define USB_OTG_FRMNUM_Pos                       (21U)

+#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */

+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */

+#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */

+#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */

+#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */

+#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */

+

+/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/

+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)

+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/

+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)

+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */

+

+/********************  Bit definition for OTG register  ********************/

+#define USB_OTG_NPTXFSA_Pos                      (0U)

+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */

+#define USB_OTG_NPTXFD_Pos                       (16U)

+#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */

+#define USB_OTG_TX0FSA_Pos                       (0U)

+#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */

+#define USB_OTG_TX0FD_Pos                        (16U)

+#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */

+

+/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/

+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)

+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */

+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */

+

+/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/

+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)

+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */

+

+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)

+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */

+

+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)

+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/

+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)

+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */

+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */

+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)

+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */

+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */

+

+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)

+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */

+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */

+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */

+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)

+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */

+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */

+

+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)

+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */

+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */

+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)

+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */

+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */

+

+/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */

+

+/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/

+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)

+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */

+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */

+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)

+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */

+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */

+

+/********************  Bit definition forUSB_OTG_GCCFG register  ********************/

+#define USB_OTG_GCCFG_DCDET_Pos                  (0U)

+#define USB_OTG_GCCFG_DCDET_Msk                  (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */

+#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */

+#define USB_OTG_GCCFG_PDET_Pos                   (1U)

+#define USB_OTG_GCCFG_PDET_Msk                   (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */

+#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */

+#define USB_OTG_GCCFG_SDET_Pos                   (2U)

+#define USB_OTG_GCCFG_SDET_Msk                   (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */

+#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */

+#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)

+#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */

+#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */

+#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)

+#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */

+#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */

+#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)

+#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */

+#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */

+#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)

+#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */

+#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/

+#define USB_OTG_GCCFG_PDEN_Pos                   (19U)

+#define USB_OTG_GCCFG_PDEN_Msk                   (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */

+#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/

+#define USB_OTG_GCCFG_SDEN_Pos                   (20U)

+#define USB_OTG_GCCFG_SDEN_Msk                   (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */

+#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */

+#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)

+#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */

+#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */

+

+/********************  Bit definition forUSB_OTG_GPWRDN) register  ********************/

+#define USB_OTG_GPWRDN_ADPMEN_Pos                (0U)

+#define USB_OTG_GPWRDN_ADPMEN_Msk                (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */

+#define USB_OTG_GPWRDN_ADPMEN                    USB_OTG_GPWRDN_ADPMEN_Msk     /*!< ADP module enable */

+#define USB_OTG_GPWRDN_ADPIF_Pos                 (23U)

+#define USB_OTG_GPWRDN_ADPIF_Msk                 (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */

+#define USB_OTG_GPWRDN_ADPIF                     USB_OTG_GPWRDN_ADPIF_Msk      /*!< ADP Interrupt flag */

+

+/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/

+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)

+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */

+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)

+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */

+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */

+

+/********************  Bit definition forUSB_OTG_CID register  ********************/

+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)

+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */

+

+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/

+#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)

+#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */

+#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */

+#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)

+#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */

+#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */

+#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)

+#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */

+#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */

+#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)

+#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */

+#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */

+#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)

+#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */

+#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */

+#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)

+#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */

+#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */

+#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)

+#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */

+#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */

+#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)

+#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */

+#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */

+#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)

+#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */

+#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */

+#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)

+#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */

+#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */

+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)

+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */

+#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */

+#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)

+#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */

+#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */

+#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)

+#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */

+#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */

+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)

+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */

+#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */

+#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)

+#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */

+#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */

+

+/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/

+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)

+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */

+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)

+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */

+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)

+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */

+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)

+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */

+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)

+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */

+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)

+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */

+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)

+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */

+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)

+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */

+

+/********************  Bit definition forUSB_OTG_HPRT register  ********************/

+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)

+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */

+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */

+#define USB_OTG_HPRT_PCDET_Pos                   (1U)

+#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */

+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */

+#define USB_OTG_HPRT_PENA_Pos                    (2U)

+#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */

+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */

+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)

+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */

+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */

+#define USB_OTG_HPRT_POCA_Pos                    (4U)

+#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */

+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */

+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)

+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */

+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */

+#define USB_OTG_HPRT_PRES_Pos                    (6U)

+#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */

+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume   */

+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)

+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */

+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend  */

+#define USB_OTG_HPRT_PRST_Pos                    (8U)

+#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */

+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset    */

+

+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)

+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */

+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */

+#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */

+#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */

+#define USB_OTG_HPRT_PPWR_Pos                    (12U)

+#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */

+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */

+

+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)

+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */

+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */

+#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */

+#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */

+#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */

+#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */

+

+#define USB_OTG_HPRT_PSPD_Pos                    (17U)

+#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */

+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */

+#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */

+#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */

+

+/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/

+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)

+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)

+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)

+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */

+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)

+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */

+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)

+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */

+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)

+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */

+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)

+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)

+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)

+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)

+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */

+

+/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/

+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)

+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */

+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)

+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/

+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)

+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */

+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)

+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */

+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */

+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)

+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */

+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */

+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)

+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */

+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */

+

+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)

+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */

+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */

+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)

+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */

+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */

+

+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)

+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */

+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */

+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */

+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */

+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */

+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */

+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)

+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */

+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */

+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)

+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */

+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */

+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)

+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */

+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)

+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */

+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)

+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */

+

+/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/

+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)

+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */

+

+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)

+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */

+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */

+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */

+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */

+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */

+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */

+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)

+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */

+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */

+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)

+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */

+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */

+

+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)

+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */

+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */

+

+#define USB_OTG_HCCHAR_MC_Pos                    (20U)

+#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */

+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */

+#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */

+#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */

+

+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)

+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */

+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */

+#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */

+#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */

+#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */

+#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */

+#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */

+#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */

+#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */

+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)

+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */

+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)

+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */

+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)

+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */

+

+/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/

+

+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)

+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */

+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */

+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */

+

+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)

+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */

+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */

+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */

+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */

+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */

+

+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)

+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */

+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */

+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */

+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */

+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)

+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */

+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */

+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)

+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */

+

+/********************  Bit definition forUSB_OTG_HCINT register  ********************/

+#define USB_OTG_HCINT_XFRC_Pos                   (0U)

+#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */

+#define USB_OTG_HCINT_CHH_Pos                    (1U)

+#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */

+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)

+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */

+#define USB_OTG_HCINT_STALL_Pos                  (3U)

+#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */

+#define USB_OTG_HCINT_NAK_Pos                    (4U)

+#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */

+#define USB_OTG_HCINT_ACK_Pos                    (5U)

+#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */

+#define USB_OTG_HCINT_NYET_Pos                   (6U)

+#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */

+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */

+#define USB_OTG_HCINT_TXERR_Pos                  (7U)

+#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */

+#define USB_OTG_HCINT_BBERR_Pos                  (8U)

+#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */

+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)

+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */

+#define USB_OTG_HCINT_DTERR_Pos                  (10U)

+#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */

+

+/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/

+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)

+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */

+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)

+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */

+#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)

+#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */

+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)

+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */

+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)

+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */

+#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)

+#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */

+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)

+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */

+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)

+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */

+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */

+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)

+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */

+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)

+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */

+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)

+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */

+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */

+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)

+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */

+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */

+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)

+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */

+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */

+

+/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/

+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)

+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */

+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)

+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */

+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)

+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */

+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)

+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */

+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)

+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */

+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)

+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */

+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)

+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */

+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */

+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)

+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */

+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)

+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */

+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)

+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */

+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)

+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */

+

+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/

+

+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)

+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */

+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)

+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */

+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)

+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */

+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */

+/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/

+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)

+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */

+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)

+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */

+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)

+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */

+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)

+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */

+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */

+#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */

+#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/

+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)

+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */

+

+/********************  Bit definition forUSB_OTG_HCDMA register  ********************/

+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)

+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */

+

+/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/

+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)

+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */

+

+/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/

+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)

+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */

+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)

+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/

+

+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)

+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */

+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)

+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */

+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */

+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)

+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */

+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */

+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)

+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */

+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)

+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */

+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */

+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)

+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */

+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */

+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)

+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */

+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */

+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)

+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */

+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */

+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)

+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */

+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */

+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)

+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */

+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)

+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */

+

+/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/

+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)

+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */

+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)

+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */

+#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)

+#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */

+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)

+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */

+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)

+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */

+#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)

+#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< OUT Status Phase Received interrupt */

+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)

+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */

+#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)

+#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */

+#define USB_OTG_DOEPINT_BERR_Pos                 (12U)

+#define USB_OTG_DOEPINT_BERR_Msk                 (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPINT_BERR                      USB_OTG_DOEPINT_BERR_Msk   /*!< Babble error interrupt */

+#define USB_OTG_DOEPINT_NAK_Pos                  (13U)

+#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */

+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)

+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */

+#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)

+#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */

+#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */

+

+/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/

+

+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)

+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */

+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)

+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */

+

+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)

+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */

+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */

+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */

+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition for PCGCCTL register  ********************/

+#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)

+#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */

+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */

+#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)

+#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */

+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */

+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)

+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */

+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/** @addtogroup Exported_macros

+  * @{

+  */

+

+/******************************* ADC Instances ********************************/

+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \

+                                       ((INSTANCE) == ADC2) || \

+                                       ((INSTANCE) == ADC3))

+

+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)

+

+#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) ||\

+                                          ((INSTANCE) == ADC3_COMMON))

+

+/******************************** COMP Instances ******************************/

+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \

+                                       ((INSTANCE) == COMP2))

+

+#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)

+/******************** COMP Instances with window mode capability **************/

+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)

+

+

+/******************************* CRC Instances ********************************/

+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

+

+/******************************* DAC Instances ********************************/

+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)

+/******************************* DCMI Instances *******************************/

+#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)

+

+/******************************* DELAYBLOCK Instances *******************************/

+#define IS_DLYB_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DLYB_SDMMC1) || \

+                                         ((INSTANCE) == DLYB_SDMMC2) || \

+                                         ((INSTANCE) == DLYB_QUADSPI))

+/****************************** DFSDM Instances *******************************/

+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \

+                                               ((INSTANCE) == DFSDM1_Filter1) || \

+                                               ((INSTANCE) == DFSDM1_Filter2) || \

+                                               ((INSTANCE) == DFSDM1_Filter3))

+

+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \

+                                                 ((INSTANCE) == DFSDM1_Channel1) || \

+                                                 ((INSTANCE) == DFSDM1_Channel2) || \

+                                                 ((INSTANCE) == DFSDM1_Channel3) || \

+                                                 ((INSTANCE) == DFSDM1_Channel4) || \

+                                                 ((INSTANCE) == DFSDM1_Channel5) || \

+                                                 ((INSTANCE) == DFSDM1_Channel6) || \

+                                                 ((INSTANCE) == DFSDM1_Channel7))

+/****************************** RAMECC Instances ******************************/

+#define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC1_Monitor1)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor2)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor3)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor4)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor5)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor1)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor2)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor3)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor4)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor5)   || \

+                                                  ((INSTANCE) == RAMECC3_Monitor1)   || \

+                                                  ((INSTANCE) == RAMECC3_Monitor2))

+

+/******************************** DMA Instances *******************************/

+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \

+                                       ((INSTANCE) == DMA1_Stream1)   || \

+                                       ((INSTANCE) == DMA1_Stream2)   || \

+                                       ((INSTANCE) == DMA1_Stream3)   || \

+                                       ((INSTANCE) == DMA1_Stream4)   || \

+                                       ((INSTANCE) == DMA1_Stream5)   || \

+                                       ((INSTANCE) == DMA1_Stream6)   || \

+                                       ((INSTANCE) == DMA1_Stream7)   || \

+                                       ((INSTANCE) == DMA2_Stream0)   || \

+                                       ((INSTANCE) == DMA2_Stream1)   || \

+                                       ((INSTANCE) == DMA2_Stream2)   || \

+                                       ((INSTANCE) == DMA2_Stream3)   || \

+                                       ((INSTANCE) == DMA2_Stream4)   || \

+                                       ((INSTANCE) == DMA2_Stream5)   || \

+                                       ((INSTANCE) == DMA2_Stream6)   || \

+                                       ((INSTANCE) == DMA2_Stream7)   || \

+                                       ((INSTANCE) == BDMA_Channel0) || \

+                                       ((INSTANCE) == BDMA_Channel1) || \

+                                       ((INSTANCE) == BDMA_Channel2) || \

+                                       ((INSTANCE) == BDMA_Channel3) || \

+                                       ((INSTANCE) == BDMA_Channel4) || \

+                                       ((INSTANCE) == BDMA_Channel5) || \

+                                       ((INSTANCE) == BDMA_Channel6) || \

+                                       ((INSTANCE) == BDMA_Channel7))

+

+/****************************** BDMA CHANNEL Instances ***************************/

+#define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \

+                                            ((INSTANCE) == BDMA_Channel1) || \

+                                            ((INSTANCE) == BDMA_Channel2) || \

+                                            ((INSTANCE) == BDMA_Channel3) || \

+                                            ((INSTANCE) == BDMA_Channel4) || \

+                                            ((INSTANCE) == BDMA_Channel5) || \

+                                            ((INSTANCE) == BDMA_Channel6) || \

+                                            ((INSTANCE) == BDMA_Channel7))

+

+/****************************** DMA DMAMUX ALL Instances ***************************/

+#define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)    || \

+                                               ((INSTANCE) == DMA1_Stream1)    || \

+                                               ((INSTANCE) == DMA1_Stream2)    || \

+                                               ((INSTANCE) == DMA1_Stream3)    || \

+                                               ((INSTANCE) == DMA1_Stream4)    || \

+                                               ((INSTANCE) == DMA1_Stream5)    || \

+                                               ((INSTANCE) == DMA1_Stream6)    || \

+                                               ((INSTANCE) == DMA1_Stream7)    || \

+                                               ((INSTANCE) == DMA2_Stream0)    || \

+                                               ((INSTANCE) == DMA2_Stream1)    || \

+                                               ((INSTANCE) == DMA2_Stream2)    || \

+                                               ((INSTANCE) == DMA2_Stream3)    || \

+                                               ((INSTANCE) == DMA2_Stream4)    || \

+                                               ((INSTANCE) == DMA2_Stream5)    || \

+                                               ((INSTANCE) == DMA2_Stream6)    || \

+                                               ((INSTANCE) == DMA2_Stream7)    || \

+                                               ((INSTANCE) == BDMA_Channel0)   || \

+                                               ((INSTANCE) == BDMA_Channel1)   || \

+                                               ((INSTANCE) == BDMA_Channel2)   || \

+                                               ((INSTANCE) == BDMA_Channel3)   || \

+                                               ((INSTANCE) == BDMA_Channel4)   || \

+                                               ((INSTANCE) == BDMA_Channel5)   || \

+                                               ((INSTANCE) == BDMA_Channel6)   || \

+                                               ((INSTANCE) == BDMA_Channel7))

+

+/****************************** BDMA DMAMUX Instances ***************************/

+#define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == BDMA_Channel0) || \

+                                                    ((INSTANCE) == BDMA_Channel1) || \

+                                                    ((INSTANCE) == BDMA_Channel2) || \

+                                                    ((INSTANCE) == BDMA_Channel3) || \

+                                                    ((INSTANCE) == BDMA_Channel4) || \

+                                                    ((INSTANCE) == BDMA_Channel5) || \

+                                                    ((INSTANCE) == BDMA_Channel6) || \

+                                                    ((INSTANCE) == BDMA_Channel7))

+

+/****************************** DMA STREAM Instances ***************************/

+#define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \

+                                          ((INSTANCE) == DMA1_Stream1)   || \

+                                          ((INSTANCE) == DMA1_Stream2)   || \

+                                          ((INSTANCE) == DMA1_Stream3)   || \

+                                          ((INSTANCE) == DMA1_Stream4)   || \

+                                          ((INSTANCE) == DMA1_Stream5)   || \

+                                          ((INSTANCE) == DMA1_Stream6)   || \

+                                          ((INSTANCE) == DMA1_Stream7)   || \

+                                          ((INSTANCE) == DMA2_Stream0)   || \

+                                          ((INSTANCE) == DMA2_Stream1)   || \

+                                          ((INSTANCE) == DMA2_Stream2)   || \

+                                          ((INSTANCE) == DMA2_Stream3)   || \

+                                          ((INSTANCE) == DMA2_Stream4)   || \

+                                          ((INSTANCE) == DMA2_Stream5)   || \

+                                          ((INSTANCE) == DMA2_Stream6)   || \

+                                          ((INSTANCE) == DMA2_Stream7))

+

+/****************************** DMA DMAMUX Instances ***************************/

+#define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)   || \

+                                                  ((INSTANCE) == DMA1_Stream1)   || \

+                                                  ((INSTANCE) == DMA1_Stream2)   || \

+                                                  ((INSTANCE) == DMA1_Stream3)   || \

+                                                  ((INSTANCE) == DMA1_Stream4)   || \

+                                                  ((INSTANCE) == DMA1_Stream5)   || \

+                                                  ((INSTANCE) == DMA1_Stream6)   || \

+                                                  ((INSTANCE) == DMA1_Stream7)   || \

+                                                  ((INSTANCE) == DMA2_Stream0)   || \

+                                                  ((INSTANCE) == DMA2_Stream1)   || \

+                                                  ((INSTANCE) == DMA2_Stream2)   || \

+                                                  ((INSTANCE) == DMA2_Stream3)   || \

+                                                  ((INSTANCE) == DMA2_Stream4)   || \

+                                                  ((INSTANCE) == DMA2_Stream5)   || \

+                                                  ((INSTANCE) == DMA2_Stream6)   || \

+                                                  ((INSTANCE) == DMA2_Stream7))

+

+/******************************** DMA Request Generator Instances **************/

+#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator1) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator2) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator3) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator4) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator5) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator6) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator7) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator0) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator1) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator2) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator3) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator4) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator5) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator6) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator7))

+

+/******************************* DMA2D Instances *******************************/

+#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)

+

+/******************************** MDMA Request Generator Instances **************/

+#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0)  || \

+                                               ((INSTANCE) == MDMA_Channel1)  || \

+                                               ((INSTANCE) == MDMA_Channel2)  || \

+                                               ((INSTANCE) == MDMA_Channel3)  || \

+                                               ((INSTANCE) == MDMA_Channel4)  || \

+                                               ((INSTANCE) == MDMA_Channel5)  || \

+                                               ((INSTANCE) == MDMA_Channel6)  || \

+                                               ((INSTANCE) == MDMA_Channel7)  || \

+                                               ((INSTANCE) == MDMA_Channel8)  || \

+                                               ((INSTANCE) == MDMA_Channel9)  || \

+                                               ((INSTANCE) == MDMA_Channel10) || \

+                                               ((INSTANCE) == MDMA_Channel11) || \

+                                               ((INSTANCE) == MDMA_Channel12) || \

+                                               ((INSTANCE) == MDMA_Channel13) || \

+                                               ((INSTANCE) == MDMA_Channel14) || \

+                                               ((INSTANCE) == MDMA_Channel15))

+

+/******************************* QUADSPI Instances *******************************/

+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)

+

+/******************************* FDCAN Instances ******************************/

+#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \

+                                             ((__INSTANCE__) == FDCAN2))

+

+#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)

+

+/******************************* GPIO Instances *******************************/

+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \

+                                        ((INSTANCE) == GPIOB) || \

+                                        ((INSTANCE) == GPIOC) || \

+                                        ((INSTANCE) == GPIOD) || \

+                                        ((INSTANCE) == GPIOE) || \

+                                        ((INSTANCE) == GPIOF) || \

+                                        ((INSTANCE) == GPIOG) || \

+                                        ((INSTANCE) == GPIOH) || \

+                                        ((INSTANCE) == GPIOI) || \

+                                        ((INSTANCE) == GPIOJ) || \

+                                        ((INSTANCE) == GPIOK))

+

+/******************************* GPIO AF Instances ****************************/

+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)

+

+/**************************** GPIO Lock Instances *****************************/

+/* On H7, all GPIO Bank support the Lock mechanism */

+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)

+

+/******************************** HSEM Instances *******************************/

+#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)

+/********************  Bit definition for HSEM_CR register  *****************/

+#define HSEM_CPU1_COREID    (0x00000003U) /* Semaphore Core CM7 ID */

+#define HSEM_CPU2_COREID    (0x00000001U) /* Semaphore Core CM4 ID */

+#define HSEM_CR_COREID_CPU1      (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)

+#define HSEM_CR_COREID_CPU2      (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos)

+#if defined(CORE_CM4)

+#define HSEM_CR_COREID_CURRENT   (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos)

+#else  /* CORE_CM7 */

+#define HSEM_CR_COREID_CURRENT   (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)

+#endif /* CORE_CM4 */

+

+#define HSEM_SEMID_MIN     (0U)       /* HSEM ID Min*/

+#define HSEM_SEMID_MAX     (31U)      /* HSEM ID Max */

+

+#define HSEM_PROCESSID_MIN (0U)       /* HSEM Process ID Min */

+#define HSEM_PROCESSID_MAX (255U)     /* HSEM Process ID Max */

+

+#define HSEM_CLEAR_KEY_MIN (0U)       /* HSEM clear Key Min value */

+#define HSEM_CLEAR_KEY_MAX (0xFFFFU)  /* HSEM clear Key Max value */

+

+/******************************** I2C Instances *******************************/

+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

+                                       ((INSTANCE) == I2C2) || \

+                                       ((INSTANCE) == I2C3) || \

+                                       ((INSTANCE) == I2C4))

+/************** I2C Instances : wakeup capability from stop modes *************/

+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)

+

+/****************************** SMBUS Instances *******************************/

+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

+                                         ((INSTANCE) == I2C2) || \

+                                         ((INSTANCE) == I2C3) || \

+                                         ((INSTANCE) == I2C4))

+/******************************** I2S Instances *******************************/

+#define IS_I2S_ALL_INSTANCE(INSTANCE)   (((INSTANCE) == SPI1) || \

+                                         ((INSTANCE) == SPI2) || \

+                                         ((INSTANCE) == SPI3))

+

+/****************************** LTDC Instances ********************************/

+#define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)

+

+/******************************* RNG Instances ********************************/

+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)

+

+/****************************** RTC Instances *********************************/

+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)

+

+/****************************** SDMMC Instances *********************************/

+#define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \

+                                           ((_INSTANCE_) == SDMMC2))

+

+/******************************** SMBUS Instances *****************************/

+#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)

+

+/******************************** SPI Instances *******************************/

+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \

+                                       ((INSTANCE) == SPI2) || \

+                                       ((INSTANCE) == SPI3) || \

+                                       ((INSTANCE) == SPI4) || \

+                                       ((INSTANCE) == SPI5) || \

+                                       ((INSTANCE) == SPI6))

+

+#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \

+                                           ((INSTANCE) == SPI2) || \

+                                           ((INSTANCE) == SPI3))

+

+/******************************** SWPMI Instances *****************************/

+#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)

+

+/****************** LPTIM Instances : All supported instances *****************/

+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \

+                                         ((INSTANCE) == LPTIM2) || \

+                                         ((INSTANCE) == LPTIM3) || \

+                                         ((INSTANCE) == LPTIM4) || \

+                                         ((INSTANCE) == LPTIM5))

+

+/****************** LPTIM Instances : supporting encoder interface **************/

+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \

+                                                           ((INSTANCE) == LPTIM2))

+

+/****************** TIM Instances : All supported instances *******************/

+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM6)   || \

+                                         ((INSTANCE) == TIM7)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM13)  || \

+                                         ((INSTANCE) == TIM14)  || \

+                                         ((INSTANCE) == TIM15)  || \

+                                         ((INSTANCE) == TIM16)  || \

+                                         ((INSTANCE) == TIM17))

+

+/************* TIM Instances : at least 1 capture/compare channel *************/

+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM13)  || \

+                                         ((INSTANCE) == TIM14)  || \

+                                         ((INSTANCE) == TIM15)  || \

+                                         ((INSTANCE) == TIM16)  || \

+                                         ((INSTANCE) == TIM17))

+

+/************ TIM Instances : at least 2 capture/compare channels *************/

+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM15))

+

+/************ TIM Instances : at least 3 capture/compare channels *************/

+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8))

+

+/************ TIM Instances : at least 4 capture/compare channels *************/

+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8))

+

+/************ TIM Instances : at least 5 capture/compare channels *************/

+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM8))

+/************ TIM Instances : at least 6 capture/compare channels *************/

+#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM8))

+

+/******************** TIM Instances : Advanced-control timers *****************/

+#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \

+                                                ((__INSTANCE__) == TIM8))

+

+/******************** TIM Instances : Advanced-control timers *****************/

+

+/******************* TIM Instances : Timer input XOR function *****************/

+#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : DMA requests generation (UDE) *************/

+#define IS_TIM_DMA_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM6)   || \

+                                           ((INSTANCE) == TIM7)   || \

+                                           ((INSTANCE) == TIM8)   || \

+                                           ((INSTANCE) == TIM15)  || \

+                                           ((INSTANCE) == TIM16)  || \

+                                           ((INSTANCE) == TIM17))

+

+/************ TIM Instances : DMA requests generation (CCxDE) *****************/

+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15)  || \

+                                            ((INSTANCE) == TIM16)  || \

+                                            ((INSTANCE) == TIM17))

+

+/************ TIM Instances : DMA requests generation (COMDE) *****************/

+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15))

+

+/******************** TIM Instances : DMA burst feature ***********************/

+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8))

+

+/*************** TIM Instances : external trigger reamp input available *******/

+#define IS_TIM_ETR_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : remapping capability **********************/

+#define IS_TIM_REMAP_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \

+                                          ((INSTANCE) == TIM2)  || \

+                                          ((INSTANCE) == TIM3)  || \

+                                          ((INSTANCE) == TIM5)  || \

+                                          ((INSTANCE) == TIM8)  || \

+                                          ((INSTANCE) == TIM16) || \

+                                          ((INSTANCE) == TIM17))

+

+/*************** TIM Instances : external trigger reamp input available *******/

+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                              ((INSTANCE) == TIM2)   || \

+                                              ((INSTANCE) == TIM3)   || \

+                                              ((INSTANCE) == TIM5)   || \

+                                              ((INSTANCE) == TIM8))

+

+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/

+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM6)   || \

+                                            ((INSTANCE) == TIM7)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15))

+

+/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/

+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM8)   || \

+                                           ((INSTANCE) == TIM12))

+

+/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/

+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM8))

+

+/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/

+#define IS_TIM_TISEL_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)   || \

+                                          ((INSTANCE) == TIM2)   || \

+                                          ((INSTANCE) == TIM3)   || \

+                                          ((INSTANCE) == TIM4)   || \

+                                          ((INSTANCE) == TIM5)   || \

+                                          ((INSTANCE) == TIM8)   || \

+                                          ((INSTANCE) == TIM15)  || \

+                                          ((INSTANCE) == TIM16)  || \

+                                          ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting commutation event *************/

+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \

+                                                     ((INSTANCE) == TIM8)    || \

+                                                     ((INSTANCE) == TIM15)   || \

+                                                     ((INSTANCE) == TIM16)   || \

+                                                     ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting encoder interface **************/

+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1)  || \

+                                                      ((__INSTANCE__) == TIM2)      || \

+                                                      ((__INSTANCE__) == TIM3)      || \

+                                                      ((__INSTANCE__) == TIM4)      || \

+                                                      ((__INSTANCE__) == TIM5)      || \

+                                                      ((__INSTANCE__) == TIM8))

+

+/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/

+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                                       ((INSTANCE) == TIM8))

+/******************* TIM Instances : output(s) available **********************/

+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \

+    ((((INSTANCE) == TIM1) &&                  \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4) ||          \

+      ((CHANNEL) == TIM_CHANNEL_5) ||          \

+      ((CHANNEL) == TIM_CHANNEL_6)))           \

+     ||                                        \

+     (((INSTANCE) == TIM2) &&                  \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM3) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1)||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM4) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM5) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM8) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4) ||          \

+      ((CHANNEL) == TIM_CHANNEL_5) ||          \

+      ((CHANNEL) == TIM_CHANNEL_6)))           \

+  ||                                           \

+     (((INSTANCE) == TIM12) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2)))           \

+  ||                                           \

+     (((INSTANCE) == TIM13) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM14) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM15) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+     ((CHANNEL) == TIM_CHANNEL_2)))            \

+  ||                                           \

+     (((INSTANCE) == TIM16) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM17) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1))))

+

+/****************** TIM Instances : supporting the break function *************/

+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\

+      (((INSTANCE) == TIM1)    || \

+      ((INSTANCE) == TIM8)     || \

+       ((INSTANCE) == TIM15)   || \

+       ((INSTANCE) == TIM16)   || \

+       ((INSTANCE) == TIM17))

+

+/************** TIM Instances : supporting Break source selection *************/

+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \

+                                               ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting complementary output(s) ********/

+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \

+   ((((INSTANCE) == TIM1) &&                    \

+     (((CHANNEL) == TIM_CHANNEL_1) ||           \

+      ((CHANNEL) == TIM_CHANNEL_2) ||           \

+      ((CHANNEL) == TIM_CHANNEL_3)))            \

+ ||                                             \

+      (((INSTANCE) == TIM8) &&                  \

+      (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||           \

+      ((CHANNEL) == TIM_CHANNEL_3)))            \

+    ||                                          \

+    (((INSTANCE) == TIM15) &&                   \

+      ((CHANNEL) == TIM_CHANNEL_1))             \

+    ||                                          \

+    (((INSTANCE) == TIM16) &&                   \

+     ((CHANNEL) == TIM_CHANNEL_1))              \

+    ||                                          \

+    (((INSTANCE) == TIM17) &&                   \

+     ((CHANNEL) == TIM_CHANNEL_1)))

+

+/****************** TIM Instances : supporting counting mode selection ********/

+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting repetition counter *************/

+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15)   || \

+   ((INSTANCE) == TIM16)   || \

+   ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting synchronization ****************/

+#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\

+    (((__INSTANCE__) == TIM1)    || \

+     ((__INSTANCE__) == TIM2)    || \

+     ((__INSTANCE__) == TIM3)    || \

+     ((__INSTANCE__) == TIM4)    || \

+     ((__INSTANCE__) == TIM5)    || \

+     ((__INSTANCE__) == TIM6)    || \

+     ((__INSTANCE__) == TIM8)    || \

+     ((__INSTANCE__) == TIM12)   || \

+     ((__INSTANCE__) == TIM15))

+

+/****************** TIM Instances : supporting clock division *****************/

+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15)   || \

+   ((INSTANCE) == TIM16)   || \

+   ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting external clock mode 1 for ETRF input */

+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting external clock mode 2 **********/

+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\

+ (((INSTANCE) == TIM1)     || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/

+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/

+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : supporting OCxREF clear *******************/

+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3))

+

+/****************** TIM Instances : TIM_32B_COUNTER ***************************/

+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM5))

+

+/****************** TIM Instances : TIM_BKIN2 ***************************/

+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting Hall sensor interface **********/

+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)  || \

+                                                             ((__INSTANCE__) == TIM2)  || \

+                                                             ((__INSTANCE__) == TIM3)  || \

+                                                             ((__INSTANCE__) == TIM4)  || \

+                                                             ((__INSTANCE__) == TIM5)  || \

+                                                             ((__INSTANCE__) == TIM15) || \

+                                                             ((__INSTANCE__) == TIM8))

+

+/****************************** HRTIM Instances *******************************/

+#define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))

+

+/******************** USART Instances : Synchronous mode **********************/

+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                     ((INSTANCE) == USART2) || \

+                                     ((INSTANCE) == USART3) || \

+                                     ((INSTANCE) == USART6))

+

+/******************** USART Instances : SPI slave mode ************************/

+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                              ((INSTANCE) == USART2) || \

+                                              ((INSTANCE) == USART3) || \

+                                              ((INSTANCE) == USART6))

+

+/******************** UART Instances : Asynchronous mode **********************/

+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                    ((INSTANCE) == USART2) || \

+                                    ((INSTANCE) == USART3) || \

+                                    ((INSTANCE) == UART4)  || \

+                                    ((INSTANCE) == UART5)  || \

+                                    ((INSTANCE) == USART6) || \

+                                    ((INSTANCE) == UART7)  || \

+                                    ((INSTANCE) == UART8))

+

+/******************** UART Instances : FIFO mode.******************************/

+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                         ((INSTANCE) == USART2) || \

+                                         ((INSTANCE) == USART3) || \

+                                         ((INSTANCE) == UART4)  || \

+                                         ((INSTANCE) == UART5)  || \

+                                         ((INSTANCE) == USART6) || \

+                                         ((INSTANCE) == UART7)  || \

+                                         ((INSTANCE) == UART8))

+

+/****************** UART Instances : Auto Baud Rate detection *****************/

+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                            ((INSTANCE) == USART2) || \

+                                                            ((INSTANCE) == USART3) || \

+                                                            ((INSTANCE) == UART4)  || \

+                                                            ((INSTANCE) == UART5)  || \

+                                                            ((INSTANCE) == USART6) || \

+                                                            ((INSTANCE) == UART7)  || \

+                                                            ((INSTANCE) == UART8))

+

+/*********************** UART Instances : Driver Enable ***********************/

+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                  ((INSTANCE) == USART2) || \

+                                                  ((INSTANCE) == USART3) || \

+                                                  ((INSTANCE) == UART4)  || \

+                                                  ((INSTANCE) == UART5)  || \

+                                                  ((INSTANCE) == USART6) || \

+                                                  ((INSTANCE) == UART7)  || \

+                                                  ((INSTANCE) == UART8)  || \

+                                                  ((INSTANCE) == LPUART1))

+

+/********************* UART Instances : Half-Duplex mode **********************/

+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                               ((INSTANCE) == USART2) || \

+                                               ((INSTANCE) == USART3) || \

+                                               ((INSTANCE) == UART4)  || \

+                                               ((INSTANCE) == UART5)  || \

+                                               ((INSTANCE) == USART6) || \

+                                               ((INSTANCE) == UART7)  || \

+                                               ((INSTANCE) == UART8)  || \

+                                               ((INSTANCE) == LPUART1))

+

+/******************* UART Instances : Hardware Flow control *******************/

+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                           ((INSTANCE) == USART2) || \

+                                           ((INSTANCE) == USART3) || \

+                                           ((INSTANCE) == UART4)  || \

+                                           ((INSTANCE) == UART5)  || \

+                                           ((INSTANCE) == USART6) || \

+                                           ((INSTANCE) == UART7)  || \

+                                           ((INSTANCE) == UART8)  || \

+                                           ((INSTANCE) == LPUART1))

+

+/************************* UART Instances : LIN mode **************************/

+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                        ((INSTANCE) == USART2) || \

+                                        ((INSTANCE) == USART3) || \

+                                        ((INSTANCE) == UART4)  || \

+                                        ((INSTANCE) == UART5)  || \

+                                        ((INSTANCE) == USART6) || \

+                                        ((INSTANCE) == UART7)  || \

+                                        ((INSTANCE) == UART8))

+

+/****************** UART Instances : Wake-up from Stop mode *******************/

+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                    ((INSTANCE) == USART2) || \

+                                                    ((INSTANCE) == USART3) || \

+                                                    ((INSTANCE) == UART4)  || \

+                                                    ((INSTANCE) == UART5)  || \

+                                                    ((INSTANCE) == USART6) || \

+                                                    ((INSTANCE) == UART7)  || \

+                                                    ((INSTANCE) == UART8)  || \

+                                                    ((INSTANCE) == LPUART1))

+

+/************************* UART Instances : IRDA mode *************************/

+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                    ((INSTANCE) == USART2) || \

+                                    ((INSTANCE) == USART3) || \

+                                    ((INSTANCE) == UART4)  || \

+                                    ((INSTANCE) == UART5)  || \

+                                    ((INSTANCE) == USART6) || \

+                                    ((INSTANCE) == UART7)  || \

+                                    ((INSTANCE) == UART8))

+

+/********************* USART Instances : Smard card mode **********************/

+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                         ((INSTANCE) == USART2) || \

+                                         ((INSTANCE) == USART3) || \

+                                         ((INSTANCE) == USART6))

+

+/****************************** LPUART Instance *******************************/

+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)

+

+/****************************** IWDG Instances ********************************/

+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2))

+/****************************** USB Instances ********************************/

+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)

+

+/****************************** WWDG Instances ********************************/

+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == WWDG1) || \

+                                         ((INSTANCE) == WWDG2))

+/****************************** MDIOS Instances ********************************/

+#define IS_MDIOS_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == MDIOS)

+

+/****************************** CEC Instances *********************************/

+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)

+

+/****************************** SAI Instances ********************************/

+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \

+                    ((INSTANCE) == SAI1_Block_B) || \

+                     ((INSTANCE) == SAI2_Block_A) || \

+                     ((INSTANCE) == SAI2_Block_B) || \

+                     ((INSTANCE) == SAI3_Block_A) || \

+                     ((INSTANCE) == SAI3_Block_B) || \

+                     ((INSTANCE) == SAI4_Block_A) || \

+                     ((INSTANCE) == SAI4_Block_B))

+

+/****************************** SPDIFRX Instances ********************************/

+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)

+

+/****************************** OPAMP Instances *******************************/

+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \

+                                         ((INSTANCE) == OPAMP2))

+

+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)

+

+/*********************** USB OTG PCD Instances ********************************/

+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \

+                                        ((INSTANCE) == USB_OTG_HS))

+

+/*********************** USB OTG HCD Instances ********************************/

+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \

+                                       ((INSTANCE) == USB_OTG_HS))

+

+/******************************************************************************/

+/*  For a painless codes migration between the STM32H7xx device product       */

+/*  lines, or with STM32F7xx devices the aliases defined below are put        */

+/*   in place to overcome the differences in the interrupt handlers and IRQn  */

+/*   definitions. No need to update developed interrupt code when moving      */

+/*  across product lines within the same STM32H7 Family                       */

+/******************************************************************************/

+

+/* Aliases for __IRQn */

+#define  HASH_RNG_IRQn                  RNG_IRQn

+#define  TIM1_BRK_TIM9_IRQn             TIM1_BRK_IRQn

+#define  TIM1_UP_TIM10_IRQn             TIM1_UP_IRQn

+#define  TIM1_TRG_COM_TIM11_IRQn        TIM1_TRG_COM_IRQn

+#define  PVD_IRQn                       PVD_AVD_IRQn

+

+

+

+/* Aliases for __IRQHandler */

+#define  HASH_RNG_IRQHandler           RNG_IRQHandler

+#define TIM1_BRK_TIM9_IRQHandler       TIM1_BRK_IRQHandler

+#define TIM1_UP_TIM9_IRQHandler        TIM1_UP_IRQHandler

+#define TIM1_TRG_COM_TIM11_IRQHandler  TIM1_TRG_COM_IRQHandler

+#define PVD_IRQHandler                 PVD_AVD_IRQHandler

+

+/* Aliases for COMP __IRQHandler */

+#define COMP_IRQHandler                COMP1_IRQHandler

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif /* __cplusplus */

+

+#endif /* STM32H745xx_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h747xx.h b/bsps/arm/stm32h7/include/stm32h747xx.h
new file mode 100644
index 0000000000..4eb0aed444
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h747xx.h
@@ -0,0 +1,30234 @@
+/**

+  ******************************************************************************

+  * @file    stm32h747xx.h

+  * @author  MCD Application Team

+  * @brief   CMSIS STM32H747xx Device Peripheral Access Layer Header File.

+  *

+  *          This file contains:

+  *           - Data structures and the address mapping for all peripherals

+  *           - Peripheral's registers declarations and bits definition

+  *           - Macros to access peripheral's registers hardware

+  *

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/** @addtogroup CMSIS_Device

+  * @{

+  */

+

+/** @addtogroup stm32h747xx

+  * @{

+  */

+

+#ifndef STM32H747xx_H

+#define STM32H747xx_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif /* __cplusplus */

+

+/** @addtogroup Peripheral_interrupt_number_definition

+  * @{

+  */

+

+/**

+ * @brief STM32H7XX Interrupt Number Definition, according to the selected device

+ *        in @ref Library_configuration_section

+ */

+typedef enum

+{

+/******  Cortex-M Processor Exceptions Numbers *****************************************************************/

+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */

+  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */

+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */

+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */

+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */

+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M SV Call Interrupt                                     */

+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M Debug Monitor Interrupt                               */

+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M Pend SV Interrupt                                     */

+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M System Tick Interrupt                                 */

+/******  STM32 specific Interrupt Numbers **********************************************************************/

+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)                   */

+  PVD_AVD_IRQn                = 1,      /*!< PVD/AVD through EXTI Line detection Interrupt                     */

+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */

+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */

+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */

+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */

+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */

+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */

+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */

+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */

+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */

+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */

+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */

+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */

+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */

+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */

+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */

+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */

+  ADC_IRQn                    = 18,     /*!< ADC1 and  ADC2 global Interrupts                                  */

+  FDCAN1_IT0_IRQn             = 19,     /*!< FDCAN1 Interrupt line 0                                           */

+  FDCAN2_IT0_IRQn             = 20,     /*!< FDCAN2 Interrupt line 0                                           */

+  FDCAN1_IT1_IRQn             = 21,     /*!< FDCAN1 Interrupt line 1                                           */

+  FDCAN2_IT1_IRQn             = 22,     /*!< FDCAN2 Interrupt line 1                                           */

+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */

+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                              */

+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                             */

+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt                            */

+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */

+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */

+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */

+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */

+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */

+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */

+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */

+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */

+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */

+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */

+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */

+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */

+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */

+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */

+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */

+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */

+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */

+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */

+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */

+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */

+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */

+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */

+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */

+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */

+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */

+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */

+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */

+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */

+  DMA2_Stream0_IRQn           = 56,     /*!<   DMA2 Stream 0 global Interrupt                                  */

+  DMA2_Stream1_IRQn           = 57,     /*!<   DMA2 Stream 1 global Interrupt                                  */

+  DMA2_Stream2_IRQn           = 58,     /*!<   DMA2 Stream 2 global Interrupt                                  */

+  DMA2_Stream3_IRQn           = 59,     /*!<   DMA2 Stream 3 global Interrupt                                  */

+  DMA2_Stream4_IRQn           = 60,     /*!<   DMA2 Stream 4 global Interrupt                                  */

+  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */

+  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */

+  FDCAN_CAL_IRQn              = 63,     /*!< FDCAN Calibration unit Interrupt                                  */

+  CM7_SEV_IRQn                = 64,     /*!< CM7 Send event interrupt for CM4                                  */

+  CM4_SEV_IRQn                = 65,     /*!< CM4 Send event interrupt for CM7                                  */

+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */

+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */

+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */

+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */

+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */

+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */

+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */

+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */

+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */

+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */

+  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */

+  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */

+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */

+  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */

+  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */

+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */

+  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */

+  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */

+  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */

+  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */

+  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */

+  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */

+  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */

+  QUADSPI_IRQn                = 92,     /*!< Quad SPI global interrupt                                         */

+  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */

+  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */

+  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */

+  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */

+  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */

+  OTG_FS_EP1_OUT_IRQn         = 98,     /*!< USB OTG HS2 global interrupt                                      */

+  OTG_FS_EP1_IN_IRQn          = 99,     /*!< USB OTG HS2 End Point 1 Out global interrupt                      */

+  OTG_FS_WKUP_IRQn            = 100,    /*!< USB OTG HS2 End Point 1 In global interrupt                       */

+  OTG_FS_IRQn                 = 101,    /*!< USB OTG HS2 Wakeup through EXTI interrupt                         */

+  DMAMUX1_OVR_IRQn            = 102,    /*!<DMAMUX1 Overrun interrupt                                          */

+  HRTIM1_Master_IRQn          = 103,    /*!< HRTIM Master Timer global Interrupts                              */

+  HRTIM1_TIMA_IRQn            = 104,    /*!< HRTIM Timer A global Interrupt                                    */

+  HRTIM1_TIMB_IRQn            = 105,    /*!< HRTIM Timer B global Interrupt                                    */

+  HRTIM1_TIMC_IRQn            = 106,    /*!< HRTIM Timer C global Interrupt                                    */

+  HRTIM1_TIMD_IRQn            = 107,    /*!< HRTIM Timer D global Interrupt                                    */

+  HRTIM1_TIME_IRQn            = 108,    /*!< HRTIM Timer E global Interrupt                                    */

+  HRTIM1_FLT_IRQn             = 109,    /*!< HRTIM Fault global Interrupt                                      */

+  DFSDM1_FLT0_IRQn            = 110,    /*!<DFSDM Filter1 Interrupt                                            */

+  DFSDM1_FLT1_IRQn            = 111,    /*!<DFSDM Filter2 Interrupt                                            */

+  DFSDM1_FLT2_IRQn            = 112,    /*!<DFSDM Filter3 Interrupt                                            */

+  DFSDM1_FLT3_IRQn            = 113,    /*!<DFSDM Filter4 Interrupt                                            */

+  SAI3_IRQn                   = 114,    /*!< SAI3 global Interrupt                                             */

+  SWPMI1_IRQn                 = 115,    /*!< Serial Wire Interface 1 global interrupt                          */

+  TIM15_IRQn                  = 116,    /*!< TIM15 global Interrupt                                            */

+  TIM16_IRQn                  = 117,    /*!< TIM16 global Interrupt                                            */

+  TIM17_IRQn                  = 118,    /*!< TIM17 global Interrupt                                            */

+  MDIOS_WKUP_IRQn             = 119,    /*!< MDIOS Wakeup  Interrupt                                           */

+  MDIOS_IRQn                  = 120,    /*!< MDIOS global Interrupt                                            */

+  JPEG_IRQn                   = 121,    /*!< JPEG global Interrupt                                             */

+  MDMA_IRQn                   = 122,    /*!< MDMA global Interrupt                                             */

+  DSI_IRQn                    = 123,    /*!< DSI global Interrupt                                              */

+  SDMMC2_IRQn                 = 124,    /*!< SDMMC2 global Interrupt                                           */

+  HSEM1_IRQn                  = 125,    /*!< HSEM1 global Interrupt                                            */

+  HSEM2_IRQn                  = 126,    /*!< HSEM2 global Interrupt                                            */

+  ADC3_IRQn                   = 127,    /*!< ADC3 global Interrupt                                             */

+  DMAMUX2_OVR_IRQn            = 128,    /*!<DMAMUX2 Overrun interrupt                                          */

+  BDMA_Channel0_IRQn          = 129,    /*!< BDMA Channel 0 global Interrupt                                   */

+  BDMA_Channel1_IRQn          = 130,    /*!< BDMA Channel 1 global Interrupt                                   */

+  BDMA_Channel2_IRQn          = 131,    /*!< BDMA Channel 2 global Interrupt                                   */

+  BDMA_Channel3_IRQn          = 132,    /*!< BDMA Channel 3 global Interrupt                                   */

+  BDMA_Channel4_IRQn          = 133,    /*!< BDMA Channel 4 global Interrupt                                   */

+  BDMA_Channel5_IRQn          = 134,    /*!< BDMA Channel 5 global Interrupt                                   */

+  BDMA_Channel6_IRQn          = 135,    /*!< BDMA Channel 6 global Interrupt                                   */

+  BDMA_Channel7_IRQn          = 136,    /*!< BDMA Channel 7 global Interrupt                                   */

+  COMP_IRQn                   = 137 ,   /*!< COMP global Interrupt                                             */

+  LPTIM2_IRQn                 = 138,    /*!< LP TIM2 global interrupt                                          */

+  LPTIM3_IRQn                 = 139,    /*!< LP TIM3 global interrupt                                          */

+  LPTIM4_IRQn                 = 140,    /*!< LP TIM4 global interrupt                                          */

+  LPTIM5_IRQn                 = 141,    /*!< LP TIM5 global interrupt                                          */

+  LPUART1_IRQn                = 142,    /*!< LP UART1 interrupt                                                */

+  WWDG_RST_IRQn               = 143,    /*!<Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */

+  CRS_IRQn                    = 144,    /*!< Clock Recovery Global Interrupt                                   */

+  ECC_IRQn                    = 145,    /*!< ECC diagnostic Global Interrupt                                   */

+  SAI4_IRQn                   = 146,    /*!< SAI4 global interrupt                                             */

+  HOLD_CORE_IRQn              = 148,    /*!< Hold core interrupt                                               */

+  WAKEUP_PIN_IRQn             = 149,    /*!< Interrupt for all 6 wake-up pins                                  */

+} IRQn_Type;

+

+/**

+  * @}

+  */

+

+/** @addtogroup Configuration_section_for_CMSIS

+  * @{

+  */

+#define DUAL_CORE  /*!< Dual core line feature */

+

+#define SMPS       /*!< Switched mode power supply feature */

+

+

+

+/**

+  * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals

+   */

+#ifdef CORE_CM4

+#define __CM4_REV                 0x0001  /*!< Cortex-M4 revision r0p1                       */

+#define __MPU_PRESENT             1       /*!< CM4 provides an MPU                           */

+#define __NVIC_PRIO_BITS          4       /*!< CM4 uses 4 Bits for the Priority Levels       */

+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */

+#define __FPU_PRESENT             1       /*!< FPU present                                   */

+

+#include "core_cm4.h"                     /*!< Cortex-M4 processor and core peripherals      */

+#else  /* CORE_CM7 */

+#ifdef CORE_CM7

+#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */

+#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */

+#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */

+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */

+#define __FPU_PRESENT             1       /*!< FPU present                                   */

+#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */

+#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */

+#include "core_cm7.h"                 /*!< Cortex-M7 processor and core peripherals          */

+#else  /* UNKNOWN_CORE */

+#error Please #define CORE_CM4 or CORE_CM7

+#endif /* CORE_CM7 */

+#endif /* CORE_CM4 */

+

+/**

+  * @}

+  */

+

+

+

+

+

+#include "system_stm32h7xx.h"

+#include <stdint.h>

+

+/** @addtogroup Peripheral_registers_structures

+  * @{

+  */

+

+/**

+  * @brief Analog to Digital Converter

+  */

+

+typedef struct

+{

+  __IO uint32_t ISR;              /*!< ADC Interrupt and Status Register,                          Address offset: 0x00 */

+  __IO uint32_t IER;              /*!< ADC Interrupt Enable Register,                              Address offset: 0x04 */

+  __IO uint32_t CR;               /*!< ADC control register,                                       Address offset: 0x08 */

+  __IO uint32_t CFGR;             /*!< ADC Configuration register,                                 Address offset: 0x0C */

+  __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                               Address offset: 0x10 */

+  __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                                 Address offset: 0x14 */

+  __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                                 Address offset: 0x18 */

+  __IO uint32_t PCSEL;            /*!< ADC pre-channel selection,                                  Address offset: 0x1C */

+  __IO uint32_t LTR1;             /*!< ADC watchdog Lower threshold register 1,                    Address offset: 0x20 */

+  __IO uint32_t HTR1;             /*!< ADC watchdog higher threshold register 1,                   Address offset: 0x24 */

+  uint32_t      RESERVED1;        /*!< Reserved, 0x028                                                                  */

+  uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                                  */

+  __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                            Address offset: 0x30 */

+  __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                            Address offset: 0x34 */

+  __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                            Address offset: 0x38 */

+  __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                            Address offset: 0x3C */

+  __IO uint32_t DR;               /*!< ADC regular data register,                                  Address offset: 0x40 */

+  uint32_t      RESERVED3;        /*!< Reserved, 0x044                                                                  */

+  uint32_t      RESERVED4;        /*!< Reserved, 0x048                                                                  */

+  __IO uint32_t JSQR;             /*!< ADC injected sequence register,                             Address offset: 0x4C */

+  uint32_t      RESERVED5[4];     /*!< Reserved, 0x050 - 0x05C                                                          */

+  __IO uint32_t OFR1;             /*!< ADC offset register 1,                                      Address offset: 0x60 */

+  __IO uint32_t OFR2;             /*!< ADC offset register 2,                                      Address offset: 0x64 */

+  __IO uint32_t OFR3;             /*!< ADC offset register 3,                                      Address offset: 0x68 */

+  __IO uint32_t OFR4;             /*!< ADC offset register 4,                                      Address offset: 0x6C */

+  uint32_t      RESERVED6[4];     /*!< Reserved, 0x070 - 0x07C                                                          */

+  __IO uint32_t JDR1;             /*!< ADC injected data register 1,                               Address offset: 0x80 */

+  __IO uint32_t JDR2;             /*!< ADC injected data register 2,                               Address offset: 0x84 */

+  __IO uint32_t JDR3;             /*!< ADC injected data register 3,                               Address offset: 0x88 */

+  __IO uint32_t JDR4;             /*!< ADC injected data register 4,                               Address offset: 0x8C */

+  uint32_t      RESERVED7[4];     /*!< Reserved, 0x090 - 0x09C                                                          */

+  __IO uint32_t AWD2CR;           /*!< ADC  Analog Watchdog 2 Configuration Register,              Address offset: 0xA0 */

+  __IO uint32_t AWD3CR;           /*!< ADC  Analog Watchdog 3 Configuration Register,              Address offset: 0xA4 */

+  uint32_t      RESERVED8;        /*!< Reserved, 0x0A8                                                                  */

+  uint32_t      RESERVED9;        /*!< Reserved, 0x0AC                                                                  */

+  __IO uint32_t LTR2;             /*!< ADC watchdog Lower threshold register 2,                    Address offset: 0xB0 */

+  __IO uint32_t HTR2;             /*!< ADC watchdog Higher threshold register 2,                   Address offset: 0xB4 */

+  __IO uint32_t LTR3;             /*!< ADC watchdog Lower threshold register 3,                    Address offset: 0xB8 */

+  __IO uint32_t HTR3;             /*!< ADC watchdog Higher threshold register 3,                   Address offset: 0xBC */

+  __IO uint32_t DIFSEL;           /*!< ADC  Differential Mode Selection Register,                  Address offset: 0xC0 */

+  __IO uint32_t CALFACT;          /*!< ADC  Calibration Factors,                                   Address offset: 0xC4 */

+  __IO uint32_t CALFACT2;         /*!< ADC  Linearity Calibration Factors,                         Address offset: 0xC8 */

+} ADC_TypeDef;

+

+

+typedef struct

+{

+__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */

+uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */

+__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */

+__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */

+__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */

+

+} ADC_Common_TypeDef;

+

+/**

+  * @brief ART

+  */

+

+typedef struct

+{

+  __IO uint32_t  CTR;        /*!< ART accelerator - control register */

+}ART_TypeDef;

+

+/**

+  * @brief VREFBUF

+  */

+

+typedef struct

+{

+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */

+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */

+} VREFBUF_TypeDef;

+

+

+/**

+  * @brief FD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */

+  __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */

+  __IO uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */

+  __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */

+  __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */

+  __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */

+  __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */

+  __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */

+  __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */

+  __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */

+  __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */

+  __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */

+  __IO uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */

+  __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */

+  __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */

+  __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */

+  __IO uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */

+  __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */

+  __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */

+  __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */

+  __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */

+  __IO uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */

+  __IO uint32_t GFC;          /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */

+  __IO uint32_t SIDFC;        /*!< FDCAN Standard ID Filter Configuration register,                 Address offset: 0x084 */

+  __IO uint32_t XIDFC;        /*!< FDCAN Extended ID Filter Configuration register,                 Address offset: 0x088 */

+  __IO uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */

+  __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x090 */

+  __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x094 */

+  __IO uint32_t NDAT1;        /*!< FDCAN New Data 1 register,                                       Address offset: 0x098 */

+  __IO uint32_t NDAT2;        /*!< FDCAN New Data 2 register,                                       Address offset: 0x09C */

+  __IO uint32_t RXF0C;        /*!< FDCAN Rx FIFO 0 Configuration register,                          Address offset: 0x0A0 */

+  __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x0A4 */

+  __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x0A8 */

+  __IO uint32_t RXBC;         /*!< FDCAN Rx Buffer Configuration register,                          Address offset: 0x0AC */

+  __IO uint32_t RXF1C;        /*!< FDCAN Rx FIFO 1 Configuration register,                          Address offset: 0x0B0 */

+  __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x0B4 */

+  __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x0B8 */

+  __IO uint32_t RXESC;        /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register,        Address offset: 0x0BC */

+  __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */

+  __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */

+  __IO uint32_t TXESC;        /*!< FDCAN Tx Buffer Element Size Configuration register,             Address offset: 0x0C8 */

+  __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0CC */

+  __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0D0 */

+  __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D4 */

+  __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D8 */

+  __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0DC */

+  __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0E0 */

+  __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */

+  __IO uint32_t RESERVED6[2]; /*!< Reserved,                                                                0x0E8 - 0x0EC */

+  __IO uint32_t TXEFC;        /*!< FDCAN Tx Event FIFO Configuration register,                      Address offset: 0x0F0 */

+  __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0F4 */

+  __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0F8 */

+  __IO uint32_t RESERVED7;    /*!< Reserved,                                                                        0x0FC */

+} FDCAN_GlobalTypeDef;

+

+/**

+  * @brief TTFD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t TTTMC;          /*!< TT Trigger Memory Configuration register,    Address offset: 0x100 */

+  __IO uint32_t TTRMC;          /*!< TT Reference Message Configuration register, Address offset: 0x104 */

+  __IO uint32_t TTOCF;          /*!< TT Operation Configuration register,         Address offset: 0x108 */

+  __IO uint32_t TTMLM;          /*!< TT Matrix Limits register,                   Address offset: 0x10C */

+  __IO uint32_t TURCF;          /*!< TUR Configuration register,                  Address offset: 0x110 */

+  __IO uint32_t TTOCN;          /*!< TT Operation Control register,               Address offset: 0x114 */

+  __IO uint32_t TTGTP;          /*!< TT Global Time Preset register,              Address offset: 0x118 */

+  __IO uint32_t TTTMK;          /*!< TT Time Mark register,                       Address offset: 0x11C */

+  __IO uint32_t TTIR;           /*!< TT Interrupt register,                       Address offset: 0x120 */

+  __IO uint32_t TTIE;           /*!< TT Interrupt Enable register,                Address offset: 0x124 */

+  __IO uint32_t TTILS;          /*!< TT Interrupt Line Select register,           Address offset: 0x128 */

+  __IO uint32_t TTOST;          /*!< TT Operation Status register,                Address offset: 0x12C */

+  __IO uint32_t TURNA;          /*!< TT TUR Numerator Actual register,            Address offset: 0x130 */

+  __IO uint32_t TTLGT;          /*!< TT Local and Global Time register,           Address offset: 0x134 */

+  __IO uint32_t TTCTC;          /*!< TT Cycle Time and Count register,            Address offset: 0x138 */

+  __IO uint32_t TTCPT;          /*!< TT Capture Time register,                    Address offset: 0x13C */

+  __IO uint32_t TTCSM;          /*!< TT Cycle Sync Mark register,                 Address offset: 0x140 */

+  __IO uint32_t RESERVED1[111]; /*!< Reserved,                                            0x144 - 0x2FC */

+  __IO uint32_t TTTS;           /*!< TT Trigger Select register,                  Address offset: 0x300 */

+} TTCAN_TypeDef;

+

+/**

+  * @brief FD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t CREL;  /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */

+  __IO uint32_t CCFG;  /*!< Calibration Configuration register,           Address offset: 0x04 */

+  __IO uint32_t CSTAT; /*!< Calibration Status register,                  Address offset: 0x08 */

+  __IO uint32_t CWD;   /*!< Calibration Watchdog register,                Address offset: 0x0C */

+  __IO uint32_t IR;    /*!< CCU Interrupt register,                       Address offset: 0x10 */

+  __IO uint32_t IE;    /*!< CCU Interrupt Enable register,                Address offset: 0x14 */

+} FDCAN_ClockCalibrationUnit_TypeDef;

+

+

+/**

+  * @brief Consumer Electronics Control

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;           /*!< CEC control register,              Address offset:0x00 */

+  __IO uint32_t CFGR;         /*!< CEC configuration register,        Address offset:0x04 */

+  __IO uint32_t TXDR;         /*!< CEC Tx data register ,             Address offset:0x08 */

+  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,              Address offset:0x0C */

+  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register, Address offset:0x10 */

+  __IO uint32_t IER;          /*!< CEC interrupt enable register,     Address offset:0x14 */

+}CEC_TypeDef;

+

+/**

+  * @brief CRC calculation unit

+  */

+

+typedef struct

+{

+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */

+  __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */

+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */

+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */

+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */

+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */

+} CRC_TypeDef;

+

+

+/**

+  * @brief Clock Recovery System

+  */

+typedef struct

+{

+__IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */

+__IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */

+__IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */

+__IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */

+} CRS_TypeDef;

+

+

+/**

+  * @brief Digital to Analog Converter

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */

+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */

+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */

+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */

+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */

+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */

+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */

+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */

+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */

+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */

+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */

+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */

+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */

+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */

+  __IO uint32_t CCR;      /*!< DAC calibration control register,                        Address offset: 0x38 */

+  __IO uint32_t MCR;      /*!< DAC mode control register,                               Address offset: 0x3C */

+  __IO uint32_t SHSR1;    /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */

+  __IO uint32_t SHSR2;    /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */

+  __IO uint32_t SHHR;     /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */

+  __IO uint32_t SHRR;     /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */

+} DAC_TypeDef;

+

+/**

+  * @brief DFSDM module registers

+  */

+typedef struct

+{

+  __IO uint32_t FLTCR1;          /*!< DFSDM control register1,                          Address offset: 0x100 */

+  __IO uint32_t FLTCR2;          /*!< DFSDM control register2,                          Address offset: 0x104 */

+  __IO uint32_t FLTISR;          /*!< DFSDM interrupt and status register,              Address offset: 0x108 */

+  __IO uint32_t FLTICR;          /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */

+  __IO uint32_t FLTJCHGR;        /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */

+  __IO uint32_t FLTFCR;          /*!< DFSDM filter control register,                    Address offset: 0x114 */

+  __IO uint32_t FLTJDATAR;       /*!< DFSDM data register for injected group,           Address offset: 0x118 */

+  __IO uint32_t FLTRDATAR;       /*!< DFSDM data register for regular group,            Address offset: 0x11C */

+  __IO uint32_t FLTAWHTR;        /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */

+  __IO uint32_t FLTAWLTR;        /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */

+  __IO uint32_t FLTAWSR;         /*!< DFSDM analog watchdog status register             Address offset: 0x128 */

+  __IO uint32_t FLTAWCFR;        /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */

+  __IO uint32_t FLTEXMAX;        /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */

+  __IO uint32_t FLTEXMIN;        /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */

+  __IO uint32_t FLTCNVTIMR;      /*!< DFSDM conversion timer,                           Address offset: 0x138 */

+} DFSDM_Filter_TypeDef;

+

+/**

+  * @brief DFSDM channel configuration registers

+  */

+typedef struct

+{

+  __IO uint32_t CHCFGR1;      /*!< DFSDM channel configuration register1,            Address offset: 0x00 */

+  __IO uint32_t CHCFGR2;      /*!< DFSDM channel configuration register2,            Address offset: 0x04 */

+  __IO uint32_t CHAWSCDR;     /*!< DFSDM channel analog watchdog and

+                                   short circuit detector register,                  Address offset: 0x08 */

+  __IO uint32_t CHWDATAR;     /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */

+  __IO uint32_t CHDATINR;     /*!< DFSDM channel data input register,                Address offset: 0x10 */

+} DFSDM_Channel_TypeDef;

+

+/**

+  * @brief Debug MCU

+  */

+typedef struct

+{

+  __IO uint32_t IDCODE;        /*!< MCU device ID code,                     Address offset: 0x00 */

+  __IO uint32_t CR;            /*!< Debug MCU configuration register,       Address offset: 0x04 */

+  __IO uint32_t  RESERVED4[11]; /*!< Reserved,                               Address offset: 0x08 */

+  __IO uint32_t APB3FZ1;     /*!< Debug MCU APB3FZ1 freeze register,    Address offset: 0x34 */

+  __IO uint32_t APB3FZ2;     /*!< Debug MCU APB3FZ2 freeze register,    Address offset: 0x38 */

+  __IO uint32_t APB1LFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x3C */

+  __IO uint32_t APB1LFZ2;    /*!< Debug MCU APB1LFZ2 freeze register,   Address offset: 0x40 */

+  __IO uint32_t APB1HFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x44 */

+  __IO uint32_t APB1HFZ2;    /*!< Debug MCU APB1LFZ2 freeze register,   Address offset: 0x48 */

+  __IO uint32_t APB2FZ1;     /*!< Debug MCU APB2FZ1 freeze register,    Address offset: 0x4C */

+  __IO uint32_t APB2FZ2;     /*!< Debug MCU APB2FZ2 freeze register,    Address offset: 0x50 */

+  __IO uint32_t APB4FZ1;     /*!< Debug MCU APB4FZ1 freeze register,    Address offset: 0x54 */

+  __IO uint32_t APB4FZ2;     /*!< Debug MCU APB4FZ2 freeze register,    Address offset: 0x58 */

+

+}DBGMCU_TypeDef;

+/**

+  * @brief DCMI

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */

+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */

+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */

+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */

+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */

+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */

+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */

+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */

+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */

+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */

+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */

+} DCMI_TypeDef;

+

+/**

+  * @brief DMA Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */

+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */

+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */

+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */

+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */

+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */

+} DMA_Stream_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */

+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */

+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */

+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */

+} DMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CCR;          /*!< DMA channel x configuration register          */

+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register         */

+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register     */

+  __IO uint32_t CM0AR;        /*!< DMA channel x memory 0 address register       */

+  __IO uint32_t CM1AR;        /*!< DMA channel x memory 1 address register       */

+} BDMA_Channel_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */

+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */

+} BDMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CCR;        /*!< DMA Multiplexer Channel x Control Register   */

+}DMAMUX_Channel_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CSR;      /*!< DMA Channel Status Register     */

+  __IO uint32_t  CFR;      /*!< DMA Channel Clear Flag Register */

+}DMAMUX_ChannelStatus_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  RGCR;        /*!< DMA Request Generator x Control Register   */

+}DMAMUX_RequestGen_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  RGSR;        /*!< DMA Request Generator Status Register       */

+  __IO uint32_t  RGCFR;       /*!< DMA Request Generator Clear Flag Register   */

+}DMAMUX_RequestGenStatus_TypeDef;

+

+/**

+  * @brief MDMA Controller

+  */

+typedef struct

+{

+  __IO uint32_t  GISR0;   /*!< MDMA Global Interrupt/Status Register 0,          Address offset: 0x00 */

+}MDMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CISR;      /*!< MDMA channel x interrupt/status register,             Address offset: 0x40 */

+  __IO uint32_t  CIFCR;     /*!< MDMA channel x interrupt flag clear register,         Address offset: 0x44 */

+  __IO uint32_t  CESR;      /*!< MDMA Channel x error status register,                 Address offset: 0x48 */

+  __IO uint32_t  CCR;       /*!< MDMA channel x control register,                      Address offset: 0x4C */

+  __IO uint32_t  CTCR;      /*!< MDMA channel x Transfer Configuration register,       Address offset: 0x50 */

+  __IO uint32_t  CBNDTR;    /*!< MDMA Channel x block number of data register,         Address offset: 0x54 */

+  __IO uint32_t  CSAR;      /*!< MDMA channel x source address register,               Address offset: 0x58 */

+  __IO uint32_t  CDAR;      /*!< MDMA channel x destination address register,          Address offset: 0x5C */

+  __IO uint32_t  CBRUR;     /*!< MDMA channel x Block Repeat address Update register,  Address offset: 0x60 */

+  __IO uint32_t  CLAR;      /*!< MDMA channel x Link Address register,                 Address offset: 0x64 */

+  __IO uint32_t  CTBR;      /*!< MDMA channel x Trigger and Bus selection Register,    Address offset: 0x68 */

+  uint32_t       RESERVED0; /*!< Reserved, 0x68                                                             */

+  __IO uint32_t  CMAR;      /*!< MDMA channel x Mask address register,                 Address offset: 0x70 */

+  __IO uint32_t  CMDR;      /*!< MDMA channel x Mask Data register,                    Address offset: 0x74 */

+}MDMA_Channel_TypeDef;

+

+/**

+  * @brief DMA2D Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */

+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */

+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */

+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */

+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */

+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */

+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */

+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */

+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */

+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */

+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */

+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */

+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */

+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */

+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */

+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */

+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */

+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */

+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */

+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */

+  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */

+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */

+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */

+} DMA2D_TypeDef;

+

+/**

+  * @brief DSI Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t VR;            /*!< DSI Host Version Register,                                 Address offset: 0x00      */

+  __IO uint32_t CR;            /*!< DSI Host Control Register,                                 Address offset: 0x04      */

+  __IO uint32_t CCR;           /*!< DSI HOST Clock Control Register,                           Address offset: 0x08      */

+  __IO uint32_t LVCIDR;        /*!< DSI Host LTDC VCID Register,                               Address offset: 0x0C      */

+  __IO uint32_t LCOLCR;        /*!< DSI Host LTDC Color Coding Register,                       Address offset: 0x10      */

+  __IO uint32_t LPCR;          /*!< DSI Host LTDC Polarity Configuration Register,             Address offset: 0x14      */

+  __IO uint32_t LPMCR;         /*!< DSI Host Low-Power Mode Configuration Register,            Address offset: 0x18      */

+  uint32_t      RESERVED0[4];  /*!< Reserved, 0x1C - 0x2B                                                                */

+  __IO uint32_t PCR;           /*!< DSI Host Protocol Configuration Register,                  Address offset: 0x2C      */

+  __IO uint32_t GVCIDR;        /*!< DSI Host Generic VCID Register,                            Address offset: 0x30      */

+  __IO uint32_t MCR;           /*!< DSI Host Mode Configuration Register,                      Address offset: 0x34      */

+  __IO uint32_t VMCR;          /*!< DSI Host Video Mode Configuration Register,                Address offset: 0x38      */

+  __IO uint32_t VPCR;          /*!< DSI Host Video Packet Configuration Register,              Address offset: 0x3C      */

+  __IO uint32_t VCCR;          /*!< DSI Host Video Chunks Configuration Register,              Address offset: 0x40      */

+  __IO uint32_t VNPCR;         /*!< DSI Host Video Null Packet Configuration Register,         Address offset: 0x44      */

+  __IO uint32_t VHSACR;        /*!< DSI Host Video HSA Configuration Register,                 Address offset: 0x48      */

+  __IO uint32_t VHBPCR;        /*!< DSI Host Video HBP Configuration Register,                 Address offset: 0x4C      */

+  __IO uint32_t VLCR;          /*!< DSI Host Video Line Configuration Register,                Address offset: 0x50      */

+  __IO uint32_t VVSACR;        /*!< DSI Host Video VSA Configuration Register,                 Address offset: 0x54      */

+  __IO uint32_t VVBPCR;        /*!< DSI Host Video VBP Configuration Register,                 Address offset: 0x58      */

+  __IO uint32_t VVFPCR;        /*!< DSI Host Video VFP Configuration Register,                 Address offset: 0x5C      */

+  __IO uint32_t VVACR;         /*!< DSI Host Video VA Configuration Register,                  Address offset: 0x60      */

+  __IO uint32_t LCCR;          /*!< DSI Host LTDC Command Configuration Register,              Address offset: 0x64      */

+  __IO uint32_t CMCR;          /*!< DSI Host Command Mode Configuration Register,              Address offset: 0x68      */

+  __IO uint32_t GHCR;          /*!< DSI Host Generic Header Configuration Register,            Address offset: 0x6C      */

+  __IO uint32_t GPDR;          /*!< DSI Host Generic Payload Data Register,                    Address offset: 0x70      */

+  __IO uint32_t GPSR;          /*!< DSI Host Generic Packet Status Register,                   Address offset: 0x74      */

+  __IO uint32_t TCCR[6];       /*!< DSI Host Timeout Counter Configuration Register,           Address offset: 0x78-0x8F */

+  __IO uint32_t TDCR;          /*!< DSI Host 3D Configuration Register,                        Address offset: 0x90      */

+  __IO uint32_t CLCR;          /*!< DSI Host Clock Lane Configuration Register,                Address offset: 0x94      */

+  __IO uint32_t CLTCR;         /*!< DSI Host Clock Lane Timer Configuration Register,          Address offset: 0x98      */

+  __IO uint32_t DLTCR;         /*!< DSI Host Data Lane Timer Configuration Register,           Address offset: 0x9C      */

+  __IO uint32_t PCTLR;         /*!< DSI Host PHY Control Register,                             Address offset: 0xA0      */

+  __IO uint32_t PCONFR;        /*!< DSI Host PHY Configuration Register,                       Address offset: 0xA4      */

+  __IO uint32_t PUCR;          /*!< DSI Host PHY ULPS Control Register,                        Address offset: 0xA8      */

+  __IO uint32_t PTTCR;         /*!< DSI Host PHY TX Triggers Configuration Register,           Address offset: 0xAC      */

+  __IO uint32_t PSR;           /*!< DSI Host PHY Status Register,                              Address offset: 0xB0      */

+  uint32_t      RESERVED1[2];  /*!< Reserved, 0xB4 - 0xBB                                                                */

+  __IO uint32_t ISR[2];        /*!< DSI Host Interrupt & Status Register,                      Address offset: 0xBC-0xC3 */

+  __IO uint32_t IER[2];        /*!< DSI Host Interrupt Enable Register,                        Address offset: 0xC4-0xCB */

+  uint32_t      RESERVED2[3];  /*!< Reserved, 0xD0 - 0xD7                                                                */

+  __IO uint32_t FIR[2];        /*!< DSI Host Force Interrupt Register,                         Address offset: 0xD8-0xDF */

+  uint32_t      RESERVED3[8];  /*!< Reserved, 0xE0 - 0xFF                                                                */

+  __IO uint32_t VSCR;          /*!< DSI Host Video Shadow Control Register,                    Address offset: 0x100     */

+  uint32_t      RESERVED4[2];  /*!< Reserved, 0x104 - 0x10B                                                              */

+  __IO uint32_t LCVCIDR;       /*!< DSI Host LTDC Current VCID Register,                       Address offset: 0x10C     */

+  __IO uint32_t LCCCR;         /*!< DSI Host LTDC Current Color Coding Register,               Address offset: 0x110     */

+  uint32_t      RESERVED5;     /*!< Reserved, 0x114                                                                      */

+  __IO uint32_t LPMCCR;        /*!< DSI Host Low-power Mode Current Configuration Register,    Address offset: 0x118     */

+  uint32_t      RESERVED6[7];  /*!< Reserved, 0x11C - 0x137                                                              */

+  __IO uint32_t VMCCR;         /*!< DSI Host Video Mode Current Configuration Register,        Address offset: 0x138     */

+  __IO uint32_t VPCCR;         /*!< DSI Host Video Packet Current Configuration Register,      Address offset: 0x13C     */

+  __IO uint32_t VCCCR;         /*!< DSI Host Video Chuncks Current Configuration Register,     Address offset: 0x140     */

+  __IO uint32_t VNPCCR;        /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144     */

+  __IO uint32_t VHSACCR;       /*!< DSI Host Video HSA Current Configuration Register,         Address offset: 0x148     */

+  __IO uint32_t VHBPCCR;       /*!< DSI Host Video HBP Current Configuration Register,         Address offset: 0x14C     */

+  __IO uint32_t VLCCR;         /*!< DSI Host Video Line Current Configuration Register,        Address offset: 0x150     */

+  __IO uint32_t VVSACCR;       /*!< DSI Host Video VSA Current Configuration Register,         Address offset: 0x154     */

+  __IO uint32_t VVBPCCR;       /*!< DSI Host Video VBP Current Configuration Register,         Address offset: 0x158     */

+  __IO uint32_t VVFPCCR;       /*!< DSI Host Video VFP Current Configuration Register,         Address offset: 0x15C     */

+  __IO uint32_t VVACCR;        /*!< DSI Host Video VA Current Configuration Register,          Address offset: 0x160     */

+  uint32_t      RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F                                                              */

+  __IO uint32_t TDCCR;         /*!< DSI Host 3D Current Configuration Register,                Address offset: 0x190     */

+  uint32_t      RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF                                                                */

+  __IO uint32_t WCFGR;          /*!< DSI Wrapper Configuration Register,                        Address offset: 0x400       */

+  __IO uint32_t WCR;            /*!< DSI Wrapper Control Register,                              Address offset: 0x404       */

+  __IO uint32_t WIER;           /*!< DSI Wrapper Interrupt Enable Register,                     Address offset: 0x408       */

+  __IO uint32_t WISR;           /*!< DSI Wrapper Interrupt and Status Register,                 Address offset: 0x40C       */

+  __IO uint32_t WIFCR;          /*!< DSI Wrapper Interrupt Flag Clear Register,                 Address offset: 0x410       */

+  uint32_t      RESERVED9;      /*!< Reserved, 0x414                                                                        */

+  __IO uint32_t WPCR[5];        /*!< DSI Wrapper PHY Configuration Register,                    Address offset: 0x418-0x42B */

+  uint32_t      RESERVED10;     /*!< Reserved, 0x42C                                                                        */

+  __IO uint32_t WRPCR;          /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430                  */

+} DSI_TypeDef;

+

+/**

+  * @brief Ethernet MAC

+  */

+typedef struct

+{

+  __IO uint32_t MACCR;

+  __IO uint32_t MACECR;

+  __IO uint32_t MACPFR;

+  __IO uint32_t MACWTR;

+  __IO uint32_t MACHT0R;

+  __IO uint32_t MACHT1R;

+  uint32_t      RESERVED1[14];

+  __IO uint32_t MACVTR;

+  uint32_t      RESERVED2;

+  __IO uint32_t MACVHTR;

+  uint32_t      RESERVED3;

+  __IO uint32_t MACVIR;

+  __IO uint32_t MACIVIR;

+  uint32_t      RESERVED4[2];

+  __IO uint32_t MACTFCR;

+  uint32_t      RESERVED5[7];

+  __IO uint32_t MACRFCR;

+  uint32_t      RESERVED6[7];

+  __IO uint32_t MACISR;

+  __IO uint32_t MACIER;

+  __IO uint32_t MACRXTXSR;

+  uint32_t      RESERVED7;

+  __IO uint32_t MACPCSR;

+  __IO uint32_t MACRWKPFR;

+  uint32_t      RESERVED8[2];

+  __IO uint32_t MACLCSR;

+  __IO uint32_t MACLTCR;

+  __IO uint32_t MACLETR;

+  __IO uint32_t MAC1USTCR;

+  uint32_t      RESERVED9[12];

+  __IO uint32_t MACVR;

+  __IO uint32_t MACDR;

+  uint32_t      RESERVED10;

+  __IO uint32_t MACHWF0R;

+  __IO uint32_t MACHWF1R;

+  __IO uint32_t MACHWF2R;

+  uint32_t      RESERVED11[54];

+  __IO uint32_t MACMDIOAR;

+  __IO uint32_t MACMDIODR;

+  uint32_t      RESERVED12[2];

+  __IO uint32_t MACARPAR;

+  uint32_t      RESERVED13[59];

+  __IO uint32_t MACA0HR;

+  __IO uint32_t MACA0LR;

+  __IO uint32_t MACA1HR;

+  __IO uint32_t MACA1LR;

+  __IO uint32_t MACA2HR;

+  __IO uint32_t MACA2LR;

+  __IO uint32_t MACA3HR;

+  __IO uint32_t MACA3LR;

+  uint32_t      RESERVED14[248];

+  __IO uint32_t MMCCR;

+  __IO uint32_t MMCRIR;

+  __IO uint32_t MMCTIR;

+  __IO uint32_t MMCRIMR;

+  __IO uint32_t MMCTIMR;

+  uint32_t      RESERVED15[14];

+  __IO uint32_t MMCTSCGPR;

+  __IO uint32_t MMCTMCGPR;

+  uint32_t      RESERVED16[5];

+  __IO uint32_t MMCTPCGR;

+  uint32_t      RESERVED17[10];

+  __IO uint32_t MMCRCRCEPR;

+  __IO uint32_t MMCRAEPR;

+  uint32_t      RESERVED18[10];

+  __IO uint32_t MMCRUPGR;

+  uint32_t      RESERVED19[9];

+  __IO uint32_t MMCTLPIMSTR;

+  __IO uint32_t MMCTLPITCR;

+  __IO uint32_t MMCRLPIMSTR;

+  __IO uint32_t MMCRLPITCR;

+  uint32_t      RESERVED20[65];

+  __IO uint32_t MACL3L4C0R;

+  __IO uint32_t MACL4A0R;

+  uint32_t      RESERVED21[2];

+  __IO uint32_t MACL3A0R0R;

+  __IO uint32_t MACL3A1R0R;

+  __IO uint32_t MACL3A2R0R;

+  __IO uint32_t MACL3A3R0R;

+  uint32_t      RESERVED22[4];

+  __IO uint32_t MACL3L4C1R;

+  __IO uint32_t MACL4A1R;

+  uint32_t      RESERVED23[2];

+  __IO uint32_t MACL3A0R1R;

+  __IO uint32_t MACL3A1R1R;

+  __IO uint32_t MACL3A2R1R;

+  __IO uint32_t MACL3A3R1R;

+  uint32_t      RESERVED24[108];

+  __IO uint32_t MACTSCR;

+  __IO uint32_t MACSSIR;

+  __IO uint32_t MACSTSR;

+  __IO uint32_t MACSTNR;

+  __IO uint32_t MACSTSUR;

+  __IO uint32_t MACSTNUR;

+  __IO uint32_t MACTSAR;

+  uint32_t      RESERVED25;

+  __IO uint32_t MACTSSR;

+  uint32_t      RESERVED26[3];

+  __IO uint32_t MACTTSSNR;

+  __IO uint32_t MACTTSSSR;

+  uint32_t      RESERVED27[2];

+  __IO uint32_t MACACR;

+  uint32_t      RESERVED28;

+  __IO uint32_t MACATSNR;

+  __IO uint32_t MACATSSR;

+  __IO uint32_t MACTSIACR;

+  __IO uint32_t MACTSEACR;

+  __IO uint32_t MACTSICNR;

+  __IO uint32_t MACTSECNR;

+  uint32_t      RESERVED29[4];

+  __IO uint32_t MACPPSCR;

+  uint32_t      RESERVED30[3];

+  __IO uint32_t MACPPSTTSR;

+  __IO uint32_t MACPPSTTNR;

+  __IO uint32_t MACPPSIR;

+  __IO uint32_t MACPPSWR;

+  uint32_t      RESERVED31[12];

+  __IO uint32_t MACPOCR;

+  __IO uint32_t MACSPI0R;

+  __IO uint32_t MACSPI1R;

+  __IO uint32_t MACSPI2R;

+  __IO uint32_t MACLMIR;

+  uint32_t      RESERVED32[11];

+  __IO uint32_t MTLOMR;

+  uint32_t      RESERVED33[7];

+  __IO uint32_t MTLISR;

+  uint32_t      RESERVED34[55];

+  __IO uint32_t MTLTQOMR;

+  __IO uint32_t MTLTQUR;

+  __IO uint32_t MTLTQDR;

+  uint32_t      RESERVED35[8];

+  __IO uint32_t MTLQICSR;

+  __IO uint32_t MTLRQOMR;

+  __IO uint32_t MTLRQMPOCR;

+  __IO uint32_t MTLRQDR;

+  uint32_t      RESERVED36[177];

+  __IO uint32_t DMAMR;

+  __IO uint32_t DMASBMR;

+  __IO uint32_t DMAISR;

+  __IO uint32_t DMADSR;

+  uint32_t      RESERVED37[60];

+  __IO uint32_t DMACCR;

+  __IO uint32_t DMACTCR;

+  __IO uint32_t DMACRCR;

+  uint32_t      RESERVED38[2];

+  __IO uint32_t DMACTDLAR;

+  uint32_t      RESERVED39;

+  __IO uint32_t DMACRDLAR;

+  __IO uint32_t DMACTDTPR;

+  uint32_t      RESERVED40;

+  __IO uint32_t DMACRDTPR;

+  __IO uint32_t DMACTDRLR;

+  __IO uint32_t DMACRDRLR;

+  __IO uint32_t DMACIER;

+  __IO uint32_t DMACRIWTR;

+__IO uint32_t DMACSFCSR;

+  uint32_t      RESERVED41;

+  __IO uint32_t DMACCATDR;

+  uint32_t      RESERVED42;

+  __IO uint32_t DMACCARDR;

+  uint32_t      RESERVED43;

+  __IO uint32_t DMACCATBR;

+  uint32_t      RESERVED44;

+  __IO uint32_t DMACCARBR;

+  __IO uint32_t DMACSR;

+uint32_t      RESERVED45[2];

+__IO uint32_t DMACMFCR;

+}ETH_TypeDef;

+/**

+  * @brief External Interrupt/Event Controller

+  */

+

+typedef struct

+{

+__IO uint32_t RTSR1;               /*!< EXTI Rising trigger selection register,          Address offset: 0x00 */

+__IO uint32_t FTSR1;               /*!< EXTI Falling trigger selection register,         Address offset: 0x04 */

+__IO uint32_t SWIER1;              /*!< EXTI Software interrupt event register,          Address offset: 0x08 */

+__IO uint32_t D3PMR1;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */

+__IO uint32_t D3PCR1L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L)     Address offset: 0x10 */

+__IO uint32_t D3PCR1H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H)   Address offset: 0x14 */

+uint32_t      RESERVED1[2];        /*!< Reserved,                                        0x18 to 0x1C         */

+__IO uint32_t RTSR2;               /*!< EXTI Rising trigger selection register,          Address offset: 0x20 */

+__IO uint32_t FTSR2;               /*!< EXTI Falling trigger selection register,         Address offset: 0x24 */

+__IO uint32_t SWIER2;              /*!< EXTI Software interrupt event register,          Address offset: 0x28 */

+__IO uint32_t D3PMR2;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */

+__IO uint32_t D3PCR2L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L)  Address offset: 0x30 */

+__IO uint32_t D3PCR2H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */

+uint32_t      RESERVED2[2];        /*!< Reserved,                                        0x38 to 0x3C         */

+__IO uint32_t RTSR3;               /*!< EXTI Rising trigger selection register,          Address offset: 0x40 */

+__IO uint32_t FTSR3;               /*!< EXTI Falling trigger selection register,         Address offset: 0x44 */

+__IO uint32_t SWIER3;              /*!< EXTI Software interrupt event register,          Address offset: 0x48 */

+__IO uint32_t D3PMR3;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */

+__IO uint32_t D3PCR3L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */

+__IO uint32_t D3PCR3H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */

+uint32_t      RESERVED3[10];       /*!< Reserved,                                        0x58 to 0x7C         */

+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                    Address offset: 0x80 */

+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                        Address offset: 0x84 */

+__IO uint32_t PR1;                 /*!< EXTI Pending register,                           Address offset: 0x88 */

+uint32_t      RESERVED4;           /*!< Reserved,                                        0x8C                 */

+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                    Address offset: 0x90 */

+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                        Address offset: 0x94 */

+__IO uint32_t PR2;                 /*!< EXTI Pending register,                           Address offset: 0x98 */

+uint32_t      RESERVED5;           /*!< Reserved,                                        0x9C                 */

+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                    Address offset: 0xA0 */

+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                        Address offset: 0xA4 */

+__IO uint32_t PR3;                 /*!< EXTI Pending register,                           Address offset: 0xA8 */

+uint32_t      RESERVED6[5];        /*!< Reserved,                                        0xAC to 0xBC         */

+__IO uint32_t C2IMR1;              /*!< EXTI Interrupt mask register,                    Address offset: 0xC0 */

+__IO uint32_t C2EMR1;              /*!< EXTI Event mask register,                        Address offset: 0xC4 */

+__IO uint32_t C2PR1;               /*!< EXTI Pending register,                           Address offset: 0xC8 */

+uint32_t      RESERVED7;           /*!< Reserved,                                        0xCC                 */

+__IO uint32_t C2IMR2;              /*!< EXTI Interrupt mask register,                    Address offset: 0xD0 */

+__IO uint32_t C2EMR2;              /*!< EXTI Event mask register,                        Address offset: 0xD4 */

+__IO uint32_t C2PR2;               /*!< EXTI Pending register,                           Address offset: 0xD8 */

+uint32_t      RESERVED8;           /*!< Reserved,                                        0xDC                 */

+__IO uint32_t C2IMR3;              /*!< EXTI Interrupt mask register,                    Address offset: 0xE0 */

+__IO uint32_t C2EMR3;              /*!< EXTI Event mask register,                        Address offset: 0xE4 */

+__IO uint32_t C2PR3;               /*!< EXTI Pending register,                           Address offset: 0xE8 */

+

+}EXTI_TypeDef;

+

+typedef struct

+{

+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                Address offset: 0x00 */

+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                    Address offset: 0x04 */

+__IO uint32_t PR1;                 /*!< EXTI Pending register,                       Address offset: 0x08 */

+uint32_t      RESERVED1;           /*!< Reserved, 0x0C                                                    */

+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                Address offset: 0x10 */

+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                    Address offset: 0x14 */

+__IO uint32_t PR2;                 /*!< EXTI Pending register,                       Address offset: 0x18 */

+uint32_t      RESERVED2;           /*!< Reserved, 0x1C                                                    */

+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                Address offset: 0x20 */

+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                    Address offset: 0x24 */

+__IO uint32_t PR3;                 /*!< EXTI Pending register,                       Address offset: 0x28 */

+}EXTI_Core_TypeDef;

+

+

+/**

+  * @brief FLASH Registers

+  */

+

+typedef struct

+{

+  __IO uint32_t ACR;             /*!< FLASH access control register,                            Address offset: 0x00  */

+  __IO uint32_t KEYR1;           /*!< Flash Key Register for bank1,                             Address offset: 0x04  */

+  __IO uint32_t OPTKEYR;         /*!< Flash Option Key Register,                                Address offset: 0x08  */

+  __IO uint32_t CR1;             /*!< Flash Control Register for bank1,                         Address offset: 0x0C  */

+  __IO uint32_t SR1;             /*!< Flash Status Register for bank1,                          Address offset: 0x10  */

+  __IO uint32_t CCR1;            /*!< Flash Control Register for bank1,                         Address offset: 0x14  */

+  __IO uint32_t OPTCR;           /*!< Flash Option Control Register,                            Address offset: 0x18  */

+  __IO uint32_t OPTSR_CUR;       /*!< Flash Option Status Current Register,                     Address offset: 0x1C  */

+  __IO uint32_t OPTSR_PRG;       /*!< Flash Option Status to Program Register,                  Address offset: 0x20  */

+  __IO uint32_t OPTCCR;          /*!< Flash Option Clear Control Register,                      Address offset: 0x24  */

+  __IO uint32_t PRAR_CUR1;       /*!< Flash Current Protection Address Register for bank1,      Address offset: 0x28  */

+  __IO uint32_t PRAR_PRG1;       /*!< Flash Protection Address to Program Register for bank1,   Address offset: 0x2C  */

+  __IO uint32_t SCAR_CUR1;       /*!< Flash Current Secure Address Register for bank1,          Address offset: 0x30  */

+  __IO uint32_t SCAR_PRG1;       /*!< Flash Secure Address to Program Register for bank1,       Address offset: 0x34  */

+  __IO uint32_t WPSN_CUR1;       /*!< Flash Current Write Protection Register on bank1,         Address offset: 0x38  */

+  __IO uint32_t WPSN_PRG1;       /*!< Flash Write Protection to Program Register on bank1,      Address offset: 0x3C  */

+  __IO uint32_t BOOT7_CUR;       /*!< Flash Current Boot Address for Pelican Core Register,     Address offset: 0x40  */

+  __IO uint32_t BOOT7_PRG;       /*!< Flash Boot Address to Program for Pelican Core Register,  Address offset: 0x44  */

+  __IO uint32_t BOOT4_CUR;       /*!< Flash Current Boot Address for M4 Core Register,          Address offset: 0x48  */

+  __IO uint32_t BOOT4_PRG;       /*!< Flash Boot Address to Program for M4 Core Register,       Address offset: 0x4C  */

+  __IO uint32_t CRCCR1;          /*!< Flash CRC Control register For Bank1 Register ,           Address offset: 0x50  */

+  __IO uint32_t CRCSADD1;        /*!< Flash CRC Start Address Register for Bank1 ,              Address offset: 0x54  */

+  __IO uint32_t CRCEADD1;        /*!< Flash CRC End Address Register for Bank1 ,                Address offset: 0x58  */

+  __IO uint32_t CRCDATA;         /*!< Flash CRC Data Register for Bank1 ,                       Address offset: 0x5C  */

+  __IO uint32_t ECC_FA1;         /*!< Flash ECC Fail Address For Bank1 Register ,               Address offset: 0x60  */

+  uint32_t      RESERVED1[40];   /*!< Reserved, 0x64 to 0x100                                                         */

+  __IO uint32_t KEYR2;           /*!< Flash Key Register for bank2,                             Address offset: 0x104 */

+  uint32_t      RESERVED2;       /*!< Reserved, 0x108                                                                 */

+  __IO uint32_t CR2;             /*!< Flash Control Register for bank2,                         Address offset: 0x10C */

+  __IO uint32_t SR2;             /*!< Flash Status Register for bank2,                          Address offset: 0x110 */

+  __IO uint32_t CCR2;            /*!< Flash Status Register for bank2,                          Address offset: 0x114 */

+  uint32_t      RESERVED3[4];    /*!< Reserved, 0x118 to 0x124                                                        */

+  __IO uint32_t PRAR_CUR2;       /*!< Flash Current Protection Address Register for bank2,      Address offset: 0x128 */

+  __IO uint32_t PRAR_PRG2;       /*!< Flash Protection Address to Program Register for bank2,   Address offset: 0x12C */

+  __IO uint32_t SCAR_CUR2;       /*!< Flash Current Secure Address Register for bank2,          Address offset: 0x130 */

+  __IO uint32_t SCAR_PRG2;       /*!< Flash Secure Address Register for bank2,                  Address offset: 0x134 */

+  __IO uint32_t WPSN_CUR2;       /*!< Flash Current Write Protection Register on bank2,         Address offset: 0x138 */

+  __IO uint32_t WPSN_PRG2;       /*!< Flash Write Protection to Program Register on bank2,      Address offset: 0x13C */

+  uint32_t      RESERVED4[4];    /*!< Reserved, 0x140 to 0x14C                                                        */

+  __IO uint32_t CRCCR2;          /*!< Flash CRC Control register For Bank2 Register ,           Address offset: 0x150 */

+  __IO uint32_t CRCSADD2;        /*!< Flash CRC Start Address Register for Bank2 ,              Address offset: 0x154 */

+  __IO uint32_t CRCEADD2;        /*!< Flash CRC End Address Register for Bank2 ,                Address offset: 0x158 */

+  __IO uint32_t CRCDATA2;        /*!< Flash CRC Data Register for Bank2 ,                       Address offset: 0x15C */

+  __IO uint32_t ECC_FA2;         /*!< Flash ECC Fail Address For Bank2 Register ,               Address offset: 0x160 */

+} FLASH_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */

+} FMC_Bank1_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank1E

+  */

+

+typedef struct

+{

+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */

+} FMC_Bank1E_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank2

+  */

+

+typedef struct

+{

+  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */

+  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */

+  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */

+  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */

+  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */

+  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */

+} FMC_Bank2_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank3

+  */

+

+typedef struct

+{

+  __IO uint32_t PCR;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */

+  __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */

+  __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */

+  __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */

+  uint32_t      RESERVED;  /*!< Reserved, 0x90                                                            */

+  __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */

+} FMC_Bank3_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank5 and 6

+  */

+

+

+typedef struct

+{

+  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */

+  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */

+  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */

+  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */

+  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */

+} FMC_Bank5_6_TypeDef;

+

+/**

+  * @brief General Purpose I/O

+  */

+

+typedef struct

+{

+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */

+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */

+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */

+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */

+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */

+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */

+  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset,               Address offset: 0x18      */

+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */

+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */

+} GPIO_TypeDef;

+

+/**

+  * @brief Operational Amplifier (OPAMP)

+  */

+

+typedef struct

+{

+  __IO uint32_t CSR;          /*!< OPAMP control/status register,                      Address offset: 0x00 */

+  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,     Address offset: 0x04 */

+  __IO uint32_t HSOTR;        /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */

+} OPAMP_TypeDef;

+

+/**

+  * @brief System configuration controller

+  */

+

+typedef struct

+{

+ uint32_t RESERVED1;           /*!< Reserved,                                           Address offset: 0x00        */

+ __IO uint32_t PMCR;           /*!< SYSCFG peripheral mode configuration register,      Address offset: 0x04        */

+ __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration registers,  Address offset: 0x08-0x14   */

+ __IO uint32_t CFGR;           /*!< SYSCFG configuration registers,                     Address offset: 0x18        */

+ uint32_t RESERVED2;           /*!< Reserved,                                           Address offset: 0x1C        */

+ __IO uint32_t CCCSR;          /*!< SYSCFG compensation cell control/status register,   Address offset: 0x20        */

+ __IO uint32_t CCVR;           /*!< SYSCFG compensation cell value register,            Address offset: 0x24        */

+ __IO uint32_t CCCR;           /*!< SYSCFG compensation cell code register,             Address offset: 0x28        */

+ __IO uint32_t PWRCR;          /*!< PWR control register,                               Address offset: 0x2C        */

+  uint32_t     RESERVED3[61];  /*!< Reserved, 0x30-0x120                                                            */

+  __IO uint32_t PKGR;          /*!< SYSCFG package register,                            Address offset: 0x124       */

+  uint32_t     RESERVED4[118]; /*!< Reserved, 0x128-0x2FC                                                           */

+ __IO uint32_t UR0;            /*!< SYSCFG user register 0,                             Address offset: 0x300       */

+ __IO uint32_t UR1;            /*!< SYSCFG user register 1,                             Address offset: 0x304       */

+ __IO uint32_t UR2;            /*!< SYSCFG user register 2,                             Address offset: 0x308       */

+ __IO uint32_t UR3;            /*!< SYSCFG user register 3,                             Address offset: 0x30C       */

+ __IO uint32_t UR4;            /*!< SYSCFG user register 4,                             Address offset: 0x310       */

+ __IO uint32_t UR5;            /*!< SYSCFG user register 5,                             Address offset: 0x314       */

+ __IO uint32_t UR6;            /*!< SYSCFG user register 6,                             Address offset: 0x318       */

+ __IO uint32_t UR7;            /*!< SYSCFG user register 7,                             Address offset: 0x31C       */

+ __IO uint32_t UR8;            /*!< SYSCFG user register 8,                             Address offset: 0x320       */

+ __IO uint32_t UR9;            /*!< SYSCFG user register 9,                             Address offset: 0x324       */

+ __IO uint32_t UR10;           /*!< SYSCFG user register 10,                            Address offset: 0x328       */

+ __IO uint32_t UR11;           /*!< SYSCFG user register 11,                            Address offset: 0x32C       */

+ __IO uint32_t UR12;           /*!< SYSCFG user register 12,                            Address offset: 0x330       */

+ __IO uint32_t UR13;           /*!< SYSCFG user register 13,                            Address offset: 0x334       */

+ __IO uint32_t UR14;           /*!< SYSCFG user register 14,                            Address offset: 0x338       */

+ __IO uint32_t UR15;           /*!< SYSCFG user register 15,                            Address offset: 0x33C       */

+ __IO uint32_t UR16;           /*!< SYSCFG user register 16,                            Address offset: 0x340       */

+ __IO uint32_t UR17;           /*!< SYSCFG user register 17,                            Address offset: 0x344       */

+

+} SYSCFG_TypeDef;

+

+/**

+  * @brief Inter-integrated Circuit Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */

+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */

+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */

+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */

+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */

+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */

+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */

+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */

+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */

+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */

+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */

+} I2C_TypeDef;

+

+/**

+  * @brief Independent WATCHDOG

+  */

+

+typedef struct

+{

+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */

+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */

+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */

+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */

+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */

+} IWDG_TypeDef;

+

+

+/**

+  * @brief JPEG Codec

+  */

+typedef struct

+{

+  __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */

+  __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */

+  __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */

+  __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */

+  __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */

+  __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */

+  __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */

+  __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */

+  uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */

+  __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */

+  __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */

+  __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */

+  uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */

+  __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */

+  __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */

+  uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */

+  __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */

+  __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */

+  __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */

+  __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */

+  __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */

+  __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */

+  __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */

+  __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */

+  uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */

+  __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0,                 Address offset: 500h-65Ch */

+  __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1,                 Address offset: 660h-7BCh */

+  __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encodor, DC Huffman table 0,                 Address offset: 7C0h-7DCh */

+  __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encodor, DC Huffman table 1,                 Address offset: 7E0h-7FCh */

+

+} JPEG_TypeDef;

+

+/**

+  * @brief LCD-TFT Display Controller

+  */

+

+typedef struct

+{

+  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04                                                       */

+  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */

+  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */

+  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */

+  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */

+  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */

+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20                                                       */

+  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */

+  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28                                                            */

+  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */

+  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30                                                            */

+  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */

+  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */

+  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */

+  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */

+  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */

+  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */

+} LTDC_TypeDef;

+

+/**

+  * @brief LCD-TFT Display layer x Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */

+  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */

+  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */

+  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */

+  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */

+  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */

+  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */

+  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */

+  uint32_t      RESERVED0[2];  /*!< Reserved */

+  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */

+  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */

+  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */

+  uint32_t      RESERVED1[3];  /*!< Reserved */

+  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */

+

+} LTDC_Layer_TypeDef;

+

+/**

+  * @brief Power Control

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;       /*!< PWR power control register 1,            Address offset: 0x00 */

+  __IO uint32_t CSR1;      /*!< PWR power control status register 1,     Address offset: 0x04 */

+  __IO uint32_t CR2;       /*!< PWR power control register 2,            Address offset: 0x08 */

+  __IO uint32_t CR3;       /*!< PWR power control register 3,            Address offset: 0x0C */

+  __IO uint32_t CPUCR;     /*!< PWR CPU control register,                Address offset: 0x10 */

+  __IO uint32_t CPU2CR;    /*!< PWR CPU2 control register,               Address offset: 0x14 */

+  __IO uint32_t D3CR;      /*!< PWR D3 domain control register,          Address offset: 0x18 */

+       uint32_t RESERVED1; /*!< Reserved,                                Address offset: 0x1C */

+  __IO uint32_t WKUPCR;    /*!< PWR wakeup clear register,               Address offset: 0x20 */

+  __IO uint32_t WKUPFR;    /*!< PWR wakeup flag register,                Address offset: 0x24 */

+  __IO uint32_t WKUPEPR;   /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */

+} PWR_TypeDef;

+

+/**

+  * @brief Reset and Clock Control

+  */

+

+typedef struct

+{

+ __IO uint32_t CR;             /*!< RCC clock control register,                                              Address offset: 0x00  */

+ __IO uint32_t HSICFGR;        /*!< HSI Clock Calibration Register,                                          Address offset: 0x04  */

+ __IO uint32_t CRRCR;          /*!< Clock Recovery RC  Register,                                             Address offset: 0x08  */

+ __IO uint32_t CSICFGR;        /*!< CSI Clock Calibration Register,                                          Address offset: 0x0C  */

+ __IO uint32_t CFGR;           /*!< RCC clock configuration register,                                        Address offset: 0x10  */

+ uint32_t     RESERVED1;       /*!< Reserved,                                                                Address offset: 0x14  */

+ __IO uint32_t D1CFGR;         /*!< RCC Domain 1 configuration register,                                     Address offset: 0x18  */

+ __IO uint32_t D2CFGR;         /*!< RCC Domain 2 configuration register,                                     Address offset: 0x1C  */

+ __IO uint32_t D3CFGR;         /*!< RCC Domain 3 configuration register,                                     Address offset: 0x20  */

+ uint32_t     RESERVED2;       /*!< Reserved,                                                                Address offset: 0x24  */

+ __IO uint32_t PLLCKSELR;      /*!< RCC PLLs Clock Source Selection Register,                                Address offset: 0x28  */

+ __IO uint32_t PLLCFGR;        /*!< RCC PLLs  Configuration Register,                                        Address offset: 0x2C  */

+ __IO uint32_t PLL1DIVR;       /*!< RCC PLL1 Dividers Configuration Register,                                Address offset: 0x30  */

+ __IO uint32_t PLL1FRACR;      /*!< RCC PLL1 Fractional Divider Configuration Register,                      Address offset: 0x34  */

+ __IO uint32_t PLL2DIVR;       /*!< RCC PLL2 Dividers Configuration Register,                                Address offset: 0x38  */

+ __IO uint32_t PLL2FRACR;      /*!< RCC PLL2 Fractional Divider Configuration Register,                      Address offset: 0x3C  */

+ __IO uint32_t PLL3DIVR;       /*!< RCC PLL3 Dividers Configuration Register,                                Address offset: 0x40  */

+ __IO uint32_t PLL3FRACR;      /*!< RCC PLL3 Fractional Divider Configuration Register,                      Address offset: 0x44  */

+ uint32_t      RESERVED3;      /*!< Reserved,                                                                Address offset: 0x48  */

+ __IO uint32_t  D1CCIPR;       /*!< RCC Domain 1 Kernel Clock Configuration Register                         Address offset: 0x4C  */

+ __IO uint32_t  D2CCIP1R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x50  */

+ __IO uint32_t  D2CCIP2R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x54  */

+ __IO uint32_t  D3CCIPR;       /*!< RCC Domain 3 Kernel Clock Configuration Register                         Address offset: 0x58  */

+ uint32_t      RESERVED4;      /*!< Reserved,                                                                Address offset: 0x5C  */

+ __IO uint32_t  CIER;          /*!< RCC Clock Source Interrupt Enable Register                               Address offset: 0x60  */

+ __IO uint32_t  CIFR;          /*!< RCC Clock Source Interrupt Flag Register                                 Address offset: 0x64  */

+ __IO uint32_t  CICR;          /*!< RCC Clock Source Interrupt Clear Register                                Address offset: 0x68  */

+ uint32_t     RESERVED5;       /*!< Reserved,                                                                Address offset: 0x6C  */

+ __IO uint32_t  BDCR;          /*!< RCC Vswitch Backup Domain Control Register,                              Address offset: 0x70  */

+ __IO uint32_t  CSR;           /*!< RCC clock control & status register,                                     Address offset: 0x74  */

+ uint32_t     RESERVED6;       /*!< Reserved,                                                                Address offset: 0x78  */

+ __IO uint32_t AHB3RSTR;       /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x7C  */

+ __IO uint32_t AHB1RSTR;       /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x80  */

+ __IO uint32_t AHB2RSTR;       /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x84  */

+ __IO uint32_t AHB4RSTR;       /*!< RCC AHB4 peripheral reset register,                                      Address offset: 0x88  */

+ __IO uint32_t APB3RSTR;       /*!< RCC APB3 peripheral reset register,                                      Address offset: 0x8C  */

+ __IO uint32_t APB1LRSTR;      /*!< RCC APB1 peripheral reset Low Word register,                             Address offset: 0x90  */

+ __IO uint32_t APB1HRSTR;      /*!< RCC APB1 peripheral reset High Word register,                            Address offset: 0x94  */

+ __IO uint32_t APB2RSTR;       /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x98  */

+ __IO uint32_t APB4RSTR;       /*!< RCC APB4 peripheral reset register,                                      Address offset: 0x9C  */

+ __IO uint32_t GCR;            /*!< RCC RCC Global Control  Register,                                        Address offset: 0xA0  */

+ uint32_t     RESERVED8;       /*!< Reserved,                                                                Address offset: 0xA4  */

+ __IO uint32_t D3AMR;          /*!< RCC Domain 3 Autonomous Mode Register,                                   Address offset: 0xA8  */

+ uint32_t     RESERVED11[9];    /*!< Reserved, 0xAC-0xCC                                                      Address offset: 0xAC  */

+ __IO uint32_t RSR;            /*!< RCC Reset status register,                                               Address offset: 0xD0  */

+ __IO uint32_t AHB3ENR;        /*!< RCC AHB3 peripheral clock  register,                                     Address offset: 0xD4  */

+ __IO uint32_t AHB1ENR;        /*!< RCC AHB1 peripheral clock  register,                                     Address offset: 0xD8  */

+ __IO uint32_t AHB2ENR;        /*!< RCC AHB2 peripheral clock  register,                                     Address offset: 0xDC  */

+ __IO uint32_t AHB4ENR;        /*!< RCC AHB4 peripheral clock  register,                                     Address offset: 0xE0  */

+ __IO uint32_t APB3ENR;        /*!< RCC APB3 peripheral clock  register,                                     Address offset: 0xE4  */

+ __IO uint32_t APB1LENR;       /*!< RCC APB1 peripheral clock  Low Word register,                            Address offset: 0xE8  */

+ __IO uint32_t APB1HENR;       /*!< RCC APB1 peripheral clock  High Word register,                           Address offset: 0xEC  */

+ __IO uint32_t APB2ENR;        /*!< RCC APB2 peripheral clock  register,                                     Address offset: 0xF0  */

+ __IO uint32_t APB4ENR;        /*!< RCC APB4 peripheral clock  register,                                     Address offset: 0xF4  */

+ uint32_t      RESERVED12;      /*!< Reserved,                                                                Address offset: 0xF8  */

+ __IO uint32_t AHB3LPENR;      /*!< RCC AHB3 peripheral sleep clock  register,                               Address offset: 0xFC  */

+ __IO uint32_t AHB1LPENR;      /*!< RCC AHB1 peripheral sleep clock  register,                               Address offset: 0x100 */

+ __IO uint32_t AHB2LPENR;      /*!< RCC AHB2 peripheral sleep clock  register,                               Address offset: 0x104 */

+ __IO uint32_t AHB4LPENR;      /*!< RCC AHB4 peripheral sleep clock  register,                               Address offset: 0x108 */

+ __IO uint32_t APB3LPENR;      /*!< RCC APB3 peripheral sleep clock  register,                               Address offset: 0x10C */

+ __IO uint32_t APB1LLPENR;     /*!< RCC APB1 peripheral sleep clock  Low Word register,                      Address offset: 0x110 */

+ __IO uint32_t APB1HLPENR;     /*!< RCC APB1 peripheral sleep clock  High Word register,                     Address offset: 0x114 */

+ __IO uint32_t APB2LPENR;      /*!< RCC APB2 peripheral sleep clock  register,                               Address offset: 0x118 */

+ __IO uint32_t APB4LPENR;      /*!< RCC APB4 peripheral sleep clock  register,                               Address offset: 0x11C */

+ uint32_t     RESERVED13[4];   /*!< Reserved, 0x120-0x12C                                                    Address offset: 0x120 */

+

+} RCC_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t RSR;          /*!< RCC Reset status register,                                               Address offset: 0x00 */

+  __IO uint32_t AHB3ENR;      /*!< RCC AHB3 peripheral clock  register,                            Address offset: 0x04 */

+  __IO uint32_t AHB1ENR;      /*!< RCC AHB1 peripheral clock  register,                            Address offset: 0x08 */

+  __IO uint32_t AHB2ENR;      /*!< RCC AHB2 peripheral clock  register,                            Address offset: 0x0C */

+  __IO uint32_t AHB4ENR;      /*!< RCC AHB4 peripheral clock  register,                            Address offset: 0x10 */

+  __IO uint32_t APB3ENR;      /*!< RCC APB3 peripheral clock  register,                            Address offset: 0x14 */

+  __IO uint32_t APB1LENR;     /*!< RCC APB1 peripheral clock  Low Word register,                   Address offset: 0x18 */

+  __IO uint32_t APB1HENR;     /*!< RCC APB1 peripheral clock  High Word register,                  Address offset: 0x1C */

+  __IO uint32_t APB2ENR;      /*!< RCC APB2 peripheral clock  register,                            Address offset: 0x20 */

+  __IO uint32_t APB4ENR;      /*!< RCC APB4 peripheral clock  register,                            Address offset: 0x24 */

+  uint32_t      RESERVED9;    /*!< Reserved,                                                       Address offset: 0x28 */

+  __IO uint32_t AHB3LPENR;    /*!< RCC AHB3 peripheral sleep clock  register,                      Address offset: 0x3C */

+  __IO uint32_t AHB1LPENR;    /*!< RCC AHB1 peripheral sleep clock  register,                      Address offset: 0x40 */

+  __IO uint32_t AHB2LPENR;    /*!< RCC AHB2 peripheral sleep clock  register,                      Address offset: 0x44 */

+  __IO uint32_t AHB4LPENR;    /*!< RCC AHB4 peripheral sleep clock  register,                      Address offset: 0x48 */

+  __IO uint32_t APB3LPENR;    /*!< RCC APB3 peripheral sleep clock  register,                      Address offset: 0x4C */

+  __IO uint32_t APB1LLPENR;   /*!< RCC APB1 peripheral sleep clock  Low Word register,             Address offset: 0x50 */

+  __IO uint32_t APB1HLPENR;   /*!< RCC APB1 peripheral sleep clock  High Word register,            Address offset: 0x54 */

+  __IO uint32_t APB2LPENR;    /*!< RCC APB2 peripheral sleep clock  register,                      Address offset: 0x58 */

+  __IO uint32_t APB4LPENR;    /*!< RCC APB4 peripheral sleep clock  register,                      Address offset: 0x5C */

+  uint32_t     RESERVED10[4]; /*!< Reserved, 0x60-0x6C                                             Address offset: 0x60 */

+

+} RCC_Core_TypeDef;

+

+/**

+  * @brief Real-Time Clock

+  */

+typedef struct

+{

+  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */

+  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */

+  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */

+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */

+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */

+  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */

+       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */

+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */

+  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */

+  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */

+  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */

+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */

+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */

+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */

+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */

+  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */

+  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */

+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */

+  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */

+  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset: 0x4C */

+  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */

+  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */

+  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */

+  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */

+  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */

+  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */

+  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */

+  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */

+  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */

+  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */

+  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */

+  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */

+  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */

+  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */

+  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */

+  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */

+  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */

+  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */

+  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */

+  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */

+  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */

+  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */

+  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */

+  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */

+  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */

+  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */

+  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */

+  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */

+  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */

+  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */

+  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */

+  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */

+} RTC_TypeDef;

+

+/**

+  * @brief Serial Audio Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t GCR;           /*!< SAI global configuration register, Address offset: 0x00 */

+  uint32_t      RESERVED0[16]; /*!< Reserved, 0x04 - 0x43                                   */

+  __IO uint32_t PDMCR;         /*!< SAI PDM control register,          Address offset: 0x44 */

+  __IO uint32_t PDMDLY;        /*!< SAI PDM delay register,            Address offset: 0x48 */

+} SAI_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */

+  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */

+  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */

+  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */

+  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */

+  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */

+  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */

+  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */

+} SAI_Block_TypeDef;

+

+/**

+  * @brief SPDIF-RX Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */

+  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */

+  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */

+  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */

+  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */

+  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */

+  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */

+  uint32_t        RESERVED2;    /*!< Reserved,  0x1A                                          */

+} SPDIFRX_TypeDef;

+

+

+/**

+  * @brief Secure digital input/output Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t POWER;          /*!< SDMMC power control register,             Address offset: 0x00  */

+  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,             Address offset: 0x04  */

+  __IO uint32_t ARG;            /*!< SDMMC argument register,                  Address offset: 0x08  */

+  __IO uint32_t CMD;            /*!< SDMMC command register,                   Address offset: 0x0C  */

+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register,          Address offset: 0x10  */

+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                Address offset: 0x14  */

+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                Address offset: 0x18  */

+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                Address offset: 0x1C  */

+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                Address offset: 0x20  */

+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                Address offset: 0x24  */

+  __IO uint32_t DLEN;           /*!< SDMMC data length register,               Address offset: 0x28  */

+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,              Address offset: 0x2C  */

+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,              Address offset: 0x30  */

+  __I uint32_t  STA;            /*!< SDMMC status register,                    Address offset: 0x34  */

+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,           Address offset: 0x38  */

+  __IO uint32_t MASK;           /*!< SDMMC mask register,                      Address offset: 0x3C  */

+  __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,     Address offset: 0x40  */

+  uint32_t      RESERVED0[3];   /*!< Reserved, 0x44 - 0x4C - 0x4C                                    */

+  __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,               Address offset: 0x50  */

+  __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,           Address offset: 0x54  */

+  __IO uint32_t IDMABASE0;      /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58  */

+  __IO uint32_t IDMABASE1;      /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C  */

+  uint32_t      RESERVED1[8];   /*!< Reserved, 0x60-0x7C                                             */

+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,                 Address offset: 0x80  */

+  uint32_t      RESERVED2[222]; /*!< Reserved, 0x84-0x3F8                                            */

+  __IO uint32_t IPVR;           /*!< SDMMC data FIFO register,                 Address offset: 0x3FC */

+} SDMMC_TypeDef;

+

+

+/**

+  * @brief Delay Block DLYB

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;          /*!< DELAY BLOCK control register,  Address offset: 0x00 */

+  __IO uint32_t CFGR;        /*!< DELAY BLOCK configuration register,  Address offset: 0x04 */

+} DLYB_TypeDef;

+

+/**

+  * @brief HW Semaphore HSEM

+  */

+

+typedef struct

+{

+  __IO uint32_t R[32];      /*!< 2-step write lock and read back registers,     Address offset: 00h-7Ch  */

+  __IO uint32_t RLR[32];    /*!< 1-step read lock registers,                    Address offset: 80h-FCh  */

+  __IO uint32_t C1IER;      /*!< HSEM Interrupt 0 enable register ,             Address offset: 100h     */

+  __IO uint32_t C1ICR;      /*!< HSEM Interrupt 0 clear register ,              Address offset: 104h     */

+  __IO uint32_t C1ISR;      /*!< HSEM Interrupt 0 Status register ,             Address offset: 108h     */

+  __IO uint32_t C1MISR;     /*!< HSEM Interrupt 0 Masked Status register ,      Address offset: 10Ch     */

+  __IO uint32_t C2IER;      /*!< HSEM Interrupt 1 enable register ,             Address offset: 110h     */

+  __IO uint32_t C2ICR;      /*!< HSEM Interrupt 1 clear register ,              Address offset: 114h     */

+  __IO uint32_t C2ISR;      /*!< HSEM Interrupt 1 Status register ,             Address offset: 118h     */

+  __IO uint32_t C2MISR;     /*!< HSEM Interrupt 1 Masked Status register ,      Address offset: 11Ch     */

+   uint32_t  Reserved[8];   /* Reserved                                         Address offset: 120h-13Ch*/

+  __IO uint32_t CR;         /*!< HSEM Semaphore clear register ,                Address offset: 140h      */

+  __IO uint32_t KEYR;       /*!< HSEM Semaphore clear key register ,            Address offset: 144h      */

+

+} HSEM_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t IER;        /*!< HSEM interrupt enable register ,                Address offset:   0h     */

+  __IO uint32_t ICR;        /*!< HSEM interrupt clear register ,                 Address offset:   4h     */

+  __IO uint32_t ISR;        /*!< HSEM interrupt status register ,                Address offset:   8h     */

+  __IO uint32_t MISR;       /*!< HSEM masked interrupt status register ,         Address offset:   Ch     */

+} HSEM_Common_TypeDef;

+

+/**

+  * @brief Serial Peripheral Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */

+  __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */

+  __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */

+  __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */

+  __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */

+  __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */

+  __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */

+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */

+  __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */

+  uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */

+  __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */

+  uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */

+  __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */

+  __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */

+  __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */

+  __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */

+  __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */

+

+} SPI_TypeDef;

+/**

+  * @brief QUAD Serial Peripheral Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */

+  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */

+  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */

+  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */

+  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */

+  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */

+  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */

+  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */

+  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */

+  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */

+  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */

+  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */

+  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */

+} QUADSPI_TypeDef;

+

+/**

+  * @brief TIM

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */

+  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */

+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */

+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */

+  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */

+  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */

+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */

+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */

+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */

+  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */

+  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */

+  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */

+  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */

+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */

+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */

+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */

+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */

+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */

+  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */

+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */

+  uint32_t      RESERVED1;   /*!< Reserved, 0x50                                                 */

+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */

+  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */

+  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */

+  __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */

+  __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */

+  __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x68 */

+} TIM_TypeDef;

+

+/**

+  * @brief LPTIMIMER

+  */

+typedef struct

+{

+  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,         Address offset: 0x00 */

+  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,              Address offset: 0x04 */

+  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,             Address offset: 0x08 */

+  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                Address offset: 0x0C */

+  __IO uint32_t CR;       /*!< LPTIM Control register,                      Address offset: 0x10 */

+  __IO uint32_t CMP;      /*!< LPTIM Compare register,                      Address offset: 0x14 */

+  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                   Address offset: 0x18 */

+  __IO uint32_t CNT;      /*!< LPTIM Counter register,                      Address offset: 0x1C */

+  uint32_t  RESERVED1;    /*!< Reserved, 0x20                                                    */

+  __IO uint32_t CFGR2;    /*!< LPTIM Configuration register,                Address offset: 0x24 */

+} LPTIM_TypeDef;

+

+/**

+  * @brief Comparator

+  */

+typedef struct

+{

+  __IO uint32_t SR;        /*!< Comparator status register,                    Address offset: 0x00 */

+  __IO uint32_t ICFR;      /*!< Comparator interrupt clear flag register,       Address offset: 0x04 */

+  __IO uint32_t OR;        /*!< Comparator option register,                  Address offset: 0x08 */

+} COMPOPT_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CFGR;      /*!< Comparator configuration register  ,           Address offset: 0x00 */

+} COMP_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CFGR;       /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */

+} COMP_Common_TypeDef;

+/**

+  * @brief Universal Synchronous Asynchronous Receiver Transmitter

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */

+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */

+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */

+  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */

+  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */

+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */

+  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */

+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */

+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */

+  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */

+  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */

+  __IO uint32_t PRESC;  /*!< USART clock Prescaler register,           Address offset: 0x2C */

+} USART_TypeDef;

+

+/**

+  * @brief Single Wire Protocol Master Interface SPWMI

+  */

+typedef struct

+{

+  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */

+  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */

+    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */

+  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */

+  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */

+  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */

+  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */

+  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */

+  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */

+  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */

+} SWPMI_TypeDef;

+

+/**

+  * @brief Window WATCHDOG

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */

+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */

+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */

+} WWDG_TypeDef;

+

+

+/**

+  * @brief RAM_ECC_Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t CR;           /*!< RAMECC monitor configuration register          */

+  __IO uint32_t SR;           /*!< RAMECC monitor status register                 */

+  __IO uint32_t FAR;          /*!< RAMECC monitor failing address register        */

+  __IO uint32_t FDRL;         /*!< RAMECC monitor failing data low register       */

+  __IO uint32_t FDRH;         /*!< RAMECC monitor failing data high register      */

+  __IO uint32_t FECR;         /*!< RAMECC monitor failing ECC error code register */

+} RAMECC_MonitorTypeDef;

+

+typedef struct

+{

+  __IO uint32_t IER;          /*!< RAMECC interrupt enable register */

+} RAMECC_TypeDef;

+/**

+  * @}

+  */

+

+

+

+/**

+  * @brief High resolution Timer (HRTIM)

+  */

+/* HRTIM master registers definition */

+typedef struct

+{

+  __IO uint32_t MCR;            /*!< HRTIM Master Timer control register,                     Address offset: 0x00 */

+  __IO uint32_t MISR;           /*!< HRTIM Master Timer interrupt status register,            Address offset: 0x04 */

+  __IO uint32_t MICR;           /*!< HRTIM Master Timer interupt clear register,              Address offset: 0x08 */

+  __IO uint32_t MDIER;          /*!< HRTIM Master Timer DMA/interrupt enable register         Address offset: 0x0C */

+  __IO uint32_t MCNTR;          /*!< HRTIM Master Timer counter register,                     Address offset: 0x10 */

+  __IO uint32_t MPER;           /*!< HRTIM Master Timer period register,                      Address offset: 0x14 */

+  __IO uint32_t MREP;           /*!< HRTIM Master Timer repetition register,                  Address offset: 0x18 */

+  __IO uint32_t MCMP1R;         /*!< HRTIM Master Timer compare 1 register,                   Address offset: 0x1C */

+  uint32_t      RESERVED0;     /*!< Reserved,                                                                 0x20 */

+  __IO uint32_t MCMP2R;         /*!< HRTIM Master Timer compare 2 register,                   Address offset: 0x24 */

+  __IO uint32_t MCMP3R;         /*!< HRTIM Master Timer compare 3 register,                   Address offset: 0x28 */

+  __IO uint32_t MCMP4R;         /*!< HRTIM Master Timer compare 4 register,                   Address offset: 0x2C */

+  uint32_t      RESERVED1[20];  /*!< Reserved,                                                          0x30..0x7C */

+}HRTIM_Master_TypeDef;

+

+/* HRTIM Timer A to E registers definition */

+typedef struct

+{

+  __IO uint32_t TIMxCR;     /*!< HRTIM Timerx control register,                              Address offset: 0x00 */

+  __IO uint32_t TIMxISR;    /*!< HRTIM Timerx interrupt status register,                     Address offset: 0x04 */

+  __IO uint32_t TIMxICR;    /*!< HRTIM Timerx interrupt clear register,                      Address offset: 0x08 */

+  __IO uint32_t TIMxDIER;   /*!< HRTIM Timerx DMA/interrupt enable register,                 Address offset: 0x0C */

+  __IO uint32_t CNTxR;      /*!< HRTIM Timerx counter register,                              Address offset: 0x10 */

+  __IO uint32_t PERxR;      /*!< HRTIM Timerx period register,                               Address offset: 0x14 */

+  __IO uint32_t REPxR;      /*!< HRTIM Timerx repetition register,                           Address offset: 0x18 */

+  __IO uint32_t CMP1xR;     /*!< HRTIM Timerx compare 1 register,                            Address offset: 0x1C */

+  __IO uint32_t CMP1CxR;    /*!< HRTIM Timerx compare 1 compound register,                   Address offset: 0x20 */

+  __IO uint32_t CMP2xR;     /*!< HRTIM Timerx compare 2 register,                            Address offset: 0x24 */

+  __IO uint32_t CMP3xR;     /*!< HRTIM Timerx compare 3 register,                            Address offset: 0x28 */

+  __IO uint32_t CMP4xR;     /*!< HRTIM Timerx compare 4 register,                            Address offset: 0x2C */

+  __IO uint32_t CPT1xR;     /*!< HRTIM Timerx capture 1 register,                            Address offset: 0x30 */

+  __IO uint32_t CPT2xR;     /*!< HRTIM Timerx capture 2 register,                            Address offset: 0x34 */

+  __IO uint32_t DTxR;       /*!< HRTIM Timerx dead time register,                            Address offset: 0x38 */

+  __IO uint32_t SETx1R;     /*!< HRTIM Timerx output 1 set register,                         Address offset: 0x3C */

+  __IO uint32_t RSTx1R;     /*!< HRTIM Timerx output 1 reset register,                       Address offset: 0x40 */

+  __IO uint32_t SETx2R;     /*!< HRTIM Timerx output 2 set register,                         Address offset: 0x44 */

+  __IO uint32_t RSTx2R;     /*!< HRTIM Timerx output 2 reset register,                       Address offset: 0x48 */

+  __IO uint32_t EEFxR1;     /*!< HRTIM Timerx external event filtering 1 register,           Address offset: 0x4C */

+  __IO uint32_t EEFxR2;     /*!< HRTIM Timerx external event filtering 2 register,           Address offset: 0x50 */

+  __IO uint32_t RSTxR;      /*!< HRTIM Timerx Reset register,                                Address offset: 0x54 */

+  __IO uint32_t CHPxR;      /*!< HRTIM Timerx Chopper register,                              Address offset: 0x58 */

+  __IO uint32_t CPT1xCR;    /*!< HRTIM Timerx Capture 1 register,                            Address offset: 0x5C */

+  __IO uint32_t CPT2xCR;    /*!< HRTIM Timerx Capture 2 register,                            Address offset: 0x60 */

+  __IO uint32_t OUTxR;      /*!< HRTIM Timerx Output register,                               Address offset: 0x64 */

+  __IO uint32_t FLTxR;      /*!< HRTIM Timerx Fault register,                                Address offset: 0x68 */

+  uint32_t      RESERVED0[5];  /*!< Reserved,                                                          0x6C..0x7C */

+}HRTIM_Timerx_TypeDef;

+

+/* HRTIM common register definition */

+typedef struct

+{

+  __IO uint32_t CR1;        /*!< HRTIM control register1,                                    Address offset: 0x00 */

+  __IO uint32_t CR2;        /*!< HRTIM control register2,                                    Address offset: 0x04 */

+  __IO uint32_t ISR;        /*!< HRTIM interrupt status register,                            Address offset: 0x08 */

+  __IO uint32_t ICR;        /*!< HRTIM interrupt clear register,                             Address offset: 0x0C */

+  __IO uint32_t IER;        /*!< HRTIM interrupt enable register,                            Address offset: 0x10 */

+  __IO uint32_t OENR;       /*!< HRTIM Output enable register,                               Address offset: 0x14 */

+  __IO uint32_t ODISR;      /*!< HRTIM Output disable register,                              Address offset: 0x18 */

+  __IO uint32_t ODSR;       /*!< HRTIM Output disable status register,                       Address offset: 0x1C */

+  __IO uint32_t BMCR;       /*!< HRTIM Burst mode control register,                          Address offset: 0x20 */

+  __IO uint32_t BMTRGR;     /*!< HRTIM Busrt mode trigger register,                          Address offset: 0x24 */

+  __IO uint32_t BMCMPR;     /*!< HRTIM Burst mode compare register,                          Address offset: 0x28 */

+  __IO uint32_t BMPER;      /*!< HRTIM Burst mode period register,                           Address offset: 0x2C */

+  __IO uint32_t EECR1;      /*!< HRTIM Timer external event control register1,               Address offset: 0x30 */

+  __IO uint32_t EECR2;      /*!< HRTIM Timer external event control register2,               Address offset: 0x34 */

+  __IO uint32_t EECR3;      /*!< HRTIM Timer external event control register3,               Address offset: 0x38 */

+  __IO uint32_t ADC1R;      /*!< HRTIM ADC Trigger 1 register,                               Address offset: 0x3C */

+  __IO uint32_t ADC2R;      /*!< HRTIM ADC Trigger 2 register,                               Address offset: 0x40 */

+  __IO uint32_t ADC3R;      /*!< HRTIM ADC Trigger 3 register,                               Address offset: 0x44 */

+  __IO uint32_t ADC4R;      /*!< HRTIM ADC Trigger 4 register,                               Address offset: 0x48 */

+  __IO uint32_t RESERVED0;  /*!< Reserved,                                                   Address offset: 0x4C */

+  __IO uint32_t FLTINR1;    /*!< HRTIM Fault input register1,                                Address offset: 0x50 */

+  __IO uint32_t FLTINR2;    /*!< HRTIM Fault input register2,                                Address offset: 0x54 */

+  __IO uint32_t BDMUPR;     /*!< HRTIM Burst DMA Master Timer update register,               Address offset: 0x58 */

+  __IO uint32_t BDTAUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x5C */

+  __IO uint32_t BDTBUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x60 */

+  __IO uint32_t BDTCUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x64 */

+  __IO uint32_t BDTDUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x68 */

+  __IO uint32_t BDTEUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x6C */

+  __IO uint32_t BDMADR;     /*!< HRTIM Burst DMA Master Data register,                       Address offset: 0x70 */

+}HRTIM_Common_TypeDef;

+

+/* HRTIM  register definition */

+typedef struct {

+  HRTIM_Master_TypeDef sMasterRegs;

+  HRTIM_Timerx_TypeDef sTimerxRegs[5];

+  uint32_t             RESERVED0[32];

+  HRTIM_Common_TypeDef sCommonRegs;

+}HRTIM_TypeDef;

+/**

+  * @brief RNG

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */

+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */

+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */

+} RNG_TypeDef;

+

+/**

+  * @brief MDIOS

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;

+  __IO uint32_t WRFR;

+  __IO uint32_t CWRFR;

+  __IO uint32_t RDFR;

+  __IO uint32_t CRDFR;

+  __IO uint32_t SR;

+  __IO uint32_t CLRFR;

+  uint32_t RESERVED[57];

+  __IO uint32_t DINR0;

+  __IO uint32_t DINR1;

+  __IO uint32_t DINR2;

+  __IO uint32_t DINR3;

+  __IO uint32_t DINR4;

+  __IO uint32_t DINR5;

+  __IO uint32_t DINR6;

+  __IO uint32_t DINR7;

+  __IO uint32_t DINR8;

+  __IO uint32_t DINR9;

+  __IO uint32_t DINR10;

+  __IO uint32_t DINR11;

+  __IO uint32_t DINR12;

+  __IO uint32_t DINR13;

+  __IO uint32_t DINR14;

+  __IO uint32_t DINR15;

+  __IO uint32_t DINR16;

+  __IO uint32_t DINR17;

+  __IO uint32_t DINR18;

+  __IO uint32_t DINR19;

+  __IO uint32_t DINR20;

+  __IO uint32_t DINR21;

+  __IO uint32_t DINR22;

+  __IO uint32_t DINR23;

+  __IO uint32_t DINR24;

+  __IO uint32_t DINR25;

+  __IO uint32_t DINR26;

+  __IO uint32_t DINR27;

+  __IO uint32_t DINR28;

+  __IO uint32_t DINR29;

+  __IO uint32_t DINR30;

+  __IO uint32_t DINR31;

+  __IO uint32_t DOUTR0;

+  __IO uint32_t DOUTR1;

+  __IO uint32_t DOUTR2;

+  __IO uint32_t DOUTR3;

+  __IO uint32_t DOUTR4;

+  __IO uint32_t DOUTR5;

+  __IO uint32_t DOUTR6;

+  __IO uint32_t DOUTR7;

+  __IO uint32_t DOUTR8;

+  __IO uint32_t DOUTR9;

+  __IO uint32_t DOUTR10;

+  __IO uint32_t DOUTR11;

+  __IO uint32_t DOUTR12;

+  __IO uint32_t DOUTR13;

+  __IO uint32_t DOUTR14;

+  __IO uint32_t DOUTR15;

+  __IO uint32_t DOUTR16;

+  __IO uint32_t DOUTR17;

+  __IO uint32_t DOUTR18;

+  __IO uint32_t DOUTR19;

+  __IO uint32_t DOUTR20;

+  __IO uint32_t DOUTR21;

+  __IO uint32_t DOUTR22;

+  __IO uint32_t DOUTR23;

+  __IO uint32_t DOUTR24;

+  __IO uint32_t DOUTR25;

+  __IO uint32_t DOUTR26;

+  __IO uint32_t DOUTR27;

+  __IO uint32_t DOUTR28;

+  __IO uint32_t DOUTR29;

+  __IO uint32_t DOUTR30;

+  __IO uint32_t DOUTR31;

+} MDIOS_TypeDef;

+

+

+/**

+  * @brief USB_OTG_Core_Registers

+  */

+typedef struct

+{

+ __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */

+  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */

+  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */

+  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */

+  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */

+  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */

+  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */

+  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */

+  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */

+  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */

+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */

+  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */

+  uint32_t Reserved30[2];             /*!< Reserved                                     030h */

+  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */

+  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */

+  __IO uint32_t GSNPSID;              /* USB_OTG core ID                                040h*/

+  __IO uint32_t GHWCFG1;              /* User HW config1                                044h*/

+  __IO uint32_t GHWCFG2;              /* User HW config2                                048h*/

+  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */

+  uint32_t  Reserved6;                /*!< Reserved                                     050h */

+  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */

+  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */

+  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */

+   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */

+    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */

+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */

+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */

+} USB_OTG_GlobalTypeDef;

+

+

+/**

+  * @brief USB_OTG_device_Registers

+  */

+typedef struct

+{

+  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */

+  __IO uint32_t DCTL;            /*!< dev Control Register         804h */

+  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */

+  uint32_t Reserved0C;           /*!< Reserved                     80Ch */

+  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */

+  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */

+  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */

+  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */

+  uint32_t  Reserved20;          /*!< Reserved                     820h */

+  uint32_t Reserved9;            /*!< Reserved                     824h */

+  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */

+  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */

+  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */

+  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */

+  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */

+  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */

+  uint32_t Reserved40;           /*!< dedicated EP mask            840h */

+  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */

+  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */

+  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */

+} USB_OTG_DeviceTypeDef;

+

+

+/**

+  * @brief USB_OTG_IN_Endpoint-Specific_Register

+  */

+typedef struct

+{

+  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */

+  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */

+  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */

+  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */

+  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */

+  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */

+  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */

+  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */

+} USB_OTG_INEndpointTypeDef;

+

+

+/**

+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */

+  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */

+  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */

+  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */

+  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */

+  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */

+  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */

+} USB_OTG_OUTEndpointTypeDef;

+

+

+/**

+  * @brief USB_OTG_Host_Mode_Register_Structures

+  */

+typedef struct

+{

+  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */

+  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */

+  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */

+  uint32_t Reserved40C;           /*!< Reserved                             40Ch */

+  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */

+  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */

+  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */

+} USB_OTG_HostTypeDef;

+

+/**

+  * @brief USB_OTG_Host_Channel_Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */

+  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */

+  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */

+  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */

+  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */

+  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */

+  uint32_t Reserved[2];           /*!< Reserved                                      */

+} USB_OTG_HostChannelTypeDef;

+/**

+  * @}

+  */

+

+

+/** @addtogroup Peripheral_memory_map

+  * @{

+  */

+#define D1_ITCMRAM_BASE           (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM  */

+#define D1_ITCMICP_BASE           (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM         */

+#define D1_DTCMRAM_BASE           (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM                            */

+#define D1_AXIFLASH_BASE          (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI                */

+#define D1_AXIICP_BASE            (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI          */

+#define D1_AXISRAM_BASE           (0x24000000UL) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI                */

+

+#define D2_AXISRAM_BASE           (0x10000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI                */

+#define D2_AHBSRAM_BASE           (0x30000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge    */

+

+#define D3_BKPSRAM_BASE           (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge                                */

+#define D3_SRAM_BASE              (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge                               */

+

+#define PERIPH_BASE               (0x40000000UL) /*!< Base address of : AHB/APB Peripherals                                                   */

+#define QSPI_BASE                 (0x90000000UL) /*!< Base address of : QSPI memories  accessible over AXI                                    */

+

+#define FLASH_BANK1_BASE          (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI                          */

+#define FLASH_BANK2_BASE          (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI                          */

+#define FLASH_END                 (0x081FFFFFUL) /*!< FLASH end address                                                                       */

+

+/* Legacy define */

+#define FLASH_BASE                FLASH_BANK1_BASE

+

+/*!< Device electronic signature memory map */

+#define UID_BASE                  (0x1FF1E800UL)            /*!< Unique device ID register base address */

+#define FLASHSIZE_BASE            (0x1FF1E880UL)            /*!< FLASH Size register base address */

+

+

+/*!< Peripheral memory map */

+#define D2_APB1PERIPH_BASE        PERIPH_BASE

+#define D2_APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)

+#define D2_AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)

+#define D2_AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)

+

+#define D1_APB1PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)

+#define D1_AHB1PERIPH_BASE       (PERIPH_BASE + 0x12000000UL)

+

+#define D3_APB1PERIPH_BASE       (PERIPH_BASE + 0x18000000UL)

+#define D3_AHB1PERIPH_BASE       (PERIPH_BASE + 0x18020000UL)

+

+/*!< Legacy Peripheral memory map */

+#define APB1PERIPH_BASE        PERIPH_BASE

+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)

+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)

+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)

+

+

+/*!< D1_AHB1PERIPH peripherals */

+

+#define MDMA_BASE             (D1_AHB1PERIPH_BASE + 0x0000UL)

+#define DMA2D_BASE            (D1_AHB1PERIPH_BASE + 0x1000UL)

+#define JPGDEC_BASE           (D1_AHB1PERIPH_BASE + 0x3000UL)

+#define FLASH_R_BASE          (D1_AHB1PERIPH_BASE + 0x2000UL)

+#define FMC_R_BASE            (D1_AHB1PERIPH_BASE + 0x4000UL)

+#define QSPI_R_BASE           (D1_AHB1PERIPH_BASE + 0x5000UL)

+#define DLYB_QSPI_BASE        (D1_AHB1PERIPH_BASE + 0x6000UL)

+#define SDMMC1_BASE           (D1_AHB1PERIPH_BASE + 0x7000UL)

+#define DLYB_SDMMC1_BASE      (D1_AHB1PERIPH_BASE + 0x8000UL)

+#define RAMECC1_BASE          (D1_AHB1PERIPH_BASE + 0x9000UL)

+

+/*!< D2_AHB1PERIPH peripherals */

+

+#define DMA1_BASE               (D2_AHB1PERIPH_BASE + 0x0000UL)

+#define DMA2_BASE               (D2_AHB1PERIPH_BASE + 0x0400UL)

+#define DMAMUX1_BASE            (D2_AHB1PERIPH_BASE + 0x0800UL)

+#define ADC1_BASE               (D2_AHB1PERIPH_BASE + 0x2000UL)

+#define ADC2_BASE               (D2_AHB1PERIPH_BASE + 0x2100UL)

+#define ADC12_COMMON_BASE       (D2_AHB1PERIPH_BASE + 0x2300UL)

+#define ART_BASE                (D2_AHB1PERIPH_BASE + 0x4400UL)

+#define ETH_BASE                (D2_AHB1PERIPH_BASE + 0x8000UL)

+#define ETH_MAC_BASE            (ETH_BASE)

+

+/*!< USB registers base address */

+#define USB1_OTG_HS_PERIPH_BASE              (0x40040000UL)

+#define USB2_OTG_FS_PERIPH_BASE              (0x40080000UL)

+#define USB_OTG_GLOBAL_BASE                  (0x000UL)

+#define USB_OTG_DEVICE_BASE                  (0x800UL)

+#define USB_OTG_IN_ENDPOINT_BASE             (0x900UL)

+#define USB_OTG_OUT_ENDPOINT_BASE            (0xB00UL)

+#define USB_OTG_EP_REG_SIZE                  (0x20UL)

+#define USB_OTG_HOST_BASE                    (0x400UL)

+#define USB_OTG_HOST_PORT_BASE               (0x440UL)

+#define USB_OTG_HOST_CHANNEL_BASE            (0x500UL)

+#define USB_OTG_HOST_CHANNEL_SIZE            (0x20UL)

+#define USB_OTG_PCGCCTL_BASE                 (0xE00UL)

+#define USB_OTG_FIFO_BASE                    (0x1000UL)

+#define USB_OTG_FIFO_SIZE                    (0x1000UL)

+

+/*!< D2_AHB2PERIPH peripherals */

+

+#define DCMI_BASE              (D2_AHB2PERIPH_BASE + 0x0000UL)

+#define RNG_BASE               (D2_AHB2PERIPH_BASE + 0x1800UL)

+#define SDMMC2_BASE            (D2_AHB2PERIPH_BASE + 0x2400UL)

+#define DLYB_SDMMC2_BASE       (D2_AHB2PERIPH_BASE + 0x2800UL)

+#define RAMECC2_BASE           (D2_AHB2PERIPH_BASE + 0x3000UL)

+

+/*!< D3_AHB1PERIPH peripherals */

+#define GPIOA_BASE            (D3_AHB1PERIPH_BASE + 0x0000UL)

+#define GPIOB_BASE            (D3_AHB1PERIPH_BASE + 0x0400UL)

+#define GPIOC_BASE            (D3_AHB1PERIPH_BASE + 0x0800UL)

+#define GPIOD_BASE            (D3_AHB1PERIPH_BASE + 0x0C00UL)

+#define GPIOE_BASE            (D3_AHB1PERIPH_BASE + 0x1000UL)

+#define GPIOF_BASE            (D3_AHB1PERIPH_BASE + 0x1400UL)

+#define GPIOG_BASE            (D3_AHB1PERIPH_BASE + 0x1800UL)

+#define GPIOH_BASE            (D3_AHB1PERIPH_BASE + 0x1C00UL)

+#define GPIOI_BASE            (D3_AHB1PERIPH_BASE + 0x2000UL)

+#define GPIOJ_BASE            (D3_AHB1PERIPH_BASE + 0x2400UL)

+#define GPIOK_BASE            (D3_AHB1PERIPH_BASE + 0x2800UL)

+#define RCC_BASE              (D3_AHB1PERIPH_BASE + 0x4400UL)

+#define RCC_C1_BASE           (RCC_BASE + 0x130UL)

+#define RCC_C2_BASE           (RCC_BASE + 0x190UL)

+#define PWR_BASE              (D3_AHB1PERIPH_BASE + 0x4800UL)

+#define CRC_BASE              (D3_AHB1PERIPH_BASE + 0x4C00UL)

+#define BDMA_BASE             (D3_AHB1PERIPH_BASE + 0x5400UL)

+#define DMAMUX2_BASE          (D3_AHB1PERIPH_BASE + 0x5800UL)

+#define ADC3_BASE             (D3_AHB1PERIPH_BASE + 0x6000UL)

+#define ADC3_COMMON_BASE      (D3_AHB1PERIPH_BASE + 0x6300UL)

+#define HSEM_BASE             (D3_AHB1PERIPH_BASE + 0x6400UL)

+#define RAMECC3_BASE          (D3_AHB1PERIPH_BASE + 0x7000UL)

+

+/*!< D1_APB1PERIPH peripherals */

+#define LTDC_BASE             (D1_APB1PERIPH_BASE + 0x1000UL)

+#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84UL)

+#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104UL)

+#define DSI_BASE              (D1_APB1PERIPH_BASE)

+#define WWDG1_BASE            (D1_APB1PERIPH_BASE + 0x3000UL)

+

+/*!< D2_APB1PERIPH peripherals */

+#define TIM2_BASE             (D2_APB1PERIPH_BASE + 0x0000UL)

+#define TIM3_BASE             (D2_APB1PERIPH_BASE + 0x0400UL)

+#define TIM4_BASE             (D2_APB1PERIPH_BASE + 0x0800UL)

+#define TIM5_BASE             (D2_APB1PERIPH_BASE + 0x0C00UL)

+#define TIM6_BASE             (D2_APB1PERIPH_BASE + 0x1000UL)

+#define TIM7_BASE             (D2_APB1PERIPH_BASE + 0x1400UL)

+#define TIM12_BASE            (D2_APB1PERIPH_BASE + 0x1800UL)

+#define TIM13_BASE            (D2_APB1PERIPH_BASE + 0x1C00UL)

+#define TIM14_BASE            (D2_APB1PERIPH_BASE + 0x2000UL)

+#define LPTIM1_BASE           (D2_APB1PERIPH_BASE + 0x2400UL)

+

+#define WWDG2_BASE            (D2_APB1PERIPH_BASE + 0x2C00UL)

+

+#define SPI2_BASE             (D2_APB1PERIPH_BASE + 0x3800UL)

+#define SPI3_BASE             (D2_APB1PERIPH_BASE + 0x3C00UL)

+#define SPDIFRX_BASE          (D2_APB1PERIPH_BASE + 0x4000UL)

+#define USART2_BASE           (D2_APB1PERIPH_BASE + 0x4400UL)

+#define USART3_BASE           (D2_APB1PERIPH_BASE + 0x4800UL)

+#define UART4_BASE            (D2_APB1PERIPH_BASE + 0x4C00UL)

+#define UART5_BASE            (D2_APB1PERIPH_BASE + 0x5000UL)

+#define I2C1_BASE             (D2_APB1PERIPH_BASE + 0x5400UL)

+#define I2C2_BASE             (D2_APB1PERIPH_BASE + 0x5800UL)

+#define I2C3_BASE             (D2_APB1PERIPH_BASE + 0x5C00UL)

+#define CEC_BASE              (D2_APB1PERIPH_BASE + 0x6C00UL)

+#define DAC1_BASE             (D2_APB1PERIPH_BASE + 0x7400UL)

+#define UART7_BASE            (D2_APB1PERIPH_BASE + 0x7800UL)

+#define UART8_BASE            (D2_APB1PERIPH_BASE + 0x7C00UL)

+#define CRS_BASE              (D2_APB1PERIPH_BASE + 0x8400UL)

+#define SWPMI1_BASE           (D2_APB1PERIPH_BASE + 0x8800UL)

+#define OPAMP_BASE            (D2_APB1PERIPH_BASE + 0x9000UL)

+#define OPAMP1_BASE           (D2_APB1PERIPH_BASE + 0x9000UL)

+#define OPAMP2_BASE           (D2_APB1PERIPH_BASE + 0x9010UL)

+#define MDIOS_BASE            (D2_APB1PERIPH_BASE + 0x9400UL)

+#define FDCAN1_BASE           (D2_APB1PERIPH_BASE + 0xA000UL)

+#define FDCAN2_BASE           (D2_APB1PERIPH_BASE + 0xA400UL)

+#define FDCAN_CCU_BASE        (D2_APB1PERIPH_BASE + 0xA800UL)

+#define SRAMCAN_BASE          (D2_APB1PERIPH_BASE + 0xAC00UL)

+

+/*!< D2_APB2PERIPH peripherals */

+

+#define TIM1_BASE             (D2_APB2PERIPH_BASE + 0x0000UL)

+#define TIM8_BASE             (D2_APB2PERIPH_BASE + 0x0400UL)

+#define USART1_BASE           (D2_APB2PERIPH_BASE + 0x1000UL)

+#define USART6_BASE           (D2_APB2PERIPH_BASE + 0x1400UL)

+#define SPI1_BASE             (D2_APB2PERIPH_BASE + 0x3000UL)

+#define SPI4_BASE             (D2_APB2PERIPH_BASE + 0x3400UL)

+#define TIM15_BASE            (D2_APB2PERIPH_BASE + 0x4000UL)

+#define TIM16_BASE            (D2_APB2PERIPH_BASE + 0x4400UL)

+#define TIM17_BASE            (D2_APB2PERIPH_BASE + 0x4800UL)

+#define SPI5_BASE             (D2_APB2PERIPH_BASE + 0x5000UL)

+#define SAI1_BASE             (D2_APB2PERIPH_BASE + 0x5800UL)

+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)

+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)

+#define SAI2_BASE             (D2_APB2PERIPH_BASE + 0x5C00UL)

+#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004UL)

+#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024UL)

+#define SAI3_BASE             (D2_APB2PERIPH_BASE + 0x6000UL)

+#define SAI3_Block_A_BASE     (SAI3_BASE + 0x004UL)

+#define SAI3_Block_B_BASE     (SAI3_BASE + 0x024UL)

+#define DFSDM1_BASE           (D2_APB2PERIPH_BASE + 0x7000UL)

+#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00UL)

+#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20UL)

+#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40UL)

+#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60UL)

+#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80UL)

+#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0UL)

+#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0UL)

+#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0UL)

+#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)

+#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)

+#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)

+#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)

+#define HRTIM1_BASE           (D2_APB2PERIPH_BASE + 0x7400UL)

+#define HRTIM1_TIMA_BASE      (HRTIM1_BASE + 0x00000080UL)

+#define HRTIM1_TIMB_BASE      (HRTIM1_BASE + 0x00000100UL)

+#define HRTIM1_TIMC_BASE      (HRTIM1_BASE + 0x00000180UL)

+#define HRTIM1_TIMD_BASE      (HRTIM1_BASE + 0x00000200UL)

+#define HRTIM1_TIME_BASE      (HRTIM1_BASE + 0x00000280UL)

+#define HRTIM1_COMMON_BASE    (HRTIM1_BASE + 0x00000380UL)

+

+

+/*!< D3_APB1PERIPH peripherals */

+#define EXTI_BASE             (D3_APB1PERIPH_BASE + 0x0000UL)

+#define EXTI_D1_BASE          (EXTI_BASE + 0x0080UL)

+#define EXTI_D2_BASE          (EXTI_BASE + 0x00C0UL)

+#define SYSCFG_BASE           (D3_APB1PERIPH_BASE + 0x0400UL)

+#define LPUART1_BASE          (D3_APB1PERIPH_BASE + 0x0C00UL)

+#define SPI6_BASE             (D3_APB1PERIPH_BASE + 0x1400UL)

+#define I2C4_BASE             (D3_APB1PERIPH_BASE + 0x1C00UL)

+#define LPTIM2_BASE           (D3_APB1PERIPH_BASE + 0x2400UL)

+#define LPTIM3_BASE           (D3_APB1PERIPH_BASE + 0x2800UL)

+#define LPTIM4_BASE           (D3_APB1PERIPH_BASE + 0x2C00UL)

+#define LPTIM5_BASE           (D3_APB1PERIPH_BASE + 0x3000UL)

+#define COMP12_BASE           (D3_APB1PERIPH_BASE + 0x3800UL)

+#define COMP1_BASE            (COMP12_BASE + 0x0CUL)

+#define COMP2_BASE            (COMP12_BASE + 0x10UL)

+#define VREFBUF_BASE          (D3_APB1PERIPH_BASE + 0x3C00UL)

+#define RTC_BASE              (D3_APB1PERIPH_BASE + 0x4000UL)

+#define IWDG1_BASE            (D3_APB1PERIPH_BASE + 0x4800UL)

+

+#define IWDG2_BASE            (D3_APB1PERIPH_BASE + 0x4C00UL)

+

+#define SAI4_BASE             (D3_APB1PERIPH_BASE + 0x5400UL)

+#define SAI4_Block_A_BASE     (SAI4_BASE + 0x004UL)

+#define SAI4_Block_B_BASE     (SAI4_BASE + 0x024UL)

+

+

+

+

+#define BDMA_Channel0_BASE    (BDMA_BASE + 0x0008UL)

+#define BDMA_Channel1_BASE    (BDMA_BASE + 0x001CUL)

+#define BDMA_Channel2_BASE    (BDMA_BASE + 0x0030UL)

+#define BDMA_Channel3_BASE    (BDMA_BASE + 0x0044UL)

+#define BDMA_Channel4_BASE    (BDMA_BASE + 0x0058UL)

+#define BDMA_Channel5_BASE    (BDMA_BASE + 0x006CUL)

+#define BDMA_Channel6_BASE    (BDMA_BASE + 0x0080UL)

+#define BDMA_Channel7_BASE    (BDMA_BASE + 0x0094UL)

+

+#define DMAMUX2_Channel0_BASE    (DMAMUX2_BASE)

+#define DMAMUX2_Channel1_BASE    (DMAMUX2_BASE + 0x0004UL)

+#define DMAMUX2_Channel2_BASE    (DMAMUX2_BASE + 0x0008UL)

+#define DMAMUX2_Channel3_BASE    (DMAMUX2_BASE + 0x000CUL)

+#define DMAMUX2_Channel4_BASE    (DMAMUX2_BASE + 0x0010UL)

+#define DMAMUX2_Channel5_BASE    (DMAMUX2_BASE + 0x0014UL)

+#define DMAMUX2_Channel6_BASE    (DMAMUX2_BASE + 0x0018UL)

+#define DMAMUX2_Channel7_BASE    (DMAMUX2_BASE + 0x001CUL)

+

+#define DMAMUX2_RequestGenerator0_BASE  (DMAMUX2_BASE + 0x0100UL)

+#define DMAMUX2_RequestGenerator1_BASE  (DMAMUX2_BASE + 0x0104UL)

+#define DMAMUX2_RequestGenerator2_BASE  (DMAMUX2_BASE + 0x0108UL)

+#define DMAMUX2_RequestGenerator3_BASE  (DMAMUX2_BASE + 0x010CUL)

+#define DMAMUX2_RequestGenerator4_BASE  (DMAMUX2_BASE + 0x0110UL)

+#define DMAMUX2_RequestGenerator5_BASE  (DMAMUX2_BASE + 0x0114UL)

+#define DMAMUX2_RequestGenerator6_BASE  (DMAMUX2_BASE + 0x0118UL)

+#define DMAMUX2_RequestGenerator7_BASE  (DMAMUX2_BASE + 0x011CUL)

+

+#define DMAMUX2_ChannelStatus_BASE      (DMAMUX2_BASE + 0x0080UL)

+#define DMAMUX2_RequestGenStatus_BASE   (DMAMUX2_BASE + 0x0140UL)

+

+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)

+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)

+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)

+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)

+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)

+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)

+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)

+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)

+

+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)

+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)

+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)

+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)

+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)

+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)

+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)

+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)

+

+#define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)

+#define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)

+#define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)

+#define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)

+#define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)

+#define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)

+#define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0018UL)

+#define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x001CUL)

+#define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0020UL)

+#define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x0024UL)

+#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)

+#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)

+#define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)

+#define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)

+#define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)

+#define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)

+

+#define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)

+#define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)

+#define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)

+#define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)

+#define DMAMUX1_RequestGenerator4_BASE  (DMAMUX1_BASE + 0x0110UL)

+#define DMAMUX1_RequestGenerator5_BASE  (DMAMUX1_BASE + 0x0114UL)

+#define DMAMUX1_RequestGenerator6_BASE  (DMAMUX1_BASE + 0x0118UL)

+#define DMAMUX1_RequestGenerator7_BASE  (DMAMUX1_BASE + 0x011CUL)

+

+#define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)

+#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)

+

+/*!< FMC Banks registers base  address */

+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)

+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)

+#define FMC_Bank2_R_BASE      (FMC_R_BASE + 0x0060UL)

+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)

+#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)

+

+/* Debug MCU registers base address */

+#define DBGMCU_BASE           (0x5C001000UL)

+

+#define MDMA_Channel0_BASE    (MDMA_BASE + 0x00000040UL)

+#define MDMA_Channel1_BASE    (MDMA_BASE + 0x00000080UL)

+#define MDMA_Channel2_BASE    (MDMA_BASE + 0x000000C0UL)

+#define MDMA_Channel3_BASE    (MDMA_BASE + 0x00000100UL)

+#define MDMA_Channel4_BASE    (MDMA_BASE + 0x00000140UL)

+#define MDMA_Channel5_BASE    (MDMA_BASE + 0x00000180UL)

+#define MDMA_Channel6_BASE    (MDMA_BASE + 0x000001C0UL)

+#define MDMA_Channel7_BASE    (MDMA_BASE + 0x00000200UL)

+#define MDMA_Channel8_BASE    (MDMA_BASE + 0x00000240UL)

+#define MDMA_Channel9_BASE    (MDMA_BASE + 0x00000280UL)

+#define MDMA_Channel10_BASE   (MDMA_BASE + 0x000002C0UL)

+#define MDMA_Channel11_BASE   (MDMA_BASE + 0x00000300UL)

+#define MDMA_Channel12_BASE   (MDMA_BASE + 0x00000340UL)

+#define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)

+#define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)

+#define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)

+

+#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)

+#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)

+#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)

+#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)

+#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)

+

+#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)

+#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)

+#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)

+#define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL)

+#define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL)

+

+#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)

+#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)

+

+

+/**

+  * @}

+  */

+

+/** @addtogroup Peripheral_declaration

+  * @{

+  */

+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)

+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)

+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)

+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)

+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)

+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)

+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)

+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)

+#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)

+#define RTC                 ((RTC_TypeDef *) RTC_BASE)

+#define WWDG1               ((WWDG_TypeDef *) WWDG1_BASE)

+

+#define WWDG2               ((WWDG_TypeDef *) WWDG2_BASE)

+#define IWDG2               ((IWDG_TypeDef *) IWDG2_BASE)

+

+#define IWDG1               ((IWDG_TypeDef *) IWDG1_BASE)

+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)

+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)

+#define SPI4                ((SPI_TypeDef *) SPI4_BASE)

+#define SPI5                ((SPI_TypeDef *) SPI5_BASE)

+#define SPI6                ((SPI_TypeDef *) SPI6_BASE)

+#define USART2              ((USART_TypeDef *) USART2_BASE)

+#define USART3              ((USART_TypeDef *) USART3_BASE)

+#define USART6              ((USART_TypeDef *) USART6_BASE)

+#define UART7               ((USART_TypeDef *) UART7_BASE)

+#define UART8               ((USART_TypeDef *) UART8_BASE)

+#define CRS                 ((CRS_TypeDef *) CRS_BASE)

+#define UART4               ((USART_TypeDef *) UART4_BASE)

+#define UART5               ((USART_TypeDef *) UART5_BASE)

+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)

+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)

+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)

+#define I2C4                ((I2C_TypeDef *) I2C4_BASE)

+#define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

+#define FDCAN2              ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

+#define FDCAN_CCU           ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

+#define CEC                 ((CEC_TypeDef *) CEC_BASE)

+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)

+#define PWR                 ((PWR_TypeDef *) PWR_BASE)

+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)

+#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)

+#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)

+#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)

+#define LPTIM3              ((LPTIM_TypeDef *) LPTIM3_BASE)

+#define LPTIM4              ((LPTIM_TypeDef *) LPTIM4_BASE)

+#define LPTIM5              ((LPTIM_TypeDef *) LPTIM5_BASE)

+

+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)

+#define COMP12              ((COMPOPT_TypeDef *) COMP12_BASE)

+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)

+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)

+#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)

+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)

+#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)

+#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)

+

+

+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)

+#define EXTI_D1             ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

+#define EXTI_D2             ((EXTI_Core_TypeDef *) EXTI_D2_BASE)

+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)

+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)

+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)

+#define USART1              ((USART_TypeDef *) USART1_BASE)

+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)

+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)

+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)

+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)

+#define HRTIM1              ((HRTIM_TypeDef *) HRTIM1_BASE)

+#define HRTIM1_TIMA         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)

+#define HRTIM1_TIMB         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)

+#define HRTIM1_TIMC         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)

+#define HRTIM1_TIMD         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)

+#define HRTIM1_TIME         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)

+#define HRTIM1_COMMON       ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)

+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)

+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

+#define SAI2                ((SAI_TypeDef *) SAI2_BASE)

+#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)

+#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)

+#define SAI3                ((SAI_TypeDef *) SAI3_BASE)

+#define SAI3_Block_A        ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)

+#define SAI3_Block_B        ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)

+#define SAI4                ((SAI_TypeDef *) SAI4_BASE)

+#define SAI4_Block_A        ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)

+#define SAI4_Block_B        ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)

+

+#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

+#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

+#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

+#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

+#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

+#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

+#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

+#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

+#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

+#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

+#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

+#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

+#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

+#define DMA2D               ((DMA2D_TypeDef *) DMA2D_BASE)

+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)

+#define RCC                 ((RCC_TypeDef *) RCC_BASE)

+#define RCC_C1              ((RCC_Core_TypeDef *) RCC_C1_BASE)

+#define RCC_C2              ((RCC_Core_TypeDef *) RCC_C2_BASE)

+

+#define ART                 ((ART_TypeDef *)  ART_BASE)

+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)

+#define CRC                 ((CRC_TypeDef *) CRC_BASE)

+

+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)

+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)

+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)

+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)

+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)

+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)

+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)

+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)

+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)

+#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)

+#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)

+

+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)

+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)

+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)

+#define ADC3_COMMON         ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)

+#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

+

+#define RNG                 ((RNG_TypeDef *) RNG_BASE)

+#define SDMMC2              ((SDMMC_TypeDef *) SDMMC2_BASE)

+#define DLYB_SDMMC2         ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

+

+#define BDMA                ((BDMA_TypeDef *) BDMA_BASE)

+#define BDMA_Channel0       ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)

+#define BDMA_Channel1       ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)

+#define BDMA_Channel2       ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)

+#define BDMA_Channel3       ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)

+#define BDMA_Channel4       ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)

+#define BDMA_Channel5       ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)

+#define BDMA_Channel6       ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)

+#define BDMA_Channel7       ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)

+

+#define RAMECC1              ((RAMECC_TypeDef *)RAMECC1_BASE)

+#define RAMECC1_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)

+#define RAMECC1_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)

+#define RAMECC1_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)

+#define RAMECC1_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)

+#define RAMECC1_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)

+

+#define RAMECC2              ((RAMECC_TypeDef *)RAMECC2_BASE)

+#define RAMECC2_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)

+#define RAMECC2_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)

+#define RAMECC2_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)

+#define RAMECC2_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)

+#define RAMECC2_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)

+

+#define RAMECC3              ((RAMECC_TypeDef *)RAMECC3_BASE)

+#define RAMECC3_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)

+#define RAMECC3_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)

+

+#define DMAMUX2                ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

+#define DMAMUX2_Channel0       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

+#define DMAMUX2_Channel1       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

+#define DMAMUX2_Channel2       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

+#define DMAMUX2_Channel3       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

+#define DMAMUX2_Channel4       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

+#define DMAMUX2_Channel5       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

+#define DMAMUX2_Channel6       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

+#define DMAMUX2_Channel7       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

+

+

+#define DMAMUX2_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

+#define DMAMUX2_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

+#define DMAMUX2_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

+#define DMAMUX2_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

+#define DMAMUX2_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

+#define DMAMUX2_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

+#define DMAMUX2_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

+#define DMAMUX2_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

+

+#define DMAMUX2_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

+#define DMAMUX2_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

+

+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)

+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

+

+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)

+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

+

+

+#define DMAMUX1              ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

+#define DMAMUX1_Channel0     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

+#define DMAMUX1_Channel1     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

+#define DMAMUX1_Channel2     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

+#define DMAMUX1_Channel3     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

+#define DMAMUX1_Channel4     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

+#define DMAMUX1_Channel5     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

+#define DMAMUX1_Channel6     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

+#define DMAMUX1_Channel7     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

+#define DMAMUX1_Channel8     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

+#define DMAMUX1_Channel9     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

+#define DMAMUX1_Channel10    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

+#define DMAMUX1_Channel11    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

+#define DMAMUX1_Channel12    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

+#define DMAMUX1_Channel13    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

+#define DMAMUX1_Channel14    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

+#define DMAMUX1_Channel15    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

+

+#define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

+#define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

+#define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

+#define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

+#define DMAMUX1_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

+#define DMAMUX1_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

+#define DMAMUX1_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

+#define DMAMUX1_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

+

+#define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *)    DMAMUX1_ChannelStatus_BASE)

+#define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

+

+

+#define FMC_Bank1_R           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

+#define FMC_Bank1E_R          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

+#define FMC_Bank2_R           ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

+#define FMC_Bank3_R           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

+#define FMC_Bank5_6_R         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

+

+

+#define QUADSPI               ((QUADSPI_TypeDef *) QSPI_R_BASE)

+#define DLYB_QUADSPI          ((DLYB_TypeDef *) DLYB_QSPI_BASE)

+#define SDMMC1                ((SDMMC_TypeDef *) SDMMC1_BASE)

+#define DLYB_SDMMC1           ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

+

+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)

+

+#define JPEG                ((JPEG_TypeDef *) JPGDEC_BASE)

+#define HSEM                ((HSEM_TypeDef *) HSEM_BASE)

+#if defined(CORE_CM4)

+#define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x110UL))

+#else  /* CORE_CM7 */

+#define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

+#endif /* CORE_CM4 */

+

+#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)

+#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

+#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

+#define DSI                 ((DSI_TypeDef *)DSI_BASE)

+

+#define MDIOS               ((MDIOS_TypeDef *) MDIOS_BASE)

+

+#define ETH                 ((ETH_TypeDef *)ETH_BASE)

+#define MDMA                ((MDMA_TypeDef *)MDMA_BASE)

+#define MDMA_Channel0       ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

+#define MDMA_Channel1       ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

+#define MDMA_Channel2       ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

+#define MDMA_Channel3       ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

+#define MDMA_Channel4       ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

+#define MDMA_Channel5       ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

+#define MDMA_Channel6       ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

+#define MDMA_Channel7       ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

+#define MDMA_Channel8       ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

+#define MDMA_Channel9       ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

+#define MDMA_Channel10      ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

+#define MDMA_Channel11      ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

+#define MDMA_Channel12      ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

+#define MDMA_Channel13      ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

+#define MDMA_Channel14      ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

+#define MDMA_Channel15      ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

+

+

+#define USB1_OTG_HS         ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

+#define USB2_OTG_FS         ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)

+

+/* Legacy defines */

+#define USB_OTG_HS                   USB1_OTG_HS

+#define USB_OTG_HS_PERIPH_BASE       USB1_OTG_HS_PERIPH_BASE

+#define USB_OTG_FS                   USB2_OTG_FS

+#define USB_OTG_FS_PERIPH_BASE       USB2_OTG_FS_PERIPH_BASE

+

+/**

+  * @}

+  */

+

+/** @addtogroup Exported_constants

+  * @{

+  */

+

+  /** @addtogroup Peripheral_Registers_Bits_Definition

+  * @{

+  */

+

+/******************************************************************************/

+/*                         Peripheral Registers_Bits_Definition               */

+/******************************************************************************/

+

+/******************************************************************************/

+/*                                                                            */

+/*                        Analog to Digital Converter                         */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  ADC VERSION  ********************************/

+#define ADC_VER_V5_X

+/********************  Bit definition for ADC_ISR register  ********************/

+#define ADC_ISR_ADRDY_Pos                 (0U)

+#define ADC_ISR_ADRDY_Msk                 (0x1UL << ADC_ISR_ADRDY_Pos)         /*!< 0x00000001 */

+#define ADC_ISR_ADRDY                     ADC_ISR_ADRDY_Msk                    /*!< ADC Ready (ADRDY) flag  */

+#define ADC_ISR_EOSMP_Pos                 (1U)

+#define ADC_ISR_EOSMP_Msk                 (0x1UL << ADC_ISR_EOSMP_Pos)         /*!< 0x00000002 */

+#define ADC_ISR_EOSMP                     ADC_ISR_EOSMP_Msk                    /*!< ADC End of Sampling flag */

+#define ADC_ISR_EOC_Pos                   (2U)

+#define ADC_ISR_EOC_Msk                   (0x1UL << ADC_ISR_EOC_Pos)           /*!< 0x00000004 */

+#define ADC_ISR_EOC                       ADC_ISR_EOC_Msk                      /*!< ADC End of Regular Conversion flag */

+#define ADC_ISR_EOS_Pos                   (3U)

+#define ADC_ISR_EOS_Msk                   (0x1UL << ADC_ISR_EOS_Pos)           /*!< 0x00000008 */

+#define ADC_ISR_EOS                       ADC_ISR_EOS_Msk                      /*!< ADC End of Regular sequence of Conversions flag */

+#define ADC_ISR_OVR_Pos                   (4U)

+#define ADC_ISR_OVR_Msk                   (0x1UL << ADC_ISR_OVR_Pos)           /*!< 0x00000010 */

+#define ADC_ISR_OVR                       ADC_ISR_OVR_Msk                      /*!< ADC overrun flag */

+#define ADC_ISR_JEOC_Pos                  (5U)

+#define ADC_ISR_JEOC_Msk                  (0x1UL << ADC_ISR_JEOC_Pos)          /*!< 0x00000020 */

+#define ADC_ISR_JEOC                      ADC_ISR_JEOC_Msk                     /*!< ADC End of Injected Conversion flag */

+#define ADC_ISR_JEOS_Pos                  (6U)

+#define ADC_ISR_JEOS_Msk                  (0x1UL << ADC_ISR_JEOS_Pos)          /*!< 0x00000040 */

+#define ADC_ISR_JEOS                      ADC_ISR_JEOS_Msk                     /*!< ADC End of Injected sequence of Conversions flag */

+#define ADC_ISR_AWD1_Pos                  (7U)

+#define ADC_ISR_AWD1_Msk                  (0x1UL << ADC_ISR_AWD1_Pos)          /*!< 0x00000080 */

+#define ADC_ISR_AWD1                      ADC_ISR_AWD1_Msk                     /*!< ADC Analog watchdog 1 flag */

+#define ADC_ISR_AWD2_Pos                  (8U)

+#define ADC_ISR_AWD2_Msk                  (0x1UL << ADC_ISR_AWD2_Pos)          /*!< 0x00000100 */

+#define ADC_ISR_AWD2                      ADC_ISR_AWD2_Msk                     /*!< ADC Analog watchdog 2 flag */

+#define ADC_ISR_AWD3_Pos                  (9U)

+#define ADC_ISR_AWD3_Msk                  (0x1UL << ADC_ISR_AWD3_Pos)          /*!< 0x00000200 */

+#define ADC_ISR_AWD3                      ADC_ISR_AWD3_Msk                     /*!< ADC Analog watchdog 3 flag */

+#define ADC_ISR_JQOVF_Pos                 (10U)

+#define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */

+#define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */

+

+/********************  Bit definition for ADC_IER register  ********************/

+#define ADC_IER_ADRDYIE_Pos               (0U)

+#define ADC_IER_ADRDYIE_Msk               (0x1UL << ADC_IER_ADRDYIE_Pos)       /*!< 0x00000001 */

+#define ADC_IER_ADRDYIE                   ADC_IER_ADRDYIE_Msk                  /*!< ADC Ready (ADRDY) interrupt source */

+#define ADC_IER_EOSMPIE_Pos               (1U)

+#define ADC_IER_EOSMPIE_Msk               (0x1UL << ADC_IER_EOSMPIE_Pos)       /*!< 0x00000002 */

+#define ADC_IER_EOSMPIE                   ADC_IER_EOSMPIE_Msk                  /*!< ADC End of Sampling interrupt source */

+#define ADC_IER_EOCIE_Pos                 (2U)

+#define ADC_IER_EOCIE_Msk                 (0x1UL << ADC_IER_EOCIE_Pos)         /*!< 0x00000004 */

+#define ADC_IER_EOCIE                     ADC_IER_EOCIE_Msk                    /*!< ADC End of Regular Conversion interrupt source */

+#define ADC_IER_EOSIE_Pos                 (3U)

+#define ADC_IER_EOSIE_Msk                 (0x1UL << ADC_IER_EOSIE_Pos)         /*!< 0x00000008 */

+#define ADC_IER_EOSIE                     ADC_IER_EOSIE_Msk                    /*!< ADC End of Regular sequence of Conversions interrupt source */

+#define ADC_IER_OVRIE_Pos                 (4U)

+#define ADC_IER_OVRIE_Msk                 (0x1UL << ADC_IER_OVRIE_Pos)         /*!< 0x00000010 */

+#define ADC_IER_OVRIE                     ADC_IER_OVRIE_Msk                    /*!< ADC overrun interrupt source */

+#define ADC_IER_JEOCIE_Pos                (5U)

+#define ADC_IER_JEOCIE_Msk                (0x1UL << ADC_IER_JEOCIE_Pos)        /*!< 0x00000020 */

+#define ADC_IER_JEOCIE                    ADC_IER_JEOCIE_Msk                   /*!< ADC End of Injected Conversion interrupt source */

+#define ADC_IER_JEOSIE_Pos                (6U)

+#define ADC_IER_JEOSIE_Msk                (0x1UL << ADC_IER_JEOSIE_Pos)        /*!< 0x00000040 */

+#define ADC_IER_JEOSIE                    ADC_IER_JEOSIE_Msk                   /*!< ADC End of Injected sequence of Conversions interrupt source */

+#define ADC_IER_AWD1IE_Pos                (7U)

+#define ADC_IER_AWD1IE_Msk                (0x1UL << ADC_IER_AWD1IE_Pos)        /*!< 0x00000080 */

+#define ADC_IER_AWD1IE                    ADC_IER_AWD1IE_Msk                   /*!< ADC Analog watchdog 1 interrupt source */

+#define ADC_IER_AWD2IE_Pos                (8U)

+#define ADC_IER_AWD2IE_Msk                (0x1UL << ADC_IER_AWD2IE_Pos)        /*!< 0x00000100 */

+#define ADC_IER_AWD2IE                    ADC_IER_AWD2IE_Msk                   /*!< ADC Analog watchdog 2 interrupt source */

+#define ADC_IER_AWD3IE_Pos                (9U)

+#define ADC_IER_AWD3IE_Msk                (0x1UL << ADC_IER_AWD3IE_Pos)        /*!< 0x00000200 */

+#define ADC_IER_AWD3IE                    ADC_IER_AWD3IE_Msk                   /*!< ADC Analog watchdog 3 interrupt source */

+#define ADC_IER_JQOVFIE_Pos               (10U)

+#define ADC_IER_JQOVFIE_Msk               (0x1UL << ADC_IER_JQOVFIE_Pos)       /*!< 0x00000400 */

+#define ADC_IER_JQOVFIE                   ADC_IER_JQOVFIE_Msk                  /*!< ADC Injected Context Queue Overflow interrupt source */

+

+/********************  Bit definition for ADC_CR register  ********************/

+#define ADC_CR_ADEN_Pos                   (0U)

+#define ADC_CR_ADEN_Msk                   (0x1UL << ADC_CR_ADEN_Pos)           /*!< 0x00000001 */

+#define ADC_CR_ADEN                       ADC_CR_ADEN_Msk                      /*!< ADC Enable control */

+#define ADC_CR_ADDIS_Pos                  (1U)

+#define ADC_CR_ADDIS_Msk                  (0x1UL << ADC_CR_ADDIS_Pos)          /*!< 0x00000002 */

+#define ADC_CR_ADDIS                      ADC_CR_ADDIS_Msk                     /*!< ADC Disable command */

+#define ADC_CR_ADSTART_Pos                (2U)

+#define ADC_CR_ADSTART_Msk                (0x1UL << ADC_CR_ADSTART_Pos)        /*!< 0x00000004 */

+#define ADC_CR_ADSTART                    ADC_CR_ADSTART_Msk                   /*!< ADC Start of Regular conversion */

+#define ADC_CR_JADSTART_Pos               (3U)

+#define ADC_CR_JADSTART_Msk               (0x1UL << ADC_CR_JADSTART_Pos)       /*!< 0x00000008 */

+#define ADC_CR_JADSTART                   ADC_CR_JADSTART_Msk                  /*!< ADC Start of injected conversion */

+#define ADC_CR_ADSTP_Pos                  (4U)

+#define ADC_CR_ADSTP_Msk                  (0x1UL << ADC_CR_ADSTP_Pos)          /*!< 0x00000010 */

+#define ADC_CR_ADSTP                      ADC_CR_ADSTP_Msk                     /*!< ADC Stop of Regular conversion */

+#define ADC_CR_JADSTP_Pos                 (5U)

+#define ADC_CR_JADSTP_Msk                 (0x1UL << ADC_CR_JADSTP_Pos)         /*!< 0x00000020 */

+#define ADC_CR_JADSTP                     ADC_CR_JADSTP_Msk                    /*!< ADC Stop of injected conversion */

+#define ADC_CR_BOOST_Pos                  (8U)

+#define ADC_CR_BOOST_Msk                  (0x3UL << ADC_CR_BOOST_Pos)          /*!< 0x00000300 */

+#define ADC_CR_BOOST                      ADC_CR_BOOST_Msk                     /*!< ADC Boost Mode configuration */

+#define ADC_CR_BOOST_0                    (0x1UL << ADC_CR_BOOST_Pos)           /*!< 0x00000100 */

+#define ADC_CR_BOOST_1                    (0x2UL << ADC_CR_BOOST_Pos)           /*!< 0x00000200 */

+#define ADC_CR_ADCALLIN_Pos               (16U)

+#define ADC_CR_ADCALLIN_Msk               (0x1UL << ADC_CR_ADCALLIN_Pos)       /*!< 0x00010000 */

+#define ADC_CR_ADCALLIN                   ADC_CR_ADCALLIN_Msk                  /*!< ADC Linearity calibration */

+#define ADC_CR_LINCALRDYW1_Pos            (22U)

+#define ADC_CR_LINCALRDYW1_Msk            (0x1UL << ADC_CR_LINCALRDYW1_Pos)    /*!< 0x00400000 */

+#define ADC_CR_LINCALRDYW1                ADC_CR_LINCALRDYW1_Msk               /*!< ADC Linearity calibration ready Word 1 */

+#define ADC_CR_LINCALRDYW2_Pos            (23U)

+#define ADC_CR_LINCALRDYW2_Msk            (0x1UL << ADC_CR_LINCALRDYW2_Pos)    /*!< 0x00800000 */

+#define ADC_CR_LINCALRDYW2                ADC_CR_LINCALRDYW2_Msk               /*!< ADC Linearity calibration ready Word 2 */

+#define ADC_CR_LINCALRDYW3_Pos            (24U)

+#define ADC_CR_LINCALRDYW3_Msk            (0x1UL << ADC_CR_LINCALRDYW3_Pos)    /*!< 0x01000000 */

+#define ADC_CR_LINCALRDYW3                ADC_CR_LINCALRDYW3_Msk               /*!< ADC Linearity calibration ready Word 3 */

+#define ADC_CR_LINCALRDYW4_Pos            (25U)

+#define ADC_CR_LINCALRDYW4_Msk            (0x1UL << ADC_CR_LINCALRDYW4_Pos)    /*!< 0x02000000 */

+#define ADC_CR_LINCALRDYW4                ADC_CR_LINCALRDYW4_Msk               /*!< ADC Linearity calibration ready Word 4 */

+#define ADC_CR_LINCALRDYW5_Pos            (26U)

+#define ADC_CR_LINCALRDYW5_Msk            (0x1UL << ADC_CR_LINCALRDYW5_Pos)    /*!< 0x04000000 */

+#define ADC_CR_LINCALRDYW5                ADC_CR_LINCALRDYW5_Msk               /*!< ADC Linearity calibration ready Word 5 */

+#define ADC_CR_LINCALRDYW6_Pos            (27U)

+#define ADC_CR_LINCALRDYW6_Msk            (0x1UL << ADC_CR_LINCALRDYW6_Pos)    /*!< 0x08000000 */

+#define ADC_CR_LINCALRDYW6                ADC_CR_LINCALRDYW6_Msk               /*!< ADC Linearity calibration ready Word 6 */

+#define ADC_CR_ADVREGEN_Pos               (28U)

+#define ADC_CR_ADVREGEN_Msk               (0x1UL << ADC_CR_ADVREGEN_Pos)       /*!< 0x10000000 */

+#define ADC_CR_ADVREGEN                   ADC_CR_ADVREGEN_Msk                  /*!< ADC Voltage regulator Enable */

+#define ADC_CR_DEEPPWD_Pos                (29U)

+#define ADC_CR_DEEPPWD_Msk                (0x1UL << ADC_CR_DEEPPWD_Pos)        /*!< 0x20000000 */

+#define ADC_CR_DEEPPWD                    ADC_CR_DEEPPWD_Msk                   /*!< ADC Deep power down Enable */

+#define ADC_CR_ADCALDIF_Pos               (30U)

+#define ADC_CR_ADCALDIF_Msk               (0x1UL << ADC_CR_ADCALDIF_Pos)       /*!< 0x40000000 */

+#define ADC_CR_ADCALDIF                   ADC_CR_ADCALDIF_Msk                  /*!< ADC Differential Mode for calibration */

+#define ADC_CR_ADCAL_Pos                  (31U)

+#define ADC_CR_ADCAL_Msk                  (0x1UL << ADC_CR_ADCAL_Pos)          /*!< 0x80000000 */

+#define ADC_CR_ADCAL                      ADC_CR_ADCAL_Msk                     /*!< ADC Calibration */

+

+/********************  Bit definition for ADC_CFGR register  ********************/

+#define ADC_CFGR_DMNGT_Pos                (0U)

+#define ADC_CFGR_DMNGT_Msk                (0x3UL << ADC_CFGR_DMNGT_Pos)        /*!< 0x00000003 */

+#define ADC_CFGR_DMNGT                    ADC_CFGR_DMNGT_Msk                   /*!< ADC Data Management configuration */

+#define ADC_CFGR_DMNGT_0                  (0x1UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000001 */

+#define ADC_CFGR_DMNGT_1                  (0x2UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000002 */

+

+#define ADC_CFGR_RES_Pos                  (2U)

+#define ADC_CFGR_RES_Msk                  (0x7UL << ADC_CFGR_RES_Pos)          /*!< 0x0000001C */

+#define ADC_CFGR_RES                      ADC_CFGR_RES_Msk                     /*!< ADC Data resolution */

+#define ADC_CFGR_RES_0                    (0x1UL << ADC_CFGR_RES_Pos)           /*!< 0x00000004 */

+#define ADC_CFGR_RES_1                    (0x2UL << ADC_CFGR_RES_Pos)           /*!< 0x00000008 */

+#define ADC_CFGR_RES_2                    (0x4UL << ADC_CFGR_RES_Pos)           /*!< 0x00000010 */

+

+#define ADC_CFGR_EXTSEL_Pos               (5U)

+#define ADC_CFGR_EXTSEL_Msk               (0x1FUL << ADC_CFGR_EXTSEL_Pos)      /*!< 0x000003E0 */

+#define ADC_CFGR_EXTSEL                   ADC_CFGR_EXTSEL_Msk                  /*!< ADC External trigger selection for regular group */

+#define ADC_CFGR_EXTSEL_0                 (0x01UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000020 */

+#define ADC_CFGR_EXTSEL_1                 (0x02UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000040 */

+#define ADC_CFGR_EXTSEL_2                 (0x04UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000080 */

+#define ADC_CFGR_EXTSEL_3                 (0x08UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000100 */

+#define ADC_CFGR_EXTSEL_4                 (0x10UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000200 */

+

+#define ADC_CFGR_EXTEN_Pos                (10U)

+#define ADC_CFGR_EXTEN_Msk                (0x3UL << ADC_CFGR_EXTEN_Pos)        /*!< 0x00000C00 */

+#define ADC_CFGR_EXTEN                    ADC_CFGR_EXTEN_Msk                   /*!< ADC External trigger enable and polarity selection for regular channels */

+#define ADC_CFGR_EXTEN_0                  (0x1UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000400 */

+#define ADC_CFGR_EXTEN_1                  (0x2UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000800 */

+

+#define ADC_CFGR_OVRMOD_Pos               (12U)

+#define ADC_CFGR_OVRMOD_Msk               (0x1UL << ADC_CFGR_OVRMOD_Pos)       /*!< 0x00001000 */

+#define ADC_CFGR_OVRMOD                   ADC_CFGR_OVRMOD_Msk                  /*!< ADC overrun mode */

+#define ADC_CFGR_CONT_Pos                 (13U)

+#define ADC_CFGR_CONT_Msk                 (0x1UL << ADC_CFGR_CONT_Pos)         /*!< 0x00002000 */

+#define ADC_CFGR_CONT                     ADC_CFGR_CONT_Msk                    /*!< ADC Single/continuous conversion mode for regular conversion */

+#define ADC_CFGR_AUTDLY_Pos               (14U)

+#define ADC_CFGR_AUTDLY_Msk               (0x1UL << ADC_CFGR_AUTDLY_Pos)       /*!< 0x00004000 */

+#define ADC_CFGR_AUTDLY                   ADC_CFGR_AUTDLY_Msk                  /*!< ADC Delayed conversion mode */

+

+#define ADC_CFGR_DISCEN_Pos               (16U)

+#define ADC_CFGR_DISCEN_Msk               (0x1UL << ADC_CFGR_DISCEN_Pos)       /*!< 0x00010000 */

+#define ADC_CFGR_DISCEN                   ADC_CFGR_DISCEN_Msk                  /*!< ADC Discontinuous mode for regular channels */

+

+#define ADC_CFGR_DISCNUM_Pos              (17U)

+#define ADC_CFGR_DISCNUM_Msk              (0x7UL << ADC_CFGR_DISCNUM_Pos)      /*!< 0x000E0000 */

+#define ADC_CFGR_DISCNUM                  ADC_CFGR_DISCNUM_Msk                 /*!< ADC Discontinuous mode channel count */

+#define ADC_CFGR_DISCNUM_0                (0x1UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00020000 */

+#define ADC_CFGR_DISCNUM_1                (0x2UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00040000 */

+#define ADC_CFGR_DISCNUM_2                (0x4UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00080000 */

+

+#define ADC_CFGR_JDISCEN_Pos              (20U)

+#define ADC_CFGR_JDISCEN_Msk              (0x1UL << ADC_CFGR_JDISCEN_Pos)      /*!< 0x00100000 */

+#define ADC_CFGR_JDISCEN                  ADC_CFGR_JDISCEN_Msk                 /*!< ADC Discontinuous mode on injected channels */

+#define ADC_CFGR_JQM_Pos                  (21U)

+#define ADC_CFGR_JQM_Msk                  (0x1UL << ADC_CFGR_JQM_Pos)          /*!< 0x00200000 */

+#define ADC_CFGR_JQM                      ADC_CFGR_JQM_Msk                     /*!< ADC JSQR Queue mode */

+#define ADC_CFGR_AWD1SGL_Pos              (22U)

+#define ADC_CFGR_AWD1SGL_Msk              (0x1UL << ADC_CFGR_AWD1SGL_Pos)      /*!< 0x00400000 */

+#define ADC_CFGR_AWD1SGL                  ADC_CFGR_AWD1SGL_Msk                 /*!< Enable the watchdog 1 on a single channel or on all channels */

+#define ADC_CFGR_AWD1EN_Pos               (23U)

+#define ADC_CFGR_AWD1EN_Msk               (0x1UL << ADC_CFGR_AWD1EN_Pos)       /*!< 0x00800000 */

+#define ADC_CFGR_AWD1EN                   ADC_CFGR_AWD1EN_Msk                  /*!< ADC Analog watchdog 1 enable on regular Channels */

+#define ADC_CFGR_JAWD1EN_Pos              (24U)

+#define ADC_CFGR_JAWD1EN_Msk              (0x1UL << ADC_CFGR_JAWD1EN_Pos)      /*!< 0x01000000 */

+#define ADC_CFGR_JAWD1EN                  ADC_CFGR_JAWD1EN_Msk                 /*!< ADC Analog watchdog 1 enable on injected Channels */

+#define ADC_CFGR_JAUTO_Pos                (25U)

+#define ADC_CFGR_JAUTO_Msk                (0x1UL << ADC_CFGR_JAUTO_Pos)        /*!< 0x02000000 */

+#define ADC_CFGR_JAUTO                    ADC_CFGR_JAUTO_Msk                   /*!< ADC Automatic injected group conversion */

+

+#define ADC_CFGR_AWD1CH_Pos               (26U)

+#define ADC_CFGR_AWD1CH_Msk               (0x1FUL << ADC_CFGR_AWD1CH_Pos)      /*!< 0x7C000000 */

+#define ADC_CFGR_AWD1CH                   ADC_CFGR_AWD1CH_Msk                  /*!< ADC Analog watchdog 1 Channel selection */

+#define ADC_CFGR_AWD1CH_0                 (0x01UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x04000000 */

+#define ADC_CFGR_AWD1CH_1                 (0x02UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x08000000 */

+#define ADC_CFGR_AWD1CH_2                 (0x04UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x10000000 */

+#define ADC_CFGR_AWD1CH_3                 (0x08UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x20000000 */

+#define ADC_CFGR_AWD1CH_4                 (0x10UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x40000000 */

+

+#define ADC_CFGR_JQDIS_Pos                (31U)

+#define ADC_CFGR_JQDIS_Msk                (0x1UL << ADC_CFGR_JQDIS_Pos)        /*!< 0x80000000 */

+#define ADC_CFGR_JQDIS                    ADC_CFGR_JQDIS_Msk                   /*!< ADC Injected queue disable */

+

+/********************  Bit definition for ADC_CFGR2 register  ********************/

+#define ADC_CFGR2_ROVSE_Pos               (0U)

+#define ADC_CFGR2_ROVSE_Msk               (0x1UL << ADC_CFGR2_ROVSE_Pos)       /*!< 0x00000001 */

+#define ADC_CFGR2_ROVSE                   ADC_CFGR2_ROVSE_Msk                  /*!< ADC Regular group oversampler enable */

+#define ADC_CFGR2_JOVSE_Pos               (1U)

+#define ADC_CFGR2_JOVSE_Msk               (0x1UL << ADC_CFGR2_JOVSE_Pos)       /*!< 0x00000002 */

+#define ADC_CFGR2_JOVSE                   ADC_CFGR2_JOVSE_Msk                  /*!< ADC Injected group oversampler enable */

+

+#define ADC_CFGR2_OVSS_Pos                (5U)

+#define ADC_CFGR2_OVSS_Msk                (0xFUL << ADC_CFGR2_OVSS_Pos)        /*!< 0x000001E0 */

+#define ADC_CFGR2_OVSS                    ADC_CFGR2_OVSS_Msk                   /*!< ADC Regular Oversampling shift */

+#define ADC_CFGR2_OVSS_0                  (0x1UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000020 */

+#define ADC_CFGR2_OVSS_1                  (0x2UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000040 */

+#define ADC_CFGR2_OVSS_2                  (0x4UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000080 */

+#define ADC_CFGR2_OVSS_3                  (0x8UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000100 */

+

+#define ADC_CFGR2_TROVS_Pos               (9U)

+#define ADC_CFGR2_TROVS_Msk               (0x1UL << ADC_CFGR2_TROVS_Pos)       /*!< 0x00000200 */

+#define ADC_CFGR2_TROVS                   ADC_CFGR2_TROVS_Msk                  /*!< ADC Triggered regular Oversampling */

+#define ADC_CFGR2_ROVSM_Pos               (10U)

+#define ADC_CFGR2_ROVSM_Msk               (0x1UL << ADC_CFGR2_ROVSM_Pos)       /*!< 0x00000400 */

+#define ADC_CFGR2_ROVSM                   ADC_CFGR2_ROVSM_Msk                  /*!< ADC Regular oversampling mode */

+

+#define ADC_CFGR2_RSHIFT1_Pos             (11U)

+#define ADC_CFGR2_RSHIFT1_Msk             (0x1UL << ADC_CFGR2_RSHIFT1_Pos)     /*!< 0x00000800 */

+#define ADC_CFGR2_RSHIFT1                 ADC_CFGR2_RSHIFT1_Msk                /*!< ADC Right-shift data after Offset 1 correction */

+#define ADC_CFGR2_RSHIFT2_Pos             (12U)

+#define ADC_CFGR2_RSHIFT2_Msk             (0x1UL << ADC_CFGR2_RSHIFT2_Pos)     /*!< 0x00001000 */

+#define ADC_CFGR2_RSHIFT2                 ADC_CFGR2_RSHIFT2_Msk                /*!< ADC Right-shift data after Offset 2 correction */

+#define ADC_CFGR2_RSHIFT3_Pos             (13U)

+#define ADC_CFGR2_RSHIFT3_Msk             (0x1UL << ADC_CFGR2_RSHIFT3_Pos)     /*!< 0x00002000 */

+#define ADC_CFGR2_RSHIFT3                 ADC_CFGR2_RSHIFT3_Msk                /*!< ADC Right-shift data after Offset 3 correction */

+#define ADC_CFGR2_RSHIFT4_Pos             (14U)

+#define ADC_CFGR2_RSHIFT4_Msk             (0x1UL << ADC_CFGR2_RSHIFT4_Pos)     /*!< 0x00004000 */

+#define ADC_CFGR2_RSHIFT4                 ADC_CFGR2_RSHIFT4_Msk                /*!< ADC Right-shift data after Offset 4 correction */

+

+#define ADC_CFGR2_OVSR_Pos                (16U)

+#define ADC_CFGR2_OVSR_Msk                (0x3FFUL << ADC_CFGR2_OVSR_Pos)      /*!< 0x03FF0000 */

+#define ADC_CFGR2_OVSR                    ADC_CFGR2_OVSR_Msk                   /*!< ADC oversampling Ratio */

+#define ADC_CFGR2_OVSR_0                  (0x001UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00010000 */

+#define ADC_CFGR2_OVSR_1                  (0x002UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00020000 */

+#define ADC_CFGR2_OVSR_2                  (0x004UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00040000 */

+#define ADC_CFGR2_OVSR_3                  (0x008UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00080000 */

+#define ADC_CFGR2_OVSR_4                  (0x010UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00100000 */

+#define ADC_CFGR2_OVSR_5                  (0x020UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00200000 */

+#define ADC_CFGR2_OVSR_6                  (0x040UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00400000 */

+#define ADC_CFGR2_OVSR_7                  (0x080UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00800000 */

+#define ADC_CFGR2_OVSR_8                  (0x100UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x01000000 */

+#define ADC_CFGR2_OVSR_9                  (0x200UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x02000000 */

+

+#define ADC_CFGR2_LSHIFT_Pos              (28U)

+#define ADC_CFGR2_LSHIFT_Msk              (0xFUL << ADC_CFGR2_LSHIFT_Pos)      /*!< 0xF0000000 */

+#define ADC_CFGR2_LSHIFT                  ADC_CFGR2_LSHIFT_Msk                 /*!< ADC Left shift factor */

+#define ADC_CFGR2_LSHIFT_0                (0x1UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x10000000 */

+#define ADC_CFGR2_LSHIFT_1                (0x2UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x20000000 */

+#define ADC_CFGR2_LSHIFT_2                (0x4UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x40000000 */

+#define ADC_CFGR2_LSHIFT_3                (0x8UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_SMPR1 register  ********************/

+#define ADC_SMPR1_SMP0_Pos                (0U)

+#define ADC_SMPR1_SMP0_Msk                (0x7UL << ADC_SMPR1_SMP0_Pos)        /*!< 0x00000007 */

+#define ADC_SMPR1_SMP0                    ADC_SMPR1_SMP0_Msk                   /*!< ADC Channel 0 Sampling time selection  */

+#define ADC_SMPR1_SMP0_0                  (0x1UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000001 */

+#define ADC_SMPR1_SMP0_1                  (0x2UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000002 */

+#define ADC_SMPR1_SMP0_2                  (0x4UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000004 */

+

+#define ADC_SMPR1_SMP1_Pos                (3U)

+#define ADC_SMPR1_SMP1_Msk                (0x7UL << ADC_SMPR1_SMP1_Pos)        /*!< 0x00000038 */

+#define ADC_SMPR1_SMP1                    ADC_SMPR1_SMP1_Msk                   /*!< ADC Channel 1 Sampling time selection  */

+#define ADC_SMPR1_SMP1_0                  (0x1UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000008 */

+#define ADC_SMPR1_SMP1_1                  (0x2UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000010 */

+#define ADC_SMPR1_SMP1_2                  (0x4UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000020 */

+

+#define ADC_SMPR1_SMP2_Pos                (6U)

+#define ADC_SMPR1_SMP2_Msk                (0x7UL << ADC_SMPR1_SMP2_Pos)        /*!< 0x000001C0 */

+#define ADC_SMPR1_SMP2                    ADC_SMPR1_SMP2_Msk                   /*!< ADC Channel 2 Sampling time selection  */

+#define ADC_SMPR1_SMP2_0                  (0x1UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000040 */

+#define ADC_SMPR1_SMP2_1                  (0x2UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000080 */

+#define ADC_SMPR1_SMP2_2                  (0x4UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000100 */

+

+#define ADC_SMPR1_SMP3_Pos                (9U)

+#define ADC_SMPR1_SMP3_Msk                (0x7UL << ADC_SMPR1_SMP3_Pos)        /*!< 0x00000E00 */

+#define ADC_SMPR1_SMP3                    ADC_SMPR1_SMP3_Msk                   /*!< ADC Channel 3 Sampling time selection  */

+#define ADC_SMPR1_SMP3_0                  (0x1UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000200 */

+#define ADC_SMPR1_SMP3_1                  (0x2UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000400 */

+#define ADC_SMPR1_SMP3_2                  (0x4UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000800 */

+

+#define ADC_SMPR1_SMP4_Pos                (12U)

+#define ADC_SMPR1_SMP4_Msk                (0x7UL << ADC_SMPR1_SMP4_Pos)        /*!< 0x00007000 */

+#define ADC_SMPR1_SMP4                    ADC_SMPR1_SMP4_Msk                   /*!< ADC Channel 4 Sampling time selection  */

+#define ADC_SMPR1_SMP4_0                  (0x1UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00001000 */

+#define ADC_SMPR1_SMP4_1                  (0x2UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00002000 */

+#define ADC_SMPR1_SMP4_2                  (0x4UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00004000 */

+

+#define ADC_SMPR1_SMP5_Pos                (15U)

+#define ADC_SMPR1_SMP5_Msk                (0x7UL << ADC_SMPR1_SMP5_Pos)        /*!< 0x00038000 */

+#define ADC_SMPR1_SMP5                    ADC_SMPR1_SMP5_Msk                   /*!< ADC Channel 5 Sampling time selection  */

+#define ADC_SMPR1_SMP5_0                  (0x1UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00008000 */

+#define ADC_SMPR1_SMP5_1                  (0x2UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00010000 */

+#define ADC_SMPR1_SMP5_2                  (0x4UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00020000 */

+

+#define ADC_SMPR1_SMP6_Pos                (18U)

+#define ADC_SMPR1_SMP6_Msk                (0x7UL << ADC_SMPR1_SMP6_Pos)        /*!< 0x001C0000 */

+#define ADC_SMPR1_SMP6                    ADC_SMPR1_SMP6_Msk                   /*!< ADC Channel 6 Sampling time selection  */

+#define ADC_SMPR1_SMP6_0                  (0x1UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00040000 */

+#define ADC_SMPR1_SMP6_1                  (0x2UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00080000 */

+#define ADC_SMPR1_SMP6_2                  (0x4UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00100000 */

+

+#define ADC_SMPR1_SMP7_Pos                (21U)

+#define ADC_SMPR1_SMP7_Msk                (0x7UL << ADC_SMPR1_SMP7_Pos)        /*!< 0x00E00000 */

+#define ADC_SMPR1_SMP7                    ADC_SMPR1_SMP7_Msk                   /*!< ADC Channel 7 Sampling time selection  */

+#define ADC_SMPR1_SMP7_0                  (0x1UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00200000 */

+#define ADC_SMPR1_SMP7_1                  (0x2UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00400000 */

+#define ADC_SMPR1_SMP7_2                  (0x4UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00800000 */

+

+#define ADC_SMPR1_SMP8_Pos                (24U)

+#define ADC_SMPR1_SMP8_Msk                (0x7UL << ADC_SMPR1_SMP8_Pos)        /*!< 0x07000000 */

+#define ADC_SMPR1_SMP8                    ADC_SMPR1_SMP8_Msk                   /*!< ADC Channel 8 Sampling time selection  */

+#define ADC_SMPR1_SMP8_0                  (0x1UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x01000000 */

+#define ADC_SMPR1_SMP8_1                  (0x2UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x02000000 */

+#define ADC_SMPR1_SMP8_2                  (0x4UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x04000000 */

+

+#define ADC_SMPR1_SMP9_Pos                (27U)

+#define ADC_SMPR1_SMP9_Msk                (0x7UL << ADC_SMPR1_SMP9_Pos)        /*!< 0x38000000 */

+#define ADC_SMPR1_SMP9                    ADC_SMPR1_SMP9_Msk                   /*!< ADC Channel 9 Sampling time selection  */

+#define ADC_SMPR1_SMP9_0                  (0x1UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x08000000 */

+#define ADC_SMPR1_SMP9_1                  (0x2UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x10000000 */

+#define ADC_SMPR1_SMP9_2                  (0x4UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x20000000 */

+

+/********************  Bit definition for ADC_SMPR2 register  ********************/

+#define ADC_SMPR2_SMP10_Pos               (0U)

+#define ADC_SMPR2_SMP10_Msk               (0x7UL << ADC_SMPR2_SMP10_Pos)       /*!< 0x00000007 */

+#define ADC_SMPR2_SMP10                   ADC_SMPR2_SMP10_Msk                  /*!< ADC Channel 10 Sampling time selection  */

+#define ADC_SMPR2_SMP10_0                 (0x1UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000001 */

+#define ADC_SMPR2_SMP10_1                 (0x2UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000002 */

+#define ADC_SMPR2_SMP10_2                 (0x4UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000004 */

+

+#define ADC_SMPR2_SMP11_Pos               (3U)

+#define ADC_SMPR2_SMP11_Msk               (0x7UL << ADC_SMPR2_SMP11_Pos)       /*!< 0x00000038 */

+#define ADC_SMPR2_SMP11                   ADC_SMPR2_SMP11_Msk                  /*!< ADC Channel 11 Sampling time selection  */

+#define ADC_SMPR2_SMP11_0                 (0x1UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000008 */

+#define ADC_SMPR2_SMP11_1                 (0x2UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000010 */

+#define ADC_SMPR2_SMP11_2                 (0x4UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000020 */

+

+#define ADC_SMPR2_SMP12_Pos               (6U)

+#define ADC_SMPR2_SMP12_Msk               (0x7UL << ADC_SMPR2_SMP12_Pos)       /*!< 0x000001C0 */

+#define ADC_SMPR2_SMP12                   ADC_SMPR2_SMP12_Msk                  /*!< ADC Channel 12 Sampling time selection  */

+#define ADC_SMPR2_SMP12_0                 (0x1UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000040 */

+#define ADC_SMPR2_SMP12_1                 (0x2UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000080 */

+#define ADC_SMPR2_SMP12_2                 (0x4UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000100 */

+

+#define ADC_SMPR2_SMP13_Pos               (9U)

+#define ADC_SMPR2_SMP13_Msk               (0x7UL << ADC_SMPR2_SMP13_Pos)       /*!< 0x00000E00 */

+#define ADC_SMPR2_SMP13                   ADC_SMPR2_SMP13_Msk                  /*!< ADC Channel 13 Sampling time selection  */

+#define ADC_SMPR2_SMP13_0                 (0x1UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000200 */

+#define ADC_SMPR2_SMP13_1                 (0x2UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000400 */

+#define ADC_SMPR2_SMP13_2                 (0x4UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000800 */

+

+#define ADC_SMPR2_SMP14_Pos               (12U)

+#define ADC_SMPR2_SMP14_Msk               (0x7UL << ADC_SMPR2_SMP14_Pos)       /*!< 0x00007000 */

+#define ADC_SMPR2_SMP14                   ADC_SMPR2_SMP14_Msk                  /*!< ADC Channel 14 Sampling time selection  */

+#define ADC_SMPR2_SMP14_0                 (0x1UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00001000 */

+#define ADC_SMPR2_SMP14_1                 (0x2UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00002000 */

+#define ADC_SMPR2_SMP14_2                 (0x4UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00004000 */

+

+#define ADC_SMPR2_SMP15_Pos               (15U)

+#define ADC_SMPR2_SMP15_Msk               (0x7UL << ADC_SMPR2_SMP15_Pos)       /*!< 0x00038000 */

+#define ADC_SMPR2_SMP15                   ADC_SMPR2_SMP15_Msk                  /*!< ADC Channel 15 Sampling time selection  */

+#define ADC_SMPR2_SMP15_0                 (0x1UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00008000 */

+#define ADC_SMPR2_SMP15_1                 (0x2UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00010000 */

+#define ADC_SMPR2_SMP15_2                 (0x4UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00020000 */

+

+#define ADC_SMPR2_SMP16_Pos               (18U)

+#define ADC_SMPR2_SMP16_Msk               (0x7UL << ADC_SMPR2_SMP16_Pos)       /*!< 0x001C0000 */

+#define ADC_SMPR2_SMP16                   ADC_SMPR2_SMP16_Msk                  /*!< ADC Channel 16 Sampling time selection  */

+#define ADC_SMPR2_SMP16_0                 (0x1UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00040000 */

+#define ADC_SMPR2_SMP16_1                 (0x2UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00080000 */

+#define ADC_SMPR2_SMP16_2                 (0x4UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00100000 */

+

+#define ADC_SMPR2_SMP17_Pos               (21U)

+#define ADC_SMPR2_SMP17_Msk               (0x7UL << ADC_SMPR2_SMP17_Pos)       /*!< 0x00E00000 */

+#define ADC_SMPR2_SMP17                   ADC_SMPR2_SMP17_Msk                  /*!< ADC Channel 17 Sampling time selection  */

+#define ADC_SMPR2_SMP17_0                 (0x1UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00200000 */

+#define ADC_SMPR2_SMP17_1                 (0x2UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00400000 */

+#define ADC_SMPR2_SMP17_2                 (0x4UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00800000 */

+

+#define ADC_SMPR2_SMP18_Pos               (24U)

+#define ADC_SMPR2_SMP18_Msk               (0x7UL << ADC_SMPR2_SMP18_Pos)       /*!< 0x07000000 */

+#define ADC_SMPR2_SMP18                   ADC_SMPR2_SMP18_Msk                  /*!< ADC Channel 18 Sampling time selection  */

+#define ADC_SMPR2_SMP18_0                 (0x1UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x01000000 */

+#define ADC_SMPR2_SMP18_1                 (0x2UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x02000000 */

+#define ADC_SMPR2_SMP18_2                 (0x4UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x04000000 */

+

+#define ADC_SMPR2_SMP19_Pos               (27U)

+#define ADC_SMPR2_SMP19_Msk               (0x7UL << ADC_SMPR2_SMP19_Pos)       /*!< 0x38000000 */

+#define ADC_SMPR2_SMP19                   ADC_SMPR2_SMP19_Msk                  /*!< ADC Channel 19 Sampling time selection  */

+#define ADC_SMPR2_SMP19_0                 (0x1UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x08000000 */

+#define ADC_SMPR2_SMP19_1                 (0x2UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x10000000 */

+#define ADC_SMPR2_SMP19_2                 (0x4UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x20000000 */

+

+/********************  Bit definition for ADC_PCSEL register  ********************/

+#define ADC_PCSEL_PCSEL_Pos               (0U)

+#define ADC_PCSEL_PCSEL_Msk               (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)   /*!< 0x000FFFFF */

+#define ADC_PCSEL_PCSEL                   ADC_PCSEL_PCSEL_Msk                  /*!< ADC pre channel selection */

+#define ADC_PCSEL_PCSEL_0                 (0x00001UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */

+#define ADC_PCSEL_PCSEL_1                 (0x00002UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */

+#define ADC_PCSEL_PCSEL_2                 (0x00004UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */

+#define ADC_PCSEL_PCSEL_3                 (0x00008UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */

+#define ADC_PCSEL_PCSEL_4                 (0x00010UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */

+#define ADC_PCSEL_PCSEL_5                 (0x00020UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */

+#define ADC_PCSEL_PCSEL_6                 (0x00040UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */

+#define ADC_PCSEL_PCSEL_7                 (0x00080UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */

+#define ADC_PCSEL_PCSEL_8                 (0x00100UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */

+#define ADC_PCSEL_PCSEL_9                 (0x00200UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */

+#define ADC_PCSEL_PCSEL_10                (0x00400UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */

+#define ADC_PCSEL_PCSEL_11                (0x00800UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */

+#define ADC_PCSEL_PCSEL_12                (0x01000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */

+#define ADC_PCSEL_PCSEL_13                (0x02000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */

+#define ADC_PCSEL_PCSEL_14                (0x04000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */

+#define ADC_PCSEL_PCSEL_15                (0x08000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */

+#define ADC_PCSEL_PCSEL_16                (0x10000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */

+#define ADC_PCSEL_PCSEL_17                (0x20000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */

+#define ADC_PCSEL_PCSEL_18                (0x40000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */

+#define ADC_PCSEL_PCSEL_19                (0x80000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00080000 */

+

+/*****************  Bit definition for ADC_LTR1, 2, 3 registers *****************/

+#define ADC_LTR_LT_Pos                    (0U)

+#define ADC_LTR_LT_Msk                    (0x3FFFFFFUL << ADC_LTR_LT_Pos)      /*!< 0x03FFFFFF */

+#define ADC_LTR_LT                        ADC_LTR_LT_Msk                       /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */

+

+/*****************  Bit definition for ADC_HTR1, 2, 3 registers  ****************/

+#define ADC_HTR_HT_Pos                    (0U)

+#define ADC_HTR_HT_Msk                    (0x3FFFFFFUL << ADC_HTR_HT_Pos)      /*!< 0x03FFFFFF */

+#define ADC_HTR_HT                        ADC_HTR_HT_Msk                       /*!< ADC Analog watchdog 1,2 and 3 higher threshold */

+

+

+/********************  Bit definition for ADC_SQR1 register  ********************/

+#define ADC_SQR1_L_Pos                    (0U)

+#define ADC_SQR1_L_Msk                    (0xFUL << ADC_SQR1_L_Pos)            /*!< 0x0000000F */

+#define ADC_SQR1_L                        ADC_SQR1_L_Msk                       /*!< ADC regular channel sequence lenght */

+#define ADC_SQR1_L_0                      (0x1UL << ADC_SQR1_L_Pos)             /*!< 0x00000001 */

+#define ADC_SQR1_L_1                      (0x2UL << ADC_SQR1_L_Pos)             /*!< 0x00000002 */

+#define ADC_SQR1_L_2                      (0x4UL << ADC_SQR1_L_Pos)             /*!< 0x00000004 */

+#define ADC_SQR1_L_3                      (0x8UL << ADC_SQR1_L_Pos)             /*!< 0x00000008 */

+

+#define ADC_SQR1_SQ1_Pos                  (6U)

+#define ADC_SQR1_SQ1_Msk                  (0x1FUL << ADC_SQR1_SQ1_Pos)         /*!< 0x000007C0 */

+#define ADC_SQR1_SQ1                      ADC_SQR1_SQ1_Msk                     /*!< ADC 1st conversion in regular sequence */

+#define ADC_SQR1_SQ1_0                    (0x01UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000040 */

+#define ADC_SQR1_SQ1_1                    (0x02UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000080 */

+#define ADC_SQR1_SQ1_2                    (0x04UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000100 */

+#define ADC_SQR1_SQ1_3                    (0x08UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000200 */

+#define ADC_SQR1_SQ1_4                    (0x10UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000400 */

+

+#define ADC_SQR1_SQ2_Pos                  (12U)

+#define ADC_SQR1_SQ2_Msk                  (0x1FUL << ADC_SQR1_SQ2_Pos)         /*!< 0x0001F000 */

+#define ADC_SQR1_SQ2                      ADC_SQR1_SQ2_Msk                     /*!< ADC 2nd conversion in regular sequence */

+#define ADC_SQR1_SQ2_0                    (0x01UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00001000 */

+#define ADC_SQR1_SQ2_1                    (0x02UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00002000 */

+#define ADC_SQR1_SQ2_2                    (0x04UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00004000 */

+#define ADC_SQR1_SQ2_3                    (0x08UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00008000 */

+#define ADC_SQR1_SQ2_4                    (0x10UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00010000 */

+

+#define ADC_SQR1_SQ3_Pos                  (18U)

+#define ADC_SQR1_SQ3_Msk                  (0x1FUL << ADC_SQR1_SQ3_Pos)         /*!< 0x007C0000 */

+#define ADC_SQR1_SQ3                      ADC_SQR1_SQ3_Msk                     /*!< ADC 3rd conversion in regular sequence */

+#define ADC_SQR1_SQ3_0                    (0x01UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00040000 */

+#define ADC_SQR1_SQ3_1                    (0x02UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00080000 */

+#define ADC_SQR1_SQ3_2                    (0x04UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00100000 */

+#define ADC_SQR1_SQ3_3                    (0x08UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00200000 */

+#define ADC_SQR1_SQ3_4                    (0x10UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00400000 */

+

+#define ADC_SQR1_SQ4_Pos                  (24U)

+#define ADC_SQR1_SQ4_Msk                  (0x1FUL << ADC_SQR1_SQ4_Pos)         /*!< 0x1F000000 */

+#define ADC_SQR1_SQ4                      ADC_SQR1_SQ4_Msk                     /*!< ADC 4th conversion in regular sequence */

+#define ADC_SQR1_SQ4_0                    (0x01UL << ADC_SQR1_SQ4_Pos)          /*!< 0x01000000 */

+#define ADC_SQR1_SQ4_1                    (0x02UL << ADC_SQR1_SQ4_Pos)          /*!< 0x02000000 */

+#define ADC_SQR1_SQ4_2                    (0x04UL << ADC_SQR1_SQ4_Pos)          /*!< 0x04000000 */

+#define ADC_SQR1_SQ4_3                    (0x08UL << ADC_SQR1_SQ4_Pos)          /*!< 0x08000000 */

+#define ADC_SQR1_SQ4_4                    (0x10UL << ADC_SQR1_SQ4_Pos)          /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR2 register  ********************/

+#define ADC_SQR2_SQ5_Pos                  (0U)

+#define ADC_SQR2_SQ5_Msk                  (0x1FUL << ADC_SQR2_SQ5_Pos)         /*!< 0x0000001F */

+#define ADC_SQR2_SQ5                      ADC_SQR2_SQ5_Msk                     /*!< ADC 5th conversion in regular sequence */

+#define ADC_SQR2_SQ5_0                    (0x01UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000001 */

+#define ADC_SQR2_SQ5_1                    (0x02UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000002 */

+#define ADC_SQR2_SQ5_2                    (0x04UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000004 */

+#define ADC_SQR2_SQ5_3                    (0x08UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000008 */

+#define ADC_SQR2_SQ5_4                    (0x10UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000010 */

+

+#define ADC_SQR2_SQ6_Pos                  (6U)

+#define ADC_SQR2_SQ6_Msk                  (0x1FUL << ADC_SQR2_SQ6_Pos)         /*!< 0x000007C0 */

+#define ADC_SQR2_SQ6                      ADC_SQR2_SQ6_Msk                     /*!< ADC 6th conversion in regular sequence */

+#define ADC_SQR2_SQ6_0                    (0x01UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000040 */

+#define ADC_SQR2_SQ6_1                    (0x02UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000080 */

+#define ADC_SQR2_SQ6_2                    (0x04UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000100 */

+#define ADC_SQR2_SQ6_3                    (0x08UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000200 */

+#define ADC_SQR2_SQ6_4                    (0x10UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000400 */

+

+#define ADC_SQR2_SQ7_Pos                  (12U)

+#define ADC_SQR2_SQ7_Msk                  (0x1FUL << ADC_SQR2_SQ7_Pos)         /*!< 0x0001F000 */

+#define ADC_SQR2_SQ7                      ADC_SQR2_SQ7_Msk                     /*!< ADC 7th conversion in regular sequence */

+#define ADC_SQR2_SQ7_0                    (0x01UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00001000 */

+#define ADC_SQR2_SQ7_1                    (0x02UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00002000 */

+#define ADC_SQR2_SQ7_2                    (0x04UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00004000 */

+#define ADC_SQR2_SQ7_3                    (0x08UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00008000 */

+#define ADC_SQR2_SQ7_4                    (0x10UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00010000 */

+

+#define ADC_SQR2_SQ8_Pos                  (18U)

+#define ADC_SQR2_SQ8_Msk                  (0x1FUL << ADC_SQR2_SQ8_Pos)         /*!< 0x007C0000 */

+#define ADC_SQR2_SQ8                      ADC_SQR2_SQ8_Msk                     /*!< ADC 8th conversion in regular sequence */

+#define ADC_SQR2_SQ8_0                    (0x01UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00040000 */

+#define ADC_SQR2_SQ8_1                    (0x02UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00080000 */

+#define ADC_SQR2_SQ8_2                    (0x04UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00100000 */

+#define ADC_SQR2_SQ8_3                    (0x08UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00200000 */

+#define ADC_SQR2_SQ8_4                    (0x10UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00400000 */

+

+#define ADC_SQR2_SQ9_Pos                  (24U)

+#define ADC_SQR2_SQ9_Msk                  (0x1FUL << ADC_SQR2_SQ9_Pos)         /*!< 0x1F000000 */

+#define ADC_SQR2_SQ9                      ADC_SQR2_SQ9_Msk                     /*!< ADC 9th conversion in regular sequence */

+#define ADC_SQR2_SQ9_0                    (0x01UL << ADC_SQR2_SQ9_Pos)          /*!< 0x01000000 */

+#define ADC_SQR2_SQ9_1                    (0x02UL << ADC_SQR2_SQ9_Pos)          /*!< 0x02000000 */

+#define ADC_SQR2_SQ9_2                    (0x04UL << ADC_SQR2_SQ9_Pos)          /*!< 0x04000000 */

+#define ADC_SQR2_SQ9_3                    (0x08UL << ADC_SQR2_SQ9_Pos)          /*!< 0x08000000 */

+#define ADC_SQR2_SQ9_4                    (0x10UL << ADC_SQR2_SQ9_Pos)          /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR3 register  ********************/

+#define ADC_SQR3_SQ10_Pos                 (0U)

+#define ADC_SQR3_SQ10_Msk                 (0x1FUL << ADC_SQR3_SQ10_Pos)        /*!< 0x0000001F */

+#define ADC_SQR3_SQ10                     ADC_SQR3_SQ10_Msk                    /*!< ADC 10th conversion in regular sequence */

+#define ADC_SQR3_SQ10_0                   (0x01UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000001 */

+#define ADC_SQR3_SQ10_1                   (0x02UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000002 */

+#define ADC_SQR3_SQ10_2                   (0x04UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000004 */

+#define ADC_SQR3_SQ10_3                   (0x08UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000008 */

+#define ADC_SQR3_SQ10_4                   (0x10UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000010 */

+

+#define ADC_SQR3_SQ11_Pos                 (6U)

+#define ADC_SQR3_SQ11_Msk                 (0x1FUL << ADC_SQR3_SQ11_Pos)        /*!< 0x000007C0 */

+#define ADC_SQR3_SQ11                     ADC_SQR3_SQ11_Msk                    /*!< ADC 11th conversion in regular sequence */

+#define ADC_SQR3_SQ11_0                   (0x01UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000040 */

+#define ADC_SQR3_SQ11_1                   (0x02UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000080 */

+#define ADC_SQR3_SQ11_2                   (0x04UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000100 */

+#define ADC_SQR3_SQ11_3                   (0x08UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000200 */

+#define ADC_SQR3_SQ11_4                   (0x10UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000400 */

+

+#define ADC_SQR3_SQ12_Pos                 (12U)

+#define ADC_SQR3_SQ12_Msk                 (0x1FUL << ADC_SQR3_SQ12_Pos)        /*!< 0x0001F000 */

+#define ADC_SQR3_SQ12                     ADC_SQR3_SQ12_Msk                    /*!< ADC 12th conversion in regular sequence */

+#define ADC_SQR3_SQ12_0                   (0x01UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00001000 */

+#define ADC_SQR3_SQ12_1                   (0x02UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00002000 */

+#define ADC_SQR3_SQ12_2                   (0x04UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00004000 */

+#define ADC_SQR3_SQ12_3                   (0x08UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00008000 */

+#define ADC_SQR3_SQ12_4                   (0x10UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00010000 */

+

+#define ADC_SQR3_SQ13_Pos                 (18U)

+#define ADC_SQR3_SQ13_Msk                 (0x1FUL << ADC_SQR3_SQ13_Pos)        /*!< 0x007C0000 */

+#define ADC_SQR3_SQ13                     ADC_SQR3_SQ13_Msk                    /*!< ADC 13th conversion in regular sequence */

+#define ADC_SQR3_SQ13_0                   (0x01UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00040000 */

+#define ADC_SQR3_SQ13_1                   (0x02UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00080000 */

+#define ADC_SQR3_SQ13_2                   (0x04UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00100000 */

+#define ADC_SQR3_SQ13_3                   (0x08UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00200000 */

+#define ADC_SQR3_SQ13_4                   (0x10UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00400000 */

+

+#define ADC_SQR3_SQ14_Pos                 (24U)

+#define ADC_SQR3_SQ14_Msk                 (0x1FUL << ADC_SQR3_SQ14_Pos)        /*!< 0x1F000000 */

+#define ADC_SQR3_SQ14                     ADC_SQR3_SQ14_Msk                    /*!< ADC 14th conversion in regular sequence */

+#define ADC_SQR3_SQ14_0                   (0x01UL << ADC_SQR3_SQ14_Pos)         /*!< 0x01000000 */

+#define ADC_SQR3_SQ14_1                   (0x02UL << ADC_SQR3_SQ14_Pos)         /*!< 0x02000000 */

+#define ADC_SQR3_SQ14_2                   (0x04UL << ADC_SQR3_SQ14_Pos)         /*!< 0x04000000 */

+#define ADC_SQR3_SQ14_3                   (0x08UL << ADC_SQR3_SQ14_Pos)         /*!< 0x08000000 */

+#define ADC_SQR3_SQ14_4                   (0x10UL << ADC_SQR3_SQ14_Pos)         /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR4 register  ********************/

+#define ADC_SQR4_SQ15_Pos                 (0U)

+#define ADC_SQR4_SQ15_Msk                 (0x1FUL << ADC_SQR4_SQ15_Pos)        /*!< 0x0000001F */

+#define ADC_SQR4_SQ15                     ADC_SQR4_SQ15_Msk                    /*!< ADC 15th conversion in regular sequence */

+#define ADC_SQR4_SQ15_0                   (0x01UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000001 */

+#define ADC_SQR4_SQ15_1                   (0x02UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000002 */

+#define ADC_SQR4_SQ15_2                   (0x04UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000004 */

+#define ADC_SQR4_SQ15_3                   (0x08UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000008 */

+#define ADC_SQR4_SQ15_4                   (0x10UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000010 */

+

+#define ADC_SQR4_SQ16_Pos                 (6U)

+#define ADC_SQR4_SQ16_Msk                 (0x1FUL << ADC_SQR4_SQ16_Pos)        /*!< 0x000007C0 */

+#define ADC_SQR4_SQ16                     ADC_SQR4_SQ16_Msk                    /*!< ADC 16th conversion in regular sequence */

+#define ADC_SQR4_SQ16_0                   (0x01UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000040 */

+#define ADC_SQR4_SQ16_1                   (0x02UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000080 */

+#define ADC_SQR4_SQ16_2                   (0x04UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000100 */

+#define ADC_SQR4_SQ16_3                   (0x08UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000200 */

+#define ADC_SQR4_SQ16_4                   (0x10UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000400 */

+/********************  Bit definition for ADC_DR register  ********************/

+#define ADC_DR_RDATA_Pos                  (0U)

+#define ADC_DR_RDATA_Msk                  (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)   /*!< 0xFFFFFFFF */

+#define ADC_DR_RDATA                      ADC_DR_RDATA_Msk                     /*!< ADC regular Data converted */

+

+/********************  Bit definition for ADC_JSQR register  ********************/

+#define ADC_JSQR_JL_Pos                   (0U)

+#define ADC_JSQR_JL_Msk                   (0x3UL << ADC_JSQR_JL_Pos)           /*!< 0x00000003 */

+#define ADC_JSQR_JL                       ADC_JSQR_JL_Msk                      /*!< ADC injected channel sequence length */

+#define ADC_JSQR_JL_0                     (0x1UL << ADC_JSQR_JL_Pos)           /*!< 0x00000001 */

+#define ADC_JSQR_JL_1                     (0x2UL << ADC_JSQR_JL_Pos)           /*!< 0x00000002 */

+

+#define ADC_JSQR_JEXTSEL_Pos              (2U)

+#define ADC_JSQR_JEXTSEL_Msk              (0x1FUL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x0000007C */

+#define ADC_JSQR_JEXTSEL                  ADC_JSQR_JEXTSEL_Msk                 /*!< ADC external trigger selection for injected group */

+#define ADC_JSQR_JEXTSEL_0                (0x01UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000004 */

+#define ADC_JSQR_JEXTSEL_1                (0x02UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000008 */

+#define ADC_JSQR_JEXTSEL_2                (0x04UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000010 */

+#define ADC_JSQR_JEXTSEL_3                (0x08UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000020 */

+#define ADC_JSQR_JEXTSEL_4                (0x10UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000040 */

+

+#define ADC_JSQR_JEXTEN_Pos               (7U)

+#define ADC_JSQR_JEXTEN_Msk               (0x3UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000180 */

+#define ADC_JSQR_JEXTEN                   ADC_JSQR_JEXTEN_Msk                  /*!< ADC external trigger enable and polarity selection for injected channels */

+#define ADC_JSQR_JEXTEN_0                 (0x1UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000080 */

+#define ADC_JSQR_JEXTEN_1                 (0x2UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000100 */

+

+#define ADC_JSQR_JSQ1_Pos                 (9U)

+#define ADC_JSQR_JSQ1_Msk                 (0x1FUL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00003E00 */

+#define ADC_JSQR_JSQ1                     ADC_JSQR_JSQ1_Msk                    /*!< ADC 1st conversion in injected sequence */

+#define ADC_JSQR_JSQ1_0                   (0x01UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000200 */

+#define ADC_JSQR_JSQ1_1                   (0x02UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000400 */

+#define ADC_JSQR_JSQ1_2                   (0x04UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000800 */

+#define ADC_JSQR_JSQ1_3                   (0x08UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00001000 */

+#define ADC_JSQR_JSQ1_4                   (0x10UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00002000 */

+

+#define ADC_JSQR_JSQ2_Pos                 (15U)

+#define ADC_JSQR_JSQ2_Msk                 (0x1FUL << ADC_JSQR_JSQ2_Pos)        /*!< 0x000F8000 */

+#define ADC_JSQR_JSQ2                     ADC_JSQR_JSQ2_Msk                    /*!< ADC 2nd conversion in injected sequence */

+#define ADC_JSQR_JSQ2_0                   (0x01UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00008000 */

+#define ADC_JSQR_JSQ2_1                   (0x02UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00010000 */

+#define ADC_JSQR_JSQ2_2                   (0x04UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00020000 */

+#define ADC_JSQR_JSQ2_3                   (0x08UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00040000 */

+#define ADC_JSQR_JSQ2_4                   (0x10UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00080000 */

+

+#define ADC_JSQR_JSQ3_Pos                 (21U)

+#define ADC_JSQR_JSQ3_Msk                 (0x1FUL << ADC_JSQR_JSQ3_Pos)        /*!< 0x03E00000 */

+#define ADC_JSQR_JSQ3                     ADC_JSQR_JSQ3_Msk                    /*!< ADC 3rd conversion in injected sequence */

+#define ADC_JSQR_JSQ3_0                   (0x01UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00200000 */

+#define ADC_JSQR_JSQ3_1                   (0x02UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00400000 */

+#define ADC_JSQR_JSQ3_2                   (0x04UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00800000 */

+#define ADC_JSQR_JSQ3_3                   (0x08UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x01000000 */

+#define ADC_JSQR_JSQ3_4                   (0x10UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x02000000 */

+

+#define ADC_JSQR_JSQ4_Pos                 (27U)

+#define ADC_JSQR_JSQ4_Msk                 (0x1FUL << ADC_JSQR_JSQ4_Pos)        /*!< 0xF8000000 */

+#define ADC_JSQR_JSQ4                     ADC_JSQR_JSQ4_Msk                    /*!< ADC 4th conversion in injected sequence */

+#define ADC_JSQR_JSQ4_0                   (0x01UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x08000000 */

+#define ADC_JSQR_JSQ4_1                   (0x02UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x10000000 */

+#define ADC_JSQR_JSQ4_2                   (0x04UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x20000000 */

+#define ADC_JSQR_JSQ4_3                   (0x08UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x40000000 */

+#define ADC_JSQR_JSQ4_4                   (0x10UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_OFR1 register  ********************/

+#define ADC_OFR1_OFFSET1_Pos              (0U)

+#define ADC_OFR1_OFFSET1_Msk              (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR1_OFFSET1                  ADC_OFR1_OFFSET1_Msk                  /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */

+#define ADC_OFR1_OFFSET1_0                (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */

+#define ADC_OFR1_OFFSET1_1                (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */

+#define ADC_OFR1_OFFSET1_2                (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */

+#define ADC_OFR1_OFFSET1_3                (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */

+#define ADC_OFR1_OFFSET1_4                (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */

+#define ADC_OFR1_OFFSET1_5                (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */

+#define ADC_OFR1_OFFSET1_6                (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */

+#define ADC_OFR1_OFFSET1_7                (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */

+#define ADC_OFR1_OFFSET1_8                (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */

+#define ADC_OFR1_OFFSET1_9                (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */

+#define ADC_OFR1_OFFSET1_10               (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */

+#define ADC_OFR1_OFFSET1_11               (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */

+#define ADC_OFR1_OFFSET1_12               (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */

+#define ADC_OFR1_OFFSET1_13               (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */

+#define ADC_OFR1_OFFSET1_14               (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */

+#define ADC_OFR1_OFFSET1_15               (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */

+#define ADC_OFR1_OFFSET1_16               (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */

+#define ADC_OFR1_OFFSET1_17               (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */

+#define ADC_OFR1_OFFSET1_18               (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */

+#define ADC_OFR1_OFFSET1_19               (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */

+#define ADC_OFR1_OFFSET1_20               (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */

+#define ADC_OFR1_OFFSET1_21               (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */

+#define ADC_OFR1_OFFSET1_22               (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */

+#define ADC_OFR1_OFFSET1_23               (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */

+#define ADC_OFR1_OFFSET1_24               (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */

+#define ADC_OFR1_OFFSET1_25               (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR1_OFFSET1_CH_Pos           (26U)

+#define ADC_OFR1_OFFSET1_CH_Msk           (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR1_OFFSET1_CH               ADC_OFR1_OFFSET1_CH_Msk               /*!< ADC Channel selection for the data offset 1 */

+#define ADC_OFR1_OFFSET1_CH_0             (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR1_OFFSET1_CH_1             (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR1_OFFSET1_CH_2             (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR1_OFFSET1_CH_3             (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR1_OFFSET1_CH_4             (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR1_SSATE_Pos                (31U)

+#define ADC_OFR1_SSATE_Msk                (0x1UL << ADC_OFR1_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR1_SSATE                    ADC_OFR1_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR2 register  ********************/

+#define ADC_OFR2_OFFSET2_Pos              (0U)

+#define ADC_OFR2_OFFSET2_Msk              (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR2_OFFSET2                  ADC_OFR2_OFFSET2_Msk                  /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */

+#define ADC_OFR2_OFFSET2_0                (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */

+#define ADC_OFR2_OFFSET2_1                (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */

+#define ADC_OFR2_OFFSET2_2                (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */

+#define ADC_OFR2_OFFSET2_3                (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */

+#define ADC_OFR2_OFFSET2_4                (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */

+#define ADC_OFR2_OFFSET2_5                (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */

+#define ADC_OFR2_OFFSET2_6                (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */

+#define ADC_OFR2_OFFSET2_7                (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */

+#define ADC_OFR2_OFFSET2_8                (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */

+#define ADC_OFR2_OFFSET2_9                (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */

+#define ADC_OFR2_OFFSET2_10               (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */

+#define ADC_OFR2_OFFSET2_11               (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */

+#define ADC_OFR2_OFFSET2_12               (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */

+#define ADC_OFR2_OFFSET2_13               (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */

+#define ADC_OFR2_OFFSET2_14               (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */

+#define ADC_OFR2_OFFSET2_15               (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */

+#define ADC_OFR2_OFFSET2_16               (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */

+#define ADC_OFR2_OFFSET2_17               (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */

+#define ADC_OFR2_OFFSET2_18               (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */

+#define ADC_OFR2_OFFSET2_19               (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */

+#define ADC_OFR2_OFFSET2_20               (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */

+#define ADC_OFR2_OFFSET2_21               (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */

+#define ADC_OFR2_OFFSET2_22               (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */

+#define ADC_OFR2_OFFSET2_23               (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */

+#define ADC_OFR2_OFFSET2_24               (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */

+#define ADC_OFR2_OFFSET2_25               (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR2_OFFSET2_CH_Pos           (26U)

+#define ADC_OFR2_OFFSET2_CH_Msk           (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR2_OFFSET2_CH               ADC_OFR2_OFFSET2_CH_Msk               /*!< ADC Channel selection for the data offset 2 */

+#define ADC_OFR2_OFFSET2_CH_0             (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR2_OFFSET2_CH_1             (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR2_OFFSET2_CH_2             (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR2_OFFSET2_CH_3             (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR2_OFFSET2_CH_4             (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR2_SSATE_Pos                (31U)

+#define ADC_OFR2_SSATE_Msk                (0x1UL << ADC_OFR2_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR2_SSATE                    ADC_OFR2_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR3 register  ********************/

+#define ADC_OFR3_OFFSET3_Pos              (0U)

+#define ADC_OFR3_OFFSET3_Msk              (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR3_OFFSET3                  ADC_OFR3_OFFSET3_Msk                  /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */

+#define ADC_OFR3_OFFSET3_0                (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */

+#define ADC_OFR3_OFFSET3_1                (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */

+#define ADC_OFR3_OFFSET3_2                (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */

+#define ADC_OFR3_OFFSET3_3                (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */

+#define ADC_OFR3_OFFSET3_4                (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */

+#define ADC_OFR3_OFFSET3_5                (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */

+#define ADC_OFR3_OFFSET3_6                (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */

+#define ADC_OFR3_OFFSET3_7                (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */

+#define ADC_OFR3_OFFSET3_8                (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */

+#define ADC_OFR3_OFFSET3_9                (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */

+#define ADC_OFR3_OFFSET3_10               (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */

+#define ADC_OFR3_OFFSET3_11               (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */

+#define ADC_OFR3_OFFSET3_12               (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */

+#define ADC_OFR3_OFFSET3_13               (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */

+#define ADC_OFR3_OFFSET3_14               (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */

+#define ADC_OFR3_OFFSET3_15               (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */

+#define ADC_OFR3_OFFSET3_16               (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */

+#define ADC_OFR3_OFFSET3_17               (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */

+#define ADC_OFR3_OFFSET3_18               (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */

+#define ADC_OFR3_OFFSET3_19               (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */

+#define ADC_OFR3_OFFSET3_20               (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */

+#define ADC_OFR3_OFFSET3_21               (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */

+#define ADC_OFR3_OFFSET3_22               (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */

+#define ADC_OFR3_OFFSET3_23               (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */

+#define ADC_OFR3_OFFSET3_24               (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */

+#define ADC_OFR3_OFFSET3_25               (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR3_OFFSET3_CH_Pos           (26U)

+#define ADC_OFR3_OFFSET3_CH_Msk           (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR3_OFFSET3_CH               ADC_OFR3_OFFSET3_CH_Msk               /*!< ADC Channel selection for the data offset 3 */

+#define ADC_OFR3_OFFSET3_CH_0             (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR3_OFFSET3_CH_1             (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR3_OFFSET3_CH_2             (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR3_OFFSET3_CH_3             (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR3_OFFSET3_CH_4             (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR3_SSATE_Pos                (31U)

+#define ADC_OFR3_SSATE_Msk                (0x1UL << ADC_OFR3_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR3_SSATE                    ADC_OFR3_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR4 register  ********************/

+#define ADC_OFR4_OFFSET4_Pos              (0U)

+#define ADC_OFR4_OFFSET4_Msk              (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR4_OFFSET4                  ADC_OFR4_OFFSET4_Msk                  /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */

+#define ADC_OFR4_OFFSET4_0                (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */

+#define ADC_OFR4_OFFSET4_1                (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */

+#define ADC_OFR4_OFFSET4_2                (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */

+#define ADC_OFR4_OFFSET4_3                (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */

+#define ADC_OFR4_OFFSET4_4                (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */

+#define ADC_OFR4_OFFSET4_5                (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */

+#define ADC_OFR4_OFFSET4_6                (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */

+#define ADC_OFR4_OFFSET4_7                (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */

+#define ADC_OFR4_OFFSET4_8                (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */

+#define ADC_OFR4_OFFSET4_9                (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */

+#define ADC_OFR4_OFFSET4_10               (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */

+#define ADC_OFR4_OFFSET4_11               (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */

+#define ADC_OFR4_OFFSET4_12               (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */

+#define ADC_OFR4_OFFSET4_13               (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */

+#define ADC_OFR4_OFFSET4_14               (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */

+#define ADC_OFR4_OFFSET4_15               (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */

+#define ADC_OFR4_OFFSET4_16               (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */

+#define ADC_OFR4_OFFSET4_17               (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */

+#define ADC_OFR4_OFFSET4_18               (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */

+#define ADC_OFR4_OFFSET4_19               (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */

+#define ADC_OFR4_OFFSET4_20               (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */

+#define ADC_OFR4_OFFSET4_21               (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */

+#define ADC_OFR4_OFFSET4_22               (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */

+#define ADC_OFR4_OFFSET4_23               (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */

+#define ADC_OFR4_OFFSET4_24               (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */

+#define ADC_OFR4_OFFSET4_25               (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR4_OFFSET4_CH_Pos           (26U)

+#define ADC_OFR4_OFFSET4_CH_Msk           (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR4_OFFSET4_CH               ADC_OFR4_OFFSET4_CH_Msk               /*!< ADC Channel selection for the data offset 4 */

+#define ADC_OFR4_OFFSET4_CH_0             (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR4_OFFSET4_CH_1             (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR4_OFFSET4_CH_2             (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR4_OFFSET4_CH_3             (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR4_OFFSET4_CH_4             (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR4_SSATE_Pos                (31U)

+#define ADC_OFR4_SSATE_Msk                (0x1UL << ADC_OFR4_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR4_SSATE                    ADC_OFR4_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_JDR1 register  ********************/

+#define ADC_JDR1_JDATA_Pos                (0U)

+#define ADC_JDR1_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR1_JDATA                    ADC_JDR1_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR1_JDATA_0                  (0x00000001UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR1_JDATA_1                  (0x00000002UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR1_JDATA_2                  (0x00000004UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR1_JDATA_3                  (0x00000008UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR1_JDATA_4                  (0x00000010UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR1_JDATA_5                  (0x00000020UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR1_JDATA_6                  (0x00000040UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR1_JDATA_7                  (0x00000080UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR1_JDATA_8                  (0x00000100UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR1_JDATA_9                  (0x00000200UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR1_JDATA_10                 (0x00000400UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR1_JDATA_11                 (0x00000800UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR1_JDATA_12                 (0x00001000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR1_JDATA_13                 (0x00002000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR1_JDATA_14                 (0x00004000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR1_JDATA_15                 (0x00008000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR1_JDATA_16                 (0x00010000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR1_JDATA_17                 (0x00020000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR1_JDATA_18                 (0x00040000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR1_JDATA_19                 (0x00080000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR1_JDATA_20                 (0x00100000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR1_JDATA_21                 (0x00200000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR1_JDATA_22                 (0x00400000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR1_JDATA_23                 (0x00800000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR1_JDATA_24                 (0x01000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR1_JDATA_25                 (0x02000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR1_JDATA_26                 (0x04000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR1_JDATA_27                 (0x08000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR1_JDATA_28                 (0x10000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR1_JDATA_29                 (0x20000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR1_JDATA_30                 (0x40000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR1_JDATA_31                 (0x80000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR2 register  ********************/

+#define ADC_JDR2_JDATA_Pos                (0U)

+#define ADC_JDR2_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR2_JDATA                    ADC_JDR2_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR2_JDATA_0                  (0x00000001UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR2_JDATA_1                  (0x00000002UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR2_JDATA_2                  (0x00000004UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR2_JDATA_3                  (0x00000008UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR2_JDATA_4                  (0x00000010UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR2_JDATA_5                  (0x00000020UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR2_JDATA_6                  (0x00000040UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR2_JDATA_7                  (0x00000080UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR2_JDATA_8                  (0x00000100UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR2_JDATA_9                  (0x00000200UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR2_JDATA_10                 (0x00000400UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR2_JDATA_11                 (0x00000800UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR2_JDATA_12                 (0x00001000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR2_JDATA_13                 (0x00002000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR2_JDATA_14                 (0x00004000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR2_JDATA_15                 (0x00008000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR2_JDATA_16                 (0x00010000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR2_JDATA_17                 (0x00020000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR2_JDATA_18                 (0x00040000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR2_JDATA_19                 (0x00080000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR2_JDATA_20                 (0x00100000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR2_JDATA_21                 (0x00200000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR2_JDATA_22                 (0x00400000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR2_JDATA_23                 (0x00800000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR2_JDATA_24                 (0x01000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR2_JDATA_25                 (0x02000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR2_JDATA_26                 (0x04000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR2_JDATA_27                 (0x08000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR2_JDATA_28                 (0x10000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR2_JDATA_29                 (0x20000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR2_JDATA_30                 (0x40000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR2_JDATA_31                 (0x80000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR3 register  ********************/

+#define ADC_JDR3_JDATA_Pos                (0U)

+#define ADC_JDR3_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR3_JDATA                    ADC_JDR3_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR3_JDATA_0                  (0x00000001UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR3_JDATA_1                  (0x00000002UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR3_JDATA_2                  (0x00000004UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR3_JDATA_3                  (0x00000008UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR3_JDATA_4                  (0x00000010UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR3_JDATA_5                  (0x00000020UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR3_JDATA_6                  (0x00000040UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR3_JDATA_7                  (0x00000080UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR3_JDATA_8                  (0x00000100UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR3_JDATA_9                  (0x00000200UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR3_JDATA_10                 (0x00000400UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR3_JDATA_11                 (0x00000800UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR3_JDATA_12                 (0x00001000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR3_JDATA_13                 (0x00002000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR3_JDATA_14                 (0x00004000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR3_JDATA_15                 (0x00008000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR3_JDATA_16                 (0x00010000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR3_JDATA_17                 (0x00020000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR3_JDATA_18                 (0x00040000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR3_JDATA_19                 (0x00080000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR3_JDATA_20                 (0x00100000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR3_JDATA_21                 (0x00200000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR3_JDATA_22                 (0x00400000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR3_JDATA_23                 (0x00800000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR3_JDATA_24                 (0x01000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR3_JDATA_25                 (0x02000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR3_JDATA_26                 (0x04000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR3_JDATA_27                 (0x08000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR3_JDATA_28                 (0x10000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR3_JDATA_29                 (0x20000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR3_JDATA_30                 (0x40000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR3_JDATA_31                 (0x80000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR4 register  ********************/

+#define ADC_JDR4_JDATA_Pos                (0U)

+#define ADC_JDR4_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR4_JDATA                    ADC_JDR4_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR4_JDATA_0                  (0x00000001UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR4_JDATA_1                  (0x00000002UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR4_JDATA_2                  (0x00000004UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR4_JDATA_3                  (0x00000008UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR4_JDATA_4                  (0x00000010UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR4_JDATA_5                  (0x00000020UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR4_JDATA_6                  (0x00000040UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR4_JDATA_7                  (0x00000080UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR4_JDATA_8                  (0x00000100UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR4_JDATA_9                  (0x00000200UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR4_JDATA_10                 (0x00000400UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR4_JDATA_11                 (0x00000800UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR4_JDATA_12                 (0x00001000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR4_JDATA_13                 (0x00002000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR4_JDATA_14                 (0x00004000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR4_JDATA_15                 (0x00008000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR4_JDATA_16                 (0x00010000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR4_JDATA_17                 (0x00020000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR4_JDATA_18                 (0x00040000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR4_JDATA_19                 (0x00080000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR4_JDATA_20                 (0x00100000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR4_JDATA_21                 (0x00200000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR4_JDATA_22                 (0x00400000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR4_JDATA_23                 (0x00800000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR4_JDATA_24                 (0x01000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR4_JDATA_25                 (0x02000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR4_JDATA_26                 (0x04000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR4_JDATA_27                 (0x08000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR4_JDATA_28                 (0x10000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR4_JDATA_29                 (0x20000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR4_JDATA_30                 (0x40000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR4_JDATA_31                 (0x80000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_AWD2CR register  ********************/

+#define ADC_AWD2CR_AWD2CH_Pos             (0U)

+#define ADC_AWD2CR_AWD2CH_Msk             (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x000FFFFF */

+#define ADC_AWD2CR_AWD2CH                 ADC_AWD2CR_AWD2CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */

+#define ADC_AWD2CR_AWD2CH_0               (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000001 */

+#define ADC_AWD2CR_AWD2CH_1               (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000002 */

+#define ADC_AWD2CR_AWD2CH_2               (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000004 */

+#define ADC_AWD2CR_AWD2CH_3               (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000008 */

+#define ADC_AWD2CR_AWD2CH_4               (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000010 */

+#define ADC_AWD2CR_AWD2CH_5               (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000020 */

+#define ADC_AWD2CR_AWD2CH_6               (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000040 */

+#define ADC_AWD2CR_AWD2CH_7               (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000080 */

+#define ADC_AWD2CR_AWD2CH_8               (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000100 */

+#define ADC_AWD2CR_AWD2CH_9               (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000200 */

+#define ADC_AWD2CR_AWD2CH_10              (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000400 */

+#define ADC_AWD2CR_AWD2CH_11              (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000800 */

+#define ADC_AWD2CR_AWD2CH_12              (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00001000 */

+#define ADC_AWD2CR_AWD2CH_13              (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00002000 */

+#define ADC_AWD2CR_AWD2CH_14              (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00004000 */

+#define ADC_AWD2CR_AWD2CH_15              (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00008000 */

+#define ADC_AWD2CR_AWD2CH_16              (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00010000 */

+#define ADC_AWD2CR_AWD2CH_17              (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00020000 */

+#define ADC_AWD2CR_AWD2CH_18              (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */

+#define ADC_AWD2CR_AWD2CH_19              (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_AWD3CR register  ********************/

+#define ADC_AWD3CR_AWD3CH_Pos             (0U)

+#define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x000FFFFF */

+#define ADC_AWD3CR_AWD3CH                 ADC_AWD3CR_AWD3CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */

+#define ADC_AWD3CR_AWD3CH_0               (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000001 */

+#define ADC_AWD3CR_AWD3CH_1               (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000002 */

+#define ADC_AWD3CR_AWD3CH_2               (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000004 */

+#define ADC_AWD3CR_AWD3CH_3               (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000008 */

+#define ADC_AWD3CR_AWD3CH_4               (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000010 */

+#define ADC_AWD3CR_AWD3CH_5               (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000020 */

+#define ADC_AWD3CR_AWD3CH_6               (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000040 */

+#define ADC_AWD3CR_AWD3CH_7               (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000080 */

+#define ADC_AWD3CR_AWD3CH_8               (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000100 */

+#define ADC_AWD3CR_AWD3CH_9               (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000200 */

+#define ADC_AWD3CR_AWD3CH_10              (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000400 */

+#define ADC_AWD3CR_AWD3CH_11              (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000800 */

+#define ADC_AWD3CR_AWD3CH_12              (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00001000 */

+#define ADC_AWD3CR_AWD3CH_13              (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00002000 */

+#define ADC_AWD3CR_AWD3CH_14              (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00004000 */

+#define ADC_AWD3CR_AWD3CH_15              (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00008000 */

+#define ADC_AWD3CR_AWD3CH_16              (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00010000 */

+#define ADC_AWD3CR_AWD3CH_17              (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00020000 */

+#define ADC_AWD3CR_AWD3CH_18              (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */

+#define ADC_AWD3CR_AWD3CH_19              (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_DIFSEL register  ********************/

+#define ADC_DIFSEL_DIFSEL_Pos             (0U)

+#define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */

+#define ADC_DIFSEL_DIFSEL                 ADC_DIFSEL_DIFSEL_Msk                 /*!< ADC differential modes for channels 1 to 18 */

+#define ADC_DIFSEL_DIFSEL_0               (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000001 */

+#define ADC_DIFSEL_DIFSEL_1               (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000002 */

+#define ADC_DIFSEL_DIFSEL_2               (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000004 */

+#define ADC_DIFSEL_DIFSEL_3               (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000008 */

+#define ADC_DIFSEL_DIFSEL_4               (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000010 */

+#define ADC_DIFSEL_DIFSEL_5               (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000020 */

+#define ADC_DIFSEL_DIFSEL_6               (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000040 */

+#define ADC_DIFSEL_DIFSEL_7               (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000080 */

+#define ADC_DIFSEL_DIFSEL_8               (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000100 */

+#define ADC_DIFSEL_DIFSEL_9               (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000200 */

+#define ADC_DIFSEL_DIFSEL_10              (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000400 */

+#define ADC_DIFSEL_DIFSEL_11              (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000800 */

+#define ADC_DIFSEL_DIFSEL_12              (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00001000 */

+#define ADC_DIFSEL_DIFSEL_13              (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00002000 */

+#define ADC_DIFSEL_DIFSEL_14              (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00004000 */

+#define ADC_DIFSEL_DIFSEL_15              (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00008000 */

+#define ADC_DIFSEL_DIFSEL_16              (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00010000 */

+#define ADC_DIFSEL_DIFSEL_17              (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00020000 */

+#define ADC_DIFSEL_DIFSEL_18              (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00040000 */

+#define ADC_DIFSEL_DIFSEL_19              (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_CALFACT register  ********************/

+#define ADC_CALFACT_CALFACT_S_Pos         (0U)

+#define ADC_CALFACT_CALFACT_S_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */

+#define ADC_CALFACT_CALFACT_S             ADC_CALFACT_CALFACT_S_Msk              /*!< ADC calibration factors in single-ended mode */

+#define ADC_CALFACT_CALFACT_S_0           (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */

+#define ADC_CALFACT_CALFACT_S_1           (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */

+#define ADC_CALFACT_CALFACT_S_2           (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */

+#define ADC_CALFACT_CALFACT_S_3           (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */

+#define ADC_CALFACT_CALFACT_S_4           (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */

+#define ADC_CALFACT_CALFACT_S_5           (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */

+#define ADC_CALFACT_CALFACT_S_6           (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */

+#define ADC_CALFACT_CALFACT_S_7           (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */

+#define ADC_CALFACT_CALFACT_S_8           (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */

+#define ADC_CALFACT_CALFACT_S_9           (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */

+#define ADC_CALFACT_CALFACT_S_10          (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */

+#define ADC_CALFACT_CALFACT_D_Pos         (16U)

+#define ADC_CALFACT_CALFACT_D_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */

+#define ADC_CALFACT_CALFACT_D             ADC_CALFACT_CALFACT_D_Msk              /*!< ADC calibration factors in differential mode */

+#define ADC_CALFACT_CALFACT_D_0           (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */

+#define ADC_CALFACT_CALFACT_D_1           (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */

+#define ADC_CALFACT_CALFACT_D_2           (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */

+#define ADC_CALFACT_CALFACT_D_3           (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */

+#define ADC_CALFACT_CALFACT_D_4           (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */

+#define ADC_CALFACT_CALFACT_D_5           (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */

+#define ADC_CALFACT_CALFACT_D_6           (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */

+#define ADC_CALFACT_CALFACT_D_7           (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */

+#define ADC_CALFACT_CALFACT_D_8           (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */

+#define ADC_CALFACT_CALFACT_D_9           (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */

+#define ADC_CALFACT_CALFACT_D_10          (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */

+

+/********************  Bit definition for ADC_CALFACT2 register  ********************/

+#define ADC_CALFACT2_LINCALFACT_Pos       (0U)

+#define ADC_CALFACT2_LINCALFACT_Msk       (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */

+#define ADC_CALFACT2_LINCALFACT           ADC_CALFACT2_LINCALFACT_Msk                   /*!< ADC Linearity calibration factors */

+#define ADC_CALFACT2_LINCALFACT_0         (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */

+#define ADC_CALFACT2_LINCALFACT_1         (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */

+#define ADC_CALFACT2_LINCALFACT_2         (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */

+#define ADC_CALFACT2_LINCALFACT_3         (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */

+#define ADC_CALFACT2_LINCALFACT_4         (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */

+#define ADC_CALFACT2_LINCALFACT_5         (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */

+#define ADC_CALFACT2_LINCALFACT_6         (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */

+#define ADC_CALFACT2_LINCALFACT_7         (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */

+#define ADC_CALFACT2_LINCALFACT_8         (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */

+#define ADC_CALFACT2_LINCALFACT_9         (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */

+#define ADC_CALFACT2_LINCALFACT_10        (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */

+#define ADC_CALFACT2_LINCALFACT_11        (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */

+#define ADC_CALFACT2_LINCALFACT_12        (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */

+#define ADC_CALFACT2_LINCALFACT_13        (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */

+#define ADC_CALFACT2_LINCALFACT_14        (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */

+#define ADC_CALFACT2_LINCALFACT_15        (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */

+#define ADC_CALFACT2_LINCALFACT_16        (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */

+#define ADC_CALFACT2_LINCALFACT_17        (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */

+#define ADC_CALFACT2_LINCALFACT_18        (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */

+#define ADC_CALFACT2_LINCALFACT_19        (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */

+#define ADC_CALFACT2_LINCALFACT_20        (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */

+#define ADC_CALFACT2_LINCALFACT_21        (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */

+#define ADC_CALFACT2_LINCALFACT_22        (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */

+#define ADC_CALFACT2_LINCALFACT_23        (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */

+#define ADC_CALFACT2_LINCALFACT_24        (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */

+#define ADC_CALFACT2_LINCALFACT_25        (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */

+#define ADC_CALFACT2_LINCALFACT_26        (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */

+#define ADC_CALFACT2_LINCALFACT_27        (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */

+#define ADC_CALFACT2_LINCALFACT_28        (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */

+#define ADC_CALFACT2_LINCALFACT_29        (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */

+

+/*************************  ADC Common registers  *****************************/

+/********************  Bit definition for ADC_CSR register  ********************/

+#define ADC_CSR_ADRDY_MST_Pos             (0U)

+#define ADC_CSR_ADRDY_MST_Msk             (0x1UL << ADC_CSR_ADRDY_MST_Pos)     /*!< 0x00000001 */

+#define ADC_CSR_ADRDY_MST                 ADC_CSR_ADRDY_MST_Msk                /*!< Master ADC ready */

+#define ADC_CSR_EOSMP_MST_Pos             (1U)

+#define ADC_CSR_EOSMP_MST_Msk             (0x1UL << ADC_CSR_EOSMP_MST_Pos)     /*!< 0x00000002 */

+#define ADC_CSR_EOSMP_MST                 ADC_CSR_EOSMP_MST_Msk                /*!< End of sampling phase flag of the master ADC */

+#define ADC_CSR_EOC_MST_Pos               (2U)

+#define ADC_CSR_EOC_MST_Msk               (0x1UL << ADC_CSR_EOC_MST_Pos)       /*!< 0x00000004 */

+#define ADC_CSR_EOC_MST                   ADC_CSR_EOC_MST_Msk                  /*!< End of regular conversion of the master ADC */

+#define ADC_CSR_EOS_MST_Pos               (3U)

+#define ADC_CSR_EOS_MST_Msk               (0x1UL << ADC_CSR_EOS_MST_Pos)       /*!< 0x00000008 */

+#define ADC_CSR_EOS_MST                   ADC_CSR_EOS_MST_Msk                  /*!< End of regular sequence flag of the master ADC */

+#define ADC_CSR_OVR_MST_Pos               (4U)

+#define ADC_CSR_OVR_MST_Msk               (0x1UL << ADC_CSR_OVR_MST_Pos)       /*!< 0x00000010 */

+#define ADC_CSR_OVR_MST                   ADC_CSR_OVR_MST_Msk                  /*!< Overrun flag of the master ADC */

+#define ADC_CSR_JEOC_MST_Pos              (5U)

+#define ADC_CSR_JEOC_MST_Msk              (0x1UL << ADC_CSR_JEOC_MST_Pos)      /*!< 0x00000020 */

+#define ADC_CSR_JEOC_MST                  ADC_CSR_JEOC_MST_Msk                 /*!< End of injected conversion of the master ADC */

+#define ADC_CSR_JEOS_MST_Pos              (6U)

+#define ADC_CSR_JEOS_MST_Msk              (0x1UL << ADC_CSR_JEOS_MST_Pos)      /*!< 0x00000040 */

+#define ADC_CSR_JEOS_MST                  ADC_CSR_JEOS_MST_Msk                 /*!< End of injected sequence flag of the master ADC */

+#define ADC_CSR_AWD1_MST_Pos              (7U)

+#define ADC_CSR_AWD1_MST_Msk              (0x1UL << ADC_CSR_AWD1_MST_Pos)      /*!< 0x00000080 */

+#define ADC_CSR_AWD1_MST                  ADC_CSR_AWD1_MST_Msk                 /*!< Analog watchdog 1 flag of the master ADC */

+#define ADC_CSR_AWD2_MST_Pos              (8U)

+#define ADC_CSR_AWD2_MST_Msk              (0x1UL << ADC_CSR_AWD2_MST_Pos)      /*!< 0x00000100 */

+#define ADC_CSR_AWD2_MST                  ADC_CSR_AWD2_MST_Msk                 /*!< Analog watchdog 2 flag of the master ADC */

+#define ADC_CSR_AWD3_MST_Pos              (9U)

+#define ADC_CSR_AWD3_MST_Msk              (0x1UL << ADC_CSR_AWD3_MST_Pos)      /*!< 0x00000200 */

+#define ADC_CSR_AWD3_MST                  ADC_CSR_AWD3_MST_Msk                 /*!< Analog watchdog 3 flag of the master ADC */

+#define ADC_CSR_JQOVF_MST_Pos             (10U)

+#define ADC_CSR_JQOVF_MST_Msk             (0x1UL << ADC_CSR_JQOVF_MST_Pos)     /*!< 0x00000400 */

+#define ADC_CSR_JQOVF_MST                 ADC_CSR_JQOVF_MST_Msk                /*!< Injected context queue overflow flag of the master ADC */

+#define ADC_CSR_ADRDY_SLV_Pos             (16U)

+#define ADC_CSR_ADRDY_SLV_Msk             (0x1UL << ADC_CSR_ADRDY_SLV_Pos)     /*!< 0x00010000 */

+#define ADC_CSR_ADRDY_SLV                 ADC_CSR_ADRDY_SLV_Msk                /*!< Slave ADC ready */

+#define ADC_CSR_EOSMP_SLV_Pos             (17U)

+#define ADC_CSR_EOSMP_SLV_Msk             (0x1UL << ADC_CSR_EOSMP_SLV_Pos)     /*!< 0x00020000 */

+#define ADC_CSR_EOSMP_SLV                 ADC_CSR_EOSMP_SLV_Msk                /*!< End of sampling phase flag of the slave ADC */

+#define ADC_CSR_EOC_SLV_Pos               (18U)

+#define ADC_CSR_EOC_SLV_Msk               (0x1UL << ADC_CSR_EOC_SLV_Pos)       /*!< 0x00040000 */

+#define ADC_CSR_EOC_SLV                   ADC_CSR_EOC_SLV_Msk                  /*!< End of regular conversion of the slave ADC */

+#define ADC_CSR_EOS_SLV_Pos               (19U)

+#define ADC_CSR_EOS_SLV_Msk               (0x1UL << ADC_CSR_EOS_SLV_Pos)       /*!< 0x00080000 */

+#define ADC_CSR_EOS_SLV                   ADC_CSR_EOS_SLV_Msk                  /*!< End of regular sequence flag of the slave ADC */

+#define ADC_CSR_OVR_SLV_Pos               (20U)

+#define ADC_CSR_OVR_SLV_Msk               (0x1UL << ADC_CSR_OVR_SLV_Pos)       /*!< 0x00100000 */

+#define ADC_CSR_OVR_SLV                   ADC_CSR_OVR_SLV_Msk                  /*!< Overrun flag of the slave ADC */

+#define ADC_CSR_JEOC_SLV_Pos              (21U)

+#define ADC_CSR_JEOC_SLV_Msk              (0x1UL << ADC_CSR_JEOC_SLV_Pos)      /*!< 0x00200000 */

+#define ADC_CSR_JEOC_SLV                  ADC_CSR_JEOC_SLV_Msk                 /*!< End of injected conversion of the slave ADC */

+#define ADC_CSR_JEOS_SLV_Pos              (22U)

+#define ADC_CSR_JEOS_SLV_Msk              (0x1UL << ADC_CSR_JEOS_SLV_Pos)      /*!< 0x00400000 */

+#define ADC_CSR_JEOS_SLV                  ADC_CSR_JEOS_SLV_Msk                 /*!< End of injected sequence flag of the slave ADC */

+#define ADC_CSR_AWD1_SLV_Pos              (23U)

+#define ADC_CSR_AWD1_SLV_Msk              (0x1UL << ADC_CSR_AWD1_SLV_Pos)      /*!< 0x00800000 */

+#define ADC_CSR_AWD1_SLV                  ADC_CSR_AWD1_SLV_Msk                 /*!< Analog watchdog 1 flag of the slave ADC */

+#define ADC_CSR_AWD2_SLV_Pos              (24U)

+#define ADC_CSR_AWD2_SLV_Msk              (0x1UL << ADC_CSR_AWD2_SLV_Pos)      /*!< 0x01000000 */

+#define ADC_CSR_AWD2_SLV                  ADC_CSR_AWD2_SLV_Msk                 /*!< Analog watchdog 2 flag of the slave ADC */

+#define ADC_CSR_AWD3_SLV_Pos              (25U)

+#define ADC_CSR_AWD3_SLV_Msk              (0x1UL << ADC_CSR_AWD3_SLV_Pos)      /*!< 0x02000000 */

+#define ADC_CSR_AWD3_SLV                  ADC_CSR_AWD3_SLV_Msk                 /*!< Analog watchdog 3 flag of the slave ADC */

+#define ADC_CSR_JQOVF_SLV_Pos             (26U)

+#define ADC_CSR_JQOVF_SLV_Msk             (0x1UL << ADC_CSR_JQOVF_SLV_Pos)     /*!< 0x04000000 */

+#define ADC_CSR_JQOVF_SLV                 ADC_CSR_JQOVF_SLV_Msk                /*!< Injected context queue overflow flag of the slave ADC */

+

+/********************  Bit definition for ADC_CCR register  ********************/

+#define ADC_CCR_DUAL_Pos                  (0U)

+#define ADC_CCR_DUAL_Msk                  (0x1FUL << ADC_CCR_DUAL_Pos)          /*!< 0x0000001F */

+#define ADC_CCR_DUAL                      ADC_CCR_DUAL_Msk                      /*!< Dual ADC mode selection */

+#define ADC_CCR_DUAL_0                    (0x01UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000001 */

+#define ADC_CCR_DUAL_1                    (0x02UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000002 */

+#define ADC_CCR_DUAL_2                    (0x04UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000004 */

+#define ADC_CCR_DUAL_3                    (0x08UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000008 */

+#define ADC_CCR_DUAL_4                    (0x10UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000010 */

+

+#define ADC_CCR_DELAY_Pos                 (8U)

+#define ADC_CCR_DELAY_Msk                 (0xFUL << ADC_CCR_DELAY_Pos)          /*!< 0x00000F00 */

+#define ADC_CCR_DELAY                     ADC_CCR_DELAY_Msk                     /*!< Delay between 2 sampling phases */

+#define ADC_CCR_DELAY_0                   (0x1UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000100 */

+#define ADC_CCR_DELAY_1                   (0x2UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000200 */

+#define ADC_CCR_DELAY_2                   (0x4UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000400 */

+#define ADC_CCR_DELAY_3                   (0x8UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000800 */

+

+

+#define ADC_CCR_DAMDF_Pos                 (14U)

+#define ADC_CCR_DAMDF_Msk                 (0x3UL << ADC_CCR_DAMDF_Pos)          /*!< 0x0000C000 */

+#define ADC_CCR_DAMDF                     ADC_CCR_DAMDF_Msk                     /*!< Dual ADC mode Data format */

+#define ADC_CCR_DAMDF_0                   (0x1UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00004000 */

+#define ADC_CCR_DAMDF_1                   (0x2UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00008000 */

+

+#define ADC_CCR_CKMODE_Pos                (16U)

+#define ADC_CCR_CKMODE_Msk                (0x3UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00030000 */

+#define ADC_CCR_CKMODE                    ADC_CCR_CKMODE_Msk                    /*!< ADC clock mode */

+#define ADC_CCR_CKMODE_0                  (0x1UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00010000 */

+#define ADC_CCR_CKMODE_1                  (0x2UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00020000 */

+

+#define ADC_CCR_PRESC_Pos                 (18U)

+#define ADC_CCR_PRESC_Msk                 (0xFUL << ADC_CCR_PRESC_Pos)          /*!< 0x003C0000 */

+#define ADC_CCR_PRESC                     ADC_CCR_PRESC_Msk                     /*!< ADC prescaler */

+#define ADC_CCR_PRESC_0                   (0x1UL << ADC_CCR_PRESC_Pos)          /*!< 0x00040000 */

+#define ADC_CCR_PRESC_1                   (0x2UL << ADC_CCR_PRESC_Pos)          /*!< 0x00080000 */

+#define ADC_CCR_PRESC_2                   (0x4UL << ADC_CCR_PRESC_Pos)          /*!< 0x00100000 */

+#define ADC_CCR_PRESC_3                   (0x8UL << ADC_CCR_PRESC_Pos)          /*!< 0x00200000 */

+

+#define ADC_CCR_VREFEN_Pos                (22U)

+#define ADC_CCR_VREFEN_Msk                (0x1UL << ADC_CCR_VREFEN_Pos)         /*!< 0x00400000 */

+#define ADC_CCR_VREFEN                    ADC_CCR_VREFEN_Msk                    /*!< VREFINT enable */

+#define ADC_CCR_TSEN_Pos                  (23U)

+#define ADC_CCR_TSEN_Msk                  (0x1UL << ADC_CCR_TSEN_Pos)           /*!< 0x00800000 */

+#define ADC_CCR_TSEN                      ADC_CCR_TSEN_Msk                      /*!< Temperature sensor enable */

+#define ADC_CCR_VBATEN_Pos                (24U)

+#define ADC_CCR_VBATEN_Msk                (0x1UL << ADC_CCR_VBATEN_Pos)         /*!< 0x01000000 */

+#define ADC_CCR_VBATEN                    ADC_CCR_VBATEN_Msk                    /*!< VBAT enable */

+

+/********************  Bit definition for ADC_CDR register  *******************/

+#define ADC_CDR_RDATA_MST_Pos             (0U)

+#define ADC_CDR_RDATA_MST_Msk             (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)   /*!< 0x0000FFFF */

+#define ADC_CDR_RDATA_MST                 ADC_CDR_RDATA_MST_Msk                 /*!< ADC multimode master group regular conversion data */

+

+#define ADC_CDR_RDATA_SLV_Pos             (16U)

+#define ADC_CDR_RDATA_SLV_Msk             (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)   /*!< 0xFFFF0000 */

+#define ADC_CDR_RDATA_SLV                 ADC_CDR_RDATA_SLV_Msk                 /*!< ADC multimode slave group regular conversion data */

+

+/********************  Bit definition for ADC_CDR2 register  ******************/

+#define ADC_CDR2_RDATA_ALT_Pos            (0U)

+#define ADC_CDR2_RDATA_ALT_Msk            (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */

+#define ADC_CDR2_RDATA_ALT                ADC_CDR2_RDATA_ALT_Msk                   /*!< Regular data of the master/slave alternated ADCs */

+

+/******************************************************************************/

+/*                                                                            */

+/*                        ART accelerator                                     */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for ART_CTR register  ********************/

+#define ART_CTR_EN_Pos              (0U)

+#define ART_CTR_EN_Msk              (0x1UL << ART_CTR_EN_Pos)                /*!< 0x00000001 */

+#define ART_CTR_EN                  ART_CTR_EN_Msk                           /*!< Cache enable*/

+

+#define ART_CTR_PCACHEADDR_Pos      (8U)

+#define ART_CTR_PCACHEADDR_Msk      (0xFFFUL << ART_CTR_PCACHEADDR_Pos)      /*!< 0x000FFF00 */

+#define ART_CTR_PCACHEADDR          ART_CTR_PCACHEADDR_Msk                   /*!< Cacheable page index */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                   VREFBUF                                  */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for VREFBUF_CSR register  ****************/

+#define VREFBUF_CSR_ENVR_Pos        (0U)

+#define VREFBUF_CSR_ENVR_Msk        (0x1UL << VREFBUF_CSR_ENVR_Pos)            /*!< 0x00000001 */

+#define VREFBUF_CSR_ENVR            VREFBUF_CSR_ENVR_Msk                       /*!<Voltage reference buffer enable */

+#define VREFBUF_CSR_HIZ_Pos         (1U)

+#define VREFBUF_CSR_HIZ_Msk         (0x1UL << VREFBUF_CSR_HIZ_Pos)             /*!< 0x00000002 */

+#define VREFBUF_CSR_HIZ             VREFBUF_CSR_HIZ_Msk                        /*!<High impedance mode             */

+#define VREFBUF_CSR_VRR_Pos         (3U)

+#define VREFBUF_CSR_VRR_Msk         (0x1UL << VREFBUF_CSR_VRR_Pos)             /*!< 0x00000008 */

+#define VREFBUF_CSR_VRR             VREFBUF_CSR_VRR_Msk                        /*!<Voltage reference buffer ready  */

+#define VREFBUF_CSR_VRS_Pos         (4U)

+#define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */

+#define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */

+

+#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */

+#define VREFBUF_CSR_VRS_OUT2_Pos    (4U)

+#define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */

+#define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */

+#define VREFBUF_CSR_VRS_OUT3_Pos    (5U)

+#define VREFBUF_CSR_VRS_OUT3_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)        /*!< 0x00000020 */

+#define VREFBUF_CSR_VRS_OUT3        VREFBUF_CSR_VRS_OUT3_Msk                   /*!<Voltage reference VREF_OUT3     */

+#define VREFBUF_CSR_VRS_OUT4_Pos    (4U)

+#define VREFBUF_CSR_VRS_OUT4_Msk    (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)        /*!< 0x00000030 */

+#define VREFBUF_CSR_VRS_OUT4        VREFBUF_CSR_VRS_OUT4_Msk                   /*!<Voltage reference VREF_OUT4     */

+

+/*******************  Bit definition for VREFBUF_CCR register  ****************/

+#define VREFBUF_CCR_TRIM_Pos        (0U)

+#define VREFBUF_CCR_TRIM_Msk        (0x3FUL << VREFBUF_CCR_TRIM_Pos)           /*!< 0x0000003F */

+#define VREFBUF_CCR_TRIM            VREFBUF_CCR_TRIM_Msk                       /*!<TRIM[5:0] bits (Trimming code)  */

+

+/******************************************************************************/

+/*                                                                            */

+/*                 Flexible Datarate Controller Area Network                  */

+/*                                                                            */

+/******************************************************************************/

+/*!<FDCAN control and status registers */

+/*****************  Bit definition for FDCAN_CREL register  *******************/

+#define FDCAN_CREL_DAY_Pos        (0U)

+#define FDCAN_CREL_DAY_Msk        (0xFFUL << FDCAN_CREL_DAY_Pos)               /*!< 0x000000FF */

+#define FDCAN_CREL_DAY            FDCAN_CREL_DAY_Msk                           /*!<Timestamp Day                           */

+#define FDCAN_CREL_MON_Pos        (8U)

+#define FDCAN_CREL_MON_Msk        (0xFFUL << FDCAN_CREL_MON_Pos)               /*!< 0x0000FF00 */

+#define FDCAN_CREL_MON            FDCAN_CREL_MON_Msk                           /*!<Timestamp Month                         */

+#define FDCAN_CREL_YEAR_Pos       (16U)

+#define FDCAN_CREL_YEAR_Msk       (0xFUL << FDCAN_CREL_YEAR_Pos)               /*!< 0x000F0000 */

+#define FDCAN_CREL_YEAR           FDCAN_CREL_YEAR_Msk                          /*!<Timestamp Year                          */

+#define FDCAN_CREL_SUBSTEP_Pos    (20U)

+#define FDCAN_CREL_SUBSTEP_Msk    (0xFUL << FDCAN_CREL_SUBSTEP_Pos)            /*!< 0x00F00000 */

+#define FDCAN_CREL_SUBSTEP        FDCAN_CREL_SUBSTEP_Msk                       /*!<Sub-step of Core release                */

+#define FDCAN_CREL_STEP_Pos       (24U)

+#define FDCAN_CREL_STEP_Msk       (0xFUL << FDCAN_CREL_STEP_Pos)               /*!< 0x0F000000 */

+#define FDCAN_CREL_STEP           FDCAN_CREL_STEP_Msk                          /*!<Step of Core release                    */

+#define FDCAN_CREL_REL_Pos        (28U)

+#define FDCAN_CREL_REL_Msk        (0xFUL << FDCAN_CREL_REL_Pos)                /*!< 0xF0000000 */

+#define FDCAN_CREL_REL            FDCAN_CREL_REL_Msk                           /*!<Core release                            */

+

+/*****************  Bit definition for FDCAN_ENDN register  *******************/

+#define FDCAN_ENDN_ETV_Pos        (0U)

+#define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endiannes Test Value                    */

+

+/*****************  Bit definition for FDCAN_DBTP register  *******************/

+#define FDCAN_DBTP_DSJW_Pos       (0U)

+#define FDCAN_DBTP_DSJW_Msk       (0xFUL << FDCAN_DBTP_DSJW_Pos)               /*!< 0x0000000F */

+#define FDCAN_DBTP_DSJW           FDCAN_DBTP_DSJW_Msk                          /*!<Synchronization Jump Width              */

+#define FDCAN_DBTP_DTSEG2_Pos     (4U)

+#define FDCAN_DBTP_DTSEG2_Msk     (0xFUL << FDCAN_DBTP_DTSEG2_Pos)             /*!< 0x000000F0 */

+#define FDCAN_DBTP_DTSEG2         FDCAN_DBTP_DTSEG2_Msk                        /*!<Data time segment after sample point    */

+#define FDCAN_DBTP_DTSEG1_Pos     (8U)

+#define FDCAN_DBTP_DTSEG1_Msk     (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)            /*!< 0x00001F00 */

+#define FDCAN_DBTP_DTSEG1         FDCAN_DBTP_DTSEG1_Msk                        /*!<Data time segment before sample point   */

+#define FDCAN_DBTP_DBRP_Pos       (16U)

+#define FDCAN_DBTP_DBRP_Msk       (0x1FUL << FDCAN_DBTP_DBRP_Pos)              /*!< 0x001F0000 */

+#define FDCAN_DBTP_DBRP           FDCAN_DBTP_DBRP_Msk                          /*!<Data BIt Rate Prescaler                 */

+#define FDCAN_DBTP_TDC_Pos        (23U)

+#define FDCAN_DBTP_TDC_Msk        (0x1UL << FDCAN_DBTP_TDC_Pos)                /*!< 0x00800000 */

+#define FDCAN_DBTP_TDC            FDCAN_DBTP_TDC_Msk                           /*!<Transceiver Delay Compensation          */

+

+/*****************  Bit definition for FDCAN_TEST register  *******************/

+#define FDCAN_TEST_LBCK_Pos       (4U)

+#define FDCAN_TEST_LBCK_Msk       (0x1UL << FDCAN_TEST_LBCK_Pos)               /*!< 0x00000010 */

+#define FDCAN_TEST_LBCK           FDCAN_TEST_LBCK_Msk                          /*!<Loop Back mode                           */

+#define FDCAN_TEST_TX_Pos         (5U)

+#define FDCAN_TEST_TX_Msk         (0x3UL << FDCAN_TEST_TX_Pos)                 /*!< 0x00000060 */

+#define FDCAN_TEST_TX             FDCAN_TEST_TX_Msk                            /*!<Control of Transmit Pin                  */

+#define FDCAN_TEST_RX_Pos         (7U)

+#define FDCAN_TEST_RX_Msk         (0x1UL << FDCAN_TEST_RX_Pos)                 /*!< 0x00000080 */

+#define FDCAN_TEST_RX             FDCAN_TEST_RX_Msk                            /*!<Receive Pin                              */

+

+/*****************  Bit definition for FDCAN_RWD register  ********************/

+#define FDCAN_RWD_WDC_Pos         (0U)

+#define FDCAN_RWD_WDC_Msk         (0xFFUL << FDCAN_RWD_WDC_Pos)                /*!< 0x000000FF */

+#define FDCAN_RWD_WDC             FDCAN_RWD_WDC_Msk                            /*!<Watchdog configuration                   */

+#define FDCAN_RWD_WDV_Pos         (8U)

+#define FDCAN_RWD_WDV_Msk         (0xFFUL << FDCAN_RWD_WDV_Pos)                /*!< 0x0000FF00 */

+#define FDCAN_RWD_WDV             FDCAN_RWD_WDV_Msk                            /*!<Watchdog value                           */

+

+/*****************  Bit definition for FDCAN_CCCR register  ********************/

+#define FDCAN_CCCR_INIT_Pos       (0U)

+#define FDCAN_CCCR_INIT_Msk       (0x1UL << FDCAN_CCCR_INIT_Pos)               /*!< 0x00000001 */

+#define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!<Initialization                           */

+#define FDCAN_CCCR_CCE_Pos        (1U)

+#define FDCAN_CCCR_CCE_Msk        (0x1UL << FDCAN_CCCR_CCE_Pos)                /*!< 0x00000002 */

+#define FDCAN_CCCR_CCE            FDCAN_CCCR_CCE_Msk                           /*!<Configuration Change Enable              */

+#define FDCAN_CCCR_ASM_Pos        (2U)

+#define FDCAN_CCCR_ASM_Msk        (0x1UL << FDCAN_CCCR_ASM_Pos)                /*!< 0x00000004 */

+#define FDCAN_CCCR_ASM            FDCAN_CCCR_ASM_Msk                           /*!<ASM Restricted Operation Mode            */

+#define FDCAN_CCCR_CSA_Pos        (3U)

+#define FDCAN_CCCR_CSA_Msk        (0x1UL << FDCAN_CCCR_CSA_Pos)                /*!< 0x00000008 */

+#define FDCAN_CCCR_CSA            FDCAN_CCCR_CSA_Msk                           /*!<Clock Stop Acknowledge                   */

+#define FDCAN_CCCR_CSR_Pos        (4U)

+#define FDCAN_CCCR_CSR_Msk        (0x1UL << FDCAN_CCCR_CSR_Pos)                /*!< 0x00000010 */

+#define FDCAN_CCCR_CSR            FDCAN_CCCR_CSR_Msk                           /*!<Clock Stop Request                       */

+#define FDCAN_CCCR_MON_Pos        (5U)

+#define FDCAN_CCCR_MON_Msk        (0x1UL << FDCAN_CCCR_MON_Pos)                /*!< 0x00000020 */

+#define FDCAN_CCCR_MON            FDCAN_CCCR_MON_Msk                           /*!<Bus Monitoring Mode                      */

+#define FDCAN_CCCR_DAR_Pos        (6U)

+#define FDCAN_CCCR_DAR_Msk        (0x1UL << FDCAN_CCCR_DAR_Pos)                /*!< 0x00000040 */

+#define FDCAN_CCCR_DAR            FDCAN_CCCR_DAR_Msk                           /*!<Disable Automatic Retransmission         */

+#define FDCAN_CCCR_TEST_Pos       (7U)

+#define FDCAN_CCCR_TEST_Msk       (0x1UL << FDCAN_CCCR_TEST_Pos)               /*!< 0x00000080 */

+#define FDCAN_CCCR_TEST           FDCAN_CCCR_TEST_Msk                          /*!<Test Mode Enable                         */

+#define FDCAN_CCCR_FDOE_Pos       (8U)

+#define FDCAN_CCCR_FDOE_Msk       (0x1UL << FDCAN_CCCR_FDOE_Pos)               /*!< 0x00000100 */

+#define FDCAN_CCCR_FDOE           FDCAN_CCCR_FDOE_Msk                          /*!<FD Operation Enable                      */

+#define FDCAN_CCCR_BRSE_Pos       (9U)

+#define FDCAN_CCCR_BRSE_Msk       (0x1UL << FDCAN_CCCR_BRSE_Pos)               /*!< 0x00000200 */

+#define FDCAN_CCCR_BRSE           FDCAN_CCCR_BRSE_Msk                          /*!<FDCAN Bit Rate Switching                 */

+#define FDCAN_CCCR_PXHD_Pos       (12U)

+#define FDCAN_CCCR_PXHD_Msk       (0x1UL << FDCAN_CCCR_PXHD_Pos)               /*!< 0x00001000 */

+#define FDCAN_CCCR_PXHD           FDCAN_CCCR_PXHD_Msk                          /*!<Protocol Exception Handling Disable      */

+#define FDCAN_CCCR_EFBI_Pos       (13U)

+#define FDCAN_CCCR_EFBI_Msk       (0x1UL << FDCAN_CCCR_EFBI_Pos)               /*!< 0x00002000 */

+#define FDCAN_CCCR_EFBI           FDCAN_CCCR_EFBI_Msk                          /*!<Edge Filtering during Bus Integration    */

+#define FDCAN_CCCR_TXP_Pos        (14U)

+#define FDCAN_CCCR_TXP_Msk        (0x1UL << FDCAN_CCCR_TXP_Pos)                /*!< 0x00004000 */

+#define FDCAN_CCCR_TXP            FDCAN_CCCR_TXP_Msk                           /*!<Two CAN bit times Pause                  */

+#define FDCAN_CCCR_NISO_Pos       (15U)

+#define FDCAN_CCCR_NISO_Msk       (0x1UL << FDCAN_CCCR_NISO_Pos)               /*!< 0x00008000 */

+#define FDCAN_CCCR_NISO           FDCAN_CCCR_NISO_Msk                          /*!<Non ISO Operation                        */

+

+/*****************  Bit definition for FDCAN_NBTP register  ********************/

+#define FDCAN_NBTP_NTSEG2_Pos     (0U)

+#define FDCAN_NBTP_NTSEG2_Msk     (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)            /*!< 0x0000007F */

+#define FDCAN_NBTP_NTSEG2         FDCAN_NBTP_NTSEG2_Msk                        /*!<Nominal Time segment after sample point  */

+#define FDCAN_NBTP_NTSEG1_Pos     (8U)

+#define FDCAN_NBTP_NTSEG1_Msk     (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)            /*!< 0x0000FF00 */

+#define FDCAN_NBTP_NTSEG1         FDCAN_NBTP_NTSEG1_Msk                        /*!<Nominal Time segment before sample point */

+#define FDCAN_NBTP_NBRP_Pos       (16U)

+#define FDCAN_NBTP_NBRP_Msk       (0x1FFUL << FDCAN_NBTP_NBRP_Pos)             /*!< 0x01FF0000 */

+#define FDCAN_NBTP_NBRP           FDCAN_NBTP_NBRP_Msk                          /*!<Bit Rate Prescaler                       */

+#define FDCAN_NBTP_NSJW_Pos       (25U)

+#define FDCAN_NBTP_NSJW_Msk       (0x7FUL << FDCAN_NBTP_NSJW_Pos)              /*!< 0xFE000000 */

+#define FDCAN_NBTP_NSJW           FDCAN_NBTP_NSJW_Msk                          /*!<Nominal (Re)Synchronization Jump Width   */

+

+/*****************  Bit definition for FDCAN_TSCC register  ********************/

+#define FDCAN_TSCC_TSS_Pos        (0U)

+#define FDCAN_TSCC_TSS_Msk        (0x3UL << FDCAN_TSCC_TSS_Pos)                /*!< 0x00000003 */

+#define FDCAN_TSCC_TSS            FDCAN_TSCC_TSS_Msk                           /*!<Timestamp Select                         */

+#define FDCAN_TSCC_TCP_Pos        (16U)

+#define FDCAN_TSCC_TCP_Msk        (0xFUL << FDCAN_TSCC_TCP_Pos)                /*!< 0x000F0000 */

+#define FDCAN_TSCC_TCP            FDCAN_TSCC_TCP_Msk                           /*!<Timestamp Counter Prescaler              */

+

+/*****************  Bit definition for FDCAN_TSCV register  ********************/

+#define FDCAN_TSCV_TSC_Pos        (0U)

+#define FDCAN_TSCV_TSC_Msk        (0xFFFFUL << FDCAN_TSCV_TSC_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TSCV_TSC            FDCAN_TSCV_TSC_Msk                           /*!<Timestamp Counter                        */

+

+/*****************  Bit definition for FDCAN_TOCC register  ********************/

+#define FDCAN_TOCC_ETOC_Pos       (0U)

+#define FDCAN_TOCC_ETOC_Msk       (0x1UL << FDCAN_TOCC_ETOC_Pos)               /*!< 0x00000001 */

+#define FDCAN_TOCC_ETOC           FDCAN_TOCC_ETOC_Msk                          /*!<Enable Timeout Counter                   */

+#define FDCAN_TOCC_TOS_Pos        (1U)

+#define FDCAN_TOCC_TOS_Msk        (0x3UL << FDCAN_TOCC_TOS_Pos)                /*!< 0x00000006 */

+#define FDCAN_TOCC_TOS            FDCAN_TOCC_TOS_Msk                           /*!<Timeout Select                           */

+#define FDCAN_TOCC_TOP_Pos        (16U)

+#define FDCAN_TOCC_TOP_Msk        (0xFFFFUL << FDCAN_TOCC_TOP_Pos)             /*!< 0xFFFF0000 */

+#define FDCAN_TOCC_TOP            FDCAN_TOCC_TOP_Msk                           /*!<Timeout Period                           */

+

+/*****************  Bit definition for FDCAN_TOCV register  ********************/

+#define FDCAN_TOCV_TOC_Pos        (0U)

+#define FDCAN_TOCV_TOC_Msk        (0xFFFFUL << FDCAN_TOCV_TOC_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TOCV_TOC            FDCAN_TOCV_TOC_Msk                           /*!<Timeout Counter                          */

+

+/*****************  Bit definition for FDCAN_ECR register  *********************/

+#define FDCAN_ECR_TEC_Pos         (0U)

+#define FDCAN_ECR_TEC_Msk         (0xFUL << FDCAN_ECR_TEC_Pos)                 /*!< 0x0000000F */

+#define FDCAN_ECR_TEC             FDCAN_ECR_TEC_Msk                            /*!<Transmit Error Counter                   */

+#define FDCAN_ECR_REC_Pos         (8U)

+#define FDCAN_ECR_REC_Msk         (0x7FUL << FDCAN_ECR_REC_Pos)                /*!< 0x00007F00 */

+#define FDCAN_ECR_REC             FDCAN_ECR_REC_Msk                            /*!<Receive Error Counter                    */

+#define FDCAN_ECR_RP_Pos          (15U)

+#define FDCAN_ECR_RP_Msk          (0x1UL << FDCAN_ECR_RP_Pos)                  /*!< 0x00008000 */

+#define FDCAN_ECR_RP              FDCAN_ECR_RP_Msk                             /*!<Receive Error Passive                    */

+#define FDCAN_ECR_CEL_Pos         (16U)

+#define FDCAN_ECR_CEL_Msk         (0xFFUL << FDCAN_ECR_CEL_Pos)                /*!< 0x00FF0000 */

+#define FDCAN_ECR_CEL             FDCAN_ECR_CEL_Msk                            /*!<CAN Error Logging                        */

+

+/*****************  Bit definition for FDCAN_PSR register  *********************/

+#define FDCAN_PSR_LEC_Pos         (0U)

+#define FDCAN_PSR_LEC_Msk         (0x7UL << FDCAN_PSR_LEC_Pos)                 /*!< 0x00000007 */

+#define FDCAN_PSR_LEC             FDCAN_PSR_LEC_Msk                            /*!<Last Error Code                          */

+#define FDCAN_PSR_ACT_Pos         (3U)

+#define FDCAN_PSR_ACT_Msk         (0x3UL << FDCAN_PSR_ACT_Pos)                 /*!< 0x00000018 */

+#define FDCAN_PSR_ACT             FDCAN_PSR_ACT_Msk                            /*!<Activity                                 */

+#define FDCAN_PSR_EP_Pos          (5U)

+#define FDCAN_PSR_EP_Msk          (0x1UL << FDCAN_PSR_EP_Pos)                  /*!< 0x00000020 */

+#define FDCAN_PSR_EP              FDCAN_PSR_EP_Msk                             /*!<Error Passive                            */

+#define FDCAN_PSR_EW_Pos          (6U)

+#define FDCAN_PSR_EW_Msk          (0x1UL << FDCAN_PSR_EW_Pos)                  /*!< 0x00000040 */

+#define FDCAN_PSR_EW              FDCAN_PSR_EW_Msk                             /*!<Warning Status                           */

+#define FDCAN_PSR_BO_Pos          (7U)

+#define FDCAN_PSR_BO_Msk          (0x1UL << FDCAN_PSR_BO_Pos)                  /*!< 0x00000080 */

+#define FDCAN_PSR_BO              FDCAN_PSR_BO_Msk                             /*!<Bus_Off Status                           */

+#define FDCAN_PSR_DLEC_Pos        (8U)

+#define FDCAN_PSR_DLEC_Msk        (0x7UL << FDCAN_PSR_DLEC_Pos)                /*!< 0x00000700 */

+#define FDCAN_PSR_DLEC            FDCAN_PSR_DLEC_Msk                           /*!<Data Last Error Code                     */

+#define FDCAN_PSR_RESI_Pos        (11U)

+#define FDCAN_PSR_RESI_Msk        (0x1UL << FDCAN_PSR_RESI_Pos)                /*!< 0x00000800 */

+#define FDCAN_PSR_RESI            FDCAN_PSR_RESI_Msk                           /*!<ESI flag of last received FDCAN Message  */

+#define FDCAN_PSR_RBRS_Pos        (12U)

+#define FDCAN_PSR_RBRS_Msk        (0x1UL << FDCAN_PSR_RBRS_Pos)                /*!< 0x00001000 */

+#define FDCAN_PSR_RBRS            FDCAN_PSR_RBRS_Msk                           /*!<BRS flag of last received FDCAN Message  */

+#define FDCAN_PSR_REDL_Pos        (13U)

+#define FDCAN_PSR_REDL_Msk        (0x1UL << FDCAN_PSR_REDL_Pos)                /*!< 0x00002000 */

+#define FDCAN_PSR_REDL            FDCAN_PSR_REDL_Msk                           /*!<Received FDCAN Message                   */

+#define FDCAN_PSR_PXE_Pos         (14U)

+#define FDCAN_PSR_PXE_Msk         (0x1UL << FDCAN_PSR_PXE_Pos)                 /*!< 0x00004000 */

+#define FDCAN_PSR_PXE             FDCAN_PSR_PXE_Msk                            /*!<Protocol Exception Event                 */

+#define FDCAN_PSR_TDCV_Pos        (16U)

+#define FDCAN_PSR_TDCV_Msk        (0x7FUL << FDCAN_PSR_TDCV_Pos)               /*!< 0x007F0000 */

+#define FDCAN_PSR_TDCV            FDCAN_PSR_TDCV_Msk                           /*!<Transmitter Delay Compensation Value     */

+

+/*****************  Bit definition for FDCAN_TDCR register  ********************/

+#define FDCAN_TDCR_TDCF_Pos       (0U)

+#define FDCAN_TDCR_TDCF_Msk       (0x7FUL << FDCAN_TDCR_TDCF_Pos)              /*!< 0x0000007F */

+#define FDCAN_TDCR_TDCF           FDCAN_TDCR_TDCF_Msk                          /*!<Transmitter Delay Compensation Filter    */

+#define FDCAN_TDCR_TDCO_Pos       (8U)

+#define FDCAN_TDCR_TDCO_Msk       (0x7FUL << FDCAN_TDCR_TDCO_Pos)              /*!< 0x00007F00 */

+#define FDCAN_TDCR_TDCO           FDCAN_TDCR_TDCO_Msk                          /*!<Transmitter Delay Compensation Offset    */

+

+/*****************  Bit definition for FDCAN_IR register  **********************/

+#define FDCAN_IR_RF0N_Pos         (0U)

+#define FDCAN_IR_RF0N_Msk         (0x1UL << FDCAN_IR_RF0N_Pos)                 /*!< 0x00000001 */

+#define FDCAN_IR_RF0N             FDCAN_IR_RF0N_Msk                            /*!<Rx FIFO 0 New Message                    */

+#define FDCAN_IR_RF0W_Pos         (1U)

+#define FDCAN_IR_RF0W_Msk         (0x1UL << FDCAN_IR_RF0W_Pos)                 /*!< 0x00000002 */

+#define FDCAN_IR_RF0W             FDCAN_IR_RF0W_Msk                            /*!<Rx FIFO 0 Watermark Reached              */

+#define FDCAN_IR_RF0F_Pos         (2U)

+#define FDCAN_IR_RF0F_Msk         (0x1UL << FDCAN_IR_RF0F_Pos)                 /*!< 0x00000004 */

+#define FDCAN_IR_RF0F             FDCAN_IR_RF0F_Msk                            /*!<Rx FIFO 0 Full                           */

+#define FDCAN_IR_RF0L_Pos         (3U)

+#define FDCAN_IR_RF0L_Msk         (0x1UL << FDCAN_IR_RF0L_Pos)                 /*!< 0x00000008 */

+#define FDCAN_IR_RF0L             FDCAN_IR_RF0L_Msk                            /*!<Rx FIFO 0 Message Lost                   */

+#define FDCAN_IR_RF1N_Pos         (4U)

+#define FDCAN_IR_RF1N_Msk         (0x1UL << FDCAN_IR_RF1N_Pos)                 /*!< 0x00000010 */

+#define FDCAN_IR_RF1N             FDCAN_IR_RF1N_Msk                            /*!<Rx FIFO 1 New Message                    */

+#define FDCAN_IR_RF1W_Pos         (5U)

+#define FDCAN_IR_RF1W_Msk         (0x1UL << FDCAN_IR_RF1W_Pos)                 /*!< 0x00000020 */

+#define FDCAN_IR_RF1W             FDCAN_IR_RF1W_Msk                            /*!<Rx FIFO 1 Watermark Reached              */

+#define FDCAN_IR_RF1F_Pos         (6U)

+#define FDCAN_IR_RF1F_Msk         (0x1UL << FDCAN_IR_RF1F_Pos)                 /*!< 0x00000040 */

+#define FDCAN_IR_RF1F             FDCAN_IR_RF1F_Msk                            /*!<Rx FIFO 1 Full                           */

+#define FDCAN_IR_RF1L_Pos         (7U)

+#define FDCAN_IR_RF1L_Msk         (0x1UL << FDCAN_IR_RF1L_Pos)                 /*!< 0x00000080 */

+#define FDCAN_IR_RF1L             FDCAN_IR_RF1L_Msk                            /*!<Rx FIFO 1 Message Lost                   */

+#define FDCAN_IR_HPM_Pos          (8U)

+#define FDCAN_IR_HPM_Msk          (0x1UL << FDCAN_IR_HPM_Pos)                  /*!< 0x00000100 */

+#define FDCAN_IR_HPM              FDCAN_IR_HPM_Msk                             /*!<High Priority Message                    */

+#define FDCAN_IR_TC_Pos           (9U)

+#define FDCAN_IR_TC_Msk           (0x1UL << FDCAN_IR_TC_Pos)                   /*!< 0x00000200 */

+#define FDCAN_IR_TC               FDCAN_IR_TC_Msk                              /*!<Transmission Completed                   */

+#define FDCAN_IR_TCF_Pos          (10U)

+#define FDCAN_IR_TCF_Msk          (0x1UL << FDCAN_IR_TCF_Pos)                  /*!< 0x00000400 */

+#define FDCAN_IR_TCF              FDCAN_IR_TCF_Msk                             /*!<Transmission Cancellation Finished       */

+#define FDCAN_IR_TFE_Pos          (11U)

+#define FDCAN_IR_TFE_Msk          (0x1UL << FDCAN_IR_TFE_Pos)                  /*!< 0x00000800 */

+#define FDCAN_IR_TFE              FDCAN_IR_TFE_Msk                             /*!<Tx FIFO Empty                            */

+#define FDCAN_IR_TEFN_Pos         (12U)

+#define FDCAN_IR_TEFN_Msk         (0x1UL << FDCAN_IR_TEFN_Pos)                 /*!< 0x00001000 */

+#define FDCAN_IR_TEFN             FDCAN_IR_TEFN_Msk                            /*!<Tx Event FIFO New Entry                  */

+#define FDCAN_IR_TEFW_Pos         (13U)

+#define FDCAN_IR_TEFW_Msk         (0x1UL << FDCAN_IR_TEFW_Pos)                 /*!< 0x00002000 */

+#define FDCAN_IR_TEFW             FDCAN_IR_TEFW_Msk                            /*!<Tx Event FIFO Watermark Reached          */

+#define FDCAN_IR_TEFF_Pos         (14U)

+#define FDCAN_IR_TEFF_Msk         (0x1UL << FDCAN_IR_TEFF_Pos)                 /*!< 0x00004000 */

+#define FDCAN_IR_TEFF             FDCAN_IR_TEFF_Msk                            /*!<Tx Event FIFO Full                       */

+#define FDCAN_IR_TEFL_Pos         (15U)

+#define FDCAN_IR_TEFL_Msk         (0x1UL << FDCAN_IR_TEFL_Pos)                 /*!< 0x00008000 */

+#define FDCAN_IR_TEFL             FDCAN_IR_TEFL_Msk                            /*!<Tx Event FIFO Element Lost               */

+#define FDCAN_IR_TSW_Pos          (16U)

+#define FDCAN_IR_TSW_Msk          (0x1UL << FDCAN_IR_TSW_Pos)                  /*!< 0x00010000 */

+#define FDCAN_IR_TSW              FDCAN_IR_TSW_Msk                             /*!<Timestamp Wraparound                     */

+#define FDCAN_IR_MRAF_Pos         (17U)

+#define FDCAN_IR_MRAF_Msk         (0x1UL << FDCAN_IR_MRAF_Pos)                 /*!< 0x00020000 */

+#define FDCAN_IR_MRAF             FDCAN_IR_MRAF_Msk                            /*!<Message RAM Access Failure               */

+#define FDCAN_IR_TOO_Pos          (18U)

+#define FDCAN_IR_TOO_Msk          (0x1UL << FDCAN_IR_TOO_Pos)                  /*!< 0x00040000 */

+#define FDCAN_IR_TOO              FDCAN_IR_TOO_Msk                             /*!<Timeout Occurred                         */

+#define FDCAN_IR_DRX_Pos          (19U)

+#define FDCAN_IR_DRX_Msk          (0x1UL << FDCAN_IR_DRX_Pos)                  /*!< 0x00080000 */

+#define FDCAN_IR_DRX              FDCAN_IR_DRX_Msk                             /*!<Message stored to Dedicated Rx Buffer    */

+#define FDCAN_IR_ELO_Pos          (22U)

+#define FDCAN_IR_ELO_Msk          (0x1UL << FDCAN_IR_ELO_Pos)                  /*!< 0x00400000 */

+#define FDCAN_IR_ELO              FDCAN_IR_ELO_Msk                             /*!<Error Logging Overflow                   */

+#define FDCAN_IR_EP_Pos           (23U)

+#define FDCAN_IR_EP_Msk           (0x1UL << FDCAN_IR_EP_Pos)                   /*!< 0x00800000 */

+#define FDCAN_IR_EP               FDCAN_IR_EP_Msk                              /*!<Error Passive                            */

+#define FDCAN_IR_EW_Pos           (24U)

+#define FDCAN_IR_EW_Msk           (0x1UL << FDCAN_IR_EW_Pos)                   /*!< 0x01000000 */

+#define FDCAN_IR_EW               FDCAN_IR_EW_Msk                              /*!<Warning Status                           */

+#define FDCAN_IR_BO_Pos           (25U)

+#define FDCAN_IR_BO_Msk           (0x1UL << FDCAN_IR_BO_Pos)                   /*!< 0x02000000 */

+#define FDCAN_IR_BO               FDCAN_IR_BO_Msk                              /*!<Bus_Off Status                           */

+#define FDCAN_IR_WDI_Pos          (26U)

+#define FDCAN_IR_WDI_Msk          (0x1UL << FDCAN_IR_WDI_Pos)                  /*!< 0x04000000 */

+#define FDCAN_IR_WDI              FDCAN_IR_WDI_Msk                             /*!<Watchdog Interrupt                       */

+#define FDCAN_IR_PEA_Pos          (27U)

+#define FDCAN_IR_PEA_Msk          (0x1UL << FDCAN_IR_PEA_Pos)                  /*!< 0x08000000 */

+#define FDCAN_IR_PEA              FDCAN_IR_PEA_Msk                             /*!<Protocol Error in Arbitration Phase      */

+#define FDCAN_IR_PED_Pos          (28U)

+#define FDCAN_IR_PED_Msk          (0x1UL << FDCAN_IR_PED_Pos)                  /*!< 0x10000000 */

+#define FDCAN_IR_PED              FDCAN_IR_PED_Msk                             /*!<Protocol Error in Data Phase             */

+#define FDCAN_IR_ARA_Pos          (29U)

+#define FDCAN_IR_ARA_Msk          (0x1UL << FDCAN_IR_ARA_Pos)                  /*!< 0x20000000 */

+#define FDCAN_IR_ARA              FDCAN_IR_ARA_Msk                             /*!<Access to Reserved Address               */

+

+/*****************  Bit definition for FDCAN_IE register  **********************/

+#define FDCAN_IE_RF0NE_Pos        (0U)

+#define FDCAN_IE_RF0NE_Msk        (0x1UL << FDCAN_IE_RF0NE_Pos)                /*!< 0x00000001 */

+#define FDCAN_IE_RF0NE            FDCAN_IE_RF0NE_Msk                           /*!<Rx FIFO 0 New Message Enable                 */

+#define FDCAN_IE_RF0WE_Pos        (1U)

+#define FDCAN_IE_RF0WE_Msk        (0x1UL << FDCAN_IE_RF0WE_Pos)                /*!< 0x00000002 */

+#define FDCAN_IE_RF0WE            FDCAN_IE_RF0WE_Msk                           /*!<Rx FIFO 0 Watermark Reached Enable           */

+#define FDCAN_IE_RF0FE_Pos        (2U)

+#define FDCAN_IE_RF0FE_Msk        (0x1UL << FDCAN_IE_RF0FE_Pos)                /*!< 0x00000004 */

+#define FDCAN_IE_RF0FE            FDCAN_IE_RF0FE_Msk                           /*!<Rx FIFO 0 Full Enable                        */

+#define FDCAN_IE_RF0LE_Pos        (3U)

+#define FDCAN_IE_RF0LE_Msk        (0x1UL << FDCAN_IE_RF0LE_Pos)                /*!< 0x00000008 */

+#define FDCAN_IE_RF0LE            FDCAN_IE_RF0LE_Msk                           /*!<Rx FIFO 0 Message Lost Enable                */

+#define FDCAN_IE_RF1NE_Pos        (4U)

+#define FDCAN_IE_RF1NE_Msk        (0x1UL << FDCAN_IE_RF1NE_Pos)                /*!< 0x00000010 */

+#define FDCAN_IE_RF1NE            FDCAN_IE_RF1NE_Msk                           /*!<Rx FIFO 1 New Message Enable                 */

+#define FDCAN_IE_RF1WE_Pos        (5U)

+#define FDCAN_IE_RF1WE_Msk        (0x1UL << FDCAN_IE_RF1WE_Pos)                /*!< 0x00000020 */

+#define FDCAN_IE_RF1WE            FDCAN_IE_RF1WE_Msk                           /*!<Rx FIFO 1 Watermark Reached Enable           */

+#define FDCAN_IE_RF1FE_Pos        (6U)

+#define FDCAN_IE_RF1FE_Msk        (0x1UL << FDCAN_IE_RF1FE_Pos)                /*!< 0x00000040 */

+#define FDCAN_IE_RF1FE            FDCAN_IE_RF1FE_Msk                           /*!<Rx FIFO 1 Full Enable                        */

+#define FDCAN_IE_RF1LE_Pos        (7U)

+#define FDCAN_IE_RF1LE_Msk        (0x1UL << FDCAN_IE_RF1LE_Pos)                /*!< 0x00000080 */

+#define FDCAN_IE_RF1LE            FDCAN_IE_RF1LE_Msk                           /*!<Rx FIFO 1 Message Lost Enable                */

+#define FDCAN_IE_HPME_Pos         (8U)

+#define FDCAN_IE_HPME_Msk         (0x1UL << FDCAN_IE_HPME_Pos)                 /*!< 0x00000100 */

+#define FDCAN_IE_HPME             FDCAN_IE_HPME_Msk                            /*!<High Priority Message Enable                 */

+#define FDCAN_IE_TCE_Pos          (9U)

+#define FDCAN_IE_TCE_Msk          (0x1UL << FDCAN_IE_TCE_Pos)                  /*!< 0x00000200 */

+#define FDCAN_IE_TCE              FDCAN_IE_TCE_Msk                             /*!<Transmission Completed Enable                */

+#define FDCAN_IE_TCFE_Pos         (10U)

+#define FDCAN_IE_TCFE_Msk         (0x1UL << FDCAN_IE_TCFE_Pos)                 /*!< 0x00000400 */

+#define FDCAN_IE_TCFE             FDCAN_IE_TCFE_Msk                            /*!<Transmission Cancellation Finished Enable    */

+#define FDCAN_IE_TFEE_Pos         (11U)

+#define FDCAN_IE_TFEE_Msk         (0x1UL << FDCAN_IE_TFEE_Pos)                 /*!< 0x00000800 */

+#define FDCAN_IE_TFEE             FDCAN_IE_TFEE_Msk                            /*!<Tx FIFO Empty Enable                         */

+#define FDCAN_IE_TEFNE_Pos        (12U)

+#define FDCAN_IE_TEFNE_Msk        (0x1UL << FDCAN_IE_TEFNE_Pos)                /*!< 0x00001000 */

+#define FDCAN_IE_TEFNE            FDCAN_IE_TEFNE_Msk                           /*!<Tx Event FIFO New Entry Enable               */

+#define FDCAN_IE_TEFWE_Pos        (13U)

+#define FDCAN_IE_TEFWE_Msk        (0x1UL << FDCAN_IE_TEFWE_Pos)                /*!< 0x00002000 */

+#define FDCAN_IE_TEFWE            FDCAN_IE_TEFWE_Msk                           /*!<Tx Event FIFO Watermark Reached Enable       */

+#define FDCAN_IE_TEFFE_Pos        (14U)

+#define FDCAN_IE_TEFFE_Msk        (0x1UL << FDCAN_IE_TEFFE_Pos)                /*!< 0x00004000 */

+#define FDCAN_IE_TEFFE            FDCAN_IE_TEFFE_Msk                           /*!<Tx Event FIFO Full Enable                    */

+#define FDCAN_IE_TEFLE_Pos        (15U)

+#define FDCAN_IE_TEFLE_Msk        (0x1UL << FDCAN_IE_TEFLE_Pos)                /*!< 0x00008000 */

+#define FDCAN_IE_TEFLE            FDCAN_IE_TEFLE_Msk                           /*!<Tx Event FIFO Element Lost Enable            */

+#define FDCAN_IE_TSWE_Pos         (16U)

+#define FDCAN_IE_TSWE_Msk         (0x1UL << FDCAN_IE_TSWE_Pos)                 /*!< 0x00010000 */

+#define FDCAN_IE_TSWE             FDCAN_IE_TSWE_Msk                            /*!<Timestamp Wraparound Enable                  */

+#define FDCAN_IE_MRAFE_Pos        (17U)

+#define FDCAN_IE_MRAFE_Msk        (0x1UL << FDCAN_IE_MRAFE_Pos)                /*!< 0x00020000 */

+#define FDCAN_IE_MRAFE            FDCAN_IE_MRAFE_Msk                           /*!<Message RAM Access Failure Enable            */

+#define FDCAN_IE_TOOE_Pos         (18U)

+#define FDCAN_IE_TOOE_Msk         (0x1UL << FDCAN_IE_TOOE_Pos)                 /*!< 0x00040000 */

+#define FDCAN_IE_TOOE             FDCAN_IE_TOOE_Msk                            /*!<Timeout Occurred Enable                      */

+#define FDCAN_IE_DRXE_Pos         (19U)

+#define FDCAN_IE_DRXE_Msk         (0x1UL << FDCAN_IE_DRXE_Pos)                 /*!< 0x00080000 */

+#define FDCAN_IE_DRXE             FDCAN_IE_DRXE_Msk                            /*!<Message stored to Dedicated Rx Buffer Enable */

+#define FDCAN_IE_BECE_Pos         (20U)

+#define FDCAN_IE_BECE_Msk         (0x1UL << FDCAN_IE_BECE_Pos)                 /*!< 0x00100000 */

+#define FDCAN_IE_BECE             FDCAN_IE_BECE_Msk                            /*!<Bit Error Corrected Interrupt Enable         */

+#define FDCAN_IE_BEUE_Pos         (21U)

+#define FDCAN_IE_BEUE_Msk         (0x1UL << FDCAN_IE_BEUE_Pos)                 /*!< 0x00200000 */

+#define FDCAN_IE_BEUE             FDCAN_IE_BEUE_Msk                            /*!<Bit Error Uncorrected Interrupt Enable       */

+#define FDCAN_IE_ELOE_Pos         (22U)

+#define FDCAN_IE_ELOE_Msk         (0x1UL << FDCAN_IE_ELOE_Pos)                 /*!< 0x00400000 */

+#define FDCAN_IE_ELOE             FDCAN_IE_ELOE_Msk                            /*!<Error Logging Overflow Enable                */

+#define FDCAN_IE_EPE_Pos          (23U)

+#define FDCAN_IE_EPE_Msk          (0x1UL << FDCAN_IE_EPE_Pos)                  /*!< 0x00800000 */

+#define FDCAN_IE_EPE              FDCAN_IE_EPE_Msk                             /*!<Error Passive Enable                         */

+#define FDCAN_IE_EWE_Pos          (24U)

+#define FDCAN_IE_EWE_Msk          (0x1UL << FDCAN_IE_EWE_Pos)                  /*!< 0x01000000 */

+#define FDCAN_IE_EWE              FDCAN_IE_EWE_Msk                             /*!<Warning Status Enable                        */

+#define FDCAN_IE_BOE_Pos          (25U)

+#define FDCAN_IE_BOE_Msk          (0x1UL << FDCAN_IE_BOE_Pos)                  /*!< 0x02000000 */

+#define FDCAN_IE_BOE              FDCAN_IE_BOE_Msk                             /*!<Bus_Off Status Enable                        */

+#define FDCAN_IE_WDIE_Pos         (26U)

+#define FDCAN_IE_WDIE_Msk         (0x1UL << FDCAN_IE_WDIE_Pos)                 /*!< 0x04000000 */

+#define FDCAN_IE_WDIE             FDCAN_IE_WDIE_Msk                            /*!<Watchdog Interrupt Enable                    */

+#define FDCAN_IE_PEAE_Pos         (27U)

+#define FDCAN_IE_PEAE_Msk         (0x1UL << FDCAN_IE_PEAE_Pos)                 /*!< 0x08000000 */

+#define FDCAN_IE_PEAE             FDCAN_IE_PEAE_Msk                            /*!<Protocol Error in Arbitration Phase Enable   */

+#define FDCAN_IE_PEDE_Pos         (28U)

+#define FDCAN_IE_PEDE_Msk         (0x1UL << FDCAN_IE_PEDE_Pos)                 /*!< 0x10000000 */

+#define FDCAN_IE_PEDE             FDCAN_IE_PEDE_Msk                            /*!<Protocol Error in Data Phase Enable          */

+#define FDCAN_IE_ARAE_Pos         (29U)

+#define FDCAN_IE_ARAE_Msk         (0x1UL << FDCAN_IE_ARAE_Pos)                 /*!< 0x20000000 */

+#define FDCAN_IE_ARAE             FDCAN_IE_ARAE_Msk                            /*!<Access to Reserved Address Enable            */

+

+/*****************  Bit definition for FDCAN_ILS register  **********************/

+#define FDCAN_ILS_RF0NL_Pos       (0U)

+#define FDCAN_ILS_RF0NL_Msk       (0x1UL << FDCAN_ILS_RF0NL_Pos)               /*!< 0x00000001 */

+#define FDCAN_ILS_RF0NL           FDCAN_ILS_RF0NL_Msk                          /*!<Rx FIFO 0 New Message Line                  */

+#define FDCAN_ILS_RF0WL_Pos       (1U)

+#define FDCAN_ILS_RF0WL_Msk       (0x1UL << FDCAN_ILS_RF0WL_Pos)               /*!< 0x00000002 */

+#define FDCAN_ILS_RF0WL           FDCAN_ILS_RF0WL_Msk                          /*!<Rx FIFO 0 Watermark Reached Line            */

+#define FDCAN_ILS_RF0FL_Pos       (2U)

+#define FDCAN_ILS_RF0FL_Msk       (0x1UL << FDCAN_ILS_RF0FL_Pos)               /*!< 0x00000004 */

+#define FDCAN_ILS_RF0FL           FDCAN_ILS_RF0FL_Msk                          /*!<Rx FIFO 0 Full Line                         */

+#define FDCAN_ILS_RF0LL_Pos       (3U)

+#define FDCAN_ILS_RF0LL_Msk       (0x1UL << FDCAN_ILS_RF0LL_Pos)               /*!< 0x00000008 */

+#define FDCAN_ILS_RF0LL           FDCAN_ILS_RF0LL_Msk                          /*!<Rx FIFO 0 Message Lost Line                 */

+#define FDCAN_ILS_RF1NL_Pos       (4U)

+#define FDCAN_ILS_RF1NL_Msk       (0x1UL << FDCAN_ILS_RF1NL_Pos)               /*!< 0x00000010 */

+#define FDCAN_ILS_RF1NL           FDCAN_ILS_RF1NL_Msk                          /*!<Rx FIFO 1 New Message Line                  */

+#define FDCAN_ILS_RF1WL_Pos       (5U)

+#define FDCAN_ILS_RF1WL_Msk       (0x1UL << FDCAN_ILS_RF1WL_Pos)               /*!< 0x00000020 */

+#define FDCAN_ILS_RF1WL           FDCAN_ILS_RF1WL_Msk                          /*!<Rx FIFO 1 Watermark Reached Line            */

+#define FDCAN_ILS_RF1FL_Pos       (6U)

+#define FDCAN_ILS_RF1FL_Msk       (0x1UL << FDCAN_ILS_RF1FL_Pos)               /*!< 0x00000040 */

+#define FDCAN_ILS_RF1FL           FDCAN_ILS_RF1FL_Msk                          /*!<Rx FIFO 1 Full Line                         */

+#define FDCAN_ILS_RF1LL_Pos       (7U)

+#define FDCAN_ILS_RF1LL_Msk       (0x1UL << FDCAN_ILS_RF1LL_Pos)               /*!< 0x00000080 */

+#define FDCAN_ILS_RF1LL           FDCAN_ILS_RF1LL_Msk                          /*!<Rx FIFO 1 Message Lost Line                 */

+#define FDCAN_ILS_HPML_Pos        (8U)

+#define FDCAN_ILS_HPML_Msk        (0x1UL << FDCAN_ILS_HPML_Pos)                /*!< 0x00000100 */

+#define FDCAN_ILS_HPML            FDCAN_ILS_HPML_Msk                           /*!<High Priority Message Line                  */

+#define FDCAN_ILS_TCL_Pos         (9U)

+#define FDCAN_ILS_TCL_Msk         (0x1UL << FDCAN_ILS_TCL_Pos)                 /*!< 0x00000200 */

+#define FDCAN_ILS_TCL             FDCAN_ILS_TCL_Msk                            /*!<Transmission Completed Line                 */

+#define FDCAN_ILS_TCFL_Pos        (10U)

+#define FDCAN_ILS_TCFL_Msk        (0x1UL << FDCAN_ILS_TCFL_Pos)                /*!< 0x00000400 */

+#define FDCAN_ILS_TCFL            FDCAN_ILS_TCFL_Msk                           /*!<Transmission Cancellation Finished Line     */

+#define FDCAN_ILS_TFEL_Pos        (11U)

+#define FDCAN_ILS_TFEL_Msk        (0x1UL << FDCAN_ILS_TFEL_Pos)                /*!< 0x00000800 */

+#define FDCAN_ILS_TFEL            FDCAN_ILS_TFEL_Msk                           /*!<Tx FIFO Empty Line                          */

+#define FDCAN_ILS_TEFNL_Pos       (12U)

+#define FDCAN_ILS_TEFNL_Msk       (0x1UL << FDCAN_ILS_TEFNL_Pos)               /*!< 0x00001000 */

+#define FDCAN_ILS_TEFNL           FDCAN_ILS_TEFNL_Msk                          /*!<Tx Event FIFO New Entry Line                */

+#define FDCAN_ILS_TEFWL_Pos       (13U)

+#define FDCAN_ILS_TEFWL_Msk       (0x1UL << FDCAN_ILS_TEFWL_Pos)               /*!< 0x00002000 */

+#define FDCAN_ILS_TEFWL           FDCAN_ILS_TEFWL_Msk                          /*!<Tx Event FIFO Watermark Reached Line        */

+#define FDCAN_ILS_TEFFL_Pos       (14U)

+#define FDCAN_ILS_TEFFL_Msk       (0x1UL << FDCAN_ILS_TEFFL_Pos)               /*!< 0x00004000 */

+#define FDCAN_ILS_TEFFL           FDCAN_ILS_TEFFL_Msk                          /*!<Tx Event FIFO Full Line                     */

+#define FDCAN_ILS_TEFLL_Pos       (15U)

+#define FDCAN_ILS_TEFLL_Msk       (0x1UL << FDCAN_ILS_TEFLL_Pos)               /*!< 0x00008000 */

+#define FDCAN_ILS_TEFLL           FDCAN_ILS_TEFLL_Msk                          /*!<Tx Event FIFO Element Lost Line             */

+#define FDCAN_ILS_TSWL_Pos        (16U)

+#define FDCAN_ILS_TSWL_Msk        (0x1UL << FDCAN_ILS_TSWL_Pos)                /*!< 0x00010000 */

+#define FDCAN_ILS_TSWL            FDCAN_ILS_TSWL_Msk                           /*!<Timestamp Wraparound Line                   */

+#define FDCAN_ILS_MRAFE_Pos       (17U)

+#define FDCAN_ILS_MRAFE_Msk       (0x1UL << FDCAN_ILS_MRAFE_Pos)               /*!< 0x00020000 */

+#define FDCAN_ILS_MRAFE           FDCAN_ILS_MRAFE_Msk                          /*!<Message RAM Access Failure Line             */

+#define FDCAN_ILS_TOOE_Pos        (18U)

+#define FDCAN_ILS_TOOE_Msk        (0x1UL << FDCAN_ILS_TOOE_Pos)                /*!< 0x00040000 */

+#define FDCAN_ILS_TOOE            FDCAN_ILS_TOOE_Msk                           /*!<Timeout Occurred Line                       */

+#define FDCAN_ILS_DRXE_Pos        (19U)

+#define FDCAN_ILS_DRXE_Msk        (0x1UL << FDCAN_ILS_DRXE_Pos)                /*!< 0x00080000 */

+#define FDCAN_ILS_DRXE            FDCAN_ILS_DRXE_Msk                           /*!<Message stored to Dedicated Rx Buffer Line  */

+#define FDCAN_ILS_BECE_Pos        (20U)

+#define FDCAN_ILS_BECE_Msk        (0x1UL << FDCAN_ILS_BECE_Pos)                /*!< 0x00100000 */

+#define FDCAN_ILS_BECE            FDCAN_ILS_BECE_Msk                           /*!<Bit Error Corrected Interrupt Line          */

+#define FDCAN_ILS_BEUE_Pos        (21U)

+#define FDCAN_ILS_BEUE_Msk        (0x1UL << FDCAN_ILS_BEUE_Pos)                /*!< 0x00200000 */

+#define FDCAN_ILS_BEUE            FDCAN_ILS_BEUE_Msk                           /*!<Bit Error Uncorrected Interrupt Line        */

+#define FDCAN_ILS_ELOE_Pos        (22U)

+#define FDCAN_ILS_ELOE_Msk        (0x1UL << FDCAN_ILS_ELOE_Pos)                /*!< 0x00400000 */

+#define FDCAN_ILS_ELOE            FDCAN_ILS_ELOE_Msk                           /*!<Error Logging Overflow Line                 */

+#define FDCAN_ILS_EPE_Pos         (23U)

+#define FDCAN_ILS_EPE_Msk         (0x1UL << FDCAN_ILS_EPE_Pos)                 /*!< 0x00800000 */

+#define FDCAN_ILS_EPE             FDCAN_ILS_EPE_Msk                            /*!<Error Passive Line                          */

+#define FDCAN_ILS_EWE_Pos         (24U)

+#define FDCAN_ILS_EWE_Msk         (0x1UL << FDCAN_ILS_EWE_Pos)                 /*!< 0x01000000 */

+#define FDCAN_ILS_EWE             FDCAN_ILS_EWE_Msk                            /*!<Warning Status Line                         */

+#define FDCAN_ILS_BOE_Pos         (25U)

+#define FDCAN_ILS_BOE_Msk         (0x1UL << FDCAN_ILS_BOE_Pos)                 /*!< 0x02000000 */

+#define FDCAN_ILS_BOE             FDCAN_ILS_BOE_Msk                            /*!<Bus_Off Status Line                         */

+#define FDCAN_ILS_WDIE_Pos        (26U)

+#define FDCAN_ILS_WDIE_Msk        (0x1UL << FDCAN_ILS_WDIE_Pos)                /*!< 0x04000000 */

+#define FDCAN_ILS_WDIE            FDCAN_ILS_WDIE_Msk                           /*!<Watchdog Interrupt Line                     */

+#define FDCAN_ILS_PEAE_Pos        (27U)

+#define FDCAN_ILS_PEAE_Msk        (0x1UL << FDCAN_ILS_PEAE_Pos)                /*!< 0x08000000 */

+#define FDCAN_ILS_PEAE            FDCAN_ILS_PEAE_Msk                           /*!<Protocol Error in Arbitration Phase Line    */

+#define FDCAN_ILS_PEDE_Pos        (28U)

+#define FDCAN_ILS_PEDE_Msk        (0x1UL << FDCAN_ILS_PEDE_Pos)                /*!< 0x10000000 */

+#define FDCAN_ILS_PEDE            FDCAN_ILS_PEDE_Msk                           /*!<Protocol Error in Data Phase Line           */

+#define FDCAN_ILS_ARAE_Pos        (29U)

+#define FDCAN_ILS_ARAE_Msk        (0x1UL << FDCAN_ILS_ARAE_Pos)                /*!< 0x20000000 */

+#define FDCAN_ILS_ARAE            FDCAN_ILS_ARAE_Msk                           /*!<Access to Reserved Address Line             */

+

+/*****************  Bit definition for FDCAN_ILE register  **********************/

+#define FDCAN_ILE_EINT0_Pos       (0U)

+#define FDCAN_ILE_EINT0_Msk       (0x1UL << FDCAN_ILE_EINT0_Pos)               /*!< 0x00000001 */

+#define FDCAN_ILE_EINT0           FDCAN_ILE_EINT0_Msk                          /*!<Enable Interrupt Line 0                   */

+#define FDCAN_ILE_EINT1_Pos       (1U)

+#define FDCAN_ILE_EINT1_Msk       (0x1UL << FDCAN_ILE_EINT1_Pos)               /*!< 0x00000002 */

+#define FDCAN_ILE_EINT1           FDCAN_ILE_EINT1_Msk                          /*!<Enable Interrupt Line 1                   */

+

+/*****************  Bit definition for FDCAN_GFC register  **********************/

+#define FDCAN_GFC_RRFE_Pos        (0U)

+#define FDCAN_GFC_RRFE_Msk        (0x1UL << FDCAN_GFC_RRFE_Pos)                /*!< 0x00000001 */

+#define FDCAN_GFC_RRFE            FDCAN_GFC_RRFE_Msk                           /*!<Reject Remote Frames Extended             */

+#define FDCAN_GFC_RRFS_Pos        (1U)

+#define FDCAN_GFC_RRFS_Msk        (0x1UL << FDCAN_GFC_RRFS_Pos)                /*!< 0x00000002 */

+#define FDCAN_GFC_RRFS            FDCAN_GFC_RRFS_Msk                           /*!<Reject Remote Frames Standard             */

+#define FDCAN_GFC_ANFE_Pos        (2U)

+#define FDCAN_GFC_ANFE_Msk        (0x3UL << FDCAN_GFC_ANFE_Pos)                /*!< 0x0000000C */

+#define FDCAN_GFC_ANFE            FDCAN_GFC_ANFE_Msk                           /*!<Accept Non-matching Frames Extended       */

+#define FDCAN_GFC_ANFS_Pos        (4U)

+#define FDCAN_GFC_ANFS_Msk        (0x3UL << FDCAN_GFC_ANFS_Pos)                /*!< 0x00000030 */

+#define FDCAN_GFC_ANFS            FDCAN_GFC_ANFS_Msk                           /*!<Accept Non-matching Frames Standard       */

+

+/*****************  Bit definition for FDCAN_SIDFC register  ********************/

+#define FDCAN_SIDFC_FLSSA_Pos     (2U)

+#define FDCAN_SIDFC_FLSSA_Msk     (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)          /*!< 0x0000FFFC */

+#define FDCAN_SIDFC_FLSSA         FDCAN_SIDFC_FLSSA_Msk                        /*!<Filter List Standard Start Address        */

+#define FDCAN_SIDFC_LSS_Pos       (16U)

+#define FDCAN_SIDFC_LSS_Msk       (0xFFUL << FDCAN_SIDFC_LSS_Pos)              /*!< 0x00FF0000 */

+#define FDCAN_SIDFC_LSS           FDCAN_SIDFC_LSS_Msk                          /*!<List Size Standard                        */

+

+/*****************  Bit definition for FDCAN_XIDFC register  ********************/

+#define FDCAN_XIDFC_FLESA_Pos     (2U)

+#define FDCAN_XIDFC_FLESA_Msk     (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)          /*!< 0x0000FFFC */

+#define FDCAN_XIDFC_FLESA         FDCAN_XIDFC_FLESA_Msk                        /*!<Filter List Standard Start Address        */

+#define FDCAN_XIDFC_LSE_Pos       (16U)

+#define FDCAN_XIDFC_LSE_Msk       (0x7FUL << FDCAN_XIDFC_LSE_Pos)              /*!< 0x007F0000 */

+#define FDCAN_XIDFC_LSE           FDCAN_XIDFC_LSE_Msk                          /*!<List Size Extended                        */

+

+/*****************  Bit definition for FDCAN_XIDAM register  ********************/

+#define FDCAN_XIDAM_EIDM_Pos      (0U)

+#define FDCAN_XIDAM_EIDM_Msk      (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)       /*!< 0x1FFFFFFF */

+#define FDCAN_XIDAM_EIDM          FDCAN_XIDAM_EIDM_Msk                         /*!<Extended ID Mask                          */

+

+/*****************  Bit definition for FDCAN_HPMS register  *********************/

+#define FDCAN_HPMS_BIDX_Pos       (0U)

+#define FDCAN_HPMS_BIDX_Msk       (0x3FUL << FDCAN_HPMS_BIDX_Pos)              /*!< 0x0000003F */

+#define FDCAN_HPMS_BIDX           FDCAN_HPMS_BIDX_Msk                          /*!<Buffer Index                              */

+#define FDCAN_HPMS_MSI_Pos        (6U)

+#define FDCAN_HPMS_MSI_Msk        (0x3UL << FDCAN_HPMS_MSI_Pos)                /*!< 0x000000C0 */

+#define FDCAN_HPMS_MSI            FDCAN_HPMS_MSI_Msk                           /*!<Message Storage Indicator                 */

+#define FDCAN_HPMS_FIDX_Pos       (8U)

+#define FDCAN_HPMS_FIDX_Msk       (0x7FUL << FDCAN_HPMS_FIDX_Pos)              /*!< 0x00007F00 */

+#define FDCAN_HPMS_FIDX           FDCAN_HPMS_FIDX_Msk                          /*!<Filter Index                              */

+#define FDCAN_HPMS_FLST_Pos       (15U)

+#define FDCAN_HPMS_FLST_Msk       (0x1UL << FDCAN_HPMS_FLST_Pos)               /*!< 0x00008000 */

+#define FDCAN_HPMS_FLST           FDCAN_HPMS_FLST_Msk                          /*!<Filter List                               */

+

+/*****************  Bit definition for FDCAN_NDAT1 register  ********************/

+#define FDCAN_NDAT1_ND0_Pos       (0U)

+#define FDCAN_NDAT1_ND0_Msk       (0x1UL << FDCAN_NDAT1_ND0_Pos)               /*!< 0x00000001 */

+#define FDCAN_NDAT1_ND0           FDCAN_NDAT1_ND0_Msk                          /*!<New Data flag of Rx Buffer 0              */

+#define FDCAN_NDAT1_ND1_Pos       (1U)

+#define FDCAN_NDAT1_ND1_Msk       (0x1UL << FDCAN_NDAT1_ND1_Pos)               /*!< 0x00000002 */

+#define FDCAN_NDAT1_ND1           FDCAN_NDAT1_ND1_Msk                          /*!<New Data flag of Rx Buffer 1              */

+#define FDCAN_NDAT1_ND2_Pos       (2U)

+#define FDCAN_NDAT1_ND2_Msk       (0x1UL << FDCAN_NDAT1_ND2_Pos)               /*!< 0x00000004 */

+#define FDCAN_NDAT1_ND2           FDCAN_NDAT1_ND2_Msk                          /*!<New Data flag of Rx Buffer 2              */

+#define FDCAN_NDAT1_ND3_Pos       (3U)

+#define FDCAN_NDAT1_ND3_Msk       (0x1UL << FDCAN_NDAT1_ND3_Pos)               /*!< 0x00000008 */

+#define FDCAN_NDAT1_ND3           FDCAN_NDAT1_ND3_Msk                          /*!<New Data flag of Rx Buffer 3              */

+#define FDCAN_NDAT1_ND4_Pos       (4U)

+#define FDCAN_NDAT1_ND4_Msk       (0x1UL << FDCAN_NDAT1_ND4_Pos)               /*!< 0x00000010 */

+#define FDCAN_NDAT1_ND4           FDCAN_NDAT1_ND4_Msk                          /*!<New Data flag of Rx Buffer 4              */

+#define FDCAN_NDAT1_ND5_Pos       (5U)

+#define FDCAN_NDAT1_ND5_Msk       (0x1UL << FDCAN_NDAT1_ND5_Pos)               /*!< 0x00000020 */

+#define FDCAN_NDAT1_ND5           FDCAN_NDAT1_ND5_Msk                          /*!<New Data flag of Rx Buffer 5              */

+#define FDCAN_NDAT1_ND6_Pos       (6U)

+#define FDCAN_NDAT1_ND6_Msk       (0x1UL << FDCAN_NDAT1_ND6_Pos)               /*!< 0x00000040 */

+#define FDCAN_NDAT1_ND6           FDCAN_NDAT1_ND6_Msk                          /*!<New Data flag of Rx Buffer 6              */

+#define FDCAN_NDAT1_ND7_Pos       (7U)

+#define FDCAN_NDAT1_ND7_Msk       (0x1UL << FDCAN_NDAT1_ND7_Pos)               /*!< 0x00000080 */

+#define FDCAN_NDAT1_ND7           FDCAN_NDAT1_ND7_Msk                          /*!<New Data flag of Rx Buffer 7              */

+#define FDCAN_NDAT1_ND8_Pos       (8U)

+#define FDCAN_NDAT1_ND8_Msk       (0x1UL << FDCAN_NDAT1_ND8_Pos)               /*!< 0x00000100 */

+#define FDCAN_NDAT1_ND8           FDCAN_NDAT1_ND8_Msk                          /*!<New Data flag of Rx Buffer 8              */

+#define FDCAN_NDAT1_ND9_Pos       (9U)

+#define FDCAN_NDAT1_ND9_Msk       (0x1UL << FDCAN_NDAT1_ND9_Pos)               /*!< 0x00000200 */

+#define FDCAN_NDAT1_ND9           FDCAN_NDAT1_ND9_Msk                          /*!<New Data flag of Rx Buffer 9              */

+#define FDCAN_NDAT1_ND10_Pos      (10U)

+#define FDCAN_NDAT1_ND10_Msk      (0x1UL << FDCAN_NDAT1_ND10_Pos)              /*!< 0x00000400 */

+#define FDCAN_NDAT1_ND10          FDCAN_NDAT1_ND10_Msk                         /*!<New Data flag of Rx Buffer 10             */

+#define FDCAN_NDAT1_ND11_Pos      (11U)

+#define FDCAN_NDAT1_ND11_Msk      (0x1UL << FDCAN_NDAT1_ND11_Pos)              /*!< 0x00000800 */

+#define FDCAN_NDAT1_ND11          FDCAN_NDAT1_ND11_Msk                         /*!<New Data flag of Rx Buffer 11             */

+#define FDCAN_NDAT1_ND12_Pos      (12U)

+#define FDCAN_NDAT1_ND12_Msk      (0x1UL << FDCAN_NDAT1_ND12_Pos)              /*!< 0x00001000 */

+#define FDCAN_NDAT1_ND12          FDCAN_NDAT1_ND12_Msk                         /*!<New Data flag of Rx Buffer 12             */

+#define FDCAN_NDAT1_ND13_Pos      (13U)

+#define FDCAN_NDAT1_ND13_Msk      (0x1UL << FDCAN_NDAT1_ND13_Pos)              /*!< 0x00002000 */

+#define FDCAN_NDAT1_ND13          FDCAN_NDAT1_ND13_Msk                         /*!<New Data flag of Rx Buffer 13             */

+#define FDCAN_NDAT1_ND14_Pos      (14U)

+#define FDCAN_NDAT1_ND14_Msk      (0x1UL << FDCAN_NDAT1_ND14_Pos)              /*!< 0x00004000 */

+#define FDCAN_NDAT1_ND14          FDCAN_NDAT1_ND14_Msk                         /*!<New Data flag of Rx Buffer 14             */

+#define FDCAN_NDAT1_ND15_Pos      (15U)

+#define FDCAN_NDAT1_ND15_Msk      (0x1UL << FDCAN_NDAT1_ND15_Pos)              /*!< 0x00008000 */

+#define FDCAN_NDAT1_ND15          FDCAN_NDAT1_ND15_Msk                         /*!<New Data flag of Rx Buffer 15             */

+#define FDCAN_NDAT1_ND16_Pos      (16U)

+#define FDCAN_NDAT1_ND16_Msk      (0x1UL << FDCAN_NDAT1_ND16_Pos)              /*!< 0x00010000 */

+#define FDCAN_NDAT1_ND16          FDCAN_NDAT1_ND16_Msk                         /*!<New Data flag of Rx Buffer 16             */

+#define FDCAN_NDAT1_ND17_Pos      (17U)

+#define FDCAN_NDAT1_ND17_Msk      (0x1UL << FDCAN_NDAT1_ND17_Pos)              /*!< 0x00020000 */

+#define FDCAN_NDAT1_ND17          FDCAN_NDAT1_ND17_Msk                         /*!<New Data flag of Rx Buffer 17             */

+#define FDCAN_NDAT1_ND18_Pos      (18U)

+#define FDCAN_NDAT1_ND18_Msk      (0x1UL << FDCAN_NDAT1_ND18_Pos)              /*!< 0x00040000 */

+#define FDCAN_NDAT1_ND18          FDCAN_NDAT1_ND18_Msk                         /*!<New Data flag of Rx Buffer 18             */

+#define FDCAN_NDAT1_ND19_Pos      (19U)

+#define FDCAN_NDAT1_ND19_Msk      (0x1UL << FDCAN_NDAT1_ND19_Pos)              /*!< 0x00080000 */

+#define FDCAN_NDAT1_ND19          FDCAN_NDAT1_ND19_Msk                         /*!<New Data flag of Rx Buffer 19             */

+#define FDCAN_NDAT1_ND20_Pos      (20U)

+#define FDCAN_NDAT1_ND20_Msk      (0x1UL << FDCAN_NDAT1_ND20_Pos)              /*!< 0x00100000 */

+#define FDCAN_NDAT1_ND20          FDCAN_NDAT1_ND20_Msk                         /*!<New Data flag of Rx Buffer 20             */

+#define FDCAN_NDAT1_ND21_Pos      (21U)

+#define FDCAN_NDAT1_ND21_Msk      (0x1UL << FDCAN_NDAT1_ND21_Pos)              /*!< 0x00200000 */

+#define FDCAN_NDAT1_ND21          FDCAN_NDAT1_ND21_Msk                         /*!<New Data flag of Rx Buffer 21             */

+#define FDCAN_NDAT1_ND22_Pos      (22U)

+#define FDCAN_NDAT1_ND22_Msk      (0x1UL << FDCAN_NDAT1_ND22_Pos)              /*!< 0x00400000 */

+#define FDCAN_NDAT1_ND22          FDCAN_NDAT1_ND22_Msk                         /*!<New Data flag of Rx Buffer 22             */

+#define FDCAN_NDAT1_ND23_Pos      (23U)

+#define FDCAN_NDAT1_ND23_Msk      (0x1UL << FDCAN_NDAT1_ND23_Pos)              /*!< 0x00800000 */

+#define FDCAN_NDAT1_ND23          FDCAN_NDAT1_ND23_Msk                         /*!<New Data flag of Rx Buffer 23             */

+#define FDCAN_NDAT1_ND24_Pos      (24U)

+#define FDCAN_NDAT1_ND24_Msk      (0x1UL << FDCAN_NDAT1_ND24_Pos)              /*!< 0x01000000 */

+#define FDCAN_NDAT1_ND24          FDCAN_NDAT1_ND24_Msk                         /*!<New Data flag of Rx Buffer 24             */

+#define FDCAN_NDAT1_ND25_Pos      (25U)

+#define FDCAN_NDAT1_ND25_Msk      (0x1UL << FDCAN_NDAT1_ND25_Pos)              /*!< 0x02000000 */

+#define FDCAN_NDAT1_ND25          FDCAN_NDAT1_ND25_Msk                         /*!<New Data flag of Rx Buffer 25             */

+#define FDCAN_NDAT1_ND26_Pos      (26U)

+#define FDCAN_NDAT1_ND26_Msk      (0x1UL << FDCAN_NDAT1_ND26_Pos)              /*!< 0x04000000 */

+#define FDCAN_NDAT1_ND26          FDCAN_NDAT1_ND26_Msk                         /*!<New Data flag of Rx Buffer 26             */

+#define FDCAN_NDAT1_ND27_Pos      (27U)

+#define FDCAN_NDAT1_ND27_Msk      (0x1UL << FDCAN_NDAT1_ND27_Pos)              /*!< 0x08000000 */

+#define FDCAN_NDAT1_ND27          FDCAN_NDAT1_ND27_Msk                         /*!<New Data flag of Rx Buffer 27             */

+#define FDCAN_NDAT1_ND28_Pos      (28U)

+#define FDCAN_NDAT1_ND28_Msk      (0x1UL << FDCAN_NDAT1_ND28_Pos)              /*!< 0x10000000 */

+#define FDCAN_NDAT1_ND28          FDCAN_NDAT1_ND28_Msk                         /*!<New Data flag of Rx Buffer 28             */

+#define FDCAN_NDAT1_ND29_Pos      (29U)

+#define FDCAN_NDAT1_ND29_Msk      (0x1UL << FDCAN_NDAT1_ND29_Pos)              /*!< 0x20000000 */

+#define FDCAN_NDAT1_ND29          FDCAN_NDAT1_ND29_Msk                         /*!<New Data flag of Rx Buffer 29             */

+#define FDCAN_NDAT1_ND30_Pos      (30U)

+#define FDCAN_NDAT1_ND30_Msk      (0x1UL << FDCAN_NDAT1_ND30_Pos)              /*!< 0x40000000 */

+#define FDCAN_NDAT1_ND30          FDCAN_NDAT1_ND30_Msk                         /*!<New Data flag of Rx Buffer 30             */

+#define FDCAN_NDAT1_ND31_Pos      (31U)

+#define FDCAN_NDAT1_ND31_Msk      (0x1UL << FDCAN_NDAT1_ND31_Pos)              /*!< 0x80000000 */

+#define FDCAN_NDAT1_ND31          FDCAN_NDAT1_ND31_Msk                         /*!<New Data flag of Rx Buffer 31             */

+

+/*****************  Bit definition for FDCAN_NDAT2 register  ********************/

+#define FDCAN_NDAT2_ND32_Pos      (0U)

+#define FDCAN_NDAT2_ND32_Msk      (0x1UL << FDCAN_NDAT2_ND32_Pos)              /*!< 0x00000001 */

+#define FDCAN_NDAT2_ND32          FDCAN_NDAT2_ND32_Msk                         /*!<New Data flag of Rx Buffer 32             */

+#define FDCAN_NDAT2_ND33_Pos      (1U)

+#define FDCAN_NDAT2_ND33_Msk      (0x1UL << FDCAN_NDAT2_ND33_Pos)              /*!< 0x00000002 */

+#define FDCAN_NDAT2_ND33          FDCAN_NDAT2_ND33_Msk                         /*!<New Data flag of Rx Buffer 33             */

+#define FDCAN_NDAT2_ND34_Pos      (2U)

+#define FDCAN_NDAT2_ND34_Msk      (0x1UL << FDCAN_NDAT2_ND34_Pos)              /*!< 0x00000004 */

+#define FDCAN_NDAT2_ND34          FDCAN_NDAT2_ND34_Msk                         /*!<New Data flag of Rx Buffer 34             */

+#define FDCAN_NDAT2_ND35_Pos      (3U)

+#define FDCAN_NDAT2_ND35_Msk      (0x1UL << FDCAN_NDAT2_ND35_Pos)              /*!< 0x00000008 */

+#define FDCAN_NDAT2_ND35          FDCAN_NDAT2_ND35_Msk                         /*!<New Data flag of Rx Buffer 35             */

+#define FDCAN_NDAT2_ND36_Pos      (4U)

+#define FDCAN_NDAT2_ND36_Msk      (0x1UL << FDCAN_NDAT2_ND36_Pos)              /*!< 0x00000010 */

+#define FDCAN_NDAT2_ND36          FDCAN_NDAT2_ND36_Msk                         /*!<New Data flag of Rx Buffer 36             */

+#define FDCAN_NDAT2_ND37_Pos      (5U)

+#define FDCAN_NDAT2_ND37_Msk      (0x1UL << FDCAN_NDAT2_ND37_Pos)              /*!< 0x00000020 */

+#define FDCAN_NDAT2_ND37          FDCAN_NDAT2_ND37_Msk                         /*!<New Data flag of Rx Buffer 37             */

+#define FDCAN_NDAT2_ND38_Pos      (6U)

+#define FDCAN_NDAT2_ND38_Msk      (0x1UL << FDCAN_NDAT2_ND38_Pos)              /*!< 0x00000040 */

+#define FDCAN_NDAT2_ND38          FDCAN_NDAT2_ND38_Msk                         /*!<New Data flag of Rx Buffer 38             */

+#define FDCAN_NDAT2_ND39_Pos      (7U)

+#define FDCAN_NDAT2_ND39_Msk      (0x1UL << FDCAN_NDAT2_ND39_Pos)              /*!< 0x00000080 */

+#define FDCAN_NDAT2_ND39          FDCAN_NDAT2_ND39_Msk                         /*!<New Data flag of Rx Buffer 39             */

+#define FDCAN_NDAT2_ND40_Pos      (8U)

+#define FDCAN_NDAT2_ND40_Msk      (0x1UL << FDCAN_NDAT2_ND40_Pos)              /*!< 0x00000100 */

+#define FDCAN_NDAT2_ND40          FDCAN_NDAT2_ND40_Msk                         /*!<New Data flag of Rx Buffer 40             */

+#define FDCAN_NDAT2_ND41_Pos      (9U)

+#define FDCAN_NDAT2_ND41_Msk      (0x1UL << FDCAN_NDAT2_ND41_Pos)              /*!< 0x00000200 */

+#define FDCAN_NDAT2_ND41          FDCAN_NDAT2_ND41_Msk                         /*!<New Data flag of Rx Buffer 41             */

+#define FDCAN_NDAT2_ND42_Pos      (10U)

+#define FDCAN_NDAT2_ND42_Msk      (0x1UL << FDCAN_NDAT2_ND42_Pos)              /*!< 0x00000400 */

+#define FDCAN_NDAT2_ND42          FDCAN_NDAT2_ND42_Msk                         /*!<New Data flag of Rx Buffer 42             */

+#define FDCAN_NDAT2_ND43_Pos      (11U)

+#define FDCAN_NDAT2_ND43_Msk      (0x1UL << FDCAN_NDAT2_ND43_Pos)              /*!< 0x00000800 */

+#define FDCAN_NDAT2_ND43          FDCAN_NDAT2_ND43_Msk                         /*!<New Data flag of Rx Buffer 43             */

+#define FDCAN_NDAT2_ND44_Pos      (12U)

+#define FDCAN_NDAT2_ND44_Msk      (0x1UL << FDCAN_NDAT2_ND44_Pos)              /*!< 0x00001000 */

+#define FDCAN_NDAT2_ND44          FDCAN_NDAT2_ND44_Msk                         /*!<New Data flag of Rx Buffer 44             */

+#define FDCAN_NDAT2_ND45_Pos      (13U)

+#define FDCAN_NDAT2_ND45_Msk      (0x1UL << FDCAN_NDAT2_ND45_Pos)              /*!< 0x00002000 */

+#define FDCAN_NDAT2_ND45          FDCAN_NDAT2_ND45_Msk                         /*!<New Data flag of Rx Buffer 45             */

+#define FDCAN_NDAT2_ND46_Pos      (14U)

+#define FDCAN_NDAT2_ND46_Msk      (0x1UL << FDCAN_NDAT2_ND46_Pos)              /*!< 0x00004000 */

+#define FDCAN_NDAT2_ND46          FDCAN_NDAT2_ND46_Msk                         /*!<New Data flag of Rx Buffer 46             */

+#define FDCAN_NDAT2_ND47_Pos      (15U)

+#define FDCAN_NDAT2_ND47_Msk      (0x1UL << FDCAN_NDAT2_ND47_Pos)              /*!< 0x00008000 */

+#define FDCAN_NDAT2_ND47          FDCAN_NDAT2_ND47_Msk                         /*!<New Data flag of Rx Buffer 47             */

+#define FDCAN_NDAT2_ND48_Pos      (16U)

+#define FDCAN_NDAT2_ND48_Msk      (0x1UL << FDCAN_NDAT2_ND48_Pos)              /*!< 0x00010000 */

+#define FDCAN_NDAT2_ND48          FDCAN_NDAT2_ND48_Msk                         /*!<New Data flag of Rx Buffer 48             */

+#define FDCAN_NDAT2_ND49_Pos      (17U)

+#define FDCAN_NDAT2_ND49_Msk      (0x1UL << FDCAN_NDAT2_ND49_Pos)              /*!< 0x00020000 */

+#define FDCAN_NDAT2_ND49          FDCAN_NDAT2_ND49_Msk                         /*!<New Data flag of Rx Buffer 49             */

+#define FDCAN_NDAT2_ND50_Pos      (18U)

+#define FDCAN_NDAT2_ND50_Msk      (0x1UL << FDCAN_NDAT2_ND50_Pos)              /*!< 0x00040000 */

+#define FDCAN_NDAT2_ND50          FDCAN_NDAT2_ND50_Msk                         /*!<New Data flag of Rx Buffer 50             */

+#define FDCAN_NDAT2_ND51_Pos      (19U)

+#define FDCAN_NDAT2_ND51_Msk      (0x1UL << FDCAN_NDAT2_ND51_Pos)              /*!< 0x00080000 */

+#define FDCAN_NDAT2_ND51          FDCAN_NDAT2_ND51_Msk                         /*!<New Data flag of Rx Buffer 51             */

+#define FDCAN_NDAT2_ND52_Pos      (20U)

+#define FDCAN_NDAT2_ND52_Msk      (0x1UL << FDCAN_NDAT2_ND52_Pos)              /*!< 0x00100000 */

+#define FDCAN_NDAT2_ND52          FDCAN_NDAT2_ND52_Msk                         /*!<New Data flag of Rx Buffer 52             */

+#define FDCAN_NDAT2_ND53_Pos      (21U)

+#define FDCAN_NDAT2_ND53_Msk      (0x1UL << FDCAN_NDAT2_ND53_Pos)              /*!< 0x00200000 */

+#define FDCAN_NDAT2_ND53          FDCAN_NDAT2_ND53_Msk                         /*!<New Data flag of Rx Buffer 53             */

+#define FDCAN_NDAT2_ND54_Pos      (22U)

+#define FDCAN_NDAT2_ND54_Msk      (0x1UL << FDCAN_NDAT2_ND54_Pos)              /*!< 0x00400000 */

+#define FDCAN_NDAT2_ND54          FDCAN_NDAT2_ND54_Msk                         /*!<New Data flag of Rx Buffer 54             */

+#define FDCAN_NDAT2_ND55_Pos      (23U)

+#define FDCAN_NDAT2_ND55_Msk      (0x1UL << FDCAN_NDAT2_ND55_Pos)              /*!< 0x00800000 */

+#define FDCAN_NDAT2_ND55          FDCAN_NDAT2_ND55_Msk                         /*!<New Data flag of Rx Buffer 55             */

+#define FDCAN_NDAT2_ND56_Pos      (24U)

+#define FDCAN_NDAT2_ND56_Msk      (0x1UL << FDCAN_NDAT2_ND56_Pos)              /*!< 0x01000000 */

+#define FDCAN_NDAT2_ND56          FDCAN_NDAT2_ND56_Msk                         /*!<New Data flag of Rx Buffer 56             */

+#define FDCAN_NDAT2_ND57_Pos      (25U)

+#define FDCAN_NDAT2_ND57_Msk      (0x1UL << FDCAN_NDAT2_ND57_Pos)              /*!< 0x02000000 */

+#define FDCAN_NDAT2_ND57          FDCAN_NDAT2_ND57_Msk                         /*!<New Data flag of Rx Buffer 57             */

+#define FDCAN_NDAT2_ND58_Pos      (26U)

+#define FDCAN_NDAT2_ND58_Msk      (0x1UL << FDCAN_NDAT2_ND58_Pos)              /*!< 0x04000000 */

+#define FDCAN_NDAT2_ND58          FDCAN_NDAT2_ND58_Msk                         /*!<New Data flag of Rx Buffer 58             */

+#define FDCAN_NDAT2_ND59_Pos      (27U)

+#define FDCAN_NDAT2_ND59_Msk      (0x1UL << FDCAN_NDAT2_ND59_Pos)              /*!< 0x08000000 */

+#define FDCAN_NDAT2_ND59          FDCAN_NDAT2_ND59_Msk                         /*!<New Data flag of Rx Buffer 59             */

+#define FDCAN_NDAT2_ND60_Pos      (28U)

+#define FDCAN_NDAT2_ND60_Msk      (0x1UL << FDCAN_NDAT2_ND60_Pos)              /*!< 0x10000000 */

+#define FDCAN_NDAT2_ND60          FDCAN_NDAT2_ND60_Msk                         /*!<New Data flag of Rx Buffer 60             */

+#define FDCAN_NDAT2_ND61_Pos      (29U)

+#define FDCAN_NDAT2_ND61_Msk      (0x1UL << FDCAN_NDAT2_ND61_Pos)              /*!< 0x20000000 */

+#define FDCAN_NDAT2_ND61          FDCAN_NDAT2_ND61_Msk                         /*!<New Data flag of Rx Buffer 61             */

+#define FDCAN_NDAT2_ND62_Pos      (30U)

+#define FDCAN_NDAT2_ND62_Msk      (0x1UL << FDCAN_NDAT2_ND62_Pos)              /*!< 0x40000000 */

+#define FDCAN_NDAT2_ND62          FDCAN_NDAT2_ND62_Msk                         /*!<New Data flag of Rx Buffer 62             */

+#define FDCAN_NDAT2_ND63_Pos      (31U)

+#define FDCAN_NDAT2_ND63_Msk      (0x1UL << FDCAN_NDAT2_ND63_Pos)              /*!< 0x80000000 */

+#define FDCAN_NDAT2_ND63          FDCAN_NDAT2_ND63_Msk                         /*!<New Data flag of Rx Buffer 63             */

+

+/*****************  Bit definition for FDCAN_RXF0C register  ********************/

+#define FDCAN_RXF0C_F0SA_Pos      (2U)

+#define FDCAN_RXF0C_F0SA_Msk      (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_RXF0C_F0SA          FDCAN_RXF0C_F0SA_Msk                         /*!<Rx FIFO 0 Start Address                   */

+#define FDCAN_RXF0C_F0S_Pos       (16U)

+#define FDCAN_RXF0C_F0S_Msk       (0x7FUL << FDCAN_RXF0C_F0S_Pos)              /*!< 0x007F0000 */

+#define FDCAN_RXF0C_F0S           FDCAN_RXF0C_F0S_Msk                          /*!<Number of Rx FIFO 0 elements              */

+#define FDCAN_RXF0C_F0WM_Pos      (24U)

+#define FDCAN_RXF0C_F0WM_Msk      (0x7FUL << FDCAN_RXF0C_F0WM_Pos)             /*!< 0x7F000000 */

+#define FDCAN_RXF0C_F0WM          FDCAN_RXF0C_F0WM_Msk                         /*!<FIFO 0 Watermark                          */

+#define FDCAN_RXF0C_F0OM_Pos      (31U)

+#define FDCAN_RXF0C_F0OM_Msk      (0x1UL << FDCAN_RXF0C_F0OM_Pos)              /*!< 0x80000000 */

+#define FDCAN_RXF0C_F0OM          FDCAN_RXF0C_F0OM_Msk                         /*!<FIFO 0 Operation Mode                     */

+

+/*****************  Bit definition for FDCAN_RXF0S register  ********************/

+#define FDCAN_RXF0S_F0FL_Pos      (0U)

+#define FDCAN_RXF0S_F0FL_Msk      (0x7FUL << FDCAN_RXF0S_F0FL_Pos)             /*!< 0x0000007F */

+#define FDCAN_RXF0S_F0FL          FDCAN_RXF0S_F0FL_Msk                         /*!<Rx FIFO 0 Fill Level                      */

+#define FDCAN_RXF0S_F0GI_Pos      (8U)

+#define FDCAN_RXF0S_F0GI_Msk      (0x3FUL << FDCAN_RXF0S_F0GI_Pos)             /*!< 0x00003F00 */

+#define FDCAN_RXF0S_F0GI          FDCAN_RXF0S_F0GI_Msk                         /*!<Rx FIFO 0 Get Index                       */

+#define FDCAN_RXF0S_F0PI_Pos      (16U)

+#define FDCAN_RXF0S_F0PI_Msk      (0x3FUL << FDCAN_RXF0S_F0PI_Pos)             /*!< 0x003F0000 */

+#define FDCAN_RXF0S_F0PI          FDCAN_RXF0S_F0PI_Msk                         /*!<Rx FIFO 0 Put Index                       */

+#define FDCAN_RXF0S_F0F_Pos       (24U)

+#define FDCAN_RXF0S_F0F_Msk       (0x1UL << FDCAN_RXF0S_F0F_Pos)               /*!< 0x01000000 */

+#define FDCAN_RXF0S_F0F           FDCAN_RXF0S_F0F_Msk                          /*!<Rx FIFO 0 Full                            */

+#define FDCAN_RXF0S_RF0L_Pos      (25U)

+#define FDCAN_RXF0S_RF0L_Msk      (0x1UL << FDCAN_RXF0S_RF0L_Pos)              /*!< 0x02000000 */

+#define FDCAN_RXF0S_RF0L          FDCAN_RXF0S_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                    */

+

+/*****************  Bit definition for FDCAN_RXF0A register  ********************/

+#define FDCAN_RXF0A_F0AI_Pos      (0U)

+#define FDCAN_RXF0A_F0AI_Msk      (0x3FUL << FDCAN_RXF0A_F0AI_Pos)             /*!< 0x0000003F */

+#define FDCAN_RXF0A_F0AI          FDCAN_RXF0A_F0AI_Msk                         /*!<Rx FIFO 0 Acknowledge Index               */

+

+/*****************  Bit definition for FDCAN_RXBC register  ********************/

+#define FDCAN_RXBC_RBSA_Pos       (2U)

+#define FDCAN_RXBC_RBSA_Msk       (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)            /*!< 0x0000FFFC */

+#define FDCAN_RXBC_RBSA           FDCAN_RXBC_RBSA_Msk                          /*!<Rx Buffer Start Address                   */

+

+/*****************  Bit definition for FDCAN_RXF1C register  ********************/

+#define FDCAN_RXF1C_F1SA_Pos      (2U)

+#define FDCAN_RXF1C_F1SA_Msk      (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_RXF1C_F1SA          FDCAN_RXF1C_F1SA_Msk                         /*!<Rx FIFO 1 Start Address                   */

+#define FDCAN_RXF1C_F1S_Pos       (16U)

+#define FDCAN_RXF1C_F1S_Msk       (0x7FUL << FDCAN_RXF1C_F1S_Pos)              /*!< 0x007F0000 */

+#define FDCAN_RXF1C_F1S           FDCAN_RXF1C_F1S_Msk                          /*!<Number of Rx FIFO 1 elements              */

+#define FDCAN_RXF1C_F1WM_Pos      (24U)

+#define FDCAN_RXF1C_F1WM_Msk      (0x7FUL << FDCAN_RXF1C_F1WM_Pos)             /*!< 0x7F000000 */

+#define FDCAN_RXF1C_F1WM          FDCAN_RXF1C_F1WM_Msk                         /*!<Rx FIFO 1 Watermark                       */

+#define FDCAN_RXF1C_F1OM_Pos      (31U)

+#define FDCAN_RXF1C_F1OM_Msk      (0x1UL << FDCAN_RXF1C_F1OM_Pos)              /*!< 0x80000000 */

+#define FDCAN_RXF1C_F1OM          FDCAN_RXF1C_F1OM_Msk                         /*!<FIFO 1 Operation Mode                     */

+

+/*****************  Bit definition for FDCAN_RXF1S register  ********************/

+#define FDCAN_RXF1S_F1FL_Pos      (0U)

+#define FDCAN_RXF1S_F1FL_Msk      (0x7FUL << FDCAN_RXF1S_F1FL_Pos)             /*!< 0x0000007F */

+#define FDCAN_RXF1S_F1FL          FDCAN_RXF1S_F1FL_Msk                         /*!<Rx FIFO 1 Fill Level                      */

+#define FDCAN_RXF1S_F1GI_Pos      (8U)

+#define FDCAN_RXF1S_F1GI_Msk      (0x3FUL << FDCAN_RXF1S_F1GI_Pos)             /*!< 0x00003F00 */

+#define FDCAN_RXF1S_F1GI          FDCAN_RXF1S_F1GI_Msk                         /*!<Rx FIFO 1 Get Index                       */

+#define FDCAN_RXF1S_F1PI_Pos      (16U)

+#define FDCAN_RXF1S_F1PI_Msk      (0x3FUL << FDCAN_RXF1S_F1PI_Pos)             /*!< 0x003F0000 */

+#define FDCAN_RXF1S_F1PI          FDCAN_RXF1S_F1PI_Msk                         /*!<Rx FIFO 1 Put Index                       */

+#define FDCAN_RXF1S_F1F_Pos       (24U)

+#define FDCAN_RXF1S_F1F_Msk       (0x1UL << FDCAN_RXF1S_F1F_Pos)               /*!< 0x01000000 */

+#define FDCAN_RXF1S_F1F           FDCAN_RXF1S_F1F_Msk                          /*!<Rx FIFO 1 Full                            */

+#define FDCAN_RXF1S_RF1L_Pos      (25U)

+#define FDCAN_RXF1S_RF1L_Msk      (0x1UL << FDCAN_RXF1S_RF1L_Pos)              /*!< 0x02000000 */

+#define FDCAN_RXF1S_RF1L          FDCAN_RXF1S_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                    */

+

+/*****************  Bit definition for FDCAN_RXF1A register  ********************/

+#define FDCAN_RXF1A_F1AI_Pos      (0U)

+#define FDCAN_RXF1A_F1AI_Msk      (0x3FUL << FDCAN_RXF1A_F1AI_Pos)             /*!< 0x0000003F */

+#define FDCAN_RXF1A_F1AI          FDCAN_RXF1A_F1AI_Msk                         /*!<Rx FIFO 1 Acknowledge Index               */

+

+/*****************  Bit definition for FDCAN_RXESC register  ********************/

+#define FDCAN_RXESC_F0DS_Pos      (0U)

+#define FDCAN_RXESC_F0DS_Msk      (0x7UL << FDCAN_RXESC_F0DS_Pos)              /*!< 0x00000007 */

+#define FDCAN_RXESC_F0DS          FDCAN_RXESC_F0DS_Msk                         /*!<Rx FIFO 1 Data Field Size                 */

+#define FDCAN_RXESC_F1DS_Pos      (4U)

+#define FDCAN_RXESC_F1DS_Msk      (0x7UL << FDCAN_RXESC_F1DS_Pos)              /*!< 0x00000070 */

+#define FDCAN_RXESC_F1DS          FDCAN_RXESC_F1DS_Msk                         /*!<Rx FIFO 0 Data Field Size                 */

+#define FDCAN_RXESC_RBDS_Pos      (8U)

+#define FDCAN_RXESC_RBDS_Msk      (0x7UL << FDCAN_RXESC_RBDS_Pos)              /*!< 0x00000700 */

+#define FDCAN_RXESC_RBDS          FDCAN_RXESC_RBDS_Msk                         /*!<Rx Buffer Data Field Size                 */

+

+/*****************  Bit definition for FDCAN_TXBC register  *********************/

+#define FDCAN_TXBC_TBSA_Pos       (2U)

+#define FDCAN_TXBC_TBSA_Msk       (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)            /*!< 0x0000FFFC */

+#define FDCAN_TXBC_TBSA           FDCAN_TXBC_TBSA_Msk                          /*!<Tx Buffers Start Address                  */

+#define FDCAN_TXBC_NDTB_Pos       (16U)

+#define FDCAN_TXBC_NDTB_Msk       (0x3FUL << FDCAN_TXBC_NDTB_Pos)              /*!< 0x003F0000 */

+#define FDCAN_TXBC_NDTB           FDCAN_TXBC_NDTB_Msk                          /*!<Number of Dedicated Transmit Buffers      */

+#define FDCAN_TXBC_TFQS_Pos       (24U)

+#define FDCAN_TXBC_TFQS_Msk       (0x3FUL << FDCAN_TXBC_TFQS_Pos)              /*!< 0x3F000000 */

+#define FDCAN_TXBC_TFQS           FDCAN_TXBC_TFQS_Msk                          /*!<Transmit FIFO/Queue Size                  */

+#define FDCAN_TXBC_TFQM_Pos       (30U)

+#define FDCAN_TXBC_TFQM_Msk       (0x1UL << FDCAN_TXBC_TFQM_Pos)               /*!< 0x40000000 */

+#define FDCAN_TXBC_TFQM           FDCAN_TXBC_TFQM_Msk                          /*!<Tx FIFO/Queue Mode                        */

+

+/*****************  Bit definition for FDCAN_TXFQS register  *********************/

+#define FDCAN_TXFQS_TFFL_Pos      (0U)

+#define FDCAN_TXFQS_TFFL_Msk      (0x3FUL << FDCAN_TXFQS_TFFL_Pos)             /*!< 0x0000003F */

+#define FDCAN_TXFQS_TFFL          FDCAN_TXFQS_TFFL_Msk                         /*!<Tx FIFO Free Level                        */

+#define FDCAN_TXFQS_TFGI_Pos      (8U)

+#define FDCAN_TXFQS_TFGI_Msk      (0x1FUL << FDCAN_TXFQS_TFGI_Pos)             /*!< 0x00001F00 */

+#define FDCAN_TXFQS_TFGI          FDCAN_TXFQS_TFGI_Msk                         /*!<Tx FIFO Get Index                         */

+#define FDCAN_TXFQS_TFQPI_Pos     (16U)

+#define FDCAN_TXFQS_TFQPI_Msk     (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)            /*!< 0x001F0000 */

+#define FDCAN_TXFQS_TFQPI         FDCAN_TXFQS_TFQPI_Msk                        /*!<Tx FIFO/Queue Put Index                   */

+#define FDCAN_TXFQS_TFQF_Pos      (21U)

+#define FDCAN_TXFQS_TFQF_Msk      (0x1UL << FDCAN_TXFQS_TFQF_Pos)              /*!< 0x00200000 */

+#define FDCAN_TXFQS_TFQF          FDCAN_TXFQS_TFQF_Msk                         /*!<Tx FIFO/Queue Full                        */

+

+/*****************  Bit definition for FDCAN_TXESC register  *********************/

+#define FDCAN_TXESC_TBDS_Pos      (0U)

+#define FDCAN_TXESC_TBDS_Msk      (0x7UL << FDCAN_TXESC_TBDS_Pos)              /*!< 0x00000007 */

+#define FDCAN_TXESC_TBDS          FDCAN_TXESC_TBDS_Msk                         /*!<Tx Buffer Data Field Size                 */

+

+/*****************  Bit definition for FDCAN_TXBRP register  *********************/

+#define FDCAN_TXBRP_TRP_Pos       (0U)

+#define FDCAN_TXBRP_TRP_Msk       (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)        /*!< 0xFFFFFFFF */

+#define FDCAN_TXBRP_TRP           FDCAN_TXBRP_TRP_Msk                          /*!<Transmission Request Pending              */

+

+/*****************  Bit definition for FDCAN_TXBAR register  *********************/

+#define FDCAN_TXBAR_AR_Pos        (0U)

+#define FDCAN_TXBAR_AR_Msk        (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBAR_AR            FDCAN_TXBAR_AR_Msk                           /*!<Add Request                               */

+

+/*****************  Bit definition for FDCAN_TXBCR register  *********************/

+#define FDCAN_TXBCR_CR_Pos        (0U)

+#define FDCAN_TXBCR_CR_Msk        (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCR_CR            FDCAN_TXBCR_CR_Msk                           /*!<Cancellation Request                      */

+

+/*****************  Bit definition for FDCAN_TXBTO register  *********************/

+#define FDCAN_TXBTO_TO_Pos        (0U)

+#define FDCAN_TXBTO_TO_Msk        (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBTO_TO            FDCAN_TXBTO_TO_Msk                           /*!<Transmission Occurred                     */

+

+/*****************  Bit definition for FDCAN_TXBCF register  *********************/

+#define FDCAN_TXBCF_CF_Pos        (0U)

+#define FDCAN_TXBCF_CF_Msk        (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCF_CF            FDCAN_TXBCF_CF_Msk                           /*!<Cancellation Finished                     */

+

+/*****************  Bit definition for FDCAN_TXBTIE register  ********************/

+#define FDCAN_TXBTIE_TIE_Pos      (0U)

+#define FDCAN_TXBTIE_TIE_Msk      (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)       /*!< 0xFFFFFFFF */

+#define FDCAN_TXBTIE_TIE          FDCAN_TXBTIE_TIE_Msk                         /*!<Transmission Interrupt Enable             */

+

+/*****************  Bit definition for FDCAN_ TXBCIE register  *******************/

+#define FDCAN_TXBCIE_CFIE_Pos     (0U)

+#define FDCAN_TXBCIE_CFIE_Msk     (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)      /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCIE_CFIE         FDCAN_TXBCIE_CFIE_Msk                        /*!<Cancellation Finished Interrupt Enable    */

+

+/*****************  Bit definition for FDCAN_TXEFC register  *********************/

+#define FDCAN_TXEFC_EFSA_Pos      (2U)

+#define FDCAN_TXEFC_EFSA_Msk      (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_TXEFC_EFSA          FDCAN_TXEFC_EFSA_Msk                         /*!<Event FIFO Start Address                  */

+#define FDCAN_TXEFC_EFS_Pos       (16U)

+#define FDCAN_TXEFC_EFS_Msk       (0x3FUL << FDCAN_TXEFC_EFS_Pos)              /*!< 0x003F0000 */

+#define FDCAN_TXEFC_EFS           FDCAN_TXEFC_EFS_Msk                          /*!<Event FIFO Size                           */

+#define FDCAN_TXEFC_EFWM_Pos      (24U)

+#define FDCAN_TXEFC_EFWM_Msk      (0x3FUL << FDCAN_TXEFC_EFWM_Pos)             /*!< 0x3F000000 */

+#define FDCAN_TXEFC_EFWM          FDCAN_TXEFC_EFWM_Msk                         /*!<Event FIFO Watermark                      */

+

+/*****************  Bit definition for FDCAN_TXEFS register  *********************/

+#define FDCAN_TXEFS_EFFL_Pos      (0U)

+#define FDCAN_TXEFS_EFFL_Msk      (0x3FUL << FDCAN_TXEFS_EFFL_Pos)             /*!< 0x0000003F */

+#define FDCAN_TXEFS_EFFL          FDCAN_TXEFS_EFFL_Msk                         /*!<Event FIFO Fill Level                     */

+#define FDCAN_TXEFS_EFGI_Pos      (8U)

+#define FDCAN_TXEFS_EFGI_Msk      (0x1FUL << FDCAN_TXEFS_EFGI_Pos)             /*!< 0x00001F00 */

+#define FDCAN_TXEFS_EFGI          FDCAN_TXEFS_EFGI_Msk                         /*!<Event FIFO Get Index                      */

+#define FDCAN_TXEFS_EFPI_Pos      (16U)

+#define FDCAN_TXEFS_EFPI_Msk      (0x1FUL << FDCAN_TXEFS_EFPI_Pos)             /*!< 0x001F0000 */

+#define FDCAN_TXEFS_EFPI          FDCAN_TXEFS_EFPI_Msk                         /*!<Event FIFO Put Index                      */

+#define FDCAN_TXEFS_EFF_Pos       (24U)

+#define FDCAN_TXEFS_EFF_Msk       (0x1UL << FDCAN_TXEFS_EFF_Pos)               /*!< 0x01000000 */

+#define FDCAN_TXEFS_EFF           FDCAN_TXEFS_EFF_Msk                          /*!<Event FIFO Full                           */

+#define FDCAN_TXEFS_TEFL_Pos      (25U)

+#define FDCAN_TXEFS_TEFL_Msk      (0x1UL << FDCAN_TXEFS_TEFL_Pos)              /*!< 0x02000000 */

+#define FDCAN_TXEFS_TEFL          FDCAN_TXEFS_TEFL_Msk                         /*!<Tx Event FIFO Element Lost                */

+

+/*****************  Bit definition for FDCAN_TXEFA register  *********************/

+#define FDCAN_TXEFA_EFAI_Pos      (0U)

+#define FDCAN_TXEFA_EFAI_Msk      (0x1FUL << FDCAN_TXEFA_EFAI_Pos)             /*!< 0x0000001F */

+#define FDCAN_TXEFA_EFAI          FDCAN_TXEFA_EFAI_Msk                         /*!<Event FIFO Acknowledge Index              */

+

+/*****************  Bit definition for FDCAN_TTTMC register  *********************/

+#define FDCAN_TTTMC_TMSA_Pos      (2U)

+#define FDCAN_TTTMC_TMSA_Msk      (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_TTTMC_TMSA          FDCAN_TTTMC_TMSA_Msk                         /*!<Trigger Memory Start Address              */

+#define FDCAN_TTTMC_TME_Pos       (16U)

+#define FDCAN_TTTMC_TME_Msk       (0x7FUL << FDCAN_TTTMC_TME_Pos)              /*!< 0x007F0000 */

+#define FDCAN_TTTMC_TME           FDCAN_TTTMC_TME_Msk                          /*!<Trigger Memory Elements                   */

+

+/*****************  Bit definition for FDCAN_TTRMC register  *********************/

+#define FDCAN_TTRMC_RID_Pos       (0U)

+#define FDCAN_TTRMC_RID_Msk       (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)        /*!< 0x1FFFFFFF */

+#define FDCAN_TTRMC_RID           FDCAN_TTRMC_RID_Msk                          /*!<Reference Identifier                      */

+#define FDCAN_TTRMC_XTD_Pos       (30U)

+#define FDCAN_TTRMC_XTD_Msk       (0x1UL << FDCAN_TTRMC_XTD_Pos)               /*!< 0x40000000 */

+#define FDCAN_TTRMC_XTD           FDCAN_TTRMC_XTD_Msk                          /*!< Extended Identifier                      */

+#define FDCAN_TTRMC_RMPS_Pos      (31U)

+#define FDCAN_TTRMC_RMPS_Msk      (0x1UL << FDCAN_TTRMC_RMPS_Pos)              /*!< 0x80000000 */

+#define FDCAN_TTRMC_RMPS          FDCAN_TTRMC_RMPS_Msk                         /*!<Reference Message Payload Select          */

+

+/*****************  Bit definition for FDCAN_TTOCF register  *********************/

+#define FDCAN_TTOCF_OM_Pos        (0U)

+#define FDCAN_TTOCF_OM_Msk        (0x3UL << FDCAN_TTOCF_OM_Pos)                /*!< 0x00000003 */

+#define FDCAN_TTOCF_OM            FDCAN_TTOCF_OM_Msk                           /*!<Operation Mode                            */

+#define FDCAN_TTOCF_GEN_Pos       (3U)

+#define FDCAN_TTOCF_GEN_Msk       (0x1UL << FDCAN_TTOCF_GEN_Pos)               /*!< 0x00000008 */

+#define FDCAN_TTOCF_GEN           FDCAN_TTOCF_GEN_Msk                          /*!<Gap Enable                                */

+#define FDCAN_TTOCF_TM_Pos        (4U)

+#define FDCAN_TTOCF_TM_Msk        (0x1UL << FDCAN_TTOCF_TM_Pos)                /*!< 0x00000010 */

+#define FDCAN_TTOCF_TM            FDCAN_TTOCF_TM_Msk                           /*!<Time Master                               */

+#define FDCAN_TTOCF_LDSDL_Pos     (5U)

+#define FDCAN_TTOCF_LDSDL_Msk     (0x7UL << FDCAN_TTOCF_LDSDL_Pos)             /*!< 0x000000E0 */

+#define FDCAN_TTOCF_LDSDL         FDCAN_TTOCF_LDSDL_Msk                        /*!<LD of Synchronization Deviation Limit     */

+#define FDCAN_TTOCF_IRTO_Pos      (8U)

+#define FDCAN_TTOCF_IRTO_Msk      (0x7FUL << FDCAN_TTOCF_IRTO_Pos)             /*!< 0x00007F00 */

+#define FDCAN_TTOCF_IRTO          FDCAN_TTOCF_IRTO_Msk                         /*!<Initial Reference Trigger Offset          */

+#define FDCAN_TTOCF_EECS_Pos      (15U)

+#define FDCAN_TTOCF_EECS_Msk      (0x1UL << FDCAN_TTOCF_EECS_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTOCF_EECS          FDCAN_TTOCF_EECS_Msk                         /*!<Enable External Clock Synchronization     */

+#define FDCAN_TTOCF_AWL_Pos       (16U)

+#define FDCAN_TTOCF_AWL_Msk       (0xFFUL << FDCAN_TTOCF_AWL_Pos)              /*!< 0x00FF0000 */

+#define FDCAN_TTOCF_AWL           FDCAN_TTOCF_AWL_Msk                          /*!<Application Watchdog Limit                */

+#define FDCAN_TTOCF_EGTF_Pos      (24U)

+#define FDCAN_TTOCF_EGTF_Msk      (0x1UL << FDCAN_TTOCF_EGTF_Pos)              /*!< 0x01000000 */

+#define FDCAN_TTOCF_EGTF          FDCAN_TTOCF_EGTF_Msk                         /*!<Enable Global Time Filtering              */

+#define FDCAN_TTOCF_ECC_Pos       (25U)

+#define FDCAN_TTOCF_ECC_Msk       (0x1UL << FDCAN_TTOCF_ECC_Pos)               /*!< 0x02000000 */

+#define FDCAN_TTOCF_ECC           FDCAN_TTOCF_ECC_Msk                          /*!<Enable Clock Calibration                  */

+#define FDCAN_TTOCF_EVTP_Pos      (26U)

+#define FDCAN_TTOCF_EVTP_Msk      (0x1UL << FDCAN_TTOCF_EVTP_Pos)              /*!< 0x04000000 */

+#define FDCAN_TTOCF_EVTP          FDCAN_TTOCF_EVTP_Msk                         /*!<Event Trigger Polarity                    */

+

+/*****************  Bit definition for FDCAN_TTMLM register  *********************/

+#define FDCAN_TTMLM_CCM_Pos       (0U)

+#define FDCAN_TTMLM_CCM_Msk       (0x3FUL << FDCAN_TTMLM_CCM_Pos)              /*!< 0x0000003F */

+#define FDCAN_TTMLM_CCM           FDCAN_TTMLM_CCM_Msk                          /*!<Cycle Count Max                           */

+#define FDCAN_TTMLM_CSS_Pos       (6U)

+#define FDCAN_TTMLM_CSS_Msk       (0x3UL << FDCAN_TTMLM_CSS_Pos)               /*!< 0x000000C0 */

+#define FDCAN_TTMLM_CSS           FDCAN_TTMLM_CSS_Msk                          /*!<Cycle Start Synchronization               */

+#define FDCAN_TTMLM_TXEW_Pos      (8U)

+#define FDCAN_TTMLM_TXEW_Msk      (0xFUL << FDCAN_TTMLM_TXEW_Pos)              /*!< 0x00000F00 */

+#define FDCAN_TTMLM_TXEW          FDCAN_TTMLM_TXEW_Msk                         /*!<Tx Enable Window                          */

+#define FDCAN_TTMLM_ENTT_Pos      (16U)

+#define FDCAN_TTMLM_ENTT_Msk      (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)            /*!< 0x0FFF0000 */

+#define FDCAN_TTMLM_ENTT          FDCAN_TTMLM_ENTT_Msk                         /*!<Expected Number of Tx Triggers            */

+

+/*****************  Bit definition for FDCAN_TURCF register  *********************/

+#define FDCAN_TURCF_NCL_Pos       (0U)

+#define FDCAN_TURCF_NCL_Msk       (0xFFFFUL << FDCAN_TURCF_NCL_Pos)            /*!< 0x0000FFFF */

+#define FDCAN_TURCF_NCL           FDCAN_TURCF_NCL_Msk                          /*!<Numerator Configuration Low               */

+#define FDCAN_TURCF_DC_Pos        (16U)

+#define FDCAN_TURCF_DC_Msk        (0x3FFFUL << FDCAN_TURCF_DC_Pos)             /*!< 0x3FFF0000 */

+#define FDCAN_TURCF_DC            FDCAN_TURCF_DC_Msk                           /*!<Denominator Configuration                 */

+#define FDCAN_TURCF_ELT_Pos       (31U)

+#define FDCAN_TURCF_ELT_Msk       (0x1UL << FDCAN_TURCF_ELT_Pos)               /*!< 0x80000000 */

+#define FDCAN_TURCF_ELT           FDCAN_TURCF_ELT_Msk                          /*!<Enable Local Time                         */

+

+/*****************  Bit definition for FDCAN_TTOCN register  ********************/

+#define FDCAN_TTOCN_SGT_Pos       (0U)

+#define FDCAN_TTOCN_SGT_Msk       (0x1UL << FDCAN_TTOCN_SGT_Pos)               /*!< 0x00000001 */

+#define FDCAN_TTOCN_SGT           FDCAN_TTOCN_SGT_Msk                          /*!<Set Global time                           */

+#define FDCAN_TTOCN_ECS_Pos       (1U)

+#define FDCAN_TTOCN_ECS_Msk       (0x1UL << FDCAN_TTOCN_ECS_Pos)               /*!< 0x00000002 */

+#define FDCAN_TTOCN_ECS           FDCAN_TTOCN_ECS_Msk                          /*!<External Clock Synchronization            */

+#define FDCAN_TTOCN_SWP_Pos       (2U)

+#define FDCAN_TTOCN_SWP_Msk       (0x1UL << FDCAN_TTOCN_SWP_Pos)               /*!< 0x00000004 */

+#define FDCAN_TTOCN_SWP           FDCAN_TTOCN_SWP_Msk                          /*!<Stop Watch Polarity                       */

+#define FDCAN_TTOCN_SWS_Pos       (3U)

+#define FDCAN_TTOCN_SWS_Msk       (0x3UL << FDCAN_TTOCN_SWS_Pos)               /*!< 0x00000018 */

+#define FDCAN_TTOCN_SWS           FDCAN_TTOCN_SWS_Msk                          /*!<Stop Watch Source                         */

+#define FDCAN_TTOCN_RTIE_Pos      (5U)

+#define FDCAN_TTOCN_RTIE_Msk      (0x1UL << FDCAN_TTOCN_RTIE_Pos)              /*!< 0x00000020 */

+#define FDCAN_TTOCN_RTIE          FDCAN_TTOCN_RTIE_Msk                         /*!<Register Time Mark Interrupt Pulse Enable */

+#define FDCAN_TTOCN_TMC_Pos       (6U)

+#define FDCAN_TTOCN_TMC_Msk       (0x3UL << FDCAN_TTOCN_TMC_Pos)               /*!< 0x000000C0 */

+#define FDCAN_TTOCN_TMC           FDCAN_TTOCN_TMC_Msk                          /*!<Register Time Mark Compare                */

+#define FDCAN_TTOCN_TTIE_Pos      (8U)

+#define FDCAN_TTOCN_TTIE_Msk      (0x1UL << FDCAN_TTOCN_TTIE_Pos)              /*!< 0x00000100 */

+#define FDCAN_TTOCN_TTIE          FDCAN_TTOCN_TTIE_Msk                         /*!<Trigger Time Mark Interrupt Pulse Enable  */

+#define FDCAN_TTOCN_GCS_Pos       (9U)

+#define FDCAN_TTOCN_GCS_Msk       (0x1UL << FDCAN_TTOCN_GCS_Pos)               /*!< 0x00000200 */

+#define FDCAN_TTOCN_GCS           FDCAN_TTOCN_GCS_Msk                          /*!<Gap Control Select                        */

+#define FDCAN_TTOCN_FGP_Pos       (10U)

+#define FDCAN_TTOCN_FGP_Msk       (0x1UL << FDCAN_TTOCN_FGP_Pos)               /*!< 0x00000400 */

+#define FDCAN_TTOCN_FGP           FDCAN_TTOCN_FGP_Msk                          /*!<Finish Gap                                */

+#define FDCAN_TTOCN_TMG_Pos       (11U)

+#define FDCAN_TTOCN_TMG_Msk       (0x1UL << FDCAN_TTOCN_TMG_Pos)               /*!< 0x00000800 */

+#define FDCAN_TTOCN_TMG           FDCAN_TTOCN_TMG_Msk                          /*!<Time Mark Gap                             */

+#define FDCAN_TTOCN_NIG_Pos       (12U)

+#define FDCAN_TTOCN_NIG_Msk       (0x1UL << FDCAN_TTOCN_NIG_Pos)               /*!< 0x00001000 */

+#define FDCAN_TTOCN_NIG           FDCAN_TTOCN_NIG_Msk                          /*!<Next is Gap                               */

+#define FDCAN_TTOCN_ESCN_Pos      (13U)

+#define FDCAN_TTOCN_ESCN_Msk      (0x1UL << FDCAN_TTOCN_ESCN_Pos)              /*!< 0x00002000 */

+#define FDCAN_TTOCN_ESCN          FDCAN_TTOCN_ESCN_Msk                         /*!<External Synchronization Control          */

+#define FDCAN_TTOCN_LCKC_Pos      (15U)

+#define FDCAN_TTOCN_LCKC_Msk      (0x1UL << FDCAN_TTOCN_LCKC_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTOCN_LCKC          FDCAN_TTOCN_LCKC_Msk                         /*!<TT Operation Control Register Locked      */

+

+/*****************  Bit definition for FDCAN_TTGTP register  ********************/

+#define FDCAN_TTGTP_TP_Pos        (0U)

+#define FDCAN_TTGTP_TP_Msk        (0xFFFFUL << FDCAN_TTGTP_TP_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTGTP_TP            FDCAN_TTGTP_TP_Msk                           /*!<Time Preset                               */

+#define FDCAN_TTGTP_CTP_Pos       (16U)

+#define FDCAN_TTGTP_CTP_Msk       (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)            /*!< 0xFFFF0000 */

+#define FDCAN_TTGTP_CTP           FDCAN_TTGTP_CTP_Msk                          /*!<Cycle Time Target Phase                   */

+

+/*****************  Bit definition for FDCAN_TTTMK register  ********************/

+#define FDCAN_TTTMK_TM_Pos        (0U)

+#define FDCAN_TTTMK_TM_Msk        (0xFFFFUL << FDCAN_TTTMK_TM_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTTMK_TM            FDCAN_TTTMK_TM_Msk                           /*!<Time Mark                                 */

+#define FDCAN_TTTMK_TICC_Pos      (16U)

+#define FDCAN_TTTMK_TICC_Msk      (0x7FUL << FDCAN_TTTMK_TICC_Pos)             /*!< 0x007F0000 */

+#define FDCAN_TTTMK_TICC          FDCAN_TTTMK_TICC_Msk                         /*!<Time Mark Cycle Code                      */

+#define FDCAN_TTTMK_LCKM_Pos      (31U)

+#define FDCAN_TTTMK_LCKM_Msk      (0x1UL << FDCAN_TTTMK_LCKM_Pos)              /*!< 0x80000000 */

+#define FDCAN_TTTMK_LCKM          FDCAN_TTTMK_LCKM_Msk                         /*!<TT Time Mark Register Locked              */

+

+/*****************  Bit definition for FDCAN_TTIR register  ********************/

+#define FDCAN_TTIR_SBC_Pos        (0U)

+#define FDCAN_TTIR_SBC_Msk        (0x1UL << FDCAN_TTIR_SBC_Pos)                /*!< 0x00000001 */

+#define FDCAN_TTIR_SBC            FDCAN_TTIR_SBC_Msk                           /*!<Start of Basic Cycle                      */

+#define FDCAN_TTIR_SMC_Pos        (1U)

+#define FDCAN_TTIR_SMC_Msk        (0x1UL << FDCAN_TTIR_SMC_Pos)                /*!< 0x00000002 */

+#define FDCAN_TTIR_SMC            FDCAN_TTIR_SMC_Msk                           /*!<Start of Matrix Cycle                     */

+#define FDCAN_TTIR_CSM_Pos        (2U)

+#define FDCAN_TTIR_CSM_Msk        (0x1UL << FDCAN_TTIR_CSM_Pos)                /*!< 0x00000004 */

+#define FDCAN_TTIR_CSM            FDCAN_TTIR_CSM_Msk                           /*!<Change of Synchronization Mode            */

+#define FDCAN_TTIR_SOG_Pos        (3U)

+#define FDCAN_TTIR_SOG_Msk        (0x1UL << FDCAN_TTIR_SOG_Pos)                /*!< 0x00000008 */

+#define FDCAN_TTIR_SOG            FDCAN_TTIR_SOG_Msk                           /*!<Start of Gap                              */

+#define FDCAN_TTIR_RTMI_Pos       (4U)

+#define FDCAN_TTIR_RTMI_Msk       (0x1UL << FDCAN_TTIR_RTMI_Pos)               /*!< 0x00000010 */

+#define FDCAN_TTIR_RTMI           FDCAN_TTIR_RTMI_Msk                          /*!<Register Time Mark Interrupt              */

+#define FDCAN_TTIR_TTMI_Pos       (5U)

+#define FDCAN_TTIR_TTMI_Msk       (0x1UL << FDCAN_TTIR_TTMI_Pos)               /*!< 0x00000020 */

+#define FDCAN_TTIR_TTMI           FDCAN_TTIR_TTMI_Msk                          /*!<Trigger Time Mark Event Internal          */

+#define FDCAN_TTIR_SWE_Pos        (6U)

+#define FDCAN_TTIR_SWE_Msk        (0x1UL << FDCAN_TTIR_SWE_Pos)                /*!< 0x00000040 */

+#define FDCAN_TTIR_SWE            FDCAN_TTIR_SWE_Msk                           /*!<Stop Watch Event                          */

+#define FDCAN_TTIR_GTW_Pos        (7U)

+#define FDCAN_TTIR_GTW_Msk        (0x1UL << FDCAN_TTIR_GTW_Pos)                /*!< 0x00000080 */

+#define FDCAN_TTIR_GTW            FDCAN_TTIR_GTW_Msk                           /*!<Global Time Wrap                          */

+#define FDCAN_TTIR_GTD_Pos        (8U)

+#define FDCAN_TTIR_GTD_Msk        (0x1UL << FDCAN_TTIR_GTD_Pos)                /*!< 0x00000100 */

+#define FDCAN_TTIR_GTD            FDCAN_TTIR_GTD_Msk                           /*!<Global Time Discontinuity                 */

+#define FDCAN_TTIR_GTE_Pos        (9U)

+#define FDCAN_TTIR_GTE_Msk        (0x1UL << FDCAN_TTIR_GTE_Pos)                /*!< 0x00000200 */

+#define FDCAN_TTIR_GTE            FDCAN_TTIR_GTE_Msk                           /*!<Global Time Error                         */

+#define FDCAN_TTIR_TXU_Pos        (10U)

+#define FDCAN_TTIR_TXU_Msk        (0x1UL << FDCAN_TTIR_TXU_Pos)                /*!< 0x00000400 */

+#define FDCAN_TTIR_TXU            FDCAN_TTIR_TXU_Msk                           /*!<Tx Count Underflow                        */

+#define FDCAN_TTIR_TXO_Pos        (11U)

+#define FDCAN_TTIR_TXO_Msk        (0x1UL << FDCAN_TTIR_TXO_Pos)                /*!< 0x00000800 */

+#define FDCAN_TTIR_TXO            FDCAN_TTIR_TXO_Msk                           /*!<Tx Count Overflow                         */

+#define FDCAN_TTIR_SE1_Pos        (12U)

+#define FDCAN_TTIR_SE1_Msk        (0x1UL << FDCAN_TTIR_SE1_Pos)                /*!< 0x00001000 */

+#define FDCAN_TTIR_SE1            FDCAN_TTIR_SE1_Msk                           /*!<Scheduling Error 1                        */

+#define FDCAN_TTIR_SE2_Pos        (13U)

+#define FDCAN_TTIR_SE2_Msk        (0x1UL << FDCAN_TTIR_SE2_Pos)                /*!< 0x00002000 */

+#define FDCAN_TTIR_SE2            FDCAN_TTIR_SE2_Msk                           /*!<Scheduling Error 2                        */

+#define FDCAN_TTIR_ELC_Pos        (14U)

+#define FDCAN_TTIR_ELC_Msk        (0x1UL << FDCAN_TTIR_ELC_Pos)                /*!< 0x00004000 */

+#define FDCAN_TTIR_ELC            FDCAN_TTIR_ELC_Msk                           /*!<Error Level Changed                       */

+#define FDCAN_TTIR_IWT_Pos        (15U)

+#define FDCAN_TTIR_IWT_Msk        (0x1UL << FDCAN_TTIR_IWT_Pos)                /*!< 0x00008000 */

+#define FDCAN_TTIR_IWT            FDCAN_TTIR_IWT_Msk                           /*!<Initialization Watch Trigger              */

+#define FDCAN_TTIR_WT_Pos         (16U)

+#define FDCAN_TTIR_WT_Msk         (0x1UL << FDCAN_TTIR_WT_Pos)                 /*!< 0x00010000 */

+#define FDCAN_TTIR_WT             FDCAN_TTIR_WT_Msk                            /*!<Watch Trigger                             */

+#define FDCAN_TTIR_AW_Pos         (17U)

+#define FDCAN_TTIR_AW_Msk         (0x1UL << FDCAN_TTIR_AW_Pos)                 /*!< 0x00020000 */

+#define FDCAN_TTIR_AW             FDCAN_TTIR_AW_Msk                            /*!<Application Watchdog                      */

+#define FDCAN_TTIR_CER_Pos        (18U)

+#define FDCAN_TTIR_CER_Msk        (0x1UL << FDCAN_TTIR_CER_Pos)                /*!< 0x00040000 */

+#define FDCAN_TTIR_CER            FDCAN_TTIR_CER_Msk                           /*!<Configuration Error                       */

+

+/*****************  Bit definition for FDCAN_TTIE register  ********************/

+#define FDCAN_TTIE_SBCE_Pos       (0U)

+#define FDCAN_TTIE_SBCE_Msk       (0x1UL << FDCAN_TTIE_SBCE_Pos)               /*!< 0x00000001 */

+#define FDCAN_TTIE_SBCE           FDCAN_TTIE_SBCE_Msk                          /*!<Start of Basic Cycle Interrupt Enable             */

+#define FDCAN_TTIE_SMCE_Pos       (1U)

+#define FDCAN_TTIE_SMCE_Msk       (0x1UL << FDCAN_TTIE_SMCE_Pos)               /*!< 0x00000002 */

+#define FDCAN_TTIE_SMCE           FDCAN_TTIE_SMCE_Msk                          /*!<Start of Matrix Cycle Interrupt Enable            */

+#define FDCAN_TTIE_CSME_Pos       (2U)

+#define FDCAN_TTIE_CSME_Msk       (0x1UL << FDCAN_TTIE_CSME_Pos)               /*!< 0x00000004 */

+#define FDCAN_TTIE_CSME           FDCAN_TTIE_CSME_Msk                          /*!<Change of Synchronization Mode Interrupt Enable   */

+#define FDCAN_TTIE_SOGE_Pos       (3U)

+#define FDCAN_TTIE_SOGE_Msk       (0x1UL << FDCAN_TTIE_SOGE_Pos)               /*!< 0x00000008 */

+#define FDCAN_TTIE_SOGE           FDCAN_TTIE_SOGE_Msk                          /*!<Start of Gap Interrupt Enable                     */

+#define FDCAN_TTIE_RTMIE_Pos      (4U)

+#define FDCAN_TTIE_RTMIE_Msk      (0x1UL << FDCAN_TTIE_RTMIE_Pos)              /*!< 0x00000010 */

+#define FDCAN_TTIE_RTMIE          FDCAN_TTIE_RTMIE_Msk                         /*!<Register Time Mark Interrupt Interrupt Enable     */

+#define FDCAN_TTIE_TTMIE_Pos      (5U)

+#define FDCAN_TTIE_TTMIE_Msk      (0x1UL << FDCAN_TTIE_TTMIE_Pos)              /*!< 0x00000020 */

+#define FDCAN_TTIE_TTMIE          FDCAN_TTIE_TTMIE_Msk                         /*!<Trigger Time Mark Event Internal Interrupt Enable */

+#define FDCAN_TTIE_SWEE_Pos       (6U)

+#define FDCAN_TTIE_SWEE_Msk       (0x1UL << FDCAN_TTIE_SWEE_Pos)               /*!< 0x00000040 */

+#define FDCAN_TTIE_SWEE           FDCAN_TTIE_SWEE_Msk                          /*!<Stop Watch Event Interrupt Enable                 */

+#define FDCAN_TTIE_GTWE_Pos       (7U)

+#define FDCAN_TTIE_GTWE_Msk       (0x1UL << FDCAN_TTIE_GTWE_Pos)               /*!< 0x00000080 */

+#define FDCAN_TTIE_GTWE           FDCAN_TTIE_GTWE_Msk                          /*!<Global Time Wrap Interrupt Enable                 */

+#define FDCAN_TTIE_GTDE_Pos       (8U)

+#define FDCAN_TTIE_GTDE_Msk       (0x1UL << FDCAN_TTIE_GTDE_Pos)               /*!< 0x00000100 */

+#define FDCAN_TTIE_GTDE           FDCAN_TTIE_GTDE_Msk                          /*!<Global Time Discontinuity Interrupt Enable        */

+#define FDCAN_TTIE_GTEE_Pos       (9U)

+#define FDCAN_TTIE_GTEE_Msk       (0x1UL << FDCAN_TTIE_GTEE_Pos)               /*!< 0x00000200 */

+#define FDCAN_TTIE_GTEE           FDCAN_TTIE_GTEE_Msk                          /*!<Global Time Error Interrupt Enable                */

+#define FDCAN_TTIE_TXUE_Pos       (10U)

+#define FDCAN_TTIE_TXUE_Msk       (0x1UL << FDCAN_TTIE_TXUE_Pos)               /*!< 0x00000400 */

+#define FDCAN_TTIE_TXUE           FDCAN_TTIE_TXUE_Msk                          /*!<Tx Count Underflow Interrupt Enable               */

+#define FDCAN_TTIE_TXOE_Pos       (11U)

+#define FDCAN_TTIE_TXOE_Msk       (0x1UL << FDCAN_TTIE_TXOE_Pos)               /*!< 0x00000800 */

+#define FDCAN_TTIE_TXOE           FDCAN_TTIE_TXOE_Msk                          /*!<Tx Count Overflow Interrupt Enable                */

+#define FDCAN_TTIE_SE1E_Pos       (12U)

+#define FDCAN_TTIE_SE1E_Msk       (0x1UL << FDCAN_TTIE_SE1E_Pos)               /*!< 0x00001000 */

+#define FDCAN_TTIE_SE1E           FDCAN_TTIE_SE1E_Msk                          /*!<Scheduling Error 1 Interrupt Enable               */

+#define FDCAN_TTIE_SE2E_Pos       (13U)

+#define FDCAN_TTIE_SE2E_Msk       (0x1UL << FDCAN_TTIE_SE2E_Pos)               /*!< 0x00002000 */

+#define FDCAN_TTIE_SE2E           FDCAN_TTIE_SE2E_Msk                          /*!<Scheduling Error 2 Interrupt Enable               */

+#define FDCAN_TTIE_ELCE_Pos       (14U)

+#define FDCAN_TTIE_ELCE_Msk       (0x1UL << FDCAN_TTIE_ELCE_Pos)               /*!< 0x00004000 */

+#define FDCAN_TTIE_ELCE           FDCAN_TTIE_ELCE_Msk                          /*!<Error Level Changed Interrupt Enable              */

+#define FDCAN_TTIE_IWTE_Pos       (15U)

+#define FDCAN_TTIE_IWTE_Msk       (0x1UL << FDCAN_TTIE_IWTE_Pos)               /*!< 0x00008000 */

+#define FDCAN_TTIE_IWTE           FDCAN_TTIE_IWTE_Msk                          /*!<Initialization Watch Trigger Interrupt Enable     */

+#define FDCAN_TTIE_WTE_Pos        (16U)

+#define FDCAN_TTIE_WTE_Msk        (0x1UL << FDCAN_TTIE_WTE_Pos)                /*!< 0x00010000 */

+#define FDCAN_TTIE_WTE            FDCAN_TTIE_WTE_Msk                           /*!<Watch Trigger Interrupt Enable                    */

+#define FDCAN_TTIE_AWE_Pos        (17U)

+#define FDCAN_TTIE_AWE_Msk        (0x1UL << FDCAN_TTIE_AWE_Pos)                /*!< 0x00020000 */

+#define FDCAN_TTIE_AWE            FDCAN_TTIE_AWE_Msk                           /*!<Application Watchdog Interrupt Enable             */

+#define FDCAN_TTIE_CERE_Pos       (18U)

+#define FDCAN_TTIE_CERE_Msk       (0x1UL << FDCAN_TTIE_CERE_Pos)               /*!< 0x00040000 */

+#define FDCAN_TTIE_CERE           FDCAN_TTIE_CERE_Msk                          /*!<Configuration Error Interrupt Enable              */

+

+/*****************  Bit definition for FDCAN_TTILS register  ********************/

+#define FDCAN_TTILS_SBCS_Pos      (0U)

+#define FDCAN_TTILS_SBCS_Msk      (0x1UL << FDCAN_TTILS_SBCS_Pos)              /*!< 0x00000001 */

+#define FDCAN_TTILS_SBCS          FDCAN_TTILS_SBCS_Msk                         /*!<Start of Basic Cycle Interrupt Line               */

+#define FDCAN_TTILS_SMCS_Pos      (1U)

+#define FDCAN_TTILS_SMCS_Msk      (0x1UL << FDCAN_TTILS_SMCS_Pos)              /*!< 0x00000002 */

+#define FDCAN_TTILS_SMCS          FDCAN_TTILS_SMCS_Msk                         /*!<Start of Matrix Cycle Interrupt Line              */

+#define FDCAN_TTILS_CSMS_Pos      (2U)

+#define FDCAN_TTILS_CSMS_Msk      (0x1UL << FDCAN_TTILS_CSMS_Pos)              /*!< 0x00000004 */

+#define FDCAN_TTILS_CSMS          FDCAN_TTILS_CSMS_Msk                         /*!<Change of Synchronization Mode Interrupt Line     */

+#define FDCAN_TTILS_SOGS_Pos      (3U)

+#define FDCAN_TTILS_SOGS_Msk      (0x1UL << FDCAN_TTILS_SOGS_Pos)              /*!< 0x00000008 */

+#define FDCAN_TTILS_SOGS          FDCAN_TTILS_SOGS_Msk                         /*!<Start of Gap Interrupt Line                       */

+#define FDCAN_TTILS_RTMIS_Pos     (4U)

+#define FDCAN_TTILS_RTMIS_Msk     (0x1UL << FDCAN_TTILS_RTMIS_Pos)             /*!< 0x00000010 */

+#define FDCAN_TTILS_RTMIS         FDCAN_TTILS_RTMIS_Msk                        /*!<Register Time Mark Interrupt Interrupt Line       */

+#define FDCAN_TTILS_TTMIS_Pos     (5U)

+#define FDCAN_TTILS_TTMIS_Msk     (0x1UL << FDCAN_TTILS_TTMIS_Pos)             /*!< 0x00000020 */

+#define FDCAN_TTILS_TTMIS         FDCAN_TTILS_TTMIS_Msk                        /*!<Trigger Time Mark Event Internal Interrupt Line   */

+#define FDCAN_TTILS_SWES_Pos      (6U)

+#define FDCAN_TTILS_SWES_Msk      (0x1UL << FDCAN_TTILS_SWES_Pos)              /*!< 0x00000040 */

+#define FDCAN_TTILS_SWES          FDCAN_TTILS_SWES_Msk                         /*!<Stop Watch Event Interrupt Line                   */

+#define FDCAN_TTILS_GTWS_Pos      (7U)

+#define FDCAN_TTILS_GTWS_Msk      (0x1UL << FDCAN_TTILS_GTWS_Pos)              /*!< 0x00000080 */

+#define FDCAN_TTILS_GTWS          FDCAN_TTILS_GTWS_Msk                         /*!<Global Time Wrap Interrupt Line                   */

+#define FDCAN_TTILS_GTDS_Pos      (8U)

+#define FDCAN_TTILS_GTDS_Msk      (0x1UL << FDCAN_TTILS_GTDS_Pos)              /*!< 0x00000100 */

+#define FDCAN_TTILS_GTDS          FDCAN_TTILS_GTDS_Msk                         /*!<Global Time Discontinuity Interrupt Line          */

+#define FDCAN_TTILS_GTES_Pos      (9U)

+#define FDCAN_TTILS_GTES_Msk      (0x1UL << FDCAN_TTILS_GTES_Pos)              /*!< 0x00000200 */

+#define FDCAN_TTILS_GTES          FDCAN_TTILS_GTES_Msk                         /*!<Global Time Error Interrupt Line                  */

+#define FDCAN_TTILS_TXUS_Pos      (10U)

+#define FDCAN_TTILS_TXUS_Msk      (0x1UL << FDCAN_TTILS_TXUS_Pos)              /*!< 0x00000400 */

+#define FDCAN_TTILS_TXUS          FDCAN_TTILS_TXUS_Msk                         /*!<Tx Count Underflow Interrupt Line                 */

+#define FDCAN_TTILS_TXOS_Pos      (11U)

+#define FDCAN_TTILS_TXOS_Msk      (0x1UL << FDCAN_TTILS_TXOS_Pos)              /*!< 0x00000800 */

+#define FDCAN_TTILS_TXOS          FDCAN_TTILS_TXOS_Msk                         /*!<Tx Count Overflow Interrupt Line                  */

+#define FDCAN_TTILS_SE1S_Pos      (12U)

+#define FDCAN_TTILS_SE1S_Msk      (0x1UL << FDCAN_TTILS_SE1S_Pos)              /*!< 0x00001000 */

+#define FDCAN_TTILS_SE1S          FDCAN_TTILS_SE1S_Msk                         /*!<Scheduling Error 1 Interrupt Line                 */

+#define FDCAN_TTILS_SE2S_Pos      (13U)

+#define FDCAN_TTILS_SE2S_Msk      (0x1UL << FDCAN_TTILS_SE2S_Pos)              /*!< 0x00002000 */

+#define FDCAN_TTILS_SE2S          FDCAN_TTILS_SE2S_Msk                         /*!<Scheduling Error 2 Interrupt Line                 */

+#define FDCAN_TTILS_ELCS_Pos      (14U)

+#define FDCAN_TTILS_ELCS_Msk      (0x1UL << FDCAN_TTILS_ELCS_Pos)              /*!< 0x00004000 */

+#define FDCAN_TTILS_ELCS          FDCAN_TTILS_ELCS_Msk                         /*!<Error Level Changed Interrupt Line                */

+#define FDCAN_TTILS_IWTS_Pos      (15U)

+#define FDCAN_TTILS_IWTS_Msk      (0x1UL << FDCAN_TTILS_IWTS_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTILS_IWTS          FDCAN_TTILS_IWTS_Msk                         /*!<Initialization Watch Trigger Interrupt Line       */

+#define FDCAN_TTILS_WTS_Pos       (16U)

+#define FDCAN_TTILS_WTS_Msk       (0x1UL << FDCAN_TTILS_WTS_Pos)               /*!< 0x00010000 */

+#define FDCAN_TTILS_WTS           FDCAN_TTILS_WTS_Msk                          /*!<Watch Trigger Interrupt Line                      */

+#define FDCAN_TTILS_AWS_Pos       (17U)

+#define FDCAN_TTILS_AWS_Msk       (0x1UL << FDCAN_TTILS_AWS_Pos)               /*!< 0x00020000 */

+#define FDCAN_TTILS_AWS           FDCAN_TTILS_AWS_Msk                          /*!<Application Watchdog Interrupt Line               */

+#define FDCAN_TTILS_CERS_Pos      (18U)

+#define FDCAN_TTILS_CERS_Msk      (0x1UL << FDCAN_TTILS_CERS_Pos)              /*!< 0x00040000 */

+#define FDCAN_TTILS_CERS          FDCAN_TTILS_CERS_Msk                         /*!<Configuration Error Interrupt Line                */

+

+/*****************  Bit definition for FDCAN_TTOST register  ********************/

+#define FDCAN_TTOST_EL_Pos        (0U)

+#define FDCAN_TTOST_EL_Msk        (0x3UL << FDCAN_TTOST_EL_Pos)                /*!< 0x00000003 */

+#define FDCAN_TTOST_EL            FDCAN_TTOST_EL_Msk                           /*!<Error Level                              */

+#define FDCAN_TTOST_MS_Pos        (2U)

+#define FDCAN_TTOST_MS_Msk        (0x3UL << FDCAN_TTOST_MS_Pos)                /*!< 0x0000000C */

+#define FDCAN_TTOST_MS            FDCAN_TTOST_MS_Msk                           /*!<Master State                             */

+#define FDCAN_TTOST_SYS_Pos       (4U)

+#define FDCAN_TTOST_SYS_Msk       (0x3UL << FDCAN_TTOST_SYS_Pos)               /*!< 0x00000030 */

+#define FDCAN_TTOST_SYS           FDCAN_TTOST_SYS_Msk                          /*!<Synchronization State                    */

+#define FDCAN_TTOST_QGTP_Pos      (6U)

+#define FDCAN_TTOST_QGTP_Msk      (0x1UL << FDCAN_TTOST_QGTP_Pos)              /*!< 0x00000040 */

+#define FDCAN_TTOST_QGTP          FDCAN_TTOST_QGTP_Msk                         /*!<Quality of Global Time Phase             */

+#define FDCAN_TTOST_QCS_Pos       (7U)

+#define FDCAN_TTOST_QCS_Msk       (0x1UL << FDCAN_TTOST_QCS_Pos)               /*!< 0x00000080 */

+#define FDCAN_TTOST_QCS           FDCAN_TTOST_QCS_Msk                          /*!<Quality of Clock Speed                   */

+#define FDCAN_TTOST_RTO_Pos       (8U)

+#define FDCAN_TTOST_RTO_Msk       (0xFFUL << FDCAN_TTOST_RTO_Pos)              /*!< 0x0000FF00 */

+#define FDCAN_TTOST_RTO           FDCAN_TTOST_RTO_Msk                          /*!<Reference Trigger Offset                 */

+#define FDCAN_TTOST_WGTD_Pos      (22U)

+#define FDCAN_TTOST_WGTD_Msk      (0x1UL << FDCAN_TTOST_WGTD_Pos)              /*!< 0x00400000 */

+#define FDCAN_TTOST_WGTD          FDCAN_TTOST_WGTD_Msk                         /*!<Wait for Global Time Discontinuity       */

+#define FDCAN_TTOST_GFI_Pos       (23U)

+#define FDCAN_TTOST_GFI_Msk       (0x1UL << FDCAN_TTOST_GFI_Pos)               /*!< 0x00800000 */

+#define FDCAN_TTOST_GFI           FDCAN_TTOST_GFI_Msk                          /*!<Gap Finished Indicator                   */

+#define FDCAN_TTOST_TMP_Pos       (24U)

+#define FDCAN_TTOST_TMP_Msk       (0x7UL << FDCAN_TTOST_TMP_Pos)               /*!< 0x07000000 */

+#define FDCAN_TTOST_TMP           FDCAN_TTOST_TMP_Msk                          /*!<Time Master Priority                     */

+#define FDCAN_TTOST_GSI_Pos       (27U)

+#define FDCAN_TTOST_GSI_Msk       (0x1UL << FDCAN_TTOST_GSI_Pos)               /*!< 0x08000000 */

+#define FDCAN_TTOST_GSI           FDCAN_TTOST_GSI_Msk                          /*!<Gap Started Indicator                    */

+#define FDCAN_TTOST_WFE_Pos       (28U)

+#define FDCAN_TTOST_WFE_Msk       (0x1UL << FDCAN_TTOST_WFE_Pos)               /*!< 0x10000000 */

+#define FDCAN_TTOST_WFE           FDCAN_TTOST_WFE_Msk                          /*!<Wait for Event                           */

+#define FDCAN_TTOST_AWE_Pos       (29U)

+#define FDCAN_TTOST_AWE_Msk       (0x1UL << FDCAN_TTOST_AWE_Pos)               /*!< 0x20000000 */

+#define FDCAN_TTOST_AWE           FDCAN_TTOST_AWE_Msk                          /*!<Application Watchdog Event               */

+#define FDCAN_TTOST_WECS_Pos      (30U)

+#define FDCAN_TTOST_WECS_Msk      (0x1UL << FDCAN_TTOST_WECS_Pos)              /*!< 0x40000000 */

+#define FDCAN_TTOST_WECS          FDCAN_TTOST_WECS_Msk                         /*!<Wait for External Clock Synchronization  */

+#define FDCAN_TTOST_SPL_Pos       (31U)

+#define FDCAN_TTOST_SPL_Msk       (0x1UL << FDCAN_TTOST_SPL_Pos)               /*!< 0x80000000 */

+#define FDCAN_TTOST_SPL           FDCAN_TTOST_SPL_Msk                          /*!<Schedule Phase Lock                      */

+

+/*****************  Bit definition for FDCAN_TURNA register  ********************/

+#define FDCAN_TURNA_NAV_Pos       (0U)

+#define FDCAN_TURNA_NAV_Msk       (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)           /*!< 0x0003FFFF */

+#define FDCAN_TURNA_NAV           FDCAN_TURNA_NAV_Msk                          /*!<Numerator Actual Value                   */

+

+/*****************  Bit definition for FDCAN_TTLGT register  ********************/

+#define FDCAN_TTLGT_LT_Pos        (0U)

+#define FDCAN_TTLGT_LT_Msk        (0xFFFFUL << FDCAN_TTLGT_LT_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTLGT_LT            FDCAN_TTLGT_LT_Msk                           /*!<Local Time                               */

+#define FDCAN_TTLGT_GT_Pos        (16U)

+#define FDCAN_TTLGT_GT_Msk        (0xFFFFUL << FDCAN_TTLGT_GT_Pos)             /*!< 0xFFFF0000 */

+#define FDCAN_TTLGT_GT            FDCAN_TTLGT_GT_Msk                           /*!<Global Time                              */

+

+/*****************  Bit definition for FDCAN_TTCTC register  ********************/

+#define FDCAN_TTCTC_CT_Pos        (0U)

+#define FDCAN_TTCTC_CT_Msk        (0xFFFFUL << FDCAN_TTCTC_CT_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTCTC_CT            FDCAN_TTCTC_CT_Msk                           /*!<Cycle Time                               */

+#define FDCAN_TTCTC_CC_Pos        (16U)

+#define FDCAN_TTCTC_CC_Msk        (0x3FUL << FDCAN_TTCTC_CC_Pos)               /*!< 0x003F0000 */

+#define FDCAN_TTCTC_CC            FDCAN_TTCTC_CC_Msk                           /*!<Cycle Count                              */

+

+/*****************  Bit definition for FDCAN_TTCPT register  ********************/

+#define FDCAN_TTCPT_CCV_Pos       (0U)

+#define FDCAN_TTCPT_CCV_Msk       (0x3FUL << FDCAN_TTCPT_CCV_Pos)              /*!< 0x0000003F */

+#define FDCAN_TTCPT_CCV           FDCAN_TTCPT_CCV_Msk                          /*!<Cycle Count Value                        */

+#define FDCAN_TTCPT_SWV_Pos       (16U)

+#define FDCAN_TTCPT_SWV_Msk       (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)            /*!< 0xFFFF0000 */

+#define FDCAN_TTCPT_SWV           FDCAN_TTCPT_SWV_Msk                          /*!<Stop Watch Value                         */

+

+/*****************  Bit definition for FDCAN_TTCSM register  ********************/

+#define FDCAN_TTCSM_CSM_Pos       (0U)

+#define FDCAN_TTCSM_CSM_Msk       (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)            /*!< 0x0000FFFF */

+#define FDCAN_TTCSM_CSM           FDCAN_TTCSM_CSM_Msk                          /*!<Cycle Sync Mark                          */

+

+/*****************  Bit definition for FDCAN_TTTS register  *********************/

+#define FDCAN_TTTS_SWTSEL_Pos     (0U)

+#define FDCAN_TTTS_SWTSEL_Msk     (0x3UL << FDCAN_TTTS_SWTSEL_Pos)             /*!< 0x00000003 */

+#define FDCAN_TTTS_SWTSEL         FDCAN_TTTS_SWTSEL_Msk                        /*!<Stop watch trigger input selection       */

+#define FDCAN_TTTS_EVTSEL_Pos     (4U)

+#define FDCAN_TTTS_EVTSEL_Msk     (0x3UL << FDCAN_TTTS_EVTSEL_Pos)             /*!< 0x00000030 */

+#define FDCAN_TTTS_EVTSEL         FDCAN_TTTS_EVTSEL_Msk                        /*!<Event trigger input selection            */

+

+/********************************************************************************/

+/*                                                                              */

+/*                      FDCANCCU (Clock Calibration unit)                       */

+/*                                                                              */

+/********************************************************************************/

+

+/*****************  Bit definition for FDCANCCU_CREL register  ******************/

+#define FDCANCCU_CREL_DAY_Pos        (0U)

+#define FDCANCCU_CREL_DAY_Msk        (0xFFUL << FDCANCCU_CREL_DAY_Pos)         /*!< 0x000000FF */

+#define FDCANCCU_CREL_DAY            FDCANCCU_CREL_DAY_Msk                     /*!<Timestamp Day                           */

+#define FDCANCCU_CREL_MON_Pos        (8U)

+#define FDCANCCU_CREL_MON_Msk        (0xFFUL << FDCANCCU_CREL_MON_Pos)         /*!< 0x0000FF00 */

+#define FDCANCCU_CREL_MON            FDCANCCU_CREL_MON_Msk                     /*!<Timestamp Month                         */

+#define FDCANCCU_CREL_YEAR_Pos       (16U)

+#define FDCANCCU_CREL_YEAR_Msk       (0xFUL << FDCANCCU_CREL_YEAR_Pos)         /*!< 0x000F0000 */

+#define FDCANCCU_CREL_YEAR           FDCANCCU_CREL_YEAR_Msk                    /*!<Timestamp Year                          */

+#define FDCANCCU_CREL_SUBSTEP_Pos    (20U)

+#define FDCANCCU_CREL_SUBSTEP_Msk    (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)      /*!< 0x00F00000 */

+#define FDCANCCU_CREL_SUBSTEP        FDCANCCU_CREL_SUBSTEP_Msk                 /*!<Sub-step of Core release                */

+#define FDCANCCU_CREL_STEP_Pos       (24U)

+#define FDCANCCU_CREL_STEP_Msk       (0xFUL << FDCANCCU_CREL_STEP_Pos)         /*!< 0x0F000000 */

+#define FDCANCCU_CREL_STEP           FDCANCCU_CREL_STEP_Msk                    /*!<Step of Core release                    */

+#define FDCANCCU_CREL_REL_Pos        (28U)

+#define FDCANCCU_CREL_REL_Msk        (0xFUL << FDCANCCU_CREL_REL_Pos)          /*!< 0xF0000000 */

+#define FDCANCCU_CREL_REL            FDCANCCU_CREL_REL_Msk                     /*!<Core release                            */

+

+/*****************  Bit definition for FDCANCCU_CCFG register  ******************/

+#define FDCANCCU_CCFG_TQBT_Pos       (0U)

+#define FDCANCCU_CCFG_TQBT_Msk       (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)        /*!< 0x0000001F */

+#define FDCANCCU_CCFG_TQBT           FDCANCCU_CCFG_TQBT_Msk                    /*!<Time Quanta per Bit Time                */

+#define FDCANCCU_CCFG_BCC_Pos        (6U)

+#define FDCANCCU_CCFG_BCC_Msk        (0x1UL << FDCANCCU_CCFG_BCC_Pos)          /*!< 0x00000040 */

+#define FDCANCCU_CCFG_BCC            FDCANCCU_CCFG_BCC_Msk                     /*!<Bypass Clock Calibration                */

+#define FDCANCCU_CCFG_CFL_Pos        (7U)

+#define FDCANCCU_CCFG_CFL_Msk        (0x1UL << FDCANCCU_CCFG_CFL_Pos)          /*!< 0x00000080 */

+#define FDCANCCU_CCFG_CFL            FDCANCCU_CCFG_CFL_Msk                     /*!<Calibration Field Length                */

+#define FDCANCCU_CCFG_OCPM_Pos       (8U)

+#define FDCANCCU_CCFG_OCPM_Msk       (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)        /*!< 0x0000FF00 */

+#define FDCANCCU_CCFG_OCPM           FDCANCCU_CCFG_OCPM_Msk                    /*!<Oscillator Clock Periods Minimum        */

+#define FDCANCCU_CCFG_CDIV_Pos       (16U)

+#define FDCANCCU_CCFG_CDIV_Msk       (0xFUL << FDCANCCU_CCFG_CDIV_Pos)         /*!< 0x000F0000 */

+#define FDCANCCU_CCFG_CDIV           FDCANCCU_CCFG_CDIV_Msk                    /*!<Clock Divider                           */

+#define FDCANCCU_CCFG_SWR_Pos        (31U)

+#define FDCANCCU_CCFG_SWR_Msk        (0x1UL << FDCANCCU_CCFG_SWR_Pos)          /*!< 0x80000000 */

+#define FDCANCCU_CCFG_SWR            FDCANCCU_CCFG_SWR_Msk                     /*!<Software Reset                          */

+

+/*****************  Bit definition for FDCANCCU_CSTAT register  *****************/

+#define FDCANCCU_CSTAT_OCPC_Pos      (0U)

+#define FDCANCCU_CSTAT_OCPC_Msk      (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)    /*!< 0x0003FFFF */

+#define FDCANCCU_CSTAT_OCPC          FDCANCCU_CSTAT_OCPC_Msk                   /*!<Oscillator Clock Period Counter        */

+#define FDCANCCU_CSTAT_TQC_Pos       (18U)

+#define FDCANCCU_CSTAT_TQC_Msk       (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)       /*!< 0x1FFC0000 */

+#define FDCANCCU_CSTAT_TQC           FDCANCCU_CSTAT_TQC_Msk                    /*!<Time Quanta Counter                    */

+#define FDCANCCU_CSTAT_CALS_Pos      (30U)

+#define FDCANCCU_CSTAT_CALS_Msk      (0x3UL << FDCANCCU_CSTAT_CALS_Pos)        /*!< 0xC0000000 */

+#define FDCANCCU_CSTAT_CALS          FDCANCCU_CSTAT_CALS_Msk                   /*!<Calibration State                      */

+

+/******************  Bit definition for FDCANCCU_CWD register  ******************/

+#define FDCANCCU_CWD_WDC_Pos         (0U)

+#define FDCANCCU_CWD_WDC_Msk         (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)        /*!< 0x0000FFFF */

+#define FDCANCCU_CWD_WDC             FDCANCCU_CWD_WDC_Msk                      /*!<Watchdog Configuration                 */

+#define FDCANCCU_CWD_WDV_Pos         (16U)

+#define FDCANCCU_CWD_WDV_Msk         (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)        /*!< 0xFFFF0000 */

+#define FDCANCCU_CWD_WDV             FDCANCCU_CWD_WDV_Msk                      /*!<Watchdog Value                         */

+

+/******************  Bit definition for FDCANCCU_IR register  *******************/

+#define FDCANCCU_IR_CWE_Pos          (0U)

+#define FDCANCCU_IR_CWE_Msk          (0x1UL << FDCANCCU_IR_CWE_Pos)            /*!< 0x00000001 */

+#define FDCANCCU_IR_CWE              FDCANCCU_IR_CWE_Msk                       /*!<Calibration Watchdog Event             */

+#define FDCANCCU_IR_CSC_Pos          (1U)

+#define FDCANCCU_IR_CSC_Msk          (0x1UL << FDCANCCU_IR_CSC_Pos)            /*!< 0x00000002 */

+#define FDCANCCU_IR_CSC              FDCANCCU_IR_CSC_Msk                       /*!<Calibration State Changed              */

+

+/******************  Bit definition for FDCANCCU_IE register  *******************/

+#define FDCANCCU_IE_CWEE_Pos         (0U)

+#define FDCANCCU_IE_CWEE_Msk         (0x1UL << FDCANCCU_IE_CWEE_Pos)           /*!< 0x00000001 */

+#define FDCANCCU_IE_CWEE             FDCANCCU_IE_CWEE_Msk                      /*!<Calibration Watchdog Event Enable      */

+#define FDCANCCU_IE_CSCE_Pos         (1U)

+#define FDCANCCU_IE_CSCE_Msk         (0x1UL << FDCANCCU_IE_CSCE_Pos)           /*!< 0x00000002 */

+#define FDCANCCU_IE_CSCE             FDCANCCU_IE_CSCE_Msk                      /*!<Calibration State Changed Enable       */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          HDMI-CEC (CEC)                                    */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for CEC_CR register  *********************/

+#define CEC_CR_CECEN_Pos         (0U)

+#define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                   /*!< 0x00000001 */

+#define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                                */

+#define CEC_CR_TXSOM_Pos         (1U)

+#define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                   /*!< 0x00000002 */

+#define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message                   */

+#define CEC_CR_TXEOM_Pos         (2U)

+#define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                   /*!< 0x00000004 */

+#define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message                     */

+

+/*******************  Bit definition for CEC_CFGR register  *******************/

+#define CEC_CFGR_SFT_Pos         (0U)

+#define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                   /*!< 0x00000007 */

+#define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time                      */

+#define CEC_CFGR_RXTOL_Pos       (3U)

+#define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                 /*!< 0x00000008 */

+#define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                             */

+#define CEC_CFGR_BRESTP_Pos      (4U)

+#define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                /*!< 0x00000010 */

+#define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                               */

+#define CEC_CFGR_BREGEN_Pos      (5U)

+#define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                /*!< 0x00000020 */

+#define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation           */

+#define CEC_CFGR_LBPEGEN_Pos     (6U)

+#define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)               /*!< 0x00000040 */

+#define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error generation      */

+#define CEC_CFGR_SFTOPT_Pos      (8U)

+#define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                /*!< 0x00000100 */

+#define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional             */

+#define CEC_CFGR_BRDNOGEN_Pos    (7U)

+#define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)              /*!< 0x00000080 */

+#define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No error generation         */

+#define CEC_CFGR_OAR_Pos         (16U)

+#define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                /*!< 0x7FFF0000 */

+#define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                           */

+#define CEC_CFGR_LSTN_Pos        (31U)

+#define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                  /*!< 0x80000000 */

+#define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                           */

+

+/*******************  Bit definition for CEC_TXDR register  *******************/

+#define CEC_TXDR_TXD_Pos         (0U)

+#define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                  /*!< 0x000000FF */

+#define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                               */

+

+/*******************  Bit definition for CEC_RXDR register  *******************/

+#define CEC_RXDR_RXD_Pos         (0U)

+#define CEC_RXDR_RXD_Msk         (0xFFUL << CEC_RXDR_RXD_Pos)                  /*!< 0x000000FF */

+#define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                              /*!< CEC Rx Data                               */

+

+/*******************  Bit definition for CEC_ISR register  ********************/

+#define CEC_ISR_RXBR_Pos         (0U)

+#define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                   /*!< 0x00000001 */

+#define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                      */

+#define CEC_ISR_RXEND_Pos        (1U)

+#define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                  /*!< 0x00000002 */

+#define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                      */

+#define CEC_ISR_RXOVR_Pos        (2U)

+#define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                  /*!< 0x00000004 */

+#define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                            */

+#define CEC_ISR_BRE_Pos          (3U)

+#define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                    /*!< 0x00000008 */

+#define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                   */

+#define CEC_ISR_SBPE_Pos         (4U)

+#define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                   /*!< 0x00000010 */

+#define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error             */

+#define CEC_ISR_LBPE_Pos         (5U)

+#define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                   /*!< 0x00000020 */

+#define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error              */

+#define CEC_ISR_RXACKE_Pos       (6U)

+#define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                 /*!< 0x00000040 */

+#define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge                */

+#define CEC_ISR_ARBLST_Pos       (7U)

+#define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                 /*!< 0x00000080 */

+#define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                      */

+#define CEC_ISR_TXBR_Pos         (8U)

+#define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                   /*!< 0x00000100 */

+#define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                       */

+#define CEC_ISR_TXEND_Pos        (9U)

+#define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                  /*!< 0x00000200 */

+#define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                   */

+#define CEC_ISR_TXUDR_Pos        (10U)

+#define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                  /*!< 0x00000400 */

+#define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                    */

+#define CEC_ISR_TXERR_Pos        (11U)

+#define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                  /*!< 0x00000800 */

+#define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                              */

+#define CEC_ISR_TXACKE_Pos       (12U)

+#define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                 /*!< 0x00001000 */

+#define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge                */

+

+/*******************  Bit definition for CEC_IER register  ********************/

+#define CEC_IER_RXBRIE_Pos       (0U)

+#define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                 /*!< 0x00000001 */

+#define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable            */

+#define CEC_IER_RXENDIE_Pos      (1U)

+#define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                /*!< 0x00000002 */

+#define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable            */

+#define CEC_IER_RXOVRIE_Pos      (2U)

+#define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                /*!< 0x00000004 */

+#define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable                  */

+#define CEC_IER_BREIE_Pos        (3U)

+#define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                  /*!< 0x00000008 */

+#define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable         */

+#define CEC_IER_SBPEIE_Pos       (4U)

+#define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                 /*!< 0x00000010 */

+#define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable   */

+#define CEC_IER_LBPEIE_Pos       (5U)

+#define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                 /*!< 0x00000020 */

+#define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable    */

+#define CEC_IER_RXACKEIE_Pos     (6U)

+#define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)               /*!< 0x00000040 */

+#define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable      */

+#define CEC_IER_ARBLSTIE_Pos     (7U)

+#define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)               /*!< 0x00000080 */

+#define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable            */

+#define CEC_IER_TXBRIE_Pos       (8U)

+#define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                 /*!< 0x00000100 */

+#define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable            */

+#define CEC_IER_TXENDIE_Pos      (9U)

+#define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                /*!< 0x00000200 */

+#define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable         */

+#define CEC_IER_TXUDRIE_Pos      (10U)

+#define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                /*!< 0x00000400 */

+#define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable          */

+#define CEC_IER_TXERRIE_Pos      (11U)

+#define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                /*!< 0x00000800 */

+#define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                    */

+#define CEC_IER_TXACKEIE_Pos     (12U)

+#define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)               /*!< 0x00001000 */

+#define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable      */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          CRC calculation unit                              */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for CRC_DR register  *********************/

+#define CRC_DR_DR_Pos            (0U)

+#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */

+#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */

+

+/*******************  Bit definition for CRC_IDR register  ********************/

+#define CRC_IDR_IDR_Pos          (0U)

+#define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */

+#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */

+

+/********************  Bit definition for CRC_CR register  ********************/

+#define CRC_CR_RESET_Pos         (0U)

+#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */

+#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */

+#define CRC_CR_POLYSIZE_Pos      (3U)

+#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */

+#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */

+#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */

+#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */

+#define CRC_CR_REV_IN_Pos        (5U)

+#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */

+#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */

+#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */

+#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */

+#define CRC_CR_REV_OUT_Pos       (7U)

+#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */

+#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */

+

+/*******************  Bit definition for CRC_INIT register  *******************/

+#define CRC_INIT_INIT_Pos        (0U)

+#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */

+#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */

+

+/*******************  Bit definition for CRC_POL register  ********************/

+#define CRC_POL_POL_Pos          (0U)

+#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */

+#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          CRS Clock Recovery System                         */

+/******************************************************************************/

+

+/*******************  Bit definition for CRS_CR register  *********************/

+#define CRS_CR_SYNCOKIE_Pos       (0U)

+#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */

+#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */

+#define CRS_CR_SYNCWARNIE_Pos     (1U)

+#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */

+#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */

+#define CRS_CR_ERRIE_Pos          (2U)

+#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */

+#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */

+#define CRS_CR_ESYNCIE_Pos        (3U)

+#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */

+#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */

+#define CRS_CR_CEN_Pos            (5U)

+#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */

+#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */

+#define CRS_CR_AUTOTRIMEN_Pos     (6U)

+#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */

+#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */

+#define CRS_CR_SWSYNC_Pos         (7U)

+#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */

+#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */

+#define CRS_CR_TRIM_Pos           (8U)

+#define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00003F00 */

+#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */

+

+/*******************  Bit definition for CRS_CFGR register  *********************/

+#define CRS_CFGR_RELOAD_Pos       (0U)

+#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */

+#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */

+#define CRS_CFGR_FELIM_Pos        (16U)

+#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */

+#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */

+

+#define CRS_CFGR_SYNCDIV_Pos      (24U)

+#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */

+#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */

+#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */

+#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */

+#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */

+

+#define CRS_CFGR_SYNCSRC_Pos      (28U)

+#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */

+#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */

+#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */

+#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */

+

+#define CRS_CFGR_SYNCPOL_Pos      (31U)

+#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */

+#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */

+

+/*******************  Bit definition for CRS_ISR register  *********************/

+#define CRS_ISR_SYNCOKF_Pos       (0U)

+#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */

+#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */

+#define CRS_ISR_SYNCWARNF_Pos     (1U)

+#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */

+#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */

+#define CRS_ISR_ERRF_Pos          (2U)

+#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */

+#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */

+#define CRS_ISR_ESYNCF_Pos        (3U)

+#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */

+#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */

+#define CRS_ISR_SYNCERR_Pos       (8U)

+#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */

+#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */

+#define CRS_ISR_SYNCMISS_Pos      (9U)

+#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */

+#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */

+#define CRS_ISR_TRIMOVF_Pos       (10U)

+#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */

+#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */

+#define CRS_ISR_FEDIR_Pos         (15U)

+#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */

+#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */

+#define CRS_ISR_FECAP_Pos         (16U)

+#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */

+#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */

+

+/*******************  Bit definition for CRS_ICR register  *********************/

+#define CRS_ICR_SYNCOKC_Pos       (0U)

+#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */

+#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */

+#define CRS_ICR_SYNCWARNC_Pos     (1U)

+#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */

+#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */

+#define CRS_ICR_ERRC_Pos          (2U)

+#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */

+#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */

+#define CRS_ICR_ESYNCC_Pos        (3U)

+#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */

+#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      Digital to Analog Converter                           */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for DAC_CR register  ********************/

+#define DAC_CR_EN1_Pos              (0U)

+#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */

+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */

+#define DAC_CR_TEN1_Pos             (1U)

+#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */

+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */

+

+#define DAC_CR_TSEL1_Pos            (2U)

+#define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */

+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */

+#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000004 */

+#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */

+#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */

+#define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */

+

+

+#define DAC_CR_WAVE1_Pos            (6U)

+#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */

+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */

+#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */

+#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */

+

+#define DAC_CR_MAMP1_Pos            (8U)

+#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */

+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */

+#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */

+#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */

+#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */

+#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */

+

+#define DAC_CR_DMAEN1_Pos           (12U)

+#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */

+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */

+#define DAC_CR_DMAUDRIE1_Pos        (13U)

+#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */

+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/

+#define DAC_CR_CEN1_Pos             (14U)

+#define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */

+#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/

+

+#define DAC_CR_EN2_Pos              (16U)

+#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */

+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */

+#define DAC_CR_TEN2_Pos             (17U)

+#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */

+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */

+

+#define DAC_CR_TSEL2_Pos            (18U)

+#define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */

+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */

+#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00040000 */

+#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */

+#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */

+#define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */

+

+

+#define DAC_CR_WAVE2_Pos            (22U)

+#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */

+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */

+#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */

+#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */

+

+#define DAC_CR_MAMP2_Pos            (24U)

+#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */

+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */

+#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */

+#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */

+#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */

+#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */

+

+#define DAC_CR_DMAEN2_Pos           (28U)

+#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */

+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */

+#define DAC_CR_DMAUDRIE2_Pos        (29U)

+#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */

+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/

+#define DAC_CR_CEN2_Pos             (30U)

+#define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */

+#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/

+

+/*****************  Bit definition for DAC_SWTRIGR register  ******************/

+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)

+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */

+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */

+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)

+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */

+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */

+

+/*****************  Bit definition for DAC_DHR12R1 register  ******************/

+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)

+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12L1 register  ******************/

+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)

+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8R1 register  ******************/

+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)

+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12R2 register  ******************/

+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)

+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12L2 register  ******************/

+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)

+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8R2 register  ******************/

+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)

+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12RD register  ******************/

+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)

+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */

+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)

+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */

+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12LD register  ******************/

+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)

+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */

+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)

+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */

+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8RD register  ******************/

+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)

+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */

+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)

+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */

+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */

+

+/*******************  Bit definition for DAC_DOR1 register  *******************/

+#define DAC_DOR1_DACC1DOR_Pos       (0U)

+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */

+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */

+

+/*******************  Bit definition for DAC_DOR2 register  *******************/

+#define DAC_DOR2_DACC2DOR_Pos       (0U)

+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */

+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */

+

+/********************  Bit definition for DAC_SR register  ********************/

+#define DAC_SR_DMAUDR1_Pos          (13U)

+#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */

+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */

+#define DAC_SR_CAL_FLAG1_Pos        (14U)

+#define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */

+#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */

+#define DAC_SR_BWST1_Pos            (15U)

+#define DAC_SR_BWST1_Msk            (0x4001UL << DAC_SR_BWST1_Pos)             /*!< 0x20008000 */

+#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */

+

+#define DAC_SR_DMAUDR2_Pos          (29U)

+#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */

+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */

+#define DAC_SR_CAL_FLAG2_Pos        (30U)

+#define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */

+#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */

+#define DAC_SR_BWST2_Pos            (31U)

+#define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */

+#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */

+

+/*******************  Bit definition for DAC_CCR register  ********************/

+#define DAC_CCR_OTRIM1_Pos          (0U)

+#define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */

+#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */

+#define DAC_CCR_OTRIM2_Pos          (16U)

+#define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */

+#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */

+

+/*******************  Bit definition for DAC_MCR register  *******************/

+#define DAC_MCR_MODE1_Pos           (0U)

+#define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */

+#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */

+#define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */

+#define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */

+#define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */

+

+#define DAC_MCR_MODE2_Pos           (16U)

+#define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */

+#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */

+#define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */

+#define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */

+#define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */

+

+/******************  Bit definition for DAC_SHSR1 register  ******************/

+#define DAC_SHSR1_TSAMPLE1_Pos      (0U)

+#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */

+#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */

+

+/******************  Bit definition for DAC_SHSR2 register  ******************/

+#define DAC_SHSR2_TSAMPLE2_Pos      (0U)

+#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */

+#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */

+

+/******************  Bit definition for DAC_SHHR register  ******************/

+#define DAC_SHHR_THOLD1_Pos         (0U)

+#define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */

+#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */

+#define DAC_SHHR_THOLD2_Pos         (16U)

+#define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */

+#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */

+

+/******************  Bit definition for DAC_SHRR register  ******************/

+#define DAC_SHRR_TREFRESH1_Pos      (0U)

+#define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */

+#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */

+#define DAC_SHRR_TREFRESH2_Pos      (16U)

+#define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */

+#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    DCMI                                    */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DCMI_CR register  ******************/

+#define DCMI_CR_CAPTURE_Pos        (0U)

+#define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)              /*!< 0x00000001 */

+#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk

+#define DCMI_CR_CM_Pos             (1U)

+#define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                   /*!< 0x00000002 */

+#define DCMI_CR_CM                 DCMI_CR_CM_Msk

+#define DCMI_CR_CROP_Pos           (2U)

+#define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                 /*!< 0x00000004 */

+#define DCMI_CR_CROP               DCMI_CR_CROP_Msk

+#define DCMI_CR_JPEG_Pos           (3U)

+#define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                 /*!< 0x00000008 */

+#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk

+#define DCMI_CR_ESS_Pos            (4U)

+#define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                  /*!< 0x00000010 */

+#define DCMI_CR_ESS                DCMI_CR_ESS_Msk

+#define DCMI_CR_PCKPOL_Pos         (5U)

+#define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)               /*!< 0x00000020 */

+#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk

+#define DCMI_CR_HSPOL_Pos          (6U)

+#define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                /*!< 0x00000040 */

+#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk

+#define DCMI_CR_VSPOL_Pos          (7U)

+#define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */

+#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk

+#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)

+#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)

+#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)

+#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)

+#define DCMI_CR_CRE_Pos            (12U)

+#define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */

+#define DCMI_CR_CRE                DCMI_CR_CRE_Msk

+#define DCMI_CR_ENABLE_Pos         (14U)

+#define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)               /*!< 0x00004000 */

+#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk

+#define DCMI_CR_BSM_Pos            (16U)

+#define DCMI_CR_BSM_Msk            (0x3UL << DCMI_CR_BSM_Pos)                  /*!< 0x00030000 */

+#define DCMI_CR_BSM                DCMI_CR_BSM_Msk

+#define DCMI_CR_BSM_0              (0x1UL << DCMI_CR_BSM_Pos)                   /*!< 0x00010000 */

+#define DCMI_CR_BSM_1              (0x2UL << DCMI_CR_BSM_Pos)                   /*!< 0x00020000 */

+#define DCMI_CR_OEBS_Pos           (18U)

+#define DCMI_CR_OEBS_Msk           (0x1UL << DCMI_CR_OEBS_Pos)                 /*!< 0x00040000 */

+#define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk

+#define DCMI_CR_LSM_Pos            (19U)

+#define DCMI_CR_LSM_Msk            (0x1UL << DCMI_CR_LSM_Pos)                  /*!< 0x00080000 */

+#define DCMI_CR_LSM                DCMI_CR_LSM_Msk

+#define DCMI_CR_OELS_Pos           (20U)

+#define DCMI_CR_OELS_Msk           (0x1UL << DCMI_CR_OELS_Pos)                 /*!< 0x00100000 */

+#define DCMI_CR_OELS               DCMI_CR_OELS_Msk

+

+/********************  Bits definition for DCMI_SR register  ******************/

+#define DCMI_SR_HSYNC_Pos          (0U)

+#define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                /*!< 0x00000001 */

+#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk

+#define DCMI_SR_VSYNC_Pos          (1U)

+#define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                /*!< 0x00000002 */

+#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk

+#define DCMI_SR_FNE_Pos            (2U)

+#define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                  /*!< 0x00000004 */

+#define DCMI_SR_FNE                DCMI_SR_FNE_Msk

+

+/********************  Bits definition for DCMI_RIS register   ****************/

+#define DCMI_RIS_FRAME_RIS_Pos     (0U)

+#define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)           /*!< 0x00000001 */

+#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk

+#define DCMI_RIS_OVR_RIS_Pos       (1U)

+#define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)             /*!< 0x00000002 */

+#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk

+#define DCMI_RIS_ERR_RIS_Pos       (2U)

+#define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)             /*!< 0x00000004 */

+#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk

+#define DCMI_RIS_VSYNC_RIS_Pos     (3U)

+#define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)           /*!< 0x00000008 */

+#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk

+#define DCMI_RIS_LINE_RIS_Pos      (4U)

+#define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)            /*!< 0x00000010 */

+#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk

+

+/********************  Bits definition for DCMI_IER register  *****************/

+#define DCMI_IER_FRAME_IE_Pos      (0U)

+#define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)            /*!< 0x00000001 */

+#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk

+#define DCMI_IER_OVR_IE_Pos        (1U)

+#define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)              /*!< 0x00000002 */

+#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk

+#define DCMI_IER_ERR_IE_Pos        (2U)

+#define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)              /*!< 0x00000004 */

+#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk

+#define DCMI_IER_VSYNC_IE_Pos      (3U)

+#define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)            /*!< 0x00000008 */

+#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk

+#define DCMI_IER_LINE_IE_Pos       (4U)

+#define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)             /*!< 0x00000010 */

+#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk

+

+

+/********************  Bits definition for DCMI_MIS register  *****************/

+#define DCMI_MIS_FRAME_MIS_Pos     (0U)

+#define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)           /*!< 0x00000001 */

+#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk

+#define DCMI_MIS_OVR_MIS_Pos       (1U)

+#define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)             /*!< 0x00000002 */

+#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk

+#define DCMI_MIS_ERR_MIS_Pos       (2U)

+#define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)             /*!< 0x00000004 */

+#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk

+#define DCMI_MIS_VSYNC_MIS_Pos     (3U)

+#define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)           /*!< 0x00000008 */

+#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk

+#define DCMI_MIS_LINE_MIS_Pos      (4U)

+#define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)            /*!< 0x00000010 */

+#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk

+

+

+/********************  Bits definition for DCMI_ICR register  *****************/

+#define DCMI_ICR_FRAME_ISC_Pos     (0U)

+#define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)           /*!< 0x00000001 */

+#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk

+#define DCMI_ICR_OVR_ISC_Pos       (1U)

+#define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)             /*!< 0x00000002 */

+#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk

+#define DCMI_ICR_ERR_ISC_Pos       (2U)

+#define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)             /*!< 0x00000004 */

+#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk

+#define DCMI_ICR_VSYNC_ISC_Pos     (3U)

+#define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)           /*!< 0x00000008 */

+#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk

+#define DCMI_ICR_LINE_ISC_Pos      (4U)

+#define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)            /*!< 0x00000010 */

+#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk

+

+

+/********************  Bits definition for DCMI_ESCR register  ******************/

+#define DCMI_ESCR_FSC_Pos          (0U)

+#define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)               /*!< 0x000000FF */

+#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk

+#define DCMI_ESCR_LSC_Pos          (8U)

+#define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)               /*!< 0x0000FF00 */

+#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk

+#define DCMI_ESCR_LEC_Pos          (16U)

+#define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)               /*!< 0x00FF0000 */

+#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk

+#define DCMI_ESCR_FEC_Pos          (24U)

+#define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)               /*!< 0xFF000000 */

+#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk

+

+/********************  Bits definition for DCMI_ESUR register  ******************/

+#define DCMI_ESUR_FSU_Pos          (0U)

+#define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)               /*!< 0x000000FF */

+#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk

+#define DCMI_ESUR_LSU_Pos          (8U)

+#define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)               /*!< 0x0000FF00 */

+#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk

+#define DCMI_ESUR_LEU_Pos          (16U)

+#define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)               /*!< 0x00FF0000 */

+#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk

+#define DCMI_ESUR_FEU_Pos          (24U)

+#define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)               /*!< 0xFF000000 */

+#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk

+

+/********************  Bits definition for DCMI_CWSTRT register  ******************/

+#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)

+#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)       /*!< 0x00003FFF */

+#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk

+#define DCMI_CWSTRT_VST_Pos        (16U)

+#define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)           /*!< 0x1FFF0000 */

+#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk

+

+/********************  Bits definition for DCMI_CWSIZE register  ******************/

+#define DCMI_CWSIZE_CAPCNT_Pos     (0U)

+#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)        /*!< 0x00003FFF */

+#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk

+#define DCMI_CWSIZE_VLINE_Pos      (16U)

+#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)         /*!< 0x3FFF0000 */

+#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk

+

+/********************  Bits definition for DCMI_DR register  ******************/

+#define DCMI_DR_BYTE0_Pos          (0U)

+#define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)               /*!< 0x000000FF */

+#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk

+#define DCMI_DR_BYTE1_Pos          (8U)

+#define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)               /*!< 0x0000FF00 */

+#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk

+#define DCMI_DR_BYTE2_Pos          (16U)

+#define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)               /*!< 0x00FF0000 */

+#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk

+#define DCMI_DR_BYTE3_Pos          (24U)

+#define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)               /*!< 0xFF000000 */

+#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                 Digital Filter for Sigma Delta Modulators                  */

+/*                                                                            */

+/******************************************************************************/

+

+/****************   DFSDM channel configuration registers  ********************/

+

+/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/

+#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)

+#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)   /*!< 0x80000000 */

+#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */

+#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)

+#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)  /*!< 0x40000000 */

+#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */

+#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)

+#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */

+#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */

+#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)

+#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x0000C000 */

+#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */

+#define DFSDM_CHCFGR1_DATPACK_1         (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */

+#define DFSDM_CHCFGR1_DATPACK_0         (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */

+#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)

+#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00003000 */

+#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */

+#define DFSDM_CHCFGR1_DATMPX_1          (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */

+#define DFSDM_CHCFGR1_DATMPX_0          (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */

+#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)

+#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)   /*!< 0x00000100 */

+#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */

+#define DFSDM_CHCFGR1_CHEN_Pos          (7U)

+#define DFSDM_CHCFGR1_CHEN_Msk          (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)      /*!< 0x00000080 */

+#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */

+#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)

+#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)    /*!< 0x00000040 */

+#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */

+#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)

+#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)     /*!< 0x00000020 */

+#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */

+#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)

+#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x0000000C */

+#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */

+#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */

+#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */

+#define DFSDM_CHCFGR1_SITP_Pos          (0U)

+#define DFSDM_CHCFGR1_SITP_Msk          (0x3UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000003 */

+#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */

+#define DFSDM_CHCFGR1_SITP_1            (0x2UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */

+#define DFSDM_CHCFGR1_SITP_0            (0x1UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */

+

+/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/

+#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)

+#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */

+#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)

+#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)    /*!< 0x000000F8 */

+#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */

+

+/******************  Bit definition for DFSDM_CHAWSCDR register *****************/

+#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)

+#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00C00000 */

+#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */

+#define DFSDM_CHAWSCDR_AWFORD_1         (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */

+#define DFSDM_CHAWSCDR_AWFORD_0         (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */

+#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)

+#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)  /*!< 0x001F0000 */

+#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */

+#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)

+#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)    /*!< 0x0000F000 */

+#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */

+#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)

+#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)    /*!< 0x000000FF */

+#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */

+

+/****************  Bit definition for DFSDM_CHWDATR register *******************/

+#define DFSDM_CHWDATR_WDATA_Pos         (0U)

+#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)  /*!< 0x0000FFFF */

+#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */

+

+/****************  Bit definition for DFSDM_CHDATINR register *****************/

+#define DFSDM_CHDATINR_INDAT0_Pos       (0U)

+#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */

+#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */

+#define DFSDM_CHDATINR_INDAT1_Pos       (16U)

+#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */

+#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */

+

+/************************   DFSDM module registers  ****************************/

+

+/********************  Bit definition for DFSDM_FLTCR1 register *******************/

+#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)

+#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)     /*!< 0x40000000 */

+#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */

+#define DFSDM_FLTCR1_FAST_Pos           (29U)

+#define DFSDM_FLTCR1_FAST_Msk           (0x1UL << DFSDM_FLTCR1_FAST_Pos)       /*!< 0x20000000 */

+#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */

+#define DFSDM_FLTCR1_RCH_Pos            (24U)

+#define DFSDM_FLTCR1_RCH_Msk            (0x7UL << DFSDM_FLTCR1_RCH_Pos)        /*!< 0x07000000 */

+#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */

+#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)

+#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)     /*!< 0x00200000 */

+#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */

+#define DFSDM_FLTCR1_RSYNC_Pos          (19U)

+#define DFSDM_FLTCR1_RSYNC_Msk          (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)      /*!< 0x00080000 */

+#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */

+#define DFSDM_FLTCR1_RCONT_Pos          (18U)

+#define DFSDM_FLTCR1_RCONT_Msk          (0x1UL << DFSDM_FLTCR1_RCONT_Pos)      /*!< 0x00040000 */

+#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */

+#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)

+#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)   /*!< 0x00020000 */

+#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */

+#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)

+#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00006000 */

+#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */

+#define DFSDM_FLTCR1_JEXTEN_1           (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */

+#define DFSDM_FLTCR1_JEXTEN_0           (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */

+#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)

+#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)   /*!< 0x00001F00 */

+#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */

+#define DFSDM_FLTCR1_JEXTSEL_0          (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000100 */

+#define DFSDM_FLTCR1_JEXTSEL_1          (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000200 */

+#define DFSDM_FLTCR1_JEXTSEL_2          (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000400 */

+#define DFSDM_FLTCR1_JEXTSEL_3          (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000800 */

+#define DFSDM_FLTCR1_JEXTSEL_4          (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00001000 */

+

+#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)

+#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)     /*!< 0x00000020 */

+#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */

+#define DFSDM_FLTCR1_JSCAN_Pos          (4U)

+#define DFSDM_FLTCR1_JSCAN_Msk          (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)      /*!< 0x00000010 */

+#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */

+#define DFSDM_FLTCR1_JSYNC_Pos          (3U)

+#define DFSDM_FLTCR1_JSYNC_Msk          (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)      /*!< 0x00000008 */

+#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */

+#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)

+#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)   /*!< 0x00000002 */

+#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */

+#define DFSDM_FLTCR1_DFEN_Pos           (0U)

+#define DFSDM_FLTCR1_DFEN_Msk           (0x1UL << DFSDM_FLTCR1_DFEN_Pos)       /*!< 0x00000001 */

+#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */

+

+/********************  Bit definition for DFSDM_FLTCR2 register *******************/

+#define DFSDM_FLTCR2_AWDCH_Pos          (16U)

+#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)     /*!< 0x00FF0000 */

+#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */

+#define DFSDM_FLTCR2_EXCH_Pos           (8U)

+#define DFSDM_FLTCR2_EXCH_Msk           (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)      /*!< 0x0000FF00 */

+#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */

+#define DFSDM_FLTCR2_CKABIE_Pos         (6U)

+#define DFSDM_FLTCR2_CKABIE_Msk         (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)     /*!< 0x00000040 */

+#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */

+#define DFSDM_FLTCR2_SCDIE_Pos          (5U)

+#define DFSDM_FLTCR2_SCDIE_Msk          (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)      /*!< 0x00000020 */

+#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */

+#define DFSDM_FLTCR2_AWDIE_Pos          (4U)

+#define DFSDM_FLTCR2_AWDIE_Msk          (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)      /*!< 0x00000010 */

+#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */

+#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)

+#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)     /*!< 0x00000008 */

+#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */

+#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)

+#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)     /*!< 0x00000004 */

+#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */

+#define DFSDM_FLTCR2_REOCIE_Pos         (1U)

+#define DFSDM_FLTCR2_REOCIE_Msk         (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)     /*!< 0x00000002 */

+#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */

+#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)

+#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)     /*!< 0x00000001 */

+#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */

+

+/********************  Bit definition for DFSDM_FLTISR register *******************/

+#define DFSDM_FLTISR_SCDF_Pos           (24U)

+#define DFSDM_FLTISR_SCDF_Msk           (0xFFUL << DFSDM_FLTISR_SCDF_Pos)      /*!< 0xFF000000 */

+#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */

+#define DFSDM_FLTISR_CKABF_Pos          (16U)

+#define DFSDM_FLTISR_CKABF_Msk          (0xFFUL << DFSDM_FLTISR_CKABF_Pos)     /*!< 0x00FF0000 */

+#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */

+#define DFSDM_FLTISR_RCIP_Pos           (14U)

+#define DFSDM_FLTISR_RCIP_Msk           (0x1UL << DFSDM_FLTISR_RCIP_Pos)       /*!< 0x00004000 */

+#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */

+#define DFSDM_FLTISR_JCIP_Pos           (13U)

+#define DFSDM_FLTISR_JCIP_Msk           (0x1UL << DFSDM_FLTISR_JCIP_Pos)       /*!< 0x00002000 */

+#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */

+#define DFSDM_FLTISR_AWDF_Pos           (4U)

+#define DFSDM_FLTISR_AWDF_Msk           (0x1UL << DFSDM_FLTISR_AWDF_Pos)       /*!< 0x00000010 */

+#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */

+#define DFSDM_FLTISR_ROVRF_Pos          (3U)

+#define DFSDM_FLTISR_ROVRF_Msk          (0x1UL << DFSDM_FLTISR_ROVRF_Pos)      /*!< 0x00000008 */

+#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */

+#define DFSDM_FLTISR_JOVRF_Pos          (2U)

+#define DFSDM_FLTISR_JOVRF_Msk          (0x1UL << DFSDM_FLTISR_JOVRF_Pos)      /*!< 0x00000004 */

+#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */

+#define DFSDM_FLTISR_REOCF_Pos          (1U)

+#define DFSDM_FLTISR_REOCF_Msk          (0x1UL << DFSDM_FLTISR_REOCF_Pos)      /*!< 0x00000002 */

+#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */

+#define DFSDM_FLTISR_JEOCF_Pos          (0U)

+#define DFSDM_FLTISR_JEOCF_Msk          (0x1UL << DFSDM_FLTISR_JEOCF_Pos)      /*!< 0x00000001 */

+#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */

+

+/********************  Bit definition for DFSDM_FLTICR register *******************/

+#define DFSDM_FLTICR_CLRSCDF_Pos        (24U)

+#define DFSDM_FLTICR_CLRSCDF_Msk        (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)   /*!< 0xFF000000 */

+#define DFSDM_FLTICR_CLRSCDF            DFSDM_FLTICR_CLRSCDF_Msk               /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */

+#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)

+#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)  /*!< 0x00FF0000 */

+#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */

+#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)

+#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)   /*!< 0x00000008 */

+#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */

+#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)

+#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)   /*!< 0x00000004 */

+#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */

+

+/*******************  Bit definition for DFSDM_FLTJCHGR register ******************/

+#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)

+#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)    /*!< 0x000000FF */

+#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */

+

+/********************  Bit definition for DFSDM_FLTFCR register *******************/

+#define DFSDM_FLTFCR_FORD_Pos           (29U)

+#define DFSDM_FLTFCR_FORD_Msk           (0x7UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0xE0000000 */

+#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */

+#define DFSDM_FLTFCR_FORD_2             (0x4UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */

+#define DFSDM_FLTFCR_FORD_1             (0x2UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */

+#define DFSDM_FLTFCR_FORD_0             (0x1UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */

+#define DFSDM_FLTFCR_FOSR_Pos           (16U)

+#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)     /*!< 0x03FF0000 */

+#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */

+#define DFSDM_FLTFCR_IOSR_Pos           (0U)

+#define DFSDM_FLTFCR_IOSR_Msk           (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)      /*!< 0x000000FF */

+#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */

+

+/******************  Bit definition for DFSDM_FLTJDATAR register *****************/

+#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)

+#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */

+#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)

+#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */

+#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */

+

+/******************  Bit definition for DFSDM_FLTRDATAR register *****************/

+#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)

+#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */

+#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)

+#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)   /*!< 0x00000010 */

+#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */

+#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)

+#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */

+#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */

+

+/******************  Bit definition for DFSDM_FLTAWHTR register ******************/

+#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)

+#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */

+#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)

+#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)    /*!< 0x0000000F */

+#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */

+

+/******************  Bit definition for DFSDM_FLTAWLTR register ******************/

+#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)

+#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWHT[23:0] Analog watchdog low threshold */

+#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)

+#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)    /*!< 0x0000000F */

+#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */

+

+/******************  Bit definition for DFSDM_FLTAWSR register ******************/

+#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)

+#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)    /*!< 0x0000FF00 */

+#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */

+#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)

+#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)    /*!< 0x000000FF */

+#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */

+

+/******************  Bit definition for DFSDM_FLTAWCFR) register *****************/

+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)

+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */

+#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */

+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)

+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */

+#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */

+

+/******************  Bit definition for DFSDM_FLTEXMAX register ******************/

+#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)

+#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */

+#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)

+#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)  /*!< 0x00000007 */

+#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */

+

+/******************  Bit definition for DFSDM_FLTEXMIN register ******************/

+#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)

+#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */

+#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)

+#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)  /*!< 0x00000007 */

+#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */

+

+/******************  Bit definition for DFSDM_FLTCNVTIMR register ******************/

+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)

+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */

+#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           BDMA Controller                                  */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for BDMA_ISR register  ********************/

+#define BDMA_ISR_GIF0_Pos       (0U)

+#define BDMA_ISR_GIF0_Msk       (0x1UL << BDMA_ISR_GIF0_Pos)                   /*!< 0x00000001 */

+#define BDMA_ISR_GIF0           BDMA_ISR_GIF0_Msk                              /*!< Channel 0 Global interrupt flag */

+#define BDMA_ISR_TCIF0_Pos      (1U)

+#define BDMA_ISR_TCIF0_Msk      (0x1UL << BDMA_ISR_TCIF0_Pos)                  /*!< 0x00000002 */

+#define BDMA_ISR_TCIF0          BDMA_ISR_TCIF0_Msk                             /*!< Channel 0 Transfer Complete flag */

+#define BDMA_ISR_HTIF0_Pos      (2U)

+#define BDMA_ISR_HTIF0_Msk      (0x1UL << BDMA_ISR_HTIF0_Pos)                  /*!< 0x00000004 */

+#define BDMA_ISR_HTIF0          BDMA_ISR_HTIF0_Msk                             /*!< Channel 0 Half Transfer flag */

+#define BDMA_ISR_TEIF0_Pos      (3U)

+#define BDMA_ISR_TEIF0_Msk      (0x1UL << BDMA_ISR_TEIF0_Pos)                  /*!< 0x00000008 */

+#define BDMA_ISR_TEIF0          BDMA_ISR_TEIF0_Msk                             /*!< Channel 0 Transfer Error flag */

+#define BDMA_ISR_GIF1_Pos       (4U)

+#define BDMA_ISR_GIF1_Msk       (0x1UL << BDMA_ISR_GIF1_Pos)                   /*!< 0x00000010 */

+#define BDMA_ISR_GIF1           BDMA_ISR_GIF1_Msk                              /*!< Channel 1 Global interrupt flag */

+#define BDMA_ISR_TCIF1_Pos      (5U)

+#define BDMA_ISR_TCIF1_Msk      (0x1UL << BDMA_ISR_TCIF1_Pos)                  /*!< 0x00000020 */

+#define BDMA_ISR_TCIF1          BDMA_ISR_TCIF1_Msk                             /*!< Channel 1 Transfer Complete flag */

+#define BDMA_ISR_HTIF1_Pos      (6U)

+#define BDMA_ISR_HTIF1_Msk      (0x1UL << BDMA_ISR_HTIF1_Pos)                  /*!< 0x00000040 */

+#define BDMA_ISR_HTIF1          BDMA_ISR_HTIF1_Msk                             /*!< Channel 1 Half Transfer flag */

+#define BDMA_ISR_TEIF1_Pos      (7U)

+#define BDMA_ISR_TEIF1_Msk      (0x1UL << BDMA_ISR_TEIF1_Pos)                  /*!< 0x00000080 */

+#define BDMA_ISR_TEIF1          BDMA_ISR_TEIF1_Msk                             /*!< Channel 1 Transfer Error flag */

+#define BDMA_ISR_GIF2_Pos       (8U)

+#define BDMA_ISR_GIF2_Msk       (0x1UL << BDMA_ISR_GIF2_Pos)                   /*!< 0x00000100 */

+#define BDMA_ISR_GIF2           BDMA_ISR_GIF2_Msk                              /*!< Channel 2 Global interrupt flag */

+#define BDMA_ISR_TCIF2_Pos      (9U)

+#define BDMA_ISR_TCIF2_Msk      (0x1UL << BDMA_ISR_TCIF2_Pos)                  /*!< 0x00000200 */

+#define BDMA_ISR_TCIF2          BDMA_ISR_TCIF2_Msk                             /*!< Channel 2 Transfer Complete flag */

+#define BDMA_ISR_HTIF2_Pos      (10U)

+#define BDMA_ISR_HTIF2_Msk      (0x1UL << BDMA_ISR_HTIF2_Pos)                  /*!< 0x00000400 */

+#define BDMA_ISR_HTIF2          BDMA_ISR_HTIF2_Msk                             /*!< Channel 2 Half Transfer flag */

+#define BDMA_ISR_TEIF2_Pos      (11U)

+#define BDMA_ISR_TEIF2_Msk      (0x1UL << BDMA_ISR_TEIF2_Pos)                  /*!< 0x00000800 */

+#define BDMA_ISR_TEIF2          BDMA_ISR_TEIF2_Msk                             /*!< Channel 2 Transfer Error flag */

+#define BDMA_ISR_GIF3_Pos       (12U)

+#define BDMA_ISR_GIF3_Msk       (0x1UL << BDMA_ISR_GIF3_Pos)                   /*!< 0x00001000 */

+#define BDMA_ISR_GIF3           BDMA_ISR_GIF3_Msk                              /*!< Channel 3 Global interrupt flag */

+#define BDMA_ISR_TCIF3_Pos      (13U)

+#define BDMA_ISR_TCIF3_Msk      (0x1UL << BDMA_ISR_TCIF3_Pos)                  /*!< 0x00002000 */

+#define BDMA_ISR_TCIF3          BDMA_ISR_TCIF3_Msk                             /*!< Channel 3 Transfer Complete flag */

+#define BDMA_ISR_HTIF3_Pos      (14U)

+#define BDMA_ISR_HTIF3_Msk      (0x1UL << BDMA_ISR_HTIF3_Pos)                  /*!< 0x00004000 */

+#define BDMA_ISR_HTIF3          BDMA_ISR_HTIF3_Msk                             /*!< Channel 3 Half Transfer flag */

+#define BDMA_ISR_TEIF3_Pos      (15U)

+#define BDMA_ISR_TEIF3_Msk      (0x1UL << BDMA_ISR_TEIF3_Pos)                  /*!< 0x00008000 */

+#define BDMA_ISR_TEIF3          BDMA_ISR_TEIF3_Msk                             /*!< Channel 3 Transfer Error flag */

+#define BDMA_ISR_GIF4_Pos       (16U)

+#define BDMA_ISR_GIF4_Msk       (0x1UL << BDMA_ISR_GIF4_Pos)                   /*!< 0x00010000 */

+#define BDMA_ISR_GIF4           BDMA_ISR_GIF4_Msk                              /*!< Channel 4 Global interrupt flag */

+#define BDMA_ISR_TCIF4_Pos      (17U)

+#define BDMA_ISR_TCIF4_Msk      (0x1UL << BDMA_ISR_TCIF4_Pos)                  /*!< 0x00020000 */

+#define BDMA_ISR_TCIF4          BDMA_ISR_TCIF4_Msk                             /*!< Channel 4 Transfer Complete flag */

+#define BDMA_ISR_HTIF4_Pos      (18U)

+#define BDMA_ISR_HTIF4_Msk      (0x1UL << BDMA_ISR_HTIF4_Pos)                  /*!< 0x00040000 */

+#define BDMA_ISR_HTIF4          BDMA_ISR_HTIF4_Msk                             /*!< Channel 4 Half Transfer flag */

+#define BDMA_ISR_TEIF4_Pos      (19U)

+#define BDMA_ISR_TEIF4_Msk      (0x1UL << BDMA_ISR_TEIF4_Pos)                  /*!< 0x00080000 */

+#define BDMA_ISR_TEIF4          BDMA_ISR_TEIF4_Msk                             /*!< Channel 4 Transfer Error flag */

+#define BDMA_ISR_GIF5_Pos       (20U)

+#define BDMA_ISR_GIF5_Msk       (0x1UL << BDMA_ISR_GIF5_Pos)                   /*!< 0x00100000 */

+#define BDMA_ISR_GIF5           BDMA_ISR_GIF5_Msk                              /*!< Channel 5 Global interrupt flag */

+#define BDMA_ISR_TCIF5_Pos      (21U)

+#define BDMA_ISR_TCIF5_Msk      (0x1UL << BDMA_ISR_TCIF5_Pos)                  /*!< 0x00200000 */

+#define BDMA_ISR_TCIF5          BDMA_ISR_TCIF5_Msk                             /*!< Channel 5 Transfer Complete flag */

+#define BDMA_ISR_HTIF5_Pos      (22U)

+#define BDMA_ISR_HTIF5_Msk      (0x1UL << BDMA_ISR_HTIF5_Pos)                  /*!< 0x00400000 */

+#define BDMA_ISR_HTIF5          BDMA_ISR_HTIF5_Msk                             /*!< Channel 5 Half Transfer flag */

+#define BDMA_ISR_TEIF5_Pos      (23U)

+#define BDMA_ISR_TEIF5_Msk      (0x1UL << BDMA_ISR_TEIF5_Pos)                  /*!< 0x00800000 */

+#define BDMA_ISR_TEIF5          BDMA_ISR_TEIF5_Msk                             /*!< Channel 5 Transfer Error flag */

+#define BDMA_ISR_GIF6_Pos       (24U)

+#define BDMA_ISR_GIF6_Msk       (0x1UL << BDMA_ISR_GIF6_Pos)                   /*!< 0x01000000 */

+#define BDMA_ISR_GIF6           BDMA_ISR_GIF6_Msk                              /*!< Channel 6 Global interrupt flag */

+#define BDMA_ISR_TCIF6_Pos      (25U)

+#define BDMA_ISR_TCIF6_Msk      (0x1UL << BDMA_ISR_TCIF6_Pos)                  /*!< 0x02000000 */

+#define BDMA_ISR_TCIF6          BDMA_ISR_TCIF6_Msk                             /*!< Channel 6 Transfer Complete flag */

+#define BDMA_ISR_HTIF6_Pos      (26U)

+#define BDMA_ISR_HTIF6_Msk      (0x1UL << BDMA_ISR_HTIF6_Pos)                  /*!< 0x04000000 */

+#define BDMA_ISR_HTIF6          BDMA_ISR_HTIF6_Msk                             /*!< Channel 6 Half Transfer flag */

+#define BDMA_ISR_TEIF6_Pos      (27U)

+#define BDMA_ISR_TEIF6_Msk      (0x1UL << BDMA_ISR_TEIF6_Pos)                  /*!< 0x08000000 */

+#define BDMA_ISR_TEIF6          BDMA_ISR_TEIF6_Msk                             /*!< Channel 6 Transfer Error flag */

+#define BDMA_ISR_GIF7_Pos       (28U)

+#define BDMA_ISR_GIF7_Msk       (0x1UL << BDMA_ISR_GIF7_Pos)                   /*!< 0x10000000 */

+#define BDMA_ISR_GIF7           BDMA_ISR_GIF7_Msk                              /*!< Channel 7 Global interrupt flag */

+#define BDMA_ISR_TCIF7_Pos      (29U)

+#define BDMA_ISR_TCIF7_Msk      (0x1UL << BDMA_ISR_TCIF7_Pos)                  /*!< 0x20000000 */

+#define BDMA_ISR_TCIF7          BDMA_ISR_TCIF7_Msk                             /*!< Channel 7 Transfer Complete flag */

+#define BDMA_ISR_HTIF7_Pos      (30U)

+#define BDMA_ISR_HTIF7_Msk      (0x1UL << BDMA_ISR_HTIF7_Pos)                  /*!< 0x40000000 */

+#define BDMA_ISR_HTIF7          BDMA_ISR_HTIF7_Msk                             /*!< Channel 7 Half Transfer flag */

+#define BDMA_ISR_TEIF7_Pos      (31U)

+#define BDMA_ISR_TEIF7_Msk      (0x1UL << BDMA_ISR_TEIF7_Pos)                  /*!< 0x80000000 */

+#define BDMA_ISR_TEIF7          BDMA_ISR_TEIF7_Msk                             /*!< Channel 7 Transfer Error flag */

+

+/*******************  Bit definition for BDMA_IFCR register  *******************/

+#define BDMA_IFCR_CGIF0_Pos     (0U)

+#define BDMA_IFCR_CGIF0_Msk     (0x1UL << BDMA_IFCR_CGIF0_Pos)                 /*!< 0x00000001 */

+#define BDMA_IFCR_CGIF0         BDMA_IFCR_CGIF0_Msk                            /*!< Channel 0 Global interrupt clearr */

+#define BDMA_IFCR_CTCIF0_Pos    (1U)

+#define BDMA_IFCR_CTCIF0_Msk    (0x1UL << BDMA_IFCR_CTCIF0_Pos)                /*!< 0x00000002 */

+#define BDMA_IFCR_CTCIF0        BDMA_IFCR_CTCIF0_Msk                           /*!< Channel 0 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF0_Pos    (2U)

+#define BDMA_IFCR_CHTIF0_Msk    (0x1UL << BDMA_IFCR_CHTIF0_Pos)                /*!< 0x00000004 */

+#define BDMA_IFCR_CHTIF0        BDMA_IFCR_CHTIF0_Msk                           /*!< Channel 0 Half Transfer clear */

+#define BDMA_IFCR_CTEIF0_Pos    (3U)

+#define BDMA_IFCR_CTEIF0_Msk    (0x1UL << BDMA_IFCR_CTEIF0_Pos)                /*!< 0x00000008 */

+#define BDMA_IFCR_CTEIF0        BDMA_IFCR_CTEIF0_Msk                           /*!< Channel 0 Transfer Error clear */

+#define BDMA_IFCR_CGIF1_Pos     (4U)

+#define BDMA_IFCR_CGIF1_Msk     (0x1UL << BDMA_IFCR_CGIF1_Pos)                 /*!< 0x00000010 */

+#define BDMA_IFCR_CGIF1         BDMA_IFCR_CGIF1_Msk                            /*!< Channel 1 Global interrupt clear */

+#define BDMA_IFCR_CTCIF1_Pos    (5U)

+#define BDMA_IFCR_CTCIF1_Msk    (0x1UL << BDMA_IFCR_CTCIF1_Pos)                /*!< 0x00000020 */

+#define BDMA_IFCR_CTCIF1        BDMA_IFCR_CTCIF1_Msk                           /*!< Channel 1 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF1_Pos    (6U)

+#define BDMA_IFCR_CHTIF1_Msk    (0x1UL << BDMA_IFCR_CHTIF1_Pos)                /*!< 0x00000040 */

+#define BDMA_IFCR_CHTIF1        BDMA_IFCR_CHTIF1_Msk                           /*!< Channel 1 Half Transfer clear */

+#define BDMA_IFCR_CTEIF1_Pos    (7U)

+#define BDMA_IFCR_CTEIF1_Msk    (0x1UL << BDMA_IFCR_CTEIF1_Pos)                /*!< 0x00000080 */

+#define BDMA_IFCR_CTEIF1        BDMA_IFCR_CTEIF1_Msk                           /*!< Channel 1 Transfer Error clear */

+#define BDMA_IFCR_CGIF2_Pos     (8U)

+#define BDMA_IFCR_CGIF2_Msk     (0x1UL << BDMA_IFCR_CGIF2_Pos)                 /*!< 0x00000100 */

+#define BDMA_IFCR_CGIF2         BDMA_IFCR_CGIF2_Msk                            /*!< Channel 2 Global interrupt clear */

+#define BDMA_IFCR_CTCIF2_Pos    (9U)

+#define BDMA_IFCR_CTCIF2_Msk    (0x1UL << BDMA_IFCR_CTCIF2_Pos)                /*!< 0x00000200 */

+#define BDMA_IFCR_CTCIF2        BDMA_IFCR_CTCIF2_Msk                           /*!< Channel 2 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF2_Pos    (10U)

+#define BDMA_IFCR_CHTIF2_Msk    (0x1UL << BDMA_IFCR_CHTIF2_Pos)                /*!< 0x00000400 */

+#define BDMA_IFCR_CHTIF2        BDMA_IFCR_CHTIF2_Msk                           /*!< Channel 2 Half Transfer clear */

+#define BDMA_IFCR_CTEIF2_Pos    (11U)

+#define BDMA_IFCR_CTEIF2_Msk    (0x1UL << BDMA_IFCR_CTEIF2_Pos)                /*!< 0x00000800 */

+#define BDMA_IFCR_CTEIF2        BDMA_IFCR_CTEIF2_Msk                           /*!< Channel 2 Transfer Error clear */

+#define BDMA_IFCR_CGIF3_Pos     (12U)

+#define BDMA_IFCR_CGIF3_Msk     (0x1UL << BDMA_IFCR_CGIF3_Pos)                 /*!< 0x00001000 */

+#define BDMA_IFCR_CGIF3         BDMA_IFCR_CGIF3_Msk                            /*!< Channel 3 Global interrupt clear */

+#define BDMA_IFCR_CTCIF3_Pos    (13U)

+#define BDMA_IFCR_CTCIF3_Msk    (0x1UL << BDMA_IFCR_CTCIF3_Pos)                /*!< 0x00002000 */

+#define BDMA_IFCR_CTCIF3        BDMA_IFCR_CTCIF3_Msk                           /*!< Channel 3 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF3_Pos    (14U)

+#define BDMA_IFCR_CHTIF3_Msk    (0x1UL << BDMA_IFCR_CHTIF3_Pos)                /*!< 0x00004000 */

+#define BDMA_IFCR_CHTIF3        BDMA_IFCR_CHTIF3_Msk                           /*!< Channel 3 Half Transfer clear */

+#define BDMA_IFCR_CTEIF3_Pos    (15U)

+#define BDMA_IFCR_CTEIF3_Msk    (0x1UL << BDMA_IFCR_CTEIF3_Pos)                /*!< 0x00008000 */

+#define BDMA_IFCR_CTEIF3        BDMA_IFCR_CTEIF3_Msk                           /*!< Channel 3 Transfer Error clear */

+#define BDMA_IFCR_CGIF4_Pos     (16U)

+#define BDMA_IFCR_CGIF4_Msk     (0x1UL << BDMA_IFCR_CGIF4_Pos)                 /*!< 0x00010000 */

+#define BDMA_IFCR_CGIF4         BDMA_IFCR_CGIF4_Msk                            /*!< Channel 4 Global interrupt clear */

+#define BDMA_IFCR_CTCIF4_Pos    (17U)

+#define BDMA_IFCR_CTCIF4_Msk    (0x1UL << BDMA_IFCR_CTCIF4_Pos)                /*!< 0x00020000 */

+#define BDMA_IFCR_CTCIF4        BDMA_IFCR_CTCIF4_Msk                           /*!< Channel 4 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF4_Pos    (18U)

+#define BDMA_IFCR_CHTIF4_Msk    (0x1UL << BDMA_IFCR_CHTIF4_Pos)                /*!< 0x00040000 */

+#define BDMA_IFCR_CHTIF4        BDMA_IFCR_CHTIF4_Msk                           /*!< Channel 4 Half Transfer clear */

+#define BDMA_IFCR_CTEIF4_Pos    (19U)

+#define BDMA_IFCR_CTEIF4_Msk    (0x1UL << BDMA_IFCR_CTEIF4_Pos)                /*!< 0x00080000 */

+#define BDMA_IFCR_CTEIF4        BDMA_IFCR_CTEIF4_Msk                           /*!< Channel 4 Transfer Error clear */

+#define BDMA_IFCR_CGIF5_Pos     (20U)

+#define BDMA_IFCR_CGIF5_Msk     (0x1UL << BDMA_IFCR_CGIF5_Pos)                 /*!< 0x00100000 */

+#define BDMA_IFCR_CGIF5         BDMA_IFCR_CGIF5_Msk                            /*!< Channel 5 Global interrupt clear */

+#define BDMA_IFCR_CTCIF5_Pos    (21U)

+#define BDMA_IFCR_CTCIF5_Msk    (0x1UL << BDMA_IFCR_CTCIF5_Pos)                /*!< 0x00200000 */

+#define BDMA_IFCR_CTCIF5        BDMA_IFCR_CTCIF5_Msk                           /*!< Channel 5 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF5_Pos    (22U)

+#define BDMA_IFCR_CHTIF5_Msk    (0x1UL << BDMA_IFCR_CHTIF5_Pos)                /*!< 0x00400000 */

+#define BDMA_IFCR_CHTIF5        BDMA_IFCR_CHTIF5_Msk                           /*!< Channel 5 Half Transfer clear */

+#define BDMA_IFCR_CTEIF5_Pos    (23U)

+#define BDMA_IFCR_CTEIF5_Msk    (0x1UL << BDMA_IFCR_CTEIF5_Pos)                /*!< 0x00800000 */

+#define BDMA_IFCR_CTEIF5        BDMA_IFCR_CTEIF5_Msk                           /*!< Channel 5 Transfer Error clear */

+#define BDMA_IFCR_CGIF6_Pos     (24U)

+#define BDMA_IFCR_CGIF6_Msk     (0x1UL << BDMA_IFCR_CGIF6_Pos)                 /*!< 0x01000000 */

+#define BDMA_IFCR_CGIF6         BDMA_IFCR_CGIF6_Msk                            /*!< Channel 6 Global interrupt clear */

+#define BDMA_IFCR_CTCIF6_Pos    (25U)

+#define BDMA_IFCR_CTCIF6_Msk    (0x1UL << BDMA_IFCR_CTCIF6_Pos)                /*!< 0x02000000 */

+#define BDMA_IFCR_CTCIF6        BDMA_IFCR_CTCIF6_Msk                           /*!< Channel 6 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF6_Pos    (26U)

+#define BDMA_IFCR_CHTIF6_Msk    (0x1UL << BDMA_IFCR_CHTIF6_Pos)                /*!< 0x04000000 */

+#define BDMA_IFCR_CHTIF6        BDMA_IFCR_CHTIF6_Msk                           /*!< Channel 6 Half Transfer clear */

+#define BDMA_IFCR_CTEIF6_Pos    (27U)

+#define BDMA_IFCR_CTEIF6_Msk    (0x1UL << BDMA_IFCR_CTEIF6_Pos)                /*!< 0x08000000 */

+#define BDMA_IFCR_CTEIF6        BDMA_IFCR_CTEIF6_Msk                           /*!< Channel 6 Transfer Error clear */

+#define BDMA_IFCR_CGIF7_Pos     (28U)

+#define BDMA_IFCR_CGIF7_Msk     (0x1UL << BDMA_IFCR_CGIF7_Pos)                 /*!< 0x10000000 */

+#define BDMA_IFCR_CGIF7         BDMA_IFCR_CGIF7_Msk                            /*!< Channel 7 Global interrupt clear */

+#define BDMA_IFCR_CTCIF7_Pos    (29U)

+#define BDMA_IFCR_CTCIF7_Msk    (0x1UL << BDMA_IFCR_CTCIF7_Pos)                /*!< 0x20000000 */

+#define BDMA_IFCR_CTCIF7        BDMA_IFCR_CTCIF7_Msk                           /*!< Channel 7 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF7_Pos    (30U)

+#define BDMA_IFCR_CHTIF7_Msk    (0x1UL << BDMA_IFCR_CHTIF7_Pos)                /*!< 0x40000000 */

+#define BDMA_IFCR_CHTIF7        BDMA_IFCR_CHTIF7_Msk                           /*!< Channel 7 Half Transfer clear */

+#define BDMA_IFCR_CTEIF7_Pos    (31U)

+#define BDMA_IFCR_CTEIF7_Msk    (0x1UL << BDMA_IFCR_CTEIF7_Pos)                /*!< 0x80000000 */

+#define BDMA_IFCR_CTEIF7        BDMA_IFCR_CTEIF7_Msk                           /*!< Channel 7 Transfer Error clear */

+

+/*******************  Bit definition for BDMA_CCR register  ********************/

+#define BDMA_CCR_EN_Pos         (0U)

+#define BDMA_CCR_EN_Msk         (0x1UL << BDMA_CCR_EN_Pos)                     /*!< 0x00000001 */

+#define BDMA_CCR_EN             BDMA_CCR_EN_Msk                                /*!< Channel enable                      */

+#define BDMA_CCR_TCIE_Pos       (1U)

+#define BDMA_CCR_TCIE_Msk       (0x1UL << BDMA_CCR_TCIE_Pos)                   /*!< 0x00000002 */

+#define BDMA_CCR_TCIE           BDMA_CCR_TCIE_Msk                              /*!< Transfer complete interrupt enable  */

+#define BDMA_CCR_HTIE_Pos       (2U)

+#define BDMA_CCR_HTIE_Msk       (0x1UL << BDMA_CCR_HTIE_Pos)                   /*!< 0x00000004 */

+#define BDMA_CCR_HTIE           BDMA_CCR_HTIE_Msk                              /*!< Half Transfer interrupt enable      */

+#define BDMA_CCR_TEIE_Pos       (3U)

+#define BDMA_CCR_TEIE_Msk       (0x1UL << BDMA_CCR_TEIE_Pos)                   /*!< 0x00000008 */

+#define BDMA_CCR_TEIE           BDMA_CCR_TEIE_Msk                              /*!< Transfer error interrupt enable     */

+#define BDMA_CCR_DIR_Pos        (4U)

+#define BDMA_CCR_DIR_Msk        (0x1UL << BDMA_CCR_DIR_Pos)                    /*!< 0x00000010 */

+#define BDMA_CCR_DIR            BDMA_CCR_DIR_Msk                               /*!< Data transfer direction             */

+#define BDMA_CCR_CIRC_Pos       (5U)

+#define BDMA_CCR_CIRC_Msk       (0x1UL << BDMA_CCR_CIRC_Pos)                   /*!< 0x00000020 */

+#define BDMA_CCR_CIRC           BDMA_CCR_CIRC_Msk                              /*!< Circular mode                       */

+#define BDMA_CCR_PINC_Pos       (6U)

+#define BDMA_CCR_PINC_Msk       (0x1UL << BDMA_CCR_PINC_Pos)                   /*!< 0x00000040 */

+#define BDMA_CCR_PINC           BDMA_CCR_PINC_Msk                              /*!< Peripheral increment mode           */

+#define BDMA_CCR_MINC_Pos       (7U)

+#define BDMA_CCR_MINC_Msk       (0x1UL << BDMA_CCR_MINC_Pos)                   /*!< 0x00000080 */

+#define BDMA_CCR_MINC           BDMA_CCR_MINC_Msk                              /*!< Memory increment mode               */

+

+#define BDMA_CCR_PSIZE_Pos      (8U)

+#define BDMA_CCR_PSIZE_Msk      (0x3UL << BDMA_CCR_PSIZE_Pos)                  /*!< 0x00000300 */

+#define BDMA_CCR_PSIZE          BDMA_CCR_PSIZE_Msk                             /*!< PSIZE[1:0] bits (Peripheral size)   */

+#define BDMA_CCR_PSIZE_0        (0x1UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000100 */

+#define BDMA_CCR_PSIZE_1        (0x2UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000200 */

+

+#define BDMA_CCR_MSIZE_Pos      (10U)

+#define BDMA_CCR_MSIZE_Msk      (0x3UL << BDMA_CCR_MSIZE_Pos)                  /*!< 0x00000C00 */

+#define BDMA_CCR_MSIZE          BDMA_CCR_MSIZE_Msk                             /*!< MSIZE[1:0] bits (Memory size)       */

+#define BDMA_CCR_MSIZE_0        (0x1UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000400 */

+#define BDMA_CCR_MSIZE_1        (0x2UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000800 */

+

+#define BDMA_CCR_PL_Pos         (12U)

+#define BDMA_CCR_PL_Msk         (0x3UL << BDMA_CCR_PL_Pos)                     /*!< 0x00003000 */

+#define BDMA_CCR_PL             BDMA_CCR_PL_Msk                                /*!< PL[1:0] bits(Channel Priority level)*/

+#define BDMA_CCR_PL_0           (0x1UL << BDMA_CCR_PL_Pos)                      /*!< 0x00001000 */

+#define BDMA_CCR_PL_1           (0x2UL << BDMA_CCR_PL_Pos)                      /*!< 0x00002000 */

+

+#define BDMA_CCR_MEM2MEM_Pos    (14U)

+#define BDMA_CCR_MEM2MEM_Msk    (0x1UL << BDMA_CCR_MEM2MEM_Pos)                /*!< 0x00004000 */

+#define BDMA_CCR_MEM2MEM        BDMA_CCR_MEM2MEM_Msk                           /*!< Memory to memory mode               */

+#define BDMA_CCR_DBM_Pos        (15U)

+#define BDMA_CCR_DBM_Msk        (0x1UL << BDMA_CCR_DBM_Pos)                    /*!< 0x0000A000 */

+#define BDMA_CCR_DBM            BDMA_CCR_DBM_Msk                               /*!< Memory to memory mode               */

+#define BDMA_CCR_CT_Pos         (16U)

+#define BDMA_CCR_CT_Msk         (0x1UL << BDMA_CCR_CT_Pos)                     /*!< 0x00010000 */

+#define BDMA_CCR_CT             BDMA_CCR_CT_Msk                                /*!< Memory to memory mode               */

+

+/******************  Bit definition for BDMA_CNDTR register  *******************/

+#define BDMA_CNDTR_NDT_Pos      (0U)

+#define BDMA_CNDTR_NDT_Msk      (0xFFFFUL << BDMA_CNDTR_NDT_Pos)               /*!< 0x0000FFFF */

+#define BDMA_CNDTR_NDT          BDMA_CNDTR_NDT_Msk                             /*!< Number of data to Transfer          */

+

+/******************  Bit definition for BDMA_CPAR register  ********************/

+#define BDMA_CPAR_PA_Pos        (0U)

+#define BDMA_CPAR_PA_Msk        (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CPAR_PA            BDMA_CPAR_PA_Msk                               /*!< Peripheral Address                  */

+

+/******************  Bit definition for BDMA_CM0AR register  ********************/

+#define BDMA_CM0AR_MA_Pos        (0U)

+#define BDMA_CM0AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CM0AR_MA            BDMA_CM0AR_MA_Msk                               /*!< Memory Address                      */

+

+/******************  Bit definition for BDMA_CM1AR register  ********************/

+#define BDMA_CM1AR_MA_Pos        (0U)

+#define BDMA_CM1AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CM1AR_MA            BDMA_CM1AR_MA_Msk                               /*!< Memory Address                      */

+

+/******************************************************************************/

+/*                                                                            */

+/*                Ethernet MAC Registers bits definitions                     */

+/*                                                                            */

+/******************************************************************************/

+/* Bit definition for Ethernet MAC Configuration Register register */

+#define ETH_MACCR_ARP_Pos                             (31U)

+#define ETH_MACCR_ARP_Msk                             (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */

+#define ETH_MACCR_ARP                                 ETH_MACCR_ARP_Msk        /* ARP Offload Enable */

+#define ETH_MACCR_SARC_Pos                            (28U)

+#define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */

+#define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */

+#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */

+#define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)

+#define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */

+#define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */

+#define ETH_MACCR_SARC_INSADDR1_Pos                   (29U)

+#define ETH_MACCR_SARC_INSADDR1_Msk                   (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */

+#define ETH_MACCR_SARC_INSADDR1                       ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */

+#define ETH_MACCR_SARC_REPADDR0_Pos                   (28U)

+#define ETH_MACCR_SARC_REPADDR0_Msk                   (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */

+#define ETH_MACCR_SARC_REPADDR0                       ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */

+#define ETH_MACCR_SARC_REPADDR1_Pos                   (28U)

+#define ETH_MACCR_SARC_REPADDR1_Msk                   (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */

+#define ETH_MACCR_SARC_REPADDR1                       ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */

+#define ETH_MACCR_IPC_Pos                             (27U)

+#define ETH_MACCR_IPC_Msk                             (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */

+#define ETH_MACCR_IPC                                 ETH_MACCR_IPC_Msk        /* Checksum Offload */

+#define ETH_MACCR_IPG_Pos                             (24U)

+#define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */

+#define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */

+#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */

+#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */

+#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */

+#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */

+#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */

+#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */

+#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */

+#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */

+#define ETH_MACCR_GPSLCE_Pos                          (23U)

+#define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */

+#define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */

+#define ETH_MACCR_S2KP_Pos                            (22U)

+#define ETH_MACCR_S2KP_Msk                            (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */

+#define ETH_MACCR_S2KP                                ETH_MACCR_S2KP_Msk       /* IEEE 802.3as Support for 2K Packets */

+#define ETH_MACCR_CST_Pos                             (21U)

+#define ETH_MACCR_CST_Msk                             (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */

+#define ETH_MACCR_CST                                 ETH_MACCR_CST_Msk        /* CRC stripping for Type packets */

+#define ETH_MACCR_ACS_Pos                             (20U)

+#define ETH_MACCR_ACS_Msk                             (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */

+#define ETH_MACCR_ACS                                 ETH_MACCR_ACS_Msk        /* Automatic Pad or CRC Stripping */

+#define ETH_MACCR_WD_Pos                              (19U)

+#define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */

+#define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */

+#define ETH_MACCR_JD_Pos                              (17U)

+#define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */

+#define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */

+#define ETH_MACCR_JE_Pos                              (16U)

+#define ETH_MACCR_JE_Msk                              (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */

+#define ETH_MACCR_JE                                  ETH_MACCR_JE_Msk         /* Jumbo Packet Enable */

+#define ETH_MACCR_FES_Pos                             (14U)

+#define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */

+#define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */

+#define ETH_MACCR_DM_Pos                              (13U)

+#define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */

+#define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */

+#define ETH_MACCR_LM_Pos                              (12U)

+#define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */

+#define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */

+#define ETH_MACCR_ECRSFD_Pos                          (11U)

+#define ETH_MACCR_ECRSFD_Msk                          (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */

+#define ETH_MACCR_ECRSFD                              ETH_MACCR_ECRSFD_Msk     /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */

+#define ETH_MACCR_DO_Pos                              (10U)

+#define ETH_MACCR_DO_Msk                              (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */

+#define ETH_MACCR_DO                                  ETH_MACCR_DO_Msk         /* Disable Receive own  */

+#define ETH_MACCR_DCRS_Pos                            (9U)

+#define ETH_MACCR_DCRS_Msk                            (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */

+#define ETH_MACCR_DCRS                                ETH_MACCR_DCRS_Msk       /* Disable Carrier Sense During Transmission */

+#define ETH_MACCR_DR_Pos                              (8U)

+#define ETH_MACCR_DR_Msk                              (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */

+#define ETH_MACCR_DR                                  ETH_MACCR_DR_Msk         /* Disable Retry */

+#define ETH_MACCR_BL_Pos                              (5U)

+#define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */

+#define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit mask */

+#define ETH_MACCR_BL_10                               (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */

+#define ETH_MACCR_BL_8                                (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */

+#define ETH_MACCR_BL_4                                (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */

+#define ETH_MACCR_BL_1                                (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */

+#define ETH_MACCR_DC_Pos                              (4U)

+#define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */

+#define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */

+#define ETH_MACCR_PRELEN_Pos                          (2U)

+#define ETH_MACCR_PRELEN_Msk                          (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */

+#define ETH_MACCR_PRELEN                              ETH_MACCR_PRELEN_Msk     /* Preamble Length for Transmit packets */

+#define ETH_MACCR_PRELEN_7                            (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */

+#define ETH_MACCR_PRELEN_5                            (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */

+#define ETH_MACCR_PRELEN_3                            (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */

+#define ETH_MACCR_TE_Pos                              (1U)

+#define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */

+#define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */

+#define ETH_MACCR_RE_Pos                              (0U)

+#define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */

+#define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */

+

+/* Bit definition for Ethernet MAC Extended Configuration Register register */

+#define ETH_MACECR_EIPG_Pos                           (25U)

+#define ETH_MACECR_EIPG_Msk                           (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */

+#define ETH_MACECR_EIPG                               ETH_MACECR_EIPG_Msk      /* Extended Inter-Packet Gap */

+#define ETH_MACECR_EIPGEN_Pos                         (24U)

+#define ETH_MACECR_EIPGEN_Msk                         (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */

+#define ETH_MACECR_EIPGEN                             ETH_MACECR_EIPGEN_Msk    /* Extended Inter-Packet Gap Enable */

+#define ETH_MACECR_USP_Pos                            (18U)

+#define ETH_MACECR_USP_Msk                            (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */

+#define ETH_MACECR_USP                                ETH_MACECR_USP_Msk       /* Unicast Slow Protocol Packet Detect */

+#define ETH_MACECR_SPEN_Pos                           (17U)

+#define ETH_MACECR_SPEN_Msk                           (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */

+#define ETH_MACECR_SPEN                               ETH_MACECR_SPEN_Msk      /* Slow Protocol Detection Enable */

+#define ETH_MACECR_DCRCC_Pos                          (16U)

+#define ETH_MACECR_DCRCC_Msk                          (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */

+#define ETH_MACECR_DCRCC                              ETH_MACECR_DCRCC_Msk     /* Disable CRC Checking for Received Packets */

+#define ETH_MACECR_GPSL_Pos                           (0U)

+#define ETH_MACECR_GPSL_Msk                           (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */

+#define ETH_MACECR_GPSL                               ETH_MACECR_GPSL_Msk      /* Giant Packet Size Limit */

+

+/* Bit definition for Ethernet MAC Packet Filter Register */

+#define ETH_MACPFR_RA_Pos                             (31U)

+#define ETH_MACPFR_RA_Msk                             (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */

+#define ETH_MACPFR_RA                                 ETH_MACPFR_RA_Msk        /* Receive all */

+#define ETH_MACPFR_DNTU_Pos                           (21U)

+#define ETH_MACPFR_DNTU_Msk                           (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */

+#define ETH_MACPFR_DNTU                               ETH_MACPFR_DNTU_Msk      /* Drop Non-TCP/UDP over IP Packets */

+#define ETH_MACPFR_IPFE_Pos                           (20U)

+#define ETH_MACPFR_IPFE_Msk                           (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */

+#define ETH_MACPFR_IPFE                               ETH_MACPFR_IPFE_Msk      /* Layer 3 and Layer 4 Filter Enable */

+#define ETH_MACPFR_VTFE_Pos                           (16U)

+#define ETH_MACPFR_VTFE_Msk                           (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */

+#define ETH_MACPFR_VTFE                               ETH_MACPFR_VTFE_Msk      /* VLAN Tag Filter Enable */

+#define ETH_MACPFR_HPF_Pos                            (10U)

+#define ETH_MACPFR_HPF_Msk                            (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */

+#define ETH_MACPFR_HPF                                ETH_MACPFR_HPF_Msk       /* Hash or perfect filter */

+#define ETH_MACPFR_SAF_Pos                            (9U)

+#define ETH_MACPFR_SAF_Msk                            (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */

+#define ETH_MACPFR_SAF                                ETH_MACPFR_SAF_Msk       /* Source address filter enable */

+#define ETH_MACPFR_SAIF_Pos                           (8U)

+#define ETH_MACPFR_SAIF_Msk                           (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */

+#define ETH_MACPFR_SAIF                               ETH_MACPFR_SAIF_Msk      /* SA inverse filtering */

+#define ETH_MACPFR_PCF_Pos                            (6U)

+#define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */

+#define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */

+#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */

+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)

+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */

+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */

+#define ETH_MACPFR_PCF_FORWARDALL_Pos                 (7U)

+#define ETH_MACPFR_PCF_FORWARDALL_Msk                 (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */

+#define ETH_MACPFR_PCF_FORWARDALL                     ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */

+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos    (6U)

+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk    (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */

+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER        ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */

+#define ETH_MACPFR_DBF_Pos                            (5U)

+#define ETH_MACPFR_DBF_Msk                            (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */

+#define ETH_MACPFR_DBF                                ETH_MACPFR_DBF_Msk       /* Disable Broadcast Packets */

+#define ETH_MACPFR_PM_Pos                             (4U)

+#define ETH_MACPFR_PM_Msk                             (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */

+#define ETH_MACPFR_PM                                 ETH_MACPFR_PM_Msk        /* Pass all mutlicast */

+#define ETH_MACPFR_DAIF_Pos                           (3U)

+#define ETH_MACPFR_DAIF_Msk                           (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */

+#define ETH_MACPFR_DAIF                               ETH_MACPFR_DAIF_Msk      /* DA Inverse filtering */

+#define ETH_MACPFR_HMC_Pos                            (2U)

+#define ETH_MACPFR_HMC_Msk                            (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */

+#define ETH_MACPFR_HMC                                ETH_MACPFR_HMC_Msk       /* Hash multicast */

+#define ETH_MACPFR_HUC_Pos                            (1U)

+#define ETH_MACPFR_HUC_Msk                            (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */

+#define ETH_MACPFR_HUC                                ETH_MACPFR_HUC_Msk       /* Hash unicast */

+#define ETH_MACPFR_PR_Pos                             (0U)

+#define ETH_MACPFR_PR_Msk                             (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */

+#define ETH_MACPFR_PR                                 ETH_MACPFR_PR_Msk        /* Promiscuous mode */

+

+/* Bit definition for Ethernet MAC Watchdog Timeout Register */

+#define ETH_MACWTR_PWE_Pos                            (8U)

+#define ETH_MACWTR_PWE_Msk                            (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */

+#define ETH_MACWTR_PWE                                ETH_MACWTR_PWE_Msk       /* Programmable Watchdog Enable */

+#define ETH_MACWTR_WTO_Pos                            (0U)

+#define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */

+#define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */

+#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/

+#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */

+#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */

+#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */

+#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */

+#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */

+#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */

+#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */

+#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */

+#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */

+#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */

+#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */

+#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */

+#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */

+#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */

+

+/* Bit definition for Ethernet MAC Hash Table High Register */

+#define ETH_MACHTHR_HTH_Pos                           (0U)

+#define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */

+

+/* Bit definition for Ethernet MAC Hash Table Low Register */

+#define ETH_MACHTLR_HTL_Pos                           (0U)

+#define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */

+

+/* Bit definition for Ethernet MAC VLAN Tag Register */

+#define ETH_MACVTR_EIVLRXS_Pos                        (31U)

+#define ETH_MACVTR_EIVLRXS_Msk                        (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */

+#define ETH_MACVTR_EIVLRXS                            ETH_MACVTR_EIVLRXS_Msk   /* Enable Inner VLAN Tag in Rx Status */

+#define ETH_MACVTR_EIVLS_Pos                          (28U)

+#define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */

+#define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */

+#define ETH_MACVTR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */

+#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)

+#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */

+#define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */

+#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos             (29U)

+#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk             (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */

+#define ETH_MACVTR_EIVLS_STRIPIFFAILS                 ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */

+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos              (28U)

+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk              (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */

+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP                  ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */

+#define ETH_MACVTR_ERIVLT_Pos                         (27U)

+#define ETH_MACVTR_ERIVLT_Msk                         (0x1UL << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */

+#define ETH_MACVTR_ERIVLT                             ETH_MACVTR_ERIVLT_Msk    /* Enable Inner VLAN Tag */

+#define ETH_MACVTR_EDVLP_Pos                          (26U)

+#define ETH_MACVTR_EDVLP_Msk                          (0x1UL << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */

+#define ETH_MACVTR_EDVLP                              ETH_MACVTR_EDVLP_Msk     /* Enable Double VLAN Processing */

+#define ETH_MACVTR_VTHM_Pos                           (25U)

+#define ETH_MACVTR_VTHM_Msk                           (0x1UL << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */

+#define ETH_MACVTR_VTHM                               ETH_MACVTR_VTHM_Msk      /* VLAN Tag Hash Table Match Enable */

+#define ETH_MACVTR_EVLRXS_Pos                         (24U)

+#define ETH_MACVTR_EVLRXS_Msk                         (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */

+#define ETH_MACVTR_EVLRXS                             ETH_MACVTR_EVLRXS_Msk    /* Enable VLAN Tag in Rx status */

+#define ETH_MACVTR_EVLS_Pos                           (21U)

+#define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */

+#define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */

+#define ETH_MACVTR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */

+#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)

+#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */

+#define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */

+#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos              (22U)

+#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk              (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */

+#define ETH_MACVTR_EVLS_STRIPIFFAILS                  ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */

+#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos               (21U)

+#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk               (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */

+#define ETH_MACVTR_EVLS_ALWAYSSTRIP                   ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */

+#define ETH_MACVTR_DOVLTC_Pos                         (20U)

+#define ETH_MACVTR_DOVLTC_Msk                         (0x1UL << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */

+#define ETH_MACVTR_DOVLTC                             ETH_MACVTR_DOVLTC_Msk    /* Disable VLAN Type Check */

+#define ETH_MACVTR_ERSVLM_Pos                         (19U)

+#define ETH_MACVTR_ERSVLM_Msk                         (0x1UL << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */

+#define ETH_MACVTR_ERSVLM                             ETH_MACVTR_ERSVLM_Msk    /* Enable Receive S-VLAN Match */

+#define ETH_MACVTR_ESVL_Pos                           (18U)

+#define ETH_MACVTR_ESVL_Msk                           (0x1UL << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */

+#define ETH_MACVTR_ESVL                               ETH_MACVTR_ESVL_Msk      /* Enable S-VLAN */

+#define ETH_MACVTR_VTIM_Pos                           (17U)

+#define ETH_MACVTR_VTIM_Msk                           (0x1UL << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */

+#define ETH_MACVTR_VTIM                               ETH_MACVTR_VTIM_Msk      /* VLAN Tag Inverse Match Enable */

+#define ETH_MACVTR_ETV_Pos                            (16U)

+#define ETH_MACVTR_ETV_Msk                            (0x1UL << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */

+#define ETH_MACVTR_ETV                                ETH_MACVTR_ETV_Msk       /* Enable 12-Bit VLAN Tag Comparison */

+#define ETH_MACVTR_VL_Pos                             (0U)

+#define ETH_MACVTR_VL_Msk                             (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */

+#define ETH_MACVTR_VL                                 ETH_MACVTR_VL_Msk        /* VLAN Tag Identifier for Receive Packets */

+#define ETH_MACVTR_VL_UP_Pos                          (13U)

+#define ETH_MACVTR_VL_UP_Msk                          (0x7UL << ETH_MACVTR_VL_UP_Pos) /*!< 0x0000E000 */

+#define ETH_MACVTR_VL_UP                              ETH_MACVTR_VL_UP_Msk     /* User Priority */

+#define ETH_MACVTR_VL_CFIDEI_Pos                      (12U)

+#define ETH_MACVTR_VL_CFIDEI_Msk                      (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos) /*!< 0x00001000 */

+#define ETH_MACVTR_VL_CFIDEI                          ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */

+#define ETH_MACVTR_VL_VID_Pos                         (0U)

+#define ETH_MACVTR_VL_VID_Msk                         (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */

+#define ETH_MACVTR_VL_VID                             ETH_MACVTR_VL_VID_Msk    /* VLAN Identifier field of VLAN tag */

+

+/* Bit definition for Ethernet MAC VLAN Hash Table Register */

+#define ETH_MACVHTR_VLHT_Pos                          (0U)

+#define ETH_MACVHTR_VLHT_Msk                          (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACVHTR_VLHT                              ETH_MACVHTR_VLHT_Msk     /* VLAN Hash Table */

+

+/* Bit definition for Ethernet MAC VLAN Incl Register */

+#define ETH_MACVIR_VLTI_Pos                           (20U)

+#define ETH_MACVIR_VLTI_Msk                           (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */

+#define ETH_MACVIR_VLTI                               ETH_MACVIR_VLTI_Msk      /* VLAN Tag Input */

+#define ETH_MACVIR_CSVL_Pos                           (19U)

+#define ETH_MACVIR_CSVL_Msk                           (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */

+#define ETH_MACVIR_CSVL                               ETH_MACVIR_CSVL_Msk      /* C-VLAN or S-VLAN */

+#define ETH_MACVIR_VLP_Pos                            (18U)

+#define ETH_MACVIR_VLP_Msk                            (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */

+#define ETH_MACVIR_VLP                                ETH_MACVIR_VLP_Msk       /* VLAN Priority Control */

+#define ETH_MACVIR_VLC_Pos                            (16U)

+#define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */

+#define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */

+#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */

+#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)

+#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */

+#define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */

+#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos              (17U)

+#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */

+#define ETH_MACVIR_VLC_VLANTAGINSERT                  ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */

+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos             (16U)

+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk             (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */

+#define ETH_MACVIR_VLC_VLANTAGREPLACE                 ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */

+#define ETH_MACVIR_VLT_Pos                            (0U)

+#define ETH_MACVIR_VLT_Msk                            (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACVIR_VLT                                ETH_MACVIR_VLT_Msk       /* VLAN Tag for Transmit Packets */

+#define ETH_MACVIR_VLT_UP_Pos                         (13U)

+#define ETH_MACVIR_VLT_UP_Msk                         (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */

+#define ETH_MACVIR_VLT_UP                             ETH_MACVIR_VLT_UP_Msk    /* User Priority */

+#define ETH_MACVIR_VLT_CFIDEI_Pos                     (12U)

+#define ETH_MACVIR_VLT_CFIDEI_Msk                     (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */

+#define ETH_MACVIR_VLT_CFIDEI                         ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */

+#define ETH_MACVIR_VLT_VID_Pos                        (0U)

+#define ETH_MACVIR_VLT_VID_Msk                        (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */

+#define ETH_MACVIR_VLT_VID                            ETH_MACVIR_VLT_VID_Msk   /* VLAN Identifier field of VLAN tag */

+

+/* Bit definition for Ethernet MAC Inner_VLAN Incl Register */

+#define ETH_MACIVIR_VLTI_Pos                          (20U)

+#define ETH_MACIVIR_VLTI_Msk                          (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */

+#define ETH_MACIVIR_VLTI                              ETH_MACIVIR_VLTI_Msk     /* VLAN Tag Input */

+#define ETH_MACIVIR_CSVL_Pos                          (19U)

+#define ETH_MACIVIR_CSVL_Msk                          (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */

+#define ETH_MACIVIR_CSVL                              ETH_MACIVIR_CSVL_Msk     /* C-VLAN or S-VLAN */

+#define ETH_MACIVIR_VLP_Pos                           (18U)

+#define ETH_MACIVIR_VLP_Msk                           (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */

+#define ETH_MACIVIR_VLP                               ETH_MACIVIR_VLP_Msk      /* VLAN Priority Control */

+#define ETH_MACIVIR_VLC_Pos                           (16U)

+#define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */

+#define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */

+#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */

+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)

+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */

+#define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */

+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos             (17U)

+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */

+#define ETH_MACIVIR_VLC_VLANTAGINSERT                 ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */

+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos            (16U)

+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk            (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */

+#define ETH_MACIVIR_VLC_VLANTAGREPLACE                ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */

+#define ETH_MACIVIR_VLT_Pos                           (0U)

+#define ETH_MACIVIR_VLT_Msk                           (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACIVIR_VLT                               ETH_MACIVIR_VLT_Msk      /* VLAN Tag for Transmit Packets */

+#define ETH_MACIVIR_VLT_UP_Pos                        (13U)

+#define ETH_MACIVIR_VLT_UP_Msk                        (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */

+#define ETH_MACIVIR_VLT_UP                            ETH_MACIVIR_VLT_UP_Msk   /* User Priority */

+#define ETH_MACIVIR_VLT_CFIDEI_Pos                    (12U)

+#define ETH_MACIVIR_VLT_CFIDEI_Msk                    (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */

+#define ETH_MACIVIR_VLT_CFIDEI                        ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */

+#define ETH_MACIVIR_VLT_VID_Pos                       (0U)

+#define ETH_MACIVIR_VLT_VID_Msk                       (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */

+#define ETH_MACIVIR_VLT_VID                           ETH_MACIVIR_VLT_VID_Msk  /* VLAN Identifier field of VLAN tag */

+

+/* Bit definition for Ethernet MAC Tx Flow Ctrl Register */

+#define ETH_MACTFCR_PT_Pos                            (16U)

+#define ETH_MACTFCR_PT_Msk                            (0xFFFFUL << ETH_MACTFCR_PT_Pos) /*!< 0xFFFF0000 */

+#define ETH_MACTFCR_PT                                ETH_MACTFCR_PT_Msk       /* Pause Time */

+#define ETH_MACTFCR_DZPQ_Pos                          (7U)

+#define ETH_MACTFCR_DZPQ_Msk                          (0x1UL << ETH_MACTFCR_DZPQ_Pos) /*!< 0x00000080 */

+#define ETH_MACTFCR_DZPQ                              ETH_MACTFCR_DZPQ_Msk     /* Disable Zero-Quanta Pause */

+#define ETH_MACTFCR_PLT_Pos                           (4U)

+#define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */

+#define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */

+#define ETH_MACTFCR_PLT_MINUS4                        ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */

+#define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)

+#define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */

+#define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */

+#define ETH_MACTFCR_PLT_MINUS36_Pos                   (5U)

+#define ETH_MACTFCR_PLT_MINUS36_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */

+#define ETH_MACTFCR_PLT_MINUS36                       ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */

+#define ETH_MACTFCR_PLT_MINUS144_Pos                  (4U)

+#define ETH_MACTFCR_PLT_MINUS144_Msk                  (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */

+#define ETH_MACTFCR_PLT_MINUS144                      ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */

+#define ETH_MACTFCR_PLT_MINUS256_Pos                  (6U)

+#define ETH_MACTFCR_PLT_MINUS256_Msk                  (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */

+#define ETH_MACTFCR_PLT_MINUS256                      ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */

+#define ETH_MACTFCR_PLT_MINUS512_Pos                  (4U)

+#define ETH_MACTFCR_PLT_MINUS512_Msk                  (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */

+#define ETH_MACTFCR_PLT_MINUS512                      ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */

+#define ETH_MACTFCR_TFE_Pos                           (1U)

+#define ETH_MACTFCR_TFE_Msk                           (0x1UL << ETH_MACTFCR_TFE_Pos) /*!< 0x00000002 */

+#define ETH_MACTFCR_TFE                               ETH_MACTFCR_TFE_Msk      /* Transmit Flow Control Enable */

+#define ETH_MACTFCR_FCB_Pos                           (0U)

+#define ETH_MACTFCR_FCB_Msk                           (0x1UL << ETH_MACTFCR_FCB_Pos) /*!< 0x00000001 */

+#define ETH_MACTFCR_FCB                               ETH_MACTFCR_FCB_Msk      /* Flow Control Busy or Backpressure Activate */

+

+/* Bit definition for Ethernet MAC Rx Flow Ctrl Register */

+#define ETH_MACRFCR_UP_Pos                            (1U)

+#define ETH_MACRFCR_UP_Msk                            (0x1UL << ETH_MACRFCR_UP_Pos) /*!< 0x00000002 */

+#define ETH_MACRFCR_UP                                ETH_MACRFCR_UP_Msk       /* Unicast Pause Packet Detect */

+#define ETH_MACRFCR_RFE_Pos                           (0U)

+#define ETH_MACRFCR_RFE_Msk                           (0x1UL << ETH_MACRFCR_RFE_Pos) /*!< 0x00000001 */

+#define ETH_MACRFCR_RFE                               ETH_MACRFCR_RFE_Msk      /* Receive Flow Control Enable */

+

+/* Bit definition for Ethernet MAC Interrupt Status Register */

+#define ETH_MACISR_RXSTSIS_Pos                        (14U)

+#define ETH_MACISR_RXSTSIS_Msk                        (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */

+#define ETH_MACISR_RXSTSIS                            ETH_MACISR_RXSTSIS_Msk   /* Receive Status Interrupt */

+#define ETH_MACISR_TXSTSIS_Pos                        (13U)

+#define ETH_MACISR_TXSTSIS_Msk                        (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */

+#define ETH_MACISR_TXSTSIS                            ETH_MACISR_TXSTSIS_Msk   /* Transmit Status Interrupt */

+#define ETH_MACISR_TSIS_Pos                           (12U)

+#define ETH_MACISR_TSIS_Msk                           (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */

+#define ETH_MACISR_TSIS                               ETH_MACISR_TSIS_Msk      /* Timestamp Interrupt Status */

+#define ETH_MACISR_MMCTXIS_Pos                        (10U)

+#define ETH_MACISR_MMCTXIS_Msk                        (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */

+#define ETH_MACISR_MMCTXIS                            ETH_MACISR_MMCTXIS_Msk   /* MMC Transmit Interrupt Status */

+#define ETH_MACISR_MMCRXIS_Pos                        (9U)

+#define ETH_MACISR_MMCRXIS_Msk                        (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */

+#define ETH_MACISR_MMCRXIS                            ETH_MACISR_MMCRXIS_Msk   /* MMC Receive Interrupt Status */

+#define ETH_MACISR_MMCIS_Pos                          (8U)

+#define ETH_MACISR_MMCIS_Msk                          (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */

+#define ETH_MACISR_MMCIS                              ETH_MACISR_MMCIS_Msk     /* MMC Interrupt Status */

+#define ETH_MACISR_LPIIS_Pos                          (5U)

+#define ETH_MACISR_LPIIS_Msk                          (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */

+#define ETH_MACISR_LPIIS                              ETH_MACISR_LPIIS_Msk     /* LPI Interrupt Status */

+#define ETH_MACISR_PMTIS_Pos                          (4U)

+#define ETH_MACISR_PMTIS_Msk                          (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */

+#define ETH_MACISR_PMTIS                              ETH_MACISR_PMTIS_Msk     /* PMT Interrupt Status */

+#define ETH_MACISR_PHYIS_Pos                          (3U)

+#define ETH_MACISR_PHYIS_Msk                          (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */

+#define ETH_MACISR_PHYIS                              ETH_MACISR_PHYIS_Msk     /* PHY Interrupt */

+

+/* Bit definition for Ethernet MAC Interrupt Enable Register */

+#define ETH_MACIER_RXSTSIE_Pos                        (14U)

+#define ETH_MACIER_RXSTSIE_Msk                        (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */

+#define ETH_MACIER_RXSTSIE                            ETH_MACIER_RXSTSIE_Msk   /* Receive Status Interrupt Enable */

+#define ETH_MACIER_TXSTSIE_Pos                        (13U)

+#define ETH_MACIER_TXSTSIE_Msk                        (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */

+#define ETH_MACIER_TXSTSIE                            ETH_MACIER_TXSTSIE_Msk   /* Transmit Status Interrupt Enable */

+#define ETH_MACIER_TSIE_Pos                           (12U)

+#define ETH_MACIER_TSIE_Msk                           (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */

+#define ETH_MACIER_TSIE                               ETH_MACIER_TSIE_Msk      /* Timestamp Interrupt Enable */

+#define ETH_MACIER_LPIIE_Pos                          (5U)

+#define ETH_MACIER_LPIIE_Msk                          (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */

+#define ETH_MACIER_LPIIE                              ETH_MACIER_LPIIE_Msk     /* LPI Interrupt Enable */

+#define ETH_MACIER_PMTIE_Pos                          (4U)

+#define ETH_MACIER_PMTIE_Msk                          (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */

+#define ETH_MACIER_PMTIE                              ETH_MACIER_PMTIE_Msk     /* PMT Interrupt Enable */

+#define ETH_MACIER_PHYIE_Pos                          (3U)

+#define ETH_MACIER_PHYIE_Msk                          (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */

+#define ETH_MACIER_PHYIE                              ETH_MACIER_PHYIE_Msk     /* PHY Interrupt Enable */

+

+/* Bit definition for Ethernet MAC Rx Tx Status Register */

+#define ETH_MACRXTXSR_RWT_Pos                         (8U)

+#define ETH_MACRXTXSR_RWT_Msk                         (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */

+#define ETH_MACRXTXSR_RWT                             ETH_MACRXTXSR_RWT_Msk    /* Receive Watchdog Timeout */

+#define ETH_MACRXTXSR_EXCOL_Pos                       (5U)

+#define ETH_MACRXTXSR_EXCOL_Msk                       (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */

+#define ETH_MACRXTXSR_EXCOL                           ETH_MACRXTXSR_EXCOL_Msk  /* Excessive Collisions */

+#define ETH_MACRXTXSR_LCOL_Pos                        (4U)

+#define ETH_MACRXTXSR_LCOL_Msk                        (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */

+#define ETH_MACRXTXSR_LCOL                            ETH_MACRXTXSR_LCOL_Msk   /* Late Collision */

+#define ETH_MACRXTXSR_EXDEF_Pos                       (3U)

+#define ETH_MACRXTXSR_EXDEF_Msk                       (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */

+#define ETH_MACRXTXSR_EXDEF                           ETH_MACRXTXSR_EXDEF_Msk  /* Excessive Deferral */

+#define ETH_MACRXTXSR_LCARR_Pos                       (2U)

+#define ETH_MACRXTXSR_LCARR_Msk                       (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */

+#define ETH_MACRXTXSR_LCARR                           ETH_MACRXTXSR_LCARR_Msk  /* Loss of Carrier */

+#define ETH_MACRXTXSR_NCARR_Pos                       (1U)

+#define ETH_MACRXTXSR_NCARR_Msk                       (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */

+#define ETH_MACRXTXSR_NCARR                           ETH_MACRXTXSR_NCARR_Msk  /* No Carrier */

+#define ETH_MACRXTXSR_TJT_Pos                         (0U)

+#define ETH_MACRXTXSR_TJT_Msk                         (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */

+#define ETH_MACRXTXSR_TJT                             ETH_MACRXTXSR_TJT_Msk    /* Transmit Jabber Timeout */

+

+/* Bit definition for Ethernet MAC PMT Control Status Register */

+#define ETH_MACPCSR_RWKFILTRST_Pos                    (31U)

+#define ETH_MACPCSR_RWKFILTRST_Msk                    (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */

+#define ETH_MACPCSR_RWKFILTRST                        ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */

+#define ETH_MACPCSR_RWKPTR_Pos                        (24U)

+#define ETH_MACPCSR_RWKPTR_Msk                        (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */

+#define ETH_MACPCSR_RWKPTR                            ETH_MACPCSR_RWKPTR_Msk   /* Remote Wake-up FIFO Pointer */

+#define ETH_MACPCSR_RWKPFE_Pos                        (10U)

+#define ETH_MACPCSR_RWKPFE_Msk                        (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */

+#define ETH_MACPCSR_RWKPFE                            ETH_MACPCSR_RWKPFE_Msk   /* Remote Wake-up Packet Forwarding Enable */

+#define ETH_MACPCSR_GLBLUCAST_Pos                     (9U)

+#define ETH_MACPCSR_GLBLUCAST_Msk                     (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */

+#define ETH_MACPCSR_GLBLUCAST                         ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */

+#define ETH_MACPCSR_RWKPRCVD_Pos                      (6U)

+#define ETH_MACPCSR_RWKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */

+#define ETH_MACPCSR_RWKPRCVD                          ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */

+#define ETH_MACPCSR_MGKPRCVD_Pos                      (5U)

+#define ETH_MACPCSR_MGKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */

+#define ETH_MACPCSR_MGKPRCVD                          ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */

+#define ETH_MACPCSR_RWKPKTEN_Pos                      (2U)

+#define ETH_MACPCSR_RWKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */

+#define ETH_MACPCSR_RWKPKTEN                          ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */

+#define ETH_MACPCSR_MGKPKTEN_Pos                      (1U)

+#define ETH_MACPCSR_MGKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */

+#define ETH_MACPCSR_MGKPKTEN                          ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */

+#define ETH_MACPCSR_PWRDWN_Pos                        (0U)

+#define ETH_MACPCSR_PWRDWN_Msk                        (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */

+#define ETH_MACPCSR_PWRDWN                            ETH_MACPCSR_PWRDWN_Msk   /* Power Down */

+

+/* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */

+#define ETH_MACRWUPFR_D_Pos                           (0U)

+#define ETH_MACRWUPFR_D_Msk                           (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACRWUPFR_D                               ETH_MACRWUPFR_D_Msk      /* Wake-up Packet filter register data */

+

+/* Bit definition for Ethernet MAC LPI Control Status Register */

+#define ETH_MACLCSR_LPITCSE_Pos                       (21U)

+#define ETH_MACLCSR_LPITCSE_Msk                       (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */

+#define ETH_MACLCSR_LPITCSE                           ETH_MACLCSR_LPITCSE_Msk  /* LPI Tx Clock Stop Enable */

+#define ETH_MACLCSR_LPITE_Pos                         (20U)

+#define ETH_MACLCSR_LPITE_Msk                         (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */

+#define ETH_MACLCSR_LPITE                             ETH_MACLCSR_LPITE_Msk    /* LPI Timer Enable */

+#define ETH_MACLCSR_LPITXA_Pos                        (19U)

+#define ETH_MACLCSR_LPITXA_Msk                        (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */

+#define ETH_MACLCSR_LPITXA                            ETH_MACLCSR_LPITXA_Msk   /* LPI Tx Automate */

+#define ETH_MACLCSR_PLS_Pos                           (17U)

+#define ETH_MACLCSR_PLS_Msk                           (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */

+#define ETH_MACLCSR_PLS                               ETH_MACLCSR_PLS_Msk      /* PHY Link Status */

+#define ETH_MACLCSR_LPIEN_Pos                         (16U)

+#define ETH_MACLCSR_LPIEN_Msk                         (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */

+#define ETH_MACLCSR_LPIEN                             ETH_MACLCSR_LPIEN_Msk    /* LPI Enable */

+#define ETH_MACLCSR_RLPIST_Pos                        (9U)

+#define ETH_MACLCSR_RLPIST_Msk                        (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */

+#define ETH_MACLCSR_RLPIST                            ETH_MACLCSR_RLPIST_Msk   /* Receive LPI State */

+#define ETH_MACLCSR_TLPIST_Pos                        (8U)

+#define ETH_MACLCSR_TLPIST_Msk                        (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */

+#define ETH_MACLCSR_TLPIST                            ETH_MACLCSR_TLPIST_Msk   /* Transmit LPI State */

+#define ETH_MACLCSR_RLPIEX_Pos                        (3U)

+#define ETH_MACLCSR_RLPIEX_Msk                        (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */

+#define ETH_MACLCSR_RLPIEX                            ETH_MACLCSR_RLPIEX_Msk   /* Receive LPI Exit */

+#define ETH_MACLCSR_RLPIEN_Pos                        (2U)

+#define ETH_MACLCSR_RLPIEN_Msk                        (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */

+#define ETH_MACLCSR_RLPIEN                            ETH_MACLCSR_RLPIEN_Msk   /* Receive LPI Entry */

+#define ETH_MACLCSR_TLPIEX_Pos                        (1U)

+#define ETH_MACLCSR_TLPIEX_Msk                        (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */

+#define ETH_MACLCSR_TLPIEX                            ETH_MACLCSR_TLPIEX_Msk   /* Transmit LPI Exit */

+#define ETH_MACLCSR_TLPIEN_Pos                        (0U)

+#define ETH_MACLCSR_TLPIEN_Msk                        (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */

+#define ETH_MACLCSR_TLPIEN                            ETH_MACLCSR_TLPIEN_Msk   /* Transmit LPI Entry */

+

+/* Bit definition for Ethernet MAC LPI Timers Control Register */

+#define ETH_MACLTCR_LST_Pos                           (16U)

+#define ETH_MACLTCR_LST_Msk                           (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */

+#define ETH_MACLTCR_LST                               ETH_MACLTCR_LST_Msk      /* LPI LS TIMER */

+#define ETH_MACLTCR_TWT_Pos                           (0U)

+#define ETH_MACLTCR_TWT_Msk                           (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACLTCR_TWT                               ETH_MACLTCR_TWT_Msk      /* LPI TW TIMER */

+

+/* Bit definition for Ethernet MAC LPI Entry Timer Register */

+#define ETH_MACLETR_LPIET_Pos                         (0U)

+#define ETH_MACLETR_LPIET_Msk                         (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */

+#define ETH_MACLETR_LPIET                             ETH_MACLETR_LPIET_Msk    /* LPI Entry Timer */

+

+/* Bit definition for Ethernet MAC 1US Tic Counter Register */

+#define ETH_MAC1USTCR_TIC1USCNTR_Pos                  (0U)

+#define ETH_MAC1USTCR_TIC1USCNTR_Msk                  (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */

+#define ETH_MAC1USTCR_TIC1USCNTR                      ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */

+

+/* Bit definition for Ethernet MAC Version Register */

+#define ETH_MACVR_USERVER_Pos                         (8U)

+#define ETH_MACVR_USERVER_Msk                         (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */

+#define ETH_MACVR_USERVER                             ETH_MACVR_USERVER_Msk    /* User-defined Version */

+#define ETH_MACVR_SNPSVER_Pos                         (0U)

+#define ETH_MACVR_SNPSVER_Msk                         (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */

+#define ETH_MACVR_SNPSVER                             ETH_MACVR_SNPSVER_Msk    /* Synopsys-defined Version */

+

+/* Bit definition for Ethernet MAC Debug Register */

+#define ETH_MACDR_TFCSTS_Pos                          (17U)

+#define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */

+#define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */

+#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */

+#define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)

+#define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */

+#define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */

+#define ETH_MACDR_TFCSTS_GENERATEPCP_Pos              (18U)

+#define ETH_MACDR_TFCSTS_GENERATEPCP_Msk              (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */

+#define ETH_MACDR_TFCSTS_GENERATEPCP                  ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */

+#define ETH_MACDR_TFCSTS_TRASFERIP_Pos                (17U)

+#define ETH_MACDR_TFCSTS_TRASFERIP_Msk                (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */

+#define ETH_MACDR_TFCSTS_TRASFERIP                    ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */

+#define ETH_MACDR_TPESTS_Pos                          (16U)

+#define ETH_MACDR_TPESTS_Msk                          (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */

+#define ETH_MACDR_TPESTS                              ETH_MACDR_TPESTS_Msk     /* MAC Receive Packet Controller FIFO Status */

+#define ETH_MACDR_RFCFCSTS_Pos                        (1U)

+#define ETH_MACDR_RFCFCSTS_Msk                        (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */

+#define ETH_MACDR_RFCFCSTS                            ETH_MACDR_RFCFCSTS_Msk   /* MAC MII Transmit Protocol Engine Status */

+#define ETH_MACDR_RPESTS_Pos                          (0U)

+#define ETH_MACDR_RPESTS_Msk                          (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */

+#define ETH_MACDR_RPESTS                              ETH_MACDR_RPESTS_Msk     /* MAC MII Receive Protocol Engine Status */

+

+/* Bit definition for Ethernet MAC HW Feature0 Register */

+#define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)

+#define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */

+#define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */

+#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */

+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)

+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */

+#define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */

+#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos             (28U)

+#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk             (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos) /*!< 0x70000000 */

+#define ETH_MACHWF0R_ACTPHYSEL_REVMII                 ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */

+#define ETH_MACHWF0R_SAVLANINS_Pos                    (27U)

+#define ETH_MACHWF0R_SAVLANINS_Msk                    (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */

+#define ETH_MACHWF0R_SAVLANINS                        ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */

+#define ETH_MACHWF0R_TSSTSSEL_Pos                     (25U)

+#define ETH_MACHWF0R_TSSTSSEL_Msk                     (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */

+#define ETH_MACHWF0R_TSSTSSEL                         ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */

+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos            (25U)

+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */

+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL                ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */

+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos            (26U)

+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */

+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL                ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */

+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos                (25U)

+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk                (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */

+#define ETH_MACHWF0R_TSSTSSEL_BOTH                    ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */

+#define ETH_MACHWF0R_MACADR64SEL_Pos                  (24U)

+#define ETH_MACHWF0R_MACADR64SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */

+#define ETH_MACHWF0R_MACADR64SEL                      ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */

+#define ETH_MACHWF0R_MACADR32SEL_Pos                  (23U)

+#define ETH_MACHWF0R_MACADR32SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */

+#define ETH_MACHWF0R_MACADR32SEL                      ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */

+#define ETH_MACHWF0R_ADDMACADRSEL_Pos                 (18U)

+#define ETH_MACHWF0R_ADDMACADRSEL_Msk                 (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */

+#define ETH_MACHWF0R_ADDMACADRSEL                     ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */

+#define ETH_MACHWF0R_RXCOESEL_Pos                     (16U)

+#define ETH_MACHWF0R_RXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */

+#define ETH_MACHWF0R_RXCOESEL                         ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */

+#define ETH_MACHWF0R_TXCOESEL_Pos                     (14U)

+#define ETH_MACHWF0R_TXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */

+#define ETH_MACHWF0R_TXCOESEL                         ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */

+#define ETH_MACHWF0R_EEESEL_Pos                       (13U)

+#define ETH_MACHWF0R_EEESEL_Msk                       (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */

+#define ETH_MACHWF0R_EEESEL                           ETH_MACHWF0R_EEESEL_Msk  /* Energy Efficient Ethernet Enabled */

+#define ETH_MACHWF0R_TSSEL_Pos                        (12U)

+#define ETH_MACHWF0R_TSSEL_Msk                        (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */

+#define ETH_MACHWF0R_TSSEL                            ETH_MACHWF0R_TSSEL_Msk   /* IEEE 1588-2008 Timestamp Enabled */

+#define ETH_MACHWF0R_ARPOFFSEL_Pos                    (9U)

+#define ETH_MACHWF0R_ARPOFFSEL_Msk                    (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */

+#define ETH_MACHWF0R_ARPOFFSEL                        ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */

+#define ETH_MACHWF0R_MMCSEL_Pos                       (8U)

+#define ETH_MACHWF0R_MMCSEL_Msk                       (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */

+#define ETH_MACHWF0R_MMCSEL                           ETH_MACHWF0R_MMCSEL_Msk  /* RMON Module Enable */

+#define ETH_MACHWF0R_MGKSEL_Pos                       (7U)

+#define ETH_MACHWF0R_MGKSEL_Msk                       (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */

+#define ETH_MACHWF0R_MGKSEL                           ETH_MACHWF0R_MGKSEL_Msk  /* PMT Magic Packet Enable */

+#define ETH_MACHWF0R_RWKSEL_Pos                       (6U)

+#define ETH_MACHWF0R_RWKSEL_Msk                       (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */

+#define ETH_MACHWF0R_RWKSEL                           ETH_MACHWF0R_RWKSEL_Msk  /* PMT Remote Wake-up Packet Enable */

+#define ETH_MACHWF0R_SMASEL_Pos                       (5U)

+#define ETH_MACHWF0R_SMASEL_Msk                       (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */

+#define ETH_MACHWF0R_SMASEL                           ETH_MACHWF0R_SMASEL_Msk  /* SMA (MDIO) Interface */

+#define ETH_MACHWF0R_VLHASH_Pos                       (4U)

+#define ETH_MACHWF0R_VLHASH_Msk                       (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */

+#define ETH_MACHWF0R_VLHASH                           ETH_MACHWF0R_VLHASH_Msk  /* VLAN Hash Filter Selected */

+#define ETH_MACHWF0R_PCSSEL_Pos                       (3U)

+#define ETH_MACHWF0R_PCSSEL_Msk                       (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */

+#define ETH_MACHWF0R_PCSSEL                           ETH_MACHWF0R_PCSSEL_Msk  /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */

+#define ETH_MACHWF0R_HDSEL_Pos                        (2U)

+#define ETH_MACHWF0R_HDSEL_Msk                        (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */

+#define ETH_MACHWF0R_HDSEL                            ETH_MACHWF0R_HDSEL_Msk   /* Half-duplex Support */

+#define ETH_MACHWF0R_GMIISEL_Pos                      (1U)

+#define ETH_MACHWF0R_GMIISEL_Msk                      (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */

+#define ETH_MACHWF0R_GMIISEL                          ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */

+#define ETH_MACHWF0R_MIISEL_Pos                       (0U)

+#define ETH_MACHWF0R_MIISEL_Msk                       (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */

+#define ETH_MACHWF0R_MIISEL                           ETH_MACHWF0R_MIISEL_Msk  /* 10 or 100 Mbps Support */

+

+/* Bit definition for Ethernet MAC HW Feature1 Register */

+#define ETH_MACHWF1R_L3L4FNUM_Pos                     (27U)

+#define ETH_MACHWF1R_L3L4FNUM_Msk                     (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */

+#define ETH_MACHWF1R_L3L4FNUM                         ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */

+#define ETH_MACHWF1R_HASHTBLSZ_Pos                    (24U)

+#define ETH_MACHWF1R_HASHTBLSZ_Msk                    (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */

+#define ETH_MACHWF1R_HASHTBLSZ                        ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */

+#define ETH_MACHWF1R_AVSEL_Pos                        (20U)

+#define ETH_MACHWF1R_AVSEL_Msk                        (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */

+#define ETH_MACHWF1R_AVSEL                            ETH_MACHWF1R_AVSEL_Msk   /* AV Feature Enabled */

+#define ETH_MACHWF1R_DBGMEMA_Pos                      (19U)

+#define ETH_MACHWF1R_DBGMEMA_Msk                      (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */

+#define ETH_MACHWF1R_DBGMEMA                          ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */

+#define ETH_MACHWF1R_TSOEN_Pos                        (18U)

+#define ETH_MACHWF1R_TSOEN_Msk                        (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */

+#define ETH_MACHWF1R_TSOEN                            ETH_MACHWF1R_TSOEN_Msk   /* TCP Segmentation Offload Enable */

+#define ETH_MACHWF1R_SPHEN_Pos                        (17U)

+#define ETH_MACHWF1R_SPHEN_Msk                        (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */

+#define ETH_MACHWF1R_SPHEN                            ETH_MACHWF1R_SPHEN_Msk   /* Split Header Feature Enable */

+#define ETH_MACHWF1R_DCBEN_Pos                        (16U)

+#define ETH_MACHWF1R_DCBEN_Msk                        (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */

+#define ETH_MACHWF1R_DCBEN                            ETH_MACHWF1R_DCBEN_Msk   /* DCB Feature Enable */

+#define ETH_MACHWF1R_ADDR64_Pos                       (14U)

+#define ETH_MACHWF1R_ADDR64_Msk                       (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */

+#define ETH_MACHWF1R_ADDR64                           ETH_MACHWF1R_ADDR64_Msk  /* Address Width */

+#define ETH_MACHWF1R_ADDR64_32                        (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */

+#define ETH_MACHWF1R_ADDR64_40                        (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */

+#define ETH_MACHWF1R_ADDR64_48                        (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */

+#define ETH_MACHWF1R_ADVTHWORD_Pos                    (13U)

+#define ETH_MACHWF1R_ADVTHWORD_Msk                    (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */

+#define ETH_MACHWF1R_ADVTHWORD                        ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */

+#define ETH_MACHWF1R_PTOEN_Pos                        (12U)

+#define ETH_MACHWF1R_PTOEN_Msk                        (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */

+#define ETH_MACHWF1R_PTOEN                            ETH_MACHWF1R_PTOEN_Msk   /* PTP Offload Enable */

+#define ETH_MACHWF1R_OSTEN_Pos                        (11U)

+#define ETH_MACHWF1R_OSTEN_Msk                        (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */

+#define ETH_MACHWF1R_OSTEN                            ETH_MACHWF1R_OSTEN_Msk   /* One-Step Timestamping Enable */

+#define ETH_MACHWF1R_TXFIFOSIZE_Pos                   (6U)

+#define ETH_MACHWF1R_TXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */

+#define ETH_MACHWF1R_TXFIFOSIZE                       ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */

+#define ETH_MACHWF1R_RXFIFOSIZE_Pos                   (0U)

+#define ETH_MACHWF1R_RXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */

+#define ETH_MACHWF1R_RXFIFOSIZE                       ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */

+

+/* Bit definition for Ethernet MAC HW Feature2 Register */

+#define ETH_MACHWF2R_AUXSNAPNUM_Pos                   (28U)

+#define ETH_MACHWF2R_AUXSNAPNUM_Msk                   (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */

+#define ETH_MACHWF2R_AUXSNAPNUM                       ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */

+#define ETH_MACHWF2R_PPSOUTNUM_Pos                    (24U)

+#define ETH_MACHWF2R_PPSOUTNUM_Msk                    (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */

+#define ETH_MACHWF2R_PPSOUTNUM                        ETH_MACHWF2R_PPSOUTNUM_Msk /*  Number of PPS Outputs */

+#define ETH_MACHWF2R_TXCHCNT_Pos                      (18U)

+#define ETH_MACHWF2R_TXCHCNT_Msk                      (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */

+#define ETH_MACHWF2R_TXCHCNT                          ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */

+#define ETH_MACHWF2R_RXCHCNT_Pos                      (13U)

+#define ETH_MACHWF2R_RXCHCNT_Msk                      (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000E000 */

+#define ETH_MACHWF2R_RXCHCNT                          ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */

+#define ETH_MACHWF2R_TXQCNT_Pos                       (6U)

+#define ETH_MACHWF2R_TXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */

+#define ETH_MACHWF2R_TXQCNT                           ETH_MACHWF2R_TXQCNT_Msk  /* Number of MTL Transmit Queues */

+#define ETH_MACHWF2R_RXQCNT_Pos                       (0U)

+#define ETH_MACHWF2R_RXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */

+#define ETH_MACHWF2R_RXQCNT                           ETH_MACHWF2R_RXQCNT_Msk  /* Number of MTL Receive Queues */

+

+/* Bit definition for Ethernet MAC MDIO Address Register */

+#define ETH_MACMDIOAR_PSE_Pos                         (27U)

+#define ETH_MACMDIOAR_PSE_Msk                         (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */

+#define ETH_MACMDIOAR_PSE                             ETH_MACMDIOAR_PSE_Msk    /* Preamble Suppression Enable */

+#define ETH_MACMDIOAR_BTB_Pos                         (26U)

+#define ETH_MACMDIOAR_BTB_Msk                         (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */

+#define ETH_MACMDIOAR_BTB                             ETH_MACMDIOAR_BTB_Msk    /* Back to Back transactions */

+#define ETH_MACMDIOAR_PA_Pos                          (21U)

+#define ETH_MACMDIOAR_PA_Msk                          (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */

+#define ETH_MACMDIOAR_PA                              ETH_MACMDIOAR_PA_Msk     /* Physical Layer Address */

+#define ETH_MACMDIOAR_RDA_Pos                         (16U)

+#define ETH_MACMDIOAR_RDA_Msk                         (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */

+#define ETH_MACMDIOAR_RDA                             ETH_MACMDIOAR_RDA_Msk    /* Register/Device Address */

+#define ETH_MACMDIOAR_NTC_Pos                         (12U)

+#define ETH_MACMDIOAR_NTC_Msk                         (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */

+#define ETH_MACMDIOAR_NTC                             ETH_MACMDIOAR_NTC_Msk    /* Number of Trailing Clocks */

+#define ETH_MACMDIOAR_CR_Pos                          (8U)

+#define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */

+#define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */

+#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */

+#define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)

+#define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */

+#define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */

+#define ETH_MACMDIOAR_CR_DIV16_Pos                    (9U)

+#define ETH_MACMDIOAR_CR_DIV16_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */

+#define ETH_MACMDIOAR_CR_DIV16                        ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */

+#define ETH_MACMDIOAR_CR_DIV26_Pos                    (8U)

+#define ETH_MACMDIOAR_CR_DIV26_Msk                    (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */

+#define ETH_MACMDIOAR_CR_DIV26                        ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */

+#define ETH_MACMDIOAR_CR_DIV102_Pos                   (10U)

+#define ETH_MACMDIOAR_CR_DIV102_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */

+#define ETH_MACMDIOAR_CR_DIV102                       ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */

+#define ETH_MACMDIOAR_CR_DIV124_Pos                   (8U)

+#define ETH_MACMDIOAR_CR_DIV124_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */

+#define ETH_MACMDIOAR_CR_DIV124                       ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */

+#define ETH_MACMDIOAR_CR_DIV4AR_Pos                   (11U)

+#define ETH_MACMDIOAR_CR_DIV4AR_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */

+#define ETH_MACMDIOAR_CR_DIV4AR                       ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV6AR_Pos                   (8U)

+#define ETH_MACMDIOAR_CR_DIV6AR_Msk                   (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */

+#define ETH_MACMDIOAR_CR_DIV6AR                       ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV8AR_Pos                   (9U)

+#define ETH_MACMDIOAR_CR_DIV8AR_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */

+#define ETH_MACMDIOAR_CR_DIV8AR                       ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV10AR_Pos                  (8U)

+#define ETH_MACMDIOAR_CR_DIV10AR_Msk                  (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */

+#define ETH_MACMDIOAR_CR_DIV10AR                      ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV12AR_Pos                  (10U)

+#define ETH_MACMDIOAR_CR_DIV12AR_Msk                  (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */

+#define ETH_MACMDIOAR_CR_DIV12AR                      ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV14AR_Pos                  (8U)

+#define ETH_MACMDIOAR_CR_DIV14AR_Msk                  (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */

+#define ETH_MACMDIOAR_CR_DIV14AR                      ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV16AR_Pos                  (9U)

+#define ETH_MACMDIOAR_CR_DIV16AR_Msk                  (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */

+#define ETH_MACMDIOAR_CR_DIV16AR                      ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV18AR_Pos                  (8U)

+#define ETH_MACMDIOAR_CR_DIV18AR_Msk                  (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */

+#define ETH_MACMDIOAR_CR_DIV18AR                      ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_SKAP_Pos                        (4U)

+#define ETH_MACMDIOAR_SKAP_Msk                        (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */

+#define ETH_MACMDIOAR_SKAP                            ETH_MACMDIOAR_SKAP_Msk   /* Skip Address Packet */

+#define ETH_MACMDIOAR_MOC_Pos                         (2U)

+#define ETH_MACMDIOAR_MOC_Msk                         (0x3UL << ETH_MACMDIOAR_MOC_Pos) /*!< 0x0000000C */

+#define ETH_MACMDIOAR_MOC                             ETH_MACMDIOAR_MOC_Msk    /* MII Operation Command */

+#define ETH_MACMDIOAR_MOC_WR_Pos                      (2U)

+#define ETH_MACMDIOAR_MOC_WR_Msk                      (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos) /*!< 0x00000004 */

+#define ETH_MACMDIOAR_MOC_WR                          ETH_MACMDIOAR_MOC_WR_Msk /* Write */

+#define ETH_MACMDIOAR_MOC_PRDIA_Pos                   (3U)

+#define ETH_MACMDIOAR_MOC_PRDIA_Msk                   (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos) /*!< 0x00000008 */

+#define ETH_MACMDIOAR_MOC_PRDIA                       ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */

+#define ETH_MACMDIOAR_MOC_RD_Pos                      (2U)

+#define ETH_MACMDIOAR_MOC_RD_Msk                      (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos) /*!< 0x0000000C */

+#define ETH_MACMDIOAR_MOC_RD                          ETH_MACMDIOAR_MOC_RD_Msk /* Read */

+#define ETH_MACMDIOAR_C45E_Pos                        (1U)

+#define ETH_MACMDIOAR_C45E_Msk                        (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */

+#define ETH_MACMDIOAR_C45E                            ETH_MACMDIOAR_C45E_Msk   /* Clause 45 PHY Enable */

+#define ETH_MACMDIOAR_MB_Pos                          (0U)

+#define ETH_MACMDIOAR_MB_Msk                          (0x1UL << ETH_MACMDIOAR_MB_Pos) /*!< 0x00000001 */

+#define ETH_MACMDIOAR_MB                              ETH_MACMDIOAR_MB_Msk     /* MII Busy */

+

+/* Bit definition for Ethernet MAC MDIO Data Register */

+#define ETH_MACMDIODR_RA_Pos                          (16U)

+#define ETH_MACMDIODR_RA_Msk                          (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */

+#define ETH_MACMDIODR_RA                              ETH_MACMDIODR_RA_Msk     /* Register Address */

+#define ETH_MACMDIODR_MD_Pos                          (0U)

+#define ETH_MACMDIODR_MD_Msk                          (0xFFFFUL << ETH_MACMDIODR_MD_Pos) /*!< 0x0000FFFF */

+#define ETH_MACMDIODR_MD                              ETH_MACMDIODR_MD_Msk     /* MII Data */

+

+/* Bit definition for Ethernet ARP Address Register */

+#define ETH_MACARPAR_ARPPA_Pos                         (0U)

+#define ETH_MACARPAR_ARPPA_Msk                         (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACARPAR_ARPPA                             ETH_MACARPAR_ARPPA_Msk     /* ARP Protocol Address */

+

+/* Bit definition for Ethernet MAC Address 0 High Register */

+#define ETH_MACA0HR_AE_Pos                            (31U)

+#define ETH_MACA0HR_AE_Msk                            (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA0HR_AE                                ETH_MACA0HR_AE_Msk /* Address Enable*/

+#define ETH_MACA0HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA0HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA0HR_ADDRHI                            ETH_MACA0HR_ADDRHI_Msk   /* MAC Address 0*/

+

+/* Bit definition for Ethernet MAC Address 0 Low Register */

+#define ETH_MACA0LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA0LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA0LR_ADDRLO                            ETH_MACA0LR_ADDRLO_Msk   /* MAC Address 0*/

+

+/* Bit definition for Ethernet MAC Address 1 High Register */

+#define ETH_MACA1HR_AE_Pos                            (31U)

+#define ETH_MACA1HR_AE_Msk                            (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk /* Address Enable*/

+#define ETH_MACA1HR_SA_Pos                            (30U)

+#define ETH_MACA1HR_SA_Msk                            (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk /* Source Address */

+#define ETH_MACA1HR_MBC_Pos                           (24U)

+#define ETH_MACA1HR_MBC_Msk                           (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk /* Mask Byte Control */

+#define ETH_MACA1HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA1HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA1HR_ADDRHI                            ETH_MACA1HR_ADDRHI_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 1 Low Register */

+#define ETH_MACA1LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA1LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA1LR_ADDRLO                            ETH_MACA1LR_ADDRLO_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 2 High Register */

+#define ETH_MACA2HR_AE_Pos                            (31U)

+#define ETH_MACA2HR_AE_Msk                            (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk /* Address Enable*/

+#define ETH_MACA2HR_SA_Pos                            (30U)

+#define ETH_MACA2HR_SA_Msk                            (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk /* Source Address */

+#define ETH_MACA2HR_MBC_Pos                           (24U)

+#define ETH_MACA2HR_MBC_Msk                           (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk /* Mask Byte Control */

+#define ETH_MACA2HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA2HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA2HR_ADDRHI                            ETH_MACA2HR_ADDRHI_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 2 Low Register */

+#define ETH_MACA2LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA2LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA2LR_ADDRLO                            ETH_MACA2LR_ADDRLO_Msk   /* MAC Address 2*/

+

+/* Bit definition for Ethernet MAC Address 3 High Register */

+#define ETH_MACA3HR_AE_Pos                            (31U)

+#define ETH_MACA3HR_AE_Msk                            (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk /* Address Enable*/

+#define ETH_MACA3HR_SA_Pos                            (30U)

+#define ETH_MACA3HR_SA_Msk                            (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk /* Source Address */

+#define ETH_MACA3HR_MBC_Pos                           (24U)

+#define ETH_MACA3HR_MBC_Msk                           (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk /* Mask Byte Control */

+#define ETH_MACA3HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA3HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA3HR_ADDRHI                            ETH_MACA3HR_ADDRHI_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 3 Low Register */

+#define ETH_MACA3LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA3LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA3LR_ADDRLO                            ETH_MACA3LR_ADDRLO_Msk   /* MAC Address 3*/

+

+/* Bit definition for Ethernet MAC Address High Register */

+#define ETH_MACAHR_AE_Pos                             (31U)

+#define ETH_MACAHR_AE_Msk                             (0x1UL << ETH_MACAHR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACAHR_AE                                 ETH_MACAHR_AE_Msk        /* Address enable */

+#define ETH_MACAHR_SA_Pos                             (30U)

+#define ETH_MACAHR_SA_Msk                             (0x1UL << ETH_MACAHR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACAHR_SA                                 ETH_MACAHR_SA_Msk        /* Source address */

+#define ETH_MACAHR_MBC_Pos                            (24U)

+#define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */

+#define ETH_MACAHR_MBC_HBITS15_8                      ((uint32_t)0x20000000)   /* Mask MAC Address high reg bits [15:8] */

+#define ETH_MACAHR_MBC_HBITS7_0                       ((uint32_t)0x10000000)   /* Mask MAC Address high reg bits [7:0] */

+#define ETH_MACAHR_MBC_LBITS31_24                     ((uint32_t)0x08000000)   /* Mask MAC Address low reg bits [31:24] */

+#define ETH_MACAHR_MBC_LBITS23_16                     ((uint32_t)0x04000000)   /* Mask MAC Address low reg bits [23:16] */

+#define ETH_MACAHR_MBC_LBITS15_8                      ((uint32_t)0x02000000)   /* Mask MAC Address low reg bits [15:8] */

+#define ETH_MACAHR_MBC_LBITS7_0                       ((uint32_t)0x01000000)   /* Mask MAC Address low reg bits [7:0] */

+#define ETH_MACAHR_MACAH_Pos                          (0U)

+#define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */

+#define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */

+

+/* Bit definition for Ethernet MAC Address Low Register */

+#define ETH_MACALR_MACAL_Pos                          (0U)

+#define ETH_MACALR_MACAL_Msk                          (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACALR_MACAL                              ETH_MACALR_MACAL_Msk     /* MAC address low */

+

+/* Bit definition for Ethernet MMC Control Register */

+#define ETH_MMCCR_UCDBC_Pos                           (8U)

+#define ETH_MMCCR_UCDBC_Msk                           (0x1UL << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */

+#define ETH_MMCCR_UCDBC                               ETH_MMCCR_UCDBC_Msk  /* Update MMC Counters for Dropped Broadcast Packets */

+#define ETH_MMCCR_CNTPRSTLVL_Pos                      (5U)

+#define ETH_MMCCR_CNTPRSTLVL_Msk                      (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */

+#define ETH_MMCCR_CNTPRSTLVL                          ETH_MMCCR_CNTPRSTLVL_Msk  /* Full-Half Preset */

+#define ETH_MMCCR_CNTPRST_Pos                         (4U)

+#define ETH_MMCCR_CNTPRST_Msk                         (0x1UL << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */

+#define ETH_MMCCR_CNTPRST                             ETH_MMCCR_CNTPRST_Msk  /* Counters Reset */

+#define ETH_MMCCR_CNTFREEZ_Pos                        (3U)

+#define ETH_MMCCR_CNTFREEZ_Msk                        (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */

+#define ETH_MMCCR_CNTFREEZ                            ETH_MMCCR_CNTFREEZ_Msk  /* MMC Counter Freeze */

+#define ETH_MMCCR_RSTONRD_Pos                         (2U)

+#define ETH_MMCCR_RSTONRD_Msk                         (0x1UL << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */

+#define ETH_MMCCR_RSTONRD                             ETH_MMCCR_RSTONRD_Msk  /* Reset On Read */

+#define ETH_MMCCR_CNTSTOPRO_Pos                       (1U)

+#define ETH_MMCCR_CNTSTOPRO_Msk                       (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */

+#define ETH_MMCCR_CNTSTOPRO                           ETH_MMCCR_CNTSTOPRO_Msk  /* Counter Stop Rollover */

+#define ETH_MMCCR_CNTRST_Pos                          (0U)

+#define ETH_MMCCR_CNTRST_Msk                          (0x1UL << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */

+#define ETH_MMCCR_CNTRST                              ETH_MMCCR_CNTRST_Msk  /* Counters Reset */

+

+/* Bit definition for Ethernet MMC Rx Interrupt Register */

+#define ETH_MMCRIR_RXLPITRCIS_Pos                     (27U)

+#define ETH_MMCRIR_RXLPITRCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) /*!< 0x08000000 */

+#define ETH_MMCRIR_RXLPITRCIS                         ETH_MMCRIR_RXLPITRCIS_Msk  /* MMC Receive LPI transition counter interrupt status */

+#define ETH_MMCRIR_RXLPIUSCIS_Pos                     (26U)

+#define ETH_MMCRIR_RXLPIUSCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */

+#define ETH_MMCRIR_RXLPIUSCIS                         ETH_MMCRIR_RXLPIUSCIS_Msk  /* MMC Receive LPI microsecond counter interrupt status */

+#define ETH_MMCRIR_RXUCGPIS_Pos                       (17U)

+#define ETH_MMCRIR_RXUCGPIS_Msk                       (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) /*!< 0x00020000 */

+#define ETH_MMCRIR_RXUCGPIS                           ETH_MMCRIR_RXUCGPIS_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Status */

+#define ETH_MMCRIR_RXALGNERPIS_Pos                    (6U)

+#define ETH_MMCRIR_RXALGNERPIS_Msk                    (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) /*!< 0x00000040 */

+#define ETH_MMCRIR_RXALGNERPIS                        ETH_MMCRIR_RXALGNERPIS_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Status */

+#define ETH_MMCRIR_RXCRCERPIS_Pos                     (5U)

+#define ETH_MMCRIR_RXCRCERPIS_Msk                     (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) /*!< 0x00000020 */

+#define ETH_MMCRIR_RXCRCERPIS                         ETH_MMCRIR_RXCRCERPIS_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Status */

+

+/* Bit definition for Ethernet MMC Tx Interrupt Register */

+#define ETH_MMCTIR_TXLPITRCIS_Pos                     (27U)

+#define ETH_MMCTIR_TXLPITRCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) /*!< 0x08000000 */

+#define ETH_MMCTIR_TXLPITRCIS                         ETH_MMCTIR_TXLPITRCIS_Msk  /* MMC Transmit LPI transition counter interrupt status */

+#define ETH_MMCTIR_TXLPIUSCIS_Pos                     (26U)

+#define ETH_MMCTIR_TXLPIUSCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */

+#define ETH_MMCTIR_TXLPIUSCIS                         ETH_MMCTIR_TXLPIUSCIS_Msk  /* MMC Transmit LPI microsecond counter interrupt status */

+#define ETH_MMCTIR_TXGPKTIS_Pos                       (21U)

+#define ETH_MMCTIR_TXGPKTIS_Msk                       (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) /*!< 0x00200000 */

+#define ETH_MMCTIR_TXGPKTIS                           ETH_MMCTIR_TXGPKTIS_Msk  /* MMC Transmit Good Packet Counter Interrupt Status */

+#define ETH_MMCTIR_TXMCOLGPIS_Pos                     (15U)

+#define ETH_MMCTIR_TXMCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */

+#define ETH_MMCTIR_TXMCOLGPIS                         ETH_MMCTIR_TXMCOLGPIS_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */

+#define ETH_MMCTIR_TXSCOLGPIS_Pos                     (14U)

+#define ETH_MMCTIR_TXSCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */

+#define ETH_MMCTIR_TXSCOLGPIS                         ETH_MMCTIR_TXSCOLGPIS_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */

+

+/* Bit definition for Ethernet MMC Rx interrupt Mask register */

+#define ETH_MMCRIMR_RXLPITRCIM_Pos                    (27U)

+#define ETH_MMCRIMR_RXLPITRCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */

+#define ETH_MMCRIMR_RXLPITRCIM                        ETH_MMCRIMR_RXLPITRCIM_Msk  /* MMC Receive LPI transition counter interrupt Mask */

+#define ETH_MMCRIMR_RXLPIUSCIM_Pos                    (26U)

+#define ETH_MMCRIMR_RXLPIUSCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */

+#define ETH_MMCRIMR_RXLPIUSCIM                        ETH_MMCRIMR_RXLPIUSCIM_Msk  /* MMC Receive LPI microsecond counter interrupt Mask */

+#define ETH_MMCRIMR_RXUCGPIM_Pos                      (17U)

+#define ETH_MMCRIMR_RXUCGPIM_Msk                      (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) /*!< 0x00020000 */

+#define ETH_MMCRIMR_RXUCGPIM                          ETH_MMCRIMR_RXUCGPIM_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Mask */

+#define ETH_MMCRIMR_RXALGNERPIM_Pos                   (6U)

+#define ETH_MMCRIMR_RXALGNERPIM_Msk                   (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */

+#define ETH_MMCRIMR_RXALGNERPIM                       ETH_MMCRIMR_RXALGNERPIM_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Mask */

+#define ETH_MMCRIMR_RXCRCERPIM_Pos                    (5U)

+#define ETH_MMCRIMR_RXCRCERPIM_Msk                    (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */

+#define ETH_MMCRIMR_RXCRCERPIM                        ETH_MMCRIMR_RXCRCERPIM_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Mask */

+

+/* Bit definition for Ethernet MMC Tx Interrupt Mask Register */

+#define ETH_MMCTIMR_TXLPITRCIM_Pos                    (27U)

+#define ETH_MMCTIMR_TXLPITRCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */

+#define ETH_MMCTIMR_TXLPITRCIM                        ETH_MMCTIMR_TXLPITRCIM_Msk  /* MMC Transmit LPI transition counter interrupt Mask*/

+#define ETH_MMCTIMR_TXLPIUSCIM_Pos                    (26U)

+#define ETH_MMCTIMR_TXLPIUSCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */

+#define ETH_MMCTIMR_TXLPIUSCIM                        ETH_MMCTIMR_TXLPIUSCIM_Msk  /* MMC Transmit LPI microsecond counter interrupt Mask*/

+#define ETH_MMCTIMR_TXGPKTIM_Pos                      (21U)

+#define ETH_MMCTIMR_TXGPKTIM_Msk                      (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) /*!< 0x00200000 */

+#define ETH_MMCTIMR_TXGPKTIM                          ETH_MMCTIMR_TXGPKTIM_Msk  /* MMC Transmit Good Packet Counter Interrupt Mask*/

+#define ETH_MMCTIMR_TXMCOLGPIM_Pos                    (15U)

+#define ETH_MMCTIMR_TXMCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */

+#define ETH_MMCTIMR_TXMCOLGPIM                        ETH_MMCTIMR_TXMCOLGPIM_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */

+#define ETH_MMCTIMR_TXSCOLGPIM_Pos                    (14U)

+#define ETH_MMCTIMR_TXSCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */

+#define ETH_MMCTIMR_TXSCOLGPIM                        ETH_MMCTIMR_TXSCOLGPIM_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */

+

+/* Bit definition for Ethernet MMC Tx Single Collision Good Packets Register */

+#define ETH_MMCTSCGPR_TXSNGLCOLG_Pos                  (0U)

+#define ETH_MMCTSCGPR_TXSNGLCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTSCGPR_TXSNGLCOLG                      ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */

+

+/* Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register */

+#define ETH_MMCTMCGPR_TXMULTCOLG_Pos                  (0U)

+#define ETH_MMCTMCGPR_TXMULTCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTMCGPR_TXMULTCOLG                      ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */

+

+/* Bit definition for Ethernet MMC Tx Packet Count Good Register */

+#define ETH_MMCTPCGR_TXPKTG_Pos                       (0U)

+#define ETH_MMCTPCGR_TXPKTG_msk                       (0xFFFFFFFFUL <<  ETH_MMCTPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTPCGR_TXPKTG                           ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */

+

+/* Bit definition for Ethernet MMC Rx CRC Error Packets Register */

+#define ETH_MMCRCRCEPR_RXCRCERR_Pos                   (0U)

+#define ETH_MMCRCRCEPR_RXCRCERR_msk                   (0xFFFFFFFFUL <<  ETH_MMCRCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRCRCEPR_RXCRCERR                       ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */

+

+/* Bit definition for Ethernet MMC Rx alignment error packets register */

+#define ETH_MMCRAEPR_RXALGNERR_Pos                    (0U)

+#define ETH_MMCRAEPR_RXALGNERR_msk                    (0xFFFFFFFFUL <<  ETH_MMCRAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRAEPR_RXALGNERR                        ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */

+

+/* Bit definition for Ethernet MMC Rx Unicast Packets Good Register */

+#define ETH_MMCRUPGR_RXUCASTG_Pos                     (0U)

+#define ETH_MMCRUPGR_RXUCASTG_msk                     (0xFFFFFFFFUL <<  ETH_MMCRUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRUPGR_RXUCASTG                         ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */

+

+/* Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register */

+#define ETH_MMCTLPIMSTR_TXLPIUSC_Pos                  (0U)

+#define ETH_MMCTLPIMSTR_TXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCTLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTLPIMSTR_TXLPIUSC                      ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */

+

+/* Bit definition for Ethernet MMC Tx LPI Transition Counter Register */

+#define ETH_MMCTLPITCR_TXLPITRC_Pos                   (0U)

+#define ETH_MMCTLPITCR_TXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCTLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTLPITCR_TXLPITRC                       ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */

+

+/* Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register */

+#define ETH_MMCRLPIMSTR_RXLPIUSC_Pos                  (0U)

+#define ETH_MMCRLPIMSTR_RXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCRLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRLPIMSTR_RXLPIUSC                      ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */

+

+/* Bit definition for Ethernet MMC Rx LPI Transition Counter Register */

+#define ETH_MMCRLPITCR_RXLPITRC_Pos                   (0U)

+#define ETH_MMCRLPITCR_RXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCRLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRLPITCR_RXLPITRC                       ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */

+

+/* Bit definition for Ethernet MAC L3 L4 Control Register */

+#define ETH_MACL3L4CR_L4DPIM_Pos                      (21U)

+#define ETH_MACL3L4CR_L4DPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos) /*!< 0x00200000 */

+#define ETH_MACL3L4CR_L4DPIM                          ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */

+#define ETH_MACL3L4CR_L4DPM_Pos                       (20U)

+#define ETH_MACL3L4CR_L4DPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4DPM_Pos) /*!< 0x00100000 */

+#define ETH_MACL3L4CR_L4DPM                           ETH_MACL3L4CR_L4DPM_Msk  /* Layer 4 Destination Port Match Enable */

+#define ETH_MACL3L4CR_L4SPIM_Pos                      (19U)

+#define ETH_MACL3L4CR_L4SPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos) /*!< 0x00080000 */

+#define ETH_MACL3L4CR_L4SPIM                          ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */

+#define ETH_MACL3L4CR_L4SPM_Pos                       (18U)

+#define ETH_MACL3L4CR_L4SPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4SPM_Pos) /*!< 0x00040000 */

+#define ETH_MACL3L4CR_L4SPM                           ETH_MACL3L4CR_L4SPM_Msk  /* Layer 4 Source Port Match Enable */

+#define ETH_MACL3L4CR_L4PEN_Pos                       (16U)

+#define ETH_MACL3L4CR_L4PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L4PEN_Pos) /*!< 0x00010000 */

+#define ETH_MACL3L4CR_L4PEN                           ETH_MACL3L4CR_L4PEN_Msk  /* Layer 4 Protocol Enable */

+#define ETH_MACL3L4CR_L3HDBM_Pos                      (11U)

+#define ETH_MACL3L4CR_L3HDBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos) /*!< 0x0000F800 */

+#define ETH_MACL3L4CR_L3HDBM                          ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */

+#define ETH_MACL3L4CR_L3HSBM_Pos                      (6U)

+#define ETH_MACL3L4CR_L3HSBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos) /*!< 0x000007C0 */

+#define ETH_MACL3L4CR_L3HSBM                          ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */

+#define ETH_MACL3L4CR_L3DAIM_Pos                      (5U)

+#define ETH_MACL3L4CR_L3DAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos) /*!< 0x00000020 */

+#define ETH_MACL3L4CR_L3DAIM                          ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */

+#define ETH_MACL3L4CR_L3DAM_Pos                       (4U)

+#define ETH_MACL3L4CR_L3DAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3DAM_Pos) /*!< 0x00000010 */

+#define ETH_MACL3L4CR_L3DAM                           ETH_MACL3L4CR_L3DAM_Msk  /* Layer 3 IP DA Match Enable */

+#define ETH_MACL3L4CR_L3SAIM_Pos                      (3U)

+#define ETH_MACL3L4CR_L3SAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos) /*!< 0x00000008 */

+#define ETH_MACL3L4CR_L3SAIM                          ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */

+#define ETH_MACL3L4CR_L3SAM_Pos                       (2U)

+#define ETH_MACL3L4CR_L3SAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3SAM_Pos) /*!< 0x00000004 */

+#define ETH_MACL3L4CR_L3SAM                           ETH_MACL3L4CR_L3SAM_Msk  /* Layer 3 IP SA Match Enable*/

+#define ETH_MACL3L4CR_L3PEN_Pos                       (0U)

+#define ETH_MACL3L4CR_L3PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L3PEN_Pos) /*!< 0x00000001 */

+#define ETH_MACL3L4CR_L3PEN                           ETH_MACL3L4CR_L3PEN_Msk  /* Layer 3 Protocol Enable */

+

+/* Bit definition for Ethernet MAC L4 Address Register */

+#define ETH_MACL4AR_L4DP_Pos                          (16U)

+#define ETH_MACL4AR_L4DP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4DP_Pos) /*!< 0xFFFF0000 */

+#define ETH_MACL4AR_L4DP                              ETH_MACL4AR_L4DP_Msk     /* Layer 4 Destination Port Number Field */

+#define ETH_MACL4AR_L4SP_Pos                          (0U)

+#define ETH_MACL4AR_L4SP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4SP_Pos) /*!< 0x0000FFFF */

+#define ETH_MACL4AR_L4SP                              ETH_MACL4AR_L4SP_Msk     /* Layer 4 Source Port Number Field */

+

+/* Bit definition for Ethernet MAC L3 Address0 Register */

+#define ETH_MACL3A0R_L3A0_Pos                         (0U)

+#define ETH_MACL3A0R_L3A0_Msk                         (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A0R_L3A0                             ETH_MACL3A0R_L3A0_Msk    /* Layer 3 Address 0 Field */

+

+/* Bit definition for Ethernet MAC L4 Address1 Register */

+#define ETH_MACL3A1R_L3A1_Pos                         (0U)

+#define ETH_MACL3A1R_L3A1_Msk                         (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A1R_L3A1                             ETH_MACL3A1R_L3A1_Msk    /* Layer 3 Address 1 Field */

+

+/* Bit definition for Ethernet MAC L4 Address2 Register */

+#define ETH_MACL3A2R_L3A2_Pos                         (0U)

+#define ETH_MACL3A2R_L3A2_Msk                         (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A2R_L3A2                             ETH_MACL3A2R_L3A2_Msk    /* Layer 3 Address 2 Field */

+

+/* Bit definition for Ethernet MAC L4 Address3 Register */

+#define ETH_MACL3A3R_L3A3_Pos                         (0U)

+#define ETH_MACL3A3R_L3A3_Msk                         (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A3R_L3A3                             ETH_MACL3A3R_L3A3_Msk    /* Layer 3 Address 3 Field */

+

+/* Bit definition for Ethernet MAC Timestamp Control Register */

+#define ETH_MACTSCR_TXTSSTSM_Pos                      (24U)

+#define ETH_MACTSCR_TXTSSTSM_Msk                      (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */

+#define ETH_MACTSCR_TXTSSTSM                          ETH_MACTSCR_TXTSSTSM_Msk  /* Transmit Timestamp Status Mode */

+#define ETH_MACTSCR_CSC_Pos                           (19U)

+#define ETH_MACTSCR_CSC_Msk                           (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */

+#define ETH_MACTSCR_CSC                               ETH_MACTSCR_CSC_Msk  /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */

+#define ETH_MACTSCR_TSENMACADDR_Pos                   (18U)

+#define ETH_MACTSCR_TSENMACADDR_Msk                   (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */

+#define ETH_MACTSCR_TSENMACADDR                       ETH_MACTSCR_TSENMACADDR_Msk  /* Enable MAC Address for PTP Packet Filtering */

+#define ETH_MACTSCR_SNAPTYPSEL_Pos                    (16U)

+#define ETH_MACTSCR_SNAPTYPSEL_Msk                    (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */

+#define ETH_MACTSCR_SNAPTYPSEL                        ETH_MACTSCR_SNAPTYPSEL_Msk  /* Select PTP packets for Taking Snapshots */

+#define ETH_MACTSCR_TSMSTRENA_Pos                     (15U)

+#define ETH_MACTSCR_TSMSTRENA_Msk                     (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */

+#define ETH_MACTSCR_TSMSTRENA                         ETH_MACTSCR_TSMSTRENA_Msk  /* Enable Snapshot for Messages Relevant to Master */

+#define ETH_MACTSCR_TSEVNTENA_Pos                     (14U)

+#define ETH_MACTSCR_TSEVNTENA_Msk                     (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */

+#define ETH_MACTSCR_TSEVNTENA                         ETH_MACTSCR_TSEVNTENA_Msk  /* Enable Timestamp Snapshot for Event Messages */

+#define ETH_MACTSCR_TSIPV4ENA_Pos                     (13U)

+#define ETH_MACTSCR_TSIPV4ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */

+#define ETH_MACTSCR_TSIPV4ENA                         ETH_MACTSCR_TSIPV4ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv4-UDP */

+#define ETH_MACTSCR_TSIPV6ENA_Pos                     (12U)

+#define ETH_MACTSCR_TSIPV6ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */

+#define ETH_MACTSCR_TSIPV6ENA                         ETH_MACTSCR_TSIPV6ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv6-UDP */

+#define ETH_MACTSCR_TSIPENA_Pos                       (11U)

+#define ETH_MACTSCR_TSIPENA_Msk                       (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */

+#define ETH_MACTSCR_TSIPENA                           ETH_MACTSCR_TSIPENA_Msk  /* Enable Processing of PTP over Ethernet Packets */

+#define ETH_MACTSCR_TSVER2ENA_Pos                     (10U)

+#define ETH_MACTSCR_TSVER2ENA_Msk                     (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */

+#define ETH_MACTSCR_TSVER2ENA                         ETH_MACTSCR_TSVER2ENA_Msk  /* Enable PTP Packet Processing for Version 2 Format */

+#define ETH_MACTSCR_TSCTRLSSR_Pos                     (9U)

+#define ETH_MACTSCR_TSCTRLSSR_Msk                     (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */

+#define ETH_MACTSCR_TSCTRLSSR                         ETH_MACTSCR_TSCTRLSSR_Msk  /* Timestamp Digital or Binary Rollover Control */

+#define ETH_MACTSCR_TSENALL_Pos                       (8U)

+#define ETH_MACTSCR_TSENALL_Msk                       (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */

+#define ETH_MACTSCR_TSENALL                           ETH_MACTSCR_TSENALL_Msk  /* Enable Timestamp for All Packets */

+#define ETH_MACTSCR_TSADDREG_Pos                      (5U)

+#define ETH_MACTSCR_TSADDREG_Msk                      (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */

+#define ETH_MACTSCR_TSADDREG                          ETH_MACTSCR_TSADDREG_Msk  /* Update Addend Register */

+#define ETH_MACTSCR_TSUPDT_Pos                        (3U)

+#define ETH_MACTSCR_TSUPDT_Msk                        (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */

+#define ETH_MACTSCR_TSUPDT                            ETH_MACTSCR_TSUPDT_Msk  /* Update Timestamp */

+#define ETH_MACTSCR_TSINIT_Pos                        (2U)

+#define ETH_MACTSCR_TSINIT_Msk                        (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */

+#define ETH_MACTSCR_TSINIT                             ETH_MACTSCR_TSINIT_Msk  /* Initialize Timestamp */

+#define ETH_MACTSCR_TSCFUPDT_Pos                      (1U)

+#define ETH_MACTSCR_TSCFUPDT_Msk                      (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */

+#define ETH_MACTSCR_TSCFUPDT                          ETH_MACTSCR_TSCFUPDT_Msk  /* Fine or Coarse Timestamp Update*/

+#define ETH_MACTSCR_TSENA_Pos                         (0U)

+#define ETH_MACTSCR_TSENA_Msk                         (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */

+#define ETH_MACTSCR_TSENA                             ETH_MACTSCR_TSENA_Msk  /* Enable Timestamp */

+

+/* Bit definition for Ethernet MAC Sub-second Increment Register */

+#define ETH_MACMACSSIR_SSINC_Pos                      (16U)

+#define ETH_MACMACSSIR_SSINC_Msk                      (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) /*!< 0x0000FF00 */

+#define ETH_MACMACSSIR_SSINC                          ETH_MACMACSSIR_SSINC_Msk  /* Sub-second Increment Value */

+#define ETH_MACMACSSIR_SNSINC_Pos                     (8U)

+#define ETH_MACMACSSIR_SNSINC_Msk                     (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos) /*!< 0x000000FF */

+#define ETH_MACMACSSIR_SNSINC                         ETH_MACMACSSIR_SNSINC_Msk  /* Sub-nanosecond Increment Value */

+

+/* Bit definition for Ethernet MAC System Time Seconds Register */

+#define ETH_MACSTSR_TSS_Pos                           (0U)

+#define ETH_MACSTSR_TSS_Msk                           (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSTSR_TSS                               ETH_MACSTSR_TSS_Msk  /* Timestamp Second */

+

+/* Bit definition for Ethernet MAC System Time Nanoseconds Register */

+#define ETH_MACSTNR_TSSS_Pos                          (0U)

+#define ETH_MACSTNR_TSSS_Msk                          (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACSTNR_TSSS                              ETH_MACSTNR_TSSS_Msk  /* Timestamp Sub-seconds */

+

+/* Bit definition for Ethernet MAC System Time Seconds Update Register */

+#define ETH_MACSTSUR_TSS_Pos                          (0U)

+#define ETH_MACSTSUR_TSS_Msk                          (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSTSUR_TSS                              ETH_MACSTSUR_TSS_Msk  /* Timestamp Seconds */

+

+/* Bit definition for Ethernet MAC System Time Nanoseconds Update Register */

+#define ETH_MACSTNUR_ADDSUB_Pos                       (31U)

+#define ETH_MACSTNUR_ADDSUB_Msk                       (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */

+#define ETH_MACSTNUR_ADDSUB                           ETH_MACSTNUR_ADDSUB_Msk  /* Add or Subtract Time */

+#define ETH_MACSTNUR_TSSS_Pos                         (0U)

+#define ETH_MACSTNUR_TSSS_Msk                         (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACSTNUR_TSSS                             ETH_MACSTNUR_TSSS_Msk  /* Timestamp Sub-seconds */

+

+/* Bit definition for Ethernet MAC Timestamp Addend Register */

+#define ETH_MACTSAR_TSAR_Pos                          (0U)

+#define ETH_MACTSAR_TSAR_Msk                          (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSAR_TSAR                              ETH_MACTSAR_TSAR_Msk  /* Timestamp Addend Register */

+

+/* Bit definition for Ethernet MAC Timestamp Status Register */

+#define ETH_MACTSSR_ATSNS_Pos                         (25U)

+#define ETH_MACTSSR_ATSNS_Msk                         (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */

+#define ETH_MACTSSR_ATSNS                             ETH_MACTSSR_ATSNS_Msk  /* Number of Auxiliary Timestamp Snapshots */

+#define ETH_MACTSSR_ATSSTM_Pos                        (24U)

+#define ETH_MACTSSR_ATSSTM_Msk                        (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */

+#define ETH_MACTSSR_ATSSTM                            ETH_MACTSSR_ATSSTM_Msk  /* Auxiliary Timestamp Snapshot Trigger Missed */

+#define ETH_MACTSSR_ATSSTN_Pos                        (16U)

+#define ETH_MACTSSR_ATSSTN_Msk                        (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */

+#define ETH_MACTSSR_ATSSTN                            ETH_MACTSSR_ATSSTN_Msk  /* Auxiliary Timestamp Snapshot Trigger Identifier */

+#define ETH_MACTSSR_TXTSSIS_Pos                       (15U)

+#define ETH_MACTSSR_TXTSSIS_Msk                       (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */

+#define ETH_MACTSSR_TXTSSIS                           ETH_MACTSSR_TXTSSIS_Msk  /* Tx Timestamp Status Interrupt Status */

+#define ETH_MACTSSR_TSTRGTERR0_Pos                    (3U)

+#define ETH_MACTSSR_TSTRGTERR0_Msk                    (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */

+#define ETH_MACTSSR_TSTRGTERR0                        ETH_MACTSSR_TSTRGTERR0_Msk  /* Timestamp Target Time Error */

+#define ETH_MACTSSR_AUXTSTRIG_Pos                     (2U)

+#define ETH_MACTSSR_AUXTSTRIG_Msk                     (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */

+#define ETH_MACTSSR_AUXTSTRIG                         ETH_MACTSSR_AUXTSTRIG_Msk  /* Auxiliary Timestamp Trigger Snapshot*/

+#define ETH_MACTSSR_TSTARGT0_Pos                      (1U)

+#define ETH_MACTSSR_TSTARGT0_Msk                      (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */

+#define ETH_MACTSSR_TSTARGT0                          ETH_MACTSSR_TSTARGT0_Msk  /* Timestamp Target Time Reached */

+#define ETH_MACTSSR_TSSOVF_Pos                        (0U)

+#define ETH_MACTSSR_TSSOVF_Msk                        (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */

+#define ETH_MACTSSR_TSSOVF                            ETH_MACTSSR_TSSOVF_Msk  /* Timestamp Seconds Overflow */

+

+/* Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register */

+#define ETH_MACTTSSNR_TXTSSMIS_Pos                    (31U)

+#define ETH_MACTTSSNR_TXTSSMIS_Msk                    (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */

+#define ETH_MACTTSSNR_TXTSSMIS                        ETH_MACTTSSNR_TXTSSMIS_Msk  /* Transmit Timestamp Status Missed */

+#define ETH_MACTTSSNR_TXTSSLO_Pos                     (0U)

+#define ETH_MACTTSSNR_TXTSSLO_Msk                     (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACTTSSNR_TXTSSLO                         ETH_MACTTSSNR_TXTSSLO_Msk  /* Transmit Timestamp Status Low */

+

+/* Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register */

+#define ETH_MACTTSSSR_TXTSSHI_Pos                     (0U)

+#define ETH_MACTTSSSR_TXTSSHI_Msk                     (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTTSSSR_TXTSSHI                         ETH_MACTTSSSR_TXTSSHI_Msk  /* Transmit Timestamp Status High */

+

+/* Bit definition for Ethernet MAC Auxiliary Control Register*/

+#define ETH_MACACR_ATSEN3_Pos                         (7U)

+#define ETH_MACACR_ATSEN3_Msk                         (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */

+#define ETH_MACACR_ATSEN3                             ETH_MACACR_ATSEN3_Msk  /* Auxiliary Snapshot 3 Enable */

+#define ETH_MACACR_ATSEN2_Pos                         (6U)

+#define ETH_MACACR_ATSEN2_Msk                         (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */

+#define ETH_MACACR_ATSEN2                             ETH_MACACR_ATSEN2_Msk  /* Auxiliary Snapshot 2 Enable */

+#define ETH_MACACR_ATSEN1_Pos                         (5U)

+#define ETH_MACACR_ATSEN1_Msk                         (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */

+#define ETH_MACACR_ATSEN1                             ETH_MACACR_ATSEN1_Msk  /* Auxiliary Snapshot 1 Enable */

+#define ETH_MACACR_ATSEN0_Pos                         (4U)

+#define ETH_MACACR_ATSEN0_Msk                         (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */

+#define ETH_MACACR_ATSEN0                             ETH_MACACR_ATSEN0_Msk  /* Auxiliary Snapshot 0 Enable */

+#define ETH_MACACR_ATSFC_Pos                          (0U)

+#define ETH_MACACR_ATSFC_Msk                          (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */

+#define ETH_MACACR_ATSFC                              ETH_MACACR_ATSFC_Msk  /* Auxiliary Snapshot FIFO Clear */

+

+/* Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register */

+#define ETH_MACATSNR_AUXTSLO_Pos                      (0U)

+#define ETH_MACATSNR_AUXTSLO_Msk                      (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACATSNR_AUXTSLO                          ETH_MACATSNR_AUXTSLO_Msk  /* Auxiliary Timestamp */

+

+/* Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register */

+#define ETH_MACATSSR_AUXTSHI_Pos                      (0U)

+#define ETH_MACATSSR_AUXTSHI_Msk                      (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACATSSR_AUXTSHI                          ETH_MACATSSR_AUXTSHI_Msk  /* Auxiliary Timestamp */

+

+/* Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register */

+#define ETH_MACTSIACR_OSTIAC_Pos                      (0U)

+#define ETH_MACTSIACR_OSTIAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSIACR_OSTIAC                          ETH_MACTSIACR_OSTIAC_Msk  /* One-Step Timestamp Ingress Asymmetry Correction */

+

+/* Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction Register */

+#define ETH_MACTSEACR_OSTEAC_Pos                      (0U)

+#define ETH_MACTSEACR_OSTEAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSEACR_OSTEAC                          ETH_MACTSEACR_OSTEAC_Msk  /* One-Step Timestamp Egress Asymmetry Correction */

+

+/* Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond Register */

+#define ETH_MACTSICNR_TSIC_Pos                        (0U)

+#define ETH_MACTSICNR_TSIC_Msk                        (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSICNR_TSIC                            ETH_MACTSICNR_TSIC_Msk  /* Timestamp Ingress Correction */

+

+/* Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond Register */

+#define ETH_MACTSECNR_TSEC_Pos                        (0U)

+#define ETH_MACTSECNR_TSEC_Msk                        (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSECNR_TSEC                            ETH_MACTSECNR_TSEC_Msk  /* Timestamp Egress Correction */

+

+/* Bit definition for Ethernet MAC PPS Control Register */

+#define ETH_MACPPSCR_TRGTMODSEL0_Pos                  (5U)

+#define ETH_MACPPSCR_TRGTMODSEL0_Msk                  (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */

+#define ETH_MACPPSCR_TRGTMODSEL0                      ETH_MACPPSCR_TRGTMODSEL0_Msk  /* Target Time Register Mode for PPS Output */

+#define ETH_MACPPSCR_PPSEN0_Pos                       (4U)

+#define ETH_MACPPSCR_PPSEN0_Msk                       (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */

+#define ETH_MACPPSCR_PPSEN0                           ETH_MACPPSCR_PPSEN0_Msk  /* Flexible PPS Output Mode Enable */

+#define ETH_MACPPSCR_PPSCTRL_Pos                      (0U)

+#define ETH_MACPPSCR_PPSCTRL_Msk                      (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */

+#define ETH_MACPPSCR_PPSCTRL                          ETH_MACPPSCR_PPSCTRL_Msk  /* PPS Output Frequency Control */

+

+/* Bit definition for Ethernet MAC PPS Target Time Seconds Register */

+#define ETH_MACPPSTTSR_TSTRH0_Pos                     (0U)

+#define ETH_MACPPSTTSR_TSTRH0_Msk                     (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACPPSTTSR_TSTRH0                         ETH_MACPPSTTSR_TSTRH0_Msk  /* PPS Target Time Seconds Register */

+

+/* Bit definition for Ethernet MAC PPS Target Time Nanoseconds Register */

+#define ETH_MACPPSTTNR_TRGTBUSY0_Pos                  (31U)

+#define ETH_MACPPSTTNR_TRGTBUSY0_Msk                  (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos) /*!< 0x80000000 */

+#define ETH_MACPPSTTNR_TRGTBUSY0                      ETH_MACPPSTTNR_TRGTBUSY0_Msk  /* PPS Target Time Register Busy */

+#define ETH_MACPPSTTNR_TTSL0_Pos                      (0U)

+#define ETH_MACPPSTTNR_TTSL0_Msk                      (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACPPSTTNR_TTSL0                          ETH_MACPPSTTNR_TTSL0_Msk  /* Target Time Low for PPS Register */

+

+/* Bit definition for Ethernet MAC PPS Interval Register */

+#define ETH_MACPPSIR_PPSINT0_Pos                      (0U)

+#define ETH_MACPPSIR_PPSINT0_Msk                      (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACPPSIR_PPSINT0                          ETH_MACPPSIR_PPSINT0_Msk  /* PPS Output Signal Interval */

+

+/* Bit definition for Ethernet MAC PPS Width Register */

+#define ETH_MACPPSWR_PPSWIDTH0_Pos                    (0U)

+#define ETH_MACPPSWR_PPSWIDTH0_Msk                    (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACPPSWR_PPSWIDTH0                        ETH_MACPPSWR_PPSWIDTH0_Msk  /* PPS Output Signal Width */

+

+/* Bit definition for Ethernet MAC PTP Offload Control Register */

+#define ETH_MACPOCR_DN_Pos                            (8U)

+#define ETH_MACPOCR_DN_Msk                            (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */

+#define ETH_MACPOCR_DN                                ETH_MACPOCR_DN_Msk  /* Domain Number */

+#define ETH_MACPOCR_DRRDIS_Pos                        (6U)

+#define ETH_MACPOCR_DRRDIS_Msk                        (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */

+#define ETH_MACPOCR_DRRDIS                            ETH_MACPOCR_DRRDIS_Msk  /* Disable PTO Delay Request/Response response generation */

+#define ETH_MACPOCR_APDREQTRIG_Pos                    (5U)

+#define ETH_MACPOCR_APDREQTRIG_Msk                    (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */

+#define ETH_MACPOCR_APDREQTRIG                        ETH_MACPOCR_APDREQTRIG_Msk  /* Automatic PTP Pdelay_Req message Trigger */

+#define ETH_MACPOCR_ASYNCTRIG_Pos                     (4U)

+#define ETH_MACPOCR_ASYNCTRIG_Msk                     (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */

+#define ETH_MACPOCR_ASYNCTRIG                         ETH_MACPOCR_ASYNCTRIG_Msk  /* Automatic PTP SYNC message Trigger */

+#define ETH_MACPOCR_APDREQEN_Pos                      (2U)

+#define ETH_MACPOCR_APDREQEN_Msk                      (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */

+#define ETH_MACPOCR_APDREQEN                          ETH_MACPOCR_APDREQEN_Msk  /* Automatic PTP Pdelay_Req message Enable */

+#define ETH_MACPOCR_ASYNCEN_Pos                       (1U)

+#define ETH_MACPOCR_ASYNCEN_Msk                       (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */

+#define ETH_MACPOCR_ASYNCEN                           ETH_MACPOCR_ASYNCEN_Msk  /* Automatic PTP SYNC message Enable */

+#define ETH_MACPOCR_PTOEN_Pos                         (0U)

+#define ETH_MACPOCR_PTOEN_Msk                         (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */

+#define ETH_MACPOCR_PTOEN                             ETH_MACPOCR_PTOEN_Msk  /* PTP Offload Enable */

+

+/* Bit definition for Ethernet MAC PTP Source Port Identity 0 Register */

+#define ETH_MACSPI0R_SPI0_Pos                         (0U)

+#define ETH_MACSPI0R_SPI0_Msk                         (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSPI0R_SPI0                             ETH_MACSPI0R_SPI0_Msk  /* Source Port Identity 0 */

+

+/* Bit definition for Ethernet MAC PTP Source Port Identity 1 Register */

+#define ETH_MACSPI1R_SPI1_Pos                         (0U)

+#define ETH_MACSPI1R_SPI1_Msk                         (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSPI1R_SPI1                             ETH_MACSPI1R_SPI1_Msk  /* Source Port Identity 1 */

+

+/* Bit definition for Ethernet MAC PTP Source Port Identity 2 Register */

+#define ETH_MACSPI2R_SPI2_Pos                         (0U)

+#define ETH_MACSPI2R_SPI2_Msk                         (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */

+#define ETH_MACSPI2R_SPI2                             ETH_MACSPI2R_SPI2_Msk  /* Source Port Identity 2 */

+

+/* Bit definition for Ethernet MAC Log Message Interval Register */

+#define ETH_MACLMIR_LMPDRI_Pos                        (24U)

+#define ETH_MACLMIR_LMPDRI_Msk                        (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */

+#define ETH_MACLMIR_LMPDRI                             ETH_MACLMIR_LMPDRI_Msk  /* Log Min Pdelay_Req Interval */

+#define ETH_MACLMIR_DRSYNCR_Pos                       (8U)

+#define ETH_MACLMIR_DRSYNCR_Msk                       (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */

+#define ETH_MACLMIR_DRSYNCR                           ETH_MACLMIR_DRSYNCR_Msk  /* Delay_Req to SYNC Ratio */

+#define ETH_MACLMIR_LSI_Pos                           (0U)

+#define ETH_MACLMIR_LSI_Msk                           (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */

+#define ETH_MACLMIR_LSI                               ETH_MACLMIR_LSI_Msk  /* Log Sync Interval */

+

+/* Bit definition for Ethernet MTL Operation Mode Register */

+#define ETH_MTLOMR_CNTCLR_Pos                         (9U)

+#define ETH_MTLOMR_CNTCLR_Msk                         (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */

+#define ETH_MTLOMR_CNTCLR                             ETH_MTLOMR_CNTCLR_Msk    /* Counters Reset */

+#define ETH_MTLOMR_CNTPRST_Pos                        (8U)

+#define ETH_MTLOMR_CNTPRST_Msk                        (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */

+#define ETH_MTLOMR_CNTPRST                            ETH_MTLOMR_CNTPRST_Msk   /* Counters Preset */

+#define ETH_MTLOMR_DTXSTS_Pos                         (1U)

+#define ETH_MTLOMR_DTXSTS_Msk                         (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */

+#define ETH_MTLOMR_DTXSTS                             ETH_MTLOMR_DTXSTS_Msk  /* Drop Transmit Status */

+

+/* Bit definition for Ethernet MTL Interrupt Status Register */

+#define ETH_MTLISR_MACIS_Pos                          (16U)

+#define ETH_MTLISR_MACIS_Msk                          (0x1UL << ETH_MTLISR_MACIS_Pos) /*!< 0x00010000 */

+#define ETH_MTLISR_MACIS                              ETH_MTLISR_MACIS_Msk     /* MAC Interrupt Status */

+#define ETH_MTLISR_QIS_Pos                            (0U)

+#define ETH_MTLISR_QIS_Msk                            (0x1UL << ETH_MTLISR_QIS_Pos) /*!< 0x00000001 */

+#define ETH_MTLISR_QIS                                ETH_MTLISR_QIS_Msk       /* Queue Interrupt status */

+

+/* Bit definition for Ethernet MTL Tx Queue Operation Mode Register */

+#define ETH_MTLTQOMR_TTC_Pos                          (4U)

+#define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */

+#define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */

+#define ETH_MTLTQOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */

+#define ETH_MTLTQOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */

+#define ETH_MTLTQOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */

+#define ETH_MTLTQOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */

+#define ETH_MTLTQOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */

+#define ETH_MTLTQOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */

+#define ETH_MTLTQOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */

+#define ETH_MTLTQOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */

+#define ETH_MTLTQOMR_TSF_Pos                          (1U)

+#define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */

+#define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */

+#define ETH_MTLTQOMR_FTQ_Pos                          (0U)

+#define ETH_MTLTQOMR_FTQ_Msk                          (0x1UL << ETH_MTLTQOMR_FTQ_Pos) /*!< 0x00000001 */

+#define ETH_MTLTQOMR_FTQ                              ETH_MTLTQOMR_FTQ_Msk     /* Flush Transmit Queue */

+

+/* Bit definition for Ethernet MTL Tx Queue Underflow Register */

+#define ETH_MTLTQUR_UFCNTOVF_Pos                      (11U)

+#define ETH_MTLTQUR_UFCNTOVF_Msk                      (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos) /*!< 0x00000800 */

+#define ETH_MTLTQUR_UFCNTOVF                          ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */

+#define ETH_MTLTQUR_UFPKTCNT_Pos                      (0U)

+#define ETH_MTLTQUR_UFPKTCNT_Msk                      (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos) /*!< 0x000007FF */

+#define ETH_MTLTQUR_UFPKTCNT                          ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */

+

+/* Bit definition for Ethernet MTL Tx Queue Debug Register */

+#define ETH_MTLTQDR_STXSTSF_Pos                       (20U)

+#define ETH_MTLTQDR_STXSTSF_Msk                       (0x7UL << ETH_MTLTQDR_STXSTSF_Pos) /*!< 0x00700000 */

+#define ETH_MTLTQDR_STXSTSF                           ETH_MTLTQDR_STXSTSF_Msk  /* Number of Status Words in the Tx Status FIFO of Queue */

+#define ETH_MTLTQDR_PTXQ_Pos                          (16U)

+#define ETH_MTLTQDR_PTXQ_Msk                          (0x7UL << ETH_MTLTQDR_PTXQ_Pos) /*!< 0x00070000 */

+#define ETH_MTLTQDR_PTXQ                              ETH_MTLTQDR_PTXQ_Msk     /* Number of Packets in the Transmit Queue */

+#define ETH_MTLTQDR_TXSTSFSTS_Pos                     (5U)

+#define ETH_MTLTQDR_TXSTSFSTS_Msk                     (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos) /*!< 0x00000020 */

+#define ETH_MTLTQDR_TXSTSFSTS                         ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */

+#define ETH_MTLTQDR_TXQSTS_Pos                        (4U)

+#define ETH_MTLTQDR_TXQSTS_Msk                        (0x1UL << ETH_MTLTQDR_TXQSTS_Pos) /*!< 0x00000010 */

+#define ETH_MTLTQDR_TXQSTS                            ETH_MTLTQDR_TXQSTS_Msk   /* MTL Tx Queue Not Empty Status */

+#define ETH_MTLTQDR_TWCSTS_Pos                        (3U)

+#define ETH_MTLTQDR_TWCSTS_Msk                        (0x1UL << ETH_MTLTQDR_TWCSTS_Pos) /*!< 0x00000008 */

+#define ETH_MTLTQDR_TWCSTS                            ETH_MTLTQDR_TWCSTS_Msk   /* MTL Tx Queue Write Controller Status */

+#define ETH_MTLTQDR_TRCSTS_Pos                        (1U)

+#define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */

+#define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */

+#define ETH_MTLTQDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */

+#define ETH_MTLTQDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */

+#define ETH_MTLTQDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */

+#define ETH_MTLTQDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */

+#define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)

+#define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */

+#define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */

+

+/* Bit definition for Ethernet MTL Queue Interrupt Control Status Register */

+#define ETH_MTLQICSR_RXOIE_Pos                        (24U)

+#define ETH_MTLQICSR_RXOIE_Msk                        (0x1UL << ETH_MTLQICSR_RXOIE_Pos) /*!< 0x01000000 */

+#define ETH_MTLQICSR_RXOIE                            ETH_MTLQICSR_RXOIE_Msk   /* Receive Queue Overflow Interrupt Enable */

+#define ETH_MTLQICSR_RXOVFIS_Pos                      (16U)

+#define ETH_MTLQICSR_RXOVFIS_Msk                      (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos) /*!< 0x00010000 */

+#define ETH_MTLQICSR_RXOVFIS                          ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */

+#define ETH_MTLQICSR_TXUIE_Pos                        (8U)

+#define ETH_MTLQICSR_TXUIE_Msk                        (0x1UL << ETH_MTLQICSR_TXUIE_Pos) /*!< 0x00000100 */

+#define ETH_MTLQICSR_TXUIE                            ETH_MTLQICSR_TXUIE_Msk   /* Transmit Queue Underflow Interrupt Enable */

+#define ETH_MTLQICSR_TXUNFIS_Pos                      (0U)

+#define ETH_MTLQICSR_TXUNFIS_Msk                      (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos) /*!< 0x00000001 */

+#define ETH_MTLQICSR_TXUNFIS                          ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */

+

+/* Bit definition for Ethernet MTL Rx Queue Operation Mode Register */

+#define ETH_MTLRQOMR_RQS_Pos                          (20U)

+#define ETH_MTLRQOMR_RQS_Msk                          (0x7UL << ETH_MTLRQOMR_RQS_Pos) /*!< 0x00700000 */

+#define ETH_MTLRQOMR_RQS                              ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */

+#define ETH_MTLRQOMR_RFD_Pos                          (14U)

+#define ETH_MTLRQOMR_RFD_Msk                          (0x7UL << ETH_MTLRQOMR_RFD_Pos) /*!< 0x0001C000 */

+#define ETH_MTLRQOMR_RFD                              ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */

+#define ETH_MTLRQOMR_RFA_Pos                          (8U)

+#define ETH_MTLRQOMR_RFA_Msk                          (0x7UL << ETH_MTLRQOMR_RFA_Pos) /*!< 0x00000700 */

+#define ETH_MTLRQOMR_RFA                              ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */

+#define ETH_MTLRQOMR_EHFC_Pos                         (7U)

+#define ETH_MTLRQOMR_EHFC_Msk                         (0x1UL << ETH_MTLRQOMR_EHFC_Pos) /*!< 0x00000080 */

+#define ETH_MTLRQOMR_EHFC                             ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */

+#define ETH_MTLRQOMR_DISTCPEF_Pos                     (6U)

+#define ETH_MTLRQOMR_DISTCPEF_Msk                     (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos) /*!< 0x00000040 */

+#define ETH_MTLRQOMR_DISTCPEF                         ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */

+#define ETH_MTLRQOMR_RSF_Pos                          (5U)

+#define ETH_MTLRQOMR_RSF_Msk                          (0x1UL << ETH_MTLRQOMR_RSF_Pos) /*!< 0x00000020 */

+#define ETH_MTLRQOMR_RSF                              ETH_MTLRQOMR_RSF_Msk     /* Receive Queue Store and Forward */

+#define ETH_MTLRQOMR_FEP_Pos                          (4U)

+#define ETH_MTLRQOMR_FEP_Msk                          (0x1UL << ETH_MTLRQOMR_FEP_Pos) /*!< 0x00000010 */

+#define ETH_MTLRQOMR_FEP                              ETH_MTLRQOMR_FEP_Msk     /* Forward Error Packets */

+#define ETH_MTLRQOMR_FUP_Pos                          (3U)

+#define ETH_MTLRQOMR_FUP_Msk                          (0x1UL << ETH_MTLRQOMR_FUP_Pos) /*!< 0x00000008 */

+#define ETH_MTLRQOMR_FUP                              ETH_MTLRQOMR_FUP_Msk     /* Forward Undersized Good Packets */

+#define ETH_MTLRQOMR_RTC_Pos                          (0U)

+#define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */

+#define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */

+#define ETH_MTLRQOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */

+#define ETH_MTLRQOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */

+#define ETH_MTLRQOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */

+#define ETH_MTLRQOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */

+

+/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */

+#define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)

+#define ETH_MTLRQMPOCR_MISCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */

+#define ETH_MTLRQMPOCR_MISCNTOVF                      ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */

+#define ETH_MTLRQMPOCR_MISPKTCNT_Pos                  (16U)

+#define ETH_MTLRQMPOCR_MISPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */

+#define ETH_MTLRQMPOCR_MISPKTCNT                      ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */

+#define ETH_MTLRQMPOCR_OVFCNTOVF_Pos                  (11U)

+#define ETH_MTLRQMPOCR_OVFCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */

+#define ETH_MTLRQMPOCR_OVFCNTOVF                      ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */

+#define ETH_MTLRQMPOCR_OVFPKTCNT_Pos                  (0U)

+#define ETH_MTLRQMPOCR_OVFPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */

+#define ETH_MTLRQMPOCR_OVFPKTCNT                      ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */

+

+/* Bit definition for Ethernet MTL Rx Queue Debug Register */

+#define ETH_MTLRQDR_PRXQ_Pos                          (16U)

+#define ETH_MTLRQDR_PRXQ_Msk                          (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos) /*!< 0x3FFF0000 */

+#define ETH_MTLRQDR_PRXQ                              ETH_MTLRQDR_PRXQ_Msk     /* Number of Packets in Receive Queue */

+#define ETH_MTLRQDR_RXQSTS_Pos                        (4U)

+#define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */

+#define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */

+#define ETH_MTLRQDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */

+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)

+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */

+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */

+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos         (5U)

+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */

+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD             ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */

+#define ETH_MTLRQDR_RXQSTS_FULL_Pos                   (4U)

+#define ETH_MTLRQDR_RXQSTS_FULL_Msk                   (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */

+#define ETH_MTLRQDR_RXQSTS_FULL                       ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */

+#define ETH_MTLRQDR_RRCSTS_Pos                        (1U)

+#define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */

+#define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */

+#define ETH_MTLRQDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */

+#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)

+#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */

+#define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */

+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos          (2U)

+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk          (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */

+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS              ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */

+#define ETH_MTLRQDR_RRCSTS_FLUSHING_Pos               (1U)

+#define ETH_MTLRQDR_RRCSTS_FLUSHING_Msk               (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */

+#define ETH_MTLRQDR_RRCSTS_FLUSHING                   ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */

+#define ETH_MTLRQDR_RWCSTS_Pos                        (0U)

+#define ETH_MTLRQDR_RWCSTS_Msk                        (0x1UL << ETH_MTLRQDR_RWCSTS_Pos) /*!< 0x00000001 */

+#define ETH_MTLRQDR_RWCSTS                            ETH_MTLRQDR_RWCSTS_Msk   /* MTL Rx Queue Write Controller Active Status */

+

+/* Bit definition for Ethernet MTL Rx Queue Control Register */

+#define ETH_MTLRQCR_RQPA_Pos                          (3U)

+#define ETH_MTLRQCR_RQPA_Msk                          (0x1UL << ETH_MTLRQCR_RQPA_Pos) /*!< 0x00000008 */

+#define ETH_MTLRQCR_RQPA                              ETH_MTLRQCR_RQPA_Msk     /* Receive Queue Packet Arbitration */

+#define ETH_MTLRQCR_RQW_Pos                           (0U)

+#define ETH_MTLRQCR_RQW_Msk                           (0x7UL << ETH_MTLRQCR_RQW_Pos) /*!< 0x00000007 */

+#define ETH_MTLRQCR_RQW                               ETH_MTLRQCR_RQW_Msk      /* Receive Queue Weight */

+

+/* Bit definition for Ethernet DMA Mode Register */

+#define ETH_DMAMR_INTM_Pos                            (16U)

+#define ETH_DMAMR_INTM_Msk                            (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */

+#define ETH_DMAMR_INTM                                ETH_DMAMR_INTM_Msk       /* This field defines the interrupt mode */

+#define ETH_DMAMR_INTM_0                              (0x0UL << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */

+#define ETH_DMAMR_INTM_1                              (0x1UL << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */

+#define ETH_DMAMR_INTM_2                              (0x2UL << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */

+#define ETH_DMAMR_PR_Pos                              (12U)

+#define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */

+#define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */

+#define ETH_DMAMR_PR_1_1                              ((uint32_t)0x00000000)   /* The priority ratio is 1:1 */

+#define ETH_DMAMR_PR_2_1                              ((uint32_t)0x00001000)   /* The priority ratio is 2:1 */

+#define ETH_DMAMR_PR_3_1                              ((uint32_t)0x00002000)   /* The priority ratio is 3:1 */

+#define ETH_DMAMR_PR_4_1                              ((uint32_t)0x00003000)   /* The priority ratio is 4:1 */

+#define ETH_DMAMR_PR_5_1                              ((uint32_t)0x00004000)   /* The priority ratio is 5:1 */

+#define ETH_DMAMR_PR_6_1                              ((uint32_t)0x00005000)   /* The priority ratio is 6:1 */

+#define ETH_DMAMR_PR_7_1                              ((uint32_t)0x00006000)   /* The priority ratio is 7:1 */

+#define ETH_DMAMR_PR_8_1                              ((uint32_t)0x00007000)   /* The priority ratio is 8:1 */

+#define ETH_DMAMR_TXPR_Pos                            (11U)

+#define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */

+#define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */

+#define ETH_DMAMR_DA_Pos                              (1U)

+#define ETH_DMAMR_DA_Msk                              (0x1UL << ETH_DMAMR_DA_Pos) /*!< 0x00000002 */

+#define ETH_DMAMR_DA                                  ETH_DMAMR_DA_Msk         /* DMA Tx or Rx Arbitration Scheme */

+#define ETH_DMAMR_SWR_Pos                             (0U)

+#define ETH_DMAMR_SWR_Msk                             (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */

+#define ETH_DMAMR_SWR                                 ETH_DMAMR_SWR_Msk        /* Software Reset */

+

+/* Bit definition for Ethernet DMA SysBus Mode Register */

+#define ETH_DMASBMR_RB_Pos                            (15U)

+#define ETH_DMASBMR_RB_Msk                            (0x1UL << ETH_DMASBMR_RB_Pos) /*!< 0x00008000 */

+#define ETH_DMASBMR_RB                                ETH_DMASBMR_RB_Msk       /* Rebuild INCRx Burst */

+#define ETH_DMASBMR_MB_Pos                            (14U)

+#define ETH_DMASBMR_MB_Msk                            (0x1UL << ETH_DMASBMR_MB_Pos) /*!< 0x00004000 */

+#define ETH_DMASBMR_MB                                ETH_DMASBMR_MB_Msk       /* Mixed Burst */

+#define ETH_DMASBMR_AAL_Pos                           (12U)

+#define ETH_DMASBMR_AAL_Msk                           (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */

+#define ETH_DMASBMR_AAL                               ETH_DMASBMR_AAL_Msk      /* Address-Aligned Beats */

+#define ETH_DMASBMR_FB_Pos                            (0U)

+#define ETH_DMASBMR_FB_Msk                            (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */

+#define ETH_DMASBMR_FB                                ETH_DMASBMR_FB_Msk       /* Fixed Burst Length */

+

+/* Bit definition for Ethernet DMA Interrupt Status Register */

+#define ETH_DMAISR_MACIS_Pos                          (17U)

+#define ETH_DMAISR_MACIS_Msk                          (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */

+#define ETH_DMAISR_MACIS                              ETH_DMAISR_MACIS_Msk     /* MAC Interrupt Status */

+#define ETH_DMAISR_MTLIS_Pos                          (16U)

+#define ETH_DMAISR_MTLIS_Msk                          (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */

+#define ETH_DMAISR_MTLIS                              ETH_DMAISR_MTLIS_Msk     /* MAC Interrupt Status */

+#define ETH_DMAISR_DMACIS_Pos                         (0U)

+#define ETH_DMAISR_DMACIS_Msk                         (0x1UL << ETH_DMAISR_DMACIS_Pos) /*!< 0x00000001 */

+#define ETH_DMAISR_DMACIS                             ETH_DMAISR_DMACIS_Msk    /* DMA Channel Interrupt Status */

+

+/* Bit definition for Ethernet DMA Debug Status Register */

+#define ETH_DMADSR_TPS_Pos                            (12U)

+#define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */

+#define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */

+#define ETH_DMADSR_TPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */

+#define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)

+#define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */

+#define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */

+#define ETH_DMADSR_TPS_WAITING_Pos                    (13U)

+#define ETH_DMADSR_TPS_WAITING_Msk                    (0x1UL << ETH_DMADSR_TPS_WAITING_Pos) /*!< 0x00002000 */

+#define ETH_DMADSR_TPS_WAITING                        ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */

+#define ETH_DMADSR_TPS_READING_Pos                    (12U)

+#define ETH_DMADSR_TPS_READING_Msk                    (0x3UL << ETH_DMADSR_TPS_READING_Pos) /*!< 0x00003000 */

+#define ETH_DMADSR_TPS_READING                        ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */

+#define ETH_DMADSR_TPS_TIMESTAMP_WR_Pos               (14U)

+#define ETH_DMADSR_TPS_TIMESTAMP_WR_Msk               (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos) /*!< 0x00004000 */

+#define ETH_DMADSR_TPS_TIMESTAMP_WR                   ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */

+#define ETH_DMADSR_TPS_SUSPENDED_Pos                  (13U)

+#define ETH_DMADSR_TPS_SUSPENDED_Msk                  (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos) /*!< 0x00006000 */

+#define ETH_DMADSR_TPS_SUSPENDED                      ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */

+#define ETH_DMADSR_TPS_CLOSING_Pos                    (12U)

+#define ETH_DMADSR_TPS_CLOSING_Msk                    (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos) /*!< 0x00007000 */

+#define ETH_DMADSR_TPS_CLOSING                        ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */

+#define ETH_DMADSR_RPS_Pos                            (8U)

+#define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */

+#define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */

+#define ETH_DMADSR_RPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */

+#define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)

+#define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */

+#define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */

+#define ETH_DMADSR_RPS_WAITING_Pos                    (12U)

+#define ETH_DMADSR_RPS_WAITING_Msk                    (0x3UL << ETH_DMADSR_RPS_WAITING_Pos) /*!< 0x00003000 */

+#define ETH_DMADSR_RPS_WAITING                        ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */

+#define ETH_DMADSR_RPS_SUSPENDED_Pos                  (14U)

+#define ETH_DMADSR_RPS_SUSPENDED_Msk                  (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos) /*!< 0x00004000 */

+#define ETH_DMADSR_RPS_SUSPENDED                      ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */

+#define ETH_DMADSR_RPS_CLOSING_Pos                    (12U)

+#define ETH_DMADSR_RPS_CLOSING_Msk                    (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos) /*!< 0x00005000 */

+#define ETH_DMADSR_RPS_CLOSING                        ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */

+#define ETH_DMADSR_RPS_TIMESTAMP_WR_Pos               (13U)

+#define ETH_DMADSR_RPS_TIMESTAMP_WR_Msk               (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos) /*!< 0x00006000 */

+#define ETH_DMADSR_RPS_TIMESTAMP_WR                   ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */

+#define ETH_DMADSR_RPS_TRANSFERRING_Pos               (12U)

+#define ETH_DMADSR_RPS_TRANSFERRING_Msk               (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos) /*!< 0x00007000 */

+#define ETH_DMADSR_RPS_TRANSFERRING                   ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */

+

+/* Bit definition for Ethernet DMA Channel Control Register */

+#define ETH_DMACCR_DSL_Pos                            (18U)

+#define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */

+#define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */

+#define ETH_DMACCR_DSL_0BIT                           ((uint32_t)0x00000000)

+#define ETH_DMACCR_DSL_32BIT                          ((uint32_t)0x00040000)

+#define ETH_DMACCR_DSL_64BIT                          ((uint32_t)0x00080000)

+#define ETH_DMACCR_DSL_128BIT                         ((uint32_t)0x00100000)

+#define ETH_DMACCR_8PBL                               ((uint32_t)0x00010000)   /* 8xPBL mode */

+#define ETH_DMACCR_MSS_Pos                            (0U)

+#define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */

+#define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */

+

+/* Bit definition for Ethernet DMA Channel Tx Control Register */

+#define ETH_DMACTCR_TPBL_Pos                          (16U)

+#define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */

+#define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */

+#define ETH_DMACTCR_TPBL_1PBL                         ((uint32_t)0x00010000)   /* Transmit Programmable Burst Length 1 */

+#define ETH_DMACTCR_TPBL_2PBL                         ((uint32_t)0x00020000)   /* Transmit Programmable Burst Length 2 */

+#define ETH_DMACTCR_TPBL_4PBL                         ((uint32_t)0x00040000)   /* Transmit Programmable Burst Length 4 */

+#define ETH_DMACTCR_TPBL_8PBL                         ((uint32_t)0x00080000)   /* Transmit Programmable Burst Length 8 */

+#define ETH_DMACTCR_TPBL_16PBL                        ((uint32_t)0x00100000)   /* Transmit Programmable Burst Length 16 */

+#define ETH_DMACTCR_TPBL_32PBL                        ((uint32_t)0x00200000)   /* Transmit Programmable Burst Length 32 */

+#define ETH_DMACTCR_TSE_Pos                           (12U)

+#define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */

+#define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */

+#define ETH_DMACTCR_OSP_Pos                           (4U)

+#define ETH_DMACTCR_OSP_Msk                           (0x1UL << ETH_DMACTCR_OSP_Pos) /*!< 0x00000010 */

+#define ETH_DMACTCR_OSP                               ETH_DMACTCR_OSP_Msk      /* Operate on Second Packet */

+#define ETH_DMACTCR_ST_Pos                            (0U)

+#define ETH_DMACTCR_ST_Msk                            (0x1UL << ETH_DMACTCR_ST_Pos) /*!< 0x00000001 */

+#define ETH_DMACTCR_ST                                ETH_DMACTCR_ST_Msk       /* Start or Stop Transmission Command */

+

+/* Bit definition for Ethernet DMA Channel Rx Control Register */

+#define ETH_DMACRCR_RPF_Pos                           (31U)

+#define ETH_DMACRCR_RPF_Msk                           (0x1UL << ETH_DMACRCR_RPF_Pos) /*!< 0x80000000 */

+#define ETH_DMACRCR_RPF                               ETH_DMACRCR_RPF_Msk      /* Rx Packet Flush */

+#define ETH_DMACRCR_RPBL_Pos                          (16U)

+#define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */

+#define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */

+#define ETH_DMACRCR_RPBL_1PBL                         ((uint32_t)0x00010000)   /* Receive Programmable Burst Length 1 */

+#define ETH_DMACRCR_RPBL_2PBL                         ((uint32_t)0x00020000)   /* Receive Programmable Burst Length 2 */

+#define ETH_DMACRCR_RPBL_4PBL                         ((uint32_t)0x00040000)   /* Receive Programmable Burst Length 4 */

+#define ETH_DMACRCR_RPBL_8PBL                         ((uint32_t)0x00080000)   /* Receive Programmable Burst Length 8 */

+#define ETH_DMACRCR_RPBL_16PBL                        ((uint32_t)0x00100000)   /* Receive Programmable Burst Length 16 */

+#define ETH_DMACRCR_RPBL_32PBL                        ((uint32_t)0x00200000)   /* Receive Programmable Burst Length 32 */

+#define ETH_DMACRCR_RBSZ_Pos                          (1U)

+#define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */

+#define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */

+#define ETH_DMACRCR_SR_Pos                            (0U)

+#define ETH_DMACRCR_SR_Msk                            (0x1UL << ETH_DMACRCR_SR_Pos) /*!< 0x00000001 */

+#define ETH_DMACRCR_SR                                ETH_DMACRCR_SR_Msk       /* Start or Stop Receive */

+

+/* Bit definition for Ethernet DMA CH Tx Desc List Address Register */

+#define ETH_DMACTDLAR_TDESLA_Pos                      (2U)

+#define ETH_DMACTDLAR_TDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACTDLAR_TDESLA                          ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */

+

+/* Bit definition for Ethernet DMA CH Rx Desc List Address Register */

+#define ETH_DMACRDLAR_RDESLA_Pos                      (2U)

+#define ETH_DMACRDLAR_RDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACRDLAR_RDESLA                          ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */

+

+/* Bit definition for Ethernet DMA CH Tx Desc Tail Pointer Register */

+#define ETH_DMACTDTPR_TDT_Pos                         (2U)

+#define ETH_DMACTDTPR_TDT_Msk                         (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACTDTPR_TDT                             ETH_DMACTDTPR_TDT_Msk    /* Transmit Descriptor Tail Pointer */

+

+/* Bit definition for Ethernet DMA CH Rx Desc Tail Pointer Register */

+#define ETH_DMACRDTPR_RDT_Pos                         (2U)

+#define ETH_DMACRDTPR_RDT_Msk                         (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACRDTPR_RDT                             ETH_DMACRDTPR_RDT_Msk    /* Receive Descriptor Tail Pointer */

+

+/* Bit definition for Ethernet DMA CH Tx Desc Ring Length Register */

+#define ETH_DMACTDRLR_TDRL_Pos                        (0U)

+#define ETH_DMACTDRLR_TDRL_Msk                        (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos) /*!< 0x000003FF */

+#define ETH_DMACTDRLR_TDRL                            ETH_DMACTDRLR_TDRL_Msk   /* Transmit Descriptor Ring Length */

+

+/* Bit definition for Ethernet DMA CH Rx Desc Ring Length Register */

+#define ETH_DMACRDRLR_RDRL_Pos                        (0U)

+#define ETH_DMACRDRLR_RDRL_Msk                        (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos) /*!< 0x000003FF */

+#define ETH_DMACRDRLR_RDRL                            ETH_DMACRDRLR_RDRL_Msk   /* Receive Descriptor Ring Length */

+

+/* Bit definition for Ethernet DMA Channel Interrupt Enable Register */

+#define ETH_DMACIER_NIE_Pos                           (15U)

+#define ETH_DMACIER_NIE_Msk                           (0x1UL << ETH_DMACIER_NIE_Pos) /*!< 0x00008000 */

+#define ETH_DMACIER_NIE                               ETH_DMACIER_NIE_Msk      /* Normal Interrupt Summary Enable */

+#define ETH_DMACIER_AIE_Pos                           (14U)

+#define ETH_DMACIER_AIE_Msk                           (0x1UL << ETH_DMACIER_AIE_Pos) /*!< 0x00004000 */

+#define ETH_DMACIER_AIE                               ETH_DMACIER_AIE_Msk      /* Abnormal Interrupt Summary Enable */

+#define ETH_DMACIER_CDEE_Pos                          (13U)

+#define ETH_DMACIER_CDEE_Msk                          (0x1UL << ETH_DMACIER_CDEE_Pos) /*!< 0x00002000 */

+#define ETH_DMACIER_CDEE                              ETH_DMACIER_CDEE_Msk     /* Context Descriptor Error Enable */

+#define ETH_DMACIER_FBEE_Pos                          (12U)

+#define ETH_DMACIER_FBEE_Msk                          (0x1UL << ETH_DMACIER_FBEE_Pos) /*!< 0x00001000 */

+#define ETH_DMACIER_FBEE                              ETH_DMACIER_FBEE_Msk     /* Fatal Bus Error Enable */

+#define ETH_DMACIER_ERIE_Pos                          (11U)

+#define ETH_DMACIER_ERIE_Msk                          (0x1UL << ETH_DMACIER_ERIE_Pos) /*!< 0x00000800 */

+#define ETH_DMACIER_ERIE                              ETH_DMACIER_ERIE_Msk     /* Early Receive Interrupt Enable */

+#define ETH_DMACIER_ETIE_Pos                          (10U)

+#define ETH_DMACIER_ETIE_Msk                          (0x1UL << ETH_DMACIER_ETIE_Pos) /*!< 0x00000400 */

+#define ETH_DMACIER_ETIE                              ETH_DMACIER_ETIE_Msk     /* Early Transmit Interrupt Enable */

+#define ETH_DMACIER_RWTE_Pos                          (9U)

+#define ETH_DMACIER_RWTE_Msk                          (0x1UL << ETH_DMACIER_RWTE_Pos) /*!< 0x00000200 */

+#define ETH_DMACIER_RWTE                              ETH_DMACIER_RWTE_Msk     /* Receive Watchdog Timeout Enable */

+#define ETH_DMACIER_RSE_Pos                           (8U)

+#define ETH_DMACIER_RSE_Msk                           (0x1UL << ETH_DMACIER_RSE_Pos) /*!< 0x00000100 */

+#define ETH_DMACIER_RSE                               ETH_DMACIER_RSE_Msk      /* Receive Stopped Enable */

+#define ETH_DMACIER_RBUE_Pos                          (7U)

+#define ETH_DMACIER_RBUE_Msk                          (0x1UL << ETH_DMACIER_RBUE_Pos) /*!< 0x00000080 */

+#define ETH_DMACIER_RBUE                              ETH_DMACIER_RBUE_Msk     /* Receive Buffer Unavailable Enable */

+#define ETH_DMACIER_RIE_Pos                           (6U)

+#define ETH_DMACIER_RIE_Msk                           (0x1UL << ETH_DMACIER_RIE_Pos) /*!< 0x00000040 */

+#define ETH_DMACIER_RIE                               ETH_DMACIER_RIE_Msk      /* Receive Interrupt Enable */

+#define ETH_DMACIER_TBUE_Pos                          (2U)

+#define ETH_DMACIER_TBUE_Msk                          (0x1UL << ETH_DMACIER_TBUE_Pos) /*!< 0x00000004 */

+#define ETH_DMACIER_TBUE                              ETH_DMACIER_TBUE_Msk     /* Transmit Buffer Unavailable Enable */

+#define ETH_DMACIER_TXSE_Pos                          (1U)

+#define ETH_DMACIER_TXSE_Msk                          (0x1UL << ETH_DMACIER_TXSE_Pos) /*!< 0x00000002 */

+#define ETH_DMACIER_TXSE                              ETH_DMACIER_TXSE_Msk     /* Transmit Stopped Enable */

+#define ETH_DMACIER_TIE_Pos                           (0U)

+#define ETH_DMACIER_TIE_Msk                           (0x1UL << ETH_DMACIER_TIE_Pos) /*!< 0x00000001 */

+#define ETH_DMACIER_TIE                               ETH_DMACIER_TIE_Msk      /* Transmit Interrupt Enable */

+

+/* Bit definition for Ethernet DMA Channel Rx Interrupt Watchdog Timer Register */

+#define ETH_DMACRIWTR_RWT_Pos                         (0U)

+#define ETH_DMACRIWTR_RWT_Msk                         (0xFFUL << ETH_DMACRIWTR_RWT_Pos) /*!< 0x000000FF */

+#define ETH_DMACRIWTR_RWT                             ETH_DMACRIWTR_RWT_Msk    /* Receive Interrupt Watchdog Timer Count */

+

+/* Bit definition for Ethernet DMA Channel Current App Tx Desc Register */

+#define ETH_DMACCATDR_CURTDESAPTR_Pos                 (0U)

+#define ETH_DMACCATDR_CURTDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCATDR_CURTDESAPTR                     ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Current App Rx Desc Register */

+#define ETH_DMACCARDR_CURRDESAPTR_Pos                 (0U)

+#define ETH_DMACCARDR_CURRDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCARDR_CURRDESAPTR                     ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Current App Tx Buffer Register */

+#define ETH_DMACCATBR_CURTBUFAPTR_Pos                 (0U)

+#define ETH_DMACCATBR_CURTBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCATBR_CURTBUFAPTR                     ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Current App Rx Buffer Register */

+#define ETH_DMACCARBR_CURRBUFAPTR_Pos                 (0U)

+#define ETH_DMACCARBR_CURRBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCARBR_CURRBUFAPTR                     ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Status Register */

+#define ETH_DMACSR_REB_Pos                            (19U)

+#define ETH_DMACSR_REB_Msk                            (0x7UL << ETH_DMACSR_REB_Pos) /*!< 0x00380000 */

+#define ETH_DMACSR_REB                                ETH_DMACSR_REB_Msk       /* Rx DMA Error Bits */

+#define ETH_DMACSR_TEB_Pos                            (16U)

+#define ETH_DMACSR_TEB_Msk                            (0x7UL << ETH_DMACSR_TEB_Pos) /*!< 0x00070000 */

+#define ETH_DMACSR_TEB                                ETH_DMACSR_TEB_Msk       /* Tx DMA Error Bits */

+#define ETH_DMACSR_NIS_Pos                            (15U)

+#define ETH_DMACSR_NIS_Msk                            (0x1UL << ETH_DMACSR_NIS_Pos) /*!< 0x00008000 */

+#define ETH_DMACSR_NIS                                ETH_DMACSR_NIS_Msk       /* Normal Interrupt Summary */

+#define ETH_DMACSR_AIS_Pos                            (14U)

+#define ETH_DMACSR_AIS_Msk                            (0x1UL << ETH_DMACSR_AIS_Pos) /*!< 0x00004000 */

+#define ETH_DMACSR_AIS                                ETH_DMACSR_AIS_Msk       /* Abnormal Interrupt Summary */

+#define ETH_DMACSR_CDE_Pos                            (13U)

+#define ETH_DMACSR_CDE_Msk                            (0x1UL << ETH_DMACSR_CDE_Pos) /*!< 0x00002000 */

+#define ETH_DMACSR_CDE                                ETH_DMACSR_CDE_Msk       /* Context Descriptor Error */

+#define ETH_DMACSR_FBE_Pos                            (12U)

+#define ETH_DMACSR_FBE_Msk                            (0x1UL << ETH_DMACSR_FBE_Pos) /*!< 0x00001000 */

+#define ETH_DMACSR_FBE                                ETH_DMACSR_FBE_Msk       /* Fatal Bus Error */

+#define ETH_DMACSR_ERI_Pos                            (11U)

+#define ETH_DMACSR_ERI_Msk                            (0x1UL << ETH_DMACSR_ERI_Pos) /*!< 0x00000800 */

+#define ETH_DMACSR_ERI                                ETH_DMACSR_ERI_Msk       /* Early Receive Interrupt */

+#define ETH_DMACSR_ETI_Pos                            (10U)

+#define ETH_DMACSR_ETI_Msk                            (0x1UL << ETH_DMACSR_ETI_Pos) /*!< 0x00000400 */

+#define ETH_DMACSR_ETI                                ETH_DMACSR_ETI_Msk       /* Early Transmit Interrupt */

+#define ETH_DMACSR_RWT_Pos                            (9U)

+#define ETH_DMACSR_RWT_Msk                            (0x1UL << ETH_DMACSR_RWT_Pos) /*!< 0x00000200 */

+#define ETH_DMACSR_RWT                                ETH_DMACSR_RWT_Msk       /* Receive Watchdog Timeout */

+#define ETH_DMACSR_RPS_Pos                            (8U)

+#define ETH_DMACSR_RPS_Msk                            (0x1UL << ETH_DMACSR_RPS_Pos) /*!< 0x00000100 */

+#define ETH_DMACSR_RPS                                ETH_DMACSR_RPS_Msk       /* Receive Process Stopped */

+#define ETH_DMACSR_RBU_Pos                            (7U)

+#define ETH_DMACSR_RBU_Msk                            (0x1UL << ETH_DMACSR_RBU_Pos) /*!< 0x00000080 */

+#define ETH_DMACSR_RBU                                ETH_DMACSR_RBU_Msk       /* Receive Buffer Unavailable */

+#define ETH_DMACSR_RI_Pos                             (6U)

+#define ETH_DMACSR_RI_Msk                             (0x1UL << ETH_DMACSR_RI_Pos) /*!< 0x00000040 */

+#define ETH_DMACSR_RI                                 ETH_DMACSR_RI_Msk        /* Receive Interrupt */

+#define ETH_DMACSR_TBU_Pos                            (2U)

+#define ETH_DMACSR_TBU_Msk                            (0x1UL << ETH_DMACSR_TBU_Pos) /*!< 0x00000004 */

+#define ETH_DMACSR_TBU                                ETH_DMACSR_TBU_Msk       /* Transmit Buffer Unavailable */

+#define ETH_DMACSR_TPS_Pos                            (1U)

+#define ETH_DMACSR_TPS_Msk                            (0x1UL << ETH_DMACSR_TPS_Pos) /*!< 0x00000002 */

+#define ETH_DMACSR_TPS                                ETH_DMACSR_TPS_Msk       /* Transmit Process Stopped */

+#define ETH_DMACSR_TI_Pos                             (0U)

+#define ETH_DMACSR_TI_Msk                             (0x1UL << ETH_DMACSR_TI_Pos) /*!< 0x00000001 */

+#define ETH_DMACSR_TI                                 ETH_DMACSR_TI_Msk        /* Transmit Interrupt */

+

+/* Bit definition for Ethernet DMA Channel missed frame count register */

+#define ETH_DMACMFCR_MFCO_Pos                         (15U)

+#define ETH_DMACMFCR_MFCO_Msk                         (0x1UL << ETH_DMACMFCR_MFCO_Pos) /*!< 0x00008000 */

+#define ETH_DMACMFCR_MFCO                             ETH_DMACMFCR_MFCO_Msk    /* Overflow status of the MFC Counter */

+#define ETH_DMACMFCR_MFC_Pos                          (0U)

+#define ETH_DMACMFCR_MFC_Msk                          (0x7FFUL << ETH_DMACMFCR_MFC_Pos) /*!< 0x000007FF */

+#define ETH_DMACMFCR_MFC                              ETH_DMACMFCR_MFC_Msk     /* The number of packet counters dropped by the DMA */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             DMA Controller                                 */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DMA_SxCR register  *****************/

+#define DMA_SxCR_MBURST_Pos      (23U)

+#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                /*!< 0x01800000 */

+#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk                           /*!< Memory burst transfer configuration */

+#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */

+#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */

+#define DMA_SxCR_PBURST_Pos      (21U)

+#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                /*!< 0x00600000 */

+#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk                           /*!< Peripheral burst transfer configuration */

+#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */

+#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */

+#define DMA_SxCR_TRBUFF_Pos      (20U)

+#define DMA_SxCR_TRBUFF_Msk      (0x1UL << DMA_SxCR_TRBUFF_Pos)                 /*!< 0x00100000 */

+#define DMA_SxCR_TRBUFF          DMA_SxCR_TRBUFF_Msk                            /*!< bufferable transfers enabled/disable */

+#define DMA_SxCR_CT_Pos          (19U)

+#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                    /*!< 0x00080000 */

+#define DMA_SxCR_CT              DMA_SxCR_CT_Msk                               /*!< Current target (only in double buffer mode) */

+#define DMA_SxCR_DBM_Pos         (18U)

+#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                   /*!< 0x00040000 */

+#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk                              /*!< Double buffer mode */

+#define DMA_SxCR_PL_Pos          (16U)

+#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                    /*!< 0x00030000 */

+#define DMA_SxCR_PL              DMA_SxCR_PL_Msk                               /*!< Priority level */

+#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */

+#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */

+#define DMA_SxCR_PINCOS_Pos      (15U)

+#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                /*!< 0x00008000 */

+#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk                           /*!< Peripheral increment offset size */

+#define DMA_SxCR_MSIZE_Pos       (13U)

+#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                 /*!< 0x00006000 */

+#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk                            /*!< Memory data size */

+#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */

+#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */

+#define DMA_SxCR_PSIZE_Pos       (11U)

+#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                 /*!< 0x00001800 */

+#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk                            /*< Peripheral data size */

+#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */

+#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */

+#define DMA_SxCR_MINC_Pos        (10U)

+#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                  /*!< 0x00000400 */

+#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk                             /*!< Memory increment mode */

+#define DMA_SxCR_PINC_Pos        (9U)

+#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                  /*!< 0x00000200 */

+#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk                             /*!< Peripheral increment mode */

+#define DMA_SxCR_CIRC_Pos        (8U)

+#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                  /*!< 0x00000100 */

+#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk                             /*!< Circular mode */

+#define DMA_SxCR_DIR_Pos         (6U)

+#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                   /*!< 0x000000C0 */

+#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk                              /*!< Data transfer direction */

+#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */

+#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */

+#define DMA_SxCR_PFCTRL_Pos      (5U)

+#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                /*!< 0x00000020 */

+#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk                           /*!< Peripheral flow controller */

+#define DMA_SxCR_TCIE_Pos        (4U)

+#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                  /*!< 0x00000010 */

+#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk                             /*!< Transfer complete interrupt enable */

+#define DMA_SxCR_HTIE_Pos        (3U)

+#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                  /*!< 0x00000008 */

+#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk                             /*!< Half transfer interrupt enable */

+#define DMA_SxCR_TEIE_Pos        (2U)

+#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                  /*!< 0x00000004 */

+#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk                             /*!< Transfer error interrupt enable */

+#define DMA_SxCR_DMEIE_Pos       (1U)

+#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                 /*!< 0x00000002 */

+#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk                            /*!< Direct mode error interrupt enable */

+#define DMA_SxCR_EN_Pos          (0U)

+#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                    /*!< 0x00000001 */

+#define DMA_SxCR_EN              DMA_SxCR_EN_Msk                               /*!< Stream enable / flag stream ready when read low */

+

+/********************  Bits definition for DMA_SxCNDTR register  **************/

+#define DMA_SxNDT_Pos            (0U)

+#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                   /*!< 0x0000FFFF */

+#define DMA_SxNDT                DMA_SxNDT_Msk                                 /*!< Number of data items to transfer */

+#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */

+#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */

+#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */

+#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */

+#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */

+#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */

+#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */

+#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */

+#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */

+#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */

+#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */

+#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */

+#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */

+#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */

+#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */

+#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */

+

+/********************  Bits definition for DMA_SxFCR register  ****************/

+#define DMA_SxFCR_FEIE_Pos       (7U)

+#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                 /*!< 0x00000080 */

+#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk                            /*!< FIFO error interrupt enable */

+#define DMA_SxFCR_FS_Pos         (3U)

+#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                   /*!< 0x00000038 */

+#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk                              /*!< FIFO status */

+#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */

+#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */

+#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */

+#define DMA_SxFCR_DMDIS_Pos      (2U)

+#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                /*!< 0x00000004 */

+#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk                           /*!< Direct mode disable */

+#define DMA_SxFCR_FTH_Pos        (0U)

+#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                  /*!< 0x00000003 */

+#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk                             /*!< FIFO threshold selection */

+#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */

+#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */

+

+/********************  Bits definition for DMA_LISR register  *****************/

+#define DMA_LISR_TCIF3_Pos       (27U)

+#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                 /*!< 0x08000000 */

+#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk                            /*!<  Stream 3 transfer complete interrupt flag */

+#define DMA_LISR_HTIF3_Pos       (26U)

+#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                 /*!< 0x04000000 */

+#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk                            /*!<  Stream 3 half transfer interrupt flag */

+#define DMA_LISR_TEIF3_Pos       (25U)

+#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                 /*!< 0x02000000 */

+#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk                            /*!<  Stream 3 transfer error interrupt flag */

+#define DMA_LISR_DMEIF3_Pos      (24U)

+#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                /*!< 0x01000000 */

+#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk                           /*!<  Stream 3 direct mode error interrupt flag */

+#define DMA_LISR_FEIF3_Pos       (22U)

+#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                 /*!< 0x00400000 */

+#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk                            /*!<  Stream 3 FIFO error interrupt flag */

+#define DMA_LISR_TCIF2_Pos       (21U)

+#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                 /*!< 0x00200000 */

+#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk                            /*!<  Stream 2 transfer complete interrupt flag */

+#define DMA_LISR_HTIF2_Pos       (20U)

+#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                 /*!< 0x00100000 */

+#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk                            /*!<  Stream 2 half transfer interrupt flag */

+#define DMA_LISR_TEIF2_Pos       (19U)

+#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                 /*!< 0x00080000 */

+#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk                            /*!<  Stream 2 transfer error interrupt flag */

+#define DMA_LISR_DMEIF2_Pos      (18U)

+#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                /*!< 0x00040000 */

+#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk                           /*!<  Stream 2 direct mode error interrupt flag */

+#define DMA_LISR_FEIF2_Pos       (16U)

+#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                 /*!< 0x00010000 */

+#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk                            /*!<  Stream 2 FIFO error interrupt flag */

+#define DMA_LISR_TCIF1_Pos       (11U)

+#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                 /*!< 0x00000800 */

+#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk                            /*!<  Stream 1 transfer complete interrupt flag */

+#define DMA_LISR_HTIF1_Pos       (10U)

+#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                 /*!< 0x00000400 */

+#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk                            /*!<  Stream 1 half transfer interrupt flag */

+#define DMA_LISR_TEIF1_Pos       (9U)

+#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                 /*!< 0x00000200 */

+#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk                            /*!<  Stream 1 transfer error interrupt flag */

+#define DMA_LISR_DMEIF1_Pos      (8U)

+#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                /*!< 0x00000100 */

+#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk                           /*!<  Stream 1 direct mode error interrupt flag */

+#define DMA_LISR_FEIF1_Pos       (6U)

+#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                 /*!< 0x00000040 */

+#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk                            /*!<  Stream 1 FIFO error interrupt flag */

+#define DMA_LISR_TCIF0_Pos       (5U)

+#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                 /*!< 0x00000020 */

+#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk                            /*!<  Stream 0 transfer complete interrupt flag */

+#define DMA_LISR_HTIF0_Pos       (4U)

+#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                 /*!< 0x00000010 */

+#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk                            /*!<  Stream 0 half transfer interrupt flag */

+#define DMA_LISR_TEIF0_Pos       (3U)

+#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                 /*!< 0x00000008 */

+#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk                            /*!<  Stream 0 transfer error interrupt flag */

+#define DMA_LISR_DMEIF0_Pos      (2U)

+#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                /*!< 0x00000004 */

+#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk                           /*!<  Stream 0 direct mode error interrupt flag */

+#define DMA_LISR_FEIF0_Pos       (0U)

+#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                 /*!< 0x00000001 */

+#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk                            /*!<  Stream 0 FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_HISR register  *****************/

+#define DMA_HISR_TCIF7_Pos       (27U)

+#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                 /*!< 0x08000000 */

+#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk                            /*!<  Stream 7 transfer complete interrupt flag */

+#define DMA_HISR_HTIF7_Pos       (26U)

+#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                 /*!< 0x04000000 */

+#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk                            /*!<  Stream 7 half transfer interrupt flag */

+#define DMA_HISR_TEIF7_Pos       (25U)

+#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                 /*!< 0x02000000 */

+#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk                            /*!<  Stream 7 transfer error interrupt flag */

+#define DMA_HISR_DMEIF7_Pos      (24U)

+#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                /*!< 0x01000000 */

+#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk                           /*!<  Stream 7 direct mode error interrupt flag */

+#define DMA_HISR_FEIF7_Pos       (22U)

+#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                 /*!< 0x00400000 */

+#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk                            /*!<  Stream 7 FIFO error interrupt flag */

+#define DMA_HISR_TCIF6_Pos       (21U)

+#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                 /*!< 0x00200000 */

+#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk                            /*!<  Stream 6 transfer complete interrupt flag */

+#define DMA_HISR_HTIF6_Pos       (20U)

+#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                 /*!< 0x00100000 */

+#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk                            /*!<  Stream 6 half transfer interrupt flag */

+#define DMA_HISR_TEIF6_Pos       (19U)

+#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                 /*!< 0x00080000 */

+#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk                            /*!<  Stream 6 transfer error interrupt flag */

+#define DMA_HISR_DMEIF6_Pos      (18U)

+#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                /*!< 0x00040000 */

+#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk                           /*!<  Stream 6 direct mode error interrupt flag */

+#define DMA_HISR_FEIF6_Pos       (16U)

+#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                 /*!< 0x00010000 */

+#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk                            /*!<  Stream 6 FIFO error interrupt flag */

+#define DMA_HISR_TCIF5_Pos       (11U)

+#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                 /*!< 0x00000800 */

+#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk                            /*!<  Stream 5 transfer complete interrupt flag */

+#define DMA_HISR_HTIF5_Pos       (10U)

+#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                 /*!< 0x00000400 */

+#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk                            /*!<  Stream 5 half transfer interrupt flag */

+#define DMA_HISR_TEIF5_Pos       (9U)

+#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                 /*!< 0x00000200 */

+#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk                            /*!<  Stream 5 transfer error interrupt flag */

+#define DMA_HISR_DMEIF5_Pos      (8U)

+#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                /*!< 0x00000100 */

+#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk                           /*!<  Stream 5 direct mode error interrupt flag */

+#define DMA_HISR_FEIF5_Pos       (6U)

+#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                 /*!< 0x00000040 */

+#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk                            /*!<  Stream 5 FIFO error interrupt flag */

+#define DMA_HISR_TCIF4_Pos       (5U)

+#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                 /*!< 0x00000020 */

+#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk                            /*!<  Stream 4 transfer complete interrupt flag */

+#define DMA_HISR_HTIF4_Pos       (4U)

+#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                 /*!< 0x00000010 */

+#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk                            /*!<  Stream 4 half transfer interrupt flag */

+#define DMA_HISR_TEIF4_Pos       (3U)

+#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                 /*!< 0x00000008 */

+#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk                            /*!<  Stream 4 transfer error interrupt flag */

+#define DMA_HISR_DMEIF4_Pos      (2U)

+#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                /*!< 0x00000004 */

+#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk                           /*!<  Stream 4 direct mode error interrupt flag */

+#define DMA_HISR_FEIF4_Pos       (0U)

+#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                 /*!< 0x00000001 */

+#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk                            /*!<  Stream 4 FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_LIFCR register  ****************/

+#define DMA_LIFCR_CTCIF3_Pos     (27U)

+#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)               /*!< 0x08000000 */

+#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk                          /*!<  Stream 3 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF3_Pos     (26U)

+#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)               /*!< 0x04000000 */

+#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk                          /*!<  Stream 3 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF3_Pos     (25U)

+#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)               /*!< 0x02000000 */

+#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk                          /*!<  Stream 3 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF3_Pos    (24U)

+#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)              /*!< 0x01000000 */

+#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk                         /*!<  Stream 3 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF3_Pos     (22U)

+#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)               /*!< 0x00400000 */

+#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk                          /*!<  Stream 3 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF2_Pos     (21U)

+#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)               /*!< 0x00200000 */

+#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk                          /*!<  Stream 2 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF2_Pos     (20U)

+#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)               /*!< 0x00100000 */

+#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk                          /*!<  Stream 2 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF2_Pos     (19U)

+#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)               /*!< 0x00080000 */

+#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk                          /*!<  Stream 2 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF2_Pos    (18U)

+#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)              /*!< 0x00040000 */

+#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk                         /*!<  Stream 2 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF2_Pos     (16U)

+#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)               /*!< 0x00010000 */

+#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk                          /*!<  Stream 2 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF1_Pos     (11U)

+#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)               /*!< 0x00000800 */

+#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk                          /*!<  Stream 1 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF1_Pos     (10U)

+#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)               /*!< 0x00000400 */

+#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk                          /*!<  Stream 1 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF1_Pos     (9U)

+#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)               /*!< 0x00000200 */

+#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk                          /*!<  Stream 1 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF1_Pos    (8U)

+#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)              /*!< 0x00000100 */

+#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk                         /*!<  Stream 1 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF1_Pos     (6U)

+#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)               /*!< 0x00000040 */

+#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk                          /*!<  Stream 1 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF0_Pos     (5U)

+#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)               /*!< 0x00000020 */

+#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk                          /*!<  Stream 0 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF0_Pos     (4U)

+#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)               /*!< 0x00000010 */

+#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk                          /*!<  Stream 0 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF0_Pos     (3U)

+#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)               /*!< 0x00000008 */

+#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk                          /*!<  Stream 0 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF0_Pos    (2U)

+#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)              /*!< 0x00000004 */

+#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk                         /*!<  Stream 0 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF0_Pos     (0U)

+#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)               /*!< 0x00000001 */

+#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk                          /*!<  Stream 0 clear FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_HIFCR  register  ****************/

+#define DMA_HIFCR_CTCIF7_Pos     (27U)

+#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)               /*!< 0x08000000 */

+#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk                          /*!<  Stream 7 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF7_Pos     (26U)

+#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)               /*!< 0x04000000 */

+#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk                          /*!<  Stream 7 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF7_Pos     (25U)

+#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)               /*!< 0x02000000 */

+#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk                          /*!<  Stream 7 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF7_Pos    (24U)

+#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)              /*!< 0x01000000 */

+#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk                         /*!<  Stream 7 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF7_Pos     (22U)

+#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)               /*!< 0x00400000 */

+#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk                          /*!<  Stream 7 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF6_Pos     (21U)

+#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)               /*!< 0x00200000 */

+#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk                          /*!<  Stream 6 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF6_Pos     (20U)

+#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)               /*!< 0x00100000 */

+#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk                          /*!<  Stream 6 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF6_Pos     (19U)

+#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)               /*!< 0x00080000 */

+#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk                          /*!<  Stream 6 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF6_Pos    (18U)

+#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)              /*!< 0x00040000 */

+#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk                         /*!<  Stream 6 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF6_Pos     (16U)

+#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)               /*!< 0x00010000 */

+#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk                          /*!<  Stream 6 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF5_Pos     (11U)

+#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)               /*!< 0x00000800 */

+#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk                          /*!<  Stream 5 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF5_Pos     (10U)

+#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)               /*!< 0x00000400 */

+#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk                          /*!<  Stream 5 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF5_Pos     (9U)

+#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)               /*!< 0x00000200 */

+#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk                          /*!<  Stream 5 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF5_Pos    (8U)

+#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)              /*!< 0x00000100 */

+#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk                         /*!<  Stream 5 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF5_Pos     (6U)

+#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)               /*!< 0x00000040 */

+#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk                          /*!<  Stream 5 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF4_Pos     (5U)

+#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)               /*!< 0x00000020 */

+#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk                          /*!<  Stream 4 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF4_Pos     (4U)

+#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)               /*!< 0x00000010 */

+#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk                          /*!<  Stream 4 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF4_Pos     (3U)

+#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)               /*!< 0x00000008 */

+#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk                          /*!<  Stream 4 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF4_Pos    (2U)

+#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)              /*!< 0x00000004 */

+#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk                         /*!<  Stream 4 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF4_Pos     (0U)

+#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)               /*!< 0x00000001 */

+#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk                          /*!<  Stream 4 clear FIFO error interrupt flag */

+

+/******************  Bit definition for DMA_SxPAR register  ********************/

+#define DMA_SxPAR_PA_Pos         (0U)

+#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)            /*!< 0xFFFFFFFF */

+#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */

+

+/******************  Bit definition for DMA_SxM0AR register  ********************/

+#define DMA_SxM0AR_M0A_Pos       (0U)

+#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)          /*!< 0xFFFFFFFF */

+#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory 0 Address */

+

+/******************  Bit definition for DMA_SxM1AR register  ********************/

+#define DMA_SxM1AR_M1A_Pos       (0U)

+#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)          /*!< 0xFFFFFFFF */

+#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory 1 Address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             DMAMUX Controller                              */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DMAMUX_CxCR register  **************/

+#define DMAMUX_CxCR_DMAREQ_ID_Pos      (0U)

+#define DMAMUX_CxCR_DMAREQ_ID_Msk      (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)   /*!< 0x000000FF */

+#define DMAMUX_CxCR_DMAREQ_ID          DMAMUX_CxCR_DMAREQ_ID_Msk               /*!<  DMA request identification */

+#define DMAMUX_CxCR_DMAREQ_ID_0        (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000001 */

+#define DMAMUX_CxCR_DMAREQ_ID_1        (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000002 */

+#define DMAMUX_CxCR_DMAREQ_ID_2        (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000004 */

+#define DMAMUX_CxCR_DMAREQ_ID_3        (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000008 */

+#define DMAMUX_CxCR_DMAREQ_ID_4        (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000010 */

+#define DMAMUX_CxCR_DMAREQ_ID_5        (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000020 */

+#define DMAMUX_CxCR_DMAREQ_ID_6        (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000040 */

+#define DMAMUX_CxCR_DMAREQ_ID_7        (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000080 */

+#define DMAMUX_CxCR_SOIE_Pos           (8U)

+#define DMAMUX_CxCR_SOIE_Msk           (0x1UL << DMAMUX_CxCR_SOIE_Pos)         /*!< 0x00000100 */

+#define DMAMUX_CxCR_SOIE               DMAMUX_CxCR_SOIE_Msk                    /*!<  Synchronization overrun interrupt enable */

+#define DMAMUX_CxCR_EGE_Pos            (9U)

+#define DMAMUX_CxCR_EGE_Msk            (0x1UL << DMAMUX_CxCR_EGE_Pos)          /*!< 0x00000200 */

+#define DMAMUX_CxCR_EGE                DMAMUX_CxCR_EGE_Msk                     /*!<  Event generation enable */

+#define DMAMUX_CxCR_SE_Pos             (16U)

+#define DMAMUX_CxCR_SE_Msk             (0x1UL << DMAMUX_CxCR_SE_Pos)           /*!< 0x00010000 */

+#define DMAMUX_CxCR_SE                 DMAMUX_CxCR_SE_Msk                      /*!<  Synchronization enable */

+#define DMAMUX_CxCR_SPOL_Pos           (17U)

+#define DMAMUX_CxCR_SPOL_Msk           (0x3UL << DMAMUX_CxCR_SPOL_Pos)         /*!< 0x00060000 */

+#define DMAMUX_CxCR_SPOL               DMAMUX_CxCR_SPOL_Msk                    /*!<  Synchronization polarity */

+#define DMAMUX_CxCR_SPOL_0             (0x1UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00020000 */

+#define DMAMUX_CxCR_SPOL_1             (0x2UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00040000 */

+#define DMAMUX_CxCR_NBREQ_Pos          (19U)

+#define DMAMUX_CxCR_NBREQ_Msk          (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)       /*!< 0x00F80000 */

+#define DMAMUX_CxCR_NBREQ              DMAMUX_CxCR_NBREQ_Msk                   /*!<  Number of DMA requests minus 1 to forward */

+#define DMAMUX_CxCR_NBREQ_0            (0x01UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00080000 */

+#define DMAMUX_CxCR_NBREQ_1            (0x02UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00100000 */

+#define DMAMUX_CxCR_NBREQ_2            (0x04UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00200000 */

+#define DMAMUX_CxCR_NBREQ_3            (0x08UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00400000 */

+#define DMAMUX_CxCR_NBREQ_4            (0x10UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00800000 */

+#define DMAMUX_CxCR_SYNC_ID_Pos        (24U)

+#define DMAMUX_CxCR_SYNC_ID_Msk        (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)     /*!< 0x1F000000 */

+#define DMAMUX_CxCR_SYNC_ID            DMAMUX_CxCR_SYNC_ID_Msk                 /*!<  Synchronization identification */

+#define DMAMUX_CxCR_SYNC_ID_0          (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x01000000 */

+#define DMAMUX_CxCR_SYNC_ID_1          (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x02000000 */

+#define DMAMUX_CxCR_SYNC_ID_2          (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x04000000 */

+#define DMAMUX_CxCR_SYNC_ID_3          (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x08000000 */

+#define DMAMUX_CxCR_SYNC_ID_4          (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x10000000 */

+

+/********************  Bits definition for DMAMUX_CSR register  **************/

+#define DMAMUX_CSR_SOF0_Pos            (0U)

+#define DMAMUX_CSR_SOF0_Msk            (0x1UL << DMAMUX_CSR_SOF0_Pos)          /*!< 0x00000001 */

+#define DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0_Msk                     /*!< Channel 0 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF1_Pos            (1U)

+#define DMAMUX_CSR_SOF1_Msk            (0x1UL << DMAMUX_CSR_SOF1_Pos)          /*!< 0x00000002 */

+#define DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1_Msk                     /*!< Channel 1 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF2_Pos            (2U)

+#define DMAMUX_CSR_SOF2_Msk            (0x1UL << DMAMUX_CSR_SOF2_Pos)          /*!< 0x00000004 */

+#define DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2_Msk                     /*!< Channel 2 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF3_Pos            (3U)

+#define DMAMUX_CSR_SOF3_Msk            (0x1UL << DMAMUX_CSR_SOF3_Pos)          /*!< 0x00000008 */

+#define DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3_Msk                     /*!< Channel 3 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF4_Pos            (4U)

+#define DMAMUX_CSR_SOF4_Msk            (0x1UL << DMAMUX_CSR_SOF4_Pos)          /*!< 0x00000010 */

+#define DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4_Msk                     /*!< Channel 4 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF5_Pos            (5U)

+#define DMAMUX_CSR_SOF5_Msk            (0x1UL << DMAMUX_CSR_SOF5_Pos)          /*!< 0x00000020 */

+#define DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5_Msk                     /*!< Channel 5 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF6_Pos            (6U)

+#define DMAMUX_CSR_SOF6_Msk            (0x1UL << DMAMUX_CSR_SOF6_Pos)          /*!< 0x00000040 */

+#define DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6_Msk                     /*!< Channel 6 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF7_Pos            (7U)

+#define DMAMUX_CSR_SOF7_Msk            (0x1UL << DMAMUX_CSR_SOF7_Pos)          /*!< 0x00000080 */

+#define DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7_Msk                     /*!< Channel 7 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF8_Pos            (8U)

+#define DMAMUX_CSR_SOF8_Msk            (0x1UL << DMAMUX_CSR_SOF8_Pos)          /*!< 0x00000100 */

+#define DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8_Msk                     /*!< Channel 8 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF9_Pos            (9U)

+#define DMAMUX_CSR_SOF9_Msk            (0x1UL << DMAMUX_CSR_SOF9_Pos)          /*!< 0x00000200 */

+#define DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9_Msk                     /*!< Channel 9 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF10_Pos           (10U)

+#define DMAMUX_CSR_SOF10_Msk           (0x1UL << DMAMUX_CSR_SOF10_Pos)         /*!< 0x00000400 */

+#define DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10_Msk                    /*!< Channel 10 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF11_Pos           (11U)

+#define DMAMUX_CSR_SOF11_Msk           (0x1UL << DMAMUX_CSR_SOF11_Pos)         /*!< 0x00000800 */

+#define DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11_Msk                    /*!< Channel 11 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF12_Pos           (12U)

+#define DMAMUX_CSR_SOF12_Msk           (0x1UL << DMAMUX_CSR_SOF12_Pos)         /*!< 0x00001000 */

+#define DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12_Msk                    /*!< Channel 12 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF13_Pos           (13U)

+#define DMAMUX_CSR_SOF13_Msk           (0x1UL << DMAMUX_CSR_SOF13_Pos)         /*!< 0x00002000 */

+#define DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13_Msk                    /*!< Channel 13 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF14_Pos           (14U)

+#define DMAMUX_CSR_SOF14_Msk           (0x1UL << DMAMUX_CSR_SOF14_Pos)         /*!< 0x00004000 */

+#define DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14_Msk                    /*!< Channel 14 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF15_Pos           (15U)

+#define DMAMUX_CSR_SOF15_Msk           (0x1UL << DMAMUX_CSR_SOF15_Pos)         /*!< 0x00008000 */

+#define DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15_Msk                    /*!< Channel 15 Synchronization overrun event flag */

+

+/********************  Bits definition for DMAMUX_CFR register  **************/

+#define DMAMUX_CFR_CSOF0_Pos           (0U)

+#define DMAMUX_CFR_CSOF0_Msk           (0x1UL << DMAMUX_CFR_CSOF0_Pos)         /*!< 0x00000001 */

+#define DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0_Msk                    /*!< Channel 0 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF1_Pos           (1U)

+#define DMAMUX_CFR_CSOF1_Msk           (0x1UL << DMAMUX_CFR_CSOF1_Pos)         /*!< 0x00000002 */

+#define DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1_Msk                    /*!< Channel 1 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF2_Pos           (2U)

+#define DMAMUX_CFR_CSOF2_Msk           (0x1UL << DMAMUX_CFR_CSOF2_Pos)         /*!< 0x00000004 */

+#define DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2_Msk                    /*!< Channel 2 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF3_Pos           (3U)

+#define DMAMUX_CFR_CSOF3_Msk           (0x1UL << DMAMUX_CFR_CSOF3_Pos)         /*!< 0x00000008 */

+#define DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3_Msk                    /*!< Channel 3 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF4_Pos           (4U)

+#define DMAMUX_CFR_CSOF4_Msk           (0x1UL << DMAMUX_CFR_CSOF4_Pos)         /*!< 0x00000010 */

+#define DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4_Msk                    /*!< Channel 4 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF5_Pos           (5U)

+#define DMAMUX_CFR_CSOF5_Msk           (0x1UL << DMAMUX_CFR_CSOF5_Pos)         /*!< 0x00000020 */

+#define DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5_Msk                    /*!< Channel 5 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF6_Pos           (6U)

+#define DMAMUX_CFR_CSOF6_Msk           (0x1UL << DMAMUX_CFR_CSOF6_Pos)         /*!< 0x00000040 */

+#define DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6_Msk                    /*!< Channel 6 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF7_Pos           (7U)

+#define DMAMUX_CFR_CSOF7_Msk           (0x1UL << DMAMUX_CFR_CSOF7_Pos)         /*!< 0x00000080 */

+#define DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7_Msk                    /*!< Channel 7 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF8_Pos           (8U)

+#define DMAMUX_CFR_CSOF8_Msk           (0x1UL << DMAMUX_CFR_CSOF8_Pos)         /*!< 0x00000100 */

+#define DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8_Msk                    /*!< Channel 8 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF9_Pos           (9U)

+#define DMAMUX_CFR_CSOF9_Msk           (0x1UL << DMAMUX_CFR_CSOF9_Pos)         /*!< 0x00000200 */

+#define DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9_Msk                    /*!< Channel 9 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF10_Pos          (10U)

+#define DMAMUX_CFR_CSOF10_Msk          (0x1UL << DMAMUX_CFR_CSOF10_Pos)        /*!< 0x00000400 */

+#define DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10_Msk                   /*!< Channel 10 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF11_Pos          (11U)

+#define DMAMUX_CFR_CSOF11_Msk          (0x1UL << DMAMUX_CFR_CSOF11_Pos)        /*!< 0x00000800 */

+#define DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11_Msk                   /*!< Channel 11 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF12_Pos          (12U)

+#define DMAMUX_CFR_CSOF12_Msk          (0x1UL << DMAMUX_CFR_CSOF12_Pos)        /*!< 0x00001000 */

+#define DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12_Msk                   /*!< Channel 12 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF13_Pos          (13U)

+#define DMAMUX_CFR_CSOF13_Msk          (0x1UL << DMAMUX_CFR_CSOF13_Pos)        /*!< 0x00002000 */

+#define DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13_Msk                   /*!< Channel 13 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF14_Pos          (14U)

+#define DMAMUX_CFR_CSOF14_Msk          (0x1UL << DMAMUX_CFR_CSOF14_Pos)        /*!< 0x00004000 */

+#define DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14_Msk                   /*!< Channel 14 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF15_Pos          (15U)

+#define DMAMUX_CFR_CSOF15_Msk          (0x1UL << DMAMUX_CFR_CSOF15_Pos)        /*!< 0x00008000 */

+#define DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15_Msk                   /*!< Channel 15 Clear synchronization overrun event flag */

+

+/********************  Bits definition for DMAMUX_RGxCR register  ************/

+#define DMAMUX_RGxCR_SIG_ID_Pos        (0U)

+#define DMAMUX_RGxCR_SIG_ID_Msk        (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)     /*!< 0x0000001F */

+#define DMAMUX_RGxCR_SIG_ID            DMAMUX_RGxCR_SIG_ID_Msk                 /*!< Signal identification */

+#define DMAMUX_RGxCR_SIG_ID_0          (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000001 */

+#define DMAMUX_RGxCR_SIG_ID_1          (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000002 */

+#define DMAMUX_RGxCR_SIG_ID_2          (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000004 */

+#define DMAMUX_RGxCR_SIG_ID_3          (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000008 */

+#define DMAMUX_RGxCR_SIG_ID_4          (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000010 */

+#define DMAMUX_RGxCR_OIE_Pos           (8U)

+#define DMAMUX_RGxCR_OIE_Msk           (0x1UL << DMAMUX_RGxCR_OIE_Pos)         /*!< 0x00000100 */

+#define DMAMUX_RGxCR_OIE               DMAMUX_RGxCR_OIE_Msk                    /*!< Trigger overrun interrupt enable */

+#define DMAMUX_RGxCR_GE_Pos            (16U)

+#define DMAMUX_RGxCR_GE_Msk            (0x1UL << DMAMUX_RGxCR_GE_Pos)          /*!< 0x00010000 */

+#define DMAMUX_RGxCR_GE                DMAMUX_RGxCR_GE_Msk                     /*!< DMA request generator enable */

+#define DMAMUX_RGxCR_GPOL_Pos          (17U)

+#define DMAMUX_RGxCR_GPOL_Msk          (0x3UL << DMAMUX_RGxCR_GPOL_Pos)        /*!< 0x00060000 */

+#define DMAMUX_RGxCR_GPOL              DMAMUX_RGxCR_GPOL_Msk                   /*!< DMA request generator trigger polarity */

+#define DMAMUX_RGxCR_GPOL_0            (0x1UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00020000 */

+#define DMAMUX_RGxCR_GPOL_1            (0x2UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00040000 */

+#define DMAMUX_RGxCR_GNBREQ_Pos        (19U)

+#define DMAMUX_RGxCR_GNBREQ_Msk        (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)     /*!< 0x00F80000 */

+#define DMAMUX_RGxCR_GNBREQ            DMAMUX_RGxCR_GNBREQ_Msk                 /*!< Number of DMA requests to be generated */

+#define DMAMUX_RGxCR_GNBREQ_0          (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00080000 */

+#define DMAMUX_RGxCR_GNBREQ_1          (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00100000 */

+#define DMAMUX_RGxCR_GNBREQ_2          (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00200000 */

+#define DMAMUX_RGxCR_GNBREQ_3          (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00400000 */

+#define DMAMUX_RGxCR_GNBREQ_4          (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00800000 */

+

+/********************  Bits definition for DMAMUX_RGSR register  **************/

+#define DMAMUX_RGSR_OF0_Pos            (0U)

+#define DMAMUX_RGSR_OF0_Msk            (0x1UL << DMAMUX_RGSR_OF0_Pos)          /*!< 0x00000001 */

+#define DMAMUX_RGSR_OF0                DMAMUX_RGSR_OF0_Msk                     /*!< Request generator channel 0 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF1_Pos            (1U)

+#define DMAMUX_RGSR_OF1_Msk            (0x1UL << DMAMUX_RGSR_OF1_Pos)          /*!< 0x00000002 */

+#define DMAMUX_RGSR_OF1                DMAMUX_RGSR_OF1_Msk                     /*!< Request generator channel 1 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF2_Pos            (2U)

+#define DMAMUX_RGSR_OF2_Msk            (0x1UL << DMAMUX_RGSR_OF2_Pos)          /*!< 0x00000004 */

+#define DMAMUX_RGSR_OF2                DMAMUX_RGSR_OF2_Msk                     /*!< Request generator channel 2 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF3_Pos            (3U)

+#define DMAMUX_RGSR_OF3_Msk            (0x1UL << DMAMUX_RGSR_OF3_Pos)          /*!< 0x00000008 */

+#define DMAMUX_RGSR_OF3                DMAMUX_RGSR_OF3_Msk                     /*!< Request generator channel 3 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF4_Pos            (4U)

+#define DMAMUX_RGSR_OF4_Msk            (0x1UL << DMAMUX_RGSR_OF4_Pos)          /*!< 0x00000010 */

+#define DMAMUX_RGSR_OF4                DMAMUX_RGSR_OF4_Msk                     /*!< Request generator channel 4 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF5_Pos            (5U)

+#define DMAMUX_RGSR_OF5_Msk            (0x1UL << DMAMUX_RGSR_OF5_Pos)          /*!< 0x00000020 */

+#define DMAMUX_RGSR_OF5                DMAMUX_RGSR_OF5_Msk                     /*!< Request generator channel 5 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF6_Pos            (6U)

+#define DMAMUX_RGSR_OF6_Msk            (0x1UL << DMAMUX_RGSR_OF6_Pos)          /*!< 0x00000040 */

+#define DMAMUX_RGSR_OF6                DMAMUX_RGSR_OF6_Msk                     /*!< Request generator channel 6 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF7_Pos            (7U)

+#define DMAMUX_RGSR_OF7_Msk            (0x1UL << DMAMUX_RGSR_OF7_Pos)          /*!< 0x00000080 */

+#define DMAMUX_RGSR_OF7                DMAMUX_RGSR_OF7_Msk                     /*!< Request generator channel 7 Trigger overrun event flag */

+

+/********************  Bits definition for DMAMUX_RGCFR register  **************/

+#define DMAMUX_RGCFR_COF0_Pos          (0U)

+#define DMAMUX_RGCFR_COF0_Msk          (0x1UL << DMAMUX_RGCFR_COF0_Pos)        /*!< 0x00000001 */

+#define DMAMUX_RGCFR_COF0              DMAMUX_RGCFR_COF0_Msk                   /*!< Request generator channel 0 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF1_Pos          (1U)

+#define DMAMUX_RGCFR_COF1_Msk          (0x1UL << DMAMUX_RGCFR_COF1_Pos)        /*!< 0x00000002 */

+#define DMAMUX_RGCFR_COF1              DMAMUX_RGCFR_COF1_Msk                   /*!< Request generator channel 1 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF2_Pos          (2U)

+#define DMAMUX_RGCFR_COF2_Msk          (0x1UL << DMAMUX_RGCFR_COF2_Pos)        /*!< 0x00000004 */

+#define DMAMUX_RGCFR_COF2              DMAMUX_RGCFR_COF2_Msk                   /*!< Request generator channel 2 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF3_Pos          (3U)

+#define DMAMUX_RGCFR_COF3_Msk          (0x1UL << DMAMUX_RGCFR_COF3_Pos)        /*!< 0x00000008 */

+#define DMAMUX_RGCFR_COF3              DMAMUX_RGCFR_COF3_Msk                   /*!< Request generator channel 3 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF4_Pos          (4U)

+#define DMAMUX_RGCFR_COF4_Msk          (0x1UL << DMAMUX_RGCFR_COF4_Pos)        /*!< 0x00000010 */

+#define DMAMUX_RGCFR_COF4              DMAMUX_RGCFR_COF4_Msk                   /*!< Request generator channel 4 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF5_Pos          (5U)

+#define DMAMUX_RGCFR_COF5_Msk          (0x1UL << DMAMUX_RGCFR_COF5_Pos)        /*!< 0x00000020 */

+#define DMAMUX_RGCFR_COF5              DMAMUX_RGCFR_COF5_Msk                   /*!< Request generator channel 5 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF6_Pos          (6U)

+#define DMAMUX_RGCFR_COF6_Msk          (0x1UL << DMAMUX_RGCFR_COF6_Pos)        /*!< 0x00000040 */

+#define DMAMUX_RGCFR_COF6              DMAMUX_RGCFR_COF6_Msk                   /*!< Request generator channel 6 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF7_Pos          (7U)

+#define DMAMUX_RGCFR_COF7_Msk          (0x1UL << DMAMUX_RGCFR_COF7_Pos)        /*!< 0x00000080 */

+#define DMAMUX_RGCFR_COF7              DMAMUX_RGCFR_COF7_Msk                   /*!< Request generator channel 7 Clear trigger overrun event flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         AHB Master DMA2D Controller (DMA2D)                */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for DMA2D_CR register  ******************/

+

+#define DMA2D_CR_START_Pos         (0U)

+#define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)               /*!< 0x00000001 */

+#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer                          */

+#define DMA2D_CR_SUSP_Pos          (1U)

+#define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                /*!< 0x00000002 */

+#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer                        */

+#define DMA2D_CR_ABORT_Pos         (2U)

+#define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)               /*!< 0x00000004 */

+#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer                          */

+#define DMA2D_CR_LOM_Pos           (6U)

+#define DMA2D_CR_LOM_Msk           (0x1UL << DMA2D_CR_LOM_Pos)                 /*!< 0x00000040 */

+#define DMA2D_CR_LOM               DMA2D_CR_LOM_Msk                            /*!< Line Offset Mode                         */

+#define DMA2D_CR_TEIE_Pos          (8U)

+#define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                /*!< 0x00000100 */

+#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable         */

+#define DMA2D_CR_TCIE_Pos          (9U)

+#define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                /*!< 0x00000200 */

+#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable      */

+#define DMA2D_CR_TWIE_Pos          (10U)

+#define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                /*!< 0x00000400 */

+#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable     */

+#define DMA2D_CR_CAEIE_Pos         (11U)

+#define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)               /*!< 0x00000800 */

+#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable      */

+#define DMA2D_CR_CTCIE_Pos         (12U)

+#define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)               /*!< 0x00001000 */

+#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */

+#define DMA2D_CR_CEIE_Pos          (13U)

+#define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                /*!< 0x00002000 */

+#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable    */

+#define DMA2D_CR_MODE_Pos          (16U)

+#define DMA2D_CR_MODE_Msk          (0x7UL << DMA2D_CR_MODE_Pos)                /*!< 0x00070000 */

+#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[2:0]                         */

+#define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */

+#define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */

+#define DMA2D_CR_MODE_2            (0x4UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00040000 */

+

+/********************  Bit definition for DMA2D_ISR register  *****************/

+

+#define DMA2D_ISR_TEIF_Pos         (0U)

+#define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)               /*!< 0x00000001 */

+#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag         */

+#define DMA2D_ISR_TCIF_Pos         (1U)

+#define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)               /*!< 0x00000002 */

+#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag      */

+#define DMA2D_ISR_TWIF_Pos         (2U)

+#define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)               /*!< 0x00000004 */

+#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag     */

+#define DMA2D_ISR_CAEIF_Pos        (3U)

+#define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)              /*!< 0x00000008 */

+#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag      */

+#define DMA2D_ISR_CTCIF_Pos        (4U)

+#define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)              /*!< 0x00000010 */

+#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */

+#define DMA2D_ISR_CEIF_Pos         (5U)

+#define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)               /*!< 0x00000020 */

+#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag    */

+

+/********************  Bit definition for DMA2D_IFCR register  ****************/

+

+#define DMA2D_IFCR_CTEIF_Pos       (0U)

+#define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)             /*!< 0x00000001 */

+#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */

+#define DMA2D_IFCR_CTCIF_Pos       (1U)

+#define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)             /*!< 0x00000002 */

+#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */

+#define DMA2D_IFCR_CTWIF_Pos       (2U)

+#define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)             /*!< 0x00000004 */

+#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */

+#define DMA2D_IFCR_CAECIF_Pos      (3U)

+#define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)            /*!< 0x00000008 */

+#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */

+#define DMA2D_IFCR_CCTCIF_Pos      (4U)

+#define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)            /*!< 0x00000010 */

+#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */

+#define DMA2D_IFCR_CCEIF_Pos       (5U)

+#define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)             /*!< 0x00000020 */

+#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */

+

+/********************  Bit definition for DMA2D_FGMAR register  ***************/

+

+#define DMA2D_FGMAR_MA_Pos         (0U)

+#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)        /*!< 0xFFFFFFFF */

+#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Foreground Memory Address */

+

+/********************  Bit definition for DMA2D_FGOR register  ****************/

+

+#define DMA2D_FGOR_LO_Pos          (0U)

+#define DMA2D_FGOR_LO_Msk          (0xFFFFUL << DMA2D_FGOR_LO_Pos)             /*!< 0x0000FFFF */

+#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */

+

+/********************  Bit definition for DMA2D_BGMAR register  ***************/

+

+#define DMA2D_BGMAR_MA_Pos         (0U)

+#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)        /*!< 0xFFFFFFFF */

+#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Background Memory Address */

+

+/********************  Bit definition for DMA2D_BGOR register  ****************/

+

+#define DMA2D_BGOR_LO_Pos          (0U)

+#define DMA2D_BGOR_LO_Msk          (0xFFFFUL << DMA2D_BGOR_LO_Pos)             /*!< 0x0000FFFF */

+#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */

+

+/********************  Bit definition for DMA2D_FGPFCCR register  *************/

+

+#define DMA2D_FGPFCCR_CM_Pos       (0U)

+#define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x0000000F */

+#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */

+#define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */

+#define DMA2D_FGPFCCR_CCM_Pos      (4U)

+#define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)            /*!< 0x00000010 */

+#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */

+#define DMA2D_FGPFCCR_START_Pos    (5U)

+#define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)          /*!< 0x00000020 */

+#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */

+#define DMA2D_FGPFCCR_CS_Pos       (8U)

+#define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)            /*!< 0x0000FF00 */

+#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */

+#define DMA2D_FGPFCCR_AM_Pos       (16U)

+#define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00030000 */

+#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */

+#define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */

+#define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */

+#define DMA2D_FGPFCCR_CSS_Pos      (18U)

+#define DMA2D_FGPFCCR_CSS_Msk      (0x3UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x000C0000 */

+#define DMA2D_FGPFCCR_CSS          DMA2D_FGPFCCR_CSS_Msk                       /* !< Chroma Sub-Sampling */

+#define DMA2D_FGPFCCR_CSS_0        (0x1UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00040000 */

+#define DMA2D_FGPFCCR_CSS_1        (0x2UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00080000 */

+#define DMA2D_FGPFCCR_AI_Pos       (20U)

+#define DMA2D_FGPFCCR_AI_Msk       (0x1UL << DMA2D_FGPFCCR_AI_Pos)             /*!< 0x00100000 */

+#define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Foreground Input Alpha Inverted */

+#define DMA2D_FGPFCCR_RBS_Pos      (21U)

+#define DMA2D_FGPFCCR_RBS_Msk      (0x1UL << DMA2D_FGPFCCR_RBS_Pos)            /*!< 0x00200000 */

+#define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Foreground Input Red Blue Swap */

+#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)

+#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */

+#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */

+

+/********************  Bit definition for DMA2D_FGCOLR register  **************/

+

+#define DMA2D_FGCOLR_BLUE_Pos      (0U)

+#define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)           /*!< 0x000000FF */

+#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Foreground Blue Value */

+#define DMA2D_FGCOLR_GREEN_Pos     (8U)

+#define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */

+#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Foreground Green Value */

+#define DMA2D_FGCOLR_RED_Pos       (16U)

+#define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)            /*!< 0x00FF0000 */

+#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Foreground Red Value */

+

+/********************  Bit definition for DMA2D_BGPFCCR register  *************/

+

+#define DMA2D_BGPFCCR_CM_Pos       (0U)

+#define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x0000000F */

+#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */

+#define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_BGPFCCR_CM_3         (0x8UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000008 */

+#define DMA2D_BGPFCCR_CCM_Pos      (4U)

+#define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)            /*!< 0x00000010 */

+#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */

+#define DMA2D_BGPFCCR_START_Pos    (5U)

+#define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)          /*!< 0x00000020 */

+#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */

+#define DMA2D_BGPFCCR_CS_Pos       (8U)

+#define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)            /*!< 0x0000FF00 */

+#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */

+#define DMA2D_BGPFCCR_AM_Pos       (16U)

+#define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00030000 */

+#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */

+#define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */

+#define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */

+#define DMA2D_BGPFCCR_AI_Pos       (20U)

+#define DMA2D_BGPFCCR_AI_Msk       (0x1UL << DMA2D_BGPFCCR_AI_Pos)             /*!< 0x00100000 */

+#define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< background Input Alpha Inverted */

+#define DMA2D_BGPFCCR_RBS_Pos      (21U)

+#define DMA2D_BGPFCCR_RBS_Msk      (0x1UL << DMA2D_BGPFCCR_RBS_Pos)            /*!< 0x00200000 */

+#define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Background Input Red Blue Swap */

+#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)

+#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */

+#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */

+

+/********************  Bit definition for DMA2D_BGCOLR register  **************/

+

+#define DMA2D_BGCOLR_BLUE_Pos      (0U)

+#define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)           /*!< 0x000000FF */

+#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Background Blue Value */

+#define DMA2D_BGCOLR_GREEN_Pos     (8U)

+#define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */

+#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Background Green Value */

+#define DMA2D_BGCOLR_RED_Pos       (16U)

+#define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)            /*!< 0x00FF0000 */

+#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Background Red Value */

+

+/********************  Bit definition for DMA2D_FGCMAR register  **************/

+

+#define DMA2D_FGCMAR_MA_Pos        (0U)

+#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */

+#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Foreground CLUT Memory Address */

+

+/********************  Bit definition for DMA2D_BGCMAR register  **************/

+

+#define DMA2D_BGCMAR_MA_Pos        (0U)

+#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */

+#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Background CLUT Memory Address */

+

+/********************  Bit definition for DMA2D_OPFCCR register  **************/

+

+#define DMA2D_OPFCCR_CM_Pos        (0U)

+#define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000007 */

+#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Output Color mode CM[2:0] */

+#define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_OPFCCR_SB_Pos        (8U)

+#define DMA2D_OPFCCR_SB_Msk        (0x1UL << DMA2D_OPFCCR_SB_Pos)              /*!< 0x00000100 */

+#define DMA2D_OPFCCR_SB            DMA2D_OPFCCR_SB_Msk                         /*!< Swap Bytes */

+#define DMA2D_OPFCCR_AI_Pos        (20U)

+#define DMA2D_OPFCCR_AI_Msk        (0x1UL << DMA2D_OPFCCR_AI_Pos)              /*!< 0x00100000 */

+#define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Output Alpha Inverted */

+#define DMA2D_OPFCCR_RBS_Pos       (21U)

+#define DMA2D_OPFCCR_RBS_Msk       (0x1UL << DMA2D_OPFCCR_RBS_Pos)             /*!< 0x00200000 */

+#define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Output Red Blue Swap */

+

+/********************  Bit definition for DMA2D_OCOLR register  ***************/

+

+/*!<Mode_ARGB8888/RGB888 */

+

+#define DMA2D_OCOLR_BLUE_1_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_1_Msk     (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos)            /*0x000000FFU*/

+#define DMA2D_OCOLR_BLUE_1         DMA2D_OCOLR_BLUE_1_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_1_Pos    (8U)

+#define DMA2D_OCOLR_GREEN_1_Msk    (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos)            /*0x0000FF00U)*/

+#define DMA2D_OCOLR_GREEN_1        DMA2D_OCOLR_GREEN_1_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_1_Pos      (16U)

+#define DMA2D_OCOLR_RED_1_Msk      (0xFFUL << DMA2D_OCOLR_RED_1_Pos)            /*0x00FF0000U */

+#define DMA2D_OCOLR_RED_1          DMA2D_OCOLR_RED_1_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_1_Pos    (24U)

+#define DMA2D_OCOLR_ALPHA_1_Msk    (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos)          /*0xFF000000U*/

+#define DMA2D_OCOLR_ALPHA_1        DMA2D_OCOLR_ALPHA_1_Msk                     /*!< Output Alpha Channel Value */

+

+/*!<Mode_RGB565 */

+#define DMA2D_OCOLR_BLUE_2_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_2_Msk     (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos)            /*0x0000001FU*/

+#define DMA2D_OCOLR_BLUE_2         DMA2D_OCOLR_BLUE_2_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_2_Pos    (5U)

+#define DMA2D_OCOLR_GREEN_2_Msk    (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos)          /* 0x000007E0U */

+#define DMA2D_OCOLR_GREEN_2        DMA2D_OCOLR_GREEN_2_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_2_Pos      (11U)

+#define DMA2D_OCOLR_RED_2_Msk      (0xF8UL<<DMA2D_OCOLR_RED_2_Pos)              /*0x0000F800U*/

+#define DMA2D_OCOLR_RED_2          DMA2D_OCOLR_RED_2_Msk                       /*!< Output Red Value */

+

+/*!<Mode_ARGB1555 */

+#define DMA2D_OCOLR_BLUE_3_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_3_Msk     (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos)           /*0x0000001FU*/

+#define DMA2D_OCOLR_BLUE_3         DMA2D_OCOLR_BLUE_3_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_3_Pos    (5U)

+#define DMA2D_OCOLR_GREEN_3_Msk    (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos)          /*0x000003E0U*/

+#define DMA2D_OCOLR_GREEN_3        DMA2D_OCOLR_GREEN_3_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_3_Pos      (10U)

+#define DMA2D_OCOLR_RED_3_Msk      (0x7CUL << DMA2D_OCOLR_RED_3_Pos)            /* 0x00007C00U*/

+#define DMA2D_OCOLR_RED_3          DMA2D_OCOLR_RED_3_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_3_Pos    (15U)

+#define DMA2D_OCOLR_ALPHA_3_Msk    (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos)           /*0x00008000U*/

+#define DMA2D_OCOLR_ALPHA_3        DMA2D_OCOLR_ALPHA_3_Msk                     /*!< Output Alpha Channel Value */

+

+/*!<Mode_ARGB4444 */

+#define DMA2D_OCOLR_BLUE_4_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_4_Msk     (0xFUL << DMA2D_OCOLR_BLUE_4_Pos)            /*0x0000000FU*/

+#define DMA2D_OCOLR_BLUE_4         DMA2D_OCOLR_BLUE_4_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_4_Pos    (4U)

+#define DMA2D_OCOLR_GREEN_4_Msk    (0xFUL << DMA2D_OCOLR_GREEN_4_Pos)           /*0x000000F0U*/

+#define DMA2D_OCOLR_GREEN_4        DMA2D_OCOLR_GREEN_4_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_4_Pos      (8U)

+#define DMA2D_OCOLR_RED_4_Msk      (0xFUL << DMA2D_OCOLR_RED_4_Pos)             /*0x00000F00U*/

+#define DMA2D_OCOLR_RED_4          DMA2D_OCOLR_RED_4_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_4_Pos    (12U)

+#define DMA2D_OCOLR_ALPHA_4_Msk    (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos)            /*0x0000F000U*/

+#define DMA2D_OCOLR_ALPHA_4        DMA2D_OCOLR_ALPHA_4_Msk                     /*!< Output Alpha Channel Value */

+

+/********************  Bit definition for DMA2D_OMAR register  ****************/

+

+#define DMA2D_OMAR_MA_Pos          (0U)

+#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)         /*!< 0xFFFFFFFF */

+#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Output Memory Address */

+

+/********************  Bit definition for DMA2D_OOR register  *****************/

+

+#define DMA2D_OOR_LO_Pos           (0U)

+#define DMA2D_OOR_LO_Msk           (0xFFFFUL << DMA2D_OOR_LO_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Output Line Offset */

+

+/********************  Bit definition for DMA2D_NLR register  *****************/

+

+#define DMA2D_NLR_NL_Pos           (0U)

+#define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */

+#define DMA2D_NLR_PL_Pos           (16U)

+#define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)              /*!< 0x3FFF0000 */

+#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */

+

+/********************  Bit definition for DMA2D_LWR register  *****************/

+

+#define DMA2D_LWR_LW_Pos           (0U)

+#define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */

+

+/********************  Bit definition for DMA2D_AMTCR register  ***************/

+

+#define DMA2D_AMTCR_EN_Pos         (0U)

+#define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)               /*!< 0x00000001 */

+#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */

+#define DMA2D_AMTCR_DT_Pos         (8U)

+#define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)              /*!< 0x0000FF00 */

+#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */

+

+

+/********************  Bit definition for DMA2D_FGCLUT register  **************/

+

+/********************  Bit definition for DMA2D_BGCLUT register  **************/

+

+/******************************************************************************/

+/*                                                                            */

+/*                     Display Serial Interface (DSI)                         */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for DSI_VR register  *****************/

+#define DSI_VR_Pos                    (1U)

+#define DSI_VR_Msk                    (0x18999815UL << DSI_VR_Pos)             /*!< 0x3133302A */

+#define DSI_VR                        DSI_VR_Msk                               /*!< DSI Host Version */

+

+/*******************  Bit definition for DSI_CR register  *****************/

+#define DSI_CR_EN_Pos                 (0U)

+#define DSI_CR_EN_Msk                 (0x1UL << DSI_CR_EN_Pos)                 /*!< 0x00000001 */

+#define DSI_CR_EN                     DSI_CR_EN_Msk                            /*!< DSI Host power up and reset */

+

+/*******************  Bit definition for DSI_CCR register  ****************/

+#define DSI_CCR_TXECKDIV_Pos          (0U)

+#define DSI_CCR_TXECKDIV_Msk          (0xFFUL << DSI_CCR_TXECKDIV_Pos)         /*!< 0x000000FF */

+#define DSI_CCR_TXECKDIV              DSI_CCR_TXECKDIV_Msk                     /*!< TX Escape Clock Division */

+#define DSI_CCR_TXECKDIV0_Pos         (0U)

+#define DSI_CCR_TXECKDIV0_Msk         (0x1UL << DSI_CCR_TXECKDIV0_Pos)         /*!< 0x00000001 */

+#define DSI_CCR_TXECKDIV0             DSI_CCR_TXECKDIV0_Msk

+#define DSI_CCR_TXECKDIV1_Pos         (1U)

+#define DSI_CCR_TXECKDIV1_Msk         (0x1UL << DSI_CCR_TXECKDIV1_Pos)         /*!< 0x00000002 */

+#define DSI_CCR_TXECKDIV1             DSI_CCR_TXECKDIV1_Msk

+#define DSI_CCR_TXECKDIV2_Pos         (2U)

+#define DSI_CCR_TXECKDIV2_Msk         (0x1UL << DSI_CCR_TXECKDIV2_Pos)         /*!< 0x00000004 */

+#define DSI_CCR_TXECKDIV2             DSI_CCR_TXECKDIV2_Msk

+#define DSI_CCR_TXECKDIV3_Pos         (3U)

+#define DSI_CCR_TXECKDIV3_Msk         (0x1UL << DSI_CCR_TXECKDIV3_Pos)         /*!< 0x00000008 */

+#define DSI_CCR_TXECKDIV3             DSI_CCR_TXECKDIV3_Msk

+#define DSI_CCR_TXECKDIV4_Pos         (4U)

+#define DSI_CCR_TXECKDIV4_Msk         (0x1UL << DSI_CCR_TXECKDIV4_Pos)         /*!< 0x00000010 */

+#define DSI_CCR_TXECKDIV4             DSI_CCR_TXECKDIV4_Msk

+#define DSI_CCR_TXECKDIV5_Pos         (5U)

+#define DSI_CCR_TXECKDIV5_Msk         (0x1UL << DSI_CCR_TXECKDIV5_Pos)         /*!< 0x00000020 */

+#define DSI_CCR_TXECKDIV5             DSI_CCR_TXECKDIV5_Msk

+#define DSI_CCR_TXECKDIV6_Pos         (6U)

+#define DSI_CCR_TXECKDIV6_Msk         (0x1UL << DSI_CCR_TXECKDIV6_Pos)         /*!< 0x00000040 */

+#define DSI_CCR_TXECKDIV6             DSI_CCR_TXECKDIV6_Msk

+#define DSI_CCR_TXECKDIV7_Pos         (7U)

+#define DSI_CCR_TXECKDIV7_Msk         (0x1UL << DSI_CCR_TXECKDIV7_Pos)         /*!< 0x00000080 */

+#define DSI_CCR_TXECKDIV7             DSI_CCR_TXECKDIV7_Msk

+

+#define DSI_CCR_TOCKDIV_Pos           (8U)

+#define DSI_CCR_TOCKDIV_Msk           (0xFFUL << DSI_CCR_TOCKDIV_Pos)          /*!< 0x0000FF00 */

+#define DSI_CCR_TOCKDIV               DSI_CCR_TOCKDIV_Msk                      /*!< Timeout Clock Division */

+#define DSI_CCR_TOCKDIV0_Pos          (8U)

+#define DSI_CCR_TOCKDIV0_Msk          (0x1UL << DSI_CCR_TOCKDIV0_Pos)          /*!< 0x00000100 */

+#define DSI_CCR_TOCKDIV0              DSI_CCR_TOCKDIV0_Msk

+#define DSI_CCR_TOCKDIV1_Pos          (9U)

+#define DSI_CCR_TOCKDIV1_Msk          (0x1UL << DSI_CCR_TOCKDIV1_Pos)          /*!< 0x00000200 */

+#define DSI_CCR_TOCKDIV1              DSI_CCR_TOCKDIV1_Msk

+#define DSI_CCR_TOCKDIV2_Pos          (10U)

+#define DSI_CCR_TOCKDIV2_Msk          (0x1UL << DSI_CCR_TOCKDIV2_Pos)          /*!< 0x00000400 */

+#define DSI_CCR_TOCKDIV2              DSI_CCR_TOCKDIV2_Msk

+#define DSI_CCR_TOCKDIV3_Pos          (11U)

+#define DSI_CCR_TOCKDIV3_Msk          (0x1UL << DSI_CCR_TOCKDIV3_Pos)          /*!< 0x00000800 */

+#define DSI_CCR_TOCKDIV3              DSI_CCR_TOCKDIV3_Msk

+#define DSI_CCR_TOCKDIV4_Pos          (12U)

+#define DSI_CCR_TOCKDIV4_Msk          (0x1UL << DSI_CCR_TOCKDIV4_Pos)          /*!< 0x00001000 */

+#define DSI_CCR_TOCKDIV4              DSI_CCR_TOCKDIV4_Msk

+#define DSI_CCR_TOCKDIV5_Pos          (13U)

+#define DSI_CCR_TOCKDIV5_Msk          (0x1UL << DSI_CCR_TOCKDIV5_Pos)          /*!< 0x00002000 */

+#define DSI_CCR_TOCKDIV5              DSI_CCR_TOCKDIV5_Msk

+#define DSI_CCR_TOCKDIV6_Pos          (14U)

+#define DSI_CCR_TOCKDIV6_Msk          (0x1UL << DSI_CCR_TOCKDIV6_Pos)          /*!< 0x00004000 */

+#define DSI_CCR_TOCKDIV6              DSI_CCR_TOCKDIV6_Msk

+#define DSI_CCR_TOCKDIV7_Pos          (15U)

+#define DSI_CCR_TOCKDIV7_Msk          (0x1UL << DSI_CCR_TOCKDIV7_Pos)          /*!< 0x00008000 */

+#define DSI_CCR_TOCKDIV7              DSI_CCR_TOCKDIV7_Msk

+

+/*******************  Bit definition for DSI_LVCIDR register  *************/

+#define DSI_LVCIDR_VCID_Pos           (0U)

+#define DSI_LVCIDR_VCID_Msk           (0x3UL << DSI_LVCIDR_VCID_Pos)           /*!< 0x00000003 */

+#define DSI_LVCIDR_VCID               DSI_LVCIDR_VCID_Msk                      /*!< Virtual Channel ID */

+#define DSI_LVCIDR_VCID0_Pos          (0U)

+#define DSI_LVCIDR_VCID0_Msk          (0x1UL << DSI_LVCIDR_VCID0_Pos)          /*!< 0x00000001 */

+#define DSI_LVCIDR_VCID0              DSI_LVCIDR_VCID0_Msk

+#define DSI_LVCIDR_VCID1_Pos          (1U)

+#define DSI_LVCIDR_VCID1_Msk          (0x1UL << DSI_LVCIDR_VCID1_Pos)          /*!< 0x00000002 */

+#define DSI_LVCIDR_VCID1              DSI_LVCIDR_VCID1_Msk

+

+/*******************  Bit definition for DSI_LCOLCR register  *************/

+#define DSI_LCOLCR_COLC_Pos           (0U)

+#define DSI_LCOLCR_COLC_Msk           (0xFUL << DSI_LCOLCR_COLC_Pos)           /*!< 0x0000000F */

+#define DSI_LCOLCR_COLC               DSI_LCOLCR_COLC_Msk                      /*!< Color Coding */

+#define DSI_LCOLCR_COLC0_Pos          (0U)

+#define DSI_LCOLCR_COLC0_Msk          (0x1UL << DSI_LCOLCR_COLC0_Pos)          /*!< 0x00000001 */

+#define DSI_LCOLCR_COLC0              DSI_LCOLCR_COLC0_Msk

+#define DSI_LCOLCR_COLC1_Pos          (5U)

+#define DSI_LCOLCR_COLC1_Msk          (0x1UL << DSI_LCOLCR_COLC1_Pos)          /*!< 0x00000020 */

+#define DSI_LCOLCR_COLC1              DSI_LCOLCR_COLC1_Msk

+#define DSI_LCOLCR_COLC2_Pos          (6U)

+#define DSI_LCOLCR_COLC2_Msk          (0x1UL << DSI_LCOLCR_COLC2_Pos)          /*!< 0x00000040 */

+#define DSI_LCOLCR_COLC2              DSI_LCOLCR_COLC2_Msk

+#define DSI_LCOLCR_COLC3_Pos          (7U)

+#define DSI_LCOLCR_COLC3_Msk          (0x1UL << DSI_LCOLCR_COLC3_Pos)          /*!< 0x00000080 */

+#define DSI_LCOLCR_COLC3              DSI_LCOLCR_COLC3_Msk

+

+#define DSI_LCOLCR_LPE_Pos            (8U)

+#define DSI_LCOLCR_LPE_Msk            (0x1UL << DSI_LCOLCR_LPE_Pos)            /*!< 0x00000100 */

+#define DSI_LCOLCR_LPE                DSI_LCOLCR_LPE_Msk                       /*!< Loosly Packet Enable */

+

+/*******************  Bit definition for DSI_LPCR register  ***************/

+#define DSI_LPCR_DEP_Pos              (0U)

+#define DSI_LPCR_DEP_Msk              (0x1UL << DSI_LPCR_DEP_Pos)              /*!< 0x00000001 */

+#define DSI_LPCR_DEP                  DSI_LPCR_DEP_Msk                         /*!< Data Enable Polarity */

+#define DSI_LPCR_VSP_Pos              (1U)

+#define DSI_LPCR_VSP_Msk              (0x1UL << DSI_LPCR_VSP_Pos)              /*!< 0x00000002 */

+#define DSI_LPCR_VSP                  DSI_LPCR_VSP_Msk                         /*!< VSYNC Polarity */

+#define DSI_LPCR_HSP_Pos              (2U)

+#define DSI_LPCR_HSP_Msk              (0x1UL << DSI_LPCR_HSP_Pos)              /*!< 0x00000004 */

+#define DSI_LPCR_HSP                  DSI_LPCR_HSP_Msk                         /*!< HSYNC Polarity */

+

+/*******************  Bit definition for DSI_LPMCR register  **************/

+#define DSI_LPMCR_VLPSIZE_Pos         (0U)

+#define DSI_LPMCR_VLPSIZE_Msk         (0xFFUL << DSI_LPMCR_VLPSIZE_Pos)        /*!< 0x000000FF */

+#define DSI_LPMCR_VLPSIZE             DSI_LPMCR_VLPSIZE_Msk                    /*!< VACT Largest Packet Size */

+#define DSI_LPMCR_VLPSIZE0_Pos        (0U)

+#define DSI_LPMCR_VLPSIZE0_Msk        (0x1UL << DSI_LPMCR_VLPSIZE0_Pos)        /*!< 0x00000001 */

+#define DSI_LPMCR_VLPSIZE0            DSI_LPMCR_VLPSIZE0_Msk

+#define DSI_LPMCR_VLPSIZE1_Pos        (1U)

+#define DSI_LPMCR_VLPSIZE1_Msk        (0x1UL << DSI_LPMCR_VLPSIZE1_Pos)        /*!< 0x00000002 */

+#define DSI_LPMCR_VLPSIZE1            DSI_LPMCR_VLPSIZE1_Msk

+#define DSI_LPMCR_VLPSIZE2_Pos        (2U)

+#define DSI_LPMCR_VLPSIZE2_Msk        (0x1UL << DSI_LPMCR_VLPSIZE2_Pos)        /*!< 0x00000004 */

+#define DSI_LPMCR_VLPSIZE2            DSI_LPMCR_VLPSIZE2_Msk

+#define DSI_LPMCR_VLPSIZE3_Pos        (3U)

+#define DSI_LPMCR_VLPSIZE3_Msk        (0x1UL << DSI_LPMCR_VLPSIZE3_Pos)        /*!< 0x00000008 */

+#define DSI_LPMCR_VLPSIZE3            DSI_LPMCR_VLPSIZE3_Msk

+#define DSI_LPMCR_VLPSIZE4_Pos        (4U)

+#define DSI_LPMCR_VLPSIZE4_Msk        (0x1UL << DSI_LPMCR_VLPSIZE4_Pos)        /*!< 0x00000010 */

+#define DSI_LPMCR_VLPSIZE4            DSI_LPMCR_VLPSIZE4_Msk

+#define DSI_LPMCR_VLPSIZE5_Pos        (5U)

+#define DSI_LPMCR_VLPSIZE5_Msk        (0x1UL << DSI_LPMCR_VLPSIZE5_Pos)        /*!< 0x00000020 */

+#define DSI_LPMCR_VLPSIZE5            DSI_LPMCR_VLPSIZE5_Msk

+#define DSI_LPMCR_VLPSIZE6_Pos        (6U)

+#define DSI_LPMCR_VLPSIZE6_Msk        (0x1UL << DSI_LPMCR_VLPSIZE6_Pos)        /*!< 0x00000040 */

+#define DSI_LPMCR_VLPSIZE6            DSI_LPMCR_VLPSIZE6_Msk

+#define DSI_LPMCR_VLPSIZE7_Pos        (7U)

+#define DSI_LPMCR_VLPSIZE7_Msk        (0x1UL << DSI_LPMCR_VLPSIZE7_Pos)        /*!< 0x00000080 */

+#define DSI_LPMCR_VLPSIZE7            DSI_LPMCR_VLPSIZE7_Msk

+

+#define DSI_LPMCR_LPSIZE_Pos          (16U)

+#define DSI_LPMCR_LPSIZE_Msk          (0xFFUL << DSI_LPMCR_LPSIZE_Pos)         /*!< 0x00FF0000 */

+#define DSI_LPMCR_LPSIZE              DSI_LPMCR_LPSIZE_Msk                     /*!< Largest Packet Size */

+#define DSI_LPMCR_LPSIZE0_Pos         (16U)

+#define DSI_LPMCR_LPSIZE0_Msk         (0x1UL << DSI_LPMCR_LPSIZE0_Pos)         /*!< 0x00010000 */

+#define DSI_LPMCR_LPSIZE0             DSI_LPMCR_LPSIZE0_Msk

+#define DSI_LPMCR_LPSIZE1_Pos         (17U)

+#define DSI_LPMCR_LPSIZE1_Msk         (0x1UL << DSI_LPMCR_LPSIZE1_Pos)         /*!< 0x00020000 */

+#define DSI_LPMCR_LPSIZE1             DSI_LPMCR_LPSIZE1_Msk

+#define DSI_LPMCR_LPSIZE2_Pos         (18U)

+#define DSI_LPMCR_LPSIZE2_Msk         (0x1UL << DSI_LPMCR_LPSIZE2_Pos)         /*!< 0x00040000 */

+#define DSI_LPMCR_LPSIZE2             DSI_LPMCR_LPSIZE2_Msk

+#define DSI_LPMCR_LPSIZE3_Pos         (19U)

+#define DSI_LPMCR_LPSIZE3_Msk         (0x1UL << DSI_LPMCR_LPSIZE3_Pos)         /*!< 0x00080000 */

+#define DSI_LPMCR_LPSIZE3             DSI_LPMCR_LPSIZE3_Msk

+#define DSI_LPMCR_LPSIZE4_Pos         (20U)

+#define DSI_LPMCR_LPSIZE4_Msk         (0x1UL << DSI_LPMCR_LPSIZE4_Pos)         /*!< 0x00100000 */

+#define DSI_LPMCR_LPSIZE4             DSI_LPMCR_LPSIZE4_Msk

+#define DSI_LPMCR_LPSIZE5_Pos         (21U)

+#define DSI_LPMCR_LPSIZE5_Msk         (0x1UL << DSI_LPMCR_LPSIZE5_Pos)         /*!< 0x00200000 */

+#define DSI_LPMCR_LPSIZE5             DSI_LPMCR_LPSIZE5_Msk

+#define DSI_LPMCR_LPSIZE6_Pos         (22U)

+#define DSI_LPMCR_LPSIZE6_Msk         (0x1UL << DSI_LPMCR_LPSIZE6_Pos)         /*!< 0x00400000 */

+#define DSI_LPMCR_LPSIZE6             DSI_LPMCR_LPSIZE6_Msk

+#define DSI_LPMCR_LPSIZE7_Pos         (23U)

+#define DSI_LPMCR_LPSIZE7_Msk         (0x1UL << DSI_LPMCR_LPSIZE7_Pos)         /*!< 0x00800000 */

+#define DSI_LPMCR_LPSIZE7             DSI_LPMCR_LPSIZE7_Msk

+

+/*******************  Bit definition for DSI_PCR register  ****************/

+#define DSI_PCR_ETTXE_Pos             (0U)

+#define DSI_PCR_ETTXE_Msk             (0x1UL << DSI_PCR_ETTXE_Pos)             /*!< 0x00000001 */

+#define DSI_PCR_ETTXE                 DSI_PCR_ETTXE_Msk                        /*!< EoTp Transmission Enable */

+#define DSI_PCR_ETRXE_Pos             (1U)

+#define DSI_PCR_ETRXE_Msk             (0x1UL << DSI_PCR_ETRXE_Pos)             /*!< 0x00000002 */

+#define DSI_PCR_ETRXE                 DSI_PCR_ETRXE_Msk                        /*!< EoTp Reception Enable */

+#define DSI_PCR_BTAE_Pos              (2U)

+#define DSI_PCR_BTAE_Msk              (0x1UL << DSI_PCR_BTAE_Pos)              /*!< 0x00000004 */

+#define DSI_PCR_BTAE                  DSI_PCR_BTAE_Msk                         /*!< Bus Turn Around Enable */

+#define DSI_PCR_ECCRXE_Pos            (3U)

+#define DSI_PCR_ECCRXE_Msk            (0x1UL << DSI_PCR_ECCRXE_Pos)            /*!< 0x00000008 */

+#define DSI_PCR_ECCRXE                DSI_PCR_ECCRXE_Msk                       /*!< ECC Reception Enable */

+#define DSI_PCR_CRCRXE_Pos            (4U)

+#define DSI_PCR_CRCRXE_Msk            (0x1UL << DSI_PCR_CRCRXE_Pos)            /*!< 0x00000010 */

+#define DSI_PCR_CRCRXE                DSI_PCR_CRCRXE_Msk                       /*!< CRC Reception Enable */

+

+/*******************  Bit definition for DSI_GVCIDR register  *************/

+#define DSI_GVCIDR_VCID_Pos           (0U)

+#define DSI_GVCIDR_VCID_Msk           (0x3UL << DSI_GVCIDR_VCID_Pos)           /*!< 0x00000003 */

+#define DSI_GVCIDR_VCID               DSI_GVCIDR_VCID_Msk                      /*!< Virtual Channel ID */

+#define DSI_GVCIDR_VCID0_Pos          (0U)

+#define DSI_GVCIDR_VCID0_Msk          (0x1UL << DSI_GVCIDR_VCID0_Pos)          /*!< 0x00000001 */

+#define DSI_GVCIDR_VCID0              DSI_GVCIDR_VCID0_Msk

+#define DSI_GVCIDR_VCID1_Pos          (1U)

+#define DSI_GVCIDR_VCID1_Msk          (0x1UL << DSI_GVCIDR_VCID1_Pos)          /*!< 0x00000002 */

+#define DSI_GVCIDR_VCID1              DSI_GVCIDR_VCID1_Msk

+

+/*******************  Bit definition for DSI_MCR register  ****************/

+#define DSI_MCR_CMDM_Pos              (0U)

+#define DSI_MCR_CMDM_Msk              (0x1UL << DSI_MCR_CMDM_Pos)              /*!< 0x00000001 */

+#define DSI_MCR_CMDM                  DSI_MCR_CMDM_Msk                         /*!< Command Mode */

+

+/*******************  Bit definition for DSI_VMCR register  ***************/

+#define DSI_VMCR_VMT_Pos              (0U)

+#define DSI_VMCR_VMT_Msk              (0x3UL << DSI_VMCR_VMT_Pos)              /*!< 0x00000003 */

+#define DSI_VMCR_VMT                  DSI_VMCR_VMT_Msk                         /*!< Video Mode Type */

+#define DSI_VMCR_VMT0_Pos             (0U)

+#define DSI_VMCR_VMT0_Msk             (0x1UL << DSI_VMCR_VMT0_Pos)             /*!< 0x00000001 */

+#define DSI_VMCR_VMT0                 DSI_VMCR_VMT0_Msk

+#define DSI_VMCR_VMT1_Pos             (1U)

+#define DSI_VMCR_VMT1_Msk             (0x1UL << DSI_VMCR_VMT1_Pos)             /*!< 0x00000002 */

+#define DSI_VMCR_VMT1                 DSI_VMCR_VMT1_Msk

+

+#define DSI_VMCR_LPVSAE_Pos           (8U)

+#define DSI_VMCR_LPVSAE_Msk           (0x1UL << DSI_VMCR_LPVSAE_Pos)           /*!< 0x00000100 */

+#define DSI_VMCR_LPVSAE               DSI_VMCR_LPVSAE_Msk                      /*!< Low-Power Vertical Sync Active Enable */

+#define DSI_VMCR_LPVBPE_Pos           (9U)

+#define DSI_VMCR_LPVBPE_Msk           (0x1UL << DSI_VMCR_LPVBPE_Pos)           /*!< 0x00000200 */

+#define DSI_VMCR_LPVBPE               DSI_VMCR_LPVBPE_Msk                      /*!< Low-power Vertical Back-Porch Enable */

+#define DSI_VMCR_LPVFPE_Pos           (10U)

+#define DSI_VMCR_LPVFPE_Msk           (0x1UL << DSI_VMCR_LPVFPE_Pos)           /*!< 0x00000400 */

+#define DSI_VMCR_LPVFPE               DSI_VMCR_LPVFPE_Msk                      /*!< Low-power Vertical Front-porch Enable */

+#define DSI_VMCR_LPVAE_Pos            (11U)

+#define DSI_VMCR_LPVAE_Msk            (0x1UL << DSI_VMCR_LPVAE_Pos)            /*!< 0x00000800 */

+#define DSI_VMCR_LPVAE                DSI_VMCR_LPVAE_Msk                       /*!< Low-Power Vertical Active Enable */

+#define DSI_VMCR_LPHBPE_Pos           (12U)

+#define DSI_VMCR_LPHBPE_Msk           (0x1UL << DSI_VMCR_LPHBPE_Pos)           /*!< 0x00001000 */

+#define DSI_VMCR_LPHBPE               DSI_VMCR_LPHBPE_Msk                      /*!< Low-Power Horizontal Back-Porch Enable */

+#define DSI_VMCR_LPHFPE_Pos           (13U)

+#define DSI_VMCR_LPHFPE_Msk           (0x1UL << DSI_VMCR_LPHFPE_Pos)           /*!< 0x00002000 */

+#define DSI_VMCR_LPHFPE               DSI_VMCR_LPHFPE_Msk                      /*!< Low-Power Horizontal Front-Porch Enable */

+#define DSI_VMCR_FBTAAE_Pos           (14U)

+#define DSI_VMCR_FBTAAE_Msk           (0x1UL << DSI_VMCR_FBTAAE_Pos)           /*!< 0x00004000 */

+#define DSI_VMCR_FBTAAE               DSI_VMCR_FBTAAE_Msk                      /*!< Frame Bus-Turn-Around Acknowledge Enable */

+#define DSI_VMCR_LPCE_Pos             (15U)

+#define DSI_VMCR_LPCE_Msk             (0x1UL << DSI_VMCR_LPCE_Pos)             /*!< 0x00008000 */

+#define DSI_VMCR_LPCE                 DSI_VMCR_LPCE_Msk                        /*!< Low-Power Command Enable */

+#define DSI_VMCR_PGE_Pos              (16U)

+#define DSI_VMCR_PGE_Msk              (0x1UL << DSI_VMCR_PGE_Pos)              /*!< 0x00010000 */

+#define DSI_VMCR_PGE                  DSI_VMCR_PGE_Msk                         /*!< Pattern Generator Enable */

+#define DSI_VMCR_PGM_Pos              (20U)

+#define DSI_VMCR_PGM_Msk              (0x1UL << DSI_VMCR_PGM_Pos)              /*!< 0x00100000 */

+#define DSI_VMCR_PGM                  DSI_VMCR_PGM_Msk                         /*!< Pattern Generator Mode */

+#define DSI_VMCR_PGO_Pos              (24U)

+#define DSI_VMCR_PGO_Msk              (0x1UL << DSI_VMCR_PGO_Pos)              /*!< 0x01000000 */

+#define DSI_VMCR_PGO                  DSI_VMCR_PGO_Msk                         /*!< Pattern Generator Orientation */

+

+/*******************  Bit definition for DSI_VPCR register  ***************/

+#define DSI_VPCR_VPSIZE_Pos           (0U)

+#define DSI_VPCR_VPSIZE_Msk           (0x3FFFUL << DSI_VPCR_VPSIZE_Pos)        /*!< 0x00003FFF */

+#define DSI_VPCR_VPSIZE               DSI_VPCR_VPSIZE_Msk                      /*!< Video Packet Size */

+#define DSI_VPCR_VPSIZE0_Pos          (0U)

+#define DSI_VPCR_VPSIZE0_Msk          (0x1UL << DSI_VPCR_VPSIZE0_Pos)          /*!< 0x00000001 */

+#define DSI_VPCR_VPSIZE0              DSI_VPCR_VPSIZE0_Msk

+#define DSI_VPCR_VPSIZE1_Pos          (1U)

+#define DSI_VPCR_VPSIZE1_Msk          (0x1UL << DSI_VPCR_VPSIZE1_Pos)          /*!< 0x00000002 */

+#define DSI_VPCR_VPSIZE1              DSI_VPCR_VPSIZE1_Msk

+#define DSI_VPCR_VPSIZE2_Pos          (2U)

+#define DSI_VPCR_VPSIZE2_Msk          (0x1UL << DSI_VPCR_VPSIZE2_Pos)          /*!< 0x00000004 */

+#define DSI_VPCR_VPSIZE2              DSI_VPCR_VPSIZE2_Msk

+#define DSI_VPCR_VPSIZE3_Pos          (3U)

+#define DSI_VPCR_VPSIZE3_Msk          (0x1UL << DSI_VPCR_VPSIZE3_Pos)          /*!< 0x00000008 */

+#define DSI_VPCR_VPSIZE3              DSI_VPCR_VPSIZE3_Msk

+#define DSI_VPCR_VPSIZE4_Pos          (4U)

+#define DSI_VPCR_VPSIZE4_Msk          (0x1UL << DSI_VPCR_VPSIZE4_Pos)          /*!< 0x00000010 */

+#define DSI_VPCR_VPSIZE4              DSI_VPCR_VPSIZE4_Msk

+#define DSI_VPCR_VPSIZE5_Pos          (5U)

+#define DSI_VPCR_VPSIZE5_Msk          (0x1UL << DSI_VPCR_VPSIZE5_Pos)          /*!< 0x00000020 */

+#define DSI_VPCR_VPSIZE5              DSI_VPCR_VPSIZE5_Msk

+#define DSI_VPCR_VPSIZE6_Pos          (6U)

+#define DSI_VPCR_VPSIZE6_Msk          (0x1UL << DSI_VPCR_VPSIZE6_Pos)          /*!< 0x00000040 */

+#define DSI_VPCR_VPSIZE6              DSI_VPCR_VPSIZE6_Msk

+#define DSI_VPCR_VPSIZE7_Pos          (7U)

+#define DSI_VPCR_VPSIZE7_Msk          (0x1UL << DSI_VPCR_VPSIZE7_Pos)          /*!< 0x00000080 */

+#define DSI_VPCR_VPSIZE7              DSI_VPCR_VPSIZE7_Msk

+#define DSI_VPCR_VPSIZE8_Pos          (8U)

+#define DSI_VPCR_VPSIZE8_Msk          (0x1UL << DSI_VPCR_VPSIZE8_Pos)          /*!< 0x00000100 */

+#define DSI_VPCR_VPSIZE8              DSI_VPCR_VPSIZE8_Msk

+#define DSI_VPCR_VPSIZE9_Pos          (9U)

+#define DSI_VPCR_VPSIZE9_Msk          (0x1UL << DSI_VPCR_VPSIZE9_Pos)          /*!< 0x00000200 */

+#define DSI_VPCR_VPSIZE9              DSI_VPCR_VPSIZE9_Msk

+#define DSI_VPCR_VPSIZE10_Pos         (10U)

+#define DSI_VPCR_VPSIZE10_Msk         (0x1UL << DSI_VPCR_VPSIZE10_Pos)         /*!< 0x00000400 */

+#define DSI_VPCR_VPSIZE10             DSI_VPCR_VPSIZE10_Msk

+#define DSI_VPCR_VPSIZE11_Pos         (11U)

+#define DSI_VPCR_VPSIZE11_Msk         (0x1UL << DSI_VPCR_VPSIZE11_Pos)         /*!< 0x00000800 */

+#define DSI_VPCR_VPSIZE11             DSI_VPCR_VPSIZE11_Msk

+#define DSI_VPCR_VPSIZE12_Pos         (12U)

+#define DSI_VPCR_VPSIZE12_Msk         (0x1UL << DSI_VPCR_VPSIZE12_Pos)         /*!< 0x00001000 */

+#define DSI_VPCR_VPSIZE12             DSI_VPCR_VPSIZE12_Msk

+#define DSI_VPCR_VPSIZE13_Pos         (13U)

+#define DSI_VPCR_VPSIZE13_Msk         (0x1UL << DSI_VPCR_VPSIZE13_Pos)         /*!< 0x00002000 */

+#define DSI_VPCR_VPSIZE13             DSI_VPCR_VPSIZE13_Msk

+

+/*******************  Bit definition for DSI_VCCR register  ***************/

+#define DSI_VCCR_NUMC_Pos             (0U)

+#define DSI_VCCR_NUMC_Msk             (0x1FFFUL << DSI_VCCR_NUMC_Pos)          /*!< 0x00001FFF */

+#define DSI_VCCR_NUMC                 DSI_VCCR_NUMC_Msk                        /*!< Number of Chunks */

+#define DSI_VCCR_NUMC0_Pos            (0U)

+#define DSI_VCCR_NUMC0_Msk            (0x1UL << DSI_VCCR_NUMC0_Pos)            /*!< 0x00000001 */

+#define DSI_VCCR_NUMC0                DSI_VCCR_NUMC0_Msk

+#define DSI_VCCR_NUMC1_Pos            (1U)

+#define DSI_VCCR_NUMC1_Msk            (0x1UL << DSI_VCCR_NUMC1_Pos)            /*!< 0x00000002 */

+#define DSI_VCCR_NUMC1                DSI_VCCR_NUMC1_Msk

+#define DSI_VCCR_NUMC2_Pos            (2U)

+#define DSI_VCCR_NUMC2_Msk            (0x1UL << DSI_VCCR_NUMC2_Pos)            /*!< 0x00000004 */

+#define DSI_VCCR_NUMC2                DSI_VCCR_NUMC2_Msk

+#define DSI_VCCR_NUMC3_Pos            (3U)

+#define DSI_VCCR_NUMC3_Msk            (0x1UL << DSI_VCCR_NUMC3_Pos)            /*!< 0x00000008 */

+#define DSI_VCCR_NUMC3                DSI_VCCR_NUMC3_Msk

+#define DSI_VCCR_NUMC4_Pos            (4U)

+#define DSI_VCCR_NUMC4_Msk            (0x1UL << DSI_VCCR_NUMC4_Pos)            /*!< 0x00000010 */

+#define DSI_VCCR_NUMC4                DSI_VCCR_NUMC4_Msk

+#define DSI_VCCR_NUMC5_Pos            (5U)

+#define DSI_VCCR_NUMC5_Msk            (0x1UL << DSI_VCCR_NUMC5_Pos)            /*!< 0x00000020 */

+#define DSI_VCCR_NUMC5                DSI_VCCR_NUMC5_Msk

+#define DSI_VCCR_NUMC6_Pos            (6U)

+#define DSI_VCCR_NUMC6_Msk            (0x1UL << DSI_VCCR_NUMC6_Pos)            /*!< 0x00000040 */

+#define DSI_VCCR_NUMC6                DSI_VCCR_NUMC6_Msk

+#define DSI_VCCR_NUMC7_Pos            (7U)

+#define DSI_VCCR_NUMC7_Msk            (0x1UL << DSI_VCCR_NUMC7_Pos)            /*!< 0x00000080 */

+#define DSI_VCCR_NUMC7                DSI_VCCR_NUMC7_Msk

+#define DSI_VCCR_NUMC8_Pos            (8U)

+#define DSI_VCCR_NUMC8_Msk            (0x1UL << DSI_VCCR_NUMC8_Pos)            /*!< 0x00000100 */

+#define DSI_VCCR_NUMC8                DSI_VCCR_NUMC8_Msk

+#define DSI_VCCR_NUMC9_Pos            (9U)

+#define DSI_VCCR_NUMC9_Msk            (0x1UL << DSI_VCCR_NUMC9_Pos)            /*!< 0x00000200 */

+#define DSI_VCCR_NUMC9                DSI_VCCR_NUMC9_Msk

+#define DSI_VCCR_NUMC10_Pos           (10U)

+#define DSI_VCCR_NUMC10_Msk           (0x1UL << DSI_VCCR_NUMC10_Pos)           /*!< 0x00000400 */

+#define DSI_VCCR_NUMC10               DSI_VCCR_NUMC10_Msk

+#define DSI_VCCR_NUMC11_Pos           (11U)

+#define DSI_VCCR_NUMC11_Msk           (0x1UL << DSI_VCCR_NUMC11_Pos)           /*!< 0x00000800 */

+#define DSI_VCCR_NUMC11               DSI_VCCR_NUMC11_Msk

+#define DSI_VCCR_NUMC12_Pos           (12U)

+#define DSI_VCCR_NUMC12_Msk           (0x1UL << DSI_VCCR_NUMC12_Pos)           /*!< 0x00001000 */

+#define DSI_VCCR_NUMC12               DSI_VCCR_NUMC12_Msk

+

+/*******************  Bit definition for DSI_VNPCR register  **************/

+#define DSI_VNPCR_NPSIZE_Pos          (0U)

+#define DSI_VNPCR_NPSIZE_Msk          (0x1FFFUL << DSI_VNPCR_NPSIZE_Pos)       /*!< 0x00001FFF */

+#define DSI_VNPCR_NPSIZE              DSI_VNPCR_NPSIZE_Msk                     /*!< Null Packet Size */

+#define DSI_VNPCR_NPSIZE0_Pos         (0U)

+#define DSI_VNPCR_NPSIZE0_Msk         (0x1UL << DSI_VNPCR_NPSIZE0_Pos)         /*!< 0x00000001 */

+#define DSI_VNPCR_NPSIZE0             DSI_VNPCR_NPSIZE0_Msk

+#define DSI_VNPCR_NPSIZE1_Pos         (1U)

+#define DSI_VNPCR_NPSIZE1_Msk         (0x1UL << DSI_VNPCR_NPSIZE1_Pos)         /*!< 0x00000002 */

+#define DSI_VNPCR_NPSIZE1             DSI_VNPCR_NPSIZE1_Msk

+#define DSI_VNPCR_NPSIZE2_Pos         (2U)

+#define DSI_VNPCR_NPSIZE2_Msk         (0x1UL << DSI_VNPCR_NPSIZE2_Pos)         /*!< 0x00000004 */

+#define DSI_VNPCR_NPSIZE2             DSI_VNPCR_NPSIZE2_Msk

+#define DSI_VNPCR_NPSIZE3_Pos         (3U)

+#define DSI_VNPCR_NPSIZE3_Msk         (0x1UL << DSI_VNPCR_NPSIZE3_Pos)         /*!< 0x00000008 */

+#define DSI_VNPCR_NPSIZE3             DSI_VNPCR_NPSIZE3_Msk

+#define DSI_VNPCR_NPSIZE4_Pos         (4U)

+#define DSI_VNPCR_NPSIZE4_Msk         (0x1UL << DSI_VNPCR_NPSIZE4_Pos)         /*!< 0x00000010 */

+#define DSI_VNPCR_NPSIZE4             DSI_VNPCR_NPSIZE4_Msk

+#define DSI_VNPCR_NPSIZE5_Pos         (5U)

+#define DSI_VNPCR_NPSIZE5_Msk         (0x1UL << DSI_VNPCR_NPSIZE5_Pos)         /*!< 0x00000020 */

+#define DSI_VNPCR_NPSIZE5             DSI_VNPCR_NPSIZE5_Msk

+#define DSI_VNPCR_NPSIZE6_Pos         (6U)

+#define DSI_VNPCR_NPSIZE6_Msk         (0x1UL << DSI_VNPCR_NPSIZE6_Pos)         /*!< 0x00000040 */

+#define DSI_VNPCR_NPSIZE6             DSI_VNPCR_NPSIZE6_Msk

+#define DSI_VNPCR_NPSIZE7_Pos         (7U)

+#define DSI_VNPCR_NPSIZE7_Msk         (0x1UL << DSI_VNPCR_NPSIZE7_Pos)         /*!< 0x00000080 */

+#define DSI_VNPCR_NPSIZE7             DSI_VNPCR_NPSIZE7_Msk

+#define DSI_VNPCR_NPSIZE8_Pos         (8U)

+#define DSI_VNPCR_NPSIZE8_Msk         (0x1UL << DSI_VNPCR_NPSIZE8_Pos)         /*!< 0x00000100 */

+#define DSI_VNPCR_NPSIZE8             DSI_VNPCR_NPSIZE8_Msk

+#define DSI_VNPCR_NPSIZE9_Pos         (9U)

+#define DSI_VNPCR_NPSIZE9_Msk         (0x1UL << DSI_VNPCR_NPSIZE9_Pos)         /*!< 0x00000200 */

+#define DSI_VNPCR_NPSIZE9             DSI_VNPCR_NPSIZE9_Msk

+#define DSI_VNPCR_NPSIZE10_Pos        (10U)

+#define DSI_VNPCR_NPSIZE10_Msk        (0x1UL << DSI_VNPCR_NPSIZE10_Pos)        /*!< 0x00000400 */

+#define DSI_VNPCR_NPSIZE10            DSI_VNPCR_NPSIZE10_Msk

+#define DSI_VNPCR_NPSIZE11_Pos        (11U)

+#define DSI_VNPCR_NPSIZE11_Msk        (0x1UL << DSI_VNPCR_NPSIZE11_Pos)        /*!< 0x00000800 */

+#define DSI_VNPCR_NPSIZE11            DSI_VNPCR_NPSIZE11_Msk

+#define DSI_VNPCR_NPSIZE12_Pos        (12U)

+#define DSI_VNPCR_NPSIZE12_Msk        (0x1UL << DSI_VNPCR_NPSIZE12_Pos)        /*!< 0x00001000 */

+#define DSI_VNPCR_NPSIZE12            DSI_VNPCR_NPSIZE12_Msk

+

+/*******************  Bit definition for DSI_VHSACR register  *************/

+#define DSI_VHSACR_HSA_Pos            (0U)

+#define DSI_VHSACR_HSA_Msk            (0xFFFUL << DSI_VHSACR_HSA_Pos)          /*!< 0x00000FFF */

+#define DSI_VHSACR_HSA                DSI_VHSACR_HSA_Msk                       /*!< Horizontal Synchronism Active duration */

+#define DSI_VHSACR_HSA0_Pos           (0U)

+#define DSI_VHSACR_HSA0_Msk           (0x1UL << DSI_VHSACR_HSA0_Pos)           /*!< 0x00000001 */

+#define DSI_VHSACR_HSA0               DSI_VHSACR_HSA0_Msk

+#define DSI_VHSACR_HSA1_Pos           (1U)

+#define DSI_VHSACR_HSA1_Msk           (0x1UL << DSI_VHSACR_HSA1_Pos)           /*!< 0x00000002 */

+#define DSI_VHSACR_HSA1               DSI_VHSACR_HSA1_Msk

+#define DSI_VHSACR_HSA2_Pos           (2U)

+#define DSI_VHSACR_HSA2_Msk           (0x1UL << DSI_VHSACR_HSA2_Pos)           /*!< 0x00000004 */

+#define DSI_VHSACR_HSA2               DSI_VHSACR_HSA2_Msk

+#define DSI_VHSACR_HSA3_Pos           (3U)

+#define DSI_VHSACR_HSA3_Msk           (0x1UL << DSI_VHSACR_HSA3_Pos)           /*!< 0x00000008 */

+#define DSI_VHSACR_HSA3               DSI_VHSACR_HSA3_Msk

+#define DSI_VHSACR_HSA4_Pos           (4U)

+#define DSI_VHSACR_HSA4_Msk           (0x1UL << DSI_VHSACR_HSA4_Pos)           /*!< 0x00000010 */

+#define DSI_VHSACR_HSA4               DSI_VHSACR_HSA4_Msk

+#define DSI_VHSACR_HSA5_Pos           (5U)

+#define DSI_VHSACR_HSA5_Msk           (0x1UL << DSI_VHSACR_HSA5_Pos)           /*!< 0x00000020 */

+#define DSI_VHSACR_HSA5               DSI_VHSACR_HSA5_Msk

+#define DSI_VHSACR_HSA6_Pos           (6U)

+#define DSI_VHSACR_HSA6_Msk           (0x1UL << DSI_VHSACR_HSA6_Pos)           /*!< 0x00000040 */

+#define DSI_VHSACR_HSA6               DSI_VHSACR_HSA6_Msk

+#define DSI_VHSACR_HSA7_Pos           (7U)

+#define DSI_VHSACR_HSA7_Msk           (0x1UL << DSI_VHSACR_HSA7_Pos)           /*!< 0x00000080 */

+#define DSI_VHSACR_HSA7               DSI_VHSACR_HSA7_Msk

+#define DSI_VHSACR_HSA8_Pos           (8U)

+#define DSI_VHSACR_HSA8_Msk           (0x1UL << DSI_VHSACR_HSA8_Pos)           /*!< 0x00000100 */

+#define DSI_VHSACR_HSA8               DSI_VHSACR_HSA8_Msk

+#define DSI_VHSACR_HSA9_Pos           (9U)

+#define DSI_VHSACR_HSA9_Msk           (0x1UL << DSI_VHSACR_HSA9_Pos)           /*!< 0x00000200 */

+#define DSI_VHSACR_HSA9               DSI_VHSACR_HSA9_Msk

+#define DSI_VHSACR_HSA10_Pos          (10U)

+#define DSI_VHSACR_HSA10_Msk          (0x1UL << DSI_VHSACR_HSA10_Pos)          /*!< 0x00000400 */

+#define DSI_VHSACR_HSA10              DSI_VHSACR_HSA10_Msk

+#define DSI_VHSACR_HSA11_Pos          (11U)

+#define DSI_VHSACR_HSA11_Msk          (0x1UL << DSI_VHSACR_HSA11_Pos)          /*!< 0x00000800 */

+#define DSI_VHSACR_HSA11              DSI_VHSACR_HSA11_Msk

+

+/*******************  Bit definition for DSI_VHBPCR register  *************/

+#define DSI_VHBPCR_HBP_Pos            (0U)

+#define DSI_VHBPCR_HBP_Msk            (0xFFFUL << DSI_VHBPCR_HBP_Pos)          /*!< 0x00000FFF */

+#define DSI_VHBPCR_HBP                DSI_VHBPCR_HBP_Msk                       /*!< Horizontal Back-Porch duration */

+#define DSI_VHBPCR_HBP0_Pos           (0U)

+#define DSI_VHBPCR_HBP0_Msk           (0x1UL << DSI_VHBPCR_HBP0_Pos)           /*!< 0x00000001 */

+#define DSI_VHBPCR_HBP0               DSI_VHBPCR_HBP0_Msk

+#define DSI_VHBPCR_HBP1_Pos           (1U)

+#define DSI_VHBPCR_HBP1_Msk           (0x1UL << DSI_VHBPCR_HBP1_Pos)           /*!< 0x00000002 */

+#define DSI_VHBPCR_HBP1               DSI_VHBPCR_HBP1_Msk

+#define DSI_VHBPCR_HBP2_Pos           (2U)

+#define DSI_VHBPCR_HBP2_Msk           (0x1UL << DSI_VHBPCR_HBP2_Pos)           /*!< 0x00000004 */

+#define DSI_VHBPCR_HBP2               DSI_VHBPCR_HBP2_Msk

+#define DSI_VHBPCR_HBP3_Pos           (3U)

+#define DSI_VHBPCR_HBP3_Msk           (0x1UL << DSI_VHBPCR_HBP3_Pos)           /*!< 0x00000008 */

+#define DSI_VHBPCR_HBP3               DSI_VHBPCR_HBP3_Msk

+#define DSI_VHBPCR_HBP4_Pos           (4U)

+#define DSI_VHBPCR_HBP4_Msk           (0x1UL << DSI_VHBPCR_HBP4_Pos)           /*!< 0x00000010 */

+#define DSI_VHBPCR_HBP4               DSI_VHBPCR_HBP4_Msk

+#define DSI_VHBPCR_HBP5_Pos           (5U)

+#define DSI_VHBPCR_HBP5_Msk           (0x1UL << DSI_VHBPCR_HBP5_Pos)           /*!< 0x00000020 */

+#define DSI_VHBPCR_HBP5               DSI_VHBPCR_HBP5_Msk

+#define DSI_VHBPCR_HBP6_Pos           (6U)

+#define DSI_VHBPCR_HBP6_Msk           (0x1UL << DSI_VHBPCR_HBP6_Pos)           /*!< 0x00000040 */

+#define DSI_VHBPCR_HBP6               DSI_VHBPCR_HBP6_Msk

+#define DSI_VHBPCR_HBP7_Pos           (7U)

+#define DSI_VHBPCR_HBP7_Msk           (0x1UL << DSI_VHBPCR_HBP7_Pos)           /*!< 0x00000080 */

+#define DSI_VHBPCR_HBP7               DSI_VHBPCR_HBP7_Msk

+#define DSI_VHBPCR_HBP8_Pos           (8U)

+#define DSI_VHBPCR_HBP8_Msk           (0x1UL << DSI_VHBPCR_HBP8_Pos)           /*!< 0x00000100 */

+#define DSI_VHBPCR_HBP8               DSI_VHBPCR_HBP8_Msk

+#define DSI_VHBPCR_HBP9_Pos           (9U)

+#define DSI_VHBPCR_HBP9_Msk           (0x1UL << DSI_VHBPCR_HBP9_Pos)           /*!< 0x00000200 */

+#define DSI_VHBPCR_HBP9               DSI_VHBPCR_HBP9_Msk

+#define DSI_VHBPCR_HBP10_Pos          (10U)

+#define DSI_VHBPCR_HBP10_Msk          (0x1UL << DSI_VHBPCR_HBP10_Pos)          /*!< 0x00000400 */

+#define DSI_VHBPCR_HBP10              DSI_VHBPCR_HBP10_Msk

+#define DSI_VHBPCR_HBP11_Pos          (11U)

+#define DSI_VHBPCR_HBP11_Msk          (0x1UL << DSI_VHBPCR_HBP11_Pos)          /*!< 0x00000800 */

+#define DSI_VHBPCR_HBP11              DSI_VHBPCR_HBP11_Msk

+

+/*******************  Bit definition for DSI_VLCR register  ***************/

+#define DSI_VLCR_HLINE_Pos            (0U)

+#define DSI_VLCR_HLINE_Msk            (0x7FFFUL << DSI_VLCR_HLINE_Pos)         /*!< 0x00007FFF */

+#define DSI_VLCR_HLINE                DSI_VLCR_HLINE_Msk                       /*!< Horizontal Line duration */

+#define DSI_VLCR_HLINE0_Pos           (0U)

+#define DSI_VLCR_HLINE0_Msk           (0x1UL << DSI_VLCR_HLINE0_Pos)           /*!< 0x00000001 */

+#define DSI_VLCR_HLINE0               DSI_VLCR_HLINE0_Msk

+#define DSI_VLCR_HLINE1_Pos           (1U)

+#define DSI_VLCR_HLINE1_Msk           (0x1UL << DSI_VLCR_HLINE1_Pos)           /*!< 0x00000002 */

+#define DSI_VLCR_HLINE1               DSI_VLCR_HLINE1_Msk

+#define DSI_VLCR_HLINE2_Pos           (2U)

+#define DSI_VLCR_HLINE2_Msk           (0x1UL << DSI_VLCR_HLINE2_Pos)           /*!< 0x00000004 */

+#define DSI_VLCR_HLINE2               DSI_VLCR_HLINE2_Msk

+#define DSI_VLCR_HLINE3_Pos           (3U)

+#define DSI_VLCR_HLINE3_Msk           (0x1UL << DSI_VLCR_HLINE3_Pos)           /*!< 0x00000008 */

+#define DSI_VLCR_HLINE3               DSI_VLCR_HLINE3_Msk

+#define DSI_VLCR_HLINE4_Pos           (4U)

+#define DSI_VLCR_HLINE4_Msk           (0x1UL << DSI_VLCR_HLINE4_Pos)           /*!< 0x00000010 */

+#define DSI_VLCR_HLINE4               DSI_VLCR_HLINE4_Msk

+#define DSI_VLCR_HLINE5_Pos           (5U)

+#define DSI_VLCR_HLINE5_Msk           (0x1UL << DSI_VLCR_HLINE5_Pos)           /*!< 0x00000020 */

+#define DSI_VLCR_HLINE5               DSI_VLCR_HLINE5_Msk

+#define DSI_VLCR_HLINE6_Pos           (6U)

+#define DSI_VLCR_HLINE6_Msk           (0x1UL << DSI_VLCR_HLINE6_Pos)           /*!< 0x00000040 */

+#define DSI_VLCR_HLINE6               DSI_VLCR_HLINE6_Msk

+#define DSI_VLCR_HLINE7_Pos           (7U)

+#define DSI_VLCR_HLINE7_Msk           (0x1UL << DSI_VLCR_HLINE7_Pos)           /*!< 0x00000080 */

+#define DSI_VLCR_HLINE7               DSI_VLCR_HLINE7_Msk

+#define DSI_VLCR_HLINE8_Pos           (8U)

+#define DSI_VLCR_HLINE8_Msk           (0x1UL << DSI_VLCR_HLINE8_Pos)           /*!< 0x00000100 */

+#define DSI_VLCR_HLINE8               DSI_VLCR_HLINE8_Msk

+#define DSI_VLCR_HLINE9_Pos           (9U)

+#define DSI_VLCR_HLINE9_Msk           (0x1UL << DSI_VLCR_HLINE9_Pos)           /*!< 0x00000200 */

+#define DSI_VLCR_HLINE9               DSI_VLCR_HLINE9_Msk

+#define DSI_VLCR_HLINE10_Pos          (10U)

+#define DSI_VLCR_HLINE10_Msk          (0x1UL << DSI_VLCR_HLINE10_Pos)          /*!< 0x00000400 */

+#define DSI_VLCR_HLINE10              DSI_VLCR_HLINE10_Msk

+#define DSI_VLCR_HLINE11_Pos          (11U)

+#define DSI_VLCR_HLINE11_Msk          (0x1UL << DSI_VLCR_HLINE11_Pos)          /*!< 0x00000800 */

+#define DSI_VLCR_HLINE11              DSI_VLCR_HLINE11_Msk

+#define DSI_VLCR_HLINE12_Pos          (12U)

+#define DSI_VLCR_HLINE12_Msk          (0x1UL << DSI_VLCR_HLINE12_Pos)          /*!< 0x00001000 */

+#define DSI_VLCR_HLINE12              DSI_VLCR_HLINE12_Msk

+#define DSI_VLCR_HLINE13_Pos          (13U)

+#define DSI_VLCR_HLINE13_Msk          (0x1UL << DSI_VLCR_HLINE13_Pos)          /*!< 0x00002000 */

+#define DSI_VLCR_HLINE13              DSI_VLCR_HLINE13_Msk

+#define DSI_VLCR_HLINE14_Pos          (14U)

+#define DSI_VLCR_HLINE14_Msk          (0x1UL << DSI_VLCR_HLINE14_Pos)          /*!< 0x00004000 */

+#define DSI_VLCR_HLINE14              DSI_VLCR_HLINE14_Msk

+

+/*******************  Bit definition for DSI_VVSACR register  *************/

+#define DSI_VVSACR_VSA_Pos            (0U)

+#define DSI_VVSACR_VSA_Msk            (0x3FFUL << DSI_VVSACR_VSA_Pos)          /*!< 0x000003FF */

+#define DSI_VVSACR_VSA                DSI_VVSACR_VSA_Msk                       /*!< Vertical Synchronism Active duration */

+#define DSI_VVSACR_VSA0_Pos           (0U)

+#define DSI_VVSACR_VSA0_Msk           (0x1UL << DSI_VVSACR_VSA0_Pos)           /*!< 0x00000001 */

+#define DSI_VVSACR_VSA0               DSI_VVSACR_VSA0_Msk

+#define DSI_VVSACR_VSA1_Pos           (1U)

+#define DSI_VVSACR_VSA1_Msk           (0x1UL << DSI_VVSACR_VSA1_Pos)           /*!< 0x00000002 */

+#define DSI_VVSACR_VSA1               DSI_VVSACR_VSA1_Msk

+#define DSI_VVSACR_VSA2_Pos           (2U)

+#define DSI_VVSACR_VSA2_Msk           (0x1UL << DSI_VVSACR_VSA2_Pos)           /*!< 0x00000004 */

+#define DSI_VVSACR_VSA2               DSI_VVSACR_VSA2_Msk

+#define DSI_VVSACR_VSA3_Pos           (3U)

+#define DSI_VVSACR_VSA3_Msk           (0x1UL << DSI_VVSACR_VSA3_Pos)           /*!< 0x00000008 */

+#define DSI_VVSACR_VSA3               DSI_VVSACR_VSA3_Msk

+#define DSI_VVSACR_VSA4_Pos           (4U)

+#define DSI_VVSACR_VSA4_Msk           (0x1UL << DSI_VVSACR_VSA4_Pos)           /*!< 0x00000010 */

+#define DSI_VVSACR_VSA4               DSI_VVSACR_VSA4_Msk

+#define DSI_VVSACR_VSA5_Pos           (5U)

+#define DSI_VVSACR_VSA5_Msk           (0x1UL << DSI_VVSACR_VSA5_Pos)           /*!< 0x00000020 */

+#define DSI_VVSACR_VSA5               DSI_VVSACR_VSA5_Msk

+#define DSI_VVSACR_VSA6_Pos           (6U)

+#define DSI_VVSACR_VSA6_Msk           (0x1UL << DSI_VVSACR_VSA6_Pos)           /*!< 0x00000040 */

+#define DSI_VVSACR_VSA6               DSI_VVSACR_VSA6_Msk

+#define DSI_VVSACR_VSA7_Pos           (7U)

+#define DSI_VVSACR_VSA7_Msk           (0x1UL << DSI_VVSACR_VSA7_Pos)           /*!< 0x00000080 */

+#define DSI_VVSACR_VSA7               DSI_VVSACR_VSA7_Msk

+#define DSI_VVSACR_VSA8_Pos           (8U)

+#define DSI_VVSACR_VSA8_Msk           (0x1UL << DSI_VVSACR_VSA8_Pos)           /*!< 0x00000100 */

+#define DSI_VVSACR_VSA8               DSI_VVSACR_VSA8_Msk

+#define DSI_VVSACR_VSA9_Pos           (9U)

+#define DSI_VVSACR_VSA9_Msk           (0x1UL << DSI_VVSACR_VSA9_Pos)           /*!< 0x00000200 */

+#define DSI_VVSACR_VSA9               DSI_VVSACR_VSA9_Msk

+

+/*******************  Bit definition for DSI_VVBPCR register  *************/

+#define DSI_VVBPCR_VBP_Pos            (0U)

+#define DSI_VVBPCR_VBP_Msk            (0x3FFUL << DSI_VVBPCR_VBP_Pos)          /*!< 0x000003FF */

+#define DSI_VVBPCR_VBP                DSI_VVBPCR_VBP_Msk                       /*!< Vertical Back-Porch duration */

+#define DSI_VVBPCR_VBP0_Pos           (0U)

+#define DSI_VVBPCR_VBP0_Msk           (0x1UL << DSI_VVBPCR_VBP0_Pos)           /*!< 0x00000001 */

+#define DSI_VVBPCR_VBP0               DSI_VVBPCR_VBP0_Msk

+#define DSI_VVBPCR_VBP1_Pos           (1U)

+#define DSI_VVBPCR_VBP1_Msk           (0x1UL << DSI_VVBPCR_VBP1_Pos)           /*!< 0x00000002 */

+#define DSI_VVBPCR_VBP1               DSI_VVBPCR_VBP1_Msk

+#define DSI_VVBPCR_VBP2_Pos           (2U)

+#define DSI_VVBPCR_VBP2_Msk           (0x1UL << DSI_VVBPCR_VBP2_Pos)           /*!< 0x00000004 */

+#define DSI_VVBPCR_VBP2               DSI_VVBPCR_VBP2_Msk

+#define DSI_VVBPCR_VBP3_Pos           (3U)

+#define DSI_VVBPCR_VBP3_Msk           (0x1UL << DSI_VVBPCR_VBP3_Pos)           /*!< 0x00000008 */

+#define DSI_VVBPCR_VBP3               DSI_VVBPCR_VBP3_Msk

+#define DSI_VVBPCR_VBP4_Pos           (4U)

+#define DSI_VVBPCR_VBP4_Msk           (0x1UL << DSI_VVBPCR_VBP4_Pos)           /*!< 0x00000010 */

+#define DSI_VVBPCR_VBP4               DSI_VVBPCR_VBP4_Msk

+#define DSI_VVBPCR_VBP5_Pos           (5U)

+#define DSI_VVBPCR_VBP5_Msk           (0x1UL << DSI_VVBPCR_VBP5_Pos)           /*!< 0x00000020 */

+#define DSI_VVBPCR_VBP5               DSI_VVBPCR_VBP5_Msk

+#define DSI_VVBPCR_VBP6_Pos           (6U)

+#define DSI_VVBPCR_VBP6_Msk           (0x1UL << DSI_VVBPCR_VBP6_Pos)           /*!< 0x00000040 */

+#define DSI_VVBPCR_VBP6               DSI_VVBPCR_VBP6_Msk

+#define DSI_VVBPCR_VBP7_Pos           (7U)

+#define DSI_VVBPCR_VBP7_Msk           (0x1UL << DSI_VVBPCR_VBP7_Pos)           /*!< 0x00000080 */

+#define DSI_VVBPCR_VBP7               DSI_VVBPCR_VBP7_Msk

+#define DSI_VVBPCR_VBP8_Pos           (8U)

+#define DSI_VVBPCR_VBP8_Msk           (0x1UL << DSI_VVBPCR_VBP8_Pos)           /*!< 0x00000100 */

+#define DSI_VVBPCR_VBP8               DSI_VVBPCR_VBP8_Msk

+#define DSI_VVBPCR_VBP9_Pos           (9U)

+#define DSI_VVBPCR_VBP9_Msk           (0x1UL << DSI_VVBPCR_VBP9_Pos)           /*!< 0x00000200 */

+#define DSI_VVBPCR_VBP9               DSI_VVBPCR_VBP9_Msk

+

+/*******************  Bit definition for DSI_VVFPCR register  *************/

+#define DSI_VVFPCR_VFP_Pos            (0U)

+#define DSI_VVFPCR_VFP_Msk            (0x3FFUL << DSI_VVFPCR_VFP_Pos)          /*!< 0x000003FF */

+#define DSI_VVFPCR_VFP                DSI_VVFPCR_VFP_Msk                       /*!< Vertical Front-Porch duration */

+#define DSI_VVFPCR_VFP0_Pos           (0U)

+#define DSI_VVFPCR_VFP0_Msk           (0x1UL << DSI_VVFPCR_VFP0_Pos)           /*!< 0x00000001 */

+#define DSI_VVFPCR_VFP0               DSI_VVFPCR_VFP0_Msk

+#define DSI_VVFPCR_VFP1_Pos           (1U)

+#define DSI_VVFPCR_VFP1_Msk           (0x1UL << DSI_VVFPCR_VFP1_Pos)           /*!< 0x00000002 */

+#define DSI_VVFPCR_VFP1               DSI_VVFPCR_VFP1_Msk

+#define DSI_VVFPCR_VFP2_Pos           (2U)

+#define DSI_VVFPCR_VFP2_Msk           (0x1UL << DSI_VVFPCR_VFP2_Pos)           /*!< 0x00000004 */

+#define DSI_VVFPCR_VFP2               DSI_VVFPCR_VFP2_Msk

+#define DSI_VVFPCR_VFP3_Pos           (3U)

+#define DSI_VVFPCR_VFP3_Msk           (0x1UL << DSI_VVFPCR_VFP3_Pos)           /*!< 0x00000008 */

+#define DSI_VVFPCR_VFP3               DSI_VVFPCR_VFP3_Msk

+#define DSI_VVFPCR_VFP4_Pos           (4U)

+#define DSI_VVFPCR_VFP4_Msk           (0x1UL << DSI_VVFPCR_VFP4_Pos)           /*!< 0x00000010 */

+#define DSI_VVFPCR_VFP4               DSI_VVFPCR_VFP4_Msk

+#define DSI_VVFPCR_VFP5_Pos           (5U)

+#define DSI_VVFPCR_VFP5_Msk           (0x1UL << DSI_VVFPCR_VFP5_Pos)           /*!< 0x00000020 */

+#define DSI_VVFPCR_VFP5               DSI_VVFPCR_VFP5_Msk

+#define DSI_VVFPCR_VFP6_Pos           (6U)

+#define DSI_VVFPCR_VFP6_Msk           (0x1UL << DSI_VVFPCR_VFP6_Pos)           /*!< 0x00000040 */

+#define DSI_VVFPCR_VFP6               DSI_VVFPCR_VFP6_Msk

+#define DSI_VVFPCR_VFP7_Pos           (7U)

+#define DSI_VVFPCR_VFP7_Msk           (0x1UL << DSI_VVFPCR_VFP7_Pos)           /*!< 0x00000080 */

+#define DSI_VVFPCR_VFP7               DSI_VVFPCR_VFP7_Msk

+#define DSI_VVFPCR_VFP8_Pos           (8U)

+#define DSI_VVFPCR_VFP8_Msk           (0x1UL << DSI_VVFPCR_VFP8_Pos)           /*!< 0x00000100 */

+#define DSI_VVFPCR_VFP8               DSI_VVFPCR_VFP8_Msk

+#define DSI_VVFPCR_VFP9_Pos           (9U)

+#define DSI_VVFPCR_VFP9_Msk           (0x1UL << DSI_VVFPCR_VFP9_Pos)           /*!< 0x00000200 */

+#define DSI_VVFPCR_VFP9               DSI_VVFPCR_VFP9_Msk

+

+/*******************  Bit definition for DSI_VVACR register  **************/

+#define DSI_VVACR_VA_Pos              (0U)

+#define DSI_VVACR_VA_Msk              (0x3FFFUL << DSI_VVACR_VA_Pos)           /*!< 0x00003FFF */

+#define DSI_VVACR_VA                  DSI_VVACR_VA_Msk                         /*!< Vertical Active duration */

+#define DSI_VVACR_VA0_Pos             (0U)

+#define DSI_VVACR_VA0_Msk             (0x1UL << DSI_VVACR_VA0_Pos)             /*!< 0x00000001 */

+#define DSI_VVACR_VA0                 DSI_VVACR_VA0_Msk

+#define DSI_VVACR_VA1_Pos             (1U)

+#define DSI_VVACR_VA1_Msk             (0x1UL << DSI_VVACR_VA1_Pos)             /*!< 0x00000002 */

+#define DSI_VVACR_VA1                 DSI_VVACR_VA1_Msk

+#define DSI_VVACR_VA2_Pos             (2U)

+#define DSI_VVACR_VA2_Msk             (0x1UL << DSI_VVACR_VA2_Pos)             /*!< 0x00000004 */

+#define DSI_VVACR_VA2                 DSI_VVACR_VA2_Msk

+#define DSI_VVACR_VA3_Pos             (3U)

+#define DSI_VVACR_VA3_Msk             (0x1UL << DSI_VVACR_VA3_Pos)             /*!< 0x00000008 */

+#define DSI_VVACR_VA3                 DSI_VVACR_VA3_Msk

+#define DSI_VVACR_VA4_Pos             (4U)

+#define DSI_VVACR_VA4_Msk             (0x1UL << DSI_VVACR_VA4_Pos)             /*!< 0x00000010 */

+#define DSI_VVACR_VA4                 DSI_VVACR_VA4_Msk

+#define DSI_VVACR_VA5_Pos             (5U)

+#define DSI_VVACR_VA5_Msk             (0x1UL << DSI_VVACR_VA5_Pos)             /*!< 0x00000020 */

+#define DSI_VVACR_VA5                 DSI_VVACR_VA5_Msk

+#define DSI_VVACR_VA6_Pos             (6U)

+#define DSI_VVACR_VA6_Msk             (0x1UL << DSI_VVACR_VA6_Pos)             /*!< 0x00000040 */

+#define DSI_VVACR_VA6                 DSI_VVACR_VA6_Msk

+#define DSI_VVACR_VA7_Pos             (7U)

+#define DSI_VVACR_VA7_Msk             (0x1UL << DSI_VVACR_VA7_Pos)             /*!< 0x00000080 */

+#define DSI_VVACR_VA7                 DSI_VVACR_VA7_Msk

+#define DSI_VVACR_VA8_Pos             (8U)

+#define DSI_VVACR_VA8_Msk             (0x1UL << DSI_VVACR_VA8_Pos)             /*!< 0x00000100 */

+#define DSI_VVACR_VA8                 DSI_VVACR_VA8_Msk

+#define DSI_VVACR_VA9_Pos             (9U)

+#define DSI_VVACR_VA9_Msk             (0x1UL << DSI_VVACR_VA9_Pos)             /*!< 0x00000200 */

+#define DSI_VVACR_VA9                 DSI_VVACR_VA9_Msk

+#define DSI_VVACR_VA10_Pos            (10U)

+#define DSI_VVACR_VA10_Msk            (0x1UL << DSI_VVACR_VA10_Pos)            /*!< 0x00000400 */

+#define DSI_VVACR_VA10                DSI_VVACR_VA10_Msk

+#define DSI_VVACR_VA11_Pos            (11U)

+#define DSI_VVACR_VA11_Msk            (0x1UL << DSI_VVACR_VA11_Pos)            /*!< 0x00000800 */

+#define DSI_VVACR_VA11                DSI_VVACR_VA11_Msk

+#define DSI_VVACR_VA12_Pos            (12U)

+#define DSI_VVACR_VA12_Msk            (0x1UL << DSI_VVACR_VA12_Pos)            /*!< 0x00001000 */

+#define DSI_VVACR_VA12                DSI_VVACR_VA12_Msk

+#define DSI_VVACR_VA13_Pos            (13U)

+#define DSI_VVACR_VA13_Msk            (0x1UL << DSI_VVACR_VA13_Pos)            /*!< 0x00002000 */

+#define DSI_VVACR_VA13                DSI_VVACR_VA13_Msk

+

+/*******************  Bit definition for DSI_LCCR register  ***************/

+#define DSI_LCCR_CMDSIZE_Pos          (0U)

+#define DSI_LCCR_CMDSIZE_Msk          (0xFFFFUL << DSI_LCCR_CMDSIZE_Pos)       /*!< 0x0000FFFF */

+#define DSI_LCCR_CMDSIZE              DSI_LCCR_CMDSIZE_Msk                     /*!< Command Size */

+#define DSI_LCCR_CMDSIZE0_Pos         (0U)

+#define DSI_LCCR_CMDSIZE0_Msk         (0x1UL << DSI_LCCR_CMDSIZE0_Pos)         /*!< 0x00000001 */

+#define DSI_LCCR_CMDSIZE0             DSI_LCCR_CMDSIZE0_Msk

+#define DSI_LCCR_CMDSIZE1_Pos         (1U)

+#define DSI_LCCR_CMDSIZE1_Msk         (0x1UL << DSI_LCCR_CMDSIZE1_Pos)         /*!< 0x00000002 */

+#define DSI_LCCR_CMDSIZE1             DSI_LCCR_CMDSIZE1_Msk

+#define DSI_LCCR_CMDSIZE2_Pos         (2U)

+#define DSI_LCCR_CMDSIZE2_Msk         (0x1UL << DSI_LCCR_CMDSIZE2_Pos)         /*!< 0x00000004 */

+#define DSI_LCCR_CMDSIZE2             DSI_LCCR_CMDSIZE2_Msk

+#define DSI_LCCR_CMDSIZE3_Pos         (3U)

+#define DSI_LCCR_CMDSIZE3_Msk         (0x1UL << DSI_LCCR_CMDSIZE3_Pos)         /*!< 0x00000008 */

+#define DSI_LCCR_CMDSIZE3             DSI_LCCR_CMDSIZE3_Msk

+#define DSI_LCCR_CMDSIZE4_Pos         (4U)

+#define DSI_LCCR_CMDSIZE4_Msk         (0x1UL << DSI_LCCR_CMDSIZE4_Pos)         /*!< 0x00000010 */

+#define DSI_LCCR_CMDSIZE4             DSI_LCCR_CMDSIZE4_Msk

+#define DSI_LCCR_CMDSIZE5_Pos         (5U)

+#define DSI_LCCR_CMDSIZE5_Msk         (0x1UL << DSI_LCCR_CMDSIZE5_Pos)         /*!< 0x00000020 */

+#define DSI_LCCR_CMDSIZE5             DSI_LCCR_CMDSIZE5_Msk

+#define DSI_LCCR_CMDSIZE6_Pos         (6U)

+#define DSI_LCCR_CMDSIZE6_Msk         (0x1UL << DSI_LCCR_CMDSIZE6_Pos)         /*!< 0x00000040 */

+#define DSI_LCCR_CMDSIZE6             DSI_LCCR_CMDSIZE6_Msk

+#define DSI_LCCR_CMDSIZE7_Pos         (7U)

+#define DSI_LCCR_CMDSIZE7_Msk         (0x1UL << DSI_LCCR_CMDSIZE7_Pos)         /*!< 0x00000080 */

+#define DSI_LCCR_CMDSIZE7             DSI_LCCR_CMDSIZE7_Msk

+#define DSI_LCCR_CMDSIZE8_Pos         (8U)

+#define DSI_LCCR_CMDSIZE8_Msk         (0x1UL << DSI_LCCR_CMDSIZE8_Pos)         /*!< 0x00000100 */

+#define DSI_LCCR_CMDSIZE8             DSI_LCCR_CMDSIZE8_Msk

+#define DSI_LCCR_CMDSIZE9_Pos         (9U)

+#define DSI_LCCR_CMDSIZE9_Msk         (0x1UL << DSI_LCCR_CMDSIZE9_Pos)         /*!< 0x00000200 */

+#define DSI_LCCR_CMDSIZE9             DSI_LCCR_CMDSIZE9_Msk

+#define DSI_LCCR_CMDSIZE10_Pos        (10U)

+#define DSI_LCCR_CMDSIZE10_Msk        (0x1UL << DSI_LCCR_CMDSIZE10_Pos)        /*!< 0x00000400 */

+#define DSI_LCCR_CMDSIZE10            DSI_LCCR_CMDSIZE10_Msk

+#define DSI_LCCR_CMDSIZE11_Pos        (11U)

+#define DSI_LCCR_CMDSIZE11_Msk        (0x1UL << DSI_LCCR_CMDSIZE11_Pos)        /*!< 0x00000800 */

+#define DSI_LCCR_CMDSIZE11            DSI_LCCR_CMDSIZE11_Msk

+#define DSI_LCCR_CMDSIZE12_Pos        (12U)

+#define DSI_LCCR_CMDSIZE12_Msk        (0x1UL << DSI_LCCR_CMDSIZE12_Pos)        /*!< 0x00001000 */

+#define DSI_LCCR_CMDSIZE12            DSI_LCCR_CMDSIZE12_Msk

+#define DSI_LCCR_CMDSIZE13_Pos        (13U)

+#define DSI_LCCR_CMDSIZE13_Msk        (0x1UL << DSI_LCCR_CMDSIZE13_Pos)        /*!< 0x00002000 */

+#define DSI_LCCR_CMDSIZE13            DSI_LCCR_CMDSIZE13_Msk

+#define DSI_LCCR_CMDSIZE14_Pos        (14U)

+#define DSI_LCCR_CMDSIZE14_Msk        (0x1UL << DSI_LCCR_CMDSIZE14_Pos)        /*!< 0x00004000 */

+#define DSI_LCCR_CMDSIZE14            DSI_LCCR_CMDSIZE14_Msk

+#define DSI_LCCR_CMDSIZE15_Pos        (15U)

+#define DSI_LCCR_CMDSIZE15_Msk        (0x1UL << DSI_LCCR_CMDSIZE15_Pos)        /*!< 0x00008000 */

+#define DSI_LCCR_CMDSIZE15            DSI_LCCR_CMDSIZE15_Msk

+

+/*******************  Bit definition for DSI_CMCR register  ***************/

+#define DSI_CMCR_TEARE_Pos            (0U)

+#define DSI_CMCR_TEARE_Msk            (0x1UL << DSI_CMCR_TEARE_Pos)            /*!< 0x00000001 */

+#define DSI_CMCR_TEARE                DSI_CMCR_TEARE_Msk                       /*!< Tearing Effect Acknowledge Request Enable */

+#define DSI_CMCR_ARE_Pos              (1U)

+#define DSI_CMCR_ARE_Msk              (0x1UL << DSI_CMCR_ARE_Pos)              /*!< 0x00000002 */

+#define DSI_CMCR_ARE                  DSI_CMCR_ARE_Msk                         /*!< Acknowledge Request Enable */

+#define DSI_CMCR_GSW0TX_Pos           (8U)

+#define DSI_CMCR_GSW0TX_Msk           (0x1UL << DSI_CMCR_GSW0TX_Pos)           /*!< 0x00000100 */

+#define DSI_CMCR_GSW0TX               DSI_CMCR_GSW0TX_Msk                      /*!< Generic Short Write Zero parameters Transmission */

+#define DSI_CMCR_GSW1TX_Pos           (9U)

+#define DSI_CMCR_GSW1TX_Msk           (0x1UL << DSI_CMCR_GSW1TX_Pos)           /*!< 0x00000200 */

+#define DSI_CMCR_GSW1TX               DSI_CMCR_GSW1TX_Msk                      /*!< Generic Short Write One parameters Transmission */

+#define DSI_CMCR_GSW2TX_Pos           (10U)

+#define DSI_CMCR_GSW2TX_Msk           (0x1UL << DSI_CMCR_GSW2TX_Pos)           /*!< 0x00000400 */

+#define DSI_CMCR_GSW2TX               DSI_CMCR_GSW2TX_Msk                      /*!< Generic Short Write Two parameters Transmission */

+#define DSI_CMCR_GSR0TX_Pos           (11U)

+#define DSI_CMCR_GSR0TX_Msk           (0x1UL << DSI_CMCR_GSR0TX_Pos)           /*!< 0x00000800 */

+#define DSI_CMCR_GSR0TX               DSI_CMCR_GSR0TX_Msk                      /*!< Generic Short Read Zero parameters Transmission */

+#define DSI_CMCR_GSR1TX_Pos           (12U)

+#define DSI_CMCR_GSR1TX_Msk           (0x1UL << DSI_CMCR_GSR1TX_Pos)           /*!< 0x00001000 */

+#define DSI_CMCR_GSR1TX               DSI_CMCR_GSR1TX_Msk                      /*!< Generic Short Read One parameters Transmission */

+#define DSI_CMCR_GSR2TX_Pos           (13U)

+#define DSI_CMCR_GSR2TX_Msk           (0x1UL << DSI_CMCR_GSR2TX_Pos)           /*!< 0x00002000 */

+#define DSI_CMCR_GSR2TX               DSI_CMCR_GSR2TX_Msk                      /*!< Generic Short Read Two parameters Transmission */

+#define DSI_CMCR_GLWTX_Pos            (14U)

+#define DSI_CMCR_GLWTX_Msk            (0x1UL << DSI_CMCR_GLWTX_Pos)            /*!< 0x00004000 */

+#define DSI_CMCR_GLWTX                DSI_CMCR_GLWTX_Msk                       /*!< Generic Long Write Transmission */

+#define DSI_CMCR_DSW0TX_Pos           (16U)

+#define DSI_CMCR_DSW0TX_Msk           (0x1UL << DSI_CMCR_DSW0TX_Pos)           /*!< 0x00010000 */

+#define DSI_CMCR_DSW0TX               DSI_CMCR_DSW0TX_Msk                      /*!< DCS Short Write Zero parameter Transmission */

+#define DSI_CMCR_DSW1TX_Pos           (17U)

+#define DSI_CMCR_DSW1TX_Msk           (0x1UL << DSI_CMCR_DSW1TX_Pos)           /*!< 0x00020000 */

+#define DSI_CMCR_DSW1TX               DSI_CMCR_DSW1TX_Msk                      /*!< DCS Short Read One parameter Transmission */

+#define DSI_CMCR_DSR0TX_Pos           (18U)

+#define DSI_CMCR_DSR0TX_Msk           (0x1UL << DSI_CMCR_DSR0TX_Pos)           /*!< 0x00040000 */

+#define DSI_CMCR_DSR0TX               DSI_CMCR_DSR0TX_Msk                      /*!< DCS Short Read Zero parameter Transmission */

+#define DSI_CMCR_DLWTX_Pos            (19U)

+#define DSI_CMCR_DLWTX_Msk            (0x1UL << DSI_CMCR_DLWTX_Pos)            /*!< 0x00080000 */

+#define DSI_CMCR_DLWTX                DSI_CMCR_DLWTX_Msk                       /*!< DCS Long Write Transmission */

+#define DSI_CMCR_MRDPS_Pos            (24U)

+#define DSI_CMCR_MRDPS_Msk            (0x1UL << DSI_CMCR_MRDPS_Pos)            /*!< 0x01000000 */

+#define DSI_CMCR_MRDPS                DSI_CMCR_MRDPS_Msk                       /*!< Maximum Read Packet Size */

+

+/*******************  Bit definition for DSI_GHCR register  ***************/

+#define DSI_GHCR_DT_Pos               (0U)

+#define DSI_GHCR_DT_Msk               (0x3FUL << DSI_GHCR_DT_Pos)              /*!< 0x0000003F */

+#define DSI_GHCR_DT                   DSI_GHCR_DT_Msk                          /*!< Type */

+#define DSI_GHCR_DT0_Pos              (0U)

+#define DSI_GHCR_DT0_Msk              (0x1UL << DSI_GHCR_DT0_Pos)              /*!< 0x00000001 */

+#define DSI_GHCR_DT0                  DSI_GHCR_DT0_Msk

+#define DSI_GHCR_DT1_Pos              (1U)

+#define DSI_GHCR_DT1_Msk              (0x1UL << DSI_GHCR_DT1_Pos)              /*!< 0x00000002 */

+#define DSI_GHCR_DT1                  DSI_GHCR_DT1_Msk

+#define DSI_GHCR_DT2_Pos              (2U)

+#define DSI_GHCR_DT2_Msk              (0x1UL << DSI_GHCR_DT2_Pos)              /*!< 0x00000004 */

+#define DSI_GHCR_DT2                  DSI_GHCR_DT2_Msk

+#define DSI_GHCR_DT3_Pos              (3U)

+#define DSI_GHCR_DT3_Msk              (0x1UL << DSI_GHCR_DT3_Pos)              /*!< 0x00000008 */

+#define DSI_GHCR_DT3                  DSI_GHCR_DT3_Msk

+#define DSI_GHCR_DT4_Pos              (4U)

+#define DSI_GHCR_DT4_Msk              (0x1UL << DSI_GHCR_DT4_Pos)              /*!< 0x00000010 */

+#define DSI_GHCR_DT4                  DSI_GHCR_DT4_Msk

+#define DSI_GHCR_DT5_Pos              (5U)

+#define DSI_GHCR_DT5_Msk              (0x1UL << DSI_GHCR_DT5_Pos)              /*!< 0x00000020 */

+#define DSI_GHCR_DT5                  DSI_GHCR_DT5_Msk

+

+#define DSI_GHCR_VCID_Pos             (6U)

+#define DSI_GHCR_VCID_Msk             (0x3UL << DSI_GHCR_VCID_Pos)             /*!< 0x000000C0 */

+#define DSI_GHCR_VCID                 DSI_GHCR_VCID_Msk                        /*!< Channel */

+#define DSI_GHCR_VCID0_Pos            (6U)

+#define DSI_GHCR_VCID0_Msk            (0x1UL << DSI_GHCR_VCID0_Pos)            /*!< 0x00000040 */

+#define DSI_GHCR_VCID0                DSI_GHCR_VCID0_Msk

+#define DSI_GHCR_VCID1_Pos            (7U)

+#define DSI_GHCR_VCID1_Msk            (0x1UL << DSI_GHCR_VCID1_Pos)            /*!< 0x00000080 */

+#define DSI_GHCR_VCID1                DSI_GHCR_VCID1_Msk

+

+#define DSI_GHCR_WCLSB_Pos            (8U)

+#define DSI_GHCR_WCLSB_Msk            (0xFFUL << DSI_GHCR_WCLSB_Pos)           /*!< 0x0000FF00 */

+#define DSI_GHCR_WCLSB                DSI_GHCR_WCLSB_Msk                       /*!< WordCount LSB */

+#define DSI_GHCR_WCLSB0_Pos           (8U)

+#define DSI_GHCR_WCLSB0_Msk           (0x1UL << DSI_GHCR_WCLSB0_Pos)           /*!< 0x00000100 */

+#define DSI_GHCR_WCLSB0               DSI_GHCR_WCLSB0_Msk

+#define DSI_GHCR_WCLSB1_Pos           (9U)

+#define DSI_GHCR_WCLSB1_Msk           (0x1UL << DSI_GHCR_WCLSB1_Pos)           /*!< 0x00000200 */

+#define DSI_GHCR_WCLSB1               DSI_GHCR_WCLSB1_Msk

+#define DSI_GHCR_WCLSB2_Pos           (10U)

+#define DSI_GHCR_WCLSB2_Msk           (0x1UL << DSI_GHCR_WCLSB2_Pos)           /*!< 0x00000400 */

+#define DSI_GHCR_WCLSB2               DSI_GHCR_WCLSB2_Msk

+#define DSI_GHCR_WCLSB3_Pos           (11U)

+#define DSI_GHCR_WCLSB3_Msk           (0x1UL << DSI_GHCR_WCLSB3_Pos)           /*!< 0x00000800 */

+#define DSI_GHCR_WCLSB3               DSI_GHCR_WCLSB3_Msk

+#define DSI_GHCR_WCLSB4_Pos           (12U)

+#define DSI_GHCR_WCLSB4_Msk           (0x1UL << DSI_GHCR_WCLSB4_Pos)           /*!< 0x00001000 */

+#define DSI_GHCR_WCLSB4               DSI_GHCR_WCLSB4_Msk

+#define DSI_GHCR_WCLSB5_Pos           (13U)

+#define DSI_GHCR_WCLSB5_Msk           (0x1UL << DSI_GHCR_WCLSB5_Pos)           /*!< 0x00002000 */

+#define DSI_GHCR_WCLSB5               DSI_GHCR_WCLSB5_Msk

+#define DSI_GHCR_WCLSB6_Pos           (14U)

+#define DSI_GHCR_WCLSB6_Msk           (0x1UL << DSI_GHCR_WCLSB6_Pos)           /*!< 0x00004000 */

+#define DSI_GHCR_WCLSB6               DSI_GHCR_WCLSB6_Msk

+#define DSI_GHCR_WCLSB7_Pos           (15U)

+#define DSI_GHCR_WCLSB7_Msk           (0x1UL << DSI_GHCR_WCLSB7_Pos)           /*!< 0x00008000 */

+#define DSI_GHCR_WCLSB7               DSI_GHCR_WCLSB7_Msk

+

+#define DSI_GHCR_WCMSB_Pos            (16U)

+#define DSI_GHCR_WCMSB_Msk            (0xFFUL << DSI_GHCR_WCMSB_Pos)           /*!< 0x00FF0000 */

+#define DSI_GHCR_WCMSB                DSI_GHCR_WCMSB_Msk                       /*!< WordCount MSB */

+#define DSI_GHCR_WCMSB0_Pos           (16U)

+#define DSI_GHCR_WCMSB0_Msk           (0x1UL << DSI_GHCR_WCMSB0_Pos)           /*!< 0x00010000 */

+#define DSI_GHCR_WCMSB0               DSI_GHCR_WCMSB0_Msk

+#define DSI_GHCR_WCMSB1_Pos           (17U)

+#define DSI_GHCR_WCMSB1_Msk           (0x1UL << DSI_GHCR_WCMSB1_Pos)           /*!< 0x00020000 */

+#define DSI_GHCR_WCMSB1               DSI_GHCR_WCMSB1_Msk

+#define DSI_GHCR_WCMSB2_Pos           (18U)

+#define DSI_GHCR_WCMSB2_Msk           (0x1UL << DSI_GHCR_WCMSB2_Pos)           /*!< 0x00040000 */

+#define DSI_GHCR_WCMSB2               DSI_GHCR_WCMSB2_Msk

+#define DSI_GHCR_WCMSB3_Pos           (19U)

+#define DSI_GHCR_WCMSB3_Msk           (0x1UL << DSI_GHCR_WCMSB3_Pos)           /*!< 0x00080000 */

+#define DSI_GHCR_WCMSB3               DSI_GHCR_WCMSB3_Msk

+#define DSI_GHCR_WCMSB4_Pos           (20U)

+#define DSI_GHCR_WCMSB4_Msk           (0x1UL << DSI_GHCR_WCMSB4_Pos)           /*!< 0x00100000 */

+#define DSI_GHCR_WCMSB4               DSI_GHCR_WCMSB4_Msk

+#define DSI_GHCR_WCMSB5_Pos           (21U)

+#define DSI_GHCR_WCMSB5_Msk           (0x1UL << DSI_GHCR_WCMSB5_Pos)           /*!< 0x00200000 */

+#define DSI_GHCR_WCMSB5               DSI_GHCR_WCMSB5_Msk

+#define DSI_GHCR_WCMSB6_Pos           (22U)

+#define DSI_GHCR_WCMSB6_Msk           (0x1UL << DSI_GHCR_WCMSB6_Pos)           /*!< 0x00400000 */

+#define DSI_GHCR_WCMSB6               DSI_GHCR_WCMSB6_Msk

+#define DSI_GHCR_WCMSB7_Pos           (23U)

+#define DSI_GHCR_WCMSB7_Msk           (0x1UL << DSI_GHCR_WCMSB7_Pos)           /*!< 0x00800000 */

+#define DSI_GHCR_WCMSB7               DSI_GHCR_WCMSB7_Msk

+

+/*******************  Bit definition for DSI_GPDR register  ***************/

+#define DSI_GPDR_DATA1_Pos            (0U)

+#define DSI_GPDR_DATA1_Msk            (0xFFUL << DSI_GPDR_DATA1_Pos)           /*!< 0x000000FF */

+#define DSI_GPDR_DATA1                DSI_GPDR_DATA1_Msk                       /*!< Payload Byte 1 */

+#define DSI_GPDR_DATA1_0              (0x01UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000001 */

+#define DSI_GPDR_DATA1_1              (0x02UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000002 */

+#define DSI_GPDR_DATA1_2              (0x04UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000004 */

+#define DSI_GPDR_DATA1_3              (0x08UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000008 */

+#define DSI_GPDR_DATA1_4              (0x10UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000010 */

+#define DSI_GPDR_DATA1_5              (0x20UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000020 */

+#define DSI_GPDR_DATA1_6              (0x40UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000040 */

+#define DSI_GPDR_DATA1_7              (0x80UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000080 */

+

+#define DSI_GPDR_DATA2_Pos            (8U)

+#define DSI_GPDR_DATA2_Msk            (0xFFUL << DSI_GPDR_DATA2_Pos)           /*!< 0x0000FF00 */

+#define DSI_GPDR_DATA2                DSI_GPDR_DATA2_Msk                       /*!< Payload Byte 2 */

+#define DSI_GPDR_DATA2_0              (0x01UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00000100 */

+#define DSI_GPDR_DATA2_1              (0x02UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00000200 */

+#define DSI_GPDR_DATA2_2              (0x04UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00000400 */

+#define DSI_GPDR_DATA2_3              (0x08UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00000800 */

+#define DSI_GPDR_DATA2_4              (0x10UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00001000 */

+#define DSI_GPDR_DATA2_5              (0x20UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00002000 */

+#define DSI_GPDR_DATA2_6              (0x40UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00004000 */

+#define DSI_GPDR_DATA2_7              (0x80UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00008000 */

+

+#define DSI_GPDR_DATA3_Pos            (16U)

+#define DSI_GPDR_DATA3_Msk            (0xFFUL << DSI_GPDR_DATA3_Pos)           /*!< 0x00FF0000 */

+#define DSI_GPDR_DATA3                DSI_GPDR_DATA3_Msk                       /*!< Payload Byte 3 */

+#define DSI_GPDR_DATA3_0              (0x01UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00010000 */

+#define DSI_GPDR_DATA3_1              (0x02UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00020000 */

+#define DSI_GPDR_DATA3_2              (0x04UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00040000 */

+#define DSI_GPDR_DATA3_3              (0x08UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00080000 */

+#define DSI_GPDR_DATA3_4              (0x10UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00100000 */

+#define DSI_GPDR_DATA3_5              (0x20UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00200000 */

+#define DSI_GPDR_DATA3_6              (0x40UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00400000 */

+#define DSI_GPDR_DATA3_7              (0x80UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00800000 */

+

+#define DSI_GPDR_DATA4_Pos            (24U)

+#define DSI_GPDR_DATA4_Msk            (0xFFUL << DSI_GPDR_DATA4_Pos)           /*!< 0xFF000000 */

+#define DSI_GPDR_DATA4                DSI_GPDR_DATA4_Msk                       /*!< Payload Byte 4 */

+#define DSI_GPDR_DATA4_0              (0x01UL << DSI_GPDR_DATA4_Pos)            /*!< 0x01000000 */

+#define DSI_GPDR_DATA4_1              (0x02UL << DSI_GPDR_DATA4_Pos)            /*!< 0x02000000 */

+#define DSI_GPDR_DATA4_2              (0x04UL << DSI_GPDR_DATA4_Pos)            /*!< 0x04000000 */

+#define DSI_GPDR_DATA4_3              (0x08UL << DSI_GPDR_DATA4_Pos)            /*!< 0x08000000 */

+#define DSI_GPDR_DATA4_4              (0x10UL << DSI_GPDR_DATA4_Pos)            /*!< 0x10000000 */

+#define DSI_GPDR_DATA4_5              (0x20UL << DSI_GPDR_DATA4_Pos)            /*!< 0x20000000 */

+#define DSI_GPDR_DATA4_6              (0x40UL << DSI_GPDR_DATA4_Pos)            /*!< 0x40000000 */

+#define DSI_GPDR_DATA4_7              (0x80UL << DSI_GPDR_DATA4_Pos)            /*!< 0x80000000 */

+

+/*******************  Bit definition for DSI_GPSR register  ***************/

+#define DSI_GPSR_CMDFE_Pos            (0U)

+#define DSI_GPSR_CMDFE_Msk            (0x1UL << DSI_GPSR_CMDFE_Pos)            /*!< 0x00000001 */

+#define DSI_GPSR_CMDFE                DSI_GPSR_CMDFE_Msk                       /*!< Command FIFO Empty */

+#define DSI_GPSR_CMDFF_Pos            (1U)

+#define DSI_GPSR_CMDFF_Msk            (0x1UL << DSI_GPSR_CMDFF_Pos)            /*!< 0x00000002 */

+#define DSI_GPSR_CMDFF                DSI_GPSR_CMDFF_Msk                       /*!< Command FIFO Full */

+#define DSI_GPSR_PWRFE_Pos            (2U)

+#define DSI_GPSR_PWRFE_Msk            (0x1UL << DSI_GPSR_PWRFE_Pos)            /*!< 0x00000004 */

+#define DSI_GPSR_PWRFE                DSI_GPSR_PWRFE_Msk                       /*!< Payload Write FIFO Empty */

+#define DSI_GPSR_PWRFF_Pos            (3U)

+#define DSI_GPSR_PWRFF_Msk            (0x1UL << DSI_GPSR_PWRFF_Pos)            /*!< 0x00000008 */

+#define DSI_GPSR_PWRFF                DSI_GPSR_PWRFF_Msk                       /*!< Payload Write FIFO Full */

+#define DSI_GPSR_PRDFE_Pos            (4U)

+#define DSI_GPSR_PRDFE_Msk            (0x1UL << DSI_GPSR_PRDFE_Pos)            /*!< 0x00000010 */

+#define DSI_GPSR_PRDFE                DSI_GPSR_PRDFE_Msk                       /*!< Payload Read FIFO Empty */

+#define DSI_GPSR_PRDFF_Pos            (5U)

+#define DSI_GPSR_PRDFF_Msk            (0x1UL << DSI_GPSR_PRDFF_Pos)            /*!< 0x00000020 */

+#define DSI_GPSR_PRDFF                DSI_GPSR_PRDFF_Msk                       /*!< Payload Read FIFO Full */

+#define DSI_GPSR_RCB_Pos              (6U)

+#define DSI_GPSR_RCB_Msk              (0x1UL << DSI_GPSR_RCB_Pos)              /*!< 0x00000040 */

+#define DSI_GPSR_RCB                  DSI_GPSR_RCB_Msk                         /*!< Read Command Busy */

+

+/*******************  Bit definition for DSI_TCCR0 register  **************/

+#define DSI_TCCR0_LPRX_TOCNT_Pos      (0U)

+#define DSI_TCCR0_LPRX_TOCNT_Msk      (0xFFFFUL << DSI_TCCR0_LPRX_TOCNT_Pos)   /*!< 0x0000FFFF */

+#define DSI_TCCR0_LPRX_TOCNT          DSI_TCCR0_LPRX_TOCNT_Msk                 /*!< Low-power Reception Timeout Counter */

+#define DSI_TCCR0_LPRX_TOCNT0_Pos     (0U)

+#define DSI_TCCR0_LPRX_TOCNT0_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT0_Pos)     /*!< 0x00000001 */

+#define DSI_TCCR0_LPRX_TOCNT0         DSI_TCCR0_LPRX_TOCNT0_Msk

+#define DSI_TCCR0_LPRX_TOCNT1_Pos     (1U)

+#define DSI_TCCR0_LPRX_TOCNT1_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT1_Pos)     /*!< 0x00000002 */

+#define DSI_TCCR0_LPRX_TOCNT1         DSI_TCCR0_LPRX_TOCNT1_Msk

+#define DSI_TCCR0_LPRX_TOCNT2_Pos     (2U)

+#define DSI_TCCR0_LPRX_TOCNT2_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT2_Pos)     /*!< 0x00000004 */

+#define DSI_TCCR0_LPRX_TOCNT2         DSI_TCCR0_LPRX_TOCNT2_Msk

+#define DSI_TCCR0_LPRX_TOCNT3_Pos     (3U)

+#define DSI_TCCR0_LPRX_TOCNT3_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT3_Pos)     /*!< 0x00000008 */

+#define DSI_TCCR0_LPRX_TOCNT3         DSI_TCCR0_LPRX_TOCNT3_Msk

+#define DSI_TCCR0_LPRX_TOCNT4_Pos     (4U)

+#define DSI_TCCR0_LPRX_TOCNT4_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT4_Pos)     /*!< 0x00000010 */

+#define DSI_TCCR0_LPRX_TOCNT4         DSI_TCCR0_LPRX_TOCNT4_Msk

+#define DSI_TCCR0_LPRX_TOCNT5_Pos     (5U)

+#define DSI_TCCR0_LPRX_TOCNT5_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT5_Pos)     /*!< 0x00000020 */

+#define DSI_TCCR0_LPRX_TOCNT5         DSI_TCCR0_LPRX_TOCNT5_Msk

+#define DSI_TCCR0_LPRX_TOCNT6_Pos     (6U)

+#define DSI_TCCR0_LPRX_TOCNT6_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT6_Pos)     /*!< 0x00000040 */

+#define DSI_TCCR0_LPRX_TOCNT6         DSI_TCCR0_LPRX_TOCNT6_Msk

+#define DSI_TCCR0_LPRX_TOCNT7_Pos     (7U)

+#define DSI_TCCR0_LPRX_TOCNT7_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT7_Pos)     /*!< 0x00000080 */

+#define DSI_TCCR0_LPRX_TOCNT7         DSI_TCCR0_LPRX_TOCNT7_Msk

+#define DSI_TCCR0_LPRX_TOCNT8_Pos     (8U)

+#define DSI_TCCR0_LPRX_TOCNT8_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT8_Pos)     /*!< 0x00000100 */

+#define DSI_TCCR0_LPRX_TOCNT8         DSI_TCCR0_LPRX_TOCNT8_Msk

+#define DSI_TCCR0_LPRX_TOCNT9_Pos     (9U)

+#define DSI_TCCR0_LPRX_TOCNT9_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT9_Pos)     /*!< 0x00000200 */

+#define DSI_TCCR0_LPRX_TOCNT9         DSI_TCCR0_LPRX_TOCNT9_Msk

+#define DSI_TCCR0_LPRX_TOCNT10_Pos    (10U)

+#define DSI_TCCR0_LPRX_TOCNT10_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT10_Pos)    /*!< 0x00000400 */

+#define DSI_TCCR0_LPRX_TOCNT10        DSI_TCCR0_LPRX_TOCNT10_Msk

+#define DSI_TCCR0_LPRX_TOCNT11_Pos    (11U)

+#define DSI_TCCR0_LPRX_TOCNT11_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT11_Pos)    /*!< 0x00000800 */

+#define DSI_TCCR0_LPRX_TOCNT11        DSI_TCCR0_LPRX_TOCNT11_Msk

+#define DSI_TCCR0_LPRX_TOCNT12_Pos    (12U)

+#define DSI_TCCR0_LPRX_TOCNT12_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT12_Pos)    /*!< 0x00001000 */

+#define DSI_TCCR0_LPRX_TOCNT12        DSI_TCCR0_LPRX_TOCNT12_Msk

+#define DSI_TCCR0_LPRX_TOCNT13_Pos    (13U)

+#define DSI_TCCR0_LPRX_TOCNT13_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT13_Pos)    /*!< 0x00002000 */

+#define DSI_TCCR0_LPRX_TOCNT13        DSI_TCCR0_LPRX_TOCNT13_Msk

+#define DSI_TCCR0_LPRX_TOCNT14_Pos    (14U)

+#define DSI_TCCR0_LPRX_TOCNT14_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT14_Pos)    /*!< 0x00004000 */

+#define DSI_TCCR0_LPRX_TOCNT14        DSI_TCCR0_LPRX_TOCNT14_Msk

+#define DSI_TCCR0_LPRX_TOCNT15_Pos    (15U)

+#define DSI_TCCR0_LPRX_TOCNT15_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT15_Pos)    /*!< 0x00008000 */

+#define DSI_TCCR0_LPRX_TOCNT15        DSI_TCCR0_LPRX_TOCNT15_Msk

+

+#define DSI_TCCR0_HSTX_TOCNT_Pos      (16U)

+#define DSI_TCCR0_HSTX_TOCNT_Msk      (0xFFFFUL << DSI_TCCR0_HSTX_TOCNT_Pos)   /*!< 0xFFFF0000 */

+#define DSI_TCCR0_HSTX_TOCNT          DSI_TCCR0_HSTX_TOCNT_Msk                 /*!< High-Speed Transmission Timeout Counter */

+#define DSI_TCCR0_HSTX_TOCNT0_Pos     (16U)

+#define DSI_TCCR0_HSTX_TOCNT0_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT0_Pos)     /*!< 0x00010000 */

+#define DSI_TCCR0_HSTX_TOCNT0         DSI_TCCR0_HSTX_TOCNT0_Msk

+#define DSI_TCCR0_HSTX_TOCNT1_Pos     (17U)

+#define DSI_TCCR0_HSTX_TOCNT1_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT1_Pos)     /*!< 0x00020000 */

+#define DSI_TCCR0_HSTX_TOCNT1         DSI_TCCR0_HSTX_TOCNT1_Msk

+#define DSI_TCCR0_HSTX_TOCNT2_Pos     (18U)

+#define DSI_TCCR0_HSTX_TOCNT2_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT2_Pos)     /*!< 0x00040000 */

+#define DSI_TCCR0_HSTX_TOCNT2         DSI_TCCR0_HSTX_TOCNT2_Msk

+#define DSI_TCCR0_HSTX_TOCNT3_Pos     (19U)

+#define DSI_TCCR0_HSTX_TOCNT3_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT3_Pos)     /*!< 0x00080000 */

+#define DSI_TCCR0_HSTX_TOCNT3         DSI_TCCR0_HSTX_TOCNT3_Msk

+#define DSI_TCCR0_HSTX_TOCNT4_Pos     (20U)

+#define DSI_TCCR0_HSTX_TOCNT4_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT4_Pos)     /*!< 0x00100000 */

+#define DSI_TCCR0_HSTX_TOCNT4         DSI_TCCR0_HSTX_TOCNT4_Msk

+#define DSI_TCCR0_HSTX_TOCNT5_Pos     (21U)

+#define DSI_TCCR0_HSTX_TOCNT5_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT5_Pos)     /*!< 0x00200000 */

+#define DSI_TCCR0_HSTX_TOCNT5         DSI_TCCR0_HSTX_TOCNT5_Msk

+#define DSI_TCCR0_HSTX_TOCNT6_Pos     (22U)

+#define DSI_TCCR0_HSTX_TOCNT6_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT6_Pos)     /*!< 0x00400000 */

+#define DSI_TCCR0_HSTX_TOCNT6         DSI_TCCR0_HSTX_TOCNT6_Msk

+#define DSI_TCCR0_HSTX_TOCNT7_Pos     (23U)

+#define DSI_TCCR0_HSTX_TOCNT7_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT7_Pos)     /*!< 0x00800000 */

+#define DSI_TCCR0_HSTX_TOCNT7         DSI_TCCR0_HSTX_TOCNT7_Msk

+#define DSI_TCCR0_HSTX_TOCNT8_Pos     (24U)

+#define DSI_TCCR0_HSTX_TOCNT8_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT8_Pos)     /*!< 0x01000000 */

+#define DSI_TCCR0_HSTX_TOCNT8         DSI_TCCR0_HSTX_TOCNT8_Msk

+#define DSI_TCCR0_HSTX_TOCNT9_Pos     (25U)

+#define DSI_TCCR0_HSTX_TOCNT9_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT9_Pos)     /*!< 0x02000000 */

+#define DSI_TCCR0_HSTX_TOCNT9         DSI_TCCR0_HSTX_TOCNT9_Msk

+#define DSI_TCCR0_HSTX_TOCNT10_Pos    (26U)

+#define DSI_TCCR0_HSTX_TOCNT10_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT10_Pos)    /*!< 0x04000000 */

+#define DSI_TCCR0_HSTX_TOCNT10        DSI_TCCR0_HSTX_TOCNT10_Msk

+#define DSI_TCCR0_HSTX_TOCNT11_Pos    (27U)

+#define DSI_TCCR0_HSTX_TOCNT11_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT11_Pos)    /*!< 0x08000000 */

+#define DSI_TCCR0_HSTX_TOCNT11        DSI_TCCR0_HSTX_TOCNT11_Msk

+#define DSI_TCCR0_HSTX_TOCNT12_Pos    (28U)

+#define DSI_TCCR0_HSTX_TOCNT12_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT12_Pos)    /*!< 0x10000000 */

+#define DSI_TCCR0_HSTX_TOCNT12        DSI_TCCR0_HSTX_TOCNT12_Msk

+#define DSI_TCCR0_HSTX_TOCNT13_Pos    (29U)

+#define DSI_TCCR0_HSTX_TOCNT13_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT13_Pos)    /*!< 0x20000000 */

+#define DSI_TCCR0_HSTX_TOCNT13        DSI_TCCR0_HSTX_TOCNT13_Msk

+#define DSI_TCCR0_HSTX_TOCNT14_Pos    (30U)

+#define DSI_TCCR0_HSTX_TOCNT14_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT14_Pos)    /*!< 0x40000000 */

+#define DSI_TCCR0_HSTX_TOCNT14        DSI_TCCR0_HSTX_TOCNT14_Msk

+#define DSI_TCCR0_HSTX_TOCNT15_Pos    (31U)

+#define DSI_TCCR0_HSTX_TOCNT15_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT15_Pos)    /*!< 0x80000000 */

+#define DSI_TCCR0_HSTX_TOCNT15        DSI_TCCR0_HSTX_TOCNT15_Msk

+

+/*******************  Bit definition for DSI_TCCR1 register  **************/

+#define DSI_TCCR1_HSRD_TOCNT_Pos      (0U)

+#define DSI_TCCR1_HSRD_TOCNT_Msk      (0xFFFFUL << DSI_TCCR1_HSRD_TOCNT_Pos)   /*!< 0x0000FFFF */

+#define DSI_TCCR1_HSRD_TOCNT          DSI_TCCR1_HSRD_TOCNT_Msk                 /*!< High-Speed Read Timeout Counter */

+#define DSI_TCCR1_HSRD_TOCNT0_Pos     (0U)

+#define DSI_TCCR1_HSRD_TOCNT0_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT0_Pos)     /*!< 0x00000001 */

+#define DSI_TCCR1_HSRD_TOCNT0         DSI_TCCR1_HSRD_TOCNT0_Msk

+#define DSI_TCCR1_HSRD_TOCNT1_Pos     (1U)

+#define DSI_TCCR1_HSRD_TOCNT1_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT1_Pos)     /*!< 0x00000002 */

+#define DSI_TCCR1_HSRD_TOCNT1         DSI_TCCR1_HSRD_TOCNT1_Msk

+#define DSI_TCCR1_HSRD_TOCNT2_Pos     (2U)

+#define DSI_TCCR1_HSRD_TOCNT2_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT2_Pos)     /*!< 0x00000004 */

+#define DSI_TCCR1_HSRD_TOCNT2         DSI_TCCR1_HSRD_TOCNT2_Msk

+#define DSI_TCCR1_HSRD_TOCNT3_Pos     (3U)

+#define DSI_TCCR1_HSRD_TOCNT3_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT3_Pos)     /*!< 0x00000008 */

+#define DSI_TCCR1_HSRD_TOCNT3         DSI_TCCR1_HSRD_TOCNT3_Msk

+#define DSI_TCCR1_HSRD_TOCNT4_Pos     (4U)

+#define DSI_TCCR1_HSRD_TOCNT4_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT4_Pos)     /*!< 0x00000010 */

+#define DSI_TCCR1_HSRD_TOCNT4         DSI_TCCR1_HSRD_TOCNT4_Msk

+#define DSI_TCCR1_HSRD_TOCNT5_Pos     (5U)

+#define DSI_TCCR1_HSRD_TOCNT5_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT5_Pos)     /*!< 0x00000020 */

+#define DSI_TCCR1_HSRD_TOCNT5         DSI_TCCR1_HSRD_TOCNT5_Msk

+#define DSI_TCCR1_HSRD_TOCNT6_Pos     (6U)

+#define DSI_TCCR1_HSRD_TOCNT6_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT6_Pos)     /*!< 0x00000040 */

+#define DSI_TCCR1_HSRD_TOCNT6         DSI_TCCR1_HSRD_TOCNT6_Msk

+#define DSI_TCCR1_HSRD_TOCNT7_Pos     (7U)

+#define DSI_TCCR1_HSRD_TOCNT7_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT7_Pos)     /*!< 0x00000080 */

+#define DSI_TCCR1_HSRD_TOCNT7         DSI_TCCR1_HSRD_TOCNT7_Msk

+#define DSI_TCCR1_HSRD_TOCNT8_Pos     (8U)

+#define DSI_TCCR1_HSRD_TOCNT8_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT8_Pos)     /*!< 0x00000100 */

+#define DSI_TCCR1_HSRD_TOCNT8         DSI_TCCR1_HSRD_TOCNT8_Msk

+#define DSI_TCCR1_HSRD_TOCNT9_Pos     (9U)

+#define DSI_TCCR1_HSRD_TOCNT9_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT9_Pos)     /*!< 0x00000200 */

+#define DSI_TCCR1_HSRD_TOCNT9         DSI_TCCR1_HSRD_TOCNT9_Msk

+#define DSI_TCCR1_HSRD_TOCNT10_Pos    (10U)

+#define DSI_TCCR1_HSRD_TOCNT10_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT10_Pos)    /*!< 0x00000400 */

+#define DSI_TCCR1_HSRD_TOCNT10        DSI_TCCR1_HSRD_TOCNT10_Msk

+#define DSI_TCCR1_HSRD_TOCNT11_Pos    (11U)

+#define DSI_TCCR1_HSRD_TOCNT11_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT11_Pos)    /*!< 0x00000800 */

+#define DSI_TCCR1_HSRD_TOCNT11        DSI_TCCR1_HSRD_TOCNT11_Msk

+#define DSI_TCCR1_HSRD_TOCNT12_Pos    (12U)

+#define DSI_TCCR1_HSRD_TOCNT12_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT12_Pos)    /*!< 0x00001000 */

+#define DSI_TCCR1_HSRD_TOCNT12        DSI_TCCR1_HSRD_TOCNT12_Msk

+#define DSI_TCCR1_HSRD_TOCNT13_Pos    (13U)

+#define DSI_TCCR1_HSRD_TOCNT13_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT13_Pos)    /*!< 0x00002000 */

+#define DSI_TCCR1_HSRD_TOCNT13        DSI_TCCR1_HSRD_TOCNT13_Msk

+#define DSI_TCCR1_HSRD_TOCNT14_Pos    (14U)

+#define DSI_TCCR1_HSRD_TOCNT14_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT14_Pos)    /*!< 0x00004000 */

+#define DSI_TCCR1_HSRD_TOCNT14        DSI_TCCR1_HSRD_TOCNT14_Msk

+#define DSI_TCCR1_HSRD_TOCNT15_Pos    (15U)

+#define DSI_TCCR1_HSRD_TOCNT15_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT15_Pos)    /*!< 0x00008000 */

+#define DSI_TCCR1_HSRD_TOCNT15        DSI_TCCR1_HSRD_TOCNT15_Msk

+

+/*******************  Bit definition for DSI_TCCR2 register  **************/

+#define DSI_TCCR2_LPRD_TOCNT_Pos      (0U)

+#define DSI_TCCR2_LPRD_TOCNT_Msk      (0xFFFFUL << DSI_TCCR2_LPRD_TOCNT_Pos)   /*!< 0x0000FFFF */

+#define DSI_TCCR2_LPRD_TOCNT          DSI_TCCR2_LPRD_TOCNT_Msk                 /*!< Low-Power Read Timeout Counter */

+#define DSI_TCCR2_LPRD_TOCNT0_Pos     (0U)

+#define DSI_TCCR2_LPRD_TOCNT0_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT0_Pos)     /*!< 0x00000001 */

+#define DSI_TCCR2_LPRD_TOCNT0         DSI_TCCR2_LPRD_TOCNT0_Msk

+#define DSI_TCCR2_LPRD_TOCNT1_Pos     (1U)

+#define DSI_TCCR2_LPRD_TOCNT1_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT1_Pos)     /*!< 0x00000002 */

+#define DSI_TCCR2_LPRD_TOCNT1         DSI_TCCR2_LPRD_TOCNT1_Msk

+#define DSI_TCCR2_LPRD_TOCNT2_Pos     (2U)

+#define DSI_TCCR2_LPRD_TOCNT2_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT2_Pos)     /*!< 0x00000004 */

+#define DSI_TCCR2_LPRD_TOCNT2         DSI_TCCR2_LPRD_TOCNT2_Msk

+#define DSI_TCCR2_LPRD_TOCNT3_Pos     (3U)

+#define DSI_TCCR2_LPRD_TOCNT3_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT3_Pos)     /*!< 0x00000008 */

+#define DSI_TCCR2_LPRD_TOCNT3         DSI_TCCR2_LPRD_TOCNT3_Msk

+#define DSI_TCCR2_LPRD_TOCNT4_Pos     (4U)

+#define DSI_TCCR2_LPRD_TOCNT4_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT4_Pos)     /*!< 0x00000010 */

+#define DSI_TCCR2_LPRD_TOCNT4         DSI_TCCR2_LPRD_TOCNT4_Msk

+#define DSI_TCCR2_LPRD_TOCNT5_Pos     (5U)

+#define DSI_TCCR2_LPRD_TOCNT5_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT5_Pos)     /*!< 0x00000020 */

+#define DSI_TCCR2_LPRD_TOCNT5         DSI_TCCR2_LPRD_TOCNT5_Msk

+#define DSI_TCCR2_LPRD_TOCNT6_Pos     (6U)

+#define DSI_TCCR2_LPRD_TOCNT6_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT6_Pos)     /*!< 0x00000040 */

+#define DSI_TCCR2_LPRD_TOCNT6         DSI_TCCR2_LPRD_TOCNT6_Msk

+#define DSI_TCCR2_LPRD_TOCNT7_Pos     (7U)

+#define DSI_TCCR2_LPRD_TOCNT7_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT7_Pos)     /*!< 0x00000080 */

+#define DSI_TCCR2_LPRD_TOCNT7         DSI_TCCR2_LPRD_TOCNT7_Msk

+#define DSI_TCCR2_LPRD_TOCNT8_Pos     (8U)

+#define DSI_TCCR2_LPRD_TOCNT8_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT8_Pos)     /*!< 0x00000100 */

+#define DSI_TCCR2_LPRD_TOCNT8         DSI_TCCR2_LPRD_TOCNT8_Msk

+#define DSI_TCCR2_LPRD_TOCNT9_Pos     (9U)

+#define DSI_TCCR2_LPRD_TOCNT9_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT9_Pos)     /*!< 0x00000200 */

+#define DSI_TCCR2_LPRD_TOCNT9         DSI_TCCR2_LPRD_TOCNT9_Msk

+#define DSI_TCCR2_LPRD_TOCNT10_Pos    (10U)

+#define DSI_TCCR2_LPRD_TOCNT10_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT10_Pos)    /*!< 0x00000400 */

+#define DSI_TCCR2_LPRD_TOCNT10        DSI_TCCR2_LPRD_TOCNT10_Msk

+#define DSI_TCCR2_LPRD_TOCNT11_Pos    (11U)

+#define DSI_TCCR2_LPRD_TOCNT11_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT11_Pos)    /*!< 0x00000800 */

+#define DSI_TCCR2_LPRD_TOCNT11        DSI_TCCR2_LPRD_TOCNT11_Msk

+#define DSI_TCCR2_LPRD_TOCNT12_Pos    (12U)

+#define DSI_TCCR2_LPRD_TOCNT12_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT12_Pos)    /*!< 0x00001000 */

+#define DSI_TCCR2_LPRD_TOCNT12        DSI_TCCR2_LPRD_TOCNT12_Msk

+#define DSI_TCCR2_LPRD_TOCNT13_Pos    (13U)

+#define DSI_TCCR2_LPRD_TOCNT13_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT13_Pos)    /*!< 0x00002000 */

+#define DSI_TCCR2_LPRD_TOCNT13        DSI_TCCR2_LPRD_TOCNT13_Msk

+#define DSI_TCCR2_LPRD_TOCNT14_Pos    (14U)

+#define DSI_TCCR2_LPRD_TOCNT14_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT14_Pos)    /*!< 0x00004000 */

+#define DSI_TCCR2_LPRD_TOCNT14        DSI_TCCR2_LPRD_TOCNT14_Msk

+#define DSI_TCCR2_LPRD_TOCNT15_Pos    (15U)

+#define DSI_TCCR2_LPRD_TOCNT15_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT15_Pos)    /*!< 0x00008000 */

+#define DSI_TCCR2_LPRD_TOCNT15        DSI_TCCR2_LPRD_TOCNT15_Msk

+

+/*******************  Bit definition for DSI_TCCR3 register  **************/

+#define DSI_TCCR3_HSWR_TOCNT_Pos      (0U)

+#define DSI_TCCR3_HSWR_TOCNT_Msk      (0xFFFFUL << DSI_TCCR3_HSWR_TOCNT_Pos)   /*!< 0x0000FFFF */

+#define DSI_TCCR3_HSWR_TOCNT          DSI_TCCR3_HSWR_TOCNT_Msk                 /*!< High-Speed Write Timeout Counter */

+#define DSI_TCCR3_HSWR_TOCNT0_Pos     (0U)

+#define DSI_TCCR3_HSWR_TOCNT0_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT0_Pos)     /*!< 0x00000001 */

+#define DSI_TCCR3_HSWR_TOCNT0         DSI_TCCR3_HSWR_TOCNT0_Msk

+#define DSI_TCCR3_HSWR_TOCNT1_Pos     (1U)

+#define DSI_TCCR3_HSWR_TOCNT1_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT1_Pos)     /*!< 0x00000002 */

+#define DSI_TCCR3_HSWR_TOCNT1         DSI_TCCR3_HSWR_TOCNT1_Msk

+#define DSI_TCCR3_HSWR_TOCNT2_Pos     (2U)

+#define DSI_TCCR3_HSWR_TOCNT2_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT2_Pos)     /*!< 0x00000004 */

+#define DSI_TCCR3_HSWR_TOCNT2         DSI_TCCR3_HSWR_TOCNT2_Msk

+#define DSI_TCCR3_HSWR_TOCNT3_Pos     (3U)

+#define DSI_TCCR3_HSWR_TOCNT3_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT3_Pos)     /*!< 0x00000008 */

+#define DSI_TCCR3_HSWR_TOCNT3         DSI_TCCR3_HSWR_TOCNT3_Msk

+#define DSI_TCCR3_HSWR_TOCNT4_Pos     (4U)

+#define DSI_TCCR3_HSWR_TOCNT4_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT4_Pos)     /*!< 0x00000010 */

+#define DSI_TCCR3_HSWR_TOCNT4         DSI_TCCR3_HSWR_TOCNT4_Msk

+#define DSI_TCCR3_HSWR_TOCNT5_Pos     (5U)

+#define DSI_TCCR3_HSWR_TOCNT5_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT5_Pos)     /*!< 0x00000020 */

+#define DSI_TCCR3_HSWR_TOCNT5         DSI_TCCR3_HSWR_TOCNT5_Msk

+#define DSI_TCCR3_HSWR_TOCNT6_Pos     (6U)

+#define DSI_TCCR3_HSWR_TOCNT6_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT6_Pos)     /*!< 0x00000040 */

+#define DSI_TCCR3_HSWR_TOCNT6         DSI_TCCR3_HSWR_TOCNT6_Msk

+#define DSI_TCCR3_HSWR_TOCNT7_Pos     (7U)

+#define DSI_TCCR3_HSWR_TOCNT7_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT7_Pos)     /*!< 0x00000080 */

+#define DSI_TCCR3_HSWR_TOCNT7         DSI_TCCR3_HSWR_TOCNT7_Msk

+#define DSI_TCCR3_HSWR_TOCNT8_Pos     (8U)

+#define DSI_TCCR3_HSWR_TOCNT8_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT8_Pos)     /*!< 0x00000100 */

+#define DSI_TCCR3_HSWR_TOCNT8         DSI_TCCR3_HSWR_TOCNT8_Msk

+#define DSI_TCCR3_HSWR_TOCNT9_Pos     (9U)

+#define DSI_TCCR3_HSWR_TOCNT9_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT9_Pos)     /*!< 0x00000200 */

+#define DSI_TCCR3_HSWR_TOCNT9         DSI_TCCR3_HSWR_TOCNT9_Msk

+#define DSI_TCCR3_HSWR_TOCNT10_Pos    (10U)

+#define DSI_TCCR3_HSWR_TOCNT10_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT10_Pos)    /*!< 0x00000400 */

+#define DSI_TCCR3_HSWR_TOCNT10        DSI_TCCR3_HSWR_TOCNT10_Msk

+#define DSI_TCCR3_HSWR_TOCNT11_Pos    (11U)

+#define DSI_TCCR3_HSWR_TOCNT11_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT11_Pos)    /*!< 0x00000800 */

+#define DSI_TCCR3_HSWR_TOCNT11        DSI_TCCR3_HSWR_TOCNT11_Msk

+#define DSI_TCCR3_HSWR_TOCNT12_Pos    (12U)

+#define DSI_TCCR3_HSWR_TOCNT12_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT12_Pos)    /*!< 0x00001000 */

+#define DSI_TCCR3_HSWR_TOCNT12        DSI_TCCR3_HSWR_TOCNT12_Msk

+#define DSI_TCCR3_HSWR_TOCNT13_Pos    (13U)

+#define DSI_TCCR3_HSWR_TOCNT13_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT13_Pos)    /*!< 0x00002000 */

+#define DSI_TCCR3_HSWR_TOCNT13        DSI_TCCR3_HSWR_TOCNT13_Msk

+#define DSI_TCCR3_HSWR_TOCNT14_Pos    (14U)

+#define DSI_TCCR3_HSWR_TOCNT14_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT14_Pos)    /*!< 0x00004000 */

+#define DSI_TCCR3_HSWR_TOCNT14        DSI_TCCR3_HSWR_TOCNT14_Msk

+#define DSI_TCCR3_HSWR_TOCNT15_Pos    (15U)

+#define DSI_TCCR3_HSWR_TOCNT15_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT15_Pos)    /*!< 0x00008000 */

+#define DSI_TCCR3_HSWR_TOCNT15        DSI_TCCR3_HSWR_TOCNT15_Msk

+

+#define DSI_TCCR3_PM_Pos              (24U)

+#define DSI_TCCR3_PM_Msk              (0x1UL << DSI_TCCR3_PM_Pos)              /*!< 0x01000000 */

+#define DSI_TCCR3_PM                  DSI_TCCR3_PM_Msk                         /*!< Presp Mode */

+

+/*******************  Bit definition for DSI_TCCR4 register  **************/

+#define DSI_TCCR4_LPWR_TOCNT_Pos      (0U)

+#define DSI_TCCR4_LPWR_TOCNT_Msk      (0xFFFFUL << DSI_TCCR4_LPWR_TOCNT_Pos)   /*!< 0x0000FFFF */

+#define DSI_TCCR4_LPWR_TOCNT          DSI_TCCR4_LPWR_TOCNT_Msk                 /*!< Low-Power Write Timeout Counter */

+#define DSI_TCCR4_LPWR_TOCNT0_Pos     (0U)

+#define DSI_TCCR4_LPWR_TOCNT0_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT0_Pos)     /*!< 0x00000001 */

+#define DSI_TCCR4_LPWR_TOCNT0         DSI_TCCR4_LPWR_TOCNT0_Msk

+#define DSI_TCCR4_LPWR_TOCNT1_Pos     (1U)

+#define DSI_TCCR4_LPWR_TOCNT1_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT1_Pos)     /*!< 0x00000002 */

+#define DSI_TCCR4_LPWR_TOCNT1         DSI_TCCR4_LPWR_TOCNT1_Msk

+#define DSI_TCCR4_LPWR_TOCNT2_Pos     (2U)

+#define DSI_TCCR4_LPWR_TOCNT2_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT2_Pos)     /*!< 0x00000004 */

+#define DSI_TCCR4_LPWR_TOCNT2         DSI_TCCR4_LPWR_TOCNT2_Msk

+#define DSI_TCCR4_LPWR_TOCNT3_Pos     (3U)

+#define DSI_TCCR4_LPWR_TOCNT3_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT3_Pos)     /*!< 0x00000008 */

+#define DSI_TCCR4_LPWR_TOCNT3         DSI_TCCR4_LPWR_TOCNT3_Msk

+#define DSI_TCCR4_LPWR_TOCNT4_Pos     (4U)

+#define DSI_TCCR4_LPWR_TOCNT4_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT4_Pos)     /*!< 0x00000010 */

+#define DSI_TCCR4_LPWR_TOCNT4         DSI_TCCR4_LPWR_TOCNT4_Msk

+#define DSI_TCCR4_LPWR_TOCNT5_Pos     (5U)

+#define DSI_TCCR4_LPWR_TOCNT5_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT5_Pos)     /*!< 0x00000020 */

+#define DSI_TCCR4_LPWR_TOCNT5         DSI_TCCR4_LPWR_TOCNT5_Msk

+#define DSI_TCCR4_LPWR_TOCNT6_Pos     (6U)

+#define DSI_TCCR4_LPWR_TOCNT6_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT6_Pos)     /*!< 0x00000040 */

+#define DSI_TCCR4_LPWR_TOCNT6         DSI_TCCR4_LPWR_TOCNT6_Msk

+#define DSI_TCCR4_LPWR_TOCNT7_Pos     (7U)

+#define DSI_TCCR4_LPWR_TOCNT7_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT7_Pos)     /*!< 0x00000080 */

+#define DSI_TCCR4_LPWR_TOCNT7         DSI_TCCR4_LPWR_TOCNT7_Msk

+#define DSI_TCCR4_LPWR_TOCNT8_Pos     (8U)

+#define DSI_TCCR4_LPWR_TOCNT8_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT8_Pos)     /*!< 0x00000100 */

+#define DSI_TCCR4_LPWR_TOCNT8         DSI_TCCR4_LPWR_TOCNT8_Msk

+#define DSI_TCCR4_LPWR_TOCNT9_Pos     (9U)

+#define DSI_TCCR4_LPWR_TOCNT9_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT9_Pos)     /*!< 0x00000200 */

+#define DSI_TCCR4_LPWR_TOCNT9         DSI_TCCR4_LPWR_TOCNT9_Msk

+#define DSI_TCCR4_LPWR_TOCNT10_Pos    (10U)

+#define DSI_TCCR4_LPWR_TOCNT10_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT10_Pos)    /*!< 0x00000400 */

+#define DSI_TCCR4_LPWR_TOCNT10        DSI_TCCR4_LPWR_TOCNT10_Msk

+#define DSI_TCCR4_LPWR_TOCNT11_Pos    (11U)

+#define DSI_TCCR4_LPWR_TOCNT11_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT11_Pos)    /*!< 0x00000800 */

+#define DSI_TCCR4_LPWR_TOCNT11        DSI_TCCR4_LPWR_TOCNT11_Msk

+#define DSI_TCCR4_LPWR_TOCNT12_Pos    (12U)

+#define DSI_TCCR4_LPWR_TOCNT12_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT12_Pos)    /*!< 0x00001000 */

+#define DSI_TCCR4_LPWR_TOCNT12        DSI_TCCR4_LPWR_TOCNT12_Msk

+#define DSI_TCCR4_LPWR_TOCNT13_Pos    (13U)

+#define DSI_TCCR4_LPWR_TOCNT13_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT13_Pos)    /*!< 0x00002000 */

+#define DSI_TCCR4_LPWR_TOCNT13        DSI_TCCR4_LPWR_TOCNT13_Msk

+#define DSI_TCCR4_LPWR_TOCNT14_Pos    (14U)

+#define DSI_TCCR4_LPWR_TOCNT14_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT14_Pos)    /*!< 0x00004000 */

+#define DSI_TCCR4_LPWR_TOCNT14        DSI_TCCR4_LPWR_TOCNT14_Msk

+#define DSI_TCCR4_LPWR_TOCNT15_Pos    (15U)

+#define DSI_TCCR4_LPWR_TOCNT15_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT15_Pos)    /*!< 0x00008000 */

+#define DSI_TCCR4_LPWR_TOCNT15        DSI_TCCR4_LPWR_TOCNT15_Msk

+

+/*******************  Bit definition for DSI_TCCR5 register  **************/

+#define DSI_TCCR5_BTA_TOCNT_Pos       (0U)

+#define DSI_TCCR5_BTA_TOCNT_Msk       (0xFFFFUL << DSI_TCCR5_BTA_TOCNT_Pos)    /*!< 0x0000FFFF */

+#define DSI_TCCR5_BTA_TOCNT           DSI_TCCR5_BTA_TOCNT_Msk                  /*!< Bus-Turn-Around Timeout Counter */

+#define DSI_TCCR5_BTA_TOCNT0_Pos      (0U)

+#define DSI_TCCR5_BTA_TOCNT0_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT0_Pos)      /*!< 0x00000001 */

+#define DSI_TCCR5_BTA_TOCNT0          DSI_TCCR5_BTA_TOCNT0_Msk

+#define DSI_TCCR5_BTA_TOCNT1_Pos      (1U)

+#define DSI_TCCR5_BTA_TOCNT1_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT1_Pos)      /*!< 0x00000002 */

+#define DSI_TCCR5_BTA_TOCNT1          DSI_TCCR5_BTA_TOCNT1_Msk

+#define DSI_TCCR5_BTA_TOCNT2_Pos      (2U)

+#define DSI_TCCR5_BTA_TOCNT2_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT2_Pos)      /*!< 0x00000004 */

+#define DSI_TCCR5_BTA_TOCNT2          DSI_TCCR5_BTA_TOCNT2_Msk

+#define DSI_TCCR5_BTA_TOCNT3_Pos      (3U)

+#define DSI_TCCR5_BTA_TOCNT3_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT3_Pos)      /*!< 0x00000008 */

+#define DSI_TCCR5_BTA_TOCNT3          DSI_TCCR5_BTA_TOCNT3_Msk

+#define DSI_TCCR5_BTA_TOCNT4_Pos      (4U)

+#define DSI_TCCR5_BTA_TOCNT4_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT4_Pos)      /*!< 0x00000010 */

+#define DSI_TCCR5_BTA_TOCNT4          DSI_TCCR5_BTA_TOCNT4_Msk

+#define DSI_TCCR5_BTA_TOCNT5_Pos      (5U)

+#define DSI_TCCR5_BTA_TOCNT5_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT5_Pos)      /*!< 0x00000020 */

+#define DSI_TCCR5_BTA_TOCNT5          DSI_TCCR5_BTA_TOCNT5_Msk

+#define DSI_TCCR5_BTA_TOCNT6_Pos      (6U)

+#define DSI_TCCR5_BTA_TOCNT6_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT6_Pos)      /*!< 0x00000040 */

+#define DSI_TCCR5_BTA_TOCNT6          DSI_TCCR5_BTA_TOCNT6_Msk

+#define DSI_TCCR5_BTA_TOCNT7_Pos      (7U)

+#define DSI_TCCR5_BTA_TOCNT7_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT7_Pos)      /*!< 0x00000080 */

+#define DSI_TCCR5_BTA_TOCNT7          DSI_TCCR5_BTA_TOCNT7_Msk

+#define DSI_TCCR5_BTA_TOCNT8_Pos      (8U)

+#define DSI_TCCR5_BTA_TOCNT8_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT8_Pos)      /*!< 0x00000100 */

+#define DSI_TCCR5_BTA_TOCNT8          DSI_TCCR5_BTA_TOCNT8_Msk

+#define DSI_TCCR5_BTA_TOCNT9_Pos      (9U)

+#define DSI_TCCR5_BTA_TOCNT9_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT9_Pos)      /*!< 0x00000200 */

+#define DSI_TCCR5_BTA_TOCNT9          DSI_TCCR5_BTA_TOCNT9_Msk

+#define DSI_TCCR5_BTA_TOCNT10_Pos     (10U)

+#define DSI_TCCR5_BTA_TOCNT10_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT10_Pos)     /*!< 0x00000400 */

+#define DSI_TCCR5_BTA_TOCNT10         DSI_TCCR5_BTA_TOCNT10_Msk

+#define DSI_TCCR5_BTA_TOCNT11_Pos     (11U)

+#define DSI_TCCR5_BTA_TOCNT11_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT11_Pos)     /*!< 0x00000800 */

+#define DSI_TCCR5_BTA_TOCNT11         DSI_TCCR5_BTA_TOCNT11_Msk

+#define DSI_TCCR5_BTA_TOCNT12_Pos     (12U)

+#define DSI_TCCR5_BTA_TOCNT12_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT12_Pos)     /*!< 0x00001000 */

+#define DSI_TCCR5_BTA_TOCNT12         DSI_TCCR5_BTA_TOCNT12_Msk

+#define DSI_TCCR5_BTA_TOCNT13_Pos     (13U)

+#define DSI_TCCR5_BTA_TOCNT13_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT13_Pos)     /*!< 0x00002000 */

+#define DSI_TCCR5_BTA_TOCNT13         DSI_TCCR5_BTA_TOCNT13_Msk

+#define DSI_TCCR5_BTA_TOCNT14_Pos     (14U)

+#define DSI_TCCR5_BTA_TOCNT14_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT14_Pos)     /*!< 0x00004000 */

+#define DSI_TCCR5_BTA_TOCNT14         DSI_TCCR5_BTA_TOCNT14_Msk

+#define DSI_TCCR5_BTA_TOCNT15_Pos     (15U)

+#define DSI_TCCR5_BTA_TOCNT15_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT15_Pos)     /*!< 0x00008000 */

+#define DSI_TCCR5_BTA_TOCNT15         DSI_TCCR5_BTA_TOCNT15_Msk

+

+/*******************  Bit definition for DSI_TDCR register  ***************/

+#define DSI_TDCR_3DM                  ((uint32_t)0x00000003U)                  /*!< 3D Mode */

+#define DSI_TDCR_3DM0                 ((uint32_t)0x00000001U)

+#define DSI_TDCR_3DM1                 ((uint32_t)0x00000002U)

+

+#define DSI_TDCR_3DF                  ((uint32_t)0x0000000CU)                  /*!< 3D Format */

+#define DSI_TDCR_3DF0                 ((uint32_t)0x00000004U)

+#define DSI_TDCR_3DF1                 ((uint32_t)0x00000008U)

+

+#define DSI_TDCR_SVS_Pos              (4U)

+#define DSI_TDCR_SVS_Msk              (0x1UL << DSI_TDCR_SVS_Pos)              /*!< 0x00000010 */

+#define DSI_TDCR_SVS                  DSI_TDCR_SVS_Msk                         /*!< Second VSYNC */

+#define DSI_TDCR_RF_Pos               (5U)

+#define DSI_TDCR_RF_Msk               (0x1UL << DSI_TDCR_RF_Pos)               /*!< 0x00000020 */

+#define DSI_TDCR_RF                   DSI_TDCR_RF_Msk                          /*!< Right First */

+#define DSI_TDCR_S3DC_Pos             (16U)

+#define DSI_TDCR_S3DC_Msk             (0x1UL << DSI_TDCR_S3DC_Pos)             /*!< 0x00010000 */

+#define DSI_TDCR_S3DC                 DSI_TDCR_S3DC_Msk                        /*!< Send 3D Control */

+

+/*******************  Bit definition for DSI_CLCR register  ***************/

+#define DSI_CLCR_DPCC_Pos             (0U)

+#define DSI_CLCR_DPCC_Msk             (0x1UL << DSI_CLCR_DPCC_Pos)             /*!< 0x00000001 */

+#define DSI_CLCR_DPCC                 DSI_CLCR_DPCC_Msk                        /*!< D-PHY Clock Control */

+#define DSI_CLCR_ACR_Pos              (1U)

+#define DSI_CLCR_ACR_Msk              (0x1UL << DSI_CLCR_ACR_Pos)              /*!< 0x00000002 */

+#define DSI_CLCR_ACR                  DSI_CLCR_ACR_Msk                         /*!< Automatic Clocklane Control */

+

+/*******************  Bit definition for DSI_CLTCR register  **************/

+#define DSI_CLTCR_LP2HS_TIME_Pos      (0U)

+#define DSI_CLTCR_LP2HS_TIME_Msk      (0x3FFUL << DSI_CLTCR_LP2HS_TIME_Pos)    /*!< 0x000003FF */

+#define DSI_CLTCR_LP2HS_TIME          DSI_CLTCR_LP2HS_TIME_Msk                 /*!< Low-Power to High-Speed Time */

+#define DSI_CLTCR_LP2HS_TIME0_Pos     (0U)

+#define DSI_CLTCR_LP2HS_TIME0_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME0_Pos)     /*!< 0x00000001 */

+#define DSI_CLTCR_LP2HS_TIME0         DSI_CLTCR_LP2HS_TIME0_Msk

+#define DSI_CLTCR_LP2HS_TIME1_Pos     (1U)

+#define DSI_CLTCR_LP2HS_TIME1_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME1_Pos)     /*!< 0x00000002 */

+#define DSI_CLTCR_LP2HS_TIME1         DSI_CLTCR_LP2HS_TIME1_Msk

+#define DSI_CLTCR_LP2HS_TIME2_Pos     (2U)

+#define DSI_CLTCR_LP2HS_TIME2_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME2_Pos)     /*!< 0x00000004 */

+#define DSI_CLTCR_LP2HS_TIME2         DSI_CLTCR_LP2HS_TIME2_Msk

+#define DSI_CLTCR_LP2HS_TIME3_Pos     (3U)

+#define DSI_CLTCR_LP2HS_TIME3_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME3_Pos)     /*!< 0x00000008 */

+#define DSI_CLTCR_LP2HS_TIME3         DSI_CLTCR_LP2HS_TIME3_Msk

+#define DSI_CLTCR_LP2HS_TIME4_Pos     (4U)

+#define DSI_CLTCR_LP2HS_TIME4_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME4_Pos)     /*!< 0x00000010 */

+#define DSI_CLTCR_LP2HS_TIME4         DSI_CLTCR_LP2HS_TIME4_Msk

+#define DSI_CLTCR_LP2HS_TIME5_Pos     (5U)

+#define DSI_CLTCR_LP2HS_TIME5_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME5_Pos)     /*!< 0x00000020 */

+#define DSI_CLTCR_LP2HS_TIME5         DSI_CLTCR_LP2HS_TIME5_Msk

+#define DSI_CLTCR_LP2HS_TIME6_Pos     (6U)

+#define DSI_CLTCR_LP2HS_TIME6_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME6_Pos)     /*!< 0x00000040 */

+#define DSI_CLTCR_LP2HS_TIME6         DSI_CLTCR_LP2HS_TIME6_Msk

+#define DSI_CLTCR_LP2HS_TIME7_Pos     (7U)

+#define DSI_CLTCR_LP2HS_TIME7_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME7_Pos)     /*!< 0x00000080 */

+#define DSI_CLTCR_LP2HS_TIME7         DSI_CLTCR_LP2HS_TIME7_Msk

+#define DSI_CLTCR_LP2HS_TIME8_Pos     (8U)

+#define DSI_CLTCR_LP2HS_TIME8_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME8_Pos)     /*!< 0x00000100 */

+#define DSI_CLTCR_LP2HS_TIME8         DSI_CLTCR_LP2HS_TIME8_Msk

+#define DSI_CLTCR_LP2HS_TIME9_Pos     (9U)

+#define DSI_CLTCR_LP2HS_TIME9_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME9_Pos)     /*!< 0x00000200 */

+#define DSI_CLTCR_LP2HS_TIME9         DSI_CLTCR_LP2HS_TIME9_Msk

+

+#define DSI_CLTCR_HS2LP_TIME_Pos      (16U)

+#define DSI_CLTCR_HS2LP_TIME_Msk      (0x3FFUL << DSI_CLTCR_HS2LP_TIME_Pos)    /*!< 0x03FF0000 */

+#define DSI_CLTCR_HS2LP_TIME          DSI_CLTCR_HS2LP_TIME_Msk                 /*!< High-Speed to Low-Power Time */

+#define DSI_CLTCR_HS2LP_TIME0_Pos     (16U)

+#define DSI_CLTCR_HS2LP_TIME0_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME0_Pos)     /*!< 0x00010000 */

+#define DSI_CLTCR_HS2LP_TIME0         DSI_CLTCR_HS2LP_TIME0_Msk

+#define DSI_CLTCR_HS2LP_TIME1_Pos     (17U)

+#define DSI_CLTCR_HS2LP_TIME1_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME1_Pos)     /*!< 0x00020000 */

+#define DSI_CLTCR_HS2LP_TIME1         DSI_CLTCR_HS2LP_TIME1_Msk

+#define DSI_CLTCR_HS2LP_TIME2_Pos     (18U)

+#define DSI_CLTCR_HS2LP_TIME2_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME2_Pos)     /*!< 0x00040000 */

+#define DSI_CLTCR_HS2LP_TIME2         DSI_CLTCR_HS2LP_TIME2_Msk

+#define DSI_CLTCR_HS2LP_TIME3_Pos     (19U)

+#define DSI_CLTCR_HS2LP_TIME3_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME3_Pos)     /*!< 0x00080000 */

+#define DSI_CLTCR_HS2LP_TIME3         DSI_CLTCR_HS2LP_TIME3_Msk

+#define DSI_CLTCR_HS2LP_TIME4_Pos     (20U)

+#define DSI_CLTCR_HS2LP_TIME4_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME4_Pos)     /*!< 0x00100000 */

+#define DSI_CLTCR_HS2LP_TIME4         DSI_CLTCR_HS2LP_TIME4_Msk

+#define DSI_CLTCR_HS2LP_TIME5_Pos     (21U)

+#define DSI_CLTCR_HS2LP_TIME5_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME5_Pos)     /*!< 0x00200000 */

+#define DSI_CLTCR_HS2LP_TIME5         DSI_CLTCR_HS2LP_TIME5_Msk

+#define DSI_CLTCR_HS2LP_TIME6_Pos     (22U)

+#define DSI_CLTCR_HS2LP_TIME6_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME6_Pos)     /*!< 0x00400000 */

+#define DSI_CLTCR_HS2LP_TIME6         DSI_CLTCR_HS2LP_TIME6_Msk

+#define DSI_CLTCR_HS2LP_TIME7_Pos     (23U)

+#define DSI_CLTCR_HS2LP_TIME7_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME7_Pos)     /*!< 0x00800000 */

+#define DSI_CLTCR_HS2LP_TIME7         DSI_CLTCR_HS2LP_TIME7_Msk

+#define DSI_CLTCR_HS2LP_TIME8_Pos     (24U)

+#define DSI_CLTCR_HS2LP_TIME8_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME8_Pos)     /*!< 0x01000000 */

+#define DSI_CLTCR_HS2LP_TIME8         DSI_CLTCR_HS2LP_TIME8_Msk

+#define DSI_CLTCR_HS2LP_TIME9_Pos     (25U)

+#define DSI_CLTCR_HS2LP_TIME9_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME9_Pos)     /*!< 0x02000000 */

+#define DSI_CLTCR_HS2LP_TIME9         DSI_CLTCR_HS2LP_TIME9_Msk

+

+/*******************  Bit definition for DSI_DLTCR register  **************/

+#define DSI_DLTCR_MRD_TIME_Pos        (0U)

+#define DSI_DLTCR_MRD_TIME_Msk        (0x7FFFUL << DSI_DLTCR_MRD_TIME_Pos)     /*!< 0x00007FFF */

+#define DSI_DLTCR_MRD_TIME            DSI_DLTCR_MRD_TIME_Msk                   /*!< Maximum Read Time */

+#define DSI_DLTCR_MRD_TIME0_Pos       (0U)

+#define DSI_DLTCR_MRD_TIME0_Msk       (0x1UL << DSI_DLTCR_MRD_TIME0_Pos)       /*!< 0x00000001 */

+#define DSI_DLTCR_MRD_TIME0           DSI_DLTCR_MRD_TIME0_Msk

+#define DSI_DLTCR_MRD_TIME1_Pos       (1U)

+#define DSI_DLTCR_MRD_TIME1_Msk       (0x1UL << DSI_DLTCR_MRD_TIME1_Pos)       /*!< 0x00000002 */

+#define DSI_DLTCR_MRD_TIME1           DSI_DLTCR_MRD_TIME1_Msk

+#define DSI_DLTCR_MRD_TIME2_Pos       (2U)

+#define DSI_DLTCR_MRD_TIME2_Msk       (0x1UL << DSI_DLTCR_MRD_TIME2_Pos)       /*!< 0x00000004 */

+#define DSI_DLTCR_MRD_TIME2           DSI_DLTCR_MRD_TIME2_Msk

+#define DSI_DLTCR_MRD_TIME3_Pos       (3U)

+#define DSI_DLTCR_MRD_TIME3_Msk       (0x1UL << DSI_DLTCR_MRD_TIME3_Pos)       /*!< 0x00000008 */

+#define DSI_DLTCR_MRD_TIME3           DSI_DLTCR_MRD_TIME3_Msk

+#define DSI_DLTCR_MRD_TIME4_Pos       (4U)

+#define DSI_DLTCR_MRD_TIME4_Msk       (0x1UL << DSI_DLTCR_MRD_TIME4_Pos)       /*!< 0x00000010 */

+#define DSI_DLTCR_MRD_TIME4           DSI_DLTCR_MRD_TIME4_Msk

+#define DSI_DLTCR_MRD_TIME5_Pos       (5U)

+#define DSI_DLTCR_MRD_TIME5_Msk       (0x1UL << DSI_DLTCR_MRD_TIME5_Pos)       /*!< 0x00000020 */

+#define DSI_DLTCR_MRD_TIME5           DSI_DLTCR_MRD_TIME5_Msk

+#define DSI_DLTCR_MRD_TIME6_Pos       (6U)

+#define DSI_DLTCR_MRD_TIME6_Msk       (0x1UL << DSI_DLTCR_MRD_TIME6_Pos)       /*!< 0x00000040 */

+#define DSI_DLTCR_MRD_TIME6           DSI_DLTCR_MRD_TIME6_Msk

+#define DSI_DLTCR_MRD_TIME7_Pos       (7U)

+#define DSI_DLTCR_MRD_TIME7_Msk       (0x1UL << DSI_DLTCR_MRD_TIME7_Pos)       /*!< 0x00000080 */

+#define DSI_DLTCR_MRD_TIME7           DSI_DLTCR_MRD_TIME7_Msk

+#define DSI_DLTCR_MRD_TIME8_Pos       (8U)

+#define DSI_DLTCR_MRD_TIME8_Msk       (0x1UL << DSI_DLTCR_MRD_TIME8_Pos)       /*!< 0x00000100 */

+#define DSI_DLTCR_MRD_TIME8           DSI_DLTCR_MRD_TIME8_Msk

+#define DSI_DLTCR_MRD_TIME9_Pos       (9U)

+#define DSI_DLTCR_MRD_TIME9_Msk       (0x1UL << DSI_DLTCR_MRD_TIME9_Pos)       /*!< 0x00000200 */

+#define DSI_DLTCR_MRD_TIME9           DSI_DLTCR_MRD_TIME9_Msk

+#define DSI_DLTCR_MRD_TIME10_Pos      (10U)

+#define DSI_DLTCR_MRD_TIME10_Msk      (0x1UL << DSI_DLTCR_MRD_TIME10_Pos)      /*!< 0x00000400 */

+#define DSI_DLTCR_MRD_TIME10          DSI_DLTCR_MRD_TIME10_Msk

+#define DSI_DLTCR_MRD_TIME11_Pos      (11U)

+#define DSI_DLTCR_MRD_TIME11_Msk      (0x1UL << DSI_DLTCR_MRD_TIME11_Pos)      /*!< 0x00000800 */

+#define DSI_DLTCR_MRD_TIME11          DSI_DLTCR_MRD_TIME11_Msk

+#define DSI_DLTCR_MRD_TIME12_Pos      (12U)

+#define DSI_DLTCR_MRD_TIME12_Msk      (0x1UL << DSI_DLTCR_MRD_TIME12_Pos)      /*!< 0x00001000 */

+#define DSI_DLTCR_MRD_TIME12          DSI_DLTCR_MRD_TIME12_Msk

+#define DSI_DLTCR_MRD_TIME13_Pos      (13U)

+#define DSI_DLTCR_MRD_TIME13_Msk      (0x1UL << DSI_DLTCR_MRD_TIME13_Pos)      /*!< 0x00002000 */

+#define DSI_DLTCR_MRD_TIME13          DSI_DLTCR_MRD_TIME13_Msk

+#define DSI_DLTCR_MRD_TIME14_Pos      (14U)

+#define DSI_DLTCR_MRD_TIME14_Msk      (0x1UL << DSI_DLTCR_MRD_TIME14_Pos)      /*!< 0x00004000 */

+#define DSI_DLTCR_MRD_TIME14          DSI_DLTCR_MRD_TIME14_Msk

+

+#define DSI_DLTCR_LP2HS_TIME_Pos      (16U)

+#define DSI_DLTCR_LP2HS_TIME_Msk      (0xFFUL << DSI_DLTCR_LP2HS_TIME_Pos)     /*!< 0x00FF0000 */

+#define DSI_DLTCR_LP2HS_TIME          DSI_DLTCR_LP2HS_TIME_Msk                 /*!< Low-Power To High-Speed Time */

+#define DSI_DLTCR_LP2HS_TIME0_Pos     (16U)

+#define DSI_DLTCR_LP2HS_TIME0_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME0_Pos)     /*!< 0x00010000 */

+#define DSI_DLTCR_LP2HS_TIME0         DSI_DLTCR_LP2HS_TIME0_Msk

+#define DSI_DLTCR_LP2HS_TIME1_Pos     (17U)

+#define DSI_DLTCR_LP2HS_TIME1_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME1_Pos)     /*!< 0x00020000 */

+#define DSI_DLTCR_LP2HS_TIME1         DSI_DLTCR_LP2HS_TIME1_Msk

+#define DSI_DLTCR_LP2HS_TIME2_Pos     (18U)

+#define DSI_DLTCR_LP2HS_TIME2_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME2_Pos)     /*!< 0x00040000 */

+#define DSI_DLTCR_LP2HS_TIME2         DSI_DLTCR_LP2HS_TIME2_Msk

+#define DSI_DLTCR_LP2HS_TIME3_Pos     (19U)

+#define DSI_DLTCR_LP2HS_TIME3_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME3_Pos)     /*!< 0x00080000 */

+#define DSI_DLTCR_LP2HS_TIME3         DSI_DLTCR_LP2HS_TIME3_Msk

+#define DSI_DLTCR_LP2HS_TIME4_Pos     (20U)

+#define DSI_DLTCR_LP2HS_TIME4_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME4_Pos)     /*!< 0x00100000 */

+#define DSI_DLTCR_LP2HS_TIME4         DSI_DLTCR_LP2HS_TIME4_Msk

+#define DSI_DLTCR_LP2HS_TIME5_Pos     (21U)

+#define DSI_DLTCR_LP2HS_TIME5_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME5_Pos)     /*!< 0x00200000 */

+#define DSI_DLTCR_LP2HS_TIME5         DSI_DLTCR_LP2HS_TIME5_Msk

+#define DSI_DLTCR_LP2HS_TIME6_Pos     (22U)

+#define DSI_DLTCR_LP2HS_TIME6_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME6_Pos)     /*!< 0x00400000 */

+#define DSI_DLTCR_LP2HS_TIME6         DSI_DLTCR_LP2HS_TIME6_Msk

+#define DSI_DLTCR_LP2HS_TIME7_Pos     (23U)

+#define DSI_DLTCR_LP2HS_TIME7_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME7_Pos)     /*!< 0x00800000 */

+#define DSI_DLTCR_LP2HS_TIME7         DSI_DLTCR_LP2HS_TIME7_Msk

+

+#define DSI_DLTCR_HS2LP_TIME_Pos      (24U)

+#define DSI_DLTCR_HS2LP_TIME_Msk      (0xFFUL << DSI_DLTCR_HS2LP_TIME_Pos)     /*!< 0xFF000000 */

+#define DSI_DLTCR_HS2LP_TIME          DSI_DLTCR_HS2LP_TIME_Msk                 /*!< High-Speed To Low-Power Time */

+#define DSI_DLTCR_HS2LP_TIME0_Pos     (24U)

+#define DSI_DLTCR_HS2LP_TIME0_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME0_Pos)     /*!< 0x01000000 */

+#define DSI_DLTCR_HS2LP_TIME0         DSI_DLTCR_HS2LP_TIME0_Msk

+#define DSI_DLTCR_HS2LP_TIME1_Pos     (25U)

+#define DSI_DLTCR_HS2LP_TIME1_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME1_Pos)     /*!< 0x02000000 */

+#define DSI_DLTCR_HS2LP_TIME1         DSI_DLTCR_HS2LP_TIME1_Msk

+#define DSI_DLTCR_HS2LP_TIME2_Pos     (26U)

+#define DSI_DLTCR_HS2LP_TIME2_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME2_Pos)     /*!< 0x04000000 */

+#define DSI_DLTCR_HS2LP_TIME2         DSI_DLTCR_HS2LP_TIME2_Msk

+#define DSI_DLTCR_HS2LP_TIME3_Pos     (27U)

+#define DSI_DLTCR_HS2LP_TIME3_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME3_Pos)     /*!< 0x08000000 */

+#define DSI_DLTCR_HS2LP_TIME3         DSI_DLTCR_HS2LP_TIME3_Msk

+#define DSI_DLTCR_HS2LP_TIME4_Pos     (28U)

+#define DSI_DLTCR_HS2LP_TIME4_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME4_Pos)     /*!< 0x10000000 */

+#define DSI_DLTCR_HS2LP_TIME4         DSI_DLTCR_HS2LP_TIME4_Msk

+#define DSI_DLTCR_HS2LP_TIME5_Pos     (29U)

+#define DSI_DLTCR_HS2LP_TIME5_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME5_Pos)     /*!< 0x20000000 */

+#define DSI_DLTCR_HS2LP_TIME5         DSI_DLTCR_HS2LP_TIME5_Msk

+#define DSI_DLTCR_HS2LP_TIME6_Pos     (30U)

+#define DSI_DLTCR_HS2LP_TIME6_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME6_Pos)     /*!< 0x40000000 */

+#define DSI_DLTCR_HS2LP_TIME6         DSI_DLTCR_HS2LP_TIME6_Msk

+#define DSI_DLTCR_HS2LP_TIME7_Pos     (31U)

+#define DSI_DLTCR_HS2LP_TIME7_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME7_Pos)     /*!< 0x80000000 */

+#define DSI_DLTCR_HS2LP_TIME7         DSI_DLTCR_HS2LP_TIME7_Msk

+

+/*******************  Bit definition for DSI_PCTLR register  **************/

+#define DSI_PCTLR_DEN_Pos             (1U)

+#define DSI_PCTLR_DEN_Msk             (0x1UL << DSI_PCTLR_DEN_Pos)             /*!< 0x00000002 */

+#define DSI_PCTLR_DEN                 DSI_PCTLR_DEN_Msk                        /*!< Digital Enable */

+#define DSI_PCTLR_CKE_Pos             (2U)

+#define DSI_PCTLR_CKE_Msk             (0x1UL << DSI_PCTLR_CKE_Pos)             /*!< 0x00000004 */

+#define DSI_PCTLR_CKE                 DSI_PCTLR_CKE_Msk                        /*!< Clock Enable */

+

+/*******************  Bit definition for DSI_PCONFR register  *************/

+#define DSI_PCONFR_NL_Pos             (0U)

+#define DSI_PCONFR_NL_Msk             (0x3UL << DSI_PCONFR_NL_Pos)             /*!< 0x00000003 */

+#define DSI_PCONFR_NL                 DSI_PCONFR_NL_Msk                        /*!< Number of Lanes */

+#define DSI_PCONFR_NL0_Pos            (0U)

+#define DSI_PCONFR_NL0_Msk            (0x1UL << DSI_PCONFR_NL0_Pos)            /*!< 0x00000001 */

+#define DSI_PCONFR_NL0                DSI_PCONFR_NL0_Msk

+#define DSI_PCONFR_NL1_Pos            (1U)

+#define DSI_PCONFR_NL1_Msk            (0x1UL << DSI_PCONFR_NL1_Pos)            /*!< 0x00000002 */

+#define DSI_PCONFR_NL1                DSI_PCONFR_NL1_Msk

+

+#define DSI_PCONFR_SW_TIME_Pos        (8U)

+#define DSI_PCONFR_SW_TIME_Msk        (0xFFUL << DSI_PCONFR_SW_TIME_Pos)       /*!< 0x0000FF00 */

+#define DSI_PCONFR_SW_TIME            DSI_PCONFR_SW_TIME_Msk                   /*!< Stop Wait Time */

+#define DSI_PCONFR_SW_TIME0_Pos       (8U)

+#define DSI_PCONFR_SW_TIME0_Msk       (0x1UL << DSI_PCONFR_SW_TIME0_Pos)       /*!< 0x00000100 */

+#define DSI_PCONFR_SW_TIME0           DSI_PCONFR_SW_TIME0_Msk

+#define DSI_PCONFR_SW_TIME1_Pos       (9U)

+#define DSI_PCONFR_SW_TIME1_Msk       (0x1UL << DSI_PCONFR_SW_TIME1_Pos)       /*!< 0x00000200 */

+#define DSI_PCONFR_SW_TIME1           DSI_PCONFR_SW_TIME1_Msk

+#define DSI_PCONFR_SW_TIME2_Pos       (10U)

+#define DSI_PCONFR_SW_TIME2_Msk       (0x1UL << DSI_PCONFR_SW_TIME2_Pos)       /*!< 0x00000400 */

+#define DSI_PCONFR_SW_TIME2           DSI_PCONFR_SW_TIME2_Msk

+#define DSI_PCONFR_SW_TIME3_Pos       (11U)

+#define DSI_PCONFR_SW_TIME3_Msk       (0x1UL << DSI_PCONFR_SW_TIME3_Pos)       /*!< 0x00000800 */

+#define DSI_PCONFR_SW_TIME3           DSI_PCONFR_SW_TIME3_Msk

+#define DSI_PCONFR_SW_TIME4_Pos       (12U)

+#define DSI_PCONFR_SW_TIME4_Msk       (0x1UL << DSI_PCONFR_SW_TIME4_Pos)       /*!< 0x00001000 */

+#define DSI_PCONFR_SW_TIME4           DSI_PCONFR_SW_TIME4_Msk

+#define DSI_PCONFR_SW_TIME5_Pos       (13U)

+#define DSI_PCONFR_SW_TIME5_Msk       (0x1UL << DSI_PCONFR_SW_TIME5_Pos)       /*!< 0x00002000 */

+#define DSI_PCONFR_SW_TIME5           DSI_PCONFR_SW_TIME5_Msk

+#define DSI_PCONFR_SW_TIME6_Pos       (14U)

+#define DSI_PCONFR_SW_TIME6_Msk       (0x1UL << DSI_PCONFR_SW_TIME6_Pos)       /*!< 0x00004000 */

+#define DSI_PCONFR_SW_TIME6           DSI_PCONFR_SW_TIME6_Msk

+#define DSI_PCONFR_SW_TIME7_Pos       (15U)

+#define DSI_PCONFR_SW_TIME7_Msk       (0x1UL << DSI_PCONFR_SW_TIME7_Pos)       /*!< 0x00008000 */

+#define DSI_PCONFR_SW_TIME7           DSI_PCONFR_SW_TIME7_Msk

+

+/*******************  Bit definition for DSI_PUCR register  ***************/

+#define DSI_PUCR_URCL_Pos             (0U)

+#define DSI_PUCR_URCL_Msk             (0x1UL << DSI_PUCR_URCL_Pos)             /*!< 0x00000001 */

+#define DSI_PUCR_URCL                 DSI_PUCR_URCL_Msk                        /*!< ULPS Request on Clock Lane */

+#define DSI_PUCR_UECL_Pos             (1U)

+#define DSI_PUCR_UECL_Msk             (0x1UL << DSI_PUCR_UECL_Pos)             /*!< 0x00000002 */

+#define DSI_PUCR_UECL                 DSI_PUCR_UECL_Msk                        /*!< ULPS Exit on Clock Lane */

+#define DSI_PUCR_URDL_Pos             (2U)

+#define DSI_PUCR_URDL_Msk             (0x1UL << DSI_PUCR_URDL_Pos)             /*!< 0x00000004 */

+#define DSI_PUCR_URDL                 DSI_PUCR_URDL_Msk                        /*!< ULPS Request on Data Lane */

+#define DSI_PUCR_UEDL_Pos             (3U)

+#define DSI_PUCR_UEDL_Msk             (0x1UL << DSI_PUCR_UEDL_Pos)             /*!< 0x00000008 */

+#define DSI_PUCR_UEDL                 DSI_PUCR_UEDL_Msk                        /*!< ULPS Exit on Data Lane */

+

+/*******************  Bit definition for DSI_PTTCR register  **************/

+#define DSI_PTTCR_TX_TRIG_Pos         (0U)

+#define DSI_PTTCR_TX_TRIG_Msk         (0xFUL << DSI_PTTCR_TX_TRIG_Pos)         /*!< 0x0000000F */

+#define DSI_PTTCR_TX_TRIG             DSI_PTTCR_TX_TRIG_Msk                    /*!< Transmission Trigger */

+#define DSI_PTTCR_TX_TRIG0_Pos        (0U)

+#define DSI_PTTCR_TX_TRIG0_Msk        (0x1UL << DSI_PTTCR_TX_TRIG0_Pos)        /*!< 0x00000001 */

+#define DSI_PTTCR_TX_TRIG0            DSI_PTTCR_TX_TRIG0_Msk

+#define DSI_PTTCR_TX_TRIG1_Pos        (1U)

+#define DSI_PTTCR_TX_TRIG1_Msk        (0x1UL << DSI_PTTCR_TX_TRIG1_Pos)        /*!< 0x00000002 */

+#define DSI_PTTCR_TX_TRIG1            DSI_PTTCR_TX_TRIG1_Msk

+#define DSI_PTTCR_TX_TRIG2_Pos        (2U)

+#define DSI_PTTCR_TX_TRIG2_Msk        (0x1UL << DSI_PTTCR_TX_TRIG2_Pos)        /*!< 0x00000004 */

+#define DSI_PTTCR_TX_TRIG2            DSI_PTTCR_TX_TRIG2_Msk

+#define DSI_PTTCR_TX_TRIG3_Pos        (3U)

+#define DSI_PTTCR_TX_TRIG3_Msk        (0x1UL << DSI_PTTCR_TX_TRIG3_Pos)        /*!< 0x00000008 */

+#define DSI_PTTCR_TX_TRIG3            DSI_PTTCR_TX_TRIG3_Msk

+

+/*******************  Bit definition for DSI_PSR register  ****************/

+#define DSI_PSR_PD_Pos                (1U)

+#define DSI_PSR_PD_Msk                (0x1UL << DSI_PSR_PD_Pos)                /*!< 0x00000002 */

+#define DSI_PSR_PD                    DSI_PSR_PD_Msk                           /*!< PHY Direction */

+#define DSI_PSR_PSSC_Pos              (2U)

+#define DSI_PSR_PSSC_Msk              (0x1UL << DSI_PSR_PSSC_Pos)              /*!< 0x00000004 */

+#define DSI_PSR_PSSC                  DSI_PSR_PSSC_Msk                         /*!< PHY Stop State Clock lane */

+#define DSI_PSR_UANC_Pos              (3U)

+#define DSI_PSR_UANC_Msk              (0x1UL << DSI_PSR_UANC_Pos)              /*!< 0x00000008 */

+#define DSI_PSR_UANC                  DSI_PSR_UANC_Msk                         /*!< ULPS Active Not Clock lane */

+#define DSI_PSR_PSS0_Pos              (4U)

+#define DSI_PSR_PSS0_Msk              (0x1UL << DSI_PSR_PSS0_Pos)              /*!< 0x00000010 */

+#define DSI_PSR_PSS0                  DSI_PSR_PSS0_Msk                         /*!< PHY Stop State lane 0 */

+#define DSI_PSR_UAN0_Pos              (5U)

+#define DSI_PSR_UAN0_Msk              (0x1UL << DSI_PSR_UAN0_Pos)              /*!< 0x00000020 */

+#define DSI_PSR_UAN0                  DSI_PSR_UAN0_Msk                         /*!< ULPS Active Not lane 0 */

+#define DSI_PSR_RUE0_Pos              (6U)

+#define DSI_PSR_RUE0_Msk              (0x1UL << DSI_PSR_RUE0_Pos)              /*!< 0x00000040 */

+#define DSI_PSR_RUE0                  DSI_PSR_RUE0_Msk                         /*!< RX ULPS Escape lane 0 */

+#define DSI_PSR_PSS1_Pos              (7U)

+#define DSI_PSR_PSS1_Msk              (0x1UL << DSI_PSR_PSS1_Pos)              /*!< 0x00000080 */

+#define DSI_PSR_PSS1                  DSI_PSR_PSS1_Msk                         /*!< PHY Stop State lane 1 */

+#define DSI_PSR_UAN1_Pos              (8U)

+#define DSI_PSR_UAN1_Msk              (0x1UL << DSI_PSR_UAN1_Pos)              /*!< 0x00000100 */

+#define DSI_PSR_UAN1                  DSI_PSR_UAN1_Msk                         /*!< ULPS Active Not lane 1 */

+

+/*******************  Bit definition for DSI_ISR0 register  ***************/

+#define DSI_ISR0_AE0_Pos              (0U)

+#define DSI_ISR0_AE0_Msk              (0x1UL << DSI_ISR0_AE0_Pos)              /*!< 0x00000001 */

+#define DSI_ISR0_AE0                  DSI_ISR0_AE0_Msk                         /*!< Acknowledge Error 0 */

+#define DSI_ISR0_AE1_Pos              (1U)

+#define DSI_ISR0_AE1_Msk              (0x1UL << DSI_ISR0_AE1_Pos)              /*!< 0x00000002 */

+#define DSI_ISR0_AE1                  DSI_ISR0_AE1_Msk                         /*!< Acknowledge Error 1 */

+#define DSI_ISR0_AE2_Pos              (2U)

+#define DSI_ISR0_AE2_Msk              (0x1UL << DSI_ISR0_AE2_Pos)              /*!< 0x00000004 */

+#define DSI_ISR0_AE2                  DSI_ISR0_AE2_Msk                         /*!< Acknowledge Error 2 */

+#define DSI_ISR0_AE3_Pos              (3U)

+#define DSI_ISR0_AE3_Msk              (0x1UL << DSI_ISR0_AE3_Pos)              /*!< 0x00000008 */

+#define DSI_ISR0_AE3                  DSI_ISR0_AE3_Msk                         /*!< Acknowledge Error 3 */

+#define DSI_ISR0_AE4_Pos              (4U)

+#define DSI_ISR0_AE4_Msk              (0x1UL << DSI_ISR0_AE4_Pos)              /*!< 0x00000010 */

+#define DSI_ISR0_AE4                  DSI_ISR0_AE4_Msk                         /*!< Acknowledge Error 4 */

+#define DSI_ISR0_AE5_Pos              (5U)

+#define DSI_ISR0_AE5_Msk              (0x1UL << DSI_ISR0_AE5_Pos)              /*!< 0x00000020 */

+#define DSI_ISR0_AE5                  DSI_ISR0_AE5_Msk                         /*!< Acknowledge Error 5 */

+#define DSI_ISR0_AE6_Pos              (6U)

+#define DSI_ISR0_AE6_Msk              (0x1UL << DSI_ISR0_AE6_Pos)              /*!< 0x00000040 */

+#define DSI_ISR0_AE6                  DSI_ISR0_AE6_Msk                         /*!< Acknowledge Error 6 */

+#define DSI_ISR0_AE7_Pos              (7U)

+#define DSI_ISR0_AE7_Msk              (0x1UL << DSI_ISR0_AE7_Pos)              /*!< 0x00000080 */

+#define DSI_ISR0_AE7                  DSI_ISR0_AE7_Msk                         /*!< Acknowledge Error 7 */

+#define DSI_ISR0_AE8_Pos              (8U)

+#define DSI_ISR0_AE8_Msk              (0x1UL << DSI_ISR0_AE8_Pos)              /*!< 0x00000100 */

+#define DSI_ISR0_AE8                  DSI_ISR0_AE8_Msk                         /*!< Acknowledge Error 8 */

+#define DSI_ISR0_AE9_Pos              (9U)

+#define DSI_ISR0_AE9_Msk              (0x1UL << DSI_ISR0_AE9_Pos)              /*!< 0x00000200 */

+#define DSI_ISR0_AE9                  DSI_ISR0_AE9_Msk                         /*!< Acknowledge Error 9 */

+#define DSI_ISR0_AE10_Pos             (10U)

+#define DSI_ISR0_AE10_Msk             (0x1UL << DSI_ISR0_AE10_Pos)             /*!< 0x00000400 */

+#define DSI_ISR0_AE10                 DSI_ISR0_AE10_Msk                        /*!< Acknowledge Error 10 */

+#define DSI_ISR0_AE11_Pos             (11U)

+#define DSI_ISR0_AE11_Msk             (0x1UL << DSI_ISR0_AE11_Pos)             /*!< 0x00000800 */

+#define DSI_ISR0_AE11                 DSI_ISR0_AE11_Msk                        /*!< Acknowledge Error 11 */

+#define DSI_ISR0_AE12_Pos             (12U)

+#define DSI_ISR0_AE12_Msk             (0x1UL << DSI_ISR0_AE12_Pos)             /*!< 0x00001000 */

+#define DSI_ISR0_AE12                 DSI_ISR0_AE12_Msk                        /*!< Acknowledge Error 12 */

+#define DSI_ISR0_AE13_Pos             (13U)

+#define DSI_ISR0_AE13_Msk             (0x1UL << DSI_ISR0_AE13_Pos)             /*!< 0x00002000 */

+#define DSI_ISR0_AE13                 DSI_ISR0_AE13_Msk                        /*!< Acknowledge Error 13 */

+#define DSI_ISR0_AE14_Pos             (14U)

+#define DSI_ISR0_AE14_Msk             (0x1UL << DSI_ISR0_AE14_Pos)             /*!< 0x00004000 */

+#define DSI_ISR0_AE14                 DSI_ISR0_AE14_Msk                        /*!< Acknowledge Error 14 */

+#define DSI_ISR0_AE15_Pos             (15U)

+#define DSI_ISR0_AE15_Msk             (0x1UL << DSI_ISR0_AE15_Pos)             /*!< 0x00008000 */

+#define DSI_ISR0_AE15                 DSI_ISR0_AE15_Msk                        /*!< Acknowledge Error 15 */

+#define DSI_ISR0_PE0_Pos              (16U)

+#define DSI_ISR0_PE0_Msk              (0x1UL << DSI_ISR0_PE0_Pos)              /*!< 0x00010000 */

+#define DSI_ISR0_PE0                  DSI_ISR0_PE0_Msk                         /*!< PHY Error 0 */

+#define DSI_ISR0_PE1_Pos              (17U)

+#define DSI_ISR0_PE1_Msk              (0x1UL << DSI_ISR0_PE1_Pos)              /*!< 0x00020000 */

+#define DSI_ISR0_PE1                  DSI_ISR0_PE1_Msk                         /*!< PHY Error 1 */

+#define DSI_ISR0_PE2_Pos              (18U)

+#define DSI_ISR0_PE2_Msk              (0x1UL << DSI_ISR0_PE2_Pos)              /*!< 0x00040000 */

+#define DSI_ISR0_PE2                  DSI_ISR0_PE2_Msk                         /*!< PHY Error 2 */

+#define DSI_ISR0_PE3_Pos              (19U)

+#define DSI_ISR0_PE3_Msk              (0x1UL << DSI_ISR0_PE3_Pos)              /*!< 0x00080000 */

+#define DSI_ISR0_PE3                  DSI_ISR0_PE3_Msk                         /*!< PHY Error 3 */

+#define DSI_ISR0_PE4_Pos              (20U)

+#define DSI_ISR0_PE4_Msk              (0x1UL << DSI_ISR0_PE4_Pos)              /*!< 0x00100000 */

+#define DSI_ISR0_PE4                  DSI_ISR0_PE4_Msk                         /*!< PHY Error 4 */

+

+/*******************  Bit definition for DSI_ISR1 register  ***************/

+#define DSI_ISR1_TOHSTX_Pos           (0U)

+#define DSI_ISR1_TOHSTX_Msk           (0x1UL << DSI_ISR1_TOHSTX_Pos)           /*!< 0x00000001 */

+#define DSI_ISR1_TOHSTX               DSI_ISR1_TOHSTX_Msk                      /*!< Timeout High-Speed Transmission */

+#define DSI_ISR1_TOLPRX_Pos           (1U)

+#define DSI_ISR1_TOLPRX_Msk           (0x1UL << DSI_ISR1_TOLPRX_Pos)           /*!< 0x00000002 */

+#define DSI_ISR1_TOLPRX               DSI_ISR1_TOLPRX_Msk                      /*!< Timeout Low-Power Reception */

+#define DSI_ISR1_ECCSE_Pos            (2U)

+#define DSI_ISR1_ECCSE_Msk            (0x1UL << DSI_ISR1_ECCSE_Pos)            /*!< 0x00000004 */

+#define DSI_ISR1_ECCSE                DSI_ISR1_ECCSE_Msk                       /*!< ECC Single-bit Error */

+#define DSI_ISR1_ECCME_Pos            (3U)

+#define DSI_ISR1_ECCME_Msk            (0x1UL << DSI_ISR1_ECCME_Pos)            /*!< 0x00000008 */

+#define DSI_ISR1_ECCME                DSI_ISR1_ECCME_Msk                       /*!< ECC Multi-bit Error */

+#define DSI_ISR1_CRCE_Pos             (4U)

+#define DSI_ISR1_CRCE_Msk             (0x1UL << DSI_ISR1_CRCE_Pos)             /*!< 0x00000010 */

+#define DSI_ISR1_CRCE                 DSI_ISR1_CRCE_Msk                        /*!< CRC Error */

+#define DSI_ISR1_PSE_Pos              (5U)

+#define DSI_ISR1_PSE_Msk              (0x1UL << DSI_ISR1_PSE_Pos)              /*!< 0x00000020 */

+#define DSI_ISR1_PSE                  DSI_ISR1_PSE_Msk                         /*!< Packet Size Error */

+#define DSI_ISR1_EOTPE_Pos            (6U)

+#define DSI_ISR1_EOTPE_Msk            (0x1UL << DSI_ISR1_EOTPE_Pos)            /*!< 0x00000040 */

+#define DSI_ISR1_EOTPE                DSI_ISR1_EOTPE_Msk                       /*!< EoTp Error */

+#define DSI_ISR1_LPWRE_Pos            (7U)

+#define DSI_ISR1_LPWRE_Msk            (0x1UL << DSI_ISR1_LPWRE_Pos)            /*!< 0x00000080 */

+#define DSI_ISR1_LPWRE                DSI_ISR1_LPWRE_Msk                       /*!< LTDC Payload Write Error */

+#define DSI_ISR1_GCWRE_Pos            (8U)

+#define DSI_ISR1_GCWRE_Msk            (0x1UL << DSI_ISR1_GCWRE_Pos)            /*!< 0x00000100 */

+#define DSI_ISR1_GCWRE                DSI_ISR1_GCWRE_Msk                       /*!< Generic Command Write Error */

+#define DSI_ISR1_GPWRE_Pos            (9U)

+#define DSI_ISR1_GPWRE_Msk            (0x1UL << DSI_ISR1_GPWRE_Pos)            /*!< 0x00000200 */

+#define DSI_ISR1_GPWRE                DSI_ISR1_GPWRE_Msk                       /*!< Generic Payload Write Error */

+#define DSI_ISR1_GPTXE_Pos            (10U)

+#define DSI_ISR1_GPTXE_Msk            (0x1UL << DSI_ISR1_GPTXE_Pos)            /*!< 0x00000400 */

+#define DSI_ISR1_GPTXE                DSI_ISR1_GPTXE_Msk                       /*!< Generic Payload Transmit Error */

+#define DSI_ISR1_GPRDE_Pos            (11U)

+#define DSI_ISR1_GPRDE_Msk            (0x1UL << DSI_ISR1_GPRDE_Pos)            /*!< 0x00000800 */

+#define DSI_ISR1_GPRDE                DSI_ISR1_GPRDE_Msk                       /*!< Generic Payload Read Error */

+#define DSI_ISR1_GPRXE_Pos            (12U)

+#define DSI_ISR1_GPRXE_Msk            (0x1UL << DSI_ISR1_GPRXE_Pos)            /*!< 0x00001000 */

+#define DSI_ISR1_GPRXE                DSI_ISR1_GPRXE_Msk                       /*!< Generic Payload Receive Error */

+

+/*******************  Bit definition for DSI_IER0 register  ***************/

+#define DSI_IER0_AE0IE_Pos            (0U)

+#define DSI_IER0_AE0IE_Msk            (0x1UL << DSI_IER0_AE0IE_Pos)            /*!< 0x00000001 */

+#define DSI_IER0_AE0IE                DSI_IER0_AE0IE_Msk                       /*!< Acknowledge Error 0 Interrupt Enable */

+#define DSI_IER0_AE1IE_Pos            (1U)

+#define DSI_IER0_AE1IE_Msk            (0x1UL << DSI_IER0_AE1IE_Pos)            /*!< 0x00000002 */

+#define DSI_IER0_AE1IE                DSI_IER0_AE1IE_Msk                       /*!< Acknowledge Error 1 Interrupt Enable */

+#define DSI_IER0_AE2IE_Pos            (2U)

+#define DSI_IER0_AE2IE_Msk            (0x1UL << DSI_IER0_AE2IE_Pos)            /*!< 0x00000004 */

+#define DSI_IER0_AE2IE                DSI_IER0_AE2IE_Msk                       /*!< Acknowledge Error 2 Interrupt Enable */

+#define DSI_IER0_AE3IE_Pos            (3U)

+#define DSI_IER0_AE3IE_Msk            (0x1UL << DSI_IER0_AE3IE_Pos)            /*!< 0x00000008 */

+#define DSI_IER0_AE3IE                DSI_IER0_AE3IE_Msk                       /*!< Acknowledge Error 3 Interrupt Enable */

+#define DSI_IER0_AE4IE_Pos            (4U)

+#define DSI_IER0_AE4IE_Msk            (0x1UL << DSI_IER0_AE4IE_Pos)            /*!< 0x00000010 */

+#define DSI_IER0_AE4IE                DSI_IER0_AE4IE_Msk                       /*!< Acknowledge Error 4 Interrupt Enable */

+#define DSI_IER0_AE5IE_Pos            (5U)

+#define DSI_IER0_AE5IE_Msk            (0x1UL << DSI_IER0_AE5IE_Pos)            /*!< 0x00000020 */

+#define DSI_IER0_AE5IE                DSI_IER0_AE5IE_Msk                       /*!< Acknowledge Error 5 Interrupt Enable */

+#define DSI_IER0_AE6IE_Pos            (6U)

+#define DSI_IER0_AE6IE_Msk            (0x1UL << DSI_IER0_AE6IE_Pos)            /*!< 0x00000040 */

+#define DSI_IER0_AE6IE                DSI_IER0_AE6IE_Msk                       /*!< Acknowledge Error 6 Interrupt Enable */

+#define DSI_IER0_AE7IE_Pos            (7U)

+#define DSI_IER0_AE7IE_Msk            (0x1UL << DSI_IER0_AE7IE_Pos)            /*!< 0x00000080 */

+#define DSI_IER0_AE7IE                DSI_IER0_AE7IE_Msk                       /*!< Acknowledge Error 7 Interrupt Enable */

+#define DSI_IER0_AE8IE_Pos            (8U)

+#define DSI_IER0_AE8IE_Msk            (0x1UL << DSI_IER0_AE8IE_Pos)            /*!< 0x00000100 */

+#define DSI_IER0_AE8IE                DSI_IER0_AE8IE_Msk                       /*!< Acknowledge Error 8 Interrupt Enable */

+#define DSI_IER0_AE9IE_Pos            (9U)

+#define DSI_IER0_AE9IE_Msk            (0x1UL << DSI_IER0_AE9IE_Pos)            /*!< 0x00000200 */

+#define DSI_IER0_AE9IE                DSI_IER0_AE9IE_Msk                       /*!< Acknowledge Error 9 Interrupt Enable */

+#define DSI_IER0_AE10IE_Pos           (10U)

+#define DSI_IER0_AE10IE_Msk           (0x1UL << DSI_IER0_AE10IE_Pos)           /*!< 0x00000400 */

+#define DSI_IER0_AE10IE               DSI_IER0_AE10IE_Msk                      /*!< Acknowledge Error 10 Interrupt Enable */

+#define DSI_IER0_AE11IE_Pos           (11U)

+#define DSI_IER0_AE11IE_Msk           (0x1UL << DSI_IER0_AE11IE_Pos)           /*!< 0x00000800 */

+#define DSI_IER0_AE11IE               DSI_IER0_AE11IE_Msk                      /*!< Acknowledge Error 11 Interrupt Enable */

+#define DSI_IER0_AE12IE_Pos           (12U)

+#define DSI_IER0_AE12IE_Msk           (0x1UL << DSI_IER0_AE12IE_Pos)           /*!< 0x00001000 */

+#define DSI_IER0_AE12IE               DSI_IER0_AE12IE_Msk                      /*!< Acknowledge Error 12 Interrupt Enable */

+#define DSI_IER0_AE13IE_Pos           (13U)

+#define DSI_IER0_AE13IE_Msk           (0x1UL << DSI_IER0_AE13IE_Pos)           /*!< 0x00002000 */

+#define DSI_IER0_AE13IE               DSI_IER0_AE13IE_Msk                      /*!< Acknowledge Error 13 Interrupt Enable */

+#define DSI_IER0_AE14IE_Pos           (14U)

+#define DSI_IER0_AE14IE_Msk           (0x1UL << DSI_IER0_AE14IE_Pos)           /*!< 0x00004000 */

+#define DSI_IER0_AE14IE               DSI_IER0_AE14IE_Msk                      /*!< Acknowledge Error 14 Interrupt Enable */

+#define DSI_IER0_AE15IE_Pos           (15U)

+#define DSI_IER0_AE15IE_Msk           (0x1UL << DSI_IER0_AE15IE_Pos)           /*!< 0x00008000 */

+#define DSI_IER0_AE15IE               DSI_IER0_AE15IE_Msk                      /*!< Acknowledge Error 15 Interrupt Enable */

+#define DSI_IER0_PE0IE_Pos            (16U)

+#define DSI_IER0_PE0IE_Msk            (0x1UL << DSI_IER0_PE0IE_Pos)            /*!< 0x00010000 */

+#define DSI_IER0_PE0IE                DSI_IER0_PE0IE_Msk                       /*!< PHY Error 0 Interrupt Enable */

+#define DSI_IER0_PE1IE_Pos            (17U)

+#define DSI_IER0_PE1IE_Msk            (0x1UL << DSI_IER0_PE1IE_Pos)            /*!< 0x00020000 */

+#define DSI_IER0_PE1IE                DSI_IER0_PE1IE_Msk                       /*!< PHY Error 1 Interrupt Enable */

+#define DSI_IER0_PE2IE_Pos            (18U)

+#define DSI_IER0_PE2IE_Msk            (0x1UL << DSI_IER0_PE2IE_Pos)            /*!< 0x00040000 */

+#define DSI_IER0_PE2IE                DSI_IER0_PE2IE_Msk                       /*!< PHY Error 2 Interrupt Enable */

+#define DSI_IER0_PE3IE_Pos            (19U)

+#define DSI_IER0_PE3IE_Msk            (0x1UL << DSI_IER0_PE3IE_Pos)            /*!< 0x00080000 */

+#define DSI_IER0_PE3IE                DSI_IER0_PE3IE_Msk                       /*!< PHY Error 3 Interrupt Enable */

+#define DSI_IER0_PE4IE_Pos            (20U)

+#define DSI_IER0_PE4IE_Msk            (0x1UL << DSI_IER0_PE4IE_Pos)            /*!< 0x00100000 */

+#define DSI_IER0_PE4IE                DSI_IER0_PE4IE_Msk                       /*!< PHY Error 4 Interrupt Enable */

+

+/*******************  Bit definition for DSI_IER1 register  ***************/

+#define DSI_IER1_TOHSTXIE_Pos         (0U)

+#define DSI_IER1_TOHSTXIE_Msk         (0x1UL << DSI_IER1_TOHSTXIE_Pos)         /*!< 0x00000001 */

+#define DSI_IER1_TOHSTXIE             DSI_IER1_TOHSTXIE_Msk                    /*!< Timeout High-Speed Transmission Interrupt Enable */

+#define DSI_IER1_TOLPRXIE_Pos         (1U)

+#define DSI_IER1_TOLPRXIE_Msk         (0x1UL << DSI_IER1_TOLPRXIE_Pos)         /*!< 0x00000002 */

+#define DSI_IER1_TOLPRXIE             DSI_IER1_TOLPRXIE_Msk                    /*!< Timeout Low-Power Reception Interrupt Enable */

+#define DSI_IER1_ECCSEIE_Pos          (2U)

+#define DSI_IER1_ECCSEIE_Msk          (0x1UL << DSI_IER1_ECCSEIE_Pos)          /*!< 0x00000004 */

+#define DSI_IER1_ECCSEIE              DSI_IER1_ECCSEIE_Msk                     /*!< ECC Single-bit Error Interrupt Enable */

+#define DSI_IER1_ECCMEIE_Pos          (3U)

+#define DSI_IER1_ECCMEIE_Msk          (0x1UL << DSI_IER1_ECCMEIE_Pos)          /*!< 0x00000008 */

+#define DSI_IER1_ECCMEIE              DSI_IER1_ECCMEIE_Msk                     /*!< ECC Multi-bit Error Interrupt Enable */

+#define DSI_IER1_CRCEIE_Pos           (4U)

+#define DSI_IER1_CRCEIE_Msk           (0x1UL << DSI_IER1_CRCEIE_Pos)           /*!< 0x00000010 */

+#define DSI_IER1_CRCEIE               DSI_IER1_CRCEIE_Msk                      /*!< CRC Error Interrupt Enable */

+#define DSI_IER1_PSEIE_Pos            (5U)

+#define DSI_IER1_PSEIE_Msk            (0x1UL << DSI_IER1_PSEIE_Pos)            /*!< 0x00000020 */

+#define DSI_IER1_PSEIE                DSI_IER1_PSEIE_Msk                       /*!< Packet Size Error Interrupt Enable */

+#define DSI_IER1_EOTPEIE_Pos          (6U)

+#define DSI_IER1_EOTPEIE_Msk          (0x1UL << DSI_IER1_EOTPEIE_Pos)          /*!< 0x00000040 */

+#define DSI_IER1_EOTPEIE              DSI_IER1_EOTPEIE_Msk                     /*!< EoTp Error Interrupt Enable */

+#define DSI_IER1_LPWREIE_Pos          (7U)

+#define DSI_IER1_LPWREIE_Msk          (0x1UL << DSI_IER1_LPWREIE_Pos)          /*!< 0x00000080 */

+#define DSI_IER1_LPWREIE              DSI_IER1_LPWREIE_Msk                     /*!< LTDC Payload Write Error Interrupt Enable */

+#define DSI_IER1_GCWREIE_Pos          (8U)

+#define DSI_IER1_GCWREIE_Msk          (0x1UL << DSI_IER1_GCWREIE_Pos)          /*!< 0x00000100 */

+#define DSI_IER1_GCWREIE              DSI_IER1_GCWREIE_Msk                     /*!< Generic Command Write Error Interrupt Enable */

+#define DSI_IER1_GPWREIE_Pos          (9U)

+#define DSI_IER1_GPWREIE_Msk          (0x1UL << DSI_IER1_GPWREIE_Pos)          /*!< 0x00000200 */

+#define DSI_IER1_GPWREIE              DSI_IER1_GPWREIE_Msk                     /*!< Generic Payload Write Error Interrupt Enable */

+#define DSI_IER1_GPTXEIE_Pos          (10U)

+#define DSI_IER1_GPTXEIE_Msk          (0x1UL << DSI_IER1_GPTXEIE_Pos)          /*!< 0x00000400 */

+#define DSI_IER1_GPTXEIE              DSI_IER1_GPTXEIE_Msk                     /*!< Generic Payload Transmit Error Interrupt Enable */

+#define DSI_IER1_GPRDEIE_Pos          (11U)

+#define DSI_IER1_GPRDEIE_Msk          (0x1UL << DSI_IER1_GPRDEIE_Pos)          /*!< 0x00000800 */

+#define DSI_IER1_GPRDEIE              DSI_IER1_GPRDEIE_Msk                     /*!< Generic Payload Read Error Interrupt Enable */

+#define DSI_IER1_GPRXEIE_Pos          (12U)

+#define DSI_IER1_GPRXEIE_Msk          (0x1UL << DSI_IER1_GPRXEIE_Pos)          /*!< 0x00001000 */

+#define DSI_IER1_GPRXEIE              DSI_IER1_GPRXEIE_Msk                     /*!< Generic Payload Receive Error Interrupt Enable */

+

+/*******************  Bit definition for DSI_FIR0 register  ***************/

+#define DSI_FIR0_FAE0_Pos             (0U)

+#define DSI_FIR0_FAE0_Msk             (0x1UL << DSI_FIR0_FAE0_Pos)             /*!< 0x00000001 */

+#define DSI_FIR0_FAE0                 DSI_FIR0_FAE0_Msk                        /*!< Force Acknowledge Error 0 */

+#define DSI_FIR0_FAE1_Pos             (1U)

+#define DSI_FIR0_FAE1_Msk             (0x1UL << DSI_FIR0_FAE1_Pos)             /*!< 0x00000002 */

+#define DSI_FIR0_FAE1                 DSI_FIR0_FAE1_Msk                        /*!< Force Acknowledge Error 1 */

+#define DSI_FIR0_FAE2_Pos             (2U)

+#define DSI_FIR0_FAE2_Msk             (0x1UL << DSI_FIR0_FAE2_Pos)             /*!< 0x00000004 */

+#define DSI_FIR0_FAE2                 DSI_FIR0_FAE2_Msk                        /*!< Force Acknowledge Error 2 */

+#define DSI_FIR0_FAE3_Pos             (3U)

+#define DSI_FIR0_FAE3_Msk             (0x1UL << DSI_FIR0_FAE3_Pos)             /*!< 0x00000008 */

+#define DSI_FIR0_FAE3                 DSI_FIR0_FAE3_Msk                        /*!< Force Acknowledge Error 3 */

+#define DSI_FIR0_FAE4_Pos             (4U)

+#define DSI_FIR0_FAE4_Msk             (0x1UL << DSI_FIR0_FAE4_Pos)             /*!< 0x00000010 */

+#define DSI_FIR0_FAE4                 DSI_FIR0_FAE4_Msk                        /*!< Force Acknowledge Error 4 */

+#define DSI_FIR0_FAE5_Pos             (5U)

+#define DSI_FIR0_FAE5_Msk             (0x1UL << DSI_FIR0_FAE5_Pos)             /*!< 0x00000020 */

+#define DSI_FIR0_FAE5                 DSI_FIR0_FAE5_Msk                        /*!< Force Acknowledge Error 5 */

+#define DSI_FIR0_FAE6_Pos             (6U)

+#define DSI_FIR0_FAE6_Msk             (0x1UL << DSI_FIR0_FAE6_Pos)             /*!< 0x00000040 */

+#define DSI_FIR0_FAE6                 DSI_FIR0_FAE6_Msk                        /*!< Force Acknowledge Error 6 */

+#define DSI_FIR0_FAE7_Pos             (7U)

+#define DSI_FIR0_FAE7_Msk             (0x1UL << DSI_FIR0_FAE7_Pos)             /*!< 0x00000080 */

+#define DSI_FIR0_FAE7                 DSI_FIR0_FAE7_Msk                        /*!< Force Acknowledge Error 7 */

+#define DSI_FIR0_FAE8_Pos             (8U)

+#define DSI_FIR0_FAE8_Msk             (0x1UL << DSI_FIR0_FAE8_Pos)             /*!< 0x00000100 */

+#define DSI_FIR0_FAE8                 DSI_FIR0_FAE8_Msk                        /*!< Force Acknowledge Error 8 */

+#define DSI_FIR0_FAE9_Pos             (9U)

+#define DSI_FIR0_FAE9_Msk             (0x1UL << DSI_FIR0_FAE9_Pos)             /*!< 0x00000200 */

+#define DSI_FIR0_FAE9                 DSI_FIR0_FAE9_Msk                        /*!< Force Acknowledge Error 9 */

+#define DSI_FIR0_FAE10_Pos            (10U)

+#define DSI_FIR0_FAE10_Msk            (0x1UL << DSI_FIR0_FAE10_Pos)            /*!< 0x00000400 */

+#define DSI_FIR0_FAE10                DSI_FIR0_FAE10_Msk                       /*!< Force Acknowledge Error 10 */

+#define DSI_FIR0_FAE11_Pos            (11U)

+#define DSI_FIR0_FAE11_Msk            (0x1UL << DSI_FIR0_FAE11_Pos)            /*!< 0x00000800 */

+#define DSI_FIR0_FAE11                DSI_FIR0_FAE11_Msk                       /*!< Force Acknowledge Error 11 */

+#define DSI_FIR0_FAE12_Pos            (12U)

+#define DSI_FIR0_FAE12_Msk            (0x1UL << DSI_FIR0_FAE12_Pos)            /*!< 0x00001000 */

+#define DSI_FIR0_FAE12                DSI_FIR0_FAE12_Msk                       /*!< Force Acknowledge Error 12 */

+#define DSI_FIR0_FAE13_Pos            (13U)

+#define DSI_FIR0_FAE13_Msk            (0x1UL << DSI_FIR0_FAE13_Pos)            /*!< 0x00002000 */

+#define DSI_FIR0_FAE13                DSI_FIR0_FAE13_Msk                       /*!< Force Acknowledge Error 13 */

+#define DSI_FIR0_FAE14_Pos            (14U)

+#define DSI_FIR0_FAE14_Msk            (0x1UL << DSI_FIR0_FAE14_Pos)            /*!< 0x00004000 */

+#define DSI_FIR0_FAE14                DSI_FIR0_FAE14_Msk                       /*!< Force Acknowledge Error 14 */

+#define DSI_FIR0_FAE15_Pos            (15U)

+#define DSI_FIR0_FAE15_Msk            (0x1UL << DSI_FIR0_FAE15_Pos)            /*!< 0x00008000 */

+#define DSI_FIR0_FAE15                DSI_FIR0_FAE15_Msk                       /*!< Force Acknowledge Error 15 */

+#define DSI_FIR0_FPE0_Pos             (16U)

+#define DSI_FIR0_FPE0_Msk             (0x1UL << DSI_FIR0_FPE0_Pos)             /*!< 0x00010000 */

+#define DSI_FIR0_FPE0                 DSI_FIR0_FPE0_Msk                        /*!< Force PHY Error 0 */

+#define DSI_FIR0_FPE1_Pos             (17U)

+#define DSI_FIR0_FPE1_Msk             (0x1UL << DSI_FIR0_FPE1_Pos)             /*!< 0x00020000 */

+#define DSI_FIR0_FPE1                 DSI_FIR0_FPE1_Msk                        /*!< Force PHY Error 1 */

+#define DSI_FIR0_FPE2_Pos             (18U)

+#define DSI_FIR0_FPE2_Msk             (0x1UL << DSI_FIR0_FPE2_Pos)             /*!< 0x00040000 */

+#define DSI_FIR0_FPE2                 DSI_FIR0_FPE2_Msk                        /*!< Force PHY Error 2 */

+#define DSI_FIR0_FPE3_Pos             (19U)

+#define DSI_FIR0_FPE3_Msk             (0x1UL << DSI_FIR0_FPE3_Pos)             /*!< 0x00080000 */

+#define DSI_FIR0_FPE3                 DSI_FIR0_FPE3_Msk                        /*!< Force PHY Error 3 */

+#define DSI_FIR0_FPE4_Pos             (20U)

+#define DSI_FIR0_FPE4_Msk             (0x1UL << DSI_FIR0_FPE4_Pos)             /*!< 0x00100000 */

+#define DSI_FIR0_FPE4                 DSI_FIR0_FPE4_Msk                        /*!< Force PHY Error 4 */

+

+/*******************  Bit definition for DSI_FIR1 register  ***************/

+#define DSI_FIR1_FTOHSTX_Pos          (0U)

+#define DSI_FIR1_FTOHSTX_Msk          (0x1UL << DSI_FIR1_FTOHSTX_Pos)          /*!< 0x00000001 */

+#define DSI_FIR1_FTOHSTX              DSI_FIR1_FTOHSTX_Msk                     /*!< Force Timeout High-Speed Transmission */

+#define DSI_FIR1_FTOLPRX_Pos          (1U)

+#define DSI_FIR1_FTOLPRX_Msk          (0x1UL << DSI_FIR1_FTOLPRX_Pos)          /*!< 0x00000002 */

+#define DSI_FIR1_FTOLPRX              DSI_FIR1_FTOLPRX_Msk                     /*!< Force Timeout Low-Power Reception */

+#define DSI_FIR1_FECCSE_Pos           (2U)

+#define DSI_FIR1_FECCSE_Msk           (0x1UL << DSI_FIR1_FECCSE_Pos)           /*!< 0x00000004 */

+#define DSI_FIR1_FECCSE               DSI_FIR1_FECCSE_Msk                      /*!< Force ECC Single-bit Error */

+#define DSI_FIR1_FECCME_Pos           (3U)

+#define DSI_FIR1_FECCME_Msk           (0x1UL << DSI_FIR1_FECCME_Pos)           /*!< 0x00000008 */

+#define DSI_FIR1_FECCME               DSI_FIR1_FECCME_Msk                      /*!< Force ECC Multi-bit Error */

+#define DSI_FIR1_FCRCE_Pos            (4U)

+#define DSI_FIR1_FCRCE_Msk            (0x1UL << DSI_FIR1_FCRCE_Pos)            /*!< 0x00000010 */

+#define DSI_FIR1_FCRCE                DSI_FIR1_FCRCE_Msk                       /*!< Force CRC Error */

+#define DSI_FIR1_FPSE_Pos             (5U)

+#define DSI_FIR1_FPSE_Msk             (0x1UL << DSI_FIR1_FPSE_Pos)             /*!< 0x00000020 */

+#define DSI_FIR1_FPSE                 DSI_FIR1_FPSE_Msk                        /*!< Force Packet Size Error */

+#define DSI_FIR1_FEOTPE_Pos           (6U)

+#define DSI_FIR1_FEOTPE_Msk           (0x1UL << DSI_FIR1_FEOTPE_Pos)           /*!< 0x00000040 */

+#define DSI_FIR1_FEOTPE               DSI_FIR1_FEOTPE_Msk                      /*!< Force EoTp Error */

+#define DSI_FIR1_FLPWRE_Pos           (7U)

+#define DSI_FIR1_FLPWRE_Msk           (0x1UL << DSI_FIR1_FLPWRE_Pos)           /*!< 0x00000080 */

+#define DSI_FIR1_FLPWRE               DSI_FIR1_FLPWRE_Msk                      /*!< Force LTDC Payload Write Error */

+#define DSI_FIR1_FGCWRE_Pos           (8U)

+#define DSI_FIR1_FGCWRE_Msk           (0x1UL << DSI_FIR1_FGCWRE_Pos)           /*!< 0x00000100 */

+#define DSI_FIR1_FGCWRE               DSI_FIR1_FGCWRE_Msk                      /*!< Force Generic Command Write Error */

+#define DSI_FIR1_FGPWRE_Pos           (9U)

+#define DSI_FIR1_FGPWRE_Msk           (0x1UL << DSI_FIR1_FGPWRE_Pos)           /*!< 0x00000200 */

+#define DSI_FIR1_FGPWRE               DSI_FIR1_FGPWRE_Msk                      /*!< Force Generic Payload Write Error */

+#define DSI_FIR1_FGPTXE_Pos           (10U)

+#define DSI_FIR1_FGPTXE_Msk           (0x1UL << DSI_FIR1_FGPTXE_Pos)           /*!< 0x00000400 */

+#define DSI_FIR1_FGPTXE               DSI_FIR1_FGPTXE_Msk                      /*!< Force Generic Payload Transmit Error */

+#define DSI_FIR1_FGPRDE_Pos           (11U)

+#define DSI_FIR1_FGPRDE_Msk           (0x1UL << DSI_FIR1_FGPRDE_Pos)           /*!< 0x00000800 */

+#define DSI_FIR1_FGPRDE               DSI_FIR1_FGPRDE_Msk                      /*!< Force Generic Payload Read Error */

+#define DSI_FIR1_FGPRXE_Pos           (12U)

+#define DSI_FIR1_FGPRXE_Msk           (0x1UL << DSI_FIR1_FGPRXE_Pos)           /*!< 0x00001000 */

+#define DSI_FIR1_FGPRXE               DSI_FIR1_FGPRXE_Msk                      /*!< Force Generic Payload Receive Error */

+

+/*******************  Bit definition for DSI_VSCR register  ***************/

+#define DSI_VSCR_EN_Pos               (0U)

+#define DSI_VSCR_EN_Msk               (0x1UL << DSI_VSCR_EN_Pos)               /*!< 0x00000001 */

+#define DSI_VSCR_EN                   DSI_VSCR_EN_Msk                          /*!< Enable */

+#define DSI_VSCR_UR_Pos               (8U)

+#define DSI_VSCR_UR_Msk               (0x1UL << DSI_VSCR_UR_Pos)               /*!< 0x00000100 */

+#define DSI_VSCR_UR                   DSI_VSCR_UR_Msk                          /*!< Update Register */

+

+/*******************  Bit definition for DSI_LCVCIDR register  ************/

+#define DSI_LCVCIDR_VCID_Pos          (0U)

+#define DSI_LCVCIDR_VCID_Msk          (0x3UL << DSI_LCVCIDR_VCID_Pos)          /*!< 0x00000003 */

+#define DSI_LCVCIDR_VCID              DSI_LCVCIDR_VCID_Msk                     /*!< Virtual Channel ID */

+#define DSI_LCVCIDR_VCID0_Pos         (0U)

+#define DSI_LCVCIDR_VCID0_Msk         (0x1UL << DSI_LCVCIDR_VCID0_Pos)         /*!< 0x00000001 */

+#define DSI_LCVCIDR_VCID0             DSI_LCVCIDR_VCID0_Msk

+#define DSI_LCVCIDR_VCID1_Pos         (1U)

+#define DSI_LCVCIDR_VCID1_Msk         (0x1UL << DSI_LCVCIDR_VCID1_Pos)         /*!< 0x00000002 */

+#define DSI_LCVCIDR_VCID1             DSI_LCVCIDR_VCID1_Msk

+

+/*******************  Bit definition for DSI_LCCCR register  **************/

+#define DSI_LCCCR_COLC_Pos            (0U)

+#define DSI_LCCCR_COLC_Msk            (0xFUL << DSI_LCCCR_COLC_Pos)            /*!< 0x0000000F */

+#define DSI_LCCCR_COLC                DSI_LCCCR_COLC_Msk                       /*!< Color Coding */

+#define DSI_LCCCR_COLC0_Pos           (0U)

+#define DSI_LCCCR_COLC0_Msk           (0x1UL << DSI_LCCCR_COLC0_Pos)           /*!< 0x00000001 */

+#define DSI_LCCCR_COLC0               DSI_LCCCR_COLC0_Msk

+#define DSI_LCCCR_COLC1_Pos           (1U)

+#define DSI_LCCCR_COLC1_Msk           (0x1UL << DSI_LCCCR_COLC1_Pos)           /*!< 0x00000002 */

+#define DSI_LCCCR_COLC1               DSI_LCCCR_COLC1_Msk

+#define DSI_LCCCR_COLC2_Pos           (2U)

+#define DSI_LCCCR_COLC2_Msk           (0x1UL << DSI_LCCCR_COLC2_Pos)           /*!< 0x00000004 */

+#define DSI_LCCCR_COLC2               DSI_LCCCR_COLC2_Msk

+#define DSI_LCCCR_COLC3_Pos           (3U)

+#define DSI_LCCCR_COLC3_Msk           (0x1UL << DSI_LCCCR_COLC3_Pos)           /*!< 0x00000008 */

+#define DSI_LCCCR_COLC3               DSI_LCCCR_COLC3_Msk

+

+#define DSI_LCCCR_LPE_Pos             (8U)

+#define DSI_LCCCR_LPE_Msk             (0x1UL << DSI_LCCCR_LPE_Pos)             /*!< 0x00000100 */

+#define DSI_LCCCR_LPE                 DSI_LCCCR_LPE_Msk                        /*!< Loosely Packed Enable */

+

+/*******************  Bit definition for DSI_LPMCCR register  *************/

+#define DSI_LPMCCR_VLPSIZE_Pos        (0U)

+#define DSI_LPMCCR_VLPSIZE_Msk        (0xFFUL << DSI_LPMCCR_VLPSIZE_Pos)       /*!< 0x000000FF */

+#define DSI_LPMCCR_VLPSIZE            DSI_LPMCCR_VLPSIZE_Msk                   /*!< VACT Largest Packet Size */

+#define DSI_LPMCCR_VLPSIZE0_Pos       (0U)

+#define DSI_LPMCCR_VLPSIZE0_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE0_Pos)       /*!< 0x00000001 */

+#define DSI_LPMCCR_VLPSIZE0           DSI_LPMCCR_VLPSIZE0_Msk

+#define DSI_LPMCCR_VLPSIZE1_Pos       (1U)

+#define DSI_LPMCCR_VLPSIZE1_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE1_Pos)       /*!< 0x00000002 */

+#define DSI_LPMCCR_VLPSIZE1           DSI_LPMCCR_VLPSIZE1_Msk

+#define DSI_LPMCCR_VLPSIZE2_Pos       (2U)

+#define DSI_LPMCCR_VLPSIZE2_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE2_Pos)       /*!< 0x00000004 */

+#define DSI_LPMCCR_VLPSIZE2           DSI_LPMCCR_VLPSIZE2_Msk

+#define DSI_LPMCCR_VLPSIZE3_Pos       (3U)

+#define DSI_LPMCCR_VLPSIZE3_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE3_Pos)       /*!< 0x00000008 */

+#define DSI_LPMCCR_VLPSIZE3           DSI_LPMCCR_VLPSIZE3_Msk

+#define DSI_LPMCCR_VLPSIZE4_Pos       (4U)

+#define DSI_LPMCCR_VLPSIZE4_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE4_Pos)       /*!< 0x00000010 */

+#define DSI_LPMCCR_VLPSIZE4           DSI_LPMCCR_VLPSIZE4_Msk

+#define DSI_LPMCCR_VLPSIZE5_Pos       (5U)

+#define DSI_LPMCCR_VLPSIZE5_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE5_Pos)       /*!< 0x00000020 */

+#define DSI_LPMCCR_VLPSIZE5           DSI_LPMCCR_VLPSIZE5_Msk

+#define DSI_LPMCCR_VLPSIZE6_Pos       (6U)

+#define DSI_LPMCCR_VLPSIZE6_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE6_Pos)       /*!< 0x00000040 */

+#define DSI_LPMCCR_VLPSIZE6           DSI_LPMCCR_VLPSIZE6_Msk

+#define DSI_LPMCCR_VLPSIZE7_Pos       (7U)

+#define DSI_LPMCCR_VLPSIZE7_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE7_Pos)       /*!< 0x00000080 */

+#define DSI_LPMCCR_VLPSIZE7           DSI_LPMCCR_VLPSIZE7_Msk

+

+#define DSI_LPMCCR_LPSIZE_Pos         (16U)

+#define DSI_LPMCCR_LPSIZE_Msk         (0xFFUL << DSI_LPMCCR_LPSIZE_Pos)        /*!< 0x00FF0000 */

+#define DSI_LPMCCR_LPSIZE             DSI_LPMCCR_LPSIZE_Msk                    /*!< Largest Packet Size */

+#define DSI_LPMCCR_LPSIZE0_Pos        (16U)

+#define DSI_LPMCCR_LPSIZE0_Msk        (0x1UL << DSI_LPMCCR_LPSIZE0_Pos)        /*!< 0x00010000 */

+#define DSI_LPMCCR_LPSIZE0            DSI_LPMCCR_LPSIZE0_Msk

+#define DSI_LPMCCR_LPSIZE1_Pos        (17U)

+#define DSI_LPMCCR_LPSIZE1_Msk        (0x1UL << DSI_LPMCCR_LPSIZE1_Pos)        /*!< 0x00020000 */

+#define DSI_LPMCCR_LPSIZE1            DSI_LPMCCR_LPSIZE1_Msk

+#define DSI_LPMCCR_LPSIZE2_Pos        (18U)

+#define DSI_LPMCCR_LPSIZE2_Msk        (0x1UL << DSI_LPMCCR_LPSIZE2_Pos)        /*!< 0x00040000 */

+#define DSI_LPMCCR_LPSIZE2            DSI_LPMCCR_LPSIZE2_Msk

+#define DSI_LPMCCR_LPSIZE3_Pos        (19U)

+#define DSI_LPMCCR_LPSIZE3_Msk        (0x1UL << DSI_LPMCCR_LPSIZE3_Pos)        /*!< 0x00080000 */

+#define DSI_LPMCCR_LPSIZE3            DSI_LPMCCR_LPSIZE3_Msk

+#define DSI_LPMCCR_LPSIZE4_Pos        (20U)

+#define DSI_LPMCCR_LPSIZE4_Msk        (0x1UL << DSI_LPMCCR_LPSIZE4_Pos)        /*!< 0x00100000 */

+#define DSI_LPMCCR_LPSIZE4            DSI_LPMCCR_LPSIZE4_Msk

+#define DSI_LPMCCR_LPSIZE5_Pos        (21U)

+#define DSI_LPMCCR_LPSIZE5_Msk        (0x1UL << DSI_LPMCCR_LPSIZE5_Pos)        /*!< 0x00200000 */

+#define DSI_LPMCCR_LPSIZE5            DSI_LPMCCR_LPSIZE5_Msk

+#define DSI_LPMCCR_LPSIZE6_Pos        (22U)

+#define DSI_LPMCCR_LPSIZE6_Msk        (0x1UL << DSI_LPMCCR_LPSIZE6_Pos)        /*!< 0x00400000 */

+#define DSI_LPMCCR_LPSIZE6            DSI_LPMCCR_LPSIZE6_Msk

+#define DSI_LPMCCR_LPSIZE7_Pos        (23U)

+#define DSI_LPMCCR_LPSIZE7_Msk        (0x1UL << DSI_LPMCCR_LPSIZE7_Pos)        /*!< 0x00800000 */

+#define DSI_LPMCCR_LPSIZE7            DSI_LPMCCR_LPSIZE7_Msk

+

+/*******************  Bit definition for DSI_VMCCR register  **************/

+#define DSI_VMCCR_VMT_Pos             (0U)

+#define DSI_VMCCR_VMT_Msk             (0x3UL << DSI_VMCCR_VMT_Pos)             /*!< 0x00000003 */

+#define DSI_VMCCR_VMT                 DSI_VMCCR_VMT_Msk                        /*!< Video Mode Type */

+#define DSI_VMCCR_VMT0_Pos            (0U)

+#define DSI_VMCCR_VMT0_Msk            (0x1UL << DSI_VMCCR_VMT0_Pos)            /*!< 0x00000001 */

+#define DSI_VMCCR_VMT0                DSI_VMCCR_VMT0_Msk

+#define DSI_VMCCR_VMT1_Pos            (1U)

+#define DSI_VMCCR_VMT1_Msk            (0x1UL << DSI_VMCCR_VMT1_Pos)            /*!< 0x00000002 */

+#define DSI_VMCCR_VMT1                DSI_VMCCR_VMT1_Msk

+

+#define DSI_VMCCR_LPVSAE_Pos          (8U)

+#define DSI_VMCCR_LPVSAE_Msk          (0x1UL << DSI_VMCCR_LPVSAE_Pos)          /*!< 0x00000100 */

+#define DSI_VMCCR_LPVSAE              DSI_VMCCR_LPVSAE_Msk                     /*!< Low-power Vertical Sync time Enable */

+#define DSI_VMCCR_LPVBPE_Pos          (9U)

+#define DSI_VMCCR_LPVBPE_Msk          (0x1UL << DSI_VMCCR_LPVBPE_Pos)          /*!< 0x00000200 */

+#define DSI_VMCCR_LPVBPE              DSI_VMCCR_LPVBPE_Msk                     /*!< Low-power Vertical Back-porch Enable */

+#define DSI_VMCCR_LPVFPE_Pos          (10U)

+#define DSI_VMCCR_LPVFPE_Msk          (0x1UL << DSI_VMCCR_LPVFPE_Pos)          /*!< 0x00000400 */

+#define DSI_VMCCR_LPVFPE              DSI_VMCCR_LPVFPE_Msk                     /*!< Low-power Vertical Front-porch Enable */

+#define DSI_VMCCR_LPVAE_Pos           (11U)

+#define DSI_VMCCR_LPVAE_Msk           (0x1UL << DSI_VMCCR_LPVAE_Pos)           /*!< 0x00000800 */

+#define DSI_VMCCR_LPVAE               DSI_VMCCR_LPVAE_Msk                      /*!< Low-power Vertical Active Enable */

+#define DSI_VMCCR_LPHBPE_Pos          (12U)

+#define DSI_VMCCR_LPHBPE_Msk          (0x1UL << DSI_VMCCR_LPHBPE_Pos)          /*!< 0x00001000 */

+#define DSI_VMCCR_LPHBPE              DSI_VMCCR_LPHBPE_Msk                     /*!< Low-power Horizontal Back-porch Enable */

+#define DSI_VMCCR_LPHFE_Pos           (13U)

+#define DSI_VMCCR_LPHFE_Msk           (0x1UL << DSI_VMCCR_LPHFE_Pos)           /*!< 0x00002000 */

+#define DSI_VMCCR_LPHFE               DSI_VMCCR_LPHFE_Msk                      /*!< Low-power Horizontal Front-porch Enable */

+#define DSI_VMCCR_FBTAAE_Pos          (14U)

+#define DSI_VMCCR_FBTAAE_Msk          (0x1UL << DSI_VMCCR_FBTAAE_Pos)          /*!< 0x00004000 */

+#define DSI_VMCCR_FBTAAE              DSI_VMCCR_FBTAAE_Msk                     /*!< Frame BTA Acknowledge Enable */

+#define DSI_VMCCR_LPCE_Pos            (15U)

+#define DSI_VMCCR_LPCE_Msk            (0x1UL << DSI_VMCCR_LPCE_Pos)            /*!< 0x00008000 */

+#define DSI_VMCCR_LPCE                DSI_VMCCR_LPCE_Msk                       /*!< Low-power Command Enable */

+

+/*******************  Bit definition for DSI_VPCCR register  **************/

+#define DSI_VPCCR_VPSIZE_Pos          (0U)

+#define DSI_VPCCR_VPSIZE_Msk          (0x3FFFUL << DSI_VPCCR_VPSIZE_Pos)       /*!< 0x00003FFF */

+#define DSI_VPCCR_VPSIZE              DSI_VPCCR_VPSIZE_Msk                     /*!< Video Packet Size */

+#define DSI_VPCCR_VPSIZE0_Pos         (0U)

+#define DSI_VPCCR_VPSIZE0_Msk         (0x1UL << DSI_VPCCR_VPSIZE0_Pos)         /*!< 0x00000001 */

+#define DSI_VPCCR_VPSIZE0             DSI_VPCCR_VPSIZE0_Msk

+#define DSI_VPCCR_VPSIZE1_Pos         (1U)

+#define DSI_VPCCR_VPSIZE1_Msk         (0x1UL << DSI_VPCCR_VPSIZE1_Pos)         /*!< 0x00000002 */

+#define DSI_VPCCR_VPSIZE1             DSI_VPCCR_VPSIZE1_Msk

+#define DSI_VPCCR_VPSIZE2_Pos         (2U)

+#define DSI_VPCCR_VPSIZE2_Msk         (0x1UL << DSI_VPCCR_VPSIZE2_Pos)         /*!< 0x00000004 */

+#define DSI_VPCCR_VPSIZE2             DSI_VPCCR_VPSIZE2_Msk

+#define DSI_VPCCR_VPSIZE3_Pos         (3U)

+#define DSI_VPCCR_VPSIZE3_Msk         (0x1UL << DSI_VPCCR_VPSIZE3_Pos)         /*!< 0x00000008 */

+#define DSI_VPCCR_VPSIZE3             DSI_VPCCR_VPSIZE3_Msk

+#define DSI_VPCCR_VPSIZE4_Pos         (4U)

+#define DSI_VPCCR_VPSIZE4_Msk         (0x1UL << DSI_VPCCR_VPSIZE4_Pos)         /*!< 0x00000010 */

+#define DSI_VPCCR_VPSIZE4             DSI_VPCCR_VPSIZE4_Msk

+#define DSI_VPCCR_VPSIZE5_Pos         (5U)

+#define DSI_VPCCR_VPSIZE5_Msk         (0x1UL << DSI_VPCCR_VPSIZE5_Pos)         /*!< 0x00000020 */

+#define DSI_VPCCR_VPSIZE5             DSI_VPCCR_VPSIZE5_Msk

+#define DSI_VPCCR_VPSIZE6_Pos         (6U)

+#define DSI_VPCCR_VPSIZE6_Msk         (0x1UL << DSI_VPCCR_VPSIZE6_Pos)         /*!< 0x00000040 */

+#define DSI_VPCCR_VPSIZE6             DSI_VPCCR_VPSIZE6_Msk

+#define DSI_VPCCR_VPSIZE7_Pos         (7U)

+#define DSI_VPCCR_VPSIZE7_Msk         (0x1UL << DSI_VPCCR_VPSIZE7_Pos)         /*!< 0x00000080 */

+#define DSI_VPCCR_VPSIZE7             DSI_VPCCR_VPSIZE7_Msk

+#define DSI_VPCCR_VPSIZE8_Pos         (8U)

+#define DSI_VPCCR_VPSIZE8_Msk         (0x1UL << DSI_VPCCR_VPSIZE8_Pos)         /*!< 0x00000100 */

+#define DSI_VPCCR_VPSIZE8             DSI_VPCCR_VPSIZE8_Msk

+#define DSI_VPCCR_VPSIZE9_Pos         (9U)

+#define DSI_VPCCR_VPSIZE9_Msk         (0x1UL << DSI_VPCCR_VPSIZE9_Pos)         /*!< 0x00000200 */

+#define DSI_VPCCR_VPSIZE9             DSI_VPCCR_VPSIZE9_Msk

+#define DSI_VPCCR_VPSIZE10_Pos        (10U)

+#define DSI_VPCCR_VPSIZE10_Msk        (0x1UL << DSI_VPCCR_VPSIZE10_Pos)        /*!< 0x00000400 */

+#define DSI_VPCCR_VPSIZE10            DSI_VPCCR_VPSIZE10_Msk

+#define DSI_VPCCR_VPSIZE11_Pos        (11U)

+#define DSI_VPCCR_VPSIZE11_Msk        (0x1UL << DSI_VPCCR_VPSIZE11_Pos)        /*!< 0x00000800 */

+#define DSI_VPCCR_VPSIZE11            DSI_VPCCR_VPSIZE11_Msk

+#define DSI_VPCCR_VPSIZE12_Pos        (12U)

+#define DSI_VPCCR_VPSIZE12_Msk        (0x1UL << DSI_VPCCR_VPSIZE12_Pos)        /*!< 0x00001000 */

+#define DSI_VPCCR_VPSIZE12            DSI_VPCCR_VPSIZE12_Msk

+#define DSI_VPCCR_VPSIZE13_Pos        (13U)

+#define DSI_VPCCR_VPSIZE13_Msk        (0x1UL << DSI_VPCCR_VPSIZE13_Pos)        /*!< 0x00002000 */

+#define DSI_VPCCR_VPSIZE13            DSI_VPCCR_VPSIZE13_Msk

+

+/*******************  Bit definition for DSI_VCCCR register  **************/

+#define DSI_VCCCR_NUMC_Pos            (0U)

+#define DSI_VCCCR_NUMC_Msk            (0x1FFFUL << DSI_VCCCR_NUMC_Pos)         /*!< 0x00001FFF */

+#define DSI_VCCCR_NUMC                DSI_VCCCR_NUMC_Msk                       /*!< Number of Chunks */

+#define DSI_VCCCR_NUMC0_Pos           (0U)

+#define DSI_VCCCR_NUMC0_Msk           (0x1UL << DSI_VCCCR_NUMC0_Pos)           /*!< 0x00000001 */

+#define DSI_VCCCR_NUMC0               DSI_VCCCR_NUMC0_Msk

+#define DSI_VCCCR_NUMC1_Pos           (1U)

+#define DSI_VCCCR_NUMC1_Msk           (0x1UL << DSI_VCCCR_NUMC1_Pos)           /*!< 0x00000002 */

+#define DSI_VCCCR_NUMC1               DSI_VCCCR_NUMC1_Msk

+#define DSI_VCCCR_NUMC2_Pos           (2U)

+#define DSI_VCCCR_NUMC2_Msk           (0x1UL << DSI_VCCCR_NUMC2_Pos)           /*!< 0x00000004 */

+#define DSI_VCCCR_NUMC2               DSI_VCCCR_NUMC2_Msk

+#define DSI_VCCCR_NUMC3_Pos           (3U)

+#define DSI_VCCCR_NUMC3_Msk           (0x1UL << DSI_VCCCR_NUMC3_Pos)           /*!< 0x00000008 */

+#define DSI_VCCCR_NUMC3               DSI_VCCCR_NUMC3_Msk

+#define DSI_VCCCR_NUMC4_Pos           (4U)

+#define DSI_VCCCR_NUMC4_Msk           (0x1UL << DSI_VCCCR_NUMC4_Pos)           /*!< 0x00000010 */

+#define DSI_VCCCR_NUMC4               DSI_VCCCR_NUMC4_Msk

+#define DSI_VCCCR_NUMC5_Pos           (5U)

+#define DSI_VCCCR_NUMC5_Msk           (0x1UL << DSI_VCCCR_NUMC5_Pos)           /*!< 0x00000020 */

+#define DSI_VCCCR_NUMC5               DSI_VCCCR_NUMC5_Msk

+#define DSI_VCCCR_NUMC6_Pos           (6U)

+#define DSI_VCCCR_NUMC6_Msk           (0x1UL << DSI_VCCCR_NUMC6_Pos)           /*!< 0x00000040 */

+#define DSI_VCCCR_NUMC6               DSI_VCCCR_NUMC6_Msk

+#define DSI_VCCCR_NUMC7_Pos           (7U)

+#define DSI_VCCCR_NUMC7_Msk           (0x1UL << DSI_VCCCR_NUMC7_Pos)           /*!< 0x00000080 */

+#define DSI_VCCCR_NUMC7               DSI_VCCCR_NUMC7_Msk

+#define DSI_VCCCR_NUMC8_Pos           (8U)

+#define DSI_VCCCR_NUMC8_Msk           (0x1UL << DSI_VCCCR_NUMC8_Pos)           /*!< 0x00000100 */

+#define DSI_VCCCR_NUMC8               DSI_VCCCR_NUMC8_Msk

+#define DSI_VCCCR_NUMC9_Pos           (9U)

+#define DSI_VCCCR_NUMC9_Msk           (0x1UL << DSI_VCCCR_NUMC9_Pos)           /*!< 0x00000200 */

+#define DSI_VCCCR_NUMC9               DSI_VCCCR_NUMC9_Msk

+#define DSI_VCCCR_NUMC10_Pos          (10U)

+#define DSI_VCCCR_NUMC10_Msk          (0x1UL << DSI_VCCCR_NUMC10_Pos)          /*!< 0x00000400 */

+#define DSI_VCCCR_NUMC10              DSI_VCCCR_NUMC10_Msk

+#define DSI_VCCCR_NUMC11_Pos          (11U)

+#define DSI_VCCCR_NUMC11_Msk          (0x1UL << DSI_VCCCR_NUMC11_Pos)          /*!< 0x00000800 */

+#define DSI_VCCCR_NUMC11              DSI_VCCCR_NUMC11_Msk

+#define DSI_VCCCR_NUMC12_Pos          (12U)

+#define DSI_VCCCR_NUMC12_Msk          (0x1UL << DSI_VCCCR_NUMC12_Pos)          /*!< 0x00001000 */

+#define DSI_VCCCR_NUMC12              DSI_VCCCR_NUMC12_Msk

+

+/*******************  Bit definition for DSI_VNPCCR register  *************/

+#define DSI_VNPCCR_NPSIZE_Pos         (0U)

+#define DSI_VNPCCR_NPSIZE_Msk         (0x1FFFUL << DSI_VNPCCR_NPSIZE_Pos)      /*!< 0x00001FFF */

+#define DSI_VNPCCR_NPSIZE             DSI_VNPCCR_NPSIZE_Msk                    /*!< Number of Chunks */

+#define DSI_VNPCCR_NPSIZE0_Pos        (0U)

+#define DSI_VNPCCR_NPSIZE0_Msk        (0x1UL << DSI_VNPCCR_NPSIZE0_Pos)        /*!< 0x00000001 */

+#define DSI_VNPCCR_NPSIZE0            DSI_VNPCCR_NPSIZE0_Msk

+#define DSI_VNPCCR_NPSIZE1_Pos        (1U)

+#define DSI_VNPCCR_NPSIZE1_Msk        (0x1UL << DSI_VNPCCR_NPSIZE1_Pos)        /*!< 0x00000002 */

+#define DSI_VNPCCR_NPSIZE1            DSI_VNPCCR_NPSIZE1_Msk

+#define DSI_VNPCCR_NPSIZE2_Pos        (2U)

+#define DSI_VNPCCR_NPSIZE2_Msk        (0x1UL << DSI_VNPCCR_NPSIZE2_Pos)        /*!< 0x00000004 */

+#define DSI_VNPCCR_NPSIZE2            DSI_VNPCCR_NPSIZE2_Msk

+#define DSI_VNPCCR_NPSIZE3_Pos        (3U)

+#define DSI_VNPCCR_NPSIZE3_Msk        (0x1UL << DSI_VNPCCR_NPSIZE3_Pos)        /*!< 0x00000008 */

+#define DSI_VNPCCR_NPSIZE3            DSI_VNPCCR_NPSIZE3_Msk

+#define DSI_VNPCCR_NPSIZE4_Pos        (4U)

+#define DSI_VNPCCR_NPSIZE4_Msk        (0x1UL << DSI_VNPCCR_NPSIZE4_Pos)        /*!< 0x00000010 */

+#define DSI_VNPCCR_NPSIZE4            DSI_VNPCCR_NPSIZE4_Msk

+#define DSI_VNPCCR_NPSIZE5_Pos        (5U)

+#define DSI_VNPCCR_NPSIZE5_Msk        (0x1UL << DSI_VNPCCR_NPSIZE5_Pos)        /*!< 0x00000020 */

+#define DSI_VNPCCR_NPSIZE5            DSI_VNPCCR_NPSIZE5_Msk

+#define DSI_VNPCCR_NPSIZE6_Pos        (6U)

+#define DSI_VNPCCR_NPSIZE6_Msk        (0x1UL << DSI_VNPCCR_NPSIZE6_Pos)        /*!< 0x00000040 */

+#define DSI_VNPCCR_NPSIZE6            DSI_VNPCCR_NPSIZE6_Msk

+#define DSI_VNPCCR_NPSIZE7_Pos        (7U)

+#define DSI_VNPCCR_NPSIZE7_Msk        (0x1UL << DSI_VNPCCR_NPSIZE7_Pos)        /*!< 0x00000080 */

+#define DSI_VNPCCR_NPSIZE7            DSI_VNPCCR_NPSIZE7_Msk

+#define DSI_VNPCCR_NPSIZE8_Pos        (8U)

+#define DSI_VNPCCR_NPSIZE8_Msk        (0x1UL << DSI_VNPCCR_NPSIZE8_Pos)        /*!< 0x00000100 */

+#define DSI_VNPCCR_NPSIZE8            DSI_VNPCCR_NPSIZE8_Msk

+#define DSI_VNPCCR_NPSIZE9_Pos        (9U)

+#define DSI_VNPCCR_NPSIZE9_Msk        (0x1UL << DSI_VNPCCR_NPSIZE9_Pos)        /*!< 0x00000200 */

+#define DSI_VNPCCR_NPSIZE9            DSI_VNPCCR_NPSIZE9_Msk

+#define DSI_VNPCCR_NPSIZE10_Pos       (10U)

+#define DSI_VNPCCR_NPSIZE10_Msk       (0x1UL << DSI_VNPCCR_NPSIZE10_Pos)       /*!< 0x00000400 */

+#define DSI_VNPCCR_NPSIZE10           DSI_VNPCCR_NPSIZE10_Msk

+#define DSI_VNPCCR_NPSIZE11_Pos       (11U)

+#define DSI_VNPCCR_NPSIZE11_Msk       (0x1UL << DSI_VNPCCR_NPSIZE11_Pos)       /*!< 0x00000800 */

+#define DSI_VNPCCR_NPSIZE11           DSI_VNPCCR_NPSIZE11_Msk

+#define DSI_VNPCCR_NPSIZE12_Pos       (12U)

+#define DSI_VNPCCR_NPSIZE12_Msk       (0x1UL << DSI_VNPCCR_NPSIZE12_Pos)       /*!< 0x00001000 */

+#define DSI_VNPCCR_NPSIZE12           DSI_VNPCCR_NPSIZE12_Msk

+

+/*******************  Bit definition for DSI_VHSACCR register  ************/

+#define DSI_VHSACCR_HSA_Pos           (0U)

+#define DSI_VHSACCR_HSA_Msk           (0xFFFUL << DSI_VHSACCR_HSA_Pos)         /*!< 0x00000FFF */

+#define DSI_VHSACCR_HSA               DSI_VHSACCR_HSA_Msk                      /*!< Horizontal Synchronism Active duration */

+#define DSI_VHSACCR_HSA0_Pos          (0U)

+#define DSI_VHSACCR_HSA0_Msk          (0x1UL << DSI_VHSACCR_HSA0_Pos)          /*!< 0x00000001 */

+#define DSI_VHSACCR_HSA0              DSI_VHSACCR_HSA0_Msk

+#define DSI_VHSACCR_HSA1_Pos          (1U)

+#define DSI_VHSACCR_HSA1_Msk          (0x1UL << DSI_VHSACCR_HSA1_Pos)          /*!< 0x00000002 */

+#define DSI_VHSACCR_HSA1              DSI_VHSACCR_HSA1_Msk

+#define DSI_VHSACCR_HSA2_Pos          (2U)

+#define DSI_VHSACCR_HSA2_Msk          (0x1UL << DSI_VHSACCR_HSA2_Pos)          /*!< 0x00000004 */

+#define DSI_VHSACCR_HSA2              DSI_VHSACCR_HSA2_Msk

+#define DSI_VHSACCR_HSA3_Pos          (3U)

+#define DSI_VHSACCR_HSA3_Msk          (0x1UL << DSI_VHSACCR_HSA3_Pos)          /*!< 0x00000008 */

+#define DSI_VHSACCR_HSA3              DSI_VHSACCR_HSA3_Msk

+#define DSI_VHSACCR_HSA4_Pos          (4U)

+#define DSI_VHSACCR_HSA4_Msk          (0x1UL << DSI_VHSACCR_HSA4_Pos)          /*!< 0x00000010 */

+#define DSI_VHSACCR_HSA4              DSI_VHSACCR_HSA4_Msk

+#define DSI_VHSACCR_HSA5_Pos          (5U)

+#define DSI_VHSACCR_HSA5_Msk          (0x1UL << DSI_VHSACCR_HSA5_Pos)          /*!< 0x00000020 */

+#define DSI_VHSACCR_HSA5              DSI_VHSACCR_HSA5_Msk

+#define DSI_VHSACCR_HSA6_Pos          (6U)

+#define DSI_VHSACCR_HSA6_Msk          (0x1UL << DSI_VHSACCR_HSA6_Pos)          /*!< 0x00000040 */

+#define DSI_VHSACCR_HSA6              DSI_VHSACCR_HSA6_Msk

+#define DSI_VHSACCR_HSA7_Pos          (7U)

+#define DSI_VHSACCR_HSA7_Msk          (0x1UL << DSI_VHSACCR_HSA7_Pos)          /*!< 0x00000080 */

+#define DSI_VHSACCR_HSA7              DSI_VHSACCR_HSA7_Msk

+#define DSI_VHSACCR_HSA8_Pos          (8U)

+#define DSI_VHSACCR_HSA8_Msk          (0x1UL << DSI_VHSACCR_HSA8_Pos)          /*!< 0x00000100 */

+#define DSI_VHSACCR_HSA8              DSI_VHSACCR_HSA8_Msk

+#define DSI_VHSACCR_HSA9_Pos          (9U)

+#define DSI_VHSACCR_HSA9_Msk          (0x1UL << DSI_VHSACCR_HSA9_Pos)          /*!< 0x00000200 */

+#define DSI_VHSACCR_HSA9              DSI_VHSACCR_HSA9_Msk

+#define DSI_VHSACCR_HSA10_Pos         (10U)

+#define DSI_VHSACCR_HSA10_Msk         (0x1UL << DSI_VHSACCR_HSA10_Pos)         /*!< 0x00000400 */

+#define DSI_VHSACCR_HSA10             DSI_VHSACCR_HSA10_Msk

+#define DSI_VHSACCR_HSA11_Pos         (11U)

+#define DSI_VHSACCR_HSA11_Msk         (0x1UL << DSI_VHSACCR_HSA11_Pos)         /*!< 0x00000800 */

+#define DSI_VHSACCR_HSA11             DSI_VHSACCR_HSA11_Msk

+

+/*******************  Bit definition for DSI_VHBPCCR register  ************/

+#define DSI_VHBPCCR_HBP_Pos           (0U)

+#define DSI_VHBPCCR_HBP_Msk           (0xFFFUL << DSI_VHBPCCR_HBP_Pos)         /*!< 0x00000FFF */

+#define DSI_VHBPCCR_HBP               DSI_VHBPCCR_HBP_Msk                      /*!< Horizontal Back-Porch duration */

+#define DSI_VHBPCCR_HBP0_Pos          (0U)

+#define DSI_VHBPCCR_HBP0_Msk          (0x1UL << DSI_VHBPCCR_HBP0_Pos)          /*!< 0x00000001 */

+#define DSI_VHBPCCR_HBP0              DSI_VHBPCCR_HBP0_Msk

+#define DSI_VHBPCCR_HBP1_Pos          (1U)

+#define DSI_VHBPCCR_HBP1_Msk          (0x1UL << DSI_VHBPCCR_HBP1_Pos)          /*!< 0x00000002 */

+#define DSI_VHBPCCR_HBP1              DSI_VHBPCCR_HBP1_Msk

+#define DSI_VHBPCCR_HBP2_Pos          (2U)

+#define DSI_VHBPCCR_HBP2_Msk          (0x1UL << DSI_VHBPCCR_HBP2_Pos)          /*!< 0x00000004 */

+#define DSI_VHBPCCR_HBP2              DSI_VHBPCCR_HBP2_Msk

+#define DSI_VHBPCCR_HBP3_Pos          (3U)

+#define DSI_VHBPCCR_HBP3_Msk          (0x1UL << DSI_VHBPCCR_HBP3_Pos)          /*!< 0x00000008 */

+#define DSI_VHBPCCR_HBP3              DSI_VHBPCCR_HBP3_Msk

+#define DSI_VHBPCCR_HBP4_Pos          (4U)

+#define DSI_VHBPCCR_HBP4_Msk          (0x1UL << DSI_VHBPCCR_HBP4_Pos)          /*!< 0x00000010 */

+#define DSI_VHBPCCR_HBP4              DSI_VHBPCCR_HBP4_Msk

+#define DSI_VHBPCCR_HBP5_Pos          (5U)

+#define DSI_VHBPCCR_HBP5_Msk          (0x1UL << DSI_VHBPCCR_HBP5_Pos)          /*!< 0x00000020 */

+#define DSI_VHBPCCR_HBP5              DSI_VHBPCCR_HBP5_Msk

+#define DSI_VHBPCCR_HBP6_Pos          (6U)

+#define DSI_VHBPCCR_HBP6_Msk          (0x1UL << DSI_VHBPCCR_HBP6_Pos)          /*!< 0x00000040 */

+#define DSI_VHBPCCR_HBP6              DSI_VHBPCCR_HBP6_Msk

+#define DSI_VHBPCCR_HBP7_Pos          (7U)

+#define DSI_VHBPCCR_HBP7_Msk          (0x1UL << DSI_VHBPCCR_HBP7_Pos)          /*!< 0x00000080 */

+#define DSI_VHBPCCR_HBP7              DSI_VHBPCCR_HBP7_Msk

+#define DSI_VHBPCCR_HBP8_Pos          (8U)

+#define DSI_VHBPCCR_HBP8_Msk          (0x1UL << DSI_VHBPCCR_HBP8_Pos)          /*!< 0x00000100 */

+#define DSI_VHBPCCR_HBP8              DSI_VHBPCCR_HBP8_Msk

+#define DSI_VHBPCCR_HBP9_Pos          (9U)

+#define DSI_VHBPCCR_HBP9_Msk          (0x1UL << DSI_VHBPCCR_HBP9_Pos)          /*!< 0x00000200 */

+#define DSI_VHBPCCR_HBP9              DSI_VHBPCCR_HBP9_Msk

+#define DSI_VHBPCCR_HBP10_Pos         (10U)

+#define DSI_VHBPCCR_HBP10_Msk         (0x1UL << DSI_VHBPCCR_HBP10_Pos)         /*!< 0x00000400 */

+#define DSI_VHBPCCR_HBP10             DSI_VHBPCCR_HBP10_Msk

+#define DSI_VHBPCCR_HBP11_Pos         (11U)

+#define DSI_VHBPCCR_HBP11_Msk         (0x1UL << DSI_VHBPCCR_HBP11_Pos)         /*!< 0x00000800 */

+#define DSI_VHBPCCR_HBP11             DSI_VHBPCCR_HBP11_Msk

+

+/*******************  Bit definition for DSI_VLCCR register  **************/

+#define DSI_VLCCR_HLINE_Pos           (0U)

+#define DSI_VLCCR_HLINE_Msk           (0x7FFFUL << DSI_VLCCR_HLINE_Pos)        /*!< 0x00007FFF */

+#define DSI_VLCCR_HLINE               DSI_VLCCR_HLINE_Msk                      /*!< Horizontal Line duration */

+#define DSI_VLCCR_HLINE0_Pos          (0U)

+#define DSI_VLCCR_HLINE0_Msk          (0x1UL << DSI_VLCCR_HLINE0_Pos)          /*!< 0x00000001 */

+#define DSI_VLCCR_HLINE0              DSI_VLCCR_HLINE0_Msk

+#define DSI_VLCCR_HLINE1_Pos          (1U)

+#define DSI_VLCCR_HLINE1_Msk          (0x1UL << DSI_VLCCR_HLINE1_Pos)          /*!< 0x00000002 */

+#define DSI_VLCCR_HLINE1              DSI_VLCCR_HLINE1_Msk

+#define DSI_VLCCR_HLINE2_Pos          (2U)

+#define DSI_VLCCR_HLINE2_Msk          (0x1UL << DSI_VLCCR_HLINE2_Pos)          /*!< 0x00000004 */

+#define DSI_VLCCR_HLINE2              DSI_VLCCR_HLINE2_Msk

+#define DSI_VLCCR_HLINE3_Pos          (3U)

+#define DSI_VLCCR_HLINE3_Msk          (0x1UL << DSI_VLCCR_HLINE3_Pos)          /*!< 0x00000008 */

+#define DSI_VLCCR_HLINE3              DSI_VLCCR_HLINE3_Msk

+#define DSI_VLCCR_HLINE4_Pos          (4U)

+#define DSI_VLCCR_HLINE4_Msk          (0x1UL << DSI_VLCCR_HLINE4_Pos)          /*!< 0x00000010 */

+#define DSI_VLCCR_HLINE4              DSI_VLCCR_HLINE4_Msk

+#define DSI_VLCCR_HLINE5_Pos          (5U)

+#define DSI_VLCCR_HLINE5_Msk          (0x1UL << DSI_VLCCR_HLINE5_Pos)          /*!< 0x00000020 */

+#define DSI_VLCCR_HLINE5              DSI_VLCCR_HLINE5_Msk

+#define DSI_VLCCR_HLINE6_Pos          (6U)

+#define DSI_VLCCR_HLINE6_Msk          (0x1UL << DSI_VLCCR_HLINE6_Pos)          /*!< 0x00000040 */

+#define DSI_VLCCR_HLINE6              DSI_VLCCR_HLINE6_Msk

+#define DSI_VLCCR_HLINE7_Pos          (7U)

+#define DSI_VLCCR_HLINE7_Msk          (0x1UL << DSI_VLCCR_HLINE7_Pos)          /*!< 0x00000080 */

+#define DSI_VLCCR_HLINE7              DSI_VLCCR_HLINE7_Msk

+#define DSI_VLCCR_HLINE8_Pos          (8U)

+#define DSI_VLCCR_HLINE8_Msk          (0x1UL << DSI_VLCCR_HLINE8_Pos)          /*!< 0x00000100 */

+#define DSI_VLCCR_HLINE8              DSI_VLCCR_HLINE8_Msk

+#define DSI_VLCCR_HLINE9_Pos          (9U)

+#define DSI_VLCCR_HLINE9_Msk          (0x1UL << DSI_VLCCR_HLINE9_Pos)          /*!< 0x00000200 */

+#define DSI_VLCCR_HLINE9              DSI_VLCCR_HLINE9_Msk

+#define DSI_VLCCR_HLINE10_Pos         (10U)

+#define DSI_VLCCR_HLINE10_Msk         (0x1UL << DSI_VLCCR_HLINE10_Pos)         /*!< 0x00000400 */

+#define DSI_VLCCR_HLINE10             DSI_VLCCR_HLINE10_Msk

+#define DSI_VLCCR_HLINE11_Pos         (11U)

+#define DSI_VLCCR_HLINE11_Msk         (0x1UL << DSI_VLCCR_HLINE11_Pos)         /*!< 0x00000800 */

+#define DSI_VLCCR_HLINE11             DSI_VLCCR_HLINE11_Msk

+#define DSI_VLCCR_HLINE12_Pos         (12U)

+#define DSI_VLCCR_HLINE12_Msk         (0x1UL << DSI_VLCCR_HLINE12_Pos)         /*!< 0x00001000 */

+#define DSI_VLCCR_HLINE12             DSI_VLCCR_HLINE12_Msk

+#define DSI_VLCCR_HLINE13_Pos         (13U)

+#define DSI_VLCCR_HLINE13_Msk         (0x1UL << DSI_VLCCR_HLINE13_Pos)         /*!< 0x00002000 */

+#define DSI_VLCCR_HLINE13             DSI_VLCCR_HLINE13_Msk

+#define DSI_VLCCR_HLINE14_Pos         (14U)

+#define DSI_VLCCR_HLINE14_Msk         (0x1UL << DSI_VLCCR_HLINE14_Pos)         /*!< 0x00004000 */

+#define DSI_VLCCR_HLINE14             DSI_VLCCR_HLINE14_Msk

+

+/*******************  Bit definition for DSI_VVSACCR register  ***************/

+#define DSI_VVSACCR_VSA_Pos           (0U)

+#define DSI_VVSACCR_VSA_Msk           (0x3FFUL << DSI_VVSACCR_VSA_Pos)         /*!< 0x000003FF */

+#define DSI_VVSACCR_VSA               DSI_VVSACCR_VSA_Msk                      /*!< Vertical Synchronism Active duration */

+#define DSI_VVSACCR_VSA0_Pos          (0U)

+#define DSI_VVSACCR_VSA0_Msk          (0x1UL << DSI_VVSACCR_VSA0_Pos)          /*!< 0x00000001 */

+#define DSI_VVSACCR_VSA0              DSI_VVSACCR_VSA0_Msk

+#define DSI_VVSACCR_VSA1_Pos          (1U)

+#define DSI_VVSACCR_VSA1_Msk          (0x1UL << DSI_VVSACCR_VSA1_Pos)          /*!< 0x00000002 */

+#define DSI_VVSACCR_VSA1              DSI_VVSACCR_VSA1_Msk

+#define DSI_VVSACCR_VSA2_Pos          (2U)

+#define DSI_VVSACCR_VSA2_Msk          (0x1UL << DSI_VVSACCR_VSA2_Pos)          /*!< 0x00000004 */

+#define DSI_VVSACCR_VSA2              DSI_VVSACCR_VSA2_Msk

+#define DSI_VVSACCR_VSA3_Pos          (3U)

+#define DSI_VVSACCR_VSA3_Msk          (0x1UL << DSI_VVSACCR_VSA3_Pos)          /*!< 0x00000008 */

+#define DSI_VVSACCR_VSA3              DSI_VVSACCR_VSA3_Msk

+#define DSI_VVSACCR_VSA4_Pos          (4U)

+#define DSI_VVSACCR_VSA4_Msk          (0x1UL << DSI_VVSACCR_VSA4_Pos)          /*!< 0x00000010 */

+#define DSI_VVSACCR_VSA4              DSI_VVSACCR_VSA4_Msk

+#define DSI_VVSACCR_VSA5_Pos          (5U)

+#define DSI_VVSACCR_VSA5_Msk          (0x1UL << DSI_VVSACCR_VSA5_Pos)          /*!< 0x00000020 */

+#define DSI_VVSACCR_VSA5              DSI_VVSACCR_VSA5_Msk

+#define DSI_VVSACCR_VSA6_Pos          (6U)

+#define DSI_VVSACCR_VSA6_Msk          (0x1UL << DSI_VVSACCR_VSA6_Pos)          /*!< 0x00000040 */

+#define DSI_VVSACCR_VSA6              DSI_VVSACCR_VSA6_Msk

+#define DSI_VVSACCR_VSA7_Pos          (7U)

+#define DSI_VVSACCR_VSA7_Msk          (0x1UL << DSI_VVSACCR_VSA7_Pos)          /*!< 0x00000080 */

+#define DSI_VVSACCR_VSA7              DSI_VVSACCR_VSA7_Msk

+#define DSI_VVSACCR_VSA8_Pos          (8U)

+#define DSI_VVSACCR_VSA8_Msk          (0x1UL << DSI_VVSACCR_VSA8_Pos)          /*!< 0x00000100 */

+#define DSI_VVSACCR_VSA8              DSI_VVSACCR_VSA8_Msk

+#define DSI_VVSACCR_VSA9_Pos          (9U)

+#define DSI_VVSACCR_VSA9_Msk          (0x1UL << DSI_VVSACCR_VSA9_Pos)          /*!< 0x00000200 */

+#define DSI_VVSACCR_VSA9              DSI_VVSACCR_VSA9_Msk

+

+/*******************  Bit definition for DSI_VVBPCCR register  ************/

+#define DSI_VVBPCCR_VBP_Pos           (0U)

+#define DSI_VVBPCCR_VBP_Msk           (0x3FFUL << DSI_VVBPCCR_VBP_Pos)         /*!< 0x000003FF */

+#define DSI_VVBPCCR_VBP               DSI_VVBPCCR_VBP_Msk                      /*!< Vertical Back-Porch duration */

+#define DSI_VVBPCCR_VBP0_Pos          (0U)

+#define DSI_VVBPCCR_VBP0_Msk          (0x1UL << DSI_VVBPCCR_VBP0_Pos)          /*!< 0x00000001 */

+#define DSI_VVBPCCR_VBP0              DSI_VVBPCCR_VBP0_Msk

+#define DSI_VVBPCCR_VBP1_Pos          (1U)

+#define DSI_VVBPCCR_VBP1_Msk          (0x1UL << DSI_VVBPCCR_VBP1_Pos)          /*!< 0x00000002 */

+#define DSI_VVBPCCR_VBP1              DSI_VVBPCCR_VBP1_Msk

+#define DSI_VVBPCCR_VBP2_Pos          (2U)

+#define DSI_VVBPCCR_VBP2_Msk          (0x1UL << DSI_VVBPCCR_VBP2_Pos)          /*!< 0x00000004 */

+#define DSI_VVBPCCR_VBP2              DSI_VVBPCCR_VBP2_Msk

+#define DSI_VVBPCCR_VBP3_Pos          (3U)

+#define DSI_VVBPCCR_VBP3_Msk          (0x1UL << DSI_VVBPCCR_VBP3_Pos)          /*!< 0x00000008 */

+#define DSI_VVBPCCR_VBP3              DSI_VVBPCCR_VBP3_Msk

+#define DSI_VVBPCCR_VBP4_Pos          (4U)

+#define DSI_VVBPCCR_VBP4_Msk          (0x1UL << DSI_VVBPCCR_VBP4_Pos)          /*!< 0x00000010 */

+#define DSI_VVBPCCR_VBP4              DSI_VVBPCCR_VBP4_Msk

+#define DSI_VVBPCCR_VBP5_Pos          (5U)

+#define DSI_VVBPCCR_VBP5_Msk          (0x1UL << DSI_VVBPCCR_VBP5_Pos)          /*!< 0x00000020 */

+#define DSI_VVBPCCR_VBP5              DSI_VVBPCCR_VBP5_Msk

+#define DSI_VVBPCCR_VBP6_Pos          (6U)

+#define DSI_VVBPCCR_VBP6_Msk          (0x1UL << DSI_VVBPCCR_VBP6_Pos)          /*!< 0x00000040 */

+#define DSI_VVBPCCR_VBP6              DSI_VVBPCCR_VBP6_Msk

+#define DSI_VVBPCCR_VBP7_Pos          (7U)

+#define DSI_VVBPCCR_VBP7_Msk          (0x1UL << DSI_VVBPCCR_VBP7_Pos)          /*!< 0x00000080 */

+#define DSI_VVBPCCR_VBP7              DSI_VVBPCCR_VBP7_Msk

+#define DSI_VVBPCCR_VBP8_Pos          (8U)

+#define DSI_VVBPCCR_VBP8_Msk          (0x1UL << DSI_VVBPCCR_VBP8_Pos)          /*!< 0x00000100 */

+#define DSI_VVBPCCR_VBP8              DSI_VVBPCCR_VBP8_Msk

+#define DSI_VVBPCCR_VBP9_Pos          (9U)

+#define DSI_VVBPCCR_VBP9_Msk          (0x1UL << DSI_VVBPCCR_VBP9_Pos)          /*!< 0x00000200 */

+#define DSI_VVBPCCR_VBP9              DSI_VVBPCCR_VBP9_Msk

+

+/*******************  Bit definition for DSI_VVFPCCR register  ************/

+#define DSI_VVFPCCR_VFP_Pos           (0U)

+#define DSI_VVFPCCR_VFP_Msk           (0x3FFUL << DSI_VVFPCCR_VFP_Pos)         /*!< 0x000003FF */

+#define DSI_VVFPCCR_VFP               DSI_VVFPCCR_VFP_Msk                      /*!< Vertical Front-Porch duration */

+#define DSI_VVFPCCR_VFP0_Pos          (0U)

+#define DSI_VVFPCCR_VFP0_Msk          (0x1UL << DSI_VVFPCCR_VFP0_Pos)          /*!< 0x00000001 */

+#define DSI_VVFPCCR_VFP0              DSI_VVFPCCR_VFP0_Msk

+#define DSI_VVFPCCR_VFP1_Pos          (1U)

+#define DSI_VVFPCCR_VFP1_Msk          (0x1UL << DSI_VVFPCCR_VFP1_Pos)          /*!< 0x00000002 */

+#define DSI_VVFPCCR_VFP1              DSI_VVFPCCR_VFP1_Msk

+#define DSI_VVFPCCR_VFP2_Pos          (2U)

+#define DSI_VVFPCCR_VFP2_Msk          (0x1UL << DSI_VVFPCCR_VFP2_Pos)          /*!< 0x00000004 */

+#define DSI_VVFPCCR_VFP2              DSI_VVFPCCR_VFP2_Msk

+#define DSI_VVFPCCR_VFP3_Pos          (3U)

+#define DSI_VVFPCCR_VFP3_Msk          (0x1UL << DSI_VVFPCCR_VFP3_Pos)          /*!< 0x00000008 */

+#define DSI_VVFPCCR_VFP3              DSI_VVFPCCR_VFP3_Msk

+#define DSI_VVFPCCR_VFP4_Pos          (4U)

+#define DSI_VVFPCCR_VFP4_Msk          (0x1UL << DSI_VVFPCCR_VFP4_Pos)          /*!< 0x00000010 */

+#define DSI_VVFPCCR_VFP4              DSI_VVFPCCR_VFP4_Msk

+#define DSI_VVFPCCR_VFP5_Pos          (5U)

+#define DSI_VVFPCCR_VFP5_Msk          (0x1UL << DSI_VVFPCCR_VFP5_Pos)          /*!< 0x00000020 */

+#define DSI_VVFPCCR_VFP5              DSI_VVFPCCR_VFP5_Msk

+#define DSI_VVFPCCR_VFP6_Pos          (6U)

+#define DSI_VVFPCCR_VFP6_Msk          (0x1UL << DSI_VVFPCCR_VFP6_Pos)          /*!< 0x00000040 */

+#define DSI_VVFPCCR_VFP6              DSI_VVFPCCR_VFP6_Msk

+#define DSI_VVFPCCR_VFP7_Pos          (7U)

+#define DSI_VVFPCCR_VFP7_Msk          (0x1UL << DSI_VVFPCCR_VFP7_Pos)          /*!< 0x00000080 */

+#define DSI_VVFPCCR_VFP7              DSI_VVFPCCR_VFP7_Msk

+#define DSI_VVFPCCR_VFP8_Pos          (8U)

+#define DSI_VVFPCCR_VFP8_Msk          (0x1UL << DSI_VVFPCCR_VFP8_Pos)          /*!< 0x00000100 */

+#define DSI_VVFPCCR_VFP8              DSI_VVFPCCR_VFP8_Msk

+#define DSI_VVFPCCR_VFP9_Pos          (9U)

+#define DSI_VVFPCCR_VFP9_Msk          (0x1UL << DSI_VVFPCCR_VFP9_Pos)          /*!< 0x00000200 */

+#define DSI_VVFPCCR_VFP9              DSI_VVFPCCR_VFP9_Msk

+

+/*******************  Bit definition for DSI_VVACCR register  *************/

+#define DSI_VVACCR_VA_Pos             (0U)

+#define DSI_VVACCR_VA_Msk             (0x3FFFUL << DSI_VVACCR_VA_Pos)          /*!< 0x00003FFF */

+#define DSI_VVACCR_VA                 DSI_VVACCR_VA_Msk                        /*!< Vertical Active duration */

+#define DSI_VVACCR_VA0_Pos            (0U)

+#define DSI_VVACCR_VA0_Msk            (0x1UL << DSI_VVACCR_VA0_Pos)            /*!< 0x00000001 */

+#define DSI_VVACCR_VA0                DSI_VVACCR_VA0_Msk

+#define DSI_VVACCR_VA1_Pos            (1U)

+#define DSI_VVACCR_VA1_Msk            (0x1UL << DSI_VVACCR_VA1_Pos)            /*!< 0x00000002 */

+#define DSI_VVACCR_VA1                DSI_VVACCR_VA1_Msk

+#define DSI_VVACCR_VA2_Pos            (2U)

+#define DSI_VVACCR_VA2_Msk            (0x1UL << DSI_VVACCR_VA2_Pos)            /*!< 0x00000004 */

+#define DSI_VVACCR_VA2                DSI_VVACCR_VA2_Msk

+#define DSI_VVACCR_VA3_Pos            (3U)

+#define DSI_VVACCR_VA3_Msk            (0x1UL << DSI_VVACCR_VA3_Pos)            /*!< 0x00000008 */

+#define DSI_VVACCR_VA3                DSI_VVACCR_VA3_Msk

+#define DSI_VVACCR_VA4_Pos            (4U)

+#define DSI_VVACCR_VA4_Msk            (0x1UL << DSI_VVACCR_VA4_Pos)            /*!< 0x00000010 */

+#define DSI_VVACCR_VA4                DSI_VVACCR_VA4_Msk

+#define DSI_VVACCR_VA5_Pos            (5U)

+#define DSI_VVACCR_VA5_Msk            (0x1UL << DSI_VVACCR_VA5_Pos)            /*!< 0x00000020 */

+#define DSI_VVACCR_VA5                DSI_VVACCR_VA5_Msk

+#define DSI_VVACCR_VA6_Pos            (6U)

+#define DSI_VVACCR_VA6_Msk            (0x1UL << DSI_VVACCR_VA6_Pos)            /*!< 0x00000040 */

+#define DSI_VVACCR_VA6                DSI_VVACCR_VA6_Msk

+#define DSI_VVACCR_VA7_Pos            (7U)

+#define DSI_VVACCR_VA7_Msk            (0x1UL << DSI_VVACCR_VA7_Pos)            /*!< 0x00000080 */

+#define DSI_VVACCR_VA7                DSI_VVACCR_VA7_Msk

+#define DSI_VVACCR_VA8_Pos            (8U)

+#define DSI_VVACCR_VA8_Msk            (0x1UL << DSI_VVACCR_VA8_Pos)            /*!< 0x00000100 */

+#define DSI_VVACCR_VA8                DSI_VVACCR_VA8_Msk

+#define DSI_VVACCR_VA9_Pos            (9U)

+#define DSI_VVACCR_VA9_Msk            (0x1UL << DSI_VVACCR_VA9_Pos)            /*!< 0x00000200 */

+#define DSI_VVACCR_VA9                DSI_VVACCR_VA9_Msk

+#define DSI_VVACCR_VA10_Pos           (10U)

+#define DSI_VVACCR_VA10_Msk           (0x1UL << DSI_VVACCR_VA10_Pos)           /*!< 0x00000400 */

+#define DSI_VVACCR_VA10               DSI_VVACCR_VA10_Msk

+#define DSI_VVACCR_VA11_Pos           (11U)

+#define DSI_VVACCR_VA11_Msk           (0x1UL << DSI_VVACCR_VA11_Pos)           /*!< 0x00000800 */

+#define DSI_VVACCR_VA11               DSI_VVACCR_VA11_Msk

+#define DSI_VVACCR_VA12_Pos           (12U)

+#define DSI_VVACCR_VA12_Msk           (0x1UL << DSI_VVACCR_VA12_Pos)           /*!< 0x00001000 */

+#define DSI_VVACCR_VA12               DSI_VVACCR_VA12_Msk

+#define DSI_VVACCR_VA13_Pos           (13U)

+#define DSI_VVACCR_VA13_Msk           (0x1UL << DSI_VVACCR_VA13_Pos)           /*!< 0x00002000 */

+#define DSI_VVACCR_VA13               DSI_VVACCR_VA13_Msk

+

+/*******************  Bit definition for DSI_TDCCR register  **************/

+#define DSI_TDCCR_3DM                 ((uint32_t)0x00000003U)                  /*!< 3D Mode */

+#define DSI_TDCCR_3DM0                ((uint32_t)0x00000001U)

+#define DSI_TDCCR_3DM1                ((uint32_t)0x00000002U)

+

+#define DSI_TDCCR_3DF                 ((uint32_t)0x0000000CU)                  /*!< 3D Format */

+#define DSI_TDCCR_3DF0                ((uint32_t)0x00000004U)

+#define DSI_TDCCR_3DF1                ((uint32_t)0x00000008U)

+

+#define DSI_TDCCR_SVS_Pos             (4U)

+#define DSI_TDCCR_SVS_Msk             (0x1UL << DSI_TDCCR_SVS_Pos)             /*!< 0x00000010 */

+#define DSI_TDCCR_SVS                 DSI_TDCCR_SVS_Msk                        /*!< Second VSYNC */

+#define DSI_TDCCR_RF_Pos              (5U)

+#define DSI_TDCCR_RF_Msk              (0x1UL << DSI_TDCCR_RF_Pos)              /*!< 0x00000020 */

+#define DSI_TDCCR_RF                  DSI_TDCCR_RF_Msk                         /*!< Right First */

+#define DSI_TDCCR_S3DC_Pos            (16U)

+#define DSI_TDCCR_S3DC_Msk            (0x1UL << DSI_TDCCR_S3DC_Pos)            /*!< 0x00010000 */

+#define DSI_TDCCR_S3DC                DSI_TDCCR_S3DC_Msk                       /*!< Send 3D Control */

+

+/*******************  Bit definition for DSI_WCFGR register  ***************/

+#define DSI_WCFGR_DSIM_Pos            (0U)

+#define DSI_WCFGR_DSIM_Msk            (0x1UL << DSI_WCFGR_DSIM_Pos)            /*!< 0x00000001 */

+#define DSI_WCFGR_DSIM                DSI_WCFGR_DSIM_Msk                       /*!< DSI Mode */

+#define DSI_WCFGR_COLMUX_Pos          (1U)

+#define DSI_WCFGR_COLMUX_Msk          (0x7UL << DSI_WCFGR_COLMUX_Pos)          /*!< 0x0000000E */

+#define DSI_WCFGR_COLMUX              DSI_WCFGR_COLMUX_Msk                     /*!< Color Multiplexing */

+#define DSI_WCFGR_COLMUX0_Pos         (1U)

+#define DSI_WCFGR_COLMUX0_Msk         (0x1UL << DSI_WCFGR_COLMUX0_Pos)         /*!< 0x00000002 */

+#define DSI_WCFGR_COLMUX0             DSI_WCFGR_COLMUX0_Msk

+#define DSI_WCFGR_COLMUX1_Pos         (2U)

+#define DSI_WCFGR_COLMUX1_Msk         (0x1UL << DSI_WCFGR_COLMUX1_Pos)         /*!< 0x00000004 */

+#define DSI_WCFGR_COLMUX1             DSI_WCFGR_COLMUX1_Msk

+#define DSI_WCFGR_COLMUX2_Pos         (3U)

+#define DSI_WCFGR_COLMUX2_Msk         (0x1UL << DSI_WCFGR_COLMUX2_Pos)         /*!< 0x00000008 */

+#define DSI_WCFGR_COLMUX2             DSI_WCFGR_COLMUX2_Msk

+

+#define DSI_WCFGR_TESRC_Pos           (4U)

+#define DSI_WCFGR_TESRC_Msk           (0x1UL << DSI_WCFGR_TESRC_Pos)           /*!< 0x00000010 */

+#define DSI_WCFGR_TESRC               DSI_WCFGR_TESRC_Msk                      /*!< Tearing Effect Source */

+#define DSI_WCFGR_TEPOL_Pos           (5U)

+#define DSI_WCFGR_TEPOL_Msk           (0x1UL << DSI_WCFGR_TEPOL_Pos)           /*!< 0x00000020 */

+#define DSI_WCFGR_TEPOL               DSI_WCFGR_TEPOL_Msk                      /*!< Tearing Effect Polarity */

+#define DSI_WCFGR_AR_Pos              (6U)

+#define DSI_WCFGR_AR_Msk              (0x1UL << DSI_WCFGR_AR_Pos)              /*!< 0x00000040 */

+#define DSI_WCFGR_AR                  DSI_WCFGR_AR_Msk                         /*!< Automatic Refresh */

+#define DSI_WCFGR_VSPOL_Pos           (7U)

+#define DSI_WCFGR_VSPOL_Msk           (0x1UL << DSI_WCFGR_VSPOL_Pos)           /*!< 0x00000080 */

+#define DSI_WCFGR_VSPOL               DSI_WCFGR_VSPOL_Msk                      /*!< VSync Polarity */

+

+/*******************  Bit definition for DSI_WCR register  *****************/

+#define DSI_WCR_COLM_Pos              (0U)

+#define DSI_WCR_COLM_Msk              (0x1UL << DSI_WCR_COLM_Pos)              /*!< 0x00000001 */

+#define DSI_WCR_COLM                  DSI_WCR_COLM_Msk                         /*!< Color Mode */

+#define DSI_WCR_SHTDN_Pos             (1U)

+#define DSI_WCR_SHTDN_Msk             (0x1UL << DSI_WCR_SHTDN_Pos)             /*!< 0x00000002 */

+#define DSI_WCR_SHTDN                 DSI_WCR_SHTDN_Msk                        /*!< Shutdown */

+#define DSI_WCR_LTDCEN_Pos            (2U)

+#define DSI_WCR_LTDCEN_Msk            (0x1UL << DSI_WCR_LTDCEN_Pos)            /*!< 0x00000004 */

+#define DSI_WCR_LTDCEN                DSI_WCR_LTDCEN_Msk                       /*!< LTDC Enable */

+#define DSI_WCR_DSIEN_Pos             (3U)

+#define DSI_WCR_DSIEN_Msk             (0x1UL << DSI_WCR_DSIEN_Pos)             /*!< 0x00000008 */

+#define DSI_WCR_DSIEN                 DSI_WCR_DSIEN_Msk                        /*!< DSI Enable */

+

+/*******************  Bit definition for DSI_WIER register  ****************/

+#define DSI_WIER_TEIE_Pos             (0U)

+#define DSI_WIER_TEIE_Msk             (0x1UL << DSI_WIER_TEIE_Pos)             /*!< 0x00000001 */

+#define DSI_WIER_TEIE                 DSI_WIER_TEIE_Msk                        /*!< Tearing Effect Interrupt Enable */

+#define DSI_WIER_ERIE_Pos             (1U)

+#define DSI_WIER_ERIE_Msk             (0x1UL << DSI_WIER_ERIE_Pos)             /*!< 0x00000002 */

+#define DSI_WIER_ERIE                 DSI_WIER_ERIE_Msk                        /*!< End of Refresh Interrupt Enable */

+#define DSI_WIER_PLLLIE_Pos           (9U)

+#define DSI_WIER_PLLLIE_Msk           (0x1UL << DSI_WIER_PLLLIE_Pos)           /*!< 0x00000200 */

+#define DSI_WIER_PLLLIE               DSI_WIER_PLLLIE_Msk                      /*!< PLL Lock Interrupt Enable */

+#define DSI_WIER_PLLUIE_Pos           (10U)

+#define DSI_WIER_PLLUIE_Msk           (0x1UL << DSI_WIER_PLLUIE_Pos)           /*!< 0x00000400 */

+#define DSI_WIER_PLLUIE               DSI_WIER_PLLUIE_Msk                      /*!< PLL Unlock Interrupt Enable */

+#define DSI_WIER_RRIE_Pos             (13U)

+#define DSI_WIER_RRIE_Msk             (0x1UL << DSI_WIER_RRIE_Pos)             /*!< 0x00002000 */

+#define DSI_WIER_RRIE                 DSI_WIER_RRIE_Msk                        /*!< Regulator Ready Interrupt Enable */

+

+/*******************  Bit definition for DSI_WISR register  ****************/

+#define DSI_WISR_TEIF_Pos             (0U)

+#define DSI_WISR_TEIF_Msk             (0x1UL << DSI_WISR_TEIF_Pos)             /*!< 0x00000001 */

+#define DSI_WISR_TEIF                 DSI_WISR_TEIF_Msk                        /*!< Tearing Effect Interrupt Flag */

+#define DSI_WISR_ERIF_Pos             (1U)

+#define DSI_WISR_ERIF_Msk             (0x1UL << DSI_WISR_ERIF_Pos)             /*!< 0x00000002 */

+#define DSI_WISR_ERIF                 DSI_WISR_ERIF_Msk                        /*!< End of Refresh Interrupt Flag */

+#define DSI_WISR_BUSY_Pos             (2U)

+#define DSI_WISR_BUSY_Msk             (0x1UL << DSI_WISR_BUSY_Pos)             /*!< 0x00000004 */

+#define DSI_WISR_BUSY                 DSI_WISR_BUSY_Msk                        /*!< Busy Flag */

+#define DSI_WISR_PLLLS_Pos            (8U)

+#define DSI_WISR_PLLLS_Msk            (0x1UL << DSI_WISR_PLLLS_Pos)            /*!< 0x00000100 */

+#define DSI_WISR_PLLLS                DSI_WISR_PLLLS_Msk                       /*!< PLL Lock Status */

+#define DSI_WISR_PLLLIF_Pos           (9U)

+#define DSI_WISR_PLLLIF_Msk           (0x1UL << DSI_WISR_PLLLIF_Pos)           /*!< 0x00000200 */

+#define DSI_WISR_PLLLIF               DSI_WISR_PLLLIF_Msk                      /*!< PLL Lock Interrupt Flag */

+#define DSI_WISR_PLLUIF_Pos           (10U)

+#define DSI_WISR_PLLUIF_Msk           (0x1UL << DSI_WISR_PLLUIF_Pos)           /*!< 0x00000400 */

+#define DSI_WISR_PLLUIF               DSI_WISR_PLLUIF_Msk                      /*!< PLL Unlock Interrupt Flag */

+#define DSI_WISR_RRS_Pos              (12U)

+#define DSI_WISR_RRS_Msk              (0x1UL << DSI_WISR_RRS_Pos)              /*!< 0x00001000 */

+#define DSI_WISR_RRS                  DSI_WISR_RRS_Msk                         /*!< Regulator Ready Flag */

+#define DSI_WISR_RRIF_Pos             (13U)

+#define DSI_WISR_RRIF_Msk             (0x1UL << DSI_WISR_RRIF_Pos)             /*!< 0x00002000 */

+#define DSI_WISR_RRIF                 DSI_WISR_RRIF_Msk                        /*!< Regulator Ready Interrupt Flag */

+

+/*******************  Bit definition for DSI_WIFCR register  ***************/

+#define DSI_WIFCR_CTEIF_Pos           (0U)

+#define DSI_WIFCR_CTEIF_Msk           (0x1UL << DSI_WIFCR_CTEIF_Pos)           /*!< 0x00000001 */

+#define DSI_WIFCR_CTEIF               DSI_WIFCR_CTEIF_Msk                      /*!< Clear Tearing Effect Interrupt Flag */

+#define DSI_WIFCR_CERIF_Pos           (1U)

+#define DSI_WIFCR_CERIF_Msk           (0x1UL << DSI_WIFCR_CERIF_Pos)           /*!< 0x00000002 */

+#define DSI_WIFCR_CERIF               DSI_WIFCR_CERIF_Msk                      /*!< Clear End of Refresh Interrupt Flag */

+#define DSI_WIFCR_CPLLLIF_Pos         (9U)

+#define DSI_WIFCR_CPLLLIF_Msk         (0x1UL << DSI_WIFCR_CPLLLIF_Pos)         /*!< 0x00000200 */

+#define DSI_WIFCR_CPLLLIF             DSI_WIFCR_CPLLLIF_Msk                    /*!< Clear PLL Lock Interrupt Flag */

+#define DSI_WIFCR_CPLLUIF_Pos         (10U)

+#define DSI_WIFCR_CPLLUIF_Msk         (0x1UL << DSI_WIFCR_CPLLUIF_Pos)         /*!< 0x00000400 */

+#define DSI_WIFCR_CPLLUIF             DSI_WIFCR_CPLLUIF_Msk                    /*!< Clear PLL Unlock Interrupt Flag */

+#define DSI_WIFCR_CRRIF_Pos           (13U)

+#define DSI_WIFCR_CRRIF_Msk           (0x1UL << DSI_WIFCR_CRRIF_Pos)           /*!< 0x00002000 */

+#define DSI_WIFCR_CRRIF               DSI_WIFCR_CRRIF_Msk                      /*!< Clear Regulator Ready Interrupt Flag */

+

+/*******************  Bit definition for DSI_WPCR0 register  ***************/

+#define DSI_WPCR0_UIX4_Pos            (0U)

+#define DSI_WPCR0_UIX4_Msk            (0x3FUL << DSI_WPCR0_UIX4_Pos)           /*!< 0x0000003F */

+#define DSI_WPCR0_UIX4                DSI_WPCR0_UIX4_Msk                       /*!< Unit Interval multiplied by 4 */

+#define DSI_WPCR0_UIX4_0              (0x01UL << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000001 */

+#define DSI_WPCR0_UIX4_1              (0x02UL << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000002 */

+#define DSI_WPCR0_UIX4_2              (0x04UL << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000004 */

+#define DSI_WPCR0_UIX4_3              (0x08UL << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000008 */

+#define DSI_WPCR0_UIX4_4              (0x10UL << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000010 */

+#define DSI_WPCR0_UIX4_5              (0x20UL << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000020 */

+

+#define DSI_WPCR0_SWCL_Pos            (6U)

+#define DSI_WPCR0_SWCL_Msk            (0x1UL << DSI_WPCR0_SWCL_Pos)            /*!< 0x00000040 */

+#define DSI_WPCR0_SWCL                DSI_WPCR0_SWCL_Msk                       /*!< Swap pins on clock lane */

+#define DSI_WPCR0_SWDL0_Pos           (7U)

+#define DSI_WPCR0_SWDL0_Msk           (0x1UL << DSI_WPCR0_SWDL0_Pos)           /*!< 0x00000080 */

+#define DSI_WPCR0_SWDL0               DSI_WPCR0_SWDL0_Msk                      /*!< Swap pins on data lane 1 */

+#define DSI_WPCR0_SWDL1_Pos           (8U)

+#define DSI_WPCR0_SWDL1_Msk           (0x1UL << DSI_WPCR0_SWDL1_Pos)           /*!< 0x00000100 */

+#define DSI_WPCR0_SWDL1               DSI_WPCR0_SWDL1_Msk                      /*!< Swap pins on data lane 2 */

+#define DSI_WPCR0_HSICL_Pos           (9U)

+#define DSI_WPCR0_HSICL_Msk           (0x1UL << DSI_WPCR0_HSICL_Pos)           /*!< 0x00000200 */

+#define DSI_WPCR0_HSICL               DSI_WPCR0_HSICL_Msk                      /*!< Invert the high-speed data signal on clock lane */

+#define DSI_WPCR0_HSIDL0_Pos          (10U)

+#define DSI_WPCR0_HSIDL0_Msk          (0x1UL << DSI_WPCR0_HSIDL0_Pos)          /*!< 0x00000400 */

+#define DSI_WPCR0_HSIDL0              DSI_WPCR0_HSIDL0_Msk                     /*!< Invert the high-speed data signal on lane 1 */

+#define DSI_WPCR0_HSIDL1_Pos          (11U)

+#define DSI_WPCR0_HSIDL1_Msk          (0x1UL << DSI_WPCR0_HSIDL1_Pos)          /*!< 0x00000800 */

+#define DSI_WPCR0_HSIDL1              DSI_WPCR0_HSIDL1_Msk                     /*!< Invert the high-speed data signal on lane 2 */

+#define DSI_WPCR0_FTXSMCL_Pos         (12U)

+#define DSI_WPCR0_FTXSMCL_Msk         (0x1UL << DSI_WPCR0_FTXSMCL_Pos)         /*!< 0x00001000 */

+#define DSI_WPCR0_FTXSMCL             DSI_WPCR0_FTXSMCL_Msk                    /*!< Force clock lane in TX stop mode */

+#define DSI_WPCR0_FTXSMDL_Pos         (13U)

+#define DSI_WPCR0_FTXSMDL_Msk         (0x1UL << DSI_WPCR0_FTXSMDL_Pos)         /*!< 0x00002000 */

+#define DSI_WPCR0_FTXSMDL             DSI_WPCR0_FTXSMDL_Msk                    /*!< Force data lanes in TX stop mode */

+#define DSI_WPCR0_CDOFFDL_Pos         (14U)

+#define DSI_WPCR0_CDOFFDL_Msk         (0x1UL << DSI_WPCR0_CDOFFDL_Pos)         /*!< 0x00004000 */

+#define DSI_WPCR0_CDOFFDL             DSI_WPCR0_CDOFFDL_Msk                    /*!< Contention detection OFF */

+#define DSI_WPCR0_TDDL_Pos            (16U)

+#define DSI_WPCR0_TDDL_Msk            (0x1UL << DSI_WPCR0_TDDL_Pos)            /*!< 0x00010000 */

+#define DSI_WPCR0_TDDL                DSI_WPCR0_TDDL_Msk                       /*!< Turn Disable Data Lanes */

+#define DSI_WPCR0_PDEN_Pos            (18U)

+#define DSI_WPCR0_PDEN_Msk            (0x1UL << DSI_WPCR0_PDEN_Pos)            /*!< 0x00040000 */

+#define DSI_WPCR0_PDEN                DSI_WPCR0_PDEN_Msk                       /*!< Pull-Down Enable */

+#define DSI_WPCR0_TCLKPREPEN_Pos      (19U)

+#define DSI_WPCR0_TCLKPREPEN_Msk      (0x1UL << DSI_WPCR0_TCLKPREPEN_Pos)      /*!< 0x00080000 */

+#define DSI_WPCR0_TCLKPREPEN          DSI_WPCR0_TCLKPREPEN_Msk                 /*!< Timer for t-CLKPREP Enable */

+#define DSI_WPCR0_TCLKZEROEN_Pos      (20U)

+#define DSI_WPCR0_TCLKZEROEN_Msk      (0x1UL << DSI_WPCR0_TCLKZEROEN_Pos)      /*!< 0x00100000 */

+#define DSI_WPCR0_TCLKZEROEN          DSI_WPCR0_TCLKZEROEN_Msk                 /*!< Timer for t-CLKZERO Enable */

+#define DSI_WPCR0_THSPREPEN_Pos       (21U)

+#define DSI_WPCR0_THSPREPEN_Msk       (0x1UL << DSI_WPCR0_THSPREPEN_Pos)       /*!< 0x00200000 */

+#define DSI_WPCR0_THSPREPEN           DSI_WPCR0_THSPREPEN_Msk                  /*!< Timer for t-HSPREP Enable */

+#define DSI_WPCR0_THSTRAILEN_Pos      (22U)

+#define DSI_WPCR0_THSTRAILEN_Msk      (0x1UL << DSI_WPCR0_THSTRAILEN_Pos)      /*!< 0x00400000 */

+#define DSI_WPCR0_THSTRAILEN          DSI_WPCR0_THSTRAILEN_Msk                 /*!< Timer for t-HSTRAIL Enable */

+#define DSI_WPCR0_THSZEROEN_Pos       (23U)

+#define DSI_WPCR0_THSZEROEN_Msk       (0x1UL << DSI_WPCR0_THSZEROEN_Pos)       /*!< 0x00800000 */

+#define DSI_WPCR0_THSZEROEN           DSI_WPCR0_THSZEROEN_Msk                  /*!< Timer for t-HSZERO Enable */

+#define DSI_WPCR0_TLPXDEN_Pos         (24U)

+#define DSI_WPCR0_TLPXDEN_Msk         (0x1UL << DSI_WPCR0_TLPXDEN_Pos)         /*!< 0x01000000 */

+#define DSI_WPCR0_TLPXDEN             DSI_WPCR0_TLPXDEN_Msk                    /*!< Timer for t-LPXD Enable */

+#define DSI_WPCR0_THSEXITEN_Pos       (25U)

+#define DSI_WPCR0_THSEXITEN_Msk       (0x1UL << DSI_WPCR0_THSEXITEN_Pos)       /*!< 0x02000000 */

+#define DSI_WPCR0_THSEXITEN           DSI_WPCR0_THSEXITEN_Msk                  /*!< Timer for t-HSEXIT Enable */

+#define DSI_WPCR0_TLPXCEN_Pos         (26U)

+#define DSI_WPCR0_TLPXCEN_Msk         (0x1UL << DSI_WPCR0_TLPXCEN_Pos)         /*!< 0x04000000 */

+#define DSI_WPCR0_TLPXCEN             DSI_WPCR0_TLPXCEN_Msk                    /*!< Timer for t-LPXC Enable */

+#define DSI_WPCR0_TCLKPOSTEN_Pos      (27U)

+#define DSI_WPCR0_TCLKPOSTEN_Msk      (0x1UL << DSI_WPCR0_TCLKPOSTEN_Pos)      /*!< 0x08000000 */

+#define DSI_WPCR0_TCLKPOSTEN          DSI_WPCR0_TCLKPOSTEN_Msk                 /*!< Timer for t-CLKPOST Enable */

+

+/*******************  Bit definition for DSI_WPCR1 register  ***************/

+#define DSI_WPCR1_HSTXDCL_Pos         (0U)

+#define DSI_WPCR1_HSTXDCL_Msk         (0x3UL << DSI_WPCR1_HSTXDCL_Pos)         /*!< 0x00000003 */

+#define DSI_WPCR1_HSTXDCL             DSI_WPCR1_HSTXDCL_Msk                    /*!< High-Speed Transmission Delay on Clock Lane */

+#define DSI_WPCR1_HSTXDCL0_Pos        (0U)

+#define DSI_WPCR1_HSTXDCL0_Msk        (0x1UL << DSI_WPCR1_HSTXDCL0_Pos)        /*!< 0x00000001 */

+#define DSI_WPCR1_HSTXDCL0            DSI_WPCR1_HSTXDCL0_Msk

+#define DSI_WPCR1_HSTXDCL1_Pos        (1U)

+#define DSI_WPCR1_HSTXDCL1_Msk        (0x1UL << DSI_WPCR1_HSTXDCL1_Pos)        /*!< 0x00000002 */

+#define DSI_WPCR1_HSTXDCL1            DSI_WPCR1_HSTXDCL1_Msk

+

+#define DSI_WPCR1_HSTXDDL_Pos         (2U)

+#define DSI_WPCR1_HSTXDDL_Msk         (0x3UL << DSI_WPCR1_HSTXDDL_Pos)         /*!< 0x0000000C */

+#define DSI_WPCR1_HSTXDDL             DSI_WPCR1_HSTXDDL_Msk                    /*!< High-Speed Transmission Delay on Data Lane */

+#define DSI_WPCR1_HSTXDDL0_Pos        (2U)

+#define DSI_WPCR1_HSTXDDL0_Msk        (0x1UL << DSI_WPCR1_HSTXDDL0_Pos)        /*!< 0x00000004 */

+#define DSI_WPCR1_HSTXDDL0            DSI_WPCR1_HSTXDDL0_Msk

+#define DSI_WPCR1_HSTXDDL1_Pos        (3U)

+#define DSI_WPCR1_HSTXDDL1_Msk        (0x1UL << DSI_WPCR1_HSTXDDL1_Pos)        /*!< 0x00000008 */

+#define DSI_WPCR1_HSTXDDL1            DSI_WPCR1_HSTXDDL1_Msk

+

+#define DSI_WPCR1_LPSRCCL_Pos         (6U)

+#define DSI_WPCR1_LPSRCCL_Msk         (0x3UL << DSI_WPCR1_LPSRCCL_Pos)         /*!< 0x000000C0 */

+#define DSI_WPCR1_LPSRCCL             DSI_WPCR1_LPSRCCL_Msk                    /*!< Low-Power transmission Slew Rate Compensation on Clock Lane */

+#define DSI_WPCR1_LPSRCCL0_Pos        (6U)

+#define DSI_WPCR1_LPSRCCL0_Msk        (0x1UL << DSI_WPCR1_LPSRCCL0_Pos)        /*!< 0x00000040 */

+#define DSI_WPCR1_LPSRCCL0            DSI_WPCR1_LPSRCCL0_Msk

+#define DSI_WPCR1_LPSRCCL1_Pos        (7U)

+#define DSI_WPCR1_LPSRCCL1_Msk        (0x1UL << DSI_WPCR1_LPSRCCL1_Pos)        /*!< 0x00000080 */

+#define DSI_WPCR1_LPSRCCL1            DSI_WPCR1_LPSRCCL1_Msk

+

+#define DSI_WPCR1_LPSRCDL_Pos         (8U)

+#define DSI_WPCR1_LPSRCDL_Msk         (0x3UL << DSI_WPCR1_LPSRCDL_Pos)         /*!< 0x00000300 */

+#define DSI_WPCR1_LPSRCDL             DSI_WPCR1_LPSRCDL_Msk                    /*!< Low-Power transmission Slew Rate Compensation on Data Lane */

+#define DSI_WPCR1_LPSRCDL0_Pos        (8U)

+#define DSI_WPCR1_LPSRCDL0_Msk        (0x1UL << DSI_WPCR1_LPSRCDL0_Pos)        /*!< 0x00000100 */

+#define DSI_WPCR1_LPSRCDL0            DSI_WPCR1_LPSRCDL0_Msk

+#define DSI_WPCR1_LPSRCDL1_Pos        (9U)

+#define DSI_WPCR1_LPSRCDL1_Msk        (0x1UL << DSI_WPCR1_LPSRCDL1_Pos)        /*!< 0x00000200 */

+#define DSI_WPCR1_LPSRCDL1            DSI_WPCR1_LPSRCDL1_Msk

+

+#define DSI_WPCR1_SDDC_Pos            (12U)

+#define DSI_WPCR1_SDDC_Msk            (0x1UL << DSI_WPCR1_SDDC_Pos)            /*!< 0x00001000 */

+#define DSI_WPCR1_SDDC                DSI_WPCR1_SDDC_Msk                       /*!< SDD Control */

+

+#define DSI_WPCR1_LPRXVCDL_Pos        (14U)

+#define DSI_WPCR1_LPRXVCDL_Msk        (0x3UL << DSI_WPCR1_LPRXVCDL_Pos)        /*!< 0x0000C000 */

+#define DSI_WPCR1_LPRXVCDL            DSI_WPCR1_LPRXVCDL_Msk                   /*!< Low-Power Reception V-IL Compensation on Data Lanes */

+#define DSI_WPCR1_LPRXVCDL0_Pos       (14U)

+#define DSI_WPCR1_LPRXVCDL0_Msk       (0x1UL << DSI_WPCR1_LPRXVCDL0_Pos)       /*!< 0x00004000 */

+#define DSI_WPCR1_LPRXVCDL0           DSI_WPCR1_LPRXVCDL0_Msk

+#define DSI_WPCR1_LPRXVCDL1_Pos       (15U)

+#define DSI_WPCR1_LPRXVCDL1_Msk       (0x1UL << DSI_WPCR1_LPRXVCDL1_Pos)       /*!< 0x00008000 */

+#define DSI_WPCR1_LPRXVCDL1           DSI_WPCR1_LPRXVCDL1_Msk

+

+#define DSI_WPCR1_HSTXSRCCL_Pos       (16U)

+#define DSI_WPCR1_HSTXSRCCL_Msk       (0x3UL << DSI_WPCR1_HSTXSRCCL_Pos)       /*!< 0x00030000 */

+#define DSI_WPCR1_HSTXSRCCL           DSI_WPCR1_HSTXSRCCL_Msk                  /*!< High-Speed Transmission Delay on Clock Lane */

+#define DSI_WPCR1_HSTXSRCCL0_Pos      (16U)

+#define DSI_WPCR1_HSTXSRCCL0_Msk      (0x1UL << DSI_WPCR1_HSTXSRCCL0_Pos)      /*!< 0x00010000 */

+#define DSI_WPCR1_HSTXSRCCL0          DSI_WPCR1_HSTXSRCCL0_Msk

+#define DSI_WPCR1_HSTXSRCCL1_Pos      (17U)

+#define DSI_WPCR1_HSTXSRCCL1_Msk      (0x1UL << DSI_WPCR1_HSTXSRCCL1_Pos)      /*!< 0x00020000 */

+#define DSI_WPCR1_HSTXSRCCL1          DSI_WPCR1_HSTXSRCCL1_Msk

+

+#define DSI_WPCR1_HSTXSRCDL_Pos       (18U)

+#define DSI_WPCR1_HSTXSRCDL_Msk       (0x3UL << DSI_WPCR1_HSTXSRCDL_Pos)       /*!< 0x000C0000 */

+#define DSI_WPCR1_HSTXSRCDL           DSI_WPCR1_HSTXSRCDL_Msk                  /*!< High-Speed Transmission Delay on Data Lane */

+#define DSI_WPCR1_HSTXSRCDL0_Pos      (18U)

+#define DSI_WPCR1_HSTXSRCDL0_Msk      (0x1UL << DSI_WPCR1_HSTXSRCDL0_Pos)      /*!< 0x00040000 */

+#define DSI_WPCR1_HSTXSRCDL0          DSI_WPCR1_HSTXSRCDL0_Msk

+#define DSI_WPCR1_HSTXSRCDL1_Pos      (19U)

+#define DSI_WPCR1_HSTXSRCDL1_Msk      (0x1UL << DSI_WPCR1_HSTXSRCDL1_Pos)      /*!< 0x00080000 */

+#define DSI_WPCR1_HSTXSRCDL1          DSI_WPCR1_HSTXSRCDL1_Msk

+

+#define DSI_WPCR1_FLPRXLPM_Pos        (22U)

+#define DSI_WPCR1_FLPRXLPM_Msk        (0x1UL << DSI_WPCR1_FLPRXLPM_Pos)        /*!< 0x00400000 */

+#define DSI_WPCR1_FLPRXLPM            DSI_WPCR1_FLPRXLPM_Msk                   /*!< Forces LP Receiver in Low-Power Mode */

+

+#define DSI_WPCR1_LPRXFT_Pos          (25U)

+#define DSI_WPCR1_LPRXFT_Msk          (0x3UL << DSI_WPCR1_LPRXFT_Pos)          /*!< 0x06000000 */

+#define DSI_WPCR1_LPRXFT              DSI_WPCR1_LPRXFT_Msk                     /*!< Low-Power RX low-pass Filtering Tuning */

+#define DSI_WPCR1_LPRXFT0_Pos         (25U)

+#define DSI_WPCR1_LPRXFT0_Msk         (0x1UL << DSI_WPCR1_LPRXFT0_Pos)         /*!< 0x02000000 */

+#define DSI_WPCR1_LPRXFT0             DSI_WPCR1_LPRXFT0_Msk

+#define DSI_WPCR1_LPRXFT1_Pos         (26U)

+#define DSI_WPCR1_LPRXFT1_Msk         (0x1UL << DSI_WPCR1_LPRXFT1_Pos)         /*!< 0x04000000 */

+#define DSI_WPCR1_LPRXFT1             DSI_WPCR1_LPRXFT1_Msk

+

+/*******************  Bit definition for DSI_WPCR2 register  ***************/

+#define DSI_WPCR2_TCLKPREP_Pos        (0U)

+#define DSI_WPCR2_TCLKPREP_Msk        (0xFFUL << DSI_WPCR2_TCLKPREP_Pos)       /*!< 0x000000FF */

+#define DSI_WPCR2_TCLKPREP            DSI_WPCR2_TCLKPREP_Msk                   /*!< t-CLKPREP */

+#define DSI_WPCR2_TCLKPREP0_Pos       (0U)

+#define DSI_WPCR2_TCLKPREP0_Msk       (0x1UL << DSI_WPCR2_TCLKPREP0_Pos)       /*!< 0x00000001 */

+#define DSI_WPCR2_TCLKPREP0           DSI_WPCR2_TCLKPREP0_Msk

+#define DSI_WPCR2_TCLKPREP1_Pos       (1U)

+#define DSI_WPCR2_TCLKPREP1_Msk       (0x1UL << DSI_WPCR2_TCLKPREP1_Pos)       /*!< 0x00000002 */

+#define DSI_WPCR2_TCLKPREP1           DSI_WPCR2_TCLKPREP1_Msk

+#define DSI_WPCR2_TCLKPREP2_Pos       (2U)

+#define DSI_WPCR2_TCLKPREP2_Msk       (0x1UL << DSI_WPCR2_TCLKPREP2_Pos)       /*!< 0x00000004 */

+#define DSI_WPCR2_TCLKPREP2           DSI_WPCR2_TCLKPREP2_Msk

+#define DSI_WPCR2_TCLKPREP3_Pos       (3U)

+#define DSI_WPCR2_TCLKPREP3_Msk       (0x1UL << DSI_WPCR2_TCLKPREP3_Pos)       /*!< 0x00000008 */

+#define DSI_WPCR2_TCLKPREP3           DSI_WPCR2_TCLKPREP3_Msk

+#define DSI_WPCR2_TCLKPREP4_Pos       (4U)

+#define DSI_WPCR2_TCLKPREP4_Msk       (0x1UL << DSI_WPCR2_TCLKPREP4_Pos)       /*!< 0x00000010 */

+#define DSI_WPCR2_TCLKPREP4           DSI_WPCR2_TCLKPREP4_Msk

+#define DSI_WPCR2_TCLKPREP5_Pos       (5U)

+#define DSI_WPCR2_TCLKPREP5_Msk       (0x1UL << DSI_WPCR2_TCLKPREP5_Pos)       /*!< 0x00000020 */

+#define DSI_WPCR2_TCLKPREP5           DSI_WPCR2_TCLKPREP5_Msk

+#define DSI_WPCR2_TCLKPREP6_Pos       (6U)

+#define DSI_WPCR2_TCLKPREP6_Msk       (0x1UL << DSI_WPCR2_TCLKPREP6_Pos)       /*!< 0x00000040 */

+#define DSI_WPCR2_TCLKPREP6           DSI_WPCR2_TCLKPREP6_Msk

+#define DSI_WPCR2_TCLKPREP7_Pos       (7U)

+#define DSI_WPCR2_TCLKPREP7_Msk       (0x1UL << DSI_WPCR2_TCLKPREP7_Pos)       /*!< 0x00000080 */

+#define DSI_WPCR2_TCLKPREP7           DSI_WPCR2_TCLKPREP7_Msk

+

+#define DSI_WPCR2_TCLKZERO_Pos        (8U)

+#define DSI_WPCR2_TCLKZERO_Msk        (0xFFUL << DSI_WPCR2_TCLKZERO_Pos)       /*!< 0x0000FF00 */

+#define DSI_WPCR2_TCLKZERO            DSI_WPCR2_TCLKZERO_Msk                   /*!< t-CLKZERO */

+#define DSI_WPCR2_TCLKZERO0_Pos       (8U)

+#define DSI_WPCR2_TCLKZERO0_Msk       (0x1UL << DSI_WPCR2_TCLKZERO0_Pos)       /*!< 0x00000100 */

+#define DSI_WPCR2_TCLKZERO0           DSI_WPCR2_TCLKZERO0_Msk

+#define DSI_WPCR2_TCLKZERO1_Pos       (9U)

+#define DSI_WPCR2_TCLKZERO1_Msk       (0x1UL << DSI_WPCR2_TCLKZERO1_Pos)       /*!< 0x00000200 */

+#define DSI_WPCR2_TCLKZERO1           DSI_WPCR2_TCLKZERO1_Msk

+#define DSI_WPCR2_TCLKZERO2_Pos       (10U)

+#define DSI_WPCR2_TCLKZERO2_Msk       (0x1UL << DSI_WPCR2_TCLKZERO2_Pos)       /*!< 0x00000400 */

+#define DSI_WPCR2_TCLKZERO2           DSI_WPCR2_TCLKZERO2_Msk

+#define DSI_WPCR2_TCLKZERO3_Pos       (11U)

+#define DSI_WPCR2_TCLKZERO3_Msk       (0x1UL << DSI_WPCR2_TCLKZERO3_Pos)       /*!< 0x00000800 */

+#define DSI_WPCR2_TCLKZERO3           DSI_WPCR2_TCLKZERO3_Msk

+#define DSI_WPCR2_TCLKZERO4_Pos       (12U)

+#define DSI_WPCR2_TCLKZERO4_Msk       (0x1UL << DSI_WPCR2_TCLKZERO4_Pos)       /*!< 0x00001000 */

+#define DSI_WPCR2_TCLKZERO4           DSI_WPCR2_TCLKZERO4_Msk

+#define DSI_WPCR2_TCLKZERO5_Pos       (13U)

+#define DSI_WPCR2_TCLKZERO5_Msk       (0x1UL << DSI_WPCR2_TCLKZERO5_Pos)       /*!< 0x00002000 */

+#define DSI_WPCR2_TCLKZERO5           DSI_WPCR2_TCLKZERO5_Msk

+#define DSI_WPCR2_TCLKZERO6_Pos       (14U)

+#define DSI_WPCR2_TCLKZERO6_Msk       (0x1UL << DSI_WPCR2_TCLKZERO6_Pos)       /*!< 0x00004000 */

+#define DSI_WPCR2_TCLKZERO6           DSI_WPCR2_TCLKZERO6_Msk

+#define DSI_WPCR2_TCLKZERO7_Pos       (15U)

+#define DSI_WPCR2_TCLKZERO7_Msk       (0x1UL << DSI_WPCR2_TCLKZERO7_Pos)       /*!< 0x00008000 */

+#define DSI_WPCR2_TCLKZERO7           DSI_WPCR2_TCLKZERO7_Msk

+

+#define DSI_WPCR2_THSPREP_Pos         (16U)

+#define DSI_WPCR2_THSPREP_Msk         (0xFFUL << DSI_WPCR2_THSPREP_Pos)        /*!< 0x00FF0000 */

+#define DSI_WPCR2_THSPREP             DSI_WPCR2_THSPREP_Msk                    /*!< t-HSPREP */

+#define DSI_WPCR2_THSPREP0_Pos        (16U)

+#define DSI_WPCR2_THSPREP0_Msk        (0x1UL << DSI_WPCR2_THSPREP0_Pos)        /*!< 0x00010000 */

+#define DSI_WPCR2_THSPREP0            DSI_WPCR2_THSPREP0_Msk

+#define DSI_WPCR2_THSPREP1_Pos        (17U)

+#define DSI_WPCR2_THSPREP1_Msk        (0x1UL << DSI_WPCR2_THSPREP1_Pos)        /*!< 0x00020000 */

+#define DSI_WPCR2_THSPREP1            DSI_WPCR2_THSPREP1_Msk

+#define DSI_WPCR2_THSPREP2_Pos        (18U)

+#define DSI_WPCR2_THSPREP2_Msk        (0x1UL << DSI_WPCR2_THSPREP2_Pos)        /*!< 0x00040000 */

+#define DSI_WPCR2_THSPREP2            DSI_WPCR2_THSPREP2_Msk

+#define DSI_WPCR2_THSPREP3_Pos        (19U)

+#define DSI_WPCR2_THSPREP3_Msk        (0x1UL << DSI_WPCR2_THSPREP3_Pos)        /*!< 0x00080000 */

+#define DSI_WPCR2_THSPREP3            DSI_WPCR2_THSPREP3_Msk

+#define DSI_WPCR2_THSPREP4_Pos        (20U)

+#define DSI_WPCR2_THSPREP4_Msk        (0x1UL << DSI_WPCR2_THSPREP4_Pos)        /*!< 0x00100000 */

+#define DSI_WPCR2_THSPREP4            DSI_WPCR2_THSPREP4_Msk

+#define DSI_WPCR2_THSPREP5_Pos        (21U)

+#define DSI_WPCR2_THSPREP5_Msk        (0x1UL << DSI_WPCR2_THSPREP5_Pos)        /*!< 0x00200000 */

+#define DSI_WPCR2_THSPREP5            DSI_WPCR2_THSPREP5_Msk

+#define DSI_WPCR2_THSPREP6_Pos        (22U)

+#define DSI_WPCR2_THSPREP6_Msk        (0x1UL << DSI_WPCR2_THSPREP6_Pos)        /*!< 0x00400000 */

+#define DSI_WPCR2_THSPREP6            DSI_WPCR2_THSPREP6_Msk

+#define DSI_WPCR2_THSPREP7_Pos        (23U)

+#define DSI_WPCR2_THSPREP7_Msk        (0x1UL << DSI_WPCR2_THSPREP7_Pos)        /*!< 0x00800000 */

+#define DSI_WPCR2_THSPREP7            DSI_WPCR2_THSPREP7_Msk

+

+#define DSI_WPCR2_THSTRAIL_Pos        (24U)

+#define DSI_WPCR2_THSTRAIL_Msk        (0xFFUL << DSI_WPCR2_THSTRAIL_Pos)       /*!< 0xFF000000 */

+#define DSI_WPCR2_THSTRAIL            DSI_WPCR2_THSTRAIL_Msk                   /*!< t-HSTRAIL */

+#define DSI_WPCR2_THSTRAIL0_Pos       (24U)

+#define DSI_WPCR2_THSTRAIL0_Msk       (0x1UL << DSI_WPCR2_THSTRAIL0_Pos)       /*!< 0x01000000 */

+#define DSI_WPCR2_THSTRAIL0           DSI_WPCR2_THSTRAIL0_Msk

+#define DSI_WPCR2_THSTRAIL1_Pos       (25U)

+#define DSI_WPCR2_THSTRAIL1_Msk       (0x1UL << DSI_WPCR2_THSTRAIL1_Pos)       /*!< 0x02000000 */

+#define DSI_WPCR2_THSTRAIL1           DSI_WPCR2_THSTRAIL1_Msk

+#define DSI_WPCR2_THSTRAIL2_Pos       (26U)

+#define DSI_WPCR2_THSTRAIL2_Msk       (0x1UL << DSI_WPCR2_THSTRAIL2_Pos)       /*!< 0x04000000 */

+#define DSI_WPCR2_THSTRAIL2           DSI_WPCR2_THSTRAIL2_Msk

+#define DSI_WPCR2_THSTRAIL3_Pos       (27U)

+#define DSI_WPCR2_THSTRAIL3_Msk       (0x1UL << DSI_WPCR2_THSTRAIL3_Pos)       /*!< 0x08000000 */

+#define DSI_WPCR2_THSTRAIL3           DSI_WPCR2_THSTRAIL3_Msk

+#define DSI_WPCR2_THSTRAIL4_Pos       (28U)

+#define DSI_WPCR2_THSTRAIL4_Msk       (0x1UL << DSI_WPCR2_THSTRAIL4_Pos)       /*!< 0x10000000 */

+#define DSI_WPCR2_THSTRAIL4           DSI_WPCR2_THSTRAIL4_Msk

+#define DSI_WPCR2_THSTRAIL5_Pos       (29U)

+#define DSI_WPCR2_THSTRAIL5_Msk       (0x1UL << DSI_WPCR2_THSTRAIL5_Pos)       /*!< 0x20000000 */

+#define DSI_WPCR2_THSTRAIL5           DSI_WPCR2_THSTRAIL5_Msk

+#define DSI_WPCR2_THSTRAIL6_Pos       (30U)

+#define DSI_WPCR2_THSTRAIL6_Msk       (0x1UL << DSI_WPCR2_THSTRAIL6_Pos)       /*!< 0x40000000 */

+#define DSI_WPCR2_THSTRAIL6           DSI_WPCR2_THSTRAIL6_Msk

+#define DSI_WPCR2_THSTRAIL7_Pos       (31U)

+#define DSI_WPCR2_THSTRAIL7_Msk       (0x1UL << DSI_WPCR2_THSTRAIL7_Pos)       /*!< 0x80000000 */

+#define DSI_WPCR2_THSTRAIL7           DSI_WPCR2_THSTRAIL7_Msk

+

+/*******************  Bit definition for DSI_WPCR3 register  ***************/

+#define DSI_WPCR3_THSZERO_Pos         (0U)

+#define DSI_WPCR3_THSZERO_Msk         (0xFFUL << DSI_WPCR3_THSZERO_Pos)        /*!< 0x000000FF */

+#define DSI_WPCR3_THSZERO             DSI_WPCR3_THSZERO_Msk                    /*!< t-HSZERO */

+#define DSI_WPCR3_THSZERO0_Pos        (0U)

+#define DSI_WPCR3_THSZERO0_Msk        (0x1UL << DSI_WPCR3_THSZERO0_Pos)        /*!< 0x00000001 */

+#define DSI_WPCR3_THSZERO0            DSI_WPCR3_THSZERO0_Msk

+#define DSI_WPCR3_THSZERO1_Pos        (1U)

+#define DSI_WPCR3_THSZERO1_Msk        (0x1UL << DSI_WPCR3_THSZERO1_Pos)        /*!< 0x00000002 */

+#define DSI_WPCR3_THSZERO1            DSI_WPCR3_THSZERO1_Msk

+#define DSI_WPCR3_THSZERO2_Pos        (2U)

+#define DSI_WPCR3_THSZERO2_Msk        (0x1UL << DSI_WPCR3_THSZERO2_Pos)        /*!< 0x00000004 */

+#define DSI_WPCR3_THSZERO2            DSI_WPCR3_THSZERO2_Msk

+#define DSI_WPCR3_THSZERO3_Pos        (3U)

+#define DSI_WPCR3_THSZERO3_Msk        (0x1UL << DSI_WPCR3_THSZERO3_Pos)        /*!< 0x00000008 */

+#define DSI_WPCR3_THSZERO3            DSI_WPCR3_THSZERO3_Msk

+#define DSI_WPCR3_THSZERO4_Pos        (4U)

+#define DSI_WPCR3_THSZERO4_Msk        (0x1UL << DSI_WPCR3_THSZERO4_Pos)        /*!< 0x00000010 */

+#define DSI_WPCR3_THSZERO4            DSI_WPCR3_THSZERO4_Msk

+#define DSI_WPCR3_THSZERO5_Pos        (5U)

+#define DSI_WPCR3_THSZERO5_Msk        (0x1UL << DSI_WPCR3_THSZERO5_Pos)        /*!< 0x00000020 */

+#define DSI_WPCR3_THSZERO5            DSI_WPCR3_THSZERO5_Msk

+#define DSI_WPCR3_THSZERO6_Pos        (6U)

+#define DSI_WPCR3_THSZERO6_Msk        (0x1UL << DSI_WPCR3_THSZERO6_Pos)        /*!< 0x00000040 */

+#define DSI_WPCR3_THSZERO6            DSI_WPCR3_THSZERO6_Msk

+#define DSI_WPCR3_THSZERO7_Pos        (7U)

+#define DSI_WPCR3_THSZERO7_Msk        (0x1UL << DSI_WPCR3_THSZERO7_Pos)        /*!< 0x00000080 */

+#define DSI_WPCR3_THSZERO7            DSI_WPCR3_THSZERO7_Msk

+

+#define DSI_WPCR3_TLPXD_Pos           (8U)

+#define DSI_WPCR3_TLPXD_Msk           (0xFFUL << DSI_WPCR3_TLPXD_Pos)          /*!< 0x0000FF00 */

+#define DSI_WPCR3_TLPXD               DSI_WPCR3_TLPXD_Msk                      /*!< t-LPXD */

+#define DSI_WPCR3_TLPXD0_Pos          (8U)

+#define DSI_WPCR3_TLPXD0_Msk          (0x1UL << DSI_WPCR3_TLPXD0_Pos)          /*!< 0x00000100 */

+#define DSI_WPCR3_TLPXD0              DSI_WPCR3_TLPXD0_Msk

+#define DSI_WPCR3_TLPXD1_Pos          (9U)

+#define DSI_WPCR3_TLPXD1_Msk          (0x1UL << DSI_WPCR3_TLPXD1_Pos)          /*!< 0x00000200 */

+#define DSI_WPCR3_TLPXD1              DSI_WPCR3_TLPXD1_Msk

+#define DSI_WPCR3_TLPXD2_Pos          (10U)

+#define DSI_WPCR3_TLPXD2_Msk          (0x1UL << DSI_WPCR3_TLPXD2_Pos)          /*!< 0x00000400 */

+#define DSI_WPCR3_TLPXD2              DSI_WPCR3_TLPXD2_Msk

+#define DSI_WPCR3_TLPXD3_Pos          (11U)

+#define DSI_WPCR3_TLPXD3_Msk          (0x1UL << DSI_WPCR3_TLPXD3_Pos)          /*!< 0x00000800 */

+#define DSI_WPCR3_TLPXD3              DSI_WPCR3_TLPXD3_Msk

+#define DSI_WPCR3_TLPXD4_Pos          (12U)

+#define DSI_WPCR3_TLPXD4_Msk          (0x1UL << DSI_WPCR3_TLPXD4_Pos)          /*!< 0x00001000 */

+#define DSI_WPCR3_TLPXD4              DSI_WPCR3_TLPXD4_Msk

+#define DSI_WPCR3_TLPXD5_Pos          (13U)

+#define DSI_WPCR3_TLPXD5_Msk          (0x1UL << DSI_WPCR3_TLPXD5_Pos)          /*!< 0x00002000 */

+#define DSI_WPCR3_TLPXD5              DSI_WPCR3_TLPXD5_Msk

+#define DSI_WPCR3_TLPXD6_Pos          (14U)

+#define DSI_WPCR3_TLPXD6_Msk          (0x1UL << DSI_WPCR3_TLPXD6_Pos)          /*!< 0x00004000 */

+#define DSI_WPCR3_TLPXD6              DSI_WPCR3_TLPXD6_Msk

+#define DSI_WPCR3_TLPXD7_Pos          (15U)

+#define DSI_WPCR3_TLPXD7_Msk          (0x1UL << DSI_WPCR3_TLPXD7_Pos)          /*!< 0x00008000 */

+#define DSI_WPCR3_TLPXD7              DSI_WPCR3_TLPXD7_Msk

+

+#define DSI_WPCR3_THSEXIT_Pos         (16U)

+#define DSI_WPCR3_THSEXIT_Msk         (0xFFUL << DSI_WPCR3_THSEXIT_Pos)        /*!< 0x00FF0000 */

+#define DSI_WPCR3_THSEXIT             DSI_WPCR3_THSEXIT_Msk                    /*!< t-HSEXIT */

+#define DSI_WPCR3_THSEXIT0_Pos        (16U)

+#define DSI_WPCR3_THSEXIT0_Msk        (0x1UL << DSI_WPCR3_THSEXIT0_Pos)        /*!< 0x00010000 */

+#define DSI_WPCR3_THSEXIT0            DSI_WPCR3_THSEXIT0_Msk

+#define DSI_WPCR3_THSEXIT1_Pos        (17U)

+#define DSI_WPCR3_THSEXIT1_Msk        (0x1UL << DSI_WPCR3_THSEXIT1_Pos)        /*!< 0x00020000 */

+#define DSI_WPCR3_THSEXIT1            DSI_WPCR3_THSEXIT1_Msk

+#define DSI_WPCR3_THSEXIT2_Pos        (18U)

+#define DSI_WPCR3_THSEXIT2_Msk        (0x1UL << DSI_WPCR3_THSEXIT2_Pos)        /*!< 0x00040000 */

+#define DSI_WPCR3_THSEXIT2            DSI_WPCR3_THSEXIT2_Msk

+#define DSI_WPCR3_THSEXIT3_Pos        (19U)

+#define DSI_WPCR3_THSEXIT3_Msk        (0x1UL << DSI_WPCR3_THSEXIT3_Pos)        /*!< 0x00080000 */

+#define DSI_WPCR3_THSEXIT3            DSI_WPCR3_THSEXIT3_Msk

+#define DSI_WPCR3_THSEXIT4_Pos        (20U)

+#define DSI_WPCR3_THSEXIT4_Msk        (0x1UL << DSI_WPCR3_THSEXIT4_Pos)        /*!< 0x00100000 */

+#define DSI_WPCR3_THSEXIT4            DSI_WPCR3_THSEXIT4_Msk

+#define DSI_WPCR3_THSEXIT5_Pos        (21U)

+#define DSI_WPCR3_THSEXIT5_Msk        (0x1UL << DSI_WPCR3_THSEXIT5_Pos)        /*!< 0x00200000 */

+#define DSI_WPCR3_THSEXIT5            DSI_WPCR3_THSEXIT5_Msk

+#define DSI_WPCR3_THSEXIT6_Pos        (22U)

+#define DSI_WPCR3_THSEXIT6_Msk        (0x1UL << DSI_WPCR3_THSEXIT6_Pos)        /*!< 0x00400000 */

+#define DSI_WPCR3_THSEXIT6            DSI_WPCR3_THSEXIT6_Msk

+#define DSI_WPCR3_THSEXIT7_Pos        (23U)

+#define DSI_WPCR3_THSEXIT7_Msk        (0x1UL << DSI_WPCR3_THSEXIT7_Pos)        /*!< 0x00800000 */

+#define DSI_WPCR3_THSEXIT7            DSI_WPCR3_THSEXIT7_Msk

+

+#define DSI_WPCR3_TLPXC_Pos           (24U)

+#define DSI_WPCR3_TLPXC_Msk           (0xFFUL << DSI_WPCR3_TLPXC_Pos)          /*!< 0xFF000000 */

+#define DSI_WPCR3_TLPXC               DSI_WPCR3_TLPXC_Msk                      /*!< t-LPXC */

+#define DSI_WPCR3_TLPXC0_Pos          (24U)

+#define DSI_WPCR3_TLPXC0_Msk          (0x1UL << DSI_WPCR3_TLPXC0_Pos)          /*!< 0x01000000 */

+#define DSI_WPCR3_TLPXC0              DSI_WPCR3_TLPXC0_Msk

+#define DSI_WPCR3_TLPXC1_Pos          (25U)

+#define DSI_WPCR3_TLPXC1_Msk          (0x1UL << DSI_WPCR3_TLPXC1_Pos)          /*!< 0x02000000 */

+#define DSI_WPCR3_TLPXC1              DSI_WPCR3_TLPXC1_Msk

+#define DSI_WPCR3_TLPXC2_Pos          (26U)

+#define DSI_WPCR3_TLPXC2_Msk          (0x1UL << DSI_WPCR3_TLPXC2_Pos)          /*!< 0x04000000 */

+#define DSI_WPCR3_TLPXC2              DSI_WPCR3_TLPXC2_Msk

+#define DSI_WPCR3_TLPXC3_Pos          (27U)

+#define DSI_WPCR3_TLPXC3_Msk          (0x1UL << DSI_WPCR3_TLPXC3_Pos)          /*!< 0x08000000 */

+#define DSI_WPCR3_TLPXC3              DSI_WPCR3_TLPXC3_Msk

+#define DSI_WPCR3_TLPXC4_Pos          (28U)

+#define DSI_WPCR3_TLPXC4_Msk          (0x1UL << DSI_WPCR3_TLPXC4_Pos)          /*!< 0x10000000 */

+#define DSI_WPCR3_TLPXC4              DSI_WPCR3_TLPXC4_Msk

+#define DSI_WPCR3_TLPXC5_Pos          (29U)

+#define DSI_WPCR3_TLPXC5_Msk          (0x1UL << DSI_WPCR3_TLPXC5_Pos)          /*!< 0x20000000 */

+#define DSI_WPCR3_TLPXC5              DSI_WPCR3_TLPXC5_Msk

+#define DSI_WPCR3_TLPXC6_Pos          (30U)

+#define DSI_WPCR3_TLPXC6_Msk          (0x1UL << DSI_WPCR3_TLPXC6_Pos)          /*!< 0x40000000 */

+#define DSI_WPCR3_TLPXC6              DSI_WPCR3_TLPXC6_Msk

+#define DSI_WPCR3_TLPXC7_Pos          (31U)

+#define DSI_WPCR3_TLPXC7_Msk          (0x1UL << DSI_WPCR3_TLPXC7_Pos)          /*!< 0x80000000 */

+#define DSI_WPCR3_TLPXC7              DSI_WPCR3_TLPXC7_Msk

+

+/*******************  Bit definition for DSI_WPCR4 register  ***************/

+#define DSI_WPCR4_TCLKPOST_Pos        (0U)

+#define DSI_WPCR4_TCLKPOST_Msk        (0xFFUL << DSI_WPCR4_TCLKPOST_Pos)       /*!< 0x000000FF */

+#define DSI_WPCR4_TCLKPOST            DSI_WPCR4_TCLKPOST_Msk                   /*!< t-CLKPOST */

+#define DSI_WPCR4_TCLKPOST0_Pos       (0U)

+#define DSI_WPCR4_TCLKPOST0_Msk       (0x1UL << DSI_WPCR4_TCLKPOST0_Pos)       /*!< 0x00000001 */

+#define DSI_WPCR4_TCLKPOST0           DSI_WPCR4_TCLKPOST0_Msk

+#define DSI_WPCR4_TCLKPOST1_Pos       (1U)

+#define DSI_WPCR4_TCLKPOST1_Msk       (0x1UL << DSI_WPCR4_TCLKPOST1_Pos)       /*!< 0x00000002 */

+#define DSI_WPCR4_TCLKPOST1           DSI_WPCR4_TCLKPOST1_Msk

+#define DSI_WPCR4_TCLKPOST2_Pos       (2U)

+#define DSI_WPCR4_TCLKPOST2_Msk       (0x1UL << DSI_WPCR4_TCLKPOST2_Pos)       /*!< 0x00000004 */

+#define DSI_WPCR4_TCLKPOST2           DSI_WPCR4_TCLKPOST2_Msk

+#define DSI_WPCR4_TCLKPOST3_Pos       (3U)

+#define DSI_WPCR4_TCLKPOST3_Msk       (0x1UL << DSI_WPCR4_TCLKPOST3_Pos)       /*!< 0x00000008 */

+#define DSI_WPCR4_TCLKPOST3           DSI_WPCR4_TCLKPOST3_Msk

+#define DSI_WPCR4_TCLKPOST4_Pos       (4U)

+#define DSI_WPCR4_TCLKPOST4_Msk       (0x1UL << DSI_WPCR4_TCLKPOST4_Pos)       /*!< 0x00000010 */

+#define DSI_WPCR4_TCLKPOST4           DSI_WPCR4_TCLKPOST4_Msk

+#define DSI_WPCR4_TCLKPOST5_Pos       (5U)

+#define DSI_WPCR4_TCLKPOST5_Msk       (0x1UL << DSI_WPCR4_TCLKPOST5_Pos)       /*!< 0x00000020 */

+#define DSI_WPCR4_TCLKPOST5           DSI_WPCR4_TCLKPOST5_Msk

+#define DSI_WPCR4_TCLKPOST6_Pos       (6U)

+#define DSI_WPCR4_TCLKPOST6_Msk       (0x1UL << DSI_WPCR4_TCLKPOST6_Pos)       /*!< 0x00000040 */

+#define DSI_WPCR4_TCLKPOST6           DSI_WPCR4_TCLKPOST6_Msk

+#define DSI_WPCR4_TCLKPOST7_Pos       (7U)

+#define DSI_WPCR4_TCLKPOST7_Msk       (0x1UL << DSI_WPCR4_TCLKPOST7_Pos)       /*!< 0x00000080 */

+#define DSI_WPCR4_TCLKPOST7           DSI_WPCR4_TCLKPOST7_Msk

+

+/*******************  Bit definition for DSI_WRPCR register  ***************/

+#define DSI_WRPCR_PLLEN_Pos           (0U)

+#define DSI_WRPCR_PLLEN_Msk           (0x1UL << DSI_WRPCR_PLLEN_Pos)           /*!< 0x00000001 */

+#define DSI_WRPCR_PLLEN               DSI_WRPCR_PLLEN_Msk                      /*!< PLL Enable */

+#define DSI_WRPCR_PLL_NDIV_Pos        (2U)

+#define DSI_WRPCR_PLL_NDIV_Msk        (0x7FUL << DSI_WRPCR_PLL_NDIV_Pos)       /*!< 0x000001FC */

+#define DSI_WRPCR_PLL_NDIV            DSI_WRPCR_PLL_NDIV_Msk                   /*!< PLL Loop Division Factor */

+#define DSI_WRPCR_PLL_NDIV0_Pos       (2U)

+#define DSI_WRPCR_PLL_NDIV0_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV0_Pos)       /*!< 0x00000004 */

+#define DSI_WRPCR_PLL_NDIV0           DSI_WRPCR_PLL_NDIV0_Msk

+#define DSI_WRPCR_PLL_NDIV1_Pos       (3U)

+#define DSI_WRPCR_PLL_NDIV1_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV1_Pos)       /*!< 0x00000008 */

+#define DSI_WRPCR_PLL_NDIV1           DSI_WRPCR_PLL_NDIV1_Msk

+#define DSI_WRPCR_PLL_NDIV2_Pos       (4U)

+#define DSI_WRPCR_PLL_NDIV2_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV2_Pos)       /*!< 0x00000010 */

+#define DSI_WRPCR_PLL_NDIV2           DSI_WRPCR_PLL_NDIV2_Msk

+#define DSI_WRPCR_PLL_NDIV3_Pos       (5U)

+#define DSI_WRPCR_PLL_NDIV3_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV3_Pos)       /*!< 0x00000020 */

+#define DSI_WRPCR_PLL_NDIV3           DSI_WRPCR_PLL_NDIV3_Msk

+#define DSI_WRPCR_PLL_NDIV4_Pos       (6U)

+#define DSI_WRPCR_PLL_NDIV4_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV4_Pos)       /*!< 0x00000040 */

+#define DSI_WRPCR_PLL_NDIV4           DSI_WRPCR_PLL_NDIV4_Msk

+#define DSI_WRPCR_PLL_NDIV5_Pos       (7U)

+#define DSI_WRPCR_PLL_NDIV5_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV5_Pos)       /*!< 0x00000080 */

+#define DSI_WRPCR_PLL_NDIV5           DSI_WRPCR_PLL_NDIV5_Msk

+#define DSI_WRPCR_PLL_NDIV6_Pos       (8U)

+#define DSI_WRPCR_PLL_NDIV6_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV6_Pos)       /*!< 0x00000100 */

+#define DSI_WRPCR_PLL_NDIV6           DSI_WRPCR_PLL_NDIV6_Msk

+

+#define DSI_WRPCR_PLL_IDF_Pos         (11U)

+#define DSI_WRPCR_PLL_IDF_Msk         (0xFUL << DSI_WRPCR_PLL_IDF_Pos)         /*!< 0x00007800 */

+#define DSI_WRPCR_PLL_IDF             DSI_WRPCR_PLL_IDF_Msk                    /*!< PLL Input Division Factor */

+#define DSI_WRPCR_PLL_IDF0_Pos        (11U)

+#define DSI_WRPCR_PLL_IDF0_Msk        (0x1UL << DSI_WRPCR_PLL_IDF0_Pos)        /*!< 0x00000800 */

+#define DSI_WRPCR_PLL_IDF0            DSI_WRPCR_PLL_IDF0_Msk

+#define DSI_WRPCR_PLL_IDF1_Pos        (12U)

+#define DSI_WRPCR_PLL_IDF1_Msk        (0x1UL << DSI_WRPCR_PLL_IDF1_Pos)        /*!< 0x00001000 */

+#define DSI_WRPCR_PLL_IDF1            DSI_WRPCR_PLL_IDF1_Msk

+#define DSI_WRPCR_PLL_IDF2_Pos        (13U)

+#define DSI_WRPCR_PLL_IDF2_Msk        (0x1UL << DSI_WRPCR_PLL_IDF2_Pos)        /*!< 0x00002000 */

+#define DSI_WRPCR_PLL_IDF2            DSI_WRPCR_PLL_IDF2_Msk

+#define DSI_WRPCR_PLL_IDF3_Pos        (14U)

+#define DSI_WRPCR_PLL_IDF3_Msk        (0x1UL << DSI_WRPCR_PLL_IDF3_Pos)        /*!< 0x00004000 */

+#define DSI_WRPCR_PLL_IDF3            DSI_WRPCR_PLL_IDF3_Msk

+

+#define DSI_WRPCR_PLL_ODF_Pos         (16U)

+#define DSI_WRPCR_PLL_ODF_Msk         (0x3UL << DSI_WRPCR_PLL_ODF_Pos)         /*!< 0x00030000 */

+#define DSI_WRPCR_PLL_ODF             DSI_WRPCR_PLL_ODF_Msk                    /*!< PLL Output Division Factor */

+#define DSI_WRPCR_PLL_ODF0_Pos        (16U)

+#define DSI_WRPCR_PLL_ODF0_Msk        (0x1UL << DSI_WRPCR_PLL_ODF0_Pos)        /*!< 0x00010000 */

+#define DSI_WRPCR_PLL_ODF0            DSI_WRPCR_PLL_ODF0_Msk

+#define DSI_WRPCR_PLL_ODF1_Pos        (17U)

+#define DSI_WRPCR_PLL_ODF1_Msk        (0x1UL << DSI_WRPCR_PLL_ODF1_Pos)        /*!< 0x00020000 */

+#define DSI_WRPCR_PLL_ODF1            DSI_WRPCR_PLL_ODF1_Msk

+

+#define DSI_WRPCR_REGEN_Pos           (24U)

+#define DSI_WRPCR_REGEN_Msk           (0x1UL << DSI_WRPCR_REGEN_Pos)           /*!< 0x01000000 */

+#define DSI_WRPCR_REGEN               DSI_WRPCR_REGEN_Msk                      /*!< Regulator Enable */

+

+/******************************************************************************/

+/*                                                                            */

+/*                    External Interrupt/Event Controller                     */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for EXTI_RTSR1 register  *******************/

+#define EXTI_RTSR1_TR_Pos          (0U)

+#define EXTI_RTSR1_TR_Msk          (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)           /*!< 0x003FFFFF */

+#define EXTI_RTSR1_TR              EXTI_RTSR1_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR1_TR0_Pos         (0U)

+#define EXTI_RTSR1_TR0_Msk         (0x1UL << EXTI_RTSR1_TR0_Pos)               /*!< 0x00000001 */

+#define EXTI_RTSR1_TR0             EXTI_RTSR1_TR0_Msk                          /*!< Rising trigger event configuration bit of line 0 */

+#define EXTI_RTSR1_TR1_Pos         (1U)

+#define EXTI_RTSR1_TR1_Msk         (0x1UL << EXTI_RTSR1_TR1_Pos)               /*!< 0x00000002 */

+#define EXTI_RTSR1_TR1             EXTI_RTSR1_TR1_Msk                          /*!< Rising trigger event configuration bit of line 1 */

+#define EXTI_RTSR1_TR2_Pos         (2U)

+#define EXTI_RTSR1_TR2_Msk         (0x1UL << EXTI_RTSR1_TR2_Pos)               /*!< 0x00000004 */

+#define EXTI_RTSR1_TR2             EXTI_RTSR1_TR2_Msk                          /*!< Rising trigger event configuration bit of line 2 */

+#define EXTI_RTSR1_TR3_Pos         (3U)

+#define EXTI_RTSR1_TR3_Msk         (0x1UL << EXTI_RTSR1_TR3_Pos)               /*!< 0x00000008 */

+#define EXTI_RTSR1_TR3             EXTI_RTSR1_TR3_Msk                          /*!< Rising trigger event configuration bit of line 3 */

+#define EXTI_RTSR1_TR4_Pos         (4U)

+#define EXTI_RTSR1_TR4_Msk         (0x1UL << EXTI_RTSR1_TR4_Pos)               /*!< 0x00000010 */

+#define EXTI_RTSR1_TR4             EXTI_RTSR1_TR4_Msk                          /*!< Rising trigger event configuration bit of line 4 */

+#define EXTI_RTSR1_TR5_Pos         (5U)

+#define EXTI_RTSR1_TR5_Msk         (0x1UL << EXTI_RTSR1_TR5_Pos)               /*!< 0x00000020 */

+#define EXTI_RTSR1_TR5             EXTI_RTSR1_TR5_Msk                          /*!< Rising trigger event configuration bit of line 5 */

+#define EXTI_RTSR1_TR6_Pos         (6U)

+#define EXTI_RTSR1_TR6_Msk         (0x1UL << EXTI_RTSR1_TR6_Pos)               /*!< 0x00000040 */

+#define EXTI_RTSR1_TR6             EXTI_RTSR1_TR6_Msk                          /*!< Rising trigger event configuration bit of line 6 */

+#define EXTI_RTSR1_TR7_Pos         (7U)

+#define EXTI_RTSR1_TR7_Msk         (0x1UL << EXTI_RTSR1_TR7_Pos)               /*!< 0x00000080 */

+#define EXTI_RTSR1_TR7             EXTI_RTSR1_TR7_Msk                          /*!< Rising trigger event configuration bit of line 7 */

+#define EXTI_RTSR1_TR8_Pos         (8U)

+#define EXTI_RTSR1_TR8_Msk         (0x1UL << EXTI_RTSR1_TR8_Pos)               /*!< 0x00000100 */

+#define EXTI_RTSR1_TR8             EXTI_RTSR1_TR8_Msk                          /*!< Rising trigger event configuration bit of line 8 */

+#define EXTI_RTSR1_TR9_Pos         (9U)

+#define EXTI_RTSR1_TR9_Msk         (0x1UL << EXTI_RTSR1_TR9_Pos)               /*!< 0x00000200 */

+#define EXTI_RTSR1_TR9             EXTI_RTSR1_TR9_Msk                          /*!< Rising trigger event configuration bit of line 9 */

+#define EXTI_RTSR1_TR10_Pos        (10U)

+#define EXTI_RTSR1_TR10_Msk        (0x1UL << EXTI_RTSR1_TR10_Pos)              /*!< 0x00000400 */

+#define EXTI_RTSR1_TR10            EXTI_RTSR1_TR10_Msk                         /*!< Rising trigger event configuration bit of line 10 */

+#define EXTI_RTSR1_TR11_Pos        (11U)

+#define EXTI_RTSR1_TR11_Msk        (0x1UL << EXTI_RTSR1_TR11_Pos)              /*!< 0x00000800 */

+#define EXTI_RTSR1_TR11            EXTI_RTSR1_TR11_Msk                         /*!< Rising trigger event configuration bit of line 11 */

+#define EXTI_RTSR1_TR12_Pos        (12U)

+#define EXTI_RTSR1_TR12_Msk        (0x1UL << EXTI_RTSR1_TR12_Pos)              /*!< 0x00001000 */

+#define EXTI_RTSR1_TR12            EXTI_RTSR1_TR12_Msk                         /*!< Rising trigger event configuration bit of line 12 */

+#define EXTI_RTSR1_TR13_Pos        (13U)

+#define EXTI_RTSR1_TR13_Msk        (0x1UL << EXTI_RTSR1_TR13_Pos)              /*!< 0x00002000 */

+#define EXTI_RTSR1_TR13            EXTI_RTSR1_TR13_Msk                         /*!< Rising trigger event configuration bit of line 13 */

+#define EXTI_RTSR1_TR14_Pos        (14U)

+#define EXTI_RTSR1_TR14_Msk        (0x1UL << EXTI_RTSR1_TR14_Pos)              /*!< 0x00004000 */

+#define EXTI_RTSR1_TR14            EXTI_RTSR1_TR14_Msk                         /*!< Rising trigger event configuration bit of line 14 */

+#define EXTI_RTSR1_TR15_Pos        (15U)

+#define EXTI_RTSR1_TR15_Msk        (0x1UL << EXTI_RTSR1_TR15_Pos)              /*!< 0x00008000 */

+#define EXTI_RTSR1_TR15            EXTI_RTSR1_TR15_Msk                         /*!< Rising trigger event configuration bit of line 15 */

+#define EXTI_RTSR1_TR16_Pos        (16U)

+#define EXTI_RTSR1_TR16_Msk        (0x1UL << EXTI_RTSR1_TR16_Pos)              /*!< 0x00010000 */

+#define EXTI_RTSR1_TR16            EXTI_RTSR1_TR16_Msk                         /*!< Rising trigger event configuration bit of line 16 */

+#define EXTI_RTSR1_TR17_Pos        (17U)

+#define EXTI_RTSR1_TR17_Msk        (0x1UL << EXTI_RTSR1_TR17_Pos)              /*!< 0x00020000 */

+#define EXTI_RTSR1_TR17            EXTI_RTSR1_TR17_Msk                         /*!< Rising trigger event configuration bit of line 17 */

+#define EXTI_RTSR1_TR18_Pos        (18U)

+#define EXTI_RTSR1_TR18_Msk        (0x1UL << EXTI_RTSR1_TR18_Pos)              /*!< 0x00040000 */

+#define EXTI_RTSR1_TR18            EXTI_RTSR1_TR18_Msk                         /*!< Rising trigger event configuration bit of line 18 */

+#define EXTI_RTSR1_TR19_Pos        (19U)

+#define EXTI_RTSR1_TR19_Msk        (0x1UL << EXTI_RTSR1_TR19_Pos)              /*!< 0x00080000 */

+#define EXTI_RTSR1_TR19            EXTI_RTSR1_TR19_Msk                         /*!< Rising trigger event configuration bit of line 19 */

+#define EXTI_RTSR1_TR20_Pos        (20U)

+#define EXTI_RTSR1_TR20_Msk        (0x1UL << EXTI_RTSR1_TR20_Pos)              /*!< 0x00100000 */

+#define EXTI_RTSR1_TR20            EXTI_RTSR1_TR20_Msk                         /*!< Rising trigger event configuration bit of line 20 */

+#define EXTI_RTSR1_TR21_Pos        (21U)

+#define EXTI_RTSR1_TR21_Msk        (0x1UL << EXTI_RTSR1_TR21_Pos)              /*!< 0x00200000 */

+#define EXTI_RTSR1_TR21            EXTI_RTSR1_TR21_Msk                         /*!< Rising trigger event configuration bit of line 21 */

+

+/******************  Bit definition for EXTI_FTSR1 register  *******************/

+#define EXTI_FTSR1_TR_Pos          (0U)

+#define EXTI_FTSR1_TR_Msk          (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)           /*!< 0x003FFFFF */

+#define EXTI_FTSR1_TR              EXTI_FTSR1_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR1_TR0_Pos         (0U)

+#define EXTI_FTSR1_TR0_Msk         (0x1UL << EXTI_FTSR1_TR0_Pos)               /*!< 0x00000001 */

+#define EXTI_FTSR1_TR0             EXTI_FTSR1_TR0_Msk                          /*!< Falling trigger event configuration bit of line 0 */

+#define EXTI_FTSR1_TR1_Pos         (1U)

+#define EXTI_FTSR1_TR1_Msk         (0x1UL << EXTI_FTSR1_TR1_Pos)               /*!< 0x00000002 */

+#define EXTI_FTSR1_TR1             EXTI_FTSR1_TR1_Msk                          /*!< Falling trigger event configuration bit of line 1 */

+#define EXTI_FTSR1_TR2_Pos         (2U)

+#define EXTI_FTSR1_TR2_Msk         (0x1UL << EXTI_FTSR1_TR2_Pos)               /*!< 0x00000004 */

+#define EXTI_FTSR1_TR2             EXTI_FTSR1_TR2_Msk                          /*!< Falling trigger event configuration bit of line 2 */

+#define EXTI_FTSR1_TR3_Pos         (3U)

+#define EXTI_FTSR1_TR3_Msk         (0x1UL << EXTI_FTSR1_TR3_Pos)               /*!< 0x00000008 */

+#define EXTI_FTSR1_TR3             EXTI_FTSR1_TR3_Msk                          /*!< Falling trigger event configuration bit of line 3 */

+#define EXTI_FTSR1_TR4_Pos         (4U)

+#define EXTI_FTSR1_TR4_Msk         (0x1UL << EXTI_FTSR1_TR4_Pos)               /*!< 0x00000010 */

+#define EXTI_FTSR1_TR4             EXTI_FTSR1_TR4_Msk                          /*!< Falling trigger event configuration bit of line 4 */

+#define EXTI_FTSR1_TR5_Pos         (5U)

+#define EXTI_FTSR1_TR5_Msk         (0x1UL << EXTI_FTSR1_TR5_Pos)               /*!< 0x00000020 */

+#define EXTI_FTSR1_TR5             EXTI_FTSR1_TR5_Msk                          /*!< Falling trigger event configuration bit of line 5 */

+#define EXTI_FTSR1_TR6_Pos         (6U)

+#define EXTI_FTSR1_TR6_Msk         (0x1UL << EXTI_FTSR1_TR6_Pos)               /*!< 0x00000040 */

+#define EXTI_FTSR1_TR6             EXTI_FTSR1_TR6_Msk                          /*!< Falling trigger event configuration bit of line 6 */

+#define EXTI_FTSR1_TR7_Pos         (7U)

+#define EXTI_FTSR1_TR7_Msk         (0x1UL << EXTI_FTSR1_TR7_Pos)               /*!< 0x00000080 */

+#define EXTI_FTSR1_TR7             EXTI_FTSR1_TR7_Msk                          /*!< Falling trigger event configuration bit of line 7 */

+#define EXTI_FTSR1_TR8_Pos         (8U)

+#define EXTI_FTSR1_TR8_Msk         (0x1UL << EXTI_FTSR1_TR8_Pos)               /*!< 0x00000100 */

+#define EXTI_FTSR1_TR8             EXTI_FTSR1_TR8_Msk                          /*!< Falling trigger event configuration bit of line 8 */

+#define EXTI_FTSR1_TR9_Pos         (9U)

+#define EXTI_FTSR1_TR9_Msk         (0x1UL << EXTI_FTSR1_TR9_Pos)               /*!< 0x00000200 */

+#define EXTI_FTSR1_TR9             EXTI_FTSR1_TR9_Msk                          /*!< Falling trigger event configuration bit of line 9 */

+#define EXTI_FTSR1_TR10_Pos        (10U)

+#define EXTI_FTSR1_TR10_Msk        (0x1UL << EXTI_FTSR1_TR10_Pos)              /*!< 0x00000400 */

+#define EXTI_FTSR1_TR10            EXTI_FTSR1_TR10_Msk                         /*!< Falling trigger event configuration bit of line 10 */

+#define EXTI_FTSR1_TR11_Pos        (11U)

+#define EXTI_FTSR1_TR11_Msk        (0x1UL << EXTI_FTSR1_TR11_Pos)              /*!< 0x00000800 */

+#define EXTI_FTSR1_TR11            EXTI_FTSR1_TR11_Msk                         /*!< Falling trigger event configuration bit of line 11 */

+#define EXTI_FTSR1_TR12_Pos        (12U)

+#define EXTI_FTSR1_TR12_Msk        (0x1UL << EXTI_FTSR1_TR12_Pos)              /*!< 0x00001000 */

+#define EXTI_FTSR1_TR12            EXTI_FTSR1_TR12_Msk                         /*!< Falling trigger event configuration bit of line 12 */

+#define EXTI_FTSR1_TR13_Pos        (13U)

+#define EXTI_FTSR1_TR13_Msk        (0x1UL << EXTI_FTSR1_TR13_Pos)              /*!< 0x00002000 */

+#define EXTI_FTSR1_TR13            EXTI_FTSR1_TR13_Msk                         /*!< Falling trigger event configuration bit of line 13 */

+#define EXTI_FTSR1_TR14_Pos        (14U)

+#define EXTI_FTSR1_TR14_Msk        (0x1UL << EXTI_FTSR1_TR14_Pos)              /*!< 0x00004000 */

+#define EXTI_FTSR1_TR14            EXTI_FTSR1_TR14_Msk                         /*!< Falling trigger event configuration bit of line 14 */

+#define EXTI_FTSR1_TR15_Pos        (15U)

+#define EXTI_FTSR1_TR15_Msk        (0x1UL << EXTI_FTSR1_TR15_Pos)              /*!< 0x00008000 */

+#define EXTI_FTSR1_TR15            EXTI_FTSR1_TR15_Msk                         /*!< Falling trigger event configuration bit of line 15 */

+#define EXTI_FTSR1_TR16_Pos        (16U)

+#define EXTI_FTSR1_TR16_Msk        (0x1UL << EXTI_FTSR1_TR16_Pos)              /*!< 0x00010000 */

+#define EXTI_FTSR1_TR16            EXTI_FTSR1_TR16_Msk                         /*!< Falling trigger event configuration bit of line 16 */

+#define EXTI_FTSR1_TR17_Pos        (17U)

+#define EXTI_FTSR1_TR17_Msk        (0x1UL << EXTI_FTSR1_TR17_Pos)              /*!< 0x00020000 */

+#define EXTI_FTSR1_TR17            EXTI_FTSR1_TR17_Msk                         /*!< Falling trigger event configuration bit of line 17 */

+#define EXTI_FTSR1_TR18_Pos        (18U)

+#define EXTI_FTSR1_TR18_Msk        (0x1UL << EXTI_FTSR1_TR18_Pos)              /*!< 0x00040000 */

+#define EXTI_FTSR1_TR18            EXTI_FTSR1_TR18_Msk                         /*!< Falling trigger event configuration bit of line 18 */

+#define EXTI_FTSR1_TR19_Pos        (19U)

+#define EXTI_FTSR1_TR19_Msk        (0x1UL << EXTI_FTSR1_TR19_Pos)              /*!< 0x00080000 */

+#define EXTI_FTSR1_TR19            EXTI_FTSR1_TR19_Msk                         /*!< Falling trigger event configuration bit of line 19 */

+#define EXTI_FTSR1_TR20_Pos        (20U)

+#define EXTI_FTSR1_TR20_Msk        (0x1UL << EXTI_FTSR1_TR20_Pos)              /*!< 0x00100000 */

+#define EXTI_FTSR1_TR20            EXTI_FTSR1_TR20_Msk                         /*!< Falling trigger event configuration bit of line 20 */

+#define EXTI_FTSR1_TR21_Pos        (21U)

+#define EXTI_FTSR1_TR21_Msk        (0x1UL << EXTI_FTSR1_TR21_Pos)              /*!< 0x00200000 */

+#define EXTI_FTSR1_TR21            EXTI_FTSR1_TR21_Msk                         /*!< Falling trigger event configuration bit of line 21 */

+

+/******************  Bit definition for EXTI_SWIER1 register  ******************/

+#define EXTI_SWIER1_SWIER0_Pos     (0U)

+#define EXTI_SWIER1_SWIER0_Msk     (0x1UL << EXTI_SWIER1_SWIER0_Pos)           /*!< 0x00000001 */

+#define EXTI_SWIER1_SWIER0         EXTI_SWIER1_SWIER0_Msk                      /*!< Software Interrupt on line 0 */

+#define EXTI_SWIER1_SWIER1_Pos     (1U)

+#define EXTI_SWIER1_SWIER1_Msk     (0x1UL << EXTI_SWIER1_SWIER1_Pos)           /*!< 0x00000002 */

+#define EXTI_SWIER1_SWIER1         EXTI_SWIER1_SWIER1_Msk                      /*!< Software Interrupt on line 1 */

+#define EXTI_SWIER1_SWIER2_Pos     (2U)

+#define EXTI_SWIER1_SWIER2_Msk     (0x1UL << EXTI_SWIER1_SWIER2_Pos)           /*!< 0x00000004 */

+#define EXTI_SWIER1_SWIER2         EXTI_SWIER1_SWIER2_Msk                      /*!< Software Interrupt on line 2 */

+#define EXTI_SWIER1_SWIER3_Pos     (3U)

+#define EXTI_SWIER1_SWIER3_Msk     (0x1UL << EXTI_SWIER1_SWIER3_Pos)           /*!< 0x00000008 */

+#define EXTI_SWIER1_SWIER3         EXTI_SWIER1_SWIER3_Msk                      /*!< Software Interrupt on line 3 */

+#define EXTI_SWIER1_SWIER4_Pos     (4U)

+#define EXTI_SWIER1_SWIER4_Msk     (0x1UL << EXTI_SWIER1_SWIER4_Pos)           /*!< 0x00000010 */

+#define EXTI_SWIER1_SWIER4         EXTI_SWIER1_SWIER4_Msk                      /*!< Software Interrupt on line 4 */

+#define EXTI_SWIER1_SWIER5_Pos     (5U)

+#define EXTI_SWIER1_SWIER5_Msk     (0x1UL << EXTI_SWIER1_SWIER5_Pos)           /*!< 0x00000020 */

+#define EXTI_SWIER1_SWIER5         EXTI_SWIER1_SWIER5_Msk                      /*!< Software Interrupt on line 5 */

+#define EXTI_SWIER1_SWIER6_Pos     (6U)

+#define EXTI_SWIER1_SWIER6_Msk     (0x1UL << EXTI_SWIER1_SWIER6_Pos)           /*!< 0x00000040 */

+#define EXTI_SWIER1_SWIER6         EXTI_SWIER1_SWIER6_Msk                      /*!< Software Interrupt on line 6 */

+#define EXTI_SWIER1_SWIER7_Pos     (7U)

+#define EXTI_SWIER1_SWIER7_Msk     (0x1UL << EXTI_SWIER1_SWIER7_Pos)           /*!< 0x00000080 */

+#define EXTI_SWIER1_SWIER7         EXTI_SWIER1_SWIER7_Msk                      /*!< Software Interrupt on line 7 */

+#define EXTI_SWIER1_SWIER8_Pos     (8U)

+#define EXTI_SWIER1_SWIER8_Msk     (0x1UL << EXTI_SWIER1_SWIER8_Pos)           /*!< 0x00000100 */

+#define EXTI_SWIER1_SWIER8         EXTI_SWIER1_SWIER8_Msk                      /*!< Software Interrupt on line 8 */

+#define EXTI_SWIER1_SWIER9_Pos     (9U)

+#define EXTI_SWIER1_SWIER9_Msk     (0x1UL << EXTI_SWIER1_SWIER9_Pos)           /*!< 0x00000200 */

+#define EXTI_SWIER1_SWIER9         EXTI_SWIER1_SWIER9_Msk                      /*!< Software Interrupt on line 9 */

+#define EXTI_SWIER1_SWIER10_Pos    (10U)

+#define EXTI_SWIER1_SWIER10_Msk    (0x1UL << EXTI_SWIER1_SWIER10_Pos)          /*!< 0x00000400 */

+#define EXTI_SWIER1_SWIER10        EXTI_SWIER1_SWIER10_Msk                     /*!< Software Interrupt on line 10 */

+#define EXTI_SWIER1_SWIER11_Pos    (11U)

+#define EXTI_SWIER1_SWIER11_Msk    (0x1UL << EXTI_SWIER1_SWIER11_Pos)          /*!< 0x00000800 */

+#define EXTI_SWIER1_SWIER11        EXTI_SWIER1_SWIER11_Msk                     /*!< Software Interrupt on line 11 */

+#define EXTI_SWIER1_SWIER12_Pos    (12U)

+#define EXTI_SWIER1_SWIER12_Msk    (0x1UL << EXTI_SWIER1_SWIER12_Pos)          /*!< 0x00001000 */

+#define EXTI_SWIER1_SWIER12        EXTI_SWIER1_SWIER12_Msk                     /*!< Software Interrupt on line 12 */

+#define EXTI_SWIER1_SWIER13_Pos    (13U)

+#define EXTI_SWIER1_SWIER13_Msk    (0x1UL << EXTI_SWIER1_SWIER13_Pos)          /*!< 0x00002000 */

+#define EXTI_SWIER1_SWIER13        EXTI_SWIER1_SWIER13_Msk                     /*!< Software Interrupt on line 13 */

+#define EXTI_SWIER1_SWIER14_Pos    (14U)

+#define EXTI_SWIER1_SWIER14_Msk    (0x1UL << EXTI_SWIER1_SWIER14_Pos)          /*!< 0x00004000 */

+#define EXTI_SWIER1_SWIER14        EXTI_SWIER1_SWIER14_Msk                     /*!< Software Interrupt on line 14 */

+#define EXTI_SWIER1_SWIER15_Pos    (15U)

+#define EXTI_SWIER1_SWIER15_Msk    (0x1UL << EXTI_SWIER1_SWIER15_Pos)          /*!< 0x00008000 */

+#define EXTI_SWIER1_SWIER15        EXTI_SWIER1_SWIER15_Msk                     /*!< Software Interrupt on line 15 */

+#define EXTI_SWIER1_SWIER16_Pos    (16U)

+#define EXTI_SWIER1_SWIER16_Msk    (0x1UL << EXTI_SWIER1_SWIER16_Pos)          /*!< 0x00010000 */

+#define EXTI_SWIER1_SWIER16        EXTI_SWIER1_SWIER16_Msk                     /*!< Software Interrupt on line 16 */

+#define EXTI_SWIER1_SWIER17_Pos    (17U)

+#define EXTI_SWIER1_SWIER17_Msk    (0x1UL << EXTI_SWIER1_SWIER17_Pos)          /*!< 0x00020000 */

+#define EXTI_SWIER1_SWIER17        EXTI_SWIER1_SWIER17_Msk                     /*!< Software Interrupt on line 17 */

+#define EXTI_SWIER1_SWIER18_Pos    (18U)

+#define EXTI_SWIER1_SWIER18_Msk    (0x1UL << EXTI_SWIER1_SWIER18_Pos)          /*!< 0x00040000 */

+#define EXTI_SWIER1_SWIER18        EXTI_SWIER1_SWIER18_Msk                     /*!< Software Interrupt on line 18 */

+#define EXTI_SWIER1_SWIER19_Pos    (19U)

+#define EXTI_SWIER1_SWIER19_Msk    (0x1UL << EXTI_SWIER1_SWIER19_Pos)          /*!< 0x00080000 */

+#define EXTI_SWIER1_SWIER19        EXTI_SWIER1_SWIER19_Msk                     /*!< Software Interrupt on line 19 */

+#define EXTI_SWIER1_SWIER20_Pos    (20U)

+#define EXTI_SWIER1_SWIER20_Msk    (0x1UL << EXTI_SWIER1_SWIER20_Pos)          /*!< 0x00100000 */

+#define EXTI_SWIER1_SWIER20        EXTI_SWIER1_SWIER20_Msk                     /*!< Software Interrupt on line 20 */

+#define EXTI_SWIER1_SWIER21_Pos    (21U)

+#define EXTI_SWIER1_SWIER21_Msk    (0x1UL << EXTI_SWIER1_SWIER21_Pos)          /*!< 0x00200000 */

+#define EXTI_SWIER1_SWIER21        EXTI_SWIER1_SWIER21_Msk                     /*!< Software Interrupt on line 21 */

+

+/******************  Bit definition for EXTI_D3PMR1 register  ******************/

+#define EXTI_D3PMR1_MR0_Pos        (0U)

+#define EXTI_D3PMR1_MR0_Msk        (0x1UL << EXTI_D3PMR1_MR0_Pos)              /*!< 0x00000001 */

+#define EXTI_D3PMR1_MR0            EXTI_D3PMR1_MR0_Msk                         /*!< Pending Mask Event for line 0  */

+#define EXTI_D3PMR1_MR1_Pos        (1U)

+#define EXTI_D3PMR1_MR1_Msk        (0x1UL << EXTI_D3PMR1_MR1_Pos)              /*!< 0x00000002 */

+#define EXTI_D3PMR1_MR1            EXTI_D3PMR1_MR1_Msk                         /*!< Pending Mask Event for line 1  */

+#define EXTI_D3PMR1_MR2_Pos        (2U)

+#define EXTI_D3PMR1_MR2_Msk        (0x1UL << EXTI_D3PMR1_MR2_Pos)              /*!< 0x00000004 */

+#define EXTI_D3PMR1_MR2            EXTI_D3PMR1_MR2_Msk                         /*!< Pending Mask Event for line 2  */

+#define EXTI_D3PMR1_MR3_Pos        (3U)

+#define EXTI_D3PMR1_MR3_Msk        (0x1UL << EXTI_D3PMR1_MR3_Pos)              /*!< 0x00000008 */

+#define EXTI_D3PMR1_MR3            EXTI_D3PMR1_MR3_Msk                         /*!< Pending Mask Event for line 3  */

+#define EXTI_D3PMR1_MR4_Pos        (4U)

+#define EXTI_D3PMR1_MR4_Msk        (0x1UL << EXTI_D3PMR1_MR4_Pos)              /*!< 0x00000010 */

+#define EXTI_D3PMR1_MR4            EXTI_D3PMR1_MR4_Msk                         /*!< Pending Mask Event for line 4  */

+#define EXTI_D3PMR1_MR5_Pos        (5U)

+#define EXTI_D3PMR1_MR5_Msk        (0x1UL << EXTI_D3PMR1_MR5_Pos)              /*!< 0x00000020 */

+#define EXTI_D3PMR1_MR5            EXTI_D3PMR1_MR5_Msk                         /*!< Pending Mask Event for line 5  */

+#define EXTI_D3PMR1_MR6_Pos        (6U)

+#define EXTI_D3PMR1_MR6_Msk        (0x1UL << EXTI_D3PMR1_MR6_Pos)              /*!< 0x00000040 */

+#define EXTI_D3PMR1_MR6            EXTI_D3PMR1_MR6_Msk                         /*!< Pending Mask Event for line 6  */

+#define EXTI_D3PMR1_MR7_Pos        (7U)

+#define EXTI_D3PMR1_MR7_Msk        (0x1UL << EXTI_D3PMR1_MR7_Pos)              /*!< 0x00000080 */

+#define EXTI_D3PMR1_MR7            EXTI_D3PMR1_MR7_Msk                         /*!< Pending Mask Event for line 7  */

+#define EXTI_D3PMR1_MR8_Pos        (8U)

+#define EXTI_D3PMR1_MR8_Msk        (0x1UL << EXTI_D3PMR1_MR8_Pos)              /*!< 0x00000100 */

+#define EXTI_D3PMR1_MR8            EXTI_D3PMR1_MR8_Msk                         /*!< Pending Mask Event for line 8  */

+#define EXTI_D3PMR1_MR9_Pos        (9U)

+#define EXTI_D3PMR1_MR9_Msk        (0x1UL << EXTI_D3PMR1_MR9_Pos)              /*!< 0x00000200 */

+#define EXTI_D3PMR1_MR9            EXTI_D3PMR1_MR9_Msk                         /*!< Pending Mask Event for line 9  */

+#define EXTI_D3PMR1_MR10_Pos       (10U)

+#define EXTI_D3PMR1_MR10_Msk       (0x1UL << EXTI_D3PMR1_MR10_Pos)             /*!< 0x00000400 */

+#define EXTI_D3PMR1_MR10           EXTI_D3PMR1_MR10_Msk                        /*!< Pending Mask Event for line 10 */

+#define EXTI_D3PMR1_MR11_Pos       (11U)

+#define EXTI_D3PMR1_MR11_Msk       (0x1UL << EXTI_D3PMR1_MR11_Pos)             /*!< 0x00000800 */

+#define EXTI_D3PMR1_MR11           EXTI_D3PMR1_MR11_Msk                        /*!< Pending Mask Event for line 11 */

+#define EXTI_D3PMR1_MR12_Pos       (12U)

+#define EXTI_D3PMR1_MR12_Msk       (0x1UL << EXTI_D3PMR1_MR12_Pos)             /*!< 0x00001000 */

+#define EXTI_D3PMR1_MR12           EXTI_D3PMR1_MR12_Msk                        /*!< Pending Mask Event for line 12 */

+#define EXTI_D3PMR1_MR13_Pos       (13U)

+#define EXTI_D3PMR1_MR13_Msk       (0x1UL << EXTI_D3PMR1_MR13_Pos)             /*!< 0x00002000 */

+#define EXTI_D3PMR1_MR13           EXTI_D3PMR1_MR13_Msk                        /*!< Pending Mask Event for line 13 */

+#define EXTI_D3PMR1_MR14_Pos       (14U)

+#define EXTI_D3PMR1_MR14_Msk       (0x1UL << EXTI_D3PMR1_MR14_Pos)             /*!< 0x00004000 */

+#define EXTI_D3PMR1_MR14           EXTI_D3PMR1_MR14_Msk                        /*!< Pending Mask Event for line 14 */

+#define EXTI_D3PMR1_MR15_Pos       (15U)

+#define EXTI_D3PMR1_MR15_Msk       (0x1UL << EXTI_D3PMR1_MR15_Pos)             /*!< 0x00008000 */

+#define EXTI_D3PMR1_MR15           EXTI_D3PMR1_MR15_Msk                        /*!< Pending Mask Event for line 15 */

+#define EXTI_D3PMR1_MR19_Pos       (19U)

+#define EXTI_D3PMR1_MR19_Msk       (0x1UL << EXTI_D3PMR1_MR19_Pos)             /*!< 0x00080000 */

+#define EXTI_D3PMR1_MR19           EXTI_D3PMR1_MR19_Msk                        /*!< Pending Mask Event for line 19 */

+#define EXTI_D3PMR1_MR20_Pos       (20U)

+#define EXTI_D3PMR1_MR20_Msk       (0x1UL << EXTI_D3PMR1_MR20_Pos)             /*!< 0x00100000 */

+#define EXTI_D3PMR1_MR20           EXTI_D3PMR1_MR20_Msk                        /*!< Pending Mask Event for line 20 */

+#define EXTI_D3PMR1_MR21_Pos       (21U)

+#define EXTI_D3PMR1_MR21_Msk       (0x1UL << EXTI_D3PMR1_MR21_Pos)             /*!< 0x00200000 */

+#define EXTI_D3PMR1_MR21           EXTI_D3PMR1_MR21_Msk                        /*!< Pending Mask Event for line 21 */

+#define EXTI_D3PMR1_MR25_Pos       (24U)

+#define EXTI_D3PMR1_MR25_Msk       (0x1UL << EXTI_D3PMR1_MR25_Pos)             /*!< 0x01000000 */

+#define EXTI_D3PMR1_MR25           EXTI_D3PMR1_MR25_Msk                        /*!< Pending Mask Event for line 25 */

+

+/*******************  Bit definition for EXTI_D3PCR1L register  ****************/

+#define EXTI_D3PCR1L_PCS0_Pos       (0U)

+#define EXTI_D3PCR1L_PCS0_Msk       (0x3UL << EXTI_D3PCR1L_PCS0_Pos)           /*!< 0x00000003 */

+#define EXTI_D3PCR1L_PCS0           EXTI_D3PCR1L_PCS0_Msk                      /*!< D3 Pending request clear input signal selection on line 0 */

+#define EXTI_D3PCR1L_PCS1_Pos       (2U)

+#define EXTI_D3PCR1L_PCS1_Msk       (0x3UL << EXTI_D3PCR1L_PCS1_Pos)           /*!< 0x000000C0 */

+#define EXTI_D3PCR1L_PCS1           EXTI_D3PCR1L_PCS1_Msk                      /*!< D3 Pending request clear input signal selection on line 1 */

+#define EXTI_D3PCR1L_PCS2_Pos       (4U)

+#define EXTI_D3PCR1L_PCS2_Msk       (0x3UL << EXTI_D3PCR1L_PCS2_Pos)           /*!< 0x00000030 */

+#define EXTI_D3PCR1L_PCS2           EXTI_D3PCR1L_PCS2_Msk                      /*!< D3 Pending request clear input signal selection on line 2 */

+#define EXTI_D3PCR1L_PCS3_Pos       (6U)

+#define EXTI_D3PCR1L_PCS3_Msk       (0x3UL << EXTI_D3PCR1L_PCS3_Pos)           /*!< 0x000000C0 */

+#define EXTI_D3PCR1L_PCS3           EXTI_D3PCR1L_PCS3_Msk                      /*!< D3 Pending request clear input signal selection on line 3 */

+#define EXTI_D3PCR1L_PCS4_Pos       (8U)

+#define EXTI_D3PCR1L_PCS4_Msk       (0x3UL << EXTI_D3PCR1L_PCS4_Pos)           /*!< 0x00000300 */

+#define EXTI_D3PCR1L_PCS4           EXTI_D3PCR1L_PCS4_Msk                      /*!< D3 Pending request clear input signal selection on line 4 */

+#define EXTI_D3PCR1L_PCS5_Pos       (10U)

+#define EXTI_D3PCR1L_PCS5_Msk       (0x3UL << EXTI_D3PCR1L_PCS5_Pos)           /*!< 0x00000C00 */

+#define EXTI_D3PCR1L_PCS5           EXTI_D3PCR1L_PCS5_Msk                      /*!< D3 Pending request clear input signal selection on line 5 */

+#define EXTI_D3PCR1L_PCS6_Pos       (12U)

+#define EXTI_D3PCR1L_PCS6_Msk       (0x3UL << EXTI_D3PCR1L_PCS6_Pos)           /*!< 0x00003000 */

+#define EXTI_D3PCR1L_PCS6           EXTI_D3PCR1L_PCS6_Msk                      /*!< D3 Pending request clear input signal selection on line 6 */

+#define EXTI_D3PCR1L_PCS7_Pos       (14U)

+#define EXTI_D3PCR1L_PCS7_Msk       (0x3UL << EXTI_D3PCR1L_PCS7_Pos)           /*!< 0x0000C000 */

+#define EXTI_D3PCR1L_PCS7           EXTI_D3PCR1L_PCS7_Msk                      /*!< D3 Pending request clear input signal selection on line 7 */

+#define EXTI_D3PCR1L_PCS8_Pos       (16U)

+#define EXTI_D3PCR1L_PCS8_Msk       (0x3UL << EXTI_D3PCR1L_PCS8_Pos)           /*!< 0x00030000 */

+#define EXTI_D3PCR1L_PCS8           EXTI_D3PCR1L_PCS8_Msk                      /*!< D3 Pending request clear input signal selection on line 8 */

+#define EXTI_D3PCR1L_PCS9_Pos       (18U)

+#define EXTI_D3PCR1L_PCS9_Msk       (0x3UL << EXTI_D3PCR1L_PCS9_Pos)           /*!< 0x000C0000 */

+#define EXTI_D3PCR1L_PCS9           EXTI_D3PCR1L_PCS9_Msk                      /*!< D3 Pending request clear input signal selection on line 9 */

+#define EXTI_D3PCR1L_PCS10_Pos      (20U)

+#define EXTI_D3PCR1L_PCS10_Msk      (0x3UL << EXTI_D3PCR1L_PCS10_Pos)          /*!< 0x00300000 */

+#define EXTI_D3PCR1L_PCS10          EXTI_D3PCR1L_PCS10_Msk                     /*!< D3 Pending request clear input signal selection on line 10*/

+#define EXTI_D3PCR1L_PCS11_Pos      (22U)

+#define EXTI_D3PCR1L_PCS11_Msk      (0x3UL << EXTI_D3PCR1L_PCS11_Pos)          /*!< 0x00C00000 */

+#define EXTI_D3PCR1L_PCS11          EXTI_D3PCR1L_PCS11_Msk                     /*!< D3 Pending request clear input signal selection on line 11*/

+#define EXTI_D3PCR1L_PCS12_Pos      (24U)

+#define EXTI_D3PCR1L_PCS12_Msk      (0x3UL << EXTI_D3PCR1L_PCS12_Pos)          /*!< 0x03000000 */

+#define EXTI_D3PCR1L_PCS12          EXTI_D3PCR1L_PCS12_Msk                     /*!< D3 Pending request clear input signal selection on line 12*/

+#define EXTI_D3PCR1L_PCS13_Pos      (26U)

+#define EXTI_D3PCR1L_PCS13_Msk      (0x3UL << EXTI_D3PCR1L_PCS13_Pos)          /*!< 0x0C000000 */

+#define EXTI_D3PCR1L_PCS13          EXTI_D3PCR1L_PCS13_Msk                     /*!< D3 Pending request clear input signal selection on line 13*/

+#define EXTI_D3PCR1L_PCS14_Pos      (28U)

+#define EXTI_D3PCR1L_PCS14_Msk      (0x3UL << EXTI_D3PCR1L_PCS14_Pos)          /*!< 0x30000000 */

+#define EXTI_D3PCR1L_PCS14          EXTI_D3PCR1L_PCS14_Msk                     /*!< D3 Pending request clear input signal selection on line 14*/

+#define EXTI_D3PCR1L_PCS15_Pos      (30U)

+#define EXTI_D3PCR1L_PCS15_Msk      (0x3UL << EXTI_D3PCR1L_PCS15_Pos)          /*!< 0xC0000000 */

+#define EXTI_D3PCR1L_PCS15          EXTI_D3PCR1L_PCS15_Msk                     /*!< D3 Pending request clear input signal selection on line 15*/

+

+/*******************  Bit definition for EXTI_D3PCR1H register  ****************/

+#define EXTI_D3PCR1H_PCS19_Pos       (6U)

+#define EXTI_D3PCR1H_PCS19_Msk       (0x3UL << EXTI_D3PCR1H_PCS19_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR1H_PCS19           EXTI_D3PCR1H_PCS19_Msk                    /*!< D3 Pending request clear input signal selection on line 19 */

+#define EXTI_D3PCR1H_PCS20_Pos       (8U)

+#define EXTI_D3PCR1H_PCS20_Msk       (0x3UL << EXTI_D3PCR1H_PCS20_Pos)         /*!< 0x00000300 */

+#define EXTI_D3PCR1H_PCS20           EXTI_D3PCR1H_PCS20_Msk                    /*!< D3 Pending request clear input signal selection on line 20 */

+#define EXTI_D3PCR1H_PCS21_Pos       (10U)

+#define EXTI_D3PCR1H_PCS21_Msk       (0x3UL << EXTI_D3PCR1H_PCS21_Pos)         /*!< 0x00000C00 */

+#define EXTI_D3PCR1H_PCS21           EXTI_D3PCR1H_PCS21_Msk                    /*!< D3 Pending request clear input signal selection on line 21 */

+#define EXTI_D3PCR1H_PCS25_Pos       (18U)

+#define EXTI_D3PCR1H_PCS25_Msk       (0x3UL << EXTI_D3PCR1H_PCS25_Pos)         /*!< 0x000C0000 */

+#define EXTI_D3PCR1H_PCS25           EXTI_D3PCR1H_PCS25_Msk                    /*!< D3 Pending request clear input signal selection on line 25 */

+

+/******************  Bit definition for EXTI_RTSR2 register  *******************/

+#define EXTI_RTSR2_TR_Pos          (17U)

+#define EXTI_RTSR2_TR_Msk          (0x5UL << EXTI_RTSR2_TR_Pos)                /*!< 0x000A0000 */

+#define EXTI_RTSR2_TR              EXTI_RTSR2_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR2_TR49_Pos        (17U)

+#define EXTI_RTSR2_TR49_Msk        (0x1UL << EXTI_RTSR2_TR49_Pos)              /*!< 0x00020000 */

+#define EXTI_RTSR2_TR49            EXTI_RTSR2_TR49_Msk                         /*!< Rising trigger event configuration bit of line 49 */

+#define EXTI_RTSR2_TR51_Pos        (19U)

+#define EXTI_RTSR2_TR51_Msk        (0x1UL << EXTI_RTSR2_TR51_Pos)              /*!< 0x00080000 */

+#define EXTI_RTSR2_TR51            EXTI_RTSR2_TR51_Msk                         /*!< Rising trigger event configuration bit of line 51 */

+

+/******************  Bit definition for EXTI_FTSR2 register  *******************/

+#define EXTI_FTSR2_TR_Pos          (17U)

+#define EXTI_FTSR2_TR_Msk          (0x5UL << EXTI_FTSR2_TR_Pos)                /*!< 0x000A0000 */

+#define EXTI_FTSR2_TR              EXTI_FTSR2_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR2_TR49_Pos        (17U)

+#define EXTI_FTSR2_TR49_Msk        (0x1UL << EXTI_FTSR2_TR49_Pos)              /*!< 0x00020000 */

+#define EXTI_FTSR2_TR49            EXTI_FTSR2_TR49_Msk                         /*!< Falling trigger event configuration bit of line 49 */

+#define EXTI_FTSR2_TR51_Pos        (19U)

+#define EXTI_FTSR2_TR51_Msk        (0x1UL << EXTI_FTSR2_TR51_Pos)              /*!< 0x00080000 */

+#define EXTI_FTSR2_TR51            EXTI_FTSR2_TR51_Msk                         /*!< Falling trigger event configuration bit of line 51 */

+

+/******************  Bit definition for EXTI_SWIER2 register  ******************/

+#define EXTI_SWIER2_SWIER49_Pos    (17U)

+#define EXTI_SWIER2_SWIER49_Msk    (0x1UL << EXTI_SWIER2_SWIER49_Pos)          /*!< 0x00020000 */

+#define EXTI_SWIER2_SWIER49        EXTI_SWIER2_SWIER49_Msk                     /*!< Software Interrupt on line 49 */

+#define EXTI_SWIER2_SWIER51_Pos    (19U)

+#define EXTI_SWIER2_SWIER51_Msk    (0x1UL << EXTI_SWIER2_SWIER51_Pos)          /*!< 0x00080000 */

+#define EXTI_SWIER2_SWIER51        EXTI_SWIER2_SWIER51_Msk                     /*!< Software Interrupt on line 51 */

+

+/******************  Bit definition for EXTI_D3PMR2 register  ******************/

+#define EXTI_D3PMR2_MR34_Pos       (2U)

+#define EXTI_D3PMR2_MR34_Msk       (0x1UL << EXTI_D3PMR2_MR34_Pos)             /*!< 0x00000004 */

+#define EXTI_D3PMR2_MR34           EXTI_D3PMR2_MR34_Msk                        /*!< Pending Mask Event for line 34  */

+#define EXTI_D3PMR2_MR35_Pos       (3U)

+#define EXTI_D3PMR2_MR35_Msk       (0x1UL << EXTI_D3PMR2_MR35_Pos)             /*!< 0x00000008 */

+#define EXTI_D3PMR2_MR35           EXTI_D3PMR2_MR35_Msk                        /*!< Pending Mask Event for line 35  */

+#define EXTI_D3PMR2_MR41_Pos       (9U)

+#define EXTI_D3PMR2_MR41_Msk       (0x1UL << EXTI_D3PMR2_MR41_Pos)             /*!< 0x00000200 */

+#define EXTI_D3PMR2_MR41           EXTI_D3PMR2_MR41_Msk                        /*!< Pending Mask Event for line 41  */

+#define EXTI_D3PMR2_MR48_Pos       (16U)

+#define EXTI_D3PMR2_MR48_Msk       (0x1UL << EXTI_D3PMR2_MR48_Pos)             /*!< 0x00010000 */

+#define EXTI_D3PMR2_MR48           EXTI_D3PMR2_MR48_Msk                        /*!< Pending Mask Event for line 48  */

+#define EXTI_D3PMR2_MR49_Pos       (17U)

+#define EXTI_D3PMR2_MR49_Msk       (0x1UL << EXTI_D3PMR2_MR49_Pos)             /*!< 0x00020000 */

+#define EXTI_D3PMR2_MR49           EXTI_D3PMR2_MR49_Msk                        /*!< Pending Mask Event for line 49  */

+#define EXTI_D3PMR2_MR50_Pos       (18U)

+#define EXTI_D3PMR2_MR50_Msk       (0x1UL << EXTI_D3PMR2_MR50_Pos)             /*!< 0x00040000 */

+#define EXTI_D3PMR2_MR50           EXTI_D3PMR2_MR50_Msk                        /*!< Pending Mask Event for line 50  */

+#define EXTI_D3PMR2_MR51_Pos       (19U)

+#define EXTI_D3PMR2_MR51_Msk       (0x1UL << EXTI_D3PMR2_MR51_Pos)             /*!< 0x00080000 */

+#define EXTI_D3PMR2_MR51           EXTI_D3PMR2_MR51_Msk                        /*!< Pending Mask Event for line 51  */

+#define EXTI_D3PMR2_MR52_Pos       (20U)

+#define EXTI_D3PMR2_MR52_Msk       (0x1UL << EXTI_D3PMR2_MR52_Pos)             /*!< 0x00100000 */

+#define EXTI_D3PMR2_MR52           EXTI_D3PMR2_MR52_Msk                        /*!< Pending Mask Event for line 52  */

+#define EXTI_D3PMR2_MR53_Pos       (21U)

+#define EXTI_D3PMR2_MR53_Msk       (0x1UL << EXTI_D3PMR2_MR53_Pos)             /*!< 0x00200000 */

+#define EXTI_D3PMR2_MR53           EXTI_D3PMR2_MR53_Msk                        /*!< Pending Mask Event for line 53  */

+/*******************  Bit definition for EXTI_D3PCR2L register  ****************/

+#define EXTI_D3PCR2L_PCS34_Pos       (4U)

+#define EXTI_D3PCR2L_PCS34_Msk       (0x3UL << EXTI_D3PCR2L_PCS34_Pos)         /*!< 0x00000030 */

+#define EXTI_D3PCR2L_PCS34           EXTI_D3PCR2L_PCS34_Msk                    /*!< D3 Pending request clear input signal selection on line 34 */

+#define EXTI_D3PCR2L_PCS35_Pos       (6U)

+#define EXTI_D3PCR2L_PCS35_Msk       (0x3UL << EXTI_D3PCR2L_PCS35_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR2L_PCS35           EXTI_D3PCR2L_PCS35_Msk                    /*!< D3 Pending request clear input signal selection on line 35 */

+#define EXTI_D3PCR2L_PCS41_Pos       (18U)

+#define EXTI_D3PCR2L_PCS41_Msk       (0x3UL << EXTI_D3PCR2L_PCS41_Pos)         /*!< 0x000C0000 */

+#define EXTI_D3PCR2L_PCS41           EXTI_D3PCR2L_PCS41_Msk                    /*!< D3 Pending request clear input signal selection on line 41 */

+

+

+/*******************  Bit definition for EXTI_D3PCR2H register  ****************/

+#define EXTI_D3PCR2H_PCS48_Pos       (0U)

+#define EXTI_D3PCR2H_PCS48_Msk       (0x3UL << EXTI_D3PCR2H_PCS48_Pos)         /*!< 0x00000003 */

+#define EXTI_D3PCR2H_PCS48           EXTI_D3PCR2H_PCS48_Msk                    /*!< D3 Pending request clear input signal selection on line 48 */

+#define EXTI_D3PCR2H_PCS49_Pos       (2U)

+#define EXTI_D3PCR2H_PCS49_Msk       (0x3UL << EXTI_D3PCR2H_PCS49_Pos)         /*!< 0x0000000C */

+#define EXTI_D3PCR2H_PCS49           EXTI_D3PCR2H_PCS49_Msk                    /*!< D3 Pending request clear input signal selection on line 49 */

+#define EXTI_D3PCR2H_PCS50_Pos       (4U)

+#define EXTI_D3PCR2H_PCS50_Msk       (0x3UL << EXTI_D3PCR2H_PCS50_Pos)         /*!< 0x00000030 */

+#define EXTI_D3PCR2H_PCS50           EXTI_D3PCR2H_PCS50_Msk                    /*!< D3 Pending request clear input signal selection on line 50 */

+#define EXTI_D3PCR2H_PCS51_Pos       (6U)

+#define EXTI_D3PCR2H_PCS51_Msk       (0x3UL << EXTI_D3PCR2H_PCS51_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR2H_PCS51           EXTI_D3PCR2H_PCS51_Msk                    /*!< D3 Pending request clear input signal selection on line 51 */

+#define EXTI_D3PCR2H_PCS52_Pos       (8U)

+#define EXTI_D3PCR2H_PCS52_Msk       (0x3UL << EXTI_D3PCR2H_PCS52_Pos)         /*!< 0x00000300 */

+#define EXTI_D3PCR2H_PCS52           EXTI_D3PCR2H_PCS52_Msk                    /*!< D3 Pending request clear input signal selection on line 52 */

+#define EXTI_D3PCR2H_PCS53_Pos       (10U)

+#define EXTI_D3PCR2H_PCS53_Msk       (0x3UL << EXTI_D3PCR2H_PCS53_Pos)         /*!< 0x00000C00 */

+#define EXTI_D3PCR2H_PCS53           EXTI_D3PCR2H_PCS53_Msk                    /*!< D3 Pending request clear input signal selection on line 53 */

+/******************  Bit definition for EXTI_RTSR3 register  *******************/

+#define EXTI_RTSR3_TR_Pos          (18U)

+#define EXTI_RTSR3_TR_Msk          (0x1DUL << EXTI_RTSR3_TR_Pos)               /*!< 0x00740000 */

+#define EXTI_RTSR3_TR              EXTI_RTSR3_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR3_TR82_Pos        (18U)

+#define EXTI_RTSR3_TR82_Msk        (0x1UL << EXTI_RTSR3_TR82_Pos)              /*!< 0x00040000 */

+#define EXTI_RTSR3_TR82            EXTI_RTSR3_TR82_Msk                         /*!< Rising trigger event configuration bit of line 82 */

+#define EXTI_RTSR3_TR84_Pos        (20U)

+#define EXTI_RTSR3_TR84_Msk        (0x1UL << EXTI_RTSR3_TR84_Pos)              /*!< 0x00100000 */

+#define EXTI_RTSR3_TR84            EXTI_RTSR3_TR84_Msk                         /*!< Rising trigger event configuration bit of line 84 */

+#define EXTI_RTSR3_TR85_Pos        (21U)

+#define EXTI_RTSR3_TR85_Msk        (0x1UL << EXTI_RTSR3_TR85_Pos)              /*!< 0x00200000 */

+#define EXTI_RTSR3_TR85            EXTI_RTSR3_TR85_Msk                         /*!< Rising trigger event configuration bit of line 85 */

+#define EXTI_RTSR3_TR86_Pos        (22U)

+#define EXTI_RTSR3_TR86_Msk        (0x1UL << EXTI_RTSR3_TR86_Pos)              /*!< 0x00400000 */

+#define EXTI_RTSR3_TR86            EXTI_RTSR3_TR86_Msk                         /*!< Rising trigger event configuration bit of line 86 */

+

+/******************  Bit definition for EXTI_FTSR3 register  *******************/

+#define EXTI_FTSR3_TR_Pos          (18U)

+#define EXTI_FTSR3_TR_Msk          (0x1DUL << EXTI_FTSR3_TR_Pos)               /*!< 0x00740000 */

+#define EXTI_FTSR3_TR              EXTI_FTSR3_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR3_TR82_Pos        (18U)

+#define EXTI_FTSR3_TR82_Msk        (0x1UL << EXTI_FTSR3_TR82_Pos)              /*!< 0x00040000 */

+#define EXTI_FTSR3_TR82            EXTI_FTSR3_TR82_Msk                         /*!< Falling trigger event configuration bit of line 82 */

+#define EXTI_FTSR3_TR84_Pos        (20U)

+#define EXTI_FTSR3_TR84_Msk        (0x1UL << EXTI_FTSR3_TR84_Pos)              /*!< 0x00100000 */

+#define EXTI_FTSR3_TR84            EXTI_FTSR3_TR84_Msk                         /*!< Falling trigger event configuration bit of line 84 */

+#define EXTI_FTSR3_TR85_Pos        (21U)

+#define EXTI_FTSR3_TR85_Msk        (0x1UL << EXTI_FTSR3_TR85_Pos)              /*!< 0x00200000 */

+#define EXTI_FTSR3_TR85            EXTI_FTSR3_TR85_Msk                         /*!< Falling trigger event configuration bit of line 85 */

+#define EXTI_FTSR3_TR86_Pos        (22U)

+#define EXTI_FTSR3_TR86_Msk        (0x1UL << EXTI_FTSR3_TR86_Pos)              /*!< 0x00400000 */

+#define EXTI_FTSR3_TR86            EXTI_FTSR3_TR86_Msk                         /*!< Falling trigger event configuration bit of line 86 */

+

+/******************  Bit definition for EXTI_SWIER3 register  ******************/

+#define EXTI_SWIER3_SWI_Pos        (18U)

+#define EXTI_SWIER3_SWI_Msk        (0x1DUL << EXTI_SWIER3_SWI_Pos)             /*!< 0x00740000 */

+#define EXTI_SWIER3_SWI            EXTI_SWIER3_SWI_Msk                         /*!< Software Interrupt event bit */

+#define EXTI_SWIER3_SWIER82_Pos    (18U)

+#define EXTI_SWIER3_SWIER82_Msk    (0x1UL << EXTI_SWIER3_SWIER82_Pos)          /*!< 0x00040000 */

+#define EXTI_SWIER3_SWIER82        EXTI_SWIER3_SWIER82_Msk                     /*!< Software Interrupt on line 82 */

+#define EXTI_SWIER3_SWIER84_Pos    (20U)

+#define EXTI_SWIER3_SWIER84_Msk    (0x1UL << EXTI_SWIER3_SWIER84_Pos)          /*!< 0x00100000 */

+#define EXTI_SWIER3_SWIER84        EXTI_SWIER3_SWIER84_Msk                     /*!< Software Interrupt on line 84 */

+#define EXTI_SWIER3_SWIER85_Pos    (21U)

+#define EXTI_SWIER3_SWIER85_Msk    (0x1UL << EXTI_SWIER3_SWIER85_Pos)          /*!< 0x00200000 */

+#define EXTI_SWIER3_SWIER85        EXTI_SWIER3_SWIER85_Msk                     /*!< Software Interrupt on line 85 */

+#define EXTI_SWIER3_SWIER86_Pos    (22U)

+#define EXTI_SWIER3_SWIER86_Msk    (0x1UL << EXTI_SWIER3_SWIER86_Pos)          /*!< 0x00400000 */

+#define EXTI_SWIER3_SWIER86        EXTI_SWIER3_SWIER86_Msk                     /*!< Software Interrupt on line 86 */

+

+/*******************  Bit definition for EXTI_IMR1 register  *******************/

+#define EXTI_IMR1_IM_Pos           (0U)

+#define EXTI_IMR1_IM_Msk           (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)          /*!< 0xFFFFFFFF */

+#define EXTI_IMR1_IM               EXTI_IMR1_IM_Msk                            /*!< Interrupt Mask */

+#define EXTI_IMR1_IM0_Pos          (0U)

+#define EXTI_IMR1_IM0_Msk          (0x1UL << EXTI_IMR1_IM0_Pos)                /*!< 0x00000001 */

+#define EXTI_IMR1_IM0              EXTI_IMR1_IM0_Msk                           /*!< Interrupt Mask on line 0 */

+#define EXTI_IMR1_IM1_Pos          (1U)

+#define EXTI_IMR1_IM1_Msk          (0x1UL << EXTI_IMR1_IM1_Pos)                /*!< 0x00000002 */

+#define EXTI_IMR1_IM1              EXTI_IMR1_IM1_Msk                           /*!< Interrupt Mask on line 1 */

+#define EXTI_IMR1_IM2_Pos          (2U)

+#define EXTI_IMR1_IM2_Msk          (0x1UL << EXTI_IMR1_IM2_Pos)                /*!< 0x00000004 */

+#define EXTI_IMR1_IM2              EXTI_IMR1_IM2_Msk                           /*!< Interrupt Mask on line 2 */

+#define EXTI_IMR1_IM3_Pos          (3U)

+#define EXTI_IMR1_IM3_Msk          (0x1UL << EXTI_IMR1_IM3_Pos)                /*!< 0x00000008 */

+#define EXTI_IMR1_IM3              EXTI_IMR1_IM3_Msk                           /*!< Interrupt Mask on line 3 */

+#define EXTI_IMR1_IM4_Pos          (4U)

+#define EXTI_IMR1_IM4_Msk          (0x1UL << EXTI_IMR1_IM4_Pos)                /*!< 0x00000010 */

+#define EXTI_IMR1_IM4              EXTI_IMR1_IM4_Msk                           /*!< Interrupt Mask on line 4 */

+#define EXTI_IMR1_IM5_Pos          (5U)

+#define EXTI_IMR1_IM5_Msk          (0x1UL << EXTI_IMR1_IM5_Pos)                /*!< 0x00000020 */

+#define EXTI_IMR1_IM5              EXTI_IMR1_IM5_Msk                           /*!< Interrupt Mask on line 5 */

+#define EXTI_IMR1_IM6_Pos          (6U)

+#define EXTI_IMR1_IM6_Msk          (0x1UL << EXTI_IMR1_IM6_Pos)                /*!< 0x00000040 */

+#define EXTI_IMR1_IM6              EXTI_IMR1_IM6_Msk                           /*!< Interrupt Mask on line 6 */

+#define EXTI_IMR1_IM7_Pos          (7U)

+#define EXTI_IMR1_IM7_Msk          (0x1UL << EXTI_IMR1_IM7_Pos)                /*!< 0x00000080 */

+#define EXTI_IMR1_IM7              EXTI_IMR1_IM7_Msk                           /*!< Interrupt Mask on line 7 */

+#define EXTI_IMR1_IM8_Pos          (8U)

+#define EXTI_IMR1_IM8_Msk          (0x1UL << EXTI_IMR1_IM8_Pos)                /*!< 0x00000100 */

+#define EXTI_IMR1_IM8              EXTI_IMR1_IM8_Msk                           /*!< Interrupt Mask on line 8 */

+#define EXTI_IMR1_IM9_Pos          (9U)

+#define EXTI_IMR1_IM9_Msk          (0x1UL << EXTI_IMR1_IM9_Pos)                /*!< 0x00000200 */

+#define EXTI_IMR1_IM9              EXTI_IMR1_IM9_Msk                           /*!< Interrupt Mask on line 9 */

+#define EXTI_IMR1_IM10_Pos         (10U)

+#define EXTI_IMR1_IM10_Msk         (0x1UL << EXTI_IMR1_IM10_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR1_IM10             EXTI_IMR1_IM10_Msk                          /*!< Interrupt Mask on line 10 */

+#define EXTI_IMR1_IM11_Pos         (11U)

+#define EXTI_IMR1_IM11_Msk         (0x1UL << EXTI_IMR1_IM11_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR1_IM11             EXTI_IMR1_IM11_Msk                          /*!< Interrupt Mask on line 11 */

+#define EXTI_IMR1_IM12_Pos         (12U)

+#define EXTI_IMR1_IM12_Msk         (0x1UL << EXTI_IMR1_IM12_Pos)               /*!< 0x00001000 */

+#define EXTI_IMR1_IM12             EXTI_IMR1_IM12_Msk                          /*!< Interrupt Mask on line 12 */

+#define EXTI_IMR1_IM13_Pos         (13U)

+#define EXTI_IMR1_IM13_Msk         (0x1UL << EXTI_IMR1_IM13_Pos)               /*!< 0x00002000 */

+#define EXTI_IMR1_IM13             EXTI_IMR1_IM13_Msk                          /*!< Interrupt Mask on line 13 */

+#define EXTI_IMR1_IM14_Pos         (14U)

+#define EXTI_IMR1_IM14_Msk         (0x1UL << EXTI_IMR1_IM14_Pos)               /*!< 0x00004000 */

+#define EXTI_IMR1_IM14             EXTI_IMR1_IM14_Msk                          /*!< Interrupt Mask on line 14 */

+#define EXTI_IMR1_IM15_Pos         (15U)

+#define EXTI_IMR1_IM15_Msk         (0x1UL << EXTI_IMR1_IM15_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR1_IM15             EXTI_IMR1_IM15_Msk                          /*!< Interrupt Mask on line 15 */

+#define EXTI_IMR1_IM16_Pos         (16U)

+#define EXTI_IMR1_IM16_Msk         (0x1UL << EXTI_IMR1_IM16_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR1_IM16             EXTI_IMR1_IM16_Msk                          /*!< Interrupt Mask on line 16 */

+#define EXTI_IMR1_IM17_Pos         (17U)

+#define EXTI_IMR1_IM17_Msk         (0x1UL << EXTI_IMR1_IM17_Pos)               /*!< 0x00020000 */

+#define EXTI_IMR1_IM17             EXTI_IMR1_IM17_Msk                          /*!< Interrupt Mask on line 17 */

+#define EXTI_IMR1_IM18_Pos         (18U)

+#define EXTI_IMR1_IM18_Msk         (0x1UL << EXTI_IMR1_IM18_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR1_IM18             EXTI_IMR1_IM18_Msk                          /*!< Interrupt Mask on line 18 */

+#define EXTI_IMR1_IM19_Pos         (19U)

+#define EXTI_IMR1_IM19_Msk         (0x1UL << EXTI_IMR1_IM19_Pos)               /*!< 0x00080000 */

+#define EXTI_IMR1_IM19             EXTI_IMR1_IM19_Msk                          /*!< Interrupt Mask on line 19 */

+#define EXTI_IMR1_IM20_Pos         (20U)

+#define EXTI_IMR1_IM20_Msk         (0x1UL << EXTI_IMR1_IM20_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR1_IM20             EXTI_IMR1_IM20_Msk                          /*!< Interrupt Mask on line 20 */

+#define EXTI_IMR1_IM21_Pos         (21U)

+#define EXTI_IMR1_IM21_Msk         (0x1UL << EXTI_IMR1_IM21_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR1_IM21             EXTI_IMR1_IM21_Msk                          /*!< Interrupt Mask on line 21 */

+#define EXTI_IMR1_IM22_Pos         (22U)

+#define EXTI_IMR1_IM22_Msk         (0x1UL << EXTI_IMR1_IM22_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR1_IM22             EXTI_IMR1_IM22_Msk                          /*!< Interrupt Mask on line 22 */

+#define EXTI_IMR1_IM23_Pos         (23U)

+#define EXTI_IMR1_IM23_Msk         (0x1UL << EXTI_IMR1_IM23_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR1_IM23             EXTI_IMR1_IM23_Msk                          /*!< Interrupt Mask on line 23 */

+#define EXTI_IMR1_IM24_Pos         (24U)

+#define EXTI_IMR1_IM24_Msk         (0x1UL << EXTI_IMR1_IM24_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR1_IM24             EXTI_IMR1_IM24_Msk                          /*!< Interrupt Mask on line 24 */

+#define EXTI_IMR1_IM25_Pos         (25U)

+#define EXTI_IMR1_IM25_Msk         (0x1UL << EXTI_IMR1_IM25_Pos)               /*!< 0x02000000 */

+#define EXTI_IMR1_IM25             EXTI_IMR1_IM25_Msk                          /*!< Interrupt Mask on line 25 */

+#define EXTI_IMR1_IM26_Pos         (26U)

+#define EXTI_IMR1_IM26_Msk         (0x1UL << EXTI_IMR1_IM26_Pos)               /*!< 0x04000000 */

+#define EXTI_IMR1_IM26             EXTI_IMR1_IM26_Msk                          /*!< Interrupt Mask on line 26 */

+#define EXTI_IMR1_IM27_Pos         (27U)

+#define EXTI_IMR1_IM27_Msk         (0x1UL << EXTI_IMR1_IM27_Pos)               /*!< 0x08000000 */

+#define EXTI_IMR1_IM27             EXTI_IMR1_IM27_Msk                          /*!< Interrupt Mask on line 27 */

+#define EXTI_IMR1_IM28_Pos         (28U)

+#define EXTI_IMR1_IM28_Msk         (0x1UL << EXTI_IMR1_IM28_Pos)               /*!< 0x10000000 */

+#define EXTI_IMR1_IM28             EXTI_IMR1_IM28_Msk                          /*!< Interrupt Mask on line 28 */

+#define EXTI_IMR1_IM29_Pos         (29U)

+#define EXTI_IMR1_IM29_Msk         (0x1UL << EXTI_IMR1_IM29_Pos)               /*!< 0x20000000 */

+#define EXTI_IMR1_IM29             EXTI_IMR1_IM29_Msk                          /*!< Interrupt Mask on line 29 */

+#define EXTI_IMR1_IM30_Pos         (30U)

+#define EXTI_IMR1_IM30_Msk         (0x1UL << EXTI_IMR1_IM30_Pos)               /*!< 0x40000000 */

+#define EXTI_IMR1_IM30             EXTI_IMR1_IM30_Msk                          /*!< Interrupt Mask on line 30 */

+#define EXTI_IMR1_IM31_Pos         (31U)

+#define EXTI_IMR1_IM31_Msk         (0x1UL << EXTI_IMR1_IM31_Pos)               /*!< 0x80000000 */

+#define EXTI_IMR1_IM31             EXTI_IMR1_IM31_Msk                          /*!< Interrupt Mask on line 31 */

+

+/*******************  Bit definition for EXTI_EMR1 register  *******************/

+#define EXTI_EMR1_EM_Pos           (0U)

+#define EXTI_EMR1_EM_Msk           (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)          /*!< 0xFFFFFFFF */

+#define EXTI_EMR1_EM               EXTI_EMR1_EM_Msk                            /*!< Event Mask */

+#define EXTI_EMR1_EM0_Pos          (0U)

+#define EXTI_EMR1_EM0_Msk          (0x1UL << EXTI_EMR1_EM0_Pos)                /*!< 0x00000001 */

+#define EXTI_EMR1_EM0              EXTI_EMR1_EM0_Msk                           /*!< Event Mask on line 0 */

+#define EXTI_EMR1_EM1_Pos          (1U)

+#define EXTI_EMR1_EM1_Msk          (0x1UL << EXTI_EMR1_EM1_Pos)                /*!< 0x00000002 */

+#define EXTI_EMR1_EM1              EXTI_EMR1_EM1_Msk                           /*!< Event Mask on line 1 */

+#define EXTI_EMR1_EM2_Pos          (2U)

+#define EXTI_EMR1_EM2_Msk          (0x1UL << EXTI_EMR1_EM2_Pos)                /*!< 0x00000004 */

+#define EXTI_EMR1_EM2              EXTI_EMR1_EM2_Msk                           /*!< Event Mask on line 2 */

+#define EXTI_EMR1_EM3_Pos          (3U)

+#define EXTI_EMR1_EM3_Msk          (0x1UL << EXTI_EMR1_EM3_Pos)                /*!< 0x00000008 */

+#define EXTI_EMR1_EM3              EXTI_EMR1_EM3_Msk                           /*!< Event Mask on line 3 */

+#define EXTI_EMR1_EM4_Pos          (4U)

+#define EXTI_EMR1_EM4_Msk          (0x1UL << EXTI_EMR1_EM4_Pos)                /*!< 0x00000010 */

+#define EXTI_EMR1_EM4              EXTI_EMR1_EM4_Msk                           /*!< Event Mask on line 4 */

+#define EXTI_EMR1_EM5_Pos          (5U)

+#define EXTI_EMR1_EM5_Msk          (0x1UL << EXTI_EMR1_EM5_Pos)                /*!< 0x00000020 */

+#define EXTI_EMR1_EM5              EXTI_EMR1_EM5_Msk                           /*!< Event Mask on line 5 */

+#define EXTI_EMR1_EM6_Pos          (6U)

+#define EXTI_EMR1_EM6_Msk          (0x1UL << EXTI_EMR1_EM6_Pos)                /*!< 0x00000040 */

+#define EXTI_EMR1_EM6              EXTI_EMR1_EM6_Msk                           /*!< Event Mask on line 6 */

+#define EXTI_EMR1_EM7_Pos          (7U)

+#define EXTI_EMR1_EM7_Msk          (0x1UL << EXTI_EMR1_EM7_Pos)                /*!< 0x00000080 */

+#define EXTI_EMR1_EM7              EXTI_EMR1_EM7_Msk                           /*!< Event Mask on line 7 */

+#define EXTI_EMR1_EM8_Pos          (8U)

+#define EXTI_EMR1_EM8_Msk          (0x1UL << EXTI_EMR1_EM8_Pos)                /*!< 0x00000100 */

+#define EXTI_EMR1_EM8              EXTI_EMR1_EM8_Msk                           /*!< Event Mask on line 8 */

+#define EXTI_EMR1_EM9_Pos          (9U)

+#define EXTI_EMR1_EM9_Msk          (0x1UL << EXTI_EMR1_EM9_Pos)                /*!< 0x00000200 */

+#define EXTI_EMR1_EM9              EXTI_EMR1_EM9_Msk                           /*!< Event Mask on line 9 */

+#define EXTI_EMR1_EM10_Pos         (10U)

+#define EXTI_EMR1_EM10_Msk         (0x1UL << EXTI_EMR1_EM10_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR1_EM10             EXTI_EMR1_EM10_Msk                          /*!< Event Mask on line 10 */

+#define EXTI_EMR1_EM11_Pos         (11U)

+#define EXTI_EMR1_EM11_Msk         (0x1UL << EXTI_EMR1_EM11_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR1_EM11             EXTI_EMR1_EM11_Msk                          /*!< Event Mask on line 11 */

+#define EXTI_EMR1_EM12_Pos         (12U)

+#define EXTI_EMR1_EM12_Msk         (0x1UL << EXTI_EMR1_EM12_Pos)               /*!< 0x00001000 */

+#define EXTI_EMR1_EM12             EXTI_EMR1_EM12_Msk                          /*!< Event Mask on line 12 */

+#define EXTI_EMR1_EM13_Pos         (13U)

+#define EXTI_EMR1_EM13_Msk         (0x1UL << EXTI_EMR1_EM13_Pos)               /*!< 0x00002000 */

+#define EXTI_EMR1_EM13             EXTI_EMR1_EM13_Msk                          /*!< Event Mask on line 13 */

+#define EXTI_EMR1_EM14_Pos         (14U)

+#define EXTI_EMR1_EM14_Msk         (0x1UL << EXTI_EMR1_EM14_Pos)               /*!< 0x00004000 */

+#define EXTI_EMR1_EM14             EXTI_EMR1_EM14_Msk                          /*!< Event Mask on line 14 */

+#define EXTI_EMR1_EM15_Pos         (15U)

+#define EXTI_EMR1_EM15_Msk         (0x1UL << EXTI_EMR1_EM15_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR1_EM15             EXTI_EMR1_EM15_Msk                          /*!< Event Mask on line 15 */

+#define EXTI_EMR1_EM16_Pos         (16U)

+#define EXTI_EMR1_EM16_Msk         (0x1UL << EXTI_EMR1_EM16_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR1_EM16             EXTI_EMR1_EM16_Msk                          /*!< Event Mask on line 16 */

+#define EXTI_EMR1_EM17_Pos         (17U)

+#define EXTI_EMR1_EM17_Msk         (0x1UL << EXTI_EMR1_EM17_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR1_EM17             EXTI_EMR1_EM17_Msk                          /*!< Event Mask on line 17 */

+#define EXTI_EMR1_EM18_Pos         (18U)

+#define EXTI_EMR1_EM18_Msk         (0x1UL << EXTI_EMR1_EM18_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR1_EM18             EXTI_EMR1_EM18_Msk                          /*!< Event Mask on line 18 */

+#define EXTI_EMR1_EM20_Pos         (20U)

+#define EXTI_EMR1_EM20_Msk         (0x1UL << EXTI_EMR1_EM20_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR1_EM20             EXTI_EMR1_EM20_Msk                          /*!< Event Mask on line 20 */

+#define EXTI_EMR1_EM21_Pos         (21U)

+#define EXTI_EMR1_EM21_Msk         (0x1UL << EXTI_EMR1_EM21_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR1_EM21             EXTI_EMR1_EM21_Msk                          /*!< Event Mask on line 21 */

+#define EXTI_EMR1_EM22_Pos         (22U)

+#define EXTI_EMR1_EM22_Msk         (0x1UL << EXTI_EMR1_EM22_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR1_EM22             EXTI_EMR1_EM22_Msk                          /*!< Event Mask on line 22 */

+#define EXTI_EMR1_EM23_Pos         (23U)

+#define EXTI_EMR1_EM23_Msk         (0x1UL << EXTI_EMR1_EM23_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR1_EM23             EXTI_EMR1_EM23_Msk                          /*!< Event Mask on line 23 */

+#define EXTI_EMR1_EM24_Pos         (24U)

+#define EXTI_EMR1_EM24_Msk         (0x1UL << EXTI_EMR1_EM24_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR1_EM24             EXTI_EMR1_EM24_Msk                          /*!< Event Mask on line 24 */

+#define EXTI_EMR1_EM25_Pos         (25U)

+#define EXTI_EMR1_EM25_Msk         (0x1UL << EXTI_EMR1_EM25_Pos)               /*!< 0x02000000 */

+#define EXTI_EMR1_EM25             EXTI_EMR1_EM25_Msk                          /*!< Event Mask on line 25 */

+#define EXTI_EMR1_EM26_Pos         (26U)

+#define EXTI_EMR1_EM26_Msk         (0x1UL << EXTI_EMR1_EM26_Pos)               /*!< 0x04000000 */

+#define EXTI_EMR1_EM26             EXTI_EMR1_EM26_Msk                          /*!< Event Mask on line 26 */

+#define EXTI_EMR1_EM27_Pos         (27U)

+#define EXTI_EMR1_EM27_Msk         (0x1UL << EXTI_EMR1_EM27_Pos)               /*!< 0x08000000 */

+#define EXTI_EMR1_EM27             EXTI_EMR1_EM27_Msk                          /*!< Event Mask on line 27 */

+#define EXTI_EMR1_EM28_Pos         (28U)

+#define EXTI_EMR1_EM28_Msk         (0x1UL << EXTI_EMR1_EM28_Pos)               /*!< 0x10000000 */

+#define EXTI_EMR1_EM28             EXTI_EMR1_EM28_Msk                          /*!< Event Mask on line 28 */

+#define EXTI_EMR1_EM29_Pos         (29U)

+#define EXTI_EMR1_EM29_Msk         (0x1UL << EXTI_EMR1_EM29_Pos)               /*!< 0x20000000 */

+#define EXTI_EMR1_EM29             EXTI_EMR1_EM29_Msk                          /*!< Event Mask on line 29 */

+#define EXTI_EMR1_EM30_Pos         (30U)

+#define EXTI_EMR1_EM30_Msk         (0x1UL << EXTI_EMR1_EM30_Pos)               /*!< 0x40000000 */

+#define EXTI_EMR1_EM30             EXTI_EMR1_EM30_Msk                          /*!< Event Mask on line 30 */

+#define EXTI_EMR1_EM31_Pos         (31U)

+#define EXTI_EMR1_EM31_Msk         (0x1UL << EXTI_EMR1_EM31_Pos)               /*!< 0x80000000 */

+#define EXTI_EMR1_EM31             EXTI_EMR1_EM31_Msk                          /*!< Event Mask on line 31 */

+

+/*******************  Bit definition for EXTI_PR1 register  ********************/

+#define EXTI_PR1_PR_Pos            (0U)

+#define EXTI_PR1_PR_Msk            (0x3FFFFFUL << EXTI_PR1_PR_Pos)             /*!< 0x003FFFFF */

+#define EXTI_PR1_PR                EXTI_PR1_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR1_PR0_Pos           (0U)

+#define EXTI_PR1_PR0_Msk           (0x1UL << EXTI_PR1_PR0_Pos)                 /*!< 0x00000001 */

+#define EXTI_PR1_PR0               EXTI_PR1_PR0_Msk                            /*!< Pending bit for line 0 */

+#define EXTI_PR1_PR1_Pos           (1U)

+#define EXTI_PR1_PR1_Msk           (0x1UL << EXTI_PR1_PR1_Pos)                 /*!< 0x00000002 */

+#define EXTI_PR1_PR1               EXTI_PR1_PR1_Msk                            /*!< Pending bit for line 1 */

+#define EXTI_PR1_PR2_Pos           (2U)

+#define EXTI_PR1_PR2_Msk           (0x1UL << EXTI_PR1_PR2_Pos)                 /*!< 0x00000004 */

+#define EXTI_PR1_PR2               EXTI_PR1_PR2_Msk                            /*!< Pending bit for line 2 */

+#define EXTI_PR1_PR3_Pos           (3U)

+#define EXTI_PR1_PR3_Msk           (0x1UL << EXTI_PR1_PR3_Pos)                 /*!< 0x00000008 */

+#define EXTI_PR1_PR3               EXTI_PR1_PR3_Msk                            /*!< Pending bit for line 3 */

+#define EXTI_PR1_PR4_Pos           (4U)

+#define EXTI_PR1_PR4_Msk           (0x1UL << EXTI_PR1_PR4_Pos)                 /*!< 0x00000010 */

+#define EXTI_PR1_PR4               EXTI_PR1_PR4_Msk                            /*!< Pending bit for line 4 */

+#define EXTI_PR1_PR5_Pos           (5U)

+#define EXTI_PR1_PR5_Msk           (0x1UL << EXTI_PR1_PR5_Pos)                 /*!< 0x00000020 */

+#define EXTI_PR1_PR5               EXTI_PR1_PR5_Msk                            /*!< Pending bit for line 5 */

+#define EXTI_PR1_PR6_Pos           (6U)

+#define EXTI_PR1_PR6_Msk           (0x1UL << EXTI_PR1_PR6_Pos)                 /*!< 0x00000040 */

+#define EXTI_PR1_PR6               EXTI_PR1_PR6_Msk                            /*!< Pending bit for line 6 */

+#define EXTI_PR1_PR7_Pos           (7U)

+#define EXTI_PR1_PR7_Msk           (0x1UL << EXTI_PR1_PR7_Pos)                 /*!< 0x00000080 */

+#define EXTI_PR1_PR7               EXTI_PR1_PR7_Msk                            /*!< Pending bit for line 7 */

+#define EXTI_PR1_PR8_Pos           (8U)

+#define EXTI_PR1_PR8_Msk           (0x1UL << EXTI_PR1_PR8_Pos)                 /*!< 0x00000100 */

+#define EXTI_PR1_PR8               EXTI_PR1_PR8_Msk                            /*!< Pending bit for line 8 */

+#define EXTI_PR1_PR9_Pos           (9U)

+#define EXTI_PR1_PR9_Msk           (0x1UL << EXTI_PR1_PR9_Pos)                 /*!< 0x00000200 */

+#define EXTI_PR1_PR9               EXTI_PR1_PR9_Msk                            /*!< Pending bit for line 9 */

+#define EXTI_PR1_PR10_Pos          (10U)

+#define EXTI_PR1_PR10_Msk          (0x1UL << EXTI_PR1_PR10_Pos)                /*!< 0x00000400 */

+#define EXTI_PR1_PR10              EXTI_PR1_PR10_Msk                           /*!< Pending bit for line 10 */

+#define EXTI_PR1_PR11_Pos          (11U)

+#define EXTI_PR1_PR11_Msk          (0x1UL << EXTI_PR1_PR11_Pos)                /*!< 0x00000800 */

+#define EXTI_PR1_PR11              EXTI_PR1_PR11_Msk                           /*!< Pending bit for line 11 */

+#define EXTI_PR1_PR12_Pos          (12U)

+#define EXTI_PR1_PR12_Msk          (0x1UL << EXTI_PR1_PR12_Pos)                /*!< 0x00001000 */

+#define EXTI_PR1_PR12              EXTI_PR1_PR12_Msk                           /*!< Pending bit for line 12 */

+#define EXTI_PR1_PR13_Pos          (13U)

+#define EXTI_PR1_PR13_Msk          (0x1UL << EXTI_PR1_PR13_Pos)                /*!< 0x00002000 */

+#define EXTI_PR1_PR13              EXTI_PR1_PR13_Msk                           /*!< Pending bit for line 13 */

+#define EXTI_PR1_PR14_Pos          (14U)

+#define EXTI_PR1_PR14_Msk          (0x1UL << EXTI_PR1_PR14_Pos)                /*!< 0x00004000 */

+#define EXTI_PR1_PR14              EXTI_PR1_PR14_Msk                           /*!< Pending bit for line 14 */

+#define EXTI_PR1_PR15_Pos          (15U)

+#define EXTI_PR1_PR15_Msk          (0x1UL << EXTI_PR1_PR15_Pos)                /*!< 0x00008000 */

+#define EXTI_PR1_PR15              EXTI_PR1_PR15_Msk                           /*!< Pending bit for line 15 */

+#define EXTI_PR1_PR16_Pos          (16U)

+#define EXTI_PR1_PR16_Msk          (0x1UL << EXTI_PR1_PR16_Pos)                /*!< 0x00010000 */

+#define EXTI_PR1_PR16              EXTI_PR1_PR16_Msk                           /*!< Pending bit for line 16 */

+#define EXTI_PR1_PR17_Pos          (17U)

+#define EXTI_PR1_PR17_Msk          (0x1UL << EXTI_PR1_PR17_Pos)                /*!< 0x00020000 */

+#define EXTI_PR1_PR17              EXTI_PR1_PR17_Msk                           /*!< Pending bit for line 17 */

+#define EXTI_PR1_PR18_Pos          (18U)

+#define EXTI_PR1_PR18_Msk          (0x1UL << EXTI_PR1_PR18_Pos)                /*!< 0x00040000 */

+#define EXTI_PR1_PR18              EXTI_PR1_PR18_Msk                           /*!< Pending bit for line 18 */

+#define EXTI_PR1_PR19_Pos          (19U)

+#define EXTI_PR1_PR19_Msk          (0x1UL << EXTI_PR1_PR19_Pos)                /*!< 0x00080000 */

+#define EXTI_PR1_PR19              EXTI_PR1_PR19_Msk                           /*!< Pending bit for line 19 */

+#define EXTI_PR1_PR20_Pos          (20U)

+#define EXTI_PR1_PR20_Msk          (0x1UL << EXTI_PR1_PR20_Pos)                /*!< 0x00100000 */

+#define EXTI_PR1_PR20              EXTI_PR1_PR20_Msk                           /*!< Pending bit for line 20 */

+#define EXTI_PR1_PR21_Pos          (21U)

+#define EXTI_PR1_PR21_Msk          (0x1UL << EXTI_PR1_PR21_Pos)                /*!< 0x00200000 */

+#define EXTI_PR1_PR21              EXTI_PR1_PR21_Msk                           /*!< Pending bit for line 21 */

+

+/*******************  Bit definition for EXTI_IMR2 register  *******************/

+#define EXTI_IMR2_IM_Pos           (0U)

+#define EXTI_IMR2_IM_Msk           (0xFFFFDFFFUL << EXTI_IMR2_IM_Pos)          /*!< 0xFFFFDFFF */

+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            /*!< Interrupt Mask */

+#define EXTI_IMR2_IM32_Pos         (0U)

+#define EXTI_IMR2_IM32_Msk         (0x1UL << EXTI_IMR2_IM32_Pos)               /*!< 0x00000001 */

+#define EXTI_IMR2_IM32             EXTI_IMR2_IM32_Msk                          /*!< Interrupt Mask on line 32 */

+#define EXTI_IMR2_IM33_Pos         (1U)

+#define EXTI_IMR2_IM33_Msk         (0x1UL << EXTI_IMR2_IM33_Pos)               /*!< 0x00000002 */

+#define EXTI_IMR2_IM33             EXTI_IMR2_IM33_Msk                          /*!< Interrupt Mask on line 33 */

+#define EXTI_IMR2_IM34_Pos         (2U)

+#define EXTI_IMR2_IM34_Msk         (0x1UL << EXTI_IMR2_IM34_Pos)               /*!< 0x00000004 */

+#define EXTI_IMR2_IM34             EXTI_IMR2_IM34_Msk                          /*!< Interrupt Mask on line 34 */

+#define EXTI_IMR2_IM35_Pos         (3U)

+#define EXTI_IMR2_IM35_Msk         (0x1UL << EXTI_IMR2_IM35_Pos)               /*!< 0x00000008 */

+#define EXTI_IMR2_IM35             EXTI_IMR2_IM35_Msk                          /*!< Interrupt Mask on line 35 */

+#define EXTI_IMR2_IM36_Pos         (4U)

+#define EXTI_IMR2_IM36_Msk         (0x1UL << EXTI_IMR2_IM36_Pos)               /*!< 0x00000010 */

+#define EXTI_IMR2_IM36             EXTI_IMR2_IM36_Msk                          /*!< Interrupt Mask on line 36 */

+#define EXTI_IMR2_IM37_Pos         (5U)

+#define EXTI_IMR2_IM37_Msk         (0x1UL << EXTI_IMR2_IM37_Pos)               /*!< 0x00000020 */

+#define EXTI_IMR2_IM37             EXTI_IMR2_IM37_Msk                          /*!< Interrupt Mask on line 37 */

+#define EXTI_IMR2_IM38_Pos         (6U)

+#define EXTI_IMR2_IM38_Msk         (0x1UL << EXTI_IMR2_IM38_Pos)               /*!< 0x00000040 */

+#define EXTI_IMR2_IM38             EXTI_IMR2_IM38_Msk                          /*!< Interrupt Mask on line 38 */

+#define EXTI_IMR2_IM39_Pos         (7U)

+#define EXTI_IMR2_IM39_Msk         (0x1UL << EXTI_IMR2_IM39_Pos)               /*!< 0x00000080 */

+#define EXTI_IMR2_IM39             EXTI_IMR2_IM39_Msk                          /*!< Interrupt Mask on line 39 */

+#define EXTI_IMR2_IM40_Pos         (8U)

+#define EXTI_IMR2_IM40_Msk         (0x1UL << EXTI_IMR2_IM40_Pos)               /*!< 0x00000100 */

+#define EXTI_IMR2_IM40             EXTI_IMR2_IM40_Msk                          /*!< Interrupt Mask on line 40 */

+#define EXTI_IMR2_IM41_Pos         (9U)

+#define EXTI_IMR2_IM41_Msk         (0x1UL << EXTI_IMR2_IM41_Pos)               /*!< 0x00000200 */

+#define EXTI_IMR2_IM41             EXTI_IMR2_IM41_Msk                          /*!< Interrupt Mask on line 41 */

+#define EXTI_IMR2_IM42_Pos         (10U)

+#define EXTI_IMR2_IM42_Msk         (0x1UL << EXTI_IMR2_IM42_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR2_IM42             EXTI_IMR2_IM42_Msk                          /*!< Interrupt Mask on line 42 */

+#define EXTI_IMR2_IM43_Pos         (11U)

+#define EXTI_IMR2_IM43_Msk         (0x1UL << EXTI_IMR2_IM43_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR2_IM43             EXTI_IMR2_IM43_Msk                          /*!< Interrupt Mask on line 43 */

+#define EXTI_IMR2_IM44_Pos         (12U)

+#define EXTI_IMR2_IM44_Msk         (0x1UL << EXTI_IMR2_IM44_Pos)               /*!< 0x00001000 */

+#define EXTI_IMR2_IM44             EXTI_IMR2_IM44_Msk                          /*!< Interrupt Mask on line 44 */

+#define EXTI_IMR2_IM46_Pos         (14U)

+#define EXTI_IMR2_IM46_Msk         (0x1UL << EXTI_IMR2_IM46_Pos)               /*!< 0x00004000 */

+#define EXTI_IMR2_IM46             EXTI_IMR2_IM46_Msk                          /*!< Interrupt Mask on line 46 */

+#define EXTI_IMR2_IM47_Pos         (15U)

+#define EXTI_IMR2_IM47_Msk         (0x1UL << EXTI_IMR2_IM47_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR2_IM47             EXTI_IMR2_IM47_Msk                          /*!< Interrupt Mask on line 47 */

+#define EXTI_IMR2_IM48_Pos         (16U)

+#define EXTI_IMR2_IM48_Msk         (0x1UL << EXTI_IMR2_IM48_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR2_IM48             EXTI_IMR2_IM48_Msk                          /*!< Interrupt Mask on line 48 */

+#define EXTI_IMR2_IM49_Pos         (17U)

+#define EXTI_IMR2_IM49_Msk         (0x1UL << EXTI_IMR2_IM49_Pos)               /*!< 0x00020000 */

+#define EXTI_IMR2_IM49             EXTI_IMR2_IM49_Msk                          /*!< Interrupt Mask on line 49 */

+#define EXTI_IMR2_IM50_Pos         (18U)

+#define EXTI_IMR2_IM50_Msk         (0x1UL << EXTI_IMR2_IM50_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR2_IM50             EXTI_IMR2_IM50_Msk                          /*!< Interrupt Mask on line 50 */

+#define EXTI_IMR2_IM51_Pos         (19U)

+#define EXTI_IMR2_IM51_Msk         (0x1UL << EXTI_IMR2_IM51_Pos)               /*!< 0x00080000 */

+#define EXTI_IMR2_IM51             EXTI_IMR2_IM51_Msk                          /*!< Interrupt Mask on line 51 */

+#define EXTI_IMR2_IM52_Pos         (20U)

+#define EXTI_IMR2_IM52_Msk         (0x1UL << EXTI_IMR2_IM52_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR2_IM52             EXTI_IMR2_IM52_Msk                          /*!< Interrupt Mask on line 52 */

+#define EXTI_IMR2_IM53_Pos         (21U)

+#define EXTI_IMR2_IM53_Msk         (0x1UL << EXTI_IMR2_IM53_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR2_IM53             EXTI_IMR2_IM53_Msk                          /*!< Interrupt Mask on line 53 */

+#define EXTI_IMR2_IM54_Pos         (22U)

+#define EXTI_IMR2_IM54_Msk         (0x1UL << EXTI_IMR2_IM54_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR2_IM54             EXTI_IMR2_IM54_Msk                          /*!< Interrupt Mask on line 54 */

+#define EXTI_IMR2_IM55_Pos         (23U)

+#define EXTI_IMR2_IM55_Msk         (0x1UL << EXTI_IMR2_IM55_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR2_IM55             EXTI_IMR2_IM55_Msk                          /*!< Interrupt Mask on line 55 */

+#define EXTI_IMR2_IM56_Pos         (24U)

+#define EXTI_IMR2_IM56_Msk         (0x1UL << EXTI_IMR2_IM56_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR2_IM56             EXTI_IMR2_IM56_Msk                          /*!< Interrupt Mask on line 56 */

+#define EXTI_IMR2_IM57_Pos         (25U)

+#define EXTI_IMR2_IM57_Msk         (0x1UL << EXTI_IMR2_IM57_Pos)               /*!< 0x02000000 */

+#define EXTI_IMR2_IM57             EXTI_IMR2_IM57_Msk                          /*!< Interrupt Mask on line 57 */

+#define EXTI_IMR2_IM58_Pos         (26U)

+#define EXTI_IMR2_IM58_Msk         (0x1UL << EXTI_IMR2_IM58_Pos)               /*!< 0x04000000 */

+#define EXTI_IMR2_IM58             EXTI_IMR2_IM58_Msk                          /*!< Interrupt Mask on line 58 */

+#define EXTI_IMR2_IM59_Pos         (27U)

+#define EXTI_IMR2_IM59_Msk         (0x1UL << EXTI_IMR2_IM59_Pos)               /*!< 0x08000000 */

+#define EXTI_IMR2_IM59             EXTI_IMR2_IM59_Msk                          /*!< Interrupt Mask on line 59 */

+#define EXTI_IMR2_IM60_Pos         (28U)

+#define EXTI_IMR2_IM60_Msk         (0x1UL << EXTI_IMR2_IM60_Pos)               /*!< 0x10000000 */

+#define EXTI_IMR2_IM60             EXTI_IMR2_IM60_Msk                          /*!< Interrupt Mask on line 60 */

+#define EXTI_IMR2_IM61_Pos         (29U)

+#define EXTI_IMR2_IM61_Msk         (0x1UL << EXTI_IMR2_IM61_Pos)               /*!< 0x20000000 */

+#define EXTI_IMR2_IM61             EXTI_IMR2_IM61_Msk                          /*!< Interrupt Mask on line 61 */

+#define EXTI_IMR2_IM62_Pos         (30U)

+#define EXTI_IMR2_IM62_Msk         (0x1UL << EXTI_IMR2_IM62_Pos)               /*!< 0x40000000 */

+#define EXTI_IMR2_IM62             EXTI_IMR2_IM62_Msk                          /*!< Interrupt Mask on line 62 */

+#define EXTI_IMR2_IM63_Pos         (31U)

+#define EXTI_IMR2_IM63_Msk         (0x1UL << EXTI_IMR2_IM63_Pos)               /*!< 0x80000000 */

+#define EXTI_IMR2_IM63             EXTI_IMR2_IM63_Msk                          /*!< Interrupt Mask on line 63 */

+

+/*******************  Bit definition for EXTI_EMR2 register  *******************/

+#define EXTI_EMR2_EM_Pos           (0U)

+#define EXTI_EMR2_EM_Msk           (0xFFFFDFFFUL << EXTI_EMR2_EM_Pos)          /*!< 0xFFFFDFFF */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            /*!< Event Mask */

+#define EXTI_EMR2_EM32_Pos         (0U)

+#define EXTI_EMR2_EM32_Msk         (0x1UL << EXTI_EMR2_EM32_Pos)               /*!< 0x00000001 */

+#define EXTI_EMR2_EM32             EXTI_EMR2_EM32_Msk                          /*!< Event Mask on line 32*/

+#define EXTI_EMR2_EM33_Pos         (1U)

+#define EXTI_EMR2_EM33_Msk         (0x1UL << EXTI_EMR2_EM33_Pos)               /*!< 0x00000002 */

+#define EXTI_EMR2_EM33             EXTI_EMR2_EM33_Msk                          /*!< Event Mask on line 33*/

+#define EXTI_EMR2_EM34_Pos         (2U)

+#define EXTI_EMR2_EM34_Msk         (0x1UL << EXTI_EMR2_EM34_Pos)               /*!< 0x00000004 */

+#define EXTI_EMR2_EM34             EXTI_EMR2_EM34_Msk                          /*!< Event Mask on line 34*/

+#define EXTI_EMR2_EM35_Pos         (3U)

+#define EXTI_EMR2_EM35_Msk         (0x1UL << EXTI_EMR2_EM35_Pos)               /*!< 0x00000008 */

+#define EXTI_EMR2_EM35             EXTI_EMR2_EM35_Msk                          /*!< Event Mask on line 35*/

+#define EXTI_EMR2_EM36_Pos         (4U)

+#define EXTI_EMR2_EM36_Msk         (0x1UL << EXTI_EMR2_EM36_Pos)               /*!< 0x00000010 */

+#define EXTI_EMR2_EM36             EXTI_EMR2_EM36_Msk                          /*!< Event Mask on line 36*/

+#define EXTI_EMR2_EM37_Pos         (5U)

+#define EXTI_EMR2_EM37_Msk         (0x1UL << EXTI_EMR2_EM37_Pos)               /*!< 0x00000020 */

+#define EXTI_EMR2_EM37             EXTI_EMR2_EM37_Msk                          /*!< Event Mask on line 37*/

+#define EXTI_EMR2_EM38_Pos         (6U)

+#define EXTI_EMR2_EM38_Msk         (0x1UL << EXTI_EMR2_EM38_Pos)               /*!< 0x00000040 */

+#define EXTI_EMR2_EM38             EXTI_EMR2_EM38_Msk                          /*!< Event Mask on line 38*/

+#define EXTI_EMR2_EM39_Pos         (7U)

+#define EXTI_EMR2_EM39_Msk         (0x1UL << EXTI_EMR2_EM39_Pos)               /*!< 0x00000080 */

+#define EXTI_EMR2_EM39             EXTI_EMR2_EM39_Msk                          /*!< Event Mask on line 39*/

+#define EXTI_EMR2_EM40_Pos         (8U)

+#define EXTI_EMR2_EM40_Msk         (0x1UL << EXTI_EMR2_EM40_Pos)               /*!< 0x00000100 */

+#define EXTI_EMR2_EM40             EXTI_EMR2_EM40_Msk                          /*!< Event Mask on line 40*/

+#define EXTI_EMR2_EM41_Pos         (9U)

+#define EXTI_EMR2_EM41_Msk         (0x1UL << EXTI_EMR2_EM41_Pos)               /*!< 0x00000200 */

+#define EXTI_EMR2_EM41             EXTI_EMR2_EM41_Msk                          /*!< Event Mask on line 41*/

+#define EXTI_EMR2_EM42_Pos         (10U)

+#define EXTI_EMR2_EM42_Msk         (0x1UL << EXTI_EMR2_EM42_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR2_EM42             EXTI_EMR2_EM42_Msk                          /*!< Event Mask on line 42 */

+#define EXTI_EMR2_EM43_Pos         (11U)

+#define EXTI_EMR2_EM43_Msk         (0x1UL << EXTI_EMR2_EM43_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR2_EM43             EXTI_EMR2_EM43_Msk                          /*!< Event Mask on line 43 */

+#define EXTI_EMR2_EM44_Pos         (12U)

+#define EXTI_EMR2_EM44_Msk         (0x1UL << EXTI_EMR2_EM44_Pos)               /*!< 0x00001000 */

+#define EXTI_EMR2_EM44             EXTI_EMR2_EM44_Msk                          /*!< Event Mask on line 44 */

+#define EXTI_EMR2_EM46_Pos         (14U)

+#define EXTI_EMR2_EM46_Msk         (0x1UL << EXTI_EMR2_EM46_Pos)               /*!< 0x00004000 */

+#define EXTI_EMR2_EM46             EXTI_EMR2_EM46_Msk                          /*!< Event Mask on line 46 */

+#define EXTI_EMR2_EM47_Pos         (15U)

+#define EXTI_EMR2_EM47_Msk         (0x1UL << EXTI_EMR2_EM47_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR2_EM47             EXTI_EMR2_EM47_Msk                          /*!< Event Mask on line 47 */

+#define EXTI_EMR2_EM48_Pos         (16U)

+#define EXTI_EMR2_EM48_Msk         (0x1UL << EXTI_EMR2_EM48_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR2_EM48             EXTI_EMR2_EM48_Msk                          /*!< Event Mask on line 48 */

+#define EXTI_EMR2_EM49_Pos         (17U)

+#define EXTI_EMR2_EM49_Msk         (0x1UL << EXTI_EMR2_EM49_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR2_EM49             EXTI_EMR2_EM49_Msk                          /*!< Event Mask on line 49 */

+#define EXTI_EMR2_EM50_Pos         (18U)

+#define EXTI_EMR2_EM50_Msk         (0x1UL << EXTI_EMR2_EM50_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR2_EM50             EXTI_EMR2_EM50_Msk                          /*!< Event Mask on line 50 */

+#define EXTI_EMR2_EM51_Pos         (19U)

+#define EXTI_EMR2_EM51_Msk         (0x1UL << EXTI_EMR2_EM51_Pos)               /*!< 0x00080000 */

+#define EXTI_EMR2_EM51             EXTI_EMR2_EM51_Msk                          /*!< Event Mask on line 51 */

+#define EXTI_EMR2_EM52_Pos         (20U)

+#define EXTI_EMR2_EM52_Msk         (0x1UL << EXTI_EMR2_EM52_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR2_EM52             EXTI_EMR2_EM52_Msk                          /*!< Event Mask on line 52 */

+#define EXTI_EMR2_EM53_Pos         (21U)

+#define EXTI_EMR2_EM53_Msk         (0x1UL << EXTI_EMR2_EM53_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR2_EM53             EXTI_EMR2_EM53_Msk                          /*!< Event Mask on line 53 */

+#define EXTI_EMR2_EM54_Pos         (22U)

+#define EXTI_EMR2_EM54_Msk         (0x1UL << EXTI_EMR2_EM54_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR2_EM54             EXTI_EMR2_EM54_Msk                          /*!< Event Mask on line 54 */

+#define EXTI_EMR2_EM55_Pos         (23U)

+#define EXTI_EMR2_EM55_Msk         (0x1UL << EXTI_EMR2_EM55_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR2_EM55             EXTI_EMR2_EM55_Msk                          /*!< Event Mask on line 55 */

+#define EXTI_EMR2_EM56_Pos         (24U)

+#define EXTI_EMR2_EM56_Msk         (0x1UL << EXTI_EMR2_EM56_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR2_EM56             EXTI_EMR2_EM56_Msk                          /*!< Event Mask on line 56 */

+#define EXTI_EMR2_EM57_Pos         (25U)

+#define EXTI_EMR2_EM57_Msk         (0x1UL << EXTI_EMR2_EM57_Pos)               /*!< 0x02000000 */

+#define EXTI_EMR2_EM57             EXTI_EMR2_EM57_Msk                          /*!< Event Mask on line 57 */

+#define EXTI_EMR2_EM58_Pos         (26U)

+#define EXTI_EMR2_EM58_Msk         (0x1UL << EXTI_EMR2_EM58_Pos)               /*!< 0x04000000 */

+#define EXTI_EMR2_EM58             EXTI_EMR2_EM58_Msk                          /*!< Event Mask on line 58 */

+#define EXTI_EMR2_EM59_Pos         (27U)

+#define EXTI_EMR2_EM59_Msk         (0x1UL << EXTI_EMR2_EM59_Pos)               /*!< 0x08000000 */

+#define EXTI_EMR2_EM59             EXTI_EMR2_EM59_Msk                          /*!< Event Mask on line 59 */

+#define EXTI_EMR2_EM60_Pos         (28U)

+#define EXTI_EMR2_EM60_Msk         (0x1UL << EXTI_EMR2_EM60_Pos)               /*!< 0x10000000 */

+#define EXTI_EMR2_EM60             EXTI_EMR2_EM60_Msk                          /*!< Event Mask on line 60 */

+#define EXTI_EMR2_EM61_Pos         (29U)

+#define EXTI_EMR2_EM61_Msk         (0x1UL << EXTI_EMR2_EM61_Pos)               /*!< 0x20000000 */

+#define EXTI_EMR2_EM61             EXTI_EMR2_EM61_Msk                          /*!< Event Mask on line 61 */

+#define EXTI_EMR2_EM62_Pos         (30U)

+#define EXTI_EMR2_EM62_Msk         (0x1UL << EXTI_EMR2_EM62_Pos)               /*!< 0x40000000 */

+#define EXTI_EMR2_EM62             EXTI_EMR2_EM62_Msk                          /*!< Event Mask on line 62 */

+#define EXTI_EMR2_EM63_Pos         (31U)

+#define EXTI_EMR2_EM63_Msk         (0x1UL << EXTI_EMR2_EM63_Pos)               /*!< 0x80000000 */

+#define EXTI_EMR2_EM63             EXTI_EMR2_EM63_Msk                          /*!< Event Mask on line 63 */

+

+/*******************  Bit definition for EXTI_PR2 register  ********************/

+#define EXTI_PR2_PR_Pos            (17U)

+#define EXTI_PR2_PR_Msk            (0x5UL << EXTI_PR2_PR_Pos)                  /*!< 0x000A0000 */

+#define EXTI_PR2_PR                EXTI_PR2_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR2_PR49_Pos          (17U)

+#define EXTI_PR2_PR49_Msk          (0x1UL << EXTI_PR2_PR49_Pos)                /*!< 0x00020000 */

+#define EXTI_PR2_PR49              EXTI_PR2_PR49_Msk                           /*!< Pending bit for line 49 */

+#define EXTI_PR2_PR51_Pos          (19U)

+#define EXTI_PR2_PR51_Msk          (0x1UL << EXTI_PR2_PR51_Pos)                /*!< 0x00080000 */

+#define EXTI_PR2_PR51              EXTI_PR2_PR51_Msk                           /*!< Pending bit for line 51 */

+

+/*******************  Bit definition for EXTI_IMR3 register  *******************/

+#define EXTI_IMR3_IM_Pos           (0U)

+#define EXTI_IMR3_IM_Msk           (0x00F5FFFFUL << EXTI_IMR3_IM_Pos)          /*!< 0x00F5FFFF */

+#define EXTI_IMR3_IM               EXTI_IMR3_IM_Msk                            /*!< Interrupt Mask */

+#define EXTI_IMR3_IM64_Pos         (0U)

+#define EXTI_IMR3_IM64_Msk         (0x1UL << EXTI_IMR3_IM64_Pos)               /*!< 0x00000001 */

+#define EXTI_IMR3_IM64             EXTI_IMR3_IM64_Msk                          /*!< Interrupt Mask on line 64 */

+#define EXTI_IMR3_IM65_Pos         (1U)

+#define EXTI_IMR3_IM65_Msk         (0x1UL << EXTI_IMR3_IM65_Pos)               /*!< 0x00000002 */

+#define EXTI_IMR3_IM65             EXTI_IMR3_IM65_Msk                          /*!< Interrupt Mask on line 65 */

+#define EXTI_IMR3_IM66_Pos         (2U)

+#define EXTI_IMR3_IM66_Msk         (0x1UL << EXTI_IMR3_IM66_Pos)               /*!< 0x00000004 */

+#define EXTI_IMR3_IM66             EXTI_IMR3_IM66_Msk                          /*!< Interrupt Mask on line 66 */

+#define EXTI_IMR3_IM67_Pos         (3U)

+#define EXTI_IMR3_IM67_Msk         (0x1UL << EXTI_IMR3_IM67_Pos)               /*!< 0x00000008 */

+#define EXTI_IMR3_IM67             EXTI_IMR3_IM67_Msk                          /*!< Interrupt Mask on line 67 */

+#define EXTI_IMR3_IM68_Pos         (4U)

+#define EXTI_IMR3_IM68_Msk         (0x1UL << EXTI_IMR3_IM68_Pos)               /*!< 0x00000010 */

+#define EXTI_IMR3_IM68             EXTI_IMR3_IM68_Msk                          /*!< Interrupt Mask on line 68 */

+#define EXTI_IMR3_IM69_Pos         (5U)

+#define EXTI_IMR3_IM69_Msk         (0x1UL << EXTI_IMR3_IM69_Pos)               /*!< 0x00000020 */

+#define EXTI_IMR3_IM69             EXTI_IMR3_IM69_Msk                          /*!< Interrupt Mask on line 69 */

+#define EXTI_IMR3_IM70_Pos         (6U)

+#define EXTI_IMR3_IM70_Msk         (0x1UL << EXTI_IMR3_IM70_Pos)               /*!< 0x00000040 */

+#define EXTI_IMR3_IM70             EXTI_IMR3_IM70_Msk                          /*!< Interrupt Mask on line 70 */

+#define EXTI_IMR3_IM71_Pos         (7U)

+#define EXTI_IMR3_IM71_Msk         (0x1UL << EXTI_IMR3_IM71_Pos)               /*!< 0x00000080 */

+#define EXTI_IMR3_IM71             EXTI_IMR3_IM71_Msk                          /*!< Interrupt Mask on line 71 */

+#define EXTI_IMR3_IM72_Pos         (8U)

+#define EXTI_IMR3_IM72_Msk         (0x1UL << EXTI_IMR3_IM72_Pos)               /*!< 0x00000100 */

+#define EXTI_IMR3_IM72             EXTI_IMR3_IM72_Msk                          /*!< Interrupt Mask on line 72 */

+#define EXTI_IMR3_IM73_Pos         (9U)

+#define EXTI_IMR3_IM73_Msk         (0x1UL << EXTI_IMR3_IM73_Pos)               /*!< 0x00000200 */

+#define EXTI_IMR3_IM73             EXTI_IMR3_IM73_Msk                          /*!< Interrupt Mask on line 73 */

+#define EXTI_IMR3_IM74_Pos         (10U)

+#define EXTI_IMR3_IM74_Msk         (0x1UL << EXTI_IMR3_IM74_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR3_IM74             EXTI_IMR3_IM74_Msk                          /*!< Interrupt Mask on line 74 */

+#define EXTI_IMR3_IM75_Pos         (11U)

+#define EXTI_IMR3_IM75_Msk         (0x1UL << EXTI_IMR3_IM75_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR3_IM75             EXTI_IMR3_IM75_Msk                          /*!< Interrupt Mask on line 75 */

+#define EXTI_IMR3_IM76_Pos         (12U)

+#define EXTI_IMR3_IM76_Msk         (0x1UL << EXTI_IMR3_IM76_Pos)               /*!< 0x00001000 */

+#define EXTI_IMR3_IM76             EXTI_IMR3_IM76_Msk                          /*!< Interrupt Mask on line 76 */

+#define EXTI_IMR3_IM77_Pos         (13U)

+#define EXTI_IMR3_IM77_Msk         (0x1UL << EXTI_IMR3_IM77_Pos)               /*!< 0x00002000 */

+#define EXTI_IMR3_IM77             EXTI_IMR3_IM77_Msk                          /*!< Interrupt Mask on line 77 */

+#define EXTI_IMR3_IM78_Pos         (14U)

+#define EXTI_IMR3_IM78_Msk         (0x1UL << EXTI_IMR3_IM78_Pos)               /*!< 0x00004000 */

+#define EXTI_IMR3_IM78             EXTI_IMR3_IM78_Msk                          /*!< Interrupt Mask on line 78 */

+#define EXTI_IMR3_IM79_Pos         (15U)

+#define EXTI_IMR3_IM79_Msk         (0x1UL << EXTI_IMR3_IM79_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR3_IM79             EXTI_IMR3_IM79_Msk                          /*!< Interrupt Mask on line 79 */

+#define EXTI_IMR3_IM80_Pos         (16U)

+#define EXTI_IMR3_IM80_Msk         (0x1UL << EXTI_IMR3_IM80_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR3_IM80             EXTI_IMR3_IM80_Msk                          /*!< Interrupt Mask on line 80 */

+#define EXTI_IMR3_IM82_Pos         (18U)

+#define EXTI_IMR3_IM82_Msk         (0x1UL << EXTI_IMR3_IM82_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR3_IM82             EXTI_IMR3_IM82_Msk                          /*!< Interrupt Mask on line 82 */

+#define EXTI_IMR3_IM84_Pos         (20U)

+#define EXTI_IMR3_IM84_Msk         (0x1UL << EXTI_IMR3_IM84_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR3_IM84             EXTI_IMR3_IM84_Msk                          /*!< Interrupt Mask on line 84 */

+#define EXTI_IMR3_IM85_Pos         (21U)

+#define EXTI_IMR3_IM85_Msk         (0x1UL << EXTI_IMR3_IM85_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR3_IM85             EXTI_IMR3_IM85_Msk                          /*!< Interrupt Mask on line 85 */

+#define EXTI_IMR3_IM86_Pos         (22U)

+#define EXTI_IMR3_IM86_Msk         (0x1UL << EXTI_IMR3_IM86_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR3_IM86             EXTI_IMR3_IM86_Msk                          /*!< Interrupt Mask on line 86 */

+#define EXTI_IMR3_IM87_Pos         (23U)

+#define EXTI_IMR3_IM87_Msk         (0x1UL << EXTI_IMR3_IM87_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR3_IM87             EXTI_IMR3_IM87_Msk                          /*!< Interrupt Mask on line 87 */

+

+

+/*******************  Bit definition for EXTI_EMR3 register  *******************/

+#define EXTI_EMR3_EM_Pos           (0U)

+#define EXTI_EMR3_EM_Msk           (0x00F5FFFFUL << EXTI_EMR3_EM_Pos)          /*!< 0x00F5FFFF */

+#define EXTI_EMR3_EM               EXTI_EMR3_EM_Msk                            /*!< Event Mask           */

+#define EXTI_EMR3_EM64_Pos         (0U)

+#define EXTI_EMR3_EM64_Msk         (0x1UL << EXTI_EMR3_EM64_Pos)               /*!< 0x00000001 */

+#define EXTI_EMR3_EM64             EXTI_EMR3_EM64_Msk                          /*!< Event Mask on line 64*/

+#define EXTI_EMR3_EM65_Pos         (1U)

+#define EXTI_EMR3_EM65_Msk         (0x1UL << EXTI_EMR3_EM65_Pos)               /*!< 0x00000002 */

+#define EXTI_EMR3_EM65             EXTI_EMR3_EM65_Msk                          /*!< Event Mask on line 65*/

+#define EXTI_EMR3_EM66_Pos         (2U)

+#define EXTI_EMR3_EM66_Msk         (0x1UL << EXTI_EMR3_EM66_Pos)               /*!< 0x00000004 */

+#define EXTI_EMR3_EM66             EXTI_EMR3_EM66_Msk                          /*!< Event Mask on line 66*/

+#define EXTI_EMR3_EM67_Pos         (3U)

+#define EXTI_EMR3_EM67_Msk         (0x1UL << EXTI_EMR3_EM67_Pos)               /*!< 0x00000008 */

+#define EXTI_EMR3_EM67             EXTI_EMR3_EM67_Msk                          /*!< Event Mask on line 67*/

+#define EXTI_EMR3_EM68_Pos         (4U)

+#define EXTI_EMR3_EM68_Msk         (0x1UL << EXTI_EMR3_EM68_Pos)               /*!< 0x00000010 */

+#define EXTI_EMR3_EM68             EXTI_EMR3_EM68_Msk                          /*!< Event Mask on line 68*/

+#define EXTI_EMR3_EM69_Pos         (5U)

+#define EXTI_EMR3_EM69_Msk         (0x1UL << EXTI_EMR3_EM69_Pos)               /*!< 0x00000020 */

+#define EXTI_EMR3_EM69             EXTI_EMR3_EM69_Msk                          /*!< Event Mask on line 69*/

+#define EXTI_EMR3_EM70_Pos         (6U)

+#define EXTI_EMR3_EM70_Msk         (0x1UL << EXTI_EMR3_EM70_Pos)               /*!< 0x00000040 */

+#define EXTI_EMR3_EM70             EXTI_EMR3_EM70_Msk                          /*!< Event Mask on line 70*/

+#define EXTI_EMR3_EM71_Pos         (7U)

+#define EXTI_EMR3_EM71_Msk         (0x1UL << EXTI_EMR3_EM71_Pos)               /*!< 0x00000080 */

+#define EXTI_EMR3_EM71             EXTI_EMR3_EM71_Msk                          /*!< Event Mask on line 71*/

+#define EXTI_EMR3_EM72_Pos         (8U)

+#define EXTI_EMR3_EM72_Msk         (0x1UL << EXTI_EMR3_EM72_Pos)               /*!< 0x00000100 */

+#define EXTI_EMR3_EM72             EXTI_EMR3_EM72_Msk                          /*!< Event Mask on line 72*/

+#define EXTI_EMR3_EM73_Pos         (9U)

+#define EXTI_EMR3_EM73_Msk         (0x1UL << EXTI_EMR3_EM73_Pos)               /*!< 0x00000200 */

+#define EXTI_EMR3_EM73             EXTI_EMR3_EM73_Msk                          /*!< Event Mask on line 73*/

+#define EXTI_EMR3_EM74_Pos         (10U)

+#define EXTI_EMR3_EM74_Msk         (0x1UL << EXTI_EMR3_EM74_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR3_EM74             EXTI_EMR3_EM74_Msk                          /*!< Event Mask on line 74 */

+#define EXTI_EMR3_EM75_Pos         (11U)

+#define EXTI_EMR3_EM75_Msk         (0x1UL << EXTI_EMR3_EM75_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR3_EM75             EXTI_EMR3_EM75_Msk                          /*!< Event Mask on line 75 */

+#define EXTI_EMR3_EM76_Pos         (12U)

+#define EXTI_EMR3_EM76_Msk         (0x1UL << EXTI_EMR3_EM76_Pos)               /*!< 0x00001000 */

+#define EXTI_EMR3_EM76             EXTI_EMR3_EM76_Msk                          /*!< Event Mask on line 76 */

+#define EXTI_EMR3_EM77_Pos         (13U)

+#define EXTI_EMR3_EM77_Msk         (0x1UL << EXTI_EMR3_EM77_Pos)               /*!< 0x00002000 */

+#define EXTI_EMR3_EM77             EXTI_EMR3_EM77_Msk                          /*!< Event Mask on line 77 */

+#define EXTI_EMR3_EM78_Pos         (14U)

+#define EXTI_EMR3_EM78_Msk         (0x1UL << EXTI_EMR3_EM78_Pos)               /*!< 0x00004000 */

+#define EXTI_EMR3_EM78             EXTI_EMR3_EM78_Msk                          /*!< Event Mask on line 78 */

+#define EXTI_EMR3_EM79_Pos         (15U)

+#define EXTI_EMR3_EM79_Msk         (0x1UL << EXTI_EMR3_EM79_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR3_EM79             EXTI_EMR3_EM79_Msk                          /*!< Event Mask on line 79 */

+#define EXTI_EMR3_EM80_Pos         (16U)

+#define EXTI_EMR3_EM80_Msk         (0x1UL << EXTI_EMR3_EM80_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR3_EM80             EXTI_EMR3_EM80_Msk                          /*!< Event Mask on line 80 */

+#define EXTI_EMR3_EM81_Pos         (17U)

+#define EXTI_EMR3_EM81_Msk         (0x1UL << EXTI_EMR3_EM81_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR3_EM81             EXTI_EMR3_EM81_Msk                          /*!< Event Mask on line 81 */

+#define EXTI_EMR3_EM82_Pos         (18U)

+#define EXTI_EMR3_EM82_Msk         (0x1UL << EXTI_EMR3_EM82_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR3_EM82             EXTI_EMR3_EM82_Msk                          /*!< Event Mask on line 82 */

+#define EXTI_EMR3_EM84_Pos         (20U)

+#define EXTI_EMR3_EM84_Msk         (0x1UL << EXTI_EMR3_EM84_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR3_EM84             EXTI_EMR3_EM84_Msk                          /*!< Event Mask on line 84 */

+#define EXTI_EMR3_EM85_Pos         (21U)

+#define EXTI_EMR3_EM85_Msk         (0x1UL << EXTI_EMR3_EM85_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR3_EM85             EXTI_EMR3_EM85_Msk                          /*!< Event Mask on line 85 */

+#define EXTI_EMR3_EM86_Pos         (22U)

+#define EXTI_EMR3_EM86_Msk         (0x1UL << EXTI_EMR3_EM86_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR3_EM86             EXTI_EMR3_EM86_Msk                          /*!< Event Mask on line 86 */

+#define EXTI_EMR3_EM87_Pos         (23U)

+#define EXTI_EMR3_EM87_Msk         (0x1UL << EXTI_EMR3_EM87_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR3_EM87             EXTI_EMR3_EM87_Msk                          /*!< Event Mask on line 87 */

+

+/*******************  Bit definition for EXTI_PR3 register  ********************/

+#define EXTI_PR3_PR_Pos            (18U)

+#define EXTI_PR3_PR_Msk            (0x1DUL << EXTI_PR3_PR_Pos)                 /*!< 0x00740000 */

+#define EXTI_PR3_PR                EXTI_PR3_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR3_PR82_Pos          (18U)

+#define EXTI_PR3_PR82_Msk          (0x1UL << EXTI_PR3_PR82_Pos)                /*!< 0x00040000 */

+#define EXTI_PR3_PR82              EXTI_PR3_PR82_Msk                           /*!< Pending bit for line 82 */

+#define EXTI_PR3_PR84_Pos          (20U)

+#define EXTI_PR3_PR84_Msk          (0x1UL << EXTI_PR3_PR84_Pos)                /*!< 0x00100000 */

+#define EXTI_PR3_PR84              EXTI_PR3_PR84_Msk                           /*!< Pending bit for line 84 */

+#define EXTI_PR3_PR85_Pos          (21U)

+#define EXTI_PR3_PR85_Msk          (0x1UL << EXTI_PR3_PR85_Pos)                /*!< 0x00200000 */

+#define EXTI_PR3_PR85              EXTI_PR3_PR85_Msk                           /*!< Pending bit for line 85 */

+#define EXTI_PR3_PR86_Pos          (22U)

+#define EXTI_PR3_PR86_Msk          (0x1UL << EXTI_PR3_PR86_Pos)                /*!< 0x00400000 */

+#define EXTI_PR3_PR86              EXTI_PR3_PR86_Msk                           /*!< Pending bit for line 86 */

+/******************************************************************************/

+/*                                                                            */

+/*                                    FLASH                                   */

+/*                                                                            */

+/******************************************************************************/

+/*

+* @brief FLASH Global Defines

+*/

+#define FLASH_SECTOR_TOTAL                   8U                    /* 8 sectors */

+#define FLASH_SIZE                           0x200000UL            /* 2 MB   */

+#define FLASH_BANK_SIZE                      (FLASH_SIZE >> 1)     /* 1 MB   */

+#define FLASH_SECTOR_SIZE                    0x00020000UL          /* 128 KB */

+#define FLASH_LATENCY_DEFAULT                FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */

+#define FLASH_NB_32BITWORD_IN_FLASHWORD      8U                    /* 256 bits */

+#define DUAL_BANK                                                  /* Dual-bank Flash */

+

+/*******************  Bits definition for FLASH_ACR register  **********************/

+#define FLASH_ACR_LATENCY_Pos                (0U)

+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */

+#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */

+#define FLASH_ACR_LATENCY_0WS                (0x00000000UL)

+#define FLASH_ACR_LATENCY_1WS                (0x00000001UL)

+#define FLASH_ACR_LATENCY_2WS                (0x00000002UL)

+#define FLASH_ACR_LATENCY_3WS                (0x00000003UL)

+#define FLASH_ACR_LATENCY_4WS                (0x00000004UL)

+#define FLASH_ACR_LATENCY_5WS                (0x00000005UL)

+#define FLASH_ACR_LATENCY_6WS                (0x00000006UL)

+#define FLASH_ACR_LATENCY_7WS                (0x00000007UL)

+#define FLASH_ACR_LATENCY_8WS                (0x00000008UL)

+#define FLASH_ACR_LATENCY_9WS                (0x00000009UL)

+#define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)

+#define FLASH_ACR_LATENCY_11WS               (0x0000000BUL)

+#define FLASH_ACR_LATENCY_12WS               (0x0000000CUL)

+#define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)

+#define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)

+#define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)

+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)

+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */

+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */

+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */

+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */

+

+/*******************  Bits definition for FLASH_CR register  ***********************/

+#define FLASH_CR_LOCK_Pos                    (0U)

+#define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */

+#define FLASH_CR_LOCK                        FLASH_CR_LOCK_Msk                 /*!< Configuration lock bit */

+#define FLASH_CR_PG_Pos                      (1U)

+#define FLASH_CR_PG_Msk                      (0x1UL << FLASH_CR_PG_Pos)        /*!< 0x00000002 */

+#define FLASH_CR_PG                          FLASH_CR_PG_Msk                   /*!< Internal buffer control bit */

+#define FLASH_CR_SER_Pos                     (2U)

+#define FLASH_CR_SER_Msk                     (0x1UL << FLASH_CR_SER_Pos)       /*!< 0x00000004 */

+#define FLASH_CR_SER                         FLASH_CR_SER_Msk                  /*!< Sector erase request */

+#define FLASH_CR_BER_Pos                     (3U)

+#define FLASH_CR_BER_Msk                     (0x1UL << FLASH_CR_BER_Pos)       /*!< 0x00000008 */

+#define FLASH_CR_BER                         FLASH_CR_BER_Msk                  /*!< Bank erase request */

+#define FLASH_CR_PSIZE_Pos                   (4U)

+#define FLASH_CR_PSIZE_Msk                   (0x3UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000030 */

+#define FLASH_CR_PSIZE                       FLASH_CR_PSIZE_Msk                /*!< Program size */

+#define FLASH_CR_PSIZE_0                     (0x1UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000010 */

+#define FLASH_CR_PSIZE_1                     (0x2UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000020 */

+#define FLASH_CR_FW_Pos                      (6U)

+#define FLASH_CR_FW_Msk                      (0x1UL << FLASH_CR_FW_Pos)        /*!< 0x00000040 */

+#define FLASH_CR_FW                          FLASH_CR_FW_Msk                   /*!< Write forcing control bit */

+#define FLASH_CR_START_Pos                   (7U)

+#define FLASH_CR_START_Msk                   (0x1UL << FLASH_CR_START_Pos)     /*!< 0x00000080 */

+#define FLASH_CR_START                       FLASH_CR_START_Msk                /*!< Erase start control bit */

+#define FLASH_CR_SNB_Pos                     (8U)

+#define FLASH_CR_SNB_Msk                     (0x7UL << FLASH_CR_SNB_Pos)       /*!< 0x00000700 */

+#define FLASH_CR_SNB                         FLASH_CR_SNB_Msk                  /*!< Sector erase selection number */

+#define FLASH_CR_SNB_0                       (0x1UL << FLASH_CR_SNB_Pos)       /*!< 0x00000100 */

+#define FLASH_CR_SNB_1                       (0x2UL << FLASH_CR_SNB_Pos)       /*!< 0x00000200 */

+#define FLASH_CR_SNB_2                       (0x4UL << FLASH_CR_SNB_Pos)       /*!< 0x00000400 */

+#define FLASH_CR_CRC_EN_Pos                  (15U)

+#define FLASH_CR_CRC_EN_Msk                  (0x1UL << FLASH_CR_CRC_EN_Pos)    /*!< 0x00008000 */

+#define FLASH_CR_CRC_EN                      FLASH_CR_CRC_EN_Msk               /*!< CRC control bit */

+#define FLASH_CR_EOPIE_Pos                   (16U)

+#define FLASH_CR_EOPIE_Msk                   (0x1UL << FLASH_CR_EOPIE_Pos)     /*!< 0x00010000 */

+#define FLASH_CR_EOPIE                       FLASH_CR_EOPIE_Msk                /*!< End-of-program interrupt control bit */

+#define FLASH_CR_WRPERRIE_Pos                (17U)

+#define FLASH_CR_WRPERRIE_Msk                (0x1UL << FLASH_CR_WRPERRIE_Pos)  /*!< 0x00020000 */

+#define FLASH_CR_WRPERRIE                    FLASH_CR_WRPERRIE_Msk             /*!< Write protection error interrupt enable bit */

+#define FLASH_CR_PGSERRIE_Pos                (18U)

+#define FLASH_CR_PGSERRIE_Msk                (0x1UL << FLASH_CR_PGSERRIE_Pos)  /*!< 0x00040000 */

+#define FLASH_CR_PGSERRIE                    FLASH_CR_PGSERRIE_Msk             /*!< Programming sequence error interrupt enable bit */

+#define FLASH_CR_STRBERRIE_Pos               (19U)

+#define FLASH_CR_STRBERRIE_Msk               (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */

+#define FLASH_CR_STRBERRIE                   FLASH_CR_STRBERRIE_Msk            /*!< Strobe error interrupt enable bit */

+#define FLASH_CR_INCERRIE_Pos                (21U)

+#define FLASH_CR_INCERRIE_Msk                (0x1UL << FLASH_CR_INCERRIE_Pos)  /*!< 0x00200000 */

+#define FLASH_CR_INCERRIE                    FLASH_CR_INCERRIE_Msk             /*!< Inconsistency error interrupt enable bit */

+#define FLASH_CR_OPERRIE_Pos                 (22U)

+#define FLASH_CR_OPERRIE_Msk                 (0x1UL << FLASH_CR_OPERRIE_Pos)   /*!< 0x00400000 */

+#define FLASH_CR_OPERRIE                     FLASH_CR_OPERRIE_Msk              /*!< Write/erase error interrupt enable bit */

+#define FLASH_CR_RDPERRIE_Pos                (23U)

+#define FLASH_CR_RDPERRIE_Msk                (0x1UL << FLASH_CR_RDPERRIE_Pos)  /*!< 0x00800000 */

+#define FLASH_CR_RDPERRIE                    FLASH_CR_RDPERRIE_Msk             /*!< Read protection error interrupt enable bit */

+#define FLASH_CR_RDSERRIE_Pos                (24U)

+#define FLASH_CR_RDSERRIE_Msk                (0x1UL << FLASH_CR_RDSERRIE_Pos)  /*!< 0x01000000 */

+#define FLASH_CR_RDSERRIE                    FLASH_CR_RDSERRIE_Msk             /*!< Secure error interrupt enable bit */

+#define FLASH_CR_SNECCERRIE_Pos              (25U)

+#define FLASH_CR_SNECCERRIE_Msk              (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */

+#define FLASH_CR_SNECCERRIE                  FLASH_CR_SNECCERRIE_Msk            /*!< ECC single correction error interrupt enable bit */

+#define FLASH_CR_DBECCERRIE_Pos              (26U)

+#define FLASH_CR_DBECCERRIE_Msk              (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */

+#define FLASH_CR_DBECCERRIE                  FLASH_CR_DBECCERRIE_Msk            /*!< ECC double detection error interrupt enable bit */

+#define FLASH_CR_CRCENDIE_Pos                (27U)

+#define FLASH_CR_CRCENDIE_Msk                (0x1UL << FLASH_CR_CRCENDIE_Pos)  /*!< 0x08000000 */

+#define FLASH_CR_CRCENDIE                    FLASH_CR_CRCENDIE_Msk             /*!< CRC end of calculation interrupt enable bit */

+#define FLASH_CR_CRCRDERRIE_Pos              (28U)

+#define FLASH_CR_CRCRDERRIE_Msk              (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */

+#define FLASH_CR_CRCRDERRIE                  FLASH_CR_CRCRDERRIE_Msk            /*!< CRC read error interrupt enable bit */

+

+/*******************  Bits definition for FLASH_SR register  ***********************/

+#define FLASH_SR_BSY_Pos                     (0U)

+#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)       /*!< 0x00000001 */

+#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy flag */

+#define FLASH_SR_WBNE_Pos                    (1U)

+#define FLASH_SR_WBNE_Msk                    (0x1UL << FLASH_SR_WBNE_Pos)      /*!< 0x00000002 */

+#define FLASH_SR_WBNE                        FLASH_SR_WBNE_Msk                 /*!< Write buffer not empty flag */

+#define FLASH_SR_QW_Pos                      (2U)

+#define FLASH_SR_QW_Msk                      (0x1UL << FLASH_SR_QW_Pos)        /*!< 0x00000004 */

+#define FLASH_SR_QW                          FLASH_SR_QW_Msk                   /*!< Wait queue flag */

+#define FLASH_SR_CRC_BUSY_Pos                (3U)

+#define FLASH_SR_CRC_BUSY_Msk                (0x1UL << FLASH_SR_CRC_BUSY_Pos)  /*!< 0x00000008 */

+#define FLASH_SR_CRC_BUSY                    FLASH_SR_CRC_BUSY_Msk             /*!< CRC busy flag */

+#define FLASH_SR_EOP_Pos                     (16U)

+#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)       /*!< 0x00010000 */

+#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End-of-program flag */

+#define FLASH_SR_WRPERR_Pos                  (17U)

+#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)    /*!< 0x00020000 */

+#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protection error flag */

+#define FLASH_SR_PGSERR_Pos                  (18U)

+#define FLASH_SR_PGSERR_Msk                  (0x1UL << FLASH_SR_PGSERR_Pos)    /*!< 0x00040000 */

+#define FLASH_SR_PGSERR                      FLASH_SR_PGSERR_Msk               /*!< Programming sequence error flag */

+#define FLASH_SR_STRBERR_Pos                 (19U)

+#define FLASH_SR_STRBERR_Msk                 (0x1UL << FLASH_SR_STRBERR_Pos)   /*!< 0x00080000 */

+#define FLASH_SR_STRBERR                     FLASH_SR_STRBERR_Msk              /*!< Strobe error flag */

+#define FLASH_SR_INCERR_Pos                  (21U)

+#define FLASH_SR_INCERR_Msk                  (0x1UL << FLASH_SR_INCERR_Pos)    /*!< 0x00200000 */

+#define FLASH_SR_INCERR                      FLASH_SR_INCERR_Msk               /*!< Inconsistency error flag */

+#define FLASH_SR_OPERR_Pos                   (22U)

+#define FLASH_SR_OPERR_Msk                   (0x1UL << FLASH_SR_OPERR_Pos)     /*!< 0x00400000 */

+#define FLASH_SR_OPERR                       FLASH_SR_OPERR_Msk                /*!< Write/erase error flag */

+#define FLASH_SR_RDPERR_Pos                  (23U)

+#define FLASH_SR_RDPERR_Msk                  (0x1UL << FLASH_SR_RDPERR_Pos)    /*!< 0x00800000 */

+#define FLASH_SR_RDPERR                      FLASH_SR_RDPERR_Msk               /*!< Read protection error flag */

+#define FLASH_SR_RDSERR_Pos                  (24U)

+#define FLASH_SR_RDSERR_Msk                  (0x1UL << FLASH_SR_RDSERR_Pos)    /*!< 0x01000000 */

+#define FLASH_SR_RDSERR                      FLASH_SR_RDSERR_Msk               /*!< Secure error flag */

+#define FLASH_SR_SNECCERR_Pos                (25U)

+#define FLASH_SR_SNECCERR_Msk                (0x1UL << FLASH_SR_SNECCERR_Pos)  /*!< 0x02000000 */

+#define FLASH_SR_SNECCERR                    FLASH_SR_SNECCERR_Msk             /*!< Single correction error flag */

+#define FLASH_SR_DBECCERR_Pos                (26U)

+#define FLASH_SR_DBECCERR_Msk                (0x1UL << FLASH_SR_DBECCERR_Pos)  /*!< 0x04000000 */

+#define FLASH_SR_DBECCERR                    FLASH_SR_DBECCERR_Msk             /*!< ECC double detection error flag */

+#define FLASH_SR_CRCEND_Pos                  (27U)

+#define FLASH_SR_CRCEND_Msk                  (0x1UL << FLASH_SR_CRCEND_Pos)    /*!< 0x08000000 */

+#define FLASH_SR_CRCEND                      FLASH_SR_CRCEND_Msk               /*!< CRC end of calculation flag */

+#define FLASH_SR_CRCRDERR_Pos                (28U)

+#define FLASH_SR_CRCRDERR_Msk                (0x1UL << FLASH_SR_CRCRDERR_Pos)  /*!< 0x10000000 */

+#define FLASH_SR_CRCRDERR                    FLASH_SR_CRCRDERR_Msk             /*!< CRC read error flag */

+

+/*******************  Bits definition for FLASH_CCR register  *******************/

+#define FLASH_CCR_CLR_EOP_Pos                (16U)

+#define FLASH_CCR_CLR_EOP_Msk                (0x1UL << FLASH_CCR_CLR_EOP_Pos)  /*!< 0x00010000 */

+#define FLASH_CCR_CLR_EOP                    FLASH_CCR_CLR_EOP_Msk             /*!< EOP flag clear bit */

+#define FLASH_CCR_CLR_WRPERR_Pos             (17U)

+#define FLASH_CCR_CLR_WRPERR_Msk             (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */

+#define FLASH_CCR_CLR_WRPERR                 FLASH_CCR_CLR_WRPERR_Msk            /*!< WRPERR flag clear bit */

+#define FLASH_CCR_CLR_PGSERR_Pos             (18U)

+#define FLASH_CCR_CLR_PGSERR_Msk             (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */

+#define FLASH_CCR_CLR_PGSERR                 FLASH_CCR_CLR_PGSERR_Msk            /*!< PGSERR flag clear bit */

+#define FLASH_CCR_CLR_STRBERR_Pos            (19U)

+#define FLASH_CCR_CLR_STRBERR_Msk            (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */

+#define FLASH_CCR_CLR_STRBERR                FLASH_CCR_CLR_STRBERR_Msk            /*!< STRBERR flag clear bit */

+#define FLASH_CCR_CLR_INCERR_Pos             (21U)

+#define FLASH_CCR_CLR_INCERR_Msk             (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */

+#define FLASH_CCR_CLR_INCERR                 FLASH_CCR_CLR_INCERR_Msk            /*!< INCERR flag clear bit */

+#define FLASH_CCR_CLR_OPERR_Pos              (22U)

+#define FLASH_CCR_CLR_OPERR_Msk              (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */

+#define FLASH_CCR_CLR_OPERR                  FLASH_CCR_CLR_OPERR_Msk            /*!< OPERR flag clear bit */

+#define FLASH_CCR_CLR_RDPERR_Pos             (23U)

+#define FLASH_CCR_CLR_RDPERR_Msk             (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */

+#define FLASH_CCR_CLR_RDPERR                 FLASH_CCR_CLR_RDPERR_Msk            /*!< RDPERR flag clear bit */

+#define FLASH_CCR_CLR_RDSERR_Pos             (24U)

+#define FLASH_CCR_CLR_RDSERR_Msk             (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */

+#define FLASH_CCR_CLR_RDSERR                 FLASH_CCR_CLR_RDSERR_Msk            /*!< RDSERR flag clear bit */

+#define FLASH_CCR_CLR_SNECCERR_Pos           (25U)

+#define FLASH_CCR_CLR_SNECCERR_Msk           (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */

+#define FLASH_CCR_CLR_SNECCERR               FLASH_CCR_CLR_SNECCERR_Msk            /*!< SNECCERR flag clear bit */

+#define FLASH_CCR_CLR_DBECCERR_Pos           (26U)

+#define FLASH_CCR_CLR_DBECCERR_Msk           (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */

+#define FLASH_CCR_CLR_DBECCERR               FLASH_CCR_CLR_DBECCERR_Msk            /*!< DBECCERR flag clear bit */

+#define FLASH_CCR_CLR_CRCEND_Pos             (27U)

+#define FLASH_CCR_CLR_CRCEND_Msk             (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */

+#define FLASH_CCR_CLR_CRCEND                 FLASH_CCR_CLR_CRCEND_Msk            /*!< CRCEND flag clear bit */

+#define FLASH_CCR_CLR_CRCRDERR_Pos           (28U)

+#define FLASH_CCR_CLR_CRCRDERR_Msk           (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */

+#define FLASH_CCR_CLR_CRCRDERR               FLASH_CCR_CLR_CRCRDERR_Msk            /*!< CRCRDERR flag clear bit */

+

+/*******************  Bits definition for FLASH_OPTCR register  *******************/

+#define FLASH_OPTCR_OPTLOCK_Pos              (0U)

+#define FLASH_OPTCR_OPTLOCK_Msk              (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)  /*!< 0x00000001 */

+#define FLASH_OPTCR_OPTLOCK                  FLASH_OPTCR_OPTLOCK_Msk             /*!< FLASH_OPTCR lock option configuration bit */

+#define FLASH_OPTCR_OPTSTART_Pos             (1U)

+#define FLASH_OPTCR_OPTSTART_Msk             (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */

+#define FLASH_OPTCR_OPTSTART                 FLASH_OPTCR_OPTSTART_Msk            /*!< Option byte start change option configuration bit */

+#define FLASH_OPTCR_MER_Pos                  (4U)

+#define FLASH_OPTCR_MER_Msk                  (0x1UL << FLASH_OPTCR_MER_Pos)      /*!< 0x00000010 */

+#define FLASH_OPTCR_MER                      FLASH_OPTCR_MER_Msk                 /*!< Mass erase request */

+#define FLASH_OPTCR_OPTCHANGEERRIE_Pos       (30U)

+#define FLASH_OPTCR_OPTCHANGEERRIE_Msk       (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */

+#define FLASH_OPTCR_OPTCHANGEERRIE           FLASH_OPTCR_OPTCHANGEERRIE_Msk            /*!< Option byte change error interrupt enable bit */

+#define FLASH_OPTCR_SWAP_BANK_Pos            (31U)

+#define FLASH_OPTCR_SWAP_BANK_Msk            (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */

+#define FLASH_OPTCR_SWAP_BANK                FLASH_OPTCR_SWAP_BANK_Msk            /*!< Bank swapping option configuration bit */

+

+/*******************  Bits definition for FLASH_OPTSR register  ***************/

+#define FLASH_OPTSR_OPT_BUSY_Pos             (0U)

+#define FLASH_OPTSR_OPT_BUSY_Msk             (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */

+#define FLASH_OPTSR_OPT_BUSY                 FLASH_OPTSR_OPT_BUSY_Msk            /*!< Option byte change ongoing flag */

+#define FLASH_OPTSR_BOR_LEV_Pos              (2U)

+#define FLASH_OPTSR_BOR_LEV_Msk              (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */

+#define FLASH_OPTSR_BOR_LEV                  FLASH_OPTSR_BOR_LEV_Msk            /*!< Brownout level option status bit */

+#define FLASH_OPTSR_BOR_LEV_0                (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */

+#define FLASH_OPTSR_BOR_LEV_1                (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */

+#define FLASH_OPTSR_IWDG1_SW_Pos             (4U)

+#define FLASH_OPTSR_IWDG1_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */

+#define FLASH_OPTSR_IWDG1_SW                 FLASH_OPTSR_IWDG1_SW_Msk            /*!< IWDG1 control mode option status bit */

+#define FLASH_OPTSR_IWDG2_SW_Pos             (5U)

+#define FLASH_OPTSR_IWDG2_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG2_SW_Pos) /*!< 0x00000020 */

+#define FLASH_OPTSR_IWDG2_SW                 FLASH_OPTSR_IWDG2_SW_Msk            /*!< IWDG2 control mode option status bit */

+#define FLASH_OPTSR_NRST_STOP_D1_Pos         (6U)

+#define FLASH_OPTSR_NRST_STOP_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */

+#define FLASH_OPTSR_NRST_STOP_D1             FLASH_OPTSR_NRST_STOP_D1_Msk            /*!< D1 domain DStop entry reset option status bit */

+#define FLASH_OPTSR_NRST_STBY_D1_Pos         (7U)

+#define FLASH_OPTSR_NRST_STBY_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */

+#define FLASH_OPTSR_NRST_STBY_D1             FLASH_OPTSR_NRST_STBY_D1_Msk            /*!< D1 domain DStandby entry reset option status bit */

+#define FLASH_OPTSR_RDP_Pos                  (8U)

+#define FLASH_OPTSR_RDP_Msk                  (0xFFUL << FLASH_OPTSR_RDP_Pos)   /*!< 0x0000FF00 */

+#define FLASH_OPTSR_RDP                      FLASH_OPTSR_RDP_Msk               /*!< Readout protection level option status byte */

+#define FLASH_OPTSR_FZ_IWDG_STOP_Pos         (17U)

+#define FLASH_OPTSR_FZ_IWDG_STOP_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */

+#define FLASH_OPTSR_FZ_IWDG_STOP             FLASH_OPTSR_FZ_IWDG_STOP_Msk            /*!< IWDG Stop mode freeze option status bit */

+#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos         (18U)

+#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */

+#define FLASH_OPTSR_FZ_IWDG_SDBY             FLASH_OPTSR_FZ_IWDG_SDBY_Msk            /*!< IWDG Standby mode freeze option status bit */

+#define FLASH_OPTSR_ST_RAM_SIZE_Pos          (19U)

+#define FLASH_OPTSR_ST_RAM_SIZE_Msk          (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */

+#define FLASH_OPTSR_ST_RAM_SIZE              FLASH_OPTSR_ST_RAM_SIZE_Msk            /*!< ST RAM size option status */

+#define FLASH_OPTSR_ST_RAM_SIZE_0            (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */

+#define FLASH_OPTSR_ST_RAM_SIZE_1            (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */

+#define FLASH_OPTSR_SECURITY_Pos             (21U)

+#define FLASH_OPTSR_SECURITY_Msk             (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */

+#define FLASH_OPTSR_SECURITY                 FLASH_OPTSR_SECURITY_Msk            /*!< Security enable option status bit */

+#define FLASH_OPTSR_BCM4_Pos                 (22U)

+#define FLASH_OPTSR_BCM4_Msk                 (0x1UL << FLASH_OPTSR_BCM4_Pos)   /*!< 0x00400000 */

+#define FLASH_OPTSR_BCM4                     FLASH_OPTSR_BCM4_Msk              /*!< Arm Cortex-M4 boot option status bit */

+#define FLASH_OPTSR_BCM7_Pos                 (23U)

+#define FLASH_OPTSR_BCM7_Msk                 (0x1UL << FLASH_OPTSR_BCM7_Pos)   /*!< 0x00800000 */

+#define FLASH_OPTSR_BCM7                     FLASH_OPTSR_BCM7_Msk              /*!< Arm Cortex-M7 boot option status bit */

+#define FLASH_OPTSR_NRST_STOP_D2_Pos         (24U)

+#define FLASH_OPTSR_NRST_STOP_D2_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D2_Pos) /*!< 0x01000000 */

+#define FLASH_OPTSR_NRST_STOP_D2             FLASH_OPTSR_NRST_STOP_D2_Msk            /*!< D2 domain DStop entry reset option status bit */

+#define FLASH_OPTSR_NRST_STBY_D2_Pos         (25U)

+#define FLASH_OPTSR_NRST_STBY_D2_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D2_Pos) /*!< 0x02000000 */

+#define FLASH_OPTSR_NRST_STBY_D2             FLASH_OPTSR_NRST_STBY_D2_Msk            /*!< D2 domain DStandby entry reset option status bit */

+#define FLASH_OPTSR_IO_HSLV_Pos              (29U)

+#define FLASH_OPTSR_IO_HSLV_Msk              (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */

+#define FLASH_OPTSR_IO_HSLV                  FLASH_OPTSR_IO_HSLV_Msk            /*!< I/O high-speed at low-voltage status bit */

+#define FLASH_OPTSR_OPTCHANGEERR_Pos         (30U)

+#define FLASH_OPTSR_OPTCHANGEERR_Msk         (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */

+#define FLASH_OPTSR_OPTCHANGEERR             FLASH_OPTSR_OPTCHANGEERR_Msk            /*!< Option byte change error flag */

+#define FLASH_OPTSR_SWAP_BANK_OPT_Pos        (31U)

+#define FLASH_OPTSR_SWAP_BANK_OPT_Msk        (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */

+#define FLASH_OPTSR_SWAP_BANK_OPT            FLASH_OPTSR_SWAP_BANK_OPT_Msk            /*!< Bank swapping option status bit */

+

+/*******************  Bits definition for FLASH_OPTCCR register  *******************/

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos    (30U)

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk    (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR        FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk            /*!< OPTCHANGEERR reset bit */

+

+/*******************  Bits definition for FLASH_PRAR register  *********************/

+#define FLASH_PRAR_PROT_AREA_START_Pos       (0U)

+#define FLASH_PRAR_PROT_AREA_START_Msk       (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */

+#define FLASH_PRAR_PROT_AREA_START           FLASH_PRAR_PROT_AREA_START_Msk              /*!< PCROP area start status bits */

+#define FLASH_PRAR_PROT_AREA_END_Pos         (16U)

+#define FLASH_PRAR_PROT_AREA_END_Msk         (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */

+#define FLASH_PRAR_PROT_AREA_END             FLASH_PRAR_PROT_AREA_END_Msk              /*!< PCROP area end status bits */

+#define FLASH_PRAR_DMEP_Pos                  (31U)

+#define FLASH_PRAR_DMEP_Msk                  (0x1UL << FLASH_PRAR_DMEP_Pos)    /*!< 0x80000000 */

+#define FLASH_PRAR_DMEP                      FLASH_PRAR_DMEP_Msk               /*!< PCROP protected erase enable option status bit */

+

+/*******************  Bits definition for FLASH_SCAR register  *********************/

+#define FLASH_SCAR_SEC_AREA_START_Pos        (0U)

+#define FLASH_SCAR_SEC_AREA_START_Msk        (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */

+#define FLASH_SCAR_SEC_AREA_START            FLASH_SCAR_SEC_AREA_START_Msk              /*!< Secure-only area start status bits */

+#define FLASH_SCAR_SEC_AREA_END_Pos          (16U)

+#define FLASH_SCAR_SEC_AREA_END_Msk          (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */

+#define FLASH_SCAR_SEC_AREA_END              FLASH_SCAR_SEC_AREA_END_Msk              /*!< Secure-only area end status bits */

+#define FLASH_SCAR_DMES_Pos                  (31U)

+#define FLASH_SCAR_DMES_Msk                  (0x1UL << FLASH_SCAR_DMES_Pos)    /*!< 0x80000000 */

+#define FLASH_SCAR_DMES                      FLASH_SCAR_DMES_Msk               /*!< Secure access protected erase enable option status bit */

+

+/*******************  Bits definition for FLASH_WPSN register  *********************/

+#define FLASH_WPSN_WRPSN_Pos                 (0U)

+#define FLASH_WPSN_WRPSN_Msk                 (0xFFUL << FLASH_WPSN_WRPSN_Pos)  /*!< 0x000000FF */

+#define FLASH_WPSN_WRPSN                     FLASH_WPSN_WRPSN_Msk              /*!< Sector write protection option status byte */

+

+/*******************  Bits definition for FLASH_BOOT7_CUR register  ****************/

+#define FLASH_BOOT7_BCM7_ADD0_Pos            (0U)

+#define FLASH_BOOT7_BCM7_ADD0_Msk            (0xFFFFUL << FLASH_BOOT7_BCM7_ADD0_Pos) /*!< 0x0000FFFF */

+#define FLASH_BOOT7_BCM7_ADD0                FLASH_BOOT7_BCM7_ADD0_Msk               /*!< Arm Cortex-M7 boot address 0 */

+#define FLASH_BOOT7_BCM7_ADD1_Pos            (16U)

+#define FLASH_BOOT7_BCM7_ADD1_Msk            (0xFFFFUL << FLASH_BOOT7_BCM7_ADD1_Pos) /*!< 0xFFFF0000 */

+#define FLASH_BOOT7_BCM7_ADD1                FLASH_BOOT7_BCM7_ADD1_Msk               /*!< Arm Cortex-M7 boot address 1 */

+

+/*******************  Bits definition for FLASH_BOOT4 register  ********************/

+#define FLASH_BOOT4_BCM4_ADD0_Pos            (0U)

+#define FLASH_BOOT4_BCM4_ADD0_Msk            (0xFFFFUL << FLASH_BOOT4_BCM4_ADD0_Pos) /*!< 0x0000FFFF */

+#define FLASH_BOOT4_BCM4_ADD0                FLASH_BOOT4_BCM4_ADD0_Msk               /*!< Arm Cortex-M4 boot address 0 */

+#define FLASH_BOOT4_BCM4_ADD1_Pos            (16U)

+#define FLASH_BOOT4_BCM4_ADD1_Msk            (0xFFFFUL << FLASH_BOOT4_BCM4_ADD1_Pos) /*!< 0xFFFF0000 */

+#define FLASH_BOOT4_BCM4_ADD1                FLASH_BOOT4_BCM4_ADD1_Msk               /*!< Arm Cortex-M4 boot address 1 */

+

+/*******************  Bits definition for FLASH_CRCCR register  ********************/

+#define FLASH_CRCCR_CRC_SECT_Pos             (0U)

+#define FLASH_CRCCR_CRC_SECT_Msk             (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */

+#define FLASH_CRCCR_CRC_SECT                 FLASH_CRCCR_CRC_SECT_Msk            /*!< CRC sector number */

+#define FLASH_CRCCR_CRC_BY_SECT_Pos          (8U)

+#define FLASH_CRCCR_CRC_BY_SECT_Msk          (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */

+#define FLASH_CRCCR_CRC_BY_SECT              FLASH_CRCCR_CRC_BY_SECT_Msk            /*!< CRC sector mode select bit */

+#define FLASH_CRCCR_ADD_SECT_Pos             (9U)

+#define FLASH_CRCCR_ADD_SECT_Msk             (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */

+#define FLASH_CRCCR_ADD_SECT                 FLASH_CRCCR_ADD_SECT_Msk            /*!< CRC sector select bit */

+#define FLASH_CRCCR_CLEAN_SECT_Pos           (10U)

+#define FLASH_CRCCR_CLEAN_SECT_Msk           (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */

+#define FLASH_CRCCR_CLEAN_SECT               FLASH_CRCCR_CLEAN_SECT_Msk            /*!< CRC sector list clear bit */

+#define FLASH_CRCCR_START_CRC_Pos            (16U)

+#define FLASH_CRCCR_START_CRC_Msk            (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */

+#define FLASH_CRCCR_START_CRC                FLASH_CRCCR_START_CRC_Msk            /*!< CRC start bit */

+#define FLASH_CRCCR_CLEAN_CRC_Pos            (17U)

+#define FLASH_CRCCR_CLEAN_CRC_Msk            (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */

+#define FLASH_CRCCR_CLEAN_CRC                FLASH_CRCCR_CLEAN_CRC_Msk            /*!< CRC clear bit */

+#define FLASH_CRCCR_CRC_BURST_Pos            (20U)

+#define FLASH_CRCCR_CRC_BURST_Msk            (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */

+#define FLASH_CRCCR_CRC_BURST                FLASH_CRCCR_CRC_BURST_Msk            /*!< CRC burst size */

+#define FLASH_CRCCR_CRC_BURST_0              (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */

+#define FLASH_CRCCR_CRC_BURST_1              (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */

+#define FLASH_CRCCR_ALL_BANK_Pos             (22U)

+#define FLASH_CRCCR_ALL_BANK_Msk             (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */

+#define FLASH_CRCCR_ALL_BANK                 FLASH_CRCCR_ALL_BANK_Msk            /*!< CRC select bit */

+

+/*******************  Bits definition for FLASH_CRCSADD register  ****************/

+#define FLASH_CRCSADD_CRC_START_ADDR_Pos     (0U)

+#define FLASH_CRCSADD_CRC_START_ADDR_Msk     (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCSADD_CRC_START_ADDR         FLASH_CRCSADD_CRC_START_ADDR_Msk                   /*!< CRC start address */

+

+/*******************  Bits definition for FLASH_CRCEADD register  ****************/

+#define FLASH_CRCEADD_CRC_END_ADDR_Pos       (0U)

+#define FLASH_CRCEADD_CRC_END_ADDR_Msk       (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCEADD_CRC_END_ADDR           FLASH_CRCEADD_CRC_END_ADDR_Msk                   /*!< CRC end address */

+

+/*******************  Bits definition for FLASH_CRCDATA register  ***************/

+#define FLASH_CRCDATA_CRC_DATA_Pos           (0U)

+#define FLASH_CRCDATA_CRC_DATA_Msk           (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCDATA_CRC_DATA               FLASH_CRCDATA_CRC_DATA_Msk                   /*!< CRC result */

+

+/*******************  Bits definition for FLASH_ECC_FA register  *******************/

+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos       (0U)

+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk       (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */

+#define FLASH_ECC_FA_FAIL_ECC_ADDR           FLASH_ECC_FA_FAIL_ECC_ADDR_Msk               /*!< ECC error address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          Flexible Memory Controller                        */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for FMC_BCR1 register  *******************/

+#define FMC_BCR1_CCLKEN_Pos        (20U)

+#define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */

+#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continous clock enable     */

+#define FMC_BCR1_WFDIS_Pos         (21U)

+#define FMC_BCR1_WFDIS_Msk         (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */

+#define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */

+

+#define FMC_BCR1_BMAP_Pos          (24U)

+#define FMC_BCR1_BMAP_Msk          (0x3UL << FMC_BCR1_BMAP_Pos)                /*!< 0x03000000 */

+#define FMC_BCR1_BMAP              FMC_BCR1_BMAP_Msk                           /*!<BMAP[1:0] FMC bank mapping */

+#define FMC_BCR1_BMAP_0            (0x1UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x01000000 */

+#define FMC_BCR1_BMAP_1            (0x2UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x02000000 */

+

+#define FMC_BCR1_FMCEN_Pos         (31U)

+#define FMC_BCR1_FMCEN_Msk         (0x1UL << FMC_BCR1_FMCEN_Pos)               /*!< 0x80000000 */

+#define FMC_BCR1_FMCEN             FMC_BCR1_FMCEN_Msk                          /*!<FMC controller Enable */

+/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/

+#define FMC_BCRx_MBKEN_Pos         (0U)

+#define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */

+#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */

+#define FMC_BCRx_MUXEN_Pos         (1U)

+#define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */

+#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */

+

+#define FMC_BCRx_MTYP_Pos          (2U)

+#define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */

+#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */

+#define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000004 */

+#define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000008 */

+

+#define FMC_BCRx_MWID_Pos          (4U)

+#define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */

+#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */

+#define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000010 */

+#define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000020 */

+

+#define FMC_BCRx_FACCEN_Pos        (6U)

+#define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */

+#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */

+#define FMC_BCRx_BURSTEN_Pos       (8U)

+#define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */

+#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */

+#define FMC_BCRx_WAITPOL_Pos       (9U)

+#define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */

+#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */

+#define FMC_BCRx_WAITCFG_Pos       (11U)

+#define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */

+#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */

+#define FMC_BCRx_WREN_Pos          (12U)

+#define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */

+#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */

+#define FMC_BCRx_WAITEN_Pos        (13U)

+#define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */

+#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */

+#define FMC_BCRx_EXTMOD_Pos        (14U)

+#define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */

+#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */

+#define FMC_BCRx_ASYNCWAIT_Pos     (15U)

+#define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */

+#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */

+

+#define FMC_BCRx_CPSIZE_Pos        (16U)

+#define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */

+#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<PSIZE[2:0] bits CRAM Page Size */

+#define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00010000 */

+#define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00020000 */

+#define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00040000 */

+

+#define FMC_BCRx_CBURSTRW_Pos      (19U)

+#define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */

+#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */

+

+/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/

+#define FMC_BTRx_ADDSET_Pos        (0U)

+#define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */

+#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */

+#define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000001 */

+#define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000002 */

+#define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000004 */

+#define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000008 */

+

+#define FMC_BTRx_ADDHLD_Pos        (4U)

+#define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */

+#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */

+#define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000010 */

+#define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000020 */

+#define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000040 */

+#define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000080 */

+

+#define FMC_BTRx_DATAST_Pos        (8U)

+#define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */

+#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */

+#define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000100 */

+#define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000200 */

+#define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000400 */

+#define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000800 */

+#define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00001000 */

+#define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00002000 */

+#define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00004000 */

+#define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00008000 */

+

+#define FMC_BTRx_BUSTURN_Pos       (16U)

+#define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */

+#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */

+#define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00010000 */

+#define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00020000 */

+#define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00040000 */

+#define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00080000 */

+

+#define FMC_BTRx_CLKDIV_Pos        (20U)

+#define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */

+#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */

+#define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00100000 */

+#define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00200000 */

+#define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00400000 */

+#define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00800000 */

+

+#define FMC_BTRx_DATLAT_Pos        (24U)

+#define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */

+#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */

+#define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x01000000 */

+#define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x02000000 */

+#define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x04000000 */

+#define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x08000000 */

+

+#define FMC_BTRx_ACCMOD_Pos        (28U)

+#define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */

+#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */

+#define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x10000000 */

+#define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x20000000 */

+

+/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/

+#define FMC_BWTRx_ADDSET_Pos       (0U)

+#define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */

+#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */

+#define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000001 */

+#define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000002 */

+#define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000004 */

+#define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000008 */

+

+#define FMC_BWTRx_ADDHLD_Pos       (4U)

+#define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */

+#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */

+#define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000010 */

+#define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000020 */

+#define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000040 */

+#define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000080 */

+

+#define FMC_BWTRx_DATAST_Pos       (8U)

+#define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */

+#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */

+#define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000100 */

+#define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000200 */

+#define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000400 */

+#define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000800 */

+#define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00001000 */

+#define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00002000 */

+#define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00004000 */

+#define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00008000 */

+

+#define FMC_BWTRx_BUSTURN_Pos      (16U)

+#define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */

+#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */

+#define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00010000 */

+#define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00020000 */

+#define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00040000 */

+#define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00080000 */

+

+#define FMC_BWTRx_ACCMOD_Pos       (28U)

+#define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */

+#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */

+#define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x10000000 */

+#define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x20000000 */

+

+/******************  Bit definition for FMC_PCR register  *******************/

+#define FMC_PCR_PWAITEN_Pos        (1U)

+#define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */

+#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */

+#define FMC_PCR_PBKEN_Pos          (2U)

+#define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */

+#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */

+

+#define FMC_PCR_PWID_Pos           (4U)

+#define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */

+#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */

+#define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */

+#define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */

+

+#define FMC_PCR_ECCEN_Pos          (6U)

+#define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */

+#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */

+

+#define FMC_PCR_TCLR_Pos           (9U)

+#define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */

+#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */

+#define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */

+#define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */

+#define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */

+#define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */

+

+#define FMC_PCR_TAR_Pos            (13U)

+#define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */

+#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */

+#define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */

+#define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */

+#define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */

+#define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */

+

+#define FMC_PCR_ECCPS_Pos          (17U)

+#define FMC_PCR_ECCPS_Msk          (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */

+#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */

+#define FMC_PCR_ECCPS_0            (0x1UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */

+#define FMC_PCR_ECCPS_1            (0x2UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */

+#define FMC_PCR_ECCPS_2            (0x4UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */

+

+/*******************  Bit definition for FMC_SR register  *******************/

+#define FMC_SR_IRS_Pos             (0U)

+#define FMC_SR_IRS_Msk             (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */

+#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */

+#define FMC_SR_ILS_Pos             (1U)

+#define FMC_SR_ILS_Msk             (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */

+#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */

+#define FMC_SR_IFS_Pos             (2U)

+#define FMC_SR_IFS_Msk             (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */

+#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */

+#define FMC_SR_IREN_Pos            (3U)

+#define FMC_SR_IREN_Msk            (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */

+#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */

+#define FMC_SR_ILEN_Pos            (4U)

+#define FMC_SR_ILEN_Msk            (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */

+#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */

+#define FMC_SR_IFEN_Pos            (5U)

+#define FMC_SR_IFEN_Msk            (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */

+#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */

+#define FMC_SR_FEMPT_Pos           (6U)

+#define FMC_SR_FEMPT_Msk           (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */

+#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */

+

+/******************  Bit definition for FMC_PMEM register  ******************/

+#define FMC_PMEM_MEMSET_Pos       (0U)

+#define FMC_PMEM_MEMSET_Msk       (0xFFUL << FMC_PMEM_MEMSET_Pos)            /*!< 0x000000FF */

+#define FMC_PMEM_MEMSET           FMC_PMEM_MEMSET_Msk                        /*!<MEMSET[7:0] bits (Common memory setup time) */

+#define FMC_PMEM_MEMSET_0         (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */

+#define FMC_PMEM_MEMSET_1         (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */

+#define FMC_PMEM_MEMSET_2         (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */

+#define FMC_PMEM_MEMSET_3         (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */

+#define FMC_PMEM_MEMSET_4         (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */

+#define FMC_PMEM_MEMSET_5         (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */

+#define FMC_PMEM_MEMSET_6         (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */

+#define FMC_PMEM_MEMSET_7         (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */

+

+#define FMC_PMEM_MEMWAIT_Pos      (8U)

+#define FMC_PMEM_MEMWAIT_Msk      (0xFFUL << FMC_PMEM_MEMWAIT_Pos)           /*!< 0x0000FF00 */

+#define FMC_PMEM_MEMWAIT          FMC_PMEM_MEMWAIT_Msk                       /*!<MEMWAIT[7:0] bits (Common memory wait time) */

+#define FMC_PMEM_MEMWAIT_0        (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */

+#define FMC_PMEM_MEMWAIT_1        (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */

+#define FMC_PMEM_MEMWAIT_2        (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */

+#define FMC_PMEM_MEMWAIT_3        (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */

+#define FMC_PMEM_MEMWAIT_4        (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */

+#define FMC_PMEM_MEMWAIT_5        (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */

+#define FMC_PMEM_MEMWAIT_6        (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */

+#define FMC_PMEM_MEMWAIT_7        (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */

+

+#define FMC_PMEM_MEMHOLD_Pos      (16U)

+#define FMC_PMEM_MEMHOLD_Msk      (0xFFUL << FMC_PMEM_MEMHOLD_Pos)           /*!< 0x00FF0000 */

+#define FMC_PMEM_MEMHOLD          FMC_PMEM_MEMHOLD_Msk                       /*!<MEMHOLD[7:0] bits (Common memory hold time) */

+#define FMC_PMEM_MEMHOLD_0        (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */

+#define FMC_PMEM_MEMHOLD_1        (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */

+#define FMC_PMEM_MEMHOLD_2        (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */

+#define FMC_PMEM_MEMHOLD_3        (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */

+#define FMC_PMEM_MEMHOLD_4        (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */

+#define FMC_PMEM_MEMHOLD_5        (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */

+#define FMC_PMEM_MEMHOLD_6        (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */

+#define FMC_PMEM_MEMHOLD_7        (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */

+

+#define FMC_PMEM_MEMHIZ_Pos       (24U)

+#define FMC_PMEM_MEMHIZ_Msk       (0xFFUL << FMC_PMEM_MEMHIZ_Pos)            /*!< 0xFF000000 */

+#define FMC_PMEM_MEMHIZ           FMC_PMEM_MEMHIZ_Msk                        /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */

+#define FMC_PMEM_MEMHIZ_0         (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */

+#define FMC_PMEM_MEMHIZ_1         (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */

+#define FMC_PMEM_MEMHIZ_2         (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */

+#define FMC_PMEM_MEMHIZ_3         (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */

+#define FMC_PMEM_MEMHIZ_4         (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */

+#define FMC_PMEM_MEMHIZ_5         (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */

+#define FMC_PMEM_MEMHIZ_6         (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */

+#define FMC_PMEM_MEMHIZ_7         (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */

+

+/******************  Bit definition for FMC_PATT register  ******************/

+#define FMC_PATT_ATTSET_Pos       (0U)

+#define FMC_PATT_ATTSET_Msk       (0xFFUL << FMC_PATT_ATTSET_Pos)            /*!< 0x000000FF */

+#define FMC_PATT_ATTSET           FMC_PATT_ATTSET_Msk                        /*!<ATTSET[7:0] bits (Attribute memory setup time) */

+#define FMC_PATT_ATTSET_0         (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */

+#define FMC_PATT_ATTSET_1         (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */

+#define FMC_PATT_ATTSET_2         (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */

+#define FMC_PATT_ATTSET_3         (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */

+#define FMC_PATT_ATTSET_4         (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */

+#define FMC_PATT_ATTSET_5         (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */

+#define FMC_PATT_ATTSET_6         (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */

+#define FMC_PATT_ATTSET_7         (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */

+

+#define FMC_PATT_ATTWAIT_Pos      (8U)

+#define FMC_PATT_ATTWAIT_Msk      (0xFFUL << FMC_PATT_ATTWAIT_Pos)           /*!< 0x0000FF00 */

+#define FMC_PATT_ATTWAIT          FMC_PATT_ATTWAIT_Msk                       /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */

+#define FMC_PATT_ATTWAIT_0        (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */

+#define FMC_PATT_ATTWAIT_1        (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */

+#define FMC_PATT_ATTWAIT_2        (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */

+#define FMC_PATT_ATTWAIT_3        (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */

+#define FMC_PATT_ATTWAIT_4        (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */

+#define FMC_PATT_ATTWAIT_5        (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */

+#define FMC_PATT_ATTWAIT_6        (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */

+#define FMC_PATT_ATTWAIT_7        (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */

+

+#define FMC_PATT_ATTHOLD_Pos      (16U)

+#define FMC_PATT_ATTHOLD_Msk      (0xFFUL << FMC_PATT_ATTHOLD_Pos)           /*!< 0x00FF0000 */

+#define FMC_PATT_ATTHOLD          FMC_PATT_ATTHOLD_Msk                       /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */

+#define FMC_PATT_ATTHOLD_0        (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */

+#define FMC_PATT_ATTHOLD_1        (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */

+#define FMC_PATT_ATTHOLD_2        (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */

+#define FMC_PATT_ATTHOLD_3        (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */

+#define FMC_PATT_ATTHOLD_4        (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */

+#define FMC_PATT_ATTHOLD_5        (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */

+#define FMC_PATT_ATTHOLD_6        (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */

+#define FMC_PATT_ATTHOLD_7        (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */

+

+#define FMC_PATT_ATTHIZ_Pos       (24U)

+#define FMC_PATT_ATTHIZ_Msk       (0xFFUL << FMC_PATT_ATTHIZ_Pos)            /*!< 0xFF000000 */

+#define FMC_PATT_ATTHIZ           FMC_PATT_ATTHIZ_Msk                        /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */

+#define FMC_PATT_ATTHIZ_0         (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */

+#define FMC_PATT_ATTHIZ_1         (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */

+#define FMC_PATT_ATTHIZ_2         (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */

+#define FMC_PATT_ATTHIZ_3         (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */

+#define FMC_PATT_ATTHIZ_4         (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */

+#define FMC_PATT_ATTHIZ_5         (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */

+#define FMC_PATT_ATTHIZ_6         (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */

+#define FMC_PATT_ATTHIZ_7         (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */

+

+/******************  Bit definition for FMC_ECCR3 register  ******************/

+#define FMC_ECCR3_ECC3_Pos         (0U)

+#define FMC_ECCR3_ECC3_Msk         (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)        /*!< 0xFFFFFFFF */

+#define FMC_ECCR3_ECC3             FMC_ECCR3_ECC3_Msk                          /*!<ECC result */

+

+/******************  Bit definition for FMC_SDCRx registers (x=1..4)  *********/

+#define FMC_SDCRx_NC_Pos           (0U)

+#define FMC_SDCRx_NC_Msk           (0x3UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000003 */

+#define FMC_SDCRx_NC               FMC_SDCRx_NC_Msk                            /*!<NC[1:0] bits (Number of column bits) */

+#define FMC_SDCRx_NC_0             (0x1UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000001 */

+#define FMC_SDCRx_NC_1             (0x2UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000002 */

+

+#define FMC_SDCRx_NR_Pos           (2U)

+#define FMC_SDCRx_NR_Msk           (0x3UL << FMC_SDCRx_NR_Pos)                 /*!< 0x0000000C */

+#define FMC_SDCRx_NR               FMC_SDCRx_NR_Msk                            /*!<NR[1:0] bits (Number of row bits) */

+#define FMC_SDCRx_NR_0             (0x1UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000004 */

+#define FMC_SDCRx_NR_1             (0x2UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000008 */

+

+#define FMC_SDCRx_MWID_Pos         (4U)

+#define FMC_SDCRx_MWID_Msk         (0x3UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000030 */

+#define FMC_SDCRx_MWID             FMC_SDCRx_MWID_Msk                          /*!<NR[1:0] bits (Number of row bits) */

+#define FMC_SDCRx_MWID_0           (0x1UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000010 */

+#define FMC_SDCRx_MWID_1           (0x2UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000020 */

+

+#define FMC_SDCRx_NB_Pos           (6U)

+#define FMC_SDCRx_NB_Msk           (0x1UL << FMC_SDCRx_NB_Pos)                 /*!< 0x00000040 */

+#define FMC_SDCRx_NB               FMC_SDCRx_NB_Msk                            /*!<Number of internal bank */

+

+#define FMC_SDCRx_CAS_Pos          (7U)

+#define FMC_SDCRx_CAS_Msk          (0x3UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000180 */

+#define FMC_SDCRx_CAS              FMC_SDCRx_CAS_Msk                           /*!<CAS[1:0] bits (CAS latency) */

+#define FMC_SDCRx_CAS_0            (0x1UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000080 */

+#define FMC_SDCRx_CAS_1            (0x2UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000100 */

+

+#define FMC_SDCRx_WP_Pos           (9U)

+#define FMC_SDCRx_WP_Msk           (0x1UL << FMC_SDCRx_WP_Pos)                 /*!< 0x00000200 */

+#define FMC_SDCRx_WP               FMC_SDCRx_WP_Msk                            /*!<Write protection */

+

+#define FMC_SDCRx_SDCLK_Pos        (10U)

+#define FMC_SDCRx_SDCLK_Msk        (0x3UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000C00 */

+#define FMC_SDCRx_SDCLK            FMC_SDCRx_SDCLK_Msk                         /*!<SDRAM clock configuration */

+#define FMC_SDCRx_SDCLK_0          (0x1UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000400 */

+#define FMC_SDCRx_SDCLK_1          (0x2UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000800 */

+

+#define FMC_SDCRx_RBURST_Pos       (12U)

+#define FMC_SDCRx_RBURST_Msk       (0x1UL << FMC_SDCRx_RBURST_Pos)             /*!< 0x00001000 */

+#define FMC_SDCRx_RBURST           FMC_SDCRx_RBURST_Msk                        /*!<Read burst */

+

+#define FMC_SDCRx_RPIPE_Pos        (13U)

+#define FMC_SDCRx_RPIPE_Msk        (0x3UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00006000 */

+#define FMC_SDCRx_RPIPE            FMC_SDCRx_RPIPE_Msk                         /*!<Write protection */

+#define FMC_SDCRx_RPIPE_0          (0x1UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00002000 */

+#define FMC_SDCRx_RPIPE_1          (0x2UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00004000 */

+

+/******************  Bit definition for FMC_SDTRx(1,2) register  ******************/

+#define FMC_SDTRx_TMRD_Pos         (0U)

+#define FMC_SDTRx_TMRD_Msk         (0xFUL << FMC_SDTRx_TMRD_Pos)               /*!< 0x0000000F */

+#define FMC_SDTRx_TMRD             FMC_SDTRx_TMRD_Msk                          /*!<TMRD[3:0] bits (Load mode register to active) */

+#define FMC_SDTRx_TMRD_0           (0x1UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000001 */

+#define FMC_SDTRx_TMRD_1           (0x2UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000002 */

+#define FMC_SDTRx_TMRD_2           (0x4UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000004 */

+#define FMC_SDTRx_TMRD_3           (0x8UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000008 */

+

+#define FMC_SDTRx_TXSR_Pos         (4U)

+#define FMC_SDTRx_TXSR_Msk         (0xFUL << FMC_SDTRx_TXSR_Pos)               /*!< 0x000000F0 */

+#define FMC_SDTRx_TXSR             FMC_SDTRx_TXSR_Msk                          /*!<TXSR[3:0] bits (Exit self refresh) */

+#define FMC_SDTRx_TXSR_0           (0x1UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000010 */

+#define FMC_SDTRx_TXSR_1           (0x2UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000020 */

+#define FMC_SDTRx_TXSR_2           (0x4UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000040 */

+#define FMC_SDTRx_TXSR_3           (0x8UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000080 */

+

+#define FMC_SDTRx_TRAS_Pos         (8U)

+#define FMC_SDTRx_TRAS_Msk         (0xFUL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000F00 */

+#define FMC_SDTRx_TRAS             FMC_SDTRx_TRAS_Msk                          /*!<TRAS[3:0] bits (Self refresh time) */

+#define FMC_SDTRx_TRAS_0           (0x1UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000100 */

+#define FMC_SDTRx_TRAS_1           (0x2UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000200 */

+#define FMC_SDTRx_TRAS_2           (0x4UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000400 */

+#define FMC_SDTRx_TRAS_3           (0x8UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000800 */

+

+#define FMC_SDTRx_TRC_Pos          (12U)

+#define FMC_SDTRx_TRC_Msk          (0xFUL << FMC_SDTRx_TRC_Pos)                /*!< 0x0000F000 */

+#define FMC_SDTRx_TRC              FMC_SDTRx_TRC_Msk                           /*!<TRC[2:0] bits (Row cycle delay) */

+#define FMC_SDTRx_TRC_0            (0x1UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00001000 */

+#define FMC_SDTRx_TRC_1            (0x2UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00002000 */

+#define FMC_SDTRx_TRC_2            (0x4UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00004000 */

+

+#define FMC_SDTRx_TWR_Pos          (16U)

+#define FMC_SDTRx_TWR_Msk          (0xFUL << FMC_SDTRx_TWR_Pos)                /*!< 0x000F0000 */

+#define FMC_SDTRx_TWR              FMC_SDTRx_TWR_Msk                           /*!<TRC[2:0] bits (Write recovery delay) */

+#define FMC_SDTRx_TWR_0            (0x1UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00010000 */

+#define FMC_SDTRx_TWR_1            (0x2UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00020000 */

+#define FMC_SDTRx_TWR_2            (0x4UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00040000 */

+

+#define FMC_SDTRx_TRP_Pos          (20U)

+#define FMC_SDTRx_TRP_Msk          (0xFUL << FMC_SDTRx_TRP_Pos)                /*!< 0x00F00000 */

+#define FMC_SDTRx_TRP              FMC_SDTRx_TRP_Msk                           /*!<TRP[2:0] bits (Row precharge delay) */

+#define FMC_SDTRx_TRP_0            (0x1UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00100000 */

+#define FMC_SDTRx_TRP_1            (0x2UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00200000 */

+#define FMC_SDTRx_TRP_2            (0x4UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00400000 */

+

+#define FMC_SDTRx_TRCD_Pos         (24U)

+#define FMC_SDTRx_TRCD_Msk         (0xFUL << FMC_SDTRx_TRCD_Pos)               /*!< 0x0F000000 */

+#define FMC_SDTRx_TRCD             FMC_SDTRx_TRCD_Msk                          /*!<TRP[2:0] bits (Row to column delay) */

+#define FMC_SDTRx_TRCD_0           (0x1UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x01000000 */

+#define FMC_SDTRx_TRCD_1           (0x2UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x02000000 */

+#define FMC_SDTRx_TRCD_2           (0x4UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x04000000 */

+

+/******************  Bit definition for FMC_SDCMR register  ******************/

+#define FMC_SDCMR_MODE_Pos         (0U)

+#define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */

+#define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */

+#define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */

+#define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */

+#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */

+

+#define FMC_SDCMR_CTB2_Pos         (3U)

+#define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */

+#define FMC_SDCMR_CTB2             FMC_SDCMR_CTB2_Msk                          /*!<Command target 2 */

+

+#define FMC_SDCMR_CTB1_Pos         (4U)

+#define FMC_SDCMR_CTB1_Msk         (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */

+#define FMC_SDCMR_CTB1             FMC_SDCMR_CTB1_Msk                          /*!<Command target 1 */

+

+#define FMC_SDCMR_NRFS_Pos         (5U)

+#define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */

+#define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!<NRFS[3:0] bits (Number of auto-refresh) */

+#define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000020 */

+#define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000040 */

+#define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000080 */

+#define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000100 */

+

+#define FMC_SDCMR_MRD_Pos          (9U)

+#define FMC_SDCMR_MRD_Msk          (0x1FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */

+#define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!<MRD[12:0] bits (Mode register definition) */

+

+/******************  Bit definition for FMC_SDRTR register  ******************/

+#define FMC_SDRTR_CRE_Pos          (0U)

+#define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */

+#define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!<Clear refresh error flag */

+

+#define FMC_SDRTR_COUNT_Pos        (1U)

+#define FMC_SDRTR_COUNT_Msk        (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */

+#define FMC_SDRTR_COUNT            FMC_SDRTR_COUNT_Msk                         /*!<COUNT[12:0] bits (Refresh timer count) */

+

+#define FMC_SDRTR_REIE_Pos         (14U)

+#define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */

+#define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!<RES interupt enable */

+

+/******************  Bit definition for FMC_SDSR register  ******************/

+#define FMC_SDSR_RE_Pos            (0U)

+#define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */

+#define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!<Refresh error flag */

+

+#define FMC_SDSR_MODES1_Pos        (1U)

+#define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */

+#define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!<MODES1[1:0]bits (Status mode for bank 1) */

+#define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000002 */

+#define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000004 */

+

+#define FMC_SDSR_MODES2_Pos        (3U)

+#define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */

+#define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!<MODES2[1:0]bits (Status mode for bank 2) */

+#define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000008 */

+#define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000010 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            General Purpose I/O                             */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bits definition for GPIO_MODER register  *****************/

+#define GPIO_MODER_MODE0_Pos           (0U)

+#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */

+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk

+#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */

+#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */

+

+#define GPIO_MODER_MODE1_Pos           (2U)

+#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */

+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk

+#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */

+#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */

+

+#define GPIO_MODER_MODE2_Pos           (4U)

+#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */

+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk

+#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */

+#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */

+

+#define GPIO_MODER_MODE3_Pos           (6U)

+#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */

+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk

+#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */

+#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */

+

+#define GPIO_MODER_MODE4_Pos           (8U)

+#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */

+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk

+#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */

+#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */

+

+#define GPIO_MODER_MODE5_Pos           (10U)

+#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */

+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk

+#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */

+#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */

+

+#define GPIO_MODER_MODE6_Pos           (12U)

+#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */

+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk

+#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */

+#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */

+

+#define GPIO_MODER_MODE7_Pos           (14U)

+#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */

+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk

+#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */

+#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */

+

+#define GPIO_MODER_MODE8_Pos           (16U)

+#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */

+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk

+#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */

+#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */

+

+#define GPIO_MODER_MODE9_Pos           (18U)

+#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */

+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk

+#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */

+#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */

+

+#define GPIO_MODER_MODE10_Pos          (20U)

+#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */

+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk

+#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */

+#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */

+

+#define GPIO_MODER_MODE11_Pos          (22U)

+#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */

+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk

+#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */

+#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */

+

+#define GPIO_MODER_MODE12_Pos          (24U)

+#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */

+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk

+#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */

+#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */

+

+#define GPIO_MODER_MODE13_Pos          (26U)

+#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */

+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk

+#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */

+#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */

+

+#define GPIO_MODER_MODE14_Pos          (28U)

+#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */

+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk

+#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */

+#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */

+

+#define GPIO_MODER_MODE15_Pos          (30U)

+#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */

+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk

+#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */

+#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_OTYPER register  ****************/

+#define GPIO_OTYPER_OT0_Pos            (0U)

+#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */

+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk

+#define GPIO_OTYPER_OT1_Pos            (1U)

+#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */

+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk

+#define GPIO_OTYPER_OT2_Pos            (2U)

+#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */

+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk

+#define GPIO_OTYPER_OT3_Pos            (3U)

+#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */

+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk

+#define GPIO_OTYPER_OT4_Pos            (4U)

+#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */

+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk

+#define GPIO_OTYPER_OT5_Pos            (5U)

+#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */

+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk

+#define GPIO_OTYPER_OT6_Pos            (6U)

+#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */

+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk

+#define GPIO_OTYPER_OT7_Pos            (7U)

+#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */

+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk

+#define GPIO_OTYPER_OT8_Pos            (8U)

+#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */

+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk

+#define GPIO_OTYPER_OT9_Pos            (9U)

+#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */

+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk

+#define GPIO_OTYPER_OT10_Pos           (10U)

+#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */

+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk

+#define GPIO_OTYPER_OT11_Pos           (11U)

+#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */

+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk

+#define GPIO_OTYPER_OT12_Pos           (12U)

+#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */

+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk

+#define GPIO_OTYPER_OT13_Pos           (13U)

+#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */

+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk

+#define GPIO_OTYPER_OT14_Pos           (14U)

+#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */

+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk

+#define GPIO_OTYPER_OT15_Pos           (15U)

+#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */

+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk

+

+/******************  Bits definition for GPIO_OSPEEDR register  ***************/

+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)

+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */

+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk

+#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */

+#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */

+

+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)

+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */

+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk

+#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */

+#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */

+

+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)

+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */

+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk

+#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */

+#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */

+

+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)

+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */

+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk

+#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */

+#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */

+

+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)

+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */

+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk

+#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */

+#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */

+

+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)

+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */

+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk

+#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */

+#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */

+

+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)

+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */

+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk

+#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */

+#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */

+

+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)

+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */

+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk

+#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */

+#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */

+

+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)

+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */

+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk

+#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */

+#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */

+

+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)

+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */

+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk

+#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */

+#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */

+

+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)

+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */

+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk

+#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */

+#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */

+

+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)

+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */

+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk

+#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */

+#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */

+

+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)

+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */

+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk

+#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */

+#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */

+

+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)

+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */

+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk

+#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */

+#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */

+

+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)

+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */

+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk

+#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */

+#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */

+

+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)

+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */

+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk

+#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */

+#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_PUPDR register  *****************/

+#define GPIO_PUPDR_PUPD0_Pos           (0U)

+#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */

+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk

+#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */

+#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */

+

+#define GPIO_PUPDR_PUPD1_Pos           (2U)

+#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */

+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk

+#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */

+#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */

+

+#define GPIO_PUPDR_PUPD2_Pos           (4U)

+#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */

+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk

+#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */

+#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */

+

+#define GPIO_PUPDR_PUPD3_Pos           (6U)

+#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */

+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk

+#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */

+#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */

+

+#define GPIO_PUPDR_PUPD4_Pos           (8U)

+#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */

+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk

+#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */

+#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */

+

+#define GPIO_PUPDR_PUPD5_Pos           (10U)

+#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */

+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk

+#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */

+#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */

+

+#define GPIO_PUPDR_PUPD6_Pos           (12U)

+#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */

+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk

+#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */

+#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */

+

+#define GPIO_PUPDR_PUPD7_Pos           (14U)

+#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */

+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk

+#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */

+#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */

+

+#define GPIO_PUPDR_PUPD8_Pos           (16U)

+#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */

+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk

+#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */

+#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */

+

+#define GPIO_PUPDR_PUPD9_Pos           (18U)

+#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */

+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk

+#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */

+#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */

+

+#define GPIO_PUPDR_PUPD10_Pos          (20U)

+#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */

+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk

+#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */

+#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */

+

+#define GPIO_PUPDR_PUPD11_Pos          (22U)

+#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */

+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk

+#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */

+#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */

+

+#define GPIO_PUPDR_PUPD12_Pos          (24U)

+#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */

+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk

+#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */

+#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */

+

+#define GPIO_PUPDR_PUPD13_Pos          (26U)

+#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */

+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk

+#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */

+#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */

+

+#define GPIO_PUPDR_PUPD14_Pos          (28U)

+#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */

+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk

+#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */

+#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */

+

+#define GPIO_PUPDR_PUPD15_Pos          (30U)

+#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */

+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk

+#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */

+#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_IDR register  *******************/

+#define GPIO_IDR_ID0_Pos               (0U)

+#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */

+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk

+#define GPIO_IDR_ID1_Pos               (1U)

+#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */

+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk

+#define GPIO_IDR_ID2_Pos               (2U)

+#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */

+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk

+#define GPIO_IDR_ID3_Pos               (3U)

+#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */

+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk

+#define GPIO_IDR_ID4_Pos               (4U)

+#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */

+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk

+#define GPIO_IDR_ID5_Pos               (5U)

+#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */

+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk

+#define GPIO_IDR_ID6_Pos               (6U)

+#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */

+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk

+#define GPIO_IDR_ID7_Pos               (7U)

+#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */

+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk

+#define GPIO_IDR_ID8_Pos               (8U)

+#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */

+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk

+#define GPIO_IDR_ID9_Pos               (9U)

+#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */

+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk

+#define GPIO_IDR_ID10_Pos              (10U)

+#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */

+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk

+#define GPIO_IDR_ID11_Pos              (11U)

+#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */

+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk

+#define GPIO_IDR_ID12_Pos              (12U)

+#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */

+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk

+#define GPIO_IDR_ID13_Pos              (13U)

+#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */

+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk

+#define GPIO_IDR_ID14_Pos              (14U)

+#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */

+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk

+#define GPIO_IDR_ID15_Pos              (15U)

+#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */

+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk

+

+/******************  Bits definition for GPIO_ODR register  *******************/

+#define GPIO_ODR_OD0_Pos               (0U)

+#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */

+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk

+#define GPIO_ODR_OD1_Pos               (1U)

+#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */

+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk

+#define GPIO_ODR_OD2_Pos               (2U)

+#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */

+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk

+#define GPIO_ODR_OD3_Pos               (3U)

+#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */

+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk

+#define GPIO_ODR_OD4_Pos               (4U)

+#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */

+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk

+#define GPIO_ODR_OD5_Pos               (5U)

+#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */

+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk

+#define GPIO_ODR_OD6_Pos               (6U)

+#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */

+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk

+#define GPIO_ODR_OD7_Pos               (7U)

+#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */

+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk

+#define GPIO_ODR_OD8_Pos               (8U)

+#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */

+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk

+#define GPIO_ODR_OD9_Pos               (9U)

+#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */

+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk

+#define GPIO_ODR_OD10_Pos              (10U)

+#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */

+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk

+#define GPIO_ODR_OD11_Pos              (11U)

+#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */

+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk

+#define GPIO_ODR_OD12_Pos              (12U)

+#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */

+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk

+#define GPIO_ODR_OD13_Pos              (13U)

+#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */

+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk

+#define GPIO_ODR_OD14_Pos              (14U)

+#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */

+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk

+#define GPIO_ODR_OD15_Pos              (15U)

+#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */

+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk

+

+/******************  Bits definition for GPIO_BSRR register  ******************/

+#define GPIO_BSRR_BS0_Pos              (0U)

+#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */

+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk

+#define GPIO_BSRR_BS1_Pos              (1U)

+#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */

+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk

+#define GPIO_BSRR_BS2_Pos              (2U)

+#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */

+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk

+#define GPIO_BSRR_BS3_Pos              (3U)

+#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */

+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk

+#define GPIO_BSRR_BS4_Pos              (4U)

+#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */

+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk

+#define GPIO_BSRR_BS5_Pos              (5U)

+#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */

+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk

+#define GPIO_BSRR_BS6_Pos              (6U)

+#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */

+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk

+#define GPIO_BSRR_BS7_Pos              (7U)

+#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */

+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk

+#define GPIO_BSRR_BS8_Pos              (8U)

+#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */

+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk

+#define GPIO_BSRR_BS9_Pos              (9U)

+#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */

+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk

+#define GPIO_BSRR_BS10_Pos             (10U)

+#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */

+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk

+#define GPIO_BSRR_BS11_Pos             (11U)

+#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */

+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk

+#define GPIO_BSRR_BS12_Pos             (12U)

+#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */

+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk

+#define GPIO_BSRR_BS13_Pos             (13U)

+#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */

+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk

+#define GPIO_BSRR_BS14_Pos             (14U)

+#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */

+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk

+#define GPIO_BSRR_BS15_Pos             (15U)

+#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */

+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk

+#define GPIO_BSRR_BR0_Pos              (16U)

+#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */

+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk

+#define GPIO_BSRR_BR1_Pos              (17U)

+#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */

+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk

+#define GPIO_BSRR_BR2_Pos              (18U)

+#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */

+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk

+#define GPIO_BSRR_BR3_Pos              (19U)

+#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */

+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk

+#define GPIO_BSRR_BR4_Pos              (20U)

+#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */

+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk

+#define GPIO_BSRR_BR5_Pos              (21U)

+#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */

+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk

+#define GPIO_BSRR_BR6_Pos              (22U)

+#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */

+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk

+#define GPIO_BSRR_BR7_Pos              (23U)

+#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */

+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk

+#define GPIO_BSRR_BR8_Pos              (24U)

+#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */

+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk

+#define GPIO_BSRR_BR9_Pos              (25U)

+#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */

+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk

+#define GPIO_BSRR_BR10_Pos             (26U)

+#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */

+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk

+#define GPIO_BSRR_BR11_Pos             (27U)

+#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */

+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk

+#define GPIO_BSRR_BR12_Pos             (28U)

+#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */

+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk

+#define GPIO_BSRR_BR13_Pos             (29U)

+#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */

+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk

+#define GPIO_BSRR_BR14_Pos             (30U)

+#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */

+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk

+#define GPIO_BSRR_BR15_Pos             (31U)

+#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */

+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk

+

+/****************** Bit definition for GPIO_LCKR register *********************/

+#define GPIO_LCKR_LCK0_Pos             (0U)

+#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */

+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk

+#define GPIO_LCKR_LCK1_Pos             (1U)

+#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */

+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk

+#define GPIO_LCKR_LCK2_Pos             (2U)

+#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */

+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk

+#define GPIO_LCKR_LCK3_Pos             (3U)

+#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */

+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk

+#define GPIO_LCKR_LCK4_Pos             (4U)

+#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */

+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk

+#define GPIO_LCKR_LCK5_Pos             (5U)

+#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */

+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk

+#define GPIO_LCKR_LCK6_Pos             (6U)

+#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */

+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk

+#define GPIO_LCKR_LCK7_Pos             (7U)

+#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */

+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk

+#define GPIO_LCKR_LCK8_Pos             (8U)

+#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */

+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk

+#define GPIO_LCKR_LCK9_Pos             (9U)

+#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */

+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk

+#define GPIO_LCKR_LCK10_Pos            (10U)

+#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */

+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk

+#define GPIO_LCKR_LCK11_Pos            (11U)

+#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */

+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk

+#define GPIO_LCKR_LCK12_Pos            (12U)

+#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */

+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk

+#define GPIO_LCKR_LCK13_Pos            (13U)

+#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */

+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk

+#define GPIO_LCKR_LCK14_Pos            (14U)

+#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */

+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk

+#define GPIO_LCKR_LCK15_Pos            (15U)

+#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */

+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk

+#define GPIO_LCKR_LCKK_Pos             (16U)

+#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */

+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk

+

+/****************** Bit definition for GPIO_AFRL register  ********************/

+#define GPIO_AFRL_AFSEL0_Pos           (0U)

+#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */

+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk

+#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */

+#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */

+#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */

+#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */

+#define GPIO_AFRL_AFSEL1_Pos           (4U)

+#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */

+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk

+#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */

+#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */

+#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */

+#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */

+#define GPIO_AFRL_AFSEL2_Pos           (8U)

+#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */

+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk

+#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */

+#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */

+#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */

+#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */

+#define GPIO_AFRL_AFSEL3_Pos           (12U)

+#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */

+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk

+#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */

+#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */

+#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */

+#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */

+#define GPIO_AFRL_AFSEL4_Pos           (16U)

+#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */

+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk

+#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */

+#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */

+#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */

+#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */

+#define GPIO_AFRL_AFSEL5_Pos           (20U)

+#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */

+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk

+#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */

+#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */

+#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */

+#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */

+#define GPIO_AFRL_AFSEL6_Pos           (24U)

+#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */

+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk

+#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */

+#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */

+#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */

+#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */

+#define GPIO_AFRL_AFSEL7_Pos           (28U)

+#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */

+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk

+#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */

+#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */

+#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */

+#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */

+

+/* Legacy defines */

+#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0

+#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1

+#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2

+#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3

+#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4

+#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5

+#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6

+#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7

+

+/****************** Bit definition for GPIO_AFRH register  ********************/

+#define GPIO_AFRH_AFSEL8_Pos           (0U)

+#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */

+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk

+#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */

+#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */

+#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */

+#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */

+#define GPIO_AFRH_AFSEL9_Pos           (4U)

+#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */

+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk

+#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */

+#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */

+#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */

+#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */

+#define GPIO_AFRH_AFSEL10_Pos          (8U)

+#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */

+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk

+#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */

+#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */

+#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */

+#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */

+#define GPIO_AFRH_AFSEL11_Pos          (12U)

+#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */

+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk

+#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */

+#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */

+#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */

+#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */

+#define GPIO_AFRH_AFSEL12_Pos          (16U)

+#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */

+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk

+#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */

+#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */

+#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */

+#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */

+#define GPIO_AFRH_AFSEL13_Pos          (20U)

+#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */

+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk

+#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */

+#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */

+#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */

+#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */

+#define GPIO_AFRH_AFSEL14_Pos          (24U)

+#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */

+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk

+#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */

+#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */

+#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */

+#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */

+#define GPIO_AFRH_AFSEL15_Pos          (28U)

+#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */

+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk

+#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */

+#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */

+#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */

+#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */

+

+/* Legacy defines */

+#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8

+#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9

+#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10

+#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11

+#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12

+#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13

+#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14

+#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15

+

+/******************************************************************************/

+/*                                                                            */

+/*                        HSEM HW Semaphore                                   */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for HSEM_R register  ********************/

+#define HSEM_R_PROCID_Pos         (0U)

+#define HSEM_R_PROCID_Msk         (0xFFUL << HSEM_R_PROCID_Pos)                /*!< 0x000000FF */

+#define HSEM_R_PROCID             HSEM_R_PROCID_Msk                            /*!<Semaphore ProcessID */

+#define HSEM_R_COREID_Pos         (8U)

+#define HSEM_R_COREID_Msk         (0xFFUL << HSEM_R_COREID_Pos)                /*!< 0x0000FF00 */

+#define HSEM_R_COREID             HSEM_R_COREID_Msk                            /*!<Semaphore CoreID.   */

+#define HSEM_R_LOCK_Pos           (31U)

+#define HSEM_R_LOCK_Msk           (0x1UL << HSEM_R_LOCK_Pos)                   /*!< 0x80000000 */

+#define HSEM_R_LOCK               HSEM_R_LOCK_Msk                              /*!<Lock indication.    */

+

+/********************  Bit definition for HSEM_RLR register  ******************/

+#define HSEM_RLR_PROCID_Pos       (0U)

+#define HSEM_RLR_PROCID_Msk       (0xFFUL << HSEM_RLR_PROCID_Pos)              /*!< 0x000000FF */

+#define HSEM_RLR_PROCID           HSEM_RLR_PROCID_Msk                          /*!<Semaphore ProcessID */

+#define HSEM_RLR_COREID_Pos       (8U)

+#define HSEM_RLR_COREID_Msk       (0xFFUL << HSEM_RLR_COREID_Pos)              /*!< 0x0000FF00 */

+#define HSEM_RLR_COREID           HSEM_RLR_COREID_Msk                          /*!<Semaphore CoreID.   */

+#define HSEM_RLR_LOCK_Pos         (31U)

+#define HSEM_RLR_LOCK_Msk         (0x1UL << HSEM_RLR_LOCK_Pos)                 /*!< 0x80000000 */

+#define HSEM_RLR_LOCK             HSEM_RLR_LOCK_Msk                            /*!<Lock indication.    */

+

+/********************  Bit definition for HSEM_C1IER register  *****************/

+#define HSEM_C1IER_ISE0_Pos       (0U)

+#define HSEM_C1IER_ISE0_Msk       (0x1UL << HSEM_C1IER_ISE0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1IER_ISE0           HSEM_C1IER_ISE0_Msk                          /*!<semaphore 0 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE1_Pos       (1U)

+#define HSEM_C1IER_ISE1_Msk       (0x1UL << HSEM_C1IER_ISE1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1IER_ISE1           HSEM_C1IER_ISE1_Msk                          /*!<semaphore 1 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE2_Pos       (2U)

+#define HSEM_C1IER_ISE2_Msk       (0x1UL << HSEM_C1IER_ISE2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1IER_ISE2           HSEM_C1IER_ISE2_Msk                          /*!<semaphore 2 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE3_Pos       (3U)

+#define HSEM_C1IER_ISE3_Msk       (0x1UL << HSEM_C1IER_ISE3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1IER_ISE3           HSEM_C1IER_ISE3_Msk                          /*!<semaphore 3 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE4_Pos       (4U)

+#define HSEM_C1IER_ISE4_Msk       (0x1UL << HSEM_C1IER_ISE4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1IER_ISE4           HSEM_C1IER_ISE4_Msk                          /*!<semaphore 4 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE5_Pos       (5U)

+#define HSEM_C1IER_ISE5_Msk       (0x1UL << HSEM_C1IER_ISE5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1IER_ISE5           HSEM_C1IER_ISE5_Msk                          /*!<semaphore 5 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE6_Pos       (6U)

+#define HSEM_C1IER_ISE6_Msk       (0x1UL << HSEM_C1IER_ISE6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1IER_ISE6           HSEM_C1IER_ISE6_Msk                          /*!<semaphore 6 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE7_Pos       (7U)

+#define HSEM_C1IER_ISE7_Msk       (0x1UL << HSEM_C1IER_ISE7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1IER_ISE7           HSEM_C1IER_ISE7_Msk                          /*!<semaphore 7 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE8_Pos       (8U)

+#define HSEM_C1IER_ISE8_Msk       (0x1UL << HSEM_C1IER_ISE8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1IER_ISE8           HSEM_C1IER_ISE8_Msk                          /*!<semaphore 8 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE9_Pos       (9U)

+#define HSEM_C1IER_ISE9_Msk       (0x1UL << HSEM_C1IER_ISE9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1IER_ISE9           HSEM_C1IER_ISE9_Msk                          /*!<semaphore 9 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE10_Pos      (10U)

+#define HSEM_C1IER_ISE10_Msk      (0x1UL << HSEM_C1IER_ISE10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1IER_ISE10          HSEM_C1IER_ISE10_Msk                         /*!<semaphore 10 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE11_Pos      (11U)

+#define HSEM_C1IER_ISE11_Msk      (0x1UL << HSEM_C1IER_ISE11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1IER_ISE11          HSEM_C1IER_ISE11_Msk                         /*!<semaphore 11 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE12_Pos      (12U)

+#define HSEM_C1IER_ISE12_Msk      (0x1UL << HSEM_C1IER_ISE12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1IER_ISE12          HSEM_C1IER_ISE12_Msk                         /*!<semaphore 12 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE13_Pos      (13U)

+#define HSEM_C1IER_ISE13_Msk      (0x1UL << HSEM_C1IER_ISE13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1IER_ISE13          HSEM_C1IER_ISE13_Msk                         /*!<semaphore 13 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE14_Pos      (14U)

+#define HSEM_C1IER_ISE14_Msk      (0x1UL << HSEM_C1IER_ISE14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1IER_ISE14          HSEM_C1IER_ISE14_Msk                         /*!<semaphore 14 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE15_Pos      (15U)

+#define HSEM_C1IER_ISE15_Msk      (0x1UL << HSEM_C1IER_ISE15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1IER_ISE15          HSEM_C1IER_ISE15_Msk                         /*!<semaphore 15 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE16_Pos      (16U)

+#define HSEM_C1IER_ISE16_Msk      (0x1UL << HSEM_C1IER_ISE16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1IER_ISE16          HSEM_C1IER_ISE16_Msk                         /*!<semaphore 16 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE17_Pos      (17U)

+#define HSEM_C1IER_ISE17_Msk      (0x1UL << HSEM_C1IER_ISE17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1IER_ISE17          HSEM_C1IER_ISE17_Msk                         /*!<semaphore 17 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE18_Pos      (18U)

+#define HSEM_C1IER_ISE18_Msk      (0x1UL << HSEM_C1IER_ISE18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1IER_ISE18          HSEM_C1IER_ISE18_Msk                         /*!<semaphore 18 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE19_Pos      (19U)

+#define HSEM_C1IER_ISE19_Msk      (0x1UL << HSEM_C1IER_ISE19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1IER_ISE19          HSEM_C1IER_ISE19_Msk                         /*!<semaphore 19 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE20_Pos      (20U)

+#define HSEM_C1IER_ISE20_Msk      (0x1UL << HSEM_C1IER_ISE20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1IER_ISE20          HSEM_C1IER_ISE20_Msk                         /*!<semaphore 20 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE21_Pos      (21U)

+#define HSEM_C1IER_ISE21_Msk      (0x1UL << HSEM_C1IER_ISE21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1IER_ISE21          HSEM_C1IER_ISE21_Msk                         /*!<semaphore 21 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE22_Pos      (22U)

+#define HSEM_C1IER_ISE22_Msk      (0x1UL << HSEM_C1IER_ISE22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1IER_ISE22          HSEM_C1IER_ISE22_Msk                         /*!<semaphore 22 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE23_Pos      (23U)

+#define HSEM_C1IER_ISE23_Msk      (0x1UL << HSEM_C1IER_ISE23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1IER_ISE23          HSEM_C1IER_ISE23_Msk                         /*!<semaphore 23 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE24_Pos      (24U)

+#define HSEM_C1IER_ISE24_Msk      (0x1UL << HSEM_C1IER_ISE24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1IER_ISE24          HSEM_C1IER_ISE24_Msk                         /*!<semaphore 24 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE25_Pos      (25U)

+#define HSEM_C1IER_ISE25_Msk      (0x1UL << HSEM_C1IER_ISE25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1IER_ISE25          HSEM_C1IER_ISE25_Msk                         /*!<semaphore 25 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE26_Pos      (26U)

+#define HSEM_C1IER_ISE26_Msk      (0x1UL << HSEM_C1IER_ISE26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1IER_ISE26          HSEM_C1IER_ISE26_Msk                         /*!<semaphore 26 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE27_Pos      (27U)

+#define HSEM_C1IER_ISE27_Msk      (0x1UL << HSEM_C1IER_ISE27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1IER_ISE27          HSEM_C1IER_ISE27_Msk                         /*!<semaphore 27 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE28_Pos      (28U)

+#define HSEM_C1IER_ISE28_Msk      (0x1UL << HSEM_C1IER_ISE28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1IER_ISE28          HSEM_C1IER_ISE28_Msk                         /*!<semaphore 28 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE29_Pos      (29U)

+#define HSEM_C1IER_ISE29_Msk      (0x1UL << HSEM_C1IER_ISE29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1IER_ISE29          HSEM_C1IER_ISE29_Msk                         /*!<semaphore 29 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE30_Pos      (30U)

+#define HSEM_C1IER_ISE30_Msk      (0x1UL << HSEM_C1IER_ISE30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1IER_ISE30          HSEM_C1IER_ISE30_Msk                         /*!<semaphore 30 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE31_Pos      (31U)

+#define HSEM_C1IER_ISE31_Msk      (0x1UL << HSEM_C1IER_ISE31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1IER_ISE31          HSEM_C1IER_ISE31_Msk                         /*!<semaphore 31 interrupt 0 enable bit. */

+

+/********************  Bit definition for HSEM_C1ICR register  *****************/

+#define HSEM_C1ICR_ISC0_Pos       (0U)

+#define HSEM_C1ICR_ISC0_Msk       (0x1UL << HSEM_C1ICR_ISC0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1ICR_ISC0           HSEM_C1ICR_ISC0_Msk                          /*!<semaphore 0 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC1_Pos       (1U)

+#define HSEM_C1ICR_ISC1_Msk       (0x1UL << HSEM_C1ICR_ISC1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1ICR_ISC1           HSEM_C1ICR_ISC1_Msk                          /*!<semaphore 1 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC2_Pos       (2U)

+#define HSEM_C1ICR_ISC2_Msk       (0x1UL << HSEM_C1ICR_ISC2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1ICR_ISC2           HSEM_C1ICR_ISC2_Msk                          /*!<semaphore 2 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC3_Pos       (3U)

+#define HSEM_C1ICR_ISC3_Msk       (0x1UL << HSEM_C1ICR_ISC3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1ICR_ISC3           HSEM_C1ICR_ISC3_Msk                          /*!<semaphore 3 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC4_Pos       (4U)

+#define HSEM_C1ICR_ISC4_Msk       (0x1UL << HSEM_C1ICR_ISC4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1ICR_ISC4           HSEM_C1ICR_ISC4_Msk                          /*!<semaphore 4 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC5_Pos       (5U)

+#define HSEM_C1ICR_ISC5_Msk       (0x1UL << HSEM_C1ICR_ISC5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1ICR_ISC5           HSEM_C1ICR_ISC5_Msk                          /*!<semaphore 5 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC6_Pos       (6U)

+#define HSEM_C1ICR_ISC6_Msk       (0x1UL << HSEM_C1ICR_ISC6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1ICR_ISC6           HSEM_C1ICR_ISC6_Msk                          /*!<semaphore 6 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC7_Pos       (7U)

+#define HSEM_C1ICR_ISC7_Msk       (0x1UL << HSEM_C1ICR_ISC7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1ICR_ISC7           HSEM_C1ICR_ISC7_Msk                          /*!<semaphore 7 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC8_Pos       (8U)

+#define HSEM_C1ICR_ISC8_Msk       (0x1UL << HSEM_C1ICR_ISC8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1ICR_ISC8           HSEM_C1ICR_ISC8_Msk                          /*!<semaphore 8 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC9_Pos       (9U)

+#define HSEM_C1ICR_ISC9_Msk       (0x1UL << HSEM_C1ICR_ISC9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1ICR_ISC9           HSEM_C1ICR_ISC9_Msk                          /*!<semaphore 9 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC10_Pos      (10U)

+#define HSEM_C1ICR_ISC10_Msk      (0x1UL << HSEM_C1ICR_ISC10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1ICR_ISC10          HSEM_C1ICR_ISC10_Msk                         /*!<semaphore 10 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC11_Pos      (11U)

+#define HSEM_C1ICR_ISC11_Msk      (0x1UL << HSEM_C1ICR_ISC11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1ICR_ISC11          HSEM_C1ICR_ISC11_Msk                         /*!<semaphore 11 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC12_Pos      (12U)

+#define HSEM_C1ICR_ISC12_Msk      (0x1UL << HSEM_C1ICR_ISC12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1ICR_ISC12          HSEM_C1ICR_ISC12_Msk                         /*!<semaphore 12 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC13_Pos      (13U)

+#define HSEM_C1ICR_ISC13_Msk      (0x1UL << HSEM_C1ICR_ISC13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1ICR_ISC13          HSEM_C1ICR_ISC13_Msk                         /*!<semaphore 13 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC14_Pos      (14U)

+#define HSEM_C1ICR_ISC14_Msk      (0x1UL << HSEM_C1ICR_ISC14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1ICR_ISC14          HSEM_C1ICR_ISC14_Msk                         /*!<semaphore 14 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC15_Pos      (15U)

+#define HSEM_C1ICR_ISC15_Msk      (0x1UL << HSEM_C1ICR_ISC15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1ICR_ISC15          HSEM_C1ICR_ISC15_Msk                         /*!<semaphore 15 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC16_Pos      (16U)

+#define HSEM_C1ICR_ISC16_Msk      (0x1UL << HSEM_C1ICR_ISC16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1ICR_ISC16          HSEM_C1ICR_ISC16_Msk                         /*!<semaphore 16 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC17_Pos      (17U)

+#define HSEM_C1ICR_ISC17_Msk      (0x1UL << HSEM_C1ICR_ISC17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1ICR_ISC17          HSEM_C1ICR_ISC17_Msk                         /*!<semaphore 17 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC18_Pos      (18U)

+#define HSEM_C1ICR_ISC18_Msk      (0x1UL << HSEM_C1ICR_ISC18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1ICR_ISC18          HSEM_C1ICR_ISC18_Msk                         /*!<semaphore 18 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC19_Pos      (19U)

+#define HSEM_C1ICR_ISC19_Msk      (0x1UL << HSEM_C1ICR_ISC19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1ICR_ISC19          HSEM_C1ICR_ISC19_Msk                         /*!<semaphore 19 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC20_Pos      (20U)

+#define HSEM_C1ICR_ISC20_Msk      (0x1UL << HSEM_C1ICR_ISC20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1ICR_ISC20          HSEM_C1ICR_ISC20_Msk                         /*!<semaphore 20 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC21_Pos      (21U)

+#define HSEM_C1ICR_ISC21_Msk      (0x1UL << HSEM_C1ICR_ISC21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1ICR_ISC21          HSEM_C1ICR_ISC21_Msk                         /*!<semaphore 21 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC22_Pos      (22U)

+#define HSEM_C1ICR_ISC22_Msk      (0x1UL << HSEM_C1ICR_ISC22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1ICR_ISC22          HSEM_C1ICR_ISC22_Msk                         /*!<semaphore 22 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC23_Pos      (23U)

+#define HSEM_C1ICR_ISC23_Msk      (0x1UL << HSEM_C1ICR_ISC23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1ICR_ISC23          HSEM_C1ICR_ISC23_Msk                         /*!<semaphore 23 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC24_Pos      (24U)

+#define HSEM_C1ICR_ISC24_Msk      (0x1UL << HSEM_C1ICR_ISC24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1ICR_ISC24          HSEM_C1ICR_ISC24_Msk                         /*!<semaphore 24 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC25_Pos      (25U)

+#define HSEM_C1ICR_ISC25_Msk      (0x1UL << HSEM_C1ICR_ISC25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1ICR_ISC25          HSEM_C1ICR_ISC25_Msk                         /*!<semaphore 25 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC26_Pos      (26U)

+#define HSEM_C1ICR_ISC26_Msk      (0x1UL << HSEM_C1ICR_ISC26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1ICR_ISC26          HSEM_C1ICR_ISC26_Msk                         /*!<semaphore 26 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC27_Pos      (27U)

+#define HSEM_C1ICR_ISC27_Msk      (0x1UL << HSEM_C1ICR_ISC27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1ICR_ISC27          HSEM_C1ICR_ISC27_Msk                         /*!<semaphore 27 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC28_Pos      (28U)

+#define HSEM_C1ICR_ISC28_Msk      (0x1UL << HSEM_C1ICR_ISC28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1ICR_ISC28          HSEM_C1ICR_ISC28_Msk                         /*!<semaphore 28 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC29_Pos      (29U)

+#define HSEM_C1ICR_ISC29_Msk      (0x1UL << HSEM_C1ICR_ISC29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1ICR_ISC29          HSEM_C1ICR_ISC29_Msk                         /*!<semaphore 29 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC30_Pos      (30U)

+#define HSEM_C1ICR_ISC30_Msk      (0x1UL << HSEM_C1ICR_ISC30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1ICR_ISC30          HSEM_C1ICR_ISC30_Msk                         /*!<semaphore 30 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC31_Pos      (31U)

+#define HSEM_C1ICR_ISC31_Msk      (0x1UL << HSEM_C1ICR_ISC31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1ICR_ISC31          HSEM_C1ICR_ISC31_Msk                         /*!<semaphore 31 interrupt 0 clear bit. */

+

+/********************  Bit definition for HSEM_C1ISR register  *****************/

+#define HSEM_C1ISR_ISF0_Pos       (0U)

+#define HSEM_C1ISR_ISF0_Msk       (0x1UL << HSEM_C1ISR_ISF0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1ISR_ISF0           HSEM_C1ISR_ISF0_Msk                          /*!<semaphore 0 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF1_Pos       (1U)

+#define HSEM_C1ISR_ISF1_Msk       (0x1UL << HSEM_C1ISR_ISF1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1ISR_ISF1           HSEM_C1ISR_ISF1_Msk                          /*!<semaphore 1 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF2_Pos       (2U)

+#define HSEM_C1ISR_ISF2_Msk       (0x1UL << HSEM_C1ISR_ISF2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1ISR_ISF2           HSEM_C1ISR_ISF2_Msk                          /*!<semaphore 2 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF3_Pos       (3U)

+#define HSEM_C1ISR_ISF3_Msk       (0x1UL << HSEM_C1ISR_ISF3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1ISR_ISF3           HSEM_C1ISR_ISF3_Msk                          /*!<semaphore 3 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF4_Pos       (4U)

+#define HSEM_C1ISR_ISF4_Msk       (0x1UL << HSEM_C1ISR_ISF4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1ISR_ISF4           HSEM_C1ISR_ISF4_Msk                          /*!<semaphore 4 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF5_Pos       (5U)

+#define HSEM_C1ISR_ISF5_Msk       (0x1UL << HSEM_C1ISR_ISF5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1ISR_ISF5           HSEM_C1ISR_ISF5_Msk                          /*!<semaphore 5 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF6_Pos       (6U)

+#define HSEM_C1ISR_ISF6_Msk       (0x1UL << HSEM_C1ISR_ISF6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1ISR_ISF6           HSEM_C1ISR_ISF6_Msk                          /*!<semaphore 6 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF7_Pos       (7U)

+#define HSEM_C1ISR_ISF7_Msk       (0x1UL << HSEM_C1ISR_ISF7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1ISR_ISF7           HSEM_C1ISR_ISF7_Msk                          /*!<semaphore 7 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF8_Pos       (8U)

+#define HSEM_C1ISR_ISF8_Msk       (0x1UL << HSEM_C1ISR_ISF8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1ISR_ISF8           HSEM_C1ISR_ISF8_Msk                          /*!<semaphore 8 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF9_Pos       (9U)

+#define HSEM_C1ISR_ISF9_Msk       (0x1UL << HSEM_C1ISR_ISF9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1ISR_ISF9           HSEM_C1ISR_ISF9_Msk                          /*!<semaphore 9 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF10_Pos      (10U)

+#define HSEM_C1ISR_ISF10_Msk      (0x1UL << HSEM_C1ISR_ISF10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1ISR_ISF10          HSEM_C1ISR_ISF10_Msk                         /*!<semaphore 10 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF11_Pos      (11U)

+#define HSEM_C1ISR_ISF11_Msk      (0x1UL << HSEM_C1ISR_ISF11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1ISR_ISF11          HSEM_C1ISR_ISF11_Msk                         /*!<semaphore 11 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF12_Pos      (12U)

+#define HSEM_C1ISR_ISF12_Msk      (0x1UL << HSEM_C1ISR_ISF12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1ISR_ISF12          HSEM_C1ISR_ISF12_Msk                         /*!<semaphore 12 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF13_Pos      (13U)

+#define HSEM_C1ISR_ISF13_Msk      (0x1UL << HSEM_C1ISR_ISF13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1ISR_ISF13          HSEM_C1ISR_ISF13_Msk                         /*!<semaphore 13 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF14_Pos      (14U)

+#define HSEM_C1ISR_ISF14_Msk      (0x1UL << HSEM_C1ISR_ISF14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1ISR_ISF14          HSEM_C1ISR_ISF14_Msk                         /*!<semaphore 14 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF15_Pos      (15U)

+#define HSEM_C1ISR_ISF15_Msk      (0x1UL << HSEM_C1ISR_ISF15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1ISR_ISF15          HSEM_C1ISR_ISF15_Msk                         /*!<semaphore 15 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF16_Pos      (16U)

+#define HSEM_C1ISR_ISF16_Msk      (0x1UL << HSEM_C1ISR_ISF16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1ISR_ISF16          HSEM_C1ISR_ISF16_Msk                         /*!<semaphore 16 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF17_Pos      (17U)

+#define HSEM_C1ISR_ISF17_Msk      (0x1UL << HSEM_C1ISR_ISF17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1ISR_ISF17          HSEM_C1ISR_ISF17_Msk                         /*!<semaphore 17 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF18_Pos      (18U)

+#define HSEM_C1ISR_ISF18_Msk      (0x1UL << HSEM_C1ISR_ISF18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1ISR_ISF18          HSEM_C1ISR_ISF18_Msk                         /*!<semaphore 18 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF19_Pos      (19U)

+#define HSEM_C1ISR_ISF19_Msk      (0x1UL << HSEM_C1ISR_ISF19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1ISR_ISF19          HSEM_C1ISR_ISF19_Msk                         /*!<semaphore 19 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF20_Pos      (20U)

+#define HSEM_C1ISR_ISF20_Msk      (0x1UL << HSEM_C1ISR_ISF20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1ISR_ISF20          HSEM_C1ISR_ISF20_Msk                         /*!<semaphore 20 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF21_Pos      (21U)

+#define HSEM_C1ISR_ISF21_Msk      (0x1UL << HSEM_C1ISR_ISF21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1ISR_ISF21          HSEM_C1ISR_ISF21_Msk                         /*!<semaphore 21 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF22_Pos      (22U)

+#define HSEM_C1ISR_ISF22_Msk      (0x1UL << HSEM_C1ISR_ISF22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1ISR_ISF22          HSEM_C1ISR_ISF22_Msk                         /*!<semaphore 22 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF23_Pos      (23U)

+#define HSEM_C1ISR_ISF23_Msk      (0x1UL << HSEM_C1ISR_ISF23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1ISR_ISF23          HSEM_C1ISR_ISF23_Msk                         /*!<semaphore 23 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF24_Pos      (24U)

+#define HSEM_C1ISR_ISF24_Msk      (0x1UL << HSEM_C1ISR_ISF24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1ISR_ISF24          HSEM_C1ISR_ISF24_Msk                         /*!<semaphore 24 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF25_Pos      (25U)

+#define HSEM_C1ISR_ISF25_Msk      (0x1UL << HSEM_C1ISR_ISF25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1ISR_ISF25          HSEM_C1ISR_ISF25_Msk                         /*!<semaphore 25 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF26_Pos      (26U)

+#define HSEM_C1ISR_ISF26_Msk      (0x1UL << HSEM_C1ISR_ISF26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1ISR_ISF26          HSEM_C1ISR_ISF26_Msk                         /*!<semaphore 26 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF27_Pos      (27U)

+#define HSEM_C1ISR_ISF27_Msk      (0x1UL << HSEM_C1ISR_ISF27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1ISR_ISF27          HSEM_C1ISR_ISF27_Msk                         /*!<semaphore 27 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF28_Pos      (28U)

+#define HSEM_C1ISR_ISF28_Msk      (0x1UL << HSEM_C1ISR_ISF28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1ISR_ISF28          HSEM_C1ISR_ISF28_Msk                         /*!<semaphore 28 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF29_Pos      (29U)

+#define HSEM_C1ISR_ISF29_Msk      (0x1UL << HSEM_C1ISR_ISF29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1ISR_ISF29          HSEM_C1ISR_ISF29_Msk                         /*!<semaphore 29 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF30_Pos      (30U)

+#define HSEM_C1ISR_ISF30_Msk      (0x1UL << HSEM_C1ISR_ISF30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1ISR_ISF30          HSEM_C1ISR_ISF30_Msk                         /*!<semaphore 30 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF31_Pos      (31U)

+#define HSEM_C1ISR_ISF31_Msk      (0x1UL << HSEM_C1ISR_ISF31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1ISR_ISF31          HSEM_C1ISR_ISF31_Msk                         /*!<semaphore 31 interrupt 0 status bit. */

+

+/********************  Bit definition for HSEM_C1MISR register  *****************/

+#define HSEM_C1MISR_MISF0_Pos     (0U)

+#define HSEM_C1MISR_MISF0_Msk     (0x1UL << HSEM_C1MISR_MISF0_Pos)             /*!< 0x00000001 */

+#define HSEM_C1MISR_MISF0         HSEM_C1MISR_MISF0_Msk                        /*!<semaphore 0 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF1_Pos     (1U)

+#define HSEM_C1MISR_MISF1_Msk     (0x1UL << HSEM_C1MISR_MISF1_Pos)             /*!< 0x00000002 */

+#define HSEM_C1MISR_MISF1         HSEM_C1MISR_MISF1_Msk                        /*!<semaphore 1 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF2_Pos     (2U)

+#define HSEM_C1MISR_MISF2_Msk     (0x1UL << HSEM_C1MISR_MISF2_Pos)             /*!< 0x00000004 */

+#define HSEM_C1MISR_MISF2         HSEM_C1MISR_MISF2_Msk                        /*!<semaphore 2 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF3_Pos     (3U)

+#define HSEM_C1MISR_MISF3_Msk     (0x1UL << HSEM_C1MISR_MISF3_Pos)             /*!< 0x00000008 */

+#define HSEM_C1MISR_MISF3         HSEM_C1MISR_MISF3_Msk                        /*!<semaphore 3 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF4_Pos     (4U)

+#define HSEM_C1MISR_MISF4_Msk     (0x1UL << HSEM_C1MISR_MISF4_Pos)             /*!< 0x00000010 */

+#define HSEM_C1MISR_MISF4         HSEM_C1MISR_MISF4_Msk                        /*!<semaphore 4 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF5_Pos     (5U)

+#define HSEM_C1MISR_MISF5_Msk     (0x1UL << HSEM_C1MISR_MISF5_Pos)             /*!< 0x00000020 */

+#define HSEM_C1MISR_MISF5         HSEM_C1MISR_MISF5_Msk                        /*!<semaphore 5 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF6_Pos     (6U)

+#define HSEM_C1MISR_MISF6_Msk     (0x1UL << HSEM_C1MISR_MISF6_Pos)             /*!< 0x00000040 */

+#define HSEM_C1MISR_MISF6         HSEM_C1MISR_MISF6_Msk                        /*!<semaphore 6 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF7_Pos     (7U)

+#define HSEM_C1MISR_MISF7_Msk     (0x1UL << HSEM_C1MISR_MISF7_Pos)             /*!< 0x00000080 */

+#define HSEM_C1MISR_MISF7         HSEM_C1MISR_MISF7_Msk                        /*!<semaphore 7 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF8_Pos     (8U)

+#define HSEM_C1MISR_MISF8_Msk     (0x1UL << HSEM_C1MISR_MISF8_Pos)             /*!< 0x00000100 */

+#define HSEM_C1MISR_MISF8         HSEM_C1MISR_MISF8_Msk                        /*!<semaphore 8 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF9_Pos     (9U)

+#define HSEM_C1MISR_MISF9_Msk     (0x1UL << HSEM_C1MISR_MISF9_Pos)             /*!< 0x00000200 */

+#define HSEM_C1MISR_MISF9         HSEM_C1MISR_MISF9_Msk                        /*!<semaphore 9 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF10_Pos    (10U)

+#define HSEM_C1MISR_MISF10_Msk    (0x1UL << HSEM_C1MISR_MISF10_Pos)            /*!< 0x00000400 */

+#define HSEM_C1MISR_MISF10        HSEM_C1MISR_MISF10_Msk                       /*!<semaphore 10 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF11_Pos    (11U)

+#define HSEM_C1MISR_MISF11_Msk    (0x1UL << HSEM_C1MISR_MISF11_Pos)            /*!< 0x00000800 */

+#define HSEM_C1MISR_MISF11        HSEM_C1MISR_MISF11_Msk                       /*!<semaphore 11 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF12_Pos    (12U)

+#define HSEM_C1MISR_MISF12_Msk    (0x1UL << HSEM_C1MISR_MISF12_Pos)            /*!< 0x00001000 */

+#define HSEM_C1MISR_MISF12        HSEM_C1MISR_MISF12_Msk                       /*!<semaphore 12 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF13_Pos    (13U)

+#define HSEM_C1MISR_MISF13_Msk    (0x1UL << HSEM_C1MISR_MISF13_Pos)            /*!< 0x00002000 */

+#define HSEM_C1MISR_MISF13        HSEM_C1MISR_MISF13_Msk                       /*!<semaphore 13 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF14_Pos    (14U)

+#define HSEM_C1MISR_MISF14_Msk    (0x1UL << HSEM_C1MISR_MISF14_Pos)            /*!< 0x00004000 */

+#define HSEM_C1MISR_MISF14        HSEM_C1MISR_MISF14_Msk                       /*!<semaphore 14 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF15_Pos    (15U)

+#define HSEM_C1MISR_MISF15_Msk    (0x1UL << HSEM_C1MISR_MISF15_Pos)            /*!< 0x00008000 */

+#define HSEM_C1MISR_MISF15        HSEM_C1MISR_MISF15_Msk                       /*!<semaphore 15 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF16_Pos    (16U)

+#define HSEM_C1MISR_MISF16_Msk    (0x1UL << HSEM_C1MISR_MISF16_Pos)            /*!< 0x00010000 */

+#define HSEM_C1MISR_MISF16        HSEM_C1MISR_MISF16_Msk                       /*!<semaphore 16 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF17_Pos    (17U)

+#define HSEM_C1MISR_MISF17_Msk    (0x1UL << HSEM_C1MISR_MISF17_Pos)            /*!< 0x00020000 */

+#define HSEM_C1MISR_MISF17        HSEM_C1MISR_MISF17_Msk                       /*!<semaphore 17 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF18_Pos    (18U)

+#define HSEM_C1MISR_MISF18_Msk    (0x1UL << HSEM_C1MISR_MISF18_Pos)            /*!< 0x00040000 */

+#define HSEM_C1MISR_MISF18        HSEM_C1MISR_MISF18_Msk                       /*!<semaphore 18 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF19_Pos    (19U)

+#define HSEM_C1MISR_MISF19_Msk    (0x1UL << HSEM_C1MISR_MISF19_Pos)            /*!< 0x00080000 */

+#define HSEM_C1MISR_MISF19        HSEM_C1MISR_MISF19_Msk                       /*!<semaphore 19 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF20_Pos    (20U)

+#define HSEM_C1MISR_MISF20_Msk    (0x1UL << HSEM_C1MISR_MISF20_Pos)            /*!< 0x00100000 */

+#define HSEM_C1MISR_MISF20        HSEM_C1MISR_MISF20_Msk                       /*!<semaphore 20 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF21_Pos    (21U)

+#define HSEM_C1MISR_MISF21_Msk    (0x1UL << HSEM_C1MISR_MISF21_Pos)            /*!< 0x00200000 */

+#define HSEM_C1MISR_MISF21        HSEM_C1MISR_MISF21_Msk                       /*!<semaphore 21 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF22_Pos    (22U)

+#define HSEM_C1MISR_MISF22_Msk    (0x1UL << HSEM_C1MISR_MISF22_Pos)            /*!< 0x00400000 */

+#define HSEM_C1MISR_MISF22        HSEM_C1MISR_MISF22_Msk                       /*!<semaphore 22 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF23_Pos    (23U)

+#define HSEM_C1MISR_MISF23_Msk    (0x1UL << HSEM_C1MISR_MISF23_Pos)            /*!< 0x00800000 */

+#define HSEM_C1MISR_MISF23        HSEM_C1MISR_MISF23_Msk                       /*!<semaphore 23 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF24_Pos    (24U)

+#define HSEM_C1MISR_MISF24_Msk    (0x1UL << HSEM_C1MISR_MISF24_Pos)            /*!< 0x01000000 */

+#define HSEM_C1MISR_MISF24        HSEM_C1MISR_MISF24_Msk                       /*!<semaphore 24 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF25_Pos    (25U)

+#define HSEM_C1MISR_MISF25_Msk    (0x1UL << HSEM_C1MISR_MISF25_Pos)            /*!< 0x02000000 */

+#define HSEM_C1MISR_MISF25        HSEM_C1MISR_MISF25_Msk                       /*!<semaphore 25 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF26_Pos    (26U)

+#define HSEM_C1MISR_MISF26_Msk    (0x1UL << HSEM_C1MISR_MISF26_Pos)            /*!< 0x04000000 */

+#define HSEM_C1MISR_MISF26        HSEM_C1MISR_MISF26_Msk                       /*!<semaphore 26 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF27_Pos    (27U)

+#define HSEM_C1MISR_MISF27_Msk    (0x1UL << HSEM_C1MISR_MISF27_Pos)            /*!< 0x08000000 */

+#define HSEM_C1MISR_MISF27        HSEM_C1MISR_MISF27_Msk                       /*!<semaphore 27 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF28_Pos    (28U)

+#define HSEM_C1MISR_MISF28_Msk    (0x1UL << HSEM_C1MISR_MISF28_Pos)            /*!< 0x10000000 */

+#define HSEM_C1MISR_MISF28        HSEM_C1MISR_MISF28_Msk                       /*!<semaphore 28 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF29_Pos    (29U)

+#define HSEM_C1MISR_MISF29_Msk    (0x1UL << HSEM_C1MISR_MISF29_Pos)            /*!< 0x20000000 */

+#define HSEM_C1MISR_MISF29        HSEM_C1MISR_MISF29_Msk                       /*!<semaphore 29 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF30_Pos    (30U)

+#define HSEM_C1MISR_MISF30_Msk    (0x1UL << HSEM_C1MISR_MISF30_Pos)            /*!< 0x40000000 */

+#define HSEM_C1MISR_MISF30        HSEM_C1MISR_MISF30_Msk                       /*!<semaphore 30 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF31_Pos    (31U)

+#define HSEM_C1MISR_MISF31_Msk    (0x1UL << HSEM_C1MISR_MISF31_Pos)            /*!< 0x80000000 */

+#define HSEM_C1MISR_MISF31        HSEM_C1MISR_MISF31_Msk                       /*!<semaphore 31 interrupt 0 masked status bit. */

+

+/********************  Bit definition for HSEM_C2IER register  *****************/

+#define HSEM_C2IER_ISE0_Pos       (0U)

+#define HSEM_C2IER_ISE0_Msk       (0x1UL << HSEM_C2IER_ISE0_Pos)               /*!< 0x00000001 */

+#define HSEM_C2IER_ISE0           HSEM_C2IER_ISE0_Msk                          /*!<semaphore 0 , interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE1_Pos       (1U)

+#define HSEM_C2IER_ISE1_Msk       (0x1UL << HSEM_C2IER_ISE1_Pos)               /*!< 0x00000002 */

+#define HSEM_C2IER_ISE1           HSEM_C2IER_ISE1_Msk                          /*!<semaphore 1 , interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE2_Pos       (2U)

+#define HSEM_C2IER_ISE2_Msk       (0x1UL << HSEM_C2IER_ISE2_Pos)               /*!< 0x00000004 */

+#define HSEM_C2IER_ISE2           HSEM_C2IER_ISE2_Msk                          /*!<semaphore 2 , interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE3_Pos       (3U)

+#define HSEM_C2IER_ISE3_Msk       (0x1UL << HSEM_C2IER_ISE3_Pos)               /*!< 0x00000008 */

+#define HSEM_C2IER_ISE3           HSEM_C2IER_ISE3_Msk                          /*!<semaphore 3 , interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE4_Pos       (4U)

+#define HSEM_C2IER_ISE4_Msk       (0x1UL << HSEM_C2IER_ISE4_Pos)               /*!< 0x00000010 */

+#define HSEM_C2IER_ISE4           HSEM_C2IER_ISE4_Msk                          /*!<semaphore 4 , interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE5_Pos       (5U)

+#define HSEM_C2IER_ISE5_Msk       (0x1UL << HSEM_C2IER_ISE5_Pos)               /*!< 0x00000020 */

+#define HSEM_C2IER_ISE5           HSEM_C2IER_ISE5_Msk                          /*!<semaphore 5 interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE6_Pos       (6U)

+#define HSEM_C2IER_ISE6_Msk       (0x1UL << HSEM_C2IER_ISE6_Pos)               /*!< 0x00000040 */

+#define HSEM_C2IER_ISE6           HSEM_C2IER_ISE6_Msk                          /*!<semaphore 6 interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE7_Pos       (7U)

+#define HSEM_C2IER_ISE7_Msk       (0x1UL << HSEM_C2IER_ISE7_Pos)               /*!< 0x00000080 */

+#define HSEM_C2IER_ISE7           HSEM_C2IER_ISE7_Msk                          /*!<semaphore 7 interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE8_Pos       (8U)

+#define HSEM_C2IER_ISE8_Msk       (0x1UL << HSEM_C2IER_ISE8_Pos)               /*!< 0x00000100 */

+#define HSEM_C2IER_ISE8           HSEM_C2IER_ISE8_Msk                          /*!<semaphore 8 interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE9_Pos       (9U)

+#define HSEM_C2IER_ISE9_Msk       (0x1UL << HSEM_C2IER_ISE9_Pos)               /*!< 0x00000200 */

+#define HSEM_C2IER_ISE9           HSEM_C2IER_ISE9_Msk                          /*!<semaphore 9 interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE10_Pos      (10U)

+#define HSEM_C2IER_ISE10_Msk      (0x1UL << HSEM_C2IER_ISE10_Pos)              /*!< 0x00000400 */

+#define HSEM_C2IER_ISE10          HSEM_C2IER_ISE10_Msk                         /*!<semaphore 10 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE11_Pos      (11U)

+#define HSEM_C2IER_ISE11_Msk      (0x1UL << HSEM_C2IER_ISE11_Pos)              /*!< 0x00000800 */

+#define HSEM_C2IER_ISE11          HSEM_C2IER_ISE11_Msk                         /*!<semaphore 11 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE12_Pos      (12U)

+#define HSEM_C2IER_ISE12_Msk      (0x1UL << HSEM_C2IER_ISE12_Pos)              /*!< 0x00001000 */

+#define HSEM_C2IER_ISE12          HSEM_C2IER_ISE12_Msk                         /*!<semaphore 12 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE13_Pos      (13U)

+#define HSEM_C2IER_ISE13_Msk      (0x1UL << HSEM_C2IER_ISE13_Pos)              /*!< 0x00002000 */

+#define HSEM_C2IER_ISE13          HSEM_C2IER_ISE13_Msk                         /*!<semaphore 13 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE14_Pos      (14U)

+#define HSEM_C2IER_ISE14_Msk      (0x1UL << HSEM_C2IER_ISE14_Pos)              /*!< 0x00004000 */

+#define HSEM_C2IER_ISE14          HSEM_C2IER_ISE14_Msk                         /*!<semaphore 14 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE15_Pos      (15U)

+#define HSEM_C2IER_ISE15_Msk      (0x1UL << HSEM_C2IER_ISE15_Pos)              /*!< 0x00008000 */

+#define HSEM_C2IER_ISE15          HSEM_C2IER_ISE15_Msk                         /*!<semaphore 15 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE16_Pos      (16U)

+#define HSEM_C2IER_ISE16_Msk      (0x1UL << HSEM_C2IER_ISE16_Pos)              /*!< 0x00010000 */

+#define HSEM_C2IER_ISE16          HSEM_C2IER_ISE16_Msk                         /*!<semaphore 16 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE17_Pos      (17U)

+#define HSEM_C2IER_ISE17_Msk      (0x1UL << HSEM_C2IER_ISE17_Pos)              /*!< 0x00020000 */

+#define HSEM_C2IER_ISE17          HSEM_C2IER_ISE17_Msk                         /*!<semaphore 17 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE18_Pos      (18U)

+#define HSEM_C2IER_ISE18_Msk      (0x1UL << HSEM_C2IER_ISE18_Pos)              /*!< 0x00040000 */

+#define HSEM_C2IER_ISE18          HSEM_C2IER_ISE18_Msk                         /*!<semaphore 18 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE19_Pos      (19U)

+#define HSEM_C2IER_ISE19_Msk      (0x1UL << HSEM_C2IER_ISE19_Pos)              /*!< 0x00080000 */

+#define HSEM_C2IER_ISE19          HSEM_C2IER_ISE19_Msk                         /*!<semaphore 19 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE20_Pos      (20U)

+#define HSEM_C2IER_ISE20_Msk      (0x1UL << HSEM_C2IER_ISE20_Pos)              /*!< 0x00100000 */

+#define HSEM_C2IER_ISE20          HSEM_C2IER_ISE20_Msk                         /*!<semaphore 20 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE21_Pos      (21U)

+#define HSEM_C2IER_ISE21_Msk      (0x1UL << HSEM_C2IER_ISE21_Pos)              /*!< 0x00200000 */

+#define HSEM_C2IER_ISE21          HSEM_C2IER_ISE21_Msk                         /*!<semaphore 21 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE22_Pos      (22U)

+#define HSEM_C2IER_ISE22_Msk      (0x1UL << HSEM_C2IER_ISE22_Pos)              /*!< 0x00400000 */

+#define HSEM_C2IER_ISE22          HSEM_C2IER_ISE22_Msk                         /*!<semaphore 22 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE23_Pos      (23U)

+#define HSEM_C2IER_ISE23_Msk      (0x1UL << HSEM_C2IER_ISE23_Pos)              /*!< 0x00800000 */

+#define HSEM_C2IER_ISE23          HSEM_C2IER_ISE23_Msk                         /*!<semaphore 23 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE24_Pos      (24U)

+#define HSEM_C2IER_ISE24_Msk      (0x1UL << HSEM_C2IER_ISE24_Pos)              /*!< 0x01000000 */

+#define HSEM_C2IER_ISE24          HSEM_C2IER_ISE24_Msk                         /*!<semaphore 24 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE25_Pos      (25U)

+#define HSEM_C2IER_ISE25_Msk      (0x1UL << HSEM_C2IER_ISE25_Pos)              /*!< 0x02000000 */

+#define HSEM_C2IER_ISE25          HSEM_C2IER_ISE25_Msk                         /*!<semaphore 25 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE26_Pos      (26U)

+#define HSEM_C2IER_ISE26_Msk      (0x1UL << HSEM_C2IER_ISE26_Pos)              /*!< 0x04000000 */

+#define HSEM_C2IER_ISE26          HSEM_C2IER_ISE26_Msk                         /*!<semaphore 26 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE27_Pos      (27U)

+#define HSEM_C2IER_ISE27_Msk      (0x1UL << HSEM_C2IER_ISE27_Pos)              /*!< 0x08000000 */

+#define HSEM_C2IER_ISE27          HSEM_C2IER_ISE27_Msk                         /*!<semaphore 27 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE28_Pos      (28U)

+#define HSEM_C2IER_ISE28_Msk      (0x1UL << HSEM_C2IER_ISE28_Pos)              /*!< 0x10000000 */

+#define HSEM_C2IER_ISE28          HSEM_C2IER_ISE28_Msk                         /*!<semaphore 28 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE29_Pos      (29U)

+#define HSEM_C2IER_ISE29_Msk      (0x1UL << HSEM_C2IER_ISE29_Pos)              /*!< 0x20000000 */

+#define HSEM_C2IER_ISE29          HSEM_C2IER_ISE29_Msk                         /*!<semaphore 29 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE30_Pos      (30U)

+#define HSEM_C2IER_ISE30_Msk      (0x1UL << HSEM_C2IER_ISE30_Pos)              /*!< 0x40000000 */

+#define HSEM_C2IER_ISE30          HSEM_C2IER_ISE30_Msk                         /*!<semaphore 30 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE31_Pos      (31U)

+#define HSEM_C2IER_ISE31_Msk      (0x1UL << HSEM_C2IER_ISE31_Pos)              /*!< 0x80000000 */

+#define HSEM_C2IER_ISE31          HSEM_C2IER_ISE31_Msk                         /*!<semaphore 31 interrupt 1 enable bit. */

+

+/********************  Bit definition for HSEM_C2ICR register  *****************/

+#define HSEM_C2ICR_ISC0_Pos       (0U)

+#define HSEM_C2ICR_ISC0_Msk       (0x1UL << HSEM_C2ICR_ISC0_Pos)               /*!< 0x00000001 */

+#define HSEM_C2ICR_ISC0           HSEM_C2ICR_ISC0_Msk                          /*!<semaphore 0 , interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC1_Pos       (1U)

+#define HSEM_C2ICR_ISC1_Msk       (0x1UL << HSEM_C2ICR_ISC1_Pos)               /*!< 0x00000002 */

+#define HSEM_C2ICR_ISC1           HSEM_C2ICR_ISC1_Msk                          /*!<semaphore 1 , interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC2_Pos       (2U)

+#define HSEM_C2ICR_ISC2_Msk       (0x1UL << HSEM_C2ICR_ISC2_Pos)               /*!< 0x00000004 */

+#define HSEM_C2ICR_ISC2           HSEM_C2ICR_ISC2_Msk                          /*!<semaphore 2 , interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC3_Pos       (3U)

+#define HSEM_C2ICR_ISC3_Msk       (0x1UL << HSEM_C2ICR_ISC3_Pos)               /*!< 0x00000008 */

+#define HSEM_C2ICR_ISC3           HSEM_C2ICR_ISC3_Msk                          /*!<semaphore 3 , interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC4_Pos       (4U)

+#define HSEM_C2ICR_ISC4_Msk       (0x1UL << HSEM_C2ICR_ISC4_Pos)               /*!< 0x00000010 */

+#define HSEM_C2ICR_ISC4           HSEM_C2ICR_ISC4_Msk                          /*!<semaphore 4 , interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC5_Pos       (5U)

+#define HSEM_C2ICR_ISC5_Msk       (0x1UL << HSEM_C2ICR_ISC5_Pos)               /*!< 0x00000020 */

+#define HSEM_C2ICR_ISC5           HSEM_C2ICR_ISC5_Msk                          /*!<semaphore 5 interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC6_Pos       (6U)

+#define HSEM_C2ICR_ISC6_Msk       (0x1UL << HSEM_C2ICR_ISC6_Pos)               /*!< 0x00000040 */

+#define HSEM_C2ICR_ISC6           HSEM_C2ICR_ISC6_Msk                          /*!<semaphore 6 interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC7_Pos       (7U)

+#define HSEM_C2ICR_ISC7_Msk       (0x1UL << HSEM_C2ICR_ISC7_Pos)               /*!< 0x00000080 */

+#define HSEM_C2ICR_ISC7           HSEM_C2ICR_ISC7_Msk                          /*!<semaphore 7 interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC8_Pos       (8U)

+#define HSEM_C2ICR_ISC8_Msk       (0x1UL << HSEM_C2ICR_ISC8_Pos)               /*!< 0x00000100 */

+#define HSEM_C2ICR_ISC8           HSEM_C2ICR_ISC8_Msk                          /*!<semaphore 8 interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC9_Pos       (9U)

+#define HSEM_C2ICR_ISC9_Msk       (0x1UL << HSEM_C2ICR_ISC9_Pos)               /*!< 0x00000200 */

+#define HSEM_C2ICR_ISC9           HSEM_C2ICR_ISC9_Msk                          /*!<semaphore 9 interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC10_Pos      (10U)

+#define HSEM_C2ICR_ISC10_Msk      (0x1UL << HSEM_C2ICR_ISC10_Pos)              /*!< 0x00000400 */

+#define HSEM_C2ICR_ISC10          HSEM_C2ICR_ISC10_Msk                         /*!<semaphore 10 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC11_Pos      (11U)

+#define HSEM_C2ICR_ISC11_Msk      (0x1UL << HSEM_C2ICR_ISC11_Pos)              /*!< 0x00000800 */

+#define HSEM_C2ICR_ISC11          HSEM_C2ICR_ISC11_Msk                         /*!<semaphore 11 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC12_Pos      (12U)

+#define HSEM_C2ICR_ISC12_Msk      (0x1UL << HSEM_C2ICR_ISC12_Pos)              /*!< 0x00001000 */

+#define HSEM_C2ICR_ISC12          HSEM_C2ICR_ISC12_Msk                         /*!<semaphore 12 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC13_Pos      (13U)

+#define HSEM_C2ICR_ISC13_Msk      (0x1UL << HSEM_C2ICR_ISC13_Pos)              /*!< 0x00002000 */

+#define HSEM_C2ICR_ISC13          HSEM_C2ICR_ISC13_Msk                         /*!<semaphore 13 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC14_Pos      (14U)

+#define HSEM_C2ICR_ISC14_Msk      (0x1UL << HSEM_C2ICR_ISC14_Pos)              /*!< 0x00004000 */

+#define HSEM_C2ICR_ISC14          HSEM_C2ICR_ISC14_Msk                         /*!<semaphore 14 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC15_Pos      (15U)

+#define HSEM_C2ICR_ISC15_Msk      (0x1UL << HSEM_C2ICR_ISC15_Pos)              /*!< 0x00008000 */

+#define HSEM_C2ICR_ISC15          HSEM_C2ICR_ISC15_Msk                         /*!<semaphore 15 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC16_Pos      (16U)

+#define HSEM_C2ICR_ISC16_Msk      (0x1UL << HSEM_C2ICR_ISC16_Pos)              /*!< 0x00010000 */

+#define HSEM_C2ICR_ISC16          HSEM_C2ICR_ISC16_Msk                         /*!<semaphore 16 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC17_Pos      (17U)

+#define HSEM_C2ICR_ISC17_Msk      (0x1UL << HSEM_C2ICR_ISC17_Pos)              /*!< 0x00020000 */

+#define HSEM_C2ICR_ISC17          HSEM_C2ICR_ISC17_Msk                         /*!<semaphore 17 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC18_Pos      (18U)

+#define HSEM_C2ICR_ISC18_Msk      (0x1UL << HSEM_C2ICR_ISC18_Pos)              /*!< 0x00040000 */

+#define HSEM_C2ICR_ISC18          HSEM_C2ICR_ISC18_Msk                         /*!<semaphore 18 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC19_Pos      (19U)

+#define HSEM_C2ICR_ISC19_Msk      (0x1UL << HSEM_C2ICR_ISC19_Pos)              /*!< 0x00080000 */

+#define HSEM_C2ICR_ISC19          HSEM_C2ICR_ISC19_Msk                         /*!<semaphore 19 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC20_Pos      (20U)

+#define HSEM_C2ICR_ISC20_Msk      (0x1UL << HSEM_C2ICR_ISC20_Pos)              /*!< 0x00100000 */

+#define HSEM_C2ICR_ISC20          HSEM_C2ICR_ISC20_Msk                         /*!<semaphore 20 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC21_Pos      (21U)

+#define HSEM_C2ICR_ISC21_Msk      (0x1UL << HSEM_C2ICR_ISC21_Pos)              /*!< 0x00200000 */

+#define HSEM_C2ICR_ISC21          HSEM_C2ICR_ISC21_Msk                         /*!<semaphore 21 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC22_Pos      (22U)

+#define HSEM_C2ICR_ISC22_Msk      (0x1UL << HSEM_C2ICR_ISC22_Pos)              /*!< 0x00400000 */

+#define HSEM_C2ICR_ISC22          HSEM_C2ICR_ISC22_Msk                         /*!<semaphore 22 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC23_Pos      (23U)

+#define HSEM_C2ICR_ISC23_Msk      (0x1UL << HSEM_C2ICR_ISC23_Pos)              /*!< 0x00800000 */

+#define HSEM_C2ICR_ISC23          HSEM_C2ICR_ISC23_Msk                         /*!<semaphore 23 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC24_Pos      (24U)

+#define HSEM_C2ICR_ISC24_Msk      (0x1UL << HSEM_C2ICR_ISC24_Pos)              /*!< 0x01000000 */

+#define HSEM_C2ICR_ISC24          HSEM_C2ICR_ISC24_Msk                         /*!<semaphore 24 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC25_Pos      (25U)

+#define HSEM_C2ICR_ISC25_Msk      (0x1UL << HSEM_C2ICR_ISC25_Pos)              /*!< 0x02000000 */

+#define HSEM_C2ICR_ISC25          HSEM_C2ICR_ISC25_Msk                         /*!<semaphore 25 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC26_Pos      (26U)

+#define HSEM_C2ICR_ISC26_Msk      (0x1UL << HSEM_C2ICR_ISC26_Pos)              /*!< 0x04000000 */

+#define HSEM_C2ICR_ISC26          HSEM_C2ICR_ISC26_Msk                         /*!<semaphore 26 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC27_Pos      (27U)

+#define HSEM_C2ICR_ISC27_Msk      (0x1UL << HSEM_C2ICR_ISC27_Pos)              /*!< 0x08000000 */

+#define HSEM_C2ICR_ISC27          HSEM_C2ICR_ISC27_Msk                         /*!<semaphore 27 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC28_Pos      (28U)

+#define HSEM_C2ICR_ISC28_Msk      (0x1UL << HSEM_C2ICR_ISC28_Pos)              /*!< 0x10000000 */

+#define HSEM_C2ICR_ISC28          HSEM_C2ICR_ISC28_Msk                         /*!<semaphore 28 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC29_Pos      (29U)

+#define HSEM_C2ICR_ISC29_Msk      (0x1UL << HSEM_C2ICR_ISC29_Pos)              /*!< 0x20000000 */

+#define HSEM_C2ICR_ISC29          HSEM_C2ICR_ISC29_Msk                         /*!<semaphore 29 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC30_Pos      (30U)

+#define HSEM_C2ICR_ISC30_Msk      (0x1UL << HSEM_C2ICR_ISC30_Pos)              /*!< 0x40000000 */

+#define HSEM_C2ICR_ISC30          HSEM_C2ICR_ISC30_Msk                         /*!<semaphore 30 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC31_Pos      (31U)

+#define HSEM_C2ICR_ISC31_Msk      (0x1UL << HSEM_C2ICR_ISC31_Pos)              /*!< 0x80000000 */

+#define HSEM_C2ICR_ISC31          HSEM_C2ICR_ISC31_Msk                         /*!<semaphore 31 interrupt 1 clear bit. */

+

+/********************  Bit definition for HSEM_C2ISR register  *****************/

+#define HSEM_C2ISR_ISF0_Pos       (0U)

+#define HSEM_C2ISR_ISF0_Msk       (0x1UL << HSEM_C2ISR_ISF0_Pos)               /*!< 0x00000001 */

+#define HSEM_C2ISR_ISF0           HSEM_C2ISR_ISF0_Msk                          /*!<semaphore 0 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF1_Pos       (1U)

+#define HSEM_C2ISR_ISF1_Msk       (0x1UL << HSEM_C2ISR_ISF1_Pos)               /*!< 0x00000002 */

+#define HSEM_C2ISR_ISF1           HSEM_C2ISR_ISF1_Msk                          /*!<semaphore 1 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF2_Pos       (2U)

+#define HSEM_C2ISR_ISF2_Msk       (0x1UL << HSEM_C2ISR_ISF2_Pos)               /*!< 0x00000004 */

+#define HSEM_C2ISR_ISF2           HSEM_C2ISR_ISF2_Msk                          /*!<semaphore 2 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF3_Pos       (3U)

+#define HSEM_C2ISR_ISF3_Msk       (0x1UL << HSEM_C2ISR_ISF3_Pos)               /*!< 0x00000008 */

+#define HSEM_C2ISR_ISF3           HSEM_C2ISR_ISF3_Msk                          /*!<semaphore 3 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF4_Pos       (4U)

+#define HSEM_C2ISR_ISF4_Msk       (0x1UL << HSEM_C2ISR_ISF4_Pos)               /*!< 0x00000010 */

+#define HSEM_C2ISR_ISF4           HSEM_C2ISR_ISF4_Msk                          /*!<semaphore 4 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF5_Pos       (5U)

+#define HSEM_C2ISR_ISF5_Msk       (0x1UL << HSEM_C2ISR_ISF5_Pos)               /*!< 0x00000020 */

+#define HSEM_C2ISR_ISF5           HSEM_C2ISR_ISF5_Msk                          /*!<semaphore 5 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF6_Pos       (6U)

+#define HSEM_C2ISR_ISF6_Msk       (0x1UL << HSEM_C2ISR_ISF6_Pos)               /*!< 0x00000040 */

+#define HSEM_C2ISR_ISF6           HSEM_C2ISR_ISF6_Msk                          /*!<semaphore 6 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF7_Pos       (7U)

+#define HSEM_C2ISR_ISF7_Msk       (0x1UL << HSEM_C2ISR_ISF7_Pos)               /*!< 0x00000080 */

+#define HSEM_C2ISR_ISF7           HSEM_C2ISR_ISF7_Msk                          /*!<semaphore 7 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF8_Pos       (8U)

+#define HSEM_C2ISR_ISF8_Msk       (0x1UL << HSEM_C2ISR_ISF8_Pos)               /*!< 0x00000100 */

+#define HSEM_C2ISR_ISF8           HSEM_C2ISR_ISF8_Msk                          /*!<semaphore 8 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF9_Pos       (9U)

+#define HSEM_C2ISR_ISF9_Msk       (0x1UL << HSEM_C2ISR_ISF9_Pos)               /*!< 0x00000200 */

+#define HSEM_C2ISR_ISF9           HSEM_C2ISR_ISF9_Msk                          /*!<semaphore 9 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF10_Pos      (10U)

+#define HSEM_C2ISR_ISF10_Msk      (0x1UL << HSEM_C2ISR_ISF10_Pos)              /*!< 0x00000400 */

+#define HSEM_C2ISR_ISF10          HSEM_C2ISR_ISF10_Msk                         /*!<semaphore 10 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF11_Pos      (11U)

+#define HSEM_C2ISR_ISF11_Msk      (0x1UL << HSEM_C2ISR_ISF11_Pos)              /*!< 0x00000800 */

+#define HSEM_C2ISR_ISF11          HSEM_C2ISR_ISF11_Msk                         /*!<semaphore 11 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF12_Pos      (12U)

+#define HSEM_C2ISR_ISF12_Msk      (0x1UL << HSEM_C2ISR_ISF12_Pos)              /*!< 0x00001000 */

+#define HSEM_C2ISR_ISF12          HSEM_C2ISR_ISF12_Msk                         /*!<semaphore 12 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF13_Pos      (13U)

+#define HSEM_C2ISR_ISF13_Msk      (0x1UL << HSEM_C2ISR_ISF13_Pos)              /*!< 0x00002000 */

+#define HSEM_C2ISR_ISF13          HSEM_C2ISR_ISF13_Msk                         /*!<semaphore 13 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF14_Pos      (14U)

+#define HSEM_C2ISR_ISF14_Msk      (0x1UL << HSEM_C2ISR_ISF14_Pos)              /*!< 0x00004000 */

+#define HSEM_C2ISR_ISF14          HSEM_C2ISR_ISF14_Msk                         /*!<semaphore 14 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF15_Pos      (15U)

+#define HSEM_C2ISR_ISF15_Msk      (0x1UL << HSEM_C2ISR_ISF15_Pos)              /*!< 0x00008000 */

+#define HSEM_C2ISR_ISF15          HSEM_C2ISR_ISF15_Msk                         /*!<semaphore 15 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF16_Pos      (16U)

+#define HSEM_C2ISR_ISF16_Msk      (0x1UL << HSEM_C2ISR_ISF16_Pos)              /*!< 0x00010000 */

+#define HSEM_C2ISR_ISF16          HSEM_C2ISR_ISF16_Msk                         /*!<semaphore 16 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF17_Pos      (17U)

+#define HSEM_C2ISR_ISF17_Msk      (0x1UL << HSEM_C2ISR_ISF17_Pos)              /*!< 0x00020000 */

+#define HSEM_C2ISR_ISF17          HSEM_C2ISR_ISF17_Msk                         /*!<semaphore 17 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF18_Pos      (18U)

+#define HSEM_C2ISR_ISF18_Msk      (0x1UL << HSEM_C2ISR_ISF18_Pos)              /*!< 0x00040000 */

+#define HSEM_C2ISR_ISF18          HSEM_C2ISR_ISF18_Msk                         /*!<semaphore 18 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF19_Pos      (19U)

+#define HSEM_C2ISR_ISF19_Msk      (0x1UL << HSEM_C2ISR_ISF19_Pos)              /*!< 0x00080000 */

+#define HSEM_C2ISR_ISF19          HSEM_C2ISR_ISF19_Msk                         /*!<semaphore 19 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF20_Pos      (20U)

+#define HSEM_C2ISR_ISF20_Msk      (0x1UL << HSEM_C2ISR_ISF20_Pos)              /*!< 0x00100000 */

+#define HSEM_C2ISR_ISF20          HSEM_C2ISR_ISF20_Msk                         /*!<semaphore 20 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF21_Pos      (21U)

+#define HSEM_C2ISR_ISF21_Msk      (0x1UL << HSEM_C2ISR_ISF21_Pos)              /*!< 0x00200000 */

+#define HSEM_C2ISR_ISF21          HSEM_C2ISR_ISF21_Msk                         /*!<semaphore 21 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF22_Pos      (22U)

+#define HSEM_C2ISR_ISF22_Msk      (0x1UL << HSEM_C2ISR_ISF22_Pos)              /*!< 0x00400000 */

+#define HSEM_C2ISR_ISF22          HSEM_C2ISR_ISF22_Msk                         /*!<semaphore 22 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF23_Pos      (23U)

+#define HSEM_C2ISR_ISF23_Msk      (0x1UL << HSEM_C2ISR_ISF23_Pos)              /*!< 0x00800000 */

+#define HSEM_C2ISR_ISF23          HSEM_C2ISR_ISF23_Msk                         /*!<semaphore 23 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF24_Pos      (24U)

+#define HSEM_C2ISR_ISF24_Msk      (0x1UL << HSEM_C2ISR_ISF24_Pos)              /*!< 0x01000000 */

+#define HSEM_C2ISR_ISF24          HSEM_C2ISR_ISF24_Msk                         /*!<semaphore 24 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF25_Pos      (25U)

+#define HSEM_C2ISR_ISF25_Msk      (0x1UL << HSEM_C2ISR_ISF25_Pos)              /*!< 0x02000000 */

+#define HSEM_C2ISR_ISF25          HSEM_C2ISR_ISF25_Msk                         /*!<semaphore 25 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF26_Pos      (26U)

+#define HSEM_C2ISR_ISF26_Msk      (0x1UL << HSEM_C2ISR_ISF26_Pos)              /*!< 0x04000000 */

+#define HSEM_C2ISR_ISF26          HSEM_C2ISR_ISF26_Msk                         /*!<semaphore 26 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF27_Pos      (27U)

+#define HSEM_C2ISR_ISF27_Msk      (0x1UL << HSEM_C2ISR_ISF27_Pos)              /*!< 0x08000000 */

+#define HSEM_C2ISR_ISF27          HSEM_C2ISR_ISF27_Msk                         /*!<semaphore 27 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF28_Pos      (28U)

+#define HSEM_C2ISR_ISF28_Msk      (0x1UL << HSEM_C2ISR_ISF28_Pos)              /*!< 0x10000000 */

+#define HSEM_C2ISR_ISF28          HSEM_C2ISR_ISF28_Msk                         /*!<semaphore 28 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF29_Pos      (29U)

+#define HSEM_C2ISR_ISF29_Msk      (0x1UL << HSEM_C2ISR_ISF29_Pos)              /*!< 0x20000000 */

+#define HSEM_C2ISR_ISF29          HSEM_C2ISR_ISF29_Msk                         /*!<semaphore 29 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF30_Pos      (30U)

+#define HSEM_C2ISR_ISF30_Msk      (0x1UL << HSEM_C2ISR_ISF30_Pos)              /*!< 0x40000000 */

+#define HSEM_C2ISR_ISF30          HSEM_C2ISR_ISF30_Msk                         /*!<semaphore 30 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF31_Pos      (31U)

+#define HSEM_C2ISR_ISF31_Msk      (0x1UL << HSEM_C2ISR_ISF31_Pos)              /*!< 0x80000000 */

+#define HSEM_C2ISR_ISF31          HSEM_C2ISR_ISF31_Msk                         /*!<semaphore 31 interrupt 1 status bit. */

+

+/********************  Bit definition for HSEM_C2MISR register  *****************/

+#define HSEM_C2MISR_MISF0_Pos     (0U)

+#define HSEM_C2MISR_MISF0_Msk     (0x1UL << HSEM_C2MISR_MISF0_Pos)             /*!< 0x00000001 */

+#define HSEM_C2MISR_MISF0         HSEM_C2MISR_MISF0_Msk                        /*!<semaphore 0 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF1_Pos     (1U)

+#define HSEM_C2MISR_MISF1_Msk     (0x1UL << HSEM_C2MISR_MISF1_Pos)             /*!< 0x00000002 */

+#define HSEM_C2MISR_MISF1         HSEM_C2MISR_MISF1_Msk                        /*!<semaphore 1 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF2_Pos     (2U)

+#define HSEM_C2MISR_MISF2_Msk     (0x1UL << HSEM_C2MISR_MISF2_Pos)             /*!< 0x00000004 */

+#define HSEM_C2MISR_MISF2         HSEM_C2MISR_MISF2_Msk                        /*!<semaphore 2 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF3_Pos     (3U)

+#define HSEM_C2MISR_MISF3_Msk     (0x1UL << HSEM_C2MISR_MISF3_Pos)             /*!< 0x00000008 */

+#define HSEM_C2MISR_MISF3         HSEM_C2MISR_MISF3_Msk                        /*!<semaphore 3 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF4_Pos     (4U)

+#define HSEM_C2MISR_MISF4_Msk     (0x1UL << HSEM_C2MISR_MISF4_Pos)             /*!< 0x00000010 */

+#define HSEM_C2MISR_MISF4         HSEM_C2MISR_MISF4_Msk                        /*!<semaphore 4 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF5_Pos     (5U)

+#define HSEM_C2MISR_MISF5_Msk     (0x1UL << HSEM_C2MISR_MISF5_Pos)             /*!< 0x00000020 */

+#define HSEM_C2MISR_MISF5         HSEM_C2MISR_MISF5_Msk                        /*!<semaphore 5 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF6_Pos     (6U)

+#define HSEM_C2MISR_MISF6_Msk     (0x1UL << HSEM_C2MISR_MISF6_Pos)             /*!< 0x00000040 */

+#define HSEM_C2MISR_MISF6         HSEM_C2MISR_MISF6_Msk                        /*!<semaphore 6 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF7_Pos     (7U)

+#define HSEM_C2MISR_MISF7_Msk     (0x1UL << HSEM_C2MISR_MISF7_Pos)             /*!< 0x00000080 */

+#define HSEM_C2MISR_MISF7         HSEM_C2MISR_MISF7_Msk                        /*!<semaphore 7 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF8_Pos     (8U)

+#define HSEM_C2MISR_MISF8_Msk     (0x1UL << HSEM_C2MISR_MISF8_Pos)             /*!< 0x00000100 */

+#define HSEM_C2MISR_MISF8         HSEM_C2MISR_MISF8_Msk                        /*!<semaphore 8 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF9_Pos     (9U)

+#define HSEM_C2MISR_MISF9_Msk     (0x1UL << HSEM_C2MISR_MISF9_Pos)             /*!< 0x00000200 */

+#define HSEM_C2MISR_MISF9         HSEM_C2MISR_MISF9_Msk                        /*!<semaphore 9 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF10_Pos    (10U)

+#define HSEM_C2MISR_MISF10_Msk    (0x1UL << HSEM_C2MISR_MISF10_Pos)            /*!< 0x00000400 */

+#define HSEM_C2MISR_MISF10        HSEM_C2MISR_MISF10_Msk                       /*!<semaphore 10 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF11_Pos    (11U)

+#define HSEM_C2MISR_MISF11_Msk    (0x1UL << HSEM_C2MISR_MISF11_Pos)            /*!< 0x00000800 */

+#define HSEM_C2MISR_MISF11        HSEM_C2MISR_MISF11_Msk                       /*!<semaphore 11 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF12_Pos    (12U)

+#define HSEM_C2MISR_MISF12_Msk    (0x1UL << HSEM_C2MISR_MISF12_Pos)            /*!< 0x00001000 */

+#define HSEM_C2MISR_MISF12        HSEM_C2MISR_MISF12_Msk                       /*!<semaphore 12 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF13_Pos    (13U)

+#define HSEM_C2MISR_MISF13_Msk    (0x1UL << HSEM_C2MISR_MISF13_Pos)            /*!< 0x00002000 */

+#define HSEM_C2MISR_MISF13        HSEM_C2MISR_MISF13_Msk                       /*!<semaphore 13 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF14_Pos    (14U)

+#define HSEM_C2MISR_MISF14_Msk    (0x1UL << HSEM_C2MISR_MISF14_Pos)            /*!< 0x00004000 */

+#define HSEM_C2MISR_MISF14        HSEM_C2MISR_MISF14_Msk                       /*!<semaphore 14 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF15_Pos    (15U)

+#define HSEM_C2MISR_MISF15_Msk    (0x1UL << HSEM_C2MISR_MISF15_Pos)            /*!< 0x00008000 */

+#define HSEM_C2MISR_MISF15        HSEM_C2MISR_MISF15_Msk                       /*!<semaphore 15 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF16_Pos    (16U)

+#define HSEM_C2MISR_MISF16_Msk    (0x1UL << HSEM_C2MISR_MISF16_Pos)            /*!< 0x00010000 */

+#define HSEM_C2MISR_MISF16        HSEM_C2MISR_MISF16_Msk                       /*!<semaphore 16 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF17_Pos    (17U)

+#define HSEM_C2MISR_MISF17_Msk    (0x1UL << HSEM_C2MISR_MISF17_Pos)            /*!< 0x00020000 */

+#define HSEM_C2MISR_MISF17        HSEM_C2MISR_MISF17_Msk                       /*!<semaphore 17 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF18_Pos    (18U)

+#define HSEM_C2MISR_MISF18_Msk    (0x1UL << HSEM_C2MISR_MISF18_Pos)            /*!< 0x00040000 */

+#define HSEM_C2MISR_MISF18        HSEM_C2MISR_MISF18_Msk                       /*!<semaphore 18 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF19_Pos    (19U)

+#define HSEM_C2MISR_MISF19_Msk    (0x1UL << HSEM_C2MISR_MISF19_Pos)            /*!< 0x00080000 */

+#define HSEM_C2MISR_MISF19        HSEM_C2MISR_MISF19_Msk                       /*!<semaphore 19 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF20_Pos    (20U)

+#define HSEM_C2MISR_MISF20_Msk    (0x1UL << HSEM_C2MISR_MISF20_Pos)            /*!< 0x00100000 */

+#define HSEM_C2MISR_MISF20        HSEM_C2MISR_MISF20_Msk                       /*!<semaphore 20 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF21_Pos    (21U)

+#define HSEM_C2MISR_MISF21_Msk    (0x1UL << HSEM_C2MISR_MISF21_Pos)            /*!< 0x00200000 */

+#define HSEM_C2MISR_MISF21        HSEM_C2MISR_MISF21_Msk                       /*!<semaphore 21 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF22_Pos    (22U)

+#define HSEM_C2MISR_MISF22_Msk    (0x1UL << HSEM_C2MISR_MISF22_Pos)            /*!< 0x00400000 */

+#define HSEM_C2MISR_MISF22        HSEM_C2MISR_MISF22_Msk                       /*!<semaphore 22 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF23_Pos    (23U)

+#define HSEM_C2MISR_MISF23_Msk    (0x1UL << HSEM_C2MISR_MISF23_Pos)            /*!< 0x00800000 */

+#define HSEM_C2MISR_MISF23        HSEM_C2MISR_MISF23_Msk                       /*!<semaphore 23 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF24_Pos    (24U)

+#define HSEM_C2MISR_MISF24_Msk    (0x1UL << HSEM_C2MISR_MISF24_Pos)            /*!< 0x01000000 */

+#define HSEM_C2MISR_MISF24        HSEM_C2MISR_MISF24_Msk                       /*!<semaphore 24 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF25_Pos    (25U)

+#define HSEM_C2MISR_MISF25_Msk    (0x1UL << HSEM_C2MISR_MISF25_Pos)            /*!< 0x02000000 */

+#define HSEM_C2MISR_MISF25        HSEM_C2MISR_MISF25_Msk                       /*!<semaphore 25 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF26_Pos    (26U)

+#define HSEM_C2MISR_MISF26_Msk    (0x1UL << HSEM_C2MISR_MISF26_Pos)            /*!< 0x04000000 */

+#define HSEM_C2MISR_MISF26        HSEM_C2MISR_MISF26_Msk                       /*!<semaphore 26 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF27_Pos    (27U)

+#define HSEM_C2MISR_MISF27_Msk    (0x1UL << HSEM_C2MISR_MISF27_Pos)            /*!< 0x08000000 */

+#define HSEM_C2MISR_MISF27        HSEM_C2MISR_MISF27_Msk                       /*!<semaphore 27 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF28_Pos    (28U)

+#define HSEM_C2MISR_MISF28_Msk    (0x1UL << HSEM_C2MISR_MISF28_Pos)            /*!< 0x10000000 */

+#define HSEM_C2MISR_MISF28        HSEM_C2MISR_MISF28_Msk                       /*!<semaphore 28 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF29_Pos    (29U)

+#define HSEM_C2MISR_MISF29_Msk    (0x1UL << HSEM_C2MISR_MISF29_Pos)            /*!< 0x20000000 */

+#define HSEM_C2MISR_MISF29        HSEM_C2MISR_MISF29_Msk                       /*!<semaphore 29 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF30_Pos    (30U)

+#define HSEM_C2MISR_MISF30_Msk    (0x1UL << HSEM_C2MISR_MISF30_Pos)            /*!< 0x40000000 */

+#define HSEM_C2MISR_MISF30        HSEM_C2MISR_MISF30_Msk                       /*!<semaphore 30 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF31_Pos    (31U)

+#define HSEM_C2MISR_MISF31_Msk    (0x1UL << HSEM_C2MISR_MISF31_Pos)            /*!< 0x80000000 */

+#define HSEM_C2MISR_MISF31        HSEM_C2MISR_MISF31_Msk                       /*!<semaphore 31 interrupt 1 masked status bit. */

+/********************  Bit definition for HSEM_CR register  *****************/

+#define HSEM_CR_COREID_Pos        (8U)

+#define HSEM_CR_COREID_Msk        (0xFFUL << HSEM_CR_COREID_Pos)               /*!< 0x0000FF00 */

+#define HSEM_CR_COREID            HSEM_CR_COREID_Msk                           /*!<CoreID of semaphores to be cleared. */

+#define HSEM_CR_KEY_Pos           (16U)

+#define HSEM_CR_KEY_Msk           (0xFFFFUL << HSEM_CR_KEY_Pos)                /*!< 0xFFFF0000 */

+#define HSEM_CR_KEY               HSEM_CR_KEY_Msk                              /*!<semaphores clear key. */

+

+/********************  Bit definition for HSEM_KEYR register  *****************/

+#define HSEM_KEYR_KEY_Pos         (16U)

+#define HSEM_KEYR_KEY_Msk         (0xFFFFUL << HSEM_KEYR_KEY_Pos)              /*!< 0xFFFF0000 */

+#define HSEM_KEYR_KEY             HSEM_KEYR_KEY_Msk                            /*!<semaphores clear key. */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      Inter-integrated Circuit Interface (I2C)              */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for I2C_CR1 register  *******************/

+#define I2C_CR1_PE_Pos               (0U)

+#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */

+#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */

+#define I2C_CR1_TXIE_Pos             (1U)

+#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */

+#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */

+#define I2C_CR1_RXIE_Pos             (2U)

+#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */

+#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */

+#define I2C_CR1_ADDRIE_Pos           (3U)

+#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */

+#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */

+#define I2C_CR1_NACKIE_Pos           (4U)

+#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */

+#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */

+#define I2C_CR1_STOPIE_Pos           (5U)

+#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */

+#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */

+#define I2C_CR1_TCIE_Pos             (6U)

+#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */

+#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */

+#define I2C_CR1_ERRIE_Pos            (7U)

+#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */

+#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */

+#define I2C_CR1_DNF_Pos              (8U)

+#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */

+#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */

+#define I2C_CR1_ANFOFF_Pos           (12U)

+#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */

+#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */

+#define I2C_CR1_TXDMAEN_Pos          (14U)

+#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */

+#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */

+#define I2C_CR1_RXDMAEN_Pos          (15U)

+#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */

+#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */

+#define I2C_CR1_SBC_Pos              (16U)

+#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */

+#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */

+#define I2C_CR1_NOSTRETCH_Pos        (17U)

+#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */

+#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */

+#define I2C_CR1_WUPEN_Pos            (18U)

+#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */

+#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */

+#define I2C_CR1_GCEN_Pos             (19U)

+#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */

+#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */

+#define I2C_CR1_SMBHEN_Pos           (20U)

+#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */

+#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */

+#define I2C_CR1_SMBDEN_Pos           (21U)

+#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */

+#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */

+#define I2C_CR1_ALERTEN_Pos          (22U)

+#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */

+#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */

+#define I2C_CR1_PECEN_Pos            (23U)

+#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */

+#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */

+

+/******************  Bit definition for I2C_CR2 register  ********************/

+#define I2C_CR2_SADD_Pos             (0U)

+#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */

+#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */

+#define I2C_CR2_RD_WRN_Pos           (10U)

+#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */

+#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */

+#define I2C_CR2_ADD10_Pos            (11U)

+#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */

+#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */

+#define I2C_CR2_HEAD10R_Pos          (12U)

+#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */

+#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */

+#define I2C_CR2_START_Pos            (13U)

+#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */

+#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */

+#define I2C_CR2_STOP_Pos             (14U)

+#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */

+#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */

+#define I2C_CR2_NACK_Pos             (15U)

+#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */

+#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */

+#define I2C_CR2_NBYTES_Pos           (16U)

+#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */

+#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */

+#define I2C_CR2_RELOAD_Pos           (24U)

+#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */

+#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */

+#define I2C_CR2_AUTOEND_Pos          (25U)

+#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */

+#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */

+#define I2C_CR2_PECBYTE_Pos          (26U)

+#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */

+#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */

+

+/*******************  Bit definition for I2C_OAR1 register  ******************/

+#define I2C_OAR1_OA1_Pos             (0U)

+#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */

+#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */

+#define I2C_OAR1_OA1MODE_Pos         (10U)

+#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */

+#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */

+#define I2C_OAR1_OA1EN_Pos           (15U)

+#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */

+#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */

+

+/*******************  Bit definition for I2C_OAR2 register  ******************/

+#define I2C_OAR2_OA2_Pos             (1U)

+#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */

+#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */

+#define I2C_OAR2_OA2MSK_Pos          (8U)

+#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */

+#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */

+#define I2C_OAR2_OA2NOMASK           0x00000000UL                              /*!< No mask */

+#define I2C_OAR2_OA2MASK01_Pos       (8U)

+#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */

+#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared */

+#define I2C_OAR2_OA2MASK02_Pos       (9U)

+#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */

+#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */

+#define I2C_OAR2_OA2MASK03_Pos       (8U)

+#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */

+#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */

+#define I2C_OAR2_OA2MASK04_Pos       (10U)

+#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */

+#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */

+#define I2C_OAR2_OA2MASK05_Pos       (8U)

+#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */

+#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */

+#define I2C_OAR2_OA2MASK06_Pos       (9U)

+#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */

+#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared */

+#define I2C_OAR2_OA2MASK07_Pos       (8U)

+#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */

+#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done */

+#define I2C_OAR2_OA2EN_Pos           (15U)

+#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */

+#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */

+

+/*******************  Bit definition for I2C_TIMINGR register *******************/

+#define I2C_TIMINGR_SCLL_Pos         (0U)

+#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */

+#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */

+#define I2C_TIMINGR_SCLH_Pos         (8U)

+#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */

+#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */

+#define I2C_TIMINGR_SDADEL_Pos       (16U)

+#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */

+#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */

+#define I2C_TIMINGR_SCLDEL_Pos       (20U)

+#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */

+#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */

+#define I2C_TIMINGR_PRESC_Pos        (28U)

+#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */

+#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */

+

+/******************* Bit definition for I2C_TIMEOUTR register *******************/

+#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)

+#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */

+#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */

+#define I2C_TIMEOUTR_TIDLE_Pos       (12U)

+#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */

+#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */

+#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)

+#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */

+#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */

+#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)

+#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */

+#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/

+#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)

+#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */

+#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */

+

+/******************  Bit definition for I2C_ISR register  *********************/

+#define I2C_ISR_TXE_Pos              (0U)

+#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */

+#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */

+#define I2C_ISR_TXIS_Pos             (1U)

+#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */

+#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */

+#define I2C_ISR_RXNE_Pos             (2U)

+#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */

+#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */

+#define I2C_ISR_ADDR_Pos             (3U)

+#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */

+#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/

+#define I2C_ISR_NACKF_Pos            (4U)

+#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */

+#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */

+#define I2C_ISR_STOPF_Pos            (5U)

+#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */

+#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */

+#define I2C_ISR_TC_Pos               (6U)

+#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */

+#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */

+#define I2C_ISR_TCR_Pos              (7U)

+#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */

+#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */

+#define I2C_ISR_BERR_Pos             (8U)

+#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */

+#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */

+#define I2C_ISR_ARLO_Pos             (9U)

+#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */

+#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */

+#define I2C_ISR_OVR_Pos              (10U)

+#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */

+#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */

+#define I2C_ISR_PECERR_Pos           (11U)

+#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */

+#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */

+#define I2C_ISR_TIMEOUT_Pos          (12U)

+#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */

+#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */

+#define I2C_ISR_ALERT_Pos            (13U)

+#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */

+#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */

+#define I2C_ISR_BUSY_Pos             (15U)

+#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */

+#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */

+#define I2C_ISR_DIR_Pos              (16U)

+#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */

+#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */

+#define I2C_ISR_ADDCODE_Pos          (17U)

+#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */

+#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */

+

+/******************  Bit definition for I2C_ICR register  *********************/

+#define I2C_ICR_ADDRCF_Pos           (3U)

+#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */

+#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */

+#define I2C_ICR_NACKCF_Pos           (4U)

+#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */

+#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */

+#define I2C_ICR_STOPCF_Pos           (5U)

+#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */

+#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */

+#define I2C_ICR_BERRCF_Pos           (8U)

+#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */

+#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */

+#define I2C_ICR_ARLOCF_Pos           (9U)

+#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */

+#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */

+#define I2C_ICR_OVRCF_Pos            (10U)

+#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */

+#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */

+#define I2C_ICR_PECCF_Pos            (11U)

+#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */

+#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */

+#define I2C_ICR_TIMOUTCF_Pos         (12U)

+#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */

+#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */

+#define I2C_ICR_ALERTCF_Pos          (13U)

+#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */

+#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */

+

+/******************  Bit definition for I2C_PECR register  *********************/

+#define I2C_PECR_PEC_Pos             (0U)

+#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */

+#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */

+

+/******************  Bit definition for I2C_RXDR register  *********************/

+#define I2C_RXDR_RXDATA_Pos          (0U)

+#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */

+#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */

+

+/******************  Bit definition for I2C_TXDR register  *********************/

+#define I2C_TXDR_TXDATA_Pos          (0U)

+#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */

+#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           Independent WATCHDOG                             */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for IWDG_KR register  ********************/

+#define IWDG_KR_KEY_Pos      (0U)

+#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */

+#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */

+

+/*******************  Bit definition for IWDG_PR register  ********************/

+#define IWDG_PR_PR_Pos       (0U)

+#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */

+#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */

+#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */

+#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */

+#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */

+

+/*******************  Bit definition for IWDG_RLR register  *******************/

+#define IWDG_RLR_RL_Pos      (0U)

+#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */

+#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */

+

+/*******************  Bit definition for IWDG_SR register  ********************/

+#define IWDG_SR_PVU_Pos      (0U)

+#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */

+#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */

+#define IWDG_SR_RVU_Pos      (1U)

+#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */

+#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */

+#define IWDG_SR_WVU_Pos      (2U)

+#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */

+#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */

+

+/*******************  Bit definition for IWDG_KR register  ********************/

+#define IWDG_WINR_WIN_Pos    (0U)

+#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */

+#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */

+

+/******************************************************************************/

+/*                                                                            */

+/*                        JPEG Encoder/Decoder                                */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for CONFR0 register  ********************/

+#define JPEG_CONFR0_START_Pos           (0U)

+#define JPEG_CONFR0_START_Msk           (0x1UL << JPEG_CONFR0_START_Pos)       /*!< 0x00000001 */

+#define JPEG_CONFR0_START               JPEG_CONFR0_START_Msk                  /*!<Start/Stop bit */

+

+/********************  Bit definition for CONFR1 register  ********************/

+#define JPEG_CONFR1_NF_Pos              (0U)

+#define JPEG_CONFR1_NF_Msk              (0x3UL << JPEG_CONFR1_NF_Pos)          /*!< 0x00000003 */

+#define JPEG_CONFR1_NF                  JPEG_CONFR1_NF_Msk                     /*!<Number of color components */

+#define JPEG_CONFR1_NF_0                (0x1UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000001 */

+#define JPEG_CONFR1_NF_1                (0x2UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000002 */

+#define JPEG_CONFR1_DE_Pos              (3U)

+#define JPEG_CONFR1_DE_Msk              (0x1UL << JPEG_CONFR1_DE_Pos)          /*!< 0x00000008 */

+#define JPEG_CONFR1_DE                  JPEG_CONFR1_DE_Msk                     /*!<Decoding Enable */

+#define JPEG_CONFR1_COLORSPACE_Pos      (4U)

+#define JPEG_CONFR1_COLORSPACE_Msk      (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)  /*!< 0x00000030 */

+#define JPEG_CONFR1_COLORSPACE          JPEG_CONFR1_COLORSPACE_Msk             /*!<Color Space */

+#define JPEG_CONFR1_COLORSPACE_0        (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000010 */

+#define JPEG_CONFR1_COLORSPACE_1        (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000020 */

+#define JPEG_CONFR1_NS_Pos              (6U)

+#define JPEG_CONFR1_NS_Msk              (0x3UL << JPEG_CONFR1_NS_Pos)          /*!< 0x000000C0 */

+#define JPEG_CONFR1_NS                  JPEG_CONFR1_NS_Msk                     /*!<Number of components for Scan */

+#define JPEG_CONFR1_NS_0                (0x1UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR1_NS_1                (0x2UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR1_HDR_Pos             (8U)

+#define JPEG_CONFR1_HDR_Msk             (0x1UL << JPEG_CONFR1_HDR_Pos)         /*!< 0x00000100 */

+#define JPEG_CONFR1_HDR                 JPEG_CONFR1_HDR_Msk                    /*!<Header Processing On/Off */

+#define JPEG_CONFR1_YSIZE_Pos           (16U)

+#define JPEG_CONFR1_YSIZE_Msk           (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)    /*!< 0xFFFF0000 */

+#define JPEG_CONFR1_YSIZE               JPEG_CONFR1_YSIZE_Msk                  /*!<Number of lines in source image */

+

+/********************  Bit definition for CONFR2 register  ********************/

+#define JPEG_CONFR2_NMCU_Pos            (0U)

+#define JPEG_CONFR2_NMCU_Msk            (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)  /*!< 0x03FFFFFF */

+#define JPEG_CONFR2_NMCU                JPEG_CONFR2_NMCU_Msk                   /*!<Number of MCU units minus 1 to encode */

+

+/********************  Bit definition for CONFR3 register  ********************/

+#define JPEG_CONFR3_XSIZE_Pos           (16U)

+#define JPEG_CONFR3_XSIZE_Msk           (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)    /*!< 0xFFFF0000 */

+#define JPEG_CONFR3_XSIZE               JPEG_CONFR3_XSIZE_Msk                  /*!<Number of pixels per line */

+

+/********************  Bit definition for CONFR4 register  ********************/

+#define JPEG_CONFR4_HD_Pos              (0U)

+#define JPEG_CONFR4_HD_Msk              (0x1UL << JPEG_CONFR4_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR4_HD                  JPEG_CONFR4_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR4_HA_Pos              (1U)

+#define JPEG_CONFR4_HA_Msk              (0x1UL << JPEG_CONFR4_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR4_HA                  JPEG_CONFR4_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR4_QT_Pos              (2U)

+#define JPEG_CONFR4_QT_Msk              (0x3UL << JPEG_CONFR4_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR4_QT                  JPEG_CONFR4_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR4_QT_0                (0x1UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR4_QT_1                (0x2UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR4_NB_Pos              (4U)

+#define JPEG_CONFR4_NB_Msk              (0xFUL << JPEG_CONFR4_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR4_NB                  JPEG_CONFR4_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR4_NB_0                (0x1UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR4_NB_1                (0x2UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR4_NB_2                (0x4UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR4_NB_3                (0x8UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR4_VSF_Pos             (8U)

+#define JPEG_CONFR4_VSF_Msk             (0xFUL << JPEG_CONFR4_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR4_VSF                 JPEG_CONFR4_VSF_Msk                    /*!<Vertical sampling factor for component 1 */

+#define JPEG_CONFR4_VSF_0               (0x1UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR4_VSF_1               (0x2UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR4_VSF_2               (0x4UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR4_VSF_3               (0x8UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR4_HSF_Pos             (12U)

+#define JPEG_CONFR4_HSF_Msk             (0xFUL << JPEG_CONFR4_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR4_HSF                 JPEG_CONFR4_HSF_Msk                    /*!<Horizontal sampling factor for component 1 */

+#define JPEG_CONFR4_HSF_0               (0x1UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR4_HSF_1               (0x2UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR4_HSF_2               (0x4UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR4_HSF_3               (0x8UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR5 register  ********************/

+#define JPEG_CONFR5_HD_Pos              (0U)

+#define JPEG_CONFR5_HD_Msk              (0x1UL << JPEG_CONFR5_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR5_HD                  JPEG_CONFR5_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR5_HA_Pos              (1U)

+#define JPEG_CONFR5_HA_Msk              (0x1UL << JPEG_CONFR5_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR5_HA                  JPEG_CONFR5_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR5_QT_Pos              (2U)

+#define JPEG_CONFR5_QT_Msk              (0x3UL << JPEG_CONFR5_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR5_QT                  JPEG_CONFR5_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR5_QT_0                (0x1UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR5_QT_1                (0x2UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR5_NB_Pos              (4U)

+#define JPEG_CONFR5_NB_Msk              (0xFUL << JPEG_CONFR5_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR5_NB                  JPEG_CONFR5_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR5_NB_0                (0x1UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR5_NB_1                (0x2UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR5_NB_2                (0x4UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR5_NB_3                (0x8UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR5_VSF_Pos             (8U)

+#define JPEG_CONFR5_VSF_Msk             (0xFUL << JPEG_CONFR5_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR5_VSF                 JPEG_CONFR5_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR5_VSF_0               (0x1UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR5_VSF_1               (0x2UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR5_VSF_2               (0x4UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR5_VSF_3               (0x8UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR5_HSF_Pos             (12U)

+#define JPEG_CONFR5_HSF_Msk             (0xFUL << JPEG_CONFR5_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR5_HSF                 JPEG_CONFR5_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR5_HSF_0               (0x1UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR5_HSF_1               (0x2UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR5_HSF_2               (0x4UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR5_HSF_3               (0x8UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR6 register  ********************/

+#define JPEG_CONFR6_HD_Pos              (0U)

+#define JPEG_CONFR6_HD_Msk              (0x1UL << JPEG_CONFR6_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR6_HD                  JPEG_CONFR6_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR6_HA_Pos              (1U)

+#define JPEG_CONFR6_HA_Msk              (0x1UL << JPEG_CONFR6_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR6_HA                  JPEG_CONFR6_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR6_QT_Pos              (2U)

+#define JPEG_CONFR6_QT_Msk              (0x3UL << JPEG_CONFR6_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR6_QT                  JPEG_CONFR6_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR6_QT_0                (0x1UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR6_QT_1                (0x2UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR6_NB_Pos              (4U)

+#define JPEG_CONFR6_NB_Msk              (0xFUL << JPEG_CONFR6_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR6_NB                  JPEG_CONFR6_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR6_NB_0                (0x1UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR6_NB_1                (0x2UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR6_NB_2                (0x4UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR6_NB_3                (0x8UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR6_VSF_Pos             (8U)

+#define JPEG_CONFR6_VSF_Msk             (0xFUL << JPEG_CONFR6_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR6_VSF                 JPEG_CONFR6_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR6_VSF_0               (0x1UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR6_VSF_1               (0x2UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR6_VSF_2               (0x4UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR6_VSF_3               (0x8UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR6_HSF_Pos             (12U)

+#define JPEG_CONFR6_HSF_Msk             (0xFUL << JPEG_CONFR6_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR6_HSF                 JPEG_CONFR6_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR6_HSF_0               (0x1UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR6_HSF_1               (0x2UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR6_HSF_2               (0x4UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR6_HSF_3               (0x8UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR7 register  ********************/

+#define JPEG_CONFR7_HD_Pos              (0U)

+#define JPEG_CONFR7_HD_Msk              (0x1UL << JPEG_CONFR7_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR7_HD                  JPEG_CONFR7_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR7_HA_Pos              (1U)

+#define JPEG_CONFR7_HA_Msk              (0x1UL << JPEG_CONFR7_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR7_HA                  JPEG_CONFR7_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR7_QT_Pos              (2U)

+#define JPEG_CONFR7_QT_Msk              (0x3UL << JPEG_CONFR7_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR7_QT                  JPEG_CONFR7_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR7_QT_0                (0x1UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR7_QT_1                (0x2UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR7_NB_Pos              (4U)

+#define JPEG_CONFR7_NB_Msk              (0xFUL << JPEG_CONFR7_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR7_NB                  JPEG_CONFR7_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR7_NB_0                (0x1UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR7_NB_1                (0x2UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR7_NB_2                (0x4UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR7_NB_3                (0x8UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR7_VSF_Pos             (8U)

+#define JPEG_CONFR7_VSF_Msk             (0xFUL << JPEG_CONFR7_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR7_VSF                 JPEG_CONFR7_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR7_VSF_0               (0x1UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR7_VSF_1               (0x2UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR7_VSF_2               (0x4UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR7_VSF_3               (0x8UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR7_HSF_Pos             (12U)

+#define JPEG_CONFR7_HSF_Msk             (0xFUL << JPEG_CONFR7_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR7_HSF                 JPEG_CONFR7_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR7_HSF_0               (0x1UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR7_HSF_1               (0x2UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR7_HSF_2               (0x4UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR7_HSF_3               (0x8UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CR register  ********************/

+#define JPEG_CR_JCEN_Pos                (0U)

+#define JPEG_CR_JCEN_Msk                (0x1UL << JPEG_CR_JCEN_Pos)            /*!< 0x00000001 */

+#define JPEG_CR_JCEN                    JPEG_CR_JCEN_Msk                       /*!<Enable the JPEG Codec Core */

+#define JPEG_CR_IFTIE_Pos               (1U)

+#define JPEG_CR_IFTIE_Msk               (0x1UL << JPEG_CR_IFTIE_Pos)           /*!< 0x00000002 */

+#define JPEG_CR_IFTIE                   JPEG_CR_IFTIE_Msk                      /*!<Input FIFO Threshold Interrupt Enable */

+#define JPEG_CR_IFNFIE_Pos              (2U)

+#define JPEG_CR_IFNFIE_Msk              (0x1UL << JPEG_CR_IFNFIE_Pos)          /*!< 0x00000004 */

+#define JPEG_CR_IFNFIE                  JPEG_CR_IFNFIE_Msk                     /*!<Input FIFO Not Full Interrupt Enable */

+#define JPEG_CR_OFTIE_Pos               (3U)

+#define JPEG_CR_OFTIE_Msk               (0x1UL << JPEG_CR_OFTIE_Pos)           /*!< 0x00000008 */

+#define JPEG_CR_OFTIE                   JPEG_CR_OFTIE_Msk                      /*!<Output FIFO Threshold Interrupt Enable */

+#define JPEG_CR_OFNEIE_Pos              (4U)

+#define JPEG_CR_OFNEIE_Msk              (0x1UL << JPEG_CR_OFNEIE_Pos)          /*!< 0x00000010 */

+#define JPEG_CR_OFNEIE                  JPEG_CR_OFNEIE_Msk                     /*!<Output FIFO Not Empty Interrupt Enable */

+#define JPEG_CR_EOCIE_Pos               (5U)

+#define JPEG_CR_EOCIE_Msk               (0x1UL << JPEG_CR_EOCIE_Pos)           /*!< 0x00000020 */

+#define JPEG_CR_EOCIE                   JPEG_CR_EOCIE_Msk                      /*!<End of Conversion Interrupt Enable */

+#define JPEG_CR_HPDIE_Pos               (6U)

+#define JPEG_CR_HPDIE_Msk               (0x1UL << JPEG_CR_HPDIE_Pos)           /*!< 0x00000040 */

+#define JPEG_CR_HPDIE                   JPEG_CR_HPDIE_Msk                      /*!<Header Parsing Done Interrupt Enable */

+#define JPEG_CR_IFF_Pos                 (13U)

+#define JPEG_CR_IFF_Msk                 (0x1UL << JPEG_CR_IFF_Pos)             /*!< 0x00002000 */

+#define JPEG_CR_IFF                     JPEG_CR_IFF_Msk                        /*!<Flush the input FIFO */

+#define JPEG_CR_OFF_Pos                 (14U)

+#define JPEG_CR_OFF_Msk                 (0x1UL << JPEG_CR_OFF_Pos)             /*!< 0x00004000 */

+#define JPEG_CR_OFF                     JPEG_CR_OFF_Msk                        /*!<Flush the output FIFO */

+

+/********************  Bit definition for SR register  ********************/

+#define JPEG_SR_IFTF_Pos                (1U)

+#define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */

+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is bellow its threshold flag */

+#define JPEG_SR_IFNFF_Pos               (2U)

+#define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */

+#define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */

+#define JPEG_SR_OFTF_Pos                (3U)

+#define JPEG_SR_OFTF_Msk                (0x1UL << JPEG_SR_OFTF_Pos)            /*!< 0x00000008 */

+#define JPEG_SR_OFTF                    JPEG_SR_OFTF_Msk                       /*!<Output FIFO is not empty and has reach its threshold */

+#define JPEG_SR_OFNEF_Pos               (4U)

+#define JPEG_SR_OFNEF_Msk               (0x1UL << JPEG_SR_OFNEF_Pos)           /*!< 0x00000010 */

+#define JPEG_SR_OFNEF                   JPEG_SR_OFNEF_Msk                      /*!<Output FIFO is not empty, a data is available */

+#define JPEG_SR_EOCF_Pos                (5U)

+#define JPEG_SR_EOCF_Msk                (0x1UL << JPEG_SR_EOCF_Pos)            /*!< 0x00000020 */

+#define JPEG_SR_EOCF                    JPEG_SR_EOCF_Msk                       /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */

+#define JPEG_SR_HPDF_Pos                (6U)

+#define JPEG_SR_HPDF_Msk                (0x1UL << JPEG_SR_HPDF_Pos)            /*!< 0x00000040 */

+#define JPEG_SR_HPDF                    JPEG_SR_HPDF_Msk                       /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */

+#define JPEG_SR_COF_Pos                 (7U)

+#define JPEG_SR_COF_Msk                 (0x1UL << JPEG_SR_COF_Pos)             /*!< 0x00000080 */

+#define JPEG_SR_COF                     JPEG_SR_COF_Msk                        /*!<JPEG Codec operation on going flag */

+

+/********************  Bit definition for CFR register  ********************/

+#define JPEG_CFR_CEOCF_Pos              (4U)

+#define JPEG_CFR_CEOCF_Msk              (0x1UL << JPEG_CFR_CEOCF_Pos)          /*!< 0x00000010 */

+#define JPEG_CFR_CEOCF                  JPEG_CFR_CEOCF_Msk                     /*!<Clear End of Conversion Flag */

+#define JPEG_CFR_CHPDF_Pos              (5U)

+#define JPEG_CFR_CHPDF_Msk              (0x1UL << JPEG_CFR_CHPDF_Pos)          /*!< 0x00000020 */

+#define JPEG_CFR_CHPDF                  JPEG_CFR_CHPDF_Msk                     /*!<Clear Header Parsing Done Flag */

+

+/********************  Bit definition for DIR register  ********************/

+#define JPEG_DIR_DATAIN_Pos             (0U)

+#define JPEG_DIR_DATAIN_Msk             (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)  /*!< 0xFFFFFFFF */

+#define JPEG_DIR_DATAIN                 JPEG_DIR_DATAIN_Msk                    /*!<Data Input FIFO */

+

+/********************  Bit definition for DOR register  ********************/

+#define JPEG_DOR_DATAOUT_Pos            (0U)

+#define JPEG_DOR_DATAOUT_Msk            (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */

+#define JPEG_DOR_DATAOUT                JPEG_DOR_DATAOUT_Msk                   /*!<Data Output FIFO */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      LCD-TFT Display Controller (LTDC)                     */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for LTDC_SSCR register  *****************/

+

+#define LTDC_SSCR_VSH_Pos            (0U)

+#define LTDC_SSCR_VSH_Msk            (0x7FFUL << LTDC_SSCR_VSH_Pos)            /*!< 0x000007FF */

+#define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height  */

+#define LTDC_SSCR_HSW_Pos            (16U)

+#define LTDC_SSCR_HSW_Msk            (0xFFFUL << LTDC_SSCR_HSW_Pos)            /*!< 0x0FFF0000 */

+#define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */

+

+/********************  Bit definition for LTDC_BPCR register  *****************/

+

+#define LTDC_BPCR_AVBP_Pos           (0U)

+#define LTDC_BPCR_AVBP_Msk           (0x7FFUL << LTDC_BPCR_AVBP_Pos)           /*!< 0x000007FF */

+#define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch   */

+#define LTDC_BPCR_AHBP_Pos           (16U)

+#define LTDC_BPCR_AHBP_Msk           (0xFFFUL << LTDC_BPCR_AHBP_Pos)           /*!< 0x0FFF0000 */

+#define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */

+

+/********************  Bit definition for LTDC_AWCR register  *****************/

+

+#define LTDC_AWCR_AAH_Pos            (0U)

+#define LTDC_AWCR_AAH_Msk            (0x7FFUL << LTDC_AWCR_AAH_Pos)            /*!< 0x000007FF */

+#define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active heigh */

+#define LTDC_AWCR_AAW_Pos            (16U)

+#define LTDC_AWCR_AAW_Msk            (0xFFFUL << LTDC_AWCR_AAW_Pos)            /*!< 0x0FFF0000 */

+#define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */

+

+/********************  Bit definition for LTDC_TWCR register  *****************/

+

+#define LTDC_TWCR_TOTALH_Pos         (0U)

+#define LTDC_TWCR_TOTALH_Msk         (0x7FFUL << LTDC_TWCR_TOTALH_Pos)         /*!< 0x000007FF */

+#define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total Heigh */

+#define LTDC_TWCR_TOTALW_Pos         (16U)

+#define LTDC_TWCR_TOTALW_Msk         (0xFFFUL << LTDC_TWCR_TOTALW_Pos)         /*!< 0x0FFF0000 */

+#define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */

+

+/********************  Bit definition for LTDC_GCR register  ******************/

+

+#define LTDC_GCR_LTDCEN_Pos          (0U)

+#define LTDC_GCR_LTDCEN_Msk          (0x1UL << LTDC_GCR_LTDCEN_Pos)            /*!< 0x00000001 */

+#define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit       */

+#define LTDC_GCR_DBW_Pos             (4U)

+#define LTDC_GCR_DBW_Msk             (0x7UL << LTDC_GCR_DBW_Pos)               /*!< 0x00000070 */

+#define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width                   */

+#define LTDC_GCR_DGW_Pos             (8U)

+#define LTDC_GCR_DGW_Msk             (0x7UL << LTDC_GCR_DGW_Pos)               /*!< 0x00000700 */

+#define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width                  */

+#define LTDC_GCR_DRW_Pos             (12U)

+#define LTDC_GCR_DRW_Msk             (0x7UL << LTDC_GCR_DRW_Pos)               /*!< 0x00007000 */

+#define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width                    */

+#define LTDC_GCR_DEN_Pos             (16U)

+#define LTDC_GCR_DEN_Msk             (0x1UL << LTDC_GCR_DEN_Pos)               /*!< 0x00010000 */

+#define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable                       */

+#define LTDC_GCR_PCPOL_Pos           (28U)

+#define LTDC_GCR_PCPOL_Msk           (0x1UL << LTDC_GCR_PCPOL_Pos)             /*!< 0x10000000 */

+#define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity                */

+#define LTDC_GCR_DEPOL_Pos           (29U)

+#define LTDC_GCR_DEPOL_Msk           (0x1UL << LTDC_GCR_DEPOL_Pos)             /*!< 0x20000000 */

+#define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity                */

+#define LTDC_GCR_VSPOL_Pos           (30U)

+#define LTDC_GCR_VSPOL_Msk           (0x1UL << LTDC_GCR_VSPOL_Pos)             /*!< 0x40000000 */

+#define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity   */

+#define LTDC_GCR_HSPOL_Pos           (31U)

+#define LTDC_GCR_HSPOL_Msk           (0x1UL << LTDC_GCR_HSPOL_Pos)             /*!< 0x80000000 */

+#define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */

+

+

+/********************  Bit definition for LTDC_SRCR register  *****************/

+

+#define LTDC_SRCR_IMR_Pos            (0U)

+#define LTDC_SRCR_IMR_Msk            (0x1UL << LTDC_SRCR_IMR_Pos)              /*!< 0x00000001 */

+#define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload         */

+#define LTDC_SRCR_VBR_Pos            (1U)

+#define LTDC_SRCR_VBR_Msk            (0x1UL << LTDC_SRCR_VBR_Pos)              /*!< 0x00000002 */

+#define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */

+

+/********************  Bit definition for LTDC_BCCR register  *****************/

+

+#define LTDC_BCCR_BCBLUE_Pos         (0U)

+#define LTDC_BCCR_BCBLUE_Msk         (0xFFUL << LTDC_BCCR_BCBLUE_Pos)          /*!< 0x000000FF */

+#define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value  */

+#define LTDC_BCCR_BCGREEN_Pos        (8U)

+#define LTDC_BCCR_BCGREEN_Msk        (0xFFUL << LTDC_BCCR_BCGREEN_Pos)         /*!< 0x0000FF00 */

+#define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */

+#define LTDC_BCCR_BCRED_Pos          (16U)

+#define LTDC_BCCR_BCRED_Msk          (0xFFUL << LTDC_BCCR_BCRED_Pos)           /*!< 0x00FF0000 */

+#define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value   */

+

+/********************  Bit definition for LTDC_IER register  ******************/

+

+#define LTDC_IER_LIE_Pos             (0U)

+#define LTDC_IER_LIE_Msk             (0x1UL << LTDC_IER_LIE_Pos)               /*!< 0x00000001 */

+#define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable            */

+#define LTDC_IER_FUIE_Pos            (1U)

+#define LTDC_IER_FUIE_Msk            (0x1UL << LTDC_IER_FUIE_Pos)              /*!< 0x00000002 */

+#define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable   */

+#define LTDC_IER_TERRIE_Pos          (2U)

+#define LTDC_IER_TERRIE_Msk          (0x1UL << LTDC_IER_TERRIE_Pos)            /*!< 0x00000004 */

+#define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable  */

+#define LTDC_IER_RRIE_Pos            (3U)

+#define LTDC_IER_RRIE_Msk            (0x1UL << LTDC_IER_RRIE_Pos)              /*!< 0x00000008 */

+#define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */

+

+/********************  Bit definition for LTDC_ISR register  ******************/

+

+#define LTDC_ISR_LIF_Pos             (0U)

+#define LTDC_ISR_LIF_Msk             (0x1UL << LTDC_ISR_LIF_Pos)               /*!< 0x00000001 */

+#define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */

+#define LTDC_ISR_FUIF_Pos            (1U)

+#define LTDC_ISR_FUIF_Msk            (0x1UL << LTDC_ISR_FUIF_Pos)              /*!< 0x00000002 */

+#define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */

+#define LTDC_ISR_TERRIF_Pos          (2U)

+#define LTDC_ISR_TERRIF_Msk          (0x1UL << LTDC_ISR_TERRIF_Pos)            /*!< 0x00000004 */

+#define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */

+#define LTDC_ISR_RRIF_Pos            (3U)

+#define LTDC_ISR_RRIF_Msk            (0x1UL << LTDC_ISR_RRIF_Pos)              /*!< 0x00000008 */

+#define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */

+

+/********************  Bit definition for LTDC_ICR register  ******************/

+

+#define LTDC_ICR_CLIF_Pos            (0U)

+#define LTDC_ICR_CLIF_Msk            (0x1UL << LTDC_ICR_CLIF_Pos)              /*!< 0x00000001 */

+#define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */

+#define LTDC_ICR_CFUIF_Pos           (1U)

+#define LTDC_ICR_CFUIF_Msk           (0x1UL << LTDC_ICR_CFUIF_Pos)             /*!< 0x00000002 */

+#define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */

+#define LTDC_ICR_CTERRIF_Pos         (2U)

+#define LTDC_ICR_CTERRIF_Msk         (0x1UL << LTDC_ICR_CTERRIF_Pos)           /*!< 0x00000004 */

+#define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */

+#define LTDC_ICR_CRRIF_Pos           (3U)

+#define LTDC_ICR_CRRIF_Msk           (0x1UL << LTDC_ICR_CRRIF_Pos)             /*!< 0x00000008 */

+#define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */

+

+/********************  Bit definition for LTDC_LIPCR register  ****************/

+

+#define LTDC_LIPCR_LIPOS_Pos         (0U)

+#define LTDC_LIPCR_LIPOS_Msk         (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)         /*!< 0x000007FF */

+#define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */

+

+/********************  Bit definition for LTDC_CPSR register  *****************/

+

+#define LTDC_CPSR_CYPOS_Pos          (0U)

+#define LTDC_CPSR_CYPOS_Msk          (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)         /*!< 0x0000FFFF */

+#define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */

+#define LTDC_CPSR_CXPOS_Pos          (16U)

+#define LTDC_CPSR_CXPOS_Msk          (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)         /*!< 0xFFFF0000 */

+#define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */

+

+/********************  Bit definition for LTDC_CDSR register  *****************/

+

+#define LTDC_CDSR_VDES_Pos           (0U)

+#define LTDC_CDSR_VDES_Msk           (0x1UL << LTDC_CDSR_VDES_Pos)             /*!< 0x00000001 */

+#define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status       */

+#define LTDC_CDSR_HDES_Pos           (1U)

+#define LTDC_CDSR_HDES_Msk           (0x1UL << LTDC_CDSR_HDES_Pos)             /*!< 0x00000002 */

+#define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status     */

+#define LTDC_CDSR_VSYNCS_Pos         (2U)

+#define LTDC_CDSR_VSYNCS_Msk         (0x1UL << LTDC_CDSR_VSYNCS_Pos)           /*!< 0x00000004 */

+#define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status   */

+#define LTDC_CDSR_HSYNCS_Pos         (3U)

+#define LTDC_CDSR_HSYNCS_Msk         (0x1UL << LTDC_CDSR_HSYNCS_Pos)           /*!< 0x00000008 */

+#define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */

+

+/********************  Bit definition for LTDC_LxCR register  *****************/

+

+#define LTDC_LxCR_LEN_Pos            (0U)

+#define LTDC_LxCR_LEN_Msk            (0x1UL << LTDC_LxCR_LEN_Pos)              /*!< 0x00000001 */

+#define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable              */

+#define LTDC_LxCR_COLKEN_Pos         (1U)

+#define LTDC_LxCR_COLKEN_Msk         (0x1UL << LTDC_LxCR_COLKEN_Pos)           /*!< 0x00000002 */

+#define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable       */

+#define LTDC_LxCR_CLUTEN_Pos         (4U)

+#define LTDC_LxCR_CLUTEN_Msk         (0x1UL << LTDC_LxCR_CLUTEN_Pos)           /*!< 0x00000010 */

+#define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */

+

+/********************  Bit definition for LTDC_LxWHPCR register  **************/

+

+#define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)

+#define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)     /*!< 0x00000FFF */

+#define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */

+#define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)

+#define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)    /*!< 0xFFFF0000 */

+#define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position  */

+

+/********************  Bit definition for LTDC_LxWVPCR register  **************/

+

+#define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)

+#define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)     /*!< 0x00000FFF */

+#define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */

+#define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)

+#define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)    /*!< 0xFFFF0000 */

+#define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position  */

+

+/********************  Bit definition for LTDC_LxCKCR register  ***************/

+

+#define LTDC_LxCKCR_CKBLUE_Pos       (0U)

+#define LTDC_LxCKCR_CKBLUE_Msk       (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value  */

+#define LTDC_LxCKCR_CKGREEN_Pos      (8U)

+#define LTDC_LxCKCR_CKGREEN_Msk      (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */

+#define LTDC_LxCKCR_CKRED_Pos        (16U)

+#define LTDC_LxCKCR_CKRED_Msk        (0xFFUL << LTDC_LxCKCR_CKRED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value   */

+

+/********************  Bit definition for LTDC_LxPFCR register  ***************/

+

+#define LTDC_LxPFCR_PF_Pos           (0U)

+#define LTDC_LxPFCR_PF_Msk           (0x7UL << LTDC_LxPFCR_PF_Pos)             /*!< 0x00000007 */

+#define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */

+

+/********************  Bit definition for LTDC_LxCACR register  ***************/

+

+#define LTDC_LxCACR_CONSTA_Pos       (0U)

+#define LTDC_LxCACR_CONSTA_Msk       (0xFFUL << LTDC_LxCACR_CONSTA_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */

+

+/********************  Bit definition for LTDC_LxDCCR register  ***************/

+

+#define LTDC_LxDCCR_DCBLUE_Pos       (0U)

+#define LTDC_LxDCCR_DCBLUE_Msk       (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue  */

+#define LTDC_LxDCCR_DCGREEN_Pos      (8U)

+#define LTDC_LxDCCR_DCGREEN_Msk      (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */

+#define LTDC_LxDCCR_DCRED_Pos        (16U)

+#define LTDC_LxDCCR_DCRED_Msk        (0xFFUL << LTDC_LxDCCR_DCRED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red   */

+#define LTDC_LxDCCR_DCALPHA_Pos      (24U)

+#define LTDC_LxDCCR_DCALPHA_Msk      (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)       /*!< 0xFF000000 */

+#define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */

+

+/********************  Bit definition for LTDC_LxBFCR register  ***************/

+

+#define LTDC_LxBFCR_BF2_Pos          (0U)

+#define LTDC_LxBFCR_BF2_Msk          (0x7UL << LTDC_LxBFCR_BF2_Pos)            /*!< 0x00000007 */

+#define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */

+#define LTDC_LxBFCR_BF1_Pos          (8U)

+#define LTDC_LxBFCR_BF1_Msk          (0x7UL << LTDC_LxBFCR_BF1_Pos)            /*!< 0x00000700 */

+#define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */

+

+/********************  Bit definition for LTDC_LxCFBAR register  **************/

+

+#define LTDC_LxCFBAR_CFBADD_Pos      (0U)

+#define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */

+#define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */

+

+/********************  Bit definition for LTDC_LxCFBLR register  **************/

+

+#define LTDC_LxCFBLR_CFBLL_Pos       (0U)

+#define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)      /*!< 0x00001FFF */

+#define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length    */

+#define LTDC_LxCFBLR_CFBP_Pos        (16U)

+#define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)       /*!< 0x1FFF0000 */

+#define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */

+

+/********************  Bit definition for LTDC_LxCFBLNR register  *************/

+

+#define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)

+#define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)    /*!< 0x000007FF */

+#define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */

+

+/********************  Bit definition for LTDC_LxCLUTWR register  *************/

+

+#define LTDC_LxCLUTWR_BLUE_Pos       (0U)

+#define LTDC_LxCLUTWR_BLUE_Msk       (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value   */

+#define LTDC_LxCLUTWR_GREEN_Pos      (8U)

+#define LTDC_LxCLUTWR_GREEN_Msk      (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value  */

+#define LTDC_LxCLUTWR_RED_Pos        (16U)

+#define LTDC_LxCLUTWR_RED_Msk        (0xFFUL << LTDC_LxCLUTWR_RED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value    */

+#define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)

+#define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)     /*!< 0xFF000000 */

+#define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                     MDMA                                   */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for MDMA_GISR0 register  ****************/

+#define MDMA_GISR0_GIF0_Pos       (0U)

+#define MDMA_GISR0_GIF0_Msk       (0x1UL << MDMA_GISR0_GIF0_Pos)               /*!< 0x00000001 */

+#define MDMA_GISR0_GIF0           MDMA_GISR0_GIF0_Msk                          /*!< Channel 0 global interrupt flag */

+#define MDMA_GISR0_GIF1_Pos       (1U)

+#define MDMA_GISR0_GIF1_Msk       (0x1UL << MDMA_GISR0_GIF1_Pos)               /*!< 0x00000002 */

+#define MDMA_GISR0_GIF1           MDMA_GISR0_GIF1_Msk                          /*!< Channel 1 global interrupt flag */

+#define MDMA_GISR0_GIF2_Pos       (2U)

+#define MDMA_GISR0_GIF2_Msk       (0x1UL << MDMA_GISR0_GIF2_Pos)               /*!< 0x00000004 */

+#define MDMA_GISR0_GIF2           MDMA_GISR0_GIF2_Msk                          /*!< Channel 2 global interrupt flag */

+#define MDMA_GISR0_GIF3_Pos       (3U)

+#define MDMA_GISR0_GIF3_Msk       (0x1UL << MDMA_GISR0_GIF3_Pos)               /*!< 0x00000008 */

+#define MDMA_GISR0_GIF3           MDMA_GISR0_GIF3_Msk                          /*!< Channel 3 global interrupt flag */

+#define MDMA_GISR0_GIF4_Pos       (4U)

+#define MDMA_GISR0_GIF4_Msk       (0x1UL << MDMA_GISR0_GIF4_Pos)               /*!< 0x00000010 */

+#define MDMA_GISR0_GIF4           MDMA_GISR0_GIF4_Msk                          /*!< Channel 4 global interrupt flag */

+#define MDMA_GISR0_GIF5_Pos       (5U)

+#define MDMA_GISR0_GIF5_Msk       (0x1UL << MDMA_GISR0_GIF5_Pos)               /*!< 0x00000020 */

+#define MDMA_GISR0_GIF5           MDMA_GISR0_GIF5_Msk                          /*!< Channel 5 global interrupt flag */

+#define MDMA_GISR0_GIF6_Pos       (6U)

+#define MDMA_GISR0_GIF6_Msk       (0x1UL << MDMA_GISR0_GIF6_Pos)               /*!< 0x00000040 */

+#define MDMA_GISR0_GIF6           MDMA_GISR0_GIF6_Msk                          /*!< Channel 6 global interrupt flag */

+#define MDMA_GISR0_GIF7_Pos       (7U)

+#define MDMA_GISR0_GIF7_Msk       (0x1UL << MDMA_GISR0_GIF7_Pos)               /*!< 0x00000080 */

+#define MDMA_GISR0_GIF7           MDMA_GISR0_GIF7_Msk                          /*!< Channel 7 global interrupt flag */

+#define MDMA_GISR0_GIF8_Pos       (8U)

+#define MDMA_GISR0_GIF8_Msk       (0x1UL << MDMA_GISR0_GIF8_Pos)               /*!< 0x00000100 */

+#define MDMA_GISR0_GIF8           MDMA_GISR0_GIF8_Msk                          /*!< Channel 8 global interrupt flag */

+#define MDMA_GISR0_GIF9_Pos       (9U)

+#define MDMA_GISR0_GIF9_Msk       (0x1UL << MDMA_GISR0_GIF9_Pos)               /*!< 0x00000200 */

+#define MDMA_GISR0_GIF9           MDMA_GISR0_GIF9_Msk                          /*!< Channel 9 global interrupt flag */

+#define MDMA_GISR0_GIF10_Pos      (10U)

+#define MDMA_GISR0_GIF10_Msk      (0x1UL << MDMA_GISR0_GIF10_Pos)              /*!< 0x00000400 */

+#define MDMA_GISR0_GIF10          MDMA_GISR0_GIF10_Msk                         /*!< Channel 10 global interrupt flag */

+#define MDMA_GISR0_GIF11_Pos      (11U)

+#define MDMA_GISR0_GIF11_Msk      (0x1UL << MDMA_GISR0_GIF11_Pos)              /*!< 0x00000800 */

+#define MDMA_GISR0_GIF11          MDMA_GISR0_GIF11_Msk                         /*!< Channel 11 global interrupt flag */

+#define MDMA_GISR0_GIF12_Pos      (12U)

+#define MDMA_GISR0_GIF12_Msk      (0x1UL << MDMA_GISR0_GIF12_Pos)              /*!< 0x00001000 */

+#define MDMA_GISR0_GIF12          MDMA_GISR0_GIF12_Msk                         /*!< Channel 12 global interrupt flag */

+#define MDMA_GISR0_GIF13_Pos      (13U)

+#define MDMA_GISR0_GIF13_Msk      (0x1UL << MDMA_GISR0_GIF13_Pos)              /*!< 0x00002000 */

+#define MDMA_GISR0_GIF13          MDMA_GISR0_GIF13_Msk                         /*!< Channel 13 global interrupt flag */

+#define MDMA_GISR0_GIF14_Pos      (14U)

+#define MDMA_GISR0_GIF14_Msk      (0x1UL << MDMA_GISR0_GIF14_Pos)              /*!< 0x00004000 */

+#define MDMA_GISR0_GIF14          MDMA_GISR0_GIF14_Msk                         /*!< Channel 14 global interrupt flag */

+#define MDMA_GISR0_GIF15_Pos      (15U)

+#define MDMA_GISR0_GIF15_Msk      (0x1UL << MDMA_GISR0_GIF15_Pos)              /*!< 0x00008000 */

+#define MDMA_GISR0_GIF15          MDMA_GISR0_GIF15_Msk                         /*!< Channel 15 global interrupt flag */

+

+/********************  Bit definition for MDMA_CxISR register  ****************/

+#define MDMA_CISR_TEIF_Pos        (0U)

+#define MDMA_CISR_TEIF_Msk        (0x1UL << MDMA_CISR_TEIF_Pos)                /*!< 0x00000001 */

+#define MDMA_CISR_TEIF            MDMA_CISR_TEIF_Msk                           /*!< Channel x transfer error interrupt flag */

+#define MDMA_CISR_CTCIF_Pos       (1U)

+#define MDMA_CISR_CTCIF_Msk       (0x1UL << MDMA_CISR_CTCIF_Pos)               /*!< 0x00000002 */

+#define MDMA_CISR_CTCIF           MDMA_CISR_CTCIF_Msk                          /*!< Channel x Channel Transfer Complete interrupt flag */

+#define MDMA_CISR_BRTIF_Pos       (2U)

+#define MDMA_CISR_BRTIF_Msk       (0x1UL << MDMA_CISR_BRTIF_Pos)               /*!< 0x00000004 */

+#define MDMA_CISR_BRTIF           MDMA_CISR_BRTIF_Msk                          /*!< Channel x block repeat transfer complete interrupt flag */

+#define MDMA_CISR_BTIF_Pos        (3U)

+#define MDMA_CISR_BTIF_Msk        (0x1UL << MDMA_CISR_BTIF_Pos)                /*!< 0x00000008 */

+#define MDMA_CISR_BTIF            MDMA_CISR_BTIF_Msk                           /*!< Channel x block transfer complete interrupt flag */

+#define MDMA_CISR_TCIF_Pos        (4U)

+#define MDMA_CISR_TCIF_Msk        (0x1UL << MDMA_CISR_TCIF_Pos)                /*!< 0x00000010 */

+#define MDMA_CISR_TCIF            MDMA_CISR_TCIF_Msk                           /*!< Channel x buffer transfer complete interrupt flag */

+#define MDMA_CISR_CRQA_Pos        (16U)

+#define MDMA_CISR_CRQA_Msk        (0x1UL << MDMA_CISR_CRQA_Pos)                /*!< 0x00010000 */

+#define MDMA_CISR_CRQA            MDMA_CISR_CRQA_Msk                           /*!< Channel x ReQest Active flag */

+

+/********************  Bit definition for MDMA_CxIFCR register  ****************/

+#define MDMA_CIFCR_CTEIF_Pos      (0U)

+#define MDMA_CIFCR_CTEIF_Msk      (0x1UL << MDMA_CIFCR_CTEIF_Pos)              /*!< 0x00000001 */

+#define MDMA_CIFCR_CTEIF          MDMA_CIFCR_CTEIF_Msk                         /*!< Channel x clear transfer error interrupt flag */

+#define MDMA_CIFCR_CCTCIF_Pos     (1U)

+#define MDMA_CIFCR_CCTCIF_Msk     (0x1UL << MDMA_CIFCR_CCTCIF_Pos)             /*!< 0x00000002 */

+#define MDMA_CIFCR_CCTCIF         MDMA_CIFCR_CCTCIF_Msk                        /*!< Clear Channel transfer complete interrupt flag for channel x */

+#define MDMA_CIFCR_CBRTIF_Pos     (2U)

+#define MDMA_CIFCR_CBRTIF_Msk     (0x1UL << MDMA_CIFCR_CBRTIF_Pos)             /*!< 0x00000004 */

+#define MDMA_CIFCR_CBRTIF         MDMA_CIFCR_CBRTIF_Msk                        /*!< Channel x clear block repeat transfer complete interrupt flag */

+#define MDMA_CIFCR_CBTIF_Pos      (3U)

+#define MDMA_CIFCR_CBTIF_Msk      (0x1UL << MDMA_CIFCR_CBTIF_Pos)              /*!< 0x00000008 */

+#define MDMA_CIFCR_CBTIF          MDMA_CIFCR_CBTIF_Msk                         /*!< Channel x Clear block transfer complete interrupt flag */

+#define MDMA_CIFCR_CLTCIF_Pos     (4U)

+#define MDMA_CIFCR_CLTCIF_Msk     (0x1UL << MDMA_CIFCR_CLTCIF_Pos)             /*!< 0x00000010 */

+#define MDMA_CIFCR_CLTCIF         MDMA_CIFCR_CLTCIF_Msk                        /*!< CLear Transfer buffer Complete Interrupt Flag for channel */

+

+/********************  Bit definition for MDMA_CxESR register  ****************/

+#define MDMA_CESR_TEA_Pos         (0U)

+#define MDMA_CESR_TEA_Msk         (0x7FUL << MDMA_CESR_TEA_Pos)                /*!< 0x0000007F */

+#define MDMA_CESR_TEA             MDMA_CESR_TEA_Msk                            /*!< Transfer Error Address */

+#define MDMA_CESR_TED_Pos         (7U)

+#define MDMA_CESR_TED_Msk         (0x1UL << MDMA_CESR_TED_Pos)                 /*!< 0x00000080 */

+#define MDMA_CESR_TED             MDMA_CESR_TED_Msk                            /*!< Transfer Error Direction */

+#define MDMA_CESR_TELD_Pos        (8U)

+#define MDMA_CESR_TELD_Msk        (0x1UL << MDMA_CESR_TELD_Pos)                /*!< 0x00000100 */

+#define MDMA_CESR_TELD            MDMA_CESR_TELD_Msk                           /*!< Transfer Error Link Data */

+#define MDMA_CESR_TEMD_Pos        (9U)

+#define MDMA_CESR_TEMD_Msk        (0x1UL << MDMA_CESR_TEMD_Pos)                /*!< 0x00000200 */

+#define MDMA_CESR_TEMD            MDMA_CESR_TEMD_Msk                           /*!< Transfer Error Mask Data */

+#define MDMA_CESR_ASE_Pos         (10U)

+#define MDMA_CESR_ASE_Msk         (0x1UL << MDMA_CESR_ASE_Pos)                 /*!< 0x00000400 */

+#define MDMA_CESR_ASE             MDMA_CESR_ASE_Msk                            /*!< Address/Size Error       */

+#define MDMA_CESR_BSE_Pos         (11U)

+#define MDMA_CESR_BSE_Msk         (0x1UL << MDMA_CESR_BSE_Pos)                 /*!< 0x00000800 */

+#define MDMA_CESR_BSE             MDMA_CESR_BSE_Msk                            /*!< Block Size Error         */

+

+/********************  Bit definition for MDMA_CxCR register  ****************/

+#define MDMA_CCR_EN_Pos           (0U)

+#define MDMA_CCR_EN_Msk           (0x1UL << MDMA_CCR_EN_Pos)                   /*!< 0x00000001 */

+#define MDMA_CCR_EN               MDMA_CCR_EN_Msk                              /*!< Channel enable / flag channel ready when read low */

+#define MDMA_CCR_TEIE_Pos         (1U)

+#define MDMA_CCR_TEIE_Msk         (0x1UL << MDMA_CCR_TEIE_Pos)                 /*!< 0x00000002 */

+#define MDMA_CCR_TEIE             MDMA_CCR_TEIE_Msk                            /*!< Transfer error interrupt enable */

+#define MDMA_CCR_CTCIE_Pos        (2U)

+#define MDMA_CCR_CTCIE_Msk        (0x1UL << MDMA_CCR_CTCIE_Pos)                /*!< 0x00000004 */

+#define MDMA_CCR_CTCIE            MDMA_CCR_CTCIE_Msk                           /*!< Channel Transfer Complete interrupt enable */

+#define MDMA_CCR_BRTIE_Pos        (3U)

+#define MDMA_CCR_BRTIE_Msk        (0x1UL << MDMA_CCR_BRTIE_Pos)                /*!< 0x00000008 */

+#define MDMA_CCR_BRTIE            MDMA_CCR_BRTIE_Msk                           /*!< Block Repeat transfer interrupt enable */

+#define MDMA_CCR_BTIE_Pos         (4U)

+#define MDMA_CCR_BTIE_Msk         (0x1UL << MDMA_CCR_BTIE_Pos)                 /*!< 0x00000010 */

+#define MDMA_CCR_BTIE             MDMA_CCR_BTIE_Msk                            /*!< Block Transfer interrupt enable */

+#define MDMA_CCR_TCIE_Pos         (5U)

+#define MDMA_CCR_TCIE_Msk         (0x1UL << MDMA_CCR_TCIE_Pos)                 /*!< 0x00000020 */

+#define MDMA_CCR_TCIE             MDMA_CCR_TCIE_Msk                            /*!< buffer Transfer Complete interrupt enable */

+#define MDMA_CCR_PL_Pos           (6U)

+#define MDMA_CCR_PL_Msk           (0x3UL << MDMA_CCR_PL_Pos)                   /*!< 0x000000C0 */

+#define MDMA_CCR_PL               MDMA_CCR_PL_Msk                              /*!< Priority level */

+#define MDMA_CCR_PL_0             (0x1UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000040 */

+#define MDMA_CCR_PL_1             (0x2UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000080 */

+#define MDMA_CCR_BEX_Pos          (12U)

+#define MDMA_CCR_BEX_Msk          (0x1UL << MDMA_CCR_BEX_Pos)                  /*!< 0x00001000 */

+#define MDMA_CCR_BEX              MDMA_CCR_BEX_Msk                             /*!< Byte Endianess eXchange */

+#define MDMA_CCR_HEX_Pos          (13U)

+#define MDMA_CCR_HEX_Msk          (0x1UL << MDMA_CCR_HEX_Pos)                  /*!< 0x00002000 */

+#define MDMA_CCR_HEX              MDMA_CCR_HEX_Msk                             /*!< Half word Endianess eXchange */

+#define MDMA_CCR_WEX_Pos          (14U)

+#define MDMA_CCR_WEX_Msk          (0x1UL << MDMA_CCR_WEX_Pos)                  /*!< 0x00004000 */

+#define MDMA_CCR_WEX              MDMA_CCR_WEX_Msk                             /*!< Word Endianess eXchange */

+#define MDMA_CCR_SWRQ_Pos         (16U)

+#define MDMA_CCR_SWRQ_Msk         (0x1UL << MDMA_CCR_SWRQ_Pos)                 /*!< 0x00010000 */

+#define MDMA_CCR_SWRQ             MDMA_CCR_SWRQ_Msk                            /*!< SW ReQuest */

+

+/********************  Bit definition for MDMA_CxTCR register  ****************/

+#define MDMA_CTCR_SINC_Pos        (0U)

+#define MDMA_CTCR_SINC_Msk        (0x3UL << MDMA_CTCR_SINC_Pos)                /*!< 0x00000003 */

+#define MDMA_CTCR_SINC            MDMA_CTCR_SINC_Msk                           /*!< Source increment mode */

+#define MDMA_CTCR_SINC_0          (0x1UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000001 */

+#define MDMA_CTCR_SINC_1          (0x2UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000002 */

+#define MDMA_CTCR_DINC_Pos        (2U)

+#define MDMA_CTCR_DINC_Msk        (0x3UL << MDMA_CTCR_DINC_Pos)                /*!< 0x0000000C */

+#define MDMA_CTCR_DINC            MDMA_CTCR_DINC_Msk                           /*!< Source increment mode */

+#define MDMA_CTCR_DINC_0          (0x1UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000004 */

+#define MDMA_CTCR_DINC_1          (0x2UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000008 */

+#define MDMA_CTCR_SSIZE_Pos       (4U)

+#define MDMA_CTCR_SSIZE_Msk       (0x3UL << MDMA_CTCR_SSIZE_Pos)               /*!< 0x00000030 */

+#define MDMA_CTCR_SSIZE           MDMA_CTCR_SSIZE_Msk                          /*!< Source data size */

+#define MDMA_CTCR_SSIZE_0         (0x1UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000010 */

+#define MDMA_CTCR_SSIZE_1         (0x2UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000020 */

+#define MDMA_CTCR_DSIZE_Pos       (6U)

+#define MDMA_CTCR_DSIZE_Msk       (0x3UL << MDMA_CTCR_DSIZE_Pos)               /*!< 0x000000C0 */

+#define MDMA_CTCR_DSIZE           MDMA_CTCR_DSIZE_Msk                          /*!< Destination data size */

+#define MDMA_CTCR_DSIZE_0         (0x1UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000040 */

+#define MDMA_CTCR_DSIZE_1         (0x2UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000080 */

+#define MDMA_CTCR_SINCOS_Pos      (8U)

+#define MDMA_CTCR_SINCOS_Msk      (0x3UL << MDMA_CTCR_SINCOS_Pos)              /*!< 0x00000300 */

+#define MDMA_CTCR_SINCOS          MDMA_CTCR_SINCOS_Msk                         /*!< Source increment offset size */

+#define MDMA_CTCR_SINCOS_0        (0x1UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000100 */

+#define MDMA_CTCR_SINCOS_1        (0x2UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000200 */

+#define MDMA_CTCR_DINCOS_Pos      (10U)

+#define MDMA_CTCR_DINCOS_Msk      (0x3UL << MDMA_CTCR_DINCOS_Pos)              /*!< 0x00000C00 */

+#define MDMA_CTCR_DINCOS          MDMA_CTCR_DINCOS_Msk                         /*!< Destination increment offset size */

+#define MDMA_CTCR_DINCOS_0        (0x1UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000400 */

+#define MDMA_CTCR_DINCOS_1        (0x2UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000800 */

+#define MDMA_CTCR_SBURST_Pos      (12U)

+#define MDMA_CTCR_SBURST_Msk      (0x7UL << MDMA_CTCR_SBURST_Pos)              /*!< 0x00007000 */

+#define MDMA_CTCR_SBURST          MDMA_CTCR_SBURST_Msk                         /*!< Source burst transfer configuration */

+#define MDMA_CTCR_SBURST_0        (0x1UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00001000 */

+#define MDMA_CTCR_SBURST_1        (0x2UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00002000 */

+#define MDMA_CTCR_SBURST_2        (0x4UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00004000 */

+#define MDMA_CTCR_DBURST_Pos      (15U)

+#define MDMA_CTCR_DBURST_Msk      (0x7UL << MDMA_CTCR_DBURST_Pos)              /*!< 0x00038000 */

+#define MDMA_CTCR_DBURST          MDMA_CTCR_DBURST_Msk                         /*!< Destination burst transfer configuration */

+#define MDMA_CTCR_DBURST_0        (0x1UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00008000 */

+#define MDMA_CTCR_DBURST_1        (0x2UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00010000 */

+#define MDMA_CTCR_DBURST_2        (0x4UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00020000 */

+#define MDMA_CTCR_TLEN_Pos        (18U)

+#define MDMA_CTCR_TLEN_Msk        (0x7FUL << MDMA_CTCR_TLEN_Pos)               /*!< 0x01FC0000 */

+#define MDMA_CTCR_TLEN            MDMA_CTCR_TLEN_Msk                           /*!< buffer Transfer Length (number of bytes - 1) */

+#define MDMA_CTCR_PKE_Pos         (25U)

+#define MDMA_CTCR_PKE_Msk         (0x1UL << MDMA_CTCR_PKE_Pos)                 /*!< 0x02000000 */

+#define MDMA_CTCR_PKE             MDMA_CTCR_PKE_Msk                            /*!< PacK Enable */

+#define MDMA_CTCR_PAM_Pos         (26U)

+#define MDMA_CTCR_PAM_Msk         (0x3UL << MDMA_CTCR_PAM_Pos)                 /*!< 0x0C000000 */

+#define MDMA_CTCR_PAM             MDMA_CTCR_PAM_Msk                            /*!< Padding/Alignement Mode */

+#define MDMA_CTCR_PAM_0           (0x1UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x4000000 */

+#define MDMA_CTCR_PAM_1           (0x2UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x8000000 */

+#define MDMA_CTCR_TRGM_Pos        (28U)

+#define MDMA_CTCR_TRGM_Msk        (0x3UL << MDMA_CTCR_TRGM_Pos)                /*!< 0x30000000 */

+#define MDMA_CTCR_TRGM            MDMA_CTCR_TRGM_Msk                           /*!< Trigger Mode */

+#define MDMA_CTCR_TRGM_0          (0x1UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x10000000 */

+#define MDMA_CTCR_TRGM_1          (0x2UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x20000000 */

+#define MDMA_CTCR_SWRM_Pos        (30U)

+#define MDMA_CTCR_SWRM_Msk        (0x1UL << MDMA_CTCR_SWRM_Pos)                /*!< 0x40000000 */

+#define MDMA_CTCR_SWRM            MDMA_CTCR_SWRM_Msk                           /*!< SW Request Mode */

+#define MDMA_CTCR_BWM_Pos         (31U)

+#define MDMA_CTCR_BWM_Msk         (0x1UL << MDMA_CTCR_BWM_Pos)                 /*!< 0x80000000 */

+#define MDMA_CTCR_BWM             MDMA_CTCR_BWM_Msk                            /*!< Bufferable Write Mode */

+

+/********************  Bit definition for MDMA_CxBNDTR register  ****************/

+#define MDMA_CBNDTR_BNDT_Pos      (0U)

+#define MDMA_CBNDTR_BNDT_Msk      (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos)          /*!< 0x0001FFFF */

+#define MDMA_CBNDTR_BNDT          MDMA_CBNDTR_BNDT_Msk                         /*!< Block Number of data bytes to transfer */

+#define MDMA_CBNDTR_BRSUM_Pos     (18U)

+#define MDMA_CBNDTR_BRSUM_Msk     (0x1UL << MDMA_CBNDTR_BRSUM_Pos)             /*!< 0x00040000 */

+#define MDMA_CBNDTR_BRSUM         MDMA_CBNDTR_BRSUM_Msk                        /*!< Block Repeat Source address Update Mode */

+#define MDMA_CBNDTR_BRDUM_Pos     (19U)

+#define MDMA_CBNDTR_BRDUM_Msk     (0x1UL << MDMA_CBNDTR_BRDUM_Pos)             /*!< 0x00080000 */

+#define MDMA_CBNDTR_BRDUM         MDMA_CBNDTR_BRDUM_Msk                        /*!< Block Repeat Destination address Update Mode */

+#define MDMA_CBNDTR_BRC_Pos       (20U)

+#define MDMA_CBNDTR_BRC_Msk       (0xFFFUL << MDMA_CBNDTR_BRC_Pos)             /*!< 0xFFF00000 */

+#define MDMA_CBNDTR_BRC           MDMA_CBNDTR_BRC_Msk                          /*!< Block Repeat Count */

+

+/********************  Bit definition for MDMA_CxSAR register  ****************/

+#define MDMA_CSAR_SAR_Pos         (0U)

+#define MDMA_CSAR_SAR_Msk         (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CSAR_SAR             MDMA_CSAR_SAR_Msk                            /*!< Source address */

+

+/********************  Bit definition for MDMA_CxDAR register  ****************/

+#define MDMA_CDAR_DAR_Pos         (0U)

+#define MDMA_CDAR_DAR_Msk         (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CDAR_DAR             MDMA_CDAR_DAR_Msk                            /*!< Destination address */

+

+/********************  Bit definition for MDMA_CxBRUR  ************************/

+#define MDMA_CBRUR_SUV_Pos        (0U)

+#define MDMA_CBRUR_SUV_Msk        (0xFFFFUL << MDMA_CBRUR_SUV_Pos)             /*!< 0x0000FFFF */

+#define MDMA_CBRUR_SUV            MDMA_CBRUR_SUV_Msk                           /*!< Source address Update Value */

+#define MDMA_CBRUR_DUV_Pos        (16U)

+#define MDMA_CBRUR_DUV_Msk        (0xFFFFUL << MDMA_CBRUR_DUV_Pos)             /*!< 0xFFFF0000 */

+#define MDMA_CBRUR_DUV            MDMA_CBRUR_DUV_Msk                           /*!< Destination address Update Value */

+

+/********************  Bit definition for MDMA_CxLAR  *************************/

+#define MDMA_CLAR_LAR_Pos         (0U)

+#define MDMA_CLAR_LAR_Msk         (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CLAR_LAR             MDMA_CLAR_LAR_Msk                            /*!< Link Address Register */

+

+/********************  Bit definition for MDMA_CxTBR)  ************************/

+#define MDMA_CTBR_TSEL_Pos        (0U)

+#define MDMA_CTBR_TSEL_Msk        (0xFFUL << MDMA_CTBR_TSEL_Pos)               /*!< 0x000000FF */

+#define MDMA_CTBR_TSEL            MDMA_CTBR_TSEL_Msk                           /*!< Trigger SELection */

+#define MDMA_CTBR_SBUS_Pos        (16U)

+#define MDMA_CTBR_SBUS_Msk        (0x1UL << MDMA_CTBR_SBUS_Pos)                /*!< 0x00010000 */

+#define MDMA_CTBR_SBUS            MDMA_CTBR_SBUS_Msk                           /*!< Source BUS select */

+#define MDMA_CTBR_DBUS_Pos        (17U)

+#define MDMA_CTBR_DBUS_Msk        (0x1UL << MDMA_CTBR_DBUS_Pos)                /*!< 0x00020000 */

+#define MDMA_CTBR_DBUS            MDMA_CTBR_DBUS_Msk                           /*!< Destination BUS select */

+

+/********************  Bit definition for MDMA_CxMAR)  ************************/

+#define MDMA_CMAR_MAR_Pos         (0U)

+#define MDMA_CMAR_MAR_Msk         (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CMAR_MAR             MDMA_CMAR_MAR_Msk                            /*!< Mask address */

+

+/********************  Bit definition for MDMA_CxMDR)  ************************/

+#define MDMA_CMDR_MDR_Pos         (0U)

+#define MDMA_CMDR_MDR_Msk         (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CMDR_MDR             MDMA_CMDR_MDR_Msk                            /*!< Mask Data */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Operational Amplifier (OPAMP)                      */

+/*                                                                            */

+/******************************************************************************/

+/*********************  Bit definition for OPAMPx_CSR register  ***************/

+#define OPAMP_CSR_OPAMPxEN_Pos           (0U)

+#define OPAMP_CSR_OPAMPxEN_Msk           (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)     /*!< 0x00000001 */

+#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */

+#define OPAMP_CSR_FORCEVP_Pos            (1U)

+#define OPAMP_CSR_FORCEVP_Msk            (0x1UL << OPAMP_CSR_FORCEVP_Pos)      /*!< 0x00000002 */

+#define OPAMP_CSR_FORCEVP                OPAMP_CSR_FORCEVP_Msk                 /*!< Force internal reference on VP */

+

+#define OPAMP_CSR_VPSEL_Pos              (2U)

+#define OPAMP_CSR_VPSEL_Msk              (0x3UL << OPAMP_CSR_VPSEL_Pos)        /*!< 0x0000000C */

+#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */

+#define OPAMP_CSR_VPSEL_0                (0x1UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000004 */

+#define OPAMP_CSR_VPSEL_1                (0x2UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000008 */

+

+#define OPAMP_CSR_VMSEL_Pos              (5U)

+#define OPAMP_CSR_VMSEL_Msk              (0x3UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000060 */

+#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */

+#define OPAMP_CSR_VMSEL_0                (0x1UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000020 */

+#define OPAMP_CSR_VMSEL_1                (0x2UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000040 */

+

+#define OPAMP_CSR_OPAHSM_Pos             (8U)

+#define OPAMP_CSR_OPAHSM_Msk             (0x1UL << OPAMP_CSR_OPAHSM_Pos)       /*!< 0x00000100 */

+#define OPAMP_CSR_OPAHSM                 OPAMP_CSR_OPAHSM_Msk                  /*!< Operational amplifier high speed mode */

+#define OPAMP_CSR_CALON_Pos              (11U)

+#define OPAMP_CSR_CALON_Msk              (0x1UL << OPAMP_CSR_CALON_Pos)        /*!< 0x00000800 */

+#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */

+

+#define OPAMP_CSR_CALSEL_Pos             (12U)

+#define OPAMP_CSR_CALSEL_Msk             (0x3UL << OPAMP_CSR_CALSEL_Pos)       /*!< 0x00003000 */

+#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */

+#define OPAMP_CSR_CALSEL_0               (0x1UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00001000 */

+#define OPAMP_CSR_CALSEL_1               (0x2UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */

+

+#define OPAMP_CSR_PGGAIN_Pos             (14U)

+#define OPAMP_CSR_PGGAIN_Msk             (0xFUL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x0003C000 */

+#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */

+#define OPAMP_CSR_PGGAIN_0               (0x1UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00004000 */

+#define OPAMP_CSR_PGGAIN_1               (0x2UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00008000 */

+#define OPAMP_CSR_PGGAIN_2               (0x4UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00010000 */

+#define OPAMP_CSR_PGGAIN_3               (0x8UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00020000 */

+

+#define OPAMP_CSR_USERTRIM_Pos           (18U)

+#define OPAMP_CSR_USERTRIM_Msk           (0x1UL << OPAMP_CSR_USERTRIM_Pos)     /*!< 0x00040000 */

+#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */

+#define OPAMP_CSR_TSTREF_Pos             (29U)

+#define OPAMP_CSR_TSTREF_Msk             (0x1UL << OPAMP_CSR_TSTREF_Pos)       /*!< 0x20000000 */

+#define OPAMP_CSR_TSTREF                 OPAMP_CSR_TSTREF_Msk                  /*!< OpAmp calibration reference voltage output control */

+#define OPAMP_CSR_CALOUT_Pos             (30U)

+#define OPAMP_CSR_CALOUT_Msk             (0x1UL << OPAMP_CSR_CALOUT_Pos)       /*!< 0x40000000 */

+#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier calibration output */

+

+/*********************  Bit definition for OPAMP1_CSR register  ***************/

+#define OPAMP1_CSR_OPAEN_Pos              (0U)

+#define OPAMP1_CSR_OPAEN_Msk              (0x1UL << OPAMP1_CSR_OPAEN_Pos)      /*!< 0x00000001 */

+#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */

+#define OPAMP1_CSR_FORCEVP_Pos            (1U)

+#define OPAMP1_CSR_FORCEVP_Msk            (0x1UL << OPAMP1_CSR_FORCEVP_Pos)    /*!< 0x00000002 */

+#define OPAMP1_CSR_FORCEVP                OPAMP1_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */

+

+#define OPAMP1_CSR_VPSEL_Pos              (2U)

+#define OPAMP1_CSR_VPSEL_Msk              (0x3UL << OPAMP1_CSR_VPSEL_Pos)      /*!< 0x0000000C */

+#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */

+#define OPAMP1_CSR_VPSEL_0                (0x1UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000004 */

+#define OPAMP1_CSR_VPSEL_1                (0x2UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000008 */

+

+#define OPAMP1_CSR_VMSEL_Pos              (5U)

+#define OPAMP1_CSR_VMSEL_Msk              (0x3UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000060 */

+#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */

+#define OPAMP1_CSR_VMSEL_0                (0x1UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000020 */

+#define OPAMP1_CSR_VMSEL_1                (0x2UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000040 */

+

+#define OPAMP1_CSR_OPAHSM_Pos             (8U)

+#define OPAMP1_CSR_OPAHSM_Msk             (0x1UL << OPAMP1_CSR_OPAHSM_Pos)     /*!< 0x00000100 */

+#define OPAMP1_CSR_OPAHSM                 OPAMP1_CSR_OPAHSM_Msk                /*!< Operational amplifier1 high speed mode */

+#define OPAMP1_CSR_CALON_Pos              (11U)

+#define OPAMP1_CSR_CALON_Msk              (0x1UL << OPAMP1_CSR_CALON_Pos)      /*!< 0x00000800 */

+#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */

+

+#define OPAMP1_CSR_CALSEL_Pos             (12U)

+#define OPAMP1_CSR_CALSEL_Msk             (0x3UL << OPAMP1_CSR_CALSEL_Pos)     /*!< 0x00003000 */

+#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */

+#define OPAMP1_CSR_CALSEL_0               (0x1UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00001000 */

+#define OPAMP1_CSR_CALSEL_1               (0x2UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */

+

+#define OPAMP1_CSR_PGGAIN_Pos             (14U)

+#define OPAMP1_CSR_PGGAIN_Msk             (0xFUL << OPAMP1_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */

+#define OPAMP1_CSR_PGGAIN                 OPAMP1_CSR_PGGAIN_Msk                /*!< Operational amplifier1 Programmable amplifier gain value */

+#define OPAMP1_CSR_PGGAIN_0               (0x1UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00004000 */

+#define OPAMP1_CSR_PGGAIN_1               (0x2UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00008000 */

+#define OPAMP1_CSR_PGGAIN_2               (0x4UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00010000 */

+#define OPAMP1_CSR_PGGAIN_3               (0x8UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00020000 */

+

+#define OPAMP1_CSR_USERTRIM_Pos           (18U)

+#define OPAMP1_CSR_USERTRIM_Msk           (0x1UL << OPAMP1_CSR_USERTRIM_Pos)   /*!< 0x00040000 */

+#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */

+#define OPAMP1_CSR_TSTREF_Pos             (29U)

+#define OPAMP1_CSR_TSTREF_Msk             (0x1UL << OPAMP1_CSR_TSTREF_Pos)     /*!< 0x20000000 */

+#define OPAMP1_CSR_TSTREF                 OPAMP1_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */

+#define OPAMP1_CSR_CALOUT_Pos             (30U)

+#define OPAMP1_CSR_CALOUT_Msk             (0x1UL << OPAMP1_CSR_CALOUT_Pos)     /*!< 0x40000000 */

+#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */

+

+/*********************  Bit definition for OPAMP2_CSR register  ***************/

+#define OPAMP2_CSR_OPAEN_Pos              (0U)

+#define OPAMP2_CSR_OPAEN_Msk              (0x1UL << OPAMP2_CSR_OPAEN_Pos)      /*!< 0x00000001 */

+#define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */

+#define OPAMP2_CSR_FORCEVP_Pos            (1U)

+#define OPAMP2_CSR_FORCEVP_Msk            (0x1UL << OPAMP2_CSR_FORCEVP_Pos)    /*!< 0x00000002 */

+#define OPAMP2_CSR_FORCEVP                OPAMP2_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */

+

+#define OPAMP2_CSR_VPSEL_Pos              (2U)

+#define OPAMP2_CSR_VPSEL_Msk              (0x3UL << OPAMP2_CSR_VPSEL_Pos)      /*!< 0x0000000C */

+#define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */

+#define OPAMP2_CSR_VPSEL_0                (0x1UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000004 */

+#define OPAMP2_CSR_VPSEL_1                (0x2UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000008 */

+

+#define OPAMP2_CSR_VMSEL_Pos              (5U)

+#define OPAMP2_CSR_VMSEL_Msk              (0x3UL << OPAMP2_CSR_VMSEL_Pos)      /*!< 0x00000060 */

+#define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */

+#define OPAMP2_CSR_VMSEL_0                (0x1UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000020 */

+#define OPAMP2_CSR_VMSEL_1                (0x2UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000040 */

+

+#define OPAMP2_CSR_OPAHSM_Pos             (8U)

+#define OPAMP2_CSR_OPAHSM_Msk             (0x1UL << OPAMP2_CSR_OPAHSM_Pos)     /*!< 0x00000100 */

+#define OPAMP2_CSR_OPAHSM                 OPAMP2_CSR_OPAHSM_Msk                /*!< Operational amplifier2 high speed mode */

+#define OPAMP2_CSR_CALON_Pos              (11U)

+#define OPAMP2_CSR_CALON_Msk              (0x1UL << OPAMP2_CSR_CALON_Pos)      /*!< 0x00000800 */

+#define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */

+

+#define OPAMP2_CSR_CALSEL_Pos             (12U)

+#define OPAMP2_CSR_CALSEL_Msk             (0x3UL << OPAMP2_CSR_CALSEL_Pos)     /*!< 0x00003000 */

+#define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */

+#define OPAMP2_CSR_CALSEL_0               (0x1UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00001000 */

+#define OPAMP2_CSR_CALSEL_1               (0x2UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */

+

+#define OPAMP2_CSR_PGGAIN_Pos             (14U)

+#define OPAMP2_CSR_PGGAIN_Msk             (0xFUL << OPAMP2_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */

+#define OPAMP2_CSR_PGGAIN                 OPAMP2_CSR_PGGAIN_Msk                /*!< Operational amplifier2 Programmable amplifier gain value */

+#define OPAMP2_CSR_PGGAIN_0               (0x1UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00004000 */

+#define OPAMP2_CSR_PGGAIN_1               (0x2UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00008000 */

+#define OPAMP2_CSR_PGGAIN_2               (0x4UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00010000 */

+#define OPAMP2_CSR_PGGAIN_3               (0x8UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00020000 */

+

+#define OPAMP2_CSR_USERTRIM_Pos           (18U)

+#define OPAMP2_CSR_USERTRIM_Msk           (0x1UL << OPAMP2_CSR_USERTRIM_Pos)   /*!< 0x00040000 */

+#define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */

+#define OPAMP2_CSR_TSTREF_Pos             (29U)

+#define OPAMP2_CSR_TSTREF_Msk             (0x1UL << OPAMP2_CSR_TSTREF_Pos)     /*!< 0x20000000 */

+#define OPAMP2_CSR_TSTREF                 OPAMP2_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */

+#define OPAMP2_CSR_CALOUT_Pos             (30U)

+#define OPAMP2_CSR_CALOUT_Msk             (0x1UL << OPAMP2_CSR_CALOUT_Pos)     /*!< 0x40000000 */

+#define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */

+

+/*******************  Bit definition for OPAMP_OTR register  ******************/

+#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */

+#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP1_OTR register  ******************/

+#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */

+#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP2_OTR register  ******************/

+#define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */

+#define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP_HSOTR register  ****************/

+#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP_HSOTR_TRIMHSOFFSETN        OPAMP_HSOTR_TRIMHSOFFSETN_Msk         /*!< Trim for NMOS differential pairs */

+#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP_HSOTR_TRIMHSOFFSETP        OPAMP_HSOTR_TRIMHSOFFSETP_Msk         /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP1_HSOTR register  ****************/

+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP1_HSOTR_TRIMHSOFFSETN        OPAMP1_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */

+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP1_HSOTR_TRIMHSOFFSETP        OPAMP1_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP2_HSOTR register  ****************/

+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP2_HSOTR_TRIMHSOFFSETN        OPAMP2_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */

+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP2_HSOTR_TRIMHSOFFSETP        OPAMP2_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             Power Control                                  */

+/*                                                                            */

+/******************************************************************************/

+/*************************  NUMBER OF POWER DOMAINS  **************************/

+#define POWER_DOMAINS_NUMBER           3U                                      /*!< 3 Domains */

+

+/********************  Bit definition for PWR_CR1 register  *******************/

+#define PWR_CR1_ALS_Pos                (17U)

+#define PWR_CR1_ALS_Msk                (0x3UL << PWR_CR1_ALS_Pos)              /*!< 0x00060000 */

+#define PWR_CR1_ALS                    PWR_CR1_ALS_Msk                         /*!< Analog Voltage Detector level selection */

+#define PWR_CR1_ALS_0                  (0x1UL << PWR_CR1_ALS_Pos)              /*!< 0x00020000 */

+#define PWR_CR1_ALS_1                  (0x2UL << PWR_CR1_ALS_Pos)              /*!< 0x00040000 */

+#define PWR_CR1_AVDEN_Pos              (16U)

+#define PWR_CR1_AVDEN_Msk              (0x1UL << PWR_CR1_AVDEN_Pos)            /*!< 0x00010000 */

+#define PWR_CR1_AVDEN                  PWR_CR1_AVDEN_Msk                       /*!< Analog Voltage Detector Enable */

+#define PWR_CR1_SVOS_Pos               (14U)

+#define PWR_CR1_SVOS_Msk               (0x3UL << PWR_CR1_SVOS_Pos)             /*!< 0x0000C000 */

+#define PWR_CR1_SVOS                   PWR_CR1_SVOS_Msk                        /*!< System STOP mode Voltage Scaling selection */

+#define PWR_CR1_SVOS_0                 (0x1UL << PWR_CR1_SVOS_Pos)             /*!< 0x00004000 */

+#define PWR_CR1_SVOS_1                 (0x2UL << PWR_CR1_SVOS_Pos)             /*!< 0x00008000 */

+#define PWR_CR1_FLPS_Pos               (9U)

+#define PWR_CR1_FLPS_Msk               (0x1UL << PWR_CR1_FLPS_Pos)             /*!< 0x00000200 */

+#define PWR_CR1_FLPS                   PWR_CR1_FLPS_Msk                        /*!< Flash low power mode in DSTOP */

+#define PWR_CR1_DBP_Pos                (8U)

+#define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */

+#define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable Back-up domain Protection */

+#define PWR_CR1_PLS_Pos                (5U)

+#define PWR_CR1_PLS_Msk                (0x7UL << PWR_CR1_PLS_Pos)              /*!< 0x000000E0 */

+#define PWR_CR1_PLS                    PWR_CR1_PLS_Msk                         /*!< Programmable Voltage Detector level selection */

+#define PWR_CR1_PLS_0                  (0x1UL << PWR_CR1_PLS_Pos)              /*!< 0x00000020 */

+#define PWR_CR1_PLS_1                  (0x2UL << PWR_CR1_PLS_Pos)              /*!< 0x00000040 */

+#define PWR_CR1_PLS_2                  (0x4UL << PWR_CR1_PLS_Pos)              /*!< 0x00000080 */

+#define PWR_CR1_PVDEN_Pos              (4U)

+#define PWR_CR1_PVDEN_Msk              (0x1UL << PWR_CR1_PVDEN_Pos)            /*!< 0x00000010 */

+#define PWR_CR1_PVDEN                  PWR_CR1_PVDEN_Msk                       /*!< Programmable Voltage detector enable */

+#define PWR_CR1_LPDS_Pos               (0U)

+#define PWR_CR1_LPDS_Msk               (0x1UL << PWR_CR1_LPDS_Pos)             /*!< 0x00000001 */

+#define PWR_CR1_LPDS                   PWR_CR1_LPDS_Msk                        /*!< Low Power Deepsleep with SVOS3 */

+

+/*!< PVD level configuration */

+#define PWR_CR1_PLS_LEV0               (0UL)                                   /*!< PVD level 0 */

+#define PWR_CR1_PLS_LEV1_Pos           (5U)

+#define PWR_CR1_PLS_LEV1_Msk           (0x1UL << PWR_CR1_PLS_LEV1_Pos)         /*!< 0x00000020 */

+#define PWR_CR1_PLS_LEV1               PWR_CR1_PLS_LEV1_Msk                    /*!< PVD level 1 */

+#define PWR_CR1_PLS_LEV2_Pos           (6U)

+#define PWR_CR1_PLS_LEV2_Msk           (0x1UL << PWR_CR1_PLS_LEV2_Pos)         /*!< 0x00000040 */

+#define PWR_CR1_PLS_LEV2               PWR_CR1_PLS_LEV2_Msk                    /*!< PVD level 2 */

+#define PWR_CR1_PLS_LEV3_Pos           (5U)

+#define PWR_CR1_PLS_LEV3_Msk           (0x3UL << PWR_CR1_PLS_LEV3_Pos)         /*!< 0x00000060 */

+#define PWR_CR1_PLS_LEV3               PWR_CR1_PLS_LEV3_Msk                    /*!< PVD level 3 */

+#define PWR_CR1_PLS_LEV4_Pos           (7U)

+#define PWR_CR1_PLS_LEV4_Msk           (0x1UL << PWR_CR1_PLS_LEV4_Pos)         /*!< 0x00000080 */

+#define PWR_CR1_PLS_LEV4               PWR_CR1_PLS_LEV4_Msk                    /*!< PVD level 4 */

+#define PWR_CR1_PLS_LEV5_Pos           (5U)

+#define PWR_CR1_PLS_LEV5_Msk           (0x5UL << PWR_CR1_PLS_LEV5_Pos)         /*!< 0x000000A0 */

+#define PWR_CR1_PLS_LEV5               PWR_CR1_PLS_LEV5_Msk                    /*!< PVD level 5 */

+#define PWR_CR1_PLS_LEV6_Pos           (6U)

+#define PWR_CR1_PLS_LEV6_Msk           (0x3UL << PWR_CR1_PLS_LEV6_Pos)         /*!< 0x000000C0 */

+#define PWR_CR1_PLS_LEV6               PWR_CR1_PLS_LEV6_Msk                    /*!< PVD level 6 */

+#define PWR_CR1_PLS_LEV7_Pos           (5U)

+#define PWR_CR1_PLS_LEV7_Msk           (0x7UL << PWR_CR1_PLS_LEV7_Pos)         /*!< 0x000000E0 */

+#define PWR_CR1_PLS_LEV7               PWR_CR1_PLS_LEV7_Msk                    /*!< PVD level 7 */

+

+/*!< AVD level configuration */

+#define PWR_CR1_ALS_LEV0               (0UL)                                   /*!< AVD level 0 */

+#define PWR_CR1_ALS_LEV1_Pos           (17U)

+#define PWR_CR1_ALS_LEV1_Msk           (0x1UL << PWR_CR1_ALS_LEV1_Pos)         /*!< 0x00020000 */

+#define PWR_CR1_ALS_LEV1               PWR_CR1_ALS_LEV1_Msk                    /*!< AVD level 1 */

+#define PWR_CR1_ALS_LEV2_Pos           (18U)

+#define PWR_CR1_ALS_LEV2_Msk           (0x1UL << PWR_CR1_ALS_LEV2_Pos)         /*!< 0x00040000 */

+#define PWR_CR1_ALS_LEV2               PWR_CR1_ALS_LEV2_Msk                    /*!< AVD level 2 */

+#define PWR_CR1_ALS_LEV3_Pos           (17U)

+#define PWR_CR1_ALS_LEV3_Msk           (0x3UL << PWR_CR1_ALS_LEV3_Pos)         /*!< 0x00060000 */

+#define PWR_CR1_ALS_LEV3               PWR_CR1_ALS_LEV3_Msk                    /*!< AVD level 3 */

+

+/********************  Bit definition for PWR_CSR1 register  ******************/

+#define PWR_CSR1_AVDO_Pos              (16U)

+#define PWR_CSR1_AVDO_Msk              (0x1UL << PWR_CSR1_AVDO_Pos)            /*!< 0x00010000 */

+#define PWR_CSR1_AVDO                  PWR_CSR1_AVDO_Msk                       /*!< Analog Voltage Detect Output */

+#define PWR_CSR1_ACTVOS_Pos            (14U)

+#define PWR_CSR1_ACTVOS_Msk            (0x3UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x0000C000 */

+#define PWR_CSR1_ACTVOS                PWR_CSR1_ACTVOS_Msk                     /*!< Current actual used VOS for VDD11 Voltage Scaling */

+#define PWR_CSR1_ACTVOS_0              (0x1UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00004000 */

+#define PWR_CSR1_ACTVOS_1              (0x2UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00008000 */

+#define PWR_CSR1_ACTVOSRDY_Pos         (13U)

+#define PWR_CSR1_ACTVOSRDY_Msk         (0x1UL << PWR_CSR1_ACTVOSRDY_Pos)       /*!< 0x00002000 */

+#define PWR_CSR1_ACTVOSRDY             PWR_CSR1_ACTVOSRDY_Msk                  /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling  */

+#define PWR_CSR1_PVDO_Pos              (4U)

+#define PWR_CSR1_PVDO_Msk              (0x1UL << PWR_CSR1_PVDO_Pos)            /*!< 0x00000010 */

+#define PWR_CSR1_PVDO                  PWR_CSR1_PVDO_Msk                       /*!< Programmable Voltage Detect Output */

+

+/********************  Bit definition for PWR_CR2 register  *******************/

+#define PWR_CR2_TEMPH_Pos              (23U)

+#define PWR_CR2_TEMPH_Msk              (0x1UL << PWR_CR2_TEMPH_Pos)            /*!< 0x00800000 */

+#define PWR_CR2_TEMPH                  PWR_CR2_TEMPH_Msk                       /*!< Monitored temperature level above high threshold */

+#define PWR_CR2_TEMPL_Pos              (22U)

+#define PWR_CR2_TEMPL_Msk              (0x1UL << PWR_CR2_TEMPL_Pos)            /*!< 0x00400000 */

+#define PWR_CR2_TEMPL                  PWR_CR2_TEMPL_Msk                       /*!< Monitored temperature level above low threshold */

+#define PWR_CR2_VBATH_Pos              (21U)

+#define PWR_CR2_VBATH_Msk              (0x1UL << PWR_CR2_VBATH_Pos)            /*!< 0x00200000 */

+#define PWR_CR2_VBATH                  PWR_CR2_VBATH_Msk                       /*!< Monitored VBAT level above high threshold */

+#define PWR_CR2_VBATL_Pos              (20U)

+#define PWR_CR2_VBATL_Msk              (0x1UL << PWR_CR2_VBATL_Pos)            /*!< 0x00100000 */

+#define PWR_CR2_VBATL                  PWR_CR2_VBATL_Msk                       /*!< Monitored VBAT level above low threshold */

+#define PWR_CR2_BRRDY_Pos              (16U)

+#define PWR_CR2_BRRDY_Msk              (0x1UL << PWR_CR2_BRRDY_Pos)            /*!< 0x00010000 */

+#define PWR_CR2_BRRDY                  PWR_CR2_BRRDY_Msk                       /*!< Backup regulator ready */

+#define PWR_CR2_MONEN_Pos              (4U)

+#define PWR_CR2_MONEN_Msk              (0x1UL << PWR_CR2_MONEN_Pos)            /*!< 0x00000010 */

+#define PWR_CR2_MONEN                  PWR_CR2_MONEN_Msk                       /*!< VBAT and temperature monitoring enable */

+#define PWR_CR2_BREN_Pos               (0U)

+#define PWR_CR2_BREN_Msk               (0x1UL << PWR_CR2_BREN_Pos)             /*!< 0x00000001 */

+#define PWR_CR2_BREN                   PWR_CR2_BREN_Msk                        /*!< Backup regulator enable */

+

+/********************  Bit definition for PWR_CR3 register  *******************/

+#define PWR_CR3_USB33RDY_Pos           (26U)

+#define PWR_CR3_USB33RDY_Msk           (0x1UL << PWR_CR3_USB33RDY_Pos)         /*!< 0x04000000 */

+#define PWR_CR3_USB33RDY               PWR_CR3_USB33RDY_Msk                    /*!< USB supply ready */

+#define PWR_CR3_USBREGEN_Pos           (25U)

+#define PWR_CR3_USBREGEN_Msk           (0x1UL << PWR_CR3_USBREGEN_Pos)         /*!< 0x02000000 */

+#define PWR_CR3_USBREGEN               PWR_CR3_USBREGEN_Msk                    /*!< USB regulator enable */

+#define PWR_CR3_USB33DEN_Pos           (24U)

+#define PWR_CR3_USB33DEN_Msk           (0x1UL << PWR_CR3_USB33DEN_Pos)         /*!< 0x01000000 */

+#define PWR_CR3_USB33DEN               PWR_CR3_USB33DEN_Msk                    /*!< VDD33_USB voltage level detector enable */

+#define PWR_CR3_SMPSEXTRDY_Pos         (16U)

+#define PWR_CR3_SMPSEXTRDY_Msk         (0x1UL << PWR_CR3_SMPSEXTRDY_Pos)       /*!< 0x00010000 */

+#define PWR_CR3_SMPSEXTRDY             PWR_CR3_SMPSEXTRDY_Msk                  /*!< SMPS External supply ready */

+#define PWR_CR3_VBRS_Pos               (9U)

+#define PWR_CR3_VBRS_Msk               (0x1UL << PWR_CR3_VBRS_Pos)             /*!< 0x00000200 */

+#define PWR_CR3_VBRS                   PWR_CR3_VBRS_Msk                        /*!< VBAT charging resistor selection */

+#define PWR_CR3_VBE_Pos                (8U)

+#define PWR_CR3_VBE_Msk                (0x1UL << PWR_CR3_VBE_Pos)              /*!< 0x00000100 */

+#define PWR_CR3_VBE                    PWR_CR3_VBE_Msk                         /*!< VBAT charging enable */

+#define PWR_CR3_SMPSLEVEL_Pos          (4U)

+#define PWR_CR3_SMPSLEVEL_Msk          (0x3UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000030 */

+#define PWR_CR3_SMPSLEVEL              PWR_CR3_SMPSLEVEL_Msk                   /*!< SMPS output Voltage */

+#define PWR_CR3_SMPSLEVEL_0            (0x1UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000010 */

+#define PWR_CR3_SMPSLEVEL_1            (0x2UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000020 */

+#define PWR_CR3_SMPSEXTHP_Pos          (3U)

+#define PWR_CR3_SMPSEXTHP_Msk          (0x1UL << PWR_CR3_SMPSEXTHP_Pos)        /*!< 0x00000008 */

+#define PWR_CR3_SMPSEXTHP              PWR_CR3_SMPSEXTHP_Msk                   /*!< SMPS forced ON and in High Power MR mode */

+#define PWR_CR3_SMPSEN_Pos             (2U)

+#define PWR_CR3_SMPSEN_Msk             (0x1UL << PWR_CR3_SMPSEN_Pos)           /*!< 0x00000004 */

+#define PWR_CR3_SMPSEN                 PWR_CR3_SMPSEN_Msk                      /*!< SMPS Enable */

+#define PWR_CR3_LDOEN_Pos              (1U)

+#define PWR_CR3_LDOEN_Msk              (0x1UL << PWR_CR3_LDOEN_Pos)            /*!< 0x00000002 */

+#define PWR_CR3_LDOEN                  PWR_CR3_LDOEN_Msk                       /*!< Low Drop Output regulator enable */

+#define PWR_CR3_BYPASS_Pos             (0U)

+#define PWR_CR3_BYPASS_Msk             (0x1UL << PWR_CR3_BYPASS_Pos)           /*!< 0x00000001 */

+#define PWR_CR3_BYPASS                 PWR_CR3_BYPASS_Msk                      /*!< Power Management Unit bypass */

+

+/********************  Bit definition for PWR_CPUCR register  *****************/

+#define PWR_CPUCR_RUN_D3_Pos           (11U)

+#define PWR_CPUCR_RUN_D3_Msk           (0x1UL << PWR_CPUCR_RUN_D3_Pos)         /*!< 0x00000800 */

+#define PWR_CPUCR_RUN_D3               PWR_CPUCR_RUN_D3_Msk                    /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */

+#define PWR_CPUCR_HOLD2_Pos            (10U)

+#define PWR_CPUCR_HOLD2_Msk            (0x1UL << PWR_CPUCR_HOLD2_Pos)          /*!< 0x00000400 */

+#define PWR_CPUCR_HOLD2                PWR_CPUCR_HOLD2_Msk                     /*!< Hold the CPU2 and allocated peripherals when exiting STOP mode */

+#define PWR_CPUCR_CSSF_Pos             (9U)

+#define PWR_CPUCR_CSSF_Msk             (0x1UL << PWR_CPUCR_CSSF_Pos)           /*!< 0x00000200 */

+#define PWR_CPUCR_CSSF                 PWR_CPUCR_CSSF_Msk                      /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */

+#define PWR_CPUCR_SBF_D2_Pos           (8U)

+#define PWR_CPUCR_SBF_D2_Msk           (0x1UL << PWR_CPUCR_SBF_D2_Pos)         /*!< 0x00000100 */

+#define PWR_CPUCR_SBF_D2               PWR_CPUCR_SBF_D2_Msk                    /*!< D2 domain DSTANDBY Flag */

+#define PWR_CPUCR_SBF_D1_Pos           (7U)

+#define PWR_CPUCR_SBF_D1_Msk           (0x1UL << PWR_CPUCR_SBF_D1_Pos)         /*!< 0x00000080 */

+#define PWR_CPUCR_SBF_D1               PWR_CPUCR_SBF_D1_Msk                    /*!< D1 domain DSTANDBY Flag */

+#define PWR_CPUCR_SBF_Pos              (6U)

+#define PWR_CPUCR_SBF_Msk              (0x1UL << PWR_CPUCR_SBF_Pos)            /*!< 0x00000040 */

+#define PWR_CPUCR_SBF                  PWR_CPUCR_SBF_Msk                       /*!< System STANDBY Flag */

+#define PWR_CPUCR_STOPF_Pos            (5U)

+#define PWR_CPUCR_STOPF_Msk            (0x1UL << PWR_CPUCR_STOPF_Pos)          /*!< 0x00000020 */

+#define PWR_CPUCR_STOPF                PWR_CPUCR_STOPF_Msk                     /*!< STOP Flag */

+#define PWR_CPUCR_HOLD2F_Pos           (4U)

+#define PWR_CPUCR_HOLD2F_Msk           (0x1UL << PWR_CPUCR_HOLD2F_Pos)         /*!< 0x00000010 */

+#define PWR_CPUCR_HOLD2F               PWR_CPUCR_HOLD2F_Msk                    /*!< CPU2 in hold wakeup flag */

+#define PWR_CPUCR_PDDS_D3_Pos          (2U)

+#define PWR_CPUCR_PDDS_D3_Msk          (0x1UL << PWR_CPUCR_PDDS_D3_Pos)        /*!< 0x00000004 */

+#define PWR_CPUCR_PDDS_D3              PWR_CPUCR_PDDS_D3_Msk                   /*!< System D3 domain Power Down Deepsleep */

+#define PWR_CPUCR_PDDS_D2_Pos          (1U)

+#define PWR_CPUCR_PDDS_D2_Msk          (0x1UL << PWR_CPUCR_PDDS_D2_Pos)        /*!< 0x00000002 */

+#define PWR_CPUCR_PDDS_D2              PWR_CPUCR_PDDS_D2_Msk                   /*!< D2 domain Power Down Deepsleep */

+#define PWR_CPUCR_PDDS_D1_Pos          (0U)

+#define PWR_CPUCR_PDDS_D1_Msk          (0x1UL << PWR_CPUCR_PDDS_D1_Pos)        /*!< 0x00000001 */

+#define PWR_CPUCR_PDDS_D1              PWR_CPUCR_PDDS_D1_Msk                   /*!< D1 domain Power Down Deepsleep selection */

+

+/********************  Bit definition for PWR_CPU2CR register  ****************/

+#define PWR_CPU2CR_RUN_D3_Pos          (11U)

+#define PWR_CPU2CR_RUN_D3_Msk          (0x1UL << PWR_CPU2CR_RUN_D3_Pos)        /*!< 0x00000800 */

+#define PWR_CPU2CR_RUN_D3              PWR_CPU2CR_RUN_D3_Msk                   /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */

+#define PWR_CPU2CR_HOLD1_Pos           (10U)

+#define PWR_CPU2CR_HOLD1_Msk           (0x1UL << PWR_CPU2CR_HOLD1_Pos)         /*!< 0x00000400 */

+#define PWR_CPU2CR_HOLD1               PWR_CPU2CR_HOLD1_Msk                    /*!< Hold the CPU1 and allocated peripherals when exiting STOP mode */

+#define PWR_CPU2CR_CSSF_Pos            (9U)

+#define PWR_CPU2CR_CSSF_Msk            (0x1UL << PWR_CPU2CR_CSSF_Pos)          /*!< 0x00000200 */

+#define PWR_CPU2CR_CSSF                PWR_CPU2CR_CSSF_Msk                     /*!< Clear D2 domain CPU2 STANDBY, STOP and HOLD flags */

+#define PWR_CPU2CR_SBF_D2_Pos          (8U)

+#define PWR_CPU2CR_SBF_D2_Msk          (0x1UL << PWR_CPU2CR_SBF_D2_Pos)        /*!< 0x00000100 */

+#define PWR_CPU2CR_SBF_D2              PWR_CPU2CR_SBF_D2_Msk                   /*!< D2 domain DSTANDBY Flag */

+#define PWR_CPU2CR_SBF_D1_Pos          (7U)

+#define PWR_CPU2CR_SBF_D1_Msk          (0x1UL << PWR_CPU2CR_SBF_D1_Pos)        /*!< 0x00000080 */

+#define PWR_CPU2CR_SBF_D1              PWR_CPU2CR_SBF_D1_Msk                   /*!< D1 domain DSTANDBY Flag */

+#define PWR_CPU2CR_SBF_Pos             (6U)

+#define PWR_CPU2CR_SBF_Msk             (0x1UL << PWR_CPU2CR_SBF_Pos)           /*!< 0x00000040 */

+#define PWR_CPU2CR_SBF                 PWR_CPU2CR_SBF_Msk                      /*!< System STANDBY Flag */

+#define PWR_CPU2CR_STOPF_Pos           (5U)

+#define PWR_CPU2CR_STOPF_Msk           (0x1UL << PWR_CPU2CR_STOPF_Pos)         /*!< 0x00000020 */

+#define PWR_CPU2CR_STOPF               PWR_CPU2CR_STOPF_Msk                    /*!< STOP Flag */

+#define PWR_CPU2CR_HOLD1F_Pos          (4U)

+#define PWR_CPU2CR_HOLD1F_Msk          (0x1UL << PWR_CPU2CR_HOLD1F_Pos)        /*!< 0x00000010 */

+#define PWR_CPU2CR_HOLD1F              PWR_CPU2CR_HOLD1F_Msk                   /*!< CPU1 in hold wakeup flag */

+#define PWR_CPU2CR_PDDS_D3_Pos         (2U)

+#define PWR_CPU2CR_PDDS_D3_Msk         (0x1UL << PWR_CPU2CR_PDDS_D3_Pos)       /*!< 0x00000004 */

+#define PWR_CPU2CR_PDDS_D3             PWR_CPU2CR_PDDS_D3_Msk                  /*!< System D3 domain Power Down Deepsleep */

+#define PWR_CPU2CR_PDDS_D2_Pos         (1U)

+#define PWR_CPU2CR_PDDS_D2_Msk         (0x1UL << PWR_CPU2CR_PDDS_D2_Pos)       /*!< 0x00000002 */

+#define PWR_CPU2CR_PDDS_D2             PWR_CPU2CR_PDDS_D2_Msk                  /*!< D2 domain Power Down Deepsleep */

+#define PWR_CPU2CR_PDDS_D1_Pos         (0U)

+#define PWR_CPU2CR_PDDS_D1_Msk         (0x1UL << PWR_CPU2CR_PDDS_D1_Pos)       /*!< 0x00000001 */

+#define PWR_CPU2CR_PDDS_D1             PWR_CPU2CR_PDDS_D1_Msk                  /*!< D1 domain Power Down Deepsleep selection */

+

+

+/********************  Bit definition for PWR_D3CR register  ******************/

+#define PWR_D3CR_VOS_Pos               (14U)

+#define PWR_D3CR_VOS_Msk               (0x3UL << PWR_D3CR_VOS_Pos)             /*!< 0x0000C000 */

+#define PWR_D3CR_VOS                   PWR_D3CR_VOS_Msk                        /*!< Voltage Scaling selection according performance */

+#define PWR_D3CR_VOS_0                 (0x1UL << PWR_D3CR_VOS_Pos)             /*!< 0x00004000 */

+#define PWR_D3CR_VOS_1                 (0x2UL << PWR_D3CR_VOS_Pos)             /*!< 0x00008000 */

+#define PWR_D3CR_VOSRDY_Pos            (13U)

+#define PWR_D3CR_VOSRDY_Msk            (0x1UL << PWR_D3CR_VOSRDY_Pos)          /*!< 0x00002000 */

+#define PWR_D3CR_VOSRDY                PWR_D3CR_VOSRDY_Msk                     /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */

+

+/******************  Bit definition for PWR_WKUPCR register  ******************/

+#define PWR_WKUPCR_WKUPC6_Pos          (5U)

+#define PWR_WKUPCR_WKUPC6_Msk          (0x1UL << PWR_WKUPCR_WKUPC6_Pos)        /*!< 0x00000020 */

+#define PWR_WKUPCR_WKUPC6              PWR_WKUPCR_WKUPC6_Msk                   /*!< Clear Wakeup Pin Flag 6 */

+#define PWR_WKUPCR_WKUPC5_Pos          (4U)

+#define PWR_WKUPCR_WKUPC5_Msk          (0x1UL << PWR_WKUPCR_WKUPC5_Pos)        /*!< 0x00000010 */

+#define PWR_WKUPCR_WKUPC5              PWR_WKUPCR_WKUPC5_Msk                   /*!< Clear Wakeup Pin Flag 5 */

+#define PWR_WKUPCR_WKUPC4_Pos          (3U)

+#define PWR_WKUPCR_WKUPC4_Msk          (0x1UL << PWR_WKUPCR_WKUPC4_Pos)        /*!< 0x00000008 */

+#define PWR_WKUPCR_WKUPC4              PWR_WKUPCR_WKUPC4_Msk                   /*!< Clear Wakeup Pin Flag 4 */

+#define PWR_WKUPCR_WKUPC3_Pos          (2U)

+#define PWR_WKUPCR_WKUPC3_Msk          (0x1UL << PWR_WKUPCR_WKUPC3_Pos)        /*!< 0x00000004 */

+#define PWR_WKUPCR_WKUPC3              PWR_WKUPCR_WKUPC3_Msk                   /*!< Clear Wakeup Pin Flag 3 */

+#define PWR_WKUPCR_WKUPC2_Pos          (1U)

+#define PWR_WKUPCR_WKUPC2_Msk          (0x1UL << PWR_WKUPCR_WKUPC2_Pos)        /*!< 0x00000002 */

+#define PWR_WKUPCR_WKUPC2              PWR_WKUPCR_WKUPC2_Msk                   /*!< Clear Wakeup Pin Flag 2 */

+#define PWR_WKUPCR_WKUPC1_Pos          (0U)

+#define PWR_WKUPCR_WKUPC1_Msk          (0x1UL << PWR_WKUPCR_WKUPC1_Pos)        /*!< 0x00000001 */

+#define PWR_WKUPCR_WKUPC1              PWR_WKUPCR_WKUPC1_Msk                   /*!< Clear Wakeup Pin Flag 1 */

+

+/********************  Bit definition for PWR_WKUPFR register  ****************/

+#define PWR_WKUPFR_WKUPF6_Pos          (5U)

+#define PWR_WKUPFR_WKUPF6_Msk          (0x1UL << PWR_WKUPFR_WKUPF6_Pos)        /*!< 0x00000020 */

+#define PWR_WKUPFR_WKUPF6              PWR_WKUPFR_WKUPF6_Msk                   /*!< Wakeup Pin Flag 6 */

+#define PWR_WKUPFR_WKUPF5_Pos          (4U)

+#define PWR_WKUPFR_WKUPF5_Msk          (0x1UL << PWR_WKUPFR_WKUPF5_Pos)        /*!< 0x00000010 */

+#define PWR_WKUPFR_WKUPF5              PWR_WKUPFR_WKUPF5_Msk                   /*!< Wakeup Pin Flag 5 */

+#define PWR_WKUPFR_WKUPF4_Pos          (3U)

+#define PWR_WKUPFR_WKUPF4_Msk          (0x1UL << PWR_WKUPFR_WKUPF4_Pos)        /*!< 0x00000008 */

+#define PWR_WKUPFR_WKUPF4              PWR_WKUPFR_WKUPF4_Msk                   /*!< Wakeup Pin Flag 4 */

+#define PWR_WKUPFR_WKUPF3_Pos          (2U)

+#define PWR_WKUPFR_WKUPF3_Msk          (0x1UL << PWR_WKUPFR_WKUPF3_Pos)        /*!< 0x00000004 */

+#define PWR_WKUPFR_WKUPF3              PWR_WKUPFR_WKUPF3_Msk                   /*!< Wakeup Pin Flag 3 */

+#define PWR_WKUPFR_WKUPF2_Pos          (1U)

+#define PWR_WKUPFR_WKUPF2_Msk          (0x1UL << PWR_WKUPFR_WKUPF2_Pos)        /*!< 0x00000002 */

+#define PWR_WKUPFR_WKUPF2              PWR_WKUPFR_WKUPF2_Msk                   /*!< Wakeup Pin Flag 2 */

+#define PWR_WKUPFR_WKUPF1_Pos          (0U)

+#define PWR_WKUPFR_WKUPF1_Msk          (0x1UL << PWR_WKUPFR_WKUPF1_Pos)        /*!< 0x00000001 */

+#define PWR_WKUPFR_WKUPF1              PWR_WKUPFR_WKUPF1_Msk                   /*!< Wakeup Pin Flag 1 */

+

+/******************  Bit definition for PWR_WKUPEPR register  *****************/

+#define PWR_WKUPEPR_WKUPPUPD6_Pos      (26U)

+#define PWR_WKUPEPR_WKUPPUPD6_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x0C000000 */

+#define PWR_WKUPEPR_WKUPPUPD6          PWR_WKUPEPR_WKUPPUPD6_Msk               /*!< Wakeup Pin pull configuration for WKUP6 */

+#define PWR_WKUPEPR_WKUPPUPD6_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x04000000 */

+#define PWR_WKUPEPR_WKUPPUPD6_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x08000000 */

+#define PWR_WKUPEPR_WKUPPUPD5_Pos      (24U)

+#define PWR_WKUPEPR_WKUPPUPD5_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x03000000 */

+#define PWR_WKUPEPR_WKUPPUPD5          PWR_WKUPEPR_WKUPPUPD5_Msk               /*!< Wakeup Pin pull configuration for WKUP5 */

+#define PWR_WKUPEPR_WKUPPUPD5_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x01000000 */

+#define PWR_WKUPEPR_WKUPPUPD5_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x02000000 */

+#define PWR_WKUPEPR_WKUPPUPD4_Pos      (22U)

+#define PWR_WKUPEPR_WKUPPUPD4_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00C00000 */

+#define PWR_WKUPEPR_WKUPPUPD4          PWR_WKUPEPR_WKUPPUPD4_Msk               /*!< Wakeup Pin pull configuration for WKUP4 */

+#define PWR_WKUPEPR_WKUPPUPD4_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00400000 */

+#define PWR_WKUPEPR_WKUPPUPD4_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00800000 */

+#define PWR_WKUPEPR_WKUPPUPD3_Pos      (20U)

+#define PWR_WKUPEPR_WKUPPUPD3_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00300000 */

+#define PWR_WKUPEPR_WKUPPUPD3          PWR_WKUPEPR_WKUPPUPD3_Msk               /*!< Wakeup Pin pull configuration for WKUP3 */

+#define PWR_WKUPEPR_WKUPPUPD3_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00100000 */

+#define PWR_WKUPEPR_WKUPPUPD3_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00200000 */

+#define PWR_WKUPEPR_WKUPPUPD2_Pos      (18U)

+#define PWR_WKUPEPR_WKUPPUPD2_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x000C0000 */

+#define PWR_WKUPEPR_WKUPPUPD2          PWR_WKUPEPR_WKUPPUPD2_Msk               /*!< Wakeup Pin pull configuration for WKUP2 */

+#define PWR_WKUPEPR_WKUPPUPD2_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00040000 */

+#define PWR_WKUPEPR_WKUPPUPD2_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00080000 */

+#define PWR_WKUPEPR_WKUPPUPD1_Pos      (16U)

+#define PWR_WKUPEPR_WKUPPUPD1_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00030000 */

+#define PWR_WKUPEPR_WKUPPUPD1          PWR_WKUPEPR_WKUPPUPD1_Msk               /*!< Wakeup Pin pull configuration for WKUP1 */

+#define PWR_WKUPEPR_WKUPPUPD1_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00010000 */

+#define PWR_WKUPEPR_WKUPPUPD1_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00020000 */

+#define PWR_WKUPEPR_WKUPP6_Pos         (13U)

+#define PWR_WKUPEPR_WKUPP6_Msk         (0x1UL << PWR_WKUPEPR_WKUPP6_Pos)       /*!< 0x00002000 */

+#define PWR_WKUPEPR_WKUPP6             PWR_WKUPEPR_WKUPP6_Msk                  /*!< Wakeup Pin Polarity for WKUP6 */

+#define PWR_WKUPEPR_WKUPP5_Pos         (12U)

+#define PWR_WKUPEPR_WKUPP5_Msk         (0x1UL << PWR_WKUPEPR_WKUPP5_Pos)       /*!< 0x00001000 */

+#define PWR_WKUPEPR_WKUPP5             PWR_WKUPEPR_WKUPP5_Msk                  /*!< Wakeup Pin Polarity for WKUP5 */

+#define PWR_WKUPEPR_WKUPP4_Pos         (11U)

+#define PWR_WKUPEPR_WKUPP4_Msk         (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)       /*!< 0x00000800 */

+#define PWR_WKUPEPR_WKUPP4             PWR_WKUPEPR_WKUPP4_Msk                  /*!< Wakeup Pin Polarity for WKUP4 */

+#define PWR_WKUPEPR_WKUPP3_Pos         (10U)

+#define PWR_WKUPEPR_WKUPP3_Msk         (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)       /*!< 0x00000400 */

+#define PWR_WKUPEPR_WKUPP3             PWR_WKUPEPR_WKUPP3_Msk                  /*!< Wakeup Pin Polarity for WKUP3 */

+#define PWR_WKUPEPR_WKUPP2_Pos         (9U)

+#define PWR_WKUPEPR_WKUPP2_Msk         (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)       /*!< 0x00000200 */

+#define PWR_WKUPEPR_WKUPP2             PWR_WKUPEPR_WKUPP2_Msk                  /*!< Wakeup Pin Polarity for WKUP2 */

+#define PWR_WKUPEPR_WKUPP1_Pos         (8U)

+#define PWR_WKUPEPR_WKUPP1_Msk         (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)       /*!< 0x00000100 */

+#define PWR_WKUPEPR_WKUPP1             PWR_WKUPEPR_WKUPP1_Msk                  /*!< Wakeup Pin Polarity for WKUP1 */

+#define PWR_WKUPEPR_WKUPEN6_Pos        (5U)

+#define PWR_WKUPEPR_WKUPEN6_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos)      /*!< 0x00000020 */

+#define PWR_WKUPEPR_WKUPEN6            PWR_WKUPEPR_WKUPEN6_Msk                 /*!< Enable Wakeup Pin WKUP6 */

+#define PWR_WKUPEPR_WKUPEN5_Pos        (4U)

+#define PWR_WKUPEPR_WKUPEN5_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos)      /*!< 0x00000010 */

+#define PWR_WKUPEPR_WKUPEN5            PWR_WKUPEPR_WKUPEN5_Msk                 /*!< Enable Wakeup Pin WKUP5 */

+#define PWR_WKUPEPR_WKUPEN4_Pos        (3U)

+#define PWR_WKUPEPR_WKUPEN4_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)      /*!< 0x00000008 */

+#define PWR_WKUPEPR_WKUPEN4            PWR_WKUPEPR_WKUPEN4_Msk                 /*!< Enable Wakeup Pin WKUP4 */

+#define PWR_WKUPEPR_WKUPEN3_Pos        (2U)

+#define PWR_WKUPEPR_WKUPEN3_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)      /*!< 0x00000004 */

+#define PWR_WKUPEPR_WKUPEN3            PWR_WKUPEPR_WKUPEN3_Msk                 /*!< Enable Wakeup Pin WKUP3 */

+#define PWR_WKUPEPR_WKUPEN2_Pos        (1U)

+#define PWR_WKUPEPR_WKUPEN2_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)      /*!< 0x00000002 */

+#define PWR_WKUPEPR_WKUPEN2            PWR_WKUPEPR_WKUPEN2_Msk                 /*!< Enable Wakeup Pin WKUP2 */

+#define PWR_WKUPEPR_WKUPEN1_Pos        (0U)

+#define PWR_WKUPEPR_WKUPEN1_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)      /*!< 0x00000001 */

+#define PWR_WKUPEPR_WKUPEN1            PWR_WKUPEPR_WKUPEN1_Msk                 /*!< Enable Wakeup Pin WKUP1 */

+#define PWR_WKUPEPR_WKUPEN_Pos         (0U)

+#define PWR_WKUPEPR_WKUPEN_Msk         (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos)      /*!< 0x0000003F */

+#define PWR_WKUPEPR_WKUPEN             PWR_WKUPEPR_WKUPEN_Msk                  /*!< Enable all Wakeup Pin */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Reset and Clock Control                            */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  RCC VERSION  ********************************/

+#define RCC_VER_X

+

+/********************  Bit definition for RCC_CR register  ********************/

+#define RCC_CR_HSION_Pos                       (0U)

+#define RCC_CR_HSION_Msk                       (0x1UL << RCC_CR_HSION_Pos)     /*!< 0x00000001 */

+#define RCC_CR_HSION                           RCC_CR_HSION_Msk                /*!< Internal High Speed clock enable */

+#define RCC_CR_HSIKERON_Pos                    (1U)

+#define RCC_CR_HSIKERON_Msk                    (0x1UL << RCC_CR_HSIKERON_Pos)  /*!< 0x00000002 */

+#define RCC_CR_HSIKERON                        RCC_CR_HSIKERON_Msk             /*!< Internal High Speed clock enable for some IPs Kernel */

+#define RCC_CR_HSIRDY_Pos                      (2U)

+#define RCC_CR_HSIRDY_Msk                      (0x1UL << RCC_CR_HSIRDY_Pos)    /*!< 0x00000004 */

+#define RCC_CR_HSIRDY                          RCC_CR_HSIRDY_Msk               /*!< Internal High Speed clock ready flag */

+#define RCC_CR_HSIDIV_Pos                      (3U)

+#define RCC_CR_HSIDIV_Msk                      (0x3UL << RCC_CR_HSIDIV_Pos)    /*!< 0x00000018 */

+#define RCC_CR_HSIDIV                          RCC_CR_HSIDIV_Msk               /*!< Internal High Speed clock divider selection */

+#define RCC_CR_HSIDIV_1                        (0x0UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000000 */

+#define RCC_CR_HSIDIV_2                        (0x1UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000008 */

+#define RCC_CR_HSIDIV_4                        (0x2UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000010 */

+#define RCC_CR_HSIDIV_8                        (0x3UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000018 */

+

+#define RCC_CR_HSIDIVF_Pos                     (5U)

+#define RCC_CR_HSIDIVF_Msk                     (0x1UL << RCC_CR_HSIDIVF_Pos)   /*!< 0x00000020 */

+#define RCC_CR_HSIDIVF                         RCC_CR_HSIDIVF_Msk              /*!< HSI Divider flag */

+#define RCC_CR_CSION_Pos                       (7U)

+#define RCC_CR_CSION_Msk                       (0x1UL << RCC_CR_CSION_Pos)     /*!< 0x00000080 */

+#define RCC_CR_CSION                           RCC_CR_CSION_Msk                /*!< The Internal RC 4MHz oscillator clock enable */

+#define RCC_CR_CSIRDY_Pos                      (8U)

+#define RCC_CR_CSIRDY_Msk                      (0x1UL << RCC_CR_CSIRDY_Pos)    /*!< 0x00000100 */

+#define RCC_CR_CSIRDY                          RCC_CR_CSIRDY_Msk               /*!< The Internal RC 4MHz oscillator clock ready */

+#define RCC_CR_CSIKERON_Pos                    (9U)

+#define RCC_CR_CSIKERON_Msk                    (0x1UL << RCC_CR_CSIKERON_Pos)  /*!< 0x00000200 */

+#define RCC_CR_CSIKERON                        RCC_CR_CSIKERON_Msk             /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */

+#define RCC_CR_HSI48ON_Pos                     (12U)

+#define RCC_CR_HSI48ON_Msk                     (0x1UL << RCC_CR_HSI48ON_Pos)   /*!< 0x00001000 */

+#define RCC_CR_HSI48ON                         RCC_CR_HSI48ON_Msk              /*!< HSI48 clock enable clock enable  */

+#define RCC_CR_HSI48RDY_Pos                    (13U)

+#define RCC_CR_HSI48RDY_Msk                    (0x1UL << RCC_CR_HSI48RDY_Pos)  /*!< 0x00002000 */

+#define RCC_CR_HSI48RDY                        RCC_CR_HSI48RDY_Msk             /*!< HSI48 clock ready */

+

+#define RCC_CR_D1CKRDY_Pos                     (14U)

+#define RCC_CR_D1CKRDY_Msk                     (0x1UL << RCC_CR_D1CKRDY_Pos)   /*!< 0x00004000 */

+#define RCC_CR_D1CKRDY                         RCC_CR_D1CKRDY_Msk              /*!< D1 domain clocks ready flag  */

+#define RCC_CR_D2CKRDY_Pos                     (15U)

+#define RCC_CR_D2CKRDY_Msk                     (0x1UL << RCC_CR_D2CKRDY_Pos)   /*!< 0x00008000 */

+#define RCC_CR_D2CKRDY                         RCC_CR_D2CKRDY_Msk              /*!< D2 domain clocks ready flag */

+

+#define RCC_CR_HSEON_Pos                       (16U)

+#define RCC_CR_HSEON_Msk                       (0x1UL << RCC_CR_HSEON_Pos)     /*!< 0x00010000 */

+#define RCC_CR_HSEON                           RCC_CR_HSEON_Msk                /*!< External High Speed clock enable */

+#define RCC_CR_HSERDY_Pos                      (17U)

+#define RCC_CR_HSERDY_Msk                      (0x1UL << RCC_CR_HSERDY_Pos)    /*!< 0x00020000 */

+#define RCC_CR_HSERDY                          RCC_CR_HSERDY_Msk               /*!< External High Speed clock ready */

+#define RCC_CR_HSEBYP_Pos                      (18U)

+#define RCC_CR_HSEBYP_Msk                      (0x1UL << RCC_CR_HSEBYP_Pos)    /*!< 0x00040000 */

+#define RCC_CR_HSEBYP                          RCC_CR_HSEBYP_Msk               /*!< External High Speed clock Bypass */

+#define RCC_CR_CSSHSEON_Pos                    (19U)

+#define RCC_CR_CSSHSEON_Msk                    (0x1UL << RCC_CR_CSSHSEON_Pos)  /*!< 0x00080000 */

+#define RCC_CR_CSSHSEON                        RCC_CR_CSSHSEON_Msk             /*!< HSE Clock security System enable */

+

+

+#define RCC_CR_PLL1ON_Pos                      (24U)

+#define RCC_CR_PLL1ON_Msk                      (0x1UL << RCC_CR_PLL1ON_Pos)    /*!< 0x01000000 */

+#define RCC_CR_PLL1ON                          RCC_CR_PLL1ON_Msk               /*!< System PLL1 clock enable */

+#define RCC_CR_PLL1RDY_Pos                     (25U)

+#define RCC_CR_PLL1RDY_Msk                     (0x1UL << RCC_CR_PLL1RDY_Pos)   /*!< 0x02000000 */

+#define RCC_CR_PLL1RDY                         RCC_CR_PLL1RDY_Msk              /*!< System PLL1 clock ready */

+#define RCC_CR_PLL2ON_Pos                      (26U)

+#define RCC_CR_PLL2ON_Msk                      (0x1UL << RCC_CR_PLL2ON_Pos)    /*!< 0x04000000 */

+#define RCC_CR_PLL2ON                          RCC_CR_PLL2ON_Msk               /*!< System PLL2 clock enable */

+#define RCC_CR_PLL2RDY_Pos                     (27U)

+#define RCC_CR_PLL2RDY_Msk                     (0x1UL << RCC_CR_PLL2RDY_Pos)   /*!< 0x08000000 */

+#define RCC_CR_PLL2RDY                         RCC_CR_PLL2RDY_Msk              /*!< System PLL2 clock ready */

+#define RCC_CR_PLL3ON_Pos                      (28U)

+#define RCC_CR_PLL3ON_Msk                      (0x1UL << RCC_CR_PLL3ON_Pos)    /*!< 0x10000000 */

+#define RCC_CR_PLL3ON                          RCC_CR_PLL3ON_Msk               /*!< System PLL3 clock enable */

+#define RCC_CR_PLL3RDY_Pos                     (29U)

+#define RCC_CR_PLL3RDY_Msk                     (0x1UL << RCC_CR_PLL3RDY_Pos)   /*!< 0x20000000 */

+#define RCC_CR_PLL3RDY                         RCC_CR_PLL3RDY_Msk              /*!< System PLL3 clock ready */

+

+/*Legacy */

+#define RCC_CR_PLLON_Pos                       (24U)

+#define RCC_CR_PLLON_Msk                       (0x1UL << RCC_CR_PLLON_Pos)     /*!< 0x01000000 */

+#define RCC_CR_PLLON                           RCC_CR_PLLON_Msk                /*!< System PLL clock enable */

+#define RCC_CR_PLLRDY_Pos                      (25U)

+#define RCC_CR_PLLRDY_Msk                      (0x1UL << RCC_CR_PLLRDY_Pos)    /*!< 0x02000000 */

+#define RCC_CR_PLLRDY                          RCC_CR_PLLRDY_Msk               /*!< System PLL clock ready */

+

+/********************  Bit definition for RCC_HSICFGR register  ***************/

+/*!< HSICAL configuration */

+#define RCC_HSICFGR_HSICAL_Pos                 (0U)

+#define RCC_HSICFGR_HSICAL_Msk                 (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */

+#define RCC_HSICFGR_HSICAL                     RCC_HSICFGR_HSICAL_Msk          /*!< HSICAL[11:0] bits */

+#define RCC_HSICFGR_HSICAL_0                   (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */

+#define RCC_HSICFGR_HSICAL_1                   (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */

+#define RCC_HSICFGR_HSICAL_2                   (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */

+#define RCC_HSICFGR_HSICAL_3                   (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */

+#define RCC_HSICFGR_HSICAL_4                   (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */

+#define RCC_HSICFGR_HSICAL_5                   (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */

+#define RCC_HSICFGR_HSICAL_6                   (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */

+#define RCC_HSICFGR_HSICAL_7                   (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */

+#define RCC_HSICFGR_HSICAL_8                   (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */

+#define RCC_HSICFGR_HSICAL_9                   (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */

+#define RCC_HSICFGR_HSICAL_10                  (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */

+#define RCC_HSICFGR_HSICAL_11                  (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */

+

+/*!< HSITRIM configuration */

+#define RCC_HSICFGR_HSITRIM_Pos                (24U)

+#define RCC_HSICFGR_HSITRIM_Msk                (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */

+#define RCC_HSICFGR_HSITRIM                    RCC_HSICFGR_HSITRIM_Msk         /*!< HSITRIM[6:0] bits */

+#define RCC_HSICFGR_HSITRIM_0                  (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */

+#define RCC_HSICFGR_HSITRIM_1                  (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */

+#define RCC_HSICFGR_HSITRIM_2                  (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */

+#define RCC_HSICFGR_HSITRIM_3                  (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */

+#define RCC_HSICFGR_HSITRIM_4                  (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */

+#define RCC_HSICFGR_HSITRIM_5                  (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */

+#define RCC_HSICFGR_HSITRIM_6                  (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */

+

+

+/********************  Bit definition for RCC_CRRCR register  *****************/

+

+/*!< HSI48CAL configuration */

+#define RCC_CRRCR_HSI48CAL_Pos                 (0U)

+#define RCC_CRRCR_HSI48CAL_Msk                 (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */

+#define RCC_CRRCR_HSI48CAL                     RCC_CRRCR_HSI48CAL_Msk          /*!< HSI48CAL[9:0] bits */

+#define RCC_CRRCR_HSI48CAL_0                   (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */

+#define RCC_CRRCR_HSI48CAL_1                   (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */

+#define RCC_CRRCR_HSI48CAL_2                   (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */

+#define RCC_CRRCR_HSI48CAL_3                   (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */

+#define RCC_CRRCR_HSI48CAL_4                   (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */

+#define RCC_CRRCR_HSI48CAL_5                   (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */

+#define RCC_CRRCR_HSI48CAL_6                   (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */

+#define RCC_CRRCR_HSI48CAL_7                   (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */

+#define RCC_CRRCR_HSI48CAL_8                   (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */

+#define RCC_CRRCR_HSI48CAL_9                   (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */

+

+

+/********************  Bit definition for RCC_CSICFGR register  *****************/

+/*!< CSICAL configuration */

+#define RCC_CSICFGR_CSICAL_Pos                 (0U)

+#define RCC_CSICFGR_CSICAL_Msk                 (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */

+#define RCC_CSICFGR_CSICAL                     RCC_CSICFGR_CSICAL_Msk          /*!< CSICAL[7:0] bits */

+#define RCC_CSICFGR_CSICAL_0                   (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */

+#define RCC_CSICFGR_CSICAL_1                   (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */

+#define RCC_CSICFGR_CSICAL_2                   (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */

+#define RCC_CSICFGR_CSICAL_3                   (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */

+#define RCC_CSICFGR_CSICAL_4                   (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */

+#define RCC_CSICFGR_CSICAL_5                   (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */

+#define RCC_CSICFGR_CSICAL_6                   (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */

+#define RCC_CSICFGR_CSICAL_7                   (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */

+

+/*!< CSITRIM configuration */

+#define RCC_CSICFGR_CSITRIM_Pos                (24U)

+#define RCC_CSICFGR_CSITRIM_Msk                (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */

+#define RCC_CSICFGR_CSITRIM                    RCC_CSICFGR_CSITRIM_Msk         /*!< CSITRIM[5:0] bits */

+#define RCC_CSICFGR_CSITRIM_0                  (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */

+#define RCC_CSICFGR_CSITRIM_1                  (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */

+#define RCC_CSICFGR_CSITRIM_2                  (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */

+#define RCC_CSICFGR_CSITRIM_3                  (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */

+#define RCC_CSICFGR_CSITRIM_4                  (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */

+#define RCC_CSICFGR_CSITRIM_5                  (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */

+

+/********************  Bit definition for RCC_CFGR register  ******************/

+/*!< SW configuration */

+#define RCC_CFGR_SW_Pos                        (0U)

+#define RCC_CFGR_SW_Msk                        (0x7UL << RCC_CFGR_SW_Pos)           /*!< 0x00000007 */

+#define RCC_CFGR_SW                            RCC_CFGR_SW_Msk                     /*!< SW[2:0] bits (System clock Switch) */

+#define RCC_CFGR_SW_0                          (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */

+#define RCC_CFGR_SW_1                          (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */

+#define RCC_CFGR_SW_2                          (0x4UL << RCC_CFGR_SW_Pos)           /*!< 0x00000004 */

+

+#define RCC_CFGR_SW_HSI                        (0x00000000UL)                       /*!< HSI selection as system clock */

+#define RCC_CFGR_SW_CSI                        (0x00000001UL)                       /*!< CSI selection as system clock */

+#define RCC_CFGR_SW_HSE                        (0x00000002UL)                       /*!< HSE selection as system clock */

+#define RCC_CFGR_SW_PLL1                       (0x00000003UL)                       /*!< PLL1 selection as system clock */

+

+/*!< SWS configuration */

+#define RCC_CFGR_SWS_Pos                       (3U)

+#define RCC_CFGR_SWS_Msk                       (0x7UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000038 */

+#define RCC_CFGR_SWS                           RCC_CFGR_SWS_Msk                    /*!< SWS[2:0] bits (System Clock Switch Status) */

+#define RCC_CFGR_SWS_0                         (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */

+#define RCC_CFGR_SWS_1                         (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000010 */

+#define RCC_CFGR_SWS_2                         (0x4UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000020 */

+

+#define RCC_CFGR_SWS_HSI                       (0x00000000UL)                       /*!< HSI used as system clock */

+#define RCC_CFGR_SWS_CSI                       (0x00000008UL)                       /*!< CSI used as system clock */

+#define RCC_CFGR_SWS_HSE                       (0x00000010UL)                       /*!< HSE used as system clock */

+#define RCC_CFGR_SWS_PLL1                      (0x00000018UL)                       /*!< PLL1 used as system clock */

+

+#define RCC_CFGR_STOPWUCK_Pos                  (6U)

+#define RCC_CFGR_STOPWUCK_Msk                  (0x1UL << RCC_CFGR_STOPWUCK_Pos)     /*!< 0x00000040 */

+#define RCC_CFGR_STOPWUCK                      RCC_CFGR_STOPWUCK_Msk                /*!< Wake Up from stop and CSS backup clock selection */

+

+#define RCC_CFGR_STOPKERWUCK_Pos               (7U)

+#define RCC_CFGR_STOPKERWUCK_Msk               (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)  /*!< 0x00000080 */

+#define RCC_CFGR_STOPKERWUCK                   RCC_CFGR_STOPKERWUCK_Msk             /*!< Kernel Clock Selection after a Wake Up from STOP */

+

+/*!< RTCPRE configuration */

+#define RCC_CFGR_RTCPRE_Pos                    (8U)

+#define RCC_CFGR_RTCPRE_Msk                    (0x3FUL << RCC_CFGR_RTCPRE_Pos)

+#define RCC_CFGR_RTCPRE                        RCC_CFGR_RTCPRE_Msk                  /*!< 0x00003F00 */

+#define RCC_CFGR_RTCPRE_0                      (0x1UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000100 */

+#define RCC_CFGR_RTCPRE_1                      (0x2UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000200 */

+#define RCC_CFGR_RTCPRE_2                      (0x4UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000400 */

+#define RCC_CFGR_RTCPRE_3                      (0x8UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000800 */

+#define RCC_CFGR_RTCPRE_4                      (0x10UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00001000 */

+#define RCC_CFGR_RTCPRE_5                      (0x20UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00002000 */

+

+/*!< HRTIMSEL configuration */

+#define RCC_CFGR_HRTIMSEL_Pos                  (14U)

+#define RCC_CFGR_HRTIMSEL_Msk                  (0x1UL << RCC_CFGR_HRTIMSEL_Pos)

+#define RCC_CFGR_HRTIMSEL                      RCC_CFGR_HRTIMSEL_Msk                /*!< 0x00004000 */

+

+/*!< TIMPRE configuration */

+#define RCC_CFGR_TIMPRE_Pos                    (15U)

+#define RCC_CFGR_TIMPRE_Msk                    (0x1UL << RCC_CFGR_TIMPRE_Pos)

+#define RCC_CFGR_TIMPRE                        RCC_CFGR_TIMPRE_Msk                  /*!< 0x00008000 */

+

+/*!< MCO1 configuration */

+#define RCC_CFGR_MCO1_Pos                      (22U)

+#define RCC_CFGR_MCO1_Msk                      (0x7UL << RCC_CFGR_MCO1_Pos)

+#define RCC_CFGR_MCO1                          RCC_CFGR_MCO1_Msk                       /*!< 0x01C00000 */

+#define RCC_CFGR_MCO1_0                        (0x1UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00400000 */

+#define RCC_CFGR_MCO1_1                        (0x2UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00800000 */

+#define RCC_CFGR_MCO1_2                        (0x4UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x01000000 */

+

+#define RCC_CFGR_MCO1PRE_Pos                   (18U)

+#define RCC_CFGR_MCO1PRE_Msk                   (0xFUL << RCC_CFGR_MCO1PRE_Pos)

+#define RCC_CFGR_MCO1PRE                       RCC_CFGR_MCO1PRE_Msk                    /*!< 0x003C0000 */

+#define RCC_CFGR_MCO1PRE_0                     (0x1UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00040000 */

+#define RCC_CFGR_MCO1PRE_1                     (0x2UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00080000 */

+#define RCC_CFGR_MCO1PRE_2                     (0x4UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00100000 */

+#define RCC_CFGR_MCO1PRE_3                     (0x8UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00200000 */

+

+#define RCC_CFGR_MCO2PRE_Pos                   (25U)

+#define RCC_CFGR_MCO2PRE_Msk                   (0xFUL << RCC_CFGR_MCO2PRE_Pos)

+#define RCC_CFGR_MCO2PRE                       RCC_CFGR_MCO2PRE_Msk                    /*!< 0x1E000000 */

+#define RCC_CFGR_MCO2PRE_0                     (0x1UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x02000000 */

+#define RCC_CFGR_MCO2PRE_1                     (0x2UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x04000000 */

+#define RCC_CFGR_MCO2PRE_2                     (0x4UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x08000000 */

+#define RCC_CFGR_MCO2PRE_3                     (0x8UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x10000000 */

+

+#define RCC_CFGR_MCO2_Pos                      (29U)

+#define RCC_CFGR_MCO2_Msk                      (0x7UL << RCC_CFGR_MCO2_Pos)

+#define RCC_CFGR_MCO2                          RCC_CFGR_MCO2_Msk                       /*!< 0xE0000000 */

+#define RCC_CFGR_MCO2_0                        (0x1UL << RCC_CFGR_MCO2_Pos)             /*!< 0x20000000 */

+#define RCC_CFGR_MCO2_1                        (0x2UL << RCC_CFGR_MCO2_Pos)             /*!< 0x40000000 */

+#define RCC_CFGR_MCO2_2                        (0x4UL << RCC_CFGR_MCO2_Pos)             /*!< 0x80000000 */

+

+/********************  Bit definition for RCC_D1CFGR register  ******************/

+/*!< D1HPRE configuration */

+#define RCC_D1CFGR_HPRE_Pos                    (0U)

+#define RCC_D1CFGR_HPRE_Msk                    (0xFUL << RCC_D1CFGR_HPRE_Pos)  /*!< 0x0000000F */

+#define RCC_D1CFGR_HPRE                        RCC_D1CFGR_HPRE_Msk             /*!< HPRE[3:0] bits (AHB3 prescaler) */

+#define RCC_D1CFGR_HPRE_0                      (0x1UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000001 */

+#define RCC_D1CFGR_HPRE_1                      (0x2UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000002 */

+#define RCC_D1CFGR_HPRE_2                      (0x4UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000004 */

+#define RCC_D1CFGR_HPRE_3                      (0x8UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000008 */

+

+

+#define RCC_D1CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)          /*!< AHB3 Clock not divided */

+#define RCC_D1CFGR_HPRE_DIV2_Pos               (3U)

+#define RCC_D1CFGR_HPRE_DIV2_Msk               (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */

+#define RCC_D1CFGR_HPRE_DIV2                   RCC_D1CFGR_HPRE_DIV2_Msk        /*!< AHB3 Clock divided by 2 */

+#define RCC_D1CFGR_HPRE_DIV4_Pos               (0U)

+#define RCC_D1CFGR_HPRE_DIV4_Msk               (0x9UL << RCC_D1CFGR_HPRE_DIV4_Pos) /*!< 0x00000009 */

+#define RCC_D1CFGR_HPRE_DIV4                   RCC_D1CFGR_HPRE_DIV4_Msk        /*!< AHB3 Clock divided by 4 */

+#define RCC_D1CFGR_HPRE_DIV8_Pos               (1U)

+#define RCC_D1CFGR_HPRE_DIV8_Msk               (0x5UL << RCC_D1CFGR_HPRE_DIV8_Pos) /*!< 0x0000000A */

+#define RCC_D1CFGR_HPRE_DIV8                   RCC_D1CFGR_HPRE_DIV8_Msk        /*!< AHB3 Clock divided by 8 */

+#define RCC_D1CFGR_HPRE_DIV16_Pos              (0U)

+#define RCC_D1CFGR_HPRE_DIV16_Msk              (0xBUL << RCC_D1CFGR_HPRE_DIV16_Pos) /*!< 0x0000000B */

+#define RCC_D1CFGR_HPRE_DIV16                  RCC_D1CFGR_HPRE_DIV16_Msk       /*!< AHB3 Clock divided by 16 */

+#define RCC_D1CFGR_HPRE_DIV64_Pos              (2U)

+#define RCC_D1CFGR_HPRE_DIV64_Msk              (0x3UL << RCC_D1CFGR_HPRE_DIV64_Pos) /*!< 0x0000000C */

+#define RCC_D1CFGR_HPRE_DIV64                  RCC_D1CFGR_HPRE_DIV64_Msk       /*!< AHB3 Clock divided by 64 */

+#define RCC_D1CFGR_HPRE_DIV128_Pos             (0U)

+#define RCC_D1CFGR_HPRE_DIV128_Msk             (0xDUL << RCC_D1CFGR_HPRE_DIV128_Pos) /*!< 0x0000000D */

+#define RCC_D1CFGR_HPRE_DIV128                 RCC_D1CFGR_HPRE_DIV128_Msk      /*!< AHB3 Clock divided by 128 */

+#define RCC_D1CFGR_HPRE_DIV256_Pos             (1U)

+#define RCC_D1CFGR_HPRE_DIV256_Msk             (0x7UL << RCC_D1CFGR_HPRE_DIV256_Pos) /*!< 0x0000000E */

+#define RCC_D1CFGR_HPRE_DIV256                 RCC_D1CFGR_HPRE_DIV256_Msk      /*!< AHB3 Clock divided by 256 */

+#define RCC_D1CFGR_HPRE_DIV512_Pos             (0U)

+#define RCC_D1CFGR_HPRE_DIV512_Msk             (0xFUL << RCC_D1CFGR_HPRE_DIV512_Pos) /*!< 0x0000000F */

+#define RCC_D1CFGR_HPRE_DIV512                 RCC_D1CFGR_HPRE_DIV512_Msk      /*!< AHB3 Clock divided by 512 */

+

+/*!< D1PPRE configuration */

+#define RCC_D1CFGR_D1PPRE_Pos                  (4U)

+#define RCC_D1CFGR_D1PPRE_Msk                  (0x7UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000070 */

+#define RCC_D1CFGR_D1PPRE                      RCC_D1CFGR_D1PPRE_Msk           /*!< D1PRE[2:0] bits (APB3 prescaler) */

+#define RCC_D1CFGR_D1PPRE_0                    (0x1UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000010 */

+#define RCC_D1CFGR_D1PPRE_1                    (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */

+#define RCC_D1CFGR_D1PPRE_2                    (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */

+

+#define RCC_D1CFGR_D1PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB3 clock not divided */

+#define RCC_D1CFGR_D1PPRE_DIV2_Pos             (6U)

+#define RCC_D1CFGR_D1PPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_D1CFGR_D1PPRE_DIV2                 RCC_D1CFGR_D1PPRE_DIV2_Msk      /*!< APB3 clock divided by 2 */

+#define RCC_D1CFGR_D1PPRE_DIV4_Pos             (4U)

+#define RCC_D1CFGR_D1PPRE_DIV4_Msk             (0x5UL << RCC_D1CFGR_D1PPRE_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_D1CFGR_D1PPRE_DIV4                 RCC_D1CFGR_D1PPRE_DIV4_Msk      /*!< APB3 clock divided by 4 */

+#define RCC_D1CFGR_D1PPRE_DIV8_Pos             (5U)

+#define RCC_D1CFGR_D1PPRE_DIV8_Msk             (0x3UL << RCC_D1CFGR_D1PPRE_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_D1CFGR_D1PPRE_DIV8                 RCC_D1CFGR_D1PPRE_DIV8_Msk      /*!< APB3 clock divided by 8 */

+#define RCC_D1CFGR_D1PPRE_DIV16_Pos            (4U)

+#define RCC_D1CFGR_D1PPRE_DIV16_Msk            (0x7UL << RCC_D1CFGR_D1PPRE_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_D1CFGR_D1PPRE_DIV16                RCC_D1CFGR_D1PPRE_DIV16_Msk     /*!< APB3 clock divided by 16 */

+

+#define RCC_D1CFGR_D1CPRE_Pos                  (8U)

+#define RCC_D1CFGR_D1CPRE_Msk                  (0xFUL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000F00 */

+#define RCC_D1CFGR_D1CPRE                      RCC_D1CFGR_D1CPRE_Msk           /*!< D1CPRE[2:0] bits (Domain 1 Core prescaler) */

+#define RCC_D1CFGR_D1CPRE_0                    (0x1UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000100 */

+#define RCC_D1CFGR_D1CPRE_1                    (0x2UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000200 */

+#define RCC_D1CFGR_D1CPRE_2                    (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */

+#define RCC_D1CFGR_D1CPRE_3                    (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */

+

+#define RCC_D1CFGR_D1CPRE_DIV1                 ((uint32_t)0x00000000)          /*!< Domain 1 Core clock not divided */

+#define RCC_D1CFGR_D1CPRE_DIV2_Pos             (11U)

+#define RCC_D1CFGR_D1CPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */

+#define RCC_D1CFGR_D1CPRE_DIV2                 RCC_D1CFGR_D1CPRE_DIV2_Msk      /*!< Domain 1 Core clock divided by 2 */

+#define RCC_D1CFGR_D1CPRE_DIV4_Pos             (8U)

+#define RCC_D1CFGR_D1CPRE_DIV4_Msk             (0x9UL << RCC_D1CFGR_D1CPRE_DIV4_Pos) /*!< 0x00000900 */

+#define RCC_D1CFGR_D1CPRE_DIV4                 RCC_D1CFGR_D1CPRE_DIV4_Msk      /*!< Domain 1 Core clock divided by 4 */

+#define RCC_D1CFGR_D1CPRE_DIV8_Pos             (9U)

+#define RCC_D1CFGR_D1CPRE_DIV8_Msk             (0x5UL << RCC_D1CFGR_D1CPRE_DIV8_Pos) /*!< 0x00000A00 */

+#define RCC_D1CFGR_D1CPRE_DIV8                 RCC_D1CFGR_D1CPRE_DIV8_Msk      /*!< Domain 1 Core clock divided by 8 */

+#define RCC_D1CFGR_D1CPRE_DIV16_Pos            (8U)

+#define RCC_D1CFGR_D1CPRE_DIV16_Msk            (0xBUL << RCC_D1CFGR_D1CPRE_DIV16_Pos) /*!< 0x00000B00 */

+#define RCC_D1CFGR_D1CPRE_DIV16                RCC_D1CFGR_D1CPRE_DIV16_Msk     /*!< Domain 1 Core clock divided by 16 */

+#define RCC_D1CFGR_D1CPRE_DIV64_Pos            (10U)

+#define RCC_D1CFGR_D1CPRE_DIV64_Msk            (0x3UL << RCC_D1CFGR_D1CPRE_DIV64_Pos) /*!< 0x00000C00 */

+#define RCC_D1CFGR_D1CPRE_DIV64                RCC_D1CFGR_D1CPRE_DIV64_Msk     /*!< Domain 1 Core clock divided by 64 */

+#define RCC_D1CFGR_D1CPRE_DIV128_Pos           (8U)

+#define RCC_D1CFGR_D1CPRE_DIV128_Msk           (0xDUL << RCC_D1CFGR_D1CPRE_DIV128_Pos) /*!< 0x00000D00 */

+#define RCC_D1CFGR_D1CPRE_DIV128               RCC_D1CFGR_D1CPRE_DIV128_Msk    /*!< Domain 1 Core clock divided by 128 */

+#define RCC_D1CFGR_D1CPRE_DIV256_Pos           (9U)

+#define RCC_D1CFGR_D1CPRE_DIV256_Msk           (0x7UL << RCC_D1CFGR_D1CPRE_DIV256_Pos) /*!< 0x00000E00 */

+#define RCC_D1CFGR_D1CPRE_DIV256               RCC_D1CFGR_D1CPRE_DIV256_Msk    /*!< Domain 1 Core clock divided by 256 */

+#define RCC_D1CFGR_D1CPRE_DIV512_Pos           (8U)

+#define RCC_D1CFGR_D1CPRE_DIV512_Msk           (0xFUL << RCC_D1CFGR_D1CPRE_DIV512_Pos) /*!< 0x00000F00 */

+#define RCC_D1CFGR_D1CPRE_DIV512               RCC_D1CFGR_D1CPRE_DIV512_Msk    /*!< Domain 1 Core clock divided by 512 */

+

+/********************  Bit definition for RCC_D2CFGR register  ******************/

+/*!< D2PPRE1 configuration */

+#define RCC_D2CFGR_D2PPRE1_Pos                 (4U)

+#define RCC_D2CFGR_D2PPRE1_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000070 */

+#define RCC_D2CFGR_D2PPRE1                     RCC_D2CFGR_D2PPRE1_Msk          /*!< D1PPRE1[2:0] bits (APB1 prescaler) */

+#define RCC_D2CFGR_D2PPRE1_0                   (0x1UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000010 */

+#define RCC_D2CFGR_D2PPRE1_1                   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */

+#define RCC_D2CFGR_D2PPRE1_2                   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */

+

+#define RCC_D2CFGR_D2PPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */

+#define RCC_D2CFGR_D2PPRE1_DIV2_Pos            (6U)

+#define RCC_D2CFGR_D2PPRE1_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_D2CFGR_D2PPRE1_DIV2                RCC_D2CFGR_D2PPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */

+#define RCC_D2CFGR_D2PPRE1_DIV4_Pos            (4U)

+#define RCC_D2CFGR_D2PPRE1_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE1_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_D2CFGR_D2PPRE1_DIV4                RCC_D2CFGR_D2PPRE1_DIV4_Msk     /*!< APB1 clock divided by 4 */

+#define RCC_D2CFGR_D2PPRE1_DIV8_Pos            (5U)

+#define RCC_D2CFGR_D2PPRE1_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE1_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_D2CFGR_D2PPRE1_DIV8                RCC_D2CFGR_D2PPRE1_DIV8_Msk     /*!< APB1 clock divided by 8 */

+#define RCC_D2CFGR_D2PPRE1_DIV16_Pos           (4U)

+#define RCC_D2CFGR_D2PPRE1_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE1_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_D2CFGR_D2PPRE1_DIV16               RCC_D2CFGR_D2PPRE1_DIV16_Msk    /*!< APB1 clock divided by 16 */

+

+/*!< D2PPRE2 configuration */

+#define RCC_D2CFGR_D2PPRE2_Pos                 (8U)

+#define RCC_D2CFGR_D2PPRE2_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000700 */

+#define RCC_D2CFGR_D2PPRE2                     RCC_D2CFGR_D2PPRE2_Msk          /*!< D2PPRE2[2:0] bits (APB2 prescaler) */

+#define RCC_D2CFGR_D2PPRE2_0                   (0x1UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000100 */

+#define RCC_D2CFGR_D2PPRE2_1                   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */

+#define RCC_D2CFGR_D2PPRE2_2                   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */

+

+#define RCC_D2CFGR_D2PPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */

+#define RCC_D2CFGR_D2PPRE2_DIV2_Pos            (10U)

+#define RCC_D2CFGR_D2PPRE2_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */

+#define RCC_D2CFGR_D2PPRE2_DIV2                RCC_D2CFGR_D2PPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */

+#define RCC_D2CFGR_D2PPRE2_DIV4_Pos            (8U)

+#define RCC_D2CFGR_D2PPRE2_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE2_DIV4_Pos) /*!< 0x00000500 */

+#define RCC_D2CFGR_D2PPRE2_DIV4                RCC_D2CFGR_D2PPRE2_DIV4_Msk     /*!< APB2 clock divided by 4 */

+#define RCC_D2CFGR_D2PPRE2_DIV8_Pos            (9U)

+#define RCC_D2CFGR_D2PPRE2_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE2_DIV8_Pos) /*!< 0x00000600 */

+#define RCC_D2CFGR_D2PPRE2_DIV8                RCC_D2CFGR_D2PPRE2_DIV8_Msk     /*!< APB2 clock divided by 8 */

+#define RCC_D2CFGR_D2PPRE2_DIV16_Pos           (8U)

+#define RCC_D2CFGR_D2PPRE2_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE2_DIV16_Pos) /*!< 0x00000700 */

+#define RCC_D2CFGR_D2PPRE2_DIV16               RCC_D2CFGR_D2PPRE2_DIV16_Msk    /*!< APB2 clock divided by 16 */

+

+/********************  Bit definition for RCC_D3CFGR register  ******************/

+/*!< D3PPRE configuration */

+#define RCC_D3CFGR_D3PPRE_Pos                  (4U)

+#define RCC_D3CFGR_D3PPRE_Msk                  (0x7UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000070 */

+#define RCC_D3CFGR_D3PPRE                      RCC_D3CFGR_D3PPRE_Msk           /*!< D3PPRE1[2:0] bits (APB4 prescaler) */

+#define RCC_D3CFGR_D3PPRE_0                    (0x1UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000010 */

+#define RCC_D3CFGR_D3PPRE_1                    (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */

+#define RCC_D3CFGR_D3PPRE_2                    (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */

+

+#define RCC_D3CFGR_D3PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */

+#define RCC_D3CFGR_D3PPRE_DIV2_Pos             (6U)

+#define RCC_D3CFGR_D3PPRE_DIV2_Msk             (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_D3CFGR_D3PPRE_DIV2                 RCC_D3CFGR_D3PPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */

+#define RCC_D3CFGR_D3PPRE_DIV4_Pos             (4U)

+#define RCC_D3CFGR_D3PPRE_DIV4_Msk             (0x5UL << RCC_D3CFGR_D3PPRE_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_D3CFGR_D3PPRE_DIV4                 RCC_D3CFGR_D3PPRE_DIV4_Msk      /*!< APB4 clock divided by 4 */

+#define RCC_D3CFGR_D3PPRE_DIV8_Pos             (5U)

+#define RCC_D3CFGR_D3PPRE_DIV8_Msk             (0x3UL << RCC_D3CFGR_D3PPRE_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_D3CFGR_D3PPRE_DIV8                 RCC_D3CFGR_D3PPRE_DIV8_Msk      /*!< APB4 clock divided by 8 */

+#define RCC_D3CFGR_D3PPRE_DIV16_Pos            (4U)

+#define RCC_D3CFGR_D3PPRE_DIV16_Msk            (0x7UL << RCC_D3CFGR_D3PPRE_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_D3CFGR_D3PPRE_DIV16                RCC_D3CFGR_D3PPRE_DIV16_Msk     /*!< APB4 clock divided by 16 */

+

+/********************  Bit definition for RCC_PLLCKSELR register  *************/

+

+#define RCC_PLLCKSELR_PLLSRC_Pos               (0U)

+#define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */

+#define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk

+

+#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)

+#define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */

+#define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_HSE_Pos           (1U)

+#define RCC_PLLCKSELR_PLLSRC_HSE_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */

+#define RCC_PLLCKSELR_PLLSRC_HSE               RCC_PLLCKSELR_PLLSRC_HSE_Msk    /*!< HSE source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_NONE_Pos          (0U)

+#define RCC_PLLCKSELR_PLLSRC_NONE_Msk          (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */

+#define RCC_PLLCKSELR_PLLSRC_NONE              RCC_PLLCKSELR_PLLSRC_NONE_Msk   /*!< No source clock selected  */

+

+#define RCC_PLLCKSELR_DIVM1_Pos                (4U)

+#define RCC_PLLCKSELR_DIVM1_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */

+#define RCC_PLLCKSELR_DIVM1                    RCC_PLLCKSELR_DIVM1_Msk

+#define RCC_PLLCKSELR_DIVM1_0                  (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */

+#define RCC_PLLCKSELR_DIVM1_1                  (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */

+#define RCC_PLLCKSELR_DIVM1_2                  (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */

+#define RCC_PLLCKSELR_DIVM1_3                  (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */

+#define RCC_PLLCKSELR_DIVM1_4                  (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */

+#define RCC_PLLCKSELR_DIVM1_5                  (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */

+

+#define RCC_PLLCKSELR_DIVM2_Pos                (12U)

+#define RCC_PLLCKSELR_DIVM2_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */

+#define RCC_PLLCKSELR_DIVM2                    RCC_PLLCKSELR_DIVM2_Msk

+#define RCC_PLLCKSELR_DIVM2_0                  (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */

+#define RCC_PLLCKSELR_DIVM2_1                  (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */

+#define RCC_PLLCKSELR_DIVM2_2                  (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */

+#define RCC_PLLCKSELR_DIVM2_3                  (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */

+#define RCC_PLLCKSELR_DIVM2_4                  (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */

+#define RCC_PLLCKSELR_DIVM2_5                  (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */

+

+#define RCC_PLLCKSELR_DIVM3_Pos                (20U)

+#define RCC_PLLCKSELR_DIVM3_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */

+#define RCC_PLLCKSELR_DIVM3                    RCC_PLLCKSELR_DIVM3_Msk

+#define RCC_PLLCKSELR_DIVM3_0                  (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */

+#define RCC_PLLCKSELR_DIVM3_1                  (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */

+#define RCC_PLLCKSELR_DIVM3_2                  (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */

+#define RCC_PLLCKSELR_DIVM3_3                  (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */

+#define RCC_PLLCKSELR_DIVM3_4                  (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */

+#define RCC_PLLCKSELR_DIVM3_5                  (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */

+

+/********************  Bit definition for RCC_PLLCFGR register  ***************/

+

+#define RCC_PLLCFGR_PLL1FRACEN_Pos             (0U)

+#define RCC_PLLCFGR_PLL1FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */

+#define RCC_PLLCFGR_PLL1FRACEN                 RCC_PLLCFGR_PLL1FRACEN_Msk

+#define RCC_PLLCFGR_PLL1VCOSEL_Pos             (1U)

+#define RCC_PLLCFGR_PLL1VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */

+#define RCC_PLLCFGR_PLL1VCOSEL                 RCC_PLLCFGR_PLL1VCOSEL_Msk

+#define RCC_PLLCFGR_PLL1RGE_Pos                (2U)

+#define RCC_PLLCFGR_PLL1RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */

+#define RCC_PLLCFGR_PLL1RGE                    RCC_PLLCFGR_PLL1RGE_Msk

+#define RCC_PLLCFGR_PLL1RGE_0                  (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL1RGE_1                  (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */

+#define RCC_PLLCFGR_PLL1RGE_2                  (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */

+#define RCC_PLLCFGR_PLL1RGE_3                  (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */

+

+#define RCC_PLLCFGR_PLL2FRACEN_Pos             (4U)

+#define RCC_PLLCFGR_PLL2FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */

+#define RCC_PLLCFGR_PLL2FRACEN                 RCC_PLLCFGR_PLL2FRACEN_Msk

+#define RCC_PLLCFGR_PLL2VCOSEL_Pos             (5U)

+#define RCC_PLLCFGR_PLL2VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */

+#define RCC_PLLCFGR_PLL2VCOSEL                 RCC_PLLCFGR_PLL2VCOSEL_Msk

+#define RCC_PLLCFGR_PLL2RGE_Pos                (6U)

+#define RCC_PLLCFGR_PLL2RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */

+#define RCC_PLLCFGR_PLL2RGE                    RCC_PLLCFGR_PLL2RGE_Msk

+#define RCC_PLLCFGR_PLL2RGE_0                  (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL2RGE_1                  (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */

+#define RCC_PLLCFGR_PLL2RGE_2                  (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */

+#define RCC_PLLCFGR_PLL2RGE_3                  (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */

+

+#define RCC_PLLCFGR_PLL3FRACEN_Pos             (8U)

+#define RCC_PLLCFGR_PLL3FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */

+#define RCC_PLLCFGR_PLL3FRACEN                 RCC_PLLCFGR_PLL3FRACEN_Msk

+#define RCC_PLLCFGR_PLL3VCOSEL_Pos             (9U)

+#define RCC_PLLCFGR_PLL3VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */

+#define RCC_PLLCFGR_PLL3VCOSEL                 RCC_PLLCFGR_PLL3VCOSEL_Msk

+#define RCC_PLLCFGR_PLL3RGE_Pos                (10U)

+#define RCC_PLLCFGR_PLL3RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */

+#define RCC_PLLCFGR_PLL3RGE                    RCC_PLLCFGR_PLL3RGE_Msk

+#define RCC_PLLCFGR_PLL3RGE_0                  (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL3RGE_1                  (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */

+#define RCC_PLLCFGR_PLL3RGE_2                  (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */

+#define RCC_PLLCFGR_PLL3RGE_3                  (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */

+

+#define RCC_PLLCFGR_DIVP1EN_Pos                (16U)

+#define RCC_PLLCFGR_DIVP1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */

+#define RCC_PLLCFGR_DIVP1EN                    RCC_PLLCFGR_DIVP1EN_Msk

+#define RCC_PLLCFGR_DIVQ1EN_Pos                (17U)

+#define RCC_PLLCFGR_DIVQ1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */

+#define RCC_PLLCFGR_DIVQ1EN                    RCC_PLLCFGR_DIVQ1EN_Msk

+#define RCC_PLLCFGR_DIVR1EN_Pos                (18U)

+#define RCC_PLLCFGR_DIVR1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */

+#define RCC_PLLCFGR_DIVR1EN                    RCC_PLLCFGR_DIVR1EN_Msk

+

+#define RCC_PLLCFGR_DIVP2EN_Pos                (19U)

+#define RCC_PLLCFGR_DIVP2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */

+#define RCC_PLLCFGR_DIVP2EN                    RCC_PLLCFGR_DIVP2EN_Msk

+#define RCC_PLLCFGR_DIVQ2EN_Pos                (20U)

+#define RCC_PLLCFGR_DIVQ2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */

+#define RCC_PLLCFGR_DIVQ2EN                    RCC_PLLCFGR_DIVQ2EN_Msk

+#define RCC_PLLCFGR_DIVR2EN_Pos                (21U)

+#define RCC_PLLCFGR_DIVR2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */

+#define RCC_PLLCFGR_DIVR2EN                    RCC_PLLCFGR_DIVR2EN_Msk

+

+#define RCC_PLLCFGR_DIVP3EN_Pos                (22U)

+#define RCC_PLLCFGR_DIVP3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */

+#define RCC_PLLCFGR_DIVP3EN                    RCC_PLLCFGR_DIVP3EN_Msk

+#define RCC_PLLCFGR_DIVQ3EN_Pos                (23U)

+#define RCC_PLLCFGR_DIVQ3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */

+#define RCC_PLLCFGR_DIVQ3EN                    RCC_PLLCFGR_DIVQ3EN_Msk

+#define RCC_PLLCFGR_DIVR3EN_Pos                (24U)

+#define RCC_PLLCFGR_DIVR3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */

+#define RCC_PLLCFGR_DIVR3EN                    RCC_PLLCFGR_DIVR3EN_Msk

+

+

+/********************  Bit definition for RCC_PLL1DIVR register  ***************/

+#define RCC_PLL1DIVR_N1_Pos                    (0U)

+#define RCC_PLL1DIVR_N1_Msk                    (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */

+#define RCC_PLL1DIVR_N1                        RCC_PLL1DIVR_N1_Msk

+#define RCC_PLL1DIVR_P1_Pos                    (9U)

+#define RCC_PLL1DIVR_P1_Msk                    (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL1DIVR_P1                        RCC_PLL1DIVR_P1_Msk

+#define RCC_PLL1DIVR_Q1_Pos                    (16U)

+#define RCC_PLL1DIVR_Q1_Msk                    (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */

+#define RCC_PLL1DIVR_Q1                        RCC_PLL1DIVR_Q1_Msk

+#define RCC_PLL1DIVR_R1_Pos                    (24U)

+#define RCC_PLL1DIVR_R1_Msk                    (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */

+#define RCC_PLL1DIVR_R1                        RCC_PLL1DIVR_R1_Msk

+

+/********************  Bit definition for RCC_PLL1FRACR register  ***************/

+#define RCC_PLL1FRACR_FRACN1_Pos               (3U)

+#define RCC_PLL1FRACR_FRACN1_Msk               (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL1FRACR_FRACN1                   RCC_PLL1FRACR_FRACN1_Msk

+

+/********************  Bit definition for RCC_PLL2DIVR register  ***************/

+#define RCC_PLL2DIVR_N2_Pos                    (0U)

+#define RCC_PLL2DIVR_N2_Msk                    (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */

+#define RCC_PLL2DIVR_N2                        RCC_PLL2DIVR_N2_Msk

+#define RCC_PLL2DIVR_P2_Pos                    (9U)

+#define RCC_PLL2DIVR_P2_Msk                    (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL2DIVR_P2                        RCC_PLL2DIVR_P2_Msk

+#define RCC_PLL2DIVR_Q2_Pos                    (16U)

+#define RCC_PLL2DIVR_Q2_Msk                    (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */

+#define RCC_PLL2DIVR_Q2                        RCC_PLL2DIVR_Q2_Msk

+#define RCC_PLL2DIVR_R2_Pos                    (24U)

+#define RCC_PLL2DIVR_R2_Msk                    (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */

+#define RCC_PLL2DIVR_R2                        RCC_PLL2DIVR_R2_Msk

+

+/********************  Bit definition for RCC_PLL2FRACR register  ***************/

+#define RCC_PLL2FRACR_FRACN2_Pos               (3U)

+#define RCC_PLL2FRACR_FRACN2_Msk               (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL2FRACR_FRACN2                   RCC_PLL2FRACR_FRACN2_Msk

+

+/********************  Bit definition for RCC_PLL3DIVR register  ***************/

+#define RCC_PLL3DIVR_N3_Pos                    (0U)

+#define RCC_PLL3DIVR_N3_Msk                    (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */

+#define RCC_PLL3DIVR_N3                        RCC_PLL3DIVR_N3_Msk

+#define RCC_PLL3DIVR_P3_Pos                    (9U)

+#define RCC_PLL3DIVR_P3_Msk                    (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL3DIVR_P3                        RCC_PLL3DIVR_P3_Msk

+#define RCC_PLL3DIVR_Q3_Pos                    (16U)

+#define RCC_PLL3DIVR_Q3_Msk                    (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */

+#define RCC_PLL3DIVR_Q3                        RCC_PLL3DIVR_Q3_Msk

+#define RCC_PLL3DIVR_R3_Pos                    (24U)

+#define RCC_PLL3DIVR_R3_Msk                    (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */

+#define RCC_PLL3DIVR_R3                        RCC_PLL3DIVR_R3_Msk

+

+/********************  Bit definition for RCC_PLL3FRACR register  ***************/

+#define RCC_PLL3FRACR_FRACN3_Pos               (3U)

+#define RCC_PLL3FRACR_FRACN3_Msk               (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL3FRACR_FRACN3                   RCC_PLL3FRACR_FRACN3_Msk

+

+/********************  Bit definition for RCC_D1CCIPR register  ***************/

+#define RCC_D1CCIPR_FMCSEL_Pos                 (0U)

+#define RCC_D1CCIPR_FMCSEL_Msk                 (0x3UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000003 */

+#define RCC_D1CCIPR_FMCSEL                     RCC_D1CCIPR_FMCSEL_Msk

+#define RCC_D1CCIPR_FMCSEL_0                   (0x1UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000001 */

+#define RCC_D1CCIPR_FMCSEL_1                   (0x2UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000002 */

+#define RCC_D1CCIPR_QSPISEL_Pos                (4U)

+#define RCC_D1CCIPR_QSPISEL_Msk                (0x3UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000030 */

+#define RCC_D1CCIPR_QSPISEL                    RCC_D1CCIPR_QSPISEL_Msk

+#define RCC_D1CCIPR_QSPISEL_0                  (0x1UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000010 */

+#define RCC_D1CCIPR_QSPISEL_1                  (0x2UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000020 */

+#define RCC_D1CCIPR_DSISEL_Pos                 (8U)

+#define RCC_D1CCIPR_DSISEL_Msk                 (0x1UL << RCC_D1CCIPR_DSISEL_Pos) /*!< 0x00000100 */

+#define RCC_D1CCIPR_DSISEL                     RCC_D1CCIPR_DSISEL_Msk

+#define RCC_D1CCIPR_SDMMCSEL_Pos               (16U)

+#define RCC_D1CCIPR_SDMMCSEL_Msk               (0x1UL << RCC_D1CCIPR_SDMMCSEL_Pos) /*!< 0x00010000 */

+#define RCC_D1CCIPR_SDMMCSEL                   RCC_D1CCIPR_SDMMCSEL_Msk

+#define RCC_D1CCIPR_CKPERSEL_Pos               (28U)

+#define RCC_D1CCIPR_CKPERSEL_Msk               (0x3UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x30000000 */

+#define RCC_D1CCIPR_CKPERSEL                   RCC_D1CCIPR_CKPERSEL_Msk

+#define RCC_D1CCIPR_CKPERSEL_0                 (0x1UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x10000000 */

+#define RCC_D1CCIPR_CKPERSEL_1                 (0x2UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x20000000 */

+

+/********************  Bit definition for RCC_D2CCIP1R register  ***************/

+#define RCC_D2CCIP1R_SAI1SEL_Pos               (0U)

+#define RCC_D2CCIP1R_SAI1SEL_Msk               (0x7UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000007 */

+#define RCC_D2CCIP1R_SAI1SEL                   RCC_D2CCIP1R_SAI1SEL_Msk

+#define RCC_D2CCIP1R_SAI1SEL_0                 (0x1UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000001 */

+#define RCC_D2CCIP1R_SAI1SEL_1                 (0x2UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000002 */

+#define RCC_D2CCIP1R_SAI1SEL_2                 (0x4UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000004 */

+

+#define RCC_D2CCIP1R_SAI23SEL_Pos              (6U)

+#define RCC_D2CCIP1R_SAI23SEL_Msk              (0x7UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x000001C0 */

+#define RCC_D2CCIP1R_SAI23SEL                  RCC_D2CCIP1R_SAI23SEL_Msk

+#define RCC_D2CCIP1R_SAI23SEL_0                (0x1UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000040 */

+#define RCC_D2CCIP1R_SAI23SEL_1                (0x2UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000080 */

+#define RCC_D2CCIP1R_SAI23SEL_2                (0x4UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000100 */

+

+#define RCC_D2CCIP1R_SPI123SEL_Pos             (12U)

+#define RCC_D2CCIP1R_SPI123SEL_Msk             (0x7UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */

+#define RCC_D2CCIP1R_SPI123SEL                 RCC_D2CCIP1R_SPI123SEL_Msk

+#define RCC_D2CCIP1R_SPI123SEL_0               (0x1UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */

+#define RCC_D2CCIP1R_SPI123SEL_1               (0x2UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */

+#define RCC_D2CCIP1R_SPI123SEL_2               (0x4UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */

+

+#define RCC_D2CCIP1R_SPI45SEL_Pos              (16U)

+#define RCC_D2CCIP1R_SPI45SEL_Msk              (0x7UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00070000 */

+#define RCC_D2CCIP1R_SPI45SEL                  RCC_D2CCIP1R_SPI45SEL_Msk

+#define RCC_D2CCIP1R_SPI45SEL_0                (0x1UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00010000 */

+#define RCC_D2CCIP1R_SPI45SEL_1                (0x2UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00020000 */

+#define RCC_D2CCIP1R_SPI45SEL_2                (0x4UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00040000 */

+

+#define RCC_D2CCIP1R_SPDIFSEL_Pos              (20U)

+#define RCC_D2CCIP1R_SPDIFSEL_Msk              (0x3UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00300000 */

+#define RCC_D2CCIP1R_SPDIFSEL                  RCC_D2CCIP1R_SPDIFSEL_Msk

+#define RCC_D2CCIP1R_SPDIFSEL_0                (0x1UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00100000 */

+#define RCC_D2CCIP1R_SPDIFSEL_1                (0x2UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00200000 */

+

+#define RCC_D2CCIP1R_DFSDM1SEL_Pos             (24U)

+#define RCC_D2CCIP1R_DFSDM1SEL_Msk             (0x1UL << RCC_D2CCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */

+#define RCC_D2CCIP1R_DFSDM1SEL                 RCC_D2CCIP1R_DFSDM1SEL_Msk

+

+#define RCC_D2CCIP1R_FDCANSEL_Pos              (28U)

+#define RCC_D2CCIP1R_FDCANSEL_Msk              (0x3UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x30000000 */

+#define RCC_D2CCIP1R_FDCANSEL                  RCC_D2CCIP1R_FDCANSEL_Msk

+#define RCC_D2CCIP1R_FDCANSEL_0                (0x1UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x10000000 */

+#define RCC_D2CCIP1R_FDCANSEL_1                (0x2UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x20000000 */

+

+#define RCC_D2CCIP1R_SWPSEL_Pos                (31U)

+#define RCC_D2CCIP1R_SWPSEL_Msk                (0x1UL << RCC_D2CCIP1R_SWPSEL_Pos) /*!< 0x80000000 */

+#define RCC_D2CCIP1R_SWPSEL                    RCC_D2CCIP1R_SWPSEL_Msk

+

+/********************  Bit definition for RCC_D2CCIP2R register  ***************/

+#define RCC_D2CCIP2R_USART16SEL_Pos            (3U)

+#define RCC_D2CCIP2R_USART16SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000038 */

+#define RCC_D2CCIP2R_USART16SEL                RCC_D2CCIP2R_USART16SEL_Msk

+#define RCC_D2CCIP2R_USART16SEL_0              (0x1UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000008 */

+#define RCC_D2CCIP2R_USART16SEL_1              (0x2UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000010 */

+#define RCC_D2CCIP2R_USART16SEL_2              (0x4UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000020 */

+

+#define RCC_D2CCIP2R_USART28SEL_Pos            (0U)

+#define RCC_D2CCIP2R_USART28SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000007 */

+#define RCC_D2CCIP2R_USART28SEL                RCC_D2CCIP2R_USART28SEL_Msk

+#define RCC_D2CCIP2R_USART28SEL_0              (0x1UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000001 */

+#define RCC_D2CCIP2R_USART28SEL_1              (0x2UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000002 */

+#define RCC_D2CCIP2R_USART28SEL_2              (0x4UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000004 */

+

+#define RCC_D2CCIP2R_RNGSEL_Pos                (8U)

+#define RCC_D2CCIP2R_RNGSEL_Msk                (0x3UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000300 */

+#define RCC_D2CCIP2R_RNGSEL                    RCC_D2CCIP2R_RNGSEL_Msk

+#define RCC_D2CCIP2R_RNGSEL_0                  (0x1UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000100 */

+#define RCC_D2CCIP2R_RNGSEL_1                  (0x2UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000200 */

+

+#define RCC_D2CCIP2R_I2C123SEL_Pos             (12U)

+#define RCC_D2CCIP2R_I2C123SEL_Msk             (0x3UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00003000 */

+#define RCC_D2CCIP2R_I2C123SEL                 RCC_D2CCIP2R_I2C123SEL_Msk

+#define RCC_D2CCIP2R_I2C123SEL_0               (0x1UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00001000 */

+#define RCC_D2CCIP2R_I2C123SEL_1               (0x2UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00002000 */

+

+#define RCC_D2CCIP2R_USBSEL_Pos                (20U)

+#define RCC_D2CCIP2R_USBSEL_Msk                (0x3UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00300000 */

+#define RCC_D2CCIP2R_USBSEL                    RCC_D2CCIP2R_USBSEL_Msk

+#define RCC_D2CCIP2R_USBSEL_0                  (0x1UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00100000 */

+#define RCC_D2CCIP2R_USBSEL_1                  (0x2UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00200000 */

+

+#define RCC_D2CCIP2R_CECSEL_Pos                (22U)

+#define RCC_D2CCIP2R_CECSEL_Msk                (0x3UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00C00000 */

+#define RCC_D2CCIP2R_CECSEL                    RCC_D2CCIP2R_CECSEL_Msk

+#define RCC_D2CCIP2R_CECSEL_0                  (0x1UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00400000 */

+#define RCC_D2CCIP2R_CECSEL_1                  (0x2UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00800000 */

+

+#define RCC_D2CCIP2R_LPTIM1SEL_Pos             (28U)

+#define RCC_D2CCIP2R_LPTIM1SEL_Msk             (0x7UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x70000000 */

+#define RCC_D2CCIP2R_LPTIM1SEL                 RCC_D2CCIP2R_LPTIM1SEL_Msk

+#define RCC_D2CCIP2R_LPTIM1SEL_0               (0x1UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x10000000 */

+#define RCC_D2CCIP2R_LPTIM1SEL_1               (0x2UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x20000000 */

+#define RCC_D2CCIP2R_LPTIM1SEL_2               (0x4UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition for RCC_D3CCIPR register  ***************/

+#define RCC_D3CCIPR_LPUART1SEL_Pos             (0U)

+#define RCC_D3CCIPR_LPUART1SEL_Msk             (0x7UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000007 */

+#define RCC_D3CCIPR_LPUART1SEL                 RCC_D3CCIPR_LPUART1SEL_Msk

+#define RCC_D3CCIPR_LPUART1SEL_0               (0x1UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000001 */

+#define RCC_D3CCIPR_LPUART1SEL_1               (0x2UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000002 */

+#define RCC_D3CCIPR_LPUART1SEL_2               (0x4UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000004 */

+

+#define RCC_D3CCIPR_I2C4SEL_Pos                (8U)

+#define RCC_D3CCIPR_I2C4SEL_Msk                (0x3UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000300 */

+#define RCC_D3CCIPR_I2C4SEL                    RCC_D3CCIPR_I2C4SEL_Msk

+#define RCC_D3CCIPR_I2C4SEL_0                  (0x1UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000100 */

+#define RCC_D3CCIPR_I2C4SEL_1                  (0x2UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000200 */

+

+#define RCC_D3CCIPR_LPTIM2SEL_Pos              (10U)

+#define RCC_D3CCIPR_LPTIM2SEL_Msk              (0x7UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001C00 */

+#define RCC_D3CCIPR_LPTIM2SEL                  RCC_D3CCIPR_LPTIM2SEL_Msk

+#define RCC_D3CCIPR_LPTIM2SEL_0                (0x1UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000400 */

+#define RCC_D3CCIPR_LPTIM2SEL_1                (0x2UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000800 */

+#define RCC_D3CCIPR_LPTIM2SEL_2                (0x4UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001000 */

+

+#define RCC_D3CCIPR_LPTIM345SEL_Pos            (13U)

+#define RCC_D3CCIPR_LPTIM345SEL_Msk            (0x7UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x0000E000 */

+#define RCC_D3CCIPR_LPTIM345SEL                RCC_D3CCIPR_LPTIM345SEL_Msk

+#define RCC_D3CCIPR_LPTIM345SEL_0              (0x1UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00002000 */

+#define RCC_D3CCIPR_LPTIM345SEL_1              (0x2UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00004000 */

+#define RCC_D3CCIPR_LPTIM345SEL_2              (0x4UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00008000 */

+

+#define RCC_D3CCIPR_SAI4ASEL_Pos               (21U)

+#define RCC_D3CCIPR_SAI4ASEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00E00000 */

+#define RCC_D3CCIPR_SAI4ASEL                   RCC_D3CCIPR_SAI4ASEL_Msk

+#define RCC_D3CCIPR_SAI4ASEL_0                 (0x1UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00200000 */

+#define RCC_D3CCIPR_SAI4ASEL_1                 (0x2UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00400000 */

+#define RCC_D3CCIPR_SAI4ASEL_2                 (0x4UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00800000 */

+

+#define RCC_D3CCIPR_SAI4BSEL_Pos               (24U)

+#define RCC_D3CCIPR_SAI4BSEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x07000000 */

+#define RCC_D3CCIPR_SAI4BSEL                   RCC_D3CCIPR_SAI4BSEL_Msk

+#define RCC_D3CCIPR_SAI4BSEL_0                 (0x1UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x01000000 */

+#define RCC_D3CCIPR_SAI4BSEL_1                 (0x2UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x02000000 */

+#define RCC_D3CCIPR_SAI4BSEL_2                 (0x4UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x04000000 */

+

+#define RCC_D3CCIPR_ADCSEL_Pos                 (16U)

+#define RCC_D3CCIPR_ADCSEL_Msk                 (0x3UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00030000 */

+#define RCC_D3CCIPR_ADCSEL                     RCC_D3CCIPR_ADCSEL_Msk

+#define RCC_D3CCIPR_ADCSEL_0                   (0x1UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00010000 */

+#define RCC_D3CCIPR_ADCSEL_1                   (0x2UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00020000 */

+

+#define RCC_D3CCIPR_SPI6SEL_Pos                (28U)

+#define RCC_D3CCIPR_SPI6SEL_Msk                (0x7UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x70000000 */

+#define RCC_D3CCIPR_SPI6SEL                    RCC_D3CCIPR_SPI6SEL_Msk

+#define RCC_D3CCIPR_SPI6SEL_0                  (0x1UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x10000000 */

+#define RCC_D3CCIPR_SPI6SEL_1                  (0x2UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x20000000 */

+#define RCC_D3CCIPR_SPI6SEL_2                  (0x4UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x40000000 */

+/********************  Bit definition for RCC_CIER register  ******************/

+#define RCC_CIER_LSIRDYIE_Pos                  (0U)

+#define RCC_CIER_LSIRDYIE_Msk                  (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */

+#define RCC_CIER_LSIRDYIE                      RCC_CIER_LSIRDYIE_Msk

+#define RCC_CIER_LSERDYIE_Pos                  (1U)

+#define RCC_CIER_LSERDYIE_Msk                  (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */

+#define RCC_CIER_LSERDYIE                      RCC_CIER_LSERDYIE_Msk

+#define RCC_CIER_HSIRDYIE_Pos                  (2U)

+#define RCC_CIER_HSIRDYIE_Msk                  (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */

+#define RCC_CIER_HSIRDYIE                      RCC_CIER_HSIRDYIE_Msk

+#define RCC_CIER_HSERDYIE_Pos                  (3U)

+#define RCC_CIER_HSERDYIE_Msk                  (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */

+#define RCC_CIER_HSERDYIE                      RCC_CIER_HSERDYIE_Msk

+#define RCC_CIER_CSIRDYIE_Pos                  (4U)

+#define RCC_CIER_CSIRDYIE_Msk                  (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */

+#define RCC_CIER_CSIRDYIE                      RCC_CIER_CSIRDYIE_Msk

+#define RCC_CIER_HSI48RDYIE_Pos                (5U)

+#define RCC_CIER_HSI48RDYIE_Msk                (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */

+#define RCC_CIER_HSI48RDYIE                    RCC_CIER_HSI48RDYIE_Msk

+#define RCC_CIER_PLL1RDYIE_Pos                 (6U)

+#define RCC_CIER_PLL1RDYIE_Msk                 (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */

+#define RCC_CIER_PLL1RDYIE                     RCC_CIER_PLL1RDYIE_Msk

+#define RCC_CIER_PLL2RDYIE_Pos                 (7U)

+#define RCC_CIER_PLL2RDYIE_Msk                 (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */

+#define RCC_CIER_PLL2RDYIE                     RCC_CIER_PLL2RDYIE_Msk

+#define RCC_CIER_PLL3RDYIE_Pos                 (8U)

+#define RCC_CIER_PLL3RDYIE_Msk                 (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */

+#define RCC_CIER_PLL3RDYIE                     RCC_CIER_PLL3RDYIE_Msk

+#define RCC_CIER_LSECSSIE_Pos                  (9U)

+#define RCC_CIER_LSECSSIE_Msk                  (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */

+#define RCC_CIER_LSECSSIE                      RCC_CIER_LSECSSIE_Msk

+

+/********************  Bit definition for RCC_CIFR register  ******************/

+#define RCC_CIFR_LSIRDYF_Pos                   (0U)

+#define RCC_CIFR_LSIRDYF_Msk                   (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */

+#define RCC_CIFR_LSIRDYF                       RCC_CIFR_LSIRDYF_Msk

+#define RCC_CIFR_LSERDYF_Pos                   (1U)

+#define RCC_CIFR_LSERDYF_Msk                   (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */

+#define RCC_CIFR_LSERDYF                       RCC_CIFR_LSERDYF_Msk

+#define RCC_CIFR_HSIRDYF_Pos                   (2U)

+#define RCC_CIFR_HSIRDYF_Msk                   (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */

+#define RCC_CIFR_HSIRDYF                       RCC_CIFR_HSIRDYF_Msk

+#define RCC_CIFR_HSERDYF_Pos                   (3U)

+#define RCC_CIFR_HSERDYF_Msk                   (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */

+#define RCC_CIFR_HSERDYF                       RCC_CIFR_HSERDYF_Msk

+#define RCC_CIFR_CSIRDYF_Pos                   (4U)

+#define RCC_CIFR_CSIRDYF_Msk                   (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */

+#define RCC_CIFR_CSIRDYF                       RCC_CIFR_CSIRDYF_Msk

+#define RCC_CIFR_HSI48RDYF_Pos                 (5U)

+#define RCC_CIFR_HSI48RDYF_Msk                 (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */

+#define RCC_CIFR_HSI48RDYF                     RCC_CIFR_HSI48RDYF_Msk

+#define RCC_CIFR_PLLRDYF_Pos                   (6U)

+#define RCC_CIFR_PLLRDYF_Msk                   (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */

+#define RCC_CIFR_PLLRDYF                       RCC_CIFR_PLLRDYF_Msk

+#define RCC_CIFR_PLL2RDYF_Pos                  (7U)

+#define RCC_CIFR_PLL2RDYF_Msk                  (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */

+#define RCC_CIFR_PLL2RDYF                      RCC_CIFR_PLL2RDYF_Msk

+#define RCC_CIFR_PLL3RDYF_Pos                  (8U)

+#define RCC_CIFR_PLL3RDYF_Msk                  (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */

+#define RCC_CIFR_PLL3RDYF                      RCC_CIFR_PLL3RDYF_Msk

+#define RCC_CIFR_LSECSSF_Pos                   (9U)

+#define RCC_CIFR_LSECSSF_Msk                   (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */

+#define RCC_CIFR_LSECSSF                       RCC_CIFR_LSECSSF_Msk

+#define RCC_CIFR_HSECSSF_Pos                   (10U)

+#define RCC_CIFR_HSECSSF_Msk                   (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */

+#define RCC_CIFR_HSECSSF                       RCC_CIFR_HSECSSF_Msk

+

+/********************  Bit definition for RCC_CICR register  ******************/

+#define RCC_CICR_LSIRDYC_Pos                   (0U)

+#define RCC_CICR_LSIRDYC_Msk                   (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */

+#define RCC_CICR_LSIRDYC                       RCC_CICR_LSIRDYC_Msk

+#define RCC_CICR_LSERDYC_Pos                   (1U)

+#define RCC_CICR_LSERDYC_Msk                   (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */

+#define RCC_CICR_LSERDYC                       RCC_CICR_LSERDYC_Msk

+#define RCC_CICR_HSIRDYC_Pos                   (2U)

+#define RCC_CICR_HSIRDYC_Msk                   (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */

+#define RCC_CICR_HSIRDYC                       RCC_CICR_HSIRDYC_Msk

+#define RCC_CICR_HSERDYC_Pos                   (3U)

+#define RCC_CICR_HSERDYC_Msk                   (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */

+#define RCC_CICR_HSERDYC                       RCC_CICR_HSERDYC_Msk

+#define RCC_CICR_CSIRDYC_Pos                   (4U)

+#define RCC_CICR_CSIRDYC_Msk                   (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */

+#define RCC_CICR_CSIRDYC                       RCC_CICR_CSIRDYC_Msk

+#define RCC_CICR_HSI48RDYC_Pos                 (5U)

+#define RCC_CICR_HSI48RDYC_Msk                 (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */

+#define RCC_CICR_HSI48RDYC                     RCC_CICR_HSI48RDYC_Msk

+#define RCC_CICR_PLLRDYC_Pos                   (6U)

+#define RCC_CICR_PLLRDYC_Msk                   (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */

+#define RCC_CICR_PLLRDYC                       RCC_CICR_PLLRDYC_Msk

+#define RCC_CICR_PLL2RDYC_Pos                  (7U)

+#define RCC_CICR_PLL2RDYC_Msk                  (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */

+#define RCC_CICR_PLL2RDYC                      RCC_CICR_PLL2RDYC_Msk

+#define RCC_CICR_PLL3RDYC_Pos                  (8U)

+#define RCC_CICR_PLL3RDYC_Msk                  (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */

+#define RCC_CICR_PLL3RDYC                      RCC_CICR_PLL3RDYC_Msk

+#define RCC_CICR_LSECSSC_Pos                   (9U)

+#define RCC_CICR_LSECSSC_Msk                   (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */

+#define RCC_CICR_LSECSSC                       RCC_CICR_LSECSSC_Msk

+#define RCC_CICR_HSECSSC_Pos                   (10U)

+#define RCC_CICR_HSECSSC_Msk                   (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */

+#define RCC_CICR_HSECSSC                       RCC_CICR_HSECSSC_Msk

+

+/********************  Bit definition for RCC_BDCR register  ******************/

+#define RCC_BDCR_LSEON_Pos                     (0U)

+#define RCC_BDCR_LSEON_Msk                     (0x1UL << RCC_BDCR_LSEON_Pos)   /*!< 0x00000001 */

+#define RCC_BDCR_LSEON                         RCC_BDCR_LSEON_Msk

+#define RCC_BDCR_LSERDY_Pos                    (1U)

+#define RCC_BDCR_LSERDY_Msk                    (0x1UL << RCC_BDCR_LSERDY_Pos)  /*!< 0x00000002 */

+#define RCC_BDCR_LSERDY                        RCC_BDCR_LSERDY_Msk

+#define RCC_BDCR_LSEBYP_Pos                    (2U)

+#define RCC_BDCR_LSEBYP_Msk                    (0x1UL << RCC_BDCR_LSEBYP_Pos)  /*!< 0x00000004 */

+#define RCC_BDCR_LSEBYP                        RCC_BDCR_LSEBYP_Msk

+

+#define RCC_BDCR_LSEDRV_Pos                    (3U)

+#define RCC_BDCR_LSEDRV_Msk                    (0x3UL << RCC_BDCR_LSEDRV_Pos)  /*!< 0x00000018 */

+#define RCC_BDCR_LSEDRV                        RCC_BDCR_LSEDRV_Msk

+#define RCC_BDCR_LSEDRV_0                      (0x1UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000008 */

+#define RCC_BDCR_LSEDRV_1                      (0x2UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000010 */

+

+#define RCC_BDCR_LSECSSON_Pos                  (5U)

+#define RCC_BDCR_LSECSSON_Msk                  (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */

+#define RCC_BDCR_LSECSSON                      RCC_BDCR_LSECSSON_Msk

+#define RCC_BDCR_LSECSSD_Pos                   (6U)

+#define RCC_BDCR_LSECSSD_Msk                   (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */

+#define RCC_BDCR_LSECSSD                       RCC_BDCR_LSECSSD_Msk

+

+#define RCC_BDCR_RTCSEL_Pos                    (8U)

+#define RCC_BDCR_RTCSEL_Msk                    (0x3UL << RCC_BDCR_RTCSEL_Pos)  /*!< 0x00000300 */

+#define RCC_BDCR_RTCSEL                        RCC_BDCR_RTCSEL_Msk

+#define RCC_BDCR_RTCSEL_0                      (0x1UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000100 */

+#define RCC_BDCR_RTCSEL_1                      (0x2UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000200 */

+

+#define RCC_BDCR_RTCEN_Pos                     (15U)

+#define RCC_BDCR_RTCEN_Msk                     (0x1UL << RCC_BDCR_RTCEN_Pos)   /*!< 0x00008000 */

+#define RCC_BDCR_RTCEN                         RCC_BDCR_RTCEN_Msk

+#define RCC_BDCR_BDRST_Pos                     (16U)

+#define RCC_BDCR_BDRST_Msk                     (0x1UL << RCC_BDCR_BDRST_Pos)   /*!< 0x00010000 */

+#define RCC_BDCR_BDRST                         RCC_BDCR_BDRST_Msk

+/********************  Bit definition for RCC_CSR register  *******************/

+#define RCC_CSR_LSION_Pos                      (0U)

+#define RCC_CSR_LSION_Msk                      (0x1UL << RCC_CSR_LSION_Pos)    /*!< 0x00000001 */

+#define RCC_CSR_LSION                          RCC_CSR_LSION_Msk

+#define RCC_CSR_LSIRDY_Pos                     (1U)

+#define RCC_CSR_LSIRDY_Msk                     (0x1UL << RCC_CSR_LSIRDY_Pos)   /*!< 0x00000002 */

+#define RCC_CSR_LSIRDY                         RCC_CSR_LSIRDY_Msk

+

+

+/********************  Bit definition for RCC_AHB3ENR register  **************/

+#define RCC_AHB3ENR_MDMAEN_Pos                 (0U)

+#define RCC_AHB3ENR_MDMAEN_Msk                 (0x1UL << RCC_AHB3ENR_MDMAEN_Pos)       /*!< 0x00000001 */

+#define RCC_AHB3ENR_MDMAEN                     RCC_AHB3ENR_MDMAEN_Msk

+#define RCC_AHB3ENR_DMA2DEN_Pos                (4U)

+#define RCC_AHB3ENR_DMA2DEN_Msk                (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos)      /*!< 0x00000010 */

+#define RCC_AHB3ENR_DMA2DEN                    RCC_AHB3ENR_DMA2DEN_Msk

+#define RCC_AHB3ENR_JPGDECEN_Pos               (5U)

+#define RCC_AHB3ENR_JPGDECEN_Msk               (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos)     /*!< 0x00000020 */

+#define RCC_AHB3ENR_JPGDECEN                   RCC_AHB3ENR_JPGDECEN_Msk

+#define RCC_AHB3ENR_FMCEN_Pos                  (12U)

+#define RCC_AHB3ENR_FMCEN_Msk                  (0x1UL << RCC_AHB3ENR_FMCEN_Pos)        /*!< 0x00001000 */

+#define RCC_AHB3ENR_FMCEN                      RCC_AHB3ENR_FMCEN_Msk

+#define RCC_AHB3ENR_QSPIEN_Pos                 (14U)

+#define RCC_AHB3ENR_QSPIEN_Msk                 (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)       /*!< 0x00004000 */

+#define RCC_AHB3ENR_QSPIEN                     RCC_AHB3ENR_QSPIEN_Msk

+#define RCC_AHB3ENR_SDMMC1EN_Pos               (16U)

+#define RCC_AHB3ENR_SDMMC1EN_Msk               (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos)     /*!< 0x00010000 */

+#define RCC_AHB3ENR_SDMMC1EN                   RCC_AHB3ENR_SDMMC1EN_Msk

+#define RCC_AHB3ENR_FLASHEN_Pos                (8U)

+#define RCC_AHB3ENR_FLASHEN_Msk                (0x1UL << RCC_AHB3ENR_FLASHEN_Pos)      /*!< 0x00000100 */

+#define RCC_AHB3ENR_FLASHEN                    RCC_AHB3ENR_FLASHEN_Msk

+#define RCC_AHB3ENR_DTCM1EN_Pos                (28U)

+#define RCC_AHB3ENR_DTCM1EN_Msk                (0x1UL << RCC_AHB3ENR_DTCM1EN_Pos)      /*!< 0x10000000 */

+#define RCC_AHB3ENR_DTCM1EN                    RCC_AHB3ENR_DTCM1EN_Msk

+#define RCC_AHB3ENR_DTCM2EN_Pos                (29U)

+#define RCC_AHB3ENR_DTCM2EN_Msk                (0x1UL << RCC_AHB3ENR_DTCM2EN_Pos)      /*!< 0x20000000 */

+#define RCC_AHB3ENR_DTCM2EN                    RCC_AHB3ENR_DTCM2EN_Msk

+#define RCC_AHB3ENR_ITCMEN_Pos                 (30U)

+#define RCC_AHB3ENR_ITCMEN_Msk                 (0x1UL << RCC_AHB3ENR_ITCMEN_Pos)       /*!< 0x40000000 */

+#define RCC_AHB3ENR_ITCMEN                     RCC_AHB3ENR_ITCMEN_Msk

+#define RCC_AHB3ENR_AXISRAMEN_Pos              (31U)

+#define RCC_AHB3ENR_AXISRAMEN_Msk              (0x1UL << RCC_AHB3ENR_AXISRAMEN_Pos)    /*!< 0x80000000 */

+#define RCC_AHB3ENR_AXISRAMEN                  RCC_AHB3ENR_AXISRAMEN_Msk

+

+/* Legacy define */

+#define RCC_AHB3ENR_D1SRAM1EN_Pos              RCC_AHB3ENR_AXISRAMEN_Pos

+#define RCC_AHB3ENR_D1SRAM1EN_Msk              RCC_AHB3ENR_AXISRAMEN_Msk

+#define RCC_AHB3ENR_D1SRAM1EN                  RCC_AHB3ENR_AXISRAMEN

+

+/********************  Bit definition for RCC_AHB1ENR register  ***************/

+#define RCC_AHB1ENR_DMA1EN_Pos                 (0U)

+#define RCC_AHB1ENR_DMA1EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)          /*!< 0x00000001 */

+#define RCC_AHB1ENR_DMA1EN                     RCC_AHB1ENR_DMA1EN_Msk

+#define RCC_AHB1ENR_DMA2EN_Pos                 (1U)

+#define RCC_AHB1ENR_DMA2EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)          /*!< 0x00000002 */

+#define RCC_AHB1ENR_DMA2EN                     RCC_AHB1ENR_DMA2EN_Msk

+#define RCC_AHB1ENR_ADC12EN_Pos                (5U)

+#define RCC_AHB1ENR_ADC12EN_Msk                (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)         /*!< 0x00000020 */

+#define RCC_AHB1ENR_ADC12EN                    RCC_AHB1ENR_ADC12EN_Msk

+#define RCC_AHB1ENR_ARTEN_Pos                  (14U)

+#define RCC_AHB1ENR_ARTEN_Msk                  (0x1UL << RCC_AHB1ENR_ARTEN_Pos)           /*!< 0x00004000 */

+#define RCC_AHB1ENR_ARTEN                      RCC_AHB1ENR_ARTEN_Msk

+#define RCC_AHB1ENR_ETH1MACEN_Pos              (15U)

+#define RCC_AHB1ENR_ETH1MACEN_Msk              (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos)       /*!< 0x00008000 */

+#define RCC_AHB1ENR_ETH1MACEN                  RCC_AHB1ENR_ETH1MACEN_Msk

+#define RCC_AHB1ENR_ETH1TXEN_Pos               (16U)

+#define RCC_AHB1ENR_ETH1TXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos)        /*!< 0x00010000 */

+#define RCC_AHB1ENR_ETH1TXEN                   RCC_AHB1ENR_ETH1TXEN_Msk

+#define RCC_AHB1ENR_ETH1RXEN_Pos               (17U)

+#define RCC_AHB1ENR_ETH1RXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos)        /*!< 0x00020000 */

+#define RCC_AHB1ENR_ETH1RXEN                   RCC_AHB1ENR_ETH1RXEN_Msk

+#define RCC_AHB1ENR_USB1OTGHSEN_Pos            (25U)

+#define RCC_AHB1ENR_USB1OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos)     /*!< 0x02000000 */

+#define RCC_AHB1ENR_USB1OTGHSEN                RCC_AHB1ENR_USB1OTGHSEN_Msk

+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos        (26U)

+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */

+#define RCC_AHB1ENR_USB1OTGHSULPIEN            RCC_AHB1ENR_USB1OTGHSULPIEN_Msk

+#define RCC_AHB1ENR_USB2OTGFSEN_Pos            (27U)

+#define RCC_AHB1ENR_USB2OTGFSEN_Msk            (0x1UL << RCC_AHB1ENR_USB2OTGFSEN_Pos)     /*!< 0x08000000 */

+#define RCC_AHB1ENR_USB2OTGFSEN                RCC_AHB1ENR_USB2OTGFSEN_Msk

+#define RCC_AHB1ENR_USB2OTGFSULPIEN_Pos        (28U)

+#define RCC_AHB1ENR_USB2OTGFSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB2OTGFSULPIEN_Pos) /*!< 0x10000000 */

+#define RCC_AHB1ENR_USB2OTGFSULPIEN            RCC_AHB1ENR_USB2OTGFSULPIEN_Msk

+

+/* Legacy define */

+#define RCC_AHB1ENR_USB2OTGHSEN_Pos            RCC_AHB1ENR_USB2OTGFSEN_Pos

+#define RCC_AHB1ENR_USB2OTGHSEN_Msk            RCC_AHB1ENR_USB2OTGFSEN_Msk

+#define RCC_AHB1ENR_USB2OTGHSEN                RCC_AHB1ENR_USB2OTGFSEN

+#define RCC_AHB1ENR_USB2OTGHSULPIEN_Pos        RCC_AHB1ENR_USB2OTGFSULPIEN_Pos

+#define RCC_AHB1ENR_USB2OTGHSULPIEN_Msk        RCC_AHB1ENR_USB2OTGFSULPIEN_Msk

+#define RCC_AHB1ENR_USB2OTGHSULPIEN            RCC_AHB1ENR_USB2OTGFSULPIEN

+

+

+/********************  Bit definition for RCC_AHB2ENR register  ***************/

+#define RCC_AHB2ENR_DCMIEN_Pos                 (0U)

+#define RCC_AHB2ENR_DCMIEN_Msk                 (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)          /*!< 0x00000001 */

+#define RCC_AHB2ENR_DCMIEN                     RCC_AHB2ENR_DCMIEN_Msk

+#define RCC_AHB2ENR_RNGEN_Pos                  (6U)

+#define RCC_AHB2ENR_RNGEN_Msk                  (0x1UL << RCC_AHB2ENR_RNGEN_Pos)           /*!< 0x00000040 */

+#define RCC_AHB2ENR_RNGEN                      RCC_AHB2ENR_RNGEN_Msk

+#define RCC_AHB2ENR_SDMMC2EN_Pos               (9U)

+#define RCC_AHB2ENR_SDMMC2EN_Msk               (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)        /*!< 0x00000200 */

+#define RCC_AHB2ENR_SDMMC2EN                   RCC_AHB2ENR_SDMMC2EN_Msk

+#define RCC_AHB2ENR_SRAM1EN_Pos                (29U)

+#define RCC_AHB2ENR_SRAM1EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos)       /*!< 0x20000000 */

+#define RCC_AHB2ENR_SRAM1EN                    RCC_AHB2ENR_SRAM1EN_Msk

+#define RCC_AHB2ENR_SRAM2EN_Pos                (30U)

+#define RCC_AHB2ENR_SRAM2EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos)       /*!< 0x40000000 */

+#define RCC_AHB2ENR_SRAM2EN                    RCC_AHB2ENR_SRAM2EN_Msk

+#define RCC_AHB2ENR_SRAM3EN_Pos                (31U)

+#define RCC_AHB2ENR_SRAM3EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM3EN_Pos)       /*!< 0x80000000 */

+#define RCC_AHB2ENR_SRAM3EN                    RCC_AHB2ENR_SRAM3EN_Msk

+

+/* Legacy define */

+#define RCC_AHB2ENR_D2SRAM1EN_Pos              RCC_AHB2ENR_SRAM1EN_Pos

+#define RCC_AHB2ENR_D2SRAM1EN_Msk              RCC_AHB2ENR_SRAM1EN_Msk

+#define RCC_AHB2ENR_D2SRAM1EN                  RCC_AHB2ENR_SRAM1EN

+#define RCC_AHB2ENR_D2SRAM2EN_Pos              RCC_AHB2ENR_SRAM2EN_Pos

+#define RCC_AHB2ENR_D2SRAM2EN_Msk              RCC_AHB2ENR_SRAM2EN_Msk

+#define RCC_AHB2ENR_D2SRAM2EN                  RCC_AHB2ENR_SRAM2EN

+#define RCC_AHB2ENR_D2SRAM3EN_Pos              RCC_AHB2ENR_SRAM3EN_Pos

+#define RCC_AHB2ENR_D2SRAM3EN_Msk              RCC_AHB2ENR_SRAM3EN_Msk

+#define RCC_AHB2ENR_D2SRAM3EN                  RCC_AHB2ENR_SRAM3EN

+

+/********************  Bit definition for RCC_AHB4ENR register  ******************/

+#define RCC_AHB4ENR_GPIOAEN_Pos                (0U)

+#define RCC_AHB4ENR_GPIOAEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)         /*!< 0x00000001 */

+#define RCC_AHB4ENR_GPIOAEN                    RCC_AHB4ENR_GPIOAEN_Msk

+#define RCC_AHB4ENR_GPIOBEN_Pos                (1U)

+#define RCC_AHB4ENR_GPIOBEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)         /*!< 0x00000002 */

+#define RCC_AHB4ENR_GPIOBEN                    RCC_AHB4ENR_GPIOBEN_Msk

+#define RCC_AHB4ENR_GPIOCEN_Pos                (2U)

+#define RCC_AHB4ENR_GPIOCEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)         /*!< 0x00000004 */

+#define RCC_AHB4ENR_GPIOCEN                    RCC_AHB4ENR_GPIOCEN_Msk

+#define RCC_AHB4ENR_GPIODEN_Pos                (3U)

+#define RCC_AHB4ENR_GPIODEN_Msk                (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)         /*!< 0x00000008 */

+#define RCC_AHB4ENR_GPIODEN                    RCC_AHB4ENR_GPIODEN_Msk

+#define RCC_AHB4ENR_GPIOEEN_Pos                (4U)

+#define RCC_AHB4ENR_GPIOEEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)         /*!< 0x00000010 */

+#define RCC_AHB4ENR_GPIOEEN                    RCC_AHB4ENR_GPIOEEN_Msk

+#define RCC_AHB4ENR_GPIOFEN_Pos                (5U)

+#define RCC_AHB4ENR_GPIOFEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)         /*!< 0x00000020 */

+#define RCC_AHB4ENR_GPIOFEN                    RCC_AHB4ENR_GPIOFEN_Msk

+#define RCC_AHB4ENR_GPIOGEN_Pos                (6U)

+#define RCC_AHB4ENR_GPIOGEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)         /*!< 0x00000040 */

+#define RCC_AHB4ENR_GPIOGEN                    RCC_AHB4ENR_GPIOGEN_Msk

+#define RCC_AHB4ENR_GPIOHEN_Pos                (7U)

+#define RCC_AHB4ENR_GPIOHEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)         /*!< 0x00000080 */

+#define RCC_AHB4ENR_GPIOHEN                    RCC_AHB4ENR_GPIOHEN_Msk

+#define RCC_AHB4ENR_GPIOIEN_Pos                (8U)

+#define RCC_AHB4ENR_GPIOIEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos)         /*!< 0x00000100 */

+#define RCC_AHB4ENR_GPIOIEN                    RCC_AHB4ENR_GPIOIEN_Msk

+#define RCC_AHB4ENR_GPIOJEN_Pos                (9U)

+#define RCC_AHB4ENR_GPIOJEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos)         /*!< 0x00000200 */

+#define RCC_AHB4ENR_GPIOJEN                    RCC_AHB4ENR_GPIOJEN_Msk

+#define RCC_AHB4ENR_GPIOKEN_Pos                (10U)

+#define RCC_AHB4ENR_GPIOKEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos)         /*!< 0x00000400 */

+#define RCC_AHB4ENR_GPIOKEN                    RCC_AHB4ENR_GPIOKEN_Msk

+#define RCC_AHB4ENR_CRCEN_Pos                  (19U)

+#define RCC_AHB4ENR_CRCEN_Msk                  (0x1UL << RCC_AHB4ENR_CRCEN_Pos)           /*!< 0x00080000 */

+#define RCC_AHB4ENR_CRCEN                      RCC_AHB4ENR_CRCEN_Msk

+#define RCC_AHB4ENR_BDMAEN_Pos                 (21U)

+#define RCC_AHB4ENR_BDMAEN_Msk                 (0x1UL << RCC_AHB4ENR_BDMAEN_Pos)          /*!< 0x00200000 */

+#define RCC_AHB4ENR_BDMAEN                     RCC_AHB4ENR_BDMAEN_Msk

+#define RCC_AHB4ENR_ADC3EN_Pos                 (24U)

+#define RCC_AHB4ENR_ADC3EN_Msk                 (0x1UL << RCC_AHB4ENR_ADC3EN_Pos)          /*!< 0x01000000 */

+#define RCC_AHB4ENR_ADC3EN                     RCC_AHB4ENR_ADC3EN_Msk

+#define RCC_AHB4ENR_HSEMEN_Pos                 (25U)

+#define RCC_AHB4ENR_HSEMEN_Msk                 (0x1UL << RCC_AHB4ENR_HSEMEN_Pos)          /*!< 0x02000000 */

+#define RCC_AHB4ENR_HSEMEN                     RCC_AHB4ENR_HSEMEN_Msk

+#define RCC_AHB4ENR_BKPRAMEN_Pos               (28U)

+#define RCC_AHB4ENR_BKPRAMEN_Msk               (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)        /*!< 0x10000000 */

+#define RCC_AHB4ENR_BKPRAMEN                   RCC_AHB4ENR_BKPRAMEN_Msk

+

+/********************  Bit definition for RCC_APB3ENR register  ******************/

+#define RCC_APB3ENR_LTDCEN_Pos                 (3U)

+#define RCC_APB3ENR_LTDCEN_Msk                 (0x1UL << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */

+#define RCC_APB3ENR_LTDCEN                     RCC_APB3ENR_LTDCEN_Msk

+#define RCC_APB3ENR_DSIEN_Pos                  (4U)

+#define RCC_APB3ENR_DSIEN_Msk                  (0x1UL << RCC_APB3ENR_DSIEN_Pos) /*!< 0x00000010 */

+#define RCC_APB3ENR_DSIEN                      RCC_APB3ENR_DSIEN_Msk

+#define RCC_APB3ENR_WWDG1EN_Pos                (6U)

+#define RCC_APB3ENR_WWDG1EN_Msk                (0x1UL << RCC_APB3ENR_WWDG1EN_Pos) /*!< 0x00000040 */

+#define RCC_APB3ENR_WWDG1EN                    RCC_APB3ENR_WWDG1EN_Msk

+

+/********************  Bit definition for RCC_APB1LENR register  ******************/

+

+#define RCC_APB1LENR_TIM2EN_Pos                (0U)

+#define RCC_APB1LENR_TIM2EN_Msk                (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */

+#define RCC_APB1LENR_TIM2EN                    RCC_APB1LENR_TIM2EN_Msk

+#define RCC_APB1LENR_TIM3EN_Pos                (1U)

+#define RCC_APB1LENR_TIM3EN_Msk                (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */

+#define RCC_APB1LENR_TIM3EN                    RCC_APB1LENR_TIM3EN_Msk

+#define RCC_APB1LENR_TIM4EN_Pos                (2U)

+#define RCC_APB1LENR_TIM4EN_Msk                (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */

+#define RCC_APB1LENR_TIM4EN                    RCC_APB1LENR_TIM4EN_Msk

+#define RCC_APB1LENR_TIM5EN_Pos                (3U)

+#define RCC_APB1LENR_TIM5EN_Msk                (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */

+#define RCC_APB1LENR_TIM5EN                    RCC_APB1LENR_TIM5EN_Msk

+#define RCC_APB1LENR_TIM6EN_Pos                (4U)

+#define RCC_APB1LENR_TIM6EN_Msk                (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */

+#define RCC_APB1LENR_TIM6EN                    RCC_APB1LENR_TIM6EN_Msk

+#define RCC_APB1LENR_TIM7EN_Pos                (5U)

+#define RCC_APB1LENR_TIM7EN_Msk                (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */

+#define RCC_APB1LENR_TIM7EN                    RCC_APB1LENR_TIM7EN_Msk

+#define RCC_APB1LENR_TIM12EN_Pos               (6U)

+#define RCC_APB1LENR_TIM12EN_Msk               (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */

+#define RCC_APB1LENR_TIM12EN                   RCC_APB1LENR_TIM12EN_Msk

+#define RCC_APB1LENR_TIM13EN_Pos               (7U)

+#define RCC_APB1LENR_TIM13EN_Msk               (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */

+#define RCC_APB1LENR_TIM13EN                   RCC_APB1LENR_TIM13EN_Msk

+#define RCC_APB1LENR_TIM14EN_Pos               (8U)

+#define RCC_APB1LENR_TIM14EN_Msk               (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */

+#define RCC_APB1LENR_TIM14EN                   RCC_APB1LENR_TIM14EN_Msk

+#define RCC_APB1LENR_LPTIM1EN_Pos              (9U)

+#define RCC_APB1LENR_LPTIM1EN_Msk              (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */

+#define RCC_APB1LENR_LPTIM1EN                  RCC_APB1LENR_LPTIM1EN_Msk

+

+#define RCC_APB1LENR_WWDG2EN_Pos               (11U)

+#define RCC_APB1LENR_WWDG2EN_Msk               (0x1UL << RCC_APB1LENR_WWDG2EN_Pos) /*!< 0x00000800 */

+#define RCC_APB1LENR_WWDG2EN                   RCC_APB1LENR_WWDG2EN_Msk

+

+#define RCC_APB1LENR_SPI2EN_Pos                (14U)

+#define RCC_APB1LENR_SPI2EN_Msk                (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */

+#define RCC_APB1LENR_SPI2EN                    RCC_APB1LENR_SPI2EN_Msk

+#define RCC_APB1LENR_SPI3EN_Pos                (15U)

+#define RCC_APB1LENR_SPI3EN_Msk                (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */

+#define RCC_APB1LENR_SPI3EN                    RCC_APB1LENR_SPI3EN_Msk

+#define RCC_APB1LENR_SPDIFRXEN_Pos             (16U)

+#define RCC_APB1LENR_SPDIFRXEN_Msk             (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */

+#define RCC_APB1LENR_SPDIFRXEN                 RCC_APB1LENR_SPDIFRXEN_Msk

+#define RCC_APB1LENR_USART2EN_Pos              (17U)

+#define RCC_APB1LENR_USART2EN_Msk              (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */

+#define RCC_APB1LENR_USART2EN                  RCC_APB1LENR_USART2EN_Msk

+#define RCC_APB1LENR_USART3EN_Pos              (18U)

+#define RCC_APB1LENR_USART3EN_Msk              (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */

+#define RCC_APB1LENR_USART3EN                  RCC_APB1LENR_USART3EN_Msk

+#define RCC_APB1LENR_UART4EN_Pos               (19U)

+#define RCC_APB1LENR_UART4EN_Msk               (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */

+#define RCC_APB1LENR_UART4EN                   RCC_APB1LENR_UART4EN_Msk

+#define RCC_APB1LENR_UART5EN_Pos               (20U)

+#define RCC_APB1LENR_UART5EN_Msk               (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */

+#define RCC_APB1LENR_UART5EN                   RCC_APB1LENR_UART5EN_Msk

+#define RCC_APB1LENR_I2C1EN_Pos                (21U)

+#define RCC_APB1LENR_I2C1EN_Msk                (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */

+#define RCC_APB1LENR_I2C1EN                    RCC_APB1LENR_I2C1EN_Msk

+#define RCC_APB1LENR_I2C2EN_Pos                (22U)

+#define RCC_APB1LENR_I2C2EN_Msk                (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */

+#define RCC_APB1LENR_I2C2EN                    RCC_APB1LENR_I2C2EN_Msk

+#define RCC_APB1LENR_I2C3EN_Pos                (23U)

+#define RCC_APB1LENR_I2C3EN_Msk                (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */

+#define RCC_APB1LENR_I2C3EN                    RCC_APB1LENR_I2C3EN_Msk

+#define RCC_APB1LENR_CECEN_Pos                 (27U)

+#define RCC_APB1LENR_CECEN_Msk                 (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */

+#define RCC_APB1LENR_CECEN                     RCC_APB1LENR_CECEN_Msk

+#define RCC_APB1LENR_DAC12EN_Pos               (29U)

+#define RCC_APB1LENR_DAC12EN_Msk               (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */

+#define RCC_APB1LENR_DAC12EN                   RCC_APB1LENR_DAC12EN_Msk

+#define RCC_APB1LENR_UART7EN_Pos               (30U)

+#define RCC_APB1LENR_UART7EN_Msk               (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */

+#define RCC_APB1LENR_UART7EN                   RCC_APB1LENR_UART7EN_Msk

+#define RCC_APB1LENR_UART8EN_Pos               (31U)

+#define RCC_APB1LENR_UART8EN_Msk               (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */

+#define RCC_APB1LENR_UART8EN                   RCC_APB1LENR_UART8EN_Msk

+

+/* Legacy define */

+#define RCC_APB1LENR_HDMICECEN_Pos             RCC_APB1LENR_CECEN_Pos

+#define RCC_APB1LENR_HDMICECEN_Msk             RCC_APB1LENR_CECEN_Msk

+#define RCC_APB1LENR_HDMICECEN                 RCC_APB1LENR_CECEN

+/********************  Bit definition for RCC_APB1HENR register  ******************/

+#define RCC_APB1HENR_CRSEN_Pos                 (1U)

+#define RCC_APB1HENR_CRSEN_Msk                 (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1HENR_CRSEN                     RCC_APB1HENR_CRSEN_Msk

+#define RCC_APB1HENR_SWPMIEN_Pos               (2U)

+#define RCC_APB1HENR_SWPMIEN_Msk               (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1HENR_SWPMIEN                   RCC_APB1HENR_SWPMIEN_Msk

+#define RCC_APB1HENR_OPAMPEN_Pos               (4U)

+#define RCC_APB1HENR_OPAMPEN_Msk               (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1HENR_OPAMPEN                   RCC_APB1HENR_OPAMPEN_Msk

+#define RCC_APB1HENR_MDIOSEN_Pos               (5U)

+#define RCC_APB1HENR_MDIOSEN_Msk               (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1HENR_MDIOSEN                   RCC_APB1HENR_MDIOSEN_Msk

+#define RCC_APB1HENR_FDCANEN_Pos               (8U)

+#define RCC_APB1HENR_FDCANEN_Msk               (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1HENR_FDCANEN                   RCC_APB1HENR_FDCANEN_Msk

+

+/********************  Bit definition for RCC_APB2ENR register  ******************/

+#define RCC_APB2ENR_TIM1EN_Pos                 (0U)

+#define RCC_APB2ENR_TIM1EN_Msk                 (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */

+#define RCC_APB2ENR_TIM1EN                     RCC_APB2ENR_TIM1EN_Msk

+#define RCC_APB2ENR_TIM8EN_Pos                 (1U)

+#define RCC_APB2ENR_TIM8EN_Msk                 (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */

+#define RCC_APB2ENR_TIM8EN                     RCC_APB2ENR_TIM8EN_Msk

+#define RCC_APB2ENR_USART1EN_Pos               (4U)

+#define RCC_APB2ENR_USART1EN_Msk               (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */

+#define RCC_APB2ENR_USART1EN                   RCC_APB2ENR_USART1EN_Msk

+#define RCC_APB2ENR_USART6EN_Pos               (5U)

+#define RCC_APB2ENR_USART6EN_Msk               (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */

+#define RCC_APB2ENR_USART6EN                   RCC_APB2ENR_USART6EN_Msk

+#define RCC_APB2ENR_SPI1EN_Pos                 (12U)

+#define RCC_APB2ENR_SPI1EN_Msk                 (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */

+#define RCC_APB2ENR_SPI1EN                     RCC_APB2ENR_SPI1EN_Msk

+#define RCC_APB2ENR_SPI4EN_Pos                 (13U)

+#define RCC_APB2ENR_SPI4EN_Msk                 (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */

+#define RCC_APB2ENR_SPI4EN                     RCC_APB2ENR_SPI4EN_Msk

+#define RCC_APB2ENR_TIM15EN_Pos                (16U)

+#define RCC_APB2ENR_TIM15EN_Msk                (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */

+#define RCC_APB2ENR_TIM15EN                    RCC_APB2ENR_TIM15EN_Msk

+#define RCC_APB2ENR_TIM16EN_Pos                (17U)

+#define RCC_APB2ENR_TIM16EN_Msk                (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */

+#define RCC_APB2ENR_TIM16EN                    RCC_APB2ENR_TIM16EN_Msk

+#define RCC_APB2ENR_TIM17EN_Pos                (18U)

+#define RCC_APB2ENR_TIM17EN_Msk                (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */

+#define RCC_APB2ENR_TIM17EN                    RCC_APB2ENR_TIM17EN_Msk

+#define RCC_APB2ENR_SPI5EN_Pos                 (20U)

+#define RCC_APB2ENR_SPI5EN_Msk                 (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */

+#define RCC_APB2ENR_SPI5EN                     RCC_APB2ENR_SPI5EN_Msk

+#define RCC_APB2ENR_SAI1EN_Pos                 (22U)

+#define RCC_APB2ENR_SAI1EN_Msk                 (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */

+#define RCC_APB2ENR_SAI1EN                     RCC_APB2ENR_SAI1EN_Msk

+#define RCC_APB2ENR_SAI2EN_Pos                 (23U)

+#define RCC_APB2ENR_SAI2EN_Msk                 (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */

+#define RCC_APB2ENR_SAI2EN                     RCC_APB2ENR_SAI2EN_Msk

+#define RCC_APB2ENR_SAI3EN_Pos                 (24U)

+#define RCC_APB2ENR_SAI3EN_Msk                 (0x1UL << RCC_APB2ENR_SAI3EN_Pos) /*!< 0x01000000 */

+#define RCC_APB2ENR_SAI3EN                     RCC_APB2ENR_SAI3EN_Msk

+#define RCC_APB2ENR_DFSDM1EN_Pos               (28U)

+#define RCC_APB2ENR_DFSDM1EN_Msk               (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x10000000 */

+#define RCC_APB2ENR_DFSDM1EN                   RCC_APB2ENR_DFSDM1EN_Msk

+#define RCC_APB2ENR_HRTIMEN_Pos                (29U)

+#define RCC_APB2ENR_HRTIMEN_Msk                (0x1UL << RCC_APB2ENR_HRTIMEN_Pos) /*!< 0x20000000 */

+#define RCC_APB2ENR_HRTIMEN                    RCC_APB2ENR_HRTIMEN_Msk

+

+/********************  Bit definition for RCC_APB4ENR register  ******************/

+#define RCC_APB4ENR_SYSCFGEN_Pos               (1U)

+#define RCC_APB4ENR_SYSCFGEN_Msk               (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */

+#define RCC_APB4ENR_SYSCFGEN                   RCC_APB4ENR_SYSCFGEN_Msk

+#define RCC_APB4ENR_LPUART1EN_Pos              (3U)

+#define RCC_APB4ENR_LPUART1EN_Msk              (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */

+#define RCC_APB4ENR_LPUART1EN                  RCC_APB4ENR_LPUART1EN_Msk

+#define RCC_APB4ENR_SPI6EN_Pos                 (5U)

+#define RCC_APB4ENR_SPI6EN_Msk                 (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */

+#define RCC_APB4ENR_SPI6EN                     RCC_APB4ENR_SPI6EN_Msk

+#define RCC_APB4ENR_I2C4EN_Pos                 (7U)

+#define RCC_APB4ENR_I2C4EN_Msk                 (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */

+#define RCC_APB4ENR_I2C4EN                     RCC_APB4ENR_I2C4EN_Msk

+#define RCC_APB4ENR_LPTIM2EN_Pos               (9U)

+#define RCC_APB4ENR_LPTIM2EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */

+#define RCC_APB4ENR_LPTIM2EN                   RCC_APB4ENR_LPTIM2EN_Msk

+#define RCC_APB4ENR_LPTIM3EN_Pos               (10U)

+#define RCC_APB4ENR_LPTIM3EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */

+#define RCC_APB4ENR_LPTIM3EN                   RCC_APB4ENR_LPTIM3EN_Msk

+#define RCC_APB4ENR_LPTIM4EN_Pos               (11U)

+#define RCC_APB4ENR_LPTIM4EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos) /*!< 0x00000800 */

+#define RCC_APB4ENR_LPTIM4EN                   RCC_APB4ENR_LPTIM4EN_Msk

+#define RCC_APB4ENR_LPTIM5EN_Pos               (12U)

+#define RCC_APB4ENR_LPTIM5EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos) /*!< 0x00001000 */

+#define RCC_APB4ENR_LPTIM5EN                   RCC_APB4ENR_LPTIM5EN_Msk

+#define RCC_APB4ENR_COMP12EN_Pos               (14U)

+#define RCC_APB4ENR_COMP12EN_Msk               (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */

+#define RCC_APB4ENR_COMP12EN                   RCC_APB4ENR_COMP12EN_Msk

+#define RCC_APB4ENR_VREFEN_Pos                 (15U)

+#define RCC_APB4ENR_VREFEN_Msk                 (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */

+#define RCC_APB4ENR_VREFEN                     RCC_APB4ENR_VREFEN_Msk

+#define RCC_APB4ENR_RTCAPBEN_Pos               (16U)

+#define RCC_APB4ENR_RTCAPBEN_Msk               (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */

+#define RCC_APB4ENR_RTCAPBEN                   RCC_APB4ENR_RTCAPBEN_Msk

+#define RCC_APB4ENR_SAI4EN_Pos                 (21U)

+#define RCC_APB4ENR_SAI4EN_Msk                 (0x1UL << RCC_APB4ENR_SAI4EN_Pos) /*!< 0x00200000 */

+#define RCC_APB4ENR_SAI4EN                     RCC_APB4ENR_SAI4EN_Msk

+

+

+/********************  Bit definition for RCC_AHB3RSTR register  ***************/

+#define RCC_AHB3RSTR_MDMARST_Pos               (0U)

+#define RCC_AHB3RSTR_MDMARST_Msk               (0x1UL << RCC_AHB3RSTR_MDMARST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB3RSTR_MDMARST                   RCC_AHB3RSTR_MDMARST_Msk

+#define RCC_AHB3RSTR_DMA2DRST_Pos              (4U)

+#define RCC_AHB3RSTR_DMA2DRST_Msk              (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos)     /*!< 0x00000010 */

+#define RCC_AHB3RSTR_DMA2DRST                  RCC_AHB3RSTR_DMA2DRST_Msk

+#define RCC_AHB3RSTR_JPGDECRST_Pos             (5U)

+#define RCC_AHB3RSTR_JPGDECRST_Msk             (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos)    /*!< 0x00000020 */

+#define RCC_AHB3RSTR_JPGDECRST                 RCC_AHB3RSTR_JPGDECRST_Msk

+#define RCC_AHB3RSTR_FMCRST_Pos                (12U)

+#define RCC_AHB3RSTR_FMCRST_Msk                (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)      /*!< 0x00001000 */

+#define RCC_AHB3RSTR_FMCRST                    RCC_AHB3RSTR_FMCRST_Msk

+#define RCC_AHB3RSTR_QSPIRST_Pos               (14U)

+#define RCC_AHB3RSTR_QSPIRST_Msk               (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)     /*!< 0x00004000 */

+#define RCC_AHB3RSTR_QSPIRST                   RCC_AHB3RSTR_QSPIRST_Msk

+#define RCC_AHB3RSTR_SDMMC1RST_Pos             (16U)

+#define RCC_AHB3RSTR_SDMMC1RST_Msk             (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos)   /*!< 0x00010000 */

+#define RCC_AHB3RSTR_SDMMC1RST                 RCC_AHB3RSTR_SDMMC1RST_Msk

+

+

+/********************  Bit definition for RCC_AHB1RSTR register  ***************/

+#define RCC_AHB1RSTR_DMA1RST_Pos               (0U)

+#define RCC_AHB1RSTR_DMA1RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB1RSTR_DMA1RST                   RCC_AHB1RSTR_DMA1RST_Msk

+#define RCC_AHB1RSTR_DMA2RST_Pos               (1U)

+#define RCC_AHB1RSTR_DMA2RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)      /*!< 0x00000002 */

+#define RCC_AHB1RSTR_DMA2RST                   RCC_AHB1RSTR_DMA2RST_Msk

+#define RCC_AHB1RSTR_ADC12RST_Pos              (5U)

+#define RCC_AHB1RSTR_ADC12RST_Msk              (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)     /*!< 0x00000020 */

+#define RCC_AHB1RSTR_ADC12RST                  RCC_AHB1RSTR_ADC12RST_Msk

+#define RCC_AHB1RSTR_ARTRST_Pos                (14U)

+#define RCC_AHB1RSTR_ARTRST_Msk                (0x1UL << RCC_AHB1RSTR_ARTRST_Pos)       /*!< 0x00004000 */

+#define RCC_AHB1RSTR_ARTRST                    RCC_AHB1RSTR_ARTRST_Msk

+#define RCC_AHB1RSTR_ETH1MACRST_Pos            (15U)

+#define RCC_AHB1RSTR_ETH1MACRST_Msk            (0x1UL << RCC_AHB1RSTR_ETH1MACRST_Pos)   /*!< 0x00008000 */

+#define RCC_AHB1RSTR_ETH1MACRST                RCC_AHB1RSTR_ETH1MACRST_Msk

+#define RCC_AHB1RSTR_USB1OTGHSRST_Pos          (25U)

+#define RCC_AHB1RSTR_USB1OTGHSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */

+#define RCC_AHB1RSTR_USB1OTGHSRST              RCC_AHB1RSTR_USB1OTGHSRST_Msk

+#define RCC_AHB1RSTR_USB2OTGFSRST_Pos          (27U)

+#define RCC_AHB1RSTR_USB2OTGFSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB2OTGFSRST_Pos) /*!< 0x08000000 */

+#define RCC_AHB1RSTR_USB2OTGFSRST              RCC_AHB1RSTR_USB2OTGFSRST_Msk

+

+/* Legacy define */

+#define RCC_AHB1RSTR_USB2OTGHSRST_Pos          RCC_AHB1RSTR_USB2OTGFSRST_Pos

+#define RCC_AHB1RSTR_USB2OTGHSRST_Msk          RCC_AHB1RSTR_USB2OTGFSRST_Msk

+#define RCC_AHB1RSTR_USB2OTGHSRST              RCC_AHB1RSTR_USB2OTGFSRST

+

+/********************  Bit definition for RCC_AHB2RSTR register  ***************/

+#define RCC_AHB2RSTR_DCMIRST_Pos               (0U)

+#define RCC_AHB2RSTR_DCMIRST_Msk               (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)       /*!< 0x00000001 */

+#define RCC_AHB2RSTR_DCMIRST                   RCC_AHB2RSTR_DCMIRST_Msk

+#define RCC_AHB2RSTR_RNGRST_Pos                (6U)

+#define RCC_AHB2RSTR_RNGRST_Msk                (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)        /*!< 0x00000040 */

+#define RCC_AHB2RSTR_RNGRST                    RCC_AHB2RSTR_RNGRST_Msk

+#define RCC_AHB2RSTR_SDMMC2RST_Pos             (9U)

+#define RCC_AHB2RSTR_SDMMC2RST_Msk             (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)     /*!< 0x00000200 */

+#define RCC_AHB2RSTR_SDMMC2RST                 RCC_AHB2RSTR_SDMMC2RST_Msk

+

+/********************  Bit definition for RCC_AHB4RSTR register  ******************/

+#define RCC_AHB4RSTR_GPIOARST_Pos              (0U)

+#define RCC_AHB4RSTR_GPIOARST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB4RSTR_GPIOARST                  RCC_AHB4RSTR_GPIOARST_Msk

+#define RCC_AHB4RSTR_GPIOBRST_Pos              (1U)

+#define RCC_AHB4RSTR_GPIOBRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)      /*!< 0x00000002 */

+#define RCC_AHB4RSTR_GPIOBRST                  RCC_AHB4RSTR_GPIOBRST_Msk

+#define RCC_AHB4RSTR_GPIOCRST_Pos              (2U)

+#define RCC_AHB4RSTR_GPIOCRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)      /*!< 0x00000004 */

+#define RCC_AHB4RSTR_GPIOCRST                  RCC_AHB4RSTR_GPIOCRST_Msk

+#define RCC_AHB4RSTR_GPIODRST_Pos              (3U)

+#define RCC_AHB4RSTR_GPIODRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)      /*!< 0x00000008 */

+#define RCC_AHB4RSTR_GPIODRST                  RCC_AHB4RSTR_GPIODRST_Msk

+#define RCC_AHB4RSTR_GPIOERST_Pos              (4U)

+#define RCC_AHB4RSTR_GPIOERST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)      /*!< 0x00000010 */

+#define RCC_AHB4RSTR_GPIOERST                  RCC_AHB4RSTR_GPIOERST_Msk

+#define RCC_AHB4RSTR_GPIOFRST_Pos              (5U)

+#define RCC_AHB4RSTR_GPIOFRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)       /*!< 0x00000020 */

+#define RCC_AHB4RSTR_GPIOFRST                  RCC_AHB4RSTR_GPIOFRST_Msk

+#define RCC_AHB4RSTR_GPIOGRST_Pos              (6U)

+#define RCC_AHB4RSTR_GPIOGRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)       /*!< 0x00000040 */

+#define RCC_AHB4RSTR_GPIOGRST                  RCC_AHB4RSTR_GPIOGRST_Msk

+#define RCC_AHB4RSTR_GPIOHRST_Pos              (7U)

+#define RCC_AHB4RSTR_GPIOHRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)       /*!< 0x00000080 */

+#define RCC_AHB4RSTR_GPIOHRST                  RCC_AHB4RSTR_GPIOHRST_Msk

+#define RCC_AHB4RSTR_GPIOIRST_Pos              (8U)

+#define RCC_AHB4RSTR_GPIOIRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos)       /*!< 0x00000100 */

+#define RCC_AHB4RSTR_GPIOIRST                  RCC_AHB4RSTR_GPIOIRST_Msk

+#define RCC_AHB4RSTR_GPIOJRST_Pos              (9U)

+#define RCC_AHB4RSTR_GPIOJRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos)       /*!< 0x00000200 */

+#define RCC_AHB4RSTR_GPIOJRST                  RCC_AHB4RSTR_GPIOJRST_Msk

+#define RCC_AHB4RSTR_GPIOKRST_Pos              (10U)

+#define RCC_AHB4RSTR_GPIOKRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos)       /*!< 0x00000400 */

+#define RCC_AHB4RSTR_GPIOKRST                  RCC_AHB4RSTR_GPIOKRST_Msk

+#define RCC_AHB4RSTR_CRCRST_Pos                (19U)

+#define RCC_AHB4RSTR_CRCRST_Msk                (0x1UL << RCC_AHB4RSTR_CRCRST_Pos)         /*!< 0x00080000 */

+#define RCC_AHB4RSTR_CRCRST                    RCC_AHB4RSTR_CRCRST_Msk

+#define RCC_AHB4RSTR_BDMARST_Pos               (21U)

+#define RCC_AHB4RSTR_BDMARST_Msk               (0x1UL << RCC_AHB4RSTR_BDMARST_Pos)        /*!< 0x00200000 */

+#define RCC_AHB4RSTR_BDMARST                   RCC_AHB4RSTR_BDMARST_Msk

+#define RCC_AHB4RSTR_ADC3RST_Pos               (24U)

+#define RCC_AHB4RSTR_ADC3RST_Msk               (0x1UL << RCC_AHB4RSTR_ADC3RST_Pos)        /*!< 0x01000000 */

+#define RCC_AHB4RSTR_ADC3RST                   RCC_AHB4RSTR_ADC3RST_Msk

+#define RCC_AHB4RSTR_HSEMRST_Pos               (25U)

+#define RCC_AHB4RSTR_HSEMRST_Msk               (0x1UL << RCC_AHB4RSTR_HSEMRST_Pos)        /*!< 0x02000000 */

+#define RCC_AHB4RSTR_HSEMRST                   RCC_AHB4RSTR_HSEMRST_Msk

+

+

+/********************  Bit definition for RCC_APB3RSTR register  ******************/

+#define RCC_APB3RSTR_LTDCRST_Pos               (3U)

+#define RCC_APB3RSTR_LTDCRST_Msk               (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */

+#define RCC_APB3RSTR_LTDCRST                   RCC_APB3RSTR_LTDCRST_Msk

+#define RCC_APB3RSTR_DSIRST_Pos                (4U)

+#define RCC_APB3RSTR_DSIRST_Msk                (0x1UL << RCC_APB3RSTR_DSIRST_Pos) /*!< 0x00000010 */

+#define RCC_APB3RSTR_DSIRST                    RCC_APB3RSTR_DSIRST_Msk

+

+/********************  Bit definition for RCC_APB1LRSTR register  ******************/

+

+#define RCC_APB1LRSTR_TIM2RST_Pos              (0U)

+#define RCC_APB1LRSTR_TIM2RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */

+#define RCC_APB1LRSTR_TIM2RST                  RCC_APB1LRSTR_TIM2RST_Msk

+#define RCC_APB1LRSTR_TIM3RST_Pos              (1U)

+#define RCC_APB1LRSTR_TIM3RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */

+#define RCC_APB1LRSTR_TIM3RST                  RCC_APB1LRSTR_TIM3RST_Msk

+#define RCC_APB1LRSTR_TIM4RST_Pos              (2U)

+#define RCC_APB1LRSTR_TIM4RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */

+#define RCC_APB1LRSTR_TIM4RST                  RCC_APB1LRSTR_TIM4RST_Msk

+#define RCC_APB1LRSTR_TIM5RST_Pos              (3U)

+#define RCC_APB1LRSTR_TIM5RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */

+#define RCC_APB1LRSTR_TIM5RST                  RCC_APB1LRSTR_TIM5RST_Msk

+#define RCC_APB1LRSTR_TIM6RST_Pos              (4U)

+#define RCC_APB1LRSTR_TIM6RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */

+#define RCC_APB1LRSTR_TIM6RST                  RCC_APB1LRSTR_TIM6RST_Msk

+#define RCC_APB1LRSTR_TIM7RST_Pos              (5U)

+#define RCC_APB1LRSTR_TIM7RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */

+#define RCC_APB1LRSTR_TIM7RST                  RCC_APB1LRSTR_TIM7RST_Msk

+#define RCC_APB1LRSTR_TIM12RST_Pos             (6U)

+#define RCC_APB1LRSTR_TIM12RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */

+#define RCC_APB1LRSTR_TIM12RST                 RCC_APB1LRSTR_TIM12RST_Msk

+#define RCC_APB1LRSTR_TIM13RST_Pos             (7U)

+#define RCC_APB1LRSTR_TIM13RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */

+#define RCC_APB1LRSTR_TIM13RST                 RCC_APB1LRSTR_TIM13RST_Msk

+#define RCC_APB1LRSTR_TIM14RST_Pos             (8U)

+#define RCC_APB1LRSTR_TIM14RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */

+#define RCC_APB1LRSTR_TIM14RST                 RCC_APB1LRSTR_TIM14RST_Msk

+#define RCC_APB1LRSTR_LPTIM1RST_Pos            (9U)

+#define RCC_APB1LRSTR_LPTIM1RST_Msk            (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */

+#define RCC_APB1LRSTR_LPTIM1RST                RCC_APB1LRSTR_LPTIM1RST_Msk

+#define RCC_APB1LRSTR_SPI2RST_Pos              (14U)

+#define RCC_APB1LRSTR_SPI2RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */

+#define RCC_APB1LRSTR_SPI2RST                  RCC_APB1LRSTR_SPI2RST_Msk

+#define RCC_APB1LRSTR_SPI3RST_Pos              (15U)

+#define RCC_APB1LRSTR_SPI3RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */

+#define RCC_APB1LRSTR_SPI3RST                  RCC_APB1LRSTR_SPI3RST_Msk

+#define RCC_APB1LRSTR_SPDIFRXRST_Pos           (16U)

+#define RCC_APB1LRSTR_SPDIFRXRST_Msk           (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */

+#define RCC_APB1LRSTR_SPDIFRXRST               RCC_APB1LRSTR_SPDIFRXRST_Msk

+#define RCC_APB1LRSTR_USART2RST_Pos            (17U)

+#define RCC_APB1LRSTR_USART2RST_Msk            (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */

+#define RCC_APB1LRSTR_USART2RST                RCC_APB1LRSTR_USART2RST_Msk

+#define RCC_APB1LRSTR_USART3RST_Pos            (18U)

+#define RCC_APB1LRSTR_USART3RST_Msk            (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */

+#define RCC_APB1LRSTR_USART3RST                RCC_APB1LRSTR_USART3RST_Msk

+#define RCC_APB1LRSTR_UART4RST_Pos             (19U)

+#define RCC_APB1LRSTR_UART4RST_Msk             (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */

+#define RCC_APB1LRSTR_UART4RST                 RCC_APB1LRSTR_UART4RST_Msk

+#define RCC_APB1LRSTR_UART5RST_Pos             (20U)

+#define RCC_APB1LRSTR_UART5RST_Msk             (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */

+#define RCC_APB1LRSTR_UART5RST                 RCC_APB1LRSTR_UART5RST_Msk

+#define RCC_APB1LRSTR_I2C1RST_Pos              (21U)

+#define RCC_APB1LRSTR_I2C1RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */

+#define RCC_APB1LRSTR_I2C1RST                  RCC_APB1LRSTR_I2C1RST_Msk

+#define RCC_APB1LRSTR_I2C2RST_Pos              (22U)

+#define RCC_APB1LRSTR_I2C2RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */

+#define RCC_APB1LRSTR_I2C2RST                  RCC_APB1LRSTR_I2C2RST_Msk

+#define RCC_APB1LRSTR_I2C3RST_Pos              (23U)

+#define RCC_APB1LRSTR_I2C3RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */

+#define RCC_APB1LRSTR_I2C3RST                  RCC_APB1LRSTR_I2C3RST_Msk

+#define RCC_APB1LRSTR_CECRST_Pos               (27U)

+#define RCC_APB1LRSTR_CECRST_Msk               (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */

+#define RCC_APB1LRSTR_CECRST                   RCC_APB1LRSTR_CECRST_Msk

+#define RCC_APB1LRSTR_DAC12RST_Pos             (29U)

+#define RCC_APB1LRSTR_DAC12RST_Msk             (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */

+#define RCC_APB1LRSTR_DAC12RST                 RCC_APB1LRSTR_DAC12RST_Msk

+#define RCC_APB1LRSTR_UART7RST_Pos             (30U)

+#define RCC_APB1LRSTR_UART7RST_Msk             (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */

+#define RCC_APB1LRSTR_UART7RST                 RCC_APB1LRSTR_UART7RST_Msk

+#define RCC_APB1LRSTR_UART8RST_Pos             (31U)

+#define RCC_APB1LRSTR_UART8RST_Msk             (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */

+#define RCC_APB1LRSTR_UART8RST                 RCC_APB1LRSTR_UART8RST_Msk

+

+/* Legacy define */

+#define RCC_APB1LRSTR_HDMICECRST_Pos           RCC_APB1LRSTR_CECRST_Pos

+#define RCC_APB1LRSTR_HDMICECRST_Msk           RCC_APB1LRSTR_CECRST_Msk

+#define RCC_APB1LRSTR_HDMICECRST               RCC_APB1LRSTR_CECRST

+/********************  Bit definition for RCC_APB1HRSTR register  ******************/

+#define RCC_APB1HRSTR_CRSRST_Pos               (1U)

+#define RCC_APB1HRSTR_CRSRST_Msk               (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */

+#define RCC_APB1HRSTR_CRSRST                   RCC_APB1HRSTR_CRSRST_Msk

+#define RCC_APB1HRSTR_SWPMIRST_Pos             (2U)

+#define RCC_APB1HRSTR_SWPMIRST_Msk             (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */

+#define RCC_APB1HRSTR_SWPMIRST                 RCC_APB1HRSTR_SWPMIRST_Msk

+#define RCC_APB1HRSTR_OPAMPRST_Pos             (4U)

+#define RCC_APB1HRSTR_OPAMPRST_Msk             (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */

+#define RCC_APB1HRSTR_OPAMPRST                 RCC_APB1HRSTR_OPAMPRST_Msk

+#define RCC_APB1HRSTR_MDIOSRST_Pos             (5U)

+#define RCC_APB1HRSTR_MDIOSRST_Msk             (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */

+#define RCC_APB1HRSTR_MDIOSRST                 RCC_APB1HRSTR_MDIOSRST_Msk

+#define RCC_APB1HRSTR_FDCANRST_Pos             (8U)

+#define RCC_APB1HRSTR_FDCANRST_Msk             (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */

+#define RCC_APB1HRSTR_FDCANRST                 RCC_APB1HRSTR_FDCANRST_Msk

+

+/********************  Bit definition for RCC_APB2RSTR register  ******************/

+#define RCC_APB2RSTR_TIM1RST_Pos               (0U)

+#define RCC_APB2RSTR_TIM1RST_Msk               (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */

+#define RCC_APB2RSTR_TIM1RST                   RCC_APB2RSTR_TIM1RST_Msk

+#define RCC_APB2RSTR_TIM8RST_Pos               (1U)

+#define RCC_APB2RSTR_TIM8RST_Msk               (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */

+#define RCC_APB2RSTR_TIM8RST                   RCC_APB2RSTR_TIM8RST_Msk

+#define RCC_APB2RSTR_USART1RST_Pos             (4U)

+#define RCC_APB2RSTR_USART1RST_Msk             (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */

+#define RCC_APB2RSTR_USART1RST                 RCC_APB2RSTR_USART1RST_Msk

+#define RCC_APB2RSTR_USART6RST_Pos             (5U)

+#define RCC_APB2RSTR_USART6RST_Msk             (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */

+#define RCC_APB2RSTR_USART6RST                 RCC_APB2RSTR_USART6RST_Msk

+#define RCC_APB2RSTR_SPI1RST_Pos               (12U)

+#define RCC_APB2RSTR_SPI1RST_Msk               (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */

+#define RCC_APB2RSTR_SPI1RST                   RCC_APB2RSTR_SPI1RST_Msk

+#define RCC_APB2RSTR_SPI4RST_Pos               (13U)

+#define RCC_APB2RSTR_SPI4RST_Msk               (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */

+#define RCC_APB2RSTR_SPI4RST                   RCC_APB2RSTR_SPI4RST_Msk

+#define RCC_APB2RSTR_TIM15RST_Pos              (16U)

+#define RCC_APB2RSTR_TIM15RST_Msk              (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */

+#define RCC_APB2RSTR_TIM15RST                  RCC_APB2RSTR_TIM15RST_Msk

+#define RCC_APB2RSTR_TIM16RST_Pos              (17U)

+#define RCC_APB2RSTR_TIM16RST_Msk              (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */

+#define RCC_APB2RSTR_TIM16RST                  RCC_APB2RSTR_TIM16RST_Msk

+#define RCC_APB2RSTR_TIM17RST_Pos              (18U)

+#define RCC_APB2RSTR_TIM17RST_Msk              (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */

+#define RCC_APB2RSTR_TIM17RST                  RCC_APB2RSTR_TIM17RST_Msk

+#define RCC_APB2RSTR_SPI5RST_Pos               (20U)

+#define RCC_APB2RSTR_SPI5RST_Msk               (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */

+#define RCC_APB2RSTR_SPI5RST                   RCC_APB2RSTR_SPI5RST_Msk

+#define RCC_APB2RSTR_SAI1RST_Pos               (22U)

+#define RCC_APB2RSTR_SAI1RST_Msk               (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */

+#define RCC_APB2RSTR_SAI1RST                   RCC_APB2RSTR_SAI1RST_Msk

+#define RCC_APB2RSTR_SAI2RST_Pos               (23U)

+#define RCC_APB2RSTR_SAI2RST_Msk               (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */

+#define RCC_APB2RSTR_SAI2RST                   RCC_APB2RSTR_SAI2RST_Msk

+#define RCC_APB2RSTR_SAI3RST_Pos               (24U)

+#define RCC_APB2RSTR_SAI3RST_Msk               (0x1UL << RCC_APB2RSTR_SAI3RST_Pos) /*!< 0x01000000 */

+#define RCC_APB2RSTR_SAI3RST                   RCC_APB2RSTR_SAI3RST_Msk

+#define RCC_APB2RSTR_DFSDM1RST_Pos             (28U)

+#define RCC_APB2RSTR_DFSDM1RST_Msk             (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */

+#define RCC_APB2RSTR_DFSDM1RST                 RCC_APB2RSTR_DFSDM1RST_Msk

+#define RCC_APB2RSTR_HRTIMRST_Pos              (29U)

+#define RCC_APB2RSTR_HRTIMRST_Msk              (0x1UL << RCC_APB2RSTR_HRTIMRST_Pos) /*!< 0x20000000 */

+#define RCC_APB2RSTR_HRTIMRST                  RCC_APB2RSTR_HRTIMRST_Msk

+

+/********************  Bit definition for RCC_APB4RSTR register  ******************/

+#define RCC_APB4RSTR_SYSCFGRST_Pos             (1U)

+#define RCC_APB4RSTR_SYSCFGRST_Msk             (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */

+#define RCC_APB4RSTR_SYSCFGRST                 RCC_APB4RSTR_SYSCFGRST_Msk

+#define RCC_APB4RSTR_LPUART1RST_Pos            (3U)

+#define RCC_APB4RSTR_LPUART1RST_Msk            (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */

+#define RCC_APB4RSTR_LPUART1RST                RCC_APB4RSTR_LPUART1RST_Msk

+#define RCC_APB4RSTR_SPI6RST_Pos               (5U)

+#define RCC_APB4RSTR_SPI6RST_Msk               (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */

+#define RCC_APB4RSTR_SPI6RST                   RCC_APB4RSTR_SPI6RST_Msk

+#define RCC_APB4RSTR_I2C4RST_Pos               (7U)

+#define RCC_APB4RSTR_I2C4RST_Msk               (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */

+#define RCC_APB4RSTR_I2C4RST                   RCC_APB4RSTR_I2C4RST_Msk

+#define RCC_APB4RSTR_LPTIM2RST_Pos             (9U)

+#define RCC_APB4RSTR_LPTIM2RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */

+#define RCC_APB4RSTR_LPTIM2RST                 RCC_APB4RSTR_LPTIM2RST_Msk

+#define RCC_APB4RSTR_LPTIM3RST_Pos             (10U)

+#define RCC_APB4RSTR_LPTIM3RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */

+#define RCC_APB4RSTR_LPTIM3RST                 RCC_APB4RSTR_LPTIM3RST_Msk

+#define RCC_APB4RSTR_LPTIM4RST_Pos             (11U)

+#define RCC_APB4RSTR_LPTIM4RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos) /*!< 0x00000800 */

+#define RCC_APB4RSTR_LPTIM4RST                 RCC_APB4RSTR_LPTIM4RST_Msk

+#define RCC_APB4RSTR_LPTIM5RST_Pos             (12U)

+#define RCC_APB4RSTR_LPTIM5RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos) /*!< 0x00001000 */

+#define RCC_APB4RSTR_LPTIM5RST                 RCC_APB4RSTR_LPTIM5RST_Msk

+#define RCC_APB4RSTR_COMP12RST_Pos             (14U)

+#define RCC_APB4RSTR_COMP12RST_Msk             (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */

+#define RCC_APB4RSTR_COMP12RST                 RCC_APB4RSTR_COMP12RST_Msk

+#define RCC_APB4RSTR_VREFRST_Pos               (15U)

+#define RCC_APB4RSTR_VREFRST_Msk               (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */

+#define RCC_APB4RSTR_VREFRST                   RCC_APB4RSTR_VREFRST_Msk

+#define RCC_APB4RSTR_SAI4RST_Pos               (21U)

+#define RCC_APB4RSTR_SAI4RST_Msk               (0x1UL << RCC_APB4RSTR_SAI4RST_Pos) /*!< 0x00200000 */

+#define RCC_APB4RSTR_SAI4RST                   RCC_APB4RSTR_SAI4RST_Msk

+

+

+/********************  Bit definition for RCC_GCR register  ********************/

+#define RCC_GCR_WW1RSC_Pos                     (0U)

+#define RCC_GCR_WW1RSC_Msk                     (0x1UL << RCC_GCR_WW1RSC_Pos)   /*!< 0x00000001 */

+#define RCC_GCR_WW1RSC                         RCC_GCR_WW1RSC_Msk

+#define RCC_GCR_WW2RSC_Pos                     (1U)

+#define RCC_GCR_WW2RSC_Msk                     (0x1UL << RCC_GCR_WW2RSC_Pos)   /*!< 0x00000002 */

+#define RCC_GCR_WW2RSC                         RCC_GCR_WW2RSC_Msk

+#define RCC_GCR_BOOT_C1_Pos                    (2U)

+#define RCC_GCR_BOOT_C1_Msk                    (0x1UL << RCC_GCR_BOOT_C1_Pos)  /*!< 0x00000004 */

+#define RCC_GCR_BOOT_C1                        RCC_GCR_BOOT_C1_Msk

+#define RCC_GCR_BOOT_C2_Pos                    (3U)

+#define RCC_GCR_BOOT_C2_Msk                    (0x1UL << RCC_GCR_BOOT_C2_Pos)  /*!< 0x00000008 */

+#define RCC_GCR_BOOT_C2                        RCC_GCR_BOOT_C2_Msk

+

+/********************  Bit definition for RCC_D3AMR register  ********************/

+#define RCC_D3AMR_BDMAAMEN_Pos                 (0U)

+#define RCC_D3AMR_BDMAAMEN_Msk                 (0x1UL << RCC_D3AMR_BDMAAMEN_Pos) /*!< 0x00000001 */

+#define RCC_D3AMR_BDMAAMEN                     RCC_D3AMR_BDMAAMEN_Msk

+#define RCC_D3AMR_LPUART1AMEN_Pos              (3U)

+#define RCC_D3AMR_LPUART1AMEN_Msk              (0x1UL << RCC_D3AMR_LPUART1AMEN_Pos) /*!< 0x00000008 */

+#define RCC_D3AMR_LPUART1AMEN                  RCC_D3AMR_LPUART1AMEN_Msk

+#define RCC_D3AMR_SPI6AMEN_Pos                 (5U)

+#define RCC_D3AMR_SPI6AMEN_Msk                 (0x1UL << RCC_D3AMR_SPI6AMEN_Pos) /*!< 0x00000020 */

+#define RCC_D3AMR_SPI6AMEN                     RCC_D3AMR_SPI6AMEN_Msk

+#define RCC_D3AMR_I2C4AMEN_Pos                 (7U)

+#define RCC_D3AMR_I2C4AMEN_Msk                 (0x1UL << RCC_D3AMR_I2C4AMEN_Pos) /*!< 0x00000080 */

+#define RCC_D3AMR_I2C4AMEN                     RCC_D3AMR_I2C4AMEN_Msk

+#define RCC_D3AMR_LPTIM2AMEN_Pos               (9U)

+#define RCC_D3AMR_LPTIM2AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */

+#define RCC_D3AMR_LPTIM2AMEN                   RCC_D3AMR_LPTIM2AMEN_Msk

+#define RCC_D3AMR_LPTIM3AMEN_Pos               (10U)

+#define RCC_D3AMR_LPTIM3AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */

+#define RCC_D3AMR_LPTIM3AMEN                   RCC_D3AMR_LPTIM3AMEN_Msk

+#define RCC_D3AMR_LPTIM4AMEN_Pos               (11U)

+#define RCC_D3AMR_LPTIM4AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM4AMEN_Pos) /*!< 0x00000800 */

+#define RCC_D3AMR_LPTIM4AMEN                   RCC_D3AMR_LPTIM4AMEN_Msk

+#define RCC_D3AMR_LPTIM5AMEN_Pos               (12U)

+#define RCC_D3AMR_LPTIM5AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM5AMEN_Pos) /*!< 0x00001000 */

+#define RCC_D3AMR_LPTIM5AMEN                   RCC_D3AMR_LPTIM5AMEN_Msk

+#define RCC_D3AMR_COMP12AMEN_Pos               (14U)

+#define RCC_D3AMR_COMP12AMEN_Msk               (0x1UL << RCC_D3AMR_COMP12AMEN_Pos) /*!< 0x00004000 */

+#define RCC_D3AMR_COMP12AMEN                   RCC_D3AMR_COMP12AMEN_Msk

+#define RCC_D3AMR_VREFAMEN_Pos                 (15U)

+#define RCC_D3AMR_VREFAMEN_Msk                 (0x1UL << RCC_D3AMR_VREFAMEN_Pos) /*!< 0x00008000 */

+#define RCC_D3AMR_VREFAMEN                     RCC_D3AMR_VREFAMEN_Msk

+#define RCC_D3AMR_RTCAMEN_Pos                  (16U)

+#define RCC_D3AMR_RTCAMEN_Msk                  (0x1UL << RCC_D3AMR_RTCAMEN_Pos) /*!< 0x00010000 */

+#define RCC_D3AMR_RTCAMEN                      RCC_D3AMR_RTCAMEN_Msk

+#define RCC_D3AMR_CRCAMEN_Pos                  (19U)

+#define RCC_D3AMR_CRCAMEN_Msk                  (0x1UL << RCC_D3AMR_CRCAMEN_Pos) /*!< 0x00080000 */

+#define RCC_D3AMR_CRCAMEN                      RCC_D3AMR_CRCAMEN_Msk

+#define RCC_D3AMR_SAI4AMEN_Pos                 (21U)

+#define RCC_D3AMR_SAI4AMEN_Msk                 (0x1UL << RCC_D3AMR_SAI4AMEN_Pos) /*!< 0x00200000 */

+#define RCC_D3AMR_SAI4AMEN                     RCC_D3AMR_SAI4AMEN_Msk

+#define RCC_D3AMR_ADC3AMEN_Pos                 (24U)

+#define RCC_D3AMR_ADC3AMEN_Msk                 (0x1UL << RCC_D3AMR_ADC3AMEN_Pos) /*!< 0x01000000 */

+#define RCC_D3AMR_ADC3AMEN                     RCC_D3AMR_ADC3AMEN_Msk

+

+

+#define RCC_D3AMR_BKPRAMAMEN_Pos               (28U)

+#define RCC_D3AMR_BKPRAMAMEN_Msk               (0x1UL << RCC_D3AMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */

+#define RCC_D3AMR_BKPRAMAMEN                   RCC_D3AMR_BKPRAMAMEN_Msk

+#define RCC_D3AMR_SRAM4AMEN_Pos                (29U)

+#define RCC_D3AMR_SRAM4AMEN_Msk                (0x1UL << RCC_D3AMR_SRAM4AMEN_Pos) /*!< 0x20000000 */

+#define RCC_D3AMR_SRAM4AMEN                    RCC_D3AMR_SRAM4AMEN_Msk

+/********************  Bit definition for RCC_AHB3LPENR register  **************/

+#define RCC_AHB3LPENR_MDMALPEN_Pos             (0U)

+#define RCC_AHB3LPENR_MDMALPEN_Msk             (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos)         /*!< 0x00000001 */

+#define RCC_AHB3LPENR_MDMALPEN                 RCC_AHB3LPENR_MDMALPEN_Msk

+#define RCC_AHB3LPENR_DMA2DLPEN_Pos            (4U)

+#define RCC_AHB3LPENR_DMA2DLPEN_Msk            (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos)        /*!< 0x00000010 */

+#define RCC_AHB3LPENR_DMA2DLPEN                RCC_AHB3LPENR_DMA2DLPEN_Msk

+#define RCC_AHB3LPENR_JPGDECLPEN_Pos           (5U)

+#define RCC_AHB3LPENR_JPGDECLPEN_Msk           (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos)       /*!< 0x00000020 */

+#define RCC_AHB3LPENR_JPGDECLPEN               RCC_AHB3LPENR_JPGDECLPEN_Msk

+#define RCC_AHB3LPENR_FLASHLPEN_Pos            (8U)

+#define RCC_AHB3LPENR_FLASHLPEN_Msk            (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos)        /*!< 0x00000100 */

+#define RCC_AHB3LPENR_FLASHLPEN                RCC_AHB3LPENR_FLASHLPEN_Msk

+#define RCC_AHB3LPENR_FMCLPEN_Pos              (12U)

+#define RCC_AHB3LPENR_FMCLPEN_Msk              (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)          /*!< 0x00001000 */

+#define RCC_AHB3LPENR_FMCLPEN                  RCC_AHB3LPENR_FMCLPEN_Msk

+#define RCC_AHB3LPENR_QSPILPEN_Pos             (14U)

+#define RCC_AHB3LPENR_QSPILPEN_Msk             (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos)         /*!< 0x00004000 */

+#define RCC_AHB3LPENR_QSPILPEN                 RCC_AHB3LPENR_QSPILPEN_Msk

+#define RCC_AHB3LPENR_SDMMC1LPEN_Pos           (16U)

+#define RCC_AHB3LPENR_SDMMC1LPEN_Msk           (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos)       /*!< 0x00010000 */

+#define RCC_AHB3LPENR_SDMMC1LPEN               RCC_AHB3LPENR_SDMMC1LPEN_Msk

+#define RCC_AHB3LPENR_DTCM1LPEN_Pos            (28U)

+#define RCC_AHB3LPENR_DTCM1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos)        /*!< 0x10000000 */

+#define RCC_AHB3LPENR_DTCM1LPEN                RCC_AHB3LPENR_DTCM1LPEN_Msk

+#define RCC_AHB3LPENR_DTCM2LPEN_Pos            (29U)

+#define RCC_AHB3LPENR_DTCM2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos)        /*!< 0x20000000 */

+#define RCC_AHB3LPENR_DTCM2LPEN                RCC_AHB3LPENR_DTCM2LPEN_Msk

+#define RCC_AHB3LPENR_ITCMLPEN_Pos             (30U)

+#define RCC_AHB3LPENR_ITCMLPEN_Msk             (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos)         /*!< 0x40000000 */

+#define RCC_AHB3LPENR_ITCMLPEN                 RCC_AHB3LPENR_ITCMLPEN_Msk

+#define RCC_AHB3LPENR_AXISRAMLPEN_Pos          (31U)

+#define RCC_AHB3LPENR_AXISRAMLPEN_Msk          (0x1UL << RCC_AHB3LPENR_AXISRAMLPEN_Pos)      /*!< 0x80000000 */

+#define RCC_AHB3LPENR_AXISRAMLPEN              RCC_AHB3LPENR_AXISRAMLPEN_Msk

+

+

+/********************  Bit definition for RCC_AHB1LPENR register  ***************/

+#define RCC_AHB1LPENR_DMA1LPEN_Pos             (0U)

+#define RCC_AHB1LPENR_DMA1LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB1LPENR_DMA1LPEN                 RCC_AHB1LPENR_DMA1LPEN_Msk

+#define RCC_AHB1LPENR_DMA2LPEN_Pos             (1U)

+#define RCC_AHB1LPENR_DMA2LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */

+#define RCC_AHB1LPENR_DMA2LPEN                 RCC_AHB1LPENR_DMA2LPEN_Msk

+#define RCC_AHB1LPENR_ADC12LPEN_Pos            (5U)

+#define RCC_AHB1LPENR_ADC12LPEN_Msk            (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB1LPENR_ADC12LPEN                RCC_AHB1LPENR_ADC12LPEN_Msk

+#define RCC_AHB1LPENR_ARTLPEN_Pos              (14U)

+#define RCC_AHB1LPENR_ARTLPEN_Msk              (0x1UL << RCC_AHB1LPENR_ARTLPEN_Pos) /*!< 0x00004000 */

+#define RCC_AHB1LPENR_ARTLPEN                  RCC_AHB1LPENR_ARTLPEN_Msk

+#define RCC_AHB1LPENR_ETH1MACLPEN_Pos          (15U)

+#define RCC_AHB1LPENR_ETH1MACLPEN_Msk          (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) /*!< 0x00008000 */

+#define RCC_AHB1LPENR_ETH1MACLPEN              RCC_AHB1LPENR_ETH1MACLPEN_Msk

+#define RCC_AHB1LPENR_ETH1TXLPEN_Pos           (16U)

+#define RCC_AHB1LPENR_ETH1TXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00010000 */

+#define RCC_AHB1LPENR_ETH1TXLPEN               RCC_AHB1LPENR_ETH1TXLPEN_Msk

+#define RCC_AHB1LPENR_ETH1RXLPEN_Pos           (17U)

+#define RCC_AHB1LPENR_ETH1RXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00020000 */

+#define RCC_AHB1LPENR_ETH1RXLPEN               RCC_AHB1LPENR_ETH1RXLPEN_Msk

+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos        (25U)

+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */

+#define RCC_AHB1LPENR_USB1OTGHSLPEN            RCC_AHB1LPENR_USB1OTGHSLPEN_Msk

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos    (26U)

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN        RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGFSLPEN_Pos        (27U)

+#define RCC_AHB1LPENR_USB2OTGFSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB2OTGFSLPEN_Pos) /*!< 0x08000000 */

+#define RCC_AHB1LPENR_USB2OTGFSLPEN            RCC_AHB1LPENR_USB2OTGFSLPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos    (28U)

+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos) /*!< 0x10000000 */

+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN        RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk

+

+/* Legacy define */

+#define RCC_AHB1LPENR_USB2OTGHSLPEN_Pos        RCC_AHB1LPENR_USB2OTGFSLPEN_Pos

+#define RCC_AHB1LPENR_USB2OTGHSLPEN_Msk        RCC_AHB1LPENR_USB2OTGFSLPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGHSLPEN            RCC_AHB1LPENR_USB2OTGFSLPEN

+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Pos    RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos

+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Msk    RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN        RCC_AHB1LPENR_USB2OTGFSULPILPEN

+

+/********************  Bit definition for RCC_AHB2LPENR register  ***************/

+#define RCC_AHB2LPENR_DCMILPEN_Pos             (0U)

+#define RCC_AHB2LPENR_DCMILPEN_Msk             (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB2LPENR_DCMILPEN                 RCC_AHB2LPENR_DCMILPEN_Msk

+#define RCC_AHB2LPENR_RNGLPEN_Pos              (6U)

+#define RCC_AHB2LPENR_RNGLPEN_Msk              (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */

+#define RCC_AHB2LPENR_RNGLPEN                  RCC_AHB2LPENR_RNGLPEN_Msk

+#define RCC_AHB2LPENR_SDMMC2LPEN_Pos           (9U)

+#define RCC_AHB2LPENR_SDMMC2LPEN_Msk           (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */

+#define RCC_AHB2LPENR_SDMMC2LPEN               RCC_AHB2LPENR_SDMMC2LPEN_Msk

+#define RCC_AHB2LPENR_SRAM1LPEN_Pos          (29U)

+#define RCC_AHB2LPENR_SRAM1LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos) /*!< 0x20000000 */

+#define RCC_AHB2LPENR_SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN_Msk

+#define RCC_AHB2LPENR_SRAM2LPEN_Pos          (30U)

+#define RCC_AHB2LPENR_SRAM2LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */

+#define RCC_AHB2LPENR_SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN_Msk

+#define RCC_AHB2LPENR_SRAM3LPEN_Pos          (31U)

+#define RCC_AHB2LPENR_SRAM3LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM3LPEN_Pos) /*!< 0x80000000 */

+#define RCC_AHB2LPENR_SRAM3LPEN              RCC_AHB2LPENR_SRAM3LPEN_Msk

+

+/* Legacy define */

+#define RCC_AHB2LPENR_D2SRAM1LPEN_Pos          RCC_AHB2LPENR_SRAM1LPEN_Pos

+#define RCC_AHB2LPENR_D2SRAM1LPEN_Msk          RCC_AHB2LPENR_SRAM1LPEN_Msk

+#define RCC_AHB2LPENR_D2SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN

+#define RCC_AHB2LPENR_D2SRAM2LPEN_Pos          RCC_AHB2LPENR_SRAM2LPEN_Pos

+#define RCC_AHB2LPENR_D2SRAM2LPEN_Msk          RCC_AHB2LPENR_SRAM2LPEN_Msk

+#define RCC_AHB2LPENR_D2SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN

+#define RCC_AHB2LPENR_D2SRAM3LPEN_Pos          RCC_AHB2LPENR_SRAM3LPEN_Pos

+#define RCC_AHB2LPENR_D2SRAM3LPEN_Msk          RCC_AHB2LPENR_SRAM3LPEN_Msk

+#define RCC_AHB2LPENR_D2SRAM3LPEN              RCC_AHB2LPENR_SRAM3LPEN

+

+/********************  Bit definition for RCC_AHB4LPENR register  ******************/

+#define RCC_AHB4LPENR_GPIOALPEN_Pos            (0U)

+#define RCC_AHB4LPENR_GPIOALPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB4LPENR_GPIOALPEN                RCC_AHB4LPENR_GPIOALPEN_Msk

+#define RCC_AHB4LPENR_GPIOBLPEN_Pos            (1U)

+#define RCC_AHB4LPENR_GPIOBLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */

+#define RCC_AHB4LPENR_GPIOBLPEN                RCC_AHB4LPENR_GPIOBLPEN_Msk

+#define RCC_AHB4LPENR_GPIOCLPEN_Pos            (2U)

+#define RCC_AHB4LPENR_GPIOCLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */

+#define RCC_AHB4LPENR_GPIOCLPEN                RCC_AHB4LPENR_GPIOCLPEN_Msk

+#define RCC_AHB4LPENR_GPIODLPEN_Pos            (3U)

+#define RCC_AHB4LPENR_GPIODLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */

+#define RCC_AHB4LPENR_GPIODLPEN                RCC_AHB4LPENR_GPIODLPEN_Msk

+#define RCC_AHB4LPENR_GPIOELPEN_Pos            (4U)

+#define RCC_AHB4LPENR_GPIOELPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */

+#define RCC_AHB4LPENR_GPIOELPEN                RCC_AHB4LPENR_GPIOELPEN_Msk

+#define RCC_AHB4LPENR_GPIOFLPEN_Pos            (5U)

+#define RCC_AHB4LPENR_GPIOFLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB4LPENR_GPIOFLPEN                RCC_AHB4LPENR_GPIOFLPEN_Msk

+#define RCC_AHB4LPENR_GPIOGLPEN_Pos            (6U)

+#define RCC_AHB4LPENR_GPIOGLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */

+#define RCC_AHB4LPENR_GPIOGLPEN                RCC_AHB4LPENR_GPIOGLPEN_Msk

+#define RCC_AHB4LPENR_GPIOHLPEN_Pos            (7U)

+#define RCC_AHB4LPENR_GPIOHLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */

+#define RCC_AHB4LPENR_GPIOHLPEN                RCC_AHB4LPENR_GPIOHLPEN_Msk

+#define RCC_AHB4LPENR_GPIOILPEN_Pos            (8U)

+#define RCC_AHB4LPENR_GPIOILPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */

+#define RCC_AHB4LPENR_GPIOILPEN                RCC_AHB4LPENR_GPIOILPEN_Msk

+#define RCC_AHB4LPENR_GPIOJLPEN_Pos            (9U)

+#define RCC_AHB4LPENR_GPIOJLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */

+#define RCC_AHB4LPENR_GPIOJLPEN                RCC_AHB4LPENR_GPIOJLPEN_Msk

+#define RCC_AHB4LPENR_GPIOKLPEN_Pos            (10U)

+#define RCC_AHB4LPENR_GPIOKLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */

+#define RCC_AHB4LPENR_GPIOKLPEN                RCC_AHB4LPENR_GPIOKLPEN_Msk

+#define RCC_AHB4LPENR_CRCLPEN_Pos              (19U)

+#define RCC_AHB4LPENR_CRCLPEN_Msk              (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */

+#define RCC_AHB4LPENR_CRCLPEN                  RCC_AHB4LPENR_CRCLPEN_Msk

+#define RCC_AHB4LPENR_BDMALPEN_Pos             (21U)

+#define RCC_AHB4LPENR_BDMALPEN_Msk             (0x1UL << RCC_AHB4LPENR_BDMALPEN_Pos) /*!< 0x00200000 */

+#define RCC_AHB4LPENR_BDMALPEN                 RCC_AHB4LPENR_BDMALPEN_Msk

+#define RCC_AHB4LPENR_ADC3LPEN_Pos             (24U)

+#define RCC_AHB4LPENR_ADC3LPEN_Msk             (0x1UL << RCC_AHB4LPENR_ADC3LPEN_Pos) /*!< 0x01000000 */

+#define RCC_AHB4LPENR_ADC3LPEN                 RCC_AHB4LPENR_ADC3LPEN_Msk

+#define RCC_AHB4LPENR_BKPRAMLPEN_Pos           (28U)

+#define RCC_AHB4LPENR_BKPRAMLPEN_Msk           (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */

+#define RCC_AHB4LPENR_BKPRAMLPEN               RCC_AHB4LPENR_BKPRAMLPEN_Msk

+#define RCC_AHB4LPENR_SRAM4LPEN_Pos            (29U)

+#define RCC_AHB4LPENR_SRAM4LPEN_Msk            (0x1UL << RCC_AHB4LPENR_SRAM4LPEN_Pos) /*!< 0x20000000 */

+#define RCC_AHB4LPENR_SRAM4LPEN                RCC_AHB4LPENR_SRAM4LPEN_Msk

+

+/* Legacy define */

+#define RCC_AHB4LPENR_D3SRAM1LPEN_Pos          RCC_AHB4LPENR_SRAM4LPEN_Pos

+#define RCC_AHB4LPENR_D3SRAM1LPEN_Msk          RCC_AHB4LPENR_SRAM4LPEN_Msk

+#define RCC_AHB4LPENR_D3SRAM1LPEN              RCC_AHB4LPENR_SRAM4LPEN

+/********************  Bit definition for RCC_APB3LPENR register  ******************/

+#define RCC_APB3LPENR_LTDCLPEN_Pos             (3U)

+#define RCC_APB3LPENR_LTDCLPEN_Msk             (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB3LPENR_LTDCLPEN                 RCC_APB3LPENR_LTDCLPEN_Msk

+#define RCC_APB3LPENR_DSILPEN_Pos              (4U)

+#define RCC_APB3LPENR_DSILPEN_Msk              (0x1UL << RCC_APB3LPENR_DSILPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB3LPENR_DSILPEN                  RCC_APB3LPENR_DSILPEN_Msk

+#define RCC_APB3LPENR_WWDG1LPEN_Pos            (6U)

+#define RCC_APB3LPENR_WWDG1LPEN_Msk            (0x1UL << RCC_APB3LPENR_WWDG1LPEN_Pos) /*!< 0x00000040 */

+#define RCC_APB3LPENR_WWDG1LPEN                RCC_APB3LPENR_WWDG1LPEN_Msk

+

+/********************  Bit definition for RCC_APB1LLPENR register  ******************/

+

+#define RCC_APB1LLPENR_TIM2LPEN_Pos            (0U)

+#define RCC_APB1LLPENR_TIM2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */

+#define RCC_APB1LLPENR_TIM2LPEN                RCC_APB1LLPENR_TIM2LPEN_Msk

+#define RCC_APB1LLPENR_TIM3LPEN_Pos            (1U)

+#define RCC_APB1LLPENR_TIM3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1LLPENR_TIM3LPEN                RCC_APB1LLPENR_TIM3LPEN_Msk

+#define RCC_APB1LLPENR_TIM4LPEN_Pos            (2U)

+#define RCC_APB1LLPENR_TIM4LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1LLPENR_TIM4LPEN                RCC_APB1LLPENR_TIM4LPEN_Msk

+#define RCC_APB1LLPENR_TIM5LPEN_Pos            (3U)

+#define RCC_APB1LLPENR_TIM5LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB1LLPENR_TIM5LPEN                RCC_APB1LLPENR_TIM5LPEN_Msk

+#define RCC_APB1LLPENR_TIM6LPEN_Pos            (4U)

+#define RCC_APB1LLPENR_TIM6LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1LLPENR_TIM6LPEN                RCC_APB1LLPENR_TIM6LPEN_Msk

+#define RCC_APB1LLPENR_TIM7LPEN_Pos            (5U)

+#define RCC_APB1LLPENR_TIM7LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1LLPENR_TIM7LPEN                RCC_APB1LLPENR_TIM7LPEN_Msk

+#define RCC_APB1LLPENR_TIM12LPEN_Pos           (6U)

+#define RCC_APB1LLPENR_TIM12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */

+#define RCC_APB1LLPENR_TIM12LPEN               RCC_APB1LLPENR_TIM12LPEN_Msk

+#define RCC_APB1LLPENR_TIM13LPEN_Pos           (7U)

+#define RCC_APB1LLPENR_TIM13LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB1LLPENR_TIM13LPEN               RCC_APB1LLPENR_TIM13LPEN_Msk

+#define RCC_APB1LLPENR_TIM14LPEN_Pos           (8U)

+#define RCC_APB1LLPENR_TIM14LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1LLPENR_TIM14LPEN               RCC_APB1LLPENR_TIM14LPEN_Msk

+#define RCC_APB1LLPENR_LPTIM1LPEN_Pos          (9U)

+#define RCC_APB1LLPENR_LPTIM1LPEN_Msk          (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */

+#define RCC_APB1LLPENR_LPTIM1LPEN              RCC_APB1LLPENR_LPTIM1LPEN_Msk

+

+#define RCC_APB1LLPENR_WWDG2LPEN_Pos           (11U)

+#define RCC_APB1LLPENR_WWDG2LPEN_Msk           (0x1UL << RCC_APB1LLPENR_WWDG2LPEN_Pos) /*!< 0x00000800 */

+#define RCC_APB1LLPENR_WWDG2LPEN               RCC_APB1LLPENR_WWDG2LPEN_Msk

+

+#define RCC_APB1LLPENR_SPI2LPEN_Pos            (14U)

+#define RCC_APB1LLPENR_SPI2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */

+#define RCC_APB1LLPENR_SPI2LPEN                RCC_APB1LLPENR_SPI2LPEN_Msk

+#define RCC_APB1LLPENR_SPI3LPEN_Pos            (15U)

+#define RCC_APB1LLPENR_SPI3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */

+#define RCC_APB1LLPENR_SPI3LPEN                RCC_APB1LLPENR_SPI3LPEN_Msk

+#define RCC_APB1LLPENR_SPDIFRXLPEN_Pos         (16U)

+#define RCC_APB1LLPENR_SPDIFRXLPEN_Msk         (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB1LLPENR_SPDIFRXLPEN             RCC_APB1LLPENR_SPDIFRXLPEN_Msk

+#define RCC_APB1LLPENR_USART2LPEN_Pos          (17U)

+#define RCC_APB1LLPENR_USART2LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */

+#define RCC_APB1LLPENR_USART2LPEN              RCC_APB1LLPENR_USART2LPEN_Msk

+#define RCC_APB1LLPENR_USART3LPEN_Pos          (18U)

+#define RCC_APB1LLPENR_USART3LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */

+#define RCC_APB1LLPENR_USART3LPEN              RCC_APB1LLPENR_USART3LPEN_Msk

+#define RCC_APB1LLPENR_UART4LPEN_Pos           (19U)

+#define RCC_APB1LLPENR_UART4LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */

+#define RCC_APB1LLPENR_UART4LPEN               RCC_APB1LLPENR_UART4LPEN_Msk

+#define RCC_APB1LLPENR_UART5LPEN_Pos           (20U)

+#define RCC_APB1LLPENR_UART5LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */

+#define RCC_APB1LLPENR_UART5LPEN               RCC_APB1LLPENR_UART5LPEN_Msk

+#define RCC_APB1LLPENR_I2C1LPEN_Pos            (21U)

+#define RCC_APB1LLPENR_I2C1LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */

+#define RCC_APB1LLPENR_I2C1LPEN                RCC_APB1LLPENR_I2C1LPEN_Msk

+#define RCC_APB1LLPENR_I2C2LPEN_Pos            (22U)

+#define RCC_APB1LLPENR_I2C2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */

+#define RCC_APB1LLPENR_I2C2LPEN                RCC_APB1LLPENR_I2C2LPEN_Msk

+#define RCC_APB1LLPENR_I2C3LPEN_Pos            (23U)

+#define RCC_APB1LLPENR_I2C3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */

+#define RCC_APB1LLPENR_I2C3LPEN                RCC_APB1LLPENR_I2C3LPEN_Msk

+#define RCC_APB1LLPENR_CECLPEN_Pos             (27U)

+#define RCC_APB1LLPENR_CECLPEN_Msk             (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */

+#define RCC_APB1LLPENR_CECLPEN                 RCC_APB1LLPENR_CECLPEN_Msk

+#define RCC_APB1LLPENR_DAC12LPEN_Pos           (29U)

+#define RCC_APB1LLPENR_DAC12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */

+#define RCC_APB1LLPENR_DAC12LPEN               RCC_APB1LLPENR_DAC12LPEN_Msk

+#define RCC_APB1LLPENR_UART7LPEN_Pos           (30U)

+#define RCC_APB1LLPENR_UART7LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */

+#define RCC_APB1LLPENR_UART7LPEN               RCC_APB1LLPENR_UART7LPEN_Msk

+#define RCC_APB1LLPENR_UART8LPEN_Pos           (31U)

+#define RCC_APB1LLPENR_UART8LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */

+#define RCC_APB1LLPENR_UART8LPEN               RCC_APB1LLPENR_UART8LPEN_Msk

+

+/* Legacy define */

+#define RCC_APB1LLPENR_HDMICECEN_Pos           RCC_APB1LLPENR_CECLPEN_Pos

+#define RCC_APB1LLPENR_HDMICECEN_Msk           RCC_APB1LLPENR_CECLPEN_Msk

+#define RCC_APB1LLPENR_HDMICECEN               RCC_APB1LLPENR_CECLPEN

+/********************  Bit definition for RCC_APB1HLPENR register  ******************/

+#define RCC_APB1HLPENR_CRSLPEN_Pos             (1U)

+#define RCC_APB1HLPENR_CRSLPEN_Msk             (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1HLPENR_CRSLPEN                 RCC_APB1HLPENR_CRSLPEN_Msk

+#define RCC_APB1HLPENR_SWPMILPEN_Pos           (2U)

+#define RCC_APB1HLPENR_SWPMILPEN_Msk           (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1HLPENR_SWPMILPEN               RCC_APB1HLPENR_SWPMILPEN_Msk

+#define RCC_APB1HLPENR_OPAMPLPEN_Pos           (4U)

+#define RCC_APB1HLPENR_OPAMPLPEN_Msk           (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1HLPENR_OPAMPLPEN               RCC_APB1HLPENR_OPAMPLPEN_Msk

+#define RCC_APB1HLPENR_MDIOSLPEN_Pos           (5U)

+#define RCC_APB1HLPENR_MDIOSLPEN_Msk           (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1HLPENR_MDIOSLPEN               RCC_APB1HLPENR_MDIOSLPEN_Msk

+#define RCC_APB1HLPENR_FDCANLPEN_Pos           (8U)

+#define RCC_APB1HLPENR_FDCANLPEN_Msk           (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1HLPENR_FDCANLPEN               RCC_APB1HLPENR_FDCANLPEN_Msk

+

+/********************  Bit definition for RCC_APB2LPENR register  ******************/

+#define RCC_APB2LPENR_TIM1LPEN_Pos             (0U)

+#define RCC_APB2LPENR_TIM1LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */

+#define RCC_APB2LPENR_TIM1LPEN                 RCC_APB2LPENR_TIM1LPEN_Msk

+#define RCC_APB2LPENR_TIM8LPEN_Pos             (1U)

+#define RCC_APB2LPENR_TIM8LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB2LPENR_TIM8LPEN                 RCC_APB2LPENR_TIM8LPEN_Msk

+#define RCC_APB2LPENR_USART1LPEN_Pos           (4U)

+#define RCC_APB2LPENR_USART1LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB2LPENR_USART1LPEN               RCC_APB2LPENR_USART1LPEN_Msk

+#define RCC_APB2LPENR_USART6LPEN_Pos           (5U)

+#define RCC_APB2LPENR_USART6LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB2LPENR_USART6LPEN               RCC_APB2LPENR_USART6LPEN_Msk

+#define RCC_APB2LPENR_SPI1LPEN_Pos             (12U)

+#define RCC_APB2LPENR_SPI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */

+#define RCC_APB2LPENR_SPI1LPEN                 RCC_APB2LPENR_SPI1LPEN_Msk

+#define RCC_APB2LPENR_SPI4LPEN_Pos             (13U)

+#define RCC_APB2LPENR_SPI4LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */

+#define RCC_APB2LPENR_SPI4LPEN                 RCC_APB2LPENR_SPI4LPEN_Msk

+#define RCC_APB2LPENR_TIM15LPEN_Pos            (16U)

+#define RCC_APB2LPENR_TIM15LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB2LPENR_TIM15LPEN                RCC_APB2LPENR_TIM15LPEN_Msk

+#define RCC_APB2LPENR_TIM16LPEN_Pos            (17U)

+#define RCC_APB2LPENR_TIM16LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */

+#define RCC_APB2LPENR_TIM16LPEN                RCC_APB2LPENR_TIM16LPEN_Msk

+#define RCC_APB2LPENR_TIM17LPEN_Pos            (18U)

+#define RCC_APB2LPENR_TIM17LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */

+#define RCC_APB2LPENR_TIM17LPEN                RCC_APB2LPENR_TIM17LPEN_Msk

+#define RCC_APB2LPENR_SPI5LPEN_Pos             (20U)

+#define RCC_APB2LPENR_SPI5LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */

+#define RCC_APB2LPENR_SPI5LPEN                 RCC_APB2LPENR_SPI5LPEN_Msk

+#define RCC_APB2LPENR_SAI1LPEN_Pos             (22U)

+#define RCC_APB2LPENR_SAI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */

+#define RCC_APB2LPENR_SAI1LPEN                 RCC_APB2LPENR_SAI1LPEN_Msk

+#define RCC_APB2LPENR_SAI2LPEN_Pos             (23U)

+#define RCC_APB2LPENR_SAI2LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */

+#define RCC_APB2LPENR_SAI2LPEN                 RCC_APB2LPENR_SAI2LPEN_Msk

+#define RCC_APB2LPENR_SAI3LPEN_Pos             (24U)

+#define RCC_APB2LPENR_SAI3LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI3LPEN_Pos) /*!< 0x01000000 */

+#define RCC_APB2LPENR_SAI3LPEN                 RCC_APB2LPENR_SAI3LPEN_Msk

+#define RCC_APB2LPENR_DFSDM1LPEN_Pos           (28U)

+#define RCC_APB2LPENR_DFSDM1LPEN_Msk           (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x10000000 */

+#define RCC_APB2LPENR_DFSDM1LPEN               RCC_APB2LPENR_DFSDM1LPEN_Msk

+#define RCC_APB2LPENR_HRTIMLPEN_Pos            (29U)

+#define RCC_APB2LPENR_HRTIMLPEN_Msk            (0x1UL << RCC_APB2LPENR_HRTIMLPEN_Pos) /*!< 0x20000000 */

+#define RCC_APB2LPENR_HRTIMLPEN                RCC_APB2LPENR_HRTIMLPEN_Msk

+

+/********************  Bit definition for RCC_APB4LPENR register  ******************/

+#define RCC_APB4LPENR_SYSCFGLPEN_Pos           (1U)

+#define RCC_APB4LPENR_SYSCFGLPEN_Msk           (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB4LPENR_SYSCFGLPEN               RCC_APB4LPENR_SYSCFGLPEN_Msk

+#define RCC_APB4LPENR_LPUART1LPEN_Pos          (3U)

+#define RCC_APB4LPENR_LPUART1LPEN_Msk          (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB4LPENR_LPUART1LPEN              RCC_APB4LPENR_LPUART1LPEN_Msk

+#define RCC_APB4LPENR_SPI6LPEN_Pos             (5U)

+#define RCC_APB4LPENR_SPI6LPEN_Msk             (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB4LPENR_SPI6LPEN                 RCC_APB4LPENR_SPI6LPEN_Msk

+#define RCC_APB4LPENR_I2C4LPEN_Pos             (7U)

+#define RCC_APB4LPENR_I2C4LPEN_Msk             (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB4LPENR_I2C4LPEN                 RCC_APB4LPENR_I2C4LPEN_Msk

+#define RCC_APB4LPENR_LPTIM2LPEN_Pos           (9U)

+#define RCC_APB4LPENR_LPTIM2LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */

+#define RCC_APB4LPENR_LPTIM2LPEN               RCC_APB4LPENR_LPTIM2LPEN_Msk

+#define RCC_APB4LPENR_LPTIM3LPEN_Pos           (10U)

+#define RCC_APB4LPENR_LPTIM3LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */

+#define RCC_APB4LPENR_LPTIM3LPEN               RCC_APB4LPENR_LPTIM3LPEN_Msk

+#define RCC_APB4LPENR_LPTIM4LPEN_Pos           (11U)

+#define RCC_APB4LPENR_LPTIM4LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) /*!< 0x00000800 */

+#define RCC_APB4LPENR_LPTIM4LPEN               RCC_APB4LPENR_LPTIM4LPEN_Msk

+#define RCC_APB4LPENR_LPTIM5LPEN_Pos           (12U)

+#define RCC_APB4LPENR_LPTIM5LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) /*!< 0x00001000 */

+#define RCC_APB4LPENR_LPTIM5LPEN               RCC_APB4LPENR_LPTIM5LPEN_Msk

+#define RCC_APB4LPENR_COMP12LPEN_Pos           (14U)

+#define RCC_APB4LPENR_COMP12LPEN_Msk           (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */

+#define RCC_APB4LPENR_COMP12LPEN               RCC_APB4LPENR_COMP12LPEN_Msk

+#define RCC_APB4LPENR_VREFLPEN_Pos             (15U)

+#define RCC_APB4LPENR_VREFLPEN_Msk             (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */

+#define RCC_APB4LPENR_VREFLPEN                 RCC_APB4LPENR_VREFLPEN_Msk

+#define RCC_APB4LPENR_RTCAPBLPEN_Pos           (16U)

+#define RCC_APB4LPENR_RTCAPBLPEN_Msk           (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB4LPENR_RTCAPBLPEN               RCC_APB4LPENR_RTCAPBLPEN_Msk

+#define RCC_APB4LPENR_SAI4LPEN_Pos             (21U)

+#define RCC_APB4LPENR_SAI4LPEN_Msk             (0x1UL << RCC_APB4LPENR_SAI4LPEN_Pos) /*!< 0x00200000 */

+#define RCC_APB4LPENR_SAI4LPEN                 RCC_APB4LPENR_SAI4LPEN_Msk

+

+/********************  Bit definition for RCC_D1CCIPR register  ****************/

+#define RCC_D1CCIPR_DSISRC_Pos                 (8U)

+#define RCC_D1CCIPR_DSISRC_Msk                 (0x1UL << RCC_D1CCIPR_DSISRC_Pos) /*!< 0x00000100 */

+#define RCC_D1CCIPR_DSISRC                     RCC_D1CCIPR_DSISRC_Msk

+

+/********************  Bit definition for RCC_RSR register  *******************/

+#define RCC_RSR_RMVF_Pos                       (16U)

+#define RCC_RSR_RMVF_Msk                       (0x1UL << RCC_RSR_RMVF_Pos)     /*!< 0x00010000 */

+#define RCC_RSR_RMVF                           RCC_RSR_RMVF_Msk

+#define RCC_RSR_C1RSTF_Pos                     (17U)

+#define RCC_RSR_C1RSTF_Msk                     (0x1UL << RCC_RSR_C1RSTF_Pos)   /*!< 0x00020000 */

+#define RCC_RSR_C1RSTF                         RCC_RSR_C1RSTF_Msk

+#define RCC_RSR_D1RSTF_Pos                     (19U)

+#define RCC_RSR_D1RSTF_Msk                     (0x1UL << RCC_RSR_D1RSTF_Pos)   /*!< 0x00080000 */

+#define RCC_RSR_D1RSTF                         RCC_RSR_D1RSTF_Msk

+#define RCC_RSR_D2RSTF_Pos                     (20U)

+#define RCC_RSR_D2RSTF_Msk                     (0x1UL << RCC_RSR_D2RSTF_Pos)   /*!< 0x00100000 */

+#define RCC_RSR_D2RSTF                         RCC_RSR_D2RSTF_Msk

+#define RCC_RSR_BORRSTF_Pos                    (21U)

+#define RCC_RSR_BORRSTF_Msk                    (0x1UL << RCC_RSR_BORRSTF_Pos)  /*!< 0x00200000 */

+#define RCC_RSR_BORRSTF                        RCC_RSR_BORRSTF_Msk

+#define RCC_RSR_PINRSTF_Pos                    (22U)

+#define RCC_RSR_PINRSTF_Msk                    (0x1UL << RCC_RSR_PINRSTF_Pos)  /*!< 0x00400000 */

+#define RCC_RSR_PINRSTF                        RCC_RSR_PINRSTF_Msk

+#define RCC_RSR_PORRSTF_Pos                    (23U)

+#define RCC_RSR_PORRSTF_Msk                    (0x1UL << RCC_RSR_PORRSTF_Pos)  /*!< 0x00800000 */

+#define RCC_RSR_PORRSTF                        RCC_RSR_PORRSTF_Msk

+#define RCC_RSR_SFT1RSTF_Pos                   (24U)

+#define RCC_RSR_SFT1RSTF_Msk                   (0x1UL << RCC_RSR_SFT1RSTF_Pos) /*!< 0x01000000 */

+#define RCC_RSR_SFT1RSTF                       RCC_RSR_SFT1RSTF_Msk

+#define RCC_RSR_IWDG1RSTF_Pos                  (26U)

+#define RCC_RSR_IWDG1RSTF_Msk                  (0x1UL << RCC_RSR_IWDG1RSTF_Pos) /*!< 0x04000000 */

+#define RCC_RSR_IWDG1RSTF                      RCC_RSR_IWDG1RSTF_Msk

+#define RCC_RSR_WWDG1RSTF_Pos                  (28U)

+#define RCC_RSR_WWDG1RSTF_Msk                  (0x1UL << RCC_RSR_WWDG1RSTF_Pos) /*!< 0x10000000 */

+#define RCC_RSR_WWDG1RSTF                      RCC_RSR_WWDG1RSTF_Msk

+

+#define RCC_RSR_WWDG2RSTF_Pos                  (29U)

+#define RCC_RSR_WWDG2RSTF_Msk                  (0x1UL << RCC_RSR_WWDG2RSTF_Pos) /*!< 0x20000000 */

+#define RCC_RSR_WWDG2RSTF                      RCC_RSR_WWDG2RSTF_Msk

+#define RCC_RSR_IWDG2RSTF_Pos                  (27U)

+#define RCC_RSR_IWDG2RSTF_Msk                  (0x1UL << RCC_RSR_IWDG2RSTF_Pos) /*!< 0x08000000 */

+#define RCC_RSR_IWDG2RSTF                      RCC_RSR_IWDG2RSTF_Msk

+#define RCC_RSR_SFT2RSTF_Pos                   (25U)

+#define RCC_RSR_SFT2RSTF_Msk                   (0x1UL << RCC_RSR_SFT2RSTF_Pos) /*!< 0x02000000 */

+#define RCC_RSR_SFT2RSTF                       RCC_RSR_SFT2RSTF_Msk

+#define RCC_RSR_C2RSTF_Pos                     (18U)

+#define RCC_RSR_C2RSTF_Msk                     (0x1UL << RCC_RSR_C2RSTF_Pos)   /*!< 0x00040000 */

+#define RCC_RSR_C2RSTF                         RCC_RSR_C2RSTF_Msk

+#define RCC_RSR_LPWR1RSTF_Pos                  (30U)

+#define RCC_RSR_LPWR1RSTF_Msk                  (0x1UL << RCC_RSR_LPWR1RSTF_Pos) /*!< 0x40000000 */

+#define RCC_RSR_LPWR1RSTF                      RCC_RSR_LPWR1RSTF_Msk

+#define RCC_RSR_LPWR2RSTF_Pos                  (31U)

+#define RCC_RSR_LPWR2RSTF_Msk                  (0x1UL << RCC_RSR_LPWR2RSTF_Pos) /*!< 0x80000000 */

+#define RCC_RSR_LPWR2RSTF                      RCC_RSR_LPWR2RSTF_Msk

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    RNG                                     */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for RNG_CR register  *******************/

+#define RNG_CR_RNGEN_Pos    (2U)

+#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */

+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk

+#define RNG_CR_IE_Pos       (3U)

+#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */

+#define RNG_CR_IE           RNG_CR_IE_Msk

+#define RNG_CR_CED_Pos      (5U)

+#define RNG_CR_CED_Msk      (0x1UL << RNG_CR_CED_Pos)                          /*!< 0x00000020 */

+#define RNG_CR_CED          RNG_CR_CED_Msk

+

+/********************  Bits definition for RNG_SR register  *******************/

+#define RNG_SR_DRDY_Pos     (0U)

+#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */

+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk

+#define RNG_SR_CECS_Pos     (1U)

+#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */

+#define RNG_SR_CECS         RNG_SR_CECS_Msk

+#define RNG_SR_SECS_Pos     (2U)

+#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */

+#define RNG_SR_SECS         RNG_SR_SECS_Msk

+#define RNG_SR_CEIS_Pos     (5U)

+#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */

+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk

+#define RNG_SR_SEIS_Pos     (6U)

+#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */

+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                           Real-Time Clock (RTC)                            */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for RTC_TR register  *******************/

+#define RTC_TR_PM_Pos                  (22U)

+#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */

+#define RTC_TR_PM                      RTC_TR_PM_Msk

+#define RTC_TR_HT_Pos                  (20U)

+#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */

+#define RTC_TR_HT                      RTC_TR_HT_Msk

+#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */

+#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */

+#define RTC_TR_HU_Pos                  (16U)

+#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */

+#define RTC_TR_HU                      RTC_TR_HU_Msk

+#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */

+#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */

+#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */

+#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */

+#define RTC_TR_MNT_Pos                 (12U)

+#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */

+#define RTC_TR_MNT                     RTC_TR_MNT_Msk

+#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */

+#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */

+#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */

+#define RTC_TR_MNU_Pos                 (8U)

+#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */

+#define RTC_TR_MNU                     RTC_TR_MNU_Msk

+#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */

+#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */

+#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */

+#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */

+#define RTC_TR_ST_Pos                  (4U)

+#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */

+#define RTC_TR_ST                      RTC_TR_ST_Msk

+#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */

+#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */

+#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */

+#define RTC_TR_SU_Pos                  (0U)

+#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */

+#define RTC_TR_SU                      RTC_TR_SU_Msk

+#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */

+#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */

+#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */

+#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_DR register  *******************/

+#define RTC_DR_YT_Pos                  (20U)

+#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */

+#define RTC_DR_YT                      RTC_DR_YT_Msk

+#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */

+#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */

+#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */

+#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */

+#define RTC_DR_YU_Pos                  (16U)

+#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */

+#define RTC_DR_YU                      RTC_DR_YU_Msk

+#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */

+#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */

+#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */

+#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */

+#define RTC_DR_WDU_Pos                 (13U)

+#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */

+#define RTC_DR_WDU                     RTC_DR_WDU_Msk

+#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */

+#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */

+#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */

+#define RTC_DR_MT_Pos                  (12U)

+#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */

+#define RTC_DR_MT                      RTC_DR_MT_Msk

+#define RTC_DR_MU_Pos                  (8U)

+#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */

+#define RTC_DR_MU                      RTC_DR_MU_Msk

+#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */

+#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */

+#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */

+#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */

+#define RTC_DR_DT_Pos                  (4U)

+#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */

+#define RTC_DR_DT                      RTC_DR_DT_Msk

+#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */

+#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */

+#define RTC_DR_DU_Pos                  (0U)

+#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */

+#define RTC_DR_DU                      RTC_DR_DU_Msk

+#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */

+#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */

+#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */

+#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_CR register  *******************/

+#define RTC_CR_ITSE_Pos                (24U)

+#define RTC_CR_ITSE_Msk                (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */

+#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk

+#define RTC_CR_COE_Pos                 (23U)

+#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */

+#define RTC_CR_COE                     RTC_CR_COE_Msk

+#define RTC_CR_OSEL_Pos                (21U)

+#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */

+#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk

+#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */

+#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */

+#define RTC_CR_POL_Pos                 (20U)

+#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */

+#define RTC_CR_POL                     RTC_CR_POL_Msk

+#define RTC_CR_COSEL_Pos               (19U)

+#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */

+#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk

+#define RTC_CR_BKP_Pos                 (18U)

+#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */

+#define RTC_CR_BKP                     RTC_CR_BKP_Msk

+#define RTC_CR_SUB1H_Pos               (17U)

+#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */

+#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk

+#define RTC_CR_ADD1H_Pos               (16U)

+#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */

+#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk

+#define RTC_CR_TSIE_Pos                (15U)

+#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */

+#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk

+#define RTC_CR_WUTIE_Pos               (14U)

+#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */

+#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk

+#define RTC_CR_ALRBIE_Pos              (13U)

+#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */

+#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk

+#define RTC_CR_ALRAIE_Pos              (12U)

+#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */

+#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk

+#define RTC_CR_TSE_Pos                 (11U)

+#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */

+#define RTC_CR_TSE                     RTC_CR_TSE_Msk

+#define RTC_CR_WUTE_Pos                (10U)

+#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */

+#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk

+#define RTC_CR_ALRBE_Pos               (9U)

+#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */

+#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk

+#define RTC_CR_ALRAE_Pos               (8U)

+#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */

+#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk

+#define RTC_CR_FMT_Pos                 (6U)

+#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */

+#define RTC_CR_FMT                     RTC_CR_FMT_Msk

+#define RTC_CR_BYPSHAD_Pos             (5U)

+#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */

+#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk

+#define RTC_CR_REFCKON_Pos             (4U)

+#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */

+#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk

+#define RTC_CR_TSEDGE_Pos              (3U)

+#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */

+#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk

+#define RTC_CR_WUCKSEL_Pos             (0U)

+#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */

+#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk

+#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */

+#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */

+#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */

+

+/********************  Bits definition for RTC_ISR register  ******************/

+#define RTC_ISR_ITSF_Pos               (17U)

+#define RTC_ISR_ITSF_Msk               (0x1UL << RTC_ISR_ITSF_Pos)             /*!< 0x00020000 */

+#define RTC_ISR_ITSF                   RTC_ISR_ITSF_Msk

+#define RTC_ISR_RECALPF_Pos            (16U)

+#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)          /*!< 0x00010000 */

+#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk

+#define RTC_ISR_TAMP3F_Pos             (15U)

+#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)           /*!< 0x00008000 */

+#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk

+#define RTC_ISR_TAMP2F_Pos             (14U)

+#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)           /*!< 0x00004000 */

+#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk

+#define RTC_ISR_TAMP1F_Pos             (13U)

+#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)           /*!< 0x00002000 */

+#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk

+#define RTC_ISR_TSOVF_Pos              (12U)

+#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)            /*!< 0x00001000 */

+#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk

+#define RTC_ISR_TSF_Pos                (11U)

+#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)              /*!< 0x00000800 */

+#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk

+#define RTC_ISR_WUTF_Pos               (10U)

+#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)             /*!< 0x00000400 */

+#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk

+#define RTC_ISR_ALRBF_Pos              (9U)

+#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)            /*!< 0x00000200 */

+#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk

+#define RTC_ISR_ALRAF_Pos              (8U)

+#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)            /*!< 0x00000100 */

+#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk

+#define RTC_ISR_INIT_Pos               (7U)

+#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)             /*!< 0x00000080 */

+#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk

+#define RTC_ISR_INITF_Pos              (6U)

+#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)            /*!< 0x00000040 */

+#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk

+#define RTC_ISR_RSF_Pos                (5U)

+#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)              /*!< 0x00000020 */

+#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk

+#define RTC_ISR_INITS_Pos              (4U)

+#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)            /*!< 0x00000010 */

+#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk

+#define RTC_ISR_SHPF_Pos               (3U)

+#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)             /*!< 0x00000008 */

+#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk

+#define RTC_ISR_WUTWF_Pos              (2U)

+#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)            /*!< 0x00000004 */

+#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk

+#define RTC_ISR_ALRBWF_Pos             (1U)

+#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)           /*!< 0x00000002 */

+#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk

+#define RTC_ISR_ALRAWF_Pos             (0U)

+#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)           /*!< 0x00000001 */

+#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk

+

+/********************  Bits definition for RTC_PRER register  *****************/

+#define RTC_PRER_PREDIV_A_Pos          (16U)

+#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */

+#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk

+#define RTC_PRER_PREDIV_S_Pos          (0U)

+#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */

+#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk

+

+/********************  Bits definition for RTC_WUTR register  *****************/

+#define RTC_WUTR_WUT_Pos               (0U)

+#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */

+#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk

+

+/********************  Bits definition for RTC_ALRMAR register  ***************/

+#define RTC_ALRMAR_MSK4_Pos            (31U)

+#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */

+#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk

+#define RTC_ALRMAR_WDSEL_Pos           (30U)

+#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */

+#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk

+#define RTC_ALRMAR_DT_Pos              (28U)

+#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */

+#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk

+#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */

+#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */

+#define RTC_ALRMAR_DU_Pos              (24U)

+#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */

+#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk

+#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */

+#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */

+#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */

+#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */

+#define RTC_ALRMAR_MSK3_Pos            (23U)

+#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */

+#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk

+#define RTC_ALRMAR_PM_Pos              (22U)

+#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */

+#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk

+#define RTC_ALRMAR_HT_Pos              (20U)

+#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */

+#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk

+#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */

+#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */

+#define RTC_ALRMAR_HU_Pos              (16U)

+#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */

+#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk

+#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */

+#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */

+#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */

+#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */

+#define RTC_ALRMAR_MSK2_Pos            (15U)

+#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */

+#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk

+#define RTC_ALRMAR_MNT_Pos             (12U)

+#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */

+#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk

+#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */

+#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */

+#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */

+#define RTC_ALRMAR_MNU_Pos             (8U)

+#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */

+#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk

+#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */

+#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */

+#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */

+#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */

+#define RTC_ALRMAR_MSK1_Pos            (7U)

+#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */

+#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk

+#define RTC_ALRMAR_ST_Pos              (4U)

+#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */

+#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk

+#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */

+#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */

+#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */

+#define RTC_ALRMAR_SU_Pos              (0U)

+#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */

+#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk

+#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */

+#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */

+#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */

+#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_ALRMBR register  ***************/

+#define RTC_ALRMBR_MSK4_Pos            (31U)

+#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */

+#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk

+#define RTC_ALRMBR_WDSEL_Pos           (30U)

+#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */

+#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk

+#define RTC_ALRMBR_DT_Pos              (28U)

+#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */

+#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk

+#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */

+#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */

+#define RTC_ALRMBR_DU_Pos              (24U)

+#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */

+#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk

+#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */

+#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */

+#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */

+#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */

+#define RTC_ALRMBR_MSK3_Pos            (23U)

+#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */

+#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk

+#define RTC_ALRMBR_PM_Pos              (22U)

+#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */

+#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk

+#define RTC_ALRMBR_HT_Pos              (20U)

+#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */

+#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk

+#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */

+#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */

+#define RTC_ALRMBR_HU_Pos              (16U)

+#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */

+#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk

+#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */

+#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */

+#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */

+#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */

+#define RTC_ALRMBR_MSK2_Pos            (15U)

+#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */

+#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk

+#define RTC_ALRMBR_MNT_Pos             (12U)

+#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */

+#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk

+#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */

+#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */

+#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */

+#define RTC_ALRMBR_MNU_Pos             (8U)

+#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */

+#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk

+#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */

+#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */

+#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */

+#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */

+#define RTC_ALRMBR_MSK1_Pos            (7U)

+#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */

+#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk

+#define RTC_ALRMBR_ST_Pos              (4U)

+#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */

+#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk

+#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */

+#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */

+#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */

+#define RTC_ALRMBR_SU_Pos              (0U)

+#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */

+#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk

+#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */

+#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */

+#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */

+#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_WPR register  ******************/

+#define RTC_WPR_KEY_Pos                (0U)

+#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */

+#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk

+

+/********************  Bits definition for RTC_SSR register  ******************/

+#define RTC_SSR_SS_Pos                 (0U)

+#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)            /*!< 0x0000FFFF */

+#define RTC_SSR_SS                     RTC_SSR_SS_Msk

+

+/********************  Bits definition for RTC_SHIFTR register  ***************/

+#define RTC_SHIFTR_SUBFS_Pos           (0U)

+#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */

+#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk

+#define RTC_SHIFTR_ADD1S_Pos           (31U)

+#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */

+#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk

+

+/********************  Bits definition for RTC_TSTR register  *****************/

+#define RTC_TSTR_PM_Pos                (22U)

+#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */

+#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk

+#define RTC_TSTR_HT_Pos                (20U)

+#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */

+#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk

+#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */

+#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */

+#define RTC_TSTR_HU_Pos                (16U)

+#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */

+#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk

+#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */

+#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */

+#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */

+#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */

+#define RTC_TSTR_MNT_Pos               (12U)

+#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */

+#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk

+#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */

+#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */

+#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */

+#define RTC_TSTR_MNU_Pos               (8U)

+#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */

+#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk

+#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */

+#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */

+#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */

+#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */

+#define RTC_TSTR_ST_Pos                (4U)

+#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */

+#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk

+#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */

+#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */

+#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */

+#define RTC_TSTR_SU_Pos                (0U)

+#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */

+#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk

+#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */

+#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */

+#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */

+#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_TSDR register  *****************/

+#define RTC_TSDR_WDU_Pos               (13U)

+#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */

+#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk

+#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */

+#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */

+#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */

+#define RTC_TSDR_MT_Pos                (12U)

+#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */

+#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk

+#define RTC_TSDR_MU_Pos                (8U)

+#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */

+#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk

+#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */

+#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */

+#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */

+#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */

+#define RTC_TSDR_DT_Pos                (4U)

+#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */

+#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk

+#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */

+#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */

+#define RTC_TSDR_DU_Pos                (0U)

+#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */

+#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk

+#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */

+#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */

+#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */

+#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_TSSSR register  ****************/

+#define RTC_TSSSR_SS_Pos               (0U)

+#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)          /*!< 0x0000FFFF */

+#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk

+

+/********************  Bits definition for RTC_CALR register  *****************/

+#define RTC_CALR_CALP_Pos              (15U)

+#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */

+#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk

+#define RTC_CALR_CALW8_Pos             (14U)

+#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */

+#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk

+#define RTC_CALR_CALW16_Pos            (13U)

+#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */

+#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk

+#define RTC_CALR_CALM_Pos              (0U)

+#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */

+#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk

+#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */

+#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */

+#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */

+#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */

+#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */

+#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */

+#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */

+#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */

+#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */

+

+/********************  Bits definition for RTC_TAMPCR register  ***************/

+#define RTC_TAMPCR_TAMP3MF_Pos         (24U)

+#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)       /*!< 0x01000000 */

+#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk

+#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)

+#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)  /*!< 0x00800000 */

+#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk

+#define RTC_TAMPCR_TAMP3IE_Pos         (22U)

+#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)       /*!< 0x00400000 */

+#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk

+#define RTC_TAMPCR_TAMP2MF_Pos         (21U)

+#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)       /*!< 0x00200000 */

+#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk

+#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)

+#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)  /*!< 0x00100000 */

+#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk

+#define RTC_TAMPCR_TAMP2IE_Pos         (19U)

+#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)       /*!< 0x00080000 */

+#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk

+#define RTC_TAMPCR_TAMP1MF_Pos         (18U)

+#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)       /*!< 0x00040000 */

+#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk

+#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)

+#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)  /*!< 0x00020000 */

+#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk

+#define RTC_TAMPCR_TAMP1IE_Pos         (16U)

+#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)       /*!< 0x00010000 */

+#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk

+#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)

+#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)     /*!< 0x00008000 */

+#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk

+#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)

+#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)      /*!< 0x00006000 */

+#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk

+#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */

+#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */

+#define RTC_TAMPCR_TAMPFLT_Pos         (11U)

+#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)       /*!< 0x00001800 */

+#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk

+#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */

+#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */

+#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)

+#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)      /*!< 0x00000700 */

+#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk

+#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */

+#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */

+#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */

+#define RTC_TAMPCR_TAMPTS_Pos          (7U)

+#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)        /*!< 0x00000080 */

+#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk

+#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)

+#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)      /*!< 0x00000040 */

+#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk

+#define RTC_TAMPCR_TAMP3E_Pos          (5U)

+#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)        /*!< 0x00000020 */

+#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk

+#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)

+#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)      /*!< 0x00000010 */

+#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk

+#define RTC_TAMPCR_TAMP2E_Pos          (3U)

+#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)        /*!< 0x00000008 */

+#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk

+#define RTC_TAMPCR_TAMPIE_Pos          (2U)

+#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)        /*!< 0x00000004 */

+#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk

+#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)

+#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)      /*!< 0x00000002 */

+#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk

+#define RTC_TAMPCR_TAMP1E_Pos          (0U)

+#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)        /*!< 0x00000001 */

+#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk

+

+/********************  Bits definition for RTC_ALRMASSR register  *************/

+#define RTC_ALRMASSR_MASKSS_Pos        (24U)

+#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x0F000000 */

+#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk

+#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */

+#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */

+#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */

+#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */

+#define RTC_ALRMASSR_SS_Pos            (0U)

+#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */

+#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk

+

+/********************  Bits definition for RTC_ALRMBSSR register  *************/

+#define RTC_ALRMBSSR_MASKSS_Pos        (24U)

+#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x0F000000 */

+#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk

+#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */

+#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */

+#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */

+#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */

+#define RTC_ALRMBSSR_SS_Pos            (0U)

+#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */

+#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk

+

+/********************  Bits definition for RTC_OR register  *******************/

+#define RTC_OR_OUT_RMP_Pos             (1U)

+#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)           /*!< 0x00000002 */

+#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk

+#define RTC_OR_ALARMOUTTYPE_Pos        (0U)

+#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)      /*!< 0x00000001 */

+#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk

+

+/********************  Bits definition for RTC_BKP0R register  ****************/

+#define RTC_BKP0R_Pos                  (0U)

+#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP0R                      RTC_BKP0R_Msk

+

+/********************  Bits definition for RTC_BKP1R register  ****************/

+#define RTC_BKP1R_Pos                  (0U)

+#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP1R                      RTC_BKP1R_Msk

+

+/********************  Bits definition for RTC_BKP2R register  ****************/

+#define RTC_BKP2R_Pos                  (0U)

+#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP2R                      RTC_BKP2R_Msk

+

+/********************  Bits definition for RTC_BKP3R register  ****************/

+#define RTC_BKP3R_Pos                  (0U)

+#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP3R                      RTC_BKP3R_Msk

+

+/********************  Bits definition for RTC_BKP4R register  ****************/

+#define RTC_BKP4R_Pos                  (0U)

+#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP4R                      RTC_BKP4R_Msk

+

+/********************  Bits definition for RTC_BKP5R register  ****************/

+#define RTC_BKP5R_Pos                  (0U)

+#define RTC_BKP5R_Msk                  (0xFFFFFFFFUL << RTC_BKP5R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP5R                      RTC_BKP5R_Msk

+

+/********************  Bits definition for RTC_BKP6R register  ****************/

+#define RTC_BKP6R_Pos                  (0U)

+#define RTC_BKP6R_Msk                  (0xFFFFFFFFUL << RTC_BKP6R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP6R                      RTC_BKP6R_Msk

+

+/********************  Bits definition for RTC_BKP7R register  ****************/

+#define RTC_BKP7R_Pos                  (0U)

+#define RTC_BKP7R_Msk                  (0xFFFFFFFFUL << RTC_BKP7R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP7R                      RTC_BKP7R_Msk

+

+/********************  Bits definition for RTC_BKP8R register  ****************/

+#define RTC_BKP8R_Pos                  (0U)

+#define RTC_BKP8R_Msk                  (0xFFFFFFFFUL << RTC_BKP8R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP8R                      RTC_BKP8R_Msk

+

+/********************  Bits definition for RTC_BKP9R register  ****************/

+#define RTC_BKP9R_Pos                  (0U)

+#define RTC_BKP9R_Msk                  (0xFFFFFFFFUL << RTC_BKP9R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP9R                      RTC_BKP9R_Msk

+

+/********************  Bits definition for RTC_BKP10R register  ***************/

+#define RTC_BKP10R_Pos                 (0U)

+#define RTC_BKP10R_Msk                 (0xFFFFFFFFUL << RTC_BKP10R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP10R                     RTC_BKP10R_Msk

+

+/********************  Bits definition for RTC_BKP11R register  ***************/

+#define RTC_BKP11R_Pos                 (0U)

+#define RTC_BKP11R_Msk                 (0xFFFFFFFFUL << RTC_BKP11R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP11R                     RTC_BKP11R_Msk

+

+/********************  Bits definition for RTC_BKP12R register  ***************/

+#define RTC_BKP12R_Pos                 (0U)

+#define RTC_BKP12R_Msk                 (0xFFFFFFFFUL << RTC_BKP12R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP12R                     RTC_BKP12R_Msk

+

+/********************  Bits definition for RTC_BKP13R register  ***************/

+#define RTC_BKP13R_Pos                 (0U)

+#define RTC_BKP13R_Msk                 (0xFFFFFFFFUL << RTC_BKP13R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP13R                     RTC_BKP13R_Msk

+

+/********************  Bits definition for RTC_BKP14R register  ***************/

+#define RTC_BKP14R_Pos                 (0U)

+#define RTC_BKP14R_Msk                 (0xFFFFFFFFUL << RTC_BKP14R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP14R                     RTC_BKP14R_Msk

+

+/********************  Bits definition for RTC_BKP15R register  ***************/

+#define RTC_BKP15R_Pos                 (0U)

+#define RTC_BKP15R_Msk                 (0xFFFFFFFFUL << RTC_BKP15R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP15R                     RTC_BKP15R_Msk

+

+/********************  Bits definition for RTC_BKP16R register  ***************/

+#define RTC_BKP16R_Pos                 (0U)

+#define RTC_BKP16R_Msk                 (0xFFFFFFFFUL << RTC_BKP16R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP16R                     RTC_BKP16R_Msk

+

+/********************  Bits definition for RTC_BKP17R register  ***************/

+#define RTC_BKP17R_Pos                 (0U)

+#define RTC_BKP17R_Msk                 (0xFFFFFFFFUL << RTC_BKP17R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP17R                     RTC_BKP17R_Msk

+

+/********************  Bits definition for RTC_BKP18R register  ***************/

+#define RTC_BKP18R_Pos                 (0U)

+#define RTC_BKP18R_Msk                 (0xFFFFFFFFUL << RTC_BKP18R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP18R                     RTC_BKP18R_Msk

+

+/********************  Bits definition for RTC_BKP19R register  ***************/

+#define RTC_BKP19R_Pos                 (0U)

+#define RTC_BKP19R_Msk                 (0xFFFFFFFFUL << RTC_BKP19R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP19R                     RTC_BKP19R_Msk

+

+/********************  Bits definition for RTC_BKP20R register  ***************/

+#define RTC_BKP20R_Pos                 (0U)

+#define RTC_BKP20R_Msk                 (0xFFFFFFFFUL << RTC_BKP20R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP20R                     RTC_BKP20R_Msk

+

+/********************  Bits definition for RTC_BKP21R register  ***************/

+#define RTC_BKP21R_Pos                 (0U)

+#define RTC_BKP21R_Msk                 (0xFFFFFFFFUL << RTC_BKP21R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP21R                     RTC_BKP21R_Msk

+

+/********************  Bits definition for RTC_BKP22R register  ***************/

+#define RTC_BKP22R_Pos                 (0U)

+#define RTC_BKP22R_Msk                 (0xFFFFFFFFUL << RTC_BKP22R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP22R                     RTC_BKP22R_Msk

+

+/********************  Bits definition for RTC_BKP23R register  ***************/

+#define RTC_BKP23R_Pos                 (0U)

+#define RTC_BKP23R_Msk                 (0xFFFFFFFFUL << RTC_BKP23R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP23R                     RTC_BKP23R_Msk

+

+/********************  Bits definition for RTC_BKP24R register  ***************/

+#define RTC_BKP24R_Pos                 (0U)

+#define RTC_BKP24R_Msk                 (0xFFFFFFFFUL << RTC_BKP24R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP24R                     RTC_BKP24R_Msk

+

+/********************  Bits definition for RTC_BKP25R register  ***************/

+#define RTC_BKP25R_Pos                 (0U)

+#define RTC_BKP25R_Msk                 (0xFFFFFFFFUL << RTC_BKP25R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP25R                     RTC_BKP25R_Msk

+

+/********************  Bits definition for RTC_BKP26R register  ***************/

+#define RTC_BKP26R_Pos                 (0U)

+#define RTC_BKP26R_Msk                 (0xFFFFFFFFUL << RTC_BKP26R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP26R                     RTC_BKP26R_Msk

+

+/********************  Bits definition for RTC_BKP27R register  ***************/

+#define RTC_BKP27R_Pos                 (0U)

+#define RTC_BKP27R_Msk                 (0xFFFFFFFFUL << RTC_BKP27R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP27R                     RTC_BKP27R_Msk

+

+/********************  Bits definition for RTC_BKP28R register  ***************/

+#define RTC_BKP28R_Pos                 (0U)

+#define RTC_BKP28R_Msk                 (0xFFFFFFFFUL << RTC_BKP28R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP28R                     RTC_BKP28R_Msk

+

+/********************  Bits definition for RTC_BKP29R register  ***************/

+#define RTC_BKP29R_Pos                 (0U)

+#define RTC_BKP29R_Msk                 (0xFFFFFFFFUL << RTC_BKP29R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP29R                     RTC_BKP29R_Msk

+

+/********************  Bits definition for RTC_BKP30R register  ***************/

+#define RTC_BKP30R_Pos                 (0U)

+#define RTC_BKP30R_Msk                 (0xFFFFFFFFUL << RTC_BKP30R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP30R                     RTC_BKP30R_Msk

+

+/********************  Bits definition for RTC_BKP31R register  ***************/

+#define RTC_BKP31R_Pos                 (0U)

+#define RTC_BKP31R_Msk                 (0xFFFFFFFFUL << RTC_BKP31R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP31R                     RTC_BKP31R_Msk

+

+/******************** Number of backup registers ******************************/

+#define RTC_BKP_NUMBER_Pos             (5U)

+#define RTC_BKP_NUMBER_Msk             (0x1UL << RTC_BKP_NUMBER_Pos)           /*!< 0x00000020 */

+#define RTC_BKP_NUMBER                 RTC_BKP_NUMBER_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                              SPDIF-RX Interface                            */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for SPDIF_CR register  ******************/

+#define SPDIFRX_CR_SPDIFEN_Pos      (0U)

+#define SPDIFRX_CR_SPDIFEN_Msk      (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)          /*!< 0x00000003 */

+#define SPDIFRX_CR_SPDIFEN          SPDIFRX_CR_SPDIFEN_Msk                     /*!<Peripheral Block Enable                      */

+#define SPDIFRX_CR_RXDMAEN_Pos      (2U)

+#define SPDIFRX_CR_RXDMAEN_Msk      (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)          /*!< 0x00000004 */

+#define SPDIFRX_CR_RXDMAEN          SPDIFRX_CR_RXDMAEN_Msk                     /*!<Receiver DMA Enable for data flow            */

+#define SPDIFRX_CR_RXSTEO_Pos       (3U)

+#define SPDIFRX_CR_RXSTEO_Msk       (0x1UL << SPDIFRX_CR_RXSTEO_Pos)           /*!< 0x00000008 */

+#define SPDIFRX_CR_RXSTEO           SPDIFRX_CR_RXSTEO_Msk                      /*!<Stereo Mode                                  */

+#define SPDIFRX_CR_DRFMT_Pos        (4U)

+#define SPDIFRX_CR_DRFMT_Msk        (0x3UL << SPDIFRX_CR_DRFMT_Pos)            /*!< 0x00000030 */

+#define SPDIFRX_CR_DRFMT            SPDIFRX_CR_DRFMT_Msk                       /*!<RX Data format                               */

+#define SPDIFRX_CR_PMSK_Pos         (6U)

+#define SPDIFRX_CR_PMSK_Msk         (0x1UL << SPDIFRX_CR_PMSK_Pos)             /*!< 0x00000040 */

+#define SPDIFRX_CR_PMSK             SPDIFRX_CR_PMSK_Msk                        /*!<Mask Parity error bit                        */

+#define SPDIFRX_CR_VMSK_Pos         (7U)

+#define SPDIFRX_CR_VMSK_Msk         (0x1UL << SPDIFRX_CR_VMSK_Pos)             /*!< 0x00000080 */

+#define SPDIFRX_CR_VMSK             SPDIFRX_CR_VMSK_Msk                        /*!<Mask of Validity bit                         */

+#define SPDIFRX_CR_CUMSK_Pos        (8U)

+#define SPDIFRX_CR_CUMSK_Msk        (0x1UL << SPDIFRX_CR_CUMSK_Pos)            /*!< 0x00000100 */

+#define SPDIFRX_CR_CUMSK            SPDIFRX_CR_CUMSK_Msk                       /*!<Mask of channel status and user bits         */

+#define SPDIFRX_CR_PTMSK_Pos        (9U)

+#define SPDIFRX_CR_PTMSK_Msk        (0x1UL << SPDIFRX_CR_PTMSK_Pos)            /*!< 0x00000200 */

+#define SPDIFRX_CR_PTMSK            SPDIFRX_CR_PTMSK_Msk                       /*!<Mask of Preamble Type bits                   */

+#define SPDIFRX_CR_CBDMAEN_Pos      (10U)

+#define SPDIFRX_CR_CBDMAEN_Msk      (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)          /*!< 0x00000400 */

+#define SPDIFRX_CR_CBDMAEN          SPDIFRX_CR_CBDMAEN_Msk                     /*!<Control Buffer DMA ENable for control flow   */

+#define SPDIFRX_CR_CHSEL_Pos        (11U)

+#define SPDIFRX_CR_CHSEL_Msk        (0x1UL << SPDIFRX_CR_CHSEL_Pos)            /*!< 0x00000800 */

+#define SPDIFRX_CR_CHSEL            SPDIFRX_CR_CHSEL_Msk                       /*!<Channel Selection                            */

+#define SPDIFRX_CR_NBTR_Pos         (12U)

+#define SPDIFRX_CR_NBTR_Msk         (0x3UL << SPDIFRX_CR_NBTR_Pos)             /*!< 0x00003000 */

+#define SPDIFRX_CR_NBTR             SPDIFRX_CR_NBTR_Msk                        /*!<Maximum allowed re-tries during synchronization phase */

+#define SPDIFRX_CR_WFA_Pos          (14U)

+#define SPDIFRX_CR_WFA_Msk          (0x1UL << SPDIFRX_CR_WFA_Pos)              /*!< 0x00004000 */

+#define SPDIFRX_CR_WFA              SPDIFRX_CR_WFA_Msk                         /*!<Wait For Activity     */

+#define SPDIFRX_CR_INSEL_Pos        (16U)

+#define SPDIFRX_CR_INSEL_Msk        (0x7UL << SPDIFRX_CR_INSEL_Pos)            /*!< 0x00070000 */

+#define SPDIFRX_CR_INSEL            SPDIFRX_CR_INSEL_Msk                       /*!<SPDIF input selection */

+#define SPDIFRX_CR_CKSEN_Pos        (20U)

+#define SPDIFRX_CR_CKSEN_Msk        (0x1UL << SPDIFRX_CR_CKSEN_Pos)            /*!< 0x00100000 */

+#define SPDIFRX_CR_CKSEN            SPDIFRX_CR_CKSEN_Msk                       /*!<Symbol Clock Enable */

+#define SPDIFRX_CR_CKSBKPEN_Pos     (21U)

+#define SPDIFRX_CR_CKSBKPEN_Msk     (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)         /*!< 0x00200000 */

+#define SPDIFRX_CR_CKSBKPEN         SPDIFRX_CR_CKSBKPEN_Msk                    /*!<Backup Symbol Clock Enable */

+

+/*******************  Bit definition for SPDIFRX_IMR register  *******************/

+#define SPDIFRX_IMR_RXNEIE_Pos      (0U)

+#define SPDIFRX_IMR_RXNEIE_Msk      (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)          /*!< 0x00000001 */

+#define SPDIFRX_IMR_RXNEIE          SPDIFRX_IMR_RXNEIE_Msk                     /*!<RXNE interrupt enable                              */

+#define SPDIFRX_IMR_CSRNEIE_Pos     (1U)

+#define SPDIFRX_IMR_CSRNEIE_Msk     (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)         /*!< 0x00000002 */

+#define SPDIFRX_IMR_CSRNEIE         SPDIFRX_IMR_CSRNEIE_Msk                    /*!<Control Buffer Ready Interrupt Enable              */

+#define SPDIFRX_IMR_PERRIE_Pos      (2U)

+#define SPDIFRX_IMR_PERRIE_Msk      (0x1UL << SPDIFRX_IMR_PERRIE_Pos)          /*!< 0x00000004 */

+#define SPDIFRX_IMR_PERRIE          SPDIFRX_IMR_PERRIE_Msk                     /*!<Parity error interrupt enable                      */

+#define SPDIFRX_IMR_OVRIE_Pos       (3U)

+#define SPDIFRX_IMR_OVRIE_Msk       (0x1UL << SPDIFRX_IMR_OVRIE_Pos)           /*!< 0x00000008 */

+#define SPDIFRX_IMR_OVRIE           SPDIFRX_IMR_OVRIE_Msk                      /*!<Overrun error Interrupt Enable                     */

+#define SPDIFRX_IMR_SBLKIE_Pos      (4U)

+#define SPDIFRX_IMR_SBLKIE_Msk      (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)          /*!< 0x00000010 */

+#define SPDIFRX_IMR_SBLKIE          SPDIFRX_IMR_SBLKIE_Msk                     /*!<Synchronization Block Detected Interrupt Enable    */

+#define SPDIFRX_IMR_SYNCDIE_Pos     (5U)

+#define SPDIFRX_IMR_SYNCDIE_Msk     (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)         /*!< 0x00000020 */

+#define SPDIFRX_IMR_SYNCDIE         SPDIFRX_IMR_SYNCDIE_Msk                    /*!<Synchronization Done                               */

+#define SPDIFRX_IMR_IFEIE_Pos       (6U)

+#define SPDIFRX_IMR_IFEIE_Msk       (0x1UL << SPDIFRX_IMR_IFEIE_Pos)           /*!< 0x00000040 */

+#define SPDIFRX_IMR_IFEIE           SPDIFRX_IMR_IFEIE_Msk                      /*!<Serial Interface Error Interrupt Enable            */

+

+/*******************  Bit definition for SPDIFRX_SR register  *******************/

+#define SPDIFRX_SR_RXNE_Pos         (0U)

+#define SPDIFRX_SR_RXNE_Msk         (0x1UL << SPDIFRX_SR_RXNE_Pos)             /*!< 0x00000001 */

+#define SPDIFRX_SR_RXNE             SPDIFRX_SR_RXNE_Msk                        /*!<Read data register not empty                          */

+#define SPDIFRX_SR_CSRNE_Pos        (1U)

+#define SPDIFRX_SR_CSRNE_Msk        (0x1UL << SPDIFRX_SR_CSRNE_Pos)            /*!< 0x00000002 */

+#define SPDIFRX_SR_CSRNE            SPDIFRX_SR_CSRNE_Msk                       /*!<The Control Buffer register is not empty              */

+#define SPDIFRX_SR_PERR_Pos         (2U)

+#define SPDIFRX_SR_PERR_Msk         (0x1UL << SPDIFRX_SR_PERR_Pos)             /*!< 0x00000004 */

+#define SPDIFRX_SR_PERR             SPDIFRX_SR_PERR_Msk                        /*!<Parity error                                          */

+#define SPDIFRX_SR_OVR_Pos          (3U)

+#define SPDIFRX_SR_OVR_Msk          (0x1UL << SPDIFRX_SR_OVR_Pos)              /*!< 0x00000008 */

+#define SPDIFRX_SR_OVR              SPDIFRX_SR_OVR_Msk                         /*!<Overrun error                                         */

+#define SPDIFRX_SR_SBD_Pos          (4U)

+#define SPDIFRX_SR_SBD_Msk          (0x1UL << SPDIFRX_SR_SBD_Pos)              /*!< 0x00000010 */

+#define SPDIFRX_SR_SBD              SPDIFRX_SR_SBD_Msk                         /*!<Synchronization Block Detected                        */

+#define SPDIFRX_SR_SYNCD_Pos        (5U)

+#define SPDIFRX_SR_SYNCD_Msk        (0x1UL << SPDIFRX_SR_SYNCD_Pos)            /*!< 0x00000020 */

+#define SPDIFRX_SR_SYNCD            SPDIFRX_SR_SYNCD_Msk                       /*!<Synchronization Done                                  */

+#define SPDIFRX_SR_FERR_Pos         (6U)

+#define SPDIFRX_SR_FERR_Msk         (0x1UL << SPDIFRX_SR_FERR_Pos)             /*!< 0x00000040 */

+#define SPDIFRX_SR_FERR             SPDIFRX_SR_FERR_Msk                        /*!<Framing error                                         */

+#define SPDIFRX_SR_SERR_Pos         (7U)

+#define SPDIFRX_SR_SERR_Msk         (0x1UL << SPDIFRX_SR_SERR_Pos)             /*!< 0x00000080 */

+#define SPDIFRX_SR_SERR             SPDIFRX_SR_SERR_Msk                        /*!<Synchronization error                                 */

+#define SPDIFRX_SR_TERR_Pos         (8U)

+#define SPDIFRX_SR_TERR_Msk         (0x1UL << SPDIFRX_SR_TERR_Pos)             /*!< 0x00000100 */

+#define SPDIFRX_SR_TERR             SPDIFRX_SR_TERR_Msk                        /*!<Time-out error                                        */

+#define SPDIFRX_SR_WIDTH5_Pos       (16U)

+#define SPDIFRX_SR_WIDTH5_Msk       (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)        /*!< 0x7FFF0000 */

+#define SPDIFRX_SR_WIDTH5           SPDIFRX_SR_WIDTH5_Msk                      /*!<Duration of 5 symbols counted with spdif_clk          */

+

+/*******************  Bit definition for SPDIFRX_IFCR register  *******************/

+#define SPDIFRX_IFCR_PERRCF_Pos     (2U)

+#define SPDIFRX_IFCR_PERRCF_Msk     (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)         /*!< 0x00000004 */

+#define SPDIFRX_IFCR_PERRCF         SPDIFRX_IFCR_PERRCF_Msk                    /*!<Clears the Parity error flag                         */

+#define SPDIFRX_IFCR_OVRCF_Pos      (3U)

+#define SPDIFRX_IFCR_OVRCF_Msk      (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)          /*!< 0x00000008 */

+#define SPDIFRX_IFCR_OVRCF          SPDIFRX_IFCR_OVRCF_Msk                     /*!<Clears the Overrun error flag                        */

+#define SPDIFRX_IFCR_SBDCF_Pos      (4U)

+#define SPDIFRX_IFCR_SBDCF_Msk      (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)          /*!< 0x00000010 */

+#define SPDIFRX_IFCR_SBDCF          SPDIFRX_IFCR_SBDCF_Msk                     /*!<Clears the Synchronization Block Detected flag       */

+#define SPDIFRX_IFCR_SYNCDCF_Pos    (5U)

+#define SPDIFRX_IFCR_SYNCDCF_Msk    (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)        /*!< 0x00000020 */

+#define SPDIFRX_IFCR_SYNCDCF        SPDIFRX_IFCR_SYNCDCF_Msk                   /*!<Clears the Synchronization Done flag                 */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/

+#define SPDIFRX_DR0_DR_Pos          (0U)

+#define SPDIFRX_DR0_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)         /*!< 0x00FFFFFF */

+#define SPDIFRX_DR0_DR              SPDIFRX_DR0_DR_Msk                         /*!<Data value            */

+#define SPDIFRX_DR0_PE_Pos          (24U)

+#define SPDIFRX_DR0_PE_Msk          (0x1UL << SPDIFRX_DR0_PE_Pos)              /*!< 0x01000000 */

+#define SPDIFRX_DR0_PE              SPDIFRX_DR0_PE_Msk                         /*!<Parity Error bit      */

+#define SPDIFRX_DR0_V_Pos           (25U)

+#define SPDIFRX_DR0_V_Msk           (0x1UL << SPDIFRX_DR0_V_Pos)               /*!< 0x02000000 */

+#define SPDIFRX_DR0_V               SPDIFRX_DR0_V_Msk                          /*!<Validity bit          */

+#define SPDIFRX_DR0_U_Pos           (26U)

+#define SPDIFRX_DR0_U_Msk           (0x1UL << SPDIFRX_DR0_U_Pos)               /*!< 0x04000000 */

+#define SPDIFRX_DR0_U               SPDIFRX_DR0_U_Msk                          /*!<User bit              */

+#define SPDIFRX_DR0_C_Pos           (27U)

+#define SPDIFRX_DR0_C_Msk           (0x1UL << SPDIFRX_DR0_C_Pos)               /*!< 0x08000000 */

+#define SPDIFRX_DR0_C               SPDIFRX_DR0_C_Msk                          /*!<Channel Status bit    */

+#define SPDIFRX_DR0_PT_Pos          (28U)

+#define SPDIFRX_DR0_PT_Msk          (0x3UL << SPDIFRX_DR0_PT_Pos)              /*!< 0x30000000 */

+#define SPDIFRX_DR0_PT              SPDIFRX_DR0_PT_Msk                         /*!<Preamble Type         */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/

+#define SPDIFRX_DR1_DR_Pos          (8U)

+#define SPDIFRX_DR1_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)         /*!< 0xFFFFFF00 */

+#define SPDIFRX_DR1_DR              SPDIFRX_DR1_DR_Msk                         /*!<Data value            */

+#define SPDIFRX_DR1_PT_Pos          (4U)

+#define SPDIFRX_DR1_PT_Msk          (0x3UL << SPDIFRX_DR1_PT_Pos)              /*!< 0x00000030 */

+#define SPDIFRX_DR1_PT              SPDIFRX_DR1_PT_Msk                         /*!<Preamble Type         */

+#define SPDIFRX_DR1_C_Pos           (3U)

+#define SPDIFRX_DR1_C_Msk           (0x1UL << SPDIFRX_DR1_C_Pos)               /*!< 0x00000008 */

+#define SPDIFRX_DR1_C               SPDIFRX_DR1_C_Msk                          /*!<Channel Status bit    */

+#define SPDIFRX_DR1_U_Pos           (2U)

+#define SPDIFRX_DR1_U_Msk           (0x1UL << SPDIFRX_DR1_U_Pos)               /*!< 0x00000004 */

+#define SPDIFRX_DR1_U               SPDIFRX_DR1_U_Msk                          /*!<User bit              */

+#define SPDIFRX_DR1_V_Pos           (1U)

+#define SPDIFRX_DR1_V_Msk           (0x1UL << SPDIFRX_DR1_V_Pos)               /*!< 0x00000002 */

+#define SPDIFRX_DR1_V               SPDIFRX_DR1_V_Msk                          /*!<Validity bit          */

+#define SPDIFRX_DR1_PE_Pos          (0U)

+#define SPDIFRX_DR1_PE_Msk          (0x1UL << SPDIFRX_DR1_PE_Pos)              /*!< 0x00000001 */

+#define SPDIFRX_DR1_PE              SPDIFRX_DR1_PE_Msk                         /*!<Parity Error bit      */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/

+#define SPDIFRX_DR1_DRNL1_Pos       (16U)

+#define SPDIFRX_DR1_DRNL1_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)        /*!< 0xFFFF0000 */

+#define SPDIFRX_DR1_DRNL1           SPDIFRX_DR1_DRNL1_Msk                      /*!<Data value Channel B      */

+#define SPDIFRX_DR1_DRNL2_Pos       (0U)

+#define SPDIFRX_DR1_DRNL2_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)        /*!< 0x0000FFFF */

+#define SPDIFRX_DR1_DRNL2           SPDIFRX_DR1_DRNL2_Msk                      /*!<Data value Channel A      */

+

+/*******************  Bit definition for SPDIFRX_CSR register   *******************/

+#define SPDIFRX_CSR_USR_Pos         (0U)

+#define SPDIFRX_CSR_USR_Msk         (0xFFFFUL << SPDIFRX_CSR_USR_Pos)          /*!< 0x0000FFFF */

+#define SPDIFRX_CSR_USR             SPDIFRX_CSR_USR_Msk                        /*!<User data information           */

+#define SPDIFRX_CSR_CS_Pos          (16U)

+#define SPDIFRX_CSR_CS_Msk          (0xFFUL << SPDIFRX_CSR_CS_Pos)             /*!< 0x00FF0000 */

+#define SPDIFRX_CSR_CS              SPDIFRX_CSR_CS_Msk                         /*!<Channel A status information    */

+#define SPDIFRX_CSR_SOB_Pos         (24U)

+#define SPDIFRX_CSR_SOB_Msk         (0x1UL << SPDIFRX_CSR_SOB_Pos)             /*!< 0x01000000 */

+#define SPDIFRX_CSR_SOB             SPDIFRX_CSR_SOB_Msk                        /*!<Start Of Block                  */

+

+/*******************  Bit definition for SPDIFRX_DIR register    *******************/

+#define SPDIFRX_DIR_THI_Pos         (0U)

+#define SPDIFRX_DIR_THI_Msk         (0x1FFFUL << SPDIFRX_DIR_THI_Pos)          /*!< 0x00001FFF */

+#define SPDIFRX_DIR_THI             SPDIFRX_DIR_THI_Msk                        /*!<Threshold LOW      */

+#define SPDIFRX_DIR_TLO_Pos         (16U)

+#define SPDIFRX_DIR_TLO_Msk         (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)          /*!< 0x1FFF0000 */

+#define SPDIFRX_DIR_TLO             SPDIFRX_DIR_TLO_Msk                        /*!<Threshold HIGH     */

+

+/*******************  Bit definition for SPDIFRX_VERR register    *******************/

+#define SPDIFRX_VERR_MINREV_Pos     (0U)

+#define SPDIFRX_VERR_MINREV_Msk     (0xFUL << SPDIFRX_VERR_MINREV_Pos)         /*!< 0x0000000F */

+#define SPDIFRX_VERR_MINREV         SPDIFRX_VERR_MINREV_Msk                    /*!<SPDIFRX Minor revision     */

+#define SPDIFRX_VERR_MAJREV_Pos     (4U)

+#define SPDIFRX_VERR_MAJREV_Msk     (0xFUL << SPDIFRX_VERR_MAJREV_Pos)         /*!< 0x000000F0 */

+#define SPDIFRX_VERR_MAJREV         SPDIFRX_VERR_MAJREV_Msk                    /*!<SPDIFRX Major revision     */

+

+/*******************  Bit definition for SPDIFRX_IDR register    *******************/

+#define SPDIFRX_IDR_ID_Pos          (0U)

+#define SPDIFRX_IDR_ID_Msk          (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos)       /*!< 0xFFFFFFFF */

+#define SPDIFRX_IDR_ID              SPDIFRX_IDR_ID_Msk                         /*!<SPDIFRX identifier     */

+

+/*******************  Bit definition for SPDIFRX_SIDR register    *******************/

+#define SPDIFRX_SIDR_SID_Pos        (0U)

+#define SPDIFRX_SIDR_SID_Msk        (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos)     /*!< 0xFFFFFFFF */

+#define SPDIFRX_SIDR_SID            SPDIFRX_SIDR_SID_Msk                       /*!<Size of the memory region allocated to SPDIFRX registers */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          Serial Audio Interface                            */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  SAI VERSION  ********************************/

+#define SAI_VER_V2_X

+

+/********************  Bit definition for SAI_GCR register  *******************/

+#define SAI_GCR_SYNCIN_Pos         (0U)

+#define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000003 */

+#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */

+#define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */

+#define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */

+

+#define SAI_GCR_SYNCOUT_Pos        (4U)

+#define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000030 */

+#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */

+#define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */

+#define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */

+

+/*******************  Bit definition for SAI_xCR1 register  *******************/

+#define SAI_xCR1_MODE_Pos          (0U)

+#define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */

+#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */

+#define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */

+#define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */

+

+#define SAI_xCR1_PRTCFG_Pos        (2U)

+#define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */

+#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */

+#define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */

+#define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */

+

+#define SAI_xCR1_DS_Pos            (5U)

+#define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */

+#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */

+#define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */

+#define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */

+#define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */

+

+#define SAI_xCR1_LSBFIRST_Pos      (8U)

+#define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */

+#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */

+#define SAI_xCR1_CKSTR_Pos         (9U)

+#define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */

+#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */

+

+#define SAI_xCR1_SYNCEN_Pos        (10U)

+#define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */

+#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */

+#define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */

+#define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */

+

+#define SAI_xCR1_MONO_Pos          (12U)

+#define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */

+#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */

+#define SAI_xCR1_OUTDRIV_Pos       (13U)

+#define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */

+#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */

+#define SAI_xCR1_SAIEN_Pos         (16U)

+#define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */

+#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */

+#define SAI_xCR1_DMAEN_Pos         (17U)

+#define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */

+#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */

+#define SAI_xCR1_NODIV_Pos         (19U)

+#define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */

+#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */

+

+#define SAI_xCR1_MCKDIV_Pos        (20U)

+#define SAI_xCR1_MCKDIV_Msk        (0x3FUL << SAI_xCR1_MCKDIV_Pos)             /*!< 0x03F00000 */

+#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[5:0] (Master ClocK Divider)  */

+#define SAI_xCR1_MCKDIV_0          (0x01UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00100000 */

+#define SAI_xCR1_MCKDIV_1          (0x02UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00200000 */

+#define SAI_xCR1_MCKDIV_2          (0x04UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00400000 */

+#define SAI_xCR1_MCKDIV_3          (0x08UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00800000 */

+#define SAI_xCR1_MCKDIV_4          (0x10UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x01000000 */

+#define SAI_xCR1_MCKDIV_5          (0x20UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x02000000 */

+

+#define SAI_xCR1_MCKEN_Pos         (27U)

+#define SAI_xCR1_MCKEN_Msk         (0x1UL << SAI_xCR1_MCKEN_Pos)               /*!< 0x08000000 */

+#define SAI_xCR1_MCKEN             SAI_xCR1_MCKEN_Msk                          /*!<Master ClocK enable */

+

+#define SAI_xCR1_OSR_Pos           (26U)

+#define SAI_xCR1_OSR_Msk           (0x1UL << SAI_xCR1_OSR_Pos)                 /*!< 0x04000000 */

+#define SAI_xCR1_OSR               SAI_xCR1_OSR_Msk                            /*!<OverSampling Ratio for master clock  */

+

+/* Legacy define */

+#define  SAI_xCR1_NOMCK               SAI_xCR1_NODIV

+

+/*******************  Bit definition for SAI_xCR2 register  *******************/

+#define SAI_xCR2_FTH_Pos           (0U)

+#define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */

+#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */

+#define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */

+#define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */

+#define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */

+

+#define SAI_xCR2_FFLUSH_Pos        (3U)

+#define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */

+#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */

+#define SAI_xCR2_TRIS_Pos          (4U)

+#define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */

+#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */

+#define SAI_xCR2_MUTE_Pos          (5U)

+#define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */

+#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */

+#define SAI_xCR2_MUTEVAL_Pos       (6U)

+#define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */

+#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */

+

+#define SAI_xCR2_MUTECNT_Pos       (7U)

+#define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */

+#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */

+#define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */

+#define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */

+#define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */

+#define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */

+#define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */

+#define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */

+

+#define SAI_xCR2_CPL_Pos           (13U)

+#define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */

+#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */

+

+#define SAI_xCR2_COMP_Pos          (14U)

+#define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */

+#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */

+#define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */

+#define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */

+

+/******************  Bit definition for SAI_xFRCR register  *******************/

+#define SAI_xFRCR_FRL_Pos          (0U)

+#define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */

+#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](FRame Length)  */

+#define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */

+#define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */

+#define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */

+#define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */

+#define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */

+#define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */

+#define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */

+#define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */

+

+#define SAI_xFRCR_FSALL_Pos        (8U)

+#define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */

+#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FSALL[6:0] (Frame Synchronization Active Level Length)  */

+#define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */

+#define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */

+#define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */

+#define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */

+#define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */

+#define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */

+#define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */

+

+#define SAI_xFRCR_FSDEF_Pos        (16U)

+#define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */

+#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!<Frame Synchronization Definition  */

+#define SAI_xFRCR_FSPOL_Pos        (17U)

+#define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */

+#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */

+#define SAI_xFRCR_FSOFF_Pos        (18U)

+#define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */

+#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */

+

+/* Legacy define */

+#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL

+

+/******************  Bit definition for SAI_xSLOTR register  *******************/

+#define SAI_xSLOTR_FBOFF_Pos       (0U)

+#define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */

+#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FBOFF[4:0](First Bit Offset)  */

+#define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */

+#define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */

+#define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */

+#define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */

+#define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */

+

+#define SAI_xSLOTR_SLOTSZ_Pos      (6U)

+#define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */

+#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */

+#define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */

+#define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */

+

+#define SAI_xSLOTR_NBSLOT_Pos      (8U)

+#define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */

+#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */

+#define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */

+#define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */

+#define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */

+#define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */

+

+#define SAI_xSLOTR_SLOTEN_Pos      (16U)

+#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */

+#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */

+

+/*******************  Bit definition for SAI_xIMR register  *******************/

+#define SAI_xIMR_OVRUDRIE_Pos      (0U)

+#define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */

+#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */

+#define SAI_xIMR_MUTEDETIE_Pos     (1U)

+#define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */

+#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */

+#define SAI_xIMR_WCKCFGIE_Pos      (2U)

+#define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */

+#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */

+#define SAI_xIMR_FREQIE_Pos        (3U)

+#define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */

+#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */

+#define SAI_xIMR_CNRDYIE_Pos       (4U)

+#define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */

+#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */

+#define SAI_xIMR_AFSDETIE_Pos      (5U)

+#define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */

+#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */

+#define SAI_xIMR_LFSDETIE_Pos      (6U)

+#define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */

+#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */

+

+/********************  Bit definition for SAI_xSR register  *******************/

+#define SAI_xSR_OVRUDR_Pos         (0U)

+#define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */

+#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */

+#define SAI_xSR_MUTEDET_Pos        (1U)

+#define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */

+#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */

+#define SAI_xSR_WCKCFG_Pos         (2U)

+#define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */

+#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */

+#define SAI_xSR_FREQ_Pos           (3U)

+#define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */

+#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */

+#define SAI_xSR_CNRDY_Pos          (4U)

+#define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */

+#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */

+#define SAI_xSR_AFSDET_Pos         (5U)

+#define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */

+#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */

+#define SAI_xSR_LFSDET_Pos         (6U)

+#define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */

+#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */

+

+#define SAI_xSR_FLVL_Pos           (16U)

+#define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */

+#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */

+#define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */

+#define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */

+#define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */

+

+/******************  Bit definition for SAI_xCLRFR register  ******************/

+#define SAI_xCLRFR_COVRUDR_Pos     (0U)

+#define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */

+#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */

+#define SAI_xCLRFR_CMUTEDET_Pos    (1U)

+#define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */

+#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */

+#define SAI_xCLRFR_CWCKCFG_Pos     (2U)

+#define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */

+#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */

+#define SAI_xCLRFR_CFREQ_Pos       (3U)

+#define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */

+#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */

+#define SAI_xCLRFR_CCNRDY_Pos      (4U)

+#define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */

+#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */

+#define SAI_xCLRFR_CAFSDET_Pos     (5U)

+#define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */

+#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */

+#define SAI_xCLRFR_CLFSDET_Pos     (6U)

+#define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */

+#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */

+

+/******************  Bit definition for SAI_xDR register  *********************/

+#define SAI_xDR_DATA_Pos           (0U)

+#define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */

+#define SAI_xDR_DATA               SAI_xDR_DATA_Msk

+

+/*******************  Bit definition for SAI_PDMCR register  ******************/

+#define SAI_PDMCR_PDMEN_Pos        (0U)

+#define SAI_PDMCR_PDMEN_Msk        (0x1UL << SAI_PDMCR_PDMEN_Pos)              /*!< 0x00000001 */

+#define SAI_PDMCR_PDMEN            SAI_PDMCR_PDMEN_Msk                         /*!<PDM Enable                                          */

+

+#define SAI_PDMCR_MICNBR_Pos       (4U)

+#define SAI_PDMCR_MICNBR_Msk       (0x3UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000030 */

+#define SAI_PDMCR_MICNBR           SAI_PDMCR_MICNBR_Msk                        /*!<Number of microphones                               */

+#define SAI_PDMCR_MICNBR_0         (0x1UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000010 */

+#define SAI_PDMCR_MICNBR_1         (0x2UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000020 */

+

+#define SAI_PDMCR_CKEN1_Pos        (8U)

+#define SAI_PDMCR_CKEN1_Msk        (0x1UL << SAI_PDMCR_CKEN1_Pos)              /*!< 0x00000100 */

+#define SAI_PDMCR_CKEN1            SAI_PDMCR_CKEN1_Msk                         /*!<Clock enable of bitstream clock number 1            */

+#define SAI_PDMCR_CKEN2_Pos        (9U)

+#define SAI_PDMCR_CKEN2_Msk        (0x1UL << SAI_PDMCR_CKEN2_Pos)              /*!< 0x00000200 */

+#define SAI_PDMCR_CKEN2            SAI_PDMCR_CKEN2_Msk                         /*!<Clock enable of bitstream clock number 2            */

+#define SAI_PDMCR_CKEN3_Pos        (10U)

+#define SAI_PDMCR_CKEN3_Msk        (0x1UL << SAI_PDMCR_CKEN3_Pos)              /*!< 0x00000400 */

+#define SAI_PDMCR_CKEN3            SAI_PDMCR_CKEN3_Msk                         /*!<Clock enable of bitstream clock number 3            */

+#define SAI_PDMCR_CKEN4_Pos        (11U)

+#define SAI_PDMCR_CKEN4_Msk        (0x1UL << SAI_PDMCR_CKEN4_Pos)              /*!< 0x00000800 */

+#define SAI_PDMCR_CKEN4            SAI_PDMCR_CKEN4_Msk                         /*!<Clock enable of bitstream clock number 4            */

+

+/******************  Bit definition for SAI_PDMDLY register  ******************/

+#define SAI_PDMDLY_DLYM1L_Pos      (0U)

+#define SAI_PDMDLY_DLYM1L_Msk      (0x7UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000007 */

+#define SAI_PDMDLY_DLYM1L          SAI_PDMDLY_DLYM1L_Msk                       /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */

+#define SAI_PDMDLY_DLYM1L_0        (0x1UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000001 */

+#define SAI_PDMDLY_DLYM1L_1        (0x2UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000002 */

+#define SAI_PDMDLY_DLYM1L_2        (0x4UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000004 */

+

+#define SAI_PDMDLY_DLYM1R_Pos      (4U)

+#define SAI_PDMDLY_DLYM1R_Msk      (0x7UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000070 */

+#define SAI_PDMDLY_DLYM1R          SAI_PDMDLY_DLYM1R_Msk                       /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */

+#define SAI_PDMDLY_DLYM1R_0        (0x1UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000010 */

+#define SAI_PDMDLY_DLYM1R_1        (0x2UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000020 */

+#define SAI_PDMDLY_DLYM1R_2        (0x4UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000040 */

+

+#define SAI_PDMDLY_DLYM2L_Pos      (8U)

+#define SAI_PDMDLY_DLYM2L_Msk      (0x7UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000700 */

+#define SAI_PDMDLY_DLYM2L          SAI_PDMDLY_DLYM2L_Msk                       /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */

+#define SAI_PDMDLY_DLYM2L_0        (0x1UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000100 */

+#define SAI_PDMDLY_DLYM2L_1        (0x2UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000200 */

+#define SAI_PDMDLY_DLYM2L_2        (0x4UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000400 */

+

+#define SAI_PDMDLY_DLYM2R_Pos      (12U)

+#define SAI_PDMDLY_DLYM2R_Msk      (0x7UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00007000 */

+#define SAI_PDMDLY_DLYM2R          SAI_PDMDLY_DLYM2R_Msk                       /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/

+#define SAI_PDMDLY_DLYM2R_0        (0x1UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00001000 */

+#define SAI_PDMDLY_DLYM2R_1        (0x2UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00002000 */

+#define SAI_PDMDLY_DLYM2R_2        (0x4UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00004000 */

+

+#define SAI_PDMDLY_DLYM3L_Pos      (16U)

+#define SAI_PDMDLY_DLYM3L_Msk      (0x7UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00070000 */

+#define SAI_PDMDLY_DLYM3L          SAI_PDMDLY_DLYM3L_Msk                       /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/

+#define SAI_PDMDLY_DLYM3L_0        (0x1UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00010000 */

+#define SAI_PDMDLY_DLYM3L_1        (0x2UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00020000 */

+#define SAI_PDMDLY_DLYM3L_2        (0x4UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00040000 */

+

+#define SAI_PDMDLY_DLYM3R_Pos      (20U)

+#define SAI_PDMDLY_DLYM3R_Msk      (0x7UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00700000 */

+#define SAI_PDMDLY_DLYM3R          SAI_PDMDLY_DLYM3R_Msk                       /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/

+#define SAI_PDMDLY_DLYM3R_0        (0x1UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00100000 */

+#define SAI_PDMDLY_DLYM3R_1        (0x2UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00200000 */

+#define SAI_PDMDLY_DLYM3R_2        (0x4UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00400000 */

+

+#define SAI_PDMDLY_DLYM4L_Pos      (24U)

+#define SAI_PDMDLY_DLYM4L_Msk      (0x7UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x07000000 */

+#define SAI_PDMDLY_DLYM4L          SAI_PDMDLY_DLYM4L_Msk                       /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/

+#define SAI_PDMDLY_DLYM4L_0        (0x1UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x01000000 */

+#define SAI_PDMDLY_DLYM4L_1        (0x2UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x02000000 */

+#define SAI_PDMDLY_DLYM4L_2        (0x4UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x04000000 */

+

+#define SAI_PDMDLY_DLYM4R_Pos      (28U)

+#define SAI_PDMDLY_DLYM4R_Msk      (0x7UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x70000000 */

+#define SAI_PDMDLY_DLYM4R          SAI_PDMDLY_DLYM4R_Msk                       /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/

+#define SAI_PDMDLY_DLYM4R_0        (0x1UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x10000000 */

+#define SAI_PDMDLY_DLYM4R_1        (0x2UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x20000000 */

+#define SAI_PDMDLY_DLYM4R_2        (0x4UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x40000000 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           SDMMC Interface                                  */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for SDMMC_POWER register  ******************/

+#define SDMMC_POWER_PWRCTRL_Pos          (0U)

+#define SDMMC_POWER_PWRCTRL_Msk          (0x3UL << SDMMC_POWER_PWRCTRL_Pos)    /*!< 0x00000003 */

+#define SDMMC_POWER_PWRCTRL              SDMMC_POWER_PWRCTRL_Msk               /*!<PWRCTRL[1:0] bits (Power supply control bits) */

+#define SDMMC_POWER_PWRCTRL_0            (0x1UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000001 */

+#define SDMMC_POWER_PWRCTRL_1            (0x2UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000002 */

+#define SDMMC_POWER_VSWITCH_Pos          (2U)

+#define SDMMC_POWER_VSWITCH_Msk          (0x1UL << SDMMC_POWER_VSWITCH_Pos)    /*!< 0x00000004 */

+#define SDMMC_POWER_VSWITCH              SDMMC_POWER_VSWITCH_Msk               /*!<Voltage switch sequence start */

+#define SDMMC_POWER_VSWITCHEN_Pos        (3U)

+#define SDMMC_POWER_VSWITCHEN_Msk        (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)  /*!< 0x00000008 */

+#define SDMMC_POWER_VSWITCHEN            SDMMC_POWER_VSWITCHEN_Msk             /*!<Voltage switch procedure enable */

+#define SDMMC_POWER_DIRPOL_Pos           (4U)

+#define SDMMC_POWER_DIRPOL_Msk           (0x1UL << SDMMC_POWER_DIRPOL_Pos)     /*!< 0x00000010 */

+#define SDMMC_POWER_DIRPOL               SDMMC_POWER_DIRPOL_Msk                /*!<Data and Command direction signals polarity selection */

+

+/******************  Bit definition for SDMMC_CLKCR register  ******************/

+#define SDMMC_CLKCR_CLKDIV_Pos           (0U)

+#define SDMMC_CLKCR_CLKDIV_Msk           (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)   /*!< 0x000003FF */

+#define SDMMC_CLKCR_CLKDIV               SDMMC_CLKCR_CLKDIV_Msk                /*!<Clock divide factor             */

+#define SDMMC_CLKCR_PWRSAV_Pos           (12U)

+#define SDMMC_CLKCR_PWRSAV_Msk           (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)     /*!< 0x00001000 */

+#define SDMMC_CLKCR_PWRSAV               SDMMC_CLKCR_PWRSAV_Msk                /*!<Power saving configuration bit  */

+

+#define SDMMC_CLKCR_WIDBUS_Pos           (14U)

+#define SDMMC_CLKCR_WIDBUS_Msk           (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)     /*!< 0x0000C000 */

+#define SDMMC_CLKCR_WIDBUS               SDMMC_CLKCR_WIDBUS_Msk                /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */

+#define SDMMC_CLKCR_WIDBUS_0             (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00004000 */

+#define SDMMC_CLKCR_WIDBUS_1             (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00008000 */

+

+#define SDMMC_CLKCR_NEGEDGE_Pos          (16U)

+#define SDMMC_CLKCR_NEGEDGE_Msk          (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)    /*!< 0x00010000 */

+#define SDMMC_CLKCR_NEGEDGE              SDMMC_CLKCR_NEGEDGE_Msk               /*!<SDMMC_CK dephasing selection bit */

+#define SDMMC_CLKCR_HWFC_EN_Pos          (17U)

+#define SDMMC_CLKCR_HWFC_EN_Msk          (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)    /*!< 0x00020000 */

+#define SDMMC_CLKCR_HWFC_EN              SDMMC_CLKCR_HWFC_EN_Msk               /*!<HW Flow Control enable           */

+#define SDMMC_CLKCR_DDR_Pos              (18U)

+#define SDMMC_CLKCR_DDR_Msk              (0x1UL << SDMMC_CLKCR_DDR_Pos)        /*!< 0x00040000 */

+#define SDMMC_CLKCR_DDR                  SDMMC_CLKCR_DDR_Msk                   /*!<Data rate signaling selection    */

+#define SDMMC_CLKCR_BUSSPEED_Pos         (19U)

+#define SDMMC_CLKCR_BUSSPEED_Msk         (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)   /*!< 0x00080000 */

+#define SDMMC_CLKCR_BUSSPEED             SDMMC_CLKCR_BUSSPEED_Msk              /*!<Bus speed mode selection         */

+#define SDMMC_CLKCR_SELCLKRX_Pos         (20U)

+#define SDMMC_CLKCR_SELCLKRX_Msk         (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)   /*!< 0x00300000 */

+#define SDMMC_CLKCR_SELCLKRX             SDMMC_CLKCR_SELCLKRX_Msk              /*!<SELCLKRX[1:0] bits (Receive clock selection) */

+#define SDMMC_CLKCR_SELCLKRX_0           (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00100000 */

+#define SDMMC_CLKCR_SELCLKRX_1           (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00200000 */

+

+/*******************  Bit definition for SDMMC_ARG register  *******************/

+#define SDMMC_ARG_CMDARG_Pos             (0U)

+#define SDMMC_ARG_CMDARG_Msk             (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_ARG_CMDARG                 SDMMC_ARG_CMDARG_Msk                  /*!<Command argument */

+

+/*******************  Bit definition for SDMMC_CMD register  *******************/

+#define SDMMC_CMD_CMDINDEX_Pos           (0U)

+#define SDMMC_CMD_CMDINDEX_Msk           (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)    /*!< 0x0000003F */

+#define SDMMC_CMD_CMDINDEX               SDMMC_CMD_CMDINDEX_Msk                /*!<Command Index                               */

+#define SDMMC_CMD_CMDTRANS_Pos           (6U)

+#define SDMMC_CMD_CMDTRANS_Msk           (0x1UL << SDMMC_CMD_CMDTRANS_Pos)     /*!< 0x00000040 */

+#define SDMMC_CMD_CMDTRANS               SDMMC_CMD_CMDTRANS_Msk                /*!<CPSM Treats command as a Data Transfer      */

+#define SDMMC_CMD_CMDSTOP_Pos            (7U)

+#define SDMMC_CMD_CMDSTOP_Msk            (0x1UL << SDMMC_CMD_CMDSTOP_Pos)      /*!< 0x00000080 */

+#define SDMMC_CMD_CMDSTOP                SDMMC_CMD_CMDSTOP_Msk                 /*!<CPSM Treats command as a Stop               */

+

+#define SDMMC_CMD_WAITRESP_Pos           (8U)

+#define SDMMC_CMD_WAITRESP_Msk           (0x3UL << SDMMC_CMD_WAITRESP_Pos)     /*!< 0x00000300 */

+#define SDMMC_CMD_WAITRESP               SDMMC_CMD_WAITRESP_Msk                /*!<WAITRESP[1:0] bits (Wait for response bits) */

+#define SDMMC_CMD_WAITRESP_0             (0x1UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000100 */

+#define SDMMC_CMD_WAITRESP_1             (0x2UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000200 */

+

+#define SDMMC_CMD_WAITINT_Pos            (10U)

+#define SDMMC_CMD_WAITINT_Msk            (0x1UL << SDMMC_CMD_WAITINT_Pos)      /*!< 0x00000400 */

+#define SDMMC_CMD_WAITINT                SDMMC_CMD_WAITINT_Msk                 /*!<CPSM Waits for Interrupt Request                               */

+#define SDMMC_CMD_WAITPEND_Pos           (11U)

+#define SDMMC_CMD_WAITPEND_Msk           (0x1UL << SDMMC_CMD_WAITPEND_Pos)     /*!< 0x00000800 */

+#define SDMMC_CMD_WAITPEND               SDMMC_CMD_WAITPEND_Msk                /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */

+#define SDMMC_CMD_CPSMEN_Pos             (12U)

+#define SDMMC_CMD_CPSMEN_Msk             (0x1UL << SDMMC_CMD_CPSMEN_Pos)       /*!< 0x00001000 */

+#define SDMMC_CMD_CPSMEN                 SDMMC_CMD_CPSMEN_Msk                  /*!<Command path state machine (CPSM) Enable bit                   */

+#define SDMMC_CMD_DTHOLD_Pos             (13U)

+#define SDMMC_CMD_DTHOLD_Msk             (0x1UL << SDMMC_CMD_DTHOLD_Pos)       /*!< 0x00002000 */

+#define SDMMC_CMD_DTHOLD                 SDMMC_CMD_DTHOLD_Msk                  /*!<Hold new data block transmission and reception in the DPSM     */

+#define SDMMC_CMD_BOOTMODE_Pos           (14U)

+#define SDMMC_CMD_BOOTMODE_Msk           (0x1UL << SDMMC_CMD_BOOTMODE_Pos)     /*!< 0x00004000 */

+#define SDMMC_CMD_BOOTMODE               SDMMC_CMD_BOOTMODE_Msk                /*!<Boot mode                                                      */

+#define SDMMC_CMD_BOOTEN_Pos             (15U)

+#define SDMMC_CMD_BOOTEN_Msk             (0x1UL << SDMMC_CMD_BOOTEN_Pos)       /*!< 0x00008000 */

+#define SDMMC_CMD_BOOTEN                 SDMMC_CMD_BOOTEN_Msk                  /*!<Enable Boot mode procedure                                     */

+#define SDMMC_CMD_CMDSUSPEND_Pos         (16U)

+#define SDMMC_CMD_CMDSUSPEND_Msk         (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)   /*!< 0x00010000 */

+#define SDMMC_CMD_CMDSUSPEND             SDMMC_CMD_CMDSUSPEND_Msk              /*!<CPSM Treats command as a Suspend or Resume command             */

+

+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/

+#define SDMMC_RESPCMD_RESPCMD_Pos        (0U)

+#define SDMMC_RESPCMD_RESPCMD_Msk        (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */

+#define SDMMC_RESPCMD_RESPCMD            SDMMC_RESPCMD_RESPCMD_Msk             /*!<Response command index */

+

+/******************  Bit definition for SDMMC_RESP0 register  ******************/

+#define SDMMC_RESP0_CARDSTATUS0_Pos      (0U)

+#define SDMMC_RESP0_CARDSTATUS0_Msk      (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP0_CARDSTATUS0          SDMMC_RESP0_CARDSTATUS0_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP1 register  ******************/

+#define SDMMC_RESP1_CARDSTATUS1_Pos      (0U)

+#define SDMMC_RESP1_CARDSTATUS1_Msk      (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP1_CARDSTATUS1          SDMMC_RESP1_CARDSTATUS1_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP2 register  ******************/

+#define SDMMC_RESP2_CARDSTATUS2_Pos      (0U)

+#define SDMMC_RESP2_CARDSTATUS2_Msk      (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP2_CARDSTATUS2          SDMMC_RESP2_CARDSTATUS2_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP3 register  ******************/

+#define SDMMC_RESP3_CARDSTATUS3_Pos      (0U)

+#define SDMMC_RESP3_CARDSTATUS3_Msk      (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP3_CARDSTATUS3          SDMMC_RESP3_CARDSTATUS3_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP4 register  ******************/

+#define SDMMC_RESP4_CARDSTATUS4_Pos      (0U)

+#define SDMMC_RESP4_CARDSTATUS4_Msk      (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP4_CARDSTATUS4          SDMMC_RESP4_CARDSTATUS4_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_DTIMER register  *****************/

+#define SDMMC_DTIMER_DATATIME_Pos        (0U)

+#define SDMMC_DTIMER_DATATIME_Msk        (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_DTIMER_DATATIME            SDMMC_DTIMER_DATATIME_Msk             /*!<Data timeout period. */

+

+/******************  Bit definition for SDMMC_DLEN register  *******************/

+#define SDMMC_DLEN_DATALENGTH_Pos        (0U)

+#define SDMMC_DLEN_DATALENGTH_Msk        (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_DLEN_DATALENGTH            SDMMC_DLEN_DATALENGTH_Msk             /*!<Data length value    */

+

+/******************  Bit definition for SDMMC_DCTRL register  ******************/

+#define SDMMC_DCTRL_DTEN_Pos             (0U)

+#define SDMMC_DCTRL_DTEN_Msk             (0x1UL << SDMMC_DCTRL_DTEN_Pos)       /*!< 0x00000001 */

+#define SDMMC_DCTRL_DTEN                 SDMMC_DCTRL_DTEN_Msk                  /*!<Data transfer enabled bit                */

+#define SDMMC_DCTRL_DTDIR_Pos            (1U)

+#define SDMMC_DCTRL_DTDIR_Msk            (0x1UL << SDMMC_DCTRL_DTDIR_Pos)      /*!< 0x00000002 */

+#define SDMMC_DCTRL_DTDIR                SDMMC_DCTRL_DTDIR_Msk                 /*!<Data transfer direction selection        */

+#define SDMMC_DCTRL_DTMODE_Pos           (2U)

+#define SDMMC_DCTRL_DTMODE_Msk           (0x3UL << SDMMC_DCTRL_DTMODE_Pos)     /*!< 0x0000000C */

+#define SDMMC_DCTRL_DTMODE               SDMMC_DCTRL_DTMODE_Msk                /*!<DTMODE[1:0] Data transfer mode selection */

+#define SDMMC_DCTRL_DTMODE_0             (0x1UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000004 */

+#define SDMMC_DCTRL_DTMODE_1             (0x2UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000008 */

+

+#define SDMMC_DCTRL_DBLOCKSIZE_Pos       (4U)

+#define SDMMC_DCTRL_DBLOCKSIZE_Msk       (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */

+#define SDMMC_DCTRL_DBLOCKSIZE           SDMMC_DCTRL_DBLOCKSIZE_Msk            /*!<DBLOCKSIZE[3:0] bits (Data block size) */

+#define SDMMC_DCTRL_DBLOCKSIZE_0         (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000010 */

+#define SDMMC_DCTRL_DBLOCKSIZE_1         (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000020 */

+#define SDMMC_DCTRL_DBLOCKSIZE_2         (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000040 */

+#define SDMMC_DCTRL_DBLOCKSIZE_3         (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000080 */

+

+#define SDMMC_DCTRL_RWSTART_Pos          (8U)

+#define SDMMC_DCTRL_RWSTART_Msk          (0x1UL << SDMMC_DCTRL_RWSTART_Pos)    /*!< 0x00000100 */

+#define SDMMC_DCTRL_RWSTART              SDMMC_DCTRL_RWSTART_Msk               /*!<Read wait start                                 */

+#define SDMMC_DCTRL_RWSTOP_Pos           (9U)

+#define SDMMC_DCTRL_RWSTOP_Msk           (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)     /*!< 0x00000200 */

+#define SDMMC_DCTRL_RWSTOP               SDMMC_DCTRL_RWSTOP_Msk                /*!<Read wait stop                                  */

+#define SDMMC_DCTRL_RWMOD_Pos            (10U)

+#define SDMMC_DCTRL_RWMOD_Msk            (0x1UL << SDMMC_DCTRL_RWMOD_Pos)      /*!< 0x00000400 */

+#define SDMMC_DCTRL_RWMOD                SDMMC_DCTRL_RWMOD_Msk                 /*!<Read wait mode                                  */

+#define SDMMC_DCTRL_SDIOEN_Pos           (11U)

+#define SDMMC_DCTRL_SDIOEN_Msk           (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)     /*!< 0x00000800 */

+#define SDMMC_DCTRL_SDIOEN               SDMMC_DCTRL_SDIOEN_Msk                /*!<SD I/O enable functions                         */

+#define SDMMC_DCTRL_BOOTACKEN_Pos        (12U)

+#define SDMMC_DCTRL_BOOTACKEN_Msk        (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)  /*!< 0x00001000 */

+#define SDMMC_DCTRL_BOOTACKEN            SDMMC_DCTRL_BOOTACKEN_Msk             /*!<Enable the reception of the Boot Acknowledgment */

+#define SDMMC_DCTRL_FIFORST_Pos          (13U)

+#define SDMMC_DCTRL_FIFORST_Msk          (0x1UL << SDMMC_DCTRL_FIFORST_Pos)    /*!< 0x00002000 */

+#define SDMMC_DCTRL_FIFORST              SDMMC_DCTRL_FIFORST_Msk               /*!<FIFO reset                                      */

+

+/******************  Bit definition for SDMMC_DCOUNT register  *****************/

+#define SDMMC_DCOUNT_DATACOUNT_Pos       (0U)

+#define SDMMC_DCOUNT_DATACOUNT_Msk       (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_DCOUNT_DATACOUNT           SDMMC_DCOUNT_DATACOUNT_Msk            /*!<Data count value */

+

+/******************  Bit definition for SDMMC_STA register  ********************/

+#define SDMMC_STA_CCRCFAIL_Pos           (0U)

+#define SDMMC_STA_CCRCFAIL_Msk           (0x1UL << SDMMC_STA_CCRCFAIL_Pos)     /*!< 0x00000001 */

+#define SDMMC_STA_CCRCFAIL               SDMMC_STA_CCRCFAIL_Msk                /*!<Command response received (CRC check failed)  */

+#define SDMMC_STA_DCRCFAIL_Pos           (1U)

+#define SDMMC_STA_DCRCFAIL_Msk           (0x1UL << SDMMC_STA_DCRCFAIL_Pos)     /*!< 0x00000002 */

+#define SDMMC_STA_DCRCFAIL               SDMMC_STA_DCRCFAIL_Msk                /*!<Data block sent/received (CRC check failed)   */

+#define SDMMC_STA_CTIMEOUT_Pos           (2U)

+#define SDMMC_STA_CTIMEOUT_Msk           (0x1UL << SDMMC_STA_CTIMEOUT_Pos)     /*!< 0x00000004 */

+#define SDMMC_STA_CTIMEOUT               SDMMC_STA_CTIMEOUT_Msk                /*!<Command response timeout                      */

+#define SDMMC_STA_DTIMEOUT_Pos           (3U)

+#define SDMMC_STA_DTIMEOUT_Msk           (0x1UL << SDMMC_STA_DTIMEOUT_Pos)     /*!< 0x00000008 */

+#define SDMMC_STA_DTIMEOUT               SDMMC_STA_DTIMEOUT_Msk                /*!<Data timeout                                  */

+#define SDMMC_STA_TXUNDERR_Pos           (4U)

+#define SDMMC_STA_TXUNDERR_Msk           (0x1UL << SDMMC_STA_TXUNDERR_Pos)     /*!< 0x00000010 */

+#define SDMMC_STA_TXUNDERR               SDMMC_STA_TXUNDERR_Msk                /*!<Transmit FIFO underrun error                  */

+#define SDMMC_STA_RXOVERR_Pos            (5U)

+#define SDMMC_STA_RXOVERR_Msk            (0x1UL << SDMMC_STA_RXOVERR_Pos)      /*!< 0x00000020 */

+#define SDMMC_STA_RXOVERR                SDMMC_STA_RXOVERR_Msk                 /*!<Received FIFO overrun error                   */

+#define SDMMC_STA_CMDREND_Pos            (6U)

+#define SDMMC_STA_CMDREND_Msk            (0x1UL << SDMMC_STA_CMDREND_Pos)      /*!< 0x00000040 */

+#define SDMMC_STA_CMDREND                SDMMC_STA_CMDREND_Msk                 /*!<Command response received (CRC check passed)  */

+#define SDMMC_STA_CMDSENT_Pos            (7U)

+#define SDMMC_STA_CMDSENT_Msk            (0x1UL << SDMMC_STA_CMDSENT_Pos)      /*!< 0x00000080 */

+#define SDMMC_STA_CMDSENT                SDMMC_STA_CMDSENT_Msk                 /*!<Command sent (no response required)           */

+#define SDMMC_STA_DATAEND_Pos            (8U)

+#define SDMMC_STA_DATAEND_Msk            (0x1UL << SDMMC_STA_DATAEND_Pos)      /*!< 0x00000100 */

+#define SDMMC_STA_DATAEND                SDMMC_STA_DATAEND_Msk                 /*!<Data end (data counter, SDIDCOUNT, is zero)   */

+#define SDMMC_STA_DHOLD_Pos              (9U)

+#define SDMMC_STA_DHOLD_Msk              (0x1UL << SDMMC_STA_DHOLD_Pos)        /*!< 0x00000200 */

+#define SDMMC_STA_DHOLD                  SDMMC_STA_DHOLD_Msk                   /*!<Data transfer Hold                                                      */

+#define SDMMC_STA_DBCKEND_Pos            (10U)

+#define SDMMC_STA_DBCKEND_Msk            (0x1UL << SDMMC_STA_DBCKEND_Pos)      /*!< 0x00000400 */

+#define SDMMC_STA_DBCKEND                SDMMC_STA_DBCKEND_Msk                 /*!<Data block sent/received (CRC check passed)   */

+#define SDMMC_STA_DABORT_Pos             (11U)

+#define SDMMC_STA_DABORT_Msk             (0x1UL << SDMMC_STA_DABORT_Pos)       /*!< 0x00000800 */

+#define SDMMC_STA_DABORT                 SDMMC_STA_DABORT_Msk                  /*!<Data transfer aborted by CMD12                                          */

+#define SDMMC_STA_DPSMACT_Pos            (12U)

+#define SDMMC_STA_DPSMACT_Msk            (0x1UL << SDMMC_STA_DPSMACT_Pos)      /*!< 0x00001000 */

+#define SDMMC_STA_DPSMACT                SDMMC_STA_DPSMACT_Msk                 /*!<Data path state machine active                                       */

+#define SDMMC_STA_CPSMACT_Pos            (13U)

+#define SDMMC_STA_CPSMACT_Msk            (0x1UL << SDMMC_STA_CPSMACT_Pos)      /*!< 0x00002000 */

+#define SDMMC_STA_CPSMACT                SDMMC_STA_CPSMACT_Msk                 /*!<Command path state machine active                                          */

+#define SDMMC_STA_TXFIFOHE_Pos           (14U)

+#define SDMMC_STA_TXFIFOHE_Msk           (0x1UL << SDMMC_STA_TXFIFOHE_Pos)     /*!< 0x00004000 */

+#define SDMMC_STA_TXFIFOHE               SDMMC_STA_TXFIFOHE_Msk                /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */

+#define SDMMC_STA_RXFIFOHF_Pos           (15U)

+#define SDMMC_STA_RXFIFOHF_Msk           (0x1UL << SDMMC_STA_RXFIFOHF_Pos)     /*!< 0x00008000 */

+#define SDMMC_STA_RXFIFOHF               SDMMC_STA_RXFIFOHF_Msk                /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */

+#define SDMMC_STA_TXFIFOF_Pos            (16U)

+#define SDMMC_STA_TXFIFOF_Msk            (0x1UL << SDMMC_STA_TXFIFOF_Pos)      /*!< 0x00010000 */

+#define SDMMC_STA_TXFIFOF                SDMMC_STA_TXFIFOF_Msk                 /*!<Transmit FIFO full                            */

+#define SDMMC_STA_RXFIFOF_Pos            (17U)

+#define SDMMC_STA_RXFIFOF_Msk            (0x1UL << SDMMC_STA_RXFIFOF_Pos)      /*!< 0x00020000 */

+#define SDMMC_STA_RXFIFOF                SDMMC_STA_RXFIFOF_Msk                 /*!<Receive FIFO full                             */

+#define SDMMC_STA_TXFIFOE_Pos            (18U)

+#define SDMMC_STA_TXFIFOE_Msk            (0x1UL << SDMMC_STA_TXFIFOE_Pos)      /*!< 0x00040000 */

+#define SDMMC_STA_TXFIFOE                SDMMC_STA_TXFIFOE_Msk                 /*!<Transmit FIFO empty                           */

+#define SDMMC_STA_RXFIFOE_Pos            (19U)

+#define SDMMC_STA_RXFIFOE_Msk            (0x1UL << SDMMC_STA_RXFIFOE_Pos)      /*!< 0x00080000 */

+#define SDMMC_STA_RXFIFOE                SDMMC_STA_RXFIFOE_Msk                 /*!<Receive FIFO empty                            */

+#define SDMMC_STA_BUSYD0_Pos             (20U)

+#define SDMMC_STA_BUSYD0_Msk             (0x1UL << SDMMC_STA_BUSYD0_Pos)       /*!< 0x00100000 */

+#define SDMMC_STA_BUSYD0                 SDMMC_STA_BUSYD0_Msk                  /*!<Inverted value of SDMMC_D0 line (Busy)                                  */

+#define SDMMC_STA_BUSYD0END_Pos          (21U)

+#define SDMMC_STA_BUSYD0END_Msk          (0x1UL << SDMMC_STA_BUSYD0END_Pos)    /*!< 0x00200000 */

+#define SDMMC_STA_BUSYD0END              SDMMC_STA_BUSYD0END_Msk               /*!<End of SDMMC_D0 Busy following a CMD response detected                  */

+#define SDMMC_STA_SDIOIT_Pos             (22U)

+#define SDMMC_STA_SDIOIT_Msk             (0x1UL << SDMMC_STA_SDIOIT_Pos)       /*!< 0x00400000 */

+#define SDMMC_STA_SDIOIT                 SDMMC_STA_SDIOIT_Msk                  /*!<SDIO interrupt received                                                 */

+#define SDMMC_STA_ACKFAIL_Pos            (23U)

+#define SDMMC_STA_ACKFAIL_Msk            (0x1UL << SDMMC_STA_ACKFAIL_Pos)      /*!< 0x00800000 */

+#define SDMMC_STA_ACKFAIL                SDMMC_STA_ACKFAIL_Msk                 /*!<Boot Acknowledgment received (BootAck check fail)                       */

+#define SDMMC_STA_ACKTIMEOUT_Pos         (24U)

+#define SDMMC_STA_ACKTIMEOUT_Msk         (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)   /*!< 0x01000000 */

+#define SDMMC_STA_ACKTIMEOUT             SDMMC_STA_ACKTIMEOUT_Msk              /*!<Boot Acknowledgment timeout                                             */

+#define SDMMC_STA_VSWEND_Pos             (25U)

+#define SDMMC_STA_VSWEND_Msk             (0x1UL << SDMMC_STA_VSWEND_Pos)       /*!< 0x02000000 */

+#define SDMMC_STA_VSWEND                 SDMMC_STA_VSWEND_Msk                  /*!<Voltage switch critical timing section completion                       */

+#define SDMMC_STA_CKSTOP_Pos             (26U)

+#define SDMMC_STA_CKSTOP_Msk             (0x1UL << SDMMC_STA_CKSTOP_Pos)       /*!< 0x04000000 */

+#define SDMMC_STA_CKSTOP                 SDMMC_STA_CKSTOP_Msk                  /*!<SDMMC_CK stopped in Voltage switch procedure                            */

+#define SDMMC_STA_IDMATE_Pos             (27U)

+#define SDMMC_STA_IDMATE_Msk             (0x1UL << SDMMC_STA_IDMATE_Pos)       /*!< 0x08000000 */

+#define SDMMC_STA_IDMATE                 SDMMC_STA_IDMATE_Msk                  /*!<IDMA transfer error                                                     */

+#define SDMMC_STA_IDMABTC_Pos            (28U)

+#define SDMMC_STA_IDMABTC_Msk            (0x1UL << SDMMC_STA_IDMABTC_Pos)      /*!< 0x10000000 */

+#define SDMMC_STA_IDMABTC                SDMMC_STA_IDMABTC_Msk                 /*!<IDMA buffer transfer complete                                           */

+

+/*******************  Bit definition for SDMMC_ICR register  *******************/

+#define SDMMC_ICR_CCRCFAILC_Pos          (0U)

+#define SDMMC_ICR_CCRCFAILC_Msk          (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)    /*!< 0x00000001 */

+#define SDMMC_ICR_CCRCFAILC              SDMMC_ICR_CCRCFAILC_Msk               /*!<CCRCFAIL flag clear bit */

+#define SDMMC_ICR_DCRCFAILC_Pos          (1U)

+#define SDMMC_ICR_DCRCFAILC_Msk          (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)    /*!< 0x00000002 */

+#define SDMMC_ICR_DCRCFAILC              SDMMC_ICR_DCRCFAILC_Msk               /*!<DCRCFAIL flag clear bit */

+#define SDMMC_ICR_CTIMEOUTC_Pos          (2U)

+#define SDMMC_ICR_CTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)    /*!< 0x00000004 */

+#define SDMMC_ICR_CTIMEOUTC              SDMMC_ICR_CTIMEOUTC_Msk               /*!<CTIMEOUT flag clear bit */

+#define SDMMC_ICR_DTIMEOUTC_Pos          (3U)

+#define SDMMC_ICR_DTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)    /*!< 0x00000008 */

+#define SDMMC_ICR_DTIMEOUTC              SDMMC_ICR_DTIMEOUTC_Msk               /*!<DTIMEOUT flag clear bit */

+#define SDMMC_ICR_TXUNDERRC_Pos          (4U)

+#define SDMMC_ICR_TXUNDERRC_Msk          (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)    /*!< 0x00000010 */

+#define SDMMC_ICR_TXUNDERRC              SDMMC_ICR_TXUNDERRC_Msk               /*!<TXUNDERR flag clear bit */

+#define SDMMC_ICR_RXOVERRC_Pos           (5U)

+#define SDMMC_ICR_RXOVERRC_Msk           (0x1UL << SDMMC_ICR_RXOVERRC_Pos)     /*!< 0x00000020 */

+#define SDMMC_ICR_RXOVERRC               SDMMC_ICR_RXOVERRC_Msk                /*!<RXOVERR flag clear bit  */

+#define SDMMC_ICR_CMDRENDC_Pos           (6U)

+#define SDMMC_ICR_CMDRENDC_Msk           (0x1UL << SDMMC_ICR_CMDRENDC_Pos)     /*!< 0x00000040 */

+#define SDMMC_ICR_CMDRENDC               SDMMC_ICR_CMDRENDC_Msk                /*!<CMDREND flag clear bit  */

+#define SDMMC_ICR_CMDSENTC_Pos           (7U)

+#define SDMMC_ICR_CMDSENTC_Msk           (0x1UL << SDMMC_ICR_CMDSENTC_Pos)     /*!< 0x00000080 */

+#define SDMMC_ICR_CMDSENTC               SDMMC_ICR_CMDSENTC_Msk                /*!<CMDSENT flag clear bit  */

+#define SDMMC_ICR_DATAENDC_Pos           (8U)

+#define SDMMC_ICR_DATAENDC_Msk           (0x1UL << SDMMC_ICR_DATAENDC_Pos)     /*!< 0x00000100 */

+#define SDMMC_ICR_DATAENDC               SDMMC_ICR_DATAENDC_Msk                /*!<DATAEND flag clear bit  */

+#define SDMMC_ICR_DHOLDC_Pos             (9U)

+#define SDMMC_ICR_DHOLDC_Msk             (0x1UL << SDMMC_ICR_DHOLDC_Pos)       /*!< 0x00000200 */

+#define SDMMC_ICR_DHOLDC                 SDMMC_ICR_DHOLDC_Msk                  /*!<DHOLD flag clear bit       */

+#define SDMMC_ICR_DBCKENDC_Pos           (10U)

+#define SDMMC_ICR_DBCKENDC_Msk           (0x1UL << SDMMC_ICR_DBCKENDC_Pos)     /*!< 0x00000400 */

+#define SDMMC_ICR_DBCKENDC               SDMMC_ICR_DBCKENDC_Msk                /*!<DBCKEND flag clear bit  */

+#define SDMMC_ICR_DABORTC_Pos            (11U)

+#define SDMMC_ICR_DABORTC_Msk            (0x1UL << SDMMC_ICR_DABORTC_Pos)      /*!< 0x00000800 */

+#define SDMMC_ICR_DABORTC                SDMMC_ICR_DABORTC_Msk                 /*!<DABORTC flag clear bit     */

+#define SDMMC_ICR_BUSYD0ENDC_Pos         (21U)

+#define SDMMC_ICR_BUSYD0ENDC_Msk         (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)   /*!< 0x00200000 */

+#define SDMMC_ICR_BUSYD0ENDC             SDMMC_ICR_BUSYD0ENDC_Msk              /*!<BUSYD0ENDC flag clear bit  */

+#define SDMMC_ICR_SDIOITC_Pos            (22U)

+#define SDMMC_ICR_SDIOITC_Msk            (0x1UL << SDMMC_ICR_SDIOITC_Pos)      /*!< 0x00400000 */

+#define SDMMC_ICR_SDIOITC                SDMMC_ICR_SDIOITC_Msk                 /*!<SDIOIT flag clear bit      */

+#define SDMMC_ICR_ACKFAILC_Pos           (23U)

+#define SDMMC_ICR_ACKFAILC_Msk           (0x1UL << SDMMC_ICR_ACKFAILC_Pos)     /*!< 0x00800000 */

+#define SDMMC_ICR_ACKFAILC               SDMMC_ICR_ACKFAILC_Msk                /*!<ACKFAILC flag clear bit    */

+#define SDMMC_ICR_ACKTIMEOUTC_Pos        (24U)

+#define SDMMC_ICR_ACKTIMEOUTC_Msk        (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)  /*!< 0x01000000 */

+#define SDMMC_ICR_ACKTIMEOUTC            SDMMC_ICR_ACKTIMEOUTC_Msk             /*!<ACKTIMEOUTC flag clear bit */

+#define SDMMC_ICR_VSWENDC_Pos            (25U)

+#define SDMMC_ICR_VSWENDC_Msk            (0x1UL << SDMMC_ICR_VSWENDC_Pos)      /*!< 0x02000000 */

+#define SDMMC_ICR_VSWENDC                SDMMC_ICR_VSWENDC_Msk                 /*!<VSWENDC flag clear bit     */

+#define SDMMC_ICR_CKSTOPC_Pos            (26U)

+#define SDMMC_ICR_CKSTOPC_Msk            (0x1UL << SDMMC_ICR_CKSTOPC_Pos)      /*!< 0x04000000 */

+#define SDMMC_ICR_CKSTOPC                SDMMC_ICR_CKSTOPC_Msk                 /*!<CKSTOPC flag clear bit     */

+#define SDMMC_ICR_IDMATEC_Pos            (27U)

+#define SDMMC_ICR_IDMATEC_Msk            (0x1UL << SDMMC_ICR_IDMATEC_Pos)      /*!< 0x08000000 */

+#define SDMMC_ICR_IDMATEC                SDMMC_ICR_IDMATEC_Msk                 /*!<IDMATEC flag clear bit     */

+#define SDMMC_ICR_IDMABTCC_Pos           (28U)

+#define SDMMC_ICR_IDMABTCC_Msk           (0x1UL << SDMMC_ICR_IDMABTCC_Pos)     /*!< 0x10000000 */

+#define SDMMC_ICR_IDMABTCC               SDMMC_ICR_IDMABTCC_Msk                /*!<IDMABTCC flag clear bit    */

+

+/******************  Bit definition for SDMMC_MASK register  *******************/

+#define SDMMC_MASK_CCRCFAILIE_Pos        (0U)

+#define SDMMC_MASK_CCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)  /*!< 0x00000001 */

+#define SDMMC_MASK_CCRCFAILIE            SDMMC_MASK_CCRCFAILIE_Msk             /*!<Command CRC Fail Interrupt Enable          */

+#define SDMMC_MASK_DCRCFAILIE_Pos        (1U)

+#define SDMMC_MASK_DCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)  /*!< 0x00000002 */

+#define SDMMC_MASK_DCRCFAILIE            SDMMC_MASK_DCRCFAILIE_Msk             /*!<Data CRC Fail Interrupt Enable             */

+#define SDMMC_MASK_CTIMEOUTIE_Pos        (2U)

+#define SDMMC_MASK_CTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)  /*!< 0x00000004 */

+#define SDMMC_MASK_CTIMEOUTIE            SDMMC_MASK_CTIMEOUTIE_Msk             /*!<Command TimeOut Interrupt Enable           */

+#define SDMMC_MASK_DTIMEOUTIE_Pos        (3U)

+#define SDMMC_MASK_DTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)  /*!< 0x00000008 */

+#define SDMMC_MASK_DTIMEOUTIE            SDMMC_MASK_DTIMEOUTIE_Msk             /*!<Data TimeOut Interrupt Enable              */

+#define SDMMC_MASK_TXUNDERRIE_Pos        (4U)

+#define SDMMC_MASK_TXUNDERRIE_Msk        (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)  /*!< 0x00000010 */

+#define SDMMC_MASK_TXUNDERRIE            SDMMC_MASK_TXUNDERRIE_Msk             /*!<Tx FIFO UnderRun Error Interrupt Enable    */

+#define SDMMC_MASK_RXOVERRIE_Pos         (5U)

+#define SDMMC_MASK_RXOVERRIE_Msk         (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)   /*!< 0x00000020 */

+#define SDMMC_MASK_RXOVERRIE             SDMMC_MASK_RXOVERRIE_Msk              /*!<Rx FIFO OverRun Error Interrupt Enable     */

+#define SDMMC_MASK_CMDRENDIE_Pos         (6U)

+#define SDMMC_MASK_CMDRENDIE_Msk         (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)   /*!< 0x00000040 */

+#define SDMMC_MASK_CMDRENDIE             SDMMC_MASK_CMDRENDIE_Msk              /*!<Command Response Received Interrupt Enable */

+#define SDMMC_MASK_CMDSENTIE_Pos         (7U)

+#define SDMMC_MASK_CMDSENTIE_Msk         (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)   /*!< 0x00000080 */

+#define SDMMC_MASK_CMDSENTIE             SDMMC_MASK_CMDSENTIE_Msk              /*!<Command Sent Interrupt Enable              */

+#define SDMMC_MASK_DATAENDIE_Pos         (8U)

+#define SDMMC_MASK_DATAENDIE_Msk         (0x1UL << SDMMC_MASK_DATAENDIE_Pos)   /*!< 0x00000100 */

+#define SDMMC_MASK_DATAENDIE             SDMMC_MASK_DATAENDIE_Msk              /*!<Data End Interrupt Enable                  */

+#define SDMMC_MASK_DHOLDIE_Pos           (9U)

+#define SDMMC_MASK_DHOLDIE_Msk           (0x1UL << SDMMC_MASK_DHOLDIE_Pos)     /*!< 0x00000200 */

+#define SDMMC_MASK_DHOLDIE               SDMMC_MASK_DHOLDIE_Msk                /*!<Data Hold Interrupt Enable                 */

+#define SDMMC_MASK_DBCKENDIE_Pos         (10U)

+#define SDMMC_MASK_DBCKENDIE_Msk         (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)   /*!< 0x00000400 */

+#define SDMMC_MASK_DBCKENDIE             SDMMC_MASK_DBCKENDIE_Msk              /*!<Data Block End Interrupt Enable            */

+#define SDMMC_MASK_DABORTIE_Pos          (11U)

+#define SDMMC_MASK_DABORTIE_Msk          (0x1UL << SDMMC_MASK_DABORTIE_Pos)    /*!< 0x00000800 */

+#define SDMMC_MASK_DABORTIE              SDMMC_MASK_DABORTIE_Msk               /*!<Data transfer aborted interrupt enable     */

+

+#define SDMMC_MASK_TXFIFOHEIE_Pos        (14U)

+#define SDMMC_MASK_TXFIFOHEIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)  /*!< 0x00004000 */

+#define SDMMC_MASK_TXFIFOHEIE            SDMMC_MASK_TXFIFOHEIE_Msk             /*!<Tx FIFO Half Empty interrupt Enable        */

+#define SDMMC_MASK_RXFIFOHFIE_Pos        (15U)

+#define SDMMC_MASK_RXFIFOHFIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)  /*!< 0x00008000 */

+#define SDMMC_MASK_RXFIFOHFIE            SDMMC_MASK_RXFIFOHFIE_Msk             /*!<Rx FIFO Half Full interrupt Enable         */

+

+#define SDMMC_MASK_RXFIFOFIE_Pos         (17U)

+#define SDMMC_MASK_RXFIFOFIE_Msk         (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)   /*!< 0x00020000 */

+#define SDMMC_MASK_RXFIFOFIE             SDMMC_MASK_RXFIFOFIE_Msk              /*!<Rx FIFO Full interrupt Enable              */

+#define SDMMC_MASK_TXFIFOEIE_Pos         (18U)

+#define SDMMC_MASK_TXFIFOEIE_Msk         (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)   /*!< 0x00040000 */

+#define SDMMC_MASK_TXFIFOEIE             SDMMC_MASK_TXFIFOEIE_Msk              /*!<Tx FIFO Empty interrupt Enable             */

+

+#define SDMMC_MASK_BUSYD0ENDIE_Pos       (21U)

+#define SDMMC_MASK_BUSYD0ENDIE_Msk       (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */

+#define SDMMC_MASK_BUSYD0ENDIE           SDMMC_MASK_BUSYD0ENDIE_Msk            /*!<BUSYD0ENDIE interrupt Enable */

+#define SDMMC_MASK_SDIOITIE_Pos           (22U)

+#define SDMMC_MASK_SDIOITIE_Msk           (0x1UL << SDMMC_MASK_SDIOITIE_Pos)     /*!< 0x00400000 */

+#define SDMMC_MASK_SDIOITIE               SDMMC_MASK_SDIOITIE_Msk                /*!<SDMMC Mode Interrupt Received interrupt Enable */

+#define SDMMC_MASK_ACKFAILIE_Pos         (23U)

+#define SDMMC_MASK_ACKFAILIE_Msk         (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)   /*!< 0x00800000 */

+#define SDMMC_MASK_ACKFAILIE             SDMMC_MASK_ACKFAILIE_Msk              /*!<Acknowledgment Fail Interrupt Enable */

+#define SDMMC_MASK_ACKTIMEOUTIE_Pos      (24U)

+#define SDMMC_MASK_ACKTIMEOUTIE_Msk      (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */

+#define SDMMC_MASK_ACKTIMEOUTIE          SDMMC_MASK_ACKTIMEOUTIE_Msk           /*!<Acknowledgment timeout Interrupt Enable */

+#define SDMMC_MASK_VSWENDIE_Pos          (25U)

+#define SDMMC_MASK_VSWENDIE_Msk          (0x1UL << SDMMC_MASK_VSWENDIE_Pos)    /*!< 0x02000000 */

+#define SDMMC_MASK_VSWENDIE              SDMMC_MASK_VSWENDIE_Msk               /*!<Voltage switch critical timing section completion Interrupt Enable */

+#define SDMMC_MASK_CKSTOPIE_Pos          (26U)

+#define SDMMC_MASK_CKSTOPIE_Msk          (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)    /*!< 0x04000000 */

+#define SDMMC_MASK_CKSTOPIE              SDMMC_MASK_CKSTOPIE_Msk               /*!<Voltage Switch clock stopped Interrupt Enable */

+#define SDMMC_MASK_IDMABTCIE_Pos         (28U)

+#define SDMMC_MASK_IDMABTCIE_Msk         (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)   /*!< 0x10000000 */

+#define SDMMC_MASK_IDMABTCIE             SDMMC_MASK_IDMABTCIE_Msk              /*!<IDMA buffer transfer complete Interrupt Enable */

+

+/*****************  Bit definition for SDMMC_ACKTIME register  *****************/

+#define SDMMC_ACKTIME_ACKTIME_Pos        (0U)

+#define SDMMC_ACKTIME_ACKTIME_Msk        (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_ACKTIME_ACKTIME            SDMMC_ACKTIME_ACKTIME_Msk             /*!<Boot acknowledgment timeout period */

+

+/******************  Bit definition for SDMMC_FIFO register  *******************/

+#define SDMMC_FIFO_FIFODATA_Pos          (0U)

+#define SDMMC_FIFO_FIFODATA_Msk          (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_FIFO_FIFODATA              SDMMC_FIFO_FIFODATA_Msk               /*!<Receive and transmit FIFO data */

+

+/******************  Bit definition for SDMMC_IDMACTRL register ****************/

+#define SDMMC_IDMA_IDMAEN_Pos            (0U)

+#define SDMMC_IDMA_IDMAEN_Msk            (0x1UL << SDMMC_IDMA_IDMAEN_Pos)      /*!< 0x00000001 */

+#define SDMMC_IDMA_IDMAEN                SDMMC_IDMA_IDMAEN_Msk                 /*!< Enable the internal DMA of the SDMMC peripheral */

+#define SDMMC_IDMA_IDMABMODE_Pos         (1U)

+#define SDMMC_IDMA_IDMABMODE_Msk         (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)   /*!< 0x00000002 */

+#define SDMMC_IDMA_IDMABMODE             SDMMC_IDMA_IDMABMODE_Msk              /*!< Enable double buffer mode for IDMA */

+#define SDMMC_IDMA_IDMABACT_Pos          (2U)

+#define SDMMC_IDMA_IDMABACT_Msk          (0x1UL << SDMMC_IDMA_IDMABACT_Pos)    /*!< 0x00000004 */

+#define SDMMC_IDMA_IDMABACT              SDMMC_IDMA_IDMABACT_Msk               /*!< Uses buffer 1 when double buffer mode is selected */

+

+/*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/

+#define SDMMC_IDMABSIZE_IDMABNDT_Pos     (5U)

+#define SDMMC_IDMABSIZE_IDMABNDT_Msk     (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */

+#define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */

+

+/*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/

+#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */

+

+/*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/

+#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                        Delay Block Interface (DLYB)                        */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for DLYB_CR register  ********************/

+#define DLYB_CR_DEN_Pos         (0U)

+#define DLYB_CR_DEN_Msk         (0x1UL << DLYB_CR_DEN_Pos)                     /*!< 0x00000001 */

+#define DLYB_CR_DEN             DLYB_CR_DEN_Msk                                /*!<Delay Block enable */

+#define DLYB_CR_SEN_Pos         (1U)

+#define DLYB_CR_SEN_Msk         (0x1UL << DLYB_CR_SEN_Pos)                     /*!< 0x00000002 */

+#define DLYB_CR_SEN             DLYB_CR_SEN_Msk                                /*!<Sampler length enable */

+

+

+/*******************  Bit definition for DLYB_CFGR register  ********************/

+#define DLYB_CFGR_SEL_Pos       (0U)

+#define DLYB_CFGR_SEL_Msk       (0xFUL << DLYB_CFGR_SEL_Pos)                   /*!< 0x0000000F */

+#define DLYB_CFGR_SEL           DLYB_CFGR_SEL_Msk                              /*!<Select the phase for the Output clock[3:0] */

+#define DLYB_CFGR_SEL_0         (0x1UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000001 */

+#define DLYB_CFGR_SEL_1         (0x2UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000002 */

+#define DLYB_CFGR_SEL_2         (0x3UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000003 */

+#define DLYB_CFGR_SEL_3         (0x8UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000008 */

+

+#define DLYB_CFGR_UNIT_Pos      (8U)

+#define DLYB_CFGR_UNIT_Msk      (0x7FUL << DLYB_CFGR_UNIT_Pos)                 /*!< 0x00007F00 */

+#define DLYB_CFGR_UNIT          DLYB_CFGR_UNIT_Msk                             /*!<Delay Defines the delay of a Unit delay cell[6:0] */

+#define DLYB_CFGR_UNIT_0        (0x01UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000100 */

+#define DLYB_CFGR_UNIT_1        (0x02UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000200 */

+#define DLYB_CFGR_UNIT_2        (0x04UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000400 */

+#define DLYB_CFGR_UNIT_3        (0x08UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000800 */

+#define DLYB_CFGR_UNIT_4        (0x10UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00001000 */

+#define DLYB_CFGR_UNIT_5        (0x20UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00002000 */

+#define DLYB_CFGR_UNIT_6        (0x40UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00004000 */

+

+#define DLYB_CFGR_LNG_Pos       (16U)

+#define DLYB_CFGR_LNG_Msk       (0xFFFUL << DLYB_CFGR_LNG_Pos)                 /*!< 0x0FFF0000 */

+#define DLYB_CFGR_LNG           DLYB_CFGR_LNG_Msk                              /*!<Delay line length value[11:0] */

+#define DLYB_CFGR_LNG_0         (0x001UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00010000 */

+#define DLYB_CFGR_LNG_1         (0x002UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00020000 */

+#define DLYB_CFGR_LNG_2         (0x004UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00040000 */

+#define DLYB_CFGR_LNG_3         (0x008UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00080000 */

+#define DLYB_CFGR_LNG_4         (0x010UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00100000 */

+#define DLYB_CFGR_LNG_5         (0x020UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00200000 */

+#define DLYB_CFGR_LNG_6         (0x040UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00400000 */

+#define DLYB_CFGR_LNG_7         (0x080UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00800000 */

+#define DLYB_CFGR_LNG_8         (0x100UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x01000000 */

+#define DLYB_CFGR_LNG_9         (0x200UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x02000000 */

+#define DLYB_CFGR_LNG_10        (0x400UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x04000000 */

+#define DLYB_CFGR_LNG_11        (0x800UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x08000000 */

+

+#define DLYB_CFGR_LNGF_Pos      (31U)

+#define DLYB_CFGR_LNGF_Msk      (0x1UL << DLYB_CFGR_LNGF_Pos)                  /*!< 0x80000000 */

+#define DLYB_CFGR_LNGF          DLYB_CFGR_LNGF_Msk                             /*!<Length valid flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                   Serial Peripheral Interface (SPI/I2S)                    */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for SPI_CR1 register  ********************/

+#define SPI_CR1_SPE_Pos             (0U)

+#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000001 */

+#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<Serial Peripheral Enable                         */

+#define SPI_CR1_MASRX_Pos           (8U)

+#define SPI_CR1_MASRX_Msk           (0x1UL << SPI_CR1_MASRX_Pos)               /*!< 0x00000100 */

+#define SPI_CR1_MASRX               SPI_CR1_MASRX_Msk                          /*!<Master automatic SUSP in Receive mode            */

+#define SPI_CR1_CSTART_Pos          (9U)

+#define SPI_CR1_CSTART_Msk          (0x1UL << SPI_CR1_CSTART_Pos)              /*!< 0x00000200 */

+#define SPI_CR1_CSTART              SPI_CR1_CSTART_Msk                         /*!<Master transfer start                            */

+#define SPI_CR1_CSUSP_Pos           (10U)

+#define SPI_CR1_CSUSP_Msk           (0x1UL << SPI_CR1_CSUSP_Pos)               /*!< 0x00000400 */

+#define SPI_CR1_CSUSP               SPI_CR1_CSUSP_Msk                          /*!<Master SUSPend request                           */

+#define SPI_CR1_HDDIR_Pos           (11U)

+#define SPI_CR1_HDDIR_Msk           (0x1UL << SPI_CR1_HDDIR_Pos)               /*!< 0x00000800 */

+#define SPI_CR1_HDDIR               SPI_CR1_HDDIR_Msk                          /*!<Rx/Tx direction at Half-duplex mode              */

+#define SPI_CR1_SSI_Pos             (12U)

+#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00001000 */

+#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal SS signal input level                   */

+#define SPI_CR1_CRC33_17_Pos        (13U)

+#define SPI_CR1_CRC33_17_Msk        (0x1UL << SPI_CR1_CRC33_17_Pos)            /*!< 0x00002000 */

+#define SPI_CR1_CRC33_17             SPI_CR1_CRC33_17_Msk                      /*!<32-bit CRC polynomial configuration              */

+#define SPI_CR1_RCRCINI_Pos         (14U)

+#define SPI_CR1_RCRCINI_Msk         (0x1UL << SPI_CR1_RCRCINI_Pos)             /*!< 0x00004000 */

+#define SPI_CR1_RCRCINI             SPI_CR1_RCRCINI_Msk                        /*!<CRC init pattern control for receiver            */

+#define SPI_CR1_TCRCINI_Pos         (15U)

+#define SPI_CR1_TCRCINI_Msk         (0x1UL << SPI_CR1_TCRCINI_Pos)             /*!< 0x00008000 */

+#define SPI_CR1_TCRCINI             SPI_CR1_TCRCINI_Msk                        /*!<CRC init pattern control for transmitter         */

+#define SPI_CR1_IOLOCK_Pos          (16U)

+#define SPI_CR1_IOLOCK_Msk          (0x1UL << SPI_CR1_IOLOCK_Pos)              /*!< 0x00010000 */

+#define SPI_CR1_IOLOCK              SPI_CR1_IOLOCK_Msk                         /*!<Locking the AF configuration of associated IOs   */

+

+/*******************  Bit definition for SPI_CR2 register  ********************/

+#define SPI_CR2_TSER_Pos            (16U)

+#define SPI_CR2_TSER_Msk            (0xFFFFUL << SPI_CR2_TSER_Pos)             /*!< 0xFFFF0000 */

+#define SPI_CR2_TSER                SPI_CR2_TSER_Msk                           /*!<Number of data transfer extension                */

+#define SPI_CR2_TSIZE_Pos           (0U)

+#define SPI_CR2_TSIZE_Msk           (0xFFFFUL << SPI_CR2_TSIZE_Pos)            /*!< 0x0000FFFF */

+#define SPI_CR2_TSIZE               SPI_CR2_TSIZE_Msk                          /*!<Number of data at current transfer               */

+

+/*******************  Bit definition for SPI_CFG1 register  ********************/

+#define SPI_CFG1_DSIZE_Pos          (0U)

+#define SPI_CFG1_DSIZE_Msk          (0x1FUL << SPI_CFG1_DSIZE_Pos)             /*!< 0x0000001F */

+#define SPI_CFG1_DSIZE              SPI_CFG1_DSIZE_Msk                         /*!<DSIZE[4:0]: Bits number in single SPI data frame */

+#define SPI_CFG1_DSIZE_0            (0x01UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000001 */

+#define SPI_CFG1_DSIZE_1            (0x02UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000002 */

+#define SPI_CFG1_DSIZE_2            (0x04UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000004 */

+#define SPI_CFG1_DSIZE_3            (0x08UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000008 */

+#define SPI_CFG1_DSIZE_4            (0x10UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000010 */

+

+#define SPI_CFG1_FTHLV_Pos          (5U)

+#define SPI_CFG1_FTHLV_Msk          (0xFUL << SPI_CFG1_FTHLV_Pos)              /*!< 0x000001E0 */

+#define SPI_CFG1_FTHLV              SPI_CFG1_FTHLV_Msk                         /*!<FTHVL [3:0]: FIFO threshold level*/

+#define SPI_CFG1_FTHLV_0            (0x1UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000020 */

+#define SPI_CFG1_FTHLV_1            (0x2UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000040 */

+#define SPI_CFG1_FTHLV_2            (0x4UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000080 */

+#define SPI_CFG1_FTHLV_3            (0x8UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000100 */

+

+#define SPI_CFG1_UDRCFG_Pos         (9U)

+#define SPI_CFG1_UDRCFG_Msk         (0x3UL << SPI_CFG1_UDRCFG_Pos)             /*!< 0x00000600 */

+#define SPI_CFG1_UDRCFG             SPI_CFG1_UDRCFG_Msk                        /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */

+#define SPI_CFG1_UDRCFG_0           (0x1UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000200 */

+#define SPI_CFG1_UDRCFG_1           (0x2UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000400 */

+

+

+#define SPI_CFG1_UDRDET_Pos         (11U)

+#define SPI_CFG1_UDRDET_Msk         (0x3UL << SPI_CFG1_UDRDET_Pos)             /*!< 0x00001800 */

+#define SPI_CFG1_UDRDET             SPI_CFG1_UDRDET_Msk                        /*!<UDRDET[1:0]: Detection of underrun condition     */

+#define SPI_CFG1_UDRDET_0           (0x1UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00000800 */

+#define SPI_CFG1_UDRDET_1           (0x2UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00001000 */

+

+#define SPI_CFG1_RXDMAEN_Pos        (14U)

+#define SPI_CFG1_RXDMAEN_Msk        (0x1UL << SPI_CFG1_RXDMAEN_Pos)            /*!< 0x00004000 */

+#define SPI_CFG1_RXDMAEN            SPI_CFG1_RXDMAEN_Msk                       /*!<Rx DMA stream enable                */

+#define SPI_CFG1_TXDMAEN_Pos        (15U)

+#define SPI_CFG1_TXDMAEN_Msk        (0x1UL << SPI_CFG1_TXDMAEN_Pos)            /*!< 0x00008000 */

+#define SPI_CFG1_TXDMAEN            SPI_CFG1_TXDMAEN_Msk                       /*!<Tx DMA stream enable                */

+

+#define SPI_CFG1_CRCSIZE_Pos        (16U)

+#define SPI_CFG1_CRCSIZE_Msk        (0x1FUL << SPI_CFG1_CRCSIZE_Pos)           /*!< 0x001F0000 */

+#define SPI_CFG1_CRCSIZE            SPI_CFG1_CRCSIZE_Msk                       /*!<CRCSIZE [4:0]: Length of CRC frame*/

+#define SPI_CFG1_CRCSIZE_0          (0x01UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00010000 */

+#define SPI_CFG1_CRCSIZE_1          (0x02UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00020000 */

+#define SPI_CFG1_CRCSIZE_2          (0x04UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00040000 */

+#define SPI_CFG1_CRCSIZE_3          (0x08UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00080000 */

+#define SPI_CFG1_CRCSIZE_4          (0x10UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00100000 */

+

+#define SPI_CFG1_CRCEN_Pos          (22U)

+#define SPI_CFG1_CRCEN_Msk          (0x1UL << SPI_CFG1_CRCEN_Pos)              /*!< 0x00400000 */

+#define SPI_CFG1_CRCEN              SPI_CFG1_CRCEN_Msk                         /*!<Hardware CRC computation enable */

+

+#define SPI_CFG1_MBR_Pos            (28U)

+#define SPI_CFG1_MBR_Msk            (0x7UL << SPI_CFG1_MBR_Pos)                /*!< 0x70000000 */

+#define SPI_CFG1_MBR                SPI_CFG1_MBR_Msk                           /*!<Master baud rate                */

+#define SPI_CFG1_MBR_0              (0x1UL << SPI_CFG1_MBR_Pos)                 /*!< 0x10000000 */

+#define SPI_CFG1_MBR_1              (0x2UL << SPI_CFG1_MBR_Pos)                 /*!< 0x20000000 */

+#define SPI_CFG1_MBR_2              (0x4UL << SPI_CFG1_MBR_Pos)                 /*!< 0x40000000 */

+

+/*******************  Bit definition for SPI_CFG2 register  ********************/

+#define SPI_CFG2_MSSI_Pos           (0U)

+#define SPI_CFG2_MSSI_Msk           (0xFUL << SPI_CFG2_MSSI_Pos)               /*!< 0x0000000F */

+#define SPI_CFG2_MSSI               SPI_CFG2_MSSI_Msk                          /*!<Master SS Idleness */

+#define SPI_CFG2_MSSI_0             (0x1UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000001 */

+#define SPI_CFG2_MSSI_1             (0x2UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000002 */

+#define SPI_CFG2_MSSI_2             (0x4UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000004 */

+#define SPI_CFG2_MSSI_3             (0x8UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000008 */

+

+#define SPI_CFG2_MIDI_Pos           (4U)

+#define SPI_CFG2_MIDI_Msk           (0xFUL << SPI_CFG2_MIDI_Pos)               /*!< 0x000000F0 */

+#define SPI_CFG2_MIDI               SPI_CFG2_MIDI_Msk                          /*!<Master Inter-Data Idleness */

+#define SPI_CFG2_MIDI_0             (0x1UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000010 */

+#define SPI_CFG2_MIDI_1             (0x2UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000020 */

+#define SPI_CFG2_MIDI_2             (0x4UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000040 */

+#define SPI_CFG2_MIDI_3             (0x8UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000080 */

+

+#define SPI_CFG2_IOSWP_Pos          (15U)

+#define SPI_CFG2_IOSWP_Msk          (0x1UL << SPI_CFG2_IOSWP_Pos)              /*!< 0x00008000 */

+#define SPI_CFG2_IOSWP              SPI_CFG2_IOSWP_Msk                         /*!<Swap functionality of MISO and MOSI pins */

+

+#define SPI_CFG2_COMM_Pos           (17U)

+#define SPI_CFG2_COMM_Msk           (0x3UL << SPI_CFG2_COMM_Pos)               /*!< 0x00060000 */

+#define SPI_CFG2_COMM               SPI_CFG2_COMM_Msk                          /*!<COMM [1:0]: SPI Communication Mode*/

+#define SPI_CFG2_COMM_0             (0x1UL << SPI_CFG2_COMM_Pos)                /*!< 0x00020000 */

+#define SPI_CFG2_COMM_1             (0x2UL << SPI_CFG2_COMM_Pos)                /*!< 0x00040000 */

+

+#define SPI_CFG2_SP_Pos             (19U)

+#define SPI_CFG2_SP_Msk             (0x7UL << SPI_CFG2_SP_Pos)                 /*!< 0x00380000 */

+#define SPI_CFG2_SP                 SPI_CFG2_SP_Msk                            /*!<SP[2:0]: Serial Protocol */

+#define SPI_CFG2_SP_0               (0x1UL << SPI_CFG2_SP_Pos)                  /*!< 0x00080000 */

+#define SPI_CFG2_SP_1               (0x2UL << SPI_CFG2_SP_Pos)                  /*!< 0x00100000 */

+#define SPI_CFG2_SP_2               (0x4UL << SPI_CFG2_SP_Pos)                  /*!< 0x00200000 */

+

+#define SPI_CFG2_MASTER_Pos         (22U)

+#define SPI_CFG2_MASTER_Msk         (0x1UL << SPI_CFG2_MASTER_Pos)             /*!< 0x00400000 */

+#define SPI_CFG2_MASTER             SPI_CFG2_MASTER_Msk                        /*!<SPI Master           */

+#define SPI_CFG2_LSBFRST_Pos        (23U)

+#define SPI_CFG2_LSBFRST_Msk        (0x1UL << SPI_CFG2_LSBFRST_Pos)            /*!< 0x00800000 */

+#define SPI_CFG2_LSBFRST            SPI_CFG2_LSBFRST_Msk                       /*!<Data frame format               */

+#define SPI_CFG2_CPHA_Pos           (24U)

+#define SPI_CFG2_CPHA_Msk           (0x1UL << SPI_CFG2_CPHA_Pos)               /*!< 0x01000000 */

+#define SPI_CFG2_CPHA               SPI_CFG2_CPHA_Msk                          /*!<Clock Phase      */

+#define SPI_CFG2_CPOL_Pos           (25U)

+#define SPI_CFG2_CPOL_Msk           (0x1UL << SPI_CFG2_CPOL_Pos)               /*!< 0x02000000 */

+#define SPI_CFG2_CPOL               SPI_CFG2_CPOL_Msk                          /*!<Clock Polarity   */

+#define SPI_CFG2_SSM_Pos            (26U)

+#define SPI_CFG2_SSM_Msk            (0x1UL << SPI_CFG2_SSM_Pos)                /*!< 0x04000000 */

+#define SPI_CFG2_SSM                SPI_CFG2_SSM_Msk                           /*!<Software slave management */

+

+#define SPI_CFG2_SSIOP_Pos          (28U)

+#define SPI_CFG2_SSIOP_Msk          (0x1UL << SPI_CFG2_SSIOP_Pos)              /*!< 0x10000000 */

+#define SPI_CFG2_SSIOP              SPI_CFG2_SSIOP_Msk                         /*!<SS input/output polarity */

+#define SPI_CFG2_SSOE_Pos           (29U)

+#define SPI_CFG2_SSOE_Msk           (0x1UL << SPI_CFG2_SSOE_Pos)               /*!< 0x20000000 */

+#define SPI_CFG2_SSOE               SPI_CFG2_SSOE_Msk                          /*!<SS output enable */

+#define SPI_CFG2_SSOM_Pos           (30U)

+#define SPI_CFG2_SSOM_Msk           (0x1UL << SPI_CFG2_SSOM_Pos)               /*!< 0x40000000 */

+#define SPI_CFG2_SSOM               SPI_CFG2_SSOM_Msk                          /*!<SS output management in master mode */

+

+#define SPI_CFG2_AFCNTR_Pos         (31U)

+#define SPI_CFG2_AFCNTR_Msk         (0x1UL << SPI_CFG2_AFCNTR_Pos)             /*!< 0x80000000 */

+#define SPI_CFG2_AFCNTR             SPI_CFG2_AFCNTR_Msk                        /*!<Alternate function GPIOs control */

+

+/*******************  Bit definition for SPI_IER register  ********************/

+#define SPI_IER_RXPIE_Pos           (0U)

+#define SPI_IER_RXPIE_Msk           (0x1UL << SPI_IER_RXPIE_Pos)               /*!< 0x00000001 */

+#define SPI_IER_RXPIE               SPI_IER_RXPIE_Msk                          /*!<RXP Interrupt Enable            */

+#define SPI_IER_TXPIE_Pos           (1U)

+#define SPI_IER_TXPIE_Msk           (0x1UL << SPI_IER_TXPIE_Pos)               /*!< 0x00000002 */

+#define SPI_IER_TXPIE               SPI_IER_TXPIE_Msk                          /*!<TXP interrupt enable            */

+#define SPI_IER_DXPIE_Pos           (2U)

+#define SPI_IER_DXPIE_Msk           (0x1UL << SPI_IER_DXPIE_Pos)               /*!< 0x00000004 */

+#define SPI_IER_DXPIE               SPI_IER_DXPIE_Msk                          /*!<DXP interrupt enable            */

+#define SPI_IER_EOTIE_Pos           (3U)

+#define SPI_IER_EOTIE_Msk           (0x1UL << SPI_IER_EOTIE_Pos)               /*!< 0x00000008 */

+#define SPI_IER_EOTIE               SPI_IER_EOTIE_Msk                          /*!<EOT/SUSP/TXC interrupt enable   */

+#define SPI_IER_TXTFIE_Pos          (4U)

+#define SPI_IER_TXTFIE_Msk          (0x1UL << SPI_IER_TXTFIE_Pos)              /*!< 0x00000010 */

+#define SPI_IER_TXTFIE              SPI_IER_TXTFIE_Msk                         /*!<TXTF interrupt enable           */

+#define SPI_IER_UDRIE_Pos           (5U)

+#define SPI_IER_UDRIE_Msk           (0x1UL << SPI_IER_UDRIE_Pos)               /*!< 0x00000020 */

+#define SPI_IER_UDRIE               SPI_IER_UDRIE_Msk                          /*!<UDR interrupt enable            */

+#define SPI_IER_OVRIE_Pos           (6U)

+#define SPI_IER_OVRIE_Msk           (0x1UL << SPI_IER_OVRIE_Pos)               /*!< 0x00000040 */

+#define SPI_IER_OVRIE               SPI_IER_OVRIE_Msk                          /*!<OVR interrupt enable            */

+#define SPI_IER_CRCEIE_Pos          (7U)

+#define SPI_IER_CRCEIE_Msk          (0x1UL << SPI_IER_CRCEIE_Pos)               /*!< 0x00000080 */

+#define SPI_IER_CRCEIE              SPI_IER_CRCEIE_Msk                          /*!<CRCE interrupt enable           */

+#define SPI_IER_TIFREIE_Pos         (8U)

+#define SPI_IER_TIFREIE_Msk         (0x1UL << SPI_IER_TIFREIE_Pos)             /*!< 0x00000100 */

+#define SPI_IER_TIFREIE             SPI_IER_TIFREIE_Msk                        /*!<TI Frame Error interrupt enable */

+#define SPI_IER_MODFIE_Pos          (9U)

+#define SPI_IER_MODFIE_Msk          (0x1UL << SPI_IER_MODFIE_Pos)              /*!< 0x00000200 */

+#define SPI_IER_MODFIE              SPI_IER_MODFIE_Msk                         /*!<MODF interrupt enable           */

+#define SPI_IER_TSERFIE_Pos         (10U)

+#define SPI_IER_TSERFIE_Msk         (0x1UL << SPI_IER_TSERFIE_Pos)              /*!< 0x00000400 */

+#define SPI_IER_TSERFIE             SPI_IER_TSERFIE_Msk                        /*!<TSERF interrupt enable          */

+

+/*******************  Bit definition for SPI_SR register  ********************/

+#define SPI_SR_RXP_Pos              (0U)

+#define SPI_SR_RXP_Msk              (0x1UL << SPI_SR_RXP_Pos)                  /*!< 0x00000001 */

+#define SPI_SR_RXP                  SPI_SR_RXP_Msk                             /*!<Rx-Packet available             */

+#define SPI_SR_TXP_Pos              (1U)

+#define SPI_SR_TXP_Msk              (0x1UL << SPI_SR_TXP_Pos)                  /*!< 0x00000002 */

+#define SPI_SR_TXP                  SPI_SR_TXP_Msk                             /*!<Tx-Packet space available       */

+#define SPI_SR_DXP_Pos              (2U)

+#define SPI_SR_DXP_Msk              (0x1UL << SPI_SR_DXP_Pos)                  /*!< 0x00000004 */

+#define SPI_SR_DXP                  SPI_SR_DXP_Msk                             /*!<Duplex Packet available         */

+#define SPI_SR_EOT_Pos              (3U)

+#define SPI_SR_EOT_Msk              (0x1UL << SPI_SR_EOT_Pos)                  /*!< 0x00000008 */

+#define SPI_SR_EOT                  SPI_SR_EOT_Msk                             /*!<Duplex Packet available         */

+#define SPI_SR_TXTF_Pos             (4U)

+#define SPI_SR_TXTF_Msk             (0x1UL << SPI_SR_TXTF_Pos)                 /*!< 0x00000010 */

+#define SPI_SR_TXTF                 SPI_SR_TXTF_Msk                            /*!<Transmission Transfer Filled    */

+#define SPI_SR_UDR_Pos              (5U)

+#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000020 */

+#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<UDR at Slave transmission       */

+#define SPI_SR_OVR_Pos              (6U)

+#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */

+#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Rx-Packet available             */

+#define SPI_SR_CRCE_Pos             (7U)

+#define SPI_SR_CRCE_Msk             (0x1UL << SPI_SR_CRCE_Pos)                 /*!< 0x00000080 */

+#define SPI_SR_CRCE                 SPI_SR_CRCE_Msk                            /*!<CRC Error Detected              */

+#define SPI_SR_TIFRE_Pos            (8U)

+#define SPI_SR_TIFRE_Msk            (0x1UL << SPI_SR_TIFRE_Pos)                /*!< 0x00000100 */

+#define SPI_SR_TIFRE                SPI_SR_TIFRE_Msk                           /*!<TI frame format error Detected  */

+#define SPI_SR_MODF_Pos             (9U)

+#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000200 */

+#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode Fault Detected             */

+#define SPI_SR_TSERF_Pos            (10U)

+#define SPI_SR_TSERF_Msk            (0x1UL << SPI_SR_TSERF_Pos)                /*!< 0x00000400 */

+#define SPI_SR_TSERF                SPI_SR_TSERF_Msk                           /*!<Number of SPI data to be transacted reloaded     */

+#define SPI_SR_SUSP_Pos             (11U)

+#define SPI_SR_SUSP_Msk             (0x1UL << SPI_SR_SUSP_Pos)                 /*!< 0x00000800 */

+#define SPI_SR_SUSP                 SPI_SR_SUSP_Msk                            /*!<SUSP is set by hardware  */

+#define SPI_SR_TXC_Pos              (12U)

+#define SPI_SR_TXC_Msk              (0x1UL << SPI_SR_TXC_Pos)                  /*!< 0x00001000 */

+#define SPI_SR_TXC                  SPI_SR_TXC_Msk                             /*!<TxFIFO transmission complete */

+#define SPI_SR_RXPLVL_Pos           (13U)

+#define SPI_SR_RXPLVL_Msk           (0x3UL << SPI_SR_RXPLVL_Pos)               /*!< 0x00006000 */

+#define SPI_SR_RXPLVL               SPI_SR_RXPLVL_Msk                          /*!<RxFIFO Packing Level                             */

+#define SPI_SR_RXPLVL_0             (0x1UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00002000 */

+#define SPI_SR_RXPLVL_1             (0x2UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00004000 */

+#define SPI_SR_RXWNE_Pos            (15U)

+#define SPI_SR_RXWNE_Msk            (0x1UL << SPI_SR_RXWNE_Pos)                /*!< 0x00008000 */

+#define SPI_SR_RXWNE                SPI_SR_RXWNE_Msk                           /*!<Rx FIFO Word Not Empty                           */

+#define SPI_SR_CTSIZE_Pos           (16U)

+#define SPI_SR_CTSIZE_Msk           (0xFFFFUL << SPI_SR_CTSIZE_Pos)            /*!< 0xFFFF0000 */

+#define SPI_SR_CTSIZE               SPI_SR_CTSIZE_Msk                          /*!<Number of data frames remaining in TSIZE         */

+

+/*******************  Bit definition for SPI_IFCR register  ********************/

+#define SPI_IFCR_EOTC_Pos           (3U)

+#define SPI_IFCR_EOTC_Msk           (0x1UL << SPI_IFCR_EOTC_Pos)               /*!< 0x00000008 */

+#define SPI_IFCR_EOTC               SPI_IFCR_EOTC_Msk                          /*!<End Of Transfer flag clear              */

+#define SPI_IFCR_TXTFC_Pos          (4U)

+#define SPI_IFCR_TXTFC_Msk          (0x1UL << SPI_IFCR_TXTFC_Pos)              /*!< 0x00000010 */

+#define SPI_IFCR_TXTFC              SPI_IFCR_TXTFC_Msk                         /*!<Transmission Transfer Filled flag clear */

+#define SPI_IFCR_UDRC_Pos           (5U)

+#define SPI_IFCR_UDRC_Msk           (0x1UL << SPI_IFCR_UDRC_Pos)               /*!< 0x00000020 */

+#define SPI_IFCR_UDRC               SPI_IFCR_UDRC_Msk                          /*!<Underrun flag clear                     */

+#define SPI_IFCR_OVRC_Pos           (6U)

+#define SPI_IFCR_OVRC_Msk           (0x1UL << SPI_IFCR_OVRC_Pos)               /*!< 0x00000040 */

+#define SPI_IFCR_OVRC               SPI_IFCR_OVRC_Msk                          /*!<Overrun flag clear                      */

+#define SPI_IFCR_CRCEC_Pos          (7U)

+#define SPI_IFCR_CRCEC_Msk          (0x1UL << SPI_IFCR_CRCEC_Pos)              /*!< 0x00000080 */

+#define SPI_IFCR_CRCEC              SPI_IFCR_CRCEC_Msk                         /*!<CRC Error flag clear                    */

+#define SPI_IFCR_TIFREC_Pos         (8U)

+#define SPI_IFCR_TIFREC_Msk         (0x1UL << SPI_IFCR_TIFREC_Pos)             /*!< 0x00000100 */

+#define SPI_IFCR_TIFREC             SPI_IFCR_TIFREC_Msk                        /*!<TI frame format error flag clear        */

+#define SPI_IFCR_MODFC_Pos          (9U)

+#define SPI_IFCR_MODFC_Msk          (0x1UL << SPI_IFCR_MODFC_Pos)              /*!< 0x00000200 */

+#define SPI_IFCR_MODFC              SPI_IFCR_MODFC_Msk                         /*!<Mode Fault flag clear                   */

+#define SPI_IFCR_TSERFC_Pos         (10U)

+#define SPI_IFCR_TSERFC_Msk         (0x1UL << SPI_IFCR_TSERFC_Pos)             /*!< 0x00000400 */

+#define SPI_IFCR_TSERFC             SPI_IFCR_TSERFC_Msk                        /*!<TSERFC flag clear                       */

+#define SPI_IFCR_SUSPC_Pos          (11U)

+#define SPI_IFCR_SUSPC_Msk          (0x1UL << SPI_IFCR_SUSPC_Pos)              /*!< 0x00000800 */

+#define SPI_IFCR_SUSPC              SPI_IFCR_SUSPC_Msk                         /*!<SUSPend flag clear                      */

+

+/*******************  Bit definition for SPI_TXDR register  ********************/

+#define SPI_TXDR_TXDR_Pos           (0U)

+#define SPI_TXDR_TXDR_Msk           (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)        /*!< 0xFFFFFFFF */

+#define SPI_TXDR_TXDR               SPI_TXDR_TXDR_Msk                          /* Transmit Data Register */

+

+/*******************  Bit definition for SPI_RXDR register  ********************/

+#define SPI_RXDR_RXDR_Pos           (0U)

+#define SPI_RXDR_RXDR_Msk           (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)        /*!< 0xFFFFFFFF */

+#define SPI_RXDR_RXDR               SPI_RXDR_RXDR_Msk                          /* Receive Data Register  */

+

+/*******************  Bit definition for SPI_CRCPOLY register  ********************/

+#define SPI_CRCPOLY_CRCPOLY_Pos     (0U)

+#define SPI_CRCPOLY_CRCPOLY_Msk     (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)  /*!< 0xFFFFFFFF */

+#define SPI_CRCPOLY_CRCPOLY         SPI_CRCPOLY_CRCPOLY_Msk                    /* CRC Polynomial register  */

+

+/*******************  Bit definition for SPI_TXCRC register  ********************/

+#define SPI_TXCRC_TXCRC_Pos         (0U)

+#define SPI_TXCRC_TXCRC_Msk         (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_TXCRC_TXCRC             SPI_TXCRC_TXCRC_Msk                        /* CRCRegister for transmitter */

+

+/*******************  Bit definition for SPI_RXCRC register  ********************/

+#define SPI_RXCRC_RXCRC_Pos         (0U)

+#define SPI_RXCRC_RXCRC_Msk         (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_RXCRC_RXCRC             SPI_RXCRC_RXCRC_Msk                        /* CRCRegister for receiver */

+

+/*******************  Bit definition for SPI_UDRDR register  ********************/

+#define SPI_UDRDR_UDRDR_Pos         (0U)

+#define SPI_UDRDR_UDRDR_Msk         (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_UDRDR_UDRDR             SPI_UDRDR_UDRDR_Msk                        /* Data at slave underrun condition */

+

+/******************  Bit definition for SPI_I2SCFGR register  *****************/

+#define SPI_I2SCFGR_I2SMOD_Pos      (0U)

+#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000001 */

+#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */

+#define SPI_I2SCFGR_I2SCFG_Pos      (1U)

+#define SPI_I2SCFGR_I2SCFG_Msk      (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x0000000E */

+#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[2:0] I2S configuration mode                */

+#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000002 */

+#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000004 */

+#define SPI_I2SCFGR_I2SCFG_2        (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000008 */

+#define SPI_I2SCFGR_I2SSTD_Pos      (4U)

+#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */

+#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] I2S standard selection                */

+#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */

+#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */

+#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)

+#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */

+#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                         */

+#define SPI_I2SCFGR_DATLEN_Pos      (8U)

+#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000300 */

+#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] Data length to be transferred         */

+#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000100 */

+#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000200 */

+#define SPI_I2SCFGR_CHLEN_Pos       (10U)

+#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000400 */

+#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */

+#define SPI_I2SCFGR_CKPOL_Pos       (11U)

+#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000800 */

+#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<Steady state clock polarity                       */

+#define SPI_I2SCFGR_FIXCH_Pos       (12U)

+#define SPI_I2SCFGR_FIXCH_Msk       (0x1UL << SPI_I2SCFGR_FIXCH_Pos)           /*!< 0x00001000 */

+#define SPI_I2SCFGR_FIXCH           SPI_I2SCFGR_FIXCH_Msk                      /*!<Fixed channel length in SLAVE                     */

+#define SPI_I2SCFGR_WSINV_Pos       (13U)

+#define SPI_I2SCFGR_WSINV_Msk       (0x1UL << SPI_I2SCFGR_WSINV_Pos)           /*!< 0x00002000 */

+#define SPI_I2SCFGR_WSINV           SPI_I2SCFGR_WSINV_Msk                      /*!<Word select inversion                             */

+#define SPI_I2SCFGR_DATFMT_Pos      (14U)

+#define SPI_I2SCFGR_DATFMT_Msk      (0x1UL << SPI_I2SCFGR_DATFMT_Pos)          /*!< 0x00004000 */

+#define SPI_I2SCFGR_DATFMT          SPI_I2SCFGR_DATFMT_Msk                     /*!<Data format                                       */

+#define SPI_I2SCFGR_I2SDIV_Pos      (16U)

+#define SPI_I2SCFGR_I2SDIV_Msk      (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)         /*!< 0x00FF0000 */

+#define SPI_I2SCFGR_I2SDIV          SPI_I2SCFGR_I2SDIV_Msk                     /*!<I2S Linear prescaler */

+#define SPI_I2SCFGR_ODD_Pos         (24U)

+#define SPI_I2SCFGR_ODD_Msk         (0x1UL << SPI_I2SCFGR_ODD_Pos)             /*!< 0x01000000 */

+#define SPI_I2SCFGR_ODD             SPI_I2SCFGR_ODD_Msk                        /*!<Odd factor for the prescaler */

+#define SPI_I2SCFGR_MCKOE_Pos       (25U)

+#define SPI_I2SCFGR_MCKOE_Msk       (0x1UL << SPI_I2SCFGR_MCKOE_Pos)           /*!< 0x02000000 */

+#define SPI_I2SCFGR_MCKOE           SPI_I2SCFGR_MCKOE_Msk                      /*!<Master Clock Output Enable */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    QUADSPI                                 */

+/*                                                                            */

+/******************************************************************************/

+/*****************  Bit definition for QUADSPI_CR register  *******************/

+#define QUADSPI_CR_EN_Pos                (0U)

+#define QUADSPI_CR_EN_Msk                (0x1UL << QUADSPI_CR_EN_Pos)          /*!< 0x00000001 */

+#define QUADSPI_CR_EN                    QUADSPI_CR_EN_Msk                     /*!< Enable */

+#define QUADSPI_CR_ABORT_Pos             (1U)

+#define QUADSPI_CR_ABORT_Msk             (0x1UL << QUADSPI_CR_ABORT_Pos)       /*!< 0x00000002 */

+#define QUADSPI_CR_ABORT                 QUADSPI_CR_ABORT_Msk                  /*!< Abort request */

+#define QUADSPI_CR_DMAEN_Pos             (2U)

+#define QUADSPI_CR_DMAEN_Msk             (0x1UL << QUADSPI_CR_DMAEN_Pos)       /*!< 0x00000004 */

+#define QUADSPI_CR_DMAEN                 QUADSPI_CR_DMAEN_Msk                  /*!< DMA Enable */

+#define QUADSPI_CR_TCEN_Pos              (3U)

+#define QUADSPI_CR_TCEN_Msk              (0x1UL << QUADSPI_CR_TCEN_Pos)        /*!< 0x00000008 */

+#define QUADSPI_CR_TCEN                  QUADSPI_CR_TCEN_Msk                   /*!< Timeout Counter Enable */

+#define QUADSPI_CR_SSHIFT_Pos            (4U)

+#define QUADSPI_CR_SSHIFT_Msk            (0x1UL << QUADSPI_CR_SSHIFT_Pos)      /*!< 0x00000010 */

+#define QUADSPI_CR_SSHIFT                QUADSPI_CR_SSHIFT_Msk                 /*!< SSHIFT Sample Shift */

+#define QUADSPI_CR_DFM_Pos               (6U)

+#define QUADSPI_CR_DFM_Msk               (0x1UL << QUADSPI_CR_DFM_Pos)         /*!< 0x00000040 */

+#define QUADSPI_CR_DFM                   QUADSPI_CR_DFM_Msk                    /*!< Dual Flash Mode */

+#define QUADSPI_CR_FSEL_Pos              (7U)

+#define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)        /*!< 0x00000080 */

+#define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select */

+#define QUADSPI_CR_FTHRES_Pos            (8U)

+#define QUADSPI_CR_FTHRES_Msk            (0xFUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000F00 */

+#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level */

+#define QUADSPI_CR_FTHRES_0              (0x1UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */

+#define QUADSPI_CR_FTHRES_1              (0x2UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */

+#define QUADSPI_CR_FTHRES_2              (0x4UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */

+#define QUADSPI_CR_FTHRES_3              (0x8UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */

+#define QUADSPI_CR_TEIE_Pos              (16U)

+#define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)        /*!< 0x00010000 */

+#define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable */

+#define QUADSPI_CR_TCIE_Pos              (17U)

+#define QUADSPI_CR_TCIE_Msk              (0x1UL << QUADSPI_CR_TCIE_Pos)        /*!< 0x00020000 */

+#define QUADSPI_CR_TCIE                  QUADSPI_CR_TCIE_Msk                   /*!< Transfer Complete Interrupt Enable */

+#define QUADSPI_CR_FTIE_Pos              (18U)

+#define QUADSPI_CR_FTIE_Msk              (0x1UL << QUADSPI_CR_FTIE_Pos)        /*!< 0x00040000 */

+#define QUADSPI_CR_FTIE                  QUADSPI_CR_FTIE_Msk                   /*!< FIFO Threshold Interrupt Enable */

+#define QUADSPI_CR_SMIE_Pos              (19U)

+#define QUADSPI_CR_SMIE_Msk              (0x1UL << QUADSPI_CR_SMIE_Pos)        /*!< 0x00080000 */

+#define QUADSPI_CR_SMIE                  QUADSPI_CR_SMIE_Msk                   /*!< Status Match Interrupt Enable */

+#define QUADSPI_CR_TOIE_Pos              (20U)

+#define QUADSPI_CR_TOIE_Msk              (0x1UL << QUADSPI_CR_TOIE_Pos)        /*!< 0x00100000 */

+#define QUADSPI_CR_TOIE                  QUADSPI_CR_TOIE_Msk                   /*!< TimeOut Interrupt Enable */

+#define QUADSPI_CR_APMS_Pos              (22U)

+#define QUADSPI_CR_APMS_Msk              (0x1UL << QUADSPI_CR_APMS_Pos)        /*!< 0x00400000 */

+#define QUADSPI_CR_APMS                  QUADSPI_CR_APMS_Msk                   /*!< Bit 1 */

+#define QUADSPI_CR_PMM_Pos               (23U)

+#define QUADSPI_CR_PMM_Msk               (0x1UL << QUADSPI_CR_PMM_Pos)         /*!< 0x00800000 */

+#define QUADSPI_CR_PMM                   QUADSPI_CR_PMM_Msk                    /*!< Polling Match Mode */

+#define QUADSPI_CR_PRESCALER_Pos         (24U)

+#define QUADSPI_CR_PRESCALER_Msk         (0xFFUL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0xFF000000 */

+#define QUADSPI_CR_PRESCALER             QUADSPI_CR_PRESCALER_Msk              /*!< PRESCALER[7:0] Clock prescaler */

+#define QUADSPI_CR_PRESCALER_0           (0x01UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x01000000 */

+#define QUADSPI_CR_PRESCALER_1           (0x02UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x02000000 */

+#define QUADSPI_CR_PRESCALER_2           (0x04UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x04000000 */

+#define QUADSPI_CR_PRESCALER_3           (0x08UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x08000000 */

+#define QUADSPI_CR_PRESCALER_4           (0x10UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x10000000 */

+#define QUADSPI_CR_PRESCALER_5           (0x20UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x20000000 */

+#define QUADSPI_CR_PRESCALER_6           (0x40UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x40000000 */

+#define QUADSPI_CR_PRESCALER_7           (0x80UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x80000000 */

+

+/*****************  Bit definition for QUADSPI_DCR register  ******************/

+#define QUADSPI_DCR_CKMODE_Pos           (0U)

+#define QUADSPI_DCR_CKMODE_Msk           (0x1UL << QUADSPI_DCR_CKMODE_Pos)     /*!< 0x00000001 */

+#define QUADSPI_DCR_CKMODE               QUADSPI_DCR_CKMODE_Msk                /*!< Mode 0 / Mode 3 */

+#define QUADSPI_DCR_CSHT_Pos             (8U)

+#define QUADSPI_DCR_CSHT_Msk             (0x7UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000700 */

+#define QUADSPI_DCR_CSHT                 QUADSPI_DCR_CSHT_Msk                  /*!< CSHT[2:0]: ChipSelect High Time */

+#define QUADSPI_DCR_CSHT_0               (0x1UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000100 */

+#define QUADSPI_DCR_CSHT_1               (0x2UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000200 */

+#define QUADSPI_DCR_CSHT_2               (0x4UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000400 */

+#define QUADSPI_DCR_FSIZE_Pos            (16U)

+#define QUADSPI_DCR_FSIZE_Msk            (0x1FUL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x001F0000 */

+#define QUADSPI_DCR_FSIZE                QUADSPI_DCR_FSIZE_Msk                 /*!< FSIZE[4:0]: Flash Size */

+#define QUADSPI_DCR_FSIZE_0              (0x01UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00010000 */

+#define QUADSPI_DCR_FSIZE_1              (0x02UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00020000 */

+#define QUADSPI_DCR_FSIZE_2              (0x04UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00040000 */

+#define QUADSPI_DCR_FSIZE_3              (0x08UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00080000 */

+#define QUADSPI_DCR_FSIZE_4              (0x10UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00100000 */

+

+/******************  Bit definition for QUADSPI_SR register  *******************/

+#define QUADSPI_SR_TEF_Pos               (0U)

+#define QUADSPI_SR_TEF_Msk               (0x1UL << QUADSPI_SR_TEF_Pos)         /*!< 0x00000001 */

+#define QUADSPI_SR_TEF                   QUADSPI_SR_TEF_Msk                    /*!< Transfer Error Flag */

+#define QUADSPI_SR_TCF_Pos               (1U)

+#define QUADSPI_SR_TCF_Msk               (0x1UL << QUADSPI_SR_TCF_Pos)         /*!< 0x00000002 */

+#define QUADSPI_SR_TCF                   QUADSPI_SR_TCF_Msk                    /*!< Transfer Complete Flag */

+#define QUADSPI_SR_FTF_Pos               (2U)

+#define QUADSPI_SR_FTF_Msk               (0x1UL << QUADSPI_SR_FTF_Pos)         /*!< 0x00000004 */

+#define QUADSPI_SR_FTF                   QUADSPI_SR_FTF_Msk                    /*!< FIFO Threshlod Flag */

+#define QUADSPI_SR_SMF_Pos               (3U)

+#define QUADSPI_SR_SMF_Msk               (0x1UL << QUADSPI_SR_SMF_Pos)         /*!< 0x00000008 */

+#define QUADSPI_SR_SMF                   QUADSPI_SR_SMF_Msk                    /*!< Status Match Flag */

+#define QUADSPI_SR_TOF_Pos               (4U)

+#define QUADSPI_SR_TOF_Msk               (0x1UL << QUADSPI_SR_TOF_Pos)         /*!< 0x00000010 */

+#define QUADSPI_SR_TOF                   QUADSPI_SR_TOF_Msk                    /*!< Timeout Flag */

+#define QUADSPI_SR_BUSY_Pos              (5U)

+#define QUADSPI_SR_BUSY_Msk              (0x1UL << QUADSPI_SR_BUSY_Pos)        /*!< 0x00000020 */

+#define QUADSPI_SR_BUSY                  QUADSPI_SR_BUSY_Msk                   /*!< Busy */

+#define QUADSPI_SR_FLEVEL_Pos            (8U)

+#define QUADSPI_SR_FLEVEL_Msk            (0x3FUL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00003F00 */

+#define QUADSPI_SR_FLEVEL                QUADSPI_SR_FLEVEL_Msk                 /*!< FIFO Threshlod Flag */

+#define QUADSPI_SR_FLEVEL_0              (0x01UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000100 */

+#define QUADSPI_SR_FLEVEL_1              (0x02UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000200 */

+#define QUADSPI_SR_FLEVEL_2              (0x04UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000400 */

+#define QUADSPI_SR_FLEVEL_3              (0x08UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000800 */

+#define QUADSPI_SR_FLEVEL_4              (0x10UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00001000 */

+#define QUADSPI_SR_FLEVEL_5              (0x20UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00002000 */

+

+/******************  Bit definition for QUADSPI_FCR register  ******************/

+#define QUADSPI_FCR_CTEF_Pos             (0U)

+#define QUADSPI_FCR_CTEF_Msk             (0x1UL << QUADSPI_FCR_CTEF_Pos)       /*!< 0x00000001 */

+#define QUADSPI_FCR_CTEF                 QUADSPI_FCR_CTEF_Msk                  /*!< Clear Transfer Error Flag */

+#define QUADSPI_FCR_CTCF_Pos             (1U)

+#define QUADSPI_FCR_CTCF_Msk             (0x1UL << QUADSPI_FCR_CTCF_Pos)       /*!< 0x00000002 */

+#define QUADSPI_FCR_CTCF                 QUADSPI_FCR_CTCF_Msk                  /*!< Clear Transfer Complete Flag */

+#define QUADSPI_FCR_CSMF_Pos             (3U)

+#define QUADSPI_FCR_CSMF_Msk             (0x1UL << QUADSPI_FCR_CSMF_Pos)       /*!< 0x00000008 */

+#define QUADSPI_FCR_CSMF                 QUADSPI_FCR_CSMF_Msk                  /*!< Clear Status Match Flag */

+#define QUADSPI_FCR_CTOF_Pos             (4U)

+#define QUADSPI_FCR_CTOF_Msk             (0x1UL << QUADSPI_FCR_CTOF_Pos)       /*!< 0x00000010 */

+#define QUADSPI_FCR_CTOF                 QUADSPI_FCR_CTOF_Msk                  /*!< Clear Timeout Flag */

+

+/******************  Bit definition for QUADSPI_DLR register  ******************/

+#define QUADSPI_DLR_DL_Pos               (0U)

+#define QUADSPI_DLR_DL_Msk               (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)  /*!< 0xFFFFFFFF */

+#define QUADSPI_DLR_DL                   QUADSPI_DLR_DL_Msk                    /*!< DL[31:0]: Data Length */

+

+/******************  Bit definition for QUADSPI_CCR register  ******************/

+#define QUADSPI_CCR_INSTRUCTION_Pos      (0U)

+#define QUADSPI_CCR_INSTRUCTION_Msk      (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */

+#define QUADSPI_CCR_INSTRUCTION          QUADSPI_CCR_INSTRUCTION_Msk             /*!< INSTRUCTION[7:0]: Instruction */

+#define QUADSPI_CCR_INSTRUCTION_0        (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */

+#define QUADSPI_CCR_INSTRUCTION_1        (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */

+#define QUADSPI_CCR_INSTRUCTION_2        (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */

+#define QUADSPI_CCR_INSTRUCTION_3        (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */

+#define QUADSPI_CCR_INSTRUCTION_4        (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */

+#define QUADSPI_CCR_INSTRUCTION_5        (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */

+#define QUADSPI_CCR_INSTRUCTION_6        (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */

+#define QUADSPI_CCR_INSTRUCTION_7        (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */

+#define QUADSPI_CCR_IMODE_Pos            (8U)

+#define QUADSPI_CCR_IMODE_Msk            (0x3UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000300 */

+#define QUADSPI_CCR_IMODE                QUADSPI_CCR_IMODE_Msk                   /*!< IMODE[1:0]: Instruction Mode */

+#define QUADSPI_CCR_IMODE_0              (0x1UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000100 */

+#define QUADSPI_CCR_IMODE_1              (0x2UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000200 */

+#define QUADSPI_CCR_ADMODE_Pos           (10U)

+#define QUADSPI_CCR_ADMODE_Msk           (0x3UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000C00 */

+#define QUADSPI_CCR_ADMODE               QUADSPI_CCR_ADMODE_Msk                  /*!< ADMODE[1:0]: Address Mode */

+#define QUADSPI_CCR_ADMODE_0             (0x1UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000400 */

+#define QUADSPI_CCR_ADMODE_1             (0x2UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000800 */

+#define QUADSPI_CCR_ADSIZE_Pos           (12U)

+#define QUADSPI_CCR_ADSIZE_Msk           (0x3UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00003000 */

+#define QUADSPI_CCR_ADSIZE               QUADSPI_CCR_ADSIZE_Msk                  /*!< ADSIZE[1:0]: Address Size */

+#define QUADSPI_CCR_ADSIZE_0             (0x1UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00001000 */

+#define QUADSPI_CCR_ADSIZE_1             (0x2UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00002000 */

+#define QUADSPI_CCR_ABMODE_Pos           (14U)

+#define QUADSPI_CCR_ABMODE_Msk           (0x3UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x0000C000 */

+#define QUADSPI_CCR_ABMODE               QUADSPI_CCR_ABMODE_Msk                  /*!< ABMODE[1:0]: Alternate Bytes Mode */

+#define QUADSPI_CCR_ABMODE_0             (0x1UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00004000 */

+#define QUADSPI_CCR_ABMODE_1             (0x2UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00008000 */

+#define QUADSPI_CCR_ABSIZE_Pos           (16U)

+#define QUADSPI_CCR_ABSIZE_Msk           (0x3UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00030000 */

+#define QUADSPI_CCR_ABSIZE               QUADSPI_CCR_ABSIZE_Msk                  /*!< ABSIZE[1:0]: Instruction Mode */

+#define QUADSPI_CCR_ABSIZE_0             (0x1UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00010000 */

+#define QUADSPI_CCR_ABSIZE_1             (0x2UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00020000 */

+#define QUADSPI_CCR_DCYC_Pos             (18U)

+#define QUADSPI_CCR_DCYC_Msk             (0x1FUL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x007C0000 */

+#define QUADSPI_CCR_DCYC                 QUADSPI_CCR_DCYC_Msk                    /*!< DCYC[4:0]: Dummy Cycles */

+#define QUADSPI_CCR_DCYC_0               (0x01UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00040000 */

+#define QUADSPI_CCR_DCYC_1               (0x02UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00080000 */

+#define QUADSPI_CCR_DCYC_2               (0x04UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00100000 */

+#define QUADSPI_CCR_DCYC_3               (0x08UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00200000 */

+#define QUADSPI_CCR_DCYC_4               (0x10UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00400000 */

+#define QUADSPI_CCR_DMODE_Pos            (24U)

+#define QUADSPI_CCR_DMODE_Msk            (0x3UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x03000000 */

+#define QUADSPI_CCR_DMODE                QUADSPI_CCR_DMODE_Msk                   /*!< DMODE[1:0]: Data Mode */

+#define QUADSPI_CCR_DMODE_0              (0x1UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x01000000 */

+#define QUADSPI_CCR_DMODE_1              (0x2UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x02000000 */

+#define QUADSPI_CCR_FMODE_Pos            (26U)

+#define QUADSPI_CCR_FMODE_Msk            (0x3UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x0C000000 */

+#define QUADSPI_CCR_FMODE                QUADSPI_CCR_FMODE_Msk                   /*!< FMODE[1:0]: Functional Mode */

+#define QUADSPI_CCR_FMODE_0              (0x1UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x04000000 */

+#define QUADSPI_CCR_FMODE_1              (0x2UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x08000000 */

+#define QUADSPI_CCR_SIOO_Pos             (28U)

+#define QUADSPI_CCR_SIOO_Msk             (0x1UL << QUADSPI_CCR_SIOO_Pos)         /*!< 0x10000000 */

+#define QUADSPI_CCR_SIOO                 QUADSPI_CCR_SIOO_Msk                    /*!< SIOO: Send Instruction Only Once Mode */

+#define QUADSPI_CCR_DHHC_Pos             (30U)

+#define QUADSPI_CCR_DHHC_Msk             (0x1UL << QUADSPI_CCR_DHHC_Pos)         /*!< 0x40000000 */

+#define QUADSPI_CCR_DHHC                 QUADSPI_CCR_DHHC_Msk                    /*!< DHHC: DDR hold half cycle */

+#define QUADSPI_CCR_DDRM_Pos             (31U)

+#define QUADSPI_CCR_DDRM_Msk             (0x1UL << QUADSPI_CCR_DDRM_Pos)         /*!< 0x80000000 */

+#define QUADSPI_CCR_DDRM                 QUADSPI_CCR_DDRM_Msk                    /*!< DDRM: Double Data Rate Mode */

+

+/******************  Bit definition for QUADSPI_AR register  *******************/

+#define QUADSPI_AR_ADDRESS_Pos           (0U)

+#define QUADSPI_AR_ADDRESS_Msk           (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_AR_ADDRESS               QUADSPI_AR_ADDRESS_Msk                /*!< ADDRESS[31:0]: Address */

+

+/******************  Bit definition for QUADSPI_ABR register  ******************/

+#define QUADSPI_ABR_ALTERNATE_Pos        (0U)

+#define QUADSPI_ABR_ALTERNATE_Msk        (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_ABR_ALTERNATE            QUADSPI_ABR_ALTERNATE_Msk             /*!< ALTERNATE[31:0]: Alternate Bytes */

+

+/******************  Bit definition for QUADSPI_DR register  *******************/

+#define QUADSPI_DR_DATA_Pos              (0U)

+#define QUADSPI_DR_DATA_Msk              (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_DR_DATA                  QUADSPI_DR_DATA_Msk                   /*!< DATA[31:0]: Data */

+

+/******************  Bit definition for QUADSPI_PSMKR register  ****************/

+#define QUADSPI_PSMKR_MASK_Pos           (0U)

+#define QUADSPI_PSMKR_MASK_Msk           (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_PSMKR_MASK               QUADSPI_PSMKR_MASK_Msk                /*!< MASK[31:0]: Status Mask */

+

+/******************  Bit definition for QUADSPI_PSMAR register  ****************/

+#define QUADSPI_PSMAR_MATCH_Pos          (0U)

+#define QUADSPI_PSMAR_MATCH_Msk          (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_PSMAR_MATCH              QUADSPI_PSMAR_MATCH_Msk               /*!< MATCH[31:0]: Status Match */

+

+/******************  Bit definition for QUADSPI_PIR register  *****************/

+#define QUADSPI_PIR_INTERVAL_Pos         (0U)

+#define QUADSPI_PIR_INTERVAL_Msk         (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */

+#define QUADSPI_PIR_INTERVAL             QUADSPI_PIR_INTERVAL_Msk              /*!< INTERVAL[15:0]: Polling Interval */

+

+/******************  Bit definition for QUADSPI_LPTR register  *****************/

+#define QUADSPI_LPTR_TIMEOUT_Pos         (0U)

+#define QUADSPI_LPTR_TIMEOUT_Msk         (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */

+#define QUADSPI_LPTR_TIMEOUT             QUADSPI_LPTR_TIMEOUT_Msk              /*!< TIMEOUT[15:0]: Timeout period */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                 SYSCFG                                     */

+/*                                                                            */

+/******************************************************************************/

+

+/******************  Bit definition for SYSCFG_PMCR register  ******************/

+#define SYSCFG_PMCR_I2C1_FMP_Pos        (0U)

+#define SYSCFG_PMCR_I2C1_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos)    /*!< 0x00000001 */

+#define SYSCFG_PMCR_I2C1_FMP            SYSCFG_PMCR_I2C1_FMP_Msk               /*!< I2C1 Fast mode plus */

+#define SYSCFG_PMCR_I2C2_FMP_Pos        (1U)

+#define SYSCFG_PMCR_I2C2_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos)    /*!< 0x00000002 */

+#define SYSCFG_PMCR_I2C2_FMP            SYSCFG_PMCR_I2C2_FMP_Msk               /*!< I2C2 Fast mode plus */

+#define SYSCFG_PMCR_I2C3_FMP_Pos        (2U)

+#define SYSCFG_PMCR_I2C3_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos)    /*!< 0x00000004 */

+#define SYSCFG_PMCR_I2C3_FMP            SYSCFG_PMCR_I2C3_FMP_Msk               /*!< I2C3 Fast mode plus */

+#define SYSCFG_PMCR_I2C4_FMP_Pos        (3U)

+#define SYSCFG_PMCR_I2C4_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos)    /*!< 0x00000008 */

+#define SYSCFG_PMCR_I2C4_FMP            SYSCFG_PMCR_I2C4_FMP_Msk               /*!< I2C4 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB6_FMP_Pos     (4U)

+#define SYSCFG_PMCR_I2C_PB6_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */

+#define SYSCFG_PMCR_I2C_PB6_FMP         SYSCFG_PMCR_I2C_PB6_FMP_Msk            /*!< I2C PB6 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB7_FMP_Pos     (5U)

+#define SYSCFG_PMCR_I2C_PB7_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */

+#define SYSCFG_PMCR_I2C_PB7_FMP         SYSCFG_PMCR_I2C_PB7_FMP_Msk            /*!< I2C PB7 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB8_FMP_Pos     (6U)

+#define SYSCFG_PMCR_I2C_PB8_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */

+#define SYSCFG_PMCR_I2C_PB8_FMP         SYSCFG_PMCR_I2C_PB8_FMP_Msk            /*!< I2C PB8 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB9_FMP_Pos     (7U)

+#define SYSCFG_PMCR_I2C_PB9_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */

+#define SYSCFG_PMCR_I2C_PB9_FMP         SYSCFG_PMCR_I2C_PB9_FMP_Msk            /*!< I2C PB9 Fast mode plus */

+#define SYSCFG_PMCR_BOOSTEN_Pos         (8U)

+#define SYSCFG_PMCR_BOOSTEN_Msk         (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos)     /*!< 0x00000100 */

+#define SYSCFG_PMCR_BOOSTEN             SYSCFG_PMCR_BOOSTEN_Msk                /*!< I/O analog switch voltage booster enable */

+

+#define SYSCFG_PMCR_BOOSTVDDSEL_Pos     (9U)

+#define SYSCFG_PMCR_BOOSTVDDSEL_Msk     (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos) /*!< 0x00000200 */

+#define SYSCFG_PMCR_BOOSTVDDSEL         SYSCFG_PMCR_BOOSTVDDSEL_Msk            /*!< Analog switch supply source selection : VDD/VDDA */

+

+#define SYSCFG_PMCR_EPIS_SEL_Pos        (21U)

+#define SYSCFG_PMCR_EPIS_SEL_Msk        (0x7UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00E00000 */

+#define SYSCFG_PMCR_EPIS_SEL            SYSCFG_PMCR_EPIS_SEL_Msk               /*!< Ethernet PHY Interface Selection */

+#define SYSCFG_PMCR_EPIS_SEL_0          (0x1UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00200000 */

+#define SYSCFG_PMCR_EPIS_SEL_1          (0x2UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00400000 */

+#define SYSCFG_PMCR_EPIS_SEL_2          (0x4UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00800000 */

+#define SYSCFG_PMCR_PA0SO_Pos           (24U)

+#define SYSCFG_PMCR_PA0SO_Msk           (0x1UL << SYSCFG_PMCR_PA0SO_Pos)       /*!< 0x01000000 */

+#define SYSCFG_PMCR_PA0SO               SYSCFG_PMCR_PA0SO_Msk                  /*!< PA0 Switch Open */

+#define SYSCFG_PMCR_PA1SO_Pos           (25U)

+#define SYSCFG_PMCR_PA1SO_Msk           (0x1UL << SYSCFG_PMCR_PA1SO_Pos)       /*!< 0x02000000 */

+#define SYSCFG_PMCR_PA1SO               SYSCFG_PMCR_PA1SO_Msk                  /*!< PA1 Switch Open */

+#define SYSCFG_PMCR_PC2SO_Pos           (26U)

+#define SYSCFG_PMCR_PC2SO_Msk           (0x1UL << SYSCFG_PMCR_PC2SO_Pos)       /*!< 0x04000000 */

+#define SYSCFG_PMCR_PC2SO               SYSCFG_PMCR_PC2SO_Msk                  /*!< PC2 Switch Open */

+#define SYSCFG_PMCR_PC3SO_Pos           (27U)

+#define SYSCFG_PMCR_PC3SO_Msk           (0x1UL << SYSCFG_PMCR_PC3SO_Pos)       /*!< 0x08000000 */

+#define SYSCFG_PMCR_PC3SO               SYSCFG_PMCR_PC3SO_Msk                  /*!< PC3 Switch Open */

+

+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/

+#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)

+#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */

+#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)

+#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */

+#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)

+#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000F00 */

+#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */

+#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)

+#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x0000F000 */

+#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */

+/**

+  * @brief   EXTI0 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */

+

+/**

+  * @brief   EXTI1 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */

+/**

+  * @brief   EXTI2 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */

+

+/**

+  * @brief   EXTI3 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/

+#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)

+#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */

+#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)

+#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */

+#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)

+#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000F00 */

+#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */

+#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)

+#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x0000F000 */

+#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */

+/**

+  * @brief   EXTI4 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */

+/**

+  * @brief   EXTI5 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */

+/**

+  * @brief   EXTI6 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */

+

+/**

+  * @brief   EXTI7 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/

+#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)

+#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */

+#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)

+#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */

+#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)

+#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000F00 */

+#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */

+#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)

+#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x0000F000 */

+#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */

+

+/**

+  * @brief   EXTI8 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */

+

+/**

+  * @brief   EXTI9 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */

+

+/**

+  * @brief   EXTI10 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */

+

+/**

+  * @brief   EXTI11 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/

+#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)

+#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x0000000F */

+#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */

+#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)

+#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x000000F0 */

+#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */

+#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)

+#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000F00 */

+#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */

+#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)

+#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x0000F000 */

+#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */

+/**

+  * @brief   EXTI12 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */

+/**

+  * @brief   EXTI13 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */

+/**

+  * @brief   EXTI14 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */

+/**

+  * @brief   EXTI15 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */

+

+/******************  Bit definition for SYSCFG_CFGR register  ******************/

+#define SYSCFG_CFGR_CM4L_Pos            (0U)

+#define SYSCFG_CFGR_CM4L_Msk            (0x1UL << SYSCFG_CFGR_CM4L_Pos)        /*!< 0x00000001 */

+#define SYSCFG_CFGR_CM4L                SYSCFG_CFGR_CM4L_Msk                   /*!<Cortex-M4 LOCKUP (Hardfault) output enable bit */

+#define SYSCFG_CFGR_PVDL_Pos            (2U)

+#define SYSCFG_CFGR_PVDL_Msk            (0x1UL << SYSCFG_CFGR_PVDL_Pos)        /*!< 0x00000004 */

+#define SYSCFG_CFGR_PVDL                SYSCFG_CFGR_PVDL_Msk                   /*!<PVD lock enable bit */

+#define SYSCFG_CFGR_FLASHL_Pos          (3U)

+#define SYSCFG_CFGR_FLASHL_Msk          (0x1UL << SYSCFG_CFGR_FLASHL_Pos)      /*!< 0x00000008 */

+#define SYSCFG_CFGR_FLASHL              SYSCFG_CFGR_FLASHL_Msk                 /*!<FLASH double ECC error lock bit */

+#define SYSCFG_CFGR_CM7L_Pos            (6U)

+#define SYSCFG_CFGR_CM7L_Msk            (0x1UL << SYSCFG_CFGR_CM7L_Pos)        /*!< 0x00000040 */

+#define SYSCFG_CFGR_CM7L                SYSCFG_CFGR_CM7L_Msk                   /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */

+#define SYSCFG_CFGR_BKRAML_Pos          (7U)

+#define SYSCFG_CFGR_BKRAML_Msk          (0x1UL << SYSCFG_CFGR_BKRAML_Pos)      /*!< 0x00000080 */

+#define SYSCFG_CFGR_BKRAML              SYSCFG_CFGR_BKRAML_Msk                 /*!<Backup SRAM double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM4L_Pos          (9U)

+#define SYSCFG_CFGR_SRAM4L_Msk          (0x1UL << SYSCFG_CFGR_SRAM4L_Pos)      /*!< 0x00000200 */

+#define SYSCFG_CFGR_SRAM4L              SYSCFG_CFGR_SRAM4L_Msk                 /*!<SRAM4 double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM3L_Pos          (10U)

+#define SYSCFG_CFGR_SRAM3L_Msk          (0x1UL << SYSCFG_CFGR_SRAM3L_Pos)      /*!< 0x00000400 */

+#define SYSCFG_CFGR_SRAM3L              SYSCFG_CFGR_SRAM3L_Msk                 /*!<SRAM3 double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM2L_Pos          (11U)

+#define SYSCFG_CFGR_SRAM2L_Msk          (0x1UL << SYSCFG_CFGR_SRAM2L_Pos)      /*!< 0x00000800 */

+#define SYSCFG_CFGR_SRAM2L              SYSCFG_CFGR_SRAM2L_Msk                 /*!<SRAM2 double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM1L_Pos          (12U)

+#define SYSCFG_CFGR_SRAM1L_Msk          (0x1UL << SYSCFG_CFGR_SRAM1L_Pos)      /*!< 0x00001000 */

+#define SYSCFG_CFGR_SRAM1L              SYSCFG_CFGR_SRAM1L_Msk                 /*!<SRAM1 double ECC error lock bit */

+#define SYSCFG_CFGR_DTCML_Pos           (13U)

+#define SYSCFG_CFGR_DTCML_Msk           (0x1UL << SYSCFG_CFGR_DTCML_Pos)       /*!< 0x00002000 */

+#define SYSCFG_CFGR_DTCML               SYSCFG_CFGR_DTCML_Msk                  /*!<DTCM double ECC error lock bit */

+#define SYSCFG_CFGR_ITCML_Pos           (14U)

+#define SYSCFG_CFGR_ITCML_Msk           (0x1UL << SYSCFG_CFGR_ITCML_Pos)       /*!< 0x00004000 */

+#define SYSCFG_CFGR_ITCML               SYSCFG_CFGR_ITCML_Msk                  /*!<ITCM double ECC error lock bit */

+#define SYSCFG_CFGR_AXISRAML_Pos        (15U)

+#define SYSCFG_CFGR_AXISRAML_Msk        (0x1UL << SYSCFG_CFGR_AXISRAML_Pos)    /*!< 0x00008000 */

+#define SYSCFG_CFGR_AXISRAML            SYSCFG_CFGR_AXISRAML_Msk               /*!<AXISRAM double ECC error lock bit */

+

+/******************  Bit definition for SYSCFG_CCCSR register  ******************/

+#define SYSCFG_CCCSR_EN_Pos             (0U)

+#define SYSCFG_CCCSR_EN_Msk             (0x1UL << SYSCFG_CCCSR_EN_Pos)         /*!< 0x00000001 */

+#define SYSCFG_CCCSR_EN                 SYSCFG_CCCSR_EN_Msk                    /*!< I/O compensation cell enable */

+#define SYSCFG_CCCSR_CS_Pos             (1U)

+#define SYSCFG_CCCSR_CS_Msk             (0x1UL << SYSCFG_CCCSR_CS_Pos)         /*!< 0x00000002 */

+#define SYSCFG_CCCSR_CS                 SYSCFG_CCCSR_CS_Msk                    /*!< I/O compensation cell code selection */

+#define SYSCFG_CCCSR_READY_Pos          (8U)

+#define SYSCFG_CCCSR_READY_Msk          (0x1UL << SYSCFG_CCCSR_READY_Pos)      /*!< 0x00000100 */

+#define SYSCFG_CCCSR_READY              SYSCFG_CCCSR_READY_Msk                 /*!< I/O compensation cell ready flag */

+#define SYSCFG_CCCSR_HSLV_Pos           (16U)

+#define SYSCFG_CCCSR_HSLV_Msk           (0x1UL << SYSCFG_CCCSR_HSLV_Pos)       /*!< 0x00010000 */

+#define SYSCFG_CCCSR_HSLV               SYSCFG_CCCSR_HSLV_Msk                  /*!< High-speed at low-voltage */

+

+/******************  Bit definition for SYSCFG_CCVR register  *******************/

+#define SYSCFG_CCVR_NCV_Pos             (0U)

+#define SYSCFG_CCVR_NCV_Msk             (0xFUL << SYSCFG_CCVR_NCV_Pos)         /*!< 0x0000000F */

+#define SYSCFG_CCVR_NCV                 SYSCFG_CCVR_NCV_Msk                    /*!< NMOS compensation value */

+#define SYSCFG_CCVR_PCV_Pos             (4U)

+#define SYSCFG_CCVR_PCV_Msk             (0xFUL << SYSCFG_CCVR_PCV_Pos)         /*!< 0x000000F0 */

+#define SYSCFG_CCVR_PCV                 SYSCFG_CCVR_PCV_Msk                    /*!< PMOS compensation value */

+

+/******************  Bit definition for SYSCFG_CCCR register  *******************/

+#define SYSCFG_CCCR_NCC_Pos             (0U)

+#define SYSCFG_CCCR_NCC_Msk             (0xFUL << SYSCFG_CCCR_NCC_Pos)         /*!< 0x0000000F */

+#define SYSCFG_CCCR_NCC                 SYSCFG_CCCR_NCC_Msk                    /*!< NMOS compensation code */

+#define SYSCFG_CCCR_PCC_Pos             (4U)

+#define SYSCFG_CCCR_PCC_Msk             (0xFUL << SYSCFG_CCCR_PCC_Pos)         /*!< 0x000000F0 */

+#define SYSCFG_CCCR_PCC                 SYSCFG_CCCR_PCC_Msk                    /*!< PMOS compensation code */

+/******************  Bit definition for SYSCFG_PWRCR register  *******************/

+#define SYSCFG_PWRCR_ODEN_Pos           (0U)

+#define SYSCFG_PWRCR_ODEN_Msk           (0x1UL << SYSCFG_PWRCR_ODEN_Pos)         /*!< 0x00000001 */

+#define SYSCFG_PWRCR_ODEN               SYSCFG_PWRCR_ODEN_Msk                    /*!< PWR overdrive enable */

+

+/******************  Bit definition for SYSCFG_PKGR register  *******************/

+#define SYSCFG_PKGR_PKG_Pos             (0U)

+#define SYSCFG_PKGR_PKG_Msk             (0xFUL << SYSCFG_PKGR_PKG_Pos)         /*!< 0x0000000F */

+#define SYSCFG_PKGR_PKG                 SYSCFG_PKGR_PKG_Msk                    /*!< Package type */

+

+/******************  Bit definition for SYSCFG_UR0 register  *******************/

+#define SYSCFG_UR0_BKS_Pos              (0U)

+#define SYSCFG_UR0_BKS_Msk              (0x1UL << SYSCFG_UR0_BKS_Pos)          /*!< 0x00000001 */

+#define SYSCFG_UR0_BKS                  SYSCFG_UR0_BKS_Msk                     /*!< Bank Swap */

+#define SYSCFG_UR0_RDP_Pos              (16U)

+#define SYSCFG_UR0_RDP_Msk              (0xFFUL << SYSCFG_UR0_RDP_Pos)         /*!< 0x00FF0000 */

+#define SYSCFG_UR0_RDP                  SYSCFG_UR0_RDP_Msk                     /*!< Readout protection */

+

+/******************  Bit definition for SYSCFG_UR1 register  *******************/

+#define SYSCFG_UR1_BCM4_Pos             (0U)

+#define SYSCFG_UR1_BCM4_Msk             (0x1UL << SYSCFG_UR1_BCM4_Pos)         /*!< 0x00000001 */

+#define SYSCFG_UR1_BCM4                 SYSCFG_UR1_BCM4_Msk                    /*!< Boot Cortex-M4 */

+#define SYSCFG_UR1_BCM7_Pos             (16U)

+#define SYSCFG_UR1_BCM7_Msk             (0x1UL << SYSCFG_UR1_BCM7_Pos)         /*!< 0x00010000 */

+#define SYSCFG_UR1_BCM7                 SYSCFG_UR1_BCM7_Msk                    /*!< Boot Cortex-M7 */

+/******************  Bit definition for SYSCFG_UR2 register  *******************/

+#define SYSCFG_UR2_BORH_Pos             (0U)

+#define SYSCFG_UR2_BORH_Msk             (0x3UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000003 */

+#define SYSCFG_UR2_BORH                 SYSCFG_UR2_BORH_Msk                    /*!< Brown Out Reset High level */

+#define SYSCFG_UR2_BORH_0               (0x1UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000001 */

+#define SYSCFG_UR2_BORH_1               (0x2UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000002 */

+#define SYSCFG_UR2_BCM7_ADD0_Pos        (16U)

+#define SYSCFG_UR2_BCM7_ADD0_Msk        (0xFFFFUL << SYSCFG_UR2_BCM7_ADD0_Pos) /*!< 0xFFFF0000 */

+#define SYSCFG_UR2_BCM7_ADD0            SYSCFG_UR2_BCM7_ADD0_Msk               /*!< Boot Cortex-M7 Address 0 */

+/******************  Bit definition for SYSCFG_UR3 register  *******************/

+#define SYSCFG_UR3_BCM7_ADD1_Pos        (0U)

+#define SYSCFG_UR3_BCM7_ADD1_Msk        (0xFFFFUL << SYSCFG_UR3_BCM7_ADD1_Pos) /*!< 0x0000FFFF */

+#define SYSCFG_UR3_BCM7_ADD1            SYSCFG_UR3_BCM7_ADD1_Msk               /*!< Boot Cortex-M7 Address 1 */

+

+#define SYSCFG_UR3_BCM4_ADD0_Pos        (16U)

+#define SYSCFG_UR3_BCM4_ADD0_Msk        (0xFFFFUL << SYSCFG_UR3_BCM4_ADD0_Pos) /*!< 0xFFFF0000 */

+#define SYSCFG_UR3_BCM4_ADD0            SYSCFG_UR3_BCM4_ADD0_Msk               /*!< Boot Cortex-M4 Address 0 */

+

+/******************  Bit definition for SYSCFG_UR4 register  *******************/

+

+#define SYSCFG_UR4_BCM4_ADD1_Pos        (0U)

+#define SYSCFG_UR4_BCM4_ADD1_Msk        (0xFFFFUL << SYSCFG_UR4_BCM4_ADD1_Pos) /*!< 0x0000FFFF */

+#define SYSCFG_UR4_BCM4_ADD1            SYSCFG_UR4_BCM4_ADD1_Msk               /*!< Boot Cortex-M4 Address 1 */

+

+#define SYSCFG_UR4_MEPAD_BANK1_Pos      (16U)

+#define SYSCFG_UR4_MEPAD_BANK1_Msk      (0x1UL << SYSCFG_UR4_MEPAD_BANK1_Pos)  /*!< 0x00010000 */

+#define SYSCFG_UR4_MEPAD_BANK1          SYSCFG_UR4_MEPAD_BANK1_Msk             /*!< Mass Erase Protected Area Disabled for bank 1 */

+

+/******************  Bit definition for SYSCFG_UR5 register  *******************/

+#define SYSCFG_UR5_MESAD_BANK1_Pos      (0U)

+#define SYSCFG_UR5_MESAD_BANK1_Msk      (0x1UL << SYSCFG_UR5_MESAD_BANK1_Pos)  /*!< 0x00000001 */

+#define SYSCFG_UR5_MESAD_BANK1          SYSCFG_UR5_MESAD_BANK1_Msk             /*!< Mass erase secured area disabled for bank 1 */

+#define SYSCFG_UR5_WRPN_BANK1_Pos       (16U)

+#define SYSCFG_UR5_WRPN_BANK1_Msk       (0xFFUL << SYSCFG_UR5_WRPN_BANK1_Pos)  /*!< 0x00FF0000 */

+#define SYSCFG_UR5_WRPN_BANK1           SYSCFG_UR5_WRPN_BANK1_Msk              /*!< Write protection for flash bank 1 */

+

+/******************  Bit definition for SYSCFG_UR6 register  *******************/

+#define SYSCFG_UR6_PABEG_BANK1_Pos      (0U)

+#define SYSCFG_UR6_PABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PABEG_BANK1_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR6_PABEG_BANK1          SYSCFG_UR6_PABEG_BANK1_Msk             /*!< Protected area start address for bank 1 */

+#define SYSCFG_UR6_PAEND_BANK1_Pos      (16U)

+#define SYSCFG_UR6_PAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PAEND_BANK1_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR6_PAEND_BANK1          SYSCFG_UR6_PAEND_BANK1_Msk             /*!< Protected area end address for bank 1 */

+

+/******************  Bit definition for SYSCFG_UR7 register  *******************/

+#define SYSCFG_UR7_SABEG_BANK1_Pos      (0U)

+#define SYSCFG_UR7_SABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SABEG_BANK1_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR7_SABEG_BANK1          SYSCFG_UR7_SABEG_BANK1_Msk             /*!< Secured area start address for bank 1 */

+#define SYSCFG_UR7_SAEND_BANK1_Pos      (16U)

+#define SYSCFG_UR7_SAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SAEND_BANK1_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR7_SAEND_BANK1          SYSCFG_UR7_SAEND_BANK1_Msk             /*!< Secured area end address for bank 1 */

+

+/******************  Bit definition for SYSCFG_UR8 register  *******************/

+#define SYSCFG_UR8_MEPAD_BANK2_Pos      (0U)

+#define SYSCFG_UR8_MEPAD_BANK2_Msk      (0x1UL << SYSCFG_UR8_MEPAD_BANK2_Pos)  /*!< 0x00000001 */

+#define SYSCFG_UR8_MEPAD_BANK2          SYSCFG_UR8_MEPAD_BANK2_Msk             /*!< Mass erase Protected area disabled for bank 2 */

+#define SYSCFG_UR8_MESAD_BANK2_Pos      (16U)

+#define SYSCFG_UR8_MESAD_BANK2_Msk      (0x1UL << SYSCFG_UR8_MESAD_BANK2_Pos)  /*!< 0x00010000 */

+#define SYSCFG_UR8_MESAD_BANK2          SYSCFG_UR8_MESAD_BANK2_Msk             /*!< Mass Erase Secured Area Disabled for bank 2 */

+

+/******************  Bit definition for SYSCFG_UR9 register  *******************/

+#define SYSCFG_UR9_WRPN_BANK2_Pos       (0U)

+#define SYSCFG_UR9_WRPN_BANK2_Msk       (0xFFUL << SYSCFG_UR9_WRPN_BANK2_Pos)  /*!< 0x000000FF */

+#define SYSCFG_UR9_WRPN_BANK2           SYSCFG_UR9_WRPN_BANK2_Msk              /*!< Write protection for flash bank 2 */

+#define SYSCFG_UR9_PABEG_BANK2_Pos      (16U)

+#define SYSCFG_UR9_PABEG_BANK2_Msk      (0xFFFUL << SYSCFG_UR9_PABEG_BANK2_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR9_PABEG_BANK2          SYSCFG_UR9_PABEG_BANK2_Msk             /*!< Protected area start address for bank 2 */

+

+/******************  Bit definition for SYSCFG_UR10 register  *******************/

+#define SYSCFG_UR10_PAEND_BANK2_Pos     (0U)

+#define SYSCFG_UR10_PAEND_BANK2_Msk     (0xFFFUL << SYSCFG_UR10_PAEND_BANK2_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR10_PAEND_BANK2         SYSCFG_UR10_PAEND_BANK2_Msk            /*!< Protected area end address for bank 2 */

+#define SYSCFG_UR10_SABEG_BANK2_Pos     (16U)

+#define SYSCFG_UR10_SABEG_BANK2_Msk     (0xFFFUL << SYSCFG_UR10_SABEG_BANK2_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR10_SABEG_BANK2         SYSCFG_UR10_SABEG_BANK2_Msk            /*!< Secured area start address for bank 2 */

+

+/******************  Bit definition for SYSCFG_UR11 register  *******************/

+#define SYSCFG_UR11_SAEND_BANK2_Pos     (0U)

+#define SYSCFG_UR11_SAEND_BANK2_Msk     (0xFFFUL << SYSCFG_UR11_SAEND_BANK2_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR11_SAEND_BANK2         SYSCFG_UR11_SAEND_BANK2_Msk            /*!< Secured area end address for bank 2 */

+#define SYSCFG_UR11_IWDG1M_Pos          (16U)

+#define SYSCFG_UR11_IWDG1M_Msk          (0x1UL << SYSCFG_UR11_IWDG1M_Pos)      /*!< 0x00010000 */

+#define SYSCFG_UR11_IWDG1M              SYSCFG_UR11_IWDG1M_Msk                 /*!< Independent Watchdog 1 mode (SW or HW) */

+

+/******************  Bit definition for SYSCFG_UR12 register  *******************/

+#define SYSCFG_UR12_IWDG2M_Pos          (0U)

+#define SYSCFG_UR12_IWDG2M_Msk          (0x1UL << SYSCFG_UR12_IWDG2M_Pos)      /*!< 0x00000001 */

+#define SYSCFG_UR12_IWDG2M              SYSCFG_UR12_IWDG2M_Msk                 /*!< Independent Watchdog 2 mode (SW or HW) */

+

+#define SYSCFG_UR12_SECURE_Pos          (16U)

+#define SYSCFG_UR12_SECURE_Msk          (0x1UL << SYSCFG_UR12_SECURE_Pos)      /*!< 0x00010000 */

+#define SYSCFG_UR12_SECURE              SYSCFG_UR12_SECURE_Msk                 /*!< Secure mode status */

+

+/******************  Bit definition for SYSCFG_UR13 register  *******************/

+#define SYSCFG_UR13_SDRS_Pos            (0U)

+#define SYSCFG_UR13_SDRS_Msk            (0x3UL << SYSCFG_UR13_SDRS_Pos)        /*!< 0x00000003 */

+#define SYSCFG_UR13_SDRS                SYSCFG_UR13_SDRS_Msk                   /*!< Secured DTCM RAM Size */

+#define SYSCFG_UR13_D1SBRST_Pos         (16U)

+#define SYSCFG_UR13_D1SBRST_Msk         (0x1UL << SYSCFG_UR13_D1SBRST_Pos)     /*!< 0x00010000 */

+#define SYSCFG_UR13_D1SBRST             SYSCFG_UR13_D1SBRST_Msk                /*!< D1 Standby reset */

+

+/******************  Bit definition for SYSCFG_UR14 register  *******************/

+#define SYSCFG_UR14_D1STPRST_Pos        (0U)

+#define SYSCFG_UR14_D1STPRST_Msk        (0x1UL << SYSCFG_UR14_D1STPRST_Pos)    /*!< 0x00000001 */

+#define SYSCFG_UR14_D1STPRST            SYSCFG_UR14_D1STPRST_Msk               /*!< D1 Stop Reset */

+#define SYSCFG_UR14_D2SBRST_Pos         (16U)

+#define SYSCFG_UR14_D2SBRST_Msk         (0x1UL << SYSCFG_UR14_D2SBRST_Pos)     /*!< 0x00010000 */

+#define SYSCFG_UR14_D2SBRST             SYSCFG_UR14_D2SBRST_Msk                /*!< D2 Standby Reset */

+

+/******************  Bit definition for SYSCFG_UR15 register  *******************/

+#define SYSCFG_UR15_D2STPRST_Pos        (0U)

+#define SYSCFG_UR15_D2STPRST_Msk        (0x1UL << SYSCFG_UR15_D2STPRST_Pos)    /*!< 0x00000001 */

+#define SYSCFG_UR15_D2STPRST            SYSCFG_UR15_D2STPRST_Msk               /*!< D2 Stop Reset */

+#define SYSCFG_UR15_FZIWDGSTB_Pos       (16U)

+#define SYSCFG_UR15_FZIWDGSTB_Msk       (0x1UL << SYSCFG_UR15_FZIWDGSTB_Pos)   /*!< 0x00010000 */

+#define SYSCFG_UR15_FZIWDGSTB           SYSCFG_UR15_FZIWDGSTB_Msk              /*!< Freeze independent watchdogs in Standby mode */

+

+/******************  Bit definition for SYSCFG_UR16 register  *******************/

+#define SYSCFG_UR16_FZIWDGSTP_Pos       (0U)

+#define SYSCFG_UR16_FZIWDGSTP_Msk       (0x1UL << SYSCFG_UR16_FZIWDGSTP_Pos)   /*!< 0x00000001 */

+#define SYSCFG_UR16_FZIWDGSTP           SYSCFG_UR16_FZIWDGSTP_Msk              /*!< Freeze independent watchdogs in Stop mode */

+#define SYSCFG_UR16_PKP_Pos             (16U)

+#define SYSCFG_UR16_PKP_Msk             (0x1UL << SYSCFG_UR16_PKP_Pos)         /*!< 0x00010000 */

+#define SYSCFG_UR16_PKP                 SYSCFG_UR16_PKP_Msk                    /*!< Private key programmed */

+

+/******************  Bit definition for SYSCFG_UR17 register  *******************/

+#define SYSCFG_UR17_IOHSLV_Pos          (0U)

+#define SYSCFG_UR17_IOHSLV_Msk          (0x1UL << SYSCFG_UR17_IOHSLV_Pos)      /*!< 0x00000001 */

+#define SYSCFG_UR17_IOHSLV              SYSCFG_UR17_IOHSLV_Msk                 /*!< I/O high speed / low voltage */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    TIM                                     */

+/*                                                                            */

+/******************************************************************************/

+#define TIM_BREAK_INPUT_SUPPORT             /*!<TIM Break input feature */

+

+/*******************  Bit definition for TIM_CR1 register  ********************/

+#define TIM_CR1_CEN_Pos           (0U)

+#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */

+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */

+#define TIM_CR1_UDIS_Pos          (1U)

+#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */

+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */

+#define TIM_CR1_URS_Pos           (2U)

+#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */

+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */

+#define TIM_CR1_OPM_Pos           (3U)

+#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */

+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */

+#define TIM_CR1_DIR_Pos           (4U)

+#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */

+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */

+

+#define TIM_CR1_CMS_Pos           (5U)

+#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */

+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */

+#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */

+#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */

+

+#define TIM_CR1_ARPE_Pos          (7U)

+#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */

+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */

+

+#define TIM_CR1_CKD_Pos           (8U)

+#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */

+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */

+#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */

+#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */

+

+#define TIM_CR1_UIFREMAP_Pos      (11U)

+#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */

+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */

+

+/*******************  Bit definition for TIM_CR2 register  ********************/

+#define TIM_CR2_CCPC_Pos          (0U)

+#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */

+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */

+#define TIM_CR2_CCUS_Pos          (2U)

+#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */

+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */

+#define TIM_CR2_CCDS_Pos          (3U)

+#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */

+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */

+

+#define TIM_CR2_MMS_Pos           (4U)

+#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */

+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */

+#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */

+#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */

+#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */

+

+#define TIM_CR2_TI1S_Pos          (7U)

+#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */

+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */

+#define TIM_CR2_OIS1_Pos          (8U)

+#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */

+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */

+#define TIM_CR2_OIS1N_Pos         (9U)

+#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */

+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */

+#define TIM_CR2_OIS2_Pos          (10U)

+#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */

+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */

+#define TIM_CR2_OIS2N_Pos         (11U)

+#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */

+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */

+#define TIM_CR2_OIS3_Pos          (12U)

+#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */

+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */

+#define TIM_CR2_OIS3N_Pos         (13U)

+#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */

+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */

+#define TIM_CR2_OIS4_Pos          (14U)

+#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */

+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */

+#define TIM_CR2_OIS5_Pos          (16U)

+#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */

+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */

+#define TIM_CR2_OIS6_Pos          (17U)

+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */

+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */

+

+#define TIM_CR2_MMS2_Pos          (20U)

+#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */

+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */

+#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */

+#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */

+#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */

+#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */

+

+/*******************  Bit definition for TIM_SMCR register  *******************/

+#define TIM_SMCR_SMS_Pos          (0U)

+#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */

+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */

+#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */

+#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */

+#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */

+#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */

+

+#define TIM_SMCR_TS_Pos           (4U)

+#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */

+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[4:0] bits (Trigger selection) */

+#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)                /*!< 0x00000010 */

+#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)                /*!< 0x00000020 */

+#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)                /*!< 0x00000040 */

+#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)                /*!< 0x00100000 */

+#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)                /*!< 0x00200000 */

+

+#define TIM_SMCR_MSM_Pos          (7U)

+#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */

+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */

+

+#define TIM_SMCR_ETF_Pos          (8U)

+#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */

+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */

+#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */

+#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */

+#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */

+#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */

+

+#define TIM_SMCR_ETPS_Pos         (12U)

+#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */

+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */

+#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */

+#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */

+

+#define TIM_SMCR_ECE_Pos          (14U)

+#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */

+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */

+#define TIM_SMCR_ETP_Pos          (15U)

+#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */

+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */

+

+/*******************  Bit definition for TIM_DIER register  *******************/

+#define TIM_DIER_UIE_Pos          (0U)

+#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */

+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */

+#define TIM_DIER_CC1IE_Pos        (1U)

+#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */

+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */

+#define TIM_DIER_CC2IE_Pos        (2U)

+#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */

+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */

+#define TIM_DIER_CC3IE_Pos        (3U)

+#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */

+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */

+#define TIM_DIER_CC4IE_Pos        (4U)

+#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */

+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */

+#define TIM_DIER_COMIE_Pos        (5U)

+#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */

+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */

+#define TIM_DIER_TIE_Pos          (6U)

+#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */

+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */

+#define TIM_DIER_BIE_Pos          (7U)

+#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */

+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */

+#define TIM_DIER_UDE_Pos          (8U)

+#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */

+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */

+#define TIM_DIER_CC1DE_Pos        (9U)

+#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */

+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */

+#define TIM_DIER_CC2DE_Pos        (10U)

+#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */

+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */

+#define TIM_DIER_CC3DE_Pos        (11U)

+#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */

+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */

+#define TIM_DIER_CC4DE_Pos        (12U)

+#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */

+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */

+#define TIM_DIER_COMDE_Pos        (13U)

+#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */

+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */

+#define TIM_DIER_TDE_Pos          (14U)

+#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */

+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */

+

+/********************  Bit definition for TIM_SR register  ********************/

+#define TIM_SR_UIF_Pos            (0U)

+#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */

+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */

+#define TIM_SR_CC1IF_Pos          (1U)

+#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */

+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */

+#define TIM_SR_CC2IF_Pos          (2U)

+#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */

+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */

+#define TIM_SR_CC3IF_Pos          (3U)

+#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */

+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */

+#define TIM_SR_CC4IF_Pos          (4U)

+#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */

+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */

+#define TIM_SR_COMIF_Pos          (5U)

+#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */

+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */

+#define TIM_SR_TIF_Pos            (6U)

+#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */

+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */

+#define TIM_SR_BIF_Pos            (7U)

+#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */

+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */

+#define TIM_SR_B2IF_Pos           (8U)

+#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */

+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break2 interrupt Flag */

+#define TIM_SR_CC1OF_Pos          (9U)

+#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */

+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */

+#define TIM_SR_CC2OF_Pos          (10U)

+#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */

+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */

+#define TIM_SR_CC3OF_Pos          (11U)

+#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */

+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */

+#define TIM_SR_CC4OF_Pos          (12U)

+#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */

+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */

+#define TIM_SR_CC5IF_Pos          (16U)

+#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */

+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */

+#define TIM_SR_CC6IF_Pos          (17U)

+#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */

+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */

+#define TIM_SR_SBIF_Pos           (13U)

+#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */

+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!< System Break Flag */

+

+/*******************  Bit definition for TIM_EGR register  ********************/

+#define TIM_EGR_UG_Pos            (0U)

+#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */

+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */

+#define TIM_EGR_CC1G_Pos          (1U)

+#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */

+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */

+#define TIM_EGR_CC2G_Pos          (2U)

+#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */

+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */

+#define TIM_EGR_CC3G_Pos          (3U)

+#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */

+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */

+#define TIM_EGR_CC4G_Pos          (4U)

+#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */

+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */

+#define TIM_EGR_COMG_Pos          (5U)

+#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */

+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */

+#define TIM_EGR_TG_Pos            (6U)

+#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */

+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */

+#define TIM_EGR_BG_Pos            (7U)

+#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */

+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */

+#define TIM_EGR_B2G_Pos           (8U)

+#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */

+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break Generation */

+

+

+/******************  Bit definition for TIM_CCMR1 register  *******************/

+#define TIM_CCMR1_CC1S_Pos        (0U)

+#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */

+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */

+#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */

+#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */

+

+#define TIM_CCMR1_OC1FE_Pos       (2U)

+#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */

+#define TIM_CCMR1_OC1PE_Pos       (3U)

+#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */

+

+#define TIM_CCMR1_OC1M_Pos        (4U)

+#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */

+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */

+#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */

+#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */

+#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */

+#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR1_OC1CE_Pos       (7U)

+#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */

+

+#define TIM_CCMR1_CC2S_Pos        (8U)

+#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */

+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */

+#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */

+#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */

+

+#define TIM_CCMR1_OC2FE_Pos       (10U)

+#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */

+#define TIM_CCMR1_OC2PE_Pos       (11U)

+#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */

+

+#define TIM_CCMR1_OC2M_Pos        (12U)

+#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */

+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */

+#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */

+#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */

+#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */

+#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */

+

+#define TIM_CCMR1_OC2CE_Pos       (15U)

+#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */

+

+/*----------------------------------------------------------------------------*/

+

+#define TIM_CCMR1_IC1PSC_Pos      (2U)

+#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */

+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */

+#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */

+

+#define TIM_CCMR1_IC1F_Pos        (4U)

+#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */

+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */

+#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */

+

+#define TIM_CCMR1_IC2PSC_Pos      (10U)

+#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */

+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */

+#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */

+

+#define TIM_CCMR1_IC2F_Pos        (12U)

+#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */

+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */

+#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */

+

+/******************  Bit definition for TIM_CCMR2 register  *******************/

+#define TIM_CCMR2_CC3S_Pos        (0U)

+#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */

+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */

+#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */

+#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */

+

+#define TIM_CCMR2_OC3FE_Pos       (2U)

+#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */

+#define TIM_CCMR2_OC3PE_Pos       (3U)

+#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */

+

+#define TIM_CCMR2_OC3M_Pos        (4U)

+#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */

+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */

+#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR2_OC3CE_Pos       (7U)

+#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */

+

+#define TIM_CCMR2_CC4S_Pos        (8U)

+#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */

+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */

+#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */

+#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */

+

+#define TIM_CCMR2_OC4FE_Pos       (10U)

+#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */

+#define TIM_CCMR2_OC4PE_Pos       (11U)

+#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */

+

+#define TIM_CCMR2_OC4M_Pos        (12U)

+#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */

+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */

+#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */

+

+#define TIM_CCMR2_OC4CE_Pos       (15U)

+#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */

+

+/*----------------------------------------------------------------------------*/

+

+#define TIM_CCMR2_IC3PSC_Pos      (2U)

+#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */

+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */

+#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */

+

+#define TIM_CCMR2_IC3F_Pos        (4U)

+#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */

+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */

+#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */

+

+#define TIM_CCMR2_IC4PSC_Pos      (10U)

+#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */

+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */

+#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */

+

+#define TIM_CCMR2_IC4F_Pos        (12U)

+#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */

+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */

+#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */

+

+/*******************  Bit definition for TIM_CCER register  *******************/

+#define TIM_CCER_CC1E_Pos         (0U)

+#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */

+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */

+#define TIM_CCER_CC1P_Pos         (1U)

+#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */

+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */

+#define TIM_CCER_CC1NE_Pos        (2U)

+#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */

+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */

+#define TIM_CCER_CC1NP_Pos        (3U)

+#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */

+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */

+#define TIM_CCER_CC2E_Pos         (4U)

+#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */

+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */

+#define TIM_CCER_CC2P_Pos         (5U)

+#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */

+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */

+#define TIM_CCER_CC2NE_Pos        (6U)

+#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */

+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */

+#define TIM_CCER_CC2NP_Pos        (7U)

+#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */

+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */

+#define TIM_CCER_CC3E_Pos         (8U)

+#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */

+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */

+#define TIM_CCER_CC3P_Pos         (9U)

+#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */

+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */

+#define TIM_CCER_CC3NE_Pos        (10U)

+#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */

+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */

+#define TIM_CCER_CC3NP_Pos        (11U)

+#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */

+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */

+#define TIM_CCER_CC4E_Pos         (12U)

+#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */

+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */

+#define TIM_CCER_CC4P_Pos         (13U)

+#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */

+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */

+#define TIM_CCER_CC4NP_Pos        (15U)

+#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */

+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */

+#define TIM_CCER_CC5E_Pos         (16U)

+#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */

+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */

+#define TIM_CCER_CC5P_Pos         (17U)

+#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */

+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */

+#define TIM_CCER_CC6E_Pos         (20U)

+#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */

+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */

+#define TIM_CCER_CC6P_Pos         (21U)

+#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */

+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */

+/*******************  Bit definition for TIM_CNT register  ********************/

+#define TIM_CNT_CNT_Pos           (0U)

+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */

+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */

+#define TIM_CNT_UIFCPY_Pos        (31U)

+#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */

+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy */

+/*******************  Bit definition for TIM_PSC register  ********************/

+#define TIM_PSC_PSC_Pos           (0U)

+#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */

+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */

+

+/*******************  Bit definition for TIM_ARR register  ********************/

+#define TIM_ARR_ARR_Pos           (0U)

+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */

+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */

+

+/*******************  Bit definition for TIM_RCR register  ********************/

+#define TIM_RCR_REP_Pos           (0U)

+#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                  /*!< 0x000000FF */

+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */

+

+/*******************  Bit definition for TIM_CCR1 register  *******************/

+#define TIM_CCR1_CCR1_Pos         (0U)

+#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */

+

+/*******************  Bit definition for TIM_CCR2 register  *******************/

+#define TIM_CCR2_CCR2_Pos         (0U)

+#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */

+

+/*******************  Bit definition for TIM_CCR3 register  *******************/

+#define TIM_CCR3_CCR3_Pos         (0U)

+#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */

+

+/*******************  Bit definition for TIM_CCR4 register  *******************/

+#define TIM_CCR4_CCR4_Pos         (0U)

+#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */

+

+/*******************  Bit definition for TIM_CCR5 register  *******************/

+#define TIM_CCR5_CCR5_Pos         (0U)

+#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */

+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */

+#define TIM_CCR5_GC5C1_Pos        (29U)

+#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */

+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */

+#define TIM_CCR5_GC5C2_Pos        (30U)

+#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */

+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */

+#define TIM_CCR5_GC5C3_Pos        (31U)

+#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */

+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */

+

+/*******************  Bit definition for TIM_CCR6 register  *******************/

+#define TIM_CCR6_CCR6_Pos         (0U)

+#define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */

+

+/*******************  Bit definition for TIM_BDTR register  *******************/

+#define TIM_BDTR_DTG_Pos          (0U)

+#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */

+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */

+#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */

+#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */

+#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */

+#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */

+#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */

+#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */

+#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */

+#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */

+

+#define TIM_BDTR_LOCK_Pos         (8U)

+#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */

+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */

+#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */

+#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */

+

+#define TIM_BDTR_OSSI_Pos         (10U)

+#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */

+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */

+#define TIM_BDTR_OSSR_Pos         (11U)

+#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */

+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */

+#define TIM_BDTR_BKE_Pos          (12U)

+#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */

+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break1 */

+#define TIM_BDTR_BKP_Pos          (13U)

+#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */

+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break1 */

+#define TIM_BDTR_AOE_Pos          (14U)

+#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */

+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */

+#define TIM_BDTR_MOE_Pos          (15U)

+#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */

+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */

+

+#define TIM_BDTR_BKF_Pos          (16U)

+#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */

+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break1 */

+#define TIM_BDTR_BK2F_Pos         (20U)

+#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */

+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break2 */

+

+#define TIM_BDTR_BK2E_Pos         (24U)

+#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */

+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break2 */

+#define TIM_BDTR_BK2P_Pos         (25U)

+#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */

+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */

+

+/*******************  Bit definition for TIM_DCR register  ********************/

+#define TIM_DCR_DBA_Pos           (0U)

+#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */

+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */

+#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */

+#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */

+#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */

+#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */

+#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */

+

+#define TIM_DCR_DBL_Pos           (8U)

+#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */

+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */

+#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */

+#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */

+#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */

+#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */

+#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */

+

+/*******************  Bit definition for TIM_DMAR register  *******************/

+#define TIM_DMAR_DMAB_Pos         (0U)

+#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */

+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */

+

+/******************  Bit definition for TIM_CCMR3 register  *******************/

+#define TIM_CCMR3_OC5FE_Pos       (2U)

+#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */

+#define TIM_CCMR3_OC5PE_Pos       (3U)

+#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */

+

+#define TIM_CCMR3_OC5M_Pos        (4U)

+#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */

+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */

+#define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR3_OC5CE_Pos       (7U)

+#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */

+

+#define TIM_CCMR3_OC6FE_Pos       (10U)

+#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 4 Fast enable */

+#define TIM_CCMR3_OC6PE_Pos       (11U)

+#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */

+

+#define TIM_CCMR3_OC6M_Pos        (12U)

+#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */

+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */

+#define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */

+

+#define TIM_CCMR3_OC6CE_Pos       (15U)

+#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 4 Clear Enable */

+/*******************  Bit definition for TIM1_AF1 register  *********************/

+#define TIM1_AF1_BKINE_Pos        (0U)

+#define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */

+#define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */

+#define TIM1_AF1_BKCMP1E_Pos      (1U)

+#define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */

+#define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM1_AF1_BKCMP2E_Pos      (2U)

+#define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */

+#define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit */

+#define TIM1_AF1_BKDF1BK0E_Pos    (8U)

+#define TIM1_AF1_BKDF1BK0E_Msk    (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)            /*!< 0x00000100 */

+#define TIM1_AF1_BKDF1BK0E        TIM1_AF1_BKDF1BK0E_Msk                       /*!<BKDF1BK0E Break input DFSDM Break 0 */

+#define TIM1_AF1_BKINP_Pos        (9U)

+#define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */

+#define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */

+#define TIM1_AF1_BKCMP1P_Pos      (10U)

+#define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */

+#define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM1_AF1_BKCMP2P_Pos      (11U)

+#define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */

+#define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */

+

+#define TIM1_AF1_ETRSEL_Pos       (14U)

+#define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */

+#define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */

+#define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00004000 */

+#define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00008000 */

+#define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00010000 */

+#define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM1_AF2 register  *********************/

+#define TIM1_AF2_BK2INE_Pos       (0U)

+#define TIM1_AF2_BK2INE_Msk       (0x1UL << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */

+#define TIM1_AF2_BK2INE           TIM1_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */

+#define TIM1_AF2_BK2CMP1E_Pos     (1U)

+#define TIM1_AF2_BK2CMP1E_Msk     (0x1UL << TIM1_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */

+#define TIM1_AF2_BK2CMP1E         TIM1_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */

+#define TIM1_AF2_BK2CMP2E_Pos     (2U)

+#define TIM1_AF2_BK2CMP2E_Msk     (0x1UL << TIM1_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */

+#define TIM1_AF2_BK2CMP2E         TIM1_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */

+#define TIM1_AF2_BK2DFBK1E_Pos    (8U)

+#define TIM1_AF2_BK2DFBK1E_Msk    (0x1UL << TIM1_AF2_BK2DFBK1E_Pos)            /*!< 0x00000100 */

+#define TIM1_AF2_BK2DFBK1E        TIM1_AF2_BK2DFBK1E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 1 */

+#define TIM1_AF2_BK2INP_Pos       (9U)

+#define TIM1_AF2_BK2INP_Msk       (0x1UL << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */

+#define TIM1_AF2_BK2INP           TIM1_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */

+#define TIM1_AF2_BK2CMP1P_Pos     (10U)

+#define TIM1_AF2_BK2CMP1P_Msk     (0x1UL << TIM1_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */

+#define TIM1_AF2_BK2CMP1P         TIM1_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */

+#define TIM1_AF2_BK2CMP2P_Pos     (11U)

+#define TIM1_AF2_BK2CMP2P_Msk     (0x1UL << TIM1_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */

+#define TIM1_AF2_BK2CMP2P         TIM1_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */

+

+/*******************  Bit definition for TIM_TISEL register  *********************/

+#define TIM_TISEL_TI1SEL_Pos      (0U)

+#define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */

+#define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/

+#define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000001 */

+#define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000002 */

+#define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000004 */

+#define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000008 */

+

+#define TIM_TISEL_TI2SEL_Pos      (8U)

+#define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */

+#define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/

+#define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000100 */

+#define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000200 */

+#define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000400 */

+#define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000800 */

+

+#define TIM_TISEL_TI3SEL_Pos      (16U)

+#define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */

+#define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/

+#define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00010000 */

+#define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00020000 */

+#define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00040000 */

+#define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00080000 */

+

+#define TIM_TISEL_TI4SEL_Pos      (24U)

+#define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */

+#define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/

+#define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x01000000 */

+#define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x02000000 */

+#define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x04000000 */

+#define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x08000000 */

+

+/*******************  Bit definition for TIM8_AF1 register  *********************/

+#define TIM8_AF1_BKINE_Pos        (0U)

+#define TIM8_AF1_BKINE_Msk        (0x1UL << TIM8_AF1_BKINE_Pos)                /*!< 0x00000001 */

+#define TIM8_AF1_BKINE            TIM8_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */

+#define TIM8_AF1_BKCMP1E_Pos      (1U)

+#define TIM8_AF1_BKCMP1E_Msk      (0x1UL << TIM8_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */

+#define TIM8_AF1_BKCMP1E          TIM8_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM8_AF1_BKCMP2E_Pos      (2U)

+#define TIM8_AF1_BKCMP2E_Msk      (0x1UL << TIM8_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */

+#define TIM8_AF1_BKCMP2E          TIM8_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM8_AF1_BKDFBK2E_Pos     (8U)

+#define TIM8_AF1_BKDFBK2E_Msk     (0x1UL << TIM8_AF1_BKDFBK2E_Pos)             /*!< 0x00000100 */

+#define TIM8_AF1_BKDFBK2E         TIM8_AF1_BKDFBK2E_Msk                        /*!<BKDFBK2E Break input DFSDM Break 2 */

+#define TIM8_AF1_BKINP_Pos        (9U)

+#define TIM8_AF1_BKINP_Msk        (0x1UL << TIM8_AF1_BKINP_Pos)                /*!< 0x00000200 */

+#define TIM8_AF1_BKINP            TIM8_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */

+#define TIM8_AF1_BKCMP1P_Pos      (10U)

+#define TIM8_AF1_BKCMP1P_Msk      (0x1UL << TIM8_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */

+#define TIM8_AF1_BKCMP1P          TIM8_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM8_AF1_BKCMP2P_Pos      (11U)

+#define TIM8_AF1_BKCMP2P_Msk      (0x1UL << TIM8_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */

+#define TIM8_AF1_BKCMP2P          TIM8_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */

+

+#define TIM8_AF1_ETRSEL_Pos       (14U)

+#define TIM8_AF1_ETRSEL_Msk       (0xFUL << TIM8_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */

+#define TIM8_AF1_ETRSEL           TIM8_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */

+#define TIM8_AF1_ETRSEL_0         (0x1UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00004000 */

+#define TIM8_AF1_ETRSEL_1         (0x2UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00008000 */

+#define TIM8_AF1_ETRSEL_2         (0x4UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00010000 */

+#define TIM8_AF1_ETRSEL_3         (0x8UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00020000 */

+/*******************  Bit definition for TIM8_AF2 register  *********************/

+#define TIM8_AF2_BK2INE_Pos       (0U)

+#define TIM8_AF2_BK2INE_Msk       (0x1UL << TIM8_AF2_BK2INE_Pos)               /*!< 0x00000001 */

+#define TIM8_AF2_BK2INE           TIM8_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */

+#define TIM8_AF2_BK2CMP1E_Pos     (1U)

+#define TIM8_AF2_BK2CMP1E_Msk     (0x1UL << TIM8_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */

+#define TIM8_AF2_BK2CMP1E         TIM8_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */

+#define TIM8_AF2_BK2CMP2E_Pos     (2U)

+#define TIM8_AF2_BK2CMP2E_Msk     (0x1UL << TIM8_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */

+#define TIM8_AF2_BK2CMP2E         TIM8_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */

+#define TIM8_AF2_BK2DFBK3E_Pos    (8U)

+#define TIM8_AF2_BK2DFBK3E_Msk    (0x1UL << TIM8_AF2_BK2DFBK3E_Pos)            /*!< 0x00000100 */

+#define TIM8_AF2_BK2DFBK3E        TIM8_AF2_BK2DFBK3E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 3 */

+#define TIM8_AF2_BK2INP_Pos       (9U)

+#define TIM8_AF2_BK2INP_Msk       (0x1UL << TIM8_AF2_BK2INP_Pos)               /*!< 0x00000200 */

+#define TIM8_AF2_BK2INP           TIM8_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */

+#define TIM8_AF2_BK2CMP1P_Pos     (10U)

+#define TIM8_AF2_BK2CMP1P_Msk     (0x1UL << TIM8_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */

+#define TIM8_AF2_BK2CMP1P         TIM8_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */

+#define TIM8_AF2_BK2CMP2P_Pos     (11U)

+#define TIM8_AF2_BK2CMP2P_Msk     (0x1UL << TIM8_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */

+#define TIM8_AF2_BK2CMP2P         TIM8_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */

+

+/*******************  Bit definition for TIM2_AF1 register  *********************/

+#define TIM2_AF1_ETRSEL_Pos      (14U)

+#define TIM2_AF1_ETRSEL_Msk      (0xFUL << TIM2_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM2_AF1_ETRSEL          TIM2_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */

+#define TIM2_AF1_ETRSEL_0        (0x1UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM2_AF1_ETRSEL_1        (0x2UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM2_AF1_ETRSEL_2        (0x4UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM2_AF1_ETRSEL_3        (0x8UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM3_AF1 register  *********************/

+#define TIM3_AF1_ETRSEL_Pos      (14U)

+#define TIM3_AF1_ETRSEL_Msk      (0xFUL << TIM3_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM3_AF1_ETRSEL          TIM3_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */

+#define TIM3_AF1_ETRSEL_0        (0x1UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM3_AF1_ETRSEL_1        (0x2UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM3_AF1_ETRSEL_2        (0x4UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM3_AF1_ETRSEL_3        (0x8UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM5_AF1 register  *********************/

+#define TIM5_AF1_ETRSEL_Pos      (14U)

+#define TIM5_AF1_ETRSEL_Msk      (0xFUL << TIM5_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM5_AF1_ETRSEL          TIM5_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */

+#define TIM5_AF1_ETRSEL_0        (0x1UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM5_AF1_ETRSEL_1        (0x2UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM5_AF1_ETRSEL_2        (0x4UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM5_AF1_ETRSEL_3        (0x8UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM15_AF1 register  *********************/

+#define TIM15_AF1_BKINE_Pos        (0U)

+#define TIM15_AF1_BKINE_Msk        (0x1UL << TIM15_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM15_AF1_BKINE            TIM15_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM15_AF1_BKCMP1E_Pos      (1U)

+#define TIM15_AF1_BKCMP1E_Msk      (0x1UL << TIM15_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM15_AF1_BKCMP1E          TIM15_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM15_AF1_BKCMP2E_Pos      (2U)

+#define TIM15_AF1_BKCMP2E_Msk      (0x1UL << TIM15_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM15_AF1_BKCMP2E          TIM15_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM15_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM15_AF1_BKDF1BK2E_Msk    (0x1UL << TIM15_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM15_AF1_BKDF1BK2E        TIM15_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[0] enable */

+#define TIM15_AF1_BKINP_Pos        (9U)

+#define TIM15_AF1_BKINP_Msk        (0x1UL << TIM15_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM15_AF1_BKINP            TIM15_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM15_AF1_BKCMP1P_Pos      (10U)

+#define TIM15_AF1_BKCMP1P_Msk      (0x1UL << TIM15_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM15_AF1_BKCMP1P          TIM15_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM15_AF1_BKCMP2P_Pos      (11U)

+#define TIM15_AF1_BKCMP2P_Msk      (0x1UL << TIM15_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM15_AF1_BKCMP2P          TIM15_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/*******************  Bit definition for TIM16_ register  *********************/

+#define TIM16_AF1_BKINE_Pos        (0U)

+#define TIM16_AF1_BKINE_Msk        (0x1UL << TIM16_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM16_AF1_BKINE            TIM16_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM16_AF1_BKCMP1E_Pos      (1U)

+#define TIM16_AF1_BKCMP1E_Msk      (0x1UL << TIM16_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM16_AF1_BKCMP1E          TIM16_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM16_AF1_BKCMP2E_Pos      (2U)

+#define TIM16_AF1_BKCMP2E_Msk      (0x1UL << TIM16_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM16_AF1_BKCMP2E          TIM16_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM16_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM16_AF1_BKDF1BK2E_Msk    (0x1UL << TIM16_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM16_AF1_BKDF1BK2E        TIM16_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[1] enable */

+#define TIM16_AF1_BKINP_Pos        (9U)

+#define TIM16_AF1_BKINP_Msk        (0x1UL << TIM16_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM16_AF1_BKINP            TIM16_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM16_AF1_BKCMP1P_Pos      (10U)

+#define TIM16_AF1_BKCMP1P_Msk      (0x1UL << TIM16_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM16_AF1_BKCMP1P          TIM16_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM16_AF1_BKCMP2P_Pos      (11U)

+#define TIM16_AF1_BKCMP2P_Msk      (0x1UL << TIM16_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM16_AF1_BKCMP2P          TIM16_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/*******************  Bit definition for TIM17_AF1 register  *********************/

+#define TIM17_AF1_BKINE_Pos        (0U)

+#define TIM17_AF1_BKINE_Msk        (0x1UL << TIM17_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM17_AF1_BKINE            TIM17_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM17_AF1_BKCMP1E_Pos      (1U)

+#define TIM17_AF1_BKCMP1E_Msk      (0x1UL << TIM17_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM17_AF1_BKCMP1E          TIM17_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM17_AF1_BKCMP2E_Pos      (2U)

+#define TIM17_AF1_BKCMP2E_Msk      (0x1UL << TIM17_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM17_AF1_BKCMP2E          TIM17_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM17_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM17_AF1_BKDF1BK2E_Msk    (0x1UL << TIM17_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM17_AF1_BKDF1BK2E        TIM17_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[2] enable */

+#define TIM17_AF1_BKINP_Pos        (9U)

+#define TIM17_AF1_BKINP_Msk        (0x1UL << TIM17_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM17_AF1_BKINP            TIM17_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM17_AF1_BKCMP1P_Pos      (10U)

+#define TIM17_AF1_BKCMP1P_Msk      (0x1UL << TIM17_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM17_AF1_BKCMP1P          TIM17_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM17_AF1_BKCMP2P_Pos      (11U)

+#define TIM17_AF1_BKCMP2P_Msk      (0x1UL << TIM17_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM17_AF1_BKCMP2P          TIM17_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Low Power Timer (LPTTIM)                           */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for LPTIM_ISR register  *******************/

+#define LPTIM_ISR_CMPM_Pos          (0U)

+#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */

+#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */

+#define LPTIM_ISR_ARRM_Pos          (1U)

+#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */

+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */

+#define LPTIM_ISR_EXTTRIG_Pos       (2U)

+#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */

+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */

+#define LPTIM_ISR_CMPOK_Pos         (3U)

+#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */

+#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */

+#define LPTIM_ISR_ARROK_Pos         (4U)

+#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */

+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */

+#define LPTIM_ISR_UP_Pos            (5U)

+#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */

+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */

+#define LPTIM_ISR_DOWN_Pos          (6U)

+#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */

+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */

+

+/******************  Bit definition for LPTIM_ICR register  *******************/

+#define LPTIM_ICR_CMPMCF_Pos        (0U)

+#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */

+#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */

+#define LPTIM_ICR_ARRMCF_Pos        (1U)

+#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */

+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */

+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)

+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */

+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */

+#define LPTIM_ICR_CMPOKCF_Pos       (3U)

+#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */

+#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */

+#define LPTIM_ICR_ARROKCF_Pos       (4U)

+#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */

+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */

+#define LPTIM_ICR_UPCF_Pos          (5U)

+#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */

+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */

+#define LPTIM_ICR_DOWNCF_Pos        (6U)

+#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */

+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */

+

+/******************  Bit definition for LPTIM_IER register ********************/

+#define LPTIM_IER_CMPMIE_Pos        (0U)

+#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */

+#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */

+#define LPTIM_IER_ARRMIE_Pos        (1U)

+#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */

+#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */

+#define LPTIM_IER_EXTTRIGIE_Pos     (2U)

+#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */

+#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */

+#define LPTIM_IER_CMPOKIE_Pos       (3U)

+#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */

+#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */

+#define LPTIM_IER_ARROKIE_Pos       (4U)

+#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */

+#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */

+#define LPTIM_IER_UPIE_Pos          (5U)

+#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */

+#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */

+#define LPTIM_IER_DOWNIE_Pos        (6U)

+#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */

+#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */

+

+/******************  Bit definition for LPTIM_CFGR register *******************/

+#define LPTIM_CFGR_CKSEL_Pos        (0U)

+#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */

+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */

+

+#define LPTIM_CFGR_CKPOL_Pos        (1U)

+#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */

+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */

+#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */

+#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */

+

+#define LPTIM_CFGR_CKFLT_Pos        (3U)

+#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */

+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */

+#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */

+#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */

+

+#define LPTIM_CFGR_TRGFLT_Pos       (6U)

+#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */

+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */

+#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */

+#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */

+

+#define LPTIM_CFGR_PRESC_Pos        (9U)

+#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */

+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */

+#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */

+#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */

+#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */

+

+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)

+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */

+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */

+#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */

+#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */

+#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */

+

+#define LPTIM_CFGR_TRIGEN_Pos       (17U)

+#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */

+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */

+#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */

+#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */

+

+#define LPTIM_CFGR_TIMOUT_Pos       (19U)

+#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */

+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */

+#define LPTIM_CFGR_WAVE_Pos         (20U)

+#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */

+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */

+#define LPTIM_CFGR_WAVPOL_Pos       (21U)

+#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */

+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */

+#define LPTIM_CFGR_PRELOAD_Pos      (22U)

+#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */

+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */

+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)

+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */

+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */

+#define LPTIM_CFGR_ENC_Pos          (24U)

+#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */

+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */

+

+/******************  Bit definition for LPTIM_CR register  ********************/

+#define LPTIM_CR_ENABLE_Pos         (0U)

+#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */

+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */

+#define LPTIM_CR_SNGSTRT_Pos        (1U)

+#define LPTIM_CR_SNGSTRT_Msk        (0x40001UL << LPTIM_CR_SNGSTRT_Pos)        /*!< 0x00080002 */

+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */

+#define LPTIM_CR_CNTSTRT_Pos        (2U)

+#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */

+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */

+#define LPTIM_CR_COUNTRST_Pos       (3U)

+#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */

+#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Timer Counter reset in synchronous mode*/

+#define LPTIM_CR_RSTARE_Pos         (4U)

+#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */

+#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Timer Counter reset after read enable (asynchronously)*/

+

+

+/******************  Bit definition for LPTIM_CMP register  *******************/

+#define LPTIM_CMP_CMP_Pos           (0U)

+#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */

+

+/******************  Bit definition for LPTIM_ARR register  *******************/

+#define LPTIM_ARR_ARR_Pos           (0U)

+#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */

+

+/******************  Bit definition for LPTIM_CNT register  *******************/

+#define LPTIM_CNT_CNT_Pos           (0U)

+#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */

+

+/******************  Bit definition for LPTIM_CFGR2 register  *****************/

+#define LPTIM_CFGR2_IN1SEL_Pos      (0U)

+#define LPTIM_CFGR2_IN1SEL_Msk      (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000003 */

+#define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< IN1SEL[1:0] bits (Remap selection) */

+#define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000001 */

+#define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000002 */

+#define LPTIM_CFGR2_IN2SEL_Pos      (4U)

+#define LPTIM_CFGR2_IN2SEL_Msk      (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000030 */

+#define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< IN2SEL[5:4] bits (Remap selection) */

+#define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000010 */

+#define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000020 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      Analog Comparators (COMP)                             */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for COMP_SR register  ********************/

+#define COMP_SR_C1VAL_Pos            (0U)

+#define COMP_SR_C1VAL_Msk            (0x1UL << COMP_SR_C1VAL_Pos)              /*!< 0x00000001 */

+#define COMP_SR_C1VAL                COMP_SR_C1VAL_Msk

+#define COMP_SR_C2VAL_Pos            (1U)

+#define COMP_SR_C2VAL_Msk            (0x1UL << COMP_SR_C2VAL_Pos)              /*!< 0x00000002 */

+#define COMP_SR_C2VAL                COMP_SR_C2VAL_Msk

+#define COMP_SR_C1IF_Pos             (16U)

+#define COMP_SR_C1IF_Msk             (0x1UL << COMP_SR_C1IF_Pos)               /*!< 0x00010000 */

+#define COMP_SR_C1IF                 COMP_SR_C1IF_Msk

+#define COMP_SR_C2IF_Pos             (17U)

+#define COMP_SR_C2IF_Msk             (0x1UL << COMP_SR_C2IF_Pos)               /*!< 0x00020000 */

+#define COMP_SR_C2IF                 COMP_SR_C2IF_Msk

+/*******************  Bit definition for COMP_ICFR register  ********************/

+#define COMP_ICFR_C1IF_Pos           (16U)

+#define COMP_ICFR_C1IF_Msk           (0x1UL << COMP_ICFR_C1IF_Pos)             /*!< 0x00010000 */

+#define COMP_ICFR_C1IF               COMP_ICFR_C1IF_Msk

+#define COMP_ICFR_C2IF_Pos           (17U)

+#define COMP_ICFR_C2IF_Msk           (0x1UL << COMP_ICFR_C2IF_Pos)             /*!< 0x00020000 */

+#define COMP_ICFR_C2IF               COMP_ICFR_C2IF_Msk

+/*******************  Bit definition for COMP_OR register  ********************/

+#define COMP_OR_AFOPA6_Pos           (0U)

+#define COMP_OR_AFOPA6_Msk           (0x1UL << COMP_OR_AFOPA6_Pos)             /*!< 0x00000001 */

+#define COMP_OR_AFOPA6               COMP_OR_AFOPA6_Msk

+#define COMP_OR_AFOPA8_Pos           (1U)

+#define COMP_OR_AFOPA8_Msk           (0x1UL << COMP_OR_AFOPA8_Pos)             /*!< 0x00000002 */

+#define COMP_OR_AFOPA8               COMP_OR_AFOPA8_Msk

+#define COMP_OR_AFOPB12_Pos          (2U)

+#define COMP_OR_AFOPB12_Msk          (0x1UL << COMP_OR_AFOPB12_Pos)            /*!< 0x00000004 */

+#define COMP_OR_AFOPB12              COMP_OR_AFOPB12_Msk

+#define COMP_OR_AFOPE6_Pos           (3U)

+#define COMP_OR_AFOPE6_Msk           (0x1UL << COMP_OR_AFOPE6_Pos)             /*!< 0x00000008 */

+#define COMP_OR_AFOPE6               COMP_OR_AFOPE6_Msk

+#define COMP_OR_AFOPE15_Pos          (4U)

+#define COMP_OR_AFOPE15_Msk          (0x1UL << COMP_OR_AFOPE15_Pos)            /*!< 0x00000010 */

+#define COMP_OR_AFOPE15              COMP_OR_AFOPE15_Msk

+#define COMP_OR_AFOPG2_Pos           (5U)

+#define COMP_OR_AFOPG2_Msk           (0x1UL << COMP_OR_AFOPG2_Pos)             /*!< 0x00000020 */

+#define COMP_OR_AFOPG2               COMP_OR_AFOPG2_Msk

+#define COMP_OR_AFOPG3_Pos           (6U)

+#define COMP_OR_AFOPG3_Msk           (0x1UL << COMP_OR_AFOPG3_Pos)             /*!< 0x00000040 */

+#define COMP_OR_AFOPG3               COMP_OR_AFOPG3_Msk

+#define COMP_OR_AFOPG4_Pos           (7U)

+#define COMP_OR_AFOPG4_Msk           (0x1UL << COMP_OR_AFOPG4_Pos)             /*!< 0x00000080 */

+#define COMP_OR_AFOPG4               COMP_OR_AFOPG4_Msk

+#define COMP_OR_AFOPI1_Pos           (8U)

+#define COMP_OR_AFOPI1_Msk           (0x1UL << COMP_OR_AFOPI1_Pos)             /*!< 0x00000100 */

+#define COMP_OR_AFOPI1               COMP_OR_AFOPI1_Msk

+#define COMP_OR_AFOPI4_Pos           (9U)

+#define COMP_OR_AFOPI4_Msk           (0x1UL << COMP_OR_AFOPI4_Pos)             /*!< 0x00000200 */

+#define COMP_OR_AFOPI4               COMP_OR_AFOPI4_Msk

+#define COMP_OR_AFOPK2_Pos           (10U)

+#define COMP_OR_AFOPK2_Msk           (0x1UL << COMP_OR_AFOPK2_Pos)             /*!< 0x00000400 */

+#define COMP_OR_AFOPK2               COMP_OR_AFOPK2_Msk

+

+/*!< ******************  Bit definition for COMP_CFGRx register  ********************/

+#define COMP_CFGRx_EN_Pos            (0U)

+#define COMP_CFGRx_EN_Msk            (0x1UL << COMP_CFGRx_EN_Pos)              /*!< 0x00000001 */

+#define COMP_CFGRx_EN                COMP_CFGRx_EN_Msk                         /*!< COMPx enable bit                     */

+#define COMP_CFGRx_BRGEN_Pos         (1U)

+#define COMP_CFGRx_BRGEN_Msk         (0x1UL << COMP_CFGRx_BRGEN_Pos)           /*!< 0x00000002 */

+#define COMP_CFGRx_BRGEN             COMP_CFGRx_BRGEN_Msk                      /*!< COMPx Scaler bridge enable           */

+#define COMP_CFGRx_SCALEN_Pos        (2U)

+#define COMP_CFGRx_SCALEN_Msk        (0x1UL << COMP_CFGRx_SCALEN_Pos)          /*!< 0x00000004 */

+#define COMP_CFGRx_SCALEN            COMP_CFGRx_SCALEN_Msk                     /*!< COMPx Voltage scaler enable bit      */

+#define COMP_CFGRx_POLARITY_Pos      (3U)

+#define COMP_CFGRx_POLARITY_Msk      (0x1UL << COMP_CFGRx_POLARITY_Pos)        /*!< 0x00000008 */

+#define COMP_CFGRx_POLARITY          COMP_CFGRx_POLARITY_Msk                   /*!< COMPx  polarity selection bit        */

+#define COMP_CFGRx_WINMODE_Pos       (4U)

+#define COMP_CFGRx_WINMODE_Msk       (0x1UL << COMP_CFGRx_WINMODE_Pos)         /*!< 0x00000010 */

+#define COMP_CFGRx_WINMODE           COMP_CFGRx_WINMODE_Msk                    /*!< COMPx Windows mode selection bit     */

+#define COMP_CFGRx_ITEN_Pos          (6U)

+#define COMP_CFGRx_ITEN_Msk          (0x1UL << COMP_CFGRx_ITEN_Pos)            /*!< 0x00000040 */

+#define COMP_CFGRx_ITEN              COMP_CFGRx_ITEN_Msk                       /*!< COMPx  interrupt enable              */

+#define COMP_CFGRx_HYST_Pos          (8U)

+#define COMP_CFGRx_HYST_Msk          (0x3UL << COMP_CFGRx_HYST_Pos)            /*!< 0x00000300 */

+#define COMP_CFGRx_HYST              COMP_CFGRx_HYST_Msk                       /*!< COMPx  hysteresis selection bits     */

+#define COMP_CFGRx_HYST_0            (0x1UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000100 */

+#define COMP_CFGRx_HYST_1            (0x2UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000200 */

+#define COMP_CFGRx_PWRMODE_Pos       (12U)

+#define COMP_CFGRx_PWRMODE_Msk       (0x3UL << COMP_CFGRx_PWRMODE_Pos)         /*!< 0x00003000 */

+#define COMP_CFGRx_PWRMODE           COMP_CFGRx_PWRMODE_Msk                    /*!< COMPx Power Mode of the comparator   */

+#define COMP_CFGRx_PWRMODE_0         (0x1UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00001000 */

+#define COMP_CFGRx_PWRMODE_1         (0x2UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00002000 */

+#define COMP_CFGRx_INMSEL_Pos        (16U)

+#define COMP_CFGRx_INMSEL_Msk        (0x7UL << COMP_CFGRx_INMSEL_Pos)          /*!< 0x00070000 */

+#define COMP_CFGRx_INMSEL            COMP_CFGRx_INMSEL_Msk                     /*!< COMPx  input minus selection bit  */

+#define COMP_CFGRx_INMSEL_0          (0x1UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00010000 */

+#define COMP_CFGRx_INMSEL_1          (0x2UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00020000 */

+#define COMP_CFGRx_INMSEL_2          (0x4UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00040000 */

+#define COMP_CFGRx_INPSEL_Pos        (20U)

+#define COMP_CFGRx_INPSEL_Msk        (0x1UL << COMP_CFGRx_INPSEL_Pos)          /*!< 0x00100000 */

+#define COMP_CFGRx_INPSEL            COMP_CFGRx_INPSEL_Msk                     /*!< COMPx  input plus selection bit       */

+#define COMP_CFGRx_BLANKING_Pos      (24U)

+#define COMP_CFGRx_BLANKING_Msk      (0xFUL << COMP_CFGRx_BLANKING_Pos)        /*!< 0x0F000000 */

+#define COMP_CFGRx_BLANKING          COMP_CFGRx_BLANKING_Msk                   /*!< COMPx  blanking source selection bits */

+#define COMP_CFGRx_BLANKING_0        (0x1UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x01000000 */

+#define COMP_CFGRx_BLANKING_1        (0x2UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x02000000 */

+#define COMP_CFGRx_BLANKING_2        (0x4UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x04000000 */

+#define COMP_CFGRx_LOCK_Pos          (31U)

+#define COMP_CFGRx_LOCK_Msk          (0x1UL << COMP_CFGRx_LOCK_Pos)            /*!< 0x80000000 */

+#define COMP_CFGRx_LOCK              COMP_CFGRx_LOCK_Msk                       /*!< COMPx Lock Bit                        */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for USART_CR1 register  *******************/

+#define USART_CR1_UE_Pos                (0U)

+#define USART_CR1_UE_Msk                (0x1UL << USART_CR1_UE_Pos)            /*!< 0x00000001 */

+#define USART_CR1_UE                    USART_CR1_UE_Msk                       /*!< USART Enable */

+#define USART_CR1_UESM_Pos              (1U)

+#define USART_CR1_UESM_Msk              (0x1UL << USART_CR1_UESM_Pos)          /*!< 0x00000002 */

+#define USART_CR1_UESM                  USART_CR1_UESM_Msk                     /*!< USART Enable in STOP Mode */

+#define USART_CR1_RE_Pos                (2U)

+#define USART_CR1_RE_Msk                (0x1UL << USART_CR1_RE_Pos)            /*!< 0x00000004 */

+#define USART_CR1_RE                    USART_CR1_RE_Msk                       /*!< Receiver Enable */

+#define USART_CR1_TE_Pos                (3U)

+#define USART_CR1_TE_Msk                (0x1UL << USART_CR1_TE_Pos)            /*!< 0x00000008 */

+#define USART_CR1_TE                    USART_CR1_TE_Msk                       /*!< Transmitter Enable */

+#define USART_CR1_IDLEIE_Pos            (4U)

+#define USART_CR1_IDLEIE_Msk            (0x1UL << USART_CR1_IDLEIE_Pos)        /*!< 0x00000010 */

+#define USART_CR1_IDLEIE                USART_CR1_IDLEIE_Msk                   /*!< IDLE Interrupt Enable */

+#define USART_CR1_RXNEIE_RXFNEIE_Pos    (5U)

+#define USART_CR1_RXNEIE_RXFNEIE_Msk    (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */

+#define USART_CR1_RXNEIE_RXFNEIE        USART_CR1_RXNEIE_RXFNEIE_Msk           /*!< RXNE and RX FIFO Not Empty Interrupt Enable */

+#define USART_CR1_TCIE_Pos              (6U)

+#define USART_CR1_TCIE_Msk              (0x1UL << USART_CR1_TCIE_Pos)          /*!< 0x00000040 */

+#define USART_CR1_TCIE                  USART_CR1_TCIE_Msk                     /*!< Transmission Complete Interrupt Enable */

+#define USART_CR1_TXEIE_TXFNFIE_Pos     (7U)

+#define USART_CR1_TXEIE_TXFNFIE_Msk     (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */

+#define USART_CR1_TXEIE_TXFNFIE         USART_CR1_TXEIE_TXFNFIE_Msk            /*!< TXE and TX FIFO Not Full Interrupt Enable */

+#define USART_CR1_PEIE_Pos              (8U)

+#define USART_CR1_PEIE_Msk              (0x1UL << USART_CR1_PEIE_Pos)          /*!< 0x00000100 */

+#define USART_CR1_PEIE                  USART_CR1_PEIE_Msk                     /*!< PE Interrupt Enable */

+#define USART_CR1_PS_Pos                (9U)

+#define USART_CR1_PS_Msk                (0x1UL << USART_CR1_PS_Pos)            /*!< 0x00000200 */

+#define USART_CR1_PS                    USART_CR1_PS_Msk                       /*!< Parity Selection */

+#define USART_CR1_PCE_Pos               (10U)

+#define USART_CR1_PCE_Msk               (0x1UL << USART_CR1_PCE_Pos)           /*!< 0x00000400 */

+#define USART_CR1_PCE                   USART_CR1_PCE_Msk                      /*!< Parity Control Enable */

+#define USART_CR1_WAKE_Pos              (11U)

+#define USART_CR1_WAKE_Msk              (0x1UL << USART_CR1_WAKE_Pos)          /*!< 0x00000800 */

+#define USART_CR1_WAKE                  USART_CR1_WAKE_Msk                     /*!< Receiver Wakeup method */

+#define USART_CR1_M_Pos                 (12U)

+#define USART_CR1_M_Msk                 (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */

+#define USART_CR1_M                     USART_CR1_M_Msk                        /*!< Word length */

+#define USART_CR1_M0_Pos                (12U)

+#define USART_CR1_M0_Msk                (0x1UL << USART_CR1_M0_Pos)            /*!< 0x00001000 */

+#define USART_CR1_M0                    USART_CR1_M0_Msk                       /*!< Word length - Bit 0 */

+#define USART_CR1_MME_Pos               (13U)

+#define USART_CR1_MME_Msk               (0x1UL << USART_CR1_MME_Pos)           /*!< 0x00002000 */

+#define USART_CR1_MME                   USART_CR1_MME_Msk                      /*!< Mute Mode Enable */

+#define USART_CR1_CMIE_Pos              (14U)

+#define USART_CR1_CMIE_Msk              (0x1UL << USART_CR1_CMIE_Pos)          /*!< 0x00004000 */

+#define USART_CR1_CMIE                  USART_CR1_CMIE_Msk                     /*!< Character match interrupt enable */

+#define USART_CR1_OVER8_Pos             (15U)

+#define USART_CR1_OVER8_Msk             (0x1UL << USART_CR1_OVER8_Pos)         /*!< 0x00008000 */

+#define USART_CR1_OVER8                 USART_CR1_OVER8_Msk                    /*!< Oversampling by 8-bit or 16-bit mode */

+#define USART_CR1_DEDT_Pos              (16U)

+#define USART_CR1_DEDT_Msk              (0x1FUL << USART_CR1_DEDT_Pos)         /*!< 0x001F0000 */

+#define USART_CR1_DEDT                  USART_CR1_DEDT_Msk                     /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */

+#define USART_CR1_DEDT_0                (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */

+#define USART_CR1_DEDT_1                (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */

+#define USART_CR1_DEDT_2                (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */

+#define USART_CR1_DEDT_3                (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */

+#define USART_CR1_DEDT_4                (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */

+#define USART_CR1_DEAT_Pos              (21U)

+#define USART_CR1_DEAT_Msk              (0x1FUL << USART_CR1_DEAT_Pos)         /*!< 0x03E00000 */

+#define USART_CR1_DEAT                  USART_CR1_DEAT_Msk                     /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */

+#define USART_CR1_DEAT_0                (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */

+#define USART_CR1_DEAT_1                (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */

+#define USART_CR1_DEAT_2                (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */

+#define USART_CR1_DEAT_3                (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */

+#define USART_CR1_DEAT_4                (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */

+#define USART_CR1_RTOIE_Pos             (26U)

+#define USART_CR1_RTOIE_Msk             (0x1UL << USART_CR1_RTOIE_Pos)         /*!< 0x04000000 */

+#define USART_CR1_RTOIE                 USART_CR1_RTOIE_Msk                    /*!< Receive Time Out interrupt enable */

+#define USART_CR1_EOBIE_Pos             (27U)

+#define USART_CR1_EOBIE_Msk             (0x1UL << USART_CR1_EOBIE_Pos)         /*!< 0x08000000 */

+#define USART_CR1_EOBIE                 USART_CR1_EOBIE_Msk                    /*!< End of Block interrupt enable */

+#define USART_CR1_M1_Pos                (28U)

+#define USART_CR1_M1_Msk                (0x1UL << USART_CR1_M1_Pos)            /*!< 0x10000000 */

+#define USART_CR1_M1                    USART_CR1_M1_Msk                       /*!< Word length - Bit 1 */

+#define USART_CR1_FIFOEN_Pos            (29U)

+#define USART_CR1_FIFOEN_Msk            (0x1UL << USART_CR1_FIFOEN_Pos)        /*!< 0x20000000 */

+#define USART_CR1_FIFOEN                USART_CR1_FIFOEN_Msk                   /*!< FIFO mode enable */

+#define USART_CR1_TXFEIE_Pos            (30U)

+#define USART_CR1_TXFEIE_Msk            (0x1UL << USART_CR1_TXFEIE_Pos)        /*!< 0x40000000 */

+#define USART_CR1_TXFEIE                USART_CR1_TXFEIE_Msk                   /*!< TXFIFO empty interrupt enable */

+#define USART_CR1_RXFFIE_Pos            (31U)

+#define USART_CR1_RXFFIE_Msk            (0x1UL << USART_CR1_RXFFIE_Pos)        /*!< 0x80000000 */

+#define USART_CR1_RXFFIE                USART_CR1_RXFFIE_Msk                   /*!< RXFIFO Full interrupt enable */

+

+/* Legacy define */

+#define  USART_CR1_RXNEIE  USART_CR1_RXNEIE_RXFNEIE

+#define  USART_CR1_TXEIE   USART_CR1_TXEIE_TXFNFIE

+

+/******************  Bit definition for USART_CR2 register  *******************/

+#define USART_CR2_SLVEN_Pos             (0U)

+#define USART_CR2_SLVEN_Msk             (0x1UL << USART_CR2_SLVEN_Pos)         /*!< 0x00000001 */

+#define USART_CR2_SLVEN                 USART_CR2_SLVEN_Msk                    /*!< Synchronous Slave mode Enable */

+#define USART_CR2_DIS_NSS_Pos           (3U)

+#define USART_CR2_DIS_NSS_Msk           (0x1UL << USART_CR2_DIS_NSS_Pos)       /*!< 0x00000008 */

+#define USART_CR2_DIS_NSS               USART_CR2_DIS_NSS_Msk                  /*!< Negative Slave Select (NSS) pin management */

+#define USART_CR2_ADDM7_Pos             (4U)

+#define USART_CR2_ADDM7_Msk             (0x1UL << USART_CR2_ADDM7_Pos)         /*!< 0x00000010 */

+#define USART_CR2_ADDM7                 USART_CR2_ADDM7_Msk                    /*!< 7-bit or 4-bit Address Detection */

+#define USART_CR2_LBDL_Pos              (5U)

+#define USART_CR2_LBDL_Msk              (0x1UL << USART_CR2_LBDL_Pos)          /*!< 0x00000020 */

+#define USART_CR2_LBDL                  USART_CR2_LBDL_Msk                     /*!< LIN Break Detection Length */

+#define USART_CR2_LBDIE_Pos             (6U)

+#define USART_CR2_LBDIE_Msk             (0x1UL << USART_CR2_LBDIE_Pos)         /*!< 0x00000040 */

+#define USART_CR2_LBDIE                 USART_CR2_LBDIE_Msk                    /*!< LIN Break Detection Interrupt Enable */

+#define USART_CR2_LBCL_Pos              (8U)

+#define USART_CR2_LBCL_Msk              (0x1UL << USART_CR2_LBCL_Pos)          /*!< 0x00000100 */

+#define USART_CR2_LBCL                  USART_CR2_LBCL_Msk                     /*!< Last Bit Clock pulse */

+#define USART_CR2_CPHA_Pos              (9U)

+#define USART_CR2_CPHA_Msk              (0x1UL << USART_CR2_CPHA_Pos)          /*!< 0x00000200 */

+#define USART_CR2_CPHA                  USART_CR2_CPHA_Msk                     /*!< Clock Phase */

+#define USART_CR2_CPOL_Pos              (10U)

+#define USART_CR2_CPOL_Msk              (0x1UL << USART_CR2_CPOL_Pos)          /*!< 0x00000400 */

+#define USART_CR2_CPOL                  USART_CR2_CPOL_Msk                     /*!< Clock Polarity */

+#define USART_CR2_CLKEN_Pos             (11U)

+#define USART_CR2_CLKEN_Msk             (0x1UL << USART_CR2_CLKEN_Pos)         /*!< 0x00000800 */

+#define USART_CR2_CLKEN                 USART_CR2_CLKEN_Msk                    /*!< Clock Enable */

+#define USART_CR2_STOP_Pos              (12U)

+#define USART_CR2_STOP_Msk              (0x3UL << USART_CR2_STOP_Pos)          /*!< 0x00003000 */

+#define USART_CR2_STOP                  USART_CR2_STOP_Msk                     /*!< STOP[1:0] bits (STOP bits) */

+#define USART_CR2_STOP_0                (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */

+#define USART_CR2_STOP_1                (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */

+#define USART_CR2_LINEN_Pos             (14U)

+#define USART_CR2_LINEN_Msk             (0x1UL << USART_CR2_LINEN_Pos)         /*!< 0x00004000 */

+#define USART_CR2_LINEN                 USART_CR2_LINEN_Msk                    /*!< LIN mode enable */

+#define USART_CR2_SWAP_Pos              (15U)

+#define USART_CR2_SWAP_Msk              (0x1UL << USART_CR2_SWAP_Pos)          /*!< 0x00008000 */

+#define USART_CR2_SWAP                  USART_CR2_SWAP_Msk                     /*!< SWAP TX/RX pins */

+#define USART_CR2_RXINV_Pos             (16U)

+#define USART_CR2_RXINV_Msk             (0x1UL << USART_CR2_RXINV_Pos)         /*!< 0x00010000 */

+#define USART_CR2_RXINV                 USART_CR2_RXINV_Msk                    /*!< RX pin active level inversion */

+#define USART_CR2_TXINV_Pos             (17U)

+#define USART_CR2_TXINV_Msk             (0x1UL << USART_CR2_TXINV_Pos)         /*!< 0x00020000 */

+#define USART_CR2_TXINV                 USART_CR2_TXINV_Msk                    /*!< TX pin active level inversion */

+#define USART_CR2_DATAINV_Pos           (18U)

+#define USART_CR2_DATAINV_Msk           (0x1UL << USART_CR2_DATAINV_Pos)       /*!< 0x00040000 */

+#define USART_CR2_DATAINV               USART_CR2_DATAINV_Msk                  /*!< Binary data inversion */

+#define USART_CR2_MSBFIRST_Pos          (19U)

+#define USART_CR2_MSBFIRST_Msk          (0x1UL << USART_CR2_MSBFIRST_Pos)      /*!< 0x00080000 */

+#define USART_CR2_MSBFIRST              USART_CR2_MSBFIRST_Msk                 /*!< Most Significant Bit First */

+#define USART_CR2_ABREN_Pos             (20U)

+#define USART_CR2_ABREN_Msk             (0x1UL << USART_CR2_ABREN_Pos)         /*!< 0x00100000 */

+#define USART_CR2_ABREN                 USART_CR2_ABREN_Msk                    /*!< Auto Baud-Rate Enable*/

+#define USART_CR2_ABRMODE_Pos           (21U)

+#define USART_CR2_ABRMODE_Msk           (0x3UL << USART_CR2_ABRMODE_Pos)       /*!< 0x00600000 */

+#define USART_CR2_ABRMODE               USART_CR2_ABRMODE_Msk                  /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */

+#define USART_CR2_ABRMODE_0             (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */

+#define USART_CR2_ABRMODE_1             (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */

+#define USART_CR2_RTOEN_Pos             (23U)

+#define USART_CR2_RTOEN_Msk             (0x1UL << USART_CR2_RTOEN_Pos)         /*!< 0x00800000 */

+#define USART_CR2_RTOEN                 USART_CR2_RTOEN_Msk                    /*!< Receiver Time-Out enable */

+#define USART_CR2_ADD_Pos               (24U)

+#define USART_CR2_ADD_Msk               (0xFFUL << USART_CR2_ADD_Pos)          /*!< 0xFF000000 */

+#define USART_CR2_ADD                   USART_CR2_ADD_Msk                      /*!< Address of the USART node */

+

+/******************  Bit definition for USART_CR3 register  *******************/

+#define USART_CR3_EIE_Pos               (0U)

+#define USART_CR3_EIE_Msk               (0x1UL << USART_CR3_EIE_Pos)           /*!< 0x00000001 */

+#define USART_CR3_EIE                   USART_CR3_EIE_Msk                      /*!< Error Interrupt Enable */

+#define USART_CR3_IREN_Pos              (1U)

+#define USART_CR3_IREN_Msk              (0x1UL << USART_CR3_IREN_Pos)          /*!< 0x00000002 */

+#define USART_CR3_IREN                  USART_CR3_IREN_Msk                     /*!< IrDA mode Enable */

+#define USART_CR3_IRLP_Pos              (2U)

+#define USART_CR3_IRLP_Msk              (0x1UL << USART_CR3_IRLP_Pos)          /*!< 0x00000004 */

+#define USART_CR3_IRLP                  USART_CR3_IRLP_Msk                     /*!< IrDA Low-Power */

+#define USART_CR3_HDSEL_Pos             (3U)

+#define USART_CR3_HDSEL_Msk             (0x1UL << USART_CR3_HDSEL_Pos)         /*!< 0x00000008 */

+#define USART_CR3_HDSEL                 USART_CR3_HDSEL_Msk                    /*!< Half-Duplex Selection */

+#define USART_CR3_NACK_Pos              (4U)

+#define USART_CR3_NACK_Msk              (0x1UL << USART_CR3_NACK_Pos)          /*!< 0x00000010 */

+#define USART_CR3_NACK                  USART_CR3_NACK_Msk                     /*!< SmartCard NACK enable */

+#define USART_CR3_SCEN_Pos              (5U)

+#define USART_CR3_SCEN_Msk              (0x1UL << USART_CR3_SCEN_Pos)          /*!< 0x00000020 */

+#define USART_CR3_SCEN                  USART_CR3_SCEN_Msk                     /*!< SmartCard mode enable */

+#define USART_CR3_DMAR_Pos              (6U)

+#define USART_CR3_DMAR_Msk              (0x1UL << USART_CR3_DMAR_Pos)          /*!< 0x00000040 */

+#define USART_CR3_DMAR                  USART_CR3_DMAR_Msk                     /*!< DMA Enable Receiver */

+#define USART_CR3_DMAT_Pos              (7U)

+#define USART_CR3_DMAT_Msk              (0x1UL << USART_CR3_DMAT_Pos)          /*!< 0x00000080 */

+#define USART_CR3_DMAT                  USART_CR3_DMAT_Msk                     /*!< DMA Enable Transmitter */

+#define USART_CR3_RTSE_Pos              (8U)

+#define USART_CR3_RTSE_Msk              (0x1UL << USART_CR3_RTSE_Pos)          /*!< 0x00000100 */

+#define USART_CR3_RTSE                  USART_CR3_RTSE_Msk                     /*!< RTS Enable */

+#define USART_CR3_CTSE_Pos              (9U)

+#define USART_CR3_CTSE_Msk              (0x1UL << USART_CR3_CTSE_Pos)          /*!< 0x00000200 */

+#define USART_CR3_CTSE                  USART_CR3_CTSE_Msk                     /*!< CTS Enable */

+#define USART_CR3_CTSIE_Pos             (10U)

+#define USART_CR3_CTSIE_Msk             (0x1UL << USART_CR3_CTSIE_Pos)         /*!< 0x00000400 */

+#define USART_CR3_CTSIE                 USART_CR3_CTSIE_Msk                    /*!< CTS Interrupt Enable */

+#define USART_CR3_ONEBIT_Pos            (11U)

+#define USART_CR3_ONEBIT_Msk            (0x1UL << USART_CR3_ONEBIT_Pos)        /*!< 0x00000800 */

+#define USART_CR3_ONEBIT                USART_CR3_ONEBIT_Msk                   /*!< One sample bit method enable */

+#define USART_CR3_OVRDIS_Pos            (12U)

+#define USART_CR3_OVRDIS_Msk            (0x1UL << USART_CR3_OVRDIS_Pos)        /*!< 0x00001000 */

+#define USART_CR3_OVRDIS                USART_CR3_OVRDIS_Msk                   /*!< Overrun Disable */

+#define USART_CR3_DDRE_Pos              (13U)

+#define USART_CR3_DDRE_Msk              (0x1UL << USART_CR3_DDRE_Pos)          /*!< 0x00002000 */

+#define USART_CR3_DDRE                  USART_CR3_DDRE_Msk                     /*!< DMA Disable on Reception Error */

+#define USART_CR3_DEM_Pos               (14U)

+#define USART_CR3_DEM_Msk               (0x1UL << USART_CR3_DEM_Pos)           /*!< 0x00004000 */

+#define USART_CR3_DEM                   USART_CR3_DEM_Msk                      /*!< Driver Enable Mode */

+#define USART_CR3_DEP_Pos               (15U)

+#define USART_CR3_DEP_Msk               (0x1UL << USART_CR3_DEP_Pos)           /*!< 0x00008000 */

+#define USART_CR3_DEP                   USART_CR3_DEP_Msk                      /*!< Driver Enable Polarity Selection */

+#define USART_CR3_SCARCNT_Pos           (17U)

+#define USART_CR3_SCARCNT_Msk           (0x7UL << USART_CR3_SCARCNT_Pos)       /*!< 0x000E0000 */

+#define USART_CR3_SCARCNT               USART_CR3_SCARCNT_Msk                  /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */

+#define USART_CR3_SCARCNT_0             (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */

+#define USART_CR3_SCARCNT_1             (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */

+#define USART_CR3_SCARCNT_2             (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */

+#define USART_CR3_WUS_Pos               (20U)

+#define USART_CR3_WUS_Msk               (0x3UL << USART_CR3_WUS_Pos)           /*!< 0x00300000 */

+#define USART_CR3_WUS                   USART_CR3_WUS_Msk                      /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */

+#define USART_CR3_WUS_0                 (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */

+#define USART_CR3_WUS_1                 (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */

+#define USART_CR3_WUFIE_Pos             (22U)

+#define USART_CR3_WUFIE_Msk             (0x1UL << USART_CR3_WUFIE_Pos)         /*!< 0x00400000 */

+#define USART_CR3_WUFIE                 USART_CR3_WUFIE_Msk                    /*!< Wake Up Interrupt Enable */

+#define USART_CR3_TXFTIE_Pos            (23U)

+#define USART_CR3_TXFTIE_Msk            (0x1UL << USART_CR3_TXFTIE_Pos)        /*!< 0x00800000 */

+#define USART_CR3_TXFTIE                USART_CR3_TXFTIE_Msk                   /*!< TXFIFO threshold interrupt enable */

+#define USART_CR3_TCBGTIE_Pos           (24U)

+#define USART_CR3_TCBGTIE_Msk           (0x1UL << USART_CR3_TCBGTIE_Pos)       /*!< 0x01000000 */

+#define USART_CR3_TCBGTIE               USART_CR3_TCBGTIE_Msk                  /*!< Transmission Complete before guard time, interrupt enable */

+#define USART_CR3_RXFTCFG_Pos           (25U)

+#define USART_CR3_RXFTCFG_Msk           (0x7UL << USART_CR3_RXFTCFG_Pos)       /*!< 0x0E000000 */

+#define USART_CR3_RXFTCFG               USART_CR3_RXFTCFG_Msk                  /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */

+#define USART_CR3_RXFTCFG_0             (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */

+#define USART_CR3_RXFTCFG_1             (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */

+#define USART_CR3_RXFTCFG_2             (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */

+#define USART_CR3_RXFTIE_Pos            (28U)

+#define USART_CR3_RXFTIE_Msk            (0x1UL << USART_CR3_RXFTIE_Pos)        /*!< 0x10000000 */

+#define USART_CR3_RXFTIE                USART_CR3_RXFTIE_Msk                   /*!< RXFIFO threshold interrupt enable */

+#define USART_CR3_TXFTCFG_Pos           (29U)

+#define USART_CR3_TXFTCFG_Msk           (0x7UL << USART_CR3_TXFTCFG_Pos)       /*!< 0xE0000000 */

+#define USART_CR3_TXFTCFG               USART_CR3_TXFTCFG_Msk                  /*!< TXFIFO [2:0] threshold configuration */

+#define USART_CR3_TXFTCFG_0             (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */

+#define USART_CR3_TXFTCFG_1             (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */

+#define USART_CR3_TXFTCFG_2             (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */

+

+/******************  Bit definition for USART_BRR register  *******************/

+#define USART_BRR_DIV_FRACTION_Pos      (0U)

+#define USART_BRR_DIV_FRACTION_Msk      (0xFUL << USART_BRR_DIV_FRACTION_Pos)  /*!< 0x0000000F */

+#define USART_BRR_DIV_FRACTION          USART_BRR_DIV_FRACTION_Msk             /*!< Fraction of USARTDIV */

+#define USART_BRR_DIV_MANTISSA_Pos      (4U)

+#define USART_BRR_DIV_MANTISSA_Msk      (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */

+#define USART_BRR_DIV_MANTISSA          USART_BRR_DIV_MANTISSA_Msk             /*!< Mantissa of USARTDIV */

+

+/******************  Bit definition for USART_GTPR register  ******************/

+#define USART_GTPR_PSC_Pos              (0U)

+#define USART_GTPR_PSC_Msk              (0xFFUL << USART_GTPR_PSC_Pos)         /*!< 0x000000FF */

+#define USART_GTPR_PSC                  USART_GTPR_PSC_Msk                     /*!< PSC[7:0] bits (Prescaler value) */

+#define USART_GTPR_GT_Pos               (8U)

+#define USART_GTPR_GT_Msk               (0xFFUL << USART_GTPR_GT_Pos)          /*!< 0x0000FF00 */

+#define USART_GTPR_GT                   USART_GTPR_GT_Msk                      /*!< GT[7:0] bits (Guard time value) */

+

+/*******************  Bit definition for USART_RTOR register  *****************/

+#define USART_RTOR_RTO_Pos              (0U)

+#define USART_RTOR_RTO_Msk              (0xFFFFFFUL << USART_RTOR_RTO_Pos)     /*!< 0x00FFFFFF */

+#define USART_RTOR_RTO                  USART_RTOR_RTO_Msk                     /*!< Receiver Time Out Value */

+#define USART_RTOR_BLEN_Pos             (24U)

+#define USART_RTOR_BLEN_Msk             (0xFFUL << USART_RTOR_BLEN_Pos)        /*!< 0xFF000000 */

+#define USART_RTOR_BLEN                 USART_RTOR_BLEN_Msk                    /*!< Block Length */

+

+/*******************  Bit definition for USART_RQR register  ******************/

+#define USART_RQR_ABRRQ_Pos             (0U)

+#define USART_RQR_ABRRQ_Msk             (0x1UL << USART_RQR_ABRRQ_Pos)         /*!< 0x00000001 */

+#define USART_RQR_ABRRQ                 USART_RQR_ABRRQ_Msk                    /*!< Auto-Baud Rate Request */

+#define USART_RQR_SBKRQ_Pos             (1U)

+#define USART_RQR_SBKRQ_Msk             (0x1UL << USART_RQR_SBKRQ_Pos)         /*!< 0x00000002 */

+#define USART_RQR_SBKRQ                 USART_RQR_SBKRQ_Msk                    /*!< Send Break Request */

+#define USART_RQR_MMRQ_Pos              (2U)

+#define USART_RQR_MMRQ_Msk              (0x1UL << USART_RQR_MMRQ_Pos)          /*!< 0x00000004 */

+#define USART_RQR_MMRQ                  USART_RQR_MMRQ_Msk                     /*!< Mute Mode Request */

+#define USART_RQR_RXFRQ_Pos             (3U)

+#define USART_RQR_RXFRQ_Msk             (0x1UL << USART_RQR_RXFRQ_Pos)         /*!< 0x00000008 */

+#define USART_RQR_RXFRQ                 USART_RQR_RXFRQ_Msk                    /*!< Receive Data flush Request */

+#define USART_RQR_TXFRQ_Pos             (4U)

+#define USART_RQR_TXFRQ_Msk             (0x1UL << USART_RQR_TXFRQ_Pos)         /*!< 0x00000010 */

+#define USART_RQR_TXFRQ                 USART_RQR_TXFRQ_Msk                    /*!< Transmit data flush Request */

+

+/*******************  Bit definition for USART_ISR register  ******************/

+#define USART_ISR_PE_Pos                (0U)

+#define USART_ISR_PE_Msk                (0x1UL << USART_ISR_PE_Pos)            /*!< 0x00000001 */

+#define USART_ISR_PE                    USART_ISR_PE_Msk                       /*!< Parity Error */

+#define USART_ISR_FE_Pos                (1U)

+#define USART_ISR_FE_Msk                (0x1UL << USART_ISR_FE_Pos)            /*!< 0x00000002 */

+#define USART_ISR_FE                    USART_ISR_FE_Msk                       /*!< Framing Error */

+#define USART_ISR_NE_Pos                (2U)

+#define USART_ISR_NE_Msk                (0x1UL << USART_ISR_NE_Pos)            /*!< 0x00000004 */

+#define USART_ISR_NE                    USART_ISR_NE_Msk                       /*!< Noise detected Flag */

+#define USART_ISR_ORE_Pos               (3U)

+#define USART_ISR_ORE_Msk               (0x1UL << USART_ISR_ORE_Pos)           /*!< 0x00000008 */

+#define USART_ISR_ORE                   USART_ISR_ORE_Msk                      /*!< OverRun Error */

+#define USART_ISR_IDLE_Pos              (4U)

+#define USART_ISR_IDLE_Msk              (0x1UL << USART_ISR_IDLE_Pos)          /*!< 0x00000010 */

+#define USART_ISR_IDLE                  USART_ISR_IDLE_Msk                     /*!< IDLE line detected */

+#define USART_ISR_RXNE_RXFNE_Pos        (5U)

+#define USART_ISR_RXNE_RXFNE_Msk        (0x1UL << USART_ISR_RXNE_RXFNE_Pos)    /*!< 0x00000020 */

+#define USART_ISR_RXNE_RXFNE            USART_ISR_RXNE_RXFNE_Msk               /*!< Read Data Register or RX FIFO Not Empty */

+#define USART_ISR_TC_Pos                (6U)

+#define USART_ISR_TC_Msk                (0x1UL << USART_ISR_TC_Pos)            /*!< 0x00000040 */

+#define USART_ISR_TC                    USART_ISR_TC_Msk                       /*!< Transmission Complete */

+#define USART_ISR_TXE_TXFNF_Pos         (7U)

+#define USART_ISR_TXE_TXFNF_Msk         (0x1UL << USART_ISR_TXE_TXFNF_Pos)     /*!< 0x00000080 */

+#define USART_ISR_TXE_TXFNF             USART_ISR_TXE_TXFNF_Msk                /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */

+#define USART_ISR_LBDF_Pos              (8U)

+#define USART_ISR_LBDF_Msk              (0x1UL << USART_ISR_LBDF_Pos)          /*!< 0x00000100 */

+#define USART_ISR_LBDF                  USART_ISR_LBDF_Msk                     /*!< LIN Break Detection Flag */

+#define USART_ISR_CTSIF_Pos             (9U)

+#define USART_ISR_CTSIF_Msk             (0x1UL << USART_ISR_CTSIF_Pos)         /*!< 0x00000200 */

+#define USART_ISR_CTSIF                 USART_ISR_CTSIF_Msk                    /*!< CTS interrupt flag */

+#define USART_ISR_CTS_Pos               (10U)

+#define USART_ISR_CTS_Msk               (0x1UL << USART_ISR_CTS_Pos)           /*!< 0x00000400 */

+#define USART_ISR_CTS                   USART_ISR_CTS_Msk                      /*!< CTS flag */

+#define USART_ISR_RTOF_Pos              (11U)

+#define USART_ISR_RTOF_Msk              (0x1UL << USART_ISR_RTOF_Pos)          /*!< 0x00000800 */

+#define USART_ISR_RTOF                  USART_ISR_RTOF_Msk                     /*!< Receiver Time Out */

+#define USART_ISR_EOBF_Pos              (12U)

+#define USART_ISR_EOBF_Msk              (0x1UL << USART_ISR_EOBF_Pos)          /*!< 0x00001000 */

+#define USART_ISR_EOBF                  USART_ISR_EOBF_Msk                     /*!< End Of Block Flag */

+#define USART_ISR_UDR_Pos               (13U)

+#define USART_ISR_UDR_Msk               (0x1UL << USART_ISR_UDR_Pos)           /*!< 0x00002000 */

+#define USART_ISR_UDR                   USART_ISR_UDR_Msk                      /*!< SPI slave underrun error flag */

+#define USART_ISR_ABRE_Pos              (14U)

+#define USART_ISR_ABRE_Msk              (0x1UL << USART_ISR_ABRE_Pos)          /*!< 0x00004000 */

+#define USART_ISR_ABRE                  USART_ISR_ABRE_Msk                     /*!< Auto-Baud Rate Error */

+#define USART_ISR_ABRF_Pos              (15U)

+#define USART_ISR_ABRF_Msk              (0x1UL << USART_ISR_ABRF_Pos)          /*!< 0x00008000 */

+#define USART_ISR_ABRF                  USART_ISR_ABRF_Msk                     /*!< Auto-Baud Rate Flag */

+#define USART_ISR_BUSY_Pos              (16U)

+#define USART_ISR_BUSY_Msk              (0x1UL << USART_ISR_BUSY_Pos)          /*!< 0x00010000 */

+#define USART_ISR_BUSY                  USART_ISR_BUSY_Msk                     /*!< Busy Flag */

+#define USART_ISR_CMF_Pos               (17U)

+#define USART_ISR_CMF_Msk               (0x1UL << USART_ISR_CMF_Pos)           /*!< 0x00020000 */

+#define USART_ISR_CMF                   USART_ISR_CMF_Msk                      /*!< Character Match Flag */

+#define USART_ISR_SBKF_Pos              (18U)

+#define USART_ISR_SBKF_Msk              (0x1UL << USART_ISR_SBKF_Pos)          /*!< 0x00040000 */

+#define USART_ISR_SBKF                  USART_ISR_SBKF_Msk                     /*!< Send Break Flag */

+#define USART_ISR_RWU_Pos               (19U)

+#define USART_ISR_RWU_Msk               (0x1UL << USART_ISR_RWU_Pos)           /*!< 0x00080000 */

+#define USART_ISR_RWU                   USART_ISR_RWU_Msk                      /*!< Receive Wake Up from mute mode Flag */

+#define USART_ISR_WUF_Pos               (20U)

+#define USART_ISR_WUF_Msk               (0x1UL << USART_ISR_WUF_Pos)           /*!< 0x00100000 */

+#define USART_ISR_WUF                   USART_ISR_WUF_Msk                      /*!< Wake Up from stop mode Flag */

+#define USART_ISR_TEACK_Pos             (21U)

+#define USART_ISR_TEACK_Msk             (0x1UL << USART_ISR_TEACK_Pos)         /*!< 0x00200000 */

+#define USART_ISR_TEACK                 USART_ISR_TEACK_Msk                    /*!< Transmit Enable Acknowledge Flag */

+#define USART_ISR_REACK_Pos             (22U)

+#define USART_ISR_REACK_Msk             (0x1UL << USART_ISR_REACK_Pos)         /*!< 0x00400000 */

+#define USART_ISR_REACK                 USART_ISR_REACK_Msk                    /*!< Receive Enable Acknowledge Flag */

+#define USART_ISR_TXFE_Pos              (23U)

+#define USART_ISR_TXFE_Msk              (0x1UL << USART_ISR_TXFE_Pos)          /*!< 0x00800000 */

+#define USART_ISR_TXFE                  USART_ISR_TXFE_Msk                     /*!< TXFIFO Empty */

+#define USART_ISR_RXFF_Pos              (24U)

+#define USART_ISR_RXFF_Msk              (0x1UL << USART_ISR_RXFF_Pos)          /*!< 0x01000000 */

+#define USART_ISR_RXFF                  USART_ISR_RXFF_Msk                     /*!< RXFIFO Full Flag */

+#define USART_ISR_TCBGT_Pos             (25U)

+#define USART_ISR_TCBGT_Msk             (0x1UL << USART_ISR_TCBGT_Pos)         /*!< 0x02000000 */

+#define USART_ISR_TCBGT                 USART_ISR_TCBGT_Msk                    /*!< Transmission complete before guard time Flag */

+#define USART_ISR_RXFT_Pos              (26U)

+#define USART_ISR_RXFT_Msk              (0x1UL << USART_ISR_RXFT_Pos)          /*!< 0x04000000 */

+#define USART_ISR_RXFT                  USART_ISR_RXFT_Msk                     /*!< RXFIFO threshold Flag */

+#define USART_ISR_TXFT_Pos              (27U)

+#define USART_ISR_TXFT_Msk              (0x1UL << USART_ISR_TXFT_Pos)          /*!< 0x08000000 */

+#define USART_ISR_TXFT                  USART_ISR_TXFT_Msk                     /*!< TXFIFO threshold Flag */

+

+/*******************  Bit definition for USART_ICR register  ******************/

+#define USART_ICR_PECF_Pos              (0U)

+#define USART_ICR_PECF_Msk              (0x1UL << USART_ICR_PECF_Pos)          /*!< 0x00000001 */

+#define USART_ICR_PECF                  USART_ICR_PECF_Msk                     /*!< Parity Error Clear Flag */

+#define USART_ICR_FECF_Pos              (1U)

+#define USART_ICR_FECF_Msk              (0x1UL << USART_ICR_FECF_Pos)          /*!< 0x00000002 */

+#define USART_ICR_FECF                  USART_ICR_FECF_Msk                     /*!< Framing Error Clear Flag */

+#define USART_ICR_NECF_Pos              (2U)

+#define USART_ICR_NECF_Msk              (0x1UL << USART_ICR_NECF_Pos)          /*!< 0x00000004 */

+#define USART_ICR_NECF                  USART_ICR_NECF_Msk                     /*!< Noise detected Clear Flag */

+#define USART_ICR_ORECF_Pos             (3U)

+#define USART_ICR_ORECF_Msk             (0x1UL << USART_ICR_ORECF_Pos)         /*!< 0x00000008 */

+#define USART_ICR_ORECF                 USART_ICR_ORECF_Msk                    /*!< OverRun Error Clear Flag */

+#define USART_ICR_IDLECF_Pos            (4U)

+#define USART_ICR_IDLECF_Msk            (0x1UL << USART_ICR_IDLECF_Pos)        /*!< 0x00000010 */

+#define USART_ICR_IDLECF                USART_ICR_IDLECF_Msk                   /*!< IDLE line detected Clear Flag */

+#define USART_ICR_TXFECF_Pos            (5U)

+#define USART_ICR_TXFECF_Msk            (0x1UL << USART_ICR_TXFECF_Pos)        /*!< 0x00000020 */

+#define USART_ICR_TXFECF                USART_ICR_TXFECF_Msk                   /*!< TXFIFO empty clear flag */

+#define USART_ICR_TCCF_Pos              (6U)

+#define USART_ICR_TCCF_Msk              (0x1UL << USART_ICR_TCCF_Pos)          /*!< 0x00000040 */

+#define USART_ICR_TCCF                  USART_ICR_TCCF_Msk                     /*!< Transmission Complete Clear Flag */

+#define USART_ICR_TCBGTCF_Pos           (7U)

+#define USART_ICR_TCBGTCF_Msk           (0x1UL << USART_ICR_TCBGTCF_Pos)       /*!< 0x00000080 */

+#define USART_ICR_TCBGTCF               USART_ICR_TCBGTCF_Msk                  /*!< Transmission complete before guard time Clear Flag */

+#define USART_ICR_LBDCF_Pos             (8U)

+#define USART_ICR_LBDCF_Msk             (0x1UL << USART_ICR_LBDCF_Pos)         /*!< 0x00000100 */

+#define USART_ICR_LBDCF                 USART_ICR_LBDCF_Msk                    /*!< LIN Break Detection Clear Flag */

+#define USART_ICR_CTSCF_Pos             (9U)

+#define USART_ICR_CTSCF_Msk             (0x1UL << USART_ICR_CTSCF_Pos)         /*!< 0x00000200 */

+#define USART_ICR_CTSCF                 USART_ICR_CTSCF_Msk                    /*!< CTS Interrupt Clear Flag */

+#define USART_ICR_RTOCF_Pos             (11U)

+#define USART_ICR_RTOCF_Msk             (0x1UL << USART_ICR_RTOCF_Pos)         /*!< 0x00000800 */

+#define USART_ICR_RTOCF                 USART_ICR_RTOCF_Msk                    /*!< Receiver Time Out Clear Flag */

+#define USART_ICR_EOBCF_Pos             (12U)

+#define USART_ICR_EOBCF_Msk             (0x1UL << USART_ICR_EOBCF_Pos)         /*!< 0x00001000 */

+#define USART_ICR_EOBCF                 USART_ICR_EOBCF_Msk                    /*!< End Of Block Clear Flag */

+#define USART_ICR_UDRCF_Pos             (13U)

+#define USART_ICR_UDRCF_Msk             (0x1UL << USART_ICR_UDRCF_Pos)         /*!< 0x00002000 */

+#define USART_ICR_UDRCF                 USART_ICR_UDRCF_Msk                    /*!< SPI slave underrun clear flag */

+#define USART_ICR_CMCF_Pos              (17U)

+#define USART_ICR_CMCF_Msk              (0x1UL << USART_ICR_CMCF_Pos)          /*!< 0x00020000 */

+#define USART_ICR_CMCF                  USART_ICR_CMCF_Msk                     /*!< Character Match Clear Flag */

+#define USART_ICR_WUCF_Pos              (20U)

+#define USART_ICR_WUCF_Msk              (0x1UL << USART_ICR_WUCF_Pos)          /*!< 0x00100000 */

+#define USART_ICR_WUCF                  USART_ICR_WUCF_Msk                     /*!< Wake Up from stop mode Clear Flag */

+

+/*******************  Bit definition for USART_RDR register  ******************/

+#define USART_RDR_RDR_Pos               (0U)

+#define USART_RDR_RDR_Msk               (0x1FFUL << USART_RDR_RDR_Pos)         /*!< 0x000001FF */

+#define USART_RDR_RDR                   USART_RDR_RDR_Msk                      /*!< RDR[8:0] bits (Receive Data value) */

+

+/*******************  Bit definition for USART_TDR register  ******************/

+#define USART_TDR_TDR_Pos               (0U)

+#define USART_TDR_TDR_Msk               (0x1FFUL << USART_TDR_TDR_Pos)         /*!< 0x000001FF */

+#define USART_TDR_TDR                   USART_TDR_TDR_Msk                      /*!< TDR[8:0] bits (Transmit Data value) */

+

+/*******************  Bit definition for USART_PRESC register  ******************/

+#define USART_PRESC_PRESCALER_Pos       (0U)

+#define USART_PRESC_PRESCALER_Msk       (0xFUL << USART_PRESC_PRESCALER_Pos)   /*!< 0x0000000F */

+#define USART_PRESC_PRESCALER           USART_PRESC_PRESCALER_Msk              /*!< PRESCALER[3:0] bits (Clock prescaler) */

+#define USART_PRESC_PRESCALER_0         (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */

+#define USART_PRESC_PRESCALER_1         (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */

+#define USART_PRESC_PRESCALER_2         (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */

+#define USART_PRESC_PRESCALER_3         (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */

+

+/******************************************************************************/

+/*                                                                            */

+/*           Single Wire Protocol Master Interface (SWPMI)                    */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for SWPMI_CR register   ********************/

+#define SWPMI_CR_RXDMA_Pos       (0U)

+#define SWPMI_CR_RXDMA_Msk       (0x1UL << SWPMI_CR_RXDMA_Pos)                 /*!< 0x00000001 */

+#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */

+#define SWPMI_CR_TXDMA_Pos       (1U)

+#define SWPMI_CR_TXDMA_Msk       (0x1UL << SWPMI_CR_TXDMA_Pos)                 /*!< 0x00000002 */

+#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */

+#define SWPMI_CR_RXMODE_Pos      (2U)

+#define SWPMI_CR_RXMODE_Msk      (0x1UL << SWPMI_CR_RXMODE_Pos)                /*!< 0x00000004 */

+#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */

+#define SWPMI_CR_TXMODE_Pos      (3U)

+#define SWPMI_CR_TXMODE_Msk      (0x1UL << SWPMI_CR_TXMODE_Pos)                /*!< 0x00000008 */

+#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */

+#define SWPMI_CR_LPBK_Pos        (4U)

+#define SWPMI_CR_LPBK_Msk        (0x1UL << SWPMI_CR_LPBK_Pos)                  /*!< 0x00000010 */

+#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */

+#define SWPMI_CR_SWPACT_Pos      (5U)

+#define SWPMI_CR_SWPACT_Msk      (0x1UL << SWPMI_CR_SWPACT_Pos)                /*!< 0x00000020 */

+#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */

+#define SWPMI_CR_DEACT_Pos       (10U)

+#define SWPMI_CR_DEACT_Msk       (0x1UL << SWPMI_CR_DEACT_Pos)                 /*!< 0x00000400 */

+#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */

+#define SWPMI_CR_SWPEN_Pos       (11U)

+#define SWPMI_CR_SWPEN_Msk       (0x1UL << SWPMI_CR_SWPEN_Pos)                 /*!< 0x00000800 */

+#define SWPMI_CR_SWPEN           SWPMI_CR_SWPEN_Msk                            /*!<Single wire protocol master transceiver enable       */

+

+/*******************  Bit definition for SWPMI_BRR register  ********************/

+#define SWPMI_BRR_BR_Pos         (0U)

+#define SWPMI_BRR_BR_Msk         (0xFFUL << SWPMI_BRR_BR_Pos)                  /*!< 0x000000FF */

+#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[7:0] bits (Bitrate prescaler) */

+

+/*******************  Bit definition for SWPMI_ISR register  ********************/

+#define SWPMI_ISR_RXBFF_Pos      (0U)

+#define SWPMI_ISR_RXBFF_Msk      (0x1UL << SWPMI_ISR_RXBFF_Pos)                /*!< 0x00000001 */

+#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */

+#define SWPMI_ISR_TXBEF_Pos      (1U)

+#define SWPMI_ISR_TXBEF_Msk      (0x1UL << SWPMI_ISR_TXBEF_Pos)                /*!< 0x00000002 */

+#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */

+#define SWPMI_ISR_RXBERF_Pos     (2U)

+#define SWPMI_ISR_RXBERF_Msk     (0x1UL << SWPMI_ISR_RXBERF_Pos)               /*!< 0x00000004 */

+#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */

+#define SWPMI_ISR_RXOVRF_Pos     (3U)

+#define SWPMI_ISR_RXOVRF_Msk     (0x1UL << SWPMI_ISR_RXOVRF_Pos)               /*!< 0x00000008 */

+#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */

+#define SWPMI_ISR_TXUNRF_Pos     (4U)

+#define SWPMI_ISR_TXUNRF_Msk     (0x1UL << SWPMI_ISR_TXUNRF_Pos)               /*!< 0x00000010 */

+#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */

+#define SWPMI_ISR_RXNE_Pos       (5U)

+#define SWPMI_ISR_RXNE_Msk       (0x1UL << SWPMI_ISR_RXNE_Pos)                 /*!< 0x00000020 */

+#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */

+#define SWPMI_ISR_TXE_Pos        (6U)

+#define SWPMI_ISR_TXE_Msk        (0x1UL << SWPMI_ISR_TXE_Pos)                  /*!< 0x00000040 */

+#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */

+#define SWPMI_ISR_TCF_Pos        (7U)

+#define SWPMI_ISR_TCF_Msk        (0x1UL << SWPMI_ISR_TCF_Pos)                  /*!< 0x00000080 */

+#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */

+#define SWPMI_ISR_SRF_Pos        (8U)

+#define SWPMI_ISR_SRF_Msk        (0x1UL << SWPMI_ISR_SRF_Pos)                  /*!< 0x00000100 */

+#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */

+#define SWPMI_ISR_SUSP_Pos       (9U)

+#define SWPMI_ISR_SUSP_Msk       (0x1UL << SWPMI_ISR_SUSP_Pos)                 /*!< 0x00000200 */

+#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */

+#define SWPMI_ISR_DEACTF_Pos     (10U)

+#define SWPMI_ISR_DEACTF_Msk     (0x1UL << SWPMI_ISR_DEACTF_Pos)               /*!< 0x00000400 */

+#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */

+#define SWPMI_ISR_RDYF_Pos       (11U)

+#define SWPMI_ISR_RDYF_Msk       (0x1UL << SWPMI_ISR_RDYF_Pos)                 /*!< 0x00000800 */

+#define SWPMI_ISR_RDYF           SWPMI_ISR_RDYF_Msk                            /*!<Transceiver ready flag          */

+

+/*******************  Bit definition for SWPMI_ICR register  ********************/

+#define SWPMI_ICR_CRXBFF_Pos     (0U)

+#define SWPMI_ICR_CRXBFF_Msk     (0x1UL << SWPMI_ICR_CRXBFF_Pos)               /*!< 0x00000001 */

+#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */

+#define SWPMI_ICR_CTXBEF_Pos     (1U)

+#define SWPMI_ICR_CTXBEF_Msk     (0x1UL << SWPMI_ICR_CTXBEF_Pos)               /*!< 0x00000002 */

+#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */

+#define SWPMI_ICR_CRXBERF_Pos    (2U)

+#define SWPMI_ICR_CRXBERF_Msk    (0x1UL << SWPMI_ICR_CRXBERF_Pos)              /*!< 0x00000004 */

+#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */

+#define SWPMI_ICR_CRXOVRF_Pos    (3U)

+#define SWPMI_ICR_CRXOVRF_Msk    (0x1UL << SWPMI_ICR_CRXOVRF_Pos)              /*!< 0x00000008 */

+#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */

+#define SWPMI_ICR_CTXUNRF_Pos    (4U)

+#define SWPMI_ICR_CTXUNRF_Msk    (0x1UL << SWPMI_ICR_CTXUNRF_Pos)              /*!< 0x00000010 */

+#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */

+#define SWPMI_ICR_CTCF_Pos       (7U)

+#define SWPMI_ICR_CTCF_Msk       (0x1UL << SWPMI_ICR_CTCF_Pos)                 /*!< 0x00000080 */

+#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */

+#define SWPMI_ICR_CSRF_Pos       (8U)

+#define SWPMI_ICR_CSRF_Msk       (0x1UL << SWPMI_ICR_CSRF_Pos)                 /*!< 0x00000100 */

+#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */

+#define SWPMI_ICR_CRDYF_Pos      (11U)

+#define SWPMI_ICR_CRDYF_Msk      (0x1UL << SWPMI_ICR_CRDYF_Pos)                /*!< 0x00000800 */

+#define SWPMI_ICR_CRDYF          SWPMI_ICR_CRDYF_Msk                           /*!<Clear transceiver ready flag         */

+

+/*******************  Bit definition for SWPMI_IER register  ********************/

+#define SWPMI_IER_RXBFIE_Pos     (0U)

+#define SWPMI_IER_RXBFIE_Msk     (0x1UL << SWPMI_IER_RXBFIE_Pos)               /*!< 0x00000001 */

+#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */

+#define SWPMI_IER_TXBEIE_Pos     (1U)

+#define SWPMI_IER_TXBEIE_Msk     (0x1UL << SWPMI_IER_TXBEIE_Pos)               /*!< 0x00000002 */

+#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */

+#define SWPMI_IER_RXBERIE_Pos    (2U)

+#define SWPMI_IER_RXBERIE_Msk    (0x1UL << SWPMI_IER_RXBERIE_Pos)              /*!< 0x00000004 */

+#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */

+#define SWPMI_IER_RXOVRIE_Pos    (3U)

+#define SWPMI_IER_RXOVRIE_Msk    (0x1UL << SWPMI_IER_RXOVRIE_Pos)              /*!< 0x00000008 */

+#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */

+#define SWPMI_IER_TXUNRIE_Pos    (4U)

+#define SWPMI_IER_TXUNRIE_Msk    (0x1UL << SWPMI_IER_TXUNRIE_Pos)              /*!< 0x00000010 */

+#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */

+#define SWPMI_IER_RIE_Pos        (5U)

+#define SWPMI_IER_RIE_Msk        (0x1UL << SWPMI_IER_RIE_Pos)                  /*!< 0x00000020 */

+#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */

+#define SWPMI_IER_TIE_Pos        (6U)

+#define SWPMI_IER_TIE_Msk        (0x1UL << SWPMI_IER_TIE_Pos)                  /*!< 0x00000040 */

+#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */

+#define SWPMI_IER_TCIE_Pos       (7U)

+#define SWPMI_IER_TCIE_Msk       (0x1UL << SWPMI_IER_TCIE_Pos)                 /*!< 0x00000080 */

+#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */

+#define SWPMI_IER_SRIE_Pos       (8U)

+#define SWPMI_IER_SRIE_Msk       (0x1UL << SWPMI_IER_SRIE_Pos)                 /*!< 0x00000100 */

+#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */

+#define SWPMI_IER_RDYIE_Pos      (11U)

+#define SWPMI_IER_RDYIE_Msk      (0x1UL << SWPMI_IER_RDYIE_Pos)                /*!< 0x00000800 */

+#define SWPMI_IER_RDYIE          SWPMI_IER_RDYIE_Msk                           /*!<Transceiver ready interrupt enable          */

+

+/*******************  Bit definition for SWPMI_RFL register  ********************/

+#define SWPMI_RFL_RFL_Pos        (0U)

+#define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */

+#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */

+#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */

+

+/*******************  Bit definition for SWPMI_TDR register  ********************/

+#define SWPMI_TDR_TD_Pos         (0U)

+#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)            /*!< 0xFFFFFFFF */

+#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */

+

+/*******************  Bit definition for SWPMI_RDR register  ********************/

+#define SWPMI_RDR_RD_Pos         (0U)

+#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)            /*!< 0xFFFFFFFF */

+#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Recive Data Register           */

+

+

+/*******************  Bit definition for SWPMI_OR register  ********************/

+#define SWPMI_OR_TBYP_Pos        (0U)

+#define SWPMI_OR_TBYP_Msk        (0x1UL << SWPMI_OR_TBYP_Pos)                  /*!< 0x00000001 */

+#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */

+#define SWPMI_OR_CLASS_Pos       (1U)

+#define SWPMI_OR_CLASS_Msk       (0x1UL << SWPMI_OR_CLASS_Pos)                 /*!< 0x00000002 */

+#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP CLASS selection */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            Window WATCHDOG                                 */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for WWDG_CR register  ********************/

+#define WWDG_CR_T_Pos           (0U)

+#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */

+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */

+#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */

+#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */

+#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */

+#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */

+#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */

+#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */

+#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */

+

+#define WWDG_CR_WDGA_Pos        (7U)

+#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */

+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */

+

+/*******************  Bit definition for WWDG_CFR register  *******************/

+#define WWDG_CFR_W_Pos          (0U)

+#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */

+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */

+#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */

+#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */

+#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */

+#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */

+#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */

+#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */

+#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */

+

+#define WWDG_CFR_EWI_Pos        (9U)

+#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */

+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */

+

+#define WWDG_CFR_WDGTB_Pos      (11U)

+#define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */

+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */

+#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000800 */

+#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00001000 */

+#define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00002000 */

+

+/*******************  Bit definition for WWDG_SR register  ********************/

+#define WWDG_SR_EWIF_Pos        (0U)

+#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */

+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                DBG                                         */

+/*                                                                            */

+/******************************************************************************/

+/*********************************  DEVICE ID  ********************************/

+#define STM32H7_DEV_ID           0x450UL

+

+/********************  Bit definition for DBGMCU_IDCODE register  *************/

+#define DBGMCU_IDCODE_DEV_ID_Pos          (0U)

+#define DBGMCU_IDCODE_DEV_ID_Msk          (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */

+#define DBGMCU_IDCODE_DEV_ID              DBGMCU_IDCODE_DEV_ID_Msk

+#define DBGMCU_IDCODE_REV_ID_Pos          (16U)

+#define DBGMCU_IDCODE_REV_ID_Msk          (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */

+#define DBGMCU_IDCODE_REV_ID              DBGMCU_IDCODE_REV_ID_Msk

+

+/********************  Bit definition for DBGMCU_CR register  *****************/

+#define DBGMCU_CR_DBG_SLEEPD1_Pos         (0U)

+#define DBGMCU_CR_DBG_SLEEPD1_Msk         (0x1UL << DBGMCU_CR_DBG_SLEEPD1_Pos) /*!< 0x00000001 */

+#define DBGMCU_CR_DBG_SLEEPD1             DBGMCU_CR_DBG_SLEEPD1_Msk

+#define DBGMCU_CR_DBG_STOPD1_Pos          (1U)

+#define DBGMCU_CR_DBG_STOPD1_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD1_Pos)  /*!< 0x00000002 */

+#define DBGMCU_CR_DBG_STOPD1              DBGMCU_CR_DBG_STOPD1_Msk

+#define DBGMCU_CR_DBG_STANDBYD1_Pos       (2U)

+#define DBGMCU_CR_DBG_STANDBYD1_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos) /*!< 0x00000004 */

+#define DBGMCU_CR_DBG_STANDBYD1           DBGMCU_CR_DBG_STANDBYD1_Msk

+#define DBGMCU_CR_DBG_SLEEPD2_Pos         (3U)

+#define DBGMCU_CR_DBG_SLEEPD2_Msk         (0x1UL << DBGMCU_CR_DBG_SLEEPD2_Pos) /*!< 0x00000008 */

+#define DBGMCU_CR_DBG_SLEEPD2             DBGMCU_CR_DBG_SLEEPD2_Msk

+#define DBGMCU_CR_DBG_STOPD2_Pos          (4U)

+#define DBGMCU_CR_DBG_STOPD2_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD2_Pos)  /*!< 0x00000010 */

+#define DBGMCU_CR_DBG_STOPD2              DBGMCU_CR_DBG_STOPD2_Msk

+#define DBGMCU_CR_DBG_STANDBYD2_Pos       (5U)

+#define DBGMCU_CR_DBG_STANDBYD2_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD2_Pos) /*!< 0x00000020 */

+#define DBGMCU_CR_DBG_STANDBYD2           DBGMCU_CR_DBG_STANDBYD2_Msk

+#define DBGMCU_CR_DBG_STOPD3_Pos          (7U)

+#define DBGMCU_CR_DBG_STOPD3_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos)  /*!< 0x00000080 */

+#define DBGMCU_CR_DBG_STOPD3              DBGMCU_CR_DBG_STOPD3_Msk

+#define DBGMCU_CR_DBG_STANDBYD3_Pos       (8U)

+#define DBGMCU_CR_DBG_STANDBYD3_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos) /*!< 0x00000100 */

+#define DBGMCU_CR_DBG_STANDBYD3           DBGMCU_CR_DBG_STANDBYD3_Msk

+#define DBGMCU_CR_DBG_TRACECKEN_Pos       (20U)

+#define DBGMCU_CR_DBG_TRACECKEN_Msk       (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */

+#define DBGMCU_CR_DBG_TRACECKEN           DBGMCU_CR_DBG_TRACECKEN_Msk

+#define DBGMCU_CR_DBG_CKD1EN_Pos          (21U)

+#define DBGMCU_CR_DBG_CKD1EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD1EN_Pos)  /*!< 0x00200000 */

+#define DBGMCU_CR_DBG_CKD1EN              DBGMCU_CR_DBG_CKD1EN_Msk

+#define DBGMCU_CR_DBG_CKD3EN_Pos          (22U)

+#define DBGMCU_CR_DBG_CKD3EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD3EN_Pos)  /*!< 0x00400000 */

+#define DBGMCU_CR_DBG_CKD3EN              DBGMCU_CR_DBG_CKD3EN_Msk

+#define DBGMCU_CR_DBG_TRGOEN_Pos          (28U)

+#define DBGMCU_CR_DBG_TRGOEN_Msk          (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)  /*!< 0x10000000 */

+#define DBGMCU_CR_DBG_TRGOEN              DBGMCU_CR_DBG_TRGOEN_Msk

+

+/********************  Bit definition for APB3FZ1 register  ************/

+#define DBGMCU_APB3FZ1_DBG_WWDG1_Pos      (6U)

+#define DBGMCU_APB3FZ1_DBG_WWDG1_Msk      (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB3FZ1_DBG_WWDG1          DBGMCU_APB3FZ1_DBG_WWDG1_Msk

+/********************  Bit definition for APB3FZ2 register  ************/

+#define DBGMCU_APB3FZ2_DBG_WWDG1_Pos      (6U)

+#define DBGMCU_APB3FZ2_DBG_WWDG1_Msk      (0x1UL << DBGMCU_APB3FZ2_DBG_WWDG1_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB3FZ2_DBG_WWDG1          DBGMCU_APB3FZ2_DBG_WWDG1_Msk

+/********************  Bit definition for APB1LFZ1 register  ************/

+#define DBGMCU_APB1LFZ1_DBG_TIM2_Pos      (0U)

+#define DBGMCU_APB1LFZ1_DBG_TIM2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB1LFZ1_DBG_TIM2          DBGMCU_APB1LFZ1_DBG_TIM2_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM3_Pos      (1U)

+#define DBGMCU_APB1LFZ1_DBG_TIM3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB1LFZ1_DBG_TIM3          DBGMCU_APB1LFZ1_DBG_TIM3_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM4_Pos      (2U)

+#define DBGMCU_APB1LFZ1_DBG_TIM4_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */

+#define DBGMCU_APB1LFZ1_DBG_TIM4          DBGMCU_APB1LFZ1_DBG_TIM4_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM5_Pos      (3U)

+#define DBGMCU_APB1LFZ1_DBG_TIM5_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */

+#define DBGMCU_APB1LFZ1_DBG_TIM5          DBGMCU_APB1LFZ1_DBG_TIM5_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM6_Pos      (4U)

+#define DBGMCU_APB1LFZ1_DBG_TIM6_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */

+#define DBGMCU_APB1LFZ1_DBG_TIM6          DBGMCU_APB1LFZ1_DBG_TIM6_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM7_Pos      (5U)

+#define DBGMCU_APB1LFZ1_DBG_TIM7_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */

+#define DBGMCU_APB1LFZ1_DBG_TIM7          DBGMCU_APB1LFZ1_DBG_TIM7_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM12_Pos     (6U)

+#define DBGMCU_APB1LFZ1_DBG_TIM12_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB1LFZ1_DBG_TIM12         DBGMCU_APB1LFZ1_DBG_TIM12_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM13_Pos     (7U)

+#define DBGMCU_APB1LFZ1_DBG_TIM13_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB1LFZ1_DBG_TIM13         DBGMCU_APB1LFZ1_DBG_TIM13_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM14_Pos     (8U)

+#define DBGMCU_APB1LFZ1_DBG_TIM14_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */

+#define DBGMCU_APB1LFZ1_DBG_TIM14         DBGMCU_APB1LFZ1_DBG_TIM14_Msk

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos    (9U)

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1        DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk

+#define DBGMCU_APB1LFZ1_DBG_WWDG2_Pos     (11U)

+#define DBGMCU_APB1LFZ1_DBG_WWDG2_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_WWDG2_Pos) /*!< 0x00000800 */

+#define DBGMCU_APB1LFZ1_DBG_WWDG2         DBGMCU_APB1LFZ1_DBG_WWDG2_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C1_Pos      (21U)

+#define DBGMCU_APB1LFZ1_DBG_I2C1_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C1          DBGMCU_APB1LFZ1_DBG_I2C1_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C2_Pos      (22U)

+#define DBGMCU_APB1LFZ1_DBG_I2C2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C2          DBGMCU_APB1LFZ1_DBG_I2C2_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C3_Pos      (23U)

+#define DBGMCU_APB1LFZ1_DBG_I2C3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C3          DBGMCU_APB1LFZ1_DBG_I2C3_Msk

+

+/********************  Bit definition for APB1LFZ2 register  ************/

+#define DBGMCU_APB1LFZ2_DBG_TIM2_Pos      (0U)

+#define DBGMCU_APB1LFZ2_DBG_TIM2_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM2_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB1LFZ2_DBG_TIM2          DBGMCU_APB1LFZ2_DBG_TIM2_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM3_Pos      (1U)

+#define DBGMCU_APB1LFZ2_DBG_TIM3_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM3_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB1LFZ2_DBG_TIM3          DBGMCU_APB1LFZ2_DBG_TIM3_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM4_Pos      (2U)

+#define DBGMCU_APB1LFZ2_DBG_TIM4_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM4_Pos) /*!< 0x00000004 */

+#define DBGMCU_APB1LFZ2_DBG_TIM4          DBGMCU_APB1LFZ2_DBG_TIM4_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM5_Pos      (3U)

+#define DBGMCU_APB1LFZ2_DBG_TIM5_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM5_Pos) /*!< 0x00000008 */

+#define DBGMCU_APB1LFZ2_DBG_TIM5          DBGMCU_APB1LFZ2_DBG_TIM5_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM6_Pos      (4U)

+#define DBGMCU_APB1LFZ2_DBG_TIM6_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM6_Pos) /*!< 0x00000010 */

+#define DBGMCU_APB1LFZ2_DBG_TIM6          DBGMCU_APB1LFZ2_DBG_TIM6_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM7_Pos      (5U)

+#define DBGMCU_APB1LFZ2_DBG_TIM7_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM7_Pos) /*!< 0x00000020 */

+#define DBGMCU_APB1LFZ2_DBG_TIM7          DBGMCU_APB1LFZ2_DBG_TIM7_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM12_Pos     (6U)

+#define DBGMCU_APB1LFZ2_DBG_TIM12_Msk     (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM12_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB1LFZ2_DBG_TIM12         DBGMCU_APB1LFZ2_DBG_TIM12_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM13_Pos     (7U)

+#define DBGMCU_APB1LFZ2_DBG_TIM13_Msk     (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM13_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB1LFZ2_DBG_TIM13         DBGMCU_APB1LFZ2_DBG_TIM13_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM14_Pos     (8U)

+#define DBGMCU_APB1LFZ2_DBG_TIM14_Msk     (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM14_Pos) /*!< 0x00000100 */

+#define DBGMCU_APB1LFZ2_DBG_TIM14         DBGMCU_APB1LFZ2_DBG_TIM14_Msk

+#define DBGMCU_APB1LFZ2_DBG_LPTIM1_Pos    (9U)

+#define DBGMCU_APB1LFZ2_DBG_LPTIM1_Msk    (0x1UL << DBGMCU_APB1LFZ2_DBG_LPTIM1_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB1LFZ2_DBG_LPTIM1        DBGMCU_APB1LFZ2_DBG_LPTIM1_Msk

+#define DBGMCU_APB1LFZ2_DBG_WWDG2_Pos     (11U)

+#define DBGMCU_APB1LFZ2_DBG_WWDG2_Msk     (0x1UL << DBGMCU_APB1LFZ2_DBG_WWDG2_Pos) /*!< 0x00000800 */

+#define DBGMCU_APB1LFZ2_DBG_WWDG2         DBGMCU_APB1LFZ2_DBG_WWDG2_Msk

+#define DBGMCU_APB1LFZ2_DBG_I2C1_Pos      (21U)

+#define DBGMCU_APB1LFZ2_DBG_I2C1_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C1_Pos) /*!< 0x00200000 */

+#define DBGMCU_APB1LFZ2_DBG_I2C1          DBGMCU_APB1LFZ2_DBG_I2C1_Msk

+#define DBGMCU_APB1LFZ2_DBG_I2C2_Pos      (22U)

+#define DBGMCU_APB1LFZ2_DBG_I2C2_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C2_Pos) /*!< 0x00400000 */

+#define DBGMCU_APB1LFZ2_DBG_I2C2          DBGMCU_APB1LFZ2_DBG_I2C2_Msk

+#define DBGMCU_APB1LFZ2_DBG_I2C3_Pos      (23U)

+#define DBGMCU_APB1LFZ2_DBG_I2C3_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C3_Pos) /*!< 0x00800000 */

+#define DBGMCU_APB1LFZ2_DBG_I2C3          DBGMCU_APB1LFZ2_DBG_I2C3_Msk

+/********************  Bit definition for APB1HFZ1 register  ************/

+#define DBGMCU_APB1HFZ1_DBG_FDCAN_Pos     (8U)

+#define DBGMCU_APB1HFZ1_DBG_FDCAN_Msk     (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_Pos) /*!< 0x00000100 */

+#define DBGMCU_APB1HFZ1_DBG_FDCAN         DBGMCU_APB1HFZ1_DBG_FDCAN_Msk

+/********************  Bit definition for APB1HFZ2 register  ************/

+#define DBGMCU_APB1HFZ2_DBG_FDCAN_Pos     (8U)

+#define DBGMCU_APB1HFZ2_DBG_FDCAN_Msk     (0x1UL << DBGMCU_APB1HFZ2_DBG_FDCAN_Pos) /*!< 0x00000100 */

+#define DBGMCU_APB1HFZ2_DBG_FDCAN         DBGMCU_APB1HFZ2_DBG_FDCAN_Msk

+

+/********************  Bit definition for APB2FZ1 register  ************/

+#define DBGMCU_APB2FZ1_DBG_TIM1_Pos       (0U)

+#define DBGMCU_APB2FZ1_DBG_TIM1_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB2FZ1_DBG_TIM1           DBGMCU_APB2FZ1_DBG_TIM1_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM8_Pos       (1U)

+#define DBGMCU_APB2FZ1_DBG_TIM8_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB2FZ1_DBG_TIM8           DBGMCU_APB2FZ1_DBG_TIM8_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM15_Pos      (16U)

+#define DBGMCU_APB2FZ1_DBG_TIM15_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB2FZ1_DBG_TIM15          DBGMCU_APB2FZ1_DBG_TIM15_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM16_Pos      (17U)

+#define DBGMCU_APB2FZ1_DBG_TIM16_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */

+#define DBGMCU_APB2FZ1_DBG_TIM16          DBGMCU_APB2FZ1_DBG_TIM16_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM17_Pos      (18U)

+#define DBGMCU_APB2FZ1_DBG_TIM17_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB2FZ1_DBG_TIM17          DBGMCU_APB2FZ1_DBG_TIM17_Msk

+#define DBGMCU_APB2FZ1_DBG_HRTIM_Pos      (29U)

+#define DBGMCU_APB2FZ1_DBG_HRTIM_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_HRTIM_Pos) /*!< 0x20000000 */

+#define DBGMCU_APB2FZ1_DBG_HRTIM          DBGMCU_APB2FZ1_DBG_HRTIM_Msk

+

+/********************  Bit definition for APB2FZ2 register  ************/

+#define DBGMCU_APB2FZ2_DBG_TIM1_Pos       (0U)

+#define DBGMCU_APB2FZ2_DBG_TIM1_Msk       (0x1UL << DBGMCU_APB2FZ2_DBG_TIM1_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB2FZ2_DBG_TIM1           DBGMCU_APB2FZ2_DBG_TIM1_Msk

+#define DBGMCU_APB2FZ2_DBG_TIM8_Pos       (1U)

+#define DBGMCU_APB2FZ2_DBG_TIM8_Msk       (0x1UL << DBGMCU_APB2FZ2_DBG_TIM8_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB2FZ2_DBG_TIM8           DBGMCU_APB2FZ2_DBG_TIM8_Msk

+#define DBGMCU_APB2FZ2_DBG_TIM15_Pos      (16U)

+#define DBGMCU_APB2FZ2_DBG_TIM15_Msk      (0x1UL << DBGMCU_APB2FZ2_DBG_TIM15_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB2FZ2_DBG_TIM15          DBGMCU_APB2FZ2_DBG_TIM15_Msk

+#define DBGMCU_APB2FZ2_DBG_TIM16_Pos      (17U)

+#define DBGMCU_APB2FZ2_DBG_TIM16_Msk      (0x1UL << DBGMCU_APB2FZ2_DBG_TIM16_Pos) /*!< 0x00020000 */

+#define DBGMCU_APB2FZ2_DBG_TIM16          DBGMCU_APB2FZ2_DBG_TIM16_Msk

+#define DBGMCU_APB2FZ2_DBG_TIM17_Pos      (18U)

+#define DBGMCU_APB2FZ2_DBG_TIM17_Msk      (0x1UL << DBGMCU_APB2FZ2_DBG_TIM17_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB2FZ2_DBG_TIM17          DBGMCU_APB2FZ2_DBG_TIM17_Msk

+#define DBGMCU_APB2FZ2_DBG_HRTIM_Pos      (29U)

+#define DBGMCU_APB2FZ2_DBG_HRTIM_Msk      (0x1UL << DBGMCU_APB2FZ2_DBG_HRTIM_Pos) /*!< 0x20000000 */

+#define DBGMCU_APB2FZ2_DBG_HRTIM          DBGMCU_APB2FZ2_DBG_HRTIM_Msk

+/********************  Bit definition for APB4FZ1 register  ************/

+#define DBGMCU_APB4FZ1_DBG_I2C4_Pos       (7U)

+#define DBGMCU_APB4FZ1_DBG_I2C4_Msk       (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB4FZ1_DBG_I2C4           DBGMCU_APB4FZ1_DBG_I2C4_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos     (9U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM2         DBGMCU_APB4FZ1_DBG_LPTIM2_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos     (10U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM3         DBGMCU_APB4FZ1_DBG_LPTIM3_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM4_Pos     (11U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM4_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos) /*!< 0x00000800 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM4         DBGMCU_APB4FZ1_DBG_LPTIM4_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM5_Pos     (12U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM5_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos) /*!< 0x00001000 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM5         DBGMCU_APB4FZ1_DBG_LPTIM5_Msk

+#define DBGMCU_APB4FZ1_DBG_RTC_Pos        (16U)

+#define DBGMCU_APB4FZ1_DBG_RTC_Msk        (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB4FZ1_DBG_RTC            DBGMCU_APB4FZ1_DBG_RTC_Msk

+#define DBGMCU_APB4FZ1_DBG_IWDG1_Pos      (18U)

+#define DBGMCU_APB4FZ1_DBG_IWDG1_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB4FZ1_DBG_IWDG1          DBGMCU_APB4FZ1_DBG_IWDG1_Msk

+#define DBGMCU_APB4FZ1_DBG_IWDG2_Pos      (19U)

+#define DBGMCU_APB4FZ1_DBG_IWDG2_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG2_Pos) /*!< 0x00080000 */

+#define DBGMCU_APB4FZ1_DBG_IWDG2          DBGMCU_APB4FZ1_DBG_IWDG2_Msk

+/********************  Bit definition for APB4FZ2 register  ************/

+#define DBGMCU_APB4FZ2_DBG_I2C4_Pos       (7U)

+#define DBGMCU_APB4FZ2_DBG_I2C4_Msk       (0x1UL << DBGMCU_APB4FZ2_DBG_I2C4_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB4FZ2_DBG_I2C4           DBGMCU_APB4FZ2_DBG_I2C4_Msk

+#define DBGMCU_APB4FZ2_DBG_LPTIM2_Pos     (9U)

+#define DBGMCU_APB4FZ2_DBG_LPTIM2_Msk     (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM2_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB4FZ2_DBG_LPTIM2         DBGMCU_APB4FZ2_DBG_LPTIM2_Msk

+#define DBGMCU_APB4FZ2_DBG_LPTIM3_Pos     (10U)

+#define DBGMCU_APB4FZ2_DBG_LPTIM3_Msk     (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM3_Pos) /*!< 0x00000400 */

+#define DBGMCU_APB4FZ2_DBG_LPTIM3         DBGMCU_APB4FZ2_DBG_LPTIM3_Msk

+#define DBGMCU_APB4FZ2_DBG_LPTIM4_Pos     (11U)

+#define DBGMCU_APB4FZ2_DBG_LPTIM4_Msk     (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM4_Pos) /*!< 0x00000800 */

+#define DBGMCU_APB4FZ2_DBG_LPTIM4         DBGMCU_APB4FZ2_DBG_LPTIM4_Msk

+#define DBGMCU_APB4FZ2_DBG_LPTIM5_Pos     (12U)

+#define DBGMCU_APB4FZ2_DBG_LPTIM5_Msk     (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM5_Pos) /*!< 0x00001000 */

+#define DBGMCU_APB4FZ2_DBG_LPTIM5         DBGMCU_APB4FZ2_DBG_LPTIM5_Msk

+#define DBGMCU_APB4FZ2_DBG_RTC_Pos        (16U)

+#define DBGMCU_APB4FZ2_DBG_RTC_Msk        (0x1UL << DBGMCU_APB4FZ2_DBG_RTC_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB4FZ2_DBG_RTC            DBGMCU_APB4FZ2_DBG_RTC_Msk

+#define DBGMCU_APB4FZ2_DBG_IWDG1_Pos      (18U)

+#define DBGMCU_APB4FZ2_DBG_IWDG1_Msk      (0x1UL << DBGMCU_APB4FZ2_DBG_IWDG1_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB4FZ2_DBG_IWDG1          DBGMCU_APB4FZ2_DBG_IWDG1_Msk

+#define DBGMCU_APB4FZ2_DBG_IWDG2_Pos      (19U)

+#define DBGMCU_APB4FZ2_DBG_IWDG2_Msk      (0x1UL << DBGMCU_APB4FZ2_DBG_IWDG2_Pos) /*!< 0x00080000 */

+#define DBGMCU_APB4FZ2_DBG_IWDG2          DBGMCU_APB4FZ2_DBG_IWDG2_Msk

+/******************************************************************************/

+/*                                                                            */

+/*                        High Resolution Timer (HRTIM)                       */

+/*                                                                            */

+/******************************************************************************/

+/******************** Master Timer control register ***************************/

+#define HRTIM_MCR_CK_PSC_Pos          (0U)

+#define HRTIM_MCR_CK_PSC_Msk          (0x7UL << HRTIM_MCR_CK_PSC_Pos)          /*!< 0x00000007 */

+#define HRTIM_MCR_CK_PSC              HRTIM_MCR_CK_PSC_Msk                     /*!< Prescaler mask */

+#define HRTIM_MCR_CK_PSC_0            (0x1UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000001 */

+#define HRTIM_MCR_CK_PSC_1            (0x2UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000002 */

+#define HRTIM_MCR_CK_PSC_2            (0x4UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000004 */

+

+#define HRTIM_MCR_CONT_Pos            (3U)

+#define HRTIM_MCR_CONT_Msk            (0x1UL << HRTIM_MCR_CONT_Pos)            /*!< 0x00000008 */

+#define HRTIM_MCR_CONT                HRTIM_MCR_CONT_Msk                       /*!< Continuous mode */

+#define HRTIM_MCR_RETRIG_Pos          (4U)

+#define HRTIM_MCR_RETRIG_Msk          (0x1UL << HRTIM_MCR_RETRIG_Pos)          /*!< 0x00000010 */

+#define HRTIM_MCR_RETRIG              HRTIM_MCR_RETRIG_Msk                     /*!< Rettrigreable mode */

+#define HRTIM_MCR_HALF_Pos            (5U)

+#define HRTIM_MCR_HALF_Msk            (0x1UL << HRTIM_MCR_HALF_Pos)            /*!< 0x00000020 */

+#define HRTIM_MCR_HALF                HRTIM_MCR_HALF_Msk                       /*!< Half mode */

+

+#define HRTIM_MCR_SYNC_IN_Pos         (8U)

+#define HRTIM_MCR_SYNC_IN_Msk         (0x3UL << HRTIM_MCR_SYNC_IN_Pos)         /*!< 0x00000300 */

+#define HRTIM_MCR_SYNC_IN             HRTIM_MCR_SYNC_IN_Msk                    /*!< Synchronization input master */

+#define HRTIM_MCR_SYNC_IN_0           (0x1UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000100 */

+#define HRTIM_MCR_SYNC_IN_1           (0x2UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000200 */

+#define HRTIM_MCR_SYNCRSTM_Pos        (10U)

+#define HRTIM_MCR_SYNCRSTM_Msk        (0x1UL << HRTIM_MCR_SYNCRSTM_Pos)        /*!< 0x00000400 */

+#define HRTIM_MCR_SYNCRSTM            HRTIM_MCR_SYNCRSTM_Msk                   /*!< Synchronization reset master */

+#define HRTIM_MCR_SYNCSTRTM_Pos       (11U)

+#define HRTIM_MCR_SYNCSTRTM_Msk       (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos)       /*!< 0x00000800 */

+#define HRTIM_MCR_SYNCSTRTM           HRTIM_MCR_SYNCSTRTM_Msk                  /*!< Synchronization start master */

+#define HRTIM_MCR_SYNC_OUT_Pos        (12U)

+#define HRTIM_MCR_SYNC_OUT_Msk        (0x3UL << HRTIM_MCR_SYNC_OUT_Pos)        /*!< 0x00003000 */

+#define HRTIM_MCR_SYNC_OUT            HRTIM_MCR_SYNC_OUT_Msk                   /*!< Synchronization output master */

+#define HRTIM_MCR_SYNC_OUT_0          (0x1UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00001000 */

+#define HRTIM_MCR_SYNC_OUT_1          (0x2UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00002000 */

+#define HRTIM_MCR_SYNC_SRC_Pos        (14U)

+#define HRTIM_MCR_SYNC_SRC_Msk        (0x3UL << HRTIM_MCR_SYNC_SRC_Pos)        /*!< 0x0000C000 */

+#define HRTIM_MCR_SYNC_SRC            HRTIM_MCR_SYNC_SRC_Msk                   /*!< Synchronization source */

+#define HRTIM_MCR_SYNC_SRC_0          (0x1UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00004000 */

+#define HRTIM_MCR_SYNC_SRC_1          (0x2UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00008000 */

+

+#define HRTIM_MCR_MCEN_Pos            (16U)

+#define HRTIM_MCR_MCEN_Msk            (0x1UL << HRTIM_MCR_MCEN_Pos)            /*!< 0x00010000 */

+#define HRTIM_MCR_MCEN                HRTIM_MCR_MCEN_Msk                       /*!< Master counter enable */

+#define HRTIM_MCR_TACEN_Pos           (17U)

+#define HRTIM_MCR_TACEN_Msk           (0x1UL << HRTIM_MCR_TACEN_Pos)           /*!< 0x00020000 */

+#define HRTIM_MCR_TACEN               HRTIM_MCR_TACEN_Msk                      /*!< Timer A counter enable */

+#define HRTIM_MCR_TBCEN_Pos           (18U)

+#define HRTIM_MCR_TBCEN_Msk           (0x1UL << HRTIM_MCR_TBCEN_Pos)           /*!< 0x00040000 */

+#define HRTIM_MCR_TBCEN               HRTIM_MCR_TBCEN_Msk                      /*!< Timer B counter enable */

+#define HRTIM_MCR_TCCEN_Pos           (19U)

+#define HRTIM_MCR_TCCEN_Msk           (0x1UL << HRTIM_MCR_TCCEN_Pos)           /*!< 0x00080000 */

+#define HRTIM_MCR_TCCEN               HRTIM_MCR_TCCEN_Msk                      /*!< Timer C counter enable */

+#define HRTIM_MCR_TDCEN_Pos           (20U)

+#define HRTIM_MCR_TDCEN_Msk           (0x1UL << HRTIM_MCR_TDCEN_Pos)           /*!< 0x00100000 */

+#define HRTIM_MCR_TDCEN               HRTIM_MCR_TDCEN_Msk                      /*!< Timer D counter enable */

+#define HRTIM_MCR_TECEN_Pos           (21U)

+#define HRTIM_MCR_TECEN_Msk           (0x1UL << HRTIM_MCR_TECEN_Pos)           /*!< 0x00200000 */

+#define HRTIM_MCR_TECEN               HRTIM_MCR_TECEN_Msk                      /*!< Timer E counter enable */

+

+#define HRTIM_MCR_DACSYNC_Pos         (25U)

+#define HRTIM_MCR_DACSYNC_Msk         (0x3UL << HRTIM_MCR_DACSYNC_Pos)         /*!< 0x06000000 */

+#define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC sychronization mask */

+#define HRTIM_MCR_DACSYNC_0           (0x1UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x02000000 */

+#define HRTIM_MCR_DACSYNC_1           (0x2UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x04000000 */

+

+#define HRTIM_MCR_PREEN_Pos           (27U)

+#define HRTIM_MCR_PREEN_Msk           (0x1UL << HRTIM_MCR_PREEN_Pos)           /*!< 0x08000000 */

+#define HRTIM_MCR_PREEN               HRTIM_MCR_PREEN_Msk                      /*!< Master preload enable */

+#define HRTIM_MCR_MREPU_Pos           (29U)

+#define HRTIM_MCR_MREPU_Msk           (0x1UL << HRTIM_MCR_MREPU_Pos)           /*!< 0x20000000 */

+#define HRTIM_MCR_MREPU               HRTIM_MCR_MREPU_Msk                      /*!< Master repetition update */

+

+#define HRTIM_MCR_BRSTDMA_Pos         (30U)

+#define HRTIM_MCR_BRSTDMA_Msk         (0x3UL << HRTIM_MCR_BRSTDMA_Pos)         /*!< 0xC0000000 */

+#define HRTIM_MCR_BRSTDMA             HRTIM_MCR_BRSTDMA_Msk                    /*!< Burst DMA update */

+#define HRTIM_MCR_BRSTDMA_0           (0x1UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x40000000 */

+#define HRTIM_MCR_BRSTDMA_1           (0x2UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x80000000 */

+

+/******************** Master Timer Interrupt status register ******************/

+#define HRTIM_MISR_MCMP1_Pos          (0U)

+#define HRTIM_MISR_MCMP1_Msk          (0x1UL << HRTIM_MISR_MCMP1_Pos)          /*!< 0x00000001 */

+#define HRTIM_MISR_MCMP1              HRTIM_MISR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag */

+#define HRTIM_MISR_MCMP2_Pos          (1U)

+#define HRTIM_MISR_MCMP2_Msk          (0x1UL << HRTIM_MISR_MCMP2_Pos)          /*!< 0x00000002 */

+#define HRTIM_MISR_MCMP2              HRTIM_MISR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag */

+#define HRTIM_MISR_MCMP3_Pos          (2U)

+#define HRTIM_MISR_MCMP3_Msk          (0x1UL << HRTIM_MISR_MCMP3_Pos)          /*!< 0x00000004 */

+#define HRTIM_MISR_MCMP3              HRTIM_MISR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag */

+#define HRTIM_MISR_MCMP4_Pos          (3U)

+#define HRTIM_MISR_MCMP4_Msk          (0x1UL << HRTIM_MISR_MCMP4_Pos)          /*!< 0x00000008 */

+#define HRTIM_MISR_MCMP4              HRTIM_MISR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag */

+#define HRTIM_MISR_MREP_Pos           (4U)

+#define HRTIM_MISR_MREP_Msk           (0x1UL << HRTIM_MISR_MREP_Pos)           /*!< 0x00000010 */

+#define HRTIM_MISR_MREP               HRTIM_MISR_MREP_Msk                      /*!< Master Repetition interrupt flag */

+#define HRTIM_MISR_SYNC_Pos           (5U)

+#define HRTIM_MISR_SYNC_Msk           (0x1UL << HRTIM_MISR_SYNC_Pos)           /*!< 0x00000020 */

+#define HRTIM_MISR_SYNC               HRTIM_MISR_SYNC_Msk                      /*!< Synchronization input interrupt flag */

+#define HRTIM_MISR_MUPD_Pos           (6U)

+#define HRTIM_MISR_MUPD_Msk           (0x1UL << HRTIM_MISR_MUPD_Pos)           /*!< 0x00000040 */

+#define HRTIM_MISR_MUPD               HRTIM_MISR_MUPD_Msk                      /*!< Master update interrupt flag */

+

+/******************** Master Timer Interrupt clear register *******************/

+#define HRTIM_MICR_MCMP1_Pos          (0U)

+#define HRTIM_MICR_MCMP1_Msk          (0x1UL << HRTIM_MICR_MCMP1_Pos)          /*!< 0x00000001 */

+#define HRTIM_MICR_MCMP1              HRTIM_MICR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag clear */

+#define HRTIM_MICR_MCMP2_Pos          (1U)

+#define HRTIM_MICR_MCMP2_Msk          (0x1UL << HRTIM_MICR_MCMP2_Pos)          /*!< 0x00000002 */

+#define HRTIM_MICR_MCMP2              HRTIM_MICR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag clear */

+#define HRTIM_MICR_MCMP3_Pos          (2U)

+#define HRTIM_MICR_MCMP3_Msk          (0x1UL << HRTIM_MICR_MCMP3_Pos)          /*!< 0x00000004 */

+#define HRTIM_MICR_MCMP3              HRTIM_MICR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag clear */

+#define HRTIM_MICR_MCMP4_Pos          (3U)

+#define HRTIM_MICR_MCMP4_Msk          (0x1UL << HRTIM_MICR_MCMP4_Pos)          /*!< 0x00000008 */

+#define HRTIM_MICR_MCMP4              HRTIM_MICR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag clear */

+#define HRTIM_MICR_MREP_Pos           (4U)

+#define HRTIM_MICR_MREP_Msk           (0x1UL << HRTIM_MICR_MREP_Pos)           /*!< 0x00000010 */

+#define HRTIM_MICR_MREP               HRTIM_MICR_MREP_Msk                      /*!< Master Repetition interrupt flag clear */

+#define HRTIM_MICR_SYNC_Pos           (5U)

+#define HRTIM_MICR_SYNC_Msk           (0x1UL << HRTIM_MICR_SYNC_Pos)           /*!< 0x00000020 */

+#define HRTIM_MICR_SYNC               HRTIM_MICR_SYNC_Msk                      /*!< Synchronization input interrupt flag clear */

+#define HRTIM_MICR_MUPD_Pos           (6U)

+#define HRTIM_MICR_MUPD_Msk           (0x1UL << HRTIM_MICR_MUPD_Pos)           /*!< 0x00000040 */

+#define HRTIM_MICR_MUPD               HRTIM_MICR_MUPD_Msk                      /*!< Master update interrupt flag clear */

+

+/******************** Master Timer DMA/Interrupt enable register **************/

+#define HRTIM_MDIER_MCMP1IE_Pos       (0U)

+#define HRTIM_MDIER_MCMP1IE_Msk       (0x1UL << HRTIM_MDIER_MCMP1IE_Pos)       /*!< 0x00000001 */

+#define HRTIM_MDIER_MCMP1IE           HRTIM_MDIER_MCMP1IE_Msk                  /*!< Master compare 1 interrupt enable */

+#define HRTIM_MDIER_MCMP2IE_Pos       (1U)

+#define HRTIM_MDIER_MCMP2IE_Msk       (0x1UL << HRTIM_MDIER_MCMP2IE_Pos)       /*!< 0x00000002 */

+#define HRTIM_MDIER_MCMP2IE           HRTIM_MDIER_MCMP2IE_Msk                  /*!< Master compare 2 interrupt enable */

+#define HRTIM_MDIER_MCMP3IE_Pos       (2U)

+#define HRTIM_MDIER_MCMP3IE_Msk       (0x1UL << HRTIM_MDIER_MCMP3IE_Pos)       /*!< 0x00000004 */

+#define HRTIM_MDIER_MCMP3IE           HRTIM_MDIER_MCMP3IE_Msk                  /*!< Master compare 3 interrupt enable */

+#define HRTIM_MDIER_MCMP4IE_Pos       (3U)

+#define HRTIM_MDIER_MCMP4IE_Msk       (0x1UL << HRTIM_MDIER_MCMP4IE_Pos)       /*!< 0x00000008 */

+#define HRTIM_MDIER_MCMP4IE           HRTIM_MDIER_MCMP4IE_Msk                  /*!< Master compare 4 interrupt enable */

+#define HRTIM_MDIER_MREPIE_Pos        (4U)

+#define HRTIM_MDIER_MREPIE_Msk        (0x1UL << HRTIM_MDIER_MREPIE_Pos)        /*!< 0x00000010 */

+#define HRTIM_MDIER_MREPIE            HRTIM_MDIER_MREPIE_Msk                   /*!< Master Repetition interrupt enable */

+#define HRTIM_MDIER_SYNCIE_Pos        (5U)

+#define HRTIM_MDIER_SYNCIE_Msk        (0x1UL << HRTIM_MDIER_SYNCIE_Pos)        /*!< 0x00000020 */

+#define HRTIM_MDIER_SYNCIE            HRTIM_MDIER_SYNCIE_Msk                   /*!< Synchronization input interrupt enable */

+#define HRTIM_MDIER_MUPDIE_Pos        (6U)

+#define HRTIM_MDIER_MUPDIE_Msk        (0x1UL << HRTIM_MDIER_MUPDIE_Pos)        /*!< 0x00000040 */

+#define HRTIM_MDIER_MUPDIE            HRTIM_MDIER_MUPDIE_Msk                   /*!< Master update interrupt enable */

+

+#define HRTIM_MDIER_MCMP1DE_Pos       (16U)

+#define HRTIM_MDIER_MCMP1DE_Msk       (0x1UL << HRTIM_MDIER_MCMP1DE_Pos)       /*!< 0x00010000 */

+#define HRTIM_MDIER_MCMP1DE           HRTIM_MDIER_MCMP1DE_Msk                  /*!< Master compare 1 DMA enable */

+#define HRTIM_MDIER_MCMP2DE_Pos       (17U)

+#define HRTIM_MDIER_MCMP2DE_Msk       (0x1UL << HRTIM_MDIER_MCMP2DE_Pos)       /*!< 0x00020000 */

+#define HRTIM_MDIER_MCMP2DE           HRTIM_MDIER_MCMP2DE_Msk                  /*!< Master compare 2 DMA enable */

+#define HRTIM_MDIER_MCMP3DE_Pos       (18U)

+#define HRTIM_MDIER_MCMP3DE_Msk       (0x1UL << HRTIM_MDIER_MCMP3DE_Pos)       /*!< 0x00040000 */

+#define HRTIM_MDIER_MCMP3DE           HRTIM_MDIER_MCMP3DE_Msk                  /*!< Master compare 3 DMA enable */

+#define HRTIM_MDIER_MCMP4DE_Pos       (19U)

+#define HRTIM_MDIER_MCMP4DE_Msk       (0x1UL << HRTIM_MDIER_MCMP4DE_Pos)       /*!< 0x00080000 */

+#define HRTIM_MDIER_MCMP4DE           HRTIM_MDIER_MCMP4DE_Msk                  /*!< Master compare 4 DMA enable */

+#define HRTIM_MDIER_MREPDE_Pos        (20U)

+#define HRTIM_MDIER_MREPDE_Msk        (0x1UL << HRTIM_MDIER_MREPDE_Pos)        /*!< 0x00100000 */

+#define HRTIM_MDIER_MREPDE            HRTIM_MDIER_MREPDE_Msk                   /*!< Master Repetition DMA enable */

+#define HRTIM_MDIER_SYNCDE_Pos        (21U)

+#define HRTIM_MDIER_SYNCDE_Msk        (0x1UL << HRTIM_MDIER_SYNCDE_Pos)        /*!< 0x00200000 */

+#define HRTIM_MDIER_SYNCDE            HRTIM_MDIER_SYNCDE_Msk                   /*!< Synchronization input DMA enable */

+#define HRTIM_MDIER_MUPDDE_Pos        (22U)

+#define HRTIM_MDIER_MUPDDE_Msk        (0x1UL << HRTIM_MDIER_MUPDDE_Pos)        /*!< 0x00400000 */

+#define HRTIM_MDIER_MUPDDE            HRTIM_MDIER_MUPDDE_Msk                   /*!< Master update DMA enable */

+

+/*******************  Bit definition for HRTIM_MCNTR register  ****************/

+#define HRTIM_MCNTR_MCNTR_Pos         (0U)

+#define HRTIM_MCNTR_MCNTR_Msk         (0xFFFFUL << HRTIM_MCNTR_MCNTR_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_MCNTR_MCNTR             HRTIM_MCNTR_MCNTR_Msk                    /*!<Counter Value */

+

+/*******************  Bit definition for HRTIM_MPER register  *****************/

+#define HRTIM_MPER_MPER_Pos           (0U)

+#define HRTIM_MPER_MPER_Msk           (0xFFFFUL << HRTIM_MPER_MPER_Pos)        /*!< 0x0000FFFF */

+#define HRTIM_MPER_MPER               HRTIM_MPER_MPER_Msk                      /*!< Period Value */

+

+/*******************  Bit definition for HRTIM_MREP register  *****************/

+#define HRTIM_MREP_MREP_Pos           (0U)

+#define HRTIM_MREP_MREP_Msk           (0xFFUL << HRTIM_MREP_MREP_Pos)          /*!< 0x000000FF */

+#define HRTIM_MREP_MREP               HRTIM_MREP_MREP_Msk                      /*!<Repetition Value */

+

+/*******************  Bit definition for HRTIM_MCMP1R register  *****************/

+#define HRTIM_MCMP1R_MCMP1R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP1R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP1R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP1R           HRTIM_MCMP1R_MCMP1R_Msk                  /*!<Compare Value */

+

+/*******************  Bit definition for HRTIM_MCMP2R register  *****************/

+#define HRTIM_MCMP1R_MCMP2R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP2R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP2R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP2R           HRTIM_MCMP1R_MCMP2R_Msk                  /*!<Compare Value */

+

+/*******************  Bit definition for HRTIM_MCMP3R register  *****************/

+#define HRTIM_MCMP1R_MCMP3R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP3R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP3R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP3R           HRTIM_MCMP1R_MCMP3R_Msk                  /*!<Compare Value */

+

+/*******************  Bit definition for HRTIM_MCMP4R register  *****************/

+#define HRTIM_MCMP1R_MCMP4R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP4R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP4R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP4R           HRTIM_MCMP1R_MCMP4R_Msk                  /*!<Compare Value */

+

+/******************** Slave control register **********************************/

+#define HRTIM_TIMCR_CK_PSC_Pos        (0U)

+#define HRTIM_TIMCR_CK_PSC_Msk        (0x7UL << HRTIM_TIMCR_CK_PSC_Pos)        /*!< 0x00000007 */

+#define HRTIM_TIMCR_CK_PSC            HRTIM_TIMCR_CK_PSC_Msk                   /*!< Slave prescaler mask*/

+#define HRTIM_TIMCR_CK_PSC_0          (0x1UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000001 */

+#define HRTIM_TIMCR_CK_PSC_1          (0x2UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000002 */

+#define HRTIM_TIMCR_CK_PSC_2          (0x4UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000004 */

+

+#define HRTIM_TIMCR_CONT_Pos          (3U)

+#define HRTIM_TIMCR_CONT_Msk          (0x1UL << HRTIM_TIMCR_CONT_Pos)          /*!< 0x00000008 */

+#define HRTIM_TIMCR_CONT              HRTIM_TIMCR_CONT_Msk                     /*!< Slave continuous mode */

+#define HRTIM_TIMCR_RETRIG_Pos        (4U)

+#define HRTIM_TIMCR_RETRIG_Msk        (0x1UL << HRTIM_TIMCR_RETRIG_Pos)        /*!< 0x00000010 */

+#define HRTIM_TIMCR_RETRIG            HRTIM_TIMCR_RETRIG_Msk                   /*!< Slave Retrigreable mode */

+#define HRTIM_TIMCR_HALF_Pos          (5U)

+#define HRTIM_TIMCR_HALF_Msk          (0x1UL << HRTIM_TIMCR_HALF_Pos)          /*!< 0x00000020 */

+#define HRTIM_TIMCR_HALF              HRTIM_TIMCR_HALF_Msk                     /*!< Slave Half mode */

+#define HRTIM_TIMCR_PSHPLL_Pos        (6U)

+#define HRTIM_TIMCR_PSHPLL_Msk        (0x1UL << HRTIM_TIMCR_PSHPLL_Pos)        /*!< 0x00000040 */

+#define HRTIM_TIMCR_PSHPLL            HRTIM_TIMCR_PSHPLL_Msk                   /*!< Slave push-pull mode */

+

+#define HRTIM_TIMCR_SYNCRST_Pos       (10U)

+#define HRTIM_TIMCR_SYNCRST_Msk       (0x1UL << HRTIM_TIMCR_SYNCRST_Pos)       /*!< 0x00000400 */

+#define HRTIM_TIMCR_SYNCRST           HRTIM_TIMCR_SYNCRST_Msk                  /*!< Slave synchronization resets */

+#define HRTIM_TIMCR_SYNCSTRT_Pos      (11U)

+#define HRTIM_TIMCR_SYNCSTRT_Msk      (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos)      /*!< 0x00000800 */

+#define HRTIM_TIMCR_SYNCSTRT          HRTIM_TIMCR_SYNCSTRT_Msk                 /*!< Slave synchronization starts */

+

+#define HRTIM_TIMCR_DELCMP2_Pos       (12U)

+#define HRTIM_TIMCR_DELCMP2_Msk       (0x3UL << HRTIM_TIMCR_DELCMP2_Pos)       /*!< 0x00003000 */

+#define HRTIM_TIMCR_DELCMP2           HRTIM_TIMCR_DELCMP2_Msk                  /*!< Slave delayed compartor 2 mode mask */

+#define HRTIM_TIMCR_DELCMP2_0         (0x1UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00001000 */

+#define HRTIM_TIMCR_DELCMP2_1         (0x2UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00002000 */

+#define HRTIM_TIMCR_DELCMP4_Pos       (14U)

+#define HRTIM_TIMCR_DELCMP4_Msk       (0x3UL << HRTIM_TIMCR_DELCMP4_Pos)       /*!< 0x0000C000 */

+#define HRTIM_TIMCR_DELCMP4           HRTIM_TIMCR_DELCMP4_Msk                  /*!< Slave delayed compartor 4 mode mask */

+#define HRTIM_TIMCR_DELCMP4_0         (0x1UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00004000 */

+#define HRTIM_TIMCR_DELCMP4_1         (0x2UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00008000 */

+

+#define HRTIM_TIMCR_TREPU_Pos         (17U)

+#define HRTIM_TIMCR_TREPU_Msk         (0x1UL << HRTIM_TIMCR_TREPU_Pos)         /*!< 0x00020000 */

+#define HRTIM_TIMCR_TREPU             HRTIM_TIMCR_TREPU_Msk                    /*!< Slave repetition update */

+#define HRTIM_TIMCR_TRSTU_Pos         (18U)

+#define HRTIM_TIMCR_TRSTU_Msk         (0x1UL << HRTIM_TIMCR_TRSTU_Pos)         /*!< 0x00040000 */

+#define HRTIM_TIMCR_TRSTU             HRTIM_TIMCR_TRSTU_Msk                    /*!< Slave reset update */

+#define HRTIM_TIMCR_TAU_Pos           (19U)

+#define HRTIM_TIMCR_TAU_Msk           (0x1UL << HRTIM_TIMCR_TAU_Pos)           /*!< 0x00080000 */

+#define HRTIM_TIMCR_TAU               HRTIM_TIMCR_TAU_Msk                      /*!< Slave Timer A update reserved for TIM A */

+#define HRTIM_TIMCR_TBU_Pos           (20U)

+#define HRTIM_TIMCR_TBU_Msk           (0x1UL << HRTIM_TIMCR_TBU_Pos)           /*!< 0x00100000 */

+#define HRTIM_TIMCR_TBU               HRTIM_TIMCR_TBU_Msk                      /*!< Slave Timer B update reserved for TIM B */

+#define HRTIM_TIMCR_TCU_Pos           (21U)

+#define HRTIM_TIMCR_TCU_Msk           (0x1UL << HRTIM_TIMCR_TCU_Pos)           /*!< 0x00200000 */

+#define HRTIM_TIMCR_TCU               HRTIM_TIMCR_TCU_Msk                      /*!< Slave Timer C update reserved for TIM C */

+#define HRTIM_TIMCR_TDU_Pos           (22U)

+#define HRTIM_TIMCR_TDU_Msk           (0x1UL << HRTIM_TIMCR_TDU_Pos)           /*!< 0x00400000 */

+#define HRTIM_TIMCR_TDU               HRTIM_TIMCR_TDU_Msk                      /*!< Slave Timer D update reserved for TIM D */

+#define HRTIM_TIMCR_TEU_Pos           (23U)

+#define HRTIM_TIMCR_TEU_Msk           (0x1UL << HRTIM_TIMCR_TEU_Pos)           /*!< 0x00800000 */

+#define HRTIM_TIMCR_TEU               HRTIM_TIMCR_TEU_Msk                      /*!< Slave Timer E update reserved for TIM E */

+#define HRTIM_TIMCR_MSTU_Pos          (24U)

+#define HRTIM_TIMCR_MSTU_Msk          (0x1UL << HRTIM_TIMCR_MSTU_Pos)          /*!< 0x01000000 */

+#define HRTIM_TIMCR_MSTU              HRTIM_TIMCR_MSTU_Msk                     /*!< Master Update */

+

+#define HRTIM_TIMCR_DACSYNC_Pos       (25U)

+#define HRTIM_TIMCR_DACSYNC_Msk       (0x3UL << HRTIM_TIMCR_DACSYNC_Pos)       /*!< 0x06000000 */

+#define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC sychronization mask */

+#define HRTIM_TIMCR_DACSYNC_0         (0x1UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x02000000 */

+#define HRTIM_TIMCR_DACSYNC_1         (0x2UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x04000000 */

+#define HRTIM_TIMCR_PREEN_Pos         (27U)

+#define HRTIM_TIMCR_PREEN_Msk         (0x1UL << HRTIM_TIMCR_PREEN_Pos)         /*!< 0x08000000 */

+#define HRTIM_TIMCR_PREEN             HRTIM_TIMCR_PREEN_Msk                    /*!< Slave preload enable */

+

+#define HRTIM_TIMCR_UPDGAT_Pos        (28U)

+#define HRTIM_TIMCR_UPDGAT_Msk        (0xFUL << HRTIM_TIMCR_UPDGAT_Pos)        /*!< 0xF0000000 */

+#define HRTIM_TIMCR_UPDGAT            HRTIM_TIMCR_UPDGAT_Msk                   /*!< Slave update gating mask */

+#define HRTIM_TIMCR_UPDGAT_0          (0x1UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x10000000 */

+#define HRTIM_TIMCR_UPDGAT_1          (0x2UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x20000000 */

+#define HRTIM_TIMCR_UPDGAT_2          (0x4UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x40000000 */

+#define HRTIM_TIMCR_UPDGAT_3          (0x8UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x80000000 */

+

+/******************** Slave Interrupt status register **************************/

+#define HRTIM_TIMISR_CMP1_Pos         (0U)

+#define HRTIM_TIMISR_CMP1_Msk         (0x1UL << HRTIM_TIMISR_CMP1_Pos)         /*!< 0x00000001 */

+#define HRTIM_TIMISR_CMP1             HRTIM_TIMISR_CMP1_Msk                    /*!< Slave compare 1 interrupt flag */

+#define HRTIM_TIMISR_CMP2_Pos         (1U)

+#define HRTIM_TIMISR_CMP2_Msk         (0x1UL << HRTIM_TIMISR_CMP2_Pos)         /*!< 0x00000002 */

+#define HRTIM_TIMISR_CMP2             HRTIM_TIMISR_CMP2_Msk                    /*!< Slave compare 2 interrupt flag */

+#define HRTIM_TIMISR_CMP3_Pos         (2U)

+#define HRTIM_TIMISR_CMP3_Msk         (0x1UL << HRTIM_TIMISR_CMP3_Pos)         /*!< 0x00000004 */

+#define HRTIM_TIMISR_CMP3             HRTIM_TIMISR_CMP3_Msk                    /*!< Slave compare 3 interrupt flag */

+#define HRTIM_TIMISR_CMP4_Pos         (3U)

+#define HRTIM_TIMISR_CMP4_Msk         (0x1UL << HRTIM_TIMISR_CMP4_Pos)         /*!< 0x00000008 */

+#define HRTIM_TIMISR_CMP4             HRTIM_TIMISR_CMP4_Msk                    /*!< Slave compare 4 interrupt flag */

+#define HRTIM_TIMISR_REP_Pos          (4U)

+#define HRTIM_TIMISR_REP_Msk          (0x1UL << HRTIM_TIMISR_REP_Pos)          /*!< 0x00000010 */

+#define HRTIM_TIMISR_REP              HRTIM_TIMISR_REP_Msk                     /*!< Slave repetition interrupt flag */

+#define HRTIM_TIMISR_UPD_Pos          (6U)

+#define HRTIM_TIMISR_UPD_Msk          (0x1UL << HRTIM_TIMISR_UPD_Pos)          /*!< 0x00000040 */

+#define HRTIM_TIMISR_UPD              HRTIM_TIMISR_UPD_Msk                     /*!< Slave update interrupt flag */

+#define HRTIM_TIMISR_CPT1_Pos         (7U)

+#define HRTIM_TIMISR_CPT1_Msk         (0x1UL << HRTIM_TIMISR_CPT1_Pos)         /*!< 0x00000080 */

+#define HRTIM_TIMISR_CPT1             HRTIM_TIMISR_CPT1_Msk                    /*!< Slave capture 1 interrupt flag */

+#define HRTIM_TIMISR_CPT2_Pos         (8U)

+#define HRTIM_TIMISR_CPT2_Msk         (0x1UL << HRTIM_TIMISR_CPT2_Pos)         /*!< 0x00000100 */

+#define HRTIM_TIMISR_CPT2             HRTIM_TIMISR_CPT2_Msk                    /*!< Slave capture 2 interrupt flag */

+#define HRTIM_TIMISR_SET1_Pos         (9U)

+#define HRTIM_TIMISR_SET1_Msk         (0x1UL << HRTIM_TIMISR_SET1_Pos)         /*!< 0x00000200 */

+#define HRTIM_TIMISR_SET1             HRTIM_TIMISR_SET1_Msk                    /*!< Slave output 1 set interrupt flag */

+#define HRTIM_TIMISR_RST1_Pos         (10U)

+#define HRTIM_TIMISR_RST1_Msk         (0x1UL << HRTIM_TIMISR_RST1_Pos)         /*!< 0x00000400 */

+#define HRTIM_TIMISR_RST1             HRTIM_TIMISR_RST1_Msk                    /*!< Slave output 1 reset interrupt flag */

+#define HRTIM_TIMISR_SET2_Pos         (11U)

+#define HRTIM_TIMISR_SET2_Msk         (0x1UL << HRTIM_TIMISR_SET2_Pos)         /*!< 0x00000800 */

+#define HRTIM_TIMISR_SET2             HRTIM_TIMISR_SET2_Msk                    /*!< Slave output 2 set interrupt flag */

+#define HRTIM_TIMISR_RST2_Pos         (12U)

+#define HRTIM_TIMISR_RST2_Msk         (0x1UL << HRTIM_TIMISR_RST2_Pos)         /*!< 0x00001000 */

+#define HRTIM_TIMISR_RST2             HRTIM_TIMISR_RST2_Msk                    /*!< Slave output 2 reset interrupt flag */

+#define HRTIM_TIMISR_RST_Pos          (13U)

+#define HRTIM_TIMISR_RST_Msk          (0x1UL << HRTIM_TIMISR_RST_Pos)          /*!< 0x00002000 */

+#define HRTIM_TIMISR_RST              HRTIM_TIMISR_RST_Msk                     /*!< Slave reset interrupt flag */

+#define HRTIM_TIMISR_DLYPRT_Pos       (14U)

+#define HRTIM_TIMISR_DLYPRT_Msk       (0x1UL << HRTIM_TIMISR_DLYPRT_Pos)       /*!< 0x00004000 */

+#define HRTIM_TIMISR_DLYPRT           HRTIM_TIMISR_DLYPRT_Msk                  /*!< Slave output 1 delay protection interrupt flag */

+#define HRTIM_TIMISR_CPPSTAT_Pos      (16U)

+#define HRTIM_TIMISR_CPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos)      /*!< 0x00010000 */

+#define HRTIM_TIMISR_CPPSTAT          HRTIM_TIMISR_CPPSTAT_Msk                 /*!< Slave current push-pull flag */

+#define HRTIM_TIMISR_IPPSTAT_Pos      (17U)

+#define HRTIM_TIMISR_IPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos)      /*!< 0x00020000 */

+#define HRTIM_TIMISR_IPPSTAT          HRTIM_TIMISR_IPPSTAT_Msk                 /*!< Slave idle push-pull flag */

+#define HRTIM_TIMISR_O1STAT_Pos       (18U)

+#define HRTIM_TIMISR_O1STAT_Msk       (0x1UL << HRTIM_TIMISR_O1STAT_Pos)       /*!< 0x00040000 */

+#define HRTIM_TIMISR_O1STAT           HRTIM_TIMISR_O1STAT_Msk                  /*!< Slave output 1 state flag */

+#define HRTIM_TIMISR_O2STAT_Pos       (19U)

+#define HRTIM_TIMISR_O2STAT_Msk       (0x1UL << HRTIM_TIMISR_O2STAT_Pos)       /*!< 0x00080000 */

+#define HRTIM_TIMISR_O2STAT           HRTIM_TIMISR_O2STAT_Msk                  /*!< Slave output 2 state flag */

+#define HRTIM_TIMISR_O1CPY_Pos        (20U)

+#define HRTIM_TIMISR_O1CPY_Msk        (0x1UL << HRTIM_TIMISR_O1CPY_Pos)        /*!< 0x00100000 */

+#define HRTIM_TIMISR_O1CPY            HRTIM_TIMISR_O1CPY_Msk                   /*!< Slave output 1 copy flag */

+#define HRTIM_TIMISR_O2CPY_Pos        (21U)

+#define HRTIM_TIMISR_O2CPY_Msk        (0x1UL << HRTIM_TIMISR_O2CPY_Pos)        /*!< 0x00200000 */

+#define HRTIM_TIMISR_O2CPY            HRTIM_TIMISR_O2CPY_Msk                   /*!< Slave output 2 copy flag */

+

+/******************** Slave Interrupt clear register **************************/

+#define HRTIM_TIMICR_CMP1C_Pos        (0U)

+#define HRTIM_TIMICR_CMP1C_Msk        (0x1UL << HRTIM_TIMICR_CMP1C_Pos)        /*!< 0x00000001 */

+#define HRTIM_TIMICR_CMP1C            HRTIM_TIMICR_CMP1C_Msk                   /*!< Slave compare 1 clear flag */

+#define HRTIM_TIMICR_CMP2C_Pos        (1U)

+#define HRTIM_TIMICR_CMP2C_Msk        (0x1UL << HRTIM_TIMICR_CMP2C_Pos)        /*!< 0x00000002 */

+#define HRTIM_TIMICR_CMP2C            HRTIM_TIMICR_CMP2C_Msk                   /*!< Slave compare 2 clear flag */

+#define HRTIM_TIMICR_CMP3C_Pos        (2U)

+#define HRTIM_TIMICR_CMP3C_Msk        (0x1UL << HRTIM_TIMICR_CMP3C_Pos)        /*!< 0x00000004 */

+#define HRTIM_TIMICR_CMP3C            HRTIM_TIMICR_CMP3C_Msk                   /*!< Slave compare 3 clear flag */

+#define HRTIM_TIMICR_CMP4C_Pos        (3U)

+#define HRTIM_TIMICR_CMP4C_Msk        (0x1UL << HRTIM_TIMICR_CMP4C_Pos)        /*!< 0x00000008 */

+#define HRTIM_TIMICR_CMP4C            HRTIM_TIMICR_CMP4C_Msk                   /*!< Slave compare 4 clear flag */

+#define HRTIM_TIMICR_REPC_Pos         (4U)

+#define HRTIM_TIMICR_REPC_Msk         (0x1UL << HRTIM_TIMICR_REPC_Pos)         /*!< 0x00000010 */

+#define HRTIM_TIMICR_REPC             HRTIM_TIMICR_REPC_Msk                    /*!< Slave repetition clear flag */

+#define HRTIM_TIMICR_UPDC_Pos         (6U)

+#define HRTIM_TIMICR_UPDC_Msk         (0x1UL << HRTIM_TIMICR_UPDC_Pos)         /*!< 0x00000040 */

+#define HRTIM_TIMICR_UPDC             HRTIM_TIMICR_UPDC_Msk                    /*!< Slave update clear flag */

+#define HRTIM_TIMICR_CPT1C_Pos        (7U)

+#define HRTIM_TIMICR_CPT1C_Msk        (0x1UL << HRTIM_TIMICR_CPT1C_Pos)        /*!< 0x00000080 */

+#define HRTIM_TIMICR_CPT1C            HRTIM_TIMICR_CPT1C_Msk                   /*!< Slave capture 1 clear flag */

+#define HRTIM_TIMICR_CPT2C_Pos        (8U)

+#define HRTIM_TIMICR_CPT2C_Msk        (0x1UL << HRTIM_TIMICR_CPT2C_Pos)        /*!< 0x00000100 */

+#define HRTIM_TIMICR_CPT2C            HRTIM_TIMICR_CPT2C_Msk                   /*!< Slave capture 2 clear flag */

+#define HRTIM_TIMICR_SET1C_Pos        (9U)

+#define HRTIM_TIMICR_SET1C_Msk        (0x1UL << HRTIM_TIMICR_SET1C_Pos)        /*!< 0x00000200 */

+#define HRTIM_TIMICR_SET1C            HRTIM_TIMICR_SET1C_Msk                   /*!< Slave output 1 set clear flag */

+#define HRTIM_TIMICR_RST1C_Pos        (10U)

+#define HRTIM_TIMICR_RST1C_Msk        (0x1UL << HRTIM_TIMICR_RST1C_Pos)        /*!< 0x00000400 */

+#define HRTIM_TIMICR_RST1C            HRTIM_TIMICR_RST1C_Msk                   /*!< Slave output 1 reset clear flag */

+#define HRTIM_TIMICR_SET2C_Pos        (11U)

+#define HRTIM_TIMICR_SET2C_Msk        (0x1UL << HRTIM_TIMICR_SET2C_Pos)        /*!< 0x00000800 */

+#define HRTIM_TIMICR_SET2C            HRTIM_TIMICR_SET2C_Msk                   /*!< Slave output 2 set clear flag */

+#define HRTIM_TIMICR_RST2C_Pos        (12U)

+#define HRTIM_TIMICR_RST2C_Msk        (0x1UL << HRTIM_TIMICR_RST2C_Pos)        /*!< 0x00001000 */

+#define HRTIM_TIMICR_RST2C            HRTIM_TIMICR_RST2C_Msk                   /*!< Slave output 2 reset clear flag */

+#define HRTIM_TIMICR_RSTC_Pos         (13U)

+#define HRTIM_TIMICR_RSTC_Msk         (0x1UL << HRTIM_TIMICR_RSTC_Pos)         /*!< 0x00002000 */

+#define HRTIM_TIMICR_RSTC             HRTIM_TIMICR_RSTC_Msk                    /*!< Slave reset clear flag */

+#define HRTIM_TIMICR_DLYPRTC_Pos      (14U)

+#define HRTIM_TIMICR_DLYPRTC_Msk      (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos)      /*!< 0x00004000 */

+#define HRTIM_TIMICR_DLYPRTC          HRTIM_TIMICR_DLYPRTC_Msk                 /*!< Slave output 1 delay protection clear flag */

+

+/******************** Slave DMA/Interrupt enable register *********************/

+#define HRTIM_TIMDIER_CMP1IE_Pos      (0U)

+#define HRTIM_TIMDIER_CMP1IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos)      /*!< 0x00000001 */

+#define HRTIM_TIMDIER_CMP1IE          HRTIM_TIMDIER_CMP1IE_Msk                 /*!< Slave compare 1 interrupt enable */

+#define HRTIM_TIMDIER_CMP2IE_Pos      (1U)

+#define HRTIM_TIMDIER_CMP2IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos)      /*!< 0x00000002 */

+#define HRTIM_TIMDIER_CMP2IE          HRTIM_TIMDIER_CMP2IE_Msk                 /*!< Slave compare 2 interrupt enable */

+#define HRTIM_TIMDIER_CMP3IE_Pos      (2U)

+#define HRTIM_TIMDIER_CMP3IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos)      /*!< 0x00000004 */

+#define HRTIM_TIMDIER_CMP3IE          HRTIM_TIMDIER_CMP3IE_Msk                 /*!< Slave compare 3 interrupt enable */

+#define HRTIM_TIMDIER_CMP4IE_Pos      (3U)

+#define HRTIM_TIMDIER_CMP4IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos)      /*!< 0x00000008 */

+#define HRTIM_TIMDIER_CMP4IE          HRTIM_TIMDIER_CMP4IE_Msk                 /*!< Slave compare 4 interrupt enable */

+#define HRTIM_TIMDIER_REPIE_Pos       (4U)

+#define HRTIM_TIMDIER_REPIE_Msk       (0x1UL << HRTIM_TIMDIER_REPIE_Pos)       /*!< 0x00000010 */

+#define HRTIM_TIMDIER_REPIE           HRTIM_TIMDIER_REPIE_Msk                  /*!< Slave repetition interrupt enable */

+#define HRTIM_TIMDIER_UPDIE_Pos       (6U)

+#define HRTIM_TIMDIER_UPDIE_Msk       (0x1UL << HRTIM_TIMDIER_UPDIE_Pos)       /*!< 0x00000040 */

+#define HRTIM_TIMDIER_UPDIE           HRTIM_TIMDIER_UPDIE_Msk                  /*!< Slave update interrupt enable */

+#define HRTIM_TIMDIER_CPT1IE_Pos      (7U)

+#define HRTIM_TIMDIER_CPT1IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos)      /*!< 0x00000080 */

+#define HRTIM_TIMDIER_CPT1IE          HRTIM_TIMDIER_CPT1IE_Msk                 /*!< Slave capture 1 interrupt enable */

+#define HRTIM_TIMDIER_CPT2IE_Pos      (8U)

+#define HRTIM_TIMDIER_CPT2IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos)      /*!< 0x00000100 */

+#define HRTIM_TIMDIER_CPT2IE          HRTIM_TIMDIER_CPT2IE_Msk                 /*!< Slave capture 2 interrupt enable */

+#define HRTIM_TIMDIER_SET1IE_Pos      (9U)

+#define HRTIM_TIMDIER_SET1IE_Msk      (0x1UL << HRTIM_TIMDIER_SET1IE_Pos)      /*!< 0x00000200 */

+#define HRTIM_TIMDIER_SET1IE          HRTIM_TIMDIER_SET1IE_Msk                 /*!< Slave output 1 set interrupt enable */

+#define HRTIM_TIMDIER_RST1IE_Pos      (10U)

+#define HRTIM_TIMDIER_RST1IE_Msk      (0x1UL << HRTIM_TIMDIER_RST1IE_Pos)      /*!< 0x00000400 */

+#define HRTIM_TIMDIER_RST1IE          HRTIM_TIMDIER_RST1IE_Msk                 /*!< Slave output 1 reset interrupt enable */

+#define HRTIM_TIMDIER_SET2IE_Pos      (11U)

+#define HRTIM_TIMDIER_SET2IE_Msk      (0x1UL << HRTIM_TIMDIER_SET2IE_Pos)      /*!< 0x00000800 */

+#define HRTIM_TIMDIER_SET2IE          HRTIM_TIMDIER_SET2IE_Msk                 /*!< Slave output 2 set interrupt enable */

+#define HRTIM_TIMDIER_RST2IE_Pos      (12U)

+#define HRTIM_TIMDIER_RST2IE_Msk      (0x1UL << HRTIM_TIMDIER_RST2IE_Pos)      /*!< 0x00001000 */

+#define HRTIM_TIMDIER_RST2IE          HRTIM_TIMDIER_RST2IE_Msk                 /*!< Slave output 2 reset interrupt enable */

+#define HRTIM_TIMDIER_RSTIE_Pos       (13U)

+#define HRTIM_TIMDIER_RSTIE_Msk       (0x1UL << HRTIM_TIMDIER_RSTIE_Pos)       /*!< 0x00002000 */

+#define HRTIM_TIMDIER_RSTIE           HRTIM_TIMDIER_RSTIE_Msk                  /*!< Slave reset interrupt enable */

+#define HRTIM_TIMDIER_DLYPRTIE_Pos    (14U)

+#define HRTIM_TIMDIER_DLYPRTIE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos)    /*!< 0x00004000 */

+#define HRTIM_TIMDIER_DLYPRTIE        HRTIM_TIMDIER_DLYPRTIE_Msk               /*!< Slave delay protection interrupt enable */

+

+#define HRTIM_TIMDIER_CMP1DE_Pos      (16U)

+#define HRTIM_TIMDIER_CMP1DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos)      /*!< 0x00010000 */

+#define HRTIM_TIMDIER_CMP1DE          HRTIM_TIMDIER_CMP1DE_Msk                 /*!< Slave compare 1 request enable */

+#define HRTIM_TIMDIER_CMP2DE_Pos      (17U)

+#define HRTIM_TIMDIER_CMP2DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos)      /*!< 0x00020000 */

+#define HRTIM_TIMDIER_CMP2DE          HRTIM_TIMDIER_CMP2DE_Msk                 /*!< Slave compare 2 request enable */

+#define HRTIM_TIMDIER_CMP3DE_Pos      (18U)

+#define HRTIM_TIMDIER_CMP3DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos)      /*!< 0x00040000 */

+#define HRTIM_TIMDIER_CMP3DE          HRTIM_TIMDIER_CMP3DE_Msk                 /*!< Slave compare 3 request enable */

+#define HRTIM_TIMDIER_CMP4DE_Pos      (19U)

+#define HRTIM_TIMDIER_CMP4DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos)      /*!< 0x00080000 */

+#define HRTIM_TIMDIER_CMP4DE          HRTIM_TIMDIER_CMP4DE_Msk                 /*!< Slave compare 4 request enable */

+#define HRTIM_TIMDIER_REPDE_Pos       (20U)

+#define HRTIM_TIMDIER_REPDE_Msk       (0x1UL << HRTIM_TIMDIER_REPDE_Pos)       /*!< 0x00100000 */

+#define HRTIM_TIMDIER_REPDE           HRTIM_TIMDIER_REPDE_Msk                  /*!< Slave repetition request enable */

+#define HRTIM_TIMDIER_UPDDE_Pos       (22U)

+#define HRTIM_TIMDIER_UPDDE_Msk       (0x1UL << HRTIM_TIMDIER_UPDDE_Pos)       /*!< 0x00400000 */

+#define HRTIM_TIMDIER_UPDDE           HRTIM_TIMDIER_UPDDE_Msk                  /*!< Slave update request enable */

+#define HRTIM_TIMDIER_CPT1DE_Pos      (23U)

+#define HRTIM_TIMDIER_CPT1DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos)      /*!< 0x00800000 */

+#define HRTIM_TIMDIER_CPT1DE          HRTIM_TIMDIER_CPT1DE_Msk                 /*!< Slave capture 1 request enable */

+#define HRTIM_TIMDIER_CPT2DE_Pos      (24U)

+#define HRTIM_TIMDIER_CPT2DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos)      /*!< 0x01000000 */

+#define HRTIM_TIMDIER_CPT2DE          HRTIM_TIMDIER_CPT2DE_Msk                 /*!< Slave capture 2 request enable */

+#define HRTIM_TIMDIER_SET1DE_Pos      (25U)

+#define HRTIM_TIMDIER_SET1DE_Msk      (0x1UL << HRTIM_TIMDIER_SET1DE_Pos)      /*!< 0x02000000 */

+#define HRTIM_TIMDIER_SET1DE          HRTIM_TIMDIER_SET1DE_Msk                 /*!< Slave output 1 set request enable */

+#define HRTIM_TIMDIER_RST1DE_Pos      (26U)

+#define HRTIM_TIMDIER_RST1DE_Msk      (0x1UL << HRTIM_TIMDIER_RST1DE_Pos)      /*!< 0x04000000 */

+#define HRTIM_TIMDIER_RST1DE          HRTIM_TIMDIER_RST1DE_Msk                 /*!< Slave output 1 reset request enable */

+#define HRTIM_TIMDIER_SET2DE_Pos      (27U)

+#define HRTIM_TIMDIER_SET2DE_Msk      (0x1UL << HRTIM_TIMDIER_SET2DE_Pos)      /*!< 0x08000000 */

+#define HRTIM_TIMDIER_SET2DE          HRTIM_TIMDIER_SET2DE_Msk                 /*!< Slave output 2 set request enable */

+#define HRTIM_TIMDIER_RST2DE_Pos      (28U)

+#define HRTIM_TIMDIER_RST2DE_Msk      (0x1UL << HRTIM_TIMDIER_RST2DE_Pos)      /*!< 0x10000000 */

+#define HRTIM_TIMDIER_RST2DE          HRTIM_TIMDIER_RST2DE_Msk                 /*!< Slave output 2 reset request enable */

+#define HRTIM_TIMDIER_RSTDE_Pos       (29U)

+#define HRTIM_TIMDIER_RSTDE_Msk       (0x1UL << HRTIM_TIMDIER_RSTDE_Pos)       /*!< 0x20000000 */

+#define HRTIM_TIMDIER_RSTDE           HRTIM_TIMDIER_RSTDE_Msk                  /*!< Slave reset request enable */

+#define HRTIM_TIMDIER_DLYPRTDE_Pos    (30U)

+#define HRTIM_TIMDIER_DLYPRTDE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos)    /*!< 0x40000000 */

+#define HRTIM_TIMDIER_DLYPRTDE        HRTIM_TIMDIER_DLYPRTDE_Msk               /*!< Slavedelay protection request enable */

+

+/******************  Bit definition for HRTIM_CNTR register  ****************/

+#define HRTIM_CNTR_CNTR_Pos           (0U)

+#define HRTIM_CNTR_CNTR_Msk           (0xFFFFUL << HRTIM_CNTR_CNTR_Pos)        /*!< 0x0000FFFF */

+#define HRTIM_CNTR_CNTR               HRTIM_CNTR_CNTR_Msk                      /*!< Counter Value */

+

+/*******************  Bit definition for HRTIM_PER register  *****************/

+#define HRTIM_PER_PER_Pos             (0U)

+#define HRTIM_PER_PER_Msk             (0xFFFFUL << HRTIM_PER_PER_Pos)          /*!< 0x0000FFFF */

+#define HRTIM_PER_PER                 HRTIM_PER_PER_Msk                        /*!< Period Value */

+

+/*******************  Bit definition for HRTIM_REP register  *****************/

+#define HRTIM_REP_REP_Pos             (0U)

+#define HRTIM_REP_REP_Msk             (0xFFUL << HRTIM_REP_REP_Pos)            /*!< 0x000000FF */

+#define HRTIM_REP_REP                 HRTIM_REP_REP_Msk                        /*!< Repetition Value */

+

+/*******************  Bit definition for HRTIM_CMP1R register  *****************/

+#define HRTIM_CMP1R_CMP1R_Pos         (0U)

+#define HRTIM_CMP1R_CMP1R_Msk         (0xFFFFUL << HRTIM_CMP1R_CMP1R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP1R_CMP1R             HRTIM_CMP1R_CMP1R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP1CR register  *****************/

+#define HRTIM_CMP1CR_CMP1CR_Pos       (0U)

+#define HRTIM_CMP1CR_CMP1CR_Msk       (0xFFFFFFFFUL << HRTIM_CMP1CR_CMP1CR_Pos) /*!< 0xFFFFFFFF */

+#define HRTIM_CMP1CR_CMP1CR           HRTIM_CMP1CR_CMP1CR_Msk                  /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP2R register  *****************/

+#define HRTIM_CMP2R_CMP2R_Pos         (0U)

+#define HRTIM_CMP2R_CMP2R_Msk         (0xFFFFUL << HRTIM_CMP2R_CMP2R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP2R_CMP2R             HRTIM_CMP2R_CMP2R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP3R register  *****************/

+#define HRTIM_CMP3R_CMP3R_Pos         (0U)

+#define HRTIM_CMP3R_CMP3R_Msk         (0xFFFFUL << HRTIM_CMP3R_CMP3R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP3R_CMP3R             HRTIM_CMP3R_CMP3R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP4R register  *****************/

+#define HRTIM_CMP4R_CMP4R_Pos         (0U)

+#define HRTIM_CMP4R_CMP4R_Msk         (0xFFFFUL << HRTIM_CMP4R_CMP4R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP4R_CMP4R             HRTIM_CMP4R_CMP4R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CPT1R register  ****************/

+#define HRTIM_CPT1R_CPT1R_Pos         (0U)

+#define HRTIM_CPT1R_CPT1R_Msk         (0xFFFFUL << HRTIM_CPT1R_CPT1R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CPT1R_CPT1R             HRTIM_CPT1R_CPT1R_Msk                    /*!< Capture Value */

+

+/*******************  Bit definition for HRTIM_CPT2R register  ****************/

+#define HRTIM_CPT2R_CPT2R_Pos         (0U)

+#define HRTIM_CPT2R_CPT2R_Msk         (0xFFFFUL << HRTIM_CPT2R_CPT2R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CPT2R_CPT2R             HRTIM_CPT2R_CPT2R_Msk                    /*!< Capture Value */

+

+/******************** Bit definition for Slave Deadtime register **************/

+#define HRTIM_DTR_DTR_Pos             (0U)

+#define HRTIM_DTR_DTR_Msk             (0x1FFUL << HRTIM_DTR_DTR_Pos)           /*!< 0x000001FF */

+#define HRTIM_DTR_DTR                 HRTIM_DTR_DTR_Msk                        /*!< Dead time rising value */

+#define HRTIM_DTR_DTR_0               (0x001UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000001 */

+#define HRTIM_DTR_DTR_1               (0x002UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000002 */

+#define HRTIM_DTR_DTR_2               (0x004UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000004 */

+#define HRTIM_DTR_DTR_3               (0x008UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000008 */

+#define HRTIM_DTR_DTR_4               (0x010UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000010 */

+#define HRTIM_DTR_DTR_5               (0x020UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000020 */

+#define HRTIM_DTR_DTR_6               (0x040UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000040 */

+#define HRTIM_DTR_DTR_7               (0x080UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000080 */

+#define HRTIM_DTR_DTR_8               (0x100UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000100 */

+#define HRTIM_DTR_SDTR_Pos            (9U)

+#define HRTIM_DTR_SDTR_Msk            (0x1UL << HRTIM_DTR_SDTR_Pos)            /*!< 0x00000200 */

+#define HRTIM_DTR_SDTR                HRTIM_DTR_SDTR_Msk                       /*!< Sign dead time rising value */

+#define HRTIM_DTR_DTPRSC_Pos          (10U)

+#define HRTIM_DTR_DTPRSC_Msk          (0x7UL << HRTIM_DTR_DTPRSC_Pos)          /*!< 0x00001C00 */

+#define HRTIM_DTR_DTPRSC              HRTIM_DTR_DTPRSC_Msk                     /*!< Dead time prescaler */

+#define HRTIM_DTR_DTPRSC_0            (0x1UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000400 */

+#define HRTIM_DTR_DTPRSC_1            (0x2UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000800 */

+#define HRTIM_DTR_DTPRSC_2            (0x4UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00001000 */

+#define HRTIM_DTR_DTRSLK_Pos          (14U)

+#define HRTIM_DTR_DTRSLK_Msk          (0x1UL << HRTIM_DTR_DTRSLK_Pos)          /*!< 0x00004000 */

+#define HRTIM_DTR_DTRSLK              HRTIM_DTR_DTRSLK_Msk                     /*!< Dead time rising sign lock */

+#define HRTIM_DTR_DTRLK_Pos           (15U)

+#define HRTIM_DTR_DTRLK_Msk           (0x1UL << HRTIM_DTR_DTRLK_Pos)           /*!< 0x00008000 */

+#define HRTIM_DTR_DTRLK               HRTIM_DTR_DTRLK_Msk                      /*!< Dead time rising lock */

+#define HRTIM_DTR_DTF_Pos             (16U)

+#define HRTIM_DTR_DTF_Msk             (0x1FFUL << HRTIM_DTR_DTF_Pos)           /*!< 0x01FF0000 */

+#define HRTIM_DTR_DTF                 HRTIM_DTR_DTF_Msk                        /*!< Dead time falling value */

+#define HRTIM_DTR_DTF_0               (0x001UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00010000 */

+#define HRTIM_DTR_DTF_1               (0x002UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00020000 */

+#define HRTIM_DTR_DTF_2               (0x004UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00040000 */

+#define HRTIM_DTR_DTF_3               (0x008UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00080000 */

+#define HRTIM_DTR_DTF_4               (0x010UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00100000 */

+#define HRTIM_DTR_DTF_5               (0x020UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00200000 */

+#define HRTIM_DTR_DTF_6               (0x040UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00400000 */

+#define HRTIM_DTR_DTF_7               (0x080UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00800000 */

+#define HRTIM_DTR_DTF_8               (0x100UL << HRTIM_DTR_DTF_Pos)            /*!< 0x01000000 */

+#define HRTIM_DTR_SDTF_Pos            (25U)

+#define HRTIM_DTR_SDTF_Msk            (0x1UL << HRTIM_DTR_SDTF_Pos)            /*!< 0x02000000 */

+#define HRTIM_DTR_SDTF                HRTIM_DTR_SDTF_Msk                       /*!< Sign dead time falling value */

+#define HRTIM_DTR_DTFSLK_Pos          (30U)

+#define HRTIM_DTR_DTFSLK_Msk          (0x1UL << HRTIM_DTR_DTFSLK_Pos)          /*!< 0x40000000 */

+#define HRTIM_DTR_DTFSLK              HRTIM_DTR_DTFSLK_Msk                     /*!< Dead time falling sign lock */

+#define HRTIM_DTR_DTFLK_Pos           (31U)

+#define HRTIM_DTR_DTFLK_Msk           (0x1UL << HRTIM_DTR_DTFLK_Pos)           /*!< 0x80000000 */

+#define HRTIM_DTR_DTFLK               HRTIM_DTR_DTFLK_Msk                      /*!< Dead time falling lock */

+

+/**** Bit definition for Slave Output 1 set register **************************/

+#define HRTIM_SET1R_SST_Pos           (0U)

+#define HRTIM_SET1R_SST_Msk           (0x1UL << HRTIM_SET1R_SST_Pos)           /*!< 0x00000001 */

+#define HRTIM_SET1R_SST               HRTIM_SET1R_SST_Msk                      /*!< software set trigger */

+#define HRTIM_SET1R_RESYNC_Pos        (1U)

+#define HRTIM_SET1R_RESYNC_Msk        (0x1UL << HRTIM_SET1R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_SET1R_RESYNC            HRTIM_SET1R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_SET1R_PER_Pos           (2U)

+#define HRTIM_SET1R_PER_Msk           (0x1UL << HRTIM_SET1R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_SET1R_PER               HRTIM_SET1R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_SET1R_CMP1_Pos          (3U)

+#define HRTIM_SET1R_CMP1_Msk          (0x1UL << HRTIM_SET1R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_SET1R_CMP1              HRTIM_SET1R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_SET1R_CMP2_Pos          (4U)

+#define HRTIM_SET1R_CMP2_Msk          (0x1UL << HRTIM_SET1R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_SET1R_CMP2              HRTIM_SET1R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_SET1R_CMP3_Pos          (5U)

+#define HRTIM_SET1R_CMP3_Msk          (0x1UL << HRTIM_SET1R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_SET1R_CMP3              HRTIM_SET1R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_SET1R_CMP4_Pos          (6U)

+#define HRTIM_SET1R_CMP4_Msk          (0x1UL << HRTIM_SET1R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_SET1R_CMP4              HRTIM_SET1R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_SET1R_MSTPER_Pos        (7U)

+#define HRTIM_SET1R_MSTPER_Msk        (0x1UL << HRTIM_SET1R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_SET1R_MSTPER            HRTIM_SET1R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_SET1R_MSTCMP1_Pos       (8U)

+#define HRTIM_SET1R_MSTCMP1_Msk       (0x1UL << HRTIM_SET1R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_SET1R_MSTCMP1           HRTIM_SET1R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_SET1R_MSTCMP2_Pos       (9U)

+#define HRTIM_SET1R_MSTCMP2_Msk       (0x1UL << HRTIM_SET1R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_SET1R_MSTCMP2           HRTIM_SET1R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_SET1R_MSTCMP3_Pos       (10U)

+#define HRTIM_SET1R_MSTCMP3_Msk       (0x1UL << HRTIM_SET1R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_SET1R_MSTCMP3           HRTIM_SET1R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_SET1R_MSTCMP4_Pos       (11U)

+#define HRTIM_SET1R_MSTCMP4_Msk       (0x1UL << HRTIM_SET1R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_SET1R_MSTCMP4           HRTIM_SET1R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_SET1R_TIMEVNT1_Pos      (12U)

+#define HRTIM_SET1R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_SET1R_TIMEVNT1          HRTIM_SET1R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_SET1R_TIMEVNT2_Pos      (13U)

+#define HRTIM_SET1R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_SET1R_TIMEVNT2          HRTIM_SET1R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_SET1R_TIMEVNT3_Pos      (14U)

+#define HRTIM_SET1R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_SET1R_TIMEVNT3          HRTIM_SET1R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_SET1R_TIMEVNT4_Pos      (15U)

+#define HRTIM_SET1R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_SET1R_TIMEVNT4          HRTIM_SET1R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_SET1R_TIMEVNT5_Pos      (16U)

+#define HRTIM_SET1R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_SET1R_TIMEVNT5          HRTIM_SET1R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_SET1R_TIMEVNT6_Pos      (17U)

+#define HRTIM_SET1R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_SET1R_TIMEVNT6          HRTIM_SET1R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_SET1R_TIMEVNT7_Pos      (18U)

+#define HRTIM_SET1R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_SET1R_TIMEVNT7          HRTIM_SET1R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_SET1R_TIMEVNT8_Pos      (19U)

+#define HRTIM_SET1R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_SET1R_TIMEVNT8          HRTIM_SET1R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_SET1R_TIMEVNT9_Pos      (20U)

+#define HRTIM_SET1R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_SET1R_TIMEVNT9          HRTIM_SET1R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_SET1R_EXTVNT1_Pos       (21U)

+#define HRTIM_SET1R_EXTVNT1_Msk       (0x1UL << HRTIM_SET1R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_SET1R_EXTVNT1           HRTIM_SET1R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_SET1R_EXTVNT2_Pos       (22U)

+#define HRTIM_SET1R_EXTVNT2_Msk       (0x1UL << HRTIM_SET1R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_SET1R_EXTVNT2           HRTIM_SET1R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_SET1R_EXTVNT3_Pos       (23U)

+#define HRTIM_SET1R_EXTVNT3_Msk       (0x1UL << HRTIM_SET1R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_SET1R_EXTVNT3           HRTIM_SET1R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_SET1R_EXTVNT4_Pos       (24U)

+#define HRTIM_SET1R_EXTVNT4_Msk       (0x1UL << HRTIM_SET1R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_SET1R_EXTVNT4           HRTIM_SET1R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_SET1R_EXTVNT5_Pos       (25U)

+#define HRTIM_SET1R_EXTVNT5_Msk       (0x1UL << HRTIM_SET1R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_SET1R_EXTVNT5           HRTIM_SET1R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_SET1R_EXTVNT6_Pos       (26U)

+#define HRTIM_SET1R_EXTVNT6_Msk       (0x1UL << HRTIM_SET1R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_SET1R_EXTVNT6           HRTIM_SET1R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_SET1R_EXTVNT7_Pos       (27U)

+#define HRTIM_SET1R_EXTVNT7_Msk       (0x1UL << HRTIM_SET1R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_SET1R_EXTVNT7           HRTIM_SET1R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_SET1R_EXTVNT8_Pos       (28U)

+#define HRTIM_SET1R_EXTVNT8_Msk       (0x1UL << HRTIM_SET1R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_SET1R_EXTVNT8           HRTIM_SET1R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_SET1R_EXTVNT9_Pos       (29U)

+#define HRTIM_SET1R_EXTVNT9_Msk       (0x1UL << HRTIM_SET1R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_SET1R_EXTVNT9           HRTIM_SET1R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_SET1R_EXTVNT10_Pos      (30U)

+#define HRTIM_SET1R_EXTVNT10_Msk      (0x1UL << HRTIM_SET1R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_SET1R_EXTVNT10          HRTIM_SET1R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_SET1R_UPDATE_Pos        (31U)

+#define HRTIM_SET1R_UPDATE_Msk        (0x1UL << HRTIM_SET1R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_SET1R_UPDATE            HRTIM_SET1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+/**** Bit definition for Slave Output 1 reset register ************************/

+#define HRTIM_RST1R_SRT_Pos           (0U)

+#define HRTIM_RST1R_SRT_Msk           (0x1UL << HRTIM_RST1R_SRT_Pos)           /*!< 0x00000001 */

+#define HRTIM_RST1R_SRT               HRTIM_RST1R_SRT_Msk                      /*!< software reset trigger */

+#define HRTIM_RST1R_RESYNC_Pos        (1U)

+#define HRTIM_RST1R_RESYNC_Msk        (0x1UL << HRTIM_RST1R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_RST1R_RESYNC            HRTIM_RST1R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_RST1R_PER_Pos           (2U)

+#define HRTIM_RST1R_PER_Msk           (0x1UL << HRTIM_RST1R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_RST1R_PER               HRTIM_RST1R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_RST1R_CMP1_Pos          (3U)

+#define HRTIM_RST1R_CMP1_Msk          (0x1UL << HRTIM_RST1R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_RST1R_CMP1              HRTIM_RST1R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_RST1R_CMP2_Pos          (4U)

+#define HRTIM_RST1R_CMP2_Msk          (0x1UL << HRTIM_RST1R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_RST1R_CMP2              HRTIM_RST1R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_RST1R_CMP3_Pos          (5U)

+#define HRTIM_RST1R_CMP3_Msk          (0x1UL << HRTIM_RST1R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_RST1R_CMP3              HRTIM_RST1R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_RST1R_CMP4_Pos          (6U)

+#define HRTIM_RST1R_CMP4_Msk          (0x1UL << HRTIM_RST1R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_RST1R_CMP4              HRTIM_RST1R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_RST1R_MSTPER_Pos        (7U)

+#define HRTIM_RST1R_MSTPER_Msk        (0x1UL << HRTIM_RST1R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_RST1R_MSTPER            HRTIM_RST1R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_RST1R_MSTCMP1_Pos       (8U)

+#define HRTIM_RST1R_MSTCMP1_Msk       (0x1UL << HRTIM_RST1R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_RST1R_MSTCMP1           HRTIM_RST1R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_RST1R_MSTCMP2_Pos       (9U)

+#define HRTIM_RST1R_MSTCMP2_Msk       (0x1UL << HRTIM_RST1R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_RST1R_MSTCMP2           HRTIM_RST1R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_RST1R_MSTCMP3_Pos       (10U)

+#define HRTIM_RST1R_MSTCMP3_Msk       (0x1UL << HRTIM_RST1R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_RST1R_MSTCMP3           HRTIM_RST1R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_RST1R_MSTCMP4_Pos       (11U)

+#define HRTIM_RST1R_MSTCMP4_Msk       (0x1UL << HRTIM_RST1R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_RST1R_MSTCMP4           HRTIM_RST1R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_RST1R_TIMEVNT1_Pos      (12U)

+#define HRTIM_RST1R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_RST1R_TIMEVNT1          HRTIM_RST1R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_RST1R_TIMEVNT2_Pos      (13U)

+#define HRTIM_RST1R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_RST1R_TIMEVNT2          HRTIM_RST1R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_RST1R_TIMEVNT3_Pos      (14U)

+#define HRTIM_RST1R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_RST1R_TIMEVNT3          HRTIM_RST1R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_RST1R_TIMEVNT4_Pos      (15U)

+#define HRTIM_RST1R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_RST1R_TIMEVNT4          HRTIM_RST1R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_RST1R_TIMEVNT5_Pos      (16U)

+#define HRTIM_RST1R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_RST1R_TIMEVNT5          HRTIM_RST1R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_RST1R_TIMEVNT6_Pos      (17U)

+#define HRTIM_RST1R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_RST1R_TIMEVNT6          HRTIM_RST1R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_RST1R_TIMEVNT7_Pos      (18U)

+#define HRTIM_RST1R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_RST1R_TIMEVNT7          HRTIM_RST1R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_RST1R_TIMEVNT8_Pos      (19U)

+#define HRTIM_RST1R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_RST1R_TIMEVNT8          HRTIM_RST1R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_RST1R_TIMEVNT9_Pos      (20U)

+#define HRTIM_RST1R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_RST1R_TIMEVNT9          HRTIM_RST1R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_RST1R_EXTVNT1_Pos       (21U)

+#define HRTIM_RST1R_EXTVNT1_Msk       (0x1UL << HRTIM_RST1R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_RST1R_EXTVNT1           HRTIM_RST1R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_RST1R_EXTVNT2_Pos       (22U)

+#define HRTIM_RST1R_EXTVNT2_Msk       (0x1UL << HRTIM_RST1R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_RST1R_EXTVNT2           HRTIM_RST1R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_RST1R_EXTVNT3_Pos       (23U)

+#define HRTIM_RST1R_EXTVNT3_Msk       (0x1UL << HRTIM_RST1R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_RST1R_EXTVNT3           HRTIM_RST1R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_RST1R_EXTVNT4_Pos       (24U)

+#define HRTIM_RST1R_EXTVNT4_Msk       (0x1UL << HRTIM_RST1R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_RST1R_EXTVNT4           HRTIM_RST1R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_RST1R_EXTVNT5_Pos       (25U)

+#define HRTIM_RST1R_EXTVNT5_Msk       (0x1UL << HRTIM_RST1R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_RST1R_EXTVNT5           HRTIM_RST1R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_RST1R_EXTVNT6_Pos       (26U)

+#define HRTIM_RST1R_EXTVNT6_Msk       (0x1UL << HRTIM_RST1R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_RST1R_EXTVNT6           HRTIM_RST1R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_RST1R_EXTVNT7_Pos       (27U)

+#define HRTIM_RST1R_EXTVNT7_Msk       (0x1UL << HRTIM_RST1R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_RST1R_EXTVNT7           HRTIM_RST1R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_RST1R_EXTVNT8_Pos       (28U)

+#define HRTIM_RST1R_EXTVNT8_Msk       (0x1UL << HRTIM_RST1R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_RST1R_EXTVNT8           HRTIM_RST1R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_RST1R_EXTVNT9_Pos       (29U)

+#define HRTIM_RST1R_EXTVNT9_Msk       (0x1UL << HRTIM_RST1R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_RST1R_EXTVNT9           HRTIM_RST1R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_RST1R_EXTVNT10_Pos      (30U)

+#define HRTIM_RST1R_EXTVNT10_Msk      (0x1UL << HRTIM_RST1R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_RST1R_EXTVNT10          HRTIM_RST1R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_RST1R_UPDATE_Pos        (31U)

+#define HRTIM_RST1R_UPDATE_Msk        (0x1UL << HRTIM_RST1R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_RST1R_UPDATE            HRTIM_RST1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+

+/**** Bit definition for Slave Output 2 set register **************************/

+#define HRTIM_SET2R_SST_Pos           (0U)

+#define HRTIM_SET2R_SST_Msk           (0x1UL << HRTIM_SET2R_SST_Pos)           /*!< 0x00000001 */

+#define HRTIM_SET2R_SST               HRTIM_SET2R_SST_Msk                      /*!< software set trigger */

+#define HRTIM_SET2R_RESYNC_Pos        (1U)

+#define HRTIM_SET2R_RESYNC_Msk        (0x1UL << HRTIM_SET2R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_SET2R_RESYNC            HRTIM_SET2R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_SET2R_PER_Pos           (2U)

+#define HRTIM_SET2R_PER_Msk           (0x1UL << HRTIM_SET2R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_SET2R_PER               HRTIM_SET2R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_SET2R_CMP1_Pos          (3U)

+#define HRTIM_SET2R_CMP1_Msk          (0x1UL << HRTIM_SET2R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_SET2R_CMP1              HRTIM_SET2R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_SET2R_CMP2_Pos          (4U)

+#define HRTIM_SET2R_CMP2_Msk          (0x1UL << HRTIM_SET2R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_SET2R_CMP2              HRTIM_SET2R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_SET2R_CMP3_Pos          (5U)

+#define HRTIM_SET2R_CMP3_Msk          (0x1UL << HRTIM_SET2R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_SET2R_CMP3              HRTIM_SET2R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_SET2R_CMP4_Pos          (6U)

+#define HRTIM_SET2R_CMP4_Msk          (0x1UL << HRTIM_SET2R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_SET2R_CMP4              HRTIM_SET2R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_SET2R_MSTPER_Pos        (7U)

+#define HRTIM_SET2R_MSTPER_Msk        (0x1UL << HRTIM_SET2R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_SET2R_MSTPER            HRTIM_SET2R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_SET2R_MSTCMP1_Pos       (8U)

+#define HRTIM_SET2R_MSTCMP1_Msk       (0x1UL << HRTIM_SET2R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_SET2R_MSTCMP1           HRTIM_SET2R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_SET2R_MSTCMP2_Pos       (9U)

+#define HRTIM_SET2R_MSTCMP2_Msk       (0x1UL << HRTIM_SET2R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_SET2R_MSTCMP2           HRTIM_SET2R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_SET2R_MSTCMP3_Pos       (10U)

+#define HRTIM_SET2R_MSTCMP3_Msk       (0x1UL << HRTIM_SET2R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_SET2R_MSTCMP3           HRTIM_SET2R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_SET2R_MSTCMP4_Pos       (11U)

+#define HRTIM_SET2R_MSTCMP4_Msk       (0x1UL << HRTIM_SET2R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_SET2R_MSTCMP4           HRTIM_SET2R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_SET2R_TIMEVNT1_Pos      (12U)

+#define HRTIM_SET2R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_SET2R_TIMEVNT1          HRTIM_SET2R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_SET2R_TIMEVNT2_Pos      (13U)

+#define HRTIM_SET2R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_SET2R_TIMEVNT2          HRTIM_SET2R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_SET2R_TIMEVNT3_Pos      (14U)

+#define HRTIM_SET2R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_SET2R_TIMEVNT3          HRTIM_SET2R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_SET2R_TIMEVNT4_Pos      (15U)

+#define HRTIM_SET2R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_SET2R_TIMEVNT4          HRTIM_SET2R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_SET2R_TIMEVNT5_Pos      (16U)

+#define HRTIM_SET2R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_SET2R_TIMEVNT5          HRTIM_SET2R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_SET2R_TIMEVNT6_Pos      (17U)

+#define HRTIM_SET2R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_SET2R_TIMEVNT6          HRTIM_SET2R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_SET2R_TIMEVNT7_Pos      (18U)

+#define HRTIM_SET2R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_SET2R_TIMEVNT7          HRTIM_SET2R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_SET2R_TIMEVNT8_Pos      (19U)

+#define HRTIM_SET2R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_SET2R_TIMEVNT8          HRTIM_SET2R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_SET2R_TIMEVNT9_Pos      (20U)

+#define HRTIM_SET2R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_SET2R_TIMEVNT9          HRTIM_SET2R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_SET2R_EXTVNT1_Pos       (21U)

+#define HRTIM_SET2R_EXTVNT1_Msk       (0x1UL << HRTIM_SET2R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_SET2R_EXTVNT1           HRTIM_SET2R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_SET2R_EXTVNT2_Pos       (22U)

+#define HRTIM_SET2R_EXTVNT2_Msk       (0x1UL << HRTIM_SET2R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_SET2R_EXTVNT2           HRTIM_SET2R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_SET2R_EXTVNT3_Pos       (23U)

+#define HRTIM_SET2R_EXTVNT3_Msk       (0x1UL << HRTIM_SET2R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_SET2R_EXTVNT3           HRTIM_SET2R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_SET2R_EXTVNT4_Pos       (24U)

+#define HRTIM_SET2R_EXTVNT4_Msk       (0x1UL << HRTIM_SET2R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_SET2R_EXTVNT4           HRTIM_SET2R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_SET2R_EXTVNT5_Pos       (25U)

+#define HRTIM_SET2R_EXTVNT5_Msk       (0x1UL << HRTIM_SET2R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_SET2R_EXTVNT5           HRTIM_SET2R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_SET2R_EXTVNT6_Pos       (26U)

+#define HRTIM_SET2R_EXTVNT6_Msk       (0x1UL << HRTIM_SET2R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_SET2R_EXTVNT6           HRTIM_SET2R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_SET2R_EXTVNT7_Pos       (27U)

+#define HRTIM_SET2R_EXTVNT7_Msk       (0x1UL << HRTIM_SET2R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_SET2R_EXTVNT7           HRTIM_SET2R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_SET2R_EXTVNT8_Pos       (28U)

+#define HRTIM_SET2R_EXTVNT8_Msk       (0x1UL << HRTIM_SET2R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_SET2R_EXTVNT8           HRTIM_SET2R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_SET2R_EXTVNT9_Pos       (29U)

+#define HRTIM_SET2R_EXTVNT9_Msk       (0x1UL << HRTIM_SET2R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_SET2R_EXTVNT9           HRTIM_SET2R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_SET2R_EXTVNT10_Pos      (30U)

+#define HRTIM_SET2R_EXTVNT10_Msk      (0x1UL << HRTIM_SET2R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_SET2R_EXTVNT10          HRTIM_SET2R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_SET2R_UPDATE_Pos        (31U)

+#define HRTIM_SET2R_UPDATE_Msk        (0x1UL << HRTIM_SET2R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_SET2R_UPDATE            HRTIM_SET2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+/**** Bit definition for Slave Output 2 reset register ************************/

+#define HRTIM_RST2R_SRT_Pos           (0U)

+#define HRTIM_RST2R_SRT_Msk           (0x1UL << HRTIM_RST2R_SRT_Pos)           /*!< 0x00000001 */

+#define HRTIM_RST2R_SRT               HRTIM_RST2R_SRT_Msk                      /*!< software reset trigger */

+#define HRTIM_RST2R_RESYNC_Pos        (1U)

+#define HRTIM_RST2R_RESYNC_Msk        (0x1UL << HRTIM_RST2R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_RST2R_RESYNC            HRTIM_RST2R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_RST2R_PER_Pos           (2U)

+#define HRTIM_RST2R_PER_Msk           (0x1UL << HRTIM_RST2R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_RST2R_PER               HRTIM_RST2R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_RST2R_CMP1_Pos          (3U)

+#define HRTIM_RST2R_CMP1_Msk          (0x1UL << HRTIM_RST2R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_RST2R_CMP1              HRTIM_RST2R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_RST2R_CMP2_Pos          (4U)

+#define HRTIM_RST2R_CMP2_Msk          (0x1UL << HRTIM_RST2R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_RST2R_CMP2              HRTIM_RST2R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_RST2R_CMP3_Pos          (5U)

+#define HRTIM_RST2R_CMP3_Msk          (0x1UL << HRTIM_RST2R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_RST2R_CMP3              HRTIM_RST2R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_RST2R_CMP4_Pos          (6U)

+#define HRTIM_RST2R_CMP4_Msk          (0x1UL << HRTIM_RST2R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_RST2R_CMP4              HRTIM_RST2R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_RST2R_MSTPER_Pos        (7U)

+#define HRTIM_RST2R_MSTPER_Msk        (0x1UL << HRTIM_RST2R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_RST2R_MSTPER            HRTIM_RST2R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_RST2R_MSTCMP1_Pos       (8U)

+#define HRTIM_RST2R_MSTCMP1_Msk       (0x1UL << HRTIM_RST2R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_RST2R_MSTCMP1           HRTIM_RST2R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_RST2R_MSTCMP2_Pos       (9U)

+#define HRTIM_RST2R_MSTCMP2_Msk       (0x1UL << HRTIM_RST2R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_RST2R_MSTCMP2           HRTIM_RST2R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_RST2R_MSTCMP3_Pos       (10U)

+#define HRTIM_RST2R_MSTCMP3_Msk       (0x1UL << HRTIM_RST2R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_RST2R_MSTCMP3           HRTIM_RST2R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_RST2R_MSTCMP4_Pos       (11U)

+#define HRTIM_RST2R_MSTCMP4_Msk       (0x1UL << HRTIM_RST2R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_RST2R_MSTCMP4           HRTIM_RST2R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_RST2R_TIMEVNT1_Pos      (12U)

+#define HRTIM_RST2R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_RST2R_TIMEVNT1          HRTIM_RST2R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_RST2R_TIMEVNT2_Pos      (13U)

+#define HRTIM_RST2R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_RST2R_TIMEVNT2          HRTIM_RST2R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_RST2R_TIMEVNT3_Pos      (14U)

+#define HRTIM_RST2R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_RST2R_TIMEVNT3          HRTIM_RST2R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_RST2R_TIMEVNT4_Pos      (15U)

+#define HRTIM_RST2R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_RST2R_TIMEVNT4          HRTIM_RST2R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_RST2R_TIMEVNT5_Pos      (16U)

+#define HRTIM_RST2R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_RST2R_TIMEVNT5          HRTIM_RST2R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_RST2R_TIMEVNT6_Pos      (17U)

+#define HRTIM_RST2R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_RST2R_TIMEVNT6          HRTIM_RST2R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_RST2R_TIMEVNT7_Pos      (18U)

+#define HRTIM_RST2R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_RST2R_TIMEVNT7          HRTIM_RST2R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_RST2R_TIMEVNT8_Pos      (19U)

+#define HRTIM_RST2R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_RST2R_TIMEVNT8          HRTIM_RST2R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_RST2R_TIMEVNT9_Pos      (20U)

+#define HRTIM_RST2R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_RST2R_TIMEVNT9          HRTIM_RST2R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_RST2R_EXTVNT1_Pos       (21U)

+#define HRTIM_RST2R_EXTVNT1_Msk       (0x1UL << HRTIM_RST2R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_RST2R_EXTVNT1           HRTIM_RST2R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_RST2R_EXTVNT2_Pos       (22U)

+#define HRTIM_RST2R_EXTVNT2_Msk       (0x1UL << HRTIM_RST2R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_RST2R_EXTVNT2           HRTIM_RST2R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_RST2R_EXTVNT3_Pos       (23U)

+#define HRTIM_RST2R_EXTVNT3_Msk       (0x1UL << HRTIM_RST2R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_RST2R_EXTVNT3           HRTIM_RST2R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_RST2R_EXTVNT4_Pos       (24U)

+#define HRTIM_RST2R_EXTVNT4_Msk       (0x1UL << HRTIM_RST2R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_RST2R_EXTVNT4           HRTIM_RST2R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_RST2R_EXTVNT5_Pos       (25U)

+#define HRTIM_RST2R_EXTVNT5_Msk       (0x1UL << HRTIM_RST2R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_RST2R_EXTVNT5           HRTIM_RST2R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_RST2R_EXTVNT6_Pos       (26U)

+#define HRTIM_RST2R_EXTVNT6_Msk       (0x1UL << HRTIM_RST2R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_RST2R_EXTVNT6           HRTIM_RST2R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_RST2R_EXTVNT7_Pos       (27U)

+#define HRTIM_RST2R_EXTVNT7_Msk       (0x1UL << HRTIM_RST2R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_RST2R_EXTVNT7           HRTIM_RST2R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_RST2R_EXTVNT8_Pos       (28U)

+#define HRTIM_RST2R_EXTVNT8_Msk       (0x1UL << HRTIM_RST2R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_RST2R_EXTVNT8           HRTIM_RST2R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_RST2R_EXTVNT9_Pos       (29U)

+#define HRTIM_RST2R_EXTVNT9_Msk       (0x1UL << HRTIM_RST2R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_RST2R_EXTVNT9           HRTIM_RST2R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_RST2R_EXTVNT10_Pos      (30U)

+#define HRTIM_RST2R_EXTVNT10_Msk      (0x1UL << HRTIM_RST2R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_RST2R_EXTVNT10          HRTIM_RST2R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_RST2R_UPDATE_Pos        (31U)

+#define HRTIM_RST2R_UPDATE_Msk        (0x1UL << HRTIM_RST2R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_RST2R_UPDATE            HRTIM_RST2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+/**** Bit definition for Slave external event filtering  register 1 ***********/

+#define HRTIM_EEFR1_EE1LTCH_Pos       (0U)

+#define HRTIM_EEFR1_EE1LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos)       /*!< 0x00000001 */

+#define HRTIM_EEFR1_EE1LTCH           HRTIM_EEFR1_EE1LTCH_Msk                  /*!< External Event 1 latch */

+#define HRTIM_EEFR1_EE1FLTR_Pos       (1U)

+#define HRTIM_EEFR1_EE1FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos)       /*!< 0x0000001E */

+#define HRTIM_EEFR1_EE1FLTR           HRTIM_EEFR1_EE1FLTR_Msk                  /*!< External Event 1 filter mask */

+#define HRTIM_EEFR1_EE1FLTR_0         (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000002 */

+#define HRTIM_EEFR1_EE1FLTR_1         (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000004 */

+#define HRTIM_EEFR1_EE1FLTR_2         (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000008 */

+#define HRTIM_EEFR1_EE1FLTR_3         (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000010 */

+

+#define HRTIM_EEFR1_EE2LTCH_Pos       (6U)

+#define HRTIM_EEFR1_EE2LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos)       /*!< 0x00000040 */

+#define HRTIM_EEFR1_EE2LTCH           HRTIM_EEFR1_EE2LTCH_Msk                  /*!< External Event 2 latch */

+#define HRTIM_EEFR1_EE2FLTR_Pos       (7U)

+#define HRTIM_EEFR1_EE2FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos)       /*!< 0x00000780 */

+#define HRTIM_EEFR1_EE2FLTR           HRTIM_EEFR1_EE2FLTR_Msk                  /*!< External Event 2 filter mask */

+#define HRTIM_EEFR1_EE2FLTR_0         (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000080 */

+#define HRTIM_EEFR1_EE2FLTR_1         (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000100 */

+#define HRTIM_EEFR1_EE2FLTR_2         (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000200 */

+#define HRTIM_EEFR1_EE2FLTR_3         (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000400 */

+

+#define HRTIM_EEFR1_EE3LTCH_Pos       (12U)

+#define HRTIM_EEFR1_EE3LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos)       /*!< 0x00001000 */

+#define HRTIM_EEFR1_EE3LTCH           HRTIM_EEFR1_EE3LTCH_Msk                  /*!< External Event 3 latch */

+#define HRTIM_EEFR1_EE3FLTR_Pos       (13U)

+#define HRTIM_EEFR1_EE3FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos)       /*!< 0x0001E000 */

+#define HRTIM_EEFR1_EE3FLTR           HRTIM_EEFR1_EE3FLTR_Msk                  /*!< External Event 3 filter mask */

+#define HRTIM_EEFR1_EE3FLTR_0         (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00002000 */

+#define HRTIM_EEFR1_EE3FLTR_1         (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00004000 */

+#define HRTIM_EEFR1_EE3FLTR_2         (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00008000 */

+#define HRTIM_EEFR1_EE3FLTR_3         (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00010000 */

+

+#define HRTIM_EEFR1_EE4LTCH_Pos       (18U)

+#define HRTIM_EEFR1_EE4LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos)       /*!< 0x00040000 */

+#define HRTIM_EEFR1_EE4LTCH           HRTIM_EEFR1_EE4LTCH_Msk                  /*!< External Event 4 latch */

+#define HRTIM_EEFR1_EE4FLTR_Pos       (19U)

+#define HRTIM_EEFR1_EE4FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos)       /*!< 0x00780000 */

+#define HRTIM_EEFR1_EE4FLTR           HRTIM_EEFR1_EE4FLTR_Msk                  /*!< External Event 4 filter mask */

+#define HRTIM_EEFR1_EE4FLTR_0         (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00080000 */

+#define HRTIM_EEFR1_EE4FLTR_1         (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00100000 */

+#define HRTIM_EEFR1_EE4FLTR_2         (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00200000 */

+#define HRTIM_EEFR1_EE4FLTR_3         (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00400000 */

+

+#define HRTIM_EEFR1_EE5LTCH_Pos       (24U)

+#define HRTIM_EEFR1_EE5LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos)       /*!< 0x01000000 */

+#define HRTIM_EEFR1_EE5LTCH           HRTIM_EEFR1_EE5LTCH_Msk                  /*!< External Event 5 latch */

+#define HRTIM_EEFR1_EE5FLTR_Pos       (25U)

+#define HRTIM_EEFR1_EE5FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos)       /*!< 0x1E000000 */

+#define HRTIM_EEFR1_EE5FLTR           HRTIM_EEFR1_EE5FLTR_Msk                  /*!< External Event 5 filter mask */

+#define HRTIM_EEFR1_EE5FLTR_0         (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x02000000 */

+#define HRTIM_EEFR1_EE5FLTR_1         (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x04000000 */

+#define HRTIM_EEFR1_EE5FLTR_2         (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x08000000 */

+#define HRTIM_EEFR1_EE5FLTR_3         (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x10000000 */

+

+/**** Bit definition for Slave external event filtering  register 2 ***********/

+#define HRTIM_EEFR2_EE6LTCH_Pos       (0U)

+#define HRTIM_EEFR2_EE6LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos)       /*!< 0x00000001 */

+#define HRTIM_EEFR2_EE6LTCH           HRTIM_EEFR2_EE6LTCH_Msk                  /*!< External Event 6 latch */

+#define HRTIM_EEFR2_EE6FLTR_Pos       (1U)

+#define HRTIM_EEFR2_EE6FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos)       /*!< 0x0000001E */

+#define HRTIM_EEFR2_EE6FLTR           HRTIM_EEFR2_EE6FLTR_Msk                  /*!< External Event 6 filter mask */

+#define HRTIM_EEFR2_EE6FLTR_0         (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000002 */

+#define HRTIM_EEFR2_EE6FLTR_1         (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000004 */

+#define HRTIM_EEFR2_EE6FLTR_2         (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000008 */

+#define HRTIM_EEFR2_EE6FLTR_3         (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000010 */

+

+#define HRTIM_EEFR2_EE7LTCH_Pos       (6U)

+#define HRTIM_EEFR2_EE7LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos)       /*!< 0x00000040 */

+#define HRTIM_EEFR2_EE7LTCH           HRTIM_EEFR2_EE7LTCH_Msk                  /*!< External Event 7 latch */

+#define HRTIM_EEFR2_EE7FLTR_Pos       (7U)

+#define HRTIM_EEFR2_EE7FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos)       /*!< 0x00000780 */

+#define HRTIM_EEFR2_EE7FLTR           HRTIM_EEFR2_EE7FLTR_Msk                  /*!< External Event 7 filter mask */

+#define HRTIM_EEFR2_EE7FLTR_0         (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000080 */

+#define HRTIM_EEFR2_EE7FLTR_1         (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000100 */

+#define HRTIM_EEFR2_EE7FLTR_2         (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000200 */

+#define HRTIM_EEFR2_EE7FLTR_3         (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000400 */

+

+#define HRTIM_EEFR2_EE8LTCH_Pos       (12U)

+#define HRTIM_EEFR2_EE8LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos)       /*!< 0x00001000 */

+#define HRTIM_EEFR2_EE8LTCH           HRTIM_EEFR2_EE8LTCH_Msk                  /*!< External Event 8 latch */

+#define HRTIM_EEFR2_EE8FLTR_Pos       (13U)

+#define HRTIM_EEFR2_EE8FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos)       /*!< 0x0001E000 */

+#define HRTIM_EEFR2_EE8FLTR           HRTIM_EEFR2_EE8FLTR_Msk                  /*!< External Event 8 filter mask */

+#define HRTIM_EEFR2_EE8FLTR_0         (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00002000 */

+#define HRTIM_EEFR2_EE8FLTR_1         (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00004000 */

+#define HRTIM_EEFR2_EE8FLTR_2         (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00008000 */

+#define HRTIM_EEFR2_EE8FLTR_3         (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00010000 */

+

+#define HRTIM_EEFR2_EE9LTCH_Pos       (18U)

+#define HRTIM_EEFR2_EE9LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos)       /*!< 0x00040000 */

+#define HRTIM_EEFR2_EE9LTCH           HRTIM_EEFR2_EE9LTCH_Msk                  /*!< External Event 9 latch */

+#define HRTIM_EEFR2_EE9FLTR_Pos       (19U)

+#define HRTIM_EEFR2_EE9FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos)       /*!< 0x00780000 */

+#define HRTIM_EEFR2_EE9FLTR           HRTIM_EEFR2_EE9FLTR_Msk                  /*!< External Event 9 filter mask */

+#define HRTIM_EEFR2_EE9FLTR_0         (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00080000 */

+#define HRTIM_EEFR2_EE9FLTR_1         (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00100000 */

+#define HRTIM_EEFR2_EE9FLTR_2         (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00200000 */

+#define HRTIM_EEFR2_EE9FLTR_3         (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00400000 */

+

+#define HRTIM_EEFR2_EE10LTCH_Pos      (24U)

+#define HRTIM_EEFR2_EE10LTCH_Msk      (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos)      /*!< 0x01000000 */

+#define HRTIM_EEFR2_EE10LTCH          HRTIM_EEFR2_EE10LTCH_Msk                 /*!< External Event 10 latch */

+#define HRTIM_EEFR2_EE10FLTR_Pos      (25U)

+#define HRTIM_EEFR2_EE10FLTR_Msk      (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos)      /*!< 0x1E000000 */

+#define HRTIM_EEFR2_EE10FLTR          HRTIM_EEFR2_EE10FLTR_Msk                 /*!< External Event 10 filter mask */

+#define HRTIM_EEFR2_EE10FLTR_0        (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x02000000 */

+#define HRTIM_EEFR2_EE10FLTR_1        (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x04000000 */

+#define HRTIM_EEFR2_EE10FLTR_2        (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x08000000 */

+#define HRTIM_EEFR2_EE10FLTR_3        (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x10000000 */

+

+/**** Bit definition for Slave Timer reset register ***************************/

+#define HRTIM_RSTR_UPDATE_Pos         (1U)

+#define HRTIM_RSTR_UPDATE_Msk         (0x1UL << HRTIM_RSTR_UPDATE_Pos)         /*!< 0x00000002 */

+#define HRTIM_RSTR_UPDATE             HRTIM_RSTR_UPDATE_Msk                    /*!< Timer update */

+#define HRTIM_RSTR_CMP2_Pos           (2U)

+#define HRTIM_RSTR_CMP2_Msk           (0x1UL << HRTIM_RSTR_CMP2_Pos)           /*!< 0x00000004 */

+#define HRTIM_RSTR_CMP2               HRTIM_RSTR_CMP2_Msk                      /*!< Timer compare2 */

+#define HRTIM_RSTR_CMP4_Pos           (3U)

+#define HRTIM_RSTR_CMP4_Msk           (0x1UL << HRTIM_RSTR_CMP4_Pos)           /*!< 0x00000008 */

+#define HRTIM_RSTR_CMP4               HRTIM_RSTR_CMP4_Msk                      /*!< Timer compare4 */

+

+#define HRTIM_RSTR_MSTPER_Pos         (4U)

+#define HRTIM_RSTR_MSTPER_Msk         (0x1UL << HRTIM_RSTR_MSTPER_Pos)         /*!< 0x00000010 */

+#define HRTIM_RSTR_MSTPER             HRTIM_RSTR_MSTPER_Msk                    /*!< Master period */

+#define HRTIM_RSTR_MSTCMP1_Pos        (5U)

+#define HRTIM_RSTR_MSTCMP1_Msk        (0x1UL << HRTIM_RSTR_MSTCMP1_Pos)        /*!< 0x00000020 */

+#define HRTIM_RSTR_MSTCMP1            HRTIM_RSTR_MSTCMP1_Msk                   /*!< Master compare1 */

+#define HRTIM_RSTR_MSTCMP2_Pos        (6U)

+#define HRTIM_RSTR_MSTCMP2_Msk        (0x1UL << HRTIM_RSTR_MSTCMP2_Pos)        /*!< 0x00000040 */

+#define HRTIM_RSTR_MSTCMP2            HRTIM_RSTR_MSTCMP2_Msk                   /*!< Master compare2 */

+#define HRTIM_RSTR_MSTCMP3_Pos        (7U)

+#define HRTIM_RSTR_MSTCMP3_Msk        (0x1UL << HRTIM_RSTR_MSTCMP3_Pos)        /*!< 0x00000080 */

+#define HRTIM_RSTR_MSTCMP3            HRTIM_RSTR_MSTCMP3_Msk                   /*!< Master compare3 */

+#define HRTIM_RSTR_MSTCMP4_Pos        (8U)

+#define HRTIM_RSTR_MSTCMP4_Msk        (0x1UL << HRTIM_RSTR_MSTCMP4_Pos)        /*!< 0x00000100 */

+#define HRTIM_RSTR_MSTCMP4            HRTIM_RSTR_MSTCMP4_Msk                   /*!< Master compare4 */

+

+#define HRTIM_RSTR_EXTEVNT1_Pos       (9U)

+#define HRTIM_RSTR_EXTEVNT1_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos)       /*!< 0x00000200 */

+#define HRTIM_RSTR_EXTEVNT1           HRTIM_RSTR_EXTEVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_RSTR_EXTEVNT2_Pos       (10U)

+#define HRTIM_RSTR_EXTEVNT2_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos)       /*!< 0x00000400 */

+#define HRTIM_RSTR_EXTEVNT2           HRTIM_RSTR_EXTEVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_RSTR_EXTEVNT3_Pos       (11U)

+#define HRTIM_RSTR_EXTEVNT3_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos)       /*!< 0x00000800 */

+#define HRTIM_RSTR_EXTEVNT3           HRTIM_RSTR_EXTEVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_RSTR_EXTEVNT4_Pos       (12U)

+#define HRTIM_RSTR_EXTEVNT4_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos)       /*!< 0x00001000 */

+#define HRTIM_RSTR_EXTEVNT4           HRTIM_RSTR_EXTEVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_RSTR_EXTEVNT5_Pos       (13U)

+#define HRTIM_RSTR_EXTEVNT5_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos)       /*!< 0x00002000 */

+#define HRTIM_RSTR_EXTEVNT5           HRTIM_RSTR_EXTEVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_RSTR_EXTEVNT6_Pos       (14U)

+#define HRTIM_RSTR_EXTEVNT6_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos)       /*!< 0x00004000 */

+#define HRTIM_RSTR_EXTEVNT6           HRTIM_RSTR_EXTEVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_RSTR_EXTEVNT7_Pos       (15U)

+#define HRTIM_RSTR_EXTEVNT7_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos)       /*!< 0x00008000 */

+#define HRTIM_RSTR_EXTEVNT7           HRTIM_RSTR_EXTEVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_RSTR_EXTEVNT8_Pos       (16U)

+#define HRTIM_RSTR_EXTEVNT8_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos)       /*!< 0x00010000 */

+#define HRTIM_RSTR_EXTEVNT8           HRTIM_RSTR_EXTEVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_RSTR_EXTEVNT9_Pos       (17U)

+#define HRTIM_RSTR_EXTEVNT9_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos)       /*!< 0x00020000 */

+#define HRTIM_RSTR_EXTEVNT9           HRTIM_RSTR_EXTEVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_RSTR_EXTEVNT10_Pos      (18U)

+#define HRTIM_RSTR_EXTEVNT10_Msk      (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos)      /*!< 0x00040000 */

+#define HRTIM_RSTR_EXTEVNT10          HRTIM_RSTR_EXTEVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_RSTR_TIMBCMP1_Pos       (19U)

+#define HRTIM_RSTR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos)       /*!< 0x00080000 */

+#define HRTIM_RSTR_TIMBCMP1           HRTIM_RSTR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */

+#define HRTIM_RSTR_TIMBCMP2_Pos       (20U)

+#define HRTIM_RSTR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos)       /*!< 0x00100000 */

+#define HRTIM_RSTR_TIMBCMP2           HRTIM_RSTR_TIMBCMP2_Msk                  /*!< Timer B compare 2 */

+#define HRTIM_RSTR_TIMBCMP4_Pos       (21U)

+#define HRTIM_RSTR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos)       /*!< 0x00200000 */

+#define HRTIM_RSTR_TIMBCMP4           HRTIM_RSTR_TIMBCMP4_Msk                  /*!< Timer B compare 4 */

+

+#define HRTIM_RSTR_TIMCCMP1_Pos       (22U)

+#define HRTIM_RSTR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos)       /*!< 0x00400000 */

+#define HRTIM_RSTR_TIMCCMP1           HRTIM_RSTR_TIMCCMP1_Msk                  /*!< Timer C compare 1 */

+#define HRTIM_RSTR_TIMCCMP2_Pos       (23U)

+#define HRTIM_RSTR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos)       /*!< 0x00800000 */

+#define HRTIM_RSTR_TIMCCMP2           HRTIM_RSTR_TIMCCMP2_Msk                  /*!< Timer C compare 2 */

+#define HRTIM_RSTR_TIMCCMP4_Pos       (24U)

+#define HRTIM_RSTR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos)       /*!< 0x01000000 */

+#define HRTIM_RSTR_TIMCCMP4           HRTIM_RSTR_TIMCCMP4_Msk                  /*!< Timer C compare 4 */

+

+#define HRTIM_RSTR_TIMDCMP1_Pos       (25U)

+#define HRTIM_RSTR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos)       /*!< 0x02000000 */

+#define HRTIM_RSTR_TIMDCMP1           HRTIM_RSTR_TIMDCMP1_Msk                  /*!< Timer D compare 1 */

+#define HRTIM_RSTR_TIMDCMP2_Pos       (26U)

+#define HRTIM_RSTR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos)       /*!< 0x04000000 */

+#define HRTIM_RSTR_TIMDCMP2           HRTIM_RSTR_TIMDCMP2_Msk                  /*!< Timer D compare 2 */

+#define HRTIM_RSTR_TIMDCMP4_Pos       (27U)

+#define HRTIM_RSTR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos)       /*!< 0x08000000 */

+#define HRTIM_RSTR_TIMDCMP4           HRTIM_RSTR_TIMDCMP4_Msk                  /*!< Timer D compare 4 */

+

+#define HRTIM_RSTR_TIMECMP1_Pos       (28U)

+#define HRTIM_RSTR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTR_TIMECMP1_Pos)       /*!< 0x10000000 */

+#define HRTIM_RSTR_TIMECMP1           HRTIM_RSTR_TIMECMP1_Msk                  /*!< Timer E compare 1 */

+#define HRTIM_RSTR_TIMECMP2_Pos       (29U)

+#define HRTIM_RSTR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTR_TIMECMP2_Pos)       /*!< 0x20000000 */

+#define HRTIM_RSTR_TIMECMP2           HRTIM_RSTR_TIMECMP2_Msk                  /*!< Timer E compare 2 */

+#define HRTIM_RSTR_TIMECMP4_Pos       (30U)

+#define HRTIM_RSTR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTR_TIMECMP4_Pos)       /*!< 0x40000000 */

+#define HRTIM_RSTR_TIMECMP4           HRTIM_RSTR_TIMECMP4_Msk                  /*!< Timer E compare 4 */

+

+/**** Bit definition for Slave Timer Chopper register *************************/

+#define HRTIM_CHPR_CARFRQ_Pos         (0U)

+#define HRTIM_CHPR_CARFRQ_Msk         (0xFUL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x0000000F */

+#define HRTIM_CHPR_CARFRQ             HRTIM_CHPR_CARFRQ_Msk                    /*!< Timer carrier frequency value */

+#define HRTIM_CHPR_CARFRQ_0           (0x1UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000001 */

+#define HRTIM_CHPR_CARFRQ_1           (0x2UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000002 */

+#define HRTIM_CHPR_CARFRQ_2           (0x4UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000004 */

+#define HRTIM_CHPR_CARFRQ_3           (0x8UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000008 */

+

+#define HRTIM_CHPR_CARDTY_Pos         (4U)

+#define HRTIM_CHPR_CARDTY_Msk         (0x7UL << HRTIM_CHPR_CARDTY_Pos)         /*!< 0x00000070 */

+#define HRTIM_CHPR_CARDTY             HRTIM_CHPR_CARDTY_Msk                    /*!< Timer chopper duty cycle value */

+#define HRTIM_CHPR_CARDTY_0           (0x1UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000010 */

+#define HRTIM_CHPR_CARDTY_1           (0x2UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000020 */

+#define HRTIM_CHPR_CARDTY_2           (0x4UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000040 */

+

+#define HRTIM_CHPR_STRPW_Pos          (7U)

+#define HRTIM_CHPR_STRPW_Msk          (0xFUL << HRTIM_CHPR_STRPW_Pos)          /*!< 0x00000780 */

+#define HRTIM_CHPR_STRPW              HRTIM_CHPR_STRPW_Msk                     /*!< Timer start pulse width value */

+#define HRTIM_CHPR_STRPW_0            (0x1UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000080 */

+#define HRTIM_CHPR_STRPW_1            (0x2UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000100 */

+#define HRTIM_CHPR_STRPW_2            (0x4UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000200 */

+#define HRTIM_CHPR_STRPW_3            (0x8UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000400 */

+

+/**** Bit definition for Slave Timer Capture 1 control register ***************/

+#define HRTIM_CPT1CR_SWCPT_Pos        (0U)

+#define HRTIM_CPT1CR_SWCPT_Msk        (0x1UL << HRTIM_CPT1CR_SWCPT_Pos)        /*!< 0x00000001 */

+#define HRTIM_CPT1CR_SWCPT            HRTIM_CPT1CR_SWCPT_Msk                   /*!< Software capture */

+#define HRTIM_CPT1CR_UPDCPT_Pos       (1U)

+#define HRTIM_CPT1CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos)       /*!< 0x00000002 */

+#define HRTIM_CPT1CR_UPDCPT           HRTIM_CPT1CR_UPDCPT_Msk                  /*!< Update capture */

+#define HRTIM_CPT1CR_EXEV1CPT_Pos     (2U)

+#define HRTIM_CPT1CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos)     /*!< 0x00000004 */

+#define HRTIM_CPT1CR_EXEV1CPT         HRTIM_CPT1CR_EXEV1CPT_Msk                /*!< External event 1 capture */

+#define HRTIM_CPT1CR_EXEV2CPT_Pos     (3U)

+#define HRTIM_CPT1CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos)     /*!< 0x00000008 */

+#define HRTIM_CPT1CR_EXEV2CPT         HRTIM_CPT1CR_EXEV2CPT_Msk                /*!< External event 2 capture */

+#define HRTIM_CPT1CR_EXEV3CPT_Pos     (4U)

+#define HRTIM_CPT1CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos)     /*!< 0x00000010 */

+#define HRTIM_CPT1CR_EXEV3CPT         HRTIM_CPT1CR_EXEV3CPT_Msk                /*!< External event 3 capture */

+#define HRTIM_CPT1CR_EXEV4CPT_Pos     (5U)

+#define HRTIM_CPT1CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos)     /*!< 0x00000020 */

+#define HRTIM_CPT1CR_EXEV4CPT         HRTIM_CPT1CR_EXEV4CPT_Msk                /*!< External event 4 capture */

+#define HRTIM_CPT1CR_EXEV5CPT_Pos     (6U)

+#define HRTIM_CPT1CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos)     /*!< 0x00000040 */

+#define HRTIM_CPT1CR_EXEV5CPT         HRTIM_CPT1CR_EXEV5CPT_Msk                /*!< External event 5 capture */

+#define HRTIM_CPT1CR_EXEV6CPT_Pos     (7U)

+#define HRTIM_CPT1CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos)     /*!< 0x00000080 */

+#define HRTIM_CPT1CR_EXEV6CPT         HRTIM_CPT1CR_EXEV6CPT_Msk                /*!< External event 6 capture */

+#define HRTIM_CPT1CR_EXEV7CPT_Pos     (8U)

+#define HRTIM_CPT1CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos)     /*!< 0x00000100 */

+#define HRTIM_CPT1CR_EXEV7CPT         HRTIM_CPT1CR_EXEV7CPT_Msk                /*!< External event 7 capture */

+#define HRTIM_CPT1CR_EXEV8CPT_Pos     (9U)

+#define HRTIM_CPT1CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos)     /*!< 0x00000200 */

+#define HRTIM_CPT1CR_EXEV8CPT         HRTIM_CPT1CR_EXEV8CPT_Msk                /*!< External event 8 capture */

+#define HRTIM_CPT1CR_EXEV9CPT_Pos     (10U)

+#define HRTIM_CPT1CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos)     /*!< 0x00000400 */

+#define HRTIM_CPT1CR_EXEV9CPT         HRTIM_CPT1CR_EXEV9CPT_Msk                /*!< External event 9 capture */

+#define HRTIM_CPT1CR_EXEV10CPT_Pos    (11U)

+#define HRTIM_CPT1CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos)    /*!< 0x00000800 */

+#define HRTIM_CPT1CR_EXEV10CPT        HRTIM_CPT1CR_EXEV10CPT_Msk               /*!< External event 10 capture */

+

+#define HRTIM_CPT1CR_TA1SET_Pos       (12U)

+#define HRTIM_CPT1CR_TA1SET_Msk       (0x1UL << HRTIM_CPT1CR_TA1SET_Pos)       /*!< 0x00001000 */

+#define HRTIM_CPT1CR_TA1SET           HRTIM_CPT1CR_TA1SET_Msk                  /*!< Timer A output 1 set */

+#define HRTIM_CPT1CR_TA1RST_Pos       (13U)

+#define HRTIM_CPT1CR_TA1RST_Msk       (0x1UL << HRTIM_CPT1CR_TA1RST_Pos)       /*!< 0x00002000 */

+#define HRTIM_CPT1CR_TA1RST           HRTIM_CPT1CR_TA1RST_Msk                  /*!< Timer A output 1 reset */

+#define HRTIM_CPT1CR_TIMACMP1_Pos     (14U)

+#define HRTIM_CPT1CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos)     /*!< 0x00004000 */

+#define HRTIM_CPT1CR_TIMACMP1         HRTIM_CPT1CR_TIMACMP1_Msk                /*!< Timer A compare 1 */

+#define HRTIM_CPT1CR_TIMACMP2_Pos     (15U)

+#define HRTIM_CPT1CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos)     /*!< 0x00008000 */

+#define HRTIM_CPT1CR_TIMACMP2         HRTIM_CPT1CR_TIMACMP2_Msk                /*!< Timer A compare 2 */

+

+#define HRTIM_CPT1CR_TB1SET_Pos       (16U)

+#define HRTIM_CPT1CR_TB1SET_Msk       (0x1UL << HRTIM_CPT1CR_TB1SET_Pos)       /*!< 0x00010000 */

+#define HRTIM_CPT1CR_TB1SET           HRTIM_CPT1CR_TB1SET_Msk                  /*!< Timer B output 1 set */

+#define HRTIM_CPT1CR_TB1RST_Pos       (17U)

+#define HRTIM_CPT1CR_TB1RST_Msk       (0x1UL << HRTIM_CPT1CR_TB1RST_Pos)       /*!< 0x00020000 */

+#define HRTIM_CPT1CR_TB1RST           HRTIM_CPT1CR_TB1RST_Msk                  /*!< Timer B output 1 reset */

+#define HRTIM_CPT1CR_TIMBCMP1_Pos     (18U)

+#define HRTIM_CPT1CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos)     /*!< 0x00040000 */

+#define HRTIM_CPT1CR_TIMBCMP1         HRTIM_CPT1CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */

+#define HRTIM_CPT1CR_TIMBCMP2_Pos     (19U)

+#define HRTIM_CPT1CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos)     /*!< 0x00080000 */

+#define HRTIM_CPT1CR_TIMBCMP2         HRTIM_CPT1CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */

+

+#define HRTIM_CPT1CR_TC1SET_Pos       (20U)

+#define HRTIM_CPT1CR_TC1SET_Msk       (0x1UL << HRTIM_CPT1CR_TC1SET_Pos)       /*!< 0x00100000 */

+#define HRTIM_CPT1CR_TC1SET           HRTIM_CPT1CR_TC1SET_Msk                  /*!< Timer C output 1 set */

+#define HRTIM_CPT1CR_TC1RST_Pos       (21U)

+#define HRTIM_CPT1CR_TC1RST_Msk       (0x1UL << HRTIM_CPT1CR_TC1RST_Pos)       /*!< 0x00200000 */

+#define HRTIM_CPT1CR_TC1RST           HRTIM_CPT1CR_TC1RST_Msk                  /*!< Timer C output 1 reset */

+#define HRTIM_CPT1CR_TIMCCMP1_Pos     (22U)

+#define HRTIM_CPT1CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos)     /*!< 0x00400000 */

+#define HRTIM_CPT1CR_TIMCCMP1         HRTIM_CPT1CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */

+#define HRTIM_CPT1CR_TIMCCMP2_Pos     (23U)

+#define HRTIM_CPT1CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos)     /*!< 0x00800000 */

+#define HRTIM_CPT1CR_TIMCCMP2         HRTIM_CPT1CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */

+

+#define HRTIM_CPT1CR_TD1SET_Pos       (24U)

+#define HRTIM_CPT1CR_TD1SET_Msk       (0x1UL << HRTIM_CPT1CR_TD1SET_Pos)       /*!< 0x01000000 */

+#define HRTIM_CPT1CR_TD1SET           HRTIM_CPT1CR_TD1SET_Msk                  /*!< Timer D output 1 set */

+#define HRTIM_CPT1CR_TD1RST_Pos       (25U)

+#define HRTIM_CPT1CR_TD1RST_Msk       (0x1UL << HRTIM_CPT1CR_TD1RST_Pos)       /*!< 0x02000000 */

+#define HRTIM_CPT1CR_TD1RST           HRTIM_CPT1CR_TD1RST_Msk                  /*!< Timer D output 1 reset */

+#define HRTIM_CPT1CR_TIMDCMP1_Pos     (26U)

+#define HRTIM_CPT1CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos)     /*!< 0x04000000 */

+#define HRTIM_CPT1CR_TIMDCMP1         HRTIM_CPT1CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */

+#define HRTIM_CPT1CR_TIMDCMP2_Pos     (27U)

+#define HRTIM_CPT1CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos)     /*!< 0x08000000 */

+#define HRTIM_CPT1CR_TIMDCMP2         HRTIM_CPT1CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */

+

+#define HRTIM_CPT1CR_TE1SET_Pos       (28U)

+#define HRTIM_CPT1CR_TE1SET_Msk       (0x1UL << HRTIM_CPT1CR_TE1SET_Pos)       /*!< 0x10000000 */

+#define HRTIM_CPT1CR_TE1SET           HRTIM_CPT1CR_TE1SET_Msk                  /*!< Timer E output 1 set */

+#define HRTIM_CPT1CR_TE1RST_Pos       (29U)

+#define HRTIM_CPT1CR_TE1RST_Msk       (0x1UL << HRTIM_CPT1CR_TE1RST_Pos)       /*!< 0x20000000 */

+#define HRTIM_CPT1CR_TE1RST           HRTIM_CPT1CR_TE1RST_Msk                  /*!< Timer E output 1 reset */

+#define HRTIM_CPT1CR_TIMECMP1_Pos     (30U)

+#define HRTIM_CPT1CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos)     /*!< 0x40000000 */

+#define HRTIM_CPT1CR_TIMECMP1         HRTIM_CPT1CR_TIMECMP1_Msk                /*!< Timer E compare 1 */

+#define HRTIM_CPT1CR_TIMECMP2_Pos     (31U)

+#define HRTIM_CPT1CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos)     /*!< 0x80000000 */

+#define HRTIM_CPT1CR_TIMECMP2         HRTIM_CPT1CR_TIMECMP2_Msk                /*!< Timer E compare 2 */

+

+/**** Bit definition for Slave Timer Capture 2 control register ***************/

+#define HRTIM_CPT2CR_SWCPT_Pos        (0U)

+#define HRTIM_CPT2CR_SWCPT_Msk        (0x1UL << HRTIM_CPT2CR_SWCPT_Pos)        /*!< 0x00000001 */

+#define HRTIM_CPT2CR_SWCPT            HRTIM_CPT2CR_SWCPT_Msk                   /*!< Software capture */

+#define HRTIM_CPT2CR_UPDCPT_Pos       (1U)

+#define HRTIM_CPT2CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos)       /*!< 0x00000002 */

+#define HRTIM_CPT2CR_UPDCPT           HRTIM_CPT2CR_UPDCPT_Msk                  /*!< Update capture */

+#define HRTIM_CPT2CR_EXEV1CPT_Pos     (2U)

+#define HRTIM_CPT2CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos)     /*!< 0x00000004 */

+#define HRTIM_CPT2CR_EXEV1CPT         HRTIM_CPT2CR_EXEV1CPT_Msk                /*!< External event 1 capture */

+#define HRTIM_CPT2CR_EXEV2CPT_Pos     (3U)

+#define HRTIM_CPT2CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos)     /*!< 0x00000008 */

+#define HRTIM_CPT2CR_EXEV2CPT         HRTIM_CPT2CR_EXEV2CPT_Msk                /*!< External event 2 capture */

+#define HRTIM_CPT2CR_EXEV3CPT_Pos     (4U)

+#define HRTIM_CPT2CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos)     /*!< 0x00000010 */

+#define HRTIM_CPT2CR_EXEV3CPT         HRTIM_CPT2CR_EXEV3CPT_Msk                /*!< External event 3 capture */

+#define HRTIM_CPT2CR_EXEV4CPT_Pos     (5U)

+#define HRTIM_CPT2CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos)     /*!< 0x00000020 */

+#define HRTIM_CPT2CR_EXEV4CPT         HRTIM_CPT2CR_EXEV4CPT_Msk                /*!< External event 4 capture */

+#define HRTIM_CPT2CR_EXEV5CPT_Pos     (6U)

+#define HRTIM_CPT2CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos)     /*!< 0x00000040 */

+#define HRTIM_CPT2CR_EXEV5CPT         HRTIM_CPT2CR_EXEV5CPT_Msk                /*!< External event 5 capture */

+#define HRTIM_CPT2CR_EXEV6CPT_Pos     (7U)

+#define HRTIM_CPT2CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos)     /*!< 0x00000080 */

+#define HRTIM_CPT2CR_EXEV6CPT         HRTIM_CPT2CR_EXEV6CPT_Msk                /*!< External event 6 capture */

+#define HRTIM_CPT2CR_EXEV7CPT_Pos     (8U)

+#define HRTIM_CPT2CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos)     /*!< 0x00000100 */

+#define HRTIM_CPT2CR_EXEV7CPT         HRTIM_CPT2CR_EXEV7CPT_Msk                /*!< External event 7 capture */

+#define HRTIM_CPT2CR_EXEV8CPT_Pos     (9U)

+#define HRTIM_CPT2CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos)     /*!< 0x00000200 */

+#define HRTIM_CPT2CR_EXEV8CPT         HRTIM_CPT2CR_EXEV8CPT_Msk                /*!< External event 8 capture */

+#define HRTIM_CPT2CR_EXEV9CPT_Pos     (10U)

+#define HRTIM_CPT2CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos)     /*!< 0x00000400 */

+#define HRTIM_CPT2CR_EXEV9CPT         HRTIM_CPT2CR_EXEV9CPT_Msk                /*!< External event 9 capture */

+#define HRTIM_CPT2CR_EXEV10CPT_Pos    (11U)

+#define HRTIM_CPT2CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos)    /*!< 0x00000800 */

+#define HRTIM_CPT2CR_EXEV10CPT        HRTIM_CPT2CR_EXEV10CPT_Msk               /*!< External event 10 capture */

+

+#define HRTIM_CPT2CR_TA1SET_Pos       (12U)

+#define HRTIM_CPT2CR_TA1SET_Msk       (0x1UL << HRTIM_CPT2CR_TA1SET_Pos)       /*!< 0x00001000 */

+#define HRTIM_CPT2CR_TA1SET           HRTIM_CPT2CR_TA1SET_Msk                  /*!< Timer A output 1 set */

+#define HRTIM_CPT2CR_TA1RST_Pos       (13U)

+#define HRTIM_CPT2CR_TA1RST_Msk       (0x1UL << HRTIM_CPT2CR_TA1RST_Pos)       /*!< 0x00002000 */

+#define HRTIM_CPT2CR_TA1RST           HRTIM_CPT2CR_TA1RST_Msk                  /*!< Timer A output 1 reset */

+#define HRTIM_CPT2CR_TIMACMP1_Pos     (14U)

+#define HRTIM_CPT2CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos)     /*!< 0x00004000 */

+#define HRTIM_CPT2CR_TIMACMP1         HRTIM_CPT2CR_TIMACMP1_Msk                /*!< Timer A compare 1 */

+#define HRTIM_CPT2CR_TIMACMP2_Pos     (15U)

+#define HRTIM_CPT2CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos)     /*!< 0x00008000 */

+#define HRTIM_CPT2CR_TIMACMP2         HRTIM_CPT2CR_TIMACMP2_Msk                /*!< Timer A compare 2 */

+

+#define HRTIM_CPT2CR_TB1SET_Pos       (16U)

+#define HRTIM_CPT2CR_TB1SET_Msk       (0x1UL << HRTIM_CPT2CR_TB1SET_Pos)       /*!< 0x00010000 */

+#define HRTIM_CPT2CR_TB1SET           HRTIM_CPT2CR_TB1SET_Msk                  /*!< Timer B output 1 set */

+#define HRTIM_CPT2CR_TB1RST_Pos       (17U)

+#define HRTIM_CPT2CR_TB1RST_Msk       (0x1UL << HRTIM_CPT2CR_TB1RST_Pos)       /*!< 0x00020000 */

+#define HRTIM_CPT2CR_TB1RST           HRTIM_CPT2CR_TB1RST_Msk                  /*!< Timer B output 1 reset */

+#define HRTIM_CPT2CR_TIMBCMP1_Pos     (18U)

+#define HRTIM_CPT2CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos)     /*!< 0x00040000 */

+#define HRTIM_CPT2CR_TIMBCMP1         HRTIM_CPT2CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */

+#define HRTIM_CPT2CR_TIMBCMP2_Pos     (19U)

+#define HRTIM_CPT2CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos)     /*!< 0x00080000 */

+#define HRTIM_CPT2CR_TIMBCMP2         HRTIM_CPT2CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */

+

+#define HRTIM_CPT2CR_TC1SET_Pos       (20U)

+#define HRTIM_CPT2CR_TC1SET_Msk       (0x1UL << HRTIM_CPT2CR_TC1SET_Pos)       /*!< 0x00100000 */

+#define HRTIM_CPT2CR_TC1SET           HRTIM_CPT2CR_TC1SET_Msk                  /*!< Timer C output 1 set */

+#define HRTIM_CPT2CR_TC1RST_Pos       (21U)

+#define HRTIM_CPT2CR_TC1RST_Msk       (0x1UL << HRTIM_CPT2CR_TC1RST_Pos)       /*!< 0x00200000 */

+#define HRTIM_CPT2CR_TC1RST           HRTIM_CPT2CR_TC1RST_Msk                  /*!< Timer C output 1 reset */

+#define HRTIM_CPT2CR_TIMCCMP1_Pos     (22U)

+#define HRTIM_CPT2CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos)     /*!< 0x00400000 */

+#define HRTIM_CPT2CR_TIMCCMP1         HRTIM_CPT2CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */

+#define HRTIM_CPT2CR_TIMCCMP2_Pos     (23U)

+#define HRTIM_CPT2CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos)     /*!< 0x00800000 */

+#define HRTIM_CPT2CR_TIMCCMP2         HRTIM_CPT2CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */

+

+#define HRTIM_CPT2CR_TD1SET_Pos       (24U)

+#define HRTIM_CPT2CR_TD1SET_Msk       (0x1UL << HRTIM_CPT2CR_TD1SET_Pos)       /*!< 0x01000000 */

+#define HRTIM_CPT2CR_TD1SET           HRTIM_CPT2CR_TD1SET_Msk                  /*!< Timer D output 1 set */

+#define HRTIM_CPT2CR_TD1RST_Pos       (25U)

+#define HRTIM_CPT2CR_TD1RST_Msk       (0x1UL << HRTIM_CPT2CR_TD1RST_Pos)       /*!< 0x02000000 */

+#define HRTIM_CPT2CR_TD1RST           HRTIM_CPT2CR_TD1RST_Msk                  /*!< Timer D output 1 reset */

+#define HRTIM_CPT2CR_TIMDCMP1_Pos     (26U)

+#define HRTIM_CPT2CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos)     /*!< 0x04000000 */

+#define HRTIM_CPT2CR_TIMDCMP1         HRTIM_CPT2CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */

+#define HRTIM_CPT2CR_TIMDCMP2_Pos     (27U)

+#define HRTIM_CPT2CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos)     /*!< 0x08000000 */

+#define HRTIM_CPT2CR_TIMDCMP2         HRTIM_CPT2CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */

+

+#define HRTIM_CPT2CR_TE1SET_Pos       (28U)

+#define HRTIM_CPT2CR_TE1SET_Msk       (0x1UL << HRTIM_CPT2CR_TE1SET_Pos)       /*!< 0x10000000 */

+#define HRTIM_CPT2CR_TE1SET           HRTIM_CPT2CR_TE1SET_Msk                  /*!< Timer E output 1 set */

+#define HRTIM_CPT2CR_TE1RST_Pos       (29U)

+#define HRTIM_CPT2CR_TE1RST_Msk       (0x1UL << HRTIM_CPT2CR_TE1RST_Pos)       /*!< 0x20000000 */

+#define HRTIM_CPT2CR_TE1RST           HRTIM_CPT2CR_TE1RST_Msk                  /*!< Timer E output 1 reset */

+#define HRTIM_CPT2CR_TIMECMP1_Pos     (30U)

+#define HRTIM_CPT2CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos)     /*!< 0x40000000 */

+#define HRTIM_CPT2CR_TIMECMP1         HRTIM_CPT2CR_TIMECMP1_Msk                /*!< Timer E compare 1 */

+#define HRTIM_CPT2CR_TIMECMP2_Pos     (31U)

+#define HRTIM_CPT2CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos)     /*!< 0x80000000 */

+#define HRTIM_CPT2CR_TIMECMP2         HRTIM_CPT2CR_TIMECMP2_Msk                /*!< Timer E compare 2 */

+

+/**** Bit definition for Slave Timer Output register **************************/

+#define HRTIM_OUTR_POL1_Pos           (1U)

+#define HRTIM_OUTR_POL1_Msk           (0x1UL << HRTIM_OUTR_POL1_Pos)           /*!< 0x00000002 */

+#define HRTIM_OUTR_POL1               HRTIM_OUTR_POL1_Msk                      /*!< Slave output 1 polarity */

+#define HRTIM_OUTR_IDLM1_Pos          (2U)

+#define HRTIM_OUTR_IDLM1_Msk          (0x1UL << HRTIM_OUTR_IDLM1_Pos)          /*!< 0x00000004 */

+#define HRTIM_OUTR_IDLM1              HRTIM_OUTR_IDLM1_Msk                     /*!< Slave output 1 idle mode */

+#define HRTIM_OUTR_IDLES1_Pos         (3U)

+#define HRTIM_OUTR_IDLES1_Msk         (0x1UL << HRTIM_OUTR_IDLES1_Pos)         /*!< 0x00000008 */

+#define HRTIM_OUTR_IDLES1             HRTIM_OUTR_IDLES1_Msk                    /*!< Slave output 1 idle state */

+#define HRTIM_OUTR_FAULT1_Pos         (4U)

+#define HRTIM_OUTR_FAULT1_Msk         (0x3UL << HRTIM_OUTR_FAULT1_Pos)         /*!< 0x00000030 */

+#define HRTIM_OUTR_FAULT1             HRTIM_OUTR_FAULT1_Msk                    /*!< Slave output 1 fault state */

+#define HRTIM_OUTR_FAULT1_0           (0x1UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000010 */

+#define HRTIM_OUTR_FAULT1_1           (0x2UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000020 */

+#define HRTIM_OUTR_CHP1_Pos           (6U)

+#define HRTIM_OUTR_CHP1_Msk           (0x1UL << HRTIM_OUTR_CHP1_Pos)           /*!< 0x00000040 */

+#define HRTIM_OUTR_CHP1               HRTIM_OUTR_CHP1_Msk                      /*!< Slave output 1 chopper enable */

+#define HRTIM_OUTR_DIDL1_Pos          (7U)

+#define HRTIM_OUTR_DIDL1_Msk          (0x1UL << HRTIM_OUTR_DIDL1_Pos)          /*!< 0x00000080 */

+#define HRTIM_OUTR_DIDL1              HRTIM_OUTR_DIDL1_Msk                     /*!< Slave output 1 dead time idle */

+

+#define HRTIM_OUTR_DTEN_Pos           (8U)

+#define HRTIM_OUTR_DTEN_Msk           (0x1UL << HRTIM_OUTR_DTEN_Pos)           /*!< 0x00000100 */

+#define HRTIM_OUTR_DTEN               HRTIM_OUTR_DTEN_Msk                      /*!< Slave output deadtime enable */

+#define HRTIM_OUTR_DLYPRTEN_Pos       (9U)

+#define HRTIM_OUTR_DLYPRTEN_Msk       (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos)       /*!< 0x00000200 */

+#define HRTIM_OUTR_DLYPRTEN           HRTIM_OUTR_DLYPRTEN_Msk                  /*!< Slave output delay protection enable */

+#define HRTIM_OUTR_DLYPRT_Pos         (10U)

+#define HRTIM_OUTR_DLYPRT_Msk         (0x7UL << HRTIM_OUTR_DLYPRT_Pos)         /*!< 0x00001C00 */

+#define HRTIM_OUTR_DLYPRT             HRTIM_OUTR_DLYPRT_Msk                    /*!< Slave output delay protection */

+#define HRTIM_OUTR_DLYPRT_0           (0x1UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000400 */

+#define HRTIM_OUTR_DLYPRT_1           (0x2UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000800 */

+#define HRTIM_OUTR_DLYPRT_2           (0x4UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00001000 */

+

+#define HRTIM_OUTR_POL2_Pos           (17U)

+#define HRTIM_OUTR_POL2_Msk           (0x1UL << HRTIM_OUTR_POL2_Pos)           /*!< 0x00020000 */

+#define HRTIM_OUTR_POL2               HRTIM_OUTR_POL2_Msk                      /*!< Slave output 2 polarity */

+#define HRTIM_OUTR_IDLM2_Pos          (18U)

+#define HRTIM_OUTR_IDLM2_Msk          (0x1UL << HRTIM_OUTR_IDLM2_Pos)          /*!< 0x00040000 */

+#define HRTIM_OUTR_IDLM2              HRTIM_OUTR_IDLM2_Msk                     /*!< Slave output 2 idle mode */

+#define HRTIM_OUTR_IDLES2_Pos         (19U)

+#define HRTIM_OUTR_IDLES2_Msk         (0x1UL << HRTIM_OUTR_IDLES2_Pos)         /*!< 0x00080000 */

+#define HRTIM_OUTR_IDLES2             HRTIM_OUTR_IDLES2_Msk                    /*!< Slave output 2 idle state */

+#define HRTIM_OUTR_FAULT2_Pos         (20U)

+#define HRTIM_OUTR_FAULT2_Msk         (0x3UL << HRTIM_OUTR_FAULT2_Pos)         /*!< 0x00300000 */

+#define HRTIM_OUTR_FAULT2             HRTIM_OUTR_FAULT2_Msk                    /*!< Slave output 2 fault state */

+#define HRTIM_OUTR_FAULT2_0           (0x1UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00100000 */

+#define HRTIM_OUTR_FAULT2_1           (0x2UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00200000 */

+#define HRTIM_OUTR_CHP2_Pos           (22U)

+#define HRTIM_OUTR_CHP2_Msk           (0x1UL << HRTIM_OUTR_CHP2_Pos)           /*!< 0x00400000 */

+#define HRTIM_OUTR_CHP2               HRTIM_OUTR_CHP2_Msk                      /*!< Slave output 2 chopper enable */

+#define HRTIM_OUTR_DIDL2_Pos          (23U)

+#define HRTIM_OUTR_DIDL2_Msk          (0x1UL << HRTIM_OUTR_DIDL2_Pos)          /*!< 0x00800000 */

+#define HRTIM_OUTR_DIDL2              HRTIM_OUTR_DIDL2_Msk                     /*!< Slave output 2 dead time idle */

+

+/**** Bit definition for Slave Timer Fault register ***************************/

+#define HRTIM_FLTR_FLT1EN_Pos         (0U)

+#define HRTIM_FLTR_FLT1EN_Msk         (0x1UL << HRTIM_FLTR_FLT1EN_Pos)         /*!< 0x00000001 */

+#define HRTIM_FLTR_FLT1EN             HRTIM_FLTR_FLT1EN_Msk                    /*!< Fault 1 enable */

+#define HRTIM_FLTR_FLT2EN_Pos         (1U)

+#define HRTIM_FLTR_FLT2EN_Msk         (0x1UL << HRTIM_FLTR_FLT2EN_Pos)         /*!< 0x00000002 */

+#define HRTIM_FLTR_FLT2EN             HRTIM_FLTR_FLT2EN_Msk                    /*!< Fault 2 enable */

+#define HRTIM_FLTR_FLT3EN_Pos         (2U)

+#define HRTIM_FLTR_FLT3EN_Msk         (0x1UL << HRTIM_FLTR_FLT3EN_Pos)         /*!< 0x00000004 */

+#define HRTIM_FLTR_FLT3EN             HRTIM_FLTR_FLT3EN_Msk                    /*!< Fault 3 enable */

+#define HRTIM_FLTR_FLT4EN_Pos         (3U)

+#define HRTIM_FLTR_FLT4EN_Msk         (0x1UL << HRTIM_FLTR_FLT4EN_Pos)         /*!< 0x00000008 */

+#define HRTIM_FLTR_FLT4EN             HRTIM_FLTR_FLT4EN_Msk                    /*!< Fault 4 enable */

+#define HRTIM_FLTR_FLT5EN_Pos         (4U)

+#define HRTIM_FLTR_FLT5EN_Msk         (0x1UL << HRTIM_FLTR_FLT5EN_Pos)         /*!< 0x00000010 */

+#define HRTIM_FLTR_FLT5EN             HRTIM_FLTR_FLT5EN_Msk                    /*!< Fault 5 enable */

+#define HRTIM_FLTR_FLTLCK_Pos         (31U)

+#define HRTIM_FLTR_FLTLCK_Msk         (0x1UL << HRTIM_FLTR_FLTLCK_Pos)         /*!< 0x80000000 */

+#define HRTIM_FLTR_FLTLCK             HRTIM_FLTR_FLTLCK_Msk                    /*!< Fault sources lock */

+

+/**** Bit definition for Common HRTIM Timer control register 1 ****************/

+#define HRTIM_CR1_MUDIS_Pos           (0U)

+#define HRTIM_CR1_MUDIS_Msk           (0x1UL << HRTIM_CR1_MUDIS_Pos)           /*!< 0x00000001 */

+#define HRTIM_CR1_MUDIS               HRTIM_CR1_MUDIS_Msk                      /*!< Master update disable*/

+#define HRTIM_CR1_TAUDIS_Pos          (1U)

+#define HRTIM_CR1_TAUDIS_Msk          (0x1UL << HRTIM_CR1_TAUDIS_Pos)          /*!< 0x00000002 */

+#define HRTIM_CR1_TAUDIS              HRTIM_CR1_TAUDIS_Msk                     /*!< Timer A update disable*/

+#define HRTIM_CR1_TBUDIS_Pos          (2U)

+#define HRTIM_CR1_TBUDIS_Msk          (0x1UL << HRTIM_CR1_TBUDIS_Pos)          /*!< 0x00000004 */

+#define HRTIM_CR1_TBUDIS              HRTIM_CR1_TBUDIS_Msk                     /*!< Timer B update disable*/

+#define HRTIM_CR1_TCUDIS_Pos          (3U)

+#define HRTIM_CR1_TCUDIS_Msk          (0x1UL << HRTIM_CR1_TCUDIS_Pos)          /*!< 0x00000008 */

+#define HRTIM_CR1_TCUDIS              HRTIM_CR1_TCUDIS_Msk                     /*!< Timer C update disable*/

+#define HRTIM_CR1_TDUDIS_Pos          (4U)

+#define HRTIM_CR1_TDUDIS_Msk          (0x1UL << HRTIM_CR1_TDUDIS_Pos)          /*!< 0x00000010 */

+#define HRTIM_CR1_TDUDIS              HRTIM_CR1_TDUDIS_Msk                     /*!< Timer D update disable*/

+#define HRTIM_CR1_TEUDIS_Pos          (5U)

+#define HRTIM_CR1_TEUDIS_Msk          (0x1UL << HRTIM_CR1_TEUDIS_Pos)          /*!< 0x00000020 */

+#define HRTIM_CR1_TEUDIS              HRTIM_CR1_TEUDIS_Msk                     /*!< Timer E update disable*/

+#define HRTIM_CR1_ADC1USRC_Pos        (16U)

+#define HRTIM_CR1_ADC1USRC_Msk        (0x7UL << HRTIM_CR1_ADC1USRC_Pos)        /*!< 0x00070000 */

+#define HRTIM_CR1_ADC1USRC            HRTIM_CR1_ADC1USRC_Msk                   /*!< ADC Trigger 1 update source */

+#define HRTIM_CR1_ADC1USRC_0          (0x1UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00010000 */

+#define HRTIM_CR1_ADC1USRC_1          (0x2UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00020000 */

+#define HRTIM_CR1_ADC1USRC_2          (0x4UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00040000 */

+#define HRTIM_CR1_ADC2USRC_Pos        (19U)

+#define HRTIM_CR1_ADC2USRC_Msk        (0x7UL << HRTIM_CR1_ADC2USRC_Pos)        /*!< 0x00380000 */

+#define HRTIM_CR1_ADC2USRC            HRTIM_CR1_ADC2USRC_Msk                   /*!< ADC Trigger 2 update source */

+#define HRTIM_CR1_ADC2USRC_0          (0x1UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00080000 */

+#define HRTIM_CR1_ADC2USRC_1          (0x2UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00100000 */

+#define HRTIM_CR1_ADC2USRC_2          (0x4UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00200000 */

+#define HRTIM_CR1_ADC3USRC_Pos        (22U)

+#define HRTIM_CR1_ADC3USRC_Msk        (0x7UL << HRTIM_CR1_ADC3USRC_Pos)        /*!< 0x01C00000 */

+#define HRTIM_CR1_ADC3USRC            HRTIM_CR1_ADC3USRC_Msk                   /*!< ADC Trigger 3 update source */

+#define HRTIM_CR1_ADC3USRC_0          (0x1UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00400000 */

+#define HRTIM_CR1_ADC3USRC_1          (0x2UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00800000 */

+#define HRTIM_CR1_ADC3USRC_2          (0x4UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x01000000 */

+#define HRTIM_CR1_ADC4USRC_Pos        (25U)

+#define HRTIM_CR1_ADC4USRC_Msk        (0x7UL << HRTIM_CR1_ADC4USRC_Pos)        /*!< 0x0E000000 */

+#define HRTIM_CR1_ADC4USRC            HRTIM_CR1_ADC4USRC_Msk                   /*!< ADC Trigger 4 update source */

+#define HRTIM_CR1_ADC4USRC_0          (0x1UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x02000000 */

+#define HRTIM_CR1_ADC4USRC_1          (0x2UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x04000000 */

+#define HRTIM_CR1_ADC4USRC_2          (0x0UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x0800000 */

+

+/**** Bit definition for Common HRTIM Timer control register 2 ****************/

+#define HRTIM_CR2_MSWU_Pos            (0U)

+#define HRTIM_CR2_MSWU_Msk            (0x1UL << HRTIM_CR2_MSWU_Pos)            /*!< 0x00000001 */

+#define HRTIM_CR2_MSWU                HRTIM_CR2_MSWU_Msk                       /*!< Master software update */

+#define HRTIM_CR2_TASWU_Pos           (1U)

+#define HRTIM_CR2_TASWU_Msk           (0x1UL << HRTIM_CR2_TASWU_Pos)           /*!< 0x00000002 */

+#define HRTIM_CR2_TASWU               HRTIM_CR2_TASWU_Msk                      /*!< Timer A software update */

+#define HRTIM_CR2_TBSWU_Pos           (2U)

+#define HRTIM_CR2_TBSWU_Msk           (0x1UL << HRTIM_CR2_TBSWU_Pos)           /*!< 0x00000004 */

+#define HRTIM_CR2_TBSWU               HRTIM_CR2_TBSWU_Msk                      /*!< Timer B software update */

+#define HRTIM_CR2_TCSWU_Pos           (3U)

+#define HRTIM_CR2_TCSWU_Msk           (0x1UL << HRTIM_CR2_TCSWU_Pos)           /*!< 0x00000008 */

+#define HRTIM_CR2_TCSWU               HRTIM_CR2_TCSWU_Msk                      /*!< Timer C software update */

+#define HRTIM_CR2_TDSWU_Pos           (4U)

+#define HRTIM_CR2_TDSWU_Msk           (0x1UL << HRTIM_CR2_TDSWU_Pos)           /*!< 0x00000010 */

+#define HRTIM_CR2_TDSWU               HRTIM_CR2_TDSWU_Msk                      /*!< Timer D software update */

+#define HRTIM_CR2_TESWU_Pos           (5U)

+#define HRTIM_CR2_TESWU_Msk           (0x1UL << HRTIM_CR2_TESWU_Pos)           /*!< 0x00000020 */

+#define HRTIM_CR2_TESWU               HRTIM_CR2_TESWU_Msk                      /*!< Timer E software update */

+#define HRTIM_CR2_MRST_Pos            (8U)

+#define HRTIM_CR2_MRST_Msk            (0x1UL << HRTIM_CR2_MRST_Pos)            /*!< 0x00000100 */

+#define HRTIM_CR2_MRST                HRTIM_CR2_MRST_Msk                       /*!< Master count software reset */

+#define HRTIM_CR2_TARST_Pos           (9U)

+#define HRTIM_CR2_TARST_Msk           (0x1UL << HRTIM_CR2_TARST_Pos)           /*!< 0x00000200 */

+#define HRTIM_CR2_TARST               HRTIM_CR2_TARST_Msk                      /*!< Timer A count software reset */

+#define HRTIM_CR2_TBRST_Pos           (10U)

+#define HRTIM_CR2_TBRST_Msk           (0x1UL << HRTIM_CR2_TBRST_Pos)           /*!< 0x00000400 */

+#define HRTIM_CR2_TBRST               HRTIM_CR2_TBRST_Msk                      /*!< Timer B count software reset */

+#define HRTIM_CR2_TCRST_Pos           (11U)

+#define HRTIM_CR2_TCRST_Msk           (0x1UL << HRTIM_CR2_TCRST_Pos)           /*!< 0x00000800 */

+#define HRTIM_CR2_TCRST               HRTIM_CR2_TCRST_Msk                      /*!< Timer C count software reset */

+#define HRTIM_CR2_TDRST_Pos           (12U)

+#define HRTIM_CR2_TDRST_Msk           (0x1UL << HRTIM_CR2_TDRST_Pos)           /*!< 0x00001000 */

+#define HRTIM_CR2_TDRST               HRTIM_CR2_TDRST_Msk                      /*!< Timer D count software reset */

+#define HRTIM_CR2_TERST_Pos           (13U)

+#define HRTIM_CR2_TERST_Msk           (0x1UL << HRTIM_CR2_TERST_Pos)           /*!< 0x00002000 */

+#define HRTIM_CR2_TERST               HRTIM_CR2_TERST_Msk                      /*!< Timer E count software reset */

+

+/**** Bit definition for Common HRTIM Timer interrupt status register *********/

+#define HRTIM_ISR_FLT1_Pos            (0U)

+#define HRTIM_ISR_FLT1_Msk            (0x1UL << HRTIM_ISR_FLT1_Pos)            /*!< 0x00000001 */

+#define HRTIM_ISR_FLT1                HRTIM_ISR_FLT1_Msk                       /*!< Fault 1 interrupt flag */

+#define HRTIM_ISR_FLT2_Pos            (1U)

+#define HRTIM_ISR_FLT2_Msk            (0x1UL << HRTIM_ISR_FLT2_Pos)            /*!< 0x00000002 */

+#define HRTIM_ISR_FLT2                HRTIM_ISR_FLT2_Msk                       /*!< Fault 2 interrupt flag */

+#define HRTIM_ISR_FLT3_Pos            (2U)

+#define HRTIM_ISR_FLT3_Msk            (0x1UL << HRTIM_ISR_FLT3_Pos)            /*!< 0x00000004 */

+#define HRTIM_ISR_FLT3                HRTIM_ISR_FLT3_Msk                       /*!< Fault 3 interrupt flag */

+#define HRTIM_ISR_FLT4_Pos            (3U)

+#define HRTIM_ISR_FLT4_Msk            (0x1UL << HRTIM_ISR_FLT4_Pos)            /*!< 0x00000008 */

+#define HRTIM_ISR_FLT4                HRTIM_ISR_FLT4_Msk                       /*!< Fault 4 interrupt flag */

+#define HRTIM_ISR_FLT5_Pos            (4U)

+#define HRTIM_ISR_FLT5_Msk            (0x1UL << HRTIM_ISR_FLT5_Pos)            /*!< 0x00000010 */

+#define HRTIM_ISR_FLT5                HRTIM_ISR_FLT5_Msk                       /*!< Fault 5 interrupt flag */

+#define HRTIM_ISR_SYSFLT_Pos          (5U)

+#define HRTIM_ISR_SYSFLT_Msk          (0x1UL << HRTIM_ISR_SYSFLT_Pos)          /*!< 0x00000020 */

+#define HRTIM_ISR_SYSFLT              HRTIM_ISR_SYSFLT_Msk                     /*!< System Fault interrupt flag */

+#define HRTIM_ISR_BMPER_Pos           (17U)

+#define HRTIM_ISR_BMPER_Msk           (0x1UL << HRTIM_ISR_BMPER_Pos)           /*!< 0x00020000 */

+#define HRTIM_ISR_BMPER               HRTIM_ISR_BMPER_Msk                      /*!<  Burst mode period interrupt flag */

+

+/**** Bit definition for Common HRTIM Timer interrupt clear register **********/

+#define HRTIM_ICR_FLT1C_Pos           (0U)

+#define HRTIM_ICR_FLT1C_Msk           (0x1UL << HRTIM_ICR_FLT1C_Pos)           /*!< 0x00000001 */

+#define HRTIM_ICR_FLT1C               HRTIM_ICR_FLT1C_Msk                      /*!< Fault 1 interrupt flag clear */

+#define HRTIM_ICR_FLT2C_Pos           (1U)

+#define HRTIM_ICR_FLT2C_Msk           (0x1UL << HRTIM_ICR_FLT2C_Pos)           /*!< 0x00000002 */

+#define HRTIM_ICR_FLT2C               HRTIM_ICR_FLT2C_Msk                      /*!< Fault 2 interrupt flag clear */

+#define HRTIM_ICR_FLT3C_Pos           (2U)

+#define HRTIM_ICR_FLT3C_Msk           (0x1UL << HRTIM_ICR_FLT3C_Pos)           /*!< 0x00000004 */

+#define HRTIM_ICR_FLT3C               HRTIM_ICR_FLT3C_Msk                      /*!< Fault 3 interrupt flag clear */

+#define HRTIM_ICR_FLT4C_Pos           (3U)

+#define HRTIM_ICR_FLT4C_Msk           (0x1UL << HRTIM_ICR_FLT4C_Pos)           /*!< 0x00000008 */

+#define HRTIM_ICR_FLT4C               HRTIM_ICR_FLT4C_Msk                      /*!< Fault 4 interrupt flag clear */

+#define HRTIM_ICR_FLT5C_Pos           (4U)

+#define HRTIM_ICR_FLT5C_Msk           (0x1UL << HRTIM_ICR_FLT5C_Pos)           /*!< 0x00000010 */

+#define HRTIM_ICR_FLT5C               HRTIM_ICR_FLT5C_Msk                      /*!< Fault 5 interrupt flag clear */

+#define HRTIM_ICR_SYSFLTC_Pos         (5U)

+#define HRTIM_ICR_SYSFLTC_Msk         (0x1UL << HRTIM_ICR_SYSFLTC_Pos)         /*!< 0x00000020 */

+#define HRTIM_ICR_SYSFLTC             HRTIM_ICR_SYSFLTC_Msk                    /*!< System Fault interrupt flag clear */

+#define HRTIM_ICR_BMPERC_Pos          (17U)

+#define HRTIM_ICR_BMPERC_Msk          (0x1UL << HRTIM_ICR_BMPERC_Pos)          /*!< 0x00020000 */

+#define HRTIM_ICR_BMPERC              HRTIM_ICR_BMPERC_Msk                     /*!<  Burst mode period interrupt flag clear */

+

+/**** Bit definition for Common HRTIM Timer interrupt enable register *********/

+#define HRTIM_IER_FLT1_Pos            (0U)

+#define HRTIM_IER_FLT1_Msk            (0x1UL << HRTIM_IER_FLT1_Pos)            /*!< 0x00000001 */

+#define HRTIM_IER_FLT1                HRTIM_IER_FLT1_Msk                       /*!< Fault 1 interrupt enable */

+#define HRTIM_IER_FLT2_Pos            (1U)

+#define HRTIM_IER_FLT2_Msk            (0x1UL << HRTIM_IER_FLT2_Pos)            /*!< 0x00000002 */

+#define HRTIM_IER_FLT2                HRTIM_IER_FLT2_Msk                       /*!< Fault 2 interrupt enable */

+#define HRTIM_IER_FLT3_Pos            (2U)

+#define HRTIM_IER_FLT3_Msk            (0x1UL << HRTIM_IER_FLT3_Pos)            /*!< 0x00000004 */

+#define HRTIM_IER_FLT3                HRTIM_IER_FLT3_Msk                       /*!< Fault 3 interrupt enable */

+#define HRTIM_IER_FLT4_Pos            (3U)

+#define HRTIM_IER_FLT4_Msk            (0x1UL << HRTIM_IER_FLT4_Pos)            /*!< 0x00000008 */

+#define HRTIM_IER_FLT4                HRTIM_IER_FLT4_Msk                       /*!< Fault 4 interrupt enable */

+#define HRTIM_IER_FLT5_Pos            (4U)

+#define HRTIM_IER_FLT5_Msk            (0x1UL << HRTIM_IER_FLT5_Pos)            /*!< 0x00000010 */

+#define HRTIM_IER_FLT5                HRTIM_IER_FLT5_Msk                       /*!< Fault 5 interrupt enable */

+#define HRTIM_IER_SYSFLT_Pos          (5U)

+#define HRTIM_IER_SYSFLT_Msk          (0x1UL << HRTIM_IER_SYSFLT_Pos)          /*!< 0x00000020 */

+#define HRTIM_IER_SYSFLT              HRTIM_IER_SYSFLT_Msk                     /*!< System Fault interrupt enable */

+#define HRTIM_IER_BMPER_Pos           (17U)

+#define HRTIM_IER_BMPER_Msk           (0x1UL << HRTIM_IER_BMPER_Pos)           /*!< 0x00020000 */

+#define HRTIM_IER_BMPER               HRTIM_IER_BMPER_Msk                      /*!<  Burst mode period interrupt enable */

+

+/**** Bit definition for Common HRTIM Timer output enable register ************/

+#define HRTIM_OENR_TA1OEN_Pos         (0U)

+#define HRTIM_OENR_TA1OEN_Msk         (0x1UL << HRTIM_OENR_TA1OEN_Pos)         /*!< 0x00000001 */

+#define HRTIM_OENR_TA1OEN             HRTIM_OENR_TA1OEN_Msk                    /*!< Timer A Output 1 enable */

+#define HRTIM_OENR_TA2OEN_Pos         (1U)

+#define HRTIM_OENR_TA2OEN_Msk         (0x1UL << HRTIM_OENR_TA2OEN_Pos)         /*!< 0x00000002 */

+#define HRTIM_OENR_TA2OEN             HRTIM_OENR_TA2OEN_Msk                    /*!< Timer A Output 2 enable */

+#define HRTIM_OENR_TB1OEN_Pos         (2U)

+#define HRTIM_OENR_TB1OEN_Msk         (0x1UL << HRTIM_OENR_TB1OEN_Pos)         /*!< 0x00000004 */

+#define HRTIM_OENR_TB1OEN             HRTIM_OENR_TB1OEN_Msk                    /*!< Timer B Output 1 enable */

+#define HRTIM_OENR_TB2OEN_Pos         (3U)

+#define HRTIM_OENR_TB2OEN_Msk         (0x1UL << HRTIM_OENR_TB2OEN_Pos)         /*!< 0x00000008 */

+#define HRTIM_OENR_TB2OEN             HRTIM_OENR_TB2OEN_Msk                    /*!< Timer B Output 2 enable */

+#define HRTIM_OENR_TC1OEN_Pos         (4U)

+#define HRTIM_OENR_TC1OEN_Msk         (0x1UL << HRTIM_OENR_TC1OEN_Pos)         /*!< 0x00000010 */

+#define HRTIM_OENR_TC1OEN             HRTIM_OENR_TC1OEN_Msk                    /*!< Timer C Output 1 enable */

+#define HRTIM_OENR_TC2OEN_Pos         (5U)

+#define HRTIM_OENR_TC2OEN_Msk         (0x1UL << HRTIM_OENR_TC2OEN_Pos)         /*!< 0x00000020 */

+#define HRTIM_OENR_TC2OEN             HRTIM_OENR_TC2OEN_Msk                    /*!< Timer C Output 2 enable */

+#define HRTIM_OENR_TD1OEN_Pos         (6U)

+#define HRTIM_OENR_TD1OEN_Msk         (0x1UL << HRTIM_OENR_TD1OEN_Pos)         /*!< 0x00000040 */

+#define HRTIM_OENR_TD1OEN             HRTIM_OENR_TD1OEN_Msk                    /*!< Timer D Output 1 enable */

+#define HRTIM_OENR_TD2OEN_Pos         (7U)

+#define HRTIM_OENR_TD2OEN_Msk         (0x1UL << HRTIM_OENR_TD2OEN_Pos)         /*!< 0x00000080 */

+#define HRTIM_OENR_TD2OEN             HRTIM_OENR_TD2OEN_Msk                    /*!< Timer D Output 2 enable */

+#define HRTIM_OENR_TE1OEN_Pos         (8U)

+#define HRTIM_OENR_TE1OEN_Msk         (0x1UL << HRTIM_OENR_TE1OEN_Pos)         /*!< 0x00000100 */

+#define HRTIM_OENR_TE1OEN             HRTIM_OENR_TE1OEN_Msk                    /*!< Timer E Output 1 enable */

+#define HRTIM_OENR_TE2OEN_Pos         (9U)

+#define HRTIM_OENR_TE2OEN_Msk         (0x1UL << HRTIM_OENR_TE2OEN_Pos)         /*!< 0x00000200 */

+#define HRTIM_OENR_TE2OEN             HRTIM_OENR_TE2OEN_Msk                    /*!< Timer E Output 2 enable */

+

+/**** Bit definition for Common HRTIM Timer output disable register ***********/

+#define HRTIM_ODISR_TA1ODIS_Pos       (0U)

+#define HRTIM_ODISR_TA1ODIS_Msk       (0x1UL << HRTIM_ODISR_TA1ODIS_Pos)       /*!< 0x00000001 */

+#define HRTIM_ODISR_TA1ODIS           HRTIM_ODISR_TA1ODIS_Msk                  /*!< Timer A Output 1 disable */

+#define HRTIM_ODISR_TA2ODIS_Pos       (1U)

+#define HRTIM_ODISR_TA2ODIS_Msk       (0x1UL << HRTIM_ODISR_TA2ODIS_Pos)       /*!< 0x00000002 */

+#define HRTIM_ODISR_TA2ODIS           HRTIM_ODISR_TA2ODIS_Msk                  /*!< Timer A Output 2 disable */

+#define HRTIM_ODISR_TB1ODIS_Pos       (2U)

+#define HRTIM_ODISR_TB1ODIS_Msk       (0x1UL << HRTIM_ODISR_TB1ODIS_Pos)       /*!< 0x00000004 */

+#define HRTIM_ODISR_TB1ODIS           HRTIM_ODISR_TB1ODIS_Msk                  /*!< Timer B Output 1 disable */

+#define HRTIM_ODISR_TB2ODIS_Pos       (3U)

+#define HRTIM_ODISR_TB2ODIS_Msk       (0x1UL << HRTIM_ODISR_TB2ODIS_Pos)       /*!< 0x00000008 */

+#define HRTIM_ODISR_TB2ODIS           HRTIM_ODISR_TB2ODIS_Msk                  /*!< Timer B Output 2 disable */

+#define HRTIM_ODISR_TC1ODIS_Pos       (4U)

+#define HRTIM_ODISR_TC1ODIS_Msk       (0x1UL << HRTIM_ODISR_TC1ODIS_Pos)       /*!< 0x00000010 */

+#define HRTIM_ODISR_TC1ODIS           HRTIM_ODISR_TC1ODIS_Msk                  /*!< Timer C Output 1 disable */

+#define HRTIM_ODISR_TC2ODIS_Pos       (5U)

+#define HRTIM_ODISR_TC2ODIS_Msk       (0x1UL << HRTIM_ODISR_TC2ODIS_Pos)       /*!< 0x00000020 */

+#define HRTIM_ODISR_TC2ODIS           HRTIM_ODISR_TC2ODIS_Msk                  /*!< Timer C Output 2 disable */

+#define HRTIM_ODISR_TD1ODIS_Pos       (6U)

+#define HRTIM_ODISR_TD1ODIS_Msk       (0x1UL << HRTIM_ODISR_TD1ODIS_Pos)       /*!< 0x00000040 */

+#define HRTIM_ODISR_TD1ODIS           HRTIM_ODISR_TD1ODIS_Msk                  /*!< Timer D Output 1 disable */

+#define HRTIM_ODISR_TD2ODIS_Pos       (7U)

+#define HRTIM_ODISR_TD2ODIS_Msk       (0x1UL << HRTIM_ODISR_TD2ODIS_Pos)       /*!< 0x00000080 */

+#define HRTIM_ODISR_TD2ODIS           HRTIM_ODISR_TD2ODIS_Msk                  /*!< Timer D Output 2 disable */

+#define HRTIM_ODISR_TE1ODIS_Pos       (8U)

+#define HRTIM_ODISR_TE1ODIS_Msk       (0x1UL << HRTIM_ODISR_TE1ODIS_Pos)       /*!< 0x00000100 */

+#define HRTIM_ODISR_TE1ODIS           HRTIM_ODISR_TE1ODIS_Msk                  /*!< Timer E Output 1 disable */

+#define HRTIM_ODISR_TE2ODIS_Pos       (9U)

+#define HRTIM_ODISR_TE2ODIS_Msk       (0x1UL << HRTIM_ODISR_TE2ODIS_Pos)       /*!< 0x00000200 */

+#define HRTIM_ODISR_TE2ODIS           HRTIM_ODISR_TE2ODIS_Msk                  /*!< Timer E Output 2 disable */

+

+/**** Bit definition for Common HRTIM Timer output disable status register *****/

+#define HRTIM_ODSR_TA1ODS_Pos         (0U)

+#define HRTIM_ODSR_TA1ODS_Msk         (0x1UL << HRTIM_ODSR_TA1ODS_Pos)         /*!< 0x00000001 */

+#define HRTIM_ODSR_TA1ODS             HRTIM_ODSR_TA1ODS_Msk                    /*!< Timer A Output 1 disable status */

+#define HRTIM_ODSR_TA2ODS_Pos         (1U)

+#define HRTIM_ODSR_TA2ODS_Msk         (0x1UL << HRTIM_ODSR_TA2ODS_Pos)         /*!< 0x00000002 */

+#define HRTIM_ODSR_TA2ODS             HRTIM_ODSR_TA2ODS_Msk                    /*!< Timer A Output 2 disable status */

+#define HRTIM_ODSR_TB1ODS_Pos         (2U)

+#define HRTIM_ODSR_TB1ODS_Msk         (0x1UL << HRTIM_ODSR_TB1ODS_Pos)         /*!< 0x00000004 */

+#define HRTIM_ODSR_TB1ODS             HRTIM_ODSR_TB1ODS_Msk                    /*!< Timer B Output 1 disable status */

+#define HRTIM_ODSR_TB2ODS_Pos         (3U)

+#define HRTIM_ODSR_TB2ODS_Msk         (0x1UL << HRTIM_ODSR_TB2ODS_Pos)         /*!< 0x00000008 */

+#define HRTIM_ODSR_TB2ODS             HRTIM_ODSR_TB2ODS_Msk                    /*!< Timer B Output 2 disable status */

+#define HRTIM_ODSR_TC1ODS_Pos         (4U)

+#define HRTIM_ODSR_TC1ODS_Msk         (0x1UL << HRTIM_ODSR_TC1ODS_Pos)         /*!< 0x00000010 */

+#define HRTIM_ODSR_TC1ODS             HRTIM_ODSR_TC1ODS_Msk                    /*!< Timer C Output 1 disable status */

+#define HRTIM_ODSR_TC2ODS_Pos         (5U)

+#define HRTIM_ODSR_TC2ODS_Msk         (0x1UL << HRTIM_ODSR_TC2ODS_Pos)         /*!< 0x00000020 */

+#define HRTIM_ODSR_TC2ODS             HRTIM_ODSR_TC2ODS_Msk                    /*!< Timer C Output 2 disable status */

+#define HRTIM_ODSR_TD1ODS_Pos         (6U)

+#define HRTIM_ODSR_TD1ODS_Msk         (0x1UL << HRTIM_ODSR_TD1ODS_Pos)         /*!< 0x00000040 */

+#define HRTIM_ODSR_TD1ODS             HRTIM_ODSR_TD1ODS_Msk                    /*!< Timer D Output 1 disable status */

+#define HRTIM_ODSR_TD2ODS_Pos         (7U)

+#define HRTIM_ODSR_TD2ODS_Msk         (0x1UL << HRTIM_ODSR_TD2ODS_Pos)         /*!< 0x00000080 */

+#define HRTIM_ODSR_TD2ODS             HRTIM_ODSR_TD2ODS_Msk                    /*!< Timer D Output 2 disable status */

+#define HRTIM_ODSR_TE1ODS_Pos         (8U)

+#define HRTIM_ODSR_TE1ODS_Msk         (0x1UL << HRTIM_ODSR_TE1ODS_Pos)         /*!< 0x00000100 */

+#define HRTIM_ODSR_TE1ODS             HRTIM_ODSR_TE1ODS_Msk                    /*!< Timer E Output 1 disable status */

+#define HRTIM_ODSR_TE2ODS_Pos         (9U)

+#define HRTIM_ODSR_TE2ODS_Msk         (0x1UL << HRTIM_ODSR_TE2ODS_Pos)         /*!< 0x00000200 */

+#define HRTIM_ODSR_TE2ODS             HRTIM_ODSR_TE2ODS_Msk                    /*!< Timer E Output 2 disable status */

+

+/**** Bit definition for Common HRTIM Timer Burst mode control register ********/

+#define HRTIM_BMCR_BME_Pos            (0U)

+#define HRTIM_BMCR_BME_Msk            (0x1UL << HRTIM_BMCR_BME_Pos)            /*!< 0x00000001 */

+#define HRTIM_BMCR_BME                HRTIM_BMCR_BME_Msk                       /*!< Burst mode enbale */

+#define HRTIM_BMCR_BMOM_Pos           (1U)

+#define HRTIM_BMCR_BMOM_Msk           (0x1UL << HRTIM_BMCR_BMOM_Pos)           /*!< 0x00000002 */

+#define HRTIM_BMCR_BMOM               HRTIM_BMCR_BMOM_Msk                      /*!< Burst mode operating mode */

+#define HRTIM_BMCR_BMCLK_Pos          (2U)

+#define HRTIM_BMCR_BMCLK_Msk          (0xFUL << HRTIM_BMCR_BMCLK_Pos)          /*!< 0x0000003C */

+#define HRTIM_BMCR_BMCLK              HRTIM_BMCR_BMCLK_Msk                     /*!< Burst mode clock source */

+#define HRTIM_BMCR_BMCLK_0            (0x1UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000004 */

+#define HRTIM_BMCR_BMCLK_1            (0x2UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000008 */

+#define HRTIM_BMCR_BMCLK_2            (0x4UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000010 */

+#define HRTIM_BMCR_BMCLK_3            (0x8UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000020 */

+#define HRTIM_BMCR_BMPRSC_Pos         (6U)

+#define HRTIM_BMCR_BMPRSC_Msk         (0xFUL << HRTIM_BMCR_BMPRSC_Pos)         /*!< 0x000003C0 */

+#define HRTIM_BMCR_BMPRSC             HRTIM_BMCR_BMPRSC_Msk                    /*!< Burst mode prescaler */

+#define HRTIM_BMCR_BMPRSC_0           (0x1UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000040 */

+#define HRTIM_BMCR_BMPRSC_1           (0x2UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000080 */

+#define HRTIM_BMCR_BMPRSC_2           (0x4UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000100 */

+#define HRTIM_BMCR_BMPRSC_3           (0x8UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000200 */

+#define HRTIM_BMCR_BMPREN_Pos         (10U)

+#define HRTIM_BMCR_BMPREN_Msk         (0x1UL << HRTIM_BMCR_BMPREN_Pos)         /*!< 0x00000400 */

+#define HRTIM_BMCR_BMPREN             HRTIM_BMCR_BMPREN_Msk                    /*!< Burst mode Preload bit */

+#define HRTIM_BMCR_MTBM_Pos           (16U)

+#define HRTIM_BMCR_MTBM_Msk           (0x1UL << HRTIM_BMCR_MTBM_Pos)           /*!< 0x00010000 */

+#define HRTIM_BMCR_MTBM               HRTIM_BMCR_MTBM_Msk                      /*!< Master Timer Burst mode */

+#define HRTIM_BMCR_TABM_Pos           (17U)

+#define HRTIM_BMCR_TABM_Msk           (0x1UL << HRTIM_BMCR_TABM_Pos)           /*!< 0x00020000 */

+#define HRTIM_BMCR_TABM               HRTIM_BMCR_TABM_Msk                      /*!< Timer A Burst mode */

+#define HRTIM_BMCR_TBBM_Pos           (18U)

+#define HRTIM_BMCR_TBBM_Msk           (0x1UL << HRTIM_BMCR_TBBM_Pos)           /*!< 0x00040000 */

+#define HRTIM_BMCR_TBBM               HRTIM_BMCR_TBBM_Msk                      /*!< Timer B Burst mode */

+#define HRTIM_BMCR_TCBM_Pos           (19U)

+#define HRTIM_BMCR_TCBM_Msk           (0x1UL << HRTIM_BMCR_TCBM_Pos)           /*!< 0x00080000 */

+#define HRTIM_BMCR_TCBM               HRTIM_BMCR_TCBM_Msk                      /*!< Timer C Burst mode */

+#define HRTIM_BMCR_TDBM_Pos           (20U)

+#define HRTIM_BMCR_TDBM_Msk           (0x1UL << HRTIM_BMCR_TDBM_Pos)           /*!< 0x00100000 */

+#define HRTIM_BMCR_TDBM               HRTIM_BMCR_TDBM_Msk                      /*!< Timer D Burst mode */

+#define HRTIM_BMCR_TEBM_Pos           (21U)

+#define HRTIM_BMCR_TEBM_Msk           (0x1UL << HRTIM_BMCR_TEBM_Pos)           /*!< 0x00200000 */

+#define HRTIM_BMCR_TEBM               HRTIM_BMCR_TEBM_Msk                      /*!< Timer E Burst mode */

+#define HRTIM_BMCR_BMSTAT_Pos         (31U)

+#define HRTIM_BMCR_BMSTAT_Msk         (0x1UL << HRTIM_BMCR_BMSTAT_Pos)         /*!< 0x80000000 */

+#define HRTIM_BMCR_BMSTAT             HRTIM_BMCR_BMSTAT_Msk                    /*!< Burst mode status */

+

+/**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/

+#define HRTIM_BMTRGR_SW_Pos           (0U)

+#define HRTIM_BMTRGR_SW_Msk           (0x1UL << HRTIM_BMTRGR_SW_Pos)           /*!< 0x00000001 */

+#define HRTIM_BMTRGR_SW               HRTIM_BMTRGR_SW_Msk                      /*!< Software start */

+#define HRTIM_BMTRGR_MSTRST_Pos       (1U)

+#define HRTIM_BMTRGR_MSTRST_Msk       (0x1UL << HRTIM_BMTRGR_MSTRST_Pos)       /*!< 0x00000002 */

+#define HRTIM_BMTRGR_MSTRST           HRTIM_BMTRGR_MSTRST_Msk                  /*!<  Master reset */

+#define HRTIM_BMTRGR_MSTREP_Pos       (2U)

+#define HRTIM_BMTRGR_MSTREP_Msk       (0x1UL << HRTIM_BMTRGR_MSTREP_Pos)       /*!< 0x00000004 */

+#define HRTIM_BMTRGR_MSTREP           HRTIM_BMTRGR_MSTREP_Msk                  /*!<  Master repetition */

+#define HRTIM_BMTRGR_MSTCMP1_Pos      (3U)

+#define HRTIM_BMTRGR_MSTCMP1_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos)      /*!< 0x00000008 */

+#define HRTIM_BMTRGR_MSTCMP1          HRTIM_BMTRGR_MSTCMP1_Msk                 /*!<  Master compare 1 */

+#define HRTIM_BMTRGR_MSTCMP2_Pos      (4U)

+#define HRTIM_BMTRGR_MSTCMP2_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos)      /*!< 0x00000010 */

+#define HRTIM_BMTRGR_MSTCMP2          HRTIM_BMTRGR_MSTCMP2_Msk                 /*!< Master compare 2  */

+#define HRTIM_BMTRGR_MSTCMP3_Pos      (5U)

+#define HRTIM_BMTRGR_MSTCMP3_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos)      /*!< 0x00000020 */

+#define HRTIM_BMTRGR_MSTCMP3          HRTIM_BMTRGR_MSTCMP3_Msk                 /*!< Master compare 3 */

+#define HRTIM_BMTRGR_MSTCMP4_Pos      (6U)

+#define HRTIM_BMTRGR_MSTCMP4_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos)      /*!< 0x00000040 */

+#define HRTIM_BMTRGR_MSTCMP4          HRTIM_BMTRGR_MSTCMP4_Msk                 /*!< Master compare 4 */

+#define HRTIM_BMTRGR_TARST_Pos        (7U)

+#define HRTIM_BMTRGR_TARST_Msk        (0x1UL << HRTIM_BMTRGR_TARST_Pos)        /*!< 0x00000080 */

+#define HRTIM_BMTRGR_TARST            HRTIM_BMTRGR_TARST_Msk                   /*!< Timer A reset  */

+#define HRTIM_BMTRGR_TAREP_Pos        (8U)

+#define HRTIM_BMTRGR_TAREP_Msk        (0x1UL << HRTIM_BMTRGR_TAREP_Pos)        /*!< 0x00000100 */

+#define HRTIM_BMTRGR_TAREP            HRTIM_BMTRGR_TAREP_Msk                   /*!< Timer A repetition  */

+#define HRTIM_BMTRGR_TACMP1_Pos       (9U)

+#define HRTIM_BMTRGR_TACMP1_Msk       (0x1UL << HRTIM_BMTRGR_TACMP1_Pos)       /*!< 0x00000200 */

+#define HRTIM_BMTRGR_TACMP1           HRTIM_BMTRGR_TACMP1_Msk                  /*!< Timer A compare 1  */

+#define HRTIM_BMTRGR_TACMP2_Pos       (10U)

+#define HRTIM_BMTRGR_TACMP2_Msk       (0x1UL << HRTIM_BMTRGR_TACMP2_Pos)       /*!< 0x00000400 */

+#define HRTIM_BMTRGR_TACMP2           HRTIM_BMTRGR_TACMP2_Msk                  /*!< Timer A compare 2  */

+#define HRTIM_BMTRGR_TBRST_Pos        (11U)

+#define HRTIM_BMTRGR_TBRST_Msk        (0x1UL << HRTIM_BMTRGR_TBRST_Pos)        /*!< 0x00000800 */

+#define HRTIM_BMTRGR_TBRST            HRTIM_BMTRGR_TBRST_Msk                   /*!< Timer B reset  */

+#define HRTIM_BMTRGR_TBREP_Pos        (12U)

+#define HRTIM_BMTRGR_TBREP_Msk        (0x1UL << HRTIM_BMTRGR_TBREP_Pos)        /*!< 0x00001000 */

+#define HRTIM_BMTRGR_TBREP            HRTIM_BMTRGR_TBREP_Msk                   /*!< Timer B repetition  */

+#define HRTIM_BMTRGR_TBCMP1_Pos       (13U)

+#define HRTIM_BMTRGR_TBCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos)       /*!< 0x00002000 */

+#define HRTIM_BMTRGR_TBCMP1           HRTIM_BMTRGR_TBCMP1_Msk                  /*!< Timer B compare 1 */

+#define HRTIM_BMTRGR_TBCMP2_Pos       (14U)

+#define HRTIM_BMTRGR_TBCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos)       /*!< 0x00004000 */

+#define HRTIM_BMTRGR_TBCMP2           HRTIM_BMTRGR_TBCMP2_Msk                  /*!< Timer B compare 2 */

+#define HRTIM_BMTRGR_TCRST_Pos        (15U)

+#define HRTIM_BMTRGR_TCRST_Msk        (0x1UL << HRTIM_BMTRGR_TCRST_Pos)        /*!< 0x00008000 */

+#define HRTIM_BMTRGR_TCRST            HRTIM_BMTRGR_TCRST_Msk                   /*!< Timer C reset  */

+#define HRTIM_BMTRGR_TCREP_Pos        (16U)

+#define HRTIM_BMTRGR_TCREP_Msk        (0x1UL << HRTIM_BMTRGR_TCREP_Pos)        /*!< 0x00010000 */

+#define HRTIM_BMTRGR_TCREP            HRTIM_BMTRGR_TCREP_Msk                   /*!< Timer C repetition */

+#define HRTIM_BMTRGR_TCCMP1_Pos       (17U)

+#define HRTIM_BMTRGR_TCCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos)       /*!< 0x00020000 */

+#define HRTIM_BMTRGR_TCCMP1           HRTIM_BMTRGR_TCCMP1_Msk                  /*!< Timer C compare 1 */

+#define HRTIM_BMTRGR_TCCMP2_Pos       (18U)

+#define HRTIM_BMTRGR_TCCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP2_Pos)       /*!< 0x00040000 */

+#define HRTIM_BMTRGR_TCCMP2           HRTIM_BMTRGR_TCCMP2_Msk                  /*!< Timer C compare 2 */

+#define HRTIM_BMTRGR_TDRST_Pos        (19U)

+#define HRTIM_BMTRGR_TDRST_Msk        (0x1UL << HRTIM_BMTRGR_TDRST_Pos)        /*!< 0x00080000 */

+#define HRTIM_BMTRGR_TDRST            HRTIM_BMTRGR_TDRST_Msk                   /*!< Timer D reset  */

+#define HRTIM_BMTRGR_TDREP_Pos        (20U)

+#define HRTIM_BMTRGR_TDREP_Msk        (0x1UL << HRTIM_BMTRGR_TDREP_Pos)        /*!< 0x00100000 */

+#define HRTIM_BMTRGR_TDREP            HRTIM_BMTRGR_TDREP_Msk                   /*!< Timer D repetition  */

+#define HRTIM_BMTRGR_TDCMP1_Pos       (21U)

+#define HRTIM_BMTRGR_TDCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP1_Pos)       /*!< 0x00200000 */

+#define HRTIM_BMTRGR_TDCMP1           HRTIM_BMTRGR_TDCMP1_Msk                  /*!< Timer D compare 1 */

+#define HRTIM_BMTRGR_TDCMP2_Pos       (22U)

+#define HRTIM_BMTRGR_TDCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos)       /*!< 0x00400000 */

+#define HRTIM_BMTRGR_TDCMP2           HRTIM_BMTRGR_TDCMP2_Msk                  /*!< Timer D compare 2 */

+#define HRTIM_BMTRGR_TERST_Pos        (23U)

+#define HRTIM_BMTRGR_TERST_Msk        (0x1UL << HRTIM_BMTRGR_TERST_Pos)        /*!< 0x00800000 */

+#define HRTIM_BMTRGR_TERST            HRTIM_BMTRGR_TERST_Msk                   /*!< Timer E reset  */

+#define HRTIM_BMTRGR_TEREP_Pos        (24U)

+#define HRTIM_BMTRGR_TEREP_Msk        (0x1UL << HRTIM_BMTRGR_TEREP_Pos)        /*!< 0x01000000 */

+#define HRTIM_BMTRGR_TEREP            HRTIM_BMTRGR_TEREP_Msk                   /*!< Timer E repetition  */

+#define HRTIM_BMTRGR_TECMP1_Pos       (25U)

+#define HRTIM_BMTRGR_TECMP1_Msk       (0x1UL << HRTIM_BMTRGR_TECMP1_Pos)       /*!< 0x02000000 */

+#define HRTIM_BMTRGR_TECMP1           HRTIM_BMTRGR_TECMP1_Msk                  /*!< Timer E compare 1 */

+#define HRTIM_BMTRGR_TECMP2_Pos       (26U)

+#define HRTIM_BMTRGR_TECMP2_Msk       (0x1UL << HRTIM_BMTRGR_TECMP2_Pos)       /*!< 0x04000000 */

+#define HRTIM_BMTRGR_TECMP2           HRTIM_BMTRGR_TECMP2_Msk                  /*!< Timer E compare 2 */

+#define HRTIM_BMTRGR_TAEEV7_Pos       (27U)

+#define HRTIM_BMTRGR_TAEEV7_Msk       (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos)       /*!< 0x08000000 */

+#define HRTIM_BMTRGR_TAEEV7           HRTIM_BMTRGR_TAEEV7_Msk                  /*!< Timer A period following External Event7  */

+#define HRTIM_BMTRGR_TDEEV8_Pos       (28U)

+#define HRTIM_BMTRGR_TDEEV8_Msk       (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos)       /*!< 0x10000000 */

+#define HRTIM_BMTRGR_TDEEV8           HRTIM_BMTRGR_TDEEV8_Msk                  /*!< Timer D period following External Event8  */

+#define HRTIM_BMTRGR_EEV7_Pos         (29U)

+#define HRTIM_BMTRGR_EEV7_Msk         (0x1UL << HRTIM_BMTRGR_EEV7_Pos)         /*!< 0x20000000 */

+#define HRTIM_BMTRGR_EEV7             HRTIM_BMTRGR_EEV7_Msk                    /*!< External Event 7 */

+#define HRTIM_BMTRGR_EEV8_Pos         (30U)

+#define HRTIM_BMTRGR_EEV8_Msk         (0x1UL << HRTIM_BMTRGR_EEV8_Pos)         /*!< 0x40000000 */

+#define HRTIM_BMTRGR_EEV8             HRTIM_BMTRGR_EEV8_Msk                    /*!< External Event 8 */

+#define HRTIM_BMTRGR_OCHPEV_Pos       (31U)

+#define HRTIM_BMTRGR_OCHPEV_Msk       (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos)       /*!< 0x80000000 */

+#define HRTIM_BMTRGR_OCHPEV           HRTIM_BMTRGR_OCHPEV_Msk                  /*!< on-chip Event */

+

+/*******************  Bit definition for HRTIM_BMCMPR register  ***************/

+#define HRTIM_BMCMPR_BMCMPR_Pos       (0U)

+#define HRTIM_BMCMPR_BMCMPR_Msk       (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_BMCMPR_BMCMPR           HRTIM_BMCMPR_BMCMPR_Msk                  /*!<!<Burst Compare Value */

+

+/*******************  Bit definition for HRTIM_BMPER register  ****************/

+#define HRTIM_BMPER_BMPER_Pos         (0U)

+#define HRTIM_BMPER_BMPER_Msk         (0xFFFFUL << HRTIM_BMPER_BMPER_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_BMPER_BMPER             HRTIM_BMPER_BMPER_Msk                    /*!<!<Burst period Value */

+

+/*******************  Bit definition for HRTIM_EECR1 register  ****************/

+#define HRTIM_EECR1_EE1SRC_Pos        (0U)

+#define HRTIM_EECR1_EE1SRC_Msk        (0x3UL << HRTIM_EECR1_EE1SRC_Pos)        /*!< 0x00000003 */

+#define HRTIM_EECR1_EE1SRC            HRTIM_EECR1_EE1SRC_Msk                   /*!< External event 1 source */

+#define HRTIM_EECR1_EE1SRC_0          (0x1UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000001 */

+#define HRTIM_EECR1_EE1SRC_1          (0x2UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000002 */

+#define HRTIM_EECR1_EE1POL_Pos        (2U)

+#define HRTIM_EECR1_EE1POL_Msk        (0x1UL << HRTIM_EECR1_EE1POL_Pos)        /*!< 0x00000004 */

+#define HRTIM_EECR1_EE1POL            HRTIM_EECR1_EE1POL_Msk                   /*!< External event 1 Polarity */

+#define HRTIM_EECR1_EE1SNS_Pos        (3U)

+#define HRTIM_EECR1_EE1SNS_Msk        (0x3UL << HRTIM_EECR1_EE1SNS_Pos)        /*!< 0x00000018 */

+#define HRTIM_EECR1_EE1SNS            HRTIM_EECR1_EE1SNS_Msk                   /*!< External event 1 sensitivity */

+#define HRTIM_EECR1_EE1SNS_0          (0x1UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000008 */

+#define HRTIM_EECR1_EE1SNS_1          (0x2UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000010 */

+#define HRTIM_EECR1_EE1FAST_Pos       (5U)

+#define HRTIM_EECR1_EE1FAST_Msk       (0x1UL << HRTIM_EECR1_EE1FAST_Pos)       /*!< 0x00000020 */

+#define HRTIM_EECR1_EE1FAST           HRTIM_EECR1_EE1FAST_Msk                  /*!< External event 1 Fast mode */

+

+#define HRTIM_EECR1_EE2SRC_Pos        (6U)

+#define HRTIM_EECR1_EE2SRC_Msk        (0x3UL << HRTIM_EECR1_EE2SRC_Pos)        /*!< 0x000000C0 */

+#define HRTIM_EECR1_EE2SRC            HRTIM_EECR1_EE2SRC_Msk                   /*!< External event 2 source */

+#define HRTIM_EECR1_EE2SRC_0          (0x1UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000040 */

+#define HRTIM_EECR1_EE2SRC_1          (0x2UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000080 */

+#define HRTIM_EECR1_EE2POL_Pos        (8U)

+#define HRTIM_EECR1_EE2POL_Msk        (0x1UL << HRTIM_EECR1_EE2POL_Pos)        /*!< 0x00000100 */

+#define HRTIM_EECR1_EE2POL            HRTIM_EECR1_EE2POL_Msk                   /*!< External event 2 Polarity */

+#define HRTIM_EECR1_EE2SNS_Pos        (9U)

+#define HRTIM_EECR1_EE2SNS_Msk        (0x3UL << HRTIM_EECR1_EE2SNS_Pos)        /*!< 0x00000600 */

+#define HRTIM_EECR1_EE2SNS            HRTIM_EECR1_EE2SNS_Msk                   /*!< External event 2 sensitivity */

+#define HRTIM_EECR1_EE2SNS_0          (0x1UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000200 */

+#define HRTIM_EECR1_EE2SNS_1          (0x2UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000400 */

+#define HRTIM_EECR1_EE2FAST_Pos       (11U)

+#define HRTIM_EECR1_EE2FAST_Msk       (0x1UL << HRTIM_EECR1_EE2FAST_Pos)       /*!< 0x00000800 */

+#define HRTIM_EECR1_EE2FAST           HRTIM_EECR1_EE2FAST_Msk                  /*!< External event 2 Fast mode */

+

+#define HRTIM_EECR1_EE3SRC_Pos        (12U)

+#define HRTIM_EECR1_EE3SRC_Msk        (0x3UL << HRTIM_EECR1_EE3SRC_Pos)        /*!< 0x00003000 */

+#define HRTIM_EECR1_EE3SRC            HRTIM_EECR1_EE3SRC_Msk                   /*!< External event 3 source */

+#define HRTIM_EECR1_EE3SRC_0          (0x1UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00001000 */

+#define HRTIM_EECR1_EE3SRC_1          (0x2UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00002000 */

+#define HRTIM_EECR1_EE3POL_Pos        (14U)

+#define HRTIM_EECR1_EE3POL_Msk        (0x1UL << HRTIM_EECR1_EE3POL_Pos)        /*!< 0x00004000 */

+#define HRTIM_EECR1_EE3POL            HRTIM_EECR1_EE3POL_Msk                   /*!< External event 3 Polarity */

+#define HRTIM_EECR1_EE3SNS_Pos        (15U)

+#define HRTIM_EECR1_EE3SNS_Msk        (0x3UL << HRTIM_EECR1_EE3SNS_Pos)        /*!< 0x00018000 */

+#define HRTIM_EECR1_EE3SNS            HRTIM_EECR1_EE3SNS_Msk                   /*!< External event 3 sensitivity */

+#define HRTIM_EECR1_EE3SNS_0          (0x1UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00008000 */

+#define HRTIM_EECR1_EE3SNS_1          (0x2UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00010000 */

+#define HRTIM_EECR1_EE3FAST_Pos       (17U)

+#define HRTIM_EECR1_EE3FAST_Msk       (0x1UL << HRTIM_EECR1_EE3FAST_Pos)       /*!< 0x00020000 */

+#define HRTIM_EECR1_EE3FAST           HRTIM_EECR1_EE3FAST_Msk                  /*!< External event 3 Fast mode */

+

+#define HRTIM_EECR1_EE4SRC_Pos        (18U)

+#define HRTIM_EECR1_EE4SRC_Msk        (0x3UL << HRTIM_EECR1_EE4SRC_Pos)        /*!< 0x000C0000 */

+#define HRTIM_EECR1_EE4SRC            HRTIM_EECR1_EE4SRC_Msk                   /*!< External event 4 source */

+#define HRTIM_EECR1_EE4SRC_0          (0x1UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00040000 */

+#define HRTIM_EECR1_EE4SRC_1          (0x2UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00080000 */

+#define HRTIM_EECR1_EE4POL_Pos        (20U)

+#define HRTIM_EECR1_EE4POL_Msk        (0x1UL << HRTIM_EECR1_EE4POL_Pos)        /*!< 0x00100000 */

+#define HRTIM_EECR1_EE4POL            HRTIM_EECR1_EE4POL_Msk                   /*!< External event 4 Polarity */

+#define HRTIM_EECR1_EE4SNS_Pos        (21U)

+#define HRTIM_EECR1_EE4SNS_Msk        (0x3UL << HRTIM_EECR1_EE4SNS_Pos)        /*!< 0x00600000 */

+#define HRTIM_EECR1_EE4SNS            HRTIM_EECR1_EE4SNS_Msk                   /*!< External event 4 sensitivity */

+#define HRTIM_EECR1_EE4SNS_0          (0x1UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00200000 */

+#define HRTIM_EECR1_EE4SNS_1          (0x2UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00400000 */

+#define HRTIM_EECR1_EE4FAST_Pos       (23U)

+#define HRTIM_EECR1_EE4FAST_Msk       (0x1UL << HRTIM_EECR1_EE4FAST_Pos)       /*!< 0x00800000 */

+#define HRTIM_EECR1_EE4FAST           HRTIM_EECR1_EE4FAST_Msk                  /*!< External event 4 Fast mode */

+

+#define HRTIM_EECR1_EE5SRC_Pos        (24U)

+#define HRTIM_EECR1_EE5SRC_Msk        (0x3UL << HRTIM_EECR1_EE5SRC_Pos)        /*!< 0x03000000 */

+#define HRTIM_EECR1_EE5SRC            HRTIM_EECR1_EE5SRC_Msk                   /*!< External event 5 source */

+#define HRTIM_EECR1_EE5SRC_0          (0x1UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x01000000 */

+#define HRTIM_EECR1_EE5SRC_1          (0x2UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x02000000 */

+#define HRTIM_EECR1_EE5POL_Pos        (26U)

+#define HRTIM_EECR1_EE5POL_Msk        (0x1UL << HRTIM_EECR1_EE5POL_Pos)        /*!< 0x04000000 */

+#define HRTIM_EECR1_EE5POL            HRTIM_EECR1_EE5POL_Msk                   /*!< External event 5 Polarity */

+#define HRTIM_EECR1_EE5SNS_Pos        (27U)

+#define HRTIM_EECR1_EE5SNS_Msk        (0x3UL << HRTIM_EECR1_EE5SNS_Pos)        /*!< 0x18000000 */

+#define HRTIM_EECR1_EE5SNS            HRTIM_EECR1_EE5SNS_Msk                   /*!< External event 5 sensitivity */

+#define HRTIM_EECR1_EE5SNS_0          (0x1UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x08000000 */

+#define HRTIM_EECR1_EE5SNS_1          (0x2UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x10000000 */

+#define HRTIM_EECR1_EE5FAST_Pos       (29U)

+#define HRTIM_EECR1_EE5FAST_Msk       (0x1UL << HRTIM_EECR1_EE5FAST_Pos)       /*!< 0x20000000 */

+#define HRTIM_EECR1_EE5FAST           HRTIM_EECR1_EE5FAST_Msk                  /*!< External event 5 Fast mode */

+

+/*******************  Bit definition for HRTIM_EECR2 register  ****************/

+#define HRTIM_EECR2_EE6SRC_Pos        (0U)

+#define HRTIM_EECR2_EE6SRC_Msk        (0x3UL << HRTIM_EECR2_EE6SRC_Pos)        /*!< 0x00000003 */

+#define HRTIM_EECR2_EE6SRC            HRTIM_EECR2_EE6SRC_Msk                   /*!< External event 6 source */

+#define HRTIM_EECR2_EE6SRC_0          (0x1UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000001 */

+#define HRTIM_EECR2_EE6SRC_1          (0x2UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000002 */

+#define HRTIM_EECR2_EE6POL_Pos        (2U)

+#define HRTIM_EECR2_EE6POL_Msk        (0x1UL << HRTIM_EECR2_EE6POL_Pos)        /*!< 0x00000004 */

+#define HRTIM_EECR2_EE6POL            HRTIM_EECR2_EE6POL_Msk                   /*!< External event 6 Polarity */

+#define HRTIM_EECR2_EE6SNS_Pos        (3U)

+#define HRTIM_EECR2_EE6SNS_Msk        (0x3UL << HRTIM_EECR2_EE6SNS_Pos)        /*!< 0x00000018 */

+#define HRTIM_EECR2_EE6SNS            HRTIM_EECR2_EE6SNS_Msk                   /*!< External event 6 sensitivity */

+#define HRTIM_EECR2_EE6SNS_0          (0x1UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000008 */

+#define HRTIM_EECR2_EE6SNS_1          (0x2UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000010 */

+

+#define HRTIM_EECR2_EE7SRC_Pos        (6U)

+#define HRTIM_EECR2_EE7SRC_Msk        (0x3UL << HRTIM_EECR2_EE7SRC_Pos)        /*!< 0x000000C0 */

+#define HRTIM_EECR2_EE7SRC            HRTIM_EECR2_EE7SRC_Msk                   /*!< External event 7 source */

+#define HRTIM_EECR2_EE7SRC_0          (0x1UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000040 */

+#define HRTIM_EECR2_EE7SRC_1          (0x2UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000080 */

+#define HRTIM_EECR2_EE7POL_Pos        (8U)

+#define HRTIM_EECR2_EE7POL_Msk        (0x1UL << HRTIM_EECR2_EE7POL_Pos)        /*!< 0x00000100 */

+#define HRTIM_EECR2_EE7POL            HRTIM_EECR2_EE7POL_Msk                   /*!< External event 7 Polarity */

+#define HRTIM_EECR2_EE7SNS_Pos        (9U)

+#define HRTIM_EECR2_EE7SNS_Msk        (0x3UL << HRTIM_EECR2_EE7SNS_Pos)        /*!< 0x00000600 */

+#define HRTIM_EECR2_EE7SNS            HRTIM_EECR2_EE7SNS_Msk                   /*!< External event 7 sensitivity */

+#define HRTIM_EECR2_EE7SNS_0          (0x1UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000200 */

+#define HRTIM_EECR2_EE7SNS_1          (0x2UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000400 */

+

+#define HRTIM_EECR2_EE8SRC_Pos        (12U)

+#define HRTIM_EECR2_EE8SRC_Msk        (0x3UL << HRTIM_EECR2_EE8SRC_Pos)        /*!< 0x00003000 */

+#define HRTIM_EECR2_EE8SRC            HRTIM_EECR2_EE8SRC_Msk                   /*!< External event 8 source */

+#define HRTIM_EECR2_EE8SRC_0          (0x1UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00001000 */

+#define HRTIM_EECR2_EE8SRC_1          (0x2UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00002000 */

+#define HRTIM_EECR2_EE8POL_Pos        (14U)

+#define HRTIM_EECR2_EE8POL_Msk        (0x1UL << HRTIM_EECR2_EE8POL_Pos)        /*!< 0x00004000 */

+#define HRTIM_EECR2_EE8POL            HRTIM_EECR2_EE8POL_Msk                   /*!< External event 8 Polarity */

+#define HRTIM_EECR2_EE8SNS_Pos        (15U)

+#define HRTIM_EECR2_EE8SNS_Msk        (0x3UL << HRTIM_EECR2_EE8SNS_Pos)        /*!< 0x00018000 */

+#define HRTIM_EECR2_EE8SNS            HRTIM_EECR2_EE8SNS_Msk                   /*!< External event 8 sensitivity */

+#define HRTIM_EECR2_EE8SNS_0          (0x1UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00008000 */

+#define HRTIM_EECR2_EE8SNS_1          (0x2UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00010000 */

+

+#define HRTIM_EECR2_EE9SRC_Pos        (18U)

+#define HRTIM_EECR2_EE9SRC_Msk        (0x3UL << HRTIM_EECR2_EE9SRC_Pos)        /*!< 0x000C0000 */

+#define HRTIM_EECR2_EE9SRC            HRTIM_EECR2_EE9SRC_Msk                   /*!< External event 9 source */

+#define HRTIM_EECR2_EE9SRC_0          (0x1UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00040000 */

+#define HRTIM_EECR2_EE9SRC_1          (0x2UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00080000 */

+#define HRTIM_EECR2_EE9POL_Pos        (20U)

+#define HRTIM_EECR2_EE9POL_Msk        (0x1UL << HRTIM_EECR2_EE9POL_Pos)        /*!< 0x00100000 */

+#define HRTIM_EECR2_EE9POL            HRTIM_EECR2_EE9POL_Msk                   /*!< External event 9 Polarity */

+#define HRTIM_EECR2_EE9SNS_Pos        (21U)

+#define HRTIM_EECR2_EE9SNS_Msk        (0x3UL << HRTIM_EECR2_EE9SNS_Pos)        /*!< 0x00600000 */

+#define HRTIM_EECR2_EE9SNS            HRTIM_EECR2_EE9SNS_Msk                   /*!< External event 9 sensitivity */

+#define HRTIM_EECR2_EE9SNS_0          (0x1UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00200000 */

+#define HRTIM_EECR2_EE9SNS_1          (0x2UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00400000 */

+

+#define HRTIM_EECR2_EE10SRC_Pos       (24U)

+#define HRTIM_EECR2_EE10SRC_Msk       (0x3UL << HRTIM_EECR2_EE10SRC_Pos)       /*!< 0x03000000 */

+#define HRTIM_EECR2_EE10SRC           HRTIM_EECR2_EE10SRC_Msk                  /*!< External event 10 source */

+#define HRTIM_EECR2_EE10SRC_0         (0x1UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x01000000 */

+#define HRTIM_EECR2_EE10SRC_1         (0x2UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x02000000 */

+#define HRTIM_EECR2_EE10POL_Pos       (26U)

+#define HRTIM_EECR2_EE10POL_Msk       (0x1UL << HRTIM_EECR2_EE10POL_Pos)       /*!< 0x04000000 */

+#define HRTIM_EECR2_EE10POL           HRTIM_EECR2_EE10POL_Msk                  /*!< External event 10 Polarity */

+#define HRTIM_EECR2_EE10SNS_Pos       (27U)

+#define HRTIM_EECR2_EE10SNS_Msk       (0x3UL << HRTIM_EECR2_EE10SNS_Pos)       /*!< 0x18000000 */

+#define HRTIM_EECR2_EE10SNS           HRTIM_EECR2_EE10SNS_Msk                  /*!< External event 10 sensitivity */

+#define HRTIM_EECR2_EE10SNS_0         (0x1UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x08000000 */

+#define HRTIM_EECR2_EE10SNS_1         (0x2UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x10000000 */

+

+/*******************  Bit definition for HRTIM_EECR3 register  ****************/

+#define HRTIM_EECR3_EE6F_Pos          (0U)

+#define HRTIM_EECR3_EE6F_Msk          (0xFUL << HRTIM_EECR3_EE6F_Pos)          /*!< 0x0000000F */

+#define HRTIM_EECR3_EE6F              HRTIM_EECR3_EE6F_Msk                     /*!< External event 6 filter */

+#define HRTIM_EECR3_EE6F_0            (0x1UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000001 */

+#define HRTIM_EECR3_EE6F_1            (0x2UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000002 */

+#define HRTIM_EECR3_EE6F_2            (0x4UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000004 */

+#define HRTIM_EECR3_EE6F_3            (0x8UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000008 */

+#define HRTIM_EECR3_EE7F_Pos          (6U)

+#define HRTIM_EECR3_EE7F_Msk          (0xFUL << HRTIM_EECR3_EE7F_Pos)          /*!< 0x000003C0 */

+#define HRTIM_EECR3_EE7F              HRTIM_EECR3_EE7F_Msk                     /*!< External event 7 filter */

+#define HRTIM_EECR3_EE7F_0            (0x1UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000040 */

+#define HRTIM_EECR3_EE7F_1            (0x2UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000080 */

+#define HRTIM_EECR3_EE7F_2            (0x4UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000100 */

+#define HRTIM_EECR3_EE7F_3            (0x8UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000200 */

+#define HRTIM_EECR3_EE8F_Pos          (12U)

+#define HRTIM_EECR3_EE8F_Msk          (0xFUL << HRTIM_EECR3_EE8F_Pos)          /*!< 0x0000F000 */

+#define HRTIM_EECR3_EE8F              HRTIM_EECR3_EE8F_Msk                     /*!< External event 8 filter */

+#define HRTIM_EECR3_EE8F_0            (0x1UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00001000 */

+#define HRTIM_EECR3_EE8F_1            (0x2UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00002000 */

+#define HRTIM_EECR3_EE8F_2            (0x4UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00004000 */

+#define HRTIM_EECR3_EE8F_3            (0x8UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00008000 */

+#define HRTIM_EECR3_EE9F_Pos          (18U)

+#define HRTIM_EECR3_EE9F_Msk          (0xFUL << HRTIM_EECR3_EE9F_Pos)          /*!< 0x003C0000 */

+#define HRTIM_EECR3_EE9F              HRTIM_EECR3_EE9F_Msk                     /*!< External event 9 filter */

+#define HRTIM_EECR3_EE9F_0            (0x1UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00040000 */

+#define HRTIM_EECR3_EE9F_1            (0x2UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00080000 */

+#define HRTIM_EECR3_EE9F_2            (0x4UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00100000 */

+#define HRTIM_EECR3_EE9F_3            (0x8UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00200000 */

+#define HRTIM_EECR3_EE10F_Pos         (24U)

+#define HRTIM_EECR3_EE10F_Msk         (0xFUL << HRTIM_EECR3_EE10F_Pos)         /*!< 0x0F000000 */

+#define HRTIM_EECR3_EE10F             HRTIM_EECR3_EE10F_Msk                    /*!< External event 10 filter */

+#define HRTIM_EECR3_EE10F_0           (0x1UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x01000000 */

+#define HRTIM_EECR3_EE10F_1           (0x2UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x02000000 */

+#define HRTIM_EECR3_EE10F_2           (0x4UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x04000000 */

+#define HRTIM_EECR3_EE10F_3           (0x8UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x08000000 */

+#define HRTIM_EECR3_EEVSD_Pos         (30U)

+#define HRTIM_EECR3_EEVSD_Msk         (0x3UL << HRTIM_EECR3_EEVSD_Pos)         /*!< 0xC0000000 */

+#define HRTIM_EECR3_EEVSD             HRTIM_EECR3_EEVSD_Msk                    /*!< External event sampling clock division */

+#define HRTIM_EECR3_EEVSD_0           (0x1UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x40000000 */

+#define HRTIM_EECR3_EEVSD_1           (0x2UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x80000000 */

+

+/*******************  Bit definition for HRTIM_ADC1R register  ****************/

+#define HRTIM_ADC1R_AD1MC1_Pos        (0U)

+#define HRTIM_ADC1R_AD1MC1_Msk        (0x1UL << HRTIM_ADC1R_AD1MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC1R_AD1MC1            HRTIM_ADC1R_AD1MC1_Msk                   /*!< ADC Trigger 1 on master compare 1 */

+#define HRTIM_ADC1R_AD1MC2_Pos        (1U)

+#define HRTIM_ADC1R_AD1MC2_Msk        (0x1UL << HRTIM_ADC1R_AD1MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC1R_AD1MC2            HRTIM_ADC1R_AD1MC2_Msk                   /*!< ADC Trigger 1 on master compare 2 */

+#define HRTIM_ADC1R_AD1MC3_Pos        (2U)

+#define HRTIM_ADC1R_AD1MC3_Msk        (0x1UL << HRTIM_ADC1R_AD1MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC1R_AD1MC3            HRTIM_ADC1R_AD1MC3_Msk                   /*!< ADC Trigger 1 on master compare 3 */

+#define HRTIM_ADC1R_AD1MC4_Pos        (3U)

+#define HRTIM_ADC1R_AD1MC4_Msk        (0x1UL << HRTIM_ADC1R_AD1MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC1R_AD1MC4            HRTIM_ADC1R_AD1MC4_Msk                   /*!< ADC Trigger 1 on master compare 4 */

+#define HRTIM_ADC1R_AD1MPER_Pos       (4U)

+#define HRTIM_ADC1R_AD1MPER_Msk       (0x1UL << HRTIM_ADC1R_AD1MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC1R_AD1MPER           HRTIM_ADC1R_AD1MPER_Msk                  /*!< ADC Trigger 1 on master period */

+#define HRTIM_ADC1R_AD1EEV1_Pos       (5U)

+#define HRTIM_ADC1R_AD1EEV1_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC1R_AD1EEV1           HRTIM_ADC1R_AD1EEV1_Msk                  /*!< ADC Trigger 1 on external event 1 */

+#define HRTIM_ADC1R_AD1EEV2_Pos       (6U)

+#define HRTIM_ADC1R_AD1EEV2_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC1R_AD1EEV2           HRTIM_ADC1R_AD1EEV2_Msk                  /*!< ADC Trigger 1 on external event 2 */

+#define HRTIM_ADC1R_AD1EEV3_Pos       (7U)

+#define HRTIM_ADC1R_AD1EEV3_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC1R_AD1EEV3           HRTIM_ADC1R_AD1EEV3_Msk                  /*!< ADC Trigger 1 on external event 3 */

+#define HRTIM_ADC1R_AD1EEV4_Pos       (8U)

+#define HRTIM_ADC1R_AD1EEV4_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC1R_AD1EEV4           HRTIM_ADC1R_AD1EEV4_Msk                  /*!< ADC Trigger 1 on external event 4 */

+#define HRTIM_ADC1R_AD1EEV5_Pos       (9U)

+#define HRTIM_ADC1R_AD1EEV5_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos)       /*!< 0x00000200 */

+#define HRTIM_ADC1R_AD1EEV5           HRTIM_ADC1R_AD1EEV5_Msk                  /*!< ADC Trigger 1 on external event 5 */

+#define HRTIM_ADC1R_AD1TAC2_Pos       (10U)

+#define HRTIM_ADC1R_AD1TAC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC1R_AD1TAC2           HRTIM_ADC1R_AD1TAC2_Msk                  /*!< ADC Trigger 1 on Timer A compare 2 */

+#define HRTIM_ADC1R_AD1TAC3_Pos       (11U)

+#define HRTIM_ADC1R_AD1TAC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC1R_AD1TAC3           HRTIM_ADC1R_AD1TAC3_Msk                  /*!< ADC Trigger 1 on Timer A compare 3 */

+#define HRTIM_ADC1R_AD1TAC4_Pos       (12U)

+#define HRTIM_ADC1R_AD1TAC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC1R_AD1TAC4           HRTIM_ADC1R_AD1TAC4_Msk                  /*!< ADC Trigger 1 on Timer A compare 4 */

+#define HRTIM_ADC1R_AD1TAPER_Pos      (13U)

+#define HRTIM_ADC1R_AD1TAPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC1R_AD1TAPER          HRTIM_ADC1R_AD1TAPER_Msk                 /*!< ADC Trigger 1 on Timer A period */

+#define HRTIM_ADC1R_AD1TARST_Pos      (14U)

+#define HRTIM_ADC1R_AD1TARST_Msk      (0x1UL << HRTIM_ADC1R_AD1TARST_Pos)      /*!< 0x00004000 */

+#define HRTIM_ADC1R_AD1TARST          HRTIM_ADC1R_AD1TARST_Msk                 /*!< ADC Trigger 1 on Timer A reset */

+#define HRTIM_ADC1R_AD1TBC2_Pos       (15U)

+#define HRTIM_ADC1R_AD1TBC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC2_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC1R_AD1TBC2           HRTIM_ADC1R_AD1TBC2_Msk                  /*!< ADC Trigger 1 on Timer B compare 2 */

+#define HRTIM_ADC1R_AD1TBC3_Pos       (16U)

+#define HRTIM_ADC1R_AD1TBC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC1R_AD1TBC3           HRTIM_ADC1R_AD1TBC3_Msk                  /*!< ADC Trigger 1 on Timer B compare 3 */

+#define HRTIM_ADC1R_AD1TBC4_Pos       (17U)

+#define HRTIM_ADC1R_AD1TBC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos)       /*!< 0x00020000 */

+#define HRTIM_ADC1R_AD1TBC4           HRTIM_ADC1R_AD1TBC4_Msk                  /*!< ADC Trigger 1 on Timer B compare 4 */

+#define HRTIM_ADC1R_AD1TBPER_Pos      (18U)

+#define HRTIM_ADC1R_AD1TBPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos)      /*!< 0x00040000 */

+#define HRTIM_ADC1R_AD1TBPER          HRTIM_ADC1R_AD1TBPER_Msk                 /*!< ADC Trigger 1 on Timer B period */

+#define HRTIM_ADC1R_AD1TBRST_Pos      (19U)

+#define HRTIM_ADC1R_AD1TBRST_Msk      (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos)      /*!< 0x00080000 */

+#define HRTIM_ADC1R_AD1TBRST          HRTIM_ADC1R_AD1TBRST_Msk                 /*!< ADC Trigger 1 on Timer B reset */

+#define HRTIM_ADC1R_AD1TCC2_Pos       (20U)

+#define HRTIM_ADC1R_AD1TCC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC2_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC1R_AD1TCC2           HRTIM_ADC1R_AD1TCC2_Msk                  /*!< ADC Trigger 1 on Timer C compare 2 */

+#define HRTIM_ADC1R_AD1TCC3_Pos       (21U)

+#define HRTIM_ADC1R_AD1TCC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos)       /*!< 0x00200000 */

+#define HRTIM_ADC1R_AD1TCC3           HRTIM_ADC1R_AD1TCC3_Msk                  /*!< ADC Trigger 1 on Timer C compare 3 */

+#define HRTIM_ADC1R_AD1TCC4_Pos       (22U)

+#define HRTIM_ADC1R_AD1TCC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos)       /*!< 0x00400000 */

+#define HRTIM_ADC1R_AD1TCC4           HRTIM_ADC1R_AD1TCC4_Msk                  /*!< ADC Trigger 1 on Timer C compare 4 */

+#define HRTIM_ADC1R_AD1TCPER_Pos      (23U)

+#define HRTIM_ADC1R_AD1TCPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos)      /*!< 0x00800000 */

+#define HRTIM_ADC1R_AD1TCPER          HRTIM_ADC1R_AD1TCPER_Msk                 /*!< ADC Trigger 1 on Timer C period */

+#define HRTIM_ADC1R_AD1TDC2_Pos       (24U)

+#define HRTIM_ADC1R_AD1TDC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC2_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC1R_AD1TDC2           HRTIM_ADC1R_AD1TDC2_Msk                  /*!< ADC Trigger 1 on Timer D compare 2 */

+#define HRTIM_ADC1R_AD1TDC3_Pos       (25U)

+#define HRTIM_ADC1R_AD1TDC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC1R_AD1TDC3           HRTIM_ADC1R_AD1TDC3_Msk                  /*!< ADC Trigger 1 on Timer D compare 3 */

+#define HRTIM_ADC1R_AD1TDC4_Pos       (26U)

+#define HRTIM_ADC1R_AD1TDC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos)       /*!< 0x04000000 */

+#define HRTIM_ADC1R_AD1TDC4           HRTIM_ADC1R_AD1TDC4_Msk                  /*!< ADC Trigger 1 on Timer D compare 4 */

+#define HRTIM_ADC1R_AD1TDPER_Pos      (27U)

+#define HRTIM_ADC1R_AD1TDPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC1R_AD1TDPER          HRTIM_ADC1R_AD1TDPER_Msk                 /*!< ADC Trigger 1 on Timer D period */

+#define HRTIM_ADC1R_AD1TEC2_Pos       (28U)

+#define HRTIM_ADC1R_AD1TEC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC1R_AD1TEC2           HRTIM_ADC1R_AD1TEC2_Msk                  /*!< ADC Trigger 1 on Timer E compare 2 */

+#define HRTIM_ADC1R_AD1TEC3_Pos       (29U)

+#define HRTIM_ADC1R_AD1TEC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC1R_AD1TEC3           HRTIM_ADC1R_AD1TEC3_Msk                  /*!< ADC Trigger 1 on Timer E compare 3 */

+#define HRTIM_ADC1R_AD1TEC4_Pos       (30U)

+#define HRTIM_ADC1R_AD1TEC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC1R_AD1TEC4           HRTIM_ADC1R_AD1TEC4_Msk                  /*!< ADC Trigger 1 on Timer E compare 4 */

+#define HRTIM_ADC1R_AD1TEPER_Pos      (31U)

+#define HRTIM_ADC1R_AD1TEPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC1R_AD1TEPER          HRTIM_ADC1R_AD1TEPER_Msk                 /*!< ADC Trigger 1 on Timer E period */

+

+/*******************  Bit definition for HRTIM_ADC2R register  ****************/

+#define HRTIM_ADC2R_AD2MC1_Pos        (0U)

+#define HRTIM_ADC2R_AD2MC1_Msk        (0x1UL << HRTIM_ADC2R_AD2MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC2R_AD2MC1            HRTIM_ADC2R_AD2MC1_Msk                   /*!< ADC Trigger 2 on master compare 1 */

+#define HRTIM_ADC2R_AD2MC2_Pos        (1U)

+#define HRTIM_ADC2R_AD2MC2_Msk        (0x1UL << HRTIM_ADC2R_AD2MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC2R_AD2MC2            HRTIM_ADC2R_AD2MC2_Msk                   /*!< ADC Trigger 2 on master compare 2 */

+#define HRTIM_ADC2R_AD2MC3_Pos        (2U)

+#define HRTIM_ADC2R_AD2MC3_Msk        (0x1UL << HRTIM_ADC2R_AD2MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC2R_AD2MC3            HRTIM_ADC2R_AD2MC3_Msk                   /*!< ADC Trigger 2 on master compare 3 */

+#define HRTIM_ADC2R_AD2MC4_Pos        (3U)

+#define HRTIM_ADC2R_AD2MC4_Msk        (0x1UL << HRTIM_ADC2R_AD2MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC2R_AD2MC4            HRTIM_ADC2R_AD2MC4_Msk                   /*!< ADC Trigger 2 on master compare 4 */

+#define HRTIM_ADC2R_AD2MPER_Pos       (4U)

+#define HRTIM_ADC2R_AD2MPER_Msk       (0x1UL << HRTIM_ADC2R_AD2MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC2R_AD2MPER           HRTIM_ADC2R_AD2MPER_Msk                  /*!< ADC Trigger 2 on master period */

+#define HRTIM_ADC2R_AD2EEV6_Pos       (5U)

+#define HRTIM_ADC2R_AD2EEV6_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC2R_AD2EEV6           HRTIM_ADC2R_AD2EEV6_Msk                  /*!< ADC Trigger 2 on external event 6 */

+#define HRTIM_ADC2R_AD2EEV7_Pos       (6U)

+#define HRTIM_ADC2R_AD2EEV7_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC2R_AD2EEV7           HRTIM_ADC2R_AD2EEV7_Msk                  /*!< ADC Trigger 2 on external event 7 */

+#define HRTIM_ADC2R_AD2EEV8_Pos       (7U)

+#define HRTIM_ADC2R_AD2EEV8_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC2R_AD2EEV8           HRTIM_ADC2R_AD2EEV8_Msk                  /*!< ADC Trigger 2 on external event 8 */

+#define HRTIM_ADC2R_AD2EEV9_Pos       (8U)

+#define HRTIM_ADC2R_AD2EEV9_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC2R_AD2EEV9           HRTIM_ADC2R_AD2EEV9_Msk                  /*!< ADC Trigger 2 on external event 9 */

+#define HRTIM_ADC2R_AD2EEV10_Pos      (9U)

+#define HRTIM_ADC2R_AD2EEV10_Msk      (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos)      /*!< 0x00000200 */

+#define HRTIM_ADC2R_AD2EEV10          HRTIM_ADC2R_AD2EEV10_Msk                 /*!< ADC Trigger 2 on external event 10 */

+#define HRTIM_ADC2R_AD2TAC2_Pos       (10U)

+#define HRTIM_ADC2R_AD2TAC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC2R_AD2TAC2           HRTIM_ADC2R_AD2TAC2_Msk                  /*!< ADC Trigger 2 on Timer A compare 2 */

+#define HRTIM_ADC2R_AD2TAC3_Pos       (11U)

+#define HRTIM_ADC2R_AD2TAC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC2R_AD2TAC3           HRTIM_ADC2R_AD2TAC3_Msk                  /*!< ADC Trigger 2 on Timer A compare 3 */

+#define HRTIM_ADC2R_AD2TAC4_Pos       (12U)

+#define HRTIM_ADC2R_AD2TAC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC2R_AD2TAC4           HRTIM_ADC2R_AD2TAC4_Msk                  /*!< ADC Trigger 2 on Timer A compare 4*/

+#define HRTIM_ADC2R_AD2TAPER_Pos      (13U)

+#define HRTIM_ADC2R_AD2TAPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC2R_AD2TAPER          HRTIM_ADC2R_AD2TAPER_Msk                 /*!< ADC Trigger 2 on Timer A period */

+#define HRTIM_ADC2R_AD2TBC2_Pos       (14U)

+#define HRTIM_ADC2R_AD2TBC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos)       /*!< 0x00004000 */

+#define HRTIM_ADC2R_AD2TBC2           HRTIM_ADC2R_AD2TBC2_Msk                  /*!< ADC Trigger 2 on Timer B compare 2 */

+#define HRTIM_ADC2R_AD2TBC3_Pos       (15U)

+#define HRTIM_ADC2R_AD2TBC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC3_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC2R_AD2TBC3           HRTIM_ADC2R_AD2TBC3_Msk                  /*!< ADC Trigger 2 on Timer B compare 3 */

+#define HRTIM_ADC2R_AD2TBC4_Pos       (16U)

+#define HRTIM_ADC2R_AD2TBC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC2R_AD2TBC4           HRTIM_ADC2R_AD2TBC4_Msk                  /*!< ADC Trigger 2 on Timer B compare 4 */

+#define HRTIM_ADC2R_AD2TBPER_Pos      (17U)

+#define HRTIM_ADC2R_AD2TBPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos)      /*!< 0x00020000 */

+#define HRTIM_ADC2R_AD2TBPER          HRTIM_ADC2R_AD2TBPER_Msk                 /*!< ADC Trigger 2 on Timer B period */

+#define HRTIM_ADC2R_AD2TCC2_Pos       (18U)

+#define HRTIM_ADC2R_AD2TCC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos)       /*!< 0x00040000 */

+#define HRTIM_ADC2R_AD2TCC2           HRTIM_ADC2R_AD2TCC2_Msk                  /*!< ADC Trigger 2 on Timer C compare 2 */

+#define HRTIM_ADC2R_AD2TCC3_Pos       (19U)

+#define HRTIM_ADC2R_AD2TCC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC3_Pos)       /*!< 0x00080000 */

+#define HRTIM_ADC2R_AD2TCC3           HRTIM_ADC2R_AD2TCC3_Msk                  /*!< ADC Trigger 2 on Timer C compare 3 */

+#define HRTIM_ADC2R_AD2TCC4_Pos       (20U)

+#define HRTIM_ADC2R_AD2TCC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC2R_AD2TCC4           HRTIM_ADC2R_AD2TCC4_Msk                  /*!< ADC Trigger 2 on Timer C compare 4 */

+#define HRTIM_ADC2R_AD2TCPER_Pos      (21U)

+#define HRTIM_ADC2R_AD2TCPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos)      /*!< 0x00200000 */

+#define HRTIM_ADC2R_AD2TCPER          HRTIM_ADC2R_AD2TCPER_Msk                 /*!< ADC Trigger 2 on Timer C period */

+#define HRTIM_ADC2R_AD2TCRST_Pos      (22U)

+#define HRTIM_ADC2R_AD2TCRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos)      /*!< 0x00400000 */

+#define HRTIM_ADC2R_AD2TCRST          HRTIM_ADC2R_AD2TCRST_Msk                 /*!< ADC Trigger 2 on Timer C reset */

+#define HRTIM_ADC2R_AD2TDC2_Pos       (23U)

+#define HRTIM_ADC2R_AD2TDC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos)       /*!< 0x00800000 */

+#define HRTIM_ADC2R_AD2TDC2           HRTIM_ADC2R_AD2TDC2_Msk                  /*!< ADC Trigger 2 on Timer D compare 2 */

+#define HRTIM_ADC2R_AD2TDC3_Pos       (24U)

+#define HRTIM_ADC2R_AD2TDC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC3_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC2R_AD2TDC3           HRTIM_ADC2R_AD2TDC3_Msk                  /*!< ADC Trigger 2 on Timer D compare 3 */

+#define HRTIM_ADC2R_AD2TDC4_Pos       (25U)

+#define HRTIM_ADC2R_AD2TDC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC2R_AD2TDC4           HRTIM_ADC2R_AD2TDC4_Msk                  /*!< ADC Trigger 2 on Timer D compare 4*/

+#define HRTIM_ADC2R_AD2TDPER_Pos      (26U)

+#define HRTIM_ADC2R_AD2TDPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos)      /*!< 0x04000000 */

+#define HRTIM_ADC2R_AD2TDPER          HRTIM_ADC2R_AD2TDPER_Msk                 /*!< ADC Trigger 2 on Timer D period */

+#define HRTIM_ADC2R_AD2TDRST_Pos      (27U)

+#define HRTIM_ADC2R_AD2TDRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC2R_AD2TDRST          HRTIM_ADC2R_AD2TDRST_Msk                 /*!< ADC Trigger 2 on Timer D reset */

+#define HRTIM_ADC2R_AD2TEC2_Pos       (28U)

+#define HRTIM_ADC2R_AD2TEC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC2R_AD2TEC2           HRTIM_ADC2R_AD2TEC2_Msk                  /*!< ADC Trigger 2 on Timer E compare 2 */

+#define HRTIM_ADC2R_AD2TEC3_Pos       (29U)

+#define HRTIM_ADC2R_AD2TEC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC2R_AD2TEC3           HRTIM_ADC2R_AD2TEC3_Msk                  /*!< ADC Trigger 2 on Timer E compare 3 */

+#define HRTIM_ADC2R_AD2TEC4_Pos       (30U)

+#define HRTIM_ADC2R_AD2TEC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC2R_AD2TEC4           HRTIM_ADC2R_AD2TEC4_Msk                  /*!< ADC Trigger 2 on Timer E compare 4 */

+#define HRTIM_ADC2R_AD2TERST_Pos      (31U)

+#define HRTIM_ADC2R_AD2TERST_Msk      (0x1UL << HRTIM_ADC2R_AD2TERST_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC2R_AD2TERST          HRTIM_ADC2R_AD2TERST_Msk                 /*!< ADC Trigger 2 on Timer E reset */

+

+/*******************  Bit definition for HRTIM_ADC3R register  ****************/

+#define HRTIM_ADC3R_AD3MC1_Pos        (0U)

+#define HRTIM_ADC3R_AD3MC1_Msk        (0x1UL << HRTIM_ADC3R_AD3MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC3R_AD3MC1            HRTIM_ADC3R_AD3MC1_Msk                   /*!< ADC Trigger 3 on master compare 1 */

+#define HRTIM_ADC3R_AD3MC2_Pos        (1U)

+#define HRTIM_ADC3R_AD3MC2_Msk        (0x1UL << HRTIM_ADC3R_AD3MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC3R_AD3MC2            HRTIM_ADC3R_AD3MC2_Msk                   /*!< ADC Trigger 3 on master compare 2 */

+#define HRTIM_ADC3R_AD3MC3_Pos        (2U)

+#define HRTIM_ADC3R_AD3MC3_Msk        (0x1UL << HRTIM_ADC3R_AD3MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC3R_AD3MC3            HRTIM_ADC3R_AD3MC3_Msk                   /*!< ADC Trigger 3 on master compare 3 */

+#define HRTIM_ADC3R_AD3MC4_Pos        (3U)

+#define HRTIM_ADC3R_AD3MC4_Msk        (0x1UL << HRTIM_ADC3R_AD3MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC3R_AD3MC4            HRTIM_ADC3R_AD3MC4_Msk                   /*!< ADC Trigger 3 on master compare 4 */

+#define HRTIM_ADC3R_AD3MPER_Pos       (4U)

+#define HRTIM_ADC3R_AD3MPER_Msk       (0x1UL << HRTIM_ADC3R_AD3MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC3R_AD3MPER           HRTIM_ADC3R_AD3MPER_Msk                  /*!< ADC Trigger 3 on master period */

+#define HRTIM_ADC3R_AD3EEV1_Pos       (5U)

+#define HRTIM_ADC3R_AD3EEV1_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC3R_AD3EEV1           HRTIM_ADC3R_AD3EEV1_Msk                  /*!< ADC Trigger 3 on external event 1 */

+#define HRTIM_ADC3R_AD3EEV2_Pos       (6U)

+#define HRTIM_ADC3R_AD3EEV2_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC3R_AD3EEV2           HRTIM_ADC3R_AD3EEV2_Msk                  /*!< ADC Trigger 3 on external event 2 */

+#define HRTIM_ADC3R_AD3EEV3_Pos       (7U)

+#define HRTIM_ADC3R_AD3EEV3_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC3R_AD3EEV3           HRTIM_ADC3R_AD3EEV3_Msk                  /*!< ADC Trigger 3 on external event 3 */

+#define HRTIM_ADC3R_AD3EEV4_Pos       (8U)

+#define HRTIM_ADC3R_AD3EEV4_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC3R_AD3EEV4           HRTIM_ADC3R_AD3EEV4_Msk                  /*!< ADC Trigger 3 on external event 4 */

+#define HRTIM_ADC3R_AD3EEV5_Pos       (9U)

+#define HRTIM_ADC3R_AD3EEV5_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos)       /*!< 0x00000200 */

+#define HRTIM_ADC3R_AD3EEV5           HRTIM_ADC3R_AD3EEV5_Msk                  /*!< ADC Trigger 3 on external event 5 */

+#define HRTIM_ADC3R_AD3TAC2_Pos       (10U)

+#define HRTIM_ADC3R_AD3TAC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC3R_AD3TAC2           HRTIM_ADC3R_AD3TAC2_Msk                  /*!< ADC Trigger 3 on Timer A compare 2 */

+#define HRTIM_ADC3R_AD3TAC3_Pos       (11U)

+#define HRTIM_ADC3R_AD3TAC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC3R_AD3TAC3           HRTIM_ADC3R_AD3TAC3_Msk                  /*!< ADC Trigger 3 on Timer A compare 3 */

+#define HRTIM_ADC3R_AD3TAC4_Pos       (12U)

+#define HRTIM_ADC3R_AD3TAC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC3R_AD3TAC4           HRTIM_ADC3R_AD3TAC4_Msk                  /*!< ADC Trigger 3 on Timer A compare 4 */

+#define HRTIM_ADC3R_AD3TAPER_Pos      (13U)

+#define HRTIM_ADC3R_AD3TAPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC3R_AD3TAPER          HRTIM_ADC3R_AD3TAPER_Msk                 /*!< ADC Trigger 3 on Timer A period */

+#define HRTIM_ADC3R_AD3TARST_Pos      (14U)

+#define HRTIM_ADC3R_AD3TARST_Msk      (0x1UL << HRTIM_ADC3R_AD3TARST_Pos)      /*!< 0x00004000 */

+#define HRTIM_ADC3R_AD3TARST          HRTIM_ADC3R_AD3TARST_Msk                 /*!< ADC Trigger 3 on Timer A reset */

+#define HRTIM_ADC3R_AD3TBC2_Pos       (15U)

+#define HRTIM_ADC3R_AD3TBC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC2_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC3R_AD3TBC2           HRTIM_ADC3R_AD3TBC2_Msk                  /*!< ADC Trigger 3 on Timer B compare 2 */

+#define HRTIM_ADC3R_AD3TBC3_Pos       (16U)

+#define HRTIM_ADC3R_AD3TBC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC3R_AD3TBC3           HRTIM_ADC3R_AD3TBC3_Msk                  /*!< ADC Trigger 3 on Timer B compare 3 */

+#define HRTIM_ADC3R_AD3TBC4_Pos       (17U)

+#define HRTIM_ADC3R_AD3TBC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos)       /*!< 0x00020000 */

+#define HRTIM_ADC3R_AD3TBC4           HRTIM_ADC3R_AD3TBC4_Msk                  /*!< ADC Trigger 3 on Timer B compare 4 */

+#define HRTIM_ADC3R_AD3TBPER_Pos      (18U)

+#define HRTIM_ADC3R_AD3TBPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos)      /*!< 0x00040000 */

+#define HRTIM_ADC3R_AD3TBPER          HRTIM_ADC3R_AD3TBPER_Msk                 /*!< ADC Trigger 3 on Timer B period */

+#define HRTIM_ADC3R_AD3TBRST_Pos      (19U)

+#define HRTIM_ADC3R_AD3TBRST_Msk      (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos)      /*!< 0x00080000 */

+#define HRTIM_ADC3R_AD3TBRST          HRTIM_ADC3R_AD3TBRST_Msk                 /*!< ADC Trigger 3 on Timer B reset */

+#define HRTIM_ADC3R_AD3TCC2_Pos       (20U)

+#define HRTIM_ADC3R_AD3TCC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC2_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC3R_AD3TCC2           HRTIM_ADC3R_AD3TCC2_Msk                  /*!< ADC Trigger 3 on Timer C compare 2 */

+#define HRTIM_ADC3R_AD3TCC3_Pos       (21U)

+#define HRTIM_ADC3R_AD3TCC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos)       /*!< 0x00200000 */

+#define HRTIM_ADC3R_AD3TCC3           HRTIM_ADC3R_AD3TCC3_Msk                  /*!< ADC Trigger 3 on Timer C compare 3 */

+#define HRTIM_ADC3R_AD3TCC4_Pos       (22U)

+#define HRTIM_ADC3R_AD3TCC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos)       /*!< 0x00400000 */

+#define HRTIM_ADC3R_AD3TCC4           HRTIM_ADC3R_AD3TCC4_Msk                  /*!< ADC Trigger 3 on Timer C compare 4 */

+#define HRTIM_ADC3R_AD3TCPER_Pos      (23U)

+#define HRTIM_ADC3R_AD3TCPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos)      /*!< 0x00800000 */

+#define HRTIM_ADC3R_AD3TCPER          HRTIM_ADC3R_AD3TCPER_Msk                 /*!< ADC Trigger 3 on Timer C period */

+#define HRTIM_ADC3R_AD3TDC2_Pos       (24U)

+#define HRTIM_ADC3R_AD3TDC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC2_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC3R_AD3TDC2           HRTIM_ADC3R_AD3TDC2_Msk                  /*!< ADC Trigger 3 on Timer D compare 2 */

+#define HRTIM_ADC3R_AD3TDC3_Pos       (25U)

+#define HRTIM_ADC3R_AD3TDC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC3R_AD3TDC3           HRTIM_ADC3R_AD3TDC3_Msk                  /*!< ADC Trigger 3 on Timer D compare 3 */

+#define HRTIM_ADC3R_AD3TDC4_Pos       (26U)

+#define HRTIM_ADC3R_AD3TDC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos)       /*!< 0x04000000 */

+#define HRTIM_ADC3R_AD3TDC4           HRTIM_ADC3R_AD3TDC4_Msk                  /*!< ADC Trigger 3 on Timer D compare 4 */

+#define HRTIM_ADC3R_AD3TDPER_Pos      (27U)

+#define HRTIM_ADC3R_AD3TDPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC3R_AD3TDPER          HRTIM_ADC3R_AD3TDPER_Msk                 /*!< ADC Trigger 3 on Timer D period */

+#define HRTIM_ADC3R_AD3TEC2_Pos       (28U)

+#define HRTIM_ADC3R_AD3TEC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC3R_AD3TEC2           HRTIM_ADC3R_AD3TEC2_Msk                  /*!< ADC Trigger 3 on Timer E compare 2 */

+#define HRTIM_ADC3R_AD3TEC3_Pos       (29U)

+#define HRTIM_ADC3R_AD3TEC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC3R_AD3TEC3           HRTIM_ADC3R_AD3TEC3_Msk                  /*!< ADC Trigger 3 on Timer E compare 3 */

+#define HRTIM_ADC3R_AD3TEC4_Pos       (30U)

+#define HRTIM_ADC3R_AD3TEC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC3R_AD3TEC4           HRTIM_ADC3R_AD3TEC4_Msk                  /*!< ADC Trigger 3 on Timer E compare 4 */

+#define HRTIM_ADC3R_AD3TEPER_Pos      (31U)

+#define HRTIM_ADC3R_AD3TEPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC3R_AD3TEPER          HRTIM_ADC3R_AD3TEPER_Msk                 /*!< ADC Trigger 3 on Timer E period */

+

+/*******************  Bit definition for HRTIM_ADC4R register  ****************/

+#define HRTIM_ADC4R_AD4MC1_Pos        (0U)

+#define HRTIM_ADC4R_AD4MC1_Msk        (0x1UL << HRTIM_ADC4R_AD4MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC4R_AD4MC1            HRTIM_ADC4R_AD4MC1_Msk                   /*!< ADC Trigger 4 on master compare 1 */

+#define HRTIM_ADC4R_AD4MC2_Pos        (1U)

+#define HRTIM_ADC4R_AD4MC2_Msk        (0x1UL << HRTIM_ADC4R_AD4MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC4R_AD4MC2            HRTIM_ADC4R_AD4MC2_Msk                   /*!< ADC Trigger 4 on master compare 2 */

+#define HRTIM_ADC4R_AD4MC3_Pos        (2U)

+#define HRTIM_ADC4R_AD4MC3_Msk        (0x1UL << HRTIM_ADC4R_AD4MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC4R_AD4MC3            HRTIM_ADC4R_AD4MC3_Msk                   /*!< ADC Trigger 4 on master compare 3 */

+#define HRTIM_ADC4R_AD4MC4_Pos        (3U)

+#define HRTIM_ADC4R_AD4MC4_Msk        (0x1UL << HRTIM_ADC4R_AD4MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC4R_AD4MC4            HRTIM_ADC4R_AD4MC4_Msk                   /*!< ADC Trigger 4 on master compare 4 */

+#define HRTIM_ADC4R_AD4MPER_Pos       (4U)

+#define HRTIM_ADC4R_AD4MPER_Msk       (0x1UL << HRTIM_ADC4R_AD4MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC4R_AD4MPER           HRTIM_ADC4R_AD4MPER_Msk                  /*!< ADC Trigger 4 on master period */

+#define HRTIM_ADC4R_AD4EEV6_Pos       (5U)

+#define HRTIM_ADC4R_AD4EEV6_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC4R_AD4EEV6           HRTIM_ADC4R_AD4EEV6_Msk                  /*!< ADC Trigger 4 on external event 6 */

+#define HRTIM_ADC4R_AD4EEV7_Pos       (6U)

+#define HRTIM_ADC4R_AD4EEV7_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC4R_AD4EEV7           HRTIM_ADC4R_AD4EEV7_Msk                  /*!< ADC Trigger 4 on external event 7 */

+#define HRTIM_ADC4R_AD4EEV8_Pos       (7U)

+#define HRTIM_ADC4R_AD4EEV8_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC4R_AD4EEV8           HRTIM_ADC4R_AD4EEV8_Msk                  /*!< ADC Trigger 4 on external event 8 */

+#define HRTIM_ADC4R_AD4EEV9_Pos       (8U)

+#define HRTIM_ADC4R_AD4EEV9_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC4R_AD4EEV9           HRTIM_ADC4R_AD4EEV9_Msk                  /*!< ADC Trigger 4 on external event 9 */

+#define HRTIM_ADC4R_AD4EEV10_Pos      (9U)

+#define HRTIM_ADC4R_AD4EEV10_Msk      (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos)      /*!< 0x00000200 */

+#define HRTIM_ADC4R_AD4EEV10          HRTIM_ADC4R_AD4EEV10_Msk                 /*!< ADC Trigger 4 on external event 10 */

+#define HRTIM_ADC4R_AD4TAC2_Pos       (10U)

+#define HRTIM_ADC4R_AD4TAC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC4R_AD4TAC2           HRTIM_ADC4R_AD4TAC2_Msk                  /*!< ADC Trigger 4 on Timer A compare 2 */

+#define HRTIM_ADC4R_AD4TAC3_Pos       (11U)

+#define HRTIM_ADC4R_AD4TAC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC4R_AD4TAC3           HRTIM_ADC4R_AD4TAC3_Msk                  /*!< ADC Trigger 4 on Timer A compare 3 */

+#define HRTIM_ADC4R_AD4TAC4_Pos       (12U)

+#define HRTIM_ADC4R_AD4TAC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC4R_AD4TAC4           HRTIM_ADC4R_AD4TAC4_Msk                  /*!< ADC Trigger 4 on Timer A compare 4*/

+#define HRTIM_ADC4R_AD4TAPER_Pos      (13U)

+#define HRTIM_ADC4R_AD4TAPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC4R_AD4TAPER          HRTIM_ADC4R_AD4TAPER_Msk                 /*!< ADC Trigger 4 on Timer A period */

+#define HRTIM_ADC4R_AD4TBC2_Pos       (14U)

+#define HRTIM_ADC4R_AD4TBC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos)       /*!< 0x00004000 */

+#define HRTIM_ADC4R_AD4TBC2           HRTIM_ADC4R_AD4TBC2_Msk                  /*!< ADC Trigger 4 on Timer B compare 2 */

+#define HRTIM_ADC4R_AD4TBC3_Pos       (15U)

+#define HRTIM_ADC4R_AD4TBC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC3_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC4R_AD4TBC3           HRTIM_ADC4R_AD4TBC3_Msk                  /*!< ADC Trigger 4 on Timer B compare 3 */

+#define HRTIM_ADC4R_AD4TBC4_Pos       (16U)

+#define HRTIM_ADC4R_AD4TBC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC4R_AD4TBC4           HRTIM_ADC4R_AD4TBC4_Msk                  /*!< ADC Trigger 4 on Timer B compare 4 */

+#define HRTIM_ADC4R_AD4TBPER_Pos      (17U)

+#define HRTIM_ADC4R_AD4TBPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos)      /*!< 0x00020000 */

+#define HRTIM_ADC4R_AD4TBPER          HRTIM_ADC4R_AD4TBPER_Msk                 /*!< ADC Trigger 4 on Timer B period */

+#define HRTIM_ADC4R_AD4TCC2_Pos       (18U)

+#define HRTIM_ADC4R_AD4TCC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos)       /*!< 0x00040000 */

+#define HRTIM_ADC4R_AD4TCC2           HRTIM_ADC4R_AD4TCC2_Msk                  /*!< ADC Trigger 4 on Timer C compare 2 */

+#define HRTIM_ADC4R_AD4TCC3_Pos       (19U)

+#define HRTIM_ADC4R_AD4TCC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC3_Pos)       /*!< 0x00080000 */

+#define HRTIM_ADC4R_AD4TCC3           HRTIM_ADC4R_AD4TCC3_Msk                  /*!< ADC Trigger 4 on Timer C compare 3 */

+#define HRTIM_ADC4R_AD4TCC4_Pos       (20U)

+#define HRTIM_ADC4R_AD4TCC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC4R_AD4TCC4           HRTIM_ADC4R_AD4TCC4_Msk                  /*!< ADC Trigger 4 on Timer C compare 4 */

+#define HRTIM_ADC4R_AD4TCPER_Pos      (21U)

+#define HRTIM_ADC4R_AD4TCPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos)      /*!< 0x00200000 */

+#define HRTIM_ADC4R_AD4TCPER          HRTIM_ADC4R_AD4TCPER_Msk                 /*!< ADC Trigger 4 on Timer C period */

+#define HRTIM_ADC4R_AD4TCRST_Pos      (22U)

+#define HRTIM_ADC4R_AD4TCRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos)      /*!< 0x00400000 */

+#define HRTIM_ADC4R_AD4TCRST          HRTIM_ADC4R_AD4TCRST_Msk                 /*!< ADC Trigger 4 on Timer C reset */

+#define HRTIM_ADC4R_AD4TDC2_Pos       (23U)

+#define HRTIM_ADC4R_AD4TDC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos)       /*!< 0x00800000 */

+#define HRTIM_ADC4R_AD4TDC2           HRTIM_ADC4R_AD4TDC2_Msk                  /*!< ADC Trigger 4 on Timer D compare 2 */

+#define HRTIM_ADC4R_AD4TDC3_Pos       (24U)

+#define HRTIM_ADC4R_AD4TDC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC3_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC4R_AD4TDC3           HRTIM_ADC4R_AD4TDC3_Msk                  /*!< ADC Trigger 4 on Timer D compare 3 */

+#define HRTIM_ADC4R_AD4TDC4_Pos       (25U)

+#define HRTIM_ADC4R_AD4TDC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC4R_AD4TDC4           HRTIM_ADC4R_AD4TDC4_Msk                  /*!< ADC Trigger 4 on Timer D compare 4*/

+#define HRTIM_ADC4R_AD4TDPER_Pos      (26U)

+#define HRTIM_ADC4R_AD4TDPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos)      /*!< 0x04000000 */

+#define HRTIM_ADC4R_AD4TDPER          HRTIM_ADC4R_AD4TDPER_Msk                 /*!< ADC Trigger 4 on Timer D period */

+#define HRTIM_ADC4R_AD4TDRST_Pos      (27U)

+#define HRTIM_ADC4R_AD4TDRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC4R_AD4TDRST          HRTIM_ADC4R_AD4TDRST_Msk                 /*!< ADC Trigger 4 on Timer D reset */

+#define HRTIM_ADC4R_AD4TEC2_Pos       (28U)

+#define HRTIM_ADC4R_AD4TEC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC4R_AD4TEC2           HRTIM_ADC4R_AD4TEC2_Msk                  /*!< ADC Trigger 4 on Timer E compare 2 */

+#define HRTIM_ADC4R_AD4TEC3_Pos       (29U)

+#define HRTIM_ADC4R_AD4TEC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC4R_AD4TEC3           HRTIM_ADC4R_AD4TEC3_Msk                  /*!< ADC Trigger 4 on Timer E compare 3 */

+#define HRTIM_ADC4R_AD4TEC4_Pos       (30U)

+#define HRTIM_ADC4R_AD4TEC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC4R_AD4TEC4           HRTIM_ADC4R_AD4TEC4_Msk                  /*!< ADC Trigger 4 on Timer E compare 4 */

+#define HRTIM_ADC4R_AD4TERST_Pos      (31U)

+#define HRTIM_ADC4R_AD4TERST_Msk      (0x1UL << HRTIM_ADC4R_AD4TERST_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC4R_AD4TERST          HRTIM_ADC4R_AD4TERST_Msk                 /*!< ADC Trigger 4 on Timer E reset */

+

+/*******************  Bit definition for HRTIM_FLTINR1 register  ***************/

+#define HRTIM_FLTINR1_FLT1E_Pos       (0U)

+#define HRTIM_FLTINR1_FLT1E_Msk       (0x1UL << HRTIM_FLTINR1_FLT1E_Pos)       /*!< 0x00000001 */

+#define HRTIM_FLTINR1_FLT1E           HRTIM_FLTINR1_FLT1E_Msk                  /*!< Fault 1 enable */

+#define HRTIM_FLTINR1_FLT1P_Pos       (1U)

+#define HRTIM_FLTINR1_FLT1P_Msk       (0x1UL << HRTIM_FLTINR1_FLT1P_Pos)       /*!< 0x00000002 */

+#define HRTIM_FLTINR1_FLT1P           HRTIM_FLTINR1_FLT1P_Msk                  /*!< Fault 1 polarity */

+#define HRTIM_FLTINR1_FLT1SRC_Pos     (2U)

+#define HRTIM_FLTINR1_FLT1SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT1SRC_Pos)     /*!< 0x00000004 */

+#define HRTIM_FLTINR1_FLT1SRC         HRTIM_FLTINR1_FLT1SRC_Msk                /*!< Fault 1 source */

+#define HRTIM_FLTINR1_FLT1F_Pos       (3U)

+#define HRTIM_FLTINR1_FLT1F_Msk       (0xFUL << HRTIM_FLTINR1_FLT1F_Pos)       /*!< 0x00000078 */

+#define HRTIM_FLTINR1_FLT1F           HRTIM_FLTINR1_FLT1F_Msk                  /*!< Fault 1 filter */

+#define HRTIM_FLTINR1_FLT1F_0         (0x1UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000008 */

+#define HRTIM_FLTINR1_FLT1F_1         (0x2UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000010 */

+#define HRTIM_FLTINR1_FLT1F_2         (0x4UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000020 */

+#define HRTIM_FLTINR1_FLT1F_3         (0x8UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000040 */

+#define HRTIM_FLTINR1_FLT1LCK_Pos     (7U)

+#define HRTIM_FLTINR1_FLT1LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos)     /*!< 0x00000080 */

+#define HRTIM_FLTINR1_FLT1LCK         HRTIM_FLTINR1_FLT1LCK_Msk                /*!< Fault 1 lock */

+

+#define HRTIM_FLTINR1_FLT2E_Pos       (8U)

+#define HRTIM_FLTINR1_FLT2E_Msk       (0x1UL << HRTIM_FLTINR1_FLT2E_Pos)       /*!< 0x00000100 */

+#define HRTIM_FLTINR1_FLT2E           HRTIM_FLTINR1_FLT2E_Msk                  /*!< Fault 2 enable */

+#define HRTIM_FLTINR1_FLT2P_Pos       (9U)

+#define HRTIM_FLTINR1_FLT2P_Msk       (0x1UL << HRTIM_FLTINR1_FLT2P_Pos)       /*!< 0x00000200 */

+#define HRTIM_FLTINR1_FLT2P           HRTIM_FLTINR1_FLT2P_Msk                  /*!< Fault 2 polarity */

+#define HRTIM_FLTINR1_FLT2SRC_Pos     (10U)

+#define HRTIM_FLTINR1_FLT2SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT2SRC_Pos)     /*!< 0x00000400 */

+#define HRTIM_FLTINR1_FLT2SRC         HRTIM_FLTINR1_FLT2SRC_Msk                /*!< Fault 2 source */

+#define HRTIM_FLTINR1_FLT2F_Pos       (11U)

+#define HRTIM_FLTINR1_FLT2F_Msk       (0xFUL << HRTIM_FLTINR1_FLT2F_Pos)       /*!< 0x00007800 */

+#define HRTIM_FLTINR1_FLT2F           HRTIM_FLTINR1_FLT2F_Msk                  /*!< Fault 2 filter */

+#define HRTIM_FLTINR1_FLT2F_0         (0x1UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00000800 */

+#define HRTIM_FLTINR1_FLT2F_1         (0x2UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00001000 */

+#define HRTIM_FLTINR1_FLT2F_2         (0x4UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00002000 */

+#define HRTIM_FLTINR1_FLT2F_3         (0x8UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00004000 */

+#define HRTIM_FLTINR1_FLT2LCK_Pos     (15U)

+#define HRTIM_FLTINR1_FLT2LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos)     /*!< 0x00008000 */

+#define HRTIM_FLTINR1_FLT2LCK         HRTIM_FLTINR1_FLT2LCK_Msk                /*!< Fault 2 lock */

+

+#define HRTIM_FLTINR1_FLT3E_Pos       (16U)

+#define HRTIM_FLTINR1_FLT3E_Msk       (0x1UL << HRTIM_FLTINR1_FLT3E_Pos)       /*!< 0x00010000 */

+#define HRTIM_FLTINR1_FLT3E           HRTIM_FLTINR1_FLT3E_Msk                  /*!< Fault 3 enable */

+#define HRTIM_FLTINR1_FLT3P_Pos       (17U)

+#define HRTIM_FLTINR1_FLT3P_Msk       (0x1UL << HRTIM_FLTINR1_FLT3P_Pos)       /*!< 0x00020000 */

+#define HRTIM_FLTINR1_FLT3P           HRTIM_FLTINR1_FLT3P_Msk                  /*!< Fault 3 polarity */

+#define HRTIM_FLTINR1_FLT3SRC_Pos     (18U)

+#define HRTIM_FLTINR1_FLT3SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT3SRC_Pos)     /*!< 0x00040000 */

+#define HRTIM_FLTINR1_FLT3SRC         HRTIM_FLTINR1_FLT3SRC_Msk                /*!< Fault 3 source */

+#define HRTIM_FLTINR1_FLT3F_Pos       (19U)

+#define HRTIM_FLTINR1_FLT3F_Msk       (0xFUL << HRTIM_FLTINR1_FLT3F_Pos)       /*!< 0x00780000 */

+#define HRTIM_FLTINR1_FLT3F           HRTIM_FLTINR1_FLT3F_Msk                  /*!< Fault 3 filter */

+#define HRTIM_FLTINR1_FLT3F_0         (0x1UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00080000 */

+#define HRTIM_FLTINR1_FLT3F_1         (0x2UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00100000 */

+#define HRTIM_FLTINR1_FLT3F_2         (0x4UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00200000 */

+#define HRTIM_FLTINR1_FLT3F_3         (0x8UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00400000 */

+#define HRTIM_FLTINR1_FLT3LCK_Pos     (23U)

+#define HRTIM_FLTINR1_FLT3LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos)     /*!< 0x00800000 */

+#define HRTIM_FLTINR1_FLT3LCK         HRTIM_FLTINR1_FLT3LCK_Msk                /*!< Fault 3 lock */

+

+#define HRTIM_FLTINR1_FLT4E_Pos       (24U)

+#define HRTIM_FLTINR1_FLT4E_Msk       (0x1UL << HRTIM_FLTINR1_FLT4E_Pos)       /*!< 0x01000000 */

+#define HRTIM_FLTINR1_FLT4E           HRTIM_FLTINR1_FLT4E_Msk                  /*!< Fault 4 enable */

+#define HRTIM_FLTINR1_FLT4P_Pos       (25U)

+#define HRTIM_FLTINR1_FLT4P_Msk       (0x1UL << HRTIM_FLTINR1_FLT4P_Pos)       /*!< 0x02000000 */

+#define HRTIM_FLTINR1_FLT4P           HRTIM_FLTINR1_FLT4P_Msk                  /*!< Fault 4 polarity */

+#define HRTIM_FLTINR1_FLT4SRC_Pos     (26U)

+#define HRTIM_FLTINR1_FLT4SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT4SRC_Pos)     /*!< 0x04000000 */

+#define HRTIM_FLTINR1_FLT4SRC         HRTIM_FLTINR1_FLT4SRC_Msk                /*!< Fault 4 source */

+#define HRTIM_FLTINR1_FLT4F_Pos       (27U)

+#define HRTIM_FLTINR1_FLT4F_Msk       (0xFUL << HRTIM_FLTINR1_FLT4F_Pos)       /*!< 0x78000000 */

+#define HRTIM_FLTINR1_FLT4F           HRTIM_FLTINR1_FLT4F_Msk                  /*!< Fault 4 filter */

+#define HRTIM_FLTINR1_FLT4F_0         (0x1UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x08000000 */

+#define HRTIM_FLTINR1_FLT4F_1         (0x2UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x10000000 */

+#define HRTIM_FLTINR1_FLT4F_2         (0x4UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x20000000 */

+#define HRTIM_FLTINR1_FLT4F_3         (0x8UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x40000000 */

+#define HRTIM_FLTINR1_FLT4LCK_Pos     (31U)

+#define HRTIM_FLTINR1_FLT4LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos)     /*!< 0x80000000 */

+#define HRTIM_FLTINR1_FLT4LCK         HRTIM_FLTINR1_FLT4LCK_Msk                /*!< Fault 4 lock */

+

+/*******************  Bit definition for HRTIM_FLTINR2 register  ***************/

+#define HRTIM_FLTINR2_FLT5E_Pos       (0U)

+#define HRTIM_FLTINR2_FLT5E_Msk       (0x1UL << HRTIM_FLTINR2_FLT5E_Pos)       /*!< 0x00000001 */

+#define HRTIM_FLTINR2_FLT5E           HRTIM_FLTINR2_FLT5E_Msk                  /*!< Fault 5 enable */

+#define HRTIM_FLTINR2_FLT5P_Pos       (1U)

+#define HRTIM_FLTINR2_FLT5P_Msk       (0x1UL << HRTIM_FLTINR2_FLT5P_Pos)       /*!< 0x00000002 */

+#define HRTIM_FLTINR2_FLT5P           HRTIM_FLTINR2_FLT5P_Msk                  /*!< Fault 5 polarity */

+#define HRTIM_FLTINR2_FLT5SRC_Pos     (2U)

+#define HRTIM_FLTINR2_FLT5SRC_Msk     (0x1UL << HRTIM_FLTINR2_FLT5SRC_Pos)     /*!< 0x00000004 */

+#define HRTIM_FLTINR2_FLT5SRC         HRTIM_FLTINR2_FLT5SRC_Msk                /*!< Fault 5 source */

+#define HRTIM_FLTINR2_FLT5F_Pos       (3U)

+#define HRTIM_FLTINR2_FLT5F_Msk       (0xFUL << HRTIM_FLTINR2_FLT5F_Pos)       /*!< 0x00000078 */

+#define HRTIM_FLTINR2_FLT5F           HRTIM_FLTINR2_FLT5F_Msk                  /*!< Fault 5 filter */

+#define HRTIM_FLTINR2_FLT5F_0         (0x1UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000008 */

+#define HRTIM_FLTINR2_FLT5F_1         (0x2UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000010 */

+#define HRTIM_FLTINR2_FLT5F_2         (0x4UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000020 */

+#define HRTIM_FLTINR2_FLT5F_3         (0x8UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000040 */

+#define HRTIM_FLTINR2_FLT5LCK_Pos     (7U)

+#define HRTIM_FLTINR2_FLT5LCK_Msk     (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos)     /*!< 0x00000080 */

+#define HRTIM_FLTINR2_FLT5LCK         HRTIM_FLTINR2_FLT5LCK_Msk                /*!< Fault 5 lock */

+#define HRTIM_FLTINR2_FLTSD_Pos       (24U)

+#define HRTIM_FLTINR2_FLTSD_Msk       (0x3UL << HRTIM_FLTINR2_FLTSD_Pos)       /*!< 0x03000000 */

+#define HRTIM_FLTINR2_FLTSD           HRTIM_FLTINR2_FLTSD_Msk                  /*!< Fault sampling clock division */

+#define HRTIM_FLTINR2_FLTSD_0         (0x1UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x01000000 */

+#define HRTIM_FLTINR2_FLTSD_1         (0x2UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x02000000 */

+

+/*******************  Bit definition for HRTIM_BDMUPR register  ***************/

+#define HRTIM_BDMUPR_MCR_Pos          (0U)

+#define HRTIM_BDMUPR_MCR_Msk          (0x1UL << HRTIM_BDMUPR_MCR_Pos)          /*!< 0x00000001 */

+#define HRTIM_BDMUPR_MCR              HRTIM_BDMUPR_MCR_Msk                     /*!< MCR register update enable */

+#define HRTIM_BDMUPR_MICR_Pos         (1U)

+#define HRTIM_BDMUPR_MICR_Msk         (0x1UL << HRTIM_BDMUPR_MICR_Pos)         /*!< 0x00000002 */

+#define HRTIM_BDMUPR_MICR             HRTIM_BDMUPR_MICR_Msk                    /*!< MICR register update enable */

+#define HRTIM_BDMUPR_MDIER_Pos        (2U)

+#define HRTIM_BDMUPR_MDIER_Msk        (0x1UL << HRTIM_BDMUPR_MDIER_Pos)        /*!< 0x00000004 */

+#define HRTIM_BDMUPR_MDIER            HRTIM_BDMUPR_MDIER_Msk                   /*!< MDIER register update enable */

+#define HRTIM_BDMUPR_MCNT_Pos         (3U)

+#define HRTIM_BDMUPR_MCNT_Msk         (0x1UL << HRTIM_BDMUPR_MCNT_Pos)         /*!< 0x00000008 */

+#define HRTIM_BDMUPR_MCNT             HRTIM_BDMUPR_MCNT_Msk                    /*!< MCNT register update enable */

+#define HRTIM_BDMUPR_MPER_Pos         (4U)

+#define HRTIM_BDMUPR_MPER_Msk         (0x1UL << HRTIM_BDMUPR_MPER_Pos)         /*!< 0x00000010 */

+#define HRTIM_BDMUPR_MPER             HRTIM_BDMUPR_MPER_Msk                    /*!< MPER register update enable */

+#define HRTIM_BDMUPR_MREP_Pos         (5U)

+#define HRTIM_BDMUPR_MREP_Msk         (0x1UL << HRTIM_BDMUPR_MREP_Pos)         /*!< 0x00000020 */

+#define HRTIM_BDMUPR_MREP             HRTIM_BDMUPR_MREP_Msk                    /*!< MREP register update enable */

+#define HRTIM_BDMUPR_MCMP1_Pos        (6U)

+#define HRTIM_BDMUPR_MCMP1_Msk        (0x1UL << HRTIM_BDMUPR_MCMP1_Pos)        /*!< 0x00000040 */

+#define HRTIM_BDMUPR_MCMP1            HRTIM_BDMUPR_MCMP1_Msk                   /*!< MCMP1 register update enable */

+#define HRTIM_BDMUPR_MCMP2_Pos        (7U)

+#define HRTIM_BDMUPR_MCMP2_Msk        (0x1UL << HRTIM_BDMUPR_MCMP2_Pos)        /*!< 0x00000080 */

+#define HRTIM_BDMUPR_MCMP2            HRTIM_BDMUPR_MCMP2_Msk                   /*!< MCMP2 register update enable */

+#define HRTIM_BDMUPR_MCMP3_Pos        (8U)

+#define HRTIM_BDMUPR_MCMP3_Msk        (0x1UL << HRTIM_BDMUPR_MCMP3_Pos)        /*!< 0x00000100 */

+#define HRTIM_BDMUPR_MCMP3            HRTIM_BDMUPR_MCMP3_Msk                   /*!< MCMP3 register update enable */

+#define HRTIM_BDMUPR_MCMP4_Pos        (9U)

+#define HRTIM_BDMUPR_MCMP4_Msk        (0x1UL << HRTIM_BDMUPR_MCMP4_Pos)        /*!< 0x00000200 */

+#define HRTIM_BDMUPR_MCMP4            HRTIM_BDMUPR_MCMP4_Msk                   /*!< MPCMP4 register update enable */

+

+/*******************  Bit definition for HRTIM_BDTUPR register  ***************/

+#define HRTIM_BDTUPR_TIMCR_Pos        (0U)

+#define HRTIM_BDTUPR_TIMCR_Msk        (0x1UL << HRTIM_BDTUPR_TIMCR_Pos)        /*!< 0x00000001 */

+#define HRTIM_BDTUPR_TIMCR            HRTIM_BDTUPR_TIMCR_Msk                   /*!<  TIMCR register update enable */

+#define HRTIM_BDTUPR_TIMICR_Pos       (1U)

+#define HRTIM_BDTUPR_TIMICR_Msk       (0x1UL << HRTIM_BDTUPR_TIMICR_Pos)       /*!< 0x00000002 */

+#define HRTIM_BDTUPR_TIMICR           HRTIM_BDTUPR_TIMICR_Msk                  /*!<  TIMICR register update enable */

+#define HRTIM_BDTUPR_TIMDIER_Pos      (2U)

+#define HRTIM_BDTUPR_TIMDIER_Msk      (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos)      /*!< 0x00000004 */

+#define HRTIM_BDTUPR_TIMDIER          HRTIM_BDTUPR_TIMDIER_Msk                 /*!<  TIMDIER register update enable */

+#define HRTIM_BDTUPR_TIMCNT_Pos       (3U)

+#define HRTIM_BDTUPR_TIMCNT_Msk       (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos)       /*!< 0x00000008 */

+#define HRTIM_BDTUPR_TIMCNT           HRTIM_BDTUPR_TIMCNT_Msk                  /*!<  TIMCNT register update enable */

+#define HRTIM_BDTUPR_TIMPER_Pos       (4U)

+#define HRTIM_BDTUPR_TIMPER_Msk       (0x1UL << HRTIM_BDTUPR_TIMPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_BDTUPR_TIMPER           HRTIM_BDTUPR_TIMPER_Msk                  /*!<  TIMPER register update enable */

+#define HRTIM_BDTUPR_TIMREP_Pos       (5U)

+#define HRTIM_BDTUPR_TIMREP_Msk       (0x1UL << HRTIM_BDTUPR_TIMREP_Pos)       /*!< 0x00000020 */

+#define HRTIM_BDTUPR_TIMREP           HRTIM_BDTUPR_TIMREP_Msk                  /*!<  TIMREP register update enable */

+#define HRTIM_BDTUPR_TIMCMP1_Pos      (6U)

+#define HRTIM_BDTUPR_TIMCMP1_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos)      /*!< 0x00000040 */

+#define HRTIM_BDTUPR_TIMCMP1          HRTIM_BDTUPR_TIMCMP1_Msk                 /*!<  TIMCMP1 register update enable */

+#define HRTIM_BDTUPR_TIMCMP2_Pos      (7U)

+#define HRTIM_BDTUPR_TIMCMP2_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos)      /*!< 0x00000080 */

+#define HRTIM_BDTUPR_TIMCMP2          HRTIM_BDTUPR_TIMCMP2_Msk                 /*!<  TIMCMP2 register update enable */

+#define HRTIM_BDTUPR_TIMCMP3_Pos      (8U)

+#define HRTIM_BDTUPR_TIMCMP3_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos)      /*!< 0x00000100 */

+#define HRTIM_BDTUPR_TIMCMP3          HRTIM_BDTUPR_TIMCMP3_Msk                 /*!<  TIMCMP3 register update enable */

+#define HRTIM_BDTUPR_TIMCMP4_Pos      (9U)

+#define HRTIM_BDTUPR_TIMCMP4_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos)      /*!< 0x00000200 */

+#define HRTIM_BDTUPR_TIMCMP4          HRTIM_BDTUPR_TIMCMP4_Msk                 /*!<  TIMCMP4 register update enable */

+#define HRTIM_BDTUPR_TIMDTR_Pos       (10U)

+#define HRTIM_BDTUPR_TIMDTR_Msk       (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos)       /*!< 0x00000400 */

+#define HRTIM_BDTUPR_TIMDTR           HRTIM_BDTUPR_TIMDTR_Msk                  /*!<  TIMDTR register update enable */

+#define HRTIM_BDTUPR_TIMSET1R_Pos     (11U)

+#define HRTIM_BDTUPR_TIMSET1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos)     /*!< 0x00000800 */

+#define HRTIM_BDTUPR_TIMSET1R         HRTIM_BDTUPR_TIMSET1R_Msk                /*!<  TIMSET1R register update enable */

+#define HRTIM_BDTUPR_TIMRST1R_Pos     (12U)

+#define HRTIM_BDTUPR_TIMRST1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos)     /*!< 0x00001000 */

+#define HRTIM_BDTUPR_TIMRST1R         HRTIM_BDTUPR_TIMRST1R_Msk                /*!<  TIMRST1R register update enable */

+#define HRTIM_BDTUPR_TIMSET2R_Pos     (13U)

+#define HRTIM_BDTUPR_TIMSET2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos)     /*!< 0x00002000 */

+#define HRTIM_BDTUPR_TIMSET2R         HRTIM_BDTUPR_TIMSET2R_Msk                /*!<  TIMSET2R register update enable */

+#define HRTIM_BDTUPR_TIMRST2R_Pos     (14U)

+#define HRTIM_BDTUPR_TIMRST2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos)     /*!< 0x00004000 */

+#define HRTIM_BDTUPR_TIMRST2R         HRTIM_BDTUPR_TIMRST2R_Msk                /*!<  TIMRST2R register update enable */

+#define HRTIM_BDTUPR_TIMEEFR1_Pos     (15U)

+#define HRTIM_BDTUPR_TIMEEFR1_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos)     /*!< 0x00008000 */

+#define HRTIM_BDTUPR_TIMEEFR1         HRTIM_BDTUPR_TIMEEFR1_Msk                /*!<  TIMEEFR1 register update enable */

+#define HRTIM_BDTUPR_TIMEEFR2_Pos     (16U)

+#define HRTIM_BDTUPR_TIMEEFR2_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos)     /*!< 0x00010000 */

+#define HRTIM_BDTUPR_TIMEEFR2         HRTIM_BDTUPR_TIMEEFR2_Msk                /*!<  TIMEEFR2 register update enable */

+#define HRTIM_BDTUPR_TIMRSTR_Pos      (17U)

+#define HRTIM_BDTUPR_TIMRSTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos)      /*!< 0x00020000 */

+#define HRTIM_BDTUPR_TIMRSTR          HRTIM_BDTUPR_TIMRSTR_Msk                 /*!<  TIMRSTR register update enable */

+#define HRTIM_BDTUPR_TIMCHPR_Pos      (18U)

+#define HRTIM_BDTUPR_TIMCHPR_Msk      (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos)      /*!< 0x00040000 */

+#define HRTIM_BDTUPR_TIMCHPR          HRTIM_BDTUPR_TIMCHPR_Msk                 /*!<  TIMCHPR register update enable */

+#define HRTIM_BDTUPR_TIMOUTR_Pos      (19U)

+#define HRTIM_BDTUPR_TIMOUTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos)      /*!< 0x00080000 */

+#define HRTIM_BDTUPR_TIMOUTR          HRTIM_BDTUPR_TIMOUTR_Msk                 /*!<  TIMOUTR register update enable */

+#define HRTIM_BDTUPR_TIMFLTR_Pos      (20U)

+#define HRTIM_BDTUPR_TIMFLTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos)      /*!< 0x00100000 */

+#define HRTIM_BDTUPR_TIMFLTR          HRTIM_BDTUPR_TIMFLTR_Msk                 /*!<  TIMFLTR register update enable */

+

+/*******************  Bit definition for HRTIM_BDMADR register  ***************/

+#define HRTIM_BDMADR_BDMADR_Pos       (0U)

+#define HRTIM_BDMADR_BDMADR_Msk       (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos) /*!< 0xFFFFFFFF */

+#define HRTIM_BDMADR_BDMADR           HRTIM_BDMADR_BDMADR_Msk                  /*!<  Burst DMA Data register */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             RAM ECC monitoring                             */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for RAMECC_IER register  ******************/

+#define RAMECC_IER_GECCDEBWIE_Pos         (3U)

+#define RAMECC_IER_GECCDEBWIE_Msk         (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)  /*!< 0x00000008 */

+#define RAMECC_IER_GECCDEBWIE             RAMECC_IER_GECCDEBWIE_Msk             /*!< Global ECC double error on byte write (BW) interrupt enable */

+#define RAMECC_IER_GECCDEIE_Pos           (2U)

+#define RAMECC_IER_GECCDEIE_Msk           (0x1UL << RAMECC_IER_GECCDEIE_Pos)    /*!< 0x00000004 */

+#define RAMECC_IER_GECCDEIE               RAMECC_IER_GECCDEIE_Msk               /*!< Global ECC double error interrupt enable */

+#define RAMECC_IER_GECCSEIE_Pos           (1U)

+#define RAMECC_IER_GECCSEIE_Msk           (0x1UL << RAMECC_IER_GECCSEIE_Pos)    /*!< 0x00000002 */

+#define RAMECC_IER_GECCSEIE               RAMECC_IER_GECCSEIE_Msk               /*!< Global ECC single error interrupt enable */

+#define RAMECC_IER_GIE_Pos                (0U)

+#define RAMECC_IER_GIE_Msk                (0x1UL << RAMECC_IER_GIE_Pos)         /*!< 0x00000001 */

+#define RAMECC_IER_GIE                    RAMECC_IER_GIE_Msk                    /*!< Global interrupt enable */

+

+/*******************  Bit definition for RAMECC_CR register  ******************/

+#define RAMECC_CR_ECCELEN_Pos             (5U)

+#define RAMECC_CR_ECCELEN_Msk             (0x1UL << RAMECC_CR_ECCELEN_Pos)      /*!< 0x00000020 */

+#define RAMECC_CR_ECCELEN                 RAMECC_CR_ECCELEN_Msk                 /*!< ECC error latching enable */

+#define RAMECC_CR_ECCDEBWIE_Pos           (4U)

+#define RAMECC_CR_ECCDEBWIE_Msk           (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)    /*!< 0x00000010 */

+#define RAMECC_CR_ECCDEBWIE               RAMECC_CR_ECCDEBWIE_Msk               /*!< ECC double error on byte write (BW) interrupt enable */

+#define RAMECC_CR_ECCDEIE_Pos             (3U)

+#define RAMECC_CR_ECCDEIE_Msk             (0x1UL << RAMECC_CR_ECCDEIE_Pos)      /*!< 0x00000008 */

+#define RAMECC_CR_ECCDEIE                 RAMECC_CR_ECCDEIE_Msk                 /*!< ECC double error interrupt enable */

+#define RAMECC_CR_ECCSEIE_Pos             (2U)

+#define RAMECC_CR_ECCSEIE_Msk             (0x1UL << RAMECC_CR_ECCSEIE_Pos)      /*!< 0x00000004 */

+#define RAMECC_CR_ECCSEIE                 RAMECC_CR_ECCSEIE_Msk                 /*!< ECC single error interrupt enable */

+

+/*******************  Bit definition for RAMECC_SR register  ******************/

+#define RAMECC_SR_DEBWDF_Pos             (2U)

+#define RAMECC_SR_DEBWDF_Msk             (0x1UL << RAMECC_SR_DEBWDF_Pos)        /*!< 0x00000004 */

+#define RAMECC_SR_DEBWDF                 RAMECC_SR_DEBWDF_Msk                   /*!< ECC double error on byte write (BW) detected flag */

+#define RAMECC_SR_DEDF_Pos               (1U)

+#define RAMECC_SR_DEDF_Msk               (0x1UL << RAMECC_SR_DEDF_Pos)          /*!< 0x00000002 */

+#define RAMECC_SR_DEDF                   RAMECC_SR_DEDF_Msk                     /*!< ECC double error detected flag */

+#define RAMECC_SR_SEDCF_Pos              (0U)

+#define RAMECC_SR_SEDCF_Msk              (0x1UL << RAMECC_SR_SEDCF_Pos)         /*!< 0x00000001 */

+#define RAMECC_SR_SEDCF                  RAMECC_SR_SEDCF_Msk                    /*!< ECC single error detected and corrected flag */

+

+/******************  Bit definition for RAMECC_FAR register  ******************/

+#define RAMECC_FAR_FADD_Pos              (0U)

+#define RAMECC_FAR_FADD_Msk              (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)  /*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FADD                  RAMECC_FAR_FADD_Msk                    /*!< ECC error failing address */

+

+/******************  Bit definition for RAMECC_FDRL register  *****************/

+#define RAMECC_FAR_FDATAL_Pos            (0U)

+#define RAMECC_FAR_FDATAL_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FDATAL                RAMECC_FAR_FDATAL_Msk                  /*!< ECC error failing address */

+

+/******************  Bit definition for RAMECC_FDRH register  *****************/

+#define RAMECC_FAR_FDATAH_Pos            (0U)

+#define RAMECC_FAR_FDATAH_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FDATAH                RAMECC_FAR_FDATAH_Msk                  /* Failing data high (64-bit memory) */

+

+/*****************  Bit definition for RAMECC_FECR register  ******************/

+#define RAMECC_FECR_FEC_Pos              (0U)

+#define RAMECC_FECR_FEC_Msk              (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)  /*!< 0xFFFFFFFF */

+#define RAMECC_FECR_FEC                  RAMECC_FECR_FEC_Msk                    /*!< Failing error code */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                MDIOS                                        */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for MDIOS_CR register  *******************/

+#define MDIOS_CR_EN_Pos                (0U)

+#define MDIOS_CR_EN_Msk                (0x1UL << MDIOS_CR_EN_Pos)              /*!< 0x00000001 */

+#define MDIOS_CR_EN                    MDIOS_CR_EN_Msk                         /*!<  MDIOS slave peripheral enable */

+#define MDIOS_CR_WRIE_Pos              (1U)

+#define MDIOS_CR_WRIE_Msk              (0x1UL << MDIOS_CR_WRIE_Pos)            /*!< 0x00000002 */

+#define MDIOS_CR_WRIE                  MDIOS_CR_WRIE_Msk                       /*!<  MDIOS slave register write interrupt enable. */

+#define MDIOS_CR_RDIE_Pos              (2U)

+#define MDIOS_CR_RDIE_Msk              (0x1UL << MDIOS_CR_RDIE_Pos)            /*!< 0x00000004 */

+#define MDIOS_CR_RDIE                  MDIOS_CR_RDIE_Msk                       /*!<  MDIOS slave register read interrupt enable. */

+#define MDIOS_CR_EIE_Pos               (3U)

+#define MDIOS_CR_EIE_Msk               (0x1UL << MDIOS_CR_EIE_Pos)             /*!< 0x00000008 */

+#define MDIOS_CR_EIE                   MDIOS_CR_EIE_Msk                        /*!<  MDIOS slave register error interrupt enable. */

+#define MDIOS_CR_DPC_Pos               (7U)

+#define MDIOS_CR_DPC_Msk               (0x1UL << MDIOS_CR_DPC_Pos)             /*!< 0x00000080 */

+#define MDIOS_CR_DPC                   MDIOS_CR_DPC_Msk                        /*!<  MDIOS slave disable preamble check. */

+#define MDIOS_CR_PORT_ADDRESS_Pos      (8U)

+#define MDIOS_CR_PORT_ADDRESS_Msk      (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)   /*!< 0x00001F00 */

+#define MDIOS_CR_PORT_ADDRESS          MDIOS_CR_PORT_ADDRESS_Msk               /*!<  MDIOS slave port address mask. */

+#define MDIOS_CR_PORT_ADDRESS_0        (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000100 */

+#define MDIOS_CR_PORT_ADDRESS_1        (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000200 */

+#define MDIOS_CR_PORT_ADDRESS_2        (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000400 */

+#define MDIOS_CR_PORT_ADDRESS_3        (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000800 */

+#define MDIOS_CR_PORT_ADDRESS_4        (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001000 */

+

+/********************  Bit definition for MDIOS_SR register  *******************/

+#define MDIOS_SR_PERF_Pos              (0U)

+#define MDIOS_SR_PERF_Msk              (0x1UL << MDIOS_SR_PERF_Pos)            /*!< 0x00000001 */

+#define MDIOS_SR_PERF                  MDIOS_SR_PERF_Msk                       /*!<  MDIOS slave turnaround error flag*/

+#define MDIOS_SR_SERF_Pos              (1U)

+#define MDIOS_SR_SERF_Msk              (0x1UL << MDIOS_SR_SERF_Pos)            /*!< 0x00000002 */

+#define MDIOS_SR_SERF                  MDIOS_SR_SERF_Msk                       /*!<  MDIOS slave start error flag */

+#define MDIOS_SR_TERF_Pos              (2U)

+#define MDIOS_SR_TERF_Msk              (0x1UL << MDIOS_SR_TERF_Pos)            /*!< 0x00000004 */

+#define MDIOS_SR_TERF                  MDIOS_SR_TERF_Msk                       /*!<  MDIOS slave preamble error flag */

+

+/********************  Bit definition for MDIOS_CLRFR register  *******************/

+#define MDIOS_SR_CPERF_Pos             (0U)

+#define MDIOS_SR_CPERF_Msk             (0x1UL << MDIOS_SR_CPERF_Pos)           /*!< 0x00000001 */

+#define MDIOS_SR_CPERF                 MDIOS_SR_CPERF_Msk                      /*!<  MDIOS slave Clear the turnaround error flag */

+#define MDIOS_SR_CSERF_Pos             (1U)

+#define MDIOS_SR_CSERF_Msk             (0x1UL << MDIOS_SR_CSERF_Pos)           /*!< 0x00000002 */

+#define MDIOS_SR_CSERF                 MDIOS_SR_CSERF_Msk                      /*!<  MDIOS slave Clear the start error flag */

+#define MDIOS_SR_CTERF_Pos             (2U)

+#define MDIOS_SR_CTERF_Msk             (0x1UL << MDIOS_SR_CTERF_Pos)           /*!< 0x00000004 */

+#define MDIOS_SR_CTERF                 MDIOS_SR_CTERF_Msk                      /*!<  MDIOS slave Clear the preamble error flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                       USB_OTG                              */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/

+#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)

+#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */

+#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */

+#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)

+#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */

+#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */

+#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)

+#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */

+#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */

+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)

+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */

+#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */

+#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)

+#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */

+#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */

+#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)

+#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */

+#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */

+#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)

+#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */

+#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */

+#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)

+#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */

+#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */

+#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)

+#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */

+#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */

+#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)

+#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */

+#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */

+#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)

+#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */

+#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */

+#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)

+#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */

+#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */

+#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)

+#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */

+#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */

+#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)

+#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */

+#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */

+#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)

+#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */

+#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */

+#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)

+#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */

+#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */

+#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)

+#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */

+#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */

+#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)

+#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */

+#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */

+

+/********************  Bit definition forUSB_OTG_HCFG register  ********************/

+

+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)

+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */

+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */

+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)

+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */

+

+/********************  Bit definition forUSB_OTG_DCFG register  ********************/

+

+#define USB_OTG_DCFG_DSPD_Pos                    (0U)

+#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */

+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */

+#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */

+#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)

+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */

+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */

+

+#define USB_OTG_DCFG_DAD_Pos                     (4U)

+#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */

+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */

+#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */

+#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */

+#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */

+#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */

+#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */

+#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */

+#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */

+

+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)

+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */

+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */

+#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */

+#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */

+

+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)

+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */

+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */

+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */

+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */

+

+/********************  Bit definition forUSB_OTG_PCGCR register  ********************/

+#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)

+#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */

+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */

+#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)

+#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */

+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */

+#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)

+#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */

+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */

+

+/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/

+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)

+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */

+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */

+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)

+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */

+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */

+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)

+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */

+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */

+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)

+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */

+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */

+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)

+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */

+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */

+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)

+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */

+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */

+

+/********************  Bit definition forUSB_OTG_DCTL register  ********************/

+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)

+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */

+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */

+#define USB_OTG_DCTL_SDIS_Pos                    (1U)

+#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */

+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */

+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)

+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */

+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */

+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)

+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */

+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */

+

+#define USB_OTG_DCTL_TCTL_Pos                    (4U)

+#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */

+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */

+#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */

+#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */

+#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */

+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)

+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */

+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */

+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)

+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */

+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */

+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)

+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */

+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */

+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)

+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */

+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */

+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)

+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */

+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */

+

+/********************  Bit definition forUSB_OTG_HFIR register  ********************/

+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)

+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */

+

+/********************  Bit definition forUSB_OTG_HFNUM register  ********************/

+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)

+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */

+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)

+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */

+

+/********************  Bit definition forUSB_OTG_DSTS register  ********************/

+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)

+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */

+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */

+

+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)

+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */

+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */

+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */

+#define USB_OTG_DSTS_EERR_Pos                    (3U)

+#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */

+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */

+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)

+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */

+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */

+

+/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/

+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)

+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */

+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */

+

+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)

+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */

+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */

+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */

+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */

+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */

+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */

+#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */

+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)

+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */

+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */

+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)

+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */

+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */

+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)

+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */

+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */

+

+/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/

+

+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)

+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */

+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */

+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */

+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */

+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */

+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)

+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */

+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */

+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)

+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */

+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */

+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)

+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */

+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */

+

+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)

+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */

+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */

+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */

+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */

+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */

+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */

+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)

+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */

+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */

+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)

+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */

+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */

+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)

+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */

+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */

+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)

+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */

+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */

+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)

+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */

+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */

+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)

+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */

+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */

+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)

+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */

+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */

+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)

+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */

+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */

+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)

+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */

+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */

+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)

+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */

+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */

+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)

+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */

+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */

+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)

+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */

+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */

+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)

+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */

+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */

+

+/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/

+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)

+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */

+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */

+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)

+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */

+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */

+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)

+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */

+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */

+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)

+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */

+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */

+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)

+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */

+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */

+

+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)

+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */

+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */

+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */

+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */

+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */

+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */

+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */

+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)

+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */

+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */

+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)

+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */

+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */

+

+/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/

+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)

+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */

+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)

+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */

+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)

+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */

+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)

+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */

+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)

+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */

+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)

+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */

+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)

+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */

+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)

+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */

+

+/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/

+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)

+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */

+

+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)

+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */

+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */

+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */

+

+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)

+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */

+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */

+

+/********************  Bit definition forUSB_OTG_HAINT register  ********************/

+#define USB_OTG_HAINT_HAINT_Pos                  (0U)

+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */

+

+/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/

+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)

+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */

+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)

+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */

+#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)

+#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */

+#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask               */

+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)

+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */

+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)

+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */

+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)

+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */

+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)

+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */

+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)

+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */

+#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)

+#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */

+#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)

+#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask               */

+#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)

+#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask               */

+#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)

+#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                */

+

+/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/

+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)

+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */

+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */

+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)

+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */

+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */

+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)

+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */

+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */

+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)

+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */

+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */

+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)

+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */

+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */

+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)

+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */

+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */

+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)

+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */

+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */

+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)

+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */

+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */

+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)

+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */

+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */

+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)

+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */

+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */

+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)

+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */

+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */

+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)

+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */

+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */

+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)

+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */

+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */

+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)

+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */

+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */

+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)

+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */

+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */

+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)

+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */

+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */

+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)

+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */

+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */

+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)

+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */

+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */

+#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)

+#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */

+#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */

+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)

+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */

+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */

+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)

+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */

+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */

+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)

+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */

+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */

+#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)

+#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */

+#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */

+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)

+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */

+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */

+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)

+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */

+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */

+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)

+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */

+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */

+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)

+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */

+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */

+

+/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/

+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)

+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */

+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */

+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)

+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */

+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */

+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)

+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */

+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */

+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)

+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */

+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */

+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)

+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */

+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */

+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)

+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */

+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */

+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)

+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */

+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */

+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)

+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */

+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */

+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)

+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */

+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */

+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)

+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */

+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */

+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)

+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */

+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */

+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)

+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */

+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */

+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)

+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */

+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */

+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)

+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */

+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */

+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)

+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */

+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */

+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)

+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */

+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */

+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)

+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */

+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */

+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)

+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */

+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */

+#define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)

+#define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */

+#define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */

+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)

+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */

+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */

+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)

+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */

+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */

+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)

+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */

+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */

+#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)

+#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */

+#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */

+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)

+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */

+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */

+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)

+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */

+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */

+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)

+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */

+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */

+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)

+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */

+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */

+

+/********************  Bit definition forUSB_OTG_DAINT register  ********************/

+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)

+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */

+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)

+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */

+

+/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/

+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)

+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */

+

+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/

+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)

+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */

+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */

+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)

+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */

+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */

+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)

+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */

+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */

+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)

+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */

+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */

+

+/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/

+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)

+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */

+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)

+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */

+

+/********************  Bit definition for OTG register  ********************/

+

+#define USB_OTG_CHNUM_Pos                        (0U)

+#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)  /*!< 0x0000000F */

+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */

+#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */

+#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */

+#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */

+#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */

+#define USB_OTG_BCNT_Pos                         (4U)

+#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */

+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */

+

+#define USB_OTG_DPID_Pos                         (15U)

+#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)   /*!< 0x00018000 */

+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */

+#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */

+#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */

+

+#define USB_OTG_PKTSTS_Pos                       (17U)

+#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */

+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */

+#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */

+#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */

+#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */

+#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */

+

+#define USB_OTG_EPNUM_Pos                        (0U)

+#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)  /*!< 0x0000000F */

+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */

+#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */

+#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */

+#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */

+#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */

+

+#define USB_OTG_FRMNUM_Pos                       (21U)

+#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */

+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */

+#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */

+#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */

+#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */

+#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */

+

+/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/

+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)

+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/

+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)

+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */

+

+/********************  Bit definition for OTG register  ********************/

+#define USB_OTG_NPTXFSA_Pos                      (0U)

+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */

+#define USB_OTG_NPTXFD_Pos                       (16U)

+#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */

+#define USB_OTG_TX0FSA_Pos                       (0U)

+#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */

+#define USB_OTG_TX0FD_Pos                        (16U)

+#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */

+

+/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/

+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)

+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */

+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */

+

+/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/

+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)

+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */

+

+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)

+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */

+

+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)

+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/

+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)

+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */

+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */

+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)

+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */

+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */

+

+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)

+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */

+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */

+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */

+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)

+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */

+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */

+

+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)

+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */

+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */

+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)

+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */

+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */

+

+/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */

+

+/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/

+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)

+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */

+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */

+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)

+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */

+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */

+

+/********************  Bit definition forUSB_OTG_GCCFG register  ********************/

+#define USB_OTG_GCCFG_DCDET_Pos                  (0U)

+#define USB_OTG_GCCFG_DCDET_Msk                  (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */

+#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */

+#define USB_OTG_GCCFG_PDET_Pos                   (1U)

+#define USB_OTG_GCCFG_PDET_Msk                   (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */

+#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */

+#define USB_OTG_GCCFG_SDET_Pos                   (2U)

+#define USB_OTG_GCCFG_SDET_Msk                   (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */

+#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */

+#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)

+#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */

+#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */

+#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)

+#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */

+#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */

+#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)

+#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */

+#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */

+#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)

+#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */

+#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/

+#define USB_OTG_GCCFG_PDEN_Pos                   (19U)

+#define USB_OTG_GCCFG_PDEN_Msk                   (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */

+#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/

+#define USB_OTG_GCCFG_SDEN_Pos                   (20U)

+#define USB_OTG_GCCFG_SDEN_Msk                   (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */

+#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */

+#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)

+#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */

+#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */

+

+/********************  Bit definition forUSB_OTG_GPWRDN) register  ********************/

+#define USB_OTG_GPWRDN_ADPMEN_Pos                (0U)

+#define USB_OTG_GPWRDN_ADPMEN_Msk                (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */

+#define USB_OTG_GPWRDN_ADPMEN                    USB_OTG_GPWRDN_ADPMEN_Msk     /*!< ADP module enable */

+#define USB_OTG_GPWRDN_ADPIF_Pos                 (23U)

+#define USB_OTG_GPWRDN_ADPIF_Msk                 (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */

+#define USB_OTG_GPWRDN_ADPIF                     USB_OTG_GPWRDN_ADPIF_Msk      /*!< ADP Interrupt flag */

+

+/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/

+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)

+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */

+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)

+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */

+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */

+

+/********************  Bit definition forUSB_OTG_CID register  ********************/

+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)

+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */

+

+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/

+#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)

+#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */

+#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */

+#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)

+#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */

+#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */

+#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)

+#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */

+#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */

+#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)

+#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */

+#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */

+#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)

+#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */

+#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */

+#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)

+#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */

+#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */

+#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)

+#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */

+#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */

+#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)

+#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */

+#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */

+#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)

+#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */

+#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */

+#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)

+#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */

+#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */

+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)

+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */

+#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */

+#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)

+#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */

+#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */

+#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)

+#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */

+#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */

+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)

+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */

+#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */

+#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)

+#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */

+#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */

+

+/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/

+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)

+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */

+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)

+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */

+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)

+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */

+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)

+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */

+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)

+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */

+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)

+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */

+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)

+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */

+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)

+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */

+

+/********************  Bit definition forUSB_OTG_HPRT register  ********************/

+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)

+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */

+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */

+#define USB_OTG_HPRT_PCDET_Pos                   (1U)

+#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */

+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */

+#define USB_OTG_HPRT_PENA_Pos                    (2U)

+#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */

+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */

+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)

+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */

+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */

+#define USB_OTG_HPRT_POCA_Pos                    (4U)

+#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */

+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */

+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)

+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */

+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */

+#define USB_OTG_HPRT_PRES_Pos                    (6U)

+#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */

+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume   */

+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)

+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */

+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend  */

+#define USB_OTG_HPRT_PRST_Pos                    (8U)

+#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */

+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset    */

+

+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)

+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */

+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */

+#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */

+#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */

+#define USB_OTG_HPRT_PPWR_Pos                    (12U)

+#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */

+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */

+

+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)

+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */

+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */

+#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */

+#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */

+#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */

+#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */

+

+#define USB_OTG_HPRT_PSPD_Pos                    (17U)

+#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */

+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */

+#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */

+#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */

+

+/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/

+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)

+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)

+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)

+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */

+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)

+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */

+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)

+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */

+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)

+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */

+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)

+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)

+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)

+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)

+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */

+

+/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/

+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)

+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */

+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)

+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/

+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)

+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */

+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)

+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */

+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */

+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)

+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */

+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */

+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)

+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */

+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */

+

+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)

+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */

+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */

+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)

+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */

+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */

+

+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)

+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */

+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */

+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */

+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */

+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */

+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */

+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)

+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */

+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */

+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)

+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */

+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */

+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)

+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */

+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)

+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */

+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)

+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */

+

+/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/

+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)

+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */

+

+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)

+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */

+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */

+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */

+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */

+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */

+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */

+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)

+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */

+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */

+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)

+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */

+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */

+

+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)

+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */

+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */

+

+#define USB_OTG_HCCHAR_MC_Pos                    (20U)

+#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */

+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */

+#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */

+#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */

+

+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)

+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */

+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */

+#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */

+#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */

+#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */

+#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */

+#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */

+#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */

+#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */

+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)

+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */

+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)

+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */

+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)

+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */

+

+/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/

+

+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)

+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */

+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */

+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */

+

+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)

+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */

+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */

+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */

+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */

+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */

+

+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)

+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */

+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */

+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */

+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */

+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)

+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */

+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */

+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)

+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */

+

+/********************  Bit definition forUSB_OTG_HCINT register  ********************/

+#define USB_OTG_HCINT_XFRC_Pos                   (0U)

+#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */

+#define USB_OTG_HCINT_CHH_Pos                    (1U)

+#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */

+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)

+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */

+#define USB_OTG_HCINT_STALL_Pos                  (3U)

+#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */

+#define USB_OTG_HCINT_NAK_Pos                    (4U)

+#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */

+#define USB_OTG_HCINT_ACK_Pos                    (5U)

+#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */

+#define USB_OTG_HCINT_NYET_Pos                   (6U)

+#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */

+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */

+#define USB_OTG_HCINT_TXERR_Pos                  (7U)

+#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */

+#define USB_OTG_HCINT_BBERR_Pos                  (8U)

+#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */

+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)

+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */

+#define USB_OTG_HCINT_DTERR_Pos                  (10U)

+#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */

+

+/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/

+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)

+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */

+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)

+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */

+#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)

+#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */

+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)

+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */

+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)

+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */

+#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)

+#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */

+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)

+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */

+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)

+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */

+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */

+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)

+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */

+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)

+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */

+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)

+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */

+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */

+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)

+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */

+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */

+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)

+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */

+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */

+

+/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/

+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)

+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */

+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)

+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */

+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)

+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */

+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)

+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */

+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)

+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */

+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)

+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */

+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)

+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */

+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */

+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)

+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */

+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)

+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */

+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)

+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */

+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)

+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */

+

+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/

+

+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)

+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */

+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)

+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */

+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)

+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */

+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */

+/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/

+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)

+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */

+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)

+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */

+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)

+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */

+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)

+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */

+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */

+#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */

+#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/

+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)

+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */

+

+/********************  Bit definition forUSB_OTG_HCDMA register  ********************/

+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)

+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */

+

+/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/

+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)

+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */

+

+/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/

+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)

+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */

+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)

+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/

+

+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)

+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */

+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)

+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */

+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */

+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)

+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */

+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */

+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)

+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */

+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)

+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */

+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */

+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)

+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */

+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */

+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)

+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */

+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */

+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)

+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */

+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */

+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)

+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */

+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */

+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)

+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */

+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)

+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */

+

+/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/

+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)

+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */

+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)

+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */

+#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)

+#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */

+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)

+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */

+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)

+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */

+#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)

+#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< OUT Status Phase Received interrupt */

+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)

+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */

+#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)

+#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */

+#define USB_OTG_DOEPINT_BERR_Pos                 (12U)

+#define USB_OTG_DOEPINT_BERR_Msk                 (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPINT_BERR                      USB_OTG_DOEPINT_BERR_Msk   /*!< Babble error interrupt */

+#define USB_OTG_DOEPINT_NAK_Pos                  (13U)

+#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */

+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)

+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */

+#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)

+#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */

+#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */

+

+/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/

+

+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)

+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */

+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)

+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */

+

+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)

+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */

+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */

+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */

+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition for PCGCCTL register  ********************/

+#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)

+#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */

+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */

+#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)

+#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */

+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */

+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)

+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */

+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/** @addtogroup Exported_macros

+  * @{

+  */

+

+/******************************* ADC Instances ********************************/

+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \

+                                       ((INSTANCE) == ADC2) || \

+                                       ((INSTANCE) == ADC3))

+

+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)

+

+#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) ||\

+                                          ((INSTANCE) == ADC3_COMMON))

+

+/******************************** COMP Instances ******************************/

+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \

+                                       ((INSTANCE) == COMP2))

+

+#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)

+/******************** COMP Instances with window mode capability **************/

+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)

+

+

+/******************************* CRC Instances ********************************/

+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

+

+/******************************* DAC Instances ********************************/

+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)

+/******************************* DCMI Instances *******************************/

+#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)

+

+/******************************* DELAYBLOCK Instances *******************************/

+#define IS_DLYB_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DLYB_SDMMC1) || \

+                                         ((INSTANCE) == DLYB_SDMMC2) || \

+                                         ((INSTANCE) == DLYB_QUADSPI))

+/****************************** DFSDM Instances *******************************/

+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \

+                                               ((INSTANCE) == DFSDM1_Filter1) || \

+                                               ((INSTANCE) == DFSDM1_Filter2) || \

+                                               ((INSTANCE) == DFSDM1_Filter3))

+

+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \

+                                                 ((INSTANCE) == DFSDM1_Channel1) || \

+                                                 ((INSTANCE) == DFSDM1_Channel2) || \

+                                                 ((INSTANCE) == DFSDM1_Channel3) || \

+                                                 ((INSTANCE) == DFSDM1_Channel4) || \

+                                                 ((INSTANCE) == DFSDM1_Channel5) || \

+                                                 ((INSTANCE) == DFSDM1_Channel6) || \

+                                                 ((INSTANCE) == DFSDM1_Channel7))

+/****************************** RAMECC Instances ******************************/

+#define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC1_Monitor1)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor2)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor3)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor4)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor5)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor1)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor2)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor3)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor4)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor5)   || \

+                                                  ((INSTANCE) == RAMECC3_Monitor1)   || \

+                                                  ((INSTANCE) == RAMECC3_Monitor2))

+

+/******************************** DMA Instances *******************************/

+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \

+                                       ((INSTANCE) == DMA1_Stream1)   || \

+                                       ((INSTANCE) == DMA1_Stream2)   || \

+                                       ((INSTANCE) == DMA1_Stream3)   || \

+                                       ((INSTANCE) == DMA1_Stream4)   || \

+                                       ((INSTANCE) == DMA1_Stream5)   || \

+                                       ((INSTANCE) == DMA1_Stream6)   || \

+                                       ((INSTANCE) == DMA1_Stream7)   || \

+                                       ((INSTANCE) == DMA2_Stream0)   || \

+                                       ((INSTANCE) == DMA2_Stream1)   || \

+                                       ((INSTANCE) == DMA2_Stream2)   || \

+                                       ((INSTANCE) == DMA2_Stream3)   || \

+                                       ((INSTANCE) == DMA2_Stream4)   || \

+                                       ((INSTANCE) == DMA2_Stream5)   || \

+                                       ((INSTANCE) == DMA2_Stream6)   || \

+                                       ((INSTANCE) == DMA2_Stream7)   || \

+                                       ((INSTANCE) == BDMA_Channel0) || \

+                                       ((INSTANCE) == BDMA_Channel1) || \

+                                       ((INSTANCE) == BDMA_Channel2) || \

+                                       ((INSTANCE) == BDMA_Channel3) || \

+                                       ((INSTANCE) == BDMA_Channel4) || \

+                                       ((INSTANCE) == BDMA_Channel5) || \

+                                       ((INSTANCE) == BDMA_Channel6) || \

+                                       ((INSTANCE) == BDMA_Channel7))

+

+/****************************** BDMA CHANNEL Instances ***************************/

+#define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \

+                                            ((INSTANCE) == BDMA_Channel1) || \

+                                            ((INSTANCE) == BDMA_Channel2) || \

+                                            ((INSTANCE) == BDMA_Channel3) || \

+                                            ((INSTANCE) == BDMA_Channel4) || \

+                                            ((INSTANCE) == BDMA_Channel5) || \

+                                            ((INSTANCE) == BDMA_Channel6) || \

+                                            ((INSTANCE) == BDMA_Channel7))

+

+/****************************** DMA DMAMUX ALL Instances ***************************/

+#define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)    || \

+                                               ((INSTANCE) == DMA1_Stream1)    || \

+                                               ((INSTANCE) == DMA1_Stream2)    || \

+                                               ((INSTANCE) == DMA1_Stream3)    || \

+                                               ((INSTANCE) == DMA1_Stream4)    || \

+                                               ((INSTANCE) == DMA1_Stream5)    || \

+                                               ((INSTANCE) == DMA1_Stream6)    || \

+                                               ((INSTANCE) == DMA1_Stream7)    || \

+                                               ((INSTANCE) == DMA2_Stream0)    || \

+                                               ((INSTANCE) == DMA2_Stream1)    || \

+                                               ((INSTANCE) == DMA2_Stream2)    || \

+                                               ((INSTANCE) == DMA2_Stream3)    || \

+                                               ((INSTANCE) == DMA2_Stream4)    || \

+                                               ((INSTANCE) == DMA2_Stream5)    || \

+                                               ((INSTANCE) == DMA2_Stream6)    || \

+                                               ((INSTANCE) == DMA2_Stream7)    || \

+                                               ((INSTANCE) == BDMA_Channel0)   || \

+                                               ((INSTANCE) == BDMA_Channel1)   || \

+                                               ((INSTANCE) == BDMA_Channel2)   || \

+                                               ((INSTANCE) == BDMA_Channel3)   || \

+                                               ((INSTANCE) == BDMA_Channel4)   || \

+                                               ((INSTANCE) == BDMA_Channel5)   || \

+                                               ((INSTANCE) == BDMA_Channel6)   || \

+                                               ((INSTANCE) == BDMA_Channel7))

+

+/****************************** BDMA DMAMUX Instances ***************************/

+#define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == BDMA_Channel0) || \

+                                                    ((INSTANCE) == BDMA_Channel1) || \

+                                                    ((INSTANCE) == BDMA_Channel2) || \

+                                                    ((INSTANCE) == BDMA_Channel3) || \

+                                                    ((INSTANCE) == BDMA_Channel4) || \

+                                                    ((INSTANCE) == BDMA_Channel5) || \

+                                                    ((INSTANCE) == BDMA_Channel6) || \

+                                                    ((INSTANCE) == BDMA_Channel7))

+

+/****************************** DMA STREAM Instances ***************************/

+#define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \

+                                          ((INSTANCE) == DMA1_Stream1)   || \

+                                          ((INSTANCE) == DMA1_Stream2)   || \

+                                          ((INSTANCE) == DMA1_Stream3)   || \

+                                          ((INSTANCE) == DMA1_Stream4)   || \

+                                          ((INSTANCE) == DMA1_Stream5)   || \

+                                          ((INSTANCE) == DMA1_Stream6)   || \

+                                          ((INSTANCE) == DMA1_Stream7)   || \

+                                          ((INSTANCE) == DMA2_Stream0)   || \

+                                          ((INSTANCE) == DMA2_Stream1)   || \

+                                          ((INSTANCE) == DMA2_Stream2)   || \

+                                          ((INSTANCE) == DMA2_Stream3)   || \

+                                          ((INSTANCE) == DMA2_Stream4)   || \

+                                          ((INSTANCE) == DMA2_Stream5)   || \

+                                          ((INSTANCE) == DMA2_Stream6)   || \

+                                          ((INSTANCE) == DMA2_Stream7))

+

+/****************************** DMA DMAMUX Instances ***************************/

+#define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)   || \

+                                                  ((INSTANCE) == DMA1_Stream1)   || \

+                                                  ((INSTANCE) == DMA1_Stream2)   || \

+                                                  ((INSTANCE) == DMA1_Stream3)   || \

+                                                  ((INSTANCE) == DMA1_Stream4)   || \

+                                                  ((INSTANCE) == DMA1_Stream5)   || \

+                                                  ((INSTANCE) == DMA1_Stream6)   || \

+                                                  ((INSTANCE) == DMA1_Stream7)   || \

+                                                  ((INSTANCE) == DMA2_Stream0)   || \

+                                                  ((INSTANCE) == DMA2_Stream1)   || \

+                                                  ((INSTANCE) == DMA2_Stream2)   || \

+                                                  ((INSTANCE) == DMA2_Stream3)   || \

+                                                  ((INSTANCE) == DMA2_Stream4)   || \

+                                                  ((INSTANCE) == DMA2_Stream5)   || \

+                                                  ((INSTANCE) == DMA2_Stream6)   || \

+                                                  ((INSTANCE) == DMA2_Stream7))

+

+/******************************** DMA Request Generator Instances **************/

+#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator1) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator2) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator3) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator4) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator5) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator6) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator7) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator0) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator1) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator2) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator3) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator4) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator5) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator6) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator7))

+

+/******************************* DMA2D Instances *******************************/

+#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)

+

+/******************************** MDMA Request Generator Instances **************/

+#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0)  || \

+                                               ((INSTANCE) == MDMA_Channel1)  || \

+                                               ((INSTANCE) == MDMA_Channel2)  || \

+                                               ((INSTANCE) == MDMA_Channel3)  || \

+                                               ((INSTANCE) == MDMA_Channel4)  || \

+                                               ((INSTANCE) == MDMA_Channel5)  || \

+                                               ((INSTANCE) == MDMA_Channel6)  || \

+                                               ((INSTANCE) == MDMA_Channel7)  || \

+                                               ((INSTANCE) == MDMA_Channel8)  || \

+                                               ((INSTANCE) == MDMA_Channel9)  || \

+                                               ((INSTANCE) == MDMA_Channel10) || \

+                                               ((INSTANCE) == MDMA_Channel11) || \

+                                               ((INSTANCE) == MDMA_Channel12) || \

+                                               ((INSTANCE) == MDMA_Channel13) || \

+                                               ((INSTANCE) == MDMA_Channel14) || \

+                                               ((INSTANCE) == MDMA_Channel15))

+

+/******************************* QUADSPI Instances *******************************/

+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)

+

+/******************************* FDCAN Instances ******************************/

+#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \

+                                             ((__INSTANCE__) == FDCAN2))

+

+#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)

+

+/******************************* GPIO Instances *******************************/

+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \

+                                        ((INSTANCE) == GPIOB) || \

+                                        ((INSTANCE) == GPIOC) || \

+                                        ((INSTANCE) == GPIOD) || \

+                                        ((INSTANCE) == GPIOE) || \

+                                        ((INSTANCE) == GPIOF) || \

+                                        ((INSTANCE) == GPIOG) || \

+                                        ((INSTANCE) == GPIOH) || \

+                                        ((INSTANCE) == GPIOI) || \

+                                        ((INSTANCE) == GPIOJ) || \

+                                        ((INSTANCE) == GPIOK))

+

+/******************************* GPIO AF Instances ****************************/

+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)

+

+/**************************** GPIO Lock Instances *****************************/

+/* On H7, all GPIO Bank support the Lock mechanism */

+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)

+

+/******************************** HSEM Instances *******************************/

+#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)

+/********************  Bit definition for HSEM_CR register  *****************/

+#define HSEM_CPU1_COREID    (0x00000003U) /* Semaphore Core CM7 ID */

+#define HSEM_CPU2_COREID    (0x00000001U) /* Semaphore Core CM4 ID */

+#define HSEM_CR_COREID_CPU1      (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)

+#define HSEM_CR_COREID_CPU2      (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos)

+#if defined(CORE_CM4)

+#define HSEM_CR_COREID_CURRENT   (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos)

+#else  /* CORE_CM7 */

+#define HSEM_CR_COREID_CURRENT   (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)

+#endif /* CORE_CM4 */

+

+#define HSEM_SEMID_MIN     (0U)       /* HSEM ID Min*/

+#define HSEM_SEMID_MAX     (31U)      /* HSEM ID Max */

+

+#define HSEM_PROCESSID_MIN (0U)       /* HSEM Process ID Min */

+#define HSEM_PROCESSID_MAX (255U)     /* HSEM Process ID Max */

+

+#define HSEM_CLEAR_KEY_MIN (0U)       /* HSEM clear Key Min value */

+#define HSEM_CLEAR_KEY_MAX (0xFFFFU)  /* HSEM clear Key Max value */

+

+/******************************** I2C Instances *******************************/

+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

+                                       ((INSTANCE) == I2C2) || \

+                                       ((INSTANCE) == I2C3) || \

+                                       ((INSTANCE) == I2C4))

+/************** I2C Instances : wakeup capability from stop modes *************/

+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)

+

+/****************************** SMBUS Instances *******************************/

+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

+                                         ((INSTANCE) == I2C2) || \

+                                         ((INSTANCE) == I2C3) || \

+                                         ((INSTANCE) == I2C4))

+/******************************** I2S Instances *******************************/

+#define IS_I2S_ALL_INSTANCE(INSTANCE)   (((INSTANCE) == SPI1) || \

+                                         ((INSTANCE) == SPI2) || \

+                                         ((INSTANCE) == SPI3))

+

+/****************************** LTDC Instances ********************************/

+#define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)

+

+/******************************* RNG Instances ********************************/

+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)

+

+/****************************** RTC Instances *********************************/

+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)

+

+/****************************** SDMMC Instances *********************************/

+#define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \

+                                           ((_INSTANCE_) == SDMMC2))

+

+/******************************** SMBUS Instances *****************************/

+#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)

+

+/******************************** SPI Instances *******************************/

+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \

+                                       ((INSTANCE) == SPI2) || \

+                                       ((INSTANCE) == SPI3) || \

+                                       ((INSTANCE) == SPI4) || \

+                                       ((INSTANCE) == SPI5) || \

+                                       ((INSTANCE) == SPI6))

+

+#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \

+                                           ((INSTANCE) == SPI2) || \

+                                           ((INSTANCE) == SPI3))

+

+/******************************** SWPMI Instances *****************************/

+#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)

+

+/****************** LPTIM Instances : All supported instances *****************/

+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \

+                                         ((INSTANCE) == LPTIM2) || \

+                                         ((INSTANCE) == LPTIM3) || \

+                                         ((INSTANCE) == LPTIM4) || \

+                                         ((INSTANCE) == LPTIM5))

+

+/****************** LPTIM Instances : supporting encoder interface **************/

+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \

+                                                           ((INSTANCE) == LPTIM2))

+

+/****************** TIM Instances : All supported instances *******************/

+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM6)   || \

+                                         ((INSTANCE) == TIM7)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM13)  || \

+                                         ((INSTANCE) == TIM14)  || \

+                                         ((INSTANCE) == TIM15)  || \

+                                         ((INSTANCE) == TIM16)  || \

+                                         ((INSTANCE) == TIM17))

+

+/************* TIM Instances : at least 1 capture/compare channel *************/

+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM13)  || \

+                                         ((INSTANCE) == TIM14)  || \

+                                         ((INSTANCE) == TIM15)  || \

+                                         ((INSTANCE) == TIM16)  || \

+                                         ((INSTANCE) == TIM17))

+

+/************ TIM Instances : at least 2 capture/compare channels *************/

+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM15))

+

+/************ TIM Instances : at least 3 capture/compare channels *************/

+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8))

+

+/************ TIM Instances : at least 4 capture/compare channels *************/

+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8))

+

+/************ TIM Instances : at least 5 capture/compare channels *************/

+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM8))

+/************ TIM Instances : at least 6 capture/compare channels *************/

+#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM8))

+

+/******************** TIM Instances : Advanced-control timers *****************/

+#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \

+                                                ((__INSTANCE__) == TIM8))

+

+/******************** TIM Instances : Advanced-control timers *****************/

+

+/******************* TIM Instances : Timer input XOR function *****************/

+#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : DMA requests generation (UDE) *************/

+#define IS_TIM_DMA_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM6)   || \

+                                           ((INSTANCE) == TIM7)   || \

+                                           ((INSTANCE) == TIM8)   || \

+                                           ((INSTANCE) == TIM15)  || \

+                                           ((INSTANCE) == TIM16)  || \

+                                           ((INSTANCE) == TIM17))

+

+/************ TIM Instances : DMA requests generation (CCxDE) *****************/

+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15)  || \

+                                            ((INSTANCE) == TIM16)  || \

+                                            ((INSTANCE) == TIM17))

+

+/************ TIM Instances : DMA requests generation (COMDE) *****************/

+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15))

+

+/******************** TIM Instances : DMA burst feature ***********************/

+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8))

+

+/*************** TIM Instances : external trigger reamp input available *******/

+#define IS_TIM_ETR_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : remapping capability **********************/

+#define IS_TIM_REMAP_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \

+                                          ((INSTANCE) == TIM2)  || \

+                                          ((INSTANCE) == TIM3)  || \

+                                          ((INSTANCE) == TIM5)  || \

+                                          ((INSTANCE) == TIM8)  || \

+                                          ((INSTANCE) == TIM16) || \

+                                          ((INSTANCE) == TIM17))

+

+/*************** TIM Instances : external trigger reamp input available *******/

+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                              ((INSTANCE) == TIM2)   || \

+                                              ((INSTANCE) == TIM3)   || \

+                                              ((INSTANCE) == TIM5)   || \

+                                              ((INSTANCE) == TIM8))

+

+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/

+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM6)   || \

+                                            ((INSTANCE) == TIM7)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15))

+

+/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/

+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM8)   || \

+                                           ((INSTANCE) == TIM12))

+

+/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/

+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM8))

+

+/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/

+#define IS_TIM_TISEL_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)   || \

+                                          ((INSTANCE) == TIM2)   || \

+                                          ((INSTANCE) == TIM3)   || \

+                                          ((INSTANCE) == TIM4)   || \

+                                          ((INSTANCE) == TIM5)   || \

+                                          ((INSTANCE) == TIM8)   || \

+                                          ((INSTANCE) == TIM15)  || \

+                                          ((INSTANCE) == TIM16)  || \

+                                          ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting commutation event *************/

+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \

+                                                     ((INSTANCE) == TIM8)    || \

+                                                     ((INSTANCE) == TIM15)   || \

+                                                     ((INSTANCE) == TIM16)   || \

+                                                     ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting encoder interface **************/

+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1)  || \

+                                                      ((__INSTANCE__) == TIM2)      || \

+                                                      ((__INSTANCE__) == TIM3)      || \

+                                                      ((__INSTANCE__) == TIM4)      || \

+                                                      ((__INSTANCE__) == TIM5)      || \

+                                                      ((__INSTANCE__) == TIM8))

+

+/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/

+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                                       ((INSTANCE) == TIM8))

+/******************* TIM Instances : output(s) available **********************/

+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \

+    ((((INSTANCE) == TIM1) &&                  \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4) ||          \

+      ((CHANNEL) == TIM_CHANNEL_5) ||          \

+      ((CHANNEL) == TIM_CHANNEL_6)))           \

+     ||                                        \

+     (((INSTANCE) == TIM2) &&                  \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM3) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1)||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM4) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM5) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM8) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4) ||          \

+      ((CHANNEL) == TIM_CHANNEL_5) ||          \

+      ((CHANNEL) == TIM_CHANNEL_6)))           \

+  ||                                           \

+     (((INSTANCE) == TIM12) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2)))           \

+  ||                                           \

+     (((INSTANCE) == TIM13) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM14) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM15) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+     ((CHANNEL) == TIM_CHANNEL_2)))            \

+  ||                                           \

+     (((INSTANCE) == TIM16) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM17) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1))))

+

+/****************** TIM Instances : supporting the break function *************/

+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\

+      (((INSTANCE) == TIM1)    || \

+      ((INSTANCE) == TIM8)     || \

+       ((INSTANCE) == TIM15)   || \

+       ((INSTANCE) == TIM16)   || \

+       ((INSTANCE) == TIM17))

+

+/************** TIM Instances : supporting Break source selection *************/

+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \

+                                               ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting complementary output(s) ********/

+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \

+   ((((INSTANCE) == TIM1) &&                    \

+     (((CHANNEL) == TIM_CHANNEL_1) ||           \

+      ((CHANNEL) == TIM_CHANNEL_2) ||           \

+      ((CHANNEL) == TIM_CHANNEL_3)))            \

+ ||                                             \

+      (((INSTANCE) == TIM8) &&                  \

+      (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||           \

+      ((CHANNEL) == TIM_CHANNEL_3)))            \

+    ||                                          \

+    (((INSTANCE) == TIM15) &&                   \

+      ((CHANNEL) == TIM_CHANNEL_1))             \

+    ||                                          \

+    (((INSTANCE) == TIM16) &&                   \

+     ((CHANNEL) == TIM_CHANNEL_1))              \

+    ||                                          \

+    (((INSTANCE) == TIM17) &&                   \

+     ((CHANNEL) == TIM_CHANNEL_1)))

+

+/****************** TIM Instances : supporting counting mode selection ********/

+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting repetition counter *************/

+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15)   || \

+   ((INSTANCE) == TIM16)   || \

+   ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting synchronization ****************/

+#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\

+    (((__INSTANCE__) == TIM1)    || \

+     ((__INSTANCE__) == TIM2)    || \

+     ((__INSTANCE__) == TIM3)    || \

+     ((__INSTANCE__) == TIM4)    || \

+     ((__INSTANCE__) == TIM5)    || \

+     ((__INSTANCE__) == TIM6)    || \

+     ((__INSTANCE__) == TIM8)    || \

+     ((__INSTANCE__) == TIM12)   || \

+     ((__INSTANCE__) == TIM15))

+

+/****************** TIM Instances : supporting clock division *****************/

+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15)   || \

+   ((INSTANCE) == TIM16)   || \

+   ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting external clock mode 1 for ETRF input */

+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting external clock mode 2 **********/

+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\

+ (((INSTANCE) == TIM1)     || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/

+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/

+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : supporting OCxREF clear *******************/

+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3))

+

+/****************** TIM Instances : TIM_32B_COUNTER ***************************/

+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM5))

+

+/****************** TIM Instances : TIM_BKIN2 ***************************/

+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting Hall sensor interface **********/

+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)  || \

+                                                             ((__INSTANCE__) == TIM2)  || \

+                                                             ((__INSTANCE__) == TIM3)  || \

+                                                             ((__INSTANCE__) == TIM4)  || \

+                                                             ((__INSTANCE__) == TIM5)  || \

+                                                             ((__INSTANCE__) == TIM15) || \

+                                                             ((__INSTANCE__) == TIM8))

+

+/****************************** HRTIM Instances *******************************/

+#define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))

+

+/******************** USART Instances : Synchronous mode **********************/

+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                     ((INSTANCE) == USART2) || \

+                                     ((INSTANCE) == USART3) || \

+                                     ((INSTANCE) == USART6))

+

+/******************** USART Instances : SPI slave mode ************************/

+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                              ((INSTANCE) == USART2) || \

+                                              ((INSTANCE) == USART3) || \

+                                              ((INSTANCE) == USART6))

+

+/******************** UART Instances : Asynchronous mode **********************/

+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                    ((INSTANCE) == USART2) || \

+                                    ((INSTANCE) == USART3) || \

+                                    ((INSTANCE) == UART4)  || \

+                                    ((INSTANCE) == UART5)  || \

+                                    ((INSTANCE) == USART6) || \

+                                    ((INSTANCE) == UART7)  || \

+                                    ((INSTANCE) == UART8))

+

+/******************** UART Instances : FIFO mode.******************************/

+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                         ((INSTANCE) == USART2) || \

+                                         ((INSTANCE) == USART3) || \

+                                         ((INSTANCE) == UART4)  || \

+                                         ((INSTANCE) == UART5)  || \

+                                         ((INSTANCE) == USART6) || \

+                                         ((INSTANCE) == UART7)  || \

+                                         ((INSTANCE) == UART8))

+

+/****************** UART Instances : Auto Baud Rate detection *****************/

+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                            ((INSTANCE) == USART2) || \

+                                                            ((INSTANCE) == USART3) || \

+                                                            ((INSTANCE) == UART4)  || \

+                                                            ((INSTANCE) == UART5)  || \

+                                                            ((INSTANCE) == USART6) || \

+                                                            ((INSTANCE) == UART7)  || \

+                                                            ((INSTANCE) == UART8))

+

+/*********************** UART Instances : Driver Enable ***********************/

+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                  ((INSTANCE) == USART2) || \

+                                                  ((INSTANCE) == USART3) || \

+                                                  ((INSTANCE) == UART4)  || \

+                                                  ((INSTANCE) == UART5)  || \

+                                                  ((INSTANCE) == USART6) || \

+                                                  ((INSTANCE) == UART7)  || \

+                                                  ((INSTANCE) == UART8)  || \

+                                                  ((INSTANCE) == LPUART1))

+

+/********************* UART Instances : Half-Duplex mode **********************/

+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                               ((INSTANCE) == USART2) || \

+                                               ((INSTANCE) == USART3) || \

+                                               ((INSTANCE) == UART4)  || \

+                                               ((INSTANCE) == UART5)  || \

+                                               ((INSTANCE) == USART6) || \

+                                               ((INSTANCE) == UART7)  || \

+                                               ((INSTANCE) == UART8)  || \

+                                               ((INSTANCE) == LPUART1))

+

+/******************* UART Instances : Hardware Flow control *******************/

+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                           ((INSTANCE) == USART2) || \

+                                           ((INSTANCE) == USART3) || \

+                                           ((INSTANCE) == UART4)  || \

+                                           ((INSTANCE) == UART5)  || \

+                                           ((INSTANCE) == USART6) || \

+                                           ((INSTANCE) == UART7)  || \

+                                           ((INSTANCE) == UART8)  || \

+                                           ((INSTANCE) == LPUART1))

+

+/************************* UART Instances : LIN mode **************************/

+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                        ((INSTANCE) == USART2) || \

+                                        ((INSTANCE) == USART3) || \

+                                        ((INSTANCE) == UART4)  || \

+                                        ((INSTANCE) == UART5)  || \

+                                        ((INSTANCE) == USART6) || \

+                                        ((INSTANCE) == UART7)  || \

+                                        ((INSTANCE) == UART8))

+

+/****************** UART Instances : Wake-up from Stop mode *******************/

+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                    ((INSTANCE) == USART2) || \

+                                                    ((INSTANCE) == USART3) || \

+                                                    ((INSTANCE) == UART4)  || \

+                                                    ((INSTANCE) == UART5)  || \

+                                                    ((INSTANCE) == USART6) || \

+                                                    ((INSTANCE) == UART7)  || \

+                                                    ((INSTANCE) == UART8)  || \

+                                                    ((INSTANCE) == LPUART1))

+

+/************************* UART Instances : IRDA mode *************************/

+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                    ((INSTANCE) == USART2) || \

+                                    ((INSTANCE) == USART3) || \

+                                    ((INSTANCE) == UART4)  || \

+                                    ((INSTANCE) == UART5)  || \

+                                    ((INSTANCE) == USART6) || \

+                                    ((INSTANCE) == UART7)  || \

+                                    ((INSTANCE) == UART8))

+

+/********************* USART Instances : Smard card mode **********************/

+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                         ((INSTANCE) == USART2) || \

+                                         ((INSTANCE) == USART3) || \

+                                         ((INSTANCE) == USART6))

+

+/****************************** LPUART Instance *******************************/

+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)

+

+/****************************** IWDG Instances ********************************/

+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2))

+/****************************** USB Instances ********************************/

+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)

+

+/****************************** WWDG Instances ********************************/

+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == WWDG1) || \

+                                         ((INSTANCE) == WWDG2))

+/****************************** MDIOS Instances ********************************/

+#define IS_MDIOS_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == MDIOS)

+

+/****************************** CEC Instances *********************************/

+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)

+

+/****************************** SAI Instances ********************************/

+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \

+                    ((INSTANCE) == SAI1_Block_B) || \

+                     ((INSTANCE) == SAI2_Block_A) || \

+                     ((INSTANCE) == SAI2_Block_B) || \

+                     ((INSTANCE) == SAI3_Block_A) || \

+                     ((INSTANCE) == SAI3_Block_B) || \

+                     ((INSTANCE) == SAI4_Block_A) || \

+                     ((INSTANCE) == SAI4_Block_B))

+

+/****************************** SPDIFRX Instances ********************************/

+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)

+

+/****************************** OPAMP Instances *******************************/

+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \

+                                         ((INSTANCE) == OPAMP2))

+

+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)

+

+/*********************** USB OTG PCD Instances ********************************/

+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \

+                                        ((INSTANCE) == USB_OTG_HS))

+

+/*********************** USB OTG HCD Instances ********************************/

+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \

+                                       ((INSTANCE) == USB_OTG_HS))

+

+/******************************************************************************/

+/*  For a painless codes migration between the STM32H7xx device product       */

+/*  lines, or with STM32F7xx devices the aliases defined below are put        */

+/*   in place to overcome the differences in the interrupt handlers and IRQn  */

+/*   definitions. No need to update developed interrupt code when moving      */

+/*  across product lines within the same STM32H7 Family                       */

+/******************************************************************************/

+

+/* Aliases for __IRQn */

+#define  HASH_RNG_IRQn                  RNG_IRQn

+#define  TIM1_BRK_TIM9_IRQn             TIM1_BRK_IRQn

+#define  TIM1_UP_TIM10_IRQn             TIM1_UP_IRQn

+#define  TIM1_TRG_COM_TIM11_IRQn        TIM1_TRG_COM_IRQn

+#define  PVD_IRQn                       PVD_AVD_IRQn

+

+

+

+/* Aliases for __IRQHandler */

+#define  HASH_RNG_IRQHandler           RNG_IRQHandler

+#define TIM1_BRK_TIM9_IRQHandler       TIM1_BRK_IRQHandler

+#define TIM1_UP_TIM9_IRQHandler        TIM1_UP_IRQHandler

+#define TIM1_TRG_COM_TIM11_IRQHandler  TIM1_TRG_COM_IRQHandler

+#define PVD_IRQHandler                 PVD_AVD_IRQHandler

+

+/* Aliases for COMP __IRQHandler */

+#define COMP_IRQHandler                COMP1_IRQHandler

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif /* __cplusplus */

+

+#endif /* STM32H747xx_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h750xx.h b/bsps/arm/stm32h7/include/stm32h750xx.h
new file mode 100644
index 0000000000..95a8d5777e
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h750xx.h
@@ -0,0 +1,26574 @@
+/**

+  ******************************************************************************

+  * @file    stm32h750xx.h

+  * @author  MCD Application Team

+  * @brief   CMSIS STM32H750xx Device Peripheral Access Layer Header File.

+  *

+  *          This file contains:

+  *           - Data structures and the address mapping for all peripherals

+  *           - Peripheral's registers declarations and bits definition

+  *           - Macros to access peripheral's registers hardware

+  *

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/** @addtogroup CMSIS_Device

+  * @{

+  */

+

+/** @addtogroup stm32h750xx

+  * @{

+  */

+

+#ifndef STM32H750xx_H

+#define STM32H750xx_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif /* __cplusplus */

+

+/** @addtogroup Peripheral_interrupt_number_definition

+  * @{

+  */

+

+/**

+ * @brief STM32H7XX Interrupt Number Definition, according to the selected device

+ *        in @ref Library_configuration_section

+ */

+typedef enum

+{

+/******  Cortex-M Processor Exceptions Numbers *****************************************************************/

+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */

+  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */

+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */

+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */

+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */

+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M SV Call Interrupt                                     */

+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M Debug Monitor Interrupt                               */

+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M Pend SV Interrupt                                     */

+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M System Tick Interrupt                                 */

+/******  STM32 specific Interrupt Numbers **********************************************************************/

+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)                   */

+  PVD_AVD_IRQn                = 1,      /*!< PVD/AVD through EXTI Line detection Interrupt                     */

+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */

+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */

+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */

+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */

+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */

+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */

+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */

+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */

+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */

+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */

+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */

+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */

+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */

+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */

+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */

+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */

+  ADC_IRQn                    = 18,     /*!< ADC1 and  ADC2 global Interrupts                                  */

+  FDCAN1_IT0_IRQn             = 19,     /*!< FDCAN1 Interrupt line 0                                           */

+  FDCAN2_IT0_IRQn             = 20,     /*!< FDCAN2 Interrupt line 0                                           */

+  FDCAN1_IT1_IRQn             = 21,     /*!< FDCAN1 Interrupt line 1                                           */

+  FDCAN2_IT1_IRQn             = 22,     /*!< FDCAN2 Interrupt line 1                                           */

+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */

+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                              */

+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                             */

+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt                            */

+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */

+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */

+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */

+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */

+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */

+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */

+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */

+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */

+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */

+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */

+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */

+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */

+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */

+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */

+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */

+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */

+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */

+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */

+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */

+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */

+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */

+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */

+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */

+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */

+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */

+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */

+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */

+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */

+  DMA2_Stream0_IRQn           = 56,     /*!<   DMA2 Stream 0 global Interrupt                                  */

+  DMA2_Stream1_IRQn           = 57,     /*!<   DMA2 Stream 1 global Interrupt                                  */

+  DMA2_Stream2_IRQn           = 58,     /*!<   DMA2 Stream 2 global Interrupt                                  */

+  DMA2_Stream3_IRQn           = 59,     /*!<   DMA2 Stream 3 global Interrupt                                  */

+  DMA2_Stream4_IRQn           = 60,     /*!<   DMA2 Stream 4 global Interrupt                                  */

+  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */

+  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */

+  FDCAN_CAL_IRQn              = 63,     /*!< FDCAN Calibration unit Interrupt                                  */

+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */

+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */

+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */

+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */

+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */

+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */

+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */

+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */

+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */

+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */

+  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */

+  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */

+  HASH_RNG_IRQn               = 80,     /*!< HASH and RNG global interrupt                                     */

+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */

+  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */

+  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */

+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */

+  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */

+  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */

+  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */

+  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */

+  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */

+  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */

+  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */

+  QUADSPI_IRQn                = 92,     /*!< Quad SPI global interrupt                                         */

+  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */

+  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */

+  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */

+  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */

+  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */

+  OTG_FS_EP1_OUT_IRQn         = 98,     /*!< USB OTG HS2 global interrupt                                      */

+  OTG_FS_EP1_IN_IRQn          = 99,     /*!< USB OTG HS2 End Point 1 Out global interrupt                      */

+  OTG_FS_WKUP_IRQn            = 100,    /*!< USB OTG HS2 End Point 1 In global interrupt                       */

+  OTG_FS_IRQn                 = 101,    /*!< USB OTG HS2 Wakeup through EXTI interrupt                         */

+  DMAMUX1_OVR_IRQn            = 102,    /*!<DMAMUX1 Overrun interrupt                                          */

+  HRTIM1_Master_IRQn          = 103,    /*!< HRTIM Master Timer global Interrupts                              */

+  HRTIM1_TIMA_IRQn            = 104,    /*!< HRTIM Timer A global Interrupt                                    */

+  HRTIM1_TIMB_IRQn            = 105,    /*!< HRTIM Timer B global Interrupt                                    */

+  HRTIM1_TIMC_IRQn            = 106,    /*!< HRTIM Timer C global Interrupt                                    */

+  HRTIM1_TIMD_IRQn            = 107,    /*!< HRTIM Timer D global Interrupt                                    */

+  HRTIM1_TIME_IRQn            = 108,    /*!< HRTIM Timer E global Interrupt                                    */

+  HRTIM1_FLT_IRQn             = 109,    /*!< HRTIM Fault global Interrupt                                      */

+  DFSDM1_FLT0_IRQn            = 110,    /*!<DFSDM Filter1 Interrupt                                            */

+  DFSDM1_FLT1_IRQn            = 111,    /*!<DFSDM Filter2 Interrupt                                            */

+  DFSDM1_FLT2_IRQn            = 112,    /*!<DFSDM Filter3 Interrupt                                            */

+  DFSDM1_FLT3_IRQn            = 113,    /*!<DFSDM Filter4 Interrupt                                            */

+  SAI3_IRQn                   = 114,    /*!< SAI3 global Interrupt                                             */

+  SWPMI1_IRQn                 = 115,    /*!< Serial Wire Interface 1 global interrupt                          */

+  TIM15_IRQn                  = 116,    /*!< TIM15 global Interrupt                                            */

+  TIM16_IRQn                  = 117,    /*!< TIM16 global Interrupt                                            */

+  TIM17_IRQn                  = 118,    /*!< TIM17 global Interrupt                                            */

+  MDIOS_WKUP_IRQn             = 119,    /*!< MDIOS Wakeup  Interrupt                                           */

+  MDIOS_IRQn                  = 120,    /*!< MDIOS global Interrupt                                            */

+  JPEG_IRQn                   = 121,    /*!< JPEG global Interrupt                                             */

+  MDMA_IRQn                   = 122,    /*!< MDMA global Interrupt                                             */

+  SDMMC2_IRQn                 = 124,    /*!< SDMMC2 global Interrupt                                           */

+  HSEM1_IRQn                  = 125,    /*!< HSEM1 global Interrupt                                            */

+  ADC3_IRQn                   = 127,    /*!< ADC3 global Interrupt                                             */

+  DMAMUX2_OVR_IRQn            = 128,    /*!<DMAMUX2 Overrun interrupt                                          */

+  BDMA_Channel0_IRQn          = 129,    /*!< BDMA Channel 0 global Interrupt                                   */

+  BDMA_Channel1_IRQn          = 130,    /*!< BDMA Channel 1 global Interrupt                                   */

+  BDMA_Channel2_IRQn          = 131,    /*!< BDMA Channel 2 global Interrupt                                   */

+  BDMA_Channel3_IRQn          = 132,    /*!< BDMA Channel 3 global Interrupt                                   */

+  BDMA_Channel4_IRQn          = 133,    /*!< BDMA Channel 4 global Interrupt                                   */

+  BDMA_Channel5_IRQn          = 134,    /*!< BDMA Channel 5 global Interrupt                                   */

+  BDMA_Channel6_IRQn          = 135,    /*!< BDMA Channel 6 global Interrupt                                   */

+  BDMA_Channel7_IRQn          = 136,    /*!< BDMA Channel 7 global Interrupt                                   */

+  COMP_IRQn                   = 137 ,   /*!< COMP global Interrupt                                             */

+  LPTIM2_IRQn                 = 138,    /*!< LP TIM2 global interrupt                                          */

+  LPTIM3_IRQn                 = 139,    /*!< LP TIM3 global interrupt                                          */

+  LPTIM4_IRQn                 = 140,    /*!< LP TIM4 global interrupt                                          */

+  LPTIM5_IRQn                 = 141,    /*!< LP TIM5 global interrupt                                          */

+  LPUART1_IRQn                = 142,    /*!< LP UART1 interrupt                                                */

+  CRS_IRQn                    = 144,    /*!< Clock Recovery Global Interrupt                                   */

+  ECC_IRQn                    = 145,    /*!< ECC diagnostic Global Interrupt                                   */

+  SAI4_IRQn                   = 146,    /*!< SAI4 global interrupt                                             */

+  WAKEUP_PIN_IRQn             = 149,    /*!< Interrupt for all 6 wake-up pins                                  */

+} IRQn_Type;

+

+/**

+  * @}

+  */

+

+/** @addtogroup Configuration_section_for_CMSIS

+  * @{

+  */

+

+

+

+

+/**

+  * @brief Configuration of the Cortex-M7 Processor and Core Peripherals

+   */

+#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */

+#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */

+#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */

+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */

+#define __FPU_PRESENT             1       /*!< FPU present                                   */

+#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */

+#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */

+#include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */

+

+/**

+  * @}

+  */

+

+

+

+

+#include "system_stm32h7xx.h"

+#include <stdint.h>

+

+/** @addtogroup Peripheral_registers_structures

+  * @{

+  */

+

+/**

+  * @brief Analog to Digital Converter

+  */

+

+typedef struct

+{

+  __IO uint32_t ISR;              /*!< ADC Interrupt and Status Register,                          Address offset: 0x00 */

+  __IO uint32_t IER;              /*!< ADC Interrupt Enable Register,                              Address offset: 0x04 */

+  __IO uint32_t CR;               /*!< ADC control register,                                       Address offset: 0x08 */

+  __IO uint32_t CFGR;             /*!< ADC Configuration register,                                 Address offset: 0x0C */

+  __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                               Address offset: 0x10 */

+  __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                                 Address offset: 0x14 */

+  __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                                 Address offset: 0x18 */

+  __IO uint32_t PCSEL;            /*!< ADC pre-channel selection,                                  Address offset: 0x1C */

+  __IO uint32_t LTR1;             /*!< ADC watchdog Lower threshold register 1,                    Address offset: 0x20 */

+  __IO uint32_t HTR1;             /*!< ADC watchdog higher threshold register 1,                   Address offset: 0x24 */

+  uint32_t      RESERVED1;        /*!< Reserved, 0x028                                                                  */

+  uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                                  */

+  __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                            Address offset: 0x30 */

+  __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                            Address offset: 0x34 */

+  __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                            Address offset: 0x38 */

+  __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                            Address offset: 0x3C */

+  __IO uint32_t DR;               /*!< ADC regular data register,                                  Address offset: 0x40 */

+  uint32_t      RESERVED3;        /*!< Reserved, 0x044                                                                  */

+  uint32_t      RESERVED4;        /*!< Reserved, 0x048                                                                  */

+  __IO uint32_t JSQR;             /*!< ADC injected sequence register,                             Address offset: 0x4C */

+  uint32_t      RESERVED5[4];     /*!< Reserved, 0x050 - 0x05C                                                          */

+  __IO uint32_t OFR1;             /*!< ADC offset register 1,                                      Address offset: 0x60 */

+  __IO uint32_t OFR2;             /*!< ADC offset register 2,                                      Address offset: 0x64 */

+  __IO uint32_t OFR3;             /*!< ADC offset register 3,                                      Address offset: 0x68 */

+  __IO uint32_t OFR4;             /*!< ADC offset register 4,                                      Address offset: 0x6C */

+  uint32_t      RESERVED6[4];     /*!< Reserved, 0x070 - 0x07C                                                          */

+  __IO uint32_t JDR1;             /*!< ADC injected data register 1,                               Address offset: 0x80 */

+  __IO uint32_t JDR2;             /*!< ADC injected data register 2,                               Address offset: 0x84 */

+  __IO uint32_t JDR3;             /*!< ADC injected data register 3,                               Address offset: 0x88 */

+  __IO uint32_t JDR4;             /*!< ADC injected data register 4,                               Address offset: 0x8C */

+  uint32_t      RESERVED7[4];     /*!< Reserved, 0x090 - 0x09C                                                          */

+  __IO uint32_t AWD2CR;           /*!< ADC  Analog Watchdog 2 Configuration Register,              Address offset: 0xA0 */

+  __IO uint32_t AWD3CR;           /*!< ADC  Analog Watchdog 3 Configuration Register,              Address offset: 0xA4 */

+  uint32_t      RESERVED8;        /*!< Reserved, 0x0A8                                                                  */

+  uint32_t      RESERVED9;        /*!< Reserved, 0x0AC                                                                  */

+  __IO uint32_t LTR2;             /*!< ADC watchdog Lower threshold register 2,                    Address offset: 0xB0 */

+  __IO uint32_t HTR2;             /*!< ADC watchdog Higher threshold register 2,                   Address offset: 0xB4 */

+  __IO uint32_t LTR3;             /*!< ADC watchdog Lower threshold register 3,                    Address offset: 0xB8 */

+  __IO uint32_t HTR3;             /*!< ADC watchdog Higher threshold register 3,                   Address offset: 0xBC */

+  __IO uint32_t DIFSEL;           /*!< ADC  Differential Mode Selection Register,                  Address offset: 0xC0 */

+  __IO uint32_t CALFACT;          /*!< ADC  Calibration Factors,                                   Address offset: 0xC4 */

+  __IO uint32_t CALFACT2;         /*!< ADC  Linearity Calibration Factors,                         Address offset: 0xC8 */

+} ADC_TypeDef;

+

+

+typedef struct

+{

+__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */

+uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */

+__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */

+__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */

+__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */

+

+} ADC_Common_TypeDef;

+

+

+/**

+  * @brief VREFBUF

+  */

+

+typedef struct

+{

+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */

+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */

+} VREFBUF_TypeDef;

+

+

+/**

+  * @brief FD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */

+  __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */

+  __IO uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */

+  __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */

+  __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */

+  __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */

+  __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */

+  __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */

+  __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */

+  __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */

+  __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */

+  __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */

+  __IO uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */

+  __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */

+  __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */

+  __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */

+  __IO uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */

+  __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */

+  __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */

+  __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */

+  __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */

+  __IO uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */

+  __IO uint32_t GFC;          /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */

+  __IO uint32_t SIDFC;        /*!< FDCAN Standard ID Filter Configuration register,                 Address offset: 0x084 */

+  __IO uint32_t XIDFC;        /*!< FDCAN Extended ID Filter Configuration register,                 Address offset: 0x088 */

+  __IO uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */

+  __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x090 */

+  __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x094 */

+  __IO uint32_t NDAT1;        /*!< FDCAN New Data 1 register,                                       Address offset: 0x098 */

+  __IO uint32_t NDAT2;        /*!< FDCAN New Data 2 register,                                       Address offset: 0x09C */

+  __IO uint32_t RXF0C;        /*!< FDCAN Rx FIFO 0 Configuration register,                          Address offset: 0x0A0 */

+  __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x0A4 */

+  __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x0A8 */

+  __IO uint32_t RXBC;         /*!< FDCAN Rx Buffer Configuration register,                          Address offset: 0x0AC */

+  __IO uint32_t RXF1C;        /*!< FDCAN Rx FIFO 1 Configuration register,                          Address offset: 0x0B0 */

+  __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x0B4 */

+  __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x0B8 */

+  __IO uint32_t RXESC;        /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register,        Address offset: 0x0BC */

+  __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */

+  __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */

+  __IO uint32_t TXESC;        /*!< FDCAN Tx Buffer Element Size Configuration register,             Address offset: 0x0C8 */

+  __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0CC */

+  __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0D0 */

+  __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D4 */

+  __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D8 */

+  __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0DC */

+  __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0E0 */

+  __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */

+  __IO uint32_t RESERVED6[2]; /*!< Reserved,                                                                0x0E8 - 0x0EC */

+  __IO uint32_t TXEFC;        /*!< FDCAN Tx Event FIFO Configuration register,                      Address offset: 0x0F0 */

+  __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0F4 */

+  __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0F8 */

+  __IO uint32_t RESERVED7;    /*!< Reserved,                                                                        0x0FC */

+} FDCAN_GlobalTypeDef;

+

+/**

+  * @brief TTFD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t TTTMC;          /*!< TT Trigger Memory Configuration register,    Address offset: 0x100 */

+  __IO uint32_t TTRMC;          /*!< TT Reference Message Configuration register, Address offset: 0x104 */

+  __IO uint32_t TTOCF;          /*!< TT Operation Configuration register,         Address offset: 0x108 */

+  __IO uint32_t TTMLM;          /*!< TT Matrix Limits register,                   Address offset: 0x10C */

+  __IO uint32_t TURCF;          /*!< TUR Configuration register,                  Address offset: 0x110 */

+  __IO uint32_t TTOCN;          /*!< TT Operation Control register,               Address offset: 0x114 */

+  __IO uint32_t TTGTP;          /*!< TT Global Time Preset register,              Address offset: 0x118 */

+  __IO uint32_t TTTMK;          /*!< TT Time Mark register,                       Address offset: 0x11C */

+  __IO uint32_t TTIR;           /*!< TT Interrupt register,                       Address offset: 0x120 */

+  __IO uint32_t TTIE;           /*!< TT Interrupt Enable register,                Address offset: 0x124 */

+  __IO uint32_t TTILS;          /*!< TT Interrupt Line Select register,           Address offset: 0x128 */

+  __IO uint32_t TTOST;          /*!< TT Operation Status register,                Address offset: 0x12C */

+  __IO uint32_t TURNA;          /*!< TT TUR Numerator Actual register,            Address offset: 0x130 */

+  __IO uint32_t TTLGT;          /*!< TT Local and Global Time register,           Address offset: 0x134 */

+  __IO uint32_t TTCTC;          /*!< TT Cycle Time and Count register,            Address offset: 0x138 */

+  __IO uint32_t TTCPT;          /*!< TT Capture Time register,                    Address offset: 0x13C */

+  __IO uint32_t TTCSM;          /*!< TT Cycle Sync Mark register,                 Address offset: 0x140 */

+  __IO uint32_t RESERVED1[111]; /*!< Reserved,                                            0x144 - 0x2FC */

+  __IO uint32_t TTTS;           /*!< TT Trigger Select register,                  Address offset: 0x300 */

+} TTCAN_TypeDef;

+

+/**

+  * @brief FD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t CREL;  /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */

+  __IO uint32_t CCFG;  /*!< Calibration Configuration register,           Address offset: 0x04 */

+  __IO uint32_t CSTAT; /*!< Calibration Status register,                  Address offset: 0x08 */

+  __IO uint32_t CWD;   /*!< Calibration Watchdog register,                Address offset: 0x0C */

+  __IO uint32_t IR;    /*!< CCU Interrupt register,                       Address offset: 0x10 */

+  __IO uint32_t IE;    /*!< CCU Interrupt Enable register,                Address offset: 0x14 */

+} FDCAN_ClockCalibrationUnit_TypeDef;

+

+

+/**

+  * @brief Consumer Electronics Control

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;           /*!< CEC control register,              Address offset:0x00 */

+  __IO uint32_t CFGR;         /*!< CEC configuration register,        Address offset:0x04 */

+  __IO uint32_t TXDR;         /*!< CEC Tx data register ,             Address offset:0x08 */

+  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,              Address offset:0x0C */

+  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register, Address offset:0x10 */

+  __IO uint32_t IER;          /*!< CEC interrupt enable register,     Address offset:0x14 */

+}CEC_TypeDef;

+

+/**

+  * @brief CRC calculation unit

+  */

+

+typedef struct

+{

+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */

+  __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */

+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */

+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */

+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */

+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */

+} CRC_TypeDef;

+

+

+/**

+  * @brief Clock Recovery System

+  */

+typedef struct

+{

+__IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */

+__IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */

+__IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */

+__IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */

+} CRS_TypeDef;

+

+

+/**

+  * @brief Digital to Analog Converter

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */

+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */

+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */

+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */

+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */

+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */

+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */

+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */

+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */

+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */

+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */

+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */

+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */

+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */

+  __IO uint32_t CCR;      /*!< DAC calibration control register,                        Address offset: 0x38 */

+  __IO uint32_t MCR;      /*!< DAC mode control register,                               Address offset: 0x3C */

+  __IO uint32_t SHSR1;    /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */

+  __IO uint32_t SHSR2;    /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */

+  __IO uint32_t SHHR;     /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */

+  __IO uint32_t SHRR;     /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */

+} DAC_TypeDef;

+

+/**

+  * @brief DFSDM module registers

+  */

+typedef struct

+{

+  __IO uint32_t FLTCR1;          /*!< DFSDM control register1,                          Address offset: 0x100 */

+  __IO uint32_t FLTCR2;          /*!< DFSDM control register2,                          Address offset: 0x104 */

+  __IO uint32_t FLTISR;          /*!< DFSDM interrupt and status register,              Address offset: 0x108 */

+  __IO uint32_t FLTICR;          /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */

+  __IO uint32_t FLTJCHGR;        /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */

+  __IO uint32_t FLTFCR;          /*!< DFSDM filter control register,                    Address offset: 0x114 */

+  __IO uint32_t FLTJDATAR;       /*!< DFSDM data register for injected group,           Address offset: 0x118 */

+  __IO uint32_t FLTRDATAR;       /*!< DFSDM data register for regular group,            Address offset: 0x11C */

+  __IO uint32_t FLTAWHTR;        /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */

+  __IO uint32_t FLTAWLTR;        /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */

+  __IO uint32_t FLTAWSR;         /*!< DFSDM analog watchdog status register             Address offset: 0x128 */

+  __IO uint32_t FLTAWCFR;        /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */

+  __IO uint32_t FLTEXMAX;        /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */

+  __IO uint32_t FLTEXMIN;        /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */

+  __IO uint32_t FLTCNVTIMR;      /*!< DFSDM conversion timer,                           Address offset: 0x138 */

+} DFSDM_Filter_TypeDef;

+

+/**

+  * @brief DFSDM channel configuration registers

+  */

+typedef struct

+{

+  __IO uint32_t CHCFGR1;      /*!< DFSDM channel configuration register1,            Address offset: 0x00 */

+  __IO uint32_t CHCFGR2;      /*!< DFSDM channel configuration register2,            Address offset: 0x04 */

+  __IO uint32_t CHAWSCDR;     /*!< DFSDM channel analog watchdog and

+                                   short circuit detector register,                  Address offset: 0x08 */

+  __IO uint32_t CHWDATAR;     /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */

+  __IO uint32_t CHDATINR;     /*!< DFSDM channel data input register,                Address offset: 0x10 */

+} DFSDM_Channel_TypeDef;

+

+/**

+  * @brief Debug MCU

+  */

+typedef struct

+{

+  __IO uint32_t IDCODE;        /*!< MCU device ID code,                     Address offset: 0x00 */

+  __IO uint32_t CR;            /*!< Debug MCU configuration register,       Address offset: 0x04 */

+  uint32_t RESERVED4[11];      /*!< Reserved,                             Address offset: 0x08 */

+  __IO uint32_t APB3FZ1;     /*!< Debug MCU APB3FZ1 freeze register,    Address offset: 0x34 */

+  uint32_t RESERVED5;          /*!< Reserved,                             Address offset: 0x38 */

+  __IO uint32_t APB1LFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x3C */

+  uint32_t RESERVED6;          /*!< Reserved,                             Address offset: 0x40 */

+  __IO uint32_t APB1HFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x44 */

+  uint32_t RESERVED7;          /*!< Reserved,                             Address offset: 0x48 */

+  __IO uint32_t APB2FZ1;     /*!< Debug MCU APB2FZ1 freeze register,    Address offset: 0x4C */

+  uint32_t RESERVED8;          /*!< Reserved,                             Address offset: 0x50 */

+  __IO uint32_t APB4FZ1;     /*!< Debug MCU APB4FZ1 freeze register,    Address offset: 0x54 */

+}DBGMCU_TypeDef;

+/**

+  * @brief DCMI

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */

+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */

+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */

+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */

+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */

+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */

+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */

+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */

+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */

+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */

+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */

+} DCMI_TypeDef;

+

+/**

+  * @brief DMA Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */

+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */

+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */

+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */

+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */

+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */

+} DMA_Stream_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */

+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */

+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */

+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */

+} DMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CCR;          /*!< DMA channel x configuration register          */

+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register         */

+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register     */

+  __IO uint32_t CM0AR;        /*!< DMA channel x memory 0 address register       */

+  __IO uint32_t CM1AR;        /*!< DMA channel x memory 1 address register       */

+} BDMA_Channel_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */

+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */

+} BDMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CCR;        /*!< DMA Multiplexer Channel x Control Register   */

+}DMAMUX_Channel_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CSR;      /*!< DMA Channel Status Register     */

+  __IO uint32_t  CFR;      /*!< DMA Channel Clear Flag Register */

+}DMAMUX_ChannelStatus_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  RGCR;        /*!< DMA Request Generator x Control Register   */

+}DMAMUX_RequestGen_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  RGSR;        /*!< DMA Request Generator Status Register       */

+  __IO uint32_t  RGCFR;       /*!< DMA Request Generator Clear Flag Register   */

+}DMAMUX_RequestGenStatus_TypeDef;

+

+/**

+  * @brief MDMA Controller

+  */

+typedef struct

+{

+  __IO uint32_t  GISR0;   /*!< MDMA Global Interrupt/Status Register 0,          Address offset: 0x00 */

+}MDMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CISR;      /*!< MDMA channel x interrupt/status register,             Address offset: 0x40 */

+  __IO uint32_t  CIFCR;     /*!< MDMA channel x interrupt flag clear register,         Address offset: 0x44 */

+  __IO uint32_t  CESR;      /*!< MDMA Channel x error status register,                 Address offset: 0x48 */

+  __IO uint32_t  CCR;       /*!< MDMA channel x control register,                      Address offset: 0x4C */

+  __IO uint32_t  CTCR;      /*!< MDMA channel x Transfer Configuration register,       Address offset: 0x50 */

+  __IO uint32_t  CBNDTR;    /*!< MDMA Channel x block number of data register,         Address offset: 0x54 */

+  __IO uint32_t  CSAR;      /*!< MDMA channel x source address register,               Address offset: 0x58 */

+  __IO uint32_t  CDAR;      /*!< MDMA channel x destination address register,          Address offset: 0x5C */

+  __IO uint32_t  CBRUR;     /*!< MDMA channel x Block Repeat address Update register,  Address offset: 0x60 */

+  __IO uint32_t  CLAR;      /*!< MDMA channel x Link Address register,                 Address offset: 0x64 */

+  __IO uint32_t  CTBR;      /*!< MDMA channel x Trigger and Bus selection Register,    Address offset: 0x68 */

+  uint32_t       RESERVED0; /*!< Reserved, 0x68                                                             */

+  __IO uint32_t  CMAR;      /*!< MDMA channel x Mask address register,                 Address offset: 0x70 */

+  __IO uint32_t  CMDR;      /*!< MDMA channel x Mask Data register,                    Address offset: 0x74 */

+}MDMA_Channel_TypeDef;

+

+/**

+  * @brief DMA2D Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */

+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */

+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */

+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */

+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */

+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */

+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */

+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */

+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */

+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */

+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */

+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */

+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */

+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */

+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */

+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */

+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */

+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */

+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */

+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */

+  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */

+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */

+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */

+} DMA2D_TypeDef;

+

+

+/**

+  * @brief Ethernet MAC

+  */

+typedef struct

+{

+  __IO uint32_t MACCR;

+  __IO uint32_t MACECR;

+  __IO uint32_t MACPFR;

+  __IO uint32_t MACWTR;

+  __IO uint32_t MACHT0R;

+  __IO uint32_t MACHT1R;

+  uint32_t      RESERVED1[14];

+  __IO uint32_t MACVTR;

+  uint32_t      RESERVED2;

+  __IO uint32_t MACVHTR;

+  uint32_t      RESERVED3;

+  __IO uint32_t MACVIR;

+  __IO uint32_t MACIVIR;

+  uint32_t      RESERVED4[2];

+  __IO uint32_t MACTFCR;

+  uint32_t      RESERVED5[7];

+  __IO uint32_t MACRFCR;

+  uint32_t      RESERVED6[7];

+  __IO uint32_t MACISR;

+  __IO uint32_t MACIER;

+  __IO uint32_t MACRXTXSR;

+  uint32_t      RESERVED7;

+  __IO uint32_t MACPCSR;

+  __IO uint32_t MACRWKPFR;

+  uint32_t      RESERVED8[2];

+  __IO uint32_t MACLCSR;

+  __IO uint32_t MACLTCR;

+  __IO uint32_t MACLETR;

+  __IO uint32_t MAC1USTCR;

+  uint32_t      RESERVED9[12];

+  __IO uint32_t MACVR;

+  __IO uint32_t MACDR;

+  uint32_t      RESERVED10;

+  __IO uint32_t MACHWF0R;

+  __IO uint32_t MACHWF1R;

+  __IO uint32_t MACHWF2R;

+  uint32_t      RESERVED11[54];

+  __IO uint32_t MACMDIOAR;

+  __IO uint32_t MACMDIODR;

+  uint32_t      RESERVED12[2];

+  __IO uint32_t MACARPAR;

+  uint32_t      RESERVED13[59];

+  __IO uint32_t MACA0HR;

+  __IO uint32_t MACA0LR;

+  __IO uint32_t MACA1HR;

+  __IO uint32_t MACA1LR;

+  __IO uint32_t MACA2HR;

+  __IO uint32_t MACA2LR;

+  __IO uint32_t MACA3HR;

+  __IO uint32_t MACA3LR;

+  uint32_t      RESERVED14[248];

+  __IO uint32_t MMCCR;

+  __IO uint32_t MMCRIR;

+  __IO uint32_t MMCTIR;

+  __IO uint32_t MMCRIMR;

+  __IO uint32_t MMCTIMR;

+  uint32_t      RESERVED15[14];

+  __IO uint32_t MMCTSCGPR;

+  __IO uint32_t MMCTMCGPR;

+  uint32_t      RESERVED16[5];

+  __IO uint32_t MMCTPCGR;

+  uint32_t      RESERVED17[10];

+  __IO uint32_t MMCRCRCEPR;

+  __IO uint32_t MMCRAEPR;

+  uint32_t      RESERVED18[10];

+  __IO uint32_t MMCRUPGR;

+  uint32_t      RESERVED19[9];

+  __IO uint32_t MMCTLPIMSTR;

+  __IO uint32_t MMCTLPITCR;

+  __IO uint32_t MMCRLPIMSTR;

+  __IO uint32_t MMCRLPITCR;

+  uint32_t      RESERVED20[65];

+  __IO uint32_t MACL3L4C0R;

+  __IO uint32_t MACL4A0R;

+  uint32_t      RESERVED21[2];

+  __IO uint32_t MACL3A0R0R;

+  __IO uint32_t MACL3A1R0R;

+  __IO uint32_t MACL3A2R0R;

+  __IO uint32_t MACL3A3R0R;

+  uint32_t      RESERVED22[4];

+  __IO uint32_t MACL3L4C1R;

+  __IO uint32_t MACL4A1R;

+  uint32_t      RESERVED23[2];

+  __IO uint32_t MACL3A0R1R;

+  __IO uint32_t MACL3A1R1R;

+  __IO uint32_t MACL3A2R1R;

+  __IO uint32_t MACL3A3R1R;

+  uint32_t      RESERVED24[108];

+  __IO uint32_t MACTSCR;

+  __IO uint32_t MACSSIR;

+  __IO uint32_t MACSTSR;

+  __IO uint32_t MACSTNR;

+  __IO uint32_t MACSTSUR;

+  __IO uint32_t MACSTNUR;

+  __IO uint32_t MACTSAR;

+  uint32_t      RESERVED25;

+  __IO uint32_t MACTSSR;

+  uint32_t      RESERVED26[3];

+  __IO uint32_t MACTTSSNR;

+  __IO uint32_t MACTTSSSR;

+  uint32_t      RESERVED27[2];

+  __IO uint32_t MACACR;

+  uint32_t      RESERVED28;

+  __IO uint32_t MACATSNR;

+  __IO uint32_t MACATSSR;

+  __IO uint32_t MACTSIACR;

+  __IO uint32_t MACTSEACR;

+  __IO uint32_t MACTSICNR;

+  __IO uint32_t MACTSECNR;

+  uint32_t      RESERVED29[4];

+  __IO uint32_t MACPPSCR;

+  uint32_t      RESERVED30[3];

+  __IO uint32_t MACPPSTTSR;

+  __IO uint32_t MACPPSTTNR;

+  __IO uint32_t MACPPSIR;

+  __IO uint32_t MACPPSWR;

+  uint32_t      RESERVED31[12];

+  __IO uint32_t MACPOCR;

+  __IO uint32_t MACSPI0R;

+  __IO uint32_t MACSPI1R;

+  __IO uint32_t MACSPI2R;

+  __IO uint32_t MACLMIR;

+  uint32_t      RESERVED32[11];

+  __IO uint32_t MTLOMR;

+  uint32_t      RESERVED33[7];

+  __IO uint32_t MTLISR;

+  uint32_t      RESERVED34[55];

+  __IO uint32_t MTLTQOMR;

+  __IO uint32_t MTLTQUR;

+  __IO uint32_t MTLTQDR;

+  uint32_t      RESERVED35[8];

+  __IO uint32_t MTLQICSR;

+  __IO uint32_t MTLRQOMR;

+  __IO uint32_t MTLRQMPOCR;

+  __IO uint32_t MTLRQDR;

+  uint32_t      RESERVED36[177];

+  __IO uint32_t DMAMR;

+  __IO uint32_t DMASBMR;

+  __IO uint32_t DMAISR;

+  __IO uint32_t DMADSR;

+  uint32_t      RESERVED37[60];

+  __IO uint32_t DMACCR;

+  __IO uint32_t DMACTCR;

+  __IO uint32_t DMACRCR;

+  uint32_t      RESERVED38[2];

+  __IO uint32_t DMACTDLAR;

+  uint32_t      RESERVED39;

+  __IO uint32_t DMACRDLAR;

+  __IO uint32_t DMACTDTPR;

+  uint32_t      RESERVED40;

+  __IO uint32_t DMACRDTPR;

+  __IO uint32_t DMACTDRLR;

+  __IO uint32_t DMACRDRLR;

+  __IO uint32_t DMACIER;

+  __IO uint32_t DMACRIWTR;

+__IO uint32_t DMACSFCSR;

+  uint32_t      RESERVED41;

+  __IO uint32_t DMACCATDR;

+  uint32_t      RESERVED42;

+  __IO uint32_t DMACCARDR;

+  uint32_t      RESERVED43;

+  __IO uint32_t DMACCATBR;

+  uint32_t      RESERVED44;

+  __IO uint32_t DMACCARBR;

+  __IO uint32_t DMACSR;

+uint32_t      RESERVED45[2];

+__IO uint32_t DMACMFCR;

+}ETH_TypeDef;

+/**

+  * @brief External Interrupt/Event Controller

+  */

+

+typedef struct

+{

+__IO uint32_t RTSR1;               /*!< EXTI Rising trigger selection register,          Address offset: 0x00 */

+__IO uint32_t FTSR1;               /*!< EXTI Falling trigger selection register,         Address offset: 0x04 */

+__IO uint32_t SWIER1;              /*!< EXTI Software interrupt event register,          Address offset: 0x08 */

+__IO uint32_t D3PMR1;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */

+__IO uint32_t D3PCR1L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L)     Address offset: 0x10 */

+__IO uint32_t D3PCR1H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H)   Address offset: 0x14 */

+uint32_t      RESERVED1[2];        /*!< Reserved,                                        0x18 to 0x1C         */

+__IO uint32_t RTSR2;               /*!< EXTI Rising trigger selection register,          Address offset: 0x20 */

+__IO uint32_t FTSR2;               /*!< EXTI Falling trigger selection register,         Address offset: 0x24 */

+__IO uint32_t SWIER2;              /*!< EXTI Software interrupt event register,          Address offset: 0x28 */

+__IO uint32_t D3PMR2;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */

+__IO uint32_t D3PCR2L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L)  Address offset: 0x30 */

+__IO uint32_t D3PCR2H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */

+uint32_t      RESERVED2[2];        /*!< Reserved,                                        0x38 to 0x3C         */

+__IO uint32_t RTSR3;               /*!< EXTI Rising trigger selection register,          Address offset: 0x40 */

+__IO uint32_t FTSR3;               /*!< EXTI Falling trigger selection register,         Address offset: 0x44 */

+__IO uint32_t SWIER3;              /*!< EXTI Software interrupt event register,          Address offset: 0x48 */

+__IO uint32_t D3PMR3;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */

+__IO uint32_t D3PCR3L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */

+__IO uint32_t D3PCR3H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */

+uint32_t      RESERVED3[10];       /*!< Reserved,                                        0x58 to 0x7C         */

+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                    Address offset: 0x80 */

+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                        Address offset: 0x84 */

+__IO uint32_t PR1;                 /*!< EXTI Pending register,                           Address offset: 0x88 */

+uint32_t      RESERVED4;           /*!< Reserved,                                        0x8C                 */

+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                    Address offset: 0x90 */

+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                        Address offset: 0x94 */

+__IO uint32_t PR2;                 /*!< EXTI Pending register,                           Address offset: 0x98 */

+uint32_t      RESERVED5;           /*!< Reserved,                                        0x9C                 */

+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                    Address offset: 0xA0 */

+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                        Address offset: 0xA4 */

+__IO uint32_t PR3;                 /*!< EXTI Pending register,                           Address offset: 0xA8 */

+}EXTI_TypeDef;

+

+typedef struct

+{

+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                Address offset: 0x00 */

+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                    Address offset: 0x04 */

+__IO uint32_t PR1;                 /*!< EXTI Pending register,                       Address offset: 0x08 */

+uint32_t      RESERVED1;           /*!< Reserved, 0x0C                                                    */

+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                Address offset: 0x10 */

+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                    Address offset: 0x14 */

+__IO uint32_t PR2;                 /*!< EXTI Pending register,                       Address offset: 0x18 */

+uint32_t      RESERVED2;           /*!< Reserved, 0x1C                                                    */

+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                Address offset: 0x20 */

+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                    Address offset: 0x24 */

+__IO uint32_t PR3;                 /*!< EXTI Pending register,                       Address offset: 0x28 */

+}EXTI_Core_TypeDef;

+

+

+/**

+  * @brief FLASH Registers

+  */

+

+typedef struct

+{

+  __IO uint32_t ACR;             /*!< FLASH access control register,                            Address offset: 0x00  */

+  __IO uint32_t KEYR1;           /*!< Flash Key Register for bank1,                             Address offset: 0x04  */

+  __IO uint32_t OPTKEYR;         /*!< Flash Option Key Register,                                Address offset: 0x08  */

+  __IO uint32_t CR1;             /*!< Flash Control Register for bank1,                         Address offset: 0x0C  */

+  __IO uint32_t SR1;             /*!< Flash Status Register for bank1,                          Address offset: 0x10  */

+  __IO uint32_t CCR1;            /*!< Flash Control Register for bank1,                         Address offset: 0x14  */

+  __IO uint32_t OPTCR;           /*!< Flash Option Control Register,                            Address offset: 0x18  */

+  __IO uint32_t OPTSR_CUR;       /*!< Flash Option Status Current Register,                     Address offset: 0x1C  */

+  __IO uint32_t OPTSR_PRG;       /*!< Flash Option Status to Program Register,                  Address offset: 0x20  */

+  __IO uint32_t OPTCCR;          /*!< Flash Option Clear Control Register,                      Address offset: 0x24  */

+  __IO uint32_t PRAR_CUR1;       /*!< Flash Current Protection Address Register for bank1,      Address offset: 0x28  */

+  __IO uint32_t PRAR_PRG1;       /*!< Flash Protection Address to Program Register for bank1,   Address offset: 0x2C  */

+  __IO uint32_t SCAR_CUR1;       /*!< Flash Current Secure Address Register for bank1,          Address offset: 0x30  */

+  __IO uint32_t SCAR_PRG1;       /*!< Flash Secure Address to Program Register for bank1,       Address offset: 0x34  */

+  __IO uint32_t WPSN_CUR1;       /*!< Flash Current Write Protection Register on bank1,         Address offset: 0x38  */

+  __IO uint32_t WPSN_PRG1;       /*!< Flash Write Protection to Program Register on bank1,      Address offset: 0x3C  */

+  __IO uint32_t BOOT_CUR;        /*!< Flash Current Boot Address for Pelican Core Register,     Address offset: 0x40  */

+  __IO uint32_t BOOT_PRG;        /*!< Flash Boot Address to Program for Pelican Core Register,  Address offset: 0x44  */

+  uint32_t      RESERVED0[2];    /*!< Reserved, 0x48 to 0x4C                                                          */

+  __IO uint32_t CRCCR1;          /*!< Flash CRC Control register For Bank1 Register ,           Address offset: 0x50  */

+  __IO uint32_t CRCSADD1;        /*!< Flash CRC Start Address Register for Bank1 ,              Address offset: 0x54  */

+  __IO uint32_t CRCEADD1;        /*!< Flash CRC End Address Register for Bank1 ,                Address offset: 0x58  */

+  __IO uint32_t CRCDATA;         /*!< Flash CRC Data Register for Bank1 ,                       Address offset: 0x5C  */

+  __IO uint32_t ECC_FA1;         /*!< Flash ECC Fail Address For Bank1 Register ,               Address offset: 0x60  */

+  uint32_t      RESERVED1[40];   /*!< Reserved, 0x64 to 0x100                                                         */

+  __IO uint32_t KEYR2;           /*!< Flash Key Register for bank2,                             Address offset: 0x104 */

+  uint32_t      RESERVED2;       /*!< Reserved, 0x108                                                                 */

+  __IO uint32_t CR2;             /*!< Flash Control Register for bank2,                         Address offset: 0x10C */

+  __IO uint32_t SR2;             /*!< Flash Status Register for bank2,                          Address offset: 0x110 */

+  __IO uint32_t CCR2;            /*!< Flash Status Register for bank2,                          Address offset: 0x114 */

+  uint32_t      RESERVED3[4];    /*!< Reserved, 0x118 to 0x124                                                        */

+  __IO uint32_t PRAR_CUR2;       /*!< Flash Current Protection Address Register for bank2,      Address offset: 0x128 */

+  __IO uint32_t PRAR_PRG2;       /*!< Flash Protection Address to Program Register for bank2,   Address offset: 0x12C */

+  __IO uint32_t SCAR_CUR2;       /*!< Flash Current Secure Address Register for bank2,          Address offset: 0x130 */

+  __IO uint32_t SCAR_PRG2;       /*!< Flash Secure Address Register for bank2,                  Address offset: 0x134 */

+  __IO uint32_t WPSN_CUR2;       /*!< Flash Current Write Protection Register on bank2,         Address offset: 0x138 */

+  __IO uint32_t WPSN_PRG2;       /*!< Flash Write Protection to Program Register on bank2,      Address offset: 0x13C */

+  uint32_t      RESERVED4[4];    /*!< Reserved, 0x140 to 0x14C                                                        */

+  __IO uint32_t CRCCR2;          /*!< Flash CRC Control register For Bank2 Register ,           Address offset: 0x150 */

+  __IO uint32_t CRCSADD2;        /*!< Flash CRC Start Address Register for Bank2 ,              Address offset: 0x154 */

+  __IO uint32_t CRCEADD2;        /*!< Flash CRC End Address Register for Bank2 ,                Address offset: 0x158 */

+  __IO uint32_t CRCDATA2;        /*!< Flash CRC Data Register for Bank2 ,                       Address offset: 0x15C */

+  __IO uint32_t ECC_FA2;         /*!< Flash ECC Fail Address For Bank2 Register ,               Address offset: 0x160 */

+} FLASH_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */

+} FMC_Bank1_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank1E

+  */

+

+typedef struct

+{

+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */

+} FMC_Bank1E_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank2

+  */

+

+typedef struct

+{

+  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */

+  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */

+  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */

+  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */

+  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */

+  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */

+} FMC_Bank2_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank3

+  */

+

+typedef struct

+{

+  __IO uint32_t PCR;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */

+  __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */

+  __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */

+  __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */

+  uint32_t      RESERVED;  /*!< Reserved, 0x90                                                            */

+  __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */

+} FMC_Bank3_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank5 and 6

+  */

+

+

+typedef struct

+{

+  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */

+  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */

+  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */

+  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */

+  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */

+} FMC_Bank5_6_TypeDef;

+

+/**

+  * @brief General Purpose I/O

+  */

+

+typedef struct

+{

+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */

+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */

+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */

+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */

+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */

+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */

+  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset,               Address offset: 0x18      */

+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */

+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */

+} GPIO_TypeDef;

+

+/**

+  * @brief Operational Amplifier (OPAMP)

+  */

+

+typedef struct

+{

+  __IO uint32_t CSR;          /*!< OPAMP control/status register,                      Address offset: 0x00 */

+  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,     Address offset: 0x04 */

+  __IO uint32_t HSOTR;        /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */

+} OPAMP_TypeDef;

+

+/**

+  * @brief System configuration controller

+  */

+

+typedef struct

+{

+ uint32_t RESERVED1;           /*!< Reserved,                                           Address offset: 0x00        */

+ __IO uint32_t PMCR;           /*!< SYSCFG peripheral mode configuration register,      Address offset: 0x04        */

+ __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration registers,  Address offset: 0x08-0x14   */

+ __IO uint32_t CFGR;           /*!< SYSCFG configuration registers,                     Address offset: 0x18        */

+ uint32_t RESERVED2;           /*!< Reserved,                                           Address offset: 0x1C        */

+ __IO uint32_t CCCSR;          /*!< SYSCFG compensation cell control/status register,   Address offset: 0x20        */

+ __IO uint32_t CCVR;           /*!< SYSCFG compensation cell value register,            Address offset: 0x24        */

+ __IO uint32_t CCCR;           /*!< SYSCFG compensation cell code register,             Address offset: 0x28        */

+ __IO uint32_t PWRCR;          /*!< PWR control register,                               Address offset: 0x2C        */

+  uint32_t     RESERVED3[61];  /*!< Reserved, 0x30-0x120                                                            */

+  __IO uint32_t PKGR;          /*!< SYSCFG package register,                            Address offset: 0x124       */

+  uint32_t     RESERVED4[118]; /*!< Reserved, 0x128-0x2FC                                                           */

+ __IO uint32_t UR0;            /*!< SYSCFG user register 0,                             Address offset: 0x300       */

+ __IO uint32_t UR1;            /*!< SYSCFG user register 1,                             Address offset: 0x304       */

+ __IO uint32_t UR2;            /*!< SYSCFG user register 2,                             Address offset: 0x308       */

+ __IO uint32_t UR3;            /*!< SYSCFG user register 3,                             Address offset: 0x30C       */

+ __IO uint32_t UR4;            /*!< SYSCFG user register 4,                             Address offset: 0x310       */

+ __IO uint32_t UR5;            /*!< SYSCFG user register 5,                             Address offset: 0x314       */

+ __IO uint32_t UR6;            /*!< SYSCFG user register 6,                             Address offset: 0x318       */

+ __IO uint32_t UR7;            /*!< SYSCFG user register 7,                             Address offset: 0x31C       */

+ __IO uint32_t UR8;            /*!< SYSCFG user register 8,                             Address offset: 0x320       */

+ __IO uint32_t UR9;            /*!< SYSCFG user register 9,                             Address offset: 0x324       */

+ __IO uint32_t UR10;           /*!< SYSCFG user register 10,                            Address offset: 0x328       */

+ __IO uint32_t UR11;           /*!< SYSCFG user register 11,                            Address offset: 0x32C       */

+ __IO uint32_t UR12;           /*!< SYSCFG user register 12,                            Address offset: 0x330       */

+ __IO uint32_t UR13;           /*!< SYSCFG user register 13,                            Address offset: 0x334       */

+ __IO uint32_t UR14;           /*!< SYSCFG user register 14,                            Address offset: 0x338       */

+ __IO uint32_t UR15;           /*!< SYSCFG user register 15,                            Address offset: 0x33C       */

+ __IO uint32_t UR16;           /*!< SYSCFG user register 16,                            Address offset: 0x340       */

+ __IO uint32_t UR17;           /*!< SYSCFG user register 17,                            Address offset: 0x344       */

+

+} SYSCFG_TypeDef;

+

+/**

+  * @brief Inter-integrated Circuit Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */

+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */

+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */

+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */

+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */

+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */

+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */

+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */

+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */

+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */

+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */

+} I2C_TypeDef;

+

+/**

+  * @brief Independent WATCHDOG

+  */

+

+typedef struct

+{

+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */

+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */

+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */

+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */

+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */

+} IWDG_TypeDef;

+

+

+/**

+  * @brief JPEG Codec

+  */

+typedef struct

+{

+  __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */

+  __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */

+  __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */

+  __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */

+  __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */

+  __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */

+  __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */

+  __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */

+  uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */

+  __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */

+  __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */

+  __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */

+  uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */

+  __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */

+  __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */

+  uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */

+  __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */

+  __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */

+  __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */

+  __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */

+  __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */

+  __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */

+  __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */

+  __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */

+  uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */

+  __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0,                 Address offset: 500h-65Ch */

+  __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1,                 Address offset: 660h-7BCh */

+  __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encodor, DC Huffman table 0,                 Address offset: 7C0h-7DCh */

+  __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encodor, DC Huffman table 1,                 Address offset: 7E0h-7FCh */

+

+} JPEG_TypeDef;

+

+/**

+  * @brief LCD-TFT Display Controller

+  */

+

+typedef struct

+{

+  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04                                                       */

+  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */

+  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */

+  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */

+  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */

+  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */

+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20                                                       */

+  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */

+  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28                                                            */

+  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */

+  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30                                                            */

+  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */

+  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */

+  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */

+  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */

+  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */

+  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */

+} LTDC_TypeDef;

+

+/**

+  * @brief LCD-TFT Display layer x Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */

+  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */

+  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */

+  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */

+  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */

+  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */

+  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */

+  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */

+  uint32_t      RESERVED0[2];  /*!< Reserved */

+  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */

+  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */

+  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */

+  uint32_t      RESERVED1[3];  /*!< Reserved */

+  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */

+

+} LTDC_Layer_TypeDef;

+

+/**

+  * @brief Power Control

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;       /*!< PWR power control register 1,            Address offset: 0x00 */

+  __IO uint32_t CSR1;      /*!< PWR power control status register 1,     Address offset: 0x04 */

+  __IO uint32_t CR2;       /*!< PWR power control register 2,            Address offset: 0x08 */

+  __IO uint32_t CR3;       /*!< PWR power control register 3,            Address offset: 0x0C */

+  __IO uint32_t CPUCR;     /*!< PWR CPU control register,                Address offset: 0x10 */

+       uint32_t RESERVED0; /*!< Reserved,                                Address offset: 0x14 */

+  __IO uint32_t D3CR;      /*!< PWR D3 domain control register,          Address offset: 0x18 */

+       uint32_t RESERVED1; /*!< Reserved,                                Address offset: 0x1C */

+  __IO uint32_t WKUPCR;    /*!< PWR wakeup clear register,               Address offset: 0x20 */

+  __IO uint32_t WKUPFR;    /*!< PWR wakeup flag register,                Address offset: 0x24 */

+  __IO uint32_t WKUPEPR;   /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */

+} PWR_TypeDef;

+

+/**

+  * @brief Reset and Clock Control

+  */

+

+typedef struct

+{

+ __IO uint32_t CR;             /*!< RCC clock control register,                                              Address offset: 0x00  */

+ __IO uint32_t HSICFGR;        /*!< HSI Clock Calibration Register,                                          Address offset: 0x04  */

+ __IO uint32_t CRRCR;          /*!< Clock Recovery RC  Register,                                             Address offset: 0x08  */

+ __IO uint32_t CSICFGR;        /*!< CSI Clock Calibration Register,                                          Address offset: 0x0C  */

+ __IO uint32_t CFGR;           /*!< RCC clock configuration register,                                        Address offset: 0x10  */

+ uint32_t     RESERVED1;       /*!< Reserved,                                                                Address offset: 0x14  */

+ __IO uint32_t D1CFGR;         /*!< RCC Domain 1 configuration register,                                     Address offset: 0x18  */

+ __IO uint32_t D2CFGR;         /*!< RCC Domain 2 configuration register,                                     Address offset: 0x1C  */

+ __IO uint32_t D3CFGR;         /*!< RCC Domain 3 configuration register,                                     Address offset: 0x20  */

+ uint32_t     RESERVED2;       /*!< Reserved,                                                                Address offset: 0x24  */

+ __IO uint32_t PLLCKSELR;      /*!< RCC PLLs Clock Source Selection Register,                                Address offset: 0x28  */

+ __IO uint32_t PLLCFGR;        /*!< RCC PLLs  Configuration Register,                                        Address offset: 0x2C  */

+ __IO uint32_t PLL1DIVR;       /*!< RCC PLL1 Dividers Configuration Register,                                Address offset: 0x30  */

+ __IO uint32_t PLL1FRACR;      /*!< RCC PLL1 Fractional Divider Configuration Register,                      Address offset: 0x34  */

+ __IO uint32_t PLL2DIVR;       /*!< RCC PLL2 Dividers Configuration Register,                                Address offset: 0x38  */

+ __IO uint32_t PLL2FRACR;      /*!< RCC PLL2 Fractional Divider Configuration Register,                      Address offset: 0x3C  */

+ __IO uint32_t PLL3DIVR;       /*!< RCC PLL3 Dividers Configuration Register,                                Address offset: 0x40  */

+ __IO uint32_t PLL3FRACR;      /*!< RCC PLL3 Fractional Divider Configuration Register,                      Address offset: 0x44  */

+ uint32_t      RESERVED3;      /*!< Reserved,                                                                Address offset: 0x48  */

+ __IO uint32_t  D1CCIPR;       /*!< RCC Domain 1 Kernel Clock Configuration Register                         Address offset: 0x4C  */

+ __IO uint32_t  D2CCIP1R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x50  */

+ __IO uint32_t  D2CCIP2R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x54  */

+ __IO uint32_t  D3CCIPR;       /*!< RCC Domain 3 Kernel Clock Configuration Register                         Address offset: 0x58  */

+ uint32_t      RESERVED4;      /*!< Reserved,                                                                Address offset: 0x5C  */

+ __IO uint32_t  CIER;          /*!< RCC Clock Source Interrupt Enable Register                               Address offset: 0x60  */

+ __IO uint32_t  CIFR;          /*!< RCC Clock Source Interrupt Flag Register                                 Address offset: 0x64  */

+ __IO uint32_t  CICR;          /*!< RCC Clock Source Interrupt Clear Register                                Address offset: 0x68  */

+ uint32_t     RESERVED5;       /*!< Reserved,                                                                Address offset: 0x6C  */

+ __IO uint32_t  BDCR;          /*!< RCC Vswitch Backup Domain Control Register,                              Address offset: 0x70  */

+ __IO uint32_t  CSR;           /*!< RCC clock control & status register,                                     Address offset: 0x74  */

+ uint32_t     RESERVED6;       /*!< Reserved,                                                                Address offset: 0x78  */

+ __IO uint32_t AHB3RSTR;       /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x7C  */

+ __IO uint32_t AHB1RSTR;       /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x80  */

+ __IO uint32_t AHB2RSTR;       /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x84  */

+ __IO uint32_t AHB4RSTR;       /*!< RCC AHB4 peripheral reset register,                                      Address offset: 0x88  */

+ __IO uint32_t APB3RSTR;       /*!< RCC APB3 peripheral reset register,                                      Address offset: 0x8C  */

+ __IO uint32_t APB1LRSTR;      /*!< RCC APB1 peripheral reset Low Word register,                             Address offset: 0x90  */

+ __IO uint32_t APB1HRSTR;      /*!< RCC APB1 peripheral reset High Word register,                            Address offset: 0x94  */

+ __IO uint32_t APB2RSTR;       /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x98  */

+ __IO uint32_t APB4RSTR;       /*!< RCC APB4 peripheral reset register,                                      Address offset: 0x9C  */

+ __IO uint32_t GCR;            /*!< RCC RCC Global Control  Register,                                        Address offset: 0xA0  */

+ uint32_t     RESERVED8;       /*!< Reserved,                                                                Address offset: 0xA4  */

+ __IO uint32_t D3AMR;          /*!< RCC Domain 3 Autonomous Mode Register,                                   Address offset: 0xA8  */

+ uint32_t     RESERVED11[9];    /*!< Reserved, 0xAC-0xCC                                                      Address offset: 0xAC  */

+ __IO uint32_t RSR;            /*!< RCC Reset status register,                                               Address offset: 0xD0  */

+ __IO uint32_t AHB3ENR;        /*!< RCC AHB3 peripheral clock  register,                                     Address offset: 0xD4  */

+ __IO uint32_t AHB1ENR;        /*!< RCC AHB1 peripheral clock  register,                                     Address offset: 0xD8  */

+ __IO uint32_t AHB2ENR;        /*!< RCC AHB2 peripheral clock  register,                                     Address offset: 0xDC  */

+ __IO uint32_t AHB4ENR;        /*!< RCC AHB4 peripheral clock  register,                                     Address offset: 0xE0  */

+ __IO uint32_t APB3ENR;        /*!< RCC APB3 peripheral clock  register,                                     Address offset: 0xE4  */

+ __IO uint32_t APB1LENR;       /*!< RCC APB1 peripheral clock  Low Word register,                            Address offset: 0xE8  */

+ __IO uint32_t APB1HENR;       /*!< RCC APB1 peripheral clock  High Word register,                           Address offset: 0xEC  */

+ __IO uint32_t APB2ENR;        /*!< RCC APB2 peripheral clock  register,                                     Address offset: 0xF0  */

+ __IO uint32_t APB4ENR;        /*!< RCC APB4 peripheral clock  register,                                     Address offset: 0xF4  */

+ uint32_t      RESERVED12;      /*!< Reserved,                                                                Address offset: 0xF8  */

+ __IO uint32_t AHB3LPENR;      /*!< RCC AHB3 peripheral sleep clock  register,                               Address offset: 0xFC  */

+ __IO uint32_t AHB1LPENR;      /*!< RCC AHB1 peripheral sleep clock  register,                               Address offset: 0x100 */

+ __IO uint32_t AHB2LPENR;      /*!< RCC AHB2 peripheral sleep clock  register,                               Address offset: 0x104 */

+ __IO uint32_t AHB4LPENR;      /*!< RCC AHB4 peripheral sleep clock  register,                               Address offset: 0x108 */

+ __IO uint32_t APB3LPENR;      /*!< RCC APB3 peripheral sleep clock  register,                               Address offset: 0x10C */

+ __IO uint32_t APB1LLPENR;     /*!< RCC APB1 peripheral sleep clock  Low Word register,                      Address offset: 0x110 */

+ __IO uint32_t APB1HLPENR;     /*!< RCC APB1 peripheral sleep clock  High Word register,                     Address offset: 0x114 */

+ __IO uint32_t APB2LPENR;      /*!< RCC APB2 peripheral sleep clock  register,                               Address offset: 0x118 */

+ __IO uint32_t APB4LPENR;      /*!< RCC APB4 peripheral sleep clock  register,                               Address offset: 0x11C */

+ uint32_t     RESERVED13[4];   /*!< Reserved, 0x120-0x12C                                                    Address offset: 0x120 */

+

+} RCC_TypeDef;

+

+

+/**

+  * @brief Real-Time Clock

+  */

+typedef struct

+{

+  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */

+  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */

+  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */

+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */

+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */

+  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */

+       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */

+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */

+  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */

+  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */

+  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */

+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */

+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */

+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */

+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */

+  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */

+  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */

+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */

+  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */

+  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset: 0x4C */

+  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */

+  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */

+  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */

+  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */

+  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */

+  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */

+  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */

+  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */

+  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */

+  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */

+  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */

+  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */

+  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */

+  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */

+  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */

+  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */

+  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */

+  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */

+  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */

+  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */

+  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */

+  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */

+  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */

+  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */

+  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */

+  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */

+  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */

+  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */

+  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */

+  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */

+  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */

+  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */

+} RTC_TypeDef;

+

+/**

+  * @brief Serial Audio Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t GCR;           /*!< SAI global configuration register, Address offset: 0x00 */

+  uint32_t      RESERVED0[16]; /*!< Reserved, 0x04 - 0x43                                   */

+  __IO uint32_t PDMCR;         /*!< SAI PDM control register,          Address offset: 0x44 */

+  __IO uint32_t PDMDLY;        /*!< SAI PDM delay register,            Address offset: 0x48 */

+} SAI_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */

+  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */

+  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */

+  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */

+  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */

+  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */

+  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */

+  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */

+} SAI_Block_TypeDef;

+

+/**

+  * @brief SPDIF-RX Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */

+  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */

+  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */

+  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */

+  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */

+  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */

+  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */

+  uint32_t        RESERVED2;    /*!< Reserved,  0x1A                                          */

+} SPDIFRX_TypeDef;

+

+

+/**

+  * @brief Secure digital input/output Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t POWER;          /*!< SDMMC power control register,             Address offset: 0x00  */

+  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,             Address offset: 0x04  */

+  __IO uint32_t ARG;            /*!< SDMMC argument register,                  Address offset: 0x08  */

+  __IO uint32_t CMD;            /*!< SDMMC command register,                   Address offset: 0x0C  */

+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register,          Address offset: 0x10  */

+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                Address offset: 0x14  */

+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                Address offset: 0x18  */

+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                Address offset: 0x1C  */

+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                Address offset: 0x20  */

+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                Address offset: 0x24  */

+  __IO uint32_t DLEN;           /*!< SDMMC data length register,               Address offset: 0x28  */

+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,              Address offset: 0x2C  */

+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,              Address offset: 0x30  */

+  __I uint32_t  STA;            /*!< SDMMC status register,                    Address offset: 0x34  */

+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,           Address offset: 0x38  */

+  __IO uint32_t MASK;           /*!< SDMMC mask register,                      Address offset: 0x3C  */

+  __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,     Address offset: 0x40  */

+  uint32_t      RESERVED0[3];   /*!< Reserved, 0x44 - 0x4C - 0x4C                                    */

+  __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,               Address offset: 0x50  */

+  __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,           Address offset: 0x54  */

+  __IO uint32_t IDMABASE0;      /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58  */

+  __IO uint32_t IDMABASE1;      /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C  */

+  uint32_t      RESERVED1[8];   /*!< Reserved, 0x60-0x7C                                             */

+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,                 Address offset: 0x80  */

+  uint32_t      RESERVED2[222]; /*!< Reserved, 0x84-0x3F8                                            */

+  __IO uint32_t IPVR;           /*!< SDMMC data FIFO register,                 Address offset: 0x3FC */

+} SDMMC_TypeDef;

+

+

+/**

+  * @brief Delay Block DLYB

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;          /*!< DELAY BLOCK control register,  Address offset: 0x00 */

+  __IO uint32_t CFGR;        /*!< DELAY BLOCK configuration register,  Address offset: 0x04 */

+} DLYB_TypeDef;

+

+/**

+  * @brief HW Semaphore HSEM

+  */

+

+typedef struct

+{

+  __IO uint32_t R[32];      /*!< 2-step write lock and read back registers,     Address offset: 00h-7Ch  */

+  __IO uint32_t RLR[32];    /*!< 1-step read lock registers,                    Address offset: 80h-FCh  */

+  __IO uint32_t C1IER;      /*!< HSEM Interrupt enable register ,             Address offset: 100h     */

+  __IO uint32_t C1ICR;      /*!< HSEM Interrupt clear register ,              Address offset: 104h     */

+  __IO uint32_t C1ISR;      /*!< HSEM Interrupt Status register ,             Address offset: 108h     */

+  __IO uint32_t C1MISR;     /*!< HSEM Interrupt Masked Status register ,      Address offset: 10Ch     */

+  uint32_t  Reserved[12];   /* Reserved                                       Address offset: 110h-13Ch  */

+  __IO uint32_t CR;         /*!< HSEM Semaphore clear register ,                Address offset: 140h      */

+  __IO uint32_t KEYR;       /*!< HSEM Semaphore clear key register ,            Address offset: 144h      */

+

+} HSEM_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t IER;        /*!< HSEM interrupt enable register ,                Address offset:   0h     */

+  __IO uint32_t ICR;        /*!< HSEM interrupt clear register ,                 Address offset:   4h     */

+  __IO uint32_t ISR;        /*!< HSEM interrupt status register ,                Address offset:   8h     */

+  __IO uint32_t MISR;       /*!< HSEM masked interrupt status register ,         Address offset:   Ch     */

+} HSEM_Common_TypeDef;

+

+/**

+  * @brief Serial Peripheral Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */

+  __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */

+  __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */

+  __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */

+  __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */

+  __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */

+  __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */

+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */

+  __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */

+  uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */

+  __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */

+  uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */

+  __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */

+  __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */

+  __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */

+  __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */

+  __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */

+

+} SPI_TypeDef;

+/**

+  * @brief QUAD Serial Peripheral Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */

+  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */

+  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */

+  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */

+  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */

+  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */

+  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */

+  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */

+  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */

+  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */

+  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */

+  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */

+  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */

+} QUADSPI_TypeDef;

+

+/**

+  * @brief TIM

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */

+  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */

+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */

+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */

+  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */

+  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */

+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */

+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */

+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */

+  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */

+  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */

+  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */

+  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */

+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */

+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */

+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */

+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */

+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */

+  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */

+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */

+  uint32_t      RESERVED1;   /*!< Reserved, 0x50                                                 */

+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */

+  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */

+  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */

+  __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */

+  __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */

+  __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x68 */

+} TIM_TypeDef;

+

+/**

+  * @brief LPTIMIMER

+  */

+typedef struct

+{

+  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,         Address offset: 0x00 */

+  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,              Address offset: 0x04 */

+  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,             Address offset: 0x08 */

+  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                Address offset: 0x0C */

+  __IO uint32_t CR;       /*!< LPTIM Control register,                      Address offset: 0x10 */

+  __IO uint32_t CMP;      /*!< LPTIM Compare register,                      Address offset: 0x14 */

+  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                   Address offset: 0x18 */

+  __IO uint32_t CNT;      /*!< LPTIM Counter register,                      Address offset: 0x1C */

+  uint32_t  RESERVED1;    /*!< Reserved, 0x20                                                    */

+  __IO uint32_t CFGR2;    /*!< LPTIM Configuration register,                Address offset: 0x24 */

+} LPTIM_TypeDef;

+

+/**

+  * @brief Comparator

+  */

+typedef struct

+{

+  __IO uint32_t SR;        /*!< Comparator status register,                    Address offset: 0x00 */

+  __IO uint32_t ICFR;      /*!< Comparator interrupt clear flag register,       Address offset: 0x04 */

+  __IO uint32_t OR;        /*!< Comparator option register,                  Address offset: 0x08 */

+} COMPOPT_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CFGR;      /*!< Comparator configuration register  ,           Address offset: 0x00 */

+} COMP_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CFGR;       /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */

+} COMP_Common_TypeDef;

+/**

+  * @brief Universal Synchronous Asynchronous Receiver Transmitter

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */

+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */

+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */

+  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */

+  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */

+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */

+  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */

+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */

+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */

+  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */

+  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */

+  __IO uint32_t PRESC;  /*!< USART clock Prescaler register,           Address offset: 0x2C */

+} USART_TypeDef;

+

+/**

+  * @brief Single Wire Protocol Master Interface SPWMI

+  */

+typedef struct

+{

+  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */

+  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */

+    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */

+  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */

+  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */

+  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */

+  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */

+  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */

+  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */

+  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */

+} SWPMI_TypeDef;

+

+/**

+  * @brief Window WATCHDOG

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */

+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */

+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */

+} WWDG_TypeDef;

+

+

+/**

+  * @brief RAM_ECC_Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t CR;           /*!< RAMECC monitor configuration register          */

+  __IO uint32_t SR;           /*!< RAMECC monitor status register                 */

+  __IO uint32_t FAR;          /*!< RAMECC monitor failing address register        */

+  __IO uint32_t FDRL;         /*!< RAMECC monitor failing data low register       */

+  __IO uint32_t FDRH;         /*!< RAMECC monitor failing data high register      */

+  __IO uint32_t FECR;         /*!< RAMECC monitor failing ECC error code register */

+} RAMECC_MonitorTypeDef;

+

+typedef struct

+{

+  __IO uint32_t IER;          /*!< RAMECC interrupt enable register */

+} RAMECC_TypeDef;

+/**

+  * @}

+  */

+

+

+/**

+  * @brief Crypto Processor

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */

+  __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */

+  __IO uint32_t DIN;         /*!< CRYP data input register,                                Address offset: 0x08 */

+  __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */

+  __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */

+  __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */

+  __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */

+  __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */

+  __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */

+  __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */

+  __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */

+  __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */

+  __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */

+  __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */

+  __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */

+  __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */

+  __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */

+  __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */

+  __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */

+  __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */

+  __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */

+  __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */

+  __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */

+  __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */

+  __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */

+  __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */

+  __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */

+  __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */

+  __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */

+  __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */

+  __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */

+  __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */

+  __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */

+  __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */

+  __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */

+  __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */

+} CRYP_TypeDef;

+

+/**

+  * @brief HASH

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */

+  __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */

+  __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */

+  __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */

+  __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */

+  __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */

+       uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */

+  __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */

+} HASH_TypeDef;

+

+/**

+  * @brief HASH_DIGEST

+  */

+

+typedef struct

+{

+  __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */

+} HASH_DIGEST_TypeDef;

+

+

+/**

+  * @brief High resolution Timer (HRTIM)

+  */

+/* HRTIM master registers definition */

+typedef struct

+{

+  __IO uint32_t MCR;            /*!< HRTIM Master Timer control register,                     Address offset: 0x00 */

+  __IO uint32_t MISR;           /*!< HRTIM Master Timer interrupt status register,            Address offset: 0x04 */

+  __IO uint32_t MICR;           /*!< HRTIM Master Timer interupt clear register,              Address offset: 0x08 */

+  __IO uint32_t MDIER;          /*!< HRTIM Master Timer DMA/interrupt enable register         Address offset: 0x0C */

+  __IO uint32_t MCNTR;          /*!< HRTIM Master Timer counter register,                     Address offset: 0x10 */

+  __IO uint32_t MPER;           /*!< HRTIM Master Timer period register,                      Address offset: 0x14 */

+  __IO uint32_t MREP;           /*!< HRTIM Master Timer repetition register,                  Address offset: 0x18 */

+  __IO uint32_t MCMP1R;         /*!< HRTIM Master Timer compare 1 register,                   Address offset: 0x1C */

+  uint32_t      RESERVED0;     /*!< Reserved,                                                                 0x20 */

+  __IO uint32_t MCMP2R;         /*!< HRTIM Master Timer compare 2 register,                   Address offset: 0x24 */

+  __IO uint32_t MCMP3R;         /*!< HRTIM Master Timer compare 3 register,                   Address offset: 0x28 */

+  __IO uint32_t MCMP4R;         /*!< HRTIM Master Timer compare 4 register,                   Address offset: 0x2C */

+  uint32_t      RESERVED1[20];  /*!< Reserved,                                                          0x30..0x7C */

+}HRTIM_Master_TypeDef;

+

+/* HRTIM Timer A to E registers definition */

+typedef struct

+{

+  __IO uint32_t TIMxCR;     /*!< HRTIM Timerx control register,                              Address offset: 0x00 */

+  __IO uint32_t TIMxISR;    /*!< HRTIM Timerx interrupt status register,                     Address offset: 0x04 */

+  __IO uint32_t TIMxICR;    /*!< HRTIM Timerx interrupt clear register,                      Address offset: 0x08 */

+  __IO uint32_t TIMxDIER;   /*!< HRTIM Timerx DMA/interrupt enable register,                 Address offset: 0x0C */

+  __IO uint32_t CNTxR;      /*!< HRTIM Timerx counter register,                              Address offset: 0x10 */

+  __IO uint32_t PERxR;      /*!< HRTIM Timerx period register,                               Address offset: 0x14 */

+  __IO uint32_t REPxR;      /*!< HRTIM Timerx repetition register,                           Address offset: 0x18 */

+  __IO uint32_t CMP1xR;     /*!< HRTIM Timerx compare 1 register,                            Address offset: 0x1C */

+  __IO uint32_t CMP1CxR;    /*!< HRTIM Timerx compare 1 compound register,                   Address offset: 0x20 */

+  __IO uint32_t CMP2xR;     /*!< HRTIM Timerx compare 2 register,                            Address offset: 0x24 */

+  __IO uint32_t CMP3xR;     /*!< HRTIM Timerx compare 3 register,                            Address offset: 0x28 */

+  __IO uint32_t CMP4xR;     /*!< HRTIM Timerx compare 4 register,                            Address offset: 0x2C */

+  __IO uint32_t CPT1xR;     /*!< HRTIM Timerx capture 1 register,                            Address offset: 0x30 */

+  __IO uint32_t CPT2xR;     /*!< HRTIM Timerx capture 2 register,                            Address offset: 0x34 */

+  __IO uint32_t DTxR;       /*!< HRTIM Timerx dead time register,                            Address offset: 0x38 */

+  __IO uint32_t SETx1R;     /*!< HRTIM Timerx output 1 set register,                         Address offset: 0x3C */

+  __IO uint32_t RSTx1R;     /*!< HRTIM Timerx output 1 reset register,                       Address offset: 0x40 */

+  __IO uint32_t SETx2R;     /*!< HRTIM Timerx output 2 set register,                         Address offset: 0x44 */

+  __IO uint32_t RSTx2R;     /*!< HRTIM Timerx output 2 reset register,                       Address offset: 0x48 */

+  __IO uint32_t EEFxR1;     /*!< HRTIM Timerx external event filtering 1 register,           Address offset: 0x4C */

+  __IO uint32_t EEFxR2;     /*!< HRTIM Timerx external event filtering 2 register,           Address offset: 0x50 */

+  __IO uint32_t RSTxR;      /*!< HRTIM Timerx Reset register,                                Address offset: 0x54 */

+  __IO uint32_t CHPxR;      /*!< HRTIM Timerx Chopper register,                              Address offset: 0x58 */

+  __IO uint32_t CPT1xCR;    /*!< HRTIM Timerx Capture 1 register,                            Address offset: 0x5C */

+  __IO uint32_t CPT2xCR;    /*!< HRTIM Timerx Capture 2 register,                            Address offset: 0x60 */

+  __IO uint32_t OUTxR;      /*!< HRTIM Timerx Output register,                               Address offset: 0x64 */

+  __IO uint32_t FLTxR;      /*!< HRTIM Timerx Fault register,                                Address offset: 0x68 */

+  uint32_t      RESERVED0[5];  /*!< Reserved,                                                          0x6C..0x7C */

+}HRTIM_Timerx_TypeDef;

+

+/* HRTIM common register definition */

+typedef struct

+{

+  __IO uint32_t CR1;        /*!< HRTIM control register1,                                    Address offset: 0x00 */

+  __IO uint32_t CR2;        /*!< HRTIM control register2,                                    Address offset: 0x04 */

+  __IO uint32_t ISR;        /*!< HRTIM interrupt status register,                            Address offset: 0x08 */

+  __IO uint32_t ICR;        /*!< HRTIM interrupt clear register,                             Address offset: 0x0C */

+  __IO uint32_t IER;        /*!< HRTIM interrupt enable register,                            Address offset: 0x10 */

+  __IO uint32_t OENR;       /*!< HRTIM Output enable register,                               Address offset: 0x14 */

+  __IO uint32_t ODISR;      /*!< HRTIM Output disable register,                              Address offset: 0x18 */

+  __IO uint32_t ODSR;       /*!< HRTIM Output disable status register,                       Address offset: 0x1C */

+  __IO uint32_t BMCR;       /*!< HRTIM Burst mode control register,                          Address offset: 0x20 */

+  __IO uint32_t BMTRGR;     /*!< HRTIM Busrt mode trigger register,                          Address offset: 0x24 */

+  __IO uint32_t BMCMPR;     /*!< HRTIM Burst mode compare register,                          Address offset: 0x28 */

+  __IO uint32_t BMPER;      /*!< HRTIM Burst mode period register,                           Address offset: 0x2C */

+  __IO uint32_t EECR1;      /*!< HRTIM Timer external event control register1,               Address offset: 0x30 */

+  __IO uint32_t EECR2;      /*!< HRTIM Timer external event control register2,               Address offset: 0x34 */

+  __IO uint32_t EECR3;      /*!< HRTIM Timer external event control register3,               Address offset: 0x38 */

+  __IO uint32_t ADC1R;      /*!< HRTIM ADC Trigger 1 register,                               Address offset: 0x3C */

+  __IO uint32_t ADC2R;      /*!< HRTIM ADC Trigger 2 register,                               Address offset: 0x40 */

+  __IO uint32_t ADC3R;      /*!< HRTIM ADC Trigger 3 register,                               Address offset: 0x44 */

+  __IO uint32_t ADC4R;      /*!< HRTIM ADC Trigger 4 register,                               Address offset: 0x48 */

+  __IO uint32_t RESERVED0;  /*!< Reserved,                                                   Address offset: 0x4C */

+  __IO uint32_t FLTINR1;    /*!< HRTIM Fault input register1,                                Address offset: 0x50 */

+  __IO uint32_t FLTINR2;    /*!< HRTIM Fault input register2,                                Address offset: 0x54 */

+  __IO uint32_t BDMUPR;     /*!< HRTIM Burst DMA Master Timer update register,               Address offset: 0x58 */

+  __IO uint32_t BDTAUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x5C */

+  __IO uint32_t BDTBUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x60 */

+  __IO uint32_t BDTCUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x64 */

+  __IO uint32_t BDTDUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x68 */

+  __IO uint32_t BDTEUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x6C */

+  __IO uint32_t BDMADR;     /*!< HRTIM Burst DMA Master Data register,                       Address offset: 0x70 */

+}HRTIM_Common_TypeDef;

+

+/* HRTIM  register definition */

+typedef struct {

+  HRTIM_Master_TypeDef sMasterRegs;

+  HRTIM_Timerx_TypeDef sTimerxRegs[5];

+  uint32_t             RESERVED0[32];

+  HRTIM_Common_TypeDef sCommonRegs;

+}HRTIM_TypeDef;

+/**

+  * @brief RNG

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */

+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */

+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */

+} RNG_TypeDef;

+

+/**

+  * @brief MDIOS

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;

+  __IO uint32_t WRFR;

+  __IO uint32_t CWRFR;

+  __IO uint32_t RDFR;

+  __IO uint32_t CRDFR;

+  __IO uint32_t SR;

+  __IO uint32_t CLRFR;

+  uint32_t RESERVED[57];

+  __IO uint32_t DINR0;

+  __IO uint32_t DINR1;

+  __IO uint32_t DINR2;

+  __IO uint32_t DINR3;

+  __IO uint32_t DINR4;

+  __IO uint32_t DINR5;

+  __IO uint32_t DINR6;

+  __IO uint32_t DINR7;

+  __IO uint32_t DINR8;

+  __IO uint32_t DINR9;

+  __IO uint32_t DINR10;

+  __IO uint32_t DINR11;

+  __IO uint32_t DINR12;

+  __IO uint32_t DINR13;

+  __IO uint32_t DINR14;

+  __IO uint32_t DINR15;

+  __IO uint32_t DINR16;

+  __IO uint32_t DINR17;

+  __IO uint32_t DINR18;

+  __IO uint32_t DINR19;

+  __IO uint32_t DINR20;

+  __IO uint32_t DINR21;

+  __IO uint32_t DINR22;

+  __IO uint32_t DINR23;

+  __IO uint32_t DINR24;

+  __IO uint32_t DINR25;

+  __IO uint32_t DINR26;

+  __IO uint32_t DINR27;

+  __IO uint32_t DINR28;

+  __IO uint32_t DINR29;

+  __IO uint32_t DINR30;

+  __IO uint32_t DINR31;

+  __IO uint32_t DOUTR0;

+  __IO uint32_t DOUTR1;

+  __IO uint32_t DOUTR2;

+  __IO uint32_t DOUTR3;

+  __IO uint32_t DOUTR4;

+  __IO uint32_t DOUTR5;

+  __IO uint32_t DOUTR6;

+  __IO uint32_t DOUTR7;

+  __IO uint32_t DOUTR8;

+  __IO uint32_t DOUTR9;

+  __IO uint32_t DOUTR10;

+  __IO uint32_t DOUTR11;

+  __IO uint32_t DOUTR12;

+  __IO uint32_t DOUTR13;

+  __IO uint32_t DOUTR14;

+  __IO uint32_t DOUTR15;

+  __IO uint32_t DOUTR16;

+  __IO uint32_t DOUTR17;

+  __IO uint32_t DOUTR18;

+  __IO uint32_t DOUTR19;

+  __IO uint32_t DOUTR20;

+  __IO uint32_t DOUTR21;

+  __IO uint32_t DOUTR22;

+  __IO uint32_t DOUTR23;

+  __IO uint32_t DOUTR24;

+  __IO uint32_t DOUTR25;

+  __IO uint32_t DOUTR26;

+  __IO uint32_t DOUTR27;

+  __IO uint32_t DOUTR28;

+  __IO uint32_t DOUTR29;

+  __IO uint32_t DOUTR30;

+  __IO uint32_t DOUTR31;

+} MDIOS_TypeDef;

+

+

+/**

+  * @brief USB_OTG_Core_Registers

+  */

+typedef struct

+{

+ __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */

+  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */

+  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */

+  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */

+  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */

+  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */

+  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */

+  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */

+  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */

+  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */

+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */

+  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */

+  uint32_t Reserved30[2];             /*!< Reserved                                     030h */

+  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */

+  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */

+  __IO uint32_t GSNPSID;              /* USB_OTG core ID                                040h*/

+  __IO uint32_t GHWCFG1;              /* User HW config1                                044h*/

+  __IO uint32_t GHWCFG2;              /* User HW config2                                048h*/

+  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */

+  uint32_t  Reserved6;                /*!< Reserved                                     050h */

+  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */

+  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */

+  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */

+   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */

+    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */

+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */

+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */

+} USB_OTG_GlobalTypeDef;

+

+

+/**

+  * @brief USB_OTG_device_Registers

+  */

+typedef struct

+{

+  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */

+  __IO uint32_t DCTL;            /*!< dev Control Register         804h */

+  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */

+  uint32_t Reserved0C;           /*!< Reserved                     80Ch */

+  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */

+  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */

+  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */

+  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */

+  uint32_t  Reserved20;          /*!< Reserved                     820h */

+  uint32_t Reserved9;            /*!< Reserved                     824h */

+  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */

+  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */

+  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */

+  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */

+  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */

+  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */

+  uint32_t Reserved40;           /*!< dedicated EP mask            840h */

+  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */

+  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */

+  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */

+} USB_OTG_DeviceTypeDef;

+

+

+/**

+  * @brief USB_OTG_IN_Endpoint-Specific_Register

+  */

+typedef struct

+{

+  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */

+  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */

+  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */

+  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */

+  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */

+  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */

+  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */

+  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */

+} USB_OTG_INEndpointTypeDef;

+

+

+/**

+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */

+  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */

+  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */

+  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */

+  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */

+  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */

+  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */

+} USB_OTG_OUTEndpointTypeDef;

+

+

+/**

+  * @brief USB_OTG_Host_Mode_Register_Structures

+  */

+typedef struct

+{

+  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */

+  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */

+  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */

+  uint32_t Reserved40C;           /*!< Reserved                             40Ch */

+  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */

+  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */

+  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */

+} USB_OTG_HostTypeDef;

+

+/**

+  * @brief USB_OTG_Host_Channel_Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */

+  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */

+  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */

+  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */

+  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */

+  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */

+  uint32_t Reserved[2];           /*!< Reserved                                      */

+} USB_OTG_HostChannelTypeDef;

+/**

+  * @}

+  */

+

+

+/** @addtogroup Peripheral_memory_map

+  * @{

+  */

+#define D1_ITCMRAM_BASE           (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM  */

+#define D1_ITCMICP_BASE           (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM         */

+#define D1_DTCMRAM_BASE           (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM                            */

+#define D1_AXIFLASH_BASE          (0x08000000UL) /*!< Base address of : (up to 128 KB) embedded FLASH memory accessible over AXI      */

+#define D1_AXIICP_BASE            (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI          */

+#define D1_AXISRAM_BASE           (0x24000000UL) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI                */

+

+#define D2_AXISRAM_BASE           (0x10000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI                */

+#define D2_AHBSRAM_BASE           (0x30000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge    */

+

+#define D3_BKPSRAM_BASE           (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge                                */

+#define D3_SRAM_BASE              (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge                               */

+

+#define PERIPH_BASE               (0x40000000UL) /*!< Base address of : AHB/APB Peripherals                                                   */

+#define QSPI_BASE                 (0x90000000UL) /*!< Base address of : QSPI memories  accessible over AXI                                    */

+

+#define FLASH_BANK1_BASE          (0x08000000UL) /*!< Base address of : (up to 128 KB) Flash Bank1 accessible over AXI                        */

+#define FLASH_BANK2_BASE          (0x08100000UL) /*!< For legacy only , Flash bank 2 not available on STM32H750xx value line          */

+#define FLASH_END                 (0x0801FFFFUL) /*!< FLASH end address                                                                       */

+

+/* Legacy define */

+#define FLASH_BASE                FLASH_BANK1_BASE

+

+/*!< Device electronic signature memory map */

+#define UID_BASE                  (0x1FF1E800UL)            /*!< Unique device ID register base address */

+#define FLASHSIZE_BASE            (0x1FF1E880UL)            /*!< FLASH Size register base address */

+

+

+/*!< Peripheral memory map */

+#define D2_APB1PERIPH_BASE        PERIPH_BASE

+#define D2_APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)

+#define D2_AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)

+#define D2_AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)

+

+#define D1_APB1PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)

+#define D1_AHB1PERIPH_BASE       (PERIPH_BASE + 0x12000000UL)

+

+#define D3_APB1PERIPH_BASE       (PERIPH_BASE + 0x18000000UL)

+#define D3_AHB1PERIPH_BASE       (PERIPH_BASE + 0x18020000UL)

+

+/*!< Legacy Peripheral memory map */

+#define APB1PERIPH_BASE        PERIPH_BASE

+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)

+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)

+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)

+

+

+/*!< D1_AHB1PERIPH peripherals */

+

+#define MDMA_BASE             (D1_AHB1PERIPH_BASE + 0x0000UL)

+#define DMA2D_BASE            (D1_AHB1PERIPH_BASE + 0x1000UL)

+#define JPGDEC_BASE           (D1_AHB1PERIPH_BASE + 0x3000UL)

+#define FLASH_R_BASE          (D1_AHB1PERIPH_BASE + 0x2000UL)

+#define FMC_R_BASE            (D1_AHB1PERIPH_BASE + 0x4000UL)

+#define QSPI_R_BASE           (D1_AHB1PERIPH_BASE + 0x5000UL)

+#define DLYB_QSPI_BASE        (D1_AHB1PERIPH_BASE + 0x6000UL)

+#define SDMMC1_BASE           (D1_AHB1PERIPH_BASE + 0x7000UL)

+#define DLYB_SDMMC1_BASE      (D1_AHB1PERIPH_BASE + 0x8000UL)

+#define RAMECC1_BASE          (D1_AHB1PERIPH_BASE + 0x9000UL)

+

+/*!< D2_AHB1PERIPH peripherals */

+

+#define DMA1_BASE               (D2_AHB1PERIPH_BASE + 0x0000UL)

+#define DMA2_BASE               (D2_AHB1PERIPH_BASE + 0x0400UL)

+#define DMAMUX1_BASE            (D2_AHB1PERIPH_BASE + 0x0800UL)

+#define ADC1_BASE               (D2_AHB1PERIPH_BASE + 0x2000UL)

+#define ADC2_BASE               (D2_AHB1PERIPH_BASE + 0x2100UL)

+#define ADC12_COMMON_BASE       (D2_AHB1PERIPH_BASE + 0x2300UL)

+#define ETH_BASE                (D2_AHB1PERIPH_BASE + 0x8000UL)

+#define ETH_MAC_BASE            (ETH_BASE)

+

+/*!< USB registers base address */

+#define USB1_OTG_HS_PERIPH_BASE              (0x40040000UL)

+#define USB2_OTG_FS_PERIPH_BASE              (0x40080000UL)

+#define USB_OTG_GLOBAL_BASE                  (0x000UL)

+#define USB_OTG_DEVICE_BASE                  (0x800UL)

+#define USB_OTG_IN_ENDPOINT_BASE             (0x900UL)

+#define USB_OTG_OUT_ENDPOINT_BASE            (0xB00UL)

+#define USB_OTG_EP_REG_SIZE                  (0x20UL)

+#define USB_OTG_HOST_BASE                    (0x400UL)

+#define USB_OTG_HOST_PORT_BASE               (0x440UL)

+#define USB_OTG_HOST_CHANNEL_BASE            (0x500UL)

+#define USB_OTG_HOST_CHANNEL_SIZE            (0x20UL)

+#define USB_OTG_PCGCCTL_BASE                 (0xE00UL)

+#define USB_OTG_FIFO_BASE                    (0x1000UL)

+#define USB_OTG_FIFO_SIZE                    (0x1000UL)

+

+/*!< D2_AHB2PERIPH peripherals */

+

+#define DCMI_BASE              (D2_AHB2PERIPH_BASE + 0x0000UL)

+#define CRYP_BASE              (D2_AHB2PERIPH_BASE + 0x1000UL)

+#define HASH_BASE              (D2_AHB2PERIPH_BASE + 0x1400UL)

+#define HASH_DIGEST_BASE       (D2_AHB2PERIPH_BASE + 0x1710UL)

+#define RNG_BASE               (D2_AHB2PERIPH_BASE + 0x1800UL)

+#define SDMMC2_BASE            (D2_AHB2PERIPH_BASE + 0x2400UL)

+#define DLYB_SDMMC2_BASE       (D2_AHB2PERIPH_BASE + 0x2800UL)

+#define RAMECC2_BASE           (D2_AHB2PERIPH_BASE + 0x3000UL)

+

+/*!< D3_AHB1PERIPH peripherals */

+#define GPIOA_BASE            (D3_AHB1PERIPH_BASE + 0x0000UL)

+#define GPIOB_BASE            (D3_AHB1PERIPH_BASE + 0x0400UL)

+#define GPIOC_BASE            (D3_AHB1PERIPH_BASE + 0x0800UL)

+#define GPIOD_BASE            (D3_AHB1PERIPH_BASE + 0x0C00UL)

+#define GPIOE_BASE            (D3_AHB1PERIPH_BASE + 0x1000UL)

+#define GPIOF_BASE            (D3_AHB1PERIPH_BASE + 0x1400UL)

+#define GPIOG_BASE            (D3_AHB1PERIPH_BASE + 0x1800UL)

+#define GPIOH_BASE            (D3_AHB1PERIPH_BASE + 0x1C00UL)

+#define GPIOI_BASE            (D3_AHB1PERIPH_BASE + 0x2000UL)

+#define GPIOJ_BASE            (D3_AHB1PERIPH_BASE + 0x2400UL)

+#define GPIOK_BASE            (D3_AHB1PERIPH_BASE + 0x2800UL)

+#define RCC_BASE              (D3_AHB1PERIPH_BASE + 0x4400UL)

+#define PWR_BASE              (D3_AHB1PERIPH_BASE + 0x4800UL)

+#define CRC_BASE              (D3_AHB1PERIPH_BASE + 0x4C00UL)

+#define BDMA_BASE             (D3_AHB1PERIPH_BASE + 0x5400UL)

+#define DMAMUX2_BASE          (D3_AHB1PERIPH_BASE + 0x5800UL)

+#define ADC3_BASE             (D3_AHB1PERIPH_BASE + 0x6000UL)

+#define ADC3_COMMON_BASE      (D3_AHB1PERIPH_BASE + 0x6300UL)

+#define HSEM_BASE             (D3_AHB1PERIPH_BASE + 0x6400UL)

+#define RAMECC3_BASE          (D3_AHB1PERIPH_BASE + 0x7000UL)

+

+/*!< D1_APB1PERIPH peripherals */

+#define LTDC_BASE             (D1_APB1PERIPH_BASE + 0x1000UL)

+#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84UL)

+#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104UL)

+#define WWDG1_BASE            (D1_APB1PERIPH_BASE + 0x3000UL)

+

+/*!< D2_APB1PERIPH peripherals */

+#define TIM2_BASE             (D2_APB1PERIPH_BASE + 0x0000UL)

+#define TIM3_BASE             (D2_APB1PERIPH_BASE + 0x0400UL)

+#define TIM4_BASE             (D2_APB1PERIPH_BASE + 0x0800UL)

+#define TIM5_BASE             (D2_APB1PERIPH_BASE + 0x0C00UL)

+#define TIM6_BASE             (D2_APB1PERIPH_BASE + 0x1000UL)

+#define TIM7_BASE             (D2_APB1PERIPH_BASE + 0x1400UL)

+#define TIM12_BASE            (D2_APB1PERIPH_BASE + 0x1800UL)

+#define TIM13_BASE            (D2_APB1PERIPH_BASE + 0x1C00UL)

+#define TIM14_BASE            (D2_APB1PERIPH_BASE + 0x2000UL)

+#define LPTIM1_BASE           (D2_APB1PERIPH_BASE + 0x2400UL)

+

+

+#define SPI2_BASE             (D2_APB1PERIPH_BASE + 0x3800UL)

+#define SPI3_BASE             (D2_APB1PERIPH_BASE + 0x3C00UL)

+#define SPDIFRX_BASE          (D2_APB1PERIPH_BASE + 0x4000UL)

+#define USART2_BASE           (D2_APB1PERIPH_BASE + 0x4400UL)

+#define USART3_BASE           (D2_APB1PERIPH_BASE + 0x4800UL)

+#define UART4_BASE            (D2_APB1PERIPH_BASE + 0x4C00UL)

+#define UART5_BASE            (D2_APB1PERIPH_BASE + 0x5000UL)

+#define I2C1_BASE             (D2_APB1PERIPH_BASE + 0x5400UL)

+#define I2C2_BASE             (D2_APB1PERIPH_BASE + 0x5800UL)

+#define I2C3_BASE             (D2_APB1PERIPH_BASE + 0x5C00UL)

+#define CEC_BASE              (D2_APB1PERIPH_BASE + 0x6C00UL)

+#define DAC1_BASE             (D2_APB1PERIPH_BASE + 0x7400UL)

+#define UART7_BASE            (D2_APB1PERIPH_BASE + 0x7800UL)

+#define UART8_BASE            (D2_APB1PERIPH_BASE + 0x7C00UL)

+#define CRS_BASE              (D2_APB1PERIPH_BASE + 0x8400UL)

+#define SWPMI1_BASE           (D2_APB1PERIPH_BASE + 0x8800UL)

+#define OPAMP_BASE            (D2_APB1PERIPH_BASE + 0x9000UL)

+#define OPAMP1_BASE           (D2_APB1PERIPH_BASE + 0x9000UL)

+#define OPAMP2_BASE           (D2_APB1PERIPH_BASE + 0x9010UL)

+#define MDIOS_BASE            (D2_APB1PERIPH_BASE + 0x9400UL)

+#define FDCAN1_BASE           (D2_APB1PERIPH_BASE + 0xA000UL)

+#define FDCAN2_BASE           (D2_APB1PERIPH_BASE + 0xA400UL)

+#define FDCAN_CCU_BASE        (D2_APB1PERIPH_BASE + 0xA800UL)

+#define SRAMCAN_BASE          (D2_APB1PERIPH_BASE + 0xAC00UL)

+

+/*!< D2_APB2PERIPH peripherals */

+

+#define TIM1_BASE             (D2_APB2PERIPH_BASE + 0x0000UL)

+#define TIM8_BASE             (D2_APB2PERIPH_BASE + 0x0400UL)

+#define USART1_BASE           (D2_APB2PERIPH_BASE + 0x1000UL)

+#define USART6_BASE           (D2_APB2PERIPH_BASE + 0x1400UL)

+#define SPI1_BASE             (D2_APB2PERIPH_BASE + 0x3000UL)

+#define SPI4_BASE             (D2_APB2PERIPH_BASE + 0x3400UL)

+#define TIM15_BASE            (D2_APB2PERIPH_BASE + 0x4000UL)

+#define TIM16_BASE            (D2_APB2PERIPH_BASE + 0x4400UL)

+#define TIM17_BASE            (D2_APB2PERIPH_BASE + 0x4800UL)

+#define SPI5_BASE             (D2_APB2PERIPH_BASE + 0x5000UL)

+#define SAI1_BASE             (D2_APB2PERIPH_BASE + 0x5800UL)

+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)

+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)

+#define SAI2_BASE             (D2_APB2PERIPH_BASE + 0x5C00UL)

+#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004UL)

+#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024UL)

+#define SAI3_BASE             (D2_APB2PERIPH_BASE + 0x6000UL)

+#define SAI3_Block_A_BASE     (SAI3_BASE + 0x004UL)

+#define SAI3_Block_B_BASE     (SAI3_BASE + 0x024UL)

+#define DFSDM1_BASE           (D2_APB2PERIPH_BASE + 0x7000UL)

+#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00UL)

+#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20UL)

+#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40UL)

+#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60UL)

+#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80UL)

+#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0UL)

+#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0UL)

+#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0UL)

+#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)

+#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)

+#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)

+#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)

+#define HRTIM1_BASE           (D2_APB2PERIPH_BASE + 0x7400UL)

+#define HRTIM1_TIMA_BASE      (HRTIM1_BASE + 0x00000080UL)

+#define HRTIM1_TIMB_BASE      (HRTIM1_BASE + 0x00000100UL)

+#define HRTIM1_TIMC_BASE      (HRTIM1_BASE + 0x00000180UL)

+#define HRTIM1_TIMD_BASE      (HRTIM1_BASE + 0x00000200UL)

+#define HRTIM1_TIME_BASE      (HRTIM1_BASE + 0x00000280UL)

+#define HRTIM1_COMMON_BASE    (HRTIM1_BASE + 0x00000380UL)

+

+

+/*!< D3_APB1PERIPH peripherals */

+#define EXTI_BASE             (D3_APB1PERIPH_BASE + 0x0000UL)

+#define EXTI_D1_BASE          (EXTI_BASE + 0x0080UL)

+#define EXTI_D2_BASE          (EXTI_BASE + 0x00C0UL)

+#define SYSCFG_BASE           (D3_APB1PERIPH_BASE + 0x0400UL)

+#define LPUART1_BASE          (D3_APB1PERIPH_BASE + 0x0C00UL)

+#define SPI6_BASE             (D3_APB1PERIPH_BASE + 0x1400UL)

+#define I2C4_BASE             (D3_APB1PERIPH_BASE + 0x1C00UL)

+#define LPTIM2_BASE           (D3_APB1PERIPH_BASE + 0x2400UL)

+#define LPTIM3_BASE           (D3_APB1PERIPH_BASE + 0x2800UL)

+#define LPTIM4_BASE           (D3_APB1PERIPH_BASE + 0x2C00UL)

+#define LPTIM5_BASE           (D3_APB1PERIPH_BASE + 0x3000UL)

+#define COMP12_BASE           (D3_APB1PERIPH_BASE + 0x3800UL)

+#define COMP1_BASE            (COMP12_BASE + 0x0CUL)

+#define COMP2_BASE            (COMP12_BASE + 0x10UL)

+#define VREFBUF_BASE          (D3_APB1PERIPH_BASE + 0x3C00UL)

+#define RTC_BASE              (D3_APB1PERIPH_BASE + 0x4000UL)

+#define IWDG1_BASE            (D3_APB1PERIPH_BASE + 0x4800UL)

+

+

+#define SAI4_BASE             (D3_APB1PERIPH_BASE + 0x5400UL)

+#define SAI4_Block_A_BASE     (SAI4_BASE + 0x004UL)

+#define SAI4_Block_B_BASE     (SAI4_BASE + 0x024UL)

+

+

+

+

+#define BDMA_Channel0_BASE    (BDMA_BASE + 0x0008UL)

+#define BDMA_Channel1_BASE    (BDMA_BASE + 0x001CUL)

+#define BDMA_Channel2_BASE    (BDMA_BASE + 0x0030UL)

+#define BDMA_Channel3_BASE    (BDMA_BASE + 0x0044UL)

+#define BDMA_Channel4_BASE    (BDMA_BASE + 0x0058UL)

+#define BDMA_Channel5_BASE    (BDMA_BASE + 0x006CUL)

+#define BDMA_Channel6_BASE    (BDMA_BASE + 0x0080UL)

+#define BDMA_Channel7_BASE    (BDMA_BASE + 0x0094UL)

+

+#define DMAMUX2_Channel0_BASE    (DMAMUX2_BASE)

+#define DMAMUX2_Channel1_BASE    (DMAMUX2_BASE + 0x0004UL)

+#define DMAMUX2_Channel2_BASE    (DMAMUX2_BASE + 0x0008UL)

+#define DMAMUX2_Channel3_BASE    (DMAMUX2_BASE + 0x000CUL)

+#define DMAMUX2_Channel4_BASE    (DMAMUX2_BASE + 0x0010UL)

+#define DMAMUX2_Channel5_BASE    (DMAMUX2_BASE + 0x0014UL)

+#define DMAMUX2_Channel6_BASE    (DMAMUX2_BASE + 0x0018UL)

+#define DMAMUX2_Channel7_BASE    (DMAMUX2_BASE + 0x001CUL)

+

+#define DMAMUX2_RequestGenerator0_BASE  (DMAMUX2_BASE + 0x0100UL)

+#define DMAMUX2_RequestGenerator1_BASE  (DMAMUX2_BASE + 0x0104UL)

+#define DMAMUX2_RequestGenerator2_BASE  (DMAMUX2_BASE + 0x0108UL)

+#define DMAMUX2_RequestGenerator3_BASE  (DMAMUX2_BASE + 0x010CUL)

+#define DMAMUX2_RequestGenerator4_BASE  (DMAMUX2_BASE + 0x0110UL)

+#define DMAMUX2_RequestGenerator5_BASE  (DMAMUX2_BASE + 0x0114UL)

+#define DMAMUX2_RequestGenerator6_BASE  (DMAMUX2_BASE + 0x0118UL)

+#define DMAMUX2_RequestGenerator7_BASE  (DMAMUX2_BASE + 0x011CUL)

+

+#define DMAMUX2_ChannelStatus_BASE      (DMAMUX2_BASE + 0x0080UL)

+#define DMAMUX2_RequestGenStatus_BASE   (DMAMUX2_BASE + 0x0140UL)

+

+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)

+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)

+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)

+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)

+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)

+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)

+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)

+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)

+

+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)

+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)

+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)

+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)

+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)

+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)

+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)

+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)

+

+#define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)

+#define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)

+#define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)

+#define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)

+#define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)

+#define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)

+#define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0018UL)

+#define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x001CUL)

+#define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0020UL)

+#define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x0024UL)

+#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)

+#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)

+#define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)

+#define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)

+#define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)

+#define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)

+

+#define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)

+#define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)

+#define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)

+#define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)

+#define DMAMUX1_RequestGenerator4_BASE  (DMAMUX1_BASE + 0x0110UL)

+#define DMAMUX1_RequestGenerator5_BASE  (DMAMUX1_BASE + 0x0114UL)

+#define DMAMUX1_RequestGenerator6_BASE  (DMAMUX1_BASE + 0x0118UL)

+#define DMAMUX1_RequestGenerator7_BASE  (DMAMUX1_BASE + 0x011CUL)

+

+#define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)

+#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)

+

+/*!< FMC Banks registers base  address */

+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)

+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)

+#define FMC_Bank2_R_BASE      (FMC_R_BASE + 0x0060UL)

+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)

+#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)

+

+/* Debug MCU registers base address */

+#define DBGMCU_BASE           (0x5C001000UL)

+

+#define MDMA_Channel0_BASE    (MDMA_BASE + 0x00000040UL)

+#define MDMA_Channel1_BASE    (MDMA_BASE + 0x00000080UL)

+#define MDMA_Channel2_BASE    (MDMA_BASE + 0x000000C0UL)

+#define MDMA_Channel3_BASE    (MDMA_BASE + 0x00000100UL)

+#define MDMA_Channel4_BASE    (MDMA_BASE + 0x00000140UL)

+#define MDMA_Channel5_BASE    (MDMA_BASE + 0x00000180UL)

+#define MDMA_Channel6_BASE    (MDMA_BASE + 0x000001C0UL)

+#define MDMA_Channel7_BASE    (MDMA_BASE + 0x00000200UL)

+#define MDMA_Channel8_BASE    (MDMA_BASE + 0x00000240UL)

+#define MDMA_Channel9_BASE    (MDMA_BASE + 0x00000280UL)

+#define MDMA_Channel10_BASE   (MDMA_BASE + 0x000002C0UL)

+#define MDMA_Channel11_BASE   (MDMA_BASE + 0x00000300UL)

+#define MDMA_Channel12_BASE   (MDMA_BASE + 0x00000340UL)

+#define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)

+#define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)

+#define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)

+

+#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)

+#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)

+#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)

+#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)

+#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)

+

+#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)

+#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)

+#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)

+#define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL)

+#define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL)

+

+#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)

+#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)

+

+

+/**

+  * @}

+  */

+

+/** @addtogroup Peripheral_declaration

+  * @{

+  */

+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)

+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)

+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)

+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)

+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)

+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)

+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)

+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)

+#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)

+#define RTC                 ((RTC_TypeDef *) RTC_BASE)

+#define WWDG1               ((WWDG_TypeDef *) WWDG1_BASE)

+

+

+#define IWDG1               ((IWDG_TypeDef *) IWDG1_BASE)

+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)

+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)

+#define SPI4                ((SPI_TypeDef *) SPI4_BASE)

+#define SPI5                ((SPI_TypeDef *) SPI5_BASE)

+#define SPI6                ((SPI_TypeDef *) SPI6_BASE)

+#define USART2              ((USART_TypeDef *) USART2_BASE)

+#define USART3              ((USART_TypeDef *) USART3_BASE)

+#define USART6              ((USART_TypeDef *) USART6_BASE)

+#define UART7               ((USART_TypeDef *) UART7_BASE)

+#define UART8               ((USART_TypeDef *) UART8_BASE)

+#define CRS                 ((CRS_TypeDef *) CRS_BASE)

+#define UART4               ((USART_TypeDef *) UART4_BASE)

+#define UART5               ((USART_TypeDef *) UART5_BASE)

+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)

+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)

+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)

+#define I2C4                ((I2C_TypeDef *) I2C4_BASE)

+#define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

+#define FDCAN2              ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

+#define FDCAN_CCU           ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

+#define CEC                 ((CEC_TypeDef *) CEC_BASE)

+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)

+#define PWR                 ((PWR_TypeDef *) PWR_BASE)

+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)

+#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)

+#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)

+#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)

+#define LPTIM3              ((LPTIM_TypeDef *) LPTIM3_BASE)

+#define LPTIM4              ((LPTIM_TypeDef *) LPTIM4_BASE)

+#define LPTIM5              ((LPTIM_TypeDef *) LPTIM5_BASE)

+

+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)

+#define COMP12              ((COMPOPT_TypeDef *) COMP12_BASE)

+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)

+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)

+#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)

+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)

+#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)

+#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)

+

+

+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)

+#define EXTI_D1             ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

+#define EXTI_D2             ((EXTI_Core_TypeDef *) EXTI_D2_BASE)

+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)

+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)

+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)

+#define USART1              ((USART_TypeDef *) USART1_BASE)

+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)

+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)

+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)

+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)

+#define HRTIM1              ((HRTIM_TypeDef *) HRTIM1_BASE)

+#define HRTIM1_TIMA         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)

+#define HRTIM1_TIMB         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)

+#define HRTIM1_TIMC         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)

+#define HRTIM1_TIMD         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)

+#define HRTIM1_TIME         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)

+#define HRTIM1_COMMON       ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)

+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)

+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

+#define SAI2                ((SAI_TypeDef *) SAI2_BASE)

+#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)

+#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)

+#define SAI3                ((SAI_TypeDef *) SAI3_BASE)

+#define SAI3_Block_A        ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)

+#define SAI3_Block_B        ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)

+#define SAI4                ((SAI_TypeDef *) SAI4_BASE)

+#define SAI4_Block_A        ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)

+#define SAI4_Block_B        ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)

+

+#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

+#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

+#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

+#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

+#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

+#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

+#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

+#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

+#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

+#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

+#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

+#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

+#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

+#define DMA2D               ((DMA2D_TypeDef *) DMA2D_BASE)

+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)

+#define RCC                 ((RCC_TypeDef *) RCC_BASE)

+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)

+#define CRC                 ((CRC_TypeDef *) CRC_BASE)

+

+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)

+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)

+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)

+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)

+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)

+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)

+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)

+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)

+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)

+#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)

+#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)

+

+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)

+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)

+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)

+#define ADC3_COMMON         ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)

+#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

+

+#define CRYP                ((CRYP_TypeDef *) CRYP_BASE)

+#define HASH                ((HASH_TypeDef *) HASH_BASE)

+#define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)

+#define RNG                 ((RNG_TypeDef *) RNG_BASE)

+#define SDMMC2              ((SDMMC_TypeDef *) SDMMC2_BASE)

+#define DLYB_SDMMC2         ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

+

+#define BDMA                ((BDMA_TypeDef *) BDMA_BASE)

+#define BDMA_Channel0       ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)

+#define BDMA_Channel1       ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)

+#define BDMA_Channel2       ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)

+#define BDMA_Channel3       ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)

+#define BDMA_Channel4       ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)

+#define BDMA_Channel5       ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)

+#define BDMA_Channel6       ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)

+#define BDMA_Channel7       ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)

+

+#define RAMECC1              ((RAMECC_TypeDef *)RAMECC1_BASE)

+#define RAMECC1_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)

+#define RAMECC1_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)

+#define RAMECC1_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)

+#define RAMECC1_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)

+#define RAMECC1_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)

+

+#define RAMECC2              ((RAMECC_TypeDef *)RAMECC2_BASE)

+#define RAMECC2_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)

+#define RAMECC2_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)

+#define RAMECC2_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)

+#define RAMECC2_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)

+#define RAMECC2_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)

+

+#define RAMECC3              ((RAMECC_TypeDef *)RAMECC3_BASE)

+#define RAMECC3_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)

+#define RAMECC3_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)

+

+#define DMAMUX2                ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

+#define DMAMUX2_Channel0       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

+#define DMAMUX2_Channel1       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

+#define DMAMUX2_Channel2       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

+#define DMAMUX2_Channel3       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

+#define DMAMUX2_Channel4       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

+#define DMAMUX2_Channel5       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

+#define DMAMUX2_Channel6       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

+#define DMAMUX2_Channel7       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

+

+

+#define DMAMUX2_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

+#define DMAMUX2_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

+#define DMAMUX2_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

+#define DMAMUX2_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

+#define DMAMUX2_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

+#define DMAMUX2_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

+#define DMAMUX2_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

+#define DMAMUX2_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

+

+#define DMAMUX2_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

+#define DMAMUX2_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

+

+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)

+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

+

+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)

+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

+

+

+#define DMAMUX1              ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

+#define DMAMUX1_Channel0     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

+#define DMAMUX1_Channel1     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

+#define DMAMUX1_Channel2     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

+#define DMAMUX1_Channel3     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

+#define DMAMUX1_Channel4     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

+#define DMAMUX1_Channel5     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

+#define DMAMUX1_Channel6     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

+#define DMAMUX1_Channel7     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

+#define DMAMUX1_Channel8     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

+#define DMAMUX1_Channel9     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

+#define DMAMUX1_Channel10    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

+#define DMAMUX1_Channel11    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

+#define DMAMUX1_Channel12    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

+#define DMAMUX1_Channel13    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

+#define DMAMUX1_Channel14    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

+#define DMAMUX1_Channel15    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

+

+#define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

+#define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

+#define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

+#define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

+#define DMAMUX1_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

+#define DMAMUX1_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

+#define DMAMUX1_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

+#define DMAMUX1_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

+

+#define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *)    DMAMUX1_ChannelStatus_BASE)

+#define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

+

+

+#define FMC_Bank1_R           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

+#define FMC_Bank1E_R          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

+#define FMC_Bank2_R           ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

+#define FMC_Bank3_R           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

+#define FMC_Bank5_6_R         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

+

+

+#define QUADSPI               ((QUADSPI_TypeDef *) QSPI_R_BASE)

+#define DLYB_QUADSPI          ((DLYB_TypeDef *) DLYB_QSPI_BASE)

+#define SDMMC1                ((SDMMC_TypeDef *) SDMMC1_BASE)

+#define DLYB_SDMMC1           ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

+

+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)

+

+#define JPEG                ((JPEG_TypeDef *) JPGDEC_BASE)

+#define HSEM                ((HSEM_TypeDef *) HSEM_BASE)

+#define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

+

+#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)

+#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

+#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

+

+#define MDIOS               ((MDIOS_TypeDef *) MDIOS_BASE)

+

+#define ETH                 ((ETH_TypeDef *)ETH_BASE)

+#define MDMA                ((MDMA_TypeDef *)MDMA_BASE)

+#define MDMA_Channel0       ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

+#define MDMA_Channel1       ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

+#define MDMA_Channel2       ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

+#define MDMA_Channel3       ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

+#define MDMA_Channel4       ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

+#define MDMA_Channel5       ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

+#define MDMA_Channel6       ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

+#define MDMA_Channel7       ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

+#define MDMA_Channel8       ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

+#define MDMA_Channel9       ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

+#define MDMA_Channel10      ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

+#define MDMA_Channel11      ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

+#define MDMA_Channel12      ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

+#define MDMA_Channel13      ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

+#define MDMA_Channel14      ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

+#define MDMA_Channel15      ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

+

+

+#define USB1_OTG_HS         ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

+#define USB2_OTG_FS         ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)

+

+/* Legacy defines */

+#define USB_OTG_HS                   USB1_OTG_HS

+#define USB_OTG_HS_PERIPH_BASE       USB1_OTG_HS_PERIPH_BASE

+#define USB_OTG_FS                   USB2_OTG_FS

+#define USB_OTG_FS_PERIPH_BASE       USB2_OTG_FS_PERIPH_BASE

+

+/**

+  * @}

+  */

+

+/** @addtogroup Exported_constants

+  * @{

+  */

+

+  /** @addtogroup Peripheral_Registers_Bits_Definition

+  * @{

+  */

+

+/******************************************************************************/

+/*                         Peripheral Registers_Bits_Definition               */

+/******************************************************************************/

+

+/******************************************************************************/

+/*                                                                            */

+/*                        Analog to Digital Converter                         */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  ADC VERSION  ********************************/

+#define ADC_VER_V5_X

+/********************  Bit definition for ADC_ISR register  ********************/

+#define ADC_ISR_ADRDY_Pos                 (0U)

+#define ADC_ISR_ADRDY_Msk                 (0x1UL << ADC_ISR_ADRDY_Pos)         /*!< 0x00000001 */

+#define ADC_ISR_ADRDY                     ADC_ISR_ADRDY_Msk                    /*!< ADC Ready (ADRDY) flag  */

+#define ADC_ISR_EOSMP_Pos                 (1U)

+#define ADC_ISR_EOSMP_Msk                 (0x1UL << ADC_ISR_EOSMP_Pos)         /*!< 0x00000002 */

+#define ADC_ISR_EOSMP                     ADC_ISR_EOSMP_Msk                    /*!< ADC End of Sampling flag */

+#define ADC_ISR_EOC_Pos                   (2U)

+#define ADC_ISR_EOC_Msk                   (0x1UL << ADC_ISR_EOC_Pos)           /*!< 0x00000004 */

+#define ADC_ISR_EOC                       ADC_ISR_EOC_Msk                      /*!< ADC End of Regular Conversion flag */

+#define ADC_ISR_EOS_Pos                   (3U)

+#define ADC_ISR_EOS_Msk                   (0x1UL << ADC_ISR_EOS_Pos)           /*!< 0x00000008 */

+#define ADC_ISR_EOS                       ADC_ISR_EOS_Msk                      /*!< ADC End of Regular sequence of Conversions flag */

+#define ADC_ISR_OVR_Pos                   (4U)

+#define ADC_ISR_OVR_Msk                   (0x1UL << ADC_ISR_OVR_Pos)           /*!< 0x00000010 */

+#define ADC_ISR_OVR                       ADC_ISR_OVR_Msk                      /*!< ADC overrun flag */

+#define ADC_ISR_JEOC_Pos                  (5U)

+#define ADC_ISR_JEOC_Msk                  (0x1UL << ADC_ISR_JEOC_Pos)          /*!< 0x00000020 */

+#define ADC_ISR_JEOC                      ADC_ISR_JEOC_Msk                     /*!< ADC End of Injected Conversion flag */

+#define ADC_ISR_JEOS_Pos                  (6U)

+#define ADC_ISR_JEOS_Msk                  (0x1UL << ADC_ISR_JEOS_Pos)          /*!< 0x00000040 */

+#define ADC_ISR_JEOS                      ADC_ISR_JEOS_Msk                     /*!< ADC End of Injected sequence of Conversions flag */

+#define ADC_ISR_AWD1_Pos                  (7U)

+#define ADC_ISR_AWD1_Msk                  (0x1UL << ADC_ISR_AWD1_Pos)          /*!< 0x00000080 */

+#define ADC_ISR_AWD1                      ADC_ISR_AWD1_Msk                     /*!< ADC Analog watchdog 1 flag */

+#define ADC_ISR_AWD2_Pos                  (8U)

+#define ADC_ISR_AWD2_Msk                  (0x1UL << ADC_ISR_AWD2_Pos)          /*!< 0x00000100 */

+#define ADC_ISR_AWD2                      ADC_ISR_AWD2_Msk                     /*!< ADC Analog watchdog 2 flag */

+#define ADC_ISR_AWD3_Pos                  (9U)

+#define ADC_ISR_AWD3_Msk                  (0x1UL << ADC_ISR_AWD3_Pos)          /*!< 0x00000200 */

+#define ADC_ISR_AWD3                      ADC_ISR_AWD3_Msk                     /*!< ADC Analog watchdog 3 flag */

+#define ADC_ISR_JQOVF_Pos                 (10U)

+#define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */

+#define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */

+

+/********************  Bit definition for ADC_IER register  ********************/

+#define ADC_IER_ADRDYIE_Pos               (0U)

+#define ADC_IER_ADRDYIE_Msk               (0x1UL << ADC_IER_ADRDYIE_Pos)       /*!< 0x00000001 */

+#define ADC_IER_ADRDYIE                   ADC_IER_ADRDYIE_Msk                  /*!< ADC Ready (ADRDY) interrupt source */

+#define ADC_IER_EOSMPIE_Pos               (1U)

+#define ADC_IER_EOSMPIE_Msk               (0x1UL << ADC_IER_EOSMPIE_Pos)       /*!< 0x00000002 */

+#define ADC_IER_EOSMPIE                   ADC_IER_EOSMPIE_Msk                  /*!< ADC End of Sampling interrupt source */

+#define ADC_IER_EOCIE_Pos                 (2U)

+#define ADC_IER_EOCIE_Msk                 (0x1UL << ADC_IER_EOCIE_Pos)         /*!< 0x00000004 */

+#define ADC_IER_EOCIE                     ADC_IER_EOCIE_Msk                    /*!< ADC End of Regular Conversion interrupt source */

+#define ADC_IER_EOSIE_Pos                 (3U)

+#define ADC_IER_EOSIE_Msk                 (0x1UL << ADC_IER_EOSIE_Pos)         /*!< 0x00000008 */

+#define ADC_IER_EOSIE                     ADC_IER_EOSIE_Msk                    /*!< ADC End of Regular sequence of Conversions interrupt source */

+#define ADC_IER_OVRIE_Pos                 (4U)

+#define ADC_IER_OVRIE_Msk                 (0x1UL << ADC_IER_OVRIE_Pos)         /*!< 0x00000010 */

+#define ADC_IER_OVRIE                     ADC_IER_OVRIE_Msk                    /*!< ADC overrun interrupt source */

+#define ADC_IER_JEOCIE_Pos                (5U)

+#define ADC_IER_JEOCIE_Msk                (0x1UL << ADC_IER_JEOCIE_Pos)        /*!< 0x00000020 */

+#define ADC_IER_JEOCIE                    ADC_IER_JEOCIE_Msk                   /*!< ADC End of Injected Conversion interrupt source */

+#define ADC_IER_JEOSIE_Pos                (6U)

+#define ADC_IER_JEOSIE_Msk                (0x1UL << ADC_IER_JEOSIE_Pos)        /*!< 0x00000040 */

+#define ADC_IER_JEOSIE                    ADC_IER_JEOSIE_Msk                   /*!< ADC End of Injected sequence of Conversions interrupt source */

+#define ADC_IER_AWD1IE_Pos                (7U)

+#define ADC_IER_AWD1IE_Msk                (0x1UL << ADC_IER_AWD1IE_Pos)        /*!< 0x00000080 */

+#define ADC_IER_AWD1IE                    ADC_IER_AWD1IE_Msk                   /*!< ADC Analog watchdog 1 interrupt source */

+#define ADC_IER_AWD2IE_Pos                (8U)

+#define ADC_IER_AWD2IE_Msk                (0x1UL << ADC_IER_AWD2IE_Pos)        /*!< 0x00000100 */

+#define ADC_IER_AWD2IE                    ADC_IER_AWD2IE_Msk                   /*!< ADC Analog watchdog 2 interrupt source */

+#define ADC_IER_AWD3IE_Pos                (9U)

+#define ADC_IER_AWD3IE_Msk                (0x1UL << ADC_IER_AWD3IE_Pos)        /*!< 0x00000200 */

+#define ADC_IER_AWD3IE                    ADC_IER_AWD3IE_Msk                   /*!< ADC Analog watchdog 3 interrupt source */

+#define ADC_IER_JQOVFIE_Pos               (10U)

+#define ADC_IER_JQOVFIE_Msk               (0x1UL << ADC_IER_JQOVFIE_Pos)       /*!< 0x00000400 */

+#define ADC_IER_JQOVFIE                   ADC_IER_JQOVFIE_Msk                  /*!< ADC Injected Context Queue Overflow interrupt source */

+

+/********************  Bit definition for ADC_CR register  ********************/

+#define ADC_CR_ADEN_Pos                   (0U)

+#define ADC_CR_ADEN_Msk                   (0x1UL << ADC_CR_ADEN_Pos)           /*!< 0x00000001 */

+#define ADC_CR_ADEN                       ADC_CR_ADEN_Msk                      /*!< ADC Enable control */

+#define ADC_CR_ADDIS_Pos                  (1U)

+#define ADC_CR_ADDIS_Msk                  (0x1UL << ADC_CR_ADDIS_Pos)          /*!< 0x00000002 */

+#define ADC_CR_ADDIS                      ADC_CR_ADDIS_Msk                     /*!< ADC Disable command */

+#define ADC_CR_ADSTART_Pos                (2U)

+#define ADC_CR_ADSTART_Msk                (0x1UL << ADC_CR_ADSTART_Pos)        /*!< 0x00000004 */

+#define ADC_CR_ADSTART                    ADC_CR_ADSTART_Msk                   /*!< ADC Start of Regular conversion */

+#define ADC_CR_JADSTART_Pos               (3U)

+#define ADC_CR_JADSTART_Msk               (0x1UL << ADC_CR_JADSTART_Pos)       /*!< 0x00000008 */

+#define ADC_CR_JADSTART                   ADC_CR_JADSTART_Msk                  /*!< ADC Start of injected conversion */

+#define ADC_CR_ADSTP_Pos                  (4U)

+#define ADC_CR_ADSTP_Msk                  (0x1UL << ADC_CR_ADSTP_Pos)          /*!< 0x00000010 */

+#define ADC_CR_ADSTP                      ADC_CR_ADSTP_Msk                     /*!< ADC Stop of Regular conversion */

+#define ADC_CR_JADSTP_Pos                 (5U)

+#define ADC_CR_JADSTP_Msk                 (0x1UL << ADC_CR_JADSTP_Pos)         /*!< 0x00000020 */

+#define ADC_CR_JADSTP                     ADC_CR_JADSTP_Msk                    /*!< ADC Stop of injected conversion */

+#define ADC_CR_BOOST_Pos                  (8U)

+#define ADC_CR_BOOST_Msk                  (0x3UL << ADC_CR_BOOST_Pos)          /*!< 0x00000300 */

+#define ADC_CR_BOOST                      ADC_CR_BOOST_Msk                     /*!< ADC Boost Mode configuration */

+#define ADC_CR_BOOST_0                    (0x1UL << ADC_CR_BOOST_Pos)           /*!< 0x00000100 */

+#define ADC_CR_BOOST_1                    (0x2UL << ADC_CR_BOOST_Pos)           /*!< 0x00000200 */

+#define ADC_CR_ADCALLIN_Pos               (16U)

+#define ADC_CR_ADCALLIN_Msk               (0x1UL << ADC_CR_ADCALLIN_Pos)       /*!< 0x00010000 */

+#define ADC_CR_ADCALLIN                   ADC_CR_ADCALLIN_Msk                  /*!< ADC Linearity calibration */

+#define ADC_CR_LINCALRDYW1_Pos            (22U)

+#define ADC_CR_LINCALRDYW1_Msk            (0x1UL << ADC_CR_LINCALRDYW1_Pos)    /*!< 0x00400000 */

+#define ADC_CR_LINCALRDYW1                ADC_CR_LINCALRDYW1_Msk               /*!< ADC Linearity calibration ready Word 1 */

+#define ADC_CR_LINCALRDYW2_Pos            (23U)

+#define ADC_CR_LINCALRDYW2_Msk            (0x1UL << ADC_CR_LINCALRDYW2_Pos)    /*!< 0x00800000 */

+#define ADC_CR_LINCALRDYW2                ADC_CR_LINCALRDYW2_Msk               /*!< ADC Linearity calibration ready Word 2 */

+#define ADC_CR_LINCALRDYW3_Pos            (24U)

+#define ADC_CR_LINCALRDYW3_Msk            (0x1UL << ADC_CR_LINCALRDYW3_Pos)    /*!< 0x01000000 */

+#define ADC_CR_LINCALRDYW3                ADC_CR_LINCALRDYW3_Msk               /*!< ADC Linearity calibration ready Word 3 */

+#define ADC_CR_LINCALRDYW4_Pos            (25U)

+#define ADC_CR_LINCALRDYW4_Msk            (0x1UL << ADC_CR_LINCALRDYW4_Pos)    /*!< 0x02000000 */

+#define ADC_CR_LINCALRDYW4                ADC_CR_LINCALRDYW4_Msk               /*!< ADC Linearity calibration ready Word 4 */

+#define ADC_CR_LINCALRDYW5_Pos            (26U)

+#define ADC_CR_LINCALRDYW5_Msk            (0x1UL << ADC_CR_LINCALRDYW5_Pos)    /*!< 0x04000000 */

+#define ADC_CR_LINCALRDYW5                ADC_CR_LINCALRDYW5_Msk               /*!< ADC Linearity calibration ready Word 5 */

+#define ADC_CR_LINCALRDYW6_Pos            (27U)

+#define ADC_CR_LINCALRDYW6_Msk            (0x1UL << ADC_CR_LINCALRDYW6_Pos)    /*!< 0x08000000 */

+#define ADC_CR_LINCALRDYW6                ADC_CR_LINCALRDYW6_Msk               /*!< ADC Linearity calibration ready Word 6 */

+#define ADC_CR_ADVREGEN_Pos               (28U)

+#define ADC_CR_ADVREGEN_Msk               (0x1UL << ADC_CR_ADVREGEN_Pos)       /*!< 0x10000000 */

+#define ADC_CR_ADVREGEN                   ADC_CR_ADVREGEN_Msk                  /*!< ADC Voltage regulator Enable */

+#define ADC_CR_DEEPPWD_Pos                (29U)

+#define ADC_CR_DEEPPWD_Msk                (0x1UL << ADC_CR_DEEPPWD_Pos)        /*!< 0x20000000 */

+#define ADC_CR_DEEPPWD                    ADC_CR_DEEPPWD_Msk                   /*!< ADC Deep power down Enable */

+#define ADC_CR_ADCALDIF_Pos               (30U)

+#define ADC_CR_ADCALDIF_Msk               (0x1UL << ADC_CR_ADCALDIF_Pos)       /*!< 0x40000000 */

+#define ADC_CR_ADCALDIF                   ADC_CR_ADCALDIF_Msk                  /*!< ADC Differential Mode for calibration */

+#define ADC_CR_ADCAL_Pos                  (31U)

+#define ADC_CR_ADCAL_Msk                  (0x1UL << ADC_CR_ADCAL_Pos)          /*!< 0x80000000 */

+#define ADC_CR_ADCAL                      ADC_CR_ADCAL_Msk                     /*!< ADC Calibration */

+

+/********************  Bit definition for ADC_CFGR register  ********************/

+#define ADC_CFGR_DMNGT_Pos                (0U)

+#define ADC_CFGR_DMNGT_Msk                (0x3UL << ADC_CFGR_DMNGT_Pos)        /*!< 0x00000003 */

+#define ADC_CFGR_DMNGT                    ADC_CFGR_DMNGT_Msk                   /*!< ADC Data Management configuration */

+#define ADC_CFGR_DMNGT_0                  (0x1UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000001 */

+#define ADC_CFGR_DMNGT_1                  (0x2UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000002 */

+

+#define ADC_CFGR_RES_Pos                  (2U)

+#define ADC_CFGR_RES_Msk                  (0x7UL << ADC_CFGR_RES_Pos)          /*!< 0x0000001C */

+#define ADC_CFGR_RES                      ADC_CFGR_RES_Msk                     /*!< ADC Data resolution */

+#define ADC_CFGR_RES_0                    (0x1UL << ADC_CFGR_RES_Pos)           /*!< 0x00000004 */

+#define ADC_CFGR_RES_1                    (0x2UL << ADC_CFGR_RES_Pos)           /*!< 0x00000008 */

+#define ADC_CFGR_RES_2                    (0x4UL << ADC_CFGR_RES_Pos)           /*!< 0x00000010 */

+

+#define ADC_CFGR_EXTSEL_Pos               (5U)

+#define ADC_CFGR_EXTSEL_Msk               (0x1FUL << ADC_CFGR_EXTSEL_Pos)      /*!< 0x000003E0 */

+#define ADC_CFGR_EXTSEL                   ADC_CFGR_EXTSEL_Msk                  /*!< ADC External trigger selection for regular group */

+#define ADC_CFGR_EXTSEL_0                 (0x01UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000020 */

+#define ADC_CFGR_EXTSEL_1                 (0x02UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000040 */

+#define ADC_CFGR_EXTSEL_2                 (0x04UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000080 */

+#define ADC_CFGR_EXTSEL_3                 (0x08UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000100 */

+#define ADC_CFGR_EXTSEL_4                 (0x10UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000200 */

+

+#define ADC_CFGR_EXTEN_Pos                (10U)

+#define ADC_CFGR_EXTEN_Msk                (0x3UL << ADC_CFGR_EXTEN_Pos)        /*!< 0x00000C00 */

+#define ADC_CFGR_EXTEN                    ADC_CFGR_EXTEN_Msk                   /*!< ADC External trigger enable and polarity selection for regular channels */

+#define ADC_CFGR_EXTEN_0                  (0x1UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000400 */

+#define ADC_CFGR_EXTEN_1                  (0x2UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000800 */

+

+#define ADC_CFGR_OVRMOD_Pos               (12U)

+#define ADC_CFGR_OVRMOD_Msk               (0x1UL << ADC_CFGR_OVRMOD_Pos)       /*!< 0x00001000 */

+#define ADC_CFGR_OVRMOD                   ADC_CFGR_OVRMOD_Msk                  /*!< ADC overrun mode */

+#define ADC_CFGR_CONT_Pos                 (13U)

+#define ADC_CFGR_CONT_Msk                 (0x1UL << ADC_CFGR_CONT_Pos)         /*!< 0x00002000 */

+#define ADC_CFGR_CONT                     ADC_CFGR_CONT_Msk                    /*!< ADC Single/continuous conversion mode for regular conversion */

+#define ADC_CFGR_AUTDLY_Pos               (14U)

+#define ADC_CFGR_AUTDLY_Msk               (0x1UL << ADC_CFGR_AUTDLY_Pos)       /*!< 0x00004000 */

+#define ADC_CFGR_AUTDLY                   ADC_CFGR_AUTDLY_Msk                  /*!< ADC Delayed conversion mode */

+

+#define ADC_CFGR_DISCEN_Pos               (16U)

+#define ADC_CFGR_DISCEN_Msk               (0x1UL << ADC_CFGR_DISCEN_Pos)       /*!< 0x00010000 */

+#define ADC_CFGR_DISCEN                   ADC_CFGR_DISCEN_Msk                  /*!< ADC Discontinuous mode for regular channels */

+

+#define ADC_CFGR_DISCNUM_Pos              (17U)

+#define ADC_CFGR_DISCNUM_Msk              (0x7UL << ADC_CFGR_DISCNUM_Pos)      /*!< 0x000E0000 */

+#define ADC_CFGR_DISCNUM                  ADC_CFGR_DISCNUM_Msk                 /*!< ADC Discontinuous mode channel count */

+#define ADC_CFGR_DISCNUM_0                (0x1UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00020000 */

+#define ADC_CFGR_DISCNUM_1                (0x2UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00040000 */

+#define ADC_CFGR_DISCNUM_2                (0x4UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00080000 */

+

+#define ADC_CFGR_JDISCEN_Pos              (20U)

+#define ADC_CFGR_JDISCEN_Msk              (0x1UL << ADC_CFGR_JDISCEN_Pos)      /*!< 0x00100000 */

+#define ADC_CFGR_JDISCEN                  ADC_CFGR_JDISCEN_Msk                 /*!< ADC Discontinuous mode on injected channels */

+#define ADC_CFGR_JQM_Pos                  (21U)

+#define ADC_CFGR_JQM_Msk                  (0x1UL << ADC_CFGR_JQM_Pos)          /*!< 0x00200000 */

+#define ADC_CFGR_JQM                      ADC_CFGR_JQM_Msk                     /*!< ADC JSQR Queue mode */

+#define ADC_CFGR_AWD1SGL_Pos              (22U)

+#define ADC_CFGR_AWD1SGL_Msk              (0x1UL << ADC_CFGR_AWD1SGL_Pos)      /*!< 0x00400000 */

+#define ADC_CFGR_AWD1SGL                  ADC_CFGR_AWD1SGL_Msk                 /*!< Enable the watchdog 1 on a single channel or on all channels */

+#define ADC_CFGR_AWD1EN_Pos               (23U)

+#define ADC_CFGR_AWD1EN_Msk               (0x1UL << ADC_CFGR_AWD1EN_Pos)       /*!< 0x00800000 */

+#define ADC_CFGR_AWD1EN                   ADC_CFGR_AWD1EN_Msk                  /*!< ADC Analog watchdog 1 enable on regular Channels */

+#define ADC_CFGR_JAWD1EN_Pos              (24U)

+#define ADC_CFGR_JAWD1EN_Msk              (0x1UL << ADC_CFGR_JAWD1EN_Pos)      /*!< 0x01000000 */

+#define ADC_CFGR_JAWD1EN                  ADC_CFGR_JAWD1EN_Msk                 /*!< ADC Analog watchdog 1 enable on injected Channels */

+#define ADC_CFGR_JAUTO_Pos                (25U)

+#define ADC_CFGR_JAUTO_Msk                (0x1UL << ADC_CFGR_JAUTO_Pos)        /*!< 0x02000000 */

+#define ADC_CFGR_JAUTO                    ADC_CFGR_JAUTO_Msk                   /*!< ADC Automatic injected group conversion */

+

+#define ADC_CFGR_AWD1CH_Pos               (26U)

+#define ADC_CFGR_AWD1CH_Msk               (0x1FUL << ADC_CFGR_AWD1CH_Pos)      /*!< 0x7C000000 */

+#define ADC_CFGR_AWD1CH                   ADC_CFGR_AWD1CH_Msk                  /*!< ADC Analog watchdog 1 Channel selection */

+#define ADC_CFGR_AWD1CH_0                 (0x01UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x04000000 */

+#define ADC_CFGR_AWD1CH_1                 (0x02UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x08000000 */

+#define ADC_CFGR_AWD1CH_2                 (0x04UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x10000000 */

+#define ADC_CFGR_AWD1CH_3                 (0x08UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x20000000 */

+#define ADC_CFGR_AWD1CH_4                 (0x10UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x40000000 */

+

+#define ADC_CFGR_JQDIS_Pos                (31U)

+#define ADC_CFGR_JQDIS_Msk                (0x1UL << ADC_CFGR_JQDIS_Pos)        /*!< 0x80000000 */

+#define ADC_CFGR_JQDIS                    ADC_CFGR_JQDIS_Msk                   /*!< ADC Injected queue disable */

+

+/********************  Bit definition for ADC_CFGR2 register  ********************/

+#define ADC_CFGR2_ROVSE_Pos               (0U)

+#define ADC_CFGR2_ROVSE_Msk               (0x1UL << ADC_CFGR2_ROVSE_Pos)       /*!< 0x00000001 */

+#define ADC_CFGR2_ROVSE                   ADC_CFGR2_ROVSE_Msk                  /*!< ADC Regular group oversampler enable */

+#define ADC_CFGR2_JOVSE_Pos               (1U)

+#define ADC_CFGR2_JOVSE_Msk               (0x1UL << ADC_CFGR2_JOVSE_Pos)       /*!< 0x00000002 */

+#define ADC_CFGR2_JOVSE                   ADC_CFGR2_JOVSE_Msk                  /*!< ADC Injected group oversampler enable */

+

+#define ADC_CFGR2_OVSS_Pos                (5U)

+#define ADC_CFGR2_OVSS_Msk                (0xFUL << ADC_CFGR2_OVSS_Pos)        /*!< 0x000001E0 */

+#define ADC_CFGR2_OVSS                    ADC_CFGR2_OVSS_Msk                   /*!< ADC Regular Oversampling shift */

+#define ADC_CFGR2_OVSS_0                  (0x1UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000020 */

+#define ADC_CFGR2_OVSS_1                  (0x2UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000040 */

+#define ADC_CFGR2_OVSS_2                  (0x4UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000080 */

+#define ADC_CFGR2_OVSS_3                  (0x8UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000100 */

+

+#define ADC_CFGR2_TROVS_Pos               (9U)

+#define ADC_CFGR2_TROVS_Msk               (0x1UL << ADC_CFGR2_TROVS_Pos)       /*!< 0x00000200 */

+#define ADC_CFGR2_TROVS                   ADC_CFGR2_TROVS_Msk                  /*!< ADC Triggered regular Oversampling */

+#define ADC_CFGR2_ROVSM_Pos               (10U)

+#define ADC_CFGR2_ROVSM_Msk               (0x1UL << ADC_CFGR2_ROVSM_Pos)       /*!< 0x00000400 */

+#define ADC_CFGR2_ROVSM                   ADC_CFGR2_ROVSM_Msk                  /*!< ADC Regular oversampling mode */

+

+#define ADC_CFGR2_RSHIFT1_Pos             (11U)

+#define ADC_CFGR2_RSHIFT1_Msk             (0x1UL << ADC_CFGR2_RSHIFT1_Pos)     /*!< 0x00000800 */

+#define ADC_CFGR2_RSHIFT1                 ADC_CFGR2_RSHIFT1_Msk                /*!< ADC Right-shift data after Offset 1 correction */

+#define ADC_CFGR2_RSHIFT2_Pos             (12U)

+#define ADC_CFGR2_RSHIFT2_Msk             (0x1UL << ADC_CFGR2_RSHIFT2_Pos)     /*!< 0x00001000 */

+#define ADC_CFGR2_RSHIFT2                 ADC_CFGR2_RSHIFT2_Msk                /*!< ADC Right-shift data after Offset 2 correction */

+#define ADC_CFGR2_RSHIFT3_Pos             (13U)

+#define ADC_CFGR2_RSHIFT3_Msk             (0x1UL << ADC_CFGR2_RSHIFT3_Pos)     /*!< 0x00002000 */

+#define ADC_CFGR2_RSHIFT3                 ADC_CFGR2_RSHIFT3_Msk                /*!< ADC Right-shift data after Offset 3 correction */

+#define ADC_CFGR2_RSHIFT4_Pos             (14U)

+#define ADC_CFGR2_RSHIFT4_Msk             (0x1UL << ADC_CFGR2_RSHIFT4_Pos)     /*!< 0x00004000 */

+#define ADC_CFGR2_RSHIFT4                 ADC_CFGR2_RSHIFT4_Msk                /*!< ADC Right-shift data after Offset 4 correction */

+

+#define ADC_CFGR2_OVSR_Pos                (16U)

+#define ADC_CFGR2_OVSR_Msk                (0x3FFUL << ADC_CFGR2_OVSR_Pos)      /*!< 0x03FF0000 */

+#define ADC_CFGR2_OVSR                    ADC_CFGR2_OVSR_Msk                   /*!< ADC oversampling Ratio */

+#define ADC_CFGR2_OVSR_0                  (0x001UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00010000 */

+#define ADC_CFGR2_OVSR_1                  (0x002UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00020000 */

+#define ADC_CFGR2_OVSR_2                  (0x004UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00040000 */

+#define ADC_CFGR2_OVSR_3                  (0x008UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00080000 */

+#define ADC_CFGR2_OVSR_4                  (0x010UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00100000 */

+#define ADC_CFGR2_OVSR_5                  (0x020UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00200000 */

+#define ADC_CFGR2_OVSR_6                  (0x040UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00400000 */

+#define ADC_CFGR2_OVSR_7                  (0x080UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00800000 */

+#define ADC_CFGR2_OVSR_8                  (0x100UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x01000000 */

+#define ADC_CFGR2_OVSR_9                  (0x200UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x02000000 */

+

+#define ADC_CFGR2_LSHIFT_Pos              (28U)

+#define ADC_CFGR2_LSHIFT_Msk              (0xFUL << ADC_CFGR2_LSHIFT_Pos)      /*!< 0xF0000000 */

+#define ADC_CFGR2_LSHIFT                  ADC_CFGR2_LSHIFT_Msk                 /*!< ADC Left shift factor */

+#define ADC_CFGR2_LSHIFT_0                (0x1UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x10000000 */

+#define ADC_CFGR2_LSHIFT_1                (0x2UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x20000000 */

+#define ADC_CFGR2_LSHIFT_2                (0x4UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x40000000 */

+#define ADC_CFGR2_LSHIFT_3                (0x8UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_SMPR1 register  ********************/

+#define ADC_SMPR1_SMP0_Pos                (0U)

+#define ADC_SMPR1_SMP0_Msk                (0x7UL << ADC_SMPR1_SMP0_Pos)        /*!< 0x00000007 */

+#define ADC_SMPR1_SMP0                    ADC_SMPR1_SMP0_Msk                   /*!< ADC Channel 0 Sampling time selection  */

+#define ADC_SMPR1_SMP0_0                  (0x1UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000001 */

+#define ADC_SMPR1_SMP0_1                  (0x2UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000002 */

+#define ADC_SMPR1_SMP0_2                  (0x4UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000004 */

+

+#define ADC_SMPR1_SMP1_Pos                (3U)

+#define ADC_SMPR1_SMP1_Msk                (0x7UL << ADC_SMPR1_SMP1_Pos)        /*!< 0x00000038 */

+#define ADC_SMPR1_SMP1                    ADC_SMPR1_SMP1_Msk                   /*!< ADC Channel 1 Sampling time selection  */

+#define ADC_SMPR1_SMP1_0                  (0x1UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000008 */

+#define ADC_SMPR1_SMP1_1                  (0x2UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000010 */

+#define ADC_SMPR1_SMP1_2                  (0x4UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000020 */

+

+#define ADC_SMPR1_SMP2_Pos                (6U)

+#define ADC_SMPR1_SMP2_Msk                (0x7UL << ADC_SMPR1_SMP2_Pos)        /*!< 0x000001C0 */

+#define ADC_SMPR1_SMP2                    ADC_SMPR1_SMP2_Msk                   /*!< ADC Channel 2 Sampling time selection  */

+#define ADC_SMPR1_SMP2_0                  (0x1UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000040 */

+#define ADC_SMPR1_SMP2_1                  (0x2UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000080 */

+#define ADC_SMPR1_SMP2_2                  (0x4UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000100 */

+

+#define ADC_SMPR1_SMP3_Pos                (9U)

+#define ADC_SMPR1_SMP3_Msk                (0x7UL << ADC_SMPR1_SMP3_Pos)        /*!< 0x00000E00 */

+#define ADC_SMPR1_SMP3                    ADC_SMPR1_SMP3_Msk                   /*!< ADC Channel 3 Sampling time selection  */

+#define ADC_SMPR1_SMP3_0                  (0x1UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000200 */

+#define ADC_SMPR1_SMP3_1                  (0x2UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000400 */

+#define ADC_SMPR1_SMP3_2                  (0x4UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000800 */

+

+#define ADC_SMPR1_SMP4_Pos                (12U)

+#define ADC_SMPR1_SMP4_Msk                (0x7UL << ADC_SMPR1_SMP4_Pos)        /*!< 0x00007000 */

+#define ADC_SMPR1_SMP4                    ADC_SMPR1_SMP4_Msk                   /*!< ADC Channel 4 Sampling time selection  */

+#define ADC_SMPR1_SMP4_0                  (0x1UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00001000 */

+#define ADC_SMPR1_SMP4_1                  (0x2UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00002000 */

+#define ADC_SMPR1_SMP4_2                  (0x4UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00004000 */

+

+#define ADC_SMPR1_SMP5_Pos                (15U)

+#define ADC_SMPR1_SMP5_Msk                (0x7UL << ADC_SMPR1_SMP5_Pos)        /*!< 0x00038000 */

+#define ADC_SMPR1_SMP5                    ADC_SMPR1_SMP5_Msk                   /*!< ADC Channel 5 Sampling time selection  */

+#define ADC_SMPR1_SMP5_0                  (0x1UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00008000 */

+#define ADC_SMPR1_SMP5_1                  (0x2UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00010000 */

+#define ADC_SMPR1_SMP5_2                  (0x4UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00020000 */

+

+#define ADC_SMPR1_SMP6_Pos                (18U)

+#define ADC_SMPR1_SMP6_Msk                (0x7UL << ADC_SMPR1_SMP6_Pos)        /*!< 0x001C0000 */

+#define ADC_SMPR1_SMP6                    ADC_SMPR1_SMP6_Msk                   /*!< ADC Channel 6 Sampling time selection  */

+#define ADC_SMPR1_SMP6_0                  (0x1UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00040000 */

+#define ADC_SMPR1_SMP6_1                  (0x2UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00080000 */

+#define ADC_SMPR1_SMP6_2                  (0x4UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00100000 */

+

+#define ADC_SMPR1_SMP7_Pos                (21U)

+#define ADC_SMPR1_SMP7_Msk                (0x7UL << ADC_SMPR1_SMP7_Pos)        /*!< 0x00E00000 */

+#define ADC_SMPR1_SMP7                    ADC_SMPR1_SMP7_Msk                   /*!< ADC Channel 7 Sampling time selection  */

+#define ADC_SMPR1_SMP7_0                  (0x1UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00200000 */

+#define ADC_SMPR1_SMP7_1                  (0x2UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00400000 */

+#define ADC_SMPR1_SMP7_2                  (0x4UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00800000 */

+

+#define ADC_SMPR1_SMP8_Pos                (24U)

+#define ADC_SMPR1_SMP8_Msk                (0x7UL << ADC_SMPR1_SMP8_Pos)        /*!< 0x07000000 */

+#define ADC_SMPR1_SMP8                    ADC_SMPR1_SMP8_Msk                   /*!< ADC Channel 8 Sampling time selection  */

+#define ADC_SMPR1_SMP8_0                  (0x1UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x01000000 */

+#define ADC_SMPR1_SMP8_1                  (0x2UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x02000000 */

+#define ADC_SMPR1_SMP8_2                  (0x4UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x04000000 */

+

+#define ADC_SMPR1_SMP9_Pos                (27U)

+#define ADC_SMPR1_SMP9_Msk                (0x7UL << ADC_SMPR1_SMP9_Pos)        /*!< 0x38000000 */

+#define ADC_SMPR1_SMP9                    ADC_SMPR1_SMP9_Msk                   /*!< ADC Channel 9 Sampling time selection  */

+#define ADC_SMPR1_SMP9_0                  (0x1UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x08000000 */

+#define ADC_SMPR1_SMP9_1                  (0x2UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x10000000 */

+#define ADC_SMPR1_SMP9_2                  (0x4UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x20000000 */

+

+/********************  Bit definition for ADC_SMPR2 register  ********************/

+#define ADC_SMPR2_SMP10_Pos               (0U)

+#define ADC_SMPR2_SMP10_Msk               (0x7UL << ADC_SMPR2_SMP10_Pos)       /*!< 0x00000007 */

+#define ADC_SMPR2_SMP10                   ADC_SMPR2_SMP10_Msk                  /*!< ADC Channel 10 Sampling time selection  */

+#define ADC_SMPR2_SMP10_0                 (0x1UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000001 */

+#define ADC_SMPR2_SMP10_1                 (0x2UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000002 */

+#define ADC_SMPR2_SMP10_2                 (0x4UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000004 */

+

+#define ADC_SMPR2_SMP11_Pos               (3U)

+#define ADC_SMPR2_SMP11_Msk               (0x7UL << ADC_SMPR2_SMP11_Pos)       /*!< 0x00000038 */

+#define ADC_SMPR2_SMP11                   ADC_SMPR2_SMP11_Msk                  /*!< ADC Channel 11 Sampling time selection  */

+#define ADC_SMPR2_SMP11_0                 (0x1UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000008 */

+#define ADC_SMPR2_SMP11_1                 (0x2UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000010 */

+#define ADC_SMPR2_SMP11_2                 (0x4UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000020 */

+

+#define ADC_SMPR2_SMP12_Pos               (6U)

+#define ADC_SMPR2_SMP12_Msk               (0x7UL << ADC_SMPR2_SMP12_Pos)       /*!< 0x000001C0 */

+#define ADC_SMPR2_SMP12                   ADC_SMPR2_SMP12_Msk                  /*!< ADC Channel 12 Sampling time selection  */

+#define ADC_SMPR2_SMP12_0                 (0x1UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000040 */

+#define ADC_SMPR2_SMP12_1                 (0x2UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000080 */

+#define ADC_SMPR2_SMP12_2                 (0x4UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000100 */

+

+#define ADC_SMPR2_SMP13_Pos               (9U)

+#define ADC_SMPR2_SMP13_Msk               (0x7UL << ADC_SMPR2_SMP13_Pos)       /*!< 0x00000E00 */

+#define ADC_SMPR2_SMP13                   ADC_SMPR2_SMP13_Msk                  /*!< ADC Channel 13 Sampling time selection  */

+#define ADC_SMPR2_SMP13_0                 (0x1UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000200 */

+#define ADC_SMPR2_SMP13_1                 (0x2UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000400 */

+#define ADC_SMPR2_SMP13_2                 (0x4UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000800 */

+

+#define ADC_SMPR2_SMP14_Pos               (12U)

+#define ADC_SMPR2_SMP14_Msk               (0x7UL << ADC_SMPR2_SMP14_Pos)       /*!< 0x00007000 */

+#define ADC_SMPR2_SMP14                   ADC_SMPR2_SMP14_Msk                  /*!< ADC Channel 14 Sampling time selection  */

+#define ADC_SMPR2_SMP14_0                 (0x1UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00001000 */

+#define ADC_SMPR2_SMP14_1                 (0x2UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00002000 */

+#define ADC_SMPR2_SMP14_2                 (0x4UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00004000 */

+

+#define ADC_SMPR2_SMP15_Pos               (15U)

+#define ADC_SMPR2_SMP15_Msk               (0x7UL << ADC_SMPR2_SMP15_Pos)       /*!< 0x00038000 */

+#define ADC_SMPR2_SMP15                   ADC_SMPR2_SMP15_Msk                  /*!< ADC Channel 15 Sampling time selection  */

+#define ADC_SMPR2_SMP15_0                 (0x1UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00008000 */

+#define ADC_SMPR2_SMP15_1                 (0x2UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00010000 */

+#define ADC_SMPR2_SMP15_2                 (0x4UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00020000 */

+

+#define ADC_SMPR2_SMP16_Pos               (18U)

+#define ADC_SMPR2_SMP16_Msk               (0x7UL << ADC_SMPR2_SMP16_Pos)       /*!< 0x001C0000 */

+#define ADC_SMPR2_SMP16                   ADC_SMPR2_SMP16_Msk                  /*!< ADC Channel 16 Sampling time selection  */

+#define ADC_SMPR2_SMP16_0                 (0x1UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00040000 */

+#define ADC_SMPR2_SMP16_1                 (0x2UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00080000 */

+#define ADC_SMPR2_SMP16_2                 (0x4UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00100000 */

+

+#define ADC_SMPR2_SMP17_Pos               (21U)

+#define ADC_SMPR2_SMP17_Msk               (0x7UL << ADC_SMPR2_SMP17_Pos)       /*!< 0x00E00000 */

+#define ADC_SMPR2_SMP17                   ADC_SMPR2_SMP17_Msk                  /*!< ADC Channel 17 Sampling time selection  */

+#define ADC_SMPR2_SMP17_0                 (0x1UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00200000 */

+#define ADC_SMPR2_SMP17_1                 (0x2UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00400000 */

+#define ADC_SMPR2_SMP17_2                 (0x4UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00800000 */

+

+#define ADC_SMPR2_SMP18_Pos               (24U)

+#define ADC_SMPR2_SMP18_Msk               (0x7UL << ADC_SMPR2_SMP18_Pos)       /*!< 0x07000000 */

+#define ADC_SMPR2_SMP18                   ADC_SMPR2_SMP18_Msk                  /*!< ADC Channel 18 Sampling time selection  */

+#define ADC_SMPR2_SMP18_0                 (0x1UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x01000000 */

+#define ADC_SMPR2_SMP18_1                 (0x2UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x02000000 */

+#define ADC_SMPR2_SMP18_2                 (0x4UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x04000000 */

+

+#define ADC_SMPR2_SMP19_Pos               (27U)

+#define ADC_SMPR2_SMP19_Msk               (0x7UL << ADC_SMPR2_SMP19_Pos)       /*!< 0x38000000 */

+#define ADC_SMPR2_SMP19                   ADC_SMPR2_SMP19_Msk                  /*!< ADC Channel 19 Sampling time selection  */

+#define ADC_SMPR2_SMP19_0                 (0x1UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x08000000 */

+#define ADC_SMPR2_SMP19_1                 (0x2UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x10000000 */

+#define ADC_SMPR2_SMP19_2                 (0x4UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x20000000 */

+

+/********************  Bit definition for ADC_PCSEL register  ********************/

+#define ADC_PCSEL_PCSEL_Pos               (0U)

+#define ADC_PCSEL_PCSEL_Msk               (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)   /*!< 0x000FFFFF */

+#define ADC_PCSEL_PCSEL                   ADC_PCSEL_PCSEL_Msk                  /*!< ADC pre channel selection */

+#define ADC_PCSEL_PCSEL_0                 (0x00001UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */

+#define ADC_PCSEL_PCSEL_1                 (0x00002UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */

+#define ADC_PCSEL_PCSEL_2                 (0x00004UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */

+#define ADC_PCSEL_PCSEL_3                 (0x00008UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */

+#define ADC_PCSEL_PCSEL_4                 (0x00010UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */

+#define ADC_PCSEL_PCSEL_5                 (0x00020UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */

+#define ADC_PCSEL_PCSEL_6                 (0x00040UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */

+#define ADC_PCSEL_PCSEL_7                 (0x00080UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */

+#define ADC_PCSEL_PCSEL_8                 (0x00100UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */

+#define ADC_PCSEL_PCSEL_9                 (0x00200UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */

+#define ADC_PCSEL_PCSEL_10                (0x00400UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */

+#define ADC_PCSEL_PCSEL_11                (0x00800UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */

+#define ADC_PCSEL_PCSEL_12                (0x01000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */

+#define ADC_PCSEL_PCSEL_13                (0x02000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */

+#define ADC_PCSEL_PCSEL_14                (0x04000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */

+#define ADC_PCSEL_PCSEL_15                (0x08000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */

+#define ADC_PCSEL_PCSEL_16                (0x10000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */

+#define ADC_PCSEL_PCSEL_17                (0x20000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */

+#define ADC_PCSEL_PCSEL_18                (0x40000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */

+#define ADC_PCSEL_PCSEL_19                (0x80000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00080000 */

+

+/*****************  Bit definition for ADC_LTR1, 2, 3 registers *****************/

+#define ADC_LTR_LT_Pos                    (0U)

+#define ADC_LTR_LT_Msk                    (0x3FFFFFFUL << ADC_LTR_LT_Pos)      /*!< 0x03FFFFFF */

+#define ADC_LTR_LT                        ADC_LTR_LT_Msk                       /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */

+

+/*****************  Bit definition for ADC_HTR1, 2, 3 registers  ****************/

+#define ADC_HTR_HT_Pos                    (0U)

+#define ADC_HTR_HT_Msk                    (0x3FFFFFFUL << ADC_HTR_HT_Pos)      /*!< 0x03FFFFFF */

+#define ADC_HTR_HT                        ADC_HTR_HT_Msk                       /*!< ADC Analog watchdog 1,2 and 3 higher threshold */

+

+

+/********************  Bit definition for ADC_SQR1 register  ********************/

+#define ADC_SQR1_L_Pos                    (0U)

+#define ADC_SQR1_L_Msk                    (0xFUL << ADC_SQR1_L_Pos)            /*!< 0x0000000F */

+#define ADC_SQR1_L                        ADC_SQR1_L_Msk                       /*!< ADC regular channel sequence lenght */

+#define ADC_SQR1_L_0                      (0x1UL << ADC_SQR1_L_Pos)             /*!< 0x00000001 */

+#define ADC_SQR1_L_1                      (0x2UL << ADC_SQR1_L_Pos)             /*!< 0x00000002 */

+#define ADC_SQR1_L_2                      (0x4UL << ADC_SQR1_L_Pos)             /*!< 0x00000004 */

+#define ADC_SQR1_L_3                      (0x8UL << ADC_SQR1_L_Pos)             /*!< 0x00000008 */

+

+#define ADC_SQR1_SQ1_Pos                  (6U)

+#define ADC_SQR1_SQ1_Msk                  (0x1FUL << ADC_SQR1_SQ1_Pos)         /*!< 0x000007C0 */

+#define ADC_SQR1_SQ1                      ADC_SQR1_SQ1_Msk                     /*!< ADC 1st conversion in regular sequence */

+#define ADC_SQR1_SQ1_0                    (0x01UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000040 */

+#define ADC_SQR1_SQ1_1                    (0x02UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000080 */

+#define ADC_SQR1_SQ1_2                    (0x04UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000100 */

+#define ADC_SQR1_SQ1_3                    (0x08UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000200 */

+#define ADC_SQR1_SQ1_4                    (0x10UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000400 */

+

+#define ADC_SQR1_SQ2_Pos                  (12U)

+#define ADC_SQR1_SQ2_Msk                  (0x1FUL << ADC_SQR1_SQ2_Pos)         /*!< 0x0001F000 */

+#define ADC_SQR1_SQ2                      ADC_SQR1_SQ2_Msk                     /*!< ADC 2nd conversion in regular sequence */

+#define ADC_SQR1_SQ2_0                    (0x01UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00001000 */

+#define ADC_SQR1_SQ2_1                    (0x02UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00002000 */

+#define ADC_SQR1_SQ2_2                    (0x04UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00004000 */

+#define ADC_SQR1_SQ2_3                    (0x08UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00008000 */

+#define ADC_SQR1_SQ2_4                    (0x10UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00010000 */

+

+#define ADC_SQR1_SQ3_Pos                  (18U)

+#define ADC_SQR1_SQ3_Msk                  (0x1FUL << ADC_SQR1_SQ3_Pos)         /*!< 0x007C0000 */

+#define ADC_SQR1_SQ3                      ADC_SQR1_SQ3_Msk                     /*!< ADC 3rd conversion in regular sequence */

+#define ADC_SQR1_SQ3_0                    (0x01UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00040000 */

+#define ADC_SQR1_SQ3_1                    (0x02UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00080000 */

+#define ADC_SQR1_SQ3_2                    (0x04UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00100000 */

+#define ADC_SQR1_SQ3_3                    (0x08UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00200000 */

+#define ADC_SQR1_SQ3_4                    (0x10UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00400000 */

+

+#define ADC_SQR1_SQ4_Pos                  (24U)

+#define ADC_SQR1_SQ4_Msk                  (0x1FUL << ADC_SQR1_SQ4_Pos)         /*!< 0x1F000000 */

+#define ADC_SQR1_SQ4                      ADC_SQR1_SQ4_Msk                     /*!< ADC 4th conversion in regular sequence */

+#define ADC_SQR1_SQ4_0                    (0x01UL << ADC_SQR1_SQ4_Pos)          /*!< 0x01000000 */

+#define ADC_SQR1_SQ4_1                    (0x02UL << ADC_SQR1_SQ4_Pos)          /*!< 0x02000000 */

+#define ADC_SQR1_SQ4_2                    (0x04UL << ADC_SQR1_SQ4_Pos)          /*!< 0x04000000 */

+#define ADC_SQR1_SQ4_3                    (0x08UL << ADC_SQR1_SQ4_Pos)          /*!< 0x08000000 */

+#define ADC_SQR1_SQ4_4                    (0x10UL << ADC_SQR1_SQ4_Pos)          /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR2 register  ********************/

+#define ADC_SQR2_SQ5_Pos                  (0U)

+#define ADC_SQR2_SQ5_Msk                  (0x1FUL << ADC_SQR2_SQ5_Pos)         /*!< 0x0000001F */

+#define ADC_SQR2_SQ5                      ADC_SQR2_SQ5_Msk                     /*!< ADC 5th conversion in regular sequence */

+#define ADC_SQR2_SQ5_0                    (0x01UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000001 */

+#define ADC_SQR2_SQ5_1                    (0x02UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000002 */

+#define ADC_SQR2_SQ5_2                    (0x04UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000004 */

+#define ADC_SQR2_SQ5_3                    (0x08UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000008 */

+#define ADC_SQR2_SQ5_4                    (0x10UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000010 */

+

+#define ADC_SQR2_SQ6_Pos                  (6U)

+#define ADC_SQR2_SQ6_Msk                  (0x1FUL << ADC_SQR2_SQ6_Pos)         /*!< 0x000007C0 */

+#define ADC_SQR2_SQ6                      ADC_SQR2_SQ6_Msk                     /*!< ADC 6th conversion in regular sequence */

+#define ADC_SQR2_SQ6_0                    (0x01UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000040 */

+#define ADC_SQR2_SQ6_1                    (0x02UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000080 */

+#define ADC_SQR2_SQ6_2                    (0x04UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000100 */

+#define ADC_SQR2_SQ6_3                    (0x08UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000200 */

+#define ADC_SQR2_SQ6_4                    (0x10UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000400 */

+

+#define ADC_SQR2_SQ7_Pos                  (12U)

+#define ADC_SQR2_SQ7_Msk                  (0x1FUL << ADC_SQR2_SQ7_Pos)         /*!< 0x0001F000 */

+#define ADC_SQR2_SQ7                      ADC_SQR2_SQ7_Msk                     /*!< ADC 7th conversion in regular sequence */

+#define ADC_SQR2_SQ7_0                    (0x01UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00001000 */

+#define ADC_SQR2_SQ7_1                    (0x02UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00002000 */

+#define ADC_SQR2_SQ7_2                    (0x04UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00004000 */

+#define ADC_SQR2_SQ7_3                    (0x08UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00008000 */

+#define ADC_SQR2_SQ7_4                    (0x10UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00010000 */

+

+#define ADC_SQR2_SQ8_Pos                  (18U)

+#define ADC_SQR2_SQ8_Msk                  (0x1FUL << ADC_SQR2_SQ8_Pos)         /*!< 0x007C0000 */

+#define ADC_SQR2_SQ8                      ADC_SQR2_SQ8_Msk                     /*!< ADC 8th conversion in regular sequence */

+#define ADC_SQR2_SQ8_0                    (0x01UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00040000 */

+#define ADC_SQR2_SQ8_1                    (0x02UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00080000 */

+#define ADC_SQR2_SQ8_2                    (0x04UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00100000 */

+#define ADC_SQR2_SQ8_3                    (0x08UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00200000 */

+#define ADC_SQR2_SQ8_4                    (0x10UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00400000 */

+

+#define ADC_SQR2_SQ9_Pos                  (24U)

+#define ADC_SQR2_SQ9_Msk                  (0x1FUL << ADC_SQR2_SQ9_Pos)         /*!< 0x1F000000 */

+#define ADC_SQR2_SQ9                      ADC_SQR2_SQ9_Msk                     /*!< ADC 9th conversion in regular sequence */

+#define ADC_SQR2_SQ9_0                    (0x01UL << ADC_SQR2_SQ9_Pos)          /*!< 0x01000000 */

+#define ADC_SQR2_SQ9_1                    (0x02UL << ADC_SQR2_SQ9_Pos)          /*!< 0x02000000 */

+#define ADC_SQR2_SQ9_2                    (0x04UL << ADC_SQR2_SQ9_Pos)          /*!< 0x04000000 */

+#define ADC_SQR2_SQ9_3                    (0x08UL << ADC_SQR2_SQ9_Pos)          /*!< 0x08000000 */

+#define ADC_SQR2_SQ9_4                    (0x10UL << ADC_SQR2_SQ9_Pos)          /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR3 register  ********************/

+#define ADC_SQR3_SQ10_Pos                 (0U)

+#define ADC_SQR3_SQ10_Msk                 (0x1FUL << ADC_SQR3_SQ10_Pos)        /*!< 0x0000001F */

+#define ADC_SQR3_SQ10                     ADC_SQR3_SQ10_Msk                    /*!< ADC 10th conversion in regular sequence */

+#define ADC_SQR3_SQ10_0                   (0x01UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000001 */

+#define ADC_SQR3_SQ10_1                   (0x02UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000002 */

+#define ADC_SQR3_SQ10_2                   (0x04UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000004 */

+#define ADC_SQR3_SQ10_3                   (0x08UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000008 */

+#define ADC_SQR3_SQ10_4                   (0x10UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000010 */

+

+#define ADC_SQR3_SQ11_Pos                 (6U)

+#define ADC_SQR3_SQ11_Msk                 (0x1FUL << ADC_SQR3_SQ11_Pos)        /*!< 0x000007C0 */

+#define ADC_SQR3_SQ11                     ADC_SQR3_SQ11_Msk                    /*!< ADC 11th conversion in regular sequence */

+#define ADC_SQR3_SQ11_0                   (0x01UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000040 */

+#define ADC_SQR3_SQ11_1                   (0x02UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000080 */

+#define ADC_SQR3_SQ11_2                   (0x04UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000100 */

+#define ADC_SQR3_SQ11_3                   (0x08UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000200 */

+#define ADC_SQR3_SQ11_4                   (0x10UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000400 */

+

+#define ADC_SQR3_SQ12_Pos                 (12U)

+#define ADC_SQR3_SQ12_Msk                 (0x1FUL << ADC_SQR3_SQ12_Pos)        /*!< 0x0001F000 */

+#define ADC_SQR3_SQ12                     ADC_SQR3_SQ12_Msk                    /*!< ADC 12th conversion in regular sequence */

+#define ADC_SQR3_SQ12_0                   (0x01UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00001000 */

+#define ADC_SQR3_SQ12_1                   (0x02UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00002000 */

+#define ADC_SQR3_SQ12_2                   (0x04UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00004000 */

+#define ADC_SQR3_SQ12_3                   (0x08UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00008000 */

+#define ADC_SQR3_SQ12_4                   (0x10UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00010000 */

+

+#define ADC_SQR3_SQ13_Pos                 (18U)

+#define ADC_SQR3_SQ13_Msk                 (0x1FUL << ADC_SQR3_SQ13_Pos)        /*!< 0x007C0000 */

+#define ADC_SQR3_SQ13                     ADC_SQR3_SQ13_Msk                    /*!< ADC 13th conversion in regular sequence */

+#define ADC_SQR3_SQ13_0                   (0x01UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00040000 */

+#define ADC_SQR3_SQ13_1                   (0x02UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00080000 */

+#define ADC_SQR3_SQ13_2                   (0x04UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00100000 */

+#define ADC_SQR3_SQ13_3                   (0x08UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00200000 */

+#define ADC_SQR3_SQ13_4                   (0x10UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00400000 */

+

+#define ADC_SQR3_SQ14_Pos                 (24U)

+#define ADC_SQR3_SQ14_Msk                 (0x1FUL << ADC_SQR3_SQ14_Pos)        /*!< 0x1F000000 */

+#define ADC_SQR3_SQ14                     ADC_SQR3_SQ14_Msk                    /*!< ADC 14th conversion in regular sequence */

+#define ADC_SQR3_SQ14_0                   (0x01UL << ADC_SQR3_SQ14_Pos)         /*!< 0x01000000 */

+#define ADC_SQR3_SQ14_1                   (0x02UL << ADC_SQR3_SQ14_Pos)         /*!< 0x02000000 */

+#define ADC_SQR3_SQ14_2                   (0x04UL << ADC_SQR3_SQ14_Pos)         /*!< 0x04000000 */

+#define ADC_SQR3_SQ14_3                   (0x08UL << ADC_SQR3_SQ14_Pos)         /*!< 0x08000000 */

+#define ADC_SQR3_SQ14_4                   (0x10UL << ADC_SQR3_SQ14_Pos)         /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR4 register  ********************/

+#define ADC_SQR4_SQ15_Pos                 (0U)

+#define ADC_SQR4_SQ15_Msk                 (0x1FUL << ADC_SQR4_SQ15_Pos)        /*!< 0x0000001F */

+#define ADC_SQR4_SQ15                     ADC_SQR4_SQ15_Msk                    /*!< ADC 15th conversion in regular sequence */

+#define ADC_SQR4_SQ15_0                   (0x01UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000001 */

+#define ADC_SQR4_SQ15_1                   (0x02UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000002 */

+#define ADC_SQR4_SQ15_2                   (0x04UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000004 */

+#define ADC_SQR4_SQ15_3                   (0x08UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000008 */

+#define ADC_SQR4_SQ15_4                   (0x10UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000010 */

+

+#define ADC_SQR4_SQ16_Pos                 (6U)

+#define ADC_SQR4_SQ16_Msk                 (0x1FUL << ADC_SQR4_SQ16_Pos)        /*!< 0x000007C0 */

+#define ADC_SQR4_SQ16                     ADC_SQR4_SQ16_Msk                    /*!< ADC 16th conversion in regular sequence */

+#define ADC_SQR4_SQ16_0                   (0x01UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000040 */

+#define ADC_SQR4_SQ16_1                   (0x02UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000080 */

+#define ADC_SQR4_SQ16_2                   (0x04UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000100 */

+#define ADC_SQR4_SQ16_3                   (0x08UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000200 */

+#define ADC_SQR4_SQ16_4                   (0x10UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000400 */

+/********************  Bit definition for ADC_DR register  ********************/

+#define ADC_DR_RDATA_Pos                  (0U)

+#define ADC_DR_RDATA_Msk                  (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)   /*!< 0xFFFFFFFF */

+#define ADC_DR_RDATA                      ADC_DR_RDATA_Msk                     /*!< ADC regular Data converted */

+

+/********************  Bit definition for ADC_JSQR register  ********************/

+#define ADC_JSQR_JL_Pos                   (0U)

+#define ADC_JSQR_JL_Msk                   (0x3UL << ADC_JSQR_JL_Pos)           /*!< 0x00000003 */

+#define ADC_JSQR_JL                       ADC_JSQR_JL_Msk                      /*!< ADC injected channel sequence length */

+#define ADC_JSQR_JL_0                     (0x1UL << ADC_JSQR_JL_Pos)           /*!< 0x00000001 */

+#define ADC_JSQR_JL_1                     (0x2UL << ADC_JSQR_JL_Pos)           /*!< 0x00000002 */

+

+#define ADC_JSQR_JEXTSEL_Pos              (2U)

+#define ADC_JSQR_JEXTSEL_Msk              (0x1FUL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x0000007C */

+#define ADC_JSQR_JEXTSEL                  ADC_JSQR_JEXTSEL_Msk                 /*!< ADC external trigger selection for injected group */

+#define ADC_JSQR_JEXTSEL_0                (0x01UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000004 */

+#define ADC_JSQR_JEXTSEL_1                (0x02UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000008 */

+#define ADC_JSQR_JEXTSEL_2                (0x04UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000010 */

+#define ADC_JSQR_JEXTSEL_3                (0x08UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000020 */

+#define ADC_JSQR_JEXTSEL_4                (0x10UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000040 */

+

+#define ADC_JSQR_JEXTEN_Pos               (7U)

+#define ADC_JSQR_JEXTEN_Msk               (0x3UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000180 */

+#define ADC_JSQR_JEXTEN                   ADC_JSQR_JEXTEN_Msk                  /*!< ADC external trigger enable and polarity selection for injected channels */

+#define ADC_JSQR_JEXTEN_0                 (0x1UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000080 */

+#define ADC_JSQR_JEXTEN_1                 (0x2UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000100 */

+

+#define ADC_JSQR_JSQ1_Pos                 (9U)

+#define ADC_JSQR_JSQ1_Msk                 (0x1FUL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00003E00 */

+#define ADC_JSQR_JSQ1                     ADC_JSQR_JSQ1_Msk                    /*!< ADC 1st conversion in injected sequence */

+#define ADC_JSQR_JSQ1_0                   (0x01UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000200 */

+#define ADC_JSQR_JSQ1_1                   (0x02UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000400 */

+#define ADC_JSQR_JSQ1_2                   (0x04UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000800 */

+#define ADC_JSQR_JSQ1_3                   (0x08UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00001000 */

+#define ADC_JSQR_JSQ1_4                   (0x10UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00002000 */

+

+#define ADC_JSQR_JSQ2_Pos                 (15U)

+#define ADC_JSQR_JSQ2_Msk                 (0x1FUL << ADC_JSQR_JSQ2_Pos)        /*!< 0x000F8000 */

+#define ADC_JSQR_JSQ2                     ADC_JSQR_JSQ2_Msk                    /*!< ADC 2nd conversion in injected sequence */

+#define ADC_JSQR_JSQ2_0                   (0x01UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00008000 */

+#define ADC_JSQR_JSQ2_1                   (0x02UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00010000 */

+#define ADC_JSQR_JSQ2_2                   (0x04UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00020000 */

+#define ADC_JSQR_JSQ2_3                   (0x08UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00040000 */

+#define ADC_JSQR_JSQ2_4                   (0x10UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00080000 */

+

+#define ADC_JSQR_JSQ3_Pos                 (21U)

+#define ADC_JSQR_JSQ3_Msk                 (0x1FUL << ADC_JSQR_JSQ3_Pos)        /*!< 0x03E00000 */

+#define ADC_JSQR_JSQ3                     ADC_JSQR_JSQ3_Msk                    /*!< ADC 3rd conversion in injected sequence */

+#define ADC_JSQR_JSQ3_0                   (0x01UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00200000 */

+#define ADC_JSQR_JSQ3_1                   (0x02UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00400000 */

+#define ADC_JSQR_JSQ3_2                   (0x04UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00800000 */

+#define ADC_JSQR_JSQ3_3                   (0x08UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x01000000 */

+#define ADC_JSQR_JSQ3_4                   (0x10UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x02000000 */

+

+#define ADC_JSQR_JSQ4_Pos                 (27U)

+#define ADC_JSQR_JSQ4_Msk                 (0x1FUL << ADC_JSQR_JSQ4_Pos)        /*!< 0xF8000000 */

+#define ADC_JSQR_JSQ4                     ADC_JSQR_JSQ4_Msk                    /*!< ADC 4th conversion in injected sequence */

+#define ADC_JSQR_JSQ4_0                   (0x01UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x08000000 */

+#define ADC_JSQR_JSQ4_1                   (0x02UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x10000000 */

+#define ADC_JSQR_JSQ4_2                   (0x04UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x20000000 */

+#define ADC_JSQR_JSQ4_3                   (0x08UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x40000000 */

+#define ADC_JSQR_JSQ4_4                   (0x10UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_OFR1 register  ********************/

+#define ADC_OFR1_OFFSET1_Pos              (0U)

+#define ADC_OFR1_OFFSET1_Msk              (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR1_OFFSET1                  ADC_OFR1_OFFSET1_Msk                  /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */

+#define ADC_OFR1_OFFSET1_0                (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */

+#define ADC_OFR1_OFFSET1_1                (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */

+#define ADC_OFR1_OFFSET1_2                (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */

+#define ADC_OFR1_OFFSET1_3                (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */

+#define ADC_OFR1_OFFSET1_4                (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */

+#define ADC_OFR1_OFFSET1_5                (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */

+#define ADC_OFR1_OFFSET1_6                (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */

+#define ADC_OFR1_OFFSET1_7                (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */

+#define ADC_OFR1_OFFSET1_8                (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */

+#define ADC_OFR1_OFFSET1_9                (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */

+#define ADC_OFR1_OFFSET1_10               (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */

+#define ADC_OFR1_OFFSET1_11               (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */

+#define ADC_OFR1_OFFSET1_12               (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */

+#define ADC_OFR1_OFFSET1_13               (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */

+#define ADC_OFR1_OFFSET1_14               (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */

+#define ADC_OFR1_OFFSET1_15               (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */

+#define ADC_OFR1_OFFSET1_16               (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */

+#define ADC_OFR1_OFFSET1_17               (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */

+#define ADC_OFR1_OFFSET1_18               (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */

+#define ADC_OFR1_OFFSET1_19               (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */

+#define ADC_OFR1_OFFSET1_20               (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */

+#define ADC_OFR1_OFFSET1_21               (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */

+#define ADC_OFR1_OFFSET1_22               (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */

+#define ADC_OFR1_OFFSET1_23               (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */

+#define ADC_OFR1_OFFSET1_24               (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */

+#define ADC_OFR1_OFFSET1_25               (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR1_OFFSET1_CH_Pos           (26U)

+#define ADC_OFR1_OFFSET1_CH_Msk           (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR1_OFFSET1_CH               ADC_OFR1_OFFSET1_CH_Msk               /*!< ADC Channel selection for the data offset 1 */

+#define ADC_OFR1_OFFSET1_CH_0             (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR1_OFFSET1_CH_1             (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR1_OFFSET1_CH_2             (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR1_OFFSET1_CH_3             (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR1_OFFSET1_CH_4             (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR1_SSATE_Pos                (31U)

+#define ADC_OFR1_SSATE_Msk                (0x1UL << ADC_OFR1_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR1_SSATE                    ADC_OFR1_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR2 register  ********************/

+#define ADC_OFR2_OFFSET2_Pos              (0U)

+#define ADC_OFR2_OFFSET2_Msk              (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR2_OFFSET2                  ADC_OFR2_OFFSET2_Msk                  /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */

+#define ADC_OFR2_OFFSET2_0                (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */

+#define ADC_OFR2_OFFSET2_1                (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */

+#define ADC_OFR2_OFFSET2_2                (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */

+#define ADC_OFR2_OFFSET2_3                (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */

+#define ADC_OFR2_OFFSET2_4                (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */

+#define ADC_OFR2_OFFSET2_5                (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */

+#define ADC_OFR2_OFFSET2_6                (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */

+#define ADC_OFR2_OFFSET2_7                (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */

+#define ADC_OFR2_OFFSET2_8                (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */

+#define ADC_OFR2_OFFSET2_9                (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */

+#define ADC_OFR2_OFFSET2_10               (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */

+#define ADC_OFR2_OFFSET2_11               (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */

+#define ADC_OFR2_OFFSET2_12               (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */

+#define ADC_OFR2_OFFSET2_13               (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */

+#define ADC_OFR2_OFFSET2_14               (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */

+#define ADC_OFR2_OFFSET2_15               (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */

+#define ADC_OFR2_OFFSET2_16               (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */

+#define ADC_OFR2_OFFSET2_17               (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */

+#define ADC_OFR2_OFFSET2_18               (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */

+#define ADC_OFR2_OFFSET2_19               (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */

+#define ADC_OFR2_OFFSET2_20               (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */

+#define ADC_OFR2_OFFSET2_21               (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */

+#define ADC_OFR2_OFFSET2_22               (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */

+#define ADC_OFR2_OFFSET2_23               (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */

+#define ADC_OFR2_OFFSET2_24               (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */

+#define ADC_OFR2_OFFSET2_25               (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR2_OFFSET2_CH_Pos           (26U)

+#define ADC_OFR2_OFFSET2_CH_Msk           (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR2_OFFSET2_CH               ADC_OFR2_OFFSET2_CH_Msk               /*!< ADC Channel selection for the data offset 2 */

+#define ADC_OFR2_OFFSET2_CH_0             (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR2_OFFSET2_CH_1             (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR2_OFFSET2_CH_2             (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR2_OFFSET2_CH_3             (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR2_OFFSET2_CH_4             (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR2_SSATE_Pos                (31U)

+#define ADC_OFR2_SSATE_Msk                (0x1UL << ADC_OFR2_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR2_SSATE                    ADC_OFR2_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR3 register  ********************/

+#define ADC_OFR3_OFFSET3_Pos              (0U)

+#define ADC_OFR3_OFFSET3_Msk              (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR3_OFFSET3                  ADC_OFR3_OFFSET3_Msk                  /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */

+#define ADC_OFR3_OFFSET3_0                (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */

+#define ADC_OFR3_OFFSET3_1                (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */

+#define ADC_OFR3_OFFSET3_2                (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */

+#define ADC_OFR3_OFFSET3_3                (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */

+#define ADC_OFR3_OFFSET3_4                (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */

+#define ADC_OFR3_OFFSET3_5                (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */

+#define ADC_OFR3_OFFSET3_6                (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */

+#define ADC_OFR3_OFFSET3_7                (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */

+#define ADC_OFR3_OFFSET3_8                (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */

+#define ADC_OFR3_OFFSET3_9                (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */

+#define ADC_OFR3_OFFSET3_10               (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */

+#define ADC_OFR3_OFFSET3_11               (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */

+#define ADC_OFR3_OFFSET3_12               (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */

+#define ADC_OFR3_OFFSET3_13               (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */

+#define ADC_OFR3_OFFSET3_14               (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */

+#define ADC_OFR3_OFFSET3_15               (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */

+#define ADC_OFR3_OFFSET3_16               (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */

+#define ADC_OFR3_OFFSET3_17               (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */

+#define ADC_OFR3_OFFSET3_18               (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */

+#define ADC_OFR3_OFFSET3_19               (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */

+#define ADC_OFR3_OFFSET3_20               (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */

+#define ADC_OFR3_OFFSET3_21               (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */

+#define ADC_OFR3_OFFSET3_22               (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */

+#define ADC_OFR3_OFFSET3_23               (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */

+#define ADC_OFR3_OFFSET3_24               (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */

+#define ADC_OFR3_OFFSET3_25               (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR3_OFFSET3_CH_Pos           (26U)

+#define ADC_OFR3_OFFSET3_CH_Msk           (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR3_OFFSET3_CH               ADC_OFR3_OFFSET3_CH_Msk               /*!< ADC Channel selection for the data offset 3 */

+#define ADC_OFR3_OFFSET3_CH_0             (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR3_OFFSET3_CH_1             (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR3_OFFSET3_CH_2             (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR3_OFFSET3_CH_3             (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR3_OFFSET3_CH_4             (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR3_SSATE_Pos                (31U)

+#define ADC_OFR3_SSATE_Msk                (0x1UL << ADC_OFR3_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR3_SSATE                    ADC_OFR3_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR4 register  ********************/

+#define ADC_OFR4_OFFSET4_Pos              (0U)

+#define ADC_OFR4_OFFSET4_Msk              (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR4_OFFSET4                  ADC_OFR4_OFFSET4_Msk                  /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */

+#define ADC_OFR4_OFFSET4_0                (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */

+#define ADC_OFR4_OFFSET4_1                (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */

+#define ADC_OFR4_OFFSET4_2                (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */

+#define ADC_OFR4_OFFSET4_3                (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */

+#define ADC_OFR4_OFFSET4_4                (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */

+#define ADC_OFR4_OFFSET4_5                (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */

+#define ADC_OFR4_OFFSET4_6                (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */

+#define ADC_OFR4_OFFSET4_7                (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */

+#define ADC_OFR4_OFFSET4_8                (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */

+#define ADC_OFR4_OFFSET4_9                (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */

+#define ADC_OFR4_OFFSET4_10               (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */

+#define ADC_OFR4_OFFSET4_11               (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */

+#define ADC_OFR4_OFFSET4_12               (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */

+#define ADC_OFR4_OFFSET4_13               (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */

+#define ADC_OFR4_OFFSET4_14               (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */

+#define ADC_OFR4_OFFSET4_15               (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */

+#define ADC_OFR4_OFFSET4_16               (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */

+#define ADC_OFR4_OFFSET4_17               (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */

+#define ADC_OFR4_OFFSET4_18               (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */

+#define ADC_OFR4_OFFSET4_19               (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */

+#define ADC_OFR4_OFFSET4_20               (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */

+#define ADC_OFR4_OFFSET4_21               (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */

+#define ADC_OFR4_OFFSET4_22               (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */

+#define ADC_OFR4_OFFSET4_23               (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */

+#define ADC_OFR4_OFFSET4_24               (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */

+#define ADC_OFR4_OFFSET4_25               (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR4_OFFSET4_CH_Pos           (26U)

+#define ADC_OFR4_OFFSET4_CH_Msk           (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR4_OFFSET4_CH               ADC_OFR4_OFFSET4_CH_Msk               /*!< ADC Channel selection for the data offset 4 */

+#define ADC_OFR4_OFFSET4_CH_0             (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR4_OFFSET4_CH_1             (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR4_OFFSET4_CH_2             (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR4_OFFSET4_CH_3             (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR4_OFFSET4_CH_4             (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR4_SSATE_Pos                (31U)

+#define ADC_OFR4_SSATE_Msk                (0x1UL << ADC_OFR4_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR4_SSATE                    ADC_OFR4_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_JDR1 register  ********************/

+#define ADC_JDR1_JDATA_Pos                (0U)

+#define ADC_JDR1_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR1_JDATA                    ADC_JDR1_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR1_JDATA_0                  (0x00000001UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR1_JDATA_1                  (0x00000002UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR1_JDATA_2                  (0x00000004UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR1_JDATA_3                  (0x00000008UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR1_JDATA_4                  (0x00000010UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR1_JDATA_5                  (0x00000020UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR1_JDATA_6                  (0x00000040UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR1_JDATA_7                  (0x00000080UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR1_JDATA_8                  (0x00000100UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR1_JDATA_9                  (0x00000200UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR1_JDATA_10                 (0x00000400UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR1_JDATA_11                 (0x00000800UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR1_JDATA_12                 (0x00001000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR1_JDATA_13                 (0x00002000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR1_JDATA_14                 (0x00004000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR1_JDATA_15                 (0x00008000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR1_JDATA_16                 (0x00010000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR1_JDATA_17                 (0x00020000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR1_JDATA_18                 (0x00040000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR1_JDATA_19                 (0x00080000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR1_JDATA_20                 (0x00100000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR1_JDATA_21                 (0x00200000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR1_JDATA_22                 (0x00400000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR1_JDATA_23                 (0x00800000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR1_JDATA_24                 (0x01000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR1_JDATA_25                 (0x02000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR1_JDATA_26                 (0x04000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR1_JDATA_27                 (0x08000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR1_JDATA_28                 (0x10000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR1_JDATA_29                 (0x20000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR1_JDATA_30                 (0x40000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR1_JDATA_31                 (0x80000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR2 register  ********************/

+#define ADC_JDR2_JDATA_Pos                (0U)

+#define ADC_JDR2_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR2_JDATA                    ADC_JDR2_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR2_JDATA_0                  (0x00000001UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR2_JDATA_1                  (0x00000002UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR2_JDATA_2                  (0x00000004UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR2_JDATA_3                  (0x00000008UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR2_JDATA_4                  (0x00000010UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR2_JDATA_5                  (0x00000020UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR2_JDATA_6                  (0x00000040UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR2_JDATA_7                  (0x00000080UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR2_JDATA_8                  (0x00000100UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR2_JDATA_9                  (0x00000200UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR2_JDATA_10                 (0x00000400UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR2_JDATA_11                 (0x00000800UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR2_JDATA_12                 (0x00001000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR2_JDATA_13                 (0x00002000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR2_JDATA_14                 (0x00004000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR2_JDATA_15                 (0x00008000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR2_JDATA_16                 (0x00010000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR2_JDATA_17                 (0x00020000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR2_JDATA_18                 (0x00040000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR2_JDATA_19                 (0x00080000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR2_JDATA_20                 (0x00100000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR2_JDATA_21                 (0x00200000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR2_JDATA_22                 (0x00400000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR2_JDATA_23                 (0x00800000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR2_JDATA_24                 (0x01000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR2_JDATA_25                 (0x02000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR2_JDATA_26                 (0x04000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR2_JDATA_27                 (0x08000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR2_JDATA_28                 (0x10000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR2_JDATA_29                 (0x20000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR2_JDATA_30                 (0x40000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR2_JDATA_31                 (0x80000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR3 register  ********************/

+#define ADC_JDR3_JDATA_Pos                (0U)

+#define ADC_JDR3_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR3_JDATA                    ADC_JDR3_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR3_JDATA_0                  (0x00000001UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR3_JDATA_1                  (0x00000002UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR3_JDATA_2                  (0x00000004UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR3_JDATA_3                  (0x00000008UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR3_JDATA_4                  (0x00000010UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR3_JDATA_5                  (0x00000020UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR3_JDATA_6                  (0x00000040UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR3_JDATA_7                  (0x00000080UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR3_JDATA_8                  (0x00000100UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR3_JDATA_9                  (0x00000200UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR3_JDATA_10                 (0x00000400UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR3_JDATA_11                 (0x00000800UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR3_JDATA_12                 (0x00001000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR3_JDATA_13                 (0x00002000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR3_JDATA_14                 (0x00004000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR3_JDATA_15                 (0x00008000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR3_JDATA_16                 (0x00010000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR3_JDATA_17                 (0x00020000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR3_JDATA_18                 (0x00040000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR3_JDATA_19                 (0x00080000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR3_JDATA_20                 (0x00100000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR3_JDATA_21                 (0x00200000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR3_JDATA_22                 (0x00400000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR3_JDATA_23                 (0x00800000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR3_JDATA_24                 (0x01000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR3_JDATA_25                 (0x02000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR3_JDATA_26                 (0x04000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR3_JDATA_27                 (0x08000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR3_JDATA_28                 (0x10000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR3_JDATA_29                 (0x20000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR3_JDATA_30                 (0x40000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR3_JDATA_31                 (0x80000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR4 register  ********************/

+#define ADC_JDR4_JDATA_Pos                (0U)

+#define ADC_JDR4_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR4_JDATA                    ADC_JDR4_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR4_JDATA_0                  (0x00000001UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR4_JDATA_1                  (0x00000002UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR4_JDATA_2                  (0x00000004UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR4_JDATA_3                  (0x00000008UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR4_JDATA_4                  (0x00000010UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR4_JDATA_5                  (0x00000020UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR4_JDATA_6                  (0x00000040UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR4_JDATA_7                  (0x00000080UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR4_JDATA_8                  (0x00000100UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR4_JDATA_9                  (0x00000200UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR4_JDATA_10                 (0x00000400UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR4_JDATA_11                 (0x00000800UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR4_JDATA_12                 (0x00001000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR4_JDATA_13                 (0x00002000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR4_JDATA_14                 (0x00004000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR4_JDATA_15                 (0x00008000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR4_JDATA_16                 (0x00010000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR4_JDATA_17                 (0x00020000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR4_JDATA_18                 (0x00040000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR4_JDATA_19                 (0x00080000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR4_JDATA_20                 (0x00100000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR4_JDATA_21                 (0x00200000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR4_JDATA_22                 (0x00400000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR4_JDATA_23                 (0x00800000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR4_JDATA_24                 (0x01000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR4_JDATA_25                 (0x02000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR4_JDATA_26                 (0x04000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR4_JDATA_27                 (0x08000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR4_JDATA_28                 (0x10000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR4_JDATA_29                 (0x20000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR4_JDATA_30                 (0x40000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR4_JDATA_31                 (0x80000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_AWD2CR register  ********************/

+#define ADC_AWD2CR_AWD2CH_Pos             (0U)

+#define ADC_AWD2CR_AWD2CH_Msk             (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x000FFFFF */

+#define ADC_AWD2CR_AWD2CH                 ADC_AWD2CR_AWD2CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */

+#define ADC_AWD2CR_AWD2CH_0               (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000001 */

+#define ADC_AWD2CR_AWD2CH_1               (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000002 */

+#define ADC_AWD2CR_AWD2CH_2               (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000004 */

+#define ADC_AWD2CR_AWD2CH_3               (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000008 */

+#define ADC_AWD2CR_AWD2CH_4               (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000010 */

+#define ADC_AWD2CR_AWD2CH_5               (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000020 */

+#define ADC_AWD2CR_AWD2CH_6               (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000040 */

+#define ADC_AWD2CR_AWD2CH_7               (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000080 */

+#define ADC_AWD2CR_AWD2CH_8               (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000100 */

+#define ADC_AWD2CR_AWD2CH_9               (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000200 */

+#define ADC_AWD2CR_AWD2CH_10              (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000400 */

+#define ADC_AWD2CR_AWD2CH_11              (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000800 */

+#define ADC_AWD2CR_AWD2CH_12              (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00001000 */

+#define ADC_AWD2CR_AWD2CH_13              (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00002000 */

+#define ADC_AWD2CR_AWD2CH_14              (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00004000 */

+#define ADC_AWD2CR_AWD2CH_15              (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00008000 */

+#define ADC_AWD2CR_AWD2CH_16              (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00010000 */

+#define ADC_AWD2CR_AWD2CH_17              (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00020000 */

+#define ADC_AWD2CR_AWD2CH_18              (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */

+#define ADC_AWD2CR_AWD2CH_19              (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_AWD3CR register  ********************/

+#define ADC_AWD3CR_AWD3CH_Pos             (0U)

+#define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x000FFFFF */

+#define ADC_AWD3CR_AWD3CH                 ADC_AWD3CR_AWD3CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */

+#define ADC_AWD3CR_AWD3CH_0               (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000001 */

+#define ADC_AWD3CR_AWD3CH_1               (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000002 */

+#define ADC_AWD3CR_AWD3CH_2               (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000004 */

+#define ADC_AWD3CR_AWD3CH_3               (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000008 */

+#define ADC_AWD3CR_AWD3CH_4               (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000010 */

+#define ADC_AWD3CR_AWD3CH_5               (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000020 */

+#define ADC_AWD3CR_AWD3CH_6               (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000040 */

+#define ADC_AWD3CR_AWD3CH_7               (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000080 */

+#define ADC_AWD3CR_AWD3CH_8               (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000100 */

+#define ADC_AWD3CR_AWD3CH_9               (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000200 */

+#define ADC_AWD3CR_AWD3CH_10              (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000400 */

+#define ADC_AWD3CR_AWD3CH_11              (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000800 */

+#define ADC_AWD3CR_AWD3CH_12              (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00001000 */

+#define ADC_AWD3CR_AWD3CH_13              (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00002000 */

+#define ADC_AWD3CR_AWD3CH_14              (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00004000 */

+#define ADC_AWD3CR_AWD3CH_15              (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00008000 */

+#define ADC_AWD3CR_AWD3CH_16              (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00010000 */

+#define ADC_AWD3CR_AWD3CH_17              (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00020000 */

+#define ADC_AWD3CR_AWD3CH_18              (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */

+#define ADC_AWD3CR_AWD3CH_19              (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_DIFSEL register  ********************/

+#define ADC_DIFSEL_DIFSEL_Pos             (0U)

+#define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */

+#define ADC_DIFSEL_DIFSEL                 ADC_DIFSEL_DIFSEL_Msk                 /*!< ADC differential modes for channels 1 to 18 */

+#define ADC_DIFSEL_DIFSEL_0               (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000001 */

+#define ADC_DIFSEL_DIFSEL_1               (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000002 */

+#define ADC_DIFSEL_DIFSEL_2               (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000004 */

+#define ADC_DIFSEL_DIFSEL_3               (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000008 */

+#define ADC_DIFSEL_DIFSEL_4               (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000010 */

+#define ADC_DIFSEL_DIFSEL_5               (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000020 */

+#define ADC_DIFSEL_DIFSEL_6               (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000040 */

+#define ADC_DIFSEL_DIFSEL_7               (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000080 */

+#define ADC_DIFSEL_DIFSEL_8               (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000100 */

+#define ADC_DIFSEL_DIFSEL_9               (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000200 */

+#define ADC_DIFSEL_DIFSEL_10              (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000400 */

+#define ADC_DIFSEL_DIFSEL_11              (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000800 */

+#define ADC_DIFSEL_DIFSEL_12              (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00001000 */

+#define ADC_DIFSEL_DIFSEL_13              (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00002000 */

+#define ADC_DIFSEL_DIFSEL_14              (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00004000 */

+#define ADC_DIFSEL_DIFSEL_15              (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00008000 */

+#define ADC_DIFSEL_DIFSEL_16              (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00010000 */

+#define ADC_DIFSEL_DIFSEL_17              (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00020000 */

+#define ADC_DIFSEL_DIFSEL_18              (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00040000 */

+#define ADC_DIFSEL_DIFSEL_19              (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_CALFACT register  ********************/

+#define ADC_CALFACT_CALFACT_S_Pos         (0U)

+#define ADC_CALFACT_CALFACT_S_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */

+#define ADC_CALFACT_CALFACT_S             ADC_CALFACT_CALFACT_S_Msk              /*!< ADC calibration factors in single-ended mode */

+#define ADC_CALFACT_CALFACT_S_0           (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */

+#define ADC_CALFACT_CALFACT_S_1           (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */

+#define ADC_CALFACT_CALFACT_S_2           (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */

+#define ADC_CALFACT_CALFACT_S_3           (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */

+#define ADC_CALFACT_CALFACT_S_4           (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */

+#define ADC_CALFACT_CALFACT_S_5           (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */

+#define ADC_CALFACT_CALFACT_S_6           (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */

+#define ADC_CALFACT_CALFACT_S_7           (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */

+#define ADC_CALFACT_CALFACT_S_8           (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */

+#define ADC_CALFACT_CALFACT_S_9           (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */

+#define ADC_CALFACT_CALFACT_S_10          (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */

+#define ADC_CALFACT_CALFACT_D_Pos         (16U)

+#define ADC_CALFACT_CALFACT_D_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */

+#define ADC_CALFACT_CALFACT_D             ADC_CALFACT_CALFACT_D_Msk              /*!< ADC calibration factors in differential mode */

+#define ADC_CALFACT_CALFACT_D_0           (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */

+#define ADC_CALFACT_CALFACT_D_1           (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */

+#define ADC_CALFACT_CALFACT_D_2           (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */

+#define ADC_CALFACT_CALFACT_D_3           (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */

+#define ADC_CALFACT_CALFACT_D_4           (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */

+#define ADC_CALFACT_CALFACT_D_5           (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */

+#define ADC_CALFACT_CALFACT_D_6           (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */

+#define ADC_CALFACT_CALFACT_D_7           (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */

+#define ADC_CALFACT_CALFACT_D_8           (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */

+#define ADC_CALFACT_CALFACT_D_9           (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */

+#define ADC_CALFACT_CALFACT_D_10          (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */

+

+/********************  Bit definition for ADC_CALFACT2 register  ********************/

+#define ADC_CALFACT2_LINCALFACT_Pos       (0U)

+#define ADC_CALFACT2_LINCALFACT_Msk       (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */

+#define ADC_CALFACT2_LINCALFACT           ADC_CALFACT2_LINCALFACT_Msk                   /*!< ADC Linearity calibration factors */

+#define ADC_CALFACT2_LINCALFACT_0         (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */

+#define ADC_CALFACT2_LINCALFACT_1         (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */

+#define ADC_CALFACT2_LINCALFACT_2         (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */

+#define ADC_CALFACT2_LINCALFACT_3         (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */

+#define ADC_CALFACT2_LINCALFACT_4         (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */

+#define ADC_CALFACT2_LINCALFACT_5         (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */

+#define ADC_CALFACT2_LINCALFACT_6         (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */

+#define ADC_CALFACT2_LINCALFACT_7         (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */

+#define ADC_CALFACT2_LINCALFACT_8         (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */

+#define ADC_CALFACT2_LINCALFACT_9         (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */

+#define ADC_CALFACT2_LINCALFACT_10        (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */

+#define ADC_CALFACT2_LINCALFACT_11        (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */

+#define ADC_CALFACT2_LINCALFACT_12        (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */

+#define ADC_CALFACT2_LINCALFACT_13        (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */

+#define ADC_CALFACT2_LINCALFACT_14        (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */

+#define ADC_CALFACT2_LINCALFACT_15        (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */

+#define ADC_CALFACT2_LINCALFACT_16        (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */

+#define ADC_CALFACT2_LINCALFACT_17        (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */

+#define ADC_CALFACT2_LINCALFACT_18        (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */

+#define ADC_CALFACT2_LINCALFACT_19        (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */

+#define ADC_CALFACT2_LINCALFACT_20        (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */

+#define ADC_CALFACT2_LINCALFACT_21        (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */

+#define ADC_CALFACT2_LINCALFACT_22        (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */

+#define ADC_CALFACT2_LINCALFACT_23        (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */

+#define ADC_CALFACT2_LINCALFACT_24        (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */

+#define ADC_CALFACT2_LINCALFACT_25        (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */

+#define ADC_CALFACT2_LINCALFACT_26        (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */

+#define ADC_CALFACT2_LINCALFACT_27        (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */

+#define ADC_CALFACT2_LINCALFACT_28        (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */

+#define ADC_CALFACT2_LINCALFACT_29        (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */

+

+/*************************  ADC Common registers  *****************************/

+/********************  Bit definition for ADC_CSR register  ********************/

+#define ADC_CSR_ADRDY_MST_Pos             (0U)

+#define ADC_CSR_ADRDY_MST_Msk             (0x1UL << ADC_CSR_ADRDY_MST_Pos)     /*!< 0x00000001 */

+#define ADC_CSR_ADRDY_MST                 ADC_CSR_ADRDY_MST_Msk                /*!< Master ADC ready */

+#define ADC_CSR_EOSMP_MST_Pos             (1U)

+#define ADC_CSR_EOSMP_MST_Msk             (0x1UL << ADC_CSR_EOSMP_MST_Pos)     /*!< 0x00000002 */

+#define ADC_CSR_EOSMP_MST                 ADC_CSR_EOSMP_MST_Msk                /*!< End of sampling phase flag of the master ADC */

+#define ADC_CSR_EOC_MST_Pos               (2U)

+#define ADC_CSR_EOC_MST_Msk               (0x1UL << ADC_CSR_EOC_MST_Pos)       /*!< 0x00000004 */

+#define ADC_CSR_EOC_MST                   ADC_CSR_EOC_MST_Msk                  /*!< End of regular conversion of the master ADC */

+#define ADC_CSR_EOS_MST_Pos               (3U)

+#define ADC_CSR_EOS_MST_Msk               (0x1UL << ADC_CSR_EOS_MST_Pos)       /*!< 0x00000008 */

+#define ADC_CSR_EOS_MST                   ADC_CSR_EOS_MST_Msk                  /*!< End of regular sequence flag of the master ADC */

+#define ADC_CSR_OVR_MST_Pos               (4U)

+#define ADC_CSR_OVR_MST_Msk               (0x1UL << ADC_CSR_OVR_MST_Pos)       /*!< 0x00000010 */

+#define ADC_CSR_OVR_MST                   ADC_CSR_OVR_MST_Msk                  /*!< Overrun flag of the master ADC */

+#define ADC_CSR_JEOC_MST_Pos              (5U)

+#define ADC_CSR_JEOC_MST_Msk              (0x1UL << ADC_CSR_JEOC_MST_Pos)      /*!< 0x00000020 */

+#define ADC_CSR_JEOC_MST                  ADC_CSR_JEOC_MST_Msk                 /*!< End of injected conversion of the master ADC */

+#define ADC_CSR_JEOS_MST_Pos              (6U)

+#define ADC_CSR_JEOS_MST_Msk              (0x1UL << ADC_CSR_JEOS_MST_Pos)      /*!< 0x00000040 */

+#define ADC_CSR_JEOS_MST                  ADC_CSR_JEOS_MST_Msk                 /*!< End of injected sequence flag of the master ADC */

+#define ADC_CSR_AWD1_MST_Pos              (7U)

+#define ADC_CSR_AWD1_MST_Msk              (0x1UL << ADC_CSR_AWD1_MST_Pos)      /*!< 0x00000080 */

+#define ADC_CSR_AWD1_MST                  ADC_CSR_AWD1_MST_Msk                 /*!< Analog watchdog 1 flag of the master ADC */

+#define ADC_CSR_AWD2_MST_Pos              (8U)

+#define ADC_CSR_AWD2_MST_Msk              (0x1UL << ADC_CSR_AWD2_MST_Pos)      /*!< 0x00000100 */

+#define ADC_CSR_AWD2_MST                  ADC_CSR_AWD2_MST_Msk                 /*!< Analog watchdog 2 flag of the master ADC */

+#define ADC_CSR_AWD3_MST_Pos              (9U)

+#define ADC_CSR_AWD3_MST_Msk              (0x1UL << ADC_CSR_AWD3_MST_Pos)      /*!< 0x00000200 */

+#define ADC_CSR_AWD3_MST                  ADC_CSR_AWD3_MST_Msk                 /*!< Analog watchdog 3 flag of the master ADC */

+#define ADC_CSR_JQOVF_MST_Pos             (10U)

+#define ADC_CSR_JQOVF_MST_Msk             (0x1UL << ADC_CSR_JQOVF_MST_Pos)     /*!< 0x00000400 */

+#define ADC_CSR_JQOVF_MST                 ADC_CSR_JQOVF_MST_Msk                /*!< Injected context queue overflow flag of the master ADC */

+#define ADC_CSR_ADRDY_SLV_Pos             (16U)

+#define ADC_CSR_ADRDY_SLV_Msk             (0x1UL << ADC_CSR_ADRDY_SLV_Pos)     /*!< 0x00010000 */

+#define ADC_CSR_ADRDY_SLV                 ADC_CSR_ADRDY_SLV_Msk                /*!< Slave ADC ready */

+#define ADC_CSR_EOSMP_SLV_Pos             (17U)

+#define ADC_CSR_EOSMP_SLV_Msk             (0x1UL << ADC_CSR_EOSMP_SLV_Pos)     /*!< 0x00020000 */

+#define ADC_CSR_EOSMP_SLV                 ADC_CSR_EOSMP_SLV_Msk                /*!< End of sampling phase flag of the slave ADC */

+#define ADC_CSR_EOC_SLV_Pos               (18U)

+#define ADC_CSR_EOC_SLV_Msk               (0x1UL << ADC_CSR_EOC_SLV_Pos)       /*!< 0x00040000 */

+#define ADC_CSR_EOC_SLV                   ADC_CSR_EOC_SLV_Msk                  /*!< End of regular conversion of the slave ADC */

+#define ADC_CSR_EOS_SLV_Pos               (19U)

+#define ADC_CSR_EOS_SLV_Msk               (0x1UL << ADC_CSR_EOS_SLV_Pos)       /*!< 0x00080000 */

+#define ADC_CSR_EOS_SLV                   ADC_CSR_EOS_SLV_Msk                  /*!< End of regular sequence flag of the slave ADC */

+#define ADC_CSR_OVR_SLV_Pos               (20U)

+#define ADC_CSR_OVR_SLV_Msk               (0x1UL << ADC_CSR_OVR_SLV_Pos)       /*!< 0x00100000 */

+#define ADC_CSR_OVR_SLV                   ADC_CSR_OVR_SLV_Msk                  /*!< Overrun flag of the slave ADC */

+#define ADC_CSR_JEOC_SLV_Pos              (21U)

+#define ADC_CSR_JEOC_SLV_Msk              (0x1UL << ADC_CSR_JEOC_SLV_Pos)      /*!< 0x00200000 */

+#define ADC_CSR_JEOC_SLV                  ADC_CSR_JEOC_SLV_Msk                 /*!< End of injected conversion of the slave ADC */

+#define ADC_CSR_JEOS_SLV_Pos              (22U)

+#define ADC_CSR_JEOS_SLV_Msk              (0x1UL << ADC_CSR_JEOS_SLV_Pos)      /*!< 0x00400000 */

+#define ADC_CSR_JEOS_SLV                  ADC_CSR_JEOS_SLV_Msk                 /*!< End of injected sequence flag of the slave ADC */

+#define ADC_CSR_AWD1_SLV_Pos              (23U)

+#define ADC_CSR_AWD1_SLV_Msk              (0x1UL << ADC_CSR_AWD1_SLV_Pos)      /*!< 0x00800000 */

+#define ADC_CSR_AWD1_SLV                  ADC_CSR_AWD1_SLV_Msk                 /*!< Analog watchdog 1 flag of the slave ADC */

+#define ADC_CSR_AWD2_SLV_Pos              (24U)

+#define ADC_CSR_AWD2_SLV_Msk              (0x1UL << ADC_CSR_AWD2_SLV_Pos)      /*!< 0x01000000 */

+#define ADC_CSR_AWD2_SLV                  ADC_CSR_AWD2_SLV_Msk                 /*!< Analog watchdog 2 flag of the slave ADC */

+#define ADC_CSR_AWD3_SLV_Pos              (25U)

+#define ADC_CSR_AWD3_SLV_Msk              (0x1UL << ADC_CSR_AWD3_SLV_Pos)      /*!< 0x02000000 */

+#define ADC_CSR_AWD3_SLV                  ADC_CSR_AWD3_SLV_Msk                 /*!< Analog watchdog 3 flag of the slave ADC */

+#define ADC_CSR_JQOVF_SLV_Pos             (26U)

+#define ADC_CSR_JQOVF_SLV_Msk             (0x1UL << ADC_CSR_JQOVF_SLV_Pos)     /*!< 0x04000000 */

+#define ADC_CSR_JQOVF_SLV                 ADC_CSR_JQOVF_SLV_Msk                /*!< Injected context queue overflow flag of the slave ADC */

+

+/********************  Bit definition for ADC_CCR register  ********************/

+#define ADC_CCR_DUAL_Pos                  (0U)

+#define ADC_CCR_DUAL_Msk                  (0x1FUL << ADC_CCR_DUAL_Pos)          /*!< 0x0000001F */

+#define ADC_CCR_DUAL                      ADC_CCR_DUAL_Msk                      /*!< Dual ADC mode selection */

+#define ADC_CCR_DUAL_0                    (0x01UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000001 */

+#define ADC_CCR_DUAL_1                    (0x02UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000002 */

+#define ADC_CCR_DUAL_2                    (0x04UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000004 */

+#define ADC_CCR_DUAL_3                    (0x08UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000008 */

+#define ADC_CCR_DUAL_4                    (0x10UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000010 */

+

+#define ADC_CCR_DELAY_Pos                 (8U)

+#define ADC_CCR_DELAY_Msk                 (0xFUL << ADC_CCR_DELAY_Pos)          /*!< 0x00000F00 */

+#define ADC_CCR_DELAY                     ADC_CCR_DELAY_Msk                     /*!< Delay between 2 sampling phases */

+#define ADC_CCR_DELAY_0                   (0x1UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000100 */

+#define ADC_CCR_DELAY_1                   (0x2UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000200 */

+#define ADC_CCR_DELAY_2                   (0x4UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000400 */

+#define ADC_CCR_DELAY_3                   (0x8UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000800 */

+

+

+#define ADC_CCR_DAMDF_Pos                 (14U)

+#define ADC_CCR_DAMDF_Msk                 (0x3UL << ADC_CCR_DAMDF_Pos)          /*!< 0x0000C000 */

+#define ADC_CCR_DAMDF                     ADC_CCR_DAMDF_Msk                     /*!< Dual ADC mode Data format */

+#define ADC_CCR_DAMDF_0                   (0x1UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00004000 */

+#define ADC_CCR_DAMDF_1                   (0x2UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00008000 */

+

+#define ADC_CCR_CKMODE_Pos                (16U)

+#define ADC_CCR_CKMODE_Msk                (0x3UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00030000 */

+#define ADC_CCR_CKMODE                    ADC_CCR_CKMODE_Msk                    /*!< ADC clock mode */

+#define ADC_CCR_CKMODE_0                  (0x1UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00010000 */

+#define ADC_CCR_CKMODE_1                  (0x2UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00020000 */

+

+#define ADC_CCR_PRESC_Pos                 (18U)

+#define ADC_CCR_PRESC_Msk                 (0xFUL << ADC_CCR_PRESC_Pos)          /*!< 0x003C0000 */

+#define ADC_CCR_PRESC                     ADC_CCR_PRESC_Msk                     /*!< ADC prescaler */

+#define ADC_CCR_PRESC_0                   (0x1UL << ADC_CCR_PRESC_Pos)          /*!< 0x00040000 */

+#define ADC_CCR_PRESC_1                   (0x2UL << ADC_CCR_PRESC_Pos)          /*!< 0x00080000 */

+#define ADC_CCR_PRESC_2                   (0x4UL << ADC_CCR_PRESC_Pos)          /*!< 0x00100000 */

+#define ADC_CCR_PRESC_3                   (0x8UL << ADC_CCR_PRESC_Pos)          /*!< 0x00200000 */

+

+#define ADC_CCR_VREFEN_Pos                (22U)

+#define ADC_CCR_VREFEN_Msk                (0x1UL << ADC_CCR_VREFEN_Pos)         /*!< 0x00400000 */

+#define ADC_CCR_VREFEN                    ADC_CCR_VREFEN_Msk                    /*!< VREFINT enable */

+#define ADC_CCR_TSEN_Pos                  (23U)

+#define ADC_CCR_TSEN_Msk                  (0x1UL << ADC_CCR_TSEN_Pos)           /*!< 0x00800000 */

+#define ADC_CCR_TSEN                      ADC_CCR_TSEN_Msk                      /*!< Temperature sensor enable */

+#define ADC_CCR_VBATEN_Pos                (24U)

+#define ADC_CCR_VBATEN_Msk                (0x1UL << ADC_CCR_VBATEN_Pos)         /*!< 0x01000000 */

+#define ADC_CCR_VBATEN                    ADC_CCR_VBATEN_Msk                    /*!< VBAT enable */

+

+/********************  Bit definition for ADC_CDR register  *******************/

+#define ADC_CDR_RDATA_MST_Pos             (0U)

+#define ADC_CDR_RDATA_MST_Msk             (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)   /*!< 0x0000FFFF */

+#define ADC_CDR_RDATA_MST                 ADC_CDR_RDATA_MST_Msk                 /*!< ADC multimode master group regular conversion data */

+

+#define ADC_CDR_RDATA_SLV_Pos             (16U)

+#define ADC_CDR_RDATA_SLV_Msk             (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)   /*!< 0xFFFF0000 */

+#define ADC_CDR_RDATA_SLV                 ADC_CDR_RDATA_SLV_Msk                 /*!< ADC multimode slave group regular conversion data */

+

+/********************  Bit definition for ADC_CDR2 register  ******************/

+#define ADC_CDR2_RDATA_ALT_Pos            (0U)

+#define ADC_CDR2_RDATA_ALT_Msk            (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */

+#define ADC_CDR2_RDATA_ALT                ADC_CDR2_RDATA_ALT_Msk                   /*!< Regular data of the master/slave alternated ADCs */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                   VREFBUF                                  */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for VREFBUF_CSR register  ****************/

+#define VREFBUF_CSR_ENVR_Pos        (0U)

+#define VREFBUF_CSR_ENVR_Msk        (0x1UL << VREFBUF_CSR_ENVR_Pos)            /*!< 0x00000001 */

+#define VREFBUF_CSR_ENVR            VREFBUF_CSR_ENVR_Msk                       /*!<Voltage reference buffer enable */

+#define VREFBUF_CSR_HIZ_Pos         (1U)

+#define VREFBUF_CSR_HIZ_Msk         (0x1UL << VREFBUF_CSR_HIZ_Pos)             /*!< 0x00000002 */

+#define VREFBUF_CSR_HIZ             VREFBUF_CSR_HIZ_Msk                        /*!<High impedance mode             */

+#define VREFBUF_CSR_VRR_Pos         (3U)

+#define VREFBUF_CSR_VRR_Msk         (0x1UL << VREFBUF_CSR_VRR_Pos)             /*!< 0x00000008 */

+#define VREFBUF_CSR_VRR             VREFBUF_CSR_VRR_Msk                        /*!<Voltage reference buffer ready  */

+#define VREFBUF_CSR_VRS_Pos         (4U)

+#define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */

+#define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */

+

+#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */

+#define VREFBUF_CSR_VRS_OUT2_Pos    (4U)

+#define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */

+#define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */

+#define VREFBUF_CSR_VRS_OUT3_Pos    (5U)

+#define VREFBUF_CSR_VRS_OUT3_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)        /*!< 0x00000020 */

+#define VREFBUF_CSR_VRS_OUT3        VREFBUF_CSR_VRS_OUT3_Msk                   /*!<Voltage reference VREF_OUT3     */

+#define VREFBUF_CSR_VRS_OUT4_Pos    (4U)

+#define VREFBUF_CSR_VRS_OUT4_Msk    (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)        /*!< 0x00000030 */

+#define VREFBUF_CSR_VRS_OUT4        VREFBUF_CSR_VRS_OUT4_Msk                   /*!<Voltage reference VREF_OUT4     */

+

+/*******************  Bit definition for VREFBUF_CCR register  ****************/

+#define VREFBUF_CCR_TRIM_Pos        (0U)

+#define VREFBUF_CCR_TRIM_Msk        (0x3FUL << VREFBUF_CCR_TRIM_Pos)           /*!< 0x0000003F */

+#define VREFBUF_CCR_TRIM            VREFBUF_CCR_TRIM_Msk                       /*!<TRIM[5:0] bits (Trimming code)  */

+

+/******************************************************************************/

+/*                                                                            */

+/*                 Flexible Datarate Controller Area Network                  */

+/*                                                                            */

+/******************************************************************************/

+/*!<FDCAN control and status registers */

+/*****************  Bit definition for FDCAN_CREL register  *******************/

+#define FDCAN_CREL_DAY_Pos        (0U)

+#define FDCAN_CREL_DAY_Msk        (0xFFUL << FDCAN_CREL_DAY_Pos)               /*!< 0x000000FF */

+#define FDCAN_CREL_DAY            FDCAN_CREL_DAY_Msk                           /*!<Timestamp Day                           */

+#define FDCAN_CREL_MON_Pos        (8U)

+#define FDCAN_CREL_MON_Msk        (0xFFUL << FDCAN_CREL_MON_Pos)               /*!< 0x0000FF00 */

+#define FDCAN_CREL_MON            FDCAN_CREL_MON_Msk                           /*!<Timestamp Month                         */

+#define FDCAN_CREL_YEAR_Pos       (16U)

+#define FDCAN_CREL_YEAR_Msk       (0xFUL << FDCAN_CREL_YEAR_Pos)               /*!< 0x000F0000 */

+#define FDCAN_CREL_YEAR           FDCAN_CREL_YEAR_Msk                          /*!<Timestamp Year                          */

+#define FDCAN_CREL_SUBSTEP_Pos    (20U)

+#define FDCAN_CREL_SUBSTEP_Msk    (0xFUL << FDCAN_CREL_SUBSTEP_Pos)            /*!< 0x00F00000 */

+#define FDCAN_CREL_SUBSTEP        FDCAN_CREL_SUBSTEP_Msk                       /*!<Sub-step of Core release                */

+#define FDCAN_CREL_STEP_Pos       (24U)

+#define FDCAN_CREL_STEP_Msk       (0xFUL << FDCAN_CREL_STEP_Pos)               /*!< 0x0F000000 */

+#define FDCAN_CREL_STEP           FDCAN_CREL_STEP_Msk                          /*!<Step of Core release                    */

+#define FDCAN_CREL_REL_Pos        (28U)

+#define FDCAN_CREL_REL_Msk        (0xFUL << FDCAN_CREL_REL_Pos)                /*!< 0xF0000000 */

+#define FDCAN_CREL_REL            FDCAN_CREL_REL_Msk                           /*!<Core release                            */

+

+/*****************  Bit definition for FDCAN_ENDN register  *******************/

+#define FDCAN_ENDN_ETV_Pos        (0U)

+#define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endiannes Test Value                    */

+

+/*****************  Bit definition for FDCAN_DBTP register  *******************/

+#define FDCAN_DBTP_DSJW_Pos       (0U)

+#define FDCAN_DBTP_DSJW_Msk       (0xFUL << FDCAN_DBTP_DSJW_Pos)               /*!< 0x0000000F */

+#define FDCAN_DBTP_DSJW           FDCAN_DBTP_DSJW_Msk                          /*!<Synchronization Jump Width              */

+#define FDCAN_DBTP_DTSEG2_Pos     (4U)

+#define FDCAN_DBTP_DTSEG2_Msk     (0xFUL << FDCAN_DBTP_DTSEG2_Pos)             /*!< 0x000000F0 */

+#define FDCAN_DBTP_DTSEG2         FDCAN_DBTP_DTSEG2_Msk                        /*!<Data time segment after sample point    */

+#define FDCAN_DBTP_DTSEG1_Pos     (8U)

+#define FDCAN_DBTP_DTSEG1_Msk     (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)            /*!< 0x00001F00 */

+#define FDCAN_DBTP_DTSEG1         FDCAN_DBTP_DTSEG1_Msk                        /*!<Data time segment before sample point   */

+#define FDCAN_DBTP_DBRP_Pos       (16U)

+#define FDCAN_DBTP_DBRP_Msk       (0x1FUL << FDCAN_DBTP_DBRP_Pos)              /*!< 0x001F0000 */

+#define FDCAN_DBTP_DBRP           FDCAN_DBTP_DBRP_Msk                          /*!<Data BIt Rate Prescaler                 */

+#define FDCAN_DBTP_TDC_Pos        (23U)

+#define FDCAN_DBTP_TDC_Msk        (0x1UL << FDCAN_DBTP_TDC_Pos)                /*!< 0x00800000 */

+#define FDCAN_DBTP_TDC            FDCAN_DBTP_TDC_Msk                           /*!<Transceiver Delay Compensation          */

+

+/*****************  Bit definition for FDCAN_TEST register  *******************/

+#define FDCAN_TEST_LBCK_Pos       (4U)

+#define FDCAN_TEST_LBCK_Msk       (0x1UL << FDCAN_TEST_LBCK_Pos)               /*!< 0x00000010 */

+#define FDCAN_TEST_LBCK           FDCAN_TEST_LBCK_Msk                          /*!<Loop Back mode                           */

+#define FDCAN_TEST_TX_Pos         (5U)

+#define FDCAN_TEST_TX_Msk         (0x3UL << FDCAN_TEST_TX_Pos)                 /*!< 0x00000060 */

+#define FDCAN_TEST_TX             FDCAN_TEST_TX_Msk                            /*!<Control of Transmit Pin                  */

+#define FDCAN_TEST_RX_Pos         (7U)

+#define FDCAN_TEST_RX_Msk         (0x1UL << FDCAN_TEST_RX_Pos)                 /*!< 0x00000080 */

+#define FDCAN_TEST_RX             FDCAN_TEST_RX_Msk                            /*!<Receive Pin                              */

+

+/*****************  Bit definition for FDCAN_RWD register  ********************/

+#define FDCAN_RWD_WDC_Pos         (0U)

+#define FDCAN_RWD_WDC_Msk         (0xFFUL << FDCAN_RWD_WDC_Pos)                /*!< 0x000000FF */

+#define FDCAN_RWD_WDC             FDCAN_RWD_WDC_Msk                            /*!<Watchdog configuration                   */

+#define FDCAN_RWD_WDV_Pos         (8U)

+#define FDCAN_RWD_WDV_Msk         (0xFFUL << FDCAN_RWD_WDV_Pos)                /*!< 0x0000FF00 */

+#define FDCAN_RWD_WDV             FDCAN_RWD_WDV_Msk                            /*!<Watchdog value                           */

+

+/*****************  Bit definition for FDCAN_CCCR register  ********************/

+#define FDCAN_CCCR_INIT_Pos       (0U)

+#define FDCAN_CCCR_INIT_Msk       (0x1UL << FDCAN_CCCR_INIT_Pos)               /*!< 0x00000001 */

+#define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!<Initialization                           */

+#define FDCAN_CCCR_CCE_Pos        (1U)

+#define FDCAN_CCCR_CCE_Msk        (0x1UL << FDCAN_CCCR_CCE_Pos)                /*!< 0x00000002 */

+#define FDCAN_CCCR_CCE            FDCAN_CCCR_CCE_Msk                           /*!<Configuration Change Enable              */

+#define FDCAN_CCCR_ASM_Pos        (2U)

+#define FDCAN_CCCR_ASM_Msk        (0x1UL << FDCAN_CCCR_ASM_Pos)                /*!< 0x00000004 */

+#define FDCAN_CCCR_ASM            FDCAN_CCCR_ASM_Msk                           /*!<ASM Restricted Operation Mode            */

+#define FDCAN_CCCR_CSA_Pos        (3U)

+#define FDCAN_CCCR_CSA_Msk        (0x1UL << FDCAN_CCCR_CSA_Pos)                /*!< 0x00000008 */

+#define FDCAN_CCCR_CSA            FDCAN_CCCR_CSA_Msk                           /*!<Clock Stop Acknowledge                   */

+#define FDCAN_CCCR_CSR_Pos        (4U)

+#define FDCAN_CCCR_CSR_Msk        (0x1UL << FDCAN_CCCR_CSR_Pos)                /*!< 0x00000010 */

+#define FDCAN_CCCR_CSR            FDCAN_CCCR_CSR_Msk                           /*!<Clock Stop Request                       */

+#define FDCAN_CCCR_MON_Pos        (5U)

+#define FDCAN_CCCR_MON_Msk        (0x1UL << FDCAN_CCCR_MON_Pos)                /*!< 0x00000020 */

+#define FDCAN_CCCR_MON            FDCAN_CCCR_MON_Msk                           /*!<Bus Monitoring Mode                      */

+#define FDCAN_CCCR_DAR_Pos        (6U)

+#define FDCAN_CCCR_DAR_Msk        (0x1UL << FDCAN_CCCR_DAR_Pos)                /*!< 0x00000040 */

+#define FDCAN_CCCR_DAR            FDCAN_CCCR_DAR_Msk                           /*!<Disable Automatic Retransmission         */

+#define FDCAN_CCCR_TEST_Pos       (7U)

+#define FDCAN_CCCR_TEST_Msk       (0x1UL << FDCAN_CCCR_TEST_Pos)               /*!< 0x00000080 */

+#define FDCAN_CCCR_TEST           FDCAN_CCCR_TEST_Msk                          /*!<Test Mode Enable                         */

+#define FDCAN_CCCR_FDOE_Pos       (8U)

+#define FDCAN_CCCR_FDOE_Msk       (0x1UL << FDCAN_CCCR_FDOE_Pos)               /*!< 0x00000100 */

+#define FDCAN_CCCR_FDOE           FDCAN_CCCR_FDOE_Msk                          /*!<FD Operation Enable                      */

+#define FDCAN_CCCR_BRSE_Pos       (9U)

+#define FDCAN_CCCR_BRSE_Msk       (0x1UL << FDCAN_CCCR_BRSE_Pos)               /*!< 0x00000200 */

+#define FDCAN_CCCR_BRSE           FDCAN_CCCR_BRSE_Msk                          /*!<FDCAN Bit Rate Switching                 */

+#define FDCAN_CCCR_PXHD_Pos       (12U)

+#define FDCAN_CCCR_PXHD_Msk       (0x1UL << FDCAN_CCCR_PXHD_Pos)               /*!< 0x00001000 */

+#define FDCAN_CCCR_PXHD           FDCAN_CCCR_PXHD_Msk                          /*!<Protocol Exception Handling Disable      */

+#define FDCAN_CCCR_EFBI_Pos       (13U)

+#define FDCAN_CCCR_EFBI_Msk       (0x1UL << FDCAN_CCCR_EFBI_Pos)               /*!< 0x00002000 */

+#define FDCAN_CCCR_EFBI           FDCAN_CCCR_EFBI_Msk                          /*!<Edge Filtering during Bus Integration    */

+#define FDCAN_CCCR_TXP_Pos        (14U)

+#define FDCAN_CCCR_TXP_Msk        (0x1UL << FDCAN_CCCR_TXP_Pos)                /*!< 0x00004000 */

+#define FDCAN_CCCR_TXP            FDCAN_CCCR_TXP_Msk                           /*!<Two CAN bit times Pause                  */

+#define FDCAN_CCCR_NISO_Pos       (15U)

+#define FDCAN_CCCR_NISO_Msk       (0x1UL << FDCAN_CCCR_NISO_Pos)               /*!< 0x00008000 */

+#define FDCAN_CCCR_NISO           FDCAN_CCCR_NISO_Msk                          /*!<Non ISO Operation                        */

+

+/*****************  Bit definition for FDCAN_NBTP register  ********************/

+#define FDCAN_NBTP_NTSEG2_Pos     (0U)

+#define FDCAN_NBTP_NTSEG2_Msk     (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)            /*!< 0x0000007F */

+#define FDCAN_NBTP_NTSEG2         FDCAN_NBTP_NTSEG2_Msk                        /*!<Nominal Time segment after sample point  */

+#define FDCAN_NBTP_NTSEG1_Pos     (8U)

+#define FDCAN_NBTP_NTSEG1_Msk     (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)            /*!< 0x0000FF00 */

+#define FDCAN_NBTP_NTSEG1         FDCAN_NBTP_NTSEG1_Msk                        /*!<Nominal Time segment before sample point */

+#define FDCAN_NBTP_NBRP_Pos       (16U)

+#define FDCAN_NBTP_NBRP_Msk       (0x1FFUL << FDCAN_NBTP_NBRP_Pos)             /*!< 0x01FF0000 */

+#define FDCAN_NBTP_NBRP           FDCAN_NBTP_NBRP_Msk                          /*!<Bit Rate Prescaler                       */

+#define FDCAN_NBTP_NSJW_Pos       (25U)

+#define FDCAN_NBTP_NSJW_Msk       (0x7FUL << FDCAN_NBTP_NSJW_Pos)              /*!< 0xFE000000 */

+#define FDCAN_NBTP_NSJW           FDCAN_NBTP_NSJW_Msk                          /*!<Nominal (Re)Synchronization Jump Width   */

+

+/*****************  Bit definition for FDCAN_TSCC register  ********************/

+#define FDCAN_TSCC_TSS_Pos        (0U)

+#define FDCAN_TSCC_TSS_Msk        (0x3UL << FDCAN_TSCC_TSS_Pos)                /*!< 0x00000003 */

+#define FDCAN_TSCC_TSS            FDCAN_TSCC_TSS_Msk                           /*!<Timestamp Select                         */

+#define FDCAN_TSCC_TCP_Pos        (16U)

+#define FDCAN_TSCC_TCP_Msk        (0xFUL << FDCAN_TSCC_TCP_Pos)                /*!< 0x000F0000 */

+#define FDCAN_TSCC_TCP            FDCAN_TSCC_TCP_Msk                           /*!<Timestamp Counter Prescaler              */

+

+/*****************  Bit definition for FDCAN_TSCV register  ********************/

+#define FDCAN_TSCV_TSC_Pos        (0U)

+#define FDCAN_TSCV_TSC_Msk        (0xFFFFUL << FDCAN_TSCV_TSC_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TSCV_TSC            FDCAN_TSCV_TSC_Msk                           /*!<Timestamp Counter                        */

+

+/*****************  Bit definition for FDCAN_TOCC register  ********************/

+#define FDCAN_TOCC_ETOC_Pos       (0U)

+#define FDCAN_TOCC_ETOC_Msk       (0x1UL << FDCAN_TOCC_ETOC_Pos)               /*!< 0x00000001 */

+#define FDCAN_TOCC_ETOC           FDCAN_TOCC_ETOC_Msk                          /*!<Enable Timeout Counter                   */

+#define FDCAN_TOCC_TOS_Pos        (1U)

+#define FDCAN_TOCC_TOS_Msk        (0x3UL << FDCAN_TOCC_TOS_Pos)                /*!< 0x00000006 */

+#define FDCAN_TOCC_TOS            FDCAN_TOCC_TOS_Msk                           /*!<Timeout Select                           */

+#define FDCAN_TOCC_TOP_Pos        (16U)

+#define FDCAN_TOCC_TOP_Msk        (0xFFFFUL << FDCAN_TOCC_TOP_Pos)             /*!< 0xFFFF0000 */

+#define FDCAN_TOCC_TOP            FDCAN_TOCC_TOP_Msk                           /*!<Timeout Period                           */

+

+/*****************  Bit definition for FDCAN_TOCV register  ********************/

+#define FDCAN_TOCV_TOC_Pos        (0U)

+#define FDCAN_TOCV_TOC_Msk        (0xFFFFUL << FDCAN_TOCV_TOC_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TOCV_TOC            FDCAN_TOCV_TOC_Msk                           /*!<Timeout Counter                          */

+

+/*****************  Bit definition for FDCAN_ECR register  *********************/

+#define FDCAN_ECR_TEC_Pos         (0U)

+#define FDCAN_ECR_TEC_Msk         (0xFUL << FDCAN_ECR_TEC_Pos)                 /*!< 0x0000000F */

+#define FDCAN_ECR_TEC             FDCAN_ECR_TEC_Msk                            /*!<Transmit Error Counter                   */

+#define FDCAN_ECR_REC_Pos         (8U)

+#define FDCAN_ECR_REC_Msk         (0x7FUL << FDCAN_ECR_REC_Pos)                /*!< 0x00007F00 */

+#define FDCAN_ECR_REC             FDCAN_ECR_REC_Msk                            /*!<Receive Error Counter                    */

+#define FDCAN_ECR_RP_Pos          (15U)

+#define FDCAN_ECR_RP_Msk          (0x1UL << FDCAN_ECR_RP_Pos)                  /*!< 0x00008000 */

+#define FDCAN_ECR_RP              FDCAN_ECR_RP_Msk                             /*!<Receive Error Passive                    */

+#define FDCAN_ECR_CEL_Pos         (16U)

+#define FDCAN_ECR_CEL_Msk         (0xFFUL << FDCAN_ECR_CEL_Pos)                /*!< 0x00FF0000 */

+#define FDCAN_ECR_CEL             FDCAN_ECR_CEL_Msk                            /*!<CAN Error Logging                        */

+

+/*****************  Bit definition for FDCAN_PSR register  *********************/

+#define FDCAN_PSR_LEC_Pos         (0U)

+#define FDCAN_PSR_LEC_Msk         (0x7UL << FDCAN_PSR_LEC_Pos)                 /*!< 0x00000007 */

+#define FDCAN_PSR_LEC             FDCAN_PSR_LEC_Msk                            /*!<Last Error Code                          */

+#define FDCAN_PSR_ACT_Pos         (3U)

+#define FDCAN_PSR_ACT_Msk         (0x3UL << FDCAN_PSR_ACT_Pos)                 /*!< 0x00000018 */

+#define FDCAN_PSR_ACT             FDCAN_PSR_ACT_Msk                            /*!<Activity                                 */

+#define FDCAN_PSR_EP_Pos          (5U)

+#define FDCAN_PSR_EP_Msk          (0x1UL << FDCAN_PSR_EP_Pos)                  /*!< 0x00000020 */

+#define FDCAN_PSR_EP              FDCAN_PSR_EP_Msk                             /*!<Error Passive                            */

+#define FDCAN_PSR_EW_Pos          (6U)

+#define FDCAN_PSR_EW_Msk          (0x1UL << FDCAN_PSR_EW_Pos)                  /*!< 0x00000040 */

+#define FDCAN_PSR_EW              FDCAN_PSR_EW_Msk                             /*!<Warning Status                           */

+#define FDCAN_PSR_BO_Pos          (7U)

+#define FDCAN_PSR_BO_Msk          (0x1UL << FDCAN_PSR_BO_Pos)                  /*!< 0x00000080 */

+#define FDCAN_PSR_BO              FDCAN_PSR_BO_Msk                             /*!<Bus_Off Status                           */

+#define FDCAN_PSR_DLEC_Pos        (8U)

+#define FDCAN_PSR_DLEC_Msk        (0x7UL << FDCAN_PSR_DLEC_Pos)                /*!< 0x00000700 */

+#define FDCAN_PSR_DLEC            FDCAN_PSR_DLEC_Msk                           /*!<Data Last Error Code                     */

+#define FDCAN_PSR_RESI_Pos        (11U)

+#define FDCAN_PSR_RESI_Msk        (0x1UL << FDCAN_PSR_RESI_Pos)                /*!< 0x00000800 */

+#define FDCAN_PSR_RESI            FDCAN_PSR_RESI_Msk                           /*!<ESI flag of last received FDCAN Message  */

+#define FDCAN_PSR_RBRS_Pos        (12U)

+#define FDCAN_PSR_RBRS_Msk        (0x1UL << FDCAN_PSR_RBRS_Pos)                /*!< 0x00001000 */

+#define FDCAN_PSR_RBRS            FDCAN_PSR_RBRS_Msk                           /*!<BRS flag of last received FDCAN Message  */

+#define FDCAN_PSR_REDL_Pos        (13U)

+#define FDCAN_PSR_REDL_Msk        (0x1UL << FDCAN_PSR_REDL_Pos)                /*!< 0x00002000 */

+#define FDCAN_PSR_REDL            FDCAN_PSR_REDL_Msk                           /*!<Received FDCAN Message                   */

+#define FDCAN_PSR_PXE_Pos         (14U)

+#define FDCAN_PSR_PXE_Msk         (0x1UL << FDCAN_PSR_PXE_Pos)                 /*!< 0x00004000 */

+#define FDCAN_PSR_PXE             FDCAN_PSR_PXE_Msk                            /*!<Protocol Exception Event                 */

+#define FDCAN_PSR_TDCV_Pos        (16U)

+#define FDCAN_PSR_TDCV_Msk        (0x7FUL << FDCAN_PSR_TDCV_Pos)               /*!< 0x007F0000 */

+#define FDCAN_PSR_TDCV            FDCAN_PSR_TDCV_Msk                           /*!<Transmitter Delay Compensation Value     */

+

+/*****************  Bit definition for FDCAN_TDCR register  ********************/

+#define FDCAN_TDCR_TDCF_Pos       (0U)

+#define FDCAN_TDCR_TDCF_Msk       (0x7FUL << FDCAN_TDCR_TDCF_Pos)              /*!< 0x0000007F */

+#define FDCAN_TDCR_TDCF           FDCAN_TDCR_TDCF_Msk                          /*!<Transmitter Delay Compensation Filter    */

+#define FDCAN_TDCR_TDCO_Pos       (8U)

+#define FDCAN_TDCR_TDCO_Msk       (0x7FUL << FDCAN_TDCR_TDCO_Pos)              /*!< 0x00007F00 */

+#define FDCAN_TDCR_TDCO           FDCAN_TDCR_TDCO_Msk                          /*!<Transmitter Delay Compensation Offset    */

+

+/*****************  Bit definition for FDCAN_IR register  **********************/

+#define FDCAN_IR_RF0N_Pos         (0U)

+#define FDCAN_IR_RF0N_Msk         (0x1UL << FDCAN_IR_RF0N_Pos)                 /*!< 0x00000001 */

+#define FDCAN_IR_RF0N             FDCAN_IR_RF0N_Msk                            /*!<Rx FIFO 0 New Message                    */

+#define FDCAN_IR_RF0W_Pos         (1U)

+#define FDCAN_IR_RF0W_Msk         (0x1UL << FDCAN_IR_RF0W_Pos)                 /*!< 0x00000002 */

+#define FDCAN_IR_RF0W             FDCAN_IR_RF0W_Msk                            /*!<Rx FIFO 0 Watermark Reached              */

+#define FDCAN_IR_RF0F_Pos         (2U)

+#define FDCAN_IR_RF0F_Msk         (0x1UL << FDCAN_IR_RF0F_Pos)                 /*!< 0x00000004 */

+#define FDCAN_IR_RF0F             FDCAN_IR_RF0F_Msk                            /*!<Rx FIFO 0 Full                           */

+#define FDCAN_IR_RF0L_Pos         (3U)

+#define FDCAN_IR_RF0L_Msk         (0x1UL << FDCAN_IR_RF0L_Pos)                 /*!< 0x00000008 */

+#define FDCAN_IR_RF0L             FDCAN_IR_RF0L_Msk                            /*!<Rx FIFO 0 Message Lost                   */

+#define FDCAN_IR_RF1N_Pos         (4U)

+#define FDCAN_IR_RF1N_Msk         (0x1UL << FDCAN_IR_RF1N_Pos)                 /*!< 0x00000010 */

+#define FDCAN_IR_RF1N             FDCAN_IR_RF1N_Msk                            /*!<Rx FIFO 1 New Message                    */

+#define FDCAN_IR_RF1W_Pos         (5U)

+#define FDCAN_IR_RF1W_Msk         (0x1UL << FDCAN_IR_RF1W_Pos)                 /*!< 0x00000020 */

+#define FDCAN_IR_RF1W             FDCAN_IR_RF1W_Msk                            /*!<Rx FIFO 1 Watermark Reached              */

+#define FDCAN_IR_RF1F_Pos         (6U)

+#define FDCAN_IR_RF1F_Msk         (0x1UL << FDCAN_IR_RF1F_Pos)                 /*!< 0x00000040 */

+#define FDCAN_IR_RF1F             FDCAN_IR_RF1F_Msk                            /*!<Rx FIFO 1 Full                           */

+#define FDCAN_IR_RF1L_Pos         (7U)

+#define FDCAN_IR_RF1L_Msk         (0x1UL << FDCAN_IR_RF1L_Pos)                 /*!< 0x00000080 */

+#define FDCAN_IR_RF1L             FDCAN_IR_RF1L_Msk                            /*!<Rx FIFO 1 Message Lost                   */

+#define FDCAN_IR_HPM_Pos          (8U)

+#define FDCAN_IR_HPM_Msk          (0x1UL << FDCAN_IR_HPM_Pos)                  /*!< 0x00000100 */

+#define FDCAN_IR_HPM              FDCAN_IR_HPM_Msk                             /*!<High Priority Message                    */

+#define FDCAN_IR_TC_Pos           (9U)

+#define FDCAN_IR_TC_Msk           (0x1UL << FDCAN_IR_TC_Pos)                   /*!< 0x00000200 */

+#define FDCAN_IR_TC               FDCAN_IR_TC_Msk                              /*!<Transmission Completed                   */

+#define FDCAN_IR_TCF_Pos          (10U)

+#define FDCAN_IR_TCF_Msk          (0x1UL << FDCAN_IR_TCF_Pos)                  /*!< 0x00000400 */

+#define FDCAN_IR_TCF              FDCAN_IR_TCF_Msk                             /*!<Transmission Cancellation Finished       */

+#define FDCAN_IR_TFE_Pos          (11U)

+#define FDCAN_IR_TFE_Msk          (0x1UL << FDCAN_IR_TFE_Pos)                  /*!< 0x00000800 */

+#define FDCAN_IR_TFE              FDCAN_IR_TFE_Msk                             /*!<Tx FIFO Empty                            */

+#define FDCAN_IR_TEFN_Pos         (12U)

+#define FDCAN_IR_TEFN_Msk         (0x1UL << FDCAN_IR_TEFN_Pos)                 /*!< 0x00001000 */

+#define FDCAN_IR_TEFN             FDCAN_IR_TEFN_Msk                            /*!<Tx Event FIFO New Entry                  */

+#define FDCAN_IR_TEFW_Pos         (13U)

+#define FDCAN_IR_TEFW_Msk         (0x1UL << FDCAN_IR_TEFW_Pos)                 /*!< 0x00002000 */

+#define FDCAN_IR_TEFW             FDCAN_IR_TEFW_Msk                            /*!<Tx Event FIFO Watermark Reached          */

+#define FDCAN_IR_TEFF_Pos         (14U)

+#define FDCAN_IR_TEFF_Msk         (0x1UL << FDCAN_IR_TEFF_Pos)                 /*!< 0x00004000 */

+#define FDCAN_IR_TEFF             FDCAN_IR_TEFF_Msk                            /*!<Tx Event FIFO Full                       */

+#define FDCAN_IR_TEFL_Pos         (15U)

+#define FDCAN_IR_TEFL_Msk         (0x1UL << FDCAN_IR_TEFL_Pos)                 /*!< 0x00008000 */

+#define FDCAN_IR_TEFL             FDCAN_IR_TEFL_Msk                            /*!<Tx Event FIFO Element Lost               */

+#define FDCAN_IR_TSW_Pos          (16U)

+#define FDCAN_IR_TSW_Msk          (0x1UL << FDCAN_IR_TSW_Pos)                  /*!< 0x00010000 */

+#define FDCAN_IR_TSW              FDCAN_IR_TSW_Msk                             /*!<Timestamp Wraparound                     */

+#define FDCAN_IR_MRAF_Pos         (17U)

+#define FDCAN_IR_MRAF_Msk         (0x1UL << FDCAN_IR_MRAF_Pos)                 /*!< 0x00020000 */

+#define FDCAN_IR_MRAF             FDCAN_IR_MRAF_Msk                            /*!<Message RAM Access Failure               */

+#define FDCAN_IR_TOO_Pos          (18U)

+#define FDCAN_IR_TOO_Msk          (0x1UL << FDCAN_IR_TOO_Pos)                  /*!< 0x00040000 */

+#define FDCAN_IR_TOO              FDCAN_IR_TOO_Msk                             /*!<Timeout Occurred                         */

+#define FDCAN_IR_DRX_Pos          (19U)

+#define FDCAN_IR_DRX_Msk          (0x1UL << FDCAN_IR_DRX_Pos)                  /*!< 0x00080000 */

+#define FDCAN_IR_DRX              FDCAN_IR_DRX_Msk                             /*!<Message stored to Dedicated Rx Buffer    */

+#define FDCAN_IR_ELO_Pos          (22U)

+#define FDCAN_IR_ELO_Msk          (0x1UL << FDCAN_IR_ELO_Pos)                  /*!< 0x00400000 */

+#define FDCAN_IR_ELO              FDCAN_IR_ELO_Msk                             /*!<Error Logging Overflow                   */

+#define FDCAN_IR_EP_Pos           (23U)

+#define FDCAN_IR_EP_Msk           (0x1UL << FDCAN_IR_EP_Pos)                   /*!< 0x00800000 */

+#define FDCAN_IR_EP               FDCAN_IR_EP_Msk                              /*!<Error Passive                            */

+#define FDCAN_IR_EW_Pos           (24U)

+#define FDCAN_IR_EW_Msk           (0x1UL << FDCAN_IR_EW_Pos)                   /*!< 0x01000000 */

+#define FDCAN_IR_EW               FDCAN_IR_EW_Msk                              /*!<Warning Status                           */

+#define FDCAN_IR_BO_Pos           (25U)

+#define FDCAN_IR_BO_Msk           (0x1UL << FDCAN_IR_BO_Pos)                   /*!< 0x02000000 */

+#define FDCAN_IR_BO               FDCAN_IR_BO_Msk                              /*!<Bus_Off Status                           */

+#define FDCAN_IR_WDI_Pos          (26U)

+#define FDCAN_IR_WDI_Msk          (0x1UL << FDCAN_IR_WDI_Pos)                  /*!< 0x04000000 */

+#define FDCAN_IR_WDI              FDCAN_IR_WDI_Msk                             /*!<Watchdog Interrupt                       */

+#define FDCAN_IR_PEA_Pos          (27U)

+#define FDCAN_IR_PEA_Msk          (0x1UL << FDCAN_IR_PEA_Pos)                  /*!< 0x08000000 */

+#define FDCAN_IR_PEA              FDCAN_IR_PEA_Msk                             /*!<Protocol Error in Arbitration Phase      */

+#define FDCAN_IR_PED_Pos          (28U)

+#define FDCAN_IR_PED_Msk          (0x1UL << FDCAN_IR_PED_Pos)                  /*!< 0x10000000 */

+#define FDCAN_IR_PED              FDCAN_IR_PED_Msk                             /*!<Protocol Error in Data Phase             */

+#define FDCAN_IR_ARA_Pos          (29U)

+#define FDCAN_IR_ARA_Msk          (0x1UL << FDCAN_IR_ARA_Pos)                  /*!< 0x20000000 */

+#define FDCAN_IR_ARA              FDCAN_IR_ARA_Msk                             /*!<Access to Reserved Address               */

+

+/*****************  Bit definition for FDCAN_IE register  **********************/

+#define FDCAN_IE_RF0NE_Pos        (0U)

+#define FDCAN_IE_RF0NE_Msk        (0x1UL << FDCAN_IE_RF0NE_Pos)                /*!< 0x00000001 */

+#define FDCAN_IE_RF0NE            FDCAN_IE_RF0NE_Msk                           /*!<Rx FIFO 0 New Message Enable                 */

+#define FDCAN_IE_RF0WE_Pos        (1U)

+#define FDCAN_IE_RF0WE_Msk        (0x1UL << FDCAN_IE_RF0WE_Pos)                /*!< 0x00000002 */

+#define FDCAN_IE_RF0WE            FDCAN_IE_RF0WE_Msk                           /*!<Rx FIFO 0 Watermark Reached Enable           */

+#define FDCAN_IE_RF0FE_Pos        (2U)

+#define FDCAN_IE_RF0FE_Msk        (0x1UL << FDCAN_IE_RF0FE_Pos)                /*!< 0x00000004 */

+#define FDCAN_IE_RF0FE            FDCAN_IE_RF0FE_Msk                           /*!<Rx FIFO 0 Full Enable                        */

+#define FDCAN_IE_RF0LE_Pos        (3U)

+#define FDCAN_IE_RF0LE_Msk        (0x1UL << FDCAN_IE_RF0LE_Pos)                /*!< 0x00000008 */

+#define FDCAN_IE_RF0LE            FDCAN_IE_RF0LE_Msk                           /*!<Rx FIFO 0 Message Lost Enable                */

+#define FDCAN_IE_RF1NE_Pos        (4U)

+#define FDCAN_IE_RF1NE_Msk        (0x1UL << FDCAN_IE_RF1NE_Pos)                /*!< 0x00000010 */

+#define FDCAN_IE_RF1NE            FDCAN_IE_RF1NE_Msk                           /*!<Rx FIFO 1 New Message Enable                 */

+#define FDCAN_IE_RF1WE_Pos        (5U)

+#define FDCAN_IE_RF1WE_Msk        (0x1UL << FDCAN_IE_RF1WE_Pos)                /*!< 0x00000020 */

+#define FDCAN_IE_RF1WE            FDCAN_IE_RF1WE_Msk                           /*!<Rx FIFO 1 Watermark Reached Enable           */

+#define FDCAN_IE_RF1FE_Pos        (6U)

+#define FDCAN_IE_RF1FE_Msk        (0x1UL << FDCAN_IE_RF1FE_Pos)                /*!< 0x00000040 */

+#define FDCAN_IE_RF1FE            FDCAN_IE_RF1FE_Msk                           /*!<Rx FIFO 1 Full Enable                        */

+#define FDCAN_IE_RF1LE_Pos        (7U)

+#define FDCAN_IE_RF1LE_Msk        (0x1UL << FDCAN_IE_RF1LE_Pos)                /*!< 0x00000080 */

+#define FDCAN_IE_RF1LE            FDCAN_IE_RF1LE_Msk                           /*!<Rx FIFO 1 Message Lost Enable                */

+#define FDCAN_IE_HPME_Pos         (8U)

+#define FDCAN_IE_HPME_Msk         (0x1UL << FDCAN_IE_HPME_Pos)                 /*!< 0x00000100 */

+#define FDCAN_IE_HPME             FDCAN_IE_HPME_Msk                            /*!<High Priority Message Enable                 */

+#define FDCAN_IE_TCE_Pos          (9U)

+#define FDCAN_IE_TCE_Msk          (0x1UL << FDCAN_IE_TCE_Pos)                  /*!< 0x00000200 */

+#define FDCAN_IE_TCE              FDCAN_IE_TCE_Msk                             /*!<Transmission Completed Enable                */

+#define FDCAN_IE_TCFE_Pos         (10U)

+#define FDCAN_IE_TCFE_Msk         (0x1UL << FDCAN_IE_TCFE_Pos)                 /*!< 0x00000400 */

+#define FDCAN_IE_TCFE             FDCAN_IE_TCFE_Msk                            /*!<Transmission Cancellation Finished Enable    */

+#define FDCAN_IE_TFEE_Pos         (11U)

+#define FDCAN_IE_TFEE_Msk         (0x1UL << FDCAN_IE_TFEE_Pos)                 /*!< 0x00000800 */

+#define FDCAN_IE_TFEE             FDCAN_IE_TFEE_Msk                            /*!<Tx FIFO Empty Enable                         */

+#define FDCAN_IE_TEFNE_Pos        (12U)

+#define FDCAN_IE_TEFNE_Msk        (0x1UL << FDCAN_IE_TEFNE_Pos)                /*!< 0x00001000 */

+#define FDCAN_IE_TEFNE            FDCAN_IE_TEFNE_Msk                           /*!<Tx Event FIFO New Entry Enable               */

+#define FDCAN_IE_TEFWE_Pos        (13U)

+#define FDCAN_IE_TEFWE_Msk        (0x1UL << FDCAN_IE_TEFWE_Pos)                /*!< 0x00002000 */

+#define FDCAN_IE_TEFWE            FDCAN_IE_TEFWE_Msk                           /*!<Tx Event FIFO Watermark Reached Enable       */

+#define FDCAN_IE_TEFFE_Pos        (14U)

+#define FDCAN_IE_TEFFE_Msk        (0x1UL << FDCAN_IE_TEFFE_Pos)                /*!< 0x00004000 */

+#define FDCAN_IE_TEFFE            FDCAN_IE_TEFFE_Msk                           /*!<Tx Event FIFO Full Enable                    */

+#define FDCAN_IE_TEFLE_Pos        (15U)

+#define FDCAN_IE_TEFLE_Msk        (0x1UL << FDCAN_IE_TEFLE_Pos)                /*!< 0x00008000 */

+#define FDCAN_IE_TEFLE            FDCAN_IE_TEFLE_Msk                           /*!<Tx Event FIFO Element Lost Enable            */

+#define FDCAN_IE_TSWE_Pos         (16U)

+#define FDCAN_IE_TSWE_Msk         (0x1UL << FDCAN_IE_TSWE_Pos)                 /*!< 0x00010000 */

+#define FDCAN_IE_TSWE             FDCAN_IE_TSWE_Msk                            /*!<Timestamp Wraparound Enable                  */

+#define FDCAN_IE_MRAFE_Pos        (17U)

+#define FDCAN_IE_MRAFE_Msk        (0x1UL << FDCAN_IE_MRAFE_Pos)                /*!< 0x00020000 */

+#define FDCAN_IE_MRAFE            FDCAN_IE_MRAFE_Msk                           /*!<Message RAM Access Failure Enable            */

+#define FDCAN_IE_TOOE_Pos         (18U)

+#define FDCAN_IE_TOOE_Msk         (0x1UL << FDCAN_IE_TOOE_Pos)                 /*!< 0x00040000 */

+#define FDCAN_IE_TOOE             FDCAN_IE_TOOE_Msk                            /*!<Timeout Occurred Enable                      */

+#define FDCAN_IE_DRXE_Pos         (19U)

+#define FDCAN_IE_DRXE_Msk         (0x1UL << FDCAN_IE_DRXE_Pos)                 /*!< 0x00080000 */

+#define FDCAN_IE_DRXE             FDCAN_IE_DRXE_Msk                            /*!<Message stored to Dedicated Rx Buffer Enable */

+#define FDCAN_IE_BECE_Pos         (20U)

+#define FDCAN_IE_BECE_Msk         (0x1UL << FDCAN_IE_BECE_Pos)                 /*!< 0x00100000 */

+#define FDCAN_IE_BECE             FDCAN_IE_BECE_Msk                            /*!<Bit Error Corrected Interrupt Enable         */

+#define FDCAN_IE_BEUE_Pos         (21U)

+#define FDCAN_IE_BEUE_Msk         (0x1UL << FDCAN_IE_BEUE_Pos)                 /*!< 0x00200000 */

+#define FDCAN_IE_BEUE             FDCAN_IE_BEUE_Msk                            /*!<Bit Error Uncorrected Interrupt Enable       */

+#define FDCAN_IE_ELOE_Pos         (22U)

+#define FDCAN_IE_ELOE_Msk         (0x1UL << FDCAN_IE_ELOE_Pos)                 /*!< 0x00400000 */

+#define FDCAN_IE_ELOE             FDCAN_IE_ELOE_Msk                            /*!<Error Logging Overflow Enable                */

+#define FDCAN_IE_EPE_Pos          (23U)

+#define FDCAN_IE_EPE_Msk          (0x1UL << FDCAN_IE_EPE_Pos)                  /*!< 0x00800000 */

+#define FDCAN_IE_EPE              FDCAN_IE_EPE_Msk                             /*!<Error Passive Enable                         */

+#define FDCAN_IE_EWE_Pos          (24U)

+#define FDCAN_IE_EWE_Msk          (0x1UL << FDCAN_IE_EWE_Pos)                  /*!< 0x01000000 */

+#define FDCAN_IE_EWE              FDCAN_IE_EWE_Msk                             /*!<Warning Status Enable                        */

+#define FDCAN_IE_BOE_Pos          (25U)

+#define FDCAN_IE_BOE_Msk          (0x1UL << FDCAN_IE_BOE_Pos)                  /*!< 0x02000000 */

+#define FDCAN_IE_BOE              FDCAN_IE_BOE_Msk                             /*!<Bus_Off Status Enable                        */

+#define FDCAN_IE_WDIE_Pos         (26U)

+#define FDCAN_IE_WDIE_Msk         (0x1UL << FDCAN_IE_WDIE_Pos)                 /*!< 0x04000000 */

+#define FDCAN_IE_WDIE             FDCAN_IE_WDIE_Msk                            /*!<Watchdog Interrupt Enable                    */

+#define FDCAN_IE_PEAE_Pos         (27U)

+#define FDCAN_IE_PEAE_Msk         (0x1UL << FDCAN_IE_PEAE_Pos)                 /*!< 0x08000000 */

+#define FDCAN_IE_PEAE             FDCAN_IE_PEAE_Msk                            /*!<Protocol Error in Arbitration Phase Enable   */

+#define FDCAN_IE_PEDE_Pos         (28U)

+#define FDCAN_IE_PEDE_Msk         (0x1UL << FDCAN_IE_PEDE_Pos)                 /*!< 0x10000000 */

+#define FDCAN_IE_PEDE             FDCAN_IE_PEDE_Msk                            /*!<Protocol Error in Data Phase Enable          */

+#define FDCAN_IE_ARAE_Pos         (29U)

+#define FDCAN_IE_ARAE_Msk         (0x1UL << FDCAN_IE_ARAE_Pos)                 /*!< 0x20000000 */

+#define FDCAN_IE_ARAE             FDCAN_IE_ARAE_Msk                            /*!<Access to Reserved Address Enable            */

+

+/*****************  Bit definition for FDCAN_ILS register  **********************/

+#define FDCAN_ILS_RF0NL_Pos       (0U)

+#define FDCAN_ILS_RF0NL_Msk       (0x1UL << FDCAN_ILS_RF0NL_Pos)               /*!< 0x00000001 */

+#define FDCAN_ILS_RF0NL           FDCAN_ILS_RF0NL_Msk                          /*!<Rx FIFO 0 New Message Line                  */

+#define FDCAN_ILS_RF0WL_Pos       (1U)

+#define FDCAN_ILS_RF0WL_Msk       (0x1UL << FDCAN_ILS_RF0WL_Pos)               /*!< 0x00000002 */

+#define FDCAN_ILS_RF0WL           FDCAN_ILS_RF0WL_Msk                          /*!<Rx FIFO 0 Watermark Reached Line            */

+#define FDCAN_ILS_RF0FL_Pos       (2U)

+#define FDCAN_ILS_RF0FL_Msk       (0x1UL << FDCAN_ILS_RF0FL_Pos)               /*!< 0x00000004 */

+#define FDCAN_ILS_RF0FL           FDCAN_ILS_RF0FL_Msk                          /*!<Rx FIFO 0 Full Line                         */

+#define FDCAN_ILS_RF0LL_Pos       (3U)

+#define FDCAN_ILS_RF0LL_Msk       (0x1UL << FDCAN_ILS_RF0LL_Pos)               /*!< 0x00000008 */

+#define FDCAN_ILS_RF0LL           FDCAN_ILS_RF0LL_Msk                          /*!<Rx FIFO 0 Message Lost Line                 */

+#define FDCAN_ILS_RF1NL_Pos       (4U)

+#define FDCAN_ILS_RF1NL_Msk       (0x1UL << FDCAN_ILS_RF1NL_Pos)               /*!< 0x00000010 */

+#define FDCAN_ILS_RF1NL           FDCAN_ILS_RF1NL_Msk                          /*!<Rx FIFO 1 New Message Line                  */

+#define FDCAN_ILS_RF1WL_Pos       (5U)

+#define FDCAN_ILS_RF1WL_Msk       (0x1UL << FDCAN_ILS_RF1WL_Pos)               /*!< 0x00000020 */

+#define FDCAN_ILS_RF1WL           FDCAN_ILS_RF1WL_Msk                          /*!<Rx FIFO 1 Watermark Reached Line            */

+#define FDCAN_ILS_RF1FL_Pos       (6U)

+#define FDCAN_ILS_RF1FL_Msk       (0x1UL << FDCAN_ILS_RF1FL_Pos)               /*!< 0x00000040 */

+#define FDCAN_ILS_RF1FL           FDCAN_ILS_RF1FL_Msk                          /*!<Rx FIFO 1 Full Line                         */

+#define FDCAN_ILS_RF1LL_Pos       (7U)

+#define FDCAN_ILS_RF1LL_Msk       (0x1UL << FDCAN_ILS_RF1LL_Pos)               /*!< 0x00000080 */

+#define FDCAN_ILS_RF1LL           FDCAN_ILS_RF1LL_Msk                          /*!<Rx FIFO 1 Message Lost Line                 */

+#define FDCAN_ILS_HPML_Pos        (8U)

+#define FDCAN_ILS_HPML_Msk        (0x1UL << FDCAN_ILS_HPML_Pos)                /*!< 0x00000100 */

+#define FDCAN_ILS_HPML            FDCAN_ILS_HPML_Msk                           /*!<High Priority Message Line                  */

+#define FDCAN_ILS_TCL_Pos         (9U)

+#define FDCAN_ILS_TCL_Msk         (0x1UL << FDCAN_ILS_TCL_Pos)                 /*!< 0x00000200 */

+#define FDCAN_ILS_TCL             FDCAN_ILS_TCL_Msk                            /*!<Transmission Completed Line                 */

+#define FDCAN_ILS_TCFL_Pos        (10U)

+#define FDCAN_ILS_TCFL_Msk        (0x1UL << FDCAN_ILS_TCFL_Pos)                /*!< 0x00000400 */

+#define FDCAN_ILS_TCFL            FDCAN_ILS_TCFL_Msk                           /*!<Transmission Cancellation Finished Line     */

+#define FDCAN_ILS_TFEL_Pos        (11U)

+#define FDCAN_ILS_TFEL_Msk        (0x1UL << FDCAN_ILS_TFEL_Pos)                /*!< 0x00000800 */

+#define FDCAN_ILS_TFEL            FDCAN_ILS_TFEL_Msk                           /*!<Tx FIFO Empty Line                          */

+#define FDCAN_ILS_TEFNL_Pos       (12U)

+#define FDCAN_ILS_TEFNL_Msk       (0x1UL << FDCAN_ILS_TEFNL_Pos)               /*!< 0x00001000 */

+#define FDCAN_ILS_TEFNL           FDCAN_ILS_TEFNL_Msk                          /*!<Tx Event FIFO New Entry Line                */

+#define FDCAN_ILS_TEFWL_Pos       (13U)

+#define FDCAN_ILS_TEFWL_Msk       (0x1UL << FDCAN_ILS_TEFWL_Pos)               /*!< 0x00002000 */

+#define FDCAN_ILS_TEFWL           FDCAN_ILS_TEFWL_Msk                          /*!<Tx Event FIFO Watermark Reached Line        */

+#define FDCAN_ILS_TEFFL_Pos       (14U)

+#define FDCAN_ILS_TEFFL_Msk       (0x1UL << FDCAN_ILS_TEFFL_Pos)               /*!< 0x00004000 */

+#define FDCAN_ILS_TEFFL           FDCAN_ILS_TEFFL_Msk                          /*!<Tx Event FIFO Full Line                     */

+#define FDCAN_ILS_TEFLL_Pos       (15U)

+#define FDCAN_ILS_TEFLL_Msk       (0x1UL << FDCAN_ILS_TEFLL_Pos)               /*!< 0x00008000 */

+#define FDCAN_ILS_TEFLL           FDCAN_ILS_TEFLL_Msk                          /*!<Tx Event FIFO Element Lost Line             */

+#define FDCAN_ILS_TSWL_Pos        (16U)

+#define FDCAN_ILS_TSWL_Msk        (0x1UL << FDCAN_ILS_TSWL_Pos)                /*!< 0x00010000 */

+#define FDCAN_ILS_TSWL            FDCAN_ILS_TSWL_Msk                           /*!<Timestamp Wraparound Line                   */

+#define FDCAN_ILS_MRAFE_Pos       (17U)

+#define FDCAN_ILS_MRAFE_Msk       (0x1UL << FDCAN_ILS_MRAFE_Pos)               /*!< 0x00020000 */

+#define FDCAN_ILS_MRAFE           FDCAN_ILS_MRAFE_Msk                          /*!<Message RAM Access Failure Line             */

+#define FDCAN_ILS_TOOE_Pos        (18U)

+#define FDCAN_ILS_TOOE_Msk        (0x1UL << FDCAN_ILS_TOOE_Pos)                /*!< 0x00040000 */

+#define FDCAN_ILS_TOOE            FDCAN_ILS_TOOE_Msk                           /*!<Timeout Occurred Line                       */

+#define FDCAN_ILS_DRXE_Pos        (19U)

+#define FDCAN_ILS_DRXE_Msk        (0x1UL << FDCAN_ILS_DRXE_Pos)                /*!< 0x00080000 */

+#define FDCAN_ILS_DRXE            FDCAN_ILS_DRXE_Msk                           /*!<Message stored to Dedicated Rx Buffer Line  */

+#define FDCAN_ILS_BECE_Pos        (20U)

+#define FDCAN_ILS_BECE_Msk        (0x1UL << FDCAN_ILS_BECE_Pos)                /*!< 0x00100000 */

+#define FDCAN_ILS_BECE            FDCAN_ILS_BECE_Msk                           /*!<Bit Error Corrected Interrupt Line          */

+#define FDCAN_ILS_BEUE_Pos        (21U)

+#define FDCAN_ILS_BEUE_Msk        (0x1UL << FDCAN_ILS_BEUE_Pos)                /*!< 0x00200000 */

+#define FDCAN_ILS_BEUE            FDCAN_ILS_BEUE_Msk                           /*!<Bit Error Uncorrected Interrupt Line        */

+#define FDCAN_ILS_ELOE_Pos        (22U)

+#define FDCAN_ILS_ELOE_Msk        (0x1UL << FDCAN_ILS_ELOE_Pos)                /*!< 0x00400000 */

+#define FDCAN_ILS_ELOE            FDCAN_ILS_ELOE_Msk                           /*!<Error Logging Overflow Line                 */

+#define FDCAN_ILS_EPE_Pos         (23U)

+#define FDCAN_ILS_EPE_Msk         (0x1UL << FDCAN_ILS_EPE_Pos)                 /*!< 0x00800000 */

+#define FDCAN_ILS_EPE             FDCAN_ILS_EPE_Msk                            /*!<Error Passive Line                          */

+#define FDCAN_ILS_EWE_Pos         (24U)

+#define FDCAN_ILS_EWE_Msk         (0x1UL << FDCAN_ILS_EWE_Pos)                 /*!< 0x01000000 */

+#define FDCAN_ILS_EWE             FDCAN_ILS_EWE_Msk                            /*!<Warning Status Line                         */

+#define FDCAN_ILS_BOE_Pos         (25U)

+#define FDCAN_ILS_BOE_Msk         (0x1UL << FDCAN_ILS_BOE_Pos)                 /*!< 0x02000000 */

+#define FDCAN_ILS_BOE             FDCAN_ILS_BOE_Msk                            /*!<Bus_Off Status Line                         */

+#define FDCAN_ILS_WDIE_Pos        (26U)

+#define FDCAN_ILS_WDIE_Msk        (0x1UL << FDCAN_ILS_WDIE_Pos)                /*!< 0x04000000 */

+#define FDCAN_ILS_WDIE            FDCAN_ILS_WDIE_Msk                           /*!<Watchdog Interrupt Line                     */

+#define FDCAN_ILS_PEAE_Pos        (27U)

+#define FDCAN_ILS_PEAE_Msk        (0x1UL << FDCAN_ILS_PEAE_Pos)                /*!< 0x08000000 */

+#define FDCAN_ILS_PEAE            FDCAN_ILS_PEAE_Msk                           /*!<Protocol Error in Arbitration Phase Line    */

+#define FDCAN_ILS_PEDE_Pos        (28U)

+#define FDCAN_ILS_PEDE_Msk        (0x1UL << FDCAN_ILS_PEDE_Pos)                /*!< 0x10000000 */

+#define FDCAN_ILS_PEDE            FDCAN_ILS_PEDE_Msk                           /*!<Protocol Error in Data Phase Line           */

+#define FDCAN_ILS_ARAE_Pos        (29U)

+#define FDCAN_ILS_ARAE_Msk        (0x1UL << FDCAN_ILS_ARAE_Pos)                /*!< 0x20000000 */

+#define FDCAN_ILS_ARAE            FDCAN_ILS_ARAE_Msk                           /*!<Access to Reserved Address Line             */

+

+/*****************  Bit definition for FDCAN_ILE register  **********************/

+#define FDCAN_ILE_EINT0_Pos       (0U)

+#define FDCAN_ILE_EINT0_Msk       (0x1UL << FDCAN_ILE_EINT0_Pos)               /*!< 0x00000001 */

+#define FDCAN_ILE_EINT0           FDCAN_ILE_EINT0_Msk                          /*!<Enable Interrupt Line 0                   */

+#define FDCAN_ILE_EINT1_Pos       (1U)

+#define FDCAN_ILE_EINT1_Msk       (0x1UL << FDCAN_ILE_EINT1_Pos)               /*!< 0x00000002 */

+#define FDCAN_ILE_EINT1           FDCAN_ILE_EINT1_Msk                          /*!<Enable Interrupt Line 1                   */

+

+/*****************  Bit definition for FDCAN_GFC register  **********************/

+#define FDCAN_GFC_RRFE_Pos        (0U)

+#define FDCAN_GFC_RRFE_Msk        (0x1UL << FDCAN_GFC_RRFE_Pos)                /*!< 0x00000001 */

+#define FDCAN_GFC_RRFE            FDCAN_GFC_RRFE_Msk                           /*!<Reject Remote Frames Extended             */

+#define FDCAN_GFC_RRFS_Pos        (1U)

+#define FDCAN_GFC_RRFS_Msk        (0x1UL << FDCAN_GFC_RRFS_Pos)                /*!< 0x00000002 */

+#define FDCAN_GFC_RRFS            FDCAN_GFC_RRFS_Msk                           /*!<Reject Remote Frames Standard             */

+#define FDCAN_GFC_ANFE_Pos        (2U)

+#define FDCAN_GFC_ANFE_Msk        (0x3UL << FDCAN_GFC_ANFE_Pos)                /*!< 0x0000000C */

+#define FDCAN_GFC_ANFE            FDCAN_GFC_ANFE_Msk                           /*!<Accept Non-matching Frames Extended       */

+#define FDCAN_GFC_ANFS_Pos        (4U)

+#define FDCAN_GFC_ANFS_Msk        (0x3UL << FDCAN_GFC_ANFS_Pos)                /*!< 0x00000030 */

+#define FDCAN_GFC_ANFS            FDCAN_GFC_ANFS_Msk                           /*!<Accept Non-matching Frames Standard       */

+

+/*****************  Bit definition for FDCAN_SIDFC register  ********************/

+#define FDCAN_SIDFC_FLSSA_Pos     (2U)

+#define FDCAN_SIDFC_FLSSA_Msk     (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)          /*!< 0x0000FFFC */

+#define FDCAN_SIDFC_FLSSA         FDCAN_SIDFC_FLSSA_Msk                        /*!<Filter List Standard Start Address        */

+#define FDCAN_SIDFC_LSS_Pos       (16U)

+#define FDCAN_SIDFC_LSS_Msk       (0xFFUL << FDCAN_SIDFC_LSS_Pos)              /*!< 0x00FF0000 */

+#define FDCAN_SIDFC_LSS           FDCAN_SIDFC_LSS_Msk                          /*!<List Size Standard                        */

+

+/*****************  Bit definition for FDCAN_XIDFC register  ********************/

+#define FDCAN_XIDFC_FLESA_Pos     (2U)

+#define FDCAN_XIDFC_FLESA_Msk     (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)          /*!< 0x0000FFFC */

+#define FDCAN_XIDFC_FLESA         FDCAN_XIDFC_FLESA_Msk                        /*!<Filter List Standard Start Address        */

+#define FDCAN_XIDFC_LSE_Pos       (16U)

+#define FDCAN_XIDFC_LSE_Msk       (0x7FUL << FDCAN_XIDFC_LSE_Pos)              /*!< 0x007F0000 */

+#define FDCAN_XIDFC_LSE           FDCAN_XIDFC_LSE_Msk                          /*!<List Size Extended                        */

+

+/*****************  Bit definition for FDCAN_XIDAM register  ********************/

+#define FDCAN_XIDAM_EIDM_Pos      (0U)

+#define FDCAN_XIDAM_EIDM_Msk      (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)       /*!< 0x1FFFFFFF */

+#define FDCAN_XIDAM_EIDM          FDCAN_XIDAM_EIDM_Msk                         /*!<Extended ID Mask                          */

+

+/*****************  Bit definition for FDCAN_HPMS register  *********************/

+#define FDCAN_HPMS_BIDX_Pos       (0U)

+#define FDCAN_HPMS_BIDX_Msk       (0x3FUL << FDCAN_HPMS_BIDX_Pos)              /*!< 0x0000003F */

+#define FDCAN_HPMS_BIDX           FDCAN_HPMS_BIDX_Msk                          /*!<Buffer Index                              */

+#define FDCAN_HPMS_MSI_Pos        (6U)

+#define FDCAN_HPMS_MSI_Msk        (0x3UL << FDCAN_HPMS_MSI_Pos)                /*!< 0x000000C0 */

+#define FDCAN_HPMS_MSI            FDCAN_HPMS_MSI_Msk                           /*!<Message Storage Indicator                 */

+#define FDCAN_HPMS_FIDX_Pos       (8U)

+#define FDCAN_HPMS_FIDX_Msk       (0x7FUL << FDCAN_HPMS_FIDX_Pos)              /*!< 0x00007F00 */

+#define FDCAN_HPMS_FIDX           FDCAN_HPMS_FIDX_Msk                          /*!<Filter Index                              */

+#define FDCAN_HPMS_FLST_Pos       (15U)

+#define FDCAN_HPMS_FLST_Msk       (0x1UL << FDCAN_HPMS_FLST_Pos)               /*!< 0x00008000 */

+#define FDCAN_HPMS_FLST           FDCAN_HPMS_FLST_Msk                          /*!<Filter List                               */

+

+/*****************  Bit definition for FDCAN_NDAT1 register  ********************/

+#define FDCAN_NDAT1_ND0_Pos       (0U)

+#define FDCAN_NDAT1_ND0_Msk       (0x1UL << FDCAN_NDAT1_ND0_Pos)               /*!< 0x00000001 */

+#define FDCAN_NDAT1_ND0           FDCAN_NDAT1_ND0_Msk                          /*!<New Data flag of Rx Buffer 0              */

+#define FDCAN_NDAT1_ND1_Pos       (1U)

+#define FDCAN_NDAT1_ND1_Msk       (0x1UL << FDCAN_NDAT1_ND1_Pos)               /*!< 0x00000002 */

+#define FDCAN_NDAT1_ND1           FDCAN_NDAT1_ND1_Msk                          /*!<New Data flag of Rx Buffer 1              */

+#define FDCAN_NDAT1_ND2_Pos       (2U)

+#define FDCAN_NDAT1_ND2_Msk       (0x1UL << FDCAN_NDAT1_ND2_Pos)               /*!< 0x00000004 */

+#define FDCAN_NDAT1_ND2           FDCAN_NDAT1_ND2_Msk                          /*!<New Data flag of Rx Buffer 2              */

+#define FDCAN_NDAT1_ND3_Pos       (3U)

+#define FDCAN_NDAT1_ND3_Msk       (0x1UL << FDCAN_NDAT1_ND3_Pos)               /*!< 0x00000008 */

+#define FDCAN_NDAT1_ND3           FDCAN_NDAT1_ND3_Msk                          /*!<New Data flag of Rx Buffer 3              */

+#define FDCAN_NDAT1_ND4_Pos       (4U)

+#define FDCAN_NDAT1_ND4_Msk       (0x1UL << FDCAN_NDAT1_ND4_Pos)               /*!< 0x00000010 */

+#define FDCAN_NDAT1_ND4           FDCAN_NDAT1_ND4_Msk                          /*!<New Data flag of Rx Buffer 4              */

+#define FDCAN_NDAT1_ND5_Pos       (5U)

+#define FDCAN_NDAT1_ND5_Msk       (0x1UL << FDCAN_NDAT1_ND5_Pos)               /*!< 0x00000020 */

+#define FDCAN_NDAT1_ND5           FDCAN_NDAT1_ND5_Msk                          /*!<New Data flag of Rx Buffer 5              */

+#define FDCAN_NDAT1_ND6_Pos       (6U)

+#define FDCAN_NDAT1_ND6_Msk       (0x1UL << FDCAN_NDAT1_ND6_Pos)               /*!< 0x00000040 */

+#define FDCAN_NDAT1_ND6           FDCAN_NDAT1_ND6_Msk                          /*!<New Data flag of Rx Buffer 6              */

+#define FDCAN_NDAT1_ND7_Pos       (7U)

+#define FDCAN_NDAT1_ND7_Msk       (0x1UL << FDCAN_NDAT1_ND7_Pos)               /*!< 0x00000080 */

+#define FDCAN_NDAT1_ND7           FDCAN_NDAT1_ND7_Msk                          /*!<New Data flag of Rx Buffer 7              */

+#define FDCAN_NDAT1_ND8_Pos       (8U)

+#define FDCAN_NDAT1_ND8_Msk       (0x1UL << FDCAN_NDAT1_ND8_Pos)               /*!< 0x00000100 */

+#define FDCAN_NDAT1_ND8           FDCAN_NDAT1_ND8_Msk                          /*!<New Data flag of Rx Buffer 8              */

+#define FDCAN_NDAT1_ND9_Pos       (9U)

+#define FDCAN_NDAT1_ND9_Msk       (0x1UL << FDCAN_NDAT1_ND9_Pos)               /*!< 0x00000200 */

+#define FDCAN_NDAT1_ND9           FDCAN_NDAT1_ND9_Msk                          /*!<New Data flag of Rx Buffer 9              */

+#define FDCAN_NDAT1_ND10_Pos      (10U)

+#define FDCAN_NDAT1_ND10_Msk      (0x1UL << FDCAN_NDAT1_ND10_Pos)              /*!< 0x00000400 */

+#define FDCAN_NDAT1_ND10          FDCAN_NDAT1_ND10_Msk                         /*!<New Data flag of Rx Buffer 10             */

+#define FDCAN_NDAT1_ND11_Pos      (11U)

+#define FDCAN_NDAT1_ND11_Msk      (0x1UL << FDCAN_NDAT1_ND11_Pos)              /*!< 0x00000800 */

+#define FDCAN_NDAT1_ND11          FDCAN_NDAT1_ND11_Msk                         /*!<New Data flag of Rx Buffer 11             */

+#define FDCAN_NDAT1_ND12_Pos      (12U)

+#define FDCAN_NDAT1_ND12_Msk      (0x1UL << FDCAN_NDAT1_ND12_Pos)              /*!< 0x00001000 */

+#define FDCAN_NDAT1_ND12          FDCAN_NDAT1_ND12_Msk                         /*!<New Data flag of Rx Buffer 12             */

+#define FDCAN_NDAT1_ND13_Pos      (13U)

+#define FDCAN_NDAT1_ND13_Msk      (0x1UL << FDCAN_NDAT1_ND13_Pos)              /*!< 0x00002000 */

+#define FDCAN_NDAT1_ND13          FDCAN_NDAT1_ND13_Msk                         /*!<New Data flag of Rx Buffer 13             */

+#define FDCAN_NDAT1_ND14_Pos      (14U)

+#define FDCAN_NDAT1_ND14_Msk      (0x1UL << FDCAN_NDAT1_ND14_Pos)              /*!< 0x00004000 */

+#define FDCAN_NDAT1_ND14          FDCAN_NDAT1_ND14_Msk                         /*!<New Data flag of Rx Buffer 14             */

+#define FDCAN_NDAT1_ND15_Pos      (15U)

+#define FDCAN_NDAT1_ND15_Msk      (0x1UL << FDCAN_NDAT1_ND15_Pos)              /*!< 0x00008000 */

+#define FDCAN_NDAT1_ND15          FDCAN_NDAT1_ND15_Msk                         /*!<New Data flag of Rx Buffer 15             */

+#define FDCAN_NDAT1_ND16_Pos      (16U)

+#define FDCAN_NDAT1_ND16_Msk      (0x1UL << FDCAN_NDAT1_ND16_Pos)              /*!< 0x00010000 */

+#define FDCAN_NDAT1_ND16          FDCAN_NDAT1_ND16_Msk                         /*!<New Data flag of Rx Buffer 16             */

+#define FDCAN_NDAT1_ND17_Pos      (17U)

+#define FDCAN_NDAT1_ND17_Msk      (0x1UL << FDCAN_NDAT1_ND17_Pos)              /*!< 0x00020000 */

+#define FDCAN_NDAT1_ND17          FDCAN_NDAT1_ND17_Msk                         /*!<New Data flag of Rx Buffer 17             */

+#define FDCAN_NDAT1_ND18_Pos      (18U)

+#define FDCAN_NDAT1_ND18_Msk      (0x1UL << FDCAN_NDAT1_ND18_Pos)              /*!< 0x00040000 */

+#define FDCAN_NDAT1_ND18          FDCAN_NDAT1_ND18_Msk                         /*!<New Data flag of Rx Buffer 18             */

+#define FDCAN_NDAT1_ND19_Pos      (19U)

+#define FDCAN_NDAT1_ND19_Msk      (0x1UL << FDCAN_NDAT1_ND19_Pos)              /*!< 0x00080000 */

+#define FDCAN_NDAT1_ND19          FDCAN_NDAT1_ND19_Msk                         /*!<New Data flag of Rx Buffer 19             */

+#define FDCAN_NDAT1_ND20_Pos      (20U)

+#define FDCAN_NDAT1_ND20_Msk      (0x1UL << FDCAN_NDAT1_ND20_Pos)              /*!< 0x00100000 */

+#define FDCAN_NDAT1_ND20          FDCAN_NDAT1_ND20_Msk                         /*!<New Data flag of Rx Buffer 20             */

+#define FDCAN_NDAT1_ND21_Pos      (21U)

+#define FDCAN_NDAT1_ND21_Msk      (0x1UL << FDCAN_NDAT1_ND21_Pos)              /*!< 0x00200000 */

+#define FDCAN_NDAT1_ND21          FDCAN_NDAT1_ND21_Msk                         /*!<New Data flag of Rx Buffer 21             */

+#define FDCAN_NDAT1_ND22_Pos      (22U)

+#define FDCAN_NDAT1_ND22_Msk      (0x1UL << FDCAN_NDAT1_ND22_Pos)              /*!< 0x00400000 */

+#define FDCAN_NDAT1_ND22          FDCAN_NDAT1_ND22_Msk                         /*!<New Data flag of Rx Buffer 22             */

+#define FDCAN_NDAT1_ND23_Pos      (23U)

+#define FDCAN_NDAT1_ND23_Msk      (0x1UL << FDCAN_NDAT1_ND23_Pos)              /*!< 0x00800000 */

+#define FDCAN_NDAT1_ND23          FDCAN_NDAT1_ND23_Msk                         /*!<New Data flag of Rx Buffer 23             */

+#define FDCAN_NDAT1_ND24_Pos      (24U)

+#define FDCAN_NDAT1_ND24_Msk      (0x1UL << FDCAN_NDAT1_ND24_Pos)              /*!< 0x01000000 */

+#define FDCAN_NDAT1_ND24          FDCAN_NDAT1_ND24_Msk                         /*!<New Data flag of Rx Buffer 24             */

+#define FDCAN_NDAT1_ND25_Pos      (25U)

+#define FDCAN_NDAT1_ND25_Msk      (0x1UL << FDCAN_NDAT1_ND25_Pos)              /*!< 0x02000000 */

+#define FDCAN_NDAT1_ND25          FDCAN_NDAT1_ND25_Msk                         /*!<New Data flag of Rx Buffer 25             */

+#define FDCAN_NDAT1_ND26_Pos      (26U)

+#define FDCAN_NDAT1_ND26_Msk      (0x1UL << FDCAN_NDAT1_ND26_Pos)              /*!< 0x04000000 */

+#define FDCAN_NDAT1_ND26          FDCAN_NDAT1_ND26_Msk                         /*!<New Data flag of Rx Buffer 26             */

+#define FDCAN_NDAT1_ND27_Pos      (27U)

+#define FDCAN_NDAT1_ND27_Msk      (0x1UL << FDCAN_NDAT1_ND27_Pos)              /*!< 0x08000000 */

+#define FDCAN_NDAT1_ND27          FDCAN_NDAT1_ND27_Msk                         /*!<New Data flag of Rx Buffer 27             */

+#define FDCAN_NDAT1_ND28_Pos      (28U)

+#define FDCAN_NDAT1_ND28_Msk      (0x1UL << FDCAN_NDAT1_ND28_Pos)              /*!< 0x10000000 */

+#define FDCAN_NDAT1_ND28          FDCAN_NDAT1_ND28_Msk                         /*!<New Data flag of Rx Buffer 28             */

+#define FDCAN_NDAT1_ND29_Pos      (29U)

+#define FDCAN_NDAT1_ND29_Msk      (0x1UL << FDCAN_NDAT1_ND29_Pos)              /*!< 0x20000000 */

+#define FDCAN_NDAT1_ND29          FDCAN_NDAT1_ND29_Msk                         /*!<New Data flag of Rx Buffer 29             */

+#define FDCAN_NDAT1_ND30_Pos      (30U)

+#define FDCAN_NDAT1_ND30_Msk      (0x1UL << FDCAN_NDAT1_ND30_Pos)              /*!< 0x40000000 */

+#define FDCAN_NDAT1_ND30          FDCAN_NDAT1_ND30_Msk                         /*!<New Data flag of Rx Buffer 30             */

+#define FDCAN_NDAT1_ND31_Pos      (31U)

+#define FDCAN_NDAT1_ND31_Msk      (0x1UL << FDCAN_NDAT1_ND31_Pos)              /*!< 0x80000000 */

+#define FDCAN_NDAT1_ND31          FDCAN_NDAT1_ND31_Msk                         /*!<New Data flag of Rx Buffer 31             */

+

+/*****************  Bit definition for FDCAN_NDAT2 register  ********************/

+#define FDCAN_NDAT2_ND32_Pos      (0U)

+#define FDCAN_NDAT2_ND32_Msk      (0x1UL << FDCAN_NDAT2_ND32_Pos)              /*!< 0x00000001 */

+#define FDCAN_NDAT2_ND32          FDCAN_NDAT2_ND32_Msk                         /*!<New Data flag of Rx Buffer 32             */

+#define FDCAN_NDAT2_ND33_Pos      (1U)

+#define FDCAN_NDAT2_ND33_Msk      (0x1UL << FDCAN_NDAT2_ND33_Pos)              /*!< 0x00000002 */

+#define FDCAN_NDAT2_ND33          FDCAN_NDAT2_ND33_Msk                         /*!<New Data flag of Rx Buffer 33             */

+#define FDCAN_NDAT2_ND34_Pos      (2U)

+#define FDCAN_NDAT2_ND34_Msk      (0x1UL << FDCAN_NDAT2_ND34_Pos)              /*!< 0x00000004 */

+#define FDCAN_NDAT2_ND34          FDCAN_NDAT2_ND34_Msk                         /*!<New Data flag of Rx Buffer 34             */

+#define FDCAN_NDAT2_ND35_Pos      (3U)

+#define FDCAN_NDAT2_ND35_Msk      (0x1UL << FDCAN_NDAT2_ND35_Pos)              /*!< 0x00000008 */

+#define FDCAN_NDAT2_ND35          FDCAN_NDAT2_ND35_Msk                         /*!<New Data flag of Rx Buffer 35             */

+#define FDCAN_NDAT2_ND36_Pos      (4U)

+#define FDCAN_NDAT2_ND36_Msk      (0x1UL << FDCAN_NDAT2_ND36_Pos)              /*!< 0x00000010 */

+#define FDCAN_NDAT2_ND36          FDCAN_NDAT2_ND36_Msk                         /*!<New Data flag of Rx Buffer 36             */

+#define FDCAN_NDAT2_ND37_Pos      (5U)

+#define FDCAN_NDAT2_ND37_Msk      (0x1UL << FDCAN_NDAT2_ND37_Pos)              /*!< 0x00000020 */

+#define FDCAN_NDAT2_ND37          FDCAN_NDAT2_ND37_Msk                         /*!<New Data flag of Rx Buffer 37             */

+#define FDCAN_NDAT2_ND38_Pos      (6U)

+#define FDCAN_NDAT2_ND38_Msk      (0x1UL << FDCAN_NDAT2_ND38_Pos)              /*!< 0x00000040 */

+#define FDCAN_NDAT2_ND38          FDCAN_NDAT2_ND38_Msk                         /*!<New Data flag of Rx Buffer 38             */

+#define FDCAN_NDAT2_ND39_Pos      (7U)

+#define FDCAN_NDAT2_ND39_Msk      (0x1UL << FDCAN_NDAT2_ND39_Pos)              /*!< 0x00000080 */

+#define FDCAN_NDAT2_ND39          FDCAN_NDAT2_ND39_Msk                         /*!<New Data flag of Rx Buffer 39             */

+#define FDCAN_NDAT2_ND40_Pos      (8U)

+#define FDCAN_NDAT2_ND40_Msk      (0x1UL << FDCAN_NDAT2_ND40_Pos)              /*!< 0x00000100 */

+#define FDCAN_NDAT2_ND40          FDCAN_NDAT2_ND40_Msk                         /*!<New Data flag of Rx Buffer 40             */

+#define FDCAN_NDAT2_ND41_Pos      (9U)

+#define FDCAN_NDAT2_ND41_Msk      (0x1UL << FDCAN_NDAT2_ND41_Pos)              /*!< 0x00000200 */

+#define FDCAN_NDAT2_ND41          FDCAN_NDAT2_ND41_Msk                         /*!<New Data flag of Rx Buffer 41             */

+#define FDCAN_NDAT2_ND42_Pos      (10U)

+#define FDCAN_NDAT2_ND42_Msk      (0x1UL << FDCAN_NDAT2_ND42_Pos)              /*!< 0x00000400 */

+#define FDCAN_NDAT2_ND42          FDCAN_NDAT2_ND42_Msk                         /*!<New Data flag of Rx Buffer 42             */

+#define FDCAN_NDAT2_ND43_Pos      (11U)

+#define FDCAN_NDAT2_ND43_Msk      (0x1UL << FDCAN_NDAT2_ND43_Pos)              /*!< 0x00000800 */

+#define FDCAN_NDAT2_ND43          FDCAN_NDAT2_ND43_Msk                         /*!<New Data flag of Rx Buffer 43             */

+#define FDCAN_NDAT2_ND44_Pos      (12U)

+#define FDCAN_NDAT2_ND44_Msk      (0x1UL << FDCAN_NDAT2_ND44_Pos)              /*!< 0x00001000 */

+#define FDCAN_NDAT2_ND44          FDCAN_NDAT2_ND44_Msk                         /*!<New Data flag of Rx Buffer 44             */

+#define FDCAN_NDAT2_ND45_Pos      (13U)

+#define FDCAN_NDAT2_ND45_Msk      (0x1UL << FDCAN_NDAT2_ND45_Pos)              /*!< 0x00002000 */

+#define FDCAN_NDAT2_ND45          FDCAN_NDAT2_ND45_Msk                         /*!<New Data flag of Rx Buffer 45             */

+#define FDCAN_NDAT2_ND46_Pos      (14U)

+#define FDCAN_NDAT2_ND46_Msk      (0x1UL << FDCAN_NDAT2_ND46_Pos)              /*!< 0x00004000 */

+#define FDCAN_NDAT2_ND46          FDCAN_NDAT2_ND46_Msk                         /*!<New Data flag of Rx Buffer 46             */

+#define FDCAN_NDAT2_ND47_Pos      (15U)

+#define FDCAN_NDAT2_ND47_Msk      (0x1UL << FDCAN_NDAT2_ND47_Pos)              /*!< 0x00008000 */

+#define FDCAN_NDAT2_ND47          FDCAN_NDAT2_ND47_Msk                         /*!<New Data flag of Rx Buffer 47             */

+#define FDCAN_NDAT2_ND48_Pos      (16U)

+#define FDCAN_NDAT2_ND48_Msk      (0x1UL << FDCAN_NDAT2_ND48_Pos)              /*!< 0x00010000 */

+#define FDCAN_NDAT2_ND48          FDCAN_NDAT2_ND48_Msk                         /*!<New Data flag of Rx Buffer 48             */

+#define FDCAN_NDAT2_ND49_Pos      (17U)

+#define FDCAN_NDAT2_ND49_Msk      (0x1UL << FDCAN_NDAT2_ND49_Pos)              /*!< 0x00020000 */

+#define FDCAN_NDAT2_ND49          FDCAN_NDAT2_ND49_Msk                         /*!<New Data flag of Rx Buffer 49             */

+#define FDCAN_NDAT2_ND50_Pos      (18U)

+#define FDCAN_NDAT2_ND50_Msk      (0x1UL << FDCAN_NDAT2_ND50_Pos)              /*!< 0x00040000 */

+#define FDCAN_NDAT2_ND50          FDCAN_NDAT2_ND50_Msk                         /*!<New Data flag of Rx Buffer 50             */

+#define FDCAN_NDAT2_ND51_Pos      (19U)

+#define FDCAN_NDAT2_ND51_Msk      (0x1UL << FDCAN_NDAT2_ND51_Pos)              /*!< 0x00080000 */

+#define FDCAN_NDAT2_ND51          FDCAN_NDAT2_ND51_Msk                         /*!<New Data flag of Rx Buffer 51             */

+#define FDCAN_NDAT2_ND52_Pos      (20U)

+#define FDCAN_NDAT2_ND52_Msk      (0x1UL << FDCAN_NDAT2_ND52_Pos)              /*!< 0x00100000 */

+#define FDCAN_NDAT2_ND52          FDCAN_NDAT2_ND52_Msk                         /*!<New Data flag of Rx Buffer 52             */

+#define FDCAN_NDAT2_ND53_Pos      (21U)

+#define FDCAN_NDAT2_ND53_Msk      (0x1UL << FDCAN_NDAT2_ND53_Pos)              /*!< 0x00200000 */

+#define FDCAN_NDAT2_ND53          FDCAN_NDAT2_ND53_Msk                         /*!<New Data flag of Rx Buffer 53             */

+#define FDCAN_NDAT2_ND54_Pos      (22U)

+#define FDCAN_NDAT2_ND54_Msk      (0x1UL << FDCAN_NDAT2_ND54_Pos)              /*!< 0x00400000 */

+#define FDCAN_NDAT2_ND54          FDCAN_NDAT2_ND54_Msk                         /*!<New Data flag of Rx Buffer 54             */

+#define FDCAN_NDAT2_ND55_Pos      (23U)

+#define FDCAN_NDAT2_ND55_Msk      (0x1UL << FDCAN_NDAT2_ND55_Pos)              /*!< 0x00800000 */

+#define FDCAN_NDAT2_ND55          FDCAN_NDAT2_ND55_Msk                         /*!<New Data flag of Rx Buffer 55             */

+#define FDCAN_NDAT2_ND56_Pos      (24U)

+#define FDCAN_NDAT2_ND56_Msk      (0x1UL << FDCAN_NDAT2_ND56_Pos)              /*!< 0x01000000 */

+#define FDCAN_NDAT2_ND56          FDCAN_NDAT2_ND56_Msk                         /*!<New Data flag of Rx Buffer 56             */

+#define FDCAN_NDAT2_ND57_Pos      (25U)

+#define FDCAN_NDAT2_ND57_Msk      (0x1UL << FDCAN_NDAT2_ND57_Pos)              /*!< 0x02000000 */

+#define FDCAN_NDAT2_ND57          FDCAN_NDAT2_ND57_Msk                         /*!<New Data flag of Rx Buffer 57             */

+#define FDCAN_NDAT2_ND58_Pos      (26U)

+#define FDCAN_NDAT2_ND58_Msk      (0x1UL << FDCAN_NDAT2_ND58_Pos)              /*!< 0x04000000 */

+#define FDCAN_NDAT2_ND58          FDCAN_NDAT2_ND58_Msk                         /*!<New Data flag of Rx Buffer 58             */

+#define FDCAN_NDAT2_ND59_Pos      (27U)

+#define FDCAN_NDAT2_ND59_Msk      (0x1UL << FDCAN_NDAT2_ND59_Pos)              /*!< 0x08000000 */

+#define FDCAN_NDAT2_ND59          FDCAN_NDAT2_ND59_Msk                         /*!<New Data flag of Rx Buffer 59             */

+#define FDCAN_NDAT2_ND60_Pos      (28U)

+#define FDCAN_NDAT2_ND60_Msk      (0x1UL << FDCAN_NDAT2_ND60_Pos)              /*!< 0x10000000 */

+#define FDCAN_NDAT2_ND60          FDCAN_NDAT2_ND60_Msk                         /*!<New Data flag of Rx Buffer 60             */

+#define FDCAN_NDAT2_ND61_Pos      (29U)

+#define FDCAN_NDAT2_ND61_Msk      (0x1UL << FDCAN_NDAT2_ND61_Pos)              /*!< 0x20000000 */

+#define FDCAN_NDAT2_ND61          FDCAN_NDAT2_ND61_Msk                         /*!<New Data flag of Rx Buffer 61             */

+#define FDCAN_NDAT2_ND62_Pos      (30U)

+#define FDCAN_NDAT2_ND62_Msk      (0x1UL << FDCAN_NDAT2_ND62_Pos)              /*!< 0x40000000 */

+#define FDCAN_NDAT2_ND62          FDCAN_NDAT2_ND62_Msk                         /*!<New Data flag of Rx Buffer 62             */

+#define FDCAN_NDAT2_ND63_Pos      (31U)

+#define FDCAN_NDAT2_ND63_Msk      (0x1UL << FDCAN_NDAT2_ND63_Pos)              /*!< 0x80000000 */

+#define FDCAN_NDAT2_ND63          FDCAN_NDAT2_ND63_Msk                         /*!<New Data flag of Rx Buffer 63             */

+

+/*****************  Bit definition for FDCAN_RXF0C register  ********************/

+#define FDCAN_RXF0C_F0SA_Pos      (2U)

+#define FDCAN_RXF0C_F0SA_Msk      (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_RXF0C_F0SA          FDCAN_RXF0C_F0SA_Msk                         /*!<Rx FIFO 0 Start Address                   */

+#define FDCAN_RXF0C_F0S_Pos       (16U)

+#define FDCAN_RXF0C_F0S_Msk       (0x7FUL << FDCAN_RXF0C_F0S_Pos)              /*!< 0x007F0000 */

+#define FDCAN_RXF0C_F0S           FDCAN_RXF0C_F0S_Msk                          /*!<Number of Rx FIFO 0 elements              */

+#define FDCAN_RXF0C_F0WM_Pos      (24U)

+#define FDCAN_RXF0C_F0WM_Msk      (0x7FUL << FDCAN_RXF0C_F0WM_Pos)             /*!< 0x7F000000 */

+#define FDCAN_RXF0C_F0WM          FDCAN_RXF0C_F0WM_Msk                         /*!<FIFO 0 Watermark                          */

+#define FDCAN_RXF0C_F0OM_Pos      (31U)

+#define FDCAN_RXF0C_F0OM_Msk      (0x1UL << FDCAN_RXF0C_F0OM_Pos)              /*!< 0x80000000 */

+#define FDCAN_RXF0C_F0OM          FDCAN_RXF0C_F0OM_Msk                         /*!<FIFO 0 Operation Mode                     */

+

+/*****************  Bit definition for FDCAN_RXF0S register  ********************/

+#define FDCAN_RXF0S_F0FL_Pos      (0U)

+#define FDCAN_RXF0S_F0FL_Msk      (0x7FUL << FDCAN_RXF0S_F0FL_Pos)             /*!< 0x0000007F */

+#define FDCAN_RXF0S_F0FL          FDCAN_RXF0S_F0FL_Msk                         /*!<Rx FIFO 0 Fill Level                      */

+#define FDCAN_RXF0S_F0GI_Pos      (8U)

+#define FDCAN_RXF0S_F0GI_Msk      (0x3FUL << FDCAN_RXF0S_F0GI_Pos)             /*!< 0x00003F00 */

+#define FDCAN_RXF0S_F0GI          FDCAN_RXF0S_F0GI_Msk                         /*!<Rx FIFO 0 Get Index                       */

+#define FDCAN_RXF0S_F0PI_Pos      (16U)

+#define FDCAN_RXF0S_F0PI_Msk      (0x3FUL << FDCAN_RXF0S_F0PI_Pos)             /*!< 0x003F0000 */

+#define FDCAN_RXF0S_F0PI          FDCAN_RXF0S_F0PI_Msk                         /*!<Rx FIFO 0 Put Index                       */

+#define FDCAN_RXF0S_F0F_Pos       (24U)

+#define FDCAN_RXF0S_F0F_Msk       (0x1UL << FDCAN_RXF0S_F0F_Pos)               /*!< 0x01000000 */

+#define FDCAN_RXF0S_F0F           FDCAN_RXF0S_F0F_Msk                          /*!<Rx FIFO 0 Full                            */

+#define FDCAN_RXF0S_RF0L_Pos      (25U)

+#define FDCAN_RXF0S_RF0L_Msk      (0x1UL << FDCAN_RXF0S_RF0L_Pos)              /*!< 0x02000000 */

+#define FDCAN_RXF0S_RF0L          FDCAN_RXF0S_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                    */

+

+/*****************  Bit definition for FDCAN_RXF0A register  ********************/

+#define FDCAN_RXF0A_F0AI_Pos      (0U)

+#define FDCAN_RXF0A_F0AI_Msk      (0x3FUL << FDCAN_RXF0A_F0AI_Pos)             /*!< 0x0000003F */

+#define FDCAN_RXF0A_F0AI          FDCAN_RXF0A_F0AI_Msk                         /*!<Rx FIFO 0 Acknowledge Index               */

+

+/*****************  Bit definition for FDCAN_RXBC register  ********************/

+#define FDCAN_RXBC_RBSA_Pos       (2U)

+#define FDCAN_RXBC_RBSA_Msk       (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)            /*!< 0x0000FFFC */

+#define FDCAN_RXBC_RBSA           FDCAN_RXBC_RBSA_Msk                          /*!<Rx Buffer Start Address                   */

+

+/*****************  Bit definition for FDCAN_RXF1C register  ********************/

+#define FDCAN_RXF1C_F1SA_Pos      (2U)

+#define FDCAN_RXF1C_F1SA_Msk      (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_RXF1C_F1SA          FDCAN_RXF1C_F1SA_Msk                         /*!<Rx FIFO 1 Start Address                   */

+#define FDCAN_RXF1C_F1S_Pos       (16U)

+#define FDCAN_RXF1C_F1S_Msk       (0x7FUL << FDCAN_RXF1C_F1S_Pos)              /*!< 0x007F0000 */

+#define FDCAN_RXF1C_F1S           FDCAN_RXF1C_F1S_Msk                          /*!<Number of Rx FIFO 1 elements              */

+#define FDCAN_RXF1C_F1WM_Pos      (24U)

+#define FDCAN_RXF1C_F1WM_Msk      (0x7FUL << FDCAN_RXF1C_F1WM_Pos)             /*!< 0x7F000000 */

+#define FDCAN_RXF1C_F1WM          FDCAN_RXF1C_F1WM_Msk                         /*!<Rx FIFO 1 Watermark                       */

+#define FDCAN_RXF1C_F1OM_Pos      (31U)

+#define FDCAN_RXF1C_F1OM_Msk      (0x1UL << FDCAN_RXF1C_F1OM_Pos)              /*!< 0x80000000 */

+#define FDCAN_RXF1C_F1OM          FDCAN_RXF1C_F1OM_Msk                         /*!<FIFO 1 Operation Mode                     */

+

+/*****************  Bit definition for FDCAN_RXF1S register  ********************/

+#define FDCAN_RXF1S_F1FL_Pos      (0U)

+#define FDCAN_RXF1S_F1FL_Msk      (0x7FUL << FDCAN_RXF1S_F1FL_Pos)             /*!< 0x0000007F */

+#define FDCAN_RXF1S_F1FL          FDCAN_RXF1S_F1FL_Msk                         /*!<Rx FIFO 1 Fill Level                      */

+#define FDCAN_RXF1S_F1GI_Pos      (8U)

+#define FDCAN_RXF1S_F1GI_Msk      (0x3FUL << FDCAN_RXF1S_F1GI_Pos)             /*!< 0x00003F00 */

+#define FDCAN_RXF1S_F1GI          FDCAN_RXF1S_F1GI_Msk                         /*!<Rx FIFO 1 Get Index                       */

+#define FDCAN_RXF1S_F1PI_Pos      (16U)

+#define FDCAN_RXF1S_F1PI_Msk      (0x3FUL << FDCAN_RXF1S_F1PI_Pos)             /*!< 0x003F0000 */

+#define FDCAN_RXF1S_F1PI          FDCAN_RXF1S_F1PI_Msk                         /*!<Rx FIFO 1 Put Index                       */

+#define FDCAN_RXF1S_F1F_Pos       (24U)

+#define FDCAN_RXF1S_F1F_Msk       (0x1UL << FDCAN_RXF1S_F1F_Pos)               /*!< 0x01000000 */

+#define FDCAN_RXF1S_F1F           FDCAN_RXF1S_F1F_Msk                          /*!<Rx FIFO 1 Full                            */

+#define FDCAN_RXF1S_RF1L_Pos      (25U)

+#define FDCAN_RXF1S_RF1L_Msk      (0x1UL << FDCAN_RXF1S_RF1L_Pos)              /*!< 0x02000000 */

+#define FDCAN_RXF1S_RF1L          FDCAN_RXF1S_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                    */

+

+/*****************  Bit definition for FDCAN_RXF1A register  ********************/

+#define FDCAN_RXF1A_F1AI_Pos      (0U)

+#define FDCAN_RXF1A_F1AI_Msk      (0x3FUL << FDCAN_RXF1A_F1AI_Pos)             /*!< 0x0000003F */

+#define FDCAN_RXF1A_F1AI          FDCAN_RXF1A_F1AI_Msk                         /*!<Rx FIFO 1 Acknowledge Index               */

+

+/*****************  Bit definition for FDCAN_RXESC register  ********************/

+#define FDCAN_RXESC_F0DS_Pos      (0U)

+#define FDCAN_RXESC_F0DS_Msk      (0x7UL << FDCAN_RXESC_F0DS_Pos)              /*!< 0x00000007 */

+#define FDCAN_RXESC_F0DS          FDCAN_RXESC_F0DS_Msk                         /*!<Rx FIFO 1 Data Field Size                 */

+#define FDCAN_RXESC_F1DS_Pos      (4U)

+#define FDCAN_RXESC_F1DS_Msk      (0x7UL << FDCAN_RXESC_F1DS_Pos)              /*!< 0x00000070 */

+#define FDCAN_RXESC_F1DS          FDCAN_RXESC_F1DS_Msk                         /*!<Rx FIFO 0 Data Field Size                 */

+#define FDCAN_RXESC_RBDS_Pos      (8U)

+#define FDCAN_RXESC_RBDS_Msk      (0x7UL << FDCAN_RXESC_RBDS_Pos)              /*!< 0x00000700 */

+#define FDCAN_RXESC_RBDS          FDCAN_RXESC_RBDS_Msk                         /*!<Rx Buffer Data Field Size                 */

+

+/*****************  Bit definition for FDCAN_TXBC register  *********************/

+#define FDCAN_TXBC_TBSA_Pos       (2U)

+#define FDCAN_TXBC_TBSA_Msk       (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)            /*!< 0x0000FFFC */

+#define FDCAN_TXBC_TBSA           FDCAN_TXBC_TBSA_Msk                          /*!<Tx Buffers Start Address                  */

+#define FDCAN_TXBC_NDTB_Pos       (16U)

+#define FDCAN_TXBC_NDTB_Msk       (0x3FUL << FDCAN_TXBC_NDTB_Pos)              /*!< 0x003F0000 */

+#define FDCAN_TXBC_NDTB           FDCAN_TXBC_NDTB_Msk                          /*!<Number of Dedicated Transmit Buffers      */

+#define FDCAN_TXBC_TFQS_Pos       (24U)

+#define FDCAN_TXBC_TFQS_Msk       (0x3FUL << FDCAN_TXBC_TFQS_Pos)              /*!< 0x3F000000 */

+#define FDCAN_TXBC_TFQS           FDCAN_TXBC_TFQS_Msk                          /*!<Transmit FIFO/Queue Size                  */

+#define FDCAN_TXBC_TFQM_Pos       (30U)

+#define FDCAN_TXBC_TFQM_Msk       (0x1UL << FDCAN_TXBC_TFQM_Pos)               /*!< 0x40000000 */

+#define FDCAN_TXBC_TFQM           FDCAN_TXBC_TFQM_Msk                          /*!<Tx FIFO/Queue Mode                        */

+

+/*****************  Bit definition for FDCAN_TXFQS register  *********************/

+#define FDCAN_TXFQS_TFFL_Pos      (0U)

+#define FDCAN_TXFQS_TFFL_Msk      (0x3FUL << FDCAN_TXFQS_TFFL_Pos)             /*!< 0x0000003F */

+#define FDCAN_TXFQS_TFFL          FDCAN_TXFQS_TFFL_Msk                         /*!<Tx FIFO Free Level                        */

+#define FDCAN_TXFQS_TFGI_Pos      (8U)

+#define FDCAN_TXFQS_TFGI_Msk      (0x1FUL << FDCAN_TXFQS_TFGI_Pos)             /*!< 0x00001F00 */

+#define FDCAN_TXFQS_TFGI          FDCAN_TXFQS_TFGI_Msk                         /*!<Tx FIFO Get Index                         */

+#define FDCAN_TXFQS_TFQPI_Pos     (16U)

+#define FDCAN_TXFQS_TFQPI_Msk     (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)            /*!< 0x001F0000 */

+#define FDCAN_TXFQS_TFQPI         FDCAN_TXFQS_TFQPI_Msk                        /*!<Tx FIFO/Queue Put Index                   */

+#define FDCAN_TXFQS_TFQF_Pos      (21U)

+#define FDCAN_TXFQS_TFQF_Msk      (0x1UL << FDCAN_TXFQS_TFQF_Pos)              /*!< 0x00200000 */

+#define FDCAN_TXFQS_TFQF          FDCAN_TXFQS_TFQF_Msk                         /*!<Tx FIFO/Queue Full                        */

+

+/*****************  Bit definition for FDCAN_TXESC register  *********************/

+#define FDCAN_TXESC_TBDS_Pos      (0U)

+#define FDCAN_TXESC_TBDS_Msk      (0x7UL << FDCAN_TXESC_TBDS_Pos)              /*!< 0x00000007 */

+#define FDCAN_TXESC_TBDS          FDCAN_TXESC_TBDS_Msk                         /*!<Tx Buffer Data Field Size                 */

+

+/*****************  Bit definition for FDCAN_TXBRP register  *********************/

+#define FDCAN_TXBRP_TRP_Pos       (0U)

+#define FDCAN_TXBRP_TRP_Msk       (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)        /*!< 0xFFFFFFFF */

+#define FDCAN_TXBRP_TRP           FDCAN_TXBRP_TRP_Msk                          /*!<Transmission Request Pending              */

+

+/*****************  Bit definition for FDCAN_TXBAR register  *********************/

+#define FDCAN_TXBAR_AR_Pos        (0U)

+#define FDCAN_TXBAR_AR_Msk        (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBAR_AR            FDCAN_TXBAR_AR_Msk                           /*!<Add Request                               */

+

+/*****************  Bit definition for FDCAN_TXBCR register  *********************/

+#define FDCAN_TXBCR_CR_Pos        (0U)

+#define FDCAN_TXBCR_CR_Msk        (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCR_CR            FDCAN_TXBCR_CR_Msk                           /*!<Cancellation Request                      */

+

+/*****************  Bit definition for FDCAN_TXBTO register  *********************/

+#define FDCAN_TXBTO_TO_Pos        (0U)

+#define FDCAN_TXBTO_TO_Msk        (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBTO_TO            FDCAN_TXBTO_TO_Msk                           /*!<Transmission Occurred                     */

+

+/*****************  Bit definition for FDCAN_TXBCF register  *********************/

+#define FDCAN_TXBCF_CF_Pos        (0U)

+#define FDCAN_TXBCF_CF_Msk        (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCF_CF            FDCAN_TXBCF_CF_Msk                           /*!<Cancellation Finished                     */

+

+/*****************  Bit definition for FDCAN_TXBTIE register  ********************/

+#define FDCAN_TXBTIE_TIE_Pos      (0U)

+#define FDCAN_TXBTIE_TIE_Msk      (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)       /*!< 0xFFFFFFFF */

+#define FDCAN_TXBTIE_TIE          FDCAN_TXBTIE_TIE_Msk                         /*!<Transmission Interrupt Enable             */

+

+/*****************  Bit definition for FDCAN_ TXBCIE register  *******************/

+#define FDCAN_TXBCIE_CFIE_Pos     (0U)

+#define FDCAN_TXBCIE_CFIE_Msk     (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)      /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCIE_CFIE         FDCAN_TXBCIE_CFIE_Msk                        /*!<Cancellation Finished Interrupt Enable    */

+

+/*****************  Bit definition for FDCAN_TXEFC register  *********************/

+#define FDCAN_TXEFC_EFSA_Pos      (2U)

+#define FDCAN_TXEFC_EFSA_Msk      (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_TXEFC_EFSA          FDCAN_TXEFC_EFSA_Msk                         /*!<Event FIFO Start Address                  */

+#define FDCAN_TXEFC_EFS_Pos       (16U)

+#define FDCAN_TXEFC_EFS_Msk       (0x3FUL << FDCAN_TXEFC_EFS_Pos)              /*!< 0x003F0000 */

+#define FDCAN_TXEFC_EFS           FDCAN_TXEFC_EFS_Msk                          /*!<Event FIFO Size                           */

+#define FDCAN_TXEFC_EFWM_Pos      (24U)

+#define FDCAN_TXEFC_EFWM_Msk      (0x3FUL << FDCAN_TXEFC_EFWM_Pos)             /*!< 0x3F000000 */

+#define FDCAN_TXEFC_EFWM          FDCAN_TXEFC_EFWM_Msk                         /*!<Event FIFO Watermark                      */

+

+/*****************  Bit definition for FDCAN_TXEFS register  *********************/

+#define FDCAN_TXEFS_EFFL_Pos      (0U)

+#define FDCAN_TXEFS_EFFL_Msk      (0x3FUL << FDCAN_TXEFS_EFFL_Pos)             /*!< 0x0000003F */

+#define FDCAN_TXEFS_EFFL          FDCAN_TXEFS_EFFL_Msk                         /*!<Event FIFO Fill Level                     */

+#define FDCAN_TXEFS_EFGI_Pos      (8U)

+#define FDCAN_TXEFS_EFGI_Msk      (0x1FUL << FDCAN_TXEFS_EFGI_Pos)             /*!< 0x00001F00 */

+#define FDCAN_TXEFS_EFGI          FDCAN_TXEFS_EFGI_Msk                         /*!<Event FIFO Get Index                      */

+#define FDCAN_TXEFS_EFPI_Pos      (16U)

+#define FDCAN_TXEFS_EFPI_Msk      (0x1FUL << FDCAN_TXEFS_EFPI_Pos)             /*!< 0x001F0000 */

+#define FDCAN_TXEFS_EFPI          FDCAN_TXEFS_EFPI_Msk                         /*!<Event FIFO Put Index                      */

+#define FDCAN_TXEFS_EFF_Pos       (24U)

+#define FDCAN_TXEFS_EFF_Msk       (0x1UL << FDCAN_TXEFS_EFF_Pos)               /*!< 0x01000000 */

+#define FDCAN_TXEFS_EFF           FDCAN_TXEFS_EFF_Msk                          /*!<Event FIFO Full                           */

+#define FDCAN_TXEFS_TEFL_Pos      (25U)

+#define FDCAN_TXEFS_TEFL_Msk      (0x1UL << FDCAN_TXEFS_TEFL_Pos)              /*!< 0x02000000 */

+#define FDCAN_TXEFS_TEFL          FDCAN_TXEFS_TEFL_Msk                         /*!<Tx Event FIFO Element Lost                */

+

+/*****************  Bit definition for FDCAN_TXEFA register  *********************/

+#define FDCAN_TXEFA_EFAI_Pos      (0U)

+#define FDCAN_TXEFA_EFAI_Msk      (0x1FUL << FDCAN_TXEFA_EFAI_Pos)             /*!< 0x0000001F */

+#define FDCAN_TXEFA_EFAI          FDCAN_TXEFA_EFAI_Msk                         /*!<Event FIFO Acknowledge Index              */

+

+/*****************  Bit definition for FDCAN_TTTMC register  *********************/

+#define FDCAN_TTTMC_TMSA_Pos      (2U)

+#define FDCAN_TTTMC_TMSA_Msk      (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_TTTMC_TMSA          FDCAN_TTTMC_TMSA_Msk                         /*!<Trigger Memory Start Address              */

+#define FDCAN_TTTMC_TME_Pos       (16U)

+#define FDCAN_TTTMC_TME_Msk       (0x7FUL << FDCAN_TTTMC_TME_Pos)              /*!< 0x007F0000 */

+#define FDCAN_TTTMC_TME           FDCAN_TTTMC_TME_Msk                          /*!<Trigger Memory Elements                   */

+

+/*****************  Bit definition for FDCAN_TTRMC register  *********************/

+#define FDCAN_TTRMC_RID_Pos       (0U)

+#define FDCAN_TTRMC_RID_Msk       (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)        /*!< 0x1FFFFFFF */

+#define FDCAN_TTRMC_RID           FDCAN_TTRMC_RID_Msk                          /*!<Reference Identifier                      */

+#define FDCAN_TTRMC_XTD_Pos       (30U)

+#define FDCAN_TTRMC_XTD_Msk       (0x1UL << FDCAN_TTRMC_XTD_Pos)               /*!< 0x40000000 */

+#define FDCAN_TTRMC_XTD           FDCAN_TTRMC_XTD_Msk                          /*!< Extended Identifier                      */

+#define FDCAN_TTRMC_RMPS_Pos      (31U)

+#define FDCAN_TTRMC_RMPS_Msk      (0x1UL << FDCAN_TTRMC_RMPS_Pos)              /*!< 0x80000000 */

+#define FDCAN_TTRMC_RMPS          FDCAN_TTRMC_RMPS_Msk                         /*!<Reference Message Payload Select          */

+

+/*****************  Bit definition for FDCAN_TTOCF register  *********************/

+#define FDCAN_TTOCF_OM_Pos        (0U)

+#define FDCAN_TTOCF_OM_Msk        (0x3UL << FDCAN_TTOCF_OM_Pos)                /*!< 0x00000003 */

+#define FDCAN_TTOCF_OM            FDCAN_TTOCF_OM_Msk                           /*!<Operation Mode                            */

+#define FDCAN_TTOCF_GEN_Pos       (3U)

+#define FDCAN_TTOCF_GEN_Msk       (0x1UL << FDCAN_TTOCF_GEN_Pos)               /*!< 0x00000008 */

+#define FDCAN_TTOCF_GEN           FDCAN_TTOCF_GEN_Msk                          /*!<Gap Enable                                */

+#define FDCAN_TTOCF_TM_Pos        (4U)

+#define FDCAN_TTOCF_TM_Msk        (0x1UL << FDCAN_TTOCF_TM_Pos)                /*!< 0x00000010 */

+#define FDCAN_TTOCF_TM            FDCAN_TTOCF_TM_Msk                           /*!<Time Master                               */

+#define FDCAN_TTOCF_LDSDL_Pos     (5U)

+#define FDCAN_TTOCF_LDSDL_Msk     (0x7UL << FDCAN_TTOCF_LDSDL_Pos)             /*!< 0x000000E0 */

+#define FDCAN_TTOCF_LDSDL         FDCAN_TTOCF_LDSDL_Msk                        /*!<LD of Synchronization Deviation Limit     */

+#define FDCAN_TTOCF_IRTO_Pos      (8U)

+#define FDCAN_TTOCF_IRTO_Msk      (0x7FUL << FDCAN_TTOCF_IRTO_Pos)             /*!< 0x00007F00 */

+#define FDCAN_TTOCF_IRTO          FDCAN_TTOCF_IRTO_Msk                         /*!<Initial Reference Trigger Offset          */

+#define FDCAN_TTOCF_EECS_Pos      (15U)

+#define FDCAN_TTOCF_EECS_Msk      (0x1UL << FDCAN_TTOCF_EECS_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTOCF_EECS          FDCAN_TTOCF_EECS_Msk                         /*!<Enable External Clock Synchronization     */

+#define FDCAN_TTOCF_AWL_Pos       (16U)

+#define FDCAN_TTOCF_AWL_Msk       (0xFFUL << FDCAN_TTOCF_AWL_Pos)              /*!< 0x00FF0000 */

+#define FDCAN_TTOCF_AWL           FDCAN_TTOCF_AWL_Msk                          /*!<Application Watchdog Limit                */

+#define FDCAN_TTOCF_EGTF_Pos      (24U)

+#define FDCAN_TTOCF_EGTF_Msk      (0x1UL << FDCAN_TTOCF_EGTF_Pos)              /*!< 0x01000000 */

+#define FDCAN_TTOCF_EGTF          FDCAN_TTOCF_EGTF_Msk                         /*!<Enable Global Time Filtering              */

+#define FDCAN_TTOCF_ECC_Pos       (25U)

+#define FDCAN_TTOCF_ECC_Msk       (0x1UL << FDCAN_TTOCF_ECC_Pos)               /*!< 0x02000000 */

+#define FDCAN_TTOCF_ECC           FDCAN_TTOCF_ECC_Msk                          /*!<Enable Clock Calibration                  */

+#define FDCAN_TTOCF_EVTP_Pos      (26U)

+#define FDCAN_TTOCF_EVTP_Msk      (0x1UL << FDCAN_TTOCF_EVTP_Pos)              /*!< 0x04000000 */

+#define FDCAN_TTOCF_EVTP          FDCAN_TTOCF_EVTP_Msk                         /*!<Event Trigger Polarity                    */

+

+/*****************  Bit definition for FDCAN_TTMLM register  *********************/

+#define FDCAN_TTMLM_CCM_Pos       (0U)

+#define FDCAN_TTMLM_CCM_Msk       (0x3FUL << FDCAN_TTMLM_CCM_Pos)              /*!< 0x0000003F */

+#define FDCAN_TTMLM_CCM           FDCAN_TTMLM_CCM_Msk                          /*!<Cycle Count Max                           */

+#define FDCAN_TTMLM_CSS_Pos       (6U)

+#define FDCAN_TTMLM_CSS_Msk       (0x3UL << FDCAN_TTMLM_CSS_Pos)               /*!< 0x000000C0 */

+#define FDCAN_TTMLM_CSS           FDCAN_TTMLM_CSS_Msk                          /*!<Cycle Start Synchronization               */

+#define FDCAN_TTMLM_TXEW_Pos      (8U)

+#define FDCAN_TTMLM_TXEW_Msk      (0xFUL << FDCAN_TTMLM_TXEW_Pos)              /*!< 0x00000F00 */

+#define FDCAN_TTMLM_TXEW          FDCAN_TTMLM_TXEW_Msk                         /*!<Tx Enable Window                          */

+#define FDCAN_TTMLM_ENTT_Pos      (16U)

+#define FDCAN_TTMLM_ENTT_Msk      (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)            /*!< 0x0FFF0000 */

+#define FDCAN_TTMLM_ENTT          FDCAN_TTMLM_ENTT_Msk                         /*!<Expected Number of Tx Triggers            */

+

+/*****************  Bit definition for FDCAN_TURCF register  *********************/

+#define FDCAN_TURCF_NCL_Pos       (0U)

+#define FDCAN_TURCF_NCL_Msk       (0xFFFFUL << FDCAN_TURCF_NCL_Pos)            /*!< 0x0000FFFF */

+#define FDCAN_TURCF_NCL           FDCAN_TURCF_NCL_Msk                          /*!<Numerator Configuration Low               */

+#define FDCAN_TURCF_DC_Pos        (16U)

+#define FDCAN_TURCF_DC_Msk        (0x3FFFUL << FDCAN_TURCF_DC_Pos)             /*!< 0x3FFF0000 */

+#define FDCAN_TURCF_DC            FDCAN_TURCF_DC_Msk                           /*!<Denominator Configuration                 */

+#define FDCAN_TURCF_ELT_Pos       (31U)

+#define FDCAN_TURCF_ELT_Msk       (0x1UL << FDCAN_TURCF_ELT_Pos)               /*!< 0x80000000 */

+#define FDCAN_TURCF_ELT           FDCAN_TURCF_ELT_Msk                          /*!<Enable Local Time                         */

+

+/*****************  Bit definition for FDCAN_TTOCN register  ********************/

+#define FDCAN_TTOCN_SGT_Pos       (0U)

+#define FDCAN_TTOCN_SGT_Msk       (0x1UL << FDCAN_TTOCN_SGT_Pos)               /*!< 0x00000001 */

+#define FDCAN_TTOCN_SGT           FDCAN_TTOCN_SGT_Msk                          /*!<Set Global time                           */

+#define FDCAN_TTOCN_ECS_Pos       (1U)

+#define FDCAN_TTOCN_ECS_Msk       (0x1UL << FDCAN_TTOCN_ECS_Pos)               /*!< 0x00000002 */

+#define FDCAN_TTOCN_ECS           FDCAN_TTOCN_ECS_Msk                          /*!<External Clock Synchronization            */

+#define FDCAN_TTOCN_SWP_Pos       (2U)

+#define FDCAN_TTOCN_SWP_Msk       (0x1UL << FDCAN_TTOCN_SWP_Pos)               /*!< 0x00000004 */

+#define FDCAN_TTOCN_SWP           FDCAN_TTOCN_SWP_Msk                          /*!<Stop Watch Polarity                       */

+#define FDCAN_TTOCN_SWS_Pos       (3U)

+#define FDCAN_TTOCN_SWS_Msk       (0x3UL << FDCAN_TTOCN_SWS_Pos)               /*!< 0x00000018 */

+#define FDCAN_TTOCN_SWS           FDCAN_TTOCN_SWS_Msk                          /*!<Stop Watch Source                         */

+#define FDCAN_TTOCN_RTIE_Pos      (5U)

+#define FDCAN_TTOCN_RTIE_Msk      (0x1UL << FDCAN_TTOCN_RTIE_Pos)              /*!< 0x00000020 */

+#define FDCAN_TTOCN_RTIE          FDCAN_TTOCN_RTIE_Msk                         /*!<Register Time Mark Interrupt Pulse Enable */

+#define FDCAN_TTOCN_TMC_Pos       (6U)

+#define FDCAN_TTOCN_TMC_Msk       (0x3UL << FDCAN_TTOCN_TMC_Pos)               /*!< 0x000000C0 */

+#define FDCAN_TTOCN_TMC           FDCAN_TTOCN_TMC_Msk                          /*!<Register Time Mark Compare                */

+#define FDCAN_TTOCN_TTIE_Pos      (8U)

+#define FDCAN_TTOCN_TTIE_Msk      (0x1UL << FDCAN_TTOCN_TTIE_Pos)              /*!< 0x00000100 */

+#define FDCAN_TTOCN_TTIE          FDCAN_TTOCN_TTIE_Msk                         /*!<Trigger Time Mark Interrupt Pulse Enable  */

+#define FDCAN_TTOCN_GCS_Pos       (9U)

+#define FDCAN_TTOCN_GCS_Msk       (0x1UL << FDCAN_TTOCN_GCS_Pos)               /*!< 0x00000200 */

+#define FDCAN_TTOCN_GCS           FDCAN_TTOCN_GCS_Msk                          /*!<Gap Control Select                        */

+#define FDCAN_TTOCN_FGP_Pos       (10U)

+#define FDCAN_TTOCN_FGP_Msk       (0x1UL << FDCAN_TTOCN_FGP_Pos)               /*!< 0x00000400 */

+#define FDCAN_TTOCN_FGP           FDCAN_TTOCN_FGP_Msk                          /*!<Finish Gap                                */

+#define FDCAN_TTOCN_TMG_Pos       (11U)

+#define FDCAN_TTOCN_TMG_Msk       (0x1UL << FDCAN_TTOCN_TMG_Pos)               /*!< 0x00000800 */

+#define FDCAN_TTOCN_TMG           FDCAN_TTOCN_TMG_Msk                          /*!<Time Mark Gap                             */

+#define FDCAN_TTOCN_NIG_Pos       (12U)

+#define FDCAN_TTOCN_NIG_Msk       (0x1UL << FDCAN_TTOCN_NIG_Pos)               /*!< 0x00001000 */

+#define FDCAN_TTOCN_NIG           FDCAN_TTOCN_NIG_Msk                          /*!<Next is Gap                               */

+#define FDCAN_TTOCN_ESCN_Pos      (13U)

+#define FDCAN_TTOCN_ESCN_Msk      (0x1UL << FDCAN_TTOCN_ESCN_Pos)              /*!< 0x00002000 */

+#define FDCAN_TTOCN_ESCN          FDCAN_TTOCN_ESCN_Msk                         /*!<External Synchronization Control          */

+#define FDCAN_TTOCN_LCKC_Pos      (15U)

+#define FDCAN_TTOCN_LCKC_Msk      (0x1UL << FDCAN_TTOCN_LCKC_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTOCN_LCKC          FDCAN_TTOCN_LCKC_Msk                         /*!<TT Operation Control Register Locked      */

+

+/*****************  Bit definition for FDCAN_TTGTP register  ********************/

+#define FDCAN_TTGTP_TP_Pos        (0U)

+#define FDCAN_TTGTP_TP_Msk        (0xFFFFUL << FDCAN_TTGTP_TP_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTGTP_TP            FDCAN_TTGTP_TP_Msk                           /*!<Time Preset                               */

+#define FDCAN_TTGTP_CTP_Pos       (16U)

+#define FDCAN_TTGTP_CTP_Msk       (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)            /*!< 0xFFFF0000 */

+#define FDCAN_TTGTP_CTP           FDCAN_TTGTP_CTP_Msk                          /*!<Cycle Time Target Phase                   */

+

+/*****************  Bit definition for FDCAN_TTTMK register  ********************/

+#define FDCAN_TTTMK_TM_Pos        (0U)

+#define FDCAN_TTTMK_TM_Msk        (0xFFFFUL << FDCAN_TTTMK_TM_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTTMK_TM            FDCAN_TTTMK_TM_Msk                           /*!<Time Mark                                 */

+#define FDCAN_TTTMK_TICC_Pos      (16U)

+#define FDCAN_TTTMK_TICC_Msk      (0x7FUL << FDCAN_TTTMK_TICC_Pos)             /*!< 0x007F0000 */

+#define FDCAN_TTTMK_TICC          FDCAN_TTTMK_TICC_Msk                         /*!<Time Mark Cycle Code                      */

+#define FDCAN_TTTMK_LCKM_Pos      (31U)

+#define FDCAN_TTTMK_LCKM_Msk      (0x1UL << FDCAN_TTTMK_LCKM_Pos)              /*!< 0x80000000 */

+#define FDCAN_TTTMK_LCKM          FDCAN_TTTMK_LCKM_Msk                         /*!<TT Time Mark Register Locked              */

+

+/*****************  Bit definition for FDCAN_TTIR register  ********************/

+#define FDCAN_TTIR_SBC_Pos        (0U)

+#define FDCAN_TTIR_SBC_Msk        (0x1UL << FDCAN_TTIR_SBC_Pos)                /*!< 0x00000001 */

+#define FDCAN_TTIR_SBC            FDCAN_TTIR_SBC_Msk                           /*!<Start of Basic Cycle                      */

+#define FDCAN_TTIR_SMC_Pos        (1U)

+#define FDCAN_TTIR_SMC_Msk        (0x1UL << FDCAN_TTIR_SMC_Pos)                /*!< 0x00000002 */

+#define FDCAN_TTIR_SMC            FDCAN_TTIR_SMC_Msk                           /*!<Start of Matrix Cycle                     */

+#define FDCAN_TTIR_CSM_Pos        (2U)

+#define FDCAN_TTIR_CSM_Msk        (0x1UL << FDCAN_TTIR_CSM_Pos)                /*!< 0x00000004 */

+#define FDCAN_TTIR_CSM            FDCAN_TTIR_CSM_Msk                           /*!<Change of Synchronization Mode            */

+#define FDCAN_TTIR_SOG_Pos        (3U)

+#define FDCAN_TTIR_SOG_Msk        (0x1UL << FDCAN_TTIR_SOG_Pos)                /*!< 0x00000008 */

+#define FDCAN_TTIR_SOG            FDCAN_TTIR_SOG_Msk                           /*!<Start of Gap                              */

+#define FDCAN_TTIR_RTMI_Pos       (4U)

+#define FDCAN_TTIR_RTMI_Msk       (0x1UL << FDCAN_TTIR_RTMI_Pos)               /*!< 0x00000010 */

+#define FDCAN_TTIR_RTMI           FDCAN_TTIR_RTMI_Msk                          /*!<Register Time Mark Interrupt              */

+#define FDCAN_TTIR_TTMI_Pos       (5U)

+#define FDCAN_TTIR_TTMI_Msk       (0x1UL << FDCAN_TTIR_TTMI_Pos)               /*!< 0x00000020 */

+#define FDCAN_TTIR_TTMI           FDCAN_TTIR_TTMI_Msk                          /*!<Trigger Time Mark Event Internal          */

+#define FDCAN_TTIR_SWE_Pos        (6U)

+#define FDCAN_TTIR_SWE_Msk        (0x1UL << FDCAN_TTIR_SWE_Pos)                /*!< 0x00000040 */

+#define FDCAN_TTIR_SWE            FDCAN_TTIR_SWE_Msk                           /*!<Stop Watch Event                          */

+#define FDCAN_TTIR_GTW_Pos        (7U)

+#define FDCAN_TTIR_GTW_Msk        (0x1UL << FDCAN_TTIR_GTW_Pos)                /*!< 0x00000080 */

+#define FDCAN_TTIR_GTW            FDCAN_TTIR_GTW_Msk                           /*!<Global Time Wrap                          */

+#define FDCAN_TTIR_GTD_Pos        (8U)

+#define FDCAN_TTIR_GTD_Msk        (0x1UL << FDCAN_TTIR_GTD_Pos)                /*!< 0x00000100 */

+#define FDCAN_TTIR_GTD            FDCAN_TTIR_GTD_Msk                           /*!<Global Time Discontinuity                 */

+#define FDCAN_TTIR_GTE_Pos        (9U)

+#define FDCAN_TTIR_GTE_Msk        (0x1UL << FDCAN_TTIR_GTE_Pos)                /*!< 0x00000200 */

+#define FDCAN_TTIR_GTE            FDCAN_TTIR_GTE_Msk                           /*!<Global Time Error                         */

+#define FDCAN_TTIR_TXU_Pos        (10U)

+#define FDCAN_TTIR_TXU_Msk        (0x1UL << FDCAN_TTIR_TXU_Pos)                /*!< 0x00000400 */

+#define FDCAN_TTIR_TXU            FDCAN_TTIR_TXU_Msk                           /*!<Tx Count Underflow                        */

+#define FDCAN_TTIR_TXO_Pos        (11U)

+#define FDCAN_TTIR_TXO_Msk        (0x1UL << FDCAN_TTIR_TXO_Pos)                /*!< 0x00000800 */

+#define FDCAN_TTIR_TXO            FDCAN_TTIR_TXO_Msk                           /*!<Tx Count Overflow                         */

+#define FDCAN_TTIR_SE1_Pos        (12U)

+#define FDCAN_TTIR_SE1_Msk        (0x1UL << FDCAN_TTIR_SE1_Pos)                /*!< 0x00001000 */

+#define FDCAN_TTIR_SE1            FDCAN_TTIR_SE1_Msk                           /*!<Scheduling Error 1                        */

+#define FDCAN_TTIR_SE2_Pos        (13U)

+#define FDCAN_TTIR_SE2_Msk        (0x1UL << FDCAN_TTIR_SE2_Pos)                /*!< 0x00002000 */

+#define FDCAN_TTIR_SE2            FDCAN_TTIR_SE2_Msk                           /*!<Scheduling Error 2                        */

+#define FDCAN_TTIR_ELC_Pos        (14U)

+#define FDCAN_TTIR_ELC_Msk        (0x1UL << FDCAN_TTIR_ELC_Pos)                /*!< 0x00004000 */

+#define FDCAN_TTIR_ELC            FDCAN_TTIR_ELC_Msk                           /*!<Error Level Changed                       */

+#define FDCAN_TTIR_IWT_Pos        (15U)

+#define FDCAN_TTIR_IWT_Msk        (0x1UL << FDCAN_TTIR_IWT_Pos)                /*!< 0x00008000 */

+#define FDCAN_TTIR_IWT            FDCAN_TTIR_IWT_Msk                           /*!<Initialization Watch Trigger              */

+#define FDCAN_TTIR_WT_Pos         (16U)

+#define FDCAN_TTIR_WT_Msk         (0x1UL << FDCAN_TTIR_WT_Pos)                 /*!< 0x00010000 */

+#define FDCAN_TTIR_WT             FDCAN_TTIR_WT_Msk                            /*!<Watch Trigger                             */

+#define FDCAN_TTIR_AW_Pos         (17U)

+#define FDCAN_TTIR_AW_Msk         (0x1UL << FDCAN_TTIR_AW_Pos)                 /*!< 0x00020000 */

+#define FDCAN_TTIR_AW             FDCAN_TTIR_AW_Msk                            /*!<Application Watchdog                      */

+#define FDCAN_TTIR_CER_Pos        (18U)

+#define FDCAN_TTIR_CER_Msk        (0x1UL << FDCAN_TTIR_CER_Pos)                /*!< 0x00040000 */

+#define FDCAN_TTIR_CER            FDCAN_TTIR_CER_Msk                           /*!<Configuration Error                       */

+

+/*****************  Bit definition for FDCAN_TTIE register  ********************/

+#define FDCAN_TTIE_SBCE_Pos       (0U)

+#define FDCAN_TTIE_SBCE_Msk       (0x1UL << FDCAN_TTIE_SBCE_Pos)               /*!< 0x00000001 */

+#define FDCAN_TTIE_SBCE           FDCAN_TTIE_SBCE_Msk                          /*!<Start of Basic Cycle Interrupt Enable             */

+#define FDCAN_TTIE_SMCE_Pos       (1U)

+#define FDCAN_TTIE_SMCE_Msk       (0x1UL << FDCAN_TTIE_SMCE_Pos)               /*!< 0x00000002 */

+#define FDCAN_TTIE_SMCE           FDCAN_TTIE_SMCE_Msk                          /*!<Start of Matrix Cycle Interrupt Enable            */

+#define FDCAN_TTIE_CSME_Pos       (2U)

+#define FDCAN_TTIE_CSME_Msk       (0x1UL << FDCAN_TTIE_CSME_Pos)               /*!< 0x00000004 */

+#define FDCAN_TTIE_CSME           FDCAN_TTIE_CSME_Msk                          /*!<Change of Synchronization Mode Interrupt Enable   */

+#define FDCAN_TTIE_SOGE_Pos       (3U)

+#define FDCAN_TTIE_SOGE_Msk       (0x1UL << FDCAN_TTIE_SOGE_Pos)               /*!< 0x00000008 */

+#define FDCAN_TTIE_SOGE           FDCAN_TTIE_SOGE_Msk                          /*!<Start of Gap Interrupt Enable                     */

+#define FDCAN_TTIE_RTMIE_Pos      (4U)

+#define FDCAN_TTIE_RTMIE_Msk      (0x1UL << FDCAN_TTIE_RTMIE_Pos)              /*!< 0x00000010 */

+#define FDCAN_TTIE_RTMIE          FDCAN_TTIE_RTMIE_Msk                         /*!<Register Time Mark Interrupt Interrupt Enable     */

+#define FDCAN_TTIE_TTMIE_Pos      (5U)

+#define FDCAN_TTIE_TTMIE_Msk      (0x1UL << FDCAN_TTIE_TTMIE_Pos)              /*!< 0x00000020 */

+#define FDCAN_TTIE_TTMIE          FDCAN_TTIE_TTMIE_Msk                         /*!<Trigger Time Mark Event Internal Interrupt Enable */

+#define FDCAN_TTIE_SWEE_Pos       (6U)

+#define FDCAN_TTIE_SWEE_Msk       (0x1UL << FDCAN_TTIE_SWEE_Pos)               /*!< 0x00000040 */

+#define FDCAN_TTIE_SWEE           FDCAN_TTIE_SWEE_Msk                          /*!<Stop Watch Event Interrupt Enable                 */

+#define FDCAN_TTIE_GTWE_Pos       (7U)

+#define FDCAN_TTIE_GTWE_Msk       (0x1UL << FDCAN_TTIE_GTWE_Pos)               /*!< 0x00000080 */

+#define FDCAN_TTIE_GTWE           FDCAN_TTIE_GTWE_Msk                          /*!<Global Time Wrap Interrupt Enable                 */

+#define FDCAN_TTIE_GTDE_Pos       (8U)

+#define FDCAN_TTIE_GTDE_Msk       (0x1UL << FDCAN_TTIE_GTDE_Pos)               /*!< 0x00000100 */

+#define FDCAN_TTIE_GTDE           FDCAN_TTIE_GTDE_Msk                          /*!<Global Time Discontinuity Interrupt Enable        */

+#define FDCAN_TTIE_GTEE_Pos       (9U)

+#define FDCAN_TTIE_GTEE_Msk       (0x1UL << FDCAN_TTIE_GTEE_Pos)               /*!< 0x00000200 */

+#define FDCAN_TTIE_GTEE           FDCAN_TTIE_GTEE_Msk                          /*!<Global Time Error Interrupt Enable                */

+#define FDCAN_TTIE_TXUE_Pos       (10U)

+#define FDCAN_TTIE_TXUE_Msk       (0x1UL << FDCAN_TTIE_TXUE_Pos)               /*!< 0x00000400 */

+#define FDCAN_TTIE_TXUE           FDCAN_TTIE_TXUE_Msk                          /*!<Tx Count Underflow Interrupt Enable               */

+#define FDCAN_TTIE_TXOE_Pos       (11U)

+#define FDCAN_TTIE_TXOE_Msk       (0x1UL << FDCAN_TTIE_TXOE_Pos)               /*!< 0x00000800 */

+#define FDCAN_TTIE_TXOE           FDCAN_TTIE_TXOE_Msk                          /*!<Tx Count Overflow Interrupt Enable                */

+#define FDCAN_TTIE_SE1E_Pos       (12U)

+#define FDCAN_TTIE_SE1E_Msk       (0x1UL << FDCAN_TTIE_SE1E_Pos)               /*!< 0x00001000 */

+#define FDCAN_TTIE_SE1E           FDCAN_TTIE_SE1E_Msk                          /*!<Scheduling Error 1 Interrupt Enable               */

+#define FDCAN_TTIE_SE2E_Pos       (13U)

+#define FDCAN_TTIE_SE2E_Msk       (0x1UL << FDCAN_TTIE_SE2E_Pos)               /*!< 0x00002000 */

+#define FDCAN_TTIE_SE2E           FDCAN_TTIE_SE2E_Msk                          /*!<Scheduling Error 2 Interrupt Enable               */

+#define FDCAN_TTIE_ELCE_Pos       (14U)

+#define FDCAN_TTIE_ELCE_Msk       (0x1UL << FDCAN_TTIE_ELCE_Pos)               /*!< 0x00004000 */

+#define FDCAN_TTIE_ELCE           FDCAN_TTIE_ELCE_Msk                          /*!<Error Level Changed Interrupt Enable              */

+#define FDCAN_TTIE_IWTE_Pos       (15U)

+#define FDCAN_TTIE_IWTE_Msk       (0x1UL << FDCAN_TTIE_IWTE_Pos)               /*!< 0x00008000 */

+#define FDCAN_TTIE_IWTE           FDCAN_TTIE_IWTE_Msk                          /*!<Initialization Watch Trigger Interrupt Enable     */

+#define FDCAN_TTIE_WTE_Pos        (16U)

+#define FDCAN_TTIE_WTE_Msk        (0x1UL << FDCAN_TTIE_WTE_Pos)                /*!< 0x00010000 */

+#define FDCAN_TTIE_WTE            FDCAN_TTIE_WTE_Msk                           /*!<Watch Trigger Interrupt Enable                    */

+#define FDCAN_TTIE_AWE_Pos        (17U)

+#define FDCAN_TTIE_AWE_Msk        (0x1UL << FDCAN_TTIE_AWE_Pos)                /*!< 0x00020000 */

+#define FDCAN_TTIE_AWE            FDCAN_TTIE_AWE_Msk                           /*!<Application Watchdog Interrupt Enable             */

+#define FDCAN_TTIE_CERE_Pos       (18U)

+#define FDCAN_TTIE_CERE_Msk       (0x1UL << FDCAN_TTIE_CERE_Pos)               /*!< 0x00040000 */

+#define FDCAN_TTIE_CERE           FDCAN_TTIE_CERE_Msk                          /*!<Configuration Error Interrupt Enable              */

+

+/*****************  Bit definition for FDCAN_TTILS register  ********************/

+#define FDCAN_TTILS_SBCS_Pos      (0U)

+#define FDCAN_TTILS_SBCS_Msk      (0x1UL << FDCAN_TTILS_SBCS_Pos)              /*!< 0x00000001 */

+#define FDCAN_TTILS_SBCS          FDCAN_TTILS_SBCS_Msk                         /*!<Start of Basic Cycle Interrupt Line               */

+#define FDCAN_TTILS_SMCS_Pos      (1U)

+#define FDCAN_TTILS_SMCS_Msk      (0x1UL << FDCAN_TTILS_SMCS_Pos)              /*!< 0x00000002 */

+#define FDCAN_TTILS_SMCS          FDCAN_TTILS_SMCS_Msk                         /*!<Start of Matrix Cycle Interrupt Line              */

+#define FDCAN_TTILS_CSMS_Pos      (2U)

+#define FDCAN_TTILS_CSMS_Msk      (0x1UL << FDCAN_TTILS_CSMS_Pos)              /*!< 0x00000004 */

+#define FDCAN_TTILS_CSMS          FDCAN_TTILS_CSMS_Msk                         /*!<Change of Synchronization Mode Interrupt Line     */

+#define FDCAN_TTILS_SOGS_Pos      (3U)

+#define FDCAN_TTILS_SOGS_Msk      (0x1UL << FDCAN_TTILS_SOGS_Pos)              /*!< 0x00000008 */

+#define FDCAN_TTILS_SOGS          FDCAN_TTILS_SOGS_Msk                         /*!<Start of Gap Interrupt Line                       */

+#define FDCAN_TTILS_RTMIS_Pos     (4U)

+#define FDCAN_TTILS_RTMIS_Msk     (0x1UL << FDCAN_TTILS_RTMIS_Pos)             /*!< 0x00000010 */

+#define FDCAN_TTILS_RTMIS         FDCAN_TTILS_RTMIS_Msk                        /*!<Register Time Mark Interrupt Interrupt Line       */

+#define FDCAN_TTILS_TTMIS_Pos     (5U)

+#define FDCAN_TTILS_TTMIS_Msk     (0x1UL << FDCAN_TTILS_TTMIS_Pos)             /*!< 0x00000020 */

+#define FDCAN_TTILS_TTMIS         FDCAN_TTILS_TTMIS_Msk                        /*!<Trigger Time Mark Event Internal Interrupt Line   */

+#define FDCAN_TTILS_SWES_Pos      (6U)

+#define FDCAN_TTILS_SWES_Msk      (0x1UL << FDCAN_TTILS_SWES_Pos)              /*!< 0x00000040 */

+#define FDCAN_TTILS_SWES          FDCAN_TTILS_SWES_Msk                         /*!<Stop Watch Event Interrupt Line                   */

+#define FDCAN_TTILS_GTWS_Pos      (7U)

+#define FDCAN_TTILS_GTWS_Msk      (0x1UL << FDCAN_TTILS_GTWS_Pos)              /*!< 0x00000080 */

+#define FDCAN_TTILS_GTWS          FDCAN_TTILS_GTWS_Msk                         /*!<Global Time Wrap Interrupt Line                   */

+#define FDCAN_TTILS_GTDS_Pos      (8U)

+#define FDCAN_TTILS_GTDS_Msk      (0x1UL << FDCAN_TTILS_GTDS_Pos)              /*!< 0x00000100 */

+#define FDCAN_TTILS_GTDS          FDCAN_TTILS_GTDS_Msk                         /*!<Global Time Discontinuity Interrupt Line          */

+#define FDCAN_TTILS_GTES_Pos      (9U)

+#define FDCAN_TTILS_GTES_Msk      (0x1UL << FDCAN_TTILS_GTES_Pos)              /*!< 0x00000200 */

+#define FDCAN_TTILS_GTES          FDCAN_TTILS_GTES_Msk                         /*!<Global Time Error Interrupt Line                  */

+#define FDCAN_TTILS_TXUS_Pos      (10U)

+#define FDCAN_TTILS_TXUS_Msk      (0x1UL << FDCAN_TTILS_TXUS_Pos)              /*!< 0x00000400 */

+#define FDCAN_TTILS_TXUS          FDCAN_TTILS_TXUS_Msk                         /*!<Tx Count Underflow Interrupt Line                 */

+#define FDCAN_TTILS_TXOS_Pos      (11U)

+#define FDCAN_TTILS_TXOS_Msk      (0x1UL << FDCAN_TTILS_TXOS_Pos)              /*!< 0x00000800 */

+#define FDCAN_TTILS_TXOS          FDCAN_TTILS_TXOS_Msk                         /*!<Tx Count Overflow Interrupt Line                  */

+#define FDCAN_TTILS_SE1S_Pos      (12U)

+#define FDCAN_TTILS_SE1S_Msk      (0x1UL << FDCAN_TTILS_SE1S_Pos)              /*!< 0x00001000 */

+#define FDCAN_TTILS_SE1S          FDCAN_TTILS_SE1S_Msk                         /*!<Scheduling Error 1 Interrupt Line                 */

+#define FDCAN_TTILS_SE2S_Pos      (13U)

+#define FDCAN_TTILS_SE2S_Msk      (0x1UL << FDCAN_TTILS_SE2S_Pos)              /*!< 0x00002000 */

+#define FDCAN_TTILS_SE2S          FDCAN_TTILS_SE2S_Msk                         /*!<Scheduling Error 2 Interrupt Line                 */

+#define FDCAN_TTILS_ELCS_Pos      (14U)

+#define FDCAN_TTILS_ELCS_Msk      (0x1UL << FDCAN_TTILS_ELCS_Pos)              /*!< 0x00004000 */

+#define FDCAN_TTILS_ELCS          FDCAN_TTILS_ELCS_Msk                         /*!<Error Level Changed Interrupt Line                */

+#define FDCAN_TTILS_IWTS_Pos      (15U)

+#define FDCAN_TTILS_IWTS_Msk      (0x1UL << FDCAN_TTILS_IWTS_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTILS_IWTS          FDCAN_TTILS_IWTS_Msk                         /*!<Initialization Watch Trigger Interrupt Line       */

+#define FDCAN_TTILS_WTS_Pos       (16U)

+#define FDCAN_TTILS_WTS_Msk       (0x1UL << FDCAN_TTILS_WTS_Pos)               /*!< 0x00010000 */

+#define FDCAN_TTILS_WTS           FDCAN_TTILS_WTS_Msk                          /*!<Watch Trigger Interrupt Line                      */

+#define FDCAN_TTILS_AWS_Pos       (17U)

+#define FDCAN_TTILS_AWS_Msk       (0x1UL << FDCAN_TTILS_AWS_Pos)               /*!< 0x00020000 */

+#define FDCAN_TTILS_AWS           FDCAN_TTILS_AWS_Msk                          /*!<Application Watchdog Interrupt Line               */

+#define FDCAN_TTILS_CERS_Pos      (18U)

+#define FDCAN_TTILS_CERS_Msk      (0x1UL << FDCAN_TTILS_CERS_Pos)              /*!< 0x00040000 */

+#define FDCAN_TTILS_CERS          FDCAN_TTILS_CERS_Msk                         /*!<Configuration Error Interrupt Line                */

+

+/*****************  Bit definition for FDCAN_TTOST register  ********************/

+#define FDCAN_TTOST_EL_Pos        (0U)

+#define FDCAN_TTOST_EL_Msk        (0x3UL << FDCAN_TTOST_EL_Pos)                /*!< 0x00000003 */

+#define FDCAN_TTOST_EL            FDCAN_TTOST_EL_Msk                           /*!<Error Level                              */

+#define FDCAN_TTOST_MS_Pos        (2U)

+#define FDCAN_TTOST_MS_Msk        (0x3UL << FDCAN_TTOST_MS_Pos)                /*!< 0x0000000C */

+#define FDCAN_TTOST_MS            FDCAN_TTOST_MS_Msk                           /*!<Master State                             */

+#define FDCAN_TTOST_SYS_Pos       (4U)

+#define FDCAN_TTOST_SYS_Msk       (0x3UL << FDCAN_TTOST_SYS_Pos)               /*!< 0x00000030 */

+#define FDCAN_TTOST_SYS           FDCAN_TTOST_SYS_Msk                          /*!<Synchronization State                    */

+#define FDCAN_TTOST_QGTP_Pos      (6U)

+#define FDCAN_TTOST_QGTP_Msk      (0x1UL << FDCAN_TTOST_QGTP_Pos)              /*!< 0x00000040 */

+#define FDCAN_TTOST_QGTP          FDCAN_TTOST_QGTP_Msk                         /*!<Quality of Global Time Phase             */

+#define FDCAN_TTOST_QCS_Pos       (7U)

+#define FDCAN_TTOST_QCS_Msk       (0x1UL << FDCAN_TTOST_QCS_Pos)               /*!< 0x00000080 */

+#define FDCAN_TTOST_QCS           FDCAN_TTOST_QCS_Msk                          /*!<Quality of Clock Speed                   */

+#define FDCAN_TTOST_RTO_Pos       (8U)

+#define FDCAN_TTOST_RTO_Msk       (0xFFUL << FDCAN_TTOST_RTO_Pos)              /*!< 0x0000FF00 */

+#define FDCAN_TTOST_RTO           FDCAN_TTOST_RTO_Msk                          /*!<Reference Trigger Offset                 */

+#define FDCAN_TTOST_WGTD_Pos      (22U)

+#define FDCAN_TTOST_WGTD_Msk      (0x1UL << FDCAN_TTOST_WGTD_Pos)              /*!< 0x00400000 */

+#define FDCAN_TTOST_WGTD          FDCAN_TTOST_WGTD_Msk                         /*!<Wait for Global Time Discontinuity       */

+#define FDCAN_TTOST_GFI_Pos       (23U)

+#define FDCAN_TTOST_GFI_Msk       (0x1UL << FDCAN_TTOST_GFI_Pos)               /*!< 0x00800000 */

+#define FDCAN_TTOST_GFI           FDCAN_TTOST_GFI_Msk                          /*!<Gap Finished Indicator                   */

+#define FDCAN_TTOST_TMP_Pos       (24U)

+#define FDCAN_TTOST_TMP_Msk       (0x7UL << FDCAN_TTOST_TMP_Pos)               /*!< 0x07000000 */

+#define FDCAN_TTOST_TMP           FDCAN_TTOST_TMP_Msk                          /*!<Time Master Priority                     */

+#define FDCAN_TTOST_GSI_Pos       (27U)

+#define FDCAN_TTOST_GSI_Msk       (0x1UL << FDCAN_TTOST_GSI_Pos)               /*!< 0x08000000 */

+#define FDCAN_TTOST_GSI           FDCAN_TTOST_GSI_Msk                          /*!<Gap Started Indicator                    */

+#define FDCAN_TTOST_WFE_Pos       (28U)

+#define FDCAN_TTOST_WFE_Msk       (0x1UL << FDCAN_TTOST_WFE_Pos)               /*!< 0x10000000 */

+#define FDCAN_TTOST_WFE           FDCAN_TTOST_WFE_Msk                          /*!<Wait for Event                           */

+#define FDCAN_TTOST_AWE_Pos       (29U)

+#define FDCAN_TTOST_AWE_Msk       (0x1UL << FDCAN_TTOST_AWE_Pos)               /*!< 0x20000000 */

+#define FDCAN_TTOST_AWE           FDCAN_TTOST_AWE_Msk                          /*!<Application Watchdog Event               */

+#define FDCAN_TTOST_WECS_Pos      (30U)

+#define FDCAN_TTOST_WECS_Msk      (0x1UL << FDCAN_TTOST_WECS_Pos)              /*!< 0x40000000 */

+#define FDCAN_TTOST_WECS          FDCAN_TTOST_WECS_Msk                         /*!<Wait for External Clock Synchronization  */

+#define FDCAN_TTOST_SPL_Pos       (31U)

+#define FDCAN_TTOST_SPL_Msk       (0x1UL << FDCAN_TTOST_SPL_Pos)               /*!< 0x80000000 */

+#define FDCAN_TTOST_SPL           FDCAN_TTOST_SPL_Msk                          /*!<Schedule Phase Lock                      */

+

+/*****************  Bit definition for FDCAN_TURNA register  ********************/

+#define FDCAN_TURNA_NAV_Pos       (0U)

+#define FDCAN_TURNA_NAV_Msk       (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)           /*!< 0x0003FFFF */

+#define FDCAN_TURNA_NAV           FDCAN_TURNA_NAV_Msk                          /*!<Numerator Actual Value                   */

+

+/*****************  Bit definition for FDCAN_TTLGT register  ********************/

+#define FDCAN_TTLGT_LT_Pos        (0U)

+#define FDCAN_TTLGT_LT_Msk        (0xFFFFUL << FDCAN_TTLGT_LT_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTLGT_LT            FDCAN_TTLGT_LT_Msk                           /*!<Local Time                               */

+#define FDCAN_TTLGT_GT_Pos        (16U)

+#define FDCAN_TTLGT_GT_Msk        (0xFFFFUL << FDCAN_TTLGT_GT_Pos)             /*!< 0xFFFF0000 */

+#define FDCAN_TTLGT_GT            FDCAN_TTLGT_GT_Msk                           /*!<Global Time                              */

+

+/*****************  Bit definition for FDCAN_TTCTC register  ********************/

+#define FDCAN_TTCTC_CT_Pos        (0U)

+#define FDCAN_TTCTC_CT_Msk        (0xFFFFUL << FDCAN_TTCTC_CT_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTCTC_CT            FDCAN_TTCTC_CT_Msk                           /*!<Cycle Time                               */

+#define FDCAN_TTCTC_CC_Pos        (16U)

+#define FDCAN_TTCTC_CC_Msk        (0x3FUL << FDCAN_TTCTC_CC_Pos)               /*!< 0x003F0000 */

+#define FDCAN_TTCTC_CC            FDCAN_TTCTC_CC_Msk                           /*!<Cycle Count                              */

+

+/*****************  Bit definition for FDCAN_TTCPT register  ********************/

+#define FDCAN_TTCPT_CCV_Pos       (0U)

+#define FDCAN_TTCPT_CCV_Msk       (0x3FUL << FDCAN_TTCPT_CCV_Pos)              /*!< 0x0000003F */

+#define FDCAN_TTCPT_CCV           FDCAN_TTCPT_CCV_Msk                          /*!<Cycle Count Value                        */

+#define FDCAN_TTCPT_SWV_Pos       (16U)

+#define FDCAN_TTCPT_SWV_Msk       (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)            /*!< 0xFFFF0000 */

+#define FDCAN_TTCPT_SWV           FDCAN_TTCPT_SWV_Msk                          /*!<Stop Watch Value                         */

+

+/*****************  Bit definition for FDCAN_TTCSM register  ********************/

+#define FDCAN_TTCSM_CSM_Pos       (0U)

+#define FDCAN_TTCSM_CSM_Msk       (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)            /*!< 0x0000FFFF */

+#define FDCAN_TTCSM_CSM           FDCAN_TTCSM_CSM_Msk                          /*!<Cycle Sync Mark                          */

+

+/*****************  Bit definition for FDCAN_TTTS register  *********************/

+#define FDCAN_TTTS_SWTSEL_Pos     (0U)

+#define FDCAN_TTTS_SWTSEL_Msk     (0x3UL << FDCAN_TTTS_SWTSEL_Pos)             /*!< 0x00000003 */

+#define FDCAN_TTTS_SWTSEL         FDCAN_TTTS_SWTSEL_Msk                        /*!<Stop watch trigger input selection       */

+#define FDCAN_TTTS_EVTSEL_Pos     (4U)

+#define FDCAN_TTTS_EVTSEL_Msk     (0x3UL << FDCAN_TTTS_EVTSEL_Pos)             /*!< 0x00000030 */

+#define FDCAN_TTTS_EVTSEL         FDCAN_TTTS_EVTSEL_Msk                        /*!<Event trigger input selection            */

+

+/********************************************************************************/

+/*                                                                              */

+/*                      FDCANCCU (Clock Calibration unit)                       */

+/*                                                                              */

+/********************************************************************************/

+

+/*****************  Bit definition for FDCANCCU_CREL register  ******************/

+#define FDCANCCU_CREL_DAY_Pos        (0U)

+#define FDCANCCU_CREL_DAY_Msk        (0xFFUL << FDCANCCU_CREL_DAY_Pos)         /*!< 0x000000FF */

+#define FDCANCCU_CREL_DAY            FDCANCCU_CREL_DAY_Msk                     /*!<Timestamp Day                           */

+#define FDCANCCU_CREL_MON_Pos        (8U)

+#define FDCANCCU_CREL_MON_Msk        (0xFFUL << FDCANCCU_CREL_MON_Pos)         /*!< 0x0000FF00 */

+#define FDCANCCU_CREL_MON            FDCANCCU_CREL_MON_Msk                     /*!<Timestamp Month                         */

+#define FDCANCCU_CREL_YEAR_Pos       (16U)

+#define FDCANCCU_CREL_YEAR_Msk       (0xFUL << FDCANCCU_CREL_YEAR_Pos)         /*!< 0x000F0000 */

+#define FDCANCCU_CREL_YEAR           FDCANCCU_CREL_YEAR_Msk                    /*!<Timestamp Year                          */

+#define FDCANCCU_CREL_SUBSTEP_Pos    (20U)

+#define FDCANCCU_CREL_SUBSTEP_Msk    (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)      /*!< 0x00F00000 */

+#define FDCANCCU_CREL_SUBSTEP        FDCANCCU_CREL_SUBSTEP_Msk                 /*!<Sub-step of Core release                */

+#define FDCANCCU_CREL_STEP_Pos       (24U)

+#define FDCANCCU_CREL_STEP_Msk       (0xFUL << FDCANCCU_CREL_STEP_Pos)         /*!< 0x0F000000 */

+#define FDCANCCU_CREL_STEP           FDCANCCU_CREL_STEP_Msk                    /*!<Step of Core release                    */

+#define FDCANCCU_CREL_REL_Pos        (28U)

+#define FDCANCCU_CREL_REL_Msk        (0xFUL << FDCANCCU_CREL_REL_Pos)          /*!< 0xF0000000 */

+#define FDCANCCU_CREL_REL            FDCANCCU_CREL_REL_Msk                     /*!<Core release                            */

+

+/*****************  Bit definition for FDCANCCU_CCFG register  ******************/

+#define FDCANCCU_CCFG_TQBT_Pos       (0U)

+#define FDCANCCU_CCFG_TQBT_Msk       (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)        /*!< 0x0000001F */

+#define FDCANCCU_CCFG_TQBT           FDCANCCU_CCFG_TQBT_Msk                    /*!<Time Quanta per Bit Time                */

+#define FDCANCCU_CCFG_BCC_Pos        (6U)

+#define FDCANCCU_CCFG_BCC_Msk        (0x1UL << FDCANCCU_CCFG_BCC_Pos)          /*!< 0x00000040 */

+#define FDCANCCU_CCFG_BCC            FDCANCCU_CCFG_BCC_Msk                     /*!<Bypass Clock Calibration                */

+#define FDCANCCU_CCFG_CFL_Pos        (7U)

+#define FDCANCCU_CCFG_CFL_Msk        (0x1UL << FDCANCCU_CCFG_CFL_Pos)          /*!< 0x00000080 */

+#define FDCANCCU_CCFG_CFL            FDCANCCU_CCFG_CFL_Msk                     /*!<Calibration Field Length                */

+#define FDCANCCU_CCFG_OCPM_Pos       (8U)

+#define FDCANCCU_CCFG_OCPM_Msk       (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)        /*!< 0x0000FF00 */

+#define FDCANCCU_CCFG_OCPM           FDCANCCU_CCFG_OCPM_Msk                    /*!<Oscillator Clock Periods Minimum        */

+#define FDCANCCU_CCFG_CDIV_Pos       (16U)

+#define FDCANCCU_CCFG_CDIV_Msk       (0xFUL << FDCANCCU_CCFG_CDIV_Pos)         /*!< 0x000F0000 */

+#define FDCANCCU_CCFG_CDIV           FDCANCCU_CCFG_CDIV_Msk                    /*!<Clock Divider                           */

+#define FDCANCCU_CCFG_SWR_Pos        (31U)

+#define FDCANCCU_CCFG_SWR_Msk        (0x1UL << FDCANCCU_CCFG_SWR_Pos)          /*!< 0x80000000 */

+#define FDCANCCU_CCFG_SWR            FDCANCCU_CCFG_SWR_Msk                     /*!<Software Reset                          */

+

+/*****************  Bit definition for FDCANCCU_CSTAT register  *****************/

+#define FDCANCCU_CSTAT_OCPC_Pos      (0U)

+#define FDCANCCU_CSTAT_OCPC_Msk      (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)    /*!< 0x0003FFFF */

+#define FDCANCCU_CSTAT_OCPC          FDCANCCU_CSTAT_OCPC_Msk                   /*!<Oscillator Clock Period Counter        */

+#define FDCANCCU_CSTAT_TQC_Pos       (18U)

+#define FDCANCCU_CSTAT_TQC_Msk       (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)       /*!< 0x1FFC0000 */

+#define FDCANCCU_CSTAT_TQC           FDCANCCU_CSTAT_TQC_Msk                    /*!<Time Quanta Counter                    */

+#define FDCANCCU_CSTAT_CALS_Pos      (30U)

+#define FDCANCCU_CSTAT_CALS_Msk      (0x3UL << FDCANCCU_CSTAT_CALS_Pos)        /*!< 0xC0000000 */

+#define FDCANCCU_CSTAT_CALS          FDCANCCU_CSTAT_CALS_Msk                   /*!<Calibration State                      */

+

+/******************  Bit definition for FDCANCCU_CWD register  ******************/

+#define FDCANCCU_CWD_WDC_Pos         (0U)

+#define FDCANCCU_CWD_WDC_Msk         (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)        /*!< 0x0000FFFF */

+#define FDCANCCU_CWD_WDC             FDCANCCU_CWD_WDC_Msk                      /*!<Watchdog Configuration                 */

+#define FDCANCCU_CWD_WDV_Pos         (16U)

+#define FDCANCCU_CWD_WDV_Msk         (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)        /*!< 0xFFFF0000 */

+#define FDCANCCU_CWD_WDV             FDCANCCU_CWD_WDV_Msk                      /*!<Watchdog Value                         */

+

+/******************  Bit definition for FDCANCCU_IR register  *******************/

+#define FDCANCCU_IR_CWE_Pos          (0U)

+#define FDCANCCU_IR_CWE_Msk          (0x1UL << FDCANCCU_IR_CWE_Pos)            /*!< 0x00000001 */

+#define FDCANCCU_IR_CWE              FDCANCCU_IR_CWE_Msk                       /*!<Calibration Watchdog Event             */

+#define FDCANCCU_IR_CSC_Pos          (1U)

+#define FDCANCCU_IR_CSC_Msk          (0x1UL << FDCANCCU_IR_CSC_Pos)            /*!< 0x00000002 */

+#define FDCANCCU_IR_CSC              FDCANCCU_IR_CSC_Msk                       /*!<Calibration State Changed              */

+

+/******************  Bit definition for FDCANCCU_IE register  *******************/

+#define FDCANCCU_IE_CWEE_Pos         (0U)

+#define FDCANCCU_IE_CWEE_Msk         (0x1UL << FDCANCCU_IE_CWEE_Pos)           /*!< 0x00000001 */

+#define FDCANCCU_IE_CWEE             FDCANCCU_IE_CWEE_Msk                      /*!<Calibration Watchdog Event Enable      */

+#define FDCANCCU_IE_CSCE_Pos         (1U)

+#define FDCANCCU_IE_CSCE_Msk         (0x1UL << FDCANCCU_IE_CSCE_Pos)           /*!< 0x00000002 */

+#define FDCANCCU_IE_CSCE             FDCANCCU_IE_CSCE_Msk                      /*!<Calibration State Changed Enable       */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          HDMI-CEC (CEC)                                    */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for CEC_CR register  *********************/

+#define CEC_CR_CECEN_Pos         (0U)

+#define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                   /*!< 0x00000001 */

+#define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                                */

+#define CEC_CR_TXSOM_Pos         (1U)

+#define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                   /*!< 0x00000002 */

+#define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message                   */

+#define CEC_CR_TXEOM_Pos         (2U)

+#define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                   /*!< 0x00000004 */

+#define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message                     */

+

+/*******************  Bit definition for CEC_CFGR register  *******************/

+#define CEC_CFGR_SFT_Pos         (0U)

+#define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                   /*!< 0x00000007 */

+#define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time                      */

+#define CEC_CFGR_RXTOL_Pos       (3U)

+#define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                 /*!< 0x00000008 */

+#define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                             */

+#define CEC_CFGR_BRESTP_Pos      (4U)

+#define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                /*!< 0x00000010 */

+#define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                               */

+#define CEC_CFGR_BREGEN_Pos      (5U)

+#define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                /*!< 0x00000020 */

+#define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation           */

+#define CEC_CFGR_LBPEGEN_Pos     (6U)

+#define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)               /*!< 0x00000040 */

+#define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error generation      */

+#define CEC_CFGR_SFTOPT_Pos      (8U)

+#define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                /*!< 0x00000100 */

+#define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional             */

+#define CEC_CFGR_BRDNOGEN_Pos    (7U)

+#define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)              /*!< 0x00000080 */

+#define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No error generation         */

+#define CEC_CFGR_OAR_Pos         (16U)

+#define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                /*!< 0x7FFF0000 */

+#define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                           */

+#define CEC_CFGR_LSTN_Pos        (31U)

+#define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                  /*!< 0x80000000 */

+#define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                           */

+

+/*******************  Bit definition for CEC_TXDR register  *******************/

+#define CEC_TXDR_TXD_Pos         (0U)

+#define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                  /*!< 0x000000FF */

+#define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                               */

+

+/*******************  Bit definition for CEC_RXDR register  *******************/

+#define CEC_RXDR_RXD_Pos         (0U)

+#define CEC_RXDR_RXD_Msk         (0xFFUL << CEC_RXDR_RXD_Pos)                  /*!< 0x000000FF */

+#define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                              /*!< CEC Rx Data                               */

+

+/*******************  Bit definition for CEC_ISR register  ********************/

+#define CEC_ISR_RXBR_Pos         (0U)

+#define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                   /*!< 0x00000001 */

+#define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                      */

+#define CEC_ISR_RXEND_Pos        (1U)

+#define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                  /*!< 0x00000002 */

+#define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                      */

+#define CEC_ISR_RXOVR_Pos        (2U)

+#define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                  /*!< 0x00000004 */

+#define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                            */

+#define CEC_ISR_BRE_Pos          (3U)

+#define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                    /*!< 0x00000008 */

+#define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                   */

+#define CEC_ISR_SBPE_Pos         (4U)

+#define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                   /*!< 0x00000010 */

+#define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error             */

+#define CEC_ISR_LBPE_Pos         (5U)

+#define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                   /*!< 0x00000020 */

+#define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error              */

+#define CEC_ISR_RXACKE_Pos       (6U)

+#define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                 /*!< 0x00000040 */

+#define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge                */

+#define CEC_ISR_ARBLST_Pos       (7U)

+#define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                 /*!< 0x00000080 */

+#define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                      */

+#define CEC_ISR_TXBR_Pos         (8U)

+#define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                   /*!< 0x00000100 */

+#define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                       */

+#define CEC_ISR_TXEND_Pos        (9U)

+#define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                  /*!< 0x00000200 */

+#define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                   */

+#define CEC_ISR_TXUDR_Pos        (10U)

+#define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                  /*!< 0x00000400 */

+#define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                    */

+#define CEC_ISR_TXERR_Pos        (11U)

+#define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                  /*!< 0x00000800 */

+#define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                              */

+#define CEC_ISR_TXACKE_Pos       (12U)

+#define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                 /*!< 0x00001000 */

+#define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge                */

+

+/*******************  Bit definition for CEC_IER register  ********************/

+#define CEC_IER_RXBRIE_Pos       (0U)

+#define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                 /*!< 0x00000001 */

+#define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable            */

+#define CEC_IER_RXENDIE_Pos      (1U)

+#define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                /*!< 0x00000002 */

+#define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable            */

+#define CEC_IER_RXOVRIE_Pos      (2U)

+#define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                /*!< 0x00000004 */

+#define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable                  */

+#define CEC_IER_BREIE_Pos        (3U)

+#define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                  /*!< 0x00000008 */

+#define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable         */

+#define CEC_IER_SBPEIE_Pos       (4U)

+#define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                 /*!< 0x00000010 */

+#define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable   */

+#define CEC_IER_LBPEIE_Pos       (5U)

+#define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                 /*!< 0x00000020 */

+#define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable    */

+#define CEC_IER_RXACKEIE_Pos     (6U)

+#define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)               /*!< 0x00000040 */

+#define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable      */

+#define CEC_IER_ARBLSTIE_Pos     (7U)

+#define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)               /*!< 0x00000080 */

+#define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable            */

+#define CEC_IER_TXBRIE_Pos       (8U)

+#define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                 /*!< 0x00000100 */

+#define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable            */

+#define CEC_IER_TXENDIE_Pos      (9U)

+#define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                /*!< 0x00000200 */

+#define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable         */

+#define CEC_IER_TXUDRIE_Pos      (10U)

+#define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                /*!< 0x00000400 */

+#define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable          */

+#define CEC_IER_TXERRIE_Pos      (11U)

+#define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                /*!< 0x00000800 */

+#define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                    */

+#define CEC_IER_TXACKEIE_Pos     (12U)

+#define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)               /*!< 0x00001000 */

+#define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable      */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          CRC calculation unit                              */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for CRC_DR register  *********************/

+#define CRC_DR_DR_Pos            (0U)

+#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */

+#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */

+

+/*******************  Bit definition for CRC_IDR register  ********************/

+#define CRC_IDR_IDR_Pos          (0U)

+#define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */

+#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */

+

+/********************  Bit definition for CRC_CR register  ********************/

+#define CRC_CR_RESET_Pos         (0U)

+#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */

+#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */

+#define CRC_CR_POLYSIZE_Pos      (3U)

+#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */

+#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */

+#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */

+#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */

+#define CRC_CR_REV_IN_Pos        (5U)

+#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */

+#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */

+#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */

+#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */

+#define CRC_CR_REV_OUT_Pos       (7U)

+#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */

+#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */

+

+/*******************  Bit definition for CRC_INIT register  *******************/

+#define CRC_INIT_INIT_Pos        (0U)

+#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */

+#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */

+

+/*******************  Bit definition for CRC_POL register  ********************/

+#define CRC_POL_POL_Pos          (0U)

+#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */

+#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          CRS Clock Recovery System                         */

+/******************************************************************************/

+

+/*******************  Bit definition for CRS_CR register  *********************/

+#define CRS_CR_SYNCOKIE_Pos       (0U)

+#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */

+#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */

+#define CRS_CR_SYNCWARNIE_Pos     (1U)

+#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */

+#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */

+#define CRS_CR_ERRIE_Pos          (2U)

+#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */

+#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */

+#define CRS_CR_ESYNCIE_Pos        (3U)

+#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */

+#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */

+#define CRS_CR_CEN_Pos            (5U)

+#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */

+#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */

+#define CRS_CR_AUTOTRIMEN_Pos     (6U)

+#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */

+#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */

+#define CRS_CR_SWSYNC_Pos         (7U)

+#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */

+#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */

+#define CRS_CR_TRIM_Pos           (8U)

+#define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00003F00 */

+#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */

+

+/*******************  Bit definition for CRS_CFGR register  *********************/

+#define CRS_CFGR_RELOAD_Pos       (0U)

+#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */

+#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */

+#define CRS_CFGR_FELIM_Pos        (16U)

+#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */

+#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */

+

+#define CRS_CFGR_SYNCDIV_Pos      (24U)

+#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */

+#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */

+#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */

+#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */

+#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */

+

+#define CRS_CFGR_SYNCSRC_Pos      (28U)

+#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */

+#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */

+#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */

+#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */

+

+#define CRS_CFGR_SYNCPOL_Pos      (31U)

+#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */

+#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */

+

+/*******************  Bit definition for CRS_ISR register  *********************/

+#define CRS_ISR_SYNCOKF_Pos       (0U)

+#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */

+#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */

+#define CRS_ISR_SYNCWARNF_Pos     (1U)

+#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */

+#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */

+#define CRS_ISR_ERRF_Pos          (2U)

+#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */

+#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */

+#define CRS_ISR_ESYNCF_Pos        (3U)

+#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */

+#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */

+#define CRS_ISR_SYNCERR_Pos       (8U)

+#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */

+#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */

+#define CRS_ISR_SYNCMISS_Pos      (9U)

+#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */

+#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */

+#define CRS_ISR_TRIMOVF_Pos       (10U)

+#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */

+#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */

+#define CRS_ISR_FEDIR_Pos         (15U)

+#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */

+#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */

+#define CRS_ISR_FECAP_Pos         (16U)

+#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */

+#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */

+

+/*******************  Bit definition for CRS_ICR register  *********************/

+#define CRS_ICR_SYNCOKC_Pos       (0U)

+#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */

+#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */

+#define CRS_ICR_SYNCWARNC_Pos     (1U)

+#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */

+#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */

+#define CRS_ICR_ERRC_Pos          (2U)

+#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */

+#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */

+#define CRS_ICR_ESYNCC_Pos        (3U)

+#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */

+#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            Crypto Processor                                */

+/*                                                                            */

+/******************************************************************************/

+/******************* Bits definition for CRYP_CR register  ********************/

+#define CRYP_CR_ALGODIR_Pos              (2U)

+#define CRYP_CR_ALGODIR_Msk              (0x1UL << CRYP_CR_ALGODIR_Pos)        /*!< 0x00000004 */

+#define CRYP_CR_ALGODIR                  CRYP_CR_ALGODIR_Msk

+

+#define CRYP_CR_ALGOMODE_Pos             (3U)

+#define CRYP_CR_ALGOMODE_Msk             (0x10007UL << CRYP_CR_ALGOMODE_Pos)   /*!< 0x00080038 */

+#define CRYP_CR_ALGOMODE                 CRYP_CR_ALGOMODE_Msk

+#define CRYP_CR_ALGOMODE_0               (0x00001UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000008 */

+#define CRYP_CR_ALGOMODE_1               (0x00002UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000010 */

+#define CRYP_CR_ALGOMODE_2               (0x00004UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000020 */

+#define CRYP_CR_ALGOMODE_TDES_ECB        ((uint32_t)0x00000000)

+#define CRYP_CR_ALGOMODE_TDES_CBC_Pos    (3U)

+#define CRYP_CR_ALGOMODE_TDES_CBC_Msk    (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */

+#define CRYP_CR_ALGOMODE_TDES_CBC        CRYP_CR_ALGOMODE_TDES_CBC_Msk

+#define CRYP_CR_ALGOMODE_DES_ECB_Pos     (4U)

+#define CRYP_CR_ALGOMODE_DES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_DES_ECB_Pos) /*!< 0x00000010 */

+#define CRYP_CR_ALGOMODE_DES_ECB         CRYP_CR_ALGOMODE_DES_ECB_Msk

+#define CRYP_CR_ALGOMODE_DES_CBC_Pos     (3U)

+#define CRYP_CR_ALGOMODE_DES_CBC_Msk     (0x3UL << CRYP_CR_ALGOMODE_DES_CBC_Pos) /*!< 0x00000018 */

+#define CRYP_CR_ALGOMODE_DES_CBC         CRYP_CR_ALGOMODE_DES_CBC_Msk

+#define CRYP_CR_ALGOMODE_AES_ECB_Pos     (5U)

+#define CRYP_CR_ALGOMODE_AES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */

+#define CRYP_CR_ALGOMODE_AES_ECB         CRYP_CR_ALGOMODE_AES_ECB_Msk

+#define CRYP_CR_ALGOMODE_AES_CBC_Pos     (3U)

+#define CRYP_CR_ALGOMODE_AES_CBC_Msk     (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */

+#define CRYP_CR_ALGOMODE_AES_CBC         CRYP_CR_ALGOMODE_AES_CBC_Msk

+#define CRYP_CR_ALGOMODE_AES_CTR_Pos     (4U)

+#define CRYP_CR_ALGOMODE_AES_CTR_Msk     (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */

+#define CRYP_CR_ALGOMODE_AES_CTR         CRYP_CR_ALGOMODE_AES_CTR_Msk

+#define CRYP_CR_ALGOMODE_AES_KEY_Pos     (3U)

+#define CRYP_CR_ALGOMODE_AES_KEY_Msk     (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */

+#define CRYP_CR_ALGOMODE_AES_KEY         CRYP_CR_ALGOMODE_AES_KEY_Msk

+#define CRYP_CR_ALGOMODE_AES_GCM_Pos     (19U)

+#define CRYP_CR_ALGOMODE_AES_GCM_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_GCM_Pos) /*!< 0x00080000 */

+#define CRYP_CR_ALGOMODE_AES_GCM         CRYP_CR_ALGOMODE_AES_GCM_Msk

+#define CRYP_CR_ALGOMODE_AES_CCM_Pos     (3U)

+#define CRYP_CR_ALGOMODE_AES_CCM_Msk     (0x10001UL << CRYP_CR_ALGOMODE_AES_CCM_Pos) /*!< 0x00080008 */

+#define CRYP_CR_ALGOMODE_AES_CCM         CRYP_CR_ALGOMODE_AES_CCM_Msk

+

+#define CRYP_CR_DATATYPE_Pos             (6U)

+#define CRYP_CR_DATATYPE_Msk             (0x3UL << CRYP_CR_DATATYPE_Pos)       /*!< 0x000000C0 */

+#define CRYP_CR_DATATYPE                 CRYP_CR_DATATYPE_Msk

+#define CRYP_CR_DATATYPE_0               (0x1UL << CRYP_CR_DATATYPE_Pos)        /*!< 0x00000040 */

+#define CRYP_CR_DATATYPE_1               (0x2UL << CRYP_CR_DATATYPE_Pos)        /*!< 0x00000080 */

+#define CRYP_CR_KEYSIZE_Pos              (8U)

+#define CRYP_CR_KEYSIZE_Msk              (0x3UL << CRYP_CR_KEYSIZE_Pos)        /*!< 0x00000300 */

+#define CRYP_CR_KEYSIZE                  CRYP_CR_KEYSIZE_Msk

+#define CRYP_CR_KEYSIZE_0                (0x1UL << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000100 */

+#define CRYP_CR_KEYSIZE_1                (0x2UL << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000200 */

+#define CRYP_CR_FFLUSH_Pos               (14U)

+#define CRYP_CR_FFLUSH_Msk               (0x1UL << CRYP_CR_FFLUSH_Pos)         /*!< 0x00004000 */

+#define CRYP_CR_FFLUSH                   CRYP_CR_FFLUSH_Msk

+#define CRYP_CR_CRYPEN_Pos               (15U)

+#define CRYP_CR_CRYPEN_Msk               (0x1UL << CRYP_CR_CRYPEN_Pos)         /*!< 0x00008000 */

+#define CRYP_CR_CRYPEN                   CRYP_CR_CRYPEN_Msk

+

+#define CRYP_CR_GCM_CCMPH_Pos            (16U)

+#define CRYP_CR_GCM_CCMPH_Msk            (0x3UL << CRYP_CR_GCM_CCMPH_Pos)      /*!< 0x00030000 */

+#define CRYP_CR_GCM_CCMPH                CRYP_CR_GCM_CCMPH_Msk

+#define CRYP_CR_GCM_CCMPH_0              (0x1UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00010000 */

+#define CRYP_CR_GCM_CCMPH_1              (0x2UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00020000 */

+#define CRYP_CR_ALGOMODE_3               ((uint32_t)0x00080000)

+#define CRYP_CR_NPBLB_Pos                (20U)

+#define CRYP_CR_NPBLB_Msk                (0xFUL << CRYP_CR_NPBLB_Pos)          /*!< 0x00F00000 */

+#define CRYP_CR_NPBLB                    CRYP_CR_NPBLB_Msk

+

+/****************** Bits definition for CRYP_SR register  *********************/

+#define CRYP_SR_IFEM_Pos                 (0U)

+#define CRYP_SR_IFEM_Msk                 (0x1UL << CRYP_SR_IFEM_Pos)           /*!< 0x00000001 */

+#define CRYP_SR_IFEM                     CRYP_SR_IFEM_Msk

+#define CRYP_SR_IFNF_Pos                 (1U)

+#define CRYP_SR_IFNF_Msk                 (0x1UL << CRYP_SR_IFNF_Pos)           /*!< 0x00000002 */

+#define CRYP_SR_IFNF                     CRYP_SR_IFNF_Msk

+#define CRYP_SR_OFNE_Pos                 (2U)

+#define CRYP_SR_OFNE_Msk                 (0x1UL << CRYP_SR_OFNE_Pos)           /*!< 0x00000004 */

+#define CRYP_SR_OFNE                     CRYP_SR_OFNE_Msk

+#define CRYP_SR_OFFU_Pos                 (3U)

+#define CRYP_SR_OFFU_Msk                 (0x1UL << CRYP_SR_OFFU_Pos)           /*!< 0x00000008 */

+#define CRYP_SR_OFFU                     CRYP_SR_OFFU_Msk

+#define CRYP_SR_BUSY_Pos                 (4U)

+#define CRYP_SR_BUSY_Msk                 (0x1UL << CRYP_SR_BUSY_Pos)           /*!< 0x00000010 */

+#define CRYP_SR_BUSY                     CRYP_SR_BUSY_Msk

+/****************** Bits definition for CRYP_DMACR register  ******************/

+#define CRYP_DMACR_DIEN_Pos              (0U)

+#define CRYP_DMACR_DIEN_Msk              (0x1UL << CRYP_DMACR_DIEN_Pos)        /*!< 0x00000001 */

+#define CRYP_DMACR_DIEN                  CRYP_DMACR_DIEN_Msk

+#define CRYP_DMACR_DOEN_Pos              (1U)

+#define CRYP_DMACR_DOEN_Msk              (0x1UL << CRYP_DMACR_DOEN_Pos)        /*!< 0x00000002 */

+#define CRYP_DMACR_DOEN                  CRYP_DMACR_DOEN_Msk

+/*****************  Bits definition for CRYP_IMSCR register  ******************/

+#define CRYP_IMSCR_INIM_Pos              (0U)

+#define CRYP_IMSCR_INIM_Msk              (0x1UL << CRYP_IMSCR_INIM_Pos)        /*!< 0x00000001 */

+#define CRYP_IMSCR_INIM                  CRYP_IMSCR_INIM_Msk

+#define CRYP_IMSCR_OUTIM_Pos             (1U)

+#define CRYP_IMSCR_OUTIM_Msk             (0x1UL << CRYP_IMSCR_OUTIM_Pos)       /*!< 0x00000002 */

+#define CRYP_IMSCR_OUTIM                 CRYP_IMSCR_OUTIM_Msk

+/****************** Bits definition for CRYP_RISR register  *******************/

+#define CRYP_RISR_INRIS_Pos              (0U)

+#define CRYP_RISR_INRIS_Msk              (0x1UL << CRYP_RISR_INRIS_Pos)        /*!< 0x00000001 */

+#define CRYP_RISR_INRIS                  CRYP_RISR_INRIS_Msk

+#define CRYP_RISR_OUTRIS_Pos             (1U)

+#define CRYP_RISR_OUTRIS_Msk             (0x1UL << CRYP_RISR_OUTRIS_Pos)       /*!< 0x00000002 */

+#define CRYP_RISR_OUTRIS                 CRYP_RISR_OUTRIS_Msk

+/****************** Bits definition for CRYP_MISR register  *******************/

+#define CRYP_MISR_INMIS_Pos              (0U)

+#define CRYP_MISR_INMIS_Msk              (0x1UL << CRYP_MISR_INMIS_Pos)        /*!< 0x00000001 */

+#define CRYP_MISR_INMIS                  CRYP_MISR_INMIS_Msk

+#define CRYP_MISR_OUTMIS_Pos             (1U)

+#define CRYP_MISR_OUTMIS_Msk             (0x1UL << CRYP_MISR_OUTMIS_Pos)       /*!< 0x00000002 */

+#define CRYP_MISR_OUTMIS                 CRYP_MISR_OUTMIS_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                      Digital to Analog Converter                           */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for DAC_CR register  ********************/

+#define DAC_CR_EN1_Pos              (0U)

+#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */

+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */

+#define DAC_CR_TEN1_Pos             (1U)

+#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */

+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */

+

+#define DAC_CR_TSEL1_Pos            (2U)

+#define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */

+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */

+#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000004 */

+#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */

+#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */

+#define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */

+

+

+#define DAC_CR_WAVE1_Pos            (6U)

+#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */

+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */

+#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */

+#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */

+

+#define DAC_CR_MAMP1_Pos            (8U)

+#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */

+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */

+#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */

+#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */

+#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */

+#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */

+

+#define DAC_CR_DMAEN1_Pos           (12U)

+#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */

+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */

+#define DAC_CR_DMAUDRIE1_Pos        (13U)

+#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */

+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/

+#define DAC_CR_CEN1_Pos             (14U)

+#define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */

+#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/

+

+#define DAC_CR_EN2_Pos              (16U)

+#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */

+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */

+#define DAC_CR_TEN2_Pos             (17U)

+#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */

+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */

+

+#define DAC_CR_TSEL2_Pos            (18U)

+#define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */

+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */

+#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00040000 */

+#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */

+#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */

+#define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */

+

+

+#define DAC_CR_WAVE2_Pos            (22U)

+#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */

+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */

+#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */

+#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */

+

+#define DAC_CR_MAMP2_Pos            (24U)

+#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */

+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */

+#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */

+#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */

+#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */

+#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */

+

+#define DAC_CR_DMAEN2_Pos           (28U)

+#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */

+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */

+#define DAC_CR_DMAUDRIE2_Pos        (29U)

+#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */

+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/

+#define DAC_CR_CEN2_Pos             (30U)

+#define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */

+#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/

+

+/*****************  Bit definition for DAC_SWTRIGR register  ******************/

+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)

+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */

+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */

+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)

+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */

+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */

+

+/*****************  Bit definition for DAC_DHR12R1 register  ******************/

+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)

+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12L1 register  ******************/

+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)

+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8R1 register  ******************/

+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)

+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12R2 register  ******************/

+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)

+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12L2 register  ******************/

+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)

+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8R2 register  ******************/

+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)

+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12RD register  ******************/

+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)

+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */

+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)

+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */

+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12LD register  ******************/

+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)

+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */

+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)

+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */

+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8RD register  ******************/

+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)

+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */

+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)

+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */

+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */

+

+/*******************  Bit definition for DAC_DOR1 register  *******************/

+#define DAC_DOR1_DACC1DOR_Pos       (0U)

+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */

+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */

+

+/*******************  Bit definition for DAC_DOR2 register  *******************/

+#define DAC_DOR2_DACC2DOR_Pos       (0U)

+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */

+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */

+

+/********************  Bit definition for DAC_SR register  ********************/

+#define DAC_SR_DMAUDR1_Pos          (13U)

+#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */

+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */

+#define DAC_SR_CAL_FLAG1_Pos        (14U)

+#define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */

+#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */

+#define DAC_SR_BWST1_Pos            (15U)

+#define DAC_SR_BWST1_Msk            (0x4001UL << DAC_SR_BWST1_Pos)             /*!< 0x20008000 */

+#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */

+

+#define DAC_SR_DMAUDR2_Pos          (29U)

+#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */

+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */

+#define DAC_SR_CAL_FLAG2_Pos        (30U)

+#define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */

+#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */

+#define DAC_SR_BWST2_Pos            (31U)

+#define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */

+#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */

+

+/*******************  Bit definition for DAC_CCR register  ********************/

+#define DAC_CCR_OTRIM1_Pos          (0U)

+#define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */

+#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */

+#define DAC_CCR_OTRIM2_Pos          (16U)

+#define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */

+#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */

+

+/*******************  Bit definition for DAC_MCR register  *******************/

+#define DAC_MCR_MODE1_Pos           (0U)

+#define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */

+#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */

+#define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */

+#define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */

+#define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */

+

+#define DAC_MCR_MODE2_Pos           (16U)

+#define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */

+#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */

+#define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */

+#define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */

+#define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */

+

+/******************  Bit definition for DAC_SHSR1 register  ******************/

+#define DAC_SHSR1_TSAMPLE1_Pos      (0U)

+#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */

+#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */

+

+/******************  Bit definition for DAC_SHSR2 register  ******************/

+#define DAC_SHSR2_TSAMPLE2_Pos      (0U)

+#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */

+#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */

+

+/******************  Bit definition for DAC_SHHR register  ******************/

+#define DAC_SHHR_THOLD1_Pos         (0U)

+#define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */

+#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */

+#define DAC_SHHR_THOLD2_Pos         (16U)

+#define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */

+#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */

+

+/******************  Bit definition for DAC_SHRR register  ******************/

+#define DAC_SHRR_TREFRESH1_Pos      (0U)

+#define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */

+#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */

+#define DAC_SHRR_TREFRESH2_Pos      (16U)

+#define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */

+#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    DCMI                                    */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DCMI_CR register  ******************/

+#define DCMI_CR_CAPTURE_Pos        (0U)

+#define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)              /*!< 0x00000001 */

+#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk

+#define DCMI_CR_CM_Pos             (1U)

+#define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                   /*!< 0x00000002 */

+#define DCMI_CR_CM                 DCMI_CR_CM_Msk

+#define DCMI_CR_CROP_Pos           (2U)

+#define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                 /*!< 0x00000004 */

+#define DCMI_CR_CROP               DCMI_CR_CROP_Msk

+#define DCMI_CR_JPEG_Pos           (3U)

+#define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                 /*!< 0x00000008 */

+#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk

+#define DCMI_CR_ESS_Pos            (4U)

+#define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                  /*!< 0x00000010 */

+#define DCMI_CR_ESS                DCMI_CR_ESS_Msk

+#define DCMI_CR_PCKPOL_Pos         (5U)

+#define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)               /*!< 0x00000020 */

+#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk

+#define DCMI_CR_HSPOL_Pos          (6U)

+#define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                /*!< 0x00000040 */

+#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk

+#define DCMI_CR_VSPOL_Pos          (7U)

+#define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */

+#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk

+#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)

+#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)

+#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)

+#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)

+#define DCMI_CR_CRE_Pos            (12U)

+#define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */

+#define DCMI_CR_CRE                DCMI_CR_CRE_Msk

+#define DCMI_CR_ENABLE_Pos         (14U)

+#define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)               /*!< 0x00004000 */

+#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk

+#define DCMI_CR_BSM_Pos            (16U)

+#define DCMI_CR_BSM_Msk            (0x3UL << DCMI_CR_BSM_Pos)                  /*!< 0x00030000 */

+#define DCMI_CR_BSM                DCMI_CR_BSM_Msk

+#define DCMI_CR_BSM_0              (0x1UL << DCMI_CR_BSM_Pos)                   /*!< 0x00010000 */

+#define DCMI_CR_BSM_1              (0x2UL << DCMI_CR_BSM_Pos)                   /*!< 0x00020000 */

+#define DCMI_CR_OEBS_Pos           (18U)

+#define DCMI_CR_OEBS_Msk           (0x1UL << DCMI_CR_OEBS_Pos)                 /*!< 0x00040000 */

+#define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk

+#define DCMI_CR_LSM_Pos            (19U)

+#define DCMI_CR_LSM_Msk            (0x1UL << DCMI_CR_LSM_Pos)                  /*!< 0x00080000 */

+#define DCMI_CR_LSM                DCMI_CR_LSM_Msk

+#define DCMI_CR_OELS_Pos           (20U)

+#define DCMI_CR_OELS_Msk           (0x1UL << DCMI_CR_OELS_Pos)                 /*!< 0x00100000 */

+#define DCMI_CR_OELS               DCMI_CR_OELS_Msk

+

+/********************  Bits definition for DCMI_SR register  ******************/

+#define DCMI_SR_HSYNC_Pos          (0U)

+#define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                /*!< 0x00000001 */

+#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk

+#define DCMI_SR_VSYNC_Pos          (1U)

+#define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                /*!< 0x00000002 */

+#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk

+#define DCMI_SR_FNE_Pos            (2U)

+#define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                  /*!< 0x00000004 */

+#define DCMI_SR_FNE                DCMI_SR_FNE_Msk

+

+/********************  Bits definition for DCMI_RIS register   ****************/

+#define DCMI_RIS_FRAME_RIS_Pos     (0U)

+#define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)           /*!< 0x00000001 */

+#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk

+#define DCMI_RIS_OVR_RIS_Pos       (1U)

+#define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)             /*!< 0x00000002 */

+#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk

+#define DCMI_RIS_ERR_RIS_Pos       (2U)

+#define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)             /*!< 0x00000004 */

+#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk

+#define DCMI_RIS_VSYNC_RIS_Pos     (3U)

+#define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)           /*!< 0x00000008 */

+#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk

+#define DCMI_RIS_LINE_RIS_Pos      (4U)

+#define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)            /*!< 0x00000010 */

+#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk

+

+/********************  Bits definition for DCMI_IER register  *****************/

+#define DCMI_IER_FRAME_IE_Pos      (0U)

+#define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)            /*!< 0x00000001 */

+#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk

+#define DCMI_IER_OVR_IE_Pos        (1U)

+#define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)              /*!< 0x00000002 */

+#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk

+#define DCMI_IER_ERR_IE_Pos        (2U)

+#define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)              /*!< 0x00000004 */

+#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk

+#define DCMI_IER_VSYNC_IE_Pos      (3U)

+#define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)            /*!< 0x00000008 */

+#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk

+#define DCMI_IER_LINE_IE_Pos       (4U)

+#define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)             /*!< 0x00000010 */

+#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk

+

+

+/********************  Bits definition for DCMI_MIS register  *****************/

+#define DCMI_MIS_FRAME_MIS_Pos     (0U)

+#define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)           /*!< 0x00000001 */

+#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk

+#define DCMI_MIS_OVR_MIS_Pos       (1U)

+#define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)             /*!< 0x00000002 */

+#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk

+#define DCMI_MIS_ERR_MIS_Pos       (2U)

+#define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)             /*!< 0x00000004 */

+#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk

+#define DCMI_MIS_VSYNC_MIS_Pos     (3U)

+#define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)           /*!< 0x00000008 */

+#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk

+#define DCMI_MIS_LINE_MIS_Pos      (4U)

+#define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)            /*!< 0x00000010 */

+#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk

+

+

+/********************  Bits definition for DCMI_ICR register  *****************/

+#define DCMI_ICR_FRAME_ISC_Pos     (0U)

+#define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)           /*!< 0x00000001 */

+#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk

+#define DCMI_ICR_OVR_ISC_Pos       (1U)

+#define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)             /*!< 0x00000002 */

+#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk

+#define DCMI_ICR_ERR_ISC_Pos       (2U)

+#define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)             /*!< 0x00000004 */

+#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk

+#define DCMI_ICR_VSYNC_ISC_Pos     (3U)

+#define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)           /*!< 0x00000008 */

+#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk

+#define DCMI_ICR_LINE_ISC_Pos      (4U)

+#define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)            /*!< 0x00000010 */

+#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk

+

+

+/********************  Bits definition for DCMI_ESCR register  ******************/

+#define DCMI_ESCR_FSC_Pos          (0U)

+#define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)               /*!< 0x000000FF */

+#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk

+#define DCMI_ESCR_LSC_Pos          (8U)

+#define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)               /*!< 0x0000FF00 */

+#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk

+#define DCMI_ESCR_LEC_Pos          (16U)

+#define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)               /*!< 0x00FF0000 */

+#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk

+#define DCMI_ESCR_FEC_Pos          (24U)

+#define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)               /*!< 0xFF000000 */

+#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk

+

+/********************  Bits definition for DCMI_ESUR register  ******************/

+#define DCMI_ESUR_FSU_Pos          (0U)

+#define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)               /*!< 0x000000FF */

+#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk

+#define DCMI_ESUR_LSU_Pos          (8U)

+#define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)               /*!< 0x0000FF00 */

+#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk

+#define DCMI_ESUR_LEU_Pos          (16U)

+#define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)               /*!< 0x00FF0000 */

+#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk

+#define DCMI_ESUR_FEU_Pos          (24U)

+#define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)               /*!< 0xFF000000 */

+#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk

+

+/********************  Bits definition for DCMI_CWSTRT register  ******************/

+#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)

+#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)       /*!< 0x00003FFF */

+#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk

+#define DCMI_CWSTRT_VST_Pos        (16U)

+#define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)           /*!< 0x1FFF0000 */

+#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk

+

+/********************  Bits definition for DCMI_CWSIZE register  ******************/

+#define DCMI_CWSIZE_CAPCNT_Pos     (0U)

+#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)        /*!< 0x00003FFF */

+#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk

+#define DCMI_CWSIZE_VLINE_Pos      (16U)

+#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)         /*!< 0x3FFF0000 */

+#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk

+

+/********************  Bits definition for DCMI_DR register  ******************/

+#define DCMI_DR_BYTE0_Pos          (0U)

+#define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)               /*!< 0x000000FF */

+#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk

+#define DCMI_DR_BYTE1_Pos          (8U)

+#define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)               /*!< 0x0000FF00 */

+#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk

+#define DCMI_DR_BYTE2_Pos          (16U)

+#define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)               /*!< 0x00FF0000 */

+#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk

+#define DCMI_DR_BYTE3_Pos          (24U)

+#define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)               /*!< 0xFF000000 */

+#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                 Digital Filter for Sigma Delta Modulators                  */

+/*                                                                            */

+/******************************************************************************/

+

+/****************   DFSDM channel configuration registers  ********************/

+

+/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/

+#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)

+#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)   /*!< 0x80000000 */

+#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */

+#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)

+#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)  /*!< 0x40000000 */

+#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */

+#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)

+#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */

+#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */

+#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)

+#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x0000C000 */

+#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */

+#define DFSDM_CHCFGR1_DATPACK_1         (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */

+#define DFSDM_CHCFGR1_DATPACK_0         (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */

+#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)

+#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00003000 */

+#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */

+#define DFSDM_CHCFGR1_DATMPX_1          (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */

+#define DFSDM_CHCFGR1_DATMPX_0          (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */

+#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)

+#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)   /*!< 0x00000100 */

+#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */

+#define DFSDM_CHCFGR1_CHEN_Pos          (7U)

+#define DFSDM_CHCFGR1_CHEN_Msk          (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)      /*!< 0x00000080 */

+#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */

+#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)

+#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)    /*!< 0x00000040 */

+#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */

+#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)

+#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)     /*!< 0x00000020 */

+#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */

+#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)

+#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x0000000C */

+#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */

+#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */

+#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */

+#define DFSDM_CHCFGR1_SITP_Pos          (0U)

+#define DFSDM_CHCFGR1_SITP_Msk          (0x3UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000003 */

+#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */

+#define DFSDM_CHCFGR1_SITP_1            (0x2UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */

+#define DFSDM_CHCFGR1_SITP_0            (0x1UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */

+

+/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/

+#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)

+#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */

+#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)

+#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)    /*!< 0x000000F8 */

+#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */

+

+/******************  Bit definition for DFSDM_CHAWSCDR register *****************/

+#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)

+#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00C00000 */

+#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */

+#define DFSDM_CHAWSCDR_AWFORD_1         (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */

+#define DFSDM_CHAWSCDR_AWFORD_0         (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */

+#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)

+#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)  /*!< 0x001F0000 */

+#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */

+#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)

+#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)    /*!< 0x0000F000 */

+#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */

+#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)

+#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)    /*!< 0x000000FF */

+#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */

+

+/****************  Bit definition for DFSDM_CHWDATR register *******************/

+#define DFSDM_CHWDATR_WDATA_Pos         (0U)

+#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)  /*!< 0x0000FFFF */

+#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */

+

+/****************  Bit definition for DFSDM_CHDATINR register *****************/

+#define DFSDM_CHDATINR_INDAT0_Pos       (0U)

+#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */

+#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */

+#define DFSDM_CHDATINR_INDAT1_Pos       (16U)

+#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */

+#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */

+

+/************************   DFSDM module registers  ****************************/

+

+/********************  Bit definition for DFSDM_FLTCR1 register *******************/

+#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)

+#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)     /*!< 0x40000000 */

+#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */

+#define DFSDM_FLTCR1_FAST_Pos           (29U)

+#define DFSDM_FLTCR1_FAST_Msk           (0x1UL << DFSDM_FLTCR1_FAST_Pos)       /*!< 0x20000000 */

+#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */

+#define DFSDM_FLTCR1_RCH_Pos            (24U)

+#define DFSDM_FLTCR1_RCH_Msk            (0x7UL << DFSDM_FLTCR1_RCH_Pos)        /*!< 0x07000000 */

+#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */

+#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)

+#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)     /*!< 0x00200000 */

+#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */

+#define DFSDM_FLTCR1_RSYNC_Pos          (19U)

+#define DFSDM_FLTCR1_RSYNC_Msk          (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)      /*!< 0x00080000 */

+#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */

+#define DFSDM_FLTCR1_RCONT_Pos          (18U)

+#define DFSDM_FLTCR1_RCONT_Msk          (0x1UL << DFSDM_FLTCR1_RCONT_Pos)      /*!< 0x00040000 */

+#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */

+#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)

+#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)   /*!< 0x00020000 */

+#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */

+#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)

+#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00006000 */

+#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */

+#define DFSDM_FLTCR1_JEXTEN_1           (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */

+#define DFSDM_FLTCR1_JEXTEN_0           (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */

+#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)

+#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)   /*!< 0x00001F00 */

+#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */

+#define DFSDM_FLTCR1_JEXTSEL_0          (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000100 */

+#define DFSDM_FLTCR1_JEXTSEL_1          (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000200 */

+#define DFSDM_FLTCR1_JEXTSEL_2          (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000400 */

+#define DFSDM_FLTCR1_JEXTSEL_3          (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000800 */

+#define DFSDM_FLTCR1_JEXTSEL_4          (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00001000 */

+

+#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)

+#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)     /*!< 0x00000020 */

+#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */

+#define DFSDM_FLTCR1_JSCAN_Pos          (4U)

+#define DFSDM_FLTCR1_JSCAN_Msk          (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)      /*!< 0x00000010 */

+#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */

+#define DFSDM_FLTCR1_JSYNC_Pos          (3U)

+#define DFSDM_FLTCR1_JSYNC_Msk          (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)      /*!< 0x00000008 */

+#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */

+#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)

+#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)   /*!< 0x00000002 */

+#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */

+#define DFSDM_FLTCR1_DFEN_Pos           (0U)

+#define DFSDM_FLTCR1_DFEN_Msk           (0x1UL << DFSDM_FLTCR1_DFEN_Pos)       /*!< 0x00000001 */

+#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */

+

+/********************  Bit definition for DFSDM_FLTCR2 register *******************/

+#define DFSDM_FLTCR2_AWDCH_Pos          (16U)

+#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)     /*!< 0x00FF0000 */

+#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */

+#define DFSDM_FLTCR2_EXCH_Pos           (8U)

+#define DFSDM_FLTCR2_EXCH_Msk           (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)      /*!< 0x0000FF00 */

+#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */

+#define DFSDM_FLTCR2_CKABIE_Pos         (6U)

+#define DFSDM_FLTCR2_CKABIE_Msk         (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)     /*!< 0x00000040 */

+#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */

+#define DFSDM_FLTCR2_SCDIE_Pos          (5U)

+#define DFSDM_FLTCR2_SCDIE_Msk          (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)      /*!< 0x00000020 */

+#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */

+#define DFSDM_FLTCR2_AWDIE_Pos          (4U)

+#define DFSDM_FLTCR2_AWDIE_Msk          (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)      /*!< 0x00000010 */

+#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */

+#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)

+#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)     /*!< 0x00000008 */

+#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */

+#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)

+#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)     /*!< 0x00000004 */

+#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */

+#define DFSDM_FLTCR2_REOCIE_Pos         (1U)

+#define DFSDM_FLTCR2_REOCIE_Msk         (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)     /*!< 0x00000002 */

+#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */

+#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)

+#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)     /*!< 0x00000001 */

+#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */

+

+/********************  Bit definition for DFSDM_FLTISR register *******************/

+#define DFSDM_FLTISR_SCDF_Pos           (24U)

+#define DFSDM_FLTISR_SCDF_Msk           (0xFFUL << DFSDM_FLTISR_SCDF_Pos)      /*!< 0xFF000000 */

+#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */

+#define DFSDM_FLTISR_CKABF_Pos          (16U)

+#define DFSDM_FLTISR_CKABF_Msk          (0xFFUL << DFSDM_FLTISR_CKABF_Pos)     /*!< 0x00FF0000 */

+#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */

+#define DFSDM_FLTISR_RCIP_Pos           (14U)

+#define DFSDM_FLTISR_RCIP_Msk           (0x1UL << DFSDM_FLTISR_RCIP_Pos)       /*!< 0x00004000 */

+#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */

+#define DFSDM_FLTISR_JCIP_Pos           (13U)

+#define DFSDM_FLTISR_JCIP_Msk           (0x1UL << DFSDM_FLTISR_JCIP_Pos)       /*!< 0x00002000 */

+#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */

+#define DFSDM_FLTISR_AWDF_Pos           (4U)

+#define DFSDM_FLTISR_AWDF_Msk           (0x1UL << DFSDM_FLTISR_AWDF_Pos)       /*!< 0x00000010 */

+#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */

+#define DFSDM_FLTISR_ROVRF_Pos          (3U)

+#define DFSDM_FLTISR_ROVRF_Msk          (0x1UL << DFSDM_FLTISR_ROVRF_Pos)      /*!< 0x00000008 */

+#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */

+#define DFSDM_FLTISR_JOVRF_Pos          (2U)

+#define DFSDM_FLTISR_JOVRF_Msk          (0x1UL << DFSDM_FLTISR_JOVRF_Pos)      /*!< 0x00000004 */

+#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */

+#define DFSDM_FLTISR_REOCF_Pos          (1U)

+#define DFSDM_FLTISR_REOCF_Msk          (0x1UL << DFSDM_FLTISR_REOCF_Pos)      /*!< 0x00000002 */

+#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */

+#define DFSDM_FLTISR_JEOCF_Pos          (0U)

+#define DFSDM_FLTISR_JEOCF_Msk          (0x1UL << DFSDM_FLTISR_JEOCF_Pos)      /*!< 0x00000001 */

+#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */

+

+/********************  Bit definition for DFSDM_FLTICR register *******************/

+#define DFSDM_FLTICR_CLRSCDF_Pos        (24U)

+#define DFSDM_FLTICR_CLRSCDF_Msk        (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)   /*!< 0xFF000000 */

+#define DFSDM_FLTICR_CLRSCDF            DFSDM_FLTICR_CLRSCDF_Msk               /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */

+#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)

+#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)  /*!< 0x00FF0000 */

+#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */

+#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)

+#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)   /*!< 0x00000008 */

+#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */

+#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)

+#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)   /*!< 0x00000004 */

+#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */

+

+/*******************  Bit definition for DFSDM_FLTJCHGR register ******************/

+#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)

+#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)    /*!< 0x000000FF */

+#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */

+

+/********************  Bit definition for DFSDM_FLTFCR register *******************/

+#define DFSDM_FLTFCR_FORD_Pos           (29U)

+#define DFSDM_FLTFCR_FORD_Msk           (0x7UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0xE0000000 */

+#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */

+#define DFSDM_FLTFCR_FORD_2             (0x4UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */

+#define DFSDM_FLTFCR_FORD_1             (0x2UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */

+#define DFSDM_FLTFCR_FORD_0             (0x1UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */

+#define DFSDM_FLTFCR_FOSR_Pos           (16U)

+#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)     /*!< 0x03FF0000 */

+#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */

+#define DFSDM_FLTFCR_IOSR_Pos           (0U)

+#define DFSDM_FLTFCR_IOSR_Msk           (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)      /*!< 0x000000FF */

+#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */

+

+/******************  Bit definition for DFSDM_FLTJDATAR register *****************/

+#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)

+#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */

+#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)

+#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */

+#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */

+

+/******************  Bit definition for DFSDM_FLTRDATAR register *****************/

+#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)

+#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */

+#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)

+#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)   /*!< 0x00000010 */

+#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */

+#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)

+#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */

+#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */

+

+/******************  Bit definition for DFSDM_FLTAWHTR register ******************/

+#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)

+#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */

+#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)

+#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)    /*!< 0x0000000F */

+#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */

+

+/******************  Bit definition for DFSDM_FLTAWLTR register ******************/

+#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)

+#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWHT[23:0] Analog watchdog low threshold */

+#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)

+#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)    /*!< 0x0000000F */

+#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */

+

+/******************  Bit definition for DFSDM_FLTAWSR register ******************/

+#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)

+#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)    /*!< 0x0000FF00 */

+#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */

+#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)

+#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)    /*!< 0x000000FF */

+#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */

+

+/******************  Bit definition for DFSDM_FLTAWCFR) register *****************/

+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)

+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */

+#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */

+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)

+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */

+#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */

+

+/******************  Bit definition for DFSDM_FLTEXMAX register ******************/

+#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)

+#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */

+#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)

+#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)  /*!< 0x00000007 */

+#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */

+

+/******************  Bit definition for DFSDM_FLTEXMIN register ******************/

+#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)

+#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */

+#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)

+#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)  /*!< 0x00000007 */

+#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */

+

+/******************  Bit definition for DFSDM_FLTCNVTIMR register ******************/

+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)

+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */

+#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           BDMA Controller                                  */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for BDMA_ISR register  ********************/

+#define BDMA_ISR_GIF0_Pos       (0U)

+#define BDMA_ISR_GIF0_Msk       (0x1UL << BDMA_ISR_GIF0_Pos)                   /*!< 0x00000001 */

+#define BDMA_ISR_GIF0           BDMA_ISR_GIF0_Msk                              /*!< Channel 0 Global interrupt flag */

+#define BDMA_ISR_TCIF0_Pos      (1U)

+#define BDMA_ISR_TCIF0_Msk      (0x1UL << BDMA_ISR_TCIF0_Pos)                  /*!< 0x00000002 */

+#define BDMA_ISR_TCIF0          BDMA_ISR_TCIF0_Msk                             /*!< Channel 0 Transfer Complete flag */

+#define BDMA_ISR_HTIF0_Pos      (2U)

+#define BDMA_ISR_HTIF0_Msk      (0x1UL << BDMA_ISR_HTIF0_Pos)                  /*!< 0x00000004 */

+#define BDMA_ISR_HTIF0          BDMA_ISR_HTIF0_Msk                             /*!< Channel 0 Half Transfer flag */

+#define BDMA_ISR_TEIF0_Pos      (3U)

+#define BDMA_ISR_TEIF0_Msk      (0x1UL << BDMA_ISR_TEIF0_Pos)                  /*!< 0x00000008 */

+#define BDMA_ISR_TEIF0          BDMA_ISR_TEIF0_Msk                             /*!< Channel 0 Transfer Error flag */

+#define BDMA_ISR_GIF1_Pos       (4U)

+#define BDMA_ISR_GIF1_Msk       (0x1UL << BDMA_ISR_GIF1_Pos)                   /*!< 0x00000010 */

+#define BDMA_ISR_GIF1           BDMA_ISR_GIF1_Msk                              /*!< Channel 1 Global interrupt flag */

+#define BDMA_ISR_TCIF1_Pos      (5U)

+#define BDMA_ISR_TCIF1_Msk      (0x1UL << BDMA_ISR_TCIF1_Pos)                  /*!< 0x00000020 */

+#define BDMA_ISR_TCIF1          BDMA_ISR_TCIF1_Msk                             /*!< Channel 1 Transfer Complete flag */

+#define BDMA_ISR_HTIF1_Pos      (6U)

+#define BDMA_ISR_HTIF1_Msk      (0x1UL << BDMA_ISR_HTIF1_Pos)                  /*!< 0x00000040 */

+#define BDMA_ISR_HTIF1          BDMA_ISR_HTIF1_Msk                             /*!< Channel 1 Half Transfer flag */

+#define BDMA_ISR_TEIF1_Pos      (7U)

+#define BDMA_ISR_TEIF1_Msk      (0x1UL << BDMA_ISR_TEIF1_Pos)                  /*!< 0x00000080 */

+#define BDMA_ISR_TEIF1          BDMA_ISR_TEIF1_Msk                             /*!< Channel 1 Transfer Error flag */

+#define BDMA_ISR_GIF2_Pos       (8U)

+#define BDMA_ISR_GIF2_Msk       (0x1UL << BDMA_ISR_GIF2_Pos)                   /*!< 0x00000100 */

+#define BDMA_ISR_GIF2           BDMA_ISR_GIF2_Msk                              /*!< Channel 2 Global interrupt flag */

+#define BDMA_ISR_TCIF2_Pos      (9U)

+#define BDMA_ISR_TCIF2_Msk      (0x1UL << BDMA_ISR_TCIF2_Pos)                  /*!< 0x00000200 */

+#define BDMA_ISR_TCIF2          BDMA_ISR_TCIF2_Msk                             /*!< Channel 2 Transfer Complete flag */

+#define BDMA_ISR_HTIF2_Pos      (10U)

+#define BDMA_ISR_HTIF2_Msk      (0x1UL << BDMA_ISR_HTIF2_Pos)                  /*!< 0x00000400 */

+#define BDMA_ISR_HTIF2          BDMA_ISR_HTIF2_Msk                             /*!< Channel 2 Half Transfer flag */

+#define BDMA_ISR_TEIF2_Pos      (11U)

+#define BDMA_ISR_TEIF2_Msk      (0x1UL << BDMA_ISR_TEIF2_Pos)                  /*!< 0x00000800 */

+#define BDMA_ISR_TEIF2          BDMA_ISR_TEIF2_Msk                             /*!< Channel 2 Transfer Error flag */

+#define BDMA_ISR_GIF3_Pos       (12U)

+#define BDMA_ISR_GIF3_Msk       (0x1UL << BDMA_ISR_GIF3_Pos)                   /*!< 0x00001000 */

+#define BDMA_ISR_GIF3           BDMA_ISR_GIF3_Msk                              /*!< Channel 3 Global interrupt flag */

+#define BDMA_ISR_TCIF3_Pos      (13U)

+#define BDMA_ISR_TCIF3_Msk      (0x1UL << BDMA_ISR_TCIF3_Pos)                  /*!< 0x00002000 */

+#define BDMA_ISR_TCIF3          BDMA_ISR_TCIF3_Msk                             /*!< Channel 3 Transfer Complete flag */

+#define BDMA_ISR_HTIF3_Pos      (14U)

+#define BDMA_ISR_HTIF3_Msk      (0x1UL << BDMA_ISR_HTIF3_Pos)                  /*!< 0x00004000 */

+#define BDMA_ISR_HTIF3          BDMA_ISR_HTIF3_Msk                             /*!< Channel 3 Half Transfer flag */

+#define BDMA_ISR_TEIF3_Pos      (15U)

+#define BDMA_ISR_TEIF3_Msk      (0x1UL << BDMA_ISR_TEIF3_Pos)                  /*!< 0x00008000 */

+#define BDMA_ISR_TEIF3          BDMA_ISR_TEIF3_Msk                             /*!< Channel 3 Transfer Error flag */

+#define BDMA_ISR_GIF4_Pos       (16U)

+#define BDMA_ISR_GIF4_Msk       (0x1UL << BDMA_ISR_GIF4_Pos)                   /*!< 0x00010000 */

+#define BDMA_ISR_GIF4           BDMA_ISR_GIF4_Msk                              /*!< Channel 4 Global interrupt flag */

+#define BDMA_ISR_TCIF4_Pos      (17U)

+#define BDMA_ISR_TCIF4_Msk      (0x1UL << BDMA_ISR_TCIF4_Pos)                  /*!< 0x00020000 */

+#define BDMA_ISR_TCIF4          BDMA_ISR_TCIF4_Msk                             /*!< Channel 4 Transfer Complete flag */

+#define BDMA_ISR_HTIF4_Pos      (18U)

+#define BDMA_ISR_HTIF4_Msk      (0x1UL << BDMA_ISR_HTIF4_Pos)                  /*!< 0x00040000 */

+#define BDMA_ISR_HTIF4          BDMA_ISR_HTIF4_Msk                             /*!< Channel 4 Half Transfer flag */

+#define BDMA_ISR_TEIF4_Pos      (19U)

+#define BDMA_ISR_TEIF4_Msk      (0x1UL << BDMA_ISR_TEIF4_Pos)                  /*!< 0x00080000 */

+#define BDMA_ISR_TEIF4          BDMA_ISR_TEIF4_Msk                             /*!< Channel 4 Transfer Error flag */

+#define BDMA_ISR_GIF5_Pos       (20U)

+#define BDMA_ISR_GIF5_Msk       (0x1UL << BDMA_ISR_GIF5_Pos)                   /*!< 0x00100000 */

+#define BDMA_ISR_GIF5           BDMA_ISR_GIF5_Msk                              /*!< Channel 5 Global interrupt flag */

+#define BDMA_ISR_TCIF5_Pos      (21U)

+#define BDMA_ISR_TCIF5_Msk      (0x1UL << BDMA_ISR_TCIF5_Pos)                  /*!< 0x00200000 */

+#define BDMA_ISR_TCIF5          BDMA_ISR_TCIF5_Msk                             /*!< Channel 5 Transfer Complete flag */

+#define BDMA_ISR_HTIF5_Pos      (22U)

+#define BDMA_ISR_HTIF5_Msk      (0x1UL << BDMA_ISR_HTIF5_Pos)                  /*!< 0x00400000 */

+#define BDMA_ISR_HTIF5          BDMA_ISR_HTIF5_Msk                             /*!< Channel 5 Half Transfer flag */

+#define BDMA_ISR_TEIF5_Pos      (23U)

+#define BDMA_ISR_TEIF5_Msk      (0x1UL << BDMA_ISR_TEIF5_Pos)                  /*!< 0x00800000 */

+#define BDMA_ISR_TEIF5          BDMA_ISR_TEIF5_Msk                             /*!< Channel 5 Transfer Error flag */

+#define BDMA_ISR_GIF6_Pos       (24U)

+#define BDMA_ISR_GIF6_Msk       (0x1UL << BDMA_ISR_GIF6_Pos)                   /*!< 0x01000000 */

+#define BDMA_ISR_GIF6           BDMA_ISR_GIF6_Msk                              /*!< Channel 6 Global interrupt flag */

+#define BDMA_ISR_TCIF6_Pos      (25U)

+#define BDMA_ISR_TCIF6_Msk      (0x1UL << BDMA_ISR_TCIF6_Pos)                  /*!< 0x02000000 */

+#define BDMA_ISR_TCIF6          BDMA_ISR_TCIF6_Msk                             /*!< Channel 6 Transfer Complete flag */

+#define BDMA_ISR_HTIF6_Pos      (26U)

+#define BDMA_ISR_HTIF6_Msk      (0x1UL << BDMA_ISR_HTIF6_Pos)                  /*!< 0x04000000 */

+#define BDMA_ISR_HTIF6          BDMA_ISR_HTIF6_Msk                             /*!< Channel 6 Half Transfer flag */

+#define BDMA_ISR_TEIF6_Pos      (27U)

+#define BDMA_ISR_TEIF6_Msk      (0x1UL << BDMA_ISR_TEIF6_Pos)                  /*!< 0x08000000 */

+#define BDMA_ISR_TEIF6          BDMA_ISR_TEIF6_Msk                             /*!< Channel 6 Transfer Error flag */

+#define BDMA_ISR_GIF7_Pos       (28U)

+#define BDMA_ISR_GIF7_Msk       (0x1UL << BDMA_ISR_GIF7_Pos)                   /*!< 0x10000000 */

+#define BDMA_ISR_GIF7           BDMA_ISR_GIF7_Msk                              /*!< Channel 7 Global interrupt flag */

+#define BDMA_ISR_TCIF7_Pos      (29U)

+#define BDMA_ISR_TCIF7_Msk      (0x1UL << BDMA_ISR_TCIF7_Pos)                  /*!< 0x20000000 */

+#define BDMA_ISR_TCIF7          BDMA_ISR_TCIF7_Msk                             /*!< Channel 7 Transfer Complete flag */

+#define BDMA_ISR_HTIF7_Pos      (30U)

+#define BDMA_ISR_HTIF7_Msk      (0x1UL << BDMA_ISR_HTIF7_Pos)                  /*!< 0x40000000 */

+#define BDMA_ISR_HTIF7          BDMA_ISR_HTIF7_Msk                             /*!< Channel 7 Half Transfer flag */

+#define BDMA_ISR_TEIF7_Pos      (31U)

+#define BDMA_ISR_TEIF7_Msk      (0x1UL << BDMA_ISR_TEIF7_Pos)                  /*!< 0x80000000 */

+#define BDMA_ISR_TEIF7          BDMA_ISR_TEIF7_Msk                             /*!< Channel 7 Transfer Error flag */

+

+/*******************  Bit definition for BDMA_IFCR register  *******************/

+#define BDMA_IFCR_CGIF0_Pos     (0U)

+#define BDMA_IFCR_CGIF0_Msk     (0x1UL << BDMA_IFCR_CGIF0_Pos)                 /*!< 0x00000001 */

+#define BDMA_IFCR_CGIF0         BDMA_IFCR_CGIF0_Msk                            /*!< Channel 0 Global interrupt clearr */

+#define BDMA_IFCR_CTCIF0_Pos    (1U)

+#define BDMA_IFCR_CTCIF0_Msk    (0x1UL << BDMA_IFCR_CTCIF0_Pos)                /*!< 0x00000002 */

+#define BDMA_IFCR_CTCIF0        BDMA_IFCR_CTCIF0_Msk                           /*!< Channel 0 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF0_Pos    (2U)

+#define BDMA_IFCR_CHTIF0_Msk    (0x1UL << BDMA_IFCR_CHTIF0_Pos)                /*!< 0x00000004 */

+#define BDMA_IFCR_CHTIF0        BDMA_IFCR_CHTIF0_Msk                           /*!< Channel 0 Half Transfer clear */

+#define BDMA_IFCR_CTEIF0_Pos    (3U)

+#define BDMA_IFCR_CTEIF0_Msk    (0x1UL << BDMA_IFCR_CTEIF0_Pos)                /*!< 0x00000008 */

+#define BDMA_IFCR_CTEIF0        BDMA_IFCR_CTEIF0_Msk                           /*!< Channel 0 Transfer Error clear */

+#define BDMA_IFCR_CGIF1_Pos     (4U)

+#define BDMA_IFCR_CGIF1_Msk     (0x1UL << BDMA_IFCR_CGIF1_Pos)                 /*!< 0x00000010 */

+#define BDMA_IFCR_CGIF1         BDMA_IFCR_CGIF1_Msk                            /*!< Channel 1 Global interrupt clear */

+#define BDMA_IFCR_CTCIF1_Pos    (5U)

+#define BDMA_IFCR_CTCIF1_Msk    (0x1UL << BDMA_IFCR_CTCIF1_Pos)                /*!< 0x00000020 */

+#define BDMA_IFCR_CTCIF1        BDMA_IFCR_CTCIF1_Msk                           /*!< Channel 1 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF1_Pos    (6U)

+#define BDMA_IFCR_CHTIF1_Msk    (0x1UL << BDMA_IFCR_CHTIF1_Pos)                /*!< 0x00000040 */

+#define BDMA_IFCR_CHTIF1        BDMA_IFCR_CHTIF1_Msk                           /*!< Channel 1 Half Transfer clear */

+#define BDMA_IFCR_CTEIF1_Pos    (7U)

+#define BDMA_IFCR_CTEIF1_Msk    (0x1UL << BDMA_IFCR_CTEIF1_Pos)                /*!< 0x00000080 */

+#define BDMA_IFCR_CTEIF1        BDMA_IFCR_CTEIF1_Msk                           /*!< Channel 1 Transfer Error clear */

+#define BDMA_IFCR_CGIF2_Pos     (8U)

+#define BDMA_IFCR_CGIF2_Msk     (0x1UL << BDMA_IFCR_CGIF2_Pos)                 /*!< 0x00000100 */

+#define BDMA_IFCR_CGIF2         BDMA_IFCR_CGIF2_Msk                            /*!< Channel 2 Global interrupt clear */

+#define BDMA_IFCR_CTCIF2_Pos    (9U)

+#define BDMA_IFCR_CTCIF2_Msk    (0x1UL << BDMA_IFCR_CTCIF2_Pos)                /*!< 0x00000200 */

+#define BDMA_IFCR_CTCIF2        BDMA_IFCR_CTCIF2_Msk                           /*!< Channel 2 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF2_Pos    (10U)

+#define BDMA_IFCR_CHTIF2_Msk    (0x1UL << BDMA_IFCR_CHTIF2_Pos)                /*!< 0x00000400 */

+#define BDMA_IFCR_CHTIF2        BDMA_IFCR_CHTIF2_Msk                           /*!< Channel 2 Half Transfer clear */

+#define BDMA_IFCR_CTEIF2_Pos    (11U)

+#define BDMA_IFCR_CTEIF2_Msk    (0x1UL << BDMA_IFCR_CTEIF2_Pos)                /*!< 0x00000800 */

+#define BDMA_IFCR_CTEIF2        BDMA_IFCR_CTEIF2_Msk                           /*!< Channel 2 Transfer Error clear */

+#define BDMA_IFCR_CGIF3_Pos     (12U)

+#define BDMA_IFCR_CGIF3_Msk     (0x1UL << BDMA_IFCR_CGIF3_Pos)                 /*!< 0x00001000 */

+#define BDMA_IFCR_CGIF3         BDMA_IFCR_CGIF3_Msk                            /*!< Channel 3 Global interrupt clear */

+#define BDMA_IFCR_CTCIF3_Pos    (13U)

+#define BDMA_IFCR_CTCIF3_Msk    (0x1UL << BDMA_IFCR_CTCIF3_Pos)                /*!< 0x00002000 */

+#define BDMA_IFCR_CTCIF3        BDMA_IFCR_CTCIF3_Msk                           /*!< Channel 3 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF3_Pos    (14U)

+#define BDMA_IFCR_CHTIF3_Msk    (0x1UL << BDMA_IFCR_CHTIF3_Pos)                /*!< 0x00004000 */

+#define BDMA_IFCR_CHTIF3        BDMA_IFCR_CHTIF3_Msk                           /*!< Channel 3 Half Transfer clear */

+#define BDMA_IFCR_CTEIF3_Pos    (15U)

+#define BDMA_IFCR_CTEIF3_Msk    (0x1UL << BDMA_IFCR_CTEIF3_Pos)                /*!< 0x00008000 */

+#define BDMA_IFCR_CTEIF3        BDMA_IFCR_CTEIF3_Msk                           /*!< Channel 3 Transfer Error clear */

+#define BDMA_IFCR_CGIF4_Pos     (16U)

+#define BDMA_IFCR_CGIF4_Msk     (0x1UL << BDMA_IFCR_CGIF4_Pos)                 /*!< 0x00010000 */

+#define BDMA_IFCR_CGIF4         BDMA_IFCR_CGIF4_Msk                            /*!< Channel 4 Global interrupt clear */

+#define BDMA_IFCR_CTCIF4_Pos    (17U)

+#define BDMA_IFCR_CTCIF4_Msk    (0x1UL << BDMA_IFCR_CTCIF4_Pos)                /*!< 0x00020000 */

+#define BDMA_IFCR_CTCIF4        BDMA_IFCR_CTCIF4_Msk                           /*!< Channel 4 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF4_Pos    (18U)

+#define BDMA_IFCR_CHTIF4_Msk    (0x1UL << BDMA_IFCR_CHTIF4_Pos)                /*!< 0x00040000 */

+#define BDMA_IFCR_CHTIF4        BDMA_IFCR_CHTIF4_Msk                           /*!< Channel 4 Half Transfer clear */

+#define BDMA_IFCR_CTEIF4_Pos    (19U)

+#define BDMA_IFCR_CTEIF4_Msk    (0x1UL << BDMA_IFCR_CTEIF4_Pos)                /*!< 0x00080000 */

+#define BDMA_IFCR_CTEIF4        BDMA_IFCR_CTEIF4_Msk                           /*!< Channel 4 Transfer Error clear */

+#define BDMA_IFCR_CGIF5_Pos     (20U)

+#define BDMA_IFCR_CGIF5_Msk     (0x1UL << BDMA_IFCR_CGIF5_Pos)                 /*!< 0x00100000 */

+#define BDMA_IFCR_CGIF5         BDMA_IFCR_CGIF5_Msk                            /*!< Channel 5 Global interrupt clear */

+#define BDMA_IFCR_CTCIF5_Pos    (21U)

+#define BDMA_IFCR_CTCIF5_Msk    (0x1UL << BDMA_IFCR_CTCIF5_Pos)                /*!< 0x00200000 */

+#define BDMA_IFCR_CTCIF5        BDMA_IFCR_CTCIF5_Msk                           /*!< Channel 5 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF5_Pos    (22U)

+#define BDMA_IFCR_CHTIF5_Msk    (0x1UL << BDMA_IFCR_CHTIF5_Pos)                /*!< 0x00400000 */

+#define BDMA_IFCR_CHTIF5        BDMA_IFCR_CHTIF5_Msk                           /*!< Channel 5 Half Transfer clear */

+#define BDMA_IFCR_CTEIF5_Pos    (23U)

+#define BDMA_IFCR_CTEIF5_Msk    (0x1UL << BDMA_IFCR_CTEIF5_Pos)                /*!< 0x00800000 */

+#define BDMA_IFCR_CTEIF5        BDMA_IFCR_CTEIF5_Msk                           /*!< Channel 5 Transfer Error clear */

+#define BDMA_IFCR_CGIF6_Pos     (24U)

+#define BDMA_IFCR_CGIF6_Msk     (0x1UL << BDMA_IFCR_CGIF6_Pos)                 /*!< 0x01000000 */

+#define BDMA_IFCR_CGIF6         BDMA_IFCR_CGIF6_Msk                            /*!< Channel 6 Global interrupt clear */

+#define BDMA_IFCR_CTCIF6_Pos    (25U)

+#define BDMA_IFCR_CTCIF6_Msk    (0x1UL << BDMA_IFCR_CTCIF6_Pos)                /*!< 0x02000000 */

+#define BDMA_IFCR_CTCIF6        BDMA_IFCR_CTCIF6_Msk                           /*!< Channel 6 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF6_Pos    (26U)

+#define BDMA_IFCR_CHTIF6_Msk    (0x1UL << BDMA_IFCR_CHTIF6_Pos)                /*!< 0x04000000 */

+#define BDMA_IFCR_CHTIF6        BDMA_IFCR_CHTIF6_Msk                           /*!< Channel 6 Half Transfer clear */

+#define BDMA_IFCR_CTEIF6_Pos    (27U)

+#define BDMA_IFCR_CTEIF6_Msk    (0x1UL << BDMA_IFCR_CTEIF6_Pos)                /*!< 0x08000000 */

+#define BDMA_IFCR_CTEIF6        BDMA_IFCR_CTEIF6_Msk                           /*!< Channel 6 Transfer Error clear */

+#define BDMA_IFCR_CGIF7_Pos     (28U)

+#define BDMA_IFCR_CGIF7_Msk     (0x1UL << BDMA_IFCR_CGIF7_Pos)                 /*!< 0x10000000 */

+#define BDMA_IFCR_CGIF7         BDMA_IFCR_CGIF7_Msk                            /*!< Channel 7 Global interrupt clear */

+#define BDMA_IFCR_CTCIF7_Pos    (29U)

+#define BDMA_IFCR_CTCIF7_Msk    (0x1UL << BDMA_IFCR_CTCIF7_Pos)                /*!< 0x20000000 */

+#define BDMA_IFCR_CTCIF7        BDMA_IFCR_CTCIF7_Msk                           /*!< Channel 7 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF7_Pos    (30U)

+#define BDMA_IFCR_CHTIF7_Msk    (0x1UL << BDMA_IFCR_CHTIF7_Pos)                /*!< 0x40000000 */

+#define BDMA_IFCR_CHTIF7        BDMA_IFCR_CHTIF7_Msk                           /*!< Channel 7 Half Transfer clear */

+#define BDMA_IFCR_CTEIF7_Pos    (31U)

+#define BDMA_IFCR_CTEIF7_Msk    (0x1UL << BDMA_IFCR_CTEIF7_Pos)                /*!< 0x80000000 */

+#define BDMA_IFCR_CTEIF7        BDMA_IFCR_CTEIF7_Msk                           /*!< Channel 7 Transfer Error clear */

+

+/*******************  Bit definition for BDMA_CCR register  ********************/

+#define BDMA_CCR_EN_Pos         (0U)

+#define BDMA_CCR_EN_Msk         (0x1UL << BDMA_CCR_EN_Pos)                     /*!< 0x00000001 */

+#define BDMA_CCR_EN             BDMA_CCR_EN_Msk                                /*!< Channel enable                      */

+#define BDMA_CCR_TCIE_Pos       (1U)

+#define BDMA_CCR_TCIE_Msk       (0x1UL << BDMA_CCR_TCIE_Pos)                   /*!< 0x00000002 */

+#define BDMA_CCR_TCIE           BDMA_CCR_TCIE_Msk                              /*!< Transfer complete interrupt enable  */

+#define BDMA_CCR_HTIE_Pos       (2U)

+#define BDMA_CCR_HTIE_Msk       (0x1UL << BDMA_CCR_HTIE_Pos)                   /*!< 0x00000004 */

+#define BDMA_CCR_HTIE           BDMA_CCR_HTIE_Msk                              /*!< Half Transfer interrupt enable      */

+#define BDMA_CCR_TEIE_Pos       (3U)

+#define BDMA_CCR_TEIE_Msk       (0x1UL << BDMA_CCR_TEIE_Pos)                   /*!< 0x00000008 */

+#define BDMA_CCR_TEIE           BDMA_CCR_TEIE_Msk                              /*!< Transfer error interrupt enable     */

+#define BDMA_CCR_DIR_Pos        (4U)

+#define BDMA_CCR_DIR_Msk        (0x1UL << BDMA_CCR_DIR_Pos)                    /*!< 0x00000010 */

+#define BDMA_CCR_DIR            BDMA_CCR_DIR_Msk                               /*!< Data transfer direction             */

+#define BDMA_CCR_CIRC_Pos       (5U)

+#define BDMA_CCR_CIRC_Msk       (0x1UL << BDMA_CCR_CIRC_Pos)                   /*!< 0x00000020 */

+#define BDMA_CCR_CIRC           BDMA_CCR_CIRC_Msk                              /*!< Circular mode                       */

+#define BDMA_CCR_PINC_Pos       (6U)

+#define BDMA_CCR_PINC_Msk       (0x1UL << BDMA_CCR_PINC_Pos)                   /*!< 0x00000040 */

+#define BDMA_CCR_PINC           BDMA_CCR_PINC_Msk                              /*!< Peripheral increment mode           */

+#define BDMA_CCR_MINC_Pos       (7U)

+#define BDMA_CCR_MINC_Msk       (0x1UL << BDMA_CCR_MINC_Pos)                   /*!< 0x00000080 */

+#define BDMA_CCR_MINC           BDMA_CCR_MINC_Msk                              /*!< Memory increment mode               */

+

+#define BDMA_CCR_PSIZE_Pos      (8U)

+#define BDMA_CCR_PSIZE_Msk      (0x3UL << BDMA_CCR_PSIZE_Pos)                  /*!< 0x00000300 */

+#define BDMA_CCR_PSIZE          BDMA_CCR_PSIZE_Msk                             /*!< PSIZE[1:0] bits (Peripheral size)   */

+#define BDMA_CCR_PSIZE_0        (0x1UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000100 */

+#define BDMA_CCR_PSIZE_1        (0x2UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000200 */

+

+#define BDMA_CCR_MSIZE_Pos      (10U)

+#define BDMA_CCR_MSIZE_Msk      (0x3UL << BDMA_CCR_MSIZE_Pos)                  /*!< 0x00000C00 */

+#define BDMA_CCR_MSIZE          BDMA_CCR_MSIZE_Msk                             /*!< MSIZE[1:0] bits (Memory size)       */

+#define BDMA_CCR_MSIZE_0        (0x1UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000400 */

+#define BDMA_CCR_MSIZE_1        (0x2UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000800 */

+

+#define BDMA_CCR_PL_Pos         (12U)

+#define BDMA_CCR_PL_Msk         (0x3UL << BDMA_CCR_PL_Pos)                     /*!< 0x00003000 */

+#define BDMA_CCR_PL             BDMA_CCR_PL_Msk                                /*!< PL[1:0] bits(Channel Priority level)*/

+#define BDMA_CCR_PL_0           (0x1UL << BDMA_CCR_PL_Pos)                      /*!< 0x00001000 */

+#define BDMA_CCR_PL_1           (0x2UL << BDMA_CCR_PL_Pos)                      /*!< 0x00002000 */

+

+#define BDMA_CCR_MEM2MEM_Pos    (14U)

+#define BDMA_CCR_MEM2MEM_Msk    (0x1UL << BDMA_CCR_MEM2MEM_Pos)                /*!< 0x00004000 */

+#define BDMA_CCR_MEM2MEM        BDMA_CCR_MEM2MEM_Msk                           /*!< Memory to memory mode               */

+#define BDMA_CCR_DBM_Pos        (15U)

+#define BDMA_CCR_DBM_Msk        (0x1UL << BDMA_CCR_DBM_Pos)                    /*!< 0x0000A000 */

+#define BDMA_CCR_DBM            BDMA_CCR_DBM_Msk                               /*!< Memory to memory mode               */

+#define BDMA_CCR_CT_Pos         (16U)

+#define BDMA_CCR_CT_Msk         (0x1UL << BDMA_CCR_CT_Pos)                     /*!< 0x00010000 */

+#define BDMA_CCR_CT             BDMA_CCR_CT_Msk                                /*!< Memory to memory mode               */

+

+/******************  Bit definition for BDMA_CNDTR register  *******************/

+#define BDMA_CNDTR_NDT_Pos      (0U)

+#define BDMA_CNDTR_NDT_Msk      (0xFFFFUL << BDMA_CNDTR_NDT_Pos)               /*!< 0x0000FFFF */

+#define BDMA_CNDTR_NDT          BDMA_CNDTR_NDT_Msk                             /*!< Number of data to Transfer          */

+

+/******************  Bit definition for BDMA_CPAR register  ********************/

+#define BDMA_CPAR_PA_Pos        (0U)

+#define BDMA_CPAR_PA_Msk        (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CPAR_PA            BDMA_CPAR_PA_Msk                               /*!< Peripheral Address                  */

+

+/******************  Bit definition for BDMA_CM0AR register  ********************/

+#define BDMA_CM0AR_MA_Pos        (0U)

+#define BDMA_CM0AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CM0AR_MA            BDMA_CM0AR_MA_Msk                               /*!< Memory Address                      */

+

+/******************  Bit definition for BDMA_CM1AR register  ********************/

+#define BDMA_CM1AR_MA_Pos        (0U)

+#define BDMA_CM1AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CM1AR_MA            BDMA_CM1AR_MA_Msk                               /*!< Memory Address                      */

+

+/******************************************************************************/

+/*                                                                            */

+/*                Ethernet MAC Registers bits definitions                     */

+/*                                                                            */

+/******************************************************************************/

+/* Bit definition for Ethernet MAC Configuration Register register */

+#define ETH_MACCR_ARP_Pos                             (31U)

+#define ETH_MACCR_ARP_Msk                             (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */

+#define ETH_MACCR_ARP                                 ETH_MACCR_ARP_Msk        /* ARP Offload Enable */

+#define ETH_MACCR_SARC_Pos                            (28U)

+#define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */

+#define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */

+#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */

+#define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)

+#define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */

+#define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */

+#define ETH_MACCR_SARC_INSADDR1_Pos                   (29U)

+#define ETH_MACCR_SARC_INSADDR1_Msk                   (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */

+#define ETH_MACCR_SARC_INSADDR1                       ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */

+#define ETH_MACCR_SARC_REPADDR0_Pos                   (28U)

+#define ETH_MACCR_SARC_REPADDR0_Msk                   (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */

+#define ETH_MACCR_SARC_REPADDR0                       ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */

+#define ETH_MACCR_SARC_REPADDR1_Pos                   (28U)

+#define ETH_MACCR_SARC_REPADDR1_Msk                   (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */

+#define ETH_MACCR_SARC_REPADDR1                       ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */

+#define ETH_MACCR_IPC_Pos                             (27U)

+#define ETH_MACCR_IPC_Msk                             (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */

+#define ETH_MACCR_IPC                                 ETH_MACCR_IPC_Msk        /* Checksum Offload */

+#define ETH_MACCR_IPG_Pos                             (24U)

+#define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */

+#define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */

+#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */

+#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */

+#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */

+#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */

+#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */

+#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */

+#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */

+#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */

+#define ETH_MACCR_GPSLCE_Pos                          (23U)

+#define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */

+#define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */

+#define ETH_MACCR_S2KP_Pos                            (22U)

+#define ETH_MACCR_S2KP_Msk                            (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */

+#define ETH_MACCR_S2KP                                ETH_MACCR_S2KP_Msk       /* IEEE 802.3as Support for 2K Packets */

+#define ETH_MACCR_CST_Pos                             (21U)

+#define ETH_MACCR_CST_Msk                             (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */

+#define ETH_MACCR_CST                                 ETH_MACCR_CST_Msk        /* CRC stripping for Type packets */

+#define ETH_MACCR_ACS_Pos                             (20U)

+#define ETH_MACCR_ACS_Msk                             (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */

+#define ETH_MACCR_ACS                                 ETH_MACCR_ACS_Msk        /* Automatic Pad or CRC Stripping */

+#define ETH_MACCR_WD_Pos                              (19U)

+#define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */

+#define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */

+#define ETH_MACCR_JD_Pos                              (17U)

+#define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */

+#define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */

+#define ETH_MACCR_JE_Pos                              (16U)

+#define ETH_MACCR_JE_Msk                              (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */

+#define ETH_MACCR_JE                                  ETH_MACCR_JE_Msk         /* Jumbo Packet Enable */

+#define ETH_MACCR_FES_Pos                             (14U)

+#define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */

+#define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */

+#define ETH_MACCR_DM_Pos                              (13U)

+#define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */

+#define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */

+#define ETH_MACCR_LM_Pos                              (12U)

+#define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */

+#define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */

+#define ETH_MACCR_ECRSFD_Pos                          (11U)

+#define ETH_MACCR_ECRSFD_Msk                          (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */

+#define ETH_MACCR_ECRSFD                              ETH_MACCR_ECRSFD_Msk     /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */

+#define ETH_MACCR_DO_Pos                              (10U)

+#define ETH_MACCR_DO_Msk                              (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */

+#define ETH_MACCR_DO                                  ETH_MACCR_DO_Msk         /* Disable Receive own  */

+#define ETH_MACCR_DCRS_Pos                            (9U)

+#define ETH_MACCR_DCRS_Msk                            (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */

+#define ETH_MACCR_DCRS                                ETH_MACCR_DCRS_Msk       /* Disable Carrier Sense During Transmission */

+#define ETH_MACCR_DR_Pos                              (8U)

+#define ETH_MACCR_DR_Msk                              (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */

+#define ETH_MACCR_DR                                  ETH_MACCR_DR_Msk         /* Disable Retry */

+#define ETH_MACCR_BL_Pos                              (5U)

+#define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */

+#define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit mask */

+#define ETH_MACCR_BL_10                               (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */

+#define ETH_MACCR_BL_8                                (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */

+#define ETH_MACCR_BL_4                                (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */

+#define ETH_MACCR_BL_1                                (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */

+#define ETH_MACCR_DC_Pos                              (4U)

+#define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */

+#define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */

+#define ETH_MACCR_PRELEN_Pos                          (2U)

+#define ETH_MACCR_PRELEN_Msk                          (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */

+#define ETH_MACCR_PRELEN                              ETH_MACCR_PRELEN_Msk     /* Preamble Length for Transmit packets */

+#define ETH_MACCR_PRELEN_7                            (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */

+#define ETH_MACCR_PRELEN_5                            (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */

+#define ETH_MACCR_PRELEN_3                            (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */

+#define ETH_MACCR_TE_Pos                              (1U)

+#define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */

+#define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */

+#define ETH_MACCR_RE_Pos                              (0U)

+#define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */

+#define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */

+

+/* Bit definition for Ethernet MAC Extended Configuration Register register */

+#define ETH_MACECR_EIPG_Pos                           (25U)

+#define ETH_MACECR_EIPG_Msk                           (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */

+#define ETH_MACECR_EIPG                               ETH_MACECR_EIPG_Msk      /* Extended Inter-Packet Gap */

+#define ETH_MACECR_EIPGEN_Pos                         (24U)

+#define ETH_MACECR_EIPGEN_Msk                         (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */

+#define ETH_MACECR_EIPGEN                             ETH_MACECR_EIPGEN_Msk    /* Extended Inter-Packet Gap Enable */

+#define ETH_MACECR_USP_Pos                            (18U)

+#define ETH_MACECR_USP_Msk                            (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */

+#define ETH_MACECR_USP                                ETH_MACECR_USP_Msk       /* Unicast Slow Protocol Packet Detect */

+#define ETH_MACECR_SPEN_Pos                           (17U)

+#define ETH_MACECR_SPEN_Msk                           (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */

+#define ETH_MACECR_SPEN                               ETH_MACECR_SPEN_Msk      /* Slow Protocol Detection Enable */

+#define ETH_MACECR_DCRCC_Pos                          (16U)

+#define ETH_MACECR_DCRCC_Msk                          (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */

+#define ETH_MACECR_DCRCC                              ETH_MACECR_DCRCC_Msk     /* Disable CRC Checking for Received Packets */

+#define ETH_MACECR_GPSL_Pos                           (0U)

+#define ETH_MACECR_GPSL_Msk                           (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */

+#define ETH_MACECR_GPSL                               ETH_MACECR_GPSL_Msk      /* Giant Packet Size Limit */

+

+/* Bit definition for Ethernet MAC Packet Filter Register */

+#define ETH_MACPFR_RA_Pos                             (31U)

+#define ETH_MACPFR_RA_Msk                             (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */

+#define ETH_MACPFR_RA                                 ETH_MACPFR_RA_Msk        /* Receive all */

+#define ETH_MACPFR_DNTU_Pos                           (21U)

+#define ETH_MACPFR_DNTU_Msk                           (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */

+#define ETH_MACPFR_DNTU                               ETH_MACPFR_DNTU_Msk      /* Drop Non-TCP/UDP over IP Packets */

+#define ETH_MACPFR_IPFE_Pos                           (20U)

+#define ETH_MACPFR_IPFE_Msk                           (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */

+#define ETH_MACPFR_IPFE                               ETH_MACPFR_IPFE_Msk      /* Layer 3 and Layer 4 Filter Enable */

+#define ETH_MACPFR_VTFE_Pos                           (16U)

+#define ETH_MACPFR_VTFE_Msk                           (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */

+#define ETH_MACPFR_VTFE                               ETH_MACPFR_VTFE_Msk      /* VLAN Tag Filter Enable */

+#define ETH_MACPFR_HPF_Pos                            (10U)

+#define ETH_MACPFR_HPF_Msk                            (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */

+#define ETH_MACPFR_HPF                                ETH_MACPFR_HPF_Msk       /* Hash or perfect filter */

+#define ETH_MACPFR_SAF_Pos                            (9U)

+#define ETH_MACPFR_SAF_Msk                            (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */

+#define ETH_MACPFR_SAF                                ETH_MACPFR_SAF_Msk       /* Source address filter enable */

+#define ETH_MACPFR_SAIF_Pos                           (8U)

+#define ETH_MACPFR_SAIF_Msk                           (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */

+#define ETH_MACPFR_SAIF                               ETH_MACPFR_SAIF_Msk      /* SA inverse filtering */

+#define ETH_MACPFR_PCF_Pos                            (6U)

+#define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */

+#define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */

+#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */

+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)

+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */

+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */

+#define ETH_MACPFR_PCF_FORWARDALL_Pos                 (7U)

+#define ETH_MACPFR_PCF_FORWARDALL_Msk                 (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */

+#define ETH_MACPFR_PCF_FORWARDALL                     ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */

+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos    (6U)

+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk    (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */

+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER        ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */

+#define ETH_MACPFR_DBF_Pos                            (5U)

+#define ETH_MACPFR_DBF_Msk                            (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */

+#define ETH_MACPFR_DBF                                ETH_MACPFR_DBF_Msk       /* Disable Broadcast Packets */

+#define ETH_MACPFR_PM_Pos                             (4U)

+#define ETH_MACPFR_PM_Msk                             (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */

+#define ETH_MACPFR_PM                                 ETH_MACPFR_PM_Msk        /* Pass all mutlicast */

+#define ETH_MACPFR_DAIF_Pos                           (3U)

+#define ETH_MACPFR_DAIF_Msk                           (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */

+#define ETH_MACPFR_DAIF                               ETH_MACPFR_DAIF_Msk      /* DA Inverse filtering */

+#define ETH_MACPFR_HMC_Pos                            (2U)

+#define ETH_MACPFR_HMC_Msk                            (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */

+#define ETH_MACPFR_HMC                                ETH_MACPFR_HMC_Msk       /* Hash multicast */

+#define ETH_MACPFR_HUC_Pos                            (1U)

+#define ETH_MACPFR_HUC_Msk                            (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */

+#define ETH_MACPFR_HUC                                ETH_MACPFR_HUC_Msk       /* Hash unicast */

+#define ETH_MACPFR_PR_Pos                             (0U)

+#define ETH_MACPFR_PR_Msk                             (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */

+#define ETH_MACPFR_PR                                 ETH_MACPFR_PR_Msk        /* Promiscuous mode */

+

+/* Bit definition for Ethernet MAC Watchdog Timeout Register */

+#define ETH_MACWTR_PWE_Pos                            (8U)

+#define ETH_MACWTR_PWE_Msk                            (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */

+#define ETH_MACWTR_PWE                                ETH_MACWTR_PWE_Msk       /* Programmable Watchdog Enable */

+#define ETH_MACWTR_WTO_Pos                            (0U)

+#define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */

+#define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */

+#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/

+#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */

+#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */

+#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */

+#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */

+#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */

+#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */

+#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */

+#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */

+#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */

+#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */

+#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */

+#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */

+#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */

+#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */

+

+/* Bit definition for Ethernet MAC Hash Table High Register */

+#define ETH_MACHTHR_HTH_Pos                           (0U)

+#define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */

+

+/* Bit definition for Ethernet MAC Hash Table Low Register */

+#define ETH_MACHTLR_HTL_Pos                           (0U)

+#define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */

+

+/* Bit definition for Ethernet MAC VLAN Tag Register */

+#define ETH_MACVTR_EIVLRXS_Pos                        (31U)

+#define ETH_MACVTR_EIVLRXS_Msk                        (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */

+#define ETH_MACVTR_EIVLRXS                            ETH_MACVTR_EIVLRXS_Msk   /* Enable Inner VLAN Tag in Rx Status */

+#define ETH_MACVTR_EIVLS_Pos                          (28U)

+#define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */

+#define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */

+#define ETH_MACVTR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */

+#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)

+#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */

+#define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */

+#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos             (29U)

+#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk             (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */

+#define ETH_MACVTR_EIVLS_STRIPIFFAILS                 ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */

+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos              (28U)

+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk              (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */

+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP                  ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */

+#define ETH_MACVTR_ERIVLT_Pos                         (27U)

+#define ETH_MACVTR_ERIVLT_Msk                         (0x1UL << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */

+#define ETH_MACVTR_ERIVLT                             ETH_MACVTR_ERIVLT_Msk    /* Enable Inner VLAN Tag */

+#define ETH_MACVTR_EDVLP_Pos                          (26U)

+#define ETH_MACVTR_EDVLP_Msk                          (0x1UL << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */

+#define ETH_MACVTR_EDVLP                              ETH_MACVTR_EDVLP_Msk     /* Enable Double VLAN Processing */

+#define ETH_MACVTR_VTHM_Pos                           (25U)

+#define ETH_MACVTR_VTHM_Msk                           (0x1UL << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */

+#define ETH_MACVTR_VTHM                               ETH_MACVTR_VTHM_Msk      /* VLAN Tag Hash Table Match Enable */

+#define ETH_MACVTR_EVLRXS_Pos                         (24U)

+#define ETH_MACVTR_EVLRXS_Msk                         (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */

+#define ETH_MACVTR_EVLRXS                             ETH_MACVTR_EVLRXS_Msk    /* Enable VLAN Tag in Rx status */

+#define ETH_MACVTR_EVLS_Pos                           (21U)

+#define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */

+#define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */

+#define ETH_MACVTR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */

+#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)

+#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */

+#define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */

+#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos              (22U)

+#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk              (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */

+#define ETH_MACVTR_EVLS_STRIPIFFAILS                  ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */

+#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos               (21U)

+#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk               (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */

+#define ETH_MACVTR_EVLS_ALWAYSSTRIP                   ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */

+#define ETH_MACVTR_DOVLTC_Pos                         (20U)

+#define ETH_MACVTR_DOVLTC_Msk                         (0x1UL << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */

+#define ETH_MACVTR_DOVLTC                             ETH_MACVTR_DOVLTC_Msk    /* Disable VLAN Type Check */

+#define ETH_MACVTR_ERSVLM_Pos                         (19U)

+#define ETH_MACVTR_ERSVLM_Msk                         (0x1UL << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */

+#define ETH_MACVTR_ERSVLM                             ETH_MACVTR_ERSVLM_Msk    /* Enable Receive S-VLAN Match */

+#define ETH_MACVTR_ESVL_Pos                           (18U)

+#define ETH_MACVTR_ESVL_Msk                           (0x1UL << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */

+#define ETH_MACVTR_ESVL                               ETH_MACVTR_ESVL_Msk      /* Enable S-VLAN */

+#define ETH_MACVTR_VTIM_Pos                           (17U)

+#define ETH_MACVTR_VTIM_Msk                           (0x1UL << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */

+#define ETH_MACVTR_VTIM                               ETH_MACVTR_VTIM_Msk      /* VLAN Tag Inverse Match Enable */

+#define ETH_MACVTR_ETV_Pos                            (16U)

+#define ETH_MACVTR_ETV_Msk                            (0x1UL << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */

+#define ETH_MACVTR_ETV                                ETH_MACVTR_ETV_Msk       /* Enable 12-Bit VLAN Tag Comparison */

+#define ETH_MACVTR_VL_Pos                             (0U)

+#define ETH_MACVTR_VL_Msk                             (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */

+#define ETH_MACVTR_VL                                 ETH_MACVTR_VL_Msk        /* VLAN Tag Identifier for Receive Packets */

+#define ETH_MACVTR_VL_UP_Pos                          (13U)

+#define ETH_MACVTR_VL_UP_Msk                          (0x7UL << ETH_MACVTR_VL_UP_Pos) /*!< 0x0000E000 */

+#define ETH_MACVTR_VL_UP                              ETH_MACVTR_VL_UP_Msk     /* User Priority */

+#define ETH_MACVTR_VL_CFIDEI_Pos                      (12U)

+#define ETH_MACVTR_VL_CFIDEI_Msk                      (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos) /*!< 0x00001000 */

+#define ETH_MACVTR_VL_CFIDEI                          ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */

+#define ETH_MACVTR_VL_VID_Pos                         (0U)

+#define ETH_MACVTR_VL_VID_Msk                         (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */

+#define ETH_MACVTR_VL_VID                             ETH_MACVTR_VL_VID_Msk    /* VLAN Identifier field of VLAN tag */

+

+/* Bit definition for Ethernet MAC VLAN Hash Table Register */

+#define ETH_MACVHTR_VLHT_Pos                          (0U)

+#define ETH_MACVHTR_VLHT_Msk                          (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACVHTR_VLHT                              ETH_MACVHTR_VLHT_Msk     /* VLAN Hash Table */

+

+/* Bit definition for Ethernet MAC VLAN Incl Register */

+#define ETH_MACVIR_VLTI_Pos                           (20U)

+#define ETH_MACVIR_VLTI_Msk                           (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */

+#define ETH_MACVIR_VLTI                               ETH_MACVIR_VLTI_Msk      /* VLAN Tag Input */

+#define ETH_MACVIR_CSVL_Pos                           (19U)

+#define ETH_MACVIR_CSVL_Msk                           (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */

+#define ETH_MACVIR_CSVL                               ETH_MACVIR_CSVL_Msk      /* C-VLAN or S-VLAN */

+#define ETH_MACVIR_VLP_Pos                            (18U)

+#define ETH_MACVIR_VLP_Msk                            (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */

+#define ETH_MACVIR_VLP                                ETH_MACVIR_VLP_Msk       /* VLAN Priority Control */

+#define ETH_MACVIR_VLC_Pos                            (16U)

+#define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */

+#define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */

+#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */

+#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)

+#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */

+#define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */

+#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos              (17U)

+#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */

+#define ETH_MACVIR_VLC_VLANTAGINSERT                  ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */

+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos             (16U)

+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk             (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */

+#define ETH_MACVIR_VLC_VLANTAGREPLACE                 ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */

+#define ETH_MACVIR_VLT_Pos                            (0U)

+#define ETH_MACVIR_VLT_Msk                            (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACVIR_VLT                                ETH_MACVIR_VLT_Msk       /* VLAN Tag for Transmit Packets */

+#define ETH_MACVIR_VLT_UP_Pos                         (13U)

+#define ETH_MACVIR_VLT_UP_Msk                         (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */

+#define ETH_MACVIR_VLT_UP                             ETH_MACVIR_VLT_UP_Msk    /* User Priority */

+#define ETH_MACVIR_VLT_CFIDEI_Pos                     (12U)

+#define ETH_MACVIR_VLT_CFIDEI_Msk                     (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */

+#define ETH_MACVIR_VLT_CFIDEI                         ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */

+#define ETH_MACVIR_VLT_VID_Pos                        (0U)

+#define ETH_MACVIR_VLT_VID_Msk                        (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */

+#define ETH_MACVIR_VLT_VID                            ETH_MACVIR_VLT_VID_Msk   /* VLAN Identifier field of VLAN tag */

+

+/* Bit definition for Ethernet MAC Inner_VLAN Incl Register */

+#define ETH_MACIVIR_VLTI_Pos                          (20U)

+#define ETH_MACIVIR_VLTI_Msk                          (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */

+#define ETH_MACIVIR_VLTI                              ETH_MACIVIR_VLTI_Msk     /* VLAN Tag Input */

+#define ETH_MACIVIR_CSVL_Pos                          (19U)

+#define ETH_MACIVIR_CSVL_Msk                          (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */

+#define ETH_MACIVIR_CSVL                              ETH_MACIVIR_CSVL_Msk     /* C-VLAN or S-VLAN */

+#define ETH_MACIVIR_VLP_Pos                           (18U)

+#define ETH_MACIVIR_VLP_Msk                           (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */

+#define ETH_MACIVIR_VLP                               ETH_MACIVIR_VLP_Msk      /* VLAN Priority Control */

+#define ETH_MACIVIR_VLC_Pos                           (16U)

+#define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */

+#define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */

+#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */

+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)

+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */

+#define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */

+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos             (17U)

+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */

+#define ETH_MACIVIR_VLC_VLANTAGINSERT                 ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */

+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos            (16U)

+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk            (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */

+#define ETH_MACIVIR_VLC_VLANTAGREPLACE                ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */

+#define ETH_MACIVIR_VLT_Pos                           (0U)

+#define ETH_MACIVIR_VLT_Msk                           (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACIVIR_VLT                               ETH_MACIVIR_VLT_Msk      /* VLAN Tag for Transmit Packets */

+#define ETH_MACIVIR_VLT_UP_Pos                        (13U)

+#define ETH_MACIVIR_VLT_UP_Msk                        (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */

+#define ETH_MACIVIR_VLT_UP                            ETH_MACIVIR_VLT_UP_Msk   /* User Priority */

+#define ETH_MACIVIR_VLT_CFIDEI_Pos                    (12U)

+#define ETH_MACIVIR_VLT_CFIDEI_Msk                    (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */

+#define ETH_MACIVIR_VLT_CFIDEI                        ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */

+#define ETH_MACIVIR_VLT_VID_Pos                       (0U)

+#define ETH_MACIVIR_VLT_VID_Msk                       (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */

+#define ETH_MACIVIR_VLT_VID                           ETH_MACIVIR_VLT_VID_Msk  /* VLAN Identifier field of VLAN tag */

+

+/* Bit definition for Ethernet MAC Tx Flow Ctrl Register */

+#define ETH_MACTFCR_PT_Pos                            (16U)

+#define ETH_MACTFCR_PT_Msk                            (0xFFFFUL << ETH_MACTFCR_PT_Pos) /*!< 0xFFFF0000 */

+#define ETH_MACTFCR_PT                                ETH_MACTFCR_PT_Msk       /* Pause Time */

+#define ETH_MACTFCR_DZPQ_Pos                          (7U)

+#define ETH_MACTFCR_DZPQ_Msk                          (0x1UL << ETH_MACTFCR_DZPQ_Pos) /*!< 0x00000080 */

+#define ETH_MACTFCR_DZPQ                              ETH_MACTFCR_DZPQ_Msk     /* Disable Zero-Quanta Pause */

+#define ETH_MACTFCR_PLT_Pos                           (4U)

+#define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */

+#define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */

+#define ETH_MACTFCR_PLT_MINUS4                        ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */

+#define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)

+#define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */

+#define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */

+#define ETH_MACTFCR_PLT_MINUS36_Pos                   (5U)

+#define ETH_MACTFCR_PLT_MINUS36_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */

+#define ETH_MACTFCR_PLT_MINUS36                       ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */

+#define ETH_MACTFCR_PLT_MINUS144_Pos                  (4U)

+#define ETH_MACTFCR_PLT_MINUS144_Msk                  (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */

+#define ETH_MACTFCR_PLT_MINUS144                      ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */

+#define ETH_MACTFCR_PLT_MINUS256_Pos                  (6U)

+#define ETH_MACTFCR_PLT_MINUS256_Msk                  (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */

+#define ETH_MACTFCR_PLT_MINUS256                      ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */

+#define ETH_MACTFCR_PLT_MINUS512_Pos                  (4U)

+#define ETH_MACTFCR_PLT_MINUS512_Msk                  (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */

+#define ETH_MACTFCR_PLT_MINUS512                      ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */

+#define ETH_MACTFCR_TFE_Pos                           (1U)

+#define ETH_MACTFCR_TFE_Msk                           (0x1UL << ETH_MACTFCR_TFE_Pos) /*!< 0x00000002 */

+#define ETH_MACTFCR_TFE                               ETH_MACTFCR_TFE_Msk      /* Transmit Flow Control Enable */

+#define ETH_MACTFCR_FCB_Pos                           (0U)

+#define ETH_MACTFCR_FCB_Msk                           (0x1UL << ETH_MACTFCR_FCB_Pos) /*!< 0x00000001 */

+#define ETH_MACTFCR_FCB                               ETH_MACTFCR_FCB_Msk      /* Flow Control Busy or Backpressure Activate */

+

+/* Bit definition for Ethernet MAC Rx Flow Ctrl Register */

+#define ETH_MACRFCR_UP_Pos                            (1U)

+#define ETH_MACRFCR_UP_Msk                            (0x1UL << ETH_MACRFCR_UP_Pos) /*!< 0x00000002 */

+#define ETH_MACRFCR_UP                                ETH_MACRFCR_UP_Msk       /* Unicast Pause Packet Detect */

+#define ETH_MACRFCR_RFE_Pos                           (0U)

+#define ETH_MACRFCR_RFE_Msk                           (0x1UL << ETH_MACRFCR_RFE_Pos) /*!< 0x00000001 */

+#define ETH_MACRFCR_RFE                               ETH_MACRFCR_RFE_Msk      /* Receive Flow Control Enable */

+

+/* Bit definition for Ethernet MAC Interrupt Status Register */

+#define ETH_MACISR_RXSTSIS_Pos                        (14U)

+#define ETH_MACISR_RXSTSIS_Msk                        (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */

+#define ETH_MACISR_RXSTSIS                            ETH_MACISR_RXSTSIS_Msk   /* Receive Status Interrupt */

+#define ETH_MACISR_TXSTSIS_Pos                        (13U)

+#define ETH_MACISR_TXSTSIS_Msk                        (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */

+#define ETH_MACISR_TXSTSIS                            ETH_MACISR_TXSTSIS_Msk   /* Transmit Status Interrupt */

+#define ETH_MACISR_TSIS_Pos                           (12U)

+#define ETH_MACISR_TSIS_Msk                           (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */

+#define ETH_MACISR_TSIS                               ETH_MACISR_TSIS_Msk      /* Timestamp Interrupt Status */

+#define ETH_MACISR_MMCTXIS_Pos                        (10U)

+#define ETH_MACISR_MMCTXIS_Msk                        (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */

+#define ETH_MACISR_MMCTXIS                            ETH_MACISR_MMCTXIS_Msk   /* MMC Transmit Interrupt Status */

+#define ETH_MACISR_MMCRXIS_Pos                        (9U)

+#define ETH_MACISR_MMCRXIS_Msk                        (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */

+#define ETH_MACISR_MMCRXIS                            ETH_MACISR_MMCRXIS_Msk   /* MMC Receive Interrupt Status */

+#define ETH_MACISR_MMCIS_Pos                          (8U)

+#define ETH_MACISR_MMCIS_Msk                          (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */

+#define ETH_MACISR_MMCIS                              ETH_MACISR_MMCIS_Msk     /* MMC Interrupt Status */

+#define ETH_MACISR_LPIIS_Pos                          (5U)

+#define ETH_MACISR_LPIIS_Msk                          (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */

+#define ETH_MACISR_LPIIS                              ETH_MACISR_LPIIS_Msk     /* LPI Interrupt Status */

+#define ETH_MACISR_PMTIS_Pos                          (4U)

+#define ETH_MACISR_PMTIS_Msk                          (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */

+#define ETH_MACISR_PMTIS                              ETH_MACISR_PMTIS_Msk     /* PMT Interrupt Status */

+#define ETH_MACISR_PHYIS_Pos                          (3U)

+#define ETH_MACISR_PHYIS_Msk                          (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */

+#define ETH_MACISR_PHYIS                              ETH_MACISR_PHYIS_Msk     /* PHY Interrupt */

+

+/* Bit definition for Ethernet MAC Interrupt Enable Register */

+#define ETH_MACIER_RXSTSIE_Pos                        (14U)

+#define ETH_MACIER_RXSTSIE_Msk                        (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */

+#define ETH_MACIER_RXSTSIE                            ETH_MACIER_RXSTSIE_Msk   /* Receive Status Interrupt Enable */

+#define ETH_MACIER_TXSTSIE_Pos                        (13U)

+#define ETH_MACIER_TXSTSIE_Msk                        (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */

+#define ETH_MACIER_TXSTSIE                            ETH_MACIER_TXSTSIE_Msk   /* Transmit Status Interrupt Enable */

+#define ETH_MACIER_TSIE_Pos                           (12U)

+#define ETH_MACIER_TSIE_Msk                           (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */

+#define ETH_MACIER_TSIE                               ETH_MACIER_TSIE_Msk      /* Timestamp Interrupt Enable */

+#define ETH_MACIER_LPIIE_Pos                          (5U)

+#define ETH_MACIER_LPIIE_Msk                          (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */

+#define ETH_MACIER_LPIIE                              ETH_MACIER_LPIIE_Msk     /* LPI Interrupt Enable */

+#define ETH_MACIER_PMTIE_Pos                          (4U)

+#define ETH_MACIER_PMTIE_Msk                          (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */

+#define ETH_MACIER_PMTIE                              ETH_MACIER_PMTIE_Msk     /* PMT Interrupt Enable */

+#define ETH_MACIER_PHYIE_Pos                          (3U)

+#define ETH_MACIER_PHYIE_Msk                          (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */

+#define ETH_MACIER_PHYIE                              ETH_MACIER_PHYIE_Msk     /* PHY Interrupt Enable */

+

+/* Bit definition for Ethernet MAC Rx Tx Status Register */

+#define ETH_MACRXTXSR_RWT_Pos                         (8U)

+#define ETH_MACRXTXSR_RWT_Msk                         (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */

+#define ETH_MACRXTXSR_RWT                             ETH_MACRXTXSR_RWT_Msk    /* Receive Watchdog Timeout */

+#define ETH_MACRXTXSR_EXCOL_Pos                       (5U)

+#define ETH_MACRXTXSR_EXCOL_Msk                       (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */

+#define ETH_MACRXTXSR_EXCOL                           ETH_MACRXTXSR_EXCOL_Msk  /* Excessive Collisions */

+#define ETH_MACRXTXSR_LCOL_Pos                        (4U)

+#define ETH_MACRXTXSR_LCOL_Msk                        (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */

+#define ETH_MACRXTXSR_LCOL                            ETH_MACRXTXSR_LCOL_Msk   /* Late Collision */

+#define ETH_MACRXTXSR_EXDEF_Pos                       (3U)

+#define ETH_MACRXTXSR_EXDEF_Msk                       (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */

+#define ETH_MACRXTXSR_EXDEF                           ETH_MACRXTXSR_EXDEF_Msk  /* Excessive Deferral */

+#define ETH_MACRXTXSR_LCARR_Pos                       (2U)

+#define ETH_MACRXTXSR_LCARR_Msk                       (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */

+#define ETH_MACRXTXSR_LCARR                           ETH_MACRXTXSR_LCARR_Msk  /* Loss of Carrier */

+#define ETH_MACRXTXSR_NCARR_Pos                       (1U)

+#define ETH_MACRXTXSR_NCARR_Msk                       (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */

+#define ETH_MACRXTXSR_NCARR                           ETH_MACRXTXSR_NCARR_Msk  /* No Carrier */

+#define ETH_MACRXTXSR_TJT_Pos                         (0U)

+#define ETH_MACRXTXSR_TJT_Msk                         (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */

+#define ETH_MACRXTXSR_TJT                             ETH_MACRXTXSR_TJT_Msk    /* Transmit Jabber Timeout */

+

+/* Bit definition for Ethernet MAC PMT Control Status Register */

+#define ETH_MACPCSR_RWKFILTRST_Pos                    (31U)

+#define ETH_MACPCSR_RWKFILTRST_Msk                    (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */

+#define ETH_MACPCSR_RWKFILTRST                        ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */

+#define ETH_MACPCSR_RWKPTR_Pos                        (24U)

+#define ETH_MACPCSR_RWKPTR_Msk                        (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */

+#define ETH_MACPCSR_RWKPTR                            ETH_MACPCSR_RWKPTR_Msk   /* Remote Wake-up FIFO Pointer */

+#define ETH_MACPCSR_RWKPFE_Pos                        (10U)

+#define ETH_MACPCSR_RWKPFE_Msk                        (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */

+#define ETH_MACPCSR_RWKPFE                            ETH_MACPCSR_RWKPFE_Msk   /* Remote Wake-up Packet Forwarding Enable */

+#define ETH_MACPCSR_GLBLUCAST_Pos                     (9U)

+#define ETH_MACPCSR_GLBLUCAST_Msk                     (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */

+#define ETH_MACPCSR_GLBLUCAST                         ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */

+#define ETH_MACPCSR_RWKPRCVD_Pos                      (6U)

+#define ETH_MACPCSR_RWKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */

+#define ETH_MACPCSR_RWKPRCVD                          ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */

+#define ETH_MACPCSR_MGKPRCVD_Pos                      (5U)

+#define ETH_MACPCSR_MGKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */

+#define ETH_MACPCSR_MGKPRCVD                          ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */

+#define ETH_MACPCSR_RWKPKTEN_Pos                      (2U)

+#define ETH_MACPCSR_RWKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */

+#define ETH_MACPCSR_RWKPKTEN                          ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */

+#define ETH_MACPCSR_MGKPKTEN_Pos                      (1U)

+#define ETH_MACPCSR_MGKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */

+#define ETH_MACPCSR_MGKPKTEN                          ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */

+#define ETH_MACPCSR_PWRDWN_Pos                        (0U)

+#define ETH_MACPCSR_PWRDWN_Msk                        (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */

+#define ETH_MACPCSR_PWRDWN                            ETH_MACPCSR_PWRDWN_Msk   /* Power Down */

+

+/* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */

+#define ETH_MACRWUPFR_D_Pos                           (0U)

+#define ETH_MACRWUPFR_D_Msk                           (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACRWUPFR_D                               ETH_MACRWUPFR_D_Msk      /* Wake-up Packet filter register data */

+

+/* Bit definition for Ethernet MAC LPI Control Status Register */

+#define ETH_MACLCSR_LPITCSE_Pos                       (21U)

+#define ETH_MACLCSR_LPITCSE_Msk                       (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */

+#define ETH_MACLCSR_LPITCSE                           ETH_MACLCSR_LPITCSE_Msk  /* LPI Tx Clock Stop Enable */

+#define ETH_MACLCSR_LPITE_Pos                         (20U)

+#define ETH_MACLCSR_LPITE_Msk                         (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */

+#define ETH_MACLCSR_LPITE                             ETH_MACLCSR_LPITE_Msk    /* LPI Timer Enable */

+#define ETH_MACLCSR_LPITXA_Pos                        (19U)

+#define ETH_MACLCSR_LPITXA_Msk                        (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */

+#define ETH_MACLCSR_LPITXA                            ETH_MACLCSR_LPITXA_Msk   /* LPI Tx Automate */

+#define ETH_MACLCSR_PLS_Pos                           (17U)

+#define ETH_MACLCSR_PLS_Msk                           (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */

+#define ETH_MACLCSR_PLS                               ETH_MACLCSR_PLS_Msk      /* PHY Link Status */

+#define ETH_MACLCSR_LPIEN_Pos                         (16U)

+#define ETH_MACLCSR_LPIEN_Msk                         (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */

+#define ETH_MACLCSR_LPIEN                             ETH_MACLCSR_LPIEN_Msk    /* LPI Enable */

+#define ETH_MACLCSR_RLPIST_Pos                        (9U)

+#define ETH_MACLCSR_RLPIST_Msk                        (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */

+#define ETH_MACLCSR_RLPIST                            ETH_MACLCSR_RLPIST_Msk   /* Receive LPI State */

+#define ETH_MACLCSR_TLPIST_Pos                        (8U)

+#define ETH_MACLCSR_TLPIST_Msk                        (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */

+#define ETH_MACLCSR_TLPIST                            ETH_MACLCSR_TLPIST_Msk   /* Transmit LPI State */

+#define ETH_MACLCSR_RLPIEX_Pos                        (3U)

+#define ETH_MACLCSR_RLPIEX_Msk                        (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */

+#define ETH_MACLCSR_RLPIEX                            ETH_MACLCSR_RLPIEX_Msk   /* Receive LPI Exit */

+#define ETH_MACLCSR_RLPIEN_Pos                        (2U)

+#define ETH_MACLCSR_RLPIEN_Msk                        (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */

+#define ETH_MACLCSR_RLPIEN                            ETH_MACLCSR_RLPIEN_Msk   /* Receive LPI Entry */

+#define ETH_MACLCSR_TLPIEX_Pos                        (1U)

+#define ETH_MACLCSR_TLPIEX_Msk                        (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */

+#define ETH_MACLCSR_TLPIEX                            ETH_MACLCSR_TLPIEX_Msk   /* Transmit LPI Exit */

+#define ETH_MACLCSR_TLPIEN_Pos                        (0U)

+#define ETH_MACLCSR_TLPIEN_Msk                        (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */

+#define ETH_MACLCSR_TLPIEN                            ETH_MACLCSR_TLPIEN_Msk   /* Transmit LPI Entry */

+

+/* Bit definition for Ethernet MAC LPI Timers Control Register */

+#define ETH_MACLTCR_LST_Pos                           (16U)

+#define ETH_MACLTCR_LST_Msk                           (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */

+#define ETH_MACLTCR_LST                               ETH_MACLTCR_LST_Msk      /* LPI LS TIMER */

+#define ETH_MACLTCR_TWT_Pos                           (0U)

+#define ETH_MACLTCR_TWT_Msk                           (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACLTCR_TWT                               ETH_MACLTCR_TWT_Msk      /* LPI TW TIMER */

+

+/* Bit definition for Ethernet MAC LPI Entry Timer Register */

+#define ETH_MACLETR_LPIET_Pos                         (0U)

+#define ETH_MACLETR_LPIET_Msk                         (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */

+#define ETH_MACLETR_LPIET                             ETH_MACLETR_LPIET_Msk    /* LPI Entry Timer */

+

+/* Bit definition for Ethernet MAC 1US Tic Counter Register */

+#define ETH_MAC1USTCR_TIC1USCNTR_Pos                  (0U)

+#define ETH_MAC1USTCR_TIC1USCNTR_Msk                  (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */

+#define ETH_MAC1USTCR_TIC1USCNTR                      ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */

+

+/* Bit definition for Ethernet MAC Version Register */

+#define ETH_MACVR_USERVER_Pos                         (8U)

+#define ETH_MACVR_USERVER_Msk                         (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */

+#define ETH_MACVR_USERVER                             ETH_MACVR_USERVER_Msk    /* User-defined Version */

+#define ETH_MACVR_SNPSVER_Pos                         (0U)

+#define ETH_MACVR_SNPSVER_Msk                         (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */

+#define ETH_MACVR_SNPSVER                             ETH_MACVR_SNPSVER_Msk    /* Synopsys-defined Version */

+

+/* Bit definition for Ethernet MAC Debug Register */

+#define ETH_MACDR_TFCSTS_Pos                          (17U)

+#define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */

+#define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */

+#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */

+#define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)

+#define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */

+#define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */

+#define ETH_MACDR_TFCSTS_GENERATEPCP_Pos              (18U)

+#define ETH_MACDR_TFCSTS_GENERATEPCP_Msk              (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */

+#define ETH_MACDR_TFCSTS_GENERATEPCP                  ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */

+#define ETH_MACDR_TFCSTS_TRASFERIP_Pos                (17U)

+#define ETH_MACDR_TFCSTS_TRASFERIP_Msk                (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */

+#define ETH_MACDR_TFCSTS_TRASFERIP                    ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */

+#define ETH_MACDR_TPESTS_Pos                          (16U)

+#define ETH_MACDR_TPESTS_Msk                          (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */

+#define ETH_MACDR_TPESTS                              ETH_MACDR_TPESTS_Msk     /* MAC Receive Packet Controller FIFO Status */

+#define ETH_MACDR_RFCFCSTS_Pos                        (1U)

+#define ETH_MACDR_RFCFCSTS_Msk                        (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */

+#define ETH_MACDR_RFCFCSTS                            ETH_MACDR_RFCFCSTS_Msk   /* MAC MII Transmit Protocol Engine Status */

+#define ETH_MACDR_RPESTS_Pos                          (0U)

+#define ETH_MACDR_RPESTS_Msk                          (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */

+#define ETH_MACDR_RPESTS                              ETH_MACDR_RPESTS_Msk     /* MAC MII Receive Protocol Engine Status */

+

+/* Bit definition for Ethernet MAC HW Feature0 Register */

+#define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)

+#define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */

+#define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */

+#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */

+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)

+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */

+#define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */

+#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos             (28U)

+#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk             (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos) /*!< 0x70000000 */

+#define ETH_MACHWF0R_ACTPHYSEL_REVMII                 ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */

+#define ETH_MACHWF0R_SAVLANINS_Pos                    (27U)

+#define ETH_MACHWF0R_SAVLANINS_Msk                    (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */

+#define ETH_MACHWF0R_SAVLANINS                        ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */

+#define ETH_MACHWF0R_TSSTSSEL_Pos                     (25U)

+#define ETH_MACHWF0R_TSSTSSEL_Msk                     (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */

+#define ETH_MACHWF0R_TSSTSSEL                         ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */

+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos            (25U)

+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */

+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL                ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */

+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos            (26U)

+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */

+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL                ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */

+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos                (25U)

+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk                (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */

+#define ETH_MACHWF0R_TSSTSSEL_BOTH                    ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */

+#define ETH_MACHWF0R_MACADR64SEL_Pos                  (24U)

+#define ETH_MACHWF0R_MACADR64SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */

+#define ETH_MACHWF0R_MACADR64SEL                      ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */

+#define ETH_MACHWF0R_MACADR32SEL_Pos                  (23U)

+#define ETH_MACHWF0R_MACADR32SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */

+#define ETH_MACHWF0R_MACADR32SEL                      ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */

+#define ETH_MACHWF0R_ADDMACADRSEL_Pos                 (18U)

+#define ETH_MACHWF0R_ADDMACADRSEL_Msk                 (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */

+#define ETH_MACHWF0R_ADDMACADRSEL                     ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */

+#define ETH_MACHWF0R_RXCOESEL_Pos                     (16U)

+#define ETH_MACHWF0R_RXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */

+#define ETH_MACHWF0R_RXCOESEL                         ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */

+#define ETH_MACHWF0R_TXCOESEL_Pos                     (14U)

+#define ETH_MACHWF0R_TXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */

+#define ETH_MACHWF0R_TXCOESEL                         ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */

+#define ETH_MACHWF0R_EEESEL_Pos                       (13U)

+#define ETH_MACHWF0R_EEESEL_Msk                       (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */

+#define ETH_MACHWF0R_EEESEL                           ETH_MACHWF0R_EEESEL_Msk  /* Energy Efficient Ethernet Enabled */

+#define ETH_MACHWF0R_TSSEL_Pos                        (12U)

+#define ETH_MACHWF0R_TSSEL_Msk                        (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */

+#define ETH_MACHWF0R_TSSEL                            ETH_MACHWF0R_TSSEL_Msk   /* IEEE 1588-2008 Timestamp Enabled */

+#define ETH_MACHWF0R_ARPOFFSEL_Pos                    (9U)

+#define ETH_MACHWF0R_ARPOFFSEL_Msk                    (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */

+#define ETH_MACHWF0R_ARPOFFSEL                        ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */

+#define ETH_MACHWF0R_MMCSEL_Pos                       (8U)

+#define ETH_MACHWF0R_MMCSEL_Msk                       (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */

+#define ETH_MACHWF0R_MMCSEL                           ETH_MACHWF0R_MMCSEL_Msk  /* RMON Module Enable */

+#define ETH_MACHWF0R_MGKSEL_Pos                       (7U)

+#define ETH_MACHWF0R_MGKSEL_Msk                       (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */

+#define ETH_MACHWF0R_MGKSEL                           ETH_MACHWF0R_MGKSEL_Msk  /* PMT Magic Packet Enable */

+#define ETH_MACHWF0R_RWKSEL_Pos                       (6U)

+#define ETH_MACHWF0R_RWKSEL_Msk                       (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */

+#define ETH_MACHWF0R_RWKSEL                           ETH_MACHWF0R_RWKSEL_Msk  /* PMT Remote Wake-up Packet Enable */

+#define ETH_MACHWF0R_SMASEL_Pos                       (5U)

+#define ETH_MACHWF0R_SMASEL_Msk                       (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */

+#define ETH_MACHWF0R_SMASEL                           ETH_MACHWF0R_SMASEL_Msk  /* SMA (MDIO) Interface */

+#define ETH_MACHWF0R_VLHASH_Pos                       (4U)

+#define ETH_MACHWF0R_VLHASH_Msk                       (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */

+#define ETH_MACHWF0R_VLHASH                           ETH_MACHWF0R_VLHASH_Msk  /* VLAN Hash Filter Selected */

+#define ETH_MACHWF0R_PCSSEL_Pos                       (3U)

+#define ETH_MACHWF0R_PCSSEL_Msk                       (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */

+#define ETH_MACHWF0R_PCSSEL                           ETH_MACHWF0R_PCSSEL_Msk  /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */

+#define ETH_MACHWF0R_HDSEL_Pos                        (2U)

+#define ETH_MACHWF0R_HDSEL_Msk                        (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */

+#define ETH_MACHWF0R_HDSEL                            ETH_MACHWF0R_HDSEL_Msk   /* Half-duplex Support */

+#define ETH_MACHWF0R_GMIISEL_Pos                      (1U)

+#define ETH_MACHWF0R_GMIISEL_Msk                      (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */

+#define ETH_MACHWF0R_GMIISEL                          ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */

+#define ETH_MACHWF0R_MIISEL_Pos                       (0U)

+#define ETH_MACHWF0R_MIISEL_Msk                       (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */

+#define ETH_MACHWF0R_MIISEL                           ETH_MACHWF0R_MIISEL_Msk  /* 10 or 100 Mbps Support */

+

+/* Bit definition for Ethernet MAC HW Feature1 Register */

+#define ETH_MACHWF1R_L3L4FNUM_Pos                     (27U)

+#define ETH_MACHWF1R_L3L4FNUM_Msk                     (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */

+#define ETH_MACHWF1R_L3L4FNUM                         ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */

+#define ETH_MACHWF1R_HASHTBLSZ_Pos                    (24U)

+#define ETH_MACHWF1R_HASHTBLSZ_Msk                    (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */

+#define ETH_MACHWF1R_HASHTBLSZ                        ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */

+#define ETH_MACHWF1R_AVSEL_Pos                        (20U)

+#define ETH_MACHWF1R_AVSEL_Msk                        (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */

+#define ETH_MACHWF1R_AVSEL                            ETH_MACHWF1R_AVSEL_Msk   /* AV Feature Enabled */

+#define ETH_MACHWF1R_DBGMEMA_Pos                      (19U)

+#define ETH_MACHWF1R_DBGMEMA_Msk                      (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */

+#define ETH_MACHWF1R_DBGMEMA                          ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */

+#define ETH_MACHWF1R_TSOEN_Pos                        (18U)

+#define ETH_MACHWF1R_TSOEN_Msk                        (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */

+#define ETH_MACHWF1R_TSOEN                            ETH_MACHWF1R_TSOEN_Msk   /* TCP Segmentation Offload Enable */

+#define ETH_MACHWF1R_SPHEN_Pos                        (17U)

+#define ETH_MACHWF1R_SPHEN_Msk                        (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */

+#define ETH_MACHWF1R_SPHEN                            ETH_MACHWF1R_SPHEN_Msk   /* Split Header Feature Enable */

+#define ETH_MACHWF1R_DCBEN_Pos                        (16U)

+#define ETH_MACHWF1R_DCBEN_Msk                        (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */

+#define ETH_MACHWF1R_DCBEN                            ETH_MACHWF1R_DCBEN_Msk   /* DCB Feature Enable */

+#define ETH_MACHWF1R_ADDR64_Pos                       (14U)

+#define ETH_MACHWF1R_ADDR64_Msk                       (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */

+#define ETH_MACHWF1R_ADDR64                           ETH_MACHWF1R_ADDR64_Msk  /* Address Width */

+#define ETH_MACHWF1R_ADDR64_32                        (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */

+#define ETH_MACHWF1R_ADDR64_40                        (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */

+#define ETH_MACHWF1R_ADDR64_48                        (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */

+#define ETH_MACHWF1R_ADVTHWORD_Pos                    (13U)

+#define ETH_MACHWF1R_ADVTHWORD_Msk                    (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */

+#define ETH_MACHWF1R_ADVTHWORD                        ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */

+#define ETH_MACHWF1R_PTOEN_Pos                        (12U)

+#define ETH_MACHWF1R_PTOEN_Msk                        (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */

+#define ETH_MACHWF1R_PTOEN                            ETH_MACHWF1R_PTOEN_Msk   /* PTP Offload Enable */

+#define ETH_MACHWF1R_OSTEN_Pos                        (11U)

+#define ETH_MACHWF1R_OSTEN_Msk                        (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */

+#define ETH_MACHWF1R_OSTEN                            ETH_MACHWF1R_OSTEN_Msk   /* One-Step Timestamping Enable */

+#define ETH_MACHWF1R_TXFIFOSIZE_Pos                   (6U)

+#define ETH_MACHWF1R_TXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */

+#define ETH_MACHWF1R_TXFIFOSIZE                       ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */

+#define ETH_MACHWF1R_RXFIFOSIZE_Pos                   (0U)

+#define ETH_MACHWF1R_RXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */

+#define ETH_MACHWF1R_RXFIFOSIZE                       ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */

+

+/* Bit definition for Ethernet MAC HW Feature2 Register */

+#define ETH_MACHWF2R_AUXSNAPNUM_Pos                   (28U)

+#define ETH_MACHWF2R_AUXSNAPNUM_Msk                   (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */

+#define ETH_MACHWF2R_AUXSNAPNUM                       ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */

+#define ETH_MACHWF2R_PPSOUTNUM_Pos                    (24U)

+#define ETH_MACHWF2R_PPSOUTNUM_Msk                    (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */

+#define ETH_MACHWF2R_PPSOUTNUM                        ETH_MACHWF2R_PPSOUTNUM_Msk /*  Number of PPS Outputs */

+#define ETH_MACHWF2R_TXCHCNT_Pos                      (18U)

+#define ETH_MACHWF2R_TXCHCNT_Msk                      (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */

+#define ETH_MACHWF2R_TXCHCNT                          ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */

+#define ETH_MACHWF2R_RXCHCNT_Pos                      (13U)

+#define ETH_MACHWF2R_RXCHCNT_Msk                      (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000E000 */

+#define ETH_MACHWF2R_RXCHCNT                          ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */

+#define ETH_MACHWF2R_TXQCNT_Pos                       (6U)

+#define ETH_MACHWF2R_TXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */

+#define ETH_MACHWF2R_TXQCNT                           ETH_MACHWF2R_TXQCNT_Msk  /* Number of MTL Transmit Queues */

+#define ETH_MACHWF2R_RXQCNT_Pos                       (0U)

+#define ETH_MACHWF2R_RXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */

+#define ETH_MACHWF2R_RXQCNT                           ETH_MACHWF2R_RXQCNT_Msk  /* Number of MTL Receive Queues */

+

+/* Bit definition for Ethernet MAC MDIO Address Register */

+#define ETH_MACMDIOAR_PSE_Pos                         (27U)

+#define ETH_MACMDIOAR_PSE_Msk                         (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */

+#define ETH_MACMDIOAR_PSE                             ETH_MACMDIOAR_PSE_Msk    /* Preamble Suppression Enable */

+#define ETH_MACMDIOAR_BTB_Pos                         (26U)

+#define ETH_MACMDIOAR_BTB_Msk                         (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */

+#define ETH_MACMDIOAR_BTB                             ETH_MACMDIOAR_BTB_Msk    /* Back to Back transactions */

+#define ETH_MACMDIOAR_PA_Pos                          (21U)

+#define ETH_MACMDIOAR_PA_Msk                          (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */

+#define ETH_MACMDIOAR_PA                              ETH_MACMDIOAR_PA_Msk     /* Physical Layer Address */

+#define ETH_MACMDIOAR_RDA_Pos                         (16U)

+#define ETH_MACMDIOAR_RDA_Msk                         (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */

+#define ETH_MACMDIOAR_RDA                             ETH_MACMDIOAR_RDA_Msk    /* Register/Device Address */

+#define ETH_MACMDIOAR_NTC_Pos                         (12U)

+#define ETH_MACMDIOAR_NTC_Msk                         (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */

+#define ETH_MACMDIOAR_NTC                             ETH_MACMDIOAR_NTC_Msk    /* Number of Trailing Clocks */

+#define ETH_MACMDIOAR_CR_Pos                          (8U)

+#define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */

+#define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */

+#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */

+#define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)

+#define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */

+#define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */

+#define ETH_MACMDIOAR_CR_DIV16_Pos                    (9U)

+#define ETH_MACMDIOAR_CR_DIV16_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */

+#define ETH_MACMDIOAR_CR_DIV16                        ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */

+#define ETH_MACMDIOAR_CR_DIV26_Pos                    (8U)

+#define ETH_MACMDIOAR_CR_DIV26_Msk                    (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */

+#define ETH_MACMDIOAR_CR_DIV26                        ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */

+#define ETH_MACMDIOAR_CR_DIV102_Pos                   (10U)

+#define ETH_MACMDIOAR_CR_DIV102_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */

+#define ETH_MACMDIOAR_CR_DIV102                       ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */

+#define ETH_MACMDIOAR_CR_DIV124_Pos                   (8U)

+#define ETH_MACMDIOAR_CR_DIV124_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */

+#define ETH_MACMDIOAR_CR_DIV124                       ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */

+#define ETH_MACMDIOAR_CR_DIV4AR_Pos                   (11U)

+#define ETH_MACMDIOAR_CR_DIV4AR_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */

+#define ETH_MACMDIOAR_CR_DIV4AR                       ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV6AR_Pos                   (8U)

+#define ETH_MACMDIOAR_CR_DIV6AR_Msk                   (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */

+#define ETH_MACMDIOAR_CR_DIV6AR                       ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV8AR_Pos                   (9U)

+#define ETH_MACMDIOAR_CR_DIV8AR_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */

+#define ETH_MACMDIOAR_CR_DIV8AR                       ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV10AR_Pos                  (8U)

+#define ETH_MACMDIOAR_CR_DIV10AR_Msk                  (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */

+#define ETH_MACMDIOAR_CR_DIV10AR                      ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV12AR_Pos                  (10U)

+#define ETH_MACMDIOAR_CR_DIV12AR_Msk                  (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */

+#define ETH_MACMDIOAR_CR_DIV12AR                      ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV14AR_Pos                  (8U)

+#define ETH_MACMDIOAR_CR_DIV14AR_Msk                  (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */

+#define ETH_MACMDIOAR_CR_DIV14AR                      ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV16AR_Pos                  (9U)

+#define ETH_MACMDIOAR_CR_DIV16AR_Msk                  (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */

+#define ETH_MACMDIOAR_CR_DIV16AR                      ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV18AR_Pos                  (8U)

+#define ETH_MACMDIOAR_CR_DIV18AR_Msk                  (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */

+#define ETH_MACMDIOAR_CR_DIV18AR                      ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_SKAP_Pos                        (4U)

+#define ETH_MACMDIOAR_SKAP_Msk                        (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */

+#define ETH_MACMDIOAR_SKAP                            ETH_MACMDIOAR_SKAP_Msk   /* Skip Address Packet */

+#define ETH_MACMDIOAR_MOC_Pos                         (2U)

+#define ETH_MACMDIOAR_MOC_Msk                         (0x3UL << ETH_MACMDIOAR_MOC_Pos) /*!< 0x0000000C */

+#define ETH_MACMDIOAR_MOC                             ETH_MACMDIOAR_MOC_Msk    /* MII Operation Command */

+#define ETH_MACMDIOAR_MOC_WR_Pos                      (2U)

+#define ETH_MACMDIOAR_MOC_WR_Msk                      (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos) /*!< 0x00000004 */

+#define ETH_MACMDIOAR_MOC_WR                          ETH_MACMDIOAR_MOC_WR_Msk /* Write */

+#define ETH_MACMDIOAR_MOC_PRDIA_Pos                   (3U)

+#define ETH_MACMDIOAR_MOC_PRDIA_Msk                   (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos) /*!< 0x00000008 */

+#define ETH_MACMDIOAR_MOC_PRDIA                       ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */

+#define ETH_MACMDIOAR_MOC_RD_Pos                      (2U)

+#define ETH_MACMDIOAR_MOC_RD_Msk                      (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos) /*!< 0x0000000C */

+#define ETH_MACMDIOAR_MOC_RD                          ETH_MACMDIOAR_MOC_RD_Msk /* Read */

+#define ETH_MACMDIOAR_C45E_Pos                        (1U)

+#define ETH_MACMDIOAR_C45E_Msk                        (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */

+#define ETH_MACMDIOAR_C45E                            ETH_MACMDIOAR_C45E_Msk   /* Clause 45 PHY Enable */

+#define ETH_MACMDIOAR_MB_Pos                          (0U)

+#define ETH_MACMDIOAR_MB_Msk                          (0x1UL << ETH_MACMDIOAR_MB_Pos) /*!< 0x00000001 */

+#define ETH_MACMDIOAR_MB                              ETH_MACMDIOAR_MB_Msk     /* MII Busy */

+

+/* Bit definition for Ethernet MAC MDIO Data Register */

+#define ETH_MACMDIODR_RA_Pos                          (16U)

+#define ETH_MACMDIODR_RA_Msk                          (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */

+#define ETH_MACMDIODR_RA                              ETH_MACMDIODR_RA_Msk     /* Register Address */

+#define ETH_MACMDIODR_MD_Pos                          (0U)

+#define ETH_MACMDIODR_MD_Msk                          (0xFFFFUL << ETH_MACMDIODR_MD_Pos) /*!< 0x0000FFFF */

+#define ETH_MACMDIODR_MD                              ETH_MACMDIODR_MD_Msk     /* MII Data */

+

+/* Bit definition for Ethernet ARP Address Register */

+#define ETH_MACARPAR_ARPPA_Pos                         (0U)

+#define ETH_MACARPAR_ARPPA_Msk                         (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACARPAR_ARPPA                             ETH_MACARPAR_ARPPA_Msk     /* ARP Protocol Address */

+

+/* Bit definition for Ethernet MAC Address 0 High Register */

+#define ETH_MACA0HR_AE_Pos                            (31U)

+#define ETH_MACA0HR_AE_Msk                            (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA0HR_AE                                ETH_MACA0HR_AE_Msk /* Address Enable*/

+#define ETH_MACA0HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA0HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA0HR_ADDRHI                            ETH_MACA0HR_ADDRHI_Msk   /* MAC Address 0*/

+

+/* Bit definition for Ethernet MAC Address 0 Low Register */

+#define ETH_MACA0LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA0LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA0LR_ADDRLO                            ETH_MACA0LR_ADDRLO_Msk   /* MAC Address 0*/

+

+/* Bit definition for Ethernet MAC Address 1 High Register */

+#define ETH_MACA1HR_AE_Pos                            (31U)

+#define ETH_MACA1HR_AE_Msk                            (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk /* Address Enable*/

+#define ETH_MACA1HR_SA_Pos                            (30U)

+#define ETH_MACA1HR_SA_Msk                            (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk /* Source Address */

+#define ETH_MACA1HR_MBC_Pos                           (24U)

+#define ETH_MACA1HR_MBC_Msk                           (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk /* Mask Byte Control */

+#define ETH_MACA1HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA1HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA1HR_ADDRHI                            ETH_MACA1HR_ADDRHI_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 1 Low Register */

+#define ETH_MACA1LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA1LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA1LR_ADDRLO                            ETH_MACA1LR_ADDRLO_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 2 High Register */

+#define ETH_MACA2HR_AE_Pos                            (31U)

+#define ETH_MACA2HR_AE_Msk                            (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk /* Address Enable*/

+#define ETH_MACA2HR_SA_Pos                            (30U)

+#define ETH_MACA2HR_SA_Msk                            (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk /* Source Address */

+#define ETH_MACA2HR_MBC_Pos                           (24U)

+#define ETH_MACA2HR_MBC_Msk                           (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk /* Mask Byte Control */

+#define ETH_MACA2HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA2HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA2HR_ADDRHI                            ETH_MACA2HR_ADDRHI_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 2 Low Register */

+#define ETH_MACA2LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA2LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA2LR_ADDRLO                            ETH_MACA2LR_ADDRLO_Msk   /* MAC Address 2*/

+

+/* Bit definition for Ethernet MAC Address 3 High Register */

+#define ETH_MACA3HR_AE_Pos                            (31U)

+#define ETH_MACA3HR_AE_Msk                            (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk /* Address Enable*/

+#define ETH_MACA3HR_SA_Pos                            (30U)

+#define ETH_MACA3HR_SA_Msk                            (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk /* Source Address */

+#define ETH_MACA3HR_MBC_Pos                           (24U)

+#define ETH_MACA3HR_MBC_Msk                           (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk /* Mask Byte Control */

+#define ETH_MACA3HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA3HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA3HR_ADDRHI                            ETH_MACA3HR_ADDRHI_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 3 Low Register */

+#define ETH_MACA3LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA3LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA3LR_ADDRLO                            ETH_MACA3LR_ADDRLO_Msk   /* MAC Address 3*/

+

+/* Bit definition for Ethernet MAC Address High Register */

+#define ETH_MACAHR_AE_Pos                             (31U)

+#define ETH_MACAHR_AE_Msk                             (0x1UL << ETH_MACAHR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACAHR_AE                                 ETH_MACAHR_AE_Msk        /* Address enable */

+#define ETH_MACAHR_SA_Pos                             (30U)

+#define ETH_MACAHR_SA_Msk                             (0x1UL << ETH_MACAHR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACAHR_SA                                 ETH_MACAHR_SA_Msk        /* Source address */

+#define ETH_MACAHR_MBC_Pos                            (24U)

+#define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */

+#define ETH_MACAHR_MBC_HBITS15_8                      ((uint32_t)0x20000000)   /* Mask MAC Address high reg bits [15:8] */

+#define ETH_MACAHR_MBC_HBITS7_0                       ((uint32_t)0x10000000)   /* Mask MAC Address high reg bits [7:0] */

+#define ETH_MACAHR_MBC_LBITS31_24                     ((uint32_t)0x08000000)   /* Mask MAC Address low reg bits [31:24] */

+#define ETH_MACAHR_MBC_LBITS23_16                     ((uint32_t)0x04000000)   /* Mask MAC Address low reg bits [23:16] */

+#define ETH_MACAHR_MBC_LBITS15_8                      ((uint32_t)0x02000000)   /* Mask MAC Address low reg bits [15:8] */

+#define ETH_MACAHR_MBC_LBITS7_0                       ((uint32_t)0x01000000)   /* Mask MAC Address low reg bits [7:0] */

+#define ETH_MACAHR_MACAH_Pos                          (0U)

+#define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */

+#define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */

+

+/* Bit definition for Ethernet MAC Address Low Register */

+#define ETH_MACALR_MACAL_Pos                          (0U)

+#define ETH_MACALR_MACAL_Msk                          (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACALR_MACAL                              ETH_MACALR_MACAL_Msk     /* MAC address low */

+

+/* Bit definition for Ethernet MMC Control Register */

+#define ETH_MMCCR_UCDBC_Pos                           (8U)

+#define ETH_MMCCR_UCDBC_Msk                           (0x1UL << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */

+#define ETH_MMCCR_UCDBC                               ETH_MMCCR_UCDBC_Msk  /* Update MMC Counters for Dropped Broadcast Packets */

+#define ETH_MMCCR_CNTPRSTLVL_Pos                      (5U)

+#define ETH_MMCCR_CNTPRSTLVL_Msk                      (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */

+#define ETH_MMCCR_CNTPRSTLVL                          ETH_MMCCR_CNTPRSTLVL_Msk  /* Full-Half Preset */

+#define ETH_MMCCR_CNTPRST_Pos                         (4U)

+#define ETH_MMCCR_CNTPRST_Msk                         (0x1UL << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */

+#define ETH_MMCCR_CNTPRST                             ETH_MMCCR_CNTPRST_Msk  /* Counters Reset */

+#define ETH_MMCCR_CNTFREEZ_Pos                        (3U)

+#define ETH_MMCCR_CNTFREEZ_Msk                        (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */

+#define ETH_MMCCR_CNTFREEZ                            ETH_MMCCR_CNTFREEZ_Msk  /* MMC Counter Freeze */

+#define ETH_MMCCR_RSTONRD_Pos                         (2U)

+#define ETH_MMCCR_RSTONRD_Msk                         (0x1UL << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */

+#define ETH_MMCCR_RSTONRD                             ETH_MMCCR_RSTONRD_Msk  /* Reset On Read */

+#define ETH_MMCCR_CNTSTOPRO_Pos                       (1U)

+#define ETH_MMCCR_CNTSTOPRO_Msk                       (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */

+#define ETH_MMCCR_CNTSTOPRO                           ETH_MMCCR_CNTSTOPRO_Msk  /* Counter Stop Rollover */

+#define ETH_MMCCR_CNTRST_Pos                          (0U)

+#define ETH_MMCCR_CNTRST_Msk                          (0x1UL << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */

+#define ETH_MMCCR_CNTRST                              ETH_MMCCR_CNTRST_Msk  /* Counters Reset */

+

+/* Bit definition for Ethernet MMC Rx Interrupt Register */

+#define ETH_MMCRIR_RXLPITRCIS_Pos                     (27U)

+#define ETH_MMCRIR_RXLPITRCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) /*!< 0x08000000 */

+#define ETH_MMCRIR_RXLPITRCIS                         ETH_MMCRIR_RXLPITRCIS_Msk  /* MMC Receive LPI transition counter interrupt status */

+#define ETH_MMCRIR_RXLPIUSCIS_Pos                     (26U)

+#define ETH_MMCRIR_RXLPIUSCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */

+#define ETH_MMCRIR_RXLPIUSCIS                         ETH_MMCRIR_RXLPIUSCIS_Msk  /* MMC Receive LPI microsecond counter interrupt status */

+#define ETH_MMCRIR_RXUCGPIS_Pos                       (17U)

+#define ETH_MMCRIR_RXUCGPIS_Msk                       (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) /*!< 0x00020000 */

+#define ETH_MMCRIR_RXUCGPIS                           ETH_MMCRIR_RXUCGPIS_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Status */

+#define ETH_MMCRIR_RXALGNERPIS_Pos                    (6U)

+#define ETH_MMCRIR_RXALGNERPIS_Msk                    (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) /*!< 0x00000040 */

+#define ETH_MMCRIR_RXALGNERPIS                        ETH_MMCRIR_RXALGNERPIS_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Status */

+#define ETH_MMCRIR_RXCRCERPIS_Pos                     (5U)

+#define ETH_MMCRIR_RXCRCERPIS_Msk                     (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) /*!< 0x00000020 */

+#define ETH_MMCRIR_RXCRCERPIS                         ETH_MMCRIR_RXCRCERPIS_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Status */

+

+/* Bit definition for Ethernet MMC Tx Interrupt Register */

+#define ETH_MMCTIR_TXLPITRCIS_Pos                     (27U)

+#define ETH_MMCTIR_TXLPITRCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) /*!< 0x08000000 */

+#define ETH_MMCTIR_TXLPITRCIS                         ETH_MMCTIR_TXLPITRCIS_Msk  /* MMC Transmit LPI transition counter interrupt status */

+#define ETH_MMCTIR_TXLPIUSCIS_Pos                     (26U)

+#define ETH_MMCTIR_TXLPIUSCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */

+#define ETH_MMCTIR_TXLPIUSCIS                         ETH_MMCTIR_TXLPIUSCIS_Msk  /* MMC Transmit LPI microsecond counter interrupt status */

+#define ETH_MMCTIR_TXGPKTIS_Pos                       (21U)

+#define ETH_MMCTIR_TXGPKTIS_Msk                       (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) /*!< 0x00200000 */

+#define ETH_MMCTIR_TXGPKTIS                           ETH_MMCTIR_TXGPKTIS_Msk  /* MMC Transmit Good Packet Counter Interrupt Status */

+#define ETH_MMCTIR_TXMCOLGPIS_Pos                     (15U)

+#define ETH_MMCTIR_TXMCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */

+#define ETH_MMCTIR_TXMCOLGPIS                         ETH_MMCTIR_TXMCOLGPIS_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */

+#define ETH_MMCTIR_TXSCOLGPIS_Pos                     (14U)

+#define ETH_MMCTIR_TXSCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */

+#define ETH_MMCTIR_TXSCOLGPIS                         ETH_MMCTIR_TXSCOLGPIS_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */

+

+/* Bit definition for Ethernet MMC Rx interrupt Mask register */

+#define ETH_MMCRIMR_RXLPITRCIM_Pos                    (27U)

+#define ETH_MMCRIMR_RXLPITRCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */

+#define ETH_MMCRIMR_RXLPITRCIM                        ETH_MMCRIMR_RXLPITRCIM_Msk  /* MMC Receive LPI transition counter interrupt Mask */

+#define ETH_MMCRIMR_RXLPIUSCIM_Pos                    (26U)

+#define ETH_MMCRIMR_RXLPIUSCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */

+#define ETH_MMCRIMR_RXLPIUSCIM                        ETH_MMCRIMR_RXLPIUSCIM_Msk  /* MMC Receive LPI microsecond counter interrupt Mask */

+#define ETH_MMCRIMR_RXUCGPIM_Pos                      (17U)

+#define ETH_MMCRIMR_RXUCGPIM_Msk                      (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) /*!< 0x00020000 */

+#define ETH_MMCRIMR_RXUCGPIM                          ETH_MMCRIMR_RXUCGPIM_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Mask */

+#define ETH_MMCRIMR_RXALGNERPIM_Pos                   (6U)

+#define ETH_MMCRIMR_RXALGNERPIM_Msk                   (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */

+#define ETH_MMCRIMR_RXALGNERPIM                       ETH_MMCRIMR_RXALGNERPIM_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Mask */

+#define ETH_MMCRIMR_RXCRCERPIM_Pos                    (5U)

+#define ETH_MMCRIMR_RXCRCERPIM_Msk                    (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */

+#define ETH_MMCRIMR_RXCRCERPIM                        ETH_MMCRIMR_RXCRCERPIM_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Mask */

+

+/* Bit definition for Ethernet MMC Tx Interrupt Mask Register */

+#define ETH_MMCTIMR_TXLPITRCIM_Pos                    (27U)

+#define ETH_MMCTIMR_TXLPITRCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */

+#define ETH_MMCTIMR_TXLPITRCIM                        ETH_MMCTIMR_TXLPITRCIM_Msk  /* MMC Transmit LPI transition counter interrupt Mask*/

+#define ETH_MMCTIMR_TXLPIUSCIM_Pos                    (26U)

+#define ETH_MMCTIMR_TXLPIUSCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */

+#define ETH_MMCTIMR_TXLPIUSCIM                        ETH_MMCTIMR_TXLPIUSCIM_Msk  /* MMC Transmit LPI microsecond counter interrupt Mask*/

+#define ETH_MMCTIMR_TXGPKTIM_Pos                      (21U)

+#define ETH_MMCTIMR_TXGPKTIM_Msk                      (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) /*!< 0x00200000 */

+#define ETH_MMCTIMR_TXGPKTIM                          ETH_MMCTIMR_TXGPKTIM_Msk  /* MMC Transmit Good Packet Counter Interrupt Mask*/

+#define ETH_MMCTIMR_TXMCOLGPIM_Pos                    (15U)

+#define ETH_MMCTIMR_TXMCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */

+#define ETH_MMCTIMR_TXMCOLGPIM                        ETH_MMCTIMR_TXMCOLGPIM_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */

+#define ETH_MMCTIMR_TXSCOLGPIM_Pos                    (14U)

+#define ETH_MMCTIMR_TXSCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */

+#define ETH_MMCTIMR_TXSCOLGPIM                        ETH_MMCTIMR_TXSCOLGPIM_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */

+

+/* Bit definition for Ethernet MMC Tx Single Collision Good Packets Register */

+#define ETH_MMCTSCGPR_TXSNGLCOLG_Pos                  (0U)

+#define ETH_MMCTSCGPR_TXSNGLCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTSCGPR_TXSNGLCOLG                      ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */

+

+/* Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register */

+#define ETH_MMCTMCGPR_TXMULTCOLG_Pos                  (0U)

+#define ETH_MMCTMCGPR_TXMULTCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTMCGPR_TXMULTCOLG                      ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */

+

+/* Bit definition for Ethernet MMC Tx Packet Count Good Register */

+#define ETH_MMCTPCGR_TXPKTG_Pos                       (0U)

+#define ETH_MMCTPCGR_TXPKTG_msk                       (0xFFFFFFFFUL <<  ETH_MMCTPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTPCGR_TXPKTG                           ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */

+

+/* Bit definition for Ethernet MMC Rx CRC Error Packets Register */

+#define ETH_MMCRCRCEPR_RXCRCERR_Pos                   (0U)

+#define ETH_MMCRCRCEPR_RXCRCERR_msk                   (0xFFFFFFFFUL <<  ETH_MMCRCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRCRCEPR_RXCRCERR                       ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */

+

+/* Bit definition for Ethernet MMC Rx alignment error packets register */

+#define ETH_MMCRAEPR_RXALGNERR_Pos                    (0U)

+#define ETH_MMCRAEPR_RXALGNERR_msk                    (0xFFFFFFFFUL <<  ETH_MMCRAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRAEPR_RXALGNERR                        ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */

+

+/* Bit definition for Ethernet MMC Rx Unicast Packets Good Register */

+#define ETH_MMCRUPGR_RXUCASTG_Pos                     (0U)

+#define ETH_MMCRUPGR_RXUCASTG_msk                     (0xFFFFFFFFUL <<  ETH_MMCRUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRUPGR_RXUCASTG                         ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */

+

+/* Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register */

+#define ETH_MMCTLPIMSTR_TXLPIUSC_Pos                  (0U)

+#define ETH_MMCTLPIMSTR_TXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCTLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTLPIMSTR_TXLPIUSC                      ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */

+

+/* Bit definition for Ethernet MMC Tx LPI Transition Counter Register */

+#define ETH_MMCTLPITCR_TXLPITRC_Pos                   (0U)

+#define ETH_MMCTLPITCR_TXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCTLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTLPITCR_TXLPITRC                       ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */

+

+/* Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register */

+#define ETH_MMCRLPIMSTR_RXLPIUSC_Pos                  (0U)

+#define ETH_MMCRLPIMSTR_RXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCRLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRLPIMSTR_RXLPIUSC                      ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */

+

+/* Bit definition for Ethernet MMC Rx LPI Transition Counter Register */

+#define ETH_MMCRLPITCR_RXLPITRC_Pos                   (0U)

+#define ETH_MMCRLPITCR_RXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCRLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRLPITCR_RXLPITRC                       ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */

+

+/* Bit definition for Ethernet MAC L3 L4 Control Register */

+#define ETH_MACL3L4CR_L4DPIM_Pos                      (21U)

+#define ETH_MACL3L4CR_L4DPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos) /*!< 0x00200000 */

+#define ETH_MACL3L4CR_L4DPIM                          ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */

+#define ETH_MACL3L4CR_L4DPM_Pos                       (20U)

+#define ETH_MACL3L4CR_L4DPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4DPM_Pos) /*!< 0x00100000 */

+#define ETH_MACL3L4CR_L4DPM                           ETH_MACL3L4CR_L4DPM_Msk  /* Layer 4 Destination Port Match Enable */

+#define ETH_MACL3L4CR_L4SPIM_Pos                      (19U)

+#define ETH_MACL3L4CR_L4SPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos) /*!< 0x00080000 */

+#define ETH_MACL3L4CR_L4SPIM                          ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */

+#define ETH_MACL3L4CR_L4SPM_Pos                       (18U)

+#define ETH_MACL3L4CR_L4SPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4SPM_Pos) /*!< 0x00040000 */

+#define ETH_MACL3L4CR_L4SPM                           ETH_MACL3L4CR_L4SPM_Msk  /* Layer 4 Source Port Match Enable */

+#define ETH_MACL3L4CR_L4PEN_Pos                       (16U)

+#define ETH_MACL3L4CR_L4PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L4PEN_Pos) /*!< 0x00010000 */

+#define ETH_MACL3L4CR_L4PEN                           ETH_MACL3L4CR_L4PEN_Msk  /* Layer 4 Protocol Enable */

+#define ETH_MACL3L4CR_L3HDBM_Pos                      (11U)

+#define ETH_MACL3L4CR_L3HDBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos) /*!< 0x0000F800 */

+#define ETH_MACL3L4CR_L3HDBM                          ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */

+#define ETH_MACL3L4CR_L3HSBM_Pos                      (6U)

+#define ETH_MACL3L4CR_L3HSBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos) /*!< 0x000007C0 */

+#define ETH_MACL3L4CR_L3HSBM                          ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */

+#define ETH_MACL3L4CR_L3DAIM_Pos                      (5U)

+#define ETH_MACL3L4CR_L3DAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos) /*!< 0x00000020 */

+#define ETH_MACL3L4CR_L3DAIM                          ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */

+#define ETH_MACL3L4CR_L3DAM_Pos                       (4U)

+#define ETH_MACL3L4CR_L3DAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3DAM_Pos) /*!< 0x00000010 */

+#define ETH_MACL3L4CR_L3DAM                           ETH_MACL3L4CR_L3DAM_Msk  /* Layer 3 IP DA Match Enable */

+#define ETH_MACL3L4CR_L3SAIM_Pos                      (3U)

+#define ETH_MACL3L4CR_L3SAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos) /*!< 0x00000008 */

+#define ETH_MACL3L4CR_L3SAIM                          ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */

+#define ETH_MACL3L4CR_L3SAM_Pos                       (2U)

+#define ETH_MACL3L4CR_L3SAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3SAM_Pos) /*!< 0x00000004 */

+#define ETH_MACL3L4CR_L3SAM                           ETH_MACL3L4CR_L3SAM_Msk  /* Layer 3 IP SA Match Enable*/

+#define ETH_MACL3L4CR_L3PEN_Pos                       (0U)

+#define ETH_MACL3L4CR_L3PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L3PEN_Pos) /*!< 0x00000001 */

+#define ETH_MACL3L4CR_L3PEN                           ETH_MACL3L4CR_L3PEN_Msk  /* Layer 3 Protocol Enable */

+

+/* Bit definition for Ethernet MAC L4 Address Register */

+#define ETH_MACL4AR_L4DP_Pos                          (16U)

+#define ETH_MACL4AR_L4DP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4DP_Pos) /*!< 0xFFFF0000 */

+#define ETH_MACL4AR_L4DP                              ETH_MACL4AR_L4DP_Msk     /* Layer 4 Destination Port Number Field */

+#define ETH_MACL4AR_L4SP_Pos                          (0U)

+#define ETH_MACL4AR_L4SP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4SP_Pos) /*!< 0x0000FFFF */

+#define ETH_MACL4AR_L4SP                              ETH_MACL4AR_L4SP_Msk     /* Layer 4 Source Port Number Field */

+

+/* Bit definition for Ethernet MAC L3 Address0 Register */

+#define ETH_MACL3A0R_L3A0_Pos                         (0U)

+#define ETH_MACL3A0R_L3A0_Msk                         (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A0R_L3A0                             ETH_MACL3A0R_L3A0_Msk    /* Layer 3 Address 0 Field */

+

+/* Bit definition for Ethernet MAC L4 Address1 Register */

+#define ETH_MACL3A1R_L3A1_Pos                         (0U)

+#define ETH_MACL3A1R_L3A1_Msk                         (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A1R_L3A1                             ETH_MACL3A1R_L3A1_Msk    /* Layer 3 Address 1 Field */

+

+/* Bit definition for Ethernet MAC L4 Address2 Register */

+#define ETH_MACL3A2R_L3A2_Pos                         (0U)

+#define ETH_MACL3A2R_L3A2_Msk                         (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A2R_L3A2                             ETH_MACL3A2R_L3A2_Msk    /* Layer 3 Address 2 Field */

+

+/* Bit definition for Ethernet MAC L4 Address3 Register */

+#define ETH_MACL3A3R_L3A3_Pos                         (0U)

+#define ETH_MACL3A3R_L3A3_Msk                         (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A3R_L3A3                             ETH_MACL3A3R_L3A3_Msk    /* Layer 3 Address 3 Field */

+

+/* Bit definition for Ethernet MAC Timestamp Control Register */

+#define ETH_MACTSCR_TXTSSTSM_Pos                      (24U)

+#define ETH_MACTSCR_TXTSSTSM_Msk                      (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */

+#define ETH_MACTSCR_TXTSSTSM                          ETH_MACTSCR_TXTSSTSM_Msk  /* Transmit Timestamp Status Mode */

+#define ETH_MACTSCR_CSC_Pos                           (19U)

+#define ETH_MACTSCR_CSC_Msk                           (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */

+#define ETH_MACTSCR_CSC                               ETH_MACTSCR_CSC_Msk  /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */

+#define ETH_MACTSCR_TSENMACADDR_Pos                   (18U)

+#define ETH_MACTSCR_TSENMACADDR_Msk                   (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */

+#define ETH_MACTSCR_TSENMACADDR                       ETH_MACTSCR_TSENMACADDR_Msk  /* Enable MAC Address for PTP Packet Filtering */

+#define ETH_MACTSCR_SNAPTYPSEL_Pos                    (16U)

+#define ETH_MACTSCR_SNAPTYPSEL_Msk                    (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */

+#define ETH_MACTSCR_SNAPTYPSEL                        ETH_MACTSCR_SNAPTYPSEL_Msk  /* Select PTP packets for Taking Snapshots */

+#define ETH_MACTSCR_TSMSTRENA_Pos                     (15U)

+#define ETH_MACTSCR_TSMSTRENA_Msk                     (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */

+#define ETH_MACTSCR_TSMSTRENA                         ETH_MACTSCR_TSMSTRENA_Msk  /* Enable Snapshot for Messages Relevant to Master */

+#define ETH_MACTSCR_TSEVNTENA_Pos                     (14U)

+#define ETH_MACTSCR_TSEVNTENA_Msk                     (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */

+#define ETH_MACTSCR_TSEVNTENA                         ETH_MACTSCR_TSEVNTENA_Msk  /* Enable Timestamp Snapshot for Event Messages */

+#define ETH_MACTSCR_TSIPV4ENA_Pos                     (13U)

+#define ETH_MACTSCR_TSIPV4ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */

+#define ETH_MACTSCR_TSIPV4ENA                         ETH_MACTSCR_TSIPV4ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv4-UDP */

+#define ETH_MACTSCR_TSIPV6ENA_Pos                     (12U)

+#define ETH_MACTSCR_TSIPV6ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */

+#define ETH_MACTSCR_TSIPV6ENA                         ETH_MACTSCR_TSIPV6ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv6-UDP */

+#define ETH_MACTSCR_TSIPENA_Pos                       (11U)

+#define ETH_MACTSCR_TSIPENA_Msk                       (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */

+#define ETH_MACTSCR_TSIPENA                           ETH_MACTSCR_TSIPENA_Msk  /* Enable Processing of PTP over Ethernet Packets */

+#define ETH_MACTSCR_TSVER2ENA_Pos                     (10U)

+#define ETH_MACTSCR_TSVER2ENA_Msk                     (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */

+#define ETH_MACTSCR_TSVER2ENA                         ETH_MACTSCR_TSVER2ENA_Msk  /* Enable PTP Packet Processing for Version 2 Format */

+#define ETH_MACTSCR_TSCTRLSSR_Pos                     (9U)

+#define ETH_MACTSCR_TSCTRLSSR_Msk                     (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */

+#define ETH_MACTSCR_TSCTRLSSR                         ETH_MACTSCR_TSCTRLSSR_Msk  /* Timestamp Digital or Binary Rollover Control */

+#define ETH_MACTSCR_TSENALL_Pos                       (8U)

+#define ETH_MACTSCR_TSENALL_Msk                       (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */

+#define ETH_MACTSCR_TSENALL                           ETH_MACTSCR_TSENALL_Msk  /* Enable Timestamp for All Packets */

+#define ETH_MACTSCR_TSADDREG_Pos                      (5U)

+#define ETH_MACTSCR_TSADDREG_Msk                      (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */

+#define ETH_MACTSCR_TSADDREG                          ETH_MACTSCR_TSADDREG_Msk  /* Update Addend Register */

+#define ETH_MACTSCR_TSUPDT_Pos                        (3U)

+#define ETH_MACTSCR_TSUPDT_Msk                        (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */

+#define ETH_MACTSCR_TSUPDT                            ETH_MACTSCR_TSUPDT_Msk  /* Update Timestamp */

+#define ETH_MACTSCR_TSINIT_Pos                        (2U)

+#define ETH_MACTSCR_TSINIT_Msk                        (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */

+#define ETH_MACTSCR_TSINIT                             ETH_MACTSCR_TSINIT_Msk  /* Initialize Timestamp */

+#define ETH_MACTSCR_TSCFUPDT_Pos                      (1U)

+#define ETH_MACTSCR_TSCFUPDT_Msk                      (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */

+#define ETH_MACTSCR_TSCFUPDT                          ETH_MACTSCR_TSCFUPDT_Msk  /* Fine or Coarse Timestamp Update*/

+#define ETH_MACTSCR_TSENA_Pos                         (0U)

+#define ETH_MACTSCR_TSENA_Msk                         (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */

+#define ETH_MACTSCR_TSENA                             ETH_MACTSCR_TSENA_Msk  /* Enable Timestamp */

+

+/* Bit definition for Ethernet MAC Sub-second Increment Register */

+#define ETH_MACMACSSIR_SSINC_Pos                      (16U)

+#define ETH_MACMACSSIR_SSINC_Msk                      (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) /*!< 0x0000FF00 */

+#define ETH_MACMACSSIR_SSINC                          ETH_MACMACSSIR_SSINC_Msk  /* Sub-second Increment Value */

+#define ETH_MACMACSSIR_SNSINC_Pos                     (8U)

+#define ETH_MACMACSSIR_SNSINC_Msk                     (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos) /*!< 0x000000FF */

+#define ETH_MACMACSSIR_SNSINC                         ETH_MACMACSSIR_SNSINC_Msk  /* Sub-nanosecond Increment Value */

+

+/* Bit definition for Ethernet MAC System Time Seconds Register */

+#define ETH_MACSTSR_TSS_Pos                           (0U)

+#define ETH_MACSTSR_TSS_Msk                           (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSTSR_TSS                               ETH_MACSTSR_TSS_Msk  /* Timestamp Second */

+

+/* Bit definition for Ethernet MAC System Time Nanoseconds Register */

+#define ETH_MACSTNR_TSSS_Pos                          (0U)

+#define ETH_MACSTNR_TSSS_Msk                          (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACSTNR_TSSS                              ETH_MACSTNR_TSSS_Msk  /* Timestamp Sub-seconds */

+

+/* Bit definition for Ethernet MAC System Time Seconds Update Register */

+#define ETH_MACSTSUR_TSS_Pos                          (0U)

+#define ETH_MACSTSUR_TSS_Msk                          (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSTSUR_TSS                              ETH_MACSTSUR_TSS_Msk  /* Timestamp Seconds */

+

+/* Bit definition for Ethernet MAC System Time Nanoseconds Update Register */

+#define ETH_MACSTNUR_ADDSUB_Pos                       (31U)

+#define ETH_MACSTNUR_ADDSUB_Msk                       (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */

+#define ETH_MACSTNUR_ADDSUB                           ETH_MACSTNUR_ADDSUB_Msk  /* Add or Subtract Time */

+#define ETH_MACSTNUR_TSSS_Pos                         (0U)

+#define ETH_MACSTNUR_TSSS_Msk                         (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACSTNUR_TSSS                             ETH_MACSTNUR_TSSS_Msk  /* Timestamp Sub-seconds */

+

+/* Bit definition for Ethernet MAC Timestamp Addend Register */

+#define ETH_MACTSAR_TSAR_Pos                          (0U)

+#define ETH_MACTSAR_TSAR_Msk                          (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSAR_TSAR                              ETH_MACTSAR_TSAR_Msk  /* Timestamp Addend Register */

+

+/* Bit definition for Ethernet MAC Timestamp Status Register */

+#define ETH_MACTSSR_ATSNS_Pos                         (25U)

+#define ETH_MACTSSR_ATSNS_Msk                         (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */

+#define ETH_MACTSSR_ATSNS                             ETH_MACTSSR_ATSNS_Msk  /* Number of Auxiliary Timestamp Snapshots */

+#define ETH_MACTSSR_ATSSTM_Pos                        (24U)

+#define ETH_MACTSSR_ATSSTM_Msk                        (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */

+#define ETH_MACTSSR_ATSSTM                            ETH_MACTSSR_ATSSTM_Msk  /* Auxiliary Timestamp Snapshot Trigger Missed */

+#define ETH_MACTSSR_ATSSTN_Pos                        (16U)

+#define ETH_MACTSSR_ATSSTN_Msk                        (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */

+#define ETH_MACTSSR_ATSSTN                            ETH_MACTSSR_ATSSTN_Msk  /* Auxiliary Timestamp Snapshot Trigger Identifier */

+#define ETH_MACTSSR_TXTSSIS_Pos                       (15U)

+#define ETH_MACTSSR_TXTSSIS_Msk                       (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */

+#define ETH_MACTSSR_TXTSSIS                           ETH_MACTSSR_TXTSSIS_Msk  /* Tx Timestamp Status Interrupt Status */

+#define ETH_MACTSSR_TSTRGTERR0_Pos                    (3U)

+#define ETH_MACTSSR_TSTRGTERR0_Msk                    (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */

+#define ETH_MACTSSR_TSTRGTERR0                        ETH_MACTSSR_TSTRGTERR0_Msk  /* Timestamp Target Time Error */

+#define ETH_MACTSSR_AUXTSTRIG_Pos                     (2U)

+#define ETH_MACTSSR_AUXTSTRIG_Msk                     (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */

+#define ETH_MACTSSR_AUXTSTRIG                         ETH_MACTSSR_AUXTSTRIG_Msk  /* Auxiliary Timestamp Trigger Snapshot*/

+#define ETH_MACTSSR_TSTARGT0_Pos                      (1U)

+#define ETH_MACTSSR_TSTARGT0_Msk                      (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */

+#define ETH_MACTSSR_TSTARGT0                          ETH_MACTSSR_TSTARGT0_Msk  /* Timestamp Target Time Reached */

+#define ETH_MACTSSR_TSSOVF_Pos                        (0U)

+#define ETH_MACTSSR_TSSOVF_Msk                        (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */

+#define ETH_MACTSSR_TSSOVF                            ETH_MACTSSR_TSSOVF_Msk  /* Timestamp Seconds Overflow */

+

+/* Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register */

+#define ETH_MACTTSSNR_TXTSSMIS_Pos                    (31U)

+#define ETH_MACTTSSNR_TXTSSMIS_Msk                    (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */

+#define ETH_MACTTSSNR_TXTSSMIS                        ETH_MACTTSSNR_TXTSSMIS_Msk  /* Transmit Timestamp Status Missed */

+#define ETH_MACTTSSNR_TXTSSLO_Pos                     (0U)

+#define ETH_MACTTSSNR_TXTSSLO_Msk                     (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACTTSSNR_TXTSSLO                         ETH_MACTTSSNR_TXTSSLO_Msk  /* Transmit Timestamp Status Low */

+

+/* Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register */

+#define ETH_MACTTSSSR_TXTSSHI_Pos                     (0U)

+#define ETH_MACTTSSSR_TXTSSHI_Msk                     (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTTSSSR_TXTSSHI                         ETH_MACTTSSSR_TXTSSHI_Msk  /* Transmit Timestamp Status High */

+

+/* Bit definition for Ethernet MAC Auxiliary Control Register*/

+#define ETH_MACACR_ATSEN3_Pos                         (7U)

+#define ETH_MACACR_ATSEN3_Msk                         (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */

+#define ETH_MACACR_ATSEN3                             ETH_MACACR_ATSEN3_Msk  /* Auxiliary Snapshot 3 Enable */

+#define ETH_MACACR_ATSEN2_Pos                         (6U)

+#define ETH_MACACR_ATSEN2_Msk                         (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */

+#define ETH_MACACR_ATSEN2                             ETH_MACACR_ATSEN2_Msk  /* Auxiliary Snapshot 2 Enable */

+#define ETH_MACACR_ATSEN1_Pos                         (5U)

+#define ETH_MACACR_ATSEN1_Msk                         (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */

+#define ETH_MACACR_ATSEN1                             ETH_MACACR_ATSEN1_Msk  /* Auxiliary Snapshot 1 Enable */

+#define ETH_MACACR_ATSEN0_Pos                         (4U)

+#define ETH_MACACR_ATSEN0_Msk                         (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */

+#define ETH_MACACR_ATSEN0                             ETH_MACACR_ATSEN0_Msk  /* Auxiliary Snapshot 0 Enable */

+#define ETH_MACACR_ATSFC_Pos                          (0U)

+#define ETH_MACACR_ATSFC_Msk                          (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */

+#define ETH_MACACR_ATSFC                              ETH_MACACR_ATSFC_Msk  /* Auxiliary Snapshot FIFO Clear */

+

+/* Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register */

+#define ETH_MACATSNR_AUXTSLO_Pos                      (0U)

+#define ETH_MACATSNR_AUXTSLO_Msk                      (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACATSNR_AUXTSLO                          ETH_MACATSNR_AUXTSLO_Msk  /* Auxiliary Timestamp */

+

+/* Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register */

+#define ETH_MACATSSR_AUXTSHI_Pos                      (0U)

+#define ETH_MACATSSR_AUXTSHI_Msk                      (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACATSSR_AUXTSHI                          ETH_MACATSSR_AUXTSHI_Msk  /* Auxiliary Timestamp */

+

+/* Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register */

+#define ETH_MACTSIACR_OSTIAC_Pos                      (0U)

+#define ETH_MACTSIACR_OSTIAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSIACR_OSTIAC                          ETH_MACTSIACR_OSTIAC_Msk  /* One-Step Timestamp Ingress Asymmetry Correction */

+

+/* Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction Register */

+#define ETH_MACTSEACR_OSTEAC_Pos                      (0U)

+#define ETH_MACTSEACR_OSTEAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSEACR_OSTEAC                          ETH_MACTSEACR_OSTEAC_Msk  /* One-Step Timestamp Egress Asymmetry Correction */

+

+/* Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond Register */

+#define ETH_MACTSICNR_TSIC_Pos                        (0U)

+#define ETH_MACTSICNR_TSIC_Msk                        (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSICNR_TSIC                            ETH_MACTSICNR_TSIC_Msk  /* Timestamp Ingress Correction */

+

+/* Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond Register */

+#define ETH_MACTSECNR_TSEC_Pos                        (0U)

+#define ETH_MACTSECNR_TSEC_Msk                        (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSECNR_TSEC                            ETH_MACTSECNR_TSEC_Msk  /* Timestamp Egress Correction */

+

+/* Bit definition for Ethernet MAC PPS Control Register */

+#define ETH_MACPPSCR_TRGTMODSEL0_Pos                  (5U)

+#define ETH_MACPPSCR_TRGTMODSEL0_Msk                  (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */

+#define ETH_MACPPSCR_TRGTMODSEL0                      ETH_MACPPSCR_TRGTMODSEL0_Msk  /* Target Time Register Mode for PPS Output */

+#define ETH_MACPPSCR_PPSEN0_Pos                       (4U)

+#define ETH_MACPPSCR_PPSEN0_Msk                       (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */

+#define ETH_MACPPSCR_PPSEN0                           ETH_MACPPSCR_PPSEN0_Msk  /* Flexible PPS Output Mode Enable */

+#define ETH_MACPPSCR_PPSCTRL_Pos                      (0U)

+#define ETH_MACPPSCR_PPSCTRL_Msk                      (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */

+#define ETH_MACPPSCR_PPSCTRL                          ETH_MACPPSCR_PPSCTRL_Msk  /* PPS Output Frequency Control */

+

+/* Bit definition for Ethernet MAC PPS Target Time Seconds Register */

+#define ETH_MACPPSTTSR_TSTRH0_Pos                     (0U)

+#define ETH_MACPPSTTSR_TSTRH0_Msk                     (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACPPSTTSR_TSTRH0                         ETH_MACPPSTTSR_TSTRH0_Msk  /* PPS Target Time Seconds Register */

+

+/* Bit definition for Ethernet MAC PPS Target Time Nanoseconds Register */

+#define ETH_MACPPSTTNR_TRGTBUSY0_Pos                  (31U)

+#define ETH_MACPPSTTNR_TRGTBUSY0_Msk                  (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos) /*!< 0x80000000 */

+#define ETH_MACPPSTTNR_TRGTBUSY0                      ETH_MACPPSTTNR_TRGTBUSY0_Msk  /* PPS Target Time Register Busy */

+#define ETH_MACPPSTTNR_TTSL0_Pos                      (0U)

+#define ETH_MACPPSTTNR_TTSL0_Msk                      (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACPPSTTNR_TTSL0                          ETH_MACPPSTTNR_TTSL0_Msk  /* Target Time Low for PPS Register */

+

+/* Bit definition for Ethernet MAC PPS Interval Register */

+#define ETH_MACPPSIR_PPSINT0_Pos                      (0U)

+#define ETH_MACPPSIR_PPSINT0_Msk                      (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACPPSIR_PPSINT0                          ETH_MACPPSIR_PPSINT0_Msk  /* PPS Output Signal Interval */

+

+/* Bit definition for Ethernet MAC PPS Width Register */

+#define ETH_MACPPSWR_PPSWIDTH0_Pos                    (0U)

+#define ETH_MACPPSWR_PPSWIDTH0_Msk                    (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACPPSWR_PPSWIDTH0                        ETH_MACPPSWR_PPSWIDTH0_Msk  /* PPS Output Signal Width */

+

+/* Bit definition for Ethernet MAC PTP Offload Control Register */

+#define ETH_MACPOCR_DN_Pos                            (8U)

+#define ETH_MACPOCR_DN_Msk                            (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */

+#define ETH_MACPOCR_DN                                ETH_MACPOCR_DN_Msk  /* Domain Number */

+#define ETH_MACPOCR_DRRDIS_Pos                        (6U)

+#define ETH_MACPOCR_DRRDIS_Msk                        (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */

+#define ETH_MACPOCR_DRRDIS                            ETH_MACPOCR_DRRDIS_Msk  /* Disable PTO Delay Request/Response response generation */

+#define ETH_MACPOCR_APDREQTRIG_Pos                    (5U)

+#define ETH_MACPOCR_APDREQTRIG_Msk                    (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */

+#define ETH_MACPOCR_APDREQTRIG                        ETH_MACPOCR_APDREQTRIG_Msk  /* Automatic PTP Pdelay_Req message Trigger */

+#define ETH_MACPOCR_ASYNCTRIG_Pos                     (4U)

+#define ETH_MACPOCR_ASYNCTRIG_Msk                     (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */

+#define ETH_MACPOCR_ASYNCTRIG                         ETH_MACPOCR_ASYNCTRIG_Msk  /* Automatic PTP SYNC message Trigger */

+#define ETH_MACPOCR_APDREQEN_Pos                      (2U)

+#define ETH_MACPOCR_APDREQEN_Msk                      (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */

+#define ETH_MACPOCR_APDREQEN                          ETH_MACPOCR_APDREQEN_Msk  /* Automatic PTP Pdelay_Req message Enable */

+#define ETH_MACPOCR_ASYNCEN_Pos                       (1U)

+#define ETH_MACPOCR_ASYNCEN_Msk                       (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */

+#define ETH_MACPOCR_ASYNCEN                           ETH_MACPOCR_ASYNCEN_Msk  /* Automatic PTP SYNC message Enable */

+#define ETH_MACPOCR_PTOEN_Pos                         (0U)

+#define ETH_MACPOCR_PTOEN_Msk                         (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */

+#define ETH_MACPOCR_PTOEN                             ETH_MACPOCR_PTOEN_Msk  /* PTP Offload Enable */

+

+/* Bit definition for Ethernet MAC PTP Source Port Identity 0 Register */

+#define ETH_MACSPI0R_SPI0_Pos                         (0U)

+#define ETH_MACSPI0R_SPI0_Msk                         (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSPI0R_SPI0                             ETH_MACSPI0R_SPI0_Msk  /* Source Port Identity 0 */

+

+/* Bit definition for Ethernet MAC PTP Source Port Identity 1 Register */

+#define ETH_MACSPI1R_SPI1_Pos                         (0U)

+#define ETH_MACSPI1R_SPI1_Msk                         (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSPI1R_SPI1                             ETH_MACSPI1R_SPI1_Msk  /* Source Port Identity 1 */

+

+/* Bit definition for Ethernet MAC PTP Source Port Identity 2 Register */

+#define ETH_MACSPI2R_SPI2_Pos                         (0U)

+#define ETH_MACSPI2R_SPI2_Msk                         (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */

+#define ETH_MACSPI2R_SPI2                             ETH_MACSPI2R_SPI2_Msk  /* Source Port Identity 2 */

+

+/* Bit definition for Ethernet MAC Log Message Interval Register */

+#define ETH_MACLMIR_LMPDRI_Pos                        (24U)

+#define ETH_MACLMIR_LMPDRI_Msk                        (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */

+#define ETH_MACLMIR_LMPDRI                             ETH_MACLMIR_LMPDRI_Msk  /* Log Min Pdelay_Req Interval */

+#define ETH_MACLMIR_DRSYNCR_Pos                       (8U)

+#define ETH_MACLMIR_DRSYNCR_Msk                       (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */

+#define ETH_MACLMIR_DRSYNCR                           ETH_MACLMIR_DRSYNCR_Msk  /* Delay_Req to SYNC Ratio */

+#define ETH_MACLMIR_LSI_Pos                           (0U)

+#define ETH_MACLMIR_LSI_Msk                           (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */

+#define ETH_MACLMIR_LSI                               ETH_MACLMIR_LSI_Msk  /* Log Sync Interval */

+

+/* Bit definition for Ethernet MTL Operation Mode Register */

+#define ETH_MTLOMR_CNTCLR_Pos                         (9U)

+#define ETH_MTLOMR_CNTCLR_Msk                         (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */

+#define ETH_MTLOMR_CNTCLR                             ETH_MTLOMR_CNTCLR_Msk    /* Counters Reset */

+#define ETH_MTLOMR_CNTPRST_Pos                        (8U)

+#define ETH_MTLOMR_CNTPRST_Msk                        (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */

+#define ETH_MTLOMR_CNTPRST                            ETH_MTLOMR_CNTPRST_Msk   /* Counters Preset */

+#define ETH_MTLOMR_DTXSTS_Pos                         (1U)

+#define ETH_MTLOMR_DTXSTS_Msk                         (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */

+#define ETH_MTLOMR_DTXSTS                             ETH_MTLOMR_DTXSTS_Msk  /* Drop Transmit Status */

+

+/* Bit definition for Ethernet MTL Interrupt Status Register */

+#define ETH_MTLISR_MACIS_Pos                          (16U)

+#define ETH_MTLISR_MACIS_Msk                          (0x1UL << ETH_MTLISR_MACIS_Pos) /*!< 0x00010000 */

+#define ETH_MTLISR_MACIS                              ETH_MTLISR_MACIS_Msk     /* MAC Interrupt Status */

+#define ETH_MTLISR_QIS_Pos                            (0U)

+#define ETH_MTLISR_QIS_Msk                            (0x1UL << ETH_MTLISR_QIS_Pos) /*!< 0x00000001 */

+#define ETH_MTLISR_QIS                                ETH_MTLISR_QIS_Msk       /* Queue Interrupt status */

+

+/* Bit definition for Ethernet MTL Tx Queue Operation Mode Register */

+#define ETH_MTLTQOMR_TTC_Pos                          (4U)

+#define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */

+#define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */

+#define ETH_MTLTQOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */

+#define ETH_MTLTQOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */

+#define ETH_MTLTQOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */

+#define ETH_MTLTQOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */

+#define ETH_MTLTQOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */

+#define ETH_MTLTQOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */

+#define ETH_MTLTQOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */

+#define ETH_MTLTQOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */

+#define ETH_MTLTQOMR_TSF_Pos                          (1U)

+#define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */

+#define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */

+#define ETH_MTLTQOMR_FTQ_Pos                          (0U)

+#define ETH_MTLTQOMR_FTQ_Msk                          (0x1UL << ETH_MTLTQOMR_FTQ_Pos) /*!< 0x00000001 */

+#define ETH_MTLTQOMR_FTQ                              ETH_MTLTQOMR_FTQ_Msk     /* Flush Transmit Queue */

+

+/* Bit definition for Ethernet MTL Tx Queue Underflow Register */

+#define ETH_MTLTQUR_UFCNTOVF_Pos                      (11U)

+#define ETH_MTLTQUR_UFCNTOVF_Msk                      (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos) /*!< 0x00000800 */

+#define ETH_MTLTQUR_UFCNTOVF                          ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */

+#define ETH_MTLTQUR_UFPKTCNT_Pos                      (0U)

+#define ETH_MTLTQUR_UFPKTCNT_Msk                      (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos) /*!< 0x000007FF */

+#define ETH_MTLTQUR_UFPKTCNT                          ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */

+

+/* Bit definition for Ethernet MTL Tx Queue Debug Register */

+#define ETH_MTLTQDR_STXSTSF_Pos                       (20U)

+#define ETH_MTLTQDR_STXSTSF_Msk                       (0x7UL << ETH_MTLTQDR_STXSTSF_Pos) /*!< 0x00700000 */

+#define ETH_MTLTQDR_STXSTSF                           ETH_MTLTQDR_STXSTSF_Msk  /* Number of Status Words in the Tx Status FIFO of Queue */

+#define ETH_MTLTQDR_PTXQ_Pos                          (16U)

+#define ETH_MTLTQDR_PTXQ_Msk                          (0x7UL << ETH_MTLTQDR_PTXQ_Pos) /*!< 0x00070000 */

+#define ETH_MTLTQDR_PTXQ                              ETH_MTLTQDR_PTXQ_Msk     /* Number of Packets in the Transmit Queue */

+#define ETH_MTLTQDR_TXSTSFSTS_Pos                     (5U)

+#define ETH_MTLTQDR_TXSTSFSTS_Msk                     (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos) /*!< 0x00000020 */

+#define ETH_MTLTQDR_TXSTSFSTS                         ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */

+#define ETH_MTLTQDR_TXQSTS_Pos                        (4U)

+#define ETH_MTLTQDR_TXQSTS_Msk                        (0x1UL << ETH_MTLTQDR_TXQSTS_Pos) /*!< 0x00000010 */

+#define ETH_MTLTQDR_TXQSTS                            ETH_MTLTQDR_TXQSTS_Msk   /* MTL Tx Queue Not Empty Status */

+#define ETH_MTLTQDR_TWCSTS_Pos                        (3U)

+#define ETH_MTLTQDR_TWCSTS_Msk                        (0x1UL << ETH_MTLTQDR_TWCSTS_Pos) /*!< 0x00000008 */

+#define ETH_MTLTQDR_TWCSTS                            ETH_MTLTQDR_TWCSTS_Msk   /* MTL Tx Queue Write Controller Status */

+#define ETH_MTLTQDR_TRCSTS_Pos                        (1U)

+#define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */

+#define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */

+#define ETH_MTLTQDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */

+#define ETH_MTLTQDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */

+#define ETH_MTLTQDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */

+#define ETH_MTLTQDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */

+#define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)

+#define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */

+#define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */

+

+/* Bit definition for Ethernet MTL Queue Interrupt Control Status Register */

+#define ETH_MTLQICSR_RXOIE_Pos                        (24U)

+#define ETH_MTLQICSR_RXOIE_Msk                        (0x1UL << ETH_MTLQICSR_RXOIE_Pos) /*!< 0x01000000 */

+#define ETH_MTLQICSR_RXOIE                            ETH_MTLQICSR_RXOIE_Msk   /* Receive Queue Overflow Interrupt Enable */

+#define ETH_MTLQICSR_RXOVFIS_Pos                      (16U)

+#define ETH_MTLQICSR_RXOVFIS_Msk                      (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos) /*!< 0x00010000 */

+#define ETH_MTLQICSR_RXOVFIS                          ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */

+#define ETH_MTLQICSR_TXUIE_Pos                        (8U)

+#define ETH_MTLQICSR_TXUIE_Msk                        (0x1UL << ETH_MTLQICSR_TXUIE_Pos) /*!< 0x00000100 */

+#define ETH_MTLQICSR_TXUIE                            ETH_MTLQICSR_TXUIE_Msk   /* Transmit Queue Underflow Interrupt Enable */

+#define ETH_MTLQICSR_TXUNFIS_Pos                      (0U)

+#define ETH_MTLQICSR_TXUNFIS_Msk                      (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos) /*!< 0x00000001 */

+#define ETH_MTLQICSR_TXUNFIS                          ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */

+

+/* Bit definition for Ethernet MTL Rx Queue Operation Mode Register */

+#define ETH_MTLRQOMR_RQS_Pos                          (20U)

+#define ETH_MTLRQOMR_RQS_Msk                          (0x7UL << ETH_MTLRQOMR_RQS_Pos) /*!< 0x00700000 */

+#define ETH_MTLRQOMR_RQS                              ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */

+#define ETH_MTLRQOMR_RFD_Pos                          (14U)

+#define ETH_MTLRQOMR_RFD_Msk                          (0x7UL << ETH_MTLRQOMR_RFD_Pos) /*!< 0x0001C000 */

+#define ETH_MTLRQOMR_RFD                              ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */

+#define ETH_MTLRQOMR_RFA_Pos                          (8U)

+#define ETH_MTLRQOMR_RFA_Msk                          (0x7UL << ETH_MTLRQOMR_RFA_Pos) /*!< 0x00000700 */

+#define ETH_MTLRQOMR_RFA                              ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */

+#define ETH_MTLRQOMR_EHFC_Pos                         (7U)

+#define ETH_MTLRQOMR_EHFC_Msk                         (0x1UL << ETH_MTLRQOMR_EHFC_Pos) /*!< 0x00000080 */

+#define ETH_MTLRQOMR_EHFC                             ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */

+#define ETH_MTLRQOMR_DISTCPEF_Pos                     (6U)

+#define ETH_MTLRQOMR_DISTCPEF_Msk                     (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos) /*!< 0x00000040 */

+#define ETH_MTLRQOMR_DISTCPEF                         ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */

+#define ETH_MTLRQOMR_RSF_Pos                          (5U)

+#define ETH_MTLRQOMR_RSF_Msk                          (0x1UL << ETH_MTLRQOMR_RSF_Pos) /*!< 0x00000020 */

+#define ETH_MTLRQOMR_RSF                              ETH_MTLRQOMR_RSF_Msk     /* Receive Queue Store and Forward */

+#define ETH_MTLRQOMR_FEP_Pos                          (4U)

+#define ETH_MTLRQOMR_FEP_Msk                          (0x1UL << ETH_MTLRQOMR_FEP_Pos) /*!< 0x00000010 */

+#define ETH_MTLRQOMR_FEP                              ETH_MTLRQOMR_FEP_Msk     /* Forward Error Packets */

+#define ETH_MTLRQOMR_FUP_Pos                          (3U)

+#define ETH_MTLRQOMR_FUP_Msk                          (0x1UL << ETH_MTLRQOMR_FUP_Pos) /*!< 0x00000008 */

+#define ETH_MTLRQOMR_FUP                              ETH_MTLRQOMR_FUP_Msk     /* Forward Undersized Good Packets */

+#define ETH_MTLRQOMR_RTC_Pos                          (0U)

+#define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */

+#define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */

+#define ETH_MTLRQOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */

+#define ETH_MTLRQOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */

+#define ETH_MTLRQOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */

+#define ETH_MTLRQOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */

+

+/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */

+#define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)

+#define ETH_MTLRQMPOCR_MISCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */

+#define ETH_MTLRQMPOCR_MISCNTOVF                      ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */

+#define ETH_MTLRQMPOCR_MISPKTCNT_Pos                  (16U)

+#define ETH_MTLRQMPOCR_MISPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */

+#define ETH_MTLRQMPOCR_MISPKTCNT                      ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */

+#define ETH_MTLRQMPOCR_OVFCNTOVF_Pos                  (11U)

+#define ETH_MTLRQMPOCR_OVFCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */

+#define ETH_MTLRQMPOCR_OVFCNTOVF                      ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */

+#define ETH_MTLRQMPOCR_OVFPKTCNT_Pos                  (0U)

+#define ETH_MTLRQMPOCR_OVFPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */

+#define ETH_MTLRQMPOCR_OVFPKTCNT                      ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */

+

+/* Bit definition for Ethernet MTL Rx Queue Debug Register */

+#define ETH_MTLRQDR_PRXQ_Pos                          (16U)

+#define ETH_MTLRQDR_PRXQ_Msk                          (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos) /*!< 0x3FFF0000 */

+#define ETH_MTLRQDR_PRXQ                              ETH_MTLRQDR_PRXQ_Msk     /* Number of Packets in Receive Queue */

+#define ETH_MTLRQDR_RXQSTS_Pos                        (4U)

+#define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */

+#define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */

+#define ETH_MTLRQDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */

+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)

+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */

+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */

+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos         (5U)

+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */

+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD             ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */

+#define ETH_MTLRQDR_RXQSTS_FULL_Pos                   (4U)

+#define ETH_MTLRQDR_RXQSTS_FULL_Msk                   (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */

+#define ETH_MTLRQDR_RXQSTS_FULL                       ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */

+#define ETH_MTLRQDR_RRCSTS_Pos                        (1U)

+#define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */

+#define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */

+#define ETH_MTLRQDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */

+#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)

+#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */

+#define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */

+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos          (2U)

+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk          (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */

+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS              ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */

+#define ETH_MTLRQDR_RRCSTS_FLUSHING_Pos               (1U)

+#define ETH_MTLRQDR_RRCSTS_FLUSHING_Msk               (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */

+#define ETH_MTLRQDR_RRCSTS_FLUSHING                   ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */

+#define ETH_MTLRQDR_RWCSTS_Pos                        (0U)

+#define ETH_MTLRQDR_RWCSTS_Msk                        (0x1UL << ETH_MTLRQDR_RWCSTS_Pos) /*!< 0x00000001 */

+#define ETH_MTLRQDR_RWCSTS                            ETH_MTLRQDR_RWCSTS_Msk   /* MTL Rx Queue Write Controller Active Status */

+

+/* Bit definition for Ethernet MTL Rx Queue Control Register */

+#define ETH_MTLRQCR_RQPA_Pos                          (3U)

+#define ETH_MTLRQCR_RQPA_Msk                          (0x1UL << ETH_MTLRQCR_RQPA_Pos) /*!< 0x00000008 */

+#define ETH_MTLRQCR_RQPA                              ETH_MTLRQCR_RQPA_Msk     /* Receive Queue Packet Arbitration */

+#define ETH_MTLRQCR_RQW_Pos                           (0U)

+#define ETH_MTLRQCR_RQW_Msk                           (0x7UL << ETH_MTLRQCR_RQW_Pos) /*!< 0x00000007 */

+#define ETH_MTLRQCR_RQW                               ETH_MTLRQCR_RQW_Msk      /* Receive Queue Weight */

+

+/* Bit definition for Ethernet DMA Mode Register */

+#define ETH_DMAMR_INTM_Pos                            (16U)

+#define ETH_DMAMR_INTM_Msk                            (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */

+#define ETH_DMAMR_INTM                                ETH_DMAMR_INTM_Msk       /* This field defines the interrupt mode */

+#define ETH_DMAMR_INTM_0                              (0x0UL << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */

+#define ETH_DMAMR_INTM_1                              (0x1UL << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */

+#define ETH_DMAMR_INTM_2                              (0x2UL << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */

+#define ETH_DMAMR_PR_Pos                              (12U)

+#define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */

+#define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */

+#define ETH_DMAMR_PR_1_1                              ((uint32_t)0x00000000)   /* The priority ratio is 1:1 */

+#define ETH_DMAMR_PR_2_1                              ((uint32_t)0x00001000)   /* The priority ratio is 2:1 */

+#define ETH_DMAMR_PR_3_1                              ((uint32_t)0x00002000)   /* The priority ratio is 3:1 */

+#define ETH_DMAMR_PR_4_1                              ((uint32_t)0x00003000)   /* The priority ratio is 4:1 */

+#define ETH_DMAMR_PR_5_1                              ((uint32_t)0x00004000)   /* The priority ratio is 5:1 */

+#define ETH_DMAMR_PR_6_1                              ((uint32_t)0x00005000)   /* The priority ratio is 6:1 */

+#define ETH_DMAMR_PR_7_1                              ((uint32_t)0x00006000)   /* The priority ratio is 7:1 */

+#define ETH_DMAMR_PR_8_1                              ((uint32_t)0x00007000)   /* The priority ratio is 8:1 */

+#define ETH_DMAMR_TXPR_Pos                            (11U)

+#define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */

+#define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */

+#define ETH_DMAMR_DA_Pos                              (1U)

+#define ETH_DMAMR_DA_Msk                              (0x1UL << ETH_DMAMR_DA_Pos) /*!< 0x00000002 */

+#define ETH_DMAMR_DA                                  ETH_DMAMR_DA_Msk         /* DMA Tx or Rx Arbitration Scheme */

+#define ETH_DMAMR_SWR_Pos                             (0U)

+#define ETH_DMAMR_SWR_Msk                             (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */

+#define ETH_DMAMR_SWR                                 ETH_DMAMR_SWR_Msk        /* Software Reset */

+

+/* Bit definition for Ethernet DMA SysBus Mode Register */

+#define ETH_DMASBMR_RB_Pos                            (15U)

+#define ETH_DMASBMR_RB_Msk                            (0x1UL << ETH_DMASBMR_RB_Pos) /*!< 0x00008000 */

+#define ETH_DMASBMR_RB                                ETH_DMASBMR_RB_Msk       /* Rebuild INCRx Burst */

+#define ETH_DMASBMR_MB_Pos                            (14U)

+#define ETH_DMASBMR_MB_Msk                            (0x1UL << ETH_DMASBMR_MB_Pos) /*!< 0x00004000 */

+#define ETH_DMASBMR_MB                                ETH_DMASBMR_MB_Msk       /* Mixed Burst */

+#define ETH_DMASBMR_AAL_Pos                           (12U)

+#define ETH_DMASBMR_AAL_Msk                           (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */

+#define ETH_DMASBMR_AAL                               ETH_DMASBMR_AAL_Msk      /* Address-Aligned Beats */

+#define ETH_DMASBMR_FB_Pos                            (0U)

+#define ETH_DMASBMR_FB_Msk                            (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */

+#define ETH_DMASBMR_FB                                ETH_DMASBMR_FB_Msk       /* Fixed Burst Length */

+

+/* Bit definition for Ethernet DMA Interrupt Status Register */

+#define ETH_DMAISR_MACIS_Pos                          (17U)

+#define ETH_DMAISR_MACIS_Msk                          (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */

+#define ETH_DMAISR_MACIS                              ETH_DMAISR_MACIS_Msk     /* MAC Interrupt Status */

+#define ETH_DMAISR_MTLIS_Pos                          (16U)

+#define ETH_DMAISR_MTLIS_Msk                          (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */

+#define ETH_DMAISR_MTLIS                              ETH_DMAISR_MTLIS_Msk     /* MAC Interrupt Status */

+#define ETH_DMAISR_DMACIS_Pos                         (0U)

+#define ETH_DMAISR_DMACIS_Msk                         (0x1UL << ETH_DMAISR_DMACIS_Pos) /*!< 0x00000001 */

+#define ETH_DMAISR_DMACIS                             ETH_DMAISR_DMACIS_Msk    /* DMA Channel Interrupt Status */

+

+/* Bit definition for Ethernet DMA Debug Status Register */

+#define ETH_DMADSR_TPS_Pos                            (12U)

+#define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */

+#define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */

+#define ETH_DMADSR_TPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */

+#define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)

+#define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */

+#define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */

+#define ETH_DMADSR_TPS_WAITING_Pos                    (13U)

+#define ETH_DMADSR_TPS_WAITING_Msk                    (0x1UL << ETH_DMADSR_TPS_WAITING_Pos) /*!< 0x00002000 */

+#define ETH_DMADSR_TPS_WAITING                        ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */

+#define ETH_DMADSR_TPS_READING_Pos                    (12U)

+#define ETH_DMADSR_TPS_READING_Msk                    (0x3UL << ETH_DMADSR_TPS_READING_Pos) /*!< 0x00003000 */

+#define ETH_DMADSR_TPS_READING                        ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */

+#define ETH_DMADSR_TPS_TIMESTAMP_WR_Pos               (14U)

+#define ETH_DMADSR_TPS_TIMESTAMP_WR_Msk               (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos) /*!< 0x00004000 */

+#define ETH_DMADSR_TPS_TIMESTAMP_WR                   ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */

+#define ETH_DMADSR_TPS_SUSPENDED_Pos                  (13U)

+#define ETH_DMADSR_TPS_SUSPENDED_Msk                  (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos) /*!< 0x00006000 */

+#define ETH_DMADSR_TPS_SUSPENDED                      ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */

+#define ETH_DMADSR_TPS_CLOSING_Pos                    (12U)

+#define ETH_DMADSR_TPS_CLOSING_Msk                    (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos) /*!< 0x00007000 */

+#define ETH_DMADSR_TPS_CLOSING                        ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */

+#define ETH_DMADSR_RPS_Pos                            (8U)

+#define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */

+#define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */

+#define ETH_DMADSR_RPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */

+#define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)

+#define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */

+#define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */

+#define ETH_DMADSR_RPS_WAITING_Pos                    (12U)

+#define ETH_DMADSR_RPS_WAITING_Msk                    (0x3UL << ETH_DMADSR_RPS_WAITING_Pos) /*!< 0x00003000 */

+#define ETH_DMADSR_RPS_WAITING                        ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */

+#define ETH_DMADSR_RPS_SUSPENDED_Pos                  (14U)

+#define ETH_DMADSR_RPS_SUSPENDED_Msk                  (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos) /*!< 0x00004000 */

+#define ETH_DMADSR_RPS_SUSPENDED                      ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */

+#define ETH_DMADSR_RPS_CLOSING_Pos                    (12U)

+#define ETH_DMADSR_RPS_CLOSING_Msk                    (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos) /*!< 0x00005000 */

+#define ETH_DMADSR_RPS_CLOSING                        ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */

+#define ETH_DMADSR_RPS_TIMESTAMP_WR_Pos               (13U)

+#define ETH_DMADSR_RPS_TIMESTAMP_WR_Msk               (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos) /*!< 0x00006000 */

+#define ETH_DMADSR_RPS_TIMESTAMP_WR                   ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */

+#define ETH_DMADSR_RPS_TRANSFERRING_Pos               (12U)

+#define ETH_DMADSR_RPS_TRANSFERRING_Msk               (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos) /*!< 0x00007000 */

+#define ETH_DMADSR_RPS_TRANSFERRING                   ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */

+

+/* Bit definition for Ethernet DMA Channel Control Register */

+#define ETH_DMACCR_DSL_Pos                            (18U)

+#define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */

+#define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */

+#define ETH_DMACCR_DSL_0BIT                           ((uint32_t)0x00000000)

+#define ETH_DMACCR_DSL_32BIT                          ((uint32_t)0x00040000)

+#define ETH_DMACCR_DSL_64BIT                          ((uint32_t)0x00080000)

+#define ETH_DMACCR_DSL_128BIT                         ((uint32_t)0x00100000)

+#define ETH_DMACCR_8PBL                               ((uint32_t)0x00010000)   /* 8xPBL mode */

+#define ETH_DMACCR_MSS_Pos                            (0U)

+#define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */

+#define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */

+

+/* Bit definition for Ethernet DMA Channel Tx Control Register */

+#define ETH_DMACTCR_TPBL_Pos                          (16U)

+#define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */

+#define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */

+#define ETH_DMACTCR_TPBL_1PBL                         ((uint32_t)0x00010000)   /* Transmit Programmable Burst Length 1 */

+#define ETH_DMACTCR_TPBL_2PBL                         ((uint32_t)0x00020000)   /* Transmit Programmable Burst Length 2 */

+#define ETH_DMACTCR_TPBL_4PBL                         ((uint32_t)0x00040000)   /* Transmit Programmable Burst Length 4 */

+#define ETH_DMACTCR_TPBL_8PBL                         ((uint32_t)0x00080000)   /* Transmit Programmable Burst Length 8 */

+#define ETH_DMACTCR_TPBL_16PBL                        ((uint32_t)0x00100000)   /* Transmit Programmable Burst Length 16 */

+#define ETH_DMACTCR_TPBL_32PBL                        ((uint32_t)0x00200000)   /* Transmit Programmable Burst Length 32 */

+#define ETH_DMACTCR_TSE_Pos                           (12U)

+#define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */

+#define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */

+#define ETH_DMACTCR_OSP_Pos                           (4U)

+#define ETH_DMACTCR_OSP_Msk                           (0x1UL << ETH_DMACTCR_OSP_Pos) /*!< 0x00000010 */

+#define ETH_DMACTCR_OSP                               ETH_DMACTCR_OSP_Msk      /* Operate on Second Packet */

+#define ETH_DMACTCR_ST_Pos                            (0U)

+#define ETH_DMACTCR_ST_Msk                            (0x1UL << ETH_DMACTCR_ST_Pos) /*!< 0x00000001 */

+#define ETH_DMACTCR_ST                                ETH_DMACTCR_ST_Msk       /* Start or Stop Transmission Command */

+

+/* Bit definition for Ethernet DMA Channel Rx Control Register */

+#define ETH_DMACRCR_RPF_Pos                           (31U)

+#define ETH_DMACRCR_RPF_Msk                           (0x1UL << ETH_DMACRCR_RPF_Pos) /*!< 0x80000000 */

+#define ETH_DMACRCR_RPF                               ETH_DMACRCR_RPF_Msk      /* Rx Packet Flush */

+#define ETH_DMACRCR_RPBL_Pos                          (16U)

+#define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */

+#define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */

+#define ETH_DMACRCR_RPBL_1PBL                         ((uint32_t)0x00010000)   /* Receive Programmable Burst Length 1 */

+#define ETH_DMACRCR_RPBL_2PBL                         ((uint32_t)0x00020000)   /* Receive Programmable Burst Length 2 */

+#define ETH_DMACRCR_RPBL_4PBL                         ((uint32_t)0x00040000)   /* Receive Programmable Burst Length 4 */

+#define ETH_DMACRCR_RPBL_8PBL                         ((uint32_t)0x00080000)   /* Receive Programmable Burst Length 8 */

+#define ETH_DMACRCR_RPBL_16PBL                        ((uint32_t)0x00100000)   /* Receive Programmable Burst Length 16 */

+#define ETH_DMACRCR_RPBL_32PBL                        ((uint32_t)0x00200000)   /* Receive Programmable Burst Length 32 */

+#define ETH_DMACRCR_RBSZ_Pos                          (1U)

+#define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */

+#define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */

+#define ETH_DMACRCR_SR_Pos                            (0U)

+#define ETH_DMACRCR_SR_Msk                            (0x1UL << ETH_DMACRCR_SR_Pos) /*!< 0x00000001 */

+#define ETH_DMACRCR_SR                                ETH_DMACRCR_SR_Msk       /* Start or Stop Receive */

+

+/* Bit definition for Ethernet DMA CH Tx Desc List Address Register */

+#define ETH_DMACTDLAR_TDESLA_Pos                      (2U)

+#define ETH_DMACTDLAR_TDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACTDLAR_TDESLA                          ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */

+

+/* Bit definition for Ethernet DMA CH Rx Desc List Address Register */

+#define ETH_DMACRDLAR_RDESLA_Pos                      (2U)

+#define ETH_DMACRDLAR_RDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACRDLAR_RDESLA                          ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */

+

+/* Bit definition for Ethernet DMA CH Tx Desc Tail Pointer Register */

+#define ETH_DMACTDTPR_TDT_Pos                         (2U)

+#define ETH_DMACTDTPR_TDT_Msk                         (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACTDTPR_TDT                             ETH_DMACTDTPR_TDT_Msk    /* Transmit Descriptor Tail Pointer */

+

+/* Bit definition for Ethernet DMA CH Rx Desc Tail Pointer Register */

+#define ETH_DMACRDTPR_RDT_Pos                         (2U)

+#define ETH_DMACRDTPR_RDT_Msk                         (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACRDTPR_RDT                             ETH_DMACRDTPR_RDT_Msk    /* Receive Descriptor Tail Pointer */

+

+/* Bit definition for Ethernet DMA CH Tx Desc Ring Length Register */

+#define ETH_DMACTDRLR_TDRL_Pos                        (0U)

+#define ETH_DMACTDRLR_TDRL_Msk                        (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos) /*!< 0x000003FF */

+#define ETH_DMACTDRLR_TDRL                            ETH_DMACTDRLR_TDRL_Msk   /* Transmit Descriptor Ring Length */

+

+/* Bit definition for Ethernet DMA CH Rx Desc Ring Length Register */

+#define ETH_DMACRDRLR_RDRL_Pos                        (0U)

+#define ETH_DMACRDRLR_RDRL_Msk                        (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos) /*!< 0x000003FF */

+#define ETH_DMACRDRLR_RDRL                            ETH_DMACRDRLR_RDRL_Msk   /* Receive Descriptor Ring Length */

+

+/* Bit definition for Ethernet DMA Channel Interrupt Enable Register */

+#define ETH_DMACIER_NIE_Pos                           (15U)

+#define ETH_DMACIER_NIE_Msk                           (0x1UL << ETH_DMACIER_NIE_Pos) /*!< 0x00008000 */

+#define ETH_DMACIER_NIE                               ETH_DMACIER_NIE_Msk      /* Normal Interrupt Summary Enable */

+#define ETH_DMACIER_AIE_Pos                           (14U)

+#define ETH_DMACIER_AIE_Msk                           (0x1UL << ETH_DMACIER_AIE_Pos) /*!< 0x00004000 */

+#define ETH_DMACIER_AIE                               ETH_DMACIER_AIE_Msk      /* Abnormal Interrupt Summary Enable */

+#define ETH_DMACIER_CDEE_Pos                          (13U)

+#define ETH_DMACIER_CDEE_Msk                          (0x1UL << ETH_DMACIER_CDEE_Pos) /*!< 0x00002000 */

+#define ETH_DMACIER_CDEE                              ETH_DMACIER_CDEE_Msk     /* Context Descriptor Error Enable */

+#define ETH_DMACIER_FBEE_Pos                          (12U)

+#define ETH_DMACIER_FBEE_Msk                          (0x1UL << ETH_DMACIER_FBEE_Pos) /*!< 0x00001000 */

+#define ETH_DMACIER_FBEE                              ETH_DMACIER_FBEE_Msk     /* Fatal Bus Error Enable */

+#define ETH_DMACIER_ERIE_Pos                          (11U)

+#define ETH_DMACIER_ERIE_Msk                          (0x1UL << ETH_DMACIER_ERIE_Pos) /*!< 0x00000800 */

+#define ETH_DMACIER_ERIE                              ETH_DMACIER_ERIE_Msk     /* Early Receive Interrupt Enable */

+#define ETH_DMACIER_ETIE_Pos                          (10U)

+#define ETH_DMACIER_ETIE_Msk                          (0x1UL << ETH_DMACIER_ETIE_Pos) /*!< 0x00000400 */

+#define ETH_DMACIER_ETIE                              ETH_DMACIER_ETIE_Msk     /* Early Transmit Interrupt Enable */

+#define ETH_DMACIER_RWTE_Pos                          (9U)

+#define ETH_DMACIER_RWTE_Msk                          (0x1UL << ETH_DMACIER_RWTE_Pos) /*!< 0x00000200 */

+#define ETH_DMACIER_RWTE                              ETH_DMACIER_RWTE_Msk     /* Receive Watchdog Timeout Enable */

+#define ETH_DMACIER_RSE_Pos                           (8U)

+#define ETH_DMACIER_RSE_Msk                           (0x1UL << ETH_DMACIER_RSE_Pos) /*!< 0x00000100 */

+#define ETH_DMACIER_RSE                               ETH_DMACIER_RSE_Msk      /* Receive Stopped Enable */

+#define ETH_DMACIER_RBUE_Pos                          (7U)

+#define ETH_DMACIER_RBUE_Msk                          (0x1UL << ETH_DMACIER_RBUE_Pos) /*!< 0x00000080 */

+#define ETH_DMACIER_RBUE                              ETH_DMACIER_RBUE_Msk     /* Receive Buffer Unavailable Enable */

+#define ETH_DMACIER_RIE_Pos                           (6U)

+#define ETH_DMACIER_RIE_Msk                           (0x1UL << ETH_DMACIER_RIE_Pos) /*!< 0x00000040 */

+#define ETH_DMACIER_RIE                               ETH_DMACIER_RIE_Msk      /* Receive Interrupt Enable */

+#define ETH_DMACIER_TBUE_Pos                          (2U)

+#define ETH_DMACIER_TBUE_Msk                          (0x1UL << ETH_DMACIER_TBUE_Pos) /*!< 0x00000004 */

+#define ETH_DMACIER_TBUE                              ETH_DMACIER_TBUE_Msk     /* Transmit Buffer Unavailable Enable */

+#define ETH_DMACIER_TXSE_Pos                          (1U)

+#define ETH_DMACIER_TXSE_Msk                          (0x1UL << ETH_DMACIER_TXSE_Pos) /*!< 0x00000002 */

+#define ETH_DMACIER_TXSE                              ETH_DMACIER_TXSE_Msk     /* Transmit Stopped Enable */

+#define ETH_DMACIER_TIE_Pos                           (0U)

+#define ETH_DMACIER_TIE_Msk                           (0x1UL << ETH_DMACIER_TIE_Pos) /*!< 0x00000001 */

+#define ETH_DMACIER_TIE                               ETH_DMACIER_TIE_Msk      /* Transmit Interrupt Enable */

+

+/* Bit definition for Ethernet DMA Channel Rx Interrupt Watchdog Timer Register */

+#define ETH_DMACRIWTR_RWT_Pos                         (0U)

+#define ETH_DMACRIWTR_RWT_Msk                         (0xFFUL << ETH_DMACRIWTR_RWT_Pos) /*!< 0x000000FF */

+#define ETH_DMACRIWTR_RWT                             ETH_DMACRIWTR_RWT_Msk    /* Receive Interrupt Watchdog Timer Count */

+

+/* Bit definition for Ethernet DMA Channel Current App Tx Desc Register */

+#define ETH_DMACCATDR_CURTDESAPTR_Pos                 (0U)

+#define ETH_DMACCATDR_CURTDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCATDR_CURTDESAPTR                     ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Current App Rx Desc Register */

+#define ETH_DMACCARDR_CURRDESAPTR_Pos                 (0U)

+#define ETH_DMACCARDR_CURRDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCARDR_CURRDESAPTR                     ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Current App Tx Buffer Register */

+#define ETH_DMACCATBR_CURTBUFAPTR_Pos                 (0U)

+#define ETH_DMACCATBR_CURTBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCATBR_CURTBUFAPTR                     ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Current App Rx Buffer Register */

+#define ETH_DMACCARBR_CURRBUFAPTR_Pos                 (0U)

+#define ETH_DMACCARBR_CURRBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCARBR_CURRBUFAPTR                     ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Status Register */

+#define ETH_DMACSR_REB_Pos                            (19U)

+#define ETH_DMACSR_REB_Msk                            (0x7UL << ETH_DMACSR_REB_Pos) /*!< 0x00380000 */

+#define ETH_DMACSR_REB                                ETH_DMACSR_REB_Msk       /* Rx DMA Error Bits */

+#define ETH_DMACSR_TEB_Pos                            (16U)

+#define ETH_DMACSR_TEB_Msk                            (0x7UL << ETH_DMACSR_TEB_Pos) /*!< 0x00070000 */

+#define ETH_DMACSR_TEB                                ETH_DMACSR_TEB_Msk       /* Tx DMA Error Bits */

+#define ETH_DMACSR_NIS_Pos                            (15U)

+#define ETH_DMACSR_NIS_Msk                            (0x1UL << ETH_DMACSR_NIS_Pos) /*!< 0x00008000 */

+#define ETH_DMACSR_NIS                                ETH_DMACSR_NIS_Msk       /* Normal Interrupt Summary */

+#define ETH_DMACSR_AIS_Pos                            (14U)

+#define ETH_DMACSR_AIS_Msk                            (0x1UL << ETH_DMACSR_AIS_Pos) /*!< 0x00004000 */

+#define ETH_DMACSR_AIS                                ETH_DMACSR_AIS_Msk       /* Abnormal Interrupt Summary */

+#define ETH_DMACSR_CDE_Pos                            (13U)

+#define ETH_DMACSR_CDE_Msk                            (0x1UL << ETH_DMACSR_CDE_Pos) /*!< 0x00002000 */

+#define ETH_DMACSR_CDE                                ETH_DMACSR_CDE_Msk       /* Context Descriptor Error */

+#define ETH_DMACSR_FBE_Pos                            (12U)

+#define ETH_DMACSR_FBE_Msk                            (0x1UL << ETH_DMACSR_FBE_Pos) /*!< 0x00001000 */

+#define ETH_DMACSR_FBE                                ETH_DMACSR_FBE_Msk       /* Fatal Bus Error */

+#define ETH_DMACSR_ERI_Pos                            (11U)

+#define ETH_DMACSR_ERI_Msk                            (0x1UL << ETH_DMACSR_ERI_Pos) /*!< 0x00000800 */

+#define ETH_DMACSR_ERI                                ETH_DMACSR_ERI_Msk       /* Early Receive Interrupt */

+#define ETH_DMACSR_ETI_Pos                            (10U)

+#define ETH_DMACSR_ETI_Msk                            (0x1UL << ETH_DMACSR_ETI_Pos) /*!< 0x00000400 */

+#define ETH_DMACSR_ETI                                ETH_DMACSR_ETI_Msk       /* Early Transmit Interrupt */

+#define ETH_DMACSR_RWT_Pos                            (9U)

+#define ETH_DMACSR_RWT_Msk                            (0x1UL << ETH_DMACSR_RWT_Pos) /*!< 0x00000200 */

+#define ETH_DMACSR_RWT                                ETH_DMACSR_RWT_Msk       /* Receive Watchdog Timeout */

+#define ETH_DMACSR_RPS_Pos                            (8U)

+#define ETH_DMACSR_RPS_Msk                            (0x1UL << ETH_DMACSR_RPS_Pos) /*!< 0x00000100 */

+#define ETH_DMACSR_RPS                                ETH_DMACSR_RPS_Msk       /* Receive Process Stopped */

+#define ETH_DMACSR_RBU_Pos                            (7U)

+#define ETH_DMACSR_RBU_Msk                            (0x1UL << ETH_DMACSR_RBU_Pos) /*!< 0x00000080 */

+#define ETH_DMACSR_RBU                                ETH_DMACSR_RBU_Msk       /* Receive Buffer Unavailable */

+#define ETH_DMACSR_RI_Pos                             (6U)

+#define ETH_DMACSR_RI_Msk                             (0x1UL << ETH_DMACSR_RI_Pos) /*!< 0x00000040 */

+#define ETH_DMACSR_RI                                 ETH_DMACSR_RI_Msk        /* Receive Interrupt */

+#define ETH_DMACSR_TBU_Pos                            (2U)

+#define ETH_DMACSR_TBU_Msk                            (0x1UL << ETH_DMACSR_TBU_Pos) /*!< 0x00000004 */

+#define ETH_DMACSR_TBU                                ETH_DMACSR_TBU_Msk       /* Transmit Buffer Unavailable */

+#define ETH_DMACSR_TPS_Pos                            (1U)

+#define ETH_DMACSR_TPS_Msk                            (0x1UL << ETH_DMACSR_TPS_Pos) /*!< 0x00000002 */

+#define ETH_DMACSR_TPS                                ETH_DMACSR_TPS_Msk       /* Transmit Process Stopped */

+#define ETH_DMACSR_TI_Pos                             (0U)

+#define ETH_DMACSR_TI_Msk                             (0x1UL << ETH_DMACSR_TI_Pos) /*!< 0x00000001 */

+#define ETH_DMACSR_TI                                 ETH_DMACSR_TI_Msk        /* Transmit Interrupt */

+

+/* Bit definition for Ethernet DMA Channel missed frame count register */

+#define ETH_DMACMFCR_MFCO_Pos                         (15U)

+#define ETH_DMACMFCR_MFCO_Msk                         (0x1UL << ETH_DMACMFCR_MFCO_Pos) /*!< 0x00008000 */

+#define ETH_DMACMFCR_MFCO                             ETH_DMACMFCR_MFCO_Msk    /* Overflow status of the MFC Counter */

+#define ETH_DMACMFCR_MFC_Pos                          (0U)

+#define ETH_DMACMFCR_MFC_Msk                          (0x7FFUL << ETH_DMACMFCR_MFC_Pos) /*!< 0x000007FF */

+#define ETH_DMACMFCR_MFC                              ETH_DMACMFCR_MFC_Msk     /* The number of packet counters dropped by the DMA */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             DMA Controller                                 */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DMA_SxCR register  *****************/

+#define DMA_SxCR_MBURST_Pos      (23U)

+#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                /*!< 0x01800000 */

+#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk                           /*!< Memory burst transfer configuration */

+#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */

+#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */

+#define DMA_SxCR_PBURST_Pos      (21U)

+#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                /*!< 0x00600000 */

+#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk                           /*!< Peripheral burst transfer configuration */

+#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */

+#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */

+#define DMA_SxCR_TRBUFF_Pos      (20U)

+#define DMA_SxCR_TRBUFF_Msk      (0x1UL << DMA_SxCR_TRBUFF_Pos)                 /*!< 0x00100000 */

+#define DMA_SxCR_TRBUFF          DMA_SxCR_TRBUFF_Msk                            /*!< bufferable transfers enabled/disable */

+#define DMA_SxCR_CT_Pos          (19U)

+#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                    /*!< 0x00080000 */

+#define DMA_SxCR_CT              DMA_SxCR_CT_Msk                               /*!< Current target (only in double buffer mode) */

+#define DMA_SxCR_DBM_Pos         (18U)

+#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                   /*!< 0x00040000 */

+#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk                              /*!< Double buffer mode */

+#define DMA_SxCR_PL_Pos          (16U)

+#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                    /*!< 0x00030000 */

+#define DMA_SxCR_PL              DMA_SxCR_PL_Msk                               /*!< Priority level */

+#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */

+#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */

+#define DMA_SxCR_PINCOS_Pos      (15U)

+#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                /*!< 0x00008000 */

+#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk                           /*!< Peripheral increment offset size */

+#define DMA_SxCR_MSIZE_Pos       (13U)

+#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                 /*!< 0x00006000 */

+#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk                            /*!< Memory data size */

+#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */

+#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */

+#define DMA_SxCR_PSIZE_Pos       (11U)

+#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                 /*!< 0x00001800 */

+#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk                            /*< Peripheral data size */

+#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */

+#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */

+#define DMA_SxCR_MINC_Pos        (10U)

+#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                  /*!< 0x00000400 */

+#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk                             /*!< Memory increment mode */

+#define DMA_SxCR_PINC_Pos        (9U)

+#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                  /*!< 0x00000200 */

+#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk                             /*!< Peripheral increment mode */

+#define DMA_SxCR_CIRC_Pos        (8U)

+#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                  /*!< 0x00000100 */

+#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk                             /*!< Circular mode */

+#define DMA_SxCR_DIR_Pos         (6U)

+#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                   /*!< 0x000000C0 */

+#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk                              /*!< Data transfer direction */

+#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */

+#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */

+#define DMA_SxCR_PFCTRL_Pos      (5U)

+#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                /*!< 0x00000020 */

+#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk                           /*!< Peripheral flow controller */

+#define DMA_SxCR_TCIE_Pos        (4U)

+#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                  /*!< 0x00000010 */

+#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk                             /*!< Transfer complete interrupt enable */

+#define DMA_SxCR_HTIE_Pos        (3U)

+#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                  /*!< 0x00000008 */

+#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk                             /*!< Half transfer interrupt enable */

+#define DMA_SxCR_TEIE_Pos        (2U)

+#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                  /*!< 0x00000004 */

+#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk                             /*!< Transfer error interrupt enable */

+#define DMA_SxCR_DMEIE_Pos       (1U)

+#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                 /*!< 0x00000002 */

+#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk                            /*!< Direct mode error interrupt enable */

+#define DMA_SxCR_EN_Pos          (0U)

+#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                    /*!< 0x00000001 */

+#define DMA_SxCR_EN              DMA_SxCR_EN_Msk                               /*!< Stream enable / flag stream ready when read low */

+

+/********************  Bits definition for DMA_SxCNDTR register  **************/

+#define DMA_SxNDT_Pos            (0U)

+#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                   /*!< 0x0000FFFF */

+#define DMA_SxNDT                DMA_SxNDT_Msk                                 /*!< Number of data items to transfer */

+#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */

+#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */

+#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */

+#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */

+#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */

+#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */

+#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */

+#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */

+#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */

+#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */

+#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */

+#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */

+#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */

+#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */

+#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */

+#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */

+

+/********************  Bits definition for DMA_SxFCR register  ****************/

+#define DMA_SxFCR_FEIE_Pos       (7U)

+#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                 /*!< 0x00000080 */

+#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk                            /*!< FIFO error interrupt enable */

+#define DMA_SxFCR_FS_Pos         (3U)

+#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                   /*!< 0x00000038 */

+#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk                              /*!< FIFO status */

+#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */

+#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */

+#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */

+#define DMA_SxFCR_DMDIS_Pos      (2U)

+#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                /*!< 0x00000004 */

+#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk                           /*!< Direct mode disable */

+#define DMA_SxFCR_FTH_Pos        (0U)

+#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                  /*!< 0x00000003 */

+#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk                             /*!< FIFO threshold selection */

+#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */

+#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */

+

+/********************  Bits definition for DMA_LISR register  *****************/

+#define DMA_LISR_TCIF3_Pos       (27U)

+#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                 /*!< 0x08000000 */

+#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk                            /*!<  Stream 3 transfer complete interrupt flag */

+#define DMA_LISR_HTIF3_Pos       (26U)

+#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                 /*!< 0x04000000 */

+#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk                            /*!<  Stream 3 half transfer interrupt flag */

+#define DMA_LISR_TEIF3_Pos       (25U)

+#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                 /*!< 0x02000000 */

+#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk                            /*!<  Stream 3 transfer error interrupt flag */

+#define DMA_LISR_DMEIF3_Pos      (24U)

+#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                /*!< 0x01000000 */

+#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk                           /*!<  Stream 3 direct mode error interrupt flag */

+#define DMA_LISR_FEIF3_Pos       (22U)

+#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                 /*!< 0x00400000 */

+#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk                            /*!<  Stream 3 FIFO error interrupt flag */

+#define DMA_LISR_TCIF2_Pos       (21U)

+#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                 /*!< 0x00200000 */

+#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk                            /*!<  Stream 2 transfer complete interrupt flag */

+#define DMA_LISR_HTIF2_Pos       (20U)

+#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                 /*!< 0x00100000 */

+#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk                            /*!<  Stream 2 half transfer interrupt flag */

+#define DMA_LISR_TEIF2_Pos       (19U)

+#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                 /*!< 0x00080000 */

+#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk                            /*!<  Stream 2 transfer error interrupt flag */

+#define DMA_LISR_DMEIF2_Pos      (18U)

+#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                /*!< 0x00040000 */

+#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk                           /*!<  Stream 2 direct mode error interrupt flag */

+#define DMA_LISR_FEIF2_Pos       (16U)

+#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                 /*!< 0x00010000 */

+#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk                            /*!<  Stream 2 FIFO error interrupt flag */

+#define DMA_LISR_TCIF1_Pos       (11U)

+#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                 /*!< 0x00000800 */

+#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk                            /*!<  Stream 1 transfer complete interrupt flag */

+#define DMA_LISR_HTIF1_Pos       (10U)

+#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                 /*!< 0x00000400 */

+#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk                            /*!<  Stream 1 half transfer interrupt flag */

+#define DMA_LISR_TEIF1_Pos       (9U)

+#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                 /*!< 0x00000200 */

+#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk                            /*!<  Stream 1 transfer error interrupt flag */

+#define DMA_LISR_DMEIF1_Pos      (8U)

+#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                /*!< 0x00000100 */

+#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk                           /*!<  Stream 1 direct mode error interrupt flag */

+#define DMA_LISR_FEIF1_Pos       (6U)

+#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                 /*!< 0x00000040 */

+#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk                            /*!<  Stream 1 FIFO error interrupt flag */

+#define DMA_LISR_TCIF0_Pos       (5U)

+#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                 /*!< 0x00000020 */

+#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk                            /*!<  Stream 0 transfer complete interrupt flag */

+#define DMA_LISR_HTIF0_Pos       (4U)

+#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                 /*!< 0x00000010 */

+#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk                            /*!<  Stream 0 half transfer interrupt flag */

+#define DMA_LISR_TEIF0_Pos       (3U)

+#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                 /*!< 0x00000008 */

+#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk                            /*!<  Stream 0 transfer error interrupt flag */

+#define DMA_LISR_DMEIF0_Pos      (2U)

+#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                /*!< 0x00000004 */

+#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk                           /*!<  Stream 0 direct mode error interrupt flag */

+#define DMA_LISR_FEIF0_Pos       (0U)

+#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                 /*!< 0x00000001 */

+#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk                            /*!<  Stream 0 FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_HISR register  *****************/

+#define DMA_HISR_TCIF7_Pos       (27U)

+#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                 /*!< 0x08000000 */

+#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk                            /*!<  Stream 7 transfer complete interrupt flag */

+#define DMA_HISR_HTIF7_Pos       (26U)

+#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                 /*!< 0x04000000 */

+#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk                            /*!<  Stream 7 half transfer interrupt flag */

+#define DMA_HISR_TEIF7_Pos       (25U)

+#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                 /*!< 0x02000000 */

+#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk                            /*!<  Stream 7 transfer error interrupt flag */

+#define DMA_HISR_DMEIF7_Pos      (24U)

+#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                /*!< 0x01000000 */

+#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk                           /*!<  Stream 7 direct mode error interrupt flag */

+#define DMA_HISR_FEIF7_Pos       (22U)

+#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                 /*!< 0x00400000 */

+#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk                            /*!<  Stream 7 FIFO error interrupt flag */

+#define DMA_HISR_TCIF6_Pos       (21U)

+#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                 /*!< 0x00200000 */

+#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk                            /*!<  Stream 6 transfer complete interrupt flag */

+#define DMA_HISR_HTIF6_Pos       (20U)

+#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                 /*!< 0x00100000 */

+#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk                            /*!<  Stream 6 half transfer interrupt flag */

+#define DMA_HISR_TEIF6_Pos       (19U)

+#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                 /*!< 0x00080000 */

+#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk                            /*!<  Stream 6 transfer error interrupt flag */

+#define DMA_HISR_DMEIF6_Pos      (18U)

+#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                /*!< 0x00040000 */

+#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk                           /*!<  Stream 6 direct mode error interrupt flag */

+#define DMA_HISR_FEIF6_Pos       (16U)

+#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                 /*!< 0x00010000 */

+#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk                            /*!<  Stream 6 FIFO error interrupt flag */

+#define DMA_HISR_TCIF5_Pos       (11U)

+#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                 /*!< 0x00000800 */

+#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk                            /*!<  Stream 5 transfer complete interrupt flag */

+#define DMA_HISR_HTIF5_Pos       (10U)

+#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                 /*!< 0x00000400 */

+#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk                            /*!<  Stream 5 half transfer interrupt flag */

+#define DMA_HISR_TEIF5_Pos       (9U)

+#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                 /*!< 0x00000200 */

+#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk                            /*!<  Stream 5 transfer error interrupt flag */

+#define DMA_HISR_DMEIF5_Pos      (8U)

+#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                /*!< 0x00000100 */

+#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk                           /*!<  Stream 5 direct mode error interrupt flag */

+#define DMA_HISR_FEIF5_Pos       (6U)

+#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                 /*!< 0x00000040 */

+#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk                            /*!<  Stream 5 FIFO error interrupt flag */

+#define DMA_HISR_TCIF4_Pos       (5U)

+#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                 /*!< 0x00000020 */

+#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk                            /*!<  Stream 4 transfer complete interrupt flag */

+#define DMA_HISR_HTIF4_Pos       (4U)

+#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                 /*!< 0x00000010 */

+#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk                            /*!<  Stream 4 half transfer interrupt flag */

+#define DMA_HISR_TEIF4_Pos       (3U)

+#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                 /*!< 0x00000008 */

+#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk                            /*!<  Stream 4 transfer error interrupt flag */

+#define DMA_HISR_DMEIF4_Pos      (2U)

+#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                /*!< 0x00000004 */

+#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk                           /*!<  Stream 4 direct mode error interrupt flag */

+#define DMA_HISR_FEIF4_Pos       (0U)

+#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                 /*!< 0x00000001 */

+#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk                            /*!<  Stream 4 FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_LIFCR register  ****************/

+#define DMA_LIFCR_CTCIF3_Pos     (27U)

+#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)               /*!< 0x08000000 */

+#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk                          /*!<  Stream 3 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF3_Pos     (26U)

+#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)               /*!< 0x04000000 */

+#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk                          /*!<  Stream 3 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF3_Pos     (25U)

+#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)               /*!< 0x02000000 */

+#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk                          /*!<  Stream 3 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF3_Pos    (24U)

+#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)              /*!< 0x01000000 */

+#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk                         /*!<  Stream 3 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF3_Pos     (22U)

+#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)               /*!< 0x00400000 */

+#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk                          /*!<  Stream 3 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF2_Pos     (21U)

+#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)               /*!< 0x00200000 */

+#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk                          /*!<  Stream 2 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF2_Pos     (20U)

+#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)               /*!< 0x00100000 */

+#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk                          /*!<  Stream 2 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF2_Pos     (19U)

+#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)               /*!< 0x00080000 */

+#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk                          /*!<  Stream 2 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF2_Pos    (18U)

+#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)              /*!< 0x00040000 */

+#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk                         /*!<  Stream 2 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF2_Pos     (16U)

+#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)               /*!< 0x00010000 */

+#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk                          /*!<  Stream 2 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF1_Pos     (11U)

+#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)               /*!< 0x00000800 */

+#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk                          /*!<  Stream 1 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF1_Pos     (10U)

+#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)               /*!< 0x00000400 */

+#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk                          /*!<  Stream 1 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF1_Pos     (9U)

+#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)               /*!< 0x00000200 */

+#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk                          /*!<  Stream 1 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF1_Pos    (8U)

+#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)              /*!< 0x00000100 */

+#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk                         /*!<  Stream 1 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF1_Pos     (6U)

+#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)               /*!< 0x00000040 */

+#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk                          /*!<  Stream 1 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF0_Pos     (5U)

+#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)               /*!< 0x00000020 */

+#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk                          /*!<  Stream 0 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF0_Pos     (4U)

+#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)               /*!< 0x00000010 */

+#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk                          /*!<  Stream 0 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF0_Pos     (3U)

+#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)               /*!< 0x00000008 */

+#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk                          /*!<  Stream 0 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF0_Pos    (2U)

+#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)              /*!< 0x00000004 */

+#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk                         /*!<  Stream 0 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF0_Pos     (0U)

+#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)               /*!< 0x00000001 */

+#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk                          /*!<  Stream 0 clear FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_HIFCR  register  ****************/

+#define DMA_HIFCR_CTCIF7_Pos     (27U)

+#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)               /*!< 0x08000000 */

+#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk                          /*!<  Stream 7 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF7_Pos     (26U)

+#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)               /*!< 0x04000000 */

+#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk                          /*!<  Stream 7 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF7_Pos     (25U)

+#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)               /*!< 0x02000000 */

+#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk                          /*!<  Stream 7 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF7_Pos    (24U)

+#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)              /*!< 0x01000000 */

+#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk                         /*!<  Stream 7 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF7_Pos     (22U)

+#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)               /*!< 0x00400000 */

+#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk                          /*!<  Stream 7 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF6_Pos     (21U)

+#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)               /*!< 0x00200000 */

+#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk                          /*!<  Stream 6 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF6_Pos     (20U)

+#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)               /*!< 0x00100000 */

+#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk                          /*!<  Stream 6 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF6_Pos     (19U)

+#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)               /*!< 0x00080000 */

+#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk                          /*!<  Stream 6 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF6_Pos    (18U)

+#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)              /*!< 0x00040000 */

+#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk                         /*!<  Stream 6 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF6_Pos     (16U)

+#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)               /*!< 0x00010000 */

+#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk                          /*!<  Stream 6 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF5_Pos     (11U)

+#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)               /*!< 0x00000800 */

+#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk                          /*!<  Stream 5 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF5_Pos     (10U)

+#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)               /*!< 0x00000400 */

+#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk                          /*!<  Stream 5 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF5_Pos     (9U)

+#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)               /*!< 0x00000200 */

+#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk                          /*!<  Stream 5 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF5_Pos    (8U)

+#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)              /*!< 0x00000100 */

+#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk                         /*!<  Stream 5 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF5_Pos     (6U)

+#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)               /*!< 0x00000040 */

+#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk                          /*!<  Stream 5 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF4_Pos     (5U)

+#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)               /*!< 0x00000020 */

+#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk                          /*!<  Stream 4 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF4_Pos     (4U)

+#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)               /*!< 0x00000010 */

+#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk                          /*!<  Stream 4 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF4_Pos     (3U)

+#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)               /*!< 0x00000008 */

+#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk                          /*!<  Stream 4 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF4_Pos    (2U)

+#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)              /*!< 0x00000004 */

+#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk                         /*!<  Stream 4 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF4_Pos     (0U)

+#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)               /*!< 0x00000001 */

+#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk                          /*!<  Stream 4 clear FIFO error interrupt flag */

+

+/******************  Bit definition for DMA_SxPAR register  ********************/

+#define DMA_SxPAR_PA_Pos         (0U)

+#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)            /*!< 0xFFFFFFFF */

+#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */

+

+/******************  Bit definition for DMA_SxM0AR register  ********************/

+#define DMA_SxM0AR_M0A_Pos       (0U)

+#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)          /*!< 0xFFFFFFFF */

+#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory 0 Address */

+

+/******************  Bit definition for DMA_SxM1AR register  ********************/

+#define DMA_SxM1AR_M1A_Pos       (0U)

+#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)          /*!< 0xFFFFFFFF */

+#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory 1 Address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             DMAMUX Controller                              */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DMAMUX_CxCR register  **************/

+#define DMAMUX_CxCR_DMAREQ_ID_Pos      (0U)

+#define DMAMUX_CxCR_DMAREQ_ID_Msk      (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)   /*!< 0x000000FF */

+#define DMAMUX_CxCR_DMAREQ_ID          DMAMUX_CxCR_DMAREQ_ID_Msk               /*!<  DMA request identification */

+#define DMAMUX_CxCR_DMAREQ_ID_0        (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000001 */

+#define DMAMUX_CxCR_DMAREQ_ID_1        (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000002 */

+#define DMAMUX_CxCR_DMAREQ_ID_2        (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000004 */

+#define DMAMUX_CxCR_DMAREQ_ID_3        (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000008 */

+#define DMAMUX_CxCR_DMAREQ_ID_4        (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000010 */

+#define DMAMUX_CxCR_DMAREQ_ID_5        (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000020 */

+#define DMAMUX_CxCR_DMAREQ_ID_6        (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000040 */

+#define DMAMUX_CxCR_DMAREQ_ID_7        (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000080 */

+#define DMAMUX_CxCR_SOIE_Pos           (8U)

+#define DMAMUX_CxCR_SOIE_Msk           (0x1UL << DMAMUX_CxCR_SOIE_Pos)         /*!< 0x00000100 */

+#define DMAMUX_CxCR_SOIE               DMAMUX_CxCR_SOIE_Msk                    /*!<  Synchronization overrun interrupt enable */

+#define DMAMUX_CxCR_EGE_Pos            (9U)

+#define DMAMUX_CxCR_EGE_Msk            (0x1UL << DMAMUX_CxCR_EGE_Pos)          /*!< 0x00000200 */

+#define DMAMUX_CxCR_EGE                DMAMUX_CxCR_EGE_Msk                     /*!<  Event generation enable */

+#define DMAMUX_CxCR_SE_Pos             (16U)

+#define DMAMUX_CxCR_SE_Msk             (0x1UL << DMAMUX_CxCR_SE_Pos)           /*!< 0x00010000 */

+#define DMAMUX_CxCR_SE                 DMAMUX_CxCR_SE_Msk                      /*!<  Synchronization enable */

+#define DMAMUX_CxCR_SPOL_Pos           (17U)

+#define DMAMUX_CxCR_SPOL_Msk           (0x3UL << DMAMUX_CxCR_SPOL_Pos)         /*!< 0x00060000 */

+#define DMAMUX_CxCR_SPOL               DMAMUX_CxCR_SPOL_Msk                    /*!<  Synchronization polarity */

+#define DMAMUX_CxCR_SPOL_0             (0x1UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00020000 */

+#define DMAMUX_CxCR_SPOL_1             (0x2UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00040000 */

+#define DMAMUX_CxCR_NBREQ_Pos          (19U)

+#define DMAMUX_CxCR_NBREQ_Msk          (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)       /*!< 0x00F80000 */

+#define DMAMUX_CxCR_NBREQ              DMAMUX_CxCR_NBREQ_Msk                   /*!<  Number of DMA requests minus 1 to forward */

+#define DMAMUX_CxCR_NBREQ_0            (0x01UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00080000 */

+#define DMAMUX_CxCR_NBREQ_1            (0x02UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00100000 */

+#define DMAMUX_CxCR_NBREQ_2            (0x04UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00200000 */

+#define DMAMUX_CxCR_NBREQ_3            (0x08UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00400000 */

+#define DMAMUX_CxCR_NBREQ_4            (0x10UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00800000 */

+#define DMAMUX_CxCR_SYNC_ID_Pos        (24U)

+#define DMAMUX_CxCR_SYNC_ID_Msk        (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)     /*!< 0x1F000000 */

+#define DMAMUX_CxCR_SYNC_ID            DMAMUX_CxCR_SYNC_ID_Msk                 /*!<  Synchronization identification */

+#define DMAMUX_CxCR_SYNC_ID_0          (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x01000000 */

+#define DMAMUX_CxCR_SYNC_ID_1          (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x02000000 */

+#define DMAMUX_CxCR_SYNC_ID_2          (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x04000000 */

+#define DMAMUX_CxCR_SYNC_ID_3          (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x08000000 */

+#define DMAMUX_CxCR_SYNC_ID_4          (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x10000000 */

+

+/********************  Bits definition for DMAMUX_CSR register  **************/

+#define DMAMUX_CSR_SOF0_Pos            (0U)

+#define DMAMUX_CSR_SOF0_Msk            (0x1UL << DMAMUX_CSR_SOF0_Pos)          /*!< 0x00000001 */

+#define DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0_Msk                     /*!< Channel 0 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF1_Pos            (1U)

+#define DMAMUX_CSR_SOF1_Msk            (0x1UL << DMAMUX_CSR_SOF1_Pos)          /*!< 0x00000002 */

+#define DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1_Msk                     /*!< Channel 1 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF2_Pos            (2U)

+#define DMAMUX_CSR_SOF2_Msk            (0x1UL << DMAMUX_CSR_SOF2_Pos)          /*!< 0x00000004 */

+#define DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2_Msk                     /*!< Channel 2 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF3_Pos            (3U)

+#define DMAMUX_CSR_SOF3_Msk            (0x1UL << DMAMUX_CSR_SOF3_Pos)          /*!< 0x00000008 */

+#define DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3_Msk                     /*!< Channel 3 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF4_Pos            (4U)

+#define DMAMUX_CSR_SOF4_Msk            (0x1UL << DMAMUX_CSR_SOF4_Pos)          /*!< 0x00000010 */

+#define DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4_Msk                     /*!< Channel 4 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF5_Pos            (5U)

+#define DMAMUX_CSR_SOF5_Msk            (0x1UL << DMAMUX_CSR_SOF5_Pos)          /*!< 0x00000020 */

+#define DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5_Msk                     /*!< Channel 5 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF6_Pos            (6U)

+#define DMAMUX_CSR_SOF6_Msk            (0x1UL << DMAMUX_CSR_SOF6_Pos)          /*!< 0x00000040 */

+#define DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6_Msk                     /*!< Channel 6 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF7_Pos            (7U)

+#define DMAMUX_CSR_SOF7_Msk            (0x1UL << DMAMUX_CSR_SOF7_Pos)          /*!< 0x00000080 */

+#define DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7_Msk                     /*!< Channel 7 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF8_Pos            (8U)

+#define DMAMUX_CSR_SOF8_Msk            (0x1UL << DMAMUX_CSR_SOF8_Pos)          /*!< 0x00000100 */

+#define DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8_Msk                     /*!< Channel 8 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF9_Pos            (9U)

+#define DMAMUX_CSR_SOF9_Msk            (0x1UL << DMAMUX_CSR_SOF9_Pos)          /*!< 0x00000200 */

+#define DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9_Msk                     /*!< Channel 9 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF10_Pos           (10U)

+#define DMAMUX_CSR_SOF10_Msk           (0x1UL << DMAMUX_CSR_SOF10_Pos)         /*!< 0x00000400 */

+#define DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10_Msk                    /*!< Channel 10 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF11_Pos           (11U)

+#define DMAMUX_CSR_SOF11_Msk           (0x1UL << DMAMUX_CSR_SOF11_Pos)         /*!< 0x00000800 */

+#define DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11_Msk                    /*!< Channel 11 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF12_Pos           (12U)

+#define DMAMUX_CSR_SOF12_Msk           (0x1UL << DMAMUX_CSR_SOF12_Pos)         /*!< 0x00001000 */

+#define DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12_Msk                    /*!< Channel 12 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF13_Pos           (13U)

+#define DMAMUX_CSR_SOF13_Msk           (0x1UL << DMAMUX_CSR_SOF13_Pos)         /*!< 0x00002000 */

+#define DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13_Msk                    /*!< Channel 13 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF14_Pos           (14U)

+#define DMAMUX_CSR_SOF14_Msk           (0x1UL << DMAMUX_CSR_SOF14_Pos)         /*!< 0x00004000 */

+#define DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14_Msk                    /*!< Channel 14 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF15_Pos           (15U)

+#define DMAMUX_CSR_SOF15_Msk           (0x1UL << DMAMUX_CSR_SOF15_Pos)         /*!< 0x00008000 */

+#define DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15_Msk                    /*!< Channel 15 Synchronization overrun event flag */

+

+/********************  Bits definition for DMAMUX_CFR register  **************/

+#define DMAMUX_CFR_CSOF0_Pos           (0U)

+#define DMAMUX_CFR_CSOF0_Msk           (0x1UL << DMAMUX_CFR_CSOF0_Pos)         /*!< 0x00000001 */

+#define DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0_Msk                    /*!< Channel 0 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF1_Pos           (1U)

+#define DMAMUX_CFR_CSOF1_Msk           (0x1UL << DMAMUX_CFR_CSOF1_Pos)         /*!< 0x00000002 */

+#define DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1_Msk                    /*!< Channel 1 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF2_Pos           (2U)

+#define DMAMUX_CFR_CSOF2_Msk           (0x1UL << DMAMUX_CFR_CSOF2_Pos)         /*!< 0x00000004 */

+#define DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2_Msk                    /*!< Channel 2 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF3_Pos           (3U)

+#define DMAMUX_CFR_CSOF3_Msk           (0x1UL << DMAMUX_CFR_CSOF3_Pos)         /*!< 0x00000008 */

+#define DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3_Msk                    /*!< Channel 3 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF4_Pos           (4U)

+#define DMAMUX_CFR_CSOF4_Msk           (0x1UL << DMAMUX_CFR_CSOF4_Pos)         /*!< 0x00000010 */

+#define DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4_Msk                    /*!< Channel 4 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF5_Pos           (5U)

+#define DMAMUX_CFR_CSOF5_Msk           (0x1UL << DMAMUX_CFR_CSOF5_Pos)         /*!< 0x00000020 */

+#define DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5_Msk                    /*!< Channel 5 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF6_Pos           (6U)

+#define DMAMUX_CFR_CSOF6_Msk           (0x1UL << DMAMUX_CFR_CSOF6_Pos)         /*!< 0x00000040 */

+#define DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6_Msk                    /*!< Channel 6 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF7_Pos           (7U)

+#define DMAMUX_CFR_CSOF7_Msk           (0x1UL << DMAMUX_CFR_CSOF7_Pos)         /*!< 0x00000080 */

+#define DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7_Msk                    /*!< Channel 7 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF8_Pos           (8U)

+#define DMAMUX_CFR_CSOF8_Msk           (0x1UL << DMAMUX_CFR_CSOF8_Pos)         /*!< 0x00000100 */

+#define DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8_Msk                    /*!< Channel 8 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF9_Pos           (9U)

+#define DMAMUX_CFR_CSOF9_Msk           (0x1UL << DMAMUX_CFR_CSOF9_Pos)         /*!< 0x00000200 */

+#define DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9_Msk                    /*!< Channel 9 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF10_Pos          (10U)

+#define DMAMUX_CFR_CSOF10_Msk          (0x1UL << DMAMUX_CFR_CSOF10_Pos)        /*!< 0x00000400 */

+#define DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10_Msk                   /*!< Channel 10 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF11_Pos          (11U)

+#define DMAMUX_CFR_CSOF11_Msk          (0x1UL << DMAMUX_CFR_CSOF11_Pos)        /*!< 0x00000800 */

+#define DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11_Msk                   /*!< Channel 11 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF12_Pos          (12U)

+#define DMAMUX_CFR_CSOF12_Msk          (0x1UL << DMAMUX_CFR_CSOF12_Pos)        /*!< 0x00001000 */

+#define DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12_Msk                   /*!< Channel 12 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF13_Pos          (13U)

+#define DMAMUX_CFR_CSOF13_Msk          (0x1UL << DMAMUX_CFR_CSOF13_Pos)        /*!< 0x00002000 */

+#define DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13_Msk                   /*!< Channel 13 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF14_Pos          (14U)

+#define DMAMUX_CFR_CSOF14_Msk          (0x1UL << DMAMUX_CFR_CSOF14_Pos)        /*!< 0x00004000 */

+#define DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14_Msk                   /*!< Channel 14 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF15_Pos          (15U)

+#define DMAMUX_CFR_CSOF15_Msk          (0x1UL << DMAMUX_CFR_CSOF15_Pos)        /*!< 0x00008000 */

+#define DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15_Msk                   /*!< Channel 15 Clear synchronization overrun event flag */

+

+/********************  Bits definition for DMAMUX_RGxCR register  ************/

+#define DMAMUX_RGxCR_SIG_ID_Pos        (0U)

+#define DMAMUX_RGxCR_SIG_ID_Msk        (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)     /*!< 0x0000001F */

+#define DMAMUX_RGxCR_SIG_ID            DMAMUX_RGxCR_SIG_ID_Msk                 /*!< Signal identification */

+#define DMAMUX_RGxCR_SIG_ID_0          (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000001 */

+#define DMAMUX_RGxCR_SIG_ID_1          (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000002 */

+#define DMAMUX_RGxCR_SIG_ID_2          (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000004 */

+#define DMAMUX_RGxCR_SIG_ID_3          (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000008 */

+#define DMAMUX_RGxCR_SIG_ID_4          (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000010 */

+#define DMAMUX_RGxCR_OIE_Pos           (8U)

+#define DMAMUX_RGxCR_OIE_Msk           (0x1UL << DMAMUX_RGxCR_OIE_Pos)         /*!< 0x00000100 */

+#define DMAMUX_RGxCR_OIE               DMAMUX_RGxCR_OIE_Msk                    /*!< Trigger overrun interrupt enable */

+#define DMAMUX_RGxCR_GE_Pos            (16U)

+#define DMAMUX_RGxCR_GE_Msk            (0x1UL << DMAMUX_RGxCR_GE_Pos)          /*!< 0x00010000 */

+#define DMAMUX_RGxCR_GE                DMAMUX_RGxCR_GE_Msk                     /*!< DMA request generator enable */

+#define DMAMUX_RGxCR_GPOL_Pos          (17U)

+#define DMAMUX_RGxCR_GPOL_Msk          (0x3UL << DMAMUX_RGxCR_GPOL_Pos)        /*!< 0x00060000 */

+#define DMAMUX_RGxCR_GPOL              DMAMUX_RGxCR_GPOL_Msk                   /*!< DMA request generator trigger polarity */

+#define DMAMUX_RGxCR_GPOL_0            (0x1UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00020000 */

+#define DMAMUX_RGxCR_GPOL_1            (0x2UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00040000 */

+#define DMAMUX_RGxCR_GNBREQ_Pos        (19U)

+#define DMAMUX_RGxCR_GNBREQ_Msk        (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)     /*!< 0x00F80000 */

+#define DMAMUX_RGxCR_GNBREQ            DMAMUX_RGxCR_GNBREQ_Msk                 /*!< Number of DMA requests to be generated */

+#define DMAMUX_RGxCR_GNBREQ_0          (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00080000 */

+#define DMAMUX_RGxCR_GNBREQ_1          (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00100000 */

+#define DMAMUX_RGxCR_GNBREQ_2          (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00200000 */

+#define DMAMUX_RGxCR_GNBREQ_3          (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00400000 */

+#define DMAMUX_RGxCR_GNBREQ_4          (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00800000 */

+

+/********************  Bits definition for DMAMUX_RGSR register  **************/

+#define DMAMUX_RGSR_OF0_Pos            (0U)

+#define DMAMUX_RGSR_OF0_Msk            (0x1UL << DMAMUX_RGSR_OF0_Pos)          /*!< 0x00000001 */

+#define DMAMUX_RGSR_OF0                DMAMUX_RGSR_OF0_Msk                     /*!< Request generator channel 0 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF1_Pos            (1U)

+#define DMAMUX_RGSR_OF1_Msk            (0x1UL << DMAMUX_RGSR_OF1_Pos)          /*!< 0x00000002 */

+#define DMAMUX_RGSR_OF1                DMAMUX_RGSR_OF1_Msk                     /*!< Request generator channel 1 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF2_Pos            (2U)

+#define DMAMUX_RGSR_OF2_Msk            (0x1UL << DMAMUX_RGSR_OF2_Pos)          /*!< 0x00000004 */

+#define DMAMUX_RGSR_OF2                DMAMUX_RGSR_OF2_Msk                     /*!< Request generator channel 2 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF3_Pos            (3U)

+#define DMAMUX_RGSR_OF3_Msk            (0x1UL << DMAMUX_RGSR_OF3_Pos)          /*!< 0x00000008 */

+#define DMAMUX_RGSR_OF3                DMAMUX_RGSR_OF3_Msk                     /*!< Request generator channel 3 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF4_Pos            (4U)

+#define DMAMUX_RGSR_OF4_Msk            (0x1UL << DMAMUX_RGSR_OF4_Pos)          /*!< 0x00000010 */

+#define DMAMUX_RGSR_OF4                DMAMUX_RGSR_OF4_Msk                     /*!< Request generator channel 4 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF5_Pos            (5U)

+#define DMAMUX_RGSR_OF5_Msk            (0x1UL << DMAMUX_RGSR_OF5_Pos)          /*!< 0x00000020 */

+#define DMAMUX_RGSR_OF5                DMAMUX_RGSR_OF5_Msk                     /*!< Request generator channel 5 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF6_Pos            (6U)

+#define DMAMUX_RGSR_OF6_Msk            (0x1UL << DMAMUX_RGSR_OF6_Pos)          /*!< 0x00000040 */

+#define DMAMUX_RGSR_OF6                DMAMUX_RGSR_OF6_Msk                     /*!< Request generator channel 6 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF7_Pos            (7U)

+#define DMAMUX_RGSR_OF7_Msk            (0x1UL << DMAMUX_RGSR_OF7_Pos)          /*!< 0x00000080 */

+#define DMAMUX_RGSR_OF7                DMAMUX_RGSR_OF7_Msk                     /*!< Request generator channel 7 Trigger overrun event flag */

+

+/********************  Bits definition for DMAMUX_RGCFR register  **************/

+#define DMAMUX_RGCFR_COF0_Pos          (0U)

+#define DMAMUX_RGCFR_COF0_Msk          (0x1UL << DMAMUX_RGCFR_COF0_Pos)        /*!< 0x00000001 */

+#define DMAMUX_RGCFR_COF0              DMAMUX_RGCFR_COF0_Msk                   /*!< Request generator channel 0 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF1_Pos          (1U)

+#define DMAMUX_RGCFR_COF1_Msk          (0x1UL << DMAMUX_RGCFR_COF1_Pos)        /*!< 0x00000002 */

+#define DMAMUX_RGCFR_COF1              DMAMUX_RGCFR_COF1_Msk                   /*!< Request generator channel 1 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF2_Pos          (2U)

+#define DMAMUX_RGCFR_COF2_Msk          (0x1UL << DMAMUX_RGCFR_COF2_Pos)        /*!< 0x00000004 */

+#define DMAMUX_RGCFR_COF2              DMAMUX_RGCFR_COF2_Msk                   /*!< Request generator channel 2 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF3_Pos          (3U)

+#define DMAMUX_RGCFR_COF3_Msk          (0x1UL << DMAMUX_RGCFR_COF3_Pos)        /*!< 0x00000008 */

+#define DMAMUX_RGCFR_COF3              DMAMUX_RGCFR_COF3_Msk                   /*!< Request generator channel 3 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF4_Pos          (4U)

+#define DMAMUX_RGCFR_COF4_Msk          (0x1UL << DMAMUX_RGCFR_COF4_Pos)        /*!< 0x00000010 */

+#define DMAMUX_RGCFR_COF4              DMAMUX_RGCFR_COF4_Msk                   /*!< Request generator channel 4 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF5_Pos          (5U)

+#define DMAMUX_RGCFR_COF5_Msk          (0x1UL << DMAMUX_RGCFR_COF5_Pos)        /*!< 0x00000020 */

+#define DMAMUX_RGCFR_COF5              DMAMUX_RGCFR_COF5_Msk                   /*!< Request generator channel 5 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF6_Pos          (6U)

+#define DMAMUX_RGCFR_COF6_Msk          (0x1UL << DMAMUX_RGCFR_COF6_Pos)        /*!< 0x00000040 */

+#define DMAMUX_RGCFR_COF6              DMAMUX_RGCFR_COF6_Msk                   /*!< Request generator channel 6 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF7_Pos          (7U)

+#define DMAMUX_RGCFR_COF7_Msk          (0x1UL << DMAMUX_RGCFR_COF7_Pos)        /*!< 0x00000080 */

+#define DMAMUX_RGCFR_COF7              DMAMUX_RGCFR_COF7_Msk                   /*!< Request generator channel 7 Clear trigger overrun event flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         AHB Master DMA2D Controller (DMA2D)                */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for DMA2D_CR register  ******************/

+

+#define DMA2D_CR_START_Pos         (0U)

+#define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)               /*!< 0x00000001 */

+#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer                          */

+#define DMA2D_CR_SUSP_Pos          (1U)

+#define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                /*!< 0x00000002 */

+#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer                        */

+#define DMA2D_CR_ABORT_Pos         (2U)

+#define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)               /*!< 0x00000004 */

+#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer                          */

+#define DMA2D_CR_LOM_Pos           (6U)

+#define DMA2D_CR_LOM_Msk           (0x1UL << DMA2D_CR_LOM_Pos)                 /*!< 0x00000040 */

+#define DMA2D_CR_LOM               DMA2D_CR_LOM_Msk                            /*!< Line Offset Mode                         */

+#define DMA2D_CR_TEIE_Pos          (8U)

+#define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                /*!< 0x00000100 */

+#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable         */

+#define DMA2D_CR_TCIE_Pos          (9U)

+#define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                /*!< 0x00000200 */

+#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable      */

+#define DMA2D_CR_TWIE_Pos          (10U)

+#define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                /*!< 0x00000400 */

+#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable     */

+#define DMA2D_CR_CAEIE_Pos         (11U)

+#define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)               /*!< 0x00000800 */

+#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable      */

+#define DMA2D_CR_CTCIE_Pos         (12U)

+#define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)               /*!< 0x00001000 */

+#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */

+#define DMA2D_CR_CEIE_Pos          (13U)

+#define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                /*!< 0x00002000 */

+#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable    */

+#define DMA2D_CR_MODE_Pos          (16U)

+#define DMA2D_CR_MODE_Msk          (0x7UL << DMA2D_CR_MODE_Pos)                /*!< 0x00070000 */

+#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[2:0]                         */

+#define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */

+#define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */

+#define DMA2D_CR_MODE_2            (0x4UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00040000 */

+

+/********************  Bit definition for DMA2D_ISR register  *****************/

+

+#define DMA2D_ISR_TEIF_Pos         (0U)

+#define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)               /*!< 0x00000001 */

+#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag         */

+#define DMA2D_ISR_TCIF_Pos         (1U)

+#define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)               /*!< 0x00000002 */

+#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag      */

+#define DMA2D_ISR_TWIF_Pos         (2U)

+#define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)               /*!< 0x00000004 */

+#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag     */

+#define DMA2D_ISR_CAEIF_Pos        (3U)

+#define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)              /*!< 0x00000008 */

+#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag      */

+#define DMA2D_ISR_CTCIF_Pos        (4U)

+#define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)              /*!< 0x00000010 */

+#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */

+#define DMA2D_ISR_CEIF_Pos         (5U)

+#define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)               /*!< 0x00000020 */

+#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag    */

+

+/********************  Bit definition for DMA2D_IFCR register  ****************/

+

+#define DMA2D_IFCR_CTEIF_Pos       (0U)

+#define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)             /*!< 0x00000001 */

+#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */

+#define DMA2D_IFCR_CTCIF_Pos       (1U)

+#define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)             /*!< 0x00000002 */

+#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */

+#define DMA2D_IFCR_CTWIF_Pos       (2U)

+#define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)             /*!< 0x00000004 */

+#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */

+#define DMA2D_IFCR_CAECIF_Pos      (3U)

+#define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)            /*!< 0x00000008 */

+#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */

+#define DMA2D_IFCR_CCTCIF_Pos      (4U)

+#define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)            /*!< 0x00000010 */

+#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */

+#define DMA2D_IFCR_CCEIF_Pos       (5U)

+#define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)             /*!< 0x00000020 */

+#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */

+

+/********************  Bit definition for DMA2D_FGMAR register  ***************/

+

+#define DMA2D_FGMAR_MA_Pos         (0U)

+#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)        /*!< 0xFFFFFFFF */

+#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Foreground Memory Address */

+

+/********************  Bit definition for DMA2D_FGOR register  ****************/

+

+#define DMA2D_FGOR_LO_Pos          (0U)

+#define DMA2D_FGOR_LO_Msk          (0xFFFFUL << DMA2D_FGOR_LO_Pos)             /*!< 0x0000FFFF */

+#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */

+

+/********************  Bit definition for DMA2D_BGMAR register  ***************/

+

+#define DMA2D_BGMAR_MA_Pos         (0U)

+#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)        /*!< 0xFFFFFFFF */

+#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Background Memory Address */

+

+/********************  Bit definition for DMA2D_BGOR register  ****************/

+

+#define DMA2D_BGOR_LO_Pos          (0U)

+#define DMA2D_BGOR_LO_Msk          (0xFFFFUL << DMA2D_BGOR_LO_Pos)             /*!< 0x0000FFFF */

+#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */

+

+/********************  Bit definition for DMA2D_FGPFCCR register  *************/

+

+#define DMA2D_FGPFCCR_CM_Pos       (0U)

+#define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x0000000F */

+#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */

+#define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */

+#define DMA2D_FGPFCCR_CCM_Pos      (4U)

+#define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)            /*!< 0x00000010 */

+#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */

+#define DMA2D_FGPFCCR_START_Pos    (5U)

+#define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)          /*!< 0x00000020 */

+#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */

+#define DMA2D_FGPFCCR_CS_Pos       (8U)

+#define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)            /*!< 0x0000FF00 */

+#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */

+#define DMA2D_FGPFCCR_AM_Pos       (16U)

+#define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00030000 */

+#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */

+#define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */

+#define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */

+#define DMA2D_FGPFCCR_CSS_Pos      (18U)

+#define DMA2D_FGPFCCR_CSS_Msk      (0x3UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x000C0000 */

+#define DMA2D_FGPFCCR_CSS          DMA2D_FGPFCCR_CSS_Msk                       /* !< Chroma Sub-Sampling */

+#define DMA2D_FGPFCCR_CSS_0        (0x1UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00040000 */

+#define DMA2D_FGPFCCR_CSS_1        (0x2UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00080000 */

+#define DMA2D_FGPFCCR_AI_Pos       (20U)

+#define DMA2D_FGPFCCR_AI_Msk       (0x1UL << DMA2D_FGPFCCR_AI_Pos)             /*!< 0x00100000 */

+#define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Foreground Input Alpha Inverted */

+#define DMA2D_FGPFCCR_RBS_Pos      (21U)

+#define DMA2D_FGPFCCR_RBS_Msk      (0x1UL << DMA2D_FGPFCCR_RBS_Pos)            /*!< 0x00200000 */

+#define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Foreground Input Red Blue Swap */

+#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)

+#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */

+#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */

+

+/********************  Bit definition for DMA2D_FGCOLR register  **************/

+

+#define DMA2D_FGCOLR_BLUE_Pos      (0U)

+#define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)           /*!< 0x000000FF */

+#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Foreground Blue Value */

+#define DMA2D_FGCOLR_GREEN_Pos     (8U)

+#define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */

+#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Foreground Green Value */

+#define DMA2D_FGCOLR_RED_Pos       (16U)

+#define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)            /*!< 0x00FF0000 */

+#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Foreground Red Value */

+

+/********************  Bit definition for DMA2D_BGPFCCR register  *************/

+

+#define DMA2D_BGPFCCR_CM_Pos       (0U)

+#define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x0000000F */

+#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */

+#define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_BGPFCCR_CM_3         (0x8UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000008 */

+#define DMA2D_BGPFCCR_CCM_Pos      (4U)

+#define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)            /*!< 0x00000010 */

+#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */

+#define DMA2D_BGPFCCR_START_Pos    (5U)

+#define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)          /*!< 0x00000020 */

+#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */

+#define DMA2D_BGPFCCR_CS_Pos       (8U)

+#define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)            /*!< 0x0000FF00 */

+#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */

+#define DMA2D_BGPFCCR_AM_Pos       (16U)

+#define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00030000 */

+#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */

+#define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */

+#define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */

+#define DMA2D_BGPFCCR_AI_Pos       (20U)

+#define DMA2D_BGPFCCR_AI_Msk       (0x1UL << DMA2D_BGPFCCR_AI_Pos)             /*!< 0x00100000 */

+#define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< background Input Alpha Inverted */

+#define DMA2D_BGPFCCR_RBS_Pos      (21U)

+#define DMA2D_BGPFCCR_RBS_Msk      (0x1UL << DMA2D_BGPFCCR_RBS_Pos)            /*!< 0x00200000 */

+#define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Background Input Red Blue Swap */

+#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)

+#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */

+#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */

+

+/********************  Bit definition for DMA2D_BGCOLR register  **************/

+

+#define DMA2D_BGCOLR_BLUE_Pos      (0U)

+#define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)           /*!< 0x000000FF */

+#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Background Blue Value */

+#define DMA2D_BGCOLR_GREEN_Pos     (8U)

+#define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */

+#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Background Green Value */

+#define DMA2D_BGCOLR_RED_Pos       (16U)

+#define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)            /*!< 0x00FF0000 */

+#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Background Red Value */

+

+/********************  Bit definition for DMA2D_FGCMAR register  **************/

+

+#define DMA2D_FGCMAR_MA_Pos        (0U)

+#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */

+#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Foreground CLUT Memory Address */

+

+/********************  Bit definition for DMA2D_BGCMAR register  **************/

+

+#define DMA2D_BGCMAR_MA_Pos        (0U)

+#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */

+#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Background CLUT Memory Address */

+

+/********************  Bit definition for DMA2D_OPFCCR register  **************/

+

+#define DMA2D_OPFCCR_CM_Pos        (0U)

+#define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000007 */

+#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Output Color mode CM[2:0] */

+#define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_OPFCCR_SB_Pos        (8U)

+#define DMA2D_OPFCCR_SB_Msk        (0x1UL << DMA2D_OPFCCR_SB_Pos)              /*!< 0x00000100 */

+#define DMA2D_OPFCCR_SB            DMA2D_OPFCCR_SB_Msk                         /*!< Swap Bytes */

+#define DMA2D_OPFCCR_AI_Pos        (20U)

+#define DMA2D_OPFCCR_AI_Msk        (0x1UL << DMA2D_OPFCCR_AI_Pos)              /*!< 0x00100000 */

+#define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Output Alpha Inverted */

+#define DMA2D_OPFCCR_RBS_Pos       (21U)

+#define DMA2D_OPFCCR_RBS_Msk       (0x1UL << DMA2D_OPFCCR_RBS_Pos)             /*!< 0x00200000 */

+#define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Output Red Blue Swap */

+

+/********************  Bit definition for DMA2D_OCOLR register  ***************/

+

+/*!<Mode_ARGB8888/RGB888 */

+

+#define DMA2D_OCOLR_BLUE_1_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_1_Msk     (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos)            /*0x000000FFU*/

+#define DMA2D_OCOLR_BLUE_1         DMA2D_OCOLR_BLUE_1_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_1_Pos    (8U)

+#define DMA2D_OCOLR_GREEN_1_Msk    (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos)            /*0x0000FF00U)*/

+#define DMA2D_OCOLR_GREEN_1        DMA2D_OCOLR_GREEN_1_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_1_Pos      (16U)

+#define DMA2D_OCOLR_RED_1_Msk      (0xFFUL << DMA2D_OCOLR_RED_1_Pos)            /*0x00FF0000U */

+#define DMA2D_OCOLR_RED_1          DMA2D_OCOLR_RED_1_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_1_Pos    (24U)

+#define DMA2D_OCOLR_ALPHA_1_Msk    (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos)          /*0xFF000000U*/

+#define DMA2D_OCOLR_ALPHA_1        DMA2D_OCOLR_ALPHA_1_Msk                     /*!< Output Alpha Channel Value */

+

+/*!<Mode_RGB565 */

+#define DMA2D_OCOLR_BLUE_2_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_2_Msk     (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos)            /*0x0000001FU*/

+#define DMA2D_OCOLR_BLUE_2         DMA2D_OCOLR_BLUE_2_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_2_Pos    (5U)

+#define DMA2D_OCOLR_GREEN_2_Msk    (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos)          /* 0x000007E0U */

+#define DMA2D_OCOLR_GREEN_2        DMA2D_OCOLR_GREEN_2_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_2_Pos      (11U)

+#define DMA2D_OCOLR_RED_2_Msk      (0xF8UL<<DMA2D_OCOLR_RED_2_Pos)              /*0x0000F800U*/

+#define DMA2D_OCOLR_RED_2          DMA2D_OCOLR_RED_2_Msk                       /*!< Output Red Value */

+

+/*!<Mode_ARGB1555 */

+#define DMA2D_OCOLR_BLUE_3_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_3_Msk     (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos)           /*0x0000001FU*/

+#define DMA2D_OCOLR_BLUE_3         DMA2D_OCOLR_BLUE_3_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_3_Pos    (5U)

+#define DMA2D_OCOLR_GREEN_3_Msk    (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos)          /*0x000003E0U*/

+#define DMA2D_OCOLR_GREEN_3        DMA2D_OCOLR_GREEN_3_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_3_Pos      (10U)

+#define DMA2D_OCOLR_RED_3_Msk      (0x7CUL << DMA2D_OCOLR_RED_3_Pos)            /* 0x00007C00U*/

+#define DMA2D_OCOLR_RED_3          DMA2D_OCOLR_RED_3_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_3_Pos    (15U)

+#define DMA2D_OCOLR_ALPHA_3_Msk    (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos)           /*0x00008000U*/

+#define DMA2D_OCOLR_ALPHA_3        DMA2D_OCOLR_ALPHA_3_Msk                     /*!< Output Alpha Channel Value */

+

+/*!<Mode_ARGB4444 */

+#define DMA2D_OCOLR_BLUE_4_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_4_Msk     (0xFUL << DMA2D_OCOLR_BLUE_4_Pos)            /*0x0000000FU*/

+#define DMA2D_OCOLR_BLUE_4         DMA2D_OCOLR_BLUE_4_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_4_Pos    (4U)

+#define DMA2D_OCOLR_GREEN_4_Msk    (0xFUL << DMA2D_OCOLR_GREEN_4_Pos)           /*0x000000F0U*/

+#define DMA2D_OCOLR_GREEN_4        DMA2D_OCOLR_GREEN_4_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_4_Pos      (8U)

+#define DMA2D_OCOLR_RED_4_Msk      (0xFUL << DMA2D_OCOLR_RED_4_Pos)             /*0x00000F00U*/

+#define DMA2D_OCOLR_RED_4          DMA2D_OCOLR_RED_4_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_4_Pos    (12U)

+#define DMA2D_OCOLR_ALPHA_4_Msk    (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos)            /*0x0000F000U*/

+#define DMA2D_OCOLR_ALPHA_4        DMA2D_OCOLR_ALPHA_4_Msk                     /*!< Output Alpha Channel Value */

+

+/********************  Bit definition for DMA2D_OMAR register  ****************/

+

+#define DMA2D_OMAR_MA_Pos          (0U)

+#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)         /*!< 0xFFFFFFFF */

+#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Output Memory Address */

+

+/********************  Bit definition for DMA2D_OOR register  *****************/

+

+#define DMA2D_OOR_LO_Pos           (0U)

+#define DMA2D_OOR_LO_Msk           (0xFFFFUL << DMA2D_OOR_LO_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Output Line Offset */

+

+/********************  Bit definition for DMA2D_NLR register  *****************/

+

+#define DMA2D_NLR_NL_Pos           (0U)

+#define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */

+#define DMA2D_NLR_PL_Pos           (16U)

+#define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)              /*!< 0x3FFF0000 */

+#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */

+

+/********************  Bit definition for DMA2D_LWR register  *****************/

+

+#define DMA2D_LWR_LW_Pos           (0U)

+#define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */

+

+/********************  Bit definition for DMA2D_AMTCR register  ***************/

+

+#define DMA2D_AMTCR_EN_Pos         (0U)

+#define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)               /*!< 0x00000001 */

+#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */

+#define DMA2D_AMTCR_DT_Pos         (8U)

+#define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)              /*!< 0x0000FF00 */

+#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */

+

+

+/********************  Bit definition for DMA2D_FGCLUT register  **************/

+

+/********************  Bit definition for DMA2D_BGCLUT register  **************/

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                    External Interrupt/Event Controller                     */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for EXTI_RTSR1 register  *******************/

+#define EXTI_RTSR1_TR_Pos          (0U)

+#define EXTI_RTSR1_TR_Msk          (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)           /*!< 0x003FFFFF */

+#define EXTI_RTSR1_TR              EXTI_RTSR1_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR1_TR0_Pos         (0U)

+#define EXTI_RTSR1_TR0_Msk         (0x1UL << EXTI_RTSR1_TR0_Pos)               /*!< 0x00000001 */

+#define EXTI_RTSR1_TR0             EXTI_RTSR1_TR0_Msk                          /*!< Rising trigger event configuration bit of line 0 */

+#define EXTI_RTSR1_TR1_Pos         (1U)

+#define EXTI_RTSR1_TR1_Msk         (0x1UL << EXTI_RTSR1_TR1_Pos)               /*!< 0x00000002 */

+#define EXTI_RTSR1_TR1             EXTI_RTSR1_TR1_Msk                          /*!< Rising trigger event configuration bit of line 1 */

+#define EXTI_RTSR1_TR2_Pos         (2U)

+#define EXTI_RTSR1_TR2_Msk         (0x1UL << EXTI_RTSR1_TR2_Pos)               /*!< 0x00000004 */

+#define EXTI_RTSR1_TR2             EXTI_RTSR1_TR2_Msk                          /*!< Rising trigger event configuration bit of line 2 */

+#define EXTI_RTSR1_TR3_Pos         (3U)

+#define EXTI_RTSR1_TR3_Msk         (0x1UL << EXTI_RTSR1_TR3_Pos)               /*!< 0x00000008 */

+#define EXTI_RTSR1_TR3             EXTI_RTSR1_TR3_Msk                          /*!< Rising trigger event configuration bit of line 3 */

+#define EXTI_RTSR1_TR4_Pos         (4U)

+#define EXTI_RTSR1_TR4_Msk         (0x1UL << EXTI_RTSR1_TR4_Pos)               /*!< 0x00000010 */

+#define EXTI_RTSR1_TR4             EXTI_RTSR1_TR4_Msk                          /*!< Rising trigger event configuration bit of line 4 */

+#define EXTI_RTSR1_TR5_Pos         (5U)

+#define EXTI_RTSR1_TR5_Msk         (0x1UL << EXTI_RTSR1_TR5_Pos)               /*!< 0x00000020 */

+#define EXTI_RTSR1_TR5             EXTI_RTSR1_TR5_Msk                          /*!< Rising trigger event configuration bit of line 5 */

+#define EXTI_RTSR1_TR6_Pos         (6U)

+#define EXTI_RTSR1_TR6_Msk         (0x1UL << EXTI_RTSR1_TR6_Pos)               /*!< 0x00000040 */

+#define EXTI_RTSR1_TR6             EXTI_RTSR1_TR6_Msk                          /*!< Rising trigger event configuration bit of line 6 */

+#define EXTI_RTSR1_TR7_Pos         (7U)

+#define EXTI_RTSR1_TR7_Msk         (0x1UL << EXTI_RTSR1_TR7_Pos)               /*!< 0x00000080 */

+#define EXTI_RTSR1_TR7             EXTI_RTSR1_TR7_Msk                          /*!< Rising trigger event configuration bit of line 7 */

+#define EXTI_RTSR1_TR8_Pos         (8U)

+#define EXTI_RTSR1_TR8_Msk         (0x1UL << EXTI_RTSR1_TR8_Pos)               /*!< 0x00000100 */

+#define EXTI_RTSR1_TR8             EXTI_RTSR1_TR8_Msk                          /*!< Rising trigger event configuration bit of line 8 */

+#define EXTI_RTSR1_TR9_Pos         (9U)

+#define EXTI_RTSR1_TR9_Msk         (0x1UL << EXTI_RTSR1_TR9_Pos)               /*!< 0x00000200 */

+#define EXTI_RTSR1_TR9             EXTI_RTSR1_TR9_Msk                          /*!< Rising trigger event configuration bit of line 9 */

+#define EXTI_RTSR1_TR10_Pos        (10U)

+#define EXTI_RTSR1_TR10_Msk        (0x1UL << EXTI_RTSR1_TR10_Pos)              /*!< 0x00000400 */

+#define EXTI_RTSR1_TR10            EXTI_RTSR1_TR10_Msk                         /*!< Rising trigger event configuration bit of line 10 */

+#define EXTI_RTSR1_TR11_Pos        (11U)

+#define EXTI_RTSR1_TR11_Msk        (0x1UL << EXTI_RTSR1_TR11_Pos)              /*!< 0x00000800 */

+#define EXTI_RTSR1_TR11            EXTI_RTSR1_TR11_Msk                         /*!< Rising trigger event configuration bit of line 11 */

+#define EXTI_RTSR1_TR12_Pos        (12U)

+#define EXTI_RTSR1_TR12_Msk        (0x1UL << EXTI_RTSR1_TR12_Pos)              /*!< 0x00001000 */

+#define EXTI_RTSR1_TR12            EXTI_RTSR1_TR12_Msk                         /*!< Rising trigger event configuration bit of line 12 */

+#define EXTI_RTSR1_TR13_Pos        (13U)

+#define EXTI_RTSR1_TR13_Msk        (0x1UL << EXTI_RTSR1_TR13_Pos)              /*!< 0x00002000 */

+#define EXTI_RTSR1_TR13            EXTI_RTSR1_TR13_Msk                         /*!< Rising trigger event configuration bit of line 13 */

+#define EXTI_RTSR1_TR14_Pos        (14U)

+#define EXTI_RTSR1_TR14_Msk        (0x1UL << EXTI_RTSR1_TR14_Pos)              /*!< 0x00004000 */

+#define EXTI_RTSR1_TR14            EXTI_RTSR1_TR14_Msk                         /*!< Rising trigger event configuration bit of line 14 */

+#define EXTI_RTSR1_TR15_Pos        (15U)

+#define EXTI_RTSR1_TR15_Msk        (0x1UL << EXTI_RTSR1_TR15_Pos)              /*!< 0x00008000 */

+#define EXTI_RTSR1_TR15            EXTI_RTSR1_TR15_Msk                         /*!< Rising trigger event configuration bit of line 15 */

+#define EXTI_RTSR1_TR16_Pos        (16U)

+#define EXTI_RTSR1_TR16_Msk        (0x1UL << EXTI_RTSR1_TR16_Pos)              /*!< 0x00010000 */

+#define EXTI_RTSR1_TR16            EXTI_RTSR1_TR16_Msk                         /*!< Rising trigger event configuration bit of line 16 */

+#define EXTI_RTSR1_TR17_Pos        (17U)

+#define EXTI_RTSR1_TR17_Msk        (0x1UL << EXTI_RTSR1_TR17_Pos)              /*!< 0x00020000 */

+#define EXTI_RTSR1_TR17            EXTI_RTSR1_TR17_Msk                         /*!< Rising trigger event configuration bit of line 17 */

+#define EXTI_RTSR1_TR18_Pos        (18U)

+#define EXTI_RTSR1_TR18_Msk        (0x1UL << EXTI_RTSR1_TR18_Pos)              /*!< 0x00040000 */

+#define EXTI_RTSR1_TR18            EXTI_RTSR1_TR18_Msk                         /*!< Rising trigger event configuration bit of line 18 */

+#define EXTI_RTSR1_TR19_Pos        (19U)

+#define EXTI_RTSR1_TR19_Msk        (0x1UL << EXTI_RTSR1_TR19_Pos)              /*!< 0x00080000 */

+#define EXTI_RTSR1_TR19            EXTI_RTSR1_TR19_Msk                         /*!< Rising trigger event configuration bit of line 19 */

+#define EXTI_RTSR1_TR20_Pos        (20U)

+#define EXTI_RTSR1_TR20_Msk        (0x1UL << EXTI_RTSR1_TR20_Pos)              /*!< 0x00100000 */

+#define EXTI_RTSR1_TR20            EXTI_RTSR1_TR20_Msk                         /*!< Rising trigger event configuration bit of line 20 */

+#define EXTI_RTSR1_TR21_Pos        (21U)

+#define EXTI_RTSR1_TR21_Msk        (0x1UL << EXTI_RTSR1_TR21_Pos)              /*!< 0x00200000 */

+#define EXTI_RTSR1_TR21            EXTI_RTSR1_TR21_Msk                         /*!< Rising trigger event configuration bit of line 21 */

+

+/******************  Bit definition for EXTI_FTSR1 register  *******************/

+#define EXTI_FTSR1_TR_Pos          (0U)

+#define EXTI_FTSR1_TR_Msk          (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)           /*!< 0x003FFFFF */

+#define EXTI_FTSR1_TR              EXTI_FTSR1_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR1_TR0_Pos         (0U)

+#define EXTI_FTSR1_TR0_Msk         (0x1UL << EXTI_FTSR1_TR0_Pos)               /*!< 0x00000001 */

+#define EXTI_FTSR1_TR0             EXTI_FTSR1_TR0_Msk                          /*!< Falling trigger event configuration bit of line 0 */

+#define EXTI_FTSR1_TR1_Pos         (1U)

+#define EXTI_FTSR1_TR1_Msk         (0x1UL << EXTI_FTSR1_TR1_Pos)               /*!< 0x00000002 */

+#define EXTI_FTSR1_TR1             EXTI_FTSR1_TR1_Msk                          /*!< Falling trigger event configuration bit of line 1 */

+#define EXTI_FTSR1_TR2_Pos         (2U)

+#define EXTI_FTSR1_TR2_Msk         (0x1UL << EXTI_FTSR1_TR2_Pos)               /*!< 0x00000004 */

+#define EXTI_FTSR1_TR2             EXTI_FTSR1_TR2_Msk                          /*!< Falling trigger event configuration bit of line 2 */

+#define EXTI_FTSR1_TR3_Pos         (3U)

+#define EXTI_FTSR1_TR3_Msk         (0x1UL << EXTI_FTSR1_TR3_Pos)               /*!< 0x00000008 */

+#define EXTI_FTSR1_TR3             EXTI_FTSR1_TR3_Msk                          /*!< Falling trigger event configuration bit of line 3 */

+#define EXTI_FTSR1_TR4_Pos         (4U)

+#define EXTI_FTSR1_TR4_Msk         (0x1UL << EXTI_FTSR1_TR4_Pos)               /*!< 0x00000010 */

+#define EXTI_FTSR1_TR4             EXTI_FTSR1_TR4_Msk                          /*!< Falling trigger event configuration bit of line 4 */

+#define EXTI_FTSR1_TR5_Pos         (5U)

+#define EXTI_FTSR1_TR5_Msk         (0x1UL << EXTI_FTSR1_TR5_Pos)               /*!< 0x00000020 */

+#define EXTI_FTSR1_TR5             EXTI_FTSR1_TR5_Msk                          /*!< Falling trigger event configuration bit of line 5 */

+#define EXTI_FTSR1_TR6_Pos         (6U)

+#define EXTI_FTSR1_TR6_Msk         (0x1UL << EXTI_FTSR1_TR6_Pos)               /*!< 0x00000040 */

+#define EXTI_FTSR1_TR6             EXTI_FTSR1_TR6_Msk                          /*!< Falling trigger event configuration bit of line 6 */

+#define EXTI_FTSR1_TR7_Pos         (7U)

+#define EXTI_FTSR1_TR7_Msk         (0x1UL << EXTI_FTSR1_TR7_Pos)               /*!< 0x00000080 */

+#define EXTI_FTSR1_TR7             EXTI_FTSR1_TR7_Msk                          /*!< Falling trigger event configuration bit of line 7 */

+#define EXTI_FTSR1_TR8_Pos         (8U)

+#define EXTI_FTSR1_TR8_Msk         (0x1UL << EXTI_FTSR1_TR8_Pos)               /*!< 0x00000100 */

+#define EXTI_FTSR1_TR8             EXTI_FTSR1_TR8_Msk                          /*!< Falling trigger event configuration bit of line 8 */

+#define EXTI_FTSR1_TR9_Pos         (9U)

+#define EXTI_FTSR1_TR9_Msk         (0x1UL << EXTI_FTSR1_TR9_Pos)               /*!< 0x00000200 */

+#define EXTI_FTSR1_TR9             EXTI_FTSR1_TR9_Msk                          /*!< Falling trigger event configuration bit of line 9 */

+#define EXTI_FTSR1_TR10_Pos        (10U)

+#define EXTI_FTSR1_TR10_Msk        (0x1UL << EXTI_FTSR1_TR10_Pos)              /*!< 0x00000400 */

+#define EXTI_FTSR1_TR10            EXTI_FTSR1_TR10_Msk                         /*!< Falling trigger event configuration bit of line 10 */

+#define EXTI_FTSR1_TR11_Pos        (11U)

+#define EXTI_FTSR1_TR11_Msk        (0x1UL << EXTI_FTSR1_TR11_Pos)              /*!< 0x00000800 */

+#define EXTI_FTSR1_TR11            EXTI_FTSR1_TR11_Msk                         /*!< Falling trigger event configuration bit of line 11 */

+#define EXTI_FTSR1_TR12_Pos        (12U)

+#define EXTI_FTSR1_TR12_Msk        (0x1UL << EXTI_FTSR1_TR12_Pos)              /*!< 0x00001000 */

+#define EXTI_FTSR1_TR12            EXTI_FTSR1_TR12_Msk                         /*!< Falling trigger event configuration bit of line 12 */

+#define EXTI_FTSR1_TR13_Pos        (13U)

+#define EXTI_FTSR1_TR13_Msk        (0x1UL << EXTI_FTSR1_TR13_Pos)              /*!< 0x00002000 */

+#define EXTI_FTSR1_TR13            EXTI_FTSR1_TR13_Msk                         /*!< Falling trigger event configuration bit of line 13 */

+#define EXTI_FTSR1_TR14_Pos        (14U)

+#define EXTI_FTSR1_TR14_Msk        (0x1UL << EXTI_FTSR1_TR14_Pos)              /*!< 0x00004000 */

+#define EXTI_FTSR1_TR14            EXTI_FTSR1_TR14_Msk                         /*!< Falling trigger event configuration bit of line 14 */

+#define EXTI_FTSR1_TR15_Pos        (15U)

+#define EXTI_FTSR1_TR15_Msk        (0x1UL << EXTI_FTSR1_TR15_Pos)              /*!< 0x00008000 */

+#define EXTI_FTSR1_TR15            EXTI_FTSR1_TR15_Msk                         /*!< Falling trigger event configuration bit of line 15 */

+#define EXTI_FTSR1_TR16_Pos        (16U)

+#define EXTI_FTSR1_TR16_Msk        (0x1UL << EXTI_FTSR1_TR16_Pos)              /*!< 0x00010000 */

+#define EXTI_FTSR1_TR16            EXTI_FTSR1_TR16_Msk                         /*!< Falling trigger event configuration bit of line 16 */

+#define EXTI_FTSR1_TR17_Pos        (17U)

+#define EXTI_FTSR1_TR17_Msk        (0x1UL << EXTI_FTSR1_TR17_Pos)              /*!< 0x00020000 */

+#define EXTI_FTSR1_TR17            EXTI_FTSR1_TR17_Msk                         /*!< Falling trigger event configuration bit of line 17 */

+#define EXTI_FTSR1_TR18_Pos        (18U)

+#define EXTI_FTSR1_TR18_Msk        (0x1UL << EXTI_FTSR1_TR18_Pos)              /*!< 0x00040000 */

+#define EXTI_FTSR1_TR18            EXTI_FTSR1_TR18_Msk                         /*!< Falling trigger event configuration bit of line 18 */

+#define EXTI_FTSR1_TR19_Pos        (19U)

+#define EXTI_FTSR1_TR19_Msk        (0x1UL << EXTI_FTSR1_TR19_Pos)              /*!< 0x00080000 */

+#define EXTI_FTSR1_TR19            EXTI_FTSR1_TR19_Msk                         /*!< Falling trigger event configuration bit of line 19 */

+#define EXTI_FTSR1_TR20_Pos        (20U)

+#define EXTI_FTSR1_TR20_Msk        (0x1UL << EXTI_FTSR1_TR20_Pos)              /*!< 0x00100000 */

+#define EXTI_FTSR1_TR20            EXTI_FTSR1_TR20_Msk                         /*!< Falling trigger event configuration bit of line 20 */

+#define EXTI_FTSR1_TR21_Pos        (21U)

+#define EXTI_FTSR1_TR21_Msk        (0x1UL << EXTI_FTSR1_TR21_Pos)              /*!< 0x00200000 */

+#define EXTI_FTSR1_TR21            EXTI_FTSR1_TR21_Msk                         /*!< Falling trigger event configuration bit of line 21 */

+

+/******************  Bit definition for EXTI_SWIER1 register  ******************/

+#define EXTI_SWIER1_SWIER0_Pos     (0U)

+#define EXTI_SWIER1_SWIER0_Msk     (0x1UL << EXTI_SWIER1_SWIER0_Pos)           /*!< 0x00000001 */

+#define EXTI_SWIER1_SWIER0         EXTI_SWIER1_SWIER0_Msk                      /*!< Software Interrupt on line 0 */

+#define EXTI_SWIER1_SWIER1_Pos     (1U)

+#define EXTI_SWIER1_SWIER1_Msk     (0x1UL << EXTI_SWIER1_SWIER1_Pos)           /*!< 0x00000002 */

+#define EXTI_SWIER1_SWIER1         EXTI_SWIER1_SWIER1_Msk                      /*!< Software Interrupt on line 1 */

+#define EXTI_SWIER1_SWIER2_Pos     (2U)

+#define EXTI_SWIER1_SWIER2_Msk     (0x1UL << EXTI_SWIER1_SWIER2_Pos)           /*!< 0x00000004 */

+#define EXTI_SWIER1_SWIER2         EXTI_SWIER1_SWIER2_Msk                      /*!< Software Interrupt on line 2 */

+#define EXTI_SWIER1_SWIER3_Pos     (3U)

+#define EXTI_SWIER1_SWIER3_Msk     (0x1UL << EXTI_SWIER1_SWIER3_Pos)           /*!< 0x00000008 */

+#define EXTI_SWIER1_SWIER3         EXTI_SWIER1_SWIER3_Msk                      /*!< Software Interrupt on line 3 */

+#define EXTI_SWIER1_SWIER4_Pos     (4U)

+#define EXTI_SWIER1_SWIER4_Msk     (0x1UL << EXTI_SWIER1_SWIER4_Pos)           /*!< 0x00000010 */

+#define EXTI_SWIER1_SWIER4         EXTI_SWIER1_SWIER4_Msk                      /*!< Software Interrupt on line 4 */

+#define EXTI_SWIER1_SWIER5_Pos     (5U)

+#define EXTI_SWIER1_SWIER5_Msk     (0x1UL << EXTI_SWIER1_SWIER5_Pos)           /*!< 0x00000020 */

+#define EXTI_SWIER1_SWIER5         EXTI_SWIER1_SWIER5_Msk                      /*!< Software Interrupt on line 5 */

+#define EXTI_SWIER1_SWIER6_Pos     (6U)

+#define EXTI_SWIER1_SWIER6_Msk     (0x1UL << EXTI_SWIER1_SWIER6_Pos)           /*!< 0x00000040 */

+#define EXTI_SWIER1_SWIER6         EXTI_SWIER1_SWIER6_Msk                      /*!< Software Interrupt on line 6 */

+#define EXTI_SWIER1_SWIER7_Pos     (7U)

+#define EXTI_SWIER1_SWIER7_Msk     (0x1UL << EXTI_SWIER1_SWIER7_Pos)           /*!< 0x00000080 */

+#define EXTI_SWIER1_SWIER7         EXTI_SWIER1_SWIER7_Msk                      /*!< Software Interrupt on line 7 */

+#define EXTI_SWIER1_SWIER8_Pos     (8U)

+#define EXTI_SWIER1_SWIER8_Msk     (0x1UL << EXTI_SWIER1_SWIER8_Pos)           /*!< 0x00000100 */

+#define EXTI_SWIER1_SWIER8         EXTI_SWIER1_SWIER8_Msk                      /*!< Software Interrupt on line 8 */

+#define EXTI_SWIER1_SWIER9_Pos     (9U)

+#define EXTI_SWIER1_SWIER9_Msk     (0x1UL << EXTI_SWIER1_SWIER9_Pos)           /*!< 0x00000200 */

+#define EXTI_SWIER1_SWIER9         EXTI_SWIER1_SWIER9_Msk                      /*!< Software Interrupt on line 9 */

+#define EXTI_SWIER1_SWIER10_Pos    (10U)

+#define EXTI_SWIER1_SWIER10_Msk    (0x1UL << EXTI_SWIER1_SWIER10_Pos)          /*!< 0x00000400 */

+#define EXTI_SWIER1_SWIER10        EXTI_SWIER1_SWIER10_Msk                     /*!< Software Interrupt on line 10 */

+#define EXTI_SWIER1_SWIER11_Pos    (11U)

+#define EXTI_SWIER1_SWIER11_Msk    (0x1UL << EXTI_SWIER1_SWIER11_Pos)          /*!< 0x00000800 */

+#define EXTI_SWIER1_SWIER11        EXTI_SWIER1_SWIER11_Msk                     /*!< Software Interrupt on line 11 */

+#define EXTI_SWIER1_SWIER12_Pos    (12U)

+#define EXTI_SWIER1_SWIER12_Msk    (0x1UL << EXTI_SWIER1_SWIER12_Pos)          /*!< 0x00001000 */

+#define EXTI_SWIER1_SWIER12        EXTI_SWIER1_SWIER12_Msk                     /*!< Software Interrupt on line 12 */

+#define EXTI_SWIER1_SWIER13_Pos    (13U)

+#define EXTI_SWIER1_SWIER13_Msk    (0x1UL << EXTI_SWIER1_SWIER13_Pos)          /*!< 0x00002000 */

+#define EXTI_SWIER1_SWIER13        EXTI_SWIER1_SWIER13_Msk                     /*!< Software Interrupt on line 13 */

+#define EXTI_SWIER1_SWIER14_Pos    (14U)

+#define EXTI_SWIER1_SWIER14_Msk    (0x1UL << EXTI_SWIER1_SWIER14_Pos)          /*!< 0x00004000 */

+#define EXTI_SWIER1_SWIER14        EXTI_SWIER1_SWIER14_Msk                     /*!< Software Interrupt on line 14 */

+#define EXTI_SWIER1_SWIER15_Pos    (15U)

+#define EXTI_SWIER1_SWIER15_Msk    (0x1UL << EXTI_SWIER1_SWIER15_Pos)          /*!< 0x00008000 */

+#define EXTI_SWIER1_SWIER15        EXTI_SWIER1_SWIER15_Msk                     /*!< Software Interrupt on line 15 */

+#define EXTI_SWIER1_SWIER16_Pos    (16U)

+#define EXTI_SWIER1_SWIER16_Msk    (0x1UL << EXTI_SWIER1_SWIER16_Pos)          /*!< 0x00010000 */

+#define EXTI_SWIER1_SWIER16        EXTI_SWIER1_SWIER16_Msk                     /*!< Software Interrupt on line 16 */

+#define EXTI_SWIER1_SWIER17_Pos    (17U)

+#define EXTI_SWIER1_SWIER17_Msk    (0x1UL << EXTI_SWIER1_SWIER17_Pos)          /*!< 0x00020000 */

+#define EXTI_SWIER1_SWIER17        EXTI_SWIER1_SWIER17_Msk                     /*!< Software Interrupt on line 17 */

+#define EXTI_SWIER1_SWIER18_Pos    (18U)

+#define EXTI_SWIER1_SWIER18_Msk    (0x1UL << EXTI_SWIER1_SWIER18_Pos)          /*!< 0x00040000 */

+#define EXTI_SWIER1_SWIER18        EXTI_SWIER1_SWIER18_Msk                     /*!< Software Interrupt on line 18 */

+#define EXTI_SWIER1_SWIER19_Pos    (19U)

+#define EXTI_SWIER1_SWIER19_Msk    (0x1UL << EXTI_SWIER1_SWIER19_Pos)          /*!< 0x00080000 */

+#define EXTI_SWIER1_SWIER19        EXTI_SWIER1_SWIER19_Msk                     /*!< Software Interrupt on line 19 */

+#define EXTI_SWIER1_SWIER20_Pos    (20U)

+#define EXTI_SWIER1_SWIER20_Msk    (0x1UL << EXTI_SWIER1_SWIER20_Pos)          /*!< 0x00100000 */

+#define EXTI_SWIER1_SWIER20        EXTI_SWIER1_SWIER20_Msk                     /*!< Software Interrupt on line 20 */

+#define EXTI_SWIER1_SWIER21_Pos    (21U)

+#define EXTI_SWIER1_SWIER21_Msk    (0x1UL << EXTI_SWIER1_SWIER21_Pos)          /*!< 0x00200000 */

+#define EXTI_SWIER1_SWIER21        EXTI_SWIER1_SWIER21_Msk                     /*!< Software Interrupt on line 21 */

+

+/******************  Bit definition for EXTI_D3PMR1 register  ******************/

+#define EXTI_D3PMR1_MR0_Pos        (0U)

+#define EXTI_D3PMR1_MR0_Msk        (0x1UL << EXTI_D3PMR1_MR0_Pos)              /*!< 0x00000001 */

+#define EXTI_D3PMR1_MR0            EXTI_D3PMR1_MR0_Msk                         /*!< Pending Mask Event for line 0  */

+#define EXTI_D3PMR1_MR1_Pos        (1U)

+#define EXTI_D3PMR1_MR1_Msk        (0x1UL << EXTI_D3PMR1_MR1_Pos)              /*!< 0x00000002 */

+#define EXTI_D3PMR1_MR1            EXTI_D3PMR1_MR1_Msk                         /*!< Pending Mask Event for line 1  */

+#define EXTI_D3PMR1_MR2_Pos        (2U)

+#define EXTI_D3PMR1_MR2_Msk        (0x1UL << EXTI_D3PMR1_MR2_Pos)              /*!< 0x00000004 */

+#define EXTI_D3PMR1_MR2            EXTI_D3PMR1_MR2_Msk                         /*!< Pending Mask Event for line 2  */

+#define EXTI_D3PMR1_MR3_Pos        (3U)

+#define EXTI_D3PMR1_MR3_Msk        (0x1UL << EXTI_D3PMR1_MR3_Pos)              /*!< 0x00000008 */

+#define EXTI_D3PMR1_MR3            EXTI_D3PMR1_MR3_Msk                         /*!< Pending Mask Event for line 3  */

+#define EXTI_D3PMR1_MR4_Pos        (4U)

+#define EXTI_D3PMR1_MR4_Msk        (0x1UL << EXTI_D3PMR1_MR4_Pos)              /*!< 0x00000010 */

+#define EXTI_D3PMR1_MR4            EXTI_D3PMR1_MR4_Msk                         /*!< Pending Mask Event for line 4  */

+#define EXTI_D3PMR1_MR5_Pos        (5U)

+#define EXTI_D3PMR1_MR5_Msk        (0x1UL << EXTI_D3PMR1_MR5_Pos)              /*!< 0x00000020 */

+#define EXTI_D3PMR1_MR5            EXTI_D3PMR1_MR5_Msk                         /*!< Pending Mask Event for line 5  */

+#define EXTI_D3PMR1_MR6_Pos        (6U)

+#define EXTI_D3PMR1_MR6_Msk        (0x1UL << EXTI_D3PMR1_MR6_Pos)              /*!< 0x00000040 */

+#define EXTI_D3PMR1_MR6            EXTI_D3PMR1_MR6_Msk                         /*!< Pending Mask Event for line 6  */

+#define EXTI_D3PMR1_MR7_Pos        (7U)

+#define EXTI_D3PMR1_MR7_Msk        (0x1UL << EXTI_D3PMR1_MR7_Pos)              /*!< 0x00000080 */

+#define EXTI_D3PMR1_MR7            EXTI_D3PMR1_MR7_Msk                         /*!< Pending Mask Event for line 7  */

+#define EXTI_D3PMR1_MR8_Pos        (8U)

+#define EXTI_D3PMR1_MR8_Msk        (0x1UL << EXTI_D3PMR1_MR8_Pos)              /*!< 0x00000100 */

+#define EXTI_D3PMR1_MR8            EXTI_D3PMR1_MR8_Msk                         /*!< Pending Mask Event for line 8  */

+#define EXTI_D3PMR1_MR9_Pos        (9U)

+#define EXTI_D3PMR1_MR9_Msk        (0x1UL << EXTI_D3PMR1_MR9_Pos)              /*!< 0x00000200 */

+#define EXTI_D3PMR1_MR9            EXTI_D3PMR1_MR9_Msk                         /*!< Pending Mask Event for line 9  */

+#define EXTI_D3PMR1_MR10_Pos       (10U)

+#define EXTI_D3PMR1_MR10_Msk       (0x1UL << EXTI_D3PMR1_MR10_Pos)             /*!< 0x00000400 */

+#define EXTI_D3PMR1_MR10           EXTI_D3PMR1_MR10_Msk                        /*!< Pending Mask Event for line 10 */

+#define EXTI_D3PMR1_MR11_Pos       (11U)

+#define EXTI_D3PMR1_MR11_Msk       (0x1UL << EXTI_D3PMR1_MR11_Pos)             /*!< 0x00000800 */

+#define EXTI_D3PMR1_MR11           EXTI_D3PMR1_MR11_Msk                        /*!< Pending Mask Event for line 11 */

+#define EXTI_D3PMR1_MR12_Pos       (12U)

+#define EXTI_D3PMR1_MR12_Msk       (0x1UL << EXTI_D3PMR1_MR12_Pos)             /*!< 0x00001000 */

+#define EXTI_D3PMR1_MR12           EXTI_D3PMR1_MR12_Msk                        /*!< Pending Mask Event for line 12 */

+#define EXTI_D3PMR1_MR13_Pos       (13U)

+#define EXTI_D3PMR1_MR13_Msk       (0x1UL << EXTI_D3PMR1_MR13_Pos)             /*!< 0x00002000 */

+#define EXTI_D3PMR1_MR13           EXTI_D3PMR1_MR13_Msk                        /*!< Pending Mask Event for line 13 */

+#define EXTI_D3PMR1_MR14_Pos       (14U)

+#define EXTI_D3PMR1_MR14_Msk       (0x1UL << EXTI_D3PMR1_MR14_Pos)             /*!< 0x00004000 */

+#define EXTI_D3PMR1_MR14           EXTI_D3PMR1_MR14_Msk                        /*!< Pending Mask Event for line 14 */

+#define EXTI_D3PMR1_MR15_Pos       (15U)

+#define EXTI_D3PMR1_MR15_Msk       (0x1UL << EXTI_D3PMR1_MR15_Pos)             /*!< 0x00008000 */

+#define EXTI_D3PMR1_MR15           EXTI_D3PMR1_MR15_Msk                        /*!< Pending Mask Event for line 15 */

+#define EXTI_D3PMR1_MR19_Pos       (19U)

+#define EXTI_D3PMR1_MR19_Msk       (0x1UL << EXTI_D3PMR1_MR19_Pos)             /*!< 0x00080000 */

+#define EXTI_D3PMR1_MR19           EXTI_D3PMR1_MR19_Msk                        /*!< Pending Mask Event for line 19 */

+#define EXTI_D3PMR1_MR20_Pos       (20U)

+#define EXTI_D3PMR1_MR20_Msk       (0x1UL << EXTI_D3PMR1_MR20_Pos)             /*!< 0x00100000 */

+#define EXTI_D3PMR1_MR20           EXTI_D3PMR1_MR20_Msk                        /*!< Pending Mask Event for line 20 */

+#define EXTI_D3PMR1_MR21_Pos       (21U)

+#define EXTI_D3PMR1_MR21_Msk       (0x1UL << EXTI_D3PMR1_MR21_Pos)             /*!< 0x00200000 */

+#define EXTI_D3PMR1_MR21           EXTI_D3PMR1_MR21_Msk                        /*!< Pending Mask Event for line 21 */

+#define EXTI_D3PMR1_MR25_Pos       (24U)

+#define EXTI_D3PMR1_MR25_Msk       (0x1UL << EXTI_D3PMR1_MR25_Pos)             /*!< 0x01000000 */

+#define EXTI_D3PMR1_MR25           EXTI_D3PMR1_MR25_Msk                        /*!< Pending Mask Event for line 25 */

+

+/*******************  Bit definition for EXTI_D3PCR1L register  ****************/

+#define EXTI_D3PCR1L_PCS0_Pos       (0U)

+#define EXTI_D3PCR1L_PCS0_Msk       (0x3UL << EXTI_D3PCR1L_PCS0_Pos)           /*!< 0x00000003 */

+#define EXTI_D3PCR1L_PCS0           EXTI_D3PCR1L_PCS0_Msk                      /*!< D3 Pending request clear input signal selection on line 0 */

+#define EXTI_D3PCR1L_PCS1_Pos       (2U)

+#define EXTI_D3PCR1L_PCS1_Msk       (0x3UL << EXTI_D3PCR1L_PCS1_Pos)           /*!< 0x000000C0 */

+#define EXTI_D3PCR1L_PCS1           EXTI_D3PCR1L_PCS1_Msk                      /*!< D3 Pending request clear input signal selection on line 1 */

+#define EXTI_D3PCR1L_PCS2_Pos       (4U)

+#define EXTI_D3PCR1L_PCS2_Msk       (0x3UL << EXTI_D3PCR1L_PCS2_Pos)           /*!< 0x00000030 */

+#define EXTI_D3PCR1L_PCS2           EXTI_D3PCR1L_PCS2_Msk                      /*!< D3 Pending request clear input signal selection on line 2 */

+#define EXTI_D3PCR1L_PCS3_Pos       (6U)

+#define EXTI_D3PCR1L_PCS3_Msk       (0x3UL << EXTI_D3PCR1L_PCS3_Pos)           /*!< 0x000000C0 */

+#define EXTI_D3PCR1L_PCS3           EXTI_D3PCR1L_PCS3_Msk                      /*!< D3 Pending request clear input signal selection on line 3 */

+#define EXTI_D3PCR1L_PCS4_Pos       (8U)

+#define EXTI_D3PCR1L_PCS4_Msk       (0x3UL << EXTI_D3PCR1L_PCS4_Pos)           /*!< 0x00000300 */

+#define EXTI_D3PCR1L_PCS4           EXTI_D3PCR1L_PCS4_Msk                      /*!< D3 Pending request clear input signal selection on line 4 */

+#define EXTI_D3PCR1L_PCS5_Pos       (10U)

+#define EXTI_D3PCR1L_PCS5_Msk       (0x3UL << EXTI_D3PCR1L_PCS5_Pos)           /*!< 0x00000C00 */

+#define EXTI_D3PCR1L_PCS5           EXTI_D3PCR1L_PCS5_Msk                      /*!< D3 Pending request clear input signal selection on line 5 */

+#define EXTI_D3PCR1L_PCS6_Pos       (12U)

+#define EXTI_D3PCR1L_PCS6_Msk       (0x3UL << EXTI_D3PCR1L_PCS6_Pos)           /*!< 0x00003000 */

+#define EXTI_D3PCR1L_PCS6           EXTI_D3PCR1L_PCS6_Msk                      /*!< D3 Pending request clear input signal selection on line 6 */

+#define EXTI_D3PCR1L_PCS7_Pos       (14U)

+#define EXTI_D3PCR1L_PCS7_Msk       (0x3UL << EXTI_D3PCR1L_PCS7_Pos)           /*!< 0x0000C000 */

+#define EXTI_D3PCR1L_PCS7           EXTI_D3PCR1L_PCS7_Msk                      /*!< D3 Pending request clear input signal selection on line 7 */

+#define EXTI_D3PCR1L_PCS8_Pos       (16U)

+#define EXTI_D3PCR1L_PCS8_Msk       (0x3UL << EXTI_D3PCR1L_PCS8_Pos)           /*!< 0x00030000 */

+#define EXTI_D3PCR1L_PCS8           EXTI_D3PCR1L_PCS8_Msk                      /*!< D3 Pending request clear input signal selection on line 8 */

+#define EXTI_D3PCR1L_PCS9_Pos       (18U)

+#define EXTI_D3PCR1L_PCS9_Msk       (0x3UL << EXTI_D3PCR1L_PCS9_Pos)           /*!< 0x000C0000 */

+#define EXTI_D3PCR1L_PCS9           EXTI_D3PCR1L_PCS9_Msk                      /*!< D3 Pending request clear input signal selection on line 9 */

+#define EXTI_D3PCR1L_PCS10_Pos      (20U)

+#define EXTI_D3PCR1L_PCS10_Msk      (0x3UL << EXTI_D3PCR1L_PCS10_Pos)          /*!< 0x00300000 */

+#define EXTI_D3PCR1L_PCS10          EXTI_D3PCR1L_PCS10_Msk                     /*!< D3 Pending request clear input signal selection on line 10*/

+#define EXTI_D3PCR1L_PCS11_Pos      (22U)

+#define EXTI_D3PCR1L_PCS11_Msk      (0x3UL << EXTI_D3PCR1L_PCS11_Pos)          /*!< 0x00C00000 */

+#define EXTI_D3PCR1L_PCS11          EXTI_D3PCR1L_PCS11_Msk                     /*!< D3 Pending request clear input signal selection on line 11*/

+#define EXTI_D3PCR1L_PCS12_Pos      (24U)

+#define EXTI_D3PCR1L_PCS12_Msk      (0x3UL << EXTI_D3PCR1L_PCS12_Pos)          /*!< 0x03000000 */

+#define EXTI_D3PCR1L_PCS12          EXTI_D3PCR1L_PCS12_Msk                     /*!< D3 Pending request clear input signal selection on line 12*/

+#define EXTI_D3PCR1L_PCS13_Pos      (26U)

+#define EXTI_D3PCR1L_PCS13_Msk      (0x3UL << EXTI_D3PCR1L_PCS13_Pos)          /*!< 0x0C000000 */

+#define EXTI_D3PCR1L_PCS13          EXTI_D3PCR1L_PCS13_Msk                     /*!< D3 Pending request clear input signal selection on line 13*/

+#define EXTI_D3PCR1L_PCS14_Pos      (28U)

+#define EXTI_D3PCR1L_PCS14_Msk      (0x3UL << EXTI_D3PCR1L_PCS14_Pos)          /*!< 0x30000000 */

+#define EXTI_D3PCR1L_PCS14          EXTI_D3PCR1L_PCS14_Msk                     /*!< D3 Pending request clear input signal selection on line 14*/

+#define EXTI_D3PCR1L_PCS15_Pos      (30U)

+#define EXTI_D3PCR1L_PCS15_Msk      (0x3UL << EXTI_D3PCR1L_PCS15_Pos)          /*!< 0xC0000000 */

+#define EXTI_D3PCR1L_PCS15          EXTI_D3PCR1L_PCS15_Msk                     /*!< D3 Pending request clear input signal selection on line 15*/

+

+/*******************  Bit definition for EXTI_D3PCR1H register  ****************/

+#define EXTI_D3PCR1H_PCS19_Pos       (6U)

+#define EXTI_D3PCR1H_PCS19_Msk       (0x3UL << EXTI_D3PCR1H_PCS19_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR1H_PCS19           EXTI_D3PCR1H_PCS19_Msk                    /*!< D3 Pending request clear input signal selection on line 19 */

+#define EXTI_D3PCR1H_PCS20_Pos       (8U)

+#define EXTI_D3PCR1H_PCS20_Msk       (0x3UL << EXTI_D3PCR1H_PCS20_Pos)         /*!< 0x00000300 */

+#define EXTI_D3PCR1H_PCS20           EXTI_D3PCR1H_PCS20_Msk                    /*!< D3 Pending request clear input signal selection on line 20 */

+#define EXTI_D3PCR1H_PCS21_Pos       (10U)

+#define EXTI_D3PCR1H_PCS21_Msk       (0x3UL << EXTI_D3PCR1H_PCS21_Pos)         /*!< 0x00000C00 */

+#define EXTI_D3PCR1H_PCS21           EXTI_D3PCR1H_PCS21_Msk                    /*!< D3 Pending request clear input signal selection on line 21 */

+#define EXTI_D3PCR1H_PCS25_Pos       (18U)

+#define EXTI_D3PCR1H_PCS25_Msk       (0x3UL << EXTI_D3PCR1H_PCS25_Pos)         /*!< 0x000C0000 */

+#define EXTI_D3PCR1H_PCS25           EXTI_D3PCR1H_PCS25_Msk                    /*!< D3 Pending request clear input signal selection on line 25 */

+

+/******************  Bit definition for EXTI_RTSR2 register  *******************/

+#define EXTI_RTSR2_TR_Pos          (17U)

+#define EXTI_RTSR2_TR_Msk          (0x5UL << EXTI_RTSR2_TR_Pos)                /*!< 0x000A0000 */

+#define EXTI_RTSR2_TR              EXTI_RTSR2_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR2_TR49_Pos        (17U)

+#define EXTI_RTSR2_TR49_Msk        (0x1UL << EXTI_RTSR2_TR49_Pos)              /*!< 0x00020000 */

+#define EXTI_RTSR2_TR49            EXTI_RTSR2_TR49_Msk                         /*!< Rising trigger event configuration bit of line 49 */

+#define EXTI_RTSR2_TR51_Pos        (19U)

+#define EXTI_RTSR2_TR51_Msk        (0x1UL << EXTI_RTSR2_TR51_Pos)              /*!< 0x00080000 */

+#define EXTI_RTSR2_TR51            EXTI_RTSR2_TR51_Msk                         /*!< Rising trigger event configuration bit of line 51 */

+

+/******************  Bit definition for EXTI_FTSR2 register  *******************/

+#define EXTI_FTSR2_TR_Pos          (17U)

+#define EXTI_FTSR2_TR_Msk          (0x5UL << EXTI_FTSR2_TR_Pos)                /*!< 0x000A0000 */

+#define EXTI_FTSR2_TR              EXTI_FTSR2_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR2_TR49_Pos        (17U)

+#define EXTI_FTSR2_TR49_Msk        (0x1UL << EXTI_FTSR2_TR49_Pos)              /*!< 0x00020000 */

+#define EXTI_FTSR2_TR49            EXTI_FTSR2_TR49_Msk                         /*!< Falling trigger event configuration bit of line 49 */

+#define EXTI_FTSR2_TR51_Pos        (19U)

+#define EXTI_FTSR2_TR51_Msk        (0x1UL << EXTI_FTSR2_TR51_Pos)              /*!< 0x00080000 */

+#define EXTI_FTSR2_TR51            EXTI_FTSR2_TR51_Msk                         /*!< Falling trigger event configuration bit of line 51 */

+

+/******************  Bit definition for EXTI_SWIER2 register  ******************/

+#define EXTI_SWIER2_SWIER49_Pos    (17U)

+#define EXTI_SWIER2_SWIER49_Msk    (0x1UL << EXTI_SWIER2_SWIER49_Pos)          /*!< 0x00020000 */

+#define EXTI_SWIER2_SWIER49        EXTI_SWIER2_SWIER49_Msk                     /*!< Software Interrupt on line 49 */

+#define EXTI_SWIER2_SWIER51_Pos    (19U)

+#define EXTI_SWIER2_SWIER51_Msk    (0x1UL << EXTI_SWIER2_SWIER51_Pos)          /*!< 0x00080000 */

+#define EXTI_SWIER2_SWIER51        EXTI_SWIER2_SWIER51_Msk                     /*!< Software Interrupt on line 51 */

+

+/******************  Bit definition for EXTI_D3PMR2 register  ******************/

+#define EXTI_D3PMR2_MR34_Pos       (2U)

+#define EXTI_D3PMR2_MR34_Msk       (0x1UL << EXTI_D3PMR2_MR34_Pos)             /*!< 0x00000004 */

+#define EXTI_D3PMR2_MR34           EXTI_D3PMR2_MR34_Msk                        /*!< Pending Mask Event for line 34  */

+#define EXTI_D3PMR2_MR35_Pos       (3U)

+#define EXTI_D3PMR2_MR35_Msk       (0x1UL << EXTI_D3PMR2_MR35_Pos)             /*!< 0x00000008 */

+#define EXTI_D3PMR2_MR35           EXTI_D3PMR2_MR35_Msk                        /*!< Pending Mask Event for line 35  */

+#define EXTI_D3PMR2_MR41_Pos       (9U)

+#define EXTI_D3PMR2_MR41_Msk       (0x1UL << EXTI_D3PMR2_MR41_Pos)             /*!< 0x00000200 */

+#define EXTI_D3PMR2_MR41           EXTI_D3PMR2_MR41_Msk                        /*!< Pending Mask Event for line 41  */

+#define EXTI_D3PMR2_MR48_Pos       (16U)

+#define EXTI_D3PMR2_MR48_Msk       (0x1UL << EXTI_D3PMR2_MR48_Pos)             /*!< 0x00010000 */

+#define EXTI_D3PMR2_MR48           EXTI_D3PMR2_MR48_Msk                        /*!< Pending Mask Event for line 48  */

+#define EXTI_D3PMR2_MR49_Pos       (17U)

+#define EXTI_D3PMR2_MR49_Msk       (0x1UL << EXTI_D3PMR2_MR49_Pos)             /*!< 0x00020000 */

+#define EXTI_D3PMR2_MR49           EXTI_D3PMR2_MR49_Msk                        /*!< Pending Mask Event for line 49  */

+#define EXTI_D3PMR2_MR50_Pos       (18U)

+#define EXTI_D3PMR2_MR50_Msk       (0x1UL << EXTI_D3PMR2_MR50_Pos)             /*!< 0x00040000 */

+#define EXTI_D3PMR2_MR50           EXTI_D3PMR2_MR50_Msk                        /*!< Pending Mask Event for line 50  */

+#define EXTI_D3PMR2_MR51_Pos       (19U)

+#define EXTI_D3PMR2_MR51_Msk       (0x1UL << EXTI_D3PMR2_MR51_Pos)             /*!< 0x00080000 */

+#define EXTI_D3PMR2_MR51           EXTI_D3PMR2_MR51_Msk                        /*!< Pending Mask Event for line 51  */

+#define EXTI_D3PMR2_MR52_Pos       (20U)

+#define EXTI_D3PMR2_MR52_Msk       (0x1UL << EXTI_D3PMR2_MR52_Pos)             /*!< 0x00100000 */

+#define EXTI_D3PMR2_MR52           EXTI_D3PMR2_MR52_Msk                        /*!< Pending Mask Event for line 52  */

+#define EXTI_D3PMR2_MR53_Pos       (21U)

+#define EXTI_D3PMR2_MR53_Msk       (0x1UL << EXTI_D3PMR2_MR53_Pos)             /*!< 0x00200000 */

+#define EXTI_D3PMR2_MR53           EXTI_D3PMR2_MR53_Msk                        /*!< Pending Mask Event for line 53  */

+/*******************  Bit definition for EXTI_D3PCR2L register  ****************/

+#define EXTI_D3PCR2L_PCS34_Pos       (4U)

+#define EXTI_D3PCR2L_PCS34_Msk       (0x3UL << EXTI_D3PCR2L_PCS34_Pos)         /*!< 0x00000030 */

+#define EXTI_D3PCR2L_PCS34           EXTI_D3PCR2L_PCS34_Msk                    /*!< D3 Pending request clear input signal selection on line 34 */

+#define EXTI_D3PCR2L_PCS35_Pos       (6U)

+#define EXTI_D3PCR2L_PCS35_Msk       (0x3UL << EXTI_D3PCR2L_PCS35_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR2L_PCS35           EXTI_D3PCR2L_PCS35_Msk                    /*!< D3 Pending request clear input signal selection on line 35 */

+#define EXTI_D3PCR2L_PCS41_Pos       (18U)

+#define EXTI_D3PCR2L_PCS41_Msk       (0x3UL << EXTI_D3PCR2L_PCS41_Pos)         /*!< 0x000C0000 */

+#define EXTI_D3PCR2L_PCS41           EXTI_D3PCR2L_PCS41_Msk                    /*!< D3 Pending request clear input signal selection on line 41 */

+

+

+/*******************  Bit definition for EXTI_D3PCR2H register  ****************/

+#define EXTI_D3PCR2H_PCS48_Pos       (0U)

+#define EXTI_D3PCR2H_PCS48_Msk       (0x3UL << EXTI_D3PCR2H_PCS48_Pos)         /*!< 0x00000003 */

+#define EXTI_D3PCR2H_PCS48           EXTI_D3PCR2H_PCS48_Msk                    /*!< D3 Pending request clear input signal selection on line 48 */

+#define EXTI_D3PCR2H_PCS49_Pos       (2U)

+#define EXTI_D3PCR2H_PCS49_Msk       (0x3UL << EXTI_D3PCR2H_PCS49_Pos)         /*!< 0x0000000C */

+#define EXTI_D3PCR2H_PCS49           EXTI_D3PCR2H_PCS49_Msk                    /*!< D3 Pending request clear input signal selection on line 49 */

+#define EXTI_D3PCR2H_PCS50_Pos       (4U)

+#define EXTI_D3PCR2H_PCS50_Msk       (0x3UL << EXTI_D3PCR2H_PCS50_Pos)         /*!< 0x00000030 */

+#define EXTI_D3PCR2H_PCS50           EXTI_D3PCR2H_PCS50_Msk                    /*!< D3 Pending request clear input signal selection on line 50 */

+#define EXTI_D3PCR2H_PCS51_Pos       (6U)

+#define EXTI_D3PCR2H_PCS51_Msk       (0x3UL << EXTI_D3PCR2H_PCS51_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR2H_PCS51           EXTI_D3PCR2H_PCS51_Msk                    /*!< D3 Pending request clear input signal selection on line 51 */

+#define EXTI_D3PCR2H_PCS52_Pos       (8U)

+#define EXTI_D3PCR2H_PCS52_Msk       (0x3UL << EXTI_D3PCR2H_PCS52_Pos)         /*!< 0x00000300 */

+#define EXTI_D3PCR2H_PCS52           EXTI_D3PCR2H_PCS52_Msk                    /*!< D3 Pending request clear input signal selection on line 52 */

+#define EXTI_D3PCR2H_PCS53_Pos       (10U)

+#define EXTI_D3PCR2H_PCS53_Msk       (0x3UL << EXTI_D3PCR2H_PCS53_Pos)         /*!< 0x00000C00 */

+#define EXTI_D3PCR2H_PCS53           EXTI_D3PCR2H_PCS53_Msk                    /*!< D3 Pending request clear input signal selection on line 53 */

+/******************  Bit definition for EXTI_RTSR3 register  *******************/

+#define EXTI_RTSR3_TR_Pos          (18U)

+#define EXTI_RTSR3_TR_Msk          (0x1DUL << EXTI_RTSR3_TR_Pos)               /*!< 0x00740000 */

+#define EXTI_RTSR3_TR              EXTI_RTSR3_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR3_TR82_Pos        (18U)

+#define EXTI_RTSR3_TR82_Msk        (0x1UL << EXTI_RTSR3_TR82_Pos)              /*!< 0x00040000 */

+#define EXTI_RTSR3_TR82            EXTI_RTSR3_TR82_Msk                         /*!< Rising trigger event configuration bit of line 82 */

+#define EXTI_RTSR3_TR84_Pos        (20U)

+#define EXTI_RTSR3_TR84_Msk        (0x1UL << EXTI_RTSR3_TR84_Pos)              /*!< 0x00100000 */

+#define EXTI_RTSR3_TR84            EXTI_RTSR3_TR84_Msk                         /*!< Rising trigger event configuration bit of line 84 */

+#define EXTI_RTSR3_TR85_Pos        (21U)

+#define EXTI_RTSR3_TR85_Msk        (0x1UL << EXTI_RTSR3_TR85_Pos)              /*!< 0x00200000 */

+#define EXTI_RTSR3_TR85            EXTI_RTSR3_TR85_Msk                         /*!< Rising trigger event configuration bit of line 85 */

+#define EXTI_RTSR3_TR86_Pos        (22U)

+#define EXTI_RTSR3_TR86_Msk        (0x1UL << EXTI_RTSR3_TR86_Pos)              /*!< 0x00400000 */

+#define EXTI_RTSR3_TR86            EXTI_RTSR3_TR86_Msk                         /*!< Rising trigger event configuration bit of line 86 */

+

+/******************  Bit definition for EXTI_FTSR3 register  *******************/

+#define EXTI_FTSR3_TR_Pos          (18U)

+#define EXTI_FTSR3_TR_Msk          (0x1DUL << EXTI_FTSR3_TR_Pos)               /*!< 0x00740000 */

+#define EXTI_FTSR3_TR              EXTI_FTSR3_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR3_TR82_Pos        (18U)

+#define EXTI_FTSR3_TR82_Msk        (0x1UL << EXTI_FTSR3_TR82_Pos)              /*!< 0x00040000 */

+#define EXTI_FTSR3_TR82            EXTI_FTSR3_TR82_Msk                         /*!< Falling trigger event configuration bit of line 82 */

+#define EXTI_FTSR3_TR84_Pos        (20U)

+#define EXTI_FTSR3_TR84_Msk        (0x1UL << EXTI_FTSR3_TR84_Pos)              /*!< 0x00100000 */

+#define EXTI_FTSR3_TR84            EXTI_FTSR3_TR84_Msk                         /*!< Falling trigger event configuration bit of line 84 */

+#define EXTI_FTSR3_TR85_Pos        (21U)

+#define EXTI_FTSR3_TR85_Msk        (0x1UL << EXTI_FTSR3_TR85_Pos)              /*!< 0x00200000 */

+#define EXTI_FTSR3_TR85            EXTI_FTSR3_TR85_Msk                         /*!< Falling trigger event configuration bit of line 85 */

+#define EXTI_FTSR3_TR86_Pos        (22U)

+#define EXTI_FTSR3_TR86_Msk        (0x1UL << EXTI_FTSR3_TR86_Pos)              /*!< 0x00400000 */

+#define EXTI_FTSR3_TR86            EXTI_FTSR3_TR86_Msk                         /*!< Falling trigger event configuration bit of line 86 */

+

+/******************  Bit definition for EXTI_SWIER3 register  ******************/

+#define EXTI_SWIER3_SWI_Pos        (18U)

+#define EXTI_SWIER3_SWI_Msk        (0x1DUL << EXTI_SWIER3_SWI_Pos)             /*!< 0x00740000 */

+#define EXTI_SWIER3_SWI            EXTI_SWIER3_SWI_Msk                         /*!< Software Interrupt event bit */

+#define EXTI_SWIER3_SWIER82_Pos    (18U)

+#define EXTI_SWIER3_SWIER82_Msk    (0x1UL << EXTI_SWIER3_SWIER82_Pos)          /*!< 0x00040000 */

+#define EXTI_SWIER3_SWIER82        EXTI_SWIER3_SWIER82_Msk                     /*!< Software Interrupt on line 82 */

+#define EXTI_SWIER3_SWIER84_Pos    (20U)

+#define EXTI_SWIER3_SWIER84_Msk    (0x1UL << EXTI_SWIER3_SWIER84_Pos)          /*!< 0x00100000 */

+#define EXTI_SWIER3_SWIER84        EXTI_SWIER3_SWIER84_Msk                     /*!< Software Interrupt on line 84 */

+#define EXTI_SWIER3_SWIER85_Pos    (21U)

+#define EXTI_SWIER3_SWIER85_Msk    (0x1UL << EXTI_SWIER3_SWIER85_Pos)          /*!< 0x00200000 */

+#define EXTI_SWIER3_SWIER85        EXTI_SWIER3_SWIER85_Msk                     /*!< Software Interrupt on line 85 */

+#define EXTI_SWIER3_SWIER86_Pos    (22U)

+#define EXTI_SWIER3_SWIER86_Msk    (0x1UL << EXTI_SWIER3_SWIER86_Pos)          /*!< 0x00400000 */

+#define EXTI_SWIER3_SWIER86        EXTI_SWIER3_SWIER86_Msk                     /*!< Software Interrupt on line 86 */

+

+/*******************  Bit definition for EXTI_IMR1 register  *******************/

+#define EXTI_IMR1_IM_Pos           (0U)

+#define EXTI_IMR1_IM_Msk           (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)          /*!< 0xFFFFFFFF */

+#define EXTI_IMR1_IM               EXTI_IMR1_IM_Msk                            /*!< Interrupt Mask */

+#define EXTI_IMR1_IM0_Pos          (0U)

+#define EXTI_IMR1_IM0_Msk          (0x1UL << EXTI_IMR1_IM0_Pos)                /*!< 0x00000001 */

+#define EXTI_IMR1_IM0              EXTI_IMR1_IM0_Msk                           /*!< Interrupt Mask on line 0 */

+#define EXTI_IMR1_IM1_Pos          (1U)

+#define EXTI_IMR1_IM1_Msk          (0x1UL << EXTI_IMR1_IM1_Pos)                /*!< 0x00000002 */

+#define EXTI_IMR1_IM1              EXTI_IMR1_IM1_Msk                           /*!< Interrupt Mask on line 1 */

+#define EXTI_IMR1_IM2_Pos          (2U)

+#define EXTI_IMR1_IM2_Msk          (0x1UL << EXTI_IMR1_IM2_Pos)                /*!< 0x00000004 */

+#define EXTI_IMR1_IM2              EXTI_IMR1_IM2_Msk                           /*!< Interrupt Mask on line 2 */

+#define EXTI_IMR1_IM3_Pos          (3U)

+#define EXTI_IMR1_IM3_Msk          (0x1UL << EXTI_IMR1_IM3_Pos)                /*!< 0x00000008 */

+#define EXTI_IMR1_IM3              EXTI_IMR1_IM3_Msk                           /*!< Interrupt Mask on line 3 */

+#define EXTI_IMR1_IM4_Pos          (4U)

+#define EXTI_IMR1_IM4_Msk          (0x1UL << EXTI_IMR1_IM4_Pos)                /*!< 0x00000010 */

+#define EXTI_IMR1_IM4              EXTI_IMR1_IM4_Msk                           /*!< Interrupt Mask on line 4 */

+#define EXTI_IMR1_IM5_Pos          (5U)

+#define EXTI_IMR1_IM5_Msk          (0x1UL << EXTI_IMR1_IM5_Pos)                /*!< 0x00000020 */

+#define EXTI_IMR1_IM5              EXTI_IMR1_IM5_Msk                           /*!< Interrupt Mask on line 5 */

+#define EXTI_IMR1_IM6_Pos          (6U)

+#define EXTI_IMR1_IM6_Msk          (0x1UL << EXTI_IMR1_IM6_Pos)                /*!< 0x00000040 */

+#define EXTI_IMR1_IM6              EXTI_IMR1_IM6_Msk                           /*!< Interrupt Mask on line 6 */

+#define EXTI_IMR1_IM7_Pos          (7U)

+#define EXTI_IMR1_IM7_Msk          (0x1UL << EXTI_IMR1_IM7_Pos)                /*!< 0x00000080 */

+#define EXTI_IMR1_IM7              EXTI_IMR1_IM7_Msk                           /*!< Interrupt Mask on line 7 */

+#define EXTI_IMR1_IM8_Pos          (8U)

+#define EXTI_IMR1_IM8_Msk          (0x1UL << EXTI_IMR1_IM8_Pos)                /*!< 0x00000100 */

+#define EXTI_IMR1_IM8              EXTI_IMR1_IM8_Msk                           /*!< Interrupt Mask on line 8 */

+#define EXTI_IMR1_IM9_Pos          (9U)

+#define EXTI_IMR1_IM9_Msk          (0x1UL << EXTI_IMR1_IM9_Pos)                /*!< 0x00000200 */

+#define EXTI_IMR1_IM9              EXTI_IMR1_IM9_Msk                           /*!< Interrupt Mask on line 9 */

+#define EXTI_IMR1_IM10_Pos         (10U)

+#define EXTI_IMR1_IM10_Msk         (0x1UL << EXTI_IMR1_IM10_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR1_IM10             EXTI_IMR1_IM10_Msk                          /*!< Interrupt Mask on line 10 */

+#define EXTI_IMR1_IM11_Pos         (11U)

+#define EXTI_IMR1_IM11_Msk         (0x1UL << EXTI_IMR1_IM11_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR1_IM11             EXTI_IMR1_IM11_Msk                          /*!< Interrupt Mask on line 11 */

+#define EXTI_IMR1_IM12_Pos         (12U)

+#define EXTI_IMR1_IM12_Msk         (0x1UL << EXTI_IMR1_IM12_Pos)               /*!< 0x00001000 */

+#define EXTI_IMR1_IM12             EXTI_IMR1_IM12_Msk                          /*!< Interrupt Mask on line 12 */

+#define EXTI_IMR1_IM13_Pos         (13U)

+#define EXTI_IMR1_IM13_Msk         (0x1UL << EXTI_IMR1_IM13_Pos)               /*!< 0x00002000 */

+#define EXTI_IMR1_IM13             EXTI_IMR1_IM13_Msk                          /*!< Interrupt Mask on line 13 */

+#define EXTI_IMR1_IM14_Pos         (14U)

+#define EXTI_IMR1_IM14_Msk         (0x1UL << EXTI_IMR1_IM14_Pos)               /*!< 0x00004000 */

+#define EXTI_IMR1_IM14             EXTI_IMR1_IM14_Msk                          /*!< Interrupt Mask on line 14 */

+#define EXTI_IMR1_IM15_Pos         (15U)

+#define EXTI_IMR1_IM15_Msk         (0x1UL << EXTI_IMR1_IM15_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR1_IM15             EXTI_IMR1_IM15_Msk                          /*!< Interrupt Mask on line 15 */

+#define EXTI_IMR1_IM16_Pos         (16U)

+#define EXTI_IMR1_IM16_Msk         (0x1UL << EXTI_IMR1_IM16_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR1_IM16             EXTI_IMR1_IM16_Msk                          /*!< Interrupt Mask on line 16 */

+#define EXTI_IMR1_IM17_Pos         (17U)

+#define EXTI_IMR1_IM17_Msk         (0x1UL << EXTI_IMR1_IM17_Pos)               /*!< 0x00020000 */

+#define EXTI_IMR1_IM17             EXTI_IMR1_IM17_Msk                          /*!< Interrupt Mask on line 17 */

+#define EXTI_IMR1_IM18_Pos         (18U)

+#define EXTI_IMR1_IM18_Msk         (0x1UL << EXTI_IMR1_IM18_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR1_IM18             EXTI_IMR1_IM18_Msk                          /*!< Interrupt Mask on line 18 */

+#define EXTI_IMR1_IM19_Pos         (19U)

+#define EXTI_IMR1_IM19_Msk         (0x1UL << EXTI_IMR1_IM19_Pos)               /*!< 0x00080000 */

+#define EXTI_IMR1_IM19             EXTI_IMR1_IM19_Msk                          /*!< Interrupt Mask on line 19 */

+#define EXTI_IMR1_IM20_Pos         (20U)

+#define EXTI_IMR1_IM20_Msk         (0x1UL << EXTI_IMR1_IM20_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR1_IM20             EXTI_IMR1_IM20_Msk                          /*!< Interrupt Mask on line 20 */

+#define EXTI_IMR1_IM21_Pos         (21U)

+#define EXTI_IMR1_IM21_Msk         (0x1UL << EXTI_IMR1_IM21_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR1_IM21             EXTI_IMR1_IM21_Msk                          /*!< Interrupt Mask on line 21 */

+#define EXTI_IMR1_IM22_Pos         (22U)

+#define EXTI_IMR1_IM22_Msk         (0x1UL << EXTI_IMR1_IM22_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR1_IM22             EXTI_IMR1_IM22_Msk                          /*!< Interrupt Mask on line 22 */

+#define EXTI_IMR1_IM23_Pos         (23U)

+#define EXTI_IMR1_IM23_Msk         (0x1UL << EXTI_IMR1_IM23_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR1_IM23             EXTI_IMR1_IM23_Msk                          /*!< Interrupt Mask on line 23 */

+#define EXTI_IMR1_IM24_Pos         (24U)

+#define EXTI_IMR1_IM24_Msk         (0x1UL << EXTI_IMR1_IM24_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR1_IM24             EXTI_IMR1_IM24_Msk                          /*!< Interrupt Mask on line 24 */

+#define EXTI_IMR1_IM25_Pos         (25U)

+#define EXTI_IMR1_IM25_Msk         (0x1UL << EXTI_IMR1_IM25_Pos)               /*!< 0x02000000 */

+#define EXTI_IMR1_IM25             EXTI_IMR1_IM25_Msk                          /*!< Interrupt Mask on line 25 */

+#define EXTI_IMR1_IM26_Pos         (26U)

+#define EXTI_IMR1_IM26_Msk         (0x1UL << EXTI_IMR1_IM26_Pos)               /*!< 0x04000000 */

+#define EXTI_IMR1_IM26             EXTI_IMR1_IM26_Msk                          /*!< Interrupt Mask on line 26 */

+#define EXTI_IMR1_IM27_Pos         (27U)

+#define EXTI_IMR1_IM27_Msk         (0x1UL << EXTI_IMR1_IM27_Pos)               /*!< 0x08000000 */

+#define EXTI_IMR1_IM27             EXTI_IMR1_IM27_Msk                          /*!< Interrupt Mask on line 27 */

+#define EXTI_IMR1_IM28_Pos         (28U)

+#define EXTI_IMR1_IM28_Msk         (0x1UL << EXTI_IMR1_IM28_Pos)               /*!< 0x10000000 */

+#define EXTI_IMR1_IM28             EXTI_IMR1_IM28_Msk                          /*!< Interrupt Mask on line 28 */

+#define EXTI_IMR1_IM29_Pos         (29U)

+#define EXTI_IMR1_IM29_Msk         (0x1UL << EXTI_IMR1_IM29_Pos)               /*!< 0x20000000 */

+#define EXTI_IMR1_IM29             EXTI_IMR1_IM29_Msk                          /*!< Interrupt Mask on line 29 */

+#define EXTI_IMR1_IM30_Pos         (30U)

+#define EXTI_IMR1_IM30_Msk         (0x1UL << EXTI_IMR1_IM30_Pos)               /*!< 0x40000000 */

+#define EXTI_IMR1_IM30             EXTI_IMR1_IM30_Msk                          /*!< Interrupt Mask on line 30 */

+#define EXTI_IMR1_IM31_Pos         (31U)

+#define EXTI_IMR1_IM31_Msk         (0x1UL << EXTI_IMR1_IM31_Pos)               /*!< 0x80000000 */

+#define EXTI_IMR1_IM31             EXTI_IMR1_IM31_Msk                          /*!< Interrupt Mask on line 31 */

+

+/*******************  Bit definition for EXTI_EMR1 register  *******************/

+#define EXTI_EMR1_EM_Pos           (0U)

+#define EXTI_EMR1_EM_Msk           (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)          /*!< 0xFFFFFFFF */

+#define EXTI_EMR1_EM               EXTI_EMR1_EM_Msk                            /*!< Event Mask */

+#define EXTI_EMR1_EM0_Pos          (0U)

+#define EXTI_EMR1_EM0_Msk          (0x1UL << EXTI_EMR1_EM0_Pos)                /*!< 0x00000001 */

+#define EXTI_EMR1_EM0              EXTI_EMR1_EM0_Msk                           /*!< Event Mask on line 0 */

+#define EXTI_EMR1_EM1_Pos          (1U)

+#define EXTI_EMR1_EM1_Msk          (0x1UL << EXTI_EMR1_EM1_Pos)                /*!< 0x00000002 */

+#define EXTI_EMR1_EM1              EXTI_EMR1_EM1_Msk                           /*!< Event Mask on line 1 */

+#define EXTI_EMR1_EM2_Pos          (2U)

+#define EXTI_EMR1_EM2_Msk          (0x1UL << EXTI_EMR1_EM2_Pos)                /*!< 0x00000004 */

+#define EXTI_EMR1_EM2              EXTI_EMR1_EM2_Msk                           /*!< Event Mask on line 2 */

+#define EXTI_EMR1_EM3_Pos          (3U)

+#define EXTI_EMR1_EM3_Msk          (0x1UL << EXTI_EMR1_EM3_Pos)                /*!< 0x00000008 */

+#define EXTI_EMR1_EM3              EXTI_EMR1_EM3_Msk                           /*!< Event Mask on line 3 */

+#define EXTI_EMR1_EM4_Pos          (4U)

+#define EXTI_EMR1_EM4_Msk          (0x1UL << EXTI_EMR1_EM4_Pos)                /*!< 0x00000010 */

+#define EXTI_EMR1_EM4              EXTI_EMR1_EM4_Msk                           /*!< Event Mask on line 4 */

+#define EXTI_EMR1_EM5_Pos          (5U)

+#define EXTI_EMR1_EM5_Msk          (0x1UL << EXTI_EMR1_EM5_Pos)                /*!< 0x00000020 */

+#define EXTI_EMR1_EM5              EXTI_EMR1_EM5_Msk                           /*!< Event Mask on line 5 */

+#define EXTI_EMR1_EM6_Pos          (6U)

+#define EXTI_EMR1_EM6_Msk          (0x1UL << EXTI_EMR1_EM6_Pos)                /*!< 0x00000040 */

+#define EXTI_EMR1_EM6              EXTI_EMR1_EM6_Msk                           /*!< Event Mask on line 6 */

+#define EXTI_EMR1_EM7_Pos          (7U)

+#define EXTI_EMR1_EM7_Msk          (0x1UL << EXTI_EMR1_EM7_Pos)                /*!< 0x00000080 */

+#define EXTI_EMR1_EM7              EXTI_EMR1_EM7_Msk                           /*!< Event Mask on line 7 */

+#define EXTI_EMR1_EM8_Pos          (8U)

+#define EXTI_EMR1_EM8_Msk          (0x1UL << EXTI_EMR1_EM8_Pos)                /*!< 0x00000100 */

+#define EXTI_EMR1_EM8              EXTI_EMR1_EM8_Msk                           /*!< Event Mask on line 8 */

+#define EXTI_EMR1_EM9_Pos          (9U)

+#define EXTI_EMR1_EM9_Msk          (0x1UL << EXTI_EMR1_EM9_Pos)                /*!< 0x00000200 */

+#define EXTI_EMR1_EM9              EXTI_EMR1_EM9_Msk                           /*!< Event Mask on line 9 */

+#define EXTI_EMR1_EM10_Pos         (10U)

+#define EXTI_EMR1_EM10_Msk         (0x1UL << EXTI_EMR1_EM10_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR1_EM10             EXTI_EMR1_EM10_Msk                          /*!< Event Mask on line 10 */

+#define EXTI_EMR1_EM11_Pos         (11U)

+#define EXTI_EMR1_EM11_Msk         (0x1UL << EXTI_EMR1_EM11_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR1_EM11             EXTI_EMR1_EM11_Msk                          /*!< Event Mask on line 11 */

+#define EXTI_EMR1_EM12_Pos         (12U)

+#define EXTI_EMR1_EM12_Msk         (0x1UL << EXTI_EMR1_EM12_Pos)               /*!< 0x00001000 */

+#define EXTI_EMR1_EM12             EXTI_EMR1_EM12_Msk                          /*!< Event Mask on line 12 */

+#define EXTI_EMR1_EM13_Pos         (13U)

+#define EXTI_EMR1_EM13_Msk         (0x1UL << EXTI_EMR1_EM13_Pos)               /*!< 0x00002000 */

+#define EXTI_EMR1_EM13             EXTI_EMR1_EM13_Msk                          /*!< Event Mask on line 13 */

+#define EXTI_EMR1_EM14_Pos         (14U)

+#define EXTI_EMR1_EM14_Msk         (0x1UL << EXTI_EMR1_EM14_Pos)               /*!< 0x00004000 */

+#define EXTI_EMR1_EM14             EXTI_EMR1_EM14_Msk                          /*!< Event Mask on line 14 */

+#define EXTI_EMR1_EM15_Pos         (15U)

+#define EXTI_EMR1_EM15_Msk         (0x1UL << EXTI_EMR1_EM15_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR1_EM15             EXTI_EMR1_EM15_Msk                          /*!< Event Mask on line 15 */

+#define EXTI_EMR1_EM16_Pos         (16U)

+#define EXTI_EMR1_EM16_Msk         (0x1UL << EXTI_EMR1_EM16_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR1_EM16             EXTI_EMR1_EM16_Msk                          /*!< Event Mask on line 16 */

+#define EXTI_EMR1_EM17_Pos         (17U)

+#define EXTI_EMR1_EM17_Msk         (0x1UL << EXTI_EMR1_EM17_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR1_EM17             EXTI_EMR1_EM17_Msk                          /*!< Event Mask on line 17 */

+#define EXTI_EMR1_EM18_Pos         (18U)

+#define EXTI_EMR1_EM18_Msk         (0x1UL << EXTI_EMR1_EM18_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR1_EM18             EXTI_EMR1_EM18_Msk                          /*!< Event Mask on line 18 */

+#define EXTI_EMR1_EM20_Pos         (20U)

+#define EXTI_EMR1_EM20_Msk         (0x1UL << EXTI_EMR1_EM20_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR1_EM20             EXTI_EMR1_EM20_Msk                          /*!< Event Mask on line 20 */

+#define EXTI_EMR1_EM21_Pos         (21U)

+#define EXTI_EMR1_EM21_Msk         (0x1UL << EXTI_EMR1_EM21_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR1_EM21             EXTI_EMR1_EM21_Msk                          /*!< Event Mask on line 21 */

+#define EXTI_EMR1_EM22_Pos         (22U)

+#define EXTI_EMR1_EM22_Msk         (0x1UL << EXTI_EMR1_EM22_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR1_EM22             EXTI_EMR1_EM22_Msk                          /*!< Event Mask on line 22 */

+#define EXTI_EMR1_EM23_Pos         (23U)

+#define EXTI_EMR1_EM23_Msk         (0x1UL << EXTI_EMR1_EM23_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR1_EM23             EXTI_EMR1_EM23_Msk                          /*!< Event Mask on line 23 */

+#define EXTI_EMR1_EM24_Pos         (24U)

+#define EXTI_EMR1_EM24_Msk         (0x1UL << EXTI_EMR1_EM24_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR1_EM24             EXTI_EMR1_EM24_Msk                          /*!< Event Mask on line 24 */

+#define EXTI_EMR1_EM25_Pos         (25U)

+#define EXTI_EMR1_EM25_Msk         (0x1UL << EXTI_EMR1_EM25_Pos)               /*!< 0x02000000 */

+#define EXTI_EMR1_EM25             EXTI_EMR1_EM25_Msk                          /*!< Event Mask on line 25 */

+#define EXTI_EMR1_EM26_Pos         (26U)

+#define EXTI_EMR1_EM26_Msk         (0x1UL << EXTI_EMR1_EM26_Pos)               /*!< 0x04000000 */

+#define EXTI_EMR1_EM26             EXTI_EMR1_EM26_Msk                          /*!< Event Mask on line 26 */

+#define EXTI_EMR1_EM27_Pos         (27U)

+#define EXTI_EMR1_EM27_Msk         (0x1UL << EXTI_EMR1_EM27_Pos)               /*!< 0x08000000 */

+#define EXTI_EMR1_EM27             EXTI_EMR1_EM27_Msk                          /*!< Event Mask on line 27 */

+#define EXTI_EMR1_EM28_Pos         (28U)

+#define EXTI_EMR1_EM28_Msk         (0x1UL << EXTI_EMR1_EM28_Pos)               /*!< 0x10000000 */

+#define EXTI_EMR1_EM28             EXTI_EMR1_EM28_Msk                          /*!< Event Mask on line 28 */

+#define EXTI_EMR1_EM29_Pos         (29U)

+#define EXTI_EMR1_EM29_Msk         (0x1UL << EXTI_EMR1_EM29_Pos)               /*!< 0x20000000 */

+#define EXTI_EMR1_EM29             EXTI_EMR1_EM29_Msk                          /*!< Event Mask on line 29 */

+#define EXTI_EMR1_EM30_Pos         (30U)

+#define EXTI_EMR1_EM30_Msk         (0x1UL << EXTI_EMR1_EM30_Pos)               /*!< 0x40000000 */

+#define EXTI_EMR1_EM30             EXTI_EMR1_EM30_Msk                          /*!< Event Mask on line 30 */

+#define EXTI_EMR1_EM31_Pos         (31U)

+#define EXTI_EMR1_EM31_Msk         (0x1UL << EXTI_EMR1_EM31_Pos)               /*!< 0x80000000 */

+#define EXTI_EMR1_EM31             EXTI_EMR1_EM31_Msk                          /*!< Event Mask on line 31 */

+

+/*******************  Bit definition for EXTI_PR1 register  ********************/

+#define EXTI_PR1_PR_Pos            (0U)

+#define EXTI_PR1_PR_Msk            (0x3FFFFFUL << EXTI_PR1_PR_Pos)             /*!< 0x003FFFFF */

+#define EXTI_PR1_PR                EXTI_PR1_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR1_PR0_Pos           (0U)

+#define EXTI_PR1_PR0_Msk           (0x1UL << EXTI_PR1_PR0_Pos)                 /*!< 0x00000001 */

+#define EXTI_PR1_PR0               EXTI_PR1_PR0_Msk                            /*!< Pending bit for line 0 */

+#define EXTI_PR1_PR1_Pos           (1U)

+#define EXTI_PR1_PR1_Msk           (0x1UL << EXTI_PR1_PR1_Pos)                 /*!< 0x00000002 */

+#define EXTI_PR1_PR1               EXTI_PR1_PR1_Msk                            /*!< Pending bit for line 1 */

+#define EXTI_PR1_PR2_Pos           (2U)

+#define EXTI_PR1_PR2_Msk           (0x1UL << EXTI_PR1_PR2_Pos)                 /*!< 0x00000004 */

+#define EXTI_PR1_PR2               EXTI_PR1_PR2_Msk                            /*!< Pending bit for line 2 */

+#define EXTI_PR1_PR3_Pos           (3U)

+#define EXTI_PR1_PR3_Msk           (0x1UL << EXTI_PR1_PR3_Pos)                 /*!< 0x00000008 */

+#define EXTI_PR1_PR3               EXTI_PR1_PR3_Msk                            /*!< Pending bit for line 3 */

+#define EXTI_PR1_PR4_Pos           (4U)

+#define EXTI_PR1_PR4_Msk           (0x1UL << EXTI_PR1_PR4_Pos)                 /*!< 0x00000010 */

+#define EXTI_PR1_PR4               EXTI_PR1_PR4_Msk                            /*!< Pending bit for line 4 */

+#define EXTI_PR1_PR5_Pos           (5U)

+#define EXTI_PR1_PR5_Msk           (0x1UL << EXTI_PR1_PR5_Pos)                 /*!< 0x00000020 */

+#define EXTI_PR1_PR5               EXTI_PR1_PR5_Msk                            /*!< Pending bit for line 5 */

+#define EXTI_PR1_PR6_Pos           (6U)

+#define EXTI_PR1_PR6_Msk           (0x1UL << EXTI_PR1_PR6_Pos)                 /*!< 0x00000040 */

+#define EXTI_PR1_PR6               EXTI_PR1_PR6_Msk                            /*!< Pending bit for line 6 */

+#define EXTI_PR1_PR7_Pos           (7U)

+#define EXTI_PR1_PR7_Msk           (0x1UL << EXTI_PR1_PR7_Pos)                 /*!< 0x00000080 */

+#define EXTI_PR1_PR7               EXTI_PR1_PR7_Msk                            /*!< Pending bit for line 7 */

+#define EXTI_PR1_PR8_Pos           (8U)

+#define EXTI_PR1_PR8_Msk           (0x1UL << EXTI_PR1_PR8_Pos)                 /*!< 0x00000100 */

+#define EXTI_PR1_PR8               EXTI_PR1_PR8_Msk                            /*!< Pending bit for line 8 */

+#define EXTI_PR1_PR9_Pos           (9U)

+#define EXTI_PR1_PR9_Msk           (0x1UL << EXTI_PR1_PR9_Pos)                 /*!< 0x00000200 */

+#define EXTI_PR1_PR9               EXTI_PR1_PR9_Msk                            /*!< Pending bit for line 9 */

+#define EXTI_PR1_PR10_Pos          (10U)

+#define EXTI_PR1_PR10_Msk          (0x1UL << EXTI_PR1_PR10_Pos)                /*!< 0x00000400 */

+#define EXTI_PR1_PR10              EXTI_PR1_PR10_Msk                           /*!< Pending bit for line 10 */

+#define EXTI_PR1_PR11_Pos          (11U)

+#define EXTI_PR1_PR11_Msk          (0x1UL << EXTI_PR1_PR11_Pos)                /*!< 0x00000800 */

+#define EXTI_PR1_PR11              EXTI_PR1_PR11_Msk                           /*!< Pending bit for line 11 */

+#define EXTI_PR1_PR12_Pos          (12U)

+#define EXTI_PR1_PR12_Msk          (0x1UL << EXTI_PR1_PR12_Pos)                /*!< 0x00001000 */

+#define EXTI_PR1_PR12              EXTI_PR1_PR12_Msk                           /*!< Pending bit for line 12 */

+#define EXTI_PR1_PR13_Pos          (13U)

+#define EXTI_PR1_PR13_Msk          (0x1UL << EXTI_PR1_PR13_Pos)                /*!< 0x00002000 */

+#define EXTI_PR1_PR13              EXTI_PR1_PR13_Msk                           /*!< Pending bit for line 13 */

+#define EXTI_PR1_PR14_Pos          (14U)

+#define EXTI_PR1_PR14_Msk          (0x1UL << EXTI_PR1_PR14_Pos)                /*!< 0x00004000 */

+#define EXTI_PR1_PR14              EXTI_PR1_PR14_Msk                           /*!< Pending bit for line 14 */

+#define EXTI_PR1_PR15_Pos          (15U)

+#define EXTI_PR1_PR15_Msk          (0x1UL << EXTI_PR1_PR15_Pos)                /*!< 0x00008000 */

+#define EXTI_PR1_PR15              EXTI_PR1_PR15_Msk                           /*!< Pending bit for line 15 */

+#define EXTI_PR1_PR16_Pos          (16U)

+#define EXTI_PR1_PR16_Msk          (0x1UL << EXTI_PR1_PR16_Pos)                /*!< 0x00010000 */

+#define EXTI_PR1_PR16              EXTI_PR1_PR16_Msk                           /*!< Pending bit for line 16 */

+#define EXTI_PR1_PR17_Pos          (17U)

+#define EXTI_PR1_PR17_Msk          (0x1UL << EXTI_PR1_PR17_Pos)                /*!< 0x00020000 */

+#define EXTI_PR1_PR17              EXTI_PR1_PR17_Msk                           /*!< Pending bit for line 17 */

+#define EXTI_PR1_PR18_Pos          (18U)

+#define EXTI_PR1_PR18_Msk          (0x1UL << EXTI_PR1_PR18_Pos)                /*!< 0x00040000 */

+#define EXTI_PR1_PR18              EXTI_PR1_PR18_Msk                           /*!< Pending bit for line 18 */

+#define EXTI_PR1_PR19_Pos          (19U)

+#define EXTI_PR1_PR19_Msk          (0x1UL << EXTI_PR1_PR19_Pos)                /*!< 0x00080000 */

+#define EXTI_PR1_PR19              EXTI_PR1_PR19_Msk                           /*!< Pending bit for line 19 */

+#define EXTI_PR1_PR20_Pos          (20U)

+#define EXTI_PR1_PR20_Msk          (0x1UL << EXTI_PR1_PR20_Pos)                /*!< 0x00100000 */

+#define EXTI_PR1_PR20              EXTI_PR1_PR20_Msk                           /*!< Pending bit for line 20 */

+#define EXTI_PR1_PR21_Pos          (21U)

+#define EXTI_PR1_PR21_Msk          (0x1UL << EXTI_PR1_PR21_Pos)                /*!< 0x00200000 */

+#define EXTI_PR1_PR21              EXTI_PR1_PR21_Msk                           /*!< Pending bit for line 21 */

+

+/*******************  Bit definition for EXTI_IMR2 register  *******************/

+#define EXTI_IMR2_IM_Pos           (0U)

+#define EXTI_IMR2_IM_Msk           (0xFFFFDFFFUL << EXTI_IMR2_IM_Pos)          /*!< 0xFFFFDFFF */

+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            /*!< Interrupt Mask */

+#define EXTI_IMR2_IM32_Pos         (0U)

+#define EXTI_IMR2_IM32_Msk         (0x1UL << EXTI_IMR2_IM32_Pos)               /*!< 0x00000001 */

+#define EXTI_IMR2_IM32             EXTI_IMR2_IM32_Msk                          /*!< Interrupt Mask on line 32 */

+#define EXTI_IMR2_IM33_Pos         (1U)

+#define EXTI_IMR2_IM33_Msk         (0x1UL << EXTI_IMR2_IM33_Pos)               /*!< 0x00000002 */

+#define EXTI_IMR2_IM33             EXTI_IMR2_IM33_Msk                          /*!< Interrupt Mask on line 33 */

+#define EXTI_IMR2_IM34_Pos         (2U)

+#define EXTI_IMR2_IM34_Msk         (0x1UL << EXTI_IMR2_IM34_Pos)               /*!< 0x00000004 */

+#define EXTI_IMR2_IM34             EXTI_IMR2_IM34_Msk                          /*!< Interrupt Mask on line 34 */

+#define EXTI_IMR2_IM35_Pos         (3U)

+#define EXTI_IMR2_IM35_Msk         (0x1UL << EXTI_IMR2_IM35_Pos)               /*!< 0x00000008 */

+#define EXTI_IMR2_IM35             EXTI_IMR2_IM35_Msk                          /*!< Interrupt Mask on line 35 */

+#define EXTI_IMR2_IM36_Pos         (4U)

+#define EXTI_IMR2_IM36_Msk         (0x1UL << EXTI_IMR2_IM36_Pos)               /*!< 0x00000010 */

+#define EXTI_IMR2_IM36             EXTI_IMR2_IM36_Msk                          /*!< Interrupt Mask on line 36 */

+#define EXTI_IMR2_IM37_Pos         (5U)

+#define EXTI_IMR2_IM37_Msk         (0x1UL << EXTI_IMR2_IM37_Pos)               /*!< 0x00000020 */

+#define EXTI_IMR2_IM37             EXTI_IMR2_IM37_Msk                          /*!< Interrupt Mask on line 37 */

+#define EXTI_IMR2_IM38_Pos         (6U)

+#define EXTI_IMR2_IM38_Msk         (0x1UL << EXTI_IMR2_IM38_Pos)               /*!< 0x00000040 */

+#define EXTI_IMR2_IM38             EXTI_IMR2_IM38_Msk                          /*!< Interrupt Mask on line 38 */

+#define EXTI_IMR2_IM39_Pos         (7U)

+#define EXTI_IMR2_IM39_Msk         (0x1UL << EXTI_IMR2_IM39_Pos)               /*!< 0x00000080 */

+#define EXTI_IMR2_IM39             EXTI_IMR2_IM39_Msk                          /*!< Interrupt Mask on line 39 */

+#define EXTI_IMR2_IM40_Pos         (8U)

+#define EXTI_IMR2_IM40_Msk         (0x1UL << EXTI_IMR2_IM40_Pos)               /*!< 0x00000100 */

+#define EXTI_IMR2_IM40             EXTI_IMR2_IM40_Msk                          /*!< Interrupt Mask on line 40 */

+#define EXTI_IMR2_IM41_Pos         (9U)

+#define EXTI_IMR2_IM41_Msk         (0x1UL << EXTI_IMR2_IM41_Pos)               /*!< 0x00000200 */

+#define EXTI_IMR2_IM41             EXTI_IMR2_IM41_Msk                          /*!< Interrupt Mask on line 41 */

+#define EXTI_IMR2_IM42_Pos         (10U)

+#define EXTI_IMR2_IM42_Msk         (0x1UL << EXTI_IMR2_IM42_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR2_IM42             EXTI_IMR2_IM42_Msk                          /*!< Interrupt Mask on line 42 */

+#define EXTI_IMR2_IM43_Pos         (11U)

+#define EXTI_IMR2_IM43_Msk         (0x1UL << EXTI_IMR2_IM43_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR2_IM43             EXTI_IMR2_IM43_Msk                          /*!< Interrupt Mask on line 43 */

+#define EXTI_IMR2_IM44_Pos         (12U)

+#define EXTI_IMR2_IM44_Msk         (0x1UL << EXTI_IMR2_IM44_Pos)               /*!< 0x00001000 */

+#define EXTI_IMR2_IM44             EXTI_IMR2_IM44_Msk                          /*!< Interrupt Mask on line 44 */

+#define EXTI_IMR2_IM46_Pos         (14U)

+#define EXTI_IMR2_IM46_Msk         (0x1UL << EXTI_IMR2_IM46_Pos)               /*!< 0x00004000 */

+#define EXTI_IMR2_IM46             EXTI_IMR2_IM46_Msk                          /*!< Interrupt Mask on line 46 */

+#define EXTI_IMR2_IM47_Pos         (15U)

+#define EXTI_IMR2_IM47_Msk         (0x1UL << EXTI_IMR2_IM47_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR2_IM47             EXTI_IMR2_IM47_Msk                          /*!< Interrupt Mask on line 47 */

+#define EXTI_IMR2_IM48_Pos         (16U)

+#define EXTI_IMR2_IM48_Msk         (0x1UL << EXTI_IMR2_IM48_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR2_IM48             EXTI_IMR2_IM48_Msk                          /*!< Interrupt Mask on line 48 */

+#define EXTI_IMR2_IM49_Pos         (17U)

+#define EXTI_IMR2_IM49_Msk         (0x1UL << EXTI_IMR2_IM49_Pos)               /*!< 0x00020000 */

+#define EXTI_IMR2_IM49             EXTI_IMR2_IM49_Msk                          /*!< Interrupt Mask on line 49 */

+#define EXTI_IMR2_IM50_Pos         (18U)

+#define EXTI_IMR2_IM50_Msk         (0x1UL << EXTI_IMR2_IM50_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR2_IM50             EXTI_IMR2_IM50_Msk                          /*!< Interrupt Mask on line 50 */

+#define EXTI_IMR2_IM51_Pos         (19U)

+#define EXTI_IMR2_IM51_Msk         (0x1UL << EXTI_IMR2_IM51_Pos)               /*!< 0x00080000 */

+#define EXTI_IMR2_IM51             EXTI_IMR2_IM51_Msk                          /*!< Interrupt Mask on line 51 */

+#define EXTI_IMR2_IM52_Pos         (20U)

+#define EXTI_IMR2_IM52_Msk         (0x1UL << EXTI_IMR2_IM52_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR2_IM52             EXTI_IMR2_IM52_Msk                          /*!< Interrupt Mask on line 52 */

+#define EXTI_IMR2_IM53_Pos         (21U)

+#define EXTI_IMR2_IM53_Msk         (0x1UL << EXTI_IMR2_IM53_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR2_IM53             EXTI_IMR2_IM53_Msk                          /*!< Interrupt Mask on line 53 */

+#define EXTI_IMR2_IM54_Pos         (22U)

+#define EXTI_IMR2_IM54_Msk         (0x1UL << EXTI_IMR2_IM54_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR2_IM54             EXTI_IMR2_IM54_Msk                          /*!< Interrupt Mask on line 54 */

+#define EXTI_IMR2_IM55_Pos         (23U)

+#define EXTI_IMR2_IM55_Msk         (0x1UL << EXTI_IMR2_IM55_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR2_IM55             EXTI_IMR2_IM55_Msk                          /*!< Interrupt Mask on line 55 */

+#define EXTI_IMR2_IM56_Pos         (24U)

+#define EXTI_IMR2_IM56_Msk         (0x1UL << EXTI_IMR2_IM56_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR2_IM56             EXTI_IMR2_IM56_Msk                          /*!< Interrupt Mask on line 56 */

+#define EXTI_IMR2_IM57_Pos         (25U)

+#define EXTI_IMR2_IM57_Msk         (0x1UL << EXTI_IMR2_IM57_Pos)               /*!< 0x02000000 */

+#define EXTI_IMR2_IM57             EXTI_IMR2_IM57_Msk                          /*!< Interrupt Mask on line 57 */

+#define EXTI_IMR2_IM58_Pos         (26U)

+#define EXTI_IMR2_IM58_Msk         (0x1UL << EXTI_IMR2_IM58_Pos)               /*!< 0x04000000 */

+#define EXTI_IMR2_IM58             EXTI_IMR2_IM58_Msk                          /*!< Interrupt Mask on line 58 */

+#define EXTI_IMR2_IM59_Pos         (27U)

+#define EXTI_IMR2_IM59_Msk         (0x1UL << EXTI_IMR2_IM59_Pos)               /*!< 0x08000000 */

+#define EXTI_IMR2_IM59             EXTI_IMR2_IM59_Msk                          /*!< Interrupt Mask on line 59 */

+#define EXTI_IMR2_IM60_Pos         (28U)

+#define EXTI_IMR2_IM60_Msk         (0x1UL << EXTI_IMR2_IM60_Pos)               /*!< 0x10000000 */

+#define EXTI_IMR2_IM60             EXTI_IMR2_IM60_Msk                          /*!< Interrupt Mask on line 60 */

+#define EXTI_IMR2_IM61_Pos         (29U)

+#define EXTI_IMR2_IM61_Msk         (0x1UL << EXTI_IMR2_IM61_Pos)               /*!< 0x20000000 */

+#define EXTI_IMR2_IM61             EXTI_IMR2_IM61_Msk                          /*!< Interrupt Mask on line 61 */

+#define EXTI_IMR2_IM62_Pos         (30U)

+#define EXTI_IMR2_IM62_Msk         (0x1UL << EXTI_IMR2_IM62_Pos)               /*!< 0x40000000 */

+#define EXTI_IMR2_IM62             EXTI_IMR2_IM62_Msk                          /*!< Interrupt Mask on line 62 */

+#define EXTI_IMR2_IM63_Pos         (31U)

+#define EXTI_IMR2_IM63_Msk         (0x1UL << EXTI_IMR2_IM63_Pos)               /*!< 0x80000000 */

+#define EXTI_IMR2_IM63             EXTI_IMR2_IM63_Msk                          /*!< Interrupt Mask on line 63 */

+

+/*******************  Bit definition for EXTI_EMR2 register  *******************/

+#define EXTI_EMR2_EM_Pos           (0U)

+#define EXTI_EMR2_EM_Msk           (0xFFFFDFFFUL << EXTI_EMR2_EM_Pos)          /*!< 0xFFFFDFFF */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            /*!< Event Mask */

+#define EXTI_EMR2_EM32_Pos         (0U)

+#define EXTI_EMR2_EM32_Msk         (0x1UL << EXTI_EMR2_EM32_Pos)               /*!< 0x00000001 */

+#define EXTI_EMR2_EM32             EXTI_EMR2_EM32_Msk                          /*!< Event Mask on line 32*/

+#define EXTI_EMR2_EM33_Pos         (1U)

+#define EXTI_EMR2_EM33_Msk         (0x1UL << EXTI_EMR2_EM33_Pos)               /*!< 0x00000002 */

+#define EXTI_EMR2_EM33             EXTI_EMR2_EM33_Msk                          /*!< Event Mask on line 33*/

+#define EXTI_EMR2_EM34_Pos         (2U)

+#define EXTI_EMR2_EM34_Msk         (0x1UL << EXTI_EMR2_EM34_Pos)               /*!< 0x00000004 */

+#define EXTI_EMR2_EM34             EXTI_EMR2_EM34_Msk                          /*!< Event Mask on line 34*/

+#define EXTI_EMR2_EM35_Pos         (3U)

+#define EXTI_EMR2_EM35_Msk         (0x1UL << EXTI_EMR2_EM35_Pos)               /*!< 0x00000008 */

+#define EXTI_EMR2_EM35             EXTI_EMR2_EM35_Msk                          /*!< Event Mask on line 35*/

+#define EXTI_EMR2_EM36_Pos         (4U)

+#define EXTI_EMR2_EM36_Msk         (0x1UL << EXTI_EMR2_EM36_Pos)               /*!< 0x00000010 */

+#define EXTI_EMR2_EM36             EXTI_EMR2_EM36_Msk                          /*!< Event Mask on line 36*/

+#define EXTI_EMR2_EM37_Pos         (5U)

+#define EXTI_EMR2_EM37_Msk         (0x1UL << EXTI_EMR2_EM37_Pos)               /*!< 0x00000020 */

+#define EXTI_EMR2_EM37             EXTI_EMR2_EM37_Msk                          /*!< Event Mask on line 37*/

+#define EXTI_EMR2_EM38_Pos         (6U)

+#define EXTI_EMR2_EM38_Msk         (0x1UL << EXTI_EMR2_EM38_Pos)               /*!< 0x00000040 */

+#define EXTI_EMR2_EM38             EXTI_EMR2_EM38_Msk                          /*!< Event Mask on line 38*/

+#define EXTI_EMR2_EM39_Pos         (7U)

+#define EXTI_EMR2_EM39_Msk         (0x1UL << EXTI_EMR2_EM39_Pos)               /*!< 0x00000080 */

+#define EXTI_EMR2_EM39             EXTI_EMR2_EM39_Msk                          /*!< Event Mask on line 39*/

+#define EXTI_EMR2_EM40_Pos         (8U)

+#define EXTI_EMR2_EM40_Msk         (0x1UL << EXTI_EMR2_EM40_Pos)               /*!< 0x00000100 */

+#define EXTI_EMR2_EM40             EXTI_EMR2_EM40_Msk                          /*!< Event Mask on line 40*/

+#define EXTI_EMR2_EM41_Pos         (9U)

+#define EXTI_EMR2_EM41_Msk         (0x1UL << EXTI_EMR2_EM41_Pos)               /*!< 0x00000200 */

+#define EXTI_EMR2_EM41             EXTI_EMR2_EM41_Msk                          /*!< Event Mask on line 41*/

+#define EXTI_EMR2_EM42_Pos         (10U)

+#define EXTI_EMR2_EM42_Msk         (0x1UL << EXTI_EMR2_EM42_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR2_EM42             EXTI_EMR2_EM42_Msk                          /*!< Event Mask on line 42 */

+#define EXTI_EMR2_EM43_Pos         (11U)

+#define EXTI_EMR2_EM43_Msk         (0x1UL << EXTI_EMR2_EM43_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR2_EM43             EXTI_EMR2_EM43_Msk                          /*!< Event Mask on line 43 */

+#define EXTI_EMR2_EM44_Pos         (12U)

+#define EXTI_EMR2_EM44_Msk         (0x1UL << EXTI_EMR2_EM44_Pos)               /*!< 0x00001000 */

+#define EXTI_EMR2_EM44             EXTI_EMR2_EM44_Msk                          /*!< Event Mask on line 44 */

+#define EXTI_EMR2_EM46_Pos         (14U)

+#define EXTI_EMR2_EM46_Msk         (0x1UL << EXTI_EMR2_EM46_Pos)               /*!< 0x00004000 */

+#define EXTI_EMR2_EM46             EXTI_EMR2_EM46_Msk                          /*!< Event Mask on line 46 */

+#define EXTI_EMR2_EM47_Pos         (15U)

+#define EXTI_EMR2_EM47_Msk         (0x1UL << EXTI_EMR2_EM47_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR2_EM47             EXTI_EMR2_EM47_Msk                          /*!< Event Mask on line 47 */

+#define EXTI_EMR2_EM48_Pos         (16U)

+#define EXTI_EMR2_EM48_Msk         (0x1UL << EXTI_EMR2_EM48_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR2_EM48             EXTI_EMR2_EM48_Msk                          /*!< Event Mask on line 48 */

+#define EXTI_EMR2_EM49_Pos         (17U)

+#define EXTI_EMR2_EM49_Msk         (0x1UL << EXTI_EMR2_EM49_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR2_EM49             EXTI_EMR2_EM49_Msk                          /*!< Event Mask on line 49 */

+#define EXTI_EMR2_EM50_Pos         (18U)

+#define EXTI_EMR2_EM50_Msk         (0x1UL << EXTI_EMR2_EM50_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR2_EM50             EXTI_EMR2_EM50_Msk                          /*!< Event Mask on line 50 */

+#define EXTI_EMR2_EM51_Pos         (19U)

+#define EXTI_EMR2_EM51_Msk         (0x1UL << EXTI_EMR2_EM51_Pos)               /*!< 0x00080000 */

+#define EXTI_EMR2_EM51             EXTI_EMR2_EM51_Msk                          /*!< Event Mask on line 51 */

+#define EXTI_EMR2_EM52_Pos         (20U)

+#define EXTI_EMR2_EM52_Msk         (0x1UL << EXTI_EMR2_EM52_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR2_EM52             EXTI_EMR2_EM52_Msk                          /*!< Event Mask on line 52 */

+#define EXTI_EMR2_EM53_Pos         (21U)

+#define EXTI_EMR2_EM53_Msk         (0x1UL << EXTI_EMR2_EM53_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR2_EM53             EXTI_EMR2_EM53_Msk                          /*!< Event Mask on line 53 */

+#define EXTI_EMR2_EM54_Pos         (22U)

+#define EXTI_EMR2_EM54_Msk         (0x1UL << EXTI_EMR2_EM54_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR2_EM54             EXTI_EMR2_EM54_Msk                          /*!< Event Mask on line 54 */

+#define EXTI_EMR2_EM55_Pos         (23U)

+#define EXTI_EMR2_EM55_Msk         (0x1UL << EXTI_EMR2_EM55_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR2_EM55             EXTI_EMR2_EM55_Msk                          /*!< Event Mask on line 55 */

+#define EXTI_EMR2_EM56_Pos         (24U)

+#define EXTI_EMR2_EM56_Msk         (0x1UL << EXTI_EMR2_EM56_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR2_EM56             EXTI_EMR2_EM56_Msk                          /*!< Event Mask on line 56 */

+#define EXTI_EMR2_EM57_Pos         (25U)

+#define EXTI_EMR2_EM57_Msk         (0x1UL << EXTI_EMR2_EM57_Pos)               /*!< 0x02000000 */

+#define EXTI_EMR2_EM57             EXTI_EMR2_EM57_Msk                          /*!< Event Mask on line 57 */

+#define EXTI_EMR2_EM58_Pos         (26U)

+#define EXTI_EMR2_EM58_Msk         (0x1UL << EXTI_EMR2_EM58_Pos)               /*!< 0x04000000 */

+#define EXTI_EMR2_EM58             EXTI_EMR2_EM58_Msk                          /*!< Event Mask on line 58 */

+#define EXTI_EMR2_EM59_Pos         (27U)

+#define EXTI_EMR2_EM59_Msk         (0x1UL << EXTI_EMR2_EM59_Pos)               /*!< 0x08000000 */

+#define EXTI_EMR2_EM59             EXTI_EMR2_EM59_Msk                          /*!< Event Mask on line 59 */

+#define EXTI_EMR2_EM60_Pos         (28U)

+#define EXTI_EMR2_EM60_Msk         (0x1UL << EXTI_EMR2_EM60_Pos)               /*!< 0x10000000 */

+#define EXTI_EMR2_EM60             EXTI_EMR2_EM60_Msk                          /*!< Event Mask on line 60 */

+#define EXTI_EMR2_EM61_Pos         (29U)

+#define EXTI_EMR2_EM61_Msk         (0x1UL << EXTI_EMR2_EM61_Pos)               /*!< 0x20000000 */

+#define EXTI_EMR2_EM61             EXTI_EMR2_EM61_Msk                          /*!< Event Mask on line 61 */

+#define EXTI_EMR2_EM62_Pos         (30U)

+#define EXTI_EMR2_EM62_Msk         (0x1UL << EXTI_EMR2_EM62_Pos)               /*!< 0x40000000 */

+#define EXTI_EMR2_EM62             EXTI_EMR2_EM62_Msk                          /*!< Event Mask on line 62 */

+#define EXTI_EMR2_EM63_Pos         (31U)

+#define EXTI_EMR2_EM63_Msk         (0x1UL << EXTI_EMR2_EM63_Pos)               /*!< 0x80000000 */

+#define EXTI_EMR2_EM63             EXTI_EMR2_EM63_Msk                          /*!< Event Mask on line 63 */

+

+/*******************  Bit definition for EXTI_PR2 register  ********************/

+#define EXTI_PR2_PR_Pos            (17U)

+#define EXTI_PR2_PR_Msk            (0x5UL << EXTI_PR2_PR_Pos)                  /*!< 0x000A0000 */

+#define EXTI_PR2_PR                EXTI_PR2_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR2_PR49_Pos          (17U)

+#define EXTI_PR2_PR49_Msk          (0x1UL << EXTI_PR2_PR49_Pos)                /*!< 0x00020000 */

+#define EXTI_PR2_PR49              EXTI_PR2_PR49_Msk                           /*!< Pending bit for line 49 */

+#define EXTI_PR2_PR51_Pos          (19U)

+#define EXTI_PR2_PR51_Msk          (0x1UL << EXTI_PR2_PR51_Pos)                /*!< 0x00080000 */

+#define EXTI_PR2_PR51              EXTI_PR2_PR51_Msk                           /*!< Pending bit for line 51 */

+

+/*******************  Bit definition for EXTI_IMR3 register  *******************/

+#define EXTI_IMR3_IM_Pos           (0U)

+#define EXTI_IMR3_IM_Msk           (0x00F5FFFFUL << EXTI_IMR3_IM_Pos)          /*!< 0x00F5FFFF */

+#define EXTI_IMR3_IM               EXTI_IMR3_IM_Msk                            /*!< Interrupt Mask */

+#define EXTI_IMR3_IM64_Pos         (0U)

+#define EXTI_IMR3_IM64_Msk         (0x1UL << EXTI_IMR3_IM64_Pos)               /*!< 0x00000001 */

+#define EXTI_IMR3_IM64             EXTI_IMR3_IM64_Msk                          /*!< Interrupt Mask on line 64 */

+#define EXTI_IMR3_IM65_Pos         (1U)

+#define EXTI_IMR3_IM65_Msk         (0x1UL << EXTI_IMR3_IM65_Pos)               /*!< 0x00000002 */

+#define EXTI_IMR3_IM65             EXTI_IMR3_IM65_Msk                          /*!< Interrupt Mask on line 65 */

+#define EXTI_IMR3_IM66_Pos         (2U)

+#define EXTI_IMR3_IM66_Msk         (0x1UL << EXTI_IMR3_IM66_Pos)               /*!< 0x00000004 */

+#define EXTI_IMR3_IM66             EXTI_IMR3_IM66_Msk                          /*!< Interrupt Mask on line 66 */

+#define EXTI_IMR3_IM67_Pos         (3U)

+#define EXTI_IMR3_IM67_Msk         (0x1UL << EXTI_IMR3_IM67_Pos)               /*!< 0x00000008 */

+#define EXTI_IMR3_IM67             EXTI_IMR3_IM67_Msk                          /*!< Interrupt Mask on line 67 */

+#define EXTI_IMR3_IM68_Pos         (4U)

+#define EXTI_IMR3_IM68_Msk         (0x1UL << EXTI_IMR3_IM68_Pos)               /*!< 0x00000010 */

+#define EXTI_IMR3_IM68             EXTI_IMR3_IM68_Msk                          /*!< Interrupt Mask on line 68 */

+#define EXTI_IMR3_IM69_Pos         (5U)

+#define EXTI_IMR3_IM69_Msk         (0x1UL << EXTI_IMR3_IM69_Pos)               /*!< 0x00000020 */

+#define EXTI_IMR3_IM69             EXTI_IMR3_IM69_Msk                          /*!< Interrupt Mask on line 69 */

+#define EXTI_IMR3_IM70_Pos         (6U)

+#define EXTI_IMR3_IM70_Msk         (0x1UL << EXTI_IMR3_IM70_Pos)               /*!< 0x00000040 */

+#define EXTI_IMR3_IM70             EXTI_IMR3_IM70_Msk                          /*!< Interrupt Mask on line 70 */

+#define EXTI_IMR3_IM71_Pos         (7U)

+#define EXTI_IMR3_IM71_Msk         (0x1UL << EXTI_IMR3_IM71_Pos)               /*!< 0x00000080 */

+#define EXTI_IMR3_IM71             EXTI_IMR3_IM71_Msk                          /*!< Interrupt Mask on line 71 */

+#define EXTI_IMR3_IM72_Pos         (8U)

+#define EXTI_IMR3_IM72_Msk         (0x1UL << EXTI_IMR3_IM72_Pos)               /*!< 0x00000100 */

+#define EXTI_IMR3_IM72             EXTI_IMR3_IM72_Msk                          /*!< Interrupt Mask on line 72 */

+#define EXTI_IMR3_IM73_Pos         (9U)

+#define EXTI_IMR3_IM73_Msk         (0x1UL << EXTI_IMR3_IM73_Pos)               /*!< 0x00000200 */

+#define EXTI_IMR3_IM73             EXTI_IMR3_IM73_Msk                          /*!< Interrupt Mask on line 73 */

+#define EXTI_IMR3_IM74_Pos         (10U)

+#define EXTI_IMR3_IM74_Msk         (0x1UL << EXTI_IMR3_IM74_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR3_IM74             EXTI_IMR3_IM74_Msk                          /*!< Interrupt Mask on line 74 */

+#define EXTI_IMR3_IM75_Pos         (11U)

+#define EXTI_IMR3_IM75_Msk         (0x1UL << EXTI_IMR3_IM75_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR3_IM75             EXTI_IMR3_IM75_Msk                          /*!< Interrupt Mask on line 75 */

+#define EXTI_IMR3_IM76_Pos         (12U)

+#define EXTI_IMR3_IM76_Msk         (0x1UL << EXTI_IMR3_IM76_Pos)               /*!< 0x00001000 */

+#define EXTI_IMR3_IM76             EXTI_IMR3_IM76_Msk                          /*!< Interrupt Mask on line 76 */

+#define EXTI_IMR3_IM77_Pos         (13U)

+#define EXTI_IMR3_IM77_Msk         (0x1UL << EXTI_IMR3_IM77_Pos)               /*!< 0x00002000 */

+#define EXTI_IMR3_IM77             EXTI_IMR3_IM77_Msk                          /*!< Interrupt Mask on line 77 */

+#define EXTI_IMR3_IM78_Pos         (14U)

+#define EXTI_IMR3_IM78_Msk         (0x1UL << EXTI_IMR3_IM78_Pos)               /*!< 0x00004000 */

+#define EXTI_IMR3_IM78             EXTI_IMR3_IM78_Msk                          /*!< Interrupt Mask on line 78 */

+#define EXTI_IMR3_IM79_Pos         (15U)

+#define EXTI_IMR3_IM79_Msk         (0x1UL << EXTI_IMR3_IM79_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR3_IM79             EXTI_IMR3_IM79_Msk                          /*!< Interrupt Mask on line 79 */

+#define EXTI_IMR3_IM80_Pos         (16U)

+#define EXTI_IMR3_IM80_Msk         (0x1UL << EXTI_IMR3_IM80_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR3_IM80             EXTI_IMR3_IM80_Msk                          /*!< Interrupt Mask on line 80 */

+#define EXTI_IMR3_IM82_Pos         (18U)

+#define EXTI_IMR3_IM82_Msk         (0x1UL << EXTI_IMR3_IM82_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR3_IM82             EXTI_IMR3_IM82_Msk                          /*!< Interrupt Mask on line 82 */

+#define EXTI_IMR3_IM84_Pos         (20U)

+#define EXTI_IMR3_IM84_Msk         (0x1UL << EXTI_IMR3_IM84_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR3_IM84             EXTI_IMR3_IM84_Msk                          /*!< Interrupt Mask on line 84 */

+#define EXTI_IMR3_IM85_Pos         (21U)

+#define EXTI_IMR3_IM85_Msk         (0x1UL << EXTI_IMR3_IM85_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR3_IM85             EXTI_IMR3_IM85_Msk                          /*!< Interrupt Mask on line 85 */

+#define EXTI_IMR3_IM86_Pos         (22U)

+#define EXTI_IMR3_IM86_Msk         (0x1UL << EXTI_IMR3_IM86_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR3_IM86             EXTI_IMR3_IM86_Msk                          /*!< Interrupt Mask on line 86 */

+#define EXTI_IMR3_IM87_Pos         (23U)

+#define EXTI_IMR3_IM87_Msk         (0x1UL << EXTI_IMR3_IM87_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR3_IM87             EXTI_IMR3_IM87_Msk                          /*!< Interrupt Mask on line 87 */

+

+

+/*******************  Bit definition for EXTI_EMR3 register  *******************/

+#define EXTI_EMR3_EM_Pos           (0U)

+#define EXTI_EMR3_EM_Msk           (0x00F5FFFFUL << EXTI_EMR3_EM_Pos)          /*!< 0x00F5FFFF */

+#define EXTI_EMR3_EM               EXTI_EMR3_EM_Msk                            /*!< Event Mask           */

+#define EXTI_EMR3_EM64_Pos         (0U)

+#define EXTI_EMR3_EM64_Msk         (0x1UL << EXTI_EMR3_EM64_Pos)               /*!< 0x00000001 */

+#define EXTI_EMR3_EM64             EXTI_EMR3_EM64_Msk                          /*!< Event Mask on line 64*/

+#define EXTI_EMR3_EM65_Pos         (1U)

+#define EXTI_EMR3_EM65_Msk         (0x1UL << EXTI_EMR3_EM65_Pos)               /*!< 0x00000002 */

+#define EXTI_EMR3_EM65             EXTI_EMR3_EM65_Msk                          /*!< Event Mask on line 65*/

+#define EXTI_EMR3_EM66_Pos         (2U)

+#define EXTI_EMR3_EM66_Msk         (0x1UL << EXTI_EMR3_EM66_Pos)               /*!< 0x00000004 */

+#define EXTI_EMR3_EM66             EXTI_EMR3_EM66_Msk                          /*!< Event Mask on line 66*/

+#define EXTI_EMR3_EM67_Pos         (3U)

+#define EXTI_EMR3_EM67_Msk         (0x1UL << EXTI_EMR3_EM67_Pos)               /*!< 0x00000008 */

+#define EXTI_EMR3_EM67             EXTI_EMR3_EM67_Msk                          /*!< Event Mask on line 67*/

+#define EXTI_EMR3_EM68_Pos         (4U)

+#define EXTI_EMR3_EM68_Msk         (0x1UL << EXTI_EMR3_EM68_Pos)               /*!< 0x00000010 */

+#define EXTI_EMR3_EM68             EXTI_EMR3_EM68_Msk                          /*!< Event Mask on line 68*/

+#define EXTI_EMR3_EM69_Pos         (5U)

+#define EXTI_EMR3_EM69_Msk         (0x1UL << EXTI_EMR3_EM69_Pos)               /*!< 0x00000020 */

+#define EXTI_EMR3_EM69             EXTI_EMR3_EM69_Msk                          /*!< Event Mask on line 69*/

+#define EXTI_EMR3_EM70_Pos         (6U)

+#define EXTI_EMR3_EM70_Msk         (0x1UL << EXTI_EMR3_EM70_Pos)               /*!< 0x00000040 */

+#define EXTI_EMR3_EM70             EXTI_EMR3_EM70_Msk                          /*!< Event Mask on line 70*/

+#define EXTI_EMR3_EM71_Pos         (7U)

+#define EXTI_EMR3_EM71_Msk         (0x1UL << EXTI_EMR3_EM71_Pos)               /*!< 0x00000080 */

+#define EXTI_EMR3_EM71             EXTI_EMR3_EM71_Msk                          /*!< Event Mask on line 71*/

+#define EXTI_EMR3_EM72_Pos         (8U)

+#define EXTI_EMR3_EM72_Msk         (0x1UL << EXTI_EMR3_EM72_Pos)               /*!< 0x00000100 */

+#define EXTI_EMR3_EM72             EXTI_EMR3_EM72_Msk                          /*!< Event Mask on line 72*/

+#define EXTI_EMR3_EM73_Pos         (9U)

+#define EXTI_EMR3_EM73_Msk         (0x1UL << EXTI_EMR3_EM73_Pos)               /*!< 0x00000200 */

+#define EXTI_EMR3_EM73             EXTI_EMR3_EM73_Msk                          /*!< Event Mask on line 73*/

+#define EXTI_EMR3_EM74_Pos         (10U)

+#define EXTI_EMR3_EM74_Msk         (0x1UL << EXTI_EMR3_EM74_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR3_EM74             EXTI_EMR3_EM74_Msk                          /*!< Event Mask on line 74 */

+#define EXTI_EMR3_EM75_Pos         (11U)

+#define EXTI_EMR3_EM75_Msk         (0x1UL << EXTI_EMR3_EM75_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR3_EM75             EXTI_EMR3_EM75_Msk                          /*!< Event Mask on line 75 */

+#define EXTI_EMR3_EM76_Pos         (12U)

+#define EXTI_EMR3_EM76_Msk         (0x1UL << EXTI_EMR3_EM76_Pos)               /*!< 0x00001000 */

+#define EXTI_EMR3_EM76             EXTI_EMR3_EM76_Msk                          /*!< Event Mask on line 76 */

+#define EXTI_EMR3_EM77_Pos         (13U)

+#define EXTI_EMR3_EM77_Msk         (0x1UL << EXTI_EMR3_EM77_Pos)               /*!< 0x00002000 */

+#define EXTI_EMR3_EM77             EXTI_EMR3_EM77_Msk                          /*!< Event Mask on line 77 */

+#define EXTI_EMR3_EM78_Pos         (14U)

+#define EXTI_EMR3_EM78_Msk         (0x1UL << EXTI_EMR3_EM78_Pos)               /*!< 0x00004000 */

+#define EXTI_EMR3_EM78             EXTI_EMR3_EM78_Msk                          /*!< Event Mask on line 78 */

+#define EXTI_EMR3_EM79_Pos         (15U)

+#define EXTI_EMR3_EM79_Msk         (0x1UL << EXTI_EMR3_EM79_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR3_EM79             EXTI_EMR3_EM79_Msk                          /*!< Event Mask on line 79 */

+#define EXTI_EMR3_EM80_Pos         (16U)

+#define EXTI_EMR3_EM80_Msk         (0x1UL << EXTI_EMR3_EM80_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR3_EM80             EXTI_EMR3_EM80_Msk                          /*!< Event Mask on line 80 */

+#define EXTI_EMR3_EM81_Pos         (17U)

+#define EXTI_EMR3_EM81_Msk         (0x1UL << EXTI_EMR3_EM81_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR3_EM81             EXTI_EMR3_EM81_Msk                          /*!< Event Mask on line 81 */

+#define EXTI_EMR3_EM82_Pos         (18U)

+#define EXTI_EMR3_EM82_Msk         (0x1UL << EXTI_EMR3_EM82_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR3_EM82             EXTI_EMR3_EM82_Msk                          /*!< Event Mask on line 82 */

+#define EXTI_EMR3_EM84_Pos         (20U)

+#define EXTI_EMR3_EM84_Msk         (0x1UL << EXTI_EMR3_EM84_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR3_EM84             EXTI_EMR3_EM84_Msk                          /*!< Event Mask on line 84 */

+#define EXTI_EMR3_EM85_Pos         (21U)

+#define EXTI_EMR3_EM85_Msk         (0x1UL << EXTI_EMR3_EM85_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR3_EM85             EXTI_EMR3_EM85_Msk                          /*!< Event Mask on line 85 */

+#define EXTI_EMR3_EM86_Pos         (22U)

+#define EXTI_EMR3_EM86_Msk         (0x1UL << EXTI_EMR3_EM86_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR3_EM86             EXTI_EMR3_EM86_Msk                          /*!< Event Mask on line 86 */

+#define EXTI_EMR3_EM87_Pos         (23U)

+#define EXTI_EMR3_EM87_Msk         (0x1UL << EXTI_EMR3_EM87_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR3_EM87             EXTI_EMR3_EM87_Msk                          /*!< Event Mask on line 87 */

+

+/*******************  Bit definition for EXTI_PR3 register  ********************/

+#define EXTI_PR3_PR_Pos            (18U)

+#define EXTI_PR3_PR_Msk            (0x1DUL << EXTI_PR3_PR_Pos)                 /*!< 0x00740000 */

+#define EXTI_PR3_PR                EXTI_PR3_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR3_PR82_Pos          (18U)

+#define EXTI_PR3_PR82_Msk          (0x1UL << EXTI_PR3_PR82_Pos)                /*!< 0x00040000 */

+#define EXTI_PR3_PR82              EXTI_PR3_PR82_Msk                           /*!< Pending bit for line 82 */

+#define EXTI_PR3_PR84_Pos          (20U)

+#define EXTI_PR3_PR84_Msk          (0x1UL << EXTI_PR3_PR84_Pos)                /*!< 0x00100000 */

+#define EXTI_PR3_PR84              EXTI_PR3_PR84_Msk                           /*!< Pending bit for line 84 */

+#define EXTI_PR3_PR85_Pos          (21U)

+#define EXTI_PR3_PR85_Msk          (0x1UL << EXTI_PR3_PR85_Pos)                /*!< 0x00200000 */

+#define EXTI_PR3_PR85              EXTI_PR3_PR85_Msk                           /*!< Pending bit for line 85 */

+#define EXTI_PR3_PR86_Pos          (22U)

+#define EXTI_PR3_PR86_Msk          (0x1UL << EXTI_PR3_PR86_Pos)                /*!< 0x00400000 */

+#define EXTI_PR3_PR86              EXTI_PR3_PR86_Msk                           /*!< Pending bit for line 86 */

+/******************************************************************************/

+/*                                                                            */

+/*                                    FLASH                                   */

+/*                                                                            */

+/******************************************************************************/

+/*

+* @brief FLASH Global Defines

+*/

+#define FLASH_SECTOR_TOTAL                   1U                    /* 1 sector */

+#define FLASH_SECTOR_SIZE                    0x00020000UL          /* 128 KB */

+#define FLASH_SIZE                           FLASH_SECTOR_SIZE     /* 128 KB */

+#define FLASH_BANK_SIZE                      FLASH_SIZE            /* 128 KB */

+#define FLASH_LATENCY_DEFAULT                FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */

+#define FLASH_NB_32BITWORD_IN_FLASHWORD      8U                    /* 256 bits */

+

+/*******************  Bits definition for FLASH_ACR register  **********************/

+#define FLASH_ACR_LATENCY_Pos                (0U)

+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */

+#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */

+#define FLASH_ACR_LATENCY_0WS                (0x00000000UL)

+#define FLASH_ACR_LATENCY_1WS                (0x00000001UL)

+#define FLASH_ACR_LATENCY_2WS                (0x00000002UL)

+#define FLASH_ACR_LATENCY_3WS                (0x00000003UL)

+#define FLASH_ACR_LATENCY_4WS                (0x00000004UL)

+#define FLASH_ACR_LATENCY_5WS                (0x00000005UL)

+#define FLASH_ACR_LATENCY_6WS                (0x00000006UL)

+#define FLASH_ACR_LATENCY_7WS                (0x00000007UL)

+#define FLASH_ACR_LATENCY_8WS                (0x00000008UL)

+#define FLASH_ACR_LATENCY_9WS                (0x00000009UL)

+#define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)

+#define FLASH_ACR_LATENCY_11WS               (0x0000000BUL)

+#define FLASH_ACR_LATENCY_12WS               (0x0000000CUL)

+#define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)

+#define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)

+#define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)

+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)

+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */

+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */

+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */

+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */

+

+/*******************  Bits definition for FLASH_CR register  ***********************/

+#define FLASH_CR_LOCK_Pos                    (0U)

+#define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */

+#define FLASH_CR_LOCK                        FLASH_CR_LOCK_Msk                 /*!< Configuration lock bit */

+#define FLASH_CR_PG_Pos                      (1U)

+#define FLASH_CR_PG_Msk                      (0x1UL << FLASH_CR_PG_Pos)        /*!< 0x00000002 */

+#define FLASH_CR_PG                          FLASH_CR_PG_Msk                   /*!< Internal buffer control bit */

+#define FLASH_CR_SER_Pos                     (2U)

+#define FLASH_CR_SER_Msk                     (0x1UL << FLASH_CR_SER_Pos)       /*!< 0x00000004 */

+#define FLASH_CR_SER                         FLASH_CR_SER_Msk                  /*!< Sector erase request */

+#define FLASH_CR_BER_Pos                     (3U)

+#define FLASH_CR_BER_Msk                     (0x1UL << FLASH_CR_BER_Pos)       /*!< 0x00000008 */

+#define FLASH_CR_BER                         FLASH_CR_BER_Msk                  /*!< Bank erase request */

+#define FLASH_CR_PSIZE_Pos                   (4U)

+#define FLASH_CR_PSIZE_Msk                   (0x3UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000030 */

+#define FLASH_CR_PSIZE                       FLASH_CR_PSIZE_Msk                /*!< Program size */

+#define FLASH_CR_PSIZE_0                     (0x1UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000010 */

+#define FLASH_CR_PSIZE_1                     (0x2UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000020 */

+#define FLASH_CR_FW_Pos                      (6U)

+#define FLASH_CR_FW_Msk                      (0x1UL << FLASH_CR_FW_Pos)        /*!< 0x00000040 */

+#define FLASH_CR_FW                          FLASH_CR_FW_Msk                   /*!< Write forcing control bit */

+#define FLASH_CR_START_Pos                   (7U)

+#define FLASH_CR_START_Msk                   (0x1UL << FLASH_CR_START_Pos)     /*!< 0x00000080 */

+#define FLASH_CR_START                       FLASH_CR_START_Msk                /*!< Erase start control bit */

+#define FLASH_CR_SNB_Pos                     (8U)

+#define FLASH_CR_SNB_Msk                     (0x7UL << FLASH_CR_SNB_Pos)       /*!< 0x00000700 */

+#define FLASH_CR_SNB                         FLASH_CR_SNB_Msk                  /*!< Sector erase selection number */

+#define FLASH_CR_SNB_0                       (0x1UL << FLASH_CR_SNB_Pos)       /*!< 0x00000100 */

+#define FLASH_CR_SNB_1                       (0x2UL << FLASH_CR_SNB_Pos)       /*!< 0x00000200 */

+#define FLASH_CR_SNB_2                       (0x4UL << FLASH_CR_SNB_Pos)       /*!< 0x00000400 */

+#define FLASH_CR_CRC_EN_Pos                  (15U)

+#define FLASH_CR_CRC_EN_Msk                  (0x1UL << FLASH_CR_CRC_EN_Pos)    /*!< 0x00008000 */

+#define FLASH_CR_CRC_EN                      FLASH_CR_CRC_EN_Msk               /*!< CRC control bit */

+#define FLASH_CR_EOPIE_Pos                   (16U)

+#define FLASH_CR_EOPIE_Msk                   (0x1UL << FLASH_CR_EOPIE_Pos)     /*!< 0x00010000 */

+#define FLASH_CR_EOPIE                       FLASH_CR_EOPIE_Msk                /*!< End-of-program interrupt control bit */

+#define FLASH_CR_WRPERRIE_Pos                (17U)

+#define FLASH_CR_WRPERRIE_Msk                (0x1UL << FLASH_CR_WRPERRIE_Pos)  /*!< 0x00020000 */

+#define FLASH_CR_WRPERRIE                    FLASH_CR_WRPERRIE_Msk             /*!< Write protection error interrupt enable bit */

+#define FLASH_CR_PGSERRIE_Pos                (18U)

+#define FLASH_CR_PGSERRIE_Msk                (0x1UL << FLASH_CR_PGSERRIE_Pos)  /*!< 0x00040000 */

+#define FLASH_CR_PGSERRIE                    FLASH_CR_PGSERRIE_Msk             /*!< Programming sequence error interrupt enable bit */

+#define FLASH_CR_STRBERRIE_Pos               (19U)

+#define FLASH_CR_STRBERRIE_Msk               (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */

+#define FLASH_CR_STRBERRIE                   FLASH_CR_STRBERRIE_Msk            /*!< Strobe error interrupt enable bit */

+#define FLASH_CR_INCERRIE_Pos                (21U)

+#define FLASH_CR_INCERRIE_Msk                (0x1UL << FLASH_CR_INCERRIE_Pos)  /*!< 0x00200000 */

+#define FLASH_CR_INCERRIE                    FLASH_CR_INCERRIE_Msk             /*!< Inconsistency error interrupt enable bit */

+#define FLASH_CR_OPERRIE_Pos                 (22U)

+#define FLASH_CR_OPERRIE_Msk                 (0x1UL << FLASH_CR_OPERRIE_Pos)   /*!< 0x00400000 */

+#define FLASH_CR_OPERRIE                     FLASH_CR_OPERRIE_Msk              /*!< Write/erase error interrupt enable bit */

+#define FLASH_CR_RDPERRIE_Pos                (23U)

+#define FLASH_CR_RDPERRIE_Msk                (0x1UL << FLASH_CR_RDPERRIE_Pos)  /*!< 0x00800000 */

+#define FLASH_CR_RDPERRIE                    FLASH_CR_RDPERRIE_Msk             /*!< Read protection error interrupt enable bit */

+#define FLASH_CR_RDSERRIE_Pos                (24U)

+#define FLASH_CR_RDSERRIE_Msk                (0x1UL << FLASH_CR_RDSERRIE_Pos)  /*!< 0x01000000 */

+#define FLASH_CR_RDSERRIE                    FLASH_CR_RDSERRIE_Msk             /*!< Secure error interrupt enable bit */

+#define FLASH_CR_SNECCERRIE_Pos              (25U)

+#define FLASH_CR_SNECCERRIE_Msk              (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */

+#define FLASH_CR_SNECCERRIE                  FLASH_CR_SNECCERRIE_Msk            /*!< ECC single correction error interrupt enable bit */

+#define FLASH_CR_DBECCERRIE_Pos              (26U)

+#define FLASH_CR_DBECCERRIE_Msk              (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */

+#define FLASH_CR_DBECCERRIE                  FLASH_CR_DBECCERRIE_Msk            /*!< ECC double detection error interrupt enable bit */

+#define FLASH_CR_CRCENDIE_Pos                (27U)

+#define FLASH_CR_CRCENDIE_Msk                (0x1UL << FLASH_CR_CRCENDIE_Pos)  /*!< 0x08000000 */

+#define FLASH_CR_CRCENDIE                    FLASH_CR_CRCENDIE_Msk             /*!< CRC end of calculation interrupt enable bit */

+#define FLASH_CR_CRCRDERRIE_Pos              (28U)

+#define FLASH_CR_CRCRDERRIE_Msk              (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */

+#define FLASH_CR_CRCRDERRIE                  FLASH_CR_CRCRDERRIE_Msk            /*!< CRC read error interrupt enable bit */

+

+/*******************  Bits definition for FLASH_SR register  ***********************/

+#define FLASH_SR_BSY_Pos                     (0U)

+#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)       /*!< 0x00000001 */

+#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy flag */

+#define FLASH_SR_WBNE_Pos                    (1U)

+#define FLASH_SR_WBNE_Msk                    (0x1UL << FLASH_SR_WBNE_Pos)      /*!< 0x00000002 */

+#define FLASH_SR_WBNE                        FLASH_SR_WBNE_Msk                 /*!< Write buffer not empty flag */

+#define FLASH_SR_QW_Pos                      (2U)

+#define FLASH_SR_QW_Msk                      (0x1UL << FLASH_SR_QW_Pos)        /*!< 0x00000004 */

+#define FLASH_SR_QW                          FLASH_SR_QW_Msk                   /*!< Wait queue flag */

+#define FLASH_SR_CRC_BUSY_Pos                (3U)

+#define FLASH_SR_CRC_BUSY_Msk                (0x1UL << FLASH_SR_CRC_BUSY_Pos)  /*!< 0x00000008 */

+#define FLASH_SR_CRC_BUSY                    FLASH_SR_CRC_BUSY_Msk             /*!< CRC busy flag */

+#define FLASH_SR_EOP_Pos                     (16U)

+#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)       /*!< 0x00010000 */

+#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End-of-program flag */

+#define FLASH_SR_WRPERR_Pos                  (17U)

+#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)    /*!< 0x00020000 */

+#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protection error flag */

+#define FLASH_SR_PGSERR_Pos                  (18U)

+#define FLASH_SR_PGSERR_Msk                  (0x1UL << FLASH_SR_PGSERR_Pos)    /*!< 0x00040000 */

+#define FLASH_SR_PGSERR                      FLASH_SR_PGSERR_Msk               /*!< Programming sequence error flag */

+#define FLASH_SR_STRBERR_Pos                 (19U)

+#define FLASH_SR_STRBERR_Msk                 (0x1UL << FLASH_SR_STRBERR_Pos)   /*!< 0x00080000 */

+#define FLASH_SR_STRBERR                     FLASH_SR_STRBERR_Msk              /*!< Strobe error flag */

+#define FLASH_SR_INCERR_Pos                  (21U)

+#define FLASH_SR_INCERR_Msk                  (0x1UL << FLASH_SR_INCERR_Pos)    /*!< 0x00200000 */

+#define FLASH_SR_INCERR                      FLASH_SR_INCERR_Msk               /*!< Inconsistency error flag */

+#define FLASH_SR_OPERR_Pos                   (22U)

+#define FLASH_SR_OPERR_Msk                   (0x1UL << FLASH_SR_OPERR_Pos)     /*!< 0x00400000 */

+#define FLASH_SR_OPERR                       FLASH_SR_OPERR_Msk                /*!< Write/erase error flag */

+#define FLASH_SR_RDPERR_Pos                  (23U)

+#define FLASH_SR_RDPERR_Msk                  (0x1UL << FLASH_SR_RDPERR_Pos)    /*!< 0x00800000 */

+#define FLASH_SR_RDPERR                      FLASH_SR_RDPERR_Msk               /*!< Read protection error flag */

+#define FLASH_SR_RDSERR_Pos                  (24U)

+#define FLASH_SR_RDSERR_Msk                  (0x1UL << FLASH_SR_RDSERR_Pos)    /*!< 0x01000000 */

+#define FLASH_SR_RDSERR                      FLASH_SR_RDSERR_Msk               /*!< Secure error flag */

+#define FLASH_SR_SNECCERR_Pos                (25U)

+#define FLASH_SR_SNECCERR_Msk                (0x1UL << FLASH_SR_SNECCERR_Pos)  /*!< 0x02000000 */

+#define FLASH_SR_SNECCERR                    FLASH_SR_SNECCERR_Msk             /*!< Single correction error flag */

+#define FLASH_SR_DBECCERR_Pos                (26U)

+#define FLASH_SR_DBECCERR_Msk                (0x1UL << FLASH_SR_DBECCERR_Pos)  /*!< 0x04000000 */

+#define FLASH_SR_DBECCERR                    FLASH_SR_DBECCERR_Msk             /*!< ECC double detection error flag */

+#define FLASH_SR_CRCEND_Pos                  (27U)

+#define FLASH_SR_CRCEND_Msk                  (0x1UL << FLASH_SR_CRCEND_Pos)    /*!< 0x08000000 */

+#define FLASH_SR_CRCEND                      FLASH_SR_CRCEND_Msk               /*!< CRC end of calculation flag */

+#define FLASH_SR_CRCRDERR_Pos                (28U)

+#define FLASH_SR_CRCRDERR_Msk                (0x1UL << FLASH_SR_CRCRDERR_Pos)  /*!< 0x10000000 */

+#define FLASH_SR_CRCRDERR                    FLASH_SR_CRCRDERR_Msk             /*!< CRC read error flag */

+

+/*******************  Bits definition for FLASH_CCR register  *******************/

+#define FLASH_CCR_CLR_EOP_Pos                (16U)

+#define FLASH_CCR_CLR_EOP_Msk                (0x1UL << FLASH_CCR_CLR_EOP_Pos)  /*!< 0x00010000 */

+#define FLASH_CCR_CLR_EOP                    FLASH_CCR_CLR_EOP_Msk             /*!< EOP flag clear bit */

+#define FLASH_CCR_CLR_WRPERR_Pos             (17U)

+#define FLASH_CCR_CLR_WRPERR_Msk             (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */

+#define FLASH_CCR_CLR_WRPERR                 FLASH_CCR_CLR_WRPERR_Msk            /*!< WRPERR flag clear bit */

+#define FLASH_CCR_CLR_PGSERR_Pos             (18U)

+#define FLASH_CCR_CLR_PGSERR_Msk             (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */

+#define FLASH_CCR_CLR_PGSERR                 FLASH_CCR_CLR_PGSERR_Msk            /*!< PGSERR flag clear bit */

+#define FLASH_CCR_CLR_STRBERR_Pos            (19U)

+#define FLASH_CCR_CLR_STRBERR_Msk            (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */

+#define FLASH_CCR_CLR_STRBERR                FLASH_CCR_CLR_STRBERR_Msk            /*!< STRBERR flag clear bit */

+#define FLASH_CCR_CLR_INCERR_Pos             (21U)

+#define FLASH_CCR_CLR_INCERR_Msk             (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */

+#define FLASH_CCR_CLR_INCERR                 FLASH_CCR_CLR_INCERR_Msk            /*!< INCERR flag clear bit */

+#define FLASH_CCR_CLR_OPERR_Pos              (22U)

+#define FLASH_CCR_CLR_OPERR_Msk              (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */

+#define FLASH_CCR_CLR_OPERR                  FLASH_CCR_CLR_OPERR_Msk            /*!< OPERR flag clear bit */

+#define FLASH_CCR_CLR_RDPERR_Pos             (23U)

+#define FLASH_CCR_CLR_RDPERR_Msk             (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */

+#define FLASH_CCR_CLR_RDPERR                 FLASH_CCR_CLR_RDPERR_Msk            /*!< RDPERR flag clear bit */

+#define FLASH_CCR_CLR_RDSERR_Pos             (24U)

+#define FLASH_CCR_CLR_RDSERR_Msk             (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */

+#define FLASH_CCR_CLR_RDSERR                 FLASH_CCR_CLR_RDSERR_Msk            /*!< RDSERR flag clear bit */

+#define FLASH_CCR_CLR_SNECCERR_Pos           (25U)

+#define FLASH_CCR_CLR_SNECCERR_Msk           (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */

+#define FLASH_CCR_CLR_SNECCERR               FLASH_CCR_CLR_SNECCERR_Msk            /*!< SNECCERR flag clear bit */

+#define FLASH_CCR_CLR_DBECCERR_Pos           (26U)

+#define FLASH_CCR_CLR_DBECCERR_Msk           (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */

+#define FLASH_CCR_CLR_DBECCERR               FLASH_CCR_CLR_DBECCERR_Msk            /*!< DBECCERR flag clear bit */

+#define FLASH_CCR_CLR_CRCEND_Pos             (27U)

+#define FLASH_CCR_CLR_CRCEND_Msk             (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */

+#define FLASH_CCR_CLR_CRCEND                 FLASH_CCR_CLR_CRCEND_Msk            /*!< CRCEND flag clear bit */

+#define FLASH_CCR_CLR_CRCRDERR_Pos           (28U)

+#define FLASH_CCR_CLR_CRCRDERR_Msk           (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */

+#define FLASH_CCR_CLR_CRCRDERR               FLASH_CCR_CLR_CRCRDERR_Msk            /*!< CRCRDERR flag clear bit */

+

+/*******************  Bits definition for FLASH_OPTCR register  *******************/

+#define FLASH_OPTCR_OPTLOCK_Pos              (0U)

+#define FLASH_OPTCR_OPTLOCK_Msk              (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)  /*!< 0x00000001 */

+#define FLASH_OPTCR_OPTLOCK                  FLASH_OPTCR_OPTLOCK_Msk             /*!< FLASH_OPTCR lock option configuration bit */

+#define FLASH_OPTCR_OPTSTART_Pos             (1U)

+#define FLASH_OPTCR_OPTSTART_Msk             (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */

+#define FLASH_OPTCR_OPTSTART                 FLASH_OPTCR_OPTSTART_Msk            /*!< Option byte start change option configuration bit */

+#define FLASH_OPTCR_MER_Pos                  (4U)

+#define FLASH_OPTCR_MER_Msk                  (0x1UL << FLASH_OPTCR_MER_Pos)      /*!< 0x00000010 */

+#define FLASH_OPTCR_MER                      FLASH_OPTCR_MER_Msk                 /*!< Mass erase request */

+#define FLASH_OPTCR_OPTCHANGEERRIE_Pos       (30U)

+#define FLASH_OPTCR_OPTCHANGEERRIE_Msk       (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */

+#define FLASH_OPTCR_OPTCHANGEERRIE           FLASH_OPTCR_OPTCHANGEERRIE_Msk            /*!< Option byte change error interrupt enable bit */

+#define FLASH_OPTCR_SWAP_BANK_Pos            (31U)

+#define FLASH_OPTCR_SWAP_BANK_Msk            (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */

+#define FLASH_OPTCR_SWAP_BANK                FLASH_OPTCR_SWAP_BANK_Msk            /*!< Bank swapping option configuration bit */

+

+/*******************  Bits definition for FLASH_OPTSR register  ***************/

+#define FLASH_OPTSR_OPT_BUSY_Pos             (0U)

+#define FLASH_OPTSR_OPT_BUSY_Msk             (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */

+#define FLASH_OPTSR_OPT_BUSY                 FLASH_OPTSR_OPT_BUSY_Msk            /*!< Option byte change ongoing flag */

+#define FLASH_OPTSR_BOR_LEV_Pos              (2U)

+#define FLASH_OPTSR_BOR_LEV_Msk              (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */

+#define FLASH_OPTSR_BOR_LEV                  FLASH_OPTSR_BOR_LEV_Msk            /*!< Brownout level option status bit */

+#define FLASH_OPTSR_BOR_LEV_0                (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */

+#define FLASH_OPTSR_BOR_LEV_1                (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */

+#define FLASH_OPTSR_IWDG1_SW_Pos             (4U)

+#define FLASH_OPTSR_IWDG1_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */

+#define FLASH_OPTSR_IWDG1_SW                 FLASH_OPTSR_IWDG1_SW_Msk            /*!< IWDG1 control mode option status bit */

+#define FLASH_OPTSR_NRST_STOP_D1_Pos         (6U)

+#define FLASH_OPTSR_NRST_STOP_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */

+#define FLASH_OPTSR_NRST_STOP_D1             FLASH_OPTSR_NRST_STOP_D1_Msk            /*!< D1 domain DStop entry reset option status bit */

+#define FLASH_OPTSR_NRST_STBY_D1_Pos         (7U)

+#define FLASH_OPTSR_NRST_STBY_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */

+#define FLASH_OPTSR_NRST_STBY_D1             FLASH_OPTSR_NRST_STBY_D1_Msk            /*!< D1 domain DStandby entry reset option status bit */

+#define FLASH_OPTSR_RDP_Pos                  (8U)

+#define FLASH_OPTSR_RDP_Msk                  (0xFFUL << FLASH_OPTSR_RDP_Pos)   /*!< 0x0000FF00 */

+#define FLASH_OPTSR_RDP                      FLASH_OPTSR_RDP_Msk               /*!< Readout protection level option status byte */

+#define FLASH_OPTSR_FZ_IWDG_STOP_Pos         (17U)

+#define FLASH_OPTSR_FZ_IWDG_STOP_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */

+#define FLASH_OPTSR_FZ_IWDG_STOP             FLASH_OPTSR_FZ_IWDG_STOP_Msk            /*!< IWDG Stop mode freeze option status bit */

+#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos         (18U)

+#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */

+#define FLASH_OPTSR_FZ_IWDG_SDBY             FLASH_OPTSR_FZ_IWDG_SDBY_Msk            /*!< IWDG Standby mode freeze option status bit */

+#define FLASH_OPTSR_ST_RAM_SIZE_Pos          (19U)

+#define FLASH_OPTSR_ST_RAM_SIZE_Msk          (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */

+#define FLASH_OPTSR_ST_RAM_SIZE              FLASH_OPTSR_ST_RAM_SIZE_Msk            /*!< ST RAM size option status */

+#define FLASH_OPTSR_ST_RAM_SIZE_0            (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */

+#define FLASH_OPTSR_ST_RAM_SIZE_1            (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */

+#define FLASH_OPTSR_SECURITY_Pos             (21U)

+#define FLASH_OPTSR_SECURITY_Msk             (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */

+#define FLASH_OPTSR_SECURITY                 FLASH_OPTSR_SECURITY_Msk            /*!< Security enable option status bit */

+#define FLASH_OPTSR_IO_HSLV_Pos              (29U)

+#define FLASH_OPTSR_IO_HSLV_Msk              (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */

+#define FLASH_OPTSR_IO_HSLV                  FLASH_OPTSR_IO_HSLV_Msk            /*!< I/O high-speed at low-voltage status bit */

+#define FLASH_OPTSR_OPTCHANGEERR_Pos         (30U)

+#define FLASH_OPTSR_OPTCHANGEERR_Msk         (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */

+#define FLASH_OPTSR_OPTCHANGEERR             FLASH_OPTSR_OPTCHANGEERR_Msk            /*!< Option byte change error flag */

+#define FLASH_OPTSR_SWAP_BANK_OPT_Pos        (31U)

+#define FLASH_OPTSR_SWAP_BANK_OPT_Msk        (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */

+#define FLASH_OPTSR_SWAP_BANK_OPT            FLASH_OPTSR_SWAP_BANK_OPT_Msk            /*!< Bank swapping option status bit */

+

+/*******************  Bits definition for FLASH_OPTCCR register  *******************/

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos    (30U)

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk    (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR        FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk            /*!< OPTCHANGEERR reset bit */

+

+/*******************  Bits definition for FLASH_PRAR register  *********************/

+#define FLASH_PRAR_PROT_AREA_START_Pos       (0U)

+#define FLASH_PRAR_PROT_AREA_START_Msk       (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */

+#define FLASH_PRAR_PROT_AREA_START           FLASH_PRAR_PROT_AREA_START_Msk              /*!< PCROP area start status bits */

+#define FLASH_PRAR_PROT_AREA_END_Pos         (16U)

+#define FLASH_PRAR_PROT_AREA_END_Msk         (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */

+#define FLASH_PRAR_PROT_AREA_END             FLASH_PRAR_PROT_AREA_END_Msk              /*!< PCROP area end status bits */

+#define FLASH_PRAR_DMEP_Pos                  (31U)

+#define FLASH_PRAR_DMEP_Msk                  (0x1UL << FLASH_PRAR_DMEP_Pos)    /*!< 0x80000000 */

+#define FLASH_PRAR_DMEP                      FLASH_PRAR_DMEP_Msk               /*!< PCROP protected erase enable option status bit */

+

+/*******************  Bits definition for FLASH_SCAR register  *********************/

+#define FLASH_SCAR_SEC_AREA_START_Pos        (0U)

+#define FLASH_SCAR_SEC_AREA_START_Msk        (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */

+#define FLASH_SCAR_SEC_AREA_START            FLASH_SCAR_SEC_AREA_START_Msk              /*!< Secure-only area start status bits */

+#define FLASH_SCAR_SEC_AREA_END_Pos          (16U)

+#define FLASH_SCAR_SEC_AREA_END_Msk          (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */

+#define FLASH_SCAR_SEC_AREA_END              FLASH_SCAR_SEC_AREA_END_Msk              /*!< Secure-only area end status bits */

+#define FLASH_SCAR_DMES_Pos                  (31U)

+#define FLASH_SCAR_DMES_Msk                  (0x1UL << FLASH_SCAR_DMES_Pos)    /*!< 0x80000000 */

+#define FLASH_SCAR_DMES                      FLASH_SCAR_DMES_Msk               /*!< Secure access protected erase enable option status bit */

+

+/*******************  Bits definition for FLASH_WPSN register  *********************/

+#define FLASH_WPSN_WRPSN_Pos                 (0U)

+#define FLASH_WPSN_WRPSN_Msk                 (0xFFUL << FLASH_WPSN_WRPSN_Pos)  /*!< 0x000000FF */

+#define FLASH_WPSN_WRPSN                     FLASH_WPSN_WRPSN_Msk              /*!< Sector write protection option status byte */

+

+/*******************  Bits definition for FLASH_BOOT_CUR register  ****************/

+#define FLASH_BOOT_ADD0_Pos                  (0U)

+#define FLASH_BOOT_ADD0_Msk                  (0xFFFFUL << FLASH_BOOT_ADD0_Pos) /*!< 0x0000FFFF */

+#define FLASH_BOOT_ADD0                      FLASH_BOOT_ADD0_Msk               /*!< Arm Cortex-M7 boot address 0 */

+#define FLASH_BOOT_ADD1_Pos                  (16U)

+#define FLASH_BOOT_ADD1_Msk                  (0xFFFFUL << FLASH_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */

+#define FLASH_BOOT_ADD1                      FLASH_BOOT_ADD1_Msk               /*!< Arm Cortex-M7 boot address 1 */

+

+

+/*******************  Bits definition for FLASH_CRCCR register  ********************/

+#define FLASH_CRCCR_CRC_SECT_Pos             (0U)

+#define FLASH_CRCCR_CRC_SECT_Msk             (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */

+#define FLASH_CRCCR_CRC_SECT                 FLASH_CRCCR_CRC_SECT_Msk            /*!< CRC sector number */

+#define FLASH_CRCCR_CRC_BY_SECT_Pos          (8U)

+#define FLASH_CRCCR_CRC_BY_SECT_Msk          (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */

+#define FLASH_CRCCR_CRC_BY_SECT              FLASH_CRCCR_CRC_BY_SECT_Msk            /*!< CRC sector mode select bit */

+#define FLASH_CRCCR_ADD_SECT_Pos             (9U)

+#define FLASH_CRCCR_ADD_SECT_Msk             (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */

+#define FLASH_CRCCR_ADD_SECT                 FLASH_CRCCR_ADD_SECT_Msk            /*!< CRC sector select bit */

+#define FLASH_CRCCR_CLEAN_SECT_Pos           (10U)

+#define FLASH_CRCCR_CLEAN_SECT_Msk           (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */

+#define FLASH_CRCCR_CLEAN_SECT               FLASH_CRCCR_CLEAN_SECT_Msk            /*!< CRC sector list clear bit */

+#define FLASH_CRCCR_START_CRC_Pos            (16U)

+#define FLASH_CRCCR_START_CRC_Msk            (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */

+#define FLASH_CRCCR_START_CRC                FLASH_CRCCR_START_CRC_Msk            /*!< CRC start bit */

+#define FLASH_CRCCR_CLEAN_CRC_Pos            (17U)

+#define FLASH_CRCCR_CLEAN_CRC_Msk            (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */

+#define FLASH_CRCCR_CLEAN_CRC                FLASH_CRCCR_CLEAN_CRC_Msk            /*!< CRC clear bit */

+#define FLASH_CRCCR_CRC_BURST_Pos            (20U)

+#define FLASH_CRCCR_CRC_BURST_Msk            (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */

+#define FLASH_CRCCR_CRC_BURST                FLASH_CRCCR_CRC_BURST_Msk            /*!< CRC burst size */

+#define FLASH_CRCCR_CRC_BURST_0              (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */

+#define FLASH_CRCCR_CRC_BURST_1              (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */

+#define FLASH_CRCCR_ALL_BANK_Pos             (22U)

+#define FLASH_CRCCR_ALL_BANK_Msk             (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */

+#define FLASH_CRCCR_ALL_BANK                 FLASH_CRCCR_ALL_BANK_Msk            /*!< CRC select bit */

+

+/*******************  Bits definition for FLASH_CRCSADD register  ****************/

+#define FLASH_CRCSADD_CRC_START_ADDR_Pos     (0U)

+#define FLASH_CRCSADD_CRC_START_ADDR_Msk     (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCSADD_CRC_START_ADDR         FLASH_CRCSADD_CRC_START_ADDR_Msk                   /*!< CRC start address */

+

+/*******************  Bits definition for FLASH_CRCEADD register  ****************/

+#define FLASH_CRCEADD_CRC_END_ADDR_Pos       (0U)

+#define FLASH_CRCEADD_CRC_END_ADDR_Msk       (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCEADD_CRC_END_ADDR           FLASH_CRCEADD_CRC_END_ADDR_Msk                   /*!< CRC end address */

+

+/*******************  Bits definition for FLASH_CRCDATA register  ***************/

+#define FLASH_CRCDATA_CRC_DATA_Pos           (0U)

+#define FLASH_CRCDATA_CRC_DATA_Msk           (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCDATA_CRC_DATA               FLASH_CRCDATA_CRC_DATA_Msk                   /*!< CRC result */

+

+/*******************  Bits definition for FLASH_ECC_FA register  *******************/

+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos       (0U)

+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk       (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */

+#define FLASH_ECC_FA_FAIL_ECC_ADDR           FLASH_ECC_FA_FAIL_ECC_ADDR_Msk               /*!< ECC error address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          Flexible Memory Controller                        */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for FMC_BCR1 register  *******************/

+#define FMC_BCR1_CCLKEN_Pos        (20U)

+#define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */

+#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continous clock enable     */

+#define FMC_BCR1_WFDIS_Pos         (21U)

+#define FMC_BCR1_WFDIS_Msk         (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */

+#define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */

+

+#define FMC_BCR1_BMAP_Pos          (24U)

+#define FMC_BCR1_BMAP_Msk          (0x3UL << FMC_BCR1_BMAP_Pos)                /*!< 0x03000000 */

+#define FMC_BCR1_BMAP              FMC_BCR1_BMAP_Msk                           /*!<BMAP[1:0] FMC bank mapping */

+#define FMC_BCR1_BMAP_0            (0x1UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x01000000 */

+#define FMC_BCR1_BMAP_1            (0x2UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x02000000 */

+

+#define FMC_BCR1_FMCEN_Pos         (31U)

+#define FMC_BCR1_FMCEN_Msk         (0x1UL << FMC_BCR1_FMCEN_Pos)               /*!< 0x80000000 */

+#define FMC_BCR1_FMCEN             FMC_BCR1_FMCEN_Msk                          /*!<FMC controller Enable */

+/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/

+#define FMC_BCRx_MBKEN_Pos         (0U)

+#define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */

+#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */

+#define FMC_BCRx_MUXEN_Pos         (1U)

+#define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */

+#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */

+

+#define FMC_BCRx_MTYP_Pos          (2U)

+#define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */

+#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */

+#define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000004 */

+#define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000008 */

+

+#define FMC_BCRx_MWID_Pos          (4U)

+#define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */

+#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */

+#define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000010 */

+#define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000020 */

+

+#define FMC_BCRx_FACCEN_Pos        (6U)

+#define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */

+#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */

+#define FMC_BCRx_BURSTEN_Pos       (8U)

+#define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */

+#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */

+#define FMC_BCRx_WAITPOL_Pos       (9U)

+#define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */

+#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */

+#define FMC_BCRx_WAITCFG_Pos       (11U)

+#define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */

+#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */

+#define FMC_BCRx_WREN_Pos          (12U)

+#define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */

+#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */

+#define FMC_BCRx_WAITEN_Pos        (13U)

+#define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */

+#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */

+#define FMC_BCRx_EXTMOD_Pos        (14U)

+#define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */

+#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */

+#define FMC_BCRx_ASYNCWAIT_Pos     (15U)

+#define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */

+#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */

+

+#define FMC_BCRx_CPSIZE_Pos        (16U)

+#define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */

+#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<PSIZE[2:0] bits CRAM Page Size */

+#define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00010000 */

+#define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00020000 */

+#define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00040000 */

+

+#define FMC_BCRx_CBURSTRW_Pos      (19U)

+#define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */

+#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */

+

+/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/

+#define FMC_BTRx_ADDSET_Pos        (0U)

+#define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */

+#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */

+#define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000001 */

+#define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000002 */

+#define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000004 */

+#define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000008 */

+

+#define FMC_BTRx_ADDHLD_Pos        (4U)

+#define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */

+#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */

+#define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000010 */

+#define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000020 */

+#define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000040 */

+#define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000080 */

+

+#define FMC_BTRx_DATAST_Pos        (8U)

+#define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */

+#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */

+#define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000100 */

+#define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000200 */

+#define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000400 */

+#define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000800 */

+#define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00001000 */

+#define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00002000 */

+#define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00004000 */

+#define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00008000 */

+

+#define FMC_BTRx_BUSTURN_Pos       (16U)

+#define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */

+#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */

+#define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00010000 */

+#define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00020000 */

+#define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00040000 */

+#define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00080000 */

+

+#define FMC_BTRx_CLKDIV_Pos        (20U)

+#define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */

+#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */

+#define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00100000 */

+#define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00200000 */

+#define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00400000 */

+#define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00800000 */

+

+#define FMC_BTRx_DATLAT_Pos        (24U)

+#define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */

+#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */

+#define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x01000000 */

+#define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x02000000 */

+#define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x04000000 */

+#define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x08000000 */

+

+#define FMC_BTRx_ACCMOD_Pos        (28U)

+#define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */

+#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */

+#define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x10000000 */

+#define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x20000000 */

+

+/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/

+#define FMC_BWTRx_ADDSET_Pos       (0U)

+#define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */

+#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */

+#define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000001 */

+#define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000002 */

+#define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000004 */

+#define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000008 */

+

+#define FMC_BWTRx_ADDHLD_Pos       (4U)

+#define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */

+#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */

+#define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000010 */

+#define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000020 */

+#define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000040 */

+#define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000080 */

+

+#define FMC_BWTRx_DATAST_Pos       (8U)

+#define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */

+#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */

+#define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000100 */

+#define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000200 */

+#define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000400 */

+#define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000800 */

+#define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00001000 */

+#define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00002000 */

+#define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00004000 */

+#define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00008000 */

+

+#define FMC_BWTRx_BUSTURN_Pos      (16U)

+#define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */

+#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */

+#define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00010000 */

+#define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00020000 */

+#define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00040000 */

+#define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00080000 */

+

+#define FMC_BWTRx_ACCMOD_Pos       (28U)

+#define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */

+#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */

+#define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x10000000 */

+#define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x20000000 */

+

+/******************  Bit definition for FMC_PCR register  *******************/

+#define FMC_PCR_PWAITEN_Pos        (1U)

+#define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */

+#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */

+#define FMC_PCR_PBKEN_Pos          (2U)

+#define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */

+#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */

+

+#define FMC_PCR_PWID_Pos           (4U)

+#define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */

+#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */

+#define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */

+#define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */

+

+#define FMC_PCR_ECCEN_Pos          (6U)

+#define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */

+#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */

+

+#define FMC_PCR_TCLR_Pos           (9U)

+#define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */

+#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */

+#define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */

+#define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */

+#define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */

+#define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */

+

+#define FMC_PCR_TAR_Pos            (13U)

+#define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */

+#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */

+#define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */

+#define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */

+#define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */

+#define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */

+

+#define FMC_PCR_ECCPS_Pos          (17U)

+#define FMC_PCR_ECCPS_Msk          (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */

+#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */

+#define FMC_PCR_ECCPS_0            (0x1UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */

+#define FMC_PCR_ECCPS_1            (0x2UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */

+#define FMC_PCR_ECCPS_2            (0x4UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */

+

+/*******************  Bit definition for FMC_SR register  *******************/

+#define FMC_SR_IRS_Pos             (0U)

+#define FMC_SR_IRS_Msk             (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */

+#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */

+#define FMC_SR_ILS_Pos             (1U)

+#define FMC_SR_ILS_Msk             (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */

+#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */

+#define FMC_SR_IFS_Pos             (2U)

+#define FMC_SR_IFS_Msk             (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */

+#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */

+#define FMC_SR_IREN_Pos            (3U)

+#define FMC_SR_IREN_Msk            (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */

+#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */

+#define FMC_SR_ILEN_Pos            (4U)

+#define FMC_SR_ILEN_Msk            (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */

+#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */

+#define FMC_SR_IFEN_Pos            (5U)

+#define FMC_SR_IFEN_Msk            (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */

+#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */

+#define FMC_SR_FEMPT_Pos           (6U)

+#define FMC_SR_FEMPT_Msk           (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */

+#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */

+

+/******************  Bit definition for FMC_PMEM register  ******************/

+#define FMC_PMEM_MEMSET_Pos       (0U)

+#define FMC_PMEM_MEMSET_Msk       (0xFFUL << FMC_PMEM_MEMSET_Pos)            /*!< 0x000000FF */

+#define FMC_PMEM_MEMSET           FMC_PMEM_MEMSET_Msk                        /*!<MEMSET[7:0] bits (Common memory setup time) */

+#define FMC_PMEM_MEMSET_0         (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */

+#define FMC_PMEM_MEMSET_1         (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */

+#define FMC_PMEM_MEMSET_2         (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */

+#define FMC_PMEM_MEMSET_3         (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */

+#define FMC_PMEM_MEMSET_4         (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */

+#define FMC_PMEM_MEMSET_5         (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */

+#define FMC_PMEM_MEMSET_6         (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */

+#define FMC_PMEM_MEMSET_7         (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */

+

+#define FMC_PMEM_MEMWAIT_Pos      (8U)

+#define FMC_PMEM_MEMWAIT_Msk      (0xFFUL << FMC_PMEM_MEMWAIT_Pos)           /*!< 0x0000FF00 */

+#define FMC_PMEM_MEMWAIT          FMC_PMEM_MEMWAIT_Msk                       /*!<MEMWAIT[7:0] bits (Common memory wait time) */

+#define FMC_PMEM_MEMWAIT_0        (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */

+#define FMC_PMEM_MEMWAIT_1        (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */

+#define FMC_PMEM_MEMWAIT_2        (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */

+#define FMC_PMEM_MEMWAIT_3        (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */

+#define FMC_PMEM_MEMWAIT_4        (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */

+#define FMC_PMEM_MEMWAIT_5        (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */

+#define FMC_PMEM_MEMWAIT_6        (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */

+#define FMC_PMEM_MEMWAIT_7        (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */

+

+#define FMC_PMEM_MEMHOLD_Pos      (16U)

+#define FMC_PMEM_MEMHOLD_Msk      (0xFFUL << FMC_PMEM_MEMHOLD_Pos)           /*!< 0x00FF0000 */

+#define FMC_PMEM_MEMHOLD          FMC_PMEM_MEMHOLD_Msk                       /*!<MEMHOLD[7:0] bits (Common memory hold time) */

+#define FMC_PMEM_MEMHOLD_0        (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */

+#define FMC_PMEM_MEMHOLD_1        (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */

+#define FMC_PMEM_MEMHOLD_2        (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */

+#define FMC_PMEM_MEMHOLD_3        (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */

+#define FMC_PMEM_MEMHOLD_4        (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */

+#define FMC_PMEM_MEMHOLD_5        (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */

+#define FMC_PMEM_MEMHOLD_6        (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */

+#define FMC_PMEM_MEMHOLD_7        (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */

+

+#define FMC_PMEM_MEMHIZ_Pos       (24U)

+#define FMC_PMEM_MEMHIZ_Msk       (0xFFUL << FMC_PMEM_MEMHIZ_Pos)            /*!< 0xFF000000 */

+#define FMC_PMEM_MEMHIZ           FMC_PMEM_MEMHIZ_Msk                        /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */

+#define FMC_PMEM_MEMHIZ_0         (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */

+#define FMC_PMEM_MEMHIZ_1         (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */

+#define FMC_PMEM_MEMHIZ_2         (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */

+#define FMC_PMEM_MEMHIZ_3         (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */

+#define FMC_PMEM_MEMHIZ_4         (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */

+#define FMC_PMEM_MEMHIZ_5         (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */

+#define FMC_PMEM_MEMHIZ_6         (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */

+#define FMC_PMEM_MEMHIZ_7         (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */

+

+/******************  Bit definition for FMC_PATT register  ******************/

+#define FMC_PATT_ATTSET_Pos       (0U)

+#define FMC_PATT_ATTSET_Msk       (0xFFUL << FMC_PATT_ATTSET_Pos)            /*!< 0x000000FF */

+#define FMC_PATT_ATTSET           FMC_PATT_ATTSET_Msk                        /*!<ATTSET[7:0] bits (Attribute memory setup time) */

+#define FMC_PATT_ATTSET_0         (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */

+#define FMC_PATT_ATTSET_1         (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */

+#define FMC_PATT_ATTSET_2         (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */

+#define FMC_PATT_ATTSET_3         (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */

+#define FMC_PATT_ATTSET_4         (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */

+#define FMC_PATT_ATTSET_5         (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */

+#define FMC_PATT_ATTSET_6         (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */

+#define FMC_PATT_ATTSET_7         (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */

+

+#define FMC_PATT_ATTWAIT_Pos      (8U)

+#define FMC_PATT_ATTWAIT_Msk      (0xFFUL << FMC_PATT_ATTWAIT_Pos)           /*!< 0x0000FF00 */

+#define FMC_PATT_ATTWAIT          FMC_PATT_ATTWAIT_Msk                       /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */

+#define FMC_PATT_ATTWAIT_0        (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */

+#define FMC_PATT_ATTWAIT_1        (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */

+#define FMC_PATT_ATTWAIT_2        (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */

+#define FMC_PATT_ATTWAIT_3        (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */

+#define FMC_PATT_ATTWAIT_4        (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */

+#define FMC_PATT_ATTWAIT_5        (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */

+#define FMC_PATT_ATTWAIT_6        (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */

+#define FMC_PATT_ATTWAIT_7        (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */

+

+#define FMC_PATT_ATTHOLD_Pos      (16U)

+#define FMC_PATT_ATTHOLD_Msk      (0xFFUL << FMC_PATT_ATTHOLD_Pos)           /*!< 0x00FF0000 */

+#define FMC_PATT_ATTHOLD          FMC_PATT_ATTHOLD_Msk                       /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */

+#define FMC_PATT_ATTHOLD_0        (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */

+#define FMC_PATT_ATTHOLD_1        (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */

+#define FMC_PATT_ATTHOLD_2        (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */

+#define FMC_PATT_ATTHOLD_3        (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */

+#define FMC_PATT_ATTHOLD_4        (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */

+#define FMC_PATT_ATTHOLD_5        (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */

+#define FMC_PATT_ATTHOLD_6        (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */

+#define FMC_PATT_ATTHOLD_7        (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */

+

+#define FMC_PATT_ATTHIZ_Pos       (24U)

+#define FMC_PATT_ATTHIZ_Msk       (0xFFUL << FMC_PATT_ATTHIZ_Pos)            /*!< 0xFF000000 */

+#define FMC_PATT_ATTHIZ           FMC_PATT_ATTHIZ_Msk                        /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */

+#define FMC_PATT_ATTHIZ_0         (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */

+#define FMC_PATT_ATTHIZ_1         (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */

+#define FMC_PATT_ATTHIZ_2         (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */

+#define FMC_PATT_ATTHIZ_3         (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */

+#define FMC_PATT_ATTHIZ_4         (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */

+#define FMC_PATT_ATTHIZ_5         (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */

+#define FMC_PATT_ATTHIZ_6         (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */

+#define FMC_PATT_ATTHIZ_7         (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */

+

+/******************  Bit definition for FMC_ECCR3 register  ******************/

+#define FMC_ECCR3_ECC3_Pos         (0U)

+#define FMC_ECCR3_ECC3_Msk         (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)        /*!< 0xFFFFFFFF */

+#define FMC_ECCR3_ECC3             FMC_ECCR3_ECC3_Msk                          /*!<ECC result */

+

+/******************  Bit definition for FMC_SDCRx registers (x=1..4)  *********/

+#define FMC_SDCRx_NC_Pos           (0U)

+#define FMC_SDCRx_NC_Msk           (0x3UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000003 */

+#define FMC_SDCRx_NC               FMC_SDCRx_NC_Msk                            /*!<NC[1:0] bits (Number of column bits) */

+#define FMC_SDCRx_NC_0             (0x1UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000001 */

+#define FMC_SDCRx_NC_1             (0x2UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000002 */

+

+#define FMC_SDCRx_NR_Pos           (2U)

+#define FMC_SDCRx_NR_Msk           (0x3UL << FMC_SDCRx_NR_Pos)                 /*!< 0x0000000C */

+#define FMC_SDCRx_NR               FMC_SDCRx_NR_Msk                            /*!<NR[1:0] bits (Number of row bits) */

+#define FMC_SDCRx_NR_0             (0x1UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000004 */

+#define FMC_SDCRx_NR_1             (0x2UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000008 */

+

+#define FMC_SDCRx_MWID_Pos         (4U)

+#define FMC_SDCRx_MWID_Msk         (0x3UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000030 */

+#define FMC_SDCRx_MWID             FMC_SDCRx_MWID_Msk                          /*!<NR[1:0] bits (Number of row bits) */

+#define FMC_SDCRx_MWID_0           (0x1UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000010 */

+#define FMC_SDCRx_MWID_1           (0x2UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000020 */

+

+#define FMC_SDCRx_NB_Pos           (6U)

+#define FMC_SDCRx_NB_Msk           (0x1UL << FMC_SDCRx_NB_Pos)                 /*!< 0x00000040 */

+#define FMC_SDCRx_NB               FMC_SDCRx_NB_Msk                            /*!<Number of internal bank */

+

+#define FMC_SDCRx_CAS_Pos          (7U)

+#define FMC_SDCRx_CAS_Msk          (0x3UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000180 */

+#define FMC_SDCRx_CAS              FMC_SDCRx_CAS_Msk                           /*!<CAS[1:0] bits (CAS latency) */

+#define FMC_SDCRx_CAS_0            (0x1UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000080 */

+#define FMC_SDCRx_CAS_1            (0x2UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000100 */

+

+#define FMC_SDCRx_WP_Pos           (9U)

+#define FMC_SDCRx_WP_Msk           (0x1UL << FMC_SDCRx_WP_Pos)                 /*!< 0x00000200 */

+#define FMC_SDCRx_WP               FMC_SDCRx_WP_Msk                            /*!<Write protection */

+

+#define FMC_SDCRx_SDCLK_Pos        (10U)

+#define FMC_SDCRx_SDCLK_Msk        (0x3UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000C00 */

+#define FMC_SDCRx_SDCLK            FMC_SDCRx_SDCLK_Msk                         /*!<SDRAM clock configuration */

+#define FMC_SDCRx_SDCLK_0          (0x1UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000400 */

+#define FMC_SDCRx_SDCLK_1          (0x2UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000800 */

+

+#define FMC_SDCRx_RBURST_Pos       (12U)

+#define FMC_SDCRx_RBURST_Msk       (0x1UL << FMC_SDCRx_RBURST_Pos)             /*!< 0x00001000 */

+#define FMC_SDCRx_RBURST           FMC_SDCRx_RBURST_Msk                        /*!<Read burst */

+

+#define FMC_SDCRx_RPIPE_Pos        (13U)

+#define FMC_SDCRx_RPIPE_Msk        (0x3UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00006000 */

+#define FMC_SDCRx_RPIPE            FMC_SDCRx_RPIPE_Msk                         /*!<Write protection */

+#define FMC_SDCRx_RPIPE_0          (0x1UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00002000 */

+#define FMC_SDCRx_RPIPE_1          (0x2UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00004000 */

+

+/******************  Bit definition for FMC_SDTRx(1,2) register  ******************/

+#define FMC_SDTRx_TMRD_Pos         (0U)

+#define FMC_SDTRx_TMRD_Msk         (0xFUL << FMC_SDTRx_TMRD_Pos)               /*!< 0x0000000F */

+#define FMC_SDTRx_TMRD             FMC_SDTRx_TMRD_Msk                          /*!<TMRD[3:0] bits (Load mode register to active) */

+#define FMC_SDTRx_TMRD_0           (0x1UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000001 */

+#define FMC_SDTRx_TMRD_1           (0x2UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000002 */

+#define FMC_SDTRx_TMRD_2           (0x4UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000004 */

+#define FMC_SDTRx_TMRD_3           (0x8UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000008 */

+

+#define FMC_SDTRx_TXSR_Pos         (4U)

+#define FMC_SDTRx_TXSR_Msk         (0xFUL << FMC_SDTRx_TXSR_Pos)               /*!< 0x000000F0 */

+#define FMC_SDTRx_TXSR             FMC_SDTRx_TXSR_Msk                          /*!<TXSR[3:0] bits (Exit self refresh) */

+#define FMC_SDTRx_TXSR_0           (0x1UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000010 */

+#define FMC_SDTRx_TXSR_1           (0x2UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000020 */

+#define FMC_SDTRx_TXSR_2           (0x4UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000040 */

+#define FMC_SDTRx_TXSR_3           (0x8UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000080 */

+

+#define FMC_SDTRx_TRAS_Pos         (8U)

+#define FMC_SDTRx_TRAS_Msk         (0xFUL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000F00 */

+#define FMC_SDTRx_TRAS             FMC_SDTRx_TRAS_Msk                          /*!<TRAS[3:0] bits (Self refresh time) */

+#define FMC_SDTRx_TRAS_0           (0x1UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000100 */

+#define FMC_SDTRx_TRAS_1           (0x2UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000200 */

+#define FMC_SDTRx_TRAS_2           (0x4UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000400 */

+#define FMC_SDTRx_TRAS_3           (0x8UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000800 */

+

+#define FMC_SDTRx_TRC_Pos          (12U)

+#define FMC_SDTRx_TRC_Msk          (0xFUL << FMC_SDTRx_TRC_Pos)                /*!< 0x0000F000 */

+#define FMC_SDTRx_TRC              FMC_SDTRx_TRC_Msk                           /*!<TRC[2:0] bits (Row cycle delay) */

+#define FMC_SDTRx_TRC_0            (0x1UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00001000 */

+#define FMC_SDTRx_TRC_1            (0x2UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00002000 */

+#define FMC_SDTRx_TRC_2            (0x4UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00004000 */

+

+#define FMC_SDTRx_TWR_Pos          (16U)

+#define FMC_SDTRx_TWR_Msk          (0xFUL << FMC_SDTRx_TWR_Pos)                /*!< 0x000F0000 */

+#define FMC_SDTRx_TWR              FMC_SDTRx_TWR_Msk                           /*!<TRC[2:0] bits (Write recovery delay) */

+#define FMC_SDTRx_TWR_0            (0x1UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00010000 */

+#define FMC_SDTRx_TWR_1            (0x2UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00020000 */

+#define FMC_SDTRx_TWR_2            (0x4UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00040000 */

+

+#define FMC_SDTRx_TRP_Pos          (20U)

+#define FMC_SDTRx_TRP_Msk          (0xFUL << FMC_SDTRx_TRP_Pos)                /*!< 0x00F00000 */

+#define FMC_SDTRx_TRP              FMC_SDTRx_TRP_Msk                           /*!<TRP[2:0] bits (Row precharge delay) */

+#define FMC_SDTRx_TRP_0            (0x1UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00100000 */

+#define FMC_SDTRx_TRP_1            (0x2UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00200000 */

+#define FMC_SDTRx_TRP_2            (0x4UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00400000 */

+

+#define FMC_SDTRx_TRCD_Pos         (24U)

+#define FMC_SDTRx_TRCD_Msk         (0xFUL << FMC_SDTRx_TRCD_Pos)               /*!< 0x0F000000 */

+#define FMC_SDTRx_TRCD             FMC_SDTRx_TRCD_Msk                          /*!<TRP[2:0] bits (Row to column delay) */

+#define FMC_SDTRx_TRCD_0           (0x1UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x01000000 */

+#define FMC_SDTRx_TRCD_1           (0x2UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x02000000 */

+#define FMC_SDTRx_TRCD_2           (0x4UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x04000000 */

+

+/******************  Bit definition for FMC_SDCMR register  ******************/

+#define FMC_SDCMR_MODE_Pos         (0U)

+#define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */

+#define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */

+#define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */

+#define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */

+#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */

+

+#define FMC_SDCMR_CTB2_Pos         (3U)

+#define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */

+#define FMC_SDCMR_CTB2             FMC_SDCMR_CTB2_Msk                          /*!<Command target 2 */

+

+#define FMC_SDCMR_CTB1_Pos         (4U)

+#define FMC_SDCMR_CTB1_Msk         (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */

+#define FMC_SDCMR_CTB1             FMC_SDCMR_CTB1_Msk                          /*!<Command target 1 */

+

+#define FMC_SDCMR_NRFS_Pos         (5U)

+#define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */

+#define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!<NRFS[3:0] bits (Number of auto-refresh) */

+#define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000020 */

+#define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000040 */

+#define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000080 */

+#define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000100 */

+

+#define FMC_SDCMR_MRD_Pos          (9U)

+#define FMC_SDCMR_MRD_Msk          (0x1FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */

+#define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!<MRD[12:0] bits (Mode register definition) */

+

+/******************  Bit definition for FMC_SDRTR register  ******************/

+#define FMC_SDRTR_CRE_Pos          (0U)

+#define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */

+#define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!<Clear refresh error flag */

+

+#define FMC_SDRTR_COUNT_Pos        (1U)

+#define FMC_SDRTR_COUNT_Msk        (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */

+#define FMC_SDRTR_COUNT            FMC_SDRTR_COUNT_Msk                         /*!<COUNT[12:0] bits (Refresh timer count) */

+

+#define FMC_SDRTR_REIE_Pos         (14U)

+#define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */

+#define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!<RES interupt enable */

+

+/******************  Bit definition for FMC_SDSR register  ******************/

+#define FMC_SDSR_RE_Pos            (0U)

+#define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */

+#define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!<Refresh error flag */

+

+#define FMC_SDSR_MODES1_Pos        (1U)

+#define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */

+#define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!<MODES1[1:0]bits (Status mode for bank 1) */

+#define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000002 */

+#define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000004 */

+

+#define FMC_SDSR_MODES2_Pos        (3U)

+#define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */

+#define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!<MODES2[1:0]bits (Status mode for bank 2) */

+#define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000008 */

+#define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000010 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            General Purpose I/O                             */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bits definition for GPIO_MODER register  *****************/

+#define GPIO_MODER_MODE0_Pos           (0U)

+#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */

+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk

+#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */

+#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */

+

+#define GPIO_MODER_MODE1_Pos           (2U)

+#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */

+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk

+#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */

+#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */

+

+#define GPIO_MODER_MODE2_Pos           (4U)

+#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */

+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk

+#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */

+#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */

+

+#define GPIO_MODER_MODE3_Pos           (6U)

+#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */

+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk

+#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */

+#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */

+

+#define GPIO_MODER_MODE4_Pos           (8U)

+#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */

+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk

+#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */

+#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */

+

+#define GPIO_MODER_MODE5_Pos           (10U)

+#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */

+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk

+#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */

+#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */

+

+#define GPIO_MODER_MODE6_Pos           (12U)

+#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */

+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk

+#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */

+#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */

+

+#define GPIO_MODER_MODE7_Pos           (14U)

+#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */

+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk

+#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */

+#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */

+

+#define GPIO_MODER_MODE8_Pos           (16U)

+#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */

+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk

+#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */

+#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */

+

+#define GPIO_MODER_MODE9_Pos           (18U)

+#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */

+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk

+#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */

+#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */

+

+#define GPIO_MODER_MODE10_Pos          (20U)

+#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */

+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk

+#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */

+#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */

+

+#define GPIO_MODER_MODE11_Pos          (22U)

+#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */

+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk

+#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */

+#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */

+

+#define GPIO_MODER_MODE12_Pos          (24U)

+#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */

+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk

+#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */

+#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */

+

+#define GPIO_MODER_MODE13_Pos          (26U)

+#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */

+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk

+#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */

+#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */

+

+#define GPIO_MODER_MODE14_Pos          (28U)

+#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */

+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk

+#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */

+#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */

+

+#define GPIO_MODER_MODE15_Pos          (30U)

+#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */

+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk

+#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */

+#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_OTYPER register  ****************/

+#define GPIO_OTYPER_OT0_Pos            (0U)

+#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */

+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk

+#define GPIO_OTYPER_OT1_Pos            (1U)

+#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */

+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk

+#define GPIO_OTYPER_OT2_Pos            (2U)

+#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */

+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk

+#define GPIO_OTYPER_OT3_Pos            (3U)

+#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */

+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk

+#define GPIO_OTYPER_OT4_Pos            (4U)

+#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */

+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk

+#define GPIO_OTYPER_OT5_Pos            (5U)

+#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */

+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk

+#define GPIO_OTYPER_OT6_Pos            (6U)

+#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */

+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk

+#define GPIO_OTYPER_OT7_Pos            (7U)

+#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */

+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk

+#define GPIO_OTYPER_OT8_Pos            (8U)

+#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */

+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk

+#define GPIO_OTYPER_OT9_Pos            (9U)

+#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */

+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk

+#define GPIO_OTYPER_OT10_Pos           (10U)

+#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */

+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk

+#define GPIO_OTYPER_OT11_Pos           (11U)

+#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */

+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk

+#define GPIO_OTYPER_OT12_Pos           (12U)

+#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */

+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk

+#define GPIO_OTYPER_OT13_Pos           (13U)

+#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */

+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk

+#define GPIO_OTYPER_OT14_Pos           (14U)

+#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */

+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk

+#define GPIO_OTYPER_OT15_Pos           (15U)

+#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */

+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk

+

+/******************  Bits definition for GPIO_OSPEEDR register  ***************/

+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)

+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */

+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk

+#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */

+#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */

+

+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)

+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */

+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk

+#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */

+#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */

+

+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)

+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */

+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk

+#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */

+#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */

+

+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)

+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */

+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk

+#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */

+#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */

+

+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)

+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */

+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk

+#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */

+#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */

+

+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)

+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */

+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk

+#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */

+#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */

+

+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)

+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */

+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk

+#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */

+#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */

+

+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)

+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */

+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk

+#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */

+#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */

+

+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)

+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */

+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk

+#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */

+#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */

+

+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)

+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */

+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk

+#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */

+#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */

+

+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)

+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */

+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk

+#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */

+#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */

+

+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)

+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */

+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk

+#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */

+#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */

+

+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)

+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */

+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk

+#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */

+#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */

+

+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)

+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */

+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk

+#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */

+#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */

+

+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)

+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */

+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk

+#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */

+#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */

+

+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)

+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */

+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk

+#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */

+#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_PUPDR register  *****************/

+#define GPIO_PUPDR_PUPD0_Pos           (0U)

+#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */

+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk

+#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */

+#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */

+

+#define GPIO_PUPDR_PUPD1_Pos           (2U)

+#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */

+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk

+#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */

+#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */

+

+#define GPIO_PUPDR_PUPD2_Pos           (4U)

+#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */

+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk

+#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */

+#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */

+

+#define GPIO_PUPDR_PUPD3_Pos           (6U)

+#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */

+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk

+#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */

+#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */

+

+#define GPIO_PUPDR_PUPD4_Pos           (8U)

+#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */

+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk

+#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */

+#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */

+

+#define GPIO_PUPDR_PUPD5_Pos           (10U)

+#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */

+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk

+#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */

+#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */

+

+#define GPIO_PUPDR_PUPD6_Pos           (12U)

+#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */

+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk

+#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */

+#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */

+

+#define GPIO_PUPDR_PUPD7_Pos           (14U)

+#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */

+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk

+#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */

+#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */

+

+#define GPIO_PUPDR_PUPD8_Pos           (16U)

+#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */

+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk

+#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */

+#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */

+

+#define GPIO_PUPDR_PUPD9_Pos           (18U)

+#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */

+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk

+#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */

+#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */

+

+#define GPIO_PUPDR_PUPD10_Pos          (20U)

+#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */

+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk

+#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */

+#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */

+

+#define GPIO_PUPDR_PUPD11_Pos          (22U)

+#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */

+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk

+#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */

+#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */

+

+#define GPIO_PUPDR_PUPD12_Pos          (24U)

+#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */

+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk

+#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */

+#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */

+

+#define GPIO_PUPDR_PUPD13_Pos          (26U)

+#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */

+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk

+#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */

+#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */

+

+#define GPIO_PUPDR_PUPD14_Pos          (28U)

+#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */

+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk

+#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */

+#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */

+

+#define GPIO_PUPDR_PUPD15_Pos          (30U)

+#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */

+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk

+#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */

+#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_IDR register  *******************/

+#define GPIO_IDR_ID0_Pos               (0U)

+#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */

+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk

+#define GPIO_IDR_ID1_Pos               (1U)

+#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */

+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk

+#define GPIO_IDR_ID2_Pos               (2U)

+#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */

+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk

+#define GPIO_IDR_ID3_Pos               (3U)

+#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */

+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk

+#define GPIO_IDR_ID4_Pos               (4U)

+#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */

+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk

+#define GPIO_IDR_ID5_Pos               (5U)

+#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */

+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk

+#define GPIO_IDR_ID6_Pos               (6U)

+#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */

+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk

+#define GPIO_IDR_ID7_Pos               (7U)

+#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */

+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk

+#define GPIO_IDR_ID8_Pos               (8U)

+#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */

+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk

+#define GPIO_IDR_ID9_Pos               (9U)

+#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */

+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk

+#define GPIO_IDR_ID10_Pos              (10U)

+#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */

+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk

+#define GPIO_IDR_ID11_Pos              (11U)

+#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */

+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk

+#define GPIO_IDR_ID12_Pos              (12U)

+#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */

+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk

+#define GPIO_IDR_ID13_Pos              (13U)

+#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */

+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk

+#define GPIO_IDR_ID14_Pos              (14U)

+#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */

+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk

+#define GPIO_IDR_ID15_Pos              (15U)

+#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */

+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk

+

+/******************  Bits definition for GPIO_ODR register  *******************/

+#define GPIO_ODR_OD0_Pos               (0U)

+#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */

+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk

+#define GPIO_ODR_OD1_Pos               (1U)

+#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */

+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk

+#define GPIO_ODR_OD2_Pos               (2U)

+#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */

+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk

+#define GPIO_ODR_OD3_Pos               (3U)

+#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */

+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk

+#define GPIO_ODR_OD4_Pos               (4U)

+#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */

+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk

+#define GPIO_ODR_OD5_Pos               (5U)

+#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */

+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk

+#define GPIO_ODR_OD6_Pos               (6U)

+#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */

+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk

+#define GPIO_ODR_OD7_Pos               (7U)

+#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */

+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk

+#define GPIO_ODR_OD8_Pos               (8U)

+#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */

+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk

+#define GPIO_ODR_OD9_Pos               (9U)

+#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */

+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk

+#define GPIO_ODR_OD10_Pos              (10U)

+#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */

+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk

+#define GPIO_ODR_OD11_Pos              (11U)

+#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */

+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk

+#define GPIO_ODR_OD12_Pos              (12U)

+#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */

+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk

+#define GPIO_ODR_OD13_Pos              (13U)

+#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */

+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk

+#define GPIO_ODR_OD14_Pos              (14U)

+#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */

+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk

+#define GPIO_ODR_OD15_Pos              (15U)

+#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */

+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk

+

+/******************  Bits definition for GPIO_BSRR register  ******************/

+#define GPIO_BSRR_BS0_Pos              (0U)

+#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */

+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk

+#define GPIO_BSRR_BS1_Pos              (1U)

+#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */

+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk

+#define GPIO_BSRR_BS2_Pos              (2U)

+#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */

+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk

+#define GPIO_BSRR_BS3_Pos              (3U)

+#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */

+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk

+#define GPIO_BSRR_BS4_Pos              (4U)

+#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */

+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk

+#define GPIO_BSRR_BS5_Pos              (5U)

+#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */

+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk

+#define GPIO_BSRR_BS6_Pos              (6U)

+#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */

+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk

+#define GPIO_BSRR_BS7_Pos              (7U)

+#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */

+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk

+#define GPIO_BSRR_BS8_Pos              (8U)

+#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */

+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk

+#define GPIO_BSRR_BS9_Pos              (9U)

+#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */

+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk

+#define GPIO_BSRR_BS10_Pos             (10U)

+#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */

+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk

+#define GPIO_BSRR_BS11_Pos             (11U)

+#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */

+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk

+#define GPIO_BSRR_BS12_Pos             (12U)

+#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */

+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk

+#define GPIO_BSRR_BS13_Pos             (13U)

+#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */

+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk

+#define GPIO_BSRR_BS14_Pos             (14U)

+#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */

+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk

+#define GPIO_BSRR_BS15_Pos             (15U)

+#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */

+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk

+#define GPIO_BSRR_BR0_Pos              (16U)

+#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */

+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk

+#define GPIO_BSRR_BR1_Pos              (17U)

+#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */

+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk

+#define GPIO_BSRR_BR2_Pos              (18U)

+#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */

+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk

+#define GPIO_BSRR_BR3_Pos              (19U)

+#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */

+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk

+#define GPIO_BSRR_BR4_Pos              (20U)

+#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */

+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk

+#define GPIO_BSRR_BR5_Pos              (21U)

+#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */

+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk

+#define GPIO_BSRR_BR6_Pos              (22U)

+#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */

+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk

+#define GPIO_BSRR_BR7_Pos              (23U)

+#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */

+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk

+#define GPIO_BSRR_BR8_Pos              (24U)

+#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */

+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk

+#define GPIO_BSRR_BR9_Pos              (25U)

+#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */

+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk

+#define GPIO_BSRR_BR10_Pos             (26U)

+#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */

+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk

+#define GPIO_BSRR_BR11_Pos             (27U)

+#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */

+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk

+#define GPIO_BSRR_BR12_Pos             (28U)

+#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */

+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk

+#define GPIO_BSRR_BR13_Pos             (29U)

+#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */

+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk

+#define GPIO_BSRR_BR14_Pos             (30U)

+#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */

+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk

+#define GPIO_BSRR_BR15_Pos             (31U)

+#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */

+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk

+

+/****************** Bit definition for GPIO_LCKR register *********************/

+#define GPIO_LCKR_LCK0_Pos             (0U)

+#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */

+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk

+#define GPIO_LCKR_LCK1_Pos             (1U)

+#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */

+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk

+#define GPIO_LCKR_LCK2_Pos             (2U)

+#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */

+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk

+#define GPIO_LCKR_LCK3_Pos             (3U)

+#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */

+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk

+#define GPIO_LCKR_LCK4_Pos             (4U)

+#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */

+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk

+#define GPIO_LCKR_LCK5_Pos             (5U)

+#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */

+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk

+#define GPIO_LCKR_LCK6_Pos             (6U)

+#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */

+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk

+#define GPIO_LCKR_LCK7_Pos             (7U)

+#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */

+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk

+#define GPIO_LCKR_LCK8_Pos             (8U)

+#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */

+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk

+#define GPIO_LCKR_LCK9_Pos             (9U)

+#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */

+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk

+#define GPIO_LCKR_LCK10_Pos            (10U)

+#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */

+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk

+#define GPIO_LCKR_LCK11_Pos            (11U)

+#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */

+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk

+#define GPIO_LCKR_LCK12_Pos            (12U)

+#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */

+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk

+#define GPIO_LCKR_LCK13_Pos            (13U)

+#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */

+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk

+#define GPIO_LCKR_LCK14_Pos            (14U)

+#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */

+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk

+#define GPIO_LCKR_LCK15_Pos            (15U)

+#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */

+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk

+#define GPIO_LCKR_LCKK_Pos             (16U)

+#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */

+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk

+

+/****************** Bit definition for GPIO_AFRL register  ********************/

+#define GPIO_AFRL_AFSEL0_Pos           (0U)

+#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */

+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk

+#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */

+#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */

+#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */

+#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */

+#define GPIO_AFRL_AFSEL1_Pos           (4U)

+#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */

+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk

+#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */

+#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */

+#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */

+#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */

+#define GPIO_AFRL_AFSEL2_Pos           (8U)

+#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */

+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk

+#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */

+#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */

+#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */

+#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */

+#define GPIO_AFRL_AFSEL3_Pos           (12U)

+#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */

+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk

+#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */

+#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */

+#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */

+#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */

+#define GPIO_AFRL_AFSEL4_Pos           (16U)

+#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */

+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk

+#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */

+#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */

+#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */

+#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */

+#define GPIO_AFRL_AFSEL5_Pos           (20U)

+#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */

+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk

+#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */

+#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */

+#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */

+#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */

+#define GPIO_AFRL_AFSEL6_Pos           (24U)

+#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */

+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk

+#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */

+#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */

+#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */

+#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */

+#define GPIO_AFRL_AFSEL7_Pos           (28U)

+#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */

+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk

+#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */

+#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */

+#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */

+#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */

+

+/* Legacy defines */

+#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0

+#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1

+#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2

+#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3

+#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4

+#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5

+#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6

+#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7

+

+/****************** Bit definition for GPIO_AFRH register  ********************/

+#define GPIO_AFRH_AFSEL8_Pos           (0U)

+#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */

+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk

+#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */

+#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */

+#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */

+#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */

+#define GPIO_AFRH_AFSEL9_Pos           (4U)

+#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */

+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk

+#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */

+#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */

+#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */

+#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */

+#define GPIO_AFRH_AFSEL10_Pos          (8U)

+#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */

+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk

+#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */

+#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */

+#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */

+#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */

+#define GPIO_AFRH_AFSEL11_Pos          (12U)

+#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */

+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk

+#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */

+#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */

+#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */

+#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */

+#define GPIO_AFRH_AFSEL12_Pos          (16U)

+#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */

+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk

+#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */

+#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */

+#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */

+#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */

+#define GPIO_AFRH_AFSEL13_Pos          (20U)

+#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */

+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk

+#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */

+#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */

+#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */

+#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */

+#define GPIO_AFRH_AFSEL14_Pos          (24U)

+#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */

+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk

+#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */

+#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */

+#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */

+#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */

+#define GPIO_AFRH_AFSEL15_Pos          (28U)

+#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */

+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk

+#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */

+#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */

+#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */

+#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */

+

+/* Legacy defines */

+#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8

+#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9

+#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10

+#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11

+#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12

+#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13

+#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14

+#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15

+

+/******************************************************************************/

+/*                                                                            */

+/*                        HSEM HW Semaphore                                   */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for HSEM_R register  ********************/

+#define HSEM_R_PROCID_Pos         (0U)

+#define HSEM_R_PROCID_Msk         (0xFFUL << HSEM_R_PROCID_Pos)                /*!< 0x000000FF */

+#define HSEM_R_PROCID             HSEM_R_PROCID_Msk                            /*!<Semaphore ProcessID */

+#define HSEM_R_COREID_Pos         (8U)

+#define HSEM_R_COREID_Msk         (0xFFUL << HSEM_R_COREID_Pos)                /*!< 0x0000FF00 */

+#define HSEM_R_COREID             HSEM_R_COREID_Msk                            /*!<Semaphore CoreID.   */

+#define HSEM_R_LOCK_Pos           (31U)

+#define HSEM_R_LOCK_Msk           (0x1UL << HSEM_R_LOCK_Pos)                   /*!< 0x80000000 */

+#define HSEM_R_LOCK               HSEM_R_LOCK_Msk                              /*!<Lock indication.    */

+

+/********************  Bit definition for HSEM_RLR register  ******************/

+#define HSEM_RLR_PROCID_Pos       (0U)

+#define HSEM_RLR_PROCID_Msk       (0xFFUL << HSEM_RLR_PROCID_Pos)              /*!< 0x000000FF */

+#define HSEM_RLR_PROCID           HSEM_RLR_PROCID_Msk                          /*!<Semaphore ProcessID */

+#define HSEM_RLR_COREID_Pos       (8U)

+#define HSEM_RLR_COREID_Msk       (0xFFUL << HSEM_RLR_COREID_Pos)              /*!< 0x0000FF00 */

+#define HSEM_RLR_COREID           HSEM_RLR_COREID_Msk                          /*!<Semaphore CoreID.   */

+#define HSEM_RLR_LOCK_Pos         (31U)

+#define HSEM_RLR_LOCK_Msk         (0x1UL << HSEM_RLR_LOCK_Pos)                 /*!< 0x80000000 */

+#define HSEM_RLR_LOCK             HSEM_RLR_LOCK_Msk                            /*!<Lock indication.    */

+

+/********************  Bit definition for HSEM_C1IER register  *****************/

+#define HSEM_C1IER_ISE0_Pos       (0U)

+#define HSEM_C1IER_ISE0_Msk       (0x1UL << HSEM_C1IER_ISE0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1IER_ISE0           HSEM_C1IER_ISE0_Msk                          /*!<semaphore 0 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE1_Pos       (1U)

+#define HSEM_C1IER_ISE1_Msk       (0x1UL << HSEM_C1IER_ISE1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1IER_ISE1           HSEM_C1IER_ISE1_Msk                          /*!<semaphore 1 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE2_Pos       (2U)

+#define HSEM_C1IER_ISE2_Msk       (0x1UL << HSEM_C1IER_ISE2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1IER_ISE2           HSEM_C1IER_ISE2_Msk                          /*!<semaphore 2 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE3_Pos       (3U)

+#define HSEM_C1IER_ISE3_Msk       (0x1UL << HSEM_C1IER_ISE3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1IER_ISE3           HSEM_C1IER_ISE3_Msk                          /*!<semaphore 3 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE4_Pos       (4U)

+#define HSEM_C1IER_ISE4_Msk       (0x1UL << HSEM_C1IER_ISE4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1IER_ISE4           HSEM_C1IER_ISE4_Msk                          /*!<semaphore 4 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE5_Pos       (5U)

+#define HSEM_C1IER_ISE5_Msk       (0x1UL << HSEM_C1IER_ISE5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1IER_ISE5           HSEM_C1IER_ISE5_Msk                          /*!<semaphore 5 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE6_Pos       (6U)

+#define HSEM_C1IER_ISE6_Msk       (0x1UL << HSEM_C1IER_ISE6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1IER_ISE6           HSEM_C1IER_ISE6_Msk                          /*!<semaphore 6 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE7_Pos       (7U)

+#define HSEM_C1IER_ISE7_Msk       (0x1UL << HSEM_C1IER_ISE7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1IER_ISE7           HSEM_C1IER_ISE7_Msk                          /*!<semaphore 7 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE8_Pos       (8U)

+#define HSEM_C1IER_ISE8_Msk       (0x1UL << HSEM_C1IER_ISE8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1IER_ISE8           HSEM_C1IER_ISE8_Msk                          /*!<semaphore 8 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE9_Pos       (9U)

+#define HSEM_C1IER_ISE9_Msk       (0x1UL << HSEM_C1IER_ISE9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1IER_ISE9           HSEM_C1IER_ISE9_Msk                          /*!<semaphore 9 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE10_Pos      (10U)

+#define HSEM_C1IER_ISE10_Msk      (0x1UL << HSEM_C1IER_ISE10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1IER_ISE10          HSEM_C1IER_ISE10_Msk                         /*!<semaphore 10 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE11_Pos      (11U)

+#define HSEM_C1IER_ISE11_Msk      (0x1UL << HSEM_C1IER_ISE11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1IER_ISE11          HSEM_C1IER_ISE11_Msk                         /*!<semaphore 11 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE12_Pos      (12U)

+#define HSEM_C1IER_ISE12_Msk      (0x1UL << HSEM_C1IER_ISE12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1IER_ISE12          HSEM_C1IER_ISE12_Msk                         /*!<semaphore 12 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE13_Pos      (13U)

+#define HSEM_C1IER_ISE13_Msk      (0x1UL << HSEM_C1IER_ISE13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1IER_ISE13          HSEM_C1IER_ISE13_Msk                         /*!<semaphore 13 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE14_Pos      (14U)

+#define HSEM_C1IER_ISE14_Msk      (0x1UL << HSEM_C1IER_ISE14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1IER_ISE14          HSEM_C1IER_ISE14_Msk                         /*!<semaphore 14 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE15_Pos      (15U)

+#define HSEM_C1IER_ISE15_Msk      (0x1UL << HSEM_C1IER_ISE15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1IER_ISE15          HSEM_C1IER_ISE15_Msk                         /*!<semaphore 15 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE16_Pos      (16U)

+#define HSEM_C1IER_ISE16_Msk      (0x1UL << HSEM_C1IER_ISE16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1IER_ISE16          HSEM_C1IER_ISE16_Msk                         /*!<semaphore 16 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE17_Pos      (17U)

+#define HSEM_C1IER_ISE17_Msk      (0x1UL << HSEM_C1IER_ISE17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1IER_ISE17          HSEM_C1IER_ISE17_Msk                         /*!<semaphore 17 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE18_Pos      (18U)

+#define HSEM_C1IER_ISE18_Msk      (0x1UL << HSEM_C1IER_ISE18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1IER_ISE18          HSEM_C1IER_ISE18_Msk                         /*!<semaphore 18 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE19_Pos      (19U)

+#define HSEM_C1IER_ISE19_Msk      (0x1UL << HSEM_C1IER_ISE19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1IER_ISE19          HSEM_C1IER_ISE19_Msk                         /*!<semaphore 19 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE20_Pos      (20U)

+#define HSEM_C1IER_ISE20_Msk      (0x1UL << HSEM_C1IER_ISE20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1IER_ISE20          HSEM_C1IER_ISE20_Msk                         /*!<semaphore 20 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE21_Pos      (21U)

+#define HSEM_C1IER_ISE21_Msk      (0x1UL << HSEM_C1IER_ISE21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1IER_ISE21          HSEM_C1IER_ISE21_Msk                         /*!<semaphore 21 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE22_Pos      (22U)

+#define HSEM_C1IER_ISE22_Msk      (0x1UL << HSEM_C1IER_ISE22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1IER_ISE22          HSEM_C1IER_ISE22_Msk                         /*!<semaphore 22 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE23_Pos      (23U)

+#define HSEM_C1IER_ISE23_Msk      (0x1UL << HSEM_C1IER_ISE23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1IER_ISE23          HSEM_C1IER_ISE23_Msk                         /*!<semaphore 23 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE24_Pos      (24U)

+#define HSEM_C1IER_ISE24_Msk      (0x1UL << HSEM_C1IER_ISE24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1IER_ISE24          HSEM_C1IER_ISE24_Msk                         /*!<semaphore 24 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE25_Pos      (25U)

+#define HSEM_C1IER_ISE25_Msk      (0x1UL << HSEM_C1IER_ISE25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1IER_ISE25          HSEM_C1IER_ISE25_Msk                         /*!<semaphore 25 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE26_Pos      (26U)

+#define HSEM_C1IER_ISE26_Msk      (0x1UL << HSEM_C1IER_ISE26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1IER_ISE26          HSEM_C1IER_ISE26_Msk                         /*!<semaphore 26 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE27_Pos      (27U)

+#define HSEM_C1IER_ISE27_Msk      (0x1UL << HSEM_C1IER_ISE27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1IER_ISE27          HSEM_C1IER_ISE27_Msk                         /*!<semaphore 27 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE28_Pos      (28U)

+#define HSEM_C1IER_ISE28_Msk      (0x1UL << HSEM_C1IER_ISE28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1IER_ISE28          HSEM_C1IER_ISE28_Msk                         /*!<semaphore 28 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE29_Pos      (29U)

+#define HSEM_C1IER_ISE29_Msk      (0x1UL << HSEM_C1IER_ISE29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1IER_ISE29          HSEM_C1IER_ISE29_Msk                         /*!<semaphore 29 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE30_Pos      (30U)

+#define HSEM_C1IER_ISE30_Msk      (0x1UL << HSEM_C1IER_ISE30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1IER_ISE30          HSEM_C1IER_ISE30_Msk                         /*!<semaphore 30 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE31_Pos      (31U)

+#define HSEM_C1IER_ISE31_Msk      (0x1UL << HSEM_C1IER_ISE31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1IER_ISE31          HSEM_C1IER_ISE31_Msk                         /*!<semaphore 31 interrupt 0 enable bit. */

+

+/********************  Bit definition for HSEM_C1ICR register  *****************/

+#define HSEM_C1ICR_ISC0_Pos       (0U)

+#define HSEM_C1ICR_ISC0_Msk       (0x1UL << HSEM_C1ICR_ISC0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1ICR_ISC0           HSEM_C1ICR_ISC0_Msk                          /*!<semaphore 0 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC1_Pos       (1U)

+#define HSEM_C1ICR_ISC1_Msk       (0x1UL << HSEM_C1ICR_ISC1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1ICR_ISC1           HSEM_C1ICR_ISC1_Msk                          /*!<semaphore 1 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC2_Pos       (2U)

+#define HSEM_C1ICR_ISC2_Msk       (0x1UL << HSEM_C1ICR_ISC2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1ICR_ISC2           HSEM_C1ICR_ISC2_Msk                          /*!<semaphore 2 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC3_Pos       (3U)

+#define HSEM_C1ICR_ISC3_Msk       (0x1UL << HSEM_C1ICR_ISC3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1ICR_ISC3           HSEM_C1ICR_ISC3_Msk                          /*!<semaphore 3 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC4_Pos       (4U)

+#define HSEM_C1ICR_ISC4_Msk       (0x1UL << HSEM_C1ICR_ISC4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1ICR_ISC4           HSEM_C1ICR_ISC4_Msk                          /*!<semaphore 4 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC5_Pos       (5U)

+#define HSEM_C1ICR_ISC5_Msk       (0x1UL << HSEM_C1ICR_ISC5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1ICR_ISC5           HSEM_C1ICR_ISC5_Msk                          /*!<semaphore 5 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC6_Pos       (6U)

+#define HSEM_C1ICR_ISC6_Msk       (0x1UL << HSEM_C1ICR_ISC6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1ICR_ISC6           HSEM_C1ICR_ISC6_Msk                          /*!<semaphore 6 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC7_Pos       (7U)

+#define HSEM_C1ICR_ISC7_Msk       (0x1UL << HSEM_C1ICR_ISC7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1ICR_ISC7           HSEM_C1ICR_ISC7_Msk                          /*!<semaphore 7 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC8_Pos       (8U)

+#define HSEM_C1ICR_ISC8_Msk       (0x1UL << HSEM_C1ICR_ISC8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1ICR_ISC8           HSEM_C1ICR_ISC8_Msk                          /*!<semaphore 8 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC9_Pos       (9U)

+#define HSEM_C1ICR_ISC9_Msk       (0x1UL << HSEM_C1ICR_ISC9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1ICR_ISC9           HSEM_C1ICR_ISC9_Msk                          /*!<semaphore 9 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC10_Pos      (10U)

+#define HSEM_C1ICR_ISC10_Msk      (0x1UL << HSEM_C1ICR_ISC10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1ICR_ISC10          HSEM_C1ICR_ISC10_Msk                         /*!<semaphore 10 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC11_Pos      (11U)

+#define HSEM_C1ICR_ISC11_Msk      (0x1UL << HSEM_C1ICR_ISC11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1ICR_ISC11          HSEM_C1ICR_ISC11_Msk                         /*!<semaphore 11 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC12_Pos      (12U)

+#define HSEM_C1ICR_ISC12_Msk      (0x1UL << HSEM_C1ICR_ISC12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1ICR_ISC12          HSEM_C1ICR_ISC12_Msk                         /*!<semaphore 12 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC13_Pos      (13U)

+#define HSEM_C1ICR_ISC13_Msk      (0x1UL << HSEM_C1ICR_ISC13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1ICR_ISC13          HSEM_C1ICR_ISC13_Msk                         /*!<semaphore 13 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC14_Pos      (14U)

+#define HSEM_C1ICR_ISC14_Msk      (0x1UL << HSEM_C1ICR_ISC14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1ICR_ISC14          HSEM_C1ICR_ISC14_Msk                         /*!<semaphore 14 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC15_Pos      (15U)

+#define HSEM_C1ICR_ISC15_Msk      (0x1UL << HSEM_C1ICR_ISC15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1ICR_ISC15          HSEM_C1ICR_ISC15_Msk                         /*!<semaphore 15 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC16_Pos      (16U)

+#define HSEM_C1ICR_ISC16_Msk      (0x1UL << HSEM_C1ICR_ISC16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1ICR_ISC16          HSEM_C1ICR_ISC16_Msk                         /*!<semaphore 16 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC17_Pos      (17U)

+#define HSEM_C1ICR_ISC17_Msk      (0x1UL << HSEM_C1ICR_ISC17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1ICR_ISC17          HSEM_C1ICR_ISC17_Msk                         /*!<semaphore 17 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC18_Pos      (18U)

+#define HSEM_C1ICR_ISC18_Msk      (0x1UL << HSEM_C1ICR_ISC18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1ICR_ISC18          HSEM_C1ICR_ISC18_Msk                         /*!<semaphore 18 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC19_Pos      (19U)

+#define HSEM_C1ICR_ISC19_Msk      (0x1UL << HSEM_C1ICR_ISC19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1ICR_ISC19          HSEM_C1ICR_ISC19_Msk                         /*!<semaphore 19 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC20_Pos      (20U)

+#define HSEM_C1ICR_ISC20_Msk      (0x1UL << HSEM_C1ICR_ISC20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1ICR_ISC20          HSEM_C1ICR_ISC20_Msk                         /*!<semaphore 20 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC21_Pos      (21U)

+#define HSEM_C1ICR_ISC21_Msk      (0x1UL << HSEM_C1ICR_ISC21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1ICR_ISC21          HSEM_C1ICR_ISC21_Msk                         /*!<semaphore 21 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC22_Pos      (22U)

+#define HSEM_C1ICR_ISC22_Msk      (0x1UL << HSEM_C1ICR_ISC22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1ICR_ISC22          HSEM_C1ICR_ISC22_Msk                         /*!<semaphore 22 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC23_Pos      (23U)

+#define HSEM_C1ICR_ISC23_Msk      (0x1UL << HSEM_C1ICR_ISC23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1ICR_ISC23          HSEM_C1ICR_ISC23_Msk                         /*!<semaphore 23 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC24_Pos      (24U)

+#define HSEM_C1ICR_ISC24_Msk      (0x1UL << HSEM_C1ICR_ISC24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1ICR_ISC24          HSEM_C1ICR_ISC24_Msk                         /*!<semaphore 24 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC25_Pos      (25U)

+#define HSEM_C1ICR_ISC25_Msk      (0x1UL << HSEM_C1ICR_ISC25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1ICR_ISC25          HSEM_C1ICR_ISC25_Msk                         /*!<semaphore 25 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC26_Pos      (26U)

+#define HSEM_C1ICR_ISC26_Msk      (0x1UL << HSEM_C1ICR_ISC26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1ICR_ISC26          HSEM_C1ICR_ISC26_Msk                         /*!<semaphore 26 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC27_Pos      (27U)

+#define HSEM_C1ICR_ISC27_Msk      (0x1UL << HSEM_C1ICR_ISC27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1ICR_ISC27          HSEM_C1ICR_ISC27_Msk                         /*!<semaphore 27 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC28_Pos      (28U)

+#define HSEM_C1ICR_ISC28_Msk      (0x1UL << HSEM_C1ICR_ISC28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1ICR_ISC28          HSEM_C1ICR_ISC28_Msk                         /*!<semaphore 28 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC29_Pos      (29U)

+#define HSEM_C1ICR_ISC29_Msk      (0x1UL << HSEM_C1ICR_ISC29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1ICR_ISC29          HSEM_C1ICR_ISC29_Msk                         /*!<semaphore 29 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC30_Pos      (30U)

+#define HSEM_C1ICR_ISC30_Msk      (0x1UL << HSEM_C1ICR_ISC30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1ICR_ISC30          HSEM_C1ICR_ISC30_Msk                         /*!<semaphore 30 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC31_Pos      (31U)

+#define HSEM_C1ICR_ISC31_Msk      (0x1UL << HSEM_C1ICR_ISC31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1ICR_ISC31          HSEM_C1ICR_ISC31_Msk                         /*!<semaphore 31 interrupt 0 clear bit. */

+

+/********************  Bit definition for HSEM_C1ISR register  *****************/

+#define HSEM_C1ISR_ISF0_Pos       (0U)

+#define HSEM_C1ISR_ISF0_Msk       (0x1UL << HSEM_C1ISR_ISF0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1ISR_ISF0           HSEM_C1ISR_ISF0_Msk                          /*!<semaphore 0 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF1_Pos       (1U)

+#define HSEM_C1ISR_ISF1_Msk       (0x1UL << HSEM_C1ISR_ISF1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1ISR_ISF1           HSEM_C1ISR_ISF1_Msk                          /*!<semaphore 1 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF2_Pos       (2U)

+#define HSEM_C1ISR_ISF2_Msk       (0x1UL << HSEM_C1ISR_ISF2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1ISR_ISF2           HSEM_C1ISR_ISF2_Msk                          /*!<semaphore 2 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF3_Pos       (3U)

+#define HSEM_C1ISR_ISF3_Msk       (0x1UL << HSEM_C1ISR_ISF3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1ISR_ISF3           HSEM_C1ISR_ISF3_Msk                          /*!<semaphore 3 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF4_Pos       (4U)

+#define HSEM_C1ISR_ISF4_Msk       (0x1UL << HSEM_C1ISR_ISF4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1ISR_ISF4           HSEM_C1ISR_ISF4_Msk                          /*!<semaphore 4 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF5_Pos       (5U)

+#define HSEM_C1ISR_ISF5_Msk       (0x1UL << HSEM_C1ISR_ISF5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1ISR_ISF5           HSEM_C1ISR_ISF5_Msk                          /*!<semaphore 5 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF6_Pos       (6U)

+#define HSEM_C1ISR_ISF6_Msk       (0x1UL << HSEM_C1ISR_ISF6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1ISR_ISF6           HSEM_C1ISR_ISF6_Msk                          /*!<semaphore 6 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF7_Pos       (7U)

+#define HSEM_C1ISR_ISF7_Msk       (0x1UL << HSEM_C1ISR_ISF7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1ISR_ISF7           HSEM_C1ISR_ISF7_Msk                          /*!<semaphore 7 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF8_Pos       (8U)

+#define HSEM_C1ISR_ISF8_Msk       (0x1UL << HSEM_C1ISR_ISF8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1ISR_ISF8           HSEM_C1ISR_ISF8_Msk                          /*!<semaphore 8 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF9_Pos       (9U)

+#define HSEM_C1ISR_ISF9_Msk       (0x1UL << HSEM_C1ISR_ISF9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1ISR_ISF9           HSEM_C1ISR_ISF9_Msk                          /*!<semaphore 9 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF10_Pos      (10U)

+#define HSEM_C1ISR_ISF10_Msk      (0x1UL << HSEM_C1ISR_ISF10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1ISR_ISF10          HSEM_C1ISR_ISF10_Msk                         /*!<semaphore 10 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF11_Pos      (11U)

+#define HSEM_C1ISR_ISF11_Msk      (0x1UL << HSEM_C1ISR_ISF11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1ISR_ISF11          HSEM_C1ISR_ISF11_Msk                         /*!<semaphore 11 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF12_Pos      (12U)

+#define HSEM_C1ISR_ISF12_Msk      (0x1UL << HSEM_C1ISR_ISF12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1ISR_ISF12          HSEM_C1ISR_ISF12_Msk                         /*!<semaphore 12 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF13_Pos      (13U)

+#define HSEM_C1ISR_ISF13_Msk      (0x1UL << HSEM_C1ISR_ISF13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1ISR_ISF13          HSEM_C1ISR_ISF13_Msk                         /*!<semaphore 13 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF14_Pos      (14U)

+#define HSEM_C1ISR_ISF14_Msk      (0x1UL << HSEM_C1ISR_ISF14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1ISR_ISF14          HSEM_C1ISR_ISF14_Msk                         /*!<semaphore 14 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF15_Pos      (15U)

+#define HSEM_C1ISR_ISF15_Msk      (0x1UL << HSEM_C1ISR_ISF15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1ISR_ISF15          HSEM_C1ISR_ISF15_Msk                         /*!<semaphore 15 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF16_Pos      (16U)

+#define HSEM_C1ISR_ISF16_Msk      (0x1UL << HSEM_C1ISR_ISF16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1ISR_ISF16          HSEM_C1ISR_ISF16_Msk                         /*!<semaphore 16 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF17_Pos      (17U)

+#define HSEM_C1ISR_ISF17_Msk      (0x1UL << HSEM_C1ISR_ISF17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1ISR_ISF17          HSEM_C1ISR_ISF17_Msk                         /*!<semaphore 17 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF18_Pos      (18U)

+#define HSEM_C1ISR_ISF18_Msk      (0x1UL << HSEM_C1ISR_ISF18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1ISR_ISF18          HSEM_C1ISR_ISF18_Msk                         /*!<semaphore 18 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF19_Pos      (19U)

+#define HSEM_C1ISR_ISF19_Msk      (0x1UL << HSEM_C1ISR_ISF19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1ISR_ISF19          HSEM_C1ISR_ISF19_Msk                         /*!<semaphore 19 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF20_Pos      (20U)

+#define HSEM_C1ISR_ISF20_Msk      (0x1UL << HSEM_C1ISR_ISF20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1ISR_ISF20          HSEM_C1ISR_ISF20_Msk                         /*!<semaphore 20 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF21_Pos      (21U)

+#define HSEM_C1ISR_ISF21_Msk      (0x1UL << HSEM_C1ISR_ISF21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1ISR_ISF21          HSEM_C1ISR_ISF21_Msk                         /*!<semaphore 21 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF22_Pos      (22U)

+#define HSEM_C1ISR_ISF22_Msk      (0x1UL << HSEM_C1ISR_ISF22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1ISR_ISF22          HSEM_C1ISR_ISF22_Msk                         /*!<semaphore 22 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF23_Pos      (23U)

+#define HSEM_C1ISR_ISF23_Msk      (0x1UL << HSEM_C1ISR_ISF23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1ISR_ISF23          HSEM_C1ISR_ISF23_Msk                         /*!<semaphore 23 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF24_Pos      (24U)

+#define HSEM_C1ISR_ISF24_Msk      (0x1UL << HSEM_C1ISR_ISF24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1ISR_ISF24          HSEM_C1ISR_ISF24_Msk                         /*!<semaphore 24 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF25_Pos      (25U)

+#define HSEM_C1ISR_ISF25_Msk      (0x1UL << HSEM_C1ISR_ISF25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1ISR_ISF25          HSEM_C1ISR_ISF25_Msk                         /*!<semaphore 25 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF26_Pos      (26U)

+#define HSEM_C1ISR_ISF26_Msk      (0x1UL << HSEM_C1ISR_ISF26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1ISR_ISF26          HSEM_C1ISR_ISF26_Msk                         /*!<semaphore 26 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF27_Pos      (27U)

+#define HSEM_C1ISR_ISF27_Msk      (0x1UL << HSEM_C1ISR_ISF27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1ISR_ISF27          HSEM_C1ISR_ISF27_Msk                         /*!<semaphore 27 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF28_Pos      (28U)

+#define HSEM_C1ISR_ISF28_Msk      (0x1UL << HSEM_C1ISR_ISF28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1ISR_ISF28          HSEM_C1ISR_ISF28_Msk                         /*!<semaphore 28 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF29_Pos      (29U)

+#define HSEM_C1ISR_ISF29_Msk      (0x1UL << HSEM_C1ISR_ISF29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1ISR_ISF29          HSEM_C1ISR_ISF29_Msk                         /*!<semaphore 29 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF30_Pos      (30U)

+#define HSEM_C1ISR_ISF30_Msk      (0x1UL << HSEM_C1ISR_ISF30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1ISR_ISF30          HSEM_C1ISR_ISF30_Msk                         /*!<semaphore 30 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF31_Pos      (31U)

+#define HSEM_C1ISR_ISF31_Msk      (0x1UL << HSEM_C1ISR_ISF31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1ISR_ISF31          HSEM_C1ISR_ISF31_Msk                         /*!<semaphore 31 interrupt 0 status bit. */

+

+/********************  Bit definition for HSEM_C1MISR register  *****************/

+#define HSEM_C1MISR_MISF0_Pos     (0U)

+#define HSEM_C1MISR_MISF0_Msk     (0x1UL << HSEM_C1MISR_MISF0_Pos)             /*!< 0x00000001 */

+#define HSEM_C1MISR_MISF0         HSEM_C1MISR_MISF0_Msk                        /*!<semaphore 0 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF1_Pos     (1U)

+#define HSEM_C1MISR_MISF1_Msk     (0x1UL << HSEM_C1MISR_MISF1_Pos)             /*!< 0x00000002 */

+#define HSEM_C1MISR_MISF1         HSEM_C1MISR_MISF1_Msk                        /*!<semaphore 1 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF2_Pos     (2U)

+#define HSEM_C1MISR_MISF2_Msk     (0x1UL << HSEM_C1MISR_MISF2_Pos)             /*!< 0x00000004 */

+#define HSEM_C1MISR_MISF2         HSEM_C1MISR_MISF2_Msk                        /*!<semaphore 2 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF3_Pos     (3U)

+#define HSEM_C1MISR_MISF3_Msk     (0x1UL << HSEM_C1MISR_MISF3_Pos)             /*!< 0x00000008 */

+#define HSEM_C1MISR_MISF3         HSEM_C1MISR_MISF3_Msk                        /*!<semaphore 3 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF4_Pos     (4U)

+#define HSEM_C1MISR_MISF4_Msk     (0x1UL << HSEM_C1MISR_MISF4_Pos)             /*!< 0x00000010 */

+#define HSEM_C1MISR_MISF4         HSEM_C1MISR_MISF4_Msk                        /*!<semaphore 4 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF5_Pos     (5U)

+#define HSEM_C1MISR_MISF5_Msk     (0x1UL << HSEM_C1MISR_MISF5_Pos)             /*!< 0x00000020 */

+#define HSEM_C1MISR_MISF5         HSEM_C1MISR_MISF5_Msk                        /*!<semaphore 5 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF6_Pos     (6U)

+#define HSEM_C1MISR_MISF6_Msk     (0x1UL << HSEM_C1MISR_MISF6_Pos)             /*!< 0x00000040 */

+#define HSEM_C1MISR_MISF6         HSEM_C1MISR_MISF6_Msk                        /*!<semaphore 6 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF7_Pos     (7U)

+#define HSEM_C1MISR_MISF7_Msk     (0x1UL << HSEM_C1MISR_MISF7_Pos)             /*!< 0x00000080 */

+#define HSEM_C1MISR_MISF7         HSEM_C1MISR_MISF7_Msk                        /*!<semaphore 7 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF8_Pos     (8U)

+#define HSEM_C1MISR_MISF8_Msk     (0x1UL << HSEM_C1MISR_MISF8_Pos)             /*!< 0x00000100 */

+#define HSEM_C1MISR_MISF8         HSEM_C1MISR_MISF8_Msk                        /*!<semaphore 8 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF9_Pos     (9U)

+#define HSEM_C1MISR_MISF9_Msk     (0x1UL << HSEM_C1MISR_MISF9_Pos)             /*!< 0x00000200 */

+#define HSEM_C1MISR_MISF9         HSEM_C1MISR_MISF9_Msk                        /*!<semaphore 9 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF10_Pos    (10U)

+#define HSEM_C1MISR_MISF10_Msk    (0x1UL << HSEM_C1MISR_MISF10_Pos)            /*!< 0x00000400 */

+#define HSEM_C1MISR_MISF10        HSEM_C1MISR_MISF10_Msk                       /*!<semaphore 10 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF11_Pos    (11U)

+#define HSEM_C1MISR_MISF11_Msk    (0x1UL << HSEM_C1MISR_MISF11_Pos)            /*!< 0x00000800 */

+#define HSEM_C1MISR_MISF11        HSEM_C1MISR_MISF11_Msk                       /*!<semaphore 11 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF12_Pos    (12U)

+#define HSEM_C1MISR_MISF12_Msk    (0x1UL << HSEM_C1MISR_MISF12_Pos)            /*!< 0x00001000 */

+#define HSEM_C1MISR_MISF12        HSEM_C1MISR_MISF12_Msk                       /*!<semaphore 12 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF13_Pos    (13U)

+#define HSEM_C1MISR_MISF13_Msk    (0x1UL << HSEM_C1MISR_MISF13_Pos)            /*!< 0x00002000 */

+#define HSEM_C1MISR_MISF13        HSEM_C1MISR_MISF13_Msk                       /*!<semaphore 13 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF14_Pos    (14U)

+#define HSEM_C1MISR_MISF14_Msk    (0x1UL << HSEM_C1MISR_MISF14_Pos)            /*!< 0x00004000 */

+#define HSEM_C1MISR_MISF14        HSEM_C1MISR_MISF14_Msk                       /*!<semaphore 14 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF15_Pos    (15U)

+#define HSEM_C1MISR_MISF15_Msk    (0x1UL << HSEM_C1MISR_MISF15_Pos)            /*!< 0x00008000 */

+#define HSEM_C1MISR_MISF15        HSEM_C1MISR_MISF15_Msk                       /*!<semaphore 15 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF16_Pos    (16U)

+#define HSEM_C1MISR_MISF16_Msk    (0x1UL << HSEM_C1MISR_MISF16_Pos)            /*!< 0x00010000 */

+#define HSEM_C1MISR_MISF16        HSEM_C1MISR_MISF16_Msk                       /*!<semaphore 16 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF17_Pos    (17U)

+#define HSEM_C1MISR_MISF17_Msk    (0x1UL << HSEM_C1MISR_MISF17_Pos)            /*!< 0x00020000 */

+#define HSEM_C1MISR_MISF17        HSEM_C1MISR_MISF17_Msk                       /*!<semaphore 17 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF18_Pos    (18U)

+#define HSEM_C1MISR_MISF18_Msk    (0x1UL << HSEM_C1MISR_MISF18_Pos)            /*!< 0x00040000 */

+#define HSEM_C1MISR_MISF18        HSEM_C1MISR_MISF18_Msk                       /*!<semaphore 18 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF19_Pos    (19U)

+#define HSEM_C1MISR_MISF19_Msk    (0x1UL << HSEM_C1MISR_MISF19_Pos)            /*!< 0x00080000 */

+#define HSEM_C1MISR_MISF19        HSEM_C1MISR_MISF19_Msk                       /*!<semaphore 19 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF20_Pos    (20U)

+#define HSEM_C1MISR_MISF20_Msk    (0x1UL << HSEM_C1MISR_MISF20_Pos)            /*!< 0x00100000 */

+#define HSEM_C1MISR_MISF20        HSEM_C1MISR_MISF20_Msk                       /*!<semaphore 20 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF21_Pos    (21U)

+#define HSEM_C1MISR_MISF21_Msk    (0x1UL << HSEM_C1MISR_MISF21_Pos)            /*!< 0x00200000 */

+#define HSEM_C1MISR_MISF21        HSEM_C1MISR_MISF21_Msk                       /*!<semaphore 21 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF22_Pos    (22U)

+#define HSEM_C1MISR_MISF22_Msk    (0x1UL << HSEM_C1MISR_MISF22_Pos)            /*!< 0x00400000 */

+#define HSEM_C1MISR_MISF22        HSEM_C1MISR_MISF22_Msk                       /*!<semaphore 22 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF23_Pos    (23U)

+#define HSEM_C1MISR_MISF23_Msk    (0x1UL << HSEM_C1MISR_MISF23_Pos)            /*!< 0x00800000 */

+#define HSEM_C1MISR_MISF23        HSEM_C1MISR_MISF23_Msk                       /*!<semaphore 23 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF24_Pos    (24U)

+#define HSEM_C1MISR_MISF24_Msk    (0x1UL << HSEM_C1MISR_MISF24_Pos)            /*!< 0x01000000 */

+#define HSEM_C1MISR_MISF24        HSEM_C1MISR_MISF24_Msk                       /*!<semaphore 24 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF25_Pos    (25U)

+#define HSEM_C1MISR_MISF25_Msk    (0x1UL << HSEM_C1MISR_MISF25_Pos)            /*!< 0x02000000 */

+#define HSEM_C1MISR_MISF25        HSEM_C1MISR_MISF25_Msk                       /*!<semaphore 25 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF26_Pos    (26U)

+#define HSEM_C1MISR_MISF26_Msk    (0x1UL << HSEM_C1MISR_MISF26_Pos)            /*!< 0x04000000 */

+#define HSEM_C1MISR_MISF26        HSEM_C1MISR_MISF26_Msk                       /*!<semaphore 26 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF27_Pos    (27U)

+#define HSEM_C1MISR_MISF27_Msk    (0x1UL << HSEM_C1MISR_MISF27_Pos)            /*!< 0x08000000 */

+#define HSEM_C1MISR_MISF27        HSEM_C1MISR_MISF27_Msk                       /*!<semaphore 27 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF28_Pos    (28U)

+#define HSEM_C1MISR_MISF28_Msk    (0x1UL << HSEM_C1MISR_MISF28_Pos)            /*!< 0x10000000 */

+#define HSEM_C1MISR_MISF28        HSEM_C1MISR_MISF28_Msk                       /*!<semaphore 28 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF29_Pos    (29U)

+#define HSEM_C1MISR_MISF29_Msk    (0x1UL << HSEM_C1MISR_MISF29_Pos)            /*!< 0x20000000 */

+#define HSEM_C1MISR_MISF29        HSEM_C1MISR_MISF29_Msk                       /*!<semaphore 29 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF30_Pos    (30U)

+#define HSEM_C1MISR_MISF30_Msk    (0x1UL << HSEM_C1MISR_MISF30_Pos)            /*!< 0x40000000 */

+#define HSEM_C1MISR_MISF30        HSEM_C1MISR_MISF30_Msk                       /*!<semaphore 30 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF31_Pos    (31U)

+#define HSEM_C1MISR_MISF31_Msk    (0x1UL << HSEM_C1MISR_MISF31_Pos)            /*!< 0x80000000 */

+#define HSEM_C1MISR_MISF31        HSEM_C1MISR_MISF31_Msk                       /*!<semaphore 31 interrupt 0 masked status bit. */

+

+/********************  Bit definition for HSEM_CR register  *****************/

+#define HSEM_CR_COREID_Pos        (8U)

+#define HSEM_CR_COREID_Msk        (0xFFUL << HSEM_CR_COREID_Pos)               /*!< 0x0000FF00 */

+#define HSEM_CR_COREID            HSEM_CR_COREID_Msk                           /*!<CoreID of semaphores to be cleared. */

+#define HSEM_CR_KEY_Pos           (16U)

+#define HSEM_CR_KEY_Msk           (0xFFFFUL << HSEM_CR_KEY_Pos)                /*!< 0xFFFF0000 */

+#define HSEM_CR_KEY               HSEM_CR_KEY_Msk                              /*!<semaphores clear key. */

+

+/********************  Bit definition for HSEM_KEYR register  *****************/

+#define HSEM_KEYR_KEY_Pos         (16U)

+#define HSEM_KEYR_KEY_Msk         (0xFFFFUL << HSEM_KEYR_KEY_Pos)              /*!< 0xFFFF0000 */

+#define HSEM_KEYR_KEY             HSEM_KEYR_KEY_Msk                            /*!<semaphores clear key. */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    HASH                                    */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bits definition for HASH_CR register  ********************/

+#define HASH_CR_INIT_Pos          (2U)

+#define HASH_CR_INIT_Msk          (0x1UL << HASH_CR_INIT_Pos)                  /*!< 0x00000004 */

+#define HASH_CR_INIT              HASH_CR_INIT_Msk

+#define HASH_CR_DMAE_Pos          (3U)

+#define HASH_CR_DMAE_Msk          (0x1UL << HASH_CR_DMAE_Pos)                  /*!< 0x00000008 */

+#define HASH_CR_DMAE              HASH_CR_DMAE_Msk

+#define HASH_CR_DATATYPE_Pos      (4U)

+#define HASH_CR_DATATYPE_Msk      (0x3UL << HASH_CR_DATATYPE_Pos)              /*!< 0x00000030 */

+#define HASH_CR_DATATYPE          HASH_CR_DATATYPE_Msk

+#define HASH_CR_DATATYPE_0        (0x1UL << HASH_CR_DATATYPE_Pos)               /*!< 0x00000010 */

+#define HASH_CR_DATATYPE_1        (0x2UL << HASH_CR_DATATYPE_Pos)               /*!< 0x00000020 */

+#define HASH_CR_MODE_Pos          (6U)

+#define HASH_CR_MODE_Msk          (0x1UL << HASH_CR_MODE_Pos)                  /*!< 0x00000040 */

+#define HASH_CR_MODE              HASH_CR_MODE_Msk

+#define HASH_CR_ALGO_Pos          (7U)

+#define HASH_CR_ALGO_Msk          (0x801UL << HASH_CR_ALGO_Pos)                /*!< 0x00040080 */

+#define HASH_CR_ALGO              HASH_CR_ALGO_Msk

+#define HASH_CR_ALGO_0            (0x001UL << HASH_CR_ALGO_Pos)                 /*!< 0x00000080 */

+#define HASH_CR_ALGO_1            (0x800UL << HASH_CR_ALGO_Pos)                 /*!< 0x00040000 */

+#define HASH_CR_NBW_Pos           (8U)

+#define HASH_CR_NBW_Msk           (0xFUL << HASH_CR_NBW_Pos)                   /*!< 0x00000F00 */

+#define HASH_CR_NBW               HASH_CR_NBW_Msk

+#define HASH_CR_NBW_0             (0x1UL << HASH_CR_NBW_Pos)                    /*!< 0x00000100 */

+#define HASH_CR_NBW_1             (0x2UL << HASH_CR_NBW_Pos)                    /*!< 0x00000200 */

+#define HASH_CR_NBW_2             (0x4UL << HASH_CR_NBW_Pos)                    /*!< 0x00000400 */

+#define HASH_CR_NBW_3             (0x8UL << HASH_CR_NBW_Pos)                    /*!< 0x00000800 */

+#define HASH_CR_DINNE_Pos         (12U)

+#define HASH_CR_DINNE_Msk         (0x1UL << HASH_CR_DINNE_Pos)                 /*!< 0x00001000 */

+#define HASH_CR_DINNE             HASH_CR_DINNE_Msk

+#define HASH_CR_MDMAT_Pos         (13U)

+#define HASH_CR_MDMAT_Msk         (0x1UL << HASH_CR_MDMAT_Pos)                 /*!< 0x00002000 */

+#define HASH_CR_MDMAT             HASH_CR_MDMAT_Msk

+#define HASH_CR_LKEY_Pos          (16U)

+#define HASH_CR_LKEY_Msk          (0x1UL << HASH_CR_LKEY_Pos)                  /*!< 0x00010000 */

+#define HASH_CR_LKEY              HASH_CR_LKEY_Msk

+

+/******************  Bits definition for HASH_STR register  *******************/

+#define HASH_STR_NBLW_Pos         (0U)

+#define HASH_STR_NBLW_Msk         (0x1FUL << HASH_STR_NBLW_Pos)                /*!< 0x0000001F */

+#define HASH_STR_NBLW             HASH_STR_NBLW_Msk

+#define HASH_STR_NBLW_0           (0x01UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000001 */

+#define HASH_STR_NBLW_1           (0x02UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000002 */

+#define HASH_STR_NBLW_2           (0x04UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000004 */

+#define HASH_STR_NBLW_3           (0x08UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000008 */

+#define HASH_STR_NBLW_4           (0x10UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000010 */

+#define HASH_STR_DCAL_Pos         (8U)

+#define HASH_STR_DCAL_Msk         (0x1UL << HASH_STR_DCAL_Pos)                 /*!< 0x00000100 */

+#define HASH_STR_DCAL             HASH_STR_DCAL_Msk

+

+/******************  Bits definition for HASH_IMR register  *******************/

+#define HASH_IMR_DINIE_Pos        (0U)

+#define HASH_IMR_DINIE_Msk        (0x1UL << HASH_IMR_DINIE_Pos)                /*!< 0x00000001 */

+#define HASH_IMR_DINIE            HASH_IMR_DINIE_Msk

+#define HASH_IMR_DCIE_Pos         (1U)

+#define HASH_IMR_DCIE_Msk         (0x1UL << HASH_IMR_DCIE_Pos)                 /*!< 0x00000002 */

+#define HASH_IMR_DCIE             HASH_IMR_DCIE_Msk

+

+/******************  Bits definition for HASH_SR register  ********************/

+#define HASH_SR_DINIS_Pos         (0U)

+#define HASH_SR_DINIS_Msk         (0x1UL << HASH_SR_DINIS_Pos)                 /*!< 0x00000001 */

+#define HASH_SR_DINIS             HASH_SR_DINIS_Msk

+#define HASH_SR_DCIS_Pos          (1U)

+#define HASH_SR_DCIS_Msk          (0x1UL << HASH_SR_DCIS_Pos)                  /*!< 0x00000002 */

+#define HASH_SR_DCIS              HASH_SR_DCIS_Msk

+#define HASH_SR_DMAS_Pos          (2U)

+#define HASH_SR_DMAS_Msk          (0x1UL << HASH_SR_DMAS_Pos)                  /*!< 0x00000004 */

+#define HASH_SR_DMAS              HASH_SR_DMAS_Msk

+#define HASH_SR_BUSY_Pos          (3U)

+#define HASH_SR_BUSY_Msk          (0x1UL << HASH_SR_BUSY_Pos)                  /*!< 0x00000008 */

+#define HASH_SR_BUSY              HASH_SR_BUSY_Msk

+/******************************************************************************/

+/*                                                                            */

+/*                      Inter-integrated Circuit Interface (I2C)              */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for I2C_CR1 register  *******************/

+#define I2C_CR1_PE_Pos               (0U)

+#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */

+#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */

+#define I2C_CR1_TXIE_Pos             (1U)

+#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */

+#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */

+#define I2C_CR1_RXIE_Pos             (2U)

+#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */

+#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */

+#define I2C_CR1_ADDRIE_Pos           (3U)

+#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */

+#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */

+#define I2C_CR1_NACKIE_Pos           (4U)

+#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */

+#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */

+#define I2C_CR1_STOPIE_Pos           (5U)

+#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */

+#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */

+#define I2C_CR1_TCIE_Pos             (6U)

+#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */

+#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */

+#define I2C_CR1_ERRIE_Pos            (7U)

+#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */

+#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */

+#define I2C_CR1_DNF_Pos              (8U)

+#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */

+#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */

+#define I2C_CR1_ANFOFF_Pos           (12U)

+#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */

+#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */

+#define I2C_CR1_TXDMAEN_Pos          (14U)

+#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */

+#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */

+#define I2C_CR1_RXDMAEN_Pos          (15U)

+#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */

+#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */

+#define I2C_CR1_SBC_Pos              (16U)

+#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */

+#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */

+#define I2C_CR1_NOSTRETCH_Pos        (17U)

+#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */

+#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */

+#define I2C_CR1_WUPEN_Pos            (18U)

+#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */

+#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */

+#define I2C_CR1_GCEN_Pos             (19U)

+#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */

+#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */

+#define I2C_CR1_SMBHEN_Pos           (20U)

+#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */

+#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */

+#define I2C_CR1_SMBDEN_Pos           (21U)

+#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */

+#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */

+#define I2C_CR1_ALERTEN_Pos          (22U)

+#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */

+#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */

+#define I2C_CR1_PECEN_Pos            (23U)

+#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */

+#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */

+

+/******************  Bit definition for I2C_CR2 register  ********************/

+#define I2C_CR2_SADD_Pos             (0U)

+#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */

+#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */

+#define I2C_CR2_RD_WRN_Pos           (10U)

+#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */

+#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */

+#define I2C_CR2_ADD10_Pos            (11U)

+#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */

+#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */

+#define I2C_CR2_HEAD10R_Pos          (12U)

+#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */

+#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */

+#define I2C_CR2_START_Pos            (13U)

+#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */

+#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */

+#define I2C_CR2_STOP_Pos             (14U)

+#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */

+#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */

+#define I2C_CR2_NACK_Pos             (15U)

+#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */

+#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */

+#define I2C_CR2_NBYTES_Pos           (16U)

+#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */

+#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */

+#define I2C_CR2_RELOAD_Pos           (24U)

+#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */

+#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */

+#define I2C_CR2_AUTOEND_Pos          (25U)

+#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */

+#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */

+#define I2C_CR2_PECBYTE_Pos          (26U)

+#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */

+#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */

+

+/*******************  Bit definition for I2C_OAR1 register  ******************/

+#define I2C_OAR1_OA1_Pos             (0U)

+#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */

+#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */

+#define I2C_OAR1_OA1MODE_Pos         (10U)

+#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */

+#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */

+#define I2C_OAR1_OA1EN_Pos           (15U)

+#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */

+#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */

+

+/*******************  Bit definition for I2C_OAR2 register  ******************/

+#define I2C_OAR2_OA2_Pos             (1U)

+#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */

+#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */

+#define I2C_OAR2_OA2MSK_Pos          (8U)

+#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */

+#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */

+#define I2C_OAR2_OA2NOMASK           0x00000000UL                              /*!< No mask */

+#define I2C_OAR2_OA2MASK01_Pos       (8U)

+#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */

+#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared */

+#define I2C_OAR2_OA2MASK02_Pos       (9U)

+#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */

+#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */

+#define I2C_OAR2_OA2MASK03_Pos       (8U)

+#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */

+#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */

+#define I2C_OAR2_OA2MASK04_Pos       (10U)

+#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */

+#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */

+#define I2C_OAR2_OA2MASK05_Pos       (8U)

+#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */

+#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */

+#define I2C_OAR2_OA2MASK06_Pos       (9U)

+#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */

+#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared */

+#define I2C_OAR2_OA2MASK07_Pos       (8U)

+#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */

+#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done */

+#define I2C_OAR2_OA2EN_Pos           (15U)

+#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */

+#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */

+

+/*******************  Bit definition for I2C_TIMINGR register *******************/

+#define I2C_TIMINGR_SCLL_Pos         (0U)

+#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */

+#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */

+#define I2C_TIMINGR_SCLH_Pos         (8U)

+#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */

+#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */

+#define I2C_TIMINGR_SDADEL_Pos       (16U)

+#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */

+#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */

+#define I2C_TIMINGR_SCLDEL_Pos       (20U)

+#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */

+#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */

+#define I2C_TIMINGR_PRESC_Pos        (28U)

+#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */

+#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */

+

+/******************* Bit definition for I2C_TIMEOUTR register *******************/

+#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)

+#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */

+#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */

+#define I2C_TIMEOUTR_TIDLE_Pos       (12U)

+#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */

+#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */

+#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)

+#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */

+#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */

+#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)

+#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */

+#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/

+#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)

+#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */

+#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */

+

+/******************  Bit definition for I2C_ISR register  *********************/

+#define I2C_ISR_TXE_Pos              (0U)

+#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */

+#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */

+#define I2C_ISR_TXIS_Pos             (1U)

+#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */

+#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */

+#define I2C_ISR_RXNE_Pos             (2U)

+#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */

+#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */

+#define I2C_ISR_ADDR_Pos             (3U)

+#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */

+#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/

+#define I2C_ISR_NACKF_Pos            (4U)

+#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */

+#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */

+#define I2C_ISR_STOPF_Pos            (5U)

+#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */

+#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */

+#define I2C_ISR_TC_Pos               (6U)

+#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */

+#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */

+#define I2C_ISR_TCR_Pos              (7U)

+#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */

+#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */

+#define I2C_ISR_BERR_Pos             (8U)

+#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */

+#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */

+#define I2C_ISR_ARLO_Pos             (9U)

+#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */

+#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */

+#define I2C_ISR_OVR_Pos              (10U)

+#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */

+#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */

+#define I2C_ISR_PECERR_Pos           (11U)

+#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */

+#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */

+#define I2C_ISR_TIMEOUT_Pos          (12U)

+#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */

+#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */

+#define I2C_ISR_ALERT_Pos            (13U)

+#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */

+#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */

+#define I2C_ISR_BUSY_Pos             (15U)

+#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */

+#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */

+#define I2C_ISR_DIR_Pos              (16U)

+#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */

+#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */

+#define I2C_ISR_ADDCODE_Pos          (17U)

+#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */

+#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */

+

+/******************  Bit definition for I2C_ICR register  *********************/

+#define I2C_ICR_ADDRCF_Pos           (3U)

+#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */

+#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */

+#define I2C_ICR_NACKCF_Pos           (4U)

+#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */

+#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */

+#define I2C_ICR_STOPCF_Pos           (5U)

+#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */

+#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */

+#define I2C_ICR_BERRCF_Pos           (8U)

+#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */

+#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */

+#define I2C_ICR_ARLOCF_Pos           (9U)

+#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */

+#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */

+#define I2C_ICR_OVRCF_Pos            (10U)

+#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */

+#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */

+#define I2C_ICR_PECCF_Pos            (11U)

+#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */

+#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */

+#define I2C_ICR_TIMOUTCF_Pos         (12U)

+#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */

+#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */

+#define I2C_ICR_ALERTCF_Pos          (13U)

+#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */

+#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */

+

+/******************  Bit definition for I2C_PECR register  *********************/

+#define I2C_PECR_PEC_Pos             (0U)

+#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */

+#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */

+

+/******************  Bit definition for I2C_RXDR register  *********************/

+#define I2C_RXDR_RXDATA_Pos          (0U)

+#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */

+#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */

+

+/******************  Bit definition for I2C_TXDR register  *********************/

+#define I2C_TXDR_TXDATA_Pos          (0U)

+#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */

+#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           Independent WATCHDOG                             */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for IWDG_KR register  ********************/

+#define IWDG_KR_KEY_Pos      (0U)

+#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */

+#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */

+

+/*******************  Bit definition for IWDG_PR register  ********************/

+#define IWDG_PR_PR_Pos       (0U)

+#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */

+#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */

+#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */

+#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */

+#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */

+

+/*******************  Bit definition for IWDG_RLR register  *******************/

+#define IWDG_RLR_RL_Pos      (0U)

+#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */

+#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */

+

+/*******************  Bit definition for IWDG_SR register  ********************/

+#define IWDG_SR_PVU_Pos      (0U)

+#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */

+#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */

+#define IWDG_SR_RVU_Pos      (1U)

+#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */

+#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */

+#define IWDG_SR_WVU_Pos      (2U)

+#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */

+#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */

+

+/*******************  Bit definition for IWDG_KR register  ********************/

+#define IWDG_WINR_WIN_Pos    (0U)

+#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */

+#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */

+

+/******************************************************************************/

+/*                                                                            */

+/*                        JPEG Encoder/Decoder                                */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for CONFR0 register  ********************/

+#define JPEG_CONFR0_START_Pos           (0U)

+#define JPEG_CONFR0_START_Msk           (0x1UL << JPEG_CONFR0_START_Pos)       /*!< 0x00000001 */

+#define JPEG_CONFR0_START               JPEG_CONFR0_START_Msk                  /*!<Start/Stop bit */

+

+/********************  Bit definition for CONFR1 register  ********************/

+#define JPEG_CONFR1_NF_Pos              (0U)

+#define JPEG_CONFR1_NF_Msk              (0x3UL << JPEG_CONFR1_NF_Pos)          /*!< 0x00000003 */

+#define JPEG_CONFR1_NF                  JPEG_CONFR1_NF_Msk                     /*!<Number of color components */

+#define JPEG_CONFR1_NF_0                (0x1UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000001 */

+#define JPEG_CONFR1_NF_1                (0x2UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000002 */

+#define JPEG_CONFR1_DE_Pos              (3U)

+#define JPEG_CONFR1_DE_Msk              (0x1UL << JPEG_CONFR1_DE_Pos)          /*!< 0x00000008 */

+#define JPEG_CONFR1_DE                  JPEG_CONFR1_DE_Msk                     /*!<Decoding Enable */

+#define JPEG_CONFR1_COLORSPACE_Pos      (4U)

+#define JPEG_CONFR1_COLORSPACE_Msk      (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)  /*!< 0x00000030 */

+#define JPEG_CONFR1_COLORSPACE          JPEG_CONFR1_COLORSPACE_Msk             /*!<Color Space */

+#define JPEG_CONFR1_COLORSPACE_0        (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000010 */

+#define JPEG_CONFR1_COLORSPACE_1        (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000020 */

+#define JPEG_CONFR1_NS_Pos              (6U)

+#define JPEG_CONFR1_NS_Msk              (0x3UL << JPEG_CONFR1_NS_Pos)          /*!< 0x000000C0 */

+#define JPEG_CONFR1_NS                  JPEG_CONFR1_NS_Msk                     /*!<Number of components for Scan */

+#define JPEG_CONFR1_NS_0                (0x1UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR1_NS_1                (0x2UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR1_HDR_Pos             (8U)

+#define JPEG_CONFR1_HDR_Msk             (0x1UL << JPEG_CONFR1_HDR_Pos)         /*!< 0x00000100 */

+#define JPEG_CONFR1_HDR                 JPEG_CONFR1_HDR_Msk                    /*!<Header Processing On/Off */

+#define JPEG_CONFR1_YSIZE_Pos           (16U)

+#define JPEG_CONFR1_YSIZE_Msk           (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)    /*!< 0xFFFF0000 */

+#define JPEG_CONFR1_YSIZE               JPEG_CONFR1_YSIZE_Msk                  /*!<Number of lines in source image */

+

+/********************  Bit definition for CONFR2 register  ********************/

+#define JPEG_CONFR2_NMCU_Pos            (0U)

+#define JPEG_CONFR2_NMCU_Msk            (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)  /*!< 0x03FFFFFF */

+#define JPEG_CONFR2_NMCU                JPEG_CONFR2_NMCU_Msk                   /*!<Number of MCU units minus 1 to encode */

+

+/********************  Bit definition for CONFR3 register  ********************/

+#define JPEG_CONFR3_XSIZE_Pos           (16U)

+#define JPEG_CONFR3_XSIZE_Msk           (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)    /*!< 0xFFFF0000 */

+#define JPEG_CONFR3_XSIZE               JPEG_CONFR3_XSIZE_Msk                  /*!<Number of pixels per line */

+

+/********************  Bit definition for CONFR4 register  ********************/

+#define JPEG_CONFR4_HD_Pos              (0U)

+#define JPEG_CONFR4_HD_Msk              (0x1UL << JPEG_CONFR4_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR4_HD                  JPEG_CONFR4_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR4_HA_Pos              (1U)

+#define JPEG_CONFR4_HA_Msk              (0x1UL << JPEG_CONFR4_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR4_HA                  JPEG_CONFR4_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR4_QT_Pos              (2U)

+#define JPEG_CONFR4_QT_Msk              (0x3UL << JPEG_CONFR4_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR4_QT                  JPEG_CONFR4_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR4_QT_0                (0x1UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR4_QT_1                (0x2UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR4_NB_Pos              (4U)

+#define JPEG_CONFR4_NB_Msk              (0xFUL << JPEG_CONFR4_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR4_NB                  JPEG_CONFR4_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR4_NB_0                (0x1UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR4_NB_1                (0x2UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR4_NB_2                (0x4UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR4_NB_3                (0x8UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR4_VSF_Pos             (8U)

+#define JPEG_CONFR4_VSF_Msk             (0xFUL << JPEG_CONFR4_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR4_VSF                 JPEG_CONFR4_VSF_Msk                    /*!<Vertical sampling factor for component 1 */

+#define JPEG_CONFR4_VSF_0               (0x1UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR4_VSF_1               (0x2UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR4_VSF_2               (0x4UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR4_VSF_3               (0x8UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR4_HSF_Pos             (12U)

+#define JPEG_CONFR4_HSF_Msk             (0xFUL << JPEG_CONFR4_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR4_HSF                 JPEG_CONFR4_HSF_Msk                    /*!<Horizontal sampling factor for component 1 */

+#define JPEG_CONFR4_HSF_0               (0x1UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR4_HSF_1               (0x2UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR4_HSF_2               (0x4UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR4_HSF_3               (0x8UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR5 register  ********************/

+#define JPEG_CONFR5_HD_Pos              (0U)

+#define JPEG_CONFR5_HD_Msk              (0x1UL << JPEG_CONFR5_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR5_HD                  JPEG_CONFR5_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR5_HA_Pos              (1U)

+#define JPEG_CONFR5_HA_Msk              (0x1UL << JPEG_CONFR5_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR5_HA                  JPEG_CONFR5_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR5_QT_Pos              (2U)

+#define JPEG_CONFR5_QT_Msk              (0x3UL << JPEG_CONFR5_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR5_QT                  JPEG_CONFR5_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR5_QT_0                (0x1UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR5_QT_1                (0x2UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR5_NB_Pos              (4U)

+#define JPEG_CONFR5_NB_Msk              (0xFUL << JPEG_CONFR5_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR5_NB                  JPEG_CONFR5_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR5_NB_0                (0x1UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR5_NB_1                (0x2UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR5_NB_2                (0x4UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR5_NB_3                (0x8UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR5_VSF_Pos             (8U)

+#define JPEG_CONFR5_VSF_Msk             (0xFUL << JPEG_CONFR5_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR5_VSF                 JPEG_CONFR5_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR5_VSF_0               (0x1UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR5_VSF_1               (0x2UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR5_VSF_2               (0x4UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR5_VSF_3               (0x8UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR5_HSF_Pos             (12U)

+#define JPEG_CONFR5_HSF_Msk             (0xFUL << JPEG_CONFR5_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR5_HSF                 JPEG_CONFR5_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR5_HSF_0               (0x1UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR5_HSF_1               (0x2UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR5_HSF_2               (0x4UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR5_HSF_3               (0x8UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR6 register  ********************/

+#define JPEG_CONFR6_HD_Pos              (0U)

+#define JPEG_CONFR6_HD_Msk              (0x1UL << JPEG_CONFR6_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR6_HD                  JPEG_CONFR6_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR6_HA_Pos              (1U)

+#define JPEG_CONFR6_HA_Msk              (0x1UL << JPEG_CONFR6_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR6_HA                  JPEG_CONFR6_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR6_QT_Pos              (2U)

+#define JPEG_CONFR6_QT_Msk              (0x3UL << JPEG_CONFR6_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR6_QT                  JPEG_CONFR6_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR6_QT_0                (0x1UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR6_QT_1                (0x2UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR6_NB_Pos              (4U)

+#define JPEG_CONFR6_NB_Msk              (0xFUL << JPEG_CONFR6_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR6_NB                  JPEG_CONFR6_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR6_NB_0                (0x1UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR6_NB_1                (0x2UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR6_NB_2                (0x4UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR6_NB_3                (0x8UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR6_VSF_Pos             (8U)

+#define JPEG_CONFR6_VSF_Msk             (0xFUL << JPEG_CONFR6_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR6_VSF                 JPEG_CONFR6_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR6_VSF_0               (0x1UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR6_VSF_1               (0x2UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR6_VSF_2               (0x4UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR6_VSF_3               (0x8UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR6_HSF_Pos             (12U)

+#define JPEG_CONFR6_HSF_Msk             (0xFUL << JPEG_CONFR6_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR6_HSF                 JPEG_CONFR6_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR6_HSF_0               (0x1UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR6_HSF_1               (0x2UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR6_HSF_2               (0x4UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR6_HSF_3               (0x8UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR7 register  ********************/

+#define JPEG_CONFR7_HD_Pos              (0U)

+#define JPEG_CONFR7_HD_Msk              (0x1UL << JPEG_CONFR7_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR7_HD                  JPEG_CONFR7_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR7_HA_Pos              (1U)

+#define JPEG_CONFR7_HA_Msk              (0x1UL << JPEG_CONFR7_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR7_HA                  JPEG_CONFR7_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR7_QT_Pos              (2U)

+#define JPEG_CONFR7_QT_Msk              (0x3UL << JPEG_CONFR7_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR7_QT                  JPEG_CONFR7_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR7_QT_0                (0x1UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR7_QT_1                (0x2UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR7_NB_Pos              (4U)

+#define JPEG_CONFR7_NB_Msk              (0xFUL << JPEG_CONFR7_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR7_NB                  JPEG_CONFR7_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR7_NB_0                (0x1UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR7_NB_1                (0x2UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR7_NB_2                (0x4UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR7_NB_3                (0x8UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR7_VSF_Pos             (8U)

+#define JPEG_CONFR7_VSF_Msk             (0xFUL << JPEG_CONFR7_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR7_VSF                 JPEG_CONFR7_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR7_VSF_0               (0x1UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR7_VSF_1               (0x2UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR7_VSF_2               (0x4UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR7_VSF_3               (0x8UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR7_HSF_Pos             (12U)

+#define JPEG_CONFR7_HSF_Msk             (0xFUL << JPEG_CONFR7_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR7_HSF                 JPEG_CONFR7_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR7_HSF_0               (0x1UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR7_HSF_1               (0x2UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR7_HSF_2               (0x4UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR7_HSF_3               (0x8UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CR register  ********************/

+#define JPEG_CR_JCEN_Pos                (0U)

+#define JPEG_CR_JCEN_Msk                (0x1UL << JPEG_CR_JCEN_Pos)            /*!< 0x00000001 */

+#define JPEG_CR_JCEN                    JPEG_CR_JCEN_Msk                       /*!<Enable the JPEG Codec Core */

+#define JPEG_CR_IFTIE_Pos               (1U)

+#define JPEG_CR_IFTIE_Msk               (0x1UL << JPEG_CR_IFTIE_Pos)           /*!< 0x00000002 */

+#define JPEG_CR_IFTIE                   JPEG_CR_IFTIE_Msk                      /*!<Input FIFO Threshold Interrupt Enable */

+#define JPEG_CR_IFNFIE_Pos              (2U)

+#define JPEG_CR_IFNFIE_Msk              (0x1UL << JPEG_CR_IFNFIE_Pos)          /*!< 0x00000004 */

+#define JPEG_CR_IFNFIE                  JPEG_CR_IFNFIE_Msk                     /*!<Input FIFO Not Full Interrupt Enable */

+#define JPEG_CR_OFTIE_Pos               (3U)

+#define JPEG_CR_OFTIE_Msk               (0x1UL << JPEG_CR_OFTIE_Pos)           /*!< 0x00000008 */

+#define JPEG_CR_OFTIE                   JPEG_CR_OFTIE_Msk                      /*!<Output FIFO Threshold Interrupt Enable */

+#define JPEG_CR_OFNEIE_Pos              (4U)

+#define JPEG_CR_OFNEIE_Msk              (0x1UL << JPEG_CR_OFNEIE_Pos)          /*!< 0x00000010 */

+#define JPEG_CR_OFNEIE                  JPEG_CR_OFNEIE_Msk                     /*!<Output FIFO Not Empty Interrupt Enable */

+#define JPEG_CR_EOCIE_Pos               (5U)

+#define JPEG_CR_EOCIE_Msk               (0x1UL << JPEG_CR_EOCIE_Pos)           /*!< 0x00000020 */

+#define JPEG_CR_EOCIE                   JPEG_CR_EOCIE_Msk                      /*!<End of Conversion Interrupt Enable */

+#define JPEG_CR_HPDIE_Pos               (6U)

+#define JPEG_CR_HPDIE_Msk               (0x1UL << JPEG_CR_HPDIE_Pos)           /*!< 0x00000040 */

+#define JPEG_CR_HPDIE                   JPEG_CR_HPDIE_Msk                      /*!<Header Parsing Done Interrupt Enable */

+#define JPEG_CR_IFF_Pos                 (13U)

+#define JPEG_CR_IFF_Msk                 (0x1UL << JPEG_CR_IFF_Pos)             /*!< 0x00002000 */

+#define JPEG_CR_IFF                     JPEG_CR_IFF_Msk                        /*!<Flush the input FIFO */

+#define JPEG_CR_OFF_Pos                 (14U)

+#define JPEG_CR_OFF_Msk                 (0x1UL << JPEG_CR_OFF_Pos)             /*!< 0x00004000 */

+#define JPEG_CR_OFF                     JPEG_CR_OFF_Msk                        /*!<Flush the output FIFO */

+

+/********************  Bit definition for SR register  ********************/

+#define JPEG_SR_IFTF_Pos                (1U)

+#define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */

+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is bellow its threshold flag */

+#define JPEG_SR_IFNFF_Pos               (2U)

+#define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */

+#define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */

+#define JPEG_SR_OFTF_Pos                (3U)

+#define JPEG_SR_OFTF_Msk                (0x1UL << JPEG_SR_OFTF_Pos)            /*!< 0x00000008 */

+#define JPEG_SR_OFTF                    JPEG_SR_OFTF_Msk                       /*!<Output FIFO is not empty and has reach its threshold */

+#define JPEG_SR_OFNEF_Pos               (4U)

+#define JPEG_SR_OFNEF_Msk               (0x1UL << JPEG_SR_OFNEF_Pos)           /*!< 0x00000010 */

+#define JPEG_SR_OFNEF                   JPEG_SR_OFNEF_Msk                      /*!<Output FIFO is not empty, a data is available */

+#define JPEG_SR_EOCF_Pos                (5U)

+#define JPEG_SR_EOCF_Msk                (0x1UL << JPEG_SR_EOCF_Pos)            /*!< 0x00000020 */

+#define JPEG_SR_EOCF                    JPEG_SR_EOCF_Msk                       /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */

+#define JPEG_SR_HPDF_Pos                (6U)

+#define JPEG_SR_HPDF_Msk                (0x1UL << JPEG_SR_HPDF_Pos)            /*!< 0x00000040 */

+#define JPEG_SR_HPDF                    JPEG_SR_HPDF_Msk                       /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */

+#define JPEG_SR_COF_Pos                 (7U)

+#define JPEG_SR_COF_Msk                 (0x1UL << JPEG_SR_COF_Pos)             /*!< 0x00000080 */

+#define JPEG_SR_COF                     JPEG_SR_COF_Msk                        /*!<JPEG Codec operation on going flag */

+

+/********************  Bit definition for CFR register  ********************/

+#define JPEG_CFR_CEOCF_Pos              (4U)

+#define JPEG_CFR_CEOCF_Msk              (0x1UL << JPEG_CFR_CEOCF_Pos)          /*!< 0x00000010 */

+#define JPEG_CFR_CEOCF                  JPEG_CFR_CEOCF_Msk                     /*!<Clear End of Conversion Flag */

+#define JPEG_CFR_CHPDF_Pos              (5U)

+#define JPEG_CFR_CHPDF_Msk              (0x1UL << JPEG_CFR_CHPDF_Pos)          /*!< 0x00000020 */

+#define JPEG_CFR_CHPDF                  JPEG_CFR_CHPDF_Msk                     /*!<Clear Header Parsing Done Flag */

+

+/********************  Bit definition for DIR register  ********************/

+#define JPEG_DIR_DATAIN_Pos             (0U)

+#define JPEG_DIR_DATAIN_Msk             (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)  /*!< 0xFFFFFFFF */

+#define JPEG_DIR_DATAIN                 JPEG_DIR_DATAIN_Msk                    /*!<Data Input FIFO */

+

+/********************  Bit definition for DOR register  ********************/

+#define JPEG_DOR_DATAOUT_Pos            (0U)

+#define JPEG_DOR_DATAOUT_Msk            (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */

+#define JPEG_DOR_DATAOUT                JPEG_DOR_DATAOUT_Msk                   /*!<Data Output FIFO */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      LCD-TFT Display Controller (LTDC)                     */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for LTDC_SSCR register  *****************/

+

+#define LTDC_SSCR_VSH_Pos            (0U)

+#define LTDC_SSCR_VSH_Msk            (0x7FFUL << LTDC_SSCR_VSH_Pos)            /*!< 0x000007FF */

+#define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height  */

+#define LTDC_SSCR_HSW_Pos            (16U)

+#define LTDC_SSCR_HSW_Msk            (0xFFFUL << LTDC_SSCR_HSW_Pos)            /*!< 0x0FFF0000 */

+#define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */

+

+/********************  Bit definition for LTDC_BPCR register  *****************/

+

+#define LTDC_BPCR_AVBP_Pos           (0U)

+#define LTDC_BPCR_AVBP_Msk           (0x7FFUL << LTDC_BPCR_AVBP_Pos)           /*!< 0x000007FF */

+#define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch   */

+#define LTDC_BPCR_AHBP_Pos           (16U)

+#define LTDC_BPCR_AHBP_Msk           (0xFFFUL << LTDC_BPCR_AHBP_Pos)           /*!< 0x0FFF0000 */

+#define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */

+

+/********************  Bit definition for LTDC_AWCR register  *****************/

+

+#define LTDC_AWCR_AAH_Pos            (0U)

+#define LTDC_AWCR_AAH_Msk            (0x7FFUL << LTDC_AWCR_AAH_Pos)            /*!< 0x000007FF */

+#define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active heigh */

+#define LTDC_AWCR_AAW_Pos            (16U)

+#define LTDC_AWCR_AAW_Msk            (0xFFFUL << LTDC_AWCR_AAW_Pos)            /*!< 0x0FFF0000 */

+#define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */

+

+/********************  Bit definition for LTDC_TWCR register  *****************/

+

+#define LTDC_TWCR_TOTALH_Pos         (0U)

+#define LTDC_TWCR_TOTALH_Msk         (0x7FFUL << LTDC_TWCR_TOTALH_Pos)         /*!< 0x000007FF */

+#define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total Heigh */

+#define LTDC_TWCR_TOTALW_Pos         (16U)

+#define LTDC_TWCR_TOTALW_Msk         (0xFFFUL << LTDC_TWCR_TOTALW_Pos)         /*!< 0x0FFF0000 */

+#define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */

+

+/********************  Bit definition for LTDC_GCR register  ******************/

+

+#define LTDC_GCR_LTDCEN_Pos          (0U)

+#define LTDC_GCR_LTDCEN_Msk          (0x1UL << LTDC_GCR_LTDCEN_Pos)            /*!< 0x00000001 */

+#define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit       */

+#define LTDC_GCR_DBW_Pos             (4U)

+#define LTDC_GCR_DBW_Msk             (0x7UL << LTDC_GCR_DBW_Pos)               /*!< 0x00000070 */

+#define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width                   */

+#define LTDC_GCR_DGW_Pos             (8U)

+#define LTDC_GCR_DGW_Msk             (0x7UL << LTDC_GCR_DGW_Pos)               /*!< 0x00000700 */

+#define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width                  */

+#define LTDC_GCR_DRW_Pos             (12U)

+#define LTDC_GCR_DRW_Msk             (0x7UL << LTDC_GCR_DRW_Pos)               /*!< 0x00007000 */

+#define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width                    */

+#define LTDC_GCR_DEN_Pos             (16U)

+#define LTDC_GCR_DEN_Msk             (0x1UL << LTDC_GCR_DEN_Pos)               /*!< 0x00010000 */

+#define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable                       */

+#define LTDC_GCR_PCPOL_Pos           (28U)

+#define LTDC_GCR_PCPOL_Msk           (0x1UL << LTDC_GCR_PCPOL_Pos)             /*!< 0x10000000 */

+#define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity                */

+#define LTDC_GCR_DEPOL_Pos           (29U)

+#define LTDC_GCR_DEPOL_Msk           (0x1UL << LTDC_GCR_DEPOL_Pos)             /*!< 0x20000000 */

+#define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity                */

+#define LTDC_GCR_VSPOL_Pos           (30U)

+#define LTDC_GCR_VSPOL_Msk           (0x1UL << LTDC_GCR_VSPOL_Pos)             /*!< 0x40000000 */

+#define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity   */

+#define LTDC_GCR_HSPOL_Pos           (31U)

+#define LTDC_GCR_HSPOL_Msk           (0x1UL << LTDC_GCR_HSPOL_Pos)             /*!< 0x80000000 */

+#define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */

+

+

+/********************  Bit definition for LTDC_SRCR register  *****************/

+

+#define LTDC_SRCR_IMR_Pos            (0U)

+#define LTDC_SRCR_IMR_Msk            (0x1UL << LTDC_SRCR_IMR_Pos)              /*!< 0x00000001 */

+#define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload         */

+#define LTDC_SRCR_VBR_Pos            (1U)

+#define LTDC_SRCR_VBR_Msk            (0x1UL << LTDC_SRCR_VBR_Pos)              /*!< 0x00000002 */

+#define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */

+

+/********************  Bit definition for LTDC_BCCR register  *****************/

+

+#define LTDC_BCCR_BCBLUE_Pos         (0U)

+#define LTDC_BCCR_BCBLUE_Msk         (0xFFUL << LTDC_BCCR_BCBLUE_Pos)          /*!< 0x000000FF */

+#define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value  */

+#define LTDC_BCCR_BCGREEN_Pos        (8U)

+#define LTDC_BCCR_BCGREEN_Msk        (0xFFUL << LTDC_BCCR_BCGREEN_Pos)         /*!< 0x0000FF00 */

+#define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */

+#define LTDC_BCCR_BCRED_Pos          (16U)

+#define LTDC_BCCR_BCRED_Msk          (0xFFUL << LTDC_BCCR_BCRED_Pos)           /*!< 0x00FF0000 */

+#define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value   */

+

+/********************  Bit definition for LTDC_IER register  ******************/

+

+#define LTDC_IER_LIE_Pos             (0U)

+#define LTDC_IER_LIE_Msk             (0x1UL << LTDC_IER_LIE_Pos)               /*!< 0x00000001 */

+#define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable            */

+#define LTDC_IER_FUIE_Pos            (1U)

+#define LTDC_IER_FUIE_Msk            (0x1UL << LTDC_IER_FUIE_Pos)              /*!< 0x00000002 */

+#define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable   */

+#define LTDC_IER_TERRIE_Pos          (2U)

+#define LTDC_IER_TERRIE_Msk          (0x1UL << LTDC_IER_TERRIE_Pos)            /*!< 0x00000004 */

+#define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable  */

+#define LTDC_IER_RRIE_Pos            (3U)

+#define LTDC_IER_RRIE_Msk            (0x1UL << LTDC_IER_RRIE_Pos)              /*!< 0x00000008 */

+#define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */

+

+/********************  Bit definition for LTDC_ISR register  ******************/

+

+#define LTDC_ISR_LIF_Pos             (0U)

+#define LTDC_ISR_LIF_Msk             (0x1UL << LTDC_ISR_LIF_Pos)               /*!< 0x00000001 */

+#define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */

+#define LTDC_ISR_FUIF_Pos            (1U)

+#define LTDC_ISR_FUIF_Msk            (0x1UL << LTDC_ISR_FUIF_Pos)              /*!< 0x00000002 */

+#define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */

+#define LTDC_ISR_TERRIF_Pos          (2U)

+#define LTDC_ISR_TERRIF_Msk          (0x1UL << LTDC_ISR_TERRIF_Pos)            /*!< 0x00000004 */

+#define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */

+#define LTDC_ISR_RRIF_Pos            (3U)

+#define LTDC_ISR_RRIF_Msk            (0x1UL << LTDC_ISR_RRIF_Pos)              /*!< 0x00000008 */

+#define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */

+

+/********************  Bit definition for LTDC_ICR register  ******************/

+

+#define LTDC_ICR_CLIF_Pos            (0U)

+#define LTDC_ICR_CLIF_Msk            (0x1UL << LTDC_ICR_CLIF_Pos)              /*!< 0x00000001 */

+#define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */

+#define LTDC_ICR_CFUIF_Pos           (1U)

+#define LTDC_ICR_CFUIF_Msk           (0x1UL << LTDC_ICR_CFUIF_Pos)             /*!< 0x00000002 */

+#define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */

+#define LTDC_ICR_CTERRIF_Pos         (2U)

+#define LTDC_ICR_CTERRIF_Msk         (0x1UL << LTDC_ICR_CTERRIF_Pos)           /*!< 0x00000004 */

+#define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */

+#define LTDC_ICR_CRRIF_Pos           (3U)

+#define LTDC_ICR_CRRIF_Msk           (0x1UL << LTDC_ICR_CRRIF_Pos)             /*!< 0x00000008 */

+#define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */

+

+/********************  Bit definition for LTDC_LIPCR register  ****************/

+

+#define LTDC_LIPCR_LIPOS_Pos         (0U)

+#define LTDC_LIPCR_LIPOS_Msk         (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)         /*!< 0x000007FF */

+#define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */

+

+/********************  Bit definition for LTDC_CPSR register  *****************/

+

+#define LTDC_CPSR_CYPOS_Pos          (0U)

+#define LTDC_CPSR_CYPOS_Msk          (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)         /*!< 0x0000FFFF */

+#define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */

+#define LTDC_CPSR_CXPOS_Pos          (16U)

+#define LTDC_CPSR_CXPOS_Msk          (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)         /*!< 0xFFFF0000 */

+#define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */

+

+/********************  Bit definition for LTDC_CDSR register  *****************/

+

+#define LTDC_CDSR_VDES_Pos           (0U)

+#define LTDC_CDSR_VDES_Msk           (0x1UL << LTDC_CDSR_VDES_Pos)             /*!< 0x00000001 */

+#define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status       */

+#define LTDC_CDSR_HDES_Pos           (1U)

+#define LTDC_CDSR_HDES_Msk           (0x1UL << LTDC_CDSR_HDES_Pos)             /*!< 0x00000002 */

+#define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status     */

+#define LTDC_CDSR_VSYNCS_Pos         (2U)

+#define LTDC_CDSR_VSYNCS_Msk         (0x1UL << LTDC_CDSR_VSYNCS_Pos)           /*!< 0x00000004 */

+#define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status   */

+#define LTDC_CDSR_HSYNCS_Pos         (3U)

+#define LTDC_CDSR_HSYNCS_Msk         (0x1UL << LTDC_CDSR_HSYNCS_Pos)           /*!< 0x00000008 */

+#define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */

+

+/********************  Bit definition for LTDC_LxCR register  *****************/

+

+#define LTDC_LxCR_LEN_Pos            (0U)

+#define LTDC_LxCR_LEN_Msk            (0x1UL << LTDC_LxCR_LEN_Pos)              /*!< 0x00000001 */

+#define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable              */

+#define LTDC_LxCR_COLKEN_Pos         (1U)

+#define LTDC_LxCR_COLKEN_Msk         (0x1UL << LTDC_LxCR_COLKEN_Pos)           /*!< 0x00000002 */

+#define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable       */

+#define LTDC_LxCR_CLUTEN_Pos         (4U)

+#define LTDC_LxCR_CLUTEN_Msk         (0x1UL << LTDC_LxCR_CLUTEN_Pos)           /*!< 0x00000010 */

+#define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */

+

+/********************  Bit definition for LTDC_LxWHPCR register  **************/

+

+#define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)

+#define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)     /*!< 0x00000FFF */

+#define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */

+#define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)

+#define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)    /*!< 0xFFFF0000 */

+#define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position  */

+

+/********************  Bit definition for LTDC_LxWVPCR register  **************/

+

+#define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)

+#define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)     /*!< 0x00000FFF */

+#define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */

+#define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)

+#define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)    /*!< 0xFFFF0000 */

+#define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position  */

+

+/********************  Bit definition for LTDC_LxCKCR register  ***************/

+

+#define LTDC_LxCKCR_CKBLUE_Pos       (0U)

+#define LTDC_LxCKCR_CKBLUE_Msk       (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value  */

+#define LTDC_LxCKCR_CKGREEN_Pos      (8U)

+#define LTDC_LxCKCR_CKGREEN_Msk      (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */

+#define LTDC_LxCKCR_CKRED_Pos        (16U)

+#define LTDC_LxCKCR_CKRED_Msk        (0xFFUL << LTDC_LxCKCR_CKRED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value   */

+

+/********************  Bit definition for LTDC_LxPFCR register  ***************/

+

+#define LTDC_LxPFCR_PF_Pos           (0U)

+#define LTDC_LxPFCR_PF_Msk           (0x7UL << LTDC_LxPFCR_PF_Pos)             /*!< 0x00000007 */

+#define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */

+

+/********************  Bit definition for LTDC_LxCACR register  ***************/

+

+#define LTDC_LxCACR_CONSTA_Pos       (0U)

+#define LTDC_LxCACR_CONSTA_Msk       (0xFFUL << LTDC_LxCACR_CONSTA_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */

+

+/********************  Bit definition for LTDC_LxDCCR register  ***************/

+

+#define LTDC_LxDCCR_DCBLUE_Pos       (0U)

+#define LTDC_LxDCCR_DCBLUE_Msk       (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue  */

+#define LTDC_LxDCCR_DCGREEN_Pos      (8U)

+#define LTDC_LxDCCR_DCGREEN_Msk      (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */

+#define LTDC_LxDCCR_DCRED_Pos        (16U)

+#define LTDC_LxDCCR_DCRED_Msk        (0xFFUL << LTDC_LxDCCR_DCRED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red   */

+#define LTDC_LxDCCR_DCALPHA_Pos      (24U)

+#define LTDC_LxDCCR_DCALPHA_Msk      (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)       /*!< 0xFF000000 */

+#define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */

+

+/********************  Bit definition for LTDC_LxBFCR register  ***************/

+

+#define LTDC_LxBFCR_BF2_Pos          (0U)

+#define LTDC_LxBFCR_BF2_Msk          (0x7UL << LTDC_LxBFCR_BF2_Pos)            /*!< 0x00000007 */

+#define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */

+#define LTDC_LxBFCR_BF1_Pos          (8U)

+#define LTDC_LxBFCR_BF1_Msk          (0x7UL << LTDC_LxBFCR_BF1_Pos)            /*!< 0x00000700 */

+#define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */

+

+/********************  Bit definition for LTDC_LxCFBAR register  **************/

+

+#define LTDC_LxCFBAR_CFBADD_Pos      (0U)

+#define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */

+#define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */

+

+/********************  Bit definition for LTDC_LxCFBLR register  **************/

+

+#define LTDC_LxCFBLR_CFBLL_Pos       (0U)

+#define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)      /*!< 0x00001FFF */

+#define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length    */

+#define LTDC_LxCFBLR_CFBP_Pos        (16U)

+#define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)       /*!< 0x1FFF0000 */

+#define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */

+

+/********************  Bit definition for LTDC_LxCFBLNR register  *************/

+

+#define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)

+#define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)    /*!< 0x000007FF */

+#define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */

+

+/********************  Bit definition for LTDC_LxCLUTWR register  *************/

+

+#define LTDC_LxCLUTWR_BLUE_Pos       (0U)

+#define LTDC_LxCLUTWR_BLUE_Msk       (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value   */

+#define LTDC_LxCLUTWR_GREEN_Pos      (8U)

+#define LTDC_LxCLUTWR_GREEN_Msk      (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value  */

+#define LTDC_LxCLUTWR_RED_Pos        (16U)

+#define LTDC_LxCLUTWR_RED_Msk        (0xFFUL << LTDC_LxCLUTWR_RED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value    */

+#define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)

+#define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)     /*!< 0xFF000000 */

+#define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                     MDMA                                   */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for MDMA_GISR0 register  ****************/

+#define MDMA_GISR0_GIF0_Pos       (0U)

+#define MDMA_GISR0_GIF0_Msk       (0x1UL << MDMA_GISR0_GIF0_Pos)               /*!< 0x00000001 */

+#define MDMA_GISR0_GIF0           MDMA_GISR0_GIF0_Msk                          /*!< Channel 0 global interrupt flag */

+#define MDMA_GISR0_GIF1_Pos       (1U)

+#define MDMA_GISR0_GIF1_Msk       (0x1UL << MDMA_GISR0_GIF1_Pos)               /*!< 0x00000002 */

+#define MDMA_GISR0_GIF1           MDMA_GISR0_GIF1_Msk                          /*!< Channel 1 global interrupt flag */

+#define MDMA_GISR0_GIF2_Pos       (2U)

+#define MDMA_GISR0_GIF2_Msk       (0x1UL << MDMA_GISR0_GIF2_Pos)               /*!< 0x00000004 */

+#define MDMA_GISR0_GIF2           MDMA_GISR0_GIF2_Msk                          /*!< Channel 2 global interrupt flag */

+#define MDMA_GISR0_GIF3_Pos       (3U)

+#define MDMA_GISR0_GIF3_Msk       (0x1UL << MDMA_GISR0_GIF3_Pos)               /*!< 0x00000008 */

+#define MDMA_GISR0_GIF3           MDMA_GISR0_GIF3_Msk                          /*!< Channel 3 global interrupt flag */

+#define MDMA_GISR0_GIF4_Pos       (4U)

+#define MDMA_GISR0_GIF4_Msk       (0x1UL << MDMA_GISR0_GIF4_Pos)               /*!< 0x00000010 */

+#define MDMA_GISR0_GIF4           MDMA_GISR0_GIF4_Msk                          /*!< Channel 4 global interrupt flag */

+#define MDMA_GISR0_GIF5_Pos       (5U)

+#define MDMA_GISR0_GIF5_Msk       (0x1UL << MDMA_GISR0_GIF5_Pos)               /*!< 0x00000020 */

+#define MDMA_GISR0_GIF5           MDMA_GISR0_GIF5_Msk                          /*!< Channel 5 global interrupt flag */

+#define MDMA_GISR0_GIF6_Pos       (6U)

+#define MDMA_GISR0_GIF6_Msk       (0x1UL << MDMA_GISR0_GIF6_Pos)               /*!< 0x00000040 */

+#define MDMA_GISR0_GIF6           MDMA_GISR0_GIF6_Msk                          /*!< Channel 6 global interrupt flag */

+#define MDMA_GISR0_GIF7_Pos       (7U)

+#define MDMA_GISR0_GIF7_Msk       (0x1UL << MDMA_GISR0_GIF7_Pos)               /*!< 0x00000080 */

+#define MDMA_GISR0_GIF7           MDMA_GISR0_GIF7_Msk                          /*!< Channel 7 global interrupt flag */

+#define MDMA_GISR0_GIF8_Pos       (8U)

+#define MDMA_GISR0_GIF8_Msk       (0x1UL << MDMA_GISR0_GIF8_Pos)               /*!< 0x00000100 */

+#define MDMA_GISR0_GIF8           MDMA_GISR0_GIF8_Msk                          /*!< Channel 8 global interrupt flag */

+#define MDMA_GISR0_GIF9_Pos       (9U)

+#define MDMA_GISR0_GIF9_Msk       (0x1UL << MDMA_GISR0_GIF9_Pos)               /*!< 0x00000200 */

+#define MDMA_GISR0_GIF9           MDMA_GISR0_GIF9_Msk                          /*!< Channel 9 global interrupt flag */

+#define MDMA_GISR0_GIF10_Pos      (10U)

+#define MDMA_GISR0_GIF10_Msk      (0x1UL << MDMA_GISR0_GIF10_Pos)              /*!< 0x00000400 */

+#define MDMA_GISR0_GIF10          MDMA_GISR0_GIF10_Msk                         /*!< Channel 10 global interrupt flag */

+#define MDMA_GISR0_GIF11_Pos      (11U)

+#define MDMA_GISR0_GIF11_Msk      (0x1UL << MDMA_GISR0_GIF11_Pos)              /*!< 0x00000800 */

+#define MDMA_GISR0_GIF11          MDMA_GISR0_GIF11_Msk                         /*!< Channel 11 global interrupt flag */

+#define MDMA_GISR0_GIF12_Pos      (12U)

+#define MDMA_GISR0_GIF12_Msk      (0x1UL << MDMA_GISR0_GIF12_Pos)              /*!< 0x00001000 */

+#define MDMA_GISR0_GIF12          MDMA_GISR0_GIF12_Msk                         /*!< Channel 12 global interrupt flag */

+#define MDMA_GISR0_GIF13_Pos      (13U)

+#define MDMA_GISR0_GIF13_Msk      (0x1UL << MDMA_GISR0_GIF13_Pos)              /*!< 0x00002000 */

+#define MDMA_GISR0_GIF13          MDMA_GISR0_GIF13_Msk                         /*!< Channel 13 global interrupt flag */

+#define MDMA_GISR0_GIF14_Pos      (14U)

+#define MDMA_GISR0_GIF14_Msk      (0x1UL << MDMA_GISR0_GIF14_Pos)              /*!< 0x00004000 */

+#define MDMA_GISR0_GIF14          MDMA_GISR0_GIF14_Msk                         /*!< Channel 14 global interrupt flag */

+#define MDMA_GISR0_GIF15_Pos      (15U)

+#define MDMA_GISR0_GIF15_Msk      (0x1UL << MDMA_GISR0_GIF15_Pos)              /*!< 0x00008000 */

+#define MDMA_GISR0_GIF15          MDMA_GISR0_GIF15_Msk                         /*!< Channel 15 global interrupt flag */

+

+/********************  Bit definition for MDMA_CxISR register  ****************/

+#define MDMA_CISR_TEIF_Pos        (0U)

+#define MDMA_CISR_TEIF_Msk        (0x1UL << MDMA_CISR_TEIF_Pos)                /*!< 0x00000001 */

+#define MDMA_CISR_TEIF            MDMA_CISR_TEIF_Msk                           /*!< Channel x transfer error interrupt flag */

+#define MDMA_CISR_CTCIF_Pos       (1U)

+#define MDMA_CISR_CTCIF_Msk       (0x1UL << MDMA_CISR_CTCIF_Pos)               /*!< 0x00000002 */

+#define MDMA_CISR_CTCIF           MDMA_CISR_CTCIF_Msk                          /*!< Channel x Channel Transfer Complete interrupt flag */

+#define MDMA_CISR_BRTIF_Pos       (2U)

+#define MDMA_CISR_BRTIF_Msk       (0x1UL << MDMA_CISR_BRTIF_Pos)               /*!< 0x00000004 */

+#define MDMA_CISR_BRTIF           MDMA_CISR_BRTIF_Msk                          /*!< Channel x block repeat transfer complete interrupt flag */

+#define MDMA_CISR_BTIF_Pos        (3U)

+#define MDMA_CISR_BTIF_Msk        (0x1UL << MDMA_CISR_BTIF_Pos)                /*!< 0x00000008 */

+#define MDMA_CISR_BTIF            MDMA_CISR_BTIF_Msk                           /*!< Channel x block transfer complete interrupt flag */

+#define MDMA_CISR_TCIF_Pos        (4U)

+#define MDMA_CISR_TCIF_Msk        (0x1UL << MDMA_CISR_TCIF_Pos)                /*!< 0x00000010 */

+#define MDMA_CISR_TCIF            MDMA_CISR_TCIF_Msk                           /*!< Channel x buffer transfer complete interrupt flag */

+#define MDMA_CISR_CRQA_Pos        (16U)

+#define MDMA_CISR_CRQA_Msk        (0x1UL << MDMA_CISR_CRQA_Pos)                /*!< 0x00010000 */

+#define MDMA_CISR_CRQA            MDMA_CISR_CRQA_Msk                           /*!< Channel x ReQest Active flag */

+

+/********************  Bit definition for MDMA_CxIFCR register  ****************/

+#define MDMA_CIFCR_CTEIF_Pos      (0U)

+#define MDMA_CIFCR_CTEIF_Msk      (0x1UL << MDMA_CIFCR_CTEIF_Pos)              /*!< 0x00000001 */

+#define MDMA_CIFCR_CTEIF          MDMA_CIFCR_CTEIF_Msk                         /*!< Channel x clear transfer error interrupt flag */

+#define MDMA_CIFCR_CCTCIF_Pos     (1U)

+#define MDMA_CIFCR_CCTCIF_Msk     (0x1UL << MDMA_CIFCR_CCTCIF_Pos)             /*!< 0x00000002 */

+#define MDMA_CIFCR_CCTCIF         MDMA_CIFCR_CCTCIF_Msk                        /*!< Clear Channel transfer complete interrupt flag for channel x */

+#define MDMA_CIFCR_CBRTIF_Pos     (2U)

+#define MDMA_CIFCR_CBRTIF_Msk     (0x1UL << MDMA_CIFCR_CBRTIF_Pos)             /*!< 0x00000004 */

+#define MDMA_CIFCR_CBRTIF         MDMA_CIFCR_CBRTIF_Msk                        /*!< Channel x clear block repeat transfer complete interrupt flag */

+#define MDMA_CIFCR_CBTIF_Pos      (3U)

+#define MDMA_CIFCR_CBTIF_Msk      (0x1UL << MDMA_CIFCR_CBTIF_Pos)              /*!< 0x00000008 */

+#define MDMA_CIFCR_CBTIF          MDMA_CIFCR_CBTIF_Msk                         /*!< Channel x Clear block transfer complete interrupt flag */

+#define MDMA_CIFCR_CLTCIF_Pos     (4U)

+#define MDMA_CIFCR_CLTCIF_Msk     (0x1UL << MDMA_CIFCR_CLTCIF_Pos)             /*!< 0x00000010 */

+#define MDMA_CIFCR_CLTCIF         MDMA_CIFCR_CLTCIF_Msk                        /*!< CLear Transfer buffer Complete Interrupt Flag for channel */

+

+/********************  Bit definition for MDMA_CxESR register  ****************/

+#define MDMA_CESR_TEA_Pos         (0U)

+#define MDMA_CESR_TEA_Msk         (0x7FUL << MDMA_CESR_TEA_Pos)                /*!< 0x0000007F */

+#define MDMA_CESR_TEA             MDMA_CESR_TEA_Msk                            /*!< Transfer Error Address */

+#define MDMA_CESR_TED_Pos         (7U)

+#define MDMA_CESR_TED_Msk         (0x1UL << MDMA_CESR_TED_Pos)                 /*!< 0x00000080 */

+#define MDMA_CESR_TED             MDMA_CESR_TED_Msk                            /*!< Transfer Error Direction */

+#define MDMA_CESR_TELD_Pos        (8U)

+#define MDMA_CESR_TELD_Msk        (0x1UL << MDMA_CESR_TELD_Pos)                /*!< 0x00000100 */

+#define MDMA_CESR_TELD            MDMA_CESR_TELD_Msk                           /*!< Transfer Error Link Data */

+#define MDMA_CESR_TEMD_Pos        (9U)

+#define MDMA_CESR_TEMD_Msk        (0x1UL << MDMA_CESR_TEMD_Pos)                /*!< 0x00000200 */

+#define MDMA_CESR_TEMD            MDMA_CESR_TEMD_Msk                           /*!< Transfer Error Mask Data */

+#define MDMA_CESR_ASE_Pos         (10U)

+#define MDMA_CESR_ASE_Msk         (0x1UL << MDMA_CESR_ASE_Pos)                 /*!< 0x00000400 */

+#define MDMA_CESR_ASE             MDMA_CESR_ASE_Msk                            /*!< Address/Size Error       */

+#define MDMA_CESR_BSE_Pos         (11U)

+#define MDMA_CESR_BSE_Msk         (0x1UL << MDMA_CESR_BSE_Pos)                 /*!< 0x00000800 */

+#define MDMA_CESR_BSE             MDMA_CESR_BSE_Msk                            /*!< Block Size Error         */

+

+/********************  Bit definition for MDMA_CxCR register  ****************/

+#define MDMA_CCR_EN_Pos           (0U)

+#define MDMA_CCR_EN_Msk           (0x1UL << MDMA_CCR_EN_Pos)                   /*!< 0x00000001 */

+#define MDMA_CCR_EN               MDMA_CCR_EN_Msk                              /*!< Channel enable / flag channel ready when read low */

+#define MDMA_CCR_TEIE_Pos         (1U)

+#define MDMA_CCR_TEIE_Msk         (0x1UL << MDMA_CCR_TEIE_Pos)                 /*!< 0x00000002 */

+#define MDMA_CCR_TEIE             MDMA_CCR_TEIE_Msk                            /*!< Transfer error interrupt enable */

+#define MDMA_CCR_CTCIE_Pos        (2U)

+#define MDMA_CCR_CTCIE_Msk        (0x1UL << MDMA_CCR_CTCIE_Pos)                /*!< 0x00000004 */

+#define MDMA_CCR_CTCIE            MDMA_CCR_CTCIE_Msk                           /*!< Channel Transfer Complete interrupt enable */

+#define MDMA_CCR_BRTIE_Pos        (3U)

+#define MDMA_CCR_BRTIE_Msk        (0x1UL << MDMA_CCR_BRTIE_Pos)                /*!< 0x00000008 */

+#define MDMA_CCR_BRTIE            MDMA_CCR_BRTIE_Msk                           /*!< Block Repeat transfer interrupt enable */

+#define MDMA_CCR_BTIE_Pos         (4U)

+#define MDMA_CCR_BTIE_Msk         (0x1UL << MDMA_CCR_BTIE_Pos)                 /*!< 0x00000010 */

+#define MDMA_CCR_BTIE             MDMA_CCR_BTIE_Msk                            /*!< Block Transfer interrupt enable */

+#define MDMA_CCR_TCIE_Pos         (5U)

+#define MDMA_CCR_TCIE_Msk         (0x1UL << MDMA_CCR_TCIE_Pos)                 /*!< 0x00000020 */

+#define MDMA_CCR_TCIE             MDMA_CCR_TCIE_Msk                            /*!< buffer Transfer Complete interrupt enable */

+#define MDMA_CCR_PL_Pos           (6U)

+#define MDMA_CCR_PL_Msk           (0x3UL << MDMA_CCR_PL_Pos)                   /*!< 0x000000C0 */

+#define MDMA_CCR_PL               MDMA_CCR_PL_Msk                              /*!< Priority level */

+#define MDMA_CCR_PL_0             (0x1UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000040 */

+#define MDMA_CCR_PL_1             (0x2UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000080 */

+#define MDMA_CCR_BEX_Pos          (12U)

+#define MDMA_CCR_BEX_Msk          (0x1UL << MDMA_CCR_BEX_Pos)                  /*!< 0x00001000 */

+#define MDMA_CCR_BEX              MDMA_CCR_BEX_Msk                             /*!< Byte Endianess eXchange */

+#define MDMA_CCR_HEX_Pos          (13U)

+#define MDMA_CCR_HEX_Msk          (0x1UL << MDMA_CCR_HEX_Pos)                  /*!< 0x00002000 */

+#define MDMA_CCR_HEX              MDMA_CCR_HEX_Msk                             /*!< Half word Endianess eXchange */

+#define MDMA_CCR_WEX_Pos          (14U)

+#define MDMA_CCR_WEX_Msk          (0x1UL << MDMA_CCR_WEX_Pos)                  /*!< 0x00004000 */

+#define MDMA_CCR_WEX              MDMA_CCR_WEX_Msk                             /*!< Word Endianess eXchange */

+#define MDMA_CCR_SWRQ_Pos         (16U)

+#define MDMA_CCR_SWRQ_Msk         (0x1UL << MDMA_CCR_SWRQ_Pos)                 /*!< 0x00010000 */

+#define MDMA_CCR_SWRQ             MDMA_CCR_SWRQ_Msk                            /*!< SW ReQuest */

+

+/********************  Bit definition for MDMA_CxTCR register  ****************/

+#define MDMA_CTCR_SINC_Pos        (0U)

+#define MDMA_CTCR_SINC_Msk        (0x3UL << MDMA_CTCR_SINC_Pos)                /*!< 0x00000003 */

+#define MDMA_CTCR_SINC            MDMA_CTCR_SINC_Msk                           /*!< Source increment mode */

+#define MDMA_CTCR_SINC_0          (0x1UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000001 */

+#define MDMA_CTCR_SINC_1          (0x2UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000002 */

+#define MDMA_CTCR_DINC_Pos        (2U)

+#define MDMA_CTCR_DINC_Msk        (0x3UL << MDMA_CTCR_DINC_Pos)                /*!< 0x0000000C */

+#define MDMA_CTCR_DINC            MDMA_CTCR_DINC_Msk                           /*!< Source increment mode */

+#define MDMA_CTCR_DINC_0          (0x1UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000004 */

+#define MDMA_CTCR_DINC_1          (0x2UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000008 */

+#define MDMA_CTCR_SSIZE_Pos       (4U)

+#define MDMA_CTCR_SSIZE_Msk       (0x3UL << MDMA_CTCR_SSIZE_Pos)               /*!< 0x00000030 */

+#define MDMA_CTCR_SSIZE           MDMA_CTCR_SSIZE_Msk                          /*!< Source data size */

+#define MDMA_CTCR_SSIZE_0         (0x1UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000010 */

+#define MDMA_CTCR_SSIZE_1         (0x2UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000020 */

+#define MDMA_CTCR_DSIZE_Pos       (6U)

+#define MDMA_CTCR_DSIZE_Msk       (0x3UL << MDMA_CTCR_DSIZE_Pos)               /*!< 0x000000C0 */

+#define MDMA_CTCR_DSIZE           MDMA_CTCR_DSIZE_Msk                          /*!< Destination data size */

+#define MDMA_CTCR_DSIZE_0         (0x1UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000040 */

+#define MDMA_CTCR_DSIZE_1         (0x2UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000080 */

+#define MDMA_CTCR_SINCOS_Pos      (8U)

+#define MDMA_CTCR_SINCOS_Msk      (0x3UL << MDMA_CTCR_SINCOS_Pos)              /*!< 0x00000300 */

+#define MDMA_CTCR_SINCOS          MDMA_CTCR_SINCOS_Msk                         /*!< Source increment offset size */

+#define MDMA_CTCR_SINCOS_0        (0x1UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000100 */

+#define MDMA_CTCR_SINCOS_1        (0x2UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000200 */

+#define MDMA_CTCR_DINCOS_Pos      (10U)

+#define MDMA_CTCR_DINCOS_Msk      (0x3UL << MDMA_CTCR_DINCOS_Pos)              /*!< 0x00000C00 */

+#define MDMA_CTCR_DINCOS          MDMA_CTCR_DINCOS_Msk                         /*!< Destination increment offset size */

+#define MDMA_CTCR_DINCOS_0        (0x1UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000400 */

+#define MDMA_CTCR_DINCOS_1        (0x2UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000800 */

+#define MDMA_CTCR_SBURST_Pos      (12U)

+#define MDMA_CTCR_SBURST_Msk      (0x7UL << MDMA_CTCR_SBURST_Pos)              /*!< 0x00007000 */

+#define MDMA_CTCR_SBURST          MDMA_CTCR_SBURST_Msk                         /*!< Source burst transfer configuration */

+#define MDMA_CTCR_SBURST_0        (0x1UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00001000 */

+#define MDMA_CTCR_SBURST_1        (0x2UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00002000 */

+#define MDMA_CTCR_SBURST_2        (0x4UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00004000 */

+#define MDMA_CTCR_DBURST_Pos      (15U)

+#define MDMA_CTCR_DBURST_Msk      (0x7UL << MDMA_CTCR_DBURST_Pos)              /*!< 0x00038000 */

+#define MDMA_CTCR_DBURST          MDMA_CTCR_DBURST_Msk                         /*!< Destination burst transfer configuration */

+#define MDMA_CTCR_DBURST_0        (0x1UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00008000 */

+#define MDMA_CTCR_DBURST_1        (0x2UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00010000 */

+#define MDMA_CTCR_DBURST_2        (0x4UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00020000 */

+#define MDMA_CTCR_TLEN_Pos        (18U)

+#define MDMA_CTCR_TLEN_Msk        (0x7FUL << MDMA_CTCR_TLEN_Pos)               /*!< 0x01FC0000 */

+#define MDMA_CTCR_TLEN            MDMA_CTCR_TLEN_Msk                           /*!< buffer Transfer Length (number of bytes - 1) */

+#define MDMA_CTCR_PKE_Pos         (25U)

+#define MDMA_CTCR_PKE_Msk         (0x1UL << MDMA_CTCR_PKE_Pos)                 /*!< 0x02000000 */

+#define MDMA_CTCR_PKE             MDMA_CTCR_PKE_Msk                            /*!< PacK Enable */

+#define MDMA_CTCR_PAM_Pos         (26U)

+#define MDMA_CTCR_PAM_Msk         (0x3UL << MDMA_CTCR_PAM_Pos)                 /*!< 0x0C000000 */

+#define MDMA_CTCR_PAM             MDMA_CTCR_PAM_Msk                            /*!< Padding/Alignement Mode */

+#define MDMA_CTCR_PAM_0           (0x1UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x4000000 */

+#define MDMA_CTCR_PAM_1           (0x2UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x8000000 */

+#define MDMA_CTCR_TRGM_Pos        (28U)

+#define MDMA_CTCR_TRGM_Msk        (0x3UL << MDMA_CTCR_TRGM_Pos)                /*!< 0x30000000 */

+#define MDMA_CTCR_TRGM            MDMA_CTCR_TRGM_Msk                           /*!< Trigger Mode */

+#define MDMA_CTCR_TRGM_0          (0x1UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x10000000 */

+#define MDMA_CTCR_TRGM_1          (0x2UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x20000000 */

+#define MDMA_CTCR_SWRM_Pos        (30U)

+#define MDMA_CTCR_SWRM_Msk        (0x1UL << MDMA_CTCR_SWRM_Pos)                /*!< 0x40000000 */

+#define MDMA_CTCR_SWRM            MDMA_CTCR_SWRM_Msk                           /*!< SW Request Mode */

+#define MDMA_CTCR_BWM_Pos         (31U)

+#define MDMA_CTCR_BWM_Msk         (0x1UL << MDMA_CTCR_BWM_Pos)                 /*!< 0x80000000 */

+#define MDMA_CTCR_BWM             MDMA_CTCR_BWM_Msk                            /*!< Bufferable Write Mode */

+

+/********************  Bit definition for MDMA_CxBNDTR register  ****************/

+#define MDMA_CBNDTR_BNDT_Pos      (0U)

+#define MDMA_CBNDTR_BNDT_Msk      (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos)          /*!< 0x0001FFFF */

+#define MDMA_CBNDTR_BNDT          MDMA_CBNDTR_BNDT_Msk                         /*!< Block Number of data bytes to transfer */

+#define MDMA_CBNDTR_BRSUM_Pos     (18U)

+#define MDMA_CBNDTR_BRSUM_Msk     (0x1UL << MDMA_CBNDTR_BRSUM_Pos)             /*!< 0x00040000 */

+#define MDMA_CBNDTR_BRSUM         MDMA_CBNDTR_BRSUM_Msk                        /*!< Block Repeat Source address Update Mode */

+#define MDMA_CBNDTR_BRDUM_Pos     (19U)

+#define MDMA_CBNDTR_BRDUM_Msk     (0x1UL << MDMA_CBNDTR_BRDUM_Pos)             /*!< 0x00080000 */

+#define MDMA_CBNDTR_BRDUM         MDMA_CBNDTR_BRDUM_Msk                        /*!< Block Repeat Destination address Update Mode */

+#define MDMA_CBNDTR_BRC_Pos       (20U)

+#define MDMA_CBNDTR_BRC_Msk       (0xFFFUL << MDMA_CBNDTR_BRC_Pos)             /*!< 0xFFF00000 */

+#define MDMA_CBNDTR_BRC           MDMA_CBNDTR_BRC_Msk                          /*!< Block Repeat Count */

+

+/********************  Bit definition for MDMA_CxSAR register  ****************/

+#define MDMA_CSAR_SAR_Pos         (0U)

+#define MDMA_CSAR_SAR_Msk         (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CSAR_SAR             MDMA_CSAR_SAR_Msk                            /*!< Source address */

+

+/********************  Bit definition for MDMA_CxDAR register  ****************/

+#define MDMA_CDAR_DAR_Pos         (0U)

+#define MDMA_CDAR_DAR_Msk         (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CDAR_DAR             MDMA_CDAR_DAR_Msk                            /*!< Destination address */

+

+/********************  Bit definition for MDMA_CxBRUR  ************************/

+#define MDMA_CBRUR_SUV_Pos        (0U)

+#define MDMA_CBRUR_SUV_Msk        (0xFFFFUL << MDMA_CBRUR_SUV_Pos)             /*!< 0x0000FFFF */

+#define MDMA_CBRUR_SUV            MDMA_CBRUR_SUV_Msk                           /*!< Source address Update Value */

+#define MDMA_CBRUR_DUV_Pos        (16U)

+#define MDMA_CBRUR_DUV_Msk        (0xFFFFUL << MDMA_CBRUR_DUV_Pos)             /*!< 0xFFFF0000 */

+#define MDMA_CBRUR_DUV            MDMA_CBRUR_DUV_Msk                           /*!< Destination address Update Value */

+

+/********************  Bit definition for MDMA_CxLAR  *************************/

+#define MDMA_CLAR_LAR_Pos         (0U)

+#define MDMA_CLAR_LAR_Msk         (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CLAR_LAR             MDMA_CLAR_LAR_Msk                            /*!< Link Address Register */

+

+/********************  Bit definition for MDMA_CxTBR)  ************************/

+#define MDMA_CTBR_TSEL_Pos        (0U)

+#define MDMA_CTBR_TSEL_Msk        (0xFFUL << MDMA_CTBR_TSEL_Pos)               /*!< 0x000000FF */

+#define MDMA_CTBR_TSEL            MDMA_CTBR_TSEL_Msk                           /*!< Trigger SELection */

+#define MDMA_CTBR_SBUS_Pos        (16U)

+#define MDMA_CTBR_SBUS_Msk        (0x1UL << MDMA_CTBR_SBUS_Pos)                /*!< 0x00010000 */

+#define MDMA_CTBR_SBUS            MDMA_CTBR_SBUS_Msk                           /*!< Source BUS select */

+#define MDMA_CTBR_DBUS_Pos        (17U)

+#define MDMA_CTBR_DBUS_Msk        (0x1UL << MDMA_CTBR_DBUS_Pos)                /*!< 0x00020000 */

+#define MDMA_CTBR_DBUS            MDMA_CTBR_DBUS_Msk                           /*!< Destination BUS select */

+

+/********************  Bit definition for MDMA_CxMAR)  ************************/

+#define MDMA_CMAR_MAR_Pos         (0U)

+#define MDMA_CMAR_MAR_Msk         (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CMAR_MAR             MDMA_CMAR_MAR_Msk                            /*!< Mask address */

+

+/********************  Bit definition for MDMA_CxMDR)  ************************/

+#define MDMA_CMDR_MDR_Pos         (0U)

+#define MDMA_CMDR_MDR_Msk         (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CMDR_MDR             MDMA_CMDR_MDR_Msk                            /*!< Mask Data */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Operational Amplifier (OPAMP)                      */

+/*                                                                            */

+/******************************************************************************/

+/*********************  Bit definition for OPAMPx_CSR register  ***************/

+#define OPAMP_CSR_OPAMPxEN_Pos           (0U)

+#define OPAMP_CSR_OPAMPxEN_Msk           (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)     /*!< 0x00000001 */

+#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */

+#define OPAMP_CSR_FORCEVP_Pos            (1U)

+#define OPAMP_CSR_FORCEVP_Msk            (0x1UL << OPAMP_CSR_FORCEVP_Pos)      /*!< 0x00000002 */

+#define OPAMP_CSR_FORCEVP                OPAMP_CSR_FORCEVP_Msk                 /*!< Force internal reference on VP */

+

+#define OPAMP_CSR_VPSEL_Pos              (2U)

+#define OPAMP_CSR_VPSEL_Msk              (0x3UL << OPAMP_CSR_VPSEL_Pos)        /*!< 0x0000000C */

+#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */

+#define OPAMP_CSR_VPSEL_0                (0x1UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000004 */

+#define OPAMP_CSR_VPSEL_1                (0x2UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000008 */

+

+#define OPAMP_CSR_VMSEL_Pos              (5U)

+#define OPAMP_CSR_VMSEL_Msk              (0x3UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000060 */

+#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */

+#define OPAMP_CSR_VMSEL_0                (0x1UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000020 */

+#define OPAMP_CSR_VMSEL_1                (0x2UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000040 */

+

+#define OPAMP_CSR_OPAHSM_Pos             (8U)

+#define OPAMP_CSR_OPAHSM_Msk             (0x1UL << OPAMP_CSR_OPAHSM_Pos)       /*!< 0x00000100 */

+#define OPAMP_CSR_OPAHSM                 OPAMP_CSR_OPAHSM_Msk                  /*!< Operational amplifier high speed mode */

+#define OPAMP_CSR_CALON_Pos              (11U)

+#define OPAMP_CSR_CALON_Msk              (0x1UL << OPAMP_CSR_CALON_Pos)        /*!< 0x00000800 */

+#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */

+

+#define OPAMP_CSR_CALSEL_Pos             (12U)

+#define OPAMP_CSR_CALSEL_Msk             (0x3UL << OPAMP_CSR_CALSEL_Pos)       /*!< 0x00003000 */

+#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */

+#define OPAMP_CSR_CALSEL_0               (0x1UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00001000 */

+#define OPAMP_CSR_CALSEL_1               (0x2UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */

+

+#define OPAMP_CSR_PGGAIN_Pos             (14U)

+#define OPAMP_CSR_PGGAIN_Msk             (0xFUL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x0003C000 */

+#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */

+#define OPAMP_CSR_PGGAIN_0               (0x1UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00004000 */

+#define OPAMP_CSR_PGGAIN_1               (0x2UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00008000 */

+#define OPAMP_CSR_PGGAIN_2               (0x4UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00010000 */

+#define OPAMP_CSR_PGGAIN_3               (0x8UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00020000 */

+

+#define OPAMP_CSR_USERTRIM_Pos           (18U)

+#define OPAMP_CSR_USERTRIM_Msk           (0x1UL << OPAMP_CSR_USERTRIM_Pos)     /*!< 0x00040000 */

+#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */

+#define OPAMP_CSR_TSTREF_Pos             (29U)

+#define OPAMP_CSR_TSTREF_Msk             (0x1UL << OPAMP_CSR_TSTREF_Pos)       /*!< 0x20000000 */

+#define OPAMP_CSR_TSTREF                 OPAMP_CSR_TSTREF_Msk                  /*!< OpAmp calibration reference voltage output control */

+#define OPAMP_CSR_CALOUT_Pos             (30U)

+#define OPAMP_CSR_CALOUT_Msk             (0x1UL << OPAMP_CSR_CALOUT_Pos)       /*!< 0x40000000 */

+#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier calibration output */

+

+/*********************  Bit definition for OPAMP1_CSR register  ***************/

+#define OPAMP1_CSR_OPAEN_Pos              (0U)

+#define OPAMP1_CSR_OPAEN_Msk              (0x1UL << OPAMP1_CSR_OPAEN_Pos)      /*!< 0x00000001 */

+#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */

+#define OPAMP1_CSR_FORCEVP_Pos            (1U)

+#define OPAMP1_CSR_FORCEVP_Msk            (0x1UL << OPAMP1_CSR_FORCEVP_Pos)    /*!< 0x00000002 */

+#define OPAMP1_CSR_FORCEVP                OPAMP1_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */

+

+#define OPAMP1_CSR_VPSEL_Pos              (2U)

+#define OPAMP1_CSR_VPSEL_Msk              (0x3UL << OPAMP1_CSR_VPSEL_Pos)      /*!< 0x0000000C */

+#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */

+#define OPAMP1_CSR_VPSEL_0                (0x1UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000004 */

+#define OPAMP1_CSR_VPSEL_1                (0x2UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000008 */

+

+#define OPAMP1_CSR_VMSEL_Pos              (5U)

+#define OPAMP1_CSR_VMSEL_Msk              (0x3UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000060 */

+#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */

+#define OPAMP1_CSR_VMSEL_0                (0x1UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000020 */

+#define OPAMP1_CSR_VMSEL_1                (0x2UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000040 */

+

+#define OPAMP1_CSR_OPAHSM_Pos             (8U)

+#define OPAMP1_CSR_OPAHSM_Msk             (0x1UL << OPAMP1_CSR_OPAHSM_Pos)     /*!< 0x00000100 */

+#define OPAMP1_CSR_OPAHSM                 OPAMP1_CSR_OPAHSM_Msk                /*!< Operational amplifier1 high speed mode */

+#define OPAMP1_CSR_CALON_Pos              (11U)

+#define OPAMP1_CSR_CALON_Msk              (0x1UL << OPAMP1_CSR_CALON_Pos)      /*!< 0x00000800 */

+#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */

+

+#define OPAMP1_CSR_CALSEL_Pos             (12U)

+#define OPAMP1_CSR_CALSEL_Msk             (0x3UL << OPAMP1_CSR_CALSEL_Pos)     /*!< 0x00003000 */

+#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */

+#define OPAMP1_CSR_CALSEL_0               (0x1UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00001000 */

+#define OPAMP1_CSR_CALSEL_1               (0x2UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */

+

+#define OPAMP1_CSR_PGGAIN_Pos             (14U)

+#define OPAMP1_CSR_PGGAIN_Msk             (0xFUL << OPAMP1_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */

+#define OPAMP1_CSR_PGGAIN                 OPAMP1_CSR_PGGAIN_Msk                /*!< Operational amplifier1 Programmable amplifier gain value */

+#define OPAMP1_CSR_PGGAIN_0               (0x1UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00004000 */

+#define OPAMP1_CSR_PGGAIN_1               (0x2UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00008000 */

+#define OPAMP1_CSR_PGGAIN_2               (0x4UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00010000 */

+#define OPAMP1_CSR_PGGAIN_3               (0x8UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00020000 */

+

+#define OPAMP1_CSR_USERTRIM_Pos           (18U)

+#define OPAMP1_CSR_USERTRIM_Msk           (0x1UL << OPAMP1_CSR_USERTRIM_Pos)   /*!< 0x00040000 */

+#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */

+#define OPAMP1_CSR_TSTREF_Pos             (29U)

+#define OPAMP1_CSR_TSTREF_Msk             (0x1UL << OPAMP1_CSR_TSTREF_Pos)     /*!< 0x20000000 */

+#define OPAMP1_CSR_TSTREF                 OPAMP1_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */

+#define OPAMP1_CSR_CALOUT_Pos             (30U)

+#define OPAMP1_CSR_CALOUT_Msk             (0x1UL << OPAMP1_CSR_CALOUT_Pos)     /*!< 0x40000000 */

+#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */

+

+/*********************  Bit definition for OPAMP2_CSR register  ***************/

+#define OPAMP2_CSR_OPAEN_Pos              (0U)

+#define OPAMP2_CSR_OPAEN_Msk              (0x1UL << OPAMP2_CSR_OPAEN_Pos)      /*!< 0x00000001 */

+#define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */

+#define OPAMP2_CSR_FORCEVP_Pos            (1U)

+#define OPAMP2_CSR_FORCEVP_Msk            (0x1UL << OPAMP2_CSR_FORCEVP_Pos)    /*!< 0x00000002 */

+#define OPAMP2_CSR_FORCEVP                OPAMP2_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */

+

+#define OPAMP2_CSR_VPSEL_Pos              (2U)

+#define OPAMP2_CSR_VPSEL_Msk              (0x3UL << OPAMP2_CSR_VPSEL_Pos)      /*!< 0x0000000C */

+#define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */

+#define OPAMP2_CSR_VPSEL_0                (0x1UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000004 */

+#define OPAMP2_CSR_VPSEL_1                (0x2UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000008 */

+

+#define OPAMP2_CSR_VMSEL_Pos              (5U)

+#define OPAMP2_CSR_VMSEL_Msk              (0x3UL << OPAMP2_CSR_VMSEL_Pos)      /*!< 0x00000060 */

+#define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */

+#define OPAMP2_CSR_VMSEL_0                (0x1UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000020 */

+#define OPAMP2_CSR_VMSEL_1                (0x2UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000040 */

+

+#define OPAMP2_CSR_OPAHSM_Pos             (8U)

+#define OPAMP2_CSR_OPAHSM_Msk             (0x1UL << OPAMP2_CSR_OPAHSM_Pos)     /*!< 0x00000100 */

+#define OPAMP2_CSR_OPAHSM                 OPAMP2_CSR_OPAHSM_Msk                /*!< Operational amplifier2 high speed mode */

+#define OPAMP2_CSR_CALON_Pos              (11U)

+#define OPAMP2_CSR_CALON_Msk              (0x1UL << OPAMP2_CSR_CALON_Pos)      /*!< 0x00000800 */

+#define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */

+

+#define OPAMP2_CSR_CALSEL_Pos             (12U)

+#define OPAMP2_CSR_CALSEL_Msk             (0x3UL << OPAMP2_CSR_CALSEL_Pos)     /*!< 0x00003000 */

+#define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */

+#define OPAMP2_CSR_CALSEL_0               (0x1UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00001000 */

+#define OPAMP2_CSR_CALSEL_1               (0x2UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */

+

+#define OPAMP2_CSR_PGGAIN_Pos             (14U)

+#define OPAMP2_CSR_PGGAIN_Msk             (0xFUL << OPAMP2_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */

+#define OPAMP2_CSR_PGGAIN                 OPAMP2_CSR_PGGAIN_Msk                /*!< Operational amplifier2 Programmable amplifier gain value */

+#define OPAMP2_CSR_PGGAIN_0               (0x1UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00004000 */

+#define OPAMP2_CSR_PGGAIN_1               (0x2UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00008000 */

+#define OPAMP2_CSR_PGGAIN_2               (0x4UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00010000 */

+#define OPAMP2_CSR_PGGAIN_3               (0x8UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00020000 */

+

+#define OPAMP2_CSR_USERTRIM_Pos           (18U)

+#define OPAMP2_CSR_USERTRIM_Msk           (0x1UL << OPAMP2_CSR_USERTRIM_Pos)   /*!< 0x00040000 */

+#define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */

+#define OPAMP2_CSR_TSTREF_Pos             (29U)

+#define OPAMP2_CSR_TSTREF_Msk             (0x1UL << OPAMP2_CSR_TSTREF_Pos)     /*!< 0x20000000 */

+#define OPAMP2_CSR_TSTREF                 OPAMP2_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */

+#define OPAMP2_CSR_CALOUT_Pos             (30U)

+#define OPAMP2_CSR_CALOUT_Msk             (0x1UL << OPAMP2_CSR_CALOUT_Pos)     /*!< 0x40000000 */

+#define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */

+

+/*******************  Bit definition for OPAMP_OTR register  ******************/

+#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */

+#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP1_OTR register  ******************/

+#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */

+#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP2_OTR register  ******************/

+#define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */

+#define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP_HSOTR register  ****************/

+#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP_HSOTR_TRIMHSOFFSETN        OPAMP_HSOTR_TRIMHSOFFSETN_Msk         /*!< Trim for NMOS differential pairs */

+#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP_HSOTR_TRIMHSOFFSETP        OPAMP_HSOTR_TRIMHSOFFSETP_Msk         /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP1_HSOTR register  ****************/

+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP1_HSOTR_TRIMHSOFFSETN        OPAMP1_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */

+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP1_HSOTR_TRIMHSOFFSETP        OPAMP1_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP2_HSOTR register  ****************/

+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP2_HSOTR_TRIMHSOFFSETN        OPAMP2_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */

+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP2_HSOTR_TRIMHSOFFSETP        OPAMP2_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             Power Control                                  */

+/*                                                                            */

+/******************************************************************************/

+/*************************  NUMBER OF POWER DOMAINS  **************************/

+#define POWER_DOMAINS_NUMBER           3U                                      /*!< 3 Domains */

+

+/********************  Bit definition for PWR_CR1 register  *******************/

+#define PWR_CR1_ALS_Pos                (17U)

+#define PWR_CR1_ALS_Msk                (0x3UL << PWR_CR1_ALS_Pos)              /*!< 0x00060000 */

+#define PWR_CR1_ALS                    PWR_CR1_ALS_Msk                         /*!< Analog Voltage Detector level selection */

+#define PWR_CR1_ALS_0                  (0x1UL << PWR_CR1_ALS_Pos)              /*!< 0x00020000 */

+#define PWR_CR1_ALS_1                  (0x2UL << PWR_CR1_ALS_Pos)              /*!< 0x00040000 */

+#define PWR_CR1_AVDEN_Pos              (16U)

+#define PWR_CR1_AVDEN_Msk              (0x1UL << PWR_CR1_AVDEN_Pos)            /*!< 0x00010000 */

+#define PWR_CR1_AVDEN                  PWR_CR1_AVDEN_Msk                       /*!< Analog Voltage Detector Enable */

+#define PWR_CR1_SVOS_Pos               (14U)

+#define PWR_CR1_SVOS_Msk               (0x3UL << PWR_CR1_SVOS_Pos)             /*!< 0x0000C000 */

+#define PWR_CR1_SVOS                   PWR_CR1_SVOS_Msk                        /*!< System STOP mode Voltage Scaling selection */

+#define PWR_CR1_SVOS_0                 (0x1UL << PWR_CR1_SVOS_Pos)             /*!< 0x00004000 */

+#define PWR_CR1_SVOS_1                 (0x2UL << PWR_CR1_SVOS_Pos)             /*!< 0x00008000 */

+#define PWR_CR1_FLPS_Pos               (9U)

+#define PWR_CR1_FLPS_Msk               (0x1UL << PWR_CR1_FLPS_Pos)             /*!< 0x00000200 */

+#define PWR_CR1_FLPS                   PWR_CR1_FLPS_Msk                        /*!< Flash low power mode in DSTOP */

+#define PWR_CR1_DBP_Pos                (8U)

+#define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */

+#define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable Back-up domain Protection */

+#define PWR_CR1_PLS_Pos                (5U)

+#define PWR_CR1_PLS_Msk                (0x7UL << PWR_CR1_PLS_Pos)              /*!< 0x000000E0 */

+#define PWR_CR1_PLS                    PWR_CR1_PLS_Msk                         /*!< Programmable Voltage Detector level selection */

+#define PWR_CR1_PLS_0                  (0x1UL << PWR_CR1_PLS_Pos)              /*!< 0x00000020 */

+#define PWR_CR1_PLS_1                  (0x2UL << PWR_CR1_PLS_Pos)              /*!< 0x00000040 */

+#define PWR_CR1_PLS_2                  (0x4UL << PWR_CR1_PLS_Pos)              /*!< 0x00000080 */

+#define PWR_CR1_PVDEN_Pos              (4U)

+#define PWR_CR1_PVDEN_Msk              (0x1UL << PWR_CR1_PVDEN_Pos)            /*!< 0x00000010 */

+#define PWR_CR1_PVDEN                  PWR_CR1_PVDEN_Msk                       /*!< Programmable Voltage detector enable */

+#define PWR_CR1_LPDS_Pos               (0U)

+#define PWR_CR1_LPDS_Msk               (0x1UL << PWR_CR1_LPDS_Pos)             /*!< 0x00000001 */

+#define PWR_CR1_LPDS                   PWR_CR1_LPDS_Msk                        /*!< Low Power Deepsleep with SVOS3 */

+

+/*!< PVD level configuration */

+#define PWR_CR1_PLS_LEV0               (0UL)                                   /*!< PVD level 0 */

+#define PWR_CR1_PLS_LEV1_Pos           (5U)

+#define PWR_CR1_PLS_LEV1_Msk           (0x1UL << PWR_CR1_PLS_LEV1_Pos)         /*!< 0x00000020 */

+#define PWR_CR1_PLS_LEV1               PWR_CR1_PLS_LEV1_Msk                    /*!< PVD level 1 */

+#define PWR_CR1_PLS_LEV2_Pos           (6U)

+#define PWR_CR1_PLS_LEV2_Msk           (0x1UL << PWR_CR1_PLS_LEV2_Pos)         /*!< 0x00000040 */

+#define PWR_CR1_PLS_LEV2               PWR_CR1_PLS_LEV2_Msk                    /*!< PVD level 2 */

+#define PWR_CR1_PLS_LEV3_Pos           (5U)

+#define PWR_CR1_PLS_LEV3_Msk           (0x3UL << PWR_CR1_PLS_LEV3_Pos)         /*!< 0x00000060 */

+#define PWR_CR1_PLS_LEV3               PWR_CR1_PLS_LEV3_Msk                    /*!< PVD level 3 */

+#define PWR_CR1_PLS_LEV4_Pos           (7U)

+#define PWR_CR1_PLS_LEV4_Msk           (0x1UL << PWR_CR1_PLS_LEV4_Pos)         /*!< 0x00000080 */

+#define PWR_CR1_PLS_LEV4               PWR_CR1_PLS_LEV4_Msk                    /*!< PVD level 4 */

+#define PWR_CR1_PLS_LEV5_Pos           (5U)

+#define PWR_CR1_PLS_LEV5_Msk           (0x5UL << PWR_CR1_PLS_LEV5_Pos)         /*!< 0x000000A0 */

+#define PWR_CR1_PLS_LEV5               PWR_CR1_PLS_LEV5_Msk                    /*!< PVD level 5 */

+#define PWR_CR1_PLS_LEV6_Pos           (6U)

+#define PWR_CR1_PLS_LEV6_Msk           (0x3UL << PWR_CR1_PLS_LEV6_Pos)         /*!< 0x000000C0 */

+#define PWR_CR1_PLS_LEV6               PWR_CR1_PLS_LEV6_Msk                    /*!< PVD level 6 */

+#define PWR_CR1_PLS_LEV7_Pos           (5U)

+#define PWR_CR1_PLS_LEV7_Msk           (0x7UL << PWR_CR1_PLS_LEV7_Pos)         /*!< 0x000000E0 */

+#define PWR_CR1_PLS_LEV7               PWR_CR1_PLS_LEV7_Msk                    /*!< PVD level 7 */

+

+/*!< AVD level configuration */

+#define PWR_CR1_ALS_LEV0               (0UL)                                   /*!< AVD level 0 */

+#define PWR_CR1_ALS_LEV1_Pos           (17U)

+#define PWR_CR1_ALS_LEV1_Msk           (0x1UL << PWR_CR1_ALS_LEV1_Pos)         /*!< 0x00020000 */

+#define PWR_CR1_ALS_LEV1               PWR_CR1_ALS_LEV1_Msk                    /*!< AVD level 1 */

+#define PWR_CR1_ALS_LEV2_Pos           (18U)

+#define PWR_CR1_ALS_LEV2_Msk           (0x1UL << PWR_CR1_ALS_LEV2_Pos)         /*!< 0x00040000 */

+#define PWR_CR1_ALS_LEV2               PWR_CR1_ALS_LEV2_Msk                    /*!< AVD level 2 */

+#define PWR_CR1_ALS_LEV3_Pos           (17U)

+#define PWR_CR1_ALS_LEV3_Msk           (0x3UL << PWR_CR1_ALS_LEV3_Pos)         /*!< 0x00060000 */

+#define PWR_CR1_ALS_LEV3               PWR_CR1_ALS_LEV3_Msk                    /*!< AVD level 3 */

+

+/********************  Bit definition for PWR_CSR1 register  ******************/

+#define PWR_CSR1_AVDO_Pos              (16U)

+#define PWR_CSR1_AVDO_Msk              (0x1UL << PWR_CSR1_AVDO_Pos)            /*!< 0x00010000 */

+#define PWR_CSR1_AVDO                  PWR_CSR1_AVDO_Msk                       /*!< Analog Voltage Detect Output */

+#define PWR_CSR1_ACTVOS_Pos            (14U)

+#define PWR_CSR1_ACTVOS_Msk            (0x3UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x0000C000 */

+#define PWR_CSR1_ACTVOS                PWR_CSR1_ACTVOS_Msk                     /*!< Current actual used VOS for VDD11 Voltage Scaling */

+#define PWR_CSR1_ACTVOS_0              (0x1UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00004000 */

+#define PWR_CSR1_ACTVOS_1              (0x2UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00008000 */

+#define PWR_CSR1_ACTVOSRDY_Pos         (13U)

+#define PWR_CSR1_ACTVOSRDY_Msk         (0x1UL << PWR_CSR1_ACTVOSRDY_Pos)       /*!< 0x00002000 */

+#define PWR_CSR1_ACTVOSRDY             PWR_CSR1_ACTVOSRDY_Msk                  /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling  */

+#define PWR_CSR1_PVDO_Pos              (4U)

+#define PWR_CSR1_PVDO_Msk              (0x1UL << PWR_CSR1_PVDO_Pos)            /*!< 0x00000010 */

+#define PWR_CSR1_PVDO                  PWR_CSR1_PVDO_Msk                       /*!< Programmable Voltage Detect Output */

+

+/********************  Bit definition for PWR_CR2 register  *******************/

+#define PWR_CR2_TEMPH_Pos              (23U)

+#define PWR_CR2_TEMPH_Msk              (0x1UL << PWR_CR2_TEMPH_Pos)            /*!< 0x00800000 */

+#define PWR_CR2_TEMPH                  PWR_CR2_TEMPH_Msk                       /*!< Monitored temperature level above high threshold */

+#define PWR_CR2_TEMPL_Pos              (22U)

+#define PWR_CR2_TEMPL_Msk              (0x1UL << PWR_CR2_TEMPL_Pos)            /*!< 0x00400000 */

+#define PWR_CR2_TEMPL                  PWR_CR2_TEMPL_Msk                       /*!< Monitored temperature level above low threshold */

+#define PWR_CR2_VBATH_Pos              (21U)

+#define PWR_CR2_VBATH_Msk              (0x1UL << PWR_CR2_VBATH_Pos)            /*!< 0x00200000 */

+#define PWR_CR2_VBATH                  PWR_CR2_VBATH_Msk                       /*!< Monitored VBAT level above high threshold */

+#define PWR_CR2_VBATL_Pos              (20U)

+#define PWR_CR2_VBATL_Msk              (0x1UL << PWR_CR2_VBATL_Pos)            /*!< 0x00100000 */

+#define PWR_CR2_VBATL                  PWR_CR2_VBATL_Msk                       /*!< Monitored VBAT level above low threshold */

+#define PWR_CR2_BRRDY_Pos              (16U)

+#define PWR_CR2_BRRDY_Msk              (0x1UL << PWR_CR2_BRRDY_Pos)            /*!< 0x00010000 */

+#define PWR_CR2_BRRDY                  PWR_CR2_BRRDY_Msk                       /*!< Backup regulator ready */

+#define PWR_CR2_MONEN_Pos              (4U)

+#define PWR_CR2_MONEN_Msk              (0x1UL << PWR_CR2_MONEN_Pos)            /*!< 0x00000010 */

+#define PWR_CR2_MONEN                  PWR_CR2_MONEN_Msk                       /*!< VBAT and temperature monitoring enable */

+#define PWR_CR2_BREN_Pos               (0U)

+#define PWR_CR2_BREN_Msk               (0x1UL << PWR_CR2_BREN_Pos)             /*!< 0x00000001 */

+#define PWR_CR2_BREN                   PWR_CR2_BREN_Msk                        /*!< Backup regulator enable */

+

+/********************  Bit definition for PWR_CR3 register  *******************/

+#define PWR_CR3_USB33RDY_Pos           (26U)

+#define PWR_CR3_USB33RDY_Msk           (0x1UL << PWR_CR3_USB33RDY_Pos)         /*!< 0x04000000 */

+#define PWR_CR3_USB33RDY               PWR_CR3_USB33RDY_Msk                    /*!< USB supply ready */

+#define PWR_CR3_USBREGEN_Pos           (25U)

+#define PWR_CR3_USBREGEN_Msk           (0x1UL << PWR_CR3_USBREGEN_Pos)         /*!< 0x02000000 */

+#define PWR_CR3_USBREGEN               PWR_CR3_USBREGEN_Msk                    /*!< USB regulator enable */

+#define PWR_CR3_USB33DEN_Pos           (24U)

+#define PWR_CR3_USB33DEN_Msk           (0x1UL << PWR_CR3_USB33DEN_Pos)         /*!< 0x01000000 */

+#define PWR_CR3_USB33DEN               PWR_CR3_USB33DEN_Msk                    /*!< VDD33_USB voltage level detector enable */

+#define PWR_CR3_VBRS_Pos               (9U)

+#define PWR_CR3_VBRS_Msk               (0x1UL << PWR_CR3_VBRS_Pos)             /*!< 0x00000200 */

+#define PWR_CR3_VBRS                   PWR_CR3_VBRS_Msk                        /*!< VBAT charging resistor selection */

+#define PWR_CR3_VBE_Pos                (8U)

+#define PWR_CR3_VBE_Msk                (0x1UL << PWR_CR3_VBE_Pos)              /*!< 0x00000100 */

+#define PWR_CR3_VBE                    PWR_CR3_VBE_Msk                         /*!< VBAT charging enable */

+#define PWR_CR3_SCUEN_Pos              (2U)

+#define PWR_CR3_SCUEN_Msk              (0x1UL << PWR_CR3_SCUEN_Pos)            /*!< 0x00000004 */

+#define PWR_CR3_SCUEN                  PWR_CR3_SCUEN_Msk                       /*!< Supply configuration update enable */

+#define PWR_CR3_LDOEN_Pos              (1U)

+#define PWR_CR3_LDOEN_Msk              (0x1UL << PWR_CR3_LDOEN_Pos)            /*!< 0x00000002 */

+#define PWR_CR3_LDOEN                  PWR_CR3_LDOEN_Msk                       /*!< Low Drop Output regulator enable */

+#define PWR_CR3_BYPASS_Pos             (0U)

+#define PWR_CR3_BYPASS_Msk             (0x1UL << PWR_CR3_BYPASS_Pos)           /*!< 0x00000001 */

+#define PWR_CR3_BYPASS                 PWR_CR3_BYPASS_Msk                      /*!< Power Management Unit bypass */

+

+/********************  Bit definition for PWR_CPUCR register  *****************/

+#define PWR_CPUCR_RUN_D3_Pos           (11U)

+#define PWR_CPUCR_RUN_D3_Msk           (0x1UL << PWR_CPUCR_RUN_D3_Pos)         /*!< 0x00000800 */

+#define PWR_CPUCR_RUN_D3               PWR_CPUCR_RUN_D3_Msk                    /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */

+#define PWR_CPUCR_CSSF_Pos             (9U)

+#define PWR_CPUCR_CSSF_Msk             (0x1UL << PWR_CPUCR_CSSF_Pos)           /*!< 0x00000200 */

+#define PWR_CPUCR_CSSF                 PWR_CPUCR_CSSF_Msk                      /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */

+#define PWR_CPUCR_SBF_D2_Pos           (8U)

+#define PWR_CPUCR_SBF_D2_Msk           (0x1UL << PWR_CPUCR_SBF_D2_Pos)         /*!< 0x00000100 */

+#define PWR_CPUCR_SBF_D2               PWR_CPUCR_SBF_D2_Msk                    /*!< D2 domain DSTANDBY Flag */

+#define PWR_CPUCR_SBF_D1_Pos           (7U)

+#define PWR_CPUCR_SBF_D1_Msk           (0x1UL << PWR_CPUCR_SBF_D1_Pos)         /*!< 0x00000080 */

+#define PWR_CPUCR_SBF_D1               PWR_CPUCR_SBF_D1_Msk                    /*!< D1 domain DSTANDBY Flag */

+#define PWR_CPUCR_SBF_Pos              (6U)

+#define PWR_CPUCR_SBF_Msk              (0x1UL << PWR_CPUCR_SBF_Pos)            /*!< 0x00000040 */

+#define PWR_CPUCR_SBF                  PWR_CPUCR_SBF_Msk                       /*!< System STANDBY Flag */

+#define PWR_CPUCR_STOPF_Pos            (5U)

+#define PWR_CPUCR_STOPF_Msk            (0x1UL << PWR_CPUCR_STOPF_Pos)          /*!< 0x00000020 */

+#define PWR_CPUCR_STOPF                PWR_CPUCR_STOPF_Msk                     /*!< STOP Flag */

+#define PWR_CPUCR_PDDS_D3_Pos          (2U)

+#define PWR_CPUCR_PDDS_D3_Msk          (0x1UL << PWR_CPUCR_PDDS_D3_Pos)        /*!< 0x00000004 */

+#define PWR_CPUCR_PDDS_D3              PWR_CPUCR_PDDS_D3_Msk                   /*!< System D3 domain Power Down Deepsleep */

+#define PWR_CPUCR_PDDS_D2_Pos          (1U)

+#define PWR_CPUCR_PDDS_D2_Msk          (0x1UL << PWR_CPUCR_PDDS_D2_Pos)        /*!< 0x00000002 */

+#define PWR_CPUCR_PDDS_D2              PWR_CPUCR_PDDS_D2_Msk                   /*!< D2 domain Power Down Deepsleep */

+#define PWR_CPUCR_PDDS_D1_Pos          (0U)

+#define PWR_CPUCR_PDDS_D1_Msk          (0x1UL << PWR_CPUCR_PDDS_D1_Pos)        /*!< 0x00000001 */

+#define PWR_CPUCR_PDDS_D1              PWR_CPUCR_PDDS_D1_Msk                   /*!< D1 domain Power Down Deepsleep selection */

+

+

+/********************  Bit definition for PWR_D3CR register  ******************/

+#define PWR_D3CR_VOS_Pos               (14U)

+#define PWR_D3CR_VOS_Msk               (0x3UL << PWR_D3CR_VOS_Pos)             /*!< 0x0000C000 */

+#define PWR_D3CR_VOS                   PWR_D3CR_VOS_Msk                        /*!< Voltage Scaling selection according performance */

+#define PWR_D3CR_VOS_0                 (0x1UL << PWR_D3CR_VOS_Pos)             /*!< 0x00004000 */

+#define PWR_D3CR_VOS_1                 (0x2UL << PWR_D3CR_VOS_Pos)             /*!< 0x00008000 */

+#define PWR_D3CR_VOSRDY_Pos            (13U)

+#define PWR_D3CR_VOSRDY_Msk            (0x1UL << PWR_D3CR_VOSRDY_Pos)          /*!< 0x00002000 */

+#define PWR_D3CR_VOSRDY                PWR_D3CR_VOSRDY_Msk                     /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */

+

+/******************  Bit definition for PWR_WKUPCR register  ******************/

+#define PWR_WKUPCR_WKUPC6_Pos          (5U)

+#define PWR_WKUPCR_WKUPC6_Msk          (0x1UL << PWR_WKUPCR_WKUPC6_Pos)        /*!< 0x00000020 */

+#define PWR_WKUPCR_WKUPC6              PWR_WKUPCR_WKUPC6_Msk                   /*!< Clear Wakeup Pin Flag 6 */

+#define PWR_WKUPCR_WKUPC5_Pos          (4U)

+#define PWR_WKUPCR_WKUPC5_Msk          (0x1UL << PWR_WKUPCR_WKUPC5_Pos)        /*!< 0x00000010 */

+#define PWR_WKUPCR_WKUPC5              PWR_WKUPCR_WKUPC5_Msk                   /*!< Clear Wakeup Pin Flag 5 */

+#define PWR_WKUPCR_WKUPC4_Pos          (3U)

+#define PWR_WKUPCR_WKUPC4_Msk          (0x1UL << PWR_WKUPCR_WKUPC4_Pos)        /*!< 0x00000008 */

+#define PWR_WKUPCR_WKUPC4              PWR_WKUPCR_WKUPC4_Msk                   /*!< Clear Wakeup Pin Flag 4 */

+#define PWR_WKUPCR_WKUPC3_Pos          (2U)

+#define PWR_WKUPCR_WKUPC3_Msk          (0x1UL << PWR_WKUPCR_WKUPC3_Pos)        /*!< 0x00000004 */

+#define PWR_WKUPCR_WKUPC3              PWR_WKUPCR_WKUPC3_Msk                   /*!< Clear Wakeup Pin Flag 3 */

+#define PWR_WKUPCR_WKUPC2_Pos          (1U)

+#define PWR_WKUPCR_WKUPC2_Msk          (0x1UL << PWR_WKUPCR_WKUPC2_Pos)        /*!< 0x00000002 */

+#define PWR_WKUPCR_WKUPC2              PWR_WKUPCR_WKUPC2_Msk                   /*!< Clear Wakeup Pin Flag 2 */

+#define PWR_WKUPCR_WKUPC1_Pos          (0U)

+#define PWR_WKUPCR_WKUPC1_Msk          (0x1UL << PWR_WKUPCR_WKUPC1_Pos)        /*!< 0x00000001 */

+#define PWR_WKUPCR_WKUPC1              PWR_WKUPCR_WKUPC1_Msk                   /*!< Clear Wakeup Pin Flag 1 */

+

+/********************  Bit definition for PWR_WKUPFR register  ****************/

+#define PWR_WKUPFR_WKUPF6_Pos          (5U)

+#define PWR_WKUPFR_WKUPF6_Msk          (0x1UL << PWR_WKUPFR_WKUPF6_Pos)        /*!< 0x00000020 */

+#define PWR_WKUPFR_WKUPF6              PWR_WKUPFR_WKUPF6_Msk                   /*!< Wakeup Pin Flag 6 */

+#define PWR_WKUPFR_WKUPF5_Pos          (4U)

+#define PWR_WKUPFR_WKUPF5_Msk          (0x1UL << PWR_WKUPFR_WKUPF5_Pos)        /*!< 0x00000010 */

+#define PWR_WKUPFR_WKUPF5              PWR_WKUPFR_WKUPF5_Msk                   /*!< Wakeup Pin Flag 5 */

+#define PWR_WKUPFR_WKUPF4_Pos          (3U)

+#define PWR_WKUPFR_WKUPF4_Msk          (0x1UL << PWR_WKUPFR_WKUPF4_Pos)        /*!< 0x00000008 */

+#define PWR_WKUPFR_WKUPF4              PWR_WKUPFR_WKUPF4_Msk                   /*!< Wakeup Pin Flag 4 */

+#define PWR_WKUPFR_WKUPF3_Pos          (2U)

+#define PWR_WKUPFR_WKUPF3_Msk          (0x1UL << PWR_WKUPFR_WKUPF3_Pos)        /*!< 0x00000004 */

+#define PWR_WKUPFR_WKUPF3              PWR_WKUPFR_WKUPF3_Msk                   /*!< Wakeup Pin Flag 3 */

+#define PWR_WKUPFR_WKUPF2_Pos          (1U)

+#define PWR_WKUPFR_WKUPF2_Msk          (0x1UL << PWR_WKUPFR_WKUPF2_Pos)        /*!< 0x00000002 */

+#define PWR_WKUPFR_WKUPF2              PWR_WKUPFR_WKUPF2_Msk                   /*!< Wakeup Pin Flag 2 */

+#define PWR_WKUPFR_WKUPF1_Pos          (0U)

+#define PWR_WKUPFR_WKUPF1_Msk          (0x1UL << PWR_WKUPFR_WKUPF1_Pos)        /*!< 0x00000001 */

+#define PWR_WKUPFR_WKUPF1              PWR_WKUPFR_WKUPF1_Msk                   /*!< Wakeup Pin Flag 1 */

+

+/******************  Bit definition for PWR_WKUPEPR register  *****************/

+#define PWR_WKUPEPR_WKUPPUPD6_Pos      (26U)

+#define PWR_WKUPEPR_WKUPPUPD6_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x0C000000 */

+#define PWR_WKUPEPR_WKUPPUPD6          PWR_WKUPEPR_WKUPPUPD6_Msk               /*!< Wakeup Pin pull configuration for WKUP6 */

+#define PWR_WKUPEPR_WKUPPUPD6_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x04000000 */

+#define PWR_WKUPEPR_WKUPPUPD6_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x08000000 */

+#define PWR_WKUPEPR_WKUPPUPD5_Pos      (24U)

+#define PWR_WKUPEPR_WKUPPUPD5_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x03000000 */

+#define PWR_WKUPEPR_WKUPPUPD5          PWR_WKUPEPR_WKUPPUPD5_Msk               /*!< Wakeup Pin pull configuration for WKUP5 */

+#define PWR_WKUPEPR_WKUPPUPD5_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x01000000 */

+#define PWR_WKUPEPR_WKUPPUPD5_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x02000000 */

+#define PWR_WKUPEPR_WKUPPUPD4_Pos      (22U)

+#define PWR_WKUPEPR_WKUPPUPD4_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00C00000 */

+#define PWR_WKUPEPR_WKUPPUPD4          PWR_WKUPEPR_WKUPPUPD4_Msk               /*!< Wakeup Pin pull configuration for WKUP4 */

+#define PWR_WKUPEPR_WKUPPUPD4_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00400000 */

+#define PWR_WKUPEPR_WKUPPUPD4_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00800000 */

+#define PWR_WKUPEPR_WKUPPUPD3_Pos      (20U)

+#define PWR_WKUPEPR_WKUPPUPD3_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00300000 */

+#define PWR_WKUPEPR_WKUPPUPD3          PWR_WKUPEPR_WKUPPUPD3_Msk               /*!< Wakeup Pin pull configuration for WKUP3 */

+#define PWR_WKUPEPR_WKUPPUPD3_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00100000 */

+#define PWR_WKUPEPR_WKUPPUPD3_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00200000 */

+#define PWR_WKUPEPR_WKUPPUPD2_Pos      (18U)

+#define PWR_WKUPEPR_WKUPPUPD2_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x000C0000 */

+#define PWR_WKUPEPR_WKUPPUPD2          PWR_WKUPEPR_WKUPPUPD2_Msk               /*!< Wakeup Pin pull configuration for WKUP2 */

+#define PWR_WKUPEPR_WKUPPUPD2_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00040000 */

+#define PWR_WKUPEPR_WKUPPUPD2_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00080000 */

+#define PWR_WKUPEPR_WKUPPUPD1_Pos      (16U)

+#define PWR_WKUPEPR_WKUPPUPD1_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00030000 */

+#define PWR_WKUPEPR_WKUPPUPD1          PWR_WKUPEPR_WKUPPUPD1_Msk               /*!< Wakeup Pin pull configuration for WKUP1 */

+#define PWR_WKUPEPR_WKUPPUPD1_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00010000 */

+#define PWR_WKUPEPR_WKUPPUPD1_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00020000 */

+#define PWR_WKUPEPR_WKUPP6_Pos         (13U)

+#define PWR_WKUPEPR_WKUPP6_Msk         (0x1UL << PWR_WKUPEPR_WKUPP6_Pos)       /*!< 0x00002000 */

+#define PWR_WKUPEPR_WKUPP6             PWR_WKUPEPR_WKUPP6_Msk                  /*!< Wakeup Pin Polarity for WKUP6 */

+#define PWR_WKUPEPR_WKUPP5_Pos         (12U)

+#define PWR_WKUPEPR_WKUPP5_Msk         (0x1UL << PWR_WKUPEPR_WKUPP5_Pos)       /*!< 0x00001000 */

+#define PWR_WKUPEPR_WKUPP5             PWR_WKUPEPR_WKUPP5_Msk                  /*!< Wakeup Pin Polarity for WKUP5 */

+#define PWR_WKUPEPR_WKUPP4_Pos         (11U)

+#define PWR_WKUPEPR_WKUPP4_Msk         (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)       /*!< 0x00000800 */

+#define PWR_WKUPEPR_WKUPP4             PWR_WKUPEPR_WKUPP4_Msk                  /*!< Wakeup Pin Polarity for WKUP4 */

+#define PWR_WKUPEPR_WKUPP3_Pos         (10U)

+#define PWR_WKUPEPR_WKUPP3_Msk         (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)       /*!< 0x00000400 */

+#define PWR_WKUPEPR_WKUPP3             PWR_WKUPEPR_WKUPP3_Msk                  /*!< Wakeup Pin Polarity for WKUP3 */

+#define PWR_WKUPEPR_WKUPP2_Pos         (9U)

+#define PWR_WKUPEPR_WKUPP2_Msk         (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)       /*!< 0x00000200 */

+#define PWR_WKUPEPR_WKUPP2             PWR_WKUPEPR_WKUPP2_Msk                  /*!< Wakeup Pin Polarity for WKUP2 */

+#define PWR_WKUPEPR_WKUPP1_Pos         (8U)

+#define PWR_WKUPEPR_WKUPP1_Msk         (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)       /*!< 0x00000100 */

+#define PWR_WKUPEPR_WKUPP1             PWR_WKUPEPR_WKUPP1_Msk                  /*!< Wakeup Pin Polarity for WKUP1 */

+#define PWR_WKUPEPR_WKUPEN6_Pos        (5U)

+#define PWR_WKUPEPR_WKUPEN6_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos)      /*!< 0x00000020 */

+#define PWR_WKUPEPR_WKUPEN6            PWR_WKUPEPR_WKUPEN6_Msk                 /*!< Enable Wakeup Pin WKUP6 */

+#define PWR_WKUPEPR_WKUPEN5_Pos        (4U)

+#define PWR_WKUPEPR_WKUPEN5_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos)      /*!< 0x00000010 */

+#define PWR_WKUPEPR_WKUPEN5            PWR_WKUPEPR_WKUPEN5_Msk                 /*!< Enable Wakeup Pin WKUP5 */

+#define PWR_WKUPEPR_WKUPEN4_Pos        (3U)

+#define PWR_WKUPEPR_WKUPEN4_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)      /*!< 0x00000008 */

+#define PWR_WKUPEPR_WKUPEN4            PWR_WKUPEPR_WKUPEN4_Msk                 /*!< Enable Wakeup Pin WKUP4 */

+#define PWR_WKUPEPR_WKUPEN3_Pos        (2U)

+#define PWR_WKUPEPR_WKUPEN3_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)      /*!< 0x00000004 */

+#define PWR_WKUPEPR_WKUPEN3            PWR_WKUPEPR_WKUPEN3_Msk                 /*!< Enable Wakeup Pin WKUP3 */

+#define PWR_WKUPEPR_WKUPEN2_Pos        (1U)

+#define PWR_WKUPEPR_WKUPEN2_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)      /*!< 0x00000002 */

+#define PWR_WKUPEPR_WKUPEN2            PWR_WKUPEPR_WKUPEN2_Msk                 /*!< Enable Wakeup Pin WKUP2 */

+#define PWR_WKUPEPR_WKUPEN1_Pos        (0U)

+#define PWR_WKUPEPR_WKUPEN1_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)      /*!< 0x00000001 */

+#define PWR_WKUPEPR_WKUPEN1            PWR_WKUPEPR_WKUPEN1_Msk                 /*!< Enable Wakeup Pin WKUP1 */

+#define PWR_WKUPEPR_WKUPEN_Pos         (0U)

+#define PWR_WKUPEPR_WKUPEN_Msk         (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos)      /*!< 0x0000003F */

+#define PWR_WKUPEPR_WKUPEN             PWR_WKUPEPR_WKUPEN_Msk                  /*!< Enable all Wakeup Pin */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Reset and Clock Control                            */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  RCC VERSION  ********************************/

+#define RCC_VER_X

+

+/********************  Bit definition for RCC_CR register  ********************/

+#define RCC_CR_HSION_Pos                       (0U)

+#define RCC_CR_HSION_Msk                       (0x1UL << RCC_CR_HSION_Pos)     /*!< 0x00000001 */

+#define RCC_CR_HSION                           RCC_CR_HSION_Msk                /*!< Internal High Speed clock enable */

+#define RCC_CR_HSIKERON_Pos                    (1U)

+#define RCC_CR_HSIKERON_Msk                    (0x1UL << RCC_CR_HSIKERON_Pos)  /*!< 0x00000002 */

+#define RCC_CR_HSIKERON                        RCC_CR_HSIKERON_Msk             /*!< Internal High Speed clock enable for some IPs Kernel */

+#define RCC_CR_HSIRDY_Pos                      (2U)

+#define RCC_CR_HSIRDY_Msk                      (0x1UL << RCC_CR_HSIRDY_Pos)    /*!< 0x00000004 */

+#define RCC_CR_HSIRDY                          RCC_CR_HSIRDY_Msk               /*!< Internal High Speed clock ready flag */

+#define RCC_CR_HSIDIV_Pos                      (3U)

+#define RCC_CR_HSIDIV_Msk                      (0x3UL << RCC_CR_HSIDIV_Pos)    /*!< 0x00000018 */

+#define RCC_CR_HSIDIV                          RCC_CR_HSIDIV_Msk               /*!< Internal High Speed clock divider selection */

+#define RCC_CR_HSIDIV_1                        (0x0UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000000 */

+#define RCC_CR_HSIDIV_2                        (0x1UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000008 */

+#define RCC_CR_HSIDIV_4                        (0x2UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000010 */

+#define RCC_CR_HSIDIV_8                        (0x3UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000018 */

+

+#define RCC_CR_HSIDIVF_Pos                     (5U)

+#define RCC_CR_HSIDIVF_Msk                     (0x1UL << RCC_CR_HSIDIVF_Pos)   /*!< 0x00000020 */

+#define RCC_CR_HSIDIVF                         RCC_CR_HSIDIVF_Msk              /*!< HSI Divider flag */

+#define RCC_CR_CSION_Pos                       (7U)

+#define RCC_CR_CSION_Msk                       (0x1UL << RCC_CR_CSION_Pos)     /*!< 0x00000080 */

+#define RCC_CR_CSION                           RCC_CR_CSION_Msk                /*!< The Internal RC 4MHz oscillator clock enable */

+#define RCC_CR_CSIRDY_Pos                      (8U)

+#define RCC_CR_CSIRDY_Msk                      (0x1UL << RCC_CR_CSIRDY_Pos)    /*!< 0x00000100 */

+#define RCC_CR_CSIRDY                          RCC_CR_CSIRDY_Msk               /*!< The Internal RC 4MHz oscillator clock ready */

+#define RCC_CR_CSIKERON_Pos                    (9U)

+#define RCC_CR_CSIKERON_Msk                    (0x1UL << RCC_CR_CSIKERON_Pos)  /*!< 0x00000200 */

+#define RCC_CR_CSIKERON                        RCC_CR_CSIKERON_Msk             /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */

+#define RCC_CR_HSI48ON_Pos                     (12U)

+#define RCC_CR_HSI48ON_Msk                     (0x1UL << RCC_CR_HSI48ON_Pos)   /*!< 0x00001000 */

+#define RCC_CR_HSI48ON                         RCC_CR_HSI48ON_Msk              /*!< HSI48 clock enable clock enable  */

+#define RCC_CR_HSI48RDY_Pos                    (13U)

+#define RCC_CR_HSI48RDY_Msk                    (0x1UL << RCC_CR_HSI48RDY_Pos)  /*!< 0x00002000 */

+#define RCC_CR_HSI48RDY                        RCC_CR_HSI48RDY_Msk             /*!< HSI48 clock ready */

+

+#define RCC_CR_D1CKRDY_Pos                     (14U)

+#define RCC_CR_D1CKRDY_Msk                     (0x1UL << RCC_CR_D1CKRDY_Pos)   /*!< 0x00004000 */

+#define RCC_CR_D1CKRDY                         RCC_CR_D1CKRDY_Msk              /*!< D1 domain clocks ready flag  */

+#define RCC_CR_D2CKRDY_Pos                     (15U)

+#define RCC_CR_D2CKRDY_Msk                     (0x1UL << RCC_CR_D2CKRDY_Pos)   /*!< 0x00008000 */

+#define RCC_CR_D2CKRDY                         RCC_CR_D2CKRDY_Msk              /*!< D2 domain clocks ready flag */

+

+#define RCC_CR_HSEON_Pos                       (16U)

+#define RCC_CR_HSEON_Msk                       (0x1UL << RCC_CR_HSEON_Pos)     /*!< 0x00010000 */

+#define RCC_CR_HSEON                           RCC_CR_HSEON_Msk                /*!< External High Speed clock enable */

+#define RCC_CR_HSERDY_Pos                      (17U)

+#define RCC_CR_HSERDY_Msk                      (0x1UL << RCC_CR_HSERDY_Pos)    /*!< 0x00020000 */

+#define RCC_CR_HSERDY                          RCC_CR_HSERDY_Msk               /*!< External High Speed clock ready */

+#define RCC_CR_HSEBYP_Pos                      (18U)

+#define RCC_CR_HSEBYP_Msk                      (0x1UL << RCC_CR_HSEBYP_Pos)    /*!< 0x00040000 */

+#define RCC_CR_HSEBYP                          RCC_CR_HSEBYP_Msk               /*!< External High Speed clock Bypass */

+#define RCC_CR_CSSHSEON_Pos                    (19U)

+#define RCC_CR_CSSHSEON_Msk                    (0x1UL << RCC_CR_CSSHSEON_Pos)  /*!< 0x00080000 */

+#define RCC_CR_CSSHSEON                        RCC_CR_CSSHSEON_Msk             /*!< HSE Clock security System enable */

+

+

+#define RCC_CR_PLL1ON_Pos                      (24U)

+#define RCC_CR_PLL1ON_Msk                      (0x1UL << RCC_CR_PLL1ON_Pos)    /*!< 0x01000000 */

+#define RCC_CR_PLL1ON                          RCC_CR_PLL1ON_Msk               /*!< System PLL1 clock enable */

+#define RCC_CR_PLL1RDY_Pos                     (25U)

+#define RCC_CR_PLL1RDY_Msk                     (0x1UL << RCC_CR_PLL1RDY_Pos)   /*!< 0x02000000 */

+#define RCC_CR_PLL1RDY                         RCC_CR_PLL1RDY_Msk              /*!< System PLL1 clock ready */

+#define RCC_CR_PLL2ON_Pos                      (26U)

+#define RCC_CR_PLL2ON_Msk                      (0x1UL << RCC_CR_PLL2ON_Pos)    /*!< 0x04000000 */

+#define RCC_CR_PLL2ON                          RCC_CR_PLL2ON_Msk               /*!< System PLL2 clock enable */

+#define RCC_CR_PLL2RDY_Pos                     (27U)

+#define RCC_CR_PLL2RDY_Msk                     (0x1UL << RCC_CR_PLL2RDY_Pos)   /*!< 0x08000000 */

+#define RCC_CR_PLL2RDY                         RCC_CR_PLL2RDY_Msk              /*!< System PLL2 clock ready */

+#define RCC_CR_PLL3ON_Pos                      (28U)

+#define RCC_CR_PLL3ON_Msk                      (0x1UL << RCC_CR_PLL3ON_Pos)    /*!< 0x10000000 */

+#define RCC_CR_PLL3ON                          RCC_CR_PLL3ON_Msk               /*!< System PLL3 clock enable */

+#define RCC_CR_PLL3RDY_Pos                     (29U)

+#define RCC_CR_PLL3RDY_Msk                     (0x1UL << RCC_CR_PLL3RDY_Pos)   /*!< 0x20000000 */

+#define RCC_CR_PLL3RDY                         RCC_CR_PLL3RDY_Msk              /*!< System PLL3 clock ready */

+

+/*Legacy */

+#define RCC_CR_PLLON_Pos                       (24U)

+#define RCC_CR_PLLON_Msk                       (0x1UL << RCC_CR_PLLON_Pos)     /*!< 0x01000000 */

+#define RCC_CR_PLLON                           RCC_CR_PLLON_Msk                /*!< System PLL clock enable */

+#define RCC_CR_PLLRDY_Pos                      (25U)

+#define RCC_CR_PLLRDY_Msk                      (0x1UL << RCC_CR_PLLRDY_Pos)    /*!< 0x02000000 */

+#define RCC_CR_PLLRDY                          RCC_CR_PLLRDY_Msk               /*!< System PLL clock ready */

+

+/********************  Bit definition for RCC_HSICFGR register  ***************/

+/*!< HSICAL configuration */

+#define RCC_HSICFGR_HSICAL_Pos                 (0U)

+#define RCC_HSICFGR_HSICAL_Msk                 (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */

+#define RCC_HSICFGR_HSICAL                     RCC_HSICFGR_HSICAL_Msk          /*!< HSICAL[11:0] bits */

+#define RCC_HSICFGR_HSICAL_0                   (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */

+#define RCC_HSICFGR_HSICAL_1                   (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */

+#define RCC_HSICFGR_HSICAL_2                   (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */

+#define RCC_HSICFGR_HSICAL_3                   (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */

+#define RCC_HSICFGR_HSICAL_4                   (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */

+#define RCC_HSICFGR_HSICAL_5                   (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */

+#define RCC_HSICFGR_HSICAL_6                   (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */

+#define RCC_HSICFGR_HSICAL_7                   (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */

+#define RCC_HSICFGR_HSICAL_8                   (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */

+#define RCC_HSICFGR_HSICAL_9                   (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */

+#define RCC_HSICFGR_HSICAL_10                  (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */

+#define RCC_HSICFGR_HSICAL_11                  (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */

+

+/*!< HSITRIM configuration */

+#define RCC_HSICFGR_HSITRIM_Pos                (24U)

+#define RCC_HSICFGR_HSITRIM_Msk                (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */

+#define RCC_HSICFGR_HSITRIM                    RCC_HSICFGR_HSITRIM_Msk         /*!< HSITRIM[6:0] bits */

+#define RCC_HSICFGR_HSITRIM_0                  (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */

+#define RCC_HSICFGR_HSITRIM_1                  (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */

+#define RCC_HSICFGR_HSITRIM_2                  (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */

+#define RCC_HSICFGR_HSITRIM_3                  (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */

+#define RCC_HSICFGR_HSITRIM_4                  (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */

+#define RCC_HSICFGR_HSITRIM_5                  (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */

+#define RCC_HSICFGR_HSITRIM_6                  (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */

+

+

+/********************  Bit definition for RCC_CRRCR register  *****************/

+

+/*!< HSI48CAL configuration */

+#define RCC_CRRCR_HSI48CAL_Pos                 (0U)

+#define RCC_CRRCR_HSI48CAL_Msk                 (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */

+#define RCC_CRRCR_HSI48CAL                     RCC_CRRCR_HSI48CAL_Msk          /*!< HSI48CAL[9:0] bits */

+#define RCC_CRRCR_HSI48CAL_0                   (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */

+#define RCC_CRRCR_HSI48CAL_1                   (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */

+#define RCC_CRRCR_HSI48CAL_2                   (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */

+#define RCC_CRRCR_HSI48CAL_3                   (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */

+#define RCC_CRRCR_HSI48CAL_4                   (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */

+#define RCC_CRRCR_HSI48CAL_5                   (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */

+#define RCC_CRRCR_HSI48CAL_6                   (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */

+#define RCC_CRRCR_HSI48CAL_7                   (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */

+#define RCC_CRRCR_HSI48CAL_8                   (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */

+#define RCC_CRRCR_HSI48CAL_9                   (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */

+

+

+/********************  Bit definition for RCC_CSICFGR register  *****************/

+/*!< CSICAL configuration */

+#define RCC_CSICFGR_CSICAL_Pos                 (0U)

+#define RCC_CSICFGR_CSICAL_Msk                 (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */

+#define RCC_CSICFGR_CSICAL                     RCC_CSICFGR_CSICAL_Msk          /*!< CSICAL[7:0] bits */

+#define RCC_CSICFGR_CSICAL_0                   (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */

+#define RCC_CSICFGR_CSICAL_1                   (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */

+#define RCC_CSICFGR_CSICAL_2                   (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */

+#define RCC_CSICFGR_CSICAL_3                   (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */

+#define RCC_CSICFGR_CSICAL_4                   (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */

+#define RCC_CSICFGR_CSICAL_5                   (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */

+#define RCC_CSICFGR_CSICAL_6                   (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */

+#define RCC_CSICFGR_CSICAL_7                   (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */

+

+/*!< CSITRIM configuration */

+#define RCC_CSICFGR_CSITRIM_Pos                (24U)

+#define RCC_CSICFGR_CSITRIM_Msk                (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */

+#define RCC_CSICFGR_CSITRIM                    RCC_CSICFGR_CSITRIM_Msk         /*!< CSITRIM[5:0] bits */

+#define RCC_CSICFGR_CSITRIM_0                  (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */

+#define RCC_CSICFGR_CSITRIM_1                  (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */

+#define RCC_CSICFGR_CSITRIM_2                  (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */

+#define RCC_CSICFGR_CSITRIM_3                  (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */

+#define RCC_CSICFGR_CSITRIM_4                  (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */

+#define RCC_CSICFGR_CSITRIM_5                  (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */

+

+/********************  Bit definition for RCC_CFGR register  ******************/

+/*!< SW configuration */

+#define RCC_CFGR_SW_Pos                        (0U)

+#define RCC_CFGR_SW_Msk                        (0x7UL << RCC_CFGR_SW_Pos)           /*!< 0x00000007 */

+#define RCC_CFGR_SW                            RCC_CFGR_SW_Msk                     /*!< SW[2:0] bits (System clock Switch) */

+#define RCC_CFGR_SW_0                          (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */

+#define RCC_CFGR_SW_1                          (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */

+#define RCC_CFGR_SW_2                          (0x4UL << RCC_CFGR_SW_Pos)           /*!< 0x00000004 */

+

+#define RCC_CFGR_SW_HSI                        (0x00000000UL)                       /*!< HSI selection as system clock */

+#define RCC_CFGR_SW_CSI                        (0x00000001UL)                       /*!< CSI selection as system clock */

+#define RCC_CFGR_SW_HSE                        (0x00000002UL)                       /*!< HSE selection as system clock */

+#define RCC_CFGR_SW_PLL1                       (0x00000003UL)                       /*!< PLL1 selection as system clock */

+

+/*!< SWS configuration */

+#define RCC_CFGR_SWS_Pos                       (3U)

+#define RCC_CFGR_SWS_Msk                       (0x7UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000038 */

+#define RCC_CFGR_SWS                           RCC_CFGR_SWS_Msk                    /*!< SWS[2:0] bits (System Clock Switch Status) */

+#define RCC_CFGR_SWS_0                         (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */

+#define RCC_CFGR_SWS_1                         (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000010 */

+#define RCC_CFGR_SWS_2                         (0x4UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000020 */

+

+#define RCC_CFGR_SWS_HSI                       (0x00000000UL)                       /*!< HSI used as system clock */

+#define RCC_CFGR_SWS_CSI                       (0x00000008UL)                       /*!< CSI used as system clock */

+#define RCC_CFGR_SWS_HSE                       (0x00000010UL)                       /*!< HSE used as system clock */

+#define RCC_CFGR_SWS_PLL1                      (0x00000018UL)                       /*!< PLL1 used as system clock */

+

+#define RCC_CFGR_STOPWUCK_Pos                  (6U)

+#define RCC_CFGR_STOPWUCK_Msk                  (0x1UL << RCC_CFGR_STOPWUCK_Pos)     /*!< 0x00000040 */

+#define RCC_CFGR_STOPWUCK                      RCC_CFGR_STOPWUCK_Msk                /*!< Wake Up from stop and CSS backup clock selection */

+

+#define RCC_CFGR_STOPKERWUCK_Pos               (7U)

+#define RCC_CFGR_STOPKERWUCK_Msk               (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)  /*!< 0x00000080 */

+#define RCC_CFGR_STOPKERWUCK                   RCC_CFGR_STOPKERWUCK_Msk             /*!< Kernel Clock Selection after a Wake Up from STOP */

+

+/*!< RTCPRE configuration */

+#define RCC_CFGR_RTCPRE_Pos                    (8U)

+#define RCC_CFGR_RTCPRE_Msk                    (0x3FUL << RCC_CFGR_RTCPRE_Pos)

+#define RCC_CFGR_RTCPRE                        RCC_CFGR_RTCPRE_Msk                  /*!< 0x00003F00 */

+#define RCC_CFGR_RTCPRE_0                      (0x1UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000100 */

+#define RCC_CFGR_RTCPRE_1                      (0x2UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000200 */

+#define RCC_CFGR_RTCPRE_2                      (0x4UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000400 */

+#define RCC_CFGR_RTCPRE_3                      (0x8UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000800 */

+#define RCC_CFGR_RTCPRE_4                      (0x10UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00001000 */

+#define RCC_CFGR_RTCPRE_5                      (0x20UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00002000 */

+

+/*!< HRTIMSEL configuration */

+#define RCC_CFGR_HRTIMSEL_Pos                  (14U)

+#define RCC_CFGR_HRTIMSEL_Msk                  (0x1UL << RCC_CFGR_HRTIMSEL_Pos)

+#define RCC_CFGR_HRTIMSEL                      RCC_CFGR_HRTIMSEL_Msk                /*!< 0x00004000 */

+

+/*!< TIMPRE configuration */

+#define RCC_CFGR_TIMPRE_Pos                    (15U)

+#define RCC_CFGR_TIMPRE_Msk                    (0x1UL << RCC_CFGR_TIMPRE_Pos)

+#define RCC_CFGR_TIMPRE                        RCC_CFGR_TIMPRE_Msk                  /*!< 0x00008000 */

+

+/*!< MCO1 configuration */

+#define RCC_CFGR_MCO1_Pos                      (22U)

+#define RCC_CFGR_MCO1_Msk                      (0x7UL << RCC_CFGR_MCO1_Pos)

+#define RCC_CFGR_MCO1                          RCC_CFGR_MCO1_Msk                       /*!< 0x01C00000 */

+#define RCC_CFGR_MCO1_0                        (0x1UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00400000 */

+#define RCC_CFGR_MCO1_1                        (0x2UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00800000 */

+#define RCC_CFGR_MCO1_2                        (0x4UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x01000000 */

+

+#define RCC_CFGR_MCO1PRE_Pos                   (18U)

+#define RCC_CFGR_MCO1PRE_Msk                   (0xFUL << RCC_CFGR_MCO1PRE_Pos)

+#define RCC_CFGR_MCO1PRE                       RCC_CFGR_MCO1PRE_Msk                    /*!< 0x003C0000 */

+#define RCC_CFGR_MCO1PRE_0                     (0x1UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00040000 */

+#define RCC_CFGR_MCO1PRE_1                     (0x2UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00080000 */

+#define RCC_CFGR_MCO1PRE_2                     (0x4UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00100000 */

+#define RCC_CFGR_MCO1PRE_3                     (0x8UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00200000 */

+

+#define RCC_CFGR_MCO2PRE_Pos                   (25U)

+#define RCC_CFGR_MCO2PRE_Msk                   (0xFUL << RCC_CFGR_MCO2PRE_Pos)

+#define RCC_CFGR_MCO2PRE                       RCC_CFGR_MCO2PRE_Msk                    /*!< 0x1E000000 */

+#define RCC_CFGR_MCO2PRE_0                     (0x1UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x02000000 */

+#define RCC_CFGR_MCO2PRE_1                     (0x2UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x04000000 */

+#define RCC_CFGR_MCO2PRE_2                     (0x4UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x08000000 */

+#define RCC_CFGR_MCO2PRE_3                     (0x8UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x10000000 */

+

+#define RCC_CFGR_MCO2_Pos                      (29U)

+#define RCC_CFGR_MCO2_Msk                      (0x7UL << RCC_CFGR_MCO2_Pos)

+#define RCC_CFGR_MCO2                          RCC_CFGR_MCO2_Msk                       /*!< 0xE0000000 */

+#define RCC_CFGR_MCO2_0                        (0x1UL << RCC_CFGR_MCO2_Pos)             /*!< 0x20000000 */

+#define RCC_CFGR_MCO2_1                        (0x2UL << RCC_CFGR_MCO2_Pos)             /*!< 0x40000000 */

+#define RCC_CFGR_MCO2_2                        (0x4UL << RCC_CFGR_MCO2_Pos)             /*!< 0x80000000 */

+

+/********************  Bit definition for RCC_D1CFGR register  ******************/

+/*!< D1HPRE configuration */

+#define RCC_D1CFGR_HPRE_Pos                    (0U)

+#define RCC_D1CFGR_HPRE_Msk                    (0xFUL << RCC_D1CFGR_HPRE_Pos)  /*!< 0x0000000F */

+#define RCC_D1CFGR_HPRE                        RCC_D1CFGR_HPRE_Msk             /*!< HPRE[3:0] bits (AHB3 prescaler) */

+#define RCC_D1CFGR_HPRE_0                      (0x1UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000001 */

+#define RCC_D1CFGR_HPRE_1                      (0x2UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000002 */

+#define RCC_D1CFGR_HPRE_2                      (0x4UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000004 */

+#define RCC_D1CFGR_HPRE_3                      (0x8UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000008 */

+

+

+#define RCC_D1CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)          /*!< AHB3 Clock not divided */

+#define RCC_D1CFGR_HPRE_DIV2_Pos               (3U)

+#define RCC_D1CFGR_HPRE_DIV2_Msk               (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */

+#define RCC_D1CFGR_HPRE_DIV2                   RCC_D1CFGR_HPRE_DIV2_Msk        /*!< AHB3 Clock divided by 2 */

+#define RCC_D1CFGR_HPRE_DIV4_Pos               (0U)

+#define RCC_D1CFGR_HPRE_DIV4_Msk               (0x9UL << RCC_D1CFGR_HPRE_DIV4_Pos) /*!< 0x00000009 */

+#define RCC_D1CFGR_HPRE_DIV4                   RCC_D1CFGR_HPRE_DIV4_Msk        /*!< AHB3 Clock divided by 4 */

+#define RCC_D1CFGR_HPRE_DIV8_Pos               (1U)

+#define RCC_D1CFGR_HPRE_DIV8_Msk               (0x5UL << RCC_D1CFGR_HPRE_DIV8_Pos) /*!< 0x0000000A */

+#define RCC_D1CFGR_HPRE_DIV8                   RCC_D1CFGR_HPRE_DIV8_Msk        /*!< AHB3 Clock divided by 8 */

+#define RCC_D1CFGR_HPRE_DIV16_Pos              (0U)

+#define RCC_D1CFGR_HPRE_DIV16_Msk              (0xBUL << RCC_D1CFGR_HPRE_DIV16_Pos) /*!< 0x0000000B */

+#define RCC_D1CFGR_HPRE_DIV16                  RCC_D1CFGR_HPRE_DIV16_Msk       /*!< AHB3 Clock divided by 16 */

+#define RCC_D1CFGR_HPRE_DIV64_Pos              (2U)

+#define RCC_D1CFGR_HPRE_DIV64_Msk              (0x3UL << RCC_D1CFGR_HPRE_DIV64_Pos) /*!< 0x0000000C */

+#define RCC_D1CFGR_HPRE_DIV64                  RCC_D1CFGR_HPRE_DIV64_Msk       /*!< AHB3 Clock divided by 64 */

+#define RCC_D1CFGR_HPRE_DIV128_Pos             (0U)

+#define RCC_D1CFGR_HPRE_DIV128_Msk             (0xDUL << RCC_D1CFGR_HPRE_DIV128_Pos) /*!< 0x0000000D */

+#define RCC_D1CFGR_HPRE_DIV128                 RCC_D1CFGR_HPRE_DIV128_Msk      /*!< AHB3 Clock divided by 128 */

+#define RCC_D1CFGR_HPRE_DIV256_Pos             (1U)

+#define RCC_D1CFGR_HPRE_DIV256_Msk             (0x7UL << RCC_D1CFGR_HPRE_DIV256_Pos) /*!< 0x0000000E */

+#define RCC_D1CFGR_HPRE_DIV256                 RCC_D1CFGR_HPRE_DIV256_Msk      /*!< AHB3 Clock divided by 256 */

+#define RCC_D1CFGR_HPRE_DIV512_Pos             (0U)

+#define RCC_D1CFGR_HPRE_DIV512_Msk             (0xFUL << RCC_D1CFGR_HPRE_DIV512_Pos) /*!< 0x0000000F */

+#define RCC_D1CFGR_HPRE_DIV512                 RCC_D1CFGR_HPRE_DIV512_Msk      /*!< AHB3 Clock divided by 512 */

+

+/*!< D1PPRE configuration */

+#define RCC_D1CFGR_D1PPRE_Pos                  (4U)

+#define RCC_D1CFGR_D1PPRE_Msk                  (0x7UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000070 */

+#define RCC_D1CFGR_D1PPRE                      RCC_D1CFGR_D1PPRE_Msk           /*!< D1PRE[2:0] bits (APB3 prescaler) */

+#define RCC_D1CFGR_D1PPRE_0                    (0x1UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000010 */

+#define RCC_D1CFGR_D1PPRE_1                    (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */

+#define RCC_D1CFGR_D1PPRE_2                    (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */

+

+#define RCC_D1CFGR_D1PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB3 clock not divided */

+#define RCC_D1CFGR_D1PPRE_DIV2_Pos             (6U)

+#define RCC_D1CFGR_D1PPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_D1CFGR_D1PPRE_DIV2                 RCC_D1CFGR_D1PPRE_DIV2_Msk      /*!< APB3 clock divided by 2 */

+#define RCC_D1CFGR_D1PPRE_DIV4_Pos             (4U)

+#define RCC_D1CFGR_D1PPRE_DIV4_Msk             (0x5UL << RCC_D1CFGR_D1PPRE_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_D1CFGR_D1PPRE_DIV4                 RCC_D1CFGR_D1PPRE_DIV4_Msk      /*!< APB3 clock divided by 4 */

+#define RCC_D1CFGR_D1PPRE_DIV8_Pos             (5U)

+#define RCC_D1CFGR_D1PPRE_DIV8_Msk             (0x3UL << RCC_D1CFGR_D1PPRE_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_D1CFGR_D1PPRE_DIV8                 RCC_D1CFGR_D1PPRE_DIV8_Msk      /*!< APB3 clock divided by 8 */

+#define RCC_D1CFGR_D1PPRE_DIV16_Pos            (4U)

+#define RCC_D1CFGR_D1PPRE_DIV16_Msk            (0x7UL << RCC_D1CFGR_D1PPRE_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_D1CFGR_D1PPRE_DIV16                RCC_D1CFGR_D1PPRE_DIV16_Msk     /*!< APB3 clock divided by 16 */

+

+#define RCC_D1CFGR_D1CPRE_Pos                  (8U)

+#define RCC_D1CFGR_D1CPRE_Msk                  (0xFUL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000F00 */

+#define RCC_D1CFGR_D1CPRE                      RCC_D1CFGR_D1CPRE_Msk           /*!< D1CPRE[2:0] bits (Domain 1 Core prescaler) */

+#define RCC_D1CFGR_D1CPRE_0                    (0x1UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000100 */

+#define RCC_D1CFGR_D1CPRE_1                    (0x2UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000200 */

+#define RCC_D1CFGR_D1CPRE_2                    (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */

+#define RCC_D1CFGR_D1CPRE_3                    (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */

+

+#define RCC_D1CFGR_D1CPRE_DIV1                 ((uint32_t)0x00000000)          /*!< Domain 1 Core clock not divided */

+#define RCC_D1CFGR_D1CPRE_DIV2_Pos             (11U)

+#define RCC_D1CFGR_D1CPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */

+#define RCC_D1CFGR_D1CPRE_DIV2                 RCC_D1CFGR_D1CPRE_DIV2_Msk      /*!< Domain 1 Core clock divided by 2 */

+#define RCC_D1CFGR_D1CPRE_DIV4_Pos             (8U)

+#define RCC_D1CFGR_D1CPRE_DIV4_Msk             (0x9UL << RCC_D1CFGR_D1CPRE_DIV4_Pos) /*!< 0x00000900 */

+#define RCC_D1CFGR_D1CPRE_DIV4                 RCC_D1CFGR_D1CPRE_DIV4_Msk      /*!< Domain 1 Core clock divided by 4 */

+#define RCC_D1CFGR_D1CPRE_DIV8_Pos             (9U)

+#define RCC_D1CFGR_D1CPRE_DIV8_Msk             (0x5UL << RCC_D1CFGR_D1CPRE_DIV8_Pos) /*!< 0x00000A00 */

+#define RCC_D1CFGR_D1CPRE_DIV8                 RCC_D1CFGR_D1CPRE_DIV8_Msk      /*!< Domain 1 Core clock divided by 8 */

+#define RCC_D1CFGR_D1CPRE_DIV16_Pos            (8U)

+#define RCC_D1CFGR_D1CPRE_DIV16_Msk            (0xBUL << RCC_D1CFGR_D1CPRE_DIV16_Pos) /*!< 0x00000B00 */

+#define RCC_D1CFGR_D1CPRE_DIV16                RCC_D1CFGR_D1CPRE_DIV16_Msk     /*!< Domain 1 Core clock divided by 16 */

+#define RCC_D1CFGR_D1CPRE_DIV64_Pos            (10U)

+#define RCC_D1CFGR_D1CPRE_DIV64_Msk            (0x3UL << RCC_D1CFGR_D1CPRE_DIV64_Pos) /*!< 0x00000C00 */

+#define RCC_D1CFGR_D1CPRE_DIV64                RCC_D1CFGR_D1CPRE_DIV64_Msk     /*!< Domain 1 Core clock divided by 64 */

+#define RCC_D1CFGR_D1CPRE_DIV128_Pos           (8U)

+#define RCC_D1CFGR_D1CPRE_DIV128_Msk           (0xDUL << RCC_D1CFGR_D1CPRE_DIV128_Pos) /*!< 0x00000D00 */

+#define RCC_D1CFGR_D1CPRE_DIV128               RCC_D1CFGR_D1CPRE_DIV128_Msk    /*!< Domain 1 Core clock divided by 128 */

+#define RCC_D1CFGR_D1CPRE_DIV256_Pos           (9U)

+#define RCC_D1CFGR_D1CPRE_DIV256_Msk           (0x7UL << RCC_D1CFGR_D1CPRE_DIV256_Pos) /*!< 0x00000E00 */

+#define RCC_D1CFGR_D1CPRE_DIV256               RCC_D1CFGR_D1CPRE_DIV256_Msk    /*!< Domain 1 Core clock divided by 256 */

+#define RCC_D1CFGR_D1CPRE_DIV512_Pos           (8U)

+#define RCC_D1CFGR_D1CPRE_DIV512_Msk           (0xFUL << RCC_D1CFGR_D1CPRE_DIV512_Pos) /*!< 0x00000F00 */

+#define RCC_D1CFGR_D1CPRE_DIV512               RCC_D1CFGR_D1CPRE_DIV512_Msk    /*!< Domain 1 Core clock divided by 512 */

+

+/********************  Bit definition for RCC_D2CFGR register  ******************/

+/*!< D2PPRE1 configuration */

+#define RCC_D2CFGR_D2PPRE1_Pos                 (4U)

+#define RCC_D2CFGR_D2PPRE1_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000070 */

+#define RCC_D2CFGR_D2PPRE1                     RCC_D2CFGR_D2PPRE1_Msk          /*!< D1PPRE1[2:0] bits (APB1 prescaler) */

+#define RCC_D2CFGR_D2PPRE1_0                   (0x1UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000010 */

+#define RCC_D2CFGR_D2PPRE1_1                   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */

+#define RCC_D2CFGR_D2PPRE1_2                   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */

+

+#define RCC_D2CFGR_D2PPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */

+#define RCC_D2CFGR_D2PPRE1_DIV2_Pos            (6U)

+#define RCC_D2CFGR_D2PPRE1_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_D2CFGR_D2PPRE1_DIV2                RCC_D2CFGR_D2PPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */

+#define RCC_D2CFGR_D2PPRE1_DIV4_Pos            (4U)

+#define RCC_D2CFGR_D2PPRE1_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE1_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_D2CFGR_D2PPRE1_DIV4                RCC_D2CFGR_D2PPRE1_DIV4_Msk     /*!< APB1 clock divided by 4 */

+#define RCC_D2CFGR_D2PPRE1_DIV8_Pos            (5U)

+#define RCC_D2CFGR_D2PPRE1_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE1_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_D2CFGR_D2PPRE1_DIV8                RCC_D2CFGR_D2PPRE1_DIV8_Msk     /*!< APB1 clock divided by 8 */

+#define RCC_D2CFGR_D2PPRE1_DIV16_Pos           (4U)

+#define RCC_D2CFGR_D2PPRE1_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE1_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_D2CFGR_D2PPRE1_DIV16               RCC_D2CFGR_D2PPRE1_DIV16_Msk    /*!< APB1 clock divided by 16 */

+

+/*!< D2PPRE2 configuration */

+#define RCC_D2CFGR_D2PPRE2_Pos                 (8U)

+#define RCC_D2CFGR_D2PPRE2_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000700 */

+#define RCC_D2CFGR_D2PPRE2                     RCC_D2CFGR_D2PPRE2_Msk          /*!< D2PPRE2[2:0] bits (APB2 prescaler) */

+#define RCC_D2CFGR_D2PPRE2_0                   (0x1UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000100 */

+#define RCC_D2CFGR_D2PPRE2_1                   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */

+#define RCC_D2CFGR_D2PPRE2_2                   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */

+

+#define RCC_D2CFGR_D2PPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */

+#define RCC_D2CFGR_D2PPRE2_DIV2_Pos            (10U)

+#define RCC_D2CFGR_D2PPRE2_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */

+#define RCC_D2CFGR_D2PPRE2_DIV2                RCC_D2CFGR_D2PPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */

+#define RCC_D2CFGR_D2PPRE2_DIV4_Pos            (8U)

+#define RCC_D2CFGR_D2PPRE2_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE2_DIV4_Pos) /*!< 0x00000500 */

+#define RCC_D2CFGR_D2PPRE2_DIV4                RCC_D2CFGR_D2PPRE2_DIV4_Msk     /*!< APB2 clock divided by 4 */

+#define RCC_D2CFGR_D2PPRE2_DIV8_Pos            (9U)

+#define RCC_D2CFGR_D2PPRE2_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE2_DIV8_Pos) /*!< 0x00000600 */

+#define RCC_D2CFGR_D2PPRE2_DIV8                RCC_D2CFGR_D2PPRE2_DIV8_Msk     /*!< APB2 clock divided by 8 */

+#define RCC_D2CFGR_D2PPRE2_DIV16_Pos           (8U)

+#define RCC_D2CFGR_D2PPRE2_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE2_DIV16_Pos) /*!< 0x00000700 */

+#define RCC_D2CFGR_D2PPRE2_DIV16               RCC_D2CFGR_D2PPRE2_DIV16_Msk    /*!< APB2 clock divided by 16 */

+

+/********************  Bit definition for RCC_D3CFGR register  ******************/

+/*!< D3PPRE configuration */

+#define RCC_D3CFGR_D3PPRE_Pos                  (4U)

+#define RCC_D3CFGR_D3PPRE_Msk                  (0x7UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000070 */

+#define RCC_D3CFGR_D3PPRE                      RCC_D3CFGR_D3PPRE_Msk           /*!< D3PPRE1[2:0] bits (APB4 prescaler) */

+#define RCC_D3CFGR_D3PPRE_0                    (0x1UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000010 */

+#define RCC_D3CFGR_D3PPRE_1                    (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */

+#define RCC_D3CFGR_D3PPRE_2                    (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */

+

+#define RCC_D3CFGR_D3PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */

+#define RCC_D3CFGR_D3PPRE_DIV2_Pos             (6U)

+#define RCC_D3CFGR_D3PPRE_DIV2_Msk             (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_D3CFGR_D3PPRE_DIV2                 RCC_D3CFGR_D3PPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */

+#define RCC_D3CFGR_D3PPRE_DIV4_Pos             (4U)

+#define RCC_D3CFGR_D3PPRE_DIV4_Msk             (0x5UL << RCC_D3CFGR_D3PPRE_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_D3CFGR_D3PPRE_DIV4                 RCC_D3CFGR_D3PPRE_DIV4_Msk      /*!< APB4 clock divided by 4 */

+#define RCC_D3CFGR_D3PPRE_DIV8_Pos             (5U)

+#define RCC_D3CFGR_D3PPRE_DIV8_Msk             (0x3UL << RCC_D3CFGR_D3PPRE_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_D3CFGR_D3PPRE_DIV8                 RCC_D3CFGR_D3PPRE_DIV8_Msk      /*!< APB4 clock divided by 8 */

+#define RCC_D3CFGR_D3PPRE_DIV16_Pos            (4U)

+#define RCC_D3CFGR_D3PPRE_DIV16_Msk            (0x7UL << RCC_D3CFGR_D3PPRE_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_D3CFGR_D3PPRE_DIV16                RCC_D3CFGR_D3PPRE_DIV16_Msk     /*!< APB4 clock divided by 16 */

+

+/********************  Bit definition for RCC_PLLCKSELR register  *************/

+

+#define RCC_PLLCKSELR_PLLSRC_Pos               (0U)

+#define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */

+#define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk

+

+#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)

+#define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */

+#define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_HSE_Pos           (1U)

+#define RCC_PLLCKSELR_PLLSRC_HSE_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */

+#define RCC_PLLCKSELR_PLLSRC_HSE               RCC_PLLCKSELR_PLLSRC_HSE_Msk    /*!< HSE source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_NONE_Pos          (0U)

+#define RCC_PLLCKSELR_PLLSRC_NONE_Msk          (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */

+#define RCC_PLLCKSELR_PLLSRC_NONE              RCC_PLLCKSELR_PLLSRC_NONE_Msk   /*!< No source clock selected  */

+

+#define RCC_PLLCKSELR_DIVM1_Pos                (4U)

+#define RCC_PLLCKSELR_DIVM1_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */

+#define RCC_PLLCKSELR_DIVM1                    RCC_PLLCKSELR_DIVM1_Msk

+#define RCC_PLLCKSELR_DIVM1_0                  (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */

+#define RCC_PLLCKSELR_DIVM1_1                  (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */

+#define RCC_PLLCKSELR_DIVM1_2                  (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */

+#define RCC_PLLCKSELR_DIVM1_3                  (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */

+#define RCC_PLLCKSELR_DIVM1_4                  (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */

+#define RCC_PLLCKSELR_DIVM1_5                  (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */

+

+#define RCC_PLLCKSELR_DIVM2_Pos                (12U)

+#define RCC_PLLCKSELR_DIVM2_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */

+#define RCC_PLLCKSELR_DIVM2                    RCC_PLLCKSELR_DIVM2_Msk

+#define RCC_PLLCKSELR_DIVM2_0                  (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */

+#define RCC_PLLCKSELR_DIVM2_1                  (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */

+#define RCC_PLLCKSELR_DIVM2_2                  (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */

+#define RCC_PLLCKSELR_DIVM2_3                  (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */

+#define RCC_PLLCKSELR_DIVM2_4                  (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */

+#define RCC_PLLCKSELR_DIVM2_5                  (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */

+

+#define RCC_PLLCKSELR_DIVM3_Pos                (20U)

+#define RCC_PLLCKSELR_DIVM3_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */

+#define RCC_PLLCKSELR_DIVM3                    RCC_PLLCKSELR_DIVM3_Msk

+#define RCC_PLLCKSELR_DIVM3_0                  (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */

+#define RCC_PLLCKSELR_DIVM3_1                  (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */

+#define RCC_PLLCKSELR_DIVM3_2                  (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */

+#define RCC_PLLCKSELR_DIVM3_3                  (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */

+#define RCC_PLLCKSELR_DIVM3_4                  (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */

+#define RCC_PLLCKSELR_DIVM3_5                  (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */

+

+/********************  Bit definition for RCC_PLLCFGR register  ***************/

+

+#define RCC_PLLCFGR_PLL1FRACEN_Pos             (0U)

+#define RCC_PLLCFGR_PLL1FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */

+#define RCC_PLLCFGR_PLL1FRACEN                 RCC_PLLCFGR_PLL1FRACEN_Msk

+#define RCC_PLLCFGR_PLL1VCOSEL_Pos             (1U)

+#define RCC_PLLCFGR_PLL1VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */

+#define RCC_PLLCFGR_PLL1VCOSEL                 RCC_PLLCFGR_PLL1VCOSEL_Msk

+#define RCC_PLLCFGR_PLL1RGE_Pos                (2U)

+#define RCC_PLLCFGR_PLL1RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */

+#define RCC_PLLCFGR_PLL1RGE                    RCC_PLLCFGR_PLL1RGE_Msk

+#define RCC_PLLCFGR_PLL1RGE_0                  (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL1RGE_1                  (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */

+#define RCC_PLLCFGR_PLL1RGE_2                  (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */

+#define RCC_PLLCFGR_PLL1RGE_3                  (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */

+

+#define RCC_PLLCFGR_PLL2FRACEN_Pos             (4U)

+#define RCC_PLLCFGR_PLL2FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */

+#define RCC_PLLCFGR_PLL2FRACEN                 RCC_PLLCFGR_PLL2FRACEN_Msk

+#define RCC_PLLCFGR_PLL2VCOSEL_Pos             (5U)

+#define RCC_PLLCFGR_PLL2VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */

+#define RCC_PLLCFGR_PLL2VCOSEL                 RCC_PLLCFGR_PLL2VCOSEL_Msk

+#define RCC_PLLCFGR_PLL2RGE_Pos                (6U)

+#define RCC_PLLCFGR_PLL2RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */

+#define RCC_PLLCFGR_PLL2RGE                    RCC_PLLCFGR_PLL2RGE_Msk

+#define RCC_PLLCFGR_PLL2RGE_0                  (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL2RGE_1                  (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */

+#define RCC_PLLCFGR_PLL2RGE_2                  (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */

+#define RCC_PLLCFGR_PLL2RGE_3                  (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */

+

+#define RCC_PLLCFGR_PLL3FRACEN_Pos             (8U)

+#define RCC_PLLCFGR_PLL3FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */

+#define RCC_PLLCFGR_PLL3FRACEN                 RCC_PLLCFGR_PLL3FRACEN_Msk

+#define RCC_PLLCFGR_PLL3VCOSEL_Pos             (9U)

+#define RCC_PLLCFGR_PLL3VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */

+#define RCC_PLLCFGR_PLL3VCOSEL                 RCC_PLLCFGR_PLL3VCOSEL_Msk

+#define RCC_PLLCFGR_PLL3RGE_Pos                (10U)

+#define RCC_PLLCFGR_PLL3RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */

+#define RCC_PLLCFGR_PLL3RGE                    RCC_PLLCFGR_PLL3RGE_Msk

+#define RCC_PLLCFGR_PLL3RGE_0                  (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL3RGE_1                  (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */

+#define RCC_PLLCFGR_PLL3RGE_2                  (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */

+#define RCC_PLLCFGR_PLL3RGE_3                  (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */

+

+#define RCC_PLLCFGR_DIVP1EN_Pos                (16U)

+#define RCC_PLLCFGR_DIVP1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */

+#define RCC_PLLCFGR_DIVP1EN                    RCC_PLLCFGR_DIVP1EN_Msk

+#define RCC_PLLCFGR_DIVQ1EN_Pos                (17U)

+#define RCC_PLLCFGR_DIVQ1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */

+#define RCC_PLLCFGR_DIVQ1EN                    RCC_PLLCFGR_DIVQ1EN_Msk

+#define RCC_PLLCFGR_DIVR1EN_Pos                (18U)

+#define RCC_PLLCFGR_DIVR1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */

+#define RCC_PLLCFGR_DIVR1EN                    RCC_PLLCFGR_DIVR1EN_Msk

+

+#define RCC_PLLCFGR_DIVP2EN_Pos                (19U)

+#define RCC_PLLCFGR_DIVP2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */

+#define RCC_PLLCFGR_DIVP2EN                    RCC_PLLCFGR_DIVP2EN_Msk

+#define RCC_PLLCFGR_DIVQ2EN_Pos                (20U)

+#define RCC_PLLCFGR_DIVQ2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */

+#define RCC_PLLCFGR_DIVQ2EN                    RCC_PLLCFGR_DIVQ2EN_Msk

+#define RCC_PLLCFGR_DIVR2EN_Pos                (21U)

+#define RCC_PLLCFGR_DIVR2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */

+#define RCC_PLLCFGR_DIVR2EN                    RCC_PLLCFGR_DIVR2EN_Msk

+

+#define RCC_PLLCFGR_DIVP3EN_Pos                (22U)

+#define RCC_PLLCFGR_DIVP3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */

+#define RCC_PLLCFGR_DIVP3EN                    RCC_PLLCFGR_DIVP3EN_Msk

+#define RCC_PLLCFGR_DIVQ3EN_Pos                (23U)

+#define RCC_PLLCFGR_DIVQ3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */

+#define RCC_PLLCFGR_DIVQ3EN                    RCC_PLLCFGR_DIVQ3EN_Msk

+#define RCC_PLLCFGR_DIVR3EN_Pos                (24U)

+#define RCC_PLLCFGR_DIVR3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */

+#define RCC_PLLCFGR_DIVR3EN                    RCC_PLLCFGR_DIVR3EN_Msk

+

+

+/********************  Bit definition for RCC_PLL1DIVR register  ***************/

+#define RCC_PLL1DIVR_N1_Pos                    (0U)

+#define RCC_PLL1DIVR_N1_Msk                    (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */

+#define RCC_PLL1DIVR_N1                        RCC_PLL1DIVR_N1_Msk

+#define RCC_PLL1DIVR_P1_Pos                    (9U)

+#define RCC_PLL1DIVR_P1_Msk                    (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL1DIVR_P1                        RCC_PLL1DIVR_P1_Msk

+#define RCC_PLL1DIVR_Q1_Pos                    (16U)

+#define RCC_PLL1DIVR_Q1_Msk                    (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */

+#define RCC_PLL1DIVR_Q1                        RCC_PLL1DIVR_Q1_Msk

+#define RCC_PLL1DIVR_R1_Pos                    (24U)

+#define RCC_PLL1DIVR_R1_Msk                    (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */

+#define RCC_PLL1DIVR_R1                        RCC_PLL1DIVR_R1_Msk

+

+/********************  Bit definition for RCC_PLL1FRACR register  ***************/

+#define RCC_PLL1FRACR_FRACN1_Pos               (3U)

+#define RCC_PLL1FRACR_FRACN1_Msk               (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL1FRACR_FRACN1                   RCC_PLL1FRACR_FRACN1_Msk

+

+/********************  Bit definition for RCC_PLL2DIVR register  ***************/

+#define RCC_PLL2DIVR_N2_Pos                    (0U)

+#define RCC_PLL2DIVR_N2_Msk                    (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */

+#define RCC_PLL2DIVR_N2                        RCC_PLL2DIVR_N2_Msk

+#define RCC_PLL2DIVR_P2_Pos                    (9U)

+#define RCC_PLL2DIVR_P2_Msk                    (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL2DIVR_P2                        RCC_PLL2DIVR_P2_Msk

+#define RCC_PLL2DIVR_Q2_Pos                    (16U)

+#define RCC_PLL2DIVR_Q2_Msk                    (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */

+#define RCC_PLL2DIVR_Q2                        RCC_PLL2DIVR_Q2_Msk

+#define RCC_PLL2DIVR_R2_Pos                    (24U)

+#define RCC_PLL2DIVR_R2_Msk                    (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */

+#define RCC_PLL2DIVR_R2                        RCC_PLL2DIVR_R2_Msk

+

+/********************  Bit definition for RCC_PLL2FRACR register  ***************/

+#define RCC_PLL2FRACR_FRACN2_Pos               (3U)

+#define RCC_PLL2FRACR_FRACN2_Msk               (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL2FRACR_FRACN2                   RCC_PLL2FRACR_FRACN2_Msk

+

+/********************  Bit definition for RCC_PLL3DIVR register  ***************/

+#define RCC_PLL3DIVR_N3_Pos                    (0U)

+#define RCC_PLL3DIVR_N3_Msk                    (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */

+#define RCC_PLL3DIVR_N3                        RCC_PLL3DIVR_N3_Msk

+#define RCC_PLL3DIVR_P3_Pos                    (9U)

+#define RCC_PLL3DIVR_P3_Msk                    (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL3DIVR_P3                        RCC_PLL3DIVR_P3_Msk

+#define RCC_PLL3DIVR_Q3_Pos                    (16U)

+#define RCC_PLL3DIVR_Q3_Msk                    (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */

+#define RCC_PLL3DIVR_Q3                        RCC_PLL3DIVR_Q3_Msk

+#define RCC_PLL3DIVR_R3_Pos                    (24U)

+#define RCC_PLL3DIVR_R3_Msk                    (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */

+#define RCC_PLL3DIVR_R3                        RCC_PLL3DIVR_R3_Msk

+

+/********************  Bit definition for RCC_PLL3FRACR register  ***************/

+#define RCC_PLL3FRACR_FRACN3_Pos               (3U)

+#define RCC_PLL3FRACR_FRACN3_Msk               (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL3FRACR_FRACN3                   RCC_PLL3FRACR_FRACN3_Msk

+

+/********************  Bit definition for RCC_D1CCIPR register  ***************/

+#define RCC_D1CCIPR_FMCSEL_Pos                 (0U)

+#define RCC_D1CCIPR_FMCSEL_Msk                 (0x3UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000003 */

+#define RCC_D1CCIPR_FMCSEL                     RCC_D1CCIPR_FMCSEL_Msk

+#define RCC_D1CCIPR_FMCSEL_0                   (0x1UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000001 */

+#define RCC_D1CCIPR_FMCSEL_1                   (0x2UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000002 */

+#define RCC_D1CCIPR_QSPISEL_Pos                (4U)

+#define RCC_D1CCIPR_QSPISEL_Msk                (0x3UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000030 */

+#define RCC_D1CCIPR_QSPISEL                    RCC_D1CCIPR_QSPISEL_Msk

+#define RCC_D1CCIPR_QSPISEL_0                  (0x1UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000010 */

+#define RCC_D1CCIPR_QSPISEL_1                  (0x2UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000020 */

+#define RCC_D1CCIPR_SDMMCSEL_Pos               (16U)

+#define RCC_D1CCIPR_SDMMCSEL_Msk               (0x1UL << RCC_D1CCIPR_SDMMCSEL_Pos) /*!< 0x00010000 */

+#define RCC_D1CCIPR_SDMMCSEL                   RCC_D1CCIPR_SDMMCSEL_Msk

+#define RCC_D1CCIPR_CKPERSEL_Pos               (28U)

+#define RCC_D1CCIPR_CKPERSEL_Msk               (0x3UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x30000000 */

+#define RCC_D1CCIPR_CKPERSEL                   RCC_D1CCIPR_CKPERSEL_Msk

+#define RCC_D1CCIPR_CKPERSEL_0                 (0x1UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x10000000 */

+#define RCC_D1CCIPR_CKPERSEL_1                 (0x2UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x20000000 */

+

+/********************  Bit definition for RCC_D2CCIP1R register  ***************/

+#define RCC_D2CCIP1R_SAI1SEL_Pos               (0U)

+#define RCC_D2CCIP1R_SAI1SEL_Msk               (0x7UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000007 */

+#define RCC_D2CCIP1R_SAI1SEL                   RCC_D2CCIP1R_SAI1SEL_Msk

+#define RCC_D2CCIP1R_SAI1SEL_0                 (0x1UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000001 */

+#define RCC_D2CCIP1R_SAI1SEL_1                 (0x2UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000002 */

+#define RCC_D2CCIP1R_SAI1SEL_2                 (0x4UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000004 */

+

+#define RCC_D2CCIP1R_SAI23SEL_Pos              (6U)

+#define RCC_D2CCIP1R_SAI23SEL_Msk              (0x7UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x000001C0 */

+#define RCC_D2CCIP1R_SAI23SEL                  RCC_D2CCIP1R_SAI23SEL_Msk

+#define RCC_D2CCIP1R_SAI23SEL_0                (0x1UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000040 */

+#define RCC_D2CCIP1R_SAI23SEL_1                (0x2UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000080 */

+#define RCC_D2CCIP1R_SAI23SEL_2                (0x4UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000100 */

+

+#define RCC_D2CCIP1R_SPI123SEL_Pos             (12U)

+#define RCC_D2CCIP1R_SPI123SEL_Msk             (0x7UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */

+#define RCC_D2CCIP1R_SPI123SEL                 RCC_D2CCIP1R_SPI123SEL_Msk

+#define RCC_D2CCIP1R_SPI123SEL_0               (0x1UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */

+#define RCC_D2CCIP1R_SPI123SEL_1               (0x2UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */

+#define RCC_D2CCIP1R_SPI123SEL_2               (0x4UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */

+

+#define RCC_D2CCIP1R_SPI45SEL_Pos              (16U)

+#define RCC_D2CCIP1R_SPI45SEL_Msk              (0x7UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00070000 */

+#define RCC_D2CCIP1R_SPI45SEL                  RCC_D2CCIP1R_SPI45SEL_Msk

+#define RCC_D2CCIP1R_SPI45SEL_0                (0x1UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00010000 */

+#define RCC_D2CCIP1R_SPI45SEL_1                (0x2UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00020000 */

+#define RCC_D2CCIP1R_SPI45SEL_2                (0x4UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00040000 */

+

+#define RCC_D2CCIP1R_SPDIFSEL_Pos              (20U)

+#define RCC_D2CCIP1R_SPDIFSEL_Msk              (0x3UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00300000 */

+#define RCC_D2CCIP1R_SPDIFSEL                  RCC_D2CCIP1R_SPDIFSEL_Msk

+#define RCC_D2CCIP1R_SPDIFSEL_0                (0x1UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00100000 */

+#define RCC_D2CCIP1R_SPDIFSEL_1                (0x2UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00200000 */

+

+#define RCC_D2CCIP1R_DFSDM1SEL_Pos             (24U)

+#define RCC_D2CCIP1R_DFSDM1SEL_Msk             (0x1UL << RCC_D2CCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */

+#define RCC_D2CCIP1R_DFSDM1SEL                 RCC_D2CCIP1R_DFSDM1SEL_Msk

+

+#define RCC_D2CCIP1R_FDCANSEL_Pos              (28U)

+#define RCC_D2CCIP1R_FDCANSEL_Msk              (0x3UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x30000000 */

+#define RCC_D2CCIP1R_FDCANSEL                  RCC_D2CCIP1R_FDCANSEL_Msk

+#define RCC_D2CCIP1R_FDCANSEL_0                (0x1UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x10000000 */

+#define RCC_D2CCIP1R_FDCANSEL_1                (0x2UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x20000000 */

+

+#define RCC_D2CCIP1R_SWPSEL_Pos                (31U)

+#define RCC_D2CCIP1R_SWPSEL_Msk                (0x1UL << RCC_D2CCIP1R_SWPSEL_Pos) /*!< 0x80000000 */

+#define RCC_D2CCIP1R_SWPSEL                    RCC_D2CCIP1R_SWPSEL_Msk

+

+/********************  Bit definition for RCC_D2CCIP2R register  ***************/

+#define RCC_D2CCIP2R_USART16SEL_Pos            (3U)

+#define RCC_D2CCIP2R_USART16SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000038 */

+#define RCC_D2CCIP2R_USART16SEL                RCC_D2CCIP2R_USART16SEL_Msk

+#define RCC_D2CCIP2R_USART16SEL_0              (0x1UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000008 */

+#define RCC_D2CCIP2R_USART16SEL_1              (0x2UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000010 */

+#define RCC_D2CCIP2R_USART16SEL_2              (0x4UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000020 */

+

+#define RCC_D2CCIP2R_USART28SEL_Pos            (0U)

+#define RCC_D2CCIP2R_USART28SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000007 */

+#define RCC_D2CCIP2R_USART28SEL                RCC_D2CCIP2R_USART28SEL_Msk

+#define RCC_D2CCIP2R_USART28SEL_0              (0x1UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000001 */

+#define RCC_D2CCIP2R_USART28SEL_1              (0x2UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000002 */

+#define RCC_D2CCIP2R_USART28SEL_2              (0x4UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000004 */

+

+#define RCC_D2CCIP2R_RNGSEL_Pos                (8U)

+#define RCC_D2CCIP2R_RNGSEL_Msk                (0x3UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000300 */

+#define RCC_D2CCIP2R_RNGSEL                    RCC_D2CCIP2R_RNGSEL_Msk

+#define RCC_D2CCIP2R_RNGSEL_0                  (0x1UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000100 */

+#define RCC_D2CCIP2R_RNGSEL_1                  (0x2UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000200 */

+

+#define RCC_D2CCIP2R_I2C123SEL_Pos             (12U)

+#define RCC_D2CCIP2R_I2C123SEL_Msk             (0x3UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00003000 */

+#define RCC_D2CCIP2R_I2C123SEL                 RCC_D2CCIP2R_I2C123SEL_Msk

+#define RCC_D2CCIP2R_I2C123SEL_0               (0x1UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00001000 */

+#define RCC_D2CCIP2R_I2C123SEL_1               (0x2UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00002000 */

+

+#define RCC_D2CCIP2R_USBSEL_Pos                (20U)

+#define RCC_D2CCIP2R_USBSEL_Msk                (0x3UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00300000 */

+#define RCC_D2CCIP2R_USBSEL                    RCC_D2CCIP2R_USBSEL_Msk

+#define RCC_D2CCIP2R_USBSEL_0                  (0x1UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00100000 */

+#define RCC_D2CCIP2R_USBSEL_1                  (0x2UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00200000 */

+

+#define RCC_D2CCIP2R_CECSEL_Pos                (22U)

+#define RCC_D2CCIP2R_CECSEL_Msk                (0x3UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00C00000 */

+#define RCC_D2CCIP2R_CECSEL                    RCC_D2CCIP2R_CECSEL_Msk

+#define RCC_D2CCIP2R_CECSEL_0                  (0x1UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00400000 */

+#define RCC_D2CCIP2R_CECSEL_1                  (0x2UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00800000 */

+

+#define RCC_D2CCIP2R_LPTIM1SEL_Pos             (28U)

+#define RCC_D2CCIP2R_LPTIM1SEL_Msk             (0x7UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x70000000 */

+#define RCC_D2CCIP2R_LPTIM1SEL                 RCC_D2CCIP2R_LPTIM1SEL_Msk

+#define RCC_D2CCIP2R_LPTIM1SEL_0               (0x1UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x10000000 */

+#define RCC_D2CCIP2R_LPTIM1SEL_1               (0x2UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x20000000 */

+#define RCC_D2CCIP2R_LPTIM1SEL_2               (0x4UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition for RCC_D3CCIPR register  ***************/

+#define RCC_D3CCIPR_LPUART1SEL_Pos             (0U)

+#define RCC_D3CCIPR_LPUART1SEL_Msk             (0x7UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000007 */

+#define RCC_D3CCIPR_LPUART1SEL                 RCC_D3CCIPR_LPUART1SEL_Msk

+#define RCC_D3CCIPR_LPUART1SEL_0               (0x1UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000001 */

+#define RCC_D3CCIPR_LPUART1SEL_1               (0x2UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000002 */

+#define RCC_D3CCIPR_LPUART1SEL_2               (0x4UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000004 */

+

+#define RCC_D3CCIPR_I2C4SEL_Pos                (8U)

+#define RCC_D3CCIPR_I2C4SEL_Msk                (0x3UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000300 */

+#define RCC_D3CCIPR_I2C4SEL                    RCC_D3CCIPR_I2C4SEL_Msk

+#define RCC_D3CCIPR_I2C4SEL_0                  (0x1UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000100 */

+#define RCC_D3CCIPR_I2C4SEL_1                  (0x2UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000200 */

+

+#define RCC_D3CCIPR_LPTIM2SEL_Pos              (10U)

+#define RCC_D3CCIPR_LPTIM2SEL_Msk              (0x7UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001C00 */

+#define RCC_D3CCIPR_LPTIM2SEL                  RCC_D3CCIPR_LPTIM2SEL_Msk

+#define RCC_D3CCIPR_LPTIM2SEL_0                (0x1UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000400 */

+#define RCC_D3CCIPR_LPTIM2SEL_1                (0x2UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000800 */

+#define RCC_D3CCIPR_LPTIM2SEL_2                (0x4UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001000 */

+

+#define RCC_D3CCIPR_LPTIM345SEL_Pos            (13U)

+#define RCC_D3CCIPR_LPTIM345SEL_Msk            (0x7UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x0000E000 */

+#define RCC_D3CCIPR_LPTIM345SEL                RCC_D3CCIPR_LPTIM345SEL_Msk

+#define RCC_D3CCIPR_LPTIM345SEL_0              (0x1UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00002000 */

+#define RCC_D3CCIPR_LPTIM345SEL_1              (0x2UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00004000 */

+#define RCC_D3CCIPR_LPTIM345SEL_2              (0x4UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00008000 */

+

+#define RCC_D3CCIPR_SAI4ASEL_Pos               (21U)

+#define RCC_D3CCIPR_SAI4ASEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00E00000 */

+#define RCC_D3CCIPR_SAI4ASEL                   RCC_D3CCIPR_SAI4ASEL_Msk

+#define RCC_D3CCIPR_SAI4ASEL_0                 (0x1UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00200000 */

+#define RCC_D3CCIPR_SAI4ASEL_1                 (0x2UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00400000 */

+#define RCC_D3CCIPR_SAI4ASEL_2                 (0x4UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00800000 */

+

+#define RCC_D3CCIPR_SAI4BSEL_Pos               (24U)

+#define RCC_D3CCIPR_SAI4BSEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x07000000 */

+#define RCC_D3CCIPR_SAI4BSEL                   RCC_D3CCIPR_SAI4BSEL_Msk

+#define RCC_D3CCIPR_SAI4BSEL_0                 (0x1UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x01000000 */

+#define RCC_D3CCIPR_SAI4BSEL_1                 (0x2UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x02000000 */

+#define RCC_D3CCIPR_SAI4BSEL_2                 (0x4UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x04000000 */

+

+#define RCC_D3CCIPR_ADCSEL_Pos                 (16U)

+#define RCC_D3CCIPR_ADCSEL_Msk                 (0x3UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00030000 */

+#define RCC_D3CCIPR_ADCSEL                     RCC_D3CCIPR_ADCSEL_Msk

+#define RCC_D3CCIPR_ADCSEL_0                   (0x1UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00010000 */

+#define RCC_D3CCIPR_ADCSEL_1                   (0x2UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00020000 */

+

+#define RCC_D3CCIPR_SPI6SEL_Pos                (28U)

+#define RCC_D3CCIPR_SPI6SEL_Msk                (0x7UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x70000000 */

+#define RCC_D3CCIPR_SPI6SEL                    RCC_D3CCIPR_SPI6SEL_Msk

+#define RCC_D3CCIPR_SPI6SEL_0                  (0x1UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x10000000 */

+#define RCC_D3CCIPR_SPI6SEL_1                  (0x2UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x20000000 */

+#define RCC_D3CCIPR_SPI6SEL_2                  (0x4UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x40000000 */

+/********************  Bit definition for RCC_CIER register  ******************/

+#define RCC_CIER_LSIRDYIE_Pos                  (0U)

+#define RCC_CIER_LSIRDYIE_Msk                  (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */

+#define RCC_CIER_LSIRDYIE                      RCC_CIER_LSIRDYIE_Msk

+#define RCC_CIER_LSERDYIE_Pos                  (1U)

+#define RCC_CIER_LSERDYIE_Msk                  (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */

+#define RCC_CIER_LSERDYIE                      RCC_CIER_LSERDYIE_Msk

+#define RCC_CIER_HSIRDYIE_Pos                  (2U)

+#define RCC_CIER_HSIRDYIE_Msk                  (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */

+#define RCC_CIER_HSIRDYIE                      RCC_CIER_HSIRDYIE_Msk

+#define RCC_CIER_HSERDYIE_Pos                  (3U)

+#define RCC_CIER_HSERDYIE_Msk                  (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */

+#define RCC_CIER_HSERDYIE                      RCC_CIER_HSERDYIE_Msk

+#define RCC_CIER_CSIRDYIE_Pos                  (4U)

+#define RCC_CIER_CSIRDYIE_Msk                  (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */

+#define RCC_CIER_CSIRDYIE                      RCC_CIER_CSIRDYIE_Msk

+#define RCC_CIER_HSI48RDYIE_Pos                (5U)

+#define RCC_CIER_HSI48RDYIE_Msk                (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */

+#define RCC_CIER_HSI48RDYIE                    RCC_CIER_HSI48RDYIE_Msk

+#define RCC_CIER_PLL1RDYIE_Pos                 (6U)

+#define RCC_CIER_PLL1RDYIE_Msk                 (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */

+#define RCC_CIER_PLL1RDYIE                     RCC_CIER_PLL1RDYIE_Msk

+#define RCC_CIER_PLL2RDYIE_Pos                 (7U)

+#define RCC_CIER_PLL2RDYIE_Msk                 (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */

+#define RCC_CIER_PLL2RDYIE                     RCC_CIER_PLL2RDYIE_Msk

+#define RCC_CIER_PLL3RDYIE_Pos                 (8U)

+#define RCC_CIER_PLL3RDYIE_Msk                 (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */

+#define RCC_CIER_PLL3RDYIE                     RCC_CIER_PLL3RDYIE_Msk

+#define RCC_CIER_LSECSSIE_Pos                  (9U)

+#define RCC_CIER_LSECSSIE_Msk                  (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */

+#define RCC_CIER_LSECSSIE                      RCC_CIER_LSECSSIE_Msk

+

+/********************  Bit definition for RCC_CIFR register  ******************/

+#define RCC_CIFR_LSIRDYF_Pos                   (0U)

+#define RCC_CIFR_LSIRDYF_Msk                   (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */

+#define RCC_CIFR_LSIRDYF                       RCC_CIFR_LSIRDYF_Msk

+#define RCC_CIFR_LSERDYF_Pos                   (1U)

+#define RCC_CIFR_LSERDYF_Msk                   (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */

+#define RCC_CIFR_LSERDYF                       RCC_CIFR_LSERDYF_Msk

+#define RCC_CIFR_HSIRDYF_Pos                   (2U)

+#define RCC_CIFR_HSIRDYF_Msk                   (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */

+#define RCC_CIFR_HSIRDYF                       RCC_CIFR_HSIRDYF_Msk

+#define RCC_CIFR_HSERDYF_Pos                   (3U)

+#define RCC_CIFR_HSERDYF_Msk                   (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */

+#define RCC_CIFR_HSERDYF                       RCC_CIFR_HSERDYF_Msk

+#define RCC_CIFR_CSIRDYF_Pos                   (4U)

+#define RCC_CIFR_CSIRDYF_Msk                   (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */

+#define RCC_CIFR_CSIRDYF                       RCC_CIFR_CSIRDYF_Msk

+#define RCC_CIFR_HSI48RDYF_Pos                 (5U)

+#define RCC_CIFR_HSI48RDYF_Msk                 (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */

+#define RCC_CIFR_HSI48RDYF                     RCC_CIFR_HSI48RDYF_Msk

+#define RCC_CIFR_PLLRDYF_Pos                   (6U)

+#define RCC_CIFR_PLLRDYF_Msk                   (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */

+#define RCC_CIFR_PLLRDYF                       RCC_CIFR_PLLRDYF_Msk

+#define RCC_CIFR_PLL2RDYF_Pos                  (7U)

+#define RCC_CIFR_PLL2RDYF_Msk                  (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */

+#define RCC_CIFR_PLL2RDYF                      RCC_CIFR_PLL2RDYF_Msk

+#define RCC_CIFR_PLL3RDYF_Pos                  (8U)

+#define RCC_CIFR_PLL3RDYF_Msk                  (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */

+#define RCC_CIFR_PLL3RDYF                      RCC_CIFR_PLL3RDYF_Msk

+#define RCC_CIFR_LSECSSF_Pos                   (9U)

+#define RCC_CIFR_LSECSSF_Msk                   (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */

+#define RCC_CIFR_LSECSSF                       RCC_CIFR_LSECSSF_Msk

+#define RCC_CIFR_HSECSSF_Pos                   (10U)

+#define RCC_CIFR_HSECSSF_Msk                   (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */

+#define RCC_CIFR_HSECSSF                       RCC_CIFR_HSECSSF_Msk

+

+/********************  Bit definition for RCC_CICR register  ******************/

+#define RCC_CICR_LSIRDYC_Pos                   (0U)

+#define RCC_CICR_LSIRDYC_Msk                   (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */

+#define RCC_CICR_LSIRDYC                       RCC_CICR_LSIRDYC_Msk

+#define RCC_CICR_LSERDYC_Pos                   (1U)

+#define RCC_CICR_LSERDYC_Msk                   (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */

+#define RCC_CICR_LSERDYC                       RCC_CICR_LSERDYC_Msk

+#define RCC_CICR_HSIRDYC_Pos                   (2U)

+#define RCC_CICR_HSIRDYC_Msk                   (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */

+#define RCC_CICR_HSIRDYC                       RCC_CICR_HSIRDYC_Msk

+#define RCC_CICR_HSERDYC_Pos                   (3U)

+#define RCC_CICR_HSERDYC_Msk                   (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */

+#define RCC_CICR_HSERDYC                       RCC_CICR_HSERDYC_Msk

+#define RCC_CICR_CSIRDYC_Pos                   (4U)

+#define RCC_CICR_CSIRDYC_Msk                   (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */

+#define RCC_CICR_CSIRDYC                       RCC_CICR_CSIRDYC_Msk

+#define RCC_CICR_HSI48RDYC_Pos                 (5U)

+#define RCC_CICR_HSI48RDYC_Msk                 (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */

+#define RCC_CICR_HSI48RDYC                     RCC_CICR_HSI48RDYC_Msk

+#define RCC_CICR_PLLRDYC_Pos                   (6U)

+#define RCC_CICR_PLLRDYC_Msk                   (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */

+#define RCC_CICR_PLLRDYC                       RCC_CICR_PLLRDYC_Msk

+#define RCC_CICR_PLL2RDYC_Pos                  (7U)

+#define RCC_CICR_PLL2RDYC_Msk                  (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */

+#define RCC_CICR_PLL2RDYC                      RCC_CICR_PLL2RDYC_Msk

+#define RCC_CICR_PLL3RDYC_Pos                  (8U)

+#define RCC_CICR_PLL3RDYC_Msk                  (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */

+#define RCC_CICR_PLL3RDYC                      RCC_CICR_PLL3RDYC_Msk

+#define RCC_CICR_LSECSSC_Pos                   (9U)

+#define RCC_CICR_LSECSSC_Msk                   (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */

+#define RCC_CICR_LSECSSC                       RCC_CICR_LSECSSC_Msk

+#define RCC_CICR_HSECSSC_Pos                   (10U)

+#define RCC_CICR_HSECSSC_Msk                   (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */

+#define RCC_CICR_HSECSSC                       RCC_CICR_HSECSSC_Msk

+

+/********************  Bit definition for RCC_BDCR register  ******************/

+#define RCC_BDCR_LSEON_Pos                     (0U)

+#define RCC_BDCR_LSEON_Msk                     (0x1UL << RCC_BDCR_LSEON_Pos)   /*!< 0x00000001 */

+#define RCC_BDCR_LSEON                         RCC_BDCR_LSEON_Msk

+#define RCC_BDCR_LSERDY_Pos                    (1U)

+#define RCC_BDCR_LSERDY_Msk                    (0x1UL << RCC_BDCR_LSERDY_Pos)  /*!< 0x00000002 */

+#define RCC_BDCR_LSERDY                        RCC_BDCR_LSERDY_Msk

+#define RCC_BDCR_LSEBYP_Pos                    (2U)

+#define RCC_BDCR_LSEBYP_Msk                    (0x1UL << RCC_BDCR_LSEBYP_Pos)  /*!< 0x00000004 */

+#define RCC_BDCR_LSEBYP                        RCC_BDCR_LSEBYP_Msk

+

+#define RCC_BDCR_LSEDRV_Pos                    (3U)

+#define RCC_BDCR_LSEDRV_Msk                    (0x3UL << RCC_BDCR_LSEDRV_Pos)  /*!< 0x00000018 */

+#define RCC_BDCR_LSEDRV                        RCC_BDCR_LSEDRV_Msk

+#define RCC_BDCR_LSEDRV_0                      (0x1UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000008 */

+#define RCC_BDCR_LSEDRV_1                      (0x2UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000010 */

+

+#define RCC_BDCR_LSECSSON_Pos                  (5U)

+#define RCC_BDCR_LSECSSON_Msk                  (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */

+#define RCC_BDCR_LSECSSON                      RCC_BDCR_LSECSSON_Msk

+#define RCC_BDCR_LSECSSD_Pos                   (6U)

+#define RCC_BDCR_LSECSSD_Msk                   (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */

+#define RCC_BDCR_LSECSSD                       RCC_BDCR_LSECSSD_Msk

+

+#define RCC_BDCR_RTCSEL_Pos                    (8U)

+#define RCC_BDCR_RTCSEL_Msk                    (0x3UL << RCC_BDCR_RTCSEL_Pos)  /*!< 0x00000300 */

+#define RCC_BDCR_RTCSEL                        RCC_BDCR_RTCSEL_Msk

+#define RCC_BDCR_RTCSEL_0                      (0x1UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000100 */

+#define RCC_BDCR_RTCSEL_1                      (0x2UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000200 */

+

+#define RCC_BDCR_RTCEN_Pos                     (15U)

+#define RCC_BDCR_RTCEN_Msk                     (0x1UL << RCC_BDCR_RTCEN_Pos)   /*!< 0x00008000 */

+#define RCC_BDCR_RTCEN                         RCC_BDCR_RTCEN_Msk

+#define RCC_BDCR_BDRST_Pos                     (16U)

+#define RCC_BDCR_BDRST_Msk                     (0x1UL << RCC_BDCR_BDRST_Pos)   /*!< 0x00010000 */

+#define RCC_BDCR_BDRST                         RCC_BDCR_BDRST_Msk

+/********************  Bit definition for RCC_CSR register  *******************/

+#define RCC_CSR_LSION_Pos                      (0U)

+#define RCC_CSR_LSION_Msk                      (0x1UL << RCC_CSR_LSION_Pos)    /*!< 0x00000001 */

+#define RCC_CSR_LSION                          RCC_CSR_LSION_Msk

+#define RCC_CSR_LSIRDY_Pos                     (1U)

+#define RCC_CSR_LSIRDY_Msk                     (0x1UL << RCC_CSR_LSIRDY_Pos)   /*!< 0x00000002 */

+#define RCC_CSR_LSIRDY                         RCC_CSR_LSIRDY_Msk

+

+

+/********************  Bit definition for RCC_AHB3ENR register  **************/

+#define RCC_AHB3ENR_MDMAEN_Pos                 (0U)

+#define RCC_AHB3ENR_MDMAEN_Msk                 (0x1UL << RCC_AHB3ENR_MDMAEN_Pos)       /*!< 0x00000001 */

+#define RCC_AHB3ENR_MDMAEN                     RCC_AHB3ENR_MDMAEN_Msk

+#define RCC_AHB3ENR_DMA2DEN_Pos                (4U)

+#define RCC_AHB3ENR_DMA2DEN_Msk                (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos)      /*!< 0x00000010 */

+#define RCC_AHB3ENR_DMA2DEN                    RCC_AHB3ENR_DMA2DEN_Msk

+#define RCC_AHB3ENR_JPGDECEN_Pos               (5U)

+#define RCC_AHB3ENR_JPGDECEN_Msk               (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos)     /*!< 0x00000020 */

+#define RCC_AHB3ENR_JPGDECEN                   RCC_AHB3ENR_JPGDECEN_Msk

+#define RCC_AHB3ENR_FMCEN_Pos                  (12U)

+#define RCC_AHB3ENR_FMCEN_Msk                  (0x1UL << RCC_AHB3ENR_FMCEN_Pos)        /*!< 0x00001000 */

+#define RCC_AHB3ENR_FMCEN                      RCC_AHB3ENR_FMCEN_Msk

+#define RCC_AHB3ENR_QSPIEN_Pos                 (14U)

+#define RCC_AHB3ENR_QSPIEN_Msk                 (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)       /*!< 0x00004000 */

+#define RCC_AHB3ENR_QSPIEN                     RCC_AHB3ENR_QSPIEN_Msk

+#define RCC_AHB3ENR_SDMMC1EN_Pos               (16U)

+#define RCC_AHB3ENR_SDMMC1EN_Msk               (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos)     /*!< 0x00010000 */

+#define RCC_AHB3ENR_SDMMC1EN                   RCC_AHB3ENR_SDMMC1EN_Msk

+

+/********************  Bit definition for RCC_AHB1ENR register  ***************/

+#define RCC_AHB1ENR_DMA1EN_Pos                 (0U)

+#define RCC_AHB1ENR_DMA1EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)          /*!< 0x00000001 */

+#define RCC_AHB1ENR_DMA1EN                     RCC_AHB1ENR_DMA1EN_Msk

+#define RCC_AHB1ENR_DMA2EN_Pos                 (1U)

+#define RCC_AHB1ENR_DMA2EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)          /*!< 0x00000002 */

+#define RCC_AHB1ENR_DMA2EN                     RCC_AHB1ENR_DMA2EN_Msk

+#define RCC_AHB1ENR_ADC12EN_Pos                (5U)

+#define RCC_AHB1ENR_ADC12EN_Msk                (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)         /*!< 0x00000020 */

+#define RCC_AHB1ENR_ADC12EN                    RCC_AHB1ENR_ADC12EN_Msk

+#define RCC_AHB1ENR_ETH1MACEN_Pos              (15U)

+#define RCC_AHB1ENR_ETH1MACEN_Msk              (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos)       /*!< 0x00008000 */

+#define RCC_AHB1ENR_ETH1MACEN                  RCC_AHB1ENR_ETH1MACEN_Msk

+#define RCC_AHB1ENR_ETH1TXEN_Pos               (16U)

+#define RCC_AHB1ENR_ETH1TXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos)        /*!< 0x00010000 */

+#define RCC_AHB1ENR_ETH1TXEN                   RCC_AHB1ENR_ETH1TXEN_Msk

+#define RCC_AHB1ENR_ETH1RXEN_Pos               (17U)

+#define RCC_AHB1ENR_ETH1RXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos)        /*!< 0x00020000 */

+#define RCC_AHB1ENR_ETH1RXEN                   RCC_AHB1ENR_ETH1RXEN_Msk

+#define RCC_AHB1ENR_USB1OTGHSEN_Pos            (25U)

+#define RCC_AHB1ENR_USB1OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos)     /*!< 0x02000000 */

+#define RCC_AHB1ENR_USB1OTGHSEN                RCC_AHB1ENR_USB1OTGHSEN_Msk

+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos        (26U)

+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */

+#define RCC_AHB1ENR_USB1OTGHSULPIEN            RCC_AHB1ENR_USB1OTGHSULPIEN_Msk

+#define RCC_AHB1ENR_USB2OTGFSEN_Pos            (27U)

+#define RCC_AHB1ENR_USB2OTGFSEN_Msk            (0x1UL << RCC_AHB1ENR_USB2OTGFSEN_Pos)     /*!< 0x08000000 */

+#define RCC_AHB1ENR_USB2OTGFSEN                RCC_AHB1ENR_USB2OTGFSEN_Msk

+#define RCC_AHB1ENR_USB2OTGFSULPIEN_Pos        (28U)

+#define RCC_AHB1ENR_USB2OTGFSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB2OTGFSULPIEN_Pos) /*!< 0x10000000 */

+#define RCC_AHB1ENR_USB2OTGFSULPIEN            RCC_AHB1ENR_USB2OTGFSULPIEN_Msk

+

+/* Legacy define */

+#define RCC_AHB1ENR_USB2OTGHSEN_Pos            RCC_AHB1ENR_USB2OTGFSEN_Pos

+#define RCC_AHB1ENR_USB2OTGHSEN_Msk            RCC_AHB1ENR_USB2OTGFSEN_Msk

+#define RCC_AHB1ENR_USB2OTGHSEN                RCC_AHB1ENR_USB2OTGFSEN

+#define RCC_AHB1ENR_USB2OTGHSULPIEN_Pos        RCC_AHB1ENR_USB2OTGFSULPIEN_Pos

+#define RCC_AHB1ENR_USB2OTGHSULPIEN_Msk        RCC_AHB1ENR_USB2OTGFSULPIEN_Msk

+#define RCC_AHB1ENR_USB2OTGHSULPIEN            RCC_AHB1ENR_USB2OTGFSULPIEN

+

+

+/********************  Bit definition for RCC_AHB2ENR register  ***************/

+#define RCC_AHB2ENR_DCMIEN_Pos                 (0U)

+#define RCC_AHB2ENR_DCMIEN_Msk                 (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)          /*!< 0x00000001 */

+#define RCC_AHB2ENR_DCMIEN                     RCC_AHB2ENR_DCMIEN_Msk

+#define RCC_AHB2ENR_CRYPEN_Pos                 (4U)

+#define RCC_AHB2ENR_CRYPEN_Msk                 (0x1UL << RCC_AHB2ENR_CRYPEN_Pos)          /*!< 0x00000010 */

+#define RCC_AHB2ENR_CRYPEN                     RCC_AHB2ENR_CRYPEN_Msk

+#define RCC_AHB2ENR_HASHEN_Pos                 (5U)

+#define RCC_AHB2ENR_HASHEN_Msk                 (0x1UL << RCC_AHB2ENR_HASHEN_Pos)          /*!< 0x00000020 */

+#define RCC_AHB2ENR_HASHEN                     RCC_AHB2ENR_HASHEN_Msk

+#define RCC_AHB2ENR_RNGEN_Pos                  (6U)

+#define RCC_AHB2ENR_RNGEN_Msk                  (0x1UL << RCC_AHB2ENR_RNGEN_Pos)           /*!< 0x00000040 */

+#define RCC_AHB2ENR_RNGEN                      RCC_AHB2ENR_RNGEN_Msk

+#define RCC_AHB2ENR_SDMMC2EN_Pos               (9U)

+#define RCC_AHB2ENR_SDMMC2EN_Msk               (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)        /*!< 0x00000200 */

+#define RCC_AHB2ENR_SDMMC2EN                   RCC_AHB2ENR_SDMMC2EN_Msk

+#define RCC_AHB2ENR_SRAM1EN_Pos                (29U)

+#define RCC_AHB2ENR_SRAM1EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos)       /*!< 0x20000000 */

+#define RCC_AHB2ENR_SRAM1EN                    RCC_AHB2ENR_SRAM1EN_Msk

+#define RCC_AHB2ENR_SRAM2EN_Pos                (30U)

+#define RCC_AHB2ENR_SRAM2EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos)       /*!< 0x40000000 */

+#define RCC_AHB2ENR_SRAM2EN                    RCC_AHB2ENR_SRAM2EN_Msk

+#define RCC_AHB2ENR_SRAM3EN_Pos                (31U)

+#define RCC_AHB2ENR_SRAM3EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM3EN_Pos)       /*!< 0x80000000 */

+#define RCC_AHB2ENR_SRAM3EN                    RCC_AHB2ENR_SRAM3EN_Msk

+

+/* Legacy define */

+#define RCC_AHB2ENR_D2SRAM1EN_Pos              RCC_AHB2ENR_SRAM1EN_Pos

+#define RCC_AHB2ENR_D2SRAM1EN_Msk              RCC_AHB2ENR_SRAM1EN_Msk

+#define RCC_AHB2ENR_D2SRAM1EN                  RCC_AHB2ENR_SRAM1EN

+#define RCC_AHB2ENR_D2SRAM2EN_Pos              RCC_AHB2ENR_SRAM2EN_Pos

+#define RCC_AHB2ENR_D2SRAM2EN_Msk              RCC_AHB2ENR_SRAM2EN_Msk

+#define RCC_AHB2ENR_D2SRAM2EN                  RCC_AHB2ENR_SRAM2EN

+#define RCC_AHB2ENR_D2SRAM3EN_Pos              RCC_AHB2ENR_SRAM3EN_Pos

+#define RCC_AHB2ENR_D2SRAM3EN_Msk              RCC_AHB2ENR_SRAM3EN_Msk

+#define RCC_AHB2ENR_D2SRAM3EN                  RCC_AHB2ENR_SRAM3EN

+

+/********************  Bit definition for RCC_AHB4ENR register  ******************/

+#define RCC_AHB4ENR_GPIOAEN_Pos                (0U)

+#define RCC_AHB4ENR_GPIOAEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)         /*!< 0x00000001 */

+#define RCC_AHB4ENR_GPIOAEN                    RCC_AHB4ENR_GPIOAEN_Msk

+#define RCC_AHB4ENR_GPIOBEN_Pos                (1U)

+#define RCC_AHB4ENR_GPIOBEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)         /*!< 0x00000002 */

+#define RCC_AHB4ENR_GPIOBEN                    RCC_AHB4ENR_GPIOBEN_Msk

+#define RCC_AHB4ENR_GPIOCEN_Pos                (2U)

+#define RCC_AHB4ENR_GPIOCEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)         /*!< 0x00000004 */

+#define RCC_AHB4ENR_GPIOCEN                    RCC_AHB4ENR_GPIOCEN_Msk

+#define RCC_AHB4ENR_GPIODEN_Pos                (3U)

+#define RCC_AHB4ENR_GPIODEN_Msk                (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)         /*!< 0x00000008 */

+#define RCC_AHB4ENR_GPIODEN                    RCC_AHB4ENR_GPIODEN_Msk

+#define RCC_AHB4ENR_GPIOEEN_Pos                (4U)

+#define RCC_AHB4ENR_GPIOEEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)         /*!< 0x00000010 */

+#define RCC_AHB4ENR_GPIOEEN                    RCC_AHB4ENR_GPIOEEN_Msk

+#define RCC_AHB4ENR_GPIOFEN_Pos                (5U)

+#define RCC_AHB4ENR_GPIOFEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)         /*!< 0x00000020 */

+#define RCC_AHB4ENR_GPIOFEN                    RCC_AHB4ENR_GPIOFEN_Msk

+#define RCC_AHB4ENR_GPIOGEN_Pos                (6U)

+#define RCC_AHB4ENR_GPIOGEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)         /*!< 0x00000040 */

+#define RCC_AHB4ENR_GPIOGEN                    RCC_AHB4ENR_GPIOGEN_Msk

+#define RCC_AHB4ENR_GPIOHEN_Pos                (7U)

+#define RCC_AHB4ENR_GPIOHEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)         /*!< 0x00000080 */

+#define RCC_AHB4ENR_GPIOHEN                    RCC_AHB4ENR_GPIOHEN_Msk

+#define RCC_AHB4ENR_GPIOIEN_Pos                (8U)

+#define RCC_AHB4ENR_GPIOIEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos)         /*!< 0x00000100 */

+#define RCC_AHB4ENR_GPIOIEN                    RCC_AHB4ENR_GPIOIEN_Msk

+#define RCC_AHB4ENR_GPIOJEN_Pos                (9U)

+#define RCC_AHB4ENR_GPIOJEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos)         /*!< 0x00000200 */

+#define RCC_AHB4ENR_GPIOJEN                    RCC_AHB4ENR_GPIOJEN_Msk

+#define RCC_AHB4ENR_GPIOKEN_Pos                (10U)

+#define RCC_AHB4ENR_GPIOKEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos)         /*!< 0x00000400 */

+#define RCC_AHB4ENR_GPIOKEN                    RCC_AHB4ENR_GPIOKEN_Msk

+#define RCC_AHB4ENR_CRCEN_Pos                  (19U)

+#define RCC_AHB4ENR_CRCEN_Msk                  (0x1UL << RCC_AHB4ENR_CRCEN_Pos)           /*!< 0x00080000 */

+#define RCC_AHB4ENR_CRCEN                      RCC_AHB4ENR_CRCEN_Msk

+#define RCC_AHB4ENR_BDMAEN_Pos                 (21U)

+#define RCC_AHB4ENR_BDMAEN_Msk                 (0x1UL << RCC_AHB4ENR_BDMAEN_Pos)          /*!< 0x00200000 */

+#define RCC_AHB4ENR_BDMAEN                     RCC_AHB4ENR_BDMAEN_Msk

+#define RCC_AHB4ENR_ADC3EN_Pos                 (24U)

+#define RCC_AHB4ENR_ADC3EN_Msk                 (0x1UL << RCC_AHB4ENR_ADC3EN_Pos)          /*!< 0x01000000 */

+#define RCC_AHB4ENR_ADC3EN                     RCC_AHB4ENR_ADC3EN_Msk

+#define RCC_AHB4ENR_HSEMEN_Pos                 (25U)

+#define RCC_AHB4ENR_HSEMEN_Msk                 (0x1UL << RCC_AHB4ENR_HSEMEN_Pos)          /*!< 0x02000000 */

+#define RCC_AHB4ENR_HSEMEN                     RCC_AHB4ENR_HSEMEN_Msk

+#define RCC_AHB4ENR_BKPRAMEN_Pos               (28U)

+#define RCC_AHB4ENR_BKPRAMEN_Msk               (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)        /*!< 0x10000000 */

+#define RCC_AHB4ENR_BKPRAMEN                   RCC_AHB4ENR_BKPRAMEN_Msk

+

+/********************  Bit definition for RCC_APB3ENR register  ******************/

+#define RCC_APB3ENR_LTDCEN_Pos                 (3U)

+#define RCC_APB3ENR_LTDCEN_Msk                 (0x1UL << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */

+#define RCC_APB3ENR_LTDCEN                     RCC_APB3ENR_LTDCEN_Msk

+#define RCC_APB3ENR_WWDG1EN_Pos                (6U)

+#define RCC_APB3ENR_WWDG1EN_Msk                (0x1UL << RCC_APB3ENR_WWDG1EN_Pos) /*!< 0x00000040 */

+#define RCC_APB3ENR_WWDG1EN                    RCC_APB3ENR_WWDG1EN_Msk

+

+/********************  Bit definition for RCC_APB1LENR register  ******************/

+

+#define RCC_APB1LENR_TIM2EN_Pos                (0U)

+#define RCC_APB1LENR_TIM2EN_Msk                (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */

+#define RCC_APB1LENR_TIM2EN                    RCC_APB1LENR_TIM2EN_Msk

+#define RCC_APB1LENR_TIM3EN_Pos                (1U)

+#define RCC_APB1LENR_TIM3EN_Msk                (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */

+#define RCC_APB1LENR_TIM3EN                    RCC_APB1LENR_TIM3EN_Msk

+#define RCC_APB1LENR_TIM4EN_Pos                (2U)

+#define RCC_APB1LENR_TIM4EN_Msk                (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */

+#define RCC_APB1LENR_TIM4EN                    RCC_APB1LENR_TIM4EN_Msk

+#define RCC_APB1LENR_TIM5EN_Pos                (3U)

+#define RCC_APB1LENR_TIM5EN_Msk                (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */

+#define RCC_APB1LENR_TIM5EN                    RCC_APB1LENR_TIM5EN_Msk

+#define RCC_APB1LENR_TIM6EN_Pos                (4U)

+#define RCC_APB1LENR_TIM6EN_Msk                (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */

+#define RCC_APB1LENR_TIM6EN                    RCC_APB1LENR_TIM6EN_Msk

+#define RCC_APB1LENR_TIM7EN_Pos                (5U)

+#define RCC_APB1LENR_TIM7EN_Msk                (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */

+#define RCC_APB1LENR_TIM7EN                    RCC_APB1LENR_TIM7EN_Msk

+#define RCC_APB1LENR_TIM12EN_Pos               (6U)

+#define RCC_APB1LENR_TIM12EN_Msk               (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */

+#define RCC_APB1LENR_TIM12EN                   RCC_APB1LENR_TIM12EN_Msk

+#define RCC_APB1LENR_TIM13EN_Pos               (7U)

+#define RCC_APB1LENR_TIM13EN_Msk               (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */

+#define RCC_APB1LENR_TIM13EN                   RCC_APB1LENR_TIM13EN_Msk

+#define RCC_APB1LENR_TIM14EN_Pos               (8U)

+#define RCC_APB1LENR_TIM14EN_Msk               (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */

+#define RCC_APB1LENR_TIM14EN                   RCC_APB1LENR_TIM14EN_Msk

+#define RCC_APB1LENR_LPTIM1EN_Pos              (9U)

+#define RCC_APB1LENR_LPTIM1EN_Msk              (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */

+#define RCC_APB1LENR_LPTIM1EN                  RCC_APB1LENR_LPTIM1EN_Msk

+

+

+#define RCC_APB1LENR_SPI2EN_Pos                (14U)

+#define RCC_APB1LENR_SPI2EN_Msk                (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */

+#define RCC_APB1LENR_SPI2EN                    RCC_APB1LENR_SPI2EN_Msk

+#define RCC_APB1LENR_SPI3EN_Pos                (15U)

+#define RCC_APB1LENR_SPI3EN_Msk                (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */

+#define RCC_APB1LENR_SPI3EN                    RCC_APB1LENR_SPI3EN_Msk

+#define RCC_APB1LENR_SPDIFRXEN_Pos             (16U)

+#define RCC_APB1LENR_SPDIFRXEN_Msk             (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */

+#define RCC_APB1LENR_SPDIFRXEN                 RCC_APB1LENR_SPDIFRXEN_Msk

+#define RCC_APB1LENR_USART2EN_Pos              (17U)

+#define RCC_APB1LENR_USART2EN_Msk              (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */

+#define RCC_APB1LENR_USART2EN                  RCC_APB1LENR_USART2EN_Msk

+#define RCC_APB1LENR_USART3EN_Pos              (18U)

+#define RCC_APB1LENR_USART3EN_Msk              (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */

+#define RCC_APB1LENR_USART3EN                  RCC_APB1LENR_USART3EN_Msk

+#define RCC_APB1LENR_UART4EN_Pos               (19U)

+#define RCC_APB1LENR_UART4EN_Msk               (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */

+#define RCC_APB1LENR_UART4EN                   RCC_APB1LENR_UART4EN_Msk

+#define RCC_APB1LENR_UART5EN_Pos               (20U)

+#define RCC_APB1LENR_UART5EN_Msk               (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */

+#define RCC_APB1LENR_UART5EN                   RCC_APB1LENR_UART5EN_Msk

+#define RCC_APB1LENR_I2C1EN_Pos                (21U)

+#define RCC_APB1LENR_I2C1EN_Msk                (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */

+#define RCC_APB1LENR_I2C1EN                    RCC_APB1LENR_I2C1EN_Msk

+#define RCC_APB1LENR_I2C2EN_Pos                (22U)

+#define RCC_APB1LENR_I2C2EN_Msk                (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */

+#define RCC_APB1LENR_I2C2EN                    RCC_APB1LENR_I2C2EN_Msk

+#define RCC_APB1LENR_I2C3EN_Pos                (23U)

+#define RCC_APB1LENR_I2C3EN_Msk                (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */

+#define RCC_APB1LENR_I2C3EN                    RCC_APB1LENR_I2C3EN_Msk

+#define RCC_APB1LENR_CECEN_Pos                 (27U)

+#define RCC_APB1LENR_CECEN_Msk                 (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */

+#define RCC_APB1LENR_CECEN                     RCC_APB1LENR_CECEN_Msk

+#define RCC_APB1LENR_DAC12EN_Pos               (29U)

+#define RCC_APB1LENR_DAC12EN_Msk               (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */

+#define RCC_APB1LENR_DAC12EN                   RCC_APB1LENR_DAC12EN_Msk

+#define RCC_APB1LENR_UART7EN_Pos               (30U)

+#define RCC_APB1LENR_UART7EN_Msk               (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */

+#define RCC_APB1LENR_UART7EN                   RCC_APB1LENR_UART7EN_Msk

+#define RCC_APB1LENR_UART8EN_Pos               (31U)

+#define RCC_APB1LENR_UART8EN_Msk               (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */

+#define RCC_APB1LENR_UART8EN                   RCC_APB1LENR_UART8EN_Msk

+

+/* Legacy define */

+#define RCC_APB1LENR_HDMICECEN_Pos             RCC_APB1LENR_CECEN_Pos

+#define RCC_APB1LENR_HDMICECEN_Msk             RCC_APB1LENR_CECEN_Msk

+#define RCC_APB1LENR_HDMICECEN                 RCC_APB1LENR_CECEN

+/********************  Bit definition for RCC_APB1HENR register  ******************/

+#define RCC_APB1HENR_CRSEN_Pos                 (1U)

+#define RCC_APB1HENR_CRSEN_Msk                 (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1HENR_CRSEN                     RCC_APB1HENR_CRSEN_Msk

+#define RCC_APB1HENR_SWPMIEN_Pos               (2U)

+#define RCC_APB1HENR_SWPMIEN_Msk               (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1HENR_SWPMIEN                   RCC_APB1HENR_SWPMIEN_Msk

+#define RCC_APB1HENR_OPAMPEN_Pos               (4U)

+#define RCC_APB1HENR_OPAMPEN_Msk               (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1HENR_OPAMPEN                   RCC_APB1HENR_OPAMPEN_Msk

+#define RCC_APB1HENR_MDIOSEN_Pos               (5U)

+#define RCC_APB1HENR_MDIOSEN_Msk               (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1HENR_MDIOSEN                   RCC_APB1HENR_MDIOSEN_Msk

+#define RCC_APB1HENR_FDCANEN_Pos               (8U)

+#define RCC_APB1HENR_FDCANEN_Msk               (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1HENR_FDCANEN                   RCC_APB1HENR_FDCANEN_Msk

+

+/********************  Bit definition for RCC_APB2ENR register  ******************/

+#define RCC_APB2ENR_TIM1EN_Pos                 (0U)

+#define RCC_APB2ENR_TIM1EN_Msk                 (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */

+#define RCC_APB2ENR_TIM1EN                     RCC_APB2ENR_TIM1EN_Msk

+#define RCC_APB2ENR_TIM8EN_Pos                 (1U)

+#define RCC_APB2ENR_TIM8EN_Msk                 (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */

+#define RCC_APB2ENR_TIM8EN                     RCC_APB2ENR_TIM8EN_Msk

+#define RCC_APB2ENR_USART1EN_Pos               (4U)

+#define RCC_APB2ENR_USART1EN_Msk               (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */

+#define RCC_APB2ENR_USART1EN                   RCC_APB2ENR_USART1EN_Msk

+#define RCC_APB2ENR_USART6EN_Pos               (5U)

+#define RCC_APB2ENR_USART6EN_Msk               (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */

+#define RCC_APB2ENR_USART6EN                   RCC_APB2ENR_USART6EN_Msk

+#define RCC_APB2ENR_SPI1EN_Pos                 (12U)

+#define RCC_APB2ENR_SPI1EN_Msk                 (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */

+#define RCC_APB2ENR_SPI1EN                     RCC_APB2ENR_SPI1EN_Msk

+#define RCC_APB2ENR_SPI4EN_Pos                 (13U)

+#define RCC_APB2ENR_SPI4EN_Msk                 (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */

+#define RCC_APB2ENR_SPI4EN                     RCC_APB2ENR_SPI4EN_Msk

+#define RCC_APB2ENR_TIM15EN_Pos                (16U)

+#define RCC_APB2ENR_TIM15EN_Msk                (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */

+#define RCC_APB2ENR_TIM15EN                    RCC_APB2ENR_TIM15EN_Msk

+#define RCC_APB2ENR_TIM16EN_Pos                (17U)

+#define RCC_APB2ENR_TIM16EN_Msk                (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */

+#define RCC_APB2ENR_TIM16EN                    RCC_APB2ENR_TIM16EN_Msk

+#define RCC_APB2ENR_TIM17EN_Pos                (18U)

+#define RCC_APB2ENR_TIM17EN_Msk                (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */

+#define RCC_APB2ENR_TIM17EN                    RCC_APB2ENR_TIM17EN_Msk

+#define RCC_APB2ENR_SPI5EN_Pos                 (20U)

+#define RCC_APB2ENR_SPI5EN_Msk                 (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */

+#define RCC_APB2ENR_SPI5EN                     RCC_APB2ENR_SPI5EN_Msk

+#define RCC_APB2ENR_SAI1EN_Pos                 (22U)

+#define RCC_APB2ENR_SAI1EN_Msk                 (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */

+#define RCC_APB2ENR_SAI1EN                     RCC_APB2ENR_SAI1EN_Msk

+#define RCC_APB2ENR_SAI2EN_Pos                 (23U)

+#define RCC_APB2ENR_SAI2EN_Msk                 (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */

+#define RCC_APB2ENR_SAI2EN                     RCC_APB2ENR_SAI2EN_Msk

+#define RCC_APB2ENR_SAI3EN_Pos                 (24U)

+#define RCC_APB2ENR_SAI3EN_Msk                 (0x1UL << RCC_APB2ENR_SAI3EN_Pos) /*!< 0x01000000 */

+#define RCC_APB2ENR_SAI3EN                     RCC_APB2ENR_SAI3EN_Msk

+#define RCC_APB2ENR_DFSDM1EN_Pos               (28U)

+#define RCC_APB2ENR_DFSDM1EN_Msk               (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x10000000 */

+#define RCC_APB2ENR_DFSDM1EN                   RCC_APB2ENR_DFSDM1EN_Msk

+#define RCC_APB2ENR_HRTIMEN_Pos                (29U)

+#define RCC_APB2ENR_HRTIMEN_Msk                (0x1UL << RCC_APB2ENR_HRTIMEN_Pos) /*!< 0x20000000 */

+#define RCC_APB2ENR_HRTIMEN                    RCC_APB2ENR_HRTIMEN_Msk

+

+/********************  Bit definition for RCC_APB4ENR register  ******************/

+#define RCC_APB4ENR_SYSCFGEN_Pos               (1U)

+#define RCC_APB4ENR_SYSCFGEN_Msk               (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */

+#define RCC_APB4ENR_SYSCFGEN                   RCC_APB4ENR_SYSCFGEN_Msk

+#define RCC_APB4ENR_LPUART1EN_Pos              (3U)

+#define RCC_APB4ENR_LPUART1EN_Msk              (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */

+#define RCC_APB4ENR_LPUART1EN                  RCC_APB4ENR_LPUART1EN_Msk

+#define RCC_APB4ENR_SPI6EN_Pos                 (5U)

+#define RCC_APB4ENR_SPI6EN_Msk                 (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */

+#define RCC_APB4ENR_SPI6EN                     RCC_APB4ENR_SPI6EN_Msk

+#define RCC_APB4ENR_I2C4EN_Pos                 (7U)

+#define RCC_APB4ENR_I2C4EN_Msk                 (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */

+#define RCC_APB4ENR_I2C4EN                     RCC_APB4ENR_I2C4EN_Msk

+#define RCC_APB4ENR_LPTIM2EN_Pos               (9U)

+#define RCC_APB4ENR_LPTIM2EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */

+#define RCC_APB4ENR_LPTIM2EN                   RCC_APB4ENR_LPTIM2EN_Msk

+#define RCC_APB4ENR_LPTIM3EN_Pos               (10U)

+#define RCC_APB4ENR_LPTIM3EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */

+#define RCC_APB4ENR_LPTIM3EN                   RCC_APB4ENR_LPTIM3EN_Msk

+#define RCC_APB4ENR_LPTIM4EN_Pos               (11U)

+#define RCC_APB4ENR_LPTIM4EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos) /*!< 0x00000800 */

+#define RCC_APB4ENR_LPTIM4EN                   RCC_APB4ENR_LPTIM4EN_Msk

+#define RCC_APB4ENR_LPTIM5EN_Pos               (12U)

+#define RCC_APB4ENR_LPTIM5EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos) /*!< 0x00001000 */

+#define RCC_APB4ENR_LPTIM5EN                   RCC_APB4ENR_LPTIM5EN_Msk

+#define RCC_APB4ENR_COMP12EN_Pos               (14U)

+#define RCC_APB4ENR_COMP12EN_Msk               (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */

+#define RCC_APB4ENR_COMP12EN                   RCC_APB4ENR_COMP12EN_Msk

+#define RCC_APB4ENR_VREFEN_Pos                 (15U)

+#define RCC_APB4ENR_VREFEN_Msk                 (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */

+#define RCC_APB4ENR_VREFEN                     RCC_APB4ENR_VREFEN_Msk

+#define RCC_APB4ENR_RTCAPBEN_Pos               (16U)

+#define RCC_APB4ENR_RTCAPBEN_Msk               (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */

+#define RCC_APB4ENR_RTCAPBEN                   RCC_APB4ENR_RTCAPBEN_Msk

+#define RCC_APB4ENR_SAI4EN_Pos                 (21U)

+#define RCC_APB4ENR_SAI4EN_Msk                 (0x1UL << RCC_APB4ENR_SAI4EN_Pos) /*!< 0x00200000 */

+#define RCC_APB4ENR_SAI4EN                     RCC_APB4ENR_SAI4EN_Msk

+

+

+/********************  Bit definition for RCC_AHB3RSTR register  ***************/

+#define RCC_AHB3RSTR_MDMARST_Pos               (0U)

+#define RCC_AHB3RSTR_MDMARST_Msk               (0x1UL << RCC_AHB3RSTR_MDMARST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB3RSTR_MDMARST                   RCC_AHB3RSTR_MDMARST_Msk

+#define RCC_AHB3RSTR_DMA2DRST_Pos              (4U)

+#define RCC_AHB3RSTR_DMA2DRST_Msk              (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos)     /*!< 0x00000010 */

+#define RCC_AHB3RSTR_DMA2DRST                  RCC_AHB3RSTR_DMA2DRST_Msk

+#define RCC_AHB3RSTR_JPGDECRST_Pos             (5U)

+#define RCC_AHB3RSTR_JPGDECRST_Msk             (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos)    /*!< 0x00000020 */

+#define RCC_AHB3RSTR_JPGDECRST                 RCC_AHB3RSTR_JPGDECRST_Msk

+#define RCC_AHB3RSTR_FMCRST_Pos                (12U)

+#define RCC_AHB3RSTR_FMCRST_Msk                (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)      /*!< 0x00001000 */

+#define RCC_AHB3RSTR_FMCRST                    RCC_AHB3RSTR_FMCRST_Msk

+#define RCC_AHB3RSTR_QSPIRST_Pos               (14U)

+#define RCC_AHB3RSTR_QSPIRST_Msk               (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)     /*!< 0x00004000 */

+#define RCC_AHB3RSTR_QSPIRST                   RCC_AHB3RSTR_QSPIRST_Msk

+#define RCC_AHB3RSTR_SDMMC1RST_Pos             (16U)

+#define RCC_AHB3RSTR_SDMMC1RST_Msk             (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos)   /*!< 0x00010000 */

+#define RCC_AHB3RSTR_SDMMC1RST                 RCC_AHB3RSTR_SDMMC1RST_Msk

+

+

+/********************  Bit definition for RCC_AHB1RSTR register  ***************/

+#define RCC_AHB1RSTR_DMA1RST_Pos               (0U)

+#define RCC_AHB1RSTR_DMA1RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB1RSTR_DMA1RST                   RCC_AHB1RSTR_DMA1RST_Msk

+#define RCC_AHB1RSTR_DMA2RST_Pos               (1U)

+#define RCC_AHB1RSTR_DMA2RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)      /*!< 0x00000002 */

+#define RCC_AHB1RSTR_DMA2RST                   RCC_AHB1RSTR_DMA2RST_Msk

+#define RCC_AHB1RSTR_ADC12RST_Pos              (5U)

+#define RCC_AHB1RSTR_ADC12RST_Msk              (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)     /*!< 0x00000020 */

+#define RCC_AHB1RSTR_ADC12RST                  RCC_AHB1RSTR_ADC12RST_Msk

+#define RCC_AHB1RSTR_ETH1MACRST_Pos            (15U)

+#define RCC_AHB1RSTR_ETH1MACRST_Msk            (0x1UL << RCC_AHB1RSTR_ETH1MACRST_Pos)   /*!< 0x00008000 */

+#define RCC_AHB1RSTR_ETH1MACRST                RCC_AHB1RSTR_ETH1MACRST_Msk

+#define RCC_AHB1RSTR_USB1OTGHSRST_Pos          (25U)

+#define RCC_AHB1RSTR_USB1OTGHSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */

+#define RCC_AHB1RSTR_USB1OTGHSRST              RCC_AHB1RSTR_USB1OTGHSRST_Msk

+#define RCC_AHB1RSTR_USB2OTGFSRST_Pos          (27U)

+#define RCC_AHB1RSTR_USB2OTGFSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB2OTGFSRST_Pos) /*!< 0x08000000 */

+#define RCC_AHB1RSTR_USB2OTGFSRST              RCC_AHB1RSTR_USB2OTGFSRST_Msk

+

+/* Legacy define */

+#define RCC_AHB1RSTR_USB2OTGHSRST_Pos          RCC_AHB1RSTR_USB2OTGFSRST_Pos

+#define RCC_AHB1RSTR_USB2OTGHSRST_Msk          RCC_AHB1RSTR_USB2OTGFSRST_Msk

+#define RCC_AHB1RSTR_USB2OTGHSRST              RCC_AHB1RSTR_USB2OTGFSRST

+

+/********************  Bit definition for RCC_AHB2RSTR register  ***************/

+#define RCC_AHB2RSTR_DCMIRST_Pos               (0U)

+#define RCC_AHB2RSTR_DCMIRST_Msk               (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)       /*!< 0x00000001 */

+#define RCC_AHB2RSTR_DCMIRST                   RCC_AHB2RSTR_DCMIRST_Msk

+#define RCC_AHB2RSTR_CRYPRST_Pos               (4U)

+#define RCC_AHB2RSTR_CRYPRST_Msk               (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos)       /*!< 0x00000010 */

+#define RCC_AHB2RSTR_CRYPRST                   RCC_AHB2RSTR_CRYPRST_Msk

+#define RCC_AHB2RSTR_HASHRST_Pos               (5U)

+#define RCC_AHB2RSTR_HASHRST_Msk               (0x1UL << RCC_AHB2RSTR_HASHRST_Pos)       /*!< 0x00000020 */

+#define RCC_AHB2RSTR_HASHRST                   RCC_AHB2RSTR_HASHRST_Msk

+#define RCC_AHB2RSTR_RNGRST_Pos                (6U)

+#define RCC_AHB2RSTR_RNGRST_Msk                (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)        /*!< 0x00000040 */

+#define RCC_AHB2RSTR_RNGRST                    RCC_AHB2RSTR_RNGRST_Msk

+#define RCC_AHB2RSTR_SDMMC2RST_Pos             (9U)

+#define RCC_AHB2RSTR_SDMMC2RST_Msk             (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)     /*!< 0x00000200 */

+#define RCC_AHB2RSTR_SDMMC2RST                 RCC_AHB2RSTR_SDMMC2RST_Msk

+

+/********************  Bit definition for RCC_AHB4RSTR register  ******************/

+#define RCC_AHB4RSTR_GPIOARST_Pos              (0U)

+#define RCC_AHB4RSTR_GPIOARST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB4RSTR_GPIOARST                  RCC_AHB4RSTR_GPIOARST_Msk

+#define RCC_AHB4RSTR_GPIOBRST_Pos              (1U)

+#define RCC_AHB4RSTR_GPIOBRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)      /*!< 0x00000002 */

+#define RCC_AHB4RSTR_GPIOBRST                  RCC_AHB4RSTR_GPIOBRST_Msk

+#define RCC_AHB4RSTR_GPIOCRST_Pos              (2U)

+#define RCC_AHB4RSTR_GPIOCRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)      /*!< 0x00000004 */

+#define RCC_AHB4RSTR_GPIOCRST                  RCC_AHB4RSTR_GPIOCRST_Msk

+#define RCC_AHB4RSTR_GPIODRST_Pos              (3U)

+#define RCC_AHB4RSTR_GPIODRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)      /*!< 0x00000008 */

+#define RCC_AHB4RSTR_GPIODRST                  RCC_AHB4RSTR_GPIODRST_Msk

+#define RCC_AHB4RSTR_GPIOERST_Pos              (4U)

+#define RCC_AHB4RSTR_GPIOERST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)      /*!< 0x00000010 */

+#define RCC_AHB4RSTR_GPIOERST                  RCC_AHB4RSTR_GPIOERST_Msk

+#define RCC_AHB4RSTR_GPIOFRST_Pos              (5U)

+#define RCC_AHB4RSTR_GPIOFRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)       /*!< 0x00000020 */

+#define RCC_AHB4RSTR_GPIOFRST                  RCC_AHB4RSTR_GPIOFRST_Msk

+#define RCC_AHB4RSTR_GPIOGRST_Pos              (6U)

+#define RCC_AHB4RSTR_GPIOGRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)       /*!< 0x00000040 */

+#define RCC_AHB4RSTR_GPIOGRST                  RCC_AHB4RSTR_GPIOGRST_Msk

+#define RCC_AHB4RSTR_GPIOHRST_Pos              (7U)

+#define RCC_AHB4RSTR_GPIOHRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)       /*!< 0x00000080 */

+#define RCC_AHB4RSTR_GPIOHRST                  RCC_AHB4RSTR_GPIOHRST_Msk

+#define RCC_AHB4RSTR_GPIOIRST_Pos              (8U)

+#define RCC_AHB4RSTR_GPIOIRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos)       /*!< 0x00000100 */

+#define RCC_AHB4RSTR_GPIOIRST                  RCC_AHB4RSTR_GPIOIRST_Msk

+#define RCC_AHB4RSTR_GPIOJRST_Pos              (9U)

+#define RCC_AHB4RSTR_GPIOJRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos)       /*!< 0x00000200 */

+#define RCC_AHB4RSTR_GPIOJRST                  RCC_AHB4RSTR_GPIOJRST_Msk

+#define RCC_AHB4RSTR_GPIOKRST_Pos              (10U)

+#define RCC_AHB4RSTR_GPIOKRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos)       /*!< 0x00000400 */

+#define RCC_AHB4RSTR_GPIOKRST                  RCC_AHB4RSTR_GPIOKRST_Msk

+#define RCC_AHB4RSTR_CRCRST_Pos                (19U)

+#define RCC_AHB4RSTR_CRCRST_Msk                (0x1UL << RCC_AHB4RSTR_CRCRST_Pos)         /*!< 0x00080000 */

+#define RCC_AHB4RSTR_CRCRST                    RCC_AHB4RSTR_CRCRST_Msk

+#define RCC_AHB4RSTR_BDMARST_Pos               (21U)

+#define RCC_AHB4RSTR_BDMARST_Msk               (0x1UL << RCC_AHB4RSTR_BDMARST_Pos)        /*!< 0x00200000 */

+#define RCC_AHB4RSTR_BDMARST                   RCC_AHB4RSTR_BDMARST_Msk

+#define RCC_AHB4RSTR_ADC3RST_Pos               (24U)

+#define RCC_AHB4RSTR_ADC3RST_Msk               (0x1UL << RCC_AHB4RSTR_ADC3RST_Pos)        /*!< 0x01000000 */

+#define RCC_AHB4RSTR_ADC3RST                   RCC_AHB4RSTR_ADC3RST_Msk

+#define RCC_AHB4RSTR_HSEMRST_Pos               (25U)

+#define RCC_AHB4RSTR_HSEMRST_Msk               (0x1UL << RCC_AHB4RSTR_HSEMRST_Pos)        /*!< 0x02000000 */

+#define RCC_AHB4RSTR_HSEMRST                   RCC_AHB4RSTR_HSEMRST_Msk

+

+

+/********************  Bit definition for RCC_APB3RSTR register  ******************/

+#define RCC_APB3RSTR_LTDCRST_Pos               (3U)

+#define RCC_APB3RSTR_LTDCRST_Msk               (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */

+#define RCC_APB3RSTR_LTDCRST                   RCC_APB3RSTR_LTDCRST_Msk

+

+/********************  Bit definition for RCC_APB1LRSTR register  ******************/

+

+#define RCC_APB1LRSTR_TIM2RST_Pos              (0U)

+#define RCC_APB1LRSTR_TIM2RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */

+#define RCC_APB1LRSTR_TIM2RST                  RCC_APB1LRSTR_TIM2RST_Msk

+#define RCC_APB1LRSTR_TIM3RST_Pos              (1U)

+#define RCC_APB1LRSTR_TIM3RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */

+#define RCC_APB1LRSTR_TIM3RST                  RCC_APB1LRSTR_TIM3RST_Msk

+#define RCC_APB1LRSTR_TIM4RST_Pos              (2U)

+#define RCC_APB1LRSTR_TIM4RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */

+#define RCC_APB1LRSTR_TIM4RST                  RCC_APB1LRSTR_TIM4RST_Msk

+#define RCC_APB1LRSTR_TIM5RST_Pos              (3U)

+#define RCC_APB1LRSTR_TIM5RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */

+#define RCC_APB1LRSTR_TIM5RST                  RCC_APB1LRSTR_TIM5RST_Msk

+#define RCC_APB1LRSTR_TIM6RST_Pos              (4U)

+#define RCC_APB1LRSTR_TIM6RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */

+#define RCC_APB1LRSTR_TIM6RST                  RCC_APB1LRSTR_TIM6RST_Msk

+#define RCC_APB1LRSTR_TIM7RST_Pos              (5U)

+#define RCC_APB1LRSTR_TIM7RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */

+#define RCC_APB1LRSTR_TIM7RST                  RCC_APB1LRSTR_TIM7RST_Msk

+#define RCC_APB1LRSTR_TIM12RST_Pos             (6U)

+#define RCC_APB1LRSTR_TIM12RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */

+#define RCC_APB1LRSTR_TIM12RST                 RCC_APB1LRSTR_TIM12RST_Msk

+#define RCC_APB1LRSTR_TIM13RST_Pos             (7U)

+#define RCC_APB1LRSTR_TIM13RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */

+#define RCC_APB1LRSTR_TIM13RST                 RCC_APB1LRSTR_TIM13RST_Msk

+#define RCC_APB1LRSTR_TIM14RST_Pos             (8U)

+#define RCC_APB1LRSTR_TIM14RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */

+#define RCC_APB1LRSTR_TIM14RST                 RCC_APB1LRSTR_TIM14RST_Msk

+#define RCC_APB1LRSTR_LPTIM1RST_Pos            (9U)

+#define RCC_APB1LRSTR_LPTIM1RST_Msk            (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */

+#define RCC_APB1LRSTR_LPTIM1RST                RCC_APB1LRSTR_LPTIM1RST_Msk

+#define RCC_APB1LRSTR_SPI2RST_Pos              (14U)

+#define RCC_APB1LRSTR_SPI2RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */

+#define RCC_APB1LRSTR_SPI2RST                  RCC_APB1LRSTR_SPI2RST_Msk

+#define RCC_APB1LRSTR_SPI3RST_Pos              (15U)

+#define RCC_APB1LRSTR_SPI3RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */

+#define RCC_APB1LRSTR_SPI3RST                  RCC_APB1LRSTR_SPI3RST_Msk

+#define RCC_APB1LRSTR_SPDIFRXRST_Pos           (16U)

+#define RCC_APB1LRSTR_SPDIFRXRST_Msk           (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */

+#define RCC_APB1LRSTR_SPDIFRXRST               RCC_APB1LRSTR_SPDIFRXRST_Msk

+#define RCC_APB1LRSTR_USART2RST_Pos            (17U)

+#define RCC_APB1LRSTR_USART2RST_Msk            (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */

+#define RCC_APB1LRSTR_USART2RST                RCC_APB1LRSTR_USART2RST_Msk

+#define RCC_APB1LRSTR_USART3RST_Pos            (18U)

+#define RCC_APB1LRSTR_USART3RST_Msk            (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */

+#define RCC_APB1LRSTR_USART3RST                RCC_APB1LRSTR_USART3RST_Msk

+#define RCC_APB1LRSTR_UART4RST_Pos             (19U)

+#define RCC_APB1LRSTR_UART4RST_Msk             (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */

+#define RCC_APB1LRSTR_UART4RST                 RCC_APB1LRSTR_UART4RST_Msk

+#define RCC_APB1LRSTR_UART5RST_Pos             (20U)

+#define RCC_APB1LRSTR_UART5RST_Msk             (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */

+#define RCC_APB1LRSTR_UART5RST                 RCC_APB1LRSTR_UART5RST_Msk

+#define RCC_APB1LRSTR_I2C1RST_Pos              (21U)

+#define RCC_APB1LRSTR_I2C1RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */

+#define RCC_APB1LRSTR_I2C1RST                  RCC_APB1LRSTR_I2C1RST_Msk

+#define RCC_APB1LRSTR_I2C2RST_Pos              (22U)

+#define RCC_APB1LRSTR_I2C2RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */

+#define RCC_APB1LRSTR_I2C2RST                  RCC_APB1LRSTR_I2C2RST_Msk

+#define RCC_APB1LRSTR_I2C3RST_Pos              (23U)

+#define RCC_APB1LRSTR_I2C3RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */

+#define RCC_APB1LRSTR_I2C3RST                  RCC_APB1LRSTR_I2C3RST_Msk

+#define RCC_APB1LRSTR_CECRST_Pos               (27U)

+#define RCC_APB1LRSTR_CECRST_Msk               (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */

+#define RCC_APB1LRSTR_CECRST                   RCC_APB1LRSTR_CECRST_Msk

+#define RCC_APB1LRSTR_DAC12RST_Pos             (29U)

+#define RCC_APB1LRSTR_DAC12RST_Msk             (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */

+#define RCC_APB1LRSTR_DAC12RST                 RCC_APB1LRSTR_DAC12RST_Msk

+#define RCC_APB1LRSTR_UART7RST_Pos             (30U)

+#define RCC_APB1LRSTR_UART7RST_Msk             (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */

+#define RCC_APB1LRSTR_UART7RST                 RCC_APB1LRSTR_UART7RST_Msk

+#define RCC_APB1LRSTR_UART8RST_Pos             (31U)

+#define RCC_APB1LRSTR_UART8RST_Msk             (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */

+#define RCC_APB1LRSTR_UART8RST                 RCC_APB1LRSTR_UART8RST_Msk

+

+/* Legacy define */

+#define RCC_APB1LRSTR_HDMICECRST_Pos           RCC_APB1LRSTR_CECRST_Pos

+#define RCC_APB1LRSTR_HDMICECRST_Msk           RCC_APB1LRSTR_CECRST_Msk

+#define RCC_APB1LRSTR_HDMICECRST               RCC_APB1LRSTR_CECRST

+/********************  Bit definition for RCC_APB1HRSTR register  ******************/

+#define RCC_APB1HRSTR_CRSRST_Pos               (1U)

+#define RCC_APB1HRSTR_CRSRST_Msk               (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */

+#define RCC_APB1HRSTR_CRSRST                   RCC_APB1HRSTR_CRSRST_Msk

+#define RCC_APB1HRSTR_SWPMIRST_Pos             (2U)

+#define RCC_APB1HRSTR_SWPMIRST_Msk             (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */

+#define RCC_APB1HRSTR_SWPMIRST                 RCC_APB1HRSTR_SWPMIRST_Msk

+#define RCC_APB1HRSTR_OPAMPRST_Pos             (4U)

+#define RCC_APB1HRSTR_OPAMPRST_Msk             (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */

+#define RCC_APB1HRSTR_OPAMPRST                 RCC_APB1HRSTR_OPAMPRST_Msk

+#define RCC_APB1HRSTR_MDIOSRST_Pos             (5U)

+#define RCC_APB1HRSTR_MDIOSRST_Msk             (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */

+#define RCC_APB1HRSTR_MDIOSRST                 RCC_APB1HRSTR_MDIOSRST_Msk

+#define RCC_APB1HRSTR_FDCANRST_Pos             (8U)

+#define RCC_APB1HRSTR_FDCANRST_Msk             (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */

+#define RCC_APB1HRSTR_FDCANRST                 RCC_APB1HRSTR_FDCANRST_Msk

+

+/********************  Bit definition for RCC_APB2RSTR register  ******************/

+#define RCC_APB2RSTR_TIM1RST_Pos               (0U)

+#define RCC_APB2RSTR_TIM1RST_Msk               (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */

+#define RCC_APB2RSTR_TIM1RST                   RCC_APB2RSTR_TIM1RST_Msk

+#define RCC_APB2RSTR_TIM8RST_Pos               (1U)

+#define RCC_APB2RSTR_TIM8RST_Msk               (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */

+#define RCC_APB2RSTR_TIM8RST                   RCC_APB2RSTR_TIM8RST_Msk

+#define RCC_APB2RSTR_USART1RST_Pos             (4U)

+#define RCC_APB2RSTR_USART1RST_Msk             (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */

+#define RCC_APB2RSTR_USART1RST                 RCC_APB2RSTR_USART1RST_Msk

+#define RCC_APB2RSTR_USART6RST_Pos             (5U)

+#define RCC_APB2RSTR_USART6RST_Msk             (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */

+#define RCC_APB2RSTR_USART6RST                 RCC_APB2RSTR_USART6RST_Msk

+#define RCC_APB2RSTR_SPI1RST_Pos               (12U)

+#define RCC_APB2RSTR_SPI1RST_Msk               (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */

+#define RCC_APB2RSTR_SPI1RST                   RCC_APB2RSTR_SPI1RST_Msk

+#define RCC_APB2RSTR_SPI4RST_Pos               (13U)

+#define RCC_APB2RSTR_SPI4RST_Msk               (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */

+#define RCC_APB2RSTR_SPI4RST                   RCC_APB2RSTR_SPI4RST_Msk

+#define RCC_APB2RSTR_TIM15RST_Pos              (16U)

+#define RCC_APB2RSTR_TIM15RST_Msk              (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */

+#define RCC_APB2RSTR_TIM15RST                  RCC_APB2RSTR_TIM15RST_Msk

+#define RCC_APB2RSTR_TIM16RST_Pos              (17U)

+#define RCC_APB2RSTR_TIM16RST_Msk              (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */

+#define RCC_APB2RSTR_TIM16RST                  RCC_APB2RSTR_TIM16RST_Msk

+#define RCC_APB2RSTR_TIM17RST_Pos              (18U)

+#define RCC_APB2RSTR_TIM17RST_Msk              (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */

+#define RCC_APB2RSTR_TIM17RST                  RCC_APB2RSTR_TIM17RST_Msk

+#define RCC_APB2RSTR_SPI5RST_Pos               (20U)

+#define RCC_APB2RSTR_SPI5RST_Msk               (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */

+#define RCC_APB2RSTR_SPI5RST                   RCC_APB2RSTR_SPI5RST_Msk

+#define RCC_APB2RSTR_SAI1RST_Pos               (22U)

+#define RCC_APB2RSTR_SAI1RST_Msk               (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */

+#define RCC_APB2RSTR_SAI1RST                   RCC_APB2RSTR_SAI1RST_Msk

+#define RCC_APB2RSTR_SAI2RST_Pos               (23U)

+#define RCC_APB2RSTR_SAI2RST_Msk               (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */

+#define RCC_APB2RSTR_SAI2RST                   RCC_APB2RSTR_SAI2RST_Msk

+#define RCC_APB2RSTR_SAI3RST_Pos               (24U)

+#define RCC_APB2RSTR_SAI3RST_Msk               (0x1UL << RCC_APB2RSTR_SAI3RST_Pos) /*!< 0x01000000 */

+#define RCC_APB2RSTR_SAI3RST                   RCC_APB2RSTR_SAI3RST_Msk

+#define RCC_APB2RSTR_DFSDM1RST_Pos             (28U)

+#define RCC_APB2RSTR_DFSDM1RST_Msk             (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */

+#define RCC_APB2RSTR_DFSDM1RST                 RCC_APB2RSTR_DFSDM1RST_Msk

+#define RCC_APB2RSTR_HRTIMRST_Pos              (29U)

+#define RCC_APB2RSTR_HRTIMRST_Msk              (0x1UL << RCC_APB2RSTR_HRTIMRST_Pos) /*!< 0x20000000 */

+#define RCC_APB2RSTR_HRTIMRST                  RCC_APB2RSTR_HRTIMRST_Msk

+

+/********************  Bit definition for RCC_APB4RSTR register  ******************/

+#define RCC_APB4RSTR_SYSCFGRST_Pos             (1U)

+#define RCC_APB4RSTR_SYSCFGRST_Msk             (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */

+#define RCC_APB4RSTR_SYSCFGRST                 RCC_APB4RSTR_SYSCFGRST_Msk

+#define RCC_APB4RSTR_LPUART1RST_Pos            (3U)

+#define RCC_APB4RSTR_LPUART1RST_Msk            (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */

+#define RCC_APB4RSTR_LPUART1RST                RCC_APB4RSTR_LPUART1RST_Msk

+#define RCC_APB4RSTR_SPI6RST_Pos               (5U)

+#define RCC_APB4RSTR_SPI6RST_Msk               (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */

+#define RCC_APB4RSTR_SPI6RST                   RCC_APB4RSTR_SPI6RST_Msk

+#define RCC_APB4RSTR_I2C4RST_Pos               (7U)

+#define RCC_APB4RSTR_I2C4RST_Msk               (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */

+#define RCC_APB4RSTR_I2C4RST                   RCC_APB4RSTR_I2C4RST_Msk

+#define RCC_APB4RSTR_LPTIM2RST_Pos             (9U)

+#define RCC_APB4RSTR_LPTIM2RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */

+#define RCC_APB4RSTR_LPTIM2RST                 RCC_APB4RSTR_LPTIM2RST_Msk

+#define RCC_APB4RSTR_LPTIM3RST_Pos             (10U)

+#define RCC_APB4RSTR_LPTIM3RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */

+#define RCC_APB4RSTR_LPTIM3RST                 RCC_APB4RSTR_LPTIM3RST_Msk

+#define RCC_APB4RSTR_LPTIM4RST_Pos             (11U)

+#define RCC_APB4RSTR_LPTIM4RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos) /*!< 0x00000800 */

+#define RCC_APB4RSTR_LPTIM4RST                 RCC_APB4RSTR_LPTIM4RST_Msk

+#define RCC_APB4RSTR_LPTIM5RST_Pos             (12U)

+#define RCC_APB4RSTR_LPTIM5RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos) /*!< 0x00001000 */

+#define RCC_APB4RSTR_LPTIM5RST                 RCC_APB4RSTR_LPTIM5RST_Msk

+#define RCC_APB4RSTR_COMP12RST_Pos             (14U)

+#define RCC_APB4RSTR_COMP12RST_Msk             (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */

+#define RCC_APB4RSTR_COMP12RST                 RCC_APB4RSTR_COMP12RST_Msk

+#define RCC_APB4RSTR_VREFRST_Pos               (15U)

+#define RCC_APB4RSTR_VREFRST_Msk               (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */

+#define RCC_APB4RSTR_VREFRST                   RCC_APB4RSTR_VREFRST_Msk

+#define RCC_APB4RSTR_SAI4RST_Pos               (21U)

+#define RCC_APB4RSTR_SAI4RST_Msk               (0x1UL << RCC_APB4RSTR_SAI4RST_Pos) /*!< 0x00200000 */

+#define RCC_APB4RSTR_SAI4RST                   RCC_APB4RSTR_SAI4RST_Msk

+

+

+/********************  Bit definition for RCC_GCR register  ********************/

+#define RCC_GCR_WW1RSC_Pos                     (0U)

+#define RCC_GCR_WW1RSC_Msk                     (0x1UL << RCC_GCR_WW1RSC_Pos)   /*!< 0x00000001 */

+#define RCC_GCR_WW1RSC                         RCC_GCR_WW1RSC_Msk

+

+/********************  Bit definition for RCC_D3AMR register  ********************/

+#define RCC_D3AMR_BDMAAMEN_Pos                 (0U)

+#define RCC_D3AMR_BDMAAMEN_Msk                 (0x1UL << RCC_D3AMR_BDMAAMEN_Pos) /*!< 0x00000001 */

+#define RCC_D3AMR_BDMAAMEN                     RCC_D3AMR_BDMAAMEN_Msk

+#define RCC_D3AMR_LPUART1AMEN_Pos              (3U)

+#define RCC_D3AMR_LPUART1AMEN_Msk              (0x1UL << RCC_D3AMR_LPUART1AMEN_Pos) /*!< 0x00000008 */

+#define RCC_D3AMR_LPUART1AMEN                  RCC_D3AMR_LPUART1AMEN_Msk

+#define RCC_D3AMR_SPI6AMEN_Pos                 (5U)

+#define RCC_D3AMR_SPI6AMEN_Msk                 (0x1UL << RCC_D3AMR_SPI6AMEN_Pos) /*!< 0x00000020 */

+#define RCC_D3AMR_SPI6AMEN                     RCC_D3AMR_SPI6AMEN_Msk

+#define RCC_D3AMR_I2C4AMEN_Pos                 (7U)

+#define RCC_D3AMR_I2C4AMEN_Msk                 (0x1UL << RCC_D3AMR_I2C4AMEN_Pos) /*!< 0x00000080 */

+#define RCC_D3AMR_I2C4AMEN                     RCC_D3AMR_I2C4AMEN_Msk

+#define RCC_D3AMR_LPTIM2AMEN_Pos               (9U)

+#define RCC_D3AMR_LPTIM2AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */

+#define RCC_D3AMR_LPTIM2AMEN                   RCC_D3AMR_LPTIM2AMEN_Msk

+#define RCC_D3AMR_LPTIM3AMEN_Pos               (10U)

+#define RCC_D3AMR_LPTIM3AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */

+#define RCC_D3AMR_LPTIM3AMEN                   RCC_D3AMR_LPTIM3AMEN_Msk

+#define RCC_D3AMR_LPTIM4AMEN_Pos               (11U)

+#define RCC_D3AMR_LPTIM4AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM4AMEN_Pos) /*!< 0x00000800 */

+#define RCC_D3AMR_LPTIM4AMEN                   RCC_D3AMR_LPTIM4AMEN_Msk

+#define RCC_D3AMR_LPTIM5AMEN_Pos               (12U)

+#define RCC_D3AMR_LPTIM5AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM5AMEN_Pos) /*!< 0x00001000 */

+#define RCC_D3AMR_LPTIM5AMEN                   RCC_D3AMR_LPTIM5AMEN_Msk

+#define RCC_D3AMR_COMP12AMEN_Pos               (14U)

+#define RCC_D3AMR_COMP12AMEN_Msk               (0x1UL << RCC_D3AMR_COMP12AMEN_Pos) /*!< 0x00004000 */

+#define RCC_D3AMR_COMP12AMEN                   RCC_D3AMR_COMP12AMEN_Msk

+#define RCC_D3AMR_VREFAMEN_Pos                 (15U)

+#define RCC_D3AMR_VREFAMEN_Msk                 (0x1UL << RCC_D3AMR_VREFAMEN_Pos) /*!< 0x00008000 */

+#define RCC_D3AMR_VREFAMEN                     RCC_D3AMR_VREFAMEN_Msk

+#define RCC_D3AMR_RTCAMEN_Pos                  (16U)

+#define RCC_D3AMR_RTCAMEN_Msk                  (0x1UL << RCC_D3AMR_RTCAMEN_Pos) /*!< 0x00010000 */

+#define RCC_D3AMR_RTCAMEN                      RCC_D3AMR_RTCAMEN_Msk

+#define RCC_D3AMR_CRCAMEN_Pos                  (19U)

+#define RCC_D3AMR_CRCAMEN_Msk                  (0x1UL << RCC_D3AMR_CRCAMEN_Pos) /*!< 0x00080000 */

+#define RCC_D3AMR_CRCAMEN                      RCC_D3AMR_CRCAMEN_Msk

+#define RCC_D3AMR_SAI4AMEN_Pos                 (21U)

+#define RCC_D3AMR_SAI4AMEN_Msk                 (0x1UL << RCC_D3AMR_SAI4AMEN_Pos) /*!< 0x00200000 */

+#define RCC_D3AMR_SAI4AMEN                     RCC_D3AMR_SAI4AMEN_Msk

+#define RCC_D3AMR_ADC3AMEN_Pos                 (24U)

+#define RCC_D3AMR_ADC3AMEN_Msk                 (0x1UL << RCC_D3AMR_ADC3AMEN_Pos) /*!< 0x01000000 */

+#define RCC_D3AMR_ADC3AMEN                     RCC_D3AMR_ADC3AMEN_Msk

+

+

+#define RCC_D3AMR_BKPRAMAMEN_Pos               (28U)

+#define RCC_D3AMR_BKPRAMAMEN_Msk               (0x1UL << RCC_D3AMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */

+#define RCC_D3AMR_BKPRAMAMEN                   RCC_D3AMR_BKPRAMAMEN_Msk

+#define RCC_D3AMR_SRAM4AMEN_Pos                (29U)

+#define RCC_D3AMR_SRAM4AMEN_Msk                (0x1UL << RCC_D3AMR_SRAM4AMEN_Pos) /*!< 0x20000000 */

+#define RCC_D3AMR_SRAM4AMEN                    RCC_D3AMR_SRAM4AMEN_Msk

+/********************  Bit definition for RCC_AHB3LPENR register  **************/

+#define RCC_AHB3LPENR_MDMALPEN_Pos             (0U)

+#define RCC_AHB3LPENR_MDMALPEN_Msk             (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos)         /*!< 0x00000001 */

+#define RCC_AHB3LPENR_MDMALPEN                 RCC_AHB3LPENR_MDMALPEN_Msk

+#define RCC_AHB3LPENR_DMA2DLPEN_Pos            (4U)

+#define RCC_AHB3LPENR_DMA2DLPEN_Msk            (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos)        /*!< 0x00000010 */

+#define RCC_AHB3LPENR_DMA2DLPEN                RCC_AHB3LPENR_DMA2DLPEN_Msk

+#define RCC_AHB3LPENR_JPGDECLPEN_Pos           (5U)

+#define RCC_AHB3LPENR_JPGDECLPEN_Msk           (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos)       /*!< 0x00000020 */

+#define RCC_AHB3LPENR_JPGDECLPEN               RCC_AHB3LPENR_JPGDECLPEN_Msk

+#define RCC_AHB3LPENR_FLASHLPEN_Pos            (8U)

+#define RCC_AHB3LPENR_FLASHLPEN_Msk            (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos)        /*!< 0x00000100 */

+#define RCC_AHB3LPENR_FLASHLPEN                RCC_AHB3LPENR_FLASHLPEN_Msk

+#define RCC_AHB3LPENR_FMCLPEN_Pos              (12U)

+#define RCC_AHB3LPENR_FMCLPEN_Msk              (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)          /*!< 0x00001000 */

+#define RCC_AHB3LPENR_FMCLPEN                  RCC_AHB3LPENR_FMCLPEN_Msk

+#define RCC_AHB3LPENR_QSPILPEN_Pos             (14U)

+#define RCC_AHB3LPENR_QSPILPEN_Msk             (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos)         /*!< 0x00004000 */

+#define RCC_AHB3LPENR_QSPILPEN                 RCC_AHB3LPENR_QSPILPEN_Msk

+#define RCC_AHB3LPENR_SDMMC1LPEN_Pos           (16U)

+#define RCC_AHB3LPENR_SDMMC1LPEN_Msk           (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos)       /*!< 0x00010000 */

+#define RCC_AHB3LPENR_SDMMC1LPEN               RCC_AHB3LPENR_SDMMC1LPEN_Msk

+#define RCC_AHB3LPENR_DTCM1LPEN_Pos            (28U)

+#define RCC_AHB3LPENR_DTCM1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos)        /*!< 0x10000000 */

+#define RCC_AHB3LPENR_DTCM1LPEN                RCC_AHB3LPENR_DTCM1LPEN_Msk

+#define RCC_AHB3LPENR_DTCM2LPEN_Pos            (29U)

+#define RCC_AHB3LPENR_DTCM2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos)        /*!< 0x20000000 */

+#define RCC_AHB3LPENR_DTCM2LPEN                RCC_AHB3LPENR_DTCM2LPEN_Msk

+#define RCC_AHB3LPENR_ITCMLPEN_Pos             (30U)

+#define RCC_AHB3LPENR_ITCMLPEN_Msk             (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos)         /*!< 0x40000000 */

+#define RCC_AHB3LPENR_ITCMLPEN                 RCC_AHB3LPENR_ITCMLPEN_Msk

+#define RCC_AHB3LPENR_AXISRAMLPEN_Pos          (31U)

+#define RCC_AHB3LPENR_AXISRAMLPEN_Msk          (0x1UL << RCC_AHB3LPENR_AXISRAMLPEN_Pos)      /*!< 0x80000000 */

+#define RCC_AHB3LPENR_AXISRAMLPEN              RCC_AHB3LPENR_AXISRAMLPEN_Msk

+

+

+/********************  Bit definition for RCC_AHB1LPENR register  ***************/

+#define RCC_AHB1LPENR_DMA1LPEN_Pos             (0U)

+#define RCC_AHB1LPENR_DMA1LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB1LPENR_DMA1LPEN                 RCC_AHB1LPENR_DMA1LPEN_Msk

+#define RCC_AHB1LPENR_DMA2LPEN_Pos             (1U)

+#define RCC_AHB1LPENR_DMA2LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */

+#define RCC_AHB1LPENR_DMA2LPEN                 RCC_AHB1LPENR_DMA2LPEN_Msk

+#define RCC_AHB1LPENR_ADC12LPEN_Pos            (5U)

+#define RCC_AHB1LPENR_ADC12LPEN_Msk            (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB1LPENR_ADC12LPEN                RCC_AHB1LPENR_ADC12LPEN_Msk

+#define RCC_AHB1LPENR_ETH1MACLPEN_Pos          (15U)

+#define RCC_AHB1LPENR_ETH1MACLPEN_Msk          (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) /*!< 0x00008000 */

+#define RCC_AHB1LPENR_ETH1MACLPEN              RCC_AHB1LPENR_ETH1MACLPEN_Msk

+#define RCC_AHB1LPENR_ETH1TXLPEN_Pos           (16U)

+#define RCC_AHB1LPENR_ETH1TXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00010000 */

+#define RCC_AHB1LPENR_ETH1TXLPEN               RCC_AHB1LPENR_ETH1TXLPEN_Msk

+#define RCC_AHB1LPENR_ETH1RXLPEN_Pos           (17U)

+#define RCC_AHB1LPENR_ETH1RXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00020000 */

+#define RCC_AHB1LPENR_ETH1RXLPEN               RCC_AHB1LPENR_ETH1RXLPEN_Msk

+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos        (25U)

+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */

+#define RCC_AHB1LPENR_USB1OTGHSLPEN            RCC_AHB1LPENR_USB1OTGHSLPEN_Msk

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos    (26U)

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN        RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGFSLPEN_Pos        (27U)

+#define RCC_AHB1LPENR_USB2OTGFSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB2OTGFSLPEN_Pos) /*!< 0x08000000 */

+#define RCC_AHB1LPENR_USB2OTGFSLPEN            RCC_AHB1LPENR_USB2OTGFSLPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos    (28U)

+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos) /*!< 0x10000000 */

+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN        RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk

+

+/* Legacy define */

+#define RCC_AHB1LPENR_USB2OTGHSLPEN_Pos        RCC_AHB1LPENR_USB2OTGFSLPEN_Pos

+#define RCC_AHB1LPENR_USB2OTGHSLPEN_Msk        RCC_AHB1LPENR_USB2OTGFSLPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGHSLPEN            RCC_AHB1LPENR_USB2OTGFSLPEN

+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Pos    RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos

+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Msk    RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN        RCC_AHB1LPENR_USB2OTGFSULPILPEN

+

+/********************  Bit definition for RCC_AHB2LPENR register  ***************/

+#define RCC_AHB2LPENR_DCMILPEN_Pos             (0U)

+#define RCC_AHB2LPENR_DCMILPEN_Msk             (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB2LPENR_DCMILPEN                 RCC_AHB2LPENR_DCMILPEN_Msk

+#define RCC_AHB2LPENR_CRYPLPEN_Pos             (4U)

+#define RCC_AHB2LPENR_CRYPLPEN_Msk             (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */

+#define RCC_AHB2LPENR_CRYPLPEN                 RCC_AHB2LPENR_CRYPLPEN_Msk

+#define RCC_AHB2LPENR_HASHLPEN_Pos             (5U)

+#define RCC_AHB2LPENR_HASHLPEN_Msk             (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB2LPENR_HASHLPEN                 RCC_AHB2LPENR_HASHLPEN_Msk

+#define RCC_AHB2LPENR_RNGLPEN_Pos              (6U)

+#define RCC_AHB2LPENR_RNGLPEN_Msk              (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */

+#define RCC_AHB2LPENR_RNGLPEN                  RCC_AHB2LPENR_RNGLPEN_Msk

+#define RCC_AHB2LPENR_SDMMC2LPEN_Pos           (9U)

+#define RCC_AHB2LPENR_SDMMC2LPEN_Msk           (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */

+#define RCC_AHB2LPENR_SDMMC2LPEN               RCC_AHB2LPENR_SDMMC2LPEN_Msk

+#define RCC_AHB2LPENR_SRAM1LPEN_Pos          (29U)

+#define RCC_AHB2LPENR_SRAM1LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos) /*!< 0x20000000 */

+#define RCC_AHB2LPENR_SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN_Msk

+#define RCC_AHB2LPENR_SRAM2LPEN_Pos          (30U)

+#define RCC_AHB2LPENR_SRAM2LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */

+#define RCC_AHB2LPENR_SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN_Msk

+#define RCC_AHB2LPENR_SRAM3LPEN_Pos          (31U)

+#define RCC_AHB2LPENR_SRAM3LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM3LPEN_Pos) /*!< 0x80000000 */

+#define RCC_AHB2LPENR_SRAM3LPEN              RCC_AHB2LPENR_SRAM3LPEN_Msk

+

+/* Legacy define */

+#define RCC_AHB2LPENR_D2SRAM1LPEN_Pos          RCC_AHB2LPENR_SRAM1LPEN_Pos

+#define RCC_AHB2LPENR_D2SRAM1LPEN_Msk          RCC_AHB2LPENR_SRAM1LPEN_Msk

+#define RCC_AHB2LPENR_D2SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN

+#define RCC_AHB2LPENR_D2SRAM2LPEN_Pos          RCC_AHB2LPENR_SRAM2LPEN_Pos

+#define RCC_AHB2LPENR_D2SRAM2LPEN_Msk          RCC_AHB2LPENR_SRAM2LPEN_Msk

+#define RCC_AHB2LPENR_D2SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN

+#define RCC_AHB2LPENR_D2SRAM3LPEN_Pos          RCC_AHB2LPENR_SRAM3LPEN_Pos

+#define RCC_AHB2LPENR_D2SRAM3LPEN_Msk          RCC_AHB2LPENR_SRAM3LPEN_Msk

+#define RCC_AHB2LPENR_D2SRAM3LPEN              RCC_AHB2LPENR_SRAM3LPEN

+

+/********************  Bit definition for RCC_AHB4LPENR register  ******************/

+#define RCC_AHB4LPENR_GPIOALPEN_Pos            (0U)

+#define RCC_AHB4LPENR_GPIOALPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB4LPENR_GPIOALPEN                RCC_AHB4LPENR_GPIOALPEN_Msk

+#define RCC_AHB4LPENR_GPIOBLPEN_Pos            (1U)

+#define RCC_AHB4LPENR_GPIOBLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */

+#define RCC_AHB4LPENR_GPIOBLPEN                RCC_AHB4LPENR_GPIOBLPEN_Msk

+#define RCC_AHB4LPENR_GPIOCLPEN_Pos            (2U)

+#define RCC_AHB4LPENR_GPIOCLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */

+#define RCC_AHB4LPENR_GPIOCLPEN                RCC_AHB4LPENR_GPIOCLPEN_Msk

+#define RCC_AHB4LPENR_GPIODLPEN_Pos            (3U)

+#define RCC_AHB4LPENR_GPIODLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */

+#define RCC_AHB4LPENR_GPIODLPEN                RCC_AHB4LPENR_GPIODLPEN_Msk

+#define RCC_AHB4LPENR_GPIOELPEN_Pos            (4U)

+#define RCC_AHB4LPENR_GPIOELPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */

+#define RCC_AHB4LPENR_GPIOELPEN                RCC_AHB4LPENR_GPIOELPEN_Msk

+#define RCC_AHB4LPENR_GPIOFLPEN_Pos            (5U)

+#define RCC_AHB4LPENR_GPIOFLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB4LPENR_GPIOFLPEN                RCC_AHB4LPENR_GPIOFLPEN_Msk

+#define RCC_AHB4LPENR_GPIOGLPEN_Pos            (6U)

+#define RCC_AHB4LPENR_GPIOGLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */

+#define RCC_AHB4LPENR_GPIOGLPEN                RCC_AHB4LPENR_GPIOGLPEN_Msk

+#define RCC_AHB4LPENR_GPIOHLPEN_Pos            (7U)

+#define RCC_AHB4LPENR_GPIOHLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */

+#define RCC_AHB4LPENR_GPIOHLPEN                RCC_AHB4LPENR_GPIOHLPEN_Msk

+#define RCC_AHB4LPENR_GPIOILPEN_Pos            (8U)

+#define RCC_AHB4LPENR_GPIOILPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */

+#define RCC_AHB4LPENR_GPIOILPEN                RCC_AHB4LPENR_GPIOILPEN_Msk

+#define RCC_AHB4LPENR_GPIOJLPEN_Pos            (9U)

+#define RCC_AHB4LPENR_GPIOJLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */

+#define RCC_AHB4LPENR_GPIOJLPEN                RCC_AHB4LPENR_GPIOJLPEN_Msk

+#define RCC_AHB4LPENR_GPIOKLPEN_Pos            (10U)

+#define RCC_AHB4LPENR_GPIOKLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */

+#define RCC_AHB4LPENR_GPIOKLPEN                RCC_AHB4LPENR_GPIOKLPEN_Msk

+#define RCC_AHB4LPENR_CRCLPEN_Pos              (19U)

+#define RCC_AHB4LPENR_CRCLPEN_Msk              (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */

+#define RCC_AHB4LPENR_CRCLPEN                  RCC_AHB4LPENR_CRCLPEN_Msk

+#define RCC_AHB4LPENR_BDMALPEN_Pos             (21U)

+#define RCC_AHB4LPENR_BDMALPEN_Msk             (0x1UL << RCC_AHB4LPENR_BDMALPEN_Pos) /*!< 0x00200000 */

+#define RCC_AHB4LPENR_BDMALPEN                 RCC_AHB4LPENR_BDMALPEN_Msk

+#define RCC_AHB4LPENR_ADC3LPEN_Pos             (24U)

+#define RCC_AHB4LPENR_ADC3LPEN_Msk             (0x1UL << RCC_AHB4LPENR_ADC3LPEN_Pos) /*!< 0x01000000 */

+#define RCC_AHB4LPENR_ADC3LPEN                 RCC_AHB4LPENR_ADC3LPEN_Msk

+#define RCC_AHB4LPENR_BKPRAMLPEN_Pos           (28U)

+#define RCC_AHB4LPENR_BKPRAMLPEN_Msk           (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */

+#define RCC_AHB4LPENR_BKPRAMLPEN               RCC_AHB4LPENR_BKPRAMLPEN_Msk

+#define RCC_AHB4LPENR_SRAM4LPEN_Pos            (29U)

+#define RCC_AHB4LPENR_SRAM4LPEN_Msk            (0x1UL << RCC_AHB4LPENR_SRAM4LPEN_Pos) /*!< 0x20000000 */

+#define RCC_AHB4LPENR_SRAM4LPEN                RCC_AHB4LPENR_SRAM4LPEN_Msk

+

+/* Legacy define */

+#define RCC_AHB4LPENR_D3SRAM1LPEN_Pos          RCC_AHB4LPENR_SRAM4LPEN_Pos

+#define RCC_AHB4LPENR_D3SRAM1LPEN_Msk          RCC_AHB4LPENR_SRAM4LPEN_Msk

+#define RCC_AHB4LPENR_D3SRAM1LPEN              RCC_AHB4LPENR_SRAM4LPEN

+/********************  Bit definition for RCC_APB3LPENR register  ******************/

+#define RCC_APB3LPENR_LTDCLPEN_Pos             (3U)

+#define RCC_APB3LPENR_LTDCLPEN_Msk             (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB3LPENR_LTDCLPEN                 RCC_APB3LPENR_LTDCLPEN_Msk

+#define RCC_APB3LPENR_WWDG1LPEN_Pos            (6U)

+#define RCC_APB3LPENR_WWDG1LPEN_Msk            (0x1UL << RCC_APB3LPENR_WWDG1LPEN_Pos) /*!< 0x00000040 */

+#define RCC_APB3LPENR_WWDG1LPEN                RCC_APB3LPENR_WWDG1LPEN_Msk

+

+/********************  Bit definition for RCC_APB1LLPENR register  ******************/

+

+#define RCC_APB1LLPENR_TIM2LPEN_Pos            (0U)

+#define RCC_APB1LLPENR_TIM2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */

+#define RCC_APB1LLPENR_TIM2LPEN                RCC_APB1LLPENR_TIM2LPEN_Msk

+#define RCC_APB1LLPENR_TIM3LPEN_Pos            (1U)

+#define RCC_APB1LLPENR_TIM3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1LLPENR_TIM3LPEN                RCC_APB1LLPENR_TIM3LPEN_Msk

+#define RCC_APB1LLPENR_TIM4LPEN_Pos            (2U)

+#define RCC_APB1LLPENR_TIM4LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1LLPENR_TIM4LPEN                RCC_APB1LLPENR_TIM4LPEN_Msk

+#define RCC_APB1LLPENR_TIM5LPEN_Pos            (3U)

+#define RCC_APB1LLPENR_TIM5LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB1LLPENR_TIM5LPEN                RCC_APB1LLPENR_TIM5LPEN_Msk

+#define RCC_APB1LLPENR_TIM6LPEN_Pos            (4U)

+#define RCC_APB1LLPENR_TIM6LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1LLPENR_TIM6LPEN                RCC_APB1LLPENR_TIM6LPEN_Msk

+#define RCC_APB1LLPENR_TIM7LPEN_Pos            (5U)

+#define RCC_APB1LLPENR_TIM7LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1LLPENR_TIM7LPEN                RCC_APB1LLPENR_TIM7LPEN_Msk

+#define RCC_APB1LLPENR_TIM12LPEN_Pos           (6U)

+#define RCC_APB1LLPENR_TIM12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */

+#define RCC_APB1LLPENR_TIM12LPEN               RCC_APB1LLPENR_TIM12LPEN_Msk

+#define RCC_APB1LLPENR_TIM13LPEN_Pos           (7U)

+#define RCC_APB1LLPENR_TIM13LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB1LLPENR_TIM13LPEN               RCC_APB1LLPENR_TIM13LPEN_Msk

+#define RCC_APB1LLPENR_TIM14LPEN_Pos           (8U)

+#define RCC_APB1LLPENR_TIM14LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1LLPENR_TIM14LPEN               RCC_APB1LLPENR_TIM14LPEN_Msk

+#define RCC_APB1LLPENR_LPTIM1LPEN_Pos          (9U)

+#define RCC_APB1LLPENR_LPTIM1LPEN_Msk          (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */

+#define RCC_APB1LLPENR_LPTIM1LPEN              RCC_APB1LLPENR_LPTIM1LPEN_Msk

+

+

+#define RCC_APB1LLPENR_SPI2LPEN_Pos            (14U)

+#define RCC_APB1LLPENR_SPI2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */

+#define RCC_APB1LLPENR_SPI2LPEN                RCC_APB1LLPENR_SPI2LPEN_Msk

+#define RCC_APB1LLPENR_SPI3LPEN_Pos            (15U)

+#define RCC_APB1LLPENR_SPI3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */

+#define RCC_APB1LLPENR_SPI3LPEN                RCC_APB1LLPENR_SPI3LPEN_Msk

+#define RCC_APB1LLPENR_SPDIFRXLPEN_Pos         (16U)

+#define RCC_APB1LLPENR_SPDIFRXLPEN_Msk         (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB1LLPENR_SPDIFRXLPEN             RCC_APB1LLPENR_SPDIFRXLPEN_Msk

+#define RCC_APB1LLPENR_USART2LPEN_Pos          (17U)

+#define RCC_APB1LLPENR_USART2LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */

+#define RCC_APB1LLPENR_USART2LPEN              RCC_APB1LLPENR_USART2LPEN_Msk

+#define RCC_APB1LLPENR_USART3LPEN_Pos          (18U)

+#define RCC_APB1LLPENR_USART3LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */

+#define RCC_APB1LLPENR_USART3LPEN              RCC_APB1LLPENR_USART3LPEN_Msk

+#define RCC_APB1LLPENR_UART4LPEN_Pos           (19U)

+#define RCC_APB1LLPENR_UART4LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */

+#define RCC_APB1LLPENR_UART4LPEN               RCC_APB1LLPENR_UART4LPEN_Msk

+#define RCC_APB1LLPENR_UART5LPEN_Pos           (20U)

+#define RCC_APB1LLPENR_UART5LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */

+#define RCC_APB1LLPENR_UART5LPEN               RCC_APB1LLPENR_UART5LPEN_Msk

+#define RCC_APB1LLPENR_I2C1LPEN_Pos            (21U)

+#define RCC_APB1LLPENR_I2C1LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */

+#define RCC_APB1LLPENR_I2C1LPEN                RCC_APB1LLPENR_I2C1LPEN_Msk

+#define RCC_APB1LLPENR_I2C2LPEN_Pos            (22U)

+#define RCC_APB1LLPENR_I2C2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */

+#define RCC_APB1LLPENR_I2C2LPEN                RCC_APB1LLPENR_I2C2LPEN_Msk

+#define RCC_APB1LLPENR_I2C3LPEN_Pos            (23U)

+#define RCC_APB1LLPENR_I2C3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */

+#define RCC_APB1LLPENR_I2C3LPEN                RCC_APB1LLPENR_I2C3LPEN_Msk

+#define RCC_APB1LLPENR_CECLPEN_Pos             (27U)

+#define RCC_APB1LLPENR_CECLPEN_Msk             (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */

+#define RCC_APB1LLPENR_CECLPEN                 RCC_APB1LLPENR_CECLPEN_Msk

+#define RCC_APB1LLPENR_DAC12LPEN_Pos           (29U)

+#define RCC_APB1LLPENR_DAC12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */

+#define RCC_APB1LLPENR_DAC12LPEN               RCC_APB1LLPENR_DAC12LPEN_Msk

+#define RCC_APB1LLPENR_UART7LPEN_Pos           (30U)

+#define RCC_APB1LLPENR_UART7LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */

+#define RCC_APB1LLPENR_UART7LPEN               RCC_APB1LLPENR_UART7LPEN_Msk

+#define RCC_APB1LLPENR_UART8LPEN_Pos           (31U)

+#define RCC_APB1LLPENR_UART8LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */

+#define RCC_APB1LLPENR_UART8LPEN               RCC_APB1LLPENR_UART8LPEN_Msk

+

+/* Legacy define */

+#define RCC_APB1LLPENR_HDMICECEN_Pos           RCC_APB1LLPENR_CECLPEN_Pos

+#define RCC_APB1LLPENR_HDMICECEN_Msk           RCC_APB1LLPENR_CECLPEN_Msk

+#define RCC_APB1LLPENR_HDMICECEN               RCC_APB1LLPENR_CECLPEN

+/********************  Bit definition for RCC_APB1HLPENR register  ******************/

+#define RCC_APB1HLPENR_CRSLPEN_Pos             (1U)

+#define RCC_APB1HLPENR_CRSLPEN_Msk             (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1HLPENR_CRSLPEN                 RCC_APB1HLPENR_CRSLPEN_Msk

+#define RCC_APB1HLPENR_SWPMILPEN_Pos           (2U)

+#define RCC_APB1HLPENR_SWPMILPEN_Msk           (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1HLPENR_SWPMILPEN               RCC_APB1HLPENR_SWPMILPEN_Msk

+#define RCC_APB1HLPENR_OPAMPLPEN_Pos           (4U)

+#define RCC_APB1HLPENR_OPAMPLPEN_Msk           (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1HLPENR_OPAMPLPEN               RCC_APB1HLPENR_OPAMPLPEN_Msk

+#define RCC_APB1HLPENR_MDIOSLPEN_Pos           (5U)

+#define RCC_APB1HLPENR_MDIOSLPEN_Msk           (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1HLPENR_MDIOSLPEN               RCC_APB1HLPENR_MDIOSLPEN_Msk

+#define RCC_APB1HLPENR_FDCANLPEN_Pos           (8U)

+#define RCC_APB1HLPENR_FDCANLPEN_Msk           (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1HLPENR_FDCANLPEN               RCC_APB1HLPENR_FDCANLPEN_Msk

+

+/********************  Bit definition for RCC_APB2LPENR register  ******************/

+#define RCC_APB2LPENR_TIM1LPEN_Pos             (0U)

+#define RCC_APB2LPENR_TIM1LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */

+#define RCC_APB2LPENR_TIM1LPEN                 RCC_APB2LPENR_TIM1LPEN_Msk

+#define RCC_APB2LPENR_TIM8LPEN_Pos             (1U)

+#define RCC_APB2LPENR_TIM8LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB2LPENR_TIM8LPEN                 RCC_APB2LPENR_TIM8LPEN_Msk

+#define RCC_APB2LPENR_USART1LPEN_Pos           (4U)

+#define RCC_APB2LPENR_USART1LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB2LPENR_USART1LPEN               RCC_APB2LPENR_USART1LPEN_Msk

+#define RCC_APB2LPENR_USART6LPEN_Pos           (5U)

+#define RCC_APB2LPENR_USART6LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB2LPENR_USART6LPEN               RCC_APB2LPENR_USART6LPEN_Msk

+#define RCC_APB2LPENR_SPI1LPEN_Pos             (12U)

+#define RCC_APB2LPENR_SPI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */

+#define RCC_APB2LPENR_SPI1LPEN                 RCC_APB2LPENR_SPI1LPEN_Msk

+#define RCC_APB2LPENR_SPI4LPEN_Pos             (13U)

+#define RCC_APB2LPENR_SPI4LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */

+#define RCC_APB2LPENR_SPI4LPEN                 RCC_APB2LPENR_SPI4LPEN_Msk

+#define RCC_APB2LPENR_TIM15LPEN_Pos            (16U)

+#define RCC_APB2LPENR_TIM15LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB2LPENR_TIM15LPEN                RCC_APB2LPENR_TIM15LPEN_Msk

+#define RCC_APB2LPENR_TIM16LPEN_Pos            (17U)

+#define RCC_APB2LPENR_TIM16LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */

+#define RCC_APB2LPENR_TIM16LPEN                RCC_APB2LPENR_TIM16LPEN_Msk

+#define RCC_APB2LPENR_TIM17LPEN_Pos            (18U)

+#define RCC_APB2LPENR_TIM17LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */

+#define RCC_APB2LPENR_TIM17LPEN                RCC_APB2LPENR_TIM17LPEN_Msk

+#define RCC_APB2LPENR_SPI5LPEN_Pos             (20U)

+#define RCC_APB2LPENR_SPI5LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */

+#define RCC_APB2LPENR_SPI5LPEN                 RCC_APB2LPENR_SPI5LPEN_Msk

+#define RCC_APB2LPENR_SAI1LPEN_Pos             (22U)

+#define RCC_APB2LPENR_SAI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */

+#define RCC_APB2LPENR_SAI1LPEN                 RCC_APB2LPENR_SAI1LPEN_Msk

+#define RCC_APB2LPENR_SAI2LPEN_Pos             (23U)

+#define RCC_APB2LPENR_SAI2LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */

+#define RCC_APB2LPENR_SAI2LPEN                 RCC_APB2LPENR_SAI2LPEN_Msk

+#define RCC_APB2LPENR_SAI3LPEN_Pos             (24U)

+#define RCC_APB2LPENR_SAI3LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI3LPEN_Pos) /*!< 0x01000000 */

+#define RCC_APB2LPENR_SAI3LPEN                 RCC_APB2LPENR_SAI3LPEN_Msk

+#define RCC_APB2LPENR_DFSDM1LPEN_Pos           (28U)

+#define RCC_APB2LPENR_DFSDM1LPEN_Msk           (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x10000000 */

+#define RCC_APB2LPENR_DFSDM1LPEN               RCC_APB2LPENR_DFSDM1LPEN_Msk

+#define RCC_APB2LPENR_HRTIMLPEN_Pos            (29U)

+#define RCC_APB2LPENR_HRTIMLPEN_Msk            (0x1UL << RCC_APB2LPENR_HRTIMLPEN_Pos) /*!< 0x20000000 */

+#define RCC_APB2LPENR_HRTIMLPEN                RCC_APB2LPENR_HRTIMLPEN_Msk

+

+/********************  Bit definition for RCC_APB4LPENR register  ******************/

+#define RCC_APB4LPENR_SYSCFGLPEN_Pos           (1U)

+#define RCC_APB4LPENR_SYSCFGLPEN_Msk           (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB4LPENR_SYSCFGLPEN               RCC_APB4LPENR_SYSCFGLPEN_Msk

+#define RCC_APB4LPENR_LPUART1LPEN_Pos          (3U)

+#define RCC_APB4LPENR_LPUART1LPEN_Msk          (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB4LPENR_LPUART1LPEN              RCC_APB4LPENR_LPUART1LPEN_Msk

+#define RCC_APB4LPENR_SPI6LPEN_Pos             (5U)

+#define RCC_APB4LPENR_SPI6LPEN_Msk             (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB4LPENR_SPI6LPEN                 RCC_APB4LPENR_SPI6LPEN_Msk

+#define RCC_APB4LPENR_I2C4LPEN_Pos             (7U)

+#define RCC_APB4LPENR_I2C4LPEN_Msk             (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB4LPENR_I2C4LPEN                 RCC_APB4LPENR_I2C4LPEN_Msk

+#define RCC_APB4LPENR_LPTIM2LPEN_Pos           (9U)

+#define RCC_APB4LPENR_LPTIM2LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */

+#define RCC_APB4LPENR_LPTIM2LPEN               RCC_APB4LPENR_LPTIM2LPEN_Msk

+#define RCC_APB4LPENR_LPTIM3LPEN_Pos           (10U)

+#define RCC_APB4LPENR_LPTIM3LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */

+#define RCC_APB4LPENR_LPTIM3LPEN               RCC_APB4LPENR_LPTIM3LPEN_Msk

+#define RCC_APB4LPENR_LPTIM4LPEN_Pos           (11U)

+#define RCC_APB4LPENR_LPTIM4LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) /*!< 0x00000800 */

+#define RCC_APB4LPENR_LPTIM4LPEN               RCC_APB4LPENR_LPTIM4LPEN_Msk

+#define RCC_APB4LPENR_LPTIM5LPEN_Pos           (12U)

+#define RCC_APB4LPENR_LPTIM5LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) /*!< 0x00001000 */

+#define RCC_APB4LPENR_LPTIM5LPEN               RCC_APB4LPENR_LPTIM5LPEN_Msk

+#define RCC_APB4LPENR_COMP12LPEN_Pos           (14U)

+#define RCC_APB4LPENR_COMP12LPEN_Msk           (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */

+#define RCC_APB4LPENR_COMP12LPEN               RCC_APB4LPENR_COMP12LPEN_Msk

+#define RCC_APB4LPENR_VREFLPEN_Pos             (15U)

+#define RCC_APB4LPENR_VREFLPEN_Msk             (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */

+#define RCC_APB4LPENR_VREFLPEN                 RCC_APB4LPENR_VREFLPEN_Msk

+#define RCC_APB4LPENR_RTCAPBLPEN_Pos           (16U)

+#define RCC_APB4LPENR_RTCAPBLPEN_Msk           (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB4LPENR_RTCAPBLPEN               RCC_APB4LPENR_RTCAPBLPEN_Msk

+#define RCC_APB4LPENR_SAI4LPEN_Pos             (21U)

+#define RCC_APB4LPENR_SAI4LPEN_Msk             (0x1UL << RCC_APB4LPENR_SAI4LPEN_Pos) /*!< 0x00200000 */

+#define RCC_APB4LPENR_SAI4LPEN                 RCC_APB4LPENR_SAI4LPEN_Msk

+

+

+/********************  Bit definition for RCC_RSR register  *******************/

+#define RCC_RSR_RMVF_Pos                       (16U)

+#define RCC_RSR_RMVF_Msk                       (0x1UL << RCC_RSR_RMVF_Pos)     /*!< 0x00010000 */

+#define RCC_RSR_RMVF                           RCC_RSR_RMVF_Msk

+#define RCC_RSR_CPURSTF_Pos                    (17U)

+#define RCC_RSR_CPURSTF_Msk                    (0x1UL << RCC_RSR_CPURSTF_Pos)  /*!< 0x00020000 */

+#define RCC_RSR_CPURSTF                        RCC_RSR_CPURSTF_Msk

+#define RCC_RSR_D1RSTF_Pos                     (19U)

+#define RCC_RSR_D1RSTF_Msk                     (0x1UL << RCC_RSR_D1RSTF_Pos)   /*!< 0x00080000 */

+#define RCC_RSR_D1RSTF                         RCC_RSR_D1RSTF_Msk

+#define RCC_RSR_D2RSTF_Pos                     (20U)

+#define RCC_RSR_D2RSTF_Msk                     (0x1UL << RCC_RSR_D2RSTF_Pos)   /*!< 0x00100000 */

+#define RCC_RSR_D2RSTF                         RCC_RSR_D2RSTF_Msk

+#define RCC_RSR_BORRSTF_Pos                    (21U)

+#define RCC_RSR_BORRSTF_Msk                    (0x1UL << RCC_RSR_BORRSTF_Pos)  /*!< 0x00200000 */

+#define RCC_RSR_BORRSTF                        RCC_RSR_BORRSTF_Msk

+#define RCC_RSR_PINRSTF_Pos                    (22U)

+#define RCC_RSR_PINRSTF_Msk                    (0x1UL << RCC_RSR_PINRSTF_Pos)  /*!< 0x00400000 */

+#define RCC_RSR_PINRSTF                        RCC_RSR_PINRSTF_Msk

+#define RCC_RSR_PORRSTF_Pos                    (23U)

+#define RCC_RSR_PORRSTF_Msk                    (0x1UL << RCC_RSR_PORRSTF_Pos)  /*!< 0x00800000 */

+#define RCC_RSR_PORRSTF                        RCC_RSR_PORRSTF_Msk

+#define RCC_RSR_SFTRSTF_Pos                    (24U)

+#define RCC_RSR_SFTRSTF_Msk                    (0x1UL << RCC_RSR_SFTRSTF_Pos)  /*!< 0x01000000 */

+#define RCC_RSR_SFTRSTF                        RCC_RSR_SFTRSTF_Msk

+#define RCC_RSR_IWDG1RSTF_Pos                  (26U)

+#define RCC_RSR_IWDG1RSTF_Msk                  (0x1UL << RCC_RSR_IWDG1RSTF_Pos) /*!< 0x04000000 */

+#define RCC_RSR_IWDG1RSTF                      RCC_RSR_IWDG1RSTF_Msk

+#define RCC_RSR_WWDG1RSTF_Pos                  (28U)

+#define RCC_RSR_WWDG1RSTF_Msk                  (0x1UL << RCC_RSR_WWDG1RSTF_Pos) /*!< 0x10000000 */

+#define RCC_RSR_WWDG1RSTF                      RCC_RSR_WWDG1RSTF_Msk

+

+#define RCC_RSR_LPWRRSTF_Pos                   (30U)

+#define RCC_RSR_LPWRRSTF_Msk                   (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */

+#define RCC_RSR_LPWRRSTF                       RCC_RSR_LPWRRSTF_Msk

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    RNG                                     */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for RNG_CR register  *******************/

+#define RNG_CR_RNGEN_Pos    (2U)

+#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */

+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk

+#define RNG_CR_IE_Pos       (3U)

+#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */

+#define RNG_CR_IE           RNG_CR_IE_Msk

+#define RNG_CR_CED_Pos      (5U)

+#define RNG_CR_CED_Msk      (0x1UL << RNG_CR_CED_Pos)                          /*!< 0x00000020 */

+#define RNG_CR_CED          RNG_CR_CED_Msk

+

+/********************  Bits definition for RNG_SR register  *******************/

+#define RNG_SR_DRDY_Pos     (0U)

+#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */

+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk

+#define RNG_SR_CECS_Pos     (1U)

+#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */

+#define RNG_SR_CECS         RNG_SR_CECS_Msk

+#define RNG_SR_SECS_Pos     (2U)

+#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */

+#define RNG_SR_SECS         RNG_SR_SECS_Msk

+#define RNG_SR_CEIS_Pos     (5U)

+#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */

+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk

+#define RNG_SR_SEIS_Pos     (6U)

+#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */

+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                           Real-Time Clock (RTC)                            */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for RTC_TR register  *******************/

+#define RTC_TR_PM_Pos                  (22U)

+#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */

+#define RTC_TR_PM                      RTC_TR_PM_Msk

+#define RTC_TR_HT_Pos                  (20U)

+#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */

+#define RTC_TR_HT                      RTC_TR_HT_Msk

+#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */

+#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */

+#define RTC_TR_HU_Pos                  (16U)

+#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */

+#define RTC_TR_HU                      RTC_TR_HU_Msk

+#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */

+#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */

+#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */

+#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */

+#define RTC_TR_MNT_Pos                 (12U)

+#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */

+#define RTC_TR_MNT                     RTC_TR_MNT_Msk

+#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */

+#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */

+#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */

+#define RTC_TR_MNU_Pos                 (8U)

+#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */

+#define RTC_TR_MNU                     RTC_TR_MNU_Msk

+#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */

+#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */

+#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */

+#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */

+#define RTC_TR_ST_Pos                  (4U)

+#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */

+#define RTC_TR_ST                      RTC_TR_ST_Msk

+#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */

+#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */

+#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */

+#define RTC_TR_SU_Pos                  (0U)

+#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */

+#define RTC_TR_SU                      RTC_TR_SU_Msk

+#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */

+#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */

+#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */

+#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_DR register  *******************/

+#define RTC_DR_YT_Pos                  (20U)

+#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */

+#define RTC_DR_YT                      RTC_DR_YT_Msk

+#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */

+#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */

+#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */

+#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */

+#define RTC_DR_YU_Pos                  (16U)

+#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */

+#define RTC_DR_YU                      RTC_DR_YU_Msk

+#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */

+#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */

+#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */

+#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */

+#define RTC_DR_WDU_Pos                 (13U)

+#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */

+#define RTC_DR_WDU                     RTC_DR_WDU_Msk

+#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */

+#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */

+#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */

+#define RTC_DR_MT_Pos                  (12U)

+#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */

+#define RTC_DR_MT                      RTC_DR_MT_Msk

+#define RTC_DR_MU_Pos                  (8U)

+#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */

+#define RTC_DR_MU                      RTC_DR_MU_Msk

+#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */

+#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */

+#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */

+#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */

+#define RTC_DR_DT_Pos                  (4U)

+#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */

+#define RTC_DR_DT                      RTC_DR_DT_Msk

+#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */

+#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */

+#define RTC_DR_DU_Pos                  (0U)

+#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */

+#define RTC_DR_DU                      RTC_DR_DU_Msk

+#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */

+#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */

+#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */

+#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_CR register  *******************/

+#define RTC_CR_ITSE_Pos                (24U)

+#define RTC_CR_ITSE_Msk                (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */

+#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk

+#define RTC_CR_COE_Pos                 (23U)

+#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */

+#define RTC_CR_COE                     RTC_CR_COE_Msk

+#define RTC_CR_OSEL_Pos                (21U)

+#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */

+#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk

+#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */

+#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */

+#define RTC_CR_POL_Pos                 (20U)

+#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */

+#define RTC_CR_POL                     RTC_CR_POL_Msk

+#define RTC_CR_COSEL_Pos               (19U)

+#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */

+#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk

+#define RTC_CR_BKP_Pos                 (18U)

+#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */

+#define RTC_CR_BKP                     RTC_CR_BKP_Msk

+#define RTC_CR_SUB1H_Pos               (17U)

+#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */

+#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk

+#define RTC_CR_ADD1H_Pos               (16U)

+#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */

+#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk

+#define RTC_CR_TSIE_Pos                (15U)

+#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */

+#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk

+#define RTC_CR_WUTIE_Pos               (14U)

+#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */

+#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk

+#define RTC_CR_ALRBIE_Pos              (13U)

+#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */

+#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk

+#define RTC_CR_ALRAIE_Pos              (12U)

+#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */

+#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk

+#define RTC_CR_TSE_Pos                 (11U)

+#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */

+#define RTC_CR_TSE                     RTC_CR_TSE_Msk

+#define RTC_CR_WUTE_Pos                (10U)

+#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */

+#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk

+#define RTC_CR_ALRBE_Pos               (9U)

+#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */

+#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk

+#define RTC_CR_ALRAE_Pos               (8U)

+#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */

+#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk

+#define RTC_CR_FMT_Pos                 (6U)

+#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */

+#define RTC_CR_FMT                     RTC_CR_FMT_Msk

+#define RTC_CR_BYPSHAD_Pos             (5U)

+#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */

+#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk

+#define RTC_CR_REFCKON_Pos             (4U)

+#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */

+#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk

+#define RTC_CR_TSEDGE_Pos              (3U)

+#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */

+#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk

+#define RTC_CR_WUCKSEL_Pos             (0U)

+#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */

+#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk

+#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */

+#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */

+#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */

+

+/********************  Bits definition for RTC_ISR register  ******************/

+#define RTC_ISR_ITSF_Pos               (17U)

+#define RTC_ISR_ITSF_Msk               (0x1UL << RTC_ISR_ITSF_Pos)             /*!< 0x00020000 */

+#define RTC_ISR_ITSF                   RTC_ISR_ITSF_Msk

+#define RTC_ISR_RECALPF_Pos            (16U)

+#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)          /*!< 0x00010000 */

+#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk

+#define RTC_ISR_TAMP3F_Pos             (15U)

+#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)           /*!< 0x00008000 */

+#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk

+#define RTC_ISR_TAMP2F_Pos             (14U)

+#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)           /*!< 0x00004000 */

+#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk

+#define RTC_ISR_TAMP1F_Pos             (13U)

+#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)           /*!< 0x00002000 */

+#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk

+#define RTC_ISR_TSOVF_Pos              (12U)

+#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)            /*!< 0x00001000 */

+#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk

+#define RTC_ISR_TSF_Pos                (11U)

+#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)              /*!< 0x00000800 */

+#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk

+#define RTC_ISR_WUTF_Pos               (10U)

+#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)             /*!< 0x00000400 */

+#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk

+#define RTC_ISR_ALRBF_Pos              (9U)

+#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)            /*!< 0x00000200 */

+#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk

+#define RTC_ISR_ALRAF_Pos              (8U)

+#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)            /*!< 0x00000100 */

+#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk

+#define RTC_ISR_INIT_Pos               (7U)

+#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)             /*!< 0x00000080 */

+#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk

+#define RTC_ISR_INITF_Pos              (6U)

+#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)            /*!< 0x00000040 */

+#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk

+#define RTC_ISR_RSF_Pos                (5U)

+#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)              /*!< 0x00000020 */

+#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk

+#define RTC_ISR_INITS_Pos              (4U)

+#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)            /*!< 0x00000010 */

+#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk

+#define RTC_ISR_SHPF_Pos               (3U)

+#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)             /*!< 0x00000008 */

+#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk

+#define RTC_ISR_WUTWF_Pos              (2U)

+#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)            /*!< 0x00000004 */

+#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk

+#define RTC_ISR_ALRBWF_Pos             (1U)

+#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)           /*!< 0x00000002 */

+#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk

+#define RTC_ISR_ALRAWF_Pos             (0U)

+#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)           /*!< 0x00000001 */

+#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk

+

+/********************  Bits definition for RTC_PRER register  *****************/

+#define RTC_PRER_PREDIV_A_Pos          (16U)

+#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */

+#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk

+#define RTC_PRER_PREDIV_S_Pos          (0U)

+#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */

+#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk

+

+/********************  Bits definition for RTC_WUTR register  *****************/

+#define RTC_WUTR_WUT_Pos               (0U)

+#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */

+#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk

+

+/********************  Bits definition for RTC_ALRMAR register  ***************/

+#define RTC_ALRMAR_MSK4_Pos            (31U)

+#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */

+#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk

+#define RTC_ALRMAR_WDSEL_Pos           (30U)

+#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */

+#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk

+#define RTC_ALRMAR_DT_Pos              (28U)

+#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */

+#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk

+#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */

+#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */

+#define RTC_ALRMAR_DU_Pos              (24U)

+#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */

+#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk

+#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */

+#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */

+#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */

+#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */

+#define RTC_ALRMAR_MSK3_Pos            (23U)

+#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */

+#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk

+#define RTC_ALRMAR_PM_Pos              (22U)

+#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */

+#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk

+#define RTC_ALRMAR_HT_Pos              (20U)

+#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */

+#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk

+#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */

+#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */

+#define RTC_ALRMAR_HU_Pos              (16U)

+#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */

+#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk

+#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */

+#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */

+#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */

+#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */

+#define RTC_ALRMAR_MSK2_Pos            (15U)

+#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */

+#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk

+#define RTC_ALRMAR_MNT_Pos             (12U)

+#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */

+#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk

+#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */

+#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */

+#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */

+#define RTC_ALRMAR_MNU_Pos             (8U)

+#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */

+#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk

+#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */

+#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */

+#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */

+#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */

+#define RTC_ALRMAR_MSK1_Pos            (7U)

+#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */

+#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk

+#define RTC_ALRMAR_ST_Pos              (4U)

+#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */

+#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk

+#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */

+#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */

+#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */

+#define RTC_ALRMAR_SU_Pos              (0U)

+#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */

+#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk

+#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */

+#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */

+#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */

+#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_ALRMBR register  ***************/

+#define RTC_ALRMBR_MSK4_Pos            (31U)

+#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */

+#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk

+#define RTC_ALRMBR_WDSEL_Pos           (30U)

+#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */

+#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk

+#define RTC_ALRMBR_DT_Pos              (28U)

+#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */

+#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk

+#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */

+#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */

+#define RTC_ALRMBR_DU_Pos              (24U)

+#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */

+#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk

+#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */

+#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */

+#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */

+#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */

+#define RTC_ALRMBR_MSK3_Pos            (23U)

+#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */

+#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk

+#define RTC_ALRMBR_PM_Pos              (22U)

+#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */

+#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk

+#define RTC_ALRMBR_HT_Pos              (20U)

+#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */

+#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk

+#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */

+#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */

+#define RTC_ALRMBR_HU_Pos              (16U)

+#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */

+#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk

+#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */

+#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */

+#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */

+#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */

+#define RTC_ALRMBR_MSK2_Pos            (15U)

+#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */

+#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk

+#define RTC_ALRMBR_MNT_Pos             (12U)

+#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */

+#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk

+#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */

+#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */

+#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */

+#define RTC_ALRMBR_MNU_Pos             (8U)

+#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */

+#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk

+#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */

+#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */

+#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */

+#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */

+#define RTC_ALRMBR_MSK1_Pos            (7U)

+#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */

+#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk

+#define RTC_ALRMBR_ST_Pos              (4U)

+#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */

+#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk

+#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */

+#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */

+#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */

+#define RTC_ALRMBR_SU_Pos              (0U)

+#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */

+#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk

+#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */

+#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */

+#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */

+#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_WPR register  ******************/

+#define RTC_WPR_KEY_Pos                (0U)

+#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */

+#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk

+

+/********************  Bits definition for RTC_SSR register  ******************/

+#define RTC_SSR_SS_Pos                 (0U)

+#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)            /*!< 0x0000FFFF */

+#define RTC_SSR_SS                     RTC_SSR_SS_Msk

+

+/********************  Bits definition for RTC_SHIFTR register  ***************/

+#define RTC_SHIFTR_SUBFS_Pos           (0U)

+#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */

+#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk

+#define RTC_SHIFTR_ADD1S_Pos           (31U)

+#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */

+#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk

+

+/********************  Bits definition for RTC_TSTR register  *****************/

+#define RTC_TSTR_PM_Pos                (22U)

+#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */

+#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk

+#define RTC_TSTR_HT_Pos                (20U)

+#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */

+#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk

+#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */

+#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */

+#define RTC_TSTR_HU_Pos                (16U)

+#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */

+#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk

+#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */

+#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */

+#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */

+#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */

+#define RTC_TSTR_MNT_Pos               (12U)

+#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */

+#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk

+#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */

+#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */

+#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */

+#define RTC_TSTR_MNU_Pos               (8U)

+#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */

+#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk

+#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */

+#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */

+#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */

+#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */

+#define RTC_TSTR_ST_Pos                (4U)

+#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */

+#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk

+#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */

+#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */

+#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */

+#define RTC_TSTR_SU_Pos                (0U)

+#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */

+#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk

+#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */

+#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */

+#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */

+#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_TSDR register  *****************/

+#define RTC_TSDR_WDU_Pos               (13U)

+#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */

+#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk

+#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */

+#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */

+#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */

+#define RTC_TSDR_MT_Pos                (12U)

+#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */

+#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk

+#define RTC_TSDR_MU_Pos                (8U)

+#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */

+#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk

+#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */

+#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */

+#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */

+#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */

+#define RTC_TSDR_DT_Pos                (4U)

+#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */

+#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk

+#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */

+#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */

+#define RTC_TSDR_DU_Pos                (0U)

+#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */

+#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk

+#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */

+#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */

+#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */

+#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_TSSSR register  ****************/

+#define RTC_TSSSR_SS_Pos               (0U)

+#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)          /*!< 0x0000FFFF */

+#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk

+

+/********************  Bits definition for RTC_CALR register  *****************/

+#define RTC_CALR_CALP_Pos              (15U)

+#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */

+#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk

+#define RTC_CALR_CALW8_Pos             (14U)

+#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */

+#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk

+#define RTC_CALR_CALW16_Pos            (13U)

+#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */

+#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk

+#define RTC_CALR_CALM_Pos              (0U)

+#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */

+#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk

+#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */

+#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */

+#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */

+#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */

+#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */

+#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */

+#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */

+#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */

+#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */

+

+/********************  Bits definition for RTC_TAMPCR register  ***************/

+#define RTC_TAMPCR_TAMP3MF_Pos         (24U)

+#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)       /*!< 0x01000000 */

+#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk

+#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)

+#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)  /*!< 0x00800000 */

+#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk

+#define RTC_TAMPCR_TAMP3IE_Pos         (22U)

+#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)       /*!< 0x00400000 */

+#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk

+#define RTC_TAMPCR_TAMP2MF_Pos         (21U)

+#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)       /*!< 0x00200000 */

+#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk

+#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)

+#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)  /*!< 0x00100000 */

+#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk

+#define RTC_TAMPCR_TAMP2IE_Pos         (19U)

+#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)       /*!< 0x00080000 */

+#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk

+#define RTC_TAMPCR_TAMP1MF_Pos         (18U)

+#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)       /*!< 0x00040000 */

+#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk

+#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)

+#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)  /*!< 0x00020000 */

+#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk

+#define RTC_TAMPCR_TAMP1IE_Pos         (16U)

+#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)       /*!< 0x00010000 */

+#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk

+#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)

+#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)     /*!< 0x00008000 */

+#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk

+#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)

+#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)      /*!< 0x00006000 */

+#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk

+#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */

+#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */

+#define RTC_TAMPCR_TAMPFLT_Pos         (11U)

+#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)       /*!< 0x00001800 */

+#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk

+#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */

+#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */

+#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)

+#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)      /*!< 0x00000700 */

+#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk

+#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */

+#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */

+#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */

+#define RTC_TAMPCR_TAMPTS_Pos          (7U)

+#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)        /*!< 0x00000080 */

+#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk

+#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)

+#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)      /*!< 0x00000040 */

+#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk

+#define RTC_TAMPCR_TAMP3E_Pos          (5U)

+#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)        /*!< 0x00000020 */

+#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk

+#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)

+#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)      /*!< 0x00000010 */

+#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk

+#define RTC_TAMPCR_TAMP2E_Pos          (3U)

+#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)        /*!< 0x00000008 */

+#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk

+#define RTC_TAMPCR_TAMPIE_Pos          (2U)

+#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)        /*!< 0x00000004 */

+#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk

+#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)

+#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)      /*!< 0x00000002 */

+#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk

+#define RTC_TAMPCR_TAMP1E_Pos          (0U)

+#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)        /*!< 0x00000001 */

+#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk

+

+/********************  Bits definition for RTC_ALRMASSR register  *************/

+#define RTC_ALRMASSR_MASKSS_Pos        (24U)

+#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x0F000000 */

+#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk

+#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */

+#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */

+#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */

+#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */

+#define RTC_ALRMASSR_SS_Pos            (0U)

+#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */

+#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk

+

+/********************  Bits definition for RTC_ALRMBSSR register  *************/

+#define RTC_ALRMBSSR_MASKSS_Pos        (24U)

+#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x0F000000 */

+#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk

+#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */

+#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */

+#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */

+#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */

+#define RTC_ALRMBSSR_SS_Pos            (0U)

+#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */

+#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk

+

+/********************  Bits definition for RTC_OR register  *******************/

+#define RTC_OR_OUT_RMP_Pos             (1U)

+#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)           /*!< 0x00000002 */

+#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk

+#define RTC_OR_ALARMOUTTYPE_Pos        (0U)

+#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)      /*!< 0x00000001 */

+#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk

+

+/********************  Bits definition for RTC_BKP0R register  ****************/

+#define RTC_BKP0R_Pos                  (0U)

+#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP0R                      RTC_BKP0R_Msk

+

+/********************  Bits definition for RTC_BKP1R register  ****************/

+#define RTC_BKP1R_Pos                  (0U)

+#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP1R                      RTC_BKP1R_Msk

+

+/********************  Bits definition for RTC_BKP2R register  ****************/

+#define RTC_BKP2R_Pos                  (0U)

+#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP2R                      RTC_BKP2R_Msk

+

+/********************  Bits definition for RTC_BKP3R register  ****************/

+#define RTC_BKP3R_Pos                  (0U)

+#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP3R                      RTC_BKP3R_Msk

+

+/********************  Bits definition for RTC_BKP4R register  ****************/

+#define RTC_BKP4R_Pos                  (0U)

+#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP4R                      RTC_BKP4R_Msk

+

+/********************  Bits definition for RTC_BKP5R register  ****************/

+#define RTC_BKP5R_Pos                  (0U)

+#define RTC_BKP5R_Msk                  (0xFFFFFFFFUL << RTC_BKP5R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP5R                      RTC_BKP5R_Msk

+

+/********************  Bits definition for RTC_BKP6R register  ****************/

+#define RTC_BKP6R_Pos                  (0U)

+#define RTC_BKP6R_Msk                  (0xFFFFFFFFUL << RTC_BKP6R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP6R                      RTC_BKP6R_Msk

+

+/********************  Bits definition for RTC_BKP7R register  ****************/

+#define RTC_BKP7R_Pos                  (0U)

+#define RTC_BKP7R_Msk                  (0xFFFFFFFFUL << RTC_BKP7R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP7R                      RTC_BKP7R_Msk

+

+/********************  Bits definition for RTC_BKP8R register  ****************/

+#define RTC_BKP8R_Pos                  (0U)

+#define RTC_BKP8R_Msk                  (0xFFFFFFFFUL << RTC_BKP8R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP8R                      RTC_BKP8R_Msk

+

+/********************  Bits definition for RTC_BKP9R register  ****************/

+#define RTC_BKP9R_Pos                  (0U)

+#define RTC_BKP9R_Msk                  (0xFFFFFFFFUL << RTC_BKP9R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP9R                      RTC_BKP9R_Msk

+

+/********************  Bits definition for RTC_BKP10R register  ***************/

+#define RTC_BKP10R_Pos                 (0U)

+#define RTC_BKP10R_Msk                 (0xFFFFFFFFUL << RTC_BKP10R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP10R                     RTC_BKP10R_Msk

+

+/********************  Bits definition for RTC_BKP11R register  ***************/

+#define RTC_BKP11R_Pos                 (0U)

+#define RTC_BKP11R_Msk                 (0xFFFFFFFFUL << RTC_BKP11R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP11R                     RTC_BKP11R_Msk

+

+/********************  Bits definition for RTC_BKP12R register  ***************/

+#define RTC_BKP12R_Pos                 (0U)

+#define RTC_BKP12R_Msk                 (0xFFFFFFFFUL << RTC_BKP12R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP12R                     RTC_BKP12R_Msk

+

+/********************  Bits definition for RTC_BKP13R register  ***************/

+#define RTC_BKP13R_Pos                 (0U)

+#define RTC_BKP13R_Msk                 (0xFFFFFFFFUL << RTC_BKP13R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP13R                     RTC_BKP13R_Msk

+

+/********************  Bits definition for RTC_BKP14R register  ***************/

+#define RTC_BKP14R_Pos                 (0U)

+#define RTC_BKP14R_Msk                 (0xFFFFFFFFUL << RTC_BKP14R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP14R                     RTC_BKP14R_Msk

+

+/********************  Bits definition for RTC_BKP15R register  ***************/

+#define RTC_BKP15R_Pos                 (0U)

+#define RTC_BKP15R_Msk                 (0xFFFFFFFFUL << RTC_BKP15R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP15R                     RTC_BKP15R_Msk

+

+/********************  Bits definition for RTC_BKP16R register  ***************/

+#define RTC_BKP16R_Pos                 (0U)

+#define RTC_BKP16R_Msk                 (0xFFFFFFFFUL << RTC_BKP16R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP16R                     RTC_BKP16R_Msk

+

+/********************  Bits definition for RTC_BKP17R register  ***************/

+#define RTC_BKP17R_Pos                 (0U)

+#define RTC_BKP17R_Msk                 (0xFFFFFFFFUL << RTC_BKP17R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP17R                     RTC_BKP17R_Msk

+

+/********************  Bits definition for RTC_BKP18R register  ***************/

+#define RTC_BKP18R_Pos                 (0U)

+#define RTC_BKP18R_Msk                 (0xFFFFFFFFUL << RTC_BKP18R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP18R                     RTC_BKP18R_Msk

+

+/********************  Bits definition for RTC_BKP19R register  ***************/

+#define RTC_BKP19R_Pos                 (0U)

+#define RTC_BKP19R_Msk                 (0xFFFFFFFFUL << RTC_BKP19R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP19R                     RTC_BKP19R_Msk

+

+/********************  Bits definition for RTC_BKP20R register  ***************/

+#define RTC_BKP20R_Pos                 (0U)

+#define RTC_BKP20R_Msk                 (0xFFFFFFFFUL << RTC_BKP20R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP20R                     RTC_BKP20R_Msk

+

+/********************  Bits definition for RTC_BKP21R register  ***************/

+#define RTC_BKP21R_Pos                 (0U)

+#define RTC_BKP21R_Msk                 (0xFFFFFFFFUL << RTC_BKP21R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP21R                     RTC_BKP21R_Msk

+

+/********************  Bits definition for RTC_BKP22R register  ***************/

+#define RTC_BKP22R_Pos                 (0U)

+#define RTC_BKP22R_Msk                 (0xFFFFFFFFUL << RTC_BKP22R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP22R                     RTC_BKP22R_Msk

+

+/********************  Bits definition for RTC_BKP23R register  ***************/

+#define RTC_BKP23R_Pos                 (0U)

+#define RTC_BKP23R_Msk                 (0xFFFFFFFFUL << RTC_BKP23R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP23R                     RTC_BKP23R_Msk

+

+/********************  Bits definition for RTC_BKP24R register  ***************/

+#define RTC_BKP24R_Pos                 (0U)

+#define RTC_BKP24R_Msk                 (0xFFFFFFFFUL << RTC_BKP24R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP24R                     RTC_BKP24R_Msk

+

+/********************  Bits definition for RTC_BKP25R register  ***************/

+#define RTC_BKP25R_Pos                 (0U)

+#define RTC_BKP25R_Msk                 (0xFFFFFFFFUL << RTC_BKP25R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP25R                     RTC_BKP25R_Msk

+

+/********************  Bits definition for RTC_BKP26R register  ***************/

+#define RTC_BKP26R_Pos                 (0U)

+#define RTC_BKP26R_Msk                 (0xFFFFFFFFUL << RTC_BKP26R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP26R                     RTC_BKP26R_Msk

+

+/********************  Bits definition for RTC_BKP27R register  ***************/

+#define RTC_BKP27R_Pos                 (0U)

+#define RTC_BKP27R_Msk                 (0xFFFFFFFFUL << RTC_BKP27R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP27R                     RTC_BKP27R_Msk

+

+/********************  Bits definition for RTC_BKP28R register  ***************/

+#define RTC_BKP28R_Pos                 (0U)

+#define RTC_BKP28R_Msk                 (0xFFFFFFFFUL << RTC_BKP28R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP28R                     RTC_BKP28R_Msk

+

+/********************  Bits definition for RTC_BKP29R register  ***************/

+#define RTC_BKP29R_Pos                 (0U)

+#define RTC_BKP29R_Msk                 (0xFFFFFFFFUL << RTC_BKP29R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP29R                     RTC_BKP29R_Msk

+

+/********************  Bits definition for RTC_BKP30R register  ***************/

+#define RTC_BKP30R_Pos                 (0U)

+#define RTC_BKP30R_Msk                 (0xFFFFFFFFUL << RTC_BKP30R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP30R                     RTC_BKP30R_Msk

+

+/********************  Bits definition for RTC_BKP31R register  ***************/

+#define RTC_BKP31R_Pos                 (0U)

+#define RTC_BKP31R_Msk                 (0xFFFFFFFFUL << RTC_BKP31R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP31R                     RTC_BKP31R_Msk

+

+/******************** Number of backup registers ******************************/

+#define RTC_BKP_NUMBER_Pos             (5U)

+#define RTC_BKP_NUMBER_Msk             (0x1UL << RTC_BKP_NUMBER_Pos)           /*!< 0x00000020 */

+#define RTC_BKP_NUMBER                 RTC_BKP_NUMBER_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                              SPDIF-RX Interface                            */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for SPDIF_CR register  ******************/

+#define SPDIFRX_CR_SPDIFEN_Pos      (0U)

+#define SPDIFRX_CR_SPDIFEN_Msk      (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)          /*!< 0x00000003 */

+#define SPDIFRX_CR_SPDIFEN          SPDIFRX_CR_SPDIFEN_Msk                     /*!<Peripheral Block Enable                      */

+#define SPDIFRX_CR_RXDMAEN_Pos      (2U)

+#define SPDIFRX_CR_RXDMAEN_Msk      (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)          /*!< 0x00000004 */

+#define SPDIFRX_CR_RXDMAEN          SPDIFRX_CR_RXDMAEN_Msk                     /*!<Receiver DMA Enable for data flow            */

+#define SPDIFRX_CR_RXSTEO_Pos       (3U)

+#define SPDIFRX_CR_RXSTEO_Msk       (0x1UL << SPDIFRX_CR_RXSTEO_Pos)           /*!< 0x00000008 */

+#define SPDIFRX_CR_RXSTEO           SPDIFRX_CR_RXSTEO_Msk                      /*!<Stereo Mode                                  */

+#define SPDIFRX_CR_DRFMT_Pos        (4U)

+#define SPDIFRX_CR_DRFMT_Msk        (0x3UL << SPDIFRX_CR_DRFMT_Pos)            /*!< 0x00000030 */

+#define SPDIFRX_CR_DRFMT            SPDIFRX_CR_DRFMT_Msk                       /*!<RX Data format                               */

+#define SPDIFRX_CR_PMSK_Pos         (6U)

+#define SPDIFRX_CR_PMSK_Msk         (0x1UL << SPDIFRX_CR_PMSK_Pos)             /*!< 0x00000040 */

+#define SPDIFRX_CR_PMSK             SPDIFRX_CR_PMSK_Msk                        /*!<Mask Parity error bit                        */

+#define SPDIFRX_CR_VMSK_Pos         (7U)

+#define SPDIFRX_CR_VMSK_Msk         (0x1UL << SPDIFRX_CR_VMSK_Pos)             /*!< 0x00000080 */

+#define SPDIFRX_CR_VMSK             SPDIFRX_CR_VMSK_Msk                        /*!<Mask of Validity bit                         */

+#define SPDIFRX_CR_CUMSK_Pos        (8U)

+#define SPDIFRX_CR_CUMSK_Msk        (0x1UL << SPDIFRX_CR_CUMSK_Pos)            /*!< 0x00000100 */

+#define SPDIFRX_CR_CUMSK            SPDIFRX_CR_CUMSK_Msk                       /*!<Mask of channel status and user bits         */

+#define SPDIFRX_CR_PTMSK_Pos        (9U)

+#define SPDIFRX_CR_PTMSK_Msk        (0x1UL << SPDIFRX_CR_PTMSK_Pos)            /*!< 0x00000200 */

+#define SPDIFRX_CR_PTMSK            SPDIFRX_CR_PTMSK_Msk                       /*!<Mask of Preamble Type bits                   */

+#define SPDIFRX_CR_CBDMAEN_Pos      (10U)

+#define SPDIFRX_CR_CBDMAEN_Msk      (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)          /*!< 0x00000400 */

+#define SPDIFRX_CR_CBDMAEN          SPDIFRX_CR_CBDMAEN_Msk                     /*!<Control Buffer DMA ENable for control flow   */

+#define SPDIFRX_CR_CHSEL_Pos        (11U)

+#define SPDIFRX_CR_CHSEL_Msk        (0x1UL << SPDIFRX_CR_CHSEL_Pos)            /*!< 0x00000800 */

+#define SPDIFRX_CR_CHSEL            SPDIFRX_CR_CHSEL_Msk                       /*!<Channel Selection                            */

+#define SPDIFRX_CR_NBTR_Pos         (12U)

+#define SPDIFRX_CR_NBTR_Msk         (0x3UL << SPDIFRX_CR_NBTR_Pos)             /*!< 0x00003000 */

+#define SPDIFRX_CR_NBTR             SPDIFRX_CR_NBTR_Msk                        /*!<Maximum allowed re-tries during synchronization phase */

+#define SPDIFRX_CR_WFA_Pos          (14U)

+#define SPDIFRX_CR_WFA_Msk          (0x1UL << SPDIFRX_CR_WFA_Pos)              /*!< 0x00004000 */

+#define SPDIFRX_CR_WFA              SPDIFRX_CR_WFA_Msk                         /*!<Wait For Activity     */

+#define SPDIFRX_CR_INSEL_Pos        (16U)

+#define SPDIFRX_CR_INSEL_Msk        (0x7UL << SPDIFRX_CR_INSEL_Pos)            /*!< 0x00070000 */

+#define SPDIFRX_CR_INSEL            SPDIFRX_CR_INSEL_Msk                       /*!<SPDIF input selection */

+#define SPDIFRX_CR_CKSEN_Pos        (20U)

+#define SPDIFRX_CR_CKSEN_Msk        (0x1UL << SPDIFRX_CR_CKSEN_Pos)            /*!< 0x00100000 */

+#define SPDIFRX_CR_CKSEN            SPDIFRX_CR_CKSEN_Msk                       /*!<Symbol Clock Enable */

+#define SPDIFRX_CR_CKSBKPEN_Pos     (21U)

+#define SPDIFRX_CR_CKSBKPEN_Msk     (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)         /*!< 0x00200000 */

+#define SPDIFRX_CR_CKSBKPEN         SPDIFRX_CR_CKSBKPEN_Msk                    /*!<Backup Symbol Clock Enable */

+

+/*******************  Bit definition for SPDIFRX_IMR register  *******************/

+#define SPDIFRX_IMR_RXNEIE_Pos      (0U)

+#define SPDIFRX_IMR_RXNEIE_Msk      (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)          /*!< 0x00000001 */

+#define SPDIFRX_IMR_RXNEIE          SPDIFRX_IMR_RXNEIE_Msk                     /*!<RXNE interrupt enable                              */

+#define SPDIFRX_IMR_CSRNEIE_Pos     (1U)

+#define SPDIFRX_IMR_CSRNEIE_Msk     (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)         /*!< 0x00000002 */

+#define SPDIFRX_IMR_CSRNEIE         SPDIFRX_IMR_CSRNEIE_Msk                    /*!<Control Buffer Ready Interrupt Enable              */

+#define SPDIFRX_IMR_PERRIE_Pos      (2U)

+#define SPDIFRX_IMR_PERRIE_Msk      (0x1UL << SPDIFRX_IMR_PERRIE_Pos)          /*!< 0x00000004 */

+#define SPDIFRX_IMR_PERRIE          SPDIFRX_IMR_PERRIE_Msk                     /*!<Parity error interrupt enable                      */

+#define SPDIFRX_IMR_OVRIE_Pos       (3U)

+#define SPDIFRX_IMR_OVRIE_Msk       (0x1UL << SPDIFRX_IMR_OVRIE_Pos)           /*!< 0x00000008 */

+#define SPDIFRX_IMR_OVRIE           SPDIFRX_IMR_OVRIE_Msk                      /*!<Overrun error Interrupt Enable                     */

+#define SPDIFRX_IMR_SBLKIE_Pos      (4U)

+#define SPDIFRX_IMR_SBLKIE_Msk      (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)          /*!< 0x00000010 */

+#define SPDIFRX_IMR_SBLKIE          SPDIFRX_IMR_SBLKIE_Msk                     /*!<Synchronization Block Detected Interrupt Enable    */

+#define SPDIFRX_IMR_SYNCDIE_Pos     (5U)

+#define SPDIFRX_IMR_SYNCDIE_Msk     (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)         /*!< 0x00000020 */

+#define SPDIFRX_IMR_SYNCDIE         SPDIFRX_IMR_SYNCDIE_Msk                    /*!<Synchronization Done                               */

+#define SPDIFRX_IMR_IFEIE_Pos       (6U)

+#define SPDIFRX_IMR_IFEIE_Msk       (0x1UL << SPDIFRX_IMR_IFEIE_Pos)           /*!< 0x00000040 */

+#define SPDIFRX_IMR_IFEIE           SPDIFRX_IMR_IFEIE_Msk                      /*!<Serial Interface Error Interrupt Enable            */

+

+/*******************  Bit definition for SPDIFRX_SR register  *******************/

+#define SPDIFRX_SR_RXNE_Pos         (0U)

+#define SPDIFRX_SR_RXNE_Msk         (0x1UL << SPDIFRX_SR_RXNE_Pos)             /*!< 0x00000001 */

+#define SPDIFRX_SR_RXNE             SPDIFRX_SR_RXNE_Msk                        /*!<Read data register not empty                          */

+#define SPDIFRX_SR_CSRNE_Pos        (1U)

+#define SPDIFRX_SR_CSRNE_Msk        (0x1UL << SPDIFRX_SR_CSRNE_Pos)            /*!< 0x00000002 */

+#define SPDIFRX_SR_CSRNE            SPDIFRX_SR_CSRNE_Msk                       /*!<The Control Buffer register is not empty              */

+#define SPDIFRX_SR_PERR_Pos         (2U)

+#define SPDIFRX_SR_PERR_Msk         (0x1UL << SPDIFRX_SR_PERR_Pos)             /*!< 0x00000004 */

+#define SPDIFRX_SR_PERR             SPDIFRX_SR_PERR_Msk                        /*!<Parity error                                          */

+#define SPDIFRX_SR_OVR_Pos          (3U)

+#define SPDIFRX_SR_OVR_Msk          (0x1UL << SPDIFRX_SR_OVR_Pos)              /*!< 0x00000008 */

+#define SPDIFRX_SR_OVR              SPDIFRX_SR_OVR_Msk                         /*!<Overrun error                                         */

+#define SPDIFRX_SR_SBD_Pos          (4U)

+#define SPDIFRX_SR_SBD_Msk          (0x1UL << SPDIFRX_SR_SBD_Pos)              /*!< 0x00000010 */

+#define SPDIFRX_SR_SBD              SPDIFRX_SR_SBD_Msk                         /*!<Synchronization Block Detected                        */

+#define SPDIFRX_SR_SYNCD_Pos        (5U)

+#define SPDIFRX_SR_SYNCD_Msk        (0x1UL << SPDIFRX_SR_SYNCD_Pos)            /*!< 0x00000020 */

+#define SPDIFRX_SR_SYNCD            SPDIFRX_SR_SYNCD_Msk                       /*!<Synchronization Done                                  */

+#define SPDIFRX_SR_FERR_Pos         (6U)

+#define SPDIFRX_SR_FERR_Msk         (0x1UL << SPDIFRX_SR_FERR_Pos)             /*!< 0x00000040 */

+#define SPDIFRX_SR_FERR             SPDIFRX_SR_FERR_Msk                        /*!<Framing error                                         */

+#define SPDIFRX_SR_SERR_Pos         (7U)

+#define SPDIFRX_SR_SERR_Msk         (0x1UL << SPDIFRX_SR_SERR_Pos)             /*!< 0x00000080 */

+#define SPDIFRX_SR_SERR             SPDIFRX_SR_SERR_Msk                        /*!<Synchronization error                                 */

+#define SPDIFRX_SR_TERR_Pos         (8U)

+#define SPDIFRX_SR_TERR_Msk         (0x1UL << SPDIFRX_SR_TERR_Pos)             /*!< 0x00000100 */

+#define SPDIFRX_SR_TERR             SPDIFRX_SR_TERR_Msk                        /*!<Time-out error                                        */

+#define SPDIFRX_SR_WIDTH5_Pos       (16U)

+#define SPDIFRX_SR_WIDTH5_Msk       (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)        /*!< 0x7FFF0000 */

+#define SPDIFRX_SR_WIDTH5           SPDIFRX_SR_WIDTH5_Msk                      /*!<Duration of 5 symbols counted with spdif_clk          */

+

+/*******************  Bit definition for SPDIFRX_IFCR register  *******************/

+#define SPDIFRX_IFCR_PERRCF_Pos     (2U)

+#define SPDIFRX_IFCR_PERRCF_Msk     (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)         /*!< 0x00000004 */

+#define SPDIFRX_IFCR_PERRCF         SPDIFRX_IFCR_PERRCF_Msk                    /*!<Clears the Parity error flag                         */

+#define SPDIFRX_IFCR_OVRCF_Pos      (3U)

+#define SPDIFRX_IFCR_OVRCF_Msk      (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)          /*!< 0x00000008 */

+#define SPDIFRX_IFCR_OVRCF          SPDIFRX_IFCR_OVRCF_Msk                     /*!<Clears the Overrun error flag                        */

+#define SPDIFRX_IFCR_SBDCF_Pos      (4U)

+#define SPDIFRX_IFCR_SBDCF_Msk      (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)          /*!< 0x00000010 */

+#define SPDIFRX_IFCR_SBDCF          SPDIFRX_IFCR_SBDCF_Msk                     /*!<Clears the Synchronization Block Detected flag       */

+#define SPDIFRX_IFCR_SYNCDCF_Pos    (5U)

+#define SPDIFRX_IFCR_SYNCDCF_Msk    (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)        /*!< 0x00000020 */

+#define SPDIFRX_IFCR_SYNCDCF        SPDIFRX_IFCR_SYNCDCF_Msk                   /*!<Clears the Synchronization Done flag                 */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/

+#define SPDIFRX_DR0_DR_Pos          (0U)

+#define SPDIFRX_DR0_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)         /*!< 0x00FFFFFF */

+#define SPDIFRX_DR0_DR              SPDIFRX_DR0_DR_Msk                         /*!<Data value            */

+#define SPDIFRX_DR0_PE_Pos          (24U)

+#define SPDIFRX_DR0_PE_Msk          (0x1UL << SPDIFRX_DR0_PE_Pos)              /*!< 0x01000000 */

+#define SPDIFRX_DR0_PE              SPDIFRX_DR0_PE_Msk                         /*!<Parity Error bit      */

+#define SPDIFRX_DR0_V_Pos           (25U)

+#define SPDIFRX_DR0_V_Msk           (0x1UL << SPDIFRX_DR0_V_Pos)               /*!< 0x02000000 */

+#define SPDIFRX_DR0_V               SPDIFRX_DR0_V_Msk                          /*!<Validity bit          */

+#define SPDIFRX_DR0_U_Pos           (26U)

+#define SPDIFRX_DR0_U_Msk           (0x1UL << SPDIFRX_DR0_U_Pos)               /*!< 0x04000000 */

+#define SPDIFRX_DR0_U               SPDIFRX_DR0_U_Msk                          /*!<User bit              */

+#define SPDIFRX_DR0_C_Pos           (27U)

+#define SPDIFRX_DR0_C_Msk           (0x1UL << SPDIFRX_DR0_C_Pos)               /*!< 0x08000000 */

+#define SPDIFRX_DR0_C               SPDIFRX_DR0_C_Msk                          /*!<Channel Status bit    */

+#define SPDIFRX_DR0_PT_Pos          (28U)

+#define SPDIFRX_DR0_PT_Msk          (0x3UL << SPDIFRX_DR0_PT_Pos)              /*!< 0x30000000 */

+#define SPDIFRX_DR0_PT              SPDIFRX_DR0_PT_Msk                         /*!<Preamble Type         */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/

+#define SPDIFRX_DR1_DR_Pos          (8U)

+#define SPDIFRX_DR1_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)         /*!< 0xFFFFFF00 */

+#define SPDIFRX_DR1_DR              SPDIFRX_DR1_DR_Msk                         /*!<Data value            */

+#define SPDIFRX_DR1_PT_Pos          (4U)

+#define SPDIFRX_DR1_PT_Msk          (0x3UL << SPDIFRX_DR1_PT_Pos)              /*!< 0x00000030 */

+#define SPDIFRX_DR1_PT              SPDIFRX_DR1_PT_Msk                         /*!<Preamble Type         */

+#define SPDIFRX_DR1_C_Pos           (3U)

+#define SPDIFRX_DR1_C_Msk           (0x1UL << SPDIFRX_DR1_C_Pos)               /*!< 0x00000008 */

+#define SPDIFRX_DR1_C               SPDIFRX_DR1_C_Msk                          /*!<Channel Status bit    */

+#define SPDIFRX_DR1_U_Pos           (2U)

+#define SPDIFRX_DR1_U_Msk           (0x1UL << SPDIFRX_DR1_U_Pos)               /*!< 0x00000004 */

+#define SPDIFRX_DR1_U               SPDIFRX_DR1_U_Msk                          /*!<User bit              */

+#define SPDIFRX_DR1_V_Pos           (1U)

+#define SPDIFRX_DR1_V_Msk           (0x1UL << SPDIFRX_DR1_V_Pos)               /*!< 0x00000002 */

+#define SPDIFRX_DR1_V               SPDIFRX_DR1_V_Msk                          /*!<Validity bit          */

+#define SPDIFRX_DR1_PE_Pos          (0U)

+#define SPDIFRX_DR1_PE_Msk          (0x1UL << SPDIFRX_DR1_PE_Pos)              /*!< 0x00000001 */

+#define SPDIFRX_DR1_PE              SPDIFRX_DR1_PE_Msk                         /*!<Parity Error bit      */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/

+#define SPDIFRX_DR1_DRNL1_Pos       (16U)

+#define SPDIFRX_DR1_DRNL1_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)        /*!< 0xFFFF0000 */

+#define SPDIFRX_DR1_DRNL1           SPDIFRX_DR1_DRNL1_Msk                      /*!<Data value Channel B      */

+#define SPDIFRX_DR1_DRNL2_Pos       (0U)

+#define SPDIFRX_DR1_DRNL2_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)        /*!< 0x0000FFFF */

+#define SPDIFRX_DR1_DRNL2           SPDIFRX_DR1_DRNL2_Msk                      /*!<Data value Channel A      */

+

+/*******************  Bit definition for SPDIFRX_CSR register   *******************/

+#define SPDIFRX_CSR_USR_Pos         (0U)

+#define SPDIFRX_CSR_USR_Msk         (0xFFFFUL << SPDIFRX_CSR_USR_Pos)          /*!< 0x0000FFFF */

+#define SPDIFRX_CSR_USR             SPDIFRX_CSR_USR_Msk                        /*!<User data information           */

+#define SPDIFRX_CSR_CS_Pos          (16U)

+#define SPDIFRX_CSR_CS_Msk          (0xFFUL << SPDIFRX_CSR_CS_Pos)             /*!< 0x00FF0000 */

+#define SPDIFRX_CSR_CS              SPDIFRX_CSR_CS_Msk                         /*!<Channel A status information    */

+#define SPDIFRX_CSR_SOB_Pos         (24U)

+#define SPDIFRX_CSR_SOB_Msk         (0x1UL << SPDIFRX_CSR_SOB_Pos)             /*!< 0x01000000 */

+#define SPDIFRX_CSR_SOB             SPDIFRX_CSR_SOB_Msk                        /*!<Start Of Block                  */

+

+/*******************  Bit definition for SPDIFRX_DIR register    *******************/

+#define SPDIFRX_DIR_THI_Pos         (0U)

+#define SPDIFRX_DIR_THI_Msk         (0x1FFFUL << SPDIFRX_DIR_THI_Pos)          /*!< 0x00001FFF */

+#define SPDIFRX_DIR_THI             SPDIFRX_DIR_THI_Msk                        /*!<Threshold LOW      */

+#define SPDIFRX_DIR_TLO_Pos         (16U)

+#define SPDIFRX_DIR_TLO_Msk         (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)          /*!< 0x1FFF0000 */

+#define SPDIFRX_DIR_TLO             SPDIFRX_DIR_TLO_Msk                        /*!<Threshold HIGH     */

+

+/*******************  Bit definition for SPDIFRX_VERR register    *******************/

+#define SPDIFRX_VERR_MINREV_Pos     (0U)

+#define SPDIFRX_VERR_MINREV_Msk     (0xFUL << SPDIFRX_VERR_MINREV_Pos)         /*!< 0x0000000F */

+#define SPDIFRX_VERR_MINREV         SPDIFRX_VERR_MINREV_Msk                    /*!<SPDIFRX Minor revision     */

+#define SPDIFRX_VERR_MAJREV_Pos     (4U)

+#define SPDIFRX_VERR_MAJREV_Msk     (0xFUL << SPDIFRX_VERR_MAJREV_Pos)         /*!< 0x000000F0 */

+#define SPDIFRX_VERR_MAJREV         SPDIFRX_VERR_MAJREV_Msk                    /*!<SPDIFRX Major revision     */

+

+/*******************  Bit definition for SPDIFRX_IDR register    *******************/

+#define SPDIFRX_IDR_ID_Pos          (0U)

+#define SPDIFRX_IDR_ID_Msk          (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos)       /*!< 0xFFFFFFFF */

+#define SPDIFRX_IDR_ID              SPDIFRX_IDR_ID_Msk                         /*!<SPDIFRX identifier     */

+

+/*******************  Bit definition for SPDIFRX_SIDR register    *******************/

+#define SPDIFRX_SIDR_SID_Pos        (0U)

+#define SPDIFRX_SIDR_SID_Msk        (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos)     /*!< 0xFFFFFFFF */

+#define SPDIFRX_SIDR_SID            SPDIFRX_SIDR_SID_Msk                       /*!<Size of the memory region allocated to SPDIFRX registers */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          Serial Audio Interface                            */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  SAI VERSION  ********************************/

+#define SAI_VER_V2_X

+

+/********************  Bit definition for SAI_GCR register  *******************/

+#define SAI_GCR_SYNCIN_Pos         (0U)

+#define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000003 */

+#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */

+#define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */

+#define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */

+

+#define SAI_GCR_SYNCOUT_Pos        (4U)

+#define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000030 */

+#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */

+#define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */

+#define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */

+

+/*******************  Bit definition for SAI_xCR1 register  *******************/

+#define SAI_xCR1_MODE_Pos          (0U)

+#define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */

+#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */

+#define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */

+#define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */

+

+#define SAI_xCR1_PRTCFG_Pos        (2U)

+#define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */

+#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */

+#define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */

+#define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */

+

+#define SAI_xCR1_DS_Pos            (5U)

+#define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */

+#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */

+#define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */

+#define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */

+#define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */

+

+#define SAI_xCR1_LSBFIRST_Pos      (8U)

+#define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */

+#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */

+#define SAI_xCR1_CKSTR_Pos         (9U)

+#define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */

+#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */

+

+#define SAI_xCR1_SYNCEN_Pos        (10U)

+#define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */

+#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */

+#define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */

+#define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */

+

+#define SAI_xCR1_MONO_Pos          (12U)

+#define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */

+#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */

+#define SAI_xCR1_OUTDRIV_Pos       (13U)

+#define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */

+#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */

+#define SAI_xCR1_SAIEN_Pos         (16U)

+#define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */

+#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */

+#define SAI_xCR1_DMAEN_Pos         (17U)

+#define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */

+#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */

+#define SAI_xCR1_NODIV_Pos         (19U)

+#define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */

+#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */

+

+#define SAI_xCR1_MCKDIV_Pos        (20U)

+#define SAI_xCR1_MCKDIV_Msk        (0x3FUL << SAI_xCR1_MCKDIV_Pos)             /*!< 0x03F00000 */

+#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[5:0] (Master ClocK Divider)  */

+#define SAI_xCR1_MCKDIV_0          (0x01UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00100000 */

+#define SAI_xCR1_MCKDIV_1          (0x02UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00200000 */

+#define SAI_xCR1_MCKDIV_2          (0x04UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00400000 */

+#define SAI_xCR1_MCKDIV_3          (0x08UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00800000 */

+#define SAI_xCR1_MCKDIV_4          (0x10UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x01000000 */

+#define SAI_xCR1_MCKDIV_5          (0x20UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x02000000 */

+

+#define SAI_xCR1_MCKEN_Pos         (27U)

+#define SAI_xCR1_MCKEN_Msk         (0x1UL << SAI_xCR1_MCKEN_Pos)               /*!< 0x08000000 */

+#define SAI_xCR1_MCKEN             SAI_xCR1_MCKEN_Msk                          /*!<Master ClocK enable */

+

+#define SAI_xCR1_OSR_Pos           (26U)

+#define SAI_xCR1_OSR_Msk           (0x1UL << SAI_xCR1_OSR_Pos)                 /*!< 0x04000000 */

+#define SAI_xCR1_OSR               SAI_xCR1_OSR_Msk                            /*!<OverSampling Ratio for master clock  */

+

+/* Legacy define */

+#define  SAI_xCR1_NOMCK               SAI_xCR1_NODIV

+

+/*******************  Bit definition for SAI_xCR2 register  *******************/

+#define SAI_xCR2_FTH_Pos           (0U)

+#define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */

+#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */

+#define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */

+#define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */

+#define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */

+

+#define SAI_xCR2_FFLUSH_Pos        (3U)

+#define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */

+#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */

+#define SAI_xCR2_TRIS_Pos          (4U)

+#define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */

+#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */

+#define SAI_xCR2_MUTE_Pos          (5U)

+#define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */

+#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */

+#define SAI_xCR2_MUTEVAL_Pos       (6U)

+#define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */

+#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */

+

+#define SAI_xCR2_MUTECNT_Pos       (7U)

+#define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */

+#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */

+#define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */

+#define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */

+#define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */

+#define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */

+#define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */

+#define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */

+

+#define SAI_xCR2_CPL_Pos           (13U)

+#define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */

+#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */

+

+#define SAI_xCR2_COMP_Pos          (14U)

+#define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */

+#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */

+#define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */

+#define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */

+

+/******************  Bit definition for SAI_xFRCR register  *******************/

+#define SAI_xFRCR_FRL_Pos          (0U)

+#define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */

+#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](FRame Length)  */

+#define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */

+#define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */

+#define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */

+#define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */

+#define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */

+#define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */

+#define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */

+#define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */

+

+#define SAI_xFRCR_FSALL_Pos        (8U)

+#define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */

+#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FSALL[6:0] (Frame Synchronization Active Level Length)  */

+#define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */

+#define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */

+#define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */

+#define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */

+#define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */

+#define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */

+#define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */

+

+#define SAI_xFRCR_FSDEF_Pos        (16U)

+#define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */

+#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!<Frame Synchronization Definition  */

+#define SAI_xFRCR_FSPOL_Pos        (17U)

+#define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */

+#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */

+#define SAI_xFRCR_FSOFF_Pos        (18U)

+#define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */

+#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */

+

+/* Legacy define */

+#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL

+

+/******************  Bit definition for SAI_xSLOTR register  *******************/

+#define SAI_xSLOTR_FBOFF_Pos       (0U)

+#define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */

+#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FBOFF[4:0](First Bit Offset)  */

+#define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */

+#define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */

+#define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */

+#define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */

+#define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */

+

+#define SAI_xSLOTR_SLOTSZ_Pos      (6U)

+#define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */

+#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */

+#define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */

+#define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */

+

+#define SAI_xSLOTR_NBSLOT_Pos      (8U)

+#define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */

+#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */

+#define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */

+#define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */

+#define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */

+#define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */

+

+#define SAI_xSLOTR_SLOTEN_Pos      (16U)

+#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */

+#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */

+

+/*******************  Bit definition for SAI_xIMR register  *******************/

+#define SAI_xIMR_OVRUDRIE_Pos      (0U)

+#define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */

+#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */

+#define SAI_xIMR_MUTEDETIE_Pos     (1U)

+#define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */

+#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */

+#define SAI_xIMR_WCKCFGIE_Pos      (2U)

+#define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */

+#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */

+#define SAI_xIMR_FREQIE_Pos        (3U)

+#define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */

+#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */

+#define SAI_xIMR_CNRDYIE_Pos       (4U)

+#define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */

+#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */

+#define SAI_xIMR_AFSDETIE_Pos      (5U)

+#define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */

+#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */

+#define SAI_xIMR_LFSDETIE_Pos      (6U)

+#define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */

+#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */

+

+/********************  Bit definition for SAI_xSR register  *******************/

+#define SAI_xSR_OVRUDR_Pos         (0U)

+#define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */

+#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */

+#define SAI_xSR_MUTEDET_Pos        (1U)

+#define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */

+#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */

+#define SAI_xSR_WCKCFG_Pos         (2U)

+#define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */

+#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */

+#define SAI_xSR_FREQ_Pos           (3U)

+#define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */

+#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */

+#define SAI_xSR_CNRDY_Pos          (4U)

+#define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */

+#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */

+#define SAI_xSR_AFSDET_Pos         (5U)

+#define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */

+#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */

+#define SAI_xSR_LFSDET_Pos         (6U)

+#define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */

+#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */

+

+#define SAI_xSR_FLVL_Pos           (16U)

+#define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */

+#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */

+#define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */

+#define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */

+#define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */

+

+/******************  Bit definition for SAI_xCLRFR register  ******************/

+#define SAI_xCLRFR_COVRUDR_Pos     (0U)

+#define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */

+#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */

+#define SAI_xCLRFR_CMUTEDET_Pos    (1U)

+#define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */

+#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */

+#define SAI_xCLRFR_CWCKCFG_Pos     (2U)

+#define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */

+#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */

+#define SAI_xCLRFR_CFREQ_Pos       (3U)

+#define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */

+#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */

+#define SAI_xCLRFR_CCNRDY_Pos      (4U)

+#define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */

+#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */

+#define SAI_xCLRFR_CAFSDET_Pos     (5U)

+#define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */

+#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */

+#define SAI_xCLRFR_CLFSDET_Pos     (6U)

+#define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */

+#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */

+

+/******************  Bit definition for SAI_xDR register  *********************/

+#define SAI_xDR_DATA_Pos           (0U)

+#define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */

+#define SAI_xDR_DATA               SAI_xDR_DATA_Msk

+

+/*******************  Bit definition for SAI_PDMCR register  ******************/

+#define SAI_PDMCR_PDMEN_Pos        (0U)

+#define SAI_PDMCR_PDMEN_Msk        (0x1UL << SAI_PDMCR_PDMEN_Pos)              /*!< 0x00000001 */

+#define SAI_PDMCR_PDMEN            SAI_PDMCR_PDMEN_Msk                         /*!<PDM Enable                                          */

+

+#define SAI_PDMCR_MICNBR_Pos       (4U)

+#define SAI_PDMCR_MICNBR_Msk       (0x3UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000030 */

+#define SAI_PDMCR_MICNBR           SAI_PDMCR_MICNBR_Msk                        /*!<Number of microphones                               */

+#define SAI_PDMCR_MICNBR_0         (0x1UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000010 */

+#define SAI_PDMCR_MICNBR_1         (0x2UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000020 */

+

+#define SAI_PDMCR_CKEN1_Pos        (8U)

+#define SAI_PDMCR_CKEN1_Msk        (0x1UL << SAI_PDMCR_CKEN1_Pos)              /*!< 0x00000100 */

+#define SAI_PDMCR_CKEN1            SAI_PDMCR_CKEN1_Msk                         /*!<Clock enable of bitstream clock number 1            */

+#define SAI_PDMCR_CKEN2_Pos        (9U)

+#define SAI_PDMCR_CKEN2_Msk        (0x1UL << SAI_PDMCR_CKEN2_Pos)              /*!< 0x00000200 */

+#define SAI_PDMCR_CKEN2            SAI_PDMCR_CKEN2_Msk                         /*!<Clock enable of bitstream clock number 2            */

+#define SAI_PDMCR_CKEN3_Pos        (10U)

+#define SAI_PDMCR_CKEN3_Msk        (0x1UL << SAI_PDMCR_CKEN3_Pos)              /*!< 0x00000400 */

+#define SAI_PDMCR_CKEN3            SAI_PDMCR_CKEN3_Msk                         /*!<Clock enable of bitstream clock number 3            */

+#define SAI_PDMCR_CKEN4_Pos        (11U)

+#define SAI_PDMCR_CKEN4_Msk        (0x1UL << SAI_PDMCR_CKEN4_Pos)              /*!< 0x00000800 */

+#define SAI_PDMCR_CKEN4            SAI_PDMCR_CKEN4_Msk                         /*!<Clock enable of bitstream clock number 4            */

+

+/******************  Bit definition for SAI_PDMDLY register  ******************/

+#define SAI_PDMDLY_DLYM1L_Pos      (0U)

+#define SAI_PDMDLY_DLYM1L_Msk      (0x7UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000007 */

+#define SAI_PDMDLY_DLYM1L          SAI_PDMDLY_DLYM1L_Msk                       /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */

+#define SAI_PDMDLY_DLYM1L_0        (0x1UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000001 */

+#define SAI_PDMDLY_DLYM1L_1        (0x2UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000002 */

+#define SAI_PDMDLY_DLYM1L_2        (0x4UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000004 */

+

+#define SAI_PDMDLY_DLYM1R_Pos      (4U)

+#define SAI_PDMDLY_DLYM1R_Msk      (0x7UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000070 */

+#define SAI_PDMDLY_DLYM1R          SAI_PDMDLY_DLYM1R_Msk                       /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */

+#define SAI_PDMDLY_DLYM1R_0        (0x1UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000010 */

+#define SAI_PDMDLY_DLYM1R_1        (0x2UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000020 */

+#define SAI_PDMDLY_DLYM1R_2        (0x4UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000040 */

+

+#define SAI_PDMDLY_DLYM2L_Pos      (8U)

+#define SAI_PDMDLY_DLYM2L_Msk      (0x7UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000700 */

+#define SAI_PDMDLY_DLYM2L          SAI_PDMDLY_DLYM2L_Msk                       /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */

+#define SAI_PDMDLY_DLYM2L_0        (0x1UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000100 */

+#define SAI_PDMDLY_DLYM2L_1        (0x2UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000200 */

+#define SAI_PDMDLY_DLYM2L_2        (0x4UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000400 */

+

+#define SAI_PDMDLY_DLYM2R_Pos      (12U)

+#define SAI_PDMDLY_DLYM2R_Msk      (0x7UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00007000 */

+#define SAI_PDMDLY_DLYM2R          SAI_PDMDLY_DLYM2R_Msk                       /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/

+#define SAI_PDMDLY_DLYM2R_0        (0x1UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00001000 */

+#define SAI_PDMDLY_DLYM2R_1        (0x2UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00002000 */

+#define SAI_PDMDLY_DLYM2R_2        (0x4UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00004000 */

+

+#define SAI_PDMDLY_DLYM3L_Pos      (16U)

+#define SAI_PDMDLY_DLYM3L_Msk      (0x7UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00070000 */

+#define SAI_PDMDLY_DLYM3L          SAI_PDMDLY_DLYM3L_Msk                       /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/

+#define SAI_PDMDLY_DLYM3L_0        (0x1UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00010000 */

+#define SAI_PDMDLY_DLYM3L_1        (0x2UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00020000 */

+#define SAI_PDMDLY_DLYM3L_2        (0x4UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00040000 */

+

+#define SAI_PDMDLY_DLYM3R_Pos      (20U)

+#define SAI_PDMDLY_DLYM3R_Msk      (0x7UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00700000 */

+#define SAI_PDMDLY_DLYM3R          SAI_PDMDLY_DLYM3R_Msk                       /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/

+#define SAI_PDMDLY_DLYM3R_0        (0x1UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00100000 */

+#define SAI_PDMDLY_DLYM3R_1        (0x2UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00200000 */

+#define SAI_PDMDLY_DLYM3R_2        (0x4UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00400000 */

+

+#define SAI_PDMDLY_DLYM4L_Pos      (24U)

+#define SAI_PDMDLY_DLYM4L_Msk      (0x7UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x07000000 */

+#define SAI_PDMDLY_DLYM4L          SAI_PDMDLY_DLYM4L_Msk                       /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/

+#define SAI_PDMDLY_DLYM4L_0        (0x1UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x01000000 */

+#define SAI_PDMDLY_DLYM4L_1        (0x2UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x02000000 */

+#define SAI_PDMDLY_DLYM4L_2        (0x4UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x04000000 */

+

+#define SAI_PDMDLY_DLYM4R_Pos      (28U)

+#define SAI_PDMDLY_DLYM4R_Msk      (0x7UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x70000000 */

+#define SAI_PDMDLY_DLYM4R          SAI_PDMDLY_DLYM4R_Msk                       /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/

+#define SAI_PDMDLY_DLYM4R_0        (0x1UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x10000000 */

+#define SAI_PDMDLY_DLYM4R_1        (0x2UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x20000000 */

+#define SAI_PDMDLY_DLYM4R_2        (0x4UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x40000000 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           SDMMC Interface                                  */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for SDMMC_POWER register  ******************/

+#define SDMMC_POWER_PWRCTRL_Pos          (0U)

+#define SDMMC_POWER_PWRCTRL_Msk          (0x3UL << SDMMC_POWER_PWRCTRL_Pos)    /*!< 0x00000003 */

+#define SDMMC_POWER_PWRCTRL              SDMMC_POWER_PWRCTRL_Msk               /*!<PWRCTRL[1:0] bits (Power supply control bits) */

+#define SDMMC_POWER_PWRCTRL_0            (0x1UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000001 */

+#define SDMMC_POWER_PWRCTRL_1            (0x2UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000002 */

+#define SDMMC_POWER_VSWITCH_Pos          (2U)

+#define SDMMC_POWER_VSWITCH_Msk          (0x1UL << SDMMC_POWER_VSWITCH_Pos)    /*!< 0x00000004 */

+#define SDMMC_POWER_VSWITCH              SDMMC_POWER_VSWITCH_Msk               /*!<Voltage switch sequence start */

+#define SDMMC_POWER_VSWITCHEN_Pos        (3U)

+#define SDMMC_POWER_VSWITCHEN_Msk        (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)  /*!< 0x00000008 */

+#define SDMMC_POWER_VSWITCHEN            SDMMC_POWER_VSWITCHEN_Msk             /*!<Voltage switch procedure enable */

+#define SDMMC_POWER_DIRPOL_Pos           (4U)

+#define SDMMC_POWER_DIRPOL_Msk           (0x1UL << SDMMC_POWER_DIRPOL_Pos)     /*!< 0x00000010 */

+#define SDMMC_POWER_DIRPOL               SDMMC_POWER_DIRPOL_Msk                /*!<Data and Command direction signals polarity selection */

+

+/******************  Bit definition for SDMMC_CLKCR register  ******************/

+#define SDMMC_CLKCR_CLKDIV_Pos           (0U)

+#define SDMMC_CLKCR_CLKDIV_Msk           (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)   /*!< 0x000003FF */

+#define SDMMC_CLKCR_CLKDIV               SDMMC_CLKCR_CLKDIV_Msk                /*!<Clock divide factor             */

+#define SDMMC_CLKCR_PWRSAV_Pos           (12U)

+#define SDMMC_CLKCR_PWRSAV_Msk           (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)     /*!< 0x00001000 */

+#define SDMMC_CLKCR_PWRSAV               SDMMC_CLKCR_PWRSAV_Msk                /*!<Power saving configuration bit  */

+

+#define SDMMC_CLKCR_WIDBUS_Pos           (14U)

+#define SDMMC_CLKCR_WIDBUS_Msk           (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)     /*!< 0x0000C000 */

+#define SDMMC_CLKCR_WIDBUS               SDMMC_CLKCR_WIDBUS_Msk                /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */

+#define SDMMC_CLKCR_WIDBUS_0             (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00004000 */

+#define SDMMC_CLKCR_WIDBUS_1             (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00008000 */

+

+#define SDMMC_CLKCR_NEGEDGE_Pos          (16U)

+#define SDMMC_CLKCR_NEGEDGE_Msk          (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)    /*!< 0x00010000 */

+#define SDMMC_CLKCR_NEGEDGE              SDMMC_CLKCR_NEGEDGE_Msk               /*!<SDMMC_CK dephasing selection bit */

+#define SDMMC_CLKCR_HWFC_EN_Pos          (17U)

+#define SDMMC_CLKCR_HWFC_EN_Msk          (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)    /*!< 0x00020000 */

+#define SDMMC_CLKCR_HWFC_EN              SDMMC_CLKCR_HWFC_EN_Msk               /*!<HW Flow Control enable           */

+#define SDMMC_CLKCR_DDR_Pos              (18U)

+#define SDMMC_CLKCR_DDR_Msk              (0x1UL << SDMMC_CLKCR_DDR_Pos)        /*!< 0x00040000 */

+#define SDMMC_CLKCR_DDR                  SDMMC_CLKCR_DDR_Msk                   /*!<Data rate signaling selection    */

+#define SDMMC_CLKCR_BUSSPEED_Pos         (19U)

+#define SDMMC_CLKCR_BUSSPEED_Msk         (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)   /*!< 0x00080000 */

+#define SDMMC_CLKCR_BUSSPEED             SDMMC_CLKCR_BUSSPEED_Msk              /*!<Bus speed mode selection         */

+#define SDMMC_CLKCR_SELCLKRX_Pos         (20U)

+#define SDMMC_CLKCR_SELCLKRX_Msk         (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)   /*!< 0x00300000 */

+#define SDMMC_CLKCR_SELCLKRX             SDMMC_CLKCR_SELCLKRX_Msk              /*!<SELCLKRX[1:0] bits (Receive clock selection) */

+#define SDMMC_CLKCR_SELCLKRX_0           (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00100000 */

+#define SDMMC_CLKCR_SELCLKRX_1           (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00200000 */

+

+/*******************  Bit definition for SDMMC_ARG register  *******************/

+#define SDMMC_ARG_CMDARG_Pos             (0U)

+#define SDMMC_ARG_CMDARG_Msk             (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_ARG_CMDARG                 SDMMC_ARG_CMDARG_Msk                  /*!<Command argument */

+

+/*******************  Bit definition for SDMMC_CMD register  *******************/

+#define SDMMC_CMD_CMDINDEX_Pos           (0U)

+#define SDMMC_CMD_CMDINDEX_Msk           (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)    /*!< 0x0000003F */

+#define SDMMC_CMD_CMDINDEX               SDMMC_CMD_CMDINDEX_Msk                /*!<Command Index                               */

+#define SDMMC_CMD_CMDTRANS_Pos           (6U)

+#define SDMMC_CMD_CMDTRANS_Msk           (0x1UL << SDMMC_CMD_CMDTRANS_Pos)     /*!< 0x00000040 */

+#define SDMMC_CMD_CMDTRANS               SDMMC_CMD_CMDTRANS_Msk                /*!<CPSM Treats command as a Data Transfer      */

+#define SDMMC_CMD_CMDSTOP_Pos            (7U)

+#define SDMMC_CMD_CMDSTOP_Msk            (0x1UL << SDMMC_CMD_CMDSTOP_Pos)      /*!< 0x00000080 */

+#define SDMMC_CMD_CMDSTOP                SDMMC_CMD_CMDSTOP_Msk                 /*!<CPSM Treats command as a Stop               */

+

+#define SDMMC_CMD_WAITRESP_Pos           (8U)

+#define SDMMC_CMD_WAITRESP_Msk           (0x3UL << SDMMC_CMD_WAITRESP_Pos)     /*!< 0x00000300 */

+#define SDMMC_CMD_WAITRESP               SDMMC_CMD_WAITRESP_Msk                /*!<WAITRESP[1:0] bits (Wait for response bits) */

+#define SDMMC_CMD_WAITRESP_0             (0x1UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000100 */

+#define SDMMC_CMD_WAITRESP_1             (0x2UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000200 */

+

+#define SDMMC_CMD_WAITINT_Pos            (10U)

+#define SDMMC_CMD_WAITINT_Msk            (0x1UL << SDMMC_CMD_WAITINT_Pos)      /*!< 0x00000400 */

+#define SDMMC_CMD_WAITINT                SDMMC_CMD_WAITINT_Msk                 /*!<CPSM Waits for Interrupt Request                               */

+#define SDMMC_CMD_WAITPEND_Pos           (11U)

+#define SDMMC_CMD_WAITPEND_Msk           (0x1UL << SDMMC_CMD_WAITPEND_Pos)     /*!< 0x00000800 */

+#define SDMMC_CMD_WAITPEND               SDMMC_CMD_WAITPEND_Msk                /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */

+#define SDMMC_CMD_CPSMEN_Pos             (12U)

+#define SDMMC_CMD_CPSMEN_Msk             (0x1UL << SDMMC_CMD_CPSMEN_Pos)       /*!< 0x00001000 */

+#define SDMMC_CMD_CPSMEN                 SDMMC_CMD_CPSMEN_Msk                  /*!<Command path state machine (CPSM) Enable bit                   */

+#define SDMMC_CMD_DTHOLD_Pos             (13U)

+#define SDMMC_CMD_DTHOLD_Msk             (0x1UL << SDMMC_CMD_DTHOLD_Pos)       /*!< 0x00002000 */

+#define SDMMC_CMD_DTHOLD                 SDMMC_CMD_DTHOLD_Msk                  /*!<Hold new data block transmission and reception in the DPSM     */

+#define SDMMC_CMD_BOOTMODE_Pos           (14U)

+#define SDMMC_CMD_BOOTMODE_Msk           (0x1UL << SDMMC_CMD_BOOTMODE_Pos)     /*!< 0x00004000 */

+#define SDMMC_CMD_BOOTMODE               SDMMC_CMD_BOOTMODE_Msk                /*!<Boot mode                                                      */

+#define SDMMC_CMD_BOOTEN_Pos             (15U)

+#define SDMMC_CMD_BOOTEN_Msk             (0x1UL << SDMMC_CMD_BOOTEN_Pos)       /*!< 0x00008000 */

+#define SDMMC_CMD_BOOTEN                 SDMMC_CMD_BOOTEN_Msk                  /*!<Enable Boot mode procedure                                     */

+#define SDMMC_CMD_CMDSUSPEND_Pos         (16U)

+#define SDMMC_CMD_CMDSUSPEND_Msk         (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)   /*!< 0x00010000 */

+#define SDMMC_CMD_CMDSUSPEND             SDMMC_CMD_CMDSUSPEND_Msk              /*!<CPSM Treats command as a Suspend or Resume command             */

+

+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/

+#define SDMMC_RESPCMD_RESPCMD_Pos        (0U)

+#define SDMMC_RESPCMD_RESPCMD_Msk        (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */

+#define SDMMC_RESPCMD_RESPCMD            SDMMC_RESPCMD_RESPCMD_Msk             /*!<Response command index */

+

+/******************  Bit definition for SDMMC_RESP0 register  ******************/

+#define SDMMC_RESP0_CARDSTATUS0_Pos      (0U)

+#define SDMMC_RESP0_CARDSTATUS0_Msk      (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP0_CARDSTATUS0          SDMMC_RESP0_CARDSTATUS0_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP1 register  ******************/

+#define SDMMC_RESP1_CARDSTATUS1_Pos      (0U)

+#define SDMMC_RESP1_CARDSTATUS1_Msk      (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP1_CARDSTATUS1          SDMMC_RESP1_CARDSTATUS1_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP2 register  ******************/

+#define SDMMC_RESP2_CARDSTATUS2_Pos      (0U)

+#define SDMMC_RESP2_CARDSTATUS2_Msk      (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP2_CARDSTATUS2          SDMMC_RESP2_CARDSTATUS2_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP3 register  ******************/

+#define SDMMC_RESP3_CARDSTATUS3_Pos      (0U)

+#define SDMMC_RESP3_CARDSTATUS3_Msk      (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP3_CARDSTATUS3          SDMMC_RESP3_CARDSTATUS3_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP4 register  ******************/

+#define SDMMC_RESP4_CARDSTATUS4_Pos      (0U)

+#define SDMMC_RESP4_CARDSTATUS4_Msk      (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP4_CARDSTATUS4          SDMMC_RESP4_CARDSTATUS4_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_DTIMER register  *****************/

+#define SDMMC_DTIMER_DATATIME_Pos        (0U)

+#define SDMMC_DTIMER_DATATIME_Msk        (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_DTIMER_DATATIME            SDMMC_DTIMER_DATATIME_Msk             /*!<Data timeout period. */

+

+/******************  Bit definition for SDMMC_DLEN register  *******************/

+#define SDMMC_DLEN_DATALENGTH_Pos        (0U)

+#define SDMMC_DLEN_DATALENGTH_Msk        (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_DLEN_DATALENGTH            SDMMC_DLEN_DATALENGTH_Msk             /*!<Data length value    */

+

+/******************  Bit definition for SDMMC_DCTRL register  ******************/

+#define SDMMC_DCTRL_DTEN_Pos             (0U)

+#define SDMMC_DCTRL_DTEN_Msk             (0x1UL << SDMMC_DCTRL_DTEN_Pos)       /*!< 0x00000001 */

+#define SDMMC_DCTRL_DTEN                 SDMMC_DCTRL_DTEN_Msk                  /*!<Data transfer enabled bit                */

+#define SDMMC_DCTRL_DTDIR_Pos            (1U)

+#define SDMMC_DCTRL_DTDIR_Msk            (0x1UL << SDMMC_DCTRL_DTDIR_Pos)      /*!< 0x00000002 */

+#define SDMMC_DCTRL_DTDIR                SDMMC_DCTRL_DTDIR_Msk                 /*!<Data transfer direction selection        */

+#define SDMMC_DCTRL_DTMODE_Pos           (2U)

+#define SDMMC_DCTRL_DTMODE_Msk           (0x3UL << SDMMC_DCTRL_DTMODE_Pos)     /*!< 0x0000000C */

+#define SDMMC_DCTRL_DTMODE               SDMMC_DCTRL_DTMODE_Msk                /*!<DTMODE[1:0] Data transfer mode selection */

+#define SDMMC_DCTRL_DTMODE_0             (0x1UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000004 */

+#define SDMMC_DCTRL_DTMODE_1             (0x2UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000008 */

+

+#define SDMMC_DCTRL_DBLOCKSIZE_Pos       (4U)

+#define SDMMC_DCTRL_DBLOCKSIZE_Msk       (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */

+#define SDMMC_DCTRL_DBLOCKSIZE           SDMMC_DCTRL_DBLOCKSIZE_Msk            /*!<DBLOCKSIZE[3:0] bits (Data block size) */

+#define SDMMC_DCTRL_DBLOCKSIZE_0         (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000010 */

+#define SDMMC_DCTRL_DBLOCKSIZE_1         (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000020 */

+#define SDMMC_DCTRL_DBLOCKSIZE_2         (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000040 */

+#define SDMMC_DCTRL_DBLOCKSIZE_3         (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000080 */

+

+#define SDMMC_DCTRL_RWSTART_Pos          (8U)

+#define SDMMC_DCTRL_RWSTART_Msk          (0x1UL << SDMMC_DCTRL_RWSTART_Pos)    /*!< 0x00000100 */

+#define SDMMC_DCTRL_RWSTART              SDMMC_DCTRL_RWSTART_Msk               /*!<Read wait start                                 */

+#define SDMMC_DCTRL_RWSTOP_Pos           (9U)

+#define SDMMC_DCTRL_RWSTOP_Msk           (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)     /*!< 0x00000200 */

+#define SDMMC_DCTRL_RWSTOP               SDMMC_DCTRL_RWSTOP_Msk                /*!<Read wait stop                                  */

+#define SDMMC_DCTRL_RWMOD_Pos            (10U)

+#define SDMMC_DCTRL_RWMOD_Msk            (0x1UL << SDMMC_DCTRL_RWMOD_Pos)      /*!< 0x00000400 */

+#define SDMMC_DCTRL_RWMOD                SDMMC_DCTRL_RWMOD_Msk                 /*!<Read wait mode                                  */

+#define SDMMC_DCTRL_SDIOEN_Pos           (11U)

+#define SDMMC_DCTRL_SDIOEN_Msk           (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)     /*!< 0x00000800 */

+#define SDMMC_DCTRL_SDIOEN               SDMMC_DCTRL_SDIOEN_Msk                /*!<SD I/O enable functions                         */

+#define SDMMC_DCTRL_BOOTACKEN_Pos        (12U)

+#define SDMMC_DCTRL_BOOTACKEN_Msk        (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)  /*!< 0x00001000 */

+#define SDMMC_DCTRL_BOOTACKEN            SDMMC_DCTRL_BOOTACKEN_Msk             /*!<Enable the reception of the Boot Acknowledgment */

+#define SDMMC_DCTRL_FIFORST_Pos          (13U)

+#define SDMMC_DCTRL_FIFORST_Msk          (0x1UL << SDMMC_DCTRL_FIFORST_Pos)    /*!< 0x00002000 */

+#define SDMMC_DCTRL_FIFORST              SDMMC_DCTRL_FIFORST_Msk               /*!<FIFO reset                                      */

+

+/******************  Bit definition for SDMMC_DCOUNT register  *****************/

+#define SDMMC_DCOUNT_DATACOUNT_Pos       (0U)

+#define SDMMC_DCOUNT_DATACOUNT_Msk       (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_DCOUNT_DATACOUNT           SDMMC_DCOUNT_DATACOUNT_Msk            /*!<Data count value */

+

+/******************  Bit definition for SDMMC_STA register  ********************/

+#define SDMMC_STA_CCRCFAIL_Pos           (0U)

+#define SDMMC_STA_CCRCFAIL_Msk           (0x1UL << SDMMC_STA_CCRCFAIL_Pos)     /*!< 0x00000001 */

+#define SDMMC_STA_CCRCFAIL               SDMMC_STA_CCRCFAIL_Msk                /*!<Command response received (CRC check failed)  */

+#define SDMMC_STA_DCRCFAIL_Pos           (1U)

+#define SDMMC_STA_DCRCFAIL_Msk           (0x1UL << SDMMC_STA_DCRCFAIL_Pos)     /*!< 0x00000002 */

+#define SDMMC_STA_DCRCFAIL               SDMMC_STA_DCRCFAIL_Msk                /*!<Data block sent/received (CRC check failed)   */

+#define SDMMC_STA_CTIMEOUT_Pos           (2U)

+#define SDMMC_STA_CTIMEOUT_Msk           (0x1UL << SDMMC_STA_CTIMEOUT_Pos)     /*!< 0x00000004 */

+#define SDMMC_STA_CTIMEOUT               SDMMC_STA_CTIMEOUT_Msk                /*!<Command response timeout                      */

+#define SDMMC_STA_DTIMEOUT_Pos           (3U)

+#define SDMMC_STA_DTIMEOUT_Msk           (0x1UL << SDMMC_STA_DTIMEOUT_Pos)     /*!< 0x00000008 */

+#define SDMMC_STA_DTIMEOUT               SDMMC_STA_DTIMEOUT_Msk                /*!<Data timeout                                  */

+#define SDMMC_STA_TXUNDERR_Pos           (4U)

+#define SDMMC_STA_TXUNDERR_Msk           (0x1UL << SDMMC_STA_TXUNDERR_Pos)     /*!< 0x00000010 */

+#define SDMMC_STA_TXUNDERR               SDMMC_STA_TXUNDERR_Msk                /*!<Transmit FIFO underrun error                  */

+#define SDMMC_STA_RXOVERR_Pos            (5U)

+#define SDMMC_STA_RXOVERR_Msk            (0x1UL << SDMMC_STA_RXOVERR_Pos)      /*!< 0x00000020 */

+#define SDMMC_STA_RXOVERR                SDMMC_STA_RXOVERR_Msk                 /*!<Received FIFO overrun error                   */

+#define SDMMC_STA_CMDREND_Pos            (6U)

+#define SDMMC_STA_CMDREND_Msk            (0x1UL << SDMMC_STA_CMDREND_Pos)      /*!< 0x00000040 */

+#define SDMMC_STA_CMDREND                SDMMC_STA_CMDREND_Msk                 /*!<Command response received (CRC check passed)  */

+#define SDMMC_STA_CMDSENT_Pos            (7U)

+#define SDMMC_STA_CMDSENT_Msk            (0x1UL << SDMMC_STA_CMDSENT_Pos)      /*!< 0x00000080 */

+#define SDMMC_STA_CMDSENT                SDMMC_STA_CMDSENT_Msk                 /*!<Command sent (no response required)           */

+#define SDMMC_STA_DATAEND_Pos            (8U)

+#define SDMMC_STA_DATAEND_Msk            (0x1UL << SDMMC_STA_DATAEND_Pos)      /*!< 0x00000100 */

+#define SDMMC_STA_DATAEND                SDMMC_STA_DATAEND_Msk                 /*!<Data end (data counter, SDIDCOUNT, is zero)   */

+#define SDMMC_STA_DHOLD_Pos              (9U)

+#define SDMMC_STA_DHOLD_Msk              (0x1UL << SDMMC_STA_DHOLD_Pos)        /*!< 0x00000200 */

+#define SDMMC_STA_DHOLD                  SDMMC_STA_DHOLD_Msk                   /*!<Data transfer Hold                                                      */

+#define SDMMC_STA_DBCKEND_Pos            (10U)

+#define SDMMC_STA_DBCKEND_Msk            (0x1UL << SDMMC_STA_DBCKEND_Pos)      /*!< 0x00000400 */

+#define SDMMC_STA_DBCKEND                SDMMC_STA_DBCKEND_Msk                 /*!<Data block sent/received (CRC check passed)   */

+#define SDMMC_STA_DABORT_Pos             (11U)

+#define SDMMC_STA_DABORT_Msk             (0x1UL << SDMMC_STA_DABORT_Pos)       /*!< 0x00000800 */

+#define SDMMC_STA_DABORT                 SDMMC_STA_DABORT_Msk                  /*!<Data transfer aborted by CMD12                                          */

+#define SDMMC_STA_DPSMACT_Pos            (12U)

+#define SDMMC_STA_DPSMACT_Msk            (0x1UL << SDMMC_STA_DPSMACT_Pos)      /*!< 0x00001000 */

+#define SDMMC_STA_DPSMACT                SDMMC_STA_DPSMACT_Msk                 /*!<Data path state machine active                                       */

+#define SDMMC_STA_CPSMACT_Pos            (13U)

+#define SDMMC_STA_CPSMACT_Msk            (0x1UL << SDMMC_STA_CPSMACT_Pos)      /*!< 0x00002000 */

+#define SDMMC_STA_CPSMACT                SDMMC_STA_CPSMACT_Msk                 /*!<Command path state machine active                                          */

+#define SDMMC_STA_TXFIFOHE_Pos           (14U)

+#define SDMMC_STA_TXFIFOHE_Msk           (0x1UL << SDMMC_STA_TXFIFOHE_Pos)     /*!< 0x00004000 */

+#define SDMMC_STA_TXFIFOHE               SDMMC_STA_TXFIFOHE_Msk                /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */

+#define SDMMC_STA_RXFIFOHF_Pos           (15U)

+#define SDMMC_STA_RXFIFOHF_Msk           (0x1UL << SDMMC_STA_RXFIFOHF_Pos)     /*!< 0x00008000 */

+#define SDMMC_STA_RXFIFOHF               SDMMC_STA_RXFIFOHF_Msk                /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */

+#define SDMMC_STA_TXFIFOF_Pos            (16U)

+#define SDMMC_STA_TXFIFOF_Msk            (0x1UL << SDMMC_STA_TXFIFOF_Pos)      /*!< 0x00010000 */

+#define SDMMC_STA_TXFIFOF                SDMMC_STA_TXFIFOF_Msk                 /*!<Transmit FIFO full                            */

+#define SDMMC_STA_RXFIFOF_Pos            (17U)

+#define SDMMC_STA_RXFIFOF_Msk            (0x1UL << SDMMC_STA_RXFIFOF_Pos)      /*!< 0x00020000 */

+#define SDMMC_STA_RXFIFOF                SDMMC_STA_RXFIFOF_Msk                 /*!<Receive FIFO full                             */

+#define SDMMC_STA_TXFIFOE_Pos            (18U)

+#define SDMMC_STA_TXFIFOE_Msk            (0x1UL << SDMMC_STA_TXFIFOE_Pos)      /*!< 0x00040000 */

+#define SDMMC_STA_TXFIFOE                SDMMC_STA_TXFIFOE_Msk                 /*!<Transmit FIFO empty                           */

+#define SDMMC_STA_RXFIFOE_Pos            (19U)

+#define SDMMC_STA_RXFIFOE_Msk            (0x1UL << SDMMC_STA_RXFIFOE_Pos)      /*!< 0x00080000 */

+#define SDMMC_STA_RXFIFOE                SDMMC_STA_RXFIFOE_Msk                 /*!<Receive FIFO empty                            */

+#define SDMMC_STA_BUSYD0_Pos             (20U)

+#define SDMMC_STA_BUSYD0_Msk             (0x1UL << SDMMC_STA_BUSYD0_Pos)       /*!< 0x00100000 */

+#define SDMMC_STA_BUSYD0                 SDMMC_STA_BUSYD0_Msk                  /*!<Inverted value of SDMMC_D0 line (Busy)                                  */

+#define SDMMC_STA_BUSYD0END_Pos          (21U)

+#define SDMMC_STA_BUSYD0END_Msk          (0x1UL << SDMMC_STA_BUSYD0END_Pos)    /*!< 0x00200000 */

+#define SDMMC_STA_BUSYD0END              SDMMC_STA_BUSYD0END_Msk               /*!<End of SDMMC_D0 Busy following a CMD response detected                  */

+#define SDMMC_STA_SDIOIT_Pos             (22U)

+#define SDMMC_STA_SDIOIT_Msk             (0x1UL << SDMMC_STA_SDIOIT_Pos)       /*!< 0x00400000 */

+#define SDMMC_STA_SDIOIT                 SDMMC_STA_SDIOIT_Msk                  /*!<SDIO interrupt received                                                 */

+#define SDMMC_STA_ACKFAIL_Pos            (23U)

+#define SDMMC_STA_ACKFAIL_Msk            (0x1UL << SDMMC_STA_ACKFAIL_Pos)      /*!< 0x00800000 */

+#define SDMMC_STA_ACKFAIL                SDMMC_STA_ACKFAIL_Msk                 /*!<Boot Acknowledgment received (BootAck check fail)                       */

+#define SDMMC_STA_ACKTIMEOUT_Pos         (24U)

+#define SDMMC_STA_ACKTIMEOUT_Msk         (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)   /*!< 0x01000000 */

+#define SDMMC_STA_ACKTIMEOUT             SDMMC_STA_ACKTIMEOUT_Msk              /*!<Boot Acknowledgment timeout                                             */

+#define SDMMC_STA_VSWEND_Pos             (25U)

+#define SDMMC_STA_VSWEND_Msk             (0x1UL << SDMMC_STA_VSWEND_Pos)       /*!< 0x02000000 */

+#define SDMMC_STA_VSWEND                 SDMMC_STA_VSWEND_Msk                  /*!<Voltage switch critical timing section completion                       */

+#define SDMMC_STA_CKSTOP_Pos             (26U)

+#define SDMMC_STA_CKSTOP_Msk             (0x1UL << SDMMC_STA_CKSTOP_Pos)       /*!< 0x04000000 */

+#define SDMMC_STA_CKSTOP                 SDMMC_STA_CKSTOP_Msk                  /*!<SDMMC_CK stopped in Voltage switch procedure                            */

+#define SDMMC_STA_IDMATE_Pos             (27U)

+#define SDMMC_STA_IDMATE_Msk             (0x1UL << SDMMC_STA_IDMATE_Pos)       /*!< 0x08000000 */

+#define SDMMC_STA_IDMATE                 SDMMC_STA_IDMATE_Msk                  /*!<IDMA transfer error                                                     */

+#define SDMMC_STA_IDMABTC_Pos            (28U)

+#define SDMMC_STA_IDMABTC_Msk            (0x1UL << SDMMC_STA_IDMABTC_Pos)      /*!< 0x10000000 */

+#define SDMMC_STA_IDMABTC                SDMMC_STA_IDMABTC_Msk                 /*!<IDMA buffer transfer complete                                           */

+

+/*******************  Bit definition for SDMMC_ICR register  *******************/

+#define SDMMC_ICR_CCRCFAILC_Pos          (0U)

+#define SDMMC_ICR_CCRCFAILC_Msk          (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)    /*!< 0x00000001 */

+#define SDMMC_ICR_CCRCFAILC              SDMMC_ICR_CCRCFAILC_Msk               /*!<CCRCFAIL flag clear bit */

+#define SDMMC_ICR_DCRCFAILC_Pos          (1U)

+#define SDMMC_ICR_DCRCFAILC_Msk          (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)    /*!< 0x00000002 */

+#define SDMMC_ICR_DCRCFAILC              SDMMC_ICR_DCRCFAILC_Msk               /*!<DCRCFAIL flag clear bit */

+#define SDMMC_ICR_CTIMEOUTC_Pos          (2U)

+#define SDMMC_ICR_CTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)    /*!< 0x00000004 */

+#define SDMMC_ICR_CTIMEOUTC              SDMMC_ICR_CTIMEOUTC_Msk               /*!<CTIMEOUT flag clear bit */

+#define SDMMC_ICR_DTIMEOUTC_Pos          (3U)

+#define SDMMC_ICR_DTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)    /*!< 0x00000008 */

+#define SDMMC_ICR_DTIMEOUTC              SDMMC_ICR_DTIMEOUTC_Msk               /*!<DTIMEOUT flag clear bit */

+#define SDMMC_ICR_TXUNDERRC_Pos          (4U)

+#define SDMMC_ICR_TXUNDERRC_Msk          (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)    /*!< 0x00000010 */

+#define SDMMC_ICR_TXUNDERRC              SDMMC_ICR_TXUNDERRC_Msk               /*!<TXUNDERR flag clear bit */

+#define SDMMC_ICR_RXOVERRC_Pos           (5U)

+#define SDMMC_ICR_RXOVERRC_Msk           (0x1UL << SDMMC_ICR_RXOVERRC_Pos)     /*!< 0x00000020 */

+#define SDMMC_ICR_RXOVERRC               SDMMC_ICR_RXOVERRC_Msk                /*!<RXOVERR flag clear bit  */

+#define SDMMC_ICR_CMDRENDC_Pos           (6U)

+#define SDMMC_ICR_CMDRENDC_Msk           (0x1UL << SDMMC_ICR_CMDRENDC_Pos)     /*!< 0x00000040 */

+#define SDMMC_ICR_CMDRENDC               SDMMC_ICR_CMDRENDC_Msk                /*!<CMDREND flag clear bit  */

+#define SDMMC_ICR_CMDSENTC_Pos           (7U)

+#define SDMMC_ICR_CMDSENTC_Msk           (0x1UL << SDMMC_ICR_CMDSENTC_Pos)     /*!< 0x00000080 */

+#define SDMMC_ICR_CMDSENTC               SDMMC_ICR_CMDSENTC_Msk                /*!<CMDSENT flag clear bit  */

+#define SDMMC_ICR_DATAENDC_Pos           (8U)

+#define SDMMC_ICR_DATAENDC_Msk           (0x1UL << SDMMC_ICR_DATAENDC_Pos)     /*!< 0x00000100 */

+#define SDMMC_ICR_DATAENDC               SDMMC_ICR_DATAENDC_Msk                /*!<DATAEND flag clear bit  */

+#define SDMMC_ICR_DHOLDC_Pos             (9U)

+#define SDMMC_ICR_DHOLDC_Msk             (0x1UL << SDMMC_ICR_DHOLDC_Pos)       /*!< 0x00000200 */

+#define SDMMC_ICR_DHOLDC                 SDMMC_ICR_DHOLDC_Msk                  /*!<DHOLD flag clear bit       */

+#define SDMMC_ICR_DBCKENDC_Pos           (10U)

+#define SDMMC_ICR_DBCKENDC_Msk           (0x1UL << SDMMC_ICR_DBCKENDC_Pos)     /*!< 0x00000400 */

+#define SDMMC_ICR_DBCKENDC               SDMMC_ICR_DBCKENDC_Msk                /*!<DBCKEND flag clear bit  */

+#define SDMMC_ICR_DABORTC_Pos            (11U)

+#define SDMMC_ICR_DABORTC_Msk            (0x1UL << SDMMC_ICR_DABORTC_Pos)      /*!< 0x00000800 */

+#define SDMMC_ICR_DABORTC                SDMMC_ICR_DABORTC_Msk                 /*!<DABORTC flag clear bit     */

+#define SDMMC_ICR_BUSYD0ENDC_Pos         (21U)

+#define SDMMC_ICR_BUSYD0ENDC_Msk         (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)   /*!< 0x00200000 */

+#define SDMMC_ICR_BUSYD0ENDC             SDMMC_ICR_BUSYD0ENDC_Msk              /*!<BUSYD0ENDC flag clear bit  */

+#define SDMMC_ICR_SDIOITC_Pos            (22U)

+#define SDMMC_ICR_SDIOITC_Msk            (0x1UL << SDMMC_ICR_SDIOITC_Pos)      /*!< 0x00400000 */

+#define SDMMC_ICR_SDIOITC                SDMMC_ICR_SDIOITC_Msk                 /*!<SDIOIT flag clear bit      */

+#define SDMMC_ICR_ACKFAILC_Pos           (23U)

+#define SDMMC_ICR_ACKFAILC_Msk           (0x1UL << SDMMC_ICR_ACKFAILC_Pos)     /*!< 0x00800000 */

+#define SDMMC_ICR_ACKFAILC               SDMMC_ICR_ACKFAILC_Msk                /*!<ACKFAILC flag clear bit    */

+#define SDMMC_ICR_ACKTIMEOUTC_Pos        (24U)

+#define SDMMC_ICR_ACKTIMEOUTC_Msk        (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)  /*!< 0x01000000 */

+#define SDMMC_ICR_ACKTIMEOUTC            SDMMC_ICR_ACKTIMEOUTC_Msk             /*!<ACKTIMEOUTC flag clear bit */

+#define SDMMC_ICR_VSWENDC_Pos            (25U)

+#define SDMMC_ICR_VSWENDC_Msk            (0x1UL << SDMMC_ICR_VSWENDC_Pos)      /*!< 0x02000000 */

+#define SDMMC_ICR_VSWENDC                SDMMC_ICR_VSWENDC_Msk                 /*!<VSWENDC flag clear bit     */

+#define SDMMC_ICR_CKSTOPC_Pos            (26U)

+#define SDMMC_ICR_CKSTOPC_Msk            (0x1UL << SDMMC_ICR_CKSTOPC_Pos)      /*!< 0x04000000 */

+#define SDMMC_ICR_CKSTOPC                SDMMC_ICR_CKSTOPC_Msk                 /*!<CKSTOPC flag clear bit     */

+#define SDMMC_ICR_IDMATEC_Pos            (27U)

+#define SDMMC_ICR_IDMATEC_Msk            (0x1UL << SDMMC_ICR_IDMATEC_Pos)      /*!< 0x08000000 */

+#define SDMMC_ICR_IDMATEC                SDMMC_ICR_IDMATEC_Msk                 /*!<IDMATEC flag clear bit     */

+#define SDMMC_ICR_IDMABTCC_Pos           (28U)

+#define SDMMC_ICR_IDMABTCC_Msk           (0x1UL << SDMMC_ICR_IDMABTCC_Pos)     /*!< 0x10000000 */

+#define SDMMC_ICR_IDMABTCC               SDMMC_ICR_IDMABTCC_Msk                /*!<IDMABTCC flag clear bit    */

+

+/******************  Bit definition for SDMMC_MASK register  *******************/

+#define SDMMC_MASK_CCRCFAILIE_Pos        (0U)

+#define SDMMC_MASK_CCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)  /*!< 0x00000001 */

+#define SDMMC_MASK_CCRCFAILIE            SDMMC_MASK_CCRCFAILIE_Msk             /*!<Command CRC Fail Interrupt Enable          */

+#define SDMMC_MASK_DCRCFAILIE_Pos        (1U)

+#define SDMMC_MASK_DCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)  /*!< 0x00000002 */

+#define SDMMC_MASK_DCRCFAILIE            SDMMC_MASK_DCRCFAILIE_Msk             /*!<Data CRC Fail Interrupt Enable             */

+#define SDMMC_MASK_CTIMEOUTIE_Pos        (2U)

+#define SDMMC_MASK_CTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)  /*!< 0x00000004 */

+#define SDMMC_MASK_CTIMEOUTIE            SDMMC_MASK_CTIMEOUTIE_Msk             /*!<Command TimeOut Interrupt Enable           */

+#define SDMMC_MASK_DTIMEOUTIE_Pos        (3U)

+#define SDMMC_MASK_DTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)  /*!< 0x00000008 */

+#define SDMMC_MASK_DTIMEOUTIE            SDMMC_MASK_DTIMEOUTIE_Msk             /*!<Data TimeOut Interrupt Enable              */

+#define SDMMC_MASK_TXUNDERRIE_Pos        (4U)

+#define SDMMC_MASK_TXUNDERRIE_Msk        (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)  /*!< 0x00000010 */

+#define SDMMC_MASK_TXUNDERRIE            SDMMC_MASK_TXUNDERRIE_Msk             /*!<Tx FIFO UnderRun Error Interrupt Enable    */

+#define SDMMC_MASK_RXOVERRIE_Pos         (5U)

+#define SDMMC_MASK_RXOVERRIE_Msk         (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)   /*!< 0x00000020 */

+#define SDMMC_MASK_RXOVERRIE             SDMMC_MASK_RXOVERRIE_Msk              /*!<Rx FIFO OverRun Error Interrupt Enable     */

+#define SDMMC_MASK_CMDRENDIE_Pos         (6U)

+#define SDMMC_MASK_CMDRENDIE_Msk         (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)   /*!< 0x00000040 */

+#define SDMMC_MASK_CMDRENDIE             SDMMC_MASK_CMDRENDIE_Msk              /*!<Command Response Received Interrupt Enable */

+#define SDMMC_MASK_CMDSENTIE_Pos         (7U)

+#define SDMMC_MASK_CMDSENTIE_Msk         (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)   /*!< 0x00000080 */

+#define SDMMC_MASK_CMDSENTIE             SDMMC_MASK_CMDSENTIE_Msk              /*!<Command Sent Interrupt Enable              */

+#define SDMMC_MASK_DATAENDIE_Pos         (8U)

+#define SDMMC_MASK_DATAENDIE_Msk         (0x1UL << SDMMC_MASK_DATAENDIE_Pos)   /*!< 0x00000100 */

+#define SDMMC_MASK_DATAENDIE             SDMMC_MASK_DATAENDIE_Msk              /*!<Data End Interrupt Enable                  */

+#define SDMMC_MASK_DHOLDIE_Pos           (9U)

+#define SDMMC_MASK_DHOLDIE_Msk           (0x1UL << SDMMC_MASK_DHOLDIE_Pos)     /*!< 0x00000200 */

+#define SDMMC_MASK_DHOLDIE               SDMMC_MASK_DHOLDIE_Msk                /*!<Data Hold Interrupt Enable                 */

+#define SDMMC_MASK_DBCKENDIE_Pos         (10U)

+#define SDMMC_MASK_DBCKENDIE_Msk         (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)   /*!< 0x00000400 */

+#define SDMMC_MASK_DBCKENDIE             SDMMC_MASK_DBCKENDIE_Msk              /*!<Data Block End Interrupt Enable            */

+#define SDMMC_MASK_DABORTIE_Pos          (11U)

+#define SDMMC_MASK_DABORTIE_Msk          (0x1UL << SDMMC_MASK_DABORTIE_Pos)    /*!< 0x00000800 */

+#define SDMMC_MASK_DABORTIE              SDMMC_MASK_DABORTIE_Msk               /*!<Data transfer aborted interrupt enable     */

+

+#define SDMMC_MASK_TXFIFOHEIE_Pos        (14U)

+#define SDMMC_MASK_TXFIFOHEIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)  /*!< 0x00004000 */

+#define SDMMC_MASK_TXFIFOHEIE            SDMMC_MASK_TXFIFOHEIE_Msk             /*!<Tx FIFO Half Empty interrupt Enable        */

+#define SDMMC_MASK_RXFIFOHFIE_Pos        (15U)

+#define SDMMC_MASK_RXFIFOHFIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)  /*!< 0x00008000 */

+#define SDMMC_MASK_RXFIFOHFIE            SDMMC_MASK_RXFIFOHFIE_Msk             /*!<Rx FIFO Half Full interrupt Enable         */

+

+#define SDMMC_MASK_RXFIFOFIE_Pos         (17U)

+#define SDMMC_MASK_RXFIFOFIE_Msk         (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)   /*!< 0x00020000 */

+#define SDMMC_MASK_RXFIFOFIE             SDMMC_MASK_RXFIFOFIE_Msk              /*!<Rx FIFO Full interrupt Enable              */

+#define SDMMC_MASK_TXFIFOEIE_Pos         (18U)

+#define SDMMC_MASK_TXFIFOEIE_Msk         (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)   /*!< 0x00040000 */

+#define SDMMC_MASK_TXFIFOEIE             SDMMC_MASK_TXFIFOEIE_Msk              /*!<Tx FIFO Empty interrupt Enable             */

+

+#define SDMMC_MASK_BUSYD0ENDIE_Pos       (21U)

+#define SDMMC_MASK_BUSYD0ENDIE_Msk       (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */

+#define SDMMC_MASK_BUSYD0ENDIE           SDMMC_MASK_BUSYD0ENDIE_Msk            /*!<BUSYD0ENDIE interrupt Enable */

+#define SDMMC_MASK_SDIOITIE_Pos           (22U)

+#define SDMMC_MASK_SDIOITIE_Msk           (0x1UL << SDMMC_MASK_SDIOITIE_Pos)     /*!< 0x00400000 */

+#define SDMMC_MASK_SDIOITIE               SDMMC_MASK_SDIOITIE_Msk                /*!<SDMMC Mode Interrupt Received interrupt Enable */

+#define SDMMC_MASK_ACKFAILIE_Pos         (23U)

+#define SDMMC_MASK_ACKFAILIE_Msk         (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)   /*!< 0x00800000 */

+#define SDMMC_MASK_ACKFAILIE             SDMMC_MASK_ACKFAILIE_Msk              /*!<Acknowledgment Fail Interrupt Enable */

+#define SDMMC_MASK_ACKTIMEOUTIE_Pos      (24U)

+#define SDMMC_MASK_ACKTIMEOUTIE_Msk      (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */

+#define SDMMC_MASK_ACKTIMEOUTIE          SDMMC_MASK_ACKTIMEOUTIE_Msk           /*!<Acknowledgment timeout Interrupt Enable */

+#define SDMMC_MASK_VSWENDIE_Pos          (25U)

+#define SDMMC_MASK_VSWENDIE_Msk          (0x1UL << SDMMC_MASK_VSWENDIE_Pos)    /*!< 0x02000000 */

+#define SDMMC_MASK_VSWENDIE              SDMMC_MASK_VSWENDIE_Msk               /*!<Voltage switch critical timing section completion Interrupt Enable */

+#define SDMMC_MASK_CKSTOPIE_Pos          (26U)

+#define SDMMC_MASK_CKSTOPIE_Msk          (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)    /*!< 0x04000000 */

+#define SDMMC_MASK_CKSTOPIE              SDMMC_MASK_CKSTOPIE_Msk               /*!<Voltage Switch clock stopped Interrupt Enable */

+#define SDMMC_MASK_IDMABTCIE_Pos         (28U)

+#define SDMMC_MASK_IDMABTCIE_Msk         (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)   /*!< 0x10000000 */

+#define SDMMC_MASK_IDMABTCIE             SDMMC_MASK_IDMABTCIE_Msk              /*!<IDMA buffer transfer complete Interrupt Enable */

+

+/*****************  Bit definition for SDMMC_ACKTIME register  *****************/

+#define SDMMC_ACKTIME_ACKTIME_Pos        (0U)

+#define SDMMC_ACKTIME_ACKTIME_Msk        (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_ACKTIME_ACKTIME            SDMMC_ACKTIME_ACKTIME_Msk             /*!<Boot acknowledgment timeout period */

+

+/******************  Bit definition for SDMMC_FIFO register  *******************/

+#define SDMMC_FIFO_FIFODATA_Pos          (0U)

+#define SDMMC_FIFO_FIFODATA_Msk          (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_FIFO_FIFODATA              SDMMC_FIFO_FIFODATA_Msk               /*!<Receive and transmit FIFO data */

+

+/******************  Bit definition for SDMMC_IDMACTRL register ****************/

+#define SDMMC_IDMA_IDMAEN_Pos            (0U)

+#define SDMMC_IDMA_IDMAEN_Msk            (0x1UL << SDMMC_IDMA_IDMAEN_Pos)      /*!< 0x00000001 */

+#define SDMMC_IDMA_IDMAEN                SDMMC_IDMA_IDMAEN_Msk                 /*!< Enable the internal DMA of the SDMMC peripheral */

+#define SDMMC_IDMA_IDMABMODE_Pos         (1U)

+#define SDMMC_IDMA_IDMABMODE_Msk         (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)   /*!< 0x00000002 */

+#define SDMMC_IDMA_IDMABMODE             SDMMC_IDMA_IDMABMODE_Msk              /*!< Enable double buffer mode for IDMA */

+#define SDMMC_IDMA_IDMABACT_Pos          (2U)

+#define SDMMC_IDMA_IDMABACT_Msk          (0x1UL << SDMMC_IDMA_IDMABACT_Pos)    /*!< 0x00000004 */

+#define SDMMC_IDMA_IDMABACT              SDMMC_IDMA_IDMABACT_Msk               /*!< Uses buffer 1 when double buffer mode is selected */

+

+/*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/

+#define SDMMC_IDMABSIZE_IDMABNDT_Pos     (5U)

+#define SDMMC_IDMABSIZE_IDMABNDT_Msk     (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */

+#define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */

+

+/*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/

+#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */

+

+/*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/

+#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                        Delay Block Interface (DLYB)                        */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for DLYB_CR register  ********************/

+#define DLYB_CR_DEN_Pos         (0U)

+#define DLYB_CR_DEN_Msk         (0x1UL << DLYB_CR_DEN_Pos)                     /*!< 0x00000001 */

+#define DLYB_CR_DEN             DLYB_CR_DEN_Msk                                /*!<Delay Block enable */

+#define DLYB_CR_SEN_Pos         (1U)

+#define DLYB_CR_SEN_Msk         (0x1UL << DLYB_CR_SEN_Pos)                     /*!< 0x00000002 */

+#define DLYB_CR_SEN             DLYB_CR_SEN_Msk                                /*!<Sampler length enable */

+

+

+/*******************  Bit definition for DLYB_CFGR register  ********************/

+#define DLYB_CFGR_SEL_Pos       (0U)

+#define DLYB_CFGR_SEL_Msk       (0xFUL << DLYB_CFGR_SEL_Pos)                   /*!< 0x0000000F */

+#define DLYB_CFGR_SEL           DLYB_CFGR_SEL_Msk                              /*!<Select the phase for the Output clock[3:0] */

+#define DLYB_CFGR_SEL_0         (0x1UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000001 */

+#define DLYB_CFGR_SEL_1         (0x2UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000002 */

+#define DLYB_CFGR_SEL_2         (0x3UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000003 */

+#define DLYB_CFGR_SEL_3         (0x8UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000008 */

+

+#define DLYB_CFGR_UNIT_Pos      (8U)

+#define DLYB_CFGR_UNIT_Msk      (0x7FUL << DLYB_CFGR_UNIT_Pos)                 /*!< 0x00007F00 */

+#define DLYB_CFGR_UNIT          DLYB_CFGR_UNIT_Msk                             /*!<Delay Defines the delay of a Unit delay cell[6:0] */

+#define DLYB_CFGR_UNIT_0        (0x01UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000100 */

+#define DLYB_CFGR_UNIT_1        (0x02UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000200 */

+#define DLYB_CFGR_UNIT_2        (0x04UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000400 */

+#define DLYB_CFGR_UNIT_3        (0x08UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000800 */

+#define DLYB_CFGR_UNIT_4        (0x10UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00001000 */

+#define DLYB_CFGR_UNIT_5        (0x20UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00002000 */

+#define DLYB_CFGR_UNIT_6        (0x40UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00004000 */

+

+#define DLYB_CFGR_LNG_Pos       (16U)

+#define DLYB_CFGR_LNG_Msk       (0xFFFUL << DLYB_CFGR_LNG_Pos)                 /*!< 0x0FFF0000 */

+#define DLYB_CFGR_LNG           DLYB_CFGR_LNG_Msk                              /*!<Delay line length value[11:0] */

+#define DLYB_CFGR_LNG_0         (0x001UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00010000 */

+#define DLYB_CFGR_LNG_1         (0x002UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00020000 */

+#define DLYB_CFGR_LNG_2         (0x004UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00040000 */

+#define DLYB_CFGR_LNG_3         (0x008UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00080000 */

+#define DLYB_CFGR_LNG_4         (0x010UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00100000 */

+#define DLYB_CFGR_LNG_5         (0x020UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00200000 */

+#define DLYB_CFGR_LNG_6         (0x040UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00400000 */

+#define DLYB_CFGR_LNG_7         (0x080UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00800000 */

+#define DLYB_CFGR_LNG_8         (0x100UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x01000000 */

+#define DLYB_CFGR_LNG_9         (0x200UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x02000000 */

+#define DLYB_CFGR_LNG_10        (0x400UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x04000000 */

+#define DLYB_CFGR_LNG_11        (0x800UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x08000000 */

+

+#define DLYB_CFGR_LNGF_Pos      (31U)

+#define DLYB_CFGR_LNGF_Msk      (0x1UL << DLYB_CFGR_LNGF_Pos)                  /*!< 0x80000000 */

+#define DLYB_CFGR_LNGF          DLYB_CFGR_LNGF_Msk                             /*!<Length valid flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                   Serial Peripheral Interface (SPI/I2S)                    */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for SPI_CR1 register  ********************/

+#define SPI_CR1_SPE_Pos             (0U)

+#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000001 */

+#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<Serial Peripheral Enable                         */

+#define SPI_CR1_MASRX_Pos           (8U)

+#define SPI_CR1_MASRX_Msk           (0x1UL << SPI_CR1_MASRX_Pos)               /*!< 0x00000100 */

+#define SPI_CR1_MASRX               SPI_CR1_MASRX_Msk                          /*!<Master automatic SUSP in Receive mode            */

+#define SPI_CR1_CSTART_Pos          (9U)

+#define SPI_CR1_CSTART_Msk          (0x1UL << SPI_CR1_CSTART_Pos)              /*!< 0x00000200 */

+#define SPI_CR1_CSTART              SPI_CR1_CSTART_Msk                         /*!<Master transfer start                            */

+#define SPI_CR1_CSUSP_Pos           (10U)

+#define SPI_CR1_CSUSP_Msk           (0x1UL << SPI_CR1_CSUSP_Pos)               /*!< 0x00000400 */

+#define SPI_CR1_CSUSP               SPI_CR1_CSUSP_Msk                          /*!<Master SUSPend request                           */

+#define SPI_CR1_HDDIR_Pos           (11U)

+#define SPI_CR1_HDDIR_Msk           (0x1UL << SPI_CR1_HDDIR_Pos)               /*!< 0x00000800 */

+#define SPI_CR1_HDDIR               SPI_CR1_HDDIR_Msk                          /*!<Rx/Tx direction at Half-duplex mode              */

+#define SPI_CR1_SSI_Pos             (12U)

+#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00001000 */

+#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal SS signal input level                   */

+#define SPI_CR1_CRC33_17_Pos        (13U)

+#define SPI_CR1_CRC33_17_Msk        (0x1UL << SPI_CR1_CRC33_17_Pos)            /*!< 0x00002000 */

+#define SPI_CR1_CRC33_17             SPI_CR1_CRC33_17_Msk                      /*!<32-bit CRC polynomial configuration              */

+#define SPI_CR1_RCRCINI_Pos         (14U)

+#define SPI_CR1_RCRCINI_Msk         (0x1UL << SPI_CR1_RCRCINI_Pos)             /*!< 0x00004000 */

+#define SPI_CR1_RCRCINI             SPI_CR1_RCRCINI_Msk                        /*!<CRC init pattern control for receiver            */

+#define SPI_CR1_TCRCINI_Pos         (15U)

+#define SPI_CR1_TCRCINI_Msk         (0x1UL << SPI_CR1_TCRCINI_Pos)             /*!< 0x00008000 */

+#define SPI_CR1_TCRCINI             SPI_CR1_TCRCINI_Msk                        /*!<CRC init pattern control for transmitter         */

+#define SPI_CR1_IOLOCK_Pos          (16U)

+#define SPI_CR1_IOLOCK_Msk          (0x1UL << SPI_CR1_IOLOCK_Pos)              /*!< 0x00010000 */

+#define SPI_CR1_IOLOCK              SPI_CR1_IOLOCK_Msk                         /*!<Locking the AF configuration of associated IOs   */

+

+/*******************  Bit definition for SPI_CR2 register  ********************/

+#define SPI_CR2_TSER_Pos            (16U)

+#define SPI_CR2_TSER_Msk            (0xFFFFUL << SPI_CR2_TSER_Pos)             /*!< 0xFFFF0000 */

+#define SPI_CR2_TSER                SPI_CR2_TSER_Msk                           /*!<Number of data transfer extension                */

+#define SPI_CR2_TSIZE_Pos           (0U)

+#define SPI_CR2_TSIZE_Msk           (0xFFFFUL << SPI_CR2_TSIZE_Pos)            /*!< 0x0000FFFF */

+#define SPI_CR2_TSIZE               SPI_CR2_TSIZE_Msk                          /*!<Number of data at current transfer               */

+

+/*******************  Bit definition for SPI_CFG1 register  ********************/

+#define SPI_CFG1_DSIZE_Pos          (0U)

+#define SPI_CFG1_DSIZE_Msk          (0x1FUL << SPI_CFG1_DSIZE_Pos)             /*!< 0x0000001F */

+#define SPI_CFG1_DSIZE              SPI_CFG1_DSIZE_Msk                         /*!<DSIZE[4:0]: Bits number in single SPI data frame */

+#define SPI_CFG1_DSIZE_0            (0x01UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000001 */

+#define SPI_CFG1_DSIZE_1            (0x02UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000002 */

+#define SPI_CFG1_DSIZE_2            (0x04UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000004 */

+#define SPI_CFG1_DSIZE_3            (0x08UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000008 */

+#define SPI_CFG1_DSIZE_4            (0x10UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000010 */

+

+#define SPI_CFG1_FTHLV_Pos          (5U)

+#define SPI_CFG1_FTHLV_Msk          (0xFUL << SPI_CFG1_FTHLV_Pos)              /*!< 0x000001E0 */

+#define SPI_CFG1_FTHLV              SPI_CFG1_FTHLV_Msk                         /*!<FTHVL [3:0]: FIFO threshold level*/

+#define SPI_CFG1_FTHLV_0            (0x1UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000020 */

+#define SPI_CFG1_FTHLV_1            (0x2UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000040 */

+#define SPI_CFG1_FTHLV_2            (0x4UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000080 */

+#define SPI_CFG1_FTHLV_3            (0x8UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000100 */

+

+#define SPI_CFG1_UDRCFG_Pos         (9U)

+#define SPI_CFG1_UDRCFG_Msk         (0x3UL << SPI_CFG1_UDRCFG_Pos)             /*!< 0x00000600 */

+#define SPI_CFG1_UDRCFG             SPI_CFG1_UDRCFG_Msk                        /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */

+#define SPI_CFG1_UDRCFG_0           (0x1UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000200 */

+#define SPI_CFG1_UDRCFG_1           (0x2UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000400 */

+

+

+#define SPI_CFG1_UDRDET_Pos         (11U)

+#define SPI_CFG1_UDRDET_Msk         (0x3UL << SPI_CFG1_UDRDET_Pos)             /*!< 0x00001800 */

+#define SPI_CFG1_UDRDET             SPI_CFG1_UDRDET_Msk                        /*!<UDRDET[1:0]: Detection of underrun condition     */

+#define SPI_CFG1_UDRDET_0           (0x1UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00000800 */

+#define SPI_CFG1_UDRDET_1           (0x2UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00001000 */

+

+#define SPI_CFG1_RXDMAEN_Pos        (14U)

+#define SPI_CFG1_RXDMAEN_Msk        (0x1UL << SPI_CFG1_RXDMAEN_Pos)            /*!< 0x00004000 */

+#define SPI_CFG1_RXDMAEN            SPI_CFG1_RXDMAEN_Msk                       /*!<Rx DMA stream enable                */

+#define SPI_CFG1_TXDMAEN_Pos        (15U)

+#define SPI_CFG1_TXDMAEN_Msk        (0x1UL << SPI_CFG1_TXDMAEN_Pos)            /*!< 0x00008000 */

+#define SPI_CFG1_TXDMAEN            SPI_CFG1_TXDMAEN_Msk                       /*!<Tx DMA stream enable                */

+

+#define SPI_CFG1_CRCSIZE_Pos        (16U)

+#define SPI_CFG1_CRCSIZE_Msk        (0x1FUL << SPI_CFG1_CRCSIZE_Pos)           /*!< 0x001F0000 */

+#define SPI_CFG1_CRCSIZE            SPI_CFG1_CRCSIZE_Msk                       /*!<CRCSIZE [4:0]: Length of CRC frame*/

+#define SPI_CFG1_CRCSIZE_0          (0x01UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00010000 */

+#define SPI_CFG1_CRCSIZE_1          (0x02UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00020000 */

+#define SPI_CFG1_CRCSIZE_2          (0x04UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00040000 */

+#define SPI_CFG1_CRCSIZE_3          (0x08UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00080000 */

+#define SPI_CFG1_CRCSIZE_4          (0x10UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00100000 */

+

+#define SPI_CFG1_CRCEN_Pos          (22U)

+#define SPI_CFG1_CRCEN_Msk          (0x1UL << SPI_CFG1_CRCEN_Pos)              /*!< 0x00400000 */

+#define SPI_CFG1_CRCEN              SPI_CFG1_CRCEN_Msk                         /*!<Hardware CRC computation enable */

+

+#define SPI_CFG1_MBR_Pos            (28U)

+#define SPI_CFG1_MBR_Msk            (0x7UL << SPI_CFG1_MBR_Pos)                /*!< 0x70000000 */

+#define SPI_CFG1_MBR                SPI_CFG1_MBR_Msk                           /*!<Master baud rate                */

+#define SPI_CFG1_MBR_0              (0x1UL << SPI_CFG1_MBR_Pos)                 /*!< 0x10000000 */

+#define SPI_CFG1_MBR_1              (0x2UL << SPI_CFG1_MBR_Pos)                 /*!< 0x20000000 */

+#define SPI_CFG1_MBR_2              (0x4UL << SPI_CFG1_MBR_Pos)                 /*!< 0x40000000 */

+

+/*******************  Bit definition for SPI_CFG2 register  ********************/

+#define SPI_CFG2_MSSI_Pos           (0U)

+#define SPI_CFG2_MSSI_Msk           (0xFUL << SPI_CFG2_MSSI_Pos)               /*!< 0x0000000F */

+#define SPI_CFG2_MSSI               SPI_CFG2_MSSI_Msk                          /*!<Master SS Idleness */

+#define SPI_CFG2_MSSI_0             (0x1UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000001 */

+#define SPI_CFG2_MSSI_1             (0x2UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000002 */

+#define SPI_CFG2_MSSI_2             (0x4UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000004 */

+#define SPI_CFG2_MSSI_3             (0x8UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000008 */

+

+#define SPI_CFG2_MIDI_Pos           (4U)

+#define SPI_CFG2_MIDI_Msk           (0xFUL << SPI_CFG2_MIDI_Pos)               /*!< 0x000000F0 */

+#define SPI_CFG2_MIDI               SPI_CFG2_MIDI_Msk                          /*!<Master Inter-Data Idleness */

+#define SPI_CFG2_MIDI_0             (0x1UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000010 */

+#define SPI_CFG2_MIDI_1             (0x2UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000020 */

+#define SPI_CFG2_MIDI_2             (0x4UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000040 */

+#define SPI_CFG2_MIDI_3             (0x8UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000080 */

+

+#define SPI_CFG2_IOSWP_Pos          (15U)

+#define SPI_CFG2_IOSWP_Msk          (0x1UL << SPI_CFG2_IOSWP_Pos)              /*!< 0x00008000 */

+#define SPI_CFG2_IOSWP              SPI_CFG2_IOSWP_Msk                         /*!<Swap functionality of MISO and MOSI pins */

+

+#define SPI_CFG2_COMM_Pos           (17U)

+#define SPI_CFG2_COMM_Msk           (0x3UL << SPI_CFG2_COMM_Pos)               /*!< 0x00060000 */

+#define SPI_CFG2_COMM               SPI_CFG2_COMM_Msk                          /*!<COMM [1:0]: SPI Communication Mode*/

+#define SPI_CFG2_COMM_0             (0x1UL << SPI_CFG2_COMM_Pos)                /*!< 0x00020000 */

+#define SPI_CFG2_COMM_1             (0x2UL << SPI_CFG2_COMM_Pos)                /*!< 0x00040000 */

+

+#define SPI_CFG2_SP_Pos             (19U)

+#define SPI_CFG2_SP_Msk             (0x7UL << SPI_CFG2_SP_Pos)                 /*!< 0x00380000 */

+#define SPI_CFG2_SP                 SPI_CFG2_SP_Msk                            /*!<SP[2:0]: Serial Protocol */

+#define SPI_CFG2_SP_0               (0x1UL << SPI_CFG2_SP_Pos)                  /*!< 0x00080000 */

+#define SPI_CFG2_SP_1               (0x2UL << SPI_CFG2_SP_Pos)                  /*!< 0x00100000 */

+#define SPI_CFG2_SP_2               (0x4UL << SPI_CFG2_SP_Pos)                  /*!< 0x00200000 */

+

+#define SPI_CFG2_MASTER_Pos         (22U)

+#define SPI_CFG2_MASTER_Msk         (0x1UL << SPI_CFG2_MASTER_Pos)             /*!< 0x00400000 */

+#define SPI_CFG2_MASTER             SPI_CFG2_MASTER_Msk                        /*!<SPI Master           */

+#define SPI_CFG2_LSBFRST_Pos        (23U)

+#define SPI_CFG2_LSBFRST_Msk        (0x1UL << SPI_CFG2_LSBFRST_Pos)            /*!< 0x00800000 */

+#define SPI_CFG2_LSBFRST            SPI_CFG2_LSBFRST_Msk                       /*!<Data frame format               */

+#define SPI_CFG2_CPHA_Pos           (24U)

+#define SPI_CFG2_CPHA_Msk           (0x1UL << SPI_CFG2_CPHA_Pos)               /*!< 0x01000000 */

+#define SPI_CFG2_CPHA               SPI_CFG2_CPHA_Msk                          /*!<Clock Phase      */

+#define SPI_CFG2_CPOL_Pos           (25U)

+#define SPI_CFG2_CPOL_Msk           (0x1UL << SPI_CFG2_CPOL_Pos)               /*!< 0x02000000 */

+#define SPI_CFG2_CPOL               SPI_CFG2_CPOL_Msk                          /*!<Clock Polarity   */

+#define SPI_CFG2_SSM_Pos            (26U)

+#define SPI_CFG2_SSM_Msk            (0x1UL << SPI_CFG2_SSM_Pos)                /*!< 0x04000000 */

+#define SPI_CFG2_SSM                SPI_CFG2_SSM_Msk                           /*!<Software slave management */

+

+#define SPI_CFG2_SSIOP_Pos          (28U)

+#define SPI_CFG2_SSIOP_Msk          (0x1UL << SPI_CFG2_SSIOP_Pos)              /*!< 0x10000000 */

+#define SPI_CFG2_SSIOP              SPI_CFG2_SSIOP_Msk                         /*!<SS input/output polarity */

+#define SPI_CFG2_SSOE_Pos           (29U)

+#define SPI_CFG2_SSOE_Msk           (0x1UL << SPI_CFG2_SSOE_Pos)               /*!< 0x20000000 */

+#define SPI_CFG2_SSOE               SPI_CFG2_SSOE_Msk                          /*!<SS output enable */

+#define SPI_CFG2_SSOM_Pos           (30U)

+#define SPI_CFG2_SSOM_Msk           (0x1UL << SPI_CFG2_SSOM_Pos)               /*!< 0x40000000 */

+#define SPI_CFG2_SSOM               SPI_CFG2_SSOM_Msk                          /*!<SS output management in master mode */

+

+#define SPI_CFG2_AFCNTR_Pos         (31U)

+#define SPI_CFG2_AFCNTR_Msk         (0x1UL << SPI_CFG2_AFCNTR_Pos)             /*!< 0x80000000 */

+#define SPI_CFG2_AFCNTR             SPI_CFG2_AFCNTR_Msk                        /*!<Alternate function GPIOs control */

+

+/*******************  Bit definition for SPI_IER register  ********************/

+#define SPI_IER_RXPIE_Pos           (0U)

+#define SPI_IER_RXPIE_Msk           (0x1UL << SPI_IER_RXPIE_Pos)               /*!< 0x00000001 */

+#define SPI_IER_RXPIE               SPI_IER_RXPIE_Msk                          /*!<RXP Interrupt Enable            */

+#define SPI_IER_TXPIE_Pos           (1U)

+#define SPI_IER_TXPIE_Msk           (0x1UL << SPI_IER_TXPIE_Pos)               /*!< 0x00000002 */

+#define SPI_IER_TXPIE               SPI_IER_TXPIE_Msk                          /*!<TXP interrupt enable            */

+#define SPI_IER_DXPIE_Pos           (2U)

+#define SPI_IER_DXPIE_Msk           (0x1UL << SPI_IER_DXPIE_Pos)               /*!< 0x00000004 */

+#define SPI_IER_DXPIE               SPI_IER_DXPIE_Msk                          /*!<DXP interrupt enable            */

+#define SPI_IER_EOTIE_Pos           (3U)

+#define SPI_IER_EOTIE_Msk           (0x1UL << SPI_IER_EOTIE_Pos)               /*!< 0x00000008 */

+#define SPI_IER_EOTIE               SPI_IER_EOTIE_Msk                          /*!<EOT/SUSP/TXC interrupt enable   */

+#define SPI_IER_TXTFIE_Pos          (4U)

+#define SPI_IER_TXTFIE_Msk          (0x1UL << SPI_IER_TXTFIE_Pos)              /*!< 0x00000010 */

+#define SPI_IER_TXTFIE              SPI_IER_TXTFIE_Msk                         /*!<TXTF interrupt enable           */

+#define SPI_IER_UDRIE_Pos           (5U)

+#define SPI_IER_UDRIE_Msk           (0x1UL << SPI_IER_UDRIE_Pos)               /*!< 0x00000020 */

+#define SPI_IER_UDRIE               SPI_IER_UDRIE_Msk                          /*!<UDR interrupt enable            */

+#define SPI_IER_OVRIE_Pos           (6U)

+#define SPI_IER_OVRIE_Msk           (0x1UL << SPI_IER_OVRIE_Pos)               /*!< 0x00000040 */

+#define SPI_IER_OVRIE               SPI_IER_OVRIE_Msk                          /*!<OVR interrupt enable            */

+#define SPI_IER_CRCEIE_Pos          (7U)

+#define SPI_IER_CRCEIE_Msk          (0x1UL << SPI_IER_CRCEIE_Pos)               /*!< 0x00000080 */

+#define SPI_IER_CRCEIE              SPI_IER_CRCEIE_Msk                          /*!<CRCE interrupt enable           */

+#define SPI_IER_TIFREIE_Pos         (8U)

+#define SPI_IER_TIFREIE_Msk         (0x1UL << SPI_IER_TIFREIE_Pos)             /*!< 0x00000100 */

+#define SPI_IER_TIFREIE             SPI_IER_TIFREIE_Msk                        /*!<TI Frame Error interrupt enable */

+#define SPI_IER_MODFIE_Pos          (9U)

+#define SPI_IER_MODFIE_Msk          (0x1UL << SPI_IER_MODFIE_Pos)              /*!< 0x00000200 */

+#define SPI_IER_MODFIE              SPI_IER_MODFIE_Msk                         /*!<MODF interrupt enable           */

+#define SPI_IER_TSERFIE_Pos         (10U)

+#define SPI_IER_TSERFIE_Msk         (0x1UL << SPI_IER_TSERFIE_Pos)              /*!< 0x00000400 */

+#define SPI_IER_TSERFIE             SPI_IER_TSERFIE_Msk                        /*!<TSERF interrupt enable          */

+

+/*******************  Bit definition for SPI_SR register  ********************/

+#define SPI_SR_RXP_Pos              (0U)

+#define SPI_SR_RXP_Msk              (0x1UL << SPI_SR_RXP_Pos)                  /*!< 0x00000001 */

+#define SPI_SR_RXP                  SPI_SR_RXP_Msk                             /*!<Rx-Packet available             */

+#define SPI_SR_TXP_Pos              (1U)

+#define SPI_SR_TXP_Msk              (0x1UL << SPI_SR_TXP_Pos)                  /*!< 0x00000002 */

+#define SPI_SR_TXP                  SPI_SR_TXP_Msk                             /*!<Tx-Packet space available       */

+#define SPI_SR_DXP_Pos              (2U)

+#define SPI_SR_DXP_Msk              (0x1UL << SPI_SR_DXP_Pos)                  /*!< 0x00000004 */

+#define SPI_SR_DXP                  SPI_SR_DXP_Msk                             /*!<Duplex Packet available         */

+#define SPI_SR_EOT_Pos              (3U)

+#define SPI_SR_EOT_Msk              (0x1UL << SPI_SR_EOT_Pos)                  /*!< 0x00000008 */

+#define SPI_SR_EOT                  SPI_SR_EOT_Msk                             /*!<Duplex Packet available         */

+#define SPI_SR_TXTF_Pos             (4U)

+#define SPI_SR_TXTF_Msk             (0x1UL << SPI_SR_TXTF_Pos)                 /*!< 0x00000010 */

+#define SPI_SR_TXTF                 SPI_SR_TXTF_Msk                            /*!<Transmission Transfer Filled    */

+#define SPI_SR_UDR_Pos              (5U)

+#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000020 */

+#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<UDR at Slave transmission       */

+#define SPI_SR_OVR_Pos              (6U)

+#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */

+#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Rx-Packet available             */

+#define SPI_SR_CRCE_Pos             (7U)

+#define SPI_SR_CRCE_Msk             (0x1UL << SPI_SR_CRCE_Pos)                 /*!< 0x00000080 */

+#define SPI_SR_CRCE                 SPI_SR_CRCE_Msk                            /*!<CRC Error Detected              */

+#define SPI_SR_TIFRE_Pos            (8U)

+#define SPI_SR_TIFRE_Msk            (0x1UL << SPI_SR_TIFRE_Pos)                /*!< 0x00000100 */

+#define SPI_SR_TIFRE                SPI_SR_TIFRE_Msk                           /*!<TI frame format error Detected  */

+#define SPI_SR_MODF_Pos             (9U)

+#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000200 */

+#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode Fault Detected             */

+#define SPI_SR_TSERF_Pos            (10U)

+#define SPI_SR_TSERF_Msk            (0x1UL << SPI_SR_TSERF_Pos)                /*!< 0x00000400 */

+#define SPI_SR_TSERF                SPI_SR_TSERF_Msk                           /*!<Number of SPI data to be transacted reloaded     */

+#define SPI_SR_SUSP_Pos             (11U)

+#define SPI_SR_SUSP_Msk             (0x1UL << SPI_SR_SUSP_Pos)                 /*!< 0x00000800 */

+#define SPI_SR_SUSP                 SPI_SR_SUSP_Msk                            /*!<SUSP is set by hardware  */

+#define SPI_SR_TXC_Pos              (12U)

+#define SPI_SR_TXC_Msk              (0x1UL << SPI_SR_TXC_Pos)                  /*!< 0x00001000 */

+#define SPI_SR_TXC                  SPI_SR_TXC_Msk                             /*!<TxFIFO transmission complete */

+#define SPI_SR_RXPLVL_Pos           (13U)

+#define SPI_SR_RXPLVL_Msk           (0x3UL << SPI_SR_RXPLVL_Pos)               /*!< 0x00006000 */

+#define SPI_SR_RXPLVL               SPI_SR_RXPLVL_Msk                          /*!<RxFIFO Packing Level                             */

+#define SPI_SR_RXPLVL_0             (0x1UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00002000 */

+#define SPI_SR_RXPLVL_1             (0x2UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00004000 */

+#define SPI_SR_RXWNE_Pos            (15U)

+#define SPI_SR_RXWNE_Msk            (0x1UL << SPI_SR_RXWNE_Pos)                /*!< 0x00008000 */

+#define SPI_SR_RXWNE                SPI_SR_RXWNE_Msk                           /*!<Rx FIFO Word Not Empty                           */

+#define SPI_SR_CTSIZE_Pos           (16U)

+#define SPI_SR_CTSIZE_Msk           (0xFFFFUL << SPI_SR_CTSIZE_Pos)            /*!< 0xFFFF0000 */

+#define SPI_SR_CTSIZE               SPI_SR_CTSIZE_Msk                          /*!<Number of data frames remaining in TSIZE         */

+

+/*******************  Bit definition for SPI_IFCR register  ********************/

+#define SPI_IFCR_EOTC_Pos           (3U)

+#define SPI_IFCR_EOTC_Msk           (0x1UL << SPI_IFCR_EOTC_Pos)               /*!< 0x00000008 */

+#define SPI_IFCR_EOTC               SPI_IFCR_EOTC_Msk                          /*!<End Of Transfer flag clear              */

+#define SPI_IFCR_TXTFC_Pos          (4U)

+#define SPI_IFCR_TXTFC_Msk          (0x1UL << SPI_IFCR_TXTFC_Pos)              /*!< 0x00000010 */

+#define SPI_IFCR_TXTFC              SPI_IFCR_TXTFC_Msk                         /*!<Transmission Transfer Filled flag clear */

+#define SPI_IFCR_UDRC_Pos           (5U)

+#define SPI_IFCR_UDRC_Msk           (0x1UL << SPI_IFCR_UDRC_Pos)               /*!< 0x00000020 */

+#define SPI_IFCR_UDRC               SPI_IFCR_UDRC_Msk                          /*!<Underrun flag clear                     */

+#define SPI_IFCR_OVRC_Pos           (6U)

+#define SPI_IFCR_OVRC_Msk           (0x1UL << SPI_IFCR_OVRC_Pos)               /*!< 0x00000040 */

+#define SPI_IFCR_OVRC               SPI_IFCR_OVRC_Msk                          /*!<Overrun flag clear                      */

+#define SPI_IFCR_CRCEC_Pos          (7U)

+#define SPI_IFCR_CRCEC_Msk          (0x1UL << SPI_IFCR_CRCEC_Pos)              /*!< 0x00000080 */

+#define SPI_IFCR_CRCEC              SPI_IFCR_CRCEC_Msk                         /*!<CRC Error flag clear                    */

+#define SPI_IFCR_TIFREC_Pos         (8U)

+#define SPI_IFCR_TIFREC_Msk         (0x1UL << SPI_IFCR_TIFREC_Pos)             /*!< 0x00000100 */

+#define SPI_IFCR_TIFREC             SPI_IFCR_TIFREC_Msk                        /*!<TI frame format error flag clear        */

+#define SPI_IFCR_MODFC_Pos          (9U)

+#define SPI_IFCR_MODFC_Msk          (0x1UL << SPI_IFCR_MODFC_Pos)              /*!< 0x00000200 */

+#define SPI_IFCR_MODFC              SPI_IFCR_MODFC_Msk                         /*!<Mode Fault flag clear                   */

+#define SPI_IFCR_TSERFC_Pos         (10U)

+#define SPI_IFCR_TSERFC_Msk         (0x1UL << SPI_IFCR_TSERFC_Pos)             /*!< 0x00000400 */

+#define SPI_IFCR_TSERFC             SPI_IFCR_TSERFC_Msk                        /*!<TSERFC flag clear                       */

+#define SPI_IFCR_SUSPC_Pos          (11U)

+#define SPI_IFCR_SUSPC_Msk          (0x1UL << SPI_IFCR_SUSPC_Pos)              /*!< 0x00000800 */

+#define SPI_IFCR_SUSPC              SPI_IFCR_SUSPC_Msk                         /*!<SUSPend flag clear                      */

+

+/*******************  Bit definition for SPI_TXDR register  ********************/

+#define SPI_TXDR_TXDR_Pos           (0U)

+#define SPI_TXDR_TXDR_Msk           (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)        /*!< 0xFFFFFFFF */

+#define SPI_TXDR_TXDR               SPI_TXDR_TXDR_Msk                          /* Transmit Data Register */

+

+/*******************  Bit definition for SPI_RXDR register  ********************/

+#define SPI_RXDR_RXDR_Pos           (0U)

+#define SPI_RXDR_RXDR_Msk           (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)        /*!< 0xFFFFFFFF */

+#define SPI_RXDR_RXDR               SPI_RXDR_RXDR_Msk                          /* Receive Data Register  */

+

+/*******************  Bit definition for SPI_CRCPOLY register  ********************/

+#define SPI_CRCPOLY_CRCPOLY_Pos     (0U)

+#define SPI_CRCPOLY_CRCPOLY_Msk     (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)  /*!< 0xFFFFFFFF */

+#define SPI_CRCPOLY_CRCPOLY         SPI_CRCPOLY_CRCPOLY_Msk                    /* CRC Polynomial register  */

+

+/*******************  Bit definition for SPI_TXCRC register  ********************/

+#define SPI_TXCRC_TXCRC_Pos         (0U)

+#define SPI_TXCRC_TXCRC_Msk         (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_TXCRC_TXCRC             SPI_TXCRC_TXCRC_Msk                        /* CRCRegister for transmitter */

+

+/*******************  Bit definition for SPI_RXCRC register  ********************/

+#define SPI_RXCRC_RXCRC_Pos         (0U)

+#define SPI_RXCRC_RXCRC_Msk         (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_RXCRC_RXCRC             SPI_RXCRC_RXCRC_Msk                        /* CRCRegister for receiver */

+

+/*******************  Bit definition for SPI_UDRDR register  ********************/

+#define SPI_UDRDR_UDRDR_Pos         (0U)

+#define SPI_UDRDR_UDRDR_Msk         (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_UDRDR_UDRDR             SPI_UDRDR_UDRDR_Msk                        /* Data at slave underrun condition */

+

+/******************  Bit definition for SPI_I2SCFGR register  *****************/

+#define SPI_I2SCFGR_I2SMOD_Pos      (0U)

+#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000001 */

+#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */

+#define SPI_I2SCFGR_I2SCFG_Pos      (1U)

+#define SPI_I2SCFGR_I2SCFG_Msk      (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x0000000E */

+#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[2:0] I2S configuration mode                */

+#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000002 */

+#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000004 */

+#define SPI_I2SCFGR_I2SCFG_2        (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000008 */

+#define SPI_I2SCFGR_I2SSTD_Pos      (4U)

+#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */

+#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] I2S standard selection                */

+#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */

+#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */

+#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)

+#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */

+#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                         */

+#define SPI_I2SCFGR_DATLEN_Pos      (8U)

+#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000300 */

+#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] Data length to be transferred         */

+#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000100 */

+#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000200 */

+#define SPI_I2SCFGR_CHLEN_Pos       (10U)

+#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000400 */

+#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */

+#define SPI_I2SCFGR_CKPOL_Pos       (11U)

+#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000800 */

+#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<Steady state clock polarity                       */

+#define SPI_I2SCFGR_FIXCH_Pos       (12U)

+#define SPI_I2SCFGR_FIXCH_Msk       (0x1UL << SPI_I2SCFGR_FIXCH_Pos)           /*!< 0x00001000 */

+#define SPI_I2SCFGR_FIXCH           SPI_I2SCFGR_FIXCH_Msk                      /*!<Fixed channel length in SLAVE                     */

+#define SPI_I2SCFGR_WSINV_Pos       (13U)

+#define SPI_I2SCFGR_WSINV_Msk       (0x1UL << SPI_I2SCFGR_WSINV_Pos)           /*!< 0x00002000 */

+#define SPI_I2SCFGR_WSINV           SPI_I2SCFGR_WSINV_Msk                      /*!<Word select inversion                             */

+#define SPI_I2SCFGR_DATFMT_Pos      (14U)

+#define SPI_I2SCFGR_DATFMT_Msk      (0x1UL << SPI_I2SCFGR_DATFMT_Pos)          /*!< 0x00004000 */

+#define SPI_I2SCFGR_DATFMT          SPI_I2SCFGR_DATFMT_Msk                     /*!<Data format                                       */

+#define SPI_I2SCFGR_I2SDIV_Pos      (16U)

+#define SPI_I2SCFGR_I2SDIV_Msk      (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)         /*!< 0x00FF0000 */

+#define SPI_I2SCFGR_I2SDIV          SPI_I2SCFGR_I2SDIV_Msk                     /*!<I2S Linear prescaler */

+#define SPI_I2SCFGR_ODD_Pos         (24U)

+#define SPI_I2SCFGR_ODD_Msk         (0x1UL << SPI_I2SCFGR_ODD_Pos)             /*!< 0x01000000 */

+#define SPI_I2SCFGR_ODD             SPI_I2SCFGR_ODD_Msk                        /*!<Odd factor for the prescaler */

+#define SPI_I2SCFGR_MCKOE_Pos       (25U)

+#define SPI_I2SCFGR_MCKOE_Msk       (0x1UL << SPI_I2SCFGR_MCKOE_Pos)           /*!< 0x02000000 */

+#define SPI_I2SCFGR_MCKOE           SPI_I2SCFGR_MCKOE_Msk                      /*!<Master Clock Output Enable */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    QUADSPI                                 */

+/*                                                                            */

+/******************************************************************************/

+/*****************  Bit definition for QUADSPI_CR register  *******************/

+#define QUADSPI_CR_EN_Pos                (0U)

+#define QUADSPI_CR_EN_Msk                (0x1UL << QUADSPI_CR_EN_Pos)          /*!< 0x00000001 */

+#define QUADSPI_CR_EN                    QUADSPI_CR_EN_Msk                     /*!< Enable */

+#define QUADSPI_CR_ABORT_Pos             (1U)

+#define QUADSPI_CR_ABORT_Msk             (0x1UL << QUADSPI_CR_ABORT_Pos)       /*!< 0x00000002 */

+#define QUADSPI_CR_ABORT                 QUADSPI_CR_ABORT_Msk                  /*!< Abort request */

+#define QUADSPI_CR_DMAEN_Pos             (2U)

+#define QUADSPI_CR_DMAEN_Msk             (0x1UL << QUADSPI_CR_DMAEN_Pos)       /*!< 0x00000004 */

+#define QUADSPI_CR_DMAEN                 QUADSPI_CR_DMAEN_Msk                  /*!< DMA Enable */

+#define QUADSPI_CR_TCEN_Pos              (3U)

+#define QUADSPI_CR_TCEN_Msk              (0x1UL << QUADSPI_CR_TCEN_Pos)        /*!< 0x00000008 */

+#define QUADSPI_CR_TCEN                  QUADSPI_CR_TCEN_Msk                   /*!< Timeout Counter Enable */

+#define QUADSPI_CR_SSHIFT_Pos            (4U)

+#define QUADSPI_CR_SSHIFT_Msk            (0x1UL << QUADSPI_CR_SSHIFT_Pos)      /*!< 0x00000010 */

+#define QUADSPI_CR_SSHIFT                QUADSPI_CR_SSHIFT_Msk                 /*!< SSHIFT Sample Shift */

+#define QUADSPI_CR_DFM_Pos               (6U)

+#define QUADSPI_CR_DFM_Msk               (0x1UL << QUADSPI_CR_DFM_Pos)         /*!< 0x00000040 */

+#define QUADSPI_CR_DFM                   QUADSPI_CR_DFM_Msk                    /*!< Dual Flash Mode */

+#define QUADSPI_CR_FSEL_Pos              (7U)

+#define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)        /*!< 0x00000080 */

+#define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select */

+#define QUADSPI_CR_FTHRES_Pos            (8U)

+#define QUADSPI_CR_FTHRES_Msk            (0xFUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000F00 */

+#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level */

+#define QUADSPI_CR_FTHRES_0              (0x1UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */

+#define QUADSPI_CR_FTHRES_1              (0x2UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */

+#define QUADSPI_CR_FTHRES_2              (0x4UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */

+#define QUADSPI_CR_FTHRES_3              (0x8UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */

+#define QUADSPI_CR_TEIE_Pos              (16U)

+#define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)        /*!< 0x00010000 */

+#define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable */

+#define QUADSPI_CR_TCIE_Pos              (17U)

+#define QUADSPI_CR_TCIE_Msk              (0x1UL << QUADSPI_CR_TCIE_Pos)        /*!< 0x00020000 */

+#define QUADSPI_CR_TCIE                  QUADSPI_CR_TCIE_Msk                   /*!< Transfer Complete Interrupt Enable */

+#define QUADSPI_CR_FTIE_Pos              (18U)

+#define QUADSPI_CR_FTIE_Msk              (0x1UL << QUADSPI_CR_FTIE_Pos)        /*!< 0x00040000 */

+#define QUADSPI_CR_FTIE                  QUADSPI_CR_FTIE_Msk                   /*!< FIFO Threshold Interrupt Enable */

+#define QUADSPI_CR_SMIE_Pos              (19U)

+#define QUADSPI_CR_SMIE_Msk              (0x1UL << QUADSPI_CR_SMIE_Pos)        /*!< 0x00080000 */

+#define QUADSPI_CR_SMIE                  QUADSPI_CR_SMIE_Msk                   /*!< Status Match Interrupt Enable */

+#define QUADSPI_CR_TOIE_Pos              (20U)

+#define QUADSPI_CR_TOIE_Msk              (0x1UL << QUADSPI_CR_TOIE_Pos)        /*!< 0x00100000 */

+#define QUADSPI_CR_TOIE                  QUADSPI_CR_TOIE_Msk                   /*!< TimeOut Interrupt Enable */

+#define QUADSPI_CR_APMS_Pos              (22U)

+#define QUADSPI_CR_APMS_Msk              (0x1UL << QUADSPI_CR_APMS_Pos)        /*!< 0x00400000 */

+#define QUADSPI_CR_APMS                  QUADSPI_CR_APMS_Msk                   /*!< Bit 1 */

+#define QUADSPI_CR_PMM_Pos               (23U)

+#define QUADSPI_CR_PMM_Msk               (0x1UL << QUADSPI_CR_PMM_Pos)         /*!< 0x00800000 */

+#define QUADSPI_CR_PMM                   QUADSPI_CR_PMM_Msk                    /*!< Polling Match Mode */

+#define QUADSPI_CR_PRESCALER_Pos         (24U)

+#define QUADSPI_CR_PRESCALER_Msk         (0xFFUL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0xFF000000 */

+#define QUADSPI_CR_PRESCALER             QUADSPI_CR_PRESCALER_Msk              /*!< PRESCALER[7:0] Clock prescaler */

+#define QUADSPI_CR_PRESCALER_0           (0x01UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x01000000 */

+#define QUADSPI_CR_PRESCALER_1           (0x02UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x02000000 */

+#define QUADSPI_CR_PRESCALER_2           (0x04UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x04000000 */

+#define QUADSPI_CR_PRESCALER_3           (0x08UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x08000000 */

+#define QUADSPI_CR_PRESCALER_4           (0x10UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x10000000 */

+#define QUADSPI_CR_PRESCALER_5           (0x20UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x20000000 */

+#define QUADSPI_CR_PRESCALER_6           (0x40UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x40000000 */

+#define QUADSPI_CR_PRESCALER_7           (0x80UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x80000000 */

+

+/*****************  Bit definition for QUADSPI_DCR register  ******************/

+#define QUADSPI_DCR_CKMODE_Pos           (0U)

+#define QUADSPI_DCR_CKMODE_Msk           (0x1UL << QUADSPI_DCR_CKMODE_Pos)     /*!< 0x00000001 */

+#define QUADSPI_DCR_CKMODE               QUADSPI_DCR_CKMODE_Msk                /*!< Mode 0 / Mode 3 */

+#define QUADSPI_DCR_CSHT_Pos             (8U)

+#define QUADSPI_DCR_CSHT_Msk             (0x7UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000700 */

+#define QUADSPI_DCR_CSHT                 QUADSPI_DCR_CSHT_Msk                  /*!< CSHT[2:0]: ChipSelect High Time */

+#define QUADSPI_DCR_CSHT_0               (0x1UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000100 */

+#define QUADSPI_DCR_CSHT_1               (0x2UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000200 */

+#define QUADSPI_DCR_CSHT_2               (0x4UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000400 */

+#define QUADSPI_DCR_FSIZE_Pos            (16U)

+#define QUADSPI_DCR_FSIZE_Msk            (0x1FUL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x001F0000 */

+#define QUADSPI_DCR_FSIZE                QUADSPI_DCR_FSIZE_Msk                 /*!< FSIZE[4:0]: Flash Size */

+#define QUADSPI_DCR_FSIZE_0              (0x01UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00010000 */

+#define QUADSPI_DCR_FSIZE_1              (0x02UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00020000 */

+#define QUADSPI_DCR_FSIZE_2              (0x04UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00040000 */

+#define QUADSPI_DCR_FSIZE_3              (0x08UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00080000 */

+#define QUADSPI_DCR_FSIZE_4              (0x10UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00100000 */

+

+/******************  Bit definition for QUADSPI_SR register  *******************/

+#define QUADSPI_SR_TEF_Pos               (0U)

+#define QUADSPI_SR_TEF_Msk               (0x1UL << QUADSPI_SR_TEF_Pos)         /*!< 0x00000001 */

+#define QUADSPI_SR_TEF                   QUADSPI_SR_TEF_Msk                    /*!< Transfer Error Flag */

+#define QUADSPI_SR_TCF_Pos               (1U)

+#define QUADSPI_SR_TCF_Msk               (0x1UL << QUADSPI_SR_TCF_Pos)         /*!< 0x00000002 */

+#define QUADSPI_SR_TCF                   QUADSPI_SR_TCF_Msk                    /*!< Transfer Complete Flag */

+#define QUADSPI_SR_FTF_Pos               (2U)

+#define QUADSPI_SR_FTF_Msk               (0x1UL << QUADSPI_SR_FTF_Pos)         /*!< 0x00000004 */

+#define QUADSPI_SR_FTF                   QUADSPI_SR_FTF_Msk                    /*!< FIFO Threshlod Flag */

+#define QUADSPI_SR_SMF_Pos               (3U)

+#define QUADSPI_SR_SMF_Msk               (0x1UL << QUADSPI_SR_SMF_Pos)         /*!< 0x00000008 */

+#define QUADSPI_SR_SMF                   QUADSPI_SR_SMF_Msk                    /*!< Status Match Flag */

+#define QUADSPI_SR_TOF_Pos               (4U)

+#define QUADSPI_SR_TOF_Msk               (0x1UL << QUADSPI_SR_TOF_Pos)         /*!< 0x00000010 */

+#define QUADSPI_SR_TOF                   QUADSPI_SR_TOF_Msk                    /*!< Timeout Flag */

+#define QUADSPI_SR_BUSY_Pos              (5U)

+#define QUADSPI_SR_BUSY_Msk              (0x1UL << QUADSPI_SR_BUSY_Pos)        /*!< 0x00000020 */

+#define QUADSPI_SR_BUSY                  QUADSPI_SR_BUSY_Msk                   /*!< Busy */

+#define QUADSPI_SR_FLEVEL_Pos            (8U)

+#define QUADSPI_SR_FLEVEL_Msk            (0x3FUL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00003F00 */

+#define QUADSPI_SR_FLEVEL                QUADSPI_SR_FLEVEL_Msk                 /*!< FIFO Threshlod Flag */

+#define QUADSPI_SR_FLEVEL_0              (0x01UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000100 */

+#define QUADSPI_SR_FLEVEL_1              (0x02UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000200 */

+#define QUADSPI_SR_FLEVEL_2              (0x04UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000400 */

+#define QUADSPI_SR_FLEVEL_3              (0x08UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000800 */

+#define QUADSPI_SR_FLEVEL_4              (0x10UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00001000 */

+#define QUADSPI_SR_FLEVEL_5              (0x20UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00002000 */

+

+/******************  Bit definition for QUADSPI_FCR register  ******************/

+#define QUADSPI_FCR_CTEF_Pos             (0U)

+#define QUADSPI_FCR_CTEF_Msk             (0x1UL << QUADSPI_FCR_CTEF_Pos)       /*!< 0x00000001 */

+#define QUADSPI_FCR_CTEF                 QUADSPI_FCR_CTEF_Msk                  /*!< Clear Transfer Error Flag */

+#define QUADSPI_FCR_CTCF_Pos             (1U)

+#define QUADSPI_FCR_CTCF_Msk             (0x1UL << QUADSPI_FCR_CTCF_Pos)       /*!< 0x00000002 */

+#define QUADSPI_FCR_CTCF                 QUADSPI_FCR_CTCF_Msk                  /*!< Clear Transfer Complete Flag */

+#define QUADSPI_FCR_CSMF_Pos             (3U)

+#define QUADSPI_FCR_CSMF_Msk             (0x1UL << QUADSPI_FCR_CSMF_Pos)       /*!< 0x00000008 */

+#define QUADSPI_FCR_CSMF                 QUADSPI_FCR_CSMF_Msk                  /*!< Clear Status Match Flag */

+#define QUADSPI_FCR_CTOF_Pos             (4U)

+#define QUADSPI_FCR_CTOF_Msk             (0x1UL << QUADSPI_FCR_CTOF_Pos)       /*!< 0x00000010 */

+#define QUADSPI_FCR_CTOF                 QUADSPI_FCR_CTOF_Msk                  /*!< Clear Timeout Flag */

+

+/******************  Bit definition for QUADSPI_DLR register  ******************/

+#define QUADSPI_DLR_DL_Pos               (0U)

+#define QUADSPI_DLR_DL_Msk               (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)  /*!< 0xFFFFFFFF */

+#define QUADSPI_DLR_DL                   QUADSPI_DLR_DL_Msk                    /*!< DL[31:0]: Data Length */

+

+/******************  Bit definition for QUADSPI_CCR register  ******************/

+#define QUADSPI_CCR_INSTRUCTION_Pos      (0U)

+#define QUADSPI_CCR_INSTRUCTION_Msk      (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */

+#define QUADSPI_CCR_INSTRUCTION          QUADSPI_CCR_INSTRUCTION_Msk             /*!< INSTRUCTION[7:0]: Instruction */

+#define QUADSPI_CCR_INSTRUCTION_0        (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */

+#define QUADSPI_CCR_INSTRUCTION_1        (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */

+#define QUADSPI_CCR_INSTRUCTION_2        (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */

+#define QUADSPI_CCR_INSTRUCTION_3        (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */

+#define QUADSPI_CCR_INSTRUCTION_4        (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */

+#define QUADSPI_CCR_INSTRUCTION_5        (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */

+#define QUADSPI_CCR_INSTRUCTION_6        (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */

+#define QUADSPI_CCR_INSTRUCTION_7        (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */

+#define QUADSPI_CCR_IMODE_Pos            (8U)

+#define QUADSPI_CCR_IMODE_Msk            (0x3UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000300 */

+#define QUADSPI_CCR_IMODE                QUADSPI_CCR_IMODE_Msk                   /*!< IMODE[1:0]: Instruction Mode */

+#define QUADSPI_CCR_IMODE_0              (0x1UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000100 */

+#define QUADSPI_CCR_IMODE_1              (0x2UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000200 */

+#define QUADSPI_CCR_ADMODE_Pos           (10U)

+#define QUADSPI_CCR_ADMODE_Msk           (0x3UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000C00 */

+#define QUADSPI_CCR_ADMODE               QUADSPI_CCR_ADMODE_Msk                  /*!< ADMODE[1:0]: Address Mode */

+#define QUADSPI_CCR_ADMODE_0             (0x1UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000400 */

+#define QUADSPI_CCR_ADMODE_1             (0x2UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000800 */

+#define QUADSPI_CCR_ADSIZE_Pos           (12U)

+#define QUADSPI_CCR_ADSIZE_Msk           (0x3UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00003000 */

+#define QUADSPI_CCR_ADSIZE               QUADSPI_CCR_ADSIZE_Msk                  /*!< ADSIZE[1:0]: Address Size */

+#define QUADSPI_CCR_ADSIZE_0             (0x1UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00001000 */

+#define QUADSPI_CCR_ADSIZE_1             (0x2UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00002000 */

+#define QUADSPI_CCR_ABMODE_Pos           (14U)

+#define QUADSPI_CCR_ABMODE_Msk           (0x3UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x0000C000 */

+#define QUADSPI_CCR_ABMODE               QUADSPI_CCR_ABMODE_Msk                  /*!< ABMODE[1:0]: Alternate Bytes Mode */

+#define QUADSPI_CCR_ABMODE_0             (0x1UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00004000 */

+#define QUADSPI_CCR_ABMODE_1             (0x2UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00008000 */

+#define QUADSPI_CCR_ABSIZE_Pos           (16U)

+#define QUADSPI_CCR_ABSIZE_Msk           (0x3UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00030000 */

+#define QUADSPI_CCR_ABSIZE               QUADSPI_CCR_ABSIZE_Msk                  /*!< ABSIZE[1:0]: Instruction Mode */

+#define QUADSPI_CCR_ABSIZE_0             (0x1UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00010000 */

+#define QUADSPI_CCR_ABSIZE_1             (0x2UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00020000 */

+#define QUADSPI_CCR_DCYC_Pos             (18U)

+#define QUADSPI_CCR_DCYC_Msk             (0x1FUL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x007C0000 */

+#define QUADSPI_CCR_DCYC                 QUADSPI_CCR_DCYC_Msk                    /*!< DCYC[4:0]: Dummy Cycles */

+#define QUADSPI_CCR_DCYC_0               (0x01UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00040000 */

+#define QUADSPI_CCR_DCYC_1               (0x02UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00080000 */

+#define QUADSPI_CCR_DCYC_2               (0x04UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00100000 */

+#define QUADSPI_CCR_DCYC_3               (0x08UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00200000 */

+#define QUADSPI_CCR_DCYC_4               (0x10UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00400000 */

+#define QUADSPI_CCR_DMODE_Pos            (24U)

+#define QUADSPI_CCR_DMODE_Msk            (0x3UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x03000000 */

+#define QUADSPI_CCR_DMODE                QUADSPI_CCR_DMODE_Msk                   /*!< DMODE[1:0]: Data Mode */

+#define QUADSPI_CCR_DMODE_0              (0x1UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x01000000 */

+#define QUADSPI_CCR_DMODE_1              (0x2UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x02000000 */

+#define QUADSPI_CCR_FMODE_Pos            (26U)

+#define QUADSPI_CCR_FMODE_Msk            (0x3UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x0C000000 */

+#define QUADSPI_CCR_FMODE                QUADSPI_CCR_FMODE_Msk                   /*!< FMODE[1:0]: Functional Mode */

+#define QUADSPI_CCR_FMODE_0              (0x1UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x04000000 */

+#define QUADSPI_CCR_FMODE_1              (0x2UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x08000000 */

+#define QUADSPI_CCR_SIOO_Pos             (28U)

+#define QUADSPI_CCR_SIOO_Msk             (0x1UL << QUADSPI_CCR_SIOO_Pos)         /*!< 0x10000000 */

+#define QUADSPI_CCR_SIOO                 QUADSPI_CCR_SIOO_Msk                    /*!< SIOO: Send Instruction Only Once Mode */

+#define QUADSPI_CCR_DHHC_Pos             (30U)

+#define QUADSPI_CCR_DHHC_Msk             (0x1UL << QUADSPI_CCR_DHHC_Pos)         /*!< 0x40000000 */

+#define QUADSPI_CCR_DHHC                 QUADSPI_CCR_DHHC_Msk                    /*!< DHHC: DDR hold half cycle */

+#define QUADSPI_CCR_DDRM_Pos             (31U)

+#define QUADSPI_CCR_DDRM_Msk             (0x1UL << QUADSPI_CCR_DDRM_Pos)         /*!< 0x80000000 */

+#define QUADSPI_CCR_DDRM                 QUADSPI_CCR_DDRM_Msk                    /*!< DDRM: Double Data Rate Mode */

+

+/******************  Bit definition for QUADSPI_AR register  *******************/

+#define QUADSPI_AR_ADDRESS_Pos           (0U)

+#define QUADSPI_AR_ADDRESS_Msk           (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_AR_ADDRESS               QUADSPI_AR_ADDRESS_Msk                /*!< ADDRESS[31:0]: Address */

+

+/******************  Bit definition for QUADSPI_ABR register  ******************/

+#define QUADSPI_ABR_ALTERNATE_Pos        (0U)

+#define QUADSPI_ABR_ALTERNATE_Msk        (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_ABR_ALTERNATE            QUADSPI_ABR_ALTERNATE_Msk             /*!< ALTERNATE[31:0]: Alternate Bytes */

+

+/******************  Bit definition for QUADSPI_DR register  *******************/

+#define QUADSPI_DR_DATA_Pos              (0U)

+#define QUADSPI_DR_DATA_Msk              (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_DR_DATA                  QUADSPI_DR_DATA_Msk                   /*!< DATA[31:0]: Data */

+

+/******************  Bit definition for QUADSPI_PSMKR register  ****************/

+#define QUADSPI_PSMKR_MASK_Pos           (0U)

+#define QUADSPI_PSMKR_MASK_Msk           (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_PSMKR_MASK               QUADSPI_PSMKR_MASK_Msk                /*!< MASK[31:0]: Status Mask */

+

+/******************  Bit definition for QUADSPI_PSMAR register  ****************/

+#define QUADSPI_PSMAR_MATCH_Pos          (0U)

+#define QUADSPI_PSMAR_MATCH_Msk          (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_PSMAR_MATCH              QUADSPI_PSMAR_MATCH_Msk               /*!< MATCH[31:0]: Status Match */

+

+/******************  Bit definition for QUADSPI_PIR register  *****************/

+#define QUADSPI_PIR_INTERVAL_Pos         (0U)

+#define QUADSPI_PIR_INTERVAL_Msk         (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */

+#define QUADSPI_PIR_INTERVAL             QUADSPI_PIR_INTERVAL_Msk              /*!< INTERVAL[15:0]: Polling Interval */

+

+/******************  Bit definition for QUADSPI_LPTR register  *****************/

+#define QUADSPI_LPTR_TIMEOUT_Pos         (0U)

+#define QUADSPI_LPTR_TIMEOUT_Msk         (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */

+#define QUADSPI_LPTR_TIMEOUT             QUADSPI_LPTR_TIMEOUT_Msk              /*!< TIMEOUT[15:0]: Timeout period */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                 SYSCFG                                     */

+/*                                                                            */

+/******************************************************************************/

+

+/******************  Bit definition for SYSCFG_PMCR register  ******************/

+#define SYSCFG_PMCR_I2C1_FMP_Pos        (0U)

+#define SYSCFG_PMCR_I2C1_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos)    /*!< 0x00000001 */

+#define SYSCFG_PMCR_I2C1_FMP            SYSCFG_PMCR_I2C1_FMP_Msk               /*!< I2C1 Fast mode plus */

+#define SYSCFG_PMCR_I2C2_FMP_Pos        (1U)

+#define SYSCFG_PMCR_I2C2_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos)    /*!< 0x00000002 */

+#define SYSCFG_PMCR_I2C2_FMP            SYSCFG_PMCR_I2C2_FMP_Msk               /*!< I2C2 Fast mode plus */

+#define SYSCFG_PMCR_I2C3_FMP_Pos        (2U)

+#define SYSCFG_PMCR_I2C3_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos)    /*!< 0x00000004 */

+#define SYSCFG_PMCR_I2C3_FMP            SYSCFG_PMCR_I2C3_FMP_Msk               /*!< I2C3 Fast mode plus */

+#define SYSCFG_PMCR_I2C4_FMP_Pos        (3U)

+#define SYSCFG_PMCR_I2C4_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos)    /*!< 0x00000008 */

+#define SYSCFG_PMCR_I2C4_FMP            SYSCFG_PMCR_I2C4_FMP_Msk               /*!< I2C4 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB6_FMP_Pos     (4U)

+#define SYSCFG_PMCR_I2C_PB6_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */

+#define SYSCFG_PMCR_I2C_PB6_FMP         SYSCFG_PMCR_I2C_PB6_FMP_Msk            /*!< I2C PB6 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB7_FMP_Pos     (5U)

+#define SYSCFG_PMCR_I2C_PB7_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */

+#define SYSCFG_PMCR_I2C_PB7_FMP         SYSCFG_PMCR_I2C_PB7_FMP_Msk            /*!< I2C PB7 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB8_FMP_Pos     (6U)

+#define SYSCFG_PMCR_I2C_PB8_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */

+#define SYSCFG_PMCR_I2C_PB8_FMP         SYSCFG_PMCR_I2C_PB8_FMP_Msk            /*!< I2C PB8 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB9_FMP_Pos     (7U)

+#define SYSCFG_PMCR_I2C_PB9_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */

+#define SYSCFG_PMCR_I2C_PB9_FMP         SYSCFG_PMCR_I2C_PB9_FMP_Msk            /*!< I2C PB9 Fast mode plus */

+#define SYSCFG_PMCR_BOOSTEN_Pos         (8U)

+#define SYSCFG_PMCR_BOOSTEN_Msk         (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos)     /*!< 0x00000100 */

+#define SYSCFG_PMCR_BOOSTEN             SYSCFG_PMCR_BOOSTEN_Msk                /*!< I/O analog switch voltage booster enable */

+

+#define SYSCFG_PMCR_BOOSTVDDSEL_Pos     (9U)

+#define SYSCFG_PMCR_BOOSTVDDSEL_Msk     (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos) /*!< 0x00000200 */

+#define SYSCFG_PMCR_BOOSTVDDSEL         SYSCFG_PMCR_BOOSTVDDSEL_Msk            /*!< Analog switch supply source selection : VDD/VDDA */

+

+#define SYSCFG_PMCR_EPIS_SEL_Pos        (21U)

+#define SYSCFG_PMCR_EPIS_SEL_Msk        (0x7UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00E00000 */

+#define SYSCFG_PMCR_EPIS_SEL            SYSCFG_PMCR_EPIS_SEL_Msk               /*!< Ethernet PHY Interface Selection */

+#define SYSCFG_PMCR_EPIS_SEL_0          (0x1UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00200000 */

+#define SYSCFG_PMCR_EPIS_SEL_1          (0x2UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00400000 */

+#define SYSCFG_PMCR_EPIS_SEL_2          (0x4UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00800000 */

+#define SYSCFG_PMCR_PA0SO_Pos           (24U)

+#define SYSCFG_PMCR_PA0SO_Msk           (0x1UL << SYSCFG_PMCR_PA0SO_Pos)       /*!< 0x01000000 */

+#define SYSCFG_PMCR_PA0SO               SYSCFG_PMCR_PA0SO_Msk                  /*!< PA0 Switch Open */

+#define SYSCFG_PMCR_PA1SO_Pos           (25U)

+#define SYSCFG_PMCR_PA1SO_Msk           (0x1UL << SYSCFG_PMCR_PA1SO_Pos)       /*!< 0x02000000 */

+#define SYSCFG_PMCR_PA1SO               SYSCFG_PMCR_PA1SO_Msk                  /*!< PA1 Switch Open */

+#define SYSCFG_PMCR_PC2SO_Pos           (26U)

+#define SYSCFG_PMCR_PC2SO_Msk           (0x1UL << SYSCFG_PMCR_PC2SO_Pos)       /*!< 0x04000000 */

+#define SYSCFG_PMCR_PC2SO               SYSCFG_PMCR_PC2SO_Msk                  /*!< PC2 Switch Open */

+#define SYSCFG_PMCR_PC3SO_Pos           (27U)

+#define SYSCFG_PMCR_PC3SO_Msk           (0x1UL << SYSCFG_PMCR_PC3SO_Pos)       /*!< 0x08000000 */

+#define SYSCFG_PMCR_PC3SO               SYSCFG_PMCR_PC3SO_Msk                  /*!< PC3 Switch Open */

+

+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/

+#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)

+#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */

+#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)

+#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */

+#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)

+#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000F00 */

+#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */

+#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)

+#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x0000F000 */

+#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */

+/**

+  * @brief   EXTI0 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */

+

+/**

+  * @brief   EXTI1 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */

+/**

+  * @brief   EXTI2 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */

+

+/**

+  * @brief   EXTI3 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/

+#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)

+#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */

+#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)

+#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */

+#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)

+#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000F00 */

+#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */

+#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)

+#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x0000F000 */

+#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */

+/**

+  * @brief   EXTI4 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */

+/**

+  * @brief   EXTI5 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */

+/**

+  * @brief   EXTI6 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */

+

+/**

+  * @brief   EXTI7 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/

+#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)

+#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */

+#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)

+#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */

+#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)

+#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000F00 */

+#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */

+#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)

+#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x0000F000 */

+#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */

+

+/**

+  * @brief   EXTI8 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */

+

+/**

+  * @brief   EXTI9 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */

+

+/**

+  * @brief   EXTI10 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */

+

+/**

+  * @brief   EXTI11 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/

+#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)

+#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x0000000F */

+#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */

+#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)

+#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x000000F0 */

+#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */

+#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)

+#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000F00 */

+#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */

+#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)

+#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x0000F000 */

+#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */

+/**

+  * @brief   EXTI12 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */

+/**

+  * @brief   EXTI13 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */

+/**

+  * @brief   EXTI14 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */

+/**

+  * @brief   EXTI15 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */

+

+/******************  Bit definition for SYSCFG_CFGR register  ******************/

+#define SYSCFG_CFGR_PVDL_Pos            (2U)

+#define SYSCFG_CFGR_PVDL_Msk            (0x1UL << SYSCFG_CFGR_PVDL_Pos)        /*!< 0x00000004 */

+#define SYSCFG_CFGR_PVDL                SYSCFG_CFGR_PVDL_Msk                   /*!<PVD lock enable bit */

+#define SYSCFG_CFGR_FLASHL_Pos          (3U)

+#define SYSCFG_CFGR_FLASHL_Msk          (0x1UL << SYSCFG_CFGR_FLASHL_Pos)      /*!< 0x00000008 */

+#define SYSCFG_CFGR_FLASHL              SYSCFG_CFGR_FLASHL_Msk                 /*!<FLASH double ECC error lock bit */

+#define SYSCFG_CFGR_CM7L_Pos            (6U)

+#define SYSCFG_CFGR_CM7L_Msk            (0x1UL << SYSCFG_CFGR_CM7L_Pos)        /*!< 0x00000040 */

+#define SYSCFG_CFGR_CM7L                SYSCFG_CFGR_CM7L_Msk                   /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */

+#define SYSCFG_CFGR_BKRAML_Pos          (7U)

+#define SYSCFG_CFGR_BKRAML_Msk          (0x1UL << SYSCFG_CFGR_BKRAML_Pos)      /*!< 0x00000080 */

+#define SYSCFG_CFGR_BKRAML              SYSCFG_CFGR_BKRAML_Msk                 /*!<Backup SRAM double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM4L_Pos          (9U)

+#define SYSCFG_CFGR_SRAM4L_Msk          (0x1UL << SYSCFG_CFGR_SRAM4L_Pos)      /*!< 0x00000200 */

+#define SYSCFG_CFGR_SRAM4L              SYSCFG_CFGR_SRAM4L_Msk                 /*!<SRAM4 double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM3L_Pos          (10U)

+#define SYSCFG_CFGR_SRAM3L_Msk          (0x1UL << SYSCFG_CFGR_SRAM3L_Pos)      /*!< 0x00000400 */

+#define SYSCFG_CFGR_SRAM3L              SYSCFG_CFGR_SRAM3L_Msk                 /*!<SRAM3 double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM2L_Pos          (11U)

+#define SYSCFG_CFGR_SRAM2L_Msk          (0x1UL << SYSCFG_CFGR_SRAM2L_Pos)      /*!< 0x00000800 */

+#define SYSCFG_CFGR_SRAM2L              SYSCFG_CFGR_SRAM2L_Msk                 /*!<SRAM2 double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM1L_Pos          (12U)

+#define SYSCFG_CFGR_SRAM1L_Msk          (0x1UL << SYSCFG_CFGR_SRAM1L_Pos)      /*!< 0x00001000 */

+#define SYSCFG_CFGR_SRAM1L              SYSCFG_CFGR_SRAM1L_Msk                 /*!<SRAM1 double ECC error lock bit */

+#define SYSCFG_CFGR_DTCML_Pos           (13U)

+#define SYSCFG_CFGR_DTCML_Msk           (0x1UL << SYSCFG_CFGR_DTCML_Pos)       /*!< 0x00002000 */

+#define SYSCFG_CFGR_DTCML               SYSCFG_CFGR_DTCML_Msk                  /*!<DTCM double ECC error lock bit */

+#define SYSCFG_CFGR_ITCML_Pos           (14U)

+#define SYSCFG_CFGR_ITCML_Msk           (0x1UL << SYSCFG_CFGR_ITCML_Pos)       /*!< 0x00004000 */

+#define SYSCFG_CFGR_ITCML               SYSCFG_CFGR_ITCML_Msk                  /*!<ITCM double ECC error lock bit */

+#define SYSCFG_CFGR_AXISRAML_Pos        (15U)

+#define SYSCFG_CFGR_AXISRAML_Msk        (0x1UL << SYSCFG_CFGR_AXISRAML_Pos)    /*!< 0x00008000 */

+#define SYSCFG_CFGR_AXISRAML            SYSCFG_CFGR_AXISRAML_Msk               /*!<AXISRAM double ECC error lock bit */

+

+/******************  Bit definition for SYSCFG_CCCSR register  ******************/

+#define SYSCFG_CCCSR_EN_Pos             (0U)

+#define SYSCFG_CCCSR_EN_Msk             (0x1UL << SYSCFG_CCCSR_EN_Pos)         /*!< 0x00000001 */

+#define SYSCFG_CCCSR_EN                 SYSCFG_CCCSR_EN_Msk                    /*!< I/O compensation cell enable */

+#define SYSCFG_CCCSR_CS_Pos             (1U)

+#define SYSCFG_CCCSR_CS_Msk             (0x1UL << SYSCFG_CCCSR_CS_Pos)         /*!< 0x00000002 */

+#define SYSCFG_CCCSR_CS                 SYSCFG_CCCSR_CS_Msk                    /*!< I/O compensation cell code selection */

+#define SYSCFG_CCCSR_READY_Pos          (8U)

+#define SYSCFG_CCCSR_READY_Msk          (0x1UL << SYSCFG_CCCSR_READY_Pos)      /*!< 0x00000100 */

+#define SYSCFG_CCCSR_READY              SYSCFG_CCCSR_READY_Msk                 /*!< I/O compensation cell ready flag */

+#define SYSCFG_CCCSR_HSLV_Pos           (16U)

+#define SYSCFG_CCCSR_HSLV_Msk           (0x1UL << SYSCFG_CCCSR_HSLV_Pos)       /*!< 0x00010000 */

+#define SYSCFG_CCCSR_HSLV               SYSCFG_CCCSR_HSLV_Msk                  /*!< High-speed at low-voltage */

+

+/******************  Bit definition for SYSCFG_CCVR register  *******************/

+#define SYSCFG_CCVR_NCV_Pos             (0U)

+#define SYSCFG_CCVR_NCV_Msk             (0xFUL << SYSCFG_CCVR_NCV_Pos)         /*!< 0x0000000F */

+#define SYSCFG_CCVR_NCV                 SYSCFG_CCVR_NCV_Msk                    /*!< NMOS compensation value */

+#define SYSCFG_CCVR_PCV_Pos             (4U)

+#define SYSCFG_CCVR_PCV_Msk             (0xFUL << SYSCFG_CCVR_PCV_Pos)         /*!< 0x000000F0 */

+#define SYSCFG_CCVR_PCV                 SYSCFG_CCVR_PCV_Msk                    /*!< PMOS compensation value */

+

+/******************  Bit definition for SYSCFG_CCCR register  *******************/

+#define SYSCFG_CCCR_NCC_Pos             (0U)

+#define SYSCFG_CCCR_NCC_Msk             (0xFUL << SYSCFG_CCCR_NCC_Pos)         /*!< 0x0000000F */

+#define SYSCFG_CCCR_NCC                 SYSCFG_CCCR_NCC_Msk                    /*!< NMOS compensation code */

+#define SYSCFG_CCCR_PCC_Pos             (4U)

+#define SYSCFG_CCCR_PCC_Msk             (0xFUL << SYSCFG_CCCR_PCC_Pos)         /*!< 0x000000F0 */

+#define SYSCFG_CCCR_PCC                 SYSCFG_CCCR_PCC_Msk                    /*!< PMOS compensation code */

+/******************  Bit definition for SYSCFG_PWRCR register  *******************/

+#define SYSCFG_PWRCR_ODEN_Pos           (0U)

+#define SYSCFG_PWRCR_ODEN_Msk           (0x1UL << SYSCFG_PWRCR_ODEN_Pos)         /*!< 0x00000001 */

+#define SYSCFG_PWRCR_ODEN               SYSCFG_PWRCR_ODEN_Msk                    /*!< PWR overdrive enable */

+

+/******************  Bit definition for SYSCFG_PKGR register  *******************/

+#define SYSCFG_PKGR_PKG_Pos             (0U)

+#define SYSCFG_PKGR_PKG_Msk             (0xFUL << SYSCFG_PKGR_PKG_Pos)         /*!< 0x0000000F */

+#define SYSCFG_PKGR_PKG                 SYSCFG_PKGR_PKG_Msk                    /*!< Package type */

+

+/******************  Bit definition for SYSCFG_UR0 register  *******************/

+#define SYSCFG_UR0_BKS_Pos              (0U)

+#define SYSCFG_UR0_BKS_Msk              (0x1UL << SYSCFG_UR0_BKS_Pos)          /*!< 0x00000001 */

+#define SYSCFG_UR0_BKS                  SYSCFG_UR0_BKS_Msk                     /*!< Bank Swap */

+#define SYSCFG_UR0_RDP_Pos              (16U)

+#define SYSCFG_UR0_RDP_Msk              (0xFFUL << SYSCFG_UR0_RDP_Pos)         /*!< 0x00FF0000 */

+#define SYSCFG_UR0_RDP                  SYSCFG_UR0_RDP_Msk                     /*!< Readout protection */

+

+/******************  Bit definition for SYSCFG_UR2 register  *******************/

+#define SYSCFG_UR2_BORH_Pos             (0U)

+#define SYSCFG_UR2_BORH_Msk             (0x3UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000003 */

+#define SYSCFG_UR2_BORH                 SYSCFG_UR2_BORH_Msk                    /*!< Brown Out Reset High level */

+#define SYSCFG_UR2_BORH_0               (0x1UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000001 */

+#define SYSCFG_UR2_BORH_1               (0x2UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000002 */

+#define SYSCFG_UR2_BOOT_ADD0_Pos        (16U)

+#define SYSCFG_UR2_BOOT_ADD0_Msk        (0xFFFFUL << SYSCFG_UR2_BOOT_ADD0_Pos) /*!< 0xFFFF0000 */

+#define SYSCFG_UR2_BOOT_ADD0            SYSCFG_UR2_BOOT_ADD0_Msk               /*!< Core Boot Address 0 */

+/******************  Bit definition for SYSCFG_UR3 register  *******************/

+#define SYSCFG_UR3_BOOT_ADD1_Pos        (0U)

+#define SYSCFG_UR3_BOOT_ADD1_Msk        (0xFFFFUL << SYSCFG_UR3_BOOT_ADD1_Pos) /*!< 0x0000FFFF */

+#define SYSCFG_UR3_BOOT_ADD1            SYSCFG_UR3_BOOT_ADD1_Msk               /*!< Core Boot Address 1 */

+

+  /******************  Bit definition for SYSCFG_UR4 register  *******************/

+

+#define SYSCFG_UR4_MEPAD_BANK1_Pos      (16U)

+#define SYSCFG_UR4_MEPAD_BANK1_Msk      (0x1UL << SYSCFG_UR4_MEPAD_BANK1_Pos)  /*!< 0x00010000 */

+#define SYSCFG_UR4_MEPAD_BANK1          SYSCFG_UR4_MEPAD_BANK1_Msk             /*!< Mass Erase Protected Area Disabled for bank 1 */

+

+/******************  Bit definition for SYSCFG_UR5 register  *******************/

+#define SYSCFG_UR5_MESAD_BANK1_Pos      (0U)

+#define SYSCFG_UR5_MESAD_BANK1_Msk      (0x1UL << SYSCFG_UR5_MESAD_BANK1_Pos)  /*!< 0x00000001 */

+#define SYSCFG_UR5_MESAD_BANK1          SYSCFG_UR5_MESAD_BANK1_Msk             /*!< Mass erase secured area disabled for bank 1 */

+#define SYSCFG_UR5_WRPN_BANK1_Pos       (16U)

+#define SYSCFG_UR5_WRPN_BANK1_Msk       (0xFFUL << SYSCFG_UR5_WRPN_BANK1_Pos)  /*!< 0x00FF0000 */

+#define SYSCFG_UR5_WRPN_BANK1           SYSCFG_UR5_WRPN_BANK1_Msk              /*!< Write protection for flash bank 1 */

+

+/******************  Bit definition for SYSCFG_UR6 register  *******************/

+#define SYSCFG_UR6_PABEG_BANK1_Pos      (0U)

+#define SYSCFG_UR6_PABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PABEG_BANK1_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR6_PABEG_BANK1          SYSCFG_UR6_PABEG_BANK1_Msk             /*!< Protected area start address for bank 1 */

+#define SYSCFG_UR6_PAEND_BANK1_Pos      (16U)

+#define SYSCFG_UR6_PAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PAEND_BANK1_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR6_PAEND_BANK1          SYSCFG_UR6_PAEND_BANK1_Msk             /*!< Protected area end address for bank 1 */

+

+/******************  Bit definition for SYSCFG_UR7 register  *******************/

+#define SYSCFG_UR7_SABEG_BANK1_Pos      (0U)

+#define SYSCFG_UR7_SABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SABEG_BANK1_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR7_SABEG_BANK1          SYSCFG_UR7_SABEG_BANK1_Msk             /*!< Secured area start address for bank 1 */

+#define SYSCFG_UR7_SAEND_BANK1_Pos      (16U)

+#define SYSCFG_UR7_SAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SAEND_BANK1_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR7_SAEND_BANK1          SYSCFG_UR7_SAEND_BANK1_Msk             /*!< Secured area end address for bank 1 */

+

+/******************  Bit definition for SYSCFG_UR8 register  *******************/

+#define SYSCFG_UR8_MEPAD_BANK2_Pos      (0U)

+#define SYSCFG_UR8_MEPAD_BANK2_Msk      (0x1UL << SYSCFG_UR8_MEPAD_BANK2_Pos)  /*!< 0x00000001 */

+#define SYSCFG_UR8_MEPAD_BANK2          SYSCFG_UR8_MEPAD_BANK2_Msk             /*!< Mass erase Protected area disabled for bank 2 */

+#define SYSCFG_UR8_MESAD_BANK2_Pos      (16U)

+#define SYSCFG_UR8_MESAD_BANK2_Msk      (0x1UL << SYSCFG_UR8_MESAD_BANK2_Pos)  /*!< 0x00010000 */

+#define SYSCFG_UR8_MESAD_BANK2          SYSCFG_UR8_MESAD_BANK2_Msk             /*!< Mass Erase Secured Area Disabled for bank 2 */

+

+/******************  Bit definition for SYSCFG_UR9 register  *******************/

+#define SYSCFG_UR9_WRPN_BANK2_Pos       (0U)

+#define SYSCFG_UR9_WRPN_BANK2_Msk       (0xFFUL << SYSCFG_UR9_WRPN_BANK2_Pos)  /*!< 0x000000FF */

+#define SYSCFG_UR9_WRPN_BANK2           SYSCFG_UR9_WRPN_BANK2_Msk              /*!< Write protection for flash bank 2 */

+#define SYSCFG_UR9_PABEG_BANK2_Pos      (16U)

+#define SYSCFG_UR9_PABEG_BANK2_Msk      (0xFFFUL << SYSCFG_UR9_PABEG_BANK2_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR9_PABEG_BANK2          SYSCFG_UR9_PABEG_BANK2_Msk             /*!< Protected area start address for bank 2 */

+

+/******************  Bit definition for SYSCFG_UR10 register  *******************/

+#define SYSCFG_UR10_PAEND_BANK2_Pos     (0U)

+#define SYSCFG_UR10_PAEND_BANK2_Msk     (0xFFFUL << SYSCFG_UR10_PAEND_BANK2_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR10_PAEND_BANK2         SYSCFG_UR10_PAEND_BANK2_Msk            /*!< Protected area end address for bank 2 */

+#define SYSCFG_UR10_SABEG_BANK2_Pos     (16U)

+#define SYSCFG_UR10_SABEG_BANK2_Msk     (0xFFFUL << SYSCFG_UR10_SABEG_BANK2_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR10_SABEG_BANK2         SYSCFG_UR10_SABEG_BANK2_Msk            /*!< Secured area start address for bank 2 */

+

+/******************  Bit definition for SYSCFG_UR11 register  *******************/

+#define SYSCFG_UR11_SAEND_BANK2_Pos     (0U)

+#define SYSCFG_UR11_SAEND_BANK2_Msk     (0xFFFUL << SYSCFG_UR11_SAEND_BANK2_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR11_SAEND_BANK2         SYSCFG_UR11_SAEND_BANK2_Msk            /*!< Secured area end address for bank 2 */

+#define SYSCFG_UR11_IWDG1M_Pos          (16U)

+#define SYSCFG_UR11_IWDG1M_Msk          (0x1UL << SYSCFG_UR11_IWDG1M_Pos)      /*!< 0x00010000 */

+#define SYSCFG_UR11_IWDG1M              SYSCFG_UR11_IWDG1M_Msk                 /*!< Independent Watchdog 1 mode (SW or HW) */

+

+/******************  Bit definition for SYSCFG_UR12 register  *******************/

+

+#define SYSCFG_UR12_SECURE_Pos          (16U)

+#define SYSCFG_UR12_SECURE_Msk          (0x1UL << SYSCFG_UR12_SECURE_Pos)      /*!< 0x00010000 */

+#define SYSCFG_UR12_SECURE              SYSCFG_UR12_SECURE_Msk                 /*!< Secure mode status */

+

+/******************  Bit definition for SYSCFG_UR13 register  *******************/

+#define SYSCFG_UR13_SDRS_Pos            (0U)

+#define SYSCFG_UR13_SDRS_Msk            (0x3UL << SYSCFG_UR13_SDRS_Pos)        /*!< 0x00000003 */

+#define SYSCFG_UR13_SDRS                SYSCFG_UR13_SDRS_Msk                   /*!< Secured DTCM RAM Size */

+#define SYSCFG_UR13_D1SBRST_Pos         (16U)

+#define SYSCFG_UR13_D1SBRST_Msk         (0x1UL << SYSCFG_UR13_D1SBRST_Pos)     /*!< 0x00010000 */

+#define SYSCFG_UR13_D1SBRST             SYSCFG_UR13_D1SBRST_Msk                /*!< D1 Standby reset */

+

+/******************  Bit definition for SYSCFG_UR14 register  *******************/

+#define SYSCFG_UR14_D1STPRST_Pos        (0U)

+#define SYSCFG_UR14_D1STPRST_Msk        (0x1UL << SYSCFG_UR14_D1STPRST_Pos)    /*!< 0x00000001 */

+#define SYSCFG_UR14_D1STPRST            SYSCFG_UR14_D1STPRST_Msk               /*!< D1 Stop Reset */

+

+/******************  Bit definition for SYSCFG_UR15 register  *******************/

+#define SYSCFG_UR15_FZIWDGSTB_Pos       (16U)

+#define SYSCFG_UR15_FZIWDGSTB_Msk       (0x1UL << SYSCFG_UR15_FZIWDGSTB_Pos)   /*!< 0x00010000 */

+#define SYSCFG_UR15_FZIWDGSTB           SYSCFG_UR15_FZIWDGSTB_Msk              /*!< Freeze independent watchdogs in Standby mode */

+

+/******************  Bit definition for SYSCFG_UR16 register  *******************/

+#define SYSCFG_UR16_FZIWDGSTP_Pos       (0U)

+#define SYSCFG_UR16_FZIWDGSTP_Msk       (0x1UL << SYSCFG_UR16_FZIWDGSTP_Pos)   /*!< 0x00000001 */

+#define SYSCFG_UR16_FZIWDGSTP           SYSCFG_UR16_FZIWDGSTP_Msk              /*!< Freeze independent watchdogs in Stop mode */

+#define SYSCFG_UR16_PKP_Pos             (16U)

+#define SYSCFG_UR16_PKP_Msk             (0x1UL << SYSCFG_UR16_PKP_Pos)         /*!< 0x00010000 */

+#define SYSCFG_UR16_PKP                 SYSCFG_UR16_PKP_Msk                    /*!< Private key programmed */

+

+/******************  Bit definition for SYSCFG_UR17 register  *******************/

+#define SYSCFG_UR17_IOHSLV_Pos          (0U)

+#define SYSCFG_UR17_IOHSLV_Msk          (0x1UL << SYSCFG_UR17_IOHSLV_Pos)      /*!< 0x00000001 */

+#define SYSCFG_UR17_IOHSLV              SYSCFG_UR17_IOHSLV_Msk                 /*!< I/O high speed / low voltage */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    TIM                                     */

+/*                                                                            */

+/******************************************************************************/

+#define TIM_BREAK_INPUT_SUPPORT             /*!<TIM Break input feature */

+

+/*******************  Bit definition for TIM_CR1 register  ********************/

+#define TIM_CR1_CEN_Pos           (0U)

+#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */

+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */

+#define TIM_CR1_UDIS_Pos          (1U)

+#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */

+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */

+#define TIM_CR1_URS_Pos           (2U)

+#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */

+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */

+#define TIM_CR1_OPM_Pos           (3U)

+#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */

+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */

+#define TIM_CR1_DIR_Pos           (4U)

+#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */

+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */

+

+#define TIM_CR1_CMS_Pos           (5U)

+#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */

+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */

+#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */

+#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */

+

+#define TIM_CR1_ARPE_Pos          (7U)

+#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */

+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */

+

+#define TIM_CR1_CKD_Pos           (8U)

+#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */

+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */

+#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */

+#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */

+

+#define TIM_CR1_UIFREMAP_Pos      (11U)

+#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */

+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */

+

+/*******************  Bit definition for TIM_CR2 register  ********************/

+#define TIM_CR2_CCPC_Pos          (0U)

+#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */

+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */

+#define TIM_CR2_CCUS_Pos          (2U)

+#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */

+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */

+#define TIM_CR2_CCDS_Pos          (3U)

+#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */

+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */

+

+#define TIM_CR2_MMS_Pos           (4U)

+#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */

+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */

+#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */

+#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */

+#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */

+

+#define TIM_CR2_TI1S_Pos          (7U)

+#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */

+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */

+#define TIM_CR2_OIS1_Pos          (8U)

+#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */

+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */

+#define TIM_CR2_OIS1N_Pos         (9U)

+#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */

+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */

+#define TIM_CR2_OIS2_Pos          (10U)

+#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */

+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */

+#define TIM_CR2_OIS2N_Pos         (11U)

+#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */

+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */

+#define TIM_CR2_OIS3_Pos          (12U)

+#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */

+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */

+#define TIM_CR2_OIS3N_Pos         (13U)

+#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */

+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */

+#define TIM_CR2_OIS4_Pos          (14U)

+#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */

+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */

+#define TIM_CR2_OIS5_Pos          (16U)

+#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */

+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */

+#define TIM_CR2_OIS6_Pos          (17U)

+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */

+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */

+

+#define TIM_CR2_MMS2_Pos          (20U)

+#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */

+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */

+#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */

+#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */

+#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */

+#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */

+

+/*******************  Bit definition for TIM_SMCR register  *******************/

+#define TIM_SMCR_SMS_Pos          (0U)

+#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */

+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */

+#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */

+#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */

+#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */

+#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */

+

+#define TIM_SMCR_TS_Pos           (4U)

+#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */

+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[4:0] bits (Trigger selection) */

+#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)                /*!< 0x00000010 */

+#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)                /*!< 0x00000020 */

+#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)                /*!< 0x00000040 */

+#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)                /*!< 0x00100000 */

+#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)                /*!< 0x00200000 */

+

+#define TIM_SMCR_MSM_Pos          (7U)

+#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */

+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */

+

+#define TIM_SMCR_ETF_Pos          (8U)

+#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */

+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */

+#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */

+#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */

+#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */

+#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */

+

+#define TIM_SMCR_ETPS_Pos         (12U)

+#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */

+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */

+#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */

+#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */

+

+#define TIM_SMCR_ECE_Pos          (14U)

+#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */

+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */

+#define TIM_SMCR_ETP_Pos          (15U)

+#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */

+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */

+

+/*******************  Bit definition for TIM_DIER register  *******************/

+#define TIM_DIER_UIE_Pos          (0U)

+#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */

+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */

+#define TIM_DIER_CC1IE_Pos        (1U)

+#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */

+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */

+#define TIM_DIER_CC2IE_Pos        (2U)

+#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */

+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */

+#define TIM_DIER_CC3IE_Pos        (3U)

+#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */

+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */

+#define TIM_DIER_CC4IE_Pos        (4U)

+#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */

+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */

+#define TIM_DIER_COMIE_Pos        (5U)

+#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */

+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */

+#define TIM_DIER_TIE_Pos          (6U)

+#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */

+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */

+#define TIM_DIER_BIE_Pos          (7U)

+#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */

+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */

+#define TIM_DIER_UDE_Pos          (8U)

+#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */

+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */

+#define TIM_DIER_CC1DE_Pos        (9U)

+#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */

+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */

+#define TIM_DIER_CC2DE_Pos        (10U)

+#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */

+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */

+#define TIM_DIER_CC3DE_Pos        (11U)

+#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */

+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */

+#define TIM_DIER_CC4DE_Pos        (12U)

+#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */

+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */

+#define TIM_DIER_COMDE_Pos        (13U)

+#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */

+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */

+#define TIM_DIER_TDE_Pos          (14U)

+#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */

+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */

+

+/********************  Bit definition for TIM_SR register  ********************/

+#define TIM_SR_UIF_Pos            (0U)

+#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */

+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */

+#define TIM_SR_CC1IF_Pos          (1U)

+#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */

+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */

+#define TIM_SR_CC2IF_Pos          (2U)

+#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */

+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */

+#define TIM_SR_CC3IF_Pos          (3U)

+#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */

+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */

+#define TIM_SR_CC4IF_Pos          (4U)

+#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */

+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */

+#define TIM_SR_COMIF_Pos          (5U)

+#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */

+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */

+#define TIM_SR_TIF_Pos            (6U)

+#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */

+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */

+#define TIM_SR_BIF_Pos            (7U)

+#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */

+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */

+#define TIM_SR_B2IF_Pos           (8U)

+#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */

+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break2 interrupt Flag */

+#define TIM_SR_CC1OF_Pos          (9U)

+#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */

+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */

+#define TIM_SR_CC2OF_Pos          (10U)

+#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */

+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */

+#define TIM_SR_CC3OF_Pos          (11U)

+#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */

+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */

+#define TIM_SR_CC4OF_Pos          (12U)

+#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */

+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */

+#define TIM_SR_CC5IF_Pos          (16U)

+#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */

+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */

+#define TIM_SR_CC6IF_Pos          (17U)

+#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */

+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */

+#define TIM_SR_SBIF_Pos           (13U)

+#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */

+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!< System Break Flag */

+

+/*******************  Bit definition for TIM_EGR register  ********************/

+#define TIM_EGR_UG_Pos            (0U)

+#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */

+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */

+#define TIM_EGR_CC1G_Pos          (1U)

+#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */

+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */

+#define TIM_EGR_CC2G_Pos          (2U)

+#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */

+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */

+#define TIM_EGR_CC3G_Pos          (3U)

+#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */

+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */

+#define TIM_EGR_CC4G_Pos          (4U)

+#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */

+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */

+#define TIM_EGR_COMG_Pos          (5U)

+#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */

+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */

+#define TIM_EGR_TG_Pos            (6U)

+#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */

+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */

+#define TIM_EGR_BG_Pos            (7U)

+#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */

+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */

+#define TIM_EGR_B2G_Pos           (8U)

+#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */

+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break Generation */

+

+

+/******************  Bit definition for TIM_CCMR1 register  *******************/

+#define TIM_CCMR1_CC1S_Pos        (0U)

+#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */

+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */

+#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */

+#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */

+

+#define TIM_CCMR1_OC1FE_Pos       (2U)

+#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */

+#define TIM_CCMR1_OC1PE_Pos       (3U)

+#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */

+

+#define TIM_CCMR1_OC1M_Pos        (4U)

+#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */

+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */

+#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */

+#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */

+#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */

+#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR1_OC1CE_Pos       (7U)

+#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */

+

+#define TIM_CCMR1_CC2S_Pos        (8U)

+#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */

+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */

+#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */

+#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */

+

+#define TIM_CCMR1_OC2FE_Pos       (10U)

+#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */

+#define TIM_CCMR1_OC2PE_Pos       (11U)

+#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */

+

+#define TIM_CCMR1_OC2M_Pos        (12U)

+#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */

+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */

+#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */

+#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */

+#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */

+#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */

+

+#define TIM_CCMR1_OC2CE_Pos       (15U)

+#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */

+

+/*----------------------------------------------------------------------------*/

+

+#define TIM_CCMR1_IC1PSC_Pos      (2U)

+#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */

+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */

+#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */

+

+#define TIM_CCMR1_IC1F_Pos        (4U)

+#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */

+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */

+#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */

+

+#define TIM_CCMR1_IC2PSC_Pos      (10U)

+#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */

+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */

+#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */

+

+#define TIM_CCMR1_IC2F_Pos        (12U)

+#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */

+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */

+#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */

+

+/******************  Bit definition for TIM_CCMR2 register  *******************/

+#define TIM_CCMR2_CC3S_Pos        (0U)

+#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */

+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */

+#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */

+#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */

+

+#define TIM_CCMR2_OC3FE_Pos       (2U)

+#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */

+#define TIM_CCMR2_OC3PE_Pos       (3U)

+#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */

+

+#define TIM_CCMR2_OC3M_Pos        (4U)

+#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */

+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */

+#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR2_OC3CE_Pos       (7U)

+#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */

+

+#define TIM_CCMR2_CC4S_Pos        (8U)

+#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */

+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */

+#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */

+#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */

+

+#define TIM_CCMR2_OC4FE_Pos       (10U)

+#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */

+#define TIM_CCMR2_OC4PE_Pos       (11U)

+#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */

+

+#define TIM_CCMR2_OC4M_Pos        (12U)

+#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */

+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */

+#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */

+

+#define TIM_CCMR2_OC4CE_Pos       (15U)

+#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */

+

+/*----------------------------------------------------------------------------*/

+

+#define TIM_CCMR2_IC3PSC_Pos      (2U)

+#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */

+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */

+#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */

+

+#define TIM_CCMR2_IC3F_Pos        (4U)

+#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */

+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */

+#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */

+

+#define TIM_CCMR2_IC4PSC_Pos      (10U)

+#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */

+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */

+#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */

+

+#define TIM_CCMR2_IC4F_Pos        (12U)

+#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */

+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */

+#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */

+

+/*******************  Bit definition for TIM_CCER register  *******************/

+#define TIM_CCER_CC1E_Pos         (0U)

+#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */

+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */

+#define TIM_CCER_CC1P_Pos         (1U)

+#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */

+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */

+#define TIM_CCER_CC1NE_Pos        (2U)

+#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */

+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */

+#define TIM_CCER_CC1NP_Pos        (3U)

+#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */

+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */

+#define TIM_CCER_CC2E_Pos         (4U)

+#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */

+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */

+#define TIM_CCER_CC2P_Pos         (5U)

+#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */

+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */

+#define TIM_CCER_CC2NE_Pos        (6U)

+#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */

+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */

+#define TIM_CCER_CC2NP_Pos        (7U)

+#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */

+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */

+#define TIM_CCER_CC3E_Pos         (8U)

+#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */

+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */

+#define TIM_CCER_CC3P_Pos         (9U)

+#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */

+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */

+#define TIM_CCER_CC3NE_Pos        (10U)

+#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */

+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */

+#define TIM_CCER_CC3NP_Pos        (11U)

+#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */

+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */

+#define TIM_CCER_CC4E_Pos         (12U)

+#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */

+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */

+#define TIM_CCER_CC4P_Pos         (13U)

+#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */

+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */

+#define TIM_CCER_CC4NP_Pos        (15U)

+#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */

+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */

+#define TIM_CCER_CC5E_Pos         (16U)

+#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */

+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */

+#define TIM_CCER_CC5P_Pos         (17U)

+#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */

+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */

+#define TIM_CCER_CC6E_Pos         (20U)

+#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */

+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */

+#define TIM_CCER_CC6P_Pos         (21U)

+#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */

+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */

+/*******************  Bit definition for TIM_CNT register  ********************/

+#define TIM_CNT_CNT_Pos           (0U)

+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */

+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */

+#define TIM_CNT_UIFCPY_Pos        (31U)

+#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */

+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy */

+/*******************  Bit definition for TIM_PSC register  ********************/

+#define TIM_PSC_PSC_Pos           (0U)

+#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */

+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */

+

+/*******************  Bit definition for TIM_ARR register  ********************/

+#define TIM_ARR_ARR_Pos           (0U)

+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */

+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */

+

+/*******************  Bit definition for TIM_RCR register  ********************/

+#define TIM_RCR_REP_Pos           (0U)

+#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                  /*!< 0x000000FF */

+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */

+

+/*******************  Bit definition for TIM_CCR1 register  *******************/

+#define TIM_CCR1_CCR1_Pos         (0U)

+#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */

+

+/*******************  Bit definition for TIM_CCR2 register  *******************/

+#define TIM_CCR2_CCR2_Pos         (0U)

+#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */

+

+/*******************  Bit definition for TIM_CCR3 register  *******************/

+#define TIM_CCR3_CCR3_Pos         (0U)

+#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */

+

+/*******************  Bit definition for TIM_CCR4 register  *******************/

+#define TIM_CCR4_CCR4_Pos         (0U)

+#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */

+

+/*******************  Bit definition for TIM_CCR5 register  *******************/

+#define TIM_CCR5_CCR5_Pos         (0U)

+#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */

+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */

+#define TIM_CCR5_GC5C1_Pos        (29U)

+#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */

+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */

+#define TIM_CCR5_GC5C2_Pos        (30U)

+#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */

+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */

+#define TIM_CCR5_GC5C3_Pos        (31U)

+#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */

+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */

+

+/*******************  Bit definition for TIM_CCR6 register  *******************/

+#define TIM_CCR6_CCR6_Pos         (0U)

+#define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */

+

+/*******************  Bit definition for TIM_BDTR register  *******************/

+#define TIM_BDTR_DTG_Pos          (0U)

+#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */

+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */

+#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */

+#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */

+#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */

+#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */

+#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */

+#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */

+#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */

+#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */

+

+#define TIM_BDTR_LOCK_Pos         (8U)

+#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */

+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */

+#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */

+#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */

+

+#define TIM_BDTR_OSSI_Pos         (10U)

+#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */

+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */

+#define TIM_BDTR_OSSR_Pos         (11U)

+#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */

+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */

+#define TIM_BDTR_BKE_Pos          (12U)

+#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */

+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break1 */

+#define TIM_BDTR_BKP_Pos          (13U)

+#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */

+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break1 */

+#define TIM_BDTR_AOE_Pos          (14U)

+#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */

+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */

+#define TIM_BDTR_MOE_Pos          (15U)

+#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */

+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */

+

+#define TIM_BDTR_BKF_Pos          (16U)

+#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */

+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break1 */

+#define TIM_BDTR_BK2F_Pos         (20U)

+#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */

+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break2 */

+

+#define TIM_BDTR_BK2E_Pos         (24U)

+#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */

+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break2 */

+#define TIM_BDTR_BK2P_Pos         (25U)

+#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */

+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */

+

+/*******************  Bit definition for TIM_DCR register  ********************/

+#define TIM_DCR_DBA_Pos           (0U)

+#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */

+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */

+#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */

+#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */

+#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */

+#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */

+#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */

+

+#define TIM_DCR_DBL_Pos           (8U)

+#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */

+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */

+#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */

+#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */

+#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */

+#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */

+#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */

+

+/*******************  Bit definition for TIM_DMAR register  *******************/

+#define TIM_DMAR_DMAB_Pos         (0U)

+#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */

+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */

+

+/******************  Bit definition for TIM_CCMR3 register  *******************/

+#define TIM_CCMR3_OC5FE_Pos       (2U)

+#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */

+#define TIM_CCMR3_OC5PE_Pos       (3U)

+#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */

+

+#define TIM_CCMR3_OC5M_Pos        (4U)

+#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */

+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */

+#define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR3_OC5CE_Pos       (7U)

+#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */

+

+#define TIM_CCMR3_OC6FE_Pos       (10U)

+#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 4 Fast enable */

+#define TIM_CCMR3_OC6PE_Pos       (11U)

+#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */

+

+#define TIM_CCMR3_OC6M_Pos        (12U)

+#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */

+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */

+#define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */

+

+#define TIM_CCMR3_OC6CE_Pos       (15U)

+#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 4 Clear Enable */

+/*******************  Bit definition for TIM1_AF1 register  *********************/

+#define TIM1_AF1_BKINE_Pos        (0U)

+#define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */

+#define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */

+#define TIM1_AF1_BKCMP1E_Pos      (1U)

+#define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */

+#define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM1_AF1_BKCMP2E_Pos      (2U)

+#define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */

+#define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit */

+#define TIM1_AF1_BKDF1BK0E_Pos    (8U)

+#define TIM1_AF1_BKDF1BK0E_Msk    (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)            /*!< 0x00000100 */

+#define TIM1_AF1_BKDF1BK0E        TIM1_AF1_BKDF1BK0E_Msk                       /*!<BKDF1BK0E Break input DFSDM Break 0 */

+#define TIM1_AF1_BKINP_Pos        (9U)

+#define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */

+#define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */

+#define TIM1_AF1_BKCMP1P_Pos      (10U)

+#define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */

+#define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM1_AF1_BKCMP2P_Pos      (11U)

+#define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */

+#define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */

+

+#define TIM1_AF1_ETRSEL_Pos       (14U)

+#define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */

+#define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */

+#define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00004000 */

+#define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00008000 */

+#define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00010000 */

+#define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM1_AF2 register  *********************/

+#define TIM1_AF2_BK2INE_Pos       (0U)

+#define TIM1_AF2_BK2INE_Msk       (0x1UL << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */

+#define TIM1_AF2_BK2INE           TIM1_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */

+#define TIM1_AF2_BK2CMP1E_Pos     (1U)

+#define TIM1_AF2_BK2CMP1E_Msk     (0x1UL << TIM1_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */

+#define TIM1_AF2_BK2CMP1E         TIM1_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */

+#define TIM1_AF2_BK2CMP2E_Pos     (2U)

+#define TIM1_AF2_BK2CMP2E_Msk     (0x1UL << TIM1_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */

+#define TIM1_AF2_BK2CMP2E         TIM1_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */

+#define TIM1_AF2_BK2DFBK1E_Pos    (8U)

+#define TIM1_AF2_BK2DFBK1E_Msk    (0x1UL << TIM1_AF2_BK2DFBK1E_Pos)            /*!< 0x00000100 */

+#define TIM1_AF2_BK2DFBK1E        TIM1_AF2_BK2DFBK1E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 1 */

+#define TIM1_AF2_BK2INP_Pos       (9U)

+#define TIM1_AF2_BK2INP_Msk       (0x1UL << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */

+#define TIM1_AF2_BK2INP           TIM1_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */

+#define TIM1_AF2_BK2CMP1P_Pos     (10U)

+#define TIM1_AF2_BK2CMP1P_Msk     (0x1UL << TIM1_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */

+#define TIM1_AF2_BK2CMP1P         TIM1_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */

+#define TIM1_AF2_BK2CMP2P_Pos     (11U)

+#define TIM1_AF2_BK2CMP2P_Msk     (0x1UL << TIM1_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */

+#define TIM1_AF2_BK2CMP2P         TIM1_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */

+

+/*******************  Bit definition for TIM_TISEL register  *********************/

+#define TIM_TISEL_TI1SEL_Pos      (0U)

+#define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */

+#define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/

+#define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000001 */

+#define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000002 */

+#define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000004 */

+#define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000008 */

+

+#define TIM_TISEL_TI2SEL_Pos      (8U)

+#define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */

+#define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/

+#define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000100 */

+#define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000200 */

+#define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000400 */

+#define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000800 */

+

+#define TIM_TISEL_TI3SEL_Pos      (16U)

+#define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */

+#define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/

+#define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00010000 */

+#define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00020000 */

+#define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00040000 */

+#define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00080000 */

+

+#define TIM_TISEL_TI4SEL_Pos      (24U)

+#define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */

+#define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/

+#define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x01000000 */

+#define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x02000000 */

+#define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x04000000 */

+#define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x08000000 */

+

+/*******************  Bit definition for TIM8_AF1 register  *********************/

+#define TIM8_AF1_BKINE_Pos        (0U)

+#define TIM8_AF1_BKINE_Msk        (0x1UL << TIM8_AF1_BKINE_Pos)                /*!< 0x00000001 */

+#define TIM8_AF1_BKINE            TIM8_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */

+#define TIM8_AF1_BKCMP1E_Pos      (1U)

+#define TIM8_AF1_BKCMP1E_Msk      (0x1UL << TIM8_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */

+#define TIM8_AF1_BKCMP1E          TIM8_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM8_AF1_BKCMP2E_Pos      (2U)

+#define TIM8_AF1_BKCMP2E_Msk      (0x1UL << TIM8_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */

+#define TIM8_AF1_BKCMP2E          TIM8_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM8_AF1_BKDFBK2E_Pos     (8U)

+#define TIM8_AF1_BKDFBK2E_Msk     (0x1UL << TIM8_AF1_BKDFBK2E_Pos)             /*!< 0x00000100 */

+#define TIM8_AF1_BKDFBK2E         TIM8_AF1_BKDFBK2E_Msk                        /*!<BKDFBK2E Break input DFSDM Break 2 */

+#define TIM8_AF1_BKINP_Pos        (9U)

+#define TIM8_AF1_BKINP_Msk        (0x1UL << TIM8_AF1_BKINP_Pos)                /*!< 0x00000200 */

+#define TIM8_AF1_BKINP            TIM8_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */

+#define TIM8_AF1_BKCMP1P_Pos      (10U)

+#define TIM8_AF1_BKCMP1P_Msk      (0x1UL << TIM8_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */

+#define TIM8_AF1_BKCMP1P          TIM8_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM8_AF1_BKCMP2P_Pos      (11U)

+#define TIM8_AF1_BKCMP2P_Msk      (0x1UL << TIM8_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */

+#define TIM8_AF1_BKCMP2P          TIM8_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */

+

+#define TIM8_AF1_ETRSEL_Pos       (14U)

+#define TIM8_AF1_ETRSEL_Msk       (0xFUL << TIM8_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */

+#define TIM8_AF1_ETRSEL           TIM8_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */

+#define TIM8_AF1_ETRSEL_0         (0x1UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00004000 */

+#define TIM8_AF1_ETRSEL_1         (0x2UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00008000 */

+#define TIM8_AF1_ETRSEL_2         (0x4UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00010000 */

+#define TIM8_AF1_ETRSEL_3         (0x8UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00020000 */

+/*******************  Bit definition for TIM8_AF2 register  *********************/

+#define TIM8_AF2_BK2INE_Pos       (0U)

+#define TIM8_AF2_BK2INE_Msk       (0x1UL << TIM8_AF2_BK2INE_Pos)               /*!< 0x00000001 */

+#define TIM8_AF2_BK2INE           TIM8_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */

+#define TIM8_AF2_BK2CMP1E_Pos     (1U)

+#define TIM8_AF2_BK2CMP1E_Msk     (0x1UL << TIM8_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */

+#define TIM8_AF2_BK2CMP1E         TIM8_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */

+#define TIM8_AF2_BK2CMP2E_Pos     (2U)

+#define TIM8_AF2_BK2CMP2E_Msk     (0x1UL << TIM8_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */

+#define TIM8_AF2_BK2CMP2E         TIM8_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */

+#define TIM8_AF2_BK2DFBK3E_Pos    (8U)

+#define TIM8_AF2_BK2DFBK3E_Msk    (0x1UL << TIM8_AF2_BK2DFBK3E_Pos)            /*!< 0x00000100 */

+#define TIM8_AF2_BK2DFBK3E        TIM8_AF2_BK2DFBK3E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 3 */

+#define TIM8_AF2_BK2INP_Pos       (9U)

+#define TIM8_AF2_BK2INP_Msk       (0x1UL << TIM8_AF2_BK2INP_Pos)               /*!< 0x00000200 */

+#define TIM8_AF2_BK2INP           TIM8_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */

+#define TIM8_AF2_BK2CMP1P_Pos     (10U)

+#define TIM8_AF2_BK2CMP1P_Msk     (0x1UL << TIM8_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */

+#define TIM8_AF2_BK2CMP1P         TIM8_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */

+#define TIM8_AF2_BK2CMP2P_Pos     (11U)

+#define TIM8_AF2_BK2CMP2P_Msk     (0x1UL << TIM8_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */

+#define TIM8_AF2_BK2CMP2P         TIM8_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */

+

+/*******************  Bit definition for TIM2_AF1 register  *********************/

+#define TIM2_AF1_ETRSEL_Pos      (14U)

+#define TIM2_AF1_ETRSEL_Msk      (0xFUL << TIM2_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM2_AF1_ETRSEL          TIM2_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */

+#define TIM2_AF1_ETRSEL_0        (0x1UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM2_AF1_ETRSEL_1        (0x2UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM2_AF1_ETRSEL_2        (0x4UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM2_AF1_ETRSEL_3        (0x8UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM3_AF1 register  *********************/

+#define TIM3_AF1_ETRSEL_Pos      (14U)

+#define TIM3_AF1_ETRSEL_Msk      (0xFUL << TIM3_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM3_AF1_ETRSEL          TIM3_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */

+#define TIM3_AF1_ETRSEL_0        (0x1UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM3_AF1_ETRSEL_1        (0x2UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM3_AF1_ETRSEL_2        (0x4UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM3_AF1_ETRSEL_3        (0x8UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM5_AF1 register  *********************/

+#define TIM5_AF1_ETRSEL_Pos      (14U)

+#define TIM5_AF1_ETRSEL_Msk      (0xFUL << TIM5_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM5_AF1_ETRSEL          TIM5_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */

+#define TIM5_AF1_ETRSEL_0        (0x1UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM5_AF1_ETRSEL_1        (0x2UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM5_AF1_ETRSEL_2        (0x4UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM5_AF1_ETRSEL_3        (0x8UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM15_AF1 register  *********************/

+#define TIM15_AF1_BKINE_Pos        (0U)

+#define TIM15_AF1_BKINE_Msk        (0x1UL << TIM15_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM15_AF1_BKINE            TIM15_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM15_AF1_BKCMP1E_Pos      (1U)

+#define TIM15_AF1_BKCMP1E_Msk      (0x1UL << TIM15_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM15_AF1_BKCMP1E          TIM15_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM15_AF1_BKCMP2E_Pos      (2U)

+#define TIM15_AF1_BKCMP2E_Msk      (0x1UL << TIM15_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM15_AF1_BKCMP2E          TIM15_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM15_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM15_AF1_BKDF1BK2E_Msk    (0x1UL << TIM15_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM15_AF1_BKDF1BK2E        TIM15_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[0] enable */

+#define TIM15_AF1_BKINP_Pos        (9U)

+#define TIM15_AF1_BKINP_Msk        (0x1UL << TIM15_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM15_AF1_BKINP            TIM15_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM15_AF1_BKCMP1P_Pos      (10U)

+#define TIM15_AF1_BKCMP1P_Msk      (0x1UL << TIM15_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM15_AF1_BKCMP1P          TIM15_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM15_AF1_BKCMP2P_Pos      (11U)

+#define TIM15_AF1_BKCMP2P_Msk      (0x1UL << TIM15_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM15_AF1_BKCMP2P          TIM15_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/*******************  Bit definition for TIM16_ register  *********************/

+#define TIM16_AF1_BKINE_Pos        (0U)

+#define TIM16_AF1_BKINE_Msk        (0x1UL << TIM16_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM16_AF1_BKINE            TIM16_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM16_AF1_BKCMP1E_Pos      (1U)

+#define TIM16_AF1_BKCMP1E_Msk      (0x1UL << TIM16_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM16_AF1_BKCMP1E          TIM16_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM16_AF1_BKCMP2E_Pos      (2U)

+#define TIM16_AF1_BKCMP2E_Msk      (0x1UL << TIM16_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM16_AF1_BKCMP2E          TIM16_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM16_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM16_AF1_BKDF1BK2E_Msk    (0x1UL << TIM16_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM16_AF1_BKDF1BK2E        TIM16_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[1] enable */

+#define TIM16_AF1_BKINP_Pos        (9U)

+#define TIM16_AF1_BKINP_Msk        (0x1UL << TIM16_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM16_AF1_BKINP            TIM16_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM16_AF1_BKCMP1P_Pos      (10U)

+#define TIM16_AF1_BKCMP1P_Msk      (0x1UL << TIM16_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM16_AF1_BKCMP1P          TIM16_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM16_AF1_BKCMP2P_Pos      (11U)

+#define TIM16_AF1_BKCMP2P_Msk      (0x1UL << TIM16_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM16_AF1_BKCMP2P          TIM16_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/*******************  Bit definition for TIM17_AF1 register  *********************/

+#define TIM17_AF1_BKINE_Pos        (0U)

+#define TIM17_AF1_BKINE_Msk        (0x1UL << TIM17_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM17_AF1_BKINE            TIM17_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM17_AF1_BKCMP1E_Pos      (1U)

+#define TIM17_AF1_BKCMP1E_Msk      (0x1UL << TIM17_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM17_AF1_BKCMP1E          TIM17_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM17_AF1_BKCMP2E_Pos      (2U)

+#define TIM17_AF1_BKCMP2E_Msk      (0x1UL << TIM17_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM17_AF1_BKCMP2E          TIM17_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM17_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM17_AF1_BKDF1BK2E_Msk    (0x1UL << TIM17_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM17_AF1_BKDF1BK2E        TIM17_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[2] enable */

+#define TIM17_AF1_BKINP_Pos        (9U)

+#define TIM17_AF1_BKINP_Msk        (0x1UL << TIM17_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM17_AF1_BKINP            TIM17_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM17_AF1_BKCMP1P_Pos      (10U)

+#define TIM17_AF1_BKCMP1P_Msk      (0x1UL << TIM17_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM17_AF1_BKCMP1P          TIM17_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM17_AF1_BKCMP2P_Pos      (11U)

+#define TIM17_AF1_BKCMP2P_Msk      (0x1UL << TIM17_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM17_AF1_BKCMP2P          TIM17_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Low Power Timer (LPTTIM)                           */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for LPTIM_ISR register  *******************/

+#define LPTIM_ISR_CMPM_Pos          (0U)

+#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */

+#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */

+#define LPTIM_ISR_ARRM_Pos          (1U)

+#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */

+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */

+#define LPTIM_ISR_EXTTRIG_Pos       (2U)

+#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */

+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */

+#define LPTIM_ISR_CMPOK_Pos         (3U)

+#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */

+#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */

+#define LPTIM_ISR_ARROK_Pos         (4U)

+#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */

+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */

+#define LPTIM_ISR_UP_Pos            (5U)

+#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */

+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */

+#define LPTIM_ISR_DOWN_Pos          (6U)

+#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */

+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */

+

+/******************  Bit definition for LPTIM_ICR register  *******************/

+#define LPTIM_ICR_CMPMCF_Pos        (0U)

+#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */

+#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */

+#define LPTIM_ICR_ARRMCF_Pos        (1U)

+#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */

+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */

+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)

+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */

+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */

+#define LPTIM_ICR_CMPOKCF_Pos       (3U)

+#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */

+#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */

+#define LPTIM_ICR_ARROKCF_Pos       (4U)

+#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */

+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */

+#define LPTIM_ICR_UPCF_Pos          (5U)

+#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */

+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */

+#define LPTIM_ICR_DOWNCF_Pos        (6U)

+#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */

+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */

+

+/******************  Bit definition for LPTIM_IER register ********************/

+#define LPTIM_IER_CMPMIE_Pos        (0U)

+#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */

+#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */

+#define LPTIM_IER_ARRMIE_Pos        (1U)

+#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */

+#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */

+#define LPTIM_IER_EXTTRIGIE_Pos     (2U)

+#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */

+#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */

+#define LPTIM_IER_CMPOKIE_Pos       (3U)

+#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */

+#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */

+#define LPTIM_IER_ARROKIE_Pos       (4U)

+#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */

+#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */

+#define LPTIM_IER_UPIE_Pos          (5U)

+#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */

+#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */

+#define LPTIM_IER_DOWNIE_Pos        (6U)

+#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */

+#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */

+

+/******************  Bit definition for LPTIM_CFGR register *******************/

+#define LPTIM_CFGR_CKSEL_Pos        (0U)

+#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */

+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */

+

+#define LPTIM_CFGR_CKPOL_Pos        (1U)

+#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */

+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */

+#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */

+#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */

+

+#define LPTIM_CFGR_CKFLT_Pos        (3U)

+#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */

+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */

+#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */

+#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */

+

+#define LPTIM_CFGR_TRGFLT_Pos       (6U)

+#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */

+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */

+#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */

+#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */

+

+#define LPTIM_CFGR_PRESC_Pos        (9U)

+#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */

+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */

+#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */

+#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */

+#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */

+

+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)

+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */

+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */

+#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */

+#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */

+#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */

+

+#define LPTIM_CFGR_TRIGEN_Pos       (17U)

+#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */

+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */

+#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */

+#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */

+

+#define LPTIM_CFGR_TIMOUT_Pos       (19U)

+#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */

+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */

+#define LPTIM_CFGR_WAVE_Pos         (20U)

+#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */

+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */

+#define LPTIM_CFGR_WAVPOL_Pos       (21U)

+#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */

+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */

+#define LPTIM_CFGR_PRELOAD_Pos      (22U)

+#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */

+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */

+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)

+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */

+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */

+#define LPTIM_CFGR_ENC_Pos          (24U)

+#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */

+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */

+

+/******************  Bit definition for LPTIM_CR register  ********************/

+#define LPTIM_CR_ENABLE_Pos         (0U)

+#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */

+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */

+#define LPTIM_CR_SNGSTRT_Pos        (1U)

+#define LPTIM_CR_SNGSTRT_Msk        (0x40001UL << LPTIM_CR_SNGSTRT_Pos)        /*!< 0x00080002 */

+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */

+#define LPTIM_CR_CNTSTRT_Pos        (2U)

+#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */

+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */

+#define LPTIM_CR_COUNTRST_Pos       (3U)

+#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */

+#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Timer Counter reset in synchronous mode*/

+#define LPTIM_CR_RSTARE_Pos         (4U)

+#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */

+#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Timer Counter reset after read enable (asynchronously)*/

+

+

+/******************  Bit definition for LPTIM_CMP register  *******************/

+#define LPTIM_CMP_CMP_Pos           (0U)

+#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */

+

+/******************  Bit definition for LPTIM_ARR register  *******************/

+#define LPTIM_ARR_ARR_Pos           (0U)

+#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */

+

+/******************  Bit definition for LPTIM_CNT register  *******************/

+#define LPTIM_CNT_CNT_Pos           (0U)

+#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */

+

+/******************  Bit definition for LPTIM_CFGR2 register  *****************/

+#define LPTIM_CFGR2_IN1SEL_Pos      (0U)

+#define LPTIM_CFGR2_IN1SEL_Msk      (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000003 */

+#define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< IN1SEL[1:0] bits (Remap selection) */

+#define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000001 */

+#define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000002 */

+#define LPTIM_CFGR2_IN2SEL_Pos      (4U)

+#define LPTIM_CFGR2_IN2SEL_Msk      (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000030 */

+#define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< IN2SEL[5:4] bits (Remap selection) */

+#define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000010 */

+#define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000020 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      Analog Comparators (COMP)                             */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for COMP_SR register  ********************/

+#define COMP_SR_C1VAL_Pos            (0U)

+#define COMP_SR_C1VAL_Msk            (0x1UL << COMP_SR_C1VAL_Pos)              /*!< 0x00000001 */

+#define COMP_SR_C1VAL                COMP_SR_C1VAL_Msk

+#define COMP_SR_C2VAL_Pos            (1U)

+#define COMP_SR_C2VAL_Msk            (0x1UL << COMP_SR_C2VAL_Pos)              /*!< 0x00000002 */

+#define COMP_SR_C2VAL                COMP_SR_C2VAL_Msk

+#define COMP_SR_C1IF_Pos             (16U)

+#define COMP_SR_C1IF_Msk             (0x1UL << COMP_SR_C1IF_Pos)               /*!< 0x00010000 */

+#define COMP_SR_C1IF                 COMP_SR_C1IF_Msk

+#define COMP_SR_C2IF_Pos             (17U)

+#define COMP_SR_C2IF_Msk             (0x1UL << COMP_SR_C2IF_Pos)               /*!< 0x00020000 */

+#define COMP_SR_C2IF                 COMP_SR_C2IF_Msk

+/*******************  Bit definition for COMP_ICFR register  ********************/

+#define COMP_ICFR_C1IF_Pos           (16U)

+#define COMP_ICFR_C1IF_Msk           (0x1UL << COMP_ICFR_C1IF_Pos)             /*!< 0x00010000 */

+#define COMP_ICFR_C1IF               COMP_ICFR_C1IF_Msk

+#define COMP_ICFR_C2IF_Pos           (17U)

+#define COMP_ICFR_C2IF_Msk           (0x1UL << COMP_ICFR_C2IF_Pos)             /*!< 0x00020000 */

+#define COMP_ICFR_C2IF               COMP_ICFR_C2IF_Msk

+/*******************  Bit definition for COMP_OR register  ********************/

+#define COMP_OR_AFOPA6_Pos           (0U)

+#define COMP_OR_AFOPA6_Msk           (0x1UL << COMP_OR_AFOPA6_Pos)             /*!< 0x00000001 */

+#define COMP_OR_AFOPA6               COMP_OR_AFOPA6_Msk

+#define COMP_OR_AFOPA8_Pos           (1U)

+#define COMP_OR_AFOPA8_Msk           (0x1UL << COMP_OR_AFOPA8_Pos)             /*!< 0x00000002 */

+#define COMP_OR_AFOPA8               COMP_OR_AFOPA8_Msk

+#define COMP_OR_AFOPB12_Pos          (2U)

+#define COMP_OR_AFOPB12_Msk          (0x1UL << COMP_OR_AFOPB12_Pos)            /*!< 0x00000004 */

+#define COMP_OR_AFOPB12              COMP_OR_AFOPB12_Msk

+#define COMP_OR_AFOPE6_Pos           (3U)

+#define COMP_OR_AFOPE6_Msk           (0x1UL << COMP_OR_AFOPE6_Pos)             /*!< 0x00000008 */

+#define COMP_OR_AFOPE6               COMP_OR_AFOPE6_Msk

+#define COMP_OR_AFOPE15_Pos          (4U)

+#define COMP_OR_AFOPE15_Msk          (0x1UL << COMP_OR_AFOPE15_Pos)            /*!< 0x00000010 */

+#define COMP_OR_AFOPE15              COMP_OR_AFOPE15_Msk

+#define COMP_OR_AFOPG2_Pos           (5U)

+#define COMP_OR_AFOPG2_Msk           (0x1UL << COMP_OR_AFOPG2_Pos)             /*!< 0x00000020 */

+#define COMP_OR_AFOPG2               COMP_OR_AFOPG2_Msk

+#define COMP_OR_AFOPG3_Pos           (6U)

+#define COMP_OR_AFOPG3_Msk           (0x1UL << COMP_OR_AFOPG3_Pos)             /*!< 0x00000040 */

+#define COMP_OR_AFOPG3               COMP_OR_AFOPG3_Msk

+#define COMP_OR_AFOPG4_Pos           (7U)

+#define COMP_OR_AFOPG4_Msk           (0x1UL << COMP_OR_AFOPG4_Pos)             /*!< 0x00000080 */

+#define COMP_OR_AFOPG4               COMP_OR_AFOPG4_Msk

+#define COMP_OR_AFOPI1_Pos           (8U)

+#define COMP_OR_AFOPI1_Msk           (0x1UL << COMP_OR_AFOPI1_Pos)             /*!< 0x00000100 */

+#define COMP_OR_AFOPI1               COMP_OR_AFOPI1_Msk

+#define COMP_OR_AFOPI4_Pos           (9U)

+#define COMP_OR_AFOPI4_Msk           (0x1UL << COMP_OR_AFOPI4_Pos)             /*!< 0x00000200 */

+#define COMP_OR_AFOPI4               COMP_OR_AFOPI4_Msk

+#define COMP_OR_AFOPK2_Pos           (10U)

+#define COMP_OR_AFOPK2_Msk           (0x1UL << COMP_OR_AFOPK2_Pos)             /*!< 0x00000400 */

+#define COMP_OR_AFOPK2               COMP_OR_AFOPK2_Msk

+

+/*!< ******************  Bit definition for COMP_CFGRx register  ********************/

+#define COMP_CFGRx_EN_Pos            (0U)

+#define COMP_CFGRx_EN_Msk            (0x1UL << COMP_CFGRx_EN_Pos)              /*!< 0x00000001 */

+#define COMP_CFGRx_EN                COMP_CFGRx_EN_Msk                         /*!< COMPx enable bit                     */

+#define COMP_CFGRx_BRGEN_Pos         (1U)

+#define COMP_CFGRx_BRGEN_Msk         (0x1UL << COMP_CFGRx_BRGEN_Pos)           /*!< 0x00000002 */

+#define COMP_CFGRx_BRGEN             COMP_CFGRx_BRGEN_Msk                      /*!< COMPx Scaler bridge enable           */

+#define COMP_CFGRx_SCALEN_Pos        (2U)

+#define COMP_CFGRx_SCALEN_Msk        (0x1UL << COMP_CFGRx_SCALEN_Pos)          /*!< 0x00000004 */

+#define COMP_CFGRx_SCALEN            COMP_CFGRx_SCALEN_Msk                     /*!< COMPx Voltage scaler enable bit      */

+#define COMP_CFGRx_POLARITY_Pos      (3U)

+#define COMP_CFGRx_POLARITY_Msk      (0x1UL << COMP_CFGRx_POLARITY_Pos)        /*!< 0x00000008 */

+#define COMP_CFGRx_POLARITY          COMP_CFGRx_POLARITY_Msk                   /*!< COMPx  polarity selection bit        */

+#define COMP_CFGRx_WINMODE_Pos       (4U)

+#define COMP_CFGRx_WINMODE_Msk       (0x1UL << COMP_CFGRx_WINMODE_Pos)         /*!< 0x00000010 */

+#define COMP_CFGRx_WINMODE           COMP_CFGRx_WINMODE_Msk                    /*!< COMPx Windows mode selection bit     */

+#define COMP_CFGRx_ITEN_Pos          (6U)

+#define COMP_CFGRx_ITEN_Msk          (0x1UL << COMP_CFGRx_ITEN_Pos)            /*!< 0x00000040 */

+#define COMP_CFGRx_ITEN              COMP_CFGRx_ITEN_Msk                       /*!< COMPx  interrupt enable              */

+#define COMP_CFGRx_HYST_Pos          (8U)

+#define COMP_CFGRx_HYST_Msk          (0x3UL << COMP_CFGRx_HYST_Pos)            /*!< 0x00000300 */

+#define COMP_CFGRx_HYST              COMP_CFGRx_HYST_Msk                       /*!< COMPx  hysteresis selection bits     */

+#define COMP_CFGRx_HYST_0            (0x1UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000100 */

+#define COMP_CFGRx_HYST_1            (0x2UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000200 */

+#define COMP_CFGRx_PWRMODE_Pos       (12U)

+#define COMP_CFGRx_PWRMODE_Msk       (0x3UL << COMP_CFGRx_PWRMODE_Pos)         /*!< 0x00003000 */

+#define COMP_CFGRx_PWRMODE           COMP_CFGRx_PWRMODE_Msk                    /*!< COMPx Power Mode of the comparator   */

+#define COMP_CFGRx_PWRMODE_0         (0x1UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00001000 */

+#define COMP_CFGRx_PWRMODE_1         (0x2UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00002000 */

+#define COMP_CFGRx_INMSEL_Pos        (16U)

+#define COMP_CFGRx_INMSEL_Msk        (0x7UL << COMP_CFGRx_INMSEL_Pos)          /*!< 0x00070000 */

+#define COMP_CFGRx_INMSEL            COMP_CFGRx_INMSEL_Msk                     /*!< COMPx  input minus selection bit  */

+#define COMP_CFGRx_INMSEL_0          (0x1UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00010000 */

+#define COMP_CFGRx_INMSEL_1          (0x2UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00020000 */

+#define COMP_CFGRx_INMSEL_2          (0x4UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00040000 */

+#define COMP_CFGRx_INPSEL_Pos        (20U)

+#define COMP_CFGRx_INPSEL_Msk        (0x1UL << COMP_CFGRx_INPSEL_Pos)          /*!< 0x00100000 */

+#define COMP_CFGRx_INPSEL            COMP_CFGRx_INPSEL_Msk                     /*!< COMPx  input plus selection bit       */

+#define COMP_CFGRx_BLANKING_Pos      (24U)

+#define COMP_CFGRx_BLANKING_Msk      (0xFUL << COMP_CFGRx_BLANKING_Pos)        /*!< 0x0F000000 */

+#define COMP_CFGRx_BLANKING          COMP_CFGRx_BLANKING_Msk                   /*!< COMPx  blanking source selection bits */

+#define COMP_CFGRx_BLANKING_0        (0x1UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x01000000 */

+#define COMP_CFGRx_BLANKING_1        (0x2UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x02000000 */

+#define COMP_CFGRx_BLANKING_2        (0x4UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x04000000 */

+#define COMP_CFGRx_LOCK_Pos          (31U)

+#define COMP_CFGRx_LOCK_Msk          (0x1UL << COMP_CFGRx_LOCK_Pos)            /*!< 0x80000000 */

+#define COMP_CFGRx_LOCK              COMP_CFGRx_LOCK_Msk                       /*!< COMPx Lock Bit                        */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for USART_CR1 register  *******************/

+#define USART_CR1_UE_Pos                (0U)

+#define USART_CR1_UE_Msk                (0x1UL << USART_CR1_UE_Pos)            /*!< 0x00000001 */

+#define USART_CR1_UE                    USART_CR1_UE_Msk                       /*!< USART Enable */

+#define USART_CR1_UESM_Pos              (1U)

+#define USART_CR1_UESM_Msk              (0x1UL << USART_CR1_UESM_Pos)          /*!< 0x00000002 */

+#define USART_CR1_UESM                  USART_CR1_UESM_Msk                     /*!< USART Enable in STOP Mode */

+#define USART_CR1_RE_Pos                (2U)

+#define USART_CR1_RE_Msk                (0x1UL << USART_CR1_RE_Pos)            /*!< 0x00000004 */

+#define USART_CR1_RE                    USART_CR1_RE_Msk                       /*!< Receiver Enable */

+#define USART_CR1_TE_Pos                (3U)

+#define USART_CR1_TE_Msk                (0x1UL << USART_CR1_TE_Pos)            /*!< 0x00000008 */

+#define USART_CR1_TE                    USART_CR1_TE_Msk                       /*!< Transmitter Enable */

+#define USART_CR1_IDLEIE_Pos            (4U)

+#define USART_CR1_IDLEIE_Msk            (0x1UL << USART_CR1_IDLEIE_Pos)        /*!< 0x00000010 */

+#define USART_CR1_IDLEIE                USART_CR1_IDLEIE_Msk                   /*!< IDLE Interrupt Enable */

+#define USART_CR1_RXNEIE_RXFNEIE_Pos    (5U)

+#define USART_CR1_RXNEIE_RXFNEIE_Msk    (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */

+#define USART_CR1_RXNEIE_RXFNEIE        USART_CR1_RXNEIE_RXFNEIE_Msk           /*!< RXNE and RX FIFO Not Empty Interrupt Enable */

+#define USART_CR1_TCIE_Pos              (6U)

+#define USART_CR1_TCIE_Msk              (0x1UL << USART_CR1_TCIE_Pos)          /*!< 0x00000040 */

+#define USART_CR1_TCIE                  USART_CR1_TCIE_Msk                     /*!< Transmission Complete Interrupt Enable */

+#define USART_CR1_TXEIE_TXFNFIE_Pos     (7U)

+#define USART_CR1_TXEIE_TXFNFIE_Msk     (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */

+#define USART_CR1_TXEIE_TXFNFIE         USART_CR1_TXEIE_TXFNFIE_Msk            /*!< TXE and TX FIFO Not Full Interrupt Enable */

+#define USART_CR1_PEIE_Pos              (8U)

+#define USART_CR1_PEIE_Msk              (0x1UL << USART_CR1_PEIE_Pos)          /*!< 0x00000100 */

+#define USART_CR1_PEIE                  USART_CR1_PEIE_Msk                     /*!< PE Interrupt Enable */

+#define USART_CR1_PS_Pos                (9U)

+#define USART_CR1_PS_Msk                (0x1UL << USART_CR1_PS_Pos)            /*!< 0x00000200 */

+#define USART_CR1_PS                    USART_CR1_PS_Msk                       /*!< Parity Selection */

+#define USART_CR1_PCE_Pos               (10U)

+#define USART_CR1_PCE_Msk               (0x1UL << USART_CR1_PCE_Pos)           /*!< 0x00000400 */

+#define USART_CR1_PCE                   USART_CR1_PCE_Msk                      /*!< Parity Control Enable */

+#define USART_CR1_WAKE_Pos              (11U)

+#define USART_CR1_WAKE_Msk              (0x1UL << USART_CR1_WAKE_Pos)          /*!< 0x00000800 */

+#define USART_CR1_WAKE                  USART_CR1_WAKE_Msk                     /*!< Receiver Wakeup method */

+#define USART_CR1_M_Pos                 (12U)

+#define USART_CR1_M_Msk                 (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */

+#define USART_CR1_M                     USART_CR1_M_Msk                        /*!< Word length */

+#define USART_CR1_M0_Pos                (12U)

+#define USART_CR1_M0_Msk                (0x1UL << USART_CR1_M0_Pos)            /*!< 0x00001000 */

+#define USART_CR1_M0                    USART_CR1_M0_Msk                       /*!< Word length - Bit 0 */

+#define USART_CR1_MME_Pos               (13U)

+#define USART_CR1_MME_Msk               (0x1UL << USART_CR1_MME_Pos)           /*!< 0x00002000 */

+#define USART_CR1_MME                   USART_CR1_MME_Msk                      /*!< Mute Mode Enable */

+#define USART_CR1_CMIE_Pos              (14U)

+#define USART_CR1_CMIE_Msk              (0x1UL << USART_CR1_CMIE_Pos)          /*!< 0x00004000 */

+#define USART_CR1_CMIE                  USART_CR1_CMIE_Msk                     /*!< Character match interrupt enable */

+#define USART_CR1_OVER8_Pos             (15U)

+#define USART_CR1_OVER8_Msk             (0x1UL << USART_CR1_OVER8_Pos)         /*!< 0x00008000 */

+#define USART_CR1_OVER8                 USART_CR1_OVER8_Msk                    /*!< Oversampling by 8-bit or 16-bit mode */

+#define USART_CR1_DEDT_Pos              (16U)

+#define USART_CR1_DEDT_Msk              (0x1FUL << USART_CR1_DEDT_Pos)         /*!< 0x001F0000 */

+#define USART_CR1_DEDT                  USART_CR1_DEDT_Msk                     /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */

+#define USART_CR1_DEDT_0                (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */

+#define USART_CR1_DEDT_1                (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */

+#define USART_CR1_DEDT_2                (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */

+#define USART_CR1_DEDT_3                (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */

+#define USART_CR1_DEDT_4                (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */

+#define USART_CR1_DEAT_Pos              (21U)

+#define USART_CR1_DEAT_Msk              (0x1FUL << USART_CR1_DEAT_Pos)         /*!< 0x03E00000 */

+#define USART_CR1_DEAT                  USART_CR1_DEAT_Msk                     /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */

+#define USART_CR1_DEAT_0                (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */

+#define USART_CR1_DEAT_1                (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */

+#define USART_CR1_DEAT_2                (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */

+#define USART_CR1_DEAT_3                (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */

+#define USART_CR1_DEAT_4                (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */

+#define USART_CR1_RTOIE_Pos             (26U)

+#define USART_CR1_RTOIE_Msk             (0x1UL << USART_CR1_RTOIE_Pos)         /*!< 0x04000000 */

+#define USART_CR1_RTOIE                 USART_CR1_RTOIE_Msk                    /*!< Receive Time Out interrupt enable */

+#define USART_CR1_EOBIE_Pos             (27U)

+#define USART_CR1_EOBIE_Msk             (0x1UL << USART_CR1_EOBIE_Pos)         /*!< 0x08000000 */

+#define USART_CR1_EOBIE                 USART_CR1_EOBIE_Msk                    /*!< End of Block interrupt enable */

+#define USART_CR1_M1_Pos                (28U)

+#define USART_CR1_M1_Msk                (0x1UL << USART_CR1_M1_Pos)            /*!< 0x10000000 */

+#define USART_CR1_M1                    USART_CR1_M1_Msk                       /*!< Word length - Bit 1 */

+#define USART_CR1_FIFOEN_Pos            (29U)

+#define USART_CR1_FIFOEN_Msk            (0x1UL << USART_CR1_FIFOEN_Pos)        /*!< 0x20000000 */

+#define USART_CR1_FIFOEN                USART_CR1_FIFOEN_Msk                   /*!< FIFO mode enable */

+#define USART_CR1_TXFEIE_Pos            (30U)

+#define USART_CR1_TXFEIE_Msk            (0x1UL << USART_CR1_TXFEIE_Pos)        /*!< 0x40000000 */

+#define USART_CR1_TXFEIE                USART_CR1_TXFEIE_Msk                   /*!< TXFIFO empty interrupt enable */

+#define USART_CR1_RXFFIE_Pos            (31U)

+#define USART_CR1_RXFFIE_Msk            (0x1UL << USART_CR1_RXFFIE_Pos)        /*!< 0x80000000 */

+#define USART_CR1_RXFFIE                USART_CR1_RXFFIE_Msk                   /*!< RXFIFO Full interrupt enable */

+

+/* Legacy define */

+#define  USART_CR1_RXNEIE  USART_CR1_RXNEIE_RXFNEIE

+#define  USART_CR1_TXEIE   USART_CR1_TXEIE_TXFNFIE

+

+/******************  Bit definition for USART_CR2 register  *******************/

+#define USART_CR2_SLVEN_Pos             (0U)

+#define USART_CR2_SLVEN_Msk             (0x1UL << USART_CR2_SLVEN_Pos)         /*!< 0x00000001 */

+#define USART_CR2_SLVEN                 USART_CR2_SLVEN_Msk                    /*!< Synchronous Slave mode Enable */

+#define USART_CR2_DIS_NSS_Pos           (3U)

+#define USART_CR2_DIS_NSS_Msk           (0x1UL << USART_CR2_DIS_NSS_Pos)       /*!< 0x00000008 */

+#define USART_CR2_DIS_NSS               USART_CR2_DIS_NSS_Msk                  /*!< Negative Slave Select (NSS) pin management */

+#define USART_CR2_ADDM7_Pos             (4U)

+#define USART_CR2_ADDM7_Msk             (0x1UL << USART_CR2_ADDM7_Pos)         /*!< 0x00000010 */

+#define USART_CR2_ADDM7                 USART_CR2_ADDM7_Msk                    /*!< 7-bit or 4-bit Address Detection */

+#define USART_CR2_LBDL_Pos              (5U)

+#define USART_CR2_LBDL_Msk              (0x1UL << USART_CR2_LBDL_Pos)          /*!< 0x00000020 */

+#define USART_CR2_LBDL                  USART_CR2_LBDL_Msk                     /*!< LIN Break Detection Length */

+#define USART_CR2_LBDIE_Pos             (6U)

+#define USART_CR2_LBDIE_Msk             (0x1UL << USART_CR2_LBDIE_Pos)         /*!< 0x00000040 */

+#define USART_CR2_LBDIE                 USART_CR2_LBDIE_Msk                    /*!< LIN Break Detection Interrupt Enable */

+#define USART_CR2_LBCL_Pos              (8U)

+#define USART_CR2_LBCL_Msk              (0x1UL << USART_CR2_LBCL_Pos)          /*!< 0x00000100 */

+#define USART_CR2_LBCL                  USART_CR2_LBCL_Msk                     /*!< Last Bit Clock pulse */

+#define USART_CR2_CPHA_Pos              (9U)

+#define USART_CR2_CPHA_Msk              (0x1UL << USART_CR2_CPHA_Pos)          /*!< 0x00000200 */

+#define USART_CR2_CPHA                  USART_CR2_CPHA_Msk                     /*!< Clock Phase */

+#define USART_CR2_CPOL_Pos              (10U)

+#define USART_CR2_CPOL_Msk              (0x1UL << USART_CR2_CPOL_Pos)          /*!< 0x00000400 */

+#define USART_CR2_CPOL                  USART_CR2_CPOL_Msk                     /*!< Clock Polarity */

+#define USART_CR2_CLKEN_Pos             (11U)

+#define USART_CR2_CLKEN_Msk             (0x1UL << USART_CR2_CLKEN_Pos)         /*!< 0x00000800 */

+#define USART_CR2_CLKEN                 USART_CR2_CLKEN_Msk                    /*!< Clock Enable */

+#define USART_CR2_STOP_Pos              (12U)

+#define USART_CR2_STOP_Msk              (0x3UL << USART_CR2_STOP_Pos)          /*!< 0x00003000 */

+#define USART_CR2_STOP                  USART_CR2_STOP_Msk                     /*!< STOP[1:0] bits (STOP bits) */

+#define USART_CR2_STOP_0                (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */

+#define USART_CR2_STOP_1                (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */

+#define USART_CR2_LINEN_Pos             (14U)

+#define USART_CR2_LINEN_Msk             (0x1UL << USART_CR2_LINEN_Pos)         /*!< 0x00004000 */

+#define USART_CR2_LINEN                 USART_CR2_LINEN_Msk                    /*!< LIN mode enable */

+#define USART_CR2_SWAP_Pos              (15U)

+#define USART_CR2_SWAP_Msk              (0x1UL << USART_CR2_SWAP_Pos)          /*!< 0x00008000 */

+#define USART_CR2_SWAP                  USART_CR2_SWAP_Msk                     /*!< SWAP TX/RX pins */

+#define USART_CR2_RXINV_Pos             (16U)

+#define USART_CR2_RXINV_Msk             (0x1UL << USART_CR2_RXINV_Pos)         /*!< 0x00010000 */

+#define USART_CR2_RXINV                 USART_CR2_RXINV_Msk                    /*!< RX pin active level inversion */

+#define USART_CR2_TXINV_Pos             (17U)

+#define USART_CR2_TXINV_Msk             (0x1UL << USART_CR2_TXINV_Pos)         /*!< 0x00020000 */

+#define USART_CR2_TXINV                 USART_CR2_TXINV_Msk                    /*!< TX pin active level inversion */

+#define USART_CR2_DATAINV_Pos           (18U)

+#define USART_CR2_DATAINV_Msk           (0x1UL << USART_CR2_DATAINV_Pos)       /*!< 0x00040000 */

+#define USART_CR2_DATAINV               USART_CR2_DATAINV_Msk                  /*!< Binary data inversion */

+#define USART_CR2_MSBFIRST_Pos          (19U)

+#define USART_CR2_MSBFIRST_Msk          (0x1UL << USART_CR2_MSBFIRST_Pos)      /*!< 0x00080000 */

+#define USART_CR2_MSBFIRST              USART_CR2_MSBFIRST_Msk                 /*!< Most Significant Bit First */

+#define USART_CR2_ABREN_Pos             (20U)

+#define USART_CR2_ABREN_Msk             (0x1UL << USART_CR2_ABREN_Pos)         /*!< 0x00100000 */

+#define USART_CR2_ABREN                 USART_CR2_ABREN_Msk                    /*!< Auto Baud-Rate Enable*/

+#define USART_CR2_ABRMODE_Pos           (21U)

+#define USART_CR2_ABRMODE_Msk           (0x3UL << USART_CR2_ABRMODE_Pos)       /*!< 0x00600000 */

+#define USART_CR2_ABRMODE               USART_CR2_ABRMODE_Msk                  /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */

+#define USART_CR2_ABRMODE_0             (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */

+#define USART_CR2_ABRMODE_1             (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */

+#define USART_CR2_RTOEN_Pos             (23U)

+#define USART_CR2_RTOEN_Msk             (0x1UL << USART_CR2_RTOEN_Pos)         /*!< 0x00800000 */

+#define USART_CR2_RTOEN                 USART_CR2_RTOEN_Msk                    /*!< Receiver Time-Out enable */

+#define USART_CR2_ADD_Pos               (24U)

+#define USART_CR2_ADD_Msk               (0xFFUL << USART_CR2_ADD_Pos)          /*!< 0xFF000000 */

+#define USART_CR2_ADD                   USART_CR2_ADD_Msk                      /*!< Address of the USART node */

+

+/******************  Bit definition for USART_CR3 register  *******************/

+#define USART_CR3_EIE_Pos               (0U)

+#define USART_CR3_EIE_Msk               (0x1UL << USART_CR3_EIE_Pos)           /*!< 0x00000001 */

+#define USART_CR3_EIE                   USART_CR3_EIE_Msk                      /*!< Error Interrupt Enable */

+#define USART_CR3_IREN_Pos              (1U)

+#define USART_CR3_IREN_Msk              (0x1UL << USART_CR3_IREN_Pos)          /*!< 0x00000002 */

+#define USART_CR3_IREN                  USART_CR3_IREN_Msk                     /*!< IrDA mode Enable */

+#define USART_CR3_IRLP_Pos              (2U)

+#define USART_CR3_IRLP_Msk              (0x1UL << USART_CR3_IRLP_Pos)          /*!< 0x00000004 */

+#define USART_CR3_IRLP                  USART_CR3_IRLP_Msk                     /*!< IrDA Low-Power */

+#define USART_CR3_HDSEL_Pos             (3U)

+#define USART_CR3_HDSEL_Msk             (0x1UL << USART_CR3_HDSEL_Pos)         /*!< 0x00000008 */

+#define USART_CR3_HDSEL                 USART_CR3_HDSEL_Msk                    /*!< Half-Duplex Selection */

+#define USART_CR3_NACK_Pos              (4U)

+#define USART_CR3_NACK_Msk              (0x1UL << USART_CR3_NACK_Pos)          /*!< 0x00000010 */

+#define USART_CR3_NACK                  USART_CR3_NACK_Msk                     /*!< SmartCard NACK enable */

+#define USART_CR3_SCEN_Pos              (5U)

+#define USART_CR3_SCEN_Msk              (0x1UL << USART_CR3_SCEN_Pos)          /*!< 0x00000020 */

+#define USART_CR3_SCEN                  USART_CR3_SCEN_Msk                     /*!< SmartCard mode enable */

+#define USART_CR3_DMAR_Pos              (6U)

+#define USART_CR3_DMAR_Msk              (0x1UL << USART_CR3_DMAR_Pos)          /*!< 0x00000040 */

+#define USART_CR3_DMAR                  USART_CR3_DMAR_Msk                     /*!< DMA Enable Receiver */

+#define USART_CR3_DMAT_Pos              (7U)

+#define USART_CR3_DMAT_Msk              (0x1UL << USART_CR3_DMAT_Pos)          /*!< 0x00000080 */

+#define USART_CR3_DMAT                  USART_CR3_DMAT_Msk                     /*!< DMA Enable Transmitter */

+#define USART_CR3_RTSE_Pos              (8U)

+#define USART_CR3_RTSE_Msk              (0x1UL << USART_CR3_RTSE_Pos)          /*!< 0x00000100 */

+#define USART_CR3_RTSE                  USART_CR3_RTSE_Msk                     /*!< RTS Enable */

+#define USART_CR3_CTSE_Pos              (9U)

+#define USART_CR3_CTSE_Msk              (0x1UL << USART_CR3_CTSE_Pos)          /*!< 0x00000200 */

+#define USART_CR3_CTSE                  USART_CR3_CTSE_Msk                     /*!< CTS Enable */

+#define USART_CR3_CTSIE_Pos             (10U)

+#define USART_CR3_CTSIE_Msk             (0x1UL << USART_CR3_CTSIE_Pos)         /*!< 0x00000400 */

+#define USART_CR3_CTSIE                 USART_CR3_CTSIE_Msk                    /*!< CTS Interrupt Enable */

+#define USART_CR3_ONEBIT_Pos            (11U)

+#define USART_CR3_ONEBIT_Msk            (0x1UL << USART_CR3_ONEBIT_Pos)        /*!< 0x00000800 */

+#define USART_CR3_ONEBIT                USART_CR3_ONEBIT_Msk                   /*!< One sample bit method enable */

+#define USART_CR3_OVRDIS_Pos            (12U)

+#define USART_CR3_OVRDIS_Msk            (0x1UL << USART_CR3_OVRDIS_Pos)        /*!< 0x00001000 */

+#define USART_CR3_OVRDIS                USART_CR3_OVRDIS_Msk                   /*!< Overrun Disable */

+#define USART_CR3_DDRE_Pos              (13U)

+#define USART_CR3_DDRE_Msk              (0x1UL << USART_CR3_DDRE_Pos)          /*!< 0x00002000 */

+#define USART_CR3_DDRE                  USART_CR3_DDRE_Msk                     /*!< DMA Disable on Reception Error */

+#define USART_CR3_DEM_Pos               (14U)

+#define USART_CR3_DEM_Msk               (0x1UL << USART_CR3_DEM_Pos)           /*!< 0x00004000 */

+#define USART_CR3_DEM                   USART_CR3_DEM_Msk                      /*!< Driver Enable Mode */

+#define USART_CR3_DEP_Pos               (15U)

+#define USART_CR3_DEP_Msk               (0x1UL << USART_CR3_DEP_Pos)           /*!< 0x00008000 */

+#define USART_CR3_DEP                   USART_CR3_DEP_Msk                      /*!< Driver Enable Polarity Selection */

+#define USART_CR3_SCARCNT_Pos           (17U)

+#define USART_CR3_SCARCNT_Msk           (0x7UL << USART_CR3_SCARCNT_Pos)       /*!< 0x000E0000 */

+#define USART_CR3_SCARCNT               USART_CR3_SCARCNT_Msk                  /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */

+#define USART_CR3_SCARCNT_0             (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */

+#define USART_CR3_SCARCNT_1             (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */

+#define USART_CR3_SCARCNT_2             (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */

+#define USART_CR3_WUS_Pos               (20U)

+#define USART_CR3_WUS_Msk               (0x3UL << USART_CR3_WUS_Pos)           /*!< 0x00300000 */

+#define USART_CR3_WUS                   USART_CR3_WUS_Msk                      /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */

+#define USART_CR3_WUS_0                 (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */

+#define USART_CR3_WUS_1                 (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */

+#define USART_CR3_WUFIE_Pos             (22U)

+#define USART_CR3_WUFIE_Msk             (0x1UL << USART_CR3_WUFIE_Pos)         /*!< 0x00400000 */

+#define USART_CR3_WUFIE                 USART_CR3_WUFIE_Msk                    /*!< Wake Up Interrupt Enable */

+#define USART_CR3_TXFTIE_Pos            (23U)

+#define USART_CR3_TXFTIE_Msk            (0x1UL << USART_CR3_TXFTIE_Pos)        /*!< 0x00800000 */

+#define USART_CR3_TXFTIE                USART_CR3_TXFTIE_Msk                   /*!< TXFIFO threshold interrupt enable */

+#define USART_CR3_TCBGTIE_Pos           (24U)

+#define USART_CR3_TCBGTIE_Msk           (0x1UL << USART_CR3_TCBGTIE_Pos)       /*!< 0x01000000 */

+#define USART_CR3_TCBGTIE               USART_CR3_TCBGTIE_Msk                  /*!< Transmission Complete before guard time, interrupt enable */

+#define USART_CR3_RXFTCFG_Pos           (25U)

+#define USART_CR3_RXFTCFG_Msk           (0x7UL << USART_CR3_RXFTCFG_Pos)       /*!< 0x0E000000 */

+#define USART_CR3_RXFTCFG               USART_CR3_RXFTCFG_Msk                  /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */

+#define USART_CR3_RXFTCFG_0             (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */

+#define USART_CR3_RXFTCFG_1             (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */

+#define USART_CR3_RXFTCFG_2             (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */

+#define USART_CR3_RXFTIE_Pos            (28U)

+#define USART_CR3_RXFTIE_Msk            (0x1UL << USART_CR3_RXFTIE_Pos)        /*!< 0x10000000 */

+#define USART_CR3_RXFTIE                USART_CR3_RXFTIE_Msk                   /*!< RXFIFO threshold interrupt enable */

+#define USART_CR3_TXFTCFG_Pos           (29U)

+#define USART_CR3_TXFTCFG_Msk           (0x7UL << USART_CR3_TXFTCFG_Pos)       /*!< 0xE0000000 */

+#define USART_CR3_TXFTCFG               USART_CR3_TXFTCFG_Msk                  /*!< TXFIFO [2:0] threshold configuration */

+#define USART_CR3_TXFTCFG_0             (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */

+#define USART_CR3_TXFTCFG_1             (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */

+#define USART_CR3_TXFTCFG_2             (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */

+

+/******************  Bit definition for USART_BRR register  *******************/

+#define USART_BRR_DIV_FRACTION_Pos      (0U)

+#define USART_BRR_DIV_FRACTION_Msk      (0xFUL << USART_BRR_DIV_FRACTION_Pos)  /*!< 0x0000000F */

+#define USART_BRR_DIV_FRACTION          USART_BRR_DIV_FRACTION_Msk             /*!< Fraction of USARTDIV */

+#define USART_BRR_DIV_MANTISSA_Pos      (4U)

+#define USART_BRR_DIV_MANTISSA_Msk      (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */

+#define USART_BRR_DIV_MANTISSA          USART_BRR_DIV_MANTISSA_Msk             /*!< Mantissa of USARTDIV */

+

+/******************  Bit definition for USART_GTPR register  ******************/

+#define USART_GTPR_PSC_Pos              (0U)

+#define USART_GTPR_PSC_Msk              (0xFFUL << USART_GTPR_PSC_Pos)         /*!< 0x000000FF */

+#define USART_GTPR_PSC                  USART_GTPR_PSC_Msk                     /*!< PSC[7:0] bits (Prescaler value) */

+#define USART_GTPR_GT_Pos               (8U)

+#define USART_GTPR_GT_Msk               (0xFFUL << USART_GTPR_GT_Pos)          /*!< 0x0000FF00 */

+#define USART_GTPR_GT                   USART_GTPR_GT_Msk                      /*!< GT[7:0] bits (Guard time value) */

+

+/*******************  Bit definition for USART_RTOR register  *****************/

+#define USART_RTOR_RTO_Pos              (0U)

+#define USART_RTOR_RTO_Msk              (0xFFFFFFUL << USART_RTOR_RTO_Pos)     /*!< 0x00FFFFFF */

+#define USART_RTOR_RTO                  USART_RTOR_RTO_Msk                     /*!< Receiver Time Out Value */

+#define USART_RTOR_BLEN_Pos             (24U)

+#define USART_RTOR_BLEN_Msk             (0xFFUL << USART_RTOR_BLEN_Pos)        /*!< 0xFF000000 */

+#define USART_RTOR_BLEN                 USART_RTOR_BLEN_Msk                    /*!< Block Length */

+

+/*******************  Bit definition for USART_RQR register  ******************/

+#define USART_RQR_ABRRQ_Pos             (0U)

+#define USART_RQR_ABRRQ_Msk             (0x1UL << USART_RQR_ABRRQ_Pos)         /*!< 0x00000001 */

+#define USART_RQR_ABRRQ                 USART_RQR_ABRRQ_Msk                    /*!< Auto-Baud Rate Request */

+#define USART_RQR_SBKRQ_Pos             (1U)

+#define USART_RQR_SBKRQ_Msk             (0x1UL << USART_RQR_SBKRQ_Pos)         /*!< 0x00000002 */

+#define USART_RQR_SBKRQ                 USART_RQR_SBKRQ_Msk                    /*!< Send Break Request */

+#define USART_RQR_MMRQ_Pos              (2U)

+#define USART_RQR_MMRQ_Msk              (0x1UL << USART_RQR_MMRQ_Pos)          /*!< 0x00000004 */

+#define USART_RQR_MMRQ                  USART_RQR_MMRQ_Msk                     /*!< Mute Mode Request */

+#define USART_RQR_RXFRQ_Pos             (3U)

+#define USART_RQR_RXFRQ_Msk             (0x1UL << USART_RQR_RXFRQ_Pos)         /*!< 0x00000008 */

+#define USART_RQR_RXFRQ                 USART_RQR_RXFRQ_Msk                    /*!< Receive Data flush Request */

+#define USART_RQR_TXFRQ_Pos             (4U)

+#define USART_RQR_TXFRQ_Msk             (0x1UL << USART_RQR_TXFRQ_Pos)         /*!< 0x00000010 */

+#define USART_RQR_TXFRQ                 USART_RQR_TXFRQ_Msk                    /*!< Transmit data flush Request */

+

+/*******************  Bit definition for USART_ISR register  ******************/

+#define USART_ISR_PE_Pos                (0U)

+#define USART_ISR_PE_Msk                (0x1UL << USART_ISR_PE_Pos)            /*!< 0x00000001 */

+#define USART_ISR_PE                    USART_ISR_PE_Msk                       /*!< Parity Error */

+#define USART_ISR_FE_Pos                (1U)

+#define USART_ISR_FE_Msk                (0x1UL << USART_ISR_FE_Pos)            /*!< 0x00000002 */

+#define USART_ISR_FE                    USART_ISR_FE_Msk                       /*!< Framing Error */

+#define USART_ISR_NE_Pos                (2U)

+#define USART_ISR_NE_Msk                (0x1UL << USART_ISR_NE_Pos)            /*!< 0x00000004 */

+#define USART_ISR_NE                    USART_ISR_NE_Msk                       /*!< Noise detected Flag */

+#define USART_ISR_ORE_Pos               (3U)

+#define USART_ISR_ORE_Msk               (0x1UL << USART_ISR_ORE_Pos)           /*!< 0x00000008 */

+#define USART_ISR_ORE                   USART_ISR_ORE_Msk                      /*!< OverRun Error */

+#define USART_ISR_IDLE_Pos              (4U)

+#define USART_ISR_IDLE_Msk              (0x1UL << USART_ISR_IDLE_Pos)          /*!< 0x00000010 */

+#define USART_ISR_IDLE                  USART_ISR_IDLE_Msk                     /*!< IDLE line detected */

+#define USART_ISR_RXNE_RXFNE_Pos        (5U)

+#define USART_ISR_RXNE_RXFNE_Msk        (0x1UL << USART_ISR_RXNE_RXFNE_Pos)    /*!< 0x00000020 */

+#define USART_ISR_RXNE_RXFNE            USART_ISR_RXNE_RXFNE_Msk               /*!< Read Data Register or RX FIFO Not Empty */

+#define USART_ISR_TC_Pos                (6U)

+#define USART_ISR_TC_Msk                (0x1UL << USART_ISR_TC_Pos)            /*!< 0x00000040 */

+#define USART_ISR_TC                    USART_ISR_TC_Msk                       /*!< Transmission Complete */

+#define USART_ISR_TXE_TXFNF_Pos         (7U)

+#define USART_ISR_TXE_TXFNF_Msk         (0x1UL << USART_ISR_TXE_TXFNF_Pos)     /*!< 0x00000080 */

+#define USART_ISR_TXE_TXFNF             USART_ISR_TXE_TXFNF_Msk                /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */

+#define USART_ISR_LBDF_Pos              (8U)

+#define USART_ISR_LBDF_Msk              (0x1UL << USART_ISR_LBDF_Pos)          /*!< 0x00000100 */

+#define USART_ISR_LBDF                  USART_ISR_LBDF_Msk                     /*!< LIN Break Detection Flag */

+#define USART_ISR_CTSIF_Pos             (9U)

+#define USART_ISR_CTSIF_Msk             (0x1UL << USART_ISR_CTSIF_Pos)         /*!< 0x00000200 */

+#define USART_ISR_CTSIF                 USART_ISR_CTSIF_Msk                    /*!< CTS interrupt flag */

+#define USART_ISR_CTS_Pos               (10U)

+#define USART_ISR_CTS_Msk               (0x1UL << USART_ISR_CTS_Pos)           /*!< 0x00000400 */

+#define USART_ISR_CTS                   USART_ISR_CTS_Msk                      /*!< CTS flag */

+#define USART_ISR_RTOF_Pos              (11U)

+#define USART_ISR_RTOF_Msk              (0x1UL << USART_ISR_RTOF_Pos)          /*!< 0x00000800 */

+#define USART_ISR_RTOF                  USART_ISR_RTOF_Msk                     /*!< Receiver Time Out */

+#define USART_ISR_EOBF_Pos              (12U)

+#define USART_ISR_EOBF_Msk              (0x1UL << USART_ISR_EOBF_Pos)          /*!< 0x00001000 */

+#define USART_ISR_EOBF                  USART_ISR_EOBF_Msk                     /*!< End Of Block Flag */

+#define USART_ISR_UDR_Pos               (13U)

+#define USART_ISR_UDR_Msk               (0x1UL << USART_ISR_UDR_Pos)           /*!< 0x00002000 */

+#define USART_ISR_UDR                   USART_ISR_UDR_Msk                      /*!< SPI slave underrun error flag */

+#define USART_ISR_ABRE_Pos              (14U)

+#define USART_ISR_ABRE_Msk              (0x1UL << USART_ISR_ABRE_Pos)          /*!< 0x00004000 */

+#define USART_ISR_ABRE                  USART_ISR_ABRE_Msk                     /*!< Auto-Baud Rate Error */

+#define USART_ISR_ABRF_Pos              (15U)

+#define USART_ISR_ABRF_Msk              (0x1UL << USART_ISR_ABRF_Pos)          /*!< 0x00008000 */

+#define USART_ISR_ABRF                  USART_ISR_ABRF_Msk                     /*!< Auto-Baud Rate Flag */

+#define USART_ISR_BUSY_Pos              (16U)

+#define USART_ISR_BUSY_Msk              (0x1UL << USART_ISR_BUSY_Pos)          /*!< 0x00010000 */

+#define USART_ISR_BUSY                  USART_ISR_BUSY_Msk                     /*!< Busy Flag */

+#define USART_ISR_CMF_Pos               (17U)

+#define USART_ISR_CMF_Msk               (0x1UL << USART_ISR_CMF_Pos)           /*!< 0x00020000 */

+#define USART_ISR_CMF                   USART_ISR_CMF_Msk                      /*!< Character Match Flag */

+#define USART_ISR_SBKF_Pos              (18U)

+#define USART_ISR_SBKF_Msk              (0x1UL << USART_ISR_SBKF_Pos)          /*!< 0x00040000 */

+#define USART_ISR_SBKF                  USART_ISR_SBKF_Msk                     /*!< Send Break Flag */

+#define USART_ISR_RWU_Pos               (19U)

+#define USART_ISR_RWU_Msk               (0x1UL << USART_ISR_RWU_Pos)           /*!< 0x00080000 */

+#define USART_ISR_RWU                   USART_ISR_RWU_Msk                      /*!< Receive Wake Up from mute mode Flag */

+#define USART_ISR_WUF_Pos               (20U)

+#define USART_ISR_WUF_Msk               (0x1UL << USART_ISR_WUF_Pos)           /*!< 0x00100000 */

+#define USART_ISR_WUF                   USART_ISR_WUF_Msk                      /*!< Wake Up from stop mode Flag */

+#define USART_ISR_TEACK_Pos             (21U)

+#define USART_ISR_TEACK_Msk             (0x1UL << USART_ISR_TEACK_Pos)         /*!< 0x00200000 */

+#define USART_ISR_TEACK                 USART_ISR_TEACK_Msk                    /*!< Transmit Enable Acknowledge Flag */

+#define USART_ISR_REACK_Pos             (22U)

+#define USART_ISR_REACK_Msk             (0x1UL << USART_ISR_REACK_Pos)         /*!< 0x00400000 */

+#define USART_ISR_REACK                 USART_ISR_REACK_Msk                    /*!< Receive Enable Acknowledge Flag */

+#define USART_ISR_TXFE_Pos              (23U)

+#define USART_ISR_TXFE_Msk              (0x1UL << USART_ISR_TXFE_Pos)          /*!< 0x00800000 */

+#define USART_ISR_TXFE                  USART_ISR_TXFE_Msk                     /*!< TXFIFO Empty */

+#define USART_ISR_RXFF_Pos              (24U)

+#define USART_ISR_RXFF_Msk              (0x1UL << USART_ISR_RXFF_Pos)          /*!< 0x01000000 */

+#define USART_ISR_RXFF                  USART_ISR_RXFF_Msk                     /*!< RXFIFO Full Flag */

+#define USART_ISR_TCBGT_Pos             (25U)

+#define USART_ISR_TCBGT_Msk             (0x1UL << USART_ISR_TCBGT_Pos)         /*!< 0x02000000 */

+#define USART_ISR_TCBGT                 USART_ISR_TCBGT_Msk                    /*!< Transmission complete before guard time Flag */

+#define USART_ISR_RXFT_Pos              (26U)

+#define USART_ISR_RXFT_Msk              (0x1UL << USART_ISR_RXFT_Pos)          /*!< 0x04000000 */

+#define USART_ISR_RXFT                  USART_ISR_RXFT_Msk                     /*!< RXFIFO threshold Flag */

+#define USART_ISR_TXFT_Pos              (27U)

+#define USART_ISR_TXFT_Msk              (0x1UL << USART_ISR_TXFT_Pos)          /*!< 0x08000000 */

+#define USART_ISR_TXFT                  USART_ISR_TXFT_Msk                     /*!< TXFIFO threshold Flag */

+

+/*******************  Bit definition for USART_ICR register  ******************/

+#define USART_ICR_PECF_Pos              (0U)

+#define USART_ICR_PECF_Msk              (0x1UL << USART_ICR_PECF_Pos)          /*!< 0x00000001 */

+#define USART_ICR_PECF                  USART_ICR_PECF_Msk                     /*!< Parity Error Clear Flag */

+#define USART_ICR_FECF_Pos              (1U)

+#define USART_ICR_FECF_Msk              (0x1UL << USART_ICR_FECF_Pos)          /*!< 0x00000002 */

+#define USART_ICR_FECF                  USART_ICR_FECF_Msk                     /*!< Framing Error Clear Flag */

+#define USART_ICR_NECF_Pos              (2U)

+#define USART_ICR_NECF_Msk              (0x1UL << USART_ICR_NECF_Pos)          /*!< 0x00000004 */

+#define USART_ICR_NECF                  USART_ICR_NECF_Msk                     /*!< Noise detected Clear Flag */

+#define USART_ICR_ORECF_Pos             (3U)

+#define USART_ICR_ORECF_Msk             (0x1UL << USART_ICR_ORECF_Pos)         /*!< 0x00000008 */

+#define USART_ICR_ORECF                 USART_ICR_ORECF_Msk                    /*!< OverRun Error Clear Flag */

+#define USART_ICR_IDLECF_Pos            (4U)

+#define USART_ICR_IDLECF_Msk            (0x1UL << USART_ICR_IDLECF_Pos)        /*!< 0x00000010 */

+#define USART_ICR_IDLECF                USART_ICR_IDLECF_Msk                   /*!< IDLE line detected Clear Flag */

+#define USART_ICR_TXFECF_Pos            (5U)

+#define USART_ICR_TXFECF_Msk            (0x1UL << USART_ICR_TXFECF_Pos)        /*!< 0x00000020 */

+#define USART_ICR_TXFECF                USART_ICR_TXFECF_Msk                   /*!< TXFIFO empty clear flag */

+#define USART_ICR_TCCF_Pos              (6U)

+#define USART_ICR_TCCF_Msk              (0x1UL << USART_ICR_TCCF_Pos)          /*!< 0x00000040 */

+#define USART_ICR_TCCF                  USART_ICR_TCCF_Msk                     /*!< Transmission Complete Clear Flag */

+#define USART_ICR_TCBGTCF_Pos           (7U)

+#define USART_ICR_TCBGTCF_Msk           (0x1UL << USART_ICR_TCBGTCF_Pos)       /*!< 0x00000080 */

+#define USART_ICR_TCBGTCF               USART_ICR_TCBGTCF_Msk                  /*!< Transmission complete before guard time Clear Flag */

+#define USART_ICR_LBDCF_Pos             (8U)

+#define USART_ICR_LBDCF_Msk             (0x1UL << USART_ICR_LBDCF_Pos)         /*!< 0x00000100 */

+#define USART_ICR_LBDCF                 USART_ICR_LBDCF_Msk                    /*!< LIN Break Detection Clear Flag */

+#define USART_ICR_CTSCF_Pos             (9U)

+#define USART_ICR_CTSCF_Msk             (0x1UL << USART_ICR_CTSCF_Pos)         /*!< 0x00000200 */

+#define USART_ICR_CTSCF                 USART_ICR_CTSCF_Msk                    /*!< CTS Interrupt Clear Flag */

+#define USART_ICR_RTOCF_Pos             (11U)

+#define USART_ICR_RTOCF_Msk             (0x1UL << USART_ICR_RTOCF_Pos)         /*!< 0x00000800 */

+#define USART_ICR_RTOCF                 USART_ICR_RTOCF_Msk                    /*!< Receiver Time Out Clear Flag */

+#define USART_ICR_EOBCF_Pos             (12U)

+#define USART_ICR_EOBCF_Msk             (0x1UL << USART_ICR_EOBCF_Pos)         /*!< 0x00001000 */

+#define USART_ICR_EOBCF                 USART_ICR_EOBCF_Msk                    /*!< End Of Block Clear Flag */

+#define USART_ICR_UDRCF_Pos             (13U)

+#define USART_ICR_UDRCF_Msk             (0x1UL << USART_ICR_UDRCF_Pos)         /*!< 0x00002000 */

+#define USART_ICR_UDRCF                 USART_ICR_UDRCF_Msk                    /*!< SPI slave underrun clear flag */

+#define USART_ICR_CMCF_Pos              (17U)

+#define USART_ICR_CMCF_Msk              (0x1UL << USART_ICR_CMCF_Pos)          /*!< 0x00020000 */

+#define USART_ICR_CMCF                  USART_ICR_CMCF_Msk                     /*!< Character Match Clear Flag */

+#define USART_ICR_WUCF_Pos              (20U)

+#define USART_ICR_WUCF_Msk              (0x1UL << USART_ICR_WUCF_Pos)          /*!< 0x00100000 */

+#define USART_ICR_WUCF                  USART_ICR_WUCF_Msk                     /*!< Wake Up from stop mode Clear Flag */

+

+/*******************  Bit definition for USART_RDR register  ******************/

+#define USART_RDR_RDR_Pos               (0U)

+#define USART_RDR_RDR_Msk               (0x1FFUL << USART_RDR_RDR_Pos)         /*!< 0x000001FF */

+#define USART_RDR_RDR                   USART_RDR_RDR_Msk                      /*!< RDR[8:0] bits (Receive Data value) */

+

+/*******************  Bit definition for USART_TDR register  ******************/

+#define USART_TDR_TDR_Pos               (0U)

+#define USART_TDR_TDR_Msk               (0x1FFUL << USART_TDR_TDR_Pos)         /*!< 0x000001FF */

+#define USART_TDR_TDR                   USART_TDR_TDR_Msk                      /*!< TDR[8:0] bits (Transmit Data value) */

+

+/*******************  Bit definition for USART_PRESC register  ******************/

+#define USART_PRESC_PRESCALER_Pos       (0U)

+#define USART_PRESC_PRESCALER_Msk       (0xFUL << USART_PRESC_PRESCALER_Pos)   /*!< 0x0000000F */

+#define USART_PRESC_PRESCALER           USART_PRESC_PRESCALER_Msk              /*!< PRESCALER[3:0] bits (Clock prescaler) */

+#define USART_PRESC_PRESCALER_0         (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */

+#define USART_PRESC_PRESCALER_1         (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */

+#define USART_PRESC_PRESCALER_2         (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */

+#define USART_PRESC_PRESCALER_3         (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */

+

+/******************************************************************************/

+/*                                                                            */

+/*           Single Wire Protocol Master Interface (SWPMI)                    */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for SWPMI_CR register   ********************/

+#define SWPMI_CR_RXDMA_Pos       (0U)

+#define SWPMI_CR_RXDMA_Msk       (0x1UL << SWPMI_CR_RXDMA_Pos)                 /*!< 0x00000001 */

+#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */

+#define SWPMI_CR_TXDMA_Pos       (1U)

+#define SWPMI_CR_TXDMA_Msk       (0x1UL << SWPMI_CR_TXDMA_Pos)                 /*!< 0x00000002 */

+#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */

+#define SWPMI_CR_RXMODE_Pos      (2U)

+#define SWPMI_CR_RXMODE_Msk      (0x1UL << SWPMI_CR_RXMODE_Pos)                /*!< 0x00000004 */

+#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */

+#define SWPMI_CR_TXMODE_Pos      (3U)

+#define SWPMI_CR_TXMODE_Msk      (0x1UL << SWPMI_CR_TXMODE_Pos)                /*!< 0x00000008 */

+#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */

+#define SWPMI_CR_LPBK_Pos        (4U)

+#define SWPMI_CR_LPBK_Msk        (0x1UL << SWPMI_CR_LPBK_Pos)                  /*!< 0x00000010 */

+#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */

+#define SWPMI_CR_SWPACT_Pos      (5U)

+#define SWPMI_CR_SWPACT_Msk      (0x1UL << SWPMI_CR_SWPACT_Pos)                /*!< 0x00000020 */

+#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */

+#define SWPMI_CR_DEACT_Pos       (10U)

+#define SWPMI_CR_DEACT_Msk       (0x1UL << SWPMI_CR_DEACT_Pos)                 /*!< 0x00000400 */

+#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */

+#define SWPMI_CR_SWPEN_Pos       (11U)

+#define SWPMI_CR_SWPEN_Msk       (0x1UL << SWPMI_CR_SWPEN_Pos)                 /*!< 0x00000800 */

+#define SWPMI_CR_SWPEN           SWPMI_CR_SWPEN_Msk                            /*!<Single wire protocol master transceiver enable       */

+

+/*******************  Bit definition for SWPMI_BRR register  ********************/

+#define SWPMI_BRR_BR_Pos         (0U)

+#define SWPMI_BRR_BR_Msk         (0xFFUL << SWPMI_BRR_BR_Pos)                  /*!< 0x000000FF */

+#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[7:0] bits (Bitrate prescaler) */

+

+/*******************  Bit definition for SWPMI_ISR register  ********************/

+#define SWPMI_ISR_RXBFF_Pos      (0U)

+#define SWPMI_ISR_RXBFF_Msk      (0x1UL << SWPMI_ISR_RXBFF_Pos)                /*!< 0x00000001 */

+#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */

+#define SWPMI_ISR_TXBEF_Pos      (1U)

+#define SWPMI_ISR_TXBEF_Msk      (0x1UL << SWPMI_ISR_TXBEF_Pos)                /*!< 0x00000002 */

+#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */

+#define SWPMI_ISR_RXBERF_Pos     (2U)

+#define SWPMI_ISR_RXBERF_Msk     (0x1UL << SWPMI_ISR_RXBERF_Pos)               /*!< 0x00000004 */

+#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */

+#define SWPMI_ISR_RXOVRF_Pos     (3U)

+#define SWPMI_ISR_RXOVRF_Msk     (0x1UL << SWPMI_ISR_RXOVRF_Pos)               /*!< 0x00000008 */

+#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */

+#define SWPMI_ISR_TXUNRF_Pos     (4U)

+#define SWPMI_ISR_TXUNRF_Msk     (0x1UL << SWPMI_ISR_TXUNRF_Pos)               /*!< 0x00000010 */

+#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */

+#define SWPMI_ISR_RXNE_Pos       (5U)

+#define SWPMI_ISR_RXNE_Msk       (0x1UL << SWPMI_ISR_RXNE_Pos)                 /*!< 0x00000020 */

+#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */

+#define SWPMI_ISR_TXE_Pos        (6U)

+#define SWPMI_ISR_TXE_Msk        (0x1UL << SWPMI_ISR_TXE_Pos)                  /*!< 0x00000040 */

+#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */

+#define SWPMI_ISR_TCF_Pos        (7U)

+#define SWPMI_ISR_TCF_Msk        (0x1UL << SWPMI_ISR_TCF_Pos)                  /*!< 0x00000080 */

+#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */

+#define SWPMI_ISR_SRF_Pos        (8U)

+#define SWPMI_ISR_SRF_Msk        (0x1UL << SWPMI_ISR_SRF_Pos)                  /*!< 0x00000100 */

+#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */

+#define SWPMI_ISR_SUSP_Pos       (9U)

+#define SWPMI_ISR_SUSP_Msk       (0x1UL << SWPMI_ISR_SUSP_Pos)                 /*!< 0x00000200 */

+#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */

+#define SWPMI_ISR_DEACTF_Pos     (10U)

+#define SWPMI_ISR_DEACTF_Msk     (0x1UL << SWPMI_ISR_DEACTF_Pos)               /*!< 0x00000400 */

+#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */

+#define SWPMI_ISR_RDYF_Pos       (11U)

+#define SWPMI_ISR_RDYF_Msk       (0x1UL << SWPMI_ISR_RDYF_Pos)                 /*!< 0x00000800 */

+#define SWPMI_ISR_RDYF           SWPMI_ISR_RDYF_Msk                            /*!<Transceiver ready flag          */

+

+/*******************  Bit definition for SWPMI_ICR register  ********************/

+#define SWPMI_ICR_CRXBFF_Pos     (0U)

+#define SWPMI_ICR_CRXBFF_Msk     (0x1UL << SWPMI_ICR_CRXBFF_Pos)               /*!< 0x00000001 */

+#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */

+#define SWPMI_ICR_CTXBEF_Pos     (1U)

+#define SWPMI_ICR_CTXBEF_Msk     (0x1UL << SWPMI_ICR_CTXBEF_Pos)               /*!< 0x00000002 */

+#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */

+#define SWPMI_ICR_CRXBERF_Pos    (2U)

+#define SWPMI_ICR_CRXBERF_Msk    (0x1UL << SWPMI_ICR_CRXBERF_Pos)              /*!< 0x00000004 */

+#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */

+#define SWPMI_ICR_CRXOVRF_Pos    (3U)

+#define SWPMI_ICR_CRXOVRF_Msk    (0x1UL << SWPMI_ICR_CRXOVRF_Pos)              /*!< 0x00000008 */

+#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */

+#define SWPMI_ICR_CTXUNRF_Pos    (4U)

+#define SWPMI_ICR_CTXUNRF_Msk    (0x1UL << SWPMI_ICR_CTXUNRF_Pos)              /*!< 0x00000010 */

+#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */

+#define SWPMI_ICR_CTCF_Pos       (7U)

+#define SWPMI_ICR_CTCF_Msk       (0x1UL << SWPMI_ICR_CTCF_Pos)                 /*!< 0x00000080 */

+#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */

+#define SWPMI_ICR_CSRF_Pos       (8U)

+#define SWPMI_ICR_CSRF_Msk       (0x1UL << SWPMI_ICR_CSRF_Pos)                 /*!< 0x00000100 */

+#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */

+#define SWPMI_ICR_CRDYF_Pos      (11U)

+#define SWPMI_ICR_CRDYF_Msk      (0x1UL << SWPMI_ICR_CRDYF_Pos)                /*!< 0x00000800 */

+#define SWPMI_ICR_CRDYF          SWPMI_ICR_CRDYF_Msk                           /*!<Clear transceiver ready flag         */

+

+/*******************  Bit definition for SWPMI_IER register  ********************/

+#define SWPMI_IER_RXBFIE_Pos     (0U)

+#define SWPMI_IER_RXBFIE_Msk     (0x1UL << SWPMI_IER_RXBFIE_Pos)               /*!< 0x00000001 */

+#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */

+#define SWPMI_IER_TXBEIE_Pos     (1U)

+#define SWPMI_IER_TXBEIE_Msk     (0x1UL << SWPMI_IER_TXBEIE_Pos)               /*!< 0x00000002 */

+#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */

+#define SWPMI_IER_RXBERIE_Pos    (2U)

+#define SWPMI_IER_RXBERIE_Msk    (0x1UL << SWPMI_IER_RXBERIE_Pos)              /*!< 0x00000004 */

+#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */

+#define SWPMI_IER_RXOVRIE_Pos    (3U)

+#define SWPMI_IER_RXOVRIE_Msk    (0x1UL << SWPMI_IER_RXOVRIE_Pos)              /*!< 0x00000008 */

+#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */

+#define SWPMI_IER_TXUNRIE_Pos    (4U)

+#define SWPMI_IER_TXUNRIE_Msk    (0x1UL << SWPMI_IER_TXUNRIE_Pos)              /*!< 0x00000010 */

+#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */

+#define SWPMI_IER_RIE_Pos        (5U)

+#define SWPMI_IER_RIE_Msk        (0x1UL << SWPMI_IER_RIE_Pos)                  /*!< 0x00000020 */

+#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */

+#define SWPMI_IER_TIE_Pos        (6U)

+#define SWPMI_IER_TIE_Msk        (0x1UL << SWPMI_IER_TIE_Pos)                  /*!< 0x00000040 */

+#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */

+#define SWPMI_IER_TCIE_Pos       (7U)

+#define SWPMI_IER_TCIE_Msk       (0x1UL << SWPMI_IER_TCIE_Pos)                 /*!< 0x00000080 */

+#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */

+#define SWPMI_IER_SRIE_Pos       (8U)

+#define SWPMI_IER_SRIE_Msk       (0x1UL << SWPMI_IER_SRIE_Pos)                 /*!< 0x00000100 */

+#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */

+#define SWPMI_IER_RDYIE_Pos      (11U)

+#define SWPMI_IER_RDYIE_Msk      (0x1UL << SWPMI_IER_RDYIE_Pos)                /*!< 0x00000800 */

+#define SWPMI_IER_RDYIE          SWPMI_IER_RDYIE_Msk                           /*!<Transceiver ready interrupt enable          */

+

+/*******************  Bit definition for SWPMI_RFL register  ********************/

+#define SWPMI_RFL_RFL_Pos        (0U)

+#define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */

+#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */

+#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */

+

+/*******************  Bit definition for SWPMI_TDR register  ********************/

+#define SWPMI_TDR_TD_Pos         (0U)

+#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)            /*!< 0xFFFFFFFF */

+#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */

+

+/*******************  Bit definition for SWPMI_RDR register  ********************/

+#define SWPMI_RDR_RD_Pos         (0U)

+#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)            /*!< 0xFFFFFFFF */

+#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Recive Data Register           */

+

+

+/*******************  Bit definition for SWPMI_OR register  ********************/

+#define SWPMI_OR_TBYP_Pos        (0U)

+#define SWPMI_OR_TBYP_Msk        (0x1UL << SWPMI_OR_TBYP_Pos)                  /*!< 0x00000001 */

+#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */

+#define SWPMI_OR_CLASS_Pos       (1U)

+#define SWPMI_OR_CLASS_Msk       (0x1UL << SWPMI_OR_CLASS_Pos)                 /*!< 0x00000002 */

+#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP CLASS selection */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            Window WATCHDOG                                 */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for WWDG_CR register  ********************/

+#define WWDG_CR_T_Pos           (0U)

+#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */

+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */

+#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */

+#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */

+#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */

+#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */

+#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */

+#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */

+#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */

+

+#define WWDG_CR_WDGA_Pos        (7U)

+#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */

+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */

+

+/*******************  Bit definition for WWDG_CFR register  *******************/

+#define WWDG_CFR_W_Pos          (0U)

+#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */

+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */

+#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */

+#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */

+#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */

+#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */

+#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */

+#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */

+#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */

+

+#define WWDG_CFR_EWI_Pos        (9U)

+#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */

+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */

+

+#define WWDG_CFR_WDGTB_Pos      (11U)

+#define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */

+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */

+#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000800 */

+#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00001000 */

+#define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00002000 */

+

+/*******************  Bit definition for WWDG_SR register  ********************/

+#define WWDG_SR_EWIF_Pos        (0U)

+#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */

+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                DBG                                         */

+/*                                                                            */

+/******************************************************************************/

+/*********************************  DEVICE ID  ********************************/

+#define STM32H7_DEV_ID           0x450UL

+

+/********************  Bit definition for DBGMCU_IDCODE register  *************/

+#define DBGMCU_IDCODE_DEV_ID_Pos          (0U)

+#define DBGMCU_IDCODE_DEV_ID_Msk          (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */

+#define DBGMCU_IDCODE_DEV_ID              DBGMCU_IDCODE_DEV_ID_Msk

+#define DBGMCU_IDCODE_REV_ID_Pos          (16U)

+#define DBGMCU_IDCODE_REV_ID_Msk          (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */

+#define DBGMCU_IDCODE_REV_ID              DBGMCU_IDCODE_REV_ID_Msk

+

+/********************  Bit definition for DBGMCU_CR register  *****************/

+#define DBGMCU_CR_DBG_SLEEPD1_Pos         (0U)

+#define DBGMCU_CR_DBG_SLEEPD1_Msk         (0x1UL << DBGMCU_CR_DBG_SLEEPD1_Pos) /*!< 0x00000001 */

+#define DBGMCU_CR_DBG_SLEEPD1             DBGMCU_CR_DBG_SLEEPD1_Msk

+#define DBGMCU_CR_DBG_STOPD1_Pos          (1U)

+#define DBGMCU_CR_DBG_STOPD1_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD1_Pos)  /*!< 0x00000002 */

+#define DBGMCU_CR_DBG_STOPD1              DBGMCU_CR_DBG_STOPD1_Msk

+#define DBGMCU_CR_DBG_STANDBYD1_Pos       (2U)

+#define DBGMCU_CR_DBG_STANDBYD1_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos) /*!< 0x00000004 */

+#define DBGMCU_CR_DBG_STANDBYD1           DBGMCU_CR_DBG_STANDBYD1_Msk

+#define DBGMCU_CR_DBG_STOPD3_Pos          (7U)

+#define DBGMCU_CR_DBG_STOPD3_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos)  /*!< 0x00000080 */

+#define DBGMCU_CR_DBG_STOPD3              DBGMCU_CR_DBG_STOPD3_Msk

+#define DBGMCU_CR_DBG_STANDBYD3_Pos       (8U)

+#define DBGMCU_CR_DBG_STANDBYD3_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos) /*!< 0x00000100 */

+#define DBGMCU_CR_DBG_STANDBYD3           DBGMCU_CR_DBG_STANDBYD3_Msk

+#define DBGMCU_CR_DBG_TRACECKEN_Pos       (20U)

+#define DBGMCU_CR_DBG_TRACECKEN_Msk       (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */

+#define DBGMCU_CR_DBG_TRACECKEN           DBGMCU_CR_DBG_TRACECKEN_Msk

+#define DBGMCU_CR_DBG_CKD1EN_Pos          (21U)

+#define DBGMCU_CR_DBG_CKD1EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD1EN_Pos)  /*!< 0x00200000 */

+#define DBGMCU_CR_DBG_CKD1EN              DBGMCU_CR_DBG_CKD1EN_Msk

+#define DBGMCU_CR_DBG_CKD3EN_Pos          (22U)

+#define DBGMCU_CR_DBG_CKD3EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD3EN_Pos)  /*!< 0x00400000 */

+#define DBGMCU_CR_DBG_CKD3EN              DBGMCU_CR_DBG_CKD3EN_Msk

+#define DBGMCU_CR_DBG_TRGOEN_Pos          (28U)

+#define DBGMCU_CR_DBG_TRGOEN_Msk          (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)  /*!< 0x10000000 */

+#define DBGMCU_CR_DBG_TRGOEN              DBGMCU_CR_DBG_TRGOEN_Msk

+

+/********************  Bit definition for APB3FZ1 register  ************/

+#define DBGMCU_APB3FZ1_DBG_WWDG1_Pos      (6U)

+#define DBGMCU_APB3FZ1_DBG_WWDG1_Msk      (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB3FZ1_DBG_WWDG1          DBGMCU_APB3FZ1_DBG_WWDG1_Msk

+/********************  Bit definition for APB1LFZ1 register  ************/

+#define DBGMCU_APB1LFZ1_DBG_TIM2_Pos      (0U)

+#define DBGMCU_APB1LFZ1_DBG_TIM2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB1LFZ1_DBG_TIM2          DBGMCU_APB1LFZ1_DBG_TIM2_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM3_Pos      (1U)

+#define DBGMCU_APB1LFZ1_DBG_TIM3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB1LFZ1_DBG_TIM3          DBGMCU_APB1LFZ1_DBG_TIM3_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM4_Pos      (2U)

+#define DBGMCU_APB1LFZ1_DBG_TIM4_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */

+#define DBGMCU_APB1LFZ1_DBG_TIM4          DBGMCU_APB1LFZ1_DBG_TIM4_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM5_Pos      (3U)

+#define DBGMCU_APB1LFZ1_DBG_TIM5_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */

+#define DBGMCU_APB1LFZ1_DBG_TIM5          DBGMCU_APB1LFZ1_DBG_TIM5_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM6_Pos      (4U)

+#define DBGMCU_APB1LFZ1_DBG_TIM6_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */

+#define DBGMCU_APB1LFZ1_DBG_TIM6          DBGMCU_APB1LFZ1_DBG_TIM6_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM7_Pos      (5U)

+#define DBGMCU_APB1LFZ1_DBG_TIM7_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */

+#define DBGMCU_APB1LFZ1_DBG_TIM7          DBGMCU_APB1LFZ1_DBG_TIM7_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM12_Pos     (6U)

+#define DBGMCU_APB1LFZ1_DBG_TIM12_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB1LFZ1_DBG_TIM12         DBGMCU_APB1LFZ1_DBG_TIM12_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM13_Pos     (7U)

+#define DBGMCU_APB1LFZ1_DBG_TIM13_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB1LFZ1_DBG_TIM13         DBGMCU_APB1LFZ1_DBG_TIM13_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM14_Pos     (8U)

+#define DBGMCU_APB1LFZ1_DBG_TIM14_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */

+#define DBGMCU_APB1LFZ1_DBG_TIM14         DBGMCU_APB1LFZ1_DBG_TIM14_Msk

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos    (9U)

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1        DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C1_Pos      (21U)

+#define DBGMCU_APB1LFZ1_DBG_I2C1_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C1          DBGMCU_APB1LFZ1_DBG_I2C1_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C2_Pos      (22U)

+#define DBGMCU_APB1LFZ1_DBG_I2C2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C2          DBGMCU_APB1LFZ1_DBG_I2C2_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C3_Pos      (23U)

+#define DBGMCU_APB1LFZ1_DBG_I2C3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C3          DBGMCU_APB1LFZ1_DBG_I2C3_Msk

+

+/********************  Bit definition for APB1HFZ1 register  ************/

+#define DBGMCU_APB1HFZ1_DBG_FDCAN_Pos     (8U)

+#define DBGMCU_APB1HFZ1_DBG_FDCAN_Msk     (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_Pos) /*!< 0x00000100 */

+#define DBGMCU_APB1HFZ1_DBG_FDCAN         DBGMCU_APB1HFZ1_DBG_FDCAN_Msk

+/********************  Bit definition for APB2FZ1 register  ************/

+#define DBGMCU_APB2FZ1_DBG_TIM1_Pos       (0U)

+#define DBGMCU_APB2FZ1_DBG_TIM1_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB2FZ1_DBG_TIM1           DBGMCU_APB2FZ1_DBG_TIM1_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM8_Pos       (1U)

+#define DBGMCU_APB2FZ1_DBG_TIM8_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB2FZ1_DBG_TIM8           DBGMCU_APB2FZ1_DBG_TIM8_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM15_Pos      (16U)

+#define DBGMCU_APB2FZ1_DBG_TIM15_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB2FZ1_DBG_TIM15          DBGMCU_APB2FZ1_DBG_TIM15_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM16_Pos      (17U)

+#define DBGMCU_APB2FZ1_DBG_TIM16_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */

+#define DBGMCU_APB2FZ1_DBG_TIM16          DBGMCU_APB2FZ1_DBG_TIM16_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM17_Pos      (18U)

+#define DBGMCU_APB2FZ1_DBG_TIM17_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB2FZ1_DBG_TIM17          DBGMCU_APB2FZ1_DBG_TIM17_Msk

+#define DBGMCU_APB2FZ1_DBG_HRTIM_Pos      (29U)

+#define DBGMCU_APB2FZ1_DBG_HRTIM_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_HRTIM_Pos) /*!< 0x20000000 */

+#define DBGMCU_APB2FZ1_DBG_HRTIM          DBGMCU_APB2FZ1_DBG_HRTIM_Msk

+

+/********************  Bit definition for APB4FZ1 register  ************/

+#define DBGMCU_APB4FZ1_DBG_I2C4_Pos       (7U)

+#define DBGMCU_APB4FZ1_DBG_I2C4_Msk       (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB4FZ1_DBG_I2C4           DBGMCU_APB4FZ1_DBG_I2C4_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos     (9U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM2         DBGMCU_APB4FZ1_DBG_LPTIM2_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos     (10U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM3         DBGMCU_APB4FZ1_DBG_LPTIM3_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM4_Pos     (11U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM4_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos) /*!< 0x00000800 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM4         DBGMCU_APB4FZ1_DBG_LPTIM4_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM5_Pos     (12U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM5_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos) /*!< 0x00001000 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM5         DBGMCU_APB4FZ1_DBG_LPTIM5_Msk

+#define DBGMCU_APB4FZ1_DBG_RTC_Pos        (16U)

+#define DBGMCU_APB4FZ1_DBG_RTC_Msk        (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB4FZ1_DBG_RTC            DBGMCU_APB4FZ1_DBG_RTC_Msk

+#define DBGMCU_APB4FZ1_DBG_IWDG1_Pos      (18U)

+#define DBGMCU_APB4FZ1_DBG_IWDG1_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB4FZ1_DBG_IWDG1          DBGMCU_APB4FZ1_DBG_IWDG1_Msk

+/******************************************************************************/

+/*                                                                            */

+/*                        High Resolution Timer (HRTIM)                       */

+/*                                                                            */

+/******************************************************************************/

+/******************** Master Timer control register ***************************/

+#define HRTIM_MCR_CK_PSC_Pos          (0U)

+#define HRTIM_MCR_CK_PSC_Msk          (0x7UL << HRTIM_MCR_CK_PSC_Pos)          /*!< 0x00000007 */

+#define HRTIM_MCR_CK_PSC              HRTIM_MCR_CK_PSC_Msk                     /*!< Prescaler mask */

+#define HRTIM_MCR_CK_PSC_0            (0x1UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000001 */

+#define HRTIM_MCR_CK_PSC_1            (0x2UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000002 */

+#define HRTIM_MCR_CK_PSC_2            (0x4UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000004 */

+

+#define HRTIM_MCR_CONT_Pos            (3U)

+#define HRTIM_MCR_CONT_Msk            (0x1UL << HRTIM_MCR_CONT_Pos)            /*!< 0x00000008 */

+#define HRTIM_MCR_CONT                HRTIM_MCR_CONT_Msk                       /*!< Continuous mode */

+#define HRTIM_MCR_RETRIG_Pos          (4U)

+#define HRTIM_MCR_RETRIG_Msk          (0x1UL << HRTIM_MCR_RETRIG_Pos)          /*!< 0x00000010 */

+#define HRTIM_MCR_RETRIG              HRTIM_MCR_RETRIG_Msk                     /*!< Rettrigreable mode */

+#define HRTIM_MCR_HALF_Pos            (5U)

+#define HRTIM_MCR_HALF_Msk            (0x1UL << HRTIM_MCR_HALF_Pos)            /*!< 0x00000020 */

+#define HRTIM_MCR_HALF                HRTIM_MCR_HALF_Msk                       /*!< Half mode */

+

+#define HRTIM_MCR_SYNC_IN_Pos         (8U)

+#define HRTIM_MCR_SYNC_IN_Msk         (0x3UL << HRTIM_MCR_SYNC_IN_Pos)         /*!< 0x00000300 */

+#define HRTIM_MCR_SYNC_IN             HRTIM_MCR_SYNC_IN_Msk                    /*!< Synchronization input master */

+#define HRTIM_MCR_SYNC_IN_0           (0x1UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000100 */

+#define HRTIM_MCR_SYNC_IN_1           (0x2UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000200 */

+#define HRTIM_MCR_SYNCRSTM_Pos        (10U)

+#define HRTIM_MCR_SYNCRSTM_Msk        (0x1UL << HRTIM_MCR_SYNCRSTM_Pos)        /*!< 0x00000400 */

+#define HRTIM_MCR_SYNCRSTM            HRTIM_MCR_SYNCRSTM_Msk                   /*!< Synchronization reset master */

+#define HRTIM_MCR_SYNCSTRTM_Pos       (11U)

+#define HRTIM_MCR_SYNCSTRTM_Msk       (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos)       /*!< 0x00000800 */

+#define HRTIM_MCR_SYNCSTRTM           HRTIM_MCR_SYNCSTRTM_Msk                  /*!< Synchronization start master */

+#define HRTIM_MCR_SYNC_OUT_Pos        (12U)

+#define HRTIM_MCR_SYNC_OUT_Msk        (0x3UL << HRTIM_MCR_SYNC_OUT_Pos)        /*!< 0x00003000 */

+#define HRTIM_MCR_SYNC_OUT            HRTIM_MCR_SYNC_OUT_Msk                   /*!< Synchronization output master */

+#define HRTIM_MCR_SYNC_OUT_0          (0x1UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00001000 */

+#define HRTIM_MCR_SYNC_OUT_1          (0x2UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00002000 */

+#define HRTIM_MCR_SYNC_SRC_Pos        (14U)

+#define HRTIM_MCR_SYNC_SRC_Msk        (0x3UL << HRTIM_MCR_SYNC_SRC_Pos)        /*!< 0x0000C000 */

+#define HRTIM_MCR_SYNC_SRC            HRTIM_MCR_SYNC_SRC_Msk                   /*!< Synchronization source */

+#define HRTIM_MCR_SYNC_SRC_0          (0x1UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00004000 */

+#define HRTIM_MCR_SYNC_SRC_1          (0x2UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00008000 */

+

+#define HRTIM_MCR_MCEN_Pos            (16U)

+#define HRTIM_MCR_MCEN_Msk            (0x1UL << HRTIM_MCR_MCEN_Pos)            /*!< 0x00010000 */

+#define HRTIM_MCR_MCEN                HRTIM_MCR_MCEN_Msk                       /*!< Master counter enable */

+#define HRTIM_MCR_TACEN_Pos           (17U)

+#define HRTIM_MCR_TACEN_Msk           (0x1UL << HRTIM_MCR_TACEN_Pos)           /*!< 0x00020000 */

+#define HRTIM_MCR_TACEN               HRTIM_MCR_TACEN_Msk                      /*!< Timer A counter enable */

+#define HRTIM_MCR_TBCEN_Pos           (18U)

+#define HRTIM_MCR_TBCEN_Msk           (0x1UL << HRTIM_MCR_TBCEN_Pos)           /*!< 0x00040000 */

+#define HRTIM_MCR_TBCEN               HRTIM_MCR_TBCEN_Msk                      /*!< Timer B counter enable */

+#define HRTIM_MCR_TCCEN_Pos           (19U)

+#define HRTIM_MCR_TCCEN_Msk           (0x1UL << HRTIM_MCR_TCCEN_Pos)           /*!< 0x00080000 */

+#define HRTIM_MCR_TCCEN               HRTIM_MCR_TCCEN_Msk                      /*!< Timer C counter enable */

+#define HRTIM_MCR_TDCEN_Pos           (20U)

+#define HRTIM_MCR_TDCEN_Msk           (0x1UL << HRTIM_MCR_TDCEN_Pos)           /*!< 0x00100000 */

+#define HRTIM_MCR_TDCEN               HRTIM_MCR_TDCEN_Msk                      /*!< Timer D counter enable */

+#define HRTIM_MCR_TECEN_Pos           (21U)

+#define HRTIM_MCR_TECEN_Msk           (0x1UL << HRTIM_MCR_TECEN_Pos)           /*!< 0x00200000 */

+#define HRTIM_MCR_TECEN               HRTIM_MCR_TECEN_Msk                      /*!< Timer E counter enable */

+

+#define HRTIM_MCR_DACSYNC_Pos         (25U)

+#define HRTIM_MCR_DACSYNC_Msk         (0x3UL << HRTIM_MCR_DACSYNC_Pos)         /*!< 0x06000000 */

+#define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC sychronization mask */

+#define HRTIM_MCR_DACSYNC_0           (0x1UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x02000000 */

+#define HRTIM_MCR_DACSYNC_1           (0x2UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x04000000 */

+

+#define HRTIM_MCR_PREEN_Pos           (27U)

+#define HRTIM_MCR_PREEN_Msk           (0x1UL << HRTIM_MCR_PREEN_Pos)           /*!< 0x08000000 */

+#define HRTIM_MCR_PREEN               HRTIM_MCR_PREEN_Msk                      /*!< Master preload enable */

+#define HRTIM_MCR_MREPU_Pos           (29U)

+#define HRTIM_MCR_MREPU_Msk           (0x1UL << HRTIM_MCR_MREPU_Pos)           /*!< 0x20000000 */

+#define HRTIM_MCR_MREPU               HRTIM_MCR_MREPU_Msk                      /*!< Master repetition update */

+

+#define HRTIM_MCR_BRSTDMA_Pos         (30U)

+#define HRTIM_MCR_BRSTDMA_Msk         (0x3UL << HRTIM_MCR_BRSTDMA_Pos)         /*!< 0xC0000000 */

+#define HRTIM_MCR_BRSTDMA             HRTIM_MCR_BRSTDMA_Msk                    /*!< Burst DMA update */

+#define HRTIM_MCR_BRSTDMA_0           (0x1UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x40000000 */

+#define HRTIM_MCR_BRSTDMA_1           (0x2UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x80000000 */

+

+/******************** Master Timer Interrupt status register ******************/

+#define HRTIM_MISR_MCMP1_Pos          (0U)

+#define HRTIM_MISR_MCMP1_Msk          (0x1UL << HRTIM_MISR_MCMP1_Pos)          /*!< 0x00000001 */

+#define HRTIM_MISR_MCMP1              HRTIM_MISR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag */

+#define HRTIM_MISR_MCMP2_Pos          (1U)

+#define HRTIM_MISR_MCMP2_Msk          (0x1UL << HRTIM_MISR_MCMP2_Pos)          /*!< 0x00000002 */

+#define HRTIM_MISR_MCMP2              HRTIM_MISR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag */

+#define HRTIM_MISR_MCMP3_Pos          (2U)

+#define HRTIM_MISR_MCMP3_Msk          (0x1UL << HRTIM_MISR_MCMP3_Pos)          /*!< 0x00000004 */

+#define HRTIM_MISR_MCMP3              HRTIM_MISR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag */

+#define HRTIM_MISR_MCMP4_Pos          (3U)

+#define HRTIM_MISR_MCMP4_Msk          (0x1UL << HRTIM_MISR_MCMP4_Pos)          /*!< 0x00000008 */

+#define HRTIM_MISR_MCMP4              HRTIM_MISR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag */

+#define HRTIM_MISR_MREP_Pos           (4U)

+#define HRTIM_MISR_MREP_Msk           (0x1UL << HRTIM_MISR_MREP_Pos)           /*!< 0x00000010 */

+#define HRTIM_MISR_MREP               HRTIM_MISR_MREP_Msk                      /*!< Master Repetition interrupt flag */

+#define HRTIM_MISR_SYNC_Pos           (5U)

+#define HRTIM_MISR_SYNC_Msk           (0x1UL << HRTIM_MISR_SYNC_Pos)           /*!< 0x00000020 */

+#define HRTIM_MISR_SYNC               HRTIM_MISR_SYNC_Msk                      /*!< Synchronization input interrupt flag */

+#define HRTIM_MISR_MUPD_Pos           (6U)

+#define HRTIM_MISR_MUPD_Msk           (0x1UL << HRTIM_MISR_MUPD_Pos)           /*!< 0x00000040 */

+#define HRTIM_MISR_MUPD               HRTIM_MISR_MUPD_Msk                      /*!< Master update interrupt flag */

+

+/******************** Master Timer Interrupt clear register *******************/

+#define HRTIM_MICR_MCMP1_Pos          (0U)

+#define HRTIM_MICR_MCMP1_Msk          (0x1UL << HRTIM_MICR_MCMP1_Pos)          /*!< 0x00000001 */

+#define HRTIM_MICR_MCMP1              HRTIM_MICR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag clear */

+#define HRTIM_MICR_MCMP2_Pos          (1U)

+#define HRTIM_MICR_MCMP2_Msk          (0x1UL << HRTIM_MICR_MCMP2_Pos)          /*!< 0x00000002 */

+#define HRTIM_MICR_MCMP2              HRTIM_MICR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag clear */

+#define HRTIM_MICR_MCMP3_Pos          (2U)

+#define HRTIM_MICR_MCMP3_Msk          (0x1UL << HRTIM_MICR_MCMP3_Pos)          /*!< 0x00000004 */

+#define HRTIM_MICR_MCMP3              HRTIM_MICR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag clear */

+#define HRTIM_MICR_MCMP4_Pos          (3U)

+#define HRTIM_MICR_MCMP4_Msk          (0x1UL << HRTIM_MICR_MCMP4_Pos)          /*!< 0x00000008 */

+#define HRTIM_MICR_MCMP4              HRTIM_MICR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag clear */

+#define HRTIM_MICR_MREP_Pos           (4U)

+#define HRTIM_MICR_MREP_Msk           (0x1UL << HRTIM_MICR_MREP_Pos)           /*!< 0x00000010 */

+#define HRTIM_MICR_MREP               HRTIM_MICR_MREP_Msk                      /*!< Master Repetition interrupt flag clear */

+#define HRTIM_MICR_SYNC_Pos           (5U)

+#define HRTIM_MICR_SYNC_Msk           (0x1UL << HRTIM_MICR_SYNC_Pos)           /*!< 0x00000020 */

+#define HRTIM_MICR_SYNC               HRTIM_MICR_SYNC_Msk                      /*!< Synchronization input interrupt flag clear */

+#define HRTIM_MICR_MUPD_Pos           (6U)

+#define HRTIM_MICR_MUPD_Msk           (0x1UL << HRTIM_MICR_MUPD_Pos)           /*!< 0x00000040 */

+#define HRTIM_MICR_MUPD               HRTIM_MICR_MUPD_Msk                      /*!< Master update interrupt flag clear */

+

+/******************** Master Timer DMA/Interrupt enable register **************/

+#define HRTIM_MDIER_MCMP1IE_Pos       (0U)

+#define HRTIM_MDIER_MCMP1IE_Msk       (0x1UL << HRTIM_MDIER_MCMP1IE_Pos)       /*!< 0x00000001 */

+#define HRTIM_MDIER_MCMP1IE           HRTIM_MDIER_MCMP1IE_Msk                  /*!< Master compare 1 interrupt enable */

+#define HRTIM_MDIER_MCMP2IE_Pos       (1U)

+#define HRTIM_MDIER_MCMP2IE_Msk       (0x1UL << HRTIM_MDIER_MCMP2IE_Pos)       /*!< 0x00000002 */

+#define HRTIM_MDIER_MCMP2IE           HRTIM_MDIER_MCMP2IE_Msk                  /*!< Master compare 2 interrupt enable */

+#define HRTIM_MDIER_MCMP3IE_Pos       (2U)

+#define HRTIM_MDIER_MCMP3IE_Msk       (0x1UL << HRTIM_MDIER_MCMP3IE_Pos)       /*!< 0x00000004 */

+#define HRTIM_MDIER_MCMP3IE           HRTIM_MDIER_MCMP3IE_Msk                  /*!< Master compare 3 interrupt enable */

+#define HRTIM_MDIER_MCMP4IE_Pos       (3U)

+#define HRTIM_MDIER_MCMP4IE_Msk       (0x1UL << HRTIM_MDIER_MCMP4IE_Pos)       /*!< 0x00000008 */

+#define HRTIM_MDIER_MCMP4IE           HRTIM_MDIER_MCMP4IE_Msk                  /*!< Master compare 4 interrupt enable */

+#define HRTIM_MDIER_MREPIE_Pos        (4U)

+#define HRTIM_MDIER_MREPIE_Msk        (0x1UL << HRTIM_MDIER_MREPIE_Pos)        /*!< 0x00000010 */

+#define HRTIM_MDIER_MREPIE            HRTIM_MDIER_MREPIE_Msk                   /*!< Master Repetition interrupt enable */

+#define HRTIM_MDIER_SYNCIE_Pos        (5U)

+#define HRTIM_MDIER_SYNCIE_Msk        (0x1UL << HRTIM_MDIER_SYNCIE_Pos)        /*!< 0x00000020 */

+#define HRTIM_MDIER_SYNCIE            HRTIM_MDIER_SYNCIE_Msk                   /*!< Synchronization input interrupt enable */

+#define HRTIM_MDIER_MUPDIE_Pos        (6U)

+#define HRTIM_MDIER_MUPDIE_Msk        (0x1UL << HRTIM_MDIER_MUPDIE_Pos)        /*!< 0x00000040 */

+#define HRTIM_MDIER_MUPDIE            HRTIM_MDIER_MUPDIE_Msk                   /*!< Master update interrupt enable */

+

+#define HRTIM_MDIER_MCMP1DE_Pos       (16U)

+#define HRTIM_MDIER_MCMP1DE_Msk       (0x1UL << HRTIM_MDIER_MCMP1DE_Pos)       /*!< 0x00010000 */

+#define HRTIM_MDIER_MCMP1DE           HRTIM_MDIER_MCMP1DE_Msk                  /*!< Master compare 1 DMA enable */

+#define HRTIM_MDIER_MCMP2DE_Pos       (17U)

+#define HRTIM_MDIER_MCMP2DE_Msk       (0x1UL << HRTIM_MDIER_MCMP2DE_Pos)       /*!< 0x00020000 */

+#define HRTIM_MDIER_MCMP2DE           HRTIM_MDIER_MCMP2DE_Msk                  /*!< Master compare 2 DMA enable */

+#define HRTIM_MDIER_MCMP3DE_Pos       (18U)

+#define HRTIM_MDIER_MCMP3DE_Msk       (0x1UL << HRTIM_MDIER_MCMP3DE_Pos)       /*!< 0x00040000 */

+#define HRTIM_MDIER_MCMP3DE           HRTIM_MDIER_MCMP3DE_Msk                  /*!< Master compare 3 DMA enable */

+#define HRTIM_MDIER_MCMP4DE_Pos       (19U)

+#define HRTIM_MDIER_MCMP4DE_Msk       (0x1UL << HRTIM_MDIER_MCMP4DE_Pos)       /*!< 0x00080000 */

+#define HRTIM_MDIER_MCMP4DE           HRTIM_MDIER_MCMP4DE_Msk                  /*!< Master compare 4 DMA enable */

+#define HRTIM_MDIER_MREPDE_Pos        (20U)

+#define HRTIM_MDIER_MREPDE_Msk        (0x1UL << HRTIM_MDIER_MREPDE_Pos)        /*!< 0x00100000 */

+#define HRTIM_MDIER_MREPDE            HRTIM_MDIER_MREPDE_Msk                   /*!< Master Repetition DMA enable */

+#define HRTIM_MDIER_SYNCDE_Pos        (21U)

+#define HRTIM_MDIER_SYNCDE_Msk        (0x1UL << HRTIM_MDIER_SYNCDE_Pos)        /*!< 0x00200000 */

+#define HRTIM_MDIER_SYNCDE            HRTIM_MDIER_SYNCDE_Msk                   /*!< Synchronization input DMA enable */

+#define HRTIM_MDIER_MUPDDE_Pos        (22U)

+#define HRTIM_MDIER_MUPDDE_Msk        (0x1UL << HRTIM_MDIER_MUPDDE_Pos)        /*!< 0x00400000 */

+#define HRTIM_MDIER_MUPDDE            HRTIM_MDIER_MUPDDE_Msk                   /*!< Master update DMA enable */

+

+/*******************  Bit definition for HRTIM_MCNTR register  ****************/

+#define HRTIM_MCNTR_MCNTR_Pos         (0U)

+#define HRTIM_MCNTR_MCNTR_Msk         (0xFFFFUL << HRTIM_MCNTR_MCNTR_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_MCNTR_MCNTR             HRTIM_MCNTR_MCNTR_Msk                    /*!<Counter Value */

+

+/*******************  Bit definition for HRTIM_MPER register  *****************/

+#define HRTIM_MPER_MPER_Pos           (0U)

+#define HRTIM_MPER_MPER_Msk           (0xFFFFUL << HRTIM_MPER_MPER_Pos)        /*!< 0x0000FFFF */

+#define HRTIM_MPER_MPER               HRTIM_MPER_MPER_Msk                      /*!< Period Value */

+

+/*******************  Bit definition for HRTIM_MREP register  *****************/

+#define HRTIM_MREP_MREP_Pos           (0U)

+#define HRTIM_MREP_MREP_Msk           (0xFFUL << HRTIM_MREP_MREP_Pos)          /*!< 0x000000FF */

+#define HRTIM_MREP_MREP               HRTIM_MREP_MREP_Msk                      /*!<Repetition Value */

+

+/*******************  Bit definition for HRTIM_MCMP1R register  *****************/

+#define HRTIM_MCMP1R_MCMP1R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP1R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP1R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP1R           HRTIM_MCMP1R_MCMP1R_Msk                  /*!<Compare Value */

+

+/*******************  Bit definition for HRTIM_MCMP2R register  *****************/

+#define HRTIM_MCMP1R_MCMP2R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP2R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP2R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP2R           HRTIM_MCMP1R_MCMP2R_Msk                  /*!<Compare Value */

+

+/*******************  Bit definition for HRTIM_MCMP3R register  *****************/

+#define HRTIM_MCMP1R_MCMP3R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP3R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP3R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP3R           HRTIM_MCMP1R_MCMP3R_Msk                  /*!<Compare Value */

+

+/*******************  Bit definition for HRTIM_MCMP4R register  *****************/

+#define HRTIM_MCMP1R_MCMP4R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP4R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP4R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP4R           HRTIM_MCMP1R_MCMP4R_Msk                  /*!<Compare Value */

+

+/******************** Slave control register **********************************/

+#define HRTIM_TIMCR_CK_PSC_Pos        (0U)

+#define HRTIM_TIMCR_CK_PSC_Msk        (0x7UL << HRTIM_TIMCR_CK_PSC_Pos)        /*!< 0x00000007 */

+#define HRTIM_TIMCR_CK_PSC            HRTIM_TIMCR_CK_PSC_Msk                   /*!< Slave prescaler mask*/

+#define HRTIM_TIMCR_CK_PSC_0          (0x1UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000001 */

+#define HRTIM_TIMCR_CK_PSC_1          (0x2UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000002 */

+#define HRTIM_TIMCR_CK_PSC_2          (0x4UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000004 */

+

+#define HRTIM_TIMCR_CONT_Pos          (3U)

+#define HRTIM_TIMCR_CONT_Msk          (0x1UL << HRTIM_TIMCR_CONT_Pos)          /*!< 0x00000008 */

+#define HRTIM_TIMCR_CONT              HRTIM_TIMCR_CONT_Msk                     /*!< Slave continuous mode */

+#define HRTIM_TIMCR_RETRIG_Pos        (4U)

+#define HRTIM_TIMCR_RETRIG_Msk        (0x1UL << HRTIM_TIMCR_RETRIG_Pos)        /*!< 0x00000010 */

+#define HRTIM_TIMCR_RETRIG            HRTIM_TIMCR_RETRIG_Msk                   /*!< Slave Retrigreable mode */

+#define HRTIM_TIMCR_HALF_Pos          (5U)

+#define HRTIM_TIMCR_HALF_Msk          (0x1UL << HRTIM_TIMCR_HALF_Pos)          /*!< 0x00000020 */

+#define HRTIM_TIMCR_HALF              HRTIM_TIMCR_HALF_Msk                     /*!< Slave Half mode */

+#define HRTIM_TIMCR_PSHPLL_Pos        (6U)

+#define HRTIM_TIMCR_PSHPLL_Msk        (0x1UL << HRTIM_TIMCR_PSHPLL_Pos)        /*!< 0x00000040 */

+#define HRTIM_TIMCR_PSHPLL            HRTIM_TIMCR_PSHPLL_Msk                   /*!< Slave push-pull mode */

+

+#define HRTIM_TIMCR_SYNCRST_Pos       (10U)

+#define HRTIM_TIMCR_SYNCRST_Msk       (0x1UL << HRTIM_TIMCR_SYNCRST_Pos)       /*!< 0x00000400 */

+#define HRTIM_TIMCR_SYNCRST           HRTIM_TIMCR_SYNCRST_Msk                  /*!< Slave synchronization resets */

+#define HRTIM_TIMCR_SYNCSTRT_Pos      (11U)

+#define HRTIM_TIMCR_SYNCSTRT_Msk      (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos)      /*!< 0x00000800 */

+#define HRTIM_TIMCR_SYNCSTRT          HRTIM_TIMCR_SYNCSTRT_Msk                 /*!< Slave synchronization starts */

+

+#define HRTIM_TIMCR_DELCMP2_Pos       (12U)

+#define HRTIM_TIMCR_DELCMP2_Msk       (0x3UL << HRTIM_TIMCR_DELCMP2_Pos)       /*!< 0x00003000 */

+#define HRTIM_TIMCR_DELCMP2           HRTIM_TIMCR_DELCMP2_Msk                  /*!< Slave delayed compartor 2 mode mask */

+#define HRTIM_TIMCR_DELCMP2_0         (0x1UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00001000 */

+#define HRTIM_TIMCR_DELCMP2_1         (0x2UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00002000 */

+#define HRTIM_TIMCR_DELCMP4_Pos       (14U)

+#define HRTIM_TIMCR_DELCMP4_Msk       (0x3UL << HRTIM_TIMCR_DELCMP4_Pos)       /*!< 0x0000C000 */

+#define HRTIM_TIMCR_DELCMP4           HRTIM_TIMCR_DELCMP4_Msk                  /*!< Slave delayed compartor 4 mode mask */

+#define HRTIM_TIMCR_DELCMP4_0         (0x1UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00004000 */

+#define HRTIM_TIMCR_DELCMP4_1         (0x2UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00008000 */

+

+#define HRTIM_TIMCR_TREPU_Pos         (17U)

+#define HRTIM_TIMCR_TREPU_Msk         (0x1UL << HRTIM_TIMCR_TREPU_Pos)         /*!< 0x00020000 */

+#define HRTIM_TIMCR_TREPU             HRTIM_TIMCR_TREPU_Msk                    /*!< Slave repetition update */

+#define HRTIM_TIMCR_TRSTU_Pos         (18U)

+#define HRTIM_TIMCR_TRSTU_Msk         (0x1UL << HRTIM_TIMCR_TRSTU_Pos)         /*!< 0x00040000 */

+#define HRTIM_TIMCR_TRSTU             HRTIM_TIMCR_TRSTU_Msk                    /*!< Slave reset update */

+#define HRTIM_TIMCR_TAU_Pos           (19U)

+#define HRTIM_TIMCR_TAU_Msk           (0x1UL << HRTIM_TIMCR_TAU_Pos)           /*!< 0x00080000 */

+#define HRTIM_TIMCR_TAU               HRTIM_TIMCR_TAU_Msk                      /*!< Slave Timer A update reserved for TIM A */

+#define HRTIM_TIMCR_TBU_Pos           (20U)

+#define HRTIM_TIMCR_TBU_Msk           (0x1UL << HRTIM_TIMCR_TBU_Pos)           /*!< 0x00100000 */

+#define HRTIM_TIMCR_TBU               HRTIM_TIMCR_TBU_Msk                      /*!< Slave Timer B update reserved for TIM B */

+#define HRTIM_TIMCR_TCU_Pos           (21U)

+#define HRTIM_TIMCR_TCU_Msk           (0x1UL << HRTIM_TIMCR_TCU_Pos)           /*!< 0x00200000 */

+#define HRTIM_TIMCR_TCU               HRTIM_TIMCR_TCU_Msk                      /*!< Slave Timer C update reserved for TIM C */

+#define HRTIM_TIMCR_TDU_Pos           (22U)

+#define HRTIM_TIMCR_TDU_Msk           (0x1UL << HRTIM_TIMCR_TDU_Pos)           /*!< 0x00400000 */

+#define HRTIM_TIMCR_TDU               HRTIM_TIMCR_TDU_Msk                      /*!< Slave Timer D update reserved for TIM D */

+#define HRTIM_TIMCR_TEU_Pos           (23U)

+#define HRTIM_TIMCR_TEU_Msk           (0x1UL << HRTIM_TIMCR_TEU_Pos)           /*!< 0x00800000 */

+#define HRTIM_TIMCR_TEU               HRTIM_TIMCR_TEU_Msk                      /*!< Slave Timer E update reserved for TIM E */

+#define HRTIM_TIMCR_MSTU_Pos          (24U)

+#define HRTIM_TIMCR_MSTU_Msk          (0x1UL << HRTIM_TIMCR_MSTU_Pos)          /*!< 0x01000000 */

+#define HRTIM_TIMCR_MSTU              HRTIM_TIMCR_MSTU_Msk                     /*!< Master Update */

+

+#define HRTIM_TIMCR_DACSYNC_Pos       (25U)

+#define HRTIM_TIMCR_DACSYNC_Msk       (0x3UL << HRTIM_TIMCR_DACSYNC_Pos)       /*!< 0x06000000 */

+#define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC sychronization mask */

+#define HRTIM_TIMCR_DACSYNC_0         (0x1UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x02000000 */

+#define HRTIM_TIMCR_DACSYNC_1         (0x2UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x04000000 */

+#define HRTIM_TIMCR_PREEN_Pos         (27U)

+#define HRTIM_TIMCR_PREEN_Msk         (0x1UL << HRTIM_TIMCR_PREEN_Pos)         /*!< 0x08000000 */

+#define HRTIM_TIMCR_PREEN             HRTIM_TIMCR_PREEN_Msk                    /*!< Slave preload enable */

+

+#define HRTIM_TIMCR_UPDGAT_Pos        (28U)

+#define HRTIM_TIMCR_UPDGAT_Msk        (0xFUL << HRTIM_TIMCR_UPDGAT_Pos)        /*!< 0xF0000000 */

+#define HRTIM_TIMCR_UPDGAT            HRTIM_TIMCR_UPDGAT_Msk                   /*!< Slave update gating mask */

+#define HRTIM_TIMCR_UPDGAT_0          (0x1UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x10000000 */

+#define HRTIM_TIMCR_UPDGAT_1          (0x2UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x20000000 */

+#define HRTIM_TIMCR_UPDGAT_2          (0x4UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x40000000 */

+#define HRTIM_TIMCR_UPDGAT_3          (0x8UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x80000000 */

+

+/******************** Slave Interrupt status register **************************/

+#define HRTIM_TIMISR_CMP1_Pos         (0U)

+#define HRTIM_TIMISR_CMP1_Msk         (0x1UL << HRTIM_TIMISR_CMP1_Pos)         /*!< 0x00000001 */

+#define HRTIM_TIMISR_CMP1             HRTIM_TIMISR_CMP1_Msk                    /*!< Slave compare 1 interrupt flag */

+#define HRTIM_TIMISR_CMP2_Pos         (1U)

+#define HRTIM_TIMISR_CMP2_Msk         (0x1UL << HRTIM_TIMISR_CMP2_Pos)         /*!< 0x00000002 */

+#define HRTIM_TIMISR_CMP2             HRTIM_TIMISR_CMP2_Msk                    /*!< Slave compare 2 interrupt flag */

+#define HRTIM_TIMISR_CMP3_Pos         (2U)

+#define HRTIM_TIMISR_CMP3_Msk         (0x1UL << HRTIM_TIMISR_CMP3_Pos)         /*!< 0x00000004 */

+#define HRTIM_TIMISR_CMP3             HRTIM_TIMISR_CMP3_Msk                    /*!< Slave compare 3 interrupt flag */

+#define HRTIM_TIMISR_CMP4_Pos         (3U)

+#define HRTIM_TIMISR_CMP4_Msk         (0x1UL << HRTIM_TIMISR_CMP4_Pos)         /*!< 0x00000008 */

+#define HRTIM_TIMISR_CMP4             HRTIM_TIMISR_CMP4_Msk                    /*!< Slave compare 4 interrupt flag */

+#define HRTIM_TIMISR_REP_Pos          (4U)

+#define HRTIM_TIMISR_REP_Msk          (0x1UL << HRTIM_TIMISR_REP_Pos)          /*!< 0x00000010 */

+#define HRTIM_TIMISR_REP              HRTIM_TIMISR_REP_Msk                     /*!< Slave repetition interrupt flag */

+#define HRTIM_TIMISR_UPD_Pos          (6U)

+#define HRTIM_TIMISR_UPD_Msk          (0x1UL << HRTIM_TIMISR_UPD_Pos)          /*!< 0x00000040 */

+#define HRTIM_TIMISR_UPD              HRTIM_TIMISR_UPD_Msk                     /*!< Slave update interrupt flag */

+#define HRTIM_TIMISR_CPT1_Pos         (7U)

+#define HRTIM_TIMISR_CPT1_Msk         (0x1UL << HRTIM_TIMISR_CPT1_Pos)         /*!< 0x00000080 */

+#define HRTIM_TIMISR_CPT1             HRTIM_TIMISR_CPT1_Msk                    /*!< Slave capture 1 interrupt flag */

+#define HRTIM_TIMISR_CPT2_Pos         (8U)

+#define HRTIM_TIMISR_CPT2_Msk         (0x1UL << HRTIM_TIMISR_CPT2_Pos)         /*!< 0x00000100 */

+#define HRTIM_TIMISR_CPT2             HRTIM_TIMISR_CPT2_Msk                    /*!< Slave capture 2 interrupt flag */

+#define HRTIM_TIMISR_SET1_Pos         (9U)

+#define HRTIM_TIMISR_SET1_Msk         (0x1UL << HRTIM_TIMISR_SET1_Pos)         /*!< 0x00000200 */

+#define HRTIM_TIMISR_SET1             HRTIM_TIMISR_SET1_Msk                    /*!< Slave output 1 set interrupt flag */

+#define HRTIM_TIMISR_RST1_Pos         (10U)

+#define HRTIM_TIMISR_RST1_Msk         (0x1UL << HRTIM_TIMISR_RST1_Pos)         /*!< 0x00000400 */

+#define HRTIM_TIMISR_RST1             HRTIM_TIMISR_RST1_Msk                    /*!< Slave output 1 reset interrupt flag */

+#define HRTIM_TIMISR_SET2_Pos         (11U)

+#define HRTIM_TIMISR_SET2_Msk         (0x1UL << HRTIM_TIMISR_SET2_Pos)         /*!< 0x00000800 */

+#define HRTIM_TIMISR_SET2             HRTIM_TIMISR_SET2_Msk                    /*!< Slave output 2 set interrupt flag */

+#define HRTIM_TIMISR_RST2_Pos         (12U)

+#define HRTIM_TIMISR_RST2_Msk         (0x1UL << HRTIM_TIMISR_RST2_Pos)         /*!< 0x00001000 */

+#define HRTIM_TIMISR_RST2             HRTIM_TIMISR_RST2_Msk                    /*!< Slave output 2 reset interrupt flag */

+#define HRTIM_TIMISR_RST_Pos          (13U)

+#define HRTIM_TIMISR_RST_Msk          (0x1UL << HRTIM_TIMISR_RST_Pos)          /*!< 0x00002000 */

+#define HRTIM_TIMISR_RST              HRTIM_TIMISR_RST_Msk                     /*!< Slave reset interrupt flag */

+#define HRTIM_TIMISR_DLYPRT_Pos       (14U)

+#define HRTIM_TIMISR_DLYPRT_Msk       (0x1UL << HRTIM_TIMISR_DLYPRT_Pos)       /*!< 0x00004000 */

+#define HRTIM_TIMISR_DLYPRT           HRTIM_TIMISR_DLYPRT_Msk                  /*!< Slave output 1 delay protection interrupt flag */

+#define HRTIM_TIMISR_CPPSTAT_Pos      (16U)

+#define HRTIM_TIMISR_CPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos)      /*!< 0x00010000 */

+#define HRTIM_TIMISR_CPPSTAT          HRTIM_TIMISR_CPPSTAT_Msk                 /*!< Slave current push-pull flag */

+#define HRTIM_TIMISR_IPPSTAT_Pos      (17U)

+#define HRTIM_TIMISR_IPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos)      /*!< 0x00020000 */

+#define HRTIM_TIMISR_IPPSTAT          HRTIM_TIMISR_IPPSTAT_Msk                 /*!< Slave idle push-pull flag */

+#define HRTIM_TIMISR_O1STAT_Pos       (18U)

+#define HRTIM_TIMISR_O1STAT_Msk       (0x1UL << HRTIM_TIMISR_O1STAT_Pos)       /*!< 0x00040000 */

+#define HRTIM_TIMISR_O1STAT           HRTIM_TIMISR_O1STAT_Msk                  /*!< Slave output 1 state flag */

+#define HRTIM_TIMISR_O2STAT_Pos       (19U)

+#define HRTIM_TIMISR_O2STAT_Msk       (0x1UL << HRTIM_TIMISR_O2STAT_Pos)       /*!< 0x00080000 */

+#define HRTIM_TIMISR_O2STAT           HRTIM_TIMISR_O2STAT_Msk                  /*!< Slave output 2 state flag */

+#define HRTIM_TIMISR_O1CPY_Pos        (20U)

+#define HRTIM_TIMISR_O1CPY_Msk        (0x1UL << HRTIM_TIMISR_O1CPY_Pos)        /*!< 0x00100000 */

+#define HRTIM_TIMISR_O1CPY            HRTIM_TIMISR_O1CPY_Msk                   /*!< Slave output 1 copy flag */

+#define HRTIM_TIMISR_O2CPY_Pos        (21U)

+#define HRTIM_TIMISR_O2CPY_Msk        (0x1UL << HRTIM_TIMISR_O2CPY_Pos)        /*!< 0x00200000 */

+#define HRTIM_TIMISR_O2CPY            HRTIM_TIMISR_O2CPY_Msk                   /*!< Slave output 2 copy flag */

+

+/******************** Slave Interrupt clear register **************************/

+#define HRTIM_TIMICR_CMP1C_Pos        (0U)

+#define HRTIM_TIMICR_CMP1C_Msk        (0x1UL << HRTIM_TIMICR_CMP1C_Pos)        /*!< 0x00000001 */

+#define HRTIM_TIMICR_CMP1C            HRTIM_TIMICR_CMP1C_Msk                   /*!< Slave compare 1 clear flag */

+#define HRTIM_TIMICR_CMP2C_Pos        (1U)

+#define HRTIM_TIMICR_CMP2C_Msk        (0x1UL << HRTIM_TIMICR_CMP2C_Pos)        /*!< 0x00000002 */

+#define HRTIM_TIMICR_CMP2C            HRTIM_TIMICR_CMP2C_Msk                   /*!< Slave compare 2 clear flag */

+#define HRTIM_TIMICR_CMP3C_Pos        (2U)

+#define HRTIM_TIMICR_CMP3C_Msk        (0x1UL << HRTIM_TIMICR_CMP3C_Pos)        /*!< 0x00000004 */

+#define HRTIM_TIMICR_CMP3C            HRTIM_TIMICR_CMP3C_Msk                   /*!< Slave compare 3 clear flag */

+#define HRTIM_TIMICR_CMP4C_Pos        (3U)

+#define HRTIM_TIMICR_CMP4C_Msk        (0x1UL << HRTIM_TIMICR_CMP4C_Pos)        /*!< 0x00000008 */

+#define HRTIM_TIMICR_CMP4C            HRTIM_TIMICR_CMP4C_Msk                   /*!< Slave compare 4 clear flag */

+#define HRTIM_TIMICR_REPC_Pos         (4U)

+#define HRTIM_TIMICR_REPC_Msk         (0x1UL << HRTIM_TIMICR_REPC_Pos)         /*!< 0x00000010 */

+#define HRTIM_TIMICR_REPC             HRTIM_TIMICR_REPC_Msk                    /*!< Slave repetition clear flag */

+#define HRTIM_TIMICR_UPDC_Pos         (6U)

+#define HRTIM_TIMICR_UPDC_Msk         (0x1UL << HRTIM_TIMICR_UPDC_Pos)         /*!< 0x00000040 */

+#define HRTIM_TIMICR_UPDC             HRTIM_TIMICR_UPDC_Msk                    /*!< Slave update clear flag */

+#define HRTIM_TIMICR_CPT1C_Pos        (7U)

+#define HRTIM_TIMICR_CPT1C_Msk        (0x1UL << HRTIM_TIMICR_CPT1C_Pos)        /*!< 0x00000080 */

+#define HRTIM_TIMICR_CPT1C            HRTIM_TIMICR_CPT1C_Msk                   /*!< Slave capture 1 clear flag */

+#define HRTIM_TIMICR_CPT2C_Pos        (8U)

+#define HRTIM_TIMICR_CPT2C_Msk        (0x1UL << HRTIM_TIMICR_CPT2C_Pos)        /*!< 0x00000100 */

+#define HRTIM_TIMICR_CPT2C            HRTIM_TIMICR_CPT2C_Msk                   /*!< Slave capture 2 clear flag */

+#define HRTIM_TIMICR_SET1C_Pos        (9U)

+#define HRTIM_TIMICR_SET1C_Msk        (0x1UL << HRTIM_TIMICR_SET1C_Pos)        /*!< 0x00000200 */

+#define HRTIM_TIMICR_SET1C            HRTIM_TIMICR_SET1C_Msk                   /*!< Slave output 1 set clear flag */

+#define HRTIM_TIMICR_RST1C_Pos        (10U)

+#define HRTIM_TIMICR_RST1C_Msk        (0x1UL << HRTIM_TIMICR_RST1C_Pos)        /*!< 0x00000400 */

+#define HRTIM_TIMICR_RST1C            HRTIM_TIMICR_RST1C_Msk                   /*!< Slave output 1 reset clear flag */

+#define HRTIM_TIMICR_SET2C_Pos        (11U)

+#define HRTIM_TIMICR_SET2C_Msk        (0x1UL << HRTIM_TIMICR_SET2C_Pos)        /*!< 0x00000800 */

+#define HRTIM_TIMICR_SET2C            HRTIM_TIMICR_SET2C_Msk                   /*!< Slave output 2 set clear flag */

+#define HRTIM_TIMICR_RST2C_Pos        (12U)

+#define HRTIM_TIMICR_RST2C_Msk        (0x1UL << HRTIM_TIMICR_RST2C_Pos)        /*!< 0x00001000 */

+#define HRTIM_TIMICR_RST2C            HRTIM_TIMICR_RST2C_Msk                   /*!< Slave output 2 reset clear flag */

+#define HRTIM_TIMICR_RSTC_Pos         (13U)

+#define HRTIM_TIMICR_RSTC_Msk         (0x1UL << HRTIM_TIMICR_RSTC_Pos)         /*!< 0x00002000 */

+#define HRTIM_TIMICR_RSTC             HRTIM_TIMICR_RSTC_Msk                    /*!< Slave reset clear flag */

+#define HRTIM_TIMICR_DLYPRTC_Pos      (14U)

+#define HRTIM_TIMICR_DLYPRTC_Msk      (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos)      /*!< 0x00004000 */

+#define HRTIM_TIMICR_DLYPRTC          HRTIM_TIMICR_DLYPRTC_Msk                 /*!< Slave output 1 delay protection clear flag */

+

+/******************** Slave DMA/Interrupt enable register *********************/

+#define HRTIM_TIMDIER_CMP1IE_Pos      (0U)

+#define HRTIM_TIMDIER_CMP1IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos)      /*!< 0x00000001 */

+#define HRTIM_TIMDIER_CMP1IE          HRTIM_TIMDIER_CMP1IE_Msk                 /*!< Slave compare 1 interrupt enable */

+#define HRTIM_TIMDIER_CMP2IE_Pos      (1U)

+#define HRTIM_TIMDIER_CMP2IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos)      /*!< 0x00000002 */

+#define HRTIM_TIMDIER_CMP2IE          HRTIM_TIMDIER_CMP2IE_Msk                 /*!< Slave compare 2 interrupt enable */

+#define HRTIM_TIMDIER_CMP3IE_Pos      (2U)

+#define HRTIM_TIMDIER_CMP3IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos)      /*!< 0x00000004 */

+#define HRTIM_TIMDIER_CMP3IE          HRTIM_TIMDIER_CMP3IE_Msk                 /*!< Slave compare 3 interrupt enable */

+#define HRTIM_TIMDIER_CMP4IE_Pos      (3U)

+#define HRTIM_TIMDIER_CMP4IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos)      /*!< 0x00000008 */

+#define HRTIM_TIMDIER_CMP4IE          HRTIM_TIMDIER_CMP4IE_Msk                 /*!< Slave compare 4 interrupt enable */

+#define HRTIM_TIMDIER_REPIE_Pos       (4U)

+#define HRTIM_TIMDIER_REPIE_Msk       (0x1UL << HRTIM_TIMDIER_REPIE_Pos)       /*!< 0x00000010 */

+#define HRTIM_TIMDIER_REPIE           HRTIM_TIMDIER_REPIE_Msk                  /*!< Slave repetition interrupt enable */

+#define HRTIM_TIMDIER_UPDIE_Pos       (6U)

+#define HRTIM_TIMDIER_UPDIE_Msk       (0x1UL << HRTIM_TIMDIER_UPDIE_Pos)       /*!< 0x00000040 */

+#define HRTIM_TIMDIER_UPDIE           HRTIM_TIMDIER_UPDIE_Msk                  /*!< Slave update interrupt enable */

+#define HRTIM_TIMDIER_CPT1IE_Pos      (7U)

+#define HRTIM_TIMDIER_CPT1IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos)      /*!< 0x00000080 */

+#define HRTIM_TIMDIER_CPT1IE          HRTIM_TIMDIER_CPT1IE_Msk                 /*!< Slave capture 1 interrupt enable */

+#define HRTIM_TIMDIER_CPT2IE_Pos      (8U)

+#define HRTIM_TIMDIER_CPT2IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos)      /*!< 0x00000100 */

+#define HRTIM_TIMDIER_CPT2IE          HRTIM_TIMDIER_CPT2IE_Msk                 /*!< Slave capture 2 interrupt enable */

+#define HRTIM_TIMDIER_SET1IE_Pos      (9U)

+#define HRTIM_TIMDIER_SET1IE_Msk      (0x1UL << HRTIM_TIMDIER_SET1IE_Pos)      /*!< 0x00000200 */

+#define HRTIM_TIMDIER_SET1IE          HRTIM_TIMDIER_SET1IE_Msk                 /*!< Slave output 1 set interrupt enable */

+#define HRTIM_TIMDIER_RST1IE_Pos      (10U)

+#define HRTIM_TIMDIER_RST1IE_Msk      (0x1UL << HRTIM_TIMDIER_RST1IE_Pos)      /*!< 0x00000400 */

+#define HRTIM_TIMDIER_RST1IE          HRTIM_TIMDIER_RST1IE_Msk                 /*!< Slave output 1 reset interrupt enable */

+#define HRTIM_TIMDIER_SET2IE_Pos      (11U)

+#define HRTIM_TIMDIER_SET2IE_Msk      (0x1UL << HRTIM_TIMDIER_SET2IE_Pos)      /*!< 0x00000800 */

+#define HRTIM_TIMDIER_SET2IE          HRTIM_TIMDIER_SET2IE_Msk                 /*!< Slave output 2 set interrupt enable */

+#define HRTIM_TIMDIER_RST2IE_Pos      (12U)

+#define HRTIM_TIMDIER_RST2IE_Msk      (0x1UL << HRTIM_TIMDIER_RST2IE_Pos)      /*!< 0x00001000 */

+#define HRTIM_TIMDIER_RST2IE          HRTIM_TIMDIER_RST2IE_Msk                 /*!< Slave output 2 reset interrupt enable */

+#define HRTIM_TIMDIER_RSTIE_Pos       (13U)

+#define HRTIM_TIMDIER_RSTIE_Msk       (0x1UL << HRTIM_TIMDIER_RSTIE_Pos)       /*!< 0x00002000 */

+#define HRTIM_TIMDIER_RSTIE           HRTIM_TIMDIER_RSTIE_Msk                  /*!< Slave reset interrupt enable */

+#define HRTIM_TIMDIER_DLYPRTIE_Pos    (14U)

+#define HRTIM_TIMDIER_DLYPRTIE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos)    /*!< 0x00004000 */

+#define HRTIM_TIMDIER_DLYPRTIE        HRTIM_TIMDIER_DLYPRTIE_Msk               /*!< Slave delay protection interrupt enable */

+

+#define HRTIM_TIMDIER_CMP1DE_Pos      (16U)

+#define HRTIM_TIMDIER_CMP1DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos)      /*!< 0x00010000 */

+#define HRTIM_TIMDIER_CMP1DE          HRTIM_TIMDIER_CMP1DE_Msk                 /*!< Slave compare 1 request enable */

+#define HRTIM_TIMDIER_CMP2DE_Pos      (17U)

+#define HRTIM_TIMDIER_CMP2DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos)      /*!< 0x00020000 */

+#define HRTIM_TIMDIER_CMP2DE          HRTIM_TIMDIER_CMP2DE_Msk                 /*!< Slave compare 2 request enable */

+#define HRTIM_TIMDIER_CMP3DE_Pos      (18U)

+#define HRTIM_TIMDIER_CMP3DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos)      /*!< 0x00040000 */

+#define HRTIM_TIMDIER_CMP3DE          HRTIM_TIMDIER_CMP3DE_Msk                 /*!< Slave compare 3 request enable */

+#define HRTIM_TIMDIER_CMP4DE_Pos      (19U)

+#define HRTIM_TIMDIER_CMP4DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos)      /*!< 0x00080000 */

+#define HRTIM_TIMDIER_CMP4DE          HRTIM_TIMDIER_CMP4DE_Msk                 /*!< Slave compare 4 request enable */

+#define HRTIM_TIMDIER_REPDE_Pos       (20U)

+#define HRTIM_TIMDIER_REPDE_Msk       (0x1UL << HRTIM_TIMDIER_REPDE_Pos)       /*!< 0x00100000 */

+#define HRTIM_TIMDIER_REPDE           HRTIM_TIMDIER_REPDE_Msk                  /*!< Slave repetition request enable */

+#define HRTIM_TIMDIER_UPDDE_Pos       (22U)

+#define HRTIM_TIMDIER_UPDDE_Msk       (0x1UL << HRTIM_TIMDIER_UPDDE_Pos)       /*!< 0x00400000 */

+#define HRTIM_TIMDIER_UPDDE           HRTIM_TIMDIER_UPDDE_Msk                  /*!< Slave update request enable */

+#define HRTIM_TIMDIER_CPT1DE_Pos      (23U)

+#define HRTIM_TIMDIER_CPT1DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos)      /*!< 0x00800000 */

+#define HRTIM_TIMDIER_CPT1DE          HRTIM_TIMDIER_CPT1DE_Msk                 /*!< Slave capture 1 request enable */

+#define HRTIM_TIMDIER_CPT2DE_Pos      (24U)

+#define HRTIM_TIMDIER_CPT2DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos)      /*!< 0x01000000 */

+#define HRTIM_TIMDIER_CPT2DE          HRTIM_TIMDIER_CPT2DE_Msk                 /*!< Slave capture 2 request enable */

+#define HRTIM_TIMDIER_SET1DE_Pos      (25U)

+#define HRTIM_TIMDIER_SET1DE_Msk      (0x1UL << HRTIM_TIMDIER_SET1DE_Pos)      /*!< 0x02000000 */

+#define HRTIM_TIMDIER_SET1DE          HRTIM_TIMDIER_SET1DE_Msk                 /*!< Slave output 1 set request enable */

+#define HRTIM_TIMDIER_RST1DE_Pos      (26U)

+#define HRTIM_TIMDIER_RST1DE_Msk      (0x1UL << HRTIM_TIMDIER_RST1DE_Pos)      /*!< 0x04000000 */

+#define HRTIM_TIMDIER_RST1DE          HRTIM_TIMDIER_RST1DE_Msk                 /*!< Slave output 1 reset request enable */

+#define HRTIM_TIMDIER_SET2DE_Pos      (27U)

+#define HRTIM_TIMDIER_SET2DE_Msk      (0x1UL << HRTIM_TIMDIER_SET2DE_Pos)      /*!< 0x08000000 */

+#define HRTIM_TIMDIER_SET2DE          HRTIM_TIMDIER_SET2DE_Msk                 /*!< Slave output 2 set request enable */

+#define HRTIM_TIMDIER_RST2DE_Pos      (28U)

+#define HRTIM_TIMDIER_RST2DE_Msk      (0x1UL << HRTIM_TIMDIER_RST2DE_Pos)      /*!< 0x10000000 */

+#define HRTIM_TIMDIER_RST2DE          HRTIM_TIMDIER_RST2DE_Msk                 /*!< Slave output 2 reset request enable */

+#define HRTIM_TIMDIER_RSTDE_Pos       (29U)

+#define HRTIM_TIMDIER_RSTDE_Msk       (0x1UL << HRTIM_TIMDIER_RSTDE_Pos)       /*!< 0x20000000 */

+#define HRTIM_TIMDIER_RSTDE           HRTIM_TIMDIER_RSTDE_Msk                  /*!< Slave reset request enable */

+#define HRTIM_TIMDIER_DLYPRTDE_Pos    (30U)

+#define HRTIM_TIMDIER_DLYPRTDE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos)    /*!< 0x40000000 */

+#define HRTIM_TIMDIER_DLYPRTDE        HRTIM_TIMDIER_DLYPRTDE_Msk               /*!< Slavedelay protection request enable */

+

+/******************  Bit definition for HRTIM_CNTR register  ****************/

+#define HRTIM_CNTR_CNTR_Pos           (0U)

+#define HRTIM_CNTR_CNTR_Msk           (0xFFFFUL << HRTIM_CNTR_CNTR_Pos)        /*!< 0x0000FFFF */

+#define HRTIM_CNTR_CNTR               HRTIM_CNTR_CNTR_Msk                      /*!< Counter Value */

+

+/*******************  Bit definition for HRTIM_PER register  *****************/

+#define HRTIM_PER_PER_Pos             (0U)

+#define HRTIM_PER_PER_Msk             (0xFFFFUL << HRTIM_PER_PER_Pos)          /*!< 0x0000FFFF */

+#define HRTIM_PER_PER                 HRTIM_PER_PER_Msk                        /*!< Period Value */

+

+/*******************  Bit definition for HRTIM_REP register  *****************/

+#define HRTIM_REP_REP_Pos             (0U)

+#define HRTIM_REP_REP_Msk             (0xFFUL << HRTIM_REP_REP_Pos)            /*!< 0x000000FF */

+#define HRTIM_REP_REP                 HRTIM_REP_REP_Msk                        /*!< Repetition Value */

+

+/*******************  Bit definition for HRTIM_CMP1R register  *****************/

+#define HRTIM_CMP1R_CMP1R_Pos         (0U)

+#define HRTIM_CMP1R_CMP1R_Msk         (0xFFFFUL << HRTIM_CMP1R_CMP1R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP1R_CMP1R             HRTIM_CMP1R_CMP1R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP1CR register  *****************/

+#define HRTIM_CMP1CR_CMP1CR_Pos       (0U)

+#define HRTIM_CMP1CR_CMP1CR_Msk       (0xFFFFFFFFUL << HRTIM_CMP1CR_CMP1CR_Pos) /*!< 0xFFFFFFFF */

+#define HRTIM_CMP1CR_CMP1CR           HRTIM_CMP1CR_CMP1CR_Msk                  /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP2R register  *****************/

+#define HRTIM_CMP2R_CMP2R_Pos         (0U)

+#define HRTIM_CMP2R_CMP2R_Msk         (0xFFFFUL << HRTIM_CMP2R_CMP2R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP2R_CMP2R             HRTIM_CMP2R_CMP2R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP3R register  *****************/

+#define HRTIM_CMP3R_CMP3R_Pos         (0U)

+#define HRTIM_CMP3R_CMP3R_Msk         (0xFFFFUL << HRTIM_CMP3R_CMP3R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP3R_CMP3R             HRTIM_CMP3R_CMP3R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP4R register  *****************/

+#define HRTIM_CMP4R_CMP4R_Pos         (0U)

+#define HRTIM_CMP4R_CMP4R_Msk         (0xFFFFUL << HRTIM_CMP4R_CMP4R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP4R_CMP4R             HRTIM_CMP4R_CMP4R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CPT1R register  ****************/

+#define HRTIM_CPT1R_CPT1R_Pos         (0U)

+#define HRTIM_CPT1R_CPT1R_Msk         (0xFFFFUL << HRTIM_CPT1R_CPT1R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CPT1R_CPT1R             HRTIM_CPT1R_CPT1R_Msk                    /*!< Capture Value */

+

+/*******************  Bit definition for HRTIM_CPT2R register  ****************/

+#define HRTIM_CPT2R_CPT2R_Pos         (0U)

+#define HRTIM_CPT2R_CPT2R_Msk         (0xFFFFUL << HRTIM_CPT2R_CPT2R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CPT2R_CPT2R             HRTIM_CPT2R_CPT2R_Msk                    /*!< Capture Value */

+

+/******************** Bit definition for Slave Deadtime register **************/

+#define HRTIM_DTR_DTR_Pos             (0U)

+#define HRTIM_DTR_DTR_Msk             (0x1FFUL << HRTIM_DTR_DTR_Pos)           /*!< 0x000001FF */

+#define HRTIM_DTR_DTR                 HRTIM_DTR_DTR_Msk                        /*!< Dead time rising value */

+#define HRTIM_DTR_DTR_0               (0x001UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000001 */

+#define HRTIM_DTR_DTR_1               (0x002UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000002 */

+#define HRTIM_DTR_DTR_2               (0x004UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000004 */

+#define HRTIM_DTR_DTR_3               (0x008UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000008 */

+#define HRTIM_DTR_DTR_4               (0x010UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000010 */

+#define HRTIM_DTR_DTR_5               (0x020UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000020 */

+#define HRTIM_DTR_DTR_6               (0x040UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000040 */

+#define HRTIM_DTR_DTR_7               (0x080UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000080 */

+#define HRTIM_DTR_DTR_8               (0x100UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000100 */

+#define HRTIM_DTR_SDTR_Pos            (9U)

+#define HRTIM_DTR_SDTR_Msk            (0x1UL << HRTIM_DTR_SDTR_Pos)            /*!< 0x00000200 */

+#define HRTIM_DTR_SDTR                HRTIM_DTR_SDTR_Msk                       /*!< Sign dead time rising value */

+#define HRTIM_DTR_DTPRSC_Pos          (10U)

+#define HRTIM_DTR_DTPRSC_Msk          (0x7UL << HRTIM_DTR_DTPRSC_Pos)          /*!< 0x00001C00 */

+#define HRTIM_DTR_DTPRSC              HRTIM_DTR_DTPRSC_Msk                     /*!< Dead time prescaler */

+#define HRTIM_DTR_DTPRSC_0            (0x1UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000400 */

+#define HRTIM_DTR_DTPRSC_1            (0x2UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000800 */

+#define HRTIM_DTR_DTPRSC_2            (0x4UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00001000 */

+#define HRTIM_DTR_DTRSLK_Pos          (14U)

+#define HRTIM_DTR_DTRSLK_Msk          (0x1UL << HRTIM_DTR_DTRSLK_Pos)          /*!< 0x00004000 */

+#define HRTIM_DTR_DTRSLK              HRTIM_DTR_DTRSLK_Msk                     /*!< Dead time rising sign lock */

+#define HRTIM_DTR_DTRLK_Pos           (15U)

+#define HRTIM_DTR_DTRLK_Msk           (0x1UL << HRTIM_DTR_DTRLK_Pos)           /*!< 0x00008000 */

+#define HRTIM_DTR_DTRLK               HRTIM_DTR_DTRLK_Msk                      /*!< Dead time rising lock */

+#define HRTIM_DTR_DTF_Pos             (16U)

+#define HRTIM_DTR_DTF_Msk             (0x1FFUL << HRTIM_DTR_DTF_Pos)           /*!< 0x01FF0000 */

+#define HRTIM_DTR_DTF                 HRTIM_DTR_DTF_Msk                        /*!< Dead time falling value */

+#define HRTIM_DTR_DTF_0               (0x001UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00010000 */

+#define HRTIM_DTR_DTF_1               (0x002UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00020000 */

+#define HRTIM_DTR_DTF_2               (0x004UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00040000 */

+#define HRTIM_DTR_DTF_3               (0x008UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00080000 */

+#define HRTIM_DTR_DTF_4               (0x010UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00100000 */

+#define HRTIM_DTR_DTF_5               (0x020UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00200000 */

+#define HRTIM_DTR_DTF_6               (0x040UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00400000 */

+#define HRTIM_DTR_DTF_7               (0x080UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00800000 */

+#define HRTIM_DTR_DTF_8               (0x100UL << HRTIM_DTR_DTF_Pos)            /*!< 0x01000000 */

+#define HRTIM_DTR_SDTF_Pos            (25U)

+#define HRTIM_DTR_SDTF_Msk            (0x1UL << HRTIM_DTR_SDTF_Pos)            /*!< 0x02000000 */

+#define HRTIM_DTR_SDTF                HRTIM_DTR_SDTF_Msk                       /*!< Sign dead time falling value */

+#define HRTIM_DTR_DTFSLK_Pos          (30U)

+#define HRTIM_DTR_DTFSLK_Msk          (0x1UL << HRTIM_DTR_DTFSLK_Pos)          /*!< 0x40000000 */

+#define HRTIM_DTR_DTFSLK              HRTIM_DTR_DTFSLK_Msk                     /*!< Dead time falling sign lock */

+#define HRTIM_DTR_DTFLK_Pos           (31U)

+#define HRTIM_DTR_DTFLK_Msk           (0x1UL << HRTIM_DTR_DTFLK_Pos)           /*!< 0x80000000 */

+#define HRTIM_DTR_DTFLK               HRTIM_DTR_DTFLK_Msk                      /*!< Dead time falling lock */

+

+/**** Bit definition for Slave Output 1 set register **************************/

+#define HRTIM_SET1R_SST_Pos           (0U)

+#define HRTIM_SET1R_SST_Msk           (0x1UL << HRTIM_SET1R_SST_Pos)           /*!< 0x00000001 */

+#define HRTIM_SET1R_SST               HRTIM_SET1R_SST_Msk                      /*!< software set trigger */

+#define HRTIM_SET1R_RESYNC_Pos        (1U)

+#define HRTIM_SET1R_RESYNC_Msk        (0x1UL << HRTIM_SET1R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_SET1R_RESYNC            HRTIM_SET1R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_SET1R_PER_Pos           (2U)

+#define HRTIM_SET1R_PER_Msk           (0x1UL << HRTIM_SET1R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_SET1R_PER               HRTIM_SET1R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_SET1R_CMP1_Pos          (3U)

+#define HRTIM_SET1R_CMP1_Msk          (0x1UL << HRTIM_SET1R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_SET1R_CMP1              HRTIM_SET1R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_SET1R_CMP2_Pos          (4U)

+#define HRTIM_SET1R_CMP2_Msk          (0x1UL << HRTIM_SET1R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_SET1R_CMP2              HRTIM_SET1R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_SET1R_CMP3_Pos          (5U)

+#define HRTIM_SET1R_CMP3_Msk          (0x1UL << HRTIM_SET1R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_SET1R_CMP3              HRTIM_SET1R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_SET1R_CMP4_Pos          (6U)

+#define HRTIM_SET1R_CMP4_Msk          (0x1UL << HRTIM_SET1R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_SET1R_CMP4              HRTIM_SET1R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_SET1R_MSTPER_Pos        (7U)

+#define HRTIM_SET1R_MSTPER_Msk        (0x1UL << HRTIM_SET1R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_SET1R_MSTPER            HRTIM_SET1R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_SET1R_MSTCMP1_Pos       (8U)

+#define HRTIM_SET1R_MSTCMP1_Msk       (0x1UL << HRTIM_SET1R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_SET1R_MSTCMP1           HRTIM_SET1R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_SET1R_MSTCMP2_Pos       (9U)

+#define HRTIM_SET1R_MSTCMP2_Msk       (0x1UL << HRTIM_SET1R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_SET1R_MSTCMP2           HRTIM_SET1R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_SET1R_MSTCMP3_Pos       (10U)

+#define HRTIM_SET1R_MSTCMP3_Msk       (0x1UL << HRTIM_SET1R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_SET1R_MSTCMP3           HRTIM_SET1R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_SET1R_MSTCMP4_Pos       (11U)

+#define HRTIM_SET1R_MSTCMP4_Msk       (0x1UL << HRTIM_SET1R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_SET1R_MSTCMP4           HRTIM_SET1R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_SET1R_TIMEVNT1_Pos      (12U)

+#define HRTIM_SET1R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_SET1R_TIMEVNT1          HRTIM_SET1R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_SET1R_TIMEVNT2_Pos      (13U)

+#define HRTIM_SET1R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_SET1R_TIMEVNT2          HRTIM_SET1R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_SET1R_TIMEVNT3_Pos      (14U)

+#define HRTIM_SET1R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_SET1R_TIMEVNT3          HRTIM_SET1R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_SET1R_TIMEVNT4_Pos      (15U)

+#define HRTIM_SET1R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_SET1R_TIMEVNT4          HRTIM_SET1R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_SET1R_TIMEVNT5_Pos      (16U)

+#define HRTIM_SET1R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_SET1R_TIMEVNT5          HRTIM_SET1R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_SET1R_TIMEVNT6_Pos      (17U)

+#define HRTIM_SET1R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_SET1R_TIMEVNT6          HRTIM_SET1R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_SET1R_TIMEVNT7_Pos      (18U)

+#define HRTIM_SET1R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_SET1R_TIMEVNT7          HRTIM_SET1R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_SET1R_TIMEVNT8_Pos      (19U)

+#define HRTIM_SET1R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_SET1R_TIMEVNT8          HRTIM_SET1R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_SET1R_TIMEVNT9_Pos      (20U)

+#define HRTIM_SET1R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_SET1R_TIMEVNT9          HRTIM_SET1R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_SET1R_EXTVNT1_Pos       (21U)

+#define HRTIM_SET1R_EXTVNT1_Msk       (0x1UL << HRTIM_SET1R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_SET1R_EXTVNT1           HRTIM_SET1R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_SET1R_EXTVNT2_Pos       (22U)

+#define HRTIM_SET1R_EXTVNT2_Msk       (0x1UL << HRTIM_SET1R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_SET1R_EXTVNT2           HRTIM_SET1R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_SET1R_EXTVNT3_Pos       (23U)

+#define HRTIM_SET1R_EXTVNT3_Msk       (0x1UL << HRTIM_SET1R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_SET1R_EXTVNT3           HRTIM_SET1R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_SET1R_EXTVNT4_Pos       (24U)

+#define HRTIM_SET1R_EXTVNT4_Msk       (0x1UL << HRTIM_SET1R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_SET1R_EXTVNT4           HRTIM_SET1R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_SET1R_EXTVNT5_Pos       (25U)

+#define HRTIM_SET1R_EXTVNT5_Msk       (0x1UL << HRTIM_SET1R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_SET1R_EXTVNT5           HRTIM_SET1R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_SET1R_EXTVNT6_Pos       (26U)

+#define HRTIM_SET1R_EXTVNT6_Msk       (0x1UL << HRTIM_SET1R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_SET1R_EXTVNT6           HRTIM_SET1R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_SET1R_EXTVNT7_Pos       (27U)

+#define HRTIM_SET1R_EXTVNT7_Msk       (0x1UL << HRTIM_SET1R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_SET1R_EXTVNT7           HRTIM_SET1R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_SET1R_EXTVNT8_Pos       (28U)

+#define HRTIM_SET1R_EXTVNT8_Msk       (0x1UL << HRTIM_SET1R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_SET1R_EXTVNT8           HRTIM_SET1R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_SET1R_EXTVNT9_Pos       (29U)

+#define HRTIM_SET1R_EXTVNT9_Msk       (0x1UL << HRTIM_SET1R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_SET1R_EXTVNT9           HRTIM_SET1R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_SET1R_EXTVNT10_Pos      (30U)

+#define HRTIM_SET1R_EXTVNT10_Msk      (0x1UL << HRTIM_SET1R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_SET1R_EXTVNT10          HRTIM_SET1R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_SET1R_UPDATE_Pos        (31U)

+#define HRTIM_SET1R_UPDATE_Msk        (0x1UL << HRTIM_SET1R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_SET1R_UPDATE            HRTIM_SET1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+/**** Bit definition for Slave Output 1 reset register ************************/

+#define HRTIM_RST1R_SRT_Pos           (0U)

+#define HRTIM_RST1R_SRT_Msk           (0x1UL << HRTIM_RST1R_SRT_Pos)           /*!< 0x00000001 */

+#define HRTIM_RST1R_SRT               HRTIM_RST1R_SRT_Msk                      /*!< software reset trigger */

+#define HRTIM_RST1R_RESYNC_Pos        (1U)

+#define HRTIM_RST1R_RESYNC_Msk        (0x1UL << HRTIM_RST1R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_RST1R_RESYNC            HRTIM_RST1R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_RST1R_PER_Pos           (2U)

+#define HRTIM_RST1R_PER_Msk           (0x1UL << HRTIM_RST1R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_RST1R_PER               HRTIM_RST1R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_RST1R_CMP1_Pos          (3U)

+#define HRTIM_RST1R_CMP1_Msk          (0x1UL << HRTIM_RST1R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_RST1R_CMP1              HRTIM_RST1R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_RST1R_CMP2_Pos          (4U)

+#define HRTIM_RST1R_CMP2_Msk          (0x1UL << HRTIM_RST1R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_RST1R_CMP2              HRTIM_RST1R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_RST1R_CMP3_Pos          (5U)

+#define HRTIM_RST1R_CMP3_Msk          (0x1UL << HRTIM_RST1R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_RST1R_CMP3              HRTIM_RST1R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_RST1R_CMP4_Pos          (6U)

+#define HRTIM_RST1R_CMP4_Msk          (0x1UL << HRTIM_RST1R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_RST1R_CMP4              HRTIM_RST1R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_RST1R_MSTPER_Pos        (7U)

+#define HRTIM_RST1R_MSTPER_Msk        (0x1UL << HRTIM_RST1R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_RST1R_MSTPER            HRTIM_RST1R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_RST1R_MSTCMP1_Pos       (8U)

+#define HRTIM_RST1R_MSTCMP1_Msk       (0x1UL << HRTIM_RST1R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_RST1R_MSTCMP1           HRTIM_RST1R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_RST1R_MSTCMP2_Pos       (9U)

+#define HRTIM_RST1R_MSTCMP2_Msk       (0x1UL << HRTIM_RST1R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_RST1R_MSTCMP2           HRTIM_RST1R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_RST1R_MSTCMP3_Pos       (10U)

+#define HRTIM_RST1R_MSTCMP3_Msk       (0x1UL << HRTIM_RST1R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_RST1R_MSTCMP3           HRTIM_RST1R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_RST1R_MSTCMP4_Pos       (11U)

+#define HRTIM_RST1R_MSTCMP4_Msk       (0x1UL << HRTIM_RST1R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_RST1R_MSTCMP4           HRTIM_RST1R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_RST1R_TIMEVNT1_Pos      (12U)

+#define HRTIM_RST1R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_RST1R_TIMEVNT1          HRTIM_RST1R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_RST1R_TIMEVNT2_Pos      (13U)

+#define HRTIM_RST1R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_RST1R_TIMEVNT2          HRTIM_RST1R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_RST1R_TIMEVNT3_Pos      (14U)

+#define HRTIM_RST1R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_RST1R_TIMEVNT3          HRTIM_RST1R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_RST1R_TIMEVNT4_Pos      (15U)

+#define HRTIM_RST1R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_RST1R_TIMEVNT4          HRTIM_RST1R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_RST1R_TIMEVNT5_Pos      (16U)

+#define HRTIM_RST1R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_RST1R_TIMEVNT5          HRTIM_RST1R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_RST1R_TIMEVNT6_Pos      (17U)

+#define HRTIM_RST1R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_RST1R_TIMEVNT6          HRTIM_RST1R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_RST1R_TIMEVNT7_Pos      (18U)

+#define HRTIM_RST1R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_RST1R_TIMEVNT7          HRTIM_RST1R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_RST1R_TIMEVNT8_Pos      (19U)

+#define HRTIM_RST1R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_RST1R_TIMEVNT8          HRTIM_RST1R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_RST1R_TIMEVNT9_Pos      (20U)

+#define HRTIM_RST1R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_RST1R_TIMEVNT9          HRTIM_RST1R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_RST1R_EXTVNT1_Pos       (21U)

+#define HRTIM_RST1R_EXTVNT1_Msk       (0x1UL << HRTIM_RST1R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_RST1R_EXTVNT1           HRTIM_RST1R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_RST1R_EXTVNT2_Pos       (22U)

+#define HRTIM_RST1R_EXTVNT2_Msk       (0x1UL << HRTIM_RST1R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_RST1R_EXTVNT2           HRTIM_RST1R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_RST1R_EXTVNT3_Pos       (23U)

+#define HRTIM_RST1R_EXTVNT3_Msk       (0x1UL << HRTIM_RST1R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_RST1R_EXTVNT3           HRTIM_RST1R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_RST1R_EXTVNT4_Pos       (24U)

+#define HRTIM_RST1R_EXTVNT4_Msk       (0x1UL << HRTIM_RST1R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_RST1R_EXTVNT4           HRTIM_RST1R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_RST1R_EXTVNT5_Pos       (25U)

+#define HRTIM_RST1R_EXTVNT5_Msk       (0x1UL << HRTIM_RST1R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_RST1R_EXTVNT5           HRTIM_RST1R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_RST1R_EXTVNT6_Pos       (26U)

+#define HRTIM_RST1R_EXTVNT6_Msk       (0x1UL << HRTIM_RST1R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_RST1R_EXTVNT6           HRTIM_RST1R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_RST1R_EXTVNT7_Pos       (27U)

+#define HRTIM_RST1R_EXTVNT7_Msk       (0x1UL << HRTIM_RST1R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_RST1R_EXTVNT7           HRTIM_RST1R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_RST1R_EXTVNT8_Pos       (28U)

+#define HRTIM_RST1R_EXTVNT8_Msk       (0x1UL << HRTIM_RST1R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_RST1R_EXTVNT8           HRTIM_RST1R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_RST1R_EXTVNT9_Pos       (29U)

+#define HRTIM_RST1R_EXTVNT9_Msk       (0x1UL << HRTIM_RST1R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_RST1R_EXTVNT9           HRTIM_RST1R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_RST1R_EXTVNT10_Pos      (30U)

+#define HRTIM_RST1R_EXTVNT10_Msk      (0x1UL << HRTIM_RST1R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_RST1R_EXTVNT10          HRTIM_RST1R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_RST1R_UPDATE_Pos        (31U)

+#define HRTIM_RST1R_UPDATE_Msk        (0x1UL << HRTIM_RST1R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_RST1R_UPDATE            HRTIM_RST1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+

+/**** Bit definition for Slave Output 2 set register **************************/

+#define HRTIM_SET2R_SST_Pos           (0U)

+#define HRTIM_SET2R_SST_Msk           (0x1UL << HRTIM_SET2R_SST_Pos)           /*!< 0x00000001 */

+#define HRTIM_SET2R_SST               HRTIM_SET2R_SST_Msk                      /*!< software set trigger */

+#define HRTIM_SET2R_RESYNC_Pos        (1U)

+#define HRTIM_SET2R_RESYNC_Msk        (0x1UL << HRTIM_SET2R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_SET2R_RESYNC            HRTIM_SET2R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_SET2R_PER_Pos           (2U)

+#define HRTIM_SET2R_PER_Msk           (0x1UL << HRTIM_SET2R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_SET2R_PER               HRTIM_SET2R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_SET2R_CMP1_Pos          (3U)

+#define HRTIM_SET2R_CMP1_Msk          (0x1UL << HRTIM_SET2R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_SET2R_CMP1              HRTIM_SET2R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_SET2R_CMP2_Pos          (4U)

+#define HRTIM_SET2R_CMP2_Msk          (0x1UL << HRTIM_SET2R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_SET2R_CMP2              HRTIM_SET2R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_SET2R_CMP3_Pos          (5U)

+#define HRTIM_SET2R_CMP3_Msk          (0x1UL << HRTIM_SET2R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_SET2R_CMP3              HRTIM_SET2R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_SET2R_CMP4_Pos          (6U)

+#define HRTIM_SET2R_CMP4_Msk          (0x1UL << HRTIM_SET2R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_SET2R_CMP4              HRTIM_SET2R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_SET2R_MSTPER_Pos        (7U)

+#define HRTIM_SET2R_MSTPER_Msk        (0x1UL << HRTIM_SET2R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_SET2R_MSTPER            HRTIM_SET2R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_SET2R_MSTCMP1_Pos       (8U)

+#define HRTIM_SET2R_MSTCMP1_Msk       (0x1UL << HRTIM_SET2R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_SET2R_MSTCMP1           HRTIM_SET2R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_SET2R_MSTCMP2_Pos       (9U)

+#define HRTIM_SET2R_MSTCMP2_Msk       (0x1UL << HRTIM_SET2R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_SET2R_MSTCMP2           HRTIM_SET2R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_SET2R_MSTCMP3_Pos       (10U)

+#define HRTIM_SET2R_MSTCMP3_Msk       (0x1UL << HRTIM_SET2R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_SET2R_MSTCMP3           HRTIM_SET2R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_SET2R_MSTCMP4_Pos       (11U)

+#define HRTIM_SET2R_MSTCMP4_Msk       (0x1UL << HRTIM_SET2R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_SET2R_MSTCMP4           HRTIM_SET2R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_SET2R_TIMEVNT1_Pos      (12U)

+#define HRTIM_SET2R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_SET2R_TIMEVNT1          HRTIM_SET2R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_SET2R_TIMEVNT2_Pos      (13U)

+#define HRTIM_SET2R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_SET2R_TIMEVNT2          HRTIM_SET2R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_SET2R_TIMEVNT3_Pos      (14U)

+#define HRTIM_SET2R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_SET2R_TIMEVNT3          HRTIM_SET2R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_SET2R_TIMEVNT4_Pos      (15U)

+#define HRTIM_SET2R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_SET2R_TIMEVNT4          HRTIM_SET2R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_SET2R_TIMEVNT5_Pos      (16U)

+#define HRTIM_SET2R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_SET2R_TIMEVNT5          HRTIM_SET2R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_SET2R_TIMEVNT6_Pos      (17U)

+#define HRTIM_SET2R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_SET2R_TIMEVNT6          HRTIM_SET2R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_SET2R_TIMEVNT7_Pos      (18U)

+#define HRTIM_SET2R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_SET2R_TIMEVNT7          HRTIM_SET2R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_SET2R_TIMEVNT8_Pos      (19U)

+#define HRTIM_SET2R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_SET2R_TIMEVNT8          HRTIM_SET2R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_SET2R_TIMEVNT9_Pos      (20U)

+#define HRTIM_SET2R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_SET2R_TIMEVNT9          HRTIM_SET2R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_SET2R_EXTVNT1_Pos       (21U)

+#define HRTIM_SET2R_EXTVNT1_Msk       (0x1UL << HRTIM_SET2R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_SET2R_EXTVNT1           HRTIM_SET2R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_SET2R_EXTVNT2_Pos       (22U)

+#define HRTIM_SET2R_EXTVNT2_Msk       (0x1UL << HRTIM_SET2R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_SET2R_EXTVNT2           HRTIM_SET2R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_SET2R_EXTVNT3_Pos       (23U)

+#define HRTIM_SET2R_EXTVNT3_Msk       (0x1UL << HRTIM_SET2R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_SET2R_EXTVNT3           HRTIM_SET2R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_SET2R_EXTVNT4_Pos       (24U)

+#define HRTIM_SET2R_EXTVNT4_Msk       (0x1UL << HRTIM_SET2R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_SET2R_EXTVNT4           HRTIM_SET2R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_SET2R_EXTVNT5_Pos       (25U)

+#define HRTIM_SET2R_EXTVNT5_Msk       (0x1UL << HRTIM_SET2R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_SET2R_EXTVNT5           HRTIM_SET2R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_SET2R_EXTVNT6_Pos       (26U)

+#define HRTIM_SET2R_EXTVNT6_Msk       (0x1UL << HRTIM_SET2R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_SET2R_EXTVNT6           HRTIM_SET2R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_SET2R_EXTVNT7_Pos       (27U)

+#define HRTIM_SET2R_EXTVNT7_Msk       (0x1UL << HRTIM_SET2R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_SET2R_EXTVNT7           HRTIM_SET2R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_SET2R_EXTVNT8_Pos       (28U)

+#define HRTIM_SET2R_EXTVNT8_Msk       (0x1UL << HRTIM_SET2R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_SET2R_EXTVNT8           HRTIM_SET2R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_SET2R_EXTVNT9_Pos       (29U)

+#define HRTIM_SET2R_EXTVNT9_Msk       (0x1UL << HRTIM_SET2R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_SET2R_EXTVNT9           HRTIM_SET2R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_SET2R_EXTVNT10_Pos      (30U)

+#define HRTIM_SET2R_EXTVNT10_Msk      (0x1UL << HRTIM_SET2R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_SET2R_EXTVNT10          HRTIM_SET2R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_SET2R_UPDATE_Pos        (31U)

+#define HRTIM_SET2R_UPDATE_Msk        (0x1UL << HRTIM_SET2R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_SET2R_UPDATE            HRTIM_SET2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+/**** Bit definition for Slave Output 2 reset register ************************/

+#define HRTIM_RST2R_SRT_Pos           (0U)

+#define HRTIM_RST2R_SRT_Msk           (0x1UL << HRTIM_RST2R_SRT_Pos)           /*!< 0x00000001 */

+#define HRTIM_RST2R_SRT               HRTIM_RST2R_SRT_Msk                      /*!< software reset trigger */

+#define HRTIM_RST2R_RESYNC_Pos        (1U)

+#define HRTIM_RST2R_RESYNC_Msk        (0x1UL << HRTIM_RST2R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_RST2R_RESYNC            HRTIM_RST2R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_RST2R_PER_Pos           (2U)

+#define HRTIM_RST2R_PER_Msk           (0x1UL << HRTIM_RST2R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_RST2R_PER               HRTIM_RST2R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_RST2R_CMP1_Pos          (3U)

+#define HRTIM_RST2R_CMP1_Msk          (0x1UL << HRTIM_RST2R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_RST2R_CMP1              HRTIM_RST2R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_RST2R_CMP2_Pos          (4U)

+#define HRTIM_RST2R_CMP2_Msk          (0x1UL << HRTIM_RST2R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_RST2R_CMP2              HRTIM_RST2R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_RST2R_CMP3_Pos          (5U)

+#define HRTIM_RST2R_CMP3_Msk          (0x1UL << HRTIM_RST2R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_RST2R_CMP3              HRTIM_RST2R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_RST2R_CMP4_Pos          (6U)

+#define HRTIM_RST2R_CMP4_Msk          (0x1UL << HRTIM_RST2R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_RST2R_CMP4              HRTIM_RST2R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_RST2R_MSTPER_Pos        (7U)

+#define HRTIM_RST2R_MSTPER_Msk        (0x1UL << HRTIM_RST2R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_RST2R_MSTPER            HRTIM_RST2R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_RST2R_MSTCMP1_Pos       (8U)

+#define HRTIM_RST2R_MSTCMP1_Msk       (0x1UL << HRTIM_RST2R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_RST2R_MSTCMP1           HRTIM_RST2R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_RST2R_MSTCMP2_Pos       (9U)

+#define HRTIM_RST2R_MSTCMP2_Msk       (0x1UL << HRTIM_RST2R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_RST2R_MSTCMP2           HRTIM_RST2R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_RST2R_MSTCMP3_Pos       (10U)

+#define HRTIM_RST2R_MSTCMP3_Msk       (0x1UL << HRTIM_RST2R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_RST2R_MSTCMP3           HRTIM_RST2R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_RST2R_MSTCMP4_Pos       (11U)

+#define HRTIM_RST2R_MSTCMP4_Msk       (0x1UL << HRTIM_RST2R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_RST2R_MSTCMP4           HRTIM_RST2R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_RST2R_TIMEVNT1_Pos      (12U)

+#define HRTIM_RST2R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_RST2R_TIMEVNT1          HRTIM_RST2R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_RST2R_TIMEVNT2_Pos      (13U)

+#define HRTIM_RST2R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_RST2R_TIMEVNT2          HRTIM_RST2R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_RST2R_TIMEVNT3_Pos      (14U)

+#define HRTIM_RST2R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_RST2R_TIMEVNT3          HRTIM_RST2R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_RST2R_TIMEVNT4_Pos      (15U)

+#define HRTIM_RST2R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_RST2R_TIMEVNT4          HRTIM_RST2R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_RST2R_TIMEVNT5_Pos      (16U)

+#define HRTIM_RST2R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_RST2R_TIMEVNT5          HRTIM_RST2R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_RST2R_TIMEVNT6_Pos      (17U)

+#define HRTIM_RST2R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_RST2R_TIMEVNT6          HRTIM_RST2R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_RST2R_TIMEVNT7_Pos      (18U)

+#define HRTIM_RST2R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_RST2R_TIMEVNT7          HRTIM_RST2R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_RST2R_TIMEVNT8_Pos      (19U)

+#define HRTIM_RST2R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_RST2R_TIMEVNT8          HRTIM_RST2R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_RST2R_TIMEVNT9_Pos      (20U)

+#define HRTIM_RST2R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_RST2R_TIMEVNT9          HRTIM_RST2R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_RST2R_EXTVNT1_Pos       (21U)

+#define HRTIM_RST2R_EXTVNT1_Msk       (0x1UL << HRTIM_RST2R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_RST2R_EXTVNT1           HRTIM_RST2R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_RST2R_EXTVNT2_Pos       (22U)

+#define HRTIM_RST2R_EXTVNT2_Msk       (0x1UL << HRTIM_RST2R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_RST2R_EXTVNT2           HRTIM_RST2R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_RST2R_EXTVNT3_Pos       (23U)

+#define HRTIM_RST2R_EXTVNT3_Msk       (0x1UL << HRTIM_RST2R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_RST2R_EXTVNT3           HRTIM_RST2R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_RST2R_EXTVNT4_Pos       (24U)

+#define HRTIM_RST2R_EXTVNT4_Msk       (0x1UL << HRTIM_RST2R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_RST2R_EXTVNT4           HRTIM_RST2R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_RST2R_EXTVNT5_Pos       (25U)

+#define HRTIM_RST2R_EXTVNT5_Msk       (0x1UL << HRTIM_RST2R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_RST2R_EXTVNT5           HRTIM_RST2R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_RST2R_EXTVNT6_Pos       (26U)

+#define HRTIM_RST2R_EXTVNT6_Msk       (0x1UL << HRTIM_RST2R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_RST2R_EXTVNT6           HRTIM_RST2R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_RST2R_EXTVNT7_Pos       (27U)

+#define HRTIM_RST2R_EXTVNT7_Msk       (0x1UL << HRTIM_RST2R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_RST2R_EXTVNT7           HRTIM_RST2R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_RST2R_EXTVNT8_Pos       (28U)

+#define HRTIM_RST2R_EXTVNT8_Msk       (0x1UL << HRTIM_RST2R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_RST2R_EXTVNT8           HRTIM_RST2R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_RST2R_EXTVNT9_Pos       (29U)

+#define HRTIM_RST2R_EXTVNT9_Msk       (0x1UL << HRTIM_RST2R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_RST2R_EXTVNT9           HRTIM_RST2R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_RST2R_EXTVNT10_Pos      (30U)

+#define HRTIM_RST2R_EXTVNT10_Msk      (0x1UL << HRTIM_RST2R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_RST2R_EXTVNT10          HRTIM_RST2R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_RST2R_UPDATE_Pos        (31U)

+#define HRTIM_RST2R_UPDATE_Msk        (0x1UL << HRTIM_RST2R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_RST2R_UPDATE            HRTIM_RST2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+/**** Bit definition for Slave external event filtering  register 1 ***********/

+#define HRTIM_EEFR1_EE1LTCH_Pos       (0U)

+#define HRTIM_EEFR1_EE1LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos)       /*!< 0x00000001 */

+#define HRTIM_EEFR1_EE1LTCH           HRTIM_EEFR1_EE1LTCH_Msk                  /*!< External Event 1 latch */

+#define HRTIM_EEFR1_EE1FLTR_Pos       (1U)

+#define HRTIM_EEFR1_EE1FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos)       /*!< 0x0000001E */

+#define HRTIM_EEFR1_EE1FLTR           HRTIM_EEFR1_EE1FLTR_Msk                  /*!< External Event 1 filter mask */

+#define HRTIM_EEFR1_EE1FLTR_0         (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000002 */

+#define HRTIM_EEFR1_EE1FLTR_1         (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000004 */

+#define HRTIM_EEFR1_EE1FLTR_2         (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000008 */

+#define HRTIM_EEFR1_EE1FLTR_3         (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000010 */

+

+#define HRTIM_EEFR1_EE2LTCH_Pos       (6U)

+#define HRTIM_EEFR1_EE2LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos)       /*!< 0x00000040 */

+#define HRTIM_EEFR1_EE2LTCH           HRTIM_EEFR1_EE2LTCH_Msk                  /*!< External Event 2 latch */

+#define HRTIM_EEFR1_EE2FLTR_Pos       (7U)

+#define HRTIM_EEFR1_EE2FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos)       /*!< 0x00000780 */

+#define HRTIM_EEFR1_EE2FLTR           HRTIM_EEFR1_EE2FLTR_Msk                  /*!< External Event 2 filter mask */

+#define HRTIM_EEFR1_EE2FLTR_0         (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000080 */

+#define HRTIM_EEFR1_EE2FLTR_1         (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000100 */

+#define HRTIM_EEFR1_EE2FLTR_2         (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000200 */

+#define HRTIM_EEFR1_EE2FLTR_3         (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000400 */

+

+#define HRTIM_EEFR1_EE3LTCH_Pos       (12U)

+#define HRTIM_EEFR1_EE3LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos)       /*!< 0x00001000 */

+#define HRTIM_EEFR1_EE3LTCH           HRTIM_EEFR1_EE3LTCH_Msk                  /*!< External Event 3 latch */

+#define HRTIM_EEFR1_EE3FLTR_Pos       (13U)

+#define HRTIM_EEFR1_EE3FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos)       /*!< 0x0001E000 */

+#define HRTIM_EEFR1_EE3FLTR           HRTIM_EEFR1_EE3FLTR_Msk                  /*!< External Event 3 filter mask */

+#define HRTIM_EEFR1_EE3FLTR_0         (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00002000 */

+#define HRTIM_EEFR1_EE3FLTR_1         (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00004000 */

+#define HRTIM_EEFR1_EE3FLTR_2         (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00008000 */

+#define HRTIM_EEFR1_EE3FLTR_3         (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00010000 */

+

+#define HRTIM_EEFR1_EE4LTCH_Pos       (18U)

+#define HRTIM_EEFR1_EE4LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos)       /*!< 0x00040000 */

+#define HRTIM_EEFR1_EE4LTCH           HRTIM_EEFR1_EE4LTCH_Msk                  /*!< External Event 4 latch */

+#define HRTIM_EEFR1_EE4FLTR_Pos       (19U)

+#define HRTIM_EEFR1_EE4FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos)       /*!< 0x00780000 */

+#define HRTIM_EEFR1_EE4FLTR           HRTIM_EEFR1_EE4FLTR_Msk                  /*!< External Event 4 filter mask */

+#define HRTIM_EEFR1_EE4FLTR_0         (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00080000 */

+#define HRTIM_EEFR1_EE4FLTR_1         (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00100000 */

+#define HRTIM_EEFR1_EE4FLTR_2         (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00200000 */

+#define HRTIM_EEFR1_EE4FLTR_3         (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00400000 */

+

+#define HRTIM_EEFR1_EE5LTCH_Pos       (24U)

+#define HRTIM_EEFR1_EE5LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos)       /*!< 0x01000000 */

+#define HRTIM_EEFR1_EE5LTCH           HRTIM_EEFR1_EE5LTCH_Msk                  /*!< External Event 5 latch */

+#define HRTIM_EEFR1_EE5FLTR_Pos       (25U)

+#define HRTIM_EEFR1_EE5FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos)       /*!< 0x1E000000 */

+#define HRTIM_EEFR1_EE5FLTR           HRTIM_EEFR1_EE5FLTR_Msk                  /*!< External Event 5 filter mask */

+#define HRTIM_EEFR1_EE5FLTR_0         (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x02000000 */

+#define HRTIM_EEFR1_EE5FLTR_1         (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x04000000 */

+#define HRTIM_EEFR1_EE5FLTR_2         (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x08000000 */

+#define HRTIM_EEFR1_EE5FLTR_3         (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x10000000 */

+

+/**** Bit definition for Slave external event filtering  register 2 ***********/

+#define HRTIM_EEFR2_EE6LTCH_Pos       (0U)

+#define HRTIM_EEFR2_EE6LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos)       /*!< 0x00000001 */

+#define HRTIM_EEFR2_EE6LTCH           HRTIM_EEFR2_EE6LTCH_Msk                  /*!< External Event 6 latch */

+#define HRTIM_EEFR2_EE6FLTR_Pos       (1U)

+#define HRTIM_EEFR2_EE6FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos)       /*!< 0x0000001E */

+#define HRTIM_EEFR2_EE6FLTR           HRTIM_EEFR2_EE6FLTR_Msk                  /*!< External Event 6 filter mask */

+#define HRTIM_EEFR2_EE6FLTR_0         (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000002 */

+#define HRTIM_EEFR2_EE6FLTR_1         (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000004 */

+#define HRTIM_EEFR2_EE6FLTR_2         (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000008 */

+#define HRTIM_EEFR2_EE6FLTR_3         (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000010 */

+

+#define HRTIM_EEFR2_EE7LTCH_Pos       (6U)

+#define HRTIM_EEFR2_EE7LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos)       /*!< 0x00000040 */

+#define HRTIM_EEFR2_EE7LTCH           HRTIM_EEFR2_EE7LTCH_Msk                  /*!< External Event 7 latch */

+#define HRTIM_EEFR2_EE7FLTR_Pos       (7U)

+#define HRTIM_EEFR2_EE7FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos)       /*!< 0x00000780 */

+#define HRTIM_EEFR2_EE7FLTR           HRTIM_EEFR2_EE7FLTR_Msk                  /*!< External Event 7 filter mask */

+#define HRTIM_EEFR2_EE7FLTR_0         (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000080 */

+#define HRTIM_EEFR2_EE7FLTR_1         (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000100 */

+#define HRTIM_EEFR2_EE7FLTR_2         (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000200 */

+#define HRTIM_EEFR2_EE7FLTR_3         (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000400 */

+

+#define HRTIM_EEFR2_EE8LTCH_Pos       (12U)

+#define HRTIM_EEFR2_EE8LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos)       /*!< 0x00001000 */

+#define HRTIM_EEFR2_EE8LTCH           HRTIM_EEFR2_EE8LTCH_Msk                  /*!< External Event 8 latch */

+#define HRTIM_EEFR2_EE8FLTR_Pos       (13U)

+#define HRTIM_EEFR2_EE8FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos)       /*!< 0x0001E000 */

+#define HRTIM_EEFR2_EE8FLTR           HRTIM_EEFR2_EE8FLTR_Msk                  /*!< External Event 8 filter mask */

+#define HRTIM_EEFR2_EE8FLTR_0         (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00002000 */

+#define HRTIM_EEFR2_EE8FLTR_1         (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00004000 */

+#define HRTIM_EEFR2_EE8FLTR_2         (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00008000 */

+#define HRTIM_EEFR2_EE8FLTR_3         (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00010000 */

+

+#define HRTIM_EEFR2_EE9LTCH_Pos       (18U)

+#define HRTIM_EEFR2_EE9LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos)       /*!< 0x00040000 */

+#define HRTIM_EEFR2_EE9LTCH           HRTIM_EEFR2_EE9LTCH_Msk                  /*!< External Event 9 latch */

+#define HRTIM_EEFR2_EE9FLTR_Pos       (19U)

+#define HRTIM_EEFR2_EE9FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos)       /*!< 0x00780000 */

+#define HRTIM_EEFR2_EE9FLTR           HRTIM_EEFR2_EE9FLTR_Msk                  /*!< External Event 9 filter mask */

+#define HRTIM_EEFR2_EE9FLTR_0         (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00080000 */

+#define HRTIM_EEFR2_EE9FLTR_1         (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00100000 */

+#define HRTIM_EEFR2_EE9FLTR_2         (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00200000 */

+#define HRTIM_EEFR2_EE9FLTR_3         (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00400000 */

+

+#define HRTIM_EEFR2_EE10LTCH_Pos      (24U)

+#define HRTIM_EEFR2_EE10LTCH_Msk      (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos)      /*!< 0x01000000 */

+#define HRTIM_EEFR2_EE10LTCH          HRTIM_EEFR2_EE10LTCH_Msk                 /*!< External Event 10 latch */

+#define HRTIM_EEFR2_EE10FLTR_Pos      (25U)

+#define HRTIM_EEFR2_EE10FLTR_Msk      (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos)      /*!< 0x1E000000 */

+#define HRTIM_EEFR2_EE10FLTR          HRTIM_EEFR2_EE10FLTR_Msk                 /*!< External Event 10 filter mask */

+#define HRTIM_EEFR2_EE10FLTR_0        (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x02000000 */

+#define HRTIM_EEFR2_EE10FLTR_1        (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x04000000 */

+#define HRTIM_EEFR2_EE10FLTR_2        (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x08000000 */

+#define HRTIM_EEFR2_EE10FLTR_3        (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x10000000 */

+

+/**** Bit definition for Slave Timer reset register ***************************/

+#define HRTIM_RSTR_UPDATE_Pos         (1U)

+#define HRTIM_RSTR_UPDATE_Msk         (0x1UL << HRTIM_RSTR_UPDATE_Pos)         /*!< 0x00000002 */

+#define HRTIM_RSTR_UPDATE             HRTIM_RSTR_UPDATE_Msk                    /*!< Timer update */

+#define HRTIM_RSTR_CMP2_Pos           (2U)

+#define HRTIM_RSTR_CMP2_Msk           (0x1UL << HRTIM_RSTR_CMP2_Pos)           /*!< 0x00000004 */

+#define HRTIM_RSTR_CMP2               HRTIM_RSTR_CMP2_Msk                      /*!< Timer compare2 */

+#define HRTIM_RSTR_CMP4_Pos           (3U)

+#define HRTIM_RSTR_CMP4_Msk           (0x1UL << HRTIM_RSTR_CMP4_Pos)           /*!< 0x00000008 */

+#define HRTIM_RSTR_CMP4               HRTIM_RSTR_CMP4_Msk                      /*!< Timer compare4 */

+

+#define HRTIM_RSTR_MSTPER_Pos         (4U)

+#define HRTIM_RSTR_MSTPER_Msk         (0x1UL << HRTIM_RSTR_MSTPER_Pos)         /*!< 0x00000010 */

+#define HRTIM_RSTR_MSTPER             HRTIM_RSTR_MSTPER_Msk                    /*!< Master period */

+#define HRTIM_RSTR_MSTCMP1_Pos        (5U)

+#define HRTIM_RSTR_MSTCMP1_Msk        (0x1UL << HRTIM_RSTR_MSTCMP1_Pos)        /*!< 0x00000020 */

+#define HRTIM_RSTR_MSTCMP1            HRTIM_RSTR_MSTCMP1_Msk                   /*!< Master compare1 */

+#define HRTIM_RSTR_MSTCMP2_Pos        (6U)

+#define HRTIM_RSTR_MSTCMP2_Msk        (0x1UL << HRTIM_RSTR_MSTCMP2_Pos)        /*!< 0x00000040 */

+#define HRTIM_RSTR_MSTCMP2            HRTIM_RSTR_MSTCMP2_Msk                   /*!< Master compare2 */

+#define HRTIM_RSTR_MSTCMP3_Pos        (7U)

+#define HRTIM_RSTR_MSTCMP3_Msk        (0x1UL << HRTIM_RSTR_MSTCMP3_Pos)        /*!< 0x00000080 */

+#define HRTIM_RSTR_MSTCMP3            HRTIM_RSTR_MSTCMP3_Msk                   /*!< Master compare3 */

+#define HRTIM_RSTR_MSTCMP4_Pos        (8U)

+#define HRTIM_RSTR_MSTCMP4_Msk        (0x1UL << HRTIM_RSTR_MSTCMP4_Pos)        /*!< 0x00000100 */

+#define HRTIM_RSTR_MSTCMP4            HRTIM_RSTR_MSTCMP4_Msk                   /*!< Master compare4 */

+

+#define HRTIM_RSTR_EXTEVNT1_Pos       (9U)

+#define HRTIM_RSTR_EXTEVNT1_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos)       /*!< 0x00000200 */

+#define HRTIM_RSTR_EXTEVNT1           HRTIM_RSTR_EXTEVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_RSTR_EXTEVNT2_Pos       (10U)

+#define HRTIM_RSTR_EXTEVNT2_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos)       /*!< 0x00000400 */

+#define HRTIM_RSTR_EXTEVNT2           HRTIM_RSTR_EXTEVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_RSTR_EXTEVNT3_Pos       (11U)

+#define HRTIM_RSTR_EXTEVNT3_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos)       /*!< 0x00000800 */

+#define HRTIM_RSTR_EXTEVNT3           HRTIM_RSTR_EXTEVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_RSTR_EXTEVNT4_Pos       (12U)

+#define HRTIM_RSTR_EXTEVNT4_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos)       /*!< 0x00001000 */

+#define HRTIM_RSTR_EXTEVNT4           HRTIM_RSTR_EXTEVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_RSTR_EXTEVNT5_Pos       (13U)

+#define HRTIM_RSTR_EXTEVNT5_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos)       /*!< 0x00002000 */

+#define HRTIM_RSTR_EXTEVNT5           HRTIM_RSTR_EXTEVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_RSTR_EXTEVNT6_Pos       (14U)

+#define HRTIM_RSTR_EXTEVNT6_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos)       /*!< 0x00004000 */

+#define HRTIM_RSTR_EXTEVNT6           HRTIM_RSTR_EXTEVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_RSTR_EXTEVNT7_Pos       (15U)

+#define HRTIM_RSTR_EXTEVNT7_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos)       /*!< 0x00008000 */

+#define HRTIM_RSTR_EXTEVNT7           HRTIM_RSTR_EXTEVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_RSTR_EXTEVNT8_Pos       (16U)

+#define HRTIM_RSTR_EXTEVNT8_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos)       /*!< 0x00010000 */

+#define HRTIM_RSTR_EXTEVNT8           HRTIM_RSTR_EXTEVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_RSTR_EXTEVNT9_Pos       (17U)

+#define HRTIM_RSTR_EXTEVNT9_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos)       /*!< 0x00020000 */

+#define HRTIM_RSTR_EXTEVNT9           HRTIM_RSTR_EXTEVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_RSTR_EXTEVNT10_Pos      (18U)

+#define HRTIM_RSTR_EXTEVNT10_Msk      (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos)      /*!< 0x00040000 */

+#define HRTIM_RSTR_EXTEVNT10          HRTIM_RSTR_EXTEVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_RSTR_TIMBCMP1_Pos       (19U)

+#define HRTIM_RSTR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos)       /*!< 0x00080000 */

+#define HRTIM_RSTR_TIMBCMP1           HRTIM_RSTR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */

+#define HRTIM_RSTR_TIMBCMP2_Pos       (20U)

+#define HRTIM_RSTR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos)       /*!< 0x00100000 */

+#define HRTIM_RSTR_TIMBCMP2           HRTIM_RSTR_TIMBCMP2_Msk                  /*!< Timer B compare 2 */

+#define HRTIM_RSTR_TIMBCMP4_Pos       (21U)

+#define HRTIM_RSTR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos)       /*!< 0x00200000 */

+#define HRTIM_RSTR_TIMBCMP4           HRTIM_RSTR_TIMBCMP4_Msk                  /*!< Timer B compare 4 */

+

+#define HRTIM_RSTR_TIMCCMP1_Pos       (22U)

+#define HRTIM_RSTR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos)       /*!< 0x00400000 */

+#define HRTIM_RSTR_TIMCCMP1           HRTIM_RSTR_TIMCCMP1_Msk                  /*!< Timer C compare 1 */

+#define HRTIM_RSTR_TIMCCMP2_Pos       (23U)

+#define HRTIM_RSTR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos)       /*!< 0x00800000 */

+#define HRTIM_RSTR_TIMCCMP2           HRTIM_RSTR_TIMCCMP2_Msk                  /*!< Timer C compare 2 */

+#define HRTIM_RSTR_TIMCCMP4_Pos       (24U)

+#define HRTIM_RSTR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos)       /*!< 0x01000000 */

+#define HRTIM_RSTR_TIMCCMP4           HRTIM_RSTR_TIMCCMP4_Msk                  /*!< Timer C compare 4 */

+

+#define HRTIM_RSTR_TIMDCMP1_Pos       (25U)

+#define HRTIM_RSTR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos)       /*!< 0x02000000 */

+#define HRTIM_RSTR_TIMDCMP1           HRTIM_RSTR_TIMDCMP1_Msk                  /*!< Timer D compare 1 */

+#define HRTIM_RSTR_TIMDCMP2_Pos       (26U)

+#define HRTIM_RSTR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos)       /*!< 0x04000000 */

+#define HRTIM_RSTR_TIMDCMP2           HRTIM_RSTR_TIMDCMP2_Msk                  /*!< Timer D compare 2 */

+#define HRTIM_RSTR_TIMDCMP4_Pos       (27U)

+#define HRTIM_RSTR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos)       /*!< 0x08000000 */

+#define HRTIM_RSTR_TIMDCMP4           HRTIM_RSTR_TIMDCMP4_Msk                  /*!< Timer D compare 4 */

+

+#define HRTIM_RSTR_TIMECMP1_Pos       (28U)

+#define HRTIM_RSTR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTR_TIMECMP1_Pos)       /*!< 0x10000000 */

+#define HRTIM_RSTR_TIMECMP1           HRTIM_RSTR_TIMECMP1_Msk                  /*!< Timer E compare 1 */

+#define HRTIM_RSTR_TIMECMP2_Pos       (29U)

+#define HRTIM_RSTR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTR_TIMECMP2_Pos)       /*!< 0x20000000 */

+#define HRTIM_RSTR_TIMECMP2           HRTIM_RSTR_TIMECMP2_Msk                  /*!< Timer E compare 2 */

+#define HRTIM_RSTR_TIMECMP4_Pos       (30U)

+#define HRTIM_RSTR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTR_TIMECMP4_Pos)       /*!< 0x40000000 */

+#define HRTIM_RSTR_TIMECMP4           HRTIM_RSTR_TIMECMP4_Msk                  /*!< Timer E compare 4 */

+

+/**** Bit definition for Slave Timer Chopper register *************************/

+#define HRTIM_CHPR_CARFRQ_Pos         (0U)

+#define HRTIM_CHPR_CARFRQ_Msk         (0xFUL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x0000000F */

+#define HRTIM_CHPR_CARFRQ             HRTIM_CHPR_CARFRQ_Msk                    /*!< Timer carrier frequency value */

+#define HRTIM_CHPR_CARFRQ_0           (0x1UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000001 */

+#define HRTIM_CHPR_CARFRQ_1           (0x2UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000002 */

+#define HRTIM_CHPR_CARFRQ_2           (0x4UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000004 */

+#define HRTIM_CHPR_CARFRQ_3           (0x8UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000008 */

+

+#define HRTIM_CHPR_CARDTY_Pos         (4U)

+#define HRTIM_CHPR_CARDTY_Msk         (0x7UL << HRTIM_CHPR_CARDTY_Pos)         /*!< 0x00000070 */

+#define HRTIM_CHPR_CARDTY             HRTIM_CHPR_CARDTY_Msk                    /*!< Timer chopper duty cycle value */

+#define HRTIM_CHPR_CARDTY_0           (0x1UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000010 */

+#define HRTIM_CHPR_CARDTY_1           (0x2UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000020 */

+#define HRTIM_CHPR_CARDTY_2           (0x4UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000040 */

+

+#define HRTIM_CHPR_STRPW_Pos          (7U)

+#define HRTIM_CHPR_STRPW_Msk          (0xFUL << HRTIM_CHPR_STRPW_Pos)          /*!< 0x00000780 */

+#define HRTIM_CHPR_STRPW              HRTIM_CHPR_STRPW_Msk                     /*!< Timer start pulse width value */

+#define HRTIM_CHPR_STRPW_0            (0x1UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000080 */

+#define HRTIM_CHPR_STRPW_1            (0x2UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000100 */

+#define HRTIM_CHPR_STRPW_2            (0x4UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000200 */

+#define HRTIM_CHPR_STRPW_3            (0x8UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000400 */

+

+/**** Bit definition for Slave Timer Capture 1 control register ***************/

+#define HRTIM_CPT1CR_SWCPT_Pos        (0U)

+#define HRTIM_CPT1CR_SWCPT_Msk        (0x1UL << HRTIM_CPT1CR_SWCPT_Pos)        /*!< 0x00000001 */

+#define HRTIM_CPT1CR_SWCPT            HRTIM_CPT1CR_SWCPT_Msk                   /*!< Software capture */

+#define HRTIM_CPT1CR_UPDCPT_Pos       (1U)

+#define HRTIM_CPT1CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos)       /*!< 0x00000002 */

+#define HRTIM_CPT1CR_UPDCPT           HRTIM_CPT1CR_UPDCPT_Msk                  /*!< Update capture */

+#define HRTIM_CPT1CR_EXEV1CPT_Pos     (2U)

+#define HRTIM_CPT1CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos)     /*!< 0x00000004 */

+#define HRTIM_CPT1CR_EXEV1CPT         HRTIM_CPT1CR_EXEV1CPT_Msk                /*!< External event 1 capture */

+#define HRTIM_CPT1CR_EXEV2CPT_Pos     (3U)

+#define HRTIM_CPT1CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos)     /*!< 0x00000008 */

+#define HRTIM_CPT1CR_EXEV2CPT         HRTIM_CPT1CR_EXEV2CPT_Msk                /*!< External event 2 capture */

+#define HRTIM_CPT1CR_EXEV3CPT_Pos     (4U)

+#define HRTIM_CPT1CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos)     /*!< 0x00000010 */

+#define HRTIM_CPT1CR_EXEV3CPT         HRTIM_CPT1CR_EXEV3CPT_Msk                /*!< External event 3 capture */

+#define HRTIM_CPT1CR_EXEV4CPT_Pos     (5U)

+#define HRTIM_CPT1CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos)     /*!< 0x00000020 */

+#define HRTIM_CPT1CR_EXEV4CPT         HRTIM_CPT1CR_EXEV4CPT_Msk                /*!< External event 4 capture */

+#define HRTIM_CPT1CR_EXEV5CPT_Pos     (6U)

+#define HRTIM_CPT1CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos)     /*!< 0x00000040 */

+#define HRTIM_CPT1CR_EXEV5CPT         HRTIM_CPT1CR_EXEV5CPT_Msk                /*!< External event 5 capture */

+#define HRTIM_CPT1CR_EXEV6CPT_Pos     (7U)

+#define HRTIM_CPT1CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos)     /*!< 0x00000080 */

+#define HRTIM_CPT1CR_EXEV6CPT         HRTIM_CPT1CR_EXEV6CPT_Msk                /*!< External event 6 capture */

+#define HRTIM_CPT1CR_EXEV7CPT_Pos     (8U)

+#define HRTIM_CPT1CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos)     /*!< 0x00000100 */

+#define HRTIM_CPT1CR_EXEV7CPT         HRTIM_CPT1CR_EXEV7CPT_Msk                /*!< External event 7 capture */

+#define HRTIM_CPT1CR_EXEV8CPT_Pos     (9U)

+#define HRTIM_CPT1CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos)     /*!< 0x00000200 */

+#define HRTIM_CPT1CR_EXEV8CPT         HRTIM_CPT1CR_EXEV8CPT_Msk                /*!< External event 8 capture */

+#define HRTIM_CPT1CR_EXEV9CPT_Pos     (10U)

+#define HRTIM_CPT1CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos)     /*!< 0x00000400 */

+#define HRTIM_CPT1CR_EXEV9CPT         HRTIM_CPT1CR_EXEV9CPT_Msk                /*!< External event 9 capture */

+#define HRTIM_CPT1CR_EXEV10CPT_Pos    (11U)

+#define HRTIM_CPT1CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos)    /*!< 0x00000800 */

+#define HRTIM_CPT1CR_EXEV10CPT        HRTIM_CPT1CR_EXEV10CPT_Msk               /*!< External event 10 capture */

+

+#define HRTIM_CPT1CR_TA1SET_Pos       (12U)

+#define HRTIM_CPT1CR_TA1SET_Msk       (0x1UL << HRTIM_CPT1CR_TA1SET_Pos)       /*!< 0x00001000 */

+#define HRTIM_CPT1CR_TA1SET           HRTIM_CPT1CR_TA1SET_Msk                  /*!< Timer A output 1 set */

+#define HRTIM_CPT1CR_TA1RST_Pos       (13U)

+#define HRTIM_CPT1CR_TA1RST_Msk       (0x1UL << HRTIM_CPT1CR_TA1RST_Pos)       /*!< 0x00002000 */

+#define HRTIM_CPT1CR_TA1RST           HRTIM_CPT1CR_TA1RST_Msk                  /*!< Timer A output 1 reset */

+#define HRTIM_CPT1CR_TIMACMP1_Pos     (14U)

+#define HRTIM_CPT1CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos)     /*!< 0x00004000 */

+#define HRTIM_CPT1CR_TIMACMP1         HRTIM_CPT1CR_TIMACMP1_Msk                /*!< Timer A compare 1 */

+#define HRTIM_CPT1CR_TIMACMP2_Pos     (15U)

+#define HRTIM_CPT1CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos)     /*!< 0x00008000 */

+#define HRTIM_CPT1CR_TIMACMP2         HRTIM_CPT1CR_TIMACMP2_Msk                /*!< Timer A compare 2 */

+

+#define HRTIM_CPT1CR_TB1SET_Pos       (16U)

+#define HRTIM_CPT1CR_TB1SET_Msk       (0x1UL << HRTIM_CPT1CR_TB1SET_Pos)       /*!< 0x00010000 */

+#define HRTIM_CPT1CR_TB1SET           HRTIM_CPT1CR_TB1SET_Msk                  /*!< Timer B output 1 set */

+#define HRTIM_CPT1CR_TB1RST_Pos       (17U)

+#define HRTIM_CPT1CR_TB1RST_Msk       (0x1UL << HRTIM_CPT1CR_TB1RST_Pos)       /*!< 0x00020000 */

+#define HRTIM_CPT1CR_TB1RST           HRTIM_CPT1CR_TB1RST_Msk                  /*!< Timer B output 1 reset */

+#define HRTIM_CPT1CR_TIMBCMP1_Pos     (18U)

+#define HRTIM_CPT1CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos)     /*!< 0x00040000 */

+#define HRTIM_CPT1CR_TIMBCMP1         HRTIM_CPT1CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */

+#define HRTIM_CPT1CR_TIMBCMP2_Pos     (19U)

+#define HRTIM_CPT1CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos)     /*!< 0x00080000 */

+#define HRTIM_CPT1CR_TIMBCMP2         HRTIM_CPT1CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */

+

+#define HRTIM_CPT1CR_TC1SET_Pos       (20U)

+#define HRTIM_CPT1CR_TC1SET_Msk       (0x1UL << HRTIM_CPT1CR_TC1SET_Pos)       /*!< 0x00100000 */

+#define HRTIM_CPT1CR_TC1SET           HRTIM_CPT1CR_TC1SET_Msk                  /*!< Timer C output 1 set */

+#define HRTIM_CPT1CR_TC1RST_Pos       (21U)

+#define HRTIM_CPT1CR_TC1RST_Msk       (0x1UL << HRTIM_CPT1CR_TC1RST_Pos)       /*!< 0x00200000 */

+#define HRTIM_CPT1CR_TC1RST           HRTIM_CPT1CR_TC1RST_Msk                  /*!< Timer C output 1 reset */

+#define HRTIM_CPT1CR_TIMCCMP1_Pos     (22U)

+#define HRTIM_CPT1CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos)     /*!< 0x00400000 */

+#define HRTIM_CPT1CR_TIMCCMP1         HRTIM_CPT1CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */

+#define HRTIM_CPT1CR_TIMCCMP2_Pos     (23U)

+#define HRTIM_CPT1CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos)     /*!< 0x00800000 */

+#define HRTIM_CPT1CR_TIMCCMP2         HRTIM_CPT1CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */

+

+#define HRTIM_CPT1CR_TD1SET_Pos       (24U)

+#define HRTIM_CPT1CR_TD1SET_Msk       (0x1UL << HRTIM_CPT1CR_TD1SET_Pos)       /*!< 0x01000000 */

+#define HRTIM_CPT1CR_TD1SET           HRTIM_CPT1CR_TD1SET_Msk                  /*!< Timer D output 1 set */

+#define HRTIM_CPT1CR_TD1RST_Pos       (25U)

+#define HRTIM_CPT1CR_TD1RST_Msk       (0x1UL << HRTIM_CPT1CR_TD1RST_Pos)       /*!< 0x02000000 */

+#define HRTIM_CPT1CR_TD1RST           HRTIM_CPT1CR_TD1RST_Msk                  /*!< Timer D output 1 reset */

+#define HRTIM_CPT1CR_TIMDCMP1_Pos     (26U)

+#define HRTIM_CPT1CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos)     /*!< 0x04000000 */

+#define HRTIM_CPT1CR_TIMDCMP1         HRTIM_CPT1CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */

+#define HRTIM_CPT1CR_TIMDCMP2_Pos     (27U)

+#define HRTIM_CPT1CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos)     /*!< 0x08000000 */

+#define HRTIM_CPT1CR_TIMDCMP2         HRTIM_CPT1CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */

+

+#define HRTIM_CPT1CR_TE1SET_Pos       (28U)

+#define HRTIM_CPT1CR_TE1SET_Msk       (0x1UL << HRTIM_CPT1CR_TE1SET_Pos)       /*!< 0x10000000 */

+#define HRTIM_CPT1CR_TE1SET           HRTIM_CPT1CR_TE1SET_Msk                  /*!< Timer E output 1 set */

+#define HRTIM_CPT1CR_TE1RST_Pos       (29U)

+#define HRTIM_CPT1CR_TE1RST_Msk       (0x1UL << HRTIM_CPT1CR_TE1RST_Pos)       /*!< 0x20000000 */

+#define HRTIM_CPT1CR_TE1RST           HRTIM_CPT1CR_TE1RST_Msk                  /*!< Timer E output 1 reset */

+#define HRTIM_CPT1CR_TIMECMP1_Pos     (30U)

+#define HRTIM_CPT1CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos)     /*!< 0x40000000 */

+#define HRTIM_CPT1CR_TIMECMP1         HRTIM_CPT1CR_TIMECMP1_Msk                /*!< Timer E compare 1 */

+#define HRTIM_CPT1CR_TIMECMP2_Pos     (31U)

+#define HRTIM_CPT1CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos)     /*!< 0x80000000 */

+#define HRTIM_CPT1CR_TIMECMP2         HRTIM_CPT1CR_TIMECMP2_Msk                /*!< Timer E compare 2 */

+

+/**** Bit definition for Slave Timer Capture 2 control register ***************/

+#define HRTIM_CPT2CR_SWCPT_Pos        (0U)

+#define HRTIM_CPT2CR_SWCPT_Msk        (0x1UL << HRTIM_CPT2CR_SWCPT_Pos)        /*!< 0x00000001 */

+#define HRTIM_CPT2CR_SWCPT            HRTIM_CPT2CR_SWCPT_Msk                   /*!< Software capture */

+#define HRTIM_CPT2CR_UPDCPT_Pos       (1U)

+#define HRTIM_CPT2CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos)       /*!< 0x00000002 */

+#define HRTIM_CPT2CR_UPDCPT           HRTIM_CPT2CR_UPDCPT_Msk                  /*!< Update capture */

+#define HRTIM_CPT2CR_EXEV1CPT_Pos     (2U)

+#define HRTIM_CPT2CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos)     /*!< 0x00000004 */

+#define HRTIM_CPT2CR_EXEV1CPT         HRTIM_CPT2CR_EXEV1CPT_Msk                /*!< External event 1 capture */

+#define HRTIM_CPT2CR_EXEV2CPT_Pos     (3U)

+#define HRTIM_CPT2CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos)     /*!< 0x00000008 */

+#define HRTIM_CPT2CR_EXEV2CPT         HRTIM_CPT2CR_EXEV2CPT_Msk                /*!< External event 2 capture */

+#define HRTIM_CPT2CR_EXEV3CPT_Pos     (4U)

+#define HRTIM_CPT2CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos)     /*!< 0x00000010 */

+#define HRTIM_CPT2CR_EXEV3CPT         HRTIM_CPT2CR_EXEV3CPT_Msk                /*!< External event 3 capture */

+#define HRTIM_CPT2CR_EXEV4CPT_Pos     (5U)

+#define HRTIM_CPT2CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos)     /*!< 0x00000020 */

+#define HRTIM_CPT2CR_EXEV4CPT         HRTIM_CPT2CR_EXEV4CPT_Msk                /*!< External event 4 capture */

+#define HRTIM_CPT2CR_EXEV5CPT_Pos     (6U)

+#define HRTIM_CPT2CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos)     /*!< 0x00000040 */

+#define HRTIM_CPT2CR_EXEV5CPT         HRTIM_CPT2CR_EXEV5CPT_Msk                /*!< External event 5 capture */

+#define HRTIM_CPT2CR_EXEV6CPT_Pos     (7U)

+#define HRTIM_CPT2CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos)     /*!< 0x00000080 */

+#define HRTIM_CPT2CR_EXEV6CPT         HRTIM_CPT2CR_EXEV6CPT_Msk                /*!< External event 6 capture */

+#define HRTIM_CPT2CR_EXEV7CPT_Pos     (8U)

+#define HRTIM_CPT2CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos)     /*!< 0x00000100 */

+#define HRTIM_CPT2CR_EXEV7CPT         HRTIM_CPT2CR_EXEV7CPT_Msk                /*!< External event 7 capture */

+#define HRTIM_CPT2CR_EXEV8CPT_Pos     (9U)

+#define HRTIM_CPT2CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos)     /*!< 0x00000200 */

+#define HRTIM_CPT2CR_EXEV8CPT         HRTIM_CPT2CR_EXEV8CPT_Msk                /*!< External event 8 capture */

+#define HRTIM_CPT2CR_EXEV9CPT_Pos     (10U)

+#define HRTIM_CPT2CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos)     /*!< 0x00000400 */

+#define HRTIM_CPT2CR_EXEV9CPT         HRTIM_CPT2CR_EXEV9CPT_Msk                /*!< External event 9 capture */

+#define HRTIM_CPT2CR_EXEV10CPT_Pos    (11U)

+#define HRTIM_CPT2CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos)    /*!< 0x00000800 */

+#define HRTIM_CPT2CR_EXEV10CPT        HRTIM_CPT2CR_EXEV10CPT_Msk               /*!< External event 10 capture */

+

+#define HRTIM_CPT2CR_TA1SET_Pos       (12U)

+#define HRTIM_CPT2CR_TA1SET_Msk       (0x1UL << HRTIM_CPT2CR_TA1SET_Pos)       /*!< 0x00001000 */

+#define HRTIM_CPT2CR_TA1SET           HRTIM_CPT2CR_TA1SET_Msk                  /*!< Timer A output 1 set */

+#define HRTIM_CPT2CR_TA1RST_Pos       (13U)

+#define HRTIM_CPT2CR_TA1RST_Msk       (0x1UL << HRTIM_CPT2CR_TA1RST_Pos)       /*!< 0x00002000 */

+#define HRTIM_CPT2CR_TA1RST           HRTIM_CPT2CR_TA1RST_Msk                  /*!< Timer A output 1 reset */

+#define HRTIM_CPT2CR_TIMACMP1_Pos     (14U)

+#define HRTIM_CPT2CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos)     /*!< 0x00004000 */

+#define HRTIM_CPT2CR_TIMACMP1         HRTIM_CPT2CR_TIMACMP1_Msk                /*!< Timer A compare 1 */

+#define HRTIM_CPT2CR_TIMACMP2_Pos     (15U)

+#define HRTIM_CPT2CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos)     /*!< 0x00008000 */

+#define HRTIM_CPT2CR_TIMACMP2         HRTIM_CPT2CR_TIMACMP2_Msk                /*!< Timer A compare 2 */

+

+#define HRTIM_CPT2CR_TB1SET_Pos       (16U)

+#define HRTIM_CPT2CR_TB1SET_Msk       (0x1UL << HRTIM_CPT2CR_TB1SET_Pos)       /*!< 0x00010000 */

+#define HRTIM_CPT2CR_TB1SET           HRTIM_CPT2CR_TB1SET_Msk                  /*!< Timer B output 1 set */

+#define HRTIM_CPT2CR_TB1RST_Pos       (17U)

+#define HRTIM_CPT2CR_TB1RST_Msk       (0x1UL << HRTIM_CPT2CR_TB1RST_Pos)       /*!< 0x00020000 */

+#define HRTIM_CPT2CR_TB1RST           HRTIM_CPT2CR_TB1RST_Msk                  /*!< Timer B output 1 reset */

+#define HRTIM_CPT2CR_TIMBCMP1_Pos     (18U)

+#define HRTIM_CPT2CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos)     /*!< 0x00040000 */

+#define HRTIM_CPT2CR_TIMBCMP1         HRTIM_CPT2CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */

+#define HRTIM_CPT2CR_TIMBCMP2_Pos     (19U)

+#define HRTIM_CPT2CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos)     /*!< 0x00080000 */

+#define HRTIM_CPT2CR_TIMBCMP2         HRTIM_CPT2CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */

+

+#define HRTIM_CPT2CR_TC1SET_Pos       (20U)

+#define HRTIM_CPT2CR_TC1SET_Msk       (0x1UL << HRTIM_CPT2CR_TC1SET_Pos)       /*!< 0x00100000 */

+#define HRTIM_CPT2CR_TC1SET           HRTIM_CPT2CR_TC1SET_Msk                  /*!< Timer C output 1 set */

+#define HRTIM_CPT2CR_TC1RST_Pos       (21U)

+#define HRTIM_CPT2CR_TC1RST_Msk       (0x1UL << HRTIM_CPT2CR_TC1RST_Pos)       /*!< 0x00200000 */

+#define HRTIM_CPT2CR_TC1RST           HRTIM_CPT2CR_TC1RST_Msk                  /*!< Timer C output 1 reset */

+#define HRTIM_CPT2CR_TIMCCMP1_Pos     (22U)

+#define HRTIM_CPT2CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos)     /*!< 0x00400000 */

+#define HRTIM_CPT2CR_TIMCCMP1         HRTIM_CPT2CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */

+#define HRTIM_CPT2CR_TIMCCMP2_Pos     (23U)

+#define HRTIM_CPT2CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos)     /*!< 0x00800000 */

+#define HRTIM_CPT2CR_TIMCCMP2         HRTIM_CPT2CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */

+

+#define HRTIM_CPT2CR_TD1SET_Pos       (24U)

+#define HRTIM_CPT2CR_TD1SET_Msk       (0x1UL << HRTIM_CPT2CR_TD1SET_Pos)       /*!< 0x01000000 */

+#define HRTIM_CPT2CR_TD1SET           HRTIM_CPT2CR_TD1SET_Msk                  /*!< Timer D output 1 set */

+#define HRTIM_CPT2CR_TD1RST_Pos       (25U)

+#define HRTIM_CPT2CR_TD1RST_Msk       (0x1UL << HRTIM_CPT2CR_TD1RST_Pos)       /*!< 0x02000000 */

+#define HRTIM_CPT2CR_TD1RST           HRTIM_CPT2CR_TD1RST_Msk                  /*!< Timer D output 1 reset */

+#define HRTIM_CPT2CR_TIMDCMP1_Pos     (26U)

+#define HRTIM_CPT2CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos)     /*!< 0x04000000 */

+#define HRTIM_CPT2CR_TIMDCMP1         HRTIM_CPT2CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */

+#define HRTIM_CPT2CR_TIMDCMP2_Pos     (27U)

+#define HRTIM_CPT2CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos)     /*!< 0x08000000 */

+#define HRTIM_CPT2CR_TIMDCMP2         HRTIM_CPT2CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */

+

+#define HRTIM_CPT2CR_TE1SET_Pos       (28U)

+#define HRTIM_CPT2CR_TE1SET_Msk       (0x1UL << HRTIM_CPT2CR_TE1SET_Pos)       /*!< 0x10000000 */

+#define HRTIM_CPT2CR_TE1SET           HRTIM_CPT2CR_TE1SET_Msk                  /*!< Timer E output 1 set */

+#define HRTIM_CPT2CR_TE1RST_Pos       (29U)

+#define HRTIM_CPT2CR_TE1RST_Msk       (0x1UL << HRTIM_CPT2CR_TE1RST_Pos)       /*!< 0x20000000 */

+#define HRTIM_CPT2CR_TE1RST           HRTIM_CPT2CR_TE1RST_Msk                  /*!< Timer E output 1 reset */

+#define HRTIM_CPT2CR_TIMECMP1_Pos     (30U)

+#define HRTIM_CPT2CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos)     /*!< 0x40000000 */

+#define HRTIM_CPT2CR_TIMECMP1         HRTIM_CPT2CR_TIMECMP1_Msk                /*!< Timer E compare 1 */

+#define HRTIM_CPT2CR_TIMECMP2_Pos     (31U)

+#define HRTIM_CPT2CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos)     /*!< 0x80000000 */

+#define HRTIM_CPT2CR_TIMECMP2         HRTIM_CPT2CR_TIMECMP2_Msk                /*!< Timer E compare 2 */

+

+/**** Bit definition for Slave Timer Output register **************************/

+#define HRTIM_OUTR_POL1_Pos           (1U)

+#define HRTIM_OUTR_POL1_Msk           (0x1UL << HRTIM_OUTR_POL1_Pos)           /*!< 0x00000002 */

+#define HRTIM_OUTR_POL1               HRTIM_OUTR_POL1_Msk                      /*!< Slave output 1 polarity */

+#define HRTIM_OUTR_IDLM1_Pos          (2U)

+#define HRTIM_OUTR_IDLM1_Msk          (0x1UL << HRTIM_OUTR_IDLM1_Pos)          /*!< 0x00000004 */

+#define HRTIM_OUTR_IDLM1              HRTIM_OUTR_IDLM1_Msk                     /*!< Slave output 1 idle mode */

+#define HRTIM_OUTR_IDLES1_Pos         (3U)

+#define HRTIM_OUTR_IDLES1_Msk         (0x1UL << HRTIM_OUTR_IDLES1_Pos)         /*!< 0x00000008 */

+#define HRTIM_OUTR_IDLES1             HRTIM_OUTR_IDLES1_Msk                    /*!< Slave output 1 idle state */

+#define HRTIM_OUTR_FAULT1_Pos         (4U)

+#define HRTIM_OUTR_FAULT1_Msk         (0x3UL << HRTIM_OUTR_FAULT1_Pos)         /*!< 0x00000030 */

+#define HRTIM_OUTR_FAULT1             HRTIM_OUTR_FAULT1_Msk                    /*!< Slave output 1 fault state */

+#define HRTIM_OUTR_FAULT1_0           (0x1UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000010 */

+#define HRTIM_OUTR_FAULT1_1           (0x2UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000020 */

+#define HRTIM_OUTR_CHP1_Pos           (6U)

+#define HRTIM_OUTR_CHP1_Msk           (0x1UL << HRTIM_OUTR_CHP1_Pos)           /*!< 0x00000040 */

+#define HRTIM_OUTR_CHP1               HRTIM_OUTR_CHP1_Msk                      /*!< Slave output 1 chopper enable */

+#define HRTIM_OUTR_DIDL1_Pos          (7U)

+#define HRTIM_OUTR_DIDL1_Msk          (0x1UL << HRTIM_OUTR_DIDL1_Pos)          /*!< 0x00000080 */

+#define HRTIM_OUTR_DIDL1              HRTIM_OUTR_DIDL1_Msk                     /*!< Slave output 1 dead time idle */

+

+#define HRTIM_OUTR_DTEN_Pos           (8U)

+#define HRTIM_OUTR_DTEN_Msk           (0x1UL << HRTIM_OUTR_DTEN_Pos)           /*!< 0x00000100 */

+#define HRTIM_OUTR_DTEN               HRTIM_OUTR_DTEN_Msk                      /*!< Slave output deadtime enable */

+#define HRTIM_OUTR_DLYPRTEN_Pos       (9U)

+#define HRTIM_OUTR_DLYPRTEN_Msk       (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos)       /*!< 0x00000200 */

+#define HRTIM_OUTR_DLYPRTEN           HRTIM_OUTR_DLYPRTEN_Msk                  /*!< Slave output delay protection enable */

+#define HRTIM_OUTR_DLYPRT_Pos         (10U)

+#define HRTIM_OUTR_DLYPRT_Msk         (0x7UL << HRTIM_OUTR_DLYPRT_Pos)         /*!< 0x00001C00 */

+#define HRTIM_OUTR_DLYPRT             HRTIM_OUTR_DLYPRT_Msk                    /*!< Slave output delay protection */

+#define HRTIM_OUTR_DLYPRT_0           (0x1UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000400 */

+#define HRTIM_OUTR_DLYPRT_1           (0x2UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000800 */

+#define HRTIM_OUTR_DLYPRT_2           (0x4UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00001000 */

+

+#define HRTIM_OUTR_POL2_Pos           (17U)

+#define HRTIM_OUTR_POL2_Msk           (0x1UL << HRTIM_OUTR_POL2_Pos)           /*!< 0x00020000 */

+#define HRTIM_OUTR_POL2               HRTIM_OUTR_POL2_Msk                      /*!< Slave output 2 polarity */

+#define HRTIM_OUTR_IDLM2_Pos          (18U)

+#define HRTIM_OUTR_IDLM2_Msk          (0x1UL << HRTIM_OUTR_IDLM2_Pos)          /*!< 0x00040000 */

+#define HRTIM_OUTR_IDLM2              HRTIM_OUTR_IDLM2_Msk                     /*!< Slave output 2 idle mode */

+#define HRTIM_OUTR_IDLES2_Pos         (19U)

+#define HRTIM_OUTR_IDLES2_Msk         (0x1UL << HRTIM_OUTR_IDLES2_Pos)         /*!< 0x00080000 */

+#define HRTIM_OUTR_IDLES2             HRTIM_OUTR_IDLES2_Msk                    /*!< Slave output 2 idle state */

+#define HRTIM_OUTR_FAULT2_Pos         (20U)

+#define HRTIM_OUTR_FAULT2_Msk         (0x3UL << HRTIM_OUTR_FAULT2_Pos)         /*!< 0x00300000 */

+#define HRTIM_OUTR_FAULT2             HRTIM_OUTR_FAULT2_Msk                    /*!< Slave output 2 fault state */

+#define HRTIM_OUTR_FAULT2_0           (0x1UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00100000 */

+#define HRTIM_OUTR_FAULT2_1           (0x2UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00200000 */

+#define HRTIM_OUTR_CHP2_Pos           (22U)

+#define HRTIM_OUTR_CHP2_Msk           (0x1UL << HRTIM_OUTR_CHP2_Pos)           /*!< 0x00400000 */

+#define HRTIM_OUTR_CHP2               HRTIM_OUTR_CHP2_Msk                      /*!< Slave output 2 chopper enable */

+#define HRTIM_OUTR_DIDL2_Pos          (23U)

+#define HRTIM_OUTR_DIDL2_Msk          (0x1UL << HRTIM_OUTR_DIDL2_Pos)          /*!< 0x00800000 */

+#define HRTIM_OUTR_DIDL2              HRTIM_OUTR_DIDL2_Msk                     /*!< Slave output 2 dead time idle */

+

+/**** Bit definition for Slave Timer Fault register ***************************/

+#define HRTIM_FLTR_FLT1EN_Pos         (0U)

+#define HRTIM_FLTR_FLT1EN_Msk         (0x1UL << HRTIM_FLTR_FLT1EN_Pos)         /*!< 0x00000001 */

+#define HRTIM_FLTR_FLT1EN             HRTIM_FLTR_FLT1EN_Msk                    /*!< Fault 1 enable */

+#define HRTIM_FLTR_FLT2EN_Pos         (1U)

+#define HRTIM_FLTR_FLT2EN_Msk         (0x1UL << HRTIM_FLTR_FLT2EN_Pos)         /*!< 0x00000002 */

+#define HRTIM_FLTR_FLT2EN             HRTIM_FLTR_FLT2EN_Msk                    /*!< Fault 2 enable */

+#define HRTIM_FLTR_FLT3EN_Pos         (2U)

+#define HRTIM_FLTR_FLT3EN_Msk         (0x1UL << HRTIM_FLTR_FLT3EN_Pos)         /*!< 0x00000004 */

+#define HRTIM_FLTR_FLT3EN             HRTIM_FLTR_FLT3EN_Msk                    /*!< Fault 3 enable */

+#define HRTIM_FLTR_FLT4EN_Pos         (3U)

+#define HRTIM_FLTR_FLT4EN_Msk         (0x1UL << HRTIM_FLTR_FLT4EN_Pos)         /*!< 0x00000008 */

+#define HRTIM_FLTR_FLT4EN             HRTIM_FLTR_FLT4EN_Msk                    /*!< Fault 4 enable */

+#define HRTIM_FLTR_FLT5EN_Pos         (4U)

+#define HRTIM_FLTR_FLT5EN_Msk         (0x1UL << HRTIM_FLTR_FLT5EN_Pos)         /*!< 0x00000010 */

+#define HRTIM_FLTR_FLT5EN             HRTIM_FLTR_FLT5EN_Msk                    /*!< Fault 5 enable */

+#define HRTIM_FLTR_FLTLCK_Pos         (31U)

+#define HRTIM_FLTR_FLTLCK_Msk         (0x1UL << HRTIM_FLTR_FLTLCK_Pos)         /*!< 0x80000000 */

+#define HRTIM_FLTR_FLTLCK             HRTIM_FLTR_FLTLCK_Msk                    /*!< Fault sources lock */

+

+/**** Bit definition for Common HRTIM Timer control register 1 ****************/

+#define HRTIM_CR1_MUDIS_Pos           (0U)

+#define HRTIM_CR1_MUDIS_Msk           (0x1UL << HRTIM_CR1_MUDIS_Pos)           /*!< 0x00000001 */

+#define HRTIM_CR1_MUDIS               HRTIM_CR1_MUDIS_Msk                      /*!< Master update disable*/

+#define HRTIM_CR1_TAUDIS_Pos          (1U)

+#define HRTIM_CR1_TAUDIS_Msk          (0x1UL << HRTIM_CR1_TAUDIS_Pos)          /*!< 0x00000002 */

+#define HRTIM_CR1_TAUDIS              HRTIM_CR1_TAUDIS_Msk                     /*!< Timer A update disable*/

+#define HRTIM_CR1_TBUDIS_Pos          (2U)

+#define HRTIM_CR1_TBUDIS_Msk          (0x1UL << HRTIM_CR1_TBUDIS_Pos)          /*!< 0x00000004 */

+#define HRTIM_CR1_TBUDIS              HRTIM_CR1_TBUDIS_Msk                     /*!< Timer B update disable*/

+#define HRTIM_CR1_TCUDIS_Pos          (3U)

+#define HRTIM_CR1_TCUDIS_Msk          (0x1UL << HRTIM_CR1_TCUDIS_Pos)          /*!< 0x00000008 */

+#define HRTIM_CR1_TCUDIS              HRTIM_CR1_TCUDIS_Msk                     /*!< Timer C update disable*/

+#define HRTIM_CR1_TDUDIS_Pos          (4U)

+#define HRTIM_CR1_TDUDIS_Msk          (0x1UL << HRTIM_CR1_TDUDIS_Pos)          /*!< 0x00000010 */

+#define HRTIM_CR1_TDUDIS              HRTIM_CR1_TDUDIS_Msk                     /*!< Timer D update disable*/

+#define HRTIM_CR1_TEUDIS_Pos          (5U)

+#define HRTIM_CR1_TEUDIS_Msk          (0x1UL << HRTIM_CR1_TEUDIS_Pos)          /*!< 0x00000020 */

+#define HRTIM_CR1_TEUDIS              HRTIM_CR1_TEUDIS_Msk                     /*!< Timer E update disable*/

+#define HRTIM_CR1_ADC1USRC_Pos        (16U)

+#define HRTIM_CR1_ADC1USRC_Msk        (0x7UL << HRTIM_CR1_ADC1USRC_Pos)        /*!< 0x00070000 */

+#define HRTIM_CR1_ADC1USRC            HRTIM_CR1_ADC1USRC_Msk                   /*!< ADC Trigger 1 update source */

+#define HRTIM_CR1_ADC1USRC_0          (0x1UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00010000 */

+#define HRTIM_CR1_ADC1USRC_1          (0x2UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00020000 */

+#define HRTIM_CR1_ADC1USRC_2          (0x4UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00040000 */

+#define HRTIM_CR1_ADC2USRC_Pos        (19U)

+#define HRTIM_CR1_ADC2USRC_Msk        (0x7UL << HRTIM_CR1_ADC2USRC_Pos)        /*!< 0x00380000 */

+#define HRTIM_CR1_ADC2USRC            HRTIM_CR1_ADC2USRC_Msk                   /*!< ADC Trigger 2 update source */

+#define HRTIM_CR1_ADC2USRC_0          (0x1UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00080000 */

+#define HRTIM_CR1_ADC2USRC_1          (0x2UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00100000 */

+#define HRTIM_CR1_ADC2USRC_2          (0x4UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00200000 */

+#define HRTIM_CR1_ADC3USRC_Pos        (22U)

+#define HRTIM_CR1_ADC3USRC_Msk        (0x7UL << HRTIM_CR1_ADC3USRC_Pos)        /*!< 0x01C00000 */

+#define HRTIM_CR1_ADC3USRC            HRTIM_CR1_ADC3USRC_Msk                   /*!< ADC Trigger 3 update source */

+#define HRTIM_CR1_ADC3USRC_0          (0x1UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00400000 */

+#define HRTIM_CR1_ADC3USRC_1          (0x2UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00800000 */

+#define HRTIM_CR1_ADC3USRC_2          (0x4UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x01000000 */

+#define HRTIM_CR1_ADC4USRC_Pos        (25U)

+#define HRTIM_CR1_ADC4USRC_Msk        (0x7UL << HRTIM_CR1_ADC4USRC_Pos)        /*!< 0x0E000000 */

+#define HRTIM_CR1_ADC4USRC            HRTIM_CR1_ADC4USRC_Msk                   /*!< ADC Trigger 4 update source */

+#define HRTIM_CR1_ADC4USRC_0          (0x1UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x02000000 */

+#define HRTIM_CR1_ADC4USRC_1          (0x2UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x04000000 */

+#define HRTIM_CR1_ADC4USRC_2          (0x0UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x0800000 */

+

+/**** Bit definition for Common HRTIM Timer control register 2 ****************/

+#define HRTIM_CR2_MSWU_Pos            (0U)

+#define HRTIM_CR2_MSWU_Msk            (0x1UL << HRTIM_CR2_MSWU_Pos)            /*!< 0x00000001 */

+#define HRTIM_CR2_MSWU                HRTIM_CR2_MSWU_Msk                       /*!< Master software update */

+#define HRTIM_CR2_TASWU_Pos           (1U)

+#define HRTIM_CR2_TASWU_Msk           (0x1UL << HRTIM_CR2_TASWU_Pos)           /*!< 0x00000002 */

+#define HRTIM_CR2_TASWU               HRTIM_CR2_TASWU_Msk                      /*!< Timer A software update */

+#define HRTIM_CR2_TBSWU_Pos           (2U)

+#define HRTIM_CR2_TBSWU_Msk           (0x1UL << HRTIM_CR2_TBSWU_Pos)           /*!< 0x00000004 */

+#define HRTIM_CR2_TBSWU               HRTIM_CR2_TBSWU_Msk                      /*!< Timer B software update */

+#define HRTIM_CR2_TCSWU_Pos           (3U)

+#define HRTIM_CR2_TCSWU_Msk           (0x1UL << HRTIM_CR2_TCSWU_Pos)           /*!< 0x00000008 */

+#define HRTIM_CR2_TCSWU               HRTIM_CR2_TCSWU_Msk                      /*!< Timer C software update */

+#define HRTIM_CR2_TDSWU_Pos           (4U)

+#define HRTIM_CR2_TDSWU_Msk           (0x1UL << HRTIM_CR2_TDSWU_Pos)           /*!< 0x00000010 */

+#define HRTIM_CR2_TDSWU               HRTIM_CR2_TDSWU_Msk                      /*!< Timer D software update */

+#define HRTIM_CR2_TESWU_Pos           (5U)

+#define HRTIM_CR2_TESWU_Msk           (0x1UL << HRTIM_CR2_TESWU_Pos)           /*!< 0x00000020 */

+#define HRTIM_CR2_TESWU               HRTIM_CR2_TESWU_Msk                      /*!< Timer E software update */

+#define HRTIM_CR2_MRST_Pos            (8U)

+#define HRTIM_CR2_MRST_Msk            (0x1UL << HRTIM_CR2_MRST_Pos)            /*!< 0x00000100 */

+#define HRTIM_CR2_MRST                HRTIM_CR2_MRST_Msk                       /*!< Master count software reset */

+#define HRTIM_CR2_TARST_Pos           (9U)

+#define HRTIM_CR2_TARST_Msk           (0x1UL << HRTIM_CR2_TARST_Pos)           /*!< 0x00000200 */

+#define HRTIM_CR2_TARST               HRTIM_CR2_TARST_Msk                      /*!< Timer A count software reset */

+#define HRTIM_CR2_TBRST_Pos           (10U)

+#define HRTIM_CR2_TBRST_Msk           (0x1UL << HRTIM_CR2_TBRST_Pos)           /*!< 0x00000400 */

+#define HRTIM_CR2_TBRST               HRTIM_CR2_TBRST_Msk                      /*!< Timer B count software reset */

+#define HRTIM_CR2_TCRST_Pos           (11U)

+#define HRTIM_CR2_TCRST_Msk           (0x1UL << HRTIM_CR2_TCRST_Pos)           /*!< 0x00000800 */

+#define HRTIM_CR2_TCRST               HRTIM_CR2_TCRST_Msk                      /*!< Timer C count software reset */

+#define HRTIM_CR2_TDRST_Pos           (12U)

+#define HRTIM_CR2_TDRST_Msk           (0x1UL << HRTIM_CR2_TDRST_Pos)           /*!< 0x00001000 */

+#define HRTIM_CR2_TDRST               HRTIM_CR2_TDRST_Msk                      /*!< Timer D count software reset */

+#define HRTIM_CR2_TERST_Pos           (13U)

+#define HRTIM_CR2_TERST_Msk           (0x1UL << HRTIM_CR2_TERST_Pos)           /*!< 0x00002000 */

+#define HRTIM_CR2_TERST               HRTIM_CR2_TERST_Msk                      /*!< Timer E count software reset */

+

+/**** Bit definition for Common HRTIM Timer interrupt status register *********/

+#define HRTIM_ISR_FLT1_Pos            (0U)

+#define HRTIM_ISR_FLT1_Msk            (0x1UL << HRTIM_ISR_FLT1_Pos)            /*!< 0x00000001 */

+#define HRTIM_ISR_FLT1                HRTIM_ISR_FLT1_Msk                       /*!< Fault 1 interrupt flag */

+#define HRTIM_ISR_FLT2_Pos            (1U)

+#define HRTIM_ISR_FLT2_Msk            (0x1UL << HRTIM_ISR_FLT2_Pos)            /*!< 0x00000002 */

+#define HRTIM_ISR_FLT2                HRTIM_ISR_FLT2_Msk                       /*!< Fault 2 interrupt flag */

+#define HRTIM_ISR_FLT3_Pos            (2U)

+#define HRTIM_ISR_FLT3_Msk            (0x1UL << HRTIM_ISR_FLT3_Pos)            /*!< 0x00000004 */

+#define HRTIM_ISR_FLT3                HRTIM_ISR_FLT3_Msk                       /*!< Fault 3 interrupt flag */

+#define HRTIM_ISR_FLT4_Pos            (3U)

+#define HRTIM_ISR_FLT4_Msk            (0x1UL << HRTIM_ISR_FLT4_Pos)            /*!< 0x00000008 */

+#define HRTIM_ISR_FLT4                HRTIM_ISR_FLT4_Msk                       /*!< Fault 4 interrupt flag */

+#define HRTIM_ISR_FLT5_Pos            (4U)

+#define HRTIM_ISR_FLT5_Msk            (0x1UL << HRTIM_ISR_FLT5_Pos)            /*!< 0x00000010 */

+#define HRTIM_ISR_FLT5                HRTIM_ISR_FLT5_Msk                       /*!< Fault 5 interrupt flag */

+#define HRTIM_ISR_SYSFLT_Pos          (5U)

+#define HRTIM_ISR_SYSFLT_Msk          (0x1UL << HRTIM_ISR_SYSFLT_Pos)          /*!< 0x00000020 */

+#define HRTIM_ISR_SYSFLT              HRTIM_ISR_SYSFLT_Msk                     /*!< System Fault interrupt flag */

+#define HRTIM_ISR_BMPER_Pos           (17U)

+#define HRTIM_ISR_BMPER_Msk           (0x1UL << HRTIM_ISR_BMPER_Pos)           /*!< 0x00020000 */

+#define HRTIM_ISR_BMPER               HRTIM_ISR_BMPER_Msk                      /*!<  Burst mode period interrupt flag */

+

+/**** Bit definition for Common HRTIM Timer interrupt clear register **********/

+#define HRTIM_ICR_FLT1C_Pos           (0U)

+#define HRTIM_ICR_FLT1C_Msk           (0x1UL << HRTIM_ICR_FLT1C_Pos)           /*!< 0x00000001 */

+#define HRTIM_ICR_FLT1C               HRTIM_ICR_FLT1C_Msk                      /*!< Fault 1 interrupt flag clear */

+#define HRTIM_ICR_FLT2C_Pos           (1U)

+#define HRTIM_ICR_FLT2C_Msk           (0x1UL << HRTIM_ICR_FLT2C_Pos)           /*!< 0x00000002 */

+#define HRTIM_ICR_FLT2C               HRTIM_ICR_FLT2C_Msk                      /*!< Fault 2 interrupt flag clear */

+#define HRTIM_ICR_FLT3C_Pos           (2U)

+#define HRTIM_ICR_FLT3C_Msk           (0x1UL << HRTIM_ICR_FLT3C_Pos)           /*!< 0x00000004 */

+#define HRTIM_ICR_FLT3C               HRTIM_ICR_FLT3C_Msk                      /*!< Fault 3 interrupt flag clear */

+#define HRTIM_ICR_FLT4C_Pos           (3U)

+#define HRTIM_ICR_FLT4C_Msk           (0x1UL << HRTIM_ICR_FLT4C_Pos)           /*!< 0x00000008 */

+#define HRTIM_ICR_FLT4C               HRTIM_ICR_FLT4C_Msk                      /*!< Fault 4 interrupt flag clear */

+#define HRTIM_ICR_FLT5C_Pos           (4U)

+#define HRTIM_ICR_FLT5C_Msk           (0x1UL << HRTIM_ICR_FLT5C_Pos)           /*!< 0x00000010 */

+#define HRTIM_ICR_FLT5C               HRTIM_ICR_FLT5C_Msk                      /*!< Fault 5 interrupt flag clear */

+#define HRTIM_ICR_SYSFLTC_Pos         (5U)

+#define HRTIM_ICR_SYSFLTC_Msk         (0x1UL << HRTIM_ICR_SYSFLTC_Pos)         /*!< 0x00000020 */

+#define HRTIM_ICR_SYSFLTC             HRTIM_ICR_SYSFLTC_Msk                    /*!< System Fault interrupt flag clear */

+#define HRTIM_ICR_BMPERC_Pos          (17U)

+#define HRTIM_ICR_BMPERC_Msk          (0x1UL << HRTIM_ICR_BMPERC_Pos)          /*!< 0x00020000 */

+#define HRTIM_ICR_BMPERC              HRTIM_ICR_BMPERC_Msk                     /*!<  Burst mode period interrupt flag clear */

+

+/**** Bit definition for Common HRTIM Timer interrupt enable register *********/

+#define HRTIM_IER_FLT1_Pos            (0U)

+#define HRTIM_IER_FLT1_Msk            (0x1UL << HRTIM_IER_FLT1_Pos)            /*!< 0x00000001 */

+#define HRTIM_IER_FLT1                HRTIM_IER_FLT1_Msk                       /*!< Fault 1 interrupt enable */

+#define HRTIM_IER_FLT2_Pos            (1U)

+#define HRTIM_IER_FLT2_Msk            (0x1UL << HRTIM_IER_FLT2_Pos)            /*!< 0x00000002 */

+#define HRTIM_IER_FLT2                HRTIM_IER_FLT2_Msk                       /*!< Fault 2 interrupt enable */

+#define HRTIM_IER_FLT3_Pos            (2U)

+#define HRTIM_IER_FLT3_Msk            (0x1UL << HRTIM_IER_FLT3_Pos)            /*!< 0x00000004 */

+#define HRTIM_IER_FLT3                HRTIM_IER_FLT3_Msk                       /*!< Fault 3 interrupt enable */

+#define HRTIM_IER_FLT4_Pos            (3U)

+#define HRTIM_IER_FLT4_Msk            (0x1UL << HRTIM_IER_FLT4_Pos)            /*!< 0x00000008 */

+#define HRTIM_IER_FLT4                HRTIM_IER_FLT4_Msk                       /*!< Fault 4 interrupt enable */

+#define HRTIM_IER_FLT5_Pos            (4U)

+#define HRTIM_IER_FLT5_Msk            (0x1UL << HRTIM_IER_FLT5_Pos)            /*!< 0x00000010 */

+#define HRTIM_IER_FLT5                HRTIM_IER_FLT5_Msk                       /*!< Fault 5 interrupt enable */

+#define HRTIM_IER_SYSFLT_Pos          (5U)

+#define HRTIM_IER_SYSFLT_Msk          (0x1UL << HRTIM_IER_SYSFLT_Pos)          /*!< 0x00000020 */

+#define HRTIM_IER_SYSFLT              HRTIM_IER_SYSFLT_Msk                     /*!< System Fault interrupt enable */

+#define HRTIM_IER_BMPER_Pos           (17U)

+#define HRTIM_IER_BMPER_Msk           (0x1UL << HRTIM_IER_BMPER_Pos)           /*!< 0x00020000 */

+#define HRTIM_IER_BMPER               HRTIM_IER_BMPER_Msk                      /*!<  Burst mode period interrupt enable */

+

+/**** Bit definition for Common HRTIM Timer output enable register ************/

+#define HRTIM_OENR_TA1OEN_Pos         (0U)

+#define HRTIM_OENR_TA1OEN_Msk         (0x1UL << HRTIM_OENR_TA1OEN_Pos)         /*!< 0x00000001 */

+#define HRTIM_OENR_TA1OEN             HRTIM_OENR_TA1OEN_Msk                    /*!< Timer A Output 1 enable */

+#define HRTIM_OENR_TA2OEN_Pos         (1U)

+#define HRTIM_OENR_TA2OEN_Msk         (0x1UL << HRTIM_OENR_TA2OEN_Pos)         /*!< 0x00000002 */

+#define HRTIM_OENR_TA2OEN             HRTIM_OENR_TA2OEN_Msk                    /*!< Timer A Output 2 enable */

+#define HRTIM_OENR_TB1OEN_Pos         (2U)

+#define HRTIM_OENR_TB1OEN_Msk         (0x1UL << HRTIM_OENR_TB1OEN_Pos)         /*!< 0x00000004 */

+#define HRTIM_OENR_TB1OEN             HRTIM_OENR_TB1OEN_Msk                    /*!< Timer B Output 1 enable */

+#define HRTIM_OENR_TB2OEN_Pos         (3U)

+#define HRTIM_OENR_TB2OEN_Msk         (0x1UL << HRTIM_OENR_TB2OEN_Pos)         /*!< 0x00000008 */

+#define HRTIM_OENR_TB2OEN             HRTIM_OENR_TB2OEN_Msk                    /*!< Timer B Output 2 enable */

+#define HRTIM_OENR_TC1OEN_Pos         (4U)

+#define HRTIM_OENR_TC1OEN_Msk         (0x1UL << HRTIM_OENR_TC1OEN_Pos)         /*!< 0x00000010 */

+#define HRTIM_OENR_TC1OEN             HRTIM_OENR_TC1OEN_Msk                    /*!< Timer C Output 1 enable */

+#define HRTIM_OENR_TC2OEN_Pos         (5U)

+#define HRTIM_OENR_TC2OEN_Msk         (0x1UL << HRTIM_OENR_TC2OEN_Pos)         /*!< 0x00000020 */

+#define HRTIM_OENR_TC2OEN             HRTIM_OENR_TC2OEN_Msk                    /*!< Timer C Output 2 enable */

+#define HRTIM_OENR_TD1OEN_Pos         (6U)

+#define HRTIM_OENR_TD1OEN_Msk         (0x1UL << HRTIM_OENR_TD1OEN_Pos)         /*!< 0x00000040 */

+#define HRTIM_OENR_TD1OEN             HRTIM_OENR_TD1OEN_Msk                    /*!< Timer D Output 1 enable */

+#define HRTIM_OENR_TD2OEN_Pos         (7U)

+#define HRTIM_OENR_TD2OEN_Msk         (0x1UL << HRTIM_OENR_TD2OEN_Pos)         /*!< 0x00000080 */

+#define HRTIM_OENR_TD2OEN             HRTIM_OENR_TD2OEN_Msk                    /*!< Timer D Output 2 enable */

+#define HRTIM_OENR_TE1OEN_Pos         (8U)

+#define HRTIM_OENR_TE1OEN_Msk         (0x1UL << HRTIM_OENR_TE1OEN_Pos)         /*!< 0x00000100 */

+#define HRTIM_OENR_TE1OEN             HRTIM_OENR_TE1OEN_Msk                    /*!< Timer E Output 1 enable */

+#define HRTIM_OENR_TE2OEN_Pos         (9U)

+#define HRTIM_OENR_TE2OEN_Msk         (0x1UL << HRTIM_OENR_TE2OEN_Pos)         /*!< 0x00000200 */

+#define HRTIM_OENR_TE2OEN             HRTIM_OENR_TE2OEN_Msk                    /*!< Timer E Output 2 enable */

+

+/**** Bit definition for Common HRTIM Timer output disable register ***********/

+#define HRTIM_ODISR_TA1ODIS_Pos       (0U)

+#define HRTIM_ODISR_TA1ODIS_Msk       (0x1UL << HRTIM_ODISR_TA1ODIS_Pos)       /*!< 0x00000001 */

+#define HRTIM_ODISR_TA1ODIS           HRTIM_ODISR_TA1ODIS_Msk                  /*!< Timer A Output 1 disable */

+#define HRTIM_ODISR_TA2ODIS_Pos       (1U)

+#define HRTIM_ODISR_TA2ODIS_Msk       (0x1UL << HRTIM_ODISR_TA2ODIS_Pos)       /*!< 0x00000002 */

+#define HRTIM_ODISR_TA2ODIS           HRTIM_ODISR_TA2ODIS_Msk                  /*!< Timer A Output 2 disable */

+#define HRTIM_ODISR_TB1ODIS_Pos       (2U)

+#define HRTIM_ODISR_TB1ODIS_Msk       (0x1UL << HRTIM_ODISR_TB1ODIS_Pos)       /*!< 0x00000004 */

+#define HRTIM_ODISR_TB1ODIS           HRTIM_ODISR_TB1ODIS_Msk                  /*!< Timer B Output 1 disable */

+#define HRTIM_ODISR_TB2ODIS_Pos       (3U)

+#define HRTIM_ODISR_TB2ODIS_Msk       (0x1UL << HRTIM_ODISR_TB2ODIS_Pos)       /*!< 0x00000008 */

+#define HRTIM_ODISR_TB2ODIS           HRTIM_ODISR_TB2ODIS_Msk                  /*!< Timer B Output 2 disable */

+#define HRTIM_ODISR_TC1ODIS_Pos       (4U)

+#define HRTIM_ODISR_TC1ODIS_Msk       (0x1UL << HRTIM_ODISR_TC1ODIS_Pos)       /*!< 0x00000010 */

+#define HRTIM_ODISR_TC1ODIS           HRTIM_ODISR_TC1ODIS_Msk                  /*!< Timer C Output 1 disable */

+#define HRTIM_ODISR_TC2ODIS_Pos       (5U)

+#define HRTIM_ODISR_TC2ODIS_Msk       (0x1UL << HRTIM_ODISR_TC2ODIS_Pos)       /*!< 0x00000020 */

+#define HRTIM_ODISR_TC2ODIS           HRTIM_ODISR_TC2ODIS_Msk                  /*!< Timer C Output 2 disable */

+#define HRTIM_ODISR_TD1ODIS_Pos       (6U)

+#define HRTIM_ODISR_TD1ODIS_Msk       (0x1UL << HRTIM_ODISR_TD1ODIS_Pos)       /*!< 0x00000040 */

+#define HRTIM_ODISR_TD1ODIS           HRTIM_ODISR_TD1ODIS_Msk                  /*!< Timer D Output 1 disable */

+#define HRTIM_ODISR_TD2ODIS_Pos       (7U)

+#define HRTIM_ODISR_TD2ODIS_Msk       (0x1UL << HRTIM_ODISR_TD2ODIS_Pos)       /*!< 0x00000080 */

+#define HRTIM_ODISR_TD2ODIS           HRTIM_ODISR_TD2ODIS_Msk                  /*!< Timer D Output 2 disable */

+#define HRTIM_ODISR_TE1ODIS_Pos       (8U)

+#define HRTIM_ODISR_TE1ODIS_Msk       (0x1UL << HRTIM_ODISR_TE1ODIS_Pos)       /*!< 0x00000100 */

+#define HRTIM_ODISR_TE1ODIS           HRTIM_ODISR_TE1ODIS_Msk                  /*!< Timer E Output 1 disable */

+#define HRTIM_ODISR_TE2ODIS_Pos       (9U)

+#define HRTIM_ODISR_TE2ODIS_Msk       (0x1UL << HRTIM_ODISR_TE2ODIS_Pos)       /*!< 0x00000200 */

+#define HRTIM_ODISR_TE2ODIS           HRTIM_ODISR_TE2ODIS_Msk                  /*!< Timer E Output 2 disable */

+

+/**** Bit definition for Common HRTIM Timer output disable status register *****/

+#define HRTIM_ODSR_TA1ODS_Pos         (0U)

+#define HRTIM_ODSR_TA1ODS_Msk         (0x1UL << HRTIM_ODSR_TA1ODS_Pos)         /*!< 0x00000001 */

+#define HRTIM_ODSR_TA1ODS             HRTIM_ODSR_TA1ODS_Msk                    /*!< Timer A Output 1 disable status */

+#define HRTIM_ODSR_TA2ODS_Pos         (1U)

+#define HRTIM_ODSR_TA2ODS_Msk         (0x1UL << HRTIM_ODSR_TA2ODS_Pos)         /*!< 0x00000002 */

+#define HRTIM_ODSR_TA2ODS             HRTIM_ODSR_TA2ODS_Msk                    /*!< Timer A Output 2 disable status */

+#define HRTIM_ODSR_TB1ODS_Pos         (2U)

+#define HRTIM_ODSR_TB1ODS_Msk         (0x1UL << HRTIM_ODSR_TB1ODS_Pos)         /*!< 0x00000004 */

+#define HRTIM_ODSR_TB1ODS             HRTIM_ODSR_TB1ODS_Msk                    /*!< Timer B Output 1 disable status */

+#define HRTIM_ODSR_TB2ODS_Pos         (3U)

+#define HRTIM_ODSR_TB2ODS_Msk         (0x1UL << HRTIM_ODSR_TB2ODS_Pos)         /*!< 0x00000008 */

+#define HRTIM_ODSR_TB2ODS             HRTIM_ODSR_TB2ODS_Msk                    /*!< Timer B Output 2 disable status */

+#define HRTIM_ODSR_TC1ODS_Pos         (4U)

+#define HRTIM_ODSR_TC1ODS_Msk         (0x1UL << HRTIM_ODSR_TC1ODS_Pos)         /*!< 0x00000010 */

+#define HRTIM_ODSR_TC1ODS             HRTIM_ODSR_TC1ODS_Msk                    /*!< Timer C Output 1 disable status */

+#define HRTIM_ODSR_TC2ODS_Pos         (5U)

+#define HRTIM_ODSR_TC2ODS_Msk         (0x1UL << HRTIM_ODSR_TC2ODS_Pos)         /*!< 0x00000020 */

+#define HRTIM_ODSR_TC2ODS             HRTIM_ODSR_TC2ODS_Msk                    /*!< Timer C Output 2 disable status */

+#define HRTIM_ODSR_TD1ODS_Pos         (6U)

+#define HRTIM_ODSR_TD1ODS_Msk         (0x1UL << HRTIM_ODSR_TD1ODS_Pos)         /*!< 0x00000040 */

+#define HRTIM_ODSR_TD1ODS             HRTIM_ODSR_TD1ODS_Msk                    /*!< Timer D Output 1 disable status */

+#define HRTIM_ODSR_TD2ODS_Pos         (7U)

+#define HRTIM_ODSR_TD2ODS_Msk         (0x1UL << HRTIM_ODSR_TD2ODS_Pos)         /*!< 0x00000080 */

+#define HRTIM_ODSR_TD2ODS             HRTIM_ODSR_TD2ODS_Msk                    /*!< Timer D Output 2 disable status */

+#define HRTIM_ODSR_TE1ODS_Pos         (8U)

+#define HRTIM_ODSR_TE1ODS_Msk         (0x1UL << HRTIM_ODSR_TE1ODS_Pos)         /*!< 0x00000100 */

+#define HRTIM_ODSR_TE1ODS             HRTIM_ODSR_TE1ODS_Msk                    /*!< Timer E Output 1 disable status */

+#define HRTIM_ODSR_TE2ODS_Pos         (9U)

+#define HRTIM_ODSR_TE2ODS_Msk         (0x1UL << HRTIM_ODSR_TE2ODS_Pos)         /*!< 0x00000200 */

+#define HRTIM_ODSR_TE2ODS             HRTIM_ODSR_TE2ODS_Msk                    /*!< Timer E Output 2 disable status */

+

+/**** Bit definition for Common HRTIM Timer Burst mode control register ********/

+#define HRTIM_BMCR_BME_Pos            (0U)

+#define HRTIM_BMCR_BME_Msk            (0x1UL << HRTIM_BMCR_BME_Pos)            /*!< 0x00000001 */

+#define HRTIM_BMCR_BME                HRTIM_BMCR_BME_Msk                       /*!< Burst mode enbale */

+#define HRTIM_BMCR_BMOM_Pos           (1U)

+#define HRTIM_BMCR_BMOM_Msk           (0x1UL << HRTIM_BMCR_BMOM_Pos)           /*!< 0x00000002 */

+#define HRTIM_BMCR_BMOM               HRTIM_BMCR_BMOM_Msk                      /*!< Burst mode operating mode */

+#define HRTIM_BMCR_BMCLK_Pos          (2U)

+#define HRTIM_BMCR_BMCLK_Msk          (0xFUL << HRTIM_BMCR_BMCLK_Pos)          /*!< 0x0000003C */

+#define HRTIM_BMCR_BMCLK              HRTIM_BMCR_BMCLK_Msk                     /*!< Burst mode clock source */

+#define HRTIM_BMCR_BMCLK_0            (0x1UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000004 */

+#define HRTIM_BMCR_BMCLK_1            (0x2UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000008 */

+#define HRTIM_BMCR_BMCLK_2            (0x4UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000010 */

+#define HRTIM_BMCR_BMCLK_3            (0x8UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000020 */

+#define HRTIM_BMCR_BMPRSC_Pos         (6U)

+#define HRTIM_BMCR_BMPRSC_Msk         (0xFUL << HRTIM_BMCR_BMPRSC_Pos)         /*!< 0x000003C0 */

+#define HRTIM_BMCR_BMPRSC             HRTIM_BMCR_BMPRSC_Msk                    /*!< Burst mode prescaler */

+#define HRTIM_BMCR_BMPRSC_0           (0x1UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000040 */

+#define HRTIM_BMCR_BMPRSC_1           (0x2UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000080 */

+#define HRTIM_BMCR_BMPRSC_2           (0x4UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000100 */

+#define HRTIM_BMCR_BMPRSC_3           (0x8UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000200 */

+#define HRTIM_BMCR_BMPREN_Pos         (10U)

+#define HRTIM_BMCR_BMPREN_Msk         (0x1UL << HRTIM_BMCR_BMPREN_Pos)         /*!< 0x00000400 */

+#define HRTIM_BMCR_BMPREN             HRTIM_BMCR_BMPREN_Msk                    /*!< Burst mode Preload bit */

+#define HRTIM_BMCR_MTBM_Pos           (16U)

+#define HRTIM_BMCR_MTBM_Msk           (0x1UL << HRTIM_BMCR_MTBM_Pos)           /*!< 0x00010000 */

+#define HRTIM_BMCR_MTBM               HRTIM_BMCR_MTBM_Msk                      /*!< Master Timer Burst mode */

+#define HRTIM_BMCR_TABM_Pos           (17U)

+#define HRTIM_BMCR_TABM_Msk           (0x1UL << HRTIM_BMCR_TABM_Pos)           /*!< 0x00020000 */

+#define HRTIM_BMCR_TABM               HRTIM_BMCR_TABM_Msk                      /*!< Timer A Burst mode */

+#define HRTIM_BMCR_TBBM_Pos           (18U)

+#define HRTIM_BMCR_TBBM_Msk           (0x1UL << HRTIM_BMCR_TBBM_Pos)           /*!< 0x00040000 */

+#define HRTIM_BMCR_TBBM               HRTIM_BMCR_TBBM_Msk                      /*!< Timer B Burst mode */

+#define HRTIM_BMCR_TCBM_Pos           (19U)

+#define HRTIM_BMCR_TCBM_Msk           (0x1UL << HRTIM_BMCR_TCBM_Pos)           /*!< 0x00080000 */

+#define HRTIM_BMCR_TCBM               HRTIM_BMCR_TCBM_Msk                      /*!< Timer C Burst mode */

+#define HRTIM_BMCR_TDBM_Pos           (20U)

+#define HRTIM_BMCR_TDBM_Msk           (0x1UL << HRTIM_BMCR_TDBM_Pos)           /*!< 0x00100000 */

+#define HRTIM_BMCR_TDBM               HRTIM_BMCR_TDBM_Msk                      /*!< Timer D Burst mode */

+#define HRTIM_BMCR_TEBM_Pos           (21U)

+#define HRTIM_BMCR_TEBM_Msk           (0x1UL << HRTIM_BMCR_TEBM_Pos)           /*!< 0x00200000 */

+#define HRTIM_BMCR_TEBM               HRTIM_BMCR_TEBM_Msk                      /*!< Timer E Burst mode */

+#define HRTIM_BMCR_BMSTAT_Pos         (31U)

+#define HRTIM_BMCR_BMSTAT_Msk         (0x1UL << HRTIM_BMCR_BMSTAT_Pos)         /*!< 0x80000000 */

+#define HRTIM_BMCR_BMSTAT             HRTIM_BMCR_BMSTAT_Msk                    /*!< Burst mode status */

+

+/**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/

+#define HRTIM_BMTRGR_SW_Pos           (0U)

+#define HRTIM_BMTRGR_SW_Msk           (0x1UL << HRTIM_BMTRGR_SW_Pos)           /*!< 0x00000001 */

+#define HRTIM_BMTRGR_SW               HRTIM_BMTRGR_SW_Msk                      /*!< Software start */

+#define HRTIM_BMTRGR_MSTRST_Pos       (1U)

+#define HRTIM_BMTRGR_MSTRST_Msk       (0x1UL << HRTIM_BMTRGR_MSTRST_Pos)       /*!< 0x00000002 */

+#define HRTIM_BMTRGR_MSTRST           HRTIM_BMTRGR_MSTRST_Msk                  /*!<  Master reset */

+#define HRTIM_BMTRGR_MSTREP_Pos       (2U)

+#define HRTIM_BMTRGR_MSTREP_Msk       (0x1UL << HRTIM_BMTRGR_MSTREP_Pos)       /*!< 0x00000004 */

+#define HRTIM_BMTRGR_MSTREP           HRTIM_BMTRGR_MSTREP_Msk                  /*!<  Master repetition */

+#define HRTIM_BMTRGR_MSTCMP1_Pos      (3U)

+#define HRTIM_BMTRGR_MSTCMP1_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos)      /*!< 0x00000008 */

+#define HRTIM_BMTRGR_MSTCMP1          HRTIM_BMTRGR_MSTCMP1_Msk                 /*!<  Master compare 1 */

+#define HRTIM_BMTRGR_MSTCMP2_Pos      (4U)

+#define HRTIM_BMTRGR_MSTCMP2_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos)      /*!< 0x00000010 */

+#define HRTIM_BMTRGR_MSTCMP2          HRTIM_BMTRGR_MSTCMP2_Msk                 /*!< Master compare 2  */

+#define HRTIM_BMTRGR_MSTCMP3_Pos      (5U)

+#define HRTIM_BMTRGR_MSTCMP3_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos)      /*!< 0x00000020 */

+#define HRTIM_BMTRGR_MSTCMP3          HRTIM_BMTRGR_MSTCMP3_Msk                 /*!< Master compare 3 */

+#define HRTIM_BMTRGR_MSTCMP4_Pos      (6U)

+#define HRTIM_BMTRGR_MSTCMP4_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos)      /*!< 0x00000040 */

+#define HRTIM_BMTRGR_MSTCMP4          HRTIM_BMTRGR_MSTCMP4_Msk                 /*!< Master compare 4 */

+#define HRTIM_BMTRGR_TARST_Pos        (7U)

+#define HRTIM_BMTRGR_TARST_Msk        (0x1UL << HRTIM_BMTRGR_TARST_Pos)        /*!< 0x00000080 */

+#define HRTIM_BMTRGR_TARST            HRTIM_BMTRGR_TARST_Msk                   /*!< Timer A reset  */

+#define HRTIM_BMTRGR_TAREP_Pos        (8U)

+#define HRTIM_BMTRGR_TAREP_Msk        (0x1UL << HRTIM_BMTRGR_TAREP_Pos)        /*!< 0x00000100 */

+#define HRTIM_BMTRGR_TAREP            HRTIM_BMTRGR_TAREP_Msk                   /*!< Timer A repetition  */

+#define HRTIM_BMTRGR_TACMP1_Pos       (9U)

+#define HRTIM_BMTRGR_TACMP1_Msk       (0x1UL << HRTIM_BMTRGR_TACMP1_Pos)       /*!< 0x00000200 */

+#define HRTIM_BMTRGR_TACMP1           HRTIM_BMTRGR_TACMP1_Msk                  /*!< Timer A compare 1  */

+#define HRTIM_BMTRGR_TACMP2_Pos       (10U)

+#define HRTIM_BMTRGR_TACMP2_Msk       (0x1UL << HRTIM_BMTRGR_TACMP2_Pos)       /*!< 0x00000400 */

+#define HRTIM_BMTRGR_TACMP2           HRTIM_BMTRGR_TACMP2_Msk                  /*!< Timer A compare 2  */

+#define HRTIM_BMTRGR_TBRST_Pos        (11U)

+#define HRTIM_BMTRGR_TBRST_Msk        (0x1UL << HRTIM_BMTRGR_TBRST_Pos)        /*!< 0x00000800 */

+#define HRTIM_BMTRGR_TBRST            HRTIM_BMTRGR_TBRST_Msk                   /*!< Timer B reset  */

+#define HRTIM_BMTRGR_TBREP_Pos        (12U)

+#define HRTIM_BMTRGR_TBREP_Msk        (0x1UL << HRTIM_BMTRGR_TBREP_Pos)        /*!< 0x00001000 */

+#define HRTIM_BMTRGR_TBREP            HRTIM_BMTRGR_TBREP_Msk                   /*!< Timer B repetition  */

+#define HRTIM_BMTRGR_TBCMP1_Pos       (13U)

+#define HRTIM_BMTRGR_TBCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos)       /*!< 0x00002000 */

+#define HRTIM_BMTRGR_TBCMP1           HRTIM_BMTRGR_TBCMP1_Msk                  /*!< Timer B compare 1 */

+#define HRTIM_BMTRGR_TBCMP2_Pos       (14U)

+#define HRTIM_BMTRGR_TBCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos)       /*!< 0x00004000 */

+#define HRTIM_BMTRGR_TBCMP2           HRTIM_BMTRGR_TBCMP2_Msk                  /*!< Timer B compare 2 */

+#define HRTIM_BMTRGR_TCRST_Pos        (15U)

+#define HRTIM_BMTRGR_TCRST_Msk        (0x1UL << HRTIM_BMTRGR_TCRST_Pos)        /*!< 0x00008000 */

+#define HRTIM_BMTRGR_TCRST            HRTIM_BMTRGR_TCRST_Msk                   /*!< Timer C reset  */

+#define HRTIM_BMTRGR_TCREP_Pos        (16U)

+#define HRTIM_BMTRGR_TCREP_Msk        (0x1UL << HRTIM_BMTRGR_TCREP_Pos)        /*!< 0x00010000 */

+#define HRTIM_BMTRGR_TCREP            HRTIM_BMTRGR_TCREP_Msk                   /*!< Timer C repetition */

+#define HRTIM_BMTRGR_TCCMP1_Pos       (17U)

+#define HRTIM_BMTRGR_TCCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos)       /*!< 0x00020000 */

+#define HRTIM_BMTRGR_TCCMP1           HRTIM_BMTRGR_TCCMP1_Msk                  /*!< Timer C compare 1 */

+#define HRTIM_BMTRGR_TCCMP2_Pos       (18U)

+#define HRTIM_BMTRGR_TCCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP2_Pos)       /*!< 0x00040000 */

+#define HRTIM_BMTRGR_TCCMP2           HRTIM_BMTRGR_TCCMP2_Msk                  /*!< Timer C compare 2 */

+#define HRTIM_BMTRGR_TDRST_Pos        (19U)

+#define HRTIM_BMTRGR_TDRST_Msk        (0x1UL << HRTIM_BMTRGR_TDRST_Pos)        /*!< 0x00080000 */

+#define HRTIM_BMTRGR_TDRST            HRTIM_BMTRGR_TDRST_Msk                   /*!< Timer D reset  */

+#define HRTIM_BMTRGR_TDREP_Pos        (20U)

+#define HRTIM_BMTRGR_TDREP_Msk        (0x1UL << HRTIM_BMTRGR_TDREP_Pos)        /*!< 0x00100000 */

+#define HRTIM_BMTRGR_TDREP            HRTIM_BMTRGR_TDREP_Msk                   /*!< Timer D repetition  */

+#define HRTIM_BMTRGR_TDCMP1_Pos       (21U)

+#define HRTIM_BMTRGR_TDCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP1_Pos)       /*!< 0x00200000 */

+#define HRTIM_BMTRGR_TDCMP1           HRTIM_BMTRGR_TDCMP1_Msk                  /*!< Timer D compare 1 */

+#define HRTIM_BMTRGR_TDCMP2_Pos       (22U)

+#define HRTIM_BMTRGR_TDCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos)       /*!< 0x00400000 */

+#define HRTIM_BMTRGR_TDCMP2           HRTIM_BMTRGR_TDCMP2_Msk                  /*!< Timer D compare 2 */

+#define HRTIM_BMTRGR_TERST_Pos        (23U)

+#define HRTIM_BMTRGR_TERST_Msk        (0x1UL << HRTIM_BMTRGR_TERST_Pos)        /*!< 0x00800000 */

+#define HRTIM_BMTRGR_TERST            HRTIM_BMTRGR_TERST_Msk                   /*!< Timer E reset  */

+#define HRTIM_BMTRGR_TEREP_Pos        (24U)

+#define HRTIM_BMTRGR_TEREP_Msk        (0x1UL << HRTIM_BMTRGR_TEREP_Pos)        /*!< 0x01000000 */

+#define HRTIM_BMTRGR_TEREP            HRTIM_BMTRGR_TEREP_Msk                   /*!< Timer E repetition  */

+#define HRTIM_BMTRGR_TECMP1_Pos       (25U)

+#define HRTIM_BMTRGR_TECMP1_Msk       (0x1UL << HRTIM_BMTRGR_TECMP1_Pos)       /*!< 0x02000000 */

+#define HRTIM_BMTRGR_TECMP1           HRTIM_BMTRGR_TECMP1_Msk                  /*!< Timer E compare 1 */

+#define HRTIM_BMTRGR_TECMP2_Pos       (26U)

+#define HRTIM_BMTRGR_TECMP2_Msk       (0x1UL << HRTIM_BMTRGR_TECMP2_Pos)       /*!< 0x04000000 */

+#define HRTIM_BMTRGR_TECMP2           HRTIM_BMTRGR_TECMP2_Msk                  /*!< Timer E compare 2 */

+#define HRTIM_BMTRGR_TAEEV7_Pos       (27U)

+#define HRTIM_BMTRGR_TAEEV7_Msk       (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos)       /*!< 0x08000000 */

+#define HRTIM_BMTRGR_TAEEV7           HRTIM_BMTRGR_TAEEV7_Msk                  /*!< Timer A period following External Event7  */

+#define HRTIM_BMTRGR_TDEEV8_Pos       (28U)

+#define HRTIM_BMTRGR_TDEEV8_Msk       (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos)       /*!< 0x10000000 */

+#define HRTIM_BMTRGR_TDEEV8           HRTIM_BMTRGR_TDEEV8_Msk                  /*!< Timer D period following External Event8  */

+#define HRTIM_BMTRGR_EEV7_Pos         (29U)

+#define HRTIM_BMTRGR_EEV7_Msk         (0x1UL << HRTIM_BMTRGR_EEV7_Pos)         /*!< 0x20000000 */

+#define HRTIM_BMTRGR_EEV7             HRTIM_BMTRGR_EEV7_Msk                    /*!< External Event 7 */

+#define HRTIM_BMTRGR_EEV8_Pos         (30U)

+#define HRTIM_BMTRGR_EEV8_Msk         (0x1UL << HRTIM_BMTRGR_EEV8_Pos)         /*!< 0x40000000 */

+#define HRTIM_BMTRGR_EEV8             HRTIM_BMTRGR_EEV8_Msk                    /*!< External Event 8 */

+#define HRTIM_BMTRGR_OCHPEV_Pos       (31U)

+#define HRTIM_BMTRGR_OCHPEV_Msk       (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos)       /*!< 0x80000000 */

+#define HRTIM_BMTRGR_OCHPEV           HRTIM_BMTRGR_OCHPEV_Msk                  /*!< on-chip Event */

+

+/*******************  Bit definition for HRTIM_BMCMPR register  ***************/

+#define HRTIM_BMCMPR_BMCMPR_Pos       (0U)

+#define HRTIM_BMCMPR_BMCMPR_Msk       (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_BMCMPR_BMCMPR           HRTIM_BMCMPR_BMCMPR_Msk                  /*!<!<Burst Compare Value */

+

+/*******************  Bit definition for HRTIM_BMPER register  ****************/

+#define HRTIM_BMPER_BMPER_Pos         (0U)

+#define HRTIM_BMPER_BMPER_Msk         (0xFFFFUL << HRTIM_BMPER_BMPER_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_BMPER_BMPER             HRTIM_BMPER_BMPER_Msk                    /*!<!<Burst period Value */

+

+/*******************  Bit definition for HRTIM_EECR1 register  ****************/

+#define HRTIM_EECR1_EE1SRC_Pos        (0U)

+#define HRTIM_EECR1_EE1SRC_Msk        (0x3UL << HRTIM_EECR1_EE1SRC_Pos)        /*!< 0x00000003 */

+#define HRTIM_EECR1_EE1SRC            HRTIM_EECR1_EE1SRC_Msk                   /*!< External event 1 source */

+#define HRTIM_EECR1_EE1SRC_0          (0x1UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000001 */

+#define HRTIM_EECR1_EE1SRC_1          (0x2UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000002 */

+#define HRTIM_EECR1_EE1POL_Pos        (2U)

+#define HRTIM_EECR1_EE1POL_Msk        (0x1UL << HRTIM_EECR1_EE1POL_Pos)        /*!< 0x00000004 */

+#define HRTIM_EECR1_EE1POL            HRTIM_EECR1_EE1POL_Msk                   /*!< External event 1 Polarity */

+#define HRTIM_EECR1_EE1SNS_Pos        (3U)

+#define HRTIM_EECR1_EE1SNS_Msk        (0x3UL << HRTIM_EECR1_EE1SNS_Pos)        /*!< 0x00000018 */

+#define HRTIM_EECR1_EE1SNS            HRTIM_EECR1_EE1SNS_Msk                   /*!< External event 1 sensitivity */

+#define HRTIM_EECR1_EE1SNS_0          (0x1UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000008 */

+#define HRTIM_EECR1_EE1SNS_1          (0x2UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000010 */

+#define HRTIM_EECR1_EE1FAST_Pos       (5U)

+#define HRTIM_EECR1_EE1FAST_Msk       (0x1UL << HRTIM_EECR1_EE1FAST_Pos)       /*!< 0x00000020 */

+#define HRTIM_EECR1_EE1FAST           HRTIM_EECR1_EE1FAST_Msk                  /*!< External event 1 Fast mode */

+

+#define HRTIM_EECR1_EE2SRC_Pos        (6U)

+#define HRTIM_EECR1_EE2SRC_Msk        (0x3UL << HRTIM_EECR1_EE2SRC_Pos)        /*!< 0x000000C0 */

+#define HRTIM_EECR1_EE2SRC            HRTIM_EECR1_EE2SRC_Msk                   /*!< External event 2 source */

+#define HRTIM_EECR1_EE2SRC_0          (0x1UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000040 */

+#define HRTIM_EECR1_EE2SRC_1          (0x2UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000080 */

+#define HRTIM_EECR1_EE2POL_Pos        (8U)

+#define HRTIM_EECR1_EE2POL_Msk        (0x1UL << HRTIM_EECR1_EE2POL_Pos)        /*!< 0x00000100 */

+#define HRTIM_EECR1_EE2POL            HRTIM_EECR1_EE2POL_Msk                   /*!< External event 2 Polarity */

+#define HRTIM_EECR1_EE2SNS_Pos        (9U)

+#define HRTIM_EECR1_EE2SNS_Msk        (0x3UL << HRTIM_EECR1_EE2SNS_Pos)        /*!< 0x00000600 */

+#define HRTIM_EECR1_EE2SNS            HRTIM_EECR1_EE2SNS_Msk                   /*!< External event 2 sensitivity */

+#define HRTIM_EECR1_EE2SNS_0          (0x1UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000200 */

+#define HRTIM_EECR1_EE2SNS_1          (0x2UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000400 */

+#define HRTIM_EECR1_EE2FAST_Pos       (11U)

+#define HRTIM_EECR1_EE2FAST_Msk       (0x1UL << HRTIM_EECR1_EE2FAST_Pos)       /*!< 0x00000800 */

+#define HRTIM_EECR1_EE2FAST           HRTIM_EECR1_EE2FAST_Msk                  /*!< External event 2 Fast mode */

+

+#define HRTIM_EECR1_EE3SRC_Pos        (12U)

+#define HRTIM_EECR1_EE3SRC_Msk        (0x3UL << HRTIM_EECR1_EE3SRC_Pos)        /*!< 0x00003000 */

+#define HRTIM_EECR1_EE3SRC            HRTIM_EECR1_EE3SRC_Msk                   /*!< External event 3 source */

+#define HRTIM_EECR1_EE3SRC_0          (0x1UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00001000 */

+#define HRTIM_EECR1_EE3SRC_1          (0x2UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00002000 */

+#define HRTIM_EECR1_EE3POL_Pos        (14U)

+#define HRTIM_EECR1_EE3POL_Msk        (0x1UL << HRTIM_EECR1_EE3POL_Pos)        /*!< 0x00004000 */

+#define HRTIM_EECR1_EE3POL            HRTIM_EECR1_EE3POL_Msk                   /*!< External event 3 Polarity */

+#define HRTIM_EECR1_EE3SNS_Pos        (15U)

+#define HRTIM_EECR1_EE3SNS_Msk        (0x3UL << HRTIM_EECR1_EE3SNS_Pos)        /*!< 0x00018000 */

+#define HRTIM_EECR1_EE3SNS            HRTIM_EECR1_EE3SNS_Msk                   /*!< External event 3 sensitivity */

+#define HRTIM_EECR1_EE3SNS_0          (0x1UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00008000 */

+#define HRTIM_EECR1_EE3SNS_1          (0x2UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00010000 */

+#define HRTIM_EECR1_EE3FAST_Pos       (17U)

+#define HRTIM_EECR1_EE3FAST_Msk       (0x1UL << HRTIM_EECR1_EE3FAST_Pos)       /*!< 0x00020000 */

+#define HRTIM_EECR1_EE3FAST           HRTIM_EECR1_EE3FAST_Msk                  /*!< External event 3 Fast mode */

+

+#define HRTIM_EECR1_EE4SRC_Pos        (18U)

+#define HRTIM_EECR1_EE4SRC_Msk        (0x3UL << HRTIM_EECR1_EE4SRC_Pos)        /*!< 0x000C0000 */

+#define HRTIM_EECR1_EE4SRC            HRTIM_EECR1_EE4SRC_Msk                   /*!< External event 4 source */

+#define HRTIM_EECR1_EE4SRC_0          (0x1UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00040000 */

+#define HRTIM_EECR1_EE4SRC_1          (0x2UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00080000 */

+#define HRTIM_EECR1_EE4POL_Pos        (20U)

+#define HRTIM_EECR1_EE4POL_Msk        (0x1UL << HRTIM_EECR1_EE4POL_Pos)        /*!< 0x00100000 */

+#define HRTIM_EECR1_EE4POL            HRTIM_EECR1_EE4POL_Msk                   /*!< External event 4 Polarity */

+#define HRTIM_EECR1_EE4SNS_Pos        (21U)

+#define HRTIM_EECR1_EE4SNS_Msk        (0x3UL << HRTIM_EECR1_EE4SNS_Pos)        /*!< 0x00600000 */

+#define HRTIM_EECR1_EE4SNS            HRTIM_EECR1_EE4SNS_Msk                   /*!< External event 4 sensitivity */

+#define HRTIM_EECR1_EE4SNS_0          (0x1UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00200000 */

+#define HRTIM_EECR1_EE4SNS_1          (0x2UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00400000 */

+#define HRTIM_EECR1_EE4FAST_Pos       (23U)

+#define HRTIM_EECR1_EE4FAST_Msk       (0x1UL << HRTIM_EECR1_EE4FAST_Pos)       /*!< 0x00800000 */

+#define HRTIM_EECR1_EE4FAST           HRTIM_EECR1_EE4FAST_Msk                  /*!< External event 4 Fast mode */

+

+#define HRTIM_EECR1_EE5SRC_Pos        (24U)

+#define HRTIM_EECR1_EE5SRC_Msk        (0x3UL << HRTIM_EECR1_EE5SRC_Pos)        /*!< 0x03000000 */

+#define HRTIM_EECR1_EE5SRC            HRTIM_EECR1_EE5SRC_Msk                   /*!< External event 5 source */

+#define HRTIM_EECR1_EE5SRC_0          (0x1UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x01000000 */

+#define HRTIM_EECR1_EE5SRC_1          (0x2UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x02000000 */

+#define HRTIM_EECR1_EE5POL_Pos        (26U)

+#define HRTIM_EECR1_EE5POL_Msk        (0x1UL << HRTIM_EECR1_EE5POL_Pos)        /*!< 0x04000000 */

+#define HRTIM_EECR1_EE5POL            HRTIM_EECR1_EE5POL_Msk                   /*!< External event 5 Polarity */

+#define HRTIM_EECR1_EE5SNS_Pos        (27U)

+#define HRTIM_EECR1_EE5SNS_Msk        (0x3UL << HRTIM_EECR1_EE5SNS_Pos)        /*!< 0x18000000 */

+#define HRTIM_EECR1_EE5SNS            HRTIM_EECR1_EE5SNS_Msk                   /*!< External event 5 sensitivity */

+#define HRTIM_EECR1_EE5SNS_0          (0x1UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x08000000 */

+#define HRTIM_EECR1_EE5SNS_1          (0x2UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x10000000 */

+#define HRTIM_EECR1_EE5FAST_Pos       (29U)

+#define HRTIM_EECR1_EE5FAST_Msk       (0x1UL << HRTIM_EECR1_EE5FAST_Pos)       /*!< 0x20000000 */

+#define HRTIM_EECR1_EE5FAST           HRTIM_EECR1_EE5FAST_Msk                  /*!< External event 5 Fast mode */

+

+/*******************  Bit definition for HRTIM_EECR2 register  ****************/

+#define HRTIM_EECR2_EE6SRC_Pos        (0U)

+#define HRTIM_EECR2_EE6SRC_Msk        (0x3UL << HRTIM_EECR2_EE6SRC_Pos)        /*!< 0x00000003 */

+#define HRTIM_EECR2_EE6SRC            HRTIM_EECR2_EE6SRC_Msk                   /*!< External event 6 source */

+#define HRTIM_EECR2_EE6SRC_0          (0x1UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000001 */

+#define HRTIM_EECR2_EE6SRC_1          (0x2UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000002 */

+#define HRTIM_EECR2_EE6POL_Pos        (2U)

+#define HRTIM_EECR2_EE6POL_Msk        (0x1UL << HRTIM_EECR2_EE6POL_Pos)        /*!< 0x00000004 */

+#define HRTIM_EECR2_EE6POL            HRTIM_EECR2_EE6POL_Msk                   /*!< External event 6 Polarity */

+#define HRTIM_EECR2_EE6SNS_Pos        (3U)

+#define HRTIM_EECR2_EE6SNS_Msk        (0x3UL << HRTIM_EECR2_EE6SNS_Pos)        /*!< 0x00000018 */

+#define HRTIM_EECR2_EE6SNS            HRTIM_EECR2_EE6SNS_Msk                   /*!< External event 6 sensitivity */

+#define HRTIM_EECR2_EE6SNS_0          (0x1UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000008 */

+#define HRTIM_EECR2_EE6SNS_1          (0x2UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000010 */

+

+#define HRTIM_EECR2_EE7SRC_Pos        (6U)

+#define HRTIM_EECR2_EE7SRC_Msk        (0x3UL << HRTIM_EECR2_EE7SRC_Pos)        /*!< 0x000000C0 */

+#define HRTIM_EECR2_EE7SRC            HRTIM_EECR2_EE7SRC_Msk                   /*!< External event 7 source */

+#define HRTIM_EECR2_EE7SRC_0          (0x1UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000040 */

+#define HRTIM_EECR2_EE7SRC_1          (0x2UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000080 */

+#define HRTIM_EECR2_EE7POL_Pos        (8U)

+#define HRTIM_EECR2_EE7POL_Msk        (0x1UL << HRTIM_EECR2_EE7POL_Pos)        /*!< 0x00000100 */

+#define HRTIM_EECR2_EE7POL            HRTIM_EECR2_EE7POL_Msk                   /*!< External event 7 Polarity */

+#define HRTIM_EECR2_EE7SNS_Pos        (9U)

+#define HRTIM_EECR2_EE7SNS_Msk        (0x3UL << HRTIM_EECR2_EE7SNS_Pos)        /*!< 0x00000600 */

+#define HRTIM_EECR2_EE7SNS            HRTIM_EECR2_EE7SNS_Msk                   /*!< External event 7 sensitivity */

+#define HRTIM_EECR2_EE7SNS_0          (0x1UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000200 */

+#define HRTIM_EECR2_EE7SNS_1          (0x2UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000400 */

+

+#define HRTIM_EECR2_EE8SRC_Pos        (12U)

+#define HRTIM_EECR2_EE8SRC_Msk        (0x3UL << HRTIM_EECR2_EE8SRC_Pos)        /*!< 0x00003000 */

+#define HRTIM_EECR2_EE8SRC            HRTIM_EECR2_EE8SRC_Msk                   /*!< External event 8 source */

+#define HRTIM_EECR2_EE8SRC_0          (0x1UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00001000 */

+#define HRTIM_EECR2_EE8SRC_1          (0x2UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00002000 */

+#define HRTIM_EECR2_EE8POL_Pos        (14U)

+#define HRTIM_EECR2_EE8POL_Msk        (0x1UL << HRTIM_EECR2_EE8POL_Pos)        /*!< 0x00004000 */

+#define HRTIM_EECR2_EE8POL            HRTIM_EECR2_EE8POL_Msk                   /*!< External event 8 Polarity */

+#define HRTIM_EECR2_EE8SNS_Pos        (15U)

+#define HRTIM_EECR2_EE8SNS_Msk        (0x3UL << HRTIM_EECR2_EE8SNS_Pos)        /*!< 0x00018000 */

+#define HRTIM_EECR2_EE8SNS            HRTIM_EECR2_EE8SNS_Msk                   /*!< External event 8 sensitivity */

+#define HRTIM_EECR2_EE8SNS_0          (0x1UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00008000 */

+#define HRTIM_EECR2_EE8SNS_1          (0x2UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00010000 */

+

+#define HRTIM_EECR2_EE9SRC_Pos        (18U)

+#define HRTIM_EECR2_EE9SRC_Msk        (0x3UL << HRTIM_EECR2_EE9SRC_Pos)        /*!< 0x000C0000 */

+#define HRTIM_EECR2_EE9SRC            HRTIM_EECR2_EE9SRC_Msk                   /*!< External event 9 source */

+#define HRTIM_EECR2_EE9SRC_0          (0x1UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00040000 */

+#define HRTIM_EECR2_EE9SRC_1          (0x2UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00080000 */

+#define HRTIM_EECR2_EE9POL_Pos        (20U)

+#define HRTIM_EECR2_EE9POL_Msk        (0x1UL << HRTIM_EECR2_EE9POL_Pos)        /*!< 0x00100000 */

+#define HRTIM_EECR2_EE9POL            HRTIM_EECR2_EE9POL_Msk                   /*!< External event 9 Polarity */

+#define HRTIM_EECR2_EE9SNS_Pos        (21U)

+#define HRTIM_EECR2_EE9SNS_Msk        (0x3UL << HRTIM_EECR2_EE9SNS_Pos)        /*!< 0x00600000 */

+#define HRTIM_EECR2_EE9SNS            HRTIM_EECR2_EE9SNS_Msk                   /*!< External event 9 sensitivity */

+#define HRTIM_EECR2_EE9SNS_0          (0x1UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00200000 */

+#define HRTIM_EECR2_EE9SNS_1          (0x2UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00400000 */

+

+#define HRTIM_EECR2_EE10SRC_Pos       (24U)

+#define HRTIM_EECR2_EE10SRC_Msk       (0x3UL << HRTIM_EECR2_EE10SRC_Pos)       /*!< 0x03000000 */

+#define HRTIM_EECR2_EE10SRC           HRTIM_EECR2_EE10SRC_Msk                  /*!< External event 10 source */

+#define HRTIM_EECR2_EE10SRC_0         (0x1UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x01000000 */

+#define HRTIM_EECR2_EE10SRC_1         (0x2UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x02000000 */

+#define HRTIM_EECR2_EE10POL_Pos       (26U)

+#define HRTIM_EECR2_EE10POL_Msk       (0x1UL << HRTIM_EECR2_EE10POL_Pos)       /*!< 0x04000000 */

+#define HRTIM_EECR2_EE10POL           HRTIM_EECR2_EE10POL_Msk                  /*!< External event 10 Polarity */

+#define HRTIM_EECR2_EE10SNS_Pos       (27U)

+#define HRTIM_EECR2_EE10SNS_Msk       (0x3UL << HRTIM_EECR2_EE10SNS_Pos)       /*!< 0x18000000 */

+#define HRTIM_EECR2_EE10SNS           HRTIM_EECR2_EE10SNS_Msk                  /*!< External event 10 sensitivity */

+#define HRTIM_EECR2_EE10SNS_0         (0x1UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x08000000 */

+#define HRTIM_EECR2_EE10SNS_1         (0x2UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x10000000 */

+

+/*******************  Bit definition for HRTIM_EECR3 register  ****************/

+#define HRTIM_EECR3_EE6F_Pos          (0U)

+#define HRTIM_EECR3_EE6F_Msk          (0xFUL << HRTIM_EECR3_EE6F_Pos)          /*!< 0x0000000F */

+#define HRTIM_EECR3_EE6F              HRTIM_EECR3_EE6F_Msk                     /*!< External event 6 filter */

+#define HRTIM_EECR3_EE6F_0            (0x1UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000001 */

+#define HRTIM_EECR3_EE6F_1            (0x2UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000002 */

+#define HRTIM_EECR3_EE6F_2            (0x4UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000004 */

+#define HRTIM_EECR3_EE6F_3            (0x8UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000008 */

+#define HRTIM_EECR3_EE7F_Pos          (6U)

+#define HRTIM_EECR3_EE7F_Msk          (0xFUL << HRTIM_EECR3_EE7F_Pos)          /*!< 0x000003C0 */

+#define HRTIM_EECR3_EE7F              HRTIM_EECR3_EE7F_Msk                     /*!< External event 7 filter */

+#define HRTIM_EECR3_EE7F_0            (0x1UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000040 */

+#define HRTIM_EECR3_EE7F_1            (0x2UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000080 */

+#define HRTIM_EECR3_EE7F_2            (0x4UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000100 */

+#define HRTIM_EECR3_EE7F_3            (0x8UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000200 */

+#define HRTIM_EECR3_EE8F_Pos          (12U)

+#define HRTIM_EECR3_EE8F_Msk          (0xFUL << HRTIM_EECR3_EE8F_Pos)          /*!< 0x0000F000 */

+#define HRTIM_EECR3_EE8F              HRTIM_EECR3_EE8F_Msk                     /*!< External event 8 filter */

+#define HRTIM_EECR3_EE8F_0            (0x1UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00001000 */

+#define HRTIM_EECR3_EE8F_1            (0x2UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00002000 */

+#define HRTIM_EECR3_EE8F_2            (0x4UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00004000 */

+#define HRTIM_EECR3_EE8F_3            (0x8UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00008000 */

+#define HRTIM_EECR3_EE9F_Pos          (18U)

+#define HRTIM_EECR3_EE9F_Msk          (0xFUL << HRTIM_EECR3_EE9F_Pos)          /*!< 0x003C0000 */

+#define HRTIM_EECR3_EE9F              HRTIM_EECR3_EE9F_Msk                     /*!< External event 9 filter */

+#define HRTIM_EECR3_EE9F_0            (0x1UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00040000 */

+#define HRTIM_EECR3_EE9F_1            (0x2UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00080000 */

+#define HRTIM_EECR3_EE9F_2            (0x4UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00100000 */

+#define HRTIM_EECR3_EE9F_3            (0x8UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00200000 */

+#define HRTIM_EECR3_EE10F_Pos         (24U)

+#define HRTIM_EECR3_EE10F_Msk         (0xFUL << HRTIM_EECR3_EE10F_Pos)         /*!< 0x0F000000 */

+#define HRTIM_EECR3_EE10F             HRTIM_EECR3_EE10F_Msk                    /*!< External event 10 filter */

+#define HRTIM_EECR3_EE10F_0           (0x1UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x01000000 */

+#define HRTIM_EECR3_EE10F_1           (0x2UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x02000000 */

+#define HRTIM_EECR3_EE10F_2           (0x4UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x04000000 */

+#define HRTIM_EECR3_EE10F_3           (0x8UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x08000000 */

+#define HRTIM_EECR3_EEVSD_Pos         (30U)

+#define HRTIM_EECR3_EEVSD_Msk         (0x3UL << HRTIM_EECR3_EEVSD_Pos)         /*!< 0xC0000000 */

+#define HRTIM_EECR3_EEVSD             HRTIM_EECR3_EEVSD_Msk                    /*!< External event sampling clock division */

+#define HRTIM_EECR3_EEVSD_0           (0x1UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x40000000 */

+#define HRTIM_EECR3_EEVSD_1           (0x2UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x80000000 */

+

+/*******************  Bit definition for HRTIM_ADC1R register  ****************/

+#define HRTIM_ADC1R_AD1MC1_Pos        (0U)

+#define HRTIM_ADC1R_AD1MC1_Msk        (0x1UL << HRTIM_ADC1R_AD1MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC1R_AD1MC1            HRTIM_ADC1R_AD1MC1_Msk                   /*!< ADC Trigger 1 on master compare 1 */

+#define HRTIM_ADC1R_AD1MC2_Pos        (1U)

+#define HRTIM_ADC1R_AD1MC2_Msk        (0x1UL << HRTIM_ADC1R_AD1MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC1R_AD1MC2            HRTIM_ADC1R_AD1MC2_Msk                   /*!< ADC Trigger 1 on master compare 2 */

+#define HRTIM_ADC1R_AD1MC3_Pos        (2U)

+#define HRTIM_ADC1R_AD1MC3_Msk        (0x1UL << HRTIM_ADC1R_AD1MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC1R_AD1MC3            HRTIM_ADC1R_AD1MC3_Msk                   /*!< ADC Trigger 1 on master compare 3 */

+#define HRTIM_ADC1R_AD1MC4_Pos        (3U)

+#define HRTIM_ADC1R_AD1MC4_Msk        (0x1UL << HRTIM_ADC1R_AD1MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC1R_AD1MC4            HRTIM_ADC1R_AD1MC4_Msk                   /*!< ADC Trigger 1 on master compare 4 */

+#define HRTIM_ADC1R_AD1MPER_Pos       (4U)

+#define HRTIM_ADC1R_AD1MPER_Msk       (0x1UL << HRTIM_ADC1R_AD1MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC1R_AD1MPER           HRTIM_ADC1R_AD1MPER_Msk                  /*!< ADC Trigger 1 on master period */

+#define HRTIM_ADC1R_AD1EEV1_Pos       (5U)

+#define HRTIM_ADC1R_AD1EEV1_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC1R_AD1EEV1           HRTIM_ADC1R_AD1EEV1_Msk                  /*!< ADC Trigger 1 on external event 1 */

+#define HRTIM_ADC1R_AD1EEV2_Pos       (6U)

+#define HRTIM_ADC1R_AD1EEV2_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC1R_AD1EEV2           HRTIM_ADC1R_AD1EEV2_Msk                  /*!< ADC Trigger 1 on external event 2 */

+#define HRTIM_ADC1R_AD1EEV3_Pos       (7U)

+#define HRTIM_ADC1R_AD1EEV3_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC1R_AD1EEV3           HRTIM_ADC1R_AD1EEV3_Msk                  /*!< ADC Trigger 1 on external event 3 */

+#define HRTIM_ADC1R_AD1EEV4_Pos       (8U)

+#define HRTIM_ADC1R_AD1EEV4_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC1R_AD1EEV4           HRTIM_ADC1R_AD1EEV4_Msk                  /*!< ADC Trigger 1 on external event 4 */

+#define HRTIM_ADC1R_AD1EEV5_Pos       (9U)

+#define HRTIM_ADC1R_AD1EEV5_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos)       /*!< 0x00000200 */

+#define HRTIM_ADC1R_AD1EEV5           HRTIM_ADC1R_AD1EEV5_Msk                  /*!< ADC Trigger 1 on external event 5 */

+#define HRTIM_ADC1R_AD1TAC2_Pos       (10U)

+#define HRTIM_ADC1R_AD1TAC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC1R_AD1TAC2           HRTIM_ADC1R_AD1TAC2_Msk                  /*!< ADC Trigger 1 on Timer A compare 2 */

+#define HRTIM_ADC1R_AD1TAC3_Pos       (11U)

+#define HRTIM_ADC1R_AD1TAC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC1R_AD1TAC3           HRTIM_ADC1R_AD1TAC3_Msk                  /*!< ADC Trigger 1 on Timer A compare 3 */

+#define HRTIM_ADC1R_AD1TAC4_Pos       (12U)

+#define HRTIM_ADC1R_AD1TAC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC1R_AD1TAC4           HRTIM_ADC1R_AD1TAC4_Msk                  /*!< ADC Trigger 1 on Timer A compare 4 */

+#define HRTIM_ADC1R_AD1TAPER_Pos      (13U)

+#define HRTIM_ADC1R_AD1TAPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC1R_AD1TAPER          HRTIM_ADC1R_AD1TAPER_Msk                 /*!< ADC Trigger 1 on Timer A period */

+#define HRTIM_ADC1R_AD1TARST_Pos      (14U)

+#define HRTIM_ADC1R_AD1TARST_Msk      (0x1UL << HRTIM_ADC1R_AD1TARST_Pos)      /*!< 0x00004000 */

+#define HRTIM_ADC1R_AD1TARST          HRTIM_ADC1R_AD1TARST_Msk                 /*!< ADC Trigger 1 on Timer A reset */

+#define HRTIM_ADC1R_AD1TBC2_Pos       (15U)

+#define HRTIM_ADC1R_AD1TBC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC2_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC1R_AD1TBC2           HRTIM_ADC1R_AD1TBC2_Msk                  /*!< ADC Trigger 1 on Timer B compare 2 */

+#define HRTIM_ADC1R_AD1TBC3_Pos       (16U)

+#define HRTIM_ADC1R_AD1TBC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC1R_AD1TBC3           HRTIM_ADC1R_AD1TBC3_Msk                  /*!< ADC Trigger 1 on Timer B compare 3 */

+#define HRTIM_ADC1R_AD1TBC4_Pos       (17U)

+#define HRTIM_ADC1R_AD1TBC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos)       /*!< 0x00020000 */

+#define HRTIM_ADC1R_AD1TBC4           HRTIM_ADC1R_AD1TBC4_Msk                  /*!< ADC Trigger 1 on Timer B compare 4 */

+#define HRTIM_ADC1R_AD1TBPER_Pos      (18U)

+#define HRTIM_ADC1R_AD1TBPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos)      /*!< 0x00040000 */

+#define HRTIM_ADC1R_AD1TBPER          HRTIM_ADC1R_AD1TBPER_Msk                 /*!< ADC Trigger 1 on Timer B period */

+#define HRTIM_ADC1R_AD1TBRST_Pos      (19U)

+#define HRTIM_ADC1R_AD1TBRST_Msk      (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos)      /*!< 0x00080000 */

+#define HRTIM_ADC1R_AD1TBRST          HRTIM_ADC1R_AD1TBRST_Msk                 /*!< ADC Trigger 1 on Timer B reset */

+#define HRTIM_ADC1R_AD1TCC2_Pos       (20U)

+#define HRTIM_ADC1R_AD1TCC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC2_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC1R_AD1TCC2           HRTIM_ADC1R_AD1TCC2_Msk                  /*!< ADC Trigger 1 on Timer C compare 2 */

+#define HRTIM_ADC1R_AD1TCC3_Pos       (21U)

+#define HRTIM_ADC1R_AD1TCC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos)       /*!< 0x00200000 */

+#define HRTIM_ADC1R_AD1TCC3           HRTIM_ADC1R_AD1TCC3_Msk                  /*!< ADC Trigger 1 on Timer C compare 3 */

+#define HRTIM_ADC1R_AD1TCC4_Pos       (22U)

+#define HRTIM_ADC1R_AD1TCC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos)       /*!< 0x00400000 */

+#define HRTIM_ADC1R_AD1TCC4           HRTIM_ADC1R_AD1TCC4_Msk                  /*!< ADC Trigger 1 on Timer C compare 4 */

+#define HRTIM_ADC1R_AD1TCPER_Pos      (23U)

+#define HRTIM_ADC1R_AD1TCPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos)      /*!< 0x00800000 */

+#define HRTIM_ADC1R_AD1TCPER          HRTIM_ADC1R_AD1TCPER_Msk                 /*!< ADC Trigger 1 on Timer C period */

+#define HRTIM_ADC1R_AD1TDC2_Pos       (24U)

+#define HRTIM_ADC1R_AD1TDC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC2_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC1R_AD1TDC2           HRTIM_ADC1R_AD1TDC2_Msk                  /*!< ADC Trigger 1 on Timer D compare 2 */

+#define HRTIM_ADC1R_AD1TDC3_Pos       (25U)

+#define HRTIM_ADC1R_AD1TDC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC1R_AD1TDC3           HRTIM_ADC1R_AD1TDC3_Msk                  /*!< ADC Trigger 1 on Timer D compare 3 */

+#define HRTIM_ADC1R_AD1TDC4_Pos       (26U)

+#define HRTIM_ADC1R_AD1TDC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos)       /*!< 0x04000000 */

+#define HRTIM_ADC1R_AD1TDC4           HRTIM_ADC1R_AD1TDC4_Msk                  /*!< ADC Trigger 1 on Timer D compare 4 */

+#define HRTIM_ADC1R_AD1TDPER_Pos      (27U)

+#define HRTIM_ADC1R_AD1TDPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC1R_AD1TDPER          HRTIM_ADC1R_AD1TDPER_Msk                 /*!< ADC Trigger 1 on Timer D period */

+#define HRTIM_ADC1R_AD1TEC2_Pos       (28U)

+#define HRTIM_ADC1R_AD1TEC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC1R_AD1TEC2           HRTIM_ADC1R_AD1TEC2_Msk                  /*!< ADC Trigger 1 on Timer E compare 2 */

+#define HRTIM_ADC1R_AD1TEC3_Pos       (29U)

+#define HRTIM_ADC1R_AD1TEC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC1R_AD1TEC3           HRTIM_ADC1R_AD1TEC3_Msk                  /*!< ADC Trigger 1 on Timer E compare 3 */

+#define HRTIM_ADC1R_AD1TEC4_Pos       (30U)

+#define HRTIM_ADC1R_AD1TEC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC1R_AD1TEC4           HRTIM_ADC1R_AD1TEC4_Msk                  /*!< ADC Trigger 1 on Timer E compare 4 */

+#define HRTIM_ADC1R_AD1TEPER_Pos      (31U)

+#define HRTIM_ADC1R_AD1TEPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC1R_AD1TEPER          HRTIM_ADC1R_AD1TEPER_Msk                 /*!< ADC Trigger 1 on Timer E period */

+

+/*******************  Bit definition for HRTIM_ADC2R register  ****************/

+#define HRTIM_ADC2R_AD2MC1_Pos        (0U)

+#define HRTIM_ADC2R_AD2MC1_Msk        (0x1UL << HRTIM_ADC2R_AD2MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC2R_AD2MC1            HRTIM_ADC2R_AD2MC1_Msk                   /*!< ADC Trigger 2 on master compare 1 */

+#define HRTIM_ADC2R_AD2MC2_Pos        (1U)

+#define HRTIM_ADC2R_AD2MC2_Msk        (0x1UL << HRTIM_ADC2R_AD2MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC2R_AD2MC2            HRTIM_ADC2R_AD2MC2_Msk                   /*!< ADC Trigger 2 on master compare 2 */

+#define HRTIM_ADC2R_AD2MC3_Pos        (2U)

+#define HRTIM_ADC2R_AD2MC3_Msk        (0x1UL << HRTIM_ADC2R_AD2MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC2R_AD2MC3            HRTIM_ADC2R_AD2MC3_Msk                   /*!< ADC Trigger 2 on master compare 3 */

+#define HRTIM_ADC2R_AD2MC4_Pos        (3U)

+#define HRTIM_ADC2R_AD2MC4_Msk        (0x1UL << HRTIM_ADC2R_AD2MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC2R_AD2MC4            HRTIM_ADC2R_AD2MC4_Msk                   /*!< ADC Trigger 2 on master compare 4 */

+#define HRTIM_ADC2R_AD2MPER_Pos       (4U)

+#define HRTIM_ADC2R_AD2MPER_Msk       (0x1UL << HRTIM_ADC2R_AD2MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC2R_AD2MPER           HRTIM_ADC2R_AD2MPER_Msk                  /*!< ADC Trigger 2 on master period */

+#define HRTIM_ADC2R_AD2EEV6_Pos       (5U)

+#define HRTIM_ADC2R_AD2EEV6_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC2R_AD2EEV6           HRTIM_ADC2R_AD2EEV6_Msk                  /*!< ADC Trigger 2 on external event 6 */

+#define HRTIM_ADC2R_AD2EEV7_Pos       (6U)

+#define HRTIM_ADC2R_AD2EEV7_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC2R_AD2EEV7           HRTIM_ADC2R_AD2EEV7_Msk                  /*!< ADC Trigger 2 on external event 7 */

+#define HRTIM_ADC2R_AD2EEV8_Pos       (7U)

+#define HRTIM_ADC2R_AD2EEV8_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC2R_AD2EEV8           HRTIM_ADC2R_AD2EEV8_Msk                  /*!< ADC Trigger 2 on external event 8 */

+#define HRTIM_ADC2R_AD2EEV9_Pos       (8U)

+#define HRTIM_ADC2R_AD2EEV9_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC2R_AD2EEV9           HRTIM_ADC2R_AD2EEV9_Msk                  /*!< ADC Trigger 2 on external event 9 */

+#define HRTIM_ADC2R_AD2EEV10_Pos      (9U)

+#define HRTIM_ADC2R_AD2EEV10_Msk      (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos)      /*!< 0x00000200 */

+#define HRTIM_ADC2R_AD2EEV10          HRTIM_ADC2R_AD2EEV10_Msk                 /*!< ADC Trigger 2 on external event 10 */

+#define HRTIM_ADC2R_AD2TAC2_Pos       (10U)

+#define HRTIM_ADC2R_AD2TAC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC2R_AD2TAC2           HRTIM_ADC2R_AD2TAC2_Msk                  /*!< ADC Trigger 2 on Timer A compare 2 */

+#define HRTIM_ADC2R_AD2TAC3_Pos       (11U)

+#define HRTIM_ADC2R_AD2TAC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC2R_AD2TAC3           HRTIM_ADC2R_AD2TAC3_Msk                  /*!< ADC Trigger 2 on Timer A compare 3 */

+#define HRTIM_ADC2R_AD2TAC4_Pos       (12U)

+#define HRTIM_ADC2R_AD2TAC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC2R_AD2TAC4           HRTIM_ADC2R_AD2TAC4_Msk                  /*!< ADC Trigger 2 on Timer A compare 4*/

+#define HRTIM_ADC2R_AD2TAPER_Pos      (13U)

+#define HRTIM_ADC2R_AD2TAPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC2R_AD2TAPER          HRTIM_ADC2R_AD2TAPER_Msk                 /*!< ADC Trigger 2 on Timer A period */

+#define HRTIM_ADC2R_AD2TBC2_Pos       (14U)

+#define HRTIM_ADC2R_AD2TBC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos)       /*!< 0x00004000 */

+#define HRTIM_ADC2R_AD2TBC2           HRTIM_ADC2R_AD2TBC2_Msk                  /*!< ADC Trigger 2 on Timer B compare 2 */

+#define HRTIM_ADC2R_AD2TBC3_Pos       (15U)

+#define HRTIM_ADC2R_AD2TBC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC3_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC2R_AD2TBC3           HRTIM_ADC2R_AD2TBC3_Msk                  /*!< ADC Trigger 2 on Timer B compare 3 */

+#define HRTIM_ADC2R_AD2TBC4_Pos       (16U)

+#define HRTIM_ADC2R_AD2TBC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC2R_AD2TBC4           HRTIM_ADC2R_AD2TBC4_Msk                  /*!< ADC Trigger 2 on Timer B compare 4 */

+#define HRTIM_ADC2R_AD2TBPER_Pos      (17U)

+#define HRTIM_ADC2R_AD2TBPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos)      /*!< 0x00020000 */

+#define HRTIM_ADC2R_AD2TBPER          HRTIM_ADC2R_AD2TBPER_Msk                 /*!< ADC Trigger 2 on Timer B period */

+#define HRTIM_ADC2R_AD2TCC2_Pos       (18U)

+#define HRTIM_ADC2R_AD2TCC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos)       /*!< 0x00040000 */

+#define HRTIM_ADC2R_AD2TCC2           HRTIM_ADC2R_AD2TCC2_Msk                  /*!< ADC Trigger 2 on Timer C compare 2 */

+#define HRTIM_ADC2R_AD2TCC3_Pos       (19U)

+#define HRTIM_ADC2R_AD2TCC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC3_Pos)       /*!< 0x00080000 */

+#define HRTIM_ADC2R_AD2TCC3           HRTIM_ADC2R_AD2TCC3_Msk                  /*!< ADC Trigger 2 on Timer C compare 3 */

+#define HRTIM_ADC2R_AD2TCC4_Pos       (20U)

+#define HRTIM_ADC2R_AD2TCC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC2R_AD2TCC4           HRTIM_ADC2R_AD2TCC4_Msk                  /*!< ADC Trigger 2 on Timer C compare 4 */

+#define HRTIM_ADC2R_AD2TCPER_Pos      (21U)

+#define HRTIM_ADC2R_AD2TCPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos)      /*!< 0x00200000 */

+#define HRTIM_ADC2R_AD2TCPER          HRTIM_ADC2R_AD2TCPER_Msk                 /*!< ADC Trigger 2 on Timer C period */

+#define HRTIM_ADC2R_AD2TCRST_Pos      (22U)

+#define HRTIM_ADC2R_AD2TCRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos)      /*!< 0x00400000 */

+#define HRTIM_ADC2R_AD2TCRST          HRTIM_ADC2R_AD2TCRST_Msk                 /*!< ADC Trigger 2 on Timer C reset */

+#define HRTIM_ADC2R_AD2TDC2_Pos       (23U)

+#define HRTIM_ADC2R_AD2TDC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos)       /*!< 0x00800000 */

+#define HRTIM_ADC2R_AD2TDC2           HRTIM_ADC2R_AD2TDC2_Msk                  /*!< ADC Trigger 2 on Timer D compare 2 */

+#define HRTIM_ADC2R_AD2TDC3_Pos       (24U)

+#define HRTIM_ADC2R_AD2TDC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC3_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC2R_AD2TDC3           HRTIM_ADC2R_AD2TDC3_Msk                  /*!< ADC Trigger 2 on Timer D compare 3 */

+#define HRTIM_ADC2R_AD2TDC4_Pos       (25U)

+#define HRTIM_ADC2R_AD2TDC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC2R_AD2TDC4           HRTIM_ADC2R_AD2TDC4_Msk                  /*!< ADC Trigger 2 on Timer D compare 4*/

+#define HRTIM_ADC2R_AD2TDPER_Pos      (26U)

+#define HRTIM_ADC2R_AD2TDPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos)      /*!< 0x04000000 */

+#define HRTIM_ADC2R_AD2TDPER          HRTIM_ADC2R_AD2TDPER_Msk                 /*!< ADC Trigger 2 on Timer D period */

+#define HRTIM_ADC2R_AD2TDRST_Pos      (27U)

+#define HRTIM_ADC2R_AD2TDRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC2R_AD2TDRST          HRTIM_ADC2R_AD2TDRST_Msk                 /*!< ADC Trigger 2 on Timer D reset */

+#define HRTIM_ADC2R_AD2TEC2_Pos       (28U)

+#define HRTIM_ADC2R_AD2TEC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC2R_AD2TEC2           HRTIM_ADC2R_AD2TEC2_Msk                  /*!< ADC Trigger 2 on Timer E compare 2 */

+#define HRTIM_ADC2R_AD2TEC3_Pos       (29U)

+#define HRTIM_ADC2R_AD2TEC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC2R_AD2TEC3           HRTIM_ADC2R_AD2TEC3_Msk                  /*!< ADC Trigger 2 on Timer E compare 3 */

+#define HRTIM_ADC2R_AD2TEC4_Pos       (30U)

+#define HRTIM_ADC2R_AD2TEC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC2R_AD2TEC4           HRTIM_ADC2R_AD2TEC4_Msk                  /*!< ADC Trigger 2 on Timer E compare 4 */

+#define HRTIM_ADC2R_AD2TERST_Pos      (31U)

+#define HRTIM_ADC2R_AD2TERST_Msk      (0x1UL << HRTIM_ADC2R_AD2TERST_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC2R_AD2TERST          HRTIM_ADC2R_AD2TERST_Msk                 /*!< ADC Trigger 2 on Timer E reset */

+

+/*******************  Bit definition for HRTIM_ADC3R register  ****************/

+#define HRTIM_ADC3R_AD3MC1_Pos        (0U)

+#define HRTIM_ADC3R_AD3MC1_Msk        (0x1UL << HRTIM_ADC3R_AD3MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC3R_AD3MC1            HRTIM_ADC3R_AD3MC1_Msk                   /*!< ADC Trigger 3 on master compare 1 */

+#define HRTIM_ADC3R_AD3MC2_Pos        (1U)

+#define HRTIM_ADC3R_AD3MC2_Msk        (0x1UL << HRTIM_ADC3R_AD3MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC3R_AD3MC2            HRTIM_ADC3R_AD3MC2_Msk                   /*!< ADC Trigger 3 on master compare 2 */

+#define HRTIM_ADC3R_AD3MC3_Pos        (2U)

+#define HRTIM_ADC3R_AD3MC3_Msk        (0x1UL << HRTIM_ADC3R_AD3MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC3R_AD3MC3            HRTIM_ADC3R_AD3MC3_Msk                   /*!< ADC Trigger 3 on master compare 3 */

+#define HRTIM_ADC3R_AD3MC4_Pos        (3U)

+#define HRTIM_ADC3R_AD3MC4_Msk        (0x1UL << HRTIM_ADC3R_AD3MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC3R_AD3MC4            HRTIM_ADC3R_AD3MC4_Msk                   /*!< ADC Trigger 3 on master compare 4 */

+#define HRTIM_ADC3R_AD3MPER_Pos       (4U)

+#define HRTIM_ADC3R_AD3MPER_Msk       (0x1UL << HRTIM_ADC3R_AD3MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC3R_AD3MPER           HRTIM_ADC3R_AD3MPER_Msk                  /*!< ADC Trigger 3 on master period */

+#define HRTIM_ADC3R_AD3EEV1_Pos       (5U)

+#define HRTIM_ADC3R_AD3EEV1_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC3R_AD3EEV1           HRTIM_ADC3R_AD3EEV1_Msk                  /*!< ADC Trigger 3 on external event 1 */

+#define HRTIM_ADC3R_AD3EEV2_Pos       (6U)

+#define HRTIM_ADC3R_AD3EEV2_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC3R_AD3EEV2           HRTIM_ADC3R_AD3EEV2_Msk                  /*!< ADC Trigger 3 on external event 2 */

+#define HRTIM_ADC3R_AD3EEV3_Pos       (7U)

+#define HRTIM_ADC3R_AD3EEV3_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC3R_AD3EEV3           HRTIM_ADC3R_AD3EEV3_Msk                  /*!< ADC Trigger 3 on external event 3 */

+#define HRTIM_ADC3R_AD3EEV4_Pos       (8U)

+#define HRTIM_ADC3R_AD3EEV4_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC3R_AD3EEV4           HRTIM_ADC3R_AD3EEV4_Msk                  /*!< ADC Trigger 3 on external event 4 */

+#define HRTIM_ADC3R_AD3EEV5_Pos       (9U)

+#define HRTIM_ADC3R_AD3EEV5_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos)       /*!< 0x00000200 */

+#define HRTIM_ADC3R_AD3EEV5           HRTIM_ADC3R_AD3EEV5_Msk                  /*!< ADC Trigger 3 on external event 5 */

+#define HRTIM_ADC3R_AD3TAC2_Pos       (10U)

+#define HRTIM_ADC3R_AD3TAC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC3R_AD3TAC2           HRTIM_ADC3R_AD3TAC2_Msk                  /*!< ADC Trigger 3 on Timer A compare 2 */

+#define HRTIM_ADC3R_AD3TAC3_Pos       (11U)

+#define HRTIM_ADC3R_AD3TAC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC3R_AD3TAC3           HRTIM_ADC3R_AD3TAC3_Msk                  /*!< ADC Trigger 3 on Timer A compare 3 */

+#define HRTIM_ADC3R_AD3TAC4_Pos       (12U)

+#define HRTIM_ADC3R_AD3TAC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC3R_AD3TAC4           HRTIM_ADC3R_AD3TAC4_Msk                  /*!< ADC Trigger 3 on Timer A compare 4 */

+#define HRTIM_ADC3R_AD3TAPER_Pos      (13U)

+#define HRTIM_ADC3R_AD3TAPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC3R_AD3TAPER          HRTIM_ADC3R_AD3TAPER_Msk                 /*!< ADC Trigger 3 on Timer A period */

+#define HRTIM_ADC3R_AD3TARST_Pos      (14U)

+#define HRTIM_ADC3R_AD3TARST_Msk      (0x1UL << HRTIM_ADC3R_AD3TARST_Pos)      /*!< 0x00004000 */

+#define HRTIM_ADC3R_AD3TARST          HRTIM_ADC3R_AD3TARST_Msk                 /*!< ADC Trigger 3 on Timer A reset */

+#define HRTIM_ADC3R_AD3TBC2_Pos       (15U)

+#define HRTIM_ADC3R_AD3TBC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC2_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC3R_AD3TBC2           HRTIM_ADC3R_AD3TBC2_Msk                  /*!< ADC Trigger 3 on Timer B compare 2 */

+#define HRTIM_ADC3R_AD3TBC3_Pos       (16U)

+#define HRTIM_ADC3R_AD3TBC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC3R_AD3TBC3           HRTIM_ADC3R_AD3TBC3_Msk                  /*!< ADC Trigger 3 on Timer B compare 3 */

+#define HRTIM_ADC3R_AD3TBC4_Pos       (17U)

+#define HRTIM_ADC3R_AD3TBC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos)       /*!< 0x00020000 */

+#define HRTIM_ADC3R_AD3TBC4           HRTIM_ADC3R_AD3TBC4_Msk                  /*!< ADC Trigger 3 on Timer B compare 4 */

+#define HRTIM_ADC3R_AD3TBPER_Pos      (18U)

+#define HRTIM_ADC3R_AD3TBPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos)      /*!< 0x00040000 */

+#define HRTIM_ADC3R_AD3TBPER          HRTIM_ADC3R_AD3TBPER_Msk                 /*!< ADC Trigger 3 on Timer B period */

+#define HRTIM_ADC3R_AD3TBRST_Pos      (19U)

+#define HRTIM_ADC3R_AD3TBRST_Msk      (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos)      /*!< 0x00080000 */

+#define HRTIM_ADC3R_AD3TBRST          HRTIM_ADC3R_AD3TBRST_Msk                 /*!< ADC Trigger 3 on Timer B reset */

+#define HRTIM_ADC3R_AD3TCC2_Pos       (20U)

+#define HRTIM_ADC3R_AD3TCC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC2_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC3R_AD3TCC2           HRTIM_ADC3R_AD3TCC2_Msk                  /*!< ADC Trigger 3 on Timer C compare 2 */

+#define HRTIM_ADC3R_AD3TCC3_Pos       (21U)

+#define HRTIM_ADC3R_AD3TCC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos)       /*!< 0x00200000 */

+#define HRTIM_ADC3R_AD3TCC3           HRTIM_ADC3R_AD3TCC3_Msk                  /*!< ADC Trigger 3 on Timer C compare 3 */

+#define HRTIM_ADC3R_AD3TCC4_Pos       (22U)

+#define HRTIM_ADC3R_AD3TCC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos)       /*!< 0x00400000 */

+#define HRTIM_ADC3R_AD3TCC4           HRTIM_ADC3R_AD3TCC4_Msk                  /*!< ADC Trigger 3 on Timer C compare 4 */

+#define HRTIM_ADC3R_AD3TCPER_Pos      (23U)

+#define HRTIM_ADC3R_AD3TCPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos)      /*!< 0x00800000 */

+#define HRTIM_ADC3R_AD3TCPER          HRTIM_ADC3R_AD3TCPER_Msk                 /*!< ADC Trigger 3 on Timer C period */

+#define HRTIM_ADC3R_AD3TDC2_Pos       (24U)

+#define HRTIM_ADC3R_AD3TDC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC2_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC3R_AD3TDC2           HRTIM_ADC3R_AD3TDC2_Msk                  /*!< ADC Trigger 3 on Timer D compare 2 */

+#define HRTIM_ADC3R_AD3TDC3_Pos       (25U)

+#define HRTIM_ADC3R_AD3TDC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC3R_AD3TDC3           HRTIM_ADC3R_AD3TDC3_Msk                  /*!< ADC Trigger 3 on Timer D compare 3 */

+#define HRTIM_ADC3R_AD3TDC4_Pos       (26U)

+#define HRTIM_ADC3R_AD3TDC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos)       /*!< 0x04000000 */

+#define HRTIM_ADC3R_AD3TDC4           HRTIM_ADC3R_AD3TDC4_Msk                  /*!< ADC Trigger 3 on Timer D compare 4 */

+#define HRTIM_ADC3R_AD3TDPER_Pos      (27U)

+#define HRTIM_ADC3R_AD3TDPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC3R_AD3TDPER          HRTIM_ADC3R_AD3TDPER_Msk                 /*!< ADC Trigger 3 on Timer D period */

+#define HRTIM_ADC3R_AD3TEC2_Pos       (28U)

+#define HRTIM_ADC3R_AD3TEC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC3R_AD3TEC2           HRTIM_ADC3R_AD3TEC2_Msk                  /*!< ADC Trigger 3 on Timer E compare 2 */

+#define HRTIM_ADC3R_AD3TEC3_Pos       (29U)

+#define HRTIM_ADC3R_AD3TEC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC3R_AD3TEC3           HRTIM_ADC3R_AD3TEC3_Msk                  /*!< ADC Trigger 3 on Timer E compare 3 */

+#define HRTIM_ADC3R_AD3TEC4_Pos       (30U)

+#define HRTIM_ADC3R_AD3TEC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC3R_AD3TEC4           HRTIM_ADC3R_AD3TEC4_Msk                  /*!< ADC Trigger 3 on Timer E compare 4 */

+#define HRTIM_ADC3R_AD3TEPER_Pos      (31U)

+#define HRTIM_ADC3R_AD3TEPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC3R_AD3TEPER          HRTIM_ADC3R_AD3TEPER_Msk                 /*!< ADC Trigger 3 on Timer E period */

+

+/*******************  Bit definition for HRTIM_ADC4R register  ****************/

+#define HRTIM_ADC4R_AD4MC1_Pos        (0U)

+#define HRTIM_ADC4R_AD4MC1_Msk        (0x1UL << HRTIM_ADC4R_AD4MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC4R_AD4MC1            HRTIM_ADC4R_AD4MC1_Msk                   /*!< ADC Trigger 4 on master compare 1 */

+#define HRTIM_ADC4R_AD4MC2_Pos        (1U)

+#define HRTIM_ADC4R_AD4MC2_Msk        (0x1UL << HRTIM_ADC4R_AD4MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC4R_AD4MC2            HRTIM_ADC4R_AD4MC2_Msk                   /*!< ADC Trigger 4 on master compare 2 */

+#define HRTIM_ADC4R_AD4MC3_Pos        (2U)

+#define HRTIM_ADC4R_AD4MC3_Msk        (0x1UL << HRTIM_ADC4R_AD4MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC4R_AD4MC3            HRTIM_ADC4R_AD4MC3_Msk                   /*!< ADC Trigger 4 on master compare 3 */

+#define HRTIM_ADC4R_AD4MC4_Pos        (3U)

+#define HRTIM_ADC4R_AD4MC4_Msk        (0x1UL << HRTIM_ADC4R_AD4MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC4R_AD4MC4            HRTIM_ADC4R_AD4MC4_Msk                   /*!< ADC Trigger 4 on master compare 4 */

+#define HRTIM_ADC4R_AD4MPER_Pos       (4U)

+#define HRTIM_ADC4R_AD4MPER_Msk       (0x1UL << HRTIM_ADC4R_AD4MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC4R_AD4MPER           HRTIM_ADC4R_AD4MPER_Msk                  /*!< ADC Trigger 4 on master period */

+#define HRTIM_ADC4R_AD4EEV6_Pos       (5U)

+#define HRTIM_ADC4R_AD4EEV6_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC4R_AD4EEV6           HRTIM_ADC4R_AD4EEV6_Msk                  /*!< ADC Trigger 4 on external event 6 */

+#define HRTIM_ADC4R_AD4EEV7_Pos       (6U)

+#define HRTIM_ADC4R_AD4EEV7_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC4R_AD4EEV7           HRTIM_ADC4R_AD4EEV7_Msk                  /*!< ADC Trigger 4 on external event 7 */

+#define HRTIM_ADC4R_AD4EEV8_Pos       (7U)

+#define HRTIM_ADC4R_AD4EEV8_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC4R_AD4EEV8           HRTIM_ADC4R_AD4EEV8_Msk                  /*!< ADC Trigger 4 on external event 8 */

+#define HRTIM_ADC4R_AD4EEV9_Pos       (8U)

+#define HRTIM_ADC4R_AD4EEV9_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC4R_AD4EEV9           HRTIM_ADC4R_AD4EEV9_Msk                  /*!< ADC Trigger 4 on external event 9 */

+#define HRTIM_ADC4R_AD4EEV10_Pos      (9U)

+#define HRTIM_ADC4R_AD4EEV10_Msk      (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos)      /*!< 0x00000200 */

+#define HRTIM_ADC4R_AD4EEV10          HRTIM_ADC4R_AD4EEV10_Msk                 /*!< ADC Trigger 4 on external event 10 */

+#define HRTIM_ADC4R_AD4TAC2_Pos       (10U)

+#define HRTIM_ADC4R_AD4TAC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC4R_AD4TAC2           HRTIM_ADC4R_AD4TAC2_Msk                  /*!< ADC Trigger 4 on Timer A compare 2 */

+#define HRTIM_ADC4R_AD4TAC3_Pos       (11U)

+#define HRTIM_ADC4R_AD4TAC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC4R_AD4TAC3           HRTIM_ADC4R_AD4TAC3_Msk                  /*!< ADC Trigger 4 on Timer A compare 3 */

+#define HRTIM_ADC4R_AD4TAC4_Pos       (12U)

+#define HRTIM_ADC4R_AD4TAC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC4R_AD4TAC4           HRTIM_ADC4R_AD4TAC4_Msk                  /*!< ADC Trigger 4 on Timer A compare 4*/

+#define HRTIM_ADC4R_AD4TAPER_Pos      (13U)

+#define HRTIM_ADC4R_AD4TAPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC4R_AD4TAPER          HRTIM_ADC4R_AD4TAPER_Msk                 /*!< ADC Trigger 4 on Timer A period */

+#define HRTIM_ADC4R_AD4TBC2_Pos       (14U)

+#define HRTIM_ADC4R_AD4TBC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos)       /*!< 0x00004000 */

+#define HRTIM_ADC4R_AD4TBC2           HRTIM_ADC4R_AD4TBC2_Msk                  /*!< ADC Trigger 4 on Timer B compare 2 */

+#define HRTIM_ADC4R_AD4TBC3_Pos       (15U)

+#define HRTIM_ADC4R_AD4TBC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC3_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC4R_AD4TBC3           HRTIM_ADC4R_AD4TBC3_Msk                  /*!< ADC Trigger 4 on Timer B compare 3 */

+#define HRTIM_ADC4R_AD4TBC4_Pos       (16U)

+#define HRTIM_ADC4R_AD4TBC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC4R_AD4TBC4           HRTIM_ADC4R_AD4TBC4_Msk                  /*!< ADC Trigger 4 on Timer B compare 4 */

+#define HRTIM_ADC4R_AD4TBPER_Pos      (17U)

+#define HRTIM_ADC4R_AD4TBPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos)      /*!< 0x00020000 */

+#define HRTIM_ADC4R_AD4TBPER          HRTIM_ADC4R_AD4TBPER_Msk                 /*!< ADC Trigger 4 on Timer B period */

+#define HRTIM_ADC4R_AD4TCC2_Pos       (18U)

+#define HRTIM_ADC4R_AD4TCC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos)       /*!< 0x00040000 */

+#define HRTIM_ADC4R_AD4TCC2           HRTIM_ADC4R_AD4TCC2_Msk                  /*!< ADC Trigger 4 on Timer C compare 2 */

+#define HRTIM_ADC4R_AD4TCC3_Pos       (19U)

+#define HRTIM_ADC4R_AD4TCC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC3_Pos)       /*!< 0x00080000 */

+#define HRTIM_ADC4R_AD4TCC3           HRTIM_ADC4R_AD4TCC3_Msk                  /*!< ADC Trigger 4 on Timer C compare 3 */

+#define HRTIM_ADC4R_AD4TCC4_Pos       (20U)

+#define HRTIM_ADC4R_AD4TCC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC4R_AD4TCC4           HRTIM_ADC4R_AD4TCC4_Msk                  /*!< ADC Trigger 4 on Timer C compare 4 */

+#define HRTIM_ADC4R_AD4TCPER_Pos      (21U)

+#define HRTIM_ADC4R_AD4TCPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos)      /*!< 0x00200000 */

+#define HRTIM_ADC4R_AD4TCPER          HRTIM_ADC4R_AD4TCPER_Msk                 /*!< ADC Trigger 4 on Timer C period */

+#define HRTIM_ADC4R_AD4TCRST_Pos      (22U)

+#define HRTIM_ADC4R_AD4TCRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos)      /*!< 0x00400000 */

+#define HRTIM_ADC4R_AD4TCRST          HRTIM_ADC4R_AD4TCRST_Msk                 /*!< ADC Trigger 4 on Timer C reset */

+#define HRTIM_ADC4R_AD4TDC2_Pos       (23U)

+#define HRTIM_ADC4R_AD4TDC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos)       /*!< 0x00800000 */

+#define HRTIM_ADC4R_AD4TDC2           HRTIM_ADC4R_AD4TDC2_Msk                  /*!< ADC Trigger 4 on Timer D compare 2 */

+#define HRTIM_ADC4R_AD4TDC3_Pos       (24U)

+#define HRTIM_ADC4R_AD4TDC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC3_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC4R_AD4TDC3           HRTIM_ADC4R_AD4TDC3_Msk                  /*!< ADC Trigger 4 on Timer D compare 3 */

+#define HRTIM_ADC4R_AD4TDC4_Pos       (25U)

+#define HRTIM_ADC4R_AD4TDC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC4R_AD4TDC4           HRTIM_ADC4R_AD4TDC4_Msk                  /*!< ADC Trigger 4 on Timer D compare 4*/

+#define HRTIM_ADC4R_AD4TDPER_Pos      (26U)

+#define HRTIM_ADC4R_AD4TDPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos)      /*!< 0x04000000 */

+#define HRTIM_ADC4R_AD4TDPER          HRTIM_ADC4R_AD4TDPER_Msk                 /*!< ADC Trigger 4 on Timer D period */

+#define HRTIM_ADC4R_AD4TDRST_Pos      (27U)

+#define HRTIM_ADC4R_AD4TDRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC4R_AD4TDRST          HRTIM_ADC4R_AD4TDRST_Msk                 /*!< ADC Trigger 4 on Timer D reset */

+#define HRTIM_ADC4R_AD4TEC2_Pos       (28U)

+#define HRTIM_ADC4R_AD4TEC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC4R_AD4TEC2           HRTIM_ADC4R_AD4TEC2_Msk                  /*!< ADC Trigger 4 on Timer E compare 2 */

+#define HRTIM_ADC4R_AD4TEC3_Pos       (29U)

+#define HRTIM_ADC4R_AD4TEC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC4R_AD4TEC3           HRTIM_ADC4R_AD4TEC3_Msk                  /*!< ADC Trigger 4 on Timer E compare 3 */

+#define HRTIM_ADC4R_AD4TEC4_Pos       (30U)

+#define HRTIM_ADC4R_AD4TEC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC4R_AD4TEC4           HRTIM_ADC4R_AD4TEC4_Msk                  /*!< ADC Trigger 4 on Timer E compare 4 */

+#define HRTIM_ADC4R_AD4TERST_Pos      (31U)

+#define HRTIM_ADC4R_AD4TERST_Msk      (0x1UL << HRTIM_ADC4R_AD4TERST_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC4R_AD4TERST          HRTIM_ADC4R_AD4TERST_Msk                 /*!< ADC Trigger 4 on Timer E reset */

+

+/*******************  Bit definition for HRTIM_FLTINR1 register  ***************/

+#define HRTIM_FLTINR1_FLT1E_Pos       (0U)

+#define HRTIM_FLTINR1_FLT1E_Msk       (0x1UL << HRTIM_FLTINR1_FLT1E_Pos)       /*!< 0x00000001 */

+#define HRTIM_FLTINR1_FLT1E           HRTIM_FLTINR1_FLT1E_Msk                  /*!< Fault 1 enable */

+#define HRTIM_FLTINR1_FLT1P_Pos       (1U)

+#define HRTIM_FLTINR1_FLT1P_Msk       (0x1UL << HRTIM_FLTINR1_FLT1P_Pos)       /*!< 0x00000002 */

+#define HRTIM_FLTINR1_FLT1P           HRTIM_FLTINR1_FLT1P_Msk                  /*!< Fault 1 polarity */

+#define HRTIM_FLTINR1_FLT1SRC_Pos     (2U)

+#define HRTIM_FLTINR1_FLT1SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT1SRC_Pos)     /*!< 0x00000004 */

+#define HRTIM_FLTINR1_FLT1SRC         HRTIM_FLTINR1_FLT1SRC_Msk                /*!< Fault 1 source */

+#define HRTIM_FLTINR1_FLT1F_Pos       (3U)

+#define HRTIM_FLTINR1_FLT1F_Msk       (0xFUL << HRTIM_FLTINR1_FLT1F_Pos)       /*!< 0x00000078 */

+#define HRTIM_FLTINR1_FLT1F           HRTIM_FLTINR1_FLT1F_Msk                  /*!< Fault 1 filter */

+#define HRTIM_FLTINR1_FLT1F_0         (0x1UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000008 */

+#define HRTIM_FLTINR1_FLT1F_1         (0x2UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000010 */

+#define HRTIM_FLTINR1_FLT1F_2         (0x4UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000020 */

+#define HRTIM_FLTINR1_FLT1F_3         (0x8UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000040 */

+#define HRTIM_FLTINR1_FLT1LCK_Pos     (7U)

+#define HRTIM_FLTINR1_FLT1LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos)     /*!< 0x00000080 */

+#define HRTIM_FLTINR1_FLT1LCK         HRTIM_FLTINR1_FLT1LCK_Msk                /*!< Fault 1 lock */

+

+#define HRTIM_FLTINR1_FLT2E_Pos       (8U)

+#define HRTIM_FLTINR1_FLT2E_Msk       (0x1UL << HRTIM_FLTINR1_FLT2E_Pos)       /*!< 0x00000100 */

+#define HRTIM_FLTINR1_FLT2E           HRTIM_FLTINR1_FLT2E_Msk                  /*!< Fault 2 enable */

+#define HRTIM_FLTINR1_FLT2P_Pos       (9U)

+#define HRTIM_FLTINR1_FLT2P_Msk       (0x1UL << HRTIM_FLTINR1_FLT2P_Pos)       /*!< 0x00000200 */

+#define HRTIM_FLTINR1_FLT2P           HRTIM_FLTINR1_FLT2P_Msk                  /*!< Fault 2 polarity */

+#define HRTIM_FLTINR1_FLT2SRC_Pos     (10U)

+#define HRTIM_FLTINR1_FLT2SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT2SRC_Pos)     /*!< 0x00000400 */

+#define HRTIM_FLTINR1_FLT2SRC         HRTIM_FLTINR1_FLT2SRC_Msk                /*!< Fault 2 source */

+#define HRTIM_FLTINR1_FLT2F_Pos       (11U)

+#define HRTIM_FLTINR1_FLT2F_Msk       (0xFUL << HRTIM_FLTINR1_FLT2F_Pos)       /*!< 0x00007800 */

+#define HRTIM_FLTINR1_FLT2F           HRTIM_FLTINR1_FLT2F_Msk                  /*!< Fault 2 filter */

+#define HRTIM_FLTINR1_FLT2F_0         (0x1UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00000800 */

+#define HRTIM_FLTINR1_FLT2F_1         (0x2UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00001000 */

+#define HRTIM_FLTINR1_FLT2F_2         (0x4UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00002000 */

+#define HRTIM_FLTINR1_FLT2F_3         (0x8UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00004000 */

+#define HRTIM_FLTINR1_FLT2LCK_Pos     (15U)

+#define HRTIM_FLTINR1_FLT2LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos)     /*!< 0x00008000 */

+#define HRTIM_FLTINR1_FLT2LCK         HRTIM_FLTINR1_FLT2LCK_Msk                /*!< Fault 2 lock */

+

+#define HRTIM_FLTINR1_FLT3E_Pos       (16U)

+#define HRTIM_FLTINR1_FLT3E_Msk       (0x1UL << HRTIM_FLTINR1_FLT3E_Pos)       /*!< 0x00010000 */

+#define HRTIM_FLTINR1_FLT3E           HRTIM_FLTINR1_FLT3E_Msk                  /*!< Fault 3 enable */

+#define HRTIM_FLTINR1_FLT3P_Pos       (17U)

+#define HRTIM_FLTINR1_FLT3P_Msk       (0x1UL << HRTIM_FLTINR1_FLT3P_Pos)       /*!< 0x00020000 */

+#define HRTIM_FLTINR1_FLT3P           HRTIM_FLTINR1_FLT3P_Msk                  /*!< Fault 3 polarity */

+#define HRTIM_FLTINR1_FLT3SRC_Pos     (18U)

+#define HRTIM_FLTINR1_FLT3SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT3SRC_Pos)     /*!< 0x00040000 */

+#define HRTIM_FLTINR1_FLT3SRC         HRTIM_FLTINR1_FLT3SRC_Msk                /*!< Fault 3 source */

+#define HRTIM_FLTINR1_FLT3F_Pos       (19U)

+#define HRTIM_FLTINR1_FLT3F_Msk       (0xFUL << HRTIM_FLTINR1_FLT3F_Pos)       /*!< 0x00780000 */

+#define HRTIM_FLTINR1_FLT3F           HRTIM_FLTINR1_FLT3F_Msk                  /*!< Fault 3 filter */

+#define HRTIM_FLTINR1_FLT3F_0         (0x1UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00080000 */

+#define HRTIM_FLTINR1_FLT3F_1         (0x2UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00100000 */

+#define HRTIM_FLTINR1_FLT3F_2         (0x4UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00200000 */

+#define HRTIM_FLTINR1_FLT3F_3         (0x8UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00400000 */

+#define HRTIM_FLTINR1_FLT3LCK_Pos     (23U)

+#define HRTIM_FLTINR1_FLT3LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos)     /*!< 0x00800000 */

+#define HRTIM_FLTINR1_FLT3LCK         HRTIM_FLTINR1_FLT3LCK_Msk                /*!< Fault 3 lock */

+

+#define HRTIM_FLTINR1_FLT4E_Pos       (24U)

+#define HRTIM_FLTINR1_FLT4E_Msk       (0x1UL << HRTIM_FLTINR1_FLT4E_Pos)       /*!< 0x01000000 */

+#define HRTIM_FLTINR1_FLT4E           HRTIM_FLTINR1_FLT4E_Msk                  /*!< Fault 4 enable */

+#define HRTIM_FLTINR1_FLT4P_Pos       (25U)

+#define HRTIM_FLTINR1_FLT4P_Msk       (0x1UL << HRTIM_FLTINR1_FLT4P_Pos)       /*!< 0x02000000 */

+#define HRTIM_FLTINR1_FLT4P           HRTIM_FLTINR1_FLT4P_Msk                  /*!< Fault 4 polarity */

+#define HRTIM_FLTINR1_FLT4SRC_Pos     (26U)

+#define HRTIM_FLTINR1_FLT4SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT4SRC_Pos)     /*!< 0x04000000 */

+#define HRTIM_FLTINR1_FLT4SRC         HRTIM_FLTINR1_FLT4SRC_Msk                /*!< Fault 4 source */

+#define HRTIM_FLTINR1_FLT4F_Pos       (27U)

+#define HRTIM_FLTINR1_FLT4F_Msk       (0xFUL << HRTIM_FLTINR1_FLT4F_Pos)       /*!< 0x78000000 */

+#define HRTIM_FLTINR1_FLT4F           HRTIM_FLTINR1_FLT4F_Msk                  /*!< Fault 4 filter */

+#define HRTIM_FLTINR1_FLT4F_0         (0x1UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x08000000 */

+#define HRTIM_FLTINR1_FLT4F_1         (0x2UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x10000000 */

+#define HRTIM_FLTINR1_FLT4F_2         (0x4UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x20000000 */

+#define HRTIM_FLTINR1_FLT4F_3         (0x8UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x40000000 */

+#define HRTIM_FLTINR1_FLT4LCK_Pos     (31U)

+#define HRTIM_FLTINR1_FLT4LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos)     /*!< 0x80000000 */

+#define HRTIM_FLTINR1_FLT4LCK         HRTIM_FLTINR1_FLT4LCK_Msk                /*!< Fault 4 lock */

+

+/*******************  Bit definition for HRTIM_FLTINR2 register  ***************/

+#define HRTIM_FLTINR2_FLT5E_Pos       (0U)

+#define HRTIM_FLTINR2_FLT5E_Msk       (0x1UL << HRTIM_FLTINR2_FLT5E_Pos)       /*!< 0x00000001 */

+#define HRTIM_FLTINR2_FLT5E           HRTIM_FLTINR2_FLT5E_Msk                  /*!< Fault 5 enable */

+#define HRTIM_FLTINR2_FLT5P_Pos       (1U)

+#define HRTIM_FLTINR2_FLT5P_Msk       (0x1UL << HRTIM_FLTINR2_FLT5P_Pos)       /*!< 0x00000002 */

+#define HRTIM_FLTINR2_FLT5P           HRTIM_FLTINR2_FLT5P_Msk                  /*!< Fault 5 polarity */

+#define HRTIM_FLTINR2_FLT5SRC_Pos     (2U)

+#define HRTIM_FLTINR2_FLT5SRC_Msk     (0x1UL << HRTIM_FLTINR2_FLT5SRC_Pos)     /*!< 0x00000004 */

+#define HRTIM_FLTINR2_FLT5SRC         HRTIM_FLTINR2_FLT5SRC_Msk                /*!< Fault 5 source */

+#define HRTIM_FLTINR2_FLT5F_Pos       (3U)

+#define HRTIM_FLTINR2_FLT5F_Msk       (0xFUL << HRTIM_FLTINR2_FLT5F_Pos)       /*!< 0x00000078 */

+#define HRTIM_FLTINR2_FLT5F           HRTIM_FLTINR2_FLT5F_Msk                  /*!< Fault 5 filter */

+#define HRTIM_FLTINR2_FLT5F_0         (0x1UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000008 */

+#define HRTIM_FLTINR2_FLT5F_1         (0x2UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000010 */

+#define HRTIM_FLTINR2_FLT5F_2         (0x4UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000020 */

+#define HRTIM_FLTINR2_FLT5F_3         (0x8UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000040 */

+#define HRTIM_FLTINR2_FLT5LCK_Pos     (7U)

+#define HRTIM_FLTINR2_FLT5LCK_Msk     (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos)     /*!< 0x00000080 */

+#define HRTIM_FLTINR2_FLT5LCK         HRTIM_FLTINR2_FLT5LCK_Msk                /*!< Fault 5 lock */

+#define HRTIM_FLTINR2_FLTSD_Pos       (24U)

+#define HRTIM_FLTINR2_FLTSD_Msk       (0x3UL << HRTIM_FLTINR2_FLTSD_Pos)       /*!< 0x03000000 */

+#define HRTIM_FLTINR2_FLTSD           HRTIM_FLTINR2_FLTSD_Msk                  /*!< Fault sampling clock division */

+#define HRTIM_FLTINR2_FLTSD_0         (0x1UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x01000000 */

+#define HRTIM_FLTINR2_FLTSD_1         (0x2UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x02000000 */

+

+/*******************  Bit definition for HRTIM_BDMUPR register  ***************/

+#define HRTIM_BDMUPR_MCR_Pos          (0U)

+#define HRTIM_BDMUPR_MCR_Msk          (0x1UL << HRTIM_BDMUPR_MCR_Pos)          /*!< 0x00000001 */

+#define HRTIM_BDMUPR_MCR              HRTIM_BDMUPR_MCR_Msk                     /*!< MCR register update enable */

+#define HRTIM_BDMUPR_MICR_Pos         (1U)

+#define HRTIM_BDMUPR_MICR_Msk         (0x1UL << HRTIM_BDMUPR_MICR_Pos)         /*!< 0x00000002 */

+#define HRTIM_BDMUPR_MICR             HRTIM_BDMUPR_MICR_Msk                    /*!< MICR register update enable */

+#define HRTIM_BDMUPR_MDIER_Pos        (2U)

+#define HRTIM_BDMUPR_MDIER_Msk        (0x1UL << HRTIM_BDMUPR_MDIER_Pos)        /*!< 0x00000004 */

+#define HRTIM_BDMUPR_MDIER            HRTIM_BDMUPR_MDIER_Msk                   /*!< MDIER register update enable */

+#define HRTIM_BDMUPR_MCNT_Pos         (3U)

+#define HRTIM_BDMUPR_MCNT_Msk         (0x1UL << HRTIM_BDMUPR_MCNT_Pos)         /*!< 0x00000008 */

+#define HRTIM_BDMUPR_MCNT             HRTIM_BDMUPR_MCNT_Msk                    /*!< MCNT register update enable */

+#define HRTIM_BDMUPR_MPER_Pos         (4U)

+#define HRTIM_BDMUPR_MPER_Msk         (0x1UL << HRTIM_BDMUPR_MPER_Pos)         /*!< 0x00000010 */

+#define HRTIM_BDMUPR_MPER             HRTIM_BDMUPR_MPER_Msk                    /*!< MPER register update enable */

+#define HRTIM_BDMUPR_MREP_Pos         (5U)

+#define HRTIM_BDMUPR_MREP_Msk         (0x1UL << HRTIM_BDMUPR_MREP_Pos)         /*!< 0x00000020 */

+#define HRTIM_BDMUPR_MREP             HRTIM_BDMUPR_MREP_Msk                    /*!< MREP register update enable */

+#define HRTIM_BDMUPR_MCMP1_Pos        (6U)

+#define HRTIM_BDMUPR_MCMP1_Msk        (0x1UL << HRTIM_BDMUPR_MCMP1_Pos)        /*!< 0x00000040 */

+#define HRTIM_BDMUPR_MCMP1            HRTIM_BDMUPR_MCMP1_Msk                   /*!< MCMP1 register update enable */

+#define HRTIM_BDMUPR_MCMP2_Pos        (7U)

+#define HRTIM_BDMUPR_MCMP2_Msk        (0x1UL << HRTIM_BDMUPR_MCMP2_Pos)        /*!< 0x00000080 */

+#define HRTIM_BDMUPR_MCMP2            HRTIM_BDMUPR_MCMP2_Msk                   /*!< MCMP2 register update enable */

+#define HRTIM_BDMUPR_MCMP3_Pos        (8U)

+#define HRTIM_BDMUPR_MCMP3_Msk        (0x1UL << HRTIM_BDMUPR_MCMP3_Pos)        /*!< 0x00000100 */

+#define HRTIM_BDMUPR_MCMP3            HRTIM_BDMUPR_MCMP3_Msk                   /*!< MCMP3 register update enable */

+#define HRTIM_BDMUPR_MCMP4_Pos        (9U)

+#define HRTIM_BDMUPR_MCMP4_Msk        (0x1UL << HRTIM_BDMUPR_MCMP4_Pos)        /*!< 0x00000200 */

+#define HRTIM_BDMUPR_MCMP4            HRTIM_BDMUPR_MCMP4_Msk                   /*!< MPCMP4 register update enable */

+

+/*******************  Bit definition for HRTIM_BDTUPR register  ***************/

+#define HRTIM_BDTUPR_TIMCR_Pos        (0U)

+#define HRTIM_BDTUPR_TIMCR_Msk        (0x1UL << HRTIM_BDTUPR_TIMCR_Pos)        /*!< 0x00000001 */

+#define HRTIM_BDTUPR_TIMCR            HRTIM_BDTUPR_TIMCR_Msk                   /*!<  TIMCR register update enable */

+#define HRTIM_BDTUPR_TIMICR_Pos       (1U)

+#define HRTIM_BDTUPR_TIMICR_Msk       (0x1UL << HRTIM_BDTUPR_TIMICR_Pos)       /*!< 0x00000002 */

+#define HRTIM_BDTUPR_TIMICR           HRTIM_BDTUPR_TIMICR_Msk                  /*!<  TIMICR register update enable */

+#define HRTIM_BDTUPR_TIMDIER_Pos      (2U)

+#define HRTIM_BDTUPR_TIMDIER_Msk      (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos)      /*!< 0x00000004 */

+#define HRTIM_BDTUPR_TIMDIER          HRTIM_BDTUPR_TIMDIER_Msk                 /*!<  TIMDIER register update enable */

+#define HRTIM_BDTUPR_TIMCNT_Pos       (3U)

+#define HRTIM_BDTUPR_TIMCNT_Msk       (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos)       /*!< 0x00000008 */

+#define HRTIM_BDTUPR_TIMCNT           HRTIM_BDTUPR_TIMCNT_Msk                  /*!<  TIMCNT register update enable */

+#define HRTIM_BDTUPR_TIMPER_Pos       (4U)

+#define HRTIM_BDTUPR_TIMPER_Msk       (0x1UL << HRTIM_BDTUPR_TIMPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_BDTUPR_TIMPER           HRTIM_BDTUPR_TIMPER_Msk                  /*!<  TIMPER register update enable */

+#define HRTIM_BDTUPR_TIMREP_Pos       (5U)

+#define HRTIM_BDTUPR_TIMREP_Msk       (0x1UL << HRTIM_BDTUPR_TIMREP_Pos)       /*!< 0x00000020 */

+#define HRTIM_BDTUPR_TIMREP           HRTIM_BDTUPR_TIMREP_Msk                  /*!<  TIMREP register update enable */

+#define HRTIM_BDTUPR_TIMCMP1_Pos      (6U)

+#define HRTIM_BDTUPR_TIMCMP1_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos)      /*!< 0x00000040 */

+#define HRTIM_BDTUPR_TIMCMP1          HRTIM_BDTUPR_TIMCMP1_Msk                 /*!<  TIMCMP1 register update enable */

+#define HRTIM_BDTUPR_TIMCMP2_Pos      (7U)

+#define HRTIM_BDTUPR_TIMCMP2_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos)      /*!< 0x00000080 */

+#define HRTIM_BDTUPR_TIMCMP2          HRTIM_BDTUPR_TIMCMP2_Msk                 /*!<  TIMCMP2 register update enable */

+#define HRTIM_BDTUPR_TIMCMP3_Pos      (8U)

+#define HRTIM_BDTUPR_TIMCMP3_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos)      /*!< 0x00000100 */

+#define HRTIM_BDTUPR_TIMCMP3          HRTIM_BDTUPR_TIMCMP3_Msk                 /*!<  TIMCMP3 register update enable */

+#define HRTIM_BDTUPR_TIMCMP4_Pos      (9U)

+#define HRTIM_BDTUPR_TIMCMP4_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos)      /*!< 0x00000200 */

+#define HRTIM_BDTUPR_TIMCMP4          HRTIM_BDTUPR_TIMCMP4_Msk                 /*!<  TIMCMP4 register update enable */

+#define HRTIM_BDTUPR_TIMDTR_Pos       (10U)

+#define HRTIM_BDTUPR_TIMDTR_Msk       (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos)       /*!< 0x00000400 */

+#define HRTIM_BDTUPR_TIMDTR           HRTIM_BDTUPR_TIMDTR_Msk                  /*!<  TIMDTR register update enable */

+#define HRTIM_BDTUPR_TIMSET1R_Pos     (11U)

+#define HRTIM_BDTUPR_TIMSET1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos)     /*!< 0x00000800 */

+#define HRTIM_BDTUPR_TIMSET1R         HRTIM_BDTUPR_TIMSET1R_Msk                /*!<  TIMSET1R register update enable */

+#define HRTIM_BDTUPR_TIMRST1R_Pos     (12U)

+#define HRTIM_BDTUPR_TIMRST1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos)     /*!< 0x00001000 */

+#define HRTIM_BDTUPR_TIMRST1R         HRTIM_BDTUPR_TIMRST1R_Msk                /*!<  TIMRST1R register update enable */

+#define HRTIM_BDTUPR_TIMSET2R_Pos     (13U)

+#define HRTIM_BDTUPR_TIMSET2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos)     /*!< 0x00002000 */

+#define HRTIM_BDTUPR_TIMSET2R         HRTIM_BDTUPR_TIMSET2R_Msk                /*!<  TIMSET2R register update enable */

+#define HRTIM_BDTUPR_TIMRST2R_Pos     (14U)

+#define HRTIM_BDTUPR_TIMRST2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos)     /*!< 0x00004000 */

+#define HRTIM_BDTUPR_TIMRST2R         HRTIM_BDTUPR_TIMRST2R_Msk                /*!<  TIMRST2R register update enable */

+#define HRTIM_BDTUPR_TIMEEFR1_Pos     (15U)

+#define HRTIM_BDTUPR_TIMEEFR1_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos)     /*!< 0x00008000 */

+#define HRTIM_BDTUPR_TIMEEFR1         HRTIM_BDTUPR_TIMEEFR1_Msk                /*!<  TIMEEFR1 register update enable */

+#define HRTIM_BDTUPR_TIMEEFR2_Pos     (16U)

+#define HRTIM_BDTUPR_TIMEEFR2_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos)     /*!< 0x00010000 */

+#define HRTIM_BDTUPR_TIMEEFR2         HRTIM_BDTUPR_TIMEEFR2_Msk                /*!<  TIMEEFR2 register update enable */

+#define HRTIM_BDTUPR_TIMRSTR_Pos      (17U)

+#define HRTIM_BDTUPR_TIMRSTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos)      /*!< 0x00020000 */

+#define HRTIM_BDTUPR_TIMRSTR          HRTIM_BDTUPR_TIMRSTR_Msk                 /*!<  TIMRSTR register update enable */

+#define HRTIM_BDTUPR_TIMCHPR_Pos      (18U)

+#define HRTIM_BDTUPR_TIMCHPR_Msk      (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos)      /*!< 0x00040000 */

+#define HRTIM_BDTUPR_TIMCHPR          HRTIM_BDTUPR_TIMCHPR_Msk                 /*!<  TIMCHPR register update enable */

+#define HRTIM_BDTUPR_TIMOUTR_Pos      (19U)

+#define HRTIM_BDTUPR_TIMOUTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos)      /*!< 0x00080000 */

+#define HRTIM_BDTUPR_TIMOUTR          HRTIM_BDTUPR_TIMOUTR_Msk                 /*!<  TIMOUTR register update enable */

+#define HRTIM_BDTUPR_TIMFLTR_Pos      (20U)

+#define HRTIM_BDTUPR_TIMFLTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos)      /*!< 0x00100000 */

+#define HRTIM_BDTUPR_TIMFLTR          HRTIM_BDTUPR_TIMFLTR_Msk                 /*!<  TIMFLTR register update enable */

+

+/*******************  Bit definition for HRTIM_BDMADR register  ***************/

+#define HRTIM_BDMADR_BDMADR_Pos       (0U)

+#define HRTIM_BDMADR_BDMADR_Msk       (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos) /*!< 0xFFFFFFFF */

+#define HRTIM_BDMADR_BDMADR           HRTIM_BDMADR_BDMADR_Msk                  /*!<  Burst DMA Data register */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             RAM ECC monitoring                             */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for RAMECC_IER register  ******************/

+#define RAMECC_IER_GECCDEBWIE_Pos         (3U)

+#define RAMECC_IER_GECCDEBWIE_Msk         (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)  /*!< 0x00000008 */

+#define RAMECC_IER_GECCDEBWIE             RAMECC_IER_GECCDEBWIE_Msk             /*!< Global ECC double error on byte write (BW) interrupt enable */

+#define RAMECC_IER_GECCDEIE_Pos           (2U)

+#define RAMECC_IER_GECCDEIE_Msk           (0x1UL << RAMECC_IER_GECCDEIE_Pos)    /*!< 0x00000004 */

+#define RAMECC_IER_GECCDEIE               RAMECC_IER_GECCDEIE_Msk               /*!< Global ECC double error interrupt enable */

+#define RAMECC_IER_GECCSEIE_Pos           (1U)

+#define RAMECC_IER_GECCSEIE_Msk           (0x1UL << RAMECC_IER_GECCSEIE_Pos)    /*!< 0x00000002 */

+#define RAMECC_IER_GECCSEIE               RAMECC_IER_GECCSEIE_Msk               /*!< Global ECC single error interrupt enable */

+#define RAMECC_IER_GIE_Pos                (0U)

+#define RAMECC_IER_GIE_Msk                (0x1UL << RAMECC_IER_GIE_Pos)         /*!< 0x00000001 */

+#define RAMECC_IER_GIE                    RAMECC_IER_GIE_Msk                    /*!< Global interrupt enable */

+

+/*******************  Bit definition for RAMECC_CR register  ******************/

+#define RAMECC_CR_ECCELEN_Pos             (5U)

+#define RAMECC_CR_ECCELEN_Msk             (0x1UL << RAMECC_CR_ECCELEN_Pos)      /*!< 0x00000020 */

+#define RAMECC_CR_ECCELEN                 RAMECC_CR_ECCELEN_Msk                 /*!< ECC error latching enable */

+#define RAMECC_CR_ECCDEBWIE_Pos           (4U)

+#define RAMECC_CR_ECCDEBWIE_Msk           (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)    /*!< 0x00000010 */

+#define RAMECC_CR_ECCDEBWIE               RAMECC_CR_ECCDEBWIE_Msk               /*!< ECC double error on byte write (BW) interrupt enable */

+#define RAMECC_CR_ECCDEIE_Pos             (3U)

+#define RAMECC_CR_ECCDEIE_Msk             (0x1UL << RAMECC_CR_ECCDEIE_Pos)      /*!< 0x00000008 */

+#define RAMECC_CR_ECCDEIE                 RAMECC_CR_ECCDEIE_Msk                 /*!< ECC double error interrupt enable */

+#define RAMECC_CR_ECCSEIE_Pos             (2U)

+#define RAMECC_CR_ECCSEIE_Msk             (0x1UL << RAMECC_CR_ECCSEIE_Pos)      /*!< 0x00000004 */

+#define RAMECC_CR_ECCSEIE                 RAMECC_CR_ECCSEIE_Msk                 /*!< ECC single error interrupt enable */

+

+/*******************  Bit definition for RAMECC_SR register  ******************/

+#define RAMECC_SR_DEBWDF_Pos             (2U)

+#define RAMECC_SR_DEBWDF_Msk             (0x1UL << RAMECC_SR_DEBWDF_Pos)        /*!< 0x00000004 */

+#define RAMECC_SR_DEBWDF                 RAMECC_SR_DEBWDF_Msk                   /*!< ECC double error on byte write (BW) detected flag */

+#define RAMECC_SR_DEDF_Pos               (1U)

+#define RAMECC_SR_DEDF_Msk               (0x1UL << RAMECC_SR_DEDF_Pos)          /*!< 0x00000002 */

+#define RAMECC_SR_DEDF                   RAMECC_SR_DEDF_Msk                     /*!< ECC double error detected flag */

+#define RAMECC_SR_SEDCF_Pos              (0U)

+#define RAMECC_SR_SEDCF_Msk              (0x1UL << RAMECC_SR_SEDCF_Pos)         /*!< 0x00000001 */

+#define RAMECC_SR_SEDCF                  RAMECC_SR_SEDCF_Msk                    /*!< ECC single error detected and corrected flag */

+

+/******************  Bit definition for RAMECC_FAR register  ******************/

+#define RAMECC_FAR_FADD_Pos              (0U)

+#define RAMECC_FAR_FADD_Msk              (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)  /*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FADD                  RAMECC_FAR_FADD_Msk                    /*!< ECC error failing address */

+

+/******************  Bit definition for RAMECC_FDRL register  *****************/

+#define RAMECC_FAR_FDATAL_Pos            (0U)

+#define RAMECC_FAR_FDATAL_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FDATAL                RAMECC_FAR_FDATAL_Msk                  /*!< ECC error failing address */

+

+/******************  Bit definition for RAMECC_FDRH register  *****************/

+#define RAMECC_FAR_FDATAH_Pos            (0U)

+#define RAMECC_FAR_FDATAH_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FDATAH                RAMECC_FAR_FDATAH_Msk                  /* Failing data high (64-bit memory) */

+

+/*****************  Bit definition for RAMECC_FECR register  ******************/

+#define RAMECC_FECR_FEC_Pos              (0U)

+#define RAMECC_FECR_FEC_Msk              (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)  /*!< 0xFFFFFFFF */

+#define RAMECC_FECR_FEC                  RAMECC_FECR_FEC_Msk                    /*!< Failing error code */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                MDIOS                                        */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for MDIOS_CR register  *******************/

+#define MDIOS_CR_EN_Pos                (0U)

+#define MDIOS_CR_EN_Msk                (0x1UL << MDIOS_CR_EN_Pos)              /*!< 0x00000001 */

+#define MDIOS_CR_EN                    MDIOS_CR_EN_Msk                         /*!<  MDIOS slave peripheral enable */

+#define MDIOS_CR_WRIE_Pos              (1U)

+#define MDIOS_CR_WRIE_Msk              (0x1UL << MDIOS_CR_WRIE_Pos)            /*!< 0x00000002 */

+#define MDIOS_CR_WRIE                  MDIOS_CR_WRIE_Msk                       /*!<  MDIOS slave register write interrupt enable. */

+#define MDIOS_CR_RDIE_Pos              (2U)

+#define MDIOS_CR_RDIE_Msk              (0x1UL << MDIOS_CR_RDIE_Pos)            /*!< 0x00000004 */

+#define MDIOS_CR_RDIE                  MDIOS_CR_RDIE_Msk                       /*!<  MDIOS slave register read interrupt enable. */

+#define MDIOS_CR_EIE_Pos               (3U)

+#define MDIOS_CR_EIE_Msk               (0x1UL << MDIOS_CR_EIE_Pos)             /*!< 0x00000008 */

+#define MDIOS_CR_EIE                   MDIOS_CR_EIE_Msk                        /*!<  MDIOS slave register error interrupt enable. */

+#define MDIOS_CR_DPC_Pos               (7U)

+#define MDIOS_CR_DPC_Msk               (0x1UL << MDIOS_CR_DPC_Pos)             /*!< 0x00000080 */

+#define MDIOS_CR_DPC                   MDIOS_CR_DPC_Msk                        /*!<  MDIOS slave disable preamble check. */

+#define MDIOS_CR_PORT_ADDRESS_Pos      (8U)

+#define MDIOS_CR_PORT_ADDRESS_Msk      (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)   /*!< 0x00001F00 */

+#define MDIOS_CR_PORT_ADDRESS          MDIOS_CR_PORT_ADDRESS_Msk               /*!<  MDIOS slave port address mask. */

+#define MDIOS_CR_PORT_ADDRESS_0        (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000100 */

+#define MDIOS_CR_PORT_ADDRESS_1        (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000200 */

+#define MDIOS_CR_PORT_ADDRESS_2        (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000400 */

+#define MDIOS_CR_PORT_ADDRESS_3        (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000800 */

+#define MDIOS_CR_PORT_ADDRESS_4        (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001000 */

+

+/********************  Bit definition for MDIOS_SR register  *******************/

+#define MDIOS_SR_PERF_Pos              (0U)

+#define MDIOS_SR_PERF_Msk              (0x1UL << MDIOS_SR_PERF_Pos)            /*!< 0x00000001 */

+#define MDIOS_SR_PERF                  MDIOS_SR_PERF_Msk                       /*!<  MDIOS slave turnaround error flag*/

+#define MDIOS_SR_SERF_Pos              (1U)

+#define MDIOS_SR_SERF_Msk              (0x1UL << MDIOS_SR_SERF_Pos)            /*!< 0x00000002 */

+#define MDIOS_SR_SERF                  MDIOS_SR_SERF_Msk                       /*!<  MDIOS slave start error flag */

+#define MDIOS_SR_TERF_Pos              (2U)

+#define MDIOS_SR_TERF_Msk              (0x1UL << MDIOS_SR_TERF_Pos)            /*!< 0x00000004 */

+#define MDIOS_SR_TERF                  MDIOS_SR_TERF_Msk                       /*!<  MDIOS slave preamble error flag */

+

+/********************  Bit definition for MDIOS_CLRFR register  *******************/

+#define MDIOS_SR_CPERF_Pos             (0U)

+#define MDIOS_SR_CPERF_Msk             (0x1UL << MDIOS_SR_CPERF_Pos)           /*!< 0x00000001 */

+#define MDIOS_SR_CPERF                 MDIOS_SR_CPERF_Msk                      /*!<  MDIOS slave Clear the turnaround error flag */

+#define MDIOS_SR_CSERF_Pos             (1U)

+#define MDIOS_SR_CSERF_Msk             (0x1UL << MDIOS_SR_CSERF_Pos)           /*!< 0x00000002 */

+#define MDIOS_SR_CSERF                 MDIOS_SR_CSERF_Msk                      /*!<  MDIOS slave Clear the start error flag */

+#define MDIOS_SR_CTERF_Pos             (2U)

+#define MDIOS_SR_CTERF_Msk             (0x1UL << MDIOS_SR_CTERF_Pos)           /*!< 0x00000004 */

+#define MDIOS_SR_CTERF                 MDIOS_SR_CTERF_Msk                      /*!<  MDIOS slave Clear the preamble error flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                       USB_OTG                              */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/

+#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)

+#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */

+#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */

+#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)

+#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */

+#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */

+#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)

+#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */

+#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */

+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)

+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */

+#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */

+#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)

+#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */

+#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */

+#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)

+#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */

+#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */

+#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)

+#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */

+#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */

+#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)

+#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */

+#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */

+#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)

+#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */

+#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */

+#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)

+#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */

+#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */

+#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)

+#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */

+#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */

+#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)

+#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */

+#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */

+#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)

+#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */

+#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */

+#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)

+#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */

+#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */

+#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)

+#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */

+#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */

+#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)

+#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */

+#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */

+#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)

+#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */

+#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */

+#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)

+#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */

+#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */

+

+/********************  Bit definition forUSB_OTG_HCFG register  ********************/

+

+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)

+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */

+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */

+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)

+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */

+

+/********************  Bit definition forUSB_OTG_DCFG register  ********************/

+

+#define USB_OTG_DCFG_DSPD_Pos                    (0U)

+#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */

+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */

+#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */

+#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)

+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */

+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */

+

+#define USB_OTG_DCFG_DAD_Pos                     (4U)

+#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */

+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */

+#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */

+#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */

+#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */

+#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */

+#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */

+#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */

+#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */

+

+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)

+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */

+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */

+#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */

+#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */

+

+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)

+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */

+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */

+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */

+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */

+

+/********************  Bit definition forUSB_OTG_PCGCR register  ********************/

+#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)

+#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */

+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */

+#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)

+#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */

+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */

+#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)

+#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */

+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */

+

+/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/

+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)

+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */

+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */

+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)

+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */

+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */

+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)

+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */

+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */

+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)

+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */

+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */

+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)

+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */

+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */

+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)

+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */

+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */

+

+/********************  Bit definition forUSB_OTG_DCTL register  ********************/

+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)

+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */

+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */

+#define USB_OTG_DCTL_SDIS_Pos                    (1U)

+#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */

+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */

+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)

+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */

+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */

+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)

+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */

+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */

+

+#define USB_OTG_DCTL_TCTL_Pos                    (4U)

+#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */

+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */

+#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */

+#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */

+#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */

+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)

+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */

+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */

+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)

+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */

+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */

+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)

+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */

+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */

+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)

+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */

+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */

+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)

+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */

+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */

+

+/********************  Bit definition forUSB_OTG_HFIR register  ********************/

+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)

+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */

+

+/********************  Bit definition forUSB_OTG_HFNUM register  ********************/

+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)

+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */

+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)

+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */

+

+/********************  Bit definition forUSB_OTG_DSTS register  ********************/

+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)

+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */

+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */

+

+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)

+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */

+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */

+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */

+#define USB_OTG_DSTS_EERR_Pos                    (3U)

+#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */

+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */

+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)

+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */

+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */

+

+/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/

+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)

+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */

+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */

+

+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)

+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */

+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */

+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */

+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */

+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */

+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */

+#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */

+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)

+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */

+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */

+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)

+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */

+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */

+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)

+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */

+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */

+

+/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/

+

+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)

+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */

+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */

+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */

+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */

+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */

+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)

+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */

+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */

+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)

+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */

+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */

+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)

+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */

+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */

+

+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)

+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */

+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */

+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */

+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */

+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */

+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */

+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)

+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */

+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */

+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)

+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */

+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */

+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)

+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */

+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */

+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)

+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */

+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */

+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)

+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */

+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */

+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)

+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */

+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */

+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)

+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */

+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */

+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)

+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */

+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */

+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)

+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */

+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */

+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)

+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */

+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */

+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)

+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */

+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */

+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)

+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */

+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */

+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)

+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */

+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */

+

+/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/

+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)

+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */

+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */

+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)

+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */

+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */

+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)

+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */

+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */

+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)

+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */

+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */

+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)

+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */

+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */

+

+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)

+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */

+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */

+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */

+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */

+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */

+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */

+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */

+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)

+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */

+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */

+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)

+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */

+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */

+

+/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/

+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)

+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */

+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)

+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */

+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)

+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */

+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)

+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */

+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)

+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */

+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)

+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */

+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)

+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */

+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)

+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */

+

+/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/

+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)

+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */

+

+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)

+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */

+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */

+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */

+

+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)

+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */

+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */

+

+/********************  Bit definition forUSB_OTG_HAINT register  ********************/

+#define USB_OTG_HAINT_HAINT_Pos                  (0U)

+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */

+

+/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/

+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)

+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */

+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)

+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */

+#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)

+#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */

+#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask               */

+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)

+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */

+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)

+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */

+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)

+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */

+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)

+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */

+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)

+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */

+#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)

+#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */

+#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)

+#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask               */

+#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)

+#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask               */

+#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)

+#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                */

+

+/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/

+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)

+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */

+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */

+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)

+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */

+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */

+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)

+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */

+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */

+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)

+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */

+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */

+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)

+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */

+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */

+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)

+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */

+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */

+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)

+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */

+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */

+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)

+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */

+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */

+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)

+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */

+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */

+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)

+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */

+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */

+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)

+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */

+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */

+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)

+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */

+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */

+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)

+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */

+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */

+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)

+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */

+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */

+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)

+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */

+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */

+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)

+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */

+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */

+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)

+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */

+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */

+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)

+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */

+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */

+#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)

+#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */

+#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */

+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)

+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */

+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */

+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)

+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */

+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */

+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)

+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */

+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */

+#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)

+#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */

+#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */

+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)

+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */

+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */

+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)

+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */

+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */

+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)

+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */

+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */

+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)

+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */

+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */

+

+/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/

+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)

+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */

+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */

+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)

+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */

+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */

+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)

+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */

+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */

+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)

+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */

+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */

+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)

+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */

+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */

+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)

+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */

+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */

+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)

+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */

+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */

+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)

+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */

+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */

+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)

+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */

+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */

+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)

+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */

+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */

+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)

+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */

+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */

+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)

+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */

+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */

+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)

+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */

+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */

+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)

+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */

+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */

+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)

+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */

+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */

+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)

+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */

+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */

+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)

+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */

+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */

+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)

+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */

+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */

+#define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)

+#define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */

+#define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */

+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)

+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */

+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */

+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)

+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */

+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */

+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)

+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */

+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */

+#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)

+#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */

+#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */

+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)

+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */

+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */

+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)

+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */

+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */

+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)

+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */

+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */

+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)

+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */

+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */

+

+/********************  Bit definition forUSB_OTG_DAINT register  ********************/

+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)

+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */

+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)

+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */

+

+/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/

+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)

+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */

+

+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/

+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)

+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */

+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */

+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)

+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */

+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */

+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)

+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */

+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */

+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)

+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */

+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */

+

+/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/

+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)

+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */

+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)

+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */

+

+/********************  Bit definition for OTG register  ********************/

+

+#define USB_OTG_CHNUM_Pos                        (0U)

+#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)  /*!< 0x0000000F */

+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */

+#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */

+#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */

+#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */

+#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */

+#define USB_OTG_BCNT_Pos                         (4U)

+#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */

+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */

+

+#define USB_OTG_DPID_Pos                         (15U)

+#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)   /*!< 0x00018000 */

+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */

+#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */

+#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */

+

+#define USB_OTG_PKTSTS_Pos                       (17U)

+#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */

+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */

+#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */

+#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */

+#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */

+#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */

+

+#define USB_OTG_EPNUM_Pos                        (0U)

+#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)  /*!< 0x0000000F */

+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */

+#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */

+#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */

+#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */

+#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */

+

+#define USB_OTG_FRMNUM_Pos                       (21U)

+#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */

+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */

+#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */

+#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */

+#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */

+#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */

+

+/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/

+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)

+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/

+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)

+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */

+

+/********************  Bit definition for OTG register  ********************/

+#define USB_OTG_NPTXFSA_Pos                      (0U)

+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */

+#define USB_OTG_NPTXFD_Pos                       (16U)

+#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */

+#define USB_OTG_TX0FSA_Pos                       (0U)

+#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */

+#define USB_OTG_TX0FD_Pos                        (16U)

+#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */

+

+/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/

+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)

+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */

+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */

+

+/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/

+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)

+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */

+

+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)

+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */

+

+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)

+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/

+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)

+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */

+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */

+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)

+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */

+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */

+

+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)

+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */

+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */

+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */

+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)

+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */

+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */

+

+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)

+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */

+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */

+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)

+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */

+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */

+

+/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */

+

+/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/

+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)

+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */

+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */

+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)

+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */

+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */

+

+/********************  Bit definition forUSB_OTG_GCCFG register  ********************/

+#define USB_OTG_GCCFG_DCDET_Pos                  (0U)

+#define USB_OTG_GCCFG_DCDET_Msk                  (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */

+#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */

+#define USB_OTG_GCCFG_PDET_Pos                   (1U)

+#define USB_OTG_GCCFG_PDET_Msk                   (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */

+#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */

+#define USB_OTG_GCCFG_SDET_Pos                   (2U)

+#define USB_OTG_GCCFG_SDET_Msk                   (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */

+#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */

+#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)

+#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */

+#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */

+#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)

+#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */

+#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */

+#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)

+#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */

+#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */

+#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)

+#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */

+#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/

+#define USB_OTG_GCCFG_PDEN_Pos                   (19U)

+#define USB_OTG_GCCFG_PDEN_Msk                   (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */

+#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/

+#define USB_OTG_GCCFG_SDEN_Pos                   (20U)

+#define USB_OTG_GCCFG_SDEN_Msk                   (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */

+#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */

+#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)

+#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */

+#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */

+

+/********************  Bit definition forUSB_OTG_GPWRDN) register  ********************/

+#define USB_OTG_GPWRDN_ADPMEN_Pos                (0U)

+#define USB_OTG_GPWRDN_ADPMEN_Msk                (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */

+#define USB_OTG_GPWRDN_ADPMEN                    USB_OTG_GPWRDN_ADPMEN_Msk     /*!< ADP module enable */

+#define USB_OTG_GPWRDN_ADPIF_Pos                 (23U)

+#define USB_OTG_GPWRDN_ADPIF_Msk                 (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */

+#define USB_OTG_GPWRDN_ADPIF                     USB_OTG_GPWRDN_ADPIF_Msk      /*!< ADP Interrupt flag */

+

+/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/

+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)

+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */

+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)

+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */

+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */

+

+/********************  Bit definition forUSB_OTG_CID register  ********************/

+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)

+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */

+

+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/

+#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)

+#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */

+#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */

+#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)

+#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */

+#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */

+#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)

+#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */

+#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */

+#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)

+#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */

+#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */

+#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)

+#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */

+#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */

+#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)

+#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */

+#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */

+#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)

+#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */

+#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */

+#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)

+#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */

+#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */

+#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)

+#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */

+#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */

+#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)

+#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */

+#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */

+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)

+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */

+#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */

+#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)

+#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */

+#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */

+#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)

+#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */

+#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */

+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)

+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */

+#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */

+#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)

+#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */

+#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */

+

+/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/

+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)

+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */

+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)

+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */

+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)

+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */

+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)

+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */

+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)

+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */

+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)

+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */

+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)

+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */

+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)

+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */

+

+/********************  Bit definition forUSB_OTG_HPRT register  ********************/

+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)

+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */

+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */

+#define USB_OTG_HPRT_PCDET_Pos                   (1U)

+#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */

+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */

+#define USB_OTG_HPRT_PENA_Pos                    (2U)

+#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */

+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */

+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)

+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */

+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */

+#define USB_OTG_HPRT_POCA_Pos                    (4U)

+#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */

+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */

+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)

+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */

+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */

+#define USB_OTG_HPRT_PRES_Pos                    (6U)

+#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */

+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume   */

+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)

+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */

+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend  */

+#define USB_OTG_HPRT_PRST_Pos                    (8U)

+#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */

+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset    */

+

+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)

+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */

+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */

+#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */

+#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */

+#define USB_OTG_HPRT_PPWR_Pos                    (12U)

+#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */

+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */

+

+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)

+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */

+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */

+#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */

+#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */

+#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */

+#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */

+

+#define USB_OTG_HPRT_PSPD_Pos                    (17U)

+#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */

+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */

+#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */

+#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */

+

+/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/

+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)

+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)

+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)

+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */

+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)

+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */

+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)

+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */

+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)

+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */

+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)

+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)

+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)

+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)

+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */

+

+/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/

+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)

+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */

+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)

+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/

+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)

+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */

+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)

+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */

+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */

+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)

+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */

+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */

+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)

+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */

+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */

+

+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)

+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */

+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */

+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)

+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */

+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */

+

+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)

+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */

+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */

+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */

+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */

+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */

+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */

+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)

+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */

+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */

+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)

+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */

+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */

+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)

+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */

+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)

+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */

+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)

+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */

+

+/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/

+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)

+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */

+

+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)

+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */

+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */

+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */

+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */

+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */

+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */

+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)

+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */

+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */

+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)

+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */

+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */

+

+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)

+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */

+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */

+

+#define USB_OTG_HCCHAR_MC_Pos                    (20U)

+#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */

+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */

+#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */

+#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */

+

+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)

+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */

+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */

+#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */

+#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */

+#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */

+#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */

+#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */

+#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */

+#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */

+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)

+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */

+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)

+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */

+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)

+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */

+

+/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/

+

+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)

+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */

+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */

+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */

+

+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)

+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */

+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */

+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */

+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */

+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */

+

+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)

+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */

+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */

+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */

+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */

+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)

+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */

+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */

+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)

+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */

+

+/********************  Bit definition forUSB_OTG_HCINT register  ********************/

+#define USB_OTG_HCINT_XFRC_Pos                   (0U)

+#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */

+#define USB_OTG_HCINT_CHH_Pos                    (1U)

+#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */

+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)

+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */

+#define USB_OTG_HCINT_STALL_Pos                  (3U)

+#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */

+#define USB_OTG_HCINT_NAK_Pos                    (4U)

+#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */

+#define USB_OTG_HCINT_ACK_Pos                    (5U)

+#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */

+#define USB_OTG_HCINT_NYET_Pos                   (6U)

+#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */

+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */

+#define USB_OTG_HCINT_TXERR_Pos                  (7U)

+#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */

+#define USB_OTG_HCINT_BBERR_Pos                  (8U)

+#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */

+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)

+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */

+#define USB_OTG_HCINT_DTERR_Pos                  (10U)

+#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */

+

+/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/

+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)

+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */

+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)

+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */

+#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)

+#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */

+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)

+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */

+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)

+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */

+#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)

+#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */

+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)

+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */

+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)

+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */

+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */

+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)

+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */

+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)

+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */

+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)

+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */

+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */

+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)

+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */

+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */

+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)

+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */

+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */

+

+/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/

+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)

+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */

+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)

+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */

+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)

+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */

+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)

+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */

+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)

+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */

+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)

+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */

+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)

+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */

+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */

+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)

+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */

+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)

+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */

+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)

+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */

+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)

+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */

+

+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/

+

+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)

+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */

+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)

+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */

+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)

+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */

+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */

+/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/

+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)

+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */

+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)

+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */

+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)

+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */

+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)

+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */

+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */

+#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */

+#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/

+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)

+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */

+

+/********************  Bit definition forUSB_OTG_HCDMA register  ********************/

+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)

+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */

+

+/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/

+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)

+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */

+

+/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/

+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)

+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */

+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)

+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/

+

+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)

+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */

+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)

+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */

+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */

+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)

+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */

+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */

+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)

+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */

+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)

+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */

+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */

+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)

+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */

+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */

+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)

+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */

+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */

+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)

+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */

+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */

+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)

+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */

+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */

+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)

+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */

+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)

+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */

+

+/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/

+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)

+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */

+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)

+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */

+#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)

+#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */

+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)

+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */

+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)

+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */

+#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)

+#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< OUT Status Phase Received interrupt */

+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)

+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */

+#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)

+#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */

+#define USB_OTG_DOEPINT_BERR_Pos                 (12U)

+#define USB_OTG_DOEPINT_BERR_Msk                 (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPINT_BERR                      USB_OTG_DOEPINT_BERR_Msk   /*!< Babble error interrupt */

+#define USB_OTG_DOEPINT_NAK_Pos                  (13U)

+#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */

+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)

+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */

+#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)

+#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */

+#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */

+

+/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/

+

+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)

+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */

+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)

+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */

+

+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)

+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */

+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */

+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */

+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition for PCGCCTL register  ********************/

+#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)

+#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */

+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */

+#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)

+#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */

+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */

+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)

+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */

+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/** @addtogroup Exported_macros

+  * @{

+  */

+

+/******************************* ADC Instances ********************************/

+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \

+                                       ((INSTANCE) == ADC2) || \

+                                       ((INSTANCE) == ADC3))

+

+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)

+

+#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) ||\

+                                          ((INSTANCE) == ADC3_COMMON))

+

+/******************************** COMP Instances ******************************/

+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \

+                                       ((INSTANCE) == COMP2))

+

+#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)

+/******************** COMP Instances with window mode capability **************/

+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)

+

+

+/******************************* CRC Instances ********************************/

+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

+

+/******************************* DAC Instances ********************************/

+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)

+/******************************* DCMI Instances *******************************/

+#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)

+

+/******************************* DELAYBLOCK Instances *******************************/

+#define IS_DLYB_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DLYB_SDMMC1) || \

+                                         ((INSTANCE) == DLYB_SDMMC2) || \

+                                         ((INSTANCE) == DLYB_QUADSPI))

+/****************************** DFSDM Instances *******************************/

+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \

+                                               ((INSTANCE) == DFSDM1_Filter1) || \

+                                               ((INSTANCE) == DFSDM1_Filter2) || \

+                                               ((INSTANCE) == DFSDM1_Filter3))

+

+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \

+                                                 ((INSTANCE) == DFSDM1_Channel1) || \

+                                                 ((INSTANCE) == DFSDM1_Channel2) || \

+                                                 ((INSTANCE) == DFSDM1_Channel3) || \

+                                                 ((INSTANCE) == DFSDM1_Channel4) || \

+                                                 ((INSTANCE) == DFSDM1_Channel5) || \

+                                                 ((INSTANCE) == DFSDM1_Channel6) || \

+                                                 ((INSTANCE) == DFSDM1_Channel7))

+/****************************** RAMECC Instances ******************************/

+#define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC1_Monitor1)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor2)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor3)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor4)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor5)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor1)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor2)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor3)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor4)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor5)   || \

+                                                  ((INSTANCE) == RAMECC3_Monitor1)   || \

+                                                  ((INSTANCE) == RAMECC3_Monitor2))

+

+/******************************** DMA Instances *******************************/

+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \

+                                       ((INSTANCE) == DMA1_Stream1)   || \

+                                       ((INSTANCE) == DMA1_Stream2)   || \

+                                       ((INSTANCE) == DMA1_Stream3)   || \

+                                       ((INSTANCE) == DMA1_Stream4)   || \

+                                       ((INSTANCE) == DMA1_Stream5)   || \

+                                       ((INSTANCE) == DMA1_Stream6)   || \

+                                       ((INSTANCE) == DMA1_Stream7)   || \

+                                       ((INSTANCE) == DMA2_Stream0)   || \

+                                       ((INSTANCE) == DMA2_Stream1)   || \

+                                       ((INSTANCE) == DMA2_Stream2)   || \

+                                       ((INSTANCE) == DMA2_Stream3)   || \

+                                       ((INSTANCE) == DMA2_Stream4)   || \

+                                       ((INSTANCE) == DMA2_Stream5)   || \

+                                       ((INSTANCE) == DMA2_Stream6)   || \

+                                       ((INSTANCE) == DMA2_Stream7)   || \

+                                       ((INSTANCE) == BDMA_Channel0) || \

+                                       ((INSTANCE) == BDMA_Channel1) || \

+                                       ((INSTANCE) == BDMA_Channel2) || \

+                                       ((INSTANCE) == BDMA_Channel3) || \

+                                       ((INSTANCE) == BDMA_Channel4) || \

+                                       ((INSTANCE) == BDMA_Channel5) || \

+                                       ((INSTANCE) == BDMA_Channel6) || \

+                                       ((INSTANCE) == BDMA_Channel7))

+

+/****************************** BDMA CHANNEL Instances ***************************/

+#define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \

+                                            ((INSTANCE) == BDMA_Channel1) || \

+                                            ((INSTANCE) == BDMA_Channel2) || \

+                                            ((INSTANCE) == BDMA_Channel3) || \

+                                            ((INSTANCE) == BDMA_Channel4) || \

+                                            ((INSTANCE) == BDMA_Channel5) || \

+                                            ((INSTANCE) == BDMA_Channel6) || \

+                                            ((INSTANCE) == BDMA_Channel7))

+

+/****************************** DMA DMAMUX ALL Instances ***************************/

+#define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)    || \

+                                               ((INSTANCE) == DMA1_Stream1)    || \

+                                               ((INSTANCE) == DMA1_Stream2)    || \

+                                               ((INSTANCE) == DMA1_Stream3)    || \

+                                               ((INSTANCE) == DMA1_Stream4)    || \

+                                               ((INSTANCE) == DMA1_Stream5)    || \

+                                               ((INSTANCE) == DMA1_Stream6)    || \

+                                               ((INSTANCE) == DMA1_Stream7)    || \

+                                               ((INSTANCE) == DMA2_Stream0)    || \

+                                               ((INSTANCE) == DMA2_Stream1)    || \

+                                               ((INSTANCE) == DMA2_Stream2)    || \

+                                               ((INSTANCE) == DMA2_Stream3)    || \

+                                               ((INSTANCE) == DMA2_Stream4)    || \

+                                               ((INSTANCE) == DMA2_Stream5)    || \

+                                               ((INSTANCE) == DMA2_Stream6)    || \

+                                               ((INSTANCE) == DMA2_Stream7)    || \

+                                               ((INSTANCE) == BDMA_Channel0)   || \

+                                               ((INSTANCE) == BDMA_Channel1)   || \

+                                               ((INSTANCE) == BDMA_Channel2)   || \

+                                               ((INSTANCE) == BDMA_Channel3)   || \

+                                               ((INSTANCE) == BDMA_Channel4)   || \

+                                               ((INSTANCE) == BDMA_Channel5)   || \

+                                               ((INSTANCE) == BDMA_Channel6)   || \

+                                               ((INSTANCE) == BDMA_Channel7))

+

+/****************************** BDMA DMAMUX Instances ***************************/

+#define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == BDMA_Channel0) || \

+                                                    ((INSTANCE) == BDMA_Channel1) || \

+                                                    ((INSTANCE) == BDMA_Channel2) || \

+                                                    ((INSTANCE) == BDMA_Channel3) || \

+                                                    ((INSTANCE) == BDMA_Channel4) || \

+                                                    ((INSTANCE) == BDMA_Channel5) || \

+                                                    ((INSTANCE) == BDMA_Channel6) || \

+                                                    ((INSTANCE) == BDMA_Channel7))

+

+/****************************** DMA STREAM Instances ***************************/

+#define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \

+                                          ((INSTANCE) == DMA1_Stream1)   || \

+                                          ((INSTANCE) == DMA1_Stream2)   || \

+                                          ((INSTANCE) == DMA1_Stream3)   || \

+                                          ((INSTANCE) == DMA1_Stream4)   || \

+                                          ((INSTANCE) == DMA1_Stream5)   || \

+                                          ((INSTANCE) == DMA1_Stream6)   || \

+                                          ((INSTANCE) == DMA1_Stream7)   || \

+                                          ((INSTANCE) == DMA2_Stream0)   || \

+                                          ((INSTANCE) == DMA2_Stream1)   || \

+                                          ((INSTANCE) == DMA2_Stream2)   || \

+                                          ((INSTANCE) == DMA2_Stream3)   || \

+                                          ((INSTANCE) == DMA2_Stream4)   || \

+                                          ((INSTANCE) == DMA2_Stream5)   || \

+                                          ((INSTANCE) == DMA2_Stream6)   || \

+                                          ((INSTANCE) == DMA2_Stream7))

+

+/****************************** DMA DMAMUX Instances ***************************/

+#define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)   || \

+                                                  ((INSTANCE) == DMA1_Stream1)   || \

+                                                  ((INSTANCE) == DMA1_Stream2)   || \

+                                                  ((INSTANCE) == DMA1_Stream3)   || \

+                                                  ((INSTANCE) == DMA1_Stream4)   || \

+                                                  ((INSTANCE) == DMA1_Stream5)   || \

+                                                  ((INSTANCE) == DMA1_Stream6)   || \

+                                                  ((INSTANCE) == DMA1_Stream7)   || \

+                                                  ((INSTANCE) == DMA2_Stream0)   || \

+                                                  ((INSTANCE) == DMA2_Stream1)   || \

+                                                  ((INSTANCE) == DMA2_Stream2)   || \

+                                                  ((INSTANCE) == DMA2_Stream3)   || \

+                                                  ((INSTANCE) == DMA2_Stream4)   || \

+                                                  ((INSTANCE) == DMA2_Stream5)   || \

+                                                  ((INSTANCE) == DMA2_Stream6)   || \

+                                                  ((INSTANCE) == DMA2_Stream7))

+

+/******************************** DMA Request Generator Instances **************/

+#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator1) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator2) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator3) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator4) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator5) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator6) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator7) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator0) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator1) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator2) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator3) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator4) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator5) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator6) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator7))

+

+/******************************* DMA2D Instances *******************************/

+#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)

+

+/******************************** MDMA Request Generator Instances **************/

+#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0)  || \

+                                               ((INSTANCE) == MDMA_Channel1)  || \

+                                               ((INSTANCE) == MDMA_Channel2)  || \

+                                               ((INSTANCE) == MDMA_Channel3)  || \

+                                               ((INSTANCE) == MDMA_Channel4)  || \

+                                               ((INSTANCE) == MDMA_Channel5)  || \

+                                               ((INSTANCE) == MDMA_Channel6)  || \

+                                               ((INSTANCE) == MDMA_Channel7)  || \

+                                               ((INSTANCE) == MDMA_Channel8)  || \

+                                               ((INSTANCE) == MDMA_Channel9)  || \

+                                               ((INSTANCE) == MDMA_Channel10) || \

+                                               ((INSTANCE) == MDMA_Channel11) || \

+                                               ((INSTANCE) == MDMA_Channel12) || \

+                                               ((INSTANCE) == MDMA_Channel13) || \

+                                               ((INSTANCE) == MDMA_Channel14) || \

+                                               ((INSTANCE) == MDMA_Channel15))

+

+/******************************* QUADSPI Instances *******************************/

+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)

+

+/******************************* FDCAN Instances ******************************/

+#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \

+                                             ((__INSTANCE__) == FDCAN2))

+

+#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)

+

+/******************************* GPIO Instances *******************************/

+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \

+                                        ((INSTANCE) == GPIOB) || \

+                                        ((INSTANCE) == GPIOC) || \

+                                        ((INSTANCE) == GPIOD) || \

+                                        ((INSTANCE) == GPIOE) || \

+                                        ((INSTANCE) == GPIOF) || \

+                                        ((INSTANCE) == GPIOG) || \

+                                        ((INSTANCE) == GPIOH) || \

+                                        ((INSTANCE) == GPIOI) || \

+                                        ((INSTANCE) == GPIOJ) || \

+                                        ((INSTANCE) == GPIOK))

+

+/******************************* GPIO AF Instances ****************************/

+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)

+

+/**************************** GPIO Lock Instances *****************************/

+/* On H7, all GPIO Bank support the Lock mechanism */

+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)

+

+/******************************** HSEM Instances *******************************/

+#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)

+#define HSEM_CPU1_COREID         (0x00000003U) /* Semaphore Core CM7 ID */

+#define HSEM_CR_COREID_CPU1      (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)

+#define HSEM_CR_COREID_CURRENT   (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)

+

+#define HSEM_SEMID_MIN     (0U)       /* HSEM ID Min*/

+#define HSEM_SEMID_MAX     (31U)      /* HSEM ID Max */

+

+#define HSEM_PROCESSID_MIN (0U)       /* HSEM Process ID Min */

+#define HSEM_PROCESSID_MAX (255U)     /* HSEM Process ID Max */

+

+#define HSEM_CLEAR_KEY_MIN (0U)       /* HSEM clear Key Min value */

+#define HSEM_CLEAR_KEY_MAX (0xFFFFU)  /* HSEM clear Key Max value */

+

+/******************************** I2C Instances *******************************/

+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

+                                       ((INSTANCE) == I2C2) || \

+                                       ((INSTANCE) == I2C3) || \

+                                       ((INSTANCE) == I2C4))

+/************** I2C Instances : wakeup capability from stop modes *************/

+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)

+

+/****************************** SMBUS Instances *******************************/

+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

+                                         ((INSTANCE) == I2C2) || \

+                                         ((INSTANCE) == I2C3) || \

+                                         ((INSTANCE) == I2C4))

+/******************************** I2S Instances *******************************/

+#define IS_I2S_ALL_INSTANCE(INSTANCE)   (((INSTANCE) == SPI1) || \

+                                         ((INSTANCE) == SPI2) || \

+                                         ((INSTANCE) == SPI3))

+

+/****************************** LTDC Instances ********************************/

+#define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)

+

+/******************************* RNG Instances ********************************/

+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)

+

+/****************************** RTC Instances *********************************/

+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)

+

+/****************************** SDMMC Instances *********************************/

+#define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \

+                                           ((_INSTANCE_) == SDMMC2))

+

+/******************************** SMBUS Instances *****************************/

+#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)

+

+/******************************** SPI Instances *******************************/

+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \

+                                       ((INSTANCE) == SPI2) || \

+                                       ((INSTANCE) == SPI3) || \

+                                       ((INSTANCE) == SPI4) || \

+                                       ((INSTANCE) == SPI5) || \

+                                       ((INSTANCE) == SPI6))

+

+#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \

+                                           ((INSTANCE) == SPI2) || \

+                                           ((INSTANCE) == SPI3))

+

+/******************************** SWPMI Instances *****************************/

+#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)

+

+/****************** LPTIM Instances : All supported instances *****************/

+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \

+                                         ((INSTANCE) == LPTIM2) || \

+                                         ((INSTANCE) == LPTIM3) || \

+                                         ((INSTANCE) == LPTIM4) || \

+                                         ((INSTANCE) == LPTIM5))

+

+/****************** LPTIM Instances : supporting encoder interface **************/

+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \

+                                                           ((INSTANCE) == LPTIM2))

+

+/****************** TIM Instances : All supported instances *******************/

+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM6)   || \

+                                         ((INSTANCE) == TIM7)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM13)  || \

+                                         ((INSTANCE) == TIM14)  || \

+                                         ((INSTANCE) == TIM15)  || \

+                                         ((INSTANCE) == TIM16)  || \

+                                         ((INSTANCE) == TIM17))

+

+/************* TIM Instances : at least 1 capture/compare channel *************/

+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM13)  || \

+                                         ((INSTANCE) == TIM14)  || \

+                                         ((INSTANCE) == TIM15)  || \

+                                         ((INSTANCE) == TIM16)  || \

+                                         ((INSTANCE) == TIM17))

+

+/************ TIM Instances : at least 2 capture/compare channels *************/

+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM15))

+

+/************ TIM Instances : at least 3 capture/compare channels *************/

+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8))

+

+/************ TIM Instances : at least 4 capture/compare channels *************/

+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8))

+

+/************ TIM Instances : at least 5 capture/compare channels *************/

+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM8))

+/************ TIM Instances : at least 6 capture/compare channels *************/

+#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM8))

+

+/******************** TIM Instances : Advanced-control timers *****************/

+#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \

+                                                ((__INSTANCE__) == TIM8))

+

+/******************** TIM Instances : Advanced-control timers *****************/

+

+/******************* TIM Instances : Timer input XOR function *****************/

+#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : DMA requests generation (UDE) *************/

+#define IS_TIM_DMA_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM6)   || \

+                                           ((INSTANCE) == TIM7)   || \

+                                           ((INSTANCE) == TIM8)   || \

+                                           ((INSTANCE) == TIM15)  || \

+                                           ((INSTANCE) == TIM16)  || \

+                                           ((INSTANCE) == TIM17))

+

+/************ TIM Instances : DMA requests generation (CCxDE) *****************/

+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15)  || \

+                                            ((INSTANCE) == TIM16)  || \

+                                            ((INSTANCE) == TIM17))

+

+/************ TIM Instances : DMA requests generation (COMDE) *****************/

+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15))

+

+/******************** TIM Instances : DMA burst feature ***********************/

+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8))

+

+/*************** TIM Instances : external trigger reamp input available *******/

+#define IS_TIM_ETR_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : remapping capability **********************/

+#define IS_TIM_REMAP_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \

+                                          ((INSTANCE) == TIM2)  || \

+                                          ((INSTANCE) == TIM3)  || \

+                                          ((INSTANCE) == TIM5)  || \

+                                          ((INSTANCE) == TIM8)  || \

+                                          ((INSTANCE) == TIM16) || \

+                                          ((INSTANCE) == TIM17))

+

+/*************** TIM Instances : external trigger reamp input available *******/

+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                              ((INSTANCE) == TIM2)   || \

+                                              ((INSTANCE) == TIM3)   || \

+                                              ((INSTANCE) == TIM5)   || \

+                                              ((INSTANCE) == TIM8))

+

+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/

+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM6)   || \

+                                            ((INSTANCE) == TIM7)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15))

+

+/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/

+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM8)   || \

+                                           ((INSTANCE) == TIM12))

+

+/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/

+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM8))

+

+/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/

+#define IS_TIM_TISEL_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)   || \

+                                          ((INSTANCE) == TIM2)   || \

+                                          ((INSTANCE) == TIM3)   || \

+                                          ((INSTANCE) == TIM4)   || \

+                                          ((INSTANCE) == TIM5)   || \

+                                          ((INSTANCE) == TIM8)   || \

+                                          ((INSTANCE) == TIM15)  || \

+                                          ((INSTANCE) == TIM16)  || \

+                                          ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting commutation event *************/

+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \

+                                                     ((INSTANCE) == TIM8)    || \

+                                                     ((INSTANCE) == TIM15)   || \

+                                                     ((INSTANCE) == TIM16)   || \

+                                                     ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting encoder interface **************/

+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1)  || \

+                                                      ((__INSTANCE__) == TIM2)      || \

+                                                      ((__INSTANCE__) == TIM3)      || \

+                                                      ((__INSTANCE__) == TIM4)      || \

+                                                      ((__INSTANCE__) == TIM5)      || \

+                                                      ((__INSTANCE__) == TIM8))

+

+/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/

+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                                       ((INSTANCE) == TIM8))

+/******************* TIM Instances : output(s) available **********************/

+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \

+    ((((INSTANCE) == TIM1) &&                  \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4) ||          \

+      ((CHANNEL) == TIM_CHANNEL_5) ||          \

+      ((CHANNEL) == TIM_CHANNEL_6)))           \

+     ||                                        \

+     (((INSTANCE) == TIM2) &&                  \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM3) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1)||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM4) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM5) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM8) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4) ||          \

+      ((CHANNEL) == TIM_CHANNEL_5) ||          \

+      ((CHANNEL) == TIM_CHANNEL_6)))           \

+  ||                                           \

+     (((INSTANCE) == TIM12) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2)))           \

+  ||                                           \

+     (((INSTANCE) == TIM13) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM14) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM15) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+     ((CHANNEL) == TIM_CHANNEL_2)))            \

+  ||                                           \

+     (((INSTANCE) == TIM16) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM17) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1))))

+

+/****************** TIM Instances : supporting the break function *************/

+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\

+      (((INSTANCE) == TIM1)    || \

+      ((INSTANCE) == TIM8)     || \

+       ((INSTANCE) == TIM15)   || \

+       ((INSTANCE) == TIM16)   || \

+       ((INSTANCE) == TIM17))

+

+/************** TIM Instances : supporting Break source selection *************/

+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \

+                                               ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting complementary output(s) ********/

+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \

+   ((((INSTANCE) == TIM1) &&                    \

+     (((CHANNEL) == TIM_CHANNEL_1) ||           \

+      ((CHANNEL) == TIM_CHANNEL_2) ||           \

+      ((CHANNEL) == TIM_CHANNEL_3)))            \

+ ||                                             \

+      (((INSTANCE) == TIM8) &&                  \

+      (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||           \

+      ((CHANNEL) == TIM_CHANNEL_3)))            \

+    ||                                          \

+    (((INSTANCE) == TIM15) &&                   \

+      ((CHANNEL) == TIM_CHANNEL_1))             \

+    ||                                          \

+    (((INSTANCE) == TIM16) &&                   \

+     ((CHANNEL) == TIM_CHANNEL_1))              \

+    ||                                          \

+    (((INSTANCE) == TIM17) &&                   \

+     ((CHANNEL) == TIM_CHANNEL_1)))

+

+/****************** TIM Instances : supporting counting mode selection ********/

+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting repetition counter *************/

+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15)   || \

+   ((INSTANCE) == TIM16)   || \

+   ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting synchronization ****************/

+#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\

+    (((__INSTANCE__) == TIM1)    || \

+     ((__INSTANCE__) == TIM2)    || \

+     ((__INSTANCE__) == TIM3)    || \

+     ((__INSTANCE__) == TIM4)    || \

+     ((__INSTANCE__) == TIM5)    || \

+     ((__INSTANCE__) == TIM6)    || \

+     ((__INSTANCE__) == TIM8)    || \

+     ((__INSTANCE__) == TIM12)   || \

+     ((__INSTANCE__) == TIM15))

+

+/****************** TIM Instances : supporting clock division *****************/

+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15)   || \

+   ((INSTANCE) == TIM16)   || \

+   ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting external clock mode 1 for ETRF input */

+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting external clock mode 2 **********/

+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\

+ (((INSTANCE) == TIM1)     || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/

+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/

+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : supporting OCxREF clear *******************/

+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3))

+

+/****************** TIM Instances : TIM_32B_COUNTER ***************************/

+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM5))

+

+/****************** TIM Instances : TIM_BKIN2 ***************************/

+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting Hall sensor interface **********/

+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)  || \

+                                                             ((__INSTANCE__) == TIM2)  || \

+                                                             ((__INSTANCE__) == TIM3)  || \

+                                                             ((__INSTANCE__) == TIM4)  || \

+                                                             ((__INSTANCE__) == TIM5)  || \

+                                                             ((__INSTANCE__) == TIM15) || \

+                                                             ((__INSTANCE__) == TIM8))

+

+/****************************** HRTIM Instances *******************************/

+#define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))

+

+/******************** USART Instances : Synchronous mode **********************/

+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                     ((INSTANCE) == USART2) || \

+                                     ((INSTANCE) == USART3) || \

+                                     ((INSTANCE) == USART6))

+

+/******************** USART Instances : SPI slave mode ************************/

+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                              ((INSTANCE) == USART2) || \

+                                              ((INSTANCE) == USART3) || \

+                                              ((INSTANCE) == USART6))

+

+/******************** UART Instances : Asynchronous mode **********************/

+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                    ((INSTANCE) == USART2) || \

+                                    ((INSTANCE) == USART3) || \

+                                    ((INSTANCE) == UART4)  || \

+                                    ((INSTANCE) == UART5)  || \

+                                    ((INSTANCE) == USART6) || \

+                                    ((INSTANCE) == UART7)  || \

+                                    ((INSTANCE) == UART8))

+

+/******************** UART Instances : FIFO mode.******************************/

+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                         ((INSTANCE) == USART2) || \

+                                         ((INSTANCE) == USART3) || \

+                                         ((INSTANCE) == UART4)  || \

+                                         ((INSTANCE) == UART5)  || \

+                                         ((INSTANCE) == USART6) || \

+                                         ((INSTANCE) == UART7)  || \

+                                         ((INSTANCE) == UART8))

+

+/****************** UART Instances : Auto Baud Rate detection *****************/

+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                            ((INSTANCE) == USART2) || \

+                                                            ((INSTANCE) == USART3) || \

+                                                            ((INSTANCE) == UART4)  || \

+                                                            ((INSTANCE) == UART5)  || \

+                                                            ((INSTANCE) == USART6) || \

+                                                            ((INSTANCE) == UART7)  || \

+                                                            ((INSTANCE) == UART8))

+

+/*********************** UART Instances : Driver Enable ***********************/

+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                  ((INSTANCE) == USART2) || \

+                                                  ((INSTANCE) == USART3) || \

+                                                  ((INSTANCE) == UART4)  || \

+                                                  ((INSTANCE) == UART5)  || \

+                                                  ((INSTANCE) == USART6) || \

+                                                  ((INSTANCE) == UART7)  || \

+                                                  ((INSTANCE) == UART8)  || \

+                                                  ((INSTANCE) == LPUART1))

+

+/********************* UART Instances : Half-Duplex mode **********************/

+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                               ((INSTANCE) == USART2) || \

+                                               ((INSTANCE) == USART3) || \

+                                               ((INSTANCE) == UART4)  || \

+                                               ((INSTANCE) == UART5)  || \

+                                               ((INSTANCE) == USART6) || \

+                                               ((INSTANCE) == UART7)  || \

+                                               ((INSTANCE) == UART8)  || \

+                                               ((INSTANCE) == LPUART1))

+

+/******************* UART Instances : Hardware Flow control *******************/

+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                           ((INSTANCE) == USART2) || \

+                                           ((INSTANCE) == USART3) || \

+                                           ((INSTANCE) == UART4)  || \

+                                           ((INSTANCE) == UART5)  || \

+                                           ((INSTANCE) == USART6) || \

+                                           ((INSTANCE) == UART7)  || \

+                                           ((INSTANCE) == UART8)  || \

+                                           ((INSTANCE) == LPUART1))

+

+/************************* UART Instances : LIN mode **************************/

+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                        ((INSTANCE) == USART2) || \

+                                        ((INSTANCE) == USART3) || \

+                                        ((INSTANCE) == UART4)  || \

+                                        ((INSTANCE) == UART5)  || \

+                                        ((INSTANCE) == USART6) || \

+                                        ((INSTANCE) == UART7)  || \

+                                        ((INSTANCE) == UART8))

+

+/****************** UART Instances : Wake-up from Stop mode *******************/

+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                    ((INSTANCE) == USART2) || \

+                                                    ((INSTANCE) == USART3) || \

+                                                    ((INSTANCE) == UART4)  || \

+                                                    ((INSTANCE) == UART5)  || \

+                                                    ((INSTANCE) == USART6) || \

+                                                    ((INSTANCE) == UART7)  || \

+                                                    ((INSTANCE) == UART8)  || \

+                                                    ((INSTANCE) == LPUART1))

+

+/************************* UART Instances : IRDA mode *************************/

+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                    ((INSTANCE) == USART2) || \

+                                    ((INSTANCE) == USART3) || \

+                                    ((INSTANCE) == UART4)  || \

+                                    ((INSTANCE) == UART5)  || \

+                                    ((INSTANCE) == USART6) || \

+                                    ((INSTANCE) == UART7)  || \

+                                    ((INSTANCE) == UART8))

+

+/********************* USART Instances : Smard card mode **********************/

+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                         ((INSTANCE) == USART2) || \

+                                         ((INSTANCE) == USART3) || \

+                                         ((INSTANCE) == USART6))

+

+/****************************** LPUART Instance *******************************/

+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)

+

+/****************************** IWDG Instances ********************************/

+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG1)

+/****************************** USB Instances ********************************/

+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)

+

+/****************************** WWDG Instances ********************************/

+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG1)

+/****************************** MDIOS Instances ********************************/

+#define IS_MDIOS_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == MDIOS)

+

+/****************************** CEC Instances *********************************/

+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)

+

+/****************************** SAI Instances ********************************/

+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \

+                    ((INSTANCE) == SAI1_Block_B) || \

+                     ((INSTANCE) == SAI2_Block_A) || \

+                     ((INSTANCE) == SAI2_Block_B) || \

+                     ((INSTANCE) == SAI3_Block_A) || \

+                     ((INSTANCE) == SAI3_Block_B) || \

+                     ((INSTANCE) == SAI4_Block_A) || \

+                     ((INSTANCE) == SAI4_Block_B))

+

+/****************************** SPDIFRX Instances ********************************/

+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)

+

+/****************************** OPAMP Instances *******************************/

+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \

+                                         ((INSTANCE) == OPAMP2))

+

+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)

+

+/*********************** USB OTG PCD Instances ********************************/

+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \

+                                        ((INSTANCE) == USB_OTG_HS))

+

+/*********************** USB OTG HCD Instances ********************************/

+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \

+                                       ((INSTANCE) == USB_OTG_HS))

+

+/******************************************************************************/

+/*  For a painless codes migration between the STM32H7xx device product       */

+/*  lines, or with STM32F7xx devices the aliases defined below are put        */

+/*   in place to overcome the differences in the interrupt handlers and IRQn  */

+/*   definitions. No need to update developed interrupt code when moving      */

+/*  across product lines within the same STM32H7 Family                       */

+/******************************************************************************/

+

+/* Aliases for __IRQn */

+#define  RNG_IRQn                       HASH_RNG_IRQn

+#define  TIM1_BRK_TIM9_IRQn             TIM1_BRK_IRQn

+#define  TIM1_UP_TIM10_IRQn             TIM1_UP_IRQn

+#define  TIM1_TRG_COM_TIM11_IRQn        TIM1_TRG_COM_IRQn

+#define  PVD_IRQn                       PVD_AVD_IRQn

+

+

+

+/* Aliases for __IRQHandler */

+#define   RNG_IRQHandler               HASH_RNG_IRQHandler

+#define TIM1_BRK_TIM9_IRQHandler       TIM1_BRK_IRQHandler

+#define TIM1_UP_TIM9_IRQHandler        TIM1_UP_IRQHandler

+#define TIM1_TRG_COM_TIM11_IRQHandler  TIM1_TRG_COM_IRQHandler

+#define PVD_IRQHandler                 PVD_AVD_IRQHandler

+

+/* Aliases for COMP __IRQHandler */

+#define COMP_IRQHandler                COMP1_IRQHandler

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif /* __cplusplus */

+

+#endif /* STM32H750xx_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h753xx.h b/bsps/arm/stm32h7/include/stm32h753xx.h
new file mode 100644
index 0000000000..1bf8eef5d9
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h753xx.h
@@ -0,0 +1,26575 @@
+/**

+  ******************************************************************************

+  * @file    stm32h753xx.h

+  * @author  MCD Application Team

+  * @brief   CMSIS STM32H753xx Device Peripheral Access Layer Header File.

+  *

+  *          This file contains:

+  *           - Data structures and the address mapping for all peripherals

+  *           - Peripheral's registers declarations and bits definition

+  *           - Macros to access peripheral's registers hardware

+  *

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/** @addtogroup CMSIS_Device

+  * @{

+  */

+

+/** @addtogroup stm32h753xx

+  * @{

+  */

+

+#ifndef STM32H753xx_H

+#define STM32H753xx_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif /* __cplusplus */

+

+/** @addtogroup Peripheral_interrupt_number_definition

+  * @{

+  */

+

+/**

+ * @brief STM32H7XX Interrupt Number Definition, according to the selected device

+ *        in @ref Library_configuration_section

+ */

+typedef enum

+{

+/******  Cortex-M Processor Exceptions Numbers *****************************************************************/

+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */

+  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */

+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */

+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */

+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */

+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M SV Call Interrupt                                     */

+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M Debug Monitor Interrupt                               */

+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M Pend SV Interrupt                                     */

+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M System Tick Interrupt                                 */

+/******  STM32 specific Interrupt Numbers **********************************************************************/

+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)                   */

+  PVD_AVD_IRQn                = 1,      /*!< PVD/AVD through EXTI Line detection Interrupt                     */

+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */

+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */

+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */

+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */

+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */

+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */

+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */

+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */

+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */

+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */

+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */

+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */

+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */

+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */

+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */

+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */

+  ADC_IRQn                    = 18,     /*!< ADC1 and  ADC2 global Interrupts                                  */

+  FDCAN1_IT0_IRQn             = 19,     /*!< FDCAN1 Interrupt line 0                                           */

+  FDCAN2_IT0_IRQn             = 20,     /*!< FDCAN2 Interrupt line 0                                           */

+  FDCAN1_IT1_IRQn             = 21,     /*!< FDCAN1 Interrupt line 1                                           */

+  FDCAN2_IT1_IRQn             = 22,     /*!< FDCAN2 Interrupt line 1                                           */

+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */

+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                              */

+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                             */

+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt                            */

+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */

+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */

+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */

+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */

+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */

+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */

+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */

+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */

+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */

+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */

+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */

+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */

+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */

+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */

+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */

+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */

+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */

+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */

+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */

+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */

+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */

+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */

+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */

+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */

+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */

+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */

+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */

+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */

+  DMA2_Stream0_IRQn           = 56,     /*!<   DMA2 Stream 0 global Interrupt                                  */

+  DMA2_Stream1_IRQn           = 57,     /*!<   DMA2 Stream 1 global Interrupt                                  */

+  DMA2_Stream2_IRQn           = 58,     /*!<   DMA2 Stream 2 global Interrupt                                  */

+  DMA2_Stream3_IRQn           = 59,     /*!<   DMA2 Stream 3 global Interrupt                                  */

+  DMA2_Stream4_IRQn           = 60,     /*!<   DMA2 Stream 4 global Interrupt                                  */

+  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */

+  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */

+  FDCAN_CAL_IRQn              = 63,     /*!< FDCAN Calibration unit Interrupt                                  */

+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */

+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */

+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */

+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */

+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */

+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */

+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */

+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */

+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */

+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */

+  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */

+  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */

+  HASH_RNG_IRQn               = 80,     /*!< HASH and RNG global interrupt                                     */

+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */

+  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */

+  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */

+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */

+  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */

+  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */

+  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */

+  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */

+  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */

+  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */

+  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */

+  QUADSPI_IRQn                = 92,     /*!< Quad SPI global interrupt                                         */

+  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */

+  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */

+  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */

+  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */

+  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */

+  OTG_FS_EP1_OUT_IRQn         = 98,     /*!< USB OTG HS2 global interrupt                                      */

+  OTG_FS_EP1_IN_IRQn          = 99,     /*!< USB OTG HS2 End Point 1 Out global interrupt                      */

+  OTG_FS_WKUP_IRQn            = 100,    /*!< USB OTG HS2 End Point 1 In global interrupt                       */

+  OTG_FS_IRQn                 = 101,    /*!< USB OTG HS2 Wakeup through EXTI interrupt                         */

+  DMAMUX1_OVR_IRQn            = 102,    /*!<DMAMUX1 Overrun interrupt                                          */

+  HRTIM1_Master_IRQn          = 103,    /*!< HRTIM Master Timer global Interrupts                              */

+  HRTIM1_TIMA_IRQn            = 104,    /*!< HRTIM Timer A global Interrupt                                    */

+  HRTIM1_TIMB_IRQn            = 105,    /*!< HRTIM Timer B global Interrupt                                    */

+  HRTIM1_TIMC_IRQn            = 106,    /*!< HRTIM Timer C global Interrupt                                    */

+  HRTIM1_TIMD_IRQn            = 107,    /*!< HRTIM Timer D global Interrupt                                    */

+  HRTIM1_TIME_IRQn            = 108,    /*!< HRTIM Timer E global Interrupt                                    */

+  HRTIM1_FLT_IRQn             = 109,    /*!< HRTIM Fault global Interrupt                                      */

+  DFSDM1_FLT0_IRQn            = 110,    /*!<DFSDM Filter1 Interrupt                                            */

+  DFSDM1_FLT1_IRQn            = 111,    /*!<DFSDM Filter2 Interrupt                                            */

+  DFSDM1_FLT2_IRQn            = 112,    /*!<DFSDM Filter3 Interrupt                                            */

+  DFSDM1_FLT3_IRQn            = 113,    /*!<DFSDM Filter4 Interrupt                                            */

+  SAI3_IRQn                   = 114,    /*!< SAI3 global Interrupt                                             */

+  SWPMI1_IRQn                 = 115,    /*!< Serial Wire Interface 1 global interrupt                          */

+  TIM15_IRQn                  = 116,    /*!< TIM15 global Interrupt                                            */

+  TIM16_IRQn                  = 117,    /*!< TIM16 global Interrupt                                            */

+  TIM17_IRQn                  = 118,    /*!< TIM17 global Interrupt                                            */

+  MDIOS_WKUP_IRQn             = 119,    /*!< MDIOS Wakeup  Interrupt                                           */

+  MDIOS_IRQn                  = 120,    /*!< MDIOS global Interrupt                                            */

+  JPEG_IRQn                   = 121,    /*!< JPEG global Interrupt                                             */

+  MDMA_IRQn                   = 122,    /*!< MDMA global Interrupt                                             */

+  SDMMC2_IRQn                 = 124,    /*!< SDMMC2 global Interrupt                                           */

+  HSEM1_IRQn                  = 125,    /*!< HSEM1 global Interrupt                                            */

+  ADC3_IRQn                   = 127,    /*!< ADC3 global Interrupt                                             */

+  DMAMUX2_OVR_IRQn            = 128,    /*!<DMAMUX2 Overrun interrupt                                          */

+  BDMA_Channel0_IRQn          = 129,    /*!< BDMA Channel 0 global Interrupt                                   */

+  BDMA_Channel1_IRQn          = 130,    /*!< BDMA Channel 1 global Interrupt                                   */

+  BDMA_Channel2_IRQn          = 131,    /*!< BDMA Channel 2 global Interrupt                                   */

+  BDMA_Channel3_IRQn          = 132,    /*!< BDMA Channel 3 global Interrupt                                   */

+  BDMA_Channel4_IRQn          = 133,    /*!< BDMA Channel 4 global Interrupt                                   */

+  BDMA_Channel5_IRQn          = 134,    /*!< BDMA Channel 5 global Interrupt                                   */

+  BDMA_Channel6_IRQn          = 135,    /*!< BDMA Channel 6 global Interrupt                                   */

+  BDMA_Channel7_IRQn          = 136,    /*!< BDMA Channel 7 global Interrupt                                   */

+  COMP_IRQn                   = 137 ,   /*!< COMP global Interrupt                                             */

+  LPTIM2_IRQn                 = 138,    /*!< LP TIM2 global interrupt                                          */

+  LPTIM3_IRQn                 = 139,    /*!< LP TIM3 global interrupt                                          */

+  LPTIM4_IRQn                 = 140,    /*!< LP TIM4 global interrupt                                          */

+  LPTIM5_IRQn                 = 141,    /*!< LP TIM5 global interrupt                                          */

+  LPUART1_IRQn                = 142,    /*!< LP UART1 interrupt                                                */

+  CRS_IRQn                    = 144,    /*!< Clock Recovery Global Interrupt                                   */

+  ECC_IRQn                    = 145,    /*!< ECC diagnostic Global Interrupt                                   */

+  SAI4_IRQn                   = 146,    /*!< SAI4 global interrupt                                             */

+  WAKEUP_PIN_IRQn             = 149,    /*!< Interrupt for all 6 wake-up pins                                  */

+} IRQn_Type;

+

+/**

+  * @}

+  */

+

+/** @addtogroup Configuration_section_for_CMSIS

+  * @{

+  */

+

+

+

+

+/**

+  * @brief Configuration of the Cortex-M7 Processor and Core Peripherals

+   */

+#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */

+#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */

+#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */

+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */

+#define __FPU_PRESENT             1       /*!< FPU present                                   */

+#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */

+#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */

+#include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */

+

+/**

+  * @}

+  */

+

+

+

+

+#include "system_stm32h7xx.h"

+#include <stdint.h>

+

+/** @addtogroup Peripheral_registers_structures

+  * @{

+  */

+

+/**

+  * @brief Analog to Digital Converter

+  */

+

+typedef struct

+{

+  __IO uint32_t ISR;              /*!< ADC Interrupt and Status Register,                          Address offset: 0x00 */

+  __IO uint32_t IER;              /*!< ADC Interrupt Enable Register,                              Address offset: 0x04 */

+  __IO uint32_t CR;               /*!< ADC control register,                                       Address offset: 0x08 */

+  __IO uint32_t CFGR;             /*!< ADC Configuration register,                                 Address offset: 0x0C */

+  __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                               Address offset: 0x10 */

+  __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                                 Address offset: 0x14 */

+  __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                                 Address offset: 0x18 */

+  __IO uint32_t PCSEL;            /*!< ADC pre-channel selection,                                  Address offset: 0x1C */

+  __IO uint32_t LTR1;             /*!< ADC watchdog Lower threshold register 1,                    Address offset: 0x20 */

+  __IO uint32_t HTR1;             /*!< ADC watchdog higher threshold register 1,                   Address offset: 0x24 */

+  uint32_t      RESERVED1;        /*!< Reserved, 0x028                                                                  */

+  uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                                  */

+  __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                            Address offset: 0x30 */

+  __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                            Address offset: 0x34 */

+  __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                            Address offset: 0x38 */

+  __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                            Address offset: 0x3C */

+  __IO uint32_t DR;               /*!< ADC regular data register,                                  Address offset: 0x40 */

+  uint32_t      RESERVED3;        /*!< Reserved, 0x044                                                                  */

+  uint32_t      RESERVED4;        /*!< Reserved, 0x048                                                                  */

+  __IO uint32_t JSQR;             /*!< ADC injected sequence register,                             Address offset: 0x4C */

+  uint32_t      RESERVED5[4];     /*!< Reserved, 0x050 - 0x05C                                                          */

+  __IO uint32_t OFR1;             /*!< ADC offset register 1,                                      Address offset: 0x60 */

+  __IO uint32_t OFR2;             /*!< ADC offset register 2,                                      Address offset: 0x64 */

+  __IO uint32_t OFR3;             /*!< ADC offset register 3,                                      Address offset: 0x68 */

+  __IO uint32_t OFR4;             /*!< ADC offset register 4,                                      Address offset: 0x6C */

+  uint32_t      RESERVED6[4];     /*!< Reserved, 0x070 - 0x07C                                                          */

+  __IO uint32_t JDR1;             /*!< ADC injected data register 1,                               Address offset: 0x80 */

+  __IO uint32_t JDR2;             /*!< ADC injected data register 2,                               Address offset: 0x84 */

+  __IO uint32_t JDR3;             /*!< ADC injected data register 3,                               Address offset: 0x88 */

+  __IO uint32_t JDR4;             /*!< ADC injected data register 4,                               Address offset: 0x8C */

+  uint32_t      RESERVED7[4];     /*!< Reserved, 0x090 - 0x09C                                                          */

+  __IO uint32_t AWD2CR;           /*!< ADC  Analog Watchdog 2 Configuration Register,              Address offset: 0xA0 */

+  __IO uint32_t AWD3CR;           /*!< ADC  Analog Watchdog 3 Configuration Register,              Address offset: 0xA4 */

+  uint32_t      RESERVED8;        /*!< Reserved, 0x0A8                                                                  */

+  uint32_t      RESERVED9;        /*!< Reserved, 0x0AC                                                                  */

+  __IO uint32_t LTR2;             /*!< ADC watchdog Lower threshold register 2,                    Address offset: 0xB0 */

+  __IO uint32_t HTR2;             /*!< ADC watchdog Higher threshold register 2,                   Address offset: 0xB4 */

+  __IO uint32_t LTR3;             /*!< ADC watchdog Lower threshold register 3,                    Address offset: 0xB8 */

+  __IO uint32_t HTR3;             /*!< ADC watchdog Higher threshold register 3,                   Address offset: 0xBC */

+  __IO uint32_t DIFSEL;           /*!< ADC  Differential Mode Selection Register,                  Address offset: 0xC0 */

+  __IO uint32_t CALFACT;          /*!< ADC  Calibration Factors,                                   Address offset: 0xC4 */

+  __IO uint32_t CALFACT2;         /*!< ADC  Linearity Calibration Factors,                         Address offset: 0xC8 */

+} ADC_TypeDef;

+

+

+typedef struct

+{

+__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */

+uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */

+__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */

+__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */

+__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */

+

+} ADC_Common_TypeDef;

+

+

+/**

+  * @brief VREFBUF

+  */

+

+typedef struct

+{

+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */

+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */

+} VREFBUF_TypeDef;

+

+

+/**

+  * @brief FD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */

+  __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */

+  __IO uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */

+  __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */

+  __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */

+  __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */

+  __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */

+  __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */

+  __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */

+  __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */

+  __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */

+  __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */

+  __IO uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */

+  __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */

+  __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */

+  __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */

+  __IO uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */

+  __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */

+  __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */

+  __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */

+  __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */

+  __IO uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */

+  __IO uint32_t GFC;          /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */

+  __IO uint32_t SIDFC;        /*!< FDCAN Standard ID Filter Configuration register,                 Address offset: 0x084 */

+  __IO uint32_t XIDFC;        /*!< FDCAN Extended ID Filter Configuration register,                 Address offset: 0x088 */

+  __IO uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */

+  __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x090 */

+  __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x094 */

+  __IO uint32_t NDAT1;        /*!< FDCAN New Data 1 register,                                       Address offset: 0x098 */

+  __IO uint32_t NDAT2;        /*!< FDCAN New Data 2 register,                                       Address offset: 0x09C */

+  __IO uint32_t RXF0C;        /*!< FDCAN Rx FIFO 0 Configuration register,                          Address offset: 0x0A0 */

+  __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x0A4 */

+  __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x0A8 */

+  __IO uint32_t RXBC;         /*!< FDCAN Rx Buffer Configuration register,                          Address offset: 0x0AC */

+  __IO uint32_t RXF1C;        /*!< FDCAN Rx FIFO 1 Configuration register,                          Address offset: 0x0B0 */

+  __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x0B4 */

+  __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x0B8 */

+  __IO uint32_t RXESC;        /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register,        Address offset: 0x0BC */

+  __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */

+  __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */

+  __IO uint32_t TXESC;        /*!< FDCAN Tx Buffer Element Size Configuration register,             Address offset: 0x0C8 */

+  __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0CC */

+  __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0D0 */

+  __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D4 */

+  __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D8 */

+  __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0DC */

+  __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0E0 */

+  __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */

+  __IO uint32_t RESERVED6[2]; /*!< Reserved,                                                                0x0E8 - 0x0EC */

+  __IO uint32_t TXEFC;        /*!< FDCAN Tx Event FIFO Configuration register,                      Address offset: 0x0F0 */

+  __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0F4 */

+  __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0F8 */

+  __IO uint32_t RESERVED7;    /*!< Reserved,                                                                        0x0FC */

+} FDCAN_GlobalTypeDef;

+

+/**

+  * @brief TTFD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t TTTMC;          /*!< TT Trigger Memory Configuration register,    Address offset: 0x100 */

+  __IO uint32_t TTRMC;          /*!< TT Reference Message Configuration register, Address offset: 0x104 */

+  __IO uint32_t TTOCF;          /*!< TT Operation Configuration register,         Address offset: 0x108 */

+  __IO uint32_t TTMLM;          /*!< TT Matrix Limits register,                   Address offset: 0x10C */

+  __IO uint32_t TURCF;          /*!< TUR Configuration register,                  Address offset: 0x110 */

+  __IO uint32_t TTOCN;          /*!< TT Operation Control register,               Address offset: 0x114 */

+  __IO uint32_t TTGTP;          /*!< TT Global Time Preset register,              Address offset: 0x118 */

+  __IO uint32_t TTTMK;          /*!< TT Time Mark register,                       Address offset: 0x11C */

+  __IO uint32_t TTIR;           /*!< TT Interrupt register,                       Address offset: 0x120 */

+  __IO uint32_t TTIE;           /*!< TT Interrupt Enable register,                Address offset: 0x124 */

+  __IO uint32_t TTILS;          /*!< TT Interrupt Line Select register,           Address offset: 0x128 */

+  __IO uint32_t TTOST;          /*!< TT Operation Status register,                Address offset: 0x12C */

+  __IO uint32_t TURNA;          /*!< TT TUR Numerator Actual register,            Address offset: 0x130 */

+  __IO uint32_t TTLGT;          /*!< TT Local and Global Time register,           Address offset: 0x134 */

+  __IO uint32_t TTCTC;          /*!< TT Cycle Time and Count register,            Address offset: 0x138 */

+  __IO uint32_t TTCPT;          /*!< TT Capture Time register,                    Address offset: 0x13C */

+  __IO uint32_t TTCSM;          /*!< TT Cycle Sync Mark register,                 Address offset: 0x140 */

+  __IO uint32_t RESERVED1[111]; /*!< Reserved,                                            0x144 - 0x2FC */

+  __IO uint32_t TTTS;           /*!< TT Trigger Select register,                  Address offset: 0x300 */

+} TTCAN_TypeDef;

+

+/**

+  * @brief FD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t CREL;  /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */

+  __IO uint32_t CCFG;  /*!< Calibration Configuration register,           Address offset: 0x04 */

+  __IO uint32_t CSTAT; /*!< Calibration Status register,                  Address offset: 0x08 */

+  __IO uint32_t CWD;   /*!< Calibration Watchdog register,                Address offset: 0x0C */

+  __IO uint32_t IR;    /*!< CCU Interrupt register,                       Address offset: 0x10 */

+  __IO uint32_t IE;    /*!< CCU Interrupt Enable register,                Address offset: 0x14 */

+} FDCAN_ClockCalibrationUnit_TypeDef;

+

+

+/**

+  * @brief Consumer Electronics Control

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;           /*!< CEC control register,              Address offset:0x00 */

+  __IO uint32_t CFGR;         /*!< CEC configuration register,        Address offset:0x04 */

+  __IO uint32_t TXDR;         /*!< CEC Tx data register ,             Address offset:0x08 */

+  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,              Address offset:0x0C */

+  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register, Address offset:0x10 */

+  __IO uint32_t IER;          /*!< CEC interrupt enable register,     Address offset:0x14 */

+}CEC_TypeDef;

+

+/**

+  * @brief CRC calculation unit

+  */

+

+typedef struct

+{

+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */

+  __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */

+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */

+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */

+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */

+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */

+} CRC_TypeDef;

+

+

+/**

+  * @brief Clock Recovery System

+  */

+typedef struct

+{

+__IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */

+__IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */

+__IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */

+__IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */

+} CRS_TypeDef;

+

+

+/**

+  * @brief Digital to Analog Converter

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */

+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */

+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */

+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */

+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */

+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */

+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */

+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */

+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */

+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */

+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */

+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */

+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */

+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */

+  __IO uint32_t CCR;      /*!< DAC calibration control register,                        Address offset: 0x38 */

+  __IO uint32_t MCR;      /*!< DAC mode control register,                               Address offset: 0x3C */

+  __IO uint32_t SHSR1;    /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */

+  __IO uint32_t SHSR2;    /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */

+  __IO uint32_t SHHR;     /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */

+  __IO uint32_t SHRR;     /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */

+} DAC_TypeDef;

+

+/**

+  * @brief DFSDM module registers

+  */

+typedef struct

+{

+  __IO uint32_t FLTCR1;          /*!< DFSDM control register1,                          Address offset: 0x100 */

+  __IO uint32_t FLTCR2;          /*!< DFSDM control register2,                          Address offset: 0x104 */

+  __IO uint32_t FLTISR;          /*!< DFSDM interrupt and status register,              Address offset: 0x108 */

+  __IO uint32_t FLTICR;          /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */

+  __IO uint32_t FLTJCHGR;        /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */

+  __IO uint32_t FLTFCR;          /*!< DFSDM filter control register,                    Address offset: 0x114 */

+  __IO uint32_t FLTJDATAR;       /*!< DFSDM data register for injected group,           Address offset: 0x118 */

+  __IO uint32_t FLTRDATAR;       /*!< DFSDM data register for regular group,            Address offset: 0x11C */

+  __IO uint32_t FLTAWHTR;        /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */

+  __IO uint32_t FLTAWLTR;        /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */

+  __IO uint32_t FLTAWSR;         /*!< DFSDM analog watchdog status register             Address offset: 0x128 */

+  __IO uint32_t FLTAWCFR;        /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */

+  __IO uint32_t FLTEXMAX;        /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */

+  __IO uint32_t FLTEXMIN;        /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */

+  __IO uint32_t FLTCNVTIMR;      /*!< DFSDM conversion timer,                           Address offset: 0x138 */

+} DFSDM_Filter_TypeDef;

+

+/**

+  * @brief DFSDM channel configuration registers

+  */

+typedef struct

+{

+  __IO uint32_t CHCFGR1;      /*!< DFSDM channel configuration register1,            Address offset: 0x00 */

+  __IO uint32_t CHCFGR2;      /*!< DFSDM channel configuration register2,            Address offset: 0x04 */

+  __IO uint32_t CHAWSCDR;     /*!< DFSDM channel analog watchdog and

+                                   short circuit detector register,                  Address offset: 0x08 */

+  __IO uint32_t CHWDATAR;     /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */

+  __IO uint32_t CHDATINR;     /*!< DFSDM channel data input register,                Address offset: 0x10 */

+} DFSDM_Channel_TypeDef;

+

+/**

+  * @brief Debug MCU

+  */

+typedef struct

+{

+  __IO uint32_t IDCODE;        /*!< MCU device ID code,                     Address offset: 0x00 */

+  __IO uint32_t CR;            /*!< Debug MCU configuration register,       Address offset: 0x04 */

+  uint32_t RESERVED4[11];      /*!< Reserved,                             Address offset: 0x08 */

+  __IO uint32_t APB3FZ1;     /*!< Debug MCU APB3FZ1 freeze register,    Address offset: 0x34 */

+  uint32_t RESERVED5;          /*!< Reserved,                             Address offset: 0x38 */

+  __IO uint32_t APB1LFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x3C */

+  uint32_t RESERVED6;          /*!< Reserved,                             Address offset: 0x40 */

+  __IO uint32_t APB1HFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x44 */

+  uint32_t RESERVED7;          /*!< Reserved,                             Address offset: 0x48 */

+  __IO uint32_t APB2FZ1;     /*!< Debug MCU APB2FZ1 freeze register,    Address offset: 0x4C */

+  uint32_t RESERVED8;          /*!< Reserved,                             Address offset: 0x50 */

+  __IO uint32_t APB4FZ1;     /*!< Debug MCU APB4FZ1 freeze register,    Address offset: 0x54 */

+}DBGMCU_TypeDef;

+/**

+  * @brief DCMI

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */

+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */

+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */

+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */

+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */

+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */

+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */

+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */

+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */

+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */

+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */

+} DCMI_TypeDef;

+

+/**

+  * @brief DMA Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */

+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */

+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */

+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */

+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */

+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */

+} DMA_Stream_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */

+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */

+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */

+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */

+} DMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CCR;          /*!< DMA channel x configuration register          */

+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register         */

+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register     */

+  __IO uint32_t CM0AR;        /*!< DMA channel x memory 0 address register       */

+  __IO uint32_t CM1AR;        /*!< DMA channel x memory 1 address register       */

+} BDMA_Channel_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */

+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */

+} BDMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CCR;        /*!< DMA Multiplexer Channel x Control Register   */

+}DMAMUX_Channel_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CSR;      /*!< DMA Channel Status Register     */

+  __IO uint32_t  CFR;      /*!< DMA Channel Clear Flag Register */

+}DMAMUX_ChannelStatus_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  RGCR;        /*!< DMA Request Generator x Control Register   */

+}DMAMUX_RequestGen_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  RGSR;        /*!< DMA Request Generator Status Register       */

+  __IO uint32_t  RGCFR;       /*!< DMA Request Generator Clear Flag Register   */

+}DMAMUX_RequestGenStatus_TypeDef;

+

+/**

+  * @brief MDMA Controller

+  */

+typedef struct

+{

+  __IO uint32_t  GISR0;   /*!< MDMA Global Interrupt/Status Register 0,          Address offset: 0x00 */

+}MDMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CISR;      /*!< MDMA channel x interrupt/status register,             Address offset: 0x40 */

+  __IO uint32_t  CIFCR;     /*!< MDMA channel x interrupt flag clear register,         Address offset: 0x44 */

+  __IO uint32_t  CESR;      /*!< MDMA Channel x error status register,                 Address offset: 0x48 */

+  __IO uint32_t  CCR;       /*!< MDMA channel x control register,                      Address offset: 0x4C */

+  __IO uint32_t  CTCR;      /*!< MDMA channel x Transfer Configuration register,       Address offset: 0x50 */

+  __IO uint32_t  CBNDTR;    /*!< MDMA Channel x block number of data register,         Address offset: 0x54 */

+  __IO uint32_t  CSAR;      /*!< MDMA channel x source address register,               Address offset: 0x58 */

+  __IO uint32_t  CDAR;      /*!< MDMA channel x destination address register,          Address offset: 0x5C */

+  __IO uint32_t  CBRUR;     /*!< MDMA channel x Block Repeat address Update register,  Address offset: 0x60 */

+  __IO uint32_t  CLAR;      /*!< MDMA channel x Link Address register,                 Address offset: 0x64 */

+  __IO uint32_t  CTBR;      /*!< MDMA channel x Trigger and Bus selection Register,    Address offset: 0x68 */

+  uint32_t       RESERVED0; /*!< Reserved, 0x68                                                             */

+  __IO uint32_t  CMAR;      /*!< MDMA channel x Mask address register,                 Address offset: 0x70 */

+  __IO uint32_t  CMDR;      /*!< MDMA channel x Mask Data register,                    Address offset: 0x74 */

+}MDMA_Channel_TypeDef;

+

+/**

+  * @brief DMA2D Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */

+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */

+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */

+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */

+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */

+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */

+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */

+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */

+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */

+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */

+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */

+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */

+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */

+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */

+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */

+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */

+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */

+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */

+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */

+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */

+  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */

+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */

+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */

+} DMA2D_TypeDef;

+

+

+/**

+  * @brief Ethernet MAC

+  */

+typedef struct

+{

+  __IO uint32_t MACCR;

+  __IO uint32_t MACECR;

+  __IO uint32_t MACPFR;

+  __IO uint32_t MACWTR;

+  __IO uint32_t MACHT0R;

+  __IO uint32_t MACHT1R;

+  uint32_t      RESERVED1[14];

+  __IO uint32_t MACVTR;

+  uint32_t      RESERVED2;

+  __IO uint32_t MACVHTR;

+  uint32_t      RESERVED3;

+  __IO uint32_t MACVIR;

+  __IO uint32_t MACIVIR;

+  uint32_t      RESERVED4[2];

+  __IO uint32_t MACTFCR;

+  uint32_t      RESERVED5[7];

+  __IO uint32_t MACRFCR;

+  uint32_t      RESERVED6[7];

+  __IO uint32_t MACISR;

+  __IO uint32_t MACIER;

+  __IO uint32_t MACRXTXSR;

+  uint32_t      RESERVED7;

+  __IO uint32_t MACPCSR;

+  __IO uint32_t MACRWKPFR;

+  uint32_t      RESERVED8[2];

+  __IO uint32_t MACLCSR;

+  __IO uint32_t MACLTCR;

+  __IO uint32_t MACLETR;

+  __IO uint32_t MAC1USTCR;

+  uint32_t      RESERVED9[12];

+  __IO uint32_t MACVR;

+  __IO uint32_t MACDR;

+  uint32_t      RESERVED10;

+  __IO uint32_t MACHWF0R;

+  __IO uint32_t MACHWF1R;

+  __IO uint32_t MACHWF2R;

+  uint32_t      RESERVED11[54];

+  __IO uint32_t MACMDIOAR;

+  __IO uint32_t MACMDIODR;

+  uint32_t      RESERVED12[2];

+  __IO uint32_t MACARPAR;

+  uint32_t      RESERVED13[59];

+  __IO uint32_t MACA0HR;

+  __IO uint32_t MACA0LR;

+  __IO uint32_t MACA1HR;

+  __IO uint32_t MACA1LR;

+  __IO uint32_t MACA2HR;

+  __IO uint32_t MACA2LR;

+  __IO uint32_t MACA3HR;

+  __IO uint32_t MACA3LR;

+  uint32_t      RESERVED14[248];

+  __IO uint32_t MMCCR;

+  __IO uint32_t MMCRIR;

+  __IO uint32_t MMCTIR;

+  __IO uint32_t MMCRIMR;

+  __IO uint32_t MMCTIMR;

+  uint32_t      RESERVED15[14];

+  __IO uint32_t MMCTSCGPR;

+  __IO uint32_t MMCTMCGPR;

+  uint32_t      RESERVED16[5];

+  __IO uint32_t MMCTPCGR;

+  uint32_t      RESERVED17[10];

+  __IO uint32_t MMCRCRCEPR;

+  __IO uint32_t MMCRAEPR;

+  uint32_t      RESERVED18[10];

+  __IO uint32_t MMCRUPGR;

+  uint32_t      RESERVED19[9];

+  __IO uint32_t MMCTLPIMSTR;

+  __IO uint32_t MMCTLPITCR;

+  __IO uint32_t MMCRLPIMSTR;

+  __IO uint32_t MMCRLPITCR;

+  uint32_t      RESERVED20[65];

+  __IO uint32_t MACL3L4C0R;

+  __IO uint32_t MACL4A0R;

+  uint32_t      RESERVED21[2];

+  __IO uint32_t MACL3A0R0R;

+  __IO uint32_t MACL3A1R0R;

+  __IO uint32_t MACL3A2R0R;

+  __IO uint32_t MACL3A3R0R;

+  uint32_t      RESERVED22[4];

+  __IO uint32_t MACL3L4C1R;

+  __IO uint32_t MACL4A1R;

+  uint32_t      RESERVED23[2];

+  __IO uint32_t MACL3A0R1R;

+  __IO uint32_t MACL3A1R1R;

+  __IO uint32_t MACL3A2R1R;

+  __IO uint32_t MACL3A3R1R;

+  uint32_t      RESERVED24[108];

+  __IO uint32_t MACTSCR;

+  __IO uint32_t MACSSIR;

+  __IO uint32_t MACSTSR;

+  __IO uint32_t MACSTNR;

+  __IO uint32_t MACSTSUR;

+  __IO uint32_t MACSTNUR;

+  __IO uint32_t MACTSAR;

+  uint32_t      RESERVED25;

+  __IO uint32_t MACTSSR;

+  uint32_t      RESERVED26[3];

+  __IO uint32_t MACTTSSNR;

+  __IO uint32_t MACTTSSSR;

+  uint32_t      RESERVED27[2];

+  __IO uint32_t MACACR;

+  uint32_t      RESERVED28;

+  __IO uint32_t MACATSNR;

+  __IO uint32_t MACATSSR;

+  __IO uint32_t MACTSIACR;

+  __IO uint32_t MACTSEACR;

+  __IO uint32_t MACTSICNR;

+  __IO uint32_t MACTSECNR;

+  uint32_t      RESERVED29[4];

+  __IO uint32_t MACPPSCR;

+  uint32_t      RESERVED30[3];

+  __IO uint32_t MACPPSTTSR;

+  __IO uint32_t MACPPSTTNR;

+  __IO uint32_t MACPPSIR;

+  __IO uint32_t MACPPSWR;

+  uint32_t      RESERVED31[12];

+  __IO uint32_t MACPOCR;

+  __IO uint32_t MACSPI0R;

+  __IO uint32_t MACSPI1R;

+  __IO uint32_t MACSPI2R;

+  __IO uint32_t MACLMIR;

+  uint32_t      RESERVED32[11];

+  __IO uint32_t MTLOMR;

+  uint32_t      RESERVED33[7];

+  __IO uint32_t MTLISR;

+  uint32_t      RESERVED34[55];

+  __IO uint32_t MTLTQOMR;

+  __IO uint32_t MTLTQUR;

+  __IO uint32_t MTLTQDR;

+  uint32_t      RESERVED35[8];

+  __IO uint32_t MTLQICSR;

+  __IO uint32_t MTLRQOMR;

+  __IO uint32_t MTLRQMPOCR;

+  __IO uint32_t MTLRQDR;

+  uint32_t      RESERVED36[177];

+  __IO uint32_t DMAMR;

+  __IO uint32_t DMASBMR;

+  __IO uint32_t DMAISR;

+  __IO uint32_t DMADSR;

+  uint32_t      RESERVED37[60];

+  __IO uint32_t DMACCR;

+  __IO uint32_t DMACTCR;

+  __IO uint32_t DMACRCR;

+  uint32_t      RESERVED38[2];

+  __IO uint32_t DMACTDLAR;

+  uint32_t      RESERVED39;

+  __IO uint32_t DMACRDLAR;

+  __IO uint32_t DMACTDTPR;

+  uint32_t      RESERVED40;

+  __IO uint32_t DMACRDTPR;

+  __IO uint32_t DMACTDRLR;

+  __IO uint32_t DMACRDRLR;

+  __IO uint32_t DMACIER;

+  __IO uint32_t DMACRIWTR;

+__IO uint32_t DMACSFCSR;

+  uint32_t      RESERVED41;

+  __IO uint32_t DMACCATDR;

+  uint32_t      RESERVED42;

+  __IO uint32_t DMACCARDR;

+  uint32_t      RESERVED43;

+  __IO uint32_t DMACCATBR;

+  uint32_t      RESERVED44;

+  __IO uint32_t DMACCARBR;

+  __IO uint32_t DMACSR;

+uint32_t      RESERVED45[2];

+__IO uint32_t DMACMFCR;

+}ETH_TypeDef;

+/**

+  * @brief External Interrupt/Event Controller

+  */

+

+typedef struct

+{

+__IO uint32_t RTSR1;               /*!< EXTI Rising trigger selection register,          Address offset: 0x00 */

+__IO uint32_t FTSR1;               /*!< EXTI Falling trigger selection register,         Address offset: 0x04 */

+__IO uint32_t SWIER1;              /*!< EXTI Software interrupt event register,          Address offset: 0x08 */

+__IO uint32_t D3PMR1;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */

+__IO uint32_t D3PCR1L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L)     Address offset: 0x10 */

+__IO uint32_t D3PCR1H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H)   Address offset: 0x14 */

+uint32_t      RESERVED1[2];        /*!< Reserved,                                        0x18 to 0x1C         */

+__IO uint32_t RTSR2;               /*!< EXTI Rising trigger selection register,          Address offset: 0x20 */

+__IO uint32_t FTSR2;               /*!< EXTI Falling trigger selection register,         Address offset: 0x24 */

+__IO uint32_t SWIER2;              /*!< EXTI Software interrupt event register,          Address offset: 0x28 */

+__IO uint32_t D3PMR2;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */

+__IO uint32_t D3PCR2L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L)  Address offset: 0x30 */

+__IO uint32_t D3PCR2H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */

+uint32_t      RESERVED2[2];        /*!< Reserved,                                        0x38 to 0x3C         */

+__IO uint32_t RTSR3;               /*!< EXTI Rising trigger selection register,          Address offset: 0x40 */

+__IO uint32_t FTSR3;               /*!< EXTI Falling trigger selection register,         Address offset: 0x44 */

+__IO uint32_t SWIER3;              /*!< EXTI Software interrupt event register,          Address offset: 0x48 */

+__IO uint32_t D3PMR3;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */

+__IO uint32_t D3PCR3L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */

+__IO uint32_t D3PCR3H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */

+uint32_t      RESERVED3[10];       /*!< Reserved,                                        0x58 to 0x7C         */

+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                    Address offset: 0x80 */

+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                        Address offset: 0x84 */

+__IO uint32_t PR1;                 /*!< EXTI Pending register,                           Address offset: 0x88 */

+uint32_t      RESERVED4;           /*!< Reserved,                                        0x8C                 */

+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                    Address offset: 0x90 */

+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                        Address offset: 0x94 */

+__IO uint32_t PR2;                 /*!< EXTI Pending register,                           Address offset: 0x98 */

+uint32_t      RESERVED5;           /*!< Reserved,                                        0x9C                 */

+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                    Address offset: 0xA0 */

+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                        Address offset: 0xA4 */

+__IO uint32_t PR3;                 /*!< EXTI Pending register,                           Address offset: 0xA8 */

+}EXTI_TypeDef;

+

+typedef struct

+{

+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                Address offset: 0x00 */

+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                    Address offset: 0x04 */

+__IO uint32_t PR1;                 /*!< EXTI Pending register,                       Address offset: 0x08 */

+uint32_t      RESERVED1;           /*!< Reserved, 0x0C                                                    */

+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                Address offset: 0x10 */

+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                    Address offset: 0x14 */

+__IO uint32_t PR2;                 /*!< EXTI Pending register,                       Address offset: 0x18 */

+uint32_t      RESERVED2;           /*!< Reserved, 0x1C                                                    */

+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                Address offset: 0x20 */

+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                    Address offset: 0x24 */

+__IO uint32_t PR3;                 /*!< EXTI Pending register,                       Address offset: 0x28 */

+}EXTI_Core_TypeDef;

+

+

+/**

+  * @brief FLASH Registers

+  */

+

+typedef struct

+{

+  __IO uint32_t ACR;             /*!< FLASH access control register,                            Address offset: 0x00  */

+  __IO uint32_t KEYR1;           /*!< Flash Key Register for bank1,                             Address offset: 0x04  */

+  __IO uint32_t OPTKEYR;         /*!< Flash Option Key Register,                                Address offset: 0x08  */

+  __IO uint32_t CR1;             /*!< Flash Control Register for bank1,                         Address offset: 0x0C  */

+  __IO uint32_t SR1;             /*!< Flash Status Register for bank1,                          Address offset: 0x10  */

+  __IO uint32_t CCR1;            /*!< Flash Control Register for bank1,                         Address offset: 0x14  */

+  __IO uint32_t OPTCR;           /*!< Flash Option Control Register,                            Address offset: 0x18  */

+  __IO uint32_t OPTSR_CUR;       /*!< Flash Option Status Current Register,                     Address offset: 0x1C  */

+  __IO uint32_t OPTSR_PRG;       /*!< Flash Option Status to Program Register,                  Address offset: 0x20  */

+  __IO uint32_t OPTCCR;          /*!< Flash Option Clear Control Register,                      Address offset: 0x24  */

+  __IO uint32_t PRAR_CUR1;       /*!< Flash Current Protection Address Register for bank1,      Address offset: 0x28  */

+  __IO uint32_t PRAR_PRG1;       /*!< Flash Protection Address to Program Register for bank1,   Address offset: 0x2C  */

+  __IO uint32_t SCAR_CUR1;       /*!< Flash Current Secure Address Register for bank1,          Address offset: 0x30  */

+  __IO uint32_t SCAR_PRG1;       /*!< Flash Secure Address to Program Register for bank1,       Address offset: 0x34  */

+  __IO uint32_t WPSN_CUR1;       /*!< Flash Current Write Protection Register on bank1,         Address offset: 0x38  */

+  __IO uint32_t WPSN_PRG1;       /*!< Flash Write Protection to Program Register on bank1,      Address offset: 0x3C  */

+  __IO uint32_t BOOT_CUR;        /*!< Flash Current Boot Address for Pelican Core Register,     Address offset: 0x40  */

+  __IO uint32_t BOOT_PRG;        /*!< Flash Boot Address to Program for Pelican Core Register,  Address offset: 0x44  */

+  uint32_t      RESERVED0[2];    /*!< Reserved, 0x48 to 0x4C                                                          */

+  __IO uint32_t CRCCR1;          /*!< Flash CRC Control register For Bank1 Register ,           Address offset: 0x50  */

+  __IO uint32_t CRCSADD1;        /*!< Flash CRC Start Address Register for Bank1 ,              Address offset: 0x54  */

+  __IO uint32_t CRCEADD1;        /*!< Flash CRC End Address Register for Bank1 ,                Address offset: 0x58  */

+  __IO uint32_t CRCDATA;         /*!< Flash CRC Data Register for Bank1 ,                       Address offset: 0x5C  */

+  __IO uint32_t ECC_FA1;         /*!< Flash ECC Fail Address For Bank1 Register ,               Address offset: 0x60  */

+  uint32_t      RESERVED1[40];   /*!< Reserved, 0x64 to 0x100                                                         */

+  __IO uint32_t KEYR2;           /*!< Flash Key Register for bank2,                             Address offset: 0x104 */

+  uint32_t      RESERVED2;       /*!< Reserved, 0x108                                                                 */

+  __IO uint32_t CR2;             /*!< Flash Control Register for bank2,                         Address offset: 0x10C */

+  __IO uint32_t SR2;             /*!< Flash Status Register for bank2,                          Address offset: 0x110 */

+  __IO uint32_t CCR2;            /*!< Flash Status Register for bank2,                          Address offset: 0x114 */

+  uint32_t      RESERVED3[4];    /*!< Reserved, 0x118 to 0x124                                                        */

+  __IO uint32_t PRAR_CUR2;       /*!< Flash Current Protection Address Register for bank2,      Address offset: 0x128 */

+  __IO uint32_t PRAR_PRG2;       /*!< Flash Protection Address to Program Register for bank2,   Address offset: 0x12C */

+  __IO uint32_t SCAR_CUR2;       /*!< Flash Current Secure Address Register for bank2,          Address offset: 0x130 */

+  __IO uint32_t SCAR_PRG2;       /*!< Flash Secure Address Register for bank2,                  Address offset: 0x134 */

+  __IO uint32_t WPSN_CUR2;       /*!< Flash Current Write Protection Register on bank2,         Address offset: 0x138 */

+  __IO uint32_t WPSN_PRG2;       /*!< Flash Write Protection to Program Register on bank2,      Address offset: 0x13C */

+  uint32_t      RESERVED4[4];    /*!< Reserved, 0x140 to 0x14C                                                        */

+  __IO uint32_t CRCCR2;          /*!< Flash CRC Control register For Bank2 Register ,           Address offset: 0x150 */

+  __IO uint32_t CRCSADD2;        /*!< Flash CRC Start Address Register for Bank2 ,              Address offset: 0x154 */

+  __IO uint32_t CRCEADD2;        /*!< Flash CRC End Address Register for Bank2 ,                Address offset: 0x158 */

+  __IO uint32_t CRCDATA2;        /*!< Flash CRC Data Register for Bank2 ,                       Address offset: 0x15C */

+  __IO uint32_t ECC_FA2;         /*!< Flash ECC Fail Address For Bank2 Register ,               Address offset: 0x160 */

+} FLASH_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */

+} FMC_Bank1_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank1E

+  */

+

+typedef struct

+{

+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */

+} FMC_Bank1E_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank2

+  */

+

+typedef struct

+{

+  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */

+  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */

+  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */

+  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */

+  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */

+  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */

+} FMC_Bank2_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank3

+  */

+

+typedef struct

+{

+  __IO uint32_t PCR;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */

+  __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */

+  __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */

+  __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */

+  uint32_t      RESERVED;  /*!< Reserved, 0x90                                                            */

+  __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */

+} FMC_Bank3_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank5 and 6

+  */

+

+

+typedef struct

+{

+  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */

+  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */

+  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */

+  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */

+  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */

+} FMC_Bank5_6_TypeDef;

+

+/**

+  * @brief General Purpose I/O

+  */

+

+typedef struct

+{

+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */

+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */

+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */

+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */

+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */

+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */

+  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset,               Address offset: 0x18      */

+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */

+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */

+} GPIO_TypeDef;

+

+/**

+  * @brief Operational Amplifier (OPAMP)

+  */

+

+typedef struct

+{

+  __IO uint32_t CSR;          /*!< OPAMP control/status register,                      Address offset: 0x00 */

+  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,     Address offset: 0x04 */

+  __IO uint32_t HSOTR;        /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */

+} OPAMP_TypeDef;

+

+/**

+  * @brief System configuration controller

+  */

+

+typedef struct

+{

+ uint32_t RESERVED1;           /*!< Reserved,                                           Address offset: 0x00        */

+ __IO uint32_t PMCR;           /*!< SYSCFG peripheral mode configuration register,      Address offset: 0x04        */

+ __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration registers,  Address offset: 0x08-0x14   */

+ __IO uint32_t CFGR;           /*!< SYSCFG configuration registers,                     Address offset: 0x18        */

+ uint32_t RESERVED2;           /*!< Reserved,                                           Address offset: 0x1C        */

+ __IO uint32_t CCCSR;          /*!< SYSCFG compensation cell control/status register,   Address offset: 0x20        */

+ __IO uint32_t CCVR;           /*!< SYSCFG compensation cell value register,            Address offset: 0x24        */

+ __IO uint32_t CCCR;           /*!< SYSCFG compensation cell code register,             Address offset: 0x28        */

+ __IO uint32_t PWRCR;          /*!< PWR control register,                               Address offset: 0x2C        */

+  uint32_t     RESERVED3[61];  /*!< Reserved, 0x30-0x120                                                            */

+  __IO uint32_t PKGR;          /*!< SYSCFG package register,                            Address offset: 0x124       */

+  uint32_t     RESERVED4[118]; /*!< Reserved, 0x128-0x2FC                                                           */

+ __IO uint32_t UR0;            /*!< SYSCFG user register 0,                             Address offset: 0x300       */

+ __IO uint32_t UR1;            /*!< SYSCFG user register 1,                             Address offset: 0x304       */

+ __IO uint32_t UR2;            /*!< SYSCFG user register 2,                             Address offset: 0x308       */

+ __IO uint32_t UR3;            /*!< SYSCFG user register 3,                             Address offset: 0x30C       */

+ __IO uint32_t UR4;            /*!< SYSCFG user register 4,                             Address offset: 0x310       */

+ __IO uint32_t UR5;            /*!< SYSCFG user register 5,                             Address offset: 0x314       */

+ __IO uint32_t UR6;            /*!< SYSCFG user register 6,                             Address offset: 0x318       */

+ __IO uint32_t UR7;            /*!< SYSCFG user register 7,                             Address offset: 0x31C       */

+ __IO uint32_t UR8;            /*!< SYSCFG user register 8,                             Address offset: 0x320       */

+ __IO uint32_t UR9;            /*!< SYSCFG user register 9,                             Address offset: 0x324       */

+ __IO uint32_t UR10;           /*!< SYSCFG user register 10,                            Address offset: 0x328       */

+ __IO uint32_t UR11;           /*!< SYSCFG user register 11,                            Address offset: 0x32C       */

+ __IO uint32_t UR12;           /*!< SYSCFG user register 12,                            Address offset: 0x330       */

+ __IO uint32_t UR13;           /*!< SYSCFG user register 13,                            Address offset: 0x334       */

+ __IO uint32_t UR14;           /*!< SYSCFG user register 14,                            Address offset: 0x338       */

+ __IO uint32_t UR15;           /*!< SYSCFG user register 15,                            Address offset: 0x33C       */

+ __IO uint32_t UR16;           /*!< SYSCFG user register 16,                            Address offset: 0x340       */

+ __IO uint32_t UR17;           /*!< SYSCFG user register 17,                            Address offset: 0x344       */

+

+} SYSCFG_TypeDef;

+

+/**

+  * @brief Inter-integrated Circuit Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */

+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */

+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */

+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */

+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */

+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */

+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */

+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */

+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */

+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */

+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */

+} I2C_TypeDef;

+

+/**

+  * @brief Independent WATCHDOG

+  */

+

+typedef struct

+{

+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */

+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */

+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */

+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */

+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */

+} IWDG_TypeDef;

+

+

+/**

+  * @brief JPEG Codec

+  */

+typedef struct

+{

+  __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */

+  __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */

+  __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */

+  __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */

+  __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */

+  __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */

+  __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */

+  __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */

+  uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */

+  __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */

+  __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */

+  __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */

+  uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */

+  __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */

+  __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */

+  uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */

+  __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */

+  __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */

+  __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */

+  __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */

+  __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */

+  __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */

+  __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */

+  __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */

+  uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */

+  __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0,                 Address offset: 500h-65Ch */

+  __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1,                 Address offset: 660h-7BCh */

+  __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encodor, DC Huffman table 0,                 Address offset: 7C0h-7DCh */

+  __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encodor, DC Huffman table 1,                 Address offset: 7E0h-7FCh */

+

+} JPEG_TypeDef;

+

+/**

+  * @brief LCD-TFT Display Controller

+  */

+

+typedef struct

+{

+  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04                                                       */

+  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */

+  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */

+  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */

+  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */

+  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */

+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20                                                       */

+  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */

+  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28                                                            */

+  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */

+  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30                                                            */

+  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */

+  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */

+  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */

+  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */

+  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */

+  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */

+} LTDC_TypeDef;

+

+/**

+  * @brief LCD-TFT Display layer x Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */

+  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */

+  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */

+  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */

+  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */

+  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */

+  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */

+  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */

+  uint32_t      RESERVED0[2];  /*!< Reserved */

+  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */

+  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */

+  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */

+  uint32_t      RESERVED1[3];  /*!< Reserved */

+  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */

+

+} LTDC_Layer_TypeDef;

+

+/**

+  * @brief Power Control

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;       /*!< PWR power control register 1,            Address offset: 0x00 */

+  __IO uint32_t CSR1;      /*!< PWR power control status register 1,     Address offset: 0x04 */

+  __IO uint32_t CR2;       /*!< PWR power control register 2,            Address offset: 0x08 */

+  __IO uint32_t CR3;       /*!< PWR power control register 3,            Address offset: 0x0C */

+  __IO uint32_t CPUCR;     /*!< PWR CPU control register,                Address offset: 0x10 */

+       uint32_t RESERVED0; /*!< Reserved,                                Address offset: 0x14 */

+  __IO uint32_t D3CR;      /*!< PWR D3 domain control register,          Address offset: 0x18 */

+       uint32_t RESERVED1; /*!< Reserved,                                Address offset: 0x1C */

+  __IO uint32_t WKUPCR;    /*!< PWR wakeup clear register,               Address offset: 0x20 */

+  __IO uint32_t WKUPFR;    /*!< PWR wakeup flag register,                Address offset: 0x24 */

+  __IO uint32_t WKUPEPR;   /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */

+} PWR_TypeDef;

+

+/**

+  * @brief Reset and Clock Control

+  */

+

+typedef struct

+{

+ __IO uint32_t CR;             /*!< RCC clock control register,                                              Address offset: 0x00  */

+ __IO uint32_t HSICFGR;        /*!< HSI Clock Calibration Register,                                          Address offset: 0x04  */

+ __IO uint32_t CRRCR;          /*!< Clock Recovery RC  Register,                                             Address offset: 0x08  */

+ __IO uint32_t CSICFGR;        /*!< CSI Clock Calibration Register,                                          Address offset: 0x0C  */

+ __IO uint32_t CFGR;           /*!< RCC clock configuration register,                                        Address offset: 0x10  */

+ uint32_t     RESERVED1;       /*!< Reserved,                                                                Address offset: 0x14  */

+ __IO uint32_t D1CFGR;         /*!< RCC Domain 1 configuration register,                                     Address offset: 0x18  */

+ __IO uint32_t D2CFGR;         /*!< RCC Domain 2 configuration register,                                     Address offset: 0x1C  */

+ __IO uint32_t D3CFGR;         /*!< RCC Domain 3 configuration register,                                     Address offset: 0x20  */

+ uint32_t     RESERVED2;       /*!< Reserved,                                                                Address offset: 0x24  */

+ __IO uint32_t PLLCKSELR;      /*!< RCC PLLs Clock Source Selection Register,                                Address offset: 0x28  */

+ __IO uint32_t PLLCFGR;        /*!< RCC PLLs  Configuration Register,                                        Address offset: 0x2C  */

+ __IO uint32_t PLL1DIVR;       /*!< RCC PLL1 Dividers Configuration Register,                                Address offset: 0x30  */

+ __IO uint32_t PLL1FRACR;      /*!< RCC PLL1 Fractional Divider Configuration Register,                      Address offset: 0x34  */

+ __IO uint32_t PLL2DIVR;       /*!< RCC PLL2 Dividers Configuration Register,                                Address offset: 0x38  */

+ __IO uint32_t PLL2FRACR;      /*!< RCC PLL2 Fractional Divider Configuration Register,                      Address offset: 0x3C  */

+ __IO uint32_t PLL3DIVR;       /*!< RCC PLL3 Dividers Configuration Register,                                Address offset: 0x40  */

+ __IO uint32_t PLL3FRACR;      /*!< RCC PLL3 Fractional Divider Configuration Register,                      Address offset: 0x44  */

+ uint32_t      RESERVED3;      /*!< Reserved,                                                                Address offset: 0x48  */

+ __IO uint32_t  D1CCIPR;       /*!< RCC Domain 1 Kernel Clock Configuration Register                         Address offset: 0x4C  */

+ __IO uint32_t  D2CCIP1R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x50  */

+ __IO uint32_t  D2CCIP2R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x54  */

+ __IO uint32_t  D3CCIPR;       /*!< RCC Domain 3 Kernel Clock Configuration Register                         Address offset: 0x58  */

+ uint32_t      RESERVED4;      /*!< Reserved,                                                                Address offset: 0x5C  */

+ __IO uint32_t  CIER;          /*!< RCC Clock Source Interrupt Enable Register                               Address offset: 0x60  */

+ __IO uint32_t  CIFR;          /*!< RCC Clock Source Interrupt Flag Register                                 Address offset: 0x64  */

+ __IO uint32_t  CICR;          /*!< RCC Clock Source Interrupt Clear Register                                Address offset: 0x68  */

+ uint32_t     RESERVED5;       /*!< Reserved,                                                                Address offset: 0x6C  */

+ __IO uint32_t  BDCR;          /*!< RCC Vswitch Backup Domain Control Register,                              Address offset: 0x70  */

+ __IO uint32_t  CSR;           /*!< RCC clock control & status register,                                     Address offset: 0x74  */

+ uint32_t     RESERVED6;       /*!< Reserved,                                                                Address offset: 0x78  */

+ __IO uint32_t AHB3RSTR;       /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x7C  */

+ __IO uint32_t AHB1RSTR;       /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x80  */

+ __IO uint32_t AHB2RSTR;       /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x84  */

+ __IO uint32_t AHB4RSTR;       /*!< RCC AHB4 peripheral reset register,                                      Address offset: 0x88  */

+ __IO uint32_t APB3RSTR;       /*!< RCC APB3 peripheral reset register,                                      Address offset: 0x8C  */

+ __IO uint32_t APB1LRSTR;      /*!< RCC APB1 peripheral reset Low Word register,                             Address offset: 0x90  */

+ __IO uint32_t APB1HRSTR;      /*!< RCC APB1 peripheral reset High Word register,                            Address offset: 0x94  */

+ __IO uint32_t APB2RSTR;       /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x98  */

+ __IO uint32_t APB4RSTR;       /*!< RCC APB4 peripheral reset register,                                      Address offset: 0x9C  */

+ __IO uint32_t GCR;            /*!< RCC RCC Global Control  Register,                                        Address offset: 0xA0  */

+ uint32_t     RESERVED8;       /*!< Reserved,                                                                Address offset: 0xA4  */

+ __IO uint32_t D3AMR;          /*!< RCC Domain 3 Autonomous Mode Register,                                   Address offset: 0xA8  */

+ uint32_t     RESERVED11[9];    /*!< Reserved, 0xAC-0xCC                                                      Address offset: 0xAC  */

+ __IO uint32_t RSR;            /*!< RCC Reset status register,                                               Address offset: 0xD0  */

+ __IO uint32_t AHB3ENR;        /*!< RCC AHB3 peripheral clock  register,                                     Address offset: 0xD4  */

+ __IO uint32_t AHB1ENR;        /*!< RCC AHB1 peripheral clock  register,                                     Address offset: 0xD8  */

+ __IO uint32_t AHB2ENR;        /*!< RCC AHB2 peripheral clock  register,                                     Address offset: 0xDC  */

+ __IO uint32_t AHB4ENR;        /*!< RCC AHB4 peripheral clock  register,                                     Address offset: 0xE0  */

+ __IO uint32_t APB3ENR;        /*!< RCC APB3 peripheral clock  register,                                     Address offset: 0xE4  */

+ __IO uint32_t APB1LENR;       /*!< RCC APB1 peripheral clock  Low Word register,                            Address offset: 0xE8  */

+ __IO uint32_t APB1HENR;       /*!< RCC APB1 peripheral clock  High Word register,                           Address offset: 0xEC  */

+ __IO uint32_t APB2ENR;        /*!< RCC APB2 peripheral clock  register,                                     Address offset: 0xF0  */

+ __IO uint32_t APB4ENR;        /*!< RCC APB4 peripheral clock  register,                                     Address offset: 0xF4  */

+ uint32_t      RESERVED12;      /*!< Reserved,                                                                Address offset: 0xF8  */

+ __IO uint32_t AHB3LPENR;      /*!< RCC AHB3 peripheral sleep clock  register,                               Address offset: 0xFC  */

+ __IO uint32_t AHB1LPENR;      /*!< RCC AHB1 peripheral sleep clock  register,                               Address offset: 0x100 */

+ __IO uint32_t AHB2LPENR;      /*!< RCC AHB2 peripheral sleep clock  register,                               Address offset: 0x104 */

+ __IO uint32_t AHB4LPENR;      /*!< RCC AHB4 peripheral sleep clock  register,                               Address offset: 0x108 */

+ __IO uint32_t APB3LPENR;      /*!< RCC APB3 peripheral sleep clock  register,                               Address offset: 0x10C */

+ __IO uint32_t APB1LLPENR;     /*!< RCC APB1 peripheral sleep clock  Low Word register,                      Address offset: 0x110 */

+ __IO uint32_t APB1HLPENR;     /*!< RCC APB1 peripheral sleep clock  High Word register,                     Address offset: 0x114 */

+ __IO uint32_t APB2LPENR;      /*!< RCC APB2 peripheral sleep clock  register,                               Address offset: 0x118 */

+ __IO uint32_t APB4LPENR;      /*!< RCC APB4 peripheral sleep clock  register,                               Address offset: 0x11C */

+ uint32_t     RESERVED13[4];   /*!< Reserved, 0x120-0x12C                                                    Address offset: 0x120 */

+

+} RCC_TypeDef;

+

+

+/**

+  * @brief Real-Time Clock

+  */

+typedef struct

+{

+  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */

+  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */

+  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */

+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */

+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */

+  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */

+       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */

+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */

+  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */

+  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */

+  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */

+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */

+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */

+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */

+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */

+  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */

+  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */

+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */

+  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */

+  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset: 0x4C */

+  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */

+  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */

+  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */

+  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */

+  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */

+  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */

+  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */

+  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */

+  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */

+  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */

+  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */

+  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */

+  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */

+  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */

+  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */

+  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */

+  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */

+  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */

+  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */

+  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */

+  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */

+  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */

+  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */

+  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */

+  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */

+  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */

+  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */

+  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */

+  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */

+  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */

+  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */

+  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */

+} RTC_TypeDef;

+

+/**

+  * @brief Serial Audio Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t GCR;           /*!< SAI global configuration register, Address offset: 0x00 */

+  uint32_t      RESERVED0[16]; /*!< Reserved, 0x04 - 0x43                                   */

+  __IO uint32_t PDMCR;         /*!< SAI PDM control register,          Address offset: 0x44 */

+  __IO uint32_t PDMDLY;        /*!< SAI PDM delay register,            Address offset: 0x48 */

+} SAI_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */

+  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */

+  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */

+  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */

+  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */

+  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */

+  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */

+  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */

+} SAI_Block_TypeDef;

+

+/**

+  * @brief SPDIF-RX Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */

+  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */

+  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */

+  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */

+  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */

+  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */

+  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */

+  uint32_t        RESERVED2;    /*!< Reserved,  0x1A                                          */

+} SPDIFRX_TypeDef;

+

+

+/**

+  * @brief Secure digital input/output Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t POWER;          /*!< SDMMC power control register,             Address offset: 0x00  */

+  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,             Address offset: 0x04  */

+  __IO uint32_t ARG;            /*!< SDMMC argument register,                  Address offset: 0x08  */

+  __IO uint32_t CMD;            /*!< SDMMC command register,                   Address offset: 0x0C  */

+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register,          Address offset: 0x10  */

+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                Address offset: 0x14  */

+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                Address offset: 0x18  */

+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                Address offset: 0x1C  */

+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                Address offset: 0x20  */

+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                Address offset: 0x24  */

+  __IO uint32_t DLEN;           /*!< SDMMC data length register,               Address offset: 0x28  */

+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,              Address offset: 0x2C  */

+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,              Address offset: 0x30  */

+  __I uint32_t  STA;            /*!< SDMMC status register,                    Address offset: 0x34  */

+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,           Address offset: 0x38  */

+  __IO uint32_t MASK;           /*!< SDMMC mask register,                      Address offset: 0x3C  */

+  __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,     Address offset: 0x40  */

+  uint32_t      RESERVED0[3];   /*!< Reserved, 0x44 - 0x4C - 0x4C                                    */

+  __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,               Address offset: 0x50  */

+  __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,           Address offset: 0x54  */

+  __IO uint32_t IDMABASE0;      /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58  */

+  __IO uint32_t IDMABASE1;      /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C  */

+  uint32_t      RESERVED1[8];   /*!< Reserved, 0x60-0x7C                                             */

+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,                 Address offset: 0x80  */

+  uint32_t      RESERVED2[222]; /*!< Reserved, 0x84-0x3F8                                            */

+  __IO uint32_t IPVR;           /*!< SDMMC data FIFO register,                 Address offset: 0x3FC */

+} SDMMC_TypeDef;

+

+

+/**

+  * @brief Delay Block DLYB

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;          /*!< DELAY BLOCK control register,  Address offset: 0x00 */

+  __IO uint32_t CFGR;        /*!< DELAY BLOCK configuration register,  Address offset: 0x04 */

+} DLYB_TypeDef;

+

+/**

+  * @brief HW Semaphore HSEM

+  */

+

+typedef struct

+{

+  __IO uint32_t R[32];      /*!< 2-step write lock and read back registers,     Address offset: 00h-7Ch  */

+  __IO uint32_t RLR[32];    /*!< 1-step read lock registers,                    Address offset: 80h-FCh  */

+  __IO uint32_t C1IER;      /*!< HSEM Interrupt enable register ,             Address offset: 100h     */

+  __IO uint32_t C1ICR;      /*!< HSEM Interrupt clear register ,              Address offset: 104h     */

+  __IO uint32_t C1ISR;      /*!< HSEM Interrupt Status register ,             Address offset: 108h     */

+  __IO uint32_t C1MISR;     /*!< HSEM Interrupt Masked Status register ,      Address offset: 10Ch     */

+  uint32_t  Reserved[12];   /* Reserved                                       Address offset: 110h-13Ch  */

+  __IO uint32_t CR;         /*!< HSEM Semaphore clear register ,                Address offset: 140h      */

+  __IO uint32_t KEYR;       /*!< HSEM Semaphore clear key register ,            Address offset: 144h      */

+

+} HSEM_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t IER;        /*!< HSEM interrupt enable register ,                Address offset:   0h     */

+  __IO uint32_t ICR;        /*!< HSEM interrupt clear register ,                 Address offset:   4h     */

+  __IO uint32_t ISR;        /*!< HSEM interrupt status register ,                Address offset:   8h     */

+  __IO uint32_t MISR;       /*!< HSEM masked interrupt status register ,         Address offset:   Ch     */

+} HSEM_Common_TypeDef;

+

+/**

+  * @brief Serial Peripheral Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */

+  __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */

+  __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */

+  __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */

+  __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */

+  __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */

+  __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */

+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */

+  __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */

+  uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */

+  __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */

+  uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */

+  __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */

+  __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */

+  __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */

+  __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */

+  __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */

+

+} SPI_TypeDef;

+/**

+  * @brief QUAD Serial Peripheral Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */

+  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */

+  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */

+  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */

+  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */

+  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */

+  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */

+  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */

+  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */

+  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */

+  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */

+  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */

+  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */

+} QUADSPI_TypeDef;

+

+/**

+  * @brief TIM

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */

+  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */

+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */

+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */

+  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */

+  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */

+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */

+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */

+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */

+  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */

+  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */

+  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */

+  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */

+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */

+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */

+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */

+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */

+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */

+  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */

+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */

+  uint32_t      RESERVED1;   /*!< Reserved, 0x50                                                 */

+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */

+  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */

+  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */

+  __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */

+  __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */

+  __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x68 */

+} TIM_TypeDef;

+

+/**

+  * @brief LPTIMIMER

+  */

+typedef struct

+{

+  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,         Address offset: 0x00 */

+  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,              Address offset: 0x04 */

+  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,             Address offset: 0x08 */

+  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                Address offset: 0x0C */

+  __IO uint32_t CR;       /*!< LPTIM Control register,                      Address offset: 0x10 */

+  __IO uint32_t CMP;      /*!< LPTIM Compare register,                      Address offset: 0x14 */

+  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                   Address offset: 0x18 */

+  __IO uint32_t CNT;      /*!< LPTIM Counter register,                      Address offset: 0x1C */

+  uint32_t  RESERVED1;    /*!< Reserved, 0x20                                                    */

+  __IO uint32_t CFGR2;    /*!< LPTIM Configuration register,                Address offset: 0x24 */

+} LPTIM_TypeDef;

+

+/**

+  * @brief Comparator

+  */

+typedef struct

+{

+  __IO uint32_t SR;        /*!< Comparator status register,                    Address offset: 0x00 */

+  __IO uint32_t ICFR;      /*!< Comparator interrupt clear flag register,       Address offset: 0x04 */

+  __IO uint32_t OR;        /*!< Comparator option register,                  Address offset: 0x08 */

+} COMPOPT_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CFGR;      /*!< Comparator configuration register  ,           Address offset: 0x00 */

+} COMP_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CFGR;       /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */

+} COMP_Common_TypeDef;

+/**

+  * @brief Universal Synchronous Asynchronous Receiver Transmitter

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */

+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */

+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */

+  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */

+  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */

+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */

+  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */

+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */

+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */

+  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */

+  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */

+  __IO uint32_t PRESC;  /*!< USART clock Prescaler register,           Address offset: 0x2C */

+} USART_TypeDef;

+

+/**

+  * @brief Single Wire Protocol Master Interface SPWMI

+  */

+typedef struct

+{

+  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */

+  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */

+    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */

+  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */

+  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */

+  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */

+  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */

+  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */

+  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */

+  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */

+} SWPMI_TypeDef;

+

+/**

+  * @brief Window WATCHDOG

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */

+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */

+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */

+} WWDG_TypeDef;

+

+

+/**

+  * @brief RAM_ECC_Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t CR;           /*!< RAMECC monitor configuration register          */

+  __IO uint32_t SR;           /*!< RAMECC monitor status register                 */

+  __IO uint32_t FAR;          /*!< RAMECC monitor failing address register        */

+  __IO uint32_t FDRL;         /*!< RAMECC monitor failing data low register       */

+  __IO uint32_t FDRH;         /*!< RAMECC monitor failing data high register      */

+  __IO uint32_t FECR;         /*!< RAMECC monitor failing ECC error code register */

+} RAMECC_MonitorTypeDef;

+

+typedef struct

+{

+  __IO uint32_t IER;          /*!< RAMECC interrupt enable register */

+} RAMECC_TypeDef;

+/**

+  * @}

+  */

+

+

+/**

+  * @brief Crypto Processor

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */

+  __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */

+  __IO uint32_t DIN;         /*!< CRYP data input register,                                Address offset: 0x08 */

+  __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */

+  __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */

+  __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */

+  __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */

+  __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */

+  __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */

+  __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */

+  __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */

+  __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */

+  __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */

+  __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */

+  __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */

+  __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */

+  __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */

+  __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */

+  __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */

+  __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */

+  __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */

+  __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */

+  __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */

+  __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */

+  __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */

+  __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */

+  __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */

+  __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */

+  __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */

+  __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */

+  __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */

+  __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */

+  __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */

+  __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */

+  __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */

+  __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */

+} CRYP_TypeDef;

+

+/**

+  * @brief HASH

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */

+  __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */

+  __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */

+  __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */

+  __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */

+  __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */

+       uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */

+  __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */

+} HASH_TypeDef;

+

+/**

+  * @brief HASH_DIGEST

+  */

+

+typedef struct

+{

+  __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */

+} HASH_DIGEST_TypeDef;

+

+

+/**

+  * @brief High resolution Timer (HRTIM)

+  */

+/* HRTIM master registers definition */

+typedef struct

+{

+  __IO uint32_t MCR;            /*!< HRTIM Master Timer control register,                     Address offset: 0x00 */

+  __IO uint32_t MISR;           /*!< HRTIM Master Timer interrupt status register,            Address offset: 0x04 */

+  __IO uint32_t MICR;           /*!< HRTIM Master Timer interupt clear register,              Address offset: 0x08 */

+  __IO uint32_t MDIER;          /*!< HRTIM Master Timer DMA/interrupt enable register         Address offset: 0x0C */

+  __IO uint32_t MCNTR;          /*!< HRTIM Master Timer counter register,                     Address offset: 0x10 */

+  __IO uint32_t MPER;           /*!< HRTIM Master Timer period register,                      Address offset: 0x14 */

+  __IO uint32_t MREP;           /*!< HRTIM Master Timer repetition register,                  Address offset: 0x18 */

+  __IO uint32_t MCMP1R;         /*!< HRTIM Master Timer compare 1 register,                   Address offset: 0x1C */

+  uint32_t      RESERVED0;     /*!< Reserved,                                                                 0x20 */

+  __IO uint32_t MCMP2R;         /*!< HRTIM Master Timer compare 2 register,                   Address offset: 0x24 */

+  __IO uint32_t MCMP3R;         /*!< HRTIM Master Timer compare 3 register,                   Address offset: 0x28 */

+  __IO uint32_t MCMP4R;         /*!< HRTIM Master Timer compare 4 register,                   Address offset: 0x2C */

+  uint32_t      RESERVED1[20];  /*!< Reserved,                                                          0x30..0x7C */

+}HRTIM_Master_TypeDef;

+

+/* HRTIM Timer A to E registers definition */

+typedef struct

+{

+  __IO uint32_t TIMxCR;     /*!< HRTIM Timerx control register,                              Address offset: 0x00 */

+  __IO uint32_t TIMxISR;    /*!< HRTIM Timerx interrupt status register,                     Address offset: 0x04 */

+  __IO uint32_t TIMxICR;    /*!< HRTIM Timerx interrupt clear register,                      Address offset: 0x08 */

+  __IO uint32_t TIMxDIER;   /*!< HRTIM Timerx DMA/interrupt enable register,                 Address offset: 0x0C */

+  __IO uint32_t CNTxR;      /*!< HRTIM Timerx counter register,                              Address offset: 0x10 */

+  __IO uint32_t PERxR;      /*!< HRTIM Timerx period register,                               Address offset: 0x14 */

+  __IO uint32_t REPxR;      /*!< HRTIM Timerx repetition register,                           Address offset: 0x18 */

+  __IO uint32_t CMP1xR;     /*!< HRTIM Timerx compare 1 register,                            Address offset: 0x1C */

+  __IO uint32_t CMP1CxR;    /*!< HRTIM Timerx compare 1 compound register,                   Address offset: 0x20 */

+  __IO uint32_t CMP2xR;     /*!< HRTIM Timerx compare 2 register,                            Address offset: 0x24 */

+  __IO uint32_t CMP3xR;     /*!< HRTIM Timerx compare 3 register,                            Address offset: 0x28 */

+  __IO uint32_t CMP4xR;     /*!< HRTIM Timerx compare 4 register,                            Address offset: 0x2C */

+  __IO uint32_t CPT1xR;     /*!< HRTIM Timerx capture 1 register,                            Address offset: 0x30 */

+  __IO uint32_t CPT2xR;     /*!< HRTIM Timerx capture 2 register,                            Address offset: 0x34 */

+  __IO uint32_t DTxR;       /*!< HRTIM Timerx dead time register,                            Address offset: 0x38 */

+  __IO uint32_t SETx1R;     /*!< HRTIM Timerx output 1 set register,                         Address offset: 0x3C */

+  __IO uint32_t RSTx1R;     /*!< HRTIM Timerx output 1 reset register,                       Address offset: 0x40 */

+  __IO uint32_t SETx2R;     /*!< HRTIM Timerx output 2 set register,                         Address offset: 0x44 */

+  __IO uint32_t RSTx2R;     /*!< HRTIM Timerx output 2 reset register,                       Address offset: 0x48 */

+  __IO uint32_t EEFxR1;     /*!< HRTIM Timerx external event filtering 1 register,           Address offset: 0x4C */

+  __IO uint32_t EEFxR2;     /*!< HRTIM Timerx external event filtering 2 register,           Address offset: 0x50 */

+  __IO uint32_t RSTxR;      /*!< HRTIM Timerx Reset register,                                Address offset: 0x54 */

+  __IO uint32_t CHPxR;      /*!< HRTIM Timerx Chopper register,                              Address offset: 0x58 */

+  __IO uint32_t CPT1xCR;    /*!< HRTIM Timerx Capture 1 register,                            Address offset: 0x5C */

+  __IO uint32_t CPT2xCR;    /*!< HRTIM Timerx Capture 2 register,                            Address offset: 0x60 */

+  __IO uint32_t OUTxR;      /*!< HRTIM Timerx Output register,                               Address offset: 0x64 */

+  __IO uint32_t FLTxR;      /*!< HRTIM Timerx Fault register,                                Address offset: 0x68 */

+  uint32_t      RESERVED0[5];  /*!< Reserved,                                                          0x6C..0x7C */

+}HRTIM_Timerx_TypeDef;

+

+/* HRTIM common register definition */

+typedef struct

+{

+  __IO uint32_t CR1;        /*!< HRTIM control register1,                                    Address offset: 0x00 */

+  __IO uint32_t CR2;        /*!< HRTIM control register2,                                    Address offset: 0x04 */

+  __IO uint32_t ISR;        /*!< HRTIM interrupt status register,                            Address offset: 0x08 */

+  __IO uint32_t ICR;        /*!< HRTIM interrupt clear register,                             Address offset: 0x0C */

+  __IO uint32_t IER;        /*!< HRTIM interrupt enable register,                            Address offset: 0x10 */

+  __IO uint32_t OENR;       /*!< HRTIM Output enable register,                               Address offset: 0x14 */

+  __IO uint32_t ODISR;      /*!< HRTIM Output disable register,                              Address offset: 0x18 */

+  __IO uint32_t ODSR;       /*!< HRTIM Output disable status register,                       Address offset: 0x1C */

+  __IO uint32_t BMCR;       /*!< HRTIM Burst mode control register,                          Address offset: 0x20 */

+  __IO uint32_t BMTRGR;     /*!< HRTIM Busrt mode trigger register,                          Address offset: 0x24 */

+  __IO uint32_t BMCMPR;     /*!< HRTIM Burst mode compare register,                          Address offset: 0x28 */

+  __IO uint32_t BMPER;      /*!< HRTIM Burst mode period register,                           Address offset: 0x2C */

+  __IO uint32_t EECR1;      /*!< HRTIM Timer external event control register1,               Address offset: 0x30 */

+  __IO uint32_t EECR2;      /*!< HRTIM Timer external event control register2,               Address offset: 0x34 */

+  __IO uint32_t EECR3;      /*!< HRTIM Timer external event control register3,               Address offset: 0x38 */

+  __IO uint32_t ADC1R;      /*!< HRTIM ADC Trigger 1 register,                               Address offset: 0x3C */

+  __IO uint32_t ADC2R;      /*!< HRTIM ADC Trigger 2 register,                               Address offset: 0x40 */

+  __IO uint32_t ADC3R;      /*!< HRTIM ADC Trigger 3 register,                               Address offset: 0x44 */

+  __IO uint32_t ADC4R;      /*!< HRTIM ADC Trigger 4 register,                               Address offset: 0x48 */

+  __IO uint32_t RESERVED0;  /*!< Reserved,                                                   Address offset: 0x4C */

+  __IO uint32_t FLTINR1;    /*!< HRTIM Fault input register1,                                Address offset: 0x50 */

+  __IO uint32_t FLTINR2;    /*!< HRTIM Fault input register2,                                Address offset: 0x54 */

+  __IO uint32_t BDMUPR;     /*!< HRTIM Burst DMA Master Timer update register,               Address offset: 0x58 */

+  __IO uint32_t BDTAUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x5C */

+  __IO uint32_t BDTBUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x60 */

+  __IO uint32_t BDTCUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x64 */

+  __IO uint32_t BDTDUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x68 */

+  __IO uint32_t BDTEUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x6C */

+  __IO uint32_t BDMADR;     /*!< HRTIM Burst DMA Master Data register,                       Address offset: 0x70 */

+}HRTIM_Common_TypeDef;

+

+/* HRTIM  register definition */

+typedef struct {

+  HRTIM_Master_TypeDef sMasterRegs;

+  HRTIM_Timerx_TypeDef sTimerxRegs[5];

+  uint32_t             RESERVED0[32];

+  HRTIM_Common_TypeDef sCommonRegs;

+}HRTIM_TypeDef;

+/**

+  * @brief RNG

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */

+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */

+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */

+} RNG_TypeDef;

+

+/**

+  * @brief MDIOS

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;

+  __IO uint32_t WRFR;

+  __IO uint32_t CWRFR;

+  __IO uint32_t RDFR;

+  __IO uint32_t CRDFR;

+  __IO uint32_t SR;

+  __IO uint32_t CLRFR;

+  uint32_t RESERVED[57];

+  __IO uint32_t DINR0;

+  __IO uint32_t DINR1;

+  __IO uint32_t DINR2;

+  __IO uint32_t DINR3;

+  __IO uint32_t DINR4;

+  __IO uint32_t DINR5;

+  __IO uint32_t DINR6;

+  __IO uint32_t DINR7;

+  __IO uint32_t DINR8;

+  __IO uint32_t DINR9;

+  __IO uint32_t DINR10;

+  __IO uint32_t DINR11;

+  __IO uint32_t DINR12;

+  __IO uint32_t DINR13;

+  __IO uint32_t DINR14;

+  __IO uint32_t DINR15;

+  __IO uint32_t DINR16;

+  __IO uint32_t DINR17;

+  __IO uint32_t DINR18;

+  __IO uint32_t DINR19;

+  __IO uint32_t DINR20;

+  __IO uint32_t DINR21;

+  __IO uint32_t DINR22;

+  __IO uint32_t DINR23;

+  __IO uint32_t DINR24;

+  __IO uint32_t DINR25;

+  __IO uint32_t DINR26;

+  __IO uint32_t DINR27;

+  __IO uint32_t DINR28;

+  __IO uint32_t DINR29;

+  __IO uint32_t DINR30;

+  __IO uint32_t DINR31;

+  __IO uint32_t DOUTR0;

+  __IO uint32_t DOUTR1;

+  __IO uint32_t DOUTR2;

+  __IO uint32_t DOUTR3;

+  __IO uint32_t DOUTR4;

+  __IO uint32_t DOUTR5;

+  __IO uint32_t DOUTR6;

+  __IO uint32_t DOUTR7;

+  __IO uint32_t DOUTR8;

+  __IO uint32_t DOUTR9;

+  __IO uint32_t DOUTR10;

+  __IO uint32_t DOUTR11;

+  __IO uint32_t DOUTR12;

+  __IO uint32_t DOUTR13;

+  __IO uint32_t DOUTR14;

+  __IO uint32_t DOUTR15;

+  __IO uint32_t DOUTR16;

+  __IO uint32_t DOUTR17;

+  __IO uint32_t DOUTR18;

+  __IO uint32_t DOUTR19;

+  __IO uint32_t DOUTR20;

+  __IO uint32_t DOUTR21;

+  __IO uint32_t DOUTR22;

+  __IO uint32_t DOUTR23;

+  __IO uint32_t DOUTR24;

+  __IO uint32_t DOUTR25;

+  __IO uint32_t DOUTR26;

+  __IO uint32_t DOUTR27;

+  __IO uint32_t DOUTR28;

+  __IO uint32_t DOUTR29;

+  __IO uint32_t DOUTR30;

+  __IO uint32_t DOUTR31;

+} MDIOS_TypeDef;

+

+

+/**

+  * @brief USB_OTG_Core_Registers

+  */

+typedef struct

+{

+ __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */

+  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */

+  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */

+  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */

+  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */

+  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */

+  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */

+  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */

+  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */

+  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */

+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */

+  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */

+  uint32_t Reserved30[2];             /*!< Reserved                                     030h */

+  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */

+  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */

+  __IO uint32_t GSNPSID;              /* USB_OTG core ID                                040h*/

+  __IO uint32_t GHWCFG1;              /* User HW config1                                044h*/

+  __IO uint32_t GHWCFG2;              /* User HW config2                                048h*/

+  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */

+  uint32_t  Reserved6;                /*!< Reserved                                     050h */

+  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */

+  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */

+  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */

+   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */

+    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */

+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */

+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */

+} USB_OTG_GlobalTypeDef;

+

+

+/**

+  * @brief USB_OTG_device_Registers

+  */

+typedef struct

+{

+  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */

+  __IO uint32_t DCTL;            /*!< dev Control Register         804h */

+  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */

+  uint32_t Reserved0C;           /*!< Reserved                     80Ch */

+  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */

+  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */

+  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */

+  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */

+  uint32_t  Reserved20;          /*!< Reserved                     820h */

+  uint32_t Reserved9;            /*!< Reserved                     824h */

+  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */

+  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */

+  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */

+  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */

+  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */

+  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */

+  uint32_t Reserved40;           /*!< dedicated EP mask            840h */

+  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */

+  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */

+  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */

+} USB_OTG_DeviceTypeDef;

+

+

+/**

+  * @brief USB_OTG_IN_Endpoint-Specific_Register

+  */

+typedef struct

+{

+  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */

+  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */

+  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */

+  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */

+  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */

+  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */

+  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */

+  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */

+} USB_OTG_INEndpointTypeDef;

+

+

+/**

+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */

+  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */

+  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */

+  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */

+  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */

+  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */

+  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */

+} USB_OTG_OUTEndpointTypeDef;

+

+

+/**

+  * @brief USB_OTG_Host_Mode_Register_Structures

+  */

+typedef struct

+{

+  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */

+  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */

+  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */

+  uint32_t Reserved40C;           /*!< Reserved                             40Ch */

+  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */

+  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */

+  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */

+} USB_OTG_HostTypeDef;

+

+/**

+  * @brief USB_OTG_Host_Channel_Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */

+  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */

+  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */

+  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */

+  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */

+  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */

+  uint32_t Reserved[2];           /*!< Reserved                                      */

+} USB_OTG_HostChannelTypeDef;

+/**

+  * @}

+  */

+

+

+/** @addtogroup Peripheral_memory_map

+  * @{

+  */

+#define D1_ITCMRAM_BASE           (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM  */

+#define D1_ITCMICP_BASE           (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM         */

+#define D1_DTCMRAM_BASE           (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM                            */

+#define D1_AXIFLASH_BASE          (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI                */

+#define D1_AXIICP_BASE            (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI          */

+#define D1_AXISRAM_BASE           (0x24000000UL) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI                */

+

+#define D2_AXISRAM_BASE           (0x10000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI                */

+#define D2_AHBSRAM_BASE           (0x30000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge    */

+

+#define D3_BKPSRAM_BASE           (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge                                */

+#define D3_SRAM_BASE              (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge                               */

+

+#define PERIPH_BASE               (0x40000000UL) /*!< Base address of : AHB/APB Peripherals                                                   */

+#define QSPI_BASE                 (0x90000000UL) /*!< Base address of : QSPI memories  accessible over AXI                                    */

+

+#define FLASH_BANK1_BASE          (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI                          */

+#define FLASH_BANK2_BASE          (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI                          */

+#define FLASH_END                 (0x081FFFFFUL) /*!< FLASH end address                                                                       */

+

+/* Legacy define */

+#define FLASH_BASE                FLASH_BANK1_BASE

+

+/*!< Device electronic signature memory map */

+#define UID_BASE                  (0x1FF1E800UL)            /*!< Unique device ID register base address */

+#define FLASHSIZE_BASE            (0x1FF1E880UL)            /*!< FLASH Size register base address */

+

+

+/*!< Peripheral memory map */

+#define D2_APB1PERIPH_BASE        PERIPH_BASE

+#define D2_APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)

+#define D2_AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)

+#define D2_AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)

+

+#define D1_APB1PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)

+#define D1_AHB1PERIPH_BASE       (PERIPH_BASE + 0x12000000UL)

+

+#define D3_APB1PERIPH_BASE       (PERIPH_BASE + 0x18000000UL)

+#define D3_AHB1PERIPH_BASE       (PERIPH_BASE + 0x18020000UL)

+

+/*!< Legacy Peripheral memory map */

+#define APB1PERIPH_BASE        PERIPH_BASE

+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)

+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)

+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)

+

+

+/*!< D1_AHB1PERIPH peripherals */

+

+#define MDMA_BASE             (D1_AHB1PERIPH_BASE + 0x0000UL)

+#define DMA2D_BASE            (D1_AHB1PERIPH_BASE + 0x1000UL)

+#define JPGDEC_BASE           (D1_AHB1PERIPH_BASE + 0x3000UL)

+#define FLASH_R_BASE          (D1_AHB1PERIPH_BASE + 0x2000UL)

+#define FMC_R_BASE            (D1_AHB1PERIPH_BASE + 0x4000UL)

+#define QSPI_R_BASE           (D1_AHB1PERIPH_BASE + 0x5000UL)

+#define DLYB_QSPI_BASE        (D1_AHB1PERIPH_BASE + 0x6000UL)

+#define SDMMC1_BASE           (D1_AHB1PERIPH_BASE + 0x7000UL)

+#define DLYB_SDMMC1_BASE      (D1_AHB1PERIPH_BASE + 0x8000UL)

+#define RAMECC1_BASE          (D1_AHB1PERIPH_BASE + 0x9000UL)

+

+/*!< D2_AHB1PERIPH peripherals */

+

+#define DMA1_BASE               (D2_AHB1PERIPH_BASE + 0x0000UL)

+#define DMA2_BASE               (D2_AHB1PERIPH_BASE + 0x0400UL)

+#define DMAMUX1_BASE            (D2_AHB1PERIPH_BASE + 0x0800UL)

+#define ADC1_BASE               (D2_AHB1PERIPH_BASE + 0x2000UL)

+#define ADC2_BASE               (D2_AHB1PERIPH_BASE + 0x2100UL)

+#define ADC12_COMMON_BASE       (D2_AHB1PERIPH_BASE + 0x2300UL)

+#define ETH_BASE                (D2_AHB1PERIPH_BASE + 0x8000UL)

+#define ETH_MAC_BASE            (ETH_BASE)

+

+/*!< USB registers base address */

+#define USB1_OTG_HS_PERIPH_BASE              (0x40040000UL)

+#define USB2_OTG_FS_PERIPH_BASE              (0x40080000UL)

+#define USB_OTG_GLOBAL_BASE                  (0x000UL)

+#define USB_OTG_DEVICE_BASE                  (0x800UL)

+#define USB_OTG_IN_ENDPOINT_BASE             (0x900UL)

+#define USB_OTG_OUT_ENDPOINT_BASE            (0xB00UL)

+#define USB_OTG_EP_REG_SIZE                  (0x20UL)

+#define USB_OTG_HOST_BASE                    (0x400UL)

+#define USB_OTG_HOST_PORT_BASE               (0x440UL)

+#define USB_OTG_HOST_CHANNEL_BASE            (0x500UL)

+#define USB_OTG_HOST_CHANNEL_SIZE            (0x20UL)

+#define USB_OTG_PCGCCTL_BASE                 (0xE00UL)

+#define USB_OTG_FIFO_BASE                    (0x1000UL)

+#define USB_OTG_FIFO_SIZE                    (0x1000UL)

+

+/*!< D2_AHB2PERIPH peripherals */

+

+#define DCMI_BASE              (D2_AHB2PERIPH_BASE + 0x0000UL)

+#define CRYP_BASE              (D2_AHB2PERIPH_BASE + 0x1000UL)

+#define HASH_BASE              (D2_AHB2PERIPH_BASE + 0x1400UL)

+#define HASH_DIGEST_BASE       (D2_AHB2PERIPH_BASE + 0x1710UL)

+#define RNG_BASE               (D2_AHB2PERIPH_BASE + 0x1800UL)

+#define SDMMC2_BASE            (D2_AHB2PERIPH_BASE + 0x2400UL)

+#define DLYB_SDMMC2_BASE       (D2_AHB2PERIPH_BASE + 0x2800UL)

+#define RAMECC2_BASE           (D2_AHB2PERIPH_BASE + 0x3000UL)

+

+/*!< D3_AHB1PERIPH peripherals */

+#define GPIOA_BASE            (D3_AHB1PERIPH_BASE + 0x0000UL)

+#define GPIOB_BASE            (D3_AHB1PERIPH_BASE + 0x0400UL)

+#define GPIOC_BASE            (D3_AHB1PERIPH_BASE + 0x0800UL)

+#define GPIOD_BASE            (D3_AHB1PERIPH_BASE + 0x0C00UL)

+#define GPIOE_BASE            (D3_AHB1PERIPH_BASE + 0x1000UL)

+#define GPIOF_BASE            (D3_AHB1PERIPH_BASE + 0x1400UL)

+#define GPIOG_BASE            (D3_AHB1PERIPH_BASE + 0x1800UL)

+#define GPIOH_BASE            (D3_AHB1PERIPH_BASE + 0x1C00UL)

+#define GPIOI_BASE            (D3_AHB1PERIPH_BASE + 0x2000UL)

+#define GPIOJ_BASE            (D3_AHB1PERIPH_BASE + 0x2400UL)

+#define GPIOK_BASE            (D3_AHB1PERIPH_BASE + 0x2800UL)

+#define RCC_BASE              (D3_AHB1PERIPH_BASE + 0x4400UL)

+#define PWR_BASE              (D3_AHB1PERIPH_BASE + 0x4800UL)

+#define CRC_BASE              (D3_AHB1PERIPH_BASE + 0x4C00UL)

+#define BDMA_BASE             (D3_AHB1PERIPH_BASE + 0x5400UL)

+#define DMAMUX2_BASE          (D3_AHB1PERIPH_BASE + 0x5800UL)

+#define ADC3_BASE             (D3_AHB1PERIPH_BASE + 0x6000UL)

+#define ADC3_COMMON_BASE      (D3_AHB1PERIPH_BASE + 0x6300UL)

+#define HSEM_BASE             (D3_AHB1PERIPH_BASE + 0x6400UL)

+#define RAMECC3_BASE          (D3_AHB1PERIPH_BASE + 0x7000UL)

+

+/*!< D1_APB1PERIPH peripherals */

+#define LTDC_BASE             (D1_APB1PERIPH_BASE + 0x1000UL)

+#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84UL)

+#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104UL)

+#define WWDG1_BASE            (D1_APB1PERIPH_BASE + 0x3000UL)

+

+/*!< D2_APB1PERIPH peripherals */

+#define TIM2_BASE             (D2_APB1PERIPH_BASE + 0x0000UL)

+#define TIM3_BASE             (D2_APB1PERIPH_BASE + 0x0400UL)

+#define TIM4_BASE             (D2_APB1PERIPH_BASE + 0x0800UL)

+#define TIM5_BASE             (D2_APB1PERIPH_BASE + 0x0C00UL)

+#define TIM6_BASE             (D2_APB1PERIPH_BASE + 0x1000UL)

+#define TIM7_BASE             (D2_APB1PERIPH_BASE + 0x1400UL)

+#define TIM12_BASE            (D2_APB1PERIPH_BASE + 0x1800UL)

+#define TIM13_BASE            (D2_APB1PERIPH_BASE + 0x1C00UL)

+#define TIM14_BASE            (D2_APB1PERIPH_BASE + 0x2000UL)

+#define LPTIM1_BASE           (D2_APB1PERIPH_BASE + 0x2400UL)

+

+

+#define SPI2_BASE             (D2_APB1PERIPH_BASE + 0x3800UL)

+#define SPI3_BASE             (D2_APB1PERIPH_BASE + 0x3C00UL)

+#define SPDIFRX_BASE          (D2_APB1PERIPH_BASE + 0x4000UL)

+#define USART2_BASE           (D2_APB1PERIPH_BASE + 0x4400UL)

+#define USART3_BASE           (D2_APB1PERIPH_BASE + 0x4800UL)

+#define UART4_BASE            (D2_APB1PERIPH_BASE + 0x4C00UL)

+#define UART5_BASE            (D2_APB1PERIPH_BASE + 0x5000UL)

+#define I2C1_BASE             (D2_APB1PERIPH_BASE + 0x5400UL)

+#define I2C2_BASE             (D2_APB1PERIPH_BASE + 0x5800UL)

+#define I2C3_BASE             (D2_APB1PERIPH_BASE + 0x5C00UL)

+#define CEC_BASE              (D2_APB1PERIPH_BASE + 0x6C00UL)

+#define DAC1_BASE             (D2_APB1PERIPH_BASE + 0x7400UL)

+#define UART7_BASE            (D2_APB1PERIPH_BASE + 0x7800UL)

+#define UART8_BASE            (D2_APB1PERIPH_BASE + 0x7C00UL)

+#define CRS_BASE              (D2_APB1PERIPH_BASE + 0x8400UL)

+#define SWPMI1_BASE           (D2_APB1PERIPH_BASE + 0x8800UL)

+#define OPAMP_BASE            (D2_APB1PERIPH_BASE + 0x9000UL)

+#define OPAMP1_BASE           (D2_APB1PERIPH_BASE + 0x9000UL)

+#define OPAMP2_BASE           (D2_APB1PERIPH_BASE + 0x9010UL)

+#define MDIOS_BASE            (D2_APB1PERIPH_BASE + 0x9400UL)

+#define FDCAN1_BASE           (D2_APB1PERIPH_BASE + 0xA000UL)

+#define FDCAN2_BASE           (D2_APB1PERIPH_BASE + 0xA400UL)

+#define FDCAN_CCU_BASE        (D2_APB1PERIPH_BASE + 0xA800UL)

+#define SRAMCAN_BASE          (D2_APB1PERIPH_BASE + 0xAC00UL)

+

+/*!< D2_APB2PERIPH peripherals */

+

+#define TIM1_BASE             (D2_APB2PERIPH_BASE + 0x0000UL)

+#define TIM8_BASE             (D2_APB2PERIPH_BASE + 0x0400UL)

+#define USART1_BASE           (D2_APB2PERIPH_BASE + 0x1000UL)

+#define USART6_BASE           (D2_APB2PERIPH_BASE + 0x1400UL)

+#define SPI1_BASE             (D2_APB2PERIPH_BASE + 0x3000UL)

+#define SPI4_BASE             (D2_APB2PERIPH_BASE + 0x3400UL)

+#define TIM15_BASE            (D2_APB2PERIPH_BASE + 0x4000UL)

+#define TIM16_BASE            (D2_APB2PERIPH_BASE + 0x4400UL)

+#define TIM17_BASE            (D2_APB2PERIPH_BASE + 0x4800UL)

+#define SPI5_BASE             (D2_APB2PERIPH_BASE + 0x5000UL)

+#define SAI1_BASE             (D2_APB2PERIPH_BASE + 0x5800UL)

+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)

+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)

+#define SAI2_BASE             (D2_APB2PERIPH_BASE + 0x5C00UL)

+#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004UL)

+#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024UL)

+#define SAI3_BASE             (D2_APB2PERIPH_BASE + 0x6000UL)

+#define SAI3_Block_A_BASE     (SAI3_BASE + 0x004UL)

+#define SAI3_Block_B_BASE     (SAI3_BASE + 0x024UL)

+#define DFSDM1_BASE           (D2_APB2PERIPH_BASE + 0x7000UL)

+#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00UL)

+#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20UL)

+#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40UL)

+#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60UL)

+#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80UL)

+#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0UL)

+#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0UL)

+#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0UL)

+#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)

+#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)

+#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)

+#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)

+#define HRTIM1_BASE           (D2_APB2PERIPH_BASE + 0x7400UL)

+#define HRTIM1_TIMA_BASE      (HRTIM1_BASE + 0x00000080UL)

+#define HRTIM1_TIMB_BASE      (HRTIM1_BASE + 0x00000100UL)

+#define HRTIM1_TIMC_BASE      (HRTIM1_BASE + 0x00000180UL)

+#define HRTIM1_TIMD_BASE      (HRTIM1_BASE + 0x00000200UL)

+#define HRTIM1_TIME_BASE      (HRTIM1_BASE + 0x00000280UL)

+#define HRTIM1_COMMON_BASE    (HRTIM1_BASE + 0x00000380UL)

+

+

+/*!< D3_APB1PERIPH peripherals */

+#define EXTI_BASE             (D3_APB1PERIPH_BASE + 0x0000UL)

+#define EXTI_D1_BASE          (EXTI_BASE + 0x0080UL)

+#define EXTI_D2_BASE          (EXTI_BASE + 0x00C0UL)

+#define SYSCFG_BASE           (D3_APB1PERIPH_BASE + 0x0400UL)

+#define LPUART1_BASE          (D3_APB1PERIPH_BASE + 0x0C00UL)

+#define SPI6_BASE             (D3_APB1PERIPH_BASE + 0x1400UL)

+#define I2C4_BASE             (D3_APB1PERIPH_BASE + 0x1C00UL)

+#define LPTIM2_BASE           (D3_APB1PERIPH_BASE + 0x2400UL)

+#define LPTIM3_BASE           (D3_APB1PERIPH_BASE + 0x2800UL)

+#define LPTIM4_BASE           (D3_APB1PERIPH_BASE + 0x2C00UL)

+#define LPTIM5_BASE           (D3_APB1PERIPH_BASE + 0x3000UL)

+#define COMP12_BASE           (D3_APB1PERIPH_BASE + 0x3800UL)

+#define COMP1_BASE            (COMP12_BASE + 0x0CUL)

+#define COMP2_BASE            (COMP12_BASE + 0x10UL)

+#define VREFBUF_BASE          (D3_APB1PERIPH_BASE + 0x3C00UL)

+#define RTC_BASE              (D3_APB1PERIPH_BASE + 0x4000UL)

+#define IWDG1_BASE            (D3_APB1PERIPH_BASE + 0x4800UL)

+

+

+#define SAI4_BASE             (D3_APB1PERIPH_BASE + 0x5400UL)

+#define SAI4_Block_A_BASE     (SAI4_BASE + 0x004UL)

+#define SAI4_Block_B_BASE     (SAI4_BASE + 0x024UL)

+

+

+

+

+#define BDMA_Channel0_BASE    (BDMA_BASE + 0x0008UL)

+#define BDMA_Channel1_BASE    (BDMA_BASE + 0x001CUL)

+#define BDMA_Channel2_BASE    (BDMA_BASE + 0x0030UL)

+#define BDMA_Channel3_BASE    (BDMA_BASE + 0x0044UL)

+#define BDMA_Channel4_BASE    (BDMA_BASE + 0x0058UL)

+#define BDMA_Channel5_BASE    (BDMA_BASE + 0x006CUL)

+#define BDMA_Channel6_BASE    (BDMA_BASE + 0x0080UL)

+#define BDMA_Channel7_BASE    (BDMA_BASE + 0x0094UL)

+

+#define DMAMUX2_Channel0_BASE    (DMAMUX2_BASE)

+#define DMAMUX2_Channel1_BASE    (DMAMUX2_BASE + 0x0004UL)

+#define DMAMUX2_Channel2_BASE    (DMAMUX2_BASE + 0x0008UL)

+#define DMAMUX2_Channel3_BASE    (DMAMUX2_BASE + 0x000CUL)

+#define DMAMUX2_Channel4_BASE    (DMAMUX2_BASE + 0x0010UL)

+#define DMAMUX2_Channel5_BASE    (DMAMUX2_BASE + 0x0014UL)

+#define DMAMUX2_Channel6_BASE    (DMAMUX2_BASE + 0x0018UL)

+#define DMAMUX2_Channel7_BASE    (DMAMUX2_BASE + 0x001CUL)

+

+#define DMAMUX2_RequestGenerator0_BASE  (DMAMUX2_BASE + 0x0100UL)

+#define DMAMUX2_RequestGenerator1_BASE  (DMAMUX2_BASE + 0x0104UL)

+#define DMAMUX2_RequestGenerator2_BASE  (DMAMUX2_BASE + 0x0108UL)

+#define DMAMUX2_RequestGenerator3_BASE  (DMAMUX2_BASE + 0x010CUL)

+#define DMAMUX2_RequestGenerator4_BASE  (DMAMUX2_BASE + 0x0110UL)

+#define DMAMUX2_RequestGenerator5_BASE  (DMAMUX2_BASE + 0x0114UL)

+#define DMAMUX2_RequestGenerator6_BASE  (DMAMUX2_BASE + 0x0118UL)

+#define DMAMUX2_RequestGenerator7_BASE  (DMAMUX2_BASE + 0x011CUL)

+

+#define DMAMUX2_ChannelStatus_BASE      (DMAMUX2_BASE + 0x0080UL)

+#define DMAMUX2_RequestGenStatus_BASE   (DMAMUX2_BASE + 0x0140UL)

+

+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)

+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)

+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)

+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)

+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)

+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)

+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)

+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)

+

+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)

+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)

+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)

+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)

+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)

+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)

+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)

+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)

+

+#define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)

+#define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)

+#define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)

+#define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)

+#define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)

+#define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)

+#define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0018UL)

+#define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x001CUL)

+#define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0020UL)

+#define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x0024UL)

+#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)

+#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)

+#define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)

+#define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)

+#define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)

+#define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)

+

+#define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)

+#define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)

+#define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)

+#define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)

+#define DMAMUX1_RequestGenerator4_BASE  (DMAMUX1_BASE + 0x0110UL)

+#define DMAMUX1_RequestGenerator5_BASE  (DMAMUX1_BASE + 0x0114UL)

+#define DMAMUX1_RequestGenerator6_BASE  (DMAMUX1_BASE + 0x0118UL)

+#define DMAMUX1_RequestGenerator7_BASE  (DMAMUX1_BASE + 0x011CUL)

+

+#define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)

+#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)

+

+/*!< FMC Banks registers base  address */

+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)

+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)

+#define FMC_Bank2_R_BASE      (FMC_R_BASE + 0x0060UL)

+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)

+#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)

+

+/* Debug MCU registers base address */

+#define DBGMCU_BASE           (0x5C001000UL)

+

+#define MDMA_Channel0_BASE    (MDMA_BASE + 0x00000040UL)

+#define MDMA_Channel1_BASE    (MDMA_BASE + 0x00000080UL)

+#define MDMA_Channel2_BASE    (MDMA_BASE + 0x000000C0UL)

+#define MDMA_Channel3_BASE    (MDMA_BASE + 0x00000100UL)

+#define MDMA_Channel4_BASE    (MDMA_BASE + 0x00000140UL)

+#define MDMA_Channel5_BASE    (MDMA_BASE + 0x00000180UL)

+#define MDMA_Channel6_BASE    (MDMA_BASE + 0x000001C0UL)

+#define MDMA_Channel7_BASE    (MDMA_BASE + 0x00000200UL)

+#define MDMA_Channel8_BASE    (MDMA_BASE + 0x00000240UL)

+#define MDMA_Channel9_BASE    (MDMA_BASE + 0x00000280UL)

+#define MDMA_Channel10_BASE   (MDMA_BASE + 0x000002C0UL)

+#define MDMA_Channel11_BASE   (MDMA_BASE + 0x00000300UL)

+#define MDMA_Channel12_BASE   (MDMA_BASE + 0x00000340UL)

+#define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)

+#define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)

+#define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)

+

+#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)

+#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)

+#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)

+#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)

+#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)

+

+#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)

+#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)

+#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)

+#define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL)

+#define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL)

+

+#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)

+#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)

+

+

+/**

+  * @}

+  */

+

+/** @addtogroup Peripheral_declaration

+  * @{

+  */

+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)

+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)

+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)

+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)

+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)

+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)

+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)

+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)

+#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)

+#define RTC                 ((RTC_TypeDef *) RTC_BASE)

+#define WWDG1               ((WWDG_TypeDef *) WWDG1_BASE)

+

+

+#define IWDG1               ((IWDG_TypeDef *) IWDG1_BASE)

+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)

+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)

+#define SPI4                ((SPI_TypeDef *) SPI4_BASE)

+#define SPI5                ((SPI_TypeDef *) SPI5_BASE)

+#define SPI6                ((SPI_TypeDef *) SPI6_BASE)

+#define USART2              ((USART_TypeDef *) USART2_BASE)

+#define USART3              ((USART_TypeDef *) USART3_BASE)

+#define USART6              ((USART_TypeDef *) USART6_BASE)

+#define UART7               ((USART_TypeDef *) UART7_BASE)

+#define UART8               ((USART_TypeDef *) UART8_BASE)

+#define CRS                 ((CRS_TypeDef *) CRS_BASE)

+#define UART4               ((USART_TypeDef *) UART4_BASE)

+#define UART5               ((USART_TypeDef *) UART5_BASE)

+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)

+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)

+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)

+#define I2C4                ((I2C_TypeDef *) I2C4_BASE)

+#define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

+#define FDCAN2              ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

+#define FDCAN_CCU           ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

+#define CEC                 ((CEC_TypeDef *) CEC_BASE)

+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)

+#define PWR                 ((PWR_TypeDef *) PWR_BASE)

+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)

+#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)

+#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)

+#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)

+#define LPTIM3              ((LPTIM_TypeDef *) LPTIM3_BASE)

+#define LPTIM4              ((LPTIM_TypeDef *) LPTIM4_BASE)

+#define LPTIM5              ((LPTIM_TypeDef *) LPTIM5_BASE)

+

+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)

+#define COMP12              ((COMPOPT_TypeDef *) COMP12_BASE)

+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)

+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)

+#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)

+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)

+#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)

+#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)

+

+

+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)

+#define EXTI_D1             ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

+#define EXTI_D2             ((EXTI_Core_TypeDef *) EXTI_D2_BASE)

+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)

+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)

+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)

+#define USART1              ((USART_TypeDef *) USART1_BASE)

+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)

+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)

+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)

+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)

+#define HRTIM1              ((HRTIM_TypeDef *) HRTIM1_BASE)

+#define HRTIM1_TIMA         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)

+#define HRTIM1_TIMB         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)

+#define HRTIM1_TIMC         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)

+#define HRTIM1_TIMD         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)

+#define HRTIM1_TIME         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)

+#define HRTIM1_COMMON       ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)

+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)

+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

+#define SAI2                ((SAI_TypeDef *) SAI2_BASE)

+#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)

+#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)

+#define SAI3                ((SAI_TypeDef *) SAI3_BASE)

+#define SAI3_Block_A        ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)

+#define SAI3_Block_B        ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)

+#define SAI4                ((SAI_TypeDef *) SAI4_BASE)

+#define SAI4_Block_A        ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)

+#define SAI4_Block_B        ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)

+

+#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

+#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

+#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

+#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

+#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

+#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

+#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

+#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

+#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

+#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

+#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

+#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

+#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

+#define DMA2D               ((DMA2D_TypeDef *) DMA2D_BASE)

+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)

+#define RCC                 ((RCC_TypeDef *) RCC_BASE)

+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)

+#define CRC                 ((CRC_TypeDef *) CRC_BASE)

+

+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)

+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)

+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)

+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)

+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)

+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)

+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)

+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)

+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)

+#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)

+#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)

+

+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)

+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)

+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)

+#define ADC3_COMMON         ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)

+#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

+

+#define CRYP                ((CRYP_TypeDef *) CRYP_BASE)

+#define HASH                ((HASH_TypeDef *) HASH_BASE)

+#define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)

+#define RNG                 ((RNG_TypeDef *) RNG_BASE)

+#define SDMMC2              ((SDMMC_TypeDef *) SDMMC2_BASE)

+#define DLYB_SDMMC2         ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

+

+#define BDMA                ((BDMA_TypeDef *) BDMA_BASE)

+#define BDMA_Channel0       ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)

+#define BDMA_Channel1       ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)

+#define BDMA_Channel2       ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)

+#define BDMA_Channel3       ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)

+#define BDMA_Channel4       ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)

+#define BDMA_Channel5       ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)

+#define BDMA_Channel6       ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)

+#define BDMA_Channel7       ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)

+

+#define RAMECC1              ((RAMECC_TypeDef *)RAMECC1_BASE)

+#define RAMECC1_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)

+#define RAMECC1_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)

+#define RAMECC1_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)

+#define RAMECC1_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)

+#define RAMECC1_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)

+

+#define RAMECC2              ((RAMECC_TypeDef *)RAMECC2_BASE)

+#define RAMECC2_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)

+#define RAMECC2_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)

+#define RAMECC2_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)

+#define RAMECC2_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)

+#define RAMECC2_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)

+

+#define RAMECC3              ((RAMECC_TypeDef *)RAMECC3_BASE)

+#define RAMECC3_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)

+#define RAMECC3_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)

+

+#define DMAMUX2                ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

+#define DMAMUX2_Channel0       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

+#define DMAMUX2_Channel1       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

+#define DMAMUX2_Channel2       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

+#define DMAMUX2_Channel3       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

+#define DMAMUX2_Channel4       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

+#define DMAMUX2_Channel5       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

+#define DMAMUX2_Channel6       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

+#define DMAMUX2_Channel7       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

+

+

+#define DMAMUX2_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

+#define DMAMUX2_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

+#define DMAMUX2_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

+#define DMAMUX2_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

+#define DMAMUX2_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

+#define DMAMUX2_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

+#define DMAMUX2_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

+#define DMAMUX2_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

+

+#define DMAMUX2_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

+#define DMAMUX2_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

+

+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)

+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

+

+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)

+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

+

+

+#define DMAMUX1              ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

+#define DMAMUX1_Channel0     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

+#define DMAMUX1_Channel1     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

+#define DMAMUX1_Channel2     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

+#define DMAMUX1_Channel3     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

+#define DMAMUX1_Channel4     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

+#define DMAMUX1_Channel5     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

+#define DMAMUX1_Channel6     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

+#define DMAMUX1_Channel7     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

+#define DMAMUX1_Channel8     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

+#define DMAMUX1_Channel9     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

+#define DMAMUX1_Channel10    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

+#define DMAMUX1_Channel11    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

+#define DMAMUX1_Channel12    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

+#define DMAMUX1_Channel13    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

+#define DMAMUX1_Channel14    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

+#define DMAMUX1_Channel15    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

+

+#define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

+#define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

+#define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

+#define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

+#define DMAMUX1_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

+#define DMAMUX1_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

+#define DMAMUX1_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

+#define DMAMUX1_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

+

+#define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *)    DMAMUX1_ChannelStatus_BASE)

+#define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

+

+

+#define FMC_Bank1_R           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

+#define FMC_Bank1E_R          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

+#define FMC_Bank2_R           ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

+#define FMC_Bank3_R           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

+#define FMC_Bank5_6_R         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

+

+

+#define QUADSPI               ((QUADSPI_TypeDef *) QSPI_R_BASE)

+#define DLYB_QUADSPI          ((DLYB_TypeDef *) DLYB_QSPI_BASE)

+#define SDMMC1                ((SDMMC_TypeDef *) SDMMC1_BASE)

+#define DLYB_SDMMC1           ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

+

+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)

+

+#define JPEG                ((JPEG_TypeDef *) JPGDEC_BASE)

+#define HSEM                ((HSEM_TypeDef *) HSEM_BASE)

+#define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

+

+#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)

+#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

+#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

+

+#define MDIOS               ((MDIOS_TypeDef *) MDIOS_BASE)

+

+#define ETH                 ((ETH_TypeDef *)ETH_BASE)

+#define MDMA                ((MDMA_TypeDef *)MDMA_BASE)

+#define MDMA_Channel0       ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

+#define MDMA_Channel1       ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

+#define MDMA_Channel2       ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

+#define MDMA_Channel3       ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

+#define MDMA_Channel4       ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

+#define MDMA_Channel5       ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

+#define MDMA_Channel6       ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

+#define MDMA_Channel7       ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

+#define MDMA_Channel8       ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

+#define MDMA_Channel9       ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

+#define MDMA_Channel10      ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

+#define MDMA_Channel11      ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

+#define MDMA_Channel12      ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

+#define MDMA_Channel13      ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

+#define MDMA_Channel14      ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

+#define MDMA_Channel15      ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

+

+

+#define USB1_OTG_HS         ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

+#define USB2_OTG_FS         ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)

+

+/* Legacy defines */

+#define USB_OTG_HS                   USB1_OTG_HS

+#define USB_OTG_HS_PERIPH_BASE       USB1_OTG_HS_PERIPH_BASE

+#define USB_OTG_FS                   USB2_OTG_FS

+#define USB_OTG_FS_PERIPH_BASE       USB2_OTG_FS_PERIPH_BASE

+

+/**

+  * @}

+  */

+

+/** @addtogroup Exported_constants

+  * @{

+  */

+

+  /** @addtogroup Peripheral_Registers_Bits_Definition

+  * @{

+  */

+

+/******************************************************************************/

+/*                         Peripheral Registers_Bits_Definition               */

+/******************************************************************************/

+

+/******************************************************************************/

+/*                                                                            */

+/*                        Analog to Digital Converter                         */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  ADC VERSION  ********************************/

+#define ADC_VER_V5_X

+/********************  Bit definition for ADC_ISR register  ********************/

+#define ADC_ISR_ADRDY_Pos                 (0U)

+#define ADC_ISR_ADRDY_Msk                 (0x1UL << ADC_ISR_ADRDY_Pos)         /*!< 0x00000001 */

+#define ADC_ISR_ADRDY                     ADC_ISR_ADRDY_Msk                    /*!< ADC Ready (ADRDY) flag  */

+#define ADC_ISR_EOSMP_Pos                 (1U)

+#define ADC_ISR_EOSMP_Msk                 (0x1UL << ADC_ISR_EOSMP_Pos)         /*!< 0x00000002 */

+#define ADC_ISR_EOSMP                     ADC_ISR_EOSMP_Msk                    /*!< ADC End of Sampling flag */

+#define ADC_ISR_EOC_Pos                   (2U)

+#define ADC_ISR_EOC_Msk                   (0x1UL << ADC_ISR_EOC_Pos)           /*!< 0x00000004 */

+#define ADC_ISR_EOC                       ADC_ISR_EOC_Msk                      /*!< ADC End of Regular Conversion flag */

+#define ADC_ISR_EOS_Pos                   (3U)

+#define ADC_ISR_EOS_Msk                   (0x1UL << ADC_ISR_EOS_Pos)           /*!< 0x00000008 */

+#define ADC_ISR_EOS                       ADC_ISR_EOS_Msk                      /*!< ADC End of Regular sequence of Conversions flag */

+#define ADC_ISR_OVR_Pos                   (4U)

+#define ADC_ISR_OVR_Msk                   (0x1UL << ADC_ISR_OVR_Pos)           /*!< 0x00000010 */

+#define ADC_ISR_OVR                       ADC_ISR_OVR_Msk                      /*!< ADC overrun flag */

+#define ADC_ISR_JEOC_Pos                  (5U)

+#define ADC_ISR_JEOC_Msk                  (0x1UL << ADC_ISR_JEOC_Pos)          /*!< 0x00000020 */

+#define ADC_ISR_JEOC                      ADC_ISR_JEOC_Msk                     /*!< ADC End of Injected Conversion flag */

+#define ADC_ISR_JEOS_Pos                  (6U)

+#define ADC_ISR_JEOS_Msk                  (0x1UL << ADC_ISR_JEOS_Pos)          /*!< 0x00000040 */

+#define ADC_ISR_JEOS                      ADC_ISR_JEOS_Msk                     /*!< ADC End of Injected sequence of Conversions flag */

+#define ADC_ISR_AWD1_Pos                  (7U)

+#define ADC_ISR_AWD1_Msk                  (0x1UL << ADC_ISR_AWD1_Pos)          /*!< 0x00000080 */

+#define ADC_ISR_AWD1                      ADC_ISR_AWD1_Msk                     /*!< ADC Analog watchdog 1 flag */

+#define ADC_ISR_AWD2_Pos                  (8U)

+#define ADC_ISR_AWD2_Msk                  (0x1UL << ADC_ISR_AWD2_Pos)          /*!< 0x00000100 */

+#define ADC_ISR_AWD2                      ADC_ISR_AWD2_Msk                     /*!< ADC Analog watchdog 2 flag */

+#define ADC_ISR_AWD3_Pos                  (9U)

+#define ADC_ISR_AWD3_Msk                  (0x1UL << ADC_ISR_AWD3_Pos)          /*!< 0x00000200 */

+#define ADC_ISR_AWD3                      ADC_ISR_AWD3_Msk                     /*!< ADC Analog watchdog 3 flag */

+#define ADC_ISR_JQOVF_Pos                 (10U)

+#define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */

+#define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */

+

+/********************  Bit definition for ADC_IER register  ********************/

+#define ADC_IER_ADRDYIE_Pos               (0U)

+#define ADC_IER_ADRDYIE_Msk               (0x1UL << ADC_IER_ADRDYIE_Pos)       /*!< 0x00000001 */

+#define ADC_IER_ADRDYIE                   ADC_IER_ADRDYIE_Msk                  /*!< ADC Ready (ADRDY) interrupt source */

+#define ADC_IER_EOSMPIE_Pos               (1U)

+#define ADC_IER_EOSMPIE_Msk               (0x1UL << ADC_IER_EOSMPIE_Pos)       /*!< 0x00000002 */

+#define ADC_IER_EOSMPIE                   ADC_IER_EOSMPIE_Msk                  /*!< ADC End of Sampling interrupt source */

+#define ADC_IER_EOCIE_Pos                 (2U)

+#define ADC_IER_EOCIE_Msk                 (0x1UL << ADC_IER_EOCIE_Pos)         /*!< 0x00000004 */

+#define ADC_IER_EOCIE                     ADC_IER_EOCIE_Msk                    /*!< ADC End of Regular Conversion interrupt source */

+#define ADC_IER_EOSIE_Pos                 (3U)

+#define ADC_IER_EOSIE_Msk                 (0x1UL << ADC_IER_EOSIE_Pos)         /*!< 0x00000008 */

+#define ADC_IER_EOSIE                     ADC_IER_EOSIE_Msk                    /*!< ADC End of Regular sequence of Conversions interrupt source */

+#define ADC_IER_OVRIE_Pos                 (4U)

+#define ADC_IER_OVRIE_Msk                 (0x1UL << ADC_IER_OVRIE_Pos)         /*!< 0x00000010 */

+#define ADC_IER_OVRIE                     ADC_IER_OVRIE_Msk                    /*!< ADC overrun interrupt source */

+#define ADC_IER_JEOCIE_Pos                (5U)

+#define ADC_IER_JEOCIE_Msk                (0x1UL << ADC_IER_JEOCIE_Pos)        /*!< 0x00000020 */

+#define ADC_IER_JEOCIE                    ADC_IER_JEOCIE_Msk                   /*!< ADC End of Injected Conversion interrupt source */

+#define ADC_IER_JEOSIE_Pos                (6U)

+#define ADC_IER_JEOSIE_Msk                (0x1UL << ADC_IER_JEOSIE_Pos)        /*!< 0x00000040 */

+#define ADC_IER_JEOSIE                    ADC_IER_JEOSIE_Msk                   /*!< ADC End of Injected sequence of Conversions interrupt source */

+#define ADC_IER_AWD1IE_Pos                (7U)

+#define ADC_IER_AWD1IE_Msk                (0x1UL << ADC_IER_AWD1IE_Pos)        /*!< 0x00000080 */

+#define ADC_IER_AWD1IE                    ADC_IER_AWD1IE_Msk                   /*!< ADC Analog watchdog 1 interrupt source */

+#define ADC_IER_AWD2IE_Pos                (8U)

+#define ADC_IER_AWD2IE_Msk                (0x1UL << ADC_IER_AWD2IE_Pos)        /*!< 0x00000100 */

+#define ADC_IER_AWD2IE                    ADC_IER_AWD2IE_Msk                   /*!< ADC Analog watchdog 2 interrupt source */

+#define ADC_IER_AWD3IE_Pos                (9U)

+#define ADC_IER_AWD3IE_Msk                (0x1UL << ADC_IER_AWD3IE_Pos)        /*!< 0x00000200 */

+#define ADC_IER_AWD3IE                    ADC_IER_AWD3IE_Msk                   /*!< ADC Analog watchdog 3 interrupt source */

+#define ADC_IER_JQOVFIE_Pos               (10U)

+#define ADC_IER_JQOVFIE_Msk               (0x1UL << ADC_IER_JQOVFIE_Pos)       /*!< 0x00000400 */

+#define ADC_IER_JQOVFIE                   ADC_IER_JQOVFIE_Msk                  /*!< ADC Injected Context Queue Overflow interrupt source */

+

+/********************  Bit definition for ADC_CR register  ********************/

+#define ADC_CR_ADEN_Pos                   (0U)

+#define ADC_CR_ADEN_Msk                   (0x1UL << ADC_CR_ADEN_Pos)           /*!< 0x00000001 */

+#define ADC_CR_ADEN                       ADC_CR_ADEN_Msk                      /*!< ADC Enable control */

+#define ADC_CR_ADDIS_Pos                  (1U)

+#define ADC_CR_ADDIS_Msk                  (0x1UL << ADC_CR_ADDIS_Pos)          /*!< 0x00000002 */

+#define ADC_CR_ADDIS                      ADC_CR_ADDIS_Msk                     /*!< ADC Disable command */

+#define ADC_CR_ADSTART_Pos                (2U)

+#define ADC_CR_ADSTART_Msk                (0x1UL << ADC_CR_ADSTART_Pos)        /*!< 0x00000004 */

+#define ADC_CR_ADSTART                    ADC_CR_ADSTART_Msk                   /*!< ADC Start of Regular conversion */

+#define ADC_CR_JADSTART_Pos               (3U)

+#define ADC_CR_JADSTART_Msk               (0x1UL << ADC_CR_JADSTART_Pos)       /*!< 0x00000008 */

+#define ADC_CR_JADSTART                   ADC_CR_JADSTART_Msk                  /*!< ADC Start of injected conversion */

+#define ADC_CR_ADSTP_Pos                  (4U)

+#define ADC_CR_ADSTP_Msk                  (0x1UL << ADC_CR_ADSTP_Pos)          /*!< 0x00000010 */

+#define ADC_CR_ADSTP                      ADC_CR_ADSTP_Msk                     /*!< ADC Stop of Regular conversion */

+#define ADC_CR_JADSTP_Pos                 (5U)

+#define ADC_CR_JADSTP_Msk                 (0x1UL << ADC_CR_JADSTP_Pos)         /*!< 0x00000020 */

+#define ADC_CR_JADSTP                     ADC_CR_JADSTP_Msk                    /*!< ADC Stop of injected conversion */

+#define ADC_CR_BOOST_Pos                  (8U)

+#define ADC_CR_BOOST_Msk                  (0x3UL << ADC_CR_BOOST_Pos)          /*!< 0x00000300 */

+#define ADC_CR_BOOST                      ADC_CR_BOOST_Msk                     /*!< ADC Boost Mode configuration */

+#define ADC_CR_BOOST_0                    (0x1UL << ADC_CR_BOOST_Pos)           /*!< 0x00000100 */

+#define ADC_CR_BOOST_1                    (0x2UL << ADC_CR_BOOST_Pos)           /*!< 0x00000200 */

+#define ADC_CR_ADCALLIN_Pos               (16U)

+#define ADC_CR_ADCALLIN_Msk               (0x1UL << ADC_CR_ADCALLIN_Pos)       /*!< 0x00010000 */

+#define ADC_CR_ADCALLIN                   ADC_CR_ADCALLIN_Msk                  /*!< ADC Linearity calibration */

+#define ADC_CR_LINCALRDYW1_Pos            (22U)

+#define ADC_CR_LINCALRDYW1_Msk            (0x1UL << ADC_CR_LINCALRDYW1_Pos)    /*!< 0x00400000 */

+#define ADC_CR_LINCALRDYW1                ADC_CR_LINCALRDYW1_Msk               /*!< ADC Linearity calibration ready Word 1 */

+#define ADC_CR_LINCALRDYW2_Pos            (23U)

+#define ADC_CR_LINCALRDYW2_Msk            (0x1UL << ADC_CR_LINCALRDYW2_Pos)    /*!< 0x00800000 */

+#define ADC_CR_LINCALRDYW2                ADC_CR_LINCALRDYW2_Msk               /*!< ADC Linearity calibration ready Word 2 */

+#define ADC_CR_LINCALRDYW3_Pos            (24U)

+#define ADC_CR_LINCALRDYW3_Msk            (0x1UL << ADC_CR_LINCALRDYW3_Pos)    /*!< 0x01000000 */

+#define ADC_CR_LINCALRDYW3                ADC_CR_LINCALRDYW3_Msk               /*!< ADC Linearity calibration ready Word 3 */

+#define ADC_CR_LINCALRDYW4_Pos            (25U)

+#define ADC_CR_LINCALRDYW4_Msk            (0x1UL << ADC_CR_LINCALRDYW4_Pos)    /*!< 0x02000000 */

+#define ADC_CR_LINCALRDYW4                ADC_CR_LINCALRDYW4_Msk               /*!< ADC Linearity calibration ready Word 4 */

+#define ADC_CR_LINCALRDYW5_Pos            (26U)

+#define ADC_CR_LINCALRDYW5_Msk            (0x1UL << ADC_CR_LINCALRDYW5_Pos)    /*!< 0x04000000 */

+#define ADC_CR_LINCALRDYW5                ADC_CR_LINCALRDYW5_Msk               /*!< ADC Linearity calibration ready Word 5 */

+#define ADC_CR_LINCALRDYW6_Pos            (27U)

+#define ADC_CR_LINCALRDYW6_Msk            (0x1UL << ADC_CR_LINCALRDYW6_Pos)    /*!< 0x08000000 */

+#define ADC_CR_LINCALRDYW6                ADC_CR_LINCALRDYW6_Msk               /*!< ADC Linearity calibration ready Word 6 */

+#define ADC_CR_ADVREGEN_Pos               (28U)

+#define ADC_CR_ADVREGEN_Msk               (0x1UL << ADC_CR_ADVREGEN_Pos)       /*!< 0x10000000 */

+#define ADC_CR_ADVREGEN                   ADC_CR_ADVREGEN_Msk                  /*!< ADC Voltage regulator Enable */

+#define ADC_CR_DEEPPWD_Pos                (29U)

+#define ADC_CR_DEEPPWD_Msk                (0x1UL << ADC_CR_DEEPPWD_Pos)        /*!< 0x20000000 */

+#define ADC_CR_DEEPPWD                    ADC_CR_DEEPPWD_Msk                   /*!< ADC Deep power down Enable */

+#define ADC_CR_ADCALDIF_Pos               (30U)

+#define ADC_CR_ADCALDIF_Msk               (0x1UL << ADC_CR_ADCALDIF_Pos)       /*!< 0x40000000 */

+#define ADC_CR_ADCALDIF                   ADC_CR_ADCALDIF_Msk                  /*!< ADC Differential Mode for calibration */

+#define ADC_CR_ADCAL_Pos                  (31U)

+#define ADC_CR_ADCAL_Msk                  (0x1UL << ADC_CR_ADCAL_Pos)          /*!< 0x80000000 */

+#define ADC_CR_ADCAL                      ADC_CR_ADCAL_Msk                     /*!< ADC Calibration */

+

+/********************  Bit definition for ADC_CFGR register  ********************/

+#define ADC_CFGR_DMNGT_Pos                (0U)

+#define ADC_CFGR_DMNGT_Msk                (0x3UL << ADC_CFGR_DMNGT_Pos)        /*!< 0x00000003 */

+#define ADC_CFGR_DMNGT                    ADC_CFGR_DMNGT_Msk                   /*!< ADC Data Management configuration */

+#define ADC_CFGR_DMNGT_0                  (0x1UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000001 */

+#define ADC_CFGR_DMNGT_1                  (0x2UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000002 */

+

+#define ADC_CFGR_RES_Pos                  (2U)

+#define ADC_CFGR_RES_Msk                  (0x7UL << ADC_CFGR_RES_Pos)          /*!< 0x0000001C */

+#define ADC_CFGR_RES                      ADC_CFGR_RES_Msk                     /*!< ADC Data resolution */

+#define ADC_CFGR_RES_0                    (0x1UL << ADC_CFGR_RES_Pos)           /*!< 0x00000004 */

+#define ADC_CFGR_RES_1                    (0x2UL << ADC_CFGR_RES_Pos)           /*!< 0x00000008 */

+#define ADC_CFGR_RES_2                    (0x4UL << ADC_CFGR_RES_Pos)           /*!< 0x00000010 */

+

+#define ADC_CFGR_EXTSEL_Pos               (5U)

+#define ADC_CFGR_EXTSEL_Msk               (0x1FUL << ADC_CFGR_EXTSEL_Pos)      /*!< 0x000003E0 */

+#define ADC_CFGR_EXTSEL                   ADC_CFGR_EXTSEL_Msk                  /*!< ADC External trigger selection for regular group */

+#define ADC_CFGR_EXTSEL_0                 (0x01UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000020 */

+#define ADC_CFGR_EXTSEL_1                 (0x02UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000040 */

+#define ADC_CFGR_EXTSEL_2                 (0x04UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000080 */

+#define ADC_CFGR_EXTSEL_3                 (0x08UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000100 */

+#define ADC_CFGR_EXTSEL_4                 (0x10UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000200 */

+

+#define ADC_CFGR_EXTEN_Pos                (10U)

+#define ADC_CFGR_EXTEN_Msk                (0x3UL << ADC_CFGR_EXTEN_Pos)        /*!< 0x00000C00 */

+#define ADC_CFGR_EXTEN                    ADC_CFGR_EXTEN_Msk                   /*!< ADC External trigger enable and polarity selection for regular channels */

+#define ADC_CFGR_EXTEN_0                  (0x1UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000400 */

+#define ADC_CFGR_EXTEN_1                  (0x2UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000800 */

+

+#define ADC_CFGR_OVRMOD_Pos               (12U)

+#define ADC_CFGR_OVRMOD_Msk               (0x1UL << ADC_CFGR_OVRMOD_Pos)       /*!< 0x00001000 */

+#define ADC_CFGR_OVRMOD                   ADC_CFGR_OVRMOD_Msk                  /*!< ADC overrun mode */

+#define ADC_CFGR_CONT_Pos                 (13U)

+#define ADC_CFGR_CONT_Msk                 (0x1UL << ADC_CFGR_CONT_Pos)         /*!< 0x00002000 */

+#define ADC_CFGR_CONT                     ADC_CFGR_CONT_Msk                    /*!< ADC Single/continuous conversion mode for regular conversion */

+#define ADC_CFGR_AUTDLY_Pos               (14U)

+#define ADC_CFGR_AUTDLY_Msk               (0x1UL << ADC_CFGR_AUTDLY_Pos)       /*!< 0x00004000 */

+#define ADC_CFGR_AUTDLY                   ADC_CFGR_AUTDLY_Msk                  /*!< ADC Delayed conversion mode */

+

+#define ADC_CFGR_DISCEN_Pos               (16U)

+#define ADC_CFGR_DISCEN_Msk               (0x1UL << ADC_CFGR_DISCEN_Pos)       /*!< 0x00010000 */

+#define ADC_CFGR_DISCEN                   ADC_CFGR_DISCEN_Msk                  /*!< ADC Discontinuous mode for regular channels */

+

+#define ADC_CFGR_DISCNUM_Pos              (17U)

+#define ADC_CFGR_DISCNUM_Msk              (0x7UL << ADC_CFGR_DISCNUM_Pos)      /*!< 0x000E0000 */

+#define ADC_CFGR_DISCNUM                  ADC_CFGR_DISCNUM_Msk                 /*!< ADC Discontinuous mode channel count */

+#define ADC_CFGR_DISCNUM_0                (0x1UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00020000 */

+#define ADC_CFGR_DISCNUM_1                (0x2UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00040000 */

+#define ADC_CFGR_DISCNUM_2                (0x4UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00080000 */

+

+#define ADC_CFGR_JDISCEN_Pos              (20U)

+#define ADC_CFGR_JDISCEN_Msk              (0x1UL << ADC_CFGR_JDISCEN_Pos)      /*!< 0x00100000 */

+#define ADC_CFGR_JDISCEN                  ADC_CFGR_JDISCEN_Msk                 /*!< ADC Discontinuous mode on injected channels */

+#define ADC_CFGR_JQM_Pos                  (21U)

+#define ADC_CFGR_JQM_Msk                  (0x1UL << ADC_CFGR_JQM_Pos)          /*!< 0x00200000 */

+#define ADC_CFGR_JQM                      ADC_CFGR_JQM_Msk                     /*!< ADC JSQR Queue mode */

+#define ADC_CFGR_AWD1SGL_Pos              (22U)

+#define ADC_CFGR_AWD1SGL_Msk              (0x1UL << ADC_CFGR_AWD1SGL_Pos)      /*!< 0x00400000 */

+#define ADC_CFGR_AWD1SGL                  ADC_CFGR_AWD1SGL_Msk                 /*!< Enable the watchdog 1 on a single channel or on all channels */

+#define ADC_CFGR_AWD1EN_Pos               (23U)

+#define ADC_CFGR_AWD1EN_Msk               (0x1UL << ADC_CFGR_AWD1EN_Pos)       /*!< 0x00800000 */

+#define ADC_CFGR_AWD1EN                   ADC_CFGR_AWD1EN_Msk                  /*!< ADC Analog watchdog 1 enable on regular Channels */

+#define ADC_CFGR_JAWD1EN_Pos              (24U)

+#define ADC_CFGR_JAWD1EN_Msk              (0x1UL << ADC_CFGR_JAWD1EN_Pos)      /*!< 0x01000000 */

+#define ADC_CFGR_JAWD1EN                  ADC_CFGR_JAWD1EN_Msk                 /*!< ADC Analog watchdog 1 enable on injected Channels */

+#define ADC_CFGR_JAUTO_Pos                (25U)

+#define ADC_CFGR_JAUTO_Msk                (0x1UL << ADC_CFGR_JAUTO_Pos)        /*!< 0x02000000 */

+#define ADC_CFGR_JAUTO                    ADC_CFGR_JAUTO_Msk                   /*!< ADC Automatic injected group conversion */

+

+#define ADC_CFGR_AWD1CH_Pos               (26U)

+#define ADC_CFGR_AWD1CH_Msk               (0x1FUL << ADC_CFGR_AWD1CH_Pos)      /*!< 0x7C000000 */

+#define ADC_CFGR_AWD1CH                   ADC_CFGR_AWD1CH_Msk                  /*!< ADC Analog watchdog 1 Channel selection */

+#define ADC_CFGR_AWD1CH_0                 (0x01UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x04000000 */

+#define ADC_CFGR_AWD1CH_1                 (0x02UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x08000000 */

+#define ADC_CFGR_AWD1CH_2                 (0x04UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x10000000 */

+#define ADC_CFGR_AWD1CH_3                 (0x08UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x20000000 */

+#define ADC_CFGR_AWD1CH_4                 (0x10UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x40000000 */

+

+#define ADC_CFGR_JQDIS_Pos                (31U)

+#define ADC_CFGR_JQDIS_Msk                (0x1UL << ADC_CFGR_JQDIS_Pos)        /*!< 0x80000000 */

+#define ADC_CFGR_JQDIS                    ADC_CFGR_JQDIS_Msk                   /*!< ADC Injected queue disable */

+

+/********************  Bit definition for ADC_CFGR2 register  ********************/

+#define ADC_CFGR2_ROVSE_Pos               (0U)

+#define ADC_CFGR2_ROVSE_Msk               (0x1UL << ADC_CFGR2_ROVSE_Pos)       /*!< 0x00000001 */

+#define ADC_CFGR2_ROVSE                   ADC_CFGR2_ROVSE_Msk                  /*!< ADC Regular group oversampler enable */

+#define ADC_CFGR2_JOVSE_Pos               (1U)

+#define ADC_CFGR2_JOVSE_Msk               (0x1UL << ADC_CFGR2_JOVSE_Pos)       /*!< 0x00000002 */

+#define ADC_CFGR2_JOVSE                   ADC_CFGR2_JOVSE_Msk                  /*!< ADC Injected group oversampler enable */

+

+#define ADC_CFGR2_OVSS_Pos                (5U)

+#define ADC_CFGR2_OVSS_Msk                (0xFUL << ADC_CFGR2_OVSS_Pos)        /*!< 0x000001E0 */

+#define ADC_CFGR2_OVSS                    ADC_CFGR2_OVSS_Msk                   /*!< ADC Regular Oversampling shift */

+#define ADC_CFGR2_OVSS_0                  (0x1UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000020 */

+#define ADC_CFGR2_OVSS_1                  (0x2UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000040 */

+#define ADC_CFGR2_OVSS_2                  (0x4UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000080 */

+#define ADC_CFGR2_OVSS_3                  (0x8UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000100 */

+

+#define ADC_CFGR2_TROVS_Pos               (9U)

+#define ADC_CFGR2_TROVS_Msk               (0x1UL << ADC_CFGR2_TROVS_Pos)       /*!< 0x00000200 */

+#define ADC_CFGR2_TROVS                   ADC_CFGR2_TROVS_Msk                  /*!< ADC Triggered regular Oversampling */

+#define ADC_CFGR2_ROVSM_Pos               (10U)

+#define ADC_CFGR2_ROVSM_Msk               (0x1UL << ADC_CFGR2_ROVSM_Pos)       /*!< 0x00000400 */

+#define ADC_CFGR2_ROVSM                   ADC_CFGR2_ROVSM_Msk                  /*!< ADC Regular oversampling mode */

+

+#define ADC_CFGR2_RSHIFT1_Pos             (11U)

+#define ADC_CFGR2_RSHIFT1_Msk             (0x1UL << ADC_CFGR2_RSHIFT1_Pos)     /*!< 0x00000800 */

+#define ADC_CFGR2_RSHIFT1                 ADC_CFGR2_RSHIFT1_Msk                /*!< ADC Right-shift data after Offset 1 correction */

+#define ADC_CFGR2_RSHIFT2_Pos             (12U)

+#define ADC_CFGR2_RSHIFT2_Msk             (0x1UL << ADC_CFGR2_RSHIFT2_Pos)     /*!< 0x00001000 */

+#define ADC_CFGR2_RSHIFT2                 ADC_CFGR2_RSHIFT2_Msk                /*!< ADC Right-shift data after Offset 2 correction */

+#define ADC_CFGR2_RSHIFT3_Pos             (13U)

+#define ADC_CFGR2_RSHIFT3_Msk             (0x1UL << ADC_CFGR2_RSHIFT3_Pos)     /*!< 0x00002000 */

+#define ADC_CFGR2_RSHIFT3                 ADC_CFGR2_RSHIFT3_Msk                /*!< ADC Right-shift data after Offset 3 correction */

+#define ADC_CFGR2_RSHIFT4_Pos             (14U)

+#define ADC_CFGR2_RSHIFT4_Msk             (0x1UL << ADC_CFGR2_RSHIFT4_Pos)     /*!< 0x00004000 */

+#define ADC_CFGR2_RSHIFT4                 ADC_CFGR2_RSHIFT4_Msk                /*!< ADC Right-shift data after Offset 4 correction */

+

+#define ADC_CFGR2_OVSR_Pos                (16U)

+#define ADC_CFGR2_OVSR_Msk                (0x3FFUL << ADC_CFGR2_OVSR_Pos)      /*!< 0x03FF0000 */

+#define ADC_CFGR2_OVSR                    ADC_CFGR2_OVSR_Msk                   /*!< ADC oversampling Ratio */

+#define ADC_CFGR2_OVSR_0                  (0x001UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00010000 */

+#define ADC_CFGR2_OVSR_1                  (0x002UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00020000 */

+#define ADC_CFGR2_OVSR_2                  (0x004UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00040000 */

+#define ADC_CFGR2_OVSR_3                  (0x008UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00080000 */

+#define ADC_CFGR2_OVSR_4                  (0x010UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00100000 */

+#define ADC_CFGR2_OVSR_5                  (0x020UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00200000 */

+#define ADC_CFGR2_OVSR_6                  (0x040UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00400000 */

+#define ADC_CFGR2_OVSR_7                  (0x080UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00800000 */

+#define ADC_CFGR2_OVSR_8                  (0x100UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x01000000 */

+#define ADC_CFGR2_OVSR_9                  (0x200UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x02000000 */

+

+#define ADC_CFGR2_LSHIFT_Pos              (28U)

+#define ADC_CFGR2_LSHIFT_Msk              (0xFUL << ADC_CFGR2_LSHIFT_Pos)      /*!< 0xF0000000 */

+#define ADC_CFGR2_LSHIFT                  ADC_CFGR2_LSHIFT_Msk                 /*!< ADC Left shift factor */

+#define ADC_CFGR2_LSHIFT_0                (0x1UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x10000000 */

+#define ADC_CFGR2_LSHIFT_1                (0x2UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x20000000 */

+#define ADC_CFGR2_LSHIFT_2                (0x4UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x40000000 */

+#define ADC_CFGR2_LSHIFT_3                (0x8UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_SMPR1 register  ********************/

+#define ADC_SMPR1_SMP0_Pos                (0U)

+#define ADC_SMPR1_SMP0_Msk                (0x7UL << ADC_SMPR1_SMP0_Pos)        /*!< 0x00000007 */

+#define ADC_SMPR1_SMP0                    ADC_SMPR1_SMP0_Msk                   /*!< ADC Channel 0 Sampling time selection  */

+#define ADC_SMPR1_SMP0_0                  (0x1UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000001 */

+#define ADC_SMPR1_SMP0_1                  (0x2UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000002 */

+#define ADC_SMPR1_SMP0_2                  (0x4UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000004 */

+

+#define ADC_SMPR1_SMP1_Pos                (3U)

+#define ADC_SMPR1_SMP1_Msk                (0x7UL << ADC_SMPR1_SMP1_Pos)        /*!< 0x00000038 */

+#define ADC_SMPR1_SMP1                    ADC_SMPR1_SMP1_Msk                   /*!< ADC Channel 1 Sampling time selection  */

+#define ADC_SMPR1_SMP1_0                  (0x1UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000008 */

+#define ADC_SMPR1_SMP1_1                  (0x2UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000010 */

+#define ADC_SMPR1_SMP1_2                  (0x4UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000020 */

+

+#define ADC_SMPR1_SMP2_Pos                (6U)

+#define ADC_SMPR1_SMP2_Msk                (0x7UL << ADC_SMPR1_SMP2_Pos)        /*!< 0x000001C0 */

+#define ADC_SMPR1_SMP2                    ADC_SMPR1_SMP2_Msk                   /*!< ADC Channel 2 Sampling time selection  */

+#define ADC_SMPR1_SMP2_0                  (0x1UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000040 */

+#define ADC_SMPR1_SMP2_1                  (0x2UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000080 */

+#define ADC_SMPR1_SMP2_2                  (0x4UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000100 */

+

+#define ADC_SMPR1_SMP3_Pos                (9U)

+#define ADC_SMPR1_SMP3_Msk                (0x7UL << ADC_SMPR1_SMP3_Pos)        /*!< 0x00000E00 */

+#define ADC_SMPR1_SMP3                    ADC_SMPR1_SMP3_Msk                   /*!< ADC Channel 3 Sampling time selection  */

+#define ADC_SMPR1_SMP3_0                  (0x1UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000200 */

+#define ADC_SMPR1_SMP3_1                  (0x2UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000400 */

+#define ADC_SMPR1_SMP3_2                  (0x4UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000800 */

+

+#define ADC_SMPR1_SMP4_Pos                (12U)

+#define ADC_SMPR1_SMP4_Msk                (0x7UL << ADC_SMPR1_SMP4_Pos)        /*!< 0x00007000 */

+#define ADC_SMPR1_SMP4                    ADC_SMPR1_SMP4_Msk                   /*!< ADC Channel 4 Sampling time selection  */

+#define ADC_SMPR1_SMP4_0                  (0x1UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00001000 */

+#define ADC_SMPR1_SMP4_1                  (0x2UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00002000 */

+#define ADC_SMPR1_SMP4_2                  (0x4UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00004000 */

+

+#define ADC_SMPR1_SMP5_Pos                (15U)

+#define ADC_SMPR1_SMP5_Msk                (0x7UL << ADC_SMPR1_SMP5_Pos)        /*!< 0x00038000 */

+#define ADC_SMPR1_SMP5                    ADC_SMPR1_SMP5_Msk                   /*!< ADC Channel 5 Sampling time selection  */

+#define ADC_SMPR1_SMP5_0                  (0x1UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00008000 */

+#define ADC_SMPR1_SMP5_1                  (0x2UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00010000 */

+#define ADC_SMPR1_SMP5_2                  (0x4UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00020000 */

+

+#define ADC_SMPR1_SMP6_Pos                (18U)

+#define ADC_SMPR1_SMP6_Msk                (0x7UL << ADC_SMPR1_SMP6_Pos)        /*!< 0x001C0000 */

+#define ADC_SMPR1_SMP6                    ADC_SMPR1_SMP6_Msk                   /*!< ADC Channel 6 Sampling time selection  */

+#define ADC_SMPR1_SMP6_0                  (0x1UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00040000 */

+#define ADC_SMPR1_SMP6_1                  (0x2UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00080000 */

+#define ADC_SMPR1_SMP6_2                  (0x4UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00100000 */

+

+#define ADC_SMPR1_SMP7_Pos                (21U)

+#define ADC_SMPR1_SMP7_Msk                (0x7UL << ADC_SMPR1_SMP7_Pos)        /*!< 0x00E00000 */

+#define ADC_SMPR1_SMP7                    ADC_SMPR1_SMP7_Msk                   /*!< ADC Channel 7 Sampling time selection  */

+#define ADC_SMPR1_SMP7_0                  (0x1UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00200000 */

+#define ADC_SMPR1_SMP7_1                  (0x2UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00400000 */

+#define ADC_SMPR1_SMP7_2                  (0x4UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00800000 */

+

+#define ADC_SMPR1_SMP8_Pos                (24U)

+#define ADC_SMPR1_SMP8_Msk                (0x7UL << ADC_SMPR1_SMP8_Pos)        /*!< 0x07000000 */

+#define ADC_SMPR1_SMP8                    ADC_SMPR1_SMP8_Msk                   /*!< ADC Channel 8 Sampling time selection  */

+#define ADC_SMPR1_SMP8_0                  (0x1UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x01000000 */

+#define ADC_SMPR1_SMP8_1                  (0x2UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x02000000 */

+#define ADC_SMPR1_SMP8_2                  (0x4UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x04000000 */

+

+#define ADC_SMPR1_SMP9_Pos                (27U)

+#define ADC_SMPR1_SMP9_Msk                (0x7UL << ADC_SMPR1_SMP9_Pos)        /*!< 0x38000000 */

+#define ADC_SMPR1_SMP9                    ADC_SMPR1_SMP9_Msk                   /*!< ADC Channel 9 Sampling time selection  */

+#define ADC_SMPR1_SMP9_0                  (0x1UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x08000000 */

+#define ADC_SMPR1_SMP9_1                  (0x2UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x10000000 */

+#define ADC_SMPR1_SMP9_2                  (0x4UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x20000000 */

+

+/********************  Bit definition for ADC_SMPR2 register  ********************/

+#define ADC_SMPR2_SMP10_Pos               (0U)

+#define ADC_SMPR2_SMP10_Msk               (0x7UL << ADC_SMPR2_SMP10_Pos)       /*!< 0x00000007 */

+#define ADC_SMPR2_SMP10                   ADC_SMPR2_SMP10_Msk                  /*!< ADC Channel 10 Sampling time selection  */

+#define ADC_SMPR2_SMP10_0                 (0x1UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000001 */

+#define ADC_SMPR2_SMP10_1                 (0x2UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000002 */

+#define ADC_SMPR2_SMP10_2                 (0x4UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000004 */

+

+#define ADC_SMPR2_SMP11_Pos               (3U)

+#define ADC_SMPR2_SMP11_Msk               (0x7UL << ADC_SMPR2_SMP11_Pos)       /*!< 0x00000038 */

+#define ADC_SMPR2_SMP11                   ADC_SMPR2_SMP11_Msk                  /*!< ADC Channel 11 Sampling time selection  */

+#define ADC_SMPR2_SMP11_0                 (0x1UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000008 */

+#define ADC_SMPR2_SMP11_1                 (0x2UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000010 */

+#define ADC_SMPR2_SMP11_2                 (0x4UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000020 */

+

+#define ADC_SMPR2_SMP12_Pos               (6U)

+#define ADC_SMPR2_SMP12_Msk               (0x7UL << ADC_SMPR2_SMP12_Pos)       /*!< 0x000001C0 */

+#define ADC_SMPR2_SMP12                   ADC_SMPR2_SMP12_Msk                  /*!< ADC Channel 12 Sampling time selection  */

+#define ADC_SMPR2_SMP12_0                 (0x1UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000040 */

+#define ADC_SMPR2_SMP12_1                 (0x2UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000080 */

+#define ADC_SMPR2_SMP12_2                 (0x4UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000100 */

+

+#define ADC_SMPR2_SMP13_Pos               (9U)

+#define ADC_SMPR2_SMP13_Msk               (0x7UL << ADC_SMPR2_SMP13_Pos)       /*!< 0x00000E00 */

+#define ADC_SMPR2_SMP13                   ADC_SMPR2_SMP13_Msk                  /*!< ADC Channel 13 Sampling time selection  */

+#define ADC_SMPR2_SMP13_0                 (0x1UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000200 */

+#define ADC_SMPR2_SMP13_1                 (0x2UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000400 */

+#define ADC_SMPR2_SMP13_2                 (0x4UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000800 */

+

+#define ADC_SMPR2_SMP14_Pos               (12U)

+#define ADC_SMPR2_SMP14_Msk               (0x7UL << ADC_SMPR2_SMP14_Pos)       /*!< 0x00007000 */

+#define ADC_SMPR2_SMP14                   ADC_SMPR2_SMP14_Msk                  /*!< ADC Channel 14 Sampling time selection  */

+#define ADC_SMPR2_SMP14_0                 (0x1UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00001000 */

+#define ADC_SMPR2_SMP14_1                 (0x2UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00002000 */

+#define ADC_SMPR2_SMP14_2                 (0x4UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00004000 */

+

+#define ADC_SMPR2_SMP15_Pos               (15U)

+#define ADC_SMPR2_SMP15_Msk               (0x7UL << ADC_SMPR2_SMP15_Pos)       /*!< 0x00038000 */

+#define ADC_SMPR2_SMP15                   ADC_SMPR2_SMP15_Msk                  /*!< ADC Channel 15 Sampling time selection  */

+#define ADC_SMPR2_SMP15_0                 (0x1UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00008000 */

+#define ADC_SMPR2_SMP15_1                 (0x2UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00010000 */

+#define ADC_SMPR2_SMP15_2                 (0x4UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00020000 */

+

+#define ADC_SMPR2_SMP16_Pos               (18U)

+#define ADC_SMPR2_SMP16_Msk               (0x7UL << ADC_SMPR2_SMP16_Pos)       /*!< 0x001C0000 */

+#define ADC_SMPR2_SMP16                   ADC_SMPR2_SMP16_Msk                  /*!< ADC Channel 16 Sampling time selection  */

+#define ADC_SMPR2_SMP16_0                 (0x1UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00040000 */

+#define ADC_SMPR2_SMP16_1                 (0x2UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00080000 */

+#define ADC_SMPR2_SMP16_2                 (0x4UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00100000 */

+

+#define ADC_SMPR2_SMP17_Pos               (21U)

+#define ADC_SMPR2_SMP17_Msk               (0x7UL << ADC_SMPR2_SMP17_Pos)       /*!< 0x00E00000 */

+#define ADC_SMPR2_SMP17                   ADC_SMPR2_SMP17_Msk                  /*!< ADC Channel 17 Sampling time selection  */

+#define ADC_SMPR2_SMP17_0                 (0x1UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00200000 */

+#define ADC_SMPR2_SMP17_1                 (0x2UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00400000 */

+#define ADC_SMPR2_SMP17_2                 (0x4UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00800000 */

+

+#define ADC_SMPR2_SMP18_Pos               (24U)

+#define ADC_SMPR2_SMP18_Msk               (0x7UL << ADC_SMPR2_SMP18_Pos)       /*!< 0x07000000 */

+#define ADC_SMPR2_SMP18                   ADC_SMPR2_SMP18_Msk                  /*!< ADC Channel 18 Sampling time selection  */

+#define ADC_SMPR2_SMP18_0                 (0x1UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x01000000 */

+#define ADC_SMPR2_SMP18_1                 (0x2UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x02000000 */

+#define ADC_SMPR2_SMP18_2                 (0x4UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x04000000 */

+

+#define ADC_SMPR2_SMP19_Pos               (27U)

+#define ADC_SMPR2_SMP19_Msk               (0x7UL << ADC_SMPR2_SMP19_Pos)       /*!< 0x38000000 */

+#define ADC_SMPR2_SMP19                   ADC_SMPR2_SMP19_Msk                  /*!< ADC Channel 19 Sampling time selection  */

+#define ADC_SMPR2_SMP19_0                 (0x1UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x08000000 */

+#define ADC_SMPR2_SMP19_1                 (0x2UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x10000000 */

+#define ADC_SMPR2_SMP19_2                 (0x4UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x20000000 */

+

+/********************  Bit definition for ADC_PCSEL register  ********************/

+#define ADC_PCSEL_PCSEL_Pos               (0U)

+#define ADC_PCSEL_PCSEL_Msk               (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)   /*!< 0x000FFFFF */

+#define ADC_PCSEL_PCSEL                   ADC_PCSEL_PCSEL_Msk                  /*!< ADC pre channel selection */

+#define ADC_PCSEL_PCSEL_0                 (0x00001UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */

+#define ADC_PCSEL_PCSEL_1                 (0x00002UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */

+#define ADC_PCSEL_PCSEL_2                 (0x00004UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */

+#define ADC_PCSEL_PCSEL_3                 (0x00008UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */

+#define ADC_PCSEL_PCSEL_4                 (0x00010UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */

+#define ADC_PCSEL_PCSEL_5                 (0x00020UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */

+#define ADC_PCSEL_PCSEL_6                 (0x00040UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */

+#define ADC_PCSEL_PCSEL_7                 (0x00080UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */

+#define ADC_PCSEL_PCSEL_8                 (0x00100UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */

+#define ADC_PCSEL_PCSEL_9                 (0x00200UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */

+#define ADC_PCSEL_PCSEL_10                (0x00400UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */

+#define ADC_PCSEL_PCSEL_11                (0x00800UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */

+#define ADC_PCSEL_PCSEL_12                (0x01000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */

+#define ADC_PCSEL_PCSEL_13                (0x02000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */

+#define ADC_PCSEL_PCSEL_14                (0x04000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */

+#define ADC_PCSEL_PCSEL_15                (0x08000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */

+#define ADC_PCSEL_PCSEL_16                (0x10000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */

+#define ADC_PCSEL_PCSEL_17                (0x20000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */

+#define ADC_PCSEL_PCSEL_18                (0x40000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */

+#define ADC_PCSEL_PCSEL_19                (0x80000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00080000 */

+

+/*****************  Bit definition for ADC_LTR1, 2, 3 registers *****************/

+#define ADC_LTR_LT_Pos                    (0U)

+#define ADC_LTR_LT_Msk                    (0x3FFFFFFUL << ADC_LTR_LT_Pos)      /*!< 0x03FFFFFF */

+#define ADC_LTR_LT                        ADC_LTR_LT_Msk                       /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */

+

+/*****************  Bit definition for ADC_HTR1, 2, 3 registers  ****************/

+#define ADC_HTR_HT_Pos                    (0U)

+#define ADC_HTR_HT_Msk                    (0x3FFFFFFUL << ADC_HTR_HT_Pos)      /*!< 0x03FFFFFF */

+#define ADC_HTR_HT                        ADC_HTR_HT_Msk                       /*!< ADC Analog watchdog 1,2 and 3 higher threshold */

+

+

+/********************  Bit definition for ADC_SQR1 register  ********************/

+#define ADC_SQR1_L_Pos                    (0U)

+#define ADC_SQR1_L_Msk                    (0xFUL << ADC_SQR1_L_Pos)            /*!< 0x0000000F */

+#define ADC_SQR1_L                        ADC_SQR1_L_Msk                       /*!< ADC regular channel sequence lenght */

+#define ADC_SQR1_L_0                      (0x1UL << ADC_SQR1_L_Pos)             /*!< 0x00000001 */

+#define ADC_SQR1_L_1                      (0x2UL << ADC_SQR1_L_Pos)             /*!< 0x00000002 */

+#define ADC_SQR1_L_2                      (0x4UL << ADC_SQR1_L_Pos)             /*!< 0x00000004 */

+#define ADC_SQR1_L_3                      (0x8UL << ADC_SQR1_L_Pos)             /*!< 0x00000008 */

+

+#define ADC_SQR1_SQ1_Pos                  (6U)

+#define ADC_SQR1_SQ1_Msk                  (0x1FUL << ADC_SQR1_SQ1_Pos)         /*!< 0x000007C0 */

+#define ADC_SQR1_SQ1                      ADC_SQR1_SQ1_Msk                     /*!< ADC 1st conversion in regular sequence */

+#define ADC_SQR1_SQ1_0                    (0x01UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000040 */

+#define ADC_SQR1_SQ1_1                    (0x02UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000080 */

+#define ADC_SQR1_SQ1_2                    (0x04UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000100 */

+#define ADC_SQR1_SQ1_3                    (0x08UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000200 */

+#define ADC_SQR1_SQ1_4                    (0x10UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000400 */

+

+#define ADC_SQR1_SQ2_Pos                  (12U)

+#define ADC_SQR1_SQ2_Msk                  (0x1FUL << ADC_SQR1_SQ2_Pos)         /*!< 0x0001F000 */

+#define ADC_SQR1_SQ2                      ADC_SQR1_SQ2_Msk                     /*!< ADC 2nd conversion in regular sequence */

+#define ADC_SQR1_SQ2_0                    (0x01UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00001000 */

+#define ADC_SQR1_SQ2_1                    (0x02UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00002000 */

+#define ADC_SQR1_SQ2_2                    (0x04UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00004000 */

+#define ADC_SQR1_SQ2_3                    (0x08UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00008000 */

+#define ADC_SQR1_SQ2_4                    (0x10UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00010000 */

+

+#define ADC_SQR1_SQ3_Pos                  (18U)

+#define ADC_SQR1_SQ3_Msk                  (0x1FUL << ADC_SQR1_SQ3_Pos)         /*!< 0x007C0000 */

+#define ADC_SQR1_SQ3                      ADC_SQR1_SQ3_Msk                     /*!< ADC 3rd conversion in regular sequence */

+#define ADC_SQR1_SQ3_0                    (0x01UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00040000 */

+#define ADC_SQR1_SQ3_1                    (0x02UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00080000 */

+#define ADC_SQR1_SQ3_2                    (0x04UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00100000 */

+#define ADC_SQR1_SQ3_3                    (0x08UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00200000 */

+#define ADC_SQR1_SQ3_4                    (0x10UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00400000 */

+

+#define ADC_SQR1_SQ4_Pos                  (24U)

+#define ADC_SQR1_SQ4_Msk                  (0x1FUL << ADC_SQR1_SQ4_Pos)         /*!< 0x1F000000 */

+#define ADC_SQR1_SQ4                      ADC_SQR1_SQ4_Msk                     /*!< ADC 4th conversion in regular sequence */

+#define ADC_SQR1_SQ4_0                    (0x01UL << ADC_SQR1_SQ4_Pos)          /*!< 0x01000000 */

+#define ADC_SQR1_SQ4_1                    (0x02UL << ADC_SQR1_SQ4_Pos)          /*!< 0x02000000 */

+#define ADC_SQR1_SQ4_2                    (0x04UL << ADC_SQR1_SQ4_Pos)          /*!< 0x04000000 */

+#define ADC_SQR1_SQ4_3                    (0x08UL << ADC_SQR1_SQ4_Pos)          /*!< 0x08000000 */

+#define ADC_SQR1_SQ4_4                    (0x10UL << ADC_SQR1_SQ4_Pos)          /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR2 register  ********************/

+#define ADC_SQR2_SQ5_Pos                  (0U)

+#define ADC_SQR2_SQ5_Msk                  (0x1FUL << ADC_SQR2_SQ5_Pos)         /*!< 0x0000001F */

+#define ADC_SQR2_SQ5                      ADC_SQR2_SQ5_Msk                     /*!< ADC 5th conversion in regular sequence */

+#define ADC_SQR2_SQ5_0                    (0x01UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000001 */

+#define ADC_SQR2_SQ5_1                    (0x02UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000002 */

+#define ADC_SQR2_SQ5_2                    (0x04UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000004 */

+#define ADC_SQR2_SQ5_3                    (0x08UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000008 */

+#define ADC_SQR2_SQ5_4                    (0x10UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000010 */

+

+#define ADC_SQR2_SQ6_Pos                  (6U)

+#define ADC_SQR2_SQ6_Msk                  (0x1FUL << ADC_SQR2_SQ6_Pos)         /*!< 0x000007C0 */

+#define ADC_SQR2_SQ6                      ADC_SQR2_SQ6_Msk                     /*!< ADC 6th conversion in regular sequence */

+#define ADC_SQR2_SQ6_0                    (0x01UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000040 */

+#define ADC_SQR2_SQ6_1                    (0x02UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000080 */

+#define ADC_SQR2_SQ6_2                    (0x04UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000100 */

+#define ADC_SQR2_SQ6_3                    (0x08UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000200 */

+#define ADC_SQR2_SQ6_4                    (0x10UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000400 */

+

+#define ADC_SQR2_SQ7_Pos                  (12U)

+#define ADC_SQR2_SQ7_Msk                  (0x1FUL << ADC_SQR2_SQ7_Pos)         /*!< 0x0001F000 */

+#define ADC_SQR2_SQ7                      ADC_SQR2_SQ7_Msk                     /*!< ADC 7th conversion in regular sequence */

+#define ADC_SQR2_SQ7_0                    (0x01UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00001000 */

+#define ADC_SQR2_SQ7_1                    (0x02UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00002000 */

+#define ADC_SQR2_SQ7_2                    (0x04UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00004000 */

+#define ADC_SQR2_SQ7_3                    (0x08UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00008000 */

+#define ADC_SQR2_SQ7_4                    (0x10UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00010000 */

+

+#define ADC_SQR2_SQ8_Pos                  (18U)

+#define ADC_SQR2_SQ8_Msk                  (0x1FUL << ADC_SQR2_SQ8_Pos)         /*!< 0x007C0000 */

+#define ADC_SQR2_SQ8                      ADC_SQR2_SQ8_Msk                     /*!< ADC 8th conversion in regular sequence */

+#define ADC_SQR2_SQ8_0                    (0x01UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00040000 */

+#define ADC_SQR2_SQ8_1                    (0x02UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00080000 */

+#define ADC_SQR2_SQ8_2                    (0x04UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00100000 */

+#define ADC_SQR2_SQ8_3                    (0x08UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00200000 */

+#define ADC_SQR2_SQ8_4                    (0x10UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00400000 */

+

+#define ADC_SQR2_SQ9_Pos                  (24U)

+#define ADC_SQR2_SQ9_Msk                  (0x1FUL << ADC_SQR2_SQ9_Pos)         /*!< 0x1F000000 */

+#define ADC_SQR2_SQ9                      ADC_SQR2_SQ9_Msk                     /*!< ADC 9th conversion in regular sequence */

+#define ADC_SQR2_SQ9_0                    (0x01UL << ADC_SQR2_SQ9_Pos)          /*!< 0x01000000 */

+#define ADC_SQR2_SQ9_1                    (0x02UL << ADC_SQR2_SQ9_Pos)          /*!< 0x02000000 */

+#define ADC_SQR2_SQ9_2                    (0x04UL << ADC_SQR2_SQ9_Pos)          /*!< 0x04000000 */

+#define ADC_SQR2_SQ9_3                    (0x08UL << ADC_SQR2_SQ9_Pos)          /*!< 0x08000000 */

+#define ADC_SQR2_SQ9_4                    (0x10UL << ADC_SQR2_SQ9_Pos)          /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR3 register  ********************/

+#define ADC_SQR3_SQ10_Pos                 (0U)

+#define ADC_SQR3_SQ10_Msk                 (0x1FUL << ADC_SQR3_SQ10_Pos)        /*!< 0x0000001F */

+#define ADC_SQR3_SQ10                     ADC_SQR3_SQ10_Msk                    /*!< ADC 10th conversion in regular sequence */

+#define ADC_SQR3_SQ10_0                   (0x01UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000001 */

+#define ADC_SQR3_SQ10_1                   (0x02UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000002 */

+#define ADC_SQR3_SQ10_2                   (0x04UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000004 */

+#define ADC_SQR3_SQ10_3                   (0x08UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000008 */

+#define ADC_SQR3_SQ10_4                   (0x10UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000010 */

+

+#define ADC_SQR3_SQ11_Pos                 (6U)

+#define ADC_SQR3_SQ11_Msk                 (0x1FUL << ADC_SQR3_SQ11_Pos)        /*!< 0x000007C0 */

+#define ADC_SQR3_SQ11                     ADC_SQR3_SQ11_Msk                    /*!< ADC 11th conversion in regular sequence */

+#define ADC_SQR3_SQ11_0                   (0x01UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000040 */

+#define ADC_SQR3_SQ11_1                   (0x02UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000080 */

+#define ADC_SQR3_SQ11_2                   (0x04UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000100 */

+#define ADC_SQR3_SQ11_3                   (0x08UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000200 */

+#define ADC_SQR3_SQ11_4                   (0x10UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000400 */

+

+#define ADC_SQR3_SQ12_Pos                 (12U)

+#define ADC_SQR3_SQ12_Msk                 (0x1FUL << ADC_SQR3_SQ12_Pos)        /*!< 0x0001F000 */

+#define ADC_SQR3_SQ12                     ADC_SQR3_SQ12_Msk                    /*!< ADC 12th conversion in regular sequence */

+#define ADC_SQR3_SQ12_0                   (0x01UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00001000 */

+#define ADC_SQR3_SQ12_1                   (0x02UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00002000 */

+#define ADC_SQR3_SQ12_2                   (0x04UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00004000 */

+#define ADC_SQR3_SQ12_3                   (0x08UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00008000 */

+#define ADC_SQR3_SQ12_4                   (0x10UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00010000 */

+

+#define ADC_SQR3_SQ13_Pos                 (18U)

+#define ADC_SQR3_SQ13_Msk                 (0x1FUL << ADC_SQR3_SQ13_Pos)        /*!< 0x007C0000 */

+#define ADC_SQR3_SQ13                     ADC_SQR3_SQ13_Msk                    /*!< ADC 13th conversion in regular sequence */

+#define ADC_SQR3_SQ13_0                   (0x01UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00040000 */

+#define ADC_SQR3_SQ13_1                   (0x02UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00080000 */

+#define ADC_SQR3_SQ13_2                   (0x04UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00100000 */

+#define ADC_SQR3_SQ13_3                   (0x08UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00200000 */

+#define ADC_SQR3_SQ13_4                   (0x10UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00400000 */

+

+#define ADC_SQR3_SQ14_Pos                 (24U)

+#define ADC_SQR3_SQ14_Msk                 (0x1FUL << ADC_SQR3_SQ14_Pos)        /*!< 0x1F000000 */

+#define ADC_SQR3_SQ14                     ADC_SQR3_SQ14_Msk                    /*!< ADC 14th conversion in regular sequence */

+#define ADC_SQR3_SQ14_0                   (0x01UL << ADC_SQR3_SQ14_Pos)         /*!< 0x01000000 */

+#define ADC_SQR3_SQ14_1                   (0x02UL << ADC_SQR3_SQ14_Pos)         /*!< 0x02000000 */

+#define ADC_SQR3_SQ14_2                   (0x04UL << ADC_SQR3_SQ14_Pos)         /*!< 0x04000000 */

+#define ADC_SQR3_SQ14_3                   (0x08UL << ADC_SQR3_SQ14_Pos)         /*!< 0x08000000 */

+#define ADC_SQR3_SQ14_4                   (0x10UL << ADC_SQR3_SQ14_Pos)         /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR4 register  ********************/

+#define ADC_SQR4_SQ15_Pos                 (0U)

+#define ADC_SQR4_SQ15_Msk                 (0x1FUL << ADC_SQR4_SQ15_Pos)        /*!< 0x0000001F */

+#define ADC_SQR4_SQ15                     ADC_SQR4_SQ15_Msk                    /*!< ADC 15th conversion in regular sequence */

+#define ADC_SQR4_SQ15_0                   (0x01UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000001 */

+#define ADC_SQR4_SQ15_1                   (0x02UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000002 */

+#define ADC_SQR4_SQ15_2                   (0x04UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000004 */

+#define ADC_SQR4_SQ15_3                   (0x08UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000008 */

+#define ADC_SQR4_SQ15_4                   (0x10UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000010 */

+

+#define ADC_SQR4_SQ16_Pos                 (6U)

+#define ADC_SQR4_SQ16_Msk                 (0x1FUL << ADC_SQR4_SQ16_Pos)        /*!< 0x000007C0 */

+#define ADC_SQR4_SQ16                     ADC_SQR4_SQ16_Msk                    /*!< ADC 16th conversion in regular sequence */

+#define ADC_SQR4_SQ16_0                   (0x01UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000040 */

+#define ADC_SQR4_SQ16_1                   (0x02UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000080 */

+#define ADC_SQR4_SQ16_2                   (0x04UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000100 */

+#define ADC_SQR4_SQ16_3                   (0x08UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000200 */

+#define ADC_SQR4_SQ16_4                   (0x10UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000400 */

+/********************  Bit definition for ADC_DR register  ********************/

+#define ADC_DR_RDATA_Pos                  (0U)

+#define ADC_DR_RDATA_Msk                  (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)   /*!< 0xFFFFFFFF */

+#define ADC_DR_RDATA                      ADC_DR_RDATA_Msk                     /*!< ADC regular Data converted */

+

+/********************  Bit definition for ADC_JSQR register  ********************/

+#define ADC_JSQR_JL_Pos                   (0U)

+#define ADC_JSQR_JL_Msk                   (0x3UL << ADC_JSQR_JL_Pos)           /*!< 0x00000003 */

+#define ADC_JSQR_JL                       ADC_JSQR_JL_Msk                      /*!< ADC injected channel sequence length */

+#define ADC_JSQR_JL_0                     (0x1UL << ADC_JSQR_JL_Pos)           /*!< 0x00000001 */

+#define ADC_JSQR_JL_1                     (0x2UL << ADC_JSQR_JL_Pos)           /*!< 0x00000002 */

+

+#define ADC_JSQR_JEXTSEL_Pos              (2U)

+#define ADC_JSQR_JEXTSEL_Msk              (0x1FUL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x0000007C */

+#define ADC_JSQR_JEXTSEL                  ADC_JSQR_JEXTSEL_Msk                 /*!< ADC external trigger selection for injected group */

+#define ADC_JSQR_JEXTSEL_0                (0x01UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000004 */

+#define ADC_JSQR_JEXTSEL_1                (0x02UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000008 */

+#define ADC_JSQR_JEXTSEL_2                (0x04UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000010 */

+#define ADC_JSQR_JEXTSEL_3                (0x08UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000020 */

+#define ADC_JSQR_JEXTSEL_4                (0x10UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000040 */

+

+#define ADC_JSQR_JEXTEN_Pos               (7U)

+#define ADC_JSQR_JEXTEN_Msk               (0x3UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000180 */

+#define ADC_JSQR_JEXTEN                   ADC_JSQR_JEXTEN_Msk                  /*!< ADC external trigger enable and polarity selection for injected channels */

+#define ADC_JSQR_JEXTEN_0                 (0x1UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000080 */

+#define ADC_JSQR_JEXTEN_1                 (0x2UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000100 */

+

+#define ADC_JSQR_JSQ1_Pos                 (9U)

+#define ADC_JSQR_JSQ1_Msk                 (0x1FUL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00003E00 */

+#define ADC_JSQR_JSQ1                     ADC_JSQR_JSQ1_Msk                    /*!< ADC 1st conversion in injected sequence */

+#define ADC_JSQR_JSQ1_0                   (0x01UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000200 */

+#define ADC_JSQR_JSQ1_1                   (0x02UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000400 */

+#define ADC_JSQR_JSQ1_2                   (0x04UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000800 */

+#define ADC_JSQR_JSQ1_3                   (0x08UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00001000 */

+#define ADC_JSQR_JSQ1_4                   (0x10UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00002000 */

+

+#define ADC_JSQR_JSQ2_Pos                 (15U)

+#define ADC_JSQR_JSQ2_Msk                 (0x1FUL << ADC_JSQR_JSQ2_Pos)        /*!< 0x000F8000 */

+#define ADC_JSQR_JSQ2                     ADC_JSQR_JSQ2_Msk                    /*!< ADC 2nd conversion in injected sequence */

+#define ADC_JSQR_JSQ2_0                   (0x01UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00008000 */

+#define ADC_JSQR_JSQ2_1                   (0x02UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00010000 */

+#define ADC_JSQR_JSQ2_2                   (0x04UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00020000 */

+#define ADC_JSQR_JSQ2_3                   (0x08UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00040000 */

+#define ADC_JSQR_JSQ2_4                   (0x10UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00080000 */

+

+#define ADC_JSQR_JSQ3_Pos                 (21U)

+#define ADC_JSQR_JSQ3_Msk                 (0x1FUL << ADC_JSQR_JSQ3_Pos)        /*!< 0x03E00000 */

+#define ADC_JSQR_JSQ3                     ADC_JSQR_JSQ3_Msk                    /*!< ADC 3rd conversion in injected sequence */

+#define ADC_JSQR_JSQ3_0                   (0x01UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00200000 */

+#define ADC_JSQR_JSQ3_1                   (0x02UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00400000 */

+#define ADC_JSQR_JSQ3_2                   (0x04UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00800000 */

+#define ADC_JSQR_JSQ3_3                   (0x08UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x01000000 */

+#define ADC_JSQR_JSQ3_4                   (0x10UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x02000000 */

+

+#define ADC_JSQR_JSQ4_Pos                 (27U)

+#define ADC_JSQR_JSQ4_Msk                 (0x1FUL << ADC_JSQR_JSQ4_Pos)        /*!< 0xF8000000 */

+#define ADC_JSQR_JSQ4                     ADC_JSQR_JSQ4_Msk                    /*!< ADC 4th conversion in injected sequence */

+#define ADC_JSQR_JSQ4_0                   (0x01UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x08000000 */

+#define ADC_JSQR_JSQ4_1                   (0x02UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x10000000 */

+#define ADC_JSQR_JSQ4_2                   (0x04UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x20000000 */

+#define ADC_JSQR_JSQ4_3                   (0x08UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x40000000 */

+#define ADC_JSQR_JSQ4_4                   (0x10UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_OFR1 register  ********************/

+#define ADC_OFR1_OFFSET1_Pos              (0U)

+#define ADC_OFR1_OFFSET1_Msk              (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR1_OFFSET1                  ADC_OFR1_OFFSET1_Msk                  /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */

+#define ADC_OFR1_OFFSET1_0                (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */

+#define ADC_OFR1_OFFSET1_1                (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */

+#define ADC_OFR1_OFFSET1_2                (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */

+#define ADC_OFR1_OFFSET1_3                (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */

+#define ADC_OFR1_OFFSET1_4                (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */

+#define ADC_OFR1_OFFSET1_5                (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */

+#define ADC_OFR1_OFFSET1_6                (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */

+#define ADC_OFR1_OFFSET1_7                (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */

+#define ADC_OFR1_OFFSET1_8                (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */

+#define ADC_OFR1_OFFSET1_9                (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */

+#define ADC_OFR1_OFFSET1_10               (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */

+#define ADC_OFR1_OFFSET1_11               (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */

+#define ADC_OFR1_OFFSET1_12               (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */

+#define ADC_OFR1_OFFSET1_13               (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */

+#define ADC_OFR1_OFFSET1_14               (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */

+#define ADC_OFR1_OFFSET1_15               (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */

+#define ADC_OFR1_OFFSET1_16               (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */

+#define ADC_OFR1_OFFSET1_17               (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */

+#define ADC_OFR1_OFFSET1_18               (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */

+#define ADC_OFR1_OFFSET1_19               (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */

+#define ADC_OFR1_OFFSET1_20               (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */

+#define ADC_OFR1_OFFSET1_21               (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */

+#define ADC_OFR1_OFFSET1_22               (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */

+#define ADC_OFR1_OFFSET1_23               (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */

+#define ADC_OFR1_OFFSET1_24               (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */

+#define ADC_OFR1_OFFSET1_25               (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR1_OFFSET1_CH_Pos           (26U)

+#define ADC_OFR1_OFFSET1_CH_Msk           (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR1_OFFSET1_CH               ADC_OFR1_OFFSET1_CH_Msk               /*!< ADC Channel selection for the data offset 1 */

+#define ADC_OFR1_OFFSET1_CH_0             (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR1_OFFSET1_CH_1             (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR1_OFFSET1_CH_2             (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR1_OFFSET1_CH_3             (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR1_OFFSET1_CH_4             (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR1_SSATE_Pos                (31U)

+#define ADC_OFR1_SSATE_Msk                (0x1UL << ADC_OFR1_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR1_SSATE                    ADC_OFR1_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR2 register  ********************/

+#define ADC_OFR2_OFFSET2_Pos              (0U)

+#define ADC_OFR2_OFFSET2_Msk              (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR2_OFFSET2                  ADC_OFR2_OFFSET2_Msk                  /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */

+#define ADC_OFR2_OFFSET2_0                (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */

+#define ADC_OFR2_OFFSET2_1                (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */

+#define ADC_OFR2_OFFSET2_2                (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */

+#define ADC_OFR2_OFFSET2_3                (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */

+#define ADC_OFR2_OFFSET2_4                (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */

+#define ADC_OFR2_OFFSET2_5                (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */

+#define ADC_OFR2_OFFSET2_6                (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */

+#define ADC_OFR2_OFFSET2_7                (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */

+#define ADC_OFR2_OFFSET2_8                (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */

+#define ADC_OFR2_OFFSET2_9                (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */

+#define ADC_OFR2_OFFSET2_10               (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */

+#define ADC_OFR2_OFFSET2_11               (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */

+#define ADC_OFR2_OFFSET2_12               (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */

+#define ADC_OFR2_OFFSET2_13               (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */

+#define ADC_OFR2_OFFSET2_14               (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */

+#define ADC_OFR2_OFFSET2_15               (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */

+#define ADC_OFR2_OFFSET2_16               (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */

+#define ADC_OFR2_OFFSET2_17               (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */

+#define ADC_OFR2_OFFSET2_18               (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */

+#define ADC_OFR2_OFFSET2_19               (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */

+#define ADC_OFR2_OFFSET2_20               (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */

+#define ADC_OFR2_OFFSET2_21               (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */

+#define ADC_OFR2_OFFSET2_22               (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */

+#define ADC_OFR2_OFFSET2_23               (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */

+#define ADC_OFR2_OFFSET2_24               (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */

+#define ADC_OFR2_OFFSET2_25               (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR2_OFFSET2_CH_Pos           (26U)

+#define ADC_OFR2_OFFSET2_CH_Msk           (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR2_OFFSET2_CH               ADC_OFR2_OFFSET2_CH_Msk               /*!< ADC Channel selection for the data offset 2 */

+#define ADC_OFR2_OFFSET2_CH_0             (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR2_OFFSET2_CH_1             (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR2_OFFSET2_CH_2             (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR2_OFFSET2_CH_3             (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR2_OFFSET2_CH_4             (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR2_SSATE_Pos                (31U)

+#define ADC_OFR2_SSATE_Msk                (0x1UL << ADC_OFR2_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR2_SSATE                    ADC_OFR2_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR3 register  ********************/

+#define ADC_OFR3_OFFSET3_Pos              (0U)

+#define ADC_OFR3_OFFSET3_Msk              (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR3_OFFSET3                  ADC_OFR3_OFFSET3_Msk                  /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */

+#define ADC_OFR3_OFFSET3_0                (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */

+#define ADC_OFR3_OFFSET3_1                (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */

+#define ADC_OFR3_OFFSET3_2                (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */

+#define ADC_OFR3_OFFSET3_3                (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */

+#define ADC_OFR3_OFFSET3_4                (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */

+#define ADC_OFR3_OFFSET3_5                (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */

+#define ADC_OFR3_OFFSET3_6                (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */

+#define ADC_OFR3_OFFSET3_7                (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */

+#define ADC_OFR3_OFFSET3_8                (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */

+#define ADC_OFR3_OFFSET3_9                (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */

+#define ADC_OFR3_OFFSET3_10               (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */

+#define ADC_OFR3_OFFSET3_11               (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */

+#define ADC_OFR3_OFFSET3_12               (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */

+#define ADC_OFR3_OFFSET3_13               (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */

+#define ADC_OFR3_OFFSET3_14               (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */

+#define ADC_OFR3_OFFSET3_15               (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */

+#define ADC_OFR3_OFFSET3_16               (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */

+#define ADC_OFR3_OFFSET3_17               (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */

+#define ADC_OFR3_OFFSET3_18               (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */

+#define ADC_OFR3_OFFSET3_19               (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */

+#define ADC_OFR3_OFFSET3_20               (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */

+#define ADC_OFR3_OFFSET3_21               (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */

+#define ADC_OFR3_OFFSET3_22               (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */

+#define ADC_OFR3_OFFSET3_23               (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */

+#define ADC_OFR3_OFFSET3_24               (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */

+#define ADC_OFR3_OFFSET3_25               (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR3_OFFSET3_CH_Pos           (26U)

+#define ADC_OFR3_OFFSET3_CH_Msk           (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR3_OFFSET3_CH               ADC_OFR3_OFFSET3_CH_Msk               /*!< ADC Channel selection for the data offset 3 */

+#define ADC_OFR3_OFFSET3_CH_0             (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR3_OFFSET3_CH_1             (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR3_OFFSET3_CH_2             (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR3_OFFSET3_CH_3             (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR3_OFFSET3_CH_4             (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR3_SSATE_Pos                (31U)

+#define ADC_OFR3_SSATE_Msk                (0x1UL << ADC_OFR3_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR3_SSATE                    ADC_OFR3_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR4 register  ********************/

+#define ADC_OFR4_OFFSET4_Pos              (0U)

+#define ADC_OFR4_OFFSET4_Msk              (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR4_OFFSET4                  ADC_OFR4_OFFSET4_Msk                  /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */

+#define ADC_OFR4_OFFSET4_0                (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */

+#define ADC_OFR4_OFFSET4_1                (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */

+#define ADC_OFR4_OFFSET4_2                (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */

+#define ADC_OFR4_OFFSET4_3                (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */

+#define ADC_OFR4_OFFSET4_4                (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */

+#define ADC_OFR4_OFFSET4_5                (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */

+#define ADC_OFR4_OFFSET4_6                (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */

+#define ADC_OFR4_OFFSET4_7                (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */

+#define ADC_OFR4_OFFSET4_8                (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */

+#define ADC_OFR4_OFFSET4_9                (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */

+#define ADC_OFR4_OFFSET4_10               (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */

+#define ADC_OFR4_OFFSET4_11               (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */

+#define ADC_OFR4_OFFSET4_12               (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */

+#define ADC_OFR4_OFFSET4_13               (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */

+#define ADC_OFR4_OFFSET4_14               (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */

+#define ADC_OFR4_OFFSET4_15               (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */

+#define ADC_OFR4_OFFSET4_16               (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */

+#define ADC_OFR4_OFFSET4_17               (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */

+#define ADC_OFR4_OFFSET4_18               (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */

+#define ADC_OFR4_OFFSET4_19               (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */

+#define ADC_OFR4_OFFSET4_20               (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */

+#define ADC_OFR4_OFFSET4_21               (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */

+#define ADC_OFR4_OFFSET4_22               (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */

+#define ADC_OFR4_OFFSET4_23               (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */

+#define ADC_OFR4_OFFSET4_24               (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */

+#define ADC_OFR4_OFFSET4_25               (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR4_OFFSET4_CH_Pos           (26U)

+#define ADC_OFR4_OFFSET4_CH_Msk           (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR4_OFFSET4_CH               ADC_OFR4_OFFSET4_CH_Msk               /*!< ADC Channel selection for the data offset 4 */

+#define ADC_OFR4_OFFSET4_CH_0             (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR4_OFFSET4_CH_1             (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR4_OFFSET4_CH_2             (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR4_OFFSET4_CH_3             (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR4_OFFSET4_CH_4             (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR4_SSATE_Pos                (31U)

+#define ADC_OFR4_SSATE_Msk                (0x1UL << ADC_OFR4_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR4_SSATE                    ADC_OFR4_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_JDR1 register  ********************/

+#define ADC_JDR1_JDATA_Pos                (0U)

+#define ADC_JDR1_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR1_JDATA                    ADC_JDR1_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR1_JDATA_0                  (0x00000001UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR1_JDATA_1                  (0x00000002UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR1_JDATA_2                  (0x00000004UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR1_JDATA_3                  (0x00000008UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR1_JDATA_4                  (0x00000010UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR1_JDATA_5                  (0x00000020UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR1_JDATA_6                  (0x00000040UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR1_JDATA_7                  (0x00000080UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR1_JDATA_8                  (0x00000100UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR1_JDATA_9                  (0x00000200UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR1_JDATA_10                 (0x00000400UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR1_JDATA_11                 (0x00000800UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR1_JDATA_12                 (0x00001000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR1_JDATA_13                 (0x00002000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR1_JDATA_14                 (0x00004000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR1_JDATA_15                 (0x00008000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR1_JDATA_16                 (0x00010000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR1_JDATA_17                 (0x00020000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR1_JDATA_18                 (0x00040000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR1_JDATA_19                 (0x00080000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR1_JDATA_20                 (0x00100000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR1_JDATA_21                 (0x00200000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR1_JDATA_22                 (0x00400000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR1_JDATA_23                 (0x00800000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR1_JDATA_24                 (0x01000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR1_JDATA_25                 (0x02000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR1_JDATA_26                 (0x04000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR1_JDATA_27                 (0x08000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR1_JDATA_28                 (0x10000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR1_JDATA_29                 (0x20000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR1_JDATA_30                 (0x40000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR1_JDATA_31                 (0x80000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR2 register  ********************/

+#define ADC_JDR2_JDATA_Pos                (0U)

+#define ADC_JDR2_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR2_JDATA                    ADC_JDR2_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR2_JDATA_0                  (0x00000001UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR2_JDATA_1                  (0x00000002UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR2_JDATA_2                  (0x00000004UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR2_JDATA_3                  (0x00000008UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR2_JDATA_4                  (0x00000010UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR2_JDATA_5                  (0x00000020UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR2_JDATA_6                  (0x00000040UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR2_JDATA_7                  (0x00000080UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR2_JDATA_8                  (0x00000100UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR2_JDATA_9                  (0x00000200UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR2_JDATA_10                 (0x00000400UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR2_JDATA_11                 (0x00000800UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR2_JDATA_12                 (0x00001000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR2_JDATA_13                 (0x00002000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR2_JDATA_14                 (0x00004000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR2_JDATA_15                 (0x00008000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR2_JDATA_16                 (0x00010000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR2_JDATA_17                 (0x00020000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR2_JDATA_18                 (0x00040000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR2_JDATA_19                 (0x00080000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR2_JDATA_20                 (0x00100000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR2_JDATA_21                 (0x00200000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR2_JDATA_22                 (0x00400000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR2_JDATA_23                 (0x00800000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR2_JDATA_24                 (0x01000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR2_JDATA_25                 (0x02000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR2_JDATA_26                 (0x04000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR2_JDATA_27                 (0x08000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR2_JDATA_28                 (0x10000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR2_JDATA_29                 (0x20000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR2_JDATA_30                 (0x40000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR2_JDATA_31                 (0x80000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR3 register  ********************/

+#define ADC_JDR3_JDATA_Pos                (0U)

+#define ADC_JDR3_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR3_JDATA                    ADC_JDR3_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR3_JDATA_0                  (0x00000001UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR3_JDATA_1                  (0x00000002UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR3_JDATA_2                  (0x00000004UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR3_JDATA_3                  (0x00000008UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR3_JDATA_4                  (0x00000010UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR3_JDATA_5                  (0x00000020UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR3_JDATA_6                  (0x00000040UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR3_JDATA_7                  (0x00000080UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR3_JDATA_8                  (0x00000100UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR3_JDATA_9                  (0x00000200UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR3_JDATA_10                 (0x00000400UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR3_JDATA_11                 (0x00000800UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR3_JDATA_12                 (0x00001000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR3_JDATA_13                 (0x00002000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR3_JDATA_14                 (0x00004000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR3_JDATA_15                 (0x00008000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR3_JDATA_16                 (0x00010000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR3_JDATA_17                 (0x00020000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR3_JDATA_18                 (0x00040000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR3_JDATA_19                 (0x00080000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR3_JDATA_20                 (0x00100000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR3_JDATA_21                 (0x00200000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR3_JDATA_22                 (0x00400000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR3_JDATA_23                 (0x00800000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR3_JDATA_24                 (0x01000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR3_JDATA_25                 (0x02000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR3_JDATA_26                 (0x04000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR3_JDATA_27                 (0x08000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR3_JDATA_28                 (0x10000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR3_JDATA_29                 (0x20000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR3_JDATA_30                 (0x40000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR3_JDATA_31                 (0x80000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR4 register  ********************/

+#define ADC_JDR4_JDATA_Pos                (0U)

+#define ADC_JDR4_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR4_JDATA                    ADC_JDR4_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR4_JDATA_0                  (0x00000001UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR4_JDATA_1                  (0x00000002UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR4_JDATA_2                  (0x00000004UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR4_JDATA_3                  (0x00000008UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR4_JDATA_4                  (0x00000010UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR4_JDATA_5                  (0x00000020UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR4_JDATA_6                  (0x00000040UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR4_JDATA_7                  (0x00000080UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR4_JDATA_8                  (0x00000100UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR4_JDATA_9                  (0x00000200UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR4_JDATA_10                 (0x00000400UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR4_JDATA_11                 (0x00000800UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR4_JDATA_12                 (0x00001000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR4_JDATA_13                 (0x00002000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR4_JDATA_14                 (0x00004000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR4_JDATA_15                 (0x00008000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR4_JDATA_16                 (0x00010000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR4_JDATA_17                 (0x00020000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR4_JDATA_18                 (0x00040000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR4_JDATA_19                 (0x00080000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR4_JDATA_20                 (0x00100000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR4_JDATA_21                 (0x00200000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR4_JDATA_22                 (0x00400000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR4_JDATA_23                 (0x00800000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR4_JDATA_24                 (0x01000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR4_JDATA_25                 (0x02000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR4_JDATA_26                 (0x04000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR4_JDATA_27                 (0x08000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR4_JDATA_28                 (0x10000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR4_JDATA_29                 (0x20000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR4_JDATA_30                 (0x40000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR4_JDATA_31                 (0x80000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_AWD2CR register  ********************/

+#define ADC_AWD2CR_AWD2CH_Pos             (0U)

+#define ADC_AWD2CR_AWD2CH_Msk             (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x000FFFFF */

+#define ADC_AWD2CR_AWD2CH                 ADC_AWD2CR_AWD2CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */

+#define ADC_AWD2CR_AWD2CH_0               (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000001 */

+#define ADC_AWD2CR_AWD2CH_1               (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000002 */

+#define ADC_AWD2CR_AWD2CH_2               (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000004 */

+#define ADC_AWD2CR_AWD2CH_3               (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000008 */

+#define ADC_AWD2CR_AWD2CH_4               (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000010 */

+#define ADC_AWD2CR_AWD2CH_5               (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000020 */

+#define ADC_AWD2CR_AWD2CH_6               (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000040 */

+#define ADC_AWD2CR_AWD2CH_7               (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000080 */

+#define ADC_AWD2CR_AWD2CH_8               (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000100 */

+#define ADC_AWD2CR_AWD2CH_9               (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000200 */

+#define ADC_AWD2CR_AWD2CH_10              (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000400 */

+#define ADC_AWD2CR_AWD2CH_11              (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000800 */

+#define ADC_AWD2CR_AWD2CH_12              (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00001000 */

+#define ADC_AWD2CR_AWD2CH_13              (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00002000 */

+#define ADC_AWD2CR_AWD2CH_14              (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00004000 */

+#define ADC_AWD2CR_AWD2CH_15              (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00008000 */

+#define ADC_AWD2CR_AWD2CH_16              (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00010000 */

+#define ADC_AWD2CR_AWD2CH_17              (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00020000 */

+#define ADC_AWD2CR_AWD2CH_18              (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */

+#define ADC_AWD2CR_AWD2CH_19              (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_AWD3CR register  ********************/

+#define ADC_AWD3CR_AWD3CH_Pos             (0U)

+#define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x000FFFFF */

+#define ADC_AWD3CR_AWD3CH                 ADC_AWD3CR_AWD3CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */

+#define ADC_AWD3CR_AWD3CH_0               (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000001 */

+#define ADC_AWD3CR_AWD3CH_1               (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000002 */

+#define ADC_AWD3CR_AWD3CH_2               (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000004 */

+#define ADC_AWD3CR_AWD3CH_3               (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000008 */

+#define ADC_AWD3CR_AWD3CH_4               (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000010 */

+#define ADC_AWD3CR_AWD3CH_5               (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000020 */

+#define ADC_AWD3CR_AWD3CH_6               (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000040 */

+#define ADC_AWD3CR_AWD3CH_7               (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000080 */

+#define ADC_AWD3CR_AWD3CH_8               (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000100 */

+#define ADC_AWD3CR_AWD3CH_9               (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000200 */

+#define ADC_AWD3CR_AWD3CH_10              (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000400 */

+#define ADC_AWD3CR_AWD3CH_11              (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000800 */

+#define ADC_AWD3CR_AWD3CH_12              (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00001000 */

+#define ADC_AWD3CR_AWD3CH_13              (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00002000 */

+#define ADC_AWD3CR_AWD3CH_14              (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00004000 */

+#define ADC_AWD3CR_AWD3CH_15              (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00008000 */

+#define ADC_AWD3CR_AWD3CH_16              (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00010000 */

+#define ADC_AWD3CR_AWD3CH_17              (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00020000 */

+#define ADC_AWD3CR_AWD3CH_18              (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */

+#define ADC_AWD3CR_AWD3CH_19              (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_DIFSEL register  ********************/

+#define ADC_DIFSEL_DIFSEL_Pos             (0U)

+#define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */

+#define ADC_DIFSEL_DIFSEL                 ADC_DIFSEL_DIFSEL_Msk                 /*!< ADC differential modes for channels 1 to 18 */

+#define ADC_DIFSEL_DIFSEL_0               (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000001 */

+#define ADC_DIFSEL_DIFSEL_1               (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000002 */

+#define ADC_DIFSEL_DIFSEL_2               (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000004 */

+#define ADC_DIFSEL_DIFSEL_3               (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000008 */

+#define ADC_DIFSEL_DIFSEL_4               (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000010 */

+#define ADC_DIFSEL_DIFSEL_5               (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000020 */

+#define ADC_DIFSEL_DIFSEL_6               (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000040 */

+#define ADC_DIFSEL_DIFSEL_7               (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000080 */

+#define ADC_DIFSEL_DIFSEL_8               (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000100 */

+#define ADC_DIFSEL_DIFSEL_9               (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000200 */

+#define ADC_DIFSEL_DIFSEL_10              (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000400 */

+#define ADC_DIFSEL_DIFSEL_11              (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000800 */

+#define ADC_DIFSEL_DIFSEL_12              (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00001000 */

+#define ADC_DIFSEL_DIFSEL_13              (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00002000 */

+#define ADC_DIFSEL_DIFSEL_14              (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00004000 */

+#define ADC_DIFSEL_DIFSEL_15              (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00008000 */

+#define ADC_DIFSEL_DIFSEL_16              (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00010000 */

+#define ADC_DIFSEL_DIFSEL_17              (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00020000 */

+#define ADC_DIFSEL_DIFSEL_18              (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00040000 */

+#define ADC_DIFSEL_DIFSEL_19              (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_CALFACT register  ********************/

+#define ADC_CALFACT_CALFACT_S_Pos         (0U)

+#define ADC_CALFACT_CALFACT_S_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */

+#define ADC_CALFACT_CALFACT_S             ADC_CALFACT_CALFACT_S_Msk              /*!< ADC calibration factors in single-ended mode */

+#define ADC_CALFACT_CALFACT_S_0           (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */

+#define ADC_CALFACT_CALFACT_S_1           (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */

+#define ADC_CALFACT_CALFACT_S_2           (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */

+#define ADC_CALFACT_CALFACT_S_3           (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */

+#define ADC_CALFACT_CALFACT_S_4           (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */

+#define ADC_CALFACT_CALFACT_S_5           (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */

+#define ADC_CALFACT_CALFACT_S_6           (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */

+#define ADC_CALFACT_CALFACT_S_7           (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */

+#define ADC_CALFACT_CALFACT_S_8           (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */

+#define ADC_CALFACT_CALFACT_S_9           (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */

+#define ADC_CALFACT_CALFACT_S_10          (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */

+#define ADC_CALFACT_CALFACT_D_Pos         (16U)

+#define ADC_CALFACT_CALFACT_D_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */

+#define ADC_CALFACT_CALFACT_D             ADC_CALFACT_CALFACT_D_Msk              /*!< ADC calibration factors in differential mode */

+#define ADC_CALFACT_CALFACT_D_0           (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */

+#define ADC_CALFACT_CALFACT_D_1           (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */

+#define ADC_CALFACT_CALFACT_D_2           (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */

+#define ADC_CALFACT_CALFACT_D_3           (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */

+#define ADC_CALFACT_CALFACT_D_4           (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */

+#define ADC_CALFACT_CALFACT_D_5           (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */

+#define ADC_CALFACT_CALFACT_D_6           (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */

+#define ADC_CALFACT_CALFACT_D_7           (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */

+#define ADC_CALFACT_CALFACT_D_8           (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */

+#define ADC_CALFACT_CALFACT_D_9           (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */

+#define ADC_CALFACT_CALFACT_D_10          (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */

+

+/********************  Bit definition for ADC_CALFACT2 register  ********************/

+#define ADC_CALFACT2_LINCALFACT_Pos       (0U)

+#define ADC_CALFACT2_LINCALFACT_Msk       (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */

+#define ADC_CALFACT2_LINCALFACT           ADC_CALFACT2_LINCALFACT_Msk                   /*!< ADC Linearity calibration factors */

+#define ADC_CALFACT2_LINCALFACT_0         (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */

+#define ADC_CALFACT2_LINCALFACT_1         (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */

+#define ADC_CALFACT2_LINCALFACT_2         (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */

+#define ADC_CALFACT2_LINCALFACT_3         (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */

+#define ADC_CALFACT2_LINCALFACT_4         (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */

+#define ADC_CALFACT2_LINCALFACT_5         (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */

+#define ADC_CALFACT2_LINCALFACT_6         (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */

+#define ADC_CALFACT2_LINCALFACT_7         (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */

+#define ADC_CALFACT2_LINCALFACT_8         (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */

+#define ADC_CALFACT2_LINCALFACT_9         (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */

+#define ADC_CALFACT2_LINCALFACT_10        (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */

+#define ADC_CALFACT2_LINCALFACT_11        (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */

+#define ADC_CALFACT2_LINCALFACT_12        (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */

+#define ADC_CALFACT2_LINCALFACT_13        (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */

+#define ADC_CALFACT2_LINCALFACT_14        (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */

+#define ADC_CALFACT2_LINCALFACT_15        (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */

+#define ADC_CALFACT2_LINCALFACT_16        (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */

+#define ADC_CALFACT2_LINCALFACT_17        (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */

+#define ADC_CALFACT2_LINCALFACT_18        (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */

+#define ADC_CALFACT2_LINCALFACT_19        (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */

+#define ADC_CALFACT2_LINCALFACT_20        (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */

+#define ADC_CALFACT2_LINCALFACT_21        (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */

+#define ADC_CALFACT2_LINCALFACT_22        (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */

+#define ADC_CALFACT2_LINCALFACT_23        (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */

+#define ADC_CALFACT2_LINCALFACT_24        (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */

+#define ADC_CALFACT2_LINCALFACT_25        (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */

+#define ADC_CALFACT2_LINCALFACT_26        (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */

+#define ADC_CALFACT2_LINCALFACT_27        (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */

+#define ADC_CALFACT2_LINCALFACT_28        (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */

+#define ADC_CALFACT2_LINCALFACT_29        (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */

+

+/*************************  ADC Common registers  *****************************/

+/********************  Bit definition for ADC_CSR register  ********************/

+#define ADC_CSR_ADRDY_MST_Pos             (0U)

+#define ADC_CSR_ADRDY_MST_Msk             (0x1UL << ADC_CSR_ADRDY_MST_Pos)     /*!< 0x00000001 */

+#define ADC_CSR_ADRDY_MST                 ADC_CSR_ADRDY_MST_Msk                /*!< Master ADC ready */

+#define ADC_CSR_EOSMP_MST_Pos             (1U)

+#define ADC_CSR_EOSMP_MST_Msk             (0x1UL << ADC_CSR_EOSMP_MST_Pos)     /*!< 0x00000002 */

+#define ADC_CSR_EOSMP_MST                 ADC_CSR_EOSMP_MST_Msk                /*!< End of sampling phase flag of the master ADC */

+#define ADC_CSR_EOC_MST_Pos               (2U)

+#define ADC_CSR_EOC_MST_Msk               (0x1UL << ADC_CSR_EOC_MST_Pos)       /*!< 0x00000004 */

+#define ADC_CSR_EOC_MST                   ADC_CSR_EOC_MST_Msk                  /*!< End of regular conversion of the master ADC */

+#define ADC_CSR_EOS_MST_Pos               (3U)

+#define ADC_CSR_EOS_MST_Msk               (0x1UL << ADC_CSR_EOS_MST_Pos)       /*!< 0x00000008 */

+#define ADC_CSR_EOS_MST                   ADC_CSR_EOS_MST_Msk                  /*!< End of regular sequence flag of the master ADC */

+#define ADC_CSR_OVR_MST_Pos               (4U)

+#define ADC_CSR_OVR_MST_Msk               (0x1UL << ADC_CSR_OVR_MST_Pos)       /*!< 0x00000010 */

+#define ADC_CSR_OVR_MST                   ADC_CSR_OVR_MST_Msk                  /*!< Overrun flag of the master ADC */

+#define ADC_CSR_JEOC_MST_Pos              (5U)

+#define ADC_CSR_JEOC_MST_Msk              (0x1UL << ADC_CSR_JEOC_MST_Pos)      /*!< 0x00000020 */

+#define ADC_CSR_JEOC_MST                  ADC_CSR_JEOC_MST_Msk                 /*!< End of injected conversion of the master ADC */

+#define ADC_CSR_JEOS_MST_Pos              (6U)

+#define ADC_CSR_JEOS_MST_Msk              (0x1UL << ADC_CSR_JEOS_MST_Pos)      /*!< 0x00000040 */

+#define ADC_CSR_JEOS_MST                  ADC_CSR_JEOS_MST_Msk                 /*!< End of injected sequence flag of the master ADC */

+#define ADC_CSR_AWD1_MST_Pos              (7U)

+#define ADC_CSR_AWD1_MST_Msk              (0x1UL << ADC_CSR_AWD1_MST_Pos)      /*!< 0x00000080 */

+#define ADC_CSR_AWD1_MST                  ADC_CSR_AWD1_MST_Msk                 /*!< Analog watchdog 1 flag of the master ADC */

+#define ADC_CSR_AWD2_MST_Pos              (8U)

+#define ADC_CSR_AWD2_MST_Msk              (0x1UL << ADC_CSR_AWD2_MST_Pos)      /*!< 0x00000100 */

+#define ADC_CSR_AWD2_MST                  ADC_CSR_AWD2_MST_Msk                 /*!< Analog watchdog 2 flag of the master ADC */

+#define ADC_CSR_AWD3_MST_Pos              (9U)

+#define ADC_CSR_AWD3_MST_Msk              (0x1UL << ADC_CSR_AWD3_MST_Pos)      /*!< 0x00000200 */

+#define ADC_CSR_AWD3_MST                  ADC_CSR_AWD3_MST_Msk                 /*!< Analog watchdog 3 flag of the master ADC */

+#define ADC_CSR_JQOVF_MST_Pos             (10U)

+#define ADC_CSR_JQOVF_MST_Msk             (0x1UL << ADC_CSR_JQOVF_MST_Pos)     /*!< 0x00000400 */

+#define ADC_CSR_JQOVF_MST                 ADC_CSR_JQOVF_MST_Msk                /*!< Injected context queue overflow flag of the master ADC */

+#define ADC_CSR_ADRDY_SLV_Pos             (16U)

+#define ADC_CSR_ADRDY_SLV_Msk             (0x1UL << ADC_CSR_ADRDY_SLV_Pos)     /*!< 0x00010000 */

+#define ADC_CSR_ADRDY_SLV                 ADC_CSR_ADRDY_SLV_Msk                /*!< Slave ADC ready */

+#define ADC_CSR_EOSMP_SLV_Pos             (17U)

+#define ADC_CSR_EOSMP_SLV_Msk             (0x1UL << ADC_CSR_EOSMP_SLV_Pos)     /*!< 0x00020000 */

+#define ADC_CSR_EOSMP_SLV                 ADC_CSR_EOSMP_SLV_Msk                /*!< End of sampling phase flag of the slave ADC */

+#define ADC_CSR_EOC_SLV_Pos               (18U)

+#define ADC_CSR_EOC_SLV_Msk               (0x1UL << ADC_CSR_EOC_SLV_Pos)       /*!< 0x00040000 */

+#define ADC_CSR_EOC_SLV                   ADC_CSR_EOC_SLV_Msk                  /*!< End of regular conversion of the slave ADC */

+#define ADC_CSR_EOS_SLV_Pos               (19U)

+#define ADC_CSR_EOS_SLV_Msk               (0x1UL << ADC_CSR_EOS_SLV_Pos)       /*!< 0x00080000 */

+#define ADC_CSR_EOS_SLV                   ADC_CSR_EOS_SLV_Msk                  /*!< End of regular sequence flag of the slave ADC */

+#define ADC_CSR_OVR_SLV_Pos               (20U)

+#define ADC_CSR_OVR_SLV_Msk               (0x1UL << ADC_CSR_OVR_SLV_Pos)       /*!< 0x00100000 */

+#define ADC_CSR_OVR_SLV                   ADC_CSR_OVR_SLV_Msk                  /*!< Overrun flag of the slave ADC */

+#define ADC_CSR_JEOC_SLV_Pos              (21U)

+#define ADC_CSR_JEOC_SLV_Msk              (0x1UL << ADC_CSR_JEOC_SLV_Pos)      /*!< 0x00200000 */

+#define ADC_CSR_JEOC_SLV                  ADC_CSR_JEOC_SLV_Msk                 /*!< End of injected conversion of the slave ADC */

+#define ADC_CSR_JEOS_SLV_Pos              (22U)

+#define ADC_CSR_JEOS_SLV_Msk              (0x1UL << ADC_CSR_JEOS_SLV_Pos)      /*!< 0x00400000 */

+#define ADC_CSR_JEOS_SLV                  ADC_CSR_JEOS_SLV_Msk                 /*!< End of injected sequence flag of the slave ADC */

+#define ADC_CSR_AWD1_SLV_Pos              (23U)

+#define ADC_CSR_AWD1_SLV_Msk              (0x1UL << ADC_CSR_AWD1_SLV_Pos)      /*!< 0x00800000 */

+#define ADC_CSR_AWD1_SLV                  ADC_CSR_AWD1_SLV_Msk                 /*!< Analog watchdog 1 flag of the slave ADC */

+#define ADC_CSR_AWD2_SLV_Pos              (24U)

+#define ADC_CSR_AWD2_SLV_Msk              (0x1UL << ADC_CSR_AWD2_SLV_Pos)      /*!< 0x01000000 */

+#define ADC_CSR_AWD2_SLV                  ADC_CSR_AWD2_SLV_Msk                 /*!< Analog watchdog 2 flag of the slave ADC */

+#define ADC_CSR_AWD3_SLV_Pos              (25U)

+#define ADC_CSR_AWD3_SLV_Msk              (0x1UL << ADC_CSR_AWD3_SLV_Pos)      /*!< 0x02000000 */

+#define ADC_CSR_AWD3_SLV                  ADC_CSR_AWD3_SLV_Msk                 /*!< Analog watchdog 3 flag of the slave ADC */

+#define ADC_CSR_JQOVF_SLV_Pos             (26U)

+#define ADC_CSR_JQOVF_SLV_Msk             (0x1UL << ADC_CSR_JQOVF_SLV_Pos)     /*!< 0x04000000 */

+#define ADC_CSR_JQOVF_SLV                 ADC_CSR_JQOVF_SLV_Msk                /*!< Injected context queue overflow flag of the slave ADC */

+

+/********************  Bit definition for ADC_CCR register  ********************/

+#define ADC_CCR_DUAL_Pos                  (0U)

+#define ADC_CCR_DUAL_Msk                  (0x1FUL << ADC_CCR_DUAL_Pos)          /*!< 0x0000001F */

+#define ADC_CCR_DUAL                      ADC_CCR_DUAL_Msk                      /*!< Dual ADC mode selection */

+#define ADC_CCR_DUAL_0                    (0x01UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000001 */

+#define ADC_CCR_DUAL_1                    (0x02UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000002 */

+#define ADC_CCR_DUAL_2                    (0x04UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000004 */

+#define ADC_CCR_DUAL_3                    (0x08UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000008 */

+#define ADC_CCR_DUAL_4                    (0x10UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000010 */

+

+#define ADC_CCR_DELAY_Pos                 (8U)

+#define ADC_CCR_DELAY_Msk                 (0xFUL << ADC_CCR_DELAY_Pos)          /*!< 0x00000F00 */

+#define ADC_CCR_DELAY                     ADC_CCR_DELAY_Msk                     /*!< Delay between 2 sampling phases */

+#define ADC_CCR_DELAY_0                   (0x1UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000100 */

+#define ADC_CCR_DELAY_1                   (0x2UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000200 */

+#define ADC_CCR_DELAY_2                   (0x4UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000400 */

+#define ADC_CCR_DELAY_3                   (0x8UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000800 */

+

+

+#define ADC_CCR_DAMDF_Pos                 (14U)

+#define ADC_CCR_DAMDF_Msk                 (0x3UL << ADC_CCR_DAMDF_Pos)          /*!< 0x0000C000 */

+#define ADC_CCR_DAMDF                     ADC_CCR_DAMDF_Msk                     /*!< Dual ADC mode Data format */

+#define ADC_CCR_DAMDF_0                   (0x1UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00004000 */

+#define ADC_CCR_DAMDF_1                   (0x2UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00008000 */

+

+#define ADC_CCR_CKMODE_Pos                (16U)

+#define ADC_CCR_CKMODE_Msk                (0x3UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00030000 */

+#define ADC_CCR_CKMODE                    ADC_CCR_CKMODE_Msk                    /*!< ADC clock mode */

+#define ADC_CCR_CKMODE_0                  (0x1UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00010000 */

+#define ADC_CCR_CKMODE_1                  (0x2UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00020000 */

+

+#define ADC_CCR_PRESC_Pos                 (18U)

+#define ADC_CCR_PRESC_Msk                 (0xFUL << ADC_CCR_PRESC_Pos)          /*!< 0x003C0000 */

+#define ADC_CCR_PRESC                     ADC_CCR_PRESC_Msk                     /*!< ADC prescaler */

+#define ADC_CCR_PRESC_0                   (0x1UL << ADC_CCR_PRESC_Pos)          /*!< 0x00040000 */

+#define ADC_CCR_PRESC_1                   (0x2UL << ADC_CCR_PRESC_Pos)          /*!< 0x00080000 */

+#define ADC_CCR_PRESC_2                   (0x4UL << ADC_CCR_PRESC_Pos)          /*!< 0x00100000 */

+#define ADC_CCR_PRESC_3                   (0x8UL << ADC_CCR_PRESC_Pos)          /*!< 0x00200000 */

+

+#define ADC_CCR_VREFEN_Pos                (22U)

+#define ADC_CCR_VREFEN_Msk                (0x1UL << ADC_CCR_VREFEN_Pos)         /*!< 0x00400000 */

+#define ADC_CCR_VREFEN                    ADC_CCR_VREFEN_Msk                    /*!< VREFINT enable */

+#define ADC_CCR_TSEN_Pos                  (23U)

+#define ADC_CCR_TSEN_Msk                  (0x1UL << ADC_CCR_TSEN_Pos)           /*!< 0x00800000 */

+#define ADC_CCR_TSEN                      ADC_CCR_TSEN_Msk                      /*!< Temperature sensor enable */

+#define ADC_CCR_VBATEN_Pos                (24U)

+#define ADC_CCR_VBATEN_Msk                (0x1UL << ADC_CCR_VBATEN_Pos)         /*!< 0x01000000 */

+#define ADC_CCR_VBATEN                    ADC_CCR_VBATEN_Msk                    /*!< VBAT enable */

+

+/********************  Bit definition for ADC_CDR register  *******************/

+#define ADC_CDR_RDATA_MST_Pos             (0U)

+#define ADC_CDR_RDATA_MST_Msk             (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)   /*!< 0x0000FFFF */

+#define ADC_CDR_RDATA_MST                 ADC_CDR_RDATA_MST_Msk                 /*!< ADC multimode master group regular conversion data */

+

+#define ADC_CDR_RDATA_SLV_Pos             (16U)

+#define ADC_CDR_RDATA_SLV_Msk             (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)   /*!< 0xFFFF0000 */

+#define ADC_CDR_RDATA_SLV                 ADC_CDR_RDATA_SLV_Msk                 /*!< ADC multimode slave group regular conversion data */

+

+/********************  Bit definition for ADC_CDR2 register  ******************/

+#define ADC_CDR2_RDATA_ALT_Pos            (0U)

+#define ADC_CDR2_RDATA_ALT_Msk            (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */

+#define ADC_CDR2_RDATA_ALT                ADC_CDR2_RDATA_ALT_Msk                   /*!< Regular data of the master/slave alternated ADCs */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                   VREFBUF                                  */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for VREFBUF_CSR register  ****************/

+#define VREFBUF_CSR_ENVR_Pos        (0U)

+#define VREFBUF_CSR_ENVR_Msk        (0x1UL << VREFBUF_CSR_ENVR_Pos)            /*!< 0x00000001 */

+#define VREFBUF_CSR_ENVR            VREFBUF_CSR_ENVR_Msk                       /*!<Voltage reference buffer enable */

+#define VREFBUF_CSR_HIZ_Pos         (1U)

+#define VREFBUF_CSR_HIZ_Msk         (0x1UL << VREFBUF_CSR_HIZ_Pos)             /*!< 0x00000002 */

+#define VREFBUF_CSR_HIZ             VREFBUF_CSR_HIZ_Msk                        /*!<High impedance mode             */

+#define VREFBUF_CSR_VRR_Pos         (3U)

+#define VREFBUF_CSR_VRR_Msk         (0x1UL << VREFBUF_CSR_VRR_Pos)             /*!< 0x00000008 */

+#define VREFBUF_CSR_VRR             VREFBUF_CSR_VRR_Msk                        /*!<Voltage reference buffer ready  */

+#define VREFBUF_CSR_VRS_Pos         (4U)

+#define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */

+#define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */

+

+#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */

+#define VREFBUF_CSR_VRS_OUT2_Pos    (4U)

+#define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */

+#define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */

+#define VREFBUF_CSR_VRS_OUT3_Pos    (5U)

+#define VREFBUF_CSR_VRS_OUT3_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)        /*!< 0x00000020 */

+#define VREFBUF_CSR_VRS_OUT3        VREFBUF_CSR_VRS_OUT3_Msk                   /*!<Voltage reference VREF_OUT3     */

+#define VREFBUF_CSR_VRS_OUT4_Pos    (4U)

+#define VREFBUF_CSR_VRS_OUT4_Msk    (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)        /*!< 0x00000030 */

+#define VREFBUF_CSR_VRS_OUT4        VREFBUF_CSR_VRS_OUT4_Msk                   /*!<Voltage reference VREF_OUT4     */

+

+/*******************  Bit definition for VREFBUF_CCR register  ****************/

+#define VREFBUF_CCR_TRIM_Pos        (0U)

+#define VREFBUF_CCR_TRIM_Msk        (0x3FUL << VREFBUF_CCR_TRIM_Pos)           /*!< 0x0000003F */

+#define VREFBUF_CCR_TRIM            VREFBUF_CCR_TRIM_Msk                       /*!<TRIM[5:0] bits (Trimming code)  */

+

+/******************************************************************************/

+/*                                                                            */

+/*                 Flexible Datarate Controller Area Network                  */

+/*                                                                            */

+/******************************************************************************/

+/*!<FDCAN control and status registers */

+/*****************  Bit definition for FDCAN_CREL register  *******************/

+#define FDCAN_CREL_DAY_Pos        (0U)

+#define FDCAN_CREL_DAY_Msk        (0xFFUL << FDCAN_CREL_DAY_Pos)               /*!< 0x000000FF */

+#define FDCAN_CREL_DAY            FDCAN_CREL_DAY_Msk                           /*!<Timestamp Day                           */

+#define FDCAN_CREL_MON_Pos        (8U)

+#define FDCAN_CREL_MON_Msk        (0xFFUL << FDCAN_CREL_MON_Pos)               /*!< 0x0000FF00 */

+#define FDCAN_CREL_MON            FDCAN_CREL_MON_Msk                           /*!<Timestamp Month                         */

+#define FDCAN_CREL_YEAR_Pos       (16U)

+#define FDCAN_CREL_YEAR_Msk       (0xFUL << FDCAN_CREL_YEAR_Pos)               /*!< 0x000F0000 */

+#define FDCAN_CREL_YEAR           FDCAN_CREL_YEAR_Msk                          /*!<Timestamp Year                          */

+#define FDCAN_CREL_SUBSTEP_Pos    (20U)

+#define FDCAN_CREL_SUBSTEP_Msk    (0xFUL << FDCAN_CREL_SUBSTEP_Pos)            /*!< 0x00F00000 */

+#define FDCAN_CREL_SUBSTEP        FDCAN_CREL_SUBSTEP_Msk                       /*!<Sub-step of Core release                */

+#define FDCAN_CREL_STEP_Pos       (24U)

+#define FDCAN_CREL_STEP_Msk       (0xFUL << FDCAN_CREL_STEP_Pos)               /*!< 0x0F000000 */

+#define FDCAN_CREL_STEP           FDCAN_CREL_STEP_Msk                          /*!<Step of Core release                    */

+#define FDCAN_CREL_REL_Pos        (28U)

+#define FDCAN_CREL_REL_Msk        (0xFUL << FDCAN_CREL_REL_Pos)                /*!< 0xF0000000 */

+#define FDCAN_CREL_REL            FDCAN_CREL_REL_Msk                           /*!<Core release                            */

+

+/*****************  Bit definition for FDCAN_ENDN register  *******************/

+#define FDCAN_ENDN_ETV_Pos        (0U)

+#define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endiannes Test Value                    */

+

+/*****************  Bit definition for FDCAN_DBTP register  *******************/

+#define FDCAN_DBTP_DSJW_Pos       (0U)

+#define FDCAN_DBTP_DSJW_Msk       (0xFUL << FDCAN_DBTP_DSJW_Pos)               /*!< 0x0000000F */

+#define FDCAN_DBTP_DSJW           FDCAN_DBTP_DSJW_Msk                          /*!<Synchronization Jump Width              */

+#define FDCAN_DBTP_DTSEG2_Pos     (4U)

+#define FDCAN_DBTP_DTSEG2_Msk     (0xFUL << FDCAN_DBTP_DTSEG2_Pos)             /*!< 0x000000F0 */

+#define FDCAN_DBTP_DTSEG2         FDCAN_DBTP_DTSEG2_Msk                        /*!<Data time segment after sample point    */

+#define FDCAN_DBTP_DTSEG1_Pos     (8U)

+#define FDCAN_DBTP_DTSEG1_Msk     (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)            /*!< 0x00001F00 */

+#define FDCAN_DBTP_DTSEG1         FDCAN_DBTP_DTSEG1_Msk                        /*!<Data time segment before sample point   */

+#define FDCAN_DBTP_DBRP_Pos       (16U)

+#define FDCAN_DBTP_DBRP_Msk       (0x1FUL << FDCAN_DBTP_DBRP_Pos)              /*!< 0x001F0000 */

+#define FDCAN_DBTP_DBRP           FDCAN_DBTP_DBRP_Msk                          /*!<Data BIt Rate Prescaler                 */

+#define FDCAN_DBTP_TDC_Pos        (23U)

+#define FDCAN_DBTP_TDC_Msk        (0x1UL << FDCAN_DBTP_TDC_Pos)                /*!< 0x00800000 */

+#define FDCAN_DBTP_TDC            FDCAN_DBTP_TDC_Msk                           /*!<Transceiver Delay Compensation          */

+

+/*****************  Bit definition for FDCAN_TEST register  *******************/

+#define FDCAN_TEST_LBCK_Pos       (4U)

+#define FDCAN_TEST_LBCK_Msk       (0x1UL << FDCAN_TEST_LBCK_Pos)               /*!< 0x00000010 */

+#define FDCAN_TEST_LBCK           FDCAN_TEST_LBCK_Msk                          /*!<Loop Back mode                           */

+#define FDCAN_TEST_TX_Pos         (5U)

+#define FDCAN_TEST_TX_Msk         (0x3UL << FDCAN_TEST_TX_Pos)                 /*!< 0x00000060 */

+#define FDCAN_TEST_TX             FDCAN_TEST_TX_Msk                            /*!<Control of Transmit Pin                  */

+#define FDCAN_TEST_RX_Pos         (7U)

+#define FDCAN_TEST_RX_Msk         (0x1UL << FDCAN_TEST_RX_Pos)                 /*!< 0x00000080 */

+#define FDCAN_TEST_RX             FDCAN_TEST_RX_Msk                            /*!<Receive Pin                              */

+

+/*****************  Bit definition for FDCAN_RWD register  ********************/

+#define FDCAN_RWD_WDC_Pos         (0U)

+#define FDCAN_RWD_WDC_Msk         (0xFFUL << FDCAN_RWD_WDC_Pos)                /*!< 0x000000FF */

+#define FDCAN_RWD_WDC             FDCAN_RWD_WDC_Msk                            /*!<Watchdog configuration                   */

+#define FDCAN_RWD_WDV_Pos         (8U)

+#define FDCAN_RWD_WDV_Msk         (0xFFUL << FDCAN_RWD_WDV_Pos)                /*!< 0x0000FF00 */

+#define FDCAN_RWD_WDV             FDCAN_RWD_WDV_Msk                            /*!<Watchdog value                           */

+

+/*****************  Bit definition for FDCAN_CCCR register  ********************/

+#define FDCAN_CCCR_INIT_Pos       (0U)

+#define FDCAN_CCCR_INIT_Msk       (0x1UL << FDCAN_CCCR_INIT_Pos)               /*!< 0x00000001 */

+#define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!<Initialization                           */

+#define FDCAN_CCCR_CCE_Pos        (1U)

+#define FDCAN_CCCR_CCE_Msk        (0x1UL << FDCAN_CCCR_CCE_Pos)                /*!< 0x00000002 */

+#define FDCAN_CCCR_CCE            FDCAN_CCCR_CCE_Msk                           /*!<Configuration Change Enable              */

+#define FDCAN_CCCR_ASM_Pos        (2U)

+#define FDCAN_CCCR_ASM_Msk        (0x1UL << FDCAN_CCCR_ASM_Pos)                /*!< 0x00000004 */

+#define FDCAN_CCCR_ASM            FDCAN_CCCR_ASM_Msk                           /*!<ASM Restricted Operation Mode            */

+#define FDCAN_CCCR_CSA_Pos        (3U)

+#define FDCAN_CCCR_CSA_Msk        (0x1UL << FDCAN_CCCR_CSA_Pos)                /*!< 0x00000008 */

+#define FDCAN_CCCR_CSA            FDCAN_CCCR_CSA_Msk                           /*!<Clock Stop Acknowledge                   */

+#define FDCAN_CCCR_CSR_Pos        (4U)

+#define FDCAN_CCCR_CSR_Msk        (0x1UL << FDCAN_CCCR_CSR_Pos)                /*!< 0x00000010 */

+#define FDCAN_CCCR_CSR            FDCAN_CCCR_CSR_Msk                           /*!<Clock Stop Request                       */

+#define FDCAN_CCCR_MON_Pos        (5U)

+#define FDCAN_CCCR_MON_Msk        (0x1UL << FDCAN_CCCR_MON_Pos)                /*!< 0x00000020 */

+#define FDCAN_CCCR_MON            FDCAN_CCCR_MON_Msk                           /*!<Bus Monitoring Mode                      */

+#define FDCAN_CCCR_DAR_Pos        (6U)

+#define FDCAN_CCCR_DAR_Msk        (0x1UL << FDCAN_CCCR_DAR_Pos)                /*!< 0x00000040 */

+#define FDCAN_CCCR_DAR            FDCAN_CCCR_DAR_Msk                           /*!<Disable Automatic Retransmission         */

+#define FDCAN_CCCR_TEST_Pos       (7U)

+#define FDCAN_CCCR_TEST_Msk       (0x1UL << FDCAN_CCCR_TEST_Pos)               /*!< 0x00000080 */

+#define FDCAN_CCCR_TEST           FDCAN_CCCR_TEST_Msk                          /*!<Test Mode Enable                         */

+#define FDCAN_CCCR_FDOE_Pos       (8U)

+#define FDCAN_CCCR_FDOE_Msk       (0x1UL << FDCAN_CCCR_FDOE_Pos)               /*!< 0x00000100 */

+#define FDCAN_CCCR_FDOE           FDCAN_CCCR_FDOE_Msk                          /*!<FD Operation Enable                      */

+#define FDCAN_CCCR_BRSE_Pos       (9U)

+#define FDCAN_CCCR_BRSE_Msk       (0x1UL << FDCAN_CCCR_BRSE_Pos)               /*!< 0x00000200 */

+#define FDCAN_CCCR_BRSE           FDCAN_CCCR_BRSE_Msk                          /*!<FDCAN Bit Rate Switching                 */

+#define FDCAN_CCCR_PXHD_Pos       (12U)

+#define FDCAN_CCCR_PXHD_Msk       (0x1UL << FDCAN_CCCR_PXHD_Pos)               /*!< 0x00001000 */

+#define FDCAN_CCCR_PXHD           FDCAN_CCCR_PXHD_Msk                          /*!<Protocol Exception Handling Disable      */

+#define FDCAN_CCCR_EFBI_Pos       (13U)

+#define FDCAN_CCCR_EFBI_Msk       (0x1UL << FDCAN_CCCR_EFBI_Pos)               /*!< 0x00002000 */

+#define FDCAN_CCCR_EFBI           FDCAN_CCCR_EFBI_Msk                          /*!<Edge Filtering during Bus Integration    */

+#define FDCAN_CCCR_TXP_Pos        (14U)

+#define FDCAN_CCCR_TXP_Msk        (0x1UL << FDCAN_CCCR_TXP_Pos)                /*!< 0x00004000 */

+#define FDCAN_CCCR_TXP            FDCAN_CCCR_TXP_Msk                           /*!<Two CAN bit times Pause                  */

+#define FDCAN_CCCR_NISO_Pos       (15U)

+#define FDCAN_CCCR_NISO_Msk       (0x1UL << FDCAN_CCCR_NISO_Pos)               /*!< 0x00008000 */

+#define FDCAN_CCCR_NISO           FDCAN_CCCR_NISO_Msk                          /*!<Non ISO Operation                        */

+

+/*****************  Bit definition for FDCAN_NBTP register  ********************/

+#define FDCAN_NBTP_NTSEG2_Pos     (0U)

+#define FDCAN_NBTP_NTSEG2_Msk     (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)            /*!< 0x0000007F */

+#define FDCAN_NBTP_NTSEG2         FDCAN_NBTP_NTSEG2_Msk                        /*!<Nominal Time segment after sample point  */

+#define FDCAN_NBTP_NTSEG1_Pos     (8U)

+#define FDCAN_NBTP_NTSEG1_Msk     (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)            /*!< 0x0000FF00 */

+#define FDCAN_NBTP_NTSEG1         FDCAN_NBTP_NTSEG1_Msk                        /*!<Nominal Time segment before sample point */

+#define FDCAN_NBTP_NBRP_Pos       (16U)

+#define FDCAN_NBTP_NBRP_Msk       (0x1FFUL << FDCAN_NBTP_NBRP_Pos)             /*!< 0x01FF0000 */

+#define FDCAN_NBTP_NBRP           FDCAN_NBTP_NBRP_Msk                          /*!<Bit Rate Prescaler                       */

+#define FDCAN_NBTP_NSJW_Pos       (25U)

+#define FDCAN_NBTP_NSJW_Msk       (0x7FUL << FDCAN_NBTP_NSJW_Pos)              /*!< 0xFE000000 */

+#define FDCAN_NBTP_NSJW           FDCAN_NBTP_NSJW_Msk                          /*!<Nominal (Re)Synchronization Jump Width   */

+

+/*****************  Bit definition for FDCAN_TSCC register  ********************/

+#define FDCAN_TSCC_TSS_Pos        (0U)

+#define FDCAN_TSCC_TSS_Msk        (0x3UL << FDCAN_TSCC_TSS_Pos)                /*!< 0x00000003 */

+#define FDCAN_TSCC_TSS            FDCAN_TSCC_TSS_Msk                           /*!<Timestamp Select                         */

+#define FDCAN_TSCC_TCP_Pos        (16U)

+#define FDCAN_TSCC_TCP_Msk        (0xFUL << FDCAN_TSCC_TCP_Pos)                /*!< 0x000F0000 */

+#define FDCAN_TSCC_TCP            FDCAN_TSCC_TCP_Msk                           /*!<Timestamp Counter Prescaler              */

+

+/*****************  Bit definition for FDCAN_TSCV register  ********************/

+#define FDCAN_TSCV_TSC_Pos        (0U)

+#define FDCAN_TSCV_TSC_Msk        (0xFFFFUL << FDCAN_TSCV_TSC_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TSCV_TSC            FDCAN_TSCV_TSC_Msk                           /*!<Timestamp Counter                        */

+

+/*****************  Bit definition for FDCAN_TOCC register  ********************/

+#define FDCAN_TOCC_ETOC_Pos       (0U)

+#define FDCAN_TOCC_ETOC_Msk       (0x1UL << FDCAN_TOCC_ETOC_Pos)               /*!< 0x00000001 */

+#define FDCAN_TOCC_ETOC           FDCAN_TOCC_ETOC_Msk                          /*!<Enable Timeout Counter                   */

+#define FDCAN_TOCC_TOS_Pos        (1U)

+#define FDCAN_TOCC_TOS_Msk        (0x3UL << FDCAN_TOCC_TOS_Pos)                /*!< 0x00000006 */

+#define FDCAN_TOCC_TOS            FDCAN_TOCC_TOS_Msk                           /*!<Timeout Select                           */

+#define FDCAN_TOCC_TOP_Pos        (16U)

+#define FDCAN_TOCC_TOP_Msk        (0xFFFFUL << FDCAN_TOCC_TOP_Pos)             /*!< 0xFFFF0000 */

+#define FDCAN_TOCC_TOP            FDCAN_TOCC_TOP_Msk                           /*!<Timeout Period                           */

+

+/*****************  Bit definition for FDCAN_TOCV register  ********************/

+#define FDCAN_TOCV_TOC_Pos        (0U)

+#define FDCAN_TOCV_TOC_Msk        (0xFFFFUL << FDCAN_TOCV_TOC_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TOCV_TOC            FDCAN_TOCV_TOC_Msk                           /*!<Timeout Counter                          */

+

+/*****************  Bit definition for FDCAN_ECR register  *********************/

+#define FDCAN_ECR_TEC_Pos         (0U)

+#define FDCAN_ECR_TEC_Msk         (0xFUL << FDCAN_ECR_TEC_Pos)                 /*!< 0x0000000F */

+#define FDCAN_ECR_TEC             FDCAN_ECR_TEC_Msk                            /*!<Transmit Error Counter                   */

+#define FDCAN_ECR_REC_Pos         (8U)

+#define FDCAN_ECR_REC_Msk         (0x7FUL << FDCAN_ECR_REC_Pos)                /*!< 0x00007F00 */

+#define FDCAN_ECR_REC             FDCAN_ECR_REC_Msk                            /*!<Receive Error Counter                    */

+#define FDCAN_ECR_RP_Pos          (15U)

+#define FDCAN_ECR_RP_Msk          (0x1UL << FDCAN_ECR_RP_Pos)                  /*!< 0x00008000 */

+#define FDCAN_ECR_RP              FDCAN_ECR_RP_Msk                             /*!<Receive Error Passive                    */

+#define FDCAN_ECR_CEL_Pos         (16U)

+#define FDCAN_ECR_CEL_Msk         (0xFFUL << FDCAN_ECR_CEL_Pos)                /*!< 0x00FF0000 */

+#define FDCAN_ECR_CEL             FDCAN_ECR_CEL_Msk                            /*!<CAN Error Logging                        */

+

+/*****************  Bit definition for FDCAN_PSR register  *********************/

+#define FDCAN_PSR_LEC_Pos         (0U)

+#define FDCAN_PSR_LEC_Msk         (0x7UL << FDCAN_PSR_LEC_Pos)                 /*!< 0x00000007 */

+#define FDCAN_PSR_LEC             FDCAN_PSR_LEC_Msk                            /*!<Last Error Code                          */

+#define FDCAN_PSR_ACT_Pos         (3U)

+#define FDCAN_PSR_ACT_Msk         (0x3UL << FDCAN_PSR_ACT_Pos)                 /*!< 0x00000018 */

+#define FDCAN_PSR_ACT             FDCAN_PSR_ACT_Msk                            /*!<Activity                                 */

+#define FDCAN_PSR_EP_Pos          (5U)

+#define FDCAN_PSR_EP_Msk          (0x1UL << FDCAN_PSR_EP_Pos)                  /*!< 0x00000020 */

+#define FDCAN_PSR_EP              FDCAN_PSR_EP_Msk                             /*!<Error Passive                            */

+#define FDCAN_PSR_EW_Pos          (6U)

+#define FDCAN_PSR_EW_Msk          (0x1UL << FDCAN_PSR_EW_Pos)                  /*!< 0x00000040 */

+#define FDCAN_PSR_EW              FDCAN_PSR_EW_Msk                             /*!<Warning Status                           */

+#define FDCAN_PSR_BO_Pos          (7U)

+#define FDCAN_PSR_BO_Msk          (0x1UL << FDCAN_PSR_BO_Pos)                  /*!< 0x00000080 */

+#define FDCAN_PSR_BO              FDCAN_PSR_BO_Msk                             /*!<Bus_Off Status                           */

+#define FDCAN_PSR_DLEC_Pos        (8U)

+#define FDCAN_PSR_DLEC_Msk        (0x7UL << FDCAN_PSR_DLEC_Pos)                /*!< 0x00000700 */

+#define FDCAN_PSR_DLEC            FDCAN_PSR_DLEC_Msk                           /*!<Data Last Error Code                     */

+#define FDCAN_PSR_RESI_Pos        (11U)

+#define FDCAN_PSR_RESI_Msk        (0x1UL << FDCAN_PSR_RESI_Pos)                /*!< 0x00000800 */

+#define FDCAN_PSR_RESI            FDCAN_PSR_RESI_Msk                           /*!<ESI flag of last received FDCAN Message  */

+#define FDCAN_PSR_RBRS_Pos        (12U)

+#define FDCAN_PSR_RBRS_Msk        (0x1UL << FDCAN_PSR_RBRS_Pos)                /*!< 0x00001000 */

+#define FDCAN_PSR_RBRS            FDCAN_PSR_RBRS_Msk                           /*!<BRS flag of last received FDCAN Message  */

+#define FDCAN_PSR_REDL_Pos        (13U)

+#define FDCAN_PSR_REDL_Msk        (0x1UL << FDCAN_PSR_REDL_Pos)                /*!< 0x00002000 */

+#define FDCAN_PSR_REDL            FDCAN_PSR_REDL_Msk                           /*!<Received FDCAN Message                   */

+#define FDCAN_PSR_PXE_Pos         (14U)

+#define FDCAN_PSR_PXE_Msk         (0x1UL << FDCAN_PSR_PXE_Pos)                 /*!< 0x00004000 */

+#define FDCAN_PSR_PXE             FDCAN_PSR_PXE_Msk                            /*!<Protocol Exception Event                 */

+#define FDCAN_PSR_TDCV_Pos        (16U)

+#define FDCAN_PSR_TDCV_Msk        (0x7FUL << FDCAN_PSR_TDCV_Pos)               /*!< 0x007F0000 */

+#define FDCAN_PSR_TDCV            FDCAN_PSR_TDCV_Msk                           /*!<Transmitter Delay Compensation Value     */

+

+/*****************  Bit definition for FDCAN_TDCR register  ********************/

+#define FDCAN_TDCR_TDCF_Pos       (0U)

+#define FDCAN_TDCR_TDCF_Msk       (0x7FUL << FDCAN_TDCR_TDCF_Pos)              /*!< 0x0000007F */

+#define FDCAN_TDCR_TDCF           FDCAN_TDCR_TDCF_Msk                          /*!<Transmitter Delay Compensation Filter    */

+#define FDCAN_TDCR_TDCO_Pos       (8U)

+#define FDCAN_TDCR_TDCO_Msk       (0x7FUL << FDCAN_TDCR_TDCO_Pos)              /*!< 0x00007F00 */

+#define FDCAN_TDCR_TDCO           FDCAN_TDCR_TDCO_Msk                          /*!<Transmitter Delay Compensation Offset    */

+

+/*****************  Bit definition for FDCAN_IR register  **********************/

+#define FDCAN_IR_RF0N_Pos         (0U)

+#define FDCAN_IR_RF0N_Msk         (0x1UL << FDCAN_IR_RF0N_Pos)                 /*!< 0x00000001 */

+#define FDCAN_IR_RF0N             FDCAN_IR_RF0N_Msk                            /*!<Rx FIFO 0 New Message                    */

+#define FDCAN_IR_RF0W_Pos         (1U)

+#define FDCAN_IR_RF0W_Msk         (0x1UL << FDCAN_IR_RF0W_Pos)                 /*!< 0x00000002 */

+#define FDCAN_IR_RF0W             FDCAN_IR_RF0W_Msk                            /*!<Rx FIFO 0 Watermark Reached              */

+#define FDCAN_IR_RF0F_Pos         (2U)

+#define FDCAN_IR_RF0F_Msk         (0x1UL << FDCAN_IR_RF0F_Pos)                 /*!< 0x00000004 */

+#define FDCAN_IR_RF0F             FDCAN_IR_RF0F_Msk                            /*!<Rx FIFO 0 Full                           */

+#define FDCAN_IR_RF0L_Pos         (3U)

+#define FDCAN_IR_RF0L_Msk         (0x1UL << FDCAN_IR_RF0L_Pos)                 /*!< 0x00000008 */

+#define FDCAN_IR_RF0L             FDCAN_IR_RF0L_Msk                            /*!<Rx FIFO 0 Message Lost                   */

+#define FDCAN_IR_RF1N_Pos         (4U)

+#define FDCAN_IR_RF1N_Msk         (0x1UL << FDCAN_IR_RF1N_Pos)                 /*!< 0x00000010 */

+#define FDCAN_IR_RF1N             FDCAN_IR_RF1N_Msk                            /*!<Rx FIFO 1 New Message                    */

+#define FDCAN_IR_RF1W_Pos         (5U)

+#define FDCAN_IR_RF1W_Msk         (0x1UL << FDCAN_IR_RF1W_Pos)                 /*!< 0x00000020 */

+#define FDCAN_IR_RF1W             FDCAN_IR_RF1W_Msk                            /*!<Rx FIFO 1 Watermark Reached              */

+#define FDCAN_IR_RF1F_Pos         (6U)

+#define FDCAN_IR_RF1F_Msk         (0x1UL << FDCAN_IR_RF1F_Pos)                 /*!< 0x00000040 */

+#define FDCAN_IR_RF1F             FDCAN_IR_RF1F_Msk                            /*!<Rx FIFO 1 Full                           */

+#define FDCAN_IR_RF1L_Pos         (7U)

+#define FDCAN_IR_RF1L_Msk         (0x1UL << FDCAN_IR_RF1L_Pos)                 /*!< 0x00000080 */

+#define FDCAN_IR_RF1L             FDCAN_IR_RF1L_Msk                            /*!<Rx FIFO 1 Message Lost                   */

+#define FDCAN_IR_HPM_Pos          (8U)

+#define FDCAN_IR_HPM_Msk          (0x1UL << FDCAN_IR_HPM_Pos)                  /*!< 0x00000100 */

+#define FDCAN_IR_HPM              FDCAN_IR_HPM_Msk                             /*!<High Priority Message                    */

+#define FDCAN_IR_TC_Pos           (9U)

+#define FDCAN_IR_TC_Msk           (0x1UL << FDCAN_IR_TC_Pos)                   /*!< 0x00000200 */

+#define FDCAN_IR_TC               FDCAN_IR_TC_Msk                              /*!<Transmission Completed                   */

+#define FDCAN_IR_TCF_Pos          (10U)

+#define FDCAN_IR_TCF_Msk          (0x1UL << FDCAN_IR_TCF_Pos)                  /*!< 0x00000400 */

+#define FDCAN_IR_TCF              FDCAN_IR_TCF_Msk                             /*!<Transmission Cancellation Finished       */

+#define FDCAN_IR_TFE_Pos          (11U)

+#define FDCAN_IR_TFE_Msk          (0x1UL << FDCAN_IR_TFE_Pos)                  /*!< 0x00000800 */

+#define FDCAN_IR_TFE              FDCAN_IR_TFE_Msk                             /*!<Tx FIFO Empty                            */

+#define FDCAN_IR_TEFN_Pos         (12U)

+#define FDCAN_IR_TEFN_Msk         (0x1UL << FDCAN_IR_TEFN_Pos)                 /*!< 0x00001000 */

+#define FDCAN_IR_TEFN             FDCAN_IR_TEFN_Msk                            /*!<Tx Event FIFO New Entry                  */

+#define FDCAN_IR_TEFW_Pos         (13U)

+#define FDCAN_IR_TEFW_Msk         (0x1UL << FDCAN_IR_TEFW_Pos)                 /*!< 0x00002000 */

+#define FDCAN_IR_TEFW             FDCAN_IR_TEFW_Msk                            /*!<Tx Event FIFO Watermark Reached          */

+#define FDCAN_IR_TEFF_Pos         (14U)

+#define FDCAN_IR_TEFF_Msk         (0x1UL << FDCAN_IR_TEFF_Pos)                 /*!< 0x00004000 */

+#define FDCAN_IR_TEFF             FDCAN_IR_TEFF_Msk                            /*!<Tx Event FIFO Full                       */

+#define FDCAN_IR_TEFL_Pos         (15U)

+#define FDCAN_IR_TEFL_Msk         (0x1UL << FDCAN_IR_TEFL_Pos)                 /*!< 0x00008000 */

+#define FDCAN_IR_TEFL             FDCAN_IR_TEFL_Msk                            /*!<Tx Event FIFO Element Lost               */

+#define FDCAN_IR_TSW_Pos          (16U)

+#define FDCAN_IR_TSW_Msk          (0x1UL << FDCAN_IR_TSW_Pos)                  /*!< 0x00010000 */

+#define FDCAN_IR_TSW              FDCAN_IR_TSW_Msk                             /*!<Timestamp Wraparound                     */

+#define FDCAN_IR_MRAF_Pos         (17U)

+#define FDCAN_IR_MRAF_Msk         (0x1UL << FDCAN_IR_MRAF_Pos)                 /*!< 0x00020000 */

+#define FDCAN_IR_MRAF             FDCAN_IR_MRAF_Msk                            /*!<Message RAM Access Failure               */

+#define FDCAN_IR_TOO_Pos          (18U)

+#define FDCAN_IR_TOO_Msk          (0x1UL << FDCAN_IR_TOO_Pos)                  /*!< 0x00040000 */

+#define FDCAN_IR_TOO              FDCAN_IR_TOO_Msk                             /*!<Timeout Occurred                         */

+#define FDCAN_IR_DRX_Pos          (19U)

+#define FDCAN_IR_DRX_Msk          (0x1UL << FDCAN_IR_DRX_Pos)                  /*!< 0x00080000 */

+#define FDCAN_IR_DRX              FDCAN_IR_DRX_Msk                             /*!<Message stored to Dedicated Rx Buffer    */

+#define FDCAN_IR_ELO_Pos          (22U)

+#define FDCAN_IR_ELO_Msk          (0x1UL << FDCAN_IR_ELO_Pos)                  /*!< 0x00400000 */

+#define FDCAN_IR_ELO              FDCAN_IR_ELO_Msk                             /*!<Error Logging Overflow                   */

+#define FDCAN_IR_EP_Pos           (23U)

+#define FDCAN_IR_EP_Msk           (0x1UL << FDCAN_IR_EP_Pos)                   /*!< 0x00800000 */

+#define FDCAN_IR_EP               FDCAN_IR_EP_Msk                              /*!<Error Passive                            */

+#define FDCAN_IR_EW_Pos           (24U)

+#define FDCAN_IR_EW_Msk           (0x1UL << FDCAN_IR_EW_Pos)                   /*!< 0x01000000 */

+#define FDCAN_IR_EW               FDCAN_IR_EW_Msk                              /*!<Warning Status                           */

+#define FDCAN_IR_BO_Pos           (25U)

+#define FDCAN_IR_BO_Msk           (0x1UL << FDCAN_IR_BO_Pos)                   /*!< 0x02000000 */

+#define FDCAN_IR_BO               FDCAN_IR_BO_Msk                              /*!<Bus_Off Status                           */

+#define FDCAN_IR_WDI_Pos          (26U)

+#define FDCAN_IR_WDI_Msk          (0x1UL << FDCAN_IR_WDI_Pos)                  /*!< 0x04000000 */

+#define FDCAN_IR_WDI              FDCAN_IR_WDI_Msk                             /*!<Watchdog Interrupt                       */

+#define FDCAN_IR_PEA_Pos          (27U)

+#define FDCAN_IR_PEA_Msk          (0x1UL << FDCAN_IR_PEA_Pos)                  /*!< 0x08000000 */

+#define FDCAN_IR_PEA              FDCAN_IR_PEA_Msk                             /*!<Protocol Error in Arbitration Phase      */

+#define FDCAN_IR_PED_Pos          (28U)

+#define FDCAN_IR_PED_Msk          (0x1UL << FDCAN_IR_PED_Pos)                  /*!< 0x10000000 */

+#define FDCAN_IR_PED              FDCAN_IR_PED_Msk                             /*!<Protocol Error in Data Phase             */

+#define FDCAN_IR_ARA_Pos          (29U)

+#define FDCAN_IR_ARA_Msk          (0x1UL << FDCAN_IR_ARA_Pos)                  /*!< 0x20000000 */

+#define FDCAN_IR_ARA              FDCAN_IR_ARA_Msk                             /*!<Access to Reserved Address               */

+

+/*****************  Bit definition for FDCAN_IE register  **********************/

+#define FDCAN_IE_RF0NE_Pos        (0U)

+#define FDCAN_IE_RF0NE_Msk        (0x1UL << FDCAN_IE_RF0NE_Pos)                /*!< 0x00000001 */

+#define FDCAN_IE_RF0NE            FDCAN_IE_RF0NE_Msk                           /*!<Rx FIFO 0 New Message Enable                 */

+#define FDCAN_IE_RF0WE_Pos        (1U)

+#define FDCAN_IE_RF0WE_Msk        (0x1UL << FDCAN_IE_RF0WE_Pos)                /*!< 0x00000002 */

+#define FDCAN_IE_RF0WE            FDCAN_IE_RF0WE_Msk                           /*!<Rx FIFO 0 Watermark Reached Enable           */

+#define FDCAN_IE_RF0FE_Pos        (2U)

+#define FDCAN_IE_RF0FE_Msk        (0x1UL << FDCAN_IE_RF0FE_Pos)                /*!< 0x00000004 */

+#define FDCAN_IE_RF0FE            FDCAN_IE_RF0FE_Msk                           /*!<Rx FIFO 0 Full Enable                        */

+#define FDCAN_IE_RF0LE_Pos        (3U)

+#define FDCAN_IE_RF0LE_Msk        (0x1UL << FDCAN_IE_RF0LE_Pos)                /*!< 0x00000008 */

+#define FDCAN_IE_RF0LE            FDCAN_IE_RF0LE_Msk                           /*!<Rx FIFO 0 Message Lost Enable                */

+#define FDCAN_IE_RF1NE_Pos        (4U)

+#define FDCAN_IE_RF1NE_Msk        (0x1UL << FDCAN_IE_RF1NE_Pos)                /*!< 0x00000010 */

+#define FDCAN_IE_RF1NE            FDCAN_IE_RF1NE_Msk                           /*!<Rx FIFO 1 New Message Enable                 */

+#define FDCAN_IE_RF1WE_Pos        (5U)

+#define FDCAN_IE_RF1WE_Msk        (0x1UL << FDCAN_IE_RF1WE_Pos)                /*!< 0x00000020 */

+#define FDCAN_IE_RF1WE            FDCAN_IE_RF1WE_Msk                           /*!<Rx FIFO 1 Watermark Reached Enable           */

+#define FDCAN_IE_RF1FE_Pos        (6U)

+#define FDCAN_IE_RF1FE_Msk        (0x1UL << FDCAN_IE_RF1FE_Pos)                /*!< 0x00000040 */

+#define FDCAN_IE_RF1FE            FDCAN_IE_RF1FE_Msk                           /*!<Rx FIFO 1 Full Enable                        */

+#define FDCAN_IE_RF1LE_Pos        (7U)

+#define FDCAN_IE_RF1LE_Msk        (0x1UL << FDCAN_IE_RF1LE_Pos)                /*!< 0x00000080 */

+#define FDCAN_IE_RF1LE            FDCAN_IE_RF1LE_Msk                           /*!<Rx FIFO 1 Message Lost Enable                */

+#define FDCAN_IE_HPME_Pos         (8U)

+#define FDCAN_IE_HPME_Msk         (0x1UL << FDCAN_IE_HPME_Pos)                 /*!< 0x00000100 */

+#define FDCAN_IE_HPME             FDCAN_IE_HPME_Msk                            /*!<High Priority Message Enable                 */

+#define FDCAN_IE_TCE_Pos          (9U)

+#define FDCAN_IE_TCE_Msk          (0x1UL << FDCAN_IE_TCE_Pos)                  /*!< 0x00000200 */

+#define FDCAN_IE_TCE              FDCAN_IE_TCE_Msk                             /*!<Transmission Completed Enable                */

+#define FDCAN_IE_TCFE_Pos         (10U)

+#define FDCAN_IE_TCFE_Msk         (0x1UL << FDCAN_IE_TCFE_Pos)                 /*!< 0x00000400 */

+#define FDCAN_IE_TCFE             FDCAN_IE_TCFE_Msk                            /*!<Transmission Cancellation Finished Enable    */

+#define FDCAN_IE_TFEE_Pos         (11U)

+#define FDCAN_IE_TFEE_Msk         (0x1UL << FDCAN_IE_TFEE_Pos)                 /*!< 0x00000800 */

+#define FDCAN_IE_TFEE             FDCAN_IE_TFEE_Msk                            /*!<Tx FIFO Empty Enable                         */

+#define FDCAN_IE_TEFNE_Pos        (12U)

+#define FDCAN_IE_TEFNE_Msk        (0x1UL << FDCAN_IE_TEFNE_Pos)                /*!< 0x00001000 */

+#define FDCAN_IE_TEFNE            FDCAN_IE_TEFNE_Msk                           /*!<Tx Event FIFO New Entry Enable               */

+#define FDCAN_IE_TEFWE_Pos        (13U)

+#define FDCAN_IE_TEFWE_Msk        (0x1UL << FDCAN_IE_TEFWE_Pos)                /*!< 0x00002000 */

+#define FDCAN_IE_TEFWE            FDCAN_IE_TEFWE_Msk                           /*!<Tx Event FIFO Watermark Reached Enable       */

+#define FDCAN_IE_TEFFE_Pos        (14U)

+#define FDCAN_IE_TEFFE_Msk        (0x1UL << FDCAN_IE_TEFFE_Pos)                /*!< 0x00004000 */

+#define FDCAN_IE_TEFFE            FDCAN_IE_TEFFE_Msk                           /*!<Tx Event FIFO Full Enable                    */

+#define FDCAN_IE_TEFLE_Pos        (15U)

+#define FDCAN_IE_TEFLE_Msk        (0x1UL << FDCAN_IE_TEFLE_Pos)                /*!< 0x00008000 */

+#define FDCAN_IE_TEFLE            FDCAN_IE_TEFLE_Msk                           /*!<Tx Event FIFO Element Lost Enable            */

+#define FDCAN_IE_TSWE_Pos         (16U)

+#define FDCAN_IE_TSWE_Msk         (0x1UL << FDCAN_IE_TSWE_Pos)                 /*!< 0x00010000 */

+#define FDCAN_IE_TSWE             FDCAN_IE_TSWE_Msk                            /*!<Timestamp Wraparound Enable                  */

+#define FDCAN_IE_MRAFE_Pos        (17U)

+#define FDCAN_IE_MRAFE_Msk        (0x1UL << FDCAN_IE_MRAFE_Pos)                /*!< 0x00020000 */

+#define FDCAN_IE_MRAFE            FDCAN_IE_MRAFE_Msk                           /*!<Message RAM Access Failure Enable            */

+#define FDCAN_IE_TOOE_Pos         (18U)

+#define FDCAN_IE_TOOE_Msk         (0x1UL << FDCAN_IE_TOOE_Pos)                 /*!< 0x00040000 */

+#define FDCAN_IE_TOOE             FDCAN_IE_TOOE_Msk                            /*!<Timeout Occurred Enable                      */

+#define FDCAN_IE_DRXE_Pos         (19U)

+#define FDCAN_IE_DRXE_Msk         (0x1UL << FDCAN_IE_DRXE_Pos)                 /*!< 0x00080000 */

+#define FDCAN_IE_DRXE             FDCAN_IE_DRXE_Msk                            /*!<Message stored to Dedicated Rx Buffer Enable */

+#define FDCAN_IE_BECE_Pos         (20U)

+#define FDCAN_IE_BECE_Msk         (0x1UL << FDCAN_IE_BECE_Pos)                 /*!< 0x00100000 */

+#define FDCAN_IE_BECE             FDCAN_IE_BECE_Msk                            /*!<Bit Error Corrected Interrupt Enable         */

+#define FDCAN_IE_BEUE_Pos         (21U)

+#define FDCAN_IE_BEUE_Msk         (0x1UL << FDCAN_IE_BEUE_Pos)                 /*!< 0x00200000 */

+#define FDCAN_IE_BEUE             FDCAN_IE_BEUE_Msk                            /*!<Bit Error Uncorrected Interrupt Enable       */

+#define FDCAN_IE_ELOE_Pos         (22U)

+#define FDCAN_IE_ELOE_Msk         (0x1UL << FDCAN_IE_ELOE_Pos)                 /*!< 0x00400000 */

+#define FDCAN_IE_ELOE             FDCAN_IE_ELOE_Msk                            /*!<Error Logging Overflow Enable                */

+#define FDCAN_IE_EPE_Pos          (23U)

+#define FDCAN_IE_EPE_Msk          (0x1UL << FDCAN_IE_EPE_Pos)                  /*!< 0x00800000 */

+#define FDCAN_IE_EPE              FDCAN_IE_EPE_Msk                             /*!<Error Passive Enable                         */

+#define FDCAN_IE_EWE_Pos          (24U)

+#define FDCAN_IE_EWE_Msk          (0x1UL << FDCAN_IE_EWE_Pos)                  /*!< 0x01000000 */

+#define FDCAN_IE_EWE              FDCAN_IE_EWE_Msk                             /*!<Warning Status Enable                        */

+#define FDCAN_IE_BOE_Pos          (25U)

+#define FDCAN_IE_BOE_Msk          (0x1UL << FDCAN_IE_BOE_Pos)                  /*!< 0x02000000 */

+#define FDCAN_IE_BOE              FDCAN_IE_BOE_Msk                             /*!<Bus_Off Status Enable                        */

+#define FDCAN_IE_WDIE_Pos         (26U)

+#define FDCAN_IE_WDIE_Msk         (0x1UL << FDCAN_IE_WDIE_Pos)                 /*!< 0x04000000 */

+#define FDCAN_IE_WDIE             FDCAN_IE_WDIE_Msk                            /*!<Watchdog Interrupt Enable                    */

+#define FDCAN_IE_PEAE_Pos         (27U)

+#define FDCAN_IE_PEAE_Msk         (0x1UL << FDCAN_IE_PEAE_Pos)                 /*!< 0x08000000 */

+#define FDCAN_IE_PEAE             FDCAN_IE_PEAE_Msk                            /*!<Protocol Error in Arbitration Phase Enable   */

+#define FDCAN_IE_PEDE_Pos         (28U)

+#define FDCAN_IE_PEDE_Msk         (0x1UL << FDCAN_IE_PEDE_Pos)                 /*!< 0x10000000 */

+#define FDCAN_IE_PEDE             FDCAN_IE_PEDE_Msk                            /*!<Protocol Error in Data Phase Enable          */

+#define FDCAN_IE_ARAE_Pos         (29U)

+#define FDCAN_IE_ARAE_Msk         (0x1UL << FDCAN_IE_ARAE_Pos)                 /*!< 0x20000000 */

+#define FDCAN_IE_ARAE             FDCAN_IE_ARAE_Msk                            /*!<Access to Reserved Address Enable            */

+

+/*****************  Bit definition for FDCAN_ILS register  **********************/

+#define FDCAN_ILS_RF0NL_Pos       (0U)

+#define FDCAN_ILS_RF0NL_Msk       (0x1UL << FDCAN_ILS_RF0NL_Pos)               /*!< 0x00000001 */

+#define FDCAN_ILS_RF0NL           FDCAN_ILS_RF0NL_Msk                          /*!<Rx FIFO 0 New Message Line                  */

+#define FDCAN_ILS_RF0WL_Pos       (1U)

+#define FDCAN_ILS_RF0WL_Msk       (0x1UL << FDCAN_ILS_RF0WL_Pos)               /*!< 0x00000002 */

+#define FDCAN_ILS_RF0WL           FDCAN_ILS_RF0WL_Msk                          /*!<Rx FIFO 0 Watermark Reached Line            */

+#define FDCAN_ILS_RF0FL_Pos       (2U)

+#define FDCAN_ILS_RF0FL_Msk       (0x1UL << FDCAN_ILS_RF0FL_Pos)               /*!< 0x00000004 */

+#define FDCAN_ILS_RF0FL           FDCAN_ILS_RF0FL_Msk                          /*!<Rx FIFO 0 Full Line                         */

+#define FDCAN_ILS_RF0LL_Pos       (3U)

+#define FDCAN_ILS_RF0LL_Msk       (0x1UL << FDCAN_ILS_RF0LL_Pos)               /*!< 0x00000008 */

+#define FDCAN_ILS_RF0LL           FDCAN_ILS_RF0LL_Msk                          /*!<Rx FIFO 0 Message Lost Line                 */

+#define FDCAN_ILS_RF1NL_Pos       (4U)

+#define FDCAN_ILS_RF1NL_Msk       (0x1UL << FDCAN_ILS_RF1NL_Pos)               /*!< 0x00000010 */

+#define FDCAN_ILS_RF1NL           FDCAN_ILS_RF1NL_Msk                          /*!<Rx FIFO 1 New Message Line                  */

+#define FDCAN_ILS_RF1WL_Pos       (5U)

+#define FDCAN_ILS_RF1WL_Msk       (0x1UL << FDCAN_ILS_RF1WL_Pos)               /*!< 0x00000020 */

+#define FDCAN_ILS_RF1WL           FDCAN_ILS_RF1WL_Msk                          /*!<Rx FIFO 1 Watermark Reached Line            */

+#define FDCAN_ILS_RF1FL_Pos       (6U)

+#define FDCAN_ILS_RF1FL_Msk       (0x1UL << FDCAN_ILS_RF1FL_Pos)               /*!< 0x00000040 */

+#define FDCAN_ILS_RF1FL           FDCAN_ILS_RF1FL_Msk                          /*!<Rx FIFO 1 Full Line                         */

+#define FDCAN_ILS_RF1LL_Pos       (7U)

+#define FDCAN_ILS_RF1LL_Msk       (0x1UL << FDCAN_ILS_RF1LL_Pos)               /*!< 0x00000080 */

+#define FDCAN_ILS_RF1LL           FDCAN_ILS_RF1LL_Msk                          /*!<Rx FIFO 1 Message Lost Line                 */

+#define FDCAN_ILS_HPML_Pos        (8U)

+#define FDCAN_ILS_HPML_Msk        (0x1UL << FDCAN_ILS_HPML_Pos)                /*!< 0x00000100 */

+#define FDCAN_ILS_HPML            FDCAN_ILS_HPML_Msk                           /*!<High Priority Message Line                  */

+#define FDCAN_ILS_TCL_Pos         (9U)

+#define FDCAN_ILS_TCL_Msk         (0x1UL << FDCAN_ILS_TCL_Pos)                 /*!< 0x00000200 */

+#define FDCAN_ILS_TCL             FDCAN_ILS_TCL_Msk                            /*!<Transmission Completed Line                 */

+#define FDCAN_ILS_TCFL_Pos        (10U)

+#define FDCAN_ILS_TCFL_Msk        (0x1UL << FDCAN_ILS_TCFL_Pos)                /*!< 0x00000400 */

+#define FDCAN_ILS_TCFL            FDCAN_ILS_TCFL_Msk                           /*!<Transmission Cancellation Finished Line     */

+#define FDCAN_ILS_TFEL_Pos        (11U)

+#define FDCAN_ILS_TFEL_Msk        (0x1UL << FDCAN_ILS_TFEL_Pos)                /*!< 0x00000800 */

+#define FDCAN_ILS_TFEL            FDCAN_ILS_TFEL_Msk                           /*!<Tx FIFO Empty Line                          */

+#define FDCAN_ILS_TEFNL_Pos       (12U)

+#define FDCAN_ILS_TEFNL_Msk       (0x1UL << FDCAN_ILS_TEFNL_Pos)               /*!< 0x00001000 */

+#define FDCAN_ILS_TEFNL           FDCAN_ILS_TEFNL_Msk                          /*!<Tx Event FIFO New Entry Line                */

+#define FDCAN_ILS_TEFWL_Pos       (13U)

+#define FDCAN_ILS_TEFWL_Msk       (0x1UL << FDCAN_ILS_TEFWL_Pos)               /*!< 0x00002000 */

+#define FDCAN_ILS_TEFWL           FDCAN_ILS_TEFWL_Msk                          /*!<Tx Event FIFO Watermark Reached Line        */

+#define FDCAN_ILS_TEFFL_Pos       (14U)

+#define FDCAN_ILS_TEFFL_Msk       (0x1UL << FDCAN_ILS_TEFFL_Pos)               /*!< 0x00004000 */

+#define FDCAN_ILS_TEFFL           FDCAN_ILS_TEFFL_Msk                          /*!<Tx Event FIFO Full Line                     */

+#define FDCAN_ILS_TEFLL_Pos       (15U)

+#define FDCAN_ILS_TEFLL_Msk       (0x1UL << FDCAN_ILS_TEFLL_Pos)               /*!< 0x00008000 */

+#define FDCAN_ILS_TEFLL           FDCAN_ILS_TEFLL_Msk                          /*!<Tx Event FIFO Element Lost Line             */

+#define FDCAN_ILS_TSWL_Pos        (16U)

+#define FDCAN_ILS_TSWL_Msk        (0x1UL << FDCAN_ILS_TSWL_Pos)                /*!< 0x00010000 */

+#define FDCAN_ILS_TSWL            FDCAN_ILS_TSWL_Msk                           /*!<Timestamp Wraparound Line                   */

+#define FDCAN_ILS_MRAFE_Pos       (17U)

+#define FDCAN_ILS_MRAFE_Msk       (0x1UL << FDCAN_ILS_MRAFE_Pos)               /*!< 0x00020000 */

+#define FDCAN_ILS_MRAFE           FDCAN_ILS_MRAFE_Msk                          /*!<Message RAM Access Failure Line             */

+#define FDCAN_ILS_TOOE_Pos        (18U)

+#define FDCAN_ILS_TOOE_Msk        (0x1UL << FDCAN_ILS_TOOE_Pos)                /*!< 0x00040000 */

+#define FDCAN_ILS_TOOE            FDCAN_ILS_TOOE_Msk                           /*!<Timeout Occurred Line                       */

+#define FDCAN_ILS_DRXE_Pos        (19U)

+#define FDCAN_ILS_DRXE_Msk        (0x1UL << FDCAN_ILS_DRXE_Pos)                /*!< 0x00080000 */

+#define FDCAN_ILS_DRXE            FDCAN_ILS_DRXE_Msk                           /*!<Message stored to Dedicated Rx Buffer Line  */

+#define FDCAN_ILS_BECE_Pos        (20U)

+#define FDCAN_ILS_BECE_Msk        (0x1UL << FDCAN_ILS_BECE_Pos)                /*!< 0x00100000 */

+#define FDCAN_ILS_BECE            FDCAN_ILS_BECE_Msk                           /*!<Bit Error Corrected Interrupt Line          */

+#define FDCAN_ILS_BEUE_Pos        (21U)

+#define FDCAN_ILS_BEUE_Msk        (0x1UL << FDCAN_ILS_BEUE_Pos)                /*!< 0x00200000 */

+#define FDCAN_ILS_BEUE            FDCAN_ILS_BEUE_Msk                           /*!<Bit Error Uncorrected Interrupt Line        */

+#define FDCAN_ILS_ELOE_Pos        (22U)

+#define FDCAN_ILS_ELOE_Msk        (0x1UL << FDCAN_ILS_ELOE_Pos)                /*!< 0x00400000 */

+#define FDCAN_ILS_ELOE            FDCAN_ILS_ELOE_Msk                           /*!<Error Logging Overflow Line                 */

+#define FDCAN_ILS_EPE_Pos         (23U)

+#define FDCAN_ILS_EPE_Msk         (0x1UL << FDCAN_ILS_EPE_Pos)                 /*!< 0x00800000 */

+#define FDCAN_ILS_EPE             FDCAN_ILS_EPE_Msk                            /*!<Error Passive Line                          */

+#define FDCAN_ILS_EWE_Pos         (24U)

+#define FDCAN_ILS_EWE_Msk         (0x1UL << FDCAN_ILS_EWE_Pos)                 /*!< 0x01000000 */

+#define FDCAN_ILS_EWE             FDCAN_ILS_EWE_Msk                            /*!<Warning Status Line                         */

+#define FDCAN_ILS_BOE_Pos         (25U)

+#define FDCAN_ILS_BOE_Msk         (0x1UL << FDCAN_ILS_BOE_Pos)                 /*!< 0x02000000 */

+#define FDCAN_ILS_BOE             FDCAN_ILS_BOE_Msk                            /*!<Bus_Off Status Line                         */

+#define FDCAN_ILS_WDIE_Pos        (26U)

+#define FDCAN_ILS_WDIE_Msk        (0x1UL << FDCAN_ILS_WDIE_Pos)                /*!< 0x04000000 */

+#define FDCAN_ILS_WDIE            FDCAN_ILS_WDIE_Msk                           /*!<Watchdog Interrupt Line                     */

+#define FDCAN_ILS_PEAE_Pos        (27U)

+#define FDCAN_ILS_PEAE_Msk        (0x1UL << FDCAN_ILS_PEAE_Pos)                /*!< 0x08000000 */

+#define FDCAN_ILS_PEAE            FDCAN_ILS_PEAE_Msk                           /*!<Protocol Error in Arbitration Phase Line    */

+#define FDCAN_ILS_PEDE_Pos        (28U)

+#define FDCAN_ILS_PEDE_Msk        (0x1UL << FDCAN_ILS_PEDE_Pos)                /*!< 0x10000000 */

+#define FDCAN_ILS_PEDE            FDCAN_ILS_PEDE_Msk                           /*!<Protocol Error in Data Phase Line           */

+#define FDCAN_ILS_ARAE_Pos        (29U)

+#define FDCAN_ILS_ARAE_Msk        (0x1UL << FDCAN_ILS_ARAE_Pos)                /*!< 0x20000000 */

+#define FDCAN_ILS_ARAE            FDCAN_ILS_ARAE_Msk                           /*!<Access to Reserved Address Line             */

+

+/*****************  Bit definition for FDCAN_ILE register  **********************/

+#define FDCAN_ILE_EINT0_Pos       (0U)

+#define FDCAN_ILE_EINT0_Msk       (0x1UL << FDCAN_ILE_EINT0_Pos)               /*!< 0x00000001 */

+#define FDCAN_ILE_EINT0           FDCAN_ILE_EINT0_Msk                          /*!<Enable Interrupt Line 0                   */

+#define FDCAN_ILE_EINT1_Pos       (1U)

+#define FDCAN_ILE_EINT1_Msk       (0x1UL << FDCAN_ILE_EINT1_Pos)               /*!< 0x00000002 */

+#define FDCAN_ILE_EINT1           FDCAN_ILE_EINT1_Msk                          /*!<Enable Interrupt Line 1                   */

+

+/*****************  Bit definition for FDCAN_GFC register  **********************/

+#define FDCAN_GFC_RRFE_Pos        (0U)

+#define FDCAN_GFC_RRFE_Msk        (0x1UL << FDCAN_GFC_RRFE_Pos)                /*!< 0x00000001 */

+#define FDCAN_GFC_RRFE            FDCAN_GFC_RRFE_Msk                           /*!<Reject Remote Frames Extended             */

+#define FDCAN_GFC_RRFS_Pos        (1U)

+#define FDCAN_GFC_RRFS_Msk        (0x1UL << FDCAN_GFC_RRFS_Pos)                /*!< 0x00000002 */

+#define FDCAN_GFC_RRFS            FDCAN_GFC_RRFS_Msk                           /*!<Reject Remote Frames Standard             */

+#define FDCAN_GFC_ANFE_Pos        (2U)

+#define FDCAN_GFC_ANFE_Msk        (0x3UL << FDCAN_GFC_ANFE_Pos)                /*!< 0x0000000C */

+#define FDCAN_GFC_ANFE            FDCAN_GFC_ANFE_Msk                           /*!<Accept Non-matching Frames Extended       */

+#define FDCAN_GFC_ANFS_Pos        (4U)

+#define FDCAN_GFC_ANFS_Msk        (0x3UL << FDCAN_GFC_ANFS_Pos)                /*!< 0x00000030 */

+#define FDCAN_GFC_ANFS            FDCAN_GFC_ANFS_Msk                           /*!<Accept Non-matching Frames Standard       */

+

+/*****************  Bit definition for FDCAN_SIDFC register  ********************/

+#define FDCAN_SIDFC_FLSSA_Pos     (2U)

+#define FDCAN_SIDFC_FLSSA_Msk     (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)          /*!< 0x0000FFFC */

+#define FDCAN_SIDFC_FLSSA         FDCAN_SIDFC_FLSSA_Msk                        /*!<Filter List Standard Start Address        */

+#define FDCAN_SIDFC_LSS_Pos       (16U)

+#define FDCAN_SIDFC_LSS_Msk       (0xFFUL << FDCAN_SIDFC_LSS_Pos)              /*!< 0x00FF0000 */

+#define FDCAN_SIDFC_LSS           FDCAN_SIDFC_LSS_Msk                          /*!<List Size Standard                        */

+

+/*****************  Bit definition for FDCAN_XIDFC register  ********************/

+#define FDCAN_XIDFC_FLESA_Pos     (2U)

+#define FDCAN_XIDFC_FLESA_Msk     (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)          /*!< 0x0000FFFC */

+#define FDCAN_XIDFC_FLESA         FDCAN_XIDFC_FLESA_Msk                        /*!<Filter List Standard Start Address        */

+#define FDCAN_XIDFC_LSE_Pos       (16U)

+#define FDCAN_XIDFC_LSE_Msk       (0x7FUL << FDCAN_XIDFC_LSE_Pos)              /*!< 0x007F0000 */

+#define FDCAN_XIDFC_LSE           FDCAN_XIDFC_LSE_Msk                          /*!<List Size Extended                        */

+

+/*****************  Bit definition for FDCAN_XIDAM register  ********************/

+#define FDCAN_XIDAM_EIDM_Pos      (0U)

+#define FDCAN_XIDAM_EIDM_Msk      (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)       /*!< 0x1FFFFFFF */

+#define FDCAN_XIDAM_EIDM          FDCAN_XIDAM_EIDM_Msk                         /*!<Extended ID Mask                          */

+

+/*****************  Bit definition for FDCAN_HPMS register  *********************/

+#define FDCAN_HPMS_BIDX_Pos       (0U)

+#define FDCAN_HPMS_BIDX_Msk       (0x3FUL << FDCAN_HPMS_BIDX_Pos)              /*!< 0x0000003F */

+#define FDCAN_HPMS_BIDX           FDCAN_HPMS_BIDX_Msk                          /*!<Buffer Index                              */

+#define FDCAN_HPMS_MSI_Pos        (6U)

+#define FDCAN_HPMS_MSI_Msk        (0x3UL << FDCAN_HPMS_MSI_Pos)                /*!< 0x000000C0 */

+#define FDCAN_HPMS_MSI            FDCAN_HPMS_MSI_Msk                           /*!<Message Storage Indicator                 */

+#define FDCAN_HPMS_FIDX_Pos       (8U)

+#define FDCAN_HPMS_FIDX_Msk       (0x7FUL << FDCAN_HPMS_FIDX_Pos)              /*!< 0x00007F00 */

+#define FDCAN_HPMS_FIDX           FDCAN_HPMS_FIDX_Msk                          /*!<Filter Index                              */

+#define FDCAN_HPMS_FLST_Pos       (15U)

+#define FDCAN_HPMS_FLST_Msk       (0x1UL << FDCAN_HPMS_FLST_Pos)               /*!< 0x00008000 */

+#define FDCAN_HPMS_FLST           FDCAN_HPMS_FLST_Msk                          /*!<Filter List                               */

+

+/*****************  Bit definition for FDCAN_NDAT1 register  ********************/

+#define FDCAN_NDAT1_ND0_Pos       (0U)

+#define FDCAN_NDAT1_ND0_Msk       (0x1UL << FDCAN_NDAT1_ND0_Pos)               /*!< 0x00000001 */

+#define FDCAN_NDAT1_ND0           FDCAN_NDAT1_ND0_Msk                          /*!<New Data flag of Rx Buffer 0              */

+#define FDCAN_NDAT1_ND1_Pos       (1U)

+#define FDCAN_NDAT1_ND1_Msk       (0x1UL << FDCAN_NDAT1_ND1_Pos)               /*!< 0x00000002 */

+#define FDCAN_NDAT1_ND1           FDCAN_NDAT1_ND1_Msk                          /*!<New Data flag of Rx Buffer 1              */

+#define FDCAN_NDAT1_ND2_Pos       (2U)

+#define FDCAN_NDAT1_ND2_Msk       (0x1UL << FDCAN_NDAT1_ND2_Pos)               /*!< 0x00000004 */

+#define FDCAN_NDAT1_ND2           FDCAN_NDAT1_ND2_Msk                          /*!<New Data flag of Rx Buffer 2              */

+#define FDCAN_NDAT1_ND3_Pos       (3U)

+#define FDCAN_NDAT1_ND3_Msk       (0x1UL << FDCAN_NDAT1_ND3_Pos)               /*!< 0x00000008 */

+#define FDCAN_NDAT1_ND3           FDCAN_NDAT1_ND3_Msk                          /*!<New Data flag of Rx Buffer 3              */

+#define FDCAN_NDAT1_ND4_Pos       (4U)

+#define FDCAN_NDAT1_ND4_Msk       (0x1UL << FDCAN_NDAT1_ND4_Pos)               /*!< 0x00000010 */

+#define FDCAN_NDAT1_ND4           FDCAN_NDAT1_ND4_Msk                          /*!<New Data flag of Rx Buffer 4              */

+#define FDCAN_NDAT1_ND5_Pos       (5U)

+#define FDCAN_NDAT1_ND5_Msk       (0x1UL << FDCAN_NDAT1_ND5_Pos)               /*!< 0x00000020 */

+#define FDCAN_NDAT1_ND5           FDCAN_NDAT1_ND5_Msk                          /*!<New Data flag of Rx Buffer 5              */

+#define FDCAN_NDAT1_ND6_Pos       (6U)

+#define FDCAN_NDAT1_ND6_Msk       (0x1UL << FDCAN_NDAT1_ND6_Pos)               /*!< 0x00000040 */

+#define FDCAN_NDAT1_ND6           FDCAN_NDAT1_ND6_Msk                          /*!<New Data flag of Rx Buffer 6              */

+#define FDCAN_NDAT1_ND7_Pos       (7U)

+#define FDCAN_NDAT1_ND7_Msk       (0x1UL << FDCAN_NDAT1_ND7_Pos)               /*!< 0x00000080 */

+#define FDCAN_NDAT1_ND7           FDCAN_NDAT1_ND7_Msk                          /*!<New Data flag of Rx Buffer 7              */

+#define FDCAN_NDAT1_ND8_Pos       (8U)

+#define FDCAN_NDAT1_ND8_Msk       (0x1UL << FDCAN_NDAT1_ND8_Pos)               /*!< 0x00000100 */

+#define FDCAN_NDAT1_ND8           FDCAN_NDAT1_ND8_Msk                          /*!<New Data flag of Rx Buffer 8              */

+#define FDCAN_NDAT1_ND9_Pos       (9U)

+#define FDCAN_NDAT1_ND9_Msk       (0x1UL << FDCAN_NDAT1_ND9_Pos)               /*!< 0x00000200 */

+#define FDCAN_NDAT1_ND9           FDCAN_NDAT1_ND9_Msk                          /*!<New Data flag of Rx Buffer 9              */

+#define FDCAN_NDAT1_ND10_Pos      (10U)

+#define FDCAN_NDAT1_ND10_Msk      (0x1UL << FDCAN_NDAT1_ND10_Pos)              /*!< 0x00000400 */

+#define FDCAN_NDAT1_ND10          FDCAN_NDAT1_ND10_Msk                         /*!<New Data flag of Rx Buffer 10             */

+#define FDCAN_NDAT1_ND11_Pos      (11U)

+#define FDCAN_NDAT1_ND11_Msk      (0x1UL << FDCAN_NDAT1_ND11_Pos)              /*!< 0x00000800 */

+#define FDCAN_NDAT1_ND11          FDCAN_NDAT1_ND11_Msk                         /*!<New Data flag of Rx Buffer 11             */

+#define FDCAN_NDAT1_ND12_Pos      (12U)

+#define FDCAN_NDAT1_ND12_Msk      (0x1UL << FDCAN_NDAT1_ND12_Pos)              /*!< 0x00001000 */

+#define FDCAN_NDAT1_ND12          FDCAN_NDAT1_ND12_Msk                         /*!<New Data flag of Rx Buffer 12             */

+#define FDCAN_NDAT1_ND13_Pos      (13U)

+#define FDCAN_NDAT1_ND13_Msk      (0x1UL << FDCAN_NDAT1_ND13_Pos)              /*!< 0x00002000 */

+#define FDCAN_NDAT1_ND13          FDCAN_NDAT1_ND13_Msk                         /*!<New Data flag of Rx Buffer 13             */

+#define FDCAN_NDAT1_ND14_Pos      (14U)

+#define FDCAN_NDAT1_ND14_Msk      (0x1UL << FDCAN_NDAT1_ND14_Pos)              /*!< 0x00004000 */

+#define FDCAN_NDAT1_ND14          FDCAN_NDAT1_ND14_Msk                         /*!<New Data flag of Rx Buffer 14             */

+#define FDCAN_NDAT1_ND15_Pos      (15U)

+#define FDCAN_NDAT1_ND15_Msk      (0x1UL << FDCAN_NDAT1_ND15_Pos)              /*!< 0x00008000 */

+#define FDCAN_NDAT1_ND15          FDCAN_NDAT1_ND15_Msk                         /*!<New Data flag of Rx Buffer 15             */

+#define FDCAN_NDAT1_ND16_Pos      (16U)

+#define FDCAN_NDAT1_ND16_Msk      (0x1UL << FDCAN_NDAT1_ND16_Pos)              /*!< 0x00010000 */

+#define FDCAN_NDAT1_ND16          FDCAN_NDAT1_ND16_Msk                         /*!<New Data flag of Rx Buffer 16             */

+#define FDCAN_NDAT1_ND17_Pos      (17U)

+#define FDCAN_NDAT1_ND17_Msk      (0x1UL << FDCAN_NDAT1_ND17_Pos)              /*!< 0x00020000 */

+#define FDCAN_NDAT1_ND17          FDCAN_NDAT1_ND17_Msk                         /*!<New Data flag of Rx Buffer 17             */

+#define FDCAN_NDAT1_ND18_Pos      (18U)

+#define FDCAN_NDAT1_ND18_Msk      (0x1UL << FDCAN_NDAT1_ND18_Pos)              /*!< 0x00040000 */

+#define FDCAN_NDAT1_ND18          FDCAN_NDAT1_ND18_Msk                         /*!<New Data flag of Rx Buffer 18             */

+#define FDCAN_NDAT1_ND19_Pos      (19U)

+#define FDCAN_NDAT1_ND19_Msk      (0x1UL << FDCAN_NDAT1_ND19_Pos)              /*!< 0x00080000 */

+#define FDCAN_NDAT1_ND19          FDCAN_NDAT1_ND19_Msk                         /*!<New Data flag of Rx Buffer 19             */

+#define FDCAN_NDAT1_ND20_Pos      (20U)

+#define FDCAN_NDAT1_ND20_Msk      (0x1UL << FDCAN_NDAT1_ND20_Pos)              /*!< 0x00100000 */

+#define FDCAN_NDAT1_ND20          FDCAN_NDAT1_ND20_Msk                         /*!<New Data flag of Rx Buffer 20             */

+#define FDCAN_NDAT1_ND21_Pos      (21U)

+#define FDCAN_NDAT1_ND21_Msk      (0x1UL << FDCAN_NDAT1_ND21_Pos)              /*!< 0x00200000 */

+#define FDCAN_NDAT1_ND21          FDCAN_NDAT1_ND21_Msk                         /*!<New Data flag of Rx Buffer 21             */

+#define FDCAN_NDAT1_ND22_Pos      (22U)

+#define FDCAN_NDAT1_ND22_Msk      (0x1UL << FDCAN_NDAT1_ND22_Pos)              /*!< 0x00400000 */

+#define FDCAN_NDAT1_ND22          FDCAN_NDAT1_ND22_Msk                         /*!<New Data flag of Rx Buffer 22             */

+#define FDCAN_NDAT1_ND23_Pos      (23U)

+#define FDCAN_NDAT1_ND23_Msk      (0x1UL << FDCAN_NDAT1_ND23_Pos)              /*!< 0x00800000 */

+#define FDCAN_NDAT1_ND23          FDCAN_NDAT1_ND23_Msk                         /*!<New Data flag of Rx Buffer 23             */

+#define FDCAN_NDAT1_ND24_Pos      (24U)

+#define FDCAN_NDAT1_ND24_Msk      (0x1UL << FDCAN_NDAT1_ND24_Pos)              /*!< 0x01000000 */

+#define FDCAN_NDAT1_ND24          FDCAN_NDAT1_ND24_Msk                         /*!<New Data flag of Rx Buffer 24             */

+#define FDCAN_NDAT1_ND25_Pos      (25U)

+#define FDCAN_NDAT1_ND25_Msk      (0x1UL << FDCAN_NDAT1_ND25_Pos)              /*!< 0x02000000 */

+#define FDCAN_NDAT1_ND25          FDCAN_NDAT1_ND25_Msk                         /*!<New Data flag of Rx Buffer 25             */

+#define FDCAN_NDAT1_ND26_Pos      (26U)

+#define FDCAN_NDAT1_ND26_Msk      (0x1UL << FDCAN_NDAT1_ND26_Pos)              /*!< 0x04000000 */

+#define FDCAN_NDAT1_ND26          FDCAN_NDAT1_ND26_Msk                         /*!<New Data flag of Rx Buffer 26             */

+#define FDCAN_NDAT1_ND27_Pos      (27U)

+#define FDCAN_NDAT1_ND27_Msk      (0x1UL << FDCAN_NDAT1_ND27_Pos)              /*!< 0x08000000 */

+#define FDCAN_NDAT1_ND27          FDCAN_NDAT1_ND27_Msk                         /*!<New Data flag of Rx Buffer 27             */

+#define FDCAN_NDAT1_ND28_Pos      (28U)

+#define FDCAN_NDAT1_ND28_Msk      (0x1UL << FDCAN_NDAT1_ND28_Pos)              /*!< 0x10000000 */

+#define FDCAN_NDAT1_ND28          FDCAN_NDAT1_ND28_Msk                         /*!<New Data flag of Rx Buffer 28             */

+#define FDCAN_NDAT1_ND29_Pos      (29U)

+#define FDCAN_NDAT1_ND29_Msk      (0x1UL << FDCAN_NDAT1_ND29_Pos)              /*!< 0x20000000 */

+#define FDCAN_NDAT1_ND29          FDCAN_NDAT1_ND29_Msk                         /*!<New Data flag of Rx Buffer 29             */

+#define FDCAN_NDAT1_ND30_Pos      (30U)

+#define FDCAN_NDAT1_ND30_Msk      (0x1UL << FDCAN_NDAT1_ND30_Pos)              /*!< 0x40000000 */

+#define FDCAN_NDAT1_ND30          FDCAN_NDAT1_ND30_Msk                         /*!<New Data flag of Rx Buffer 30             */

+#define FDCAN_NDAT1_ND31_Pos      (31U)

+#define FDCAN_NDAT1_ND31_Msk      (0x1UL << FDCAN_NDAT1_ND31_Pos)              /*!< 0x80000000 */

+#define FDCAN_NDAT1_ND31          FDCAN_NDAT1_ND31_Msk                         /*!<New Data flag of Rx Buffer 31             */

+

+/*****************  Bit definition for FDCAN_NDAT2 register  ********************/

+#define FDCAN_NDAT2_ND32_Pos      (0U)

+#define FDCAN_NDAT2_ND32_Msk      (0x1UL << FDCAN_NDAT2_ND32_Pos)              /*!< 0x00000001 */

+#define FDCAN_NDAT2_ND32          FDCAN_NDAT2_ND32_Msk                         /*!<New Data flag of Rx Buffer 32             */

+#define FDCAN_NDAT2_ND33_Pos      (1U)

+#define FDCAN_NDAT2_ND33_Msk      (0x1UL << FDCAN_NDAT2_ND33_Pos)              /*!< 0x00000002 */

+#define FDCAN_NDAT2_ND33          FDCAN_NDAT2_ND33_Msk                         /*!<New Data flag of Rx Buffer 33             */

+#define FDCAN_NDAT2_ND34_Pos      (2U)

+#define FDCAN_NDAT2_ND34_Msk      (0x1UL << FDCAN_NDAT2_ND34_Pos)              /*!< 0x00000004 */

+#define FDCAN_NDAT2_ND34          FDCAN_NDAT2_ND34_Msk                         /*!<New Data flag of Rx Buffer 34             */

+#define FDCAN_NDAT2_ND35_Pos      (3U)

+#define FDCAN_NDAT2_ND35_Msk      (0x1UL << FDCAN_NDAT2_ND35_Pos)              /*!< 0x00000008 */

+#define FDCAN_NDAT2_ND35          FDCAN_NDAT2_ND35_Msk                         /*!<New Data flag of Rx Buffer 35             */

+#define FDCAN_NDAT2_ND36_Pos      (4U)

+#define FDCAN_NDAT2_ND36_Msk      (0x1UL << FDCAN_NDAT2_ND36_Pos)              /*!< 0x00000010 */

+#define FDCAN_NDAT2_ND36          FDCAN_NDAT2_ND36_Msk                         /*!<New Data flag of Rx Buffer 36             */

+#define FDCAN_NDAT2_ND37_Pos      (5U)

+#define FDCAN_NDAT2_ND37_Msk      (0x1UL << FDCAN_NDAT2_ND37_Pos)              /*!< 0x00000020 */

+#define FDCAN_NDAT2_ND37          FDCAN_NDAT2_ND37_Msk                         /*!<New Data flag of Rx Buffer 37             */

+#define FDCAN_NDAT2_ND38_Pos      (6U)

+#define FDCAN_NDAT2_ND38_Msk      (0x1UL << FDCAN_NDAT2_ND38_Pos)              /*!< 0x00000040 */

+#define FDCAN_NDAT2_ND38          FDCAN_NDAT2_ND38_Msk                         /*!<New Data flag of Rx Buffer 38             */

+#define FDCAN_NDAT2_ND39_Pos      (7U)

+#define FDCAN_NDAT2_ND39_Msk      (0x1UL << FDCAN_NDAT2_ND39_Pos)              /*!< 0x00000080 */

+#define FDCAN_NDAT2_ND39          FDCAN_NDAT2_ND39_Msk                         /*!<New Data flag of Rx Buffer 39             */

+#define FDCAN_NDAT2_ND40_Pos      (8U)

+#define FDCAN_NDAT2_ND40_Msk      (0x1UL << FDCAN_NDAT2_ND40_Pos)              /*!< 0x00000100 */

+#define FDCAN_NDAT2_ND40          FDCAN_NDAT2_ND40_Msk                         /*!<New Data flag of Rx Buffer 40             */

+#define FDCAN_NDAT2_ND41_Pos      (9U)

+#define FDCAN_NDAT2_ND41_Msk      (0x1UL << FDCAN_NDAT2_ND41_Pos)              /*!< 0x00000200 */

+#define FDCAN_NDAT2_ND41          FDCAN_NDAT2_ND41_Msk                         /*!<New Data flag of Rx Buffer 41             */

+#define FDCAN_NDAT2_ND42_Pos      (10U)

+#define FDCAN_NDAT2_ND42_Msk      (0x1UL << FDCAN_NDAT2_ND42_Pos)              /*!< 0x00000400 */

+#define FDCAN_NDAT2_ND42          FDCAN_NDAT2_ND42_Msk                         /*!<New Data flag of Rx Buffer 42             */

+#define FDCAN_NDAT2_ND43_Pos      (11U)

+#define FDCAN_NDAT2_ND43_Msk      (0x1UL << FDCAN_NDAT2_ND43_Pos)              /*!< 0x00000800 */

+#define FDCAN_NDAT2_ND43          FDCAN_NDAT2_ND43_Msk                         /*!<New Data flag of Rx Buffer 43             */

+#define FDCAN_NDAT2_ND44_Pos      (12U)

+#define FDCAN_NDAT2_ND44_Msk      (0x1UL << FDCAN_NDAT2_ND44_Pos)              /*!< 0x00001000 */

+#define FDCAN_NDAT2_ND44          FDCAN_NDAT2_ND44_Msk                         /*!<New Data flag of Rx Buffer 44             */

+#define FDCAN_NDAT2_ND45_Pos      (13U)

+#define FDCAN_NDAT2_ND45_Msk      (0x1UL << FDCAN_NDAT2_ND45_Pos)              /*!< 0x00002000 */

+#define FDCAN_NDAT2_ND45          FDCAN_NDAT2_ND45_Msk                         /*!<New Data flag of Rx Buffer 45             */

+#define FDCAN_NDAT2_ND46_Pos      (14U)

+#define FDCAN_NDAT2_ND46_Msk      (0x1UL << FDCAN_NDAT2_ND46_Pos)              /*!< 0x00004000 */

+#define FDCAN_NDAT2_ND46          FDCAN_NDAT2_ND46_Msk                         /*!<New Data flag of Rx Buffer 46             */

+#define FDCAN_NDAT2_ND47_Pos      (15U)

+#define FDCAN_NDAT2_ND47_Msk      (0x1UL << FDCAN_NDAT2_ND47_Pos)              /*!< 0x00008000 */

+#define FDCAN_NDAT2_ND47          FDCAN_NDAT2_ND47_Msk                         /*!<New Data flag of Rx Buffer 47             */

+#define FDCAN_NDAT2_ND48_Pos      (16U)

+#define FDCAN_NDAT2_ND48_Msk      (0x1UL << FDCAN_NDAT2_ND48_Pos)              /*!< 0x00010000 */

+#define FDCAN_NDAT2_ND48          FDCAN_NDAT2_ND48_Msk                         /*!<New Data flag of Rx Buffer 48             */

+#define FDCAN_NDAT2_ND49_Pos      (17U)

+#define FDCAN_NDAT2_ND49_Msk      (0x1UL << FDCAN_NDAT2_ND49_Pos)              /*!< 0x00020000 */

+#define FDCAN_NDAT2_ND49          FDCAN_NDAT2_ND49_Msk                         /*!<New Data flag of Rx Buffer 49             */

+#define FDCAN_NDAT2_ND50_Pos      (18U)

+#define FDCAN_NDAT2_ND50_Msk      (0x1UL << FDCAN_NDAT2_ND50_Pos)              /*!< 0x00040000 */

+#define FDCAN_NDAT2_ND50          FDCAN_NDAT2_ND50_Msk                         /*!<New Data flag of Rx Buffer 50             */

+#define FDCAN_NDAT2_ND51_Pos      (19U)

+#define FDCAN_NDAT2_ND51_Msk      (0x1UL << FDCAN_NDAT2_ND51_Pos)              /*!< 0x00080000 */

+#define FDCAN_NDAT2_ND51          FDCAN_NDAT2_ND51_Msk                         /*!<New Data flag of Rx Buffer 51             */

+#define FDCAN_NDAT2_ND52_Pos      (20U)

+#define FDCAN_NDAT2_ND52_Msk      (0x1UL << FDCAN_NDAT2_ND52_Pos)              /*!< 0x00100000 */

+#define FDCAN_NDAT2_ND52          FDCAN_NDAT2_ND52_Msk                         /*!<New Data flag of Rx Buffer 52             */

+#define FDCAN_NDAT2_ND53_Pos      (21U)

+#define FDCAN_NDAT2_ND53_Msk      (0x1UL << FDCAN_NDAT2_ND53_Pos)              /*!< 0x00200000 */

+#define FDCAN_NDAT2_ND53          FDCAN_NDAT2_ND53_Msk                         /*!<New Data flag of Rx Buffer 53             */

+#define FDCAN_NDAT2_ND54_Pos      (22U)

+#define FDCAN_NDAT2_ND54_Msk      (0x1UL << FDCAN_NDAT2_ND54_Pos)              /*!< 0x00400000 */

+#define FDCAN_NDAT2_ND54          FDCAN_NDAT2_ND54_Msk                         /*!<New Data flag of Rx Buffer 54             */

+#define FDCAN_NDAT2_ND55_Pos      (23U)

+#define FDCAN_NDAT2_ND55_Msk      (0x1UL << FDCAN_NDAT2_ND55_Pos)              /*!< 0x00800000 */

+#define FDCAN_NDAT2_ND55          FDCAN_NDAT2_ND55_Msk                         /*!<New Data flag of Rx Buffer 55             */

+#define FDCAN_NDAT2_ND56_Pos      (24U)

+#define FDCAN_NDAT2_ND56_Msk      (0x1UL << FDCAN_NDAT2_ND56_Pos)              /*!< 0x01000000 */

+#define FDCAN_NDAT2_ND56          FDCAN_NDAT2_ND56_Msk                         /*!<New Data flag of Rx Buffer 56             */

+#define FDCAN_NDAT2_ND57_Pos      (25U)

+#define FDCAN_NDAT2_ND57_Msk      (0x1UL << FDCAN_NDAT2_ND57_Pos)              /*!< 0x02000000 */

+#define FDCAN_NDAT2_ND57          FDCAN_NDAT2_ND57_Msk                         /*!<New Data flag of Rx Buffer 57             */

+#define FDCAN_NDAT2_ND58_Pos      (26U)

+#define FDCAN_NDAT2_ND58_Msk      (0x1UL << FDCAN_NDAT2_ND58_Pos)              /*!< 0x04000000 */

+#define FDCAN_NDAT2_ND58          FDCAN_NDAT2_ND58_Msk                         /*!<New Data flag of Rx Buffer 58             */

+#define FDCAN_NDAT2_ND59_Pos      (27U)

+#define FDCAN_NDAT2_ND59_Msk      (0x1UL << FDCAN_NDAT2_ND59_Pos)              /*!< 0x08000000 */

+#define FDCAN_NDAT2_ND59          FDCAN_NDAT2_ND59_Msk                         /*!<New Data flag of Rx Buffer 59             */

+#define FDCAN_NDAT2_ND60_Pos      (28U)

+#define FDCAN_NDAT2_ND60_Msk      (0x1UL << FDCAN_NDAT2_ND60_Pos)              /*!< 0x10000000 */

+#define FDCAN_NDAT2_ND60          FDCAN_NDAT2_ND60_Msk                         /*!<New Data flag of Rx Buffer 60             */

+#define FDCAN_NDAT2_ND61_Pos      (29U)

+#define FDCAN_NDAT2_ND61_Msk      (0x1UL << FDCAN_NDAT2_ND61_Pos)              /*!< 0x20000000 */

+#define FDCAN_NDAT2_ND61          FDCAN_NDAT2_ND61_Msk                         /*!<New Data flag of Rx Buffer 61             */

+#define FDCAN_NDAT2_ND62_Pos      (30U)

+#define FDCAN_NDAT2_ND62_Msk      (0x1UL << FDCAN_NDAT2_ND62_Pos)              /*!< 0x40000000 */

+#define FDCAN_NDAT2_ND62          FDCAN_NDAT2_ND62_Msk                         /*!<New Data flag of Rx Buffer 62             */

+#define FDCAN_NDAT2_ND63_Pos      (31U)

+#define FDCAN_NDAT2_ND63_Msk      (0x1UL << FDCAN_NDAT2_ND63_Pos)              /*!< 0x80000000 */

+#define FDCAN_NDAT2_ND63          FDCAN_NDAT2_ND63_Msk                         /*!<New Data flag of Rx Buffer 63             */

+

+/*****************  Bit definition for FDCAN_RXF0C register  ********************/

+#define FDCAN_RXF0C_F0SA_Pos      (2U)

+#define FDCAN_RXF0C_F0SA_Msk      (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_RXF0C_F0SA          FDCAN_RXF0C_F0SA_Msk                         /*!<Rx FIFO 0 Start Address                   */

+#define FDCAN_RXF0C_F0S_Pos       (16U)

+#define FDCAN_RXF0C_F0S_Msk       (0x7FUL << FDCAN_RXF0C_F0S_Pos)              /*!< 0x007F0000 */

+#define FDCAN_RXF0C_F0S           FDCAN_RXF0C_F0S_Msk                          /*!<Number of Rx FIFO 0 elements              */

+#define FDCAN_RXF0C_F0WM_Pos      (24U)

+#define FDCAN_RXF0C_F0WM_Msk      (0x7FUL << FDCAN_RXF0C_F0WM_Pos)             /*!< 0x7F000000 */

+#define FDCAN_RXF0C_F0WM          FDCAN_RXF0C_F0WM_Msk                         /*!<FIFO 0 Watermark                          */

+#define FDCAN_RXF0C_F0OM_Pos      (31U)

+#define FDCAN_RXF0C_F0OM_Msk      (0x1UL << FDCAN_RXF0C_F0OM_Pos)              /*!< 0x80000000 */

+#define FDCAN_RXF0C_F0OM          FDCAN_RXF0C_F0OM_Msk                         /*!<FIFO 0 Operation Mode                     */

+

+/*****************  Bit definition for FDCAN_RXF0S register  ********************/

+#define FDCAN_RXF0S_F0FL_Pos      (0U)

+#define FDCAN_RXF0S_F0FL_Msk      (0x7FUL << FDCAN_RXF0S_F0FL_Pos)             /*!< 0x0000007F */

+#define FDCAN_RXF0S_F0FL          FDCAN_RXF0S_F0FL_Msk                         /*!<Rx FIFO 0 Fill Level                      */

+#define FDCAN_RXF0S_F0GI_Pos      (8U)

+#define FDCAN_RXF0S_F0GI_Msk      (0x3FUL << FDCAN_RXF0S_F0GI_Pos)             /*!< 0x00003F00 */

+#define FDCAN_RXF0S_F0GI          FDCAN_RXF0S_F0GI_Msk                         /*!<Rx FIFO 0 Get Index                       */

+#define FDCAN_RXF0S_F0PI_Pos      (16U)

+#define FDCAN_RXF0S_F0PI_Msk      (0x3FUL << FDCAN_RXF0S_F0PI_Pos)             /*!< 0x003F0000 */

+#define FDCAN_RXF0S_F0PI          FDCAN_RXF0S_F0PI_Msk                         /*!<Rx FIFO 0 Put Index                       */

+#define FDCAN_RXF0S_F0F_Pos       (24U)

+#define FDCAN_RXF0S_F0F_Msk       (0x1UL << FDCAN_RXF0S_F0F_Pos)               /*!< 0x01000000 */

+#define FDCAN_RXF0S_F0F           FDCAN_RXF0S_F0F_Msk                          /*!<Rx FIFO 0 Full                            */

+#define FDCAN_RXF0S_RF0L_Pos      (25U)

+#define FDCAN_RXF0S_RF0L_Msk      (0x1UL << FDCAN_RXF0S_RF0L_Pos)              /*!< 0x02000000 */

+#define FDCAN_RXF0S_RF0L          FDCAN_RXF0S_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                    */

+

+/*****************  Bit definition for FDCAN_RXF0A register  ********************/

+#define FDCAN_RXF0A_F0AI_Pos      (0U)

+#define FDCAN_RXF0A_F0AI_Msk      (0x3FUL << FDCAN_RXF0A_F0AI_Pos)             /*!< 0x0000003F */

+#define FDCAN_RXF0A_F0AI          FDCAN_RXF0A_F0AI_Msk                         /*!<Rx FIFO 0 Acknowledge Index               */

+

+/*****************  Bit definition for FDCAN_RXBC register  ********************/

+#define FDCAN_RXBC_RBSA_Pos       (2U)

+#define FDCAN_RXBC_RBSA_Msk       (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)            /*!< 0x0000FFFC */

+#define FDCAN_RXBC_RBSA           FDCAN_RXBC_RBSA_Msk                          /*!<Rx Buffer Start Address                   */

+

+/*****************  Bit definition for FDCAN_RXF1C register  ********************/

+#define FDCAN_RXF1C_F1SA_Pos      (2U)

+#define FDCAN_RXF1C_F1SA_Msk      (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_RXF1C_F1SA          FDCAN_RXF1C_F1SA_Msk                         /*!<Rx FIFO 1 Start Address                   */

+#define FDCAN_RXF1C_F1S_Pos       (16U)

+#define FDCAN_RXF1C_F1S_Msk       (0x7FUL << FDCAN_RXF1C_F1S_Pos)              /*!< 0x007F0000 */

+#define FDCAN_RXF1C_F1S           FDCAN_RXF1C_F1S_Msk                          /*!<Number of Rx FIFO 1 elements              */

+#define FDCAN_RXF1C_F1WM_Pos      (24U)

+#define FDCAN_RXF1C_F1WM_Msk      (0x7FUL << FDCAN_RXF1C_F1WM_Pos)             /*!< 0x7F000000 */

+#define FDCAN_RXF1C_F1WM          FDCAN_RXF1C_F1WM_Msk                         /*!<Rx FIFO 1 Watermark                       */

+#define FDCAN_RXF1C_F1OM_Pos      (31U)

+#define FDCAN_RXF1C_F1OM_Msk      (0x1UL << FDCAN_RXF1C_F1OM_Pos)              /*!< 0x80000000 */

+#define FDCAN_RXF1C_F1OM          FDCAN_RXF1C_F1OM_Msk                         /*!<FIFO 1 Operation Mode                     */

+

+/*****************  Bit definition for FDCAN_RXF1S register  ********************/

+#define FDCAN_RXF1S_F1FL_Pos      (0U)

+#define FDCAN_RXF1S_F1FL_Msk      (0x7FUL << FDCAN_RXF1S_F1FL_Pos)             /*!< 0x0000007F */

+#define FDCAN_RXF1S_F1FL          FDCAN_RXF1S_F1FL_Msk                         /*!<Rx FIFO 1 Fill Level                      */

+#define FDCAN_RXF1S_F1GI_Pos      (8U)

+#define FDCAN_RXF1S_F1GI_Msk      (0x3FUL << FDCAN_RXF1S_F1GI_Pos)             /*!< 0x00003F00 */

+#define FDCAN_RXF1S_F1GI          FDCAN_RXF1S_F1GI_Msk                         /*!<Rx FIFO 1 Get Index                       */

+#define FDCAN_RXF1S_F1PI_Pos      (16U)

+#define FDCAN_RXF1S_F1PI_Msk      (0x3FUL << FDCAN_RXF1S_F1PI_Pos)             /*!< 0x003F0000 */

+#define FDCAN_RXF1S_F1PI          FDCAN_RXF1S_F1PI_Msk                         /*!<Rx FIFO 1 Put Index                       */

+#define FDCAN_RXF1S_F1F_Pos       (24U)

+#define FDCAN_RXF1S_F1F_Msk       (0x1UL << FDCAN_RXF1S_F1F_Pos)               /*!< 0x01000000 */

+#define FDCAN_RXF1S_F1F           FDCAN_RXF1S_F1F_Msk                          /*!<Rx FIFO 1 Full                            */

+#define FDCAN_RXF1S_RF1L_Pos      (25U)

+#define FDCAN_RXF1S_RF1L_Msk      (0x1UL << FDCAN_RXF1S_RF1L_Pos)              /*!< 0x02000000 */

+#define FDCAN_RXF1S_RF1L          FDCAN_RXF1S_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                    */

+

+/*****************  Bit definition for FDCAN_RXF1A register  ********************/

+#define FDCAN_RXF1A_F1AI_Pos      (0U)

+#define FDCAN_RXF1A_F1AI_Msk      (0x3FUL << FDCAN_RXF1A_F1AI_Pos)             /*!< 0x0000003F */

+#define FDCAN_RXF1A_F1AI          FDCAN_RXF1A_F1AI_Msk                         /*!<Rx FIFO 1 Acknowledge Index               */

+

+/*****************  Bit definition for FDCAN_RXESC register  ********************/

+#define FDCAN_RXESC_F0DS_Pos      (0U)

+#define FDCAN_RXESC_F0DS_Msk      (0x7UL << FDCAN_RXESC_F0DS_Pos)              /*!< 0x00000007 */

+#define FDCAN_RXESC_F0DS          FDCAN_RXESC_F0DS_Msk                         /*!<Rx FIFO 1 Data Field Size                 */

+#define FDCAN_RXESC_F1DS_Pos      (4U)

+#define FDCAN_RXESC_F1DS_Msk      (0x7UL << FDCAN_RXESC_F1DS_Pos)              /*!< 0x00000070 */

+#define FDCAN_RXESC_F1DS          FDCAN_RXESC_F1DS_Msk                         /*!<Rx FIFO 0 Data Field Size                 */

+#define FDCAN_RXESC_RBDS_Pos      (8U)

+#define FDCAN_RXESC_RBDS_Msk      (0x7UL << FDCAN_RXESC_RBDS_Pos)              /*!< 0x00000700 */

+#define FDCAN_RXESC_RBDS          FDCAN_RXESC_RBDS_Msk                         /*!<Rx Buffer Data Field Size                 */

+

+/*****************  Bit definition for FDCAN_TXBC register  *********************/

+#define FDCAN_TXBC_TBSA_Pos       (2U)

+#define FDCAN_TXBC_TBSA_Msk       (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)            /*!< 0x0000FFFC */

+#define FDCAN_TXBC_TBSA           FDCAN_TXBC_TBSA_Msk                          /*!<Tx Buffers Start Address                  */

+#define FDCAN_TXBC_NDTB_Pos       (16U)

+#define FDCAN_TXBC_NDTB_Msk       (0x3FUL << FDCAN_TXBC_NDTB_Pos)              /*!< 0x003F0000 */

+#define FDCAN_TXBC_NDTB           FDCAN_TXBC_NDTB_Msk                          /*!<Number of Dedicated Transmit Buffers      */

+#define FDCAN_TXBC_TFQS_Pos       (24U)

+#define FDCAN_TXBC_TFQS_Msk       (0x3FUL << FDCAN_TXBC_TFQS_Pos)              /*!< 0x3F000000 */

+#define FDCAN_TXBC_TFQS           FDCAN_TXBC_TFQS_Msk                          /*!<Transmit FIFO/Queue Size                  */

+#define FDCAN_TXBC_TFQM_Pos       (30U)

+#define FDCAN_TXBC_TFQM_Msk       (0x1UL << FDCAN_TXBC_TFQM_Pos)               /*!< 0x40000000 */

+#define FDCAN_TXBC_TFQM           FDCAN_TXBC_TFQM_Msk                          /*!<Tx FIFO/Queue Mode                        */

+

+/*****************  Bit definition for FDCAN_TXFQS register  *********************/

+#define FDCAN_TXFQS_TFFL_Pos      (0U)

+#define FDCAN_TXFQS_TFFL_Msk      (0x3FUL << FDCAN_TXFQS_TFFL_Pos)             /*!< 0x0000003F */

+#define FDCAN_TXFQS_TFFL          FDCAN_TXFQS_TFFL_Msk                         /*!<Tx FIFO Free Level                        */

+#define FDCAN_TXFQS_TFGI_Pos      (8U)

+#define FDCAN_TXFQS_TFGI_Msk      (0x1FUL << FDCAN_TXFQS_TFGI_Pos)             /*!< 0x00001F00 */

+#define FDCAN_TXFQS_TFGI          FDCAN_TXFQS_TFGI_Msk                         /*!<Tx FIFO Get Index                         */

+#define FDCAN_TXFQS_TFQPI_Pos     (16U)

+#define FDCAN_TXFQS_TFQPI_Msk     (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)            /*!< 0x001F0000 */

+#define FDCAN_TXFQS_TFQPI         FDCAN_TXFQS_TFQPI_Msk                        /*!<Tx FIFO/Queue Put Index                   */

+#define FDCAN_TXFQS_TFQF_Pos      (21U)

+#define FDCAN_TXFQS_TFQF_Msk      (0x1UL << FDCAN_TXFQS_TFQF_Pos)              /*!< 0x00200000 */

+#define FDCAN_TXFQS_TFQF          FDCAN_TXFQS_TFQF_Msk                         /*!<Tx FIFO/Queue Full                        */

+

+/*****************  Bit definition for FDCAN_TXESC register  *********************/

+#define FDCAN_TXESC_TBDS_Pos      (0U)

+#define FDCAN_TXESC_TBDS_Msk      (0x7UL << FDCAN_TXESC_TBDS_Pos)              /*!< 0x00000007 */

+#define FDCAN_TXESC_TBDS          FDCAN_TXESC_TBDS_Msk                         /*!<Tx Buffer Data Field Size                 */

+

+/*****************  Bit definition for FDCAN_TXBRP register  *********************/

+#define FDCAN_TXBRP_TRP_Pos       (0U)

+#define FDCAN_TXBRP_TRP_Msk       (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)        /*!< 0xFFFFFFFF */

+#define FDCAN_TXBRP_TRP           FDCAN_TXBRP_TRP_Msk                          /*!<Transmission Request Pending              */

+

+/*****************  Bit definition for FDCAN_TXBAR register  *********************/

+#define FDCAN_TXBAR_AR_Pos        (0U)

+#define FDCAN_TXBAR_AR_Msk        (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBAR_AR            FDCAN_TXBAR_AR_Msk                           /*!<Add Request                               */

+

+/*****************  Bit definition for FDCAN_TXBCR register  *********************/

+#define FDCAN_TXBCR_CR_Pos        (0U)

+#define FDCAN_TXBCR_CR_Msk        (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCR_CR            FDCAN_TXBCR_CR_Msk                           /*!<Cancellation Request                      */

+

+/*****************  Bit definition for FDCAN_TXBTO register  *********************/

+#define FDCAN_TXBTO_TO_Pos        (0U)

+#define FDCAN_TXBTO_TO_Msk        (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBTO_TO            FDCAN_TXBTO_TO_Msk                           /*!<Transmission Occurred                     */

+

+/*****************  Bit definition for FDCAN_TXBCF register  *********************/

+#define FDCAN_TXBCF_CF_Pos        (0U)

+#define FDCAN_TXBCF_CF_Msk        (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCF_CF            FDCAN_TXBCF_CF_Msk                           /*!<Cancellation Finished                     */

+

+/*****************  Bit definition for FDCAN_TXBTIE register  ********************/

+#define FDCAN_TXBTIE_TIE_Pos      (0U)

+#define FDCAN_TXBTIE_TIE_Msk      (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)       /*!< 0xFFFFFFFF */

+#define FDCAN_TXBTIE_TIE          FDCAN_TXBTIE_TIE_Msk                         /*!<Transmission Interrupt Enable             */

+

+/*****************  Bit definition for FDCAN_ TXBCIE register  *******************/

+#define FDCAN_TXBCIE_CFIE_Pos     (0U)

+#define FDCAN_TXBCIE_CFIE_Msk     (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)      /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCIE_CFIE         FDCAN_TXBCIE_CFIE_Msk                        /*!<Cancellation Finished Interrupt Enable    */

+

+/*****************  Bit definition for FDCAN_TXEFC register  *********************/

+#define FDCAN_TXEFC_EFSA_Pos      (2U)

+#define FDCAN_TXEFC_EFSA_Msk      (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_TXEFC_EFSA          FDCAN_TXEFC_EFSA_Msk                         /*!<Event FIFO Start Address                  */

+#define FDCAN_TXEFC_EFS_Pos       (16U)

+#define FDCAN_TXEFC_EFS_Msk       (0x3FUL << FDCAN_TXEFC_EFS_Pos)              /*!< 0x003F0000 */

+#define FDCAN_TXEFC_EFS           FDCAN_TXEFC_EFS_Msk                          /*!<Event FIFO Size                           */

+#define FDCAN_TXEFC_EFWM_Pos      (24U)

+#define FDCAN_TXEFC_EFWM_Msk      (0x3FUL << FDCAN_TXEFC_EFWM_Pos)             /*!< 0x3F000000 */

+#define FDCAN_TXEFC_EFWM          FDCAN_TXEFC_EFWM_Msk                         /*!<Event FIFO Watermark                      */

+

+/*****************  Bit definition for FDCAN_TXEFS register  *********************/

+#define FDCAN_TXEFS_EFFL_Pos      (0U)

+#define FDCAN_TXEFS_EFFL_Msk      (0x3FUL << FDCAN_TXEFS_EFFL_Pos)             /*!< 0x0000003F */

+#define FDCAN_TXEFS_EFFL          FDCAN_TXEFS_EFFL_Msk                         /*!<Event FIFO Fill Level                     */

+#define FDCAN_TXEFS_EFGI_Pos      (8U)

+#define FDCAN_TXEFS_EFGI_Msk      (0x1FUL << FDCAN_TXEFS_EFGI_Pos)             /*!< 0x00001F00 */

+#define FDCAN_TXEFS_EFGI          FDCAN_TXEFS_EFGI_Msk                         /*!<Event FIFO Get Index                      */

+#define FDCAN_TXEFS_EFPI_Pos      (16U)

+#define FDCAN_TXEFS_EFPI_Msk      (0x1FUL << FDCAN_TXEFS_EFPI_Pos)             /*!< 0x001F0000 */

+#define FDCAN_TXEFS_EFPI          FDCAN_TXEFS_EFPI_Msk                         /*!<Event FIFO Put Index                      */

+#define FDCAN_TXEFS_EFF_Pos       (24U)

+#define FDCAN_TXEFS_EFF_Msk       (0x1UL << FDCAN_TXEFS_EFF_Pos)               /*!< 0x01000000 */

+#define FDCAN_TXEFS_EFF           FDCAN_TXEFS_EFF_Msk                          /*!<Event FIFO Full                           */

+#define FDCAN_TXEFS_TEFL_Pos      (25U)

+#define FDCAN_TXEFS_TEFL_Msk      (0x1UL << FDCAN_TXEFS_TEFL_Pos)              /*!< 0x02000000 */

+#define FDCAN_TXEFS_TEFL          FDCAN_TXEFS_TEFL_Msk                         /*!<Tx Event FIFO Element Lost                */

+

+/*****************  Bit definition for FDCAN_TXEFA register  *********************/

+#define FDCAN_TXEFA_EFAI_Pos      (0U)

+#define FDCAN_TXEFA_EFAI_Msk      (0x1FUL << FDCAN_TXEFA_EFAI_Pos)             /*!< 0x0000001F */

+#define FDCAN_TXEFA_EFAI          FDCAN_TXEFA_EFAI_Msk                         /*!<Event FIFO Acknowledge Index              */

+

+/*****************  Bit definition for FDCAN_TTTMC register  *********************/

+#define FDCAN_TTTMC_TMSA_Pos      (2U)

+#define FDCAN_TTTMC_TMSA_Msk      (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_TTTMC_TMSA          FDCAN_TTTMC_TMSA_Msk                         /*!<Trigger Memory Start Address              */

+#define FDCAN_TTTMC_TME_Pos       (16U)

+#define FDCAN_TTTMC_TME_Msk       (0x7FUL << FDCAN_TTTMC_TME_Pos)              /*!< 0x007F0000 */

+#define FDCAN_TTTMC_TME           FDCAN_TTTMC_TME_Msk                          /*!<Trigger Memory Elements                   */

+

+/*****************  Bit definition for FDCAN_TTRMC register  *********************/

+#define FDCAN_TTRMC_RID_Pos       (0U)

+#define FDCAN_TTRMC_RID_Msk       (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)        /*!< 0x1FFFFFFF */

+#define FDCAN_TTRMC_RID           FDCAN_TTRMC_RID_Msk                          /*!<Reference Identifier                      */

+#define FDCAN_TTRMC_XTD_Pos       (30U)

+#define FDCAN_TTRMC_XTD_Msk       (0x1UL << FDCAN_TTRMC_XTD_Pos)               /*!< 0x40000000 */

+#define FDCAN_TTRMC_XTD           FDCAN_TTRMC_XTD_Msk                          /*!< Extended Identifier                      */

+#define FDCAN_TTRMC_RMPS_Pos      (31U)

+#define FDCAN_TTRMC_RMPS_Msk      (0x1UL << FDCAN_TTRMC_RMPS_Pos)              /*!< 0x80000000 */

+#define FDCAN_TTRMC_RMPS          FDCAN_TTRMC_RMPS_Msk                         /*!<Reference Message Payload Select          */

+

+/*****************  Bit definition for FDCAN_TTOCF register  *********************/

+#define FDCAN_TTOCF_OM_Pos        (0U)

+#define FDCAN_TTOCF_OM_Msk        (0x3UL << FDCAN_TTOCF_OM_Pos)                /*!< 0x00000003 */

+#define FDCAN_TTOCF_OM            FDCAN_TTOCF_OM_Msk                           /*!<Operation Mode                            */

+#define FDCAN_TTOCF_GEN_Pos       (3U)

+#define FDCAN_TTOCF_GEN_Msk       (0x1UL << FDCAN_TTOCF_GEN_Pos)               /*!< 0x00000008 */

+#define FDCAN_TTOCF_GEN           FDCAN_TTOCF_GEN_Msk                          /*!<Gap Enable                                */

+#define FDCAN_TTOCF_TM_Pos        (4U)

+#define FDCAN_TTOCF_TM_Msk        (0x1UL << FDCAN_TTOCF_TM_Pos)                /*!< 0x00000010 */

+#define FDCAN_TTOCF_TM            FDCAN_TTOCF_TM_Msk                           /*!<Time Master                               */

+#define FDCAN_TTOCF_LDSDL_Pos     (5U)

+#define FDCAN_TTOCF_LDSDL_Msk     (0x7UL << FDCAN_TTOCF_LDSDL_Pos)             /*!< 0x000000E0 */

+#define FDCAN_TTOCF_LDSDL         FDCAN_TTOCF_LDSDL_Msk                        /*!<LD of Synchronization Deviation Limit     */

+#define FDCAN_TTOCF_IRTO_Pos      (8U)

+#define FDCAN_TTOCF_IRTO_Msk      (0x7FUL << FDCAN_TTOCF_IRTO_Pos)             /*!< 0x00007F00 */

+#define FDCAN_TTOCF_IRTO          FDCAN_TTOCF_IRTO_Msk                         /*!<Initial Reference Trigger Offset          */

+#define FDCAN_TTOCF_EECS_Pos      (15U)

+#define FDCAN_TTOCF_EECS_Msk      (0x1UL << FDCAN_TTOCF_EECS_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTOCF_EECS          FDCAN_TTOCF_EECS_Msk                         /*!<Enable External Clock Synchronization     */

+#define FDCAN_TTOCF_AWL_Pos       (16U)

+#define FDCAN_TTOCF_AWL_Msk       (0xFFUL << FDCAN_TTOCF_AWL_Pos)              /*!< 0x00FF0000 */

+#define FDCAN_TTOCF_AWL           FDCAN_TTOCF_AWL_Msk                          /*!<Application Watchdog Limit                */

+#define FDCAN_TTOCF_EGTF_Pos      (24U)

+#define FDCAN_TTOCF_EGTF_Msk      (0x1UL << FDCAN_TTOCF_EGTF_Pos)              /*!< 0x01000000 */

+#define FDCAN_TTOCF_EGTF          FDCAN_TTOCF_EGTF_Msk                         /*!<Enable Global Time Filtering              */

+#define FDCAN_TTOCF_ECC_Pos       (25U)

+#define FDCAN_TTOCF_ECC_Msk       (0x1UL << FDCAN_TTOCF_ECC_Pos)               /*!< 0x02000000 */

+#define FDCAN_TTOCF_ECC           FDCAN_TTOCF_ECC_Msk                          /*!<Enable Clock Calibration                  */

+#define FDCAN_TTOCF_EVTP_Pos      (26U)

+#define FDCAN_TTOCF_EVTP_Msk      (0x1UL << FDCAN_TTOCF_EVTP_Pos)              /*!< 0x04000000 */

+#define FDCAN_TTOCF_EVTP          FDCAN_TTOCF_EVTP_Msk                         /*!<Event Trigger Polarity                    */

+

+/*****************  Bit definition for FDCAN_TTMLM register  *********************/

+#define FDCAN_TTMLM_CCM_Pos       (0U)

+#define FDCAN_TTMLM_CCM_Msk       (0x3FUL << FDCAN_TTMLM_CCM_Pos)              /*!< 0x0000003F */

+#define FDCAN_TTMLM_CCM           FDCAN_TTMLM_CCM_Msk                          /*!<Cycle Count Max                           */

+#define FDCAN_TTMLM_CSS_Pos       (6U)

+#define FDCAN_TTMLM_CSS_Msk       (0x3UL << FDCAN_TTMLM_CSS_Pos)               /*!< 0x000000C0 */

+#define FDCAN_TTMLM_CSS           FDCAN_TTMLM_CSS_Msk                          /*!<Cycle Start Synchronization               */

+#define FDCAN_TTMLM_TXEW_Pos      (8U)

+#define FDCAN_TTMLM_TXEW_Msk      (0xFUL << FDCAN_TTMLM_TXEW_Pos)              /*!< 0x00000F00 */

+#define FDCAN_TTMLM_TXEW          FDCAN_TTMLM_TXEW_Msk                         /*!<Tx Enable Window                          */

+#define FDCAN_TTMLM_ENTT_Pos      (16U)

+#define FDCAN_TTMLM_ENTT_Msk      (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)            /*!< 0x0FFF0000 */

+#define FDCAN_TTMLM_ENTT          FDCAN_TTMLM_ENTT_Msk                         /*!<Expected Number of Tx Triggers            */

+

+/*****************  Bit definition for FDCAN_TURCF register  *********************/

+#define FDCAN_TURCF_NCL_Pos       (0U)

+#define FDCAN_TURCF_NCL_Msk       (0xFFFFUL << FDCAN_TURCF_NCL_Pos)            /*!< 0x0000FFFF */

+#define FDCAN_TURCF_NCL           FDCAN_TURCF_NCL_Msk                          /*!<Numerator Configuration Low               */

+#define FDCAN_TURCF_DC_Pos        (16U)

+#define FDCAN_TURCF_DC_Msk        (0x3FFFUL << FDCAN_TURCF_DC_Pos)             /*!< 0x3FFF0000 */

+#define FDCAN_TURCF_DC            FDCAN_TURCF_DC_Msk                           /*!<Denominator Configuration                 */

+#define FDCAN_TURCF_ELT_Pos       (31U)

+#define FDCAN_TURCF_ELT_Msk       (0x1UL << FDCAN_TURCF_ELT_Pos)               /*!< 0x80000000 */

+#define FDCAN_TURCF_ELT           FDCAN_TURCF_ELT_Msk                          /*!<Enable Local Time                         */

+

+/*****************  Bit definition for FDCAN_TTOCN register  ********************/

+#define FDCAN_TTOCN_SGT_Pos       (0U)

+#define FDCAN_TTOCN_SGT_Msk       (0x1UL << FDCAN_TTOCN_SGT_Pos)               /*!< 0x00000001 */

+#define FDCAN_TTOCN_SGT           FDCAN_TTOCN_SGT_Msk                          /*!<Set Global time                           */

+#define FDCAN_TTOCN_ECS_Pos       (1U)

+#define FDCAN_TTOCN_ECS_Msk       (0x1UL << FDCAN_TTOCN_ECS_Pos)               /*!< 0x00000002 */

+#define FDCAN_TTOCN_ECS           FDCAN_TTOCN_ECS_Msk                          /*!<External Clock Synchronization            */

+#define FDCAN_TTOCN_SWP_Pos       (2U)

+#define FDCAN_TTOCN_SWP_Msk       (0x1UL << FDCAN_TTOCN_SWP_Pos)               /*!< 0x00000004 */

+#define FDCAN_TTOCN_SWP           FDCAN_TTOCN_SWP_Msk                          /*!<Stop Watch Polarity                       */

+#define FDCAN_TTOCN_SWS_Pos       (3U)

+#define FDCAN_TTOCN_SWS_Msk       (0x3UL << FDCAN_TTOCN_SWS_Pos)               /*!< 0x00000018 */

+#define FDCAN_TTOCN_SWS           FDCAN_TTOCN_SWS_Msk                          /*!<Stop Watch Source                         */

+#define FDCAN_TTOCN_RTIE_Pos      (5U)

+#define FDCAN_TTOCN_RTIE_Msk      (0x1UL << FDCAN_TTOCN_RTIE_Pos)              /*!< 0x00000020 */

+#define FDCAN_TTOCN_RTIE          FDCAN_TTOCN_RTIE_Msk                         /*!<Register Time Mark Interrupt Pulse Enable */

+#define FDCAN_TTOCN_TMC_Pos       (6U)

+#define FDCAN_TTOCN_TMC_Msk       (0x3UL << FDCAN_TTOCN_TMC_Pos)               /*!< 0x000000C0 */

+#define FDCAN_TTOCN_TMC           FDCAN_TTOCN_TMC_Msk                          /*!<Register Time Mark Compare                */

+#define FDCAN_TTOCN_TTIE_Pos      (8U)

+#define FDCAN_TTOCN_TTIE_Msk      (0x1UL << FDCAN_TTOCN_TTIE_Pos)              /*!< 0x00000100 */

+#define FDCAN_TTOCN_TTIE          FDCAN_TTOCN_TTIE_Msk                         /*!<Trigger Time Mark Interrupt Pulse Enable  */

+#define FDCAN_TTOCN_GCS_Pos       (9U)

+#define FDCAN_TTOCN_GCS_Msk       (0x1UL << FDCAN_TTOCN_GCS_Pos)               /*!< 0x00000200 */

+#define FDCAN_TTOCN_GCS           FDCAN_TTOCN_GCS_Msk                          /*!<Gap Control Select                        */

+#define FDCAN_TTOCN_FGP_Pos       (10U)

+#define FDCAN_TTOCN_FGP_Msk       (0x1UL << FDCAN_TTOCN_FGP_Pos)               /*!< 0x00000400 */

+#define FDCAN_TTOCN_FGP           FDCAN_TTOCN_FGP_Msk                          /*!<Finish Gap                                */

+#define FDCAN_TTOCN_TMG_Pos       (11U)

+#define FDCAN_TTOCN_TMG_Msk       (0x1UL << FDCAN_TTOCN_TMG_Pos)               /*!< 0x00000800 */

+#define FDCAN_TTOCN_TMG           FDCAN_TTOCN_TMG_Msk                          /*!<Time Mark Gap                             */

+#define FDCAN_TTOCN_NIG_Pos       (12U)

+#define FDCAN_TTOCN_NIG_Msk       (0x1UL << FDCAN_TTOCN_NIG_Pos)               /*!< 0x00001000 */

+#define FDCAN_TTOCN_NIG           FDCAN_TTOCN_NIG_Msk                          /*!<Next is Gap                               */

+#define FDCAN_TTOCN_ESCN_Pos      (13U)

+#define FDCAN_TTOCN_ESCN_Msk      (0x1UL << FDCAN_TTOCN_ESCN_Pos)              /*!< 0x00002000 */

+#define FDCAN_TTOCN_ESCN          FDCAN_TTOCN_ESCN_Msk                         /*!<External Synchronization Control          */

+#define FDCAN_TTOCN_LCKC_Pos      (15U)

+#define FDCAN_TTOCN_LCKC_Msk      (0x1UL << FDCAN_TTOCN_LCKC_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTOCN_LCKC          FDCAN_TTOCN_LCKC_Msk                         /*!<TT Operation Control Register Locked      */

+

+/*****************  Bit definition for FDCAN_TTGTP register  ********************/

+#define FDCAN_TTGTP_TP_Pos        (0U)

+#define FDCAN_TTGTP_TP_Msk        (0xFFFFUL << FDCAN_TTGTP_TP_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTGTP_TP            FDCAN_TTGTP_TP_Msk                           /*!<Time Preset                               */

+#define FDCAN_TTGTP_CTP_Pos       (16U)

+#define FDCAN_TTGTP_CTP_Msk       (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)            /*!< 0xFFFF0000 */

+#define FDCAN_TTGTP_CTP           FDCAN_TTGTP_CTP_Msk                          /*!<Cycle Time Target Phase                   */

+

+/*****************  Bit definition for FDCAN_TTTMK register  ********************/

+#define FDCAN_TTTMK_TM_Pos        (0U)

+#define FDCAN_TTTMK_TM_Msk        (0xFFFFUL << FDCAN_TTTMK_TM_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTTMK_TM            FDCAN_TTTMK_TM_Msk                           /*!<Time Mark                                 */

+#define FDCAN_TTTMK_TICC_Pos      (16U)

+#define FDCAN_TTTMK_TICC_Msk      (0x7FUL << FDCAN_TTTMK_TICC_Pos)             /*!< 0x007F0000 */

+#define FDCAN_TTTMK_TICC          FDCAN_TTTMK_TICC_Msk                         /*!<Time Mark Cycle Code                      */

+#define FDCAN_TTTMK_LCKM_Pos      (31U)

+#define FDCAN_TTTMK_LCKM_Msk      (0x1UL << FDCAN_TTTMK_LCKM_Pos)              /*!< 0x80000000 */

+#define FDCAN_TTTMK_LCKM          FDCAN_TTTMK_LCKM_Msk                         /*!<TT Time Mark Register Locked              */

+

+/*****************  Bit definition for FDCAN_TTIR register  ********************/

+#define FDCAN_TTIR_SBC_Pos        (0U)

+#define FDCAN_TTIR_SBC_Msk        (0x1UL << FDCAN_TTIR_SBC_Pos)                /*!< 0x00000001 */

+#define FDCAN_TTIR_SBC            FDCAN_TTIR_SBC_Msk                           /*!<Start of Basic Cycle                      */

+#define FDCAN_TTIR_SMC_Pos        (1U)

+#define FDCAN_TTIR_SMC_Msk        (0x1UL << FDCAN_TTIR_SMC_Pos)                /*!< 0x00000002 */

+#define FDCAN_TTIR_SMC            FDCAN_TTIR_SMC_Msk                           /*!<Start of Matrix Cycle                     */

+#define FDCAN_TTIR_CSM_Pos        (2U)

+#define FDCAN_TTIR_CSM_Msk        (0x1UL << FDCAN_TTIR_CSM_Pos)                /*!< 0x00000004 */

+#define FDCAN_TTIR_CSM            FDCAN_TTIR_CSM_Msk                           /*!<Change of Synchronization Mode            */

+#define FDCAN_TTIR_SOG_Pos        (3U)

+#define FDCAN_TTIR_SOG_Msk        (0x1UL << FDCAN_TTIR_SOG_Pos)                /*!< 0x00000008 */

+#define FDCAN_TTIR_SOG            FDCAN_TTIR_SOG_Msk                           /*!<Start of Gap                              */

+#define FDCAN_TTIR_RTMI_Pos       (4U)

+#define FDCAN_TTIR_RTMI_Msk       (0x1UL << FDCAN_TTIR_RTMI_Pos)               /*!< 0x00000010 */

+#define FDCAN_TTIR_RTMI           FDCAN_TTIR_RTMI_Msk                          /*!<Register Time Mark Interrupt              */

+#define FDCAN_TTIR_TTMI_Pos       (5U)

+#define FDCAN_TTIR_TTMI_Msk       (0x1UL << FDCAN_TTIR_TTMI_Pos)               /*!< 0x00000020 */

+#define FDCAN_TTIR_TTMI           FDCAN_TTIR_TTMI_Msk                          /*!<Trigger Time Mark Event Internal          */

+#define FDCAN_TTIR_SWE_Pos        (6U)

+#define FDCAN_TTIR_SWE_Msk        (0x1UL << FDCAN_TTIR_SWE_Pos)                /*!< 0x00000040 */

+#define FDCAN_TTIR_SWE            FDCAN_TTIR_SWE_Msk                           /*!<Stop Watch Event                          */

+#define FDCAN_TTIR_GTW_Pos        (7U)

+#define FDCAN_TTIR_GTW_Msk        (0x1UL << FDCAN_TTIR_GTW_Pos)                /*!< 0x00000080 */

+#define FDCAN_TTIR_GTW            FDCAN_TTIR_GTW_Msk                           /*!<Global Time Wrap                          */

+#define FDCAN_TTIR_GTD_Pos        (8U)

+#define FDCAN_TTIR_GTD_Msk        (0x1UL << FDCAN_TTIR_GTD_Pos)                /*!< 0x00000100 */

+#define FDCAN_TTIR_GTD            FDCAN_TTIR_GTD_Msk                           /*!<Global Time Discontinuity                 */

+#define FDCAN_TTIR_GTE_Pos        (9U)

+#define FDCAN_TTIR_GTE_Msk        (0x1UL << FDCAN_TTIR_GTE_Pos)                /*!< 0x00000200 */

+#define FDCAN_TTIR_GTE            FDCAN_TTIR_GTE_Msk                           /*!<Global Time Error                         */

+#define FDCAN_TTIR_TXU_Pos        (10U)

+#define FDCAN_TTIR_TXU_Msk        (0x1UL << FDCAN_TTIR_TXU_Pos)                /*!< 0x00000400 */

+#define FDCAN_TTIR_TXU            FDCAN_TTIR_TXU_Msk                           /*!<Tx Count Underflow                        */

+#define FDCAN_TTIR_TXO_Pos        (11U)

+#define FDCAN_TTIR_TXO_Msk        (0x1UL << FDCAN_TTIR_TXO_Pos)                /*!< 0x00000800 */

+#define FDCAN_TTIR_TXO            FDCAN_TTIR_TXO_Msk                           /*!<Tx Count Overflow                         */

+#define FDCAN_TTIR_SE1_Pos        (12U)

+#define FDCAN_TTIR_SE1_Msk        (0x1UL << FDCAN_TTIR_SE1_Pos)                /*!< 0x00001000 */

+#define FDCAN_TTIR_SE1            FDCAN_TTIR_SE1_Msk                           /*!<Scheduling Error 1                        */

+#define FDCAN_TTIR_SE2_Pos        (13U)

+#define FDCAN_TTIR_SE2_Msk        (0x1UL << FDCAN_TTIR_SE2_Pos)                /*!< 0x00002000 */

+#define FDCAN_TTIR_SE2            FDCAN_TTIR_SE2_Msk                           /*!<Scheduling Error 2                        */

+#define FDCAN_TTIR_ELC_Pos        (14U)

+#define FDCAN_TTIR_ELC_Msk        (0x1UL << FDCAN_TTIR_ELC_Pos)                /*!< 0x00004000 */

+#define FDCAN_TTIR_ELC            FDCAN_TTIR_ELC_Msk                           /*!<Error Level Changed                       */

+#define FDCAN_TTIR_IWT_Pos        (15U)

+#define FDCAN_TTIR_IWT_Msk        (0x1UL << FDCAN_TTIR_IWT_Pos)                /*!< 0x00008000 */

+#define FDCAN_TTIR_IWT            FDCAN_TTIR_IWT_Msk                           /*!<Initialization Watch Trigger              */

+#define FDCAN_TTIR_WT_Pos         (16U)

+#define FDCAN_TTIR_WT_Msk         (0x1UL << FDCAN_TTIR_WT_Pos)                 /*!< 0x00010000 */

+#define FDCAN_TTIR_WT             FDCAN_TTIR_WT_Msk                            /*!<Watch Trigger                             */

+#define FDCAN_TTIR_AW_Pos         (17U)

+#define FDCAN_TTIR_AW_Msk         (0x1UL << FDCAN_TTIR_AW_Pos)                 /*!< 0x00020000 */

+#define FDCAN_TTIR_AW             FDCAN_TTIR_AW_Msk                            /*!<Application Watchdog                      */

+#define FDCAN_TTIR_CER_Pos        (18U)

+#define FDCAN_TTIR_CER_Msk        (0x1UL << FDCAN_TTIR_CER_Pos)                /*!< 0x00040000 */

+#define FDCAN_TTIR_CER            FDCAN_TTIR_CER_Msk                           /*!<Configuration Error                       */

+

+/*****************  Bit definition for FDCAN_TTIE register  ********************/

+#define FDCAN_TTIE_SBCE_Pos       (0U)

+#define FDCAN_TTIE_SBCE_Msk       (0x1UL << FDCAN_TTIE_SBCE_Pos)               /*!< 0x00000001 */

+#define FDCAN_TTIE_SBCE           FDCAN_TTIE_SBCE_Msk                          /*!<Start of Basic Cycle Interrupt Enable             */

+#define FDCAN_TTIE_SMCE_Pos       (1U)

+#define FDCAN_TTIE_SMCE_Msk       (0x1UL << FDCAN_TTIE_SMCE_Pos)               /*!< 0x00000002 */

+#define FDCAN_TTIE_SMCE           FDCAN_TTIE_SMCE_Msk                          /*!<Start of Matrix Cycle Interrupt Enable            */

+#define FDCAN_TTIE_CSME_Pos       (2U)

+#define FDCAN_TTIE_CSME_Msk       (0x1UL << FDCAN_TTIE_CSME_Pos)               /*!< 0x00000004 */

+#define FDCAN_TTIE_CSME           FDCAN_TTIE_CSME_Msk                          /*!<Change of Synchronization Mode Interrupt Enable   */

+#define FDCAN_TTIE_SOGE_Pos       (3U)

+#define FDCAN_TTIE_SOGE_Msk       (0x1UL << FDCAN_TTIE_SOGE_Pos)               /*!< 0x00000008 */

+#define FDCAN_TTIE_SOGE           FDCAN_TTIE_SOGE_Msk                          /*!<Start of Gap Interrupt Enable                     */

+#define FDCAN_TTIE_RTMIE_Pos      (4U)

+#define FDCAN_TTIE_RTMIE_Msk      (0x1UL << FDCAN_TTIE_RTMIE_Pos)              /*!< 0x00000010 */

+#define FDCAN_TTIE_RTMIE          FDCAN_TTIE_RTMIE_Msk                         /*!<Register Time Mark Interrupt Interrupt Enable     */

+#define FDCAN_TTIE_TTMIE_Pos      (5U)

+#define FDCAN_TTIE_TTMIE_Msk      (0x1UL << FDCAN_TTIE_TTMIE_Pos)              /*!< 0x00000020 */

+#define FDCAN_TTIE_TTMIE          FDCAN_TTIE_TTMIE_Msk                         /*!<Trigger Time Mark Event Internal Interrupt Enable */

+#define FDCAN_TTIE_SWEE_Pos       (6U)

+#define FDCAN_TTIE_SWEE_Msk       (0x1UL << FDCAN_TTIE_SWEE_Pos)               /*!< 0x00000040 */

+#define FDCAN_TTIE_SWEE           FDCAN_TTIE_SWEE_Msk                          /*!<Stop Watch Event Interrupt Enable                 */

+#define FDCAN_TTIE_GTWE_Pos       (7U)

+#define FDCAN_TTIE_GTWE_Msk       (0x1UL << FDCAN_TTIE_GTWE_Pos)               /*!< 0x00000080 */

+#define FDCAN_TTIE_GTWE           FDCAN_TTIE_GTWE_Msk                          /*!<Global Time Wrap Interrupt Enable                 */

+#define FDCAN_TTIE_GTDE_Pos       (8U)

+#define FDCAN_TTIE_GTDE_Msk       (0x1UL << FDCAN_TTIE_GTDE_Pos)               /*!< 0x00000100 */

+#define FDCAN_TTIE_GTDE           FDCAN_TTIE_GTDE_Msk                          /*!<Global Time Discontinuity Interrupt Enable        */

+#define FDCAN_TTIE_GTEE_Pos       (9U)

+#define FDCAN_TTIE_GTEE_Msk       (0x1UL << FDCAN_TTIE_GTEE_Pos)               /*!< 0x00000200 */

+#define FDCAN_TTIE_GTEE           FDCAN_TTIE_GTEE_Msk                          /*!<Global Time Error Interrupt Enable                */

+#define FDCAN_TTIE_TXUE_Pos       (10U)

+#define FDCAN_TTIE_TXUE_Msk       (0x1UL << FDCAN_TTIE_TXUE_Pos)               /*!< 0x00000400 */

+#define FDCAN_TTIE_TXUE           FDCAN_TTIE_TXUE_Msk                          /*!<Tx Count Underflow Interrupt Enable               */

+#define FDCAN_TTIE_TXOE_Pos       (11U)

+#define FDCAN_TTIE_TXOE_Msk       (0x1UL << FDCAN_TTIE_TXOE_Pos)               /*!< 0x00000800 */

+#define FDCAN_TTIE_TXOE           FDCAN_TTIE_TXOE_Msk                          /*!<Tx Count Overflow Interrupt Enable                */

+#define FDCAN_TTIE_SE1E_Pos       (12U)

+#define FDCAN_TTIE_SE1E_Msk       (0x1UL << FDCAN_TTIE_SE1E_Pos)               /*!< 0x00001000 */

+#define FDCAN_TTIE_SE1E           FDCAN_TTIE_SE1E_Msk                          /*!<Scheduling Error 1 Interrupt Enable               */

+#define FDCAN_TTIE_SE2E_Pos       (13U)

+#define FDCAN_TTIE_SE2E_Msk       (0x1UL << FDCAN_TTIE_SE2E_Pos)               /*!< 0x00002000 */

+#define FDCAN_TTIE_SE2E           FDCAN_TTIE_SE2E_Msk                          /*!<Scheduling Error 2 Interrupt Enable               */

+#define FDCAN_TTIE_ELCE_Pos       (14U)

+#define FDCAN_TTIE_ELCE_Msk       (0x1UL << FDCAN_TTIE_ELCE_Pos)               /*!< 0x00004000 */

+#define FDCAN_TTIE_ELCE           FDCAN_TTIE_ELCE_Msk                          /*!<Error Level Changed Interrupt Enable              */

+#define FDCAN_TTIE_IWTE_Pos       (15U)

+#define FDCAN_TTIE_IWTE_Msk       (0x1UL << FDCAN_TTIE_IWTE_Pos)               /*!< 0x00008000 */

+#define FDCAN_TTIE_IWTE           FDCAN_TTIE_IWTE_Msk                          /*!<Initialization Watch Trigger Interrupt Enable     */

+#define FDCAN_TTIE_WTE_Pos        (16U)

+#define FDCAN_TTIE_WTE_Msk        (0x1UL << FDCAN_TTIE_WTE_Pos)                /*!< 0x00010000 */

+#define FDCAN_TTIE_WTE            FDCAN_TTIE_WTE_Msk                           /*!<Watch Trigger Interrupt Enable                    */

+#define FDCAN_TTIE_AWE_Pos        (17U)

+#define FDCAN_TTIE_AWE_Msk        (0x1UL << FDCAN_TTIE_AWE_Pos)                /*!< 0x00020000 */

+#define FDCAN_TTIE_AWE            FDCAN_TTIE_AWE_Msk                           /*!<Application Watchdog Interrupt Enable             */

+#define FDCAN_TTIE_CERE_Pos       (18U)

+#define FDCAN_TTIE_CERE_Msk       (0x1UL << FDCAN_TTIE_CERE_Pos)               /*!< 0x00040000 */

+#define FDCAN_TTIE_CERE           FDCAN_TTIE_CERE_Msk                          /*!<Configuration Error Interrupt Enable              */

+

+/*****************  Bit definition for FDCAN_TTILS register  ********************/

+#define FDCAN_TTILS_SBCS_Pos      (0U)

+#define FDCAN_TTILS_SBCS_Msk      (0x1UL << FDCAN_TTILS_SBCS_Pos)              /*!< 0x00000001 */

+#define FDCAN_TTILS_SBCS          FDCAN_TTILS_SBCS_Msk                         /*!<Start of Basic Cycle Interrupt Line               */

+#define FDCAN_TTILS_SMCS_Pos      (1U)

+#define FDCAN_TTILS_SMCS_Msk      (0x1UL << FDCAN_TTILS_SMCS_Pos)              /*!< 0x00000002 */

+#define FDCAN_TTILS_SMCS          FDCAN_TTILS_SMCS_Msk                         /*!<Start of Matrix Cycle Interrupt Line              */

+#define FDCAN_TTILS_CSMS_Pos      (2U)

+#define FDCAN_TTILS_CSMS_Msk      (0x1UL << FDCAN_TTILS_CSMS_Pos)              /*!< 0x00000004 */

+#define FDCAN_TTILS_CSMS          FDCAN_TTILS_CSMS_Msk                         /*!<Change of Synchronization Mode Interrupt Line     */

+#define FDCAN_TTILS_SOGS_Pos      (3U)

+#define FDCAN_TTILS_SOGS_Msk      (0x1UL << FDCAN_TTILS_SOGS_Pos)              /*!< 0x00000008 */

+#define FDCAN_TTILS_SOGS          FDCAN_TTILS_SOGS_Msk                         /*!<Start of Gap Interrupt Line                       */

+#define FDCAN_TTILS_RTMIS_Pos     (4U)

+#define FDCAN_TTILS_RTMIS_Msk     (0x1UL << FDCAN_TTILS_RTMIS_Pos)             /*!< 0x00000010 */

+#define FDCAN_TTILS_RTMIS         FDCAN_TTILS_RTMIS_Msk                        /*!<Register Time Mark Interrupt Interrupt Line       */

+#define FDCAN_TTILS_TTMIS_Pos     (5U)

+#define FDCAN_TTILS_TTMIS_Msk     (0x1UL << FDCAN_TTILS_TTMIS_Pos)             /*!< 0x00000020 */

+#define FDCAN_TTILS_TTMIS         FDCAN_TTILS_TTMIS_Msk                        /*!<Trigger Time Mark Event Internal Interrupt Line   */

+#define FDCAN_TTILS_SWES_Pos      (6U)

+#define FDCAN_TTILS_SWES_Msk      (0x1UL << FDCAN_TTILS_SWES_Pos)              /*!< 0x00000040 */

+#define FDCAN_TTILS_SWES          FDCAN_TTILS_SWES_Msk                         /*!<Stop Watch Event Interrupt Line                   */

+#define FDCAN_TTILS_GTWS_Pos      (7U)

+#define FDCAN_TTILS_GTWS_Msk      (0x1UL << FDCAN_TTILS_GTWS_Pos)              /*!< 0x00000080 */

+#define FDCAN_TTILS_GTWS          FDCAN_TTILS_GTWS_Msk                         /*!<Global Time Wrap Interrupt Line                   */

+#define FDCAN_TTILS_GTDS_Pos      (8U)

+#define FDCAN_TTILS_GTDS_Msk      (0x1UL << FDCAN_TTILS_GTDS_Pos)              /*!< 0x00000100 */

+#define FDCAN_TTILS_GTDS          FDCAN_TTILS_GTDS_Msk                         /*!<Global Time Discontinuity Interrupt Line          */

+#define FDCAN_TTILS_GTES_Pos      (9U)

+#define FDCAN_TTILS_GTES_Msk      (0x1UL << FDCAN_TTILS_GTES_Pos)              /*!< 0x00000200 */

+#define FDCAN_TTILS_GTES          FDCAN_TTILS_GTES_Msk                         /*!<Global Time Error Interrupt Line                  */

+#define FDCAN_TTILS_TXUS_Pos      (10U)

+#define FDCAN_TTILS_TXUS_Msk      (0x1UL << FDCAN_TTILS_TXUS_Pos)              /*!< 0x00000400 */

+#define FDCAN_TTILS_TXUS          FDCAN_TTILS_TXUS_Msk                         /*!<Tx Count Underflow Interrupt Line                 */

+#define FDCAN_TTILS_TXOS_Pos      (11U)

+#define FDCAN_TTILS_TXOS_Msk      (0x1UL << FDCAN_TTILS_TXOS_Pos)              /*!< 0x00000800 */

+#define FDCAN_TTILS_TXOS          FDCAN_TTILS_TXOS_Msk                         /*!<Tx Count Overflow Interrupt Line                  */

+#define FDCAN_TTILS_SE1S_Pos      (12U)

+#define FDCAN_TTILS_SE1S_Msk      (0x1UL << FDCAN_TTILS_SE1S_Pos)              /*!< 0x00001000 */

+#define FDCAN_TTILS_SE1S          FDCAN_TTILS_SE1S_Msk                         /*!<Scheduling Error 1 Interrupt Line                 */

+#define FDCAN_TTILS_SE2S_Pos      (13U)

+#define FDCAN_TTILS_SE2S_Msk      (0x1UL << FDCAN_TTILS_SE2S_Pos)              /*!< 0x00002000 */

+#define FDCAN_TTILS_SE2S          FDCAN_TTILS_SE2S_Msk                         /*!<Scheduling Error 2 Interrupt Line                 */

+#define FDCAN_TTILS_ELCS_Pos      (14U)

+#define FDCAN_TTILS_ELCS_Msk      (0x1UL << FDCAN_TTILS_ELCS_Pos)              /*!< 0x00004000 */

+#define FDCAN_TTILS_ELCS          FDCAN_TTILS_ELCS_Msk                         /*!<Error Level Changed Interrupt Line                */

+#define FDCAN_TTILS_IWTS_Pos      (15U)

+#define FDCAN_TTILS_IWTS_Msk      (0x1UL << FDCAN_TTILS_IWTS_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTILS_IWTS          FDCAN_TTILS_IWTS_Msk                         /*!<Initialization Watch Trigger Interrupt Line       */

+#define FDCAN_TTILS_WTS_Pos       (16U)

+#define FDCAN_TTILS_WTS_Msk       (0x1UL << FDCAN_TTILS_WTS_Pos)               /*!< 0x00010000 */

+#define FDCAN_TTILS_WTS           FDCAN_TTILS_WTS_Msk                          /*!<Watch Trigger Interrupt Line                      */

+#define FDCAN_TTILS_AWS_Pos       (17U)

+#define FDCAN_TTILS_AWS_Msk       (0x1UL << FDCAN_TTILS_AWS_Pos)               /*!< 0x00020000 */

+#define FDCAN_TTILS_AWS           FDCAN_TTILS_AWS_Msk                          /*!<Application Watchdog Interrupt Line               */

+#define FDCAN_TTILS_CERS_Pos      (18U)

+#define FDCAN_TTILS_CERS_Msk      (0x1UL << FDCAN_TTILS_CERS_Pos)              /*!< 0x00040000 */

+#define FDCAN_TTILS_CERS          FDCAN_TTILS_CERS_Msk                         /*!<Configuration Error Interrupt Line                */

+

+/*****************  Bit definition for FDCAN_TTOST register  ********************/

+#define FDCAN_TTOST_EL_Pos        (0U)

+#define FDCAN_TTOST_EL_Msk        (0x3UL << FDCAN_TTOST_EL_Pos)                /*!< 0x00000003 */

+#define FDCAN_TTOST_EL            FDCAN_TTOST_EL_Msk                           /*!<Error Level                              */

+#define FDCAN_TTOST_MS_Pos        (2U)

+#define FDCAN_TTOST_MS_Msk        (0x3UL << FDCAN_TTOST_MS_Pos)                /*!< 0x0000000C */

+#define FDCAN_TTOST_MS            FDCAN_TTOST_MS_Msk                           /*!<Master State                             */

+#define FDCAN_TTOST_SYS_Pos       (4U)

+#define FDCAN_TTOST_SYS_Msk       (0x3UL << FDCAN_TTOST_SYS_Pos)               /*!< 0x00000030 */

+#define FDCAN_TTOST_SYS           FDCAN_TTOST_SYS_Msk                          /*!<Synchronization State                    */

+#define FDCAN_TTOST_QGTP_Pos      (6U)

+#define FDCAN_TTOST_QGTP_Msk      (0x1UL << FDCAN_TTOST_QGTP_Pos)              /*!< 0x00000040 */

+#define FDCAN_TTOST_QGTP          FDCAN_TTOST_QGTP_Msk                         /*!<Quality of Global Time Phase             */

+#define FDCAN_TTOST_QCS_Pos       (7U)

+#define FDCAN_TTOST_QCS_Msk       (0x1UL << FDCAN_TTOST_QCS_Pos)               /*!< 0x00000080 */

+#define FDCAN_TTOST_QCS           FDCAN_TTOST_QCS_Msk                          /*!<Quality of Clock Speed                   */

+#define FDCAN_TTOST_RTO_Pos       (8U)

+#define FDCAN_TTOST_RTO_Msk       (0xFFUL << FDCAN_TTOST_RTO_Pos)              /*!< 0x0000FF00 */

+#define FDCAN_TTOST_RTO           FDCAN_TTOST_RTO_Msk                          /*!<Reference Trigger Offset                 */

+#define FDCAN_TTOST_WGTD_Pos      (22U)

+#define FDCAN_TTOST_WGTD_Msk      (0x1UL << FDCAN_TTOST_WGTD_Pos)              /*!< 0x00400000 */

+#define FDCAN_TTOST_WGTD          FDCAN_TTOST_WGTD_Msk                         /*!<Wait for Global Time Discontinuity       */

+#define FDCAN_TTOST_GFI_Pos       (23U)

+#define FDCAN_TTOST_GFI_Msk       (0x1UL << FDCAN_TTOST_GFI_Pos)               /*!< 0x00800000 */

+#define FDCAN_TTOST_GFI           FDCAN_TTOST_GFI_Msk                          /*!<Gap Finished Indicator                   */

+#define FDCAN_TTOST_TMP_Pos       (24U)

+#define FDCAN_TTOST_TMP_Msk       (0x7UL << FDCAN_TTOST_TMP_Pos)               /*!< 0x07000000 */

+#define FDCAN_TTOST_TMP           FDCAN_TTOST_TMP_Msk                          /*!<Time Master Priority                     */

+#define FDCAN_TTOST_GSI_Pos       (27U)

+#define FDCAN_TTOST_GSI_Msk       (0x1UL << FDCAN_TTOST_GSI_Pos)               /*!< 0x08000000 */

+#define FDCAN_TTOST_GSI           FDCAN_TTOST_GSI_Msk                          /*!<Gap Started Indicator                    */

+#define FDCAN_TTOST_WFE_Pos       (28U)

+#define FDCAN_TTOST_WFE_Msk       (0x1UL << FDCAN_TTOST_WFE_Pos)               /*!< 0x10000000 */

+#define FDCAN_TTOST_WFE           FDCAN_TTOST_WFE_Msk                          /*!<Wait for Event                           */

+#define FDCAN_TTOST_AWE_Pos       (29U)

+#define FDCAN_TTOST_AWE_Msk       (0x1UL << FDCAN_TTOST_AWE_Pos)               /*!< 0x20000000 */

+#define FDCAN_TTOST_AWE           FDCAN_TTOST_AWE_Msk                          /*!<Application Watchdog Event               */

+#define FDCAN_TTOST_WECS_Pos      (30U)

+#define FDCAN_TTOST_WECS_Msk      (0x1UL << FDCAN_TTOST_WECS_Pos)              /*!< 0x40000000 */

+#define FDCAN_TTOST_WECS          FDCAN_TTOST_WECS_Msk                         /*!<Wait for External Clock Synchronization  */

+#define FDCAN_TTOST_SPL_Pos       (31U)

+#define FDCAN_TTOST_SPL_Msk       (0x1UL << FDCAN_TTOST_SPL_Pos)               /*!< 0x80000000 */

+#define FDCAN_TTOST_SPL           FDCAN_TTOST_SPL_Msk                          /*!<Schedule Phase Lock                      */

+

+/*****************  Bit definition for FDCAN_TURNA register  ********************/

+#define FDCAN_TURNA_NAV_Pos       (0U)

+#define FDCAN_TURNA_NAV_Msk       (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)           /*!< 0x0003FFFF */

+#define FDCAN_TURNA_NAV           FDCAN_TURNA_NAV_Msk                          /*!<Numerator Actual Value                   */

+

+/*****************  Bit definition for FDCAN_TTLGT register  ********************/

+#define FDCAN_TTLGT_LT_Pos        (0U)

+#define FDCAN_TTLGT_LT_Msk        (0xFFFFUL << FDCAN_TTLGT_LT_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTLGT_LT            FDCAN_TTLGT_LT_Msk                           /*!<Local Time                               */

+#define FDCAN_TTLGT_GT_Pos        (16U)

+#define FDCAN_TTLGT_GT_Msk        (0xFFFFUL << FDCAN_TTLGT_GT_Pos)             /*!< 0xFFFF0000 */

+#define FDCAN_TTLGT_GT            FDCAN_TTLGT_GT_Msk                           /*!<Global Time                              */

+

+/*****************  Bit definition for FDCAN_TTCTC register  ********************/

+#define FDCAN_TTCTC_CT_Pos        (0U)

+#define FDCAN_TTCTC_CT_Msk        (0xFFFFUL << FDCAN_TTCTC_CT_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTCTC_CT            FDCAN_TTCTC_CT_Msk                           /*!<Cycle Time                               */

+#define FDCAN_TTCTC_CC_Pos        (16U)

+#define FDCAN_TTCTC_CC_Msk        (0x3FUL << FDCAN_TTCTC_CC_Pos)               /*!< 0x003F0000 */

+#define FDCAN_TTCTC_CC            FDCAN_TTCTC_CC_Msk                           /*!<Cycle Count                              */

+

+/*****************  Bit definition for FDCAN_TTCPT register  ********************/

+#define FDCAN_TTCPT_CCV_Pos       (0U)

+#define FDCAN_TTCPT_CCV_Msk       (0x3FUL << FDCAN_TTCPT_CCV_Pos)              /*!< 0x0000003F */

+#define FDCAN_TTCPT_CCV           FDCAN_TTCPT_CCV_Msk                          /*!<Cycle Count Value                        */

+#define FDCAN_TTCPT_SWV_Pos       (16U)

+#define FDCAN_TTCPT_SWV_Msk       (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)            /*!< 0xFFFF0000 */

+#define FDCAN_TTCPT_SWV           FDCAN_TTCPT_SWV_Msk                          /*!<Stop Watch Value                         */

+

+/*****************  Bit definition for FDCAN_TTCSM register  ********************/

+#define FDCAN_TTCSM_CSM_Pos       (0U)

+#define FDCAN_TTCSM_CSM_Msk       (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)            /*!< 0x0000FFFF */

+#define FDCAN_TTCSM_CSM           FDCAN_TTCSM_CSM_Msk                          /*!<Cycle Sync Mark                          */

+

+/*****************  Bit definition for FDCAN_TTTS register  *********************/

+#define FDCAN_TTTS_SWTSEL_Pos     (0U)

+#define FDCAN_TTTS_SWTSEL_Msk     (0x3UL << FDCAN_TTTS_SWTSEL_Pos)             /*!< 0x00000003 */

+#define FDCAN_TTTS_SWTSEL         FDCAN_TTTS_SWTSEL_Msk                        /*!<Stop watch trigger input selection       */

+#define FDCAN_TTTS_EVTSEL_Pos     (4U)

+#define FDCAN_TTTS_EVTSEL_Msk     (0x3UL << FDCAN_TTTS_EVTSEL_Pos)             /*!< 0x00000030 */

+#define FDCAN_TTTS_EVTSEL         FDCAN_TTTS_EVTSEL_Msk                        /*!<Event trigger input selection            */

+

+/********************************************************************************/

+/*                                                                              */

+/*                      FDCANCCU (Clock Calibration unit)                       */

+/*                                                                              */

+/********************************************************************************/

+

+/*****************  Bit definition for FDCANCCU_CREL register  ******************/

+#define FDCANCCU_CREL_DAY_Pos        (0U)

+#define FDCANCCU_CREL_DAY_Msk        (0xFFUL << FDCANCCU_CREL_DAY_Pos)         /*!< 0x000000FF */

+#define FDCANCCU_CREL_DAY            FDCANCCU_CREL_DAY_Msk                     /*!<Timestamp Day                           */

+#define FDCANCCU_CREL_MON_Pos        (8U)

+#define FDCANCCU_CREL_MON_Msk        (0xFFUL << FDCANCCU_CREL_MON_Pos)         /*!< 0x0000FF00 */

+#define FDCANCCU_CREL_MON            FDCANCCU_CREL_MON_Msk                     /*!<Timestamp Month                         */

+#define FDCANCCU_CREL_YEAR_Pos       (16U)

+#define FDCANCCU_CREL_YEAR_Msk       (0xFUL << FDCANCCU_CREL_YEAR_Pos)         /*!< 0x000F0000 */

+#define FDCANCCU_CREL_YEAR           FDCANCCU_CREL_YEAR_Msk                    /*!<Timestamp Year                          */

+#define FDCANCCU_CREL_SUBSTEP_Pos    (20U)

+#define FDCANCCU_CREL_SUBSTEP_Msk    (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)      /*!< 0x00F00000 */

+#define FDCANCCU_CREL_SUBSTEP        FDCANCCU_CREL_SUBSTEP_Msk                 /*!<Sub-step of Core release                */

+#define FDCANCCU_CREL_STEP_Pos       (24U)

+#define FDCANCCU_CREL_STEP_Msk       (0xFUL << FDCANCCU_CREL_STEP_Pos)         /*!< 0x0F000000 */

+#define FDCANCCU_CREL_STEP           FDCANCCU_CREL_STEP_Msk                    /*!<Step of Core release                    */

+#define FDCANCCU_CREL_REL_Pos        (28U)

+#define FDCANCCU_CREL_REL_Msk        (0xFUL << FDCANCCU_CREL_REL_Pos)          /*!< 0xF0000000 */

+#define FDCANCCU_CREL_REL            FDCANCCU_CREL_REL_Msk                     /*!<Core release                            */

+

+/*****************  Bit definition for FDCANCCU_CCFG register  ******************/

+#define FDCANCCU_CCFG_TQBT_Pos       (0U)

+#define FDCANCCU_CCFG_TQBT_Msk       (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)        /*!< 0x0000001F */

+#define FDCANCCU_CCFG_TQBT           FDCANCCU_CCFG_TQBT_Msk                    /*!<Time Quanta per Bit Time                */

+#define FDCANCCU_CCFG_BCC_Pos        (6U)

+#define FDCANCCU_CCFG_BCC_Msk        (0x1UL << FDCANCCU_CCFG_BCC_Pos)          /*!< 0x00000040 */

+#define FDCANCCU_CCFG_BCC            FDCANCCU_CCFG_BCC_Msk                     /*!<Bypass Clock Calibration                */

+#define FDCANCCU_CCFG_CFL_Pos        (7U)

+#define FDCANCCU_CCFG_CFL_Msk        (0x1UL << FDCANCCU_CCFG_CFL_Pos)          /*!< 0x00000080 */

+#define FDCANCCU_CCFG_CFL            FDCANCCU_CCFG_CFL_Msk                     /*!<Calibration Field Length                */

+#define FDCANCCU_CCFG_OCPM_Pos       (8U)

+#define FDCANCCU_CCFG_OCPM_Msk       (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)        /*!< 0x0000FF00 */

+#define FDCANCCU_CCFG_OCPM           FDCANCCU_CCFG_OCPM_Msk                    /*!<Oscillator Clock Periods Minimum        */

+#define FDCANCCU_CCFG_CDIV_Pos       (16U)

+#define FDCANCCU_CCFG_CDIV_Msk       (0xFUL << FDCANCCU_CCFG_CDIV_Pos)         /*!< 0x000F0000 */

+#define FDCANCCU_CCFG_CDIV           FDCANCCU_CCFG_CDIV_Msk                    /*!<Clock Divider                           */

+#define FDCANCCU_CCFG_SWR_Pos        (31U)

+#define FDCANCCU_CCFG_SWR_Msk        (0x1UL << FDCANCCU_CCFG_SWR_Pos)          /*!< 0x80000000 */

+#define FDCANCCU_CCFG_SWR            FDCANCCU_CCFG_SWR_Msk                     /*!<Software Reset                          */

+

+/*****************  Bit definition for FDCANCCU_CSTAT register  *****************/

+#define FDCANCCU_CSTAT_OCPC_Pos      (0U)

+#define FDCANCCU_CSTAT_OCPC_Msk      (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)    /*!< 0x0003FFFF */

+#define FDCANCCU_CSTAT_OCPC          FDCANCCU_CSTAT_OCPC_Msk                   /*!<Oscillator Clock Period Counter        */

+#define FDCANCCU_CSTAT_TQC_Pos       (18U)

+#define FDCANCCU_CSTAT_TQC_Msk       (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)       /*!< 0x1FFC0000 */

+#define FDCANCCU_CSTAT_TQC           FDCANCCU_CSTAT_TQC_Msk                    /*!<Time Quanta Counter                    */

+#define FDCANCCU_CSTAT_CALS_Pos      (30U)

+#define FDCANCCU_CSTAT_CALS_Msk      (0x3UL << FDCANCCU_CSTAT_CALS_Pos)        /*!< 0xC0000000 */

+#define FDCANCCU_CSTAT_CALS          FDCANCCU_CSTAT_CALS_Msk                   /*!<Calibration State                      */

+

+/******************  Bit definition for FDCANCCU_CWD register  ******************/

+#define FDCANCCU_CWD_WDC_Pos         (0U)

+#define FDCANCCU_CWD_WDC_Msk         (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)        /*!< 0x0000FFFF */

+#define FDCANCCU_CWD_WDC             FDCANCCU_CWD_WDC_Msk                      /*!<Watchdog Configuration                 */

+#define FDCANCCU_CWD_WDV_Pos         (16U)

+#define FDCANCCU_CWD_WDV_Msk         (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)        /*!< 0xFFFF0000 */

+#define FDCANCCU_CWD_WDV             FDCANCCU_CWD_WDV_Msk                      /*!<Watchdog Value                         */

+

+/******************  Bit definition for FDCANCCU_IR register  *******************/

+#define FDCANCCU_IR_CWE_Pos          (0U)

+#define FDCANCCU_IR_CWE_Msk          (0x1UL << FDCANCCU_IR_CWE_Pos)            /*!< 0x00000001 */

+#define FDCANCCU_IR_CWE              FDCANCCU_IR_CWE_Msk                       /*!<Calibration Watchdog Event             */

+#define FDCANCCU_IR_CSC_Pos          (1U)

+#define FDCANCCU_IR_CSC_Msk          (0x1UL << FDCANCCU_IR_CSC_Pos)            /*!< 0x00000002 */

+#define FDCANCCU_IR_CSC              FDCANCCU_IR_CSC_Msk                       /*!<Calibration State Changed              */

+

+/******************  Bit definition for FDCANCCU_IE register  *******************/

+#define FDCANCCU_IE_CWEE_Pos         (0U)

+#define FDCANCCU_IE_CWEE_Msk         (0x1UL << FDCANCCU_IE_CWEE_Pos)           /*!< 0x00000001 */

+#define FDCANCCU_IE_CWEE             FDCANCCU_IE_CWEE_Msk                      /*!<Calibration Watchdog Event Enable      */

+#define FDCANCCU_IE_CSCE_Pos         (1U)

+#define FDCANCCU_IE_CSCE_Msk         (0x1UL << FDCANCCU_IE_CSCE_Pos)           /*!< 0x00000002 */

+#define FDCANCCU_IE_CSCE             FDCANCCU_IE_CSCE_Msk                      /*!<Calibration State Changed Enable       */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          HDMI-CEC (CEC)                                    */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for CEC_CR register  *********************/

+#define CEC_CR_CECEN_Pos         (0U)

+#define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                   /*!< 0x00000001 */

+#define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                                */

+#define CEC_CR_TXSOM_Pos         (1U)

+#define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                   /*!< 0x00000002 */

+#define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message                   */

+#define CEC_CR_TXEOM_Pos         (2U)

+#define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                   /*!< 0x00000004 */

+#define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message                     */

+

+/*******************  Bit definition for CEC_CFGR register  *******************/

+#define CEC_CFGR_SFT_Pos         (0U)

+#define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                   /*!< 0x00000007 */

+#define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time                      */

+#define CEC_CFGR_RXTOL_Pos       (3U)

+#define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                 /*!< 0x00000008 */

+#define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                             */

+#define CEC_CFGR_BRESTP_Pos      (4U)

+#define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                /*!< 0x00000010 */

+#define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                               */

+#define CEC_CFGR_BREGEN_Pos      (5U)

+#define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                /*!< 0x00000020 */

+#define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation           */

+#define CEC_CFGR_LBPEGEN_Pos     (6U)

+#define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)               /*!< 0x00000040 */

+#define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error generation      */

+#define CEC_CFGR_SFTOPT_Pos      (8U)

+#define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                /*!< 0x00000100 */

+#define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional             */

+#define CEC_CFGR_BRDNOGEN_Pos    (7U)

+#define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)              /*!< 0x00000080 */

+#define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No error generation         */

+#define CEC_CFGR_OAR_Pos         (16U)

+#define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                /*!< 0x7FFF0000 */

+#define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                           */

+#define CEC_CFGR_LSTN_Pos        (31U)

+#define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                  /*!< 0x80000000 */

+#define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                           */

+

+/*******************  Bit definition for CEC_TXDR register  *******************/

+#define CEC_TXDR_TXD_Pos         (0U)

+#define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                  /*!< 0x000000FF */

+#define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                               */

+

+/*******************  Bit definition for CEC_RXDR register  *******************/

+#define CEC_RXDR_RXD_Pos         (0U)

+#define CEC_RXDR_RXD_Msk         (0xFFUL << CEC_RXDR_RXD_Pos)                  /*!< 0x000000FF */

+#define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                              /*!< CEC Rx Data                               */

+

+/*******************  Bit definition for CEC_ISR register  ********************/

+#define CEC_ISR_RXBR_Pos         (0U)

+#define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                   /*!< 0x00000001 */

+#define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                      */

+#define CEC_ISR_RXEND_Pos        (1U)

+#define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                  /*!< 0x00000002 */

+#define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                      */

+#define CEC_ISR_RXOVR_Pos        (2U)

+#define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                  /*!< 0x00000004 */

+#define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                            */

+#define CEC_ISR_BRE_Pos          (3U)

+#define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                    /*!< 0x00000008 */

+#define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                   */

+#define CEC_ISR_SBPE_Pos         (4U)

+#define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                   /*!< 0x00000010 */

+#define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error             */

+#define CEC_ISR_LBPE_Pos         (5U)

+#define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                   /*!< 0x00000020 */

+#define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error              */

+#define CEC_ISR_RXACKE_Pos       (6U)

+#define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                 /*!< 0x00000040 */

+#define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge                */

+#define CEC_ISR_ARBLST_Pos       (7U)

+#define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                 /*!< 0x00000080 */

+#define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                      */

+#define CEC_ISR_TXBR_Pos         (8U)

+#define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                   /*!< 0x00000100 */

+#define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                       */

+#define CEC_ISR_TXEND_Pos        (9U)

+#define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                  /*!< 0x00000200 */

+#define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                   */

+#define CEC_ISR_TXUDR_Pos        (10U)

+#define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                  /*!< 0x00000400 */

+#define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                    */

+#define CEC_ISR_TXERR_Pos        (11U)

+#define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                  /*!< 0x00000800 */

+#define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                              */

+#define CEC_ISR_TXACKE_Pos       (12U)

+#define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                 /*!< 0x00001000 */

+#define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge                */

+

+/*******************  Bit definition for CEC_IER register  ********************/

+#define CEC_IER_RXBRIE_Pos       (0U)

+#define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                 /*!< 0x00000001 */

+#define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable            */

+#define CEC_IER_RXENDIE_Pos      (1U)

+#define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                /*!< 0x00000002 */

+#define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable            */

+#define CEC_IER_RXOVRIE_Pos      (2U)

+#define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                /*!< 0x00000004 */

+#define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable                  */

+#define CEC_IER_BREIE_Pos        (3U)

+#define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                  /*!< 0x00000008 */

+#define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable         */

+#define CEC_IER_SBPEIE_Pos       (4U)

+#define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                 /*!< 0x00000010 */

+#define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable   */

+#define CEC_IER_LBPEIE_Pos       (5U)

+#define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                 /*!< 0x00000020 */

+#define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable    */

+#define CEC_IER_RXACKEIE_Pos     (6U)

+#define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)               /*!< 0x00000040 */

+#define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable      */

+#define CEC_IER_ARBLSTIE_Pos     (7U)

+#define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)               /*!< 0x00000080 */

+#define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable            */

+#define CEC_IER_TXBRIE_Pos       (8U)

+#define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                 /*!< 0x00000100 */

+#define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable            */

+#define CEC_IER_TXENDIE_Pos      (9U)

+#define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                /*!< 0x00000200 */

+#define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable         */

+#define CEC_IER_TXUDRIE_Pos      (10U)

+#define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                /*!< 0x00000400 */

+#define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable          */

+#define CEC_IER_TXERRIE_Pos      (11U)

+#define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                /*!< 0x00000800 */

+#define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                    */

+#define CEC_IER_TXACKEIE_Pos     (12U)

+#define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)               /*!< 0x00001000 */

+#define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable      */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          CRC calculation unit                              */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for CRC_DR register  *********************/

+#define CRC_DR_DR_Pos            (0U)

+#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */

+#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */

+

+/*******************  Bit definition for CRC_IDR register  ********************/

+#define CRC_IDR_IDR_Pos          (0U)

+#define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */

+#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */

+

+/********************  Bit definition for CRC_CR register  ********************/

+#define CRC_CR_RESET_Pos         (0U)

+#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */

+#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */

+#define CRC_CR_POLYSIZE_Pos      (3U)

+#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */

+#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */

+#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */

+#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */

+#define CRC_CR_REV_IN_Pos        (5U)

+#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */

+#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */

+#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */

+#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */

+#define CRC_CR_REV_OUT_Pos       (7U)

+#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */

+#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */

+

+/*******************  Bit definition for CRC_INIT register  *******************/

+#define CRC_INIT_INIT_Pos        (0U)

+#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */

+#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */

+

+/*******************  Bit definition for CRC_POL register  ********************/

+#define CRC_POL_POL_Pos          (0U)

+#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */

+#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          CRS Clock Recovery System                         */

+/******************************************************************************/

+

+/*******************  Bit definition for CRS_CR register  *********************/

+#define CRS_CR_SYNCOKIE_Pos       (0U)

+#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */

+#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */

+#define CRS_CR_SYNCWARNIE_Pos     (1U)

+#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */

+#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */

+#define CRS_CR_ERRIE_Pos          (2U)

+#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */

+#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */

+#define CRS_CR_ESYNCIE_Pos        (3U)

+#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */

+#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */

+#define CRS_CR_CEN_Pos            (5U)

+#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */

+#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */

+#define CRS_CR_AUTOTRIMEN_Pos     (6U)

+#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */

+#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */

+#define CRS_CR_SWSYNC_Pos         (7U)

+#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */

+#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */

+#define CRS_CR_TRIM_Pos           (8U)

+#define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00003F00 */

+#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */

+

+/*******************  Bit definition for CRS_CFGR register  *********************/

+#define CRS_CFGR_RELOAD_Pos       (0U)

+#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */

+#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */

+#define CRS_CFGR_FELIM_Pos        (16U)

+#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */

+#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */

+

+#define CRS_CFGR_SYNCDIV_Pos      (24U)

+#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */

+#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */

+#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */

+#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */

+#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */

+

+#define CRS_CFGR_SYNCSRC_Pos      (28U)

+#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */

+#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */

+#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */

+#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */

+

+#define CRS_CFGR_SYNCPOL_Pos      (31U)

+#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */

+#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */

+

+/*******************  Bit definition for CRS_ISR register  *********************/

+#define CRS_ISR_SYNCOKF_Pos       (0U)

+#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */

+#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */

+#define CRS_ISR_SYNCWARNF_Pos     (1U)

+#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */

+#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */

+#define CRS_ISR_ERRF_Pos          (2U)

+#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */

+#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */

+#define CRS_ISR_ESYNCF_Pos        (3U)

+#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */

+#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */

+#define CRS_ISR_SYNCERR_Pos       (8U)

+#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */

+#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */

+#define CRS_ISR_SYNCMISS_Pos      (9U)

+#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */

+#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */

+#define CRS_ISR_TRIMOVF_Pos       (10U)

+#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */

+#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */

+#define CRS_ISR_FEDIR_Pos         (15U)

+#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */

+#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */

+#define CRS_ISR_FECAP_Pos         (16U)

+#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */

+#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */

+

+/*******************  Bit definition for CRS_ICR register  *********************/

+#define CRS_ICR_SYNCOKC_Pos       (0U)

+#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */

+#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */

+#define CRS_ICR_SYNCWARNC_Pos     (1U)

+#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */

+#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */

+#define CRS_ICR_ERRC_Pos          (2U)

+#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */

+#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */

+#define CRS_ICR_ESYNCC_Pos        (3U)

+#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */

+#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            Crypto Processor                                */

+/*                                                                            */

+/******************************************************************************/

+/******************* Bits definition for CRYP_CR register  ********************/

+#define CRYP_CR_ALGODIR_Pos              (2U)

+#define CRYP_CR_ALGODIR_Msk              (0x1UL << CRYP_CR_ALGODIR_Pos)        /*!< 0x00000004 */

+#define CRYP_CR_ALGODIR                  CRYP_CR_ALGODIR_Msk

+

+#define CRYP_CR_ALGOMODE_Pos             (3U)

+#define CRYP_CR_ALGOMODE_Msk             (0x10007UL << CRYP_CR_ALGOMODE_Pos)   /*!< 0x00080038 */

+#define CRYP_CR_ALGOMODE                 CRYP_CR_ALGOMODE_Msk

+#define CRYP_CR_ALGOMODE_0               (0x00001UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000008 */

+#define CRYP_CR_ALGOMODE_1               (0x00002UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000010 */

+#define CRYP_CR_ALGOMODE_2               (0x00004UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000020 */

+#define CRYP_CR_ALGOMODE_TDES_ECB        ((uint32_t)0x00000000)

+#define CRYP_CR_ALGOMODE_TDES_CBC_Pos    (3U)

+#define CRYP_CR_ALGOMODE_TDES_CBC_Msk    (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */

+#define CRYP_CR_ALGOMODE_TDES_CBC        CRYP_CR_ALGOMODE_TDES_CBC_Msk

+#define CRYP_CR_ALGOMODE_DES_ECB_Pos     (4U)

+#define CRYP_CR_ALGOMODE_DES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_DES_ECB_Pos) /*!< 0x00000010 */

+#define CRYP_CR_ALGOMODE_DES_ECB         CRYP_CR_ALGOMODE_DES_ECB_Msk

+#define CRYP_CR_ALGOMODE_DES_CBC_Pos     (3U)

+#define CRYP_CR_ALGOMODE_DES_CBC_Msk     (0x3UL << CRYP_CR_ALGOMODE_DES_CBC_Pos) /*!< 0x00000018 */

+#define CRYP_CR_ALGOMODE_DES_CBC         CRYP_CR_ALGOMODE_DES_CBC_Msk

+#define CRYP_CR_ALGOMODE_AES_ECB_Pos     (5U)

+#define CRYP_CR_ALGOMODE_AES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */

+#define CRYP_CR_ALGOMODE_AES_ECB         CRYP_CR_ALGOMODE_AES_ECB_Msk

+#define CRYP_CR_ALGOMODE_AES_CBC_Pos     (3U)

+#define CRYP_CR_ALGOMODE_AES_CBC_Msk     (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */

+#define CRYP_CR_ALGOMODE_AES_CBC         CRYP_CR_ALGOMODE_AES_CBC_Msk

+#define CRYP_CR_ALGOMODE_AES_CTR_Pos     (4U)

+#define CRYP_CR_ALGOMODE_AES_CTR_Msk     (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */

+#define CRYP_CR_ALGOMODE_AES_CTR         CRYP_CR_ALGOMODE_AES_CTR_Msk

+#define CRYP_CR_ALGOMODE_AES_KEY_Pos     (3U)

+#define CRYP_CR_ALGOMODE_AES_KEY_Msk     (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */

+#define CRYP_CR_ALGOMODE_AES_KEY         CRYP_CR_ALGOMODE_AES_KEY_Msk

+#define CRYP_CR_ALGOMODE_AES_GCM_Pos     (19U)

+#define CRYP_CR_ALGOMODE_AES_GCM_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_GCM_Pos) /*!< 0x00080000 */

+#define CRYP_CR_ALGOMODE_AES_GCM         CRYP_CR_ALGOMODE_AES_GCM_Msk

+#define CRYP_CR_ALGOMODE_AES_CCM_Pos     (3U)

+#define CRYP_CR_ALGOMODE_AES_CCM_Msk     (0x10001UL << CRYP_CR_ALGOMODE_AES_CCM_Pos) /*!< 0x00080008 */

+#define CRYP_CR_ALGOMODE_AES_CCM         CRYP_CR_ALGOMODE_AES_CCM_Msk

+

+#define CRYP_CR_DATATYPE_Pos             (6U)

+#define CRYP_CR_DATATYPE_Msk             (0x3UL << CRYP_CR_DATATYPE_Pos)       /*!< 0x000000C0 */

+#define CRYP_CR_DATATYPE                 CRYP_CR_DATATYPE_Msk

+#define CRYP_CR_DATATYPE_0               (0x1UL << CRYP_CR_DATATYPE_Pos)        /*!< 0x00000040 */

+#define CRYP_CR_DATATYPE_1               (0x2UL << CRYP_CR_DATATYPE_Pos)        /*!< 0x00000080 */

+#define CRYP_CR_KEYSIZE_Pos              (8U)

+#define CRYP_CR_KEYSIZE_Msk              (0x3UL << CRYP_CR_KEYSIZE_Pos)        /*!< 0x00000300 */

+#define CRYP_CR_KEYSIZE                  CRYP_CR_KEYSIZE_Msk

+#define CRYP_CR_KEYSIZE_0                (0x1UL << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000100 */

+#define CRYP_CR_KEYSIZE_1                (0x2UL << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000200 */

+#define CRYP_CR_FFLUSH_Pos               (14U)

+#define CRYP_CR_FFLUSH_Msk               (0x1UL << CRYP_CR_FFLUSH_Pos)         /*!< 0x00004000 */

+#define CRYP_CR_FFLUSH                   CRYP_CR_FFLUSH_Msk

+#define CRYP_CR_CRYPEN_Pos               (15U)

+#define CRYP_CR_CRYPEN_Msk               (0x1UL << CRYP_CR_CRYPEN_Pos)         /*!< 0x00008000 */

+#define CRYP_CR_CRYPEN                   CRYP_CR_CRYPEN_Msk

+

+#define CRYP_CR_GCM_CCMPH_Pos            (16U)

+#define CRYP_CR_GCM_CCMPH_Msk            (0x3UL << CRYP_CR_GCM_CCMPH_Pos)      /*!< 0x00030000 */

+#define CRYP_CR_GCM_CCMPH                CRYP_CR_GCM_CCMPH_Msk

+#define CRYP_CR_GCM_CCMPH_0              (0x1UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00010000 */

+#define CRYP_CR_GCM_CCMPH_1              (0x2UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00020000 */

+#define CRYP_CR_ALGOMODE_3               ((uint32_t)0x00080000)

+#define CRYP_CR_NPBLB_Pos                (20U)

+#define CRYP_CR_NPBLB_Msk                (0xFUL << CRYP_CR_NPBLB_Pos)          /*!< 0x00F00000 */

+#define CRYP_CR_NPBLB                    CRYP_CR_NPBLB_Msk

+

+/****************** Bits definition for CRYP_SR register  *********************/

+#define CRYP_SR_IFEM_Pos                 (0U)

+#define CRYP_SR_IFEM_Msk                 (0x1UL << CRYP_SR_IFEM_Pos)           /*!< 0x00000001 */

+#define CRYP_SR_IFEM                     CRYP_SR_IFEM_Msk

+#define CRYP_SR_IFNF_Pos                 (1U)

+#define CRYP_SR_IFNF_Msk                 (0x1UL << CRYP_SR_IFNF_Pos)           /*!< 0x00000002 */

+#define CRYP_SR_IFNF                     CRYP_SR_IFNF_Msk

+#define CRYP_SR_OFNE_Pos                 (2U)

+#define CRYP_SR_OFNE_Msk                 (0x1UL << CRYP_SR_OFNE_Pos)           /*!< 0x00000004 */

+#define CRYP_SR_OFNE                     CRYP_SR_OFNE_Msk

+#define CRYP_SR_OFFU_Pos                 (3U)

+#define CRYP_SR_OFFU_Msk                 (0x1UL << CRYP_SR_OFFU_Pos)           /*!< 0x00000008 */

+#define CRYP_SR_OFFU                     CRYP_SR_OFFU_Msk

+#define CRYP_SR_BUSY_Pos                 (4U)

+#define CRYP_SR_BUSY_Msk                 (0x1UL << CRYP_SR_BUSY_Pos)           /*!< 0x00000010 */

+#define CRYP_SR_BUSY                     CRYP_SR_BUSY_Msk

+/****************** Bits definition for CRYP_DMACR register  ******************/

+#define CRYP_DMACR_DIEN_Pos              (0U)

+#define CRYP_DMACR_DIEN_Msk              (0x1UL << CRYP_DMACR_DIEN_Pos)        /*!< 0x00000001 */

+#define CRYP_DMACR_DIEN                  CRYP_DMACR_DIEN_Msk

+#define CRYP_DMACR_DOEN_Pos              (1U)

+#define CRYP_DMACR_DOEN_Msk              (0x1UL << CRYP_DMACR_DOEN_Pos)        /*!< 0x00000002 */

+#define CRYP_DMACR_DOEN                  CRYP_DMACR_DOEN_Msk

+/*****************  Bits definition for CRYP_IMSCR register  ******************/

+#define CRYP_IMSCR_INIM_Pos              (0U)

+#define CRYP_IMSCR_INIM_Msk              (0x1UL << CRYP_IMSCR_INIM_Pos)        /*!< 0x00000001 */

+#define CRYP_IMSCR_INIM                  CRYP_IMSCR_INIM_Msk

+#define CRYP_IMSCR_OUTIM_Pos             (1U)

+#define CRYP_IMSCR_OUTIM_Msk             (0x1UL << CRYP_IMSCR_OUTIM_Pos)       /*!< 0x00000002 */

+#define CRYP_IMSCR_OUTIM                 CRYP_IMSCR_OUTIM_Msk

+/****************** Bits definition for CRYP_RISR register  *******************/

+#define CRYP_RISR_INRIS_Pos              (0U)

+#define CRYP_RISR_INRIS_Msk              (0x1UL << CRYP_RISR_INRIS_Pos)        /*!< 0x00000001 */

+#define CRYP_RISR_INRIS                  CRYP_RISR_INRIS_Msk

+#define CRYP_RISR_OUTRIS_Pos             (1U)

+#define CRYP_RISR_OUTRIS_Msk             (0x1UL << CRYP_RISR_OUTRIS_Pos)       /*!< 0x00000002 */

+#define CRYP_RISR_OUTRIS                 CRYP_RISR_OUTRIS_Msk

+/****************** Bits definition for CRYP_MISR register  *******************/

+#define CRYP_MISR_INMIS_Pos              (0U)

+#define CRYP_MISR_INMIS_Msk              (0x1UL << CRYP_MISR_INMIS_Pos)        /*!< 0x00000001 */

+#define CRYP_MISR_INMIS                  CRYP_MISR_INMIS_Msk

+#define CRYP_MISR_OUTMIS_Pos             (1U)

+#define CRYP_MISR_OUTMIS_Msk             (0x1UL << CRYP_MISR_OUTMIS_Pos)       /*!< 0x00000002 */

+#define CRYP_MISR_OUTMIS                 CRYP_MISR_OUTMIS_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                      Digital to Analog Converter                           */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for DAC_CR register  ********************/

+#define DAC_CR_EN1_Pos              (0U)

+#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */

+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */

+#define DAC_CR_TEN1_Pos             (1U)

+#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */

+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */

+

+#define DAC_CR_TSEL1_Pos            (2U)

+#define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */

+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */

+#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000004 */

+#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */

+#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */

+#define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */

+

+

+#define DAC_CR_WAVE1_Pos            (6U)

+#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */

+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */

+#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */

+#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */

+

+#define DAC_CR_MAMP1_Pos            (8U)

+#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */

+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */

+#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */

+#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */

+#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */

+#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */

+

+#define DAC_CR_DMAEN1_Pos           (12U)

+#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */

+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */

+#define DAC_CR_DMAUDRIE1_Pos        (13U)

+#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */

+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/

+#define DAC_CR_CEN1_Pos             (14U)

+#define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */

+#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/

+

+#define DAC_CR_EN2_Pos              (16U)

+#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */

+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */

+#define DAC_CR_TEN2_Pos             (17U)

+#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */

+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */

+

+#define DAC_CR_TSEL2_Pos            (18U)

+#define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */

+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */

+#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00040000 */

+#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */

+#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */

+#define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */

+

+

+#define DAC_CR_WAVE2_Pos            (22U)

+#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */

+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */

+#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */

+#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */

+

+#define DAC_CR_MAMP2_Pos            (24U)

+#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */

+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */

+#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */

+#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */

+#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */

+#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */

+

+#define DAC_CR_DMAEN2_Pos           (28U)

+#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */

+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */

+#define DAC_CR_DMAUDRIE2_Pos        (29U)

+#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */

+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/

+#define DAC_CR_CEN2_Pos             (30U)

+#define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */

+#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/

+

+/*****************  Bit definition for DAC_SWTRIGR register  ******************/

+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)

+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */

+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */

+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)

+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */

+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */

+

+/*****************  Bit definition for DAC_DHR12R1 register  ******************/

+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)

+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12L1 register  ******************/

+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)

+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8R1 register  ******************/

+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)

+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12R2 register  ******************/

+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)

+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12L2 register  ******************/

+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)

+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8R2 register  ******************/

+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)

+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12RD register  ******************/

+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)

+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */

+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)

+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */

+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12LD register  ******************/

+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)

+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */

+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)

+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */

+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8RD register  ******************/

+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)

+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */

+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)

+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */

+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */

+

+/*******************  Bit definition for DAC_DOR1 register  *******************/

+#define DAC_DOR1_DACC1DOR_Pos       (0U)

+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */

+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */

+

+/*******************  Bit definition for DAC_DOR2 register  *******************/

+#define DAC_DOR2_DACC2DOR_Pos       (0U)

+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */

+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */

+

+/********************  Bit definition for DAC_SR register  ********************/

+#define DAC_SR_DMAUDR1_Pos          (13U)

+#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */

+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */

+#define DAC_SR_CAL_FLAG1_Pos        (14U)

+#define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */

+#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */

+#define DAC_SR_BWST1_Pos            (15U)

+#define DAC_SR_BWST1_Msk            (0x4001UL << DAC_SR_BWST1_Pos)             /*!< 0x20008000 */

+#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */

+

+#define DAC_SR_DMAUDR2_Pos          (29U)

+#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */

+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */

+#define DAC_SR_CAL_FLAG2_Pos        (30U)

+#define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */

+#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */

+#define DAC_SR_BWST2_Pos            (31U)

+#define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */

+#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */

+

+/*******************  Bit definition for DAC_CCR register  ********************/

+#define DAC_CCR_OTRIM1_Pos          (0U)

+#define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */

+#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */

+#define DAC_CCR_OTRIM2_Pos          (16U)

+#define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */

+#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */

+

+/*******************  Bit definition for DAC_MCR register  *******************/

+#define DAC_MCR_MODE1_Pos           (0U)

+#define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */

+#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */

+#define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */

+#define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */

+#define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */

+

+#define DAC_MCR_MODE2_Pos           (16U)

+#define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */

+#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */

+#define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */

+#define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */

+#define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */

+

+/******************  Bit definition for DAC_SHSR1 register  ******************/

+#define DAC_SHSR1_TSAMPLE1_Pos      (0U)

+#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */

+#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */

+

+/******************  Bit definition for DAC_SHSR2 register  ******************/

+#define DAC_SHSR2_TSAMPLE2_Pos      (0U)

+#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */

+#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */

+

+/******************  Bit definition for DAC_SHHR register  ******************/

+#define DAC_SHHR_THOLD1_Pos         (0U)

+#define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */

+#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */

+#define DAC_SHHR_THOLD2_Pos         (16U)

+#define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */

+#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */

+

+/******************  Bit definition for DAC_SHRR register  ******************/

+#define DAC_SHRR_TREFRESH1_Pos      (0U)

+#define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */

+#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */

+#define DAC_SHRR_TREFRESH2_Pos      (16U)

+#define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */

+#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    DCMI                                    */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DCMI_CR register  ******************/

+#define DCMI_CR_CAPTURE_Pos        (0U)

+#define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)              /*!< 0x00000001 */

+#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk

+#define DCMI_CR_CM_Pos             (1U)

+#define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                   /*!< 0x00000002 */

+#define DCMI_CR_CM                 DCMI_CR_CM_Msk

+#define DCMI_CR_CROP_Pos           (2U)

+#define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                 /*!< 0x00000004 */

+#define DCMI_CR_CROP               DCMI_CR_CROP_Msk

+#define DCMI_CR_JPEG_Pos           (3U)

+#define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                 /*!< 0x00000008 */

+#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk

+#define DCMI_CR_ESS_Pos            (4U)

+#define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                  /*!< 0x00000010 */

+#define DCMI_CR_ESS                DCMI_CR_ESS_Msk

+#define DCMI_CR_PCKPOL_Pos         (5U)

+#define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)               /*!< 0x00000020 */

+#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk

+#define DCMI_CR_HSPOL_Pos          (6U)

+#define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                /*!< 0x00000040 */

+#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk

+#define DCMI_CR_VSPOL_Pos          (7U)

+#define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */

+#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk

+#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)

+#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)

+#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)

+#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)

+#define DCMI_CR_CRE_Pos            (12U)

+#define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */

+#define DCMI_CR_CRE                DCMI_CR_CRE_Msk

+#define DCMI_CR_ENABLE_Pos         (14U)

+#define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)               /*!< 0x00004000 */

+#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk

+#define DCMI_CR_BSM_Pos            (16U)

+#define DCMI_CR_BSM_Msk            (0x3UL << DCMI_CR_BSM_Pos)                  /*!< 0x00030000 */

+#define DCMI_CR_BSM                DCMI_CR_BSM_Msk

+#define DCMI_CR_BSM_0              (0x1UL << DCMI_CR_BSM_Pos)                   /*!< 0x00010000 */

+#define DCMI_CR_BSM_1              (0x2UL << DCMI_CR_BSM_Pos)                   /*!< 0x00020000 */

+#define DCMI_CR_OEBS_Pos           (18U)

+#define DCMI_CR_OEBS_Msk           (0x1UL << DCMI_CR_OEBS_Pos)                 /*!< 0x00040000 */

+#define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk

+#define DCMI_CR_LSM_Pos            (19U)

+#define DCMI_CR_LSM_Msk            (0x1UL << DCMI_CR_LSM_Pos)                  /*!< 0x00080000 */

+#define DCMI_CR_LSM                DCMI_CR_LSM_Msk

+#define DCMI_CR_OELS_Pos           (20U)

+#define DCMI_CR_OELS_Msk           (0x1UL << DCMI_CR_OELS_Pos)                 /*!< 0x00100000 */

+#define DCMI_CR_OELS               DCMI_CR_OELS_Msk

+

+/********************  Bits definition for DCMI_SR register  ******************/

+#define DCMI_SR_HSYNC_Pos          (0U)

+#define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                /*!< 0x00000001 */

+#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk

+#define DCMI_SR_VSYNC_Pos          (1U)

+#define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                /*!< 0x00000002 */

+#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk

+#define DCMI_SR_FNE_Pos            (2U)

+#define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                  /*!< 0x00000004 */

+#define DCMI_SR_FNE                DCMI_SR_FNE_Msk

+

+/********************  Bits definition for DCMI_RIS register   ****************/

+#define DCMI_RIS_FRAME_RIS_Pos     (0U)

+#define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)           /*!< 0x00000001 */

+#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk

+#define DCMI_RIS_OVR_RIS_Pos       (1U)

+#define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)             /*!< 0x00000002 */

+#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk

+#define DCMI_RIS_ERR_RIS_Pos       (2U)

+#define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)             /*!< 0x00000004 */

+#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk

+#define DCMI_RIS_VSYNC_RIS_Pos     (3U)

+#define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)           /*!< 0x00000008 */

+#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk

+#define DCMI_RIS_LINE_RIS_Pos      (4U)

+#define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)            /*!< 0x00000010 */

+#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk

+

+/********************  Bits definition for DCMI_IER register  *****************/

+#define DCMI_IER_FRAME_IE_Pos      (0U)

+#define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)            /*!< 0x00000001 */

+#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk

+#define DCMI_IER_OVR_IE_Pos        (1U)

+#define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)              /*!< 0x00000002 */

+#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk

+#define DCMI_IER_ERR_IE_Pos        (2U)

+#define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)              /*!< 0x00000004 */

+#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk

+#define DCMI_IER_VSYNC_IE_Pos      (3U)

+#define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)            /*!< 0x00000008 */

+#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk

+#define DCMI_IER_LINE_IE_Pos       (4U)

+#define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)             /*!< 0x00000010 */

+#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk

+

+

+/********************  Bits definition for DCMI_MIS register  *****************/

+#define DCMI_MIS_FRAME_MIS_Pos     (0U)

+#define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)           /*!< 0x00000001 */

+#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk

+#define DCMI_MIS_OVR_MIS_Pos       (1U)

+#define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)             /*!< 0x00000002 */

+#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk

+#define DCMI_MIS_ERR_MIS_Pos       (2U)

+#define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)             /*!< 0x00000004 */

+#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk

+#define DCMI_MIS_VSYNC_MIS_Pos     (3U)

+#define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)           /*!< 0x00000008 */

+#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk

+#define DCMI_MIS_LINE_MIS_Pos      (4U)

+#define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)            /*!< 0x00000010 */

+#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk

+

+

+/********************  Bits definition for DCMI_ICR register  *****************/

+#define DCMI_ICR_FRAME_ISC_Pos     (0U)

+#define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)           /*!< 0x00000001 */

+#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk

+#define DCMI_ICR_OVR_ISC_Pos       (1U)

+#define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)             /*!< 0x00000002 */

+#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk

+#define DCMI_ICR_ERR_ISC_Pos       (2U)

+#define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)             /*!< 0x00000004 */

+#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk

+#define DCMI_ICR_VSYNC_ISC_Pos     (3U)

+#define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)           /*!< 0x00000008 */

+#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk

+#define DCMI_ICR_LINE_ISC_Pos      (4U)

+#define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)            /*!< 0x00000010 */

+#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk

+

+

+/********************  Bits definition for DCMI_ESCR register  ******************/

+#define DCMI_ESCR_FSC_Pos          (0U)

+#define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)               /*!< 0x000000FF */

+#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk

+#define DCMI_ESCR_LSC_Pos          (8U)

+#define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)               /*!< 0x0000FF00 */

+#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk

+#define DCMI_ESCR_LEC_Pos          (16U)

+#define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)               /*!< 0x00FF0000 */

+#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk

+#define DCMI_ESCR_FEC_Pos          (24U)

+#define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)               /*!< 0xFF000000 */

+#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk

+

+/********************  Bits definition for DCMI_ESUR register  ******************/

+#define DCMI_ESUR_FSU_Pos          (0U)

+#define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)               /*!< 0x000000FF */

+#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk

+#define DCMI_ESUR_LSU_Pos          (8U)

+#define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)               /*!< 0x0000FF00 */

+#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk

+#define DCMI_ESUR_LEU_Pos          (16U)

+#define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)               /*!< 0x00FF0000 */

+#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk

+#define DCMI_ESUR_FEU_Pos          (24U)

+#define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)               /*!< 0xFF000000 */

+#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk

+

+/********************  Bits definition for DCMI_CWSTRT register  ******************/

+#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)

+#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)       /*!< 0x00003FFF */

+#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk

+#define DCMI_CWSTRT_VST_Pos        (16U)

+#define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)           /*!< 0x1FFF0000 */

+#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk

+

+/********************  Bits definition for DCMI_CWSIZE register  ******************/

+#define DCMI_CWSIZE_CAPCNT_Pos     (0U)

+#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)        /*!< 0x00003FFF */

+#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk

+#define DCMI_CWSIZE_VLINE_Pos      (16U)

+#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)         /*!< 0x3FFF0000 */

+#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk

+

+/********************  Bits definition for DCMI_DR register  ******************/

+#define DCMI_DR_BYTE0_Pos          (0U)

+#define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)               /*!< 0x000000FF */

+#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk

+#define DCMI_DR_BYTE1_Pos          (8U)

+#define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)               /*!< 0x0000FF00 */

+#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk

+#define DCMI_DR_BYTE2_Pos          (16U)

+#define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)               /*!< 0x00FF0000 */

+#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk

+#define DCMI_DR_BYTE3_Pos          (24U)

+#define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)               /*!< 0xFF000000 */

+#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                 Digital Filter for Sigma Delta Modulators                  */

+/*                                                                            */

+/******************************************************************************/

+

+/****************   DFSDM channel configuration registers  ********************/

+

+/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/

+#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)

+#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)   /*!< 0x80000000 */

+#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */

+#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)

+#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)  /*!< 0x40000000 */

+#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */

+#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)

+#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */

+#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */

+#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)

+#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x0000C000 */

+#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */

+#define DFSDM_CHCFGR1_DATPACK_1         (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */

+#define DFSDM_CHCFGR1_DATPACK_0         (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */

+#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)

+#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00003000 */

+#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */

+#define DFSDM_CHCFGR1_DATMPX_1          (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */

+#define DFSDM_CHCFGR1_DATMPX_0          (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */

+#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)

+#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)   /*!< 0x00000100 */

+#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */

+#define DFSDM_CHCFGR1_CHEN_Pos          (7U)

+#define DFSDM_CHCFGR1_CHEN_Msk          (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)      /*!< 0x00000080 */

+#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */

+#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)

+#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)    /*!< 0x00000040 */

+#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */

+#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)

+#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)     /*!< 0x00000020 */

+#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */

+#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)

+#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x0000000C */

+#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */

+#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */

+#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */

+#define DFSDM_CHCFGR1_SITP_Pos          (0U)

+#define DFSDM_CHCFGR1_SITP_Msk          (0x3UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000003 */

+#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */

+#define DFSDM_CHCFGR1_SITP_1            (0x2UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */

+#define DFSDM_CHCFGR1_SITP_0            (0x1UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */

+

+/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/

+#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)

+#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */

+#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)

+#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)    /*!< 0x000000F8 */

+#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */

+

+/******************  Bit definition for DFSDM_CHAWSCDR register *****************/

+#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)

+#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00C00000 */

+#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */

+#define DFSDM_CHAWSCDR_AWFORD_1         (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */

+#define DFSDM_CHAWSCDR_AWFORD_0         (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */

+#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)

+#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)  /*!< 0x001F0000 */

+#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */

+#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)

+#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)    /*!< 0x0000F000 */

+#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */

+#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)

+#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)    /*!< 0x000000FF */

+#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */

+

+/****************  Bit definition for DFSDM_CHWDATR register *******************/

+#define DFSDM_CHWDATR_WDATA_Pos         (0U)

+#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)  /*!< 0x0000FFFF */

+#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */

+

+/****************  Bit definition for DFSDM_CHDATINR register *****************/

+#define DFSDM_CHDATINR_INDAT0_Pos       (0U)

+#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */

+#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */

+#define DFSDM_CHDATINR_INDAT1_Pos       (16U)

+#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */

+#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */

+

+/************************   DFSDM module registers  ****************************/

+

+/********************  Bit definition for DFSDM_FLTCR1 register *******************/

+#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)

+#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)     /*!< 0x40000000 */

+#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */

+#define DFSDM_FLTCR1_FAST_Pos           (29U)

+#define DFSDM_FLTCR1_FAST_Msk           (0x1UL << DFSDM_FLTCR1_FAST_Pos)       /*!< 0x20000000 */

+#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */

+#define DFSDM_FLTCR1_RCH_Pos            (24U)

+#define DFSDM_FLTCR1_RCH_Msk            (0x7UL << DFSDM_FLTCR1_RCH_Pos)        /*!< 0x07000000 */

+#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */

+#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)

+#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)     /*!< 0x00200000 */

+#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */

+#define DFSDM_FLTCR1_RSYNC_Pos          (19U)

+#define DFSDM_FLTCR1_RSYNC_Msk          (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)      /*!< 0x00080000 */

+#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */

+#define DFSDM_FLTCR1_RCONT_Pos          (18U)

+#define DFSDM_FLTCR1_RCONT_Msk          (0x1UL << DFSDM_FLTCR1_RCONT_Pos)      /*!< 0x00040000 */

+#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */

+#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)

+#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)   /*!< 0x00020000 */

+#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */

+#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)

+#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00006000 */

+#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */

+#define DFSDM_FLTCR1_JEXTEN_1           (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */

+#define DFSDM_FLTCR1_JEXTEN_0           (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */

+#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)

+#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)   /*!< 0x00001F00 */

+#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */

+#define DFSDM_FLTCR1_JEXTSEL_0          (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000100 */

+#define DFSDM_FLTCR1_JEXTSEL_1          (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000200 */

+#define DFSDM_FLTCR1_JEXTSEL_2          (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000400 */

+#define DFSDM_FLTCR1_JEXTSEL_3          (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000800 */

+#define DFSDM_FLTCR1_JEXTSEL_4          (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00001000 */

+

+#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)

+#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)     /*!< 0x00000020 */

+#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */

+#define DFSDM_FLTCR1_JSCAN_Pos          (4U)

+#define DFSDM_FLTCR1_JSCAN_Msk          (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)      /*!< 0x00000010 */

+#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */

+#define DFSDM_FLTCR1_JSYNC_Pos          (3U)

+#define DFSDM_FLTCR1_JSYNC_Msk          (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)      /*!< 0x00000008 */

+#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */

+#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)

+#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)   /*!< 0x00000002 */

+#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */

+#define DFSDM_FLTCR1_DFEN_Pos           (0U)

+#define DFSDM_FLTCR1_DFEN_Msk           (0x1UL << DFSDM_FLTCR1_DFEN_Pos)       /*!< 0x00000001 */

+#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */

+

+/********************  Bit definition for DFSDM_FLTCR2 register *******************/

+#define DFSDM_FLTCR2_AWDCH_Pos          (16U)

+#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)     /*!< 0x00FF0000 */

+#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */

+#define DFSDM_FLTCR2_EXCH_Pos           (8U)

+#define DFSDM_FLTCR2_EXCH_Msk           (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)      /*!< 0x0000FF00 */

+#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */

+#define DFSDM_FLTCR2_CKABIE_Pos         (6U)

+#define DFSDM_FLTCR2_CKABIE_Msk         (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)     /*!< 0x00000040 */

+#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */

+#define DFSDM_FLTCR2_SCDIE_Pos          (5U)

+#define DFSDM_FLTCR2_SCDIE_Msk          (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)      /*!< 0x00000020 */

+#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */

+#define DFSDM_FLTCR2_AWDIE_Pos          (4U)

+#define DFSDM_FLTCR2_AWDIE_Msk          (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)      /*!< 0x00000010 */

+#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */

+#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)

+#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)     /*!< 0x00000008 */

+#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */

+#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)

+#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)     /*!< 0x00000004 */

+#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */

+#define DFSDM_FLTCR2_REOCIE_Pos         (1U)

+#define DFSDM_FLTCR2_REOCIE_Msk         (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)     /*!< 0x00000002 */

+#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */

+#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)

+#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)     /*!< 0x00000001 */

+#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */

+

+/********************  Bit definition for DFSDM_FLTISR register *******************/

+#define DFSDM_FLTISR_SCDF_Pos           (24U)

+#define DFSDM_FLTISR_SCDF_Msk           (0xFFUL << DFSDM_FLTISR_SCDF_Pos)      /*!< 0xFF000000 */

+#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */

+#define DFSDM_FLTISR_CKABF_Pos          (16U)

+#define DFSDM_FLTISR_CKABF_Msk          (0xFFUL << DFSDM_FLTISR_CKABF_Pos)     /*!< 0x00FF0000 */

+#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */

+#define DFSDM_FLTISR_RCIP_Pos           (14U)

+#define DFSDM_FLTISR_RCIP_Msk           (0x1UL << DFSDM_FLTISR_RCIP_Pos)       /*!< 0x00004000 */

+#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */

+#define DFSDM_FLTISR_JCIP_Pos           (13U)

+#define DFSDM_FLTISR_JCIP_Msk           (0x1UL << DFSDM_FLTISR_JCIP_Pos)       /*!< 0x00002000 */

+#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */

+#define DFSDM_FLTISR_AWDF_Pos           (4U)

+#define DFSDM_FLTISR_AWDF_Msk           (0x1UL << DFSDM_FLTISR_AWDF_Pos)       /*!< 0x00000010 */

+#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */

+#define DFSDM_FLTISR_ROVRF_Pos          (3U)

+#define DFSDM_FLTISR_ROVRF_Msk          (0x1UL << DFSDM_FLTISR_ROVRF_Pos)      /*!< 0x00000008 */

+#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */

+#define DFSDM_FLTISR_JOVRF_Pos          (2U)

+#define DFSDM_FLTISR_JOVRF_Msk          (0x1UL << DFSDM_FLTISR_JOVRF_Pos)      /*!< 0x00000004 */

+#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */

+#define DFSDM_FLTISR_REOCF_Pos          (1U)

+#define DFSDM_FLTISR_REOCF_Msk          (0x1UL << DFSDM_FLTISR_REOCF_Pos)      /*!< 0x00000002 */

+#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */

+#define DFSDM_FLTISR_JEOCF_Pos          (0U)

+#define DFSDM_FLTISR_JEOCF_Msk          (0x1UL << DFSDM_FLTISR_JEOCF_Pos)      /*!< 0x00000001 */

+#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */

+

+/********************  Bit definition for DFSDM_FLTICR register *******************/

+#define DFSDM_FLTICR_CLRSCDF_Pos        (24U)

+#define DFSDM_FLTICR_CLRSCDF_Msk        (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)   /*!< 0xFF000000 */

+#define DFSDM_FLTICR_CLRSCDF            DFSDM_FLTICR_CLRSCDF_Msk               /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */

+#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)

+#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)  /*!< 0x00FF0000 */

+#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */

+#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)

+#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)   /*!< 0x00000008 */

+#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */

+#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)

+#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)   /*!< 0x00000004 */

+#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */

+

+/*******************  Bit definition for DFSDM_FLTJCHGR register ******************/

+#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)

+#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)    /*!< 0x000000FF */

+#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */

+

+/********************  Bit definition for DFSDM_FLTFCR register *******************/

+#define DFSDM_FLTFCR_FORD_Pos           (29U)

+#define DFSDM_FLTFCR_FORD_Msk           (0x7UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0xE0000000 */

+#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */

+#define DFSDM_FLTFCR_FORD_2             (0x4UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */

+#define DFSDM_FLTFCR_FORD_1             (0x2UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */

+#define DFSDM_FLTFCR_FORD_0             (0x1UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */

+#define DFSDM_FLTFCR_FOSR_Pos           (16U)

+#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)     /*!< 0x03FF0000 */

+#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */

+#define DFSDM_FLTFCR_IOSR_Pos           (0U)

+#define DFSDM_FLTFCR_IOSR_Msk           (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)      /*!< 0x000000FF */

+#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */

+

+/******************  Bit definition for DFSDM_FLTJDATAR register *****************/

+#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)

+#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */

+#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)

+#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */

+#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */

+

+/******************  Bit definition for DFSDM_FLTRDATAR register *****************/

+#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)

+#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */

+#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)

+#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)   /*!< 0x00000010 */

+#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */

+#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)

+#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */

+#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */

+

+/******************  Bit definition for DFSDM_FLTAWHTR register ******************/

+#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)

+#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */

+#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)

+#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)    /*!< 0x0000000F */

+#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */

+

+/******************  Bit definition for DFSDM_FLTAWLTR register ******************/

+#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)

+#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWHT[23:0] Analog watchdog low threshold */

+#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)

+#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)    /*!< 0x0000000F */

+#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */

+

+/******************  Bit definition for DFSDM_FLTAWSR register ******************/

+#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)

+#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)    /*!< 0x0000FF00 */

+#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */

+#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)

+#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)    /*!< 0x000000FF */

+#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */

+

+/******************  Bit definition for DFSDM_FLTAWCFR) register *****************/

+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)

+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */

+#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */

+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)

+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */

+#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */

+

+/******************  Bit definition for DFSDM_FLTEXMAX register ******************/

+#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)

+#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */

+#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)

+#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)  /*!< 0x00000007 */

+#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */

+

+/******************  Bit definition for DFSDM_FLTEXMIN register ******************/

+#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)

+#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */

+#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)

+#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)  /*!< 0x00000007 */

+#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */

+

+/******************  Bit definition for DFSDM_FLTCNVTIMR register ******************/

+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)

+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */

+#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           BDMA Controller                                  */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for BDMA_ISR register  ********************/

+#define BDMA_ISR_GIF0_Pos       (0U)

+#define BDMA_ISR_GIF0_Msk       (0x1UL << BDMA_ISR_GIF0_Pos)                   /*!< 0x00000001 */

+#define BDMA_ISR_GIF0           BDMA_ISR_GIF0_Msk                              /*!< Channel 0 Global interrupt flag */

+#define BDMA_ISR_TCIF0_Pos      (1U)

+#define BDMA_ISR_TCIF0_Msk      (0x1UL << BDMA_ISR_TCIF0_Pos)                  /*!< 0x00000002 */

+#define BDMA_ISR_TCIF0          BDMA_ISR_TCIF0_Msk                             /*!< Channel 0 Transfer Complete flag */

+#define BDMA_ISR_HTIF0_Pos      (2U)

+#define BDMA_ISR_HTIF0_Msk      (0x1UL << BDMA_ISR_HTIF0_Pos)                  /*!< 0x00000004 */

+#define BDMA_ISR_HTIF0          BDMA_ISR_HTIF0_Msk                             /*!< Channel 0 Half Transfer flag */

+#define BDMA_ISR_TEIF0_Pos      (3U)

+#define BDMA_ISR_TEIF0_Msk      (0x1UL << BDMA_ISR_TEIF0_Pos)                  /*!< 0x00000008 */

+#define BDMA_ISR_TEIF0          BDMA_ISR_TEIF0_Msk                             /*!< Channel 0 Transfer Error flag */

+#define BDMA_ISR_GIF1_Pos       (4U)

+#define BDMA_ISR_GIF1_Msk       (0x1UL << BDMA_ISR_GIF1_Pos)                   /*!< 0x00000010 */

+#define BDMA_ISR_GIF1           BDMA_ISR_GIF1_Msk                              /*!< Channel 1 Global interrupt flag */

+#define BDMA_ISR_TCIF1_Pos      (5U)

+#define BDMA_ISR_TCIF1_Msk      (0x1UL << BDMA_ISR_TCIF1_Pos)                  /*!< 0x00000020 */

+#define BDMA_ISR_TCIF1          BDMA_ISR_TCIF1_Msk                             /*!< Channel 1 Transfer Complete flag */

+#define BDMA_ISR_HTIF1_Pos      (6U)

+#define BDMA_ISR_HTIF1_Msk      (0x1UL << BDMA_ISR_HTIF1_Pos)                  /*!< 0x00000040 */

+#define BDMA_ISR_HTIF1          BDMA_ISR_HTIF1_Msk                             /*!< Channel 1 Half Transfer flag */

+#define BDMA_ISR_TEIF1_Pos      (7U)

+#define BDMA_ISR_TEIF1_Msk      (0x1UL << BDMA_ISR_TEIF1_Pos)                  /*!< 0x00000080 */

+#define BDMA_ISR_TEIF1          BDMA_ISR_TEIF1_Msk                             /*!< Channel 1 Transfer Error flag */

+#define BDMA_ISR_GIF2_Pos       (8U)

+#define BDMA_ISR_GIF2_Msk       (0x1UL << BDMA_ISR_GIF2_Pos)                   /*!< 0x00000100 */

+#define BDMA_ISR_GIF2           BDMA_ISR_GIF2_Msk                              /*!< Channel 2 Global interrupt flag */

+#define BDMA_ISR_TCIF2_Pos      (9U)

+#define BDMA_ISR_TCIF2_Msk      (0x1UL << BDMA_ISR_TCIF2_Pos)                  /*!< 0x00000200 */

+#define BDMA_ISR_TCIF2          BDMA_ISR_TCIF2_Msk                             /*!< Channel 2 Transfer Complete flag */

+#define BDMA_ISR_HTIF2_Pos      (10U)

+#define BDMA_ISR_HTIF2_Msk      (0x1UL << BDMA_ISR_HTIF2_Pos)                  /*!< 0x00000400 */

+#define BDMA_ISR_HTIF2          BDMA_ISR_HTIF2_Msk                             /*!< Channel 2 Half Transfer flag */

+#define BDMA_ISR_TEIF2_Pos      (11U)

+#define BDMA_ISR_TEIF2_Msk      (0x1UL << BDMA_ISR_TEIF2_Pos)                  /*!< 0x00000800 */

+#define BDMA_ISR_TEIF2          BDMA_ISR_TEIF2_Msk                             /*!< Channel 2 Transfer Error flag */

+#define BDMA_ISR_GIF3_Pos       (12U)

+#define BDMA_ISR_GIF3_Msk       (0x1UL << BDMA_ISR_GIF3_Pos)                   /*!< 0x00001000 */

+#define BDMA_ISR_GIF3           BDMA_ISR_GIF3_Msk                              /*!< Channel 3 Global interrupt flag */

+#define BDMA_ISR_TCIF3_Pos      (13U)

+#define BDMA_ISR_TCIF3_Msk      (0x1UL << BDMA_ISR_TCIF3_Pos)                  /*!< 0x00002000 */

+#define BDMA_ISR_TCIF3          BDMA_ISR_TCIF3_Msk                             /*!< Channel 3 Transfer Complete flag */

+#define BDMA_ISR_HTIF3_Pos      (14U)

+#define BDMA_ISR_HTIF3_Msk      (0x1UL << BDMA_ISR_HTIF3_Pos)                  /*!< 0x00004000 */

+#define BDMA_ISR_HTIF3          BDMA_ISR_HTIF3_Msk                             /*!< Channel 3 Half Transfer flag */

+#define BDMA_ISR_TEIF3_Pos      (15U)

+#define BDMA_ISR_TEIF3_Msk      (0x1UL << BDMA_ISR_TEIF3_Pos)                  /*!< 0x00008000 */

+#define BDMA_ISR_TEIF3          BDMA_ISR_TEIF3_Msk                             /*!< Channel 3 Transfer Error flag */

+#define BDMA_ISR_GIF4_Pos       (16U)

+#define BDMA_ISR_GIF4_Msk       (0x1UL << BDMA_ISR_GIF4_Pos)                   /*!< 0x00010000 */

+#define BDMA_ISR_GIF4           BDMA_ISR_GIF4_Msk                              /*!< Channel 4 Global interrupt flag */

+#define BDMA_ISR_TCIF4_Pos      (17U)

+#define BDMA_ISR_TCIF4_Msk      (0x1UL << BDMA_ISR_TCIF4_Pos)                  /*!< 0x00020000 */

+#define BDMA_ISR_TCIF4          BDMA_ISR_TCIF4_Msk                             /*!< Channel 4 Transfer Complete flag */

+#define BDMA_ISR_HTIF4_Pos      (18U)

+#define BDMA_ISR_HTIF4_Msk      (0x1UL << BDMA_ISR_HTIF4_Pos)                  /*!< 0x00040000 */

+#define BDMA_ISR_HTIF4          BDMA_ISR_HTIF4_Msk                             /*!< Channel 4 Half Transfer flag */

+#define BDMA_ISR_TEIF4_Pos      (19U)

+#define BDMA_ISR_TEIF4_Msk      (0x1UL << BDMA_ISR_TEIF4_Pos)                  /*!< 0x00080000 */

+#define BDMA_ISR_TEIF4          BDMA_ISR_TEIF4_Msk                             /*!< Channel 4 Transfer Error flag */

+#define BDMA_ISR_GIF5_Pos       (20U)

+#define BDMA_ISR_GIF5_Msk       (0x1UL << BDMA_ISR_GIF5_Pos)                   /*!< 0x00100000 */

+#define BDMA_ISR_GIF5           BDMA_ISR_GIF5_Msk                              /*!< Channel 5 Global interrupt flag */

+#define BDMA_ISR_TCIF5_Pos      (21U)

+#define BDMA_ISR_TCIF5_Msk      (0x1UL << BDMA_ISR_TCIF5_Pos)                  /*!< 0x00200000 */

+#define BDMA_ISR_TCIF5          BDMA_ISR_TCIF5_Msk                             /*!< Channel 5 Transfer Complete flag */

+#define BDMA_ISR_HTIF5_Pos      (22U)

+#define BDMA_ISR_HTIF5_Msk      (0x1UL << BDMA_ISR_HTIF5_Pos)                  /*!< 0x00400000 */

+#define BDMA_ISR_HTIF5          BDMA_ISR_HTIF5_Msk                             /*!< Channel 5 Half Transfer flag */

+#define BDMA_ISR_TEIF5_Pos      (23U)

+#define BDMA_ISR_TEIF5_Msk      (0x1UL << BDMA_ISR_TEIF5_Pos)                  /*!< 0x00800000 */

+#define BDMA_ISR_TEIF5          BDMA_ISR_TEIF5_Msk                             /*!< Channel 5 Transfer Error flag */

+#define BDMA_ISR_GIF6_Pos       (24U)

+#define BDMA_ISR_GIF6_Msk       (0x1UL << BDMA_ISR_GIF6_Pos)                   /*!< 0x01000000 */

+#define BDMA_ISR_GIF6           BDMA_ISR_GIF6_Msk                              /*!< Channel 6 Global interrupt flag */

+#define BDMA_ISR_TCIF6_Pos      (25U)

+#define BDMA_ISR_TCIF6_Msk      (0x1UL << BDMA_ISR_TCIF6_Pos)                  /*!< 0x02000000 */

+#define BDMA_ISR_TCIF6          BDMA_ISR_TCIF6_Msk                             /*!< Channel 6 Transfer Complete flag */

+#define BDMA_ISR_HTIF6_Pos      (26U)

+#define BDMA_ISR_HTIF6_Msk      (0x1UL << BDMA_ISR_HTIF6_Pos)                  /*!< 0x04000000 */

+#define BDMA_ISR_HTIF6          BDMA_ISR_HTIF6_Msk                             /*!< Channel 6 Half Transfer flag */

+#define BDMA_ISR_TEIF6_Pos      (27U)

+#define BDMA_ISR_TEIF6_Msk      (0x1UL << BDMA_ISR_TEIF6_Pos)                  /*!< 0x08000000 */

+#define BDMA_ISR_TEIF6          BDMA_ISR_TEIF6_Msk                             /*!< Channel 6 Transfer Error flag */

+#define BDMA_ISR_GIF7_Pos       (28U)

+#define BDMA_ISR_GIF7_Msk       (0x1UL << BDMA_ISR_GIF7_Pos)                   /*!< 0x10000000 */

+#define BDMA_ISR_GIF7           BDMA_ISR_GIF7_Msk                              /*!< Channel 7 Global interrupt flag */

+#define BDMA_ISR_TCIF7_Pos      (29U)

+#define BDMA_ISR_TCIF7_Msk      (0x1UL << BDMA_ISR_TCIF7_Pos)                  /*!< 0x20000000 */

+#define BDMA_ISR_TCIF7          BDMA_ISR_TCIF7_Msk                             /*!< Channel 7 Transfer Complete flag */

+#define BDMA_ISR_HTIF7_Pos      (30U)

+#define BDMA_ISR_HTIF7_Msk      (0x1UL << BDMA_ISR_HTIF7_Pos)                  /*!< 0x40000000 */

+#define BDMA_ISR_HTIF7          BDMA_ISR_HTIF7_Msk                             /*!< Channel 7 Half Transfer flag */

+#define BDMA_ISR_TEIF7_Pos      (31U)

+#define BDMA_ISR_TEIF7_Msk      (0x1UL << BDMA_ISR_TEIF7_Pos)                  /*!< 0x80000000 */

+#define BDMA_ISR_TEIF7          BDMA_ISR_TEIF7_Msk                             /*!< Channel 7 Transfer Error flag */

+

+/*******************  Bit definition for BDMA_IFCR register  *******************/

+#define BDMA_IFCR_CGIF0_Pos     (0U)

+#define BDMA_IFCR_CGIF0_Msk     (0x1UL << BDMA_IFCR_CGIF0_Pos)                 /*!< 0x00000001 */

+#define BDMA_IFCR_CGIF0         BDMA_IFCR_CGIF0_Msk                            /*!< Channel 0 Global interrupt clearr */

+#define BDMA_IFCR_CTCIF0_Pos    (1U)

+#define BDMA_IFCR_CTCIF0_Msk    (0x1UL << BDMA_IFCR_CTCIF0_Pos)                /*!< 0x00000002 */

+#define BDMA_IFCR_CTCIF0        BDMA_IFCR_CTCIF0_Msk                           /*!< Channel 0 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF0_Pos    (2U)

+#define BDMA_IFCR_CHTIF0_Msk    (0x1UL << BDMA_IFCR_CHTIF0_Pos)                /*!< 0x00000004 */

+#define BDMA_IFCR_CHTIF0        BDMA_IFCR_CHTIF0_Msk                           /*!< Channel 0 Half Transfer clear */

+#define BDMA_IFCR_CTEIF0_Pos    (3U)

+#define BDMA_IFCR_CTEIF0_Msk    (0x1UL << BDMA_IFCR_CTEIF0_Pos)                /*!< 0x00000008 */

+#define BDMA_IFCR_CTEIF0        BDMA_IFCR_CTEIF0_Msk                           /*!< Channel 0 Transfer Error clear */

+#define BDMA_IFCR_CGIF1_Pos     (4U)

+#define BDMA_IFCR_CGIF1_Msk     (0x1UL << BDMA_IFCR_CGIF1_Pos)                 /*!< 0x00000010 */

+#define BDMA_IFCR_CGIF1         BDMA_IFCR_CGIF1_Msk                            /*!< Channel 1 Global interrupt clear */

+#define BDMA_IFCR_CTCIF1_Pos    (5U)

+#define BDMA_IFCR_CTCIF1_Msk    (0x1UL << BDMA_IFCR_CTCIF1_Pos)                /*!< 0x00000020 */

+#define BDMA_IFCR_CTCIF1        BDMA_IFCR_CTCIF1_Msk                           /*!< Channel 1 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF1_Pos    (6U)

+#define BDMA_IFCR_CHTIF1_Msk    (0x1UL << BDMA_IFCR_CHTIF1_Pos)                /*!< 0x00000040 */

+#define BDMA_IFCR_CHTIF1        BDMA_IFCR_CHTIF1_Msk                           /*!< Channel 1 Half Transfer clear */

+#define BDMA_IFCR_CTEIF1_Pos    (7U)

+#define BDMA_IFCR_CTEIF1_Msk    (0x1UL << BDMA_IFCR_CTEIF1_Pos)                /*!< 0x00000080 */

+#define BDMA_IFCR_CTEIF1        BDMA_IFCR_CTEIF1_Msk                           /*!< Channel 1 Transfer Error clear */

+#define BDMA_IFCR_CGIF2_Pos     (8U)

+#define BDMA_IFCR_CGIF2_Msk     (0x1UL << BDMA_IFCR_CGIF2_Pos)                 /*!< 0x00000100 */

+#define BDMA_IFCR_CGIF2         BDMA_IFCR_CGIF2_Msk                            /*!< Channel 2 Global interrupt clear */

+#define BDMA_IFCR_CTCIF2_Pos    (9U)

+#define BDMA_IFCR_CTCIF2_Msk    (0x1UL << BDMA_IFCR_CTCIF2_Pos)                /*!< 0x00000200 */

+#define BDMA_IFCR_CTCIF2        BDMA_IFCR_CTCIF2_Msk                           /*!< Channel 2 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF2_Pos    (10U)

+#define BDMA_IFCR_CHTIF2_Msk    (0x1UL << BDMA_IFCR_CHTIF2_Pos)                /*!< 0x00000400 */

+#define BDMA_IFCR_CHTIF2        BDMA_IFCR_CHTIF2_Msk                           /*!< Channel 2 Half Transfer clear */

+#define BDMA_IFCR_CTEIF2_Pos    (11U)

+#define BDMA_IFCR_CTEIF2_Msk    (0x1UL << BDMA_IFCR_CTEIF2_Pos)                /*!< 0x00000800 */

+#define BDMA_IFCR_CTEIF2        BDMA_IFCR_CTEIF2_Msk                           /*!< Channel 2 Transfer Error clear */

+#define BDMA_IFCR_CGIF3_Pos     (12U)

+#define BDMA_IFCR_CGIF3_Msk     (0x1UL << BDMA_IFCR_CGIF3_Pos)                 /*!< 0x00001000 */

+#define BDMA_IFCR_CGIF3         BDMA_IFCR_CGIF3_Msk                            /*!< Channel 3 Global interrupt clear */

+#define BDMA_IFCR_CTCIF3_Pos    (13U)

+#define BDMA_IFCR_CTCIF3_Msk    (0x1UL << BDMA_IFCR_CTCIF3_Pos)                /*!< 0x00002000 */

+#define BDMA_IFCR_CTCIF3        BDMA_IFCR_CTCIF3_Msk                           /*!< Channel 3 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF3_Pos    (14U)

+#define BDMA_IFCR_CHTIF3_Msk    (0x1UL << BDMA_IFCR_CHTIF3_Pos)                /*!< 0x00004000 */

+#define BDMA_IFCR_CHTIF3        BDMA_IFCR_CHTIF3_Msk                           /*!< Channel 3 Half Transfer clear */

+#define BDMA_IFCR_CTEIF3_Pos    (15U)

+#define BDMA_IFCR_CTEIF3_Msk    (0x1UL << BDMA_IFCR_CTEIF3_Pos)                /*!< 0x00008000 */

+#define BDMA_IFCR_CTEIF3        BDMA_IFCR_CTEIF3_Msk                           /*!< Channel 3 Transfer Error clear */

+#define BDMA_IFCR_CGIF4_Pos     (16U)

+#define BDMA_IFCR_CGIF4_Msk     (0x1UL << BDMA_IFCR_CGIF4_Pos)                 /*!< 0x00010000 */

+#define BDMA_IFCR_CGIF4         BDMA_IFCR_CGIF4_Msk                            /*!< Channel 4 Global interrupt clear */

+#define BDMA_IFCR_CTCIF4_Pos    (17U)

+#define BDMA_IFCR_CTCIF4_Msk    (0x1UL << BDMA_IFCR_CTCIF4_Pos)                /*!< 0x00020000 */

+#define BDMA_IFCR_CTCIF4        BDMA_IFCR_CTCIF4_Msk                           /*!< Channel 4 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF4_Pos    (18U)

+#define BDMA_IFCR_CHTIF4_Msk    (0x1UL << BDMA_IFCR_CHTIF4_Pos)                /*!< 0x00040000 */

+#define BDMA_IFCR_CHTIF4        BDMA_IFCR_CHTIF4_Msk                           /*!< Channel 4 Half Transfer clear */

+#define BDMA_IFCR_CTEIF4_Pos    (19U)

+#define BDMA_IFCR_CTEIF4_Msk    (0x1UL << BDMA_IFCR_CTEIF4_Pos)                /*!< 0x00080000 */

+#define BDMA_IFCR_CTEIF4        BDMA_IFCR_CTEIF4_Msk                           /*!< Channel 4 Transfer Error clear */

+#define BDMA_IFCR_CGIF5_Pos     (20U)

+#define BDMA_IFCR_CGIF5_Msk     (0x1UL << BDMA_IFCR_CGIF5_Pos)                 /*!< 0x00100000 */

+#define BDMA_IFCR_CGIF5         BDMA_IFCR_CGIF5_Msk                            /*!< Channel 5 Global interrupt clear */

+#define BDMA_IFCR_CTCIF5_Pos    (21U)

+#define BDMA_IFCR_CTCIF5_Msk    (0x1UL << BDMA_IFCR_CTCIF5_Pos)                /*!< 0x00200000 */

+#define BDMA_IFCR_CTCIF5        BDMA_IFCR_CTCIF5_Msk                           /*!< Channel 5 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF5_Pos    (22U)

+#define BDMA_IFCR_CHTIF5_Msk    (0x1UL << BDMA_IFCR_CHTIF5_Pos)                /*!< 0x00400000 */

+#define BDMA_IFCR_CHTIF5        BDMA_IFCR_CHTIF5_Msk                           /*!< Channel 5 Half Transfer clear */

+#define BDMA_IFCR_CTEIF5_Pos    (23U)

+#define BDMA_IFCR_CTEIF5_Msk    (0x1UL << BDMA_IFCR_CTEIF5_Pos)                /*!< 0x00800000 */

+#define BDMA_IFCR_CTEIF5        BDMA_IFCR_CTEIF5_Msk                           /*!< Channel 5 Transfer Error clear */

+#define BDMA_IFCR_CGIF6_Pos     (24U)

+#define BDMA_IFCR_CGIF6_Msk     (0x1UL << BDMA_IFCR_CGIF6_Pos)                 /*!< 0x01000000 */

+#define BDMA_IFCR_CGIF6         BDMA_IFCR_CGIF6_Msk                            /*!< Channel 6 Global interrupt clear */

+#define BDMA_IFCR_CTCIF6_Pos    (25U)

+#define BDMA_IFCR_CTCIF6_Msk    (0x1UL << BDMA_IFCR_CTCIF6_Pos)                /*!< 0x02000000 */

+#define BDMA_IFCR_CTCIF6        BDMA_IFCR_CTCIF6_Msk                           /*!< Channel 6 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF6_Pos    (26U)

+#define BDMA_IFCR_CHTIF6_Msk    (0x1UL << BDMA_IFCR_CHTIF6_Pos)                /*!< 0x04000000 */

+#define BDMA_IFCR_CHTIF6        BDMA_IFCR_CHTIF6_Msk                           /*!< Channel 6 Half Transfer clear */

+#define BDMA_IFCR_CTEIF6_Pos    (27U)

+#define BDMA_IFCR_CTEIF6_Msk    (0x1UL << BDMA_IFCR_CTEIF6_Pos)                /*!< 0x08000000 */

+#define BDMA_IFCR_CTEIF6        BDMA_IFCR_CTEIF6_Msk                           /*!< Channel 6 Transfer Error clear */

+#define BDMA_IFCR_CGIF7_Pos     (28U)

+#define BDMA_IFCR_CGIF7_Msk     (0x1UL << BDMA_IFCR_CGIF7_Pos)                 /*!< 0x10000000 */

+#define BDMA_IFCR_CGIF7         BDMA_IFCR_CGIF7_Msk                            /*!< Channel 7 Global interrupt clear */

+#define BDMA_IFCR_CTCIF7_Pos    (29U)

+#define BDMA_IFCR_CTCIF7_Msk    (0x1UL << BDMA_IFCR_CTCIF7_Pos)                /*!< 0x20000000 */

+#define BDMA_IFCR_CTCIF7        BDMA_IFCR_CTCIF7_Msk                           /*!< Channel 7 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF7_Pos    (30U)

+#define BDMA_IFCR_CHTIF7_Msk    (0x1UL << BDMA_IFCR_CHTIF7_Pos)                /*!< 0x40000000 */

+#define BDMA_IFCR_CHTIF7        BDMA_IFCR_CHTIF7_Msk                           /*!< Channel 7 Half Transfer clear */

+#define BDMA_IFCR_CTEIF7_Pos    (31U)

+#define BDMA_IFCR_CTEIF7_Msk    (0x1UL << BDMA_IFCR_CTEIF7_Pos)                /*!< 0x80000000 */

+#define BDMA_IFCR_CTEIF7        BDMA_IFCR_CTEIF7_Msk                           /*!< Channel 7 Transfer Error clear */

+

+/*******************  Bit definition for BDMA_CCR register  ********************/

+#define BDMA_CCR_EN_Pos         (0U)

+#define BDMA_CCR_EN_Msk         (0x1UL << BDMA_CCR_EN_Pos)                     /*!< 0x00000001 */

+#define BDMA_CCR_EN             BDMA_CCR_EN_Msk                                /*!< Channel enable                      */

+#define BDMA_CCR_TCIE_Pos       (1U)

+#define BDMA_CCR_TCIE_Msk       (0x1UL << BDMA_CCR_TCIE_Pos)                   /*!< 0x00000002 */

+#define BDMA_CCR_TCIE           BDMA_CCR_TCIE_Msk                              /*!< Transfer complete interrupt enable  */

+#define BDMA_CCR_HTIE_Pos       (2U)

+#define BDMA_CCR_HTIE_Msk       (0x1UL << BDMA_CCR_HTIE_Pos)                   /*!< 0x00000004 */

+#define BDMA_CCR_HTIE           BDMA_CCR_HTIE_Msk                              /*!< Half Transfer interrupt enable      */

+#define BDMA_CCR_TEIE_Pos       (3U)

+#define BDMA_CCR_TEIE_Msk       (0x1UL << BDMA_CCR_TEIE_Pos)                   /*!< 0x00000008 */

+#define BDMA_CCR_TEIE           BDMA_CCR_TEIE_Msk                              /*!< Transfer error interrupt enable     */

+#define BDMA_CCR_DIR_Pos        (4U)

+#define BDMA_CCR_DIR_Msk        (0x1UL << BDMA_CCR_DIR_Pos)                    /*!< 0x00000010 */

+#define BDMA_CCR_DIR            BDMA_CCR_DIR_Msk                               /*!< Data transfer direction             */

+#define BDMA_CCR_CIRC_Pos       (5U)

+#define BDMA_CCR_CIRC_Msk       (0x1UL << BDMA_CCR_CIRC_Pos)                   /*!< 0x00000020 */

+#define BDMA_CCR_CIRC           BDMA_CCR_CIRC_Msk                              /*!< Circular mode                       */

+#define BDMA_CCR_PINC_Pos       (6U)

+#define BDMA_CCR_PINC_Msk       (0x1UL << BDMA_CCR_PINC_Pos)                   /*!< 0x00000040 */

+#define BDMA_CCR_PINC           BDMA_CCR_PINC_Msk                              /*!< Peripheral increment mode           */

+#define BDMA_CCR_MINC_Pos       (7U)

+#define BDMA_CCR_MINC_Msk       (0x1UL << BDMA_CCR_MINC_Pos)                   /*!< 0x00000080 */

+#define BDMA_CCR_MINC           BDMA_CCR_MINC_Msk                              /*!< Memory increment mode               */

+

+#define BDMA_CCR_PSIZE_Pos      (8U)

+#define BDMA_CCR_PSIZE_Msk      (0x3UL << BDMA_CCR_PSIZE_Pos)                  /*!< 0x00000300 */

+#define BDMA_CCR_PSIZE          BDMA_CCR_PSIZE_Msk                             /*!< PSIZE[1:0] bits (Peripheral size)   */

+#define BDMA_CCR_PSIZE_0        (0x1UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000100 */

+#define BDMA_CCR_PSIZE_1        (0x2UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000200 */

+

+#define BDMA_CCR_MSIZE_Pos      (10U)

+#define BDMA_CCR_MSIZE_Msk      (0x3UL << BDMA_CCR_MSIZE_Pos)                  /*!< 0x00000C00 */

+#define BDMA_CCR_MSIZE          BDMA_CCR_MSIZE_Msk                             /*!< MSIZE[1:0] bits (Memory size)       */

+#define BDMA_CCR_MSIZE_0        (0x1UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000400 */

+#define BDMA_CCR_MSIZE_1        (0x2UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000800 */

+

+#define BDMA_CCR_PL_Pos         (12U)

+#define BDMA_CCR_PL_Msk         (0x3UL << BDMA_CCR_PL_Pos)                     /*!< 0x00003000 */

+#define BDMA_CCR_PL             BDMA_CCR_PL_Msk                                /*!< PL[1:0] bits(Channel Priority level)*/

+#define BDMA_CCR_PL_0           (0x1UL << BDMA_CCR_PL_Pos)                      /*!< 0x00001000 */

+#define BDMA_CCR_PL_1           (0x2UL << BDMA_CCR_PL_Pos)                      /*!< 0x00002000 */

+

+#define BDMA_CCR_MEM2MEM_Pos    (14U)

+#define BDMA_CCR_MEM2MEM_Msk    (0x1UL << BDMA_CCR_MEM2MEM_Pos)                /*!< 0x00004000 */

+#define BDMA_CCR_MEM2MEM        BDMA_CCR_MEM2MEM_Msk                           /*!< Memory to memory mode               */

+#define BDMA_CCR_DBM_Pos        (15U)

+#define BDMA_CCR_DBM_Msk        (0x1UL << BDMA_CCR_DBM_Pos)                    /*!< 0x0000A000 */

+#define BDMA_CCR_DBM            BDMA_CCR_DBM_Msk                               /*!< Memory to memory mode               */

+#define BDMA_CCR_CT_Pos         (16U)

+#define BDMA_CCR_CT_Msk         (0x1UL << BDMA_CCR_CT_Pos)                     /*!< 0x00010000 */

+#define BDMA_CCR_CT             BDMA_CCR_CT_Msk                                /*!< Memory to memory mode               */

+

+/******************  Bit definition for BDMA_CNDTR register  *******************/

+#define BDMA_CNDTR_NDT_Pos      (0U)

+#define BDMA_CNDTR_NDT_Msk      (0xFFFFUL << BDMA_CNDTR_NDT_Pos)               /*!< 0x0000FFFF */

+#define BDMA_CNDTR_NDT          BDMA_CNDTR_NDT_Msk                             /*!< Number of data to Transfer          */

+

+/******************  Bit definition for BDMA_CPAR register  ********************/

+#define BDMA_CPAR_PA_Pos        (0U)

+#define BDMA_CPAR_PA_Msk        (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CPAR_PA            BDMA_CPAR_PA_Msk                               /*!< Peripheral Address                  */

+

+/******************  Bit definition for BDMA_CM0AR register  ********************/

+#define BDMA_CM0AR_MA_Pos        (0U)

+#define BDMA_CM0AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CM0AR_MA            BDMA_CM0AR_MA_Msk                               /*!< Memory Address                      */

+

+/******************  Bit definition for BDMA_CM1AR register  ********************/

+#define BDMA_CM1AR_MA_Pos        (0U)

+#define BDMA_CM1AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CM1AR_MA            BDMA_CM1AR_MA_Msk                               /*!< Memory Address                      */

+

+/******************************************************************************/

+/*                                                                            */

+/*                Ethernet MAC Registers bits definitions                     */

+/*                                                                            */

+/******************************************************************************/

+/* Bit definition for Ethernet MAC Configuration Register register */

+#define ETH_MACCR_ARP_Pos                             (31U)

+#define ETH_MACCR_ARP_Msk                             (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */

+#define ETH_MACCR_ARP                                 ETH_MACCR_ARP_Msk        /* ARP Offload Enable */

+#define ETH_MACCR_SARC_Pos                            (28U)

+#define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */

+#define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */

+#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */

+#define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)

+#define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */

+#define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */

+#define ETH_MACCR_SARC_INSADDR1_Pos                   (29U)

+#define ETH_MACCR_SARC_INSADDR1_Msk                   (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */

+#define ETH_MACCR_SARC_INSADDR1                       ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */

+#define ETH_MACCR_SARC_REPADDR0_Pos                   (28U)

+#define ETH_MACCR_SARC_REPADDR0_Msk                   (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */

+#define ETH_MACCR_SARC_REPADDR0                       ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */

+#define ETH_MACCR_SARC_REPADDR1_Pos                   (28U)

+#define ETH_MACCR_SARC_REPADDR1_Msk                   (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */

+#define ETH_MACCR_SARC_REPADDR1                       ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */

+#define ETH_MACCR_IPC_Pos                             (27U)

+#define ETH_MACCR_IPC_Msk                             (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */

+#define ETH_MACCR_IPC                                 ETH_MACCR_IPC_Msk        /* Checksum Offload */

+#define ETH_MACCR_IPG_Pos                             (24U)

+#define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */

+#define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */

+#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */

+#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */

+#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */

+#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */

+#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */

+#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */

+#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */

+#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */

+#define ETH_MACCR_GPSLCE_Pos                          (23U)

+#define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */

+#define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */

+#define ETH_MACCR_S2KP_Pos                            (22U)

+#define ETH_MACCR_S2KP_Msk                            (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */

+#define ETH_MACCR_S2KP                                ETH_MACCR_S2KP_Msk       /* IEEE 802.3as Support for 2K Packets */

+#define ETH_MACCR_CST_Pos                             (21U)

+#define ETH_MACCR_CST_Msk                             (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */

+#define ETH_MACCR_CST                                 ETH_MACCR_CST_Msk        /* CRC stripping for Type packets */

+#define ETH_MACCR_ACS_Pos                             (20U)

+#define ETH_MACCR_ACS_Msk                             (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */

+#define ETH_MACCR_ACS                                 ETH_MACCR_ACS_Msk        /* Automatic Pad or CRC Stripping */

+#define ETH_MACCR_WD_Pos                              (19U)

+#define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */

+#define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */

+#define ETH_MACCR_JD_Pos                              (17U)

+#define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */

+#define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */

+#define ETH_MACCR_JE_Pos                              (16U)

+#define ETH_MACCR_JE_Msk                              (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */

+#define ETH_MACCR_JE                                  ETH_MACCR_JE_Msk         /* Jumbo Packet Enable */

+#define ETH_MACCR_FES_Pos                             (14U)

+#define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */

+#define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */

+#define ETH_MACCR_DM_Pos                              (13U)

+#define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */

+#define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */

+#define ETH_MACCR_LM_Pos                              (12U)

+#define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */

+#define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */

+#define ETH_MACCR_ECRSFD_Pos                          (11U)

+#define ETH_MACCR_ECRSFD_Msk                          (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */

+#define ETH_MACCR_ECRSFD                              ETH_MACCR_ECRSFD_Msk     /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */

+#define ETH_MACCR_DO_Pos                              (10U)

+#define ETH_MACCR_DO_Msk                              (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */

+#define ETH_MACCR_DO                                  ETH_MACCR_DO_Msk         /* Disable Receive own  */

+#define ETH_MACCR_DCRS_Pos                            (9U)

+#define ETH_MACCR_DCRS_Msk                            (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */

+#define ETH_MACCR_DCRS                                ETH_MACCR_DCRS_Msk       /* Disable Carrier Sense During Transmission */

+#define ETH_MACCR_DR_Pos                              (8U)

+#define ETH_MACCR_DR_Msk                              (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */

+#define ETH_MACCR_DR                                  ETH_MACCR_DR_Msk         /* Disable Retry */

+#define ETH_MACCR_BL_Pos                              (5U)

+#define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */

+#define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit mask */

+#define ETH_MACCR_BL_10                               (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */

+#define ETH_MACCR_BL_8                                (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */

+#define ETH_MACCR_BL_4                                (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */

+#define ETH_MACCR_BL_1                                (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */

+#define ETH_MACCR_DC_Pos                              (4U)

+#define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */

+#define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */

+#define ETH_MACCR_PRELEN_Pos                          (2U)

+#define ETH_MACCR_PRELEN_Msk                          (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */

+#define ETH_MACCR_PRELEN                              ETH_MACCR_PRELEN_Msk     /* Preamble Length for Transmit packets */

+#define ETH_MACCR_PRELEN_7                            (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */

+#define ETH_MACCR_PRELEN_5                            (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */

+#define ETH_MACCR_PRELEN_3                            (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */

+#define ETH_MACCR_TE_Pos                              (1U)

+#define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */

+#define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */

+#define ETH_MACCR_RE_Pos                              (0U)

+#define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */

+#define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */

+

+/* Bit definition for Ethernet MAC Extended Configuration Register register */

+#define ETH_MACECR_EIPG_Pos                           (25U)

+#define ETH_MACECR_EIPG_Msk                           (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */

+#define ETH_MACECR_EIPG                               ETH_MACECR_EIPG_Msk      /* Extended Inter-Packet Gap */

+#define ETH_MACECR_EIPGEN_Pos                         (24U)

+#define ETH_MACECR_EIPGEN_Msk                         (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */

+#define ETH_MACECR_EIPGEN                             ETH_MACECR_EIPGEN_Msk    /* Extended Inter-Packet Gap Enable */

+#define ETH_MACECR_USP_Pos                            (18U)

+#define ETH_MACECR_USP_Msk                            (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */

+#define ETH_MACECR_USP                                ETH_MACECR_USP_Msk       /* Unicast Slow Protocol Packet Detect */

+#define ETH_MACECR_SPEN_Pos                           (17U)

+#define ETH_MACECR_SPEN_Msk                           (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */

+#define ETH_MACECR_SPEN                               ETH_MACECR_SPEN_Msk      /* Slow Protocol Detection Enable */

+#define ETH_MACECR_DCRCC_Pos                          (16U)

+#define ETH_MACECR_DCRCC_Msk                          (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */

+#define ETH_MACECR_DCRCC                              ETH_MACECR_DCRCC_Msk     /* Disable CRC Checking for Received Packets */

+#define ETH_MACECR_GPSL_Pos                           (0U)

+#define ETH_MACECR_GPSL_Msk                           (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */

+#define ETH_MACECR_GPSL                               ETH_MACECR_GPSL_Msk      /* Giant Packet Size Limit */

+

+/* Bit definition for Ethernet MAC Packet Filter Register */

+#define ETH_MACPFR_RA_Pos                             (31U)

+#define ETH_MACPFR_RA_Msk                             (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */

+#define ETH_MACPFR_RA                                 ETH_MACPFR_RA_Msk        /* Receive all */

+#define ETH_MACPFR_DNTU_Pos                           (21U)

+#define ETH_MACPFR_DNTU_Msk                           (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */

+#define ETH_MACPFR_DNTU                               ETH_MACPFR_DNTU_Msk      /* Drop Non-TCP/UDP over IP Packets */

+#define ETH_MACPFR_IPFE_Pos                           (20U)

+#define ETH_MACPFR_IPFE_Msk                           (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */

+#define ETH_MACPFR_IPFE                               ETH_MACPFR_IPFE_Msk      /* Layer 3 and Layer 4 Filter Enable */

+#define ETH_MACPFR_VTFE_Pos                           (16U)

+#define ETH_MACPFR_VTFE_Msk                           (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */

+#define ETH_MACPFR_VTFE                               ETH_MACPFR_VTFE_Msk      /* VLAN Tag Filter Enable */

+#define ETH_MACPFR_HPF_Pos                            (10U)

+#define ETH_MACPFR_HPF_Msk                            (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */

+#define ETH_MACPFR_HPF                                ETH_MACPFR_HPF_Msk       /* Hash or perfect filter */

+#define ETH_MACPFR_SAF_Pos                            (9U)

+#define ETH_MACPFR_SAF_Msk                            (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */

+#define ETH_MACPFR_SAF                                ETH_MACPFR_SAF_Msk       /* Source address filter enable */

+#define ETH_MACPFR_SAIF_Pos                           (8U)

+#define ETH_MACPFR_SAIF_Msk                           (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */

+#define ETH_MACPFR_SAIF                               ETH_MACPFR_SAIF_Msk      /* SA inverse filtering */

+#define ETH_MACPFR_PCF_Pos                            (6U)

+#define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */

+#define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */

+#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */

+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)

+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */

+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */

+#define ETH_MACPFR_PCF_FORWARDALL_Pos                 (7U)

+#define ETH_MACPFR_PCF_FORWARDALL_Msk                 (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */

+#define ETH_MACPFR_PCF_FORWARDALL                     ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */

+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos    (6U)

+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk    (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */

+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER        ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */

+#define ETH_MACPFR_DBF_Pos                            (5U)

+#define ETH_MACPFR_DBF_Msk                            (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */

+#define ETH_MACPFR_DBF                                ETH_MACPFR_DBF_Msk       /* Disable Broadcast Packets */

+#define ETH_MACPFR_PM_Pos                             (4U)

+#define ETH_MACPFR_PM_Msk                             (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */

+#define ETH_MACPFR_PM                                 ETH_MACPFR_PM_Msk        /* Pass all mutlicast */

+#define ETH_MACPFR_DAIF_Pos                           (3U)

+#define ETH_MACPFR_DAIF_Msk                           (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */

+#define ETH_MACPFR_DAIF                               ETH_MACPFR_DAIF_Msk      /* DA Inverse filtering */

+#define ETH_MACPFR_HMC_Pos                            (2U)

+#define ETH_MACPFR_HMC_Msk                            (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */

+#define ETH_MACPFR_HMC                                ETH_MACPFR_HMC_Msk       /* Hash multicast */

+#define ETH_MACPFR_HUC_Pos                            (1U)

+#define ETH_MACPFR_HUC_Msk                            (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */

+#define ETH_MACPFR_HUC                                ETH_MACPFR_HUC_Msk       /* Hash unicast */

+#define ETH_MACPFR_PR_Pos                             (0U)

+#define ETH_MACPFR_PR_Msk                             (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */

+#define ETH_MACPFR_PR                                 ETH_MACPFR_PR_Msk        /* Promiscuous mode */

+

+/* Bit definition for Ethernet MAC Watchdog Timeout Register */

+#define ETH_MACWTR_PWE_Pos                            (8U)

+#define ETH_MACWTR_PWE_Msk                            (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */

+#define ETH_MACWTR_PWE                                ETH_MACWTR_PWE_Msk       /* Programmable Watchdog Enable */

+#define ETH_MACWTR_WTO_Pos                            (0U)

+#define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */

+#define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */

+#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/

+#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */

+#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */

+#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */

+#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */

+#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */

+#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */

+#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */

+#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */

+#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */

+#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */

+#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */

+#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */

+#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */

+#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */

+

+/* Bit definition for Ethernet MAC Hash Table High Register */

+#define ETH_MACHTHR_HTH_Pos                           (0U)

+#define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */

+

+/* Bit definition for Ethernet MAC Hash Table Low Register */

+#define ETH_MACHTLR_HTL_Pos                           (0U)

+#define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */

+

+/* Bit definition for Ethernet MAC VLAN Tag Register */

+#define ETH_MACVTR_EIVLRXS_Pos                        (31U)

+#define ETH_MACVTR_EIVLRXS_Msk                        (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */

+#define ETH_MACVTR_EIVLRXS                            ETH_MACVTR_EIVLRXS_Msk   /* Enable Inner VLAN Tag in Rx Status */

+#define ETH_MACVTR_EIVLS_Pos                          (28U)

+#define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */

+#define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */

+#define ETH_MACVTR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */

+#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)

+#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */

+#define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */

+#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos             (29U)

+#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk             (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */

+#define ETH_MACVTR_EIVLS_STRIPIFFAILS                 ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */

+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos              (28U)

+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk              (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */

+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP                  ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */

+#define ETH_MACVTR_ERIVLT_Pos                         (27U)

+#define ETH_MACVTR_ERIVLT_Msk                         (0x1UL << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */

+#define ETH_MACVTR_ERIVLT                             ETH_MACVTR_ERIVLT_Msk    /* Enable Inner VLAN Tag */

+#define ETH_MACVTR_EDVLP_Pos                          (26U)

+#define ETH_MACVTR_EDVLP_Msk                          (0x1UL << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */

+#define ETH_MACVTR_EDVLP                              ETH_MACVTR_EDVLP_Msk     /* Enable Double VLAN Processing */

+#define ETH_MACVTR_VTHM_Pos                           (25U)

+#define ETH_MACVTR_VTHM_Msk                           (0x1UL << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */

+#define ETH_MACVTR_VTHM                               ETH_MACVTR_VTHM_Msk      /* VLAN Tag Hash Table Match Enable */

+#define ETH_MACVTR_EVLRXS_Pos                         (24U)

+#define ETH_MACVTR_EVLRXS_Msk                         (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */

+#define ETH_MACVTR_EVLRXS                             ETH_MACVTR_EVLRXS_Msk    /* Enable VLAN Tag in Rx status */

+#define ETH_MACVTR_EVLS_Pos                           (21U)

+#define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */

+#define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */

+#define ETH_MACVTR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */

+#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)

+#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */

+#define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */

+#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos              (22U)

+#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk              (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */

+#define ETH_MACVTR_EVLS_STRIPIFFAILS                  ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */

+#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos               (21U)

+#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk               (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */

+#define ETH_MACVTR_EVLS_ALWAYSSTRIP                   ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */

+#define ETH_MACVTR_DOVLTC_Pos                         (20U)

+#define ETH_MACVTR_DOVLTC_Msk                         (0x1UL << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */

+#define ETH_MACVTR_DOVLTC                             ETH_MACVTR_DOVLTC_Msk    /* Disable VLAN Type Check */

+#define ETH_MACVTR_ERSVLM_Pos                         (19U)

+#define ETH_MACVTR_ERSVLM_Msk                         (0x1UL << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */

+#define ETH_MACVTR_ERSVLM                             ETH_MACVTR_ERSVLM_Msk    /* Enable Receive S-VLAN Match */

+#define ETH_MACVTR_ESVL_Pos                           (18U)

+#define ETH_MACVTR_ESVL_Msk                           (0x1UL << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */

+#define ETH_MACVTR_ESVL                               ETH_MACVTR_ESVL_Msk      /* Enable S-VLAN */

+#define ETH_MACVTR_VTIM_Pos                           (17U)

+#define ETH_MACVTR_VTIM_Msk                           (0x1UL << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */

+#define ETH_MACVTR_VTIM                               ETH_MACVTR_VTIM_Msk      /* VLAN Tag Inverse Match Enable */

+#define ETH_MACVTR_ETV_Pos                            (16U)

+#define ETH_MACVTR_ETV_Msk                            (0x1UL << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */

+#define ETH_MACVTR_ETV                                ETH_MACVTR_ETV_Msk       /* Enable 12-Bit VLAN Tag Comparison */

+#define ETH_MACVTR_VL_Pos                             (0U)

+#define ETH_MACVTR_VL_Msk                             (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */

+#define ETH_MACVTR_VL                                 ETH_MACVTR_VL_Msk        /* VLAN Tag Identifier for Receive Packets */

+#define ETH_MACVTR_VL_UP_Pos                          (13U)

+#define ETH_MACVTR_VL_UP_Msk                          (0x7UL << ETH_MACVTR_VL_UP_Pos) /*!< 0x0000E000 */

+#define ETH_MACVTR_VL_UP                              ETH_MACVTR_VL_UP_Msk     /* User Priority */

+#define ETH_MACVTR_VL_CFIDEI_Pos                      (12U)

+#define ETH_MACVTR_VL_CFIDEI_Msk                      (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos) /*!< 0x00001000 */

+#define ETH_MACVTR_VL_CFIDEI                          ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */

+#define ETH_MACVTR_VL_VID_Pos                         (0U)

+#define ETH_MACVTR_VL_VID_Msk                         (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */

+#define ETH_MACVTR_VL_VID                             ETH_MACVTR_VL_VID_Msk    /* VLAN Identifier field of VLAN tag */

+

+/* Bit definition for Ethernet MAC VLAN Hash Table Register */

+#define ETH_MACVHTR_VLHT_Pos                          (0U)

+#define ETH_MACVHTR_VLHT_Msk                          (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACVHTR_VLHT                              ETH_MACVHTR_VLHT_Msk     /* VLAN Hash Table */

+

+/* Bit definition for Ethernet MAC VLAN Incl Register */

+#define ETH_MACVIR_VLTI_Pos                           (20U)

+#define ETH_MACVIR_VLTI_Msk                           (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */

+#define ETH_MACVIR_VLTI                               ETH_MACVIR_VLTI_Msk      /* VLAN Tag Input */

+#define ETH_MACVIR_CSVL_Pos                           (19U)

+#define ETH_MACVIR_CSVL_Msk                           (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */

+#define ETH_MACVIR_CSVL                               ETH_MACVIR_CSVL_Msk      /* C-VLAN or S-VLAN */

+#define ETH_MACVIR_VLP_Pos                            (18U)

+#define ETH_MACVIR_VLP_Msk                            (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */

+#define ETH_MACVIR_VLP                                ETH_MACVIR_VLP_Msk       /* VLAN Priority Control */

+#define ETH_MACVIR_VLC_Pos                            (16U)

+#define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */

+#define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */

+#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */

+#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)

+#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */

+#define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */

+#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos              (17U)

+#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */

+#define ETH_MACVIR_VLC_VLANTAGINSERT                  ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */

+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos             (16U)

+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk             (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */

+#define ETH_MACVIR_VLC_VLANTAGREPLACE                 ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */

+#define ETH_MACVIR_VLT_Pos                            (0U)

+#define ETH_MACVIR_VLT_Msk                            (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACVIR_VLT                                ETH_MACVIR_VLT_Msk       /* VLAN Tag for Transmit Packets */

+#define ETH_MACVIR_VLT_UP_Pos                         (13U)

+#define ETH_MACVIR_VLT_UP_Msk                         (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */

+#define ETH_MACVIR_VLT_UP                             ETH_MACVIR_VLT_UP_Msk    /* User Priority */

+#define ETH_MACVIR_VLT_CFIDEI_Pos                     (12U)

+#define ETH_MACVIR_VLT_CFIDEI_Msk                     (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */

+#define ETH_MACVIR_VLT_CFIDEI                         ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */

+#define ETH_MACVIR_VLT_VID_Pos                        (0U)

+#define ETH_MACVIR_VLT_VID_Msk                        (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */

+#define ETH_MACVIR_VLT_VID                            ETH_MACVIR_VLT_VID_Msk   /* VLAN Identifier field of VLAN tag */

+

+/* Bit definition for Ethernet MAC Inner_VLAN Incl Register */

+#define ETH_MACIVIR_VLTI_Pos                          (20U)

+#define ETH_MACIVIR_VLTI_Msk                          (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */

+#define ETH_MACIVIR_VLTI                              ETH_MACIVIR_VLTI_Msk     /* VLAN Tag Input */

+#define ETH_MACIVIR_CSVL_Pos                          (19U)

+#define ETH_MACIVIR_CSVL_Msk                          (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */

+#define ETH_MACIVIR_CSVL                              ETH_MACIVIR_CSVL_Msk     /* C-VLAN or S-VLAN */

+#define ETH_MACIVIR_VLP_Pos                           (18U)

+#define ETH_MACIVIR_VLP_Msk                           (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */

+#define ETH_MACIVIR_VLP                               ETH_MACIVIR_VLP_Msk      /* VLAN Priority Control */

+#define ETH_MACIVIR_VLC_Pos                           (16U)

+#define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */

+#define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */

+#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */

+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)

+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */

+#define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */

+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos             (17U)

+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */

+#define ETH_MACIVIR_VLC_VLANTAGINSERT                 ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */

+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos            (16U)

+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk            (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */

+#define ETH_MACIVIR_VLC_VLANTAGREPLACE                ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */

+#define ETH_MACIVIR_VLT_Pos                           (0U)

+#define ETH_MACIVIR_VLT_Msk                           (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACIVIR_VLT                               ETH_MACIVIR_VLT_Msk      /* VLAN Tag for Transmit Packets */

+#define ETH_MACIVIR_VLT_UP_Pos                        (13U)

+#define ETH_MACIVIR_VLT_UP_Msk                        (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */

+#define ETH_MACIVIR_VLT_UP                            ETH_MACIVIR_VLT_UP_Msk   /* User Priority */

+#define ETH_MACIVIR_VLT_CFIDEI_Pos                    (12U)

+#define ETH_MACIVIR_VLT_CFIDEI_Msk                    (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */

+#define ETH_MACIVIR_VLT_CFIDEI                        ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */

+#define ETH_MACIVIR_VLT_VID_Pos                       (0U)

+#define ETH_MACIVIR_VLT_VID_Msk                       (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */

+#define ETH_MACIVIR_VLT_VID                           ETH_MACIVIR_VLT_VID_Msk  /* VLAN Identifier field of VLAN tag */

+

+/* Bit definition for Ethernet MAC Tx Flow Ctrl Register */

+#define ETH_MACTFCR_PT_Pos                            (16U)

+#define ETH_MACTFCR_PT_Msk                            (0xFFFFUL << ETH_MACTFCR_PT_Pos) /*!< 0xFFFF0000 */

+#define ETH_MACTFCR_PT                                ETH_MACTFCR_PT_Msk       /* Pause Time */

+#define ETH_MACTFCR_DZPQ_Pos                          (7U)

+#define ETH_MACTFCR_DZPQ_Msk                          (0x1UL << ETH_MACTFCR_DZPQ_Pos) /*!< 0x00000080 */

+#define ETH_MACTFCR_DZPQ                              ETH_MACTFCR_DZPQ_Msk     /* Disable Zero-Quanta Pause */

+#define ETH_MACTFCR_PLT_Pos                           (4U)

+#define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */

+#define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */

+#define ETH_MACTFCR_PLT_MINUS4                        ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */

+#define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)

+#define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */

+#define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */

+#define ETH_MACTFCR_PLT_MINUS36_Pos                   (5U)

+#define ETH_MACTFCR_PLT_MINUS36_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */

+#define ETH_MACTFCR_PLT_MINUS36                       ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */

+#define ETH_MACTFCR_PLT_MINUS144_Pos                  (4U)

+#define ETH_MACTFCR_PLT_MINUS144_Msk                  (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */

+#define ETH_MACTFCR_PLT_MINUS144                      ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */

+#define ETH_MACTFCR_PLT_MINUS256_Pos                  (6U)

+#define ETH_MACTFCR_PLT_MINUS256_Msk                  (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */

+#define ETH_MACTFCR_PLT_MINUS256                      ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */

+#define ETH_MACTFCR_PLT_MINUS512_Pos                  (4U)

+#define ETH_MACTFCR_PLT_MINUS512_Msk                  (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */

+#define ETH_MACTFCR_PLT_MINUS512                      ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */

+#define ETH_MACTFCR_TFE_Pos                           (1U)

+#define ETH_MACTFCR_TFE_Msk                           (0x1UL << ETH_MACTFCR_TFE_Pos) /*!< 0x00000002 */

+#define ETH_MACTFCR_TFE                               ETH_MACTFCR_TFE_Msk      /* Transmit Flow Control Enable */

+#define ETH_MACTFCR_FCB_Pos                           (0U)

+#define ETH_MACTFCR_FCB_Msk                           (0x1UL << ETH_MACTFCR_FCB_Pos) /*!< 0x00000001 */

+#define ETH_MACTFCR_FCB                               ETH_MACTFCR_FCB_Msk      /* Flow Control Busy or Backpressure Activate */

+

+/* Bit definition for Ethernet MAC Rx Flow Ctrl Register */

+#define ETH_MACRFCR_UP_Pos                            (1U)

+#define ETH_MACRFCR_UP_Msk                            (0x1UL << ETH_MACRFCR_UP_Pos) /*!< 0x00000002 */

+#define ETH_MACRFCR_UP                                ETH_MACRFCR_UP_Msk       /* Unicast Pause Packet Detect */

+#define ETH_MACRFCR_RFE_Pos                           (0U)

+#define ETH_MACRFCR_RFE_Msk                           (0x1UL << ETH_MACRFCR_RFE_Pos) /*!< 0x00000001 */

+#define ETH_MACRFCR_RFE                               ETH_MACRFCR_RFE_Msk      /* Receive Flow Control Enable */

+

+/* Bit definition for Ethernet MAC Interrupt Status Register */

+#define ETH_MACISR_RXSTSIS_Pos                        (14U)

+#define ETH_MACISR_RXSTSIS_Msk                        (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */

+#define ETH_MACISR_RXSTSIS                            ETH_MACISR_RXSTSIS_Msk   /* Receive Status Interrupt */

+#define ETH_MACISR_TXSTSIS_Pos                        (13U)

+#define ETH_MACISR_TXSTSIS_Msk                        (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */

+#define ETH_MACISR_TXSTSIS                            ETH_MACISR_TXSTSIS_Msk   /* Transmit Status Interrupt */

+#define ETH_MACISR_TSIS_Pos                           (12U)

+#define ETH_MACISR_TSIS_Msk                           (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */

+#define ETH_MACISR_TSIS                               ETH_MACISR_TSIS_Msk      /* Timestamp Interrupt Status */

+#define ETH_MACISR_MMCTXIS_Pos                        (10U)

+#define ETH_MACISR_MMCTXIS_Msk                        (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */

+#define ETH_MACISR_MMCTXIS                            ETH_MACISR_MMCTXIS_Msk   /* MMC Transmit Interrupt Status */

+#define ETH_MACISR_MMCRXIS_Pos                        (9U)

+#define ETH_MACISR_MMCRXIS_Msk                        (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */

+#define ETH_MACISR_MMCRXIS                            ETH_MACISR_MMCRXIS_Msk   /* MMC Receive Interrupt Status */

+#define ETH_MACISR_MMCIS_Pos                          (8U)

+#define ETH_MACISR_MMCIS_Msk                          (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */

+#define ETH_MACISR_MMCIS                              ETH_MACISR_MMCIS_Msk     /* MMC Interrupt Status */

+#define ETH_MACISR_LPIIS_Pos                          (5U)

+#define ETH_MACISR_LPIIS_Msk                          (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */

+#define ETH_MACISR_LPIIS                              ETH_MACISR_LPIIS_Msk     /* LPI Interrupt Status */

+#define ETH_MACISR_PMTIS_Pos                          (4U)

+#define ETH_MACISR_PMTIS_Msk                          (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */

+#define ETH_MACISR_PMTIS                              ETH_MACISR_PMTIS_Msk     /* PMT Interrupt Status */

+#define ETH_MACISR_PHYIS_Pos                          (3U)

+#define ETH_MACISR_PHYIS_Msk                          (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */

+#define ETH_MACISR_PHYIS                              ETH_MACISR_PHYIS_Msk     /* PHY Interrupt */

+

+/* Bit definition for Ethernet MAC Interrupt Enable Register */

+#define ETH_MACIER_RXSTSIE_Pos                        (14U)

+#define ETH_MACIER_RXSTSIE_Msk                        (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */

+#define ETH_MACIER_RXSTSIE                            ETH_MACIER_RXSTSIE_Msk   /* Receive Status Interrupt Enable */

+#define ETH_MACIER_TXSTSIE_Pos                        (13U)

+#define ETH_MACIER_TXSTSIE_Msk                        (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */

+#define ETH_MACIER_TXSTSIE                            ETH_MACIER_TXSTSIE_Msk   /* Transmit Status Interrupt Enable */

+#define ETH_MACIER_TSIE_Pos                           (12U)

+#define ETH_MACIER_TSIE_Msk                           (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */

+#define ETH_MACIER_TSIE                               ETH_MACIER_TSIE_Msk      /* Timestamp Interrupt Enable */

+#define ETH_MACIER_LPIIE_Pos                          (5U)

+#define ETH_MACIER_LPIIE_Msk                          (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */

+#define ETH_MACIER_LPIIE                              ETH_MACIER_LPIIE_Msk     /* LPI Interrupt Enable */

+#define ETH_MACIER_PMTIE_Pos                          (4U)

+#define ETH_MACIER_PMTIE_Msk                          (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */

+#define ETH_MACIER_PMTIE                              ETH_MACIER_PMTIE_Msk     /* PMT Interrupt Enable */

+#define ETH_MACIER_PHYIE_Pos                          (3U)

+#define ETH_MACIER_PHYIE_Msk                          (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */

+#define ETH_MACIER_PHYIE                              ETH_MACIER_PHYIE_Msk     /* PHY Interrupt Enable */

+

+/* Bit definition for Ethernet MAC Rx Tx Status Register */

+#define ETH_MACRXTXSR_RWT_Pos                         (8U)

+#define ETH_MACRXTXSR_RWT_Msk                         (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */

+#define ETH_MACRXTXSR_RWT                             ETH_MACRXTXSR_RWT_Msk    /* Receive Watchdog Timeout */

+#define ETH_MACRXTXSR_EXCOL_Pos                       (5U)

+#define ETH_MACRXTXSR_EXCOL_Msk                       (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */

+#define ETH_MACRXTXSR_EXCOL                           ETH_MACRXTXSR_EXCOL_Msk  /* Excessive Collisions */

+#define ETH_MACRXTXSR_LCOL_Pos                        (4U)

+#define ETH_MACRXTXSR_LCOL_Msk                        (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */

+#define ETH_MACRXTXSR_LCOL                            ETH_MACRXTXSR_LCOL_Msk   /* Late Collision */

+#define ETH_MACRXTXSR_EXDEF_Pos                       (3U)

+#define ETH_MACRXTXSR_EXDEF_Msk                       (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */

+#define ETH_MACRXTXSR_EXDEF                           ETH_MACRXTXSR_EXDEF_Msk  /* Excessive Deferral */

+#define ETH_MACRXTXSR_LCARR_Pos                       (2U)

+#define ETH_MACRXTXSR_LCARR_Msk                       (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */

+#define ETH_MACRXTXSR_LCARR                           ETH_MACRXTXSR_LCARR_Msk  /* Loss of Carrier */

+#define ETH_MACRXTXSR_NCARR_Pos                       (1U)

+#define ETH_MACRXTXSR_NCARR_Msk                       (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */

+#define ETH_MACRXTXSR_NCARR                           ETH_MACRXTXSR_NCARR_Msk  /* No Carrier */

+#define ETH_MACRXTXSR_TJT_Pos                         (0U)

+#define ETH_MACRXTXSR_TJT_Msk                         (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */

+#define ETH_MACRXTXSR_TJT                             ETH_MACRXTXSR_TJT_Msk    /* Transmit Jabber Timeout */

+

+/* Bit definition for Ethernet MAC PMT Control Status Register */

+#define ETH_MACPCSR_RWKFILTRST_Pos                    (31U)

+#define ETH_MACPCSR_RWKFILTRST_Msk                    (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */

+#define ETH_MACPCSR_RWKFILTRST                        ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */

+#define ETH_MACPCSR_RWKPTR_Pos                        (24U)

+#define ETH_MACPCSR_RWKPTR_Msk                        (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */

+#define ETH_MACPCSR_RWKPTR                            ETH_MACPCSR_RWKPTR_Msk   /* Remote Wake-up FIFO Pointer */

+#define ETH_MACPCSR_RWKPFE_Pos                        (10U)

+#define ETH_MACPCSR_RWKPFE_Msk                        (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */

+#define ETH_MACPCSR_RWKPFE                            ETH_MACPCSR_RWKPFE_Msk   /* Remote Wake-up Packet Forwarding Enable */

+#define ETH_MACPCSR_GLBLUCAST_Pos                     (9U)

+#define ETH_MACPCSR_GLBLUCAST_Msk                     (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */

+#define ETH_MACPCSR_GLBLUCAST                         ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */

+#define ETH_MACPCSR_RWKPRCVD_Pos                      (6U)

+#define ETH_MACPCSR_RWKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */

+#define ETH_MACPCSR_RWKPRCVD                          ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */

+#define ETH_MACPCSR_MGKPRCVD_Pos                      (5U)

+#define ETH_MACPCSR_MGKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */

+#define ETH_MACPCSR_MGKPRCVD                          ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */

+#define ETH_MACPCSR_RWKPKTEN_Pos                      (2U)

+#define ETH_MACPCSR_RWKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */

+#define ETH_MACPCSR_RWKPKTEN                          ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */

+#define ETH_MACPCSR_MGKPKTEN_Pos                      (1U)

+#define ETH_MACPCSR_MGKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */

+#define ETH_MACPCSR_MGKPKTEN                          ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */

+#define ETH_MACPCSR_PWRDWN_Pos                        (0U)

+#define ETH_MACPCSR_PWRDWN_Msk                        (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */

+#define ETH_MACPCSR_PWRDWN                            ETH_MACPCSR_PWRDWN_Msk   /* Power Down */

+

+/* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */

+#define ETH_MACRWUPFR_D_Pos                           (0U)

+#define ETH_MACRWUPFR_D_Msk                           (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACRWUPFR_D                               ETH_MACRWUPFR_D_Msk      /* Wake-up Packet filter register data */

+

+/* Bit definition for Ethernet MAC LPI Control Status Register */

+#define ETH_MACLCSR_LPITCSE_Pos                       (21U)

+#define ETH_MACLCSR_LPITCSE_Msk                       (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */

+#define ETH_MACLCSR_LPITCSE                           ETH_MACLCSR_LPITCSE_Msk  /* LPI Tx Clock Stop Enable */

+#define ETH_MACLCSR_LPITE_Pos                         (20U)

+#define ETH_MACLCSR_LPITE_Msk                         (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */

+#define ETH_MACLCSR_LPITE                             ETH_MACLCSR_LPITE_Msk    /* LPI Timer Enable */

+#define ETH_MACLCSR_LPITXA_Pos                        (19U)

+#define ETH_MACLCSR_LPITXA_Msk                        (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */

+#define ETH_MACLCSR_LPITXA                            ETH_MACLCSR_LPITXA_Msk   /* LPI Tx Automate */

+#define ETH_MACLCSR_PLS_Pos                           (17U)

+#define ETH_MACLCSR_PLS_Msk                           (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */

+#define ETH_MACLCSR_PLS                               ETH_MACLCSR_PLS_Msk      /* PHY Link Status */

+#define ETH_MACLCSR_LPIEN_Pos                         (16U)

+#define ETH_MACLCSR_LPIEN_Msk                         (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */

+#define ETH_MACLCSR_LPIEN                             ETH_MACLCSR_LPIEN_Msk    /* LPI Enable */

+#define ETH_MACLCSR_RLPIST_Pos                        (9U)

+#define ETH_MACLCSR_RLPIST_Msk                        (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */

+#define ETH_MACLCSR_RLPIST                            ETH_MACLCSR_RLPIST_Msk   /* Receive LPI State */

+#define ETH_MACLCSR_TLPIST_Pos                        (8U)

+#define ETH_MACLCSR_TLPIST_Msk                        (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */

+#define ETH_MACLCSR_TLPIST                            ETH_MACLCSR_TLPIST_Msk   /* Transmit LPI State */

+#define ETH_MACLCSR_RLPIEX_Pos                        (3U)

+#define ETH_MACLCSR_RLPIEX_Msk                        (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */

+#define ETH_MACLCSR_RLPIEX                            ETH_MACLCSR_RLPIEX_Msk   /* Receive LPI Exit */

+#define ETH_MACLCSR_RLPIEN_Pos                        (2U)

+#define ETH_MACLCSR_RLPIEN_Msk                        (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */

+#define ETH_MACLCSR_RLPIEN                            ETH_MACLCSR_RLPIEN_Msk   /* Receive LPI Entry */

+#define ETH_MACLCSR_TLPIEX_Pos                        (1U)

+#define ETH_MACLCSR_TLPIEX_Msk                        (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */

+#define ETH_MACLCSR_TLPIEX                            ETH_MACLCSR_TLPIEX_Msk   /* Transmit LPI Exit */

+#define ETH_MACLCSR_TLPIEN_Pos                        (0U)

+#define ETH_MACLCSR_TLPIEN_Msk                        (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */

+#define ETH_MACLCSR_TLPIEN                            ETH_MACLCSR_TLPIEN_Msk   /* Transmit LPI Entry */

+

+/* Bit definition for Ethernet MAC LPI Timers Control Register */

+#define ETH_MACLTCR_LST_Pos                           (16U)

+#define ETH_MACLTCR_LST_Msk                           (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */

+#define ETH_MACLTCR_LST                               ETH_MACLTCR_LST_Msk      /* LPI LS TIMER */

+#define ETH_MACLTCR_TWT_Pos                           (0U)

+#define ETH_MACLTCR_TWT_Msk                           (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACLTCR_TWT                               ETH_MACLTCR_TWT_Msk      /* LPI TW TIMER */

+

+/* Bit definition for Ethernet MAC LPI Entry Timer Register */

+#define ETH_MACLETR_LPIET_Pos                         (0U)

+#define ETH_MACLETR_LPIET_Msk                         (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */

+#define ETH_MACLETR_LPIET                             ETH_MACLETR_LPIET_Msk    /* LPI Entry Timer */

+

+/* Bit definition for Ethernet MAC 1US Tic Counter Register */

+#define ETH_MAC1USTCR_TIC1USCNTR_Pos                  (0U)

+#define ETH_MAC1USTCR_TIC1USCNTR_Msk                  (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */

+#define ETH_MAC1USTCR_TIC1USCNTR                      ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */

+

+/* Bit definition for Ethernet MAC Version Register */

+#define ETH_MACVR_USERVER_Pos                         (8U)

+#define ETH_MACVR_USERVER_Msk                         (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */

+#define ETH_MACVR_USERVER                             ETH_MACVR_USERVER_Msk    /* User-defined Version */

+#define ETH_MACVR_SNPSVER_Pos                         (0U)

+#define ETH_MACVR_SNPSVER_Msk                         (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */

+#define ETH_MACVR_SNPSVER                             ETH_MACVR_SNPSVER_Msk    /* Synopsys-defined Version */

+

+/* Bit definition for Ethernet MAC Debug Register */

+#define ETH_MACDR_TFCSTS_Pos                          (17U)

+#define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */

+#define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */

+#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */

+#define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)

+#define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */

+#define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */

+#define ETH_MACDR_TFCSTS_GENERATEPCP_Pos              (18U)

+#define ETH_MACDR_TFCSTS_GENERATEPCP_Msk              (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */

+#define ETH_MACDR_TFCSTS_GENERATEPCP                  ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */

+#define ETH_MACDR_TFCSTS_TRASFERIP_Pos                (17U)

+#define ETH_MACDR_TFCSTS_TRASFERIP_Msk                (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */

+#define ETH_MACDR_TFCSTS_TRASFERIP                    ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */

+#define ETH_MACDR_TPESTS_Pos                          (16U)

+#define ETH_MACDR_TPESTS_Msk                          (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */

+#define ETH_MACDR_TPESTS                              ETH_MACDR_TPESTS_Msk     /* MAC Receive Packet Controller FIFO Status */

+#define ETH_MACDR_RFCFCSTS_Pos                        (1U)

+#define ETH_MACDR_RFCFCSTS_Msk                        (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */

+#define ETH_MACDR_RFCFCSTS                            ETH_MACDR_RFCFCSTS_Msk   /* MAC MII Transmit Protocol Engine Status */

+#define ETH_MACDR_RPESTS_Pos                          (0U)

+#define ETH_MACDR_RPESTS_Msk                          (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */

+#define ETH_MACDR_RPESTS                              ETH_MACDR_RPESTS_Msk     /* MAC MII Receive Protocol Engine Status */

+

+/* Bit definition for Ethernet MAC HW Feature0 Register */

+#define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)

+#define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */

+#define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */

+#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */

+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)

+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */

+#define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */

+#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos             (28U)

+#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk             (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos) /*!< 0x70000000 */

+#define ETH_MACHWF0R_ACTPHYSEL_REVMII                 ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */

+#define ETH_MACHWF0R_SAVLANINS_Pos                    (27U)

+#define ETH_MACHWF0R_SAVLANINS_Msk                    (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */

+#define ETH_MACHWF0R_SAVLANINS                        ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */

+#define ETH_MACHWF0R_TSSTSSEL_Pos                     (25U)

+#define ETH_MACHWF0R_TSSTSSEL_Msk                     (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */

+#define ETH_MACHWF0R_TSSTSSEL                         ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */

+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos            (25U)

+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */

+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL                ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */

+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos            (26U)

+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */

+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL                ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */

+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos                (25U)

+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk                (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */

+#define ETH_MACHWF0R_TSSTSSEL_BOTH                    ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */

+#define ETH_MACHWF0R_MACADR64SEL_Pos                  (24U)

+#define ETH_MACHWF0R_MACADR64SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */

+#define ETH_MACHWF0R_MACADR64SEL                      ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */

+#define ETH_MACHWF0R_MACADR32SEL_Pos                  (23U)

+#define ETH_MACHWF0R_MACADR32SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */

+#define ETH_MACHWF0R_MACADR32SEL                      ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */

+#define ETH_MACHWF0R_ADDMACADRSEL_Pos                 (18U)

+#define ETH_MACHWF0R_ADDMACADRSEL_Msk                 (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */

+#define ETH_MACHWF0R_ADDMACADRSEL                     ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */

+#define ETH_MACHWF0R_RXCOESEL_Pos                     (16U)

+#define ETH_MACHWF0R_RXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */

+#define ETH_MACHWF0R_RXCOESEL                         ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */

+#define ETH_MACHWF0R_TXCOESEL_Pos                     (14U)

+#define ETH_MACHWF0R_TXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */

+#define ETH_MACHWF0R_TXCOESEL                         ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */

+#define ETH_MACHWF0R_EEESEL_Pos                       (13U)

+#define ETH_MACHWF0R_EEESEL_Msk                       (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */

+#define ETH_MACHWF0R_EEESEL                           ETH_MACHWF0R_EEESEL_Msk  /* Energy Efficient Ethernet Enabled */

+#define ETH_MACHWF0R_TSSEL_Pos                        (12U)

+#define ETH_MACHWF0R_TSSEL_Msk                        (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */

+#define ETH_MACHWF0R_TSSEL                            ETH_MACHWF0R_TSSEL_Msk   /* IEEE 1588-2008 Timestamp Enabled */

+#define ETH_MACHWF0R_ARPOFFSEL_Pos                    (9U)

+#define ETH_MACHWF0R_ARPOFFSEL_Msk                    (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */

+#define ETH_MACHWF0R_ARPOFFSEL                        ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */

+#define ETH_MACHWF0R_MMCSEL_Pos                       (8U)

+#define ETH_MACHWF0R_MMCSEL_Msk                       (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */

+#define ETH_MACHWF0R_MMCSEL                           ETH_MACHWF0R_MMCSEL_Msk  /* RMON Module Enable */

+#define ETH_MACHWF0R_MGKSEL_Pos                       (7U)

+#define ETH_MACHWF0R_MGKSEL_Msk                       (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */

+#define ETH_MACHWF0R_MGKSEL                           ETH_MACHWF0R_MGKSEL_Msk  /* PMT Magic Packet Enable */

+#define ETH_MACHWF0R_RWKSEL_Pos                       (6U)

+#define ETH_MACHWF0R_RWKSEL_Msk                       (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */

+#define ETH_MACHWF0R_RWKSEL                           ETH_MACHWF0R_RWKSEL_Msk  /* PMT Remote Wake-up Packet Enable */

+#define ETH_MACHWF0R_SMASEL_Pos                       (5U)

+#define ETH_MACHWF0R_SMASEL_Msk                       (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */

+#define ETH_MACHWF0R_SMASEL                           ETH_MACHWF0R_SMASEL_Msk  /* SMA (MDIO) Interface */

+#define ETH_MACHWF0R_VLHASH_Pos                       (4U)

+#define ETH_MACHWF0R_VLHASH_Msk                       (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */

+#define ETH_MACHWF0R_VLHASH                           ETH_MACHWF0R_VLHASH_Msk  /* VLAN Hash Filter Selected */

+#define ETH_MACHWF0R_PCSSEL_Pos                       (3U)

+#define ETH_MACHWF0R_PCSSEL_Msk                       (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */

+#define ETH_MACHWF0R_PCSSEL                           ETH_MACHWF0R_PCSSEL_Msk  /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */

+#define ETH_MACHWF0R_HDSEL_Pos                        (2U)

+#define ETH_MACHWF0R_HDSEL_Msk                        (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */

+#define ETH_MACHWF0R_HDSEL                            ETH_MACHWF0R_HDSEL_Msk   /* Half-duplex Support */

+#define ETH_MACHWF0R_GMIISEL_Pos                      (1U)

+#define ETH_MACHWF0R_GMIISEL_Msk                      (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */

+#define ETH_MACHWF0R_GMIISEL                          ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */

+#define ETH_MACHWF0R_MIISEL_Pos                       (0U)

+#define ETH_MACHWF0R_MIISEL_Msk                       (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */

+#define ETH_MACHWF0R_MIISEL                           ETH_MACHWF0R_MIISEL_Msk  /* 10 or 100 Mbps Support */

+

+/* Bit definition for Ethernet MAC HW Feature1 Register */

+#define ETH_MACHWF1R_L3L4FNUM_Pos                     (27U)

+#define ETH_MACHWF1R_L3L4FNUM_Msk                     (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */

+#define ETH_MACHWF1R_L3L4FNUM                         ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */

+#define ETH_MACHWF1R_HASHTBLSZ_Pos                    (24U)

+#define ETH_MACHWF1R_HASHTBLSZ_Msk                    (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */

+#define ETH_MACHWF1R_HASHTBLSZ                        ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */

+#define ETH_MACHWF1R_AVSEL_Pos                        (20U)

+#define ETH_MACHWF1R_AVSEL_Msk                        (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */

+#define ETH_MACHWF1R_AVSEL                            ETH_MACHWF1R_AVSEL_Msk   /* AV Feature Enabled */

+#define ETH_MACHWF1R_DBGMEMA_Pos                      (19U)

+#define ETH_MACHWF1R_DBGMEMA_Msk                      (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */

+#define ETH_MACHWF1R_DBGMEMA                          ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */

+#define ETH_MACHWF1R_TSOEN_Pos                        (18U)

+#define ETH_MACHWF1R_TSOEN_Msk                        (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */

+#define ETH_MACHWF1R_TSOEN                            ETH_MACHWF1R_TSOEN_Msk   /* TCP Segmentation Offload Enable */

+#define ETH_MACHWF1R_SPHEN_Pos                        (17U)

+#define ETH_MACHWF1R_SPHEN_Msk                        (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */

+#define ETH_MACHWF1R_SPHEN                            ETH_MACHWF1R_SPHEN_Msk   /* Split Header Feature Enable */

+#define ETH_MACHWF1R_DCBEN_Pos                        (16U)

+#define ETH_MACHWF1R_DCBEN_Msk                        (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */

+#define ETH_MACHWF1R_DCBEN                            ETH_MACHWF1R_DCBEN_Msk   /* DCB Feature Enable */

+#define ETH_MACHWF1R_ADDR64_Pos                       (14U)

+#define ETH_MACHWF1R_ADDR64_Msk                       (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */

+#define ETH_MACHWF1R_ADDR64                           ETH_MACHWF1R_ADDR64_Msk  /* Address Width */

+#define ETH_MACHWF1R_ADDR64_32                        (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */

+#define ETH_MACHWF1R_ADDR64_40                        (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */

+#define ETH_MACHWF1R_ADDR64_48                        (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */

+#define ETH_MACHWF1R_ADVTHWORD_Pos                    (13U)

+#define ETH_MACHWF1R_ADVTHWORD_Msk                    (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */

+#define ETH_MACHWF1R_ADVTHWORD                        ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */

+#define ETH_MACHWF1R_PTOEN_Pos                        (12U)

+#define ETH_MACHWF1R_PTOEN_Msk                        (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */

+#define ETH_MACHWF1R_PTOEN                            ETH_MACHWF1R_PTOEN_Msk   /* PTP Offload Enable */

+#define ETH_MACHWF1R_OSTEN_Pos                        (11U)

+#define ETH_MACHWF1R_OSTEN_Msk                        (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */

+#define ETH_MACHWF1R_OSTEN                            ETH_MACHWF1R_OSTEN_Msk   /* One-Step Timestamping Enable */

+#define ETH_MACHWF1R_TXFIFOSIZE_Pos                   (6U)

+#define ETH_MACHWF1R_TXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */

+#define ETH_MACHWF1R_TXFIFOSIZE                       ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */

+#define ETH_MACHWF1R_RXFIFOSIZE_Pos                   (0U)

+#define ETH_MACHWF1R_RXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */

+#define ETH_MACHWF1R_RXFIFOSIZE                       ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */

+

+/* Bit definition for Ethernet MAC HW Feature2 Register */

+#define ETH_MACHWF2R_AUXSNAPNUM_Pos                   (28U)

+#define ETH_MACHWF2R_AUXSNAPNUM_Msk                   (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */

+#define ETH_MACHWF2R_AUXSNAPNUM                       ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */

+#define ETH_MACHWF2R_PPSOUTNUM_Pos                    (24U)

+#define ETH_MACHWF2R_PPSOUTNUM_Msk                    (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */

+#define ETH_MACHWF2R_PPSOUTNUM                        ETH_MACHWF2R_PPSOUTNUM_Msk /*  Number of PPS Outputs */

+#define ETH_MACHWF2R_TXCHCNT_Pos                      (18U)

+#define ETH_MACHWF2R_TXCHCNT_Msk                      (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */

+#define ETH_MACHWF2R_TXCHCNT                          ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */

+#define ETH_MACHWF2R_RXCHCNT_Pos                      (13U)

+#define ETH_MACHWF2R_RXCHCNT_Msk                      (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000E000 */

+#define ETH_MACHWF2R_RXCHCNT                          ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */

+#define ETH_MACHWF2R_TXQCNT_Pos                       (6U)

+#define ETH_MACHWF2R_TXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */

+#define ETH_MACHWF2R_TXQCNT                           ETH_MACHWF2R_TXQCNT_Msk  /* Number of MTL Transmit Queues */

+#define ETH_MACHWF2R_RXQCNT_Pos                       (0U)

+#define ETH_MACHWF2R_RXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */

+#define ETH_MACHWF2R_RXQCNT                           ETH_MACHWF2R_RXQCNT_Msk  /* Number of MTL Receive Queues */

+

+/* Bit definition for Ethernet MAC MDIO Address Register */

+#define ETH_MACMDIOAR_PSE_Pos                         (27U)

+#define ETH_MACMDIOAR_PSE_Msk                         (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */

+#define ETH_MACMDIOAR_PSE                             ETH_MACMDIOAR_PSE_Msk    /* Preamble Suppression Enable */

+#define ETH_MACMDIOAR_BTB_Pos                         (26U)

+#define ETH_MACMDIOAR_BTB_Msk                         (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */

+#define ETH_MACMDIOAR_BTB                             ETH_MACMDIOAR_BTB_Msk    /* Back to Back transactions */

+#define ETH_MACMDIOAR_PA_Pos                          (21U)

+#define ETH_MACMDIOAR_PA_Msk                          (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */

+#define ETH_MACMDIOAR_PA                              ETH_MACMDIOAR_PA_Msk     /* Physical Layer Address */

+#define ETH_MACMDIOAR_RDA_Pos                         (16U)

+#define ETH_MACMDIOAR_RDA_Msk                         (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */

+#define ETH_MACMDIOAR_RDA                             ETH_MACMDIOAR_RDA_Msk    /* Register/Device Address */

+#define ETH_MACMDIOAR_NTC_Pos                         (12U)

+#define ETH_MACMDIOAR_NTC_Msk                         (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */

+#define ETH_MACMDIOAR_NTC                             ETH_MACMDIOAR_NTC_Msk    /* Number of Trailing Clocks */

+#define ETH_MACMDIOAR_CR_Pos                          (8U)

+#define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */

+#define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */

+#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */

+#define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)

+#define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */

+#define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */

+#define ETH_MACMDIOAR_CR_DIV16_Pos                    (9U)

+#define ETH_MACMDIOAR_CR_DIV16_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */

+#define ETH_MACMDIOAR_CR_DIV16                        ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */

+#define ETH_MACMDIOAR_CR_DIV26_Pos                    (8U)

+#define ETH_MACMDIOAR_CR_DIV26_Msk                    (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */

+#define ETH_MACMDIOAR_CR_DIV26                        ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */

+#define ETH_MACMDIOAR_CR_DIV102_Pos                   (10U)

+#define ETH_MACMDIOAR_CR_DIV102_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */

+#define ETH_MACMDIOAR_CR_DIV102                       ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */

+#define ETH_MACMDIOAR_CR_DIV124_Pos                   (8U)

+#define ETH_MACMDIOAR_CR_DIV124_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */

+#define ETH_MACMDIOAR_CR_DIV124                       ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */

+#define ETH_MACMDIOAR_CR_DIV4AR_Pos                   (11U)

+#define ETH_MACMDIOAR_CR_DIV4AR_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */

+#define ETH_MACMDIOAR_CR_DIV4AR                       ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV6AR_Pos                   (8U)

+#define ETH_MACMDIOAR_CR_DIV6AR_Msk                   (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */

+#define ETH_MACMDIOAR_CR_DIV6AR                       ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV8AR_Pos                   (9U)

+#define ETH_MACMDIOAR_CR_DIV8AR_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */

+#define ETH_MACMDIOAR_CR_DIV8AR                       ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV10AR_Pos                  (8U)

+#define ETH_MACMDIOAR_CR_DIV10AR_Msk                  (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */

+#define ETH_MACMDIOAR_CR_DIV10AR                      ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV12AR_Pos                  (10U)

+#define ETH_MACMDIOAR_CR_DIV12AR_Msk                  (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */

+#define ETH_MACMDIOAR_CR_DIV12AR                      ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV14AR_Pos                  (8U)

+#define ETH_MACMDIOAR_CR_DIV14AR_Msk                  (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */

+#define ETH_MACMDIOAR_CR_DIV14AR                      ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV16AR_Pos                  (9U)

+#define ETH_MACMDIOAR_CR_DIV16AR_Msk                  (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */

+#define ETH_MACMDIOAR_CR_DIV16AR                      ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV18AR_Pos                  (8U)

+#define ETH_MACMDIOAR_CR_DIV18AR_Msk                  (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */

+#define ETH_MACMDIOAR_CR_DIV18AR                      ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_SKAP_Pos                        (4U)

+#define ETH_MACMDIOAR_SKAP_Msk                        (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */

+#define ETH_MACMDIOAR_SKAP                            ETH_MACMDIOAR_SKAP_Msk   /* Skip Address Packet */

+#define ETH_MACMDIOAR_MOC_Pos                         (2U)

+#define ETH_MACMDIOAR_MOC_Msk                         (0x3UL << ETH_MACMDIOAR_MOC_Pos) /*!< 0x0000000C */

+#define ETH_MACMDIOAR_MOC                             ETH_MACMDIOAR_MOC_Msk    /* MII Operation Command */

+#define ETH_MACMDIOAR_MOC_WR_Pos                      (2U)

+#define ETH_MACMDIOAR_MOC_WR_Msk                      (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos) /*!< 0x00000004 */

+#define ETH_MACMDIOAR_MOC_WR                          ETH_MACMDIOAR_MOC_WR_Msk /* Write */

+#define ETH_MACMDIOAR_MOC_PRDIA_Pos                   (3U)

+#define ETH_MACMDIOAR_MOC_PRDIA_Msk                   (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos) /*!< 0x00000008 */

+#define ETH_MACMDIOAR_MOC_PRDIA                       ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */

+#define ETH_MACMDIOAR_MOC_RD_Pos                      (2U)

+#define ETH_MACMDIOAR_MOC_RD_Msk                      (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos) /*!< 0x0000000C */

+#define ETH_MACMDIOAR_MOC_RD                          ETH_MACMDIOAR_MOC_RD_Msk /* Read */

+#define ETH_MACMDIOAR_C45E_Pos                        (1U)

+#define ETH_MACMDIOAR_C45E_Msk                        (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */

+#define ETH_MACMDIOAR_C45E                            ETH_MACMDIOAR_C45E_Msk   /* Clause 45 PHY Enable */

+#define ETH_MACMDIOAR_MB_Pos                          (0U)

+#define ETH_MACMDIOAR_MB_Msk                          (0x1UL << ETH_MACMDIOAR_MB_Pos) /*!< 0x00000001 */

+#define ETH_MACMDIOAR_MB                              ETH_MACMDIOAR_MB_Msk     /* MII Busy */

+

+/* Bit definition for Ethernet MAC MDIO Data Register */

+#define ETH_MACMDIODR_RA_Pos                          (16U)

+#define ETH_MACMDIODR_RA_Msk                          (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */

+#define ETH_MACMDIODR_RA                              ETH_MACMDIODR_RA_Msk     /* Register Address */

+#define ETH_MACMDIODR_MD_Pos                          (0U)

+#define ETH_MACMDIODR_MD_Msk                          (0xFFFFUL << ETH_MACMDIODR_MD_Pos) /*!< 0x0000FFFF */

+#define ETH_MACMDIODR_MD                              ETH_MACMDIODR_MD_Msk     /* MII Data */

+

+/* Bit definition for Ethernet ARP Address Register */

+#define ETH_MACARPAR_ARPPA_Pos                         (0U)

+#define ETH_MACARPAR_ARPPA_Msk                         (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACARPAR_ARPPA                             ETH_MACARPAR_ARPPA_Msk     /* ARP Protocol Address */

+

+/* Bit definition for Ethernet MAC Address 0 High Register */

+#define ETH_MACA0HR_AE_Pos                            (31U)

+#define ETH_MACA0HR_AE_Msk                            (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA0HR_AE                                ETH_MACA0HR_AE_Msk /* Address Enable*/

+#define ETH_MACA0HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA0HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA0HR_ADDRHI                            ETH_MACA0HR_ADDRHI_Msk   /* MAC Address 0*/

+

+/* Bit definition for Ethernet MAC Address 0 Low Register */

+#define ETH_MACA0LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA0LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA0LR_ADDRLO                            ETH_MACA0LR_ADDRLO_Msk   /* MAC Address 0*/

+

+/* Bit definition for Ethernet MAC Address 1 High Register */

+#define ETH_MACA1HR_AE_Pos                            (31U)

+#define ETH_MACA1HR_AE_Msk                            (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk /* Address Enable*/

+#define ETH_MACA1HR_SA_Pos                            (30U)

+#define ETH_MACA1HR_SA_Msk                            (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk /* Source Address */

+#define ETH_MACA1HR_MBC_Pos                           (24U)

+#define ETH_MACA1HR_MBC_Msk                           (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk /* Mask Byte Control */

+#define ETH_MACA1HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA1HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA1HR_ADDRHI                            ETH_MACA1HR_ADDRHI_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 1 Low Register */

+#define ETH_MACA1LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA1LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA1LR_ADDRLO                            ETH_MACA1LR_ADDRLO_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 2 High Register */

+#define ETH_MACA2HR_AE_Pos                            (31U)

+#define ETH_MACA2HR_AE_Msk                            (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk /* Address Enable*/

+#define ETH_MACA2HR_SA_Pos                            (30U)

+#define ETH_MACA2HR_SA_Msk                            (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk /* Source Address */

+#define ETH_MACA2HR_MBC_Pos                           (24U)

+#define ETH_MACA2HR_MBC_Msk                           (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk /* Mask Byte Control */

+#define ETH_MACA2HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA2HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA2HR_ADDRHI                            ETH_MACA2HR_ADDRHI_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 2 Low Register */

+#define ETH_MACA2LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA2LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA2LR_ADDRLO                            ETH_MACA2LR_ADDRLO_Msk   /* MAC Address 2*/

+

+/* Bit definition for Ethernet MAC Address 3 High Register */

+#define ETH_MACA3HR_AE_Pos                            (31U)

+#define ETH_MACA3HR_AE_Msk                            (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk /* Address Enable*/

+#define ETH_MACA3HR_SA_Pos                            (30U)

+#define ETH_MACA3HR_SA_Msk                            (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk /* Source Address */

+#define ETH_MACA3HR_MBC_Pos                           (24U)

+#define ETH_MACA3HR_MBC_Msk                           (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk /* Mask Byte Control */

+#define ETH_MACA3HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA3HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA3HR_ADDRHI                            ETH_MACA3HR_ADDRHI_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 3 Low Register */

+#define ETH_MACA3LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA3LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA3LR_ADDRLO                            ETH_MACA3LR_ADDRLO_Msk   /* MAC Address 3*/

+

+/* Bit definition for Ethernet MAC Address High Register */

+#define ETH_MACAHR_AE_Pos                             (31U)

+#define ETH_MACAHR_AE_Msk                             (0x1UL << ETH_MACAHR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACAHR_AE                                 ETH_MACAHR_AE_Msk        /* Address enable */

+#define ETH_MACAHR_SA_Pos                             (30U)

+#define ETH_MACAHR_SA_Msk                             (0x1UL << ETH_MACAHR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACAHR_SA                                 ETH_MACAHR_SA_Msk        /* Source address */

+#define ETH_MACAHR_MBC_Pos                            (24U)

+#define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */

+#define ETH_MACAHR_MBC_HBITS15_8                      ((uint32_t)0x20000000)   /* Mask MAC Address high reg bits [15:8] */

+#define ETH_MACAHR_MBC_HBITS7_0                       ((uint32_t)0x10000000)   /* Mask MAC Address high reg bits [7:0] */

+#define ETH_MACAHR_MBC_LBITS31_24                     ((uint32_t)0x08000000)   /* Mask MAC Address low reg bits [31:24] */

+#define ETH_MACAHR_MBC_LBITS23_16                     ((uint32_t)0x04000000)   /* Mask MAC Address low reg bits [23:16] */

+#define ETH_MACAHR_MBC_LBITS15_8                      ((uint32_t)0x02000000)   /* Mask MAC Address low reg bits [15:8] */

+#define ETH_MACAHR_MBC_LBITS7_0                       ((uint32_t)0x01000000)   /* Mask MAC Address low reg bits [7:0] */

+#define ETH_MACAHR_MACAH_Pos                          (0U)

+#define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */

+#define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */

+

+/* Bit definition for Ethernet MAC Address Low Register */

+#define ETH_MACALR_MACAL_Pos                          (0U)

+#define ETH_MACALR_MACAL_Msk                          (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACALR_MACAL                              ETH_MACALR_MACAL_Msk     /* MAC address low */

+

+/* Bit definition for Ethernet MMC Control Register */

+#define ETH_MMCCR_UCDBC_Pos                           (8U)

+#define ETH_MMCCR_UCDBC_Msk                           (0x1UL << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */

+#define ETH_MMCCR_UCDBC                               ETH_MMCCR_UCDBC_Msk  /* Update MMC Counters for Dropped Broadcast Packets */

+#define ETH_MMCCR_CNTPRSTLVL_Pos                      (5U)

+#define ETH_MMCCR_CNTPRSTLVL_Msk                      (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */

+#define ETH_MMCCR_CNTPRSTLVL                          ETH_MMCCR_CNTPRSTLVL_Msk  /* Full-Half Preset */

+#define ETH_MMCCR_CNTPRST_Pos                         (4U)

+#define ETH_MMCCR_CNTPRST_Msk                         (0x1UL << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */

+#define ETH_MMCCR_CNTPRST                             ETH_MMCCR_CNTPRST_Msk  /* Counters Reset */

+#define ETH_MMCCR_CNTFREEZ_Pos                        (3U)

+#define ETH_MMCCR_CNTFREEZ_Msk                        (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */

+#define ETH_MMCCR_CNTFREEZ                            ETH_MMCCR_CNTFREEZ_Msk  /* MMC Counter Freeze */

+#define ETH_MMCCR_RSTONRD_Pos                         (2U)

+#define ETH_MMCCR_RSTONRD_Msk                         (0x1UL << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */

+#define ETH_MMCCR_RSTONRD                             ETH_MMCCR_RSTONRD_Msk  /* Reset On Read */

+#define ETH_MMCCR_CNTSTOPRO_Pos                       (1U)

+#define ETH_MMCCR_CNTSTOPRO_Msk                       (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */

+#define ETH_MMCCR_CNTSTOPRO                           ETH_MMCCR_CNTSTOPRO_Msk  /* Counter Stop Rollover */

+#define ETH_MMCCR_CNTRST_Pos                          (0U)

+#define ETH_MMCCR_CNTRST_Msk                          (0x1UL << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */

+#define ETH_MMCCR_CNTRST                              ETH_MMCCR_CNTRST_Msk  /* Counters Reset */

+

+/* Bit definition for Ethernet MMC Rx Interrupt Register */

+#define ETH_MMCRIR_RXLPITRCIS_Pos                     (27U)

+#define ETH_MMCRIR_RXLPITRCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) /*!< 0x08000000 */

+#define ETH_MMCRIR_RXLPITRCIS                         ETH_MMCRIR_RXLPITRCIS_Msk  /* MMC Receive LPI transition counter interrupt status */

+#define ETH_MMCRIR_RXLPIUSCIS_Pos                     (26U)

+#define ETH_MMCRIR_RXLPIUSCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */

+#define ETH_MMCRIR_RXLPIUSCIS                         ETH_MMCRIR_RXLPIUSCIS_Msk  /* MMC Receive LPI microsecond counter interrupt status */

+#define ETH_MMCRIR_RXUCGPIS_Pos                       (17U)

+#define ETH_MMCRIR_RXUCGPIS_Msk                       (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) /*!< 0x00020000 */

+#define ETH_MMCRIR_RXUCGPIS                           ETH_MMCRIR_RXUCGPIS_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Status */

+#define ETH_MMCRIR_RXALGNERPIS_Pos                    (6U)

+#define ETH_MMCRIR_RXALGNERPIS_Msk                    (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) /*!< 0x00000040 */

+#define ETH_MMCRIR_RXALGNERPIS                        ETH_MMCRIR_RXALGNERPIS_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Status */

+#define ETH_MMCRIR_RXCRCERPIS_Pos                     (5U)

+#define ETH_MMCRIR_RXCRCERPIS_Msk                     (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) /*!< 0x00000020 */

+#define ETH_MMCRIR_RXCRCERPIS                         ETH_MMCRIR_RXCRCERPIS_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Status */

+

+/* Bit definition for Ethernet MMC Tx Interrupt Register */

+#define ETH_MMCTIR_TXLPITRCIS_Pos                     (27U)

+#define ETH_MMCTIR_TXLPITRCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) /*!< 0x08000000 */

+#define ETH_MMCTIR_TXLPITRCIS                         ETH_MMCTIR_TXLPITRCIS_Msk  /* MMC Transmit LPI transition counter interrupt status */

+#define ETH_MMCTIR_TXLPIUSCIS_Pos                     (26U)

+#define ETH_MMCTIR_TXLPIUSCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */

+#define ETH_MMCTIR_TXLPIUSCIS                         ETH_MMCTIR_TXLPIUSCIS_Msk  /* MMC Transmit LPI microsecond counter interrupt status */

+#define ETH_MMCTIR_TXGPKTIS_Pos                       (21U)

+#define ETH_MMCTIR_TXGPKTIS_Msk                       (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) /*!< 0x00200000 */

+#define ETH_MMCTIR_TXGPKTIS                           ETH_MMCTIR_TXGPKTIS_Msk  /* MMC Transmit Good Packet Counter Interrupt Status */

+#define ETH_MMCTIR_TXMCOLGPIS_Pos                     (15U)

+#define ETH_MMCTIR_TXMCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */

+#define ETH_MMCTIR_TXMCOLGPIS                         ETH_MMCTIR_TXMCOLGPIS_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */

+#define ETH_MMCTIR_TXSCOLGPIS_Pos                     (14U)

+#define ETH_MMCTIR_TXSCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */

+#define ETH_MMCTIR_TXSCOLGPIS                         ETH_MMCTIR_TXSCOLGPIS_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */

+

+/* Bit definition for Ethernet MMC Rx interrupt Mask register */

+#define ETH_MMCRIMR_RXLPITRCIM_Pos                    (27U)

+#define ETH_MMCRIMR_RXLPITRCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */

+#define ETH_MMCRIMR_RXLPITRCIM                        ETH_MMCRIMR_RXLPITRCIM_Msk  /* MMC Receive LPI transition counter interrupt Mask */

+#define ETH_MMCRIMR_RXLPIUSCIM_Pos                    (26U)

+#define ETH_MMCRIMR_RXLPIUSCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */

+#define ETH_MMCRIMR_RXLPIUSCIM                        ETH_MMCRIMR_RXLPIUSCIM_Msk  /* MMC Receive LPI microsecond counter interrupt Mask */

+#define ETH_MMCRIMR_RXUCGPIM_Pos                      (17U)

+#define ETH_MMCRIMR_RXUCGPIM_Msk                      (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) /*!< 0x00020000 */

+#define ETH_MMCRIMR_RXUCGPIM                          ETH_MMCRIMR_RXUCGPIM_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Mask */

+#define ETH_MMCRIMR_RXALGNERPIM_Pos                   (6U)

+#define ETH_MMCRIMR_RXALGNERPIM_Msk                   (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */

+#define ETH_MMCRIMR_RXALGNERPIM                       ETH_MMCRIMR_RXALGNERPIM_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Mask */

+#define ETH_MMCRIMR_RXCRCERPIM_Pos                    (5U)

+#define ETH_MMCRIMR_RXCRCERPIM_Msk                    (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */

+#define ETH_MMCRIMR_RXCRCERPIM                        ETH_MMCRIMR_RXCRCERPIM_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Mask */

+

+/* Bit definition for Ethernet MMC Tx Interrupt Mask Register */

+#define ETH_MMCTIMR_TXLPITRCIM_Pos                    (27U)

+#define ETH_MMCTIMR_TXLPITRCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */

+#define ETH_MMCTIMR_TXLPITRCIM                        ETH_MMCTIMR_TXLPITRCIM_Msk  /* MMC Transmit LPI transition counter interrupt Mask*/

+#define ETH_MMCTIMR_TXLPIUSCIM_Pos                    (26U)

+#define ETH_MMCTIMR_TXLPIUSCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */

+#define ETH_MMCTIMR_TXLPIUSCIM                        ETH_MMCTIMR_TXLPIUSCIM_Msk  /* MMC Transmit LPI microsecond counter interrupt Mask*/

+#define ETH_MMCTIMR_TXGPKTIM_Pos                      (21U)

+#define ETH_MMCTIMR_TXGPKTIM_Msk                      (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) /*!< 0x00200000 */

+#define ETH_MMCTIMR_TXGPKTIM                          ETH_MMCTIMR_TXGPKTIM_Msk  /* MMC Transmit Good Packet Counter Interrupt Mask*/

+#define ETH_MMCTIMR_TXMCOLGPIM_Pos                    (15U)

+#define ETH_MMCTIMR_TXMCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */

+#define ETH_MMCTIMR_TXMCOLGPIM                        ETH_MMCTIMR_TXMCOLGPIM_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */

+#define ETH_MMCTIMR_TXSCOLGPIM_Pos                    (14U)

+#define ETH_MMCTIMR_TXSCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */

+#define ETH_MMCTIMR_TXSCOLGPIM                        ETH_MMCTIMR_TXSCOLGPIM_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */

+

+/* Bit definition for Ethernet MMC Tx Single Collision Good Packets Register */

+#define ETH_MMCTSCGPR_TXSNGLCOLG_Pos                  (0U)

+#define ETH_MMCTSCGPR_TXSNGLCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTSCGPR_TXSNGLCOLG                      ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */

+

+/* Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register */

+#define ETH_MMCTMCGPR_TXMULTCOLG_Pos                  (0U)

+#define ETH_MMCTMCGPR_TXMULTCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTMCGPR_TXMULTCOLG                      ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */

+

+/* Bit definition for Ethernet MMC Tx Packet Count Good Register */

+#define ETH_MMCTPCGR_TXPKTG_Pos                       (0U)

+#define ETH_MMCTPCGR_TXPKTG_msk                       (0xFFFFFFFFUL <<  ETH_MMCTPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTPCGR_TXPKTG                           ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */

+

+/* Bit definition for Ethernet MMC Rx CRC Error Packets Register */

+#define ETH_MMCRCRCEPR_RXCRCERR_Pos                   (0U)

+#define ETH_MMCRCRCEPR_RXCRCERR_msk                   (0xFFFFFFFFUL <<  ETH_MMCRCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRCRCEPR_RXCRCERR                       ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */

+

+/* Bit definition for Ethernet MMC Rx alignment error packets register */

+#define ETH_MMCRAEPR_RXALGNERR_Pos                    (0U)

+#define ETH_MMCRAEPR_RXALGNERR_msk                    (0xFFFFFFFFUL <<  ETH_MMCRAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRAEPR_RXALGNERR                        ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */

+

+/* Bit definition for Ethernet MMC Rx Unicast Packets Good Register */

+#define ETH_MMCRUPGR_RXUCASTG_Pos                     (0U)

+#define ETH_MMCRUPGR_RXUCASTG_msk                     (0xFFFFFFFFUL <<  ETH_MMCRUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRUPGR_RXUCASTG                         ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */

+

+/* Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register */

+#define ETH_MMCTLPIMSTR_TXLPIUSC_Pos                  (0U)

+#define ETH_MMCTLPIMSTR_TXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCTLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTLPIMSTR_TXLPIUSC                      ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */

+

+/* Bit definition for Ethernet MMC Tx LPI Transition Counter Register */

+#define ETH_MMCTLPITCR_TXLPITRC_Pos                   (0U)

+#define ETH_MMCTLPITCR_TXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCTLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTLPITCR_TXLPITRC                       ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */

+

+/* Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register */

+#define ETH_MMCRLPIMSTR_RXLPIUSC_Pos                  (0U)

+#define ETH_MMCRLPIMSTR_RXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCRLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRLPIMSTR_RXLPIUSC                      ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */

+

+/* Bit definition for Ethernet MMC Rx LPI Transition Counter Register */

+#define ETH_MMCRLPITCR_RXLPITRC_Pos                   (0U)

+#define ETH_MMCRLPITCR_RXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCRLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRLPITCR_RXLPITRC                       ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */

+

+/* Bit definition for Ethernet MAC L3 L4 Control Register */

+#define ETH_MACL3L4CR_L4DPIM_Pos                      (21U)

+#define ETH_MACL3L4CR_L4DPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos) /*!< 0x00200000 */

+#define ETH_MACL3L4CR_L4DPIM                          ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */

+#define ETH_MACL3L4CR_L4DPM_Pos                       (20U)

+#define ETH_MACL3L4CR_L4DPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4DPM_Pos) /*!< 0x00100000 */

+#define ETH_MACL3L4CR_L4DPM                           ETH_MACL3L4CR_L4DPM_Msk  /* Layer 4 Destination Port Match Enable */

+#define ETH_MACL3L4CR_L4SPIM_Pos                      (19U)

+#define ETH_MACL3L4CR_L4SPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos) /*!< 0x00080000 */

+#define ETH_MACL3L4CR_L4SPIM                          ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */

+#define ETH_MACL3L4CR_L4SPM_Pos                       (18U)

+#define ETH_MACL3L4CR_L4SPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4SPM_Pos) /*!< 0x00040000 */

+#define ETH_MACL3L4CR_L4SPM                           ETH_MACL3L4CR_L4SPM_Msk  /* Layer 4 Source Port Match Enable */

+#define ETH_MACL3L4CR_L4PEN_Pos                       (16U)

+#define ETH_MACL3L4CR_L4PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L4PEN_Pos) /*!< 0x00010000 */

+#define ETH_MACL3L4CR_L4PEN                           ETH_MACL3L4CR_L4PEN_Msk  /* Layer 4 Protocol Enable */

+#define ETH_MACL3L4CR_L3HDBM_Pos                      (11U)

+#define ETH_MACL3L4CR_L3HDBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos) /*!< 0x0000F800 */

+#define ETH_MACL3L4CR_L3HDBM                          ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */

+#define ETH_MACL3L4CR_L3HSBM_Pos                      (6U)

+#define ETH_MACL3L4CR_L3HSBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos) /*!< 0x000007C0 */

+#define ETH_MACL3L4CR_L3HSBM                          ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */

+#define ETH_MACL3L4CR_L3DAIM_Pos                      (5U)

+#define ETH_MACL3L4CR_L3DAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos) /*!< 0x00000020 */

+#define ETH_MACL3L4CR_L3DAIM                          ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */

+#define ETH_MACL3L4CR_L3DAM_Pos                       (4U)

+#define ETH_MACL3L4CR_L3DAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3DAM_Pos) /*!< 0x00000010 */

+#define ETH_MACL3L4CR_L3DAM                           ETH_MACL3L4CR_L3DAM_Msk  /* Layer 3 IP DA Match Enable */

+#define ETH_MACL3L4CR_L3SAIM_Pos                      (3U)

+#define ETH_MACL3L4CR_L3SAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos) /*!< 0x00000008 */

+#define ETH_MACL3L4CR_L3SAIM                          ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */

+#define ETH_MACL3L4CR_L3SAM_Pos                       (2U)

+#define ETH_MACL3L4CR_L3SAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3SAM_Pos) /*!< 0x00000004 */

+#define ETH_MACL3L4CR_L3SAM                           ETH_MACL3L4CR_L3SAM_Msk  /* Layer 3 IP SA Match Enable*/

+#define ETH_MACL3L4CR_L3PEN_Pos                       (0U)

+#define ETH_MACL3L4CR_L3PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L3PEN_Pos) /*!< 0x00000001 */

+#define ETH_MACL3L4CR_L3PEN                           ETH_MACL3L4CR_L3PEN_Msk  /* Layer 3 Protocol Enable */

+

+/* Bit definition for Ethernet MAC L4 Address Register */

+#define ETH_MACL4AR_L4DP_Pos                          (16U)

+#define ETH_MACL4AR_L4DP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4DP_Pos) /*!< 0xFFFF0000 */

+#define ETH_MACL4AR_L4DP                              ETH_MACL4AR_L4DP_Msk     /* Layer 4 Destination Port Number Field */

+#define ETH_MACL4AR_L4SP_Pos                          (0U)

+#define ETH_MACL4AR_L4SP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4SP_Pos) /*!< 0x0000FFFF */

+#define ETH_MACL4AR_L4SP                              ETH_MACL4AR_L4SP_Msk     /* Layer 4 Source Port Number Field */

+

+/* Bit definition for Ethernet MAC L3 Address0 Register */

+#define ETH_MACL3A0R_L3A0_Pos                         (0U)

+#define ETH_MACL3A0R_L3A0_Msk                         (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A0R_L3A0                             ETH_MACL3A0R_L3A0_Msk    /* Layer 3 Address 0 Field */

+

+/* Bit definition for Ethernet MAC L4 Address1 Register */

+#define ETH_MACL3A1R_L3A1_Pos                         (0U)

+#define ETH_MACL3A1R_L3A1_Msk                         (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A1R_L3A1                             ETH_MACL3A1R_L3A1_Msk    /* Layer 3 Address 1 Field */

+

+/* Bit definition for Ethernet MAC L4 Address2 Register */

+#define ETH_MACL3A2R_L3A2_Pos                         (0U)

+#define ETH_MACL3A2R_L3A2_Msk                         (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A2R_L3A2                             ETH_MACL3A2R_L3A2_Msk    /* Layer 3 Address 2 Field */

+

+/* Bit definition for Ethernet MAC L4 Address3 Register */

+#define ETH_MACL3A3R_L3A3_Pos                         (0U)

+#define ETH_MACL3A3R_L3A3_Msk                         (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A3R_L3A3                             ETH_MACL3A3R_L3A3_Msk    /* Layer 3 Address 3 Field */

+

+/* Bit definition for Ethernet MAC Timestamp Control Register */

+#define ETH_MACTSCR_TXTSSTSM_Pos                      (24U)

+#define ETH_MACTSCR_TXTSSTSM_Msk                      (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */

+#define ETH_MACTSCR_TXTSSTSM                          ETH_MACTSCR_TXTSSTSM_Msk  /* Transmit Timestamp Status Mode */

+#define ETH_MACTSCR_CSC_Pos                           (19U)

+#define ETH_MACTSCR_CSC_Msk                           (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */

+#define ETH_MACTSCR_CSC                               ETH_MACTSCR_CSC_Msk  /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */

+#define ETH_MACTSCR_TSENMACADDR_Pos                   (18U)

+#define ETH_MACTSCR_TSENMACADDR_Msk                   (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */

+#define ETH_MACTSCR_TSENMACADDR                       ETH_MACTSCR_TSENMACADDR_Msk  /* Enable MAC Address for PTP Packet Filtering */

+#define ETH_MACTSCR_SNAPTYPSEL_Pos                    (16U)

+#define ETH_MACTSCR_SNAPTYPSEL_Msk                    (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */

+#define ETH_MACTSCR_SNAPTYPSEL                        ETH_MACTSCR_SNAPTYPSEL_Msk  /* Select PTP packets for Taking Snapshots */

+#define ETH_MACTSCR_TSMSTRENA_Pos                     (15U)

+#define ETH_MACTSCR_TSMSTRENA_Msk                     (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */

+#define ETH_MACTSCR_TSMSTRENA                         ETH_MACTSCR_TSMSTRENA_Msk  /* Enable Snapshot for Messages Relevant to Master */

+#define ETH_MACTSCR_TSEVNTENA_Pos                     (14U)

+#define ETH_MACTSCR_TSEVNTENA_Msk                     (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */

+#define ETH_MACTSCR_TSEVNTENA                         ETH_MACTSCR_TSEVNTENA_Msk  /* Enable Timestamp Snapshot for Event Messages */

+#define ETH_MACTSCR_TSIPV4ENA_Pos                     (13U)

+#define ETH_MACTSCR_TSIPV4ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */

+#define ETH_MACTSCR_TSIPV4ENA                         ETH_MACTSCR_TSIPV4ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv4-UDP */

+#define ETH_MACTSCR_TSIPV6ENA_Pos                     (12U)

+#define ETH_MACTSCR_TSIPV6ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */

+#define ETH_MACTSCR_TSIPV6ENA                         ETH_MACTSCR_TSIPV6ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv6-UDP */

+#define ETH_MACTSCR_TSIPENA_Pos                       (11U)

+#define ETH_MACTSCR_TSIPENA_Msk                       (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */

+#define ETH_MACTSCR_TSIPENA                           ETH_MACTSCR_TSIPENA_Msk  /* Enable Processing of PTP over Ethernet Packets */

+#define ETH_MACTSCR_TSVER2ENA_Pos                     (10U)

+#define ETH_MACTSCR_TSVER2ENA_Msk                     (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */

+#define ETH_MACTSCR_TSVER2ENA                         ETH_MACTSCR_TSVER2ENA_Msk  /* Enable PTP Packet Processing for Version 2 Format */

+#define ETH_MACTSCR_TSCTRLSSR_Pos                     (9U)

+#define ETH_MACTSCR_TSCTRLSSR_Msk                     (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */

+#define ETH_MACTSCR_TSCTRLSSR                         ETH_MACTSCR_TSCTRLSSR_Msk  /* Timestamp Digital or Binary Rollover Control */

+#define ETH_MACTSCR_TSENALL_Pos                       (8U)

+#define ETH_MACTSCR_TSENALL_Msk                       (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */

+#define ETH_MACTSCR_TSENALL                           ETH_MACTSCR_TSENALL_Msk  /* Enable Timestamp for All Packets */

+#define ETH_MACTSCR_TSADDREG_Pos                      (5U)

+#define ETH_MACTSCR_TSADDREG_Msk                      (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */

+#define ETH_MACTSCR_TSADDREG                          ETH_MACTSCR_TSADDREG_Msk  /* Update Addend Register */

+#define ETH_MACTSCR_TSUPDT_Pos                        (3U)

+#define ETH_MACTSCR_TSUPDT_Msk                        (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */

+#define ETH_MACTSCR_TSUPDT                            ETH_MACTSCR_TSUPDT_Msk  /* Update Timestamp */

+#define ETH_MACTSCR_TSINIT_Pos                        (2U)

+#define ETH_MACTSCR_TSINIT_Msk                        (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */

+#define ETH_MACTSCR_TSINIT                             ETH_MACTSCR_TSINIT_Msk  /* Initialize Timestamp */

+#define ETH_MACTSCR_TSCFUPDT_Pos                      (1U)

+#define ETH_MACTSCR_TSCFUPDT_Msk                      (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */

+#define ETH_MACTSCR_TSCFUPDT                          ETH_MACTSCR_TSCFUPDT_Msk  /* Fine or Coarse Timestamp Update*/

+#define ETH_MACTSCR_TSENA_Pos                         (0U)

+#define ETH_MACTSCR_TSENA_Msk                         (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */

+#define ETH_MACTSCR_TSENA                             ETH_MACTSCR_TSENA_Msk  /* Enable Timestamp */

+

+/* Bit definition for Ethernet MAC Sub-second Increment Register */

+#define ETH_MACMACSSIR_SSINC_Pos                      (16U)

+#define ETH_MACMACSSIR_SSINC_Msk                      (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) /*!< 0x0000FF00 */

+#define ETH_MACMACSSIR_SSINC                          ETH_MACMACSSIR_SSINC_Msk  /* Sub-second Increment Value */

+#define ETH_MACMACSSIR_SNSINC_Pos                     (8U)

+#define ETH_MACMACSSIR_SNSINC_Msk                     (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos) /*!< 0x000000FF */

+#define ETH_MACMACSSIR_SNSINC                         ETH_MACMACSSIR_SNSINC_Msk  /* Sub-nanosecond Increment Value */

+

+/* Bit definition for Ethernet MAC System Time Seconds Register */

+#define ETH_MACSTSR_TSS_Pos                           (0U)

+#define ETH_MACSTSR_TSS_Msk                           (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSTSR_TSS                               ETH_MACSTSR_TSS_Msk  /* Timestamp Second */

+

+/* Bit definition for Ethernet MAC System Time Nanoseconds Register */

+#define ETH_MACSTNR_TSSS_Pos                          (0U)

+#define ETH_MACSTNR_TSSS_Msk                          (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACSTNR_TSSS                              ETH_MACSTNR_TSSS_Msk  /* Timestamp Sub-seconds */

+

+/* Bit definition for Ethernet MAC System Time Seconds Update Register */

+#define ETH_MACSTSUR_TSS_Pos                          (0U)

+#define ETH_MACSTSUR_TSS_Msk                          (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSTSUR_TSS                              ETH_MACSTSUR_TSS_Msk  /* Timestamp Seconds */

+

+/* Bit definition for Ethernet MAC System Time Nanoseconds Update Register */

+#define ETH_MACSTNUR_ADDSUB_Pos                       (31U)

+#define ETH_MACSTNUR_ADDSUB_Msk                       (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */

+#define ETH_MACSTNUR_ADDSUB                           ETH_MACSTNUR_ADDSUB_Msk  /* Add or Subtract Time */

+#define ETH_MACSTNUR_TSSS_Pos                         (0U)

+#define ETH_MACSTNUR_TSSS_Msk                         (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACSTNUR_TSSS                             ETH_MACSTNUR_TSSS_Msk  /* Timestamp Sub-seconds */

+

+/* Bit definition for Ethernet MAC Timestamp Addend Register */

+#define ETH_MACTSAR_TSAR_Pos                          (0U)

+#define ETH_MACTSAR_TSAR_Msk                          (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSAR_TSAR                              ETH_MACTSAR_TSAR_Msk  /* Timestamp Addend Register */

+

+/* Bit definition for Ethernet MAC Timestamp Status Register */

+#define ETH_MACTSSR_ATSNS_Pos                         (25U)

+#define ETH_MACTSSR_ATSNS_Msk                         (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */

+#define ETH_MACTSSR_ATSNS                             ETH_MACTSSR_ATSNS_Msk  /* Number of Auxiliary Timestamp Snapshots */

+#define ETH_MACTSSR_ATSSTM_Pos                        (24U)

+#define ETH_MACTSSR_ATSSTM_Msk                        (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */

+#define ETH_MACTSSR_ATSSTM                            ETH_MACTSSR_ATSSTM_Msk  /* Auxiliary Timestamp Snapshot Trigger Missed */

+#define ETH_MACTSSR_ATSSTN_Pos                        (16U)

+#define ETH_MACTSSR_ATSSTN_Msk                        (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */

+#define ETH_MACTSSR_ATSSTN                            ETH_MACTSSR_ATSSTN_Msk  /* Auxiliary Timestamp Snapshot Trigger Identifier */

+#define ETH_MACTSSR_TXTSSIS_Pos                       (15U)

+#define ETH_MACTSSR_TXTSSIS_Msk                       (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */

+#define ETH_MACTSSR_TXTSSIS                           ETH_MACTSSR_TXTSSIS_Msk  /* Tx Timestamp Status Interrupt Status */

+#define ETH_MACTSSR_TSTRGTERR0_Pos                    (3U)

+#define ETH_MACTSSR_TSTRGTERR0_Msk                    (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */

+#define ETH_MACTSSR_TSTRGTERR0                        ETH_MACTSSR_TSTRGTERR0_Msk  /* Timestamp Target Time Error */

+#define ETH_MACTSSR_AUXTSTRIG_Pos                     (2U)

+#define ETH_MACTSSR_AUXTSTRIG_Msk                     (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */

+#define ETH_MACTSSR_AUXTSTRIG                         ETH_MACTSSR_AUXTSTRIG_Msk  /* Auxiliary Timestamp Trigger Snapshot*/

+#define ETH_MACTSSR_TSTARGT0_Pos                      (1U)

+#define ETH_MACTSSR_TSTARGT0_Msk                      (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */

+#define ETH_MACTSSR_TSTARGT0                          ETH_MACTSSR_TSTARGT0_Msk  /* Timestamp Target Time Reached */

+#define ETH_MACTSSR_TSSOVF_Pos                        (0U)

+#define ETH_MACTSSR_TSSOVF_Msk                        (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */

+#define ETH_MACTSSR_TSSOVF                            ETH_MACTSSR_TSSOVF_Msk  /* Timestamp Seconds Overflow */

+

+/* Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register */

+#define ETH_MACTTSSNR_TXTSSMIS_Pos                    (31U)

+#define ETH_MACTTSSNR_TXTSSMIS_Msk                    (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */

+#define ETH_MACTTSSNR_TXTSSMIS                        ETH_MACTTSSNR_TXTSSMIS_Msk  /* Transmit Timestamp Status Missed */

+#define ETH_MACTTSSNR_TXTSSLO_Pos                     (0U)

+#define ETH_MACTTSSNR_TXTSSLO_Msk                     (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACTTSSNR_TXTSSLO                         ETH_MACTTSSNR_TXTSSLO_Msk  /* Transmit Timestamp Status Low */

+

+/* Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register */

+#define ETH_MACTTSSSR_TXTSSHI_Pos                     (0U)

+#define ETH_MACTTSSSR_TXTSSHI_Msk                     (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTTSSSR_TXTSSHI                         ETH_MACTTSSSR_TXTSSHI_Msk  /* Transmit Timestamp Status High */

+

+/* Bit definition for Ethernet MAC Auxiliary Control Register*/

+#define ETH_MACACR_ATSEN3_Pos                         (7U)

+#define ETH_MACACR_ATSEN3_Msk                         (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */

+#define ETH_MACACR_ATSEN3                             ETH_MACACR_ATSEN3_Msk  /* Auxiliary Snapshot 3 Enable */

+#define ETH_MACACR_ATSEN2_Pos                         (6U)

+#define ETH_MACACR_ATSEN2_Msk                         (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */

+#define ETH_MACACR_ATSEN2                             ETH_MACACR_ATSEN2_Msk  /* Auxiliary Snapshot 2 Enable */

+#define ETH_MACACR_ATSEN1_Pos                         (5U)

+#define ETH_MACACR_ATSEN1_Msk                         (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */

+#define ETH_MACACR_ATSEN1                             ETH_MACACR_ATSEN1_Msk  /* Auxiliary Snapshot 1 Enable */

+#define ETH_MACACR_ATSEN0_Pos                         (4U)

+#define ETH_MACACR_ATSEN0_Msk                         (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */

+#define ETH_MACACR_ATSEN0                             ETH_MACACR_ATSEN0_Msk  /* Auxiliary Snapshot 0 Enable */

+#define ETH_MACACR_ATSFC_Pos                          (0U)

+#define ETH_MACACR_ATSFC_Msk                          (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */

+#define ETH_MACACR_ATSFC                              ETH_MACACR_ATSFC_Msk  /* Auxiliary Snapshot FIFO Clear */

+

+/* Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register */

+#define ETH_MACATSNR_AUXTSLO_Pos                      (0U)

+#define ETH_MACATSNR_AUXTSLO_Msk                      (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACATSNR_AUXTSLO                          ETH_MACATSNR_AUXTSLO_Msk  /* Auxiliary Timestamp */

+

+/* Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register */

+#define ETH_MACATSSR_AUXTSHI_Pos                      (0U)

+#define ETH_MACATSSR_AUXTSHI_Msk                      (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACATSSR_AUXTSHI                          ETH_MACATSSR_AUXTSHI_Msk  /* Auxiliary Timestamp */

+

+/* Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register */

+#define ETH_MACTSIACR_OSTIAC_Pos                      (0U)

+#define ETH_MACTSIACR_OSTIAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSIACR_OSTIAC                          ETH_MACTSIACR_OSTIAC_Msk  /* One-Step Timestamp Ingress Asymmetry Correction */

+

+/* Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction Register */

+#define ETH_MACTSEACR_OSTEAC_Pos                      (0U)

+#define ETH_MACTSEACR_OSTEAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSEACR_OSTEAC                          ETH_MACTSEACR_OSTEAC_Msk  /* One-Step Timestamp Egress Asymmetry Correction */

+

+/* Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond Register */

+#define ETH_MACTSICNR_TSIC_Pos                        (0U)

+#define ETH_MACTSICNR_TSIC_Msk                        (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSICNR_TSIC                            ETH_MACTSICNR_TSIC_Msk  /* Timestamp Ingress Correction */

+

+/* Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond Register */

+#define ETH_MACTSECNR_TSEC_Pos                        (0U)

+#define ETH_MACTSECNR_TSEC_Msk                        (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSECNR_TSEC                            ETH_MACTSECNR_TSEC_Msk  /* Timestamp Egress Correction */

+

+/* Bit definition for Ethernet MAC PPS Control Register */

+#define ETH_MACPPSCR_TRGTMODSEL0_Pos                  (5U)

+#define ETH_MACPPSCR_TRGTMODSEL0_Msk                  (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */

+#define ETH_MACPPSCR_TRGTMODSEL0                      ETH_MACPPSCR_TRGTMODSEL0_Msk  /* Target Time Register Mode for PPS Output */

+#define ETH_MACPPSCR_PPSEN0_Pos                       (4U)

+#define ETH_MACPPSCR_PPSEN0_Msk                       (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */

+#define ETH_MACPPSCR_PPSEN0                           ETH_MACPPSCR_PPSEN0_Msk  /* Flexible PPS Output Mode Enable */

+#define ETH_MACPPSCR_PPSCTRL_Pos                      (0U)

+#define ETH_MACPPSCR_PPSCTRL_Msk                      (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */

+#define ETH_MACPPSCR_PPSCTRL                          ETH_MACPPSCR_PPSCTRL_Msk  /* PPS Output Frequency Control */

+

+/* Bit definition for Ethernet MAC PPS Target Time Seconds Register */

+#define ETH_MACPPSTTSR_TSTRH0_Pos                     (0U)

+#define ETH_MACPPSTTSR_TSTRH0_Msk                     (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACPPSTTSR_TSTRH0                         ETH_MACPPSTTSR_TSTRH0_Msk  /* PPS Target Time Seconds Register */

+

+/* Bit definition for Ethernet MAC PPS Target Time Nanoseconds Register */

+#define ETH_MACPPSTTNR_TRGTBUSY0_Pos                  (31U)

+#define ETH_MACPPSTTNR_TRGTBUSY0_Msk                  (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos) /*!< 0x80000000 */

+#define ETH_MACPPSTTNR_TRGTBUSY0                      ETH_MACPPSTTNR_TRGTBUSY0_Msk  /* PPS Target Time Register Busy */

+#define ETH_MACPPSTTNR_TTSL0_Pos                      (0U)

+#define ETH_MACPPSTTNR_TTSL0_Msk                      (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACPPSTTNR_TTSL0                          ETH_MACPPSTTNR_TTSL0_Msk  /* Target Time Low for PPS Register */

+

+/* Bit definition for Ethernet MAC PPS Interval Register */

+#define ETH_MACPPSIR_PPSINT0_Pos                      (0U)

+#define ETH_MACPPSIR_PPSINT0_Msk                      (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACPPSIR_PPSINT0                          ETH_MACPPSIR_PPSINT0_Msk  /* PPS Output Signal Interval */

+

+/* Bit definition for Ethernet MAC PPS Width Register */

+#define ETH_MACPPSWR_PPSWIDTH0_Pos                    (0U)

+#define ETH_MACPPSWR_PPSWIDTH0_Msk                    (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACPPSWR_PPSWIDTH0                        ETH_MACPPSWR_PPSWIDTH0_Msk  /* PPS Output Signal Width */

+

+/* Bit definition for Ethernet MAC PTP Offload Control Register */

+#define ETH_MACPOCR_DN_Pos                            (8U)

+#define ETH_MACPOCR_DN_Msk                            (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */

+#define ETH_MACPOCR_DN                                ETH_MACPOCR_DN_Msk  /* Domain Number */

+#define ETH_MACPOCR_DRRDIS_Pos                        (6U)

+#define ETH_MACPOCR_DRRDIS_Msk                        (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */

+#define ETH_MACPOCR_DRRDIS                            ETH_MACPOCR_DRRDIS_Msk  /* Disable PTO Delay Request/Response response generation */

+#define ETH_MACPOCR_APDREQTRIG_Pos                    (5U)

+#define ETH_MACPOCR_APDREQTRIG_Msk                    (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */

+#define ETH_MACPOCR_APDREQTRIG                        ETH_MACPOCR_APDREQTRIG_Msk  /* Automatic PTP Pdelay_Req message Trigger */

+#define ETH_MACPOCR_ASYNCTRIG_Pos                     (4U)

+#define ETH_MACPOCR_ASYNCTRIG_Msk                     (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */

+#define ETH_MACPOCR_ASYNCTRIG                         ETH_MACPOCR_ASYNCTRIG_Msk  /* Automatic PTP SYNC message Trigger */

+#define ETH_MACPOCR_APDREQEN_Pos                      (2U)

+#define ETH_MACPOCR_APDREQEN_Msk                      (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */

+#define ETH_MACPOCR_APDREQEN                          ETH_MACPOCR_APDREQEN_Msk  /* Automatic PTP Pdelay_Req message Enable */

+#define ETH_MACPOCR_ASYNCEN_Pos                       (1U)

+#define ETH_MACPOCR_ASYNCEN_Msk                       (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */

+#define ETH_MACPOCR_ASYNCEN                           ETH_MACPOCR_ASYNCEN_Msk  /* Automatic PTP SYNC message Enable */

+#define ETH_MACPOCR_PTOEN_Pos                         (0U)

+#define ETH_MACPOCR_PTOEN_Msk                         (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */

+#define ETH_MACPOCR_PTOEN                             ETH_MACPOCR_PTOEN_Msk  /* PTP Offload Enable */

+

+/* Bit definition for Ethernet MAC PTP Source Port Identity 0 Register */

+#define ETH_MACSPI0R_SPI0_Pos                         (0U)

+#define ETH_MACSPI0R_SPI0_Msk                         (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSPI0R_SPI0                             ETH_MACSPI0R_SPI0_Msk  /* Source Port Identity 0 */

+

+/* Bit definition for Ethernet MAC PTP Source Port Identity 1 Register */

+#define ETH_MACSPI1R_SPI1_Pos                         (0U)

+#define ETH_MACSPI1R_SPI1_Msk                         (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSPI1R_SPI1                             ETH_MACSPI1R_SPI1_Msk  /* Source Port Identity 1 */

+

+/* Bit definition for Ethernet MAC PTP Source Port Identity 2 Register */

+#define ETH_MACSPI2R_SPI2_Pos                         (0U)

+#define ETH_MACSPI2R_SPI2_Msk                         (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */

+#define ETH_MACSPI2R_SPI2                             ETH_MACSPI2R_SPI2_Msk  /* Source Port Identity 2 */

+

+/* Bit definition for Ethernet MAC Log Message Interval Register */

+#define ETH_MACLMIR_LMPDRI_Pos                        (24U)

+#define ETH_MACLMIR_LMPDRI_Msk                        (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */

+#define ETH_MACLMIR_LMPDRI                             ETH_MACLMIR_LMPDRI_Msk  /* Log Min Pdelay_Req Interval */

+#define ETH_MACLMIR_DRSYNCR_Pos                       (8U)

+#define ETH_MACLMIR_DRSYNCR_Msk                       (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */

+#define ETH_MACLMIR_DRSYNCR                           ETH_MACLMIR_DRSYNCR_Msk  /* Delay_Req to SYNC Ratio */

+#define ETH_MACLMIR_LSI_Pos                           (0U)

+#define ETH_MACLMIR_LSI_Msk                           (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */

+#define ETH_MACLMIR_LSI                               ETH_MACLMIR_LSI_Msk  /* Log Sync Interval */

+

+/* Bit definition for Ethernet MTL Operation Mode Register */

+#define ETH_MTLOMR_CNTCLR_Pos                         (9U)

+#define ETH_MTLOMR_CNTCLR_Msk                         (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */

+#define ETH_MTLOMR_CNTCLR                             ETH_MTLOMR_CNTCLR_Msk    /* Counters Reset */

+#define ETH_MTLOMR_CNTPRST_Pos                        (8U)

+#define ETH_MTLOMR_CNTPRST_Msk                        (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */

+#define ETH_MTLOMR_CNTPRST                            ETH_MTLOMR_CNTPRST_Msk   /* Counters Preset */

+#define ETH_MTLOMR_DTXSTS_Pos                         (1U)

+#define ETH_MTLOMR_DTXSTS_Msk                         (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */

+#define ETH_MTLOMR_DTXSTS                             ETH_MTLOMR_DTXSTS_Msk  /* Drop Transmit Status */

+

+/* Bit definition for Ethernet MTL Interrupt Status Register */

+#define ETH_MTLISR_MACIS_Pos                          (16U)

+#define ETH_MTLISR_MACIS_Msk                          (0x1UL << ETH_MTLISR_MACIS_Pos) /*!< 0x00010000 */

+#define ETH_MTLISR_MACIS                              ETH_MTLISR_MACIS_Msk     /* MAC Interrupt Status */

+#define ETH_MTLISR_QIS_Pos                            (0U)

+#define ETH_MTLISR_QIS_Msk                            (0x1UL << ETH_MTLISR_QIS_Pos) /*!< 0x00000001 */

+#define ETH_MTLISR_QIS                                ETH_MTLISR_QIS_Msk       /* Queue Interrupt status */

+

+/* Bit definition for Ethernet MTL Tx Queue Operation Mode Register */

+#define ETH_MTLTQOMR_TTC_Pos                          (4U)

+#define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */

+#define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */

+#define ETH_MTLTQOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */

+#define ETH_MTLTQOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */

+#define ETH_MTLTQOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */

+#define ETH_MTLTQOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */

+#define ETH_MTLTQOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */

+#define ETH_MTLTQOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */

+#define ETH_MTLTQOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */

+#define ETH_MTLTQOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */

+#define ETH_MTLTQOMR_TSF_Pos                          (1U)

+#define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */

+#define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */

+#define ETH_MTLTQOMR_FTQ_Pos                          (0U)

+#define ETH_MTLTQOMR_FTQ_Msk                          (0x1UL << ETH_MTLTQOMR_FTQ_Pos) /*!< 0x00000001 */

+#define ETH_MTLTQOMR_FTQ                              ETH_MTLTQOMR_FTQ_Msk     /* Flush Transmit Queue */

+

+/* Bit definition for Ethernet MTL Tx Queue Underflow Register */

+#define ETH_MTLTQUR_UFCNTOVF_Pos                      (11U)

+#define ETH_MTLTQUR_UFCNTOVF_Msk                      (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos) /*!< 0x00000800 */

+#define ETH_MTLTQUR_UFCNTOVF                          ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */

+#define ETH_MTLTQUR_UFPKTCNT_Pos                      (0U)

+#define ETH_MTLTQUR_UFPKTCNT_Msk                      (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos) /*!< 0x000007FF */

+#define ETH_MTLTQUR_UFPKTCNT                          ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */

+

+/* Bit definition for Ethernet MTL Tx Queue Debug Register */

+#define ETH_MTLTQDR_STXSTSF_Pos                       (20U)

+#define ETH_MTLTQDR_STXSTSF_Msk                       (0x7UL << ETH_MTLTQDR_STXSTSF_Pos) /*!< 0x00700000 */

+#define ETH_MTLTQDR_STXSTSF                           ETH_MTLTQDR_STXSTSF_Msk  /* Number of Status Words in the Tx Status FIFO of Queue */

+#define ETH_MTLTQDR_PTXQ_Pos                          (16U)

+#define ETH_MTLTQDR_PTXQ_Msk                          (0x7UL << ETH_MTLTQDR_PTXQ_Pos) /*!< 0x00070000 */

+#define ETH_MTLTQDR_PTXQ                              ETH_MTLTQDR_PTXQ_Msk     /* Number of Packets in the Transmit Queue */

+#define ETH_MTLTQDR_TXSTSFSTS_Pos                     (5U)

+#define ETH_MTLTQDR_TXSTSFSTS_Msk                     (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos) /*!< 0x00000020 */

+#define ETH_MTLTQDR_TXSTSFSTS                         ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */

+#define ETH_MTLTQDR_TXQSTS_Pos                        (4U)

+#define ETH_MTLTQDR_TXQSTS_Msk                        (0x1UL << ETH_MTLTQDR_TXQSTS_Pos) /*!< 0x00000010 */

+#define ETH_MTLTQDR_TXQSTS                            ETH_MTLTQDR_TXQSTS_Msk   /* MTL Tx Queue Not Empty Status */

+#define ETH_MTLTQDR_TWCSTS_Pos                        (3U)

+#define ETH_MTLTQDR_TWCSTS_Msk                        (0x1UL << ETH_MTLTQDR_TWCSTS_Pos) /*!< 0x00000008 */

+#define ETH_MTLTQDR_TWCSTS                            ETH_MTLTQDR_TWCSTS_Msk   /* MTL Tx Queue Write Controller Status */

+#define ETH_MTLTQDR_TRCSTS_Pos                        (1U)

+#define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */

+#define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */

+#define ETH_MTLTQDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */

+#define ETH_MTLTQDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */

+#define ETH_MTLTQDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */

+#define ETH_MTLTQDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */

+#define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)

+#define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */

+#define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */

+

+/* Bit definition for Ethernet MTL Queue Interrupt Control Status Register */

+#define ETH_MTLQICSR_RXOIE_Pos                        (24U)

+#define ETH_MTLQICSR_RXOIE_Msk                        (0x1UL << ETH_MTLQICSR_RXOIE_Pos) /*!< 0x01000000 */

+#define ETH_MTLQICSR_RXOIE                            ETH_MTLQICSR_RXOIE_Msk   /* Receive Queue Overflow Interrupt Enable */

+#define ETH_MTLQICSR_RXOVFIS_Pos                      (16U)

+#define ETH_MTLQICSR_RXOVFIS_Msk                      (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos) /*!< 0x00010000 */

+#define ETH_MTLQICSR_RXOVFIS                          ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */

+#define ETH_MTLQICSR_TXUIE_Pos                        (8U)

+#define ETH_MTLQICSR_TXUIE_Msk                        (0x1UL << ETH_MTLQICSR_TXUIE_Pos) /*!< 0x00000100 */

+#define ETH_MTLQICSR_TXUIE                            ETH_MTLQICSR_TXUIE_Msk   /* Transmit Queue Underflow Interrupt Enable */

+#define ETH_MTLQICSR_TXUNFIS_Pos                      (0U)

+#define ETH_MTLQICSR_TXUNFIS_Msk                      (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos) /*!< 0x00000001 */

+#define ETH_MTLQICSR_TXUNFIS                          ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */

+

+/* Bit definition for Ethernet MTL Rx Queue Operation Mode Register */

+#define ETH_MTLRQOMR_RQS_Pos                          (20U)

+#define ETH_MTLRQOMR_RQS_Msk                          (0x7UL << ETH_MTLRQOMR_RQS_Pos) /*!< 0x00700000 */

+#define ETH_MTLRQOMR_RQS                              ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */

+#define ETH_MTLRQOMR_RFD_Pos                          (14U)

+#define ETH_MTLRQOMR_RFD_Msk                          (0x7UL << ETH_MTLRQOMR_RFD_Pos) /*!< 0x0001C000 */

+#define ETH_MTLRQOMR_RFD                              ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */

+#define ETH_MTLRQOMR_RFA_Pos                          (8U)

+#define ETH_MTLRQOMR_RFA_Msk                          (0x7UL << ETH_MTLRQOMR_RFA_Pos) /*!< 0x00000700 */

+#define ETH_MTLRQOMR_RFA                              ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */

+#define ETH_MTLRQOMR_EHFC_Pos                         (7U)

+#define ETH_MTLRQOMR_EHFC_Msk                         (0x1UL << ETH_MTLRQOMR_EHFC_Pos) /*!< 0x00000080 */

+#define ETH_MTLRQOMR_EHFC                             ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */

+#define ETH_MTLRQOMR_DISTCPEF_Pos                     (6U)

+#define ETH_MTLRQOMR_DISTCPEF_Msk                     (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos) /*!< 0x00000040 */

+#define ETH_MTLRQOMR_DISTCPEF                         ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */

+#define ETH_MTLRQOMR_RSF_Pos                          (5U)

+#define ETH_MTLRQOMR_RSF_Msk                          (0x1UL << ETH_MTLRQOMR_RSF_Pos) /*!< 0x00000020 */

+#define ETH_MTLRQOMR_RSF                              ETH_MTLRQOMR_RSF_Msk     /* Receive Queue Store and Forward */

+#define ETH_MTLRQOMR_FEP_Pos                          (4U)

+#define ETH_MTLRQOMR_FEP_Msk                          (0x1UL << ETH_MTLRQOMR_FEP_Pos) /*!< 0x00000010 */

+#define ETH_MTLRQOMR_FEP                              ETH_MTLRQOMR_FEP_Msk     /* Forward Error Packets */

+#define ETH_MTLRQOMR_FUP_Pos                          (3U)

+#define ETH_MTLRQOMR_FUP_Msk                          (0x1UL << ETH_MTLRQOMR_FUP_Pos) /*!< 0x00000008 */

+#define ETH_MTLRQOMR_FUP                              ETH_MTLRQOMR_FUP_Msk     /* Forward Undersized Good Packets */

+#define ETH_MTLRQOMR_RTC_Pos                          (0U)

+#define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */

+#define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */

+#define ETH_MTLRQOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */

+#define ETH_MTLRQOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */

+#define ETH_MTLRQOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */

+#define ETH_MTLRQOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */

+

+/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */

+#define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)

+#define ETH_MTLRQMPOCR_MISCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */

+#define ETH_MTLRQMPOCR_MISCNTOVF                      ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */

+#define ETH_MTLRQMPOCR_MISPKTCNT_Pos                  (16U)

+#define ETH_MTLRQMPOCR_MISPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */

+#define ETH_MTLRQMPOCR_MISPKTCNT                      ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */

+#define ETH_MTLRQMPOCR_OVFCNTOVF_Pos                  (11U)

+#define ETH_MTLRQMPOCR_OVFCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */

+#define ETH_MTLRQMPOCR_OVFCNTOVF                      ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */

+#define ETH_MTLRQMPOCR_OVFPKTCNT_Pos                  (0U)

+#define ETH_MTLRQMPOCR_OVFPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */

+#define ETH_MTLRQMPOCR_OVFPKTCNT                      ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */

+

+/* Bit definition for Ethernet MTL Rx Queue Debug Register */

+#define ETH_MTLRQDR_PRXQ_Pos                          (16U)

+#define ETH_MTLRQDR_PRXQ_Msk                          (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos) /*!< 0x3FFF0000 */

+#define ETH_MTLRQDR_PRXQ                              ETH_MTLRQDR_PRXQ_Msk     /* Number of Packets in Receive Queue */

+#define ETH_MTLRQDR_RXQSTS_Pos                        (4U)

+#define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */

+#define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */

+#define ETH_MTLRQDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */

+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)

+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */

+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */

+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos         (5U)

+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */

+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD             ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */

+#define ETH_MTLRQDR_RXQSTS_FULL_Pos                   (4U)

+#define ETH_MTLRQDR_RXQSTS_FULL_Msk                   (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */

+#define ETH_MTLRQDR_RXQSTS_FULL                       ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */

+#define ETH_MTLRQDR_RRCSTS_Pos                        (1U)

+#define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */

+#define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */

+#define ETH_MTLRQDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */

+#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)

+#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */

+#define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */

+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos          (2U)

+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk          (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */

+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS              ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */

+#define ETH_MTLRQDR_RRCSTS_FLUSHING_Pos               (1U)

+#define ETH_MTLRQDR_RRCSTS_FLUSHING_Msk               (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */

+#define ETH_MTLRQDR_RRCSTS_FLUSHING                   ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */

+#define ETH_MTLRQDR_RWCSTS_Pos                        (0U)

+#define ETH_MTLRQDR_RWCSTS_Msk                        (0x1UL << ETH_MTLRQDR_RWCSTS_Pos) /*!< 0x00000001 */

+#define ETH_MTLRQDR_RWCSTS                            ETH_MTLRQDR_RWCSTS_Msk   /* MTL Rx Queue Write Controller Active Status */

+

+/* Bit definition for Ethernet MTL Rx Queue Control Register */

+#define ETH_MTLRQCR_RQPA_Pos                          (3U)

+#define ETH_MTLRQCR_RQPA_Msk                          (0x1UL << ETH_MTLRQCR_RQPA_Pos) /*!< 0x00000008 */

+#define ETH_MTLRQCR_RQPA                              ETH_MTLRQCR_RQPA_Msk     /* Receive Queue Packet Arbitration */

+#define ETH_MTLRQCR_RQW_Pos                           (0U)

+#define ETH_MTLRQCR_RQW_Msk                           (0x7UL << ETH_MTLRQCR_RQW_Pos) /*!< 0x00000007 */

+#define ETH_MTLRQCR_RQW                               ETH_MTLRQCR_RQW_Msk      /* Receive Queue Weight */

+

+/* Bit definition for Ethernet DMA Mode Register */

+#define ETH_DMAMR_INTM_Pos                            (16U)

+#define ETH_DMAMR_INTM_Msk                            (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */

+#define ETH_DMAMR_INTM                                ETH_DMAMR_INTM_Msk       /* This field defines the interrupt mode */

+#define ETH_DMAMR_INTM_0                              (0x0UL << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */

+#define ETH_DMAMR_INTM_1                              (0x1UL << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */

+#define ETH_DMAMR_INTM_2                              (0x2UL << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */

+#define ETH_DMAMR_PR_Pos                              (12U)

+#define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */

+#define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */

+#define ETH_DMAMR_PR_1_1                              ((uint32_t)0x00000000)   /* The priority ratio is 1:1 */

+#define ETH_DMAMR_PR_2_1                              ((uint32_t)0x00001000)   /* The priority ratio is 2:1 */

+#define ETH_DMAMR_PR_3_1                              ((uint32_t)0x00002000)   /* The priority ratio is 3:1 */

+#define ETH_DMAMR_PR_4_1                              ((uint32_t)0x00003000)   /* The priority ratio is 4:1 */

+#define ETH_DMAMR_PR_5_1                              ((uint32_t)0x00004000)   /* The priority ratio is 5:1 */

+#define ETH_DMAMR_PR_6_1                              ((uint32_t)0x00005000)   /* The priority ratio is 6:1 */

+#define ETH_DMAMR_PR_7_1                              ((uint32_t)0x00006000)   /* The priority ratio is 7:1 */

+#define ETH_DMAMR_PR_8_1                              ((uint32_t)0x00007000)   /* The priority ratio is 8:1 */

+#define ETH_DMAMR_TXPR_Pos                            (11U)

+#define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */

+#define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */

+#define ETH_DMAMR_DA_Pos                              (1U)

+#define ETH_DMAMR_DA_Msk                              (0x1UL << ETH_DMAMR_DA_Pos) /*!< 0x00000002 */

+#define ETH_DMAMR_DA                                  ETH_DMAMR_DA_Msk         /* DMA Tx or Rx Arbitration Scheme */

+#define ETH_DMAMR_SWR_Pos                             (0U)

+#define ETH_DMAMR_SWR_Msk                             (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */

+#define ETH_DMAMR_SWR                                 ETH_DMAMR_SWR_Msk        /* Software Reset */

+

+/* Bit definition for Ethernet DMA SysBus Mode Register */

+#define ETH_DMASBMR_RB_Pos                            (15U)

+#define ETH_DMASBMR_RB_Msk                            (0x1UL << ETH_DMASBMR_RB_Pos) /*!< 0x00008000 */

+#define ETH_DMASBMR_RB                                ETH_DMASBMR_RB_Msk       /* Rebuild INCRx Burst */

+#define ETH_DMASBMR_MB_Pos                            (14U)

+#define ETH_DMASBMR_MB_Msk                            (0x1UL << ETH_DMASBMR_MB_Pos) /*!< 0x00004000 */

+#define ETH_DMASBMR_MB                                ETH_DMASBMR_MB_Msk       /* Mixed Burst */

+#define ETH_DMASBMR_AAL_Pos                           (12U)

+#define ETH_DMASBMR_AAL_Msk                           (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */

+#define ETH_DMASBMR_AAL                               ETH_DMASBMR_AAL_Msk      /* Address-Aligned Beats */

+#define ETH_DMASBMR_FB_Pos                            (0U)

+#define ETH_DMASBMR_FB_Msk                            (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */

+#define ETH_DMASBMR_FB                                ETH_DMASBMR_FB_Msk       /* Fixed Burst Length */

+

+/* Bit definition for Ethernet DMA Interrupt Status Register */

+#define ETH_DMAISR_MACIS_Pos                          (17U)

+#define ETH_DMAISR_MACIS_Msk                          (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */

+#define ETH_DMAISR_MACIS                              ETH_DMAISR_MACIS_Msk     /* MAC Interrupt Status */

+#define ETH_DMAISR_MTLIS_Pos                          (16U)

+#define ETH_DMAISR_MTLIS_Msk                          (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */

+#define ETH_DMAISR_MTLIS                              ETH_DMAISR_MTLIS_Msk     /* MAC Interrupt Status */

+#define ETH_DMAISR_DMACIS_Pos                         (0U)

+#define ETH_DMAISR_DMACIS_Msk                         (0x1UL << ETH_DMAISR_DMACIS_Pos) /*!< 0x00000001 */

+#define ETH_DMAISR_DMACIS                             ETH_DMAISR_DMACIS_Msk    /* DMA Channel Interrupt Status */

+

+/* Bit definition for Ethernet DMA Debug Status Register */

+#define ETH_DMADSR_TPS_Pos                            (12U)

+#define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */

+#define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */

+#define ETH_DMADSR_TPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */

+#define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)

+#define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */

+#define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */

+#define ETH_DMADSR_TPS_WAITING_Pos                    (13U)

+#define ETH_DMADSR_TPS_WAITING_Msk                    (0x1UL << ETH_DMADSR_TPS_WAITING_Pos) /*!< 0x00002000 */

+#define ETH_DMADSR_TPS_WAITING                        ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */

+#define ETH_DMADSR_TPS_READING_Pos                    (12U)

+#define ETH_DMADSR_TPS_READING_Msk                    (0x3UL << ETH_DMADSR_TPS_READING_Pos) /*!< 0x00003000 */

+#define ETH_DMADSR_TPS_READING                        ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */

+#define ETH_DMADSR_TPS_TIMESTAMP_WR_Pos               (14U)

+#define ETH_DMADSR_TPS_TIMESTAMP_WR_Msk               (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos) /*!< 0x00004000 */

+#define ETH_DMADSR_TPS_TIMESTAMP_WR                   ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */

+#define ETH_DMADSR_TPS_SUSPENDED_Pos                  (13U)

+#define ETH_DMADSR_TPS_SUSPENDED_Msk                  (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos) /*!< 0x00006000 */

+#define ETH_DMADSR_TPS_SUSPENDED                      ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */

+#define ETH_DMADSR_TPS_CLOSING_Pos                    (12U)

+#define ETH_DMADSR_TPS_CLOSING_Msk                    (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos) /*!< 0x00007000 */

+#define ETH_DMADSR_TPS_CLOSING                        ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */

+#define ETH_DMADSR_RPS_Pos                            (8U)

+#define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */

+#define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */

+#define ETH_DMADSR_RPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */

+#define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)

+#define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */

+#define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */

+#define ETH_DMADSR_RPS_WAITING_Pos                    (12U)

+#define ETH_DMADSR_RPS_WAITING_Msk                    (0x3UL << ETH_DMADSR_RPS_WAITING_Pos) /*!< 0x00003000 */

+#define ETH_DMADSR_RPS_WAITING                        ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */

+#define ETH_DMADSR_RPS_SUSPENDED_Pos                  (14U)

+#define ETH_DMADSR_RPS_SUSPENDED_Msk                  (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos) /*!< 0x00004000 */

+#define ETH_DMADSR_RPS_SUSPENDED                      ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */

+#define ETH_DMADSR_RPS_CLOSING_Pos                    (12U)

+#define ETH_DMADSR_RPS_CLOSING_Msk                    (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos) /*!< 0x00005000 */

+#define ETH_DMADSR_RPS_CLOSING                        ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */

+#define ETH_DMADSR_RPS_TIMESTAMP_WR_Pos               (13U)

+#define ETH_DMADSR_RPS_TIMESTAMP_WR_Msk               (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos) /*!< 0x00006000 */

+#define ETH_DMADSR_RPS_TIMESTAMP_WR                   ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */

+#define ETH_DMADSR_RPS_TRANSFERRING_Pos               (12U)

+#define ETH_DMADSR_RPS_TRANSFERRING_Msk               (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos) /*!< 0x00007000 */

+#define ETH_DMADSR_RPS_TRANSFERRING                   ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */

+

+/* Bit definition for Ethernet DMA Channel Control Register */

+#define ETH_DMACCR_DSL_Pos                            (18U)

+#define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */

+#define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */

+#define ETH_DMACCR_DSL_0BIT                           ((uint32_t)0x00000000)

+#define ETH_DMACCR_DSL_32BIT                          ((uint32_t)0x00040000)

+#define ETH_DMACCR_DSL_64BIT                          ((uint32_t)0x00080000)

+#define ETH_DMACCR_DSL_128BIT                         ((uint32_t)0x00100000)

+#define ETH_DMACCR_8PBL                               ((uint32_t)0x00010000)   /* 8xPBL mode */

+#define ETH_DMACCR_MSS_Pos                            (0U)

+#define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */

+#define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */

+

+/* Bit definition for Ethernet DMA Channel Tx Control Register */

+#define ETH_DMACTCR_TPBL_Pos                          (16U)

+#define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */

+#define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */

+#define ETH_DMACTCR_TPBL_1PBL                         ((uint32_t)0x00010000)   /* Transmit Programmable Burst Length 1 */

+#define ETH_DMACTCR_TPBL_2PBL                         ((uint32_t)0x00020000)   /* Transmit Programmable Burst Length 2 */

+#define ETH_DMACTCR_TPBL_4PBL                         ((uint32_t)0x00040000)   /* Transmit Programmable Burst Length 4 */

+#define ETH_DMACTCR_TPBL_8PBL                         ((uint32_t)0x00080000)   /* Transmit Programmable Burst Length 8 */

+#define ETH_DMACTCR_TPBL_16PBL                        ((uint32_t)0x00100000)   /* Transmit Programmable Burst Length 16 */

+#define ETH_DMACTCR_TPBL_32PBL                        ((uint32_t)0x00200000)   /* Transmit Programmable Burst Length 32 */

+#define ETH_DMACTCR_TSE_Pos                           (12U)

+#define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */

+#define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */

+#define ETH_DMACTCR_OSP_Pos                           (4U)

+#define ETH_DMACTCR_OSP_Msk                           (0x1UL << ETH_DMACTCR_OSP_Pos) /*!< 0x00000010 */

+#define ETH_DMACTCR_OSP                               ETH_DMACTCR_OSP_Msk      /* Operate on Second Packet */

+#define ETH_DMACTCR_ST_Pos                            (0U)

+#define ETH_DMACTCR_ST_Msk                            (0x1UL << ETH_DMACTCR_ST_Pos) /*!< 0x00000001 */

+#define ETH_DMACTCR_ST                                ETH_DMACTCR_ST_Msk       /* Start or Stop Transmission Command */

+

+/* Bit definition for Ethernet DMA Channel Rx Control Register */

+#define ETH_DMACRCR_RPF_Pos                           (31U)

+#define ETH_DMACRCR_RPF_Msk                           (0x1UL << ETH_DMACRCR_RPF_Pos) /*!< 0x80000000 */

+#define ETH_DMACRCR_RPF                               ETH_DMACRCR_RPF_Msk      /* Rx Packet Flush */

+#define ETH_DMACRCR_RPBL_Pos                          (16U)

+#define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */

+#define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */

+#define ETH_DMACRCR_RPBL_1PBL                         ((uint32_t)0x00010000)   /* Receive Programmable Burst Length 1 */

+#define ETH_DMACRCR_RPBL_2PBL                         ((uint32_t)0x00020000)   /* Receive Programmable Burst Length 2 */

+#define ETH_DMACRCR_RPBL_4PBL                         ((uint32_t)0x00040000)   /* Receive Programmable Burst Length 4 */

+#define ETH_DMACRCR_RPBL_8PBL                         ((uint32_t)0x00080000)   /* Receive Programmable Burst Length 8 */

+#define ETH_DMACRCR_RPBL_16PBL                        ((uint32_t)0x00100000)   /* Receive Programmable Burst Length 16 */

+#define ETH_DMACRCR_RPBL_32PBL                        ((uint32_t)0x00200000)   /* Receive Programmable Burst Length 32 */

+#define ETH_DMACRCR_RBSZ_Pos                          (1U)

+#define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */

+#define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */

+#define ETH_DMACRCR_SR_Pos                            (0U)

+#define ETH_DMACRCR_SR_Msk                            (0x1UL << ETH_DMACRCR_SR_Pos) /*!< 0x00000001 */

+#define ETH_DMACRCR_SR                                ETH_DMACRCR_SR_Msk       /* Start or Stop Receive */

+

+/* Bit definition for Ethernet DMA CH Tx Desc List Address Register */

+#define ETH_DMACTDLAR_TDESLA_Pos                      (2U)

+#define ETH_DMACTDLAR_TDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACTDLAR_TDESLA                          ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */

+

+/* Bit definition for Ethernet DMA CH Rx Desc List Address Register */

+#define ETH_DMACRDLAR_RDESLA_Pos                      (2U)

+#define ETH_DMACRDLAR_RDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACRDLAR_RDESLA                          ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */

+

+/* Bit definition for Ethernet DMA CH Tx Desc Tail Pointer Register */

+#define ETH_DMACTDTPR_TDT_Pos                         (2U)

+#define ETH_DMACTDTPR_TDT_Msk                         (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACTDTPR_TDT                             ETH_DMACTDTPR_TDT_Msk    /* Transmit Descriptor Tail Pointer */

+

+/* Bit definition for Ethernet DMA CH Rx Desc Tail Pointer Register */

+#define ETH_DMACRDTPR_RDT_Pos                         (2U)

+#define ETH_DMACRDTPR_RDT_Msk                         (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACRDTPR_RDT                             ETH_DMACRDTPR_RDT_Msk    /* Receive Descriptor Tail Pointer */

+

+/* Bit definition for Ethernet DMA CH Tx Desc Ring Length Register */

+#define ETH_DMACTDRLR_TDRL_Pos                        (0U)

+#define ETH_DMACTDRLR_TDRL_Msk                        (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos) /*!< 0x000003FF */

+#define ETH_DMACTDRLR_TDRL                            ETH_DMACTDRLR_TDRL_Msk   /* Transmit Descriptor Ring Length */

+

+/* Bit definition for Ethernet DMA CH Rx Desc Ring Length Register */

+#define ETH_DMACRDRLR_RDRL_Pos                        (0U)

+#define ETH_DMACRDRLR_RDRL_Msk                        (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos) /*!< 0x000003FF */

+#define ETH_DMACRDRLR_RDRL                            ETH_DMACRDRLR_RDRL_Msk   /* Receive Descriptor Ring Length */

+

+/* Bit definition for Ethernet DMA Channel Interrupt Enable Register */

+#define ETH_DMACIER_NIE_Pos                           (15U)

+#define ETH_DMACIER_NIE_Msk                           (0x1UL << ETH_DMACIER_NIE_Pos) /*!< 0x00008000 */

+#define ETH_DMACIER_NIE                               ETH_DMACIER_NIE_Msk      /* Normal Interrupt Summary Enable */

+#define ETH_DMACIER_AIE_Pos                           (14U)

+#define ETH_DMACIER_AIE_Msk                           (0x1UL << ETH_DMACIER_AIE_Pos) /*!< 0x00004000 */

+#define ETH_DMACIER_AIE                               ETH_DMACIER_AIE_Msk      /* Abnormal Interrupt Summary Enable */

+#define ETH_DMACIER_CDEE_Pos                          (13U)

+#define ETH_DMACIER_CDEE_Msk                          (0x1UL << ETH_DMACIER_CDEE_Pos) /*!< 0x00002000 */

+#define ETH_DMACIER_CDEE                              ETH_DMACIER_CDEE_Msk     /* Context Descriptor Error Enable */

+#define ETH_DMACIER_FBEE_Pos                          (12U)

+#define ETH_DMACIER_FBEE_Msk                          (0x1UL << ETH_DMACIER_FBEE_Pos) /*!< 0x00001000 */

+#define ETH_DMACIER_FBEE                              ETH_DMACIER_FBEE_Msk     /* Fatal Bus Error Enable */

+#define ETH_DMACIER_ERIE_Pos                          (11U)

+#define ETH_DMACIER_ERIE_Msk                          (0x1UL << ETH_DMACIER_ERIE_Pos) /*!< 0x00000800 */

+#define ETH_DMACIER_ERIE                              ETH_DMACIER_ERIE_Msk     /* Early Receive Interrupt Enable */

+#define ETH_DMACIER_ETIE_Pos                          (10U)

+#define ETH_DMACIER_ETIE_Msk                          (0x1UL << ETH_DMACIER_ETIE_Pos) /*!< 0x00000400 */

+#define ETH_DMACIER_ETIE                              ETH_DMACIER_ETIE_Msk     /* Early Transmit Interrupt Enable */

+#define ETH_DMACIER_RWTE_Pos                          (9U)

+#define ETH_DMACIER_RWTE_Msk                          (0x1UL << ETH_DMACIER_RWTE_Pos) /*!< 0x00000200 */

+#define ETH_DMACIER_RWTE                              ETH_DMACIER_RWTE_Msk     /* Receive Watchdog Timeout Enable */

+#define ETH_DMACIER_RSE_Pos                           (8U)

+#define ETH_DMACIER_RSE_Msk                           (0x1UL << ETH_DMACIER_RSE_Pos) /*!< 0x00000100 */

+#define ETH_DMACIER_RSE                               ETH_DMACIER_RSE_Msk      /* Receive Stopped Enable */

+#define ETH_DMACIER_RBUE_Pos                          (7U)

+#define ETH_DMACIER_RBUE_Msk                          (0x1UL << ETH_DMACIER_RBUE_Pos) /*!< 0x00000080 */

+#define ETH_DMACIER_RBUE                              ETH_DMACIER_RBUE_Msk     /* Receive Buffer Unavailable Enable */

+#define ETH_DMACIER_RIE_Pos                           (6U)

+#define ETH_DMACIER_RIE_Msk                           (0x1UL << ETH_DMACIER_RIE_Pos) /*!< 0x00000040 */

+#define ETH_DMACIER_RIE                               ETH_DMACIER_RIE_Msk      /* Receive Interrupt Enable */

+#define ETH_DMACIER_TBUE_Pos                          (2U)

+#define ETH_DMACIER_TBUE_Msk                          (0x1UL << ETH_DMACIER_TBUE_Pos) /*!< 0x00000004 */

+#define ETH_DMACIER_TBUE                              ETH_DMACIER_TBUE_Msk     /* Transmit Buffer Unavailable Enable */

+#define ETH_DMACIER_TXSE_Pos                          (1U)

+#define ETH_DMACIER_TXSE_Msk                          (0x1UL << ETH_DMACIER_TXSE_Pos) /*!< 0x00000002 */

+#define ETH_DMACIER_TXSE                              ETH_DMACIER_TXSE_Msk     /* Transmit Stopped Enable */

+#define ETH_DMACIER_TIE_Pos                           (0U)

+#define ETH_DMACIER_TIE_Msk                           (0x1UL << ETH_DMACIER_TIE_Pos) /*!< 0x00000001 */

+#define ETH_DMACIER_TIE                               ETH_DMACIER_TIE_Msk      /* Transmit Interrupt Enable */

+

+/* Bit definition for Ethernet DMA Channel Rx Interrupt Watchdog Timer Register */

+#define ETH_DMACRIWTR_RWT_Pos                         (0U)

+#define ETH_DMACRIWTR_RWT_Msk                         (0xFFUL << ETH_DMACRIWTR_RWT_Pos) /*!< 0x000000FF */

+#define ETH_DMACRIWTR_RWT                             ETH_DMACRIWTR_RWT_Msk    /* Receive Interrupt Watchdog Timer Count */

+

+/* Bit definition for Ethernet DMA Channel Current App Tx Desc Register */

+#define ETH_DMACCATDR_CURTDESAPTR_Pos                 (0U)

+#define ETH_DMACCATDR_CURTDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCATDR_CURTDESAPTR                     ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Current App Rx Desc Register */

+#define ETH_DMACCARDR_CURRDESAPTR_Pos                 (0U)

+#define ETH_DMACCARDR_CURRDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCARDR_CURRDESAPTR                     ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Current App Tx Buffer Register */

+#define ETH_DMACCATBR_CURTBUFAPTR_Pos                 (0U)

+#define ETH_DMACCATBR_CURTBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCATBR_CURTBUFAPTR                     ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Current App Rx Buffer Register */

+#define ETH_DMACCARBR_CURRBUFAPTR_Pos                 (0U)

+#define ETH_DMACCARBR_CURRBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCARBR_CURRBUFAPTR                     ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Status Register */

+#define ETH_DMACSR_REB_Pos                            (19U)

+#define ETH_DMACSR_REB_Msk                            (0x7UL << ETH_DMACSR_REB_Pos) /*!< 0x00380000 */

+#define ETH_DMACSR_REB                                ETH_DMACSR_REB_Msk       /* Rx DMA Error Bits */

+#define ETH_DMACSR_TEB_Pos                            (16U)

+#define ETH_DMACSR_TEB_Msk                            (0x7UL << ETH_DMACSR_TEB_Pos) /*!< 0x00070000 */

+#define ETH_DMACSR_TEB                                ETH_DMACSR_TEB_Msk       /* Tx DMA Error Bits */

+#define ETH_DMACSR_NIS_Pos                            (15U)

+#define ETH_DMACSR_NIS_Msk                            (0x1UL << ETH_DMACSR_NIS_Pos) /*!< 0x00008000 */

+#define ETH_DMACSR_NIS                                ETH_DMACSR_NIS_Msk       /* Normal Interrupt Summary */

+#define ETH_DMACSR_AIS_Pos                            (14U)

+#define ETH_DMACSR_AIS_Msk                            (0x1UL << ETH_DMACSR_AIS_Pos) /*!< 0x00004000 */

+#define ETH_DMACSR_AIS                                ETH_DMACSR_AIS_Msk       /* Abnormal Interrupt Summary */

+#define ETH_DMACSR_CDE_Pos                            (13U)

+#define ETH_DMACSR_CDE_Msk                            (0x1UL << ETH_DMACSR_CDE_Pos) /*!< 0x00002000 */

+#define ETH_DMACSR_CDE                                ETH_DMACSR_CDE_Msk       /* Context Descriptor Error */

+#define ETH_DMACSR_FBE_Pos                            (12U)

+#define ETH_DMACSR_FBE_Msk                            (0x1UL << ETH_DMACSR_FBE_Pos) /*!< 0x00001000 */

+#define ETH_DMACSR_FBE                                ETH_DMACSR_FBE_Msk       /* Fatal Bus Error */

+#define ETH_DMACSR_ERI_Pos                            (11U)

+#define ETH_DMACSR_ERI_Msk                            (0x1UL << ETH_DMACSR_ERI_Pos) /*!< 0x00000800 */

+#define ETH_DMACSR_ERI                                ETH_DMACSR_ERI_Msk       /* Early Receive Interrupt */

+#define ETH_DMACSR_ETI_Pos                            (10U)

+#define ETH_DMACSR_ETI_Msk                            (0x1UL << ETH_DMACSR_ETI_Pos) /*!< 0x00000400 */

+#define ETH_DMACSR_ETI                                ETH_DMACSR_ETI_Msk       /* Early Transmit Interrupt */

+#define ETH_DMACSR_RWT_Pos                            (9U)

+#define ETH_DMACSR_RWT_Msk                            (0x1UL << ETH_DMACSR_RWT_Pos) /*!< 0x00000200 */

+#define ETH_DMACSR_RWT                                ETH_DMACSR_RWT_Msk       /* Receive Watchdog Timeout */

+#define ETH_DMACSR_RPS_Pos                            (8U)

+#define ETH_DMACSR_RPS_Msk                            (0x1UL << ETH_DMACSR_RPS_Pos) /*!< 0x00000100 */

+#define ETH_DMACSR_RPS                                ETH_DMACSR_RPS_Msk       /* Receive Process Stopped */

+#define ETH_DMACSR_RBU_Pos                            (7U)

+#define ETH_DMACSR_RBU_Msk                            (0x1UL << ETH_DMACSR_RBU_Pos) /*!< 0x00000080 */

+#define ETH_DMACSR_RBU                                ETH_DMACSR_RBU_Msk       /* Receive Buffer Unavailable */

+#define ETH_DMACSR_RI_Pos                             (6U)

+#define ETH_DMACSR_RI_Msk                             (0x1UL << ETH_DMACSR_RI_Pos) /*!< 0x00000040 */

+#define ETH_DMACSR_RI                                 ETH_DMACSR_RI_Msk        /* Receive Interrupt */

+#define ETH_DMACSR_TBU_Pos                            (2U)

+#define ETH_DMACSR_TBU_Msk                            (0x1UL << ETH_DMACSR_TBU_Pos) /*!< 0x00000004 */

+#define ETH_DMACSR_TBU                                ETH_DMACSR_TBU_Msk       /* Transmit Buffer Unavailable */

+#define ETH_DMACSR_TPS_Pos                            (1U)

+#define ETH_DMACSR_TPS_Msk                            (0x1UL << ETH_DMACSR_TPS_Pos) /*!< 0x00000002 */

+#define ETH_DMACSR_TPS                                ETH_DMACSR_TPS_Msk       /* Transmit Process Stopped */

+#define ETH_DMACSR_TI_Pos                             (0U)

+#define ETH_DMACSR_TI_Msk                             (0x1UL << ETH_DMACSR_TI_Pos) /*!< 0x00000001 */

+#define ETH_DMACSR_TI                                 ETH_DMACSR_TI_Msk        /* Transmit Interrupt */

+

+/* Bit definition for Ethernet DMA Channel missed frame count register */

+#define ETH_DMACMFCR_MFCO_Pos                         (15U)

+#define ETH_DMACMFCR_MFCO_Msk                         (0x1UL << ETH_DMACMFCR_MFCO_Pos) /*!< 0x00008000 */

+#define ETH_DMACMFCR_MFCO                             ETH_DMACMFCR_MFCO_Msk    /* Overflow status of the MFC Counter */

+#define ETH_DMACMFCR_MFC_Pos                          (0U)

+#define ETH_DMACMFCR_MFC_Msk                          (0x7FFUL << ETH_DMACMFCR_MFC_Pos) /*!< 0x000007FF */

+#define ETH_DMACMFCR_MFC                              ETH_DMACMFCR_MFC_Msk     /* The number of packet counters dropped by the DMA */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             DMA Controller                                 */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DMA_SxCR register  *****************/

+#define DMA_SxCR_MBURST_Pos      (23U)

+#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                /*!< 0x01800000 */

+#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk                           /*!< Memory burst transfer configuration */

+#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */

+#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */

+#define DMA_SxCR_PBURST_Pos      (21U)

+#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                /*!< 0x00600000 */

+#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk                           /*!< Peripheral burst transfer configuration */

+#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */

+#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */

+#define DMA_SxCR_TRBUFF_Pos      (20U)

+#define DMA_SxCR_TRBUFF_Msk      (0x1UL << DMA_SxCR_TRBUFF_Pos)                 /*!< 0x00100000 */

+#define DMA_SxCR_TRBUFF          DMA_SxCR_TRBUFF_Msk                            /*!< bufferable transfers enabled/disable */

+#define DMA_SxCR_CT_Pos          (19U)

+#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                    /*!< 0x00080000 */

+#define DMA_SxCR_CT              DMA_SxCR_CT_Msk                               /*!< Current target (only in double buffer mode) */

+#define DMA_SxCR_DBM_Pos         (18U)

+#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                   /*!< 0x00040000 */

+#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk                              /*!< Double buffer mode */

+#define DMA_SxCR_PL_Pos          (16U)

+#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                    /*!< 0x00030000 */

+#define DMA_SxCR_PL              DMA_SxCR_PL_Msk                               /*!< Priority level */

+#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */

+#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */

+#define DMA_SxCR_PINCOS_Pos      (15U)

+#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                /*!< 0x00008000 */

+#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk                           /*!< Peripheral increment offset size */

+#define DMA_SxCR_MSIZE_Pos       (13U)

+#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                 /*!< 0x00006000 */

+#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk                            /*!< Memory data size */

+#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */

+#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */

+#define DMA_SxCR_PSIZE_Pos       (11U)

+#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                 /*!< 0x00001800 */

+#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk                            /*< Peripheral data size */

+#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */

+#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */

+#define DMA_SxCR_MINC_Pos        (10U)

+#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                  /*!< 0x00000400 */

+#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk                             /*!< Memory increment mode */

+#define DMA_SxCR_PINC_Pos        (9U)

+#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                  /*!< 0x00000200 */

+#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk                             /*!< Peripheral increment mode */

+#define DMA_SxCR_CIRC_Pos        (8U)

+#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                  /*!< 0x00000100 */

+#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk                             /*!< Circular mode */

+#define DMA_SxCR_DIR_Pos         (6U)

+#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                   /*!< 0x000000C0 */

+#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk                              /*!< Data transfer direction */

+#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */

+#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */

+#define DMA_SxCR_PFCTRL_Pos      (5U)

+#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                /*!< 0x00000020 */

+#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk                           /*!< Peripheral flow controller */

+#define DMA_SxCR_TCIE_Pos        (4U)

+#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                  /*!< 0x00000010 */

+#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk                             /*!< Transfer complete interrupt enable */

+#define DMA_SxCR_HTIE_Pos        (3U)

+#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                  /*!< 0x00000008 */

+#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk                             /*!< Half transfer interrupt enable */

+#define DMA_SxCR_TEIE_Pos        (2U)

+#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                  /*!< 0x00000004 */

+#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk                             /*!< Transfer error interrupt enable */

+#define DMA_SxCR_DMEIE_Pos       (1U)

+#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                 /*!< 0x00000002 */

+#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk                            /*!< Direct mode error interrupt enable */

+#define DMA_SxCR_EN_Pos          (0U)

+#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                    /*!< 0x00000001 */

+#define DMA_SxCR_EN              DMA_SxCR_EN_Msk                               /*!< Stream enable / flag stream ready when read low */

+

+/********************  Bits definition for DMA_SxCNDTR register  **************/

+#define DMA_SxNDT_Pos            (0U)

+#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                   /*!< 0x0000FFFF */

+#define DMA_SxNDT                DMA_SxNDT_Msk                                 /*!< Number of data items to transfer */

+#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */

+#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */

+#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */

+#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */

+#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */

+#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */

+#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */

+#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */

+#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */

+#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */

+#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */

+#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */

+#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */

+#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */

+#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */

+#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */

+

+/********************  Bits definition for DMA_SxFCR register  ****************/

+#define DMA_SxFCR_FEIE_Pos       (7U)

+#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                 /*!< 0x00000080 */

+#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk                            /*!< FIFO error interrupt enable */

+#define DMA_SxFCR_FS_Pos         (3U)

+#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                   /*!< 0x00000038 */

+#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk                              /*!< FIFO status */

+#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */

+#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */

+#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */

+#define DMA_SxFCR_DMDIS_Pos      (2U)

+#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                /*!< 0x00000004 */

+#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk                           /*!< Direct mode disable */

+#define DMA_SxFCR_FTH_Pos        (0U)

+#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                  /*!< 0x00000003 */

+#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk                             /*!< FIFO threshold selection */

+#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */

+#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */

+

+/********************  Bits definition for DMA_LISR register  *****************/

+#define DMA_LISR_TCIF3_Pos       (27U)

+#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                 /*!< 0x08000000 */

+#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk                            /*!<  Stream 3 transfer complete interrupt flag */

+#define DMA_LISR_HTIF3_Pos       (26U)

+#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                 /*!< 0x04000000 */

+#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk                            /*!<  Stream 3 half transfer interrupt flag */

+#define DMA_LISR_TEIF3_Pos       (25U)

+#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                 /*!< 0x02000000 */

+#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk                            /*!<  Stream 3 transfer error interrupt flag */

+#define DMA_LISR_DMEIF3_Pos      (24U)

+#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                /*!< 0x01000000 */

+#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk                           /*!<  Stream 3 direct mode error interrupt flag */

+#define DMA_LISR_FEIF3_Pos       (22U)

+#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                 /*!< 0x00400000 */

+#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk                            /*!<  Stream 3 FIFO error interrupt flag */

+#define DMA_LISR_TCIF2_Pos       (21U)

+#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                 /*!< 0x00200000 */

+#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk                            /*!<  Stream 2 transfer complete interrupt flag */

+#define DMA_LISR_HTIF2_Pos       (20U)

+#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                 /*!< 0x00100000 */

+#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk                            /*!<  Stream 2 half transfer interrupt flag */

+#define DMA_LISR_TEIF2_Pos       (19U)

+#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                 /*!< 0x00080000 */

+#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk                            /*!<  Stream 2 transfer error interrupt flag */

+#define DMA_LISR_DMEIF2_Pos      (18U)

+#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                /*!< 0x00040000 */

+#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk                           /*!<  Stream 2 direct mode error interrupt flag */

+#define DMA_LISR_FEIF2_Pos       (16U)

+#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                 /*!< 0x00010000 */

+#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk                            /*!<  Stream 2 FIFO error interrupt flag */

+#define DMA_LISR_TCIF1_Pos       (11U)

+#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                 /*!< 0x00000800 */

+#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk                            /*!<  Stream 1 transfer complete interrupt flag */

+#define DMA_LISR_HTIF1_Pos       (10U)

+#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                 /*!< 0x00000400 */

+#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk                            /*!<  Stream 1 half transfer interrupt flag */

+#define DMA_LISR_TEIF1_Pos       (9U)

+#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                 /*!< 0x00000200 */

+#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk                            /*!<  Stream 1 transfer error interrupt flag */

+#define DMA_LISR_DMEIF1_Pos      (8U)

+#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                /*!< 0x00000100 */

+#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk                           /*!<  Stream 1 direct mode error interrupt flag */

+#define DMA_LISR_FEIF1_Pos       (6U)

+#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                 /*!< 0x00000040 */

+#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk                            /*!<  Stream 1 FIFO error interrupt flag */

+#define DMA_LISR_TCIF0_Pos       (5U)

+#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                 /*!< 0x00000020 */

+#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk                            /*!<  Stream 0 transfer complete interrupt flag */

+#define DMA_LISR_HTIF0_Pos       (4U)

+#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                 /*!< 0x00000010 */

+#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk                            /*!<  Stream 0 half transfer interrupt flag */

+#define DMA_LISR_TEIF0_Pos       (3U)

+#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                 /*!< 0x00000008 */

+#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk                            /*!<  Stream 0 transfer error interrupt flag */

+#define DMA_LISR_DMEIF0_Pos      (2U)

+#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                /*!< 0x00000004 */

+#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk                           /*!<  Stream 0 direct mode error interrupt flag */

+#define DMA_LISR_FEIF0_Pos       (0U)

+#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                 /*!< 0x00000001 */

+#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk                            /*!<  Stream 0 FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_HISR register  *****************/

+#define DMA_HISR_TCIF7_Pos       (27U)

+#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                 /*!< 0x08000000 */

+#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk                            /*!<  Stream 7 transfer complete interrupt flag */

+#define DMA_HISR_HTIF7_Pos       (26U)

+#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                 /*!< 0x04000000 */

+#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk                            /*!<  Stream 7 half transfer interrupt flag */

+#define DMA_HISR_TEIF7_Pos       (25U)

+#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                 /*!< 0x02000000 */

+#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk                            /*!<  Stream 7 transfer error interrupt flag */

+#define DMA_HISR_DMEIF7_Pos      (24U)

+#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                /*!< 0x01000000 */

+#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk                           /*!<  Stream 7 direct mode error interrupt flag */

+#define DMA_HISR_FEIF7_Pos       (22U)

+#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                 /*!< 0x00400000 */

+#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk                            /*!<  Stream 7 FIFO error interrupt flag */

+#define DMA_HISR_TCIF6_Pos       (21U)

+#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                 /*!< 0x00200000 */

+#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk                            /*!<  Stream 6 transfer complete interrupt flag */

+#define DMA_HISR_HTIF6_Pos       (20U)

+#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                 /*!< 0x00100000 */

+#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk                            /*!<  Stream 6 half transfer interrupt flag */

+#define DMA_HISR_TEIF6_Pos       (19U)

+#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                 /*!< 0x00080000 */

+#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk                            /*!<  Stream 6 transfer error interrupt flag */

+#define DMA_HISR_DMEIF6_Pos      (18U)

+#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                /*!< 0x00040000 */

+#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk                           /*!<  Stream 6 direct mode error interrupt flag */

+#define DMA_HISR_FEIF6_Pos       (16U)

+#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                 /*!< 0x00010000 */

+#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk                            /*!<  Stream 6 FIFO error interrupt flag */

+#define DMA_HISR_TCIF5_Pos       (11U)

+#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                 /*!< 0x00000800 */

+#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk                            /*!<  Stream 5 transfer complete interrupt flag */

+#define DMA_HISR_HTIF5_Pos       (10U)

+#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                 /*!< 0x00000400 */

+#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk                            /*!<  Stream 5 half transfer interrupt flag */

+#define DMA_HISR_TEIF5_Pos       (9U)

+#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                 /*!< 0x00000200 */

+#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk                            /*!<  Stream 5 transfer error interrupt flag */

+#define DMA_HISR_DMEIF5_Pos      (8U)

+#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                /*!< 0x00000100 */

+#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk                           /*!<  Stream 5 direct mode error interrupt flag */

+#define DMA_HISR_FEIF5_Pos       (6U)

+#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                 /*!< 0x00000040 */

+#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk                            /*!<  Stream 5 FIFO error interrupt flag */

+#define DMA_HISR_TCIF4_Pos       (5U)

+#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                 /*!< 0x00000020 */

+#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk                            /*!<  Stream 4 transfer complete interrupt flag */

+#define DMA_HISR_HTIF4_Pos       (4U)

+#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                 /*!< 0x00000010 */

+#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk                            /*!<  Stream 4 half transfer interrupt flag */

+#define DMA_HISR_TEIF4_Pos       (3U)

+#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                 /*!< 0x00000008 */

+#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk                            /*!<  Stream 4 transfer error interrupt flag */

+#define DMA_HISR_DMEIF4_Pos      (2U)

+#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                /*!< 0x00000004 */

+#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk                           /*!<  Stream 4 direct mode error interrupt flag */

+#define DMA_HISR_FEIF4_Pos       (0U)

+#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                 /*!< 0x00000001 */

+#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk                            /*!<  Stream 4 FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_LIFCR register  ****************/

+#define DMA_LIFCR_CTCIF3_Pos     (27U)

+#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)               /*!< 0x08000000 */

+#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk                          /*!<  Stream 3 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF3_Pos     (26U)

+#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)               /*!< 0x04000000 */

+#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk                          /*!<  Stream 3 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF3_Pos     (25U)

+#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)               /*!< 0x02000000 */

+#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk                          /*!<  Stream 3 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF3_Pos    (24U)

+#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)              /*!< 0x01000000 */

+#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk                         /*!<  Stream 3 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF3_Pos     (22U)

+#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)               /*!< 0x00400000 */

+#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk                          /*!<  Stream 3 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF2_Pos     (21U)

+#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)               /*!< 0x00200000 */

+#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk                          /*!<  Stream 2 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF2_Pos     (20U)

+#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)               /*!< 0x00100000 */

+#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk                          /*!<  Stream 2 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF2_Pos     (19U)

+#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)               /*!< 0x00080000 */

+#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk                          /*!<  Stream 2 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF2_Pos    (18U)

+#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)              /*!< 0x00040000 */

+#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk                         /*!<  Stream 2 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF2_Pos     (16U)

+#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)               /*!< 0x00010000 */

+#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk                          /*!<  Stream 2 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF1_Pos     (11U)

+#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)               /*!< 0x00000800 */

+#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk                          /*!<  Stream 1 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF1_Pos     (10U)

+#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)               /*!< 0x00000400 */

+#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk                          /*!<  Stream 1 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF1_Pos     (9U)

+#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)               /*!< 0x00000200 */

+#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk                          /*!<  Stream 1 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF1_Pos    (8U)

+#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)              /*!< 0x00000100 */

+#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk                         /*!<  Stream 1 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF1_Pos     (6U)

+#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)               /*!< 0x00000040 */

+#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk                          /*!<  Stream 1 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF0_Pos     (5U)

+#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)               /*!< 0x00000020 */

+#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk                          /*!<  Stream 0 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF0_Pos     (4U)

+#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)               /*!< 0x00000010 */

+#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk                          /*!<  Stream 0 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF0_Pos     (3U)

+#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)               /*!< 0x00000008 */

+#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk                          /*!<  Stream 0 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF0_Pos    (2U)

+#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)              /*!< 0x00000004 */

+#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk                         /*!<  Stream 0 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF0_Pos     (0U)

+#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)               /*!< 0x00000001 */

+#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk                          /*!<  Stream 0 clear FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_HIFCR  register  ****************/

+#define DMA_HIFCR_CTCIF7_Pos     (27U)

+#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)               /*!< 0x08000000 */

+#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk                          /*!<  Stream 7 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF7_Pos     (26U)

+#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)               /*!< 0x04000000 */

+#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk                          /*!<  Stream 7 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF7_Pos     (25U)

+#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)               /*!< 0x02000000 */

+#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk                          /*!<  Stream 7 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF7_Pos    (24U)

+#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)              /*!< 0x01000000 */

+#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk                         /*!<  Stream 7 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF7_Pos     (22U)

+#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)               /*!< 0x00400000 */

+#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk                          /*!<  Stream 7 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF6_Pos     (21U)

+#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)               /*!< 0x00200000 */

+#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk                          /*!<  Stream 6 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF6_Pos     (20U)

+#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)               /*!< 0x00100000 */

+#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk                          /*!<  Stream 6 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF6_Pos     (19U)

+#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)               /*!< 0x00080000 */

+#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk                          /*!<  Stream 6 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF6_Pos    (18U)

+#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)              /*!< 0x00040000 */

+#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk                         /*!<  Stream 6 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF6_Pos     (16U)

+#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)               /*!< 0x00010000 */

+#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk                          /*!<  Stream 6 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF5_Pos     (11U)

+#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)               /*!< 0x00000800 */

+#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk                          /*!<  Stream 5 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF5_Pos     (10U)

+#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)               /*!< 0x00000400 */

+#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk                          /*!<  Stream 5 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF5_Pos     (9U)

+#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)               /*!< 0x00000200 */

+#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk                          /*!<  Stream 5 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF5_Pos    (8U)

+#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)              /*!< 0x00000100 */

+#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk                         /*!<  Stream 5 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF5_Pos     (6U)

+#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)               /*!< 0x00000040 */

+#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk                          /*!<  Stream 5 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF4_Pos     (5U)

+#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)               /*!< 0x00000020 */

+#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk                          /*!<  Stream 4 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF4_Pos     (4U)

+#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)               /*!< 0x00000010 */

+#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk                          /*!<  Stream 4 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF4_Pos     (3U)

+#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)               /*!< 0x00000008 */

+#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk                          /*!<  Stream 4 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF4_Pos    (2U)

+#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)              /*!< 0x00000004 */

+#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk                         /*!<  Stream 4 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF4_Pos     (0U)

+#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)               /*!< 0x00000001 */

+#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk                          /*!<  Stream 4 clear FIFO error interrupt flag */

+

+/******************  Bit definition for DMA_SxPAR register  ********************/

+#define DMA_SxPAR_PA_Pos         (0U)

+#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)            /*!< 0xFFFFFFFF */

+#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */

+

+/******************  Bit definition for DMA_SxM0AR register  ********************/

+#define DMA_SxM0AR_M0A_Pos       (0U)

+#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)          /*!< 0xFFFFFFFF */

+#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory 0 Address */

+

+/******************  Bit definition for DMA_SxM1AR register  ********************/

+#define DMA_SxM1AR_M1A_Pos       (0U)

+#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)          /*!< 0xFFFFFFFF */

+#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory 1 Address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             DMAMUX Controller                              */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DMAMUX_CxCR register  **************/

+#define DMAMUX_CxCR_DMAREQ_ID_Pos      (0U)

+#define DMAMUX_CxCR_DMAREQ_ID_Msk      (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)   /*!< 0x000000FF */

+#define DMAMUX_CxCR_DMAREQ_ID          DMAMUX_CxCR_DMAREQ_ID_Msk               /*!<  DMA request identification */

+#define DMAMUX_CxCR_DMAREQ_ID_0        (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000001 */

+#define DMAMUX_CxCR_DMAREQ_ID_1        (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000002 */

+#define DMAMUX_CxCR_DMAREQ_ID_2        (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000004 */

+#define DMAMUX_CxCR_DMAREQ_ID_3        (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000008 */

+#define DMAMUX_CxCR_DMAREQ_ID_4        (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000010 */

+#define DMAMUX_CxCR_DMAREQ_ID_5        (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000020 */

+#define DMAMUX_CxCR_DMAREQ_ID_6        (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000040 */

+#define DMAMUX_CxCR_DMAREQ_ID_7        (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000080 */

+#define DMAMUX_CxCR_SOIE_Pos           (8U)

+#define DMAMUX_CxCR_SOIE_Msk           (0x1UL << DMAMUX_CxCR_SOIE_Pos)         /*!< 0x00000100 */

+#define DMAMUX_CxCR_SOIE               DMAMUX_CxCR_SOIE_Msk                    /*!<  Synchronization overrun interrupt enable */

+#define DMAMUX_CxCR_EGE_Pos            (9U)

+#define DMAMUX_CxCR_EGE_Msk            (0x1UL << DMAMUX_CxCR_EGE_Pos)          /*!< 0x00000200 */

+#define DMAMUX_CxCR_EGE                DMAMUX_CxCR_EGE_Msk                     /*!<  Event generation enable */

+#define DMAMUX_CxCR_SE_Pos             (16U)

+#define DMAMUX_CxCR_SE_Msk             (0x1UL << DMAMUX_CxCR_SE_Pos)           /*!< 0x00010000 */

+#define DMAMUX_CxCR_SE                 DMAMUX_CxCR_SE_Msk                      /*!<  Synchronization enable */

+#define DMAMUX_CxCR_SPOL_Pos           (17U)

+#define DMAMUX_CxCR_SPOL_Msk           (0x3UL << DMAMUX_CxCR_SPOL_Pos)         /*!< 0x00060000 */

+#define DMAMUX_CxCR_SPOL               DMAMUX_CxCR_SPOL_Msk                    /*!<  Synchronization polarity */

+#define DMAMUX_CxCR_SPOL_0             (0x1UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00020000 */

+#define DMAMUX_CxCR_SPOL_1             (0x2UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00040000 */

+#define DMAMUX_CxCR_NBREQ_Pos          (19U)

+#define DMAMUX_CxCR_NBREQ_Msk          (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)       /*!< 0x00F80000 */

+#define DMAMUX_CxCR_NBREQ              DMAMUX_CxCR_NBREQ_Msk                   /*!<  Number of DMA requests minus 1 to forward */

+#define DMAMUX_CxCR_NBREQ_0            (0x01UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00080000 */

+#define DMAMUX_CxCR_NBREQ_1            (0x02UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00100000 */

+#define DMAMUX_CxCR_NBREQ_2            (0x04UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00200000 */

+#define DMAMUX_CxCR_NBREQ_3            (0x08UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00400000 */

+#define DMAMUX_CxCR_NBREQ_4            (0x10UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00800000 */

+#define DMAMUX_CxCR_SYNC_ID_Pos        (24U)

+#define DMAMUX_CxCR_SYNC_ID_Msk        (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)     /*!< 0x1F000000 */

+#define DMAMUX_CxCR_SYNC_ID            DMAMUX_CxCR_SYNC_ID_Msk                 /*!<  Synchronization identification */

+#define DMAMUX_CxCR_SYNC_ID_0          (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x01000000 */

+#define DMAMUX_CxCR_SYNC_ID_1          (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x02000000 */

+#define DMAMUX_CxCR_SYNC_ID_2          (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x04000000 */

+#define DMAMUX_CxCR_SYNC_ID_3          (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x08000000 */

+#define DMAMUX_CxCR_SYNC_ID_4          (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x10000000 */

+

+/********************  Bits definition for DMAMUX_CSR register  **************/

+#define DMAMUX_CSR_SOF0_Pos            (0U)

+#define DMAMUX_CSR_SOF0_Msk            (0x1UL << DMAMUX_CSR_SOF0_Pos)          /*!< 0x00000001 */

+#define DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0_Msk                     /*!< Channel 0 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF1_Pos            (1U)

+#define DMAMUX_CSR_SOF1_Msk            (0x1UL << DMAMUX_CSR_SOF1_Pos)          /*!< 0x00000002 */

+#define DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1_Msk                     /*!< Channel 1 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF2_Pos            (2U)

+#define DMAMUX_CSR_SOF2_Msk            (0x1UL << DMAMUX_CSR_SOF2_Pos)          /*!< 0x00000004 */

+#define DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2_Msk                     /*!< Channel 2 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF3_Pos            (3U)

+#define DMAMUX_CSR_SOF3_Msk            (0x1UL << DMAMUX_CSR_SOF3_Pos)          /*!< 0x00000008 */

+#define DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3_Msk                     /*!< Channel 3 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF4_Pos            (4U)

+#define DMAMUX_CSR_SOF4_Msk            (0x1UL << DMAMUX_CSR_SOF4_Pos)          /*!< 0x00000010 */

+#define DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4_Msk                     /*!< Channel 4 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF5_Pos            (5U)

+#define DMAMUX_CSR_SOF5_Msk            (0x1UL << DMAMUX_CSR_SOF5_Pos)          /*!< 0x00000020 */

+#define DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5_Msk                     /*!< Channel 5 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF6_Pos            (6U)

+#define DMAMUX_CSR_SOF6_Msk            (0x1UL << DMAMUX_CSR_SOF6_Pos)          /*!< 0x00000040 */

+#define DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6_Msk                     /*!< Channel 6 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF7_Pos            (7U)

+#define DMAMUX_CSR_SOF7_Msk            (0x1UL << DMAMUX_CSR_SOF7_Pos)          /*!< 0x00000080 */

+#define DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7_Msk                     /*!< Channel 7 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF8_Pos            (8U)

+#define DMAMUX_CSR_SOF8_Msk            (0x1UL << DMAMUX_CSR_SOF8_Pos)          /*!< 0x00000100 */

+#define DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8_Msk                     /*!< Channel 8 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF9_Pos            (9U)

+#define DMAMUX_CSR_SOF9_Msk            (0x1UL << DMAMUX_CSR_SOF9_Pos)          /*!< 0x00000200 */

+#define DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9_Msk                     /*!< Channel 9 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF10_Pos           (10U)

+#define DMAMUX_CSR_SOF10_Msk           (0x1UL << DMAMUX_CSR_SOF10_Pos)         /*!< 0x00000400 */

+#define DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10_Msk                    /*!< Channel 10 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF11_Pos           (11U)

+#define DMAMUX_CSR_SOF11_Msk           (0x1UL << DMAMUX_CSR_SOF11_Pos)         /*!< 0x00000800 */

+#define DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11_Msk                    /*!< Channel 11 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF12_Pos           (12U)

+#define DMAMUX_CSR_SOF12_Msk           (0x1UL << DMAMUX_CSR_SOF12_Pos)         /*!< 0x00001000 */

+#define DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12_Msk                    /*!< Channel 12 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF13_Pos           (13U)

+#define DMAMUX_CSR_SOF13_Msk           (0x1UL << DMAMUX_CSR_SOF13_Pos)         /*!< 0x00002000 */

+#define DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13_Msk                    /*!< Channel 13 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF14_Pos           (14U)

+#define DMAMUX_CSR_SOF14_Msk           (0x1UL << DMAMUX_CSR_SOF14_Pos)         /*!< 0x00004000 */

+#define DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14_Msk                    /*!< Channel 14 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF15_Pos           (15U)

+#define DMAMUX_CSR_SOF15_Msk           (0x1UL << DMAMUX_CSR_SOF15_Pos)         /*!< 0x00008000 */

+#define DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15_Msk                    /*!< Channel 15 Synchronization overrun event flag */

+

+/********************  Bits definition for DMAMUX_CFR register  **************/

+#define DMAMUX_CFR_CSOF0_Pos           (0U)

+#define DMAMUX_CFR_CSOF0_Msk           (0x1UL << DMAMUX_CFR_CSOF0_Pos)         /*!< 0x00000001 */

+#define DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0_Msk                    /*!< Channel 0 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF1_Pos           (1U)

+#define DMAMUX_CFR_CSOF1_Msk           (0x1UL << DMAMUX_CFR_CSOF1_Pos)         /*!< 0x00000002 */

+#define DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1_Msk                    /*!< Channel 1 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF2_Pos           (2U)

+#define DMAMUX_CFR_CSOF2_Msk           (0x1UL << DMAMUX_CFR_CSOF2_Pos)         /*!< 0x00000004 */

+#define DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2_Msk                    /*!< Channel 2 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF3_Pos           (3U)

+#define DMAMUX_CFR_CSOF3_Msk           (0x1UL << DMAMUX_CFR_CSOF3_Pos)         /*!< 0x00000008 */

+#define DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3_Msk                    /*!< Channel 3 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF4_Pos           (4U)

+#define DMAMUX_CFR_CSOF4_Msk           (0x1UL << DMAMUX_CFR_CSOF4_Pos)         /*!< 0x00000010 */

+#define DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4_Msk                    /*!< Channel 4 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF5_Pos           (5U)

+#define DMAMUX_CFR_CSOF5_Msk           (0x1UL << DMAMUX_CFR_CSOF5_Pos)         /*!< 0x00000020 */

+#define DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5_Msk                    /*!< Channel 5 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF6_Pos           (6U)

+#define DMAMUX_CFR_CSOF6_Msk           (0x1UL << DMAMUX_CFR_CSOF6_Pos)         /*!< 0x00000040 */

+#define DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6_Msk                    /*!< Channel 6 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF7_Pos           (7U)

+#define DMAMUX_CFR_CSOF7_Msk           (0x1UL << DMAMUX_CFR_CSOF7_Pos)         /*!< 0x00000080 */

+#define DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7_Msk                    /*!< Channel 7 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF8_Pos           (8U)

+#define DMAMUX_CFR_CSOF8_Msk           (0x1UL << DMAMUX_CFR_CSOF8_Pos)         /*!< 0x00000100 */

+#define DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8_Msk                    /*!< Channel 8 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF9_Pos           (9U)

+#define DMAMUX_CFR_CSOF9_Msk           (0x1UL << DMAMUX_CFR_CSOF9_Pos)         /*!< 0x00000200 */

+#define DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9_Msk                    /*!< Channel 9 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF10_Pos          (10U)

+#define DMAMUX_CFR_CSOF10_Msk          (0x1UL << DMAMUX_CFR_CSOF10_Pos)        /*!< 0x00000400 */

+#define DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10_Msk                   /*!< Channel 10 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF11_Pos          (11U)

+#define DMAMUX_CFR_CSOF11_Msk          (0x1UL << DMAMUX_CFR_CSOF11_Pos)        /*!< 0x00000800 */

+#define DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11_Msk                   /*!< Channel 11 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF12_Pos          (12U)

+#define DMAMUX_CFR_CSOF12_Msk          (0x1UL << DMAMUX_CFR_CSOF12_Pos)        /*!< 0x00001000 */

+#define DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12_Msk                   /*!< Channel 12 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF13_Pos          (13U)

+#define DMAMUX_CFR_CSOF13_Msk          (0x1UL << DMAMUX_CFR_CSOF13_Pos)        /*!< 0x00002000 */

+#define DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13_Msk                   /*!< Channel 13 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF14_Pos          (14U)

+#define DMAMUX_CFR_CSOF14_Msk          (0x1UL << DMAMUX_CFR_CSOF14_Pos)        /*!< 0x00004000 */

+#define DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14_Msk                   /*!< Channel 14 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF15_Pos          (15U)

+#define DMAMUX_CFR_CSOF15_Msk          (0x1UL << DMAMUX_CFR_CSOF15_Pos)        /*!< 0x00008000 */

+#define DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15_Msk                   /*!< Channel 15 Clear synchronization overrun event flag */

+

+/********************  Bits definition for DMAMUX_RGxCR register  ************/

+#define DMAMUX_RGxCR_SIG_ID_Pos        (0U)

+#define DMAMUX_RGxCR_SIG_ID_Msk        (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)     /*!< 0x0000001F */

+#define DMAMUX_RGxCR_SIG_ID            DMAMUX_RGxCR_SIG_ID_Msk                 /*!< Signal identification */

+#define DMAMUX_RGxCR_SIG_ID_0          (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000001 */

+#define DMAMUX_RGxCR_SIG_ID_1          (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000002 */

+#define DMAMUX_RGxCR_SIG_ID_2          (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000004 */

+#define DMAMUX_RGxCR_SIG_ID_3          (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000008 */

+#define DMAMUX_RGxCR_SIG_ID_4          (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000010 */

+#define DMAMUX_RGxCR_OIE_Pos           (8U)

+#define DMAMUX_RGxCR_OIE_Msk           (0x1UL << DMAMUX_RGxCR_OIE_Pos)         /*!< 0x00000100 */

+#define DMAMUX_RGxCR_OIE               DMAMUX_RGxCR_OIE_Msk                    /*!< Trigger overrun interrupt enable */

+#define DMAMUX_RGxCR_GE_Pos            (16U)

+#define DMAMUX_RGxCR_GE_Msk            (0x1UL << DMAMUX_RGxCR_GE_Pos)          /*!< 0x00010000 */

+#define DMAMUX_RGxCR_GE                DMAMUX_RGxCR_GE_Msk                     /*!< DMA request generator enable */

+#define DMAMUX_RGxCR_GPOL_Pos          (17U)

+#define DMAMUX_RGxCR_GPOL_Msk          (0x3UL << DMAMUX_RGxCR_GPOL_Pos)        /*!< 0x00060000 */

+#define DMAMUX_RGxCR_GPOL              DMAMUX_RGxCR_GPOL_Msk                   /*!< DMA request generator trigger polarity */

+#define DMAMUX_RGxCR_GPOL_0            (0x1UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00020000 */

+#define DMAMUX_RGxCR_GPOL_1            (0x2UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00040000 */

+#define DMAMUX_RGxCR_GNBREQ_Pos        (19U)

+#define DMAMUX_RGxCR_GNBREQ_Msk        (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)     /*!< 0x00F80000 */

+#define DMAMUX_RGxCR_GNBREQ            DMAMUX_RGxCR_GNBREQ_Msk                 /*!< Number of DMA requests to be generated */

+#define DMAMUX_RGxCR_GNBREQ_0          (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00080000 */

+#define DMAMUX_RGxCR_GNBREQ_1          (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00100000 */

+#define DMAMUX_RGxCR_GNBREQ_2          (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00200000 */

+#define DMAMUX_RGxCR_GNBREQ_3          (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00400000 */

+#define DMAMUX_RGxCR_GNBREQ_4          (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00800000 */

+

+/********************  Bits definition for DMAMUX_RGSR register  **************/

+#define DMAMUX_RGSR_OF0_Pos            (0U)

+#define DMAMUX_RGSR_OF0_Msk            (0x1UL << DMAMUX_RGSR_OF0_Pos)          /*!< 0x00000001 */

+#define DMAMUX_RGSR_OF0                DMAMUX_RGSR_OF0_Msk                     /*!< Request generator channel 0 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF1_Pos            (1U)

+#define DMAMUX_RGSR_OF1_Msk            (0x1UL << DMAMUX_RGSR_OF1_Pos)          /*!< 0x00000002 */

+#define DMAMUX_RGSR_OF1                DMAMUX_RGSR_OF1_Msk                     /*!< Request generator channel 1 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF2_Pos            (2U)

+#define DMAMUX_RGSR_OF2_Msk            (0x1UL << DMAMUX_RGSR_OF2_Pos)          /*!< 0x00000004 */

+#define DMAMUX_RGSR_OF2                DMAMUX_RGSR_OF2_Msk                     /*!< Request generator channel 2 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF3_Pos            (3U)

+#define DMAMUX_RGSR_OF3_Msk            (0x1UL << DMAMUX_RGSR_OF3_Pos)          /*!< 0x00000008 */

+#define DMAMUX_RGSR_OF3                DMAMUX_RGSR_OF3_Msk                     /*!< Request generator channel 3 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF4_Pos            (4U)

+#define DMAMUX_RGSR_OF4_Msk            (0x1UL << DMAMUX_RGSR_OF4_Pos)          /*!< 0x00000010 */

+#define DMAMUX_RGSR_OF4                DMAMUX_RGSR_OF4_Msk                     /*!< Request generator channel 4 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF5_Pos            (5U)

+#define DMAMUX_RGSR_OF5_Msk            (0x1UL << DMAMUX_RGSR_OF5_Pos)          /*!< 0x00000020 */

+#define DMAMUX_RGSR_OF5                DMAMUX_RGSR_OF5_Msk                     /*!< Request generator channel 5 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF6_Pos            (6U)

+#define DMAMUX_RGSR_OF6_Msk            (0x1UL << DMAMUX_RGSR_OF6_Pos)          /*!< 0x00000040 */

+#define DMAMUX_RGSR_OF6                DMAMUX_RGSR_OF6_Msk                     /*!< Request generator channel 6 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF7_Pos            (7U)

+#define DMAMUX_RGSR_OF7_Msk            (0x1UL << DMAMUX_RGSR_OF7_Pos)          /*!< 0x00000080 */

+#define DMAMUX_RGSR_OF7                DMAMUX_RGSR_OF7_Msk                     /*!< Request generator channel 7 Trigger overrun event flag */

+

+/********************  Bits definition for DMAMUX_RGCFR register  **************/

+#define DMAMUX_RGCFR_COF0_Pos          (0U)

+#define DMAMUX_RGCFR_COF0_Msk          (0x1UL << DMAMUX_RGCFR_COF0_Pos)        /*!< 0x00000001 */

+#define DMAMUX_RGCFR_COF0              DMAMUX_RGCFR_COF0_Msk                   /*!< Request generator channel 0 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF1_Pos          (1U)

+#define DMAMUX_RGCFR_COF1_Msk          (0x1UL << DMAMUX_RGCFR_COF1_Pos)        /*!< 0x00000002 */

+#define DMAMUX_RGCFR_COF1              DMAMUX_RGCFR_COF1_Msk                   /*!< Request generator channel 1 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF2_Pos          (2U)

+#define DMAMUX_RGCFR_COF2_Msk          (0x1UL << DMAMUX_RGCFR_COF2_Pos)        /*!< 0x00000004 */

+#define DMAMUX_RGCFR_COF2              DMAMUX_RGCFR_COF2_Msk                   /*!< Request generator channel 2 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF3_Pos          (3U)

+#define DMAMUX_RGCFR_COF3_Msk          (0x1UL << DMAMUX_RGCFR_COF3_Pos)        /*!< 0x00000008 */

+#define DMAMUX_RGCFR_COF3              DMAMUX_RGCFR_COF3_Msk                   /*!< Request generator channel 3 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF4_Pos          (4U)

+#define DMAMUX_RGCFR_COF4_Msk          (0x1UL << DMAMUX_RGCFR_COF4_Pos)        /*!< 0x00000010 */

+#define DMAMUX_RGCFR_COF4              DMAMUX_RGCFR_COF4_Msk                   /*!< Request generator channel 4 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF5_Pos          (5U)

+#define DMAMUX_RGCFR_COF5_Msk          (0x1UL << DMAMUX_RGCFR_COF5_Pos)        /*!< 0x00000020 */

+#define DMAMUX_RGCFR_COF5              DMAMUX_RGCFR_COF5_Msk                   /*!< Request generator channel 5 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF6_Pos          (6U)

+#define DMAMUX_RGCFR_COF6_Msk          (0x1UL << DMAMUX_RGCFR_COF6_Pos)        /*!< 0x00000040 */

+#define DMAMUX_RGCFR_COF6              DMAMUX_RGCFR_COF6_Msk                   /*!< Request generator channel 6 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF7_Pos          (7U)

+#define DMAMUX_RGCFR_COF7_Msk          (0x1UL << DMAMUX_RGCFR_COF7_Pos)        /*!< 0x00000080 */

+#define DMAMUX_RGCFR_COF7              DMAMUX_RGCFR_COF7_Msk                   /*!< Request generator channel 7 Clear trigger overrun event flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         AHB Master DMA2D Controller (DMA2D)                */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for DMA2D_CR register  ******************/

+

+#define DMA2D_CR_START_Pos         (0U)

+#define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)               /*!< 0x00000001 */

+#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer                          */

+#define DMA2D_CR_SUSP_Pos          (1U)

+#define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                /*!< 0x00000002 */

+#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer                        */

+#define DMA2D_CR_ABORT_Pos         (2U)

+#define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)               /*!< 0x00000004 */

+#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer                          */

+#define DMA2D_CR_LOM_Pos           (6U)

+#define DMA2D_CR_LOM_Msk           (0x1UL << DMA2D_CR_LOM_Pos)                 /*!< 0x00000040 */

+#define DMA2D_CR_LOM               DMA2D_CR_LOM_Msk                            /*!< Line Offset Mode                         */

+#define DMA2D_CR_TEIE_Pos          (8U)

+#define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                /*!< 0x00000100 */

+#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable         */

+#define DMA2D_CR_TCIE_Pos          (9U)

+#define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                /*!< 0x00000200 */

+#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable      */

+#define DMA2D_CR_TWIE_Pos          (10U)

+#define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                /*!< 0x00000400 */

+#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable     */

+#define DMA2D_CR_CAEIE_Pos         (11U)

+#define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)               /*!< 0x00000800 */

+#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable      */

+#define DMA2D_CR_CTCIE_Pos         (12U)

+#define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)               /*!< 0x00001000 */

+#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */

+#define DMA2D_CR_CEIE_Pos          (13U)

+#define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                /*!< 0x00002000 */

+#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable    */

+#define DMA2D_CR_MODE_Pos          (16U)

+#define DMA2D_CR_MODE_Msk          (0x7UL << DMA2D_CR_MODE_Pos)                /*!< 0x00070000 */

+#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[2:0]                         */

+#define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */

+#define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */

+#define DMA2D_CR_MODE_2            (0x4UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00040000 */

+

+/********************  Bit definition for DMA2D_ISR register  *****************/

+

+#define DMA2D_ISR_TEIF_Pos         (0U)

+#define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)               /*!< 0x00000001 */

+#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag         */

+#define DMA2D_ISR_TCIF_Pos         (1U)

+#define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)               /*!< 0x00000002 */

+#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag      */

+#define DMA2D_ISR_TWIF_Pos         (2U)

+#define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)               /*!< 0x00000004 */

+#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag     */

+#define DMA2D_ISR_CAEIF_Pos        (3U)

+#define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)              /*!< 0x00000008 */

+#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag      */

+#define DMA2D_ISR_CTCIF_Pos        (4U)

+#define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)              /*!< 0x00000010 */

+#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */

+#define DMA2D_ISR_CEIF_Pos         (5U)

+#define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)               /*!< 0x00000020 */

+#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag    */

+

+/********************  Bit definition for DMA2D_IFCR register  ****************/

+

+#define DMA2D_IFCR_CTEIF_Pos       (0U)

+#define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)             /*!< 0x00000001 */

+#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */

+#define DMA2D_IFCR_CTCIF_Pos       (1U)

+#define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)             /*!< 0x00000002 */

+#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */

+#define DMA2D_IFCR_CTWIF_Pos       (2U)

+#define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)             /*!< 0x00000004 */

+#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */

+#define DMA2D_IFCR_CAECIF_Pos      (3U)

+#define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)            /*!< 0x00000008 */

+#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */

+#define DMA2D_IFCR_CCTCIF_Pos      (4U)

+#define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)            /*!< 0x00000010 */

+#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */

+#define DMA2D_IFCR_CCEIF_Pos       (5U)

+#define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)             /*!< 0x00000020 */

+#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */

+

+/********************  Bit definition for DMA2D_FGMAR register  ***************/

+

+#define DMA2D_FGMAR_MA_Pos         (0U)

+#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)        /*!< 0xFFFFFFFF */

+#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Foreground Memory Address */

+

+/********************  Bit definition for DMA2D_FGOR register  ****************/

+

+#define DMA2D_FGOR_LO_Pos          (0U)

+#define DMA2D_FGOR_LO_Msk          (0xFFFFUL << DMA2D_FGOR_LO_Pos)             /*!< 0x0000FFFF */

+#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */

+

+/********************  Bit definition for DMA2D_BGMAR register  ***************/

+

+#define DMA2D_BGMAR_MA_Pos         (0U)

+#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)        /*!< 0xFFFFFFFF */

+#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Background Memory Address */

+

+/********************  Bit definition for DMA2D_BGOR register  ****************/

+

+#define DMA2D_BGOR_LO_Pos          (0U)

+#define DMA2D_BGOR_LO_Msk          (0xFFFFUL << DMA2D_BGOR_LO_Pos)             /*!< 0x0000FFFF */

+#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */

+

+/********************  Bit definition for DMA2D_FGPFCCR register  *************/

+

+#define DMA2D_FGPFCCR_CM_Pos       (0U)

+#define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x0000000F */

+#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */

+#define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */

+#define DMA2D_FGPFCCR_CCM_Pos      (4U)

+#define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)            /*!< 0x00000010 */

+#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */

+#define DMA2D_FGPFCCR_START_Pos    (5U)

+#define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)          /*!< 0x00000020 */

+#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */

+#define DMA2D_FGPFCCR_CS_Pos       (8U)

+#define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)            /*!< 0x0000FF00 */

+#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */

+#define DMA2D_FGPFCCR_AM_Pos       (16U)

+#define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00030000 */

+#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */

+#define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */

+#define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */

+#define DMA2D_FGPFCCR_CSS_Pos      (18U)

+#define DMA2D_FGPFCCR_CSS_Msk      (0x3UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x000C0000 */

+#define DMA2D_FGPFCCR_CSS          DMA2D_FGPFCCR_CSS_Msk                       /* !< Chroma Sub-Sampling */

+#define DMA2D_FGPFCCR_CSS_0        (0x1UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00040000 */

+#define DMA2D_FGPFCCR_CSS_1        (0x2UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00080000 */

+#define DMA2D_FGPFCCR_AI_Pos       (20U)

+#define DMA2D_FGPFCCR_AI_Msk       (0x1UL << DMA2D_FGPFCCR_AI_Pos)             /*!< 0x00100000 */

+#define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Foreground Input Alpha Inverted */

+#define DMA2D_FGPFCCR_RBS_Pos      (21U)

+#define DMA2D_FGPFCCR_RBS_Msk      (0x1UL << DMA2D_FGPFCCR_RBS_Pos)            /*!< 0x00200000 */

+#define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Foreground Input Red Blue Swap */

+#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)

+#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */

+#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */

+

+/********************  Bit definition for DMA2D_FGCOLR register  **************/

+

+#define DMA2D_FGCOLR_BLUE_Pos      (0U)

+#define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)           /*!< 0x000000FF */

+#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Foreground Blue Value */

+#define DMA2D_FGCOLR_GREEN_Pos     (8U)

+#define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */

+#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Foreground Green Value */

+#define DMA2D_FGCOLR_RED_Pos       (16U)

+#define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)            /*!< 0x00FF0000 */

+#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Foreground Red Value */

+

+/********************  Bit definition for DMA2D_BGPFCCR register  *************/

+

+#define DMA2D_BGPFCCR_CM_Pos       (0U)

+#define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x0000000F */

+#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */

+#define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_BGPFCCR_CM_3         (0x8UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000008 */

+#define DMA2D_BGPFCCR_CCM_Pos      (4U)

+#define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)            /*!< 0x00000010 */

+#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */

+#define DMA2D_BGPFCCR_START_Pos    (5U)

+#define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)          /*!< 0x00000020 */

+#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */

+#define DMA2D_BGPFCCR_CS_Pos       (8U)

+#define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)            /*!< 0x0000FF00 */

+#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */

+#define DMA2D_BGPFCCR_AM_Pos       (16U)

+#define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00030000 */

+#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */

+#define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */

+#define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */

+#define DMA2D_BGPFCCR_AI_Pos       (20U)

+#define DMA2D_BGPFCCR_AI_Msk       (0x1UL << DMA2D_BGPFCCR_AI_Pos)             /*!< 0x00100000 */

+#define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< background Input Alpha Inverted */

+#define DMA2D_BGPFCCR_RBS_Pos      (21U)

+#define DMA2D_BGPFCCR_RBS_Msk      (0x1UL << DMA2D_BGPFCCR_RBS_Pos)            /*!< 0x00200000 */

+#define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Background Input Red Blue Swap */

+#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)

+#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */

+#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */

+

+/********************  Bit definition for DMA2D_BGCOLR register  **************/

+

+#define DMA2D_BGCOLR_BLUE_Pos      (0U)

+#define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)           /*!< 0x000000FF */

+#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Background Blue Value */

+#define DMA2D_BGCOLR_GREEN_Pos     (8U)

+#define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */

+#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Background Green Value */

+#define DMA2D_BGCOLR_RED_Pos       (16U)

+#define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)            /*!< 0x00FF0000 */

+#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Background Red Value */

+

+/********************  Bit definition for DMA2D_FGCMAR register  **************/

+

+#define DMA2D_FGCMAR_MA_Pos        (0U)

+#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */

+#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Foreground CLUT Memory Address */

+

+/********************  Bit definition for DMA2D_BGCMAR register  **************/

+

+#define DMA2D_BGCMAR_MA_Pos        (0U)

+#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */

+#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Background CLUT Memory Address */

+

+/********************  Bit definition for DMA2D_OPFCCR register  **************/

+

+#define DMA2D_OPFCCR_CM_Pos        (0U)

+#define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000007 */

+#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Output Color mode CM[2:0] */

+#define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_OPFCCR_SB_Pos        (8U)

+#define DMA2D_OPFCCR_SB_Msk        (0x1UL << DMA2D_OPFCCR_SB_Pos)              /*!< 0x00000100 */

+#define DMA2D_OPFCCR_SB            DMA2D_OPFCCR_SB_Msk                         /*!< Swap Bytes */

+#define DMA2D_OPFCCR_AI_Pos        (20U)

+#define DMA2D_OPFCCR_AI_Msk        (0x1UL << DMA2D_OPFCCR_AI_Pos)              /*!< 0x00100000 */

+#define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Output Alpha Inverted */

+#define DMA2D_OPFCCR_RBS_Pos       (21U)

+#define DMA2D_OPFCCR_RBS_Msk       (0x1UL << DMA2D_OPFCCR_RBS_Pos)             /*!< 0x00200000 */

+#define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Output Red Blue Swap */

+

+/********************  Bit definition for DMA2D_OCOLR register  ***************/

+

+/*!<Mode_ARGB8888/RGB888 */

+

+#define DMA2D_OCOLR_BLUE_1_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_1_Msk     (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos)            /*0x000000FFU*/

+#define DMA2D_OCOLR_BLUE_1         DMA2D_OCOLR_BLUE_1_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_1_Pos    (8U)

+#define DMA2D_OCOLR_GREEN_1_Msk    (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos)            /*0x0000FF00U)*/

+#define DMA2D_OCOLR_GREEN_1        DMA2D_OCOLR_GREEN_1_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_1_Pos      (16U)

+#define DMA2D_OCOLR_RED_1_Msk      (0xFFUL << DMA2D_OCOLR_RED_1_Pos)            /*0x00FF0000U */

+#define DMA2D_OCOLR_RED_1          DMA2D_OCOLR_RED_1_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_1_Pos    (24U)

+#define DMA2D_OCOLR_ALPHA_1_Msk    (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos)          /*0xFF000000U*/

+#define DMA2D_OCOLR_ALPHA_1        DMA2D_OCOLR_ALPHA_1_Msk                     /*!< Output Alpha Channel Value */

+

+/*!<Mode_RGB565 */

+#define DMA2D_OCOLR_BLUE_2_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_2_Msk     (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos)            /*0x0000001FU*/

+#define DMA2D_OCOLR_BLUE_2         DMA2D_OCOLR_BLUE_2_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_2_Pos    (5U)

+#define DMA2D_OCOLR_GREEN_2_Msk    (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos)          /* 0x000007E0U */

+#define DMA2D_OCOLR_GREEN_2        DMA2D_OCOLR_GREEN_2_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_2_Pos      (11U)

+#define DMA2D_OCOLR_RED_2_Msk      (0xF8UL<<DMA2D_OCOLR_RED_2_Pos)              /*0x0000F800U*/

+#define DMA2D_OCOLR_RED_2          DMA2D_OCOLR_RED_2_Msk                       /*!< Output Red Value */

+

+/*!<Mode_ARGB1555 */

+#define DMA2D_OCOLR_BLUE_3_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_3_Msk     (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos)           /*0x0000001FU*/

+#define DMA2D_OCOLR_BLUE_3         DMA2D_OCOLR_BLUE_3_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_3_Pos    (5U)

+#define DMA2D_OCOLR_GREEN_3_Msk    (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos)          /*0x000003E0U*/

+#define DMA2D_OCOLR_GREEN_3        DMA2D_OCOLR_GREEN_3_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_3_Pos      (10U)

+#define DMA2D_OCOLR_RED_3_Msk      (0x7CUL << DMA2D_OCOLR_RED_3_Pos)            /* 0x00007C00U*/

+#define DMA2D_OCOLR_RED_3          DMA2D_OCOLR_RED_3_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_3_Pos    (15U)

+#define DMA2D_OCOLR_ALPHA_3_Msk    (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos)           /*0x00008000U*/

+#define DMA2D_OCOLR_ALPHA_3        DMA2D_OCOLR_ALPHA_3_Msk                     /*!< Output Alpha Channel Value */

+

+/*!<Mode_ARGB4444 */

+#define DMA2D_OCOLR_BLUE_4_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_4_Msk     (0xFUL << DMA2D_OCOLR_BLUE_4_Pos)            /*0x0000000FU*/

+#define DMA2D_OCOLR_BLUE_4         DMA2D_OCOLR_BLUE_4_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_4_Pos    (4U)

+#define DMA2D_OCOLR_GREEN_4_Msk    (0xFUL << DMA2D_OCOLR_GREEN_4_Pos)           /*0x000000F0U*/

+#define DMA2D_OCOLR_GREEN_4        DMA2D_OCOLR_GREEN_4_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_4_Pos      (8U)

+#define DMA2D_OCOLR_RED_4_Msk      (0xFUL << DMA2D_OCOLR_RED_4_Pos)             /*0x00000F00U*/

+#define DMA2D_OCOLR_RED_4          DMA2D_OCOLR_RED_4_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_4_Pos    (12U)

+#define DMA2D_OCOLR_ALPHA_4_Msk    (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos)            /*0x0000F000U*/

+#define DMA2D_OCOLR_ALPHA_4        DMA2D_OCOLR_ALPHA_4_Msk                     /*!< Output Alpha Channel Value */

+

+/********************  Bit definition for DMA2D_OMAR register  ****************/

+

+#define DMA2D_OMAR_MA_Pos          (0U)

+#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)         /*!< 0xFFFFFFFF */

+#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Output Memory Address */

+

+/********************  Bit definition for DMA2D_OOR register  *****************/

+

+#define DMA2D_OOR_LO_Pos           (0U)

+#define DMA2D_OOR_LO_Msk           (0xFFFFUL << DMA2D_OOR_LO_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Output Line Offset */

+

+/********************  Bit definition for DMA2D_NLR register  *****************/

+

+#define DMA2D_NLR_NL_Pos           (0U)

+#define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */

+#define DMA2D_NLR_PL_Pos           (16U)

+#define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)              /*!< 0x3FFF0000 */

+#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */

+

+/********************  Bit definition for DMA2D_LWR register  *****************/

+

+#define DMA2D_LWR_LW_Pos           (0U)

+#define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */

+

+/********************  Bit definition for DMA2D_AMTCR register  ***************/

+

+#define DMA2D_AMTCR_EN_Pos         (0U)

+#define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)               /*!< 0x00000001 */

+#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */

+#define DMA2D_AMTCR_DT_Pos         (8U)

+#define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)              /*!< 0x0000FF00 */

+#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */

+

+

+/********************  Bit definition for DMA2D_FGCLUT register  **************/

+

+/********************  Bit definition for DMA2D_BGCLUT register  **************/

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                    External Interrupt/Event Controller                     */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for EXTI_RTSR1 register  *******************/

+#define EXTI_RTSR1_TR_Pos          (0U)

+#define EXTI_RTSR1_TR_Msk          (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)           /*!< 0x003FFFFF */

+#define EXTI_RTSR1_TR              EXTI_RTSR1_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR1_TR0_Pos         (0U)

+#define EXTI_RTSR1_TR0_Msk         (0x1UL << EXTI_RTSR1_TR0_Pos)               /*!< 0x00000001 */

+#define EXTI_RTSR1_TR0             EXTI_RTSR1_TR0_Msk                          /*!< Rising trigger event configuration bit of line 0 */

+#define EXTI_RTSR1_TR1_Pos         (1U)

+#define EXTI_RTSR1_TR1_Msk         (0x1UL << EXTI_RTSR1_TR1_Pos)               /*!< 0x00000002 */

+#define EXTI_RTSR1_TR1             EXTI_RTSR1_TR1_Msk                          /*!< Rising trigger event configuration bit of line 1 */

+#define EXTI_RTSR1_TR2_Pos         (2U)

+#define EXTI_RTSR1_TR2_Msk         (0x1UL << EXTI_RTSR1_TR2_Pos)               /*!< 0x00000004 */

+#define EXTI_RTSR1_TR2             EXTI_RTSR1_TR2_Msk                          /*!< Rising trigger event configuration bit of line 2 */

+#define EXTI_RTSR1_TR3_Pos         (3U)

+#define EXTI_RTSR1_TR3_Msk         (0x1UL << EXTI_RTSR1_TR3_Pos)               /*!< 0x00000008 */

+#define EXTI_RTSR1_TR3             EXTI_RTSR1_TR3_Msk                          /*!< Rising trigger event configuration bit of line 3 */

+#define EXTI_RTSR1_TR4_Pos         (4U)

+#define EXTI_RTSR1_TR4_Msk         (0x1UL << EXTI_RTSR1_TR4_Pos)               /*!< 0x00000010 */

+#define EXTI_RTSR1_TR4             EXTI_RTSR1_TR4_Msk                          /*!< Rising trigger event configuration bit of line 4 */

+#define EXTI_RTSR1_TR5_Pos         (5U)

+#define EXTI_RTSR1_TR5_Msk         (0x1UL << EXTI_RTSR1_TR5_Pos)               /*!< 0x00000020 */

+#define EXTI_RTSR1_TR5             EXTI_RTSR1_TR5_Msk                          /*!< Rising trigger event configuration bit of line 5 */

+#define EXTI_RTSR1_TR6_Pos         (6U)

+#define EXTI_RTSR1_TR6_Msk         (0x1UL << EXTI_RTSR1_TR6_Pos)               /*!< 0x00000040 */

+#define EXTI_RTSR1_TR6             EXTI_RTSR1_TR6_Msk                          /*!< Rising trigger event configuration bit of line 6 */

+#define EXTI_RTSR1_TR7_Pos         (7U)

+#define EXTI_RTSR1_TR7_Msk         (0x1UL << EXTI_RTSR1_TR7_Pos)               /*!< 0x00000080 */

+#define EXTI_RTSR1_TR7             EXTI_RTSR1_TR7_Msk                          /*!< Rising trigger event configuration bit of line 7 */

+#define EXTI_RTSR1_TR8_Pos         (8U)

+#define EXTI_RTSR1_TR8_Msk         (0x1UL << EXTI_RTSR1_TR8_Pos)               /*!< 0x00000100 */

+#define EXTI_RTSR1_TR8             EXTI_RTSR1_TR8_Msk                          /*!< Rising trigger event configuration bit of line 8 */

+#define EXTI_RTSR1_TR9_Pos         (9U)

+#define EXTI_RTSR1_TR9_Msk         (0x1UL << EXTI_RTSR1_TR9_Pos)               /*!< 0x00000200 */

+#define EXTI_RTSR1_TR9             EXTI_RTSR1_TR9_Msk                          /*!< Rising trigger event configuration bit of line 9 */

+#define EXTI_RTSR1_TR10_Pos        (10U)

+#define EXTI_RTSR1_TR10_Msk        (0x1UL << EXTI_RTSR1_TR10_Pos)              /*!< 0x00000400 */

+#define EXTI_RTSR1_TR10            EXTI_RTSR1_TR10_Msk                         /*!< Rising trigger event configuration bit of line 10 */

+#define EXTI_RTSR1_TR11_Pos        (11U)

+#define EXTI_RTSR1_TR11_Msk        (0x1UL << EXTI_RTSR1_TR11_Pos)              /*!< 0x00000800 */

+#define EXTI_RTSR1_TR11            EXTI_RTSR1_TR11_Msk                         /*!< Rising trigger event configuration bit of line 11 */

+#define EXTI_RTSR1_TR12_Pos        (12U)

+#define EXTI_RTSR1_TR12_Msk        (0x1UL << EXTI_RTSR1_TR12_Pos)              /*!< 0x00001000 */

+#define EXTI_RTSR1_TR12            EXTI_RTSR1_TR12_Msk                         /*!< Rising trigger event configuration bit of line 12 */

+#define EXTI_RTSR1_TR13_Pos        (13U)

+#define EXTI_RTSR1_TR13_Msk        (0x1UL << EXTI_RTSR1_TR13_Pos)              /*!< 0x00002000 */

+#define EXTI_RTSR1_TR13            EXTI_RTSR1_TR13_Msk                         /*!< Rising trigger event configuration bit of line 13 */

+#define EXTI_RTSR1_TR14_Pos        (14U)

+#define EXTI_RTSR1_TR14_Msk        (0x1UL << EXTI_RTSR1_TR14_Pos)              /*!< 0x00004000 */

+#define EXTI_RTSR1_TR14            EXTI_RTSR1_TR14_Msk                         /*!< Rising trigger event configuration bit of line 14 */

+#define EXTI_RTSR1_TR15_Pos        (15U)

+#define EXTI_RTSR1_TR15_Msk        (0x1UL << EXTI_RTSR1_TR15_Pos)              /*!< 0x00008000 */

+#define EXTI_RTSR1_TR15            EXTI_RTSR1_TR15_Msk                         /*!< Rising trigger event configuration bit of line 15 */

+#define EXTI_RTSR1_TR16_Pos        (16U)

+#define EXTI_RTSR1_TR16_Msk        (0x1UL << EXTI_RTSR1_TR16_Pos)              /*!< 0x00010000 */

+#define EXTI_RTSR1_TR16            EXTI_RTSR1_TR16_Msk                         /*!< Rising trigger event configuration bit of line 16 */

+#define EXTI_RTSR1_TR17_Pos        (17U)

+#define EXTI_RTSR1_TR17_Msk        (0x1UL << EXTI_RTSR1_TR17_Pos)              /*!< 0x00020000 */

+#define EXTI_RTSR1_TR17            EXTI_RTSR1_TR17_Msk                         /*!< Rising trigger event configuration bit of line 17 */

+#define EXTI_RTSR1_TR18_Pos        (18U)

+#define EXTI_RTSR1_TR18_Msk        (0x1UL << EXTI_RTSR1_TR18_Pos)              /*!< 0x00040000 */

+#define EXTI_RTSR1_TR18            EXTI_RTSR1_TR18_Msk                         /*!< Rising trigger event configuration bit of line 18 */

+#define EXTI_RTSR1_TR19_Pos        (19U)

+#define EXTI_RTSR1_TR19_Msk        (0x1UL << EXTI_RTSR1_TR19_Pos)              /*!< 0x00080000 */

+#define EXTI_RTSR1_TR19            EXTI_RTSR1_TR19_Msk                         /*!< Rising trigger event configuration bit of line 19 */

+#define EXTI_RTSR1_TR20_Pos        (20U)

+#define EXTI_RTSR1_TR20_Msk        (0x1UL << EXTI_RTSR1_TR20_Pos)              /*!< 0x00100000 */

+#define EXTI_RTSR1_TR20            EXTI_RTSR1_TR20_Msk                         /*!< Rising trigger event configuration bit of line 20 */

+#define EXTI_RTSR1_TR21_Pos        (21U)

+#define EXTI_RTSR1_TR21_Msk        (0x1UL << EXTI_RTSR1_TR21_Pos)              /*!< 0x00200000 */

+#define EXTI_RTSR1_TR21            EXTI_RTSR1_TR21_Msk                         /*!< Rising trigger event configuration bit of line 21 */

+

+/******************  Bit definition for EXTI_FTSR1 register  *******************/

+#define EXTI_FTSR1_TR_Pos          (0U)

+#define EXTI_FTSR1_TR_Msk          (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)           /*!< 0x003FFFFF */

+#define EXTI_FTSR1_TR              EXTI_FTSR1_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR1_TR0_Pos         (0U)

+#define EXTI_FTSR1_TR0_Msk         (0x1UL << EXTI_FTSR1_TR0_Pos)               /*!< 0x00000001 */

+#define EXTI_FTSR1_TR0             EXTI_FTSR1_TR0_Msk                          /*!< Falling trigger event configuration bit of line 0 */

+#define EXTI_FTSR1_TR1_Pos         (1U)

+#define EXTI_FTSR1_TR1_Msk         (0x1UL << EXTI_FTSR1_TR1_Pos)               /*!< 0x00000002 */

+#define EXTI_FTSR1_TR1             EXTI_FTSR1_TR1_Msk                          /*!< Falling trigger event configuration bit of line 1 */

+#define EXTI_FTSR1_TR2_Pos         (2U)

+#define EXTI_FTSR1_TR2_Msk         (0x1UL << EXTI_FTSR1_TR2_Pos)               /*!< 0x00000004 */

+#define EXTI_FTSR1_TR2             EXTI_FTSR1_TR2_Msk                          /*!< Falling trigger event configuration bit of line 2 */

+#define EXTI_FTSR1_TR3_Pos         (3U)

+#define EXTI_FTSR1_TR3_Msk         (0x1UL << EXTI_FTSR1_TR3_Pos)               /*!< 0x00000008 */

+#define EXTI_FTSR1_TR3             EXTI_FTSR1_TR3_Msk                          /*!< Falling trigger event configuration bit of line 3 */

+#define EXTI_FTSR1_TR4_Pos         (4U)

+#define EXTI_FTSR1_TR4_Msk         (0x1UL << EXTI_FTSR1_TR4_Pos)               /*!< 0x00000010 */

+#define EXTI_FTSR1_TR4             EXTI_FTSR1_TR4_Msk                          /*!< Falling trigger event configuration bit of line 4 */

+#define EXTI_FTSR1_TR5_Pos         (5U)

+#define EXTI_FTSR1_TR5_Msk         (0x1UL << EXTI_FTSR1_TR5_Pos)               /*!< 0x00000020 */

+#define EXTI_FTSR1_TR5             EXTI_FTSR1_TR5_Msk                          /*!< Falling trigger event configuration bit of line 5 */

+#define EXTI_FTSR1_TR6_Pos         (6U)

+#define EXTI_FTSR1_TR6_Msk         (0x1UL << EXTI_FTSR1_TR6_Pos)               /*!< 0x00000040 */

+#define EXTI_FTSR1_TR6             EXTI_FTSR1_TR6_Msk                          /*!< Falling trigger event configuration bit of line 6 */

+#define EXTI_FTSR1_TR7_Pos         (7U)

+#define EXTI_FTSR1_TR7_Msk         (0x1UL << EXTI_FTSR1_TR7_Pos)               /*!< 0x00000080 */

+#define EXTI_FTSR1_TR7             EXTI_FTSR1_TR7_Msk                          /*!< Falling trigger event configuration bit of line 7 */

+#define EXTI_FTSR1_TR8_Pos         (8U)

+#define EXTI_FTSR1_TR8_Msk         (0x1UL << EXTI_FTSR1_TR8_Pos)               /*!< 0x00000100 */

+#define EXTI_FTSR1_TR8             EXTI_FTSR1_TR8_Msk                          /*!< Falling trigger event configuration bit of line 8 */

+#define EXTI_FTSR1_TR9_Pos         (9U)

+#define EXTI_FTSR1_TR9_Msk         (0x1UL << EXTI_FTSR1_TR9_Pos)               /*!< 0x00000200 */

+#define EXTI_FTSR1_TR9             EXTI_FTSR1_TR9_Msk                          /*!< Falling trigger event configuration bit of line 9 */

+#define EXTI_FTSR1_TR10_Pos        (10U)

+#define EXTI_FTSR1_TR10_Msk        (0x1UL << EXTI_FTSR1_TR10_Pos)              /*!< 0x00000400 */

+#define EXTI_FTSR1_TR10            EXTI_FTSR1_TR10_Msk                         /*!< Falling trigger event configuration bit of line 10 */

+#define EXTI_FTSR1_TR11_Pos        (11U)

+#define EXTI_FTSR1_TR11_Msk        (0x1UL << EXTI_FTSR1_TR11_Pos)              /*!< 0x00000800 */

+#define EXTI_FTSR1_TR11            EXTI_FTSR1_TR11_Msk                         /*!< Falling trigger event configuration bit of line 11 */

+#define EXTI_FTSR1_TR12_Pos        (12U)

+#define EXTI_FTSR1_TR12_Msk        (0x1UL << EXTI_FTSR1_TR12_Pos)              /*!< 0x00001000 */

+#define EXTI_FTSR1_TR12            EXTI_FTSR1_TR12_Msk                         /*!< Falling trigger event configuration bit of line 12 */

+#define EXTI_FTSR1_TR13_Pos        (13U)

+#define EXTI_FTSR1_TR13_Msk        (0x1UL << EXTI_FTSR1_TR13_Pos)              /*!< 0x00002000 */

+#define EXTI_FTSR1_TR13            EXTI_FTSR1_TR13_Msk                         /*!< Falling trigger event configuration bit of line 13 */

+#define EXTI_FTSR1_TR14_Pos        (14U)

+#define EXTI_FTSR1_TR14_Msk        (0x1UL << EXTI_FTSR1_TR14_Pos)              /*!< 0x00004000 */

+#define EXTI_FTSR1_TR14            EXTI_FTSR1_TR14_Msk                         /*!< Falling trigger event configuration bit of line 14 */

+#define EXTI_FTSR1_TR15_Pos        (15U)

+#define EXTI_FTSR1_TR15_Msk        (0x1UL << EXTI_FTSR1_TR15_Pos)              /*!< 0x00008000 */

+#define EXTI_FTSR1_TR15            EXTI_FTSR1_TR15_Msk                         /*!< Falling trigger event configuration bit of line 15 */

+#define EXTI_FTSR1_TR16_Pos        (16U)

+#define EXTI_FTSR1_TR16_Msk        (0x1UL << EXTI_FTSR1_TR16_Pos)              /*!< 0x00010000 */

+#define EXTI_FTSR1_TR16            EXTI_FTSR1_TR16_Msk                         /*!< Falling trigger event configuration bit of line 16 */

+#define EXTI_FTSR1_TR17_Pos        (17U)

+#define EXTI_FTSR1_TR17_Msk        (0x1UL << EXTI_FTSR1_TR17_Pos)              /*!< 0x00020000 */

+#define EXTI_FTSR1_TR17            EXTI_FTSR1_TR17_Msk                         /*!< Falling trigger event configuration bit of line 17 */

+#define EXTI_FTSR1_TR18_Pos        (18U)

+#define EXTI_FTSR1_TR18_Msk        (0x1UL << EXTI_FTSR1_TR18_Pos)              /*!< 0x00040000 */

+#define EXTI_FTSR1_TR18            EXTI_FTSR1_TR18_Msk                         /*!< Falling trigger event configuration bit of line 18 */

+#define EXTI_FTSR1_TR19_Pos        (19U)

+#define EXTI_FTSR1_TR19_Msk        (0x1UL << EXTI_FTSR1_TR19_Pos)              /*!< 0x00080000 */

+#define EXTI_FTSR1_TR19            EXTI_FTSR1_TR19_Msk                         /*!< Falling trigger event configuration bit of line 19 */

+#define EXTI_FTSR1_TR20_Pos        (20U)

+#define EXTI_FTSR1_TR20_Msk        (0x1UL << EXTI_FTSR1_TR20_Pos)              /*!< 0x00100000 */

+#define EXTI_FTSR1_TR20            EXTI_FTSR1_TR20_Msk                         /*!< Falling trigger event configuration bit of line 20 */

+#define EXTI_FTSR1_TR21_Pos        (21U)

+#define EXTI_FTSR1_TR21_Msk        (0x1UL << EXTI_FTSR1_TR21_Pos)              /*!< 0x00200000 */

+#define EXTI_FTSR1_TR21            EXTI_FTSR1_TR21_Msk                         /*!< Falling trigger event configuration bit of line 21 */

+

+/******************  Bit definition for EXTI_SWIER1 register  ******************/

+#define EXTI_SWIER1_SWIER0_Pos     (0U)

+#define EXTI_SWIER1_SWIER0_Msk     (0x1UL << EXTI_SWIER1_SWIER0_Pos)           /*!< 0x00000001 */

+#define EXTI_SWIER1_SWIER0         EXTI_SWIER1_SWIER0_Msk                      /*!< Software Interrupt on line 0 */

+#define EXTI_SWIER1_SWIER1_Pos     (1U)

+#define EXTI_SWIER1_SWIER1_Msk     (0x1UL << EXTI_SWIER1_SWIER1_Pos)           /*!< 0x00000002 */

+#define EXTI_SWIER1_SWIER1         EXTI_SWIER1_SWIER1_Msk                      /*!< Software Interrupt on line 1 */

+#define EXTI_SWIER1_SWIER2_Pos     (2U)

+#define EXTI_SWIER1_SWIER2_Msk     (0x1UL << EXTI_SWIER1_SWIER2_Pos)           /*!< 0x00000004 */

+#define EXTI_SWIER1_SWIER2         EXTI_SWIER1_SWIER2_Msk                      /*!< Software Interrupt on line 2 */

+#define EXTI_SWIER1_SWIER3_Pos     (3U)

+#define EXTI_SWIER1_SWIER3_Msk     (0x1UL << EXTI_SWIER1_SWIER3_Pos)           /*!< 0x00000008 */

+#define EXTI_SWIER1_SWIER3         EXTI_SWIER1_SWIER3_Msk                      /*!< Software Interrupt on line 3 */

+#define EXTI_SWIER1_SWIER4_Pos     (4U)

+#define EXTI_SWIER1_SWIER4_Msk     (0x1UL << EXTI_SWIER1_SWIER4_Pos)           /*!< 0x00000010 */

+#define EXTI_SWIER1_SWIER4         EXTI_SWIER1_SWIER4_Msk                      /*!< Software Interrupt on line 4 */

+#define EXTI_SWIER1_SWIER5_Pos     (5U)

+#define EXTI_SWIER1_SWIER5_Msk     (0x1UL << EXTI_SWIER1_SWIER5_Pos)           /*!< 0x00000020 */

+#define EXTI_SWIER1_SWIER5         EXTI_SWIER1_SWIER5_Msk                      /*!< Software Interrupt on line 5 */

+#define EXTI_SWIER1_SWIER6_Pos     (6U)

+#define EXTI_SWIER1_SWIER6_Msk     (0x1UL << EXTI_SWIER1_SWIER6_Pos)           /*!< 0x00000040 */

+#define EXTI_SWIER1_SWIER6         EXTI_SWIER1_SWIER6_Msk                      /*!< Software Interrupt on line 6 */

+#define EXTI_SWIER1_SWIER7_Pos     (7U)

+#define EXTI_SWIER1_SWIER7_Msk     (0x1UL << EXTI_SWIER1_SWIER7_Pos)           /*!< 0x00000080 */

+#define EXTI_SWIER1_SWIER7         EXTI_SWIER1_SWIER7_Msk                      /*!< Software Interrupt on line 7 */

+#define EXTI_SWIER1_SWIER8_Pos     (8U)

+#define EXTI_SWIER1_SWIER8_Msk     (0x1UL << EXTI_SWIER1_SWIER8_Pos)           /*!< 0x00000100 */

+#define EXTI_SWIER1_SWIER8         EXTI_SWIER1_SWIER8_Msk                      /*!< Software Interrupt on line 8 */

+#define EXTI_SWIER1_SWIER9_Pos     (9U)

+#define EXTI_SWIER1_SWIER9_Msk     (0x1UL << EXTI_SWIER1_SWIER9_Pos)           /*!< 0x00000200 */

+#define EXTI_SWIER1_SWIER9         EXTI_SWIER1_SWIER9_Msk                      /*!< Software Interrupt on line 9 */

+#define EXTI_SWIER1_SWIER10_Pos    (10U)

+#define EXTI_SWIER1_SWIER10_Msk    (0x1UL << EXTI_SWIER1_SWIER10_Pos)          /*!< 0x00000400 */

+#define EXTI_SWIER1_SWIER10        EXTI_SWIER1_SWIER10_Msk                     /*!< Software Interrupt on line 10 */

+#define EXTI_SWIER1_SWIER11_Pos    (11U)

+#define EXTI_SWIER1_SWIER11_Msk    (0x1UL << EXTI_SWIER1_SWIER11_Pos)          /*!< 0x00000800 */

+#define EXTI_SWIER1_SWIER11        EXTI_SWIER1_SWIER11_Msk                     /*!< Software Interrupt on line 11 */

+#define EXTI_SWIER1_SWIER12_Pos    (12U)

+#define EXTI_SWIER1_SWIER12_Msk    (0x1UL << EXTI_SWIER1_SWIER12_Pos)          /*!< 0x00001000 */

+#define EXTI_SWIER1_SWIER12        EXTI_SWIER1_SWIER12_Msk                     /*!< Software Interrupt on line 12 */

+#define EXTI_SWIER1_SWIER13_Pos    (13U)

+#define EXTI_SWIER1_SWIER13_Msk    (0x1UL << EXTI_SWIER1_SWIER13_Pos)          /*!< 0x00002000 */

+#define EXTI_SWIER1_SWIER13        EXTI_SWIER1_SWIER13_Msk                     /*!< Software Interrupt on line 13 */

+#define EXTI_SWIER1_SWIER14_Pos    (14U)

+#define EXTI_SWIER1_SWIER14_Msk    (0x1UL << EXTI_SWIER1_SWIER14_Pos)          /*!< 0x00004000 */

+#define EXTI_SWIER1_SWIER14        EXTI_SWIER1_SWIER14_Msk                     /*!< Software Interrupt on line 14 */

+#define EXTI_SWIER1_SWIER15_Pos    (15U)

+#define EXTI_SWIER1_SWIER15_Msk    (0x1UL << EXTI_SWIER1_SWIER15_Pos)          /*!< 0x00008000 */

+#define EXTI_SWIER1_SWIER15        EXTI_SWIER1_SWIER15_Msk                     /*!< Software Interrupt on line 15 */

+#define EXTI_SWIER1_SWIER16_Pos    (16U)

+#define EXTI_SWIER1_SWIER16_Msk    (0x1UL << EXTI_SWIER1_SWIER16_Pos)          /*!< 0x00010000 */

+#define EXTI_SWIER1_SWIER16        EXTI_SWIER1_SWIER16_Msk                     /*!< Software Interrupt on line 16 */

+#define EXTI_SWIER1_SWIER17_Pos    (17U)

+#define EXTI_SWIER1_SWIER17_Msk    (0x1UL << EXTI_SWIER1_SWIER17_Pos)          /*!< 0x00020000 */

+#define EXTI_SWIER1_SWIER17        EXTI_SWIER1_SWIER17_Msk                     /*!< Software Interrupt on line 17 */

+#define EXTI_SWIER1_SWIER18_Pos    (18U)

+#define EXTI_SWIER1_SWIER18_Msk    (0x1UL << EXTI_SWIER1_SWIER18_Pos)          /*!< 0x00040000 */

+#define EXTI_SWIER1_SWIER18        EXTI_SWIER1_SWIER18_Msk                     /*!< Software Interrupt on line 18 */

+#define EXTI_SWIER1_SWIER19_Pos    (19U)

+#define EXTI_SWIER1_SWIER19_Msk    (0x1UL << EXTI_SWIER1_SWIER19_Pos)          /*!< 0x00080000 */

+#define EXTI_SWIER1_SWIER19        EXTI_SWIER1_SWIER19_Msk                     /*!< Software Interrupt on line 19 */

+#define EXTI_SWIER1_SWIER20_Pos    (20U)

+#define EXTI_SWIER1_SWIER20_Msk    (0x1UL << EXTI_SWIER1_SWIER20_Pos)          /*!< 0x00100000 */

+#define EXTI_SWIER1_SWIER20        EXTI_SWIER1_SWIER20_Msk                     /*!< Software Interrupt on line 20 */

+#define EXTI_SWIER1_SWIER21_Pos    (21U)

+#define EXTI_SWIER1_SWIER21_Msk    (0x1UL << EXTI_SWIER1_SWIER21_Pos)          /*!< 0x00200000 */

+#define EXTI_SWIER1_SWIER21        EXTI_SWIER1_SWIER21_Msk                     /*!< Software Interrupt on line 21 */

+

+/******************  Bit definition for EXTI_D3PMR1 register  ******************/

+#define EXTI_D3PMR1_MR0_Pos        (0U)

+#define EXTI_D3PMR1_MR0_Msk        (0x1UL << EXTI_D3PMR1_MR0_Pos)              /*!< 0x00000001 */

+#define EXTI_D3PMR1_MR0            EXTI_D3PMR1_MR0_Msk                         /*!< Pending Mask Event for line 0  */

+#define EXTI_D3PMR1_MR1_Pos        (1U)

+#define EXTI_D3PMR1_MR1_Msk        (0x1UL << EXTI_D3PMR1_MR1_Pos)              /*!< 0x00000002 */

+#define EXTI_D3PMR1_MR1            EXTI_D3PMR1_MR1_Msk                         /*!< Pending Mask Event for line 1  */

+#define EXTI_D3PMR1_MR2_Pos        (2U)

+#define EXTI_D3PMR1_MR2_Msk        (0x1UL << EXTI_D3PMR1_MR2_Pos)              /*!< 0x00000004 */

+#define EXTI_D3PMR1_MR2            EXTI_D3PMR1_MR2_Msk                         /*!< Pending Mask Event for line 2  */

+#define EXTI_D3PMR1_MR3_Pos        (3U)

+#define EXTI_D3PMR1_MR3_Msk        (0x1UL << EXTI_D3PMR1_MR3_Pos)              /*!< 0x00000008 */

+#define EXTI_D3PMR1_MR3            EXTI_D3PMR1_MR3_Msk                         /*!< Pending Mask Event for line 3  */

+#define EXTI_D3PMR1_MR4_Pos        (4U)

+#define EXTI_D3PMR1_MR4_Msk        (0x1UL << EXTI_D3PMR1_MR4_Pos)              /*!< 0x00000010 */

+#define EXTI_D3PMR1_MR4            EXTI_D3PMR1_MR4_Msk                         /*!< Pending Mask Event for line 4  */

+#define EXTI_D3PMR1_MR5_Pos        (5U)

+#define EXTI_D3PMR1_MR5_Msk        (0x1UL << EXTI_D3PMR1_MR5_Pos)              /*!< 0x00000020 */

+#define EXTI_D3PMR1_MR5            EXTI_D3PMR1_MR5_Msk                         /*!< Pending Mask Event for line 5  */

+#define EXTI_D3PMR1_MR6_Pos        (6U)

+#define EXTI_D3PMR1_MR6_Msk        (0x1UL << EXTI_D3PMR1_MR6_Pos)              /*!< 0x00000040 */

+#define EXTI_D3PMR1_MR6            EXTI_D3PMR1_MR6_Msk                         /*!< Pending Mask Event for line 6  */

+#define EXTI_D3PMR1_MR7_Pos        (7U)

+#define EXTI_D3PMR1_MR7_Msk        (0x1UL << EXTI_D3PMR1_MR7_Pos)              /*!< 0x00000080 */

+#define EXTI_D3PMR1_MR7            EXTI_D3PMR1_MR7_Msk                         /*!< Pending Mask Event for line 7  */

+#define EXTI_D3PMR1_MR8_Pos        (8U)

+#define EXTI_D3PMR1_MR8_Msk        (0x1UL << EXTI_D3PMR1_MR8_Pos)              /*!< 0x00000100 */

+#define EXTI_D3PMR1_MR8            EXTI_D3PMR1_MR8_Msk                         /*!< Pending Mask Event for line 8  */

+#define EXTI_D3PMR1_MR9_Pos        (9U)

+#define EXTI_D3PMR1_MR9_Msk        (0x1UL << EXTI_D3PMR1_MR9_Pos)              /*!< 0x00000200 */

+#define EXTI_D3PMR1_MR9            EXTI_D3PMR1_MR9_Msk                         /*!< Pending Mask Event for line 9  */

+#define EXTI_D3PMR1_MR10_Pos       (10U)

+#define EXTI_D3PMR1_MR10_Msk       (0x1UL << EXTI_D3PMR1_MR10_Pos)             /*!< 0x00000400 */

+#define EXTI_D3PMR1_MR10           EXTI_D3PMR1_MR10_Msk                        /*!< Pending Mask Event for line 10 */

+#define EXTI_D3PMR1_MR11_Pos       (11U)

+#define EXTI_D3PMR1_MR11_Msk       (0x1UL << EXTI_D3PMR1_MR11_Pos)             /*!< 0x00000800 */

+#define EXTI_D3PMR1_MR11           EXTI_D3PMR1_MR11_Msk                        /*!< Pending Mask Event for line 11 */

+#define EXTI_D3PMR1_MR12_Pos       (12U)

+#define EXTI_D3PMR1_MR12_Msk       (0x1UL << EXTI_D3PMR1_MR12_Pos)             /*!< 0x00001000 */

+#define EXTI_D3PMR1_MR12           EXTI_D3PMR1_MR12_Msk                        /*!< Pending Mask Event for line 12 */

+#define EXTI_D3PMR1_MR13_Pos       (13U)

+#define EXTI_D3PMR1_MR13_Msk       (0x1UL << EXTI_D3PMR1_MR13_Pos)             /*!< 0x00002000 */

+#define EXTI_D3PMR1_MR13           EXTI_D3PMR1_MR13_Msk                        /*!< Pending Mask Event for line 13 */

+#define EXTI_D3PMR1_MR14_Pos       (14U)

+#define EXTI_D3PMR1_MR14_Msk       (0x1UL << EXTI_D3PMR1_MR14_Pos)             /*!< 0x00004000 */

+#define EXTI_D3PMR1_MR14           EXTI_D3PMR1_MR14_Msk                        /*!< Pending Mask Event for line 14 */

+#define EXTI_D3PMR1_MR15_Pos       (15U)

+#define EXTI_D3PMR1_MR15_Msk       (0x1UL << EXTI_D3PMR1_MR15_Pos)             /*!< 0x00008000 */

+#define EXTI_D3PMR1_MR15           EXTI_D3PMR1_MR15_Msk                        /*!< Pending Mask Event for line 15 */

+#define EXTI_D3PMR1_MR19_Pos       (19U)

+#define EXTI_D3PMR1_MR19_Msk       (0x1UL << EXTI_D3PMR1_MR19_Pos)             /*!< 0x00080000 */

+#define EXTI_D3PMR1_MR19           EXTI_D3PMR1_MR19_Msk                        /*!< Pending Mask Event for line 19 */

+#define EXTI_D3PMR1_MR20_Pos       (20U)

+#define EXTI_D3PMR1_MR20_Msk       (0x1UL << EXTI_D3PMR1_MR20_Pos)             /*!< 0x00100000 */

+#define EXTI_D3PMR1_MR20           EXTI_D3PMR1_MR20_Msk                        /*!< Pending Mask Event for line 20 */

+#define EXTI_D3PMR1_MR21_Pos       (21U)

+#define EXTI_D3PMR1_MR21_Msk       (0x1UL << EXTI_D3PMR1_MR21_Pos)             /*!< 0x00200000 */

+#define EXTI_D3PMR1_MR21           EXTI_D3PMR1_MR21_Msk                        /*!< Pending Mask Event for line 21 */

+#define EXTI_D3PMR1_MR25_Pos       (24U)

+#define EXTI_D3PMR1_MR25_Msk       (0x1UL << EXTI_D3PMR1_MR25_Pos)             /*!< 0x01000000 */

+#define EXTI_D3PMR1_MR25           EXTI_D3PMR1_MR25_Msk                        /*!< Pending Mask Event for line 25 */

+

+/*******************  Bit definition for EXTI_D3PCR1L register  ****************/

+#define EXTI_D3PCR1L_PCS0_Pos       (0U)

+#define EXTI_D3PCR1L_PCS0_Msk       (0x3UL << EXTI_D3PCR1L_PCS0_Pos)           /*!< 0x00000003 */

+#define EXTI_D3PCR1L_PCS0           EXTI_D3PCR1L_PCS0_Msk                      /*!< D3 Pending request clear input signal selection on line 0 */

+#define EXTI_D3PCR1L_PCS1_Pos       (2U)

+#define EXTI_D3PCR1L_PCS1_Msk       (0x3UL << EXTI_D3PCR1L_PCS1_Pos)           /*!< 0x000000C0 */

+#define EXTI_D3PCR1L_PCS1           EXTI_D3PCR1L_PCS1_Msk                      /*!< D3 Pending request clear input signal selection on line 1 */

+#define EXTI_D3PCR1L_PCS2_Pos       (4U)

+#define EXTI_D3PCR1L_PCS2_Msk       (0x3UL << EXTI_D3PCR1L_PCS2_Pos)           /*!< 0x00000030 */

+#define EXTI_D3PCR1L_PCS2           EXTI_D3PCR1L_PCS2_Msk                      /*!< D3 Pending request clear input signal selection on line 2 */

+#define EXTI_D3PCR1L_PCS3_Pos       (6U)

+#define EXTI_D3PCR1L_PCS3_Msk       (0x3UL << EXTI_D3PCR1L_PCS3_Pos)           /*!< 0x000000C0 */

+#define EXTI_D3PCR1L_PCS3           EXTI_D3PCR1L_PCS3_Msk                      /*!< D3 Pending request clear input signal selection on line 3 */

+#define EXTI_D3PCR1L_PCS4_Pos       (8U)

+#define EXTI_D3PCR1L_PCS4_Msk       (0x3UL << EXTI_D3PCR1L_PCS4_Pos)           /*!< 0x00000300 */

+#define EXTI_D3PCR1L_PCS4           EXTI_D3PCR1L_PCS4_Msk                      /*!< D3 Pending request clear input signal selection on line 4 */

+#define EXTI_D3PCR1L_PCS5_Pos       (10U)

+#define EXTI_D3PCR1L_PCS5_Msk       (0x3UL << EXTI_D3PCR1L_PCS5_Pos)           /*!< 0x00000C00 */

+#define EXTI_D3PCR1L_PCS5           EXTI_D3PCR1L_PCS5_Msk                      /*!< D3 Pending request clear input signal selection on line 5 */

+#define EXTI_D3PCR1L_PCS6_Pos       (12U)

+#define EXTI_D3PCR1L_PCS6_Msk       (0x3UL << EXTI_D3PCR1L_PCS6_Pos)           /*!< 0x00003000 */

+#define EXTI_D3PCR1L_PCS6           EXTI_D3PCR1L_PCS6_Msk                      /*!< D3 Pending request clear input signal selection on line 6 */

+#define EXTI_D3PCR1L_PCS7_Pos       (14U)

+#define EXTI_D3PCR1L_PCS7_Msk       (0x3UL << EXTI_D3PCR1L_PCS7_Pos)           /*!< 0x0000C000 */

+#define EXTI_D3PCR1L_PCS7           EXTI_D3PCR1L_PCS7_Msk                      /*!< D3 Pending request clear input signal selection on line 7 */

+#define EXTI_D3PCR1L_PCS8_Pos       (16U)

+#define EXTI_D3PCR1L_PCS8_Msk       (0x3UL << EXTI_D3PCR1L_PCS8_Pos)           /*!< 0x00030000 */

+#define EXTI_D3PCR1L_PCS8           EXTI_D3PCR1L_PCS8_Msk                      /*!< D3 Pending request clear input signal selection on line 8 */

+#define EXTI_D3PCR1L_PCS9_Pos       (18U)

+#define EXTI_D3PCR1L_PCS9_Msk       (0x3UL << EXTI_D3PCR1L_PCS9_Pos)           /*!< 0x000C0000 */

+#define EXTI_D3PCR1L_PCS9           EXTI_D3PCR1L_PCS9_Msk                      /*!< D3 Pending request clear input signal selection on line 9 */

+#define EXTI_D3PCR1L_PCS10_Pos      (20U)

+#define EXTI_D3PCR1L_PCS10_Msk      (0x3UL << EXTI_D3PCR1L_PCS10_Pos)          /*!< 0x00300000 */

+#define EXTI_D3PCR1L_PCS10          EXTI_D3PCR1L_PCS10_Msk                     /*!< D3 Pending request clear input signal selection on line 10*/

+#define EXTI_D3PCR1L_PCS11_Pos      (22U)

+#define EXTI_D3PCR1L_PCS11_Msk      (0x3UL << EXTI_D3PCR1L_PCS11_Pos)          /*!< 0x00C00000 */

+#define EXTI_D3PCR1L_PCS11          EXTI_D3PCR1L_PCS11_Msk                     /*!< D3 Pending request clear input signal selection on line 11*/

+#define EXTI_D3PCR1L_PCS12_Pos      (24U)

+#define EXTI_D3PCR1L_PCS12_Msk      (0x3UL << EXTI_D3PCR1L_PCS12_Pos)          /*!< 0x03000000 */

+#define EXTI_D3PCR1L_PCS12          EXTI_D3PCR1L_PCS12_Msk                     /*!< D3 Pending request clear input signal selection on line 12*/

+#define EXTI_D3PCR1L_PCS13_Pos      (26U)

+#define EXTI_D3PCR1L_PCS13_Msk      (0x3UL << EXTI_D3PCR1L_PCS13_Pos)          /*!< 0x0C000000 */

+#define EXTI_D3PCR1L_PCS13          EXTI_D3PCR1L_PCS13_Msk                     /*!< D3 Pending request clear input signal selection on line 13*/

+#define EXTI_D3PCR1L_PCS14_Pos      (28U)

+#define EXTI_D3PCR1L_PCS14_Msk      (0x3UL << EXTI_D3PCR1L_PCS14_Pos)          /*!< 0x30000000 */

+#define EXTI_D3PCR1L_PCS14          EXTI_D3PCR1L_PCS14_Msk                     /*!< D3 Pending request clear input signal selection on line 14*/

+#define EXTI_D3PCR1L_PCS15_Pos      (30U)

+#define EXTI_D3PCR1L_PCS15_Msk      (0x3UL << EXTI_D3PCR1L_PCS15_Pos)          /*!< 0xC0000000 */

+#define EXTI_D3PCR1L_PCS15          EXTI_D3PCR1L_PCS15_Msk                     /*!< D3 Pending request clear input signal selection on line 15*/

+

+/*******************  Bit definition for EXTI_D3PCR1H register  ****************/

+#define EXTI_D3PCR1H_PCS19_Pos       (6U)

+#define EXTI_D3PCR1H_PCS19_Msk       (0x3UL << EXTI_D3PCR1H_PCS19_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR1H_PCS19           EXTI_D3PCR1H_PCS19_Msk                    /*!< D3 Pending request clear input signal selection on line 19 */

+#define EXTI_D3PCR1H_PCS20_Pos       (8U)

+#define EXTI_D3PCR1H_PCS20_Msk       (0x3UL << EXTI_D3PCR1H_PCS20_Pos)         /*!< 0x00000300 */

+#define EXTI_D3PCR1H_PCS20           EXTI_D3PCR1H_PCS20_Msk                    /*!< D3 Pending request clear input signal selection on line 20 */

+#define EXTI_D3PCR1H_PCS21_Pos       (10U)

+#define EXTI_D3PCR1H_PCS21_Msk       (0x3UL << EXTI_D3PCR1H_PCS21_Pos)         /*!< 0x00000C00 */

+#define EXTI_D3PCR1H_PCS21           EXTI_D3PCR1H_PCS21_Msk                    /*!< D3 Pending request clear input signal selection on line 21 */

+#define EXTI_D3PCR1H_PCS25_Pos       (18U)

+#define EXTI_D3PCR1H_PCS25_Msk       (0x3UL << EXTI_D3PCR1H_PCS25_Pos)         /*!< 0x000C0000 */

+#define EXTI_D3PCR1H_PCS25           EXTI_D3PCR1H_PCS25_Msk                    /*!< D3 Pending request clear input signal selection on line 25 */

+

+/******************  Bit definition for EXTI_RTSR2 register  *******************/

+#define EXTI_RTSR2_TR_Pos          (17U)

+#define EXTI_RTSR2_TR_Msk          (0x5UL << EXTI_RTSR2_TR_Pos)                /*!< 0x000A0000 */

+#define EXTI_RTSR2_TR              EXTI_RTSR2_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR2_TR49_Pos        (17U)

+#define EXTI_RTSR2_TR49_Msk        (0x1UL << EXTI_RTSR2_TR49_Pos)              /*!< 0x00020000 */

+#define EXTI_RTSR2_TR49            EXTI_RTSR2_TR49_Msk                         /*!< Rising trigger event configuration bit of line 49 */

+#define EXTI_RTSR2_TR51_Pos        (19U)

+#define EXTI_RTSR2_TR51_Msk        (0x1UL << EXTI_RTSR2_TR51_Pos)              /*!< 0x00080000 */

+#define EXTI_RTSR2_TR51            EXTI_RTSR2_TR51_Msk                         /*!< Rising trigger event configuration bit of line 51 */

+

+/******************  Bit definition for EXTI_FTSR2 register  *******************/

+#define EXTI_FTSR2_TR_Pos          (17U)

+#define EXTI_FTSR2_TR_Msk          (0x5UL << EXTI_FTSR2_TR_Pos)                /*!< 0x000A0000 */

+#define EXTI_FTSR2_TR              EXTI_FTSR2_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR2_TR49_Pos        (17U)

+#define EXTI_FTSR2_TR49_Msk        (0x1UL << EXTI_FTSR2_TR49_Pos)              /*!< 0x00020000 */

+#define EXTI_FTSR2_TR49            EXTI_FTSR2_TR49_Msk                         /*!< Falling trigger event configuration bit of line 49 */

+#define EXTI_FTSR2_TR51_Pos        (19U)

+#define EXTI_FTSR2_TR51_Msk        (0x1UL << EXTI_FTSR2_TR51_Pos)              /*!< 0x00080000 */

+#define EXTI_FTSR2_TR51            EXTI_FTSR2_TR51_Msk                         /*!< Falling trigger event configuration bit of line 51 */

+

+/******************  Bit definition for EXTI_SWIER2 register  ******************/

+#define EXTI_SWIER2_SWIER49_Pos    (17U)

+#define EXTI_SWIER2_SWIER49_Msk    (0x1UL << EXTI_SWIER2_SWIER49_Pos)          /*!< 0x00020000 */

+#define EXTI_SWIER2_SWIER49        EXTI_SWIER2_SWIER49_Msk                     /*!< Software Interrupt on line 49 */

+#define EXTI_SWIER2_SWIER51_Pos    (19U)

+#define EXTI_SWIER2_SWIER51_Msk    (0x1UL << EXTI_SWIER2_SWIER51_Pos)          /*!< 0x00080000 */

+#define EXTI_SWIER2_SWIER51        EXTI_SWIER2_SWIER51_Msk                     /*!< Software Interrupt on line 51 */

+

+/******************  Bit definition for EXTI_D3PMR2 register  ******************/

+#define EXTI_D3PMR2_MR34_Pos       (2U)

+#define EXTI_D3PMR2_MR34_Msk       (0x1UL << EXTI_D3PMR2_MR34_Pos)             /*!< 0x00000004 */

+#define EXTI_D3PMR2_MR34           EXTI_D3PMR2_MR34_Msk                        /*!< Pending Mask Event for line 34  */

+#define EXTI_D3PMR2_MR35_Pos       (3U)

+#define EXTI_D3PMR2_MR35_Msk       (0x1UL << EXTI_D3PMR2_MR35_Pos)             /*!< 0x00000008 */

+#define EXTI_D3PMR2_MR35           EXTI_D3PMR2_MR35_Msk                        /*!< Pending Mask Event for line 35  */

+#define EXTI_D3PMR2_MR41_Pos       (9U)

+#define EXTI_D3PMR2_MR41_Msk       (0x1UL << EXTI_D3PMR2_MR41_Pos)             /*!< 0x00000200 */

+#define EXTI_D3PMR2_MR41           EXTI_D3PMR2_MR41_Msk                        /*!< Pending Mask Event for line 41  */

+#define EXTI_D3PMR2_MR48_Pos       (16U)

+#define EXTI_D3PMR2_MR48_Msk       (0x1UL << EXTI_D3PMR2_MR48_Pos)             /*!< 0x00010000 */

+#define EXTI_D3PMR2_MR48           EXTI_D3PMR2_MR48_Msk                        /*!< Pending Mask Event for line 48  */

+#define EXTI_D3PMR2_MR49_Pos       (17U)

+#define EXTI_D3PMR2_MR49_Msk       (0x1UL << EXTI_D3PMR2_MR49_Pos)             /*!< 0x00020000 */

+#define EXTI_D3PMR2_MR49           EXTI_D3PMR2_MR49_Msk                        /*!< Pending Mask Event for line 49  */

+#define EXTI_D3PMR2_MR50_Pos       (18U)

+#define EXTI_D3PMR2_MR50_Msk       (0x1UL << EXTI_D3PMR2_MR50_Pos)             /*!< 0x00040000 */

+#define EXTI_D3PMR2_MR50           EXTI_D3PMR2_MR50_Msk                        /*!< Pending Mask Event for line 50  */

+#define EXTI_D3PMR2_MR51_Pos       (19U)

+#define EXTI_D3PMR2_MR51_Msk       (0x1UL << EXTI_D3PMR2_MR51_Pos)             /*!< 0x00080000 */

+#define EXTI_D3PMR2_MR51           EXTI_D3PMR2_MR51_Msk                        /*!< Pending Mask Event for line 51  */

+#define EXTI_D3PMR2_MR52_Pos       (20U)

+#define EXTI_D3PMR2_MR52_Msk       (0x1UL << EXTI_D3PMR2_MR52_Pos)             /*!< 0x00100000 */

+#define EXTI_D3PMR2_MR52           EXTI_D3PMR2_MR52_Msk                        /*!< Pending Mask Event for line 52  */

+#define EXTI_D3PMR2_MR53_Pos       (21U)

+#define EXTI_D3PMR2_MR53_Msk       (0x1UL << EXTI_D3PMR2_MR53_Pos)             /*!< 0x00200000 */

+#define EXTI_D3PMR2_MR53           EXTI_D3PMR2_MR53_Msk                        /*!< Pending Mask Event for line 53  */

+/*******************  Bit definition for EXTI_D3PCR2L register  ****************/

+#define EXTI_D3PCR2L_PCS34_Pos       (4U)

+#define EXTI_D3PCR2L_PCS34_Msk       (0x3UL << EXTI_D3PCR2L_PCS34_Pos)         /*!< 0x00000030 */

+#define EXTI_D3PCR2L_PCS34           EXTI_D3PCR2L_PCS34_Msk                    /*!< D3 Pending request clear input signal selection on line 34 */

+#define EXTI_D3PCR2L_PCS35_Pos       (6U)

+#define EXTI_D3PCR2L_PCS35_Msk       (0x3UL << EXTI_D3PCR2L_PCS35_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR2L_PCS35           EXTI_D3PCR2L_PCS35_Msk                    /*!< D3 Pending request clear input signal selection on line 35 */

+#define EXTI_D3PCR2L_PCS41_Pos       (18U)

+#define EXTI_D3PCR2L_PCS41_Msk       (0x3UL << EXTI_D3PCR2L_PCS41_Pos)         /*!< 0x000C0000 */

+#define EXTI_D3PCR2L_PCS41           EXTI_D3PCR2L_PCS41_Msk                    /*!< D3 Pending request clear input signal selection on line 41 */

+

+

+/*******************  Bit definition for EXTI_D3PCR2H register  ****************/

+#define EXTI_D3PCR2H_PCS48_Pos       (0U)

+#define EXTI_D3PCR2H_PCS48_Msk       (0x3UL << EXTI_D3PCR2H_PCS48_Pos)         /*!< 0x00000003 */

+#define EXTI_D3PCR2H_PCS48           EXTI_D3PCR2H_PCS48_Msk                    /*!< D3 Pending request clear input signal selection on line 48 */

+#define EXTI_D3PCR2H_PCS49_Pos       (2U)

+#define EXTI_D3PCR2H_PCS49_Msk       (0x3UL << EXTI_D3PCR2H_PCS49_Pos)         /*!< 0x0000000C */

+#define EXTI_D3PCR2H_PCS49           EXTI_D3PCR2H_PCS49_Msk                    /*!< D3 Pending request clear input signal selection on line 49 */

+#define EXTI_D3PCR2H_PCS50_Pos       (4U)

+#define EXTI_D3PCR2H_PCS50_Msk       (0x3UL << EXTI_D3PCR2H_PCS50_Pos)         /*!< 0x00000030 */

+#define EXTI_D3PCR2H_PCS50           EXTI_D3PCR2H_PCS50_Msk                    /*!< D3 Pending request clear input signal selection on line 50 */

+#define EXTI_D3PCR2H_PCS51_Pos       (6U)

+#define EXTI_D3PCR2H_PCS51_Msk       (0x3UL << EXTI_D3PCR2H_PCS51_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR2H_PCS51           EXTI_D3PCR2H_PCS51_Msk                    /*!< D3 Pending request clear input signal selection on line 51 */

+#define EXTI_D3PCR2H_PCS52_Pos       (8U)

+#define EXTI_D3PCR2H_PCS52_Msk       (0x3UL << EXTI_D3PCR2H_PCS52_Pos)         /*!< 0x00000300 */

+#define EXTI_D3PCR2H_PCS52           EXTI_D3PCR2H_PCS52_Msk                    /*!< D3 Pending request clear input signal selection on line 52 */

+#define EXTI_D3PCR2H_PCS53_Pos       (10U)

+#define EXTI_D3PCR2H_PCS53_Msk       (0x3UL << EXTI_D3PCR2H_PCS53_Pos)         /*!< 0x00000C00 */

+#define EXTI_D3PCR2H_PCS53           EXTI_D3PCR2H_PCS53_Msk                    /*!< D3 Pending request clear input signal selection on line 53 */

+/******************  Bit definition for EXTI_RTSR3 register  *******************/

+#define EXTI_RTSR3_TR_Pos          (18U)

+#define EXTI_RTSR3_TR_Msk          (0x1DUL << EXTI_RTSR3_TR_Pos)               /*!< 0x00740000 */

+#define EXTI_RTSR3_TR              EXTI_RTSR3_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR3_TR82_Pos        (18U)

+#define EXTI_RTSR3_TR82_Msk        (0x1UL << EXTI_RTSR3_TR82_Pos)              /*!< 0x00040000 */

+#define EXTI_RTSR3_TR82            EXTI_RTSR3_TR82_Msk                         /*!< Rising trigger event configuration bit of line 82 */

+#define EXTI_RTSR3_TR84_Pos        (20U)

+#define EXTI_RTSR3_TR84_Msk        (0x1UL << EXTI_RTSR3_TR84_Pos)              /*!< 0x00100000 */

+#define EXTI_RTSR3_TR84            EXTI_RTSR3_TR84_Msk                         /*!< Rising trigger event configuration bit of line 84 */

+#define EXTI_RTSR3_TR85_Pos        (21U)

+#define EXTI_RTSR3_TR85_Msk        (0x1UL << EXTI_RTSR3_TR85_Pos)              /*!< 0x00200000 */

+#define EXTI_RTSR3_TR85            EXTI_RTSR3_TR85_Msk                         /*!< Rising trigger event configuration bit of line 85 */

+#define EXTI_RTSR3_TR86_Pos        (22U)

+#define EXTI_RTSR3_TR86_Msk        (0x1UL << EXTI_RTSR3_TR86_Pos)              /*!< 0x00400000 */

+#define EXTI_RTSR3_TR86            EXTI_RTSR3_TR86_Msk                         /*!< Rising trigger event configuration bit of line 86 */

+

+/******************  Bit definition for EXTI_FTSR3 register  *******************/

+#define EXTI_FTSR3_TR_Pos          (18U)

+#define EXTI_FTSR3_TR_Msk          (0x1DUL << EXTI_FTSR3_TR_Pos)               /*!< 0x00740000 */

+#define EXTI_FTSR3_TR              EXTI_FTSR3_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR3_TR82_Pos        (18U)

+#define EXTI_FTSR3_TR82_Msk        (0x1UL << EXTI_FTSR3_TR82_Pos)              /*!< 0x00040000 */

+#define EXTI_FTSR3_TR82            EXTI_FTSR3_TR82_Msk                         /*!< Falling trigger event configuration bit of line 82 */

+#define EXTI_FTSR3_TR84_Pos        (20U)

+#define EXTI_FTSR3_TR84_Msk        (0x1UL << EXTI_FTSR3_TR84_Pos)              /*!< 0x00100000 */

+#define EXTI_FTSR3_TR84            EXTI_FTSR3_TR84_Msk                         /*!< Falling trigger event configuration bit of line 84 */

+#define EXTI_FTSR3_TR85_Pos        (21U)

+#define EXTI_FTSR3_TR85_Msk        (0x1UL << EXTI_FTSR3_TR85_Pos)              /*!< 0x00200000 */

+#define EXTI_FTSR3_TR85            EXTI_FTSR3_TR85_Msk                         /*!< Falling trigger event configuration bit of line 85 */

+#define EXTI_FTSR3_TR86_Pos        (22U)

+#define EXTI_FTSR3_TR86_Msk        (0x1UL << EXTI_FTSR3_TR86_Pos)              /*!< 0x00400000 */

+#define EXTI_FTSR3_TR86            EXTI_FTSR3_TR86_Msk                         /*!< Falling trigger event configuration bit of line 86 */

+

+/******************  Bit definition for EXTI_SWIER3 register  ******************/

+#define EXTI_SWIER3_SWI_Pos        (18U)

+#define EXTI_SWIER3_SWI_Msk        (0x1DUL << EXTI_SWIER3_SWI_Pos)             /*!< 0x00740000 */

+#define EXTI_SWIER3_SWI            EXTI_SWIER3_SWI_Msk                         /*!< Software Interrupt event bit */

+#define EXTI_SWIER3_SWIER82_Pos    (18U)

+#define EXTI_SWIER3_SWIER82_Msk    (0x1UL << EXTI_SWIER3_SWIER82_Pos)          /*!< 0x00040000 */

+#define EXTI_SWIER3_SWIER82        EXTI_SWIER3_SWIER82_Msk                     /*!< Software Interrupt on line 82 */

+#define EXTI_SWIER3_SWIER84_Pos    (20U)

+#define EXTI_SWIER3_SWIER84_Msk    (0x1UL << EXTI_SWIER3_SWIER84_Pos)          /*!< 0x00100000 */

+#define EXTI_SWIER3_SWIER84        EXTI_SWIER3_SWIER84_Msk                     /*!< Software Interrupt on line 84 */

+#define EXTI_SWIER3_SWIER85_Pos    (21U)

+#define EXTI_SWIER3_SWIER85_Msk    (0x1UL << EXTI_SWIER3_SWIER85_Pos)          /*!< 0x00200000 */

+#define EXTI_SWIER3_SWIER85        EXTI_SWIER3_SWIER85_Msk                     /*!< Software Interrupt on line 85 */

+#define EXTI_SWIER3_SWIER86_Pos    (22U)

+#define EXTI_SWIER3_SWIER86_Msk    (0x1UL << EXTI_SWIER3_SWIER86_Pos)          /*!< 0x00400000 */

+#define EXTI_SWIER3_SWIER86        EXTI_SWIER3_SWIER86_Msk                     /*!< Software Interrupt on line 86 */

+

+/*******************  Bit definition for EXTI_IMR1 register  *******************/

+#define EXTI_IMR1_IM_Pos           (0U)

+#define EXTI_IMR1_IM_Msk           (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)          /*!< 0xFFFFFFFF */

+#define EXTI_IMR1_IM               EXTI_IMR1_IM_Msk                            /*!< Interrupt Mask */

+#define EXTI_IMR1_IM0_Pos          (0U)

+#define EXTI_IMR1_IM0_Msk          (0x1UL << EXTI_IMR1_IM0_Pos)                /*!< 0x00000001 */

+#define EXTI_IMR1_IM0              EXTI_IMR1_IM0_Msk                           /*!< Interrupt Mask on line 0 */

+#define EXTI_IMR1_IM1_Pos          (1U)

+#define EXTI_IMR1_IM1_Msk          (0x1UL << EXTI_IMR1_IM1_Pos)                /*!< 0x00000002 */

+#define EXTI_IMR1_IM1              EXTI_IMR1_IM1_Msk                           /*!< Interrupt Mask on line 1 */

+#define EXTI_IMR1_IM2_Pos          (2U)

+#define EXTI_IMR1_IM2_Msk          (0x1UL << EXTI_IMR1_IM2_Pos)                /*!< 0x00000004 */

+#define EXTI_IMR1_IM2              EXTI_IMR1_IM2_Msk                           /*!< Interrupt Mask on line 2 */

+#define EXTI_IMR1_IM3_Pos          (3U)

+#define EXTI_IMR1_IM3_Msk          (0x1UL << EXTI_IMR1_IM3_Pos)                /*!< 0x00000008 */

+#define EXTI_IMR1_IM3              EXTI_IMR1_IM3_Msk                           /*!< Interrupt Mask on line 3 */

+#define EXTI_IMR1_IM4_Pos          (4U)

+#define EXTI_IMR1_IM4_Msk          (0x1UL << EXTI_IMR1_IM4_Pos)                /*!< 0x00000010 */

+#define EXTI_IMR1_IM4              EXTI_IMR1_IM4_Msk                           /*!< Interrupt Mask on line 4 */

+#define EXTI_IMR1_IM5_Pos          (5U)

+#define EXTI_IMR1_IM5_Msk          (0x1UL << EXTI_IMR1_IM5_Pos)                /*!< 0x00000020 */

+#define EXTI_IMR1_IM5              EXTI_IMR1_IM5_Msk                           /*!< Interrupt Mask on line 5 */

+#define EXTI_IMR1_IM6_Pos          (6U)

+#define EXTI_IMR1_IM6_Msk          (0x1UL << EXTI_IMR1_IM6_Pos)                /*!< 0x00000040 */

+#define EXTI_IMR1_IM6              EXTI_IMR1_IM6_Msk                           /*!< Interrupt Mask on line 6 */

+#define EXTI_IMR1_IM7_Pos          (7U)

+#define EXTI_IMR1_IM7_Msk          (0x1UL << EXTI_IMR1_IM7_Pos)                /*!< 0x00000080 */

+#define EXTI_IMR1_IM7              EXTI_IMR1_IM7_Msk                           /*!< Interrupt Mask on line 7 */

+#define EXTI_IMR1_IM8_Pos          (8U)

+#define EXTI_IMR1_IM8_Msk          (0x1UL << EXTI_IMR1_IM8_Pos)                /*!< 0x00000100 */

+#define EXTI_IMR1_IM8              EXTI_IMR1_IM8_Msk                           /*!< Interrupt Mask on line 8 */

+#define EXTI_IMR1_IM9_Pos          (9U)

+#define EXTI_IMR1_IM9_Msk          (0x1UL << EXTI_IMR1_IM9_Pos)                /*!< 0x00000200 */

+#define EXTI_IMR1_IM9              EXTI_IMR1_IM9_Msk                           /*!< Interrupt Mask on line 9 */

+#define EXTI_IMR1_IM10_Pos         (10U)

+#define EXTI_IMR1_IM10_Msk         (0x1UL << EXTI_IMR1_IM10_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR1_IM10             EXTI_IMR1_IM10_Msk                          /*!< Interrupt Mask on line 10 */

+#define EXTI_IMR1_IM11_Pos         (11U)

+#define EXTI_IMR1_IM11_Msk         (0x1UL << EXTI_IMR1_IM11_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR1_IM11             EXTI_IMR1_IM11_Msk                          /*!< Interrupt Mask on line 11 */

+#define EXTI_IMR1_IM12_Pos         (12U)

+#define EXTI_IMR1_IM12_Msk         (0x1UL << EXTI_IMR1_IM12_Pos)               /*!< 0x00001000 */

+#define EXTI_IMR1_IM12             EXTI_IMR1_IM12_Msk                          /*!< Interrupt Mask on line 12 */

+#define EXTI_IMR1_IM13_Pos         (13U)

+#define EXTI_IMR1_IM13_Msk         (0x1UL << EXTI_IMR1_IM13_Pos)               /*!< 0x00002000 */

+#define EXTI_IMR1_IM13             EXTI_IMR1_IM13_Msk                          /*!< Interrupt Mask on line 13 */

+#define EXTI_IMR1_IM14_Pos         (14U)

+#define EXTI_IMR1_IM14_Msk         (0x1UL << EXTI_IMR1_IM14_Pos)               /*!< 0x00004000 */

+#define EXTI_IMR1_IM14             EXTI_IMR1_IM14_Msk                          /*!< Interrupt Mask on line 14 */

+#define EXTI_IMR1_IM15_Pos         (15U)

+#define EXTI_IMR1_IM15_Msk         (0x1UL << EXTI_IMR1_IM15_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR1_IM15             EXTI_IMR1_IM15_Msk                          /*!< Interrupt Mask on line 15 */

+#define EXTI_IMR1_IM16_Pos         (16U)

+#define EXTI_IMR1_IM16_Msk         (0x1UL << EXTI_IMR1_IM16_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR1_IM16             EXTI_IMR1_IM16_Msk                          /*!< Interrupt Mask on line 16 */

+#define EXTI_IMR1_IM17_Pos         (17U)

+#define EXTI_IMR1_IM17_Msk         (0x1UL << EXTI_IMR1_IM17_Pos)               /*!< 0x00020000 */

+#define EXTI_IMR1_IM17             EXTI_IMR1_IM17_Msk                          /*!< Interrupt Mask on line 17 */

+#define EXTI_IMR1_IM18_Pos         (18U)

+#define EXTI_IMR1_IM18_Msk         (0x1UL << EXTI_IMR1_IM18_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR1_IM18             EXTI_IMR1_IM18_Msk                          /*!< Interrupt Mask on line 18 */

+#define EXTI_IMR1_IM19_Pos         (19U)

+#define EXTI_IMR1_IM19_Msk         (0x1UL << EXTI_IMR1_IM19_Pos)               /*!< 0x00080000 */

+#define EXTI_IMR1_IM19             EXTI_IMR1_IM19_Msk                          /*!< Interrupt Mask on line 19 */

+#define EXTI_IMR1_IM20_Pos         (20U)

+#define EXTI_IMR1_IM20_Msk         (0x1UL << EXTI_IMR1_IM20_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR1_IM20             EXTI_IMR1_IM20_Msk                          /*!< Interrupt Mask on line 20 */

+#define EXTI_IMR1_IM21_Pos         (21U)

+#define EXTI_IMR1_IM21_Msk         (0x1UL << EXTI_IMR1_IM21_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR1_IM21             EXTI_IMR1_IM21_Msk                          /*!< Interrupt Mask on line 21 */

+#define EXTI_IMR1_IM22_Pos         (22U)

+#define EXTI_IMR1_IM22_Msk         (0x1UL << EXTI_IMR1_IM22_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR1_IM22             EXTI_IMR1_IM22_Msk                          /*!< Interrupt Mask on line 22 */

+#define EXTI_IMR1_IM23_Pos         (23U)

+#define EXTI_IMR1_IM23_Msk         (0x1UL << EXTI_IMR1_IM23_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR1_IM23             EXTI_IMR1_IM23_Msk                          /*!< Interrupt Mask on line 23 */

+#define EXTI_IMR1_IM24_Pos         (24U)

+#define EXTI_IMR1_IM24_Msk         (0x1UL << EXTI_IMR1_IM24_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR1_IM24             EXTI_IMR1_IM24_Msk                          /*!< Interrupt Mask on line 24 */

+#define EXTI_IMR1_IM25_Pos         (25U)

+#define EXTI_IMR1_IM25_Msk         (0x1UL << EXTI_IMR1_IM25_Pos)               /*!< 0x02000000 */

+#define EXTI_IMR1_IM25             EXTI_IMR1_IM25_Msk                          /*!< Interrupt Mask on line 25 */

+#define EXTI_IMR1_IM26_Pos         (26U)

+#define EXTI_IMR1_IM26_Msk         (0x1UL << EXTI_IMR1_IM26_Pos)               /*!< 0x04000000 */

+#define EXTI_IMR1_IM26             EXTI_IMR1_IM26_Msk                          /*!< Interrupt Mask on line 26 */

+#define EXTI_IMR1_IM27_Pos         (27U)

+#define EXTI_IMR1_IM27_Msk         (0x1UL << EXTI_IMR1_IM27_Pos)               /*!< 0x08000000 */

+#define EXTI_IMR1_IM27             EXTI_IMR1_IM27_Msk                          /*!< Interrupt Mask on line 27 */

+#define EXTI_IMR1_IM28_Pos         (28U)

+#define EXTI_IMR1_IM28_Msk         (0x1UL << EXTI_IMR1_IM28_Pos)               /*!< 0x10000000 */

+#define EXTI_IMR1_IM28             EXTI_IMR1_IM28_Msk                          /*!< Interrupt Mask on line 28 */

+#define EXTI_IMR1_IM29_Pos         (29U)

+#define EXTI_IMR1_IM29_Msk         (0x1UL << EXTI_IMR1_IM29_Pos)               /*!< 0x20000000 */

+#define EXTI_IMR1_IM29             EXTI_IMR1_IM29_Msk                          /*!< Interrupt Mask on line 29 */

+#define EXTI_IMR1_IM30_Pos         (30U)

+#define EXTI_IMR1_IM30_Msk         (0x1UL << EXTI_IMR1_IM30_Pos)               /*!< 0x40000000 */

+#define EXTI_IMR1_IM30             EXTI_IMR1_IM30_Msk                          /*!< Interrupt Mask on line 30 */

+#define EXTI_IMR1_IM31_Pos         (31U)

+#define EXTI_IMR1_IM31_Msk         (0x1UL << EXTI_IMR1_IM31_Pos)               /*!< 0x80000000 */

+#define EXTI_IMR1_IM31             EXTI_IMR1_IM31_Msk                          /*!< Interrupt Mask on line 31 */

+

+/*******************  Bit definition for EXTI_EMR1 register  *******************/

+#define EXTI_EMR1_EM_Pos           (0U)

+#define EXTI_EMR1_EM_Msk           (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)          /*!< 0xFFFFFFFF */

+#define EXTI_EMR1_EM               EXTI_EMR1_EM_Msk                            /*!< Event Mask */

+#define EXTI_EMR1_EM0_Pos          (0U)

+#define EXTI_EMR1_EM0_Msk          (0x1UL << EXTI_EMR1_EM0_Pos)                /*!< 0x00000001 */

+#define EXTI_EMR1_EM0              EXTI_EMR1_EM0_Msk                           /*!< Event Mask on line 0 */

+#define EXTI_EMR1_EM1_Pos          (1U)

+#define EXTI_EMR1_EM1_Msk          (0x1UL << EXTI_EMR1_EM1_Pos)                /*!< 0x00000002 */

+#define EXTI_EMR1_EM1              EXTI_EMR1_EM1_Msk                           /*!< Event Mask on line 1 */

+#define EXTI_EMR1_EM2_Pos          (2U)

+#define EXTI_EMR1_EM2_Msk          (0x1UL << EXTI_EMR1_EM2_Pos)                /*!< 0x00000004 */

+#define EXTI_EMR1_EM2              EXTI_EMR1_EM2_Msk                           /*!< Event Mask on line 2 */

+#define EXTI_EMR1_EM3_Pos          (3U)

+#define EXTI_EMR1_EM3_Msk          (0x1UL << EXTI_EMR1_EM3_Pos)                /*!< 0x00000008 */

+#define EXTI_EMR1_EM3              EXTI_EMR1_EM3_Msk                           /*!< Event Mask on line 3 */

+#define EXTI_EMR1_EM4_Pos          (4U)

+#define EXTI_EMR1_EM4_Msk          (0x1UL << EXTI_EMR1_EM4_Pos)                /*!< 0x00000010 */

+#define EXTI_EMR1_EM4              EXTI_EMR1_EM4_Msk                           /*!< Event Mask on line 4 */

+#define EXTI_EMR1_EM5_Pos          (5U)

+#define EXTI_EMR1_EM5_Msk          (0x1UL << EXTI_EMR1_EM5_Pos)                /*!< 0x00000020 */

+#define EXTI_EMR1_EM5              EXTI_EMR1_EM5_Msk                           /*!< Event Mask on line 5 */

+#define EXTI_EMR1_EM6_Pos          (6U)

+#define EXTI_EMR1_EM6_Msk          (0x1UL << EXTI_EMR1_EM6_Pos)                /*!< 0x00000040 */

+#define EXTI_EMR1_EM6              EXTI_EMR1_EM6_Msk                           /*!< Event Mask on line 6 */

+#define EXTI_EMR1_EM7_Pos          (7U)

+#define EXTI_EMR1_EM7_Msk          (0x1UL << EXTI_EMR1_EM7_Pos)                /*!< 0x00000080 */

+#define EXTI_EMR1_EM7              EXTI_EMR1_EM7_Msk                           /*!< Event Mask on line 7 */

+#define EXTI_EMR1_EM8_Pos          (8U)

+#define EXTI_EMR1_EM8_Msk          (0x1UL << EXTI_EMR1_EM8_Pos)                /*!< 0x00000100 */

+#define EXTI_EMR1_EM8              EXTI_EMR1_EM8_Msk                           /*!< Event Mask on line 8 */

+#define EXTI_EMR1_EM9_Pos          (9U)

+#define EXTI_EMR1_EM9_Msk          (0x1UL << EXTI_EMR1_EM9_Pos)                /*!< 0x00000200 */

+#define EXTI_EMR1_EM9              EXTI_EMR1_EM9_Msk                           /*!< Event Mask on line 9 */

+#define EXTI_EMR1_EM10_Pos         (10U)

+#define EXTI_EMR1_EM10_Msk         (0x1UL << EXTI_EMR1_EM10_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR1_EM10             EXTI_EMR1_EM10_Msk                          /*!< Event Mask on line 10 */

+#define EXTI_EMR1_EM11_Pos         (11U)

+#define EXTI_EMR1_EM11_Msk         (0x1UL << EXTI_EMR1_EM11_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR1_EM11             EXTI_EMR1_EM11_Msk                          /*!< Event Mask on line 11 */

+#define EXTI_EMR1_EM12_Pos         (12U)

+#define EXTI_EMR1_EM12_Msk         (0x1UL << EXTI_EMR1_EM12_Pos)               /*!< 0x00001000 */

+#define EXTI_EMR1_EM12             EXTI_EMR1_EM12_Msk                          /*!< Event Mask on line 12 */

+#define EXTI_EMR1_EM13_Pos         (13U)

+#define EXTI_EMR1_EM13_Msk         (0x1UL << EXTI_EMR1_EM13_Pos)               /*!< 0x00002000 */

+#define EXTI_EMR1_EM13             EXTI_EMR1_EM13_Msk                          /*!< Event Mask on line 13 */

+#define EXTI_EMR1_EM14_Pos         (14U)

+#define EXTI_EMR1_EM14_Msk         (0x1UL << EXTI_EMR1_EM14_Pos)               /*!< 0x00004000 */

+#define EXTI_EMR1_EM14             EXTI_EMR1_EM14_Msk                          /*!< Event Mask on line 14 */

+#define EXTI_EMR1_EM15_Pos         (15U)

+#define EXTI_EMR1_EM15_Msk         (0x1UL << EXTI_EMR1_EM15_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR1_EM15             EXTI_EMR1_EM15_Msk                          /*!< Event Mask on line 15 */

+#define EXTI_EMR1_EM16_Pos         (16U)

+#define EXTI_EMR1_EM16_Msk         (0x1UL << EXTI_EMR1_EM16_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR1_EM16             EXTI_EMR1_EM16_Msk                          /*!< Event Mask on line 16 */

+#define EXTI_EMR1_EM17_Pos         (17U)

+#define EXTI_EMR1_EM17_Msk         (0x1UL << EXTI_EMR1_EM17_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR1_EM17             EXTI_EMR1_EM17_Msk                          /*!< Event Mask on line 17 */

+#define EXTI_EMR1_EM18_Pos         (18U)

+#define EXTI_EMR1_EM18_Msk         (0x1UL << EXTI_EMR1_EM18_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR1_EM18             EXTI_EMR1_EM18_Msk                          /*!< Event Mask on line 18 */

+#define EXTI_EMR1_EM20_Pos         (20U)

+#define EXTI_EMR1_EM20_Msk         (0x1UL << EXTI_EMR1_EM20_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR1_EM20             EXTI_EMR1_EM20_Msk                          /*!< Event Mask on line 20 */

+#define EXTI_EMR1_EM21_Pos         (21U)

+#define EXTI_EMR1_EM21_Msk         (0x1UL << EXTI_EMR1_EM21_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR1_EM21             EXTI_EMR1_EM21_Msk                          /*!< Event Mask on line 21 */

+#define EXTI_EMR1_EM22_Pos         (22U)

+#define EXTI_EMR1_EM22_Msk         (0x1UL << EXTI_EMR1_EM22_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR1_EM22             EXTI_EMR1_EM22_Msk                          /*!< Event Mask on line 22 */

+#define EXTI_EMR1_EM23_Pos         (23U)

+#define EXTI_EMR1_EM23_Msk         (0x1UL << EXTI_EMR1_EM23_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR1_EM23             EXTI_EMR1_EM23_Msk                          /*!< Event Mask on line 23 */

+#define EXTI_EMR1_EM24_Pos         (24U)

+#define EXTI_EMR1_EM24_Msk         (0x1UL << EXTI_EMR1_EM24_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR1_EM24             EXTI_EMR1_EM24_Msk                          /*!< Event Mask on line 24 */

+#define EXTI_EMR1_EM25_Pos         (25U)

+#define EXTI_EMR1_EM25_Msk         (0x1UL << EXTI_EMR1_EM25_Pos)               /*!< 0x02000000 */

+#define EXTI_EMR1_EM25             EXTI_EMR1_EM25_Msk                          /*!< Event Mask on line 25 */

+#define EXTI_EMR1_EM26_Pos         (26U)

+#define EXTI_EMR1_EM26_Msk         (0x1UL << EXTI_EMR1_EM26_Pos)               /*!< 0x04000000 */

+#define EXTI_EMR1_EM26             EXTI_EMR1_EM26_Msk                          /*!< Event Mask on line 26 */

+#define EXTI_EMR1_EM27_Pos         (27U)

+#define EXTI_EMR1_EM27_Msk         (0x1UL << EXTI_EMR1_EM27_Pos)               /*!< 0x08000000 */

+#define EXTI_EMR1_EM27             EXTI_EMR1_EM27_Msk                          /*!< Event Mask on line 27 */

+#define EXTI_EMR1_EM28_Pos         (28U)

+#define EXTI_EMR1_EM28_Msk         (0x1UL << EXTI_EMR1_EM28_Pos)               /*!< 0x10000000 */

+#define EXTI_EMR1_EM28             EXTI_EMR1_EM28_Msk                          /*!< Event Mask on line 28 */

+#define EXTI_EMR1_EM29_Pos         (29U)

+#define EXTI_EMR1_EM29_Msk         (0x1UL << EXTI_EMR1_EM29_Pos)               /*!< 0x20000000 */

+#define EXTI_EMR1_EM29             EXTI_EMR1_EM29_Msk                          /*!< Event Mask on line 29 */

+#define EXTI_EMR1_EM30_Pos         (30U)

+#define EXTI_EMR1_EM30_Msk         (0x1UL << EXTI_EMR1_EM30_Pos)               /*!< 0x40000000 */

+#define EXTI_EMR1_EM30             EXTI_EMR1_EM30_Msk                          /*!< Event Mask on line 30 */

+#define EXTI_EMR1_EM31_Pos         (31U)

+#define EXTI_EMR1_EM31_Msk         (0x1UL << EXTI_EMR1_EM31_Pos)               /*!< 0x80000000 */

+#define EXTI_EMR1_EM31             EXTI_EMR1_EM31_Msk                          /*!< Event Mask on line 31 */

+

+/*******************  Bit definition for EXTI_PR1 register  ********************/

+#define EXTI_PR1_PR_Pos            (0U)

+#define EXTI_PR1_PR_Msk            (0x3FFFFFUL << EXTI_PR1_PR_Pos)             /*!< 0x003FFFFF */

+#define EXTI_PR1_PR                EXTI_PR1_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR1_PR0_Pos           (0U)

+#define EXTI_PR1_PR0_Msk           (0x1UL << EXTI_PR1_PR0_Pos)                 /*!< 0x00000001 */

+#define EXTI_PR1_PR0               EXTI_PR1_PR0_Msk                            /*!< Pending bit for line 0 */

+#define EXTI_PR1_PR1_Pos           (1U)

+#define EXTI_PR1_PR1_Msk           (0x1UL << EXTI_PR1_PR1_Pos)                 /*!< 0x00000002 */

+#define EXTI_PR1_PR1               EXTI_PR1_PR1_Msk                            /*!< Pending bit for line 1 */

+#define EXTI_PR1_PR2_Pos           (2U)

+#define EXTI_PR1_PR2_Msk           (0x1UL << EXTI_PR1_PR2_Pos)                 /*!< 0x00000004 */

+#define EXTI_PR1_PR2               EXTI_PR1_PR2_Msk                            /*!< Pending bit for line 2 */

+#define EXTI_PR1_PR3_Pos           (3U)

+#define EXTI_PR1_PR3_Msk           (0x1UL << EXTI_PR1_PR3_Pos)                 /*!< 0x00000008 */

+#define EXTI_PR1_PR3               EXTI_PR1_PR3_Msk                            /*!< Pending bit for line 3 */

+#define EXTI_PR1_PR4_Pos           (4U)

+#define EXTI_PR1_PR4_Msk           (0x1UL << EXTI_PR1_PR4_Pos)                 /*!< 0x00000010 */

+#define EXTI_PR1_PR4               EXTI_PR1_PR4_Msk                            /*!< Pending bit for line 4 */

+#define EXTI_PR1_PR5_Pos           (5U)

+#define EXTI_PR1_PR5_Msk           (0x1UL << EXTI_PR1_PR5_Pos)                 /*!< 0x00000020 */

+#define EXTI_PR1_PR5               EXTI_PR1_PR5_Msk                            /*!< Pending bit for line 5 */

+#define EXTI_PR1_PR6_Pos           (6U)

+#define EXTI_PR1_PR6_Msk           (0x1UL << EXTI_PR1_PR6_Pos)                 /*!< 0x00000040 */

+#define EXTI_PR1_PR6               EXTI_PR1_PR6_Msk                            /*!< Pending bit for line 6 */

+#define EXTI_PR1_PR7_Pos           (7U)

+#define EXTI_PR1_PR7_Msk           (0x1UL << EXTI_PR1_PR7_Pos)                 /*!< 0x00000080 */

+#define EXTI_PR1_PR7               EXTI_PR1_PR7_Msk                            /*!< Pending bit for line 7 */

+#define EXTI_PR1_PR8_Pos           (8U)

+#define EXTI_PR1_PR8_Msk           (0x1UL << EXTI_PR1_PR8_Pos)                 /*!< 0x00000100 */

+#define EXTI_PR1_PR8               EXTI_PR1_PR8_Msk                            /*!< Pending bit for line 8 */

+#define EXTI_PR1_PR9_Pos           (9U)

+#define EXTI_PR1_PR9_Msk           (0x1UL << EXTI_PR1_PR9_Pos)                 /*!< 0x00000200 */

+#define EXTI_PR1_PR9               EXTI_PR1_PR9_Msk                            /*!< Pending bit for line 9 */

+#define EXTI_PR1_PR10_Pos          (10U)

+#define EXTI_PR1_PR10_Msk          (0x1UL << EXTI_PR1_PR10_Pos)                /*!< 0x00000400 */

+#define EXTI_PR1_PR10              EXTI_PR1_PR10_Msk                           /*!< Pending bit for line 10 */

+#define EXTI_PR1_PR11_Pos          (11U)

+#define EXTI_PR1_PR11_Msk          (0x1UL << EXTI_PR1_PR11_Pos)                /*!< 0x00000800 */

+#define EXTI_PR1_PR11              EXTI_PR1_PR11_Msk                           /*!< Pending bit for line 11 */

+#define EXTI_PR1_PR12_Pos          (12U)

+#define EXTI_PR1_PR12_Msk          (0x1UL << EXTI_PR1_PR12_Pos)                /*!< 0x00001000 */

+#define EXTI_PR1_PR12              EXTI_PR1_PR12_Msk                           /*!< Pending bit for line 12 */

+#define EXTI_PR1_PR13_Pos          (13U)

+#define EXTI_PR1_PR13_Msk          (0x1UL << EXTI_PR1_PR13_Pos)                /*!< 0x00002000 */

+#define EXTI_PR1_PR13              EXTI_PR1_PR13_Msk                           /*!< Pending bit for line 13 */

+#define EXTI_PR1_PR14_Pos          (14U)

+#define EXTI_PR1_PR14_Msk          (0x1UL << EXTI_PR1_PR14_Pos)                /*!< 0x00004000 */

+#define EXTI_PR1_PR14              EXTI_PR1_PR14_Msk                           /*!< Pending bit for line 14 */

+#define EXTI_PR1_PR15_Pos          (15U)

+#define EXTI_PR1_PR15_Msk          (0x1UL << EXTI_PR1_PR15_Pos)                /*!< 0x00008000 */

+#define EXTI_PR1_PR15              EXTI_PR1_PR15_Msk                           /*!< Pending bit for line 15 */

+#define EXTI_PR1_PR16_Pos          (16U)

+#define EXTI_PR1_PR16_Msk          (0x1UL << EXTI_PR1_PR16_Pos)                /*!< 0x00010000 */

+#define EXTI_PR1_PR16              EXTI_PR1_PR16_Msk                           /*!< Pending bit for line 16 */

+#define EXTI_PR1_PR17_Pos          (17U)

+#define EXTI_PR1_PR17_Msk          (0x1UL << EXTI_PR1_PR17_Pos)                /*!< 0x00020000 */

+#define EXTI_PR1_PR17              EXTI_PR1_PR17_Msk                           /*!< Pending bit for line 17 */

+#define EXTI_PR1_PR18_Pos          (18U)

+#define EXTI_PR1_PR18_Msk          (0x1UL << EXTI_PR1_PR18_Pos)                /*!< 0x00040000 */

+#define EXTI_PR1_PR18              EXTI_PR1_PR18_Msk                           /*!< Pending bit for line 18 */

+#define EXTI_PR1_PR19_Pos          (19U)

+#define EXTI_PR1_PR19_Msk          (0x1UL << EXTI_PR1_PR19_Pos)                /*!< 0x00080000 */

+#define EXTI_PR1_PR19              EXTI_PR1_PR19_Msk                           /*!< Pending bit for line 19 */

+#define EXTI_PR1_PR20_Pos          (20U)

+#define EXTI_PR1_PR20_Msk          (0x1UL << EXTI_PR1_PR20_Pos)                /*!< 0x00100000 */

+#define EXTI_PR1_PR20              EXTI_PR1_PR20_Msk                           /*!< Pending bit for line 20 */

+#define EXTI_PR1_PR21_Pos          (21U)

+#define EXTI_PR1_PR21_Msk          (0x1UL << EXTI_PR1_PR21_Pos)                /*!< 0x00200000 */

+#define EXTI_PR1_PR21              EXTI_PR1_PR21_Msk                           /*!< Pending bit for line 21 */

+

+/*******************  Bit definition for EXTI_IMR2 register  *******************/

+#define EXTI_IMR2_IM_Pos           (0U)

+#define EXTI_IMR2_IM_Msk           (0xFFFFDFFFUL << EXTI_IMR2_IM_Pos)          /*!< 0xFFFFDFFF */

+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            /*!< Interrupt Mask */

+#define EXTI_IMR2_IM32_Pos         (0U)

+#define EXTI_IMR2_IM32_Msk         (0x1UL << EXTI_IMR2_IM32_Pos)               /*!< 0x00000001 */

+#define EXTI_IMR2_IM32             EXTI_IMR2_IM32_Msk                          /*!< Interrupt Mask on line 32 */

+#define EXTI_IMR2_IM33_Pos         (1U)

+#define EXTI_IMR2_IM33_Msk         (0x1UL << EXTI_IMR2_IM33_Pos)               /*!< 0x00000002 */

+#define EXTI_IMR2_IM33             EXTI_IMR2_IM33_Msk                          /*!< Interrupt Mask on line 33 */

+#define EXTI_IMR2_IM34_Pos         (2U)

+#define EXTI_IMR2_IM34_Msk         (0x1UL << EXTI_IMR2_IM34_Pos)               /*!< 0x00000004 */

+#define EXTI_IMR2_IM34             EXTI_IMR2_IM34_Msk                          /*!< Interrupt Mask on line 34 */

+#define EXTI_IMR2_IM35_Pos         (3U)

+#define EXTI_IMR2_IM35_Msk         (0x1UL << EXTI_IMR2_IM35_Pos)               /*!< 0x00000008 */

+#define EXTI_IMR2_IM35             EXTI_IMR2_IM35_Msk                          /*!< Interrupt Mask on line 35 */

+#define EXTI_IMR2_IM36_Pos         (4U)

+#define EXTI_IMR2_IM36_Msk         (0x1UL << EXTI_IMR2_IM36_Pos)               /*!< 0x00000010 */

+#define EXTI_IMR2_IM36             EXTI_IMR2_IM36_Msk                          /*!< Interrupt Mask on line 36 */

+#define EXTI_IMR2_IM37_Pos         (5U)

+#define EXTI_IMR2_IM37_Msk         (0x1UL << EXTI_IMR2_IM37_Pos)               /*!< 0x00000020 */

+#define EXTI_IMR2_IM37             EXTI_IMR2_IM37_Msk                          /*!< Interrupt Mask on line 37 */

+#define EXTI_IMR2_IM38_Pos         (6U)

+#define EXTI_IMR2_IM38_Msk         (0x1UL << EXTI_IMR2_IM38_Pos)               /*!< 0x00000040 */

+#define EXTI_IMR2_IM38             EXTI_IMR2_IM38_Msk                          /*!< Interrupt Mask on line 38 */

+#define EXTI_IMR2_IM39_Pos         (7U)

+#define EXTI_IMR2_IM39_Msk         (0x1UL << EXTI_IMR2_IM39_Pos)               /*!< 0x00000080 */

+#define EXTI_IMR2_IM39             EXTI_IMR2_IM39_Msk                          /*!< Interrupt Mask on line 39 */

+#define EXTI_IMR2_IM40_Pos         (8U)

+#define EXTI_IMR2_IM40_Msk         (0x1UL << EXTI_IMR2_IM40_Pos)               /*!< 0x00000100 */

+#define EXTI_IMR2_IM40             EXTI_IMR2_IM40_Msk                          /*!< Interrupt Mask on line 40 */

+#define EXTI_IMR2_IM41_Pos         (9U)

+#define EXTI_IMR2_IM41_Msk         (0x1UL << EXTI_IMR2_IM41_Pos)               /*!< 0x00000200 */

+#define EXTI_IMR2_IM41             EXTI_IMR2_IM41_Msk                          /*!< Interrupt Mask on line 41 */

+#define EXTI_IMR2_IM42_Pos         (10U)

+#define EXTI_IMR2_IM42_Msk         (0x1UL << EXTI_IMR2_IM42_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR2_IM42             EXTI_IMR2_IM42_Msk                          /*!< Interrupt Mask on line 42 */

+#define EXTI_IMR2_IM43_Pos         (11U)

+#define EXTI_IMR2_IM43_Msk         (0x1UL << EXTI_IMR2_IM43_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR2_IM43             EXTI_IMR2_IM43_Msk                          /*!< Interrupt Mask on line 43 */

+#define EXTI_IMR2_IM44_Pos         (12U)

+#define EXTI_IMR2_IM44_Msk         (0x1UL << EXTI_IMR2_IM44_Pos)               /*!< 0x00001000 */

+#define EXTI_IMR2_IM44             EXTI_IMR2_IM44_Msk                          /*!< Interrupt Mask on line 44 */

+#define EXTI_IMR2_IM46_Pos         (14U)

+#define EXTI_IMR2_IM46_Msk         (0x1UL << EXTI_IMR2_IM46_Pos)               /*!< 0x00004000 */

+#define EXTI_IMR2_IM46             EXTI_IMR2_IM46_Msk                          /*!< Interrupt Mask on line 46 */

+#define EXTI_IMR2_IM47_Pos         (15U)

+#define EXTI_IMR2_IM47_Msk         (0x1UL << EXTI_IMR2_IM47_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR2_IM47             EXTI_IMR2_IM47_Msk                          /*!< Interrupt Mask on line 47 */

+#define EXTI_IMR2_IM48_Pos         (16U)

+#define EXTI_IMR2_IM48_Msk         (0x1UL << EXTI_IMR2_IM48_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR2_IM48             EXTI_IMR2_IM48_Msk                          /*!< Interrupt Mask on line 48 */

+#define EXTI_IMR2_IM49_Pos         (17U)

+#define EXTI_IMR2_IM49_Msk         (0x1UL << EXTI_IMR2_IM49_Pos)               /*!< 0x00020000 */

+#define EXTI_IMR2_IM49             EXTI_IMR2_IM49_Msk                          /*!< Interrupt Mask on line 49 */

+#define EXTI_IMR2_IM50_Pos         (18U)

+#define EXTI_IMR2_IM50_Msk         (0x1UL << EXTI_IMR2_IM50_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR2_IM50             EXTI_IMR2_IM50_Msk                          /*!< Interrupt Mask on line 50 */

+#define EXTI_IMR2_IM51_Pos         (19U)

+#define EXTI_IMR2_IM51_Msk         (0x1UL << EXTI_IMR2_IM51_Pos)               /*!< 0x00080000 */

+#define EXTI_IMR2_IM51             EXTI_IMR2_IM51_Msk                          /*!< Interrupt Mask on line 51 */

+#define EXTI_IMR2_IM52_Pos         (20U)

+#define EXTI_IMR2_IM52_Msk         (0x1UL << EXTI_IMR2_IM52_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR2_IM52             EXTI_IMR2_IM52_Msk                          /*!< Interrupt Mask on line 52 */

+#define EXTI_IMR2_IM53_Pos         (21U)

+#define EXTI_IMR2_IM53_Msk         (0x1UL << EXTI_IMR2_IM53_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR2_IM53             EXTI_IMR2_IM53_Msk                          /*!< Interrupt Mask on line 53 */

+#define EXTI_IMR2_IM54_Pos         (22U)

+#define EXTI_IMR2_IM54_Msk         (0x1UL << EXTI_IMR2_IM54_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR2_IM54             EXTI_IMR2_IM54_Msk                          /*!< Interrupt Mask on line 54 */

+#define EXTI_IMR2_IM55_Pos         (23U)

+#define EXTI_IMR2_IM55_Msk         (0x1UL << EXTI_IMR2_IM55_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR2_IM55             EXTI_IMR2_IM55_Msk                          /*!< Interrupt Mask on line 55 */

+#define EXTI_IMR2_IM56_Pos         (24U)

+#define EXTI_IMR2_IM56_Msk         (0x1UL << EXTI_IMR2_IM56_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR2_IM56             EXTI_IMR2_IM56_Msk                          /*!< Interrupt Mask on line 56 */

+#define EXTI_IMR2_IM57_Pos         (25U)

+#define EXTI_IMR2_IM57_Msk         (0x1UL << EXTI_IMR2_IM57_Pos)               /*!< 0x02000000 */

+#define EXTI_IMR2_IM57             EXTI_IMR2_IM57_Msk                          /*!< Interrupt Mask on line 57 */

+#define EXTI_IMR2_IM58_Pos         (26U)

+#define EXTI_IMR2_IM58_Msk         (0x1UL << EXTI_IMR2_IM58_Pos)               /*!< 0x04000000 */

+#define EXTI_IMR2_IM58             EXTI_IMR2_IM58_Msk                          /*!< Interrupt Mask on line 58 */

+#define EXTI_IMR2_IM59_Pos         (27U)

+#define EXTI_IMR2_IM59_Msk         (0x1UL << EXTI_IMR2_IM59_Pos)               /*!< 0x08000000 */

+#define EXTI_IMR2_IM59             EXTI_IMR2_IM59_Msk                          /*!< Interrupt Mask on line 59 */

+#define EXTI_IMR2_IM60_Pos         (28U)

+#define EXTI_IMR2_IM60_Msk         (0x1UL << EXTI_IMR2_IM60_Pos)               /*!< 0x10000000 */

+#define EXTI_IMR2_IM60             EXTI_IMR2_IM60_Msk                          /*!< Interrupt Mask on line 60 */

+#define EXTI_IMR2_IM61_Pos         (29U)

+#define EXTI_IMR2_IM61_Msk         (0x1UL << EXTI_IMR2_IM61_Pos)               /*!< 0x20000000 */

+#define EXTI_IMR2_IM61             EXTI_IMR2_IM61_Msk                          /*!< Interrupt Mask on line 61 */

+#define EXTI_IMR2_IM62_Pos         (30U)

+#define EXTI_IMR2_IM62_Msk         (0x1UL << EXTI_IMR2_IM62_Pos)               /*!< 0x40000000 */

+#define EXTI_IMR2_IM62             EXTI_IMR2_IM62_Msk                          /*!< Interrupt Mask on line 62 */

+#define EXTI_IMR2_IM63_Pos         (31U)

+#define EXTI_IMR2_IM63_Msk         (0x1UL << EXTI_IMR2_IM63_Pos)               /*!< 0x80000000 */

+#define EXTI_IMR2_IM63             EXTI_IMR2_IM63_Msk                          /*!< Interrupt Mask on line 63 */

+

+/*******************  Bit definition for EXTI_EMR2 register  *******************/

+#define EXTI_EMR2_EM_Pos           (0U)

+#define EXTI_EMR2_EM_Msk           (0xFFFFDFFFUL << EXTI_EMR2_EM_Pos)          /*!< 0xFFFFDFFF */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            /*!< Event Mask */

+#define EXTI_EMR2_EM32_Pos         (0U)

+#define EXTI_EMR2_EM32_Msk         (0x1UL << EXTI_EMR2_EM32_Pos)               /*!< 0x00000001 */

+#define EXTI_EMR2_EM32             EXTI_EMR2_EM32_Msk                          /*!< Event Mask on line 32*/

+#define EXTI_EMR2_EM33_Pos         (1U)

+#define EXTI_EMR2_EM33_Msk         (0x1UL << EXTI_EMR2_EM33_Pos)               /*!< 0x00000002 */

+#define EXTI_EMR2_EM33             EXTI_EMR2_EM33_Msk                          /*!< Event Mask on line 33*/

+#define EXTI_EMR2_EM34_Pos         (2U)

+#define EXTI_EMR2_EM34_Msk         (0x1UL << EXTI_EMR2_EM34_Pos)               /*!< 0x00000004 */

+#define EXTI_EMR2_EM34             EXTI_EMR2_EM34_Msk                          /*!< Event Mask on line 34*/

+#define EXTI_EMR2_EM35_Pos         (3U)

+#define EXTI_EMR2_EM35_Msk         (0x1UL << EXTI_EMR2_EM35_Pos)               /*!< 0x00000008 */

+#define EXTI_EMR2_EM35             EXTI_EMR2_EM35_Msk                          /*!< Event Mask on line 35*/

+#define EXTI_EMR2_EM36_Pos         (4U)

+#define EXTI_EMR2_EM36_Msk         (0x1UL << EXTI_EMR2_EM36_Pos)               /*!< 0x00000010 */

+#define EXTI_EMR2_EM36             EXTI_EMR2_EM36_Msk                          /*!< Event Mask on line 36*/

+#define EXTI_EMR2_EM37_Pos         (5U)

+#define EXTI_EMR2_EM37_Msk         (0x1UL << EXTI_EMR2_EM37_Pos)               /*!< 0x00000020 */

+#define EXTI_EMR2_EM37             EXTI_EMR2_EM37_Msk                          /*!< Event Mask on line 37*/

+#define EXTI_EMR2_EM38_Pos         (6U)

+#define EXTI_EMR2_EM38_Msk         (0x1UL << EXTI_EMR2_EM38_Pos)               /*!< 0x00000040 */

+#define EXTI_EMR2_EM38             EXTI_EMR2_EM38_Msk                          /*!< Event Mask on line 38*/

+#define EXTI_EMR2_EM39_Pos         (7U)

+#define EXTI_EMR2_EM39_Msk         (0x1UL << EXTI_EMR2_EM39_Pos)               /*!< 0x00000080 */

+#define EXTI_EMR2_EM39             EXTI_EMR2_EM39_Msk                          /*!< Event Mask on line 39*/

+#define EXTI_EMR2_EM40_Pos         (8U)

+#define EXTI_EMR2_EM40_Msk         (0x1UL << EXTI_EMR2_EM40_Pos)               /*!< 0x00000100 */

+#define EXTI_EMR2_EM40             EXTI_EMR2_EM40_Msk                          /*!< Event Mask on line 40*/

+#define EXTI_EMR2_EM41_Pos         (9U)

+#define EXTI_EMR2_EM41_Msk         (0x1UL << EXTI_EMR2_EM41_Pos)               /*!< 0x00000200 */

+#define EXTI_EMR2_EM41             EXTI_EMR2_EM41_Msk                          /*!< Event Mask on line 41*/

+#define EXTI_EMR2_EM42_Pos         (10U)

+#define EXTI_EMR2_EM42_Msk         (0x1UL << EXTI_EMR2_EM42_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR2_EM42             EXTI_EMR2_EM42_Msk                          /*!< Event Mask on line 42 */

+#define EXTI_EMR2_EM43_Pos         (11U)

+#define EXTI_EMR2_EM43_Msk         (0x1UL << EXTI_EMR2_EM43_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR2_EM43             EXTI_EMR2_EM43_Msk                          /*!< Event Mask on line 43 */

+#define EXTI_EMR2_EM44_Pos         (12U)

+#define EXTI_EMR2_EM44_Msk         (0x1UL << EXTI_EMR2_EM44_Pos)               /*!< 0x00001000 */

+#define EXTI_EMR2_EM44             EXTI_EMR2_EM44_Msk                          /*!< Event Mask on line 44 */

+#define EXTI_EMR2_EM46_Pos         (14U)

+#define EXTI_EMR2_EM46_Msk         (0x1UL << EXTI_EMR2_EM46_Pos)               /*!< 0x00004000 */

+#define EXTI_EMR2_EM46             EXTI_EMR2_EM46_Msk                          /*!< Event Mask on line 46 */

+#define EXTI_EMR2_EM47_Pos         (15U)

+#define EXTI_EMR2_EM47_Msk         (0x1UL << EXTI_EMR2_EM47_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR2_EM47             EXTI_EMR2_EM47_Msk                          /*!< Event Mask on line 47 */

+#define EXTI_EMR2_EM48_Pos         (16U)

+#define EXTI_EMR2_EM48_Msk         (0x1UL << EXTI_EMR2_EM48_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR2_EM48             EXTI_EMR2_EM48_Msk                          /*!< Event Mask on line 48 */

+#define EXTI_EMR2_EM49_Pos         (17U)

+#define EXTI_EMR2_EM49_Msk         (0x1UL << EXTI_EMR2_EM49_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR2_EM49             EXTI_EMR2_EM49_Msk                          /*!< Event Mask on line 49 */

+#define EXTI_EMR2_EM50_Pos         (18U)

+#define EXTI_EMR2_EM50_Msk         (0x1UL << EXTI_EMR2_EM50_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR2_EM50             EXTI_EMR2_EM50_Msk                          /*!< Event Mask on line 50 */

+#define EXTI_EMR2_EM51_Pos         (19U)

+#define EXTI_EMR2_EM51_Msk         (0x1UL << EXTI_EMR2_EM51_Pos)               /*!< 0x00080000 */

+#define EXTI_EMR2_EM51             EXTI_EMR2_EM51_Msk                          /*!< Event Mask on line 51 */

+#define EXTI_EMR2_EM52_Pos         (20U)

+#define EXTI_EMR2_EM52_Msk         (0x1UL << EXTI_EMR2_EM52_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR2_EM52             EXTI_EMR2_EM52_Msk                          /*!< Event Mask on line 52 */

+#define EXTI_EMR2_EM53_Pos         (21U)

+#define EXTI_EMR2_EM53_Msk         (0x1UL << EXTI_EMR2_EM53_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR2_EM53             EXTI_EMR2_EM53_Msk                          /*!< Event Mask on line 53 */

+#define EXTI_EMR2_EM54_Pos         (22U)

+#define EXTI_EMR2_EM54_Msk         (0x1UL << EXTI_EMR2_EM54_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR2_EM54             EXTI_EMR2_EM54_Msk                          /*!< Event Mask on line 54 */

+#define EXTI_EMR2_EM55_Pos         (23U)

+#define EXTI_EMR2_EM55_Msk         (0x1UL << EXTI_EMR2_EM55_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR2_EM55             EXTI_EMR2_EM55_Msk                          /*!< Event Mask on line 55 */

+#define EXTI_EMR2_EM56_Pos         (24U)

+#define EXTI_EMR2_EM56_Msk         (0x1UL << EXTI_EMR2_EM56_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR2_EM56             EXTI_EMR2_EM56_Msk                          /*!< Event Mask on line 56 */

+#define EXTI_EMR2_EM57_Pos         (25U)

+#define EXTI_EMR2_EM57_Msk         (0x1UL << EXTI_EMR2_EM57_Pos)               /*!< 0x02000000 */

+#define EXTI_EMR2_EM57             EXTI_EMR2_EM57_Msk                          /*!< Event Mask on line 57 */

+#define EXTI_EMR2_EM58_Pos         (26U)

+#define EXTI_EMR2_EM58_Msk         (0x1UL << EXTI_EMR2_EM58_Pos)               /*!< 0x04000000 */

+#define EXTI_EMR2_EM58             EXTI_EMR2_EM58_Msk                          /*!< Event Mask on line 58 */

+#define EXTI_EMR2_EM59_Pos         (27U)

+#define EXTI_EMR2_EM59_Msk         (0x1UL << EXTI_EMR2_EM59_Pos)               /*!< 0x08000000 */

+#define EXTI_EMR2_EM59             EXTI_EMR2_EM59_Msk                          /*!< Event Mask on line 59 */

+#define EXTI_EMR2_EM60_Pos         (28U)

+#define EXTI_EMR2_EM60_Msk         (0x1UL << EXTI_EMR2_EM60_Pos)               /*!< 0x10000000 */

+#define EXTI_EMR2_EM60             EXTI_EMR2_EM60_Msk                          /*!< Event Mask on line 60 */

+#define EXTI_EMR2_EM61_Pos         (29U)

+#define EXTI_EMR2_EM61_Msk         (0x1UL << EXTI_EMR2_EM61_Pos)               /*!< 0x20000000 */

+#define EXTI_EMR2_EM61             EXTI_EMR2_EM61_Msk                          /*!< Event Mask on line 61 */

+#define EXTI_EMR2_EM62_Pos         (30U)

+#define EXTI_EMR2_EM62_Msk         (0x1UL << EXTI_EMR2_EM62_Pos)               /*!< 0x40000000 */

+#define EXTI_EMR2_EM62             EXTI_EMR2_EM62_Msk                          /*!< Event Mask on line 62 */

+#define EXTI_EMR2_EM63_Pos         (31U)

+#define EXTI_EMR2_EM63_Msk         (0x1UL << EXTI_EMR2_EM63_Pos)               /*!< 0x80000000 */

+#define EXTI_EMR2_EM63             EXTI_EMR2_EM63_Msk                          /*!< Event Mask on line 63 */

+

+/*******************  Bit definition for EXTI_PR2 register  ********************/

+#define EXTI_PR2_PR_Pos            (17U)

+#define EXTI_PR2_PR_Msk            (0x5UL << EXTI_PR2_PR_Pos)                  /*!< 0x000A0000 */

+#define EXTI_PR2_PR                EXTI_PR2_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR2_PR49_Pos          (17U)

+#define EXTI_PR2_PR49_Msk          (0x1UL << EXTI_PR2_PR49_Pos)                /*!< 0x00020000 */

+#define EXTI_PR2_PR49              EXTI_PR2_PR49_Msk                           /*!< Pending bit for line 49 */

+#define EXTI_PR2_PR51_Pos          (19U)

+#define EXTI_PR2_PR51_Msk          (0x1UL << EXTI_PR2_PR51_Pos)                /*!< 0x00080000 */

+#define EXTI_PR2_PR51              EXTI_PR2_PR51_Msk                           /*!< Pending bit for line 51 */

+

+/*******************  Bit definition for EXTI_IMR3 register  *******************/

+#define EXTI_IMR3_IM_Pos           (0U)

+#define EXTI_IMR3_IM_Msk           (0x00F5FFFFUL << EXTI_IMR3_IM_Pos)          /*!< 0x00F5FFFF */

+#define EXTI_IMR3_IM               EXTI_IMR3_IM_Msk                            /*!< Interrupt Mask */

+#define EXTI_IMR3_IM64_Pos         (0U)

+#define EXTI_IMR3_IM64_Msk         (0x1UL << EXTI_IMR3_IM64_Pos)               /*!< 0x00000001 */

+#define EXTI_IMR3_IM64             EXTI_IMR3_IM64_Msk                          /*!< Interrupt Mask on line 64 */

+#define EXTI_IMR3_IM65_Pos         (1U)

+#define EXTI_IMR3_IM65_Msk         (0x1UL << EXTI_IMR3_IM65_Pos)               /*!< 0x00000002 */

+#define EXTI_IMR3_IM65             EXTI_IMR3_IM65_Msk                          /*!< Interrupt Mask on line 65 */

+#define EXTI_IMR3_IM66_Pos         (2U)

+#define EXTI_IMR3_IM66_Msk         (0x1UL << EXTI_IMR3_IM66_Pos)               /*!< 0x00000004 */

+#define EXTI_IMR3_IM66             EXTI_IMR3_IM66_Msk                          /*!< Interrupt Mask on line 66 */

+#define EXTI_IMR3_IM67_Pos         (3U)

+#define EXTI_IMR3_IM67_Msk         (0x1UL << EXTI_IMR3_IM67_Pos)               /*!< 0x00000008 */

+#define EXTI_IMR3_IM67             EXTI_IMR3_IM67_Msk                          /*!< Interrupt Mask on line 67 */

+#define EXTI_IMR3_IM68_Pos         (4U)

+#define EXTI_IMR3_IM68_Msk         (0x1UL << EXTI_IMR3_IM68_Pos)               /*!< 0x00000010 */

+#define EXTI_IMR3_IM68             EXTI_IMR3_IM68_Msk                          /*!< Interrupt Mask on line 68 */

+#define EXTI_IMR3_IM69_Pos         (5U)

+#define EXTI_IMR3_IM69_Msk         (0x1UL << EXTI_IMR3_IM69_Pos)               /*!< 0x00000020 */

+#define EXTI_IMR3_IM69             EXTI_IMR3_IM69_Msk                          /*!< Interrupt Mask on line 69 */

+#define EXTI_IMR3_IM70_Pos         (6U)

+#define EXTI_IMR3_IM70_Msk         (0x1UL << EXTI_IMR3_IM70_Pos)               /*!< 0x00000040 */

+#define EXTI_IMR3_IM70             EXTI_IMR3_IM70_Msk                          /*!< Interrupt Mask on line 70 */

+#define EXTI_IMR3_IM71_Pos         (7U)

+#define EXTI_IMR3_IM71_Msk         (0x1UL << EXTI_IMR3_IM71_Pos)               /*!< 0x00000080 */

+#define EXTI_IMR3_IM71             EXTI_IMR3_IM71_Msk                          /*!< Interrupt Mask on line 71 */

+#define EXTI_IMR3_IM72_Pos         (8U)

+#define EXTI_IMR3_IM72_Msk         (0x1UL << EXTI_IMR3_IM72_Pos)               /*!< 0x00000100 */

+#define EXTI_IMR3_IM72             EXTI_IMR3_IM72_Msk                          /*!< Interrupt Mask on line 72 */

+#define EXTI_IMR3_IM73_Pos         (9U)

+#define EXTI_IMR3_IM73_Msk         (0x1UL << EXTI_IMR3_IM73_Pos)               /*!< 0x00000200 */

+#define EXTI_IMR3_IM73             EXTI_IMR3_IM73_Msk                          /*!< Interrupt Mask on line 73 */

+#define EXTI_IMR3_IM74_Pos         (10U)

+#define EXTI_IMR3_IM74_Msk         (0x1UL << EXTI_IMR3_IM74_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR3_IM74             EXTI_IMR3_IM74_Msk                          /*!< Interrupt Mask on line 74 */

+#define EXTI_IMR3_IM75_Pos         (11U)

+#define EXTI_IMR3_IM75_Msk         (0x1UL << EXTI_IMR3_IM75_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR3_IM75             EXTI_IMR3_IM75_Msk                          /*!< Interrupt Mask on line 75 */

+#define EXTI_IMR3_IM76_Pos         (12U)

+#define EXTI_IMR3_IM76_Msk         (0x1UL << EXTI_IMR3_IM76_Pos)               /*!< 0x00001000 */

+#define EXTI_IMR3_IM76             EXTI_IMR3_IM76_Msk                          /*!< Interrupt Mask on line 76 */

+#define EXTI_IMR3_IM77_Pos         (13U)

+#define EXTI_IMR3_IM77_Msk         (0x1UL << EXTI_IMR3_IM77_Pos)               /*!< 0x00002000 */

+#define EXTI_IMR3_IM77             EXTI_IMR3_IM77_Msk                          /*!< Interrupt Mask on line 77 */

+#define EXTI_IMR3_IM78_Pos         (14U)

+#define EXTI_IMR3_IM78_Msk         (0x1UL << EXTI_IMR3_IM78_Pos)               /*!< 0x00004000 */

+#define EXTI_IMR3_IM78             EXTI_IMR3_IM78_Msk                          /*!< Interrupt Mask on line 78 */

+#define EXTI_IMR3_IM79_Pos         (15U)

+#define EXTI_IMR3_IM79_Msk         (0x1UL << EXTI_IMR3_IM79_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR3_IM79             EXTI_IMR3_IM79_Msk                          /*!< Interrupt Mask on line 79 */

+#define EXTI_IMR3_IM80_Pos         (16U)

+#define EXTI_IMR3_IM80_Msk         (0x1UL << EXTI_IMR3_IM80_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR3_IM80             EXTI_IMR3_IM80_Msk                          /*!< Interrupt Mask on line 80 */

+#define EXTI_IMR3_IM82_Pos         (18U)

+#define EXTI_IMR3_IM82_Msk         (0x1UL << EXTI_IMR3_IM82_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR3_IM82             EXTI_IMR3_IM82_Msk                          /*!< Interrupt Mask on line 82 */

+#define EXTI_IMR3_IM84_Pos         (20U)

+#define EXTI_IMR3_IM84_Msk         (0x1UL << EXTI_IMR3_IM84_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR3_IM84             EXTI_IMR3_IM84_Msk                          /*!< Interrupt Mask on line 84 */

+#define EXTI_IMR3_IM85_Pos         (21U)

+#define EXTI_IMR3_IM85_Msk         (0x1UL << EXTI_IMR3_IM85_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR3_IM85             EXTI_IMR3_IM85_Msk                          /*!< Interrupt Mask on line 85 */

+#define EXTI_IMR3_IM86_Pos         (22U)

+#define EXTI_IMR3_IM86_Msk         (0x1UL << EXTI_IMR3_IM86_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR3_IM86             EXTI_IMR3_IM86_Msk                          /*!< Interrupt Mask on line 86 */

+#define EXTI_IMR3_IM87_Pos         (23U)

+#define EXTI_IMR3_IM87_Msk         (0x1UL << EXTI_IMR3_IM87_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR3_IM87             EXTI_IMR3_IM87_Msk                          /*!< Interrupt Mask on line 87 */

+

+

+/*******************  Bit definition for EXTI_EMR3 register  *******************/

+#define EXTI_EMR3_EM_Pos           (0U)

+#define EXTI_EMR3_EM_Msk           (0x00F5FFFFUL << EXTI_EMR3_EM_Pos)          /*!< 0x00F5FFFF */

+#define EXTI_EMR3_EM               EXTI_EMR3_EM_Msk                            /*!< Event Mask           */

+#define EXTI_EMR3_EM64_Pos         (0U)

+#define EXTI_EMR3_EM64_Msk         (0x1UL << EXTI_EMR3_EM64_Pos)               /*!< 0x00000001 */

+#define EXTI_EMR3_EM64             EXTI_EMR3_EM64_Msk                          /*!< Event Mask on line 64*/

+#define EXTI_EMR3_EM65_Pos         (1U)

+#define EXTI_EMR3_EM65_Msk         (0x1UL << EXTI_EMR3_EM65_Pos)               /*!< 0x00000002 */

+#define EXTI_EMR3_EM65             EXTI_EMR3_EM65_Msk                          /*!< Event Mask on line 65*/

+#define EXTI_EMR3_EM66_Pos         (2U)

+#define EXTI_EMR3_EM66_Msk         (0x1UL << EXTI_EMR3_EM66_Pos)               /*!< 0x00000004 */

+#define EXTI_EMR3_EM66             EXTI_EMR3_EM66_Msk                          /*!< Event Mask on line 66*/

+#define EXTI_EMR3_EM67_Pos         (3U)

+#define EXTI_EMR3_EM67_Msk         (0x1UL << EXTI_EMR3_EM67_Pos)               /*!< 0x00000008 */

+#define EXTI_EMR3_EM67             EXTI_EMR3_EM67_Msk                          /*!< Event Mask on line 67*/

+#define EXTI_EMR3_EM68_Pos         (4U)

+#define EXTI_EMR3_EM68_Msk         (0x1UL << EXTI_EMR3_EM68_Pos)               /*!< 0x00000010 */

+#define EXTI_EMR3_EM68             EXTI_EMR3_EM68_Msk                          /*!< Event Mask on line 68*/

+#define EXTI_EMR3_EM69_Pos         (5U)

+#define EXTI_EMR3_EM69_Msk         (0x1UL << EXTI_EMR3_EM69_Pos)               /*!< 0x00000020 */

+#define EXTI_EMR3_EM69             EXTI_EMR3_EM69_Msk                          /*!< Event Mask on line 69*/

+#define EXTI_EMR3_EM70_Pos         (6U)

+#define EXTI_EMR3_EM70_Msk         (0x1UL << EXTI_EMR3_EM70_Pos)               /*!< 0x00000040 */

+#define EXTI_EMR3_EM70             EXTI_EMR3_EM70_Msk                          /*!< Event Mask on line 70*/

+#define EXTI_EMR3_EM71_Pos         (7U)

+#define EXTI_EMR3_EM71_Msk         (0x1UL << EXTI_EMR3_EM71_Pos)               /*!< 0x00000080 */

+#define EXTI_EMR3_EM71             EXTI_EMR3_EM71_Msk                          /*!< Event Mask on line 71*/

+#define EXTI_EMR3_EM72_Pos         (8U)

+#define EXTI_EMR3_EM72_Msk         (0x1UL << EXTI_EMR3_EM72_Pos)               /*!< 0x00000100 */

+#define EXTI_EMR3_EM72             EXTI_EMR3_EM72_Msk                          /*!< Event Mask on line 72*/

+#define EXTI_EMR3_EM73_Pos         (9U)

+#define EXTI_EMR3_EM73_Msk         (0x1UL << EXTI_EMR3_EM73_Pos)               /*!< 0x00000200 */

+#define EXTI_EMR3_EM73             EXTI_EMR3_EM73_Msk                          /*!< Event Mask on line 73*/

+#define EXTI_EMR3_EM74_Pos         (10U)

+#define EXTI_EMR3_EM74_Msk         (0x1UL << EXTI_EMR3_EM74_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR3_EM74             EXTI_EMR3_EM74_Msk                          /*!< Event Mask on line 74 */

+#define EXTI_EMR3_EM75_Pos         (11U)

+#define EXTI_EMR3_EM75_Msk         (0x1UL << EXTI_EMR3_EM75_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR3_EM75             EXTI_EMR3_EM75_Msk                          /*!< Event Mask on line 75 */

+#define EXTI_EMR3_EM76_Pos         (12U)

+#define EXTI_EMR3_EM76_Msk         (0x1UL << EXTI_EMR3_EM76_Pos)               /*!< 0x00001000 */

+#define EXTI_EMR3_EM76             EXTI_EMR3_EM76_Msk                          /*!< Event Mask on line 76 */

+#define EXTI_EMR3_EM77_Pos         (13U)

+#define EXTI_EMR3_EM77_Msk         (0x1UL << EXTI_EMR3_EM77_Pos)               /*!< 0x00002000 */

+#define EXTI_EMR3_EM77             EXTI_EMR3_EM77_Msk                          /*!< Event Mask on line 77 */

+#define EXTI_EMR3_EM78_Pos         (14U)

+#define EXTI_EMR3_EM78_Msk         (0x1UL << EXTI_EMR3_EM78_Pos)               /*!< 0x00004000 */

+#define EXTI_EMR3_EM78             EXTI_EMR3_EM78_Msk                          /*!< Event Mask on line 78 */

+#define EXTI_EMR3_EM79_Pos         (15U)

+#define EXTI_EMR3_EM79_Msk         (0x1UL << EXTI_EMR3_EM79_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR3_EM79             EXTI_EMR3_EM79_Msk                          /*!< Event Mask on line 79 */

+#define EXTI_EMR3_EM80_Pos         (16U)

+#define EXTI_EMR3_EM80_Msk         (0x1UL << EXTI_EMR3_EM80_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR3_EM80             EXTI_EMR3_EM80_Msk                          /*!< Event Mask on line 80 */

+#define EXTI_EMR3_EM81_Pos         (17U)

+#define EXTI_EMR3_EM81_Msk         (0x1UL << EXTI_EMR3_EM81_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR3_EM81             EXTI_EMR3_EM81_Msk                          /*!< Event Mask on line 81 */

+#define EXTI_EMR3_EM82_Pos         (18U)

+#define EXTI_EMR3_EM82_Msk         (0x1UL << EXTI_EMR3_EM82_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR3_EM82             EXTI_EMR3_EM82_Msk                          /*!< Event Mask on line 82 */

+#define EXTI_EMR3_EM84_Pos         (20U)

+#define EXTI_EMR3_EM84_Msk         (0x1UL << EXTI_EMR3_EM84_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR3_EM84             EXTI_EMR3_EM84_Msk                          /*!< Event Mask on line 84 */

+#define EXTI_EMR3_EM85_Pos         (21U)

+#define EXTI_EMR3_EM85_Msk         (0x1UL << EXTI_EMR3_EM85_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR3_EM85             EXTI_EMR3_EM85_Msk                          /*!< Event Mask on line 85 */

+#define EXTI_EMR3_EM86_Pos         (22U)

+#define EXTI_EMR3_EM86_Msk         (0x1UL << EXTI_EMR3_EM86_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR3_EM86             EXTI_EMR3_EM86_Msk                          /*!< Event Mask on line 86 */

+#define EXTI_EMR3_EM87_Pos         (23U)

+#define EXTI_EMR3_EM87_Msk         (0x1UL << EXTI_EMR3_EM87_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR3_EM87             EXTI_EMR3_EM87_Msk                          /*!< Event Mask on line 87 */

+

+/*******************  Bit definition for EXTI_PR3 register  ********************/

+#define EXTI_PR3_PR_Pos            (18U)

+#define EXTI_PR3_PR_Msk            (0x1DUL << EXTI_PR3_PR_Pos)                 /*!< 0x00740000 */

+#define EXTI_PR3_PR                EXTI_PR3_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR3_PR82_Pos          (18U)

+#define EXTI_PR3_PR82_Msk          (0x1UL << EXTI_PR3_PR82_Pos)                /*!< 0x00040000 */

+#define EXTI_PR3_PR82              EXTI_PR3_PR82_Msk                           /*!< Pending bit for line 82 */

+#define EXTI_PR3_PR84_Pos          (20U)

+#define EXTI_PR3_PR84_Msk          (0x1UL << EXTI_PR3_PR84_Pos)                /*!< 0x00100000 */

+#define EXTI_PR3_PR84              EXTI_PR3_PR84_Msk                           /*!< Pending bit for line 84 */

+#define EXTI_PR3_PR85_Pos          (21U)

+#define EXTI_PR3_PR85_Msk          (0x1UL << EXTI_PR3_PR85_Pos)                /*!< 0x00200000 */

+#define EXTI_PR3_PR85              EXTI_PR3_PR85_Msk                           /*!< Pending bit for line 85 */

+#define EXTI_PR3_PR86_Pos          (22U)

+#define EXTI_PR3_PR86_Msk          (0x1UL << EXTI_PR3_PR86_Pos)                /*!< 0x00400000 */

+#define EXTI_PR3_PR86              EXTI_PR3_PR86_Msk                           /*!< Pending bit for line 86 */

+/******************************************************************************/

+/*                                                                            */

+/*                                    FLASH                                   */

+/*                                                                            */

+/******************************************************************************/

+/*

+* @brief FLASH Global Defines

+*/

+#define FLASH_SECTOR_TOTAL                   8U                    /* 8 sectors */

+#define FLASH_SIZE                           0x200000UL            /* 2 MB   */

+#define FLASH_BANK_SIZE                      (FLASH_SIZE >> 1)     /* 1 MB   */

+#define FLASH_SECTOR_SIZE                    0x00020000UL          /* 128 KB */

+#define FLASH_LATENCY_DEFAULT                FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */

+#define FLASH_NB_32BITWORD_IN_FLASHWORD      8U                    /* 256 bits */

+#define DUAL_BANK                                                  /* Dual-bank Flash */

+

+/*******************  Bits definition for FLASH_ACR register  **********************/

+#define FLASH_ACR_LATENCY_Pos                (0U)

+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */

+#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */

+#define FLASH_ACR_LATENCY_0WS                (0x00000000UL)

+#define FLASH_ACR_LATENCY_1WS                (0x00000001UL)

+#define FLASH_ACR_LATENCY_2WS                (0x00000002UL)

+#define FLASH_ACR_LATENCY_3WS                (0x00000003UL)

+#define FLASH_ACR_LATENCY_4WS                (0x00000004UL)

+#define FLASH_ACR_LATENCY_5WS                (0x00000005UL)

+#define FLASH_ACR_LATENCY_6WS                (0x00000006UL)

+#define FLASH_ACR_LATENCY_7WS                (0x00000007UL)

+#define FLASH_ACR_LATENCY_8WS                (0x00000008UL)

+#define FLASH_ACR_LATENCY_9WS                (0x00000009UL)

+#define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)

+#define FLASH_ACR_LATENCY_11WS               (0x0000000BUL)

+#define FLASH_ACR_LATENCY_12WS               (0x0000000CUL)

+#define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)

+#define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)

+#define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)

+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)

+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */

+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */

+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */

+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */

+

+/*******************  Bits definition for FLASH_CR register  ***********************/

+#define FLASH_CR_LOCK_Pos                    (0U)

+#define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */

+#define FLASH_CR_LOCK                        FLASH_CR_LOCK_Msk                 /*!< Configuration lock bit */

+#define FLASH_CR_PG_Pos                      (1U)

+#define FLASH_CR_PG_Msk                      (0x1UL << FLASH_CR_PG_Pos)        /*!< 0x00000002 */

+#define FLASH_CR_PG                          FLASH_CR_PG_Msk                   /*!< Internal buffer control bit */

+#define FLASH_CR_SER_Pos                     (2U)

+#define FLASH_CR_SER_Msk                     (0x1UL << FLASH_CR_SER_Pos)       /*!< 0x00000004 */

+#define FLASH_CR_SER                         FLASH_CR_SER_Msk                  /*!< Sector erase request */

+#define FLASH_CR_BER_Pos                     (3U)

+#define FLASH_CR_BER_Msk                     (0x1UL << FLASH_CR_BER_Pos)       /*!< 0x00000008 */

+#define FLASH_CR_BER                         FLASH_CR_BER_Msk                  /*!< Bank erase request */

+#define FLASH_CR_PSIZE_Pos                   (4U)

+#define FLASH_CR_PSIZE_Msk                   (0x3UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000030 */

+#define FLASH_CR_PSIZE                       FLASH_CR_PSIZE_Msk                /*!< Program size */

+#define FLASH_CR_PSIZE_0                     (0x1UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000010 */

+#define FLASH_CR_PSIZE_1                     (0x2UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000020 */

+#define FLASH_CR_FW_Pos                      (6U)

+#define FLASH_CR_FW_Msk                      (0x1UL << FLASH_CR_FW_Pos)        /*!< 0x00000040 */

+#define FLASH_CR_FW                          FLASH_CR_FW_Msk                   /*!< Write forcing control bit */

+#define FLASH_CR_START_Pos                   (7U)

+#define FLASH_CR_START_Msk                   (0x1UL << FLASH_CR_START_Pos)     /*!< 0x00000080 */

+#define FLASH_CR_START                       FLASH_CR_START_Msk                /*!< Erase start control bit */

+#define FLASH_CR_SNB_Pos                     (8U)

+#define FLASH_CR_SNB_Msk                     (0x7UL << FLASH_CR_SNB_Pos)       /*!< 0x00000700 */

+#define FLASH_CR_SNB                         FLASH_CR_SNB_Msk                  /*!< Sector erase selection number */

+#define FLASH_CR_SNB_0                       (0x1UL << FLASH_CR_SNB_Pos)       /*!< 0x00000100 */

+#define FLASH_CR_SNB_1                       (0x2UL << FLASH_CR_SNB_Pos)       /*!< 0x00000200 */

+#define FLASH_CR_SNB_2                       (0x4UL << FLASH_CR_SNB_Pos)       /*!< 0x00000400 */

+#define FLASH_CR_CRC_EN_Pos                  (15U)

+#define FLASH_CR_CRC_EN_Msk                  (0x1UL << FLASH_CR_CRC_EN_Pos)    /*!< 0x00008000 */

+#define FLASH_CR_CRC_EN                      FLASH_CR_CRC_EN_Msk               /*!< CRC control bit */

+#define FLASH_CR_EOPIE_Pos                   (16U)

+#define FLASH_CR_EOPIE_Msk                   (0x1UL << FLASH_CR_EOPIE_Pos)     /*!< 0x00010000 */

+#define FLASH_CR_EOPIE                       FLASH_CR_EOPIE_Msk                /*!< End-of-program interrupt control bit */

+#define FLASH_CR_WRPERRIE_Pos                (17U)

+#define FLASH_CR_WRPERRIE_Msk                (0x1UL << FLASH_CR_WRPERRIE_Pos)  /*!< 0x00020000 */

+#define FLASH_CR_WRPERRIE                    FLASH_CR_WRPERRIE_Msk             /*!< Write protection error interrupt enable bit */

+#define FLASH_CR_PGSERRIE_Pos                (18U)

+#define FLASH_CR_PGSERRIE_Msk                (0x1UL << FLASH_CR_PGSERRIE_Pos)  /*!< 0x00040000 */

+#define FLASH_CR_PGSERRIE                    FLASH_CR_PGSERRIE_Msk             /*!< Programming sequence error interrupt enable bit */

+#define FLASH_CR_STRBERRIE_Pos               (19U)

+#define FLASH_CR_STRBERRIE_Msk               (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */

+#define FLASH_CR_STRBERRIE                   FLASH_CR_STRBERRIE_Msk            /*!< Strobe error interrupt enable bit */

+#define FLASH_CR_INCERRIE_Pos                (21U)

+#define FLASH_CR_INCERRIE_Msk                (0x1UL << FLASH_CR_INCERRIE_Pos)  /*!< 0x00200000 */

+#define FLASH_CR_INCERRIE                    FLASH_CR_INCERRIE_Msk             /*!< Inconsistency error interrupt enable bit */

+#define FLASH_CR_OPERRIE_Pos                 (22U)

+#define FLASH_CR_OPERRIE_Msk                 (0x1UL << FLASH_CR_OPERRIE_Pos)   /*!< 0x00400000 */

+#define FLASH_CR_OPERRIE                     FLASH_CR_OPERRIE_Msk              /*!< Write/erase error interrupt enable bit */

+#define FLASH_CR_RDPERRIE_Pos                (23U)

+#define FLASH_CR_RDPERRIE_Msk                (0x1UL << FLASH_CR_RDPERRIE_Pos)  /*!< 0x00800000 */

+#define FLASH_CR_RDPERRIE                    FLASH_CR_RDPERRIE_Msk             /*!< Read protection error interrupt enable bit */

+#define FLASH_CR_RDSERRIE_Pos                (24U)

+#define FLASH_CR_RDSERRIE_Msk                (0x1UL << FLASH_CR_RDSERRIE_Pos)  /*!< 0x01000000 */

+#define FLASH_CR_RDSERRIE                    FLASH_CR_RDSERRIE_Msk             /*!< Secure error interrupt enable bit */

+#define FLASH_CR_SNECCERRIE_Pos              (25U)

+#define FLASH_CR_SNECCERRIE_Msk              (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */

+#define FLASH_CR_SNECCERRIE                  FLASH_CR_SNECCERRIE_Msk            /*!< ECC single correction error interrupt enable bit */

+#define FLASH_CR_DBECCERRIE_Pos              (26U)

+#define FLASH_CR_DBECCERRIE_Msk              (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */

+#define FLASH_CR_DBECCERRIE                  FLASH_CR_DBECCERRIE_Msk            /*!< ECC double detection error interrupt enable bit */

+#define FLASH_CR_CRCENDIE_Pos                (27U)

+#define FLASH_CR_CRCENDIE_Msk                (0x1UL << FLASH_CR_CRCENDIE_Pos)  /*!< 0x08000000 */

+#define FLASH_CR_CRCENDIE                    FLASH_CR_CRCENDIE_Msk             /*!< CRC end of calculation interrupt enable bit */

+#define FLASH_CR_CRCRDERRIE_Pos              (28U)

+#define FLASH_CR_CRCRDERRIE_Msk              (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */

+#define FLASH_CR_CRCRDERRIE                  FLASH_CR_CRCRDERRIE_Msk            /*!< CRC read error interrupt enable bit */

+

+/*******************  Bits definition for FLASH_SR register  ***********************/

+#define FLASH_SR_BSY_Pos                     (0U)

+#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)       /*!< 0x00000001 */

+#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy flag */

+#define FLASH_SR_WBNE_Pos                    (1U)

+#define FLASH_SR_WBNE_Msk                    (0x1UL << FLASH_SR_WBNE_Pos)      /*!< 0x00000002 */

+#define FLASH_SR_WBNE                        FLASH_SR_WBNE_Msk                 /*!< Write buffer not empty flag */

+#define FLASH_SR_QW_Pos                      (2U)

+#define FLASH_SR_QW_Msk                      (0x1UL << FLASH_SR_QW_Pos)        /*!< 0x00000004 */

+#define FLASH_SR_QW                          FLASH_SR_QW_Msk                   /*!< Wait queue flag */

+#define FLASH_SR_CRC_BUSY_Pos                (3U)

+#define FLASH_SR_CRC_BUSY_Msk                (0x1UL << FLASH_SR_CRC_BUSY_Pos)  /*!< 0x00000008 */

+#define FLASH_SR_CRC_BUSY                    FLASH_SR_CRC_BUSY_Msk             /*!< CRC busy flag */

+#define FLASH_SR_EOP_Pos                     (16U)

+#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)       /*!< 0x00010000 */

+#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End-of-program flag */

+#define FLASH_SR_WRPERR_Pos                  (17U)

+#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)    /*!< 0x00020000 */

+#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protection error flag */

+#define FLASH_SR_PGSERR_Pos                  (18U)

+#define FLASH_SR_PGSERR_Msk                  (0x1UL << FLASH_SR_PGSERR_Pos)    /*!< 0x00040000 */

+#define FLASH_SR_PGSERR                      FLASH_SR_PGSERR_Msk               /*!< Programming sequence error flag */

+#define FLASH_SR_STRBERR_Pos                 (19U)

+#define FLASH_SR_STRBERR_Msk                 (0x1UL << FLASH_SR_STRBERR_Pos)   /*!< 0x00080000 */

+#define FLASH_SR_STRBERR                     FLASH_SR_STRBERR_Msk              /*!< Strobe error flag */

+#define FLASH_SR_INCERR_Pos                  (21U)

+#define FLASH_SR_INCERR_Msk                  (0x1UL << FLASH_SR_INCERR_Pos)    /*!< 0x00200000 */

+#define FLASH_SR_INCERR                      FLASH_SR_INCERR_Msk               /*!< Inconsistency error flag */

+#define FLASH_SR_OPERR_Pos                   (22U)

+#define FLASH_SR_OPERR_Msk                   (0x1UL << FLASH_SR_OPERR_Pos)     /*!< 0x00400000 */

+#define FLASH_SR_OPERR                       FLASH_SR_OPERR_Msk                /*!< Write/erase error flag */

+#define FLASH_SR_RDPERR_Pos                  (23U)

+#define FLASH_SR_RDPERR_Msk                  (0x1UL << FLASH_SR_RDPERR_Pos)    /*!< 0x00800000 */

+#define FLASH_SR_RDPERR                      FLASH_SR_RDPERR_Msk               /*!< Read protection error flag */

+#define FLASH_SR_RDSERR_Pos                  (24U)

+#define FLASH_SR_RDSERR_Msk                  (0x1UL << FLASH_SR_RDSERR_Pos)    /*!< 0x01000000 */

+#define FLASH_SR_RDSERR                      FLASH_SR_RDSERR_Msk               /*!< Secure error flag */

+#define FLASH_SR_SNECCERR_Pos                (25U)

+#define FLASH_SR_SNECCERR_Msk                (0x1UL << FLASH_SR_SNECCERR_Pos)  /*!< 0x02000000 */

+#define FLASH_SR_SNECCERR                    FLASH_SR_SNECCERR_Msk             /*!< Single correction error flag */

+#define FLASH_SR_DBECCERR_Pos                (26U)

+#define FLASH_SR_DBECCERR_Msk                (0x1UL << FLASH_SR_DBECCERR_Pos)  /*!< 0x04000000 */

+#define FLASH_SR_DBECCERR                    FLASH_SR_DBECCERR_Msk             /*!< ECC double detection error flag */

+#define FLASH_SR_CRCEND_Pos                  (27U)

+#define FLASH_SR_CRCEND_Msk                  (0x1UL << FLASH_SR_CRCEND_Pos)    /*!< 0x08000000 */

+#define FLASH_SR_CRCEND                      FLASH_SR_CRCEND_Msk               /*!< CRC end of calculation flag */

+#define FLASH_SR_CRCRDERR_Pos                (28U)

+#define FLASH_SR_CRCRDERR_Msk                (0x1UL << FLASH_SR_CRCRDERR_Pos)  /*!< 0x10000000 */

+#define FLASH_SR_CRCRDERR                    FLASH_SR_CRCRDERR_Msk             /*!< CRC read error flag */

+

+/*******************  Bits definition for FLASH_CCR register  *******************/

+#define FLASH_CCR_CLR_EOP_Pos                (16U)

+#define FLASH_CCR_CLR_EOP_Msk                (0x1UL << FLASH_CCR_CLR_EOP_Pos)  /*!< 0x00010000 */

+#define FLASH_CCR_CLR_EOP                    FLASH_CCR_CLR_EOP_Msk             /*!< EOP flag clear bit */

+#define FLASH_CCR_CLR_WRPERR_Pos             (17U)

+#define FLASH_CCR_CLR_WRPERR_Msk             (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */

+#define FLASH_CCR_CLR_WRPERR                 FLASH_CCR_CLR_WRPERR_Msk            /*!< WRPERR flag clear bit */

+#define FLASH_CCR_CLR_PGSERR_Pos             (18U)

+#define FLASH_CCR_CLR_PGSERR_Msk             (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */

+#define FLASH_CCR_CLR_PGSERR                 FLASH_CCR_CLR_PGSERR_Msk            /*!< PGSERR flag clear bit */

+#define FLASH_CCR_CLR_STRBERR_Pos            (19U)

+#define FLASH_CCR_CLR_STRBERR_Msk            (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */

+#define FLASH_CCR_CLR_STRBERR                FLASH_CCR_CLR_STRBERR_Msk            /*!< STRBERR flag clear bit */

+#define FLASH_CCR_CLR_INCERR_Pos             (21U)

+#define FLASH_CCR_CLR_INCERR_Msk             (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */

+#define FLASH_CCR_CLR_INCERR                 FLASH_CCR_CLR_INCERR_Msk            /*!< INCERR flag clear bit */

+#define FLASH_CCR_CLR_OPERR_Pos              (22U)

+#define FLASH_CCR_CLR_OPERR_Msk              (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */

+#define FLASH_CCR_CLR_OPERR                  FLASH_CCR_CLR_OPERR_Msk            /*!< OPERR flag clear bit */

+#define FLASH_CCR_CLR_RDPERR_Pos             (23U)

+#define FLASH_CCR_CLR_RDPERR_Msk             (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */

+#define FLASH_CCR_CLR_RDPERR                 FLASH_CCR_CLR_RDPERR_Msk            /*!< RDPERR flag clear bit */

+#define FLASH_CCR_CLR_RDSERR_Pos             (24U)

+#define FLASH_CCR_CLR_RDSERR_Msk             (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */

+#define FLASH_CCR_CLR_RDSERR                 FLASH_CCR_CLR_RDSERR_Msk            /*!< RDSERR flag clear bit */

+#define FLASH_CCR_CLR_SNECCERR_Pos           (25U)

+#define FLASH_CCR_CLR_SNECCERR_Msk           (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */

+#define FLASH_CCR_CLR_SNECCERR               FLASH_CCR_CLR_SNECCERR_Msk            /*!< SNECCERR flag clear bit */

+#define FLASH_CCR_CLR_DBECCERR_Pos           (26U)

+#define FLASH_CCR_CLR_DBECCERR_Msk           (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */

+#define FLASH_CCR_CLR_DBECCERR               FLASH_CCR_CLR_DBECCERR_Msk            /*!< DBECCERR flag clear bit */

+#define FLASH_CCR_CLR_CRCEND_Pos             (27U)

+#define FLASH_CCR_CLR_CRCEND_Msk             (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */

+#define FLASH_CCR_CLR_CRCEND                 FLASH_CCR_CLR_CRCEND_Msk            /*!< CRCEND flag clear bit */

+#define FLASH_CCR_CLR_CRCRDERR_Pos           (28U)

+#define FLASH_CCR_CLR_CRCRDERR_Msk           (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */

+#define FLASH_CCR_CLR_CRCRDERR               FLASH_CCR_CLR_CRCRDERR_Msk            /*!< CRCRDERR flag clear bit */

+

+/*******************  Bits definition for FLASH_OPTCR register  *******************/

+#define FLASH_OPTCR_OPTLOCK_Pos              (0U)

+#define FLASH_OPTCR_OPTLOCK_Msk              (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)  /*!< 0x00000001 */

+#define FLASH_OPTCR_OPTLOCK                  FLASH_OPTCR_OPTLOCK_Msk             /*!< FLASH_OPTCR lock option configuration bit */

+#define FLASH_OPTCR_OPTSTART_Pos             (1U)

+#define FLASH_OPTCR_OPTSTART_Msk             (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */

+#define FLASH_OPTCR_OPTSTART                 FLASH_OPTCR_OPTSTART_Msk            /*!< Option byte start change option configuration bit */

+#define FLASH_OPTCR_MER_Pos                  (4U)

+#define FLASH_OPTCR_MER_Msk                  (0x1UL << FLASH_OPTCR_MER_Pos)      /*!< 0x00000010 */

+#define FLASH_OPTCR_MER                      FLASH_OPTCR_MER_Msk                 /*!< Mass erase request */

+#define FLASH_OPTCR_OPTCHANGEERRIE_Pos       (30U)

+#define FLASH_OPTCR_OPTCHANGEERRIE_Msk       (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */

+#define FLASH_OPTCR_OPTCHANGEERRIE           FLASH_OPTCR_OPTCHANGEERRIE_Msk            /*!< Option byte change error interrupt enable bit */

+#define FLASH_OPTCR_SWAP_BANK_Pos            (31U)

+#define FLASH_OPTCR_SWAP_BANK_Msk            (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */

+#define FLASH_OPTCR_SWAP_BANK                FLASH_OPTCR_SWAP_BANK_Msk            /*!< Bank swapping option configuration bit */

+

+/*******************  Bits definition for FLASH_OPTSR register  ***************/

+#define FLASH_OPTSR_OPT_BUSY_Pos             (0U)

+#define FLASH_OPTSR_OPT_BUSY_Msk             (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */

+#define FLASH_OPTSR_OPT_BUSY                 FLASH_OPTSR_OPT_BUSY_Msk            /*!< Option byte change ongoing flag */

+#define FLASH_OPTSR_BOR_LEV_Pos              (2U)

+#define FLASH_OPTSR_BOR_LEV_Msk              (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */

+#define FLASH_OPTSR_BOR_LEV                  FLASH_OPTSR_BOR_LEV_Msk            /*!< Brownout level option status bit */

+#define FLASH_OPTSR_BOR_LEV_0                (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */

+#define FLASH_OPTSR_BOR_LEV_1                (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */

+#define FLASH_OPTSR_IWDG1_SW_Pos             (4U)

+#define FLASH_OPTSR_IWDG1_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */

+#define FLASH_OPTSR_IWDG1_SW                 FLASH_OPTSR_IWDG1_SW_Msk            /*!< IWDG1 control mode option status bit */

+#define FLASH_OPTSR_NRST_STOP_D1_Pos         (6U)

+#define FLASH_OPTSR_NRST_STOP_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */

+#define FLASH_OPTSR_NRST_STOP_D1             FLASH_OPTSR_NRST_STOP_D1_Msk            /*!< D1 domain DStop entry reset option status bit */

+#define FLASH_OPTSR_NRST_STBY_D1_Pos         (7U)

+#define FLASH_OPTSR_NRST_STBY_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */

+#define FLASH_OPTSR_NRST_STBY_D1             FLASH_OPTSR_NRST_STBY_D1_Msk            /*!< D1 domain DStandby entry reset option status bit */

+#define FLASH_OPTSR_RDP_Pos                  (8U)

+#define FLASH_OPTSR_RDP_Msk                  (0xFFUL << FLASH_OPTSR_RDP_Pos)   /*!< 0x0000FF00 */

+#define FLASH_OPTSR_RDP                      FLASH_OPTSR_RDP_Msk               /*!< Readout protection level option status byte */

+#define FLASH_OPTSR_FZ_IWDG_STOP_Pos         (17U)

+#define FLASH_OPTSR_FZ_IWDG_STOP_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */

+#define FLASH_OPTSR_FZ_IWDG_STOP             FLASH_OPTSR_FZ_IWDG_STOP_Msk            /*!< IWDG Stop mode freeze option status bit */

+#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos         (18U)

+#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */

+#define FLASH_OPTSR_FZ_IWDG_SDBY             FLASH_OPTSR_FZ_IWDG_SDBY_Msk            /*!< IWDG Standby mode freeze option status bit */

+#define FLASH_OPTSR_ST_RAM_SIZE_Pos          (19U)

+#define FLASH_OPTSR_ST_RAM_SIZE_Msk          (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */

+#define FLASH_OPTSR_ST_RAM_SIZE              FLASH_OPTSR_ST_RAM_SIZE_Msk            /*!< ST RAM size option status */

+#define FLASH_OPTSR_ST_RAM_SIZE_0            (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */

+#define FLASH_OPTSR_ST_RAM_SIZE_1            (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */

+#define FLASH_OPTSR_SECURITY_Pos             (21U)

+#define FLASH_OPTSR_SECURITY_Msk             (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */

+#define FLASH_OPTSR_SECURITY                 FLASH_OPTSR_SECURITY_Msk            /*!< Security enable option status bit */

+#define FLASH_OPTSR_IO_HSLV_Pos              (29U)

+#define FLASH_OPTSR_IO_HSLV_Msk              (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */

+#define FLASH_OPTSR_IO_HSLV                  FLASH_OPTSR_IO_HSLV_Msk            /*!< I/O high-speed at low-voltage status bit */

+#define FLASH_OPTSR_OPTCHANGEERR_Pos         (30U)

+#define FLASH_OPTSR_OPTCHANGEERR_Msk         (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */

+#define FLASH_OPTSR_OPTCHANGEERR             FLASH_OPTSR_OPTCHANGEERR_Msk            /*!< Option byte change error flag */

+#define FLASH_OPTSR_SWAP_BANK_OPT_Pos        (31U)

+#define FLASH_OPTSR_SWAP_BANK_OPT_Msk        (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */

+#define FLASH_OPTSR_SWAP_BANK_OPT            FLASH_OPTSR_SWAP_BANK_OPT_Msk            /*!< Bank swapping option status bit */

+

+/*******************  Bits definition for FLASH_OPTCCR register  *******************/

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos    (30U)

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk    (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR        FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk            /*!< OPTCHANGEERR reset bit */

+

+/*******************  Bits definition for FLASH_PRAR register  *********************/

+#define FLASH_PRAR_PROT_AREA_START_Pos       (0U)

+#define FLASH_PRAR_PROT_AREA_START_Msk       (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */

+#define FLASH_PRAR_PROT_AREA_START           FLASH_PRAR_PROT_AREA_START_Msk              /*!< PCROP area start status bits */

+#define FLASH_PRAR_PROT_AREA_END_Pos         (16U)

+#define FLASH_PRAR_PROT_AREA_END_Msk         (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */

+#define FLASH_PRAR_PROT_AREA_END             FLASH_PRAR_PROT_AREA_END_Msk              /*!< PCROP area end status bits */

+#define FLASH_PRAR_DMEP_Pos                  (31U)

+#define FLASH_PRAR_DMEP_Msk                  (0x1UL << FLASH_PRAR_DMEP_Pos)    /*!< 0x80000000 */

+#define FLASH_PRAR_DMEP                      FLASH_PRAR_DMEP_Msk               /*!< PCROP protected erase enable option status bit */

+

+/*******************  Bits definition for FLASH_SCAR register  *********************/

+#define FLASH_SCAR_SEC_AREA_START_Pos        (0U)

+#define FLASH_SCAR_SEC_AREA_START_Msk        (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */

+#define FLASH_SCAR_SEC_AREA_START            FLASH_SCAR_SEC_AREA_START_Msk              /*!< Secure-only area start status bits */

+#define FLASH_SCAR_SEC_AREA_END_Pos          (16U)

+#define FLASH_SCAR_SEC_AREA_END_Msk          (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */

+#define FLASH_SCAR_SEC_AREA_END              FLASH_SCAR_SEC_AREA_END_Msk              /*!< Secure-only area end status bits */

+#define FLASH_SCAR_DMES_Pos                  (31U)

+#define FLASH_SCAR_DMES_Msk                  (0x1UL << FLASH_SCAR_DMES_Pos)    /*!< 0x80000000 */

+#define FLASH_SCAR_DMES                      FLASH_SCAR_DMES_Msk               /*!< Secure access protected erase enable option status bit */

+

+/*******************  Bits definition for FLASH_WPSN register  *********************/

+#define FLASH_WPSN_WRPSN_Pos                 (0U)

+#define FLASH_WPSN_WRPSN_Msk                 (0xFFUL << FLASH_WPSN_WRPSN_Pos)  /*!< 0x000000FF */

+#define FLASH_WPSN_WRPSN                     FLASH_WPSN_WRPSN_Msk              /*!< Sector write protection option status byte */

+

+/*******************  Bits definition for FLASH_BOOT_CUR register  ****************/

+#define FLASH_BOOT_ADD0_Pos                  (0U)

+#define FLASH_BOOT_ADD0_Msk                  (0xFFFFUL << FLASH_BOOT_ADD0_Pos) /*!< 0x0000FFFF */

+#define FLASH_BOOT_ADD0                      FLASH_BOOT_ADD0_Msk               /*!< Arm Cortex-M7 boot address 0 */

+#define FLASH_BOOT_ADD1_Pos                  (16U)

+#define FLASH_BOOT_ADD1_Msk                  (0xFFFFUL << FLASH_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */

+#define FLASH_BOOT_ADD1                      FLASH_BOOT_ADD1_Msk               /*!< Arm Cortex-M7 boot address 1 */

+

+

+/*******************  Bits definition for FLASH_CRCCR register  ********************/

+#define FLASH_CRCCR_CRC_SECT_Pos             (0U)

+#define FLASH_CRCCR_CRC_SECT_Msk             (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */

+#define FLASH_CRCCR_CRC_SECT                 FLASH_CRCCR_CRC_SECT_Msk            /*!< CRC sector number */

+#define FLASH_CRCCR_CRC_BY_SECT_Pos          (8U)

+#define FLASH_CRCCR_CRC_BY_SECT_Msk          (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */

+#define FLASH_CRCCR_CRC_BY_SECT              FLASH_CRCCR_CRC_BY_SECT_Msk            /*!< CRC sector mode select bit */

+#define FLASH_CRCCR_ADD_SECT_Pos             (9U)

+#define FLASH_CRCCR_ADD_SECT_Msk             (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */

+#define FLASH_CRCCR_ADD_SECT                 FLASH_CRCCR_ADD_SECT_Msk            /*!< CRC sector select bit */

+#define FLASH_CRCCR_CLEAN_SECT_Pos           (10U)

+#define FLASH_CRCCR_CLEAN_SECT_Msk           (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */

+#define FLASH_CRCCR_CLEAN_SECT               FLASH_CRCCR_CLEAN_SECT_Msk            /*!< CRC sector list clear bit */

+#define FLASH_CRCCR_START_CRC_Pos            (16U)

+#define FLASH_CRCCR_START_CRC_Msk            (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */

+#define FLASH_CRCCR_START_CRC                FLASH_CRCCR_START_CRC_Msk            /*!< CRC start bit */

+#define FLASH_CRCCR_CLEAN_CRC_Pos            (17U)

+#define FLASH_CRCCR_CLEAN_CRC_Msk            (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */

+#define FLASH_CRCCR_CLEAN_CRC                FLASH_CRCCR_CLEAN_CRC_Msk            /*!< CRC clear bit */

+#define FLASH_CRCCR_CRC_BURST_Pos            (20U)

+#define FLASH_CRCCR_CRC_BURST_Msk            (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */

+#define FLASH_CRCCR_CRC_BURST                FLASH_CRCCR_CRC_BURST_Msk            /*!< CRC burst size */

+#define FLASH_CRCCR_CRC_BURST_0              (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */

+#define FLASH_CRCCR_CRC_BURST_1              (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */

+#define FLASH_CRCCR_ALL_BANK_Pos             (22U)

+#define FLASH_CRCCR_ALL_BANK_Msk             (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */

+#define FLASH_CRCCR_ALL_BANK                 FLASH_CRCCR_ALL_BANK_Msk            /*!< CRC select bit */

+

+/*******************  Bits definition for FLASH_CRCSADD register  ****************/

+#define FLASH_CRCSADD_CRC_START_ADDR_Pos     (0U)

+#define FLASH_CRCSADD_CRC_START_ADDR_Msk     (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCSADD_CRC_START_ADDR         FLASH_CRCSADD_CRC_START_ADDR_Msk                   /*!< CRC start address */

+

+/*******************  Bits definition for FLASH_CRCEADD register  ****************/

+#define FLASH_CRCEADD_CRC_END_ADDR_Pos       (0U)

+#define FLASH_CRCEADD_CRC_END_ADDR_Msk       (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCEADD_CRC_END_ADDR           FLASH_CRCEADD_CRC_END_ADDR_Msk                   /*!< CRC end address */

+

+/*******************  Bits definition for FLASH_CRCDATA register  ***************/

+#define FLASH_CRCDATA_CRC_DATA_Pos           (0U)

+#define FLASH_CRCDATA_CRC_DATA_Msk           (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCDATA_CRC_DATA               FLASH_CRCDATA_CRC_DATA_Msk                   /*!< CRC result */

+

+/*******************  Bits definition for FLASH_ECC_FA register  *******************/

+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos       (0U)

+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk       (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */

+#define FLASH_ECC_FA_FAIL_ECC_ADDR           FLASH_ECC_FA_FAIL_ECC_ADDR_Msk               /*!< ECC error address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          Flexible Memory Controller                        */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for FMC_BCR1 register  *******************/

+#define FMC_BCR1_CCLKEN_Pos        (20U)

+#define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */

+#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continous clock enable     */

+#define FMC_BCR1_WFDIS_Pos         (21U)

+#define FMC_BCR1_WFDIS_Msk         (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */

+#define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */

+

+#define FMC_BCR1_BMAP_Pos          (24U)

+#define FMC_BCR1_BMAP_Msk          (0x3UL << FMC_BCR1_BMAP_Pos)                /*!< 0x03000000 */

+#define FMC_BCR1_BMAP              FMC_BCR1_BMAP_Msk                           /*!<BMAP[1:0] FMC bank mapping */

+#define FMC_BCR1_BMAP_0            (0x1UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x01000000 */

+#define FMC_BCR1_BMAP_1            (0x2UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x02000000 */

+

+#define FMC_BCR1_FMCEN_Pos         (31U)

+#define FMC_BCR1_FMCEN_Msk         (0x1UL << FMC_BCR1_FMCEN_Pos)               /*!< 0x80000000 */

+#define FMC_BCR1_FMCEN             FMC_BCR1_FMCEN_Msk                          /*!<FMC controller Enable */

+/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/

+#define FMC_BCRx_MBKEN_Pos         (0U)

+#define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */

+#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */

+#define FMC_BCRx_MUXEN_Pos         (1U)

+#define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */

+#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */

+

+#define FMC_BCRx_MTYP_Pos          (2U)

+#define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */

+#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */

+#define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000004 */

+#define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000008 */

+

+#define FMC_BCRx_MWID_Pos          (4U)

+#define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */

+#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */

+#define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000010 */

+#define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000020 */

+

+#define FMC_BCRx_FACCEN_Pos        (6U)

+#define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */

+#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */

+#define FMC_BCRx_BURSTEN_Pos       (8U)

+#define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */

+#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */

+#define FMC_BCRx_WAITPOL_Pos       (9U)

+#define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */

+#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */

+#define FMC_BCRx_WAITCFG_Pos       (11U)

+#define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */

+#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */

+#define FMC_BCRx_WREN_Pos          (12U)

+#define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */

+#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */

+#define FMC_BCRx_WAITEN_Pos        (13U)

+#define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */

+#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */

+#define FMC_BCRx_EXTMOD_Pos        (14U)

+#define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */

+#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */

+#define FMC_BCRx_ASYNCWAIT_Pos     (15U)

+#define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */

+#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */

+

+#define FMC_BCRx_CPSIZE_Pos        (16U)

+#define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */

+#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<PSIZE[2:0] bits CRAM Page Size */

+#define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00010000 */

+#define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00020000 */

+#define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00040000 */

+

+#define FMC_BCRx_CBURSTRW_Pos      (19U)

+#define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */

+#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */

+

+/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/

+#define FMC_BTRx_ADDSET_Pos        (0U)

+#define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */

+#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */

+#define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000001 */

+#define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000002 */

+#define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000004 */

+#define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000008 */

+

+#define FMC_BTRx_ADDHLD_Pos        (4U)

+#define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */

+#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */

+#define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000010 */

+#define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000020 */

+#define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000040 */

+#define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000080 */

+

+#define FMC_BTRx_DATAST_Pos        (8U)

+#define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */

+#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */

+#define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000100 */

+#define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000200 */

+#define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000400 */

+#define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000800 */

+#define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00001000 */

+#define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00002000 */

+#define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00004000 */

+#define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00008000 */

+

+#define FMC_BTRx_BUSTURN_Pos       (16U)

+#define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */

+#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */

+#define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00010000 */

+#define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00020000 */

+#define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00040000 */

+#define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00080000 */

+

+#define FMC_BTRx_CLKDIV_Pos        (20U)

+#define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */

+#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */

+#define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00100000 */

+#define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00200000 */

+#define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00400000 */

+#define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00800000 */

+

+#define FMC_BTRx_DATLAT_Pos        (24U)

+#define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */

+#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */

+#define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x01000000 */

+#define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x02000000 */

+#define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x04000000 */

+#define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x08000000 */

+

+#define FMC_BTRx_ACCMOD_Pos        (28U)

+#define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */

+#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */

+#define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x10000000 */

+#define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x20000000 */

+

+/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/

+#define FMC_BWTRx_ADDSET_Pos       (0U)

+#define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */

+#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */

+#define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000001 */

+#define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000002 */

+#define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000004 */

+#define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000008 */

+

+#define FMC_BWTRx_ADDHLD_Pos       (4U)

+#define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */

+#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */

+#define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000010 */

+#define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000020 */

+#define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000040 */

+#define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000080 */

+

+#define FMC_BWTRx_DATAST_Pos       (8U)

+#define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */

+#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */

+#define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000100 */

+#define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000200 */

+#define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000400 */

+#define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000800 */

+#define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00001000 */

+#define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00002000 */

+#define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00004000 */

+#define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00008000 */

+

+#define FMC_BWTRx_BUSTURN_Pos      (16U)

+#define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */

+#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */

+#define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00010000 */

+#define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00020000 */

+#define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00040000 */

+#define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00080000 */

+

+#define FMC_BWTRx_ACCMOD_Pos       (28U)

+#define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */

+#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */

+#define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x10000000 */

+#define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x20000000 */

+

+/******************  Bit definition for FMC_PCR register  *******************/

+#define FMC_PCR_PWAITEN_Pos        (1U)

+#define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */

+#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */

+#define FMC_PCR_PBKEN_Pos          (2U)

+#define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */

+#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */

+

+#define FMC_PCR_PWID_Pos           (4U)

+#define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */

+#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */

+#define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */

+#define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */

+

+#define FMC_PCR_ECCEN_Pos          (6U)

+#define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */

+#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */

+

+#define FMC_PCR_TCLR_Pos           (9U)

+#define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */

+#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */

+#define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */

+#define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */

+#define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */

+#define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */

+

+#define FMC_PCR_TAR_Pos            (13U)

+#define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */

+#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */

+#define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */

+#define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */

+#define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */

+#define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */

+

+#define FMC_PCR_ECCPS_Pos          (17U)

+#define FMC_PCR_ECCPS_Msk          (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */

+#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */

+#define FMC_PCR_ECCPS_0            (0x1UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */

+#define FMC_PCR_ECCPS_1            (0x2UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */

+#define FMC_PCR_ECCPS_2            (0x4UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */

+

+/*******************  Bit definition for FMC_SR register  *******************/

+#define FMC_SR_IRS_Pos             (0U)

+#define FMC_SR_IRS_Msk             (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */

+#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */

+#define FMC_SR_ILS_Pos             (1U)

+#define FMC_SR_ILS_Msk             (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */

+#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */

+#define FMC_SR_IFS_Pos             (2U)

+#define FMC_SR_IFS_Msk             (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */

+#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */

+#define FMC_SR_IREN_Pos            (3U)

+#define FMC_SR_IREN_Msk            (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */

+#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */

+#define FMC_SR_ILEN_Pos            (4U)

+#define FMC_SR_ILEN_Msk            (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */

+#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */

+#define FMC_SR_IFEN_Pos            (5U)

+#define FMC_SR_IFEN_Msk            (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */

+#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */

+#define FMC_SR_FEMPT_Pos           (6U)

+#define FMC_SR_FEMPT_Msk           (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */

+#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */

+

+/******************  Bit definition for FMC_PMEM register  ******************/

+#define FMC_PMEM_MEMSET_Pos       (0U)

+#define FMC_PMEM_MEMSET_Msk       (0xFFUL << FMC_PMEM_MEMSET_Pos)            /*!< 0x000000FF */

+#define FMC_PMEM_MEMSET           FMC_PMEM_MEMSET_Msk                        /*!<MEMSET[7:0] bits (Common memory setup time) */

+#define FMC_PMEM_MEMSET_0         (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */

+#define FMC_PMEM_MEMSET_1         (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */

+#define FMC_PMEM_MEMSET_2         (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */

+#define FMC_PMEM_MEMSET_3         (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */

+#define FMC_PMEM_MEMSET_4         (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */

+#define FMC_PMEM_MEMSET_5         (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */

+#define FMC_PMEM_MEMSET_6         (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */

+#define FMC_PMEM_MEMSET_7         (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */

+

+#define FMC_PMEM_MEMWAIT_Pos      (8U)

+#define FMC_PMEM_MEMWAIT_Msk      (0xFFUL << FMC_PMEM_MEMWAIT_Pos)           /*!< 0x0000FF00 */

+#define FMC_PMEM_MEMWAIT          FMC_PMEM_MEMWAIT_Msk                       /*!<MEMWAIT[7:0] bits (Common memory wait time) */

+#define FMC_PMEM_MEMWAIT_0        (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */

+#define FMC_PMEM_MEMWAIT_1        (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */

+#define FMC_PMEM_MEMWAIT_2        (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */

+#define FMC_PMEM_MEMWAIT_3        (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */

+#define FMC_PMEM_MEMWAIT_4        (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */

+#define FMC_PMEM_MEMWAIT_5        (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */

+#define FMC_PMEM_MEMWAIT_6        (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */

+#define FMC_PMEM_MEMWAIT_7        (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */

+

+#define FMC_PMEM_MEMHOLD_Pos      (16U)

+#define FMC_PMEM_MEMHOLD_Msk      (0xFFUL << FMC_PMEM_MEMHOLD_Pos)           /*!< 0x00FF0000 */

+#define FMC_PMEM_MEMHOLD          FMC_PMEM_MEMHOLD_Msk                       /*!<MEMHOLD[7:0] bits (Common memory hold time) */

+#define FMC_PMEM_MEMHOLD_0        (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */

+#define FMC_PMEM_MEMHOLD_1        (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */

+#define FMC_PMEM_MEMHOLD_2        (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */

+#define FMC_PMEM_MEMHOLD_3        (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */

+#define FMC_PMEM_MEMHOLD_4        (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */

+#define FMC_PMEM_MEMHOLD_5        (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */

+#define FMC_PMEM_MEMHOLD_6        (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */

+#define FMC_PMEM_MEMHOLD_7        (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */

+

+#define FMC_PMEM_MEMHIZ_Pos       (24U)

+#define FMC_PMEM_MEMHIZ_Msk       (0xFFUL << FMC_PMEM_MEMHIZ_Pos)            /*!< 0xFF000000 */

+#define FMC_PMEM_MEMHIZ           FMC_PMEM_MEMHIZ_Msk                        /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */

+#define FMC_PMEM_MEMHIZ_0         (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */

+#define FMC_PMEM_MEMHIZ_1         (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */

+#define FMC_PMEM_MEMHIZ_2         (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */

+#define FMC_PMEM_MEMHIZ_3         (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */

+#define FMC_PMEM_MEMHIZ_4         (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */

+#define FMC_PMEM_MEMHIZ_5         (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */

+#define FMC_PMEM_MEMHIZ_6         (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */

+#define FMC_PMEM_MEMHIZ_7         (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */

+

+/******************  Bit definition for FMC_PATT register  ******************/

+#define FMC_PATT_ATTSET_Pos       (0U)

+#define FMC_PATT_ATTSET_Msk       (0xFFUL << FMC_PATT_ATTSET_Pos)            /*!< 0x000000FF */

+#define FMC_PATT_ATTSET           FMC_PATT_ATTSET_Msk                        /*!<ATTSET[7:0] bits (Attribute memory setup time) */

+#define FMC_PATT_ATTSET_0         (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */

+#define FMC_PATT_ATTSET_1         (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */

+#define FMC_PATT_ATTSET_2         (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */

+#define FMC_PATT_ATTSET_3         (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */

+#define FMC_PATT_ATTSET_4         (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */

+#define FMC_PATT_ATTSET_5         (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */

+#define FMC_PATT_ATTSET_6         (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */

+#define FMC_PATT_ATTSET_7         (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */

+

+#define FMC_PATT_ATTWAIT_Pos      (8U)

+#define FMC_PATT_ATTWAIT_Msk      (0xFFUL << FMC_PATT_ATTWAIT_Pos)           /*!< 0x0000FF00 */

+#define FMC_PATT_ATTWAIT          FMC_PATT_ATTWAIT_Msk                       /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */

+#define FMC_PATT_ATTWAIT_0        (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */

+#define FMC_PATT_ATTWAIT_1        (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */

+#define FMC_PATT_ATTWAIT_2        (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */

+#define FMC_PATT_ATTWAIT_3        (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */

+#define FMC_PATT_ATTWAIT_4        (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */

+#define FMC_PATT_ATTWAIT_5        (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */

+#define FMC_PATT_ATTWAIT_6        (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */

+#define FMC_PATT_ATTWAIT_7        (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */

+

+#define FMC_PATT_ATTHOLD_Pos      (16U)

+#define FMC_PATT_ATTHOLD_Msk      (0xFFUL << FMC_PATT_ATTHOLD_Pos)           /*!< 0x00FF0000 */

+#define FMC_PATT_ATTHOLD          FMC_PATT_ATTHOLD_Msk                       /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */

+#define FMC_PATT_ATTHOLD_0        (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */

+#define FMC_PATT_ATTHOLD_1        (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */

+#define FMC_PATT_ATTHOLD_2        (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */

+#define FMC_PATT_ATTHOLD_3        (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */

+#define FMC_PATT_ATTHOLD_4        (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */

+#define FMC_PATT_ATTHOLD_5        (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */

+#define FMC_PATT_ATTHOLD_6        (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */

+#define FMC_PATT_ATTHOLD_7        (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */

+

+#define FMC_PATT_ATTHIZ_Pos       (24U)

+#define FMC_PATT_ATTHIZ_Msk       (0xFFUL << FMC_PATT_ATTHIZ_Pos)            /*!< 0xFF000000 */

+#define FMC_PATT_ATTHIZ           FMC_PATT_ATTHIZ_Msk                        /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */

+#define FMC_PATT_ATTHIZ_0         (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */

+#define FMC_PATT_ATTHIZ_1         (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */

+#define FMC_PATT_ATTHIZ_2         (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */

+#define FMC_PATT_ATTHIZ_3         (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */

+#define FMC_PATT_ATTHIZ_4         (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */

+#define FMC_PATT_ATTHIZ_5         (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */

+#define FMC_PATT_ATTHIZ_6         (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */

+#define FMC_PATT_ATTHIZ_7         (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */

+

+/******************  Bit definition for FMC_ECCR3 register  ******************/

+#define FMC_ECCR3_ECC3_Pos         (0U)

+#define FMC_ECCR3_ECC3_Msk         (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)        /*!< 0xFFFFFFFF */

+#define FMC_ECCR3_ECC3             FMC_ECCR3_ECC3_Msk                          /*!<ECC result */

+

+/******************  Bit definition for FMC_SDCRx registers (x=1..4)  *********/

+#define FMC_SDCRx_NC_Pos           (0U)

+#define FMC_SDCRx_NC_Msk           (0x3UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000003 */

+#define FMC_SDCRx_NC               FMC_SDCRx_NC_Msk                            /*!<NC[1:0] bits (Number of column bits) */

+#define FMC_SDCRx_NC_0             (0x1UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000001 */

+#define FMC_SDCRx_NC_1             (0x2UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000002 */

+

+#define FMC_SDCRx_NR_Pos           (2U)

+#define FMC_SDCRx_NR_Msk           (0x3UL << FMC_SDCRx_NR_Pos)                 /*!< 0x0000000C */

+#define FMC_SDCRx_NR               FMC_SDCRx_NR_Msk                            /*!<NR[1:0] bits (Number of row bits) */

+#define FMC_SDCRx_NR_0             (0x1UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000004 */

+#define FMC_SDCRx_NR_1             (0x2UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000008 */

+

+#define FMC_SDCRx_MWID_Pos         (4U)

+#define FMC_SDCRx_MWID_Msk         (0x3UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000030 */

+#define FMC_SDCRx_MWID             FMC_SDCRx_MWID_Msk                          /*!<NR[1:0] bits (Number of row bits) */

+#define FMC_SDCRx_MWID_0           (0x1UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000010 */

+#define FMC_SDCRx_MWID_1           (0x2UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000020 */

+

+#define FMC_SDCRx_NB_Pos           (6U)

+#define FMC_SDCRx_NB_Msk           (0x1UL << FMC_SDCRx_NB_Pos)                 /*!< 0x00000040 */

+#define FMC_SDCRx_NB               FMC_SDCRx_NB_Msk                            /*!<Number of internal bank */

+

+#define FMC_SDCRx_CAS_Pos          (7U)

+#define FMC_SDCRx_CAS_Msk          (0x3UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000180 */

+#define FMC_SDCRx_CAS              FMC_SDCRx_CAS_Msk                           /*!<CAS[1:0] bits (CAS latency) */

+#define FMC_SDCRx_CAS_0            (0x1UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000080 */

+#define FMC_SDCRx_CAS_1            (0x2UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000100 */

+

+#define FMC_SDCRx_WP_Pos           (9U)

+#define FMC_SDCRx_WP_Msk           (0x1UL << FMC_SDCRx_WP_Pos)                 /*!< 0x00000200 */

+#define FMC_SDCRx_WP               FMC_SDCRx_WP_Msk                            /*!<Write protection */

+

+#define FMC_SDCRx_SDCLK_Pos        (10U)

+#define FMC_SDCRx_SDCLK_Msk        (0x3UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000C00 */

+#define FMC_SDCRx_SDCLK            FMC_SDCRx_SDCLK_Msk                         /*!<SDRAM clock configuration */

+#define FMC_SDCRx_SDCLK_0          (0x1UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000400 */

+#define FMC_SDCRx_SDCLK_1          (0x2UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000800 */

+

+#define FMC_SDCRx_RBURST_Pos       (12U)

+#define FMC_SDCRx_RBURST_Msk       (0x1UL << FMC_SDCRx_RBURST_Pos)             /*!< 0x00001000 */

+#define FMC_SDCRx_RBURST           FMC_SDCRx_RBURST_Msk                        /*!<Read burst */

+

+#define FMC_SDCRx_RPIPE_Pos        (13U)

+#define FMC_SDCRx_RPIPE_Msk        (0x3UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00006000 */

+#define FMC_SDCRx_RPIPE            FMC_SDCRx_RPIPE_Msk                         /*!<Write protection */

+#define FMC_SDCRx_RPIPE_0          (0x1UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00002000 */

+#define FMC_SDCRx_RPIPE_1          (0x2UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00004000 */

+

+/******************  Bit definition for FMC_SDTRx(1,2) register  ******************/

+#define FMC_SDTRx_TMRD_Pos         (0U)

+#define FMC_SDTRx_TMRD_Msk         (0xFUL << FMC_SDTRx_TMRD_Pos)               /*!< 0x0000000F */

+#define FMC_SDTRx_TMRD             FMC_SDTRx_TMRD_Msk                          /*!<TMRD[3:0] bits (Load mode register to active) */

+#define FMC_SDTRx_TMRD_0           (0x1UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000001 */

+#define FMC_SDTRx_TMRD_1           (0x2UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000002 */

+#define FMC_SDTRx_TMRD_2           (0x4UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000004 */

+#define FMC_SDTRx_TMRD_3           (0x8UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000008 */

+

+#define FMC_SDTRx_TXSR_Pos         (4U)

+#define FMC_SDTRx_TXSR_Msk         (0xFUL << FMC_SDTRx_TXSR_Pos)               /*!< 0x000000F0 */

+#define FMC_SDTRx_TXSR             FMC_SDTRx_TXSR_Msk                          /*!<TXSR[3:0] bits (Exit self refresh) */

+#define FMC_SDTRx_TXSR_0           (0x1UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000010 */

+#define FMC_SDTRx_TXSR_1           (0x2UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000020 */

+#define FMC_SDTRx_TXSR_2           (0x4UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000040 */

+#define FMC_SDTRx_TXSR_3           (0x8UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000080 */

+

+#define FMC_SDTRx_TRAS_Pos         (8U)

+#define FMC_SDTRx_TRAS_Msk         (0xFUL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000F00 */

+#define FMC_SDTRx_TRAS             FMC_SDTRx_TRAS_Msk                          /*!<TRAS[3:0] bits (Self refresh time) */

+#define FMC_SDTRx_TRAS_0           (0x1UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000100 */

+#define FMC_SDTRx_TRAS_1           (0x2UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000200 */

+#define FMC_SDTRx_TRAS_2           (0x4UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000400 */

+#define FMC_SDTRx_TRAS_3           (0x8UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000800 */

+

+#define FMC_SDTRx_TRC_Pos          (12U)

+#define FMC_SDTRx_TRC_Msk          (0xFUL << FMC_SDTRx_TRC_Pos)                /*!< 0x0000F000 */

+#define FMC_SDTRx_TRC              FMC_SDTRx_TRC_Msk                           /*!<TRC[2:0] bits (Row cycle delay) */

+#define FMC_SDTRx_TRC_0            (0x1UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00001000 */

+#define FMC_SDTRx_TRC_1            (0x2UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00002000 */

+#define FMC_SDTRx_TRC_2            (0x4UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00004000 */

+

+#define FMC_SDTRx_TWR_Pos          (16U)

+#define FMC_SDTRx_TWR_Msk          (0xFUL << FMC_SDTRx_TWR_Pos)                /*!< 0x000F0000 */

+#define FMC_SDTRx_TWR              FMC_SDTRx_TWR_Msk                           /*!<TRC[2:0] bits (Write recovery delay) */

+#define FMC_SDTRx_TWR_0            (0x1UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00010000 */

+#define FMC_SDTRx_TWR_1            (0x2UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00020000 */

+#define FMC_SDTRx_TWR_2            (0x4UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00040000 */

+

+#define FMC_SDTRx_TRP_Pos          (20U)

+#define FMC_SDTRx_TRP_Msk          (0xFUL << FMC_SDTRx_TRP_Pos)                /*!< 0x00F00000 */

+#define FMC_SDTRx_TRP              FMC_SDTRx_TRP_Msk                           /*!<TRP[2:0] bits (Row precharge delay) */

+#define FMC_SDTRx_TRP_0            (0x1UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00100000 */

+#define FMC_SDTRx_TRP_1            (0x2UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00200000 */

+#define FMC_SDTRx_TRP_2            (0x4UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00400000 */

+

+#define FMC_SDTRx_TRCD_Pos         (24U)

+#define FMC_SDTRx_TRCD_Msk         (0xFUL << FMC_SDTRx_TRCD_Pos)               /*!< 0x0F000000 */

+#define FMC_SDTRx_TRCD             FMC_SDTRx_TRCD_Msk                          /*!<TRP[2:0] bits (Row to column delay) */

+#define FMC_SDTRx_TRCD_0           (0x1UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x01000000 */

+#define FMC_SDTRx_TRCD_1           (0x2UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x02000000 */

+#define FMC_SDTRx_TRCD_2           (0x4UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x04000000 */

+

+/******************  Bit definition for FMC_SDCMR register  ******************/

+#define FMC_SDCMR_MODE_Pos         (0U)

+#define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */

+#define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */

+#define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */

+#define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */

+#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */

+

+#define FMC_SDCMR_CTB2_Pos         (3U)

+#define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */

+#define FMC_SDCMR_CTB2             FMC_SDCMR_CTB2_Msk                          /*!<Command target 2 */

+

+#define FMC_SDCMR_CTB1_Pos         (4U)

+#define FMC_SDCMR_CTB1_Msk         (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */

+#define FMC_SDCMR_CTB1             FMC_SDCMR_CTB1_Msk                          /*!<Command target 1 */

+

+#define FMC_SDCMR_NRFS_Pos         (5U)

+#define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */

+#define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!<NRFS[3:0] bits (Number of auto-refresh) */

+#define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000020 */

+#define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000040 */

+#define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000080 */

+#define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000100 */

+

+#define FMC_SDCMR_MRD_Pos          (9U)

+#define FMC_SDCMR_MRD_Msk          (0x1FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */

+#define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!<MRD[12:0] bits (Mode register definition) */

+

+/******************  Bit definition for FMC_SDRTR register  ******************/

+#define FMC_SDRTR_CRE_Pos          (0U)

+#define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */

+#define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!<Clear refresh error flag */

+

+#define FMC_SDRTR_COUNT_Pos        (1U)

+#define FMC_SDRTR_COUNT_Msk        (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */

+#define FMC_SDRTR_COUNT            FMC_SDRTR_COUNT_Msk                         /*!<COUNT[12:0] bits (Refresh timer count) */

+

+#define FMC_SDRTR_REIE_Pos         (14U)

+#define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */

+#define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!<RES interupt enable */

+

+/******************  Bit definition for FMC_SDSR register  ******************/

+#define FMC_SDSR_RE_Pos            (0U)

+#define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */

+#define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!<Refresh error flag */

+

+#define FMC_SDSR_MODES1_Pos        (1U)

+#define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */

+#define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!<MODES1[1:0]bits (Status mode for bank 1) */

+#define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000002 */

+#define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000004 */

+

+#define FMC_SDSR_MODES2_Pos        (3U)

+#define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */

+#define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!<MODES2[1:0]bits (Status mode for bank 2) */

+#define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000008 */

+#define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000010 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            General Purpose I/O                             */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bits definition for GPIO_MODER register  *****************/

+#define GPIO_MODER_MODE0_Pos           (0U)

+#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */

+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk

+#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */

+#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */

+

+#define GPIO_MODER_MODE1_Pos           (2U)

+#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */

+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk

+#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */

+#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */

+

+#define GPIO_MODER_MODE2_Pos           (4U)

+#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */

+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk

+#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */

+#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */

+

+#define GPIO_MODER_MODE3_Pos           (6U)

+#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */

+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk

+#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */

+#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */

+

+#define GPIO_MODER_MODE4_Pos           (8U)

+#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */

+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk

+#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */

+#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */

+

+#define GPIO_MODER_MODE5_Pos           (10U)

+#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */

+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk

+#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */

+#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */

+

+#define GPIO_MODER_MODE6_Pos           (12U)

+#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */

+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk

+#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */

+#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */

+

+#define GPIO_MODER_MODE7_Pos           (14U)

+#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */

+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk

+#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */

+#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */

+

+#define GPIO_MODER_MODE8_Pos           (16U)

+#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */

+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk

+#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */

+#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */

+

+#define GPIO_MODER_MODE9_Pos           (18U)

+#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */

+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk

+#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */

+#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */

+

+#define GPIO_MODER_MODE10_Pos          (20U)

+#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */

+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk

+#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */

+#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */

+

+#define GPIO_MODER_MODE11_Pos          (22U)

+#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */

+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk

+#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */

+#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */

+

+#define GPIO_MODER_MODE12_Pos          (24U)

+#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */

+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk

+#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */

+#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */

+

+#define GPIO_MODER_MODE13_Pos          (26U)

+#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */

+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk

+#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */

+#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */

+

+#define GPIO_MODER_MODE14_Pos          (28U)

+#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */

+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk

+#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */

+#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */

+

+#define GPIO_MODER_MODE15_Pos          (30U)

+#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */

+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk

+#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */

+#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_OTYPER register  ****************/

+#define GPIO_OTYPER_OT0_Pos            (0U)

+#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */

+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk

+#define GPIO_OTYPER_OT1_Pos            (1U)

+#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */

+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk

+#define GPIO_OTYPER_OT2_Pos            (2U)

+#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */

+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk

+#define GPIO_OTYPER_OT3_Pos            (3U)

+#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */

+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk

+#define GPIO_OTYPER_OT4_Pos            (4U)

+#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */

+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk

+#define GPIO_OTYPER_OT5_Pos            (5U)

+#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */

+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk

+#define GPIO_OTYPER_OT6_Pos            (6U)

+#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */

+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk

+#define GPIO_OTYPER_OT7_Pos            (7U)

+#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */

+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk

+#define GPIO_OTYPER_OT8_Pos            (8U)

+#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */

+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk

+#define GPIO_OTYPER_OT9_Pos            (9U)

+#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */

+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk

+#define GPIO_OTYPER_OT10_Pos           (10U)

+#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */

+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk

+#define GPIO_OTYPER_OT11_Pos           (11U)

+#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */

+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk

+#define GPIO_OTYPER_OT12_Pos           (12U)

+#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */

+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk

+#define GPIO_OTYPER_OT13_Pos           (13U)

+#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */

+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk

+#define GPIO_OTYPER_OT14_Pos           (14U)

+#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */

+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk

+#define GPIO_OTYPER_OT15_Pos           (15U)

+#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */

+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk

+

+/******************  Bits definition for GPIO_OSPEEDR register  ***************/

+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)

+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */

+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk

+#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */

+#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */

+

+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)

+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */

+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk

+#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */

+#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */

+

+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)

+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */

+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk

+#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */

+#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */

+

+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)

+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */

+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk

+#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */

+#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */

+

+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)

+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */

+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk

+#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */

+#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */

+

+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)

+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */

+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk

+#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */

+#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */

+

+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)

+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */

+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk

+#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */

+#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */

+

+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)

+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */

+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk

+#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */

+#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */

+

+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)

+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */

+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk

+#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */

+#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */

+

+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)

+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */

+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk

+#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */

+#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */

+

+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)

+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */

+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk

+#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */

+#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */

+

+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)

+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */

+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk

+#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */

+#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */

+

+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)

+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */

+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk

+#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */

+#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */

+

+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)

+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */

+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk

+#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */

+#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */

+

+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)

+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */

+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk

+#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */

+#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */

+

+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)

+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */

+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk

+#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */

+#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_PUPDR register  *****************/

+#define GPIO_PUPDR_PUPD0_Pos           (0U)

+#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */

+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk

+#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */

+#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */

+

+#define GPIO_PUPDR_PUPD1_Pos           (2U)

+#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */

+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk

+#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */

+#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */

+

+#define GPIO_PUPDR_PUPD2_Pos           (4U)

+#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */

+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk

+#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */

+#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */

+

+#define GPIO_PUPDR_PUPD3_Pos           (6U)

+#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */

+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk

+#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */

+#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */

+

+#define GPIO_PUPDR_PUPD4_Pos           (8U)

+#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */

+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk

+#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */

+#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */

+

+#define GPIO_PUPDR_PUPD5_Pos           (10U)

+#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */

+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk

+#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */

+#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */

+

+#define GPIO_PUPDR_PUPD6_Pos           (12U)

+#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */

+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk

+#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */

+#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */

+

+#define GPIO_PUPDR_PUPD7_Pos           (14U)

+#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */

+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk

+#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */

+#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */

+

+#define GPIO_PUPDR_PUPD8_Pos           (16U)

+#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */

+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk

+#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */

+#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */

+

+#define GPIO_PUPDR_PUPD9_Pos           (18U)

+#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */

+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk

+#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */

+#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */

+

+#define GPIO_PUPDR_PUPD10_Pos          (20U)

+#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */

+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk

+#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */

+#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */

+

+#define GPIO_PUPDR_PUPD11_Pos          (22U)

+#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */

+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk

+#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */

+#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */

+

+#define GPIO_PUPDR_PUPD12_Pos          (24U)

+#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */

+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk

+#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */

+#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */

+

+#define GPIO_PUPDR_PUPD13_Pos          (26U)

+#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */

+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk

+#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */

+#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */

+

+#define GPIO_PUPDR_PUPD14_Pos          (28U)

+#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */

+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk

+#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */

+#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */

+

+#define GPIO_PUPDR_PUPD15_Pos          (30U)

+#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */

+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk

+#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */

+#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_IDR register  *******************/

+#define GPIO_IDR_ID0_Pos               (0U)

+#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */

+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk

+#define GPIO_IDR_ID1_Pos               (1U)

+#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */

+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk

+#define GPIO_IDR_ID2_Pos               (2U)

+#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */

+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk

+#define GPIO_IDR_ID3_Pos               (3U)

+#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */

+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk

+#define GPIO_IDR_ID4_Pos               (4U)

+#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */

+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk

+#define GPIO_IDR_ID5_Pos               (5U)

+#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */

+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk

+#define GPIO_IDR_ID6_Pos               (6U)

+#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */

+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk

+#define GPIO_IDR_ID7_Pos               (7U)

+#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */

+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk

+#define GPIO_IDR_ID8_Pos               (8U)

+#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */

+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk

+#define GPIO_IDR_ID9_Pos               (9U)

+#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */

+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk

+#define GPIO_IDR_ID10_Pos              (10U)

+#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */

+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk

+#define GPIO_IDR_ID11_Pos              (11U)

+#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */

+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk

+#define GPIO_IDR_ID12_Pos              (12U)

+#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */

+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk

+#define GPIO_IDR_ID13_Pos              (13U)

+#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */

+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk

+#define GPIO_IDR_ID14_Pos              (14U)

+#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */

+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk

+#define GPIO_IDR_ID15_Pos              (15U)

+#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */

+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk

+

+/******************  Bits definition for GPIO_ODR register  *******************/

+#define GPIO_ODR_OD0_Pos               (0U)

+#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */

+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk

+#define GPIO_ODR_OD1_Pos               (1U)

+#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */

+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk

+#define GPIO_ODR_OD2_Pos               (2U)

+#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */

+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk

+#define GPIO_ODR_OD3_Pos               (3U)

+#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */

+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk

+#define GPIO_ODR_OD4_Pos               (4U)

+#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */

+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk

+#define GPIO_ODR_OD5_Pos               (5U)

+#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */

+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk

+#define GPIO_ODR_OD6_Pos               (6U)

+#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */

+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk

+#define GPIO_ODR_OD7_Pos               (7U)

+#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */

+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk

+#define GPIO_ODR_OD8_Pos               (8U)

+#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */

+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk

+#define GPIO_ODR_OD9_Pos               (9U)

+#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */

+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk

+#define GPIO_ODR_OD10_Pos              (10U)

+#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */

+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk

+#define GPIO_ODR_OD11_Pos              (11U)

+#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */

+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk

+#define GPIO_ODR_OD12_Pos              (12U)

+#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */

+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk

+#define GPIO_ODR_OD13_Pos              (13U)

+#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */

+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk

+#define GPIO_ODR_OD14_Pos              (14U)

+#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */

+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk

+#define GPIO_ODR_OD15_Pos              (15U)

+#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */

+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk

+

+/******************  Bits definition for GPIO_BSRR register  ******************/

+#define GPIO_BSRR_BS0_Pos              (0U)

+#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */

+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk

+#define GPIO_BSRR_BS1_Pos              (1U)

+#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */

+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk

+#define GPIO_BSRR_BS2_Pos              (2U)

+#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */

+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk

+#define GPIO_BSRR_BS3_Pos              (3U)

+#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */

+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk

+#define GPIO_BSRR_BS4_Pos              (4U)

+#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */

+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk

+#define GPIO_BSRR_BS5_Pos              (5U)

+#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */

+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk

+#define GPIO_BSRR_BS6_Pos              (6U)

+#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */

+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk

+#define GPIO_BSRR_BS7_Pos              (7U)

+#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */

+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk

+#define GPIO_BSRR_BS8_Pos              (8U)

+#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */

+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk

+#define GPIO_BSRR_BS9_Pos              (9U)

+#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */

+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk

+#define GPIO_BSRR_BS10_Pos             (10U)

+#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */

+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk

+#define GPIO_BSRR_BS11_Pos             (11U)

+#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */

+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk

+#define GPIO_BSRR_BS12_Pos             (12U)

+#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */

+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk

+#define GPIO_BSRR_BS13_Pos             (13U)

+#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */

+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk

+#define GPIO_BSRR_BS14_Pos             (14U)

+#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */

+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk

+#define GPIO_BSRR_BS15_Pos             (15U)

+#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */

+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk

+#define GPIO_BSRR_BR0_Pos              (16U)

+#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */

+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk

+#define GPIO_BSRR_BR1_Pos              (17U)

+#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */

+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk

+#define GPIO_BSRR_BR2_Pos              (18U)

+#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */

+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk

+#define GPIO_BSRR_BR3_Pos              (19U)

+#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */

+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk

+#define GPIO_BSRR_BR4_Pos              (20U)

+#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */

+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk

+#define GPIO_BSRR_BR5_Pos              (21U)

+#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */

+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk

+#define GPIO_BSRR_BR6_Pos              (22U)

+#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */

+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk

+#define GPIO_BSRR_BR7_Pos              (23U)

+#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */

+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk

+#define GPIO_BSRR_BR8_Pos              (24U)

+#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */

+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk

+#define GPIO_BSRR_BR9_Pos              (25U)

+#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */

+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk

+#define GPIO_BSRR_BR10_Pos             (26U)

+#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */

+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk

+#define GPIO_BSRR_BR11_Pos             (27U)

+#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */

+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk

+#define GPIO_BSRR_BR12_Pos             (28U)

+#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */

+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk

+#define GPIO_BSRR_BR13_Pos             (29U)

+#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */

+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk

+#define GPIO_BSRR_BR14_Pos             (30U)

+#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */

+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk

+#define GPIO_BSRR_BR15_Pos             (31U)

+#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */

+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk

+

+/****************** Bit definition for GPIO_LCKR register *********************/

+#define GPIO_LCKR_LCK0_Pos             (0U)

+#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */

+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk

+#define GPIO_LCKR_LCK1_Pos             (1U)

+#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */

+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk

+#define GPIO_LCKR_LCK2_Pos             (2U)

+#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */

+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk

+#define GPIO_LCKR_LCK3_Pos             (3U)

+#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */

+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk

+#define GPIO_LCKR_LCK4_Pos             (4U)

+#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */

+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk

+#define GPIO_LCKR_LCK5_Pos             (5U)

+#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */

+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk

+#define GPIO_LCKR_LCK6_Pos             (6U)

+#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */

+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk

+#define GPIO_LCKR_LCK7_Pos             (7U)

+#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */

+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk

+#define GPIO_LCKR_LCK8_Pos             (8U)

+#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */

+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk

+#define GPIO_LCKR_LCK9_Pos             (9U)

+#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */

+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk

+#define GPIO_LCKR_LCK10_Pos            (10U)

+#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */

+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk

+#define GPIO_LCKR_LCK11_Pos            (11U)

+#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */

+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk

+#define GPIO_LCKR_LCK12_Pos            (12U)

+#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */

+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk

+#define GPIO_LCKR_LCK13_Pos            (13U)

+#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */

+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk

+#define GPIO_LCKR_LCK14_Pos            (14U)

+#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */

+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk

+#define GPIO_LCKR_LCK15_Pos            (15U)

+#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */

+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk

+#define GPIO_LCKR_LCKK_Pos             (16U)

+#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */

+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk

+

+/****************** Bit definition for GPIO_AFRL register  ********************/

+#define GPIO_AFRL_AFSEL0_Pos           (0U)

+#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */

+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk

+#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */

+#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */

+#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */

+#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */

+#define GPIO_AFRL_AFSEL1_Pos           (4U)

+#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */

+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk

+#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */

+#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */

+#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */

+#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */

+#define GPIO_AFRL_AFSEL2_Pos           (8U)

+#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */

+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk

+#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */

+#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */

+#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */

+#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */

+#define GPIO_AFRL_AFSEL3_Pos           (12U)

+#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */

+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk

+#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */

+#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */

+#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */

+#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */

+#define GPIO_AFRL_AFSEL4_Pos           (16U)

+#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */

+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk

+#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */

+#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */

+#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */

+#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */

+#define GPIO_AFRL_AFSEL5_Pos           (20U)

+#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */

+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk

+#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */

+#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */

+#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */

+#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */

+#define GPIO_AFRL_AFSEL6_Pos           (24U)

+#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */

+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk

+#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */

+#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */

+#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */

+#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */

+#define GPIO_AFRL_AFSEL7_Pos           (28U)

+#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */

+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk

+#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */

+#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */

+#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */

+#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */

+

+/* Legacy defines */

+#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0

+#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1

+#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2

+#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3

+#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4

+#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5

+#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6

+#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7

+

+/****************** Bit definition for GPIO_AFRH register  ********************/

+#define GPIO_AFRH_AFSEL8_Pos           (0U)

+#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */

+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk

+#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */

+#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */

+#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */

+#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */

+#define GPIO_AFRH_AFSEL9_Pos           (4U)

+#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */

+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk

+#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */

+#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */

+#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */

+#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */

+#define GPIO_AFRH_AFSEL10_Pos          (8U)

+#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */

+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk

+#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */

+#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */

+#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */

+#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */

+#define GPIO_AFRH_AFSEL11_Pos          (12U)

+#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */

+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk

+#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */

+#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */

+#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */

+#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */

+#define GPIO_AFRH_AFSEL12_Pos          (16U)

+#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */

+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk

+#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */

+#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */

+#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */

+#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */

+#define GPIO_AFRH_AFSEL13_Pos          (20U)

+#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */

+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk

+#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */

+#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */

+#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */

+#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */

+#define GPIO_AFRH_AFSEL14_Pos          (24U)

+#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */

+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk

+#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */

+#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */

+#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */

+#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */

+#define GPIO_AFRH_AFSEL15_Pos          (28U)

+#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */

+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk

+#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */

+#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */

+#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */

+#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */

+

+/* Legacy defines */

+#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8

+#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9

+#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10

+#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11

+#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12

+#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13

+#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14

+#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15

+

+/******************************************************************************/

+/*                                                                            */

+/*                        HSEM HW Semaphore                                   */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for HSEM_R register  ********************/

+#define HSEM_R_PROCID_Pos         (0U)

+#define HSEM_R_PROCID_Msk         (0xFFUL << HSEM_R_PROCID_Pos)                /*!< 0x000000FF */

+#define HSEM_R_PROCID             HSEM_R_PROCID_Msk                            /*!<Semaphore ProcessID */

+#define HSEM_R_COREID_Pos         (8U)

+#define HSEM_R_COREID_Msk         (0xFFUL << HSEM_R_COREID_Pos)                /*!< 0x0000FF00 */

+#define HSEM_R_COREID             HSEM_R_COREID_Msk                            /*!<Semaphore CoreID.   */

+#define HSEM_R_LOCK_Pos           (31U)

+#define HSEM_R_LOCK_Msk           (0x1UL << HSEM_R_LOCK_Pos)                   /*!< 0x80000000 */

+#define HSEM_R_LOCK               HSEM_R_LOCK_Msk                              /*!<Lock indication.    */

+

+/********************  Bit definition for HSEM_RLR register  ******************/

+#define HSEM_RLR_PROCID_Pos       (0U)

+#define HSEM_RLR_PROCID_Msk       (0xFFUL << HSEM_RLR_PROCID_Pos)              /*!< 0x000000FF */

+#define HSEM_RLR_PROCID           HSEM_RLR_PROCID_Msk                          /*!<Semaphore ProcessID */

+#define HSEM_RLR_COREID_Pos       (8U)

+#define HSEM_RLR_COREID_Msk       (0xFFUL << HSEM_RLR_COREID_Pos)              /*!< 0x0000FF00 */

+#define HSEM_RLR_COREID           HSEM_RLR_COREID_Msk                          /*!<Semaphore CoreID.   */

+#define HSEM_RLR_LOCK_Pos         (31U)

+#define HSEM_RLR_LOCK_Msk         (0x1UL << HSEM_RLR_LOCK_Pos)                 /*!< 0x80000000 */

+#define HSEM_RLR_LOCK             HSEM_RLR_LOCK_Msk                            /*!<Lock indication.    */

+

+/********************  Bit definition for HSEM_C1IER register  *****************/

+#define HSEM_C1IER_ISE0_Pos       (0U)

+#define HSEM_C1IER_ISE0_Msk       (0x1UL << HSEM_C1IER_ISE0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1IER_ISE0           HSEM_C1IER_ISE0_Msk                          /*!<semaphore 0 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE1_Pos       (1U)

+#define HSEM_C1IER_ISE1_Msk       (0x1UL << HSEM_C1IER_ISE1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1IER_ISE1           HSEM_C1IER_ISE1_Msk                          /*!<semaphore 1 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE2_Pos       (2U)

+#define HSEM_C1IER_ISE2_Msk       (0x1UL << HSEM_C1IER_ISE2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1IER_ISE2           HSEM_C1IER_ISE2_Msk                          /*!<semaphore 2 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE3_Pos       (3U)

+#define HSEM_C1IER_ISE3_Msk       (0x1UL << HSEM_C1IER_ISE3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1IER_ISE3           HSEM_C1IER_ISE3_Msk                          /*!<semaphore 3 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE4_Pos       (4U)

+#define HSEM_C1IER_ISE4_Msk       (0x1UL << HSEM_C1IER_ISE4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1IER_ISE4           HSEM_C1IER_ISE4_Msk                          /*!<semaphore 4 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE5_Pos       (5U)

+#define HSEM_C1IER_ISE5_Msk       (0x1UL << HSEM_C1IER_ISE5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1IER_ISE5           HSEM_C1IER_ISE5_Msk                          /*!<semaphore 5 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE6_Pos       (6U)

+#define HSEM_C1IER_ISE6_Msk       (0x1UL << HSEM_C1IER_ISE6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1IER_ISE6           HSEM_C1IER_ISE6_Msk                          /*!<semaphore 6 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE7_Pos       (7U)

+#define HSEM_C1IER_ISE7_Msk       (0x1UL << HSEM_C1IER_ISE7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1IER_ISE7           HSEM_C1IER_ISE7_Msk                          /*!<semaphore 7 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE8_Pos       (8U)

+#define HSEM_C1IER_ISE8_Msk       (0x1UL << HSEM_C1IER_ISE8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1IER_ISE8           HSEM_C1IER_ISE8_Msk                          /*!<semaphore 8 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE9_Pos       (9U)

+#define HSEM_C1IER_ISE9_Msk       (0x1UL << HSEM_C1IER_ISE9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1IER_ISE9           HSEM_C1IER_ISE9_Msk                          /*!<semaphore 9 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE10_Pos      (10U)

+#define HSEM_C1IER_ISE10_Msk      (0x1UL << HSEM_C1IER_ISE10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1IER_ISE10          HSEM_C1IER_ISE10_Msk                         /*!<semaphore 10 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE11_Pos      (11U)

+#define HSEM_C1IER_ISE11_Msk      (0x1UL << HSEM_C1IER_ISE11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1IER_ISE11          HSEM_C1IER_ISE11_Msk                         /*!<semaphore 11 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE12_Pos      (12U)

+#define HSEM_C1IER_ISE12_Msk      (0x1UL << HSEM_C1IER_ISE12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1IER_ISE12          HSEM_C1IER_ISE12_Msk                         /*!<semaphore 12 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE13_Pos      (13U)

+#define HSEM_C1IER_ISE13_Msk      (0x1UL << HSEM_C1IER_ISE13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1IER_ISE13          HSEM_C1IER_ISE13_Msk                         /*!<semaphore 13 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE14_Pos      (14U)

+#define HSEM_C1IER_ISE14_Msk      (0x1UL << HSEM_C1IER_ISE14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1IER_ISE14          HSEM_C1IER_ISE14_Msk                         /*!<semaphore 14 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE15_Pos      (15U)

+#define HSEM_C1IER_ISE15_Msk      (0x1UL << HSEM_C1IER_ISE15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1IER_ISE15          HSEM_C1IER_ISE15_Msk                         /*!<semaphore 15 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE16_Pos      (16U)

+#define HSEM_C1IER_ISE16_Msk      (0x1UL << HSEM_C1IER_ISE16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1IER_ISE16          HSEM_C1IER_ISE16_Msk                         /*!<semaphore 16 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE17_Pos      (17U)

+#define HSEM_C1IER_ISE17_Msk      (0x1UL << HSEM_C1IER_ISE17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1IER_ISE17          HSEM_C1IER_ISE17_Msk                         /*!<semaphore 17 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE18_Pos      (18U)

+#define HSEM_C1IER_ISE18_Msk      (0x1UL << HSEM_C1IER_ISE18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1IER_ISE18          HSEM_C1IER_ISE18_Msk                         /*!<semaphore 18 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE19_Pos      (19U)

+#define HSEM_C1IER_ISE19_Msk      (0x1UL << HSEM_C1IER_ISE19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1IER_ISE19          HSEM_C1IER_ISE19_Msk                         /*!<semaphore 19 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE20_Pos      (20U)

+#define HSEM_C1IER_ISE20_Msk      (0x1UL << HSEM_C1IER_ISE20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1IER_ISE20          HSEM_C1IER_ISE20_Msk                         /*!<semaphore 20 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE21_Pos      (21U)

+#define HSEM_C1IER_ISE21_Msk      (0x1UL << HSEM_C1IER_ISE21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1IER_ISE21          HSEM_C1IER_ISE21_Msk                         /*!<semaphore 21 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE22_Pos      (22U)

+#define HSEM_C1IER_ISE22_Msk      (0x1UL << HSEM_C1IER_ISE22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1IER_ISE22          HSEM_C1IER_ISE22_Msk                         /*!<semaphore 22 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE23_Pos      (23U)

+#define HSEM_C1IER_ISE23_Msk      (0x1UL << HSEM_C1IER_ISE23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1IER_ISE23          HSEM_C1IER_ISE23_Msk                         /*!<semaphore 23 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE24_Pos      (24U)

+#define HSEM_C1IER_ISE24_Msk      (0x1UL << HSEM_C1IER_ISE24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1IER_ISE24          HSEM_C1IER_ISE24_Msk                         /*!<semaphore 24 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE25_Pos      (25U)

+#define HSEM_C1IER_ISE25_Msk      (0x1UL << HSEM_C1IER_ISE25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1IER_ISE25          HSEM_C1IER_ISE25_Msk                         /*!<semaphore 25 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE26_Pos      (26U)

+#define HSEM_C1IER_ISE26_Msk      (0x1UL << HSEM_C1IER_ISE26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1IER_ISE26          HSEM_C1IER_ISE26_Msk                         /*!<semaphore 26 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE27_Pos      (27U)

+#define HSEM_C1IER_ISE27_Msk      (0x1UL << HSEM_C1IER_ISE27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1IER_ISE27          HSEM_C1IER_ISE27_Msk                         /*!<semaphore 27 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE28_Pos      (28U)

+#define HSEM_C1IER_ISE28_Msk      (0x1UL << HSEM_C1IER_ISE28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1IER_ISE28          HSEM_C1IER_ISE28_Msk                         /*!<semaphore 28 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE29_Pos      (29U)

+#define HSEM_C1IER_ISE29_Msk      (0x1UL << HSEM_C1IER_ISE29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1IER_ISE29          HSEM_C1IER_ISE29_Msk                         /*!<semaphore 29 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE30_Pos      (30U)

+#define HSEM_C1IER_ISE30_Msk      (0x1UL << HSEM_C1IER_ISE30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1IER_ISE30          HSEM_C1IER_ISE30_Msk                         /*!<semaphore 30 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE31_Pos      (31U)

+#define HSEM_C1IER_ISE31_Msk      (0x1UL << HSEM_C1IER_ISE31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1IER_ISE31          HSEM_C1IER_ISE31_Msk                         /*!<semaphore 31 interrupt 0 enable bit. */

+

+/********************  Bit definition for HSEM_C1ICR register  *****************/

+#define HSEM_C1ICR_ISC0_Pos       (0U)

+#define HSEM_C1ICR_ISC0_Msk       (0x1UL << HSEM_C1ICR_ISC0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1ICR_ISC0           HSEM_C1ICR_ISC0_Msk                          /*!<semaphore 0 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC1_Pos       (1U)

+#define HSEM_C1ICR_ISC1_Msk       (0x1UL << HSEM_C1ICR_ISC1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1ICR_ISC1           HSEM_C1ICR_ISC1_Msk                          /*!<semaphore 1 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC2_Pos       (2U)

+#define HSEM_C1ICR_ISC2_Msk       (0x1UL << HSEM_C1ICR_ISC2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1ICR_ISC2           HSEM_C1ICR_ISC2_Msk                          /*!<semaphore 2 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC3_Pos       (3U)

+#define HSEM_C1ICR_ISC3_Msk       (0x1UL << HSEM_C1ICR_ISC3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1ICR_ISC3           HSEM_C1ICR_ISC3_Msk                          /*!<semaphore 3 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC4_Pos       (4U)

+#define HSEM_C1ICR_ISC4_Msk       (0x1UL << HSEM_C1ICR_ISC4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1ICR_ISC4           HSEM_C1ICR_ISC4_Msk                          /*!<semaphore 4 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC5_Pos       (5U)

+#define HSEM_C1ICR_ISC5_Msk       (0x1UL << HSEM_C1ICR_ISC5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1ICR_ISC5           HSEM_C1ICR_ISC5_Msk                          /*!<semaphore 5 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC6_Pos       (6U)

+#define HSEM_C1ICR_ISC6_Msk       (0x1UL << HSEM_C1ICR_ISC6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1ICR_ISC6           HSEM_C1ICR_ISC6_Msk                          /*!<semaphore 6 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC7_Pos       (7U)

+#define HSEM_C1ICR_ISC7_Msk       (0x1UL << HSEM_C1ICR_ISC7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1ICR_ISC7           HSEM_C1ICR_ISC7_Msk                          /*!<semaphore 7 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC8_Pos       (8U)

+#define HSEM_C1ICR_ISC8_Msk       (0x1UL << HSEM_C1ICR_ISC8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1ICR_ISC8           HSEM_C1ICR_ISC8_Msk                          /*!<semaphore 8 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC9_Pos       (9U)

+#define HSEM_C1ICR_ISC9_Msk       (0x1UL << HSEM_C1ICR_ISC9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1ICR_ISC9           HSEM_C1ICR_ISC9_Msk                          /*!<semaphore 9 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC10_Pos      (10U)

+#define HSEM_C1ICR_ISC10_Msk      (0x1UL << HSEM_C1ICR_ISC10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1ICR_ISC10          HSEM_C1ICR_ISC10_Msk                         /*!<semaphore 10 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC11_Pos      (11U)

+#define HSEM_C1ICR_ISC11_Msk      (0x1UL << HSEM_C1ICR_ISC11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1ICR_ISC11          HSEM_C1ICR_ISC11_Msk                         /*!<semaphore 11 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC12_Pos      (12U)

+#define HSEM_C1ICR_ISC12_Msk      (0x1UL << HSEM_C1ICR_ISC12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1ICR_ISC12          HSEM_C1ICR_ISC12_Msk                         /*!<semaphore 12 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC13_Pos      (13U)

+#define HSEM_C1ICR_ISC13_Msk      (0x1UL << HSEM_C1ICR_ISC13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1ICR_ISC13          HSEM_C1ICR_ISC13_Msk                         /*!<semaphore 13 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC14_Pos      (14U)

+#define HSEM_C1ICR_ISC14_Msk      (0x1UL << HSEM_C1ICR_ISC14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1ICR_ISC14          HSEM_C1ICR_ISC14_Msk                         /*!<semaphore 14 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC15_Pos      (15U)

+#define HSEM_C1ICR_ISC15_Msk      (0x1UL << HSEM_C1ICR_ISC15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1ICR_ISC15          HSEM_C1ICR_ISC15_Msk                         /*!<semaphore 15 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC16_Pos      (16U)

+#define HSEM_C1ICR_ISC16_Msk      (0x1UL << HSEM_C1ICR_ISC16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1ICR_ISC16          HSEM_C1ICR_ISC16_Msk                         /*!<semaphore 16 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC17_Pos      (17U)

+#define HSEM_C1ICR_ISC17_Msk      (0x1UL << HSEM_C1ICR_ISC17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1ICR_ISC17          HSEM_C1ICR_ISC17_Msk                         /*!<semaphore 17 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC18_Pos      (18U)

+#define HSEM_C1ICR_ISC18_Msk      (0x1UL << HSEM_C1ICR_ISC18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1ICR_ISC18          HSEM_C1ICR_ISC18_Msk                         /*!<semaphore 18 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC19_Pos      (19U)

+#define HSEM_C1ICR_ISC19_Msk      (0x1UL << HSEM_C1ICR_ISC19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1ICR_ISC19          HSEM_C1ICR_ISC19_Msk                         /*!<semaphore 19 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC20_Pos      (20U)

+#define HSEM_C1ICR_ISC20_Msk      (0x1UL << HSEM_C1ICR_ISC20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1ICR_ISC20          HSEM_C1ICR_ISC20_Msk                         /*!<semaphore 20 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC21_Pos      (21U)

+#define HSEM_C1ICR_ISC21_Msk      (0x1UL << HSEM_C1ICR_ISC21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1ICR_ISC21          HSEM_C1ICR_ISC21_Msk                         /*!<semaphore 21 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC22_Pos      (22U)

+#define HSEM_C1ICR_ISC22_Msk      (0x1UL << HSEM_C1ICR_ISC22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1ICR_ISC22          HSEM_C1ICR_ISC22_Msk                         /*!<semaphore 22 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC23_Pos      (23U)

+#define HSEM_C1ICR_ISC23_Msk      (0x1UL << HSEM_C1ICR_ISC23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1ICR_ISC23          HSEM_C1ICR_ISC23_Msk                         /*!<semaphore 23 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC24_Pos      (24U)

+#define HSEM_C1ICR_ISC24_Msk      (0x1UL << HSEM_C1ICR_ISC24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1ICR_ISC24          HSEM_C1ICR_ISC24_Msk                         /*!<semaphore 24 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC25_Pos      (25U)

+#define HSEM_C1ICR_ISC25_Msk      (0x1UL << HSEM_C1ICR_ISC25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1ICR_ISC25          HSEM_C1ICR_ISC25_Msk                         /*!<semaphore 25 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC26_Pos      (26U)

+#define HSEM_C1ICR_ISC26_Msk      (0x1UL << HSEM_C1ICR_ISC26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1ICR_ISC26          HSEM_C1ICR_ISC26_Msk                         /*!<semaphore 26 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC27_Pos      (27U)

+#define HSEM_C1ICR_ISC27_Msk      (0x1UL << HSEM_C1ICR_ISC27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1ICR_ISC27          HSEM_C1ICR_ISC27_Msk                         /*!<semaphore 27 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC28_Pos      (28U)

+#define HSEM_C1ICR_ISC28_Msk      (0x1UL << HSEM_C1ICR_ISC28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1ICR_ISC28          HSEM_C1ICR_ISC28_Msk                         /*!<semaphore 28 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC29_Pos      (29U)

+#define HSEM_C1ICR_ISC29_Msk      (0x1UL << HSEM_C1ICR_ISC29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1ICR_ISC29          HSEM_C1ICR_ISC29_Msk                         /*!<semaphore 29 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC30_Pos      (30U)

+#define HSEM_C1ICR_ISC30_Msk      (0x1UL << HSEM_C1ICR_ISC30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1ICR_ISC30          HSEM_C1ICR_ISC30_Msk                         /*!<semaphore 30 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC31_Pos      (31U)

+#define HSEM_C1ICR_ISC31_Msk      (0x1UL << HSEM_C1ICR_ISC31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1ICR_ISC31          HSEM_C1ICR_ISC31_Msk                         /*!<semaphore 31 interrupt 0 clear bit. */

+

+/********************  Bit definition for HSEM_C1ISR register  *****************/

+#define HSEM_C1ISR_ISF0_Pos       (0U)

+#define HSEM_C1ISR_ISF0_Msk       (0x1UL << HSEM_C1ISR_ISF0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1ISR_ISF0           HSEM_C1ISR_ISF0_Msk                          /*!<semaphore 0 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF1_Pos       (1U)

+#define HSEM_C1ISR_ISF1_Msk       (0x1UL << HSEM_C1ISR_ISF1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1ISR_ISF1           HSEM_C1ISR_ISF1_Msk                          /*!<semaphore 1 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF2_Pos       (2U)

+#define HSEM_C1ISR_ISF2_Msk       (0x1UL << HSEM_C1ISR_ISF2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1ISR_ISF2           HSEM_C1ISR_ISF2_Msk                          /*!<semaphore 2 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF3_Pos       (3U)

+#define HSEM_C1ISR_ISF3_Msk       (0x1UL << HSEM_C1ISR_ISF3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1ISR_ISF3           HSEM_C1ISR_ISF3_Msk                          /*!<semaphore 3 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF4_Pos       (4U)

+#define HSEM_C1ISR_ISF4_Msk       (0x1UL << HSEM_C1ISR_ISF4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1ISR_ISF4           HSEM_C1ISR_ISF4_Msk                          /*!<semaphore 4 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF5_Pos       (5U)

+#define HSEM_C1ISR_ISF5_Msk       (0x1UL << HSEM_C1ISR_ISF5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1ISR_ISF5           HSEM_C1ISR_ISF5_Msk                          /*!<semaphore 5 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF6_Pos       (6U)

+#define HSEM_C1ISR_ISF6_Msk       (0x1UL << HSEM_C1ISR_ISF6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1ISR_ISF6           HSEM_C1ISR_ISF6_Msk                          /*!<semaphore 6 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF7_Pos       (7U)

+#define HSEM_C1ISR_ISF7_Msk       (0x1UL << HSEM_C1ISR_ISF7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1ISR_ISF7           HSEM_C1ISR_ISF7_Msk                          /*!<semaphore 7 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF8_Pos       (8U)

+#define HSEM_C1ISR_ISF8_Msk       (0x1UL << HSEM_C1ISR_ISF8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1ISR_ISF8           HSEM_C1ISR_ISF8_Msk                          /*!<semaphore 8 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF9_Pos       (9U)

+#define HSEM_C1ISR_ISF9_Msk       (0x1UL << HSEM_C1ISR_ISF9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1ISR_ISF9           HSEM_C1ISR_ISF9_Msk                          /*!<semaphore 9 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF10_Pos      (10U)

+#define HSEM_C1ISR_ISF10_Msk      (0x1UL << HSEM_C1ISR_ISF10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1ISR_ISF10          HSEM_C1ISR_ISF10_Msk                         /*!<semaphore 10 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF11_Pos      (11U)

+#define HSEM_C1ISR_ISF11_Msk      (0x1UL << HSEM_C1ISR_ISF11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1ISR_ISF11          HSEM_C1ISR_ISF11_Msk                         /*!<semaphore 11 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF12_Pos      (12U)

+#define HSEM_C1ISR_ISF12_Msk      (0x1UL << HSEM_C1ISR_ISF12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1ISR_ISF12          HSEM_C1ISR_ISF12_Msk                         /*!<semaphore 12 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF13_Pos      (13U)

+#define HSEM_C1ISR_ISF13_Msk      (0x1UL << HSEM_C1ISR_ISF13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1ISR_ISF13          HSEM_C1ISR_ISF13_Msk                         /*!<semaphore 13 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF14_Pos      (14U)

+#define HSEM_C1ISR_ISF14_Msk      (0x1UL << HSEM_C1ISR_ISF14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1ISR_ISF14          HSEM_C1ISR_ISF14_Msk                         /*!<semaphore 14 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF15_Pos      (15U)

+#define HSEM_C1ISR_ISF15_Msk      (0x1UL << HSEM_C1ISR_ISF15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1ISR_ISF15          HSEM_C1ISR_ISF15_Msk                         /*!<semaphore 15 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF16_Pos      (16U)

+#define HSEM_C1ISR_ISF16_Msk      (0x1UL << HSEM_C1ISR_ISF16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1ISR_ISF16          HSEM_C1ISR_ISF16_Msk                         /*!<semaphore 16 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF17_Pos      (17U)

+#define HSEM_C1ISR_ISF17_Msk      (0x1UL << HSEM_C1ISR_ISF17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1ISR_ISF17          HSEM_C1ISR_ISF17_Msk                         /*!<semaphore 17 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF18_Pos      (18U)

+#define HSEM_C1ISR_ISF18_Msk      (0x1UL << HSEM_C1ISR_ISF18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1ISR_ISF18          HSEM_C1ISR_ISF18_Msk                         /*!<semaphore 18 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF19_Pos      (19U)

+#define HSEM_C1ISR_ISF19_Msk      (0x1UL << HSEM_C1ISR_ISF19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1ISR_ISF19          HSEM_C1ISR_ISF19_Msk                         /*!<semaphore 19 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF20_Pos      (20U)

+#define HSEM_C1ISR_ISF20_Msk      (0x1UL << HSEM_C1ISR_ISF20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1ISR_ISF20          HSEM_C1ISR_ISF20_Msk                         /*!<semaphore 20 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF21_Pos      (21U)

+#define HSEM_C1ISR_ISF21_Msk      (0x1UL << HSEM_C1ISR_ISF21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1ISR_ISF21          HSEM_C1ISR_ISF21_Msk                         /*!<semaphore 21 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF22_Pos      (22U)

+#define HSEM_C1ISR_ISF22_Msk      (0x1UL << HSEM_C1ISR_ISF22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1ISR_ISF22          HSEM_C1ISR_ISF22_Msk                         /*!<semaphore 22 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF23_Pos      (23U)

+#define HSEM_C1ISR_ISF23_Msk      (0x1UL << HSEM_C1ISR_ISF23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1ISR_ISF23          HSEM_C1ISR_ISF23_Msk                         /*!<semaphore 23 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF24_Pos      (24U)

+#define HSEM_C1ISR_ISF24_Msk      (0x1UL << HSEM_C1ISR_ISF24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1ISR_ISF24          HSEM_C1ISR_ISF24_Msk                         /*!<semaphore 24 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF25_Pos      (25U)

+#define HSEM_C1ISR_ISF25_Msk      (0x1UL << HSEM_C1ISR_ISF25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1ISR_ISF25          HSEM_C1ISR_ISF25_Msk                         /*!<semaphore 25 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF26_Pos      (26U)

+#define HSEM_C1ISR_ISF26_Msk      (0x1UL << HSEM_C1ISR_ISF26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1ISR_ISF26          HSEM_C1ISR_ISF26_Msk                         /*!<semaphore 26 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF27_Pos      (27U)

+#define HSEM_C1ISR_ISF27_Msk      (0x1UL << HSEM_C1ISR_ISF27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1ISR_ISF27          HSEM_C1ISR_ISF27_Msk                         /*!<semaphore 27 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF28_Pos      (28U)

+#define HSEM_C1ISR_ISF28_Msk      (0x1UL << HSEM_C1ISR_ISF28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1ISR_ISF28          HSEM_C1ISR_ISF28_Msk                         /*!<semaphore 28 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF29_Pos      (29U)

+#define HSEM_C1ISR_ISF29_Msk      (0x1UL << HSEM_C1ISR_ISF29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1ISR_ISF29          HSEM_C1ISR_ISF29_Msk                         /*!<semaphore 29 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF30_Pos      (30U)

+#define HSEM_C1ISR_ISF30_Msk      (0x1UL << HSEM_C1ISR_ISF30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1ISR_ISF30          HSEM_C1ISR_ISF30_Msk                         /*!<semaphore 30 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF31_Pos      (31U)

+#define HSEM_C1ISR_ISF31_Msk      (0x1UL << HSEM_C1ISR_ISF31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1ISR_ISF31          HSEM_C1ISR_ISF31_Msk                         /*!<semaphore 31 interrupt 0 status bit. */

+

+/********************  Bit definition for HSEM_C1MISR register  *****************/

+#define HSEM_C1MISR_MISF0_Pos     (0U)

+#define HSEM_C1MISR_MISF0_Msk     (0x1UL << HSEM_C1MISR_MISF0_Pos)             /*!< 0x00000001 */

+#define HSEM_C1MISR_MISF0         HSEM_C1MISR_MISF0_Msk                        /*!<semaphore 0 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF1_Pos     (1U)

+#define HSEM_C1MISR_MISF1_Msk     (0x1UL << HSEM_C1MISR_MISF1_Pos)             /*!< 0x00000002 */

+#define HSEM_C1MISR_MISF1         HSEM_C1MISR_MISF1_Msk                        /*!<semaphore 1 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF2_Pos     (2U)

+#define HSEM_C1MISR_MISF2_Msk     (0x1UL << HSEM_C1MISR_MISF2_Pos)             /*!< 0x00000004 */

+#define HSEM_C1MISR_MISF2         HSEM_C1MISR_MISF2_Msk                        /*!<semaphore 2 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF3_Pos     (3U)

+#define HSEM_C1MISR_MISF3_Msk     (0x1UL << HSEM_C1MISR_MISF3_Pos)             /*!< 0x00000008 */

+#define HSEM_C1MISR_MISF3         HSEM_C1MISR_MISF3_Msk                        /*!<semaphore 3 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF4_Pos     (4U)

+#define HSEM_C1MISR_MISF4_Msk     (0x1UL << HSEM_C1MISR_MISF4_Pos)             /*!< 0x00000010 */

+#define HSEM_C1MISR_MISF4         HSEM_C1MISR_MISF4_Msk                        /*!<semaphore 4 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF5_Pos     (5U)

+#define HSEM_C1MISR_MISF5_Msk     (0x1UL << HSEM_C1MISR_MISF5_Pos)             /*!< 0x00000020 */

+#define HSEM_C1MISR_MISF5         HSEM_C1MISR_MISF5_Msk                        /*!<semaphore 5 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF6_Pos     (6U)

+#define HSEM_C1MISR_MISF6_Msk     (0x1UL << HSEM_C1MISR_MISF6_Pos)             /*!< 0x00000040 */

+#define HSEM_C1MISR_MISF6         HSEM_C1MISR_MISF6_Msk                        /*!<semaphore 6 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF7_Pos     (7U)

+#define HSEM_C1MISR_MISF7_Msk     (0x1UL << HSEM_C1MISR_MISF7_Pos)             /*!< 0x00000080 */

+#define HSEM_C1MISR_MISF7         HSEM_C1MISR_MISF7_Msk                        /*!<semaphore 7 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF8_Pos     (8U)

+#define HSEM_C1MISR_MISF8_Msk     (0x1UL << HSEM_C1MISR_MISF8_Pos)             /*!< 0x00000100 */

+#define HSEM_C1MISR_MISF8         HSEM_C1MISR_MISF8_Msk                        /*!<semaphore 8 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF9_Pos     (9U)

+#define HSEM_C1MISR_MISF9_Msk     (0x1UL << HSEM_C1MISR_MISF9_Pos)             /*!< 0x00000200 */

+#define HSEM_C1MISR_MISF9         HSEM_C1MISR_MISF9_Msk                        /*!<semaphore 9 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF10_Pos    (10U)

+#define HSEM_C1MISR_MISF10_Msk    (0x1UL << HSEM_C1MISR_MISF10_Pos)            /*!< 0x00000400 */

+#define HSEM_C1MISR_MISF10        HSEM_C1MISR_MISF10_Msk                       /*!<semaphore 10 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF11_Pos    (11U)

+#define HSEM_C1MISR_MISF11_Msk    (0x1UL << HSEM_C1MISR_MISF11_Pos)            /*!< 0x00000800 */

+#define HSEM_C1MISR_MISF11        HSEM_C1MISR_MISF11_Msk                       /*!<semaphore 11 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF12_Pos    (12U)

+#define HSEM_C1MISR_MISF12_Msk    (0x1UL << HSEM_C1MISR_MISF12_Pos)            /*!< 0x00001000 */

+#define HSEM_C1MISR_MISF12        HSEM_C1MISR_MISF12_Msk                       /*!<semaphore 12 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF13_Pos    (13U)

+#define HSEM_C1MISR_MISF13_Msk    (0x1UL << HSEM_C1MISR_MISF13_Pos)            /*!< 0x00002000 */

+#define HSEM_C1MISR_MISF13        HSEM_C1MISR_MISF13_Msk                       /*!<semaphore 13 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF14_Pos    (14U)

+#define HSEM_C1MISR_MISF14_Msk    (0x1UL << HSEM_C1MISR_MISF14_Pos)            /*!< 0x00004000 */

+#define HSEM_C1MISR_MISF14        HSEM_C1MISR_MISF14_Msk                       /*!<semaphore 14 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF15_Pos    (15U)

+#define HSEM_C1MISR_MISF15_Msk    (0x1UL << HSEM_C1MISR_MISF15_Pos)            /*!< 0x00008000 */

+#define HSEM_C1MISR_MISF15        HSEM_C1MISR_MISF15_Msk                       /*!<semaphore 15 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF16_Pos    (16U)

+#define HSEM_C1MISR_MISF16_Msk    (0x1UL << HSEM_C1MISR_MISF16_Pos)            /*!< 0x00010000 */

+#define HSEM_C1MISR_MISF16        HSEM_C1MISR_MISF16_Msk                       /*!<semaphore 16 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF17_Pos    (17U)

+#define HSEM_C1MISR_MISF17_Msk    (0x1UL << HSEM_C1MISR_MISF17_Pos)            /*!< 0x00020000 */

+#define HSEM_C1MISR_MISF17        HSEM_C1MISR_MISF17_Msk                       /*!<semaphore 17 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF18_Pos    (18U)

+#define HSEM_C1MISR_MISF18_Msk    (0x1UL << HSEM_C1MISR_MISF18_Pos)            /*!< 0x00040000 */

+#define HSEM_C1MISR_MISF18        HSEM_C1MISR_MISF18_Msk                       /*!<semaphore 18 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF19_Pos    (19U)

+#define HSEM_C1MISR_MISF19_Msk    (0x1UL << HSEM_C1MISR_MISF19_Pos)            /*!< 0x00080000 */

+#define HSEM_C1MISR_MISF19        HSEM_C1MISR_MISF19_Msk                       /*!<semaphore 19 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF20_Pos    (20U)

+#define HSEM_C1MISR_MISF20_Msk    (0x1UL << HSEM_C1MISR_MISF20_Pos)            /*!< 0x00100000 */

+#define HSEM_C1MISR_MISF20        HSEM_C1MISR_MISF20_Msk                       /*!<semaphore 20 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF21_Pos    (21U)

+#define HSEM_C1MISR_MISF21_Msk    (0x1UL << HSEM_C1MISR_MISF21_Pos)            /*!< 0x00200000 */

+#define HSEM_C1MISR_MISF21        HSEM_C1MISR_MISF21_Msk                       /*!<semaphore 21 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF22_Pos    (22U)

+#define HSEM_C1MISR_MISF22_Msk    (0x1UL << HSEM_C1MISR_MISF22_Pos)            /*!< 0x00400000 */

+#define HSEM_C1MISR_MISF22        HSEM_C1MISR_MISF22_Msk                       /*!<semaphore 22 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF23_Pos    (23U)

+#define HSEM_C1MISR_MISF23_Msk    (0x1UL << HSEM_C1MISR_MISF23_Pos)            /*!< 0x00800000 */

+#define HSEM_C1MISR_MISF23        HSEM_C1MISR_MISF23_Msk                       /*!<semaphore 23 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF24_Pos    (24U)

+#define HSEM_C1MISR_MISF24_Msk    (0x1UL << HSEM_C1MISR_MISF24_Pos)            /*!< 0x01000000 */

+#define HSEM_C1MISR_MISF24        HSEM_C1MISR_MISF24_Msk                       /*!<semaphore 24 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF25_Pos    (25U)

+#define HSEM_C1MISR_MISF25_Msk    (0x1UL << HSEM_C1MISR_MISF25_Pos)            /*!< 0x02000000 */

+#define HSEM_C1MISR_MISF25        HSEM_C1MISR_MISF25_Msk                       /*!<semaphore 25 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF26_Pos    (26U)

+#define HSEM_C1MISR_MISF26_Msk    (0x1UL << HSEM_C1MISR_MISF26_Pos)            /*!< 0x04000000 */

+#define HSEM_C1MISR_MISF26        HSEM_C1MISR_MISF26_Msk                       /*!<semaphore 26 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF27_Pos    (27U)

+#define HSEM_C1MISR_MISF27_Msk    (0x1UL << HSEM_C1MISR_MISF27_Pos)            /*!< 0x08000000 */

+#define HSEM_C1MISR_MISF27        HSEM_C1MISR_MISF27_Msk                       /*!<semaphore 27 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF28_Pos    (28U)

+#define HSEM_C1MISR_MISF28_Msk    (0x1UL << HSEM_C1MISR_MISF28_Pos)            /*!< 0x10000000 */

+#define HSEM_C1MISR_MISF28        HSEM_C1MISR_MISF28_Msk                       /*!<semaphore 28 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF29_Pos    (29U)

+#define HSEM_C1MISR_MISF29_Msk    (0x1UL << HSEM_C1MISR_MISF29_Pos)            /*!< 0x20000000 */

+#define HSEM_C1MISR_MISF29        HSEM_C1MISR_MISF29_Msk                       /*!<semaphore 29 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF30_Pos    (30U)

+#define HSEM_C1MISR_MISF30_Msk    (0x1UL << HSEM_C1MISR_MISF30_Pos)            /*!< 0x40000000 */

+#define HSEM_C1MISR_MISF30        HSEM_C1MISR_MISF30_Msk                       /*!<semaphore 30 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF31_Pos    (31U)

+#define HSEM_C1MISR_MISF31_Msk    (0x1UL << HSEM_C1MISR_MISF31_Pos)            /*!< 0x80000000 */

+#define HSEM_C1MISR_MISF31        HSEM_C1MISR_MISF31_Msk                       /*!<semaphore 31 interrupt 0 masked status bit. */

+

+/********************  Bit definition for HSEM_CR register  *****************/

+#define HSEM_CR_COREID_Pos        (8U)

+#define HSEM_CR_COREID_Msk        (0xFFUL << HSEM_CR_COREID_Pos)               /*!< 0x0000FF00 */

+#define HSEM_CR_COREID            HSEM_CR_COREID_Msk                           /*!<CoreID of semaphores to be cleared. */

+#define HSEM_CR_KEY_Pos           (16U)

+#define HSEM_CR_KEY_Msk           (0xFFFFUL << HSEM_CR_KEY_Pos)                /*!< 0xFFFF0000 */

+#define HSEM_CR_KEY               HSEM_CR_KEY_Msk                              /*!<semaphores clear key. */

+

+/********************  Bit definition for HSEM_KEYR register  *****************/

+#define HSEM_KEYR_KEY_Pos         (16U)

+#define HSEM_KEYR_KEY_Msk         (0xFFFFUL << HSEM_KEYR_KEY_Pos)              /*!< 0xFFFF0000 */

+#define HSEM_KEYR_KEY             HSEM_KEYR_KEY_Msk                            /*!<semaphores clear key. */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    HASH                                    */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bits definition for HASH_CR register  ********************/

+#define HASH_CR_INIT_Pos          (2U)

+#define HASH_CR_INIT_Msk          (0x1UL << HASH_CR_INIT_Pos)                  /*!< 0x00000004 */

+#define HASH_CR_INIT              HASH_CR_INIT_Msk

+#define HASH_CR_DMAE_Pos          (3U)

+#define HASH_CR_DMAE_Msk          (0x1UL << HASH_CR_DMAE_Pos)                  /*!< 0x00000008 */

+#define HASH_CR_DMAE              HASH_CR_DMAE_Msk

+#define HASH_CR_DATATYPE_Pos      (4U)

+#define HASH_CR_DATATYPE_Msk      (0x3UL << HASH_CR_DATATYPE_Pos)              /*!< 0x00000030 */

+#define HASH_CR_DATATYPE          HASH_CR_DATATYPE_Msk

+#define HASH_CR_DATATYPE_0        (0x1UL << HASH_CR_DATATYPE_Pos)               /*!< 0x00000010 */

+#define HASH_CR_DATATYPE_1        (0x2UL << HASH_CR_DATATYPE_Pos)               /*!< 0x00000020 */

+#define HASH_CR_MODE_Pos          (6U)

+#define HASH_CR_MODE_Msk          (0x1UL << HASH_CR_MODE_Pos)                  /*!< 0x00000040 */

+#define HASH_CR_MODE              HASH_CR_MODE_Msk

+#define HASH_CR_ALGO_Pos          (7U)

+#define HASH_CR_ALGO_Msk          (0x801UL << HASH_CR_ALGO_Pos)                /*!< 0x00040080 */

+#define HASH_CR_ALGO              HASH_CR_ALGO_Msk

+#define HASH_CR_ALGO_0            (0x001UL << HASH_CR_ALGO_Pos)                 /*!< 0x00000080 */

+#define HASH_CR_ALGO_1            (0x800UL << HASH_CR_ALGO_Pos)                 /*!< 0x00040000 */

+#define HASH_CR_NBW_Pos           (8U)

+#define HASH_CR_NBW_Msk           (0xFUL << HASH_CR_NBW_Pos)                   /*!< 0x00000F00 */

+#define HASH_CR_NBW               HASH_CR_NBW_Msk

+#define HASH_CR_NBW_0             (0x1UL << HASH_CR_NBW_Pos)                    /*!< 0x00000100 */

+#define HASH_CR_NBW_1             (0x2UL << HASH_CR_NBW_Pos)                    /*!< 0x00000200 */

+#define HASH_CR_NBW_2             (0x4UL << HASH_CR_NBW_Pos)                    /*!< 0x00000400 */

+#define HASH_CR_NBW_3             (0x8UL << HASH_CR_NBW_Pos)                    /*!< 0x00000800 */

+#define HASH_CR_DINNE_Pos         (12U)

+#define HASH_CR_DINNE_Msk         (0x1UL << HASH_CR_DINNE_Pos)                 /*!< 0x00001000 */

+#define HASH_CR_DINNE             HASH_CR_DINNE_Msk

+#define HASH_CR_MDMAT_Pos         (13U)

+#define HASH_CR_MDMAT_Msk         (0x1UL << HASH_CR_MDMAT_Pos)                 /*!< 0x00002000 */

+#define HASH_CR_MDMAT             HASH_CR_MDMAT_Msk

+#define HASH_CR_LKEY_Pos          (16U)

+#define HASH_CR_LKEY_Msk          (0x1UL << HASH_CR_LKEY_Pos)                  /*!< 0x00010000 */

+#define HASH_CR_LKEY              HASH_CR_LKEY_Msk

+

+/******************  Bits definition for HASH_STR register  *******************/

+#define HASH_STR_NBLW_Pos         (0U)

+#define HASH_STR_NBLW_Msk         (0x1FUL << HASH_STR_NBLW_Pos)                /*!< 0x0000001F */

+#define HASH_STR_NBLW             HASH_STR_NBLW_Msk

+#define HASH_STR_NBLW_0           (0x01UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000001 */

+#define HASH_STR_NBLW_1           (0x02UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000002 */

+#define HASH_STR_NBLW_2           (0x04UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000004 */

+#define HASH_STR_NBLW_3           (0x08UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000008 */

+#define HASH_STR_NBLW_4           (0x10UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000010 */

+#define HASH_STR_DCAL_Pos         (8U)

+#define HASH_STR_DCAL_Msk         (0x1UL << HASH_STR_DCAL_Pos)                 /*!< 0x00000100 */

+#define HASH_STR_DCAL             HASH_STR_DCAL_Msk

+

+/******************  Bits definition for HASH_IMR register  *******************/

+#define HASH_IMR_DINIE_Pos        (0U)

+#define HASH_IMR_DINIE_Msk        (0x1UL << HASH_IMR_DINIE_Pos)                /*!< 0x00000001 */

+#define HASH_IMR_DINIE            HASH_IMR_DINIE_Msk

+#define HASH_IMR_DCIE_Pos         (1U)

+#define HASH_IMR_DCIE_Msk         (0x1UL << HASH_IMR_DCIE_Pos)                 /*!< 0x00000002 */

+#define HASH_IMR_DCIE             HASH_IMR_DCIE_Msk

+

+/******************  Bits definition for HASH_SR register  ********************/

+#define HASH_SR_DINIS_Pos         (0U)

+#define HASH_SR_DINIS_Msk         (0x1UL << HASH_SR_DINIS_Pos)                 /*!< 0x00000001 */

+#define HASH_SR_DINIS             HASH_SR_DINIS_Msk

+#define HASH_SR_DCIS_Pos          (1U)

+#define HASH_SR_DCIS_Msk          (0x1UL << HASH_SR_DCIS_Pos)                  /*!< 0x00000002 */

+#define HASH_SR_DCIS              HASH_SR_DCIS_Msk

+#define HASH_SR_DMAS_Pos          (2U)

+#define HASH_SR_DMAS_Msk          (0x1UL << HASH_SR_DMAS_Pos)                  /*!< 0x00000004 */

+#define HASH_SR_DMAS              HASH_SR_DMAS_Msk

+#define HASH_SR_BUSY_Pos          (3U)

+#define HASH_SR_BUSY_Msk          (0x1UL << HASH_SR_BUSY_Pos)                  /*!< 0x00000008 */

+#define HASH_SR_BUSY              HASH_SR_BUSY_Msk

+/******************************************************************************/

+/*                                                                            */

+/*                      Inter-integrated Circuit Interface (I2C)              */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for I2C_CR1 register  *******************/

+#define I2C_CR1_PE_Pos               (0U)

+#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */

+#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */

+#define I2C_CR1_TXIE_Pos             (1U)

+#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */

+#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */

+#define I2C_CR1_RXIE_Pos             (2U)

+#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */

+#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */

+#define I2C_CR1_ADDRIE_Pos           (3U)

+#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */

+#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */

+#define I2C_CR1_NACKIE_Pos           (4U)

+#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */

+#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */

+#define I2C_CR1_STOPIE_Pos           (5U)

+#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */

+#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */

+#define I2C_CR1_TCIE_Pos             (6U)

+#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */

+#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */

+#define I2C_CR1_ERRIE_Pos            (7U)

+#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */

+#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */

+#define I2C_CR1_DNF_Pos              (8U)

+#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */

+#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */

+#define I2C_CR1_ANFOFF_Pos           (12U)

+#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */

+#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */

+#define I2C_CR1_TXDMAEN_Pos          (14U)

+#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */

+#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */

+#define I2C_CR1_RXDMAEN_Pos          (15U)

+#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */

+#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */

+#define I2C_CR1_SBC_Pos              (16U)

+#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */

+#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */

+#define I2C_CR1_NOSTRETCH_Pos        (17U)

+#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */

+#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */

+#define I2C_CR1_WUPEN_Pos            (18U)

+#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */

+#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */

+#define I2C_CR1_GCEN_Pos             (19U)

+#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */

+#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */

+#define I2C_CR1_SMBHEN_Pos           (20U)

+#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */

+#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */

+#define I2C_CR1_SMBDEN_Pos           (21U)

+#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */

+#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */

+#define I2C_CR1_ALERTEN_Pos          (22U)

+#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */

+#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */

+#define I2C_CR1_PECEN_Pos            (23U)

+#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */

+#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */

+

+/******************  Bit definition for I2C_CR2 register  ********************/

+#define I2C_CR2_SADD_Pos             (0U)

+#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */

+#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */

+#define I2C_CR2_RD_WRN_Pos           (10U)

+#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */

+#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */

+#define I2C_CR2_ADD10_Pos            (11U)

+#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */

+#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */

+#define I2C_CR2_HEAD10R_Pos          (12U)

+#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */

+#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */

+#define I2C_CR2_START_Pos            (13U)

+#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */

+#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */

+#define I2C_CR2_STOP_Pos             (14U)

+#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */

+#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */

+#define I2C_CR2_NACK_Pos             (15U)

+#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */

+#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */

+#define I2C_CR2_NBYTES_Pos           (16U)

+#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */

+#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */

+#define I2C_CR2_RELOAD_Pos           (24U)

+#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */

+#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */

+#define I2C_CR2_AUTOEND_Pos          (25U)

+#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */

+#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */

+#define I2C_CR2_PECBYTE_Pos          (26U)

+#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */

+#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */

+

+/*******************  Bit definition for I2C_OAR1 register  ******************/

+#define I2C_OAR1_OA1_Pos             (0U)

+#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */

+#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */

+#define I2C_OAR1_OA1MODE_Pos         (10U)

+#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */

+#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */

+#define I2C_OAR1_OA1EN_Pos           (15U)

+#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */

+#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */

+

+/*******************  Bit definition for I2C_OAR2 register  ******************/

+#define I2C_OAR2_OA2_Pos             (1U)

+#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */

+#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */

+#define I2C_OAR2_OA2MSK_Pos          (8U)

+#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */

+#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */

+#define I2C_OAR2_OA2NOMASK           0x00000000UL                              /*!< No mask */

+#define I2C_OAR2_OA2MASK01_Pos       (8U)

+#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */

+#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared */

+#define I2C_OAR2_OA2MASK02_Pos       (9U)

+#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */

+#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */

+#define I2C_OAR2_OA2MASK03_Pos       (8U)

+#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */

+#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */

+#define I2C_OAR2_OA2MASK04_Pos       (10U)

+#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */

+#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */

+#define I2C_OAR2_OA2MASK05_Pos       (8U)

+#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */

+#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */

+#define I2C_OAR2_OA2MASK06_Pos       (9U)

+#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */

+#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared */

+#define I2C_OAR2_OA2MASK07_Pos       (8U)

+#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */

+#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done */

+#define I2C_OAR2_OA2EN_Pos           (15U)

+#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */

+#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */

+

+/*******************  Bit definition for I2C_TIMINGR register *******************/

+#define I2C_TIMINGR_SCLL_Pos         (0U)

+#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */

+#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */

+#define I2C_TIMINGR_SCLH_Pos         (8U)

+#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */

+#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */

+#define I2C_TIMINGR_SDADEL_Pos       (16U)

+#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */

+#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */

+#define I2C_TIMINGR_SCLDEL_Pos       (20U)

+#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */

+#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */

+#define I2C_TIMINGR_PRESC_Pos        (28U)

+#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */

+#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */

+

+/******************* Bit definition for I2C_TIMEOUTR register *******************/

+#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)

+#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */

+#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */

+#define I2C_TIMEOUTR_TIDLE_Pos       (12U)

+#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */

+#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */

+#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)

+#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */

+#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */

+#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)

+#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */

+#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/

+#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)

+#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */

+#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */

+

+/******************  Bit definition for I2C_ISR register  *********************/

+#define I2C_ISR_TXE_Pos              (0U)

+#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */

+#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */

+#define I2C_ISR_TXIS_Pos             (1U)

+#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */

+#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */

+#define I2C_ISR_RXNE_Pos             (2U)

+#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */

+#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */

+#define I2C_ISR_ADDR_Pos             (3U)

+#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */

+#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/

+#define I2C_ISR_NACKF_Pos            (4U)

+#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */

+#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */

+#define I2C_ISR_STOPF_Pos            (5U)

+#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */

+#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */

+#define I2C_ISR_TC_Pos               (6U)

+#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */

+#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */

+#define I2C_ISR_TCR_Pos              (7U)

+#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */

+#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */

+#define I2C_ISR_BERR_Pos             (8U)

+#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */

+#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */

+#define I2C_ISR_ARLO_Pos             (9U)

+#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */

+#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */

+#define I2C_ISR_OVR_Pos              (10U)

+#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */

+#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */

+#define I2C_ISR_PECERR_Pos           (11U)

+#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */

+#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */

+#define I2C_ISR_TIMEOUT_Pos          (12U)

+#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */

+#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */

+#define I2C_ISR_ALERT_Pos            (13U)

+#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */

+#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */

+#define I2C_ISR_BUSY_Pos             (15U)

+#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */

+#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */

+#define I2C_ISR_DIR_Pos              (16U)

+#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */

+#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */

+#define I2C_ISR_ADDCODE_Pos          (17U)

+#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */

+#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */

+

+/******************  Bit definition for I2C_ICR register  *********************/

+#define I2C_ICR_ADDRCF_Pos           (3U)

+#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */

+#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */

+#define I2C_ICR_NACKCF_Pos           (4U)

+#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */

+#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */

+#define I2C_ICR_STOPCF_Pos           (5U)

+#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */

+#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */

+#define I2C_ICR_BERRCF_Pos           (8U)

+#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */

+#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */

+#define I2C_ICR_ARLOCF_Pos           (9U)

+#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */

+#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */

+#define I2C_ICR_OVRCF_Pos            (10U)

+#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */

+#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */

+#define I2C_ICR_PECCF_Pos            (11U)

+#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */

+#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */

+#define I2C_ICR_TIMOUTCF_Pos         (12U)

+#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */

+#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */

+#define I2C_ICR_ALERTCF_Pos          (13U)

+#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */

+#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */

+

+/******************  Bit definition for I2C_PECR register  *********************/

+#define I2C_PECR_PEC_Pos             (0U)

+#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */

+#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */

+

+/******************  Bit definition for I2C_RXDR register  *********************/

+#define I2C_RXDR_RXDATA_Pos          (0U)

+#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */

+#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */

+

+/******************  Bit definition for I2C_TXDR register  *********************/

+#define I2C_TXDR_TXDATA_Pos          (0U)

+#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */

+#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           Independent WATCHDOG                             */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for IWDG_KR register  ********************/

+#define IWDG_KR_KEY_Pos      (0U)

+#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */

+#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */

+

+/*******************  Bit definition for IWDG_PR register  ********************/

+#define IWDG_PR_PR_Pos       (0U)

+#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */

+#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */

+#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */

+#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */

+#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */

+

+/*******************  Bit definition for IWDG_RLR register  *******************/

+#define IWDG_RLR_RL_Pos      (0U)

+#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */

+#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */

+

+/*******************  Bit definition for IWDG_SR register  ********************/

+#define IWDG_SR_PVU_Pos      (0U)

+#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */

+#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */

+#define IWDG_SR_RVU_Pos      (1U)

+#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */

+#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */

+#define IWDG_SR_WVU_Pos      (2U)

+#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */

+#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */

+

+/*******************  Bit definition for IWDG_KR register  ********************/

+#define IWDG_WINR_WIN_Pos    (0U)

+#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */

+#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */

+

+/******************************************************************************/

+/*                                                                            */

+/*                        JPEG Encoder/Decoder                                */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for CONFR0 register  ********************/

+#define JPEG_CONFR0_START_Pos           (0U)

+#define JPEG_CONFR0_START_Msk           (0x1UL << JPEG_CONFR0_START_Pos)       /*!< 0x00000001 */

+#define JPEG_CONFR0_START               JPEG_CONFR0_START_Msk                  /*!<Start/Stop bit */

+

+/********************  Bit definition for CONFR1 register  ********************/

+#define JPEG_CONFR1_NF_Pos              (0U)

+#define JPEG_CONFR1_NF_Msk              (0x3UL << JPEG_CONFR1_NF_Pos)          /*!< 0x00000003 */

+#define JPEG_CONFR1_NF                  JPEG_CONFR1_NF_Msk                     /*!<Number of color components */

+#define JPEG_CONFR1_NF_0                (0x1UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000001 */

+#define JPEG_CONFR1_NF_1                (0x2UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000002 */

+#define JPEG_CONFR1_DE_Pos              (3U)

+#define JPEG_CONFR1_DE_Msk              (0x1UL << JPEG_CONFR1_DE_Pos)          /*!< 0x00000008 */

+#define JPEG_CONFR1_DE                  JPEG_CONFR1_DE_Msk                     /*!<Decoding Enable */

+#define JPEG_CONFR1_COLORSPACE_Pos      (4U)

+#define JPEG_CONFR1_COLORSPACE_Msk      (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)  /*!< 0x00000030 */

+#define JPEG_CONFR1_COLORSPACE          JPEG_CONFR1_COLORSPACE_Msk             /*!<Color Space */

+#define JPEG_CONFR1_COLORSPACE_0        (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000010 */

+#define JPEG_CONFR1_COLORSPACE_1        (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000020 */

+#define JPEG_CONFR1_NS_Pos              (6U)

+#define JPEG_CONFR1_NS_Msk              (0x3UL << JPEG_CONFR1_NS_Pos)          /*!< 0x000000C0 */

+#define JPEG_CONFR1_NS                  JPEG_CONFR1_NS_Msk                     /*!<Number of components for Scan */

+#define JPEG_CONFR1_NS_0                (0x1UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR1_NS_1                (0x2UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR1_HDR_Pos             (8U)

+#define JPEG_CONFR1_HDR_Msk             (0x1UL << JPEG_CONFR1_HDR_Pos)         /*!< 0x00000100 */

+#define JPEG_CONFR1_HDR                 JPEG_CONFR1_HDR_Msk                    /*!<Header Processing On/Off */

+#define JPEG_CONFR1_YSIZE_Pos           (16U)

+#define JPEG_CONFR1_YSIZE_Msk           (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)    /*!< 0xFFFF0000 */

+#define JPEG_CONFR1_YSIZE               JPEG_CONFR1_YSIZE_Msk                  /*!<Number of lines in source image */

+

+/********************  Bit definition for CONFR2 register  ********************/

+#define JPEG_CONFR2_NMCU_Pos            (0U)

+#define JPEG_CONFR2_NMCU_Msk            (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)  /*!< 0x03FFFFFF */

+#define JPEG_CONFR2_NMCU                JPEG_CONFR2_NMCU_Msk                   /*!<Number of MCU units minus 1 to encode */

+

+/********************  Bit definition for CONFR3 register  ********************/

+#define JPEG_CONFR3_XSIZE_Pos           (16U)

+#define JPEG_CONFR3_XSIZE_Msk           (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)    /*!< 0xFFFF0000 */

+#define JPEG_CONFR3_XSIZE               JPEG_CONFR3_XSIZE_Msk                  /*!<Number of pixels per line */

+

+/********************  Bit definition for CONFR4 register  ********************/

+#define JPEG_CONFR4_HD_Pos              (0U)

+#define JPEG_CONFR4_HD_Msk              (0x1UL << JPEG_CONFR4_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR4_HD                  JPEG_CONFR4_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR4_HA_Pos              (1U)

+#define JPEG_CONFR4_HA_Msk              (0x1UL << JPEG_CONFR4_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR4_HA                  JPEG_CONFR4_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR4_QT_Pos              (2U)

+#define JPEG_CONFR4_QT_Msk              (0x3UL << JPEG_CONFR4_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR4_QT                  JPEG_CONFR4_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR4_QT_0                (0x1UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR4_QT_1                (0x2UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR4_NB_Pos              (4U)

+#define JPEG_CONFR4_NB_Msk              (0xFUL << JPEG_CONFR4_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR4_NB                  JPEG_CONFR4_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR4_NB_0                (0x1UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR4_NB_1                (0x2UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR4_NB_2                (0x4UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR4_NB_3                (0x8UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR4_VSF_Pos             (8U)

+#define JPEG_CONFR4_VSF_Msk             (0xFUL << JPEG_CONFR4_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR4_VSF                 JPEG_CONFR4_VSF_Msk                    /*!<Vertical sampling factor for component 1 */

+#define JPEG_CONFR4_VSF_0               (0x1UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR4_VSF_1               (0x2UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR4_VSF_2               (0x4UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR4_VSF_3               (0x8UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR4_HSF_Pos             (12U)

+#define JPEG_CONFR4_HSF_Msk             (0xFUL << JPEG_CONFR4_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR4_HSF                 JPEG_CONFR4_HSF_Msk                    /*!<Horizontal sampling factor for component 1 */

+#define JPEG_CONFR4_HSF_0               (0x1UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR4_HSF_1               (0x2UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR4_HSF_2               (0x4UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR4_HSF_3               (0x8UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR5 register  ********************/

+#define JPEG_CONFR5_HD_Pos              (0U)

+#define JPEG_CONFR5_HD_Msk              (0x1UL << JPEG_CONFR5_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR5_HD                  JPEG_CONFR5_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR5_HA_Pos              (1U)

+#define JPEG_CONFR5_HA_Msk              (0x1UL << JPEG_CONFR5_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR5_HA                  JPEG_CONFR5_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR5_QT_Pos              (2U)

+#define JPEG_CONFR5_QT_Msk              (0x3UL << JPEG_CONFR5_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR5_QT                  JPEG_CONFR5_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR5_QT_0                (0x1UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR5_QT_1                (0x2UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR5_NB_Pos              (4U)

+#define JPEG_CONFR5_NB_Msk              (0xFUL << JPEG_CONFR5_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR5_NB                  JPEG_CONFR5_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR5_NB_0                (0x1UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR5_NB_1                (0x2UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR5_NB_2                (0x4UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR5_NB_3                (0x8UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR5_VSF_Pos             (8U)

+#define JPEG_CONFR5_VSF_Msk             (0xFUL << JPEG_CONFR5_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR5_VSF                 JPEG_CONFR5_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR5_VSF_0               (0x1UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR5_VSF_1               (0x2UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR5_VSF_2               (0x4UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR5_VSF_3               (0x8UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR5_HSF_Pos             (12U)

+#define JPEG_CONFR5_HSF_Msk             (0xFUL << JPEG_CONFR5_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR5_HSF                 JPEG_CONFR5_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR5_HSF_0               (0x1UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR5_HSF_1               (0x2UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR5_HSF_2               (0x4UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR5_HSF_3               (0x8UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR6 register  ********************/

+#define JPEG_CONFR6_HD_Pos              (0U)

+#define JPEG_CONFR6_HD_Msk              (0x1UL << JPEG_CONFR6_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR6_HD                  JPEG_CONFR6_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR6_HA_Pos              (1U)

+#define JPEG_CONFR6_HA_Msk              (0x1UL << JPEG_CONFR6_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR6_HA                  JPEG_CONFR6_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR6_QT_Pos              (2U)

+#define JPEG_CONFR6_QT_Msk              (0x3UL << JPEG_CONFR6_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR6_QT                  JPEG_CONFR6_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR6_QT_0                (0x1UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR6_QT_1                (0x2UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR6_NB_Pos              (4U)

+#define JPEG_CONFR6_NB_Msk              (0xFUL << JPEG_CONFR6_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR6_NB                  JPEG_CONFR6_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR6_NB_0                (0x1UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR6_NB_1                (0x2UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR6_NB_2                (0x4UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR6_NB_3                (0x8UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR6_VSF_Pos             (8U)

+#define JPEG_CONFR6_VSF_Msk             (0xFUL << JPEG_CONFR6_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR6_VSF                 JPEG_CONFR6_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR6_VSF_0               (0x1UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR6_VSF_1               (0x2UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR6_VSF_2               (0x4UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR6_VSF_3               (0x8UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR6_HSF_Pos             (12U)

+#define JPEG_CONFR6_HSF_Msk             (0xFUL << JPEG_CONFR6_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR6_HSF                 JPEG_CONFR6_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR6_HSF_0               (0x1UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR6_HSF_1               (0x2UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR6_HSF_2               (0x4UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR6_HSF_3               (0x8UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR7 register  ********************/

+#define JPEG_CONFR7_HD_Pos              (0U)

+#define JPEG_CONFR7_HD_Msk              (0x1UL << JPEG_CONFR7_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR7_HD                  JPEG_CONFR7_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR7_HA_Pos              (1U)

+#define JPEG_CONFR7_HA_Msk              (0x1UL << JPEG_CONFR7_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR7_HA                  JPEG_CONFR7_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR7_QT_Pos              (2U)

+#define JPEG_CONFR7_QT_Msk              (0x3UL << JPEG_CONFR7_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR7_QT                  JPEG_CONFR7_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR7_QT_0                (0x1UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR7_QT_1                (0x2UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR7_NB_Pos              (4U)

+#define JPEG_CONFR7_NB_Msk              (0xFUL << JPEG_CONFR7_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR7_NB                  JPEG_CONFR7_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR7_NB_0                (0x1UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR7_NB_1                (0x2UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR7_NB_2                (0x4UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR7_NB_3                (0x8UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR7_VSF_Pos             (8U)

+#define JPEG_CONFR7_VSF_Msk             (0xFUL << JPEG_CONFR7_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR7_VSF                 JPEG_CONFR7_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR7_VSF_0               (0x1UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR7_VSF_1               (0x2UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR7_VSF_2               (0x4UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR7_VSF_3               (0x8UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR7_HSF_Pos             (12U)

+#define JPEG_CONFR7_HSF_Msk             (0xFUL << JPEG_CONFR7_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR7_HSF                 JPEG_CONFR7_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR7_HSF_0               (0x1UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR7_HSF_1               (0x2UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR7_HSF_2               (0x4UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR7_HSF_3               (0x8UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CR register  ********************/

+#define JPEG_CR_JCEN_Pos                (0U)

+#define JPEG_CR_JCEN_Msk                (0x1UL << JPEG_CR_JCEN_Pos)            /*!< 0x00000001 */

+#define JPEG_CR_JCEN                    JPEG_CR_JCEN_Msk                       /*!<Enable the JPEG Codec Core */

+#define JPEG_CR_IFTIE_Pos               (1U)

+#define JPEG_CR_IFTIE_Msk               (0x1UL << JPEG_CR_IFTIE_Pos)           /*!< 0x00000002 */

+#define JPEG_CR_IFTIE                   JPEG_CR_IFTIE_Msk                      /*!<Input FIFO Threshold Interrupt Enable */

+#define JPEG_CR_IFNFIE_Pos              (2U)

+#define JPEG_CR_IFNFIE_Msk              (0x1UL << JPEG_CR_IFNFIE_Pos)          /*!< 0x00000004 */

+#define JPEG_CR_IFNFIE                  JPEG_CR_IFNFIE_Msk                     /*!<Input FIFO Not Full Interrupt Enable */

+#define JPEG_CR_OFTIE_Pos               (3U)

+#define JPEG_CR_OFTIE_Msk               (0x1UL << JPEG_CR_OFTIE_Pos)           /*!< 0x00000008 */

+#define JPEG_CR_OFTIE                   JPEG_CR_OFTIE_Msk                      /*!<Output FIFO Threshold Interrupt Enable */

+#define JPEG_CR_OFNEIE_Pos              (4U)

+#define JPEG_CR_OFNEIE_Msk              (0x1UL << JPEG_CR_OFNEIE_Pos)          /*!< 0x00000010 */

+#define JPEG_CR_OFNEIE                  JPEG_CR_OFNEIE_Msk                     /*!<Output FIFO Not Empty Interrupt Enable */

+#define JPEG_CR_EOCIE_Pos               (5U)

+#define JPEG_CR_EOCIE_Msk               (0x1UL << JPEG_CR_EOCIE_Pos)           /*!< 0x00000020 */

+#define JPEG_CR_EOCIE                   JPEG_CR_EOCIE_Msk                      /*!<End of Conversion Interrupt Enable */

+#define JPEG_CR_HPDIE_Pos               (6U)

+#define JPEG_CR_HPDIE_Msk               (0x1UL << JPEG_CR_HPDIE_Pos)           /*!< 0x00000040 */

+#define JPEG_CR_HPDIE                   JPEG_CR_HPDIE_Msk                      /*!<Header Parsing Done Interrupt Enable */

+#define JPEG_CR_IFF_Pos                 (13U)

+#define JPEG_CR_IFF_Msk                 (0x1UL << JPEG_CR_IFF_Pos)             /*!< 0x00002000 */

+#define JPEG_CR_IFF                     JPEG_CR_IFF_Msk                        /*!<Flush the input FIFO */

+#define JPEG_CR_OFF_Pos                 (14U)

+#define JPEG_CR_OFF_Msk                 (0x1UL << JPEG_CR_OFF_Pos)             /*!< 0x00004000 */

+#define JPEG_CR_OFF                     JPEG_CR_OFF_Msk                        /*!<Flush the output FIFO */

+

+/********************  Bit definition for SR register  ********************/

+#define JPEG_SR_IFTF_Pos                (1U)

+#define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */

+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is bellow its threshold flag */

+#define JPEG_SR_IFNFF_Pos               (2U)

+#define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */

+#define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */

+#define JPEG_SR_OFTF_Pos                (3U)

+#define JPEG_SR_OFTF_Msk                (0x1UL << JPEG_SR_OFTF_Pos)            /*!< 0x00000008 */

+#define JPEG_SR_OFTF                    JPEG_SR_OFTF_Msk                       /*!<Output FIFO is not empty and has reach its threshold */

+#define JPEG_SR_OFNEF_Pos               (4U)

+#define JPEG_SR_OFNEF_Msk               (0x1UL << JPEG_SR_OFNEF_Pos)           /*!< 0x00000010 */

+#define JPEG_SR_OFNEF                   JPEG_SR_OFNEF_Msk                      /*!<Output FIFO is not empty, a data is available */

+#define JPEG_SR_EOCF_Pos                (5U)

+#define JPEG_SR_EOCF_Msk                (0x1UL << JPEG_SR_EOCF_Pos)            /*!< 0x00000020 */

+#define JPEG_SR_EOCF                    JPEG_SR_EOCF_Msk                       /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */

+#define JPEG_SR_HPDF_Pos                (6U)

+#define JPEG_SR_HPDF_Msk                (0x1UL << JPEG_SR_HPDF_Pos)            /*!< 0x00000040 */

+#define JPEG_SR_HPDF                    JPEG_SR_HPDF_Msk                       /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */

+#define JPEG_SR_COF_Pos                 (7U)

+#define JPEG_SR_COF_Msk                 (0x1UL << JPEG_SR_COF_Pos)             /*!< 0x00000080 */

+#define JPEG_SR_COF                     JPEG_SR_COF_Msk                        /*!<JPEG Codec operation on going flag */

+

+/********************  Bit definition for CFR register  ********************/

+#define JPEG_CFR_CEOCF_Pos              (4U)

+#define JPEG_CFR_CEOCF_Msk              (0x1UL << JPEG_CFR_CEOCF_Pos)          /*!< 0x00000010 */

+#define JPEG_CFR_CEOCF                  JPEG_CFR_CEOCF_Msk                     /*!<Clear End of Conversion Flag */

+#define JPEG_CFR_CHPDF_Pos              (5U)

+#define JPEG_CFR_CHPDF_Msk              (0x1UL << JPEG_CFR_CHPDF_Pos)          /*!< 0x00000020 */

+#define JPEG_CFR_CHPDF                  JPEG_CFR_CHPDF_Msk                     /*!<Clear Header Parsing Done Flag */

+

+/********************  Bit definition for DIR register  ********************/

+#define JPEG_DIR_DATAIN_Pos             (0U)

+#define JPEG_DIR_DATAIN_Msk             (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)  /*!< 0xFFFFFFFF */

+#define JPEG_DIR_DATAIN                 JPEG_DIR_DATAIN_Msk                    /*!<Data Input FIFO */

+

+/********************  Bit definition for DOR register  ********************/

+#define JPEG_DOR_DATAOUT_Pos            (0U)

+#define JPEG_DOR_DATAOUT_Msk            (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */

+#define JPEG_DOR_DATAOUT                JPEG_DOR_DATAOUT_Msk                   /*!<Data Output FIFO */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      LCD-TFT Display Controller (LTDC)                     */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for LTDC_SSCR register  *****************/

+

+#define LTDC_SSCR_VSH_Pos            (0U)

+#define LTDC_SSCR_VSH_Msk            (0x7FFUL << LTDC_SSCR_VSH_Pos)            /*!< 0x000007FF */

+#define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height  */

+#define LTDC_SSCR_HSW_Pos            (16U)

+#define LTDC_SSCR_HSW_Msk            (0xFFFUL << LTDC_SSCR_HSW_Pos)            /*!< 0x0FFF0000 */

+#define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */

+

+/********************  Bit definition for LTDC_BPCR register  *****************/

+

+#define LTDC_BPCR_AVBP_Pos           (0U)

+#define LTDC_BPCR_AVBP_Msk           (0x7FFUL << LTDC_BPCR_AVBP_Pos)           /*!< 0x000007FF */

+#define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch   */

+#define LTDC_BPCR_AHBP_Pos           (16U)

+#define LTDC_BPCR_AHBP_Msk           (0xFFFUL << LTDC_BPCR_AHBP_Pos)           /*!< 0x0FFF0000 */

+#define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */

+

+/********************  Bit definition for LTDC_AWCR register  *****************/

+

+#define LTDC_AWCR_AAH_Pos            (0U)

+#define LTDC_AWCR_AAH_Msk            (0x7FFUL << LTDC_AWCR_AAH_Pos)            /*!< 0x000007FF */

+#define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active heigh */

+#define LTDC_AWCR_AAW_Pos            (16U)

+#define LTDC_AWCR_AAW_Msk            (0xFFFUL << LTDC_AWCR_AAW_Pos)            /*!< 0x0FFF0000 */

+#define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */

+

+/********************  Bit definition for LTDC_TWCR register  *****************/

+

+#define LTDC_TWCR_TOTALH_Pos         (0U)

+#define LTDC_TWCR_TOTALH_Msk         (0x7FFUL << LTDC_TWCR_TOTALH_Pos)         /*!< 0x000007FF */

+#define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total Heigh */

+#define LTDC_TWCR_TOTALW_Pos         (16U)

+#define LTDC_TWCR_TOTALW_Msk         (0xFFFUL << LTDC_TWCR_TOTALW_Pos)         /*!< 0x0FFF0000 */

+#define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */

+

+/********************  Bit definition for LTDC_GCR register  ******************/

+

+#define LTDC_GCR_LTDCEN_Pos          (0U)

+#define LTDC_GCR_LTDCEN_Msk          (0x1UL << LTDC_GCR_LTDCEN_Pos)            /*!< 0x00000001 */

+#define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit       */

+#define LTDC_GCR_DBW_Pos             (4U)

+#define LTDC_GCR_DBW_Msk             (0x7UL << LTDC_GCR_DBW_Pos)               /*!< 0x00000070 */

+#define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width                   */

+#define LTDC_GCR_DGW_Pos             (8U)

+#define LTDC_GCR_DGW_Msk             (0x7UL << LTDC_GCR_DGW_Pos)               /*!< 0x00000700 */

+#define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width                  */

+#define LTDC_GCR_DRW_Pos             (12U)

+#define LTDC_GCR_DRW_Msk             (0x7UL << LTDC_GCR_DRW_Pos)               /*!< 0x00007000 */

+#define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width                    */

+#define LTDC_GCR_DEN_Pos             (16U)

+#define LTDC_GCR_DEN_Msk             (0x1UL << LTDC_GCR_DEN_Pos)               /*!< 0x00010000 */

+#define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable                       */

+#define LTDC_GCR_PCPOL_Pos           (28U)

+#define LTDC_GCR_PCPOL_Msk           (0x1UL << LTDC_GCR_PCPOL_Pos)             /*!< 0x10000000 */

+#define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity                */

+#define LTDC_GCR_DEPOL_Pos           (29U)

+#define LTDC_GCR_DEPOL_Msk           (0x1UL << LTDC_GCR_DEPOL_Pos)             /*!< 0x20000000 */

+#define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity                */

+#define LTDC_GCR_VSPOL_Pos           (30U)

+#define LTDC_GCR_VSPOL_Msk           (0x1UL << LTDC_GCR_VSPOL_Pos)             /*!< 0x40000000 */

+#define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity   */

+#define LTDC_GCR_HSPOL_Pos           (31U)

+#define LTDC_GCR_HSPOL_Msk           (0x1UL << LTDC_GCR_HSPOL_Pos)             /*!< 0x80000000 */

+#define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */

+

+

+/********************  Bit definition for LTDC_SRCR register  *****************/

+

+#define LTDC_SRCR_IMR_Pos            (0U)

+#define LTDC_SRCR_IMR_Msk            (0x1UL << LTDC_SRCR_IMR_Pos)              /*!< 0x00000001 */

+#define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload         */

+#define LTDC_SRCR_VBR_Pos            (1U)

+#define LTDC_SRCR_VBR_Msk            (0x1UL << LTDC_SRCR_VBR_Pos)              /*!< 0x00000002 */

+#define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */

+

+/********************  Bit definition for LTDC_BCCR register  *****************/

+

+#define LTDC_BCCR_BCBLUE_Pos         (0U)

+#define LTDC_BCCR_BCBLUE_Msk         (0xFFUL << LTDC_BCCR_BCBLUE_Pos)          /*!< 0x000000FF */

+#define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value  */

+#define LTDC_BCCR_BCGREEN_Pos        (8U)

+#define LTDC_BCCR_BCGREEN_Msk        (0xFFUL << LTDC_BCCR_BCGREEN_Pos)         /*!< 0x0000FF00 */

+#define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */

+#define LTDC_BCCR_BCRED_Pos          (16U)

+#define LTDC_BCCR_BCRED_Msk          (0xFFUL << LTDC_BCCR_BCRED_Pos)           /*!< 0x00FF0000 */

+#define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value   */

+

+/********************  Bit definition for LTDC_IER register  ******************/

+

+#define LTDC_IER_LIE_Pos             (0U)

+#define LTDC_IER_LIE_Msk             (0x1UL << LTDC_IER_LIE_Pos)               /*!< 0x00000001 */

+#define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable            */

+#define LTDC_IER_FUIE_Pos            (1U)

+#define LTDC_IER_FUIE_Msk            (0x1UL << LTDC_IER_FUIE_Pos)              /*!< 0x00000002 */

+#define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable   */

+#define LTDC_IER_TERRIE_Pos          (2U)

+#define LTDC_IER_TERRIE_Msk          (0x1UL << LTDC_IER_TERRIE_Pos)            /*!< 0x00000004 */

+#define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable  */

+#define LTDC_IER_RRIE_Pos            (3U)

+#define LTDC_IER_RRIE_Msk            (0x1UL << LTDC_IER_RRIE_Pos)              /*!< 0x00000008 */

+#define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */

+

+/********************  Bit definition for LTDC_ISR register  ******************/

+

+#define LTDC_ISR_LIF_Pos             (0U)

+#define LTDC_ISR_LIF_Msk             (0x1UL << LTDC_ISR_LIF_Pos)               /*!< 0x00000001 */

+#define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */

+#define LTDC_ISR_FUIF_Pos            (1U)

+#define LTDC_ISR_FUIF_Msk            (0x1UL << LTDC_ISR_FUIF_Pos)              /*!< 0x00000002 */

+#define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */

+#define LTDC_ISR_TERRIF_Pos          (2U)

+#define LTDC_ISR_TERRIF_Msk          (0x1UL << LTDC_ISR_TERRIF_Pos)            /*!< 0x00000004 */

+#define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */

+#define LTDC_ISR_RRIF_Pos            (3U)

+#define LTDC_ISR_RRIF_Msk            (0x1UL << LTDC_ISR_RRIF_Pos)              /*!< 0x00000008 */

+#define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */

+

+/********************  Bit definition for LTDC_ICR register  ******************/

+

+#define LTDC_ICR_CLIF_Pos            (0U)

+#define LTDC_ICR_CLIF_Msk            (0x1UL << LTDC_ICR_CLIF_Pos)              /*!< 0x00000001 */

+#define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */

+#define LTDC_ICR_CFUIF_Pos           (1U)

+#define LTDC_ICR_CFUIF_Msk           (0x1UL << LTDC_ICR_CFUIF_Pos)             /*!< 0x00000002 */

+#define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */

+#define LTDC_ICR_CTERRIF_Pos         (2U)

+#define LTDC_ICR_CTERRIF_Msk         (0x1UL << LTDC_ICR_CTERRIF_Pos)           /*!< 0x00000004 */

+#define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */

+#define LTDC_ICR_CRRIF_Pos           (3U)

+#define LTDC_ICR_CRRIF_Msk           (0x1UL << LTDC_ICR_CRRIF_Pos)             /*!< 0x00000008 */

+#define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */

+

+/********************  Bit definition for LTDC_LIPCR register  ****************/

+

+#define LTDC_LIPCR_LIPOS_Pos         (0U)

+#define LTDC_LIPCR_LIPOS_Msk         (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)         /*!< 0x000007FF */

+#define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */

+

+/********************  Bit definition for LTDC_CPSR register  *****************/

+

+#define LTDC_CPSR_CYPOS_Pos          (0U)

+#define LTDC_CPSR_CYPOS_Msk          (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)         /*!< 0x0000FFFF */

+#define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */

+#define LTDC_CPSR_CXPOS_Pos          (16U)

+#define LTDC_CPSR_CXPOS_Msk          (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)         /*!< 0xFFFF0000 */

+#define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */

+

+/********************  Bit definition for LTDC_CDSR register  *****************/

+

+#define LTDC_CDSR_VDES_Pos           (0U)

+#define LTDC_CDSR_VDES_Msk           (0x1UL << LTDC_CDSR_VDES_Pos)             /*!< 0x00000001 */

+#define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status       */

+#define LTDC_CDSR_HDES_Pos           (1U)

+#define LTDC_CDSR_HDES_Msk           (0x1UL << LTDC_CDSR_HDES_Pos)             /*!< 0x00000002 */

+#define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status     */

+#define LTDC_CDSR_VSYNCS_Pos         (2U)

+#define LTDC_CDSR_VSYNCS_Msk         (0x1UL << LTDC_CDSR_VSYNCS_Pos)           /*!< 0x00000004 */

+#define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status   */

+#define LTDC_CDSR_HSYNCS_Pos         (3U)

+#define LTDC_CDSR_HSYNCS_Msk         (0x1UL << LTDC_CDSR_HSYNCS_Pos)           /*!< 0x00000008 */

+#define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */

+

+/********************  Bit definition for LTDC_LxCR register  *****************/

+

+#define LTDC_LxCR_LEN_Pos            (0U)

+#define LTDC_LxCR_LEN_Msk            (0x1UL << LTDC_LxCR_LEN_Pos)              /*!< 0x00000001 */

+#define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable              */

+#define LTDC_LxCR_COLKEN_Pos         (1U)

+#define LTDC_LxCR_COLKEN_Msk         (0x1UL << LTDC_LxCR_COLKEN_Pos)           /*!< 0x00000002 */

+#define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable       */

+#define LTDC_LxCR_CLUTEN_Pos         (4U)

+#define LTDC_LxCR_CLUTEN_Msk         (0x1UL << LTDC_LxCR_CLUTEN_Pos)           /*!< 0x00000010 */

+#define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */

+

+/********************  Bit definition for LTDC_LxWHPCR register  **************/

+

+#define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)

+#define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)     /*!< 0x00000FFF */

+#define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */

+#define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)

+#define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)    /*!< 0xFFFF0000 */

+#define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position  */

+

+/********************  Bit definition for LTDC_LxWVPCR register  **************/

+

+#define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)

+#define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)     /*!< 0x00000FFF */

+#define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */

+#define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)

+#define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)    /*!< 0xFFFF0000 */

+#define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position  */

+

+/********************  Bit definition for LTDC_LxCKCR register  ***************/

+

+#define LTDC_LxCKCR_CKBLUE_Pos       (0U)

+#define LTDC_LxCKCR_CKBLUE_Msk       (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value  */

+#define LTDC_LxCKCR_CKGREEN_Pos      (8U)

+#define LTDC_LxCKCR_CKGREEN_Msk      (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */

+#define LTDC_LxCKCR_CKRED_Pos        (16U)

+#define LTDC_LxCKCR_CKRED_Msk        (0xFFUL << LTDC_LxCKCR_CKRED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value   */

+

+/********************  Bit definition for LTDC_LxPFCR register  ***************/

+

+#define LTDC_LxPFCR_PF_Pos           (0U)

+#define LTDC_LxPFCR_PF_Msk           (0x7UL << LTDC_LxPFCR_PF_Pos)             /*!< 0x00000007 */

+#define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */

+

+/********************  Bit definition for LTDC_LxCACR register  ***************/

+

+#define LTDC_LxCACR_CONSTA_Pos       (0U)

+#define LTDC_LxCACR_CONSTA_Msk       (0xFFUL << LTDC_LxCACR_CONSTA_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */

+

+/********************  Bit definition for LTDC_LxDCCR register  ***************/

+

+#define LTDC_LxDCCR_DCBLUE_Pos       (0U)

+#define LTDC_LxDCCR_DCBLUE_Msk       (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue  */

+#define LTDC_LxDCCR_DCGREEN_Pos      (8U)

+#define LTDC_LxDCCR_DCGREEN_Msk      (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */

+#define LTDC_LxDCCR_DCRED_Pos        (16U)

+#define LTDC_LxDCCR_DCRED_Msk        (0xFFUL << LTDC_LxDCCR_DCRED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red   */

+#define LTDC_LxDCCR_DCALPHA_Pos      (24U)

+#define LTDC_LxDCCR_DCALPHA_Msk      (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)       /*!< 0xFF000000 */

+#define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */

+

+/********************  Bit definition for LTDC_LxBFCR register  ***************/

+

+#define LTDC_LxBFCR_BF2_Pos          (0U)

+#define LTDC_LxBFCR_BF2_Msk          (0x7UL << LTDC_LxBFCR_BF2_Pos)            /*!< 0x00000007 */

+#define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */

+#define LTDC_LxBFCR_BF1_Pos          (8U)

+#define LTDC_LxBFCR_BF1_Msk          (0x7UL << LTDC_LxBFCR_BF1_Pos)            /*!< 0x00000700 */

+#define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */

+

+/********************  Bit definition for LTDC_LxCFBAR register  **************/

+

+#define LTDC_LxCFBAR_CFBADD_Pos      (0U)

+#define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */

+#define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */

+

+/********************  Bit definition for LTDC_LxCFBLR register  **************/

+

+#define LTDC_LxCFBLR_CFBLL_Pos       (0U)

+#define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)      /*!< 0x00001FFF */

+#define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length    */

+#define LTDC_LxCFBLR_CFBP_Pos        (16U)

+#define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)       /*!< 0x1FFF0000 */

+#define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */

+

+/********************  Bit definition for LTDC_LxCFBLNR register  *************/

+

+#define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)

+#define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)    /*!< 0x000007FF */

+#define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */

+

+/********************  Bit definition for LTDC_LxCLUTWR register  *************/

+

+#define LTDC_LxCLUTWR_BLUE_Pos       (0U)

+#define LTDC_LxCLUTWR_BLUE_Msk       (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value   */

+#define LTDC_LxCLUTWR_GREEN_Pos      (8U)

+#define LTDC_LxCLUTWR_GREEN_Msk      (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value  */

+#define LTDC_LxCLUTWR_RED_Pos        (16U)

+#define LTDC_LxCLUTWR_RED_Msk        (0xFFUL << LTDC_LxCLUTWR_RED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value    */

+#define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)

+#define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)     /*!< 0xFF000000 */

+#define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                     MDMA                                   */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for MDMA_GISR0 register  ****************/

+#define MDMA_GISR0_GIF0_Pos       (0U)

+#define MDMA_GISR0_GIF0_Msk       (0x1UL << MDMA_GISR0_GIF0_Pos)               /*!< 0x00000001 */

+#define MDMA_GISR0_GIF0           MDMA_GISR0_GIF0_Msk                          /*!< Channel 0 global interrupt flag */

+#define MDMA_GISR0_GIF1_Pos       (1U)

+#define MDMA_GISR0_GIF1_Msk       (0x1UL << MDMA_GISR0_GIF1_Pos)               /*!< 0x00000002 */

+#define MDMA_GISR0_GIF1           MDMA_GISR0_GIF1_Msk                          /*!< Channel 1 global interrupt flag */

+#define MDMA_GISR0_GIF2_Pos       (2U)

+#define MDMA_GISR0_GIF2_Msk       (0x1UL << MDMA_GISR0_GIF2_Pos)               /*!< 0x00000004 */

+#define MDMA_GISR0_GIF2           MDMA_GISR0_GIF2_Msk                          /*!< Channel 2 global interrupt flag */

+#define MDMA_GISR0_GIF3_Pos       (3U)

+#define MDMA_GISR0_GIF3_Msk       (0x1UL << MDMA_GISR0_GIF3_Pos)               /*!< 0x00000008 */

+#define MDMA_GISR0_GIF3           MDMA_GISR0_GIF3_Msk                          /*!< Channel 3 global interrupt flag */

+#define MDMA_GISR0_GIF4_Pos       (4U)

+#define MDMA_GISR0_GIF4_Msk       (0x1UL << MDMA_GISR0_GIF4_Pos)               /*!< 0x00000010 */

+#define MDMA_GISR0_GIF4           MDMA_GISR0_GIF4_Msk                          /*!< Channel 4 global interrupt flag */

+#define MDMA_GISR0_GIF5_Pos       (5U)

+#define MDMA_GISR0_GIF5_Msk       (0x1UL << MDMA_GISR0_GIF5_Pos)               /*!< 0x00000020 */

+#define MDMA_GISR0_GIF5           MDMA_GISR0_GIF5_Msk                          /*!< Channel 5 global interrupt flag */

+#define MDMA_GISR0_GIF6_Pos       (6U)

+#define MDMA_GISR0_GIF6_Msk       (0x1UL << MDMA_GISR0_GIF6_Pos)               /*!< 0x00000040 */

+#define MDMA_GISR0_GIF6           MDMA_GISR0_GIF6_Msk                          /*!< Channel 6 global interrupt flag */

+#define MDMA_GISR0_GIF7_Pos       (7U)

+#define MDMA_GISR0_GIF7_Msk       (0x1UL << MDMA_GISR0_GIF7_Pos)               /*!< 0x00000080 */

+#define MDMA_GISR0_GIF7           MDMA_GISR0_GIF7_Msk                          /*!< Channel 7 global interrupt flag */

+#define MDMA_GISR0_GIF8_Pos       (8U)

+#define MDMA_GISR0_GIF8_Msk       (0x1UL << MDMA_GISR0_GIF8_Pos)               /*!< 0x00000100 */

+#define MDMA_GISR0_GIF8           MDMA_GISR0_GIF8_Msk                          /*!< Channel 8 global interrupt flag */

+#define MDMA_GISR0_GIF9_Pos       (9U)

+#define MDMA_GISR0_GIF9_Msk       (0x1UL << MDMA_GISR0_GIF9_Pos)               /*!< 0x00000200 */

+#define MDMA_GISR0_GIF9           MDMA_GISR0_GIF9_Msk                          /*!< Channel 9 global interrupt flag */

+#define MDMA_GISR0_GIF10_Pos      (10U)

+#define MDMA_GISR0_GIF10_Msk      (0x1UL << MDMA_GISR0_GIF10_Pos)              /*!< 0x00000400 */

+#define MDMA_GISR0_GIF10          MDMA_GISR0_GIF10_Msk                         /*!< Channel 10 global interrupt flag */

+#define MDMA_GISR0_GIF11_Pos      (11U)

+#define MDMA_GISR0_GIF11_Msk      (0x1UL << MDMA_GISR0_GIF11_Pos)              /*!< 0x00000800 */

+#define MDMA_GISR0_GIF11          MDMA_GISR0_GIF11_Msk                         /*!< Channel 11 global interrupt flag */

+#define MDMA_GISR0_GIF12_Pos      (12U)

+#define MDMA_GISR0_GIF12_Msk      (0x1UL << MDMA_GISR0_GIF12_Pos)              /*!< 0x00001000 */

+#define MDMA_GISR0_GIF12          MDMA_GISR0_GIF12_Msk                         /*!< Channel 12 global interrupt flag */

+#define MDMA_GISR0_GIF13_Pos      (13U)

+#define MDMA_GISR0_GIF13_Msk      (0x1UL << MDMA_GISR0_GIF13_Pos)              /*!< 0x00002000 */

+#define MDMA_GISR0_GIF13          MDMA_GISR0_GIF13_Msk                         /*!< Channel 13 global interrupt flag */

+#define MDMA_GISR0_GIF14_Pos      (14U)

+#define MDMA_GISR0_GIF14_Msk      (0x1UL << MDMA_GISR0_GIF14_Pos)              /*!< 0x00004000 */

+#define MDMA_GISR0_GIF14          MDMA_GISR0_GIF14_Msk                         /*!< Channel 14 global interrupt flag */

+#define MDMA_GISR0_GIF15_Pos      (15U)

+#define MDMA_GISR0_GIF15_Msk      (0x1UL << MDMA_GISR0_GIF15_Pos)              /*!< 0x00008000 */

+#define MDMA_GISR0_GIF15          MDMA_GISR0_GIF15_Msk                         /*!< Channel 15 global interrupt flag */

+

+/********************  Bit definition for MDMA_CxISR register  ****************/

+#define MDMA_CISR_TEIF_Pos        (0U)

+#define MDMA_CISR_TEIF_Msk        (0x1UL << MDMA_CISR_TEIF_Pos)                /*!< 0x00000001 */

+#define MDMA_CISR_TEIF            MDMA_CISR_TEIF_Msk                           /*!< Channel x transfer error interrupt flag */

+#define MDMA_CISR_CTCIF_Pos       (1U)

+#define MDMA_CISR_CTCIF_Msk       (0x1UL << MDMA_CISR_CTCIF_Pos)               /*!< 0x00000002 */

+#define MDMA_CISR_CTCIF           MDMA_CISR_CTCIF_Msk                          /*!< Channel x Channel Transfer Complete interrupt flag */

+#define MDMA_CISR_BRTIF_Pos       (2U)

+#define MDMA_CISR_BRTIF_Msk       (0x1UL << MDMA_CISR_BRTIF_Pos)               /*!< 0x00000004 */

+#define MDMA_CISR_BRTIF           MDMA_CISR_BRTIF_Msk                          /*!< Channel x block repeat transfer complete interrupt flag */

+#define MDMA_CISR_BTIF_Pos        (3U)

+#define MDMA_CISR_BTIF_Msk        (0x1UL << MDMA_CISR_BTIF_Pos)                /*!< 0x00000008 */

+#define MDMA_CISR_BTIF            MDMA_CISR_BTIF_Msk                           /*!< Channel x block transfer complete interrupt flag */

+#define MDMA_CISR_TCIF_Pos        (4U)

+#define MDMA_CISR_TCIF_Msk        (0x1UL << MDMA_CISR_TCIF_Pos)                /*!< 0x00000010 */

+#define MDMA_CISR_TCIF            MDMA_CISR_TCIF_Msk                           /*!< Channel x buffer transfer complete interrupt flag */

+#define MDMA_CISR_CRQA_Pos        (16U)

+#define MDMA_CISR_CRQA_Msk        (0x1UL << MDMA_CISR_CRQA_Pos)                /*!< 0x00010000 */

+#define MDMA_CISR_CRQA            MDMA_CISR_CRQA_Msk                           /*!< Channel x ReQest Active flag */

+

+/********************  Bit definition for MDMA_CxIFCR register  ****************/

+#define MDMA_CIFCR_CTEIF_Pos      (0U)

+#define MDMA_CIFCR_CTEIF_Msk      (0x1UL << MDMA_CIFCR_CTEIF_Pos)              /*!< 0x00000001 */

+#define MDMA_CIFCR_CTEIF          MDMA_CIFCR_CTEIF_Msk                         /*!< Channel x clear transfer error interrupt flag */

+#define MDMA_CIFCR_CCTCIF_Pos     (1U)

+#define MDMA_CIFCR_CCTCIF_Msk     (0x1UL << MDMA_CIFCR_CCTCIF_Pos)             /*!< 0x00000002 */

+#define MDMA_CIFCR_CCTCIF         MDMA_CIFCR_CCTCIF_Msk                        /*!< Clear Channel transfer complete interrupt flag for channel x */

+#define MDMA_CIFCR_CBRTIF_Pos     (2U)

+#define MDMA_CIFCR_CBRTIF_Msk     (0x1UL << MDMA_CIFCR_CBRTIF_Pos)             /*!< 0x00000004 */

+#define MDMA_CIFCR_CBRTIF         MDMA_CIFCR_CBRTIF_Msk                        /*!< Channel x clear block repeat transfer complete interrupt flag */

+#define MDMA_CIFCR_CBTIF_Pos      (3U)

+#define MDMA_CIFCR_CBTIF_Msk      (0x1UL << MDMA_CIFCR_CBTIF_Pos)              /*!< 0x00000008 */

+#define MDMA_CIFCR_CBTIF          MDMA_CIFCR_CBTIF_Msk                         /*!< Channel x Clear block transfer complete interrupt flag */

+#define MDMA_CIFCR_CLTCIF_Pos     (4U)

+#define MDMA_CIFCR_CLTCIF_Msk     (0x1UL << MDMA_CIFCR_CLTCIF_Pos)             /*!< 0x00000010 */

+#define MDMA_CIFCR_CLTCIF         MDMA_CIFCR_CLTCIF_Msk                        /*!< CLear Transfer buffer Complete Interrupt Flag for channel */

+

+/********************  Bit definition for MDMA_CxESR register  ****************/

+#define MDMA_CESR_TEA_Pos         (0U)

+#define MDMA_CESR_TEA_Msk         (0x7FUL << MDMA_CESR_TEA_Pos)                /*!< 0x0000007F */

+#define MDMA_CESR_TEA             MDMA_CESR_TEA_Msk                            /*!< Transfer Error Address */

+#define MDMA_CESR_TED_Pos         (7U)

+#define MDMA_CESR_TED_Msk         (0x1UL << MDMA_CESR_TED_Pos)                 /*!< 0x00000080 */

+#define MDMA_CESR_TED             MDMA_CESR_TED_Msk                            /*!< Transfer Error Direction */

+#define MDMA_CESR_TELD_Pos        (8U)

+#define MDMA_CESR_TELD_Msk        (0x1UL << MDMA_CESR_TELD_Pos)                /*!< 0x00000100 */

+#define MDMA_CESR_TELD            MDMA_CESR_TELD_Msk                           /*!< Transfer Error Link Data */

+#define MDMA_CESR_TEMD_Pos        (9U)

+#define MDMA_CESR_TEMD_Msk        (0x1UL << MDMA_CESR_TEMD_Pos)                /*!< 0x00000200 */

+#define MDMA_CESR_TEMD            MDMA_CESR_TEMD_Msk                           /*!< Transfer Error Mask Data */

+#define MDMA_CESR_ASE_Pos         (10U)

+#define MDMA_CESR_ASE_Msk         (0x1UL << MDMA_CESR_ASE_Pos)                 /*!< 0x00000400 */

+#define MDMA_CESR_ASE             MDMA_CESR_ASE_Msk                            /*!< Address/Size Error       */

+#define MDMA_CESR_BSE_Pos         (11U)

+#define MDMA_CESR_BSE_Msk         (0x1UL << MDMA_CESR_BSE_Pos)                 /*!< 0x00000800 */

+#define MDMA_CESR_BSE             MDMA_CESR_BSE_Msk                            /*!< Block Size Error         */

+

+/********************  Bit definition for MDMA_CxCR register  ****************/

+#define MDMA_CCR_EN_Pos           (0U)

+#define MDMA_CCR_EN_Msk           (0x1UL << MDMA_CCR_EN_Pos)                   /*!< 0x00000001 */

+#define MDMA_CCR_EN               MDMA_CCR_EN_Msk                              /*!< Channel enable / flag channel ready when read low */

+#define MDMA_CCR_TEIE_Pos         (1U)

+#define MDMA_CCR_TEIE_Msk         (0x1UL << MDMA_CCR_TEIE_Pos)                 /*!< 0x00000002 */

+#define MDMA_CCR_TEIE             MDMA_CCR_TEIE_Msk                            /*!< Transfer error interrupt enable */

+#define MDMA_CCR_CTCIE_Pos        (2U)

+#define MDMA_CCR_CTCIE_Msk        (0x1UL << MDMA_CCR_CTCIE_Pos)                /*!< 0x00000004 */

+#define MDMA_CCR_CTCIE            MDMA_CCR_CTCIE_Msk                           /*!< Channel Transfer Complete interrupt enable */

+#define MDMA_CCR_BRTIE_Pos        (3U)

+#define MDMA_CCR_BRTIE_Msk        (0x1UL << MDMA_CCR_BRTIE_Pos)                /*!< 0x00000008 */

+#define MDMA_CCR_BRTIE            MDMA_CCR_BRTIE_Msk                           /*!< Block Repeat transfer interrupt enable */

+#define MDMA_CCR_BTIE_Pos         (4U)

+#define MDMA_CCR_BTIE_Msk         (0x1UL << MDMA_CCR_BTIE_Pos)                 /*!< 0x00000010 */

+#define MDMA_CCR_BTIE             MDMA_CCR_BTIE_Msk                            /*!< Block Transfer interrupt enable */

+#define MDMA_CCR_TCIE_Pos         (5U)

+#define MDMA_CCR_TCIE_Msk         (0x1UL << MDMA_CCR_TCIE_Pos)                 /*!< 0x00000020 */

+#define MDMA_CCR_TCIE             MDMA_CCR_TCIE_Msk                            /*!< buffer Transfer Complete interrupt enable */

+#define MDMA_CCR_PL_Pos           (6U)

+#define MDMA_CCR_PL_Msk           (0x3UL << MDMA_CCR_PL_Pos)                   /*!< 0x000000C0 */

+#define MDMA_CCR_PL               MDMA_CCR_PL_Msk                              /*!< Priority level */

+#define MDMA_CCR_PL_0             (0x1UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000040 */

+#define MDMA_CCR_PL_1             (0x2UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000080 */

+#define MDMA_CCR_BEX_Pos          (12U)

+#define MDMA_CCR_BEX_Msk          (0x1UL << MDMA_CCR_BEX_Pos)                  /*!< 0x00001000 */

+#define MDMA_CCR_BEX              MDMA_CCR_BEX_Msk                             /*!< Byte Endianess eXchange */

+#define MDMA_CCR_HEX_Pos          (13U)

+#define MDMA_CCR_HEX_Msk          (0x1UL << MDMA_CCR_HEX_Pos)                  /*!< 0x00002000 */

+#define MDMA_CCR_HEX              MDMA_CCR_HEX_Msk                             /*!< Half word Endianess eXchange */

+#define MDMA_CCR_WEX_Pos          (14U)

+#define MDMA_CCR_WEX_Msk          (0x1UL << MDMA_CCR_WEX_Pos)                  /*!< 0x00004000 */

+#define MDMA_CCR_WEX              MDMA_CCR_WEX_Msk                             /*!< Word Endianess eXchange */

+#define MDMA_CCR_SWRQ_Pos         (16U)

+#define MDMA_CCR_SWRQ_Msk         (0x1UL << MDMA_CCR_SWRQ_Pos)                 /*!< 0x00010000 */

+#define MDMA_CCR_SWRQ             MDMA_CCR_SWRQ_Msk                            /*!< SW ReQuest */

+

+/********************  Bit definition for MDMA_CxTCR register  ****************/

+#define MDMA_CTCR_SINC_Pos        (0U)

+#define MDMA_CTCR_SINC_Msk        (0x3UL << MDMA_CTCR_SINC_Pos)                /*!< 0x00000003 */

+#define MDMA_CTCR_SINC            MDMA_CTCR_SINC_Msk                           /*!< Source increment mode */

+#define MDMA_CTCR_SINC_0          (0x1UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000001 */

+#define MDMA_CTCR_SINC_1          (0x2UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000002 */

+#define MDMA_CTCR_DINC_Pos        (2U)

+#define MDMA_CTCR_DINC_Msk        (0x3UL << MDMA_CTCR_DINC_Pos)                /*!< 0x0000000C */

+#define MDMA_CTCR_DINC            MDMA_CTCR_DINC_Msk                           /*!< Source increment mode */

+#define MDMA_CTCR_DINC_0          (0x1UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000004 */

+#define MDMA_CTCR_DINC_1          (0x2UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000008 */

+#define MDMA_CTCR_SSIZE_Pos       (4U)

+#define MDMA_CTCR_SSIZE_Msk       (0x3UL << MDMA_CTCR_SSIZE_Pos)               /*!< 0x00000030 */

+#define MDMA_CTCR_SSIZE           MDMA_CTCR_SSIZE_Msk                          /*!< Source data size */

+#define MDMA_CTCR_SSIZE_0         (0x1UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000010 */

+#define MDMA_CTCR_SSIZE_1         (0x2UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000020 */

+#define MDMA_CTCR_DSIZE_Pos       (6U)

+#define MDMA_CTCR_DSIZE_Msk       (0x3UL << MDMA_CTCR_DSIZE_Pos)               /*!< 0x000000C0 */

+#define MDMA_CTCR_DSIZE           MDMA_CTCR_DSIZE_Msk                          /*!< Destination data size */

+#define MDMA_CTCR_DSIZE_0         (0x1UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000040 */

+#define MDMA_CTCR_DSIZE_1         (0x2UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000080 */

+#define MDMA_CTCR_SINCOS_Pos      (8U)

+#define MDMA_CTCR_SINCOS_Msk      (0x3UL << MDMA_CTCR_SINCOS_Pos)              /*!< 0x00000300 */

+#define MDMA_CTCR_SINCOS          MDMA_CTCR_SINCOS_Msk                         /*!< Source increment offset size */

+#define MDMA_CTCR_SINCOS_0        (0x1UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000100 */

+#define MDMA_CTCR_SINCOS_1        (0x2UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000200 */

+#define MDMA_CTCR_DINCOS_Pos      (10U)

+#define MDMA_CTCR_DINCOS_Msk      (0x3UL << MDMA_CTCR_DINCOS_Pos)              /*!< 0x00000C00 */

+#define MDMA_CTCR_DINCOS          MDMA_CTCR_DINCOS_Msk                         /*!< Destination increment offset size */

+#define MDMA_CTCR_DINCOS_0        (0x1UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000400 */

+#define MDMA_CTCR_DINCOS_1        (0x2UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000800 */

+#define MDMA_CTCR_SBURST_Pos      (12U)

+#define MDMA_CTCR_SBURST_Msk      (0x7UL << MDMA_CTCR_SBURST_Pos)              /*!< 0x00007000 */

+#define MDMA_CTCR_SBURST          MDMA_CTCR_SBURST_Msk                         /*!< Source burst transfer configuration */

+#define MDMA_CTCR_SBURST_0        (0x1UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00001000 */

+#define MDMA_CTCR_SBURST_1        (0x2UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00002000 */

+#define MDMA_CTCR_SBURST_2        (0x4UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00004000 */

+#define MDMA_CTCR_DBURST_Pos      (15U)

+#define MDMA_CTCR_DBURST_Msk      (0x7UL << MDMA_CTCR_DBURST_Pos)              /*!< 0x00038000 */

+#define MDMA_CTCR_DBURST          MDMA_CTCR_DBURST_Msk                         /*!< Destination burst transfer configuration */

+#define MDMA_CTCR_DBURST_0        (0x1UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00008000 */

+#define MDMA_CTCR_DBURST_1        (0x2UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00010000 */

+#define MDMA_CTCR_DBURST_2        (0x4UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00020000 */

+#define MDMA_CTCR_TLEN_Pos        (18U)

+#define MDMA_CTCR_TLEN_Msk        (0x7FUL << MDMA_CTCR_TLEN_Pos)               /*!< 0x01FC0000 */

+#define MDMA_CTCR_TLEN            MDMA_CTCR_TLEN_Msk                           /*!< buffer Transfer Length (number of bytes - 1) */

+#define MDMA_CTCR_PKE_Pos         (25U)

+#define MDMA_CTCR_PKE_Msk         (0x1UL << MDMA_CTCR_PKE_Pos)                 /*!< 0x02000000 */

+#define MDMA_CTCR_PKE             MDMA_CTCR_PKE_Msk                            /*!< PacK Enable */

+#define MDMA_CTCR_PAM_Pos         (26U)

+#define MDMA_CTCR_PAM_Msk         (0x3UL << MDMA_CTCR_PAM_Pos)                 /*!< 0x0C000000 */

+#define MDMA_CTCR_PAM             MDMA_CTCR_PAM_Msk                            /*!< Padding/Alignement Mode */

+#define MDMA_CTCR_PAM_0           (0x1UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x4000000 */

+#define MDMA_CTCR_PAM_1           (0x2UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x8000000 */

+#define MDMA_CTCR_TRGM_Pos        (28U)

+#define MDMA_CTCR_TRGM_Msk        (0x3UL << MDMA_CTCR_TRGM_Pos)                /*!< 0x30000000 */

+#define MDMA_CTCR_TRGM            MDMA_CTCR_TRGM_Msk                           /*!< Trigger Mode */

+#define MDMA_CTCR_TRGM_0          (0x1UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x10000000 */

+#define MDMA_CTCR_TRGM_1          (0x2UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x20000000 */

+#define MDMA_CTCR_SWRM_Pos        (30U)

+#define MDMA_CTCR_SWRM_Msk        (0x1UL << MDMA_CTCR_SWRM_Pos)                /*!< 0x40000000 */

+#define MDMA_CTCR_SWRM            MDMA_CTCR_SWRM_Msk                           /*!< SW Request Mode */

+#define MDMA_CTCR_BWM_Pos         (31U)

+#define MDMA_CTCR_BWM_Msk         (0x1UL << MDMA_CTCR_BWM_Pos)                 /*!< 0x80000000 */

+#define MDMA_CTCR_BWM             MDMA_CTCR_BWM_Msk                            /*!< Bufferable Write Mode */

+

+/********************  Bit definition for MDMA_CxBNDTR register  ****************/

+#define MDMA_CBNDTR_BNDT_Pos      (0U)

+#define MDMA_CBNDTR_BNDT_Msk      (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos)          /*!< 0x0001FFFF */

+#define MDMA_CBNDTR_BNDT          MDMA_CBNDTR_BNDT_Msk                         /*!< Block Number of data bytes to transfer */

+#define MDMA_CBNDTR_BRSUM_Pos     (18U)

+#define MDMA_CBNDTR_BRSUM_Msk     (0x1UL << MDMA_CBNDTR_BRSUM_Pos)             /*!< 0x00040000 */

+#define MDMA_CBNDTR_BRSUM         MDMA_CBNDTR_BRSUM_Msk                        /*!< Block Repeat Source address Update Mode */

+#define MDMA_CBNDTR_BRDUM_Pos     (19U)

+#define MDMA_CBNDTR_BRDUM_Msk     (0x1UL << MDMA_CBNDTR_BRDUM_Pos)             /*!< 0x00080000 */

+#define MDMA_CBNDTR_BRDUM         MDMA_CBNDTR_BRDUM_Msk                        /*!< Block Repeat Destination address Update Mode */

+#define MDMA_CBNDTR_BRC_Pos       (20U)

+#define MDMA_CBNDTR_BRC_Msk       (0xFFFUL << MDMA_CBNDTR_BRC_Pos)             /*!< 0xFFF00000 */

+#define MDMA_CBNDTR_BRC           MDMA_CBNDTR_BRC_Msk                          /*!< Block Repeat Count */

+

+/********************  Bit definition for MDMA_CxSAR register  ****************/

+#define MDMA_CSAR_SAR_Pos         (0U)

+#define MDMA_CSAR_SAR_Msk         (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CSAR_SAR             MDMA_CSAR_SAR_Msk                            /*!< Source address */

+

+/********************  Bit definition for MDMA_CxDAR register  ****************/

+#define MDMA_CDAR_DAR_Pos         (0U)

+#define MDMA_CDAR_DAR_Msk         (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CDAR_DAR             MDMA_CDAR_DAR_Msk                            /*!< Destination address */

+

+/********************  Bit definition for MDMA_CxBRUR  ************************/

+#define MDMA_CBRUR_SUV_Pos        (0U)

+#define MDMA_CBRUR_SUV_Msk        (0xFFFFUL << MDMA_CBRUR_SUV_Pos)             /*!< 0x0000FFFF */

+#define MDMA_CBRUR_SUV            MDMA_CBRUR_SUV_Msk                           /*!< Source address Update Value */

+#define MDMA_CBRUR_DUV_Pos        (16U)

+#define MDMA_CBRUR_DUV_Msk        (0xFFFFUL << MDMA_CBRUR_DUV_Pos)             /*!< 0xFFFF0000 */

+#define MDMA_CBRUR_DUV            MDMA_CBRUR_DUV_Msk                           /*!< Destination address Update Value */

+

+/********************  Bit definition for MDMA_CxLAR  *************************/

+#define MDMA_CLAR_LAR_Pos         (0U)

+#define MDMA_CLAR_LAR_Msk         (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CLAR_LAR             MDMA_CLAR_LAR_Msk                            /*!< Link Address Register */

+

+/********************  Bit definition for MDMA_CxTBR)  ************************/

+#define MDMA_CTBR_TSEL_Pos        (0U)

+#define MDMA_CTBR_TSEL_Msk        (0xFFUL << MDMA_CTBR_TSEL_Pos)               /*!< 0x000000FF */

+#define MDMA_CTBR_TSEL            MDMA_CTBR_TSEL_Msk                           /*!< Trigger SELection */

+#define MDMA_CTBR_SBUS_Pos        (16U)

+#define MDMA_CTBR_SBUS_Msk        (0x1UL << MDMA_CTBR_SBUS_Pos)                /*!< 0x00010000 */

+#define MDMA_CTBR_SBUS            MDMA_CTBR_SBUS_Msk                           /*!< Source BUS select */

+#define MDMA_CTBR_DBUS_Pos        (17U)

+#define MDMA_CTBR_DBUS_Msk        (0x1UL << MDMA_CTBR_DBUS_Pos)                /*!< 0x00020000 */

+#define MDMA_CTBR_DBUS            MDMA_CTBR_DBUS_Msk                           /*!< Destination BUS select */

+

+/********************  Bit definition for MDMA_CxMAR)  ************************/

+#define MDMA_CMAR_MAR_Pos         (0U)

+#define MDMA_CMAR_MAR_Msk         (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CMAR_MAR             MDMA_CMAR_MAR_Msk                            /*!< Mask address */

+

+/********************  Bit definition for MDMA_CxMDR)  ************************/

+#define MDMA_CMDR_MDR_Pos         (0U)

+#define MDMA_CMDR_MDR_Msk         (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CMDR_MDR             MDMA_CMDR_MDR_Msk                            /*!< Mask Data */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Operational Amplifier (OPAMP)                      */

+/*                                                                            */

+/******************************************************************************/

+/*********************  Bit definition for OPAMPx_CSR register  ***************/

+#define OPAMP_CSR_OPAMPxEN_Pos           (0U)

+#define OPAMP_CSR_OPAMPxEN_Msk           (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)     /*!< 0x00000001 */

+#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */

+#define OPAMP_CSR_FORCEVP_Pos            (1U)

+#define OPAMP_CSR_FORCEVP_Msk            (0x1UL << OPAMP_CSR_FORCEVP_Pos)      /*!< 0x00000002 */

+#define OPAMP_CSR_FORCEVP                OPAMP_CSR_FORCEVP_Msk                 /*!< Force internal reference on VP */

+

+#define OPAMP_CSR_VPSEL_Pos              (2U)

+#define OPAMP_CSR_VPSEL_Msk              (0x3UL << OPAMP_CSR_VPSEL_Pos)        /*!< 0x0000000C */

+#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */

+#define OPAMP_CSR_VPSEL_0                (0x1UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000004 */

+#define OPAMP_CSR_VPSEL_1                (0x2UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000008 */

+

+#define OPAMP_CSR_VMSEL_Pos              (5U)

+#define OPAMP_CSR_VMSEL_Msk              (0x3UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000060 */

+#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */

+#define OPAMP_CSR_VMSEL_0                (0x1UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000020 */

+#define OPAMP_CSR_VMSEL_1                (0x2UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000040 */

+

+#define OPAMP_CSR_OPAHSM_Pos             (8U)

+#define OPAMP_CSR_OPAHSM_Msk             (0x1UL << OPAMP_CSR_OPAHSM_Pos)       /*!< 0x00000100 */

+#define OPAMP_CSR_OPAHSM                 OPAMP_CSR_OPAHSM_Msk                  /*!< Operational amplifier high speed mode */

+#define OPAMP_CSR_CALON_Pos              (11U)

+#define OPAMP_CSR_CALON_Msk              (0x1UL << OPAMP_CSR_CALON_Pos)        /*!< 0x00000800 */

+#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */

+

+#define OPAMP_CSR_CALSEL_Pos             (12U)

+#define OPAMP_CSR_CALSEL_Msk             (0x3UL << OPAMP_CSR_CALSEL_Pos)       /*!< 0x00003000 */

+#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */

+#define OPAMP_CSR_CALSEL_0               (0x1UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00001000 */

+#define OPAMP_CSR_CALSEL_1               (0x2UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */

+

+#define OPAMP_CSR_PGGAIN_Pos             (14U)

+#define OPAMP_CSR_PGGAIN_Msk             (0xFUL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x0003C000 */

+#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */

+#define OPAMP_CSR_PGGAIN_0               (0x1UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00004000 */

+#define OPAMP_CSR_PGGAIN_1               (0x2UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00008000 */

+#define OPAMP_CSR_PGGAIN_2               (0x4UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00010000 */

+#define OPAMP_CSR_PGGAIN_3               (0x8UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00020000 */

+

+#define OPAMP_CSR_USERTRIM_Pos           (18U)

+#define OPAMP_CSR_USERTRIM_Msk           (0x1UL << OPAMP_CSR_USERTRIM_Pos)     /*!< 0x00040000 */

+#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */

+#define OPAMP_CSR_TSTREF_Pos             (29U)

+#define OPAMP_CSR_TSTREF_Msk             (0x1UL << OPAMP_CSR_TSTREF_Pos)       /*!< 0x20000000 */

+#define OPAMP_CSR_TSTREF                 OPAMP_CSR_TSTREF_Msk                  /*!< OpAmp calibration reference voltage output control */

+#define OPAMP_CSR_CALOUT_Pos             (30U)

+#define OPAMP_CSR_CALOUT_Msk             (0x1UL << OPAMP_CSR_CALOUT_Pos)       /*!< 0x40000000 */

+#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier calibration output */

+

+/*********************  Bit definition for OPAMP1_CSR register  ***************/

+#define OPAMP1_CSR_OPAEN_Pos              (0U)

+#define OPAMP1_CSR_OPAEN_Msk              (0x1UL << OPAMP1_CSR_OPAEN_Pos)      /*!< 0x00000001 */

+#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */

+#define OPAMP1_CSR_FORCEVP_Pos            (1U)

+#define OPAMP1_CSR_FORCEVP_Msk            (0x1UL << OPAMP1_CSR_FORCEVP_Pos)    /*!< 0x00000002 */

+#define OPAMP1_CSR_FORCEVP                OPAMP1_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */

+

+#define OPAMP1_CSR_VPSEL_Pos              (2U)

+#define OPAMP1_CSR_VPSEL_Msk              (0x3UL << OPAMP1_CSR_VPSEL_Pos)      /*!< 0x0000000C */

+#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */

+#define OPAMP1_CSR_VPSEL_0                (0x1UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000004 */

+#define OPAMP1_CSR_VPSEL_1                (0x2UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000008 */

+

+#define OPAMP1_CSR_VMSEL_Pos              (5U)

+#define OPAMP1_CSR_VMSEL_Msk              (0x3UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000060 */

+#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */

+#define OPAMP1_CSR_VMSEL_0                (0x1UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000020 */

+#define OPAMP1_CSR_VMSEL_1                (0x2UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000040 */

+

+#define OPAMP1_CSR_OPAHSM_Pos             (8U)

+#define OPAMP1_CSR_OPAHSM_Msk             (0x1UL << OPAMP1_CSR_OPAHSM_Pos)     /*!< 0x00000100 */

+#define OPAMP1_CSR_OPAHSM                 OPAMP1_CSR_OPAHSM_Msk                /*!< Operational amplifier1 high speed mode */

+#define OPAMP1_CSR_CALON_Pos              (11U)

+#define OPAMP1_CSR_CALON_Msk              (0x1UL << OPAMP1_CSR_CALON_Pos)      /*!< 0x00000800 */

+#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */

+

+#define OPAMP1_CSR_CALSEL_Pos             (12U)

+#define OPAMP1_CSR_CALSEL_Msk             (0x3UL << OPAMP1_CSR_CALSEL_Pos)     /*!< 0x00003000 */

+#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */

+#define OPAMP1_CSR_CALSEL_0               (0x1UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00001000 */

+#define OPAMP1_CSR_CALSEL_1               (0x2UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */

+

+#define OPAMP1_CSR_PGGAIN_Pos             (14U)

+#define OPAMP1_CSR_PGGAIN_Msk             (0xFUL << OPAMP1_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */

+#define OPAMP1_CSR_PGGAIN                 OPAMP1_CSR_PGGAIN_Msk                /*!< Operational amplifier1 Programmable amplifier gain value */

+#define OPAMP1_CSR_PGGAIN_0               (0x1UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00004000 */

+#define OPAMP1_CSR_PGGAIN_1               (0x2UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00008000 */

+#define OPAMP1_CSR_PGGAIN_2               (0x4UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00010000 */

+#define OPAMP1_CSR_PGGAIN_3               (0x8UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00020000 */

+

+#define OPAMP1_CSR_USERTRIM_Pos           (18U)

+#define OPAMP1_CSR_USERTRIM_Msk           (0x1UL << OPAMP1_CSR_USERTRIM_Pos)   /*!< 0x00040000 */

+#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */

+#define OPAMP1_CSR_TSTREF_Pos             (29U)

+#define OPAMP1_CSR_TSTREF_Msk             (0x1UL << OPAMP1_CSR_TSTREF_Pos)     /*!< 0x20000000 */

+#define OPAMP1_CSR_TSTREF                 OPAMP1_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */

+#define OPAMP1_CSR_CALOUT_Pos             (30U)

+#define OPAMP1_CSR_CALOUT_Msk             (0x1UL << OPAMP1_CSR_CALOUT_Pos)     /*!< 0x40000000 */

+#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */

+

+/*********************  Bit definition for OPAMP2_CSR register  ***************/

+#define OPAMP2_CSR_OPAEN_Pos              (0U)

+#define OPAMP2_CSR_OPAEN_Msk              (0x1UL << OPAMP2_CSR_OPAEN_Pos)      /*!< 0x00000001 */

+#define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */

+#define OPAMP2_CSR_FORCEVP_Pos            (1U)

+#define OPAMP2_CSR_FORCEVP_Msk            (0x1UL << OPAMP2_CSR_FORCEVP_Pos)    /*!< 0x00000002 */

+#define OPAMP2_CSR_FORCEVP                OPAMP2_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */

+

+#define OPAMP2_CSR_VPSEL_Pos              (2U)

+#define OPAMP2_CSR_VPSEL_Msk              (0x3UL << OPAMP2_CSR_VPSEL_Pos)      /*!< 0x0000000C */

+#define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */

+#define OPAMP2_CSR_VPSEL_0                (0x1UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000004 */

+#define OPAMP2_CSR_VPSEL_1                (0x2UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000008 */

+

+#define OPAMP2_CSR_VMSEL_Pos              (5U)

+#define OPAMP2_CSR_VMSEL_Msk              (0x3UL << OPAMP2_CSR_VMSEL_Pos)      /*!< 0x00000060 */

+#define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */

+#define OPAMP2_CSR_VMSEL_0                (0x1UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000020 */

+#define OPAMP2_CSR_VMSEL_1                (0x2UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000040 */

+

+#define OPAMP2_CSR_OPAHSM_Pos             (8U)

+#define OPAMP2_CSR_OPAHSM_Msk             (0x1UL << OPAMP2_CSR_OPAHSM_Pos)     /*!< 0x00000100 */

+#define OPAMP2_CSR_OPAHSM                 OPAMP2_CSR_OPAHSM_Msk                /*!< Operational amplifier2 high speed mode */

+#define OPAMP2_CSR_CALON_Pos              (11U)

+#define OPAMP2_CSR_CALON_Msk              (0x1UL << OPAMP2_CSR_CALON_Pos)      /*!< 0x00000800 */

+#define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */

+

+#define OPAMP2_CSR_CALSEL_Pos             (12U)

+#define OPAMP2_CSR_CALSEL_Msk             (0x3UL << OPAMP2_CSR_CALSEL_Pos)     /*!< 0x00003000 */

+#define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */

+#define OPAMP2_CSR_CALSEL_0               (0x1UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00001000 */

+#define OPAMP2_CSR_CALSEL_1               (0x2UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */

+

+#define OPAMP2_CSR_PGGAIN_Pos             (14U)

+#define OPAMP2_CSR_PGGAIN_Msk             (0xFUL << OPAMP2_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */

+#define OPAMP2_CSR_PGGAIN                 OPAMP2_CSR_PGGAIN_Msk                /*!< Operational amplifier2 Programmable amplifier gain value */

+#define OPAMP2_CSR_PGGAIN_0               (0x1UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00004000 */

+#define OPAMP2_CSR_PGGAIN_1               (0x2UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00008000 */

+#define OPAMP2_CSR_PGGAIN_2               (0x4UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00010000 */

+#define OPAMP2_CSR_PGGAIN_3               (0x8UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00020000 */

+

+#define OPAMP2_CSR_USERTRIM_Pos           (18U)

+#define OPAMP2_CSR_USERTRIM_Msk           (0x1UL << OPAMP2_CSR_USERTRIM_Pos)   /*!< 0x00040000 */

+#define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */

+#define OPAMP2_CSR_TSTREF_Pos             (29U)

+#define OPAMP2_CSR_TSTREF_Msk             (0x1UL << OPAMP2_CSR_TSTREF_Pos)     /*!< 0x20000000 */

+#define OPAMP2_CSR_TSTREF                 OPAMP2_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */

+#define OPAMP2_CSR_CALOUT_Pos             (30U)

+#define OPAMP2_CSR_CALOUT_Msk             (0x1UL << OPAMP2_CSR_CALOUT_Pos)     /*!< 0x40000000 */

+#define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */

+

+/*******************  Bit definition for OPAMP_OTR register  ******************/

+#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */

+#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP1_OTR register  ******************/

+#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */

+#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP2_OTR register  ******************/

+#define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */

+#define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP_HSOTR register  ****************/

+#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP_HSOTR_TRIMHSOFFSETN        OPAMP_HSOTR_TRIMHSOFFSETN_Msk         /*!< Trim for NMOS differential pairs */

+#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP_HSOTR_TRIMHSOFFSETP        OPAMP_HSOTR_TRIMHSOFFSETP_Msk         /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP1_HSOTR register  ****************/

+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP1_HSOTR_TRIMHSOFFSETN        OPAMP1_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */

+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP1_HSOTR_TRIMHSOFFSETP        OPAMP1_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP2_HSOTR register  ****************/

+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP2_HSOTR_TRIMHSOFFSETN        OPAMP2_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */

+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP2_HSOTR_TRIMHSOFFSETP        OPAMP2_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             Power Control                                  */

+/*                                                                            */

+/******************************************************************************/

+/*************************  NUMBER OF POWER DOMAINS  **************************/

+#define POWER_DOMAINS_NUMBER           3U                                      /*!< 3 Domains */

+

+/********************  Bit definition for PWR_CR1 register  *******************/

+#define PWR_CR1_ALS_Pos                (17U)

+#define PWR_CR1_ALS_Msk                (0x3UL << PWR_CR1_ALS_Pos)              /*!< 0x00060000 */

+#define PWR_CR1_ALS                    PWR_CR1_ALS_Msk                         /*!< Analog Voltage Detector level selection */

+#define PWR_CR1_ALS_0                  (0x1UL << PWR_CR1_ALS_Pos)              /*!< 0x00020000 */

+#define PWR_CR1_ALS_1                  (0x2UL << PWR_CR1_ALS_Pos)              /*!< 0x00040000 */

+#define PWR_CR1_AVDEN_Pos              (16U)

+#define PWR_CR1_AVDEN_Msk              (0x1UL << PWR_CR1_AVDEN_Pos)            /*!< 0x00010000 */

+#define PWR_CR1_AVDEN                  PWR_CR1_AVDEN_Msk                       /*!< Analog Voltage Detector Enable */

+#define PWR_CR1_SVOS_Pos               (14U)

+#define PWR_CR1_SVOS_Msk               (0x3UL << PWR_CR1_SVOS_Pos)             /*!< 0x0000C000 */

+#define PWR_CR1_SVOS                   PWR_CR1_SVOS_Msk                        /*!< System STOP mode Voltage Scaling selection */

+#define PWR_CR1_SVOS_0                 (0x1UL << PWR_CR1_SVOS_Pos)             /*!< 0x00004000 */

+#define PWR_CR1_SVOS_1                 (0x2UL << PWR_CR1_SVOS_Pos)             /*!< 0x00008000 */

+#define PWR_CR1_FLPS_Pos               (9U)

+#define PWR_CR1_FLPS_Msk               (0x1UL << PWR_CR1_FLPS_Pos)             /*!< 0x00000200 */

+#define PWR_CR1_FLPS                   PWR_CR1_FLPS_Msk                        /*!< Flash low power mode in DSTOP */

+#define PWR_CR1_DBP_Pos                (8U)

+#define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */

+#define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable Back-up domain Protection */

+#define PWR_CR1_PLS_Pos                (5U)

+#define PWR_CR1_PLS_Msk                (0x7UL << PWR_CR1_PLS_Pos)              /*!< 0x000000E0 */

+#define PWR_CR1_PLS                    PWR_CR1_PLS_Msk                         /*!< Programmable Voltage Detector level selection */

+#define PWR_CR1_PLS_0                  (0x1UL << PWR_CR1_PLS_Pos)              /*!< 0x00000020 */

+#define PWR_CR1_PLS_1                  (0x2UL << PWR_CR1_PLS_Pos)              /*!< 0x00000040 */

+#define PWR_CR1_PLS_2                  (0x4UL << PWR_CR1_PLS_Pos)              /*!< 0x00000080 */

+#define PWR_CR1_PVDEN_Pos              (4U)

+#define PWR_CR1_PVDEN_Msk              (0x1UL << PWR_CR1_PVDEN_Pos)            /*!< 0x00000010 */

+#define PWR_CR1_PVDEN                  PWR_CR1_PVDEN_Msk                       /*!< Programmable Voltage detector enable */

+#define PWR_CR1_LPDS_Pos               (0U)

+#define PWR_CR1_LPDS_Msk               (0x1UL << PWR_CR1_LPDS_Pos)             /*!< 0x00000001 */

+#define PWR_CR1_LPDS                   PWR_CR1_LPDS_Msk                        /*!< Low Power Deepsleep with SVOS3 */

+

+/*!< PVD level configuration */

+#define PWR_CR1_PLS_LEV0               (0UL)                                   /*!< PVD level 0 */

+#define PWR_CR1_PLS_LEV1_Pos           (5U)

+#define PWR_CR1_PLS_LEV1_Msk           (0x1UL << PWR_CR1_PLS_LEV1_Pos)         /*!< 0x00000020 */

+#define PWR_CR1_PLS_LEV1               PWR_CR1_PLS_LEV1_Msk                    /*!< PVD level 1 */

+#define PWR_CR1_PLS_LEV2_Pos           (6U)

+#define PWR_CR1_PLS_LEV2_Msk           (0x1UL << PWR_CR1_PLS_LEV2_Pos)         /*!< 0x00000040 */

+#define PWR_CR1_PLS_LEV2               PWR_CR1_PLS_LEV2_Msk                    /*!< PVD level 2 */

+#define PWR_CR1_PLS_LEV3_Pos           (5U)

+#define PWR_CR1_PLS_LEV3_Msk           (0x3UL << PWR_CR1_PLS_LEV3_Pos)         /*!< 0x00000060 */

+#define PWR_CR1_PLS_LEV3               PWR_CR1_PLS_LEV3_Msk                    /*!< PVD level 3 */

+#define PWR_CR1_PLS_LEV4_Pos           (7U)

+#define PWR_CR1_PLS_LEV4_Msk           (0x1UL << PWR_CR1_PLS_LEV4_Pos)         /*!< 0x00000080 */

+#define PWR_CR1_PLS_LEV4               PWR_CR1_PLS_LEV4_Msk                    /*!< PVD level 4 */

+#define PWR_CR1_PLS_LEV5_Pos           (5U)

+#define PWR_CR1_PLS_LEV5_Msk           (0x5UL << PWR_CR1_PLS_LEV5_Pos)         /*!< 0x000000A0 */

+#define PWR_CR1_PLS_LEV5               PWR_CR1_PLS_LEV5_Msk                    /*!< PVD level 5 */

+#define PWR_CR1_PLS_LEV6_Pos           (6U)

+#define PWR_CR1_PLS_LEV6_Msk           (0x3UL << PWR_CR1_PLS_LEV6_Pos)         /*!< 0x000000C0 */

+#define PWR_CR1_PLS_LEV6               PWR_CR1_PLS_LEV6_Msk                    /*!< PVD level 6 */

+#define PWR_CR1_PLS_LEV7_Pos           (5U)

+#define PWR_CR1_PLS_LEV7_Msk           (0x7UL << PWR_CR1_PLS_LEV7_Pos)         /*!< 0x000000E0 */

+#define PWR_CR1_PLS_LEV7               PWR_CR1_PLS_LEV7_Msk                    /*!< PVD level 7 */

+

+/*!< AVD level configuration */

+#define PWR_CR1_ALS_LEV0               (0UL)                                   /*!< AVD level 0 */

+#define PWR_CR1_ALS_LEV1_Pos           (17U)

+#define PWR_CR1_ALS_LEV1_Msk           (0x1UL << PWR_CR1_ALS_LEV1_Pos)         /*!< 0x00020000 */

+#define PWR_CR1_ALS_LEV1               PWR_CR1_ALS_LEV1_Msk                    /*!< AVD level 1 */

+#define PWR_CR1_ALS_LEV2_Pos           (18U)

+#define PWR_CR1_ALS_LEV2_Msk           (0x1UL << PWR_CR1_ALS_LEV2_Pos)         /*!< 0x00040000 */

+#define PWR_CR1_ALS_LEV2               PWR_CR1_ALS_LEV2_Msk                    /*!< AVD level 2 */

+#define PWR_CR1_ALS_LEV3_Pos           (17U)

+#define PWR_CR1_ALS_LEV3_Msk           (0x3UL << PWR_CR1_ALS_LEV3_Pos)         /*!< 0x00060000 */

+#define PWR_CR1_ALS_LEV3               PWR_CR1_ALS_LEV3_Msk                    /*!< AVD level 3 */

+

+/********************  Bit definition for PWR_CSR1 register  ******************/

+#define PWR_CSR1_AVDO_Pos              (16U)

+#define PWR_CSR1_AVDO_Msk              (0x1UL << PWR_CSR1_AVDO_Pos)            /*!< 0x00010000 */

+#define PWR_CSR1_AVDO                  PWR_CSR1_AVDO_Msk                       /*!< Analog Voltage Detect Output */

+#define PWR_CSR1_ACTVOS_Pos            (14U)

+#define PWR_CSR1_ACTVOS_Msk            (0x3UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x0000C000 */

+#define PWR_CSR1_ACTVOS                PWR_CSR1_ACTVOS_Msk                     /*!< Current actual used VOS for VDD11 Voltage Scaling */

+#define PWR_CSR1_ACTVOS_0              (0x1UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00004000 */

+#define PWR_CSR1_ACTVOS_1              (0x2UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00008000 */

+#define PWR_CSR1_ACTVOSRDY_Pos         (13U)

+#define PWR_CSR1_ACTVOSRDY_Msk         (0x1UL << PWR_CSR1_ACTVOSRDY_Pos)       /*!< 0x00002000 */

+#define PWR_CSR1_ACTVOSRDY             PWR_CSR1_ACTVOSRDY_Msk                  /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling  */

+#define PWR_CSR1_PVDO_Pos              (4U)

+#define PWR_CSR1_PVDO_Msk              (0x1UL << PWR_CSR1_PVDO_Pos)            /*!< 0x00000010 */

+#define PWR_CSR1_PVDO                  PWR_CSR1_PVDO_Msk                       /*!< Programmable Voltage Detect Output */

+

+/********************  Bit definition for PWR_CR2 register  *******************/

+#define PWR_CR2_TEMPH_Pos              (23U)

+#define PWR_CR2_TEMPH_Msk              (0x1UL << PWR_CR2_TEMPH_Pos)            /*!< 0x00800000 */

+#define PWR_CR2_TEMPH                  PWR_CR2_TEMPH_Msk                       /*!< Monitored temperature level above high threshold */

+#define PWR_CR2_TEMPL_Pos              (22U)

+#define PWR_CR2_TEMPL_Msk              (0x1UL << PWR_CR2_TEMPL_Pos)            /*!< 0x00400000 */

+#define PWR_CR2_TEMPL                  PWR_CR2_TEMPL_Msk                       /*!< Monitored temperature level above low threshold */

+#define PWR_CR2_VBATH_Pos              (21U)

+#define PWR_CR2_VBATH_Msk              (0x1UL << PWR_CR2_VBATH_Pos)            /*!< 0x00200000 */

+#define PWR_CR2_VBATH                  PWR_CR2_VBATH_Msk                       /*!< Monitored VBAT level above high threshold */

+#define PWR_CR2_VBATL_Pos              (20U)

+#define PWR_CR2_VBATL_Msk              (0x1UL << PWR_CR2_VBATL_Pos)            /*!< 0x00100000 */

+#define PWR_CR2_VBATL                  PWR_CR2_VBATL_Msk                       /*!< Monitored VBAT level above low threshold */

+#define PWR_CR2_BRRDY_Pos              (16U)

+#define PWR_CR2_BRRDY_Msk              (0x1UL << PWR_CR2_BRRDY_Pos)            /*!< 0x00010000 */

+#define PWR_CR2_BRRDY                  PWR_CR2_BRRDY_Msk                       /*!< Backup regulator ready */

+#define PWR_CR2_MONEN_Pos              (4U)

+#define PWR_CR2_MONEN_Msk              (0x1UL << PWR_CR2_MONEN_Pos)            /*!< 0x00000010 */

+#define PWR_CR2_MONEN                  PWR_CR2_MONEN_Msk                       /*!< VBAT and temperature monitoring enable */

+#define PWR_CR2_BREN_Pos               (0U)

+#define PWR_CR2_BREN_Msk               (0x1UL << PWR_CR2_BREN_Pos)             /*!< 0x00000001 */

+#define PWR_CR2_BREN                   PWR_CR2_BREN_Msk                        /*!< Backup regulator enable */

+

+/********************  Bit definition for PWR_CR3 register  *******************/

+#define PWR_CR3_USB33RDY_Pos           (26U)

+#define PWR_CR3_USB33RDY_Msk           (0x1UL << PWR_CR3_USB33RDY_Pos)         /*!< 0x04000000 */

+#define PWR_CR3_USB33RDY               PWR_CR3_USB33RDY_Msk                    /*!< USB supply ready */

+#define PWR_CR3_USBREGEN_Pos           (25U)

+#define PWR_CR3_USBREGEN_Msk           (0x1UL << PWR_CR3_USBREGEN_Pos)         /*!< 0x02000000 */

+#define PWR_CR3_USBREGEN               PWR_CR3_USBREGEN_Msk                    /*!< USB regulator enable */

+#define PWR_CR3_USB33DEN_Pos           (24U)

+#define PWR_CR3_USB33DEN_Msk           (0x1UL << PWR_CR3_USB33DEN_Pos)         /*!< 0x01000000 */

+#define PWR_CR3_USB33DEN               PWR_CR3_USB33DEN_Msk                    /*!< VDD33_USB voltage level detector enable */

+#define PWR_CR3_VBRS_Pos               (9U)

+#define PWR_CR3_VBRS_Msk               (0x1UL << PWR_CR3_VBRS_Pos)             /*!< 0x00000200 */

+#define PWR_CR3_VBRS                   PWR_CR3_VBRS_Msk                        /*!< VBAT charging resistor selection */

+#define PWR_CR3_VBE_Pos                (8U)

+#define PWR_CR3_VBE_Msk                (0x1UL << PWR_CR3_VBE_Pos)              /*!< 0x00000100 */

+#define PWR_CR3_VBE                    PWR_CR3_VBE_Msk                         /*!< VBAT charging enable */

+#define PWR_CR3_SCUEN_Pos              (2U)

+#define PWR_CR3_SCUEN_Msk              (0x1UL << PWR_CR3_SCUEN_Pos)            /*!< 0x00000004 */

+#define PWR_CR3_SCUEN                  PWR_CR3_SCUEN_Msk                       /*!< Supply configuration update enable */

+#define PWR_CR3_LDOEN_Pos              (1U)

+#define PWR_CR3_LDOEN_Msk              (0x1UL << PWR_CR3_LDOEN_Pos)            /*!< 0x00000002 */

+#define PWR_CR3_LDOEN                  PWR_CR3_LDOEN_Msk                       /*!< Low Drop Output regulator enable */

+#define PWR_CR3_BYPASS_Pos             (0U)

+#define PWR_CR3_BYPASS_Msk             (0x1UL << PWR_CR3_BYPASS_Pos)           /*!< 0x00000001 */

+#define PWR_CR3_BYPASS                 PWR_CR3_BYPASS_Msk                      /*!< Power Management Unit bypass */

+

+/********************  Bit definition for PWR_CPUCR register  *****************/

+#define PWR_CPUCR_RUN_D3_Pos           (11U)

+#define PWR_CPUCR_RUN_D3_Msk           (0x1UL << PWR_CPUCR_RUN_D3_Pos)         /*!< 0x00000800 */

+#define PWR_CPUCR_RUN_D3               PWR_CPUCR_RUN_D3_Msk                    /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */

+#define PWR_CPUCR_CSSF_Pos             (9U)

+#define PWR_CPUCR_CSSF_Msk             (0x1UL << PWR_CPUCR_CSSF_Pos)           /*!< 0x00000200 */

+#define PWR_CPUCR_CSSF                 PWR_CPUCR_CSSF_Msk                      /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */

+#define PWR_CPUCR_SBF_D2_Pos           (8U)

+#define PWR_CPUCR_SBF_D2_Msk           (0x1UL << PWR_CPUCR_SBF_D2_Pos)         /*!< 0x00000100 */

+#define PWR_CPUCR_SBF_D2               PWR_CPUCR_SBF_D2_Msk                    /*!< D2 domain DSTANDBY Flag */

+#define PWR_CPUCR_SBF_D1_Pos           (7U)

+#define PWR_CPUCR_SBF_D1_Msk           (0x1UL << PWR_CPUCR_SBF_D1_Pos)         /*!< 0x00000080 */

+#define PWR_CPUCR_SBF_D1               PWR_CPUCR_SBF_D1_Msk                    /*!< D1 domain DSTANDBY Flag */

+#define PWR_CPUCR_SBF_Pos              (6U)

+#define PWR_CPUCR_SBF_Msk              (0x1UL << PWR_CPUCR_SBF_Pos)            /*!< 0x00000040 */

+#define PWR_CPUCR_SBF                  PWR_CPUCR_SBF_Msk                       /*!< System STANDBY Flag */

+#define PWR_CPUCR_STOPF_Pos            (5U)

+#define PWR_CPUCR_STOPF_Msk            (0x1UL << PWR_CPUCR_STOPF_Pos)          /*!< 0x00000020 */

+#define PWR_CPUCR_STOPF                PWR_CPUCR_STOPF_Msk                     /*!< STOP Flag */

+#define PWR_CPUCR_PDDS_D3_Pos          (2U)

+#define PWR_CPUCR_PDDS_D3_Msk          (0x1UL << PWR_CPUCR_PDDS_D3_Pos)        /*!< 0x00000004 */

+#define PWR_CPUCR_PDDS_D3              PWR_CPUCR_PDDS_D3_Msk                   /*!< System D3 domain Power Down Deepsleep */

+#define PWR_CPUCR_PDDS_D2_Pos          (1U)

+#define PWR_CPUCR_PDDS_D2_Msk          (0x1UL << PWR_CPUCR_PDDS_D2_Pos)        /*!< 0x00000002 */

+#define PWR_CPUCR_PDDS_D2              PWR_CPUCR_PDDS_D2_Msk                   /*!< D2 domain Power Down Deepsleep */

+#define PWR_CPUCR_PDDS_D1_Pos          (0U)

+#define PWR_CPUCR_PDDS_D1_Msk          (0x1UL << PWR_CPUCR_PDDS_D1_Pos)        /*!< 0x00000001 */

+#define PWR_CPUCR_PDDS_D1              PWR_CPUCR_PDDS_D1_Msk                   /*!< D1 domain Power Down Deepsleep selection */

+

+

+/********************  Bit definition for PWR_D3CR register  ******************/

+#define PWR_D3CR_VOS_Pos               (14U)

+#define PWR_D3CR_VOS_Msk               (0x3UL << PWR_D3CR_VOS_Pos)             /*!< 0x0000C000 */

+#define PWR_D3CR_VOS                   PWR_D3CR_VOS_Msk                        /*!< Voltage Scaling selection according performance */

+#define PWR_D3CR_VOS_0                 (0x1UL << PWR_D3CR_VOS_Pos)             /*!< 0x00004000 */

+#define PWR_D3CR_VOS_1                 (0x2UL << PWR_D3CR_VOS_Pos)             /*!< 0x00008000 */

+#define PWR_D3CR_VOSRDY_Pos            (13U)

+#define PWR_D3CR_VOSRDY_Msk            (0x1UL << PWR_D3CR_VOSRDY_Pos)          /*!< 0x00002000 */

+#define PWR_D3CR_VOSRDY                PWR_D3CR_VOSRDY_Msk                     /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */

+

+/******************  Bit definition for PWR_WKUPCR register  ******************/

+#define PWR_WKUPCR_WKUPC6_Pos          (5U)

+#define PWR_WKUPCR_WKUPC6_Msk          (0x1UL << PWR_WKUPCR_WKUPC6_Pos)        /*!< 0x00000020 */

+#define PWR_WKUPCR_WKUPC6              PWR_WKUPCR_WKUPC6_Msk                   /*!< Clear Wakeup Pin Flag 6 */

+#define PWR_WKUPCR_WKUPC5_Pos          (4U)

+#define PWR_WKUPCR_WKUPC5_Msk          (0x1UL << PWR_WKUPCR_WKUPC5_Pos)        /*!< 0x00000010 */

+#define PWR_WKUPCR_WKUPC5              PWR_WKUPCR_WKUPC5_Msk                   /*!< Clear Wakeup Pin Flag 5 */

+#define PWR_WKUPCR_WKUPC4_Pos          (3U)

+#define PWR_WKUPCR_WKUPC4_Msk          (0x1UL << PWR_WKUPCR_WKUPC4_Pos)        /*!< 0x00000008 */

+#define PWR_WKUPCR_WKUPC4              PWR_WKUPCR_WKUPC4_Msk                   /*!< Clear Wakeup Pin Flag 4 */

+#define PWR_WKUPCR_WKUPC3_Pos          (2U)

+#define PWR_WKUPCR_WKUPC3_Msk          (0x1UL << PWR_WKUPCR_WKUPC3_Pos)        /*!< 0x00000004 */

+#define PWR_WKUPCR_WKUPC3              PWR_WKUPCR_WKUPC3_Msk                   /*!< Clear Wakeup Pin Flag 3 */

+#define PWR_WKUPCR_WKUPC2_Pos          (1U)

+#define PWR_WKUPCR_WKUPC2_Msk          (0x1UL << PWR_WKUPCR_WKUPC2_Pos)        /*!< 0x00000002 */

+#define PWR_WKUPCR_WKUPC2              PWR_WKUPCR_WKUPC2_Msk                   /*!< Clear Wakeup Pin Flag 2 */

+#define PWR_WKUPCR_WKUPC1_Pos          (0U)

+#define PWR_WKUPCR_WKUPC1_Msk          (0x1UL << PWR_WKUPCR_WKUPC1_Pos)        /*!< 0x00000001 */

+#define PWR_WKUPCR_WKUPC1              PWR_WKUPCR_WKUPC1_Msk                   /*!< Clear Wakeup Pin Flag 1 */

+

+/********************  Bit definition for PWR_WKUPFR register  ****************/

+#define PWR_WKUPFR_WKUPF6_Pos          (5U)

+#define PWR_WKUPFR_WKUPF6_Msk          (0x1UL << PWR_WKUPFR_WKUPF6_Pos)        /*!< 0x00000020 */

+#define PWR_WKUPFR_WKUPF6              PWR_WKUPFR_WKUPF6_Msk                   /*!< Wakeup Pin Flag 6 */

+#define PWR_WKUPFR_WKUPF5_Pos          (4U)

+#define PWR_WKUPFR_WKUPF5_Msk          (0x1UL << PWR_WKUPFR_WKUPF5_Pos)        /*!< 0x00000010 */

+#define PWR_WKUPFR_WKUPF5              PWR_WKUPFR_WKUPF5_Msk                   /*!< Wakeup Pin Flag 5 */

+#define PWR_WKUPFR_WKUPF4_Pos          (3U)

+#define PWR_WKUPFR_WKUPF4_Msk          (0x1UL << PWR_WKUPFR_WKUPF4_Pos)        /*!< 0x00000008 */

+#define PWR_WKUPFR_WKUPF4              PWR_WKUPFR_WKUPF4_Msk                   /*!< Wakeup Pin Flag 4 */

+#define PWR_WKUPFR_WKUPF3_Pos          (2U)

+#define PWR_WKUPFR_WKUPF3_Msk          (0x1UL << PWR_WKUPFR_WKUPF3_Pos)        /*!< 0x00000004 */

+#define PWR_WKUPFR_WKUPF3              PWR_WKUPFR_WKUPF3_Msk                   /*!< Wakeup Pin Flag 3 */

+#define PWR_WKUPFR_WKUPF2_Pos          (1U)

+#define PWR_WKUPFR_WKUPF2_Msk          (0x1UL << PWR_WKUPFR_WKUPF2_Pos)        /*!< 0x00000002 */

+#define PWR_WKUPFR_WKUPF2              PWR_WKUPFR_WKUPF2_Msk                   /*!< Wakeup Pin Flag 2 */

+#define PWR_WKUPFR_WKUPF1_Pos          (0U)

+#define PWR_WKUPFR_WKUPF1_Msk          (0x1UL << PWR_WKUPFR_WKUPF1_Pos)        /*!< 0x00000001 */

+#define PWR_WKUPFR_WKUPF1              PWR_WKUPFR_WKUPF1_Msk                   /*!< Wakeup Pin Flag 1 */

+

+/******************  Bit definition for PWR_WKUPEPR register  *****************/

+#define PWR_WKUPEPR_WKUPPUPD6_Pos      (26U)

+#define PWR_WKUPEPR_WKUPPUPD6_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x0C000000 */

+#define PWR_WKUPEPR_WKUPPUPD6          PWR_WKUPEPR_WKUPPUPD6_Msk               /*!< Wakeup Pin pull configuration for WKUP6 */

+#define PWR_WKUPEPR_WKUPPUPD6_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x04000000 */

+#define PWR_WKUPEPR_WKUPPUPD6_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x08000000 */

+#define PWR_WKUPEPR_WKUPPUPD5_Pos      (24U)

+#define PWR_WKUPEPR_WKUPPUPD5_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x03000000 */

+#define PWR_WKUPEPR_WKUPPUPD5          PWR_WKUPEPR_WKUPPUPD5_Msk               /*!< Wakeup Pin pull configuration for WKUP5 */

+#define PWR_WKUPEPR_WKUPPUPD5_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x01000000 */

+#define PWR_WKUPEPR_WKUPPUPD5_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x02000000 */

+#define PWR_WKUPEPR_WKUPPUPD4_Pos      (22U)

+#define PWR_WKUPEPR_WKUPPUPD4_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00C00000 */

+#define PWR_WKUPEPR_WKUPPUPD4          PWR_WKUPEPR_WKUPPUPD4_Msk               /*!< Wakeup Pin pull configuration for WKUP4 */

+#define PWR_WKUPEPR_WKUPPUPD4_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00400000 */

+#define PWR_WKUPEPR_WKUPPUPD4_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00800000 */

+#define PWR_WKUPEPR_WKUPPUPD3_Pos      (20U)

+#define PWR_WKUPEPR_WKUPPUPD3_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00300000 */

+#define PWR_WKUPEPR_WKUPPUPD3          PWR_WKUPEPR_WKUPPUPD3_Msk               /*!< Wakeup Pin pull configuration for WKUP3 */

+#define PWR_WKUPEPR_WKUPPUPD3_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00100000 */

+#define PWR_WKUPEPR_WKUPPUPD3_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00200000 */

+#define PWR_WKUPEPR_WKUPPUPD2_Pos      (18U)

+#define PWR_WKUPEPR_WKUPPUPD2_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x000C0000 */

+#define PWR_WKUPEPR_WKUPPUPD2          PWR_WKUPEPR_WKUPPUPD2_Msk               /*!< Wakeup Pin pull configuration for WKUP2 */

+#define PWR_WKUPEPR_WKUPPUPD2_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00040000 */

+#define PWR_WKUPEPR_WKUPPUPD2_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00080000 */

+#define PWR_WKUPEPR_WKUPPUPD1_Pos      (16U)

+#define PWR_WKUPEPR_WKUPPUPD1_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00030000 */

+#define PWR_WKUPEPR_WKUPPUPD1          PWR_WKUPEPR_WKUPPUPD1_Msk               /*!< Wakeup Pin pull configuration for WKUP1 */

+#define PWR_WKUPEPR_WKUPPUPD1_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00010000 */

+#define PWR_WKUPEPR_WKUPPUPD1_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00020000 */

+#define PWR_WKUPEPR_WKUPP6_Pos         (13U)

+#define PWR_WKUPEPR_WKUPP6_Msk         (0x1UL << PWR_WKUPEPR_WKUPP6_Pos)       /*!< 0x00002000 */

+#define PWR_WKUPEPR_WKUPP6             PWR_WKUPEPR_WKUPP6_Msk                  /*!< Wakeup Pin Polarity for WKUP6 */

+#define PWR_WKUPEPR_WKUPP5_Pos         (12U)

+#define PWR_WKUPEPR_WKUPP5_Msk         (0x1UL << PWR_WKUPEPR_WKUPP5_Pos)       /*!< 0x00001000 */

+#define PWR_WKUPEPR_WKUPP5             PWR_WKUPEPR_WKUPP5_Msk                  /*!< Wakeup Pin Polarity for WKUP5 */

+#define PWR_WKUPEPR_WKUPP4_Pos         (11U)

+#define PWR_WKUPEPR_WKUPP4_Msk         (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)       /*!< 0x00000800 */

+#define PWR_WKUPEPR_WKUPP4             PWR_WKUPEPR_WKUPP4_Msk                  /*!< Wakeup Pin Polarity for WKUP4 */

+#define PWR_WKUPEPR_WKUPP3_Pos         (10U)

+#define PWR_WKUPEPR_WKUPP3_Msk         (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)       /*!< 0x00000400 */

+#define PWR_WKUPEPR_WKUPP3             PWR_WKUPEPR_WKUPP3_Msk                  /*!< Wakeup Pin Polarity for WKUP3 */

+#define PWR_WKUPEPR_WKUPP2_Pos         (9U)

+#define PWR_WKUPEPR_WKUPP2_Msk         (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)       /*!< 0x00000200 */

+#define PWR_WKUPEPR_WKUPP2             PWR_WKUPEPR_WKUPP2_Msk                  /*!< Wakeup Pin Polarity for WKUP2 */

+#define PWR_WKUPEPR_WKUPP1_Pos         (8U)

+#define PWR_WKUPEPR_WKUPP1_Msk         (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)       /*!< 0x00000100 */

+#define PWR_WKUPEPR_WKUPP1             PWR_WKUPEPR_WKUPP1_Msk                  /*!< Wakeup Pin Polarity for WKUP1 */

+#define PWR_WKUPEPR_WKUPEN6_Pos        (5U)

+#define PWR_WKUPEPR_WKUPEN6_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos)      /*!< 0x00000020 */

+#define PWR_WKUPEPR_WKUPEN6            PWR_WKUPEPR_WKUPEN6_Msk                 /*!< Enable Wakeup Pin WKUP6 */

+#define PWR_WKUPEPR_WKUPEN5_Pos        (4U)

+#define PWR_WKUPEPR_WKUPEN5_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos)      /*!< 0x00000010 */

+#define PWR_WKUPEPR_WKUPEN5            PWR_WKUPEPR_WKUPEN5_Msk                 /*!< Enable Wakeup Pin WKUP5 */

+#define PWR_WKUPEPR_WKUPEN4_Pos        (3U)

+#define PWR_WKUPEPR_WKUPEN4_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)      /*!< 0x00000008 */

+#define PWR_WKUPEPR_WKUPEN4            PWR_WKUPEPR_WKUPEN4_Msk                 /*!< Enable Wakeup Pin WKUP4 */

+#define PWR_WKUPEPR_WKUPEN3_Pos        (2U)

+#define PWR_WKUPEPR_WKUPEN3_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)      /*!< 0x00000004 */

+#define PWR_WKUPEPR_WKUPEN3            PWR_WKUPEPR_WKUPEN3_Msk                 /*!< Enable Wakeup Pin WKUP3 */

+#define PWR_WKUPEPR_WKUPEN2_Pos        (1U)

+#define PWR_WKUPEPR_WKUPEN2_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)      /*!< 0x00000002 */

+#define PWR_WKUPEPR_WKUPEN2            PWR_WKUPEPR_WKUPEN2_Msk                 /*!< Enable Wakeup Pin WKUP2 */

+#define PWR_WKUPEPR_WKUPEN1_Pos        (0U)

+#define PWR_WKUPEPR_WKUPEN1_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)      /*!< 0x00000001 */

+#define PWR_WKUPEPR_WKUPEN1            PWR_WKUPEPR_WKUPEN1_Msk                 /*!< Enable Wakeup Pin WKUP1 */

+#define PWR_WKUPEPR_WKUPEN_Pos         (0U)

+#define PWR_WKUPEPR_WKUPEN_Msk         (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos)      /*!< 0x0000003F */

+#define PWR_WKUPEPR_WKUPEN             PWR_WKUPEPR_WKUPEN_Msk                  /*!< Enable all Wakeup Pin */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Reset and Clock Control                            */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  RCC VERSION  ********************************/

+#define RCC_VER_X

+

+/********************  Bit definition for RCC_CR register  ********************/

+#define RCC_CR_HSION_Pos                       (0U)

+#define RCC_CR_HSION_Msk                       (0x1UL << RCC_CR_HSION_Pos)     /*!< 0x00000001 */

+#define RCC_CR_HSION                           RCC_CR_HSION_Msk                /*!< Internal High Speed clock enable */

+#define RCC_CR_HSIKERON_Pos                    (1U)

+#define RCC_CR_HSIKERON_Msk                    (0x1UL << RCC_CR_HSIKERON_Pos)  /*!< 0x00000002 */

+#define RCC_CR_HSIKERON                        RCC_CR_HSIKERON_Msk             /*!< Internal High Speed clock enable for some IPs Kernel */

+#define RCC_CR_HSIRDY_Pos                      (2U)

+#define RCC_CR_HSIRDY_Msk                      (0x1UL << RCC_CR_HSIRDY_Pos)    /*!< 0x00000004 */

+#define RCC_CR_HSIRDY                          RCC_CR_HSIRDY_Msk               /*!< Internal High Speed clock ready flag */

+#define RCC_CR_HSIDIV_Pos                      (3U)

+#define RCC_CR_HSIDIV_Msk                      (0x3UL << RCC_CR_HSIDIV_Pos)    /*!< 0x00000018 */

+#define RCC_CR_HSIDIV                          RCC_CR_HSIDIV_Msk               /*!< Internal High Speed clock divider selection */

+#define RCC_CR_HSIDIV_1                        (0x0UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000000 */

+#define RCC_CR_HSIDIV_2                        (0x1UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000008 */

+#define RCC_CR_HSIDIV_4                        (0x2UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000010 */

+#define RCC_CR_HSIDIV_8                        (0x3UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000018 */

+

+#define RCC_CR_HSIDIVF_Pos                     (5U)

+#define RCC_CR_HSIDIVF_Msk                     (0x1UL << RCC_CR_HSIDIVF_Pos)   /*!< 0x00000020 */

+#define RCC_CR_HSIDIVF                         RCC_CR_HSIDIVF_Msk              /*!< HSI Divider flag */

+#define RCC_CR_CSION_Pos                       (7U)

+#define RCC_CR_CSION_Msk                       (0x1UL << RCC_CR_CSION_Pos)     /*!< 0x00000080 */

+#define RCC_CR_CSION                           RCC_CR_CSION_Msk                /*!< The Internal RC 4MHz oscillator clock enable */

+#define RCC_CR_CSIRDY_Pos                      (8U)

+#define RCC_CR_CSIRDY_Msk                      (0x1UL << RCC_CR_CSIRDY_Pos)    /*!< 0x00000100 */

+#define RCC_CR_CSIRDY                          RCC_CR_CSIRDY_Msk               /*!< The Internal RC 4MHz oscillator clock ready */

+#define RCC_CR_CSIKERON_Pos                    (9U)

+#define RCC_CR_CSIKERON_Msk                    (0x1UL << RCC_CR_CSIKERON_Pos)  /*!< 0x00000200 */

+#define RCC_CR_CSIKERON                        RCC_CR_CSIKERON_Msk             /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */

+#define RCC_CR_HSI48ON_Pos                     (12U)

+#define RCC_CR_HSI48ON_Msk                     (0x1UL << RCC_CR_HSI48ON_Pos)   /*!< 0x00001000 */

+#define RCC_CR_HSI48ON                         RCC_CR_HSI48ON_Msk              /*!< HSI48 clock enable clock enable  */

+#define RCC_CR_HSI48RDY_Pos                    (13U)

+#define RCC_CR_HSI48RDY_Msk                    (0x1UL << RCC_CR_HSI48RDY_Pos)  /*!< 0x00002000 */

+#define RCC_CR_HSI48RDY                        RCC_CR_HSI48RDY_Msk             /*!< HSI48 clock ready */

+

+#define RCC_CR_D1CKRDY_Pos                     (14U)

+#define RCC_CR_D1CKRDY_Msk                     (0x1UL << RCC_CR_D1CKRDY_Pos)   /*!< 0x00004000 */

+#define RCC_CR_D1CKRDY                         RCC_CR_D1CKRDY_Msk              /*!< D1 domain clocks ready flag  */

+#define RCC_CR_D2CKRDY_Pos                     (15U)

+#define RCC_CR_D2CKRDY_Msk                     (0x1UL << RCC_CR_D2CKRDY_Pos)   /*!< 0x00008000 */

+#define RCC_CR_D2CKRDY                         RCC_CR_D2CKRDY_Msk              /*!< D2 domain clocks ready flag */

+

+#define RCC_CR_HSEON_Pos                       (16U)

+#define RCC_CR_HSEON_Msk                       (0x1UL << RCC_CR_HSEON_Pos)     /*!< 0x00010000 */

+#define RCC_CR_HSEON                           RCC_CR_HSEON_Msk                /*!< External High Speed clock enable */

+#define RCC_CR_HSERDY_Pos                      (17U)

+#define RCC_CR_HSERDY_Msk                      (0x1UL << RCC_CR_HSERDY_Pos)    /*!< 0x00020000 */

+#define RCC_CR_HSERDY                          RCC_CR_HSERDY_Msk               /*!< External High Speed clock ready */

+#define RCC_CR_HSEBYP_Pos                      (18U)

+#define RCC_CR_HSEBYP_Msk                      (0x1UL << RCC_CR_HSEBYP_Pos)    /*!< 0x00040000 */

+#define RCC_CR_HSEBYP                          RCC_CR_HSEBYP_Msk               /*!< External High Speed clock Bypass */

+#define RCC_CR_CSSHSEON_Pos                    (19U)

+#define RCC_CR_CSSHSEON_Msk                    (0x1UL << RCC_CR_CSSHSEON_Pos)  /*!< 0x00080000 */

+#define RCC_CR_CSSHSEON                        RCC_CR_CSSHSEON_Msk             /*!< HSE Clock security System enable */

+

+

+#define RCC_CR_PLL1ON_Pos                      (24U)

+#define RCC_CR_PLL1ON_Msk                      (0x1UL << RCC_CR_PLL1ON_Pos)    /*!< 0x01000000 */

+#define RCC_CR_PLL1ON                          RCC_CR_PLL1ON_Msk               /*!< System PLL1 clock enable */

+#define RCC_CR_PLL1RDY_Pos                     (25U)

+#define RCC_CR_PLL1RDY_Msk                     (0x1UL << RCC_CR_PLL1RDY_Pos)   /*!< 0x02000000 */

+#define RCC_CR_PLL1RDY                         RCC_CR_PLL1RDY_Msk              /*!< System PLL1 clock ready */

+#define RCC_CR_PLL2ON_Pos                      (26U)

+#define RCC_CR_PLL2ON_Msk                      (0x1UL << RCC_CR_PLL2ON_Pos)    /*!< 0x04000000 */

+#define RCC_CR_PLL2ON                          RCC_CR_PLL2ON_Msk               /*!< System PLL2 clock enable */

+#define RCC_CR_PLL2RDY_Pos                     (27U)

+#define RCC_CR_PLL2RDY_Msk                     (0x1UL << RCC_CR_PLL2RDY_Pos)   /*!< 0x08000000 */

+#define RCC_CR_PLL2RDY                         RCC_CR_PLL2RDY_Msk              /*!< System PLL2 clock ready */

+#define RCC_CR_PLL3ON_Pos                      (28U)

+#define RCC_CR_PLL3ON_Msk                      (0x1UL << RCC_CR_PLL3ON_Pos)    /*!< 0x10000000 */

+#define RCC_CR_PLL3ON                          RCC_CR_PLL3ON_Msk               /*!< System PLL3 clock enable */

+#define RCC_CR_PLL3RDY_Pos                     (29U)

+#define RCC_CR_PLL3RDY_Msk                     (0x1UL << RCC_CR_PLL3RDY_Pos)   /*!< 0x20000000 */

+#define RCC_CR_PLL3RDY                         RCC_CR_PLL3RDY_Msk              /*!< System PLL3 clock ready */

+

+/*Legacy */

+#define RCC_CR_PLLON_Pos                       (24U)

+#define RCC_CR_PLLON_Msk                       (0x1UL << RCC_CR_PLLON_Pos)     /*!< 0x01000000 */

+#define RCC_CR_PLLON                           RCC_CR_PLLON_Msk                /*!< System PLL clock enable */

+#define RCC_CR_PLLRDY_Pos                      (25U)

+#define RCC_CR_PLLRDY_Msk                      (0x1UL << RCC_CR_PLLRDY_Pos)    /*!< 0x02000000 */

+#define RCC_CR_PLLRDY                          RCC_CR_PLLRDY_Msk               /*!< System PLL clock ready */

+

+/********************  Bit definition for RCC_HSICFGR register  ***************/

+/*!< HSICAL configuration */

+#define RCC_HSICFGR_HSICAL_Pos                 (0U)

+#define RCC_HSICFGR_HSICAL_Msk                 (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */

+#define RCC_HSICFGR_HSICAL                     RCC_HSICFGR_HSICAL_Msk          /*!< HSICAL[11:0] bits */

+#define RCC_HSICFGR_HSICAL_0                   (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */

+#define RCC_HSICFGR_HSICAL_1                   (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */

+#define RCC_HSICFGR_HSICAL_2                   (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */

+#define RCC_HSICFGR_HSICAL_3                   (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */

+#define RCC_HSICFGR_HSICAL_4                   (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */

+#define RCC_HSICFGR_HSICAL_5                   (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */

+#define RCC_HSICFGR_HSICAL_6                   (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */

+#define RCC_HSICFGR_HSICAL_7                   (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */

+#define RCC_HSICFGR_HSICAL_8                   (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */

+#define RCC_HSICFGR_HSICAL_9                   (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */

+#define RCC_HSICFGR_HSICAL_10                  (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */

+#define RCC_HSICFGR_HSICAL_11                  (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */

+

+/*!< HSITRIM configuration */

+#define RCC_HSICFGR_HSITRIM_Pos                (24U)

+#define RCC_HSICFGR_HSITRIM_Msk                (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */

+#define RCC_HSICFGR_HSITRIM                    RCC_HSICFGR_HSITRIM_Msk         /*!< HSITRIM[6:0] bits */

+#define RCC_HSICFGR_HSITRIM_0                  (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */

+#define RCC_HSICFGR_HSITRIM_1                  (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */

+#define RCC_HSICFGR_HSITRIM_2                  (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */

+#define RCC_HSICFGR_HSITRIM_3                  (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */

+#define RCC_HSICFGR_HSITRIM_4                  (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */

+#define RCC_HSICFGR_HSITRIM_5                  (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */

+#define RCC_HSICFGR_HSITRIM_6                  (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */

+

+

+/********************  Bit definition for RCC_CRRCR register  *****************/

+

+/*!< HSI48CAL configuration */

+#define RCC_CRRCR_HSI48CAL_Pos                 (0U)

+#define RCC_CRRCR_HSI48CAL_Msk                 (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */

+#define RCC_CRRCR_HSI48CAL                     RCC_CRRCR_HSI48CAL_Msk          /*!< HSI48CAL[9:0] bits */

+#define RCC_CRRCR_HSI48CAL_0                   (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */

+#define RCC_CRRCR_HSI48CAL_1                   (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */

+#define RCC_CRRCR_HSI48CAL_2                   (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */

+#define RCC_CRRCR_HSI48CAL_3                   (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */

+#define RCC_CRRCR_HSI48CAL_4                   (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */

+#define RCC_CRRCR_HSI48CAL_5                   (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */

+#define RCC_CRRCR_HSI48CAL_6                   (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */

+#define RCC_CRRCR_HSI48CAL_7                   (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */

+#define RCC_CRRCR_HSI48CAL_8                   (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */

+#define RCC_CRRCR_HSI48CAL_9                   (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */

+

+

+/********************  Bit definition for RCC_CSICFGR register  *****************/

+/*!< CSICAL configuration */

+#define RCC_CSICFGR_CSICAL_Pos                 (0U)

+#define RCC_CSICFGR_CSICAL_Msk                 (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */

+#define RCC_CSICFGR_CSICAL                     RCC_CSICFGR_CSICAL_Msk          /*!< CSICAL[7:0] bits */

+#define RCC_CSICFGR_CSICAL_0                   (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */

+#define RCC_CSICFGR_CSICAL_1                   (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */

+#define RCC_CSICFGR_CSICAL_2                   (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */

+#define RCC_CSICFGR_CSICAL_3                   (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */

+#define RCC_CSICFGR_CSICAL_4                   (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */

+#define RCC_CSICFGR_CSICAL_5                   (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */

+#define RCC_CSICFGR_CSICAL_6                   (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */

+#define RCC_CSICFGR_CSICAL_7                   (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */

+

+/*!< CSITRIM configuration */

+#define RCC_CSICFGR_CSITRIM_Pos                (24U)

+#define RCC_CSICFGR_CSITRIM_Msk                (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */

+#define RCC_CSICFGR_CSITRIM                    RCC_CSICFGR_CSITRIM_Msk         /*!< CSITRIM[5:0] bits */

+#define RCC_CSICFGR_CSITRIM_0                  (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */

+#define RCC_CSICFGR_CSITRIM_1                  (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */

+#define RCC_CSICFGR_CSITRIM_2                  (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */

+#define RCC_CSICFGR_CSITRIM_3                  (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */

+#define RCC_CSICFGR_CSITRIM_4                  (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */

+#define RCC_CSICFGR_CSITRIM_5                  (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */

+

+/********************  Bit definition for RCC_CFGR register  ******************/

+/*!< SW configuration */

+#define RCC_CFGR_SW_Pos                        (0U)

+#define RCC_CFGR_SW_Msk                        (0x7UL << RCC_CFGR_SW_Pos)           /*!< 0x00000007 */

+#define RCC_CFGR_SW                            RCC_CFGR_SW_Msk                     /*!< SW[2:0] bits (System clock Switch) */

+#define RCC_CFGR_SW_0                          (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */

+#define RCC_CFGR_SW_1                          (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */

+#define RCC_CFGR_SW_2                          (0x4UL << RCC_CFGR_SW_Pos)           /*!< 0x00000004 */

+

+#define RCC_CFGR_SW_HSI                        (0x00000000UL)                       /*!< HSI selection as system clock */

+#define RCC_CFGR_SW_CSI                        (0x00000001UL)                       /*!< CSI selection as system clock */

+#define RCC_CFGR_SW_HSE                        (0x00000002UL)                       /*!< HSE selection as system clock */

+#define RCC_CFGR_SW_PLL1                       (0x00000003UL)                       /*!< PLL1 selection as system clock */

+

+/*!< SWS configuration */

+#define RCC_CFGR_SWS_Pos                       (3U)

+#define RCC_CFGR_SWS_Msk                       (0x7UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000038 */

+#define RCC_CFGR_SWS                           RCC_CFGR_SWS_Msk                    /*!< SWS[2:0] bits (System Clock Switch Status) */

+#define RCC_CFGR_SWS_0                         (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */

+#define RCC_CFGR_SWS_1                         (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000010 */

+#define RCC_CFGR_SWS_2                         (0x4UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000020 */

+

+#define RCC_CFGR_SWS_HSI                       (0x00000000UL)                       /*!< HSI used as system clock */

+#define RCC_CFGR_SWS_CSI                       (0x00000008UL)                       /*!< CSI used as system clock */

+#define RCC_CFGR_SWS_HSE                       (0x00000010UL)                       /*!< HSE used as system clock */

+#define RCC_CFGR_SWS_PLL1                      (0x00000018UL)                       /*!< PLL1 used as system clock */

+

+#define RCC_CFGR_STOPWUCK_Pos                  (6U)

+#define RCC_CFGR_STOPWUCK_Msk                  (0x1UL << RCC_CFGR_STOPWUCK_Pos)     /*!< 0x00000040 */

+#define RCC_CFGR_STOPWUCK                      RCC_CFGR_STOPWUCK_Msk                /*!< Wake Up from stop and CSS backup clock selection */

+

+#define RCC_CFGR_STOPKERWUCK_Pos               (7U)

+#define RCC_CFGR_STOPKERWUCK_Msk               (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)  /*!< 0x00000080 */

+#define RCC_CFGR_STOPKERWUCK                   RCC_CFGR_STOPKERWUCK_Msk             /*!< Kernel Clock Selection after a Wake Up from STOP */

+

+/*!< RTCPRE configuration */

+#define RCC_CFGR_RTCPRE_Pos                    (8U)

+#define RCC_CFGR_RTCPRE_Msk                    (0x3FUL << RCC_CFGR_RTCPRE_Pos)

+#define RCC_CFGR_RTCPRE                        RCC_CFGR_RTCPRE_Msk                  /*!< 0x00003F00 */

+#define RCC_CFGR_RTCPRE_0                      (0x1UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000100 */

+#define RCC_CFGR_RTCPRE_1                      (0x2UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000200 */

+#define RCC_CFGR_RTCPRE_2                      (0x4UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000400 */

+#define RCC_CFGR_RTCPRE_3                      (0x8UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000800 */

+#define RCC_CFGR_RTCPRE_4                      (0x10UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00001000 */

+#define RCC_CFGR_RTCPRE_5                      (0x20UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00002000 */

+

+/*!< HRTIMSEL configuration */

+#define RCC_CFGR_HRTIMSEL_Pos                  (14U)

+#define RCC_CFGR_HRTIMSEL_Msk                  (0x1UL << RCC_CFGR_HRTIMSEL_Pos)

+#define RCC_CFGR_HRTIMSEL                      RCC_CFGR_HRTIMSEL_Msk                /*!< 0x00004000 */

+

+/*!< TIMPRE configuration */

+#define RCC_CFGR_TIMPRE_Pos                    (15U)

+#define RCC_CFGR_TIMPRE_Msk                    (0x1UL << RCC_CFGR_TIMPRE_Pos)

+#define RCC_CFGR_TIMPRE                        RCC_CFGR_TIMPRE_Msk                  /*!< 0x00008000 */

+

+/*!< MCO1 configuration */

+#define RCC_CFGR_MCO1_Pos                      (22U)

+#define RCC_CFGR_MCO1_Msk                      (0x7UL << RCC_CFGR_MCO1_Pos)

+#define RCC_CFGR_MCO1                          RCC_CFGR_MCO1_Msk                       /*!< 0x01C00000 */

+#define RCC_CFGR_MCO1_0                        (0x1UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00400000 */

+#define RCC_CFGR_MCO1_1                        (0x2UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00800000 */

+#define RCC_CFGR_MCO1_2                        (0x4UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x01000000 */

+

+#define RCC_CFGR_MCO1PRE_Pos                   (18U)

+#define RCC_CFGR_MCO1PRE_Msk                   (0xFUL << RCC_CFGR_MCO1PRE_Pos)

+#define RCC_CFGR_MCO1PRE                       RCC_CFGR_MCO1PRE_Msk                    /*!< 0x003C0000 */

+#define RCC_CFGR_MCO1PRE_0                     (0x1UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00040000 */

+#define RCC_CFGR_MCO1PRE_1                     (0x2UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00080000 */

+#define RCC_CFGR_MCO1PRE_2                     (0x4UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00100000 */

+#define RCC_CFGR_MCO1PRE_3                     (0x8UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00200000 */

+

+#define RCC_CFGR_MCO2PRE_Pos                   (25U)

+#define RCC_CFGR_MCO2PRE_Msk                   (0xFUL << RCC_CFGR_MCO2PRE_Pos)

+#define RCC_CFGR_MCO2PRE                       RCC_CFGR_MCO2PRE_Msk                    /*!< 0x1E000000 */

+#define RCC_CFGR_MCO2PRE_0                     (0x1UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x02000000 */

+#define RCC_CFGR_MCO2PRE_1                     (0x2UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x04000000 */

+#define RCC_CFGR_MCO2PRE_2                     (0x4UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x08000000 */

+#define RCC_CFGR_MCO2PRE_3                     (0x8UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x10000000 */

+

+#define RCC_CFGR_MCO2_Pos                      (29U)

+#define RCC_CFGR_MCO2_Msk                      (0x7UL << RCC_CFGR_MCO2_Pos)

+#define RCC_CFGR_MCO2                          RCC_CFGR_MCO2_Msk                       /*!< 0xE0000000 */

+#define RCC_CFGR_MCO2_0                        (0x1UL << RCC_CFGR_MCO2_Pos)             /*!< 0x20000000 */

+#define RCC_CFGR_MCO2_1                        (0x2UL << RCC_CFGR_MCO2_Pos)             /*!< 0x40000000 */

+#define RCC_CFGR_MCO2_2                        (0x4UL << RCC_CFGR_MCO2_Pos)             /*!< 0x80000000 */

+

+/********************  Bit definition for RCC_D1CFGR register  ******************/

+/*!< D1HPRE configuration */

+#define RCC_D1CFGR_HPRE_Pos                    (0U)

+#define RCC_D1CFGR_HPRE_Msk                    (0xFUL << RCC_D1CFGR_HPRE_Pos)  /*!< 0x0000000F */

+#define RCC_D1CFGR_HPRE                        RCC_D1CFGR_HPRE_Msk             /*!< HPRE[3:0] bits (AHB3 prescaler) */

+#define RCC_D1CFGR_HPRE_0                      (0x1UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000001 */

+#define RCC_D1CFGR_HPRE_1                      (0x2UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000002 */

+#define RCC_D1CFGR_HPRE_2                      (0x4UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000004 */

+#define RCC_D1CFGR_HPRE_3                      (0x8UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000008 */

+

+

+#define RCC_D1CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)          /*!< AHB3 Clock not divided */

+#define RCC_D1CFGR_HPRE_DIV2_Pos               (3U)

+#define RCC_D1CFGR_HPRE_DIV2_Msk               (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */

+#define RCC_D1CFGR_HPRE_DIV2                   RCC_D1CFGR_HPRE_DIV2_Msk        /*!< AHB3 Clock divided by 2 */

+#define RCC_D1CFGR_HPRE_DIV4_Pos               (0U)

+#define RCC_D1CFGR_HPRE_DIV4_Msk               (0x9UL << RCC_D1CFGR_HPRE_DIV4_Pos) /*!< 0x00000009 */

+#define RCC_D1CFGR_HPRE_DIV4                   RCC_D1CFGR_HPRE_DIV4_Msk        /*!< AHB3 Clock divided by 4 */

+#define RCC_D1CFGR_HPRE_DIV8_Pos               (1U)

+#define RCC_D1CFGR_HPRE_DIV8_Msk               (0x5UL << RCC_D1CFGR_HPRE_DIV8_Pos) /*!< 0x0000000A */

+#define RCC_D1CFGR_HPRE_DIV8                   RCC_D1CFGR_HPRE_DIV8_Msk        /*!< AHB3 Clock divided by 8 */

+#define RCC_D1CFGR_HPRE_DIV16_Pos              (0U)

+#define RCC_D1CFGR_HPRE_DIV16_Msk              (0xBUL << RCC_D1CFGR_HPRE_DIV16_Pos) /*!< 0x0000000B */

+#define RCC_D1CFGR_HPRE_DIV16                  RCC_D1CFGR_HPRE_DIV16_Msk       /*!< AHB3 Clock divided by 16 */

+#define RCC_D1CFGR_HPRE_DIV64_Pos              (2U)

+#define RCC_D1CFGR_HPRE_DIV64_Msk              (0x3UL << RCC_D1CFGR_HPRE_DIV64_Pos) /*!< 0x0000000C */

+#define RCC_D1CFGR_HPRE_DIV64                  RCC_D1CFGR_HPRE_DIV64_Msk       /*!< AHB3 Clock divided by 64 */

+#define RCC_D1CFGR_HPRE_DIV128_Pos             (0U)

+#define RCC_D1CFGR_HPRE_DIV128_Msk             (0xDUL << RCC_D1CFGR_HPRE_DIV128_Pos) /*!< 0x0000000D */

+#define RCC_D1CFGR_HPRE_DIV128                 RCC_D1CFGR_HPRE_DIV128_Msk      /*!< AHB3 Clock divided by 128 */

+#define RCC_D1CFGR_HPRE_DIV256_Pos             (1U)

+#define RCC_D1CFGR_HPRE_DIV256_Msk             (0x7UL << RCC_D1CFGR_HPRE_DIV256_Pos) /*!< 0x0000000E */

+#define RCC_D1CFGR_HPRE_DIV256                 RCC_D1CFGR_HPRE_DIV256_Msk      /*!< AHB3 Clock divided by 256 */

+#define RCC_D1CFGR_HPRE_DIV512_Pos             (0U)

+#define RCC_D1CFGR_HPRE_DIV512_Msk             (0xFUL << RCC_D1CFGR_HPRE_DIV512_Pos) /*!< 0x0000000F */

+#define RCC_D1CFGR_HPRE_DIV512                 RCC_D1CFGR_HPRE_DIV512_Msk      /*!< AHB3 Clock divided by 512 */

+

+/*!< D1PPRE configuration */

+#define RCC_D1CFGR_D1PPRE_Pos                  (4U)

+#define RCC_D1CFGR_D1PPRE_Msk                  (0x7UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000070 */

+#define RCC_D1CFGR_D1PPRE                      RCC_D1CFGR_D1PPRE_Msk           /*!< D1PRE[2:0] bits (APB3 prescaler) */

+#define RCC_D1CFGR_D1PPRE_0                    (0x1UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000010 */

+#define RCC_D1CFGR_D1PPRE_1                    (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */

+#define RCC_D1CFGR_D1PPRE_2                    (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */

+

+#define RCC_D1CFGR_D1PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB3 clock not divided */

+#define RCC_D1CFGR_D1PPRE_DIV2_Pos             (6U)

+#define RCC_D1CFGR_D1PPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_D1CFGR_D1PPRE_DIV2                 RCC_D1CFGR_D1PPRE_DIV2_Msk      /*!< APB3 clock divided by 2 */

+#define RCC_D1CFGR_D1PPRE_DIV4_Pos             (4U)

+#define RCC_D1CFGR_D1PPRE_DIV4_Msk             (0x5UL << RCC_D1CFGR_D1PPRE_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_D1CFGR_D1PPRE_DIV4                 RCC_D1CFGR_D1PPRE_DIV4_Msk      /*!< APB3 clock divided by 4 */

+#define RCC_D1CFGR_D1PPRE_DIV8_Pos             (5U)

+#define RCC_D1CFGR_D1PPRE_DIV8_Msk             (0x3UL << RCC_D1CFGR_D1PPRE_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_D1CFGR_D1PPRE_DIV8                 RCC_D1CFGR_D1PPRE_DIV8_Msk      /*!< APB3 clock divided by 8 */

+#define RCC_D1CFGR_D1PPRE_DIV16_Pos            (4U)

+#define RCC_D1CFGR_D1PPRE_DIV16_Msk            (0x7UL << RCC_D1CFGR_D1PPRE_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_D1CFGR_D1PPRE_DIV16                RCC_D1CFGR_D1PPRE_DIV16_Msk     /*!< APB3 clock divided by 16 */

+

+#define RCC_D1CFGR_D1CPRE_Pos                  (8U)

+#define RCC_D1CFGR_D1CPRE_Msk                  (0xFUL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000F00 */

+#define RCC_D1CFGR_D1CPRE                      RCC_D1CFGR_D1CPRE_Msk           /*!< D1CPRE[2:0] bits (Domain 1 Core prescaler) */

+#define RCC_D1CFGR_D1CPRE_0                    (0x1UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000100 */

+#define RCC_D1CFGR_D1CPRE_1                    (0x2UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000200 */

+#define RCC_D1CFGR_D1CPRE_2                    (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */

+#define RCC_D1CFGR_D1CPRE_3                    (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */

+

+#define RCC_D1CFGR_D1CPRE_DIV1                 ((uint32_t)0x00000000)          /*!< Domain 1 Core clock not divided */

+#define RCC_D1CFGR_D1CPRE_DIV2_Pos             (11U)

+#define RCC_D1CFGR_D1CPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */

+#define RCC_D1CFGR_D1CPRE_DIV2                 RCC_D1CFGR_D1CPRE_DIV2_Msk      /*!< Domain 1 Core clock divided by 2 */

+#define RCC_D1CFGR_D1CPRE_DIV4_Pos             (8U)

+#define RCC_D1CFGR_D1CPRE_DIV4_Msk             (0x9UL << RCC_D1CFGR_D1CPRE_DIV4_Pos) /*!< 0x00000900 */

+#define RCC_D1CFGR_D1CPRE_DIV4                 RCC_D1CFGR_D1CPRE_DIV4_Msk      /*!< Domain 1 Core clock divided by 4 */

+#define RCC_D1CFGR_D1CPRE_DIV8_Pos             (9U)

+#define RCC_D1CFGR_D1CPRE_DIV8_Msk             (0x5UL << RCC_D1CFGR_D1CPRE_DIV8_Pos) /*!< 0x00000A00 */

+#define RCC_D1CFGR_D1CPRE_DIV8                 RCC_D1CFGR_D1CPRE_DIV8_Msk      /*!< Domain 1 Core clock divided by 8 */

+#define RCC_D1CFGR_D1CPRE_DIV16_Pos            (8U)

+#define RCC_D1CFGR_D1CPRE_DIV16_Msk            (0xBUL << RCC_D1CFGR_D1CPRE_DIV16_Pos) /*!< 0x00000B00 */

+#define RCC_D1CFGR_D1CPRE_DIV16                RCC_D1CFGR_D1CPRE_DIV16_Msk     /*!< Domain 1 Core clock divided by 16 */

+#define RCC_D1CFGR_D1CPRE_DIV64_Pos            (10U)

+#define RCC_D1CFGR_D1CPRE_DIV64_Msk            (0x3UL << RCC_D1CFGR_D1CPRE_DIV64_Pos) /*!< 0x00000C00 */

+#define RCC_D1CFGR_D1CPRE_DIV64                RCC_D1CFGR_D1CPRE_DIV64_Msk     /*!< Domain 1 Core clock divided by 64 */

+#define RCC_D1CFGR_D1CPRE_DIV128_Pos           (8U)

+#define RCC_D1CFGR_D1CPRE_DIV128_Msk           (0xDUL << RCC_D1CFGR_D1CPRE_DIV128_Pos) /*!< 0x00000D00 */

+#define RCC_D1CFGR_D1CPRE_DIV128               RCC_D1CFGR_D1CPRE_DIV128_Msk    /*!< Domain 1 Core clock divided by 128 */

+#define RCC_D1CFGR_D1CPRE_DIV256_Pos           (9U)

+#define RCC_D1CFGR_D1CPRE_DIV256_Msk           (0x7UL << RCC_D1CFGR_D1CPRE_DIV256_Pos) /*!< 0x00000E00 */

+#define RCC_D1CFGR_D1CPRE_DIV256               RCC_D1CFGR_D1CPRE_DIV256_Msk    /*!< Domain 1 Core clock divided by 256 */

+#define RCC_D1CFGR_D1CPRE_DIV512_Pos           (8U)

+#define RCC_D1CFGR_D1CPRE_DIV512_Msk           (0xFUL << RCC_D1CFGR_D1CPRE_DIV512_Pos) /*!< 0x00000F00 */

+#define RCC_D1CFGR_D1CPRE_DIV512               RCC_D1CFGR_D1CPRE_DIV512_Msk    /*!< Domain 1 Core clock divided by 512 */

+

+/********************  Bit definition for RCC_D2CFGR register  ******************/

+/*!< D2PPRE1 configuration */

+#define RCC_D2CFGR_D2PPRE1_Pos                 (4U)

+#define RCC_D2CFGR_D2PPRE1_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000070 */

+#define RCC_D2CFGR_D2PPRE1                     RCC_D2CFGR_D2PPRE1_Msk          /*!< D1PPRE1[2:0] bits (APB1 prescaler) */

+#define RCC_D2CFGR_D2PPRE1_0                   (0x1UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000010 */

+#define RCC_D2CFGR_D2PPRE1_1                   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */

+#define RCC_D2CFGR_D2PPRE1_2                   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */

+

+#define RCC_D2CFGR_D2PPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */

+#define RCC_D2CFGR_D2PPRE1_DIV2_Pos            (6U)

+#define RCC_D2CFGR_D2PPRE1_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_D2CFGR_D2PPRE1_DIV2                RCC_D2CFGR_D2PPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */

+#define RCC_D2CFGR_D2PPRE1_DIV4_Pos            (4U)

+#define RCC_D2CFGR_D2PPRE1_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE1_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_D2CFGR_D2PPRE1_DIV4                RCC_D2CFGR_D2PPRE1_DIV4_Msk     /*!< APB1 clock divided by 4 */

+#define RCC_D2CFGR_D2PPRE1_DIV8_Pos            (5U)

+#define RCC_D2CFGR_D2PPRE1_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE1_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_D2CFGR_D2PPRE1_DIV8                RCC_D2CFGR_D2PPRE1_DIV8_Msk     /*!< APB1 clock divided by 8 */

+#define RCC_D2CFGR_D2PPRE1_DIV16_Pos           (4U)

+#define RCC_D2CFGR_D2PPRE1_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE1_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_D2CFGR_D2PPRE1_DIV16               RCC_D2CFGR_D2PPRE1_DIV16_Msk    /*!< APB1 clock divided by 16 */

+

+/*!< D2PPRE2 configuration */

+#define RCC_D2CFGR_D2PPRE2_Pos                 (8U)

+#define RCC_D2CFGR_D2PPRE2_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000700 */

+#define RCC_D2CFGR_D2PPRE2                     RCC_D2CFGR_D2PPRE2_Msk          /*!< D2PPRE2[2:0] bits (APB2 prescaler) */

+#define RCC_D2CFGR_D2PPRE2_0                   (0x1UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000100 */

+#define RCC_D2CFGR_D2PPRE2_1                   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */

+#define RCC_D2CFGR_D2PPRE2_2                   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */

+

+#define RCC_D2CFGR_D2PPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */

+#define RCC_D2CFGR_D2PPRE2_DIV2_Pos            (10U)

+#define RCC_D2CFGR_D2PPRE2_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */

+#define RCC_D2CFGR_D2PPRE2_DIV2                RCC_D2CFGR_D2PPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */

+#define RCC_D2CFGR_D2PPRE2_DIV4_Pos            (8U)

+#define RCC_D2CFGR_D2PPRE2_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE2_DIV4_Pos) /*!< 0x00000500 */

+#define RCC_D2CFGR_D2PPRE2_DIV4                RCC_D2CFGR_D2PPRE2_DIV4_Msk     /*!< APB2 clock divided by 4 */

+#define RCC_D2CFGR_D2PPRE2_DIV8_Pos            (9U)

+#define RCC_D2CFGR_D2PPRE2_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE2_DIV8_Pos) /*!< 0x00000600 */

+#define RCC_D2CFGR_D2PPRE2_DIV8                RCC_D2CFGR_D2PPRE2_DIV8_Msk     /*!< APB2 clock divided by 8 */

+#define RCC_D2CFGR_D2PPRE2_DIV16_Pos           (8U)

+#define RCC_D2CFGR_D2PPRE2_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE2_DIV16_Pos) /*!< 0x00000700 */

+#define RCC_D2CFGR_D2PPRE2_DIV16               RCC_D2CFGR_D2PPRE2_DIV16_Msk    /*!< APB2 clock divided by 16 */

+

+/********************  Bit definition for RCC_D3CFGR register  ******************/

+/*!< D3PPRE configuration */

+#define RCC_D3CFGR_D3PPRE_Pos                  (4U)

+#define RCC_D3CFGR_D3PPRE_Msk                  (0x7UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000070 */

+#define RCC_D3CFGR_D3PPRE                      RCC_D3CFGR_D3PPRE_Msk           /*!< D3PPRE1[2:0] bits (APB4 prescaler) */

+#define RCC_D3CFGR_D3PPRE_0                    (0x1UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000010 */

+#define RCC_D3CFGR_D3PPRE_1                    (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */

+#define RCC_D3CFGR_D3PPRE_2                    (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */

+

+#define RCC_D3CFGR_D3PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */

+#define RCC_D3CFGR_D3PPRE_DIV2_Pos             (6U)

+#define RCC_D3CFGR_D3PPRE_DIV2_Msk             (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_D3CFGR_D3PPRE_DIV2                 RCC_D3CFGR_D3PPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */

+#define RCC_D3CFGR_D3PPRE_DIV4_Pos             (4U)

+#define RCC_D3CFGR_D3PPRE_DIV4_Msk             (0x5UL << RCC_D3CFGR_D3PPRE_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_D3CFGR_D3PPRE_DIV4                 RCC_D3CFGR_D3PPRE_DIV4_Msk      /*!< APB4 clock divided by 4 */

+#define RCC_D3CFGR_D3PPRE_DIV8_Pos             (5U)

+#define RCC_D3CFGR_D3PPRE_DIV8_Msk             (0x3UL << RCC_D3CFGR_D3PPRE_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_D3CFGR_D3PPRE_DIV8                 RCC_D3CFGR_D3PPRE_DIV8_Msk      /*!< APB4 clock divided by 8 */

+#define RCC_D3CFGR_D3PPRE_DIV16_Pos            (4U)

+#define RCC_D3CFGR_D3PPRE_DIV16_Msk            (0x7UL << RCC_D3CFGR_D3PPRE_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_D3CFGR_D3PPRE_DIV16                RCC_D3CFGR_D3PPRE_DIV16_Msk     /*!< APB4 clock divided by 16 */

+

+/********************  Bit definition for RCC_PLLCKSELR register  *************/

+

+#define RCC_PLLCKSELR_PLLSRC_Pos               (0U)

+#define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */

+#define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk

+

+#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)

+#define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */

+#define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_HSE_Pos           (1U)

+#define RCC_PLLCKSELR_PLLSRC_HSE_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */

+#define RCC_PLLCKSELR_PLLSRC_HSE               RCC_PLLCKSELR_PLLSRC_HSE_Msk    /*!< HSE source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_NONE_Pos          (0U)

+#define RCC_PLLCKSELR_PLLSRC_NONE_Msk          (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */

+#define RCC_PLLCKSELR_PLLSRC_NONE              RCC_PLLCKSELR_PLLSRC_NONE_Msk   /*!< No source clock selected  */

+

+#define RCC_PLLCKSELR_DIVM1_Pos                (4U)

+#define RCC_PLLCKSELR_DIVM1_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */

+#define RCC_PLLCKSELR_DIVM1                    RCC_PLLCKSELR_DIVM1_Msk

+#define RCC_PLLCKSELR_DIVM1_0                  (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */

+#define RCC_PLLCKSELR_DIVM1_1                  (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */

+#define RCC_PLLCKSELR_DIVM1_2                  (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */

+#define RCC_PLLCKSELR_DIVM1_3                  (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */

+#define RCC_PLLCKSELR_DIVM1_4                  (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */

+#define RCC_PLLCKSELR_DIVM1_5                  (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */

+

+#define RCC_PLLCKSELR_DIVM2_Pos                (12U)

+#define RCC_PLLCKSELR_DIVM2_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */

+#define RCC_PLLCKSELR_DIVM2                    RCC_PLLCKSELR_DIVM2_Msk

+#define RCC_PLLCKSELR_DIVM2_0                  (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */

+#define RCC_PLLCKSELR_DIVM2_1                  (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */

+#define RCC_PLLCKSELR_DIVM2_2                  (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */

+#define RCC_PLLCKSELR_DIVM2_3                  (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */

+#define RCC_PLLCKSELR_DIVM2_4                  (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */

+#define RCC_PLLCKSELR_DIVM2_5                  (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */

+

+#define RCC_PLLCKSELR_DIVM3_Pos                (20U)

+#define RCC_PLLCKSELR_DIVM3_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */

+#define RCC_PLLCKSELR_DIVM3                    RCC_PLLCKSELR_DIVM3_Msk

+#define RCC_PLLCKSELR_DIVM3_0                  (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */

+#define RCC_PLLCKSELR_DIVM3_1                  (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */

+#define RCC_PLLCKSELR_DIVM3_2                  (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */

+#define RCC_PLLCKSELR_DIVM3_3                  (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */

+#define RCC_PLLCKSELR_DIVM3_4                  (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */

+#define RCC_PLLCKSELR_DIVM3_5                  (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */

+

+/********************  Bit definition for RCC_PLLCFGR register  ***************/

+

+#define RCC_PLLCFGR_PLL1FRACEN_Pos             (0U)

+#define RCC_PLLCFGR_PLL1FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */

+#define RCC_PLLCFGR_PLL1FRACEN                 RCC_PLLCFGR_PLL1FRACEN_Msk

+#define RCC_PLLCFGR_PLL1VCOSEL_Pos             (1U)

+#define RCC_PLLCFGR_PLL1VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */

+#define RCC_PLLCFGR_PLL1VCOSEL                 RCC_PLLCFGR_PLL1VCOSEL_Msk

+#define RCC_PLLCFGR_PLL1RGE_Pos                (2U)

+#define RCC_PLLCFGR_PLL1RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */

+#define RCC_PLLCFGR_PLL1RGE                    RCC_PLLCFGR_PLL1RGE_Msk

+#define RCC_PLLCFGR_PLL1RGE_0                  (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL1RGE_1                  (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */

+#define RCC_PLLCFGR_PLL1RGE_2                  (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */

+#define RCC_PLLCFGR_PLL1RGE_3                  (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */

+

+#define RCC_PLLCFGR_PLL2FRACEN_Pos             (4U)

+#define RCC_PLLCFGR_PLL2FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */

+#define RCC_PLLCFGR_PLL2FRACEN                 RCC_PLLCFGR_PLL2FRACEN_Msk

+#define RCC_PLLCFGR_PLL2VCOSEL_Pos             (5U)

+#define RCC_PLLCFGR_PLL2VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */

+#define RCC_PLLCFGR_PLL2VCOSEL                 RCC_PLLCFGR_PLL2VCOSEL_Msk

+#define RCC_PLLCFGR_PLL2RGE_Pos                (6U)

+#define RCC_PLLCFGR_PLL2RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */

+#define RCC_PLLCFGR_PLL2RGE                    RCC_PLLCFGR_PLL2RGE_Msk

+#define RCC_PLLCFGR_PLL2RGE_0                  (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL2RGE_1                  (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */

+#define RCC_PLLCFGR_PLL2RGE_2                  (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */

+#define RCC_PLLCFGR_PLL2RGE_3                  (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */

+

+#define RCC_PLLCFGR_PLL3FRACEN_Pos             (8U)

+#define RCC_PLLCFGR_PLL3FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */

+#define RCC_PLLCFGR_PLL3FRACEN                 RCC_PLLCFGR_PLL3FRACEN_Msk

+#define RCC_PLLCFGR_PLL3VCOSEL_Pos             (9U)

+#define RCC_PLLCFGR_PLL3VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */

+#define RCC_PLLCFGR_PLL3VCOSEL                 RCC_PLLCFGR_PLL3VCOSEL_Msk

+#define RCC_PLLCFGR_PLL3RGE_Pos                (10U)

+#define RCC_PLLCFGR_PLL3RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */

+#define RCC_PLLCFGR_PLL3RGE                    RCC_PLLCFGR_PLL3RGE_Msk

+#define RCC_PLLCFGR_PLL3RGE_0                  (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL3RGE_1                  (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */

+#define RCC_PLLCFGR_PLL3RGE_2                  (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */

+#define RCC_PLLCFGR_PLL3RGE_3                  (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */

+

+#define RCC_PLLCFGR_DIVP1EN_Pos                (16U)

+#define RCC_PLLCFGR_DIVP1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */

+#define RCC_PLLCFGR_DIVP1EN                    RCC_PLLCFGR_DIVP1EN_Msk

+#define RCC_PLLCFGR_DIVQ1EN_Pos                (17U)

+#define RCC_PLLCFGR_DIVQ1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */

+#define RCC_PLLCFGR_DIVQ1EN                    RCC_PLLCFGR_DIVQ1EN_Msk

+#define RCC_PLLCFGR_DIVR1EN_Pos                (18U)

+#define RCC_PLLCFGR_DIVR1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */

+#define RCC_PLLCFGR_DIVR1EN                    RCC_PLLCFGR_DIVR1EN_Msk

+

+#define RCC_PLLCFGR_DIVP2EN_Pos                (19U)

+#define RCC_PLLCFGR_DIVP2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */

+#define RCC_PLLCFGR_DIVP2EN                    RCC_PLLCFGR_DIVP2EN_Msk

+#define RCC_PLLCFGR_DIVQ2EN_Pos                (20U)

+#define RCC_PLLCFGR_DIVQ2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */

+#define RCC_PLLCFGR_DIVQ2EN                    RCC_PLLCFGR_DIVQ2EN_Msk

+#define RCC_PLLCFGR_DIVR2EN_Pos                (21U)

+#define RCC_PLLCFGR_DIVR2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */

+#define RCC_PLLCFGR_DIVR2EN                    RCC_PLLCFGR_DIVR2EN_Msk

+

+#define RCC_PLLCFGR_DIVP3EN_Pos                (22U)

+#define RCC_PLLCFGR_DIVP3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */

+#define RCC_PLLCFGR_DIVP3EN                    RCC_PLLCFGR_DIVP3EN_Msk

+#define RCC_PLLCFGR_DIVQ3EN_Pos                (23U)

+#define RCC_PLLCFGR_DIVQ3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */

+#define RCC_PLLCFGR_DIVQ3EN                    RCC_PLLCFGR_DIVQ3EN_Msk

+#define RCC_PLLCFGR_DIVR3EN_Pos                (24U)

+#define RCC_PLLCFGR_DIVR3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */

+#define RCC_PLLCFGR_DIVR3EN                    RCC_PLLCFGR_DIVR3EN_Msk

+

+

+/********************  Bit definition for RCC_PLL1DIVR register  ***************/

+#define RCC_PLL1DIVR_N1_Pos                    (0U)

+#define RCC_PLL1DIVR_N1_Msk                    (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */

+#define RCC_PLL1DIVR_N1                        RCC_PLL1DIVR_N1_Msk

+#define RCC_PLL1DIVR_P1_Pos                    (9U)

+#define RCC_PLL1DIVR_P1_Msk                    (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL1DIVR_P1                        RCC_PLL1DIVR_P1_Msk

+#define RCC_PLL1DIVR_Q1_Pos                    (16U)

+#define RCC_PLL1DIVR_Q1_Msk                    (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */

+#define RCC_PLL1DIVR_Q1                        RCC_PLL1DIVR_Q1_Msk

+#define RCC_PLL1DIVR_R1_Pos                    (24U)

+#define RCC_PLL1DIVR_R1_Msk                    (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */

+#define RCC_PLL1DIVR_R1                        RCC_PLL1DIVR_R1_Msk

+

+/********************  Bit definition for RCC_PLL1FRACR register  ***************/

+#define RCC_PLL1FRACR_FRACN1_Pos               (3U)

+#define RCC_PLL1FRACR_FRACN1_Msk               (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL1FRACR_FRACN1                   RCC_PLL1FRACR_FRACN1_Msk

+

+/********************  Bit definition for RCC_PLL2DIVR register  ***************/

+#define RCC_PLL2DIVR_N2_Pos                    (0U)

+#define RCC_PLL2DIVR_N2_Msk                    (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */

+#define RCC_PLL2DIVR_N2                        RCC_PLL2DIVR_N2_Msk

+#define RCC_PLL2DIVR_P2_Pos                    (9U)

+#define RCC_PLL2DIVR_P2_Msk                    (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL2DIVR_P2                        RCC_PLL2DIVR_P2_Msk

+#define RCC_PLL2DIVR_Q2_Pos                    (16U)

+#define RCC_PLL2DIVR_Q2_Msk                    (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */

+#define RCC_PLL2DIVR_Q2                        RCC_PLL2DIVR_Q2_Msk

+#define RCC_PLL2DIVR_R2_Pos                    (24U)

+#define RCC_PLL2DIVR_R2_Msk                    (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */

+#define RCC_PLL2DIVR_R2                        RCC_PLL2DIVR_R2_Msk

+

+/********************  Bit definition for RCC_PLL2FRACR register  ***************/

+#define RCC_PLL2FRACR_FRACN2_Pos               (3U)

+#define RCC_PLL2FRACR_FRACN2_Msk               (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL2FRACR_FRACN2                   RCC_PLL2FRACR_FRACN2_Msk

+

+/********************  Bit definition for RCC_PLL3DIVR register  ***************/

+#define RCC_PLL3DIVR_N3_Pos                    (0U)

+#define RCC_PLL3DIVR_N3_Msk                    (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */

+#define RCC_PLL3DIVR_N3                        RCC_PLL3DIVR_N3_Msk

+#define RCC_PLL3DIVR_P3_Pos                    (9U)

+#define RCC_PLL3DIVR_P3_Msk                    (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL3DIVR_P3                        RCC_PLL3DIVR_P3_Msk

+#define RCC_PLL3DIVR_Q3_Pos                    (16U)

+#define RCC_PLL3DIVR_Q3_Msk                    (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */

+#define RCC_PLL3DIVR_Q3                        RCC_PLL3DIVR_Q3_Msk

+#define RCC_PLL3DIVR_R3_Pos                    (24U)

+#define RCC_PLL3DIVR_R3_Msk                    (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */

+#define RCC_PLL3DIVR_R3                        RCC_PLL3DIVR_R3_Msk

+

+/********************  Bit definition for RCC_PLL3FRACR register  ***************/

+#define RCC_PLL3FRACR_FRACN3_Pos               (3U)

+#define RCC_PLL3FRACR_FRACN3_Msk               (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL3FRACR_FRACN3                   RCC_PLL3FRACR_FRACN3_Msk

+

+/********************  Bit definition for RCC_D1CCIPR register  ***************/

+#define RCC_D1CCIPR_FMCSEL_Pos                 (0U)

+#define RCC_D1CCIPR_FMCSEL_Msk                 (0x3UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000003 */

+#define RCC_D1CCIPR_FMCSEL                     RCC_D1CCIPR_FMCSEL_Msk

+#define RCC_D1CCIPR_FMCSEL_0                   (0x1UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000001 */

+#define RCC_D1CCIPR_FMCSEL_1                   (0x2UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000002 */

+#define RCC_D1CCIPR_QSPISEL_Pos                (4U)

+#define RCC_D1CCIPR_QSPISEL_Msk                (0x3UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000030 */

+#define RCC_D1CCIPR_QSPISEL                    RCC_D1CCIPR_QSPISEL_Msk

+#define RCC_D1CCIPR_QSPISEL_0                  (0x1UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000010 */

+#define RCC_D1CCIPR_QSPISEL_1                  (0x2UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000020 */

+#define RCC_D1CCIPR_SDMMCSEL_Pos               (16U)

+#define RCC_D1CCIPR_SDMMCSEL_Msk               (0x1UL << RCC_D1CCIPR_SDMMCSEL_Pos) /*!< 0x00010000 */

+#define RCC_D1CCIPR_SDMMCSEL                   RCC_D1CCIPR_SDMMCSEL_Msk

+#define RCC_D1CCIPR_CKPERSEL_Pos               (28U)

+#define RCC_D1CCIPR_CKPERSEL_Msk               (0x3UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x30000000 */

+#define RCC_D1CCIPR_CKPERSEL                   RCC_D1CCIPR_CKPERSEL_Msk

+#define RCC_D1CCIPR_CKPERSEL_0                 (0x1UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x10000000 */

+#define RCC_D1CCIPR_CKPERSEL_1                 (0x2UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x20000000 */

+

+/********************  Bit definition for RCC_D2CCIP1R register  ***************/

+#define RCC_D2CCIP1R_SAI1SEL_Pos               (0U)

+#define RCC_D2CCIP1R_SAI1SEL_Msk               (0x7UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000007 */

+#define RCC_D2CCIP1R_SAI1SEL                   RCC_D2CCIP1R_SAI1SEL_Msk

+#define RCC_D2CCIP1R_SAI1SEL_0                 (0x1UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000001 */

+#define RCC_D2CCIP1R_SAI1SEL_1                 (0x2UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000002 */

+#define RCC_D2CCIP1R_SAI1SEL_2                 (0x4UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000004 */

+

+#define RCC_D2CCIP1R_SAI23SEL_Pos              (6U)

+#define RCC_D2CCIP1R_SAI23SEL_Msk              (0x7UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x000001C0 */

+#define RCC_D2CCIP1R_SAI23SEL                  RCC_D2CCIP1R_SAI23SEL_Msk

+#define RCC_D2CCIP1R_SAI23SEL_0                (0x1UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000040 */

+#define RCC_D2CCIP1R_SAI23SEL_1                (0x2UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000080 */

+#define RCC_D2CCIP1R_SAI23SEL_2                (0x4UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000100 */

+

+#define RCC_D2CCIP1R_SPI123SEL_Pos             (12U)

+#define RCC_D2CCIP1R_SPI123SEL_Msk             (0x7UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */

+#define RCC_D2CCIP1R_SPI123SEL                 RCC_D2CCIP1R_SPI123SEL_Msk

+#define RCC_D2CCIP1R_SPI123SEL_0               (0x1UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */

+#define RCC_D2CCIP1R_SPI123SEL_1               (0x2UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */

+#define RCC_D2CCIP1R_SPI123SEL_2               (0x4UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */

+

+#define RCC_D2CCIP1R_SPI45SEL_Pos              (16U)

+#define RCC_D2CCIP1R_SPI45SEL_Msk              (0x7UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00070000 */

+#define RCC_D2CCIP1R_SPI45SEL                  RCC_D2CCIP1R_SPI45SEL_Msk

+#define RCC_D2CCIP1R_SPI45SEL_0                (0x1UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00010000 */

+#define RCC_D2CCIP1R_SPI45SEL_1                (0x2UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00020000 */

+#define RCC_D2CCIP1R_SPI45SEL_2                (0x4UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00040000 */

+

+#define RCC_D2CCIP1R_SPDIFSEL_Pos              (20U)

+#define RCC_D2CCIP1R_SPDIFSEL_Msk              (0x3UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00300000 */

+#define RCC_D2CCIP1R_SPDIFSEL                  RCC_D2CCIP1R_SPDIFSEL_Msk

+#define RCC_D2CCIP1R_SPDIFSEL_0                (0x1UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00100000 */

+#define RCC_D2CCIP1R_SPDIFSEL_1                (0x2UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00200000 */

+

+#define RCC_D2CCIP1R_DFSDM1SEL_Pos             (24U)

+#define RCC_D2CCIP1R_DFSDM1SEL_Msk             (0x1UL << RCC_D2CCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */

+#define RCC_D2CCIP1R_DFSDM1SEL                 RCC_D2CCIP1R_DFSDM1SEL_Msk

+

+#define RCC_D2CCIP1R_FDCANSEL_Pos              (28U)

+#define RCC_D2CCIP1R_FDCANSEL_Msk              (0x3UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x30000000 */

+#define RCC_D2CCIP1R_FDCANSEL                  RCC_D2CCIP1R_FDCANSEL_Msk

+#define RCC_D2CCIP1R_FDCANSEL_0                (0x1UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x10000000 */

+#define RCC_D2CCIP1R_FDCANSEL_1                (0x2UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x20000000 */

+

+#define RCC_D2CCIP1R_SWPSEL_Pos                (31U)

+#define RCC_D2CCIP1R_SWPSEL_Msk                (0x1UL << RCC_D2CCIP1R_SWPSEL_Pos) /*!< 0x80000000 */

+#define RCC_D2CCIP1R_SWPSEL                    RCC_D2CCIP1R_SWPSEL_Msk

+

+/********************  Bit definition for RCC_D2CCIP2R register  ***************/

+#define RCC_D2CCIP2R_USART16SEL_Pos            (3U)

+#define RCC_D2CCIP2R_USART16SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000038 */

+#define RCC_D2CCIP2R_USART16SEL                RCC_D2CCIP2R_USART16SEL_Msk

+#define RCC_D2CCIP2R_USART16SEL_0              (0x1UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000008 */

+#define RCC_D2CCIP2R_USART16SEL_1              (0x2UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000010 */

+#define RCC_D2CCIP2R_USART16SEL_2              (0x4UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000020 */

+

+#define RCC_D2CCIP2R_USART28SEL_Pos            (0U)

+#define RCC_D2CCIP2R_USART28SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000007 */

+#define RCC_D2CCIP2R_USART28SEL                RCC_D2CCIP2R_USART28SEL_Msk

+#define RCC_D2CCIP2R_USART28SEL_0              (0x1UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000001 */

+#define RCC_D2CCIP2R_USART28SEL_1              (0x2UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000002 */

+#define RCC_D2CCIP2R_USART28SEL_2              (0x4UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000004 */

+

+#define RCC_D2CCIP2R_RNGSEL_Pos                (8U)

+#define RCC_D2CCIP2R_RNGSEL_Msk                (0x3UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000300 */

+#define RCC_D2CCIP2R_RNGSEL                    RCC_D2CCIP2R_RNGSEL_Msk

+#define RCC_D2CCIP2R_RNGSEL_0                  (0x1UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000100 */

+#define RCC_D2CCIP2R_RNGSEL_1                  (0x2UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000200 */

+

+#define RCC_D2CCIP2R_I2C123SEL_Pos             (12U)

+#define RCC_D2CCIP2R_I2C123SEL_Msk             (0x3UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00003000 */

+#define RCC_D2CCIP2R_I2C123SEL                 RCC_D2CCIP2R_I2C123SEL_Msk

+#define RCC_D2CCIP2R_I2C123SEL_0               (0x1UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00001000 */

+#define RCC_D2CCIP2R_I2C123SEL_1               (0x2UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00002000 */

+

+#define RCC_D2CCIP2R_USBSEL_Pos                (20U)

+#define RCC_D2CCIP2R_USBSEL_Msk                (0x3UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00300000 */

+#define RCC_D2CCIP2R_USBSEL                    RCC_D2CCIP2R_USBSEL_Msk

+#define RCC_D2CCIP2R_USBSEL_0                  (0x1UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00100000 */

+#define RCC_D2CCIP2R_USBSEL_1                  (0x2UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00200000 */

+

+#define RCC_D2CCIP2R_CECSEL_Pos                (22U)

+#define RCC_D2CCIP2R_CECSEL_Msk                (0x3UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00C00000 */

+#define RCC_D2CCIP2R_CECSEL                    RCC_D2CCIP2R_CECSEL_Msk

+#define RCC_D2CCIP2R_CECSEL_0                  (0x1UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00400000 */

+#define RCC_D2CCIP2R_CECSEL_1                  (0x2UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00800000 */

+

+#define RCC_D2CCIP2R_LPTIM1SEL_Pos             (28U)

+#define RCC_D2CCIP2R_LPTIM1SEL_Msk             (0x7UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x70000000 */

+#define RCC_D2CCIP2R_LPTIM1SEL                 RCC_D2CCIP2R_LPTIM1SEL_Msk

+#define RCC_D2CCIP2R_LPTIM1SEL_0               (0x1UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x10000000 */

+#define RCC_D2CCIP2R_LPTIM1SEL_1               (0x2UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x20000000 */

+#define RCC_D2CCIP2R_LPTIM1SEL_2               (0x4UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition for RCC_D3CCIPR register  ***************/

+#define RCC_D3CCIPR_LPUART1SEL_Pos             (0U)

+#define RCC_D3CCIPR_LPUART1SEL_Msk             (0x7UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000007 */

+#define RCC_D3CCIPR_LPUART1SEL                 RCC_D3CCIPR_LPUART1SEL_Msk

+#define RCC_D3CCIPR_LPUART1SEL_0               (0x1UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000001 */

+#define RCC_D3CCIPR_LPUART1SEL_1               (0x2UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000002 */

+#define RCC_D3CCIPR_LPUART1SEL_2               (0x4UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000004 */

+

+#define RCC_D3CCIPR_I2C4SEL_Pos                (8U)

+#define RCC_D3CCIPR_I2C4SEL_Msk                (0x3UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000300 */

+#define RCC_D3CCIPR_I2C4SEL                    RCC_D3CCIPR_I2C4SEL_Msk

+#define RCC_D3CCIPR_I2C4SEL_0                  (0x1UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000100 */

+#define RCC_D3CCIPR_I2C4SEL_1                  (0x2UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000200 */

+

+#define RCC_D3CCIPR_LPTIM2SEL_Pos              (10U)

+#define RCC_D3CCIPR_LPTIM2SEL_Msk              (0x7UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001C00 */

+#define RCC_D3CCIPR_LPTIM2SEL                  RCC_D3CCIPR_LPTIM2SEL_Msk

+#define RCC_D3CCIPR_LPTIM2SEL_0                (0x1UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000400 */

+#define RCC_D3CCIPR_LPTIM2SEL_1                (0x2UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000800 */

+#define RCC_D3CCIPR_LPTIM2SEL_2                (0x4UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001000 */

+

+#define RCC_D3CCIPR_LPTIM345SEL_Pos            (13U)

+#define RCC_D3CCIPR_LPTIM345SEL_Msk            (0x7UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x0000E000 */

+#define RCC_D3CCIPR_LPTIM345SEL                RCC_D3CCIPR_LPTIM345SEL_Msk

+#define RCC_D3CCIPR_LPTIM345SEL_0              (0x1UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00002000 */

+#define RCC_D3CCIPR_LPTIM345SEL_1              (0x2UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00004000 */

+#define RCC_D3CCIPR_LPTIM345SEL_2              (0x4UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00008000 */

+

+#define RCC_D3CCIPR_SAI4ASEL_Pos               (21U)

+#define RCC_D3CCIPR_SAI4ASEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00E00000 */

+#define RCC_D3CCIPR_SAI4ASEL                   RCC_D3CCIPR_SAI4ASEL_Msk

+#define RCC_D3CCIPR_SAI4ASEL_0                 (0x1UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00200000 */

+#define RCC_D3CCIPR_SAI4ASEL_1                 (0x2UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00400000 */

+#define RCC_D3CCIPR_SAI4ASEL_2                 (0x4UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00800000 */

+

+#define RCC_D3CCIPR_SAI4BSEL_Pos               (24U)

+#define RCC_D3CCIPR_SAI4BSEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x07000000 */

+#define RCC_D3CCIPR_SAI4BSEL                   RCC_D3CCIPR_SAI4BSEL_Msk

+#define RCC_D3CCIPR_SAI4BSEL_0                 (0x1UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x01000000 */

+#define RCC_D3CCIPR_SAI4BSEL_1                 (0x2UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x02000000 */

+#define RCC_D3CCIPR_SAI4BSEL_2                 (0x4UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x04000000 */

+

+#define RCC_D3CCIPR_ADCSEL_Pos                 (16U)

+#define RCC_D3CCIPR_ADCSEL_Msk                 (0x3UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00030000 */

+#define RCC_D3CCIPR_ADCSEL                     RCC_D3CCIPR_ADCSEL_Msk

+#define RCC_D3CCIPR_ADCSEL_0                   (0x1UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00010000 */

+#define RCC_D3CCIPR_ADCSEL_1                   (0x2UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00020000 */

+

+#define RCC_D3CCIPR_SPI6SEL_Pos                (28U)

+#define RCC_D3CCIPR_SPI6SEL_Msk                (0x7UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x70000000 */

+#define RCC_D3CCIPR_SPI6SEL                    RCC_D3CCIPR_SPI6SEL_Msk

+#define RCC_D3CCIPR_SPI6SEL_0                  (0x1UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x10000000 */

+#define RCC_D3CCIPR_SPI6SEL_1                  (0x2UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x20000000 */

+#define RCC_D3CCIPR_SPI6SEL_2                  (0x4UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x40000000 */

+/********************  Bit definition for RCC_CIER register  ******************/

+#define RCC_CIER_LSIRDYIE_Pos                  (0U)

+#define RCC_CIER_LSIRDYIE_Msk                  (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */

+#define RCC_CIER_LSIRDYIE                      RCC_CIER_LSIRDYIE_Msk

+#define RCC_CIER_LSERDYIE_Pos                  (1U)

+#define RCC_CIER_LSERDYIE_Msk                  (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */

+#define RCC_CIER_LSERDYIE                      RCC_CIER_LSERDYIE_Msk

+#define RCC_CIER_HSIRDYIE_Pos                  (2U)

+#define RCC_CIER_HSIRDYIE_Msk                  (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */

+#define RCC_CIER_HSIRDYIE                      RCC_CIER_HSIRDYIE_Msk

+#define RCC_CIER_HSERDYIE_Pos                  (3U)

+#define RCC_CIER_HSERDYIE_Msk                  (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */

+#define RCC_CIER_HSERDYIE                      RCC_CIER_HSERDYIE_Msk

+#define RCC_CIER_CSIRDYIE_Pos                  (4U)

+#define RCC_CIER_CSIRDYIE_Msk                  (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */

+#define RCC_CIER_CSIRDYIE                      RCC_CIER_CSIRDYIE_Msk

+#define RCC_CIER_HSI48RDYIE_Pos                (5U)

+#define RCC_CIER_HSI48RDYIE_Msk                (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */

+#define RCC_CIER_HSI48RDYIE                    RCC_CIER_HSI48RDYIE_Msk

+#define RCC_CIER_PLL1RDYIE_Pos                 (6U)

+#define RCC_CIER_PLL1RDYIE_Msk                 (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */

+#define RCC_CIER_PLL1RDYIE                     RCC_CIER_PLL1RDYIE_Msk

+#define RCC_CIER_PLL2RDYIE_Pos                 (7U)

+#define RCC_CIER_PLL2RDYIE_Msk                 (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */

+#define RCC_CIER_PLL2RDYIE                     RCC_CIER_PLL2RDYIE_Msk

+#define RCC_CIER_PLL3RDYIE_Pos                 (8U)

+#define RCC_CIER_PLL3RDYIE_Msk                 (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */

+#define RCC_CIER_PLL3RDYIE                     RCC_CIER_PLL3RDYIE_Msk

+#define RCC_CIER_LSECSSIE_Pos                  (9U)

+#define RCC_CIER_LSECSSIE_Msk                  (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */

+#define RCC_CIER_LSECSSIE                      RCC_CIER_LSECSSIE_Msk

+

+/********************  Bit definition for RCC_CIFR register  ******************/

+#define RCC_CIFR_LSIRDYF_Pos                   (0U)

+#define RCC_CIFR_LSIRDYF_Msk                   (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */

+#define RCC_CIFR_LSIRDYF                       RCC_CIFR_LSIRDYF_Msk

+#define RCC_CIFR_LSERDYF_Pos                   (1U)

+#define RCC_CIFR_LSERDYF_Msk                   (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */

+#define RCC_CIFR_LSERDYF                       RCC_CIFR_LSERDYF_Msk

+#define RCC_CIFR_HSIRDYF_Pos                   (2U)

+#define RCC_CIFR_HSIRDYF_Msk                   (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */

+#define RCC_CIFR_HSIRDYF                       RCC_CIFR_HSIRDYF_Msk

+#define RCC_CIFR_HSERDYF_Pos                   (3U)

+#define RCC_CIFR_HSERDYF_Msk                   (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */

+#define RCC_CIFR_HSERDYF                       RCC_CIFR_HSERDYF_Msk

+#define RCC_CIFR_CSIRDYF_Pos                   (4U)

+#define RCC_CIFR_CSIRDYF_Msk                   (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */

+#define RCC_CIFR_CSIRDYF                       RCC_CIFR_CSIRDYF_Msk

+#define RCC_CIFR_HSI48RDYF_Pos                 (5U)

+#define RCC_CIFR_HSI48RDYF_Msk                 (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */

+#define RCC_CIFR_HSI48RDYF                     RCC_CIFR_HSI48RDYF_Msk

+#define RCC_CIFR_PLLRDYF_Pos                   (6U)

+#define RCC_CIFR_PLLRDYF_Msk                   (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */

+#define RCC_CIFR_PLLRDYF                       RCC_CIFR_PLLRDYF_Msk

+#define RCC_CIFR_PLL2RDYF_Pos                  (7U)

+#define RCC_CIFR_PLL2RDYF_Msk                  (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */

+#define RCC_CIFR_PLL2RDYF                      RCC_CIFR_PLL2RDYF_Msk

+#define RCC_CIFR_PLL3RDYF_Pos                  (8U)

+#define RCC_CIFR_PLL3RDYF_Msk                  (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */

+#define RCC_CIFR_PLL3RDYF                      RCC_CIFR_PLL3RDYF_Msk

+#define RCC_CIFR_LSECSSF_Pos                   (9U)

+#define RCC_CIFR_LSECSSF_Msk                   (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */

+#define RCC_CIFR_LSECSSF                       RCC_CIFR_LSECSSF_Msk

+#define RCC_CIFR_HSECSSF_Pos                   (10U)

+#define RCC_CIFR_HSECSSF_Msk                   (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */

+#define RCC_CIFR_HSECSSF                       RCC_CIFR_HSECSSF_Msk

+

+/********************  Bit definition for RCC_CICR register  ******************/

+#define RCC_CICR_LSIRDYC_Pos                   (0U)

+#define RCC_CICR_LSIRDYC_Msk                   (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */

+#define RCC_CICR_LSIRDYC                       RCC_CICR_LSIRDYC_Msk

+#define RCC_CICR_LSERDYC_Pos                   (1U)

+#define RCC_CICR_LSERDYC_Msk                   (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */

+#define RCC_CICR_LSERDYC                       RCC_CICR_LSERDYC_Msk

+#define RCC_CICR_HSIRDYC_Pos                   (2U)

+#define RCC_CICR_HSIRDYC_Msk                   (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */

+#define RCC_CICR_HSIRDYC                       RCC_CICR_HSIRDYC_Msk

+#define RCC_CICR_HSERDYC_Pos                   (3U)

+#define RCC_CICR_HSERDYC_Msk                   (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */

+#define RCC_CICR_HSERDYC                       RCC_CICR_HSERDYC_Msk

+#define RCC_CICR_CSIRDYC_Pos                   (4U)

+#define RCC_CICR_CSIRDYC_Msk                   (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */

+#define RCC_CICR_CSIRDYC                       RCC_CICR_CSIRDYC_Msk

+#define RCC_CICR_HSI48RDYC_Pos                 (5U)

+#define RCC_CICR_HSI48RDYC_Msk                 (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */

+#define RCC_CICR_HSI48RDYC                     RCC_CICR_HSI48RDYC_Msk

+#define RCC_CICR_PLLRDYC_Pos                   (6U)

+#define RCC_CICR_PLLRDYC_Msk                   (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */

+#define RCC_CICR_PLLRDYC                       RCC_CICR_PLLRDYC_Msk

+#define RCC_CICR_PLL2RDYC_Pos                  (7U)

+#define RCC_CICR_PLL2RDYC_Msk                  (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */

+#define RCC_CICR_PLL2RDYC                      RCC_CICR_PLL2RDYC_Msk

+#define RCC_CICR_PLL3RDYC_Pos                  (8U)

+#define RCC_CICR_PLL3RDYC_Msk                  (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */

+#define RCC_CICR_PLL3RDYC                      RCC_CICR_PLL3RDYC_Msk

+#define RCC_CICR_LSECSSC_Pos                   (9U)

+#define RCC_CICR_LSECSSC_Msk                   (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */

+#define RCC_CICR_LSECSSC                       RCC_CICR_LSECSSC_Msk

+#define RCC_CICR_HSECSSC_Pos                   (10U)

+#define RCC_CICR_HSECSSC_Msk                   (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */

+#define RCC_CICR_HSECSSC                       RCC_CICR_HSECSSC_Msk

+

+/********************  Bit definition for RCC_BDCR register  ******************/

+#define RCC_BDCR_LSEON_Pos                     (0U)

+#define RCC_BDCR_LSEON_Msk                     (0x1UL << RCC_BDCR_LSEON_Pos)   /*!< 0x00000001 */

+#define RCC_BDCR_LSEON                         RCC_BDCR_LSEON_Msk

+#define RCC_BDCR_LSERDY_Pos                    (1U)

+#define RCC_BDCR_LSERDY_Msk                    (0x1UL << RCC_BDCR_LSERDY_Pos)  /*!< 0x00000002 */

+#define RCC_BDCR_LSERDY                        RCC_BDCR_LSERDY_Msk

+#define RCC_BDCR_LSEBYP_Pos                    (2U)

+#define RCC_BDCR_LSEBYP_Msk                    (0x1UL << RCC_BDCR_LSEBYP_Pos)  /*!< 0x00000004 */

+#define RCC_BDCR_LSEBYP                        RCC_BDCR_LSEBYP_Msk

+

+#define RCC_BDCR_LSEDRV_Pos                    (3U)

+#define RCC_BDCR_LSEDRV_Msk                    (0x3UL << RCC_BDCR_LSEDRV_Pos)  /*!< 0x00000018 */

+#define RCC_BDCR_LSEDRV                        RCC_BDCR_LSEDRV_Msk

+#define RCC_BDCR_LSEDRV_0                      (0x1UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000008 */

+#define RCC_BDCR_LSEDRV_1                      (0x2UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000010 */

+

+#define RCC_BDCR_LSECSSON_Pos                  (5U)

+#define RCC_BDCR_LSECSSON_Msk                  (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */

+#define RCC_BDCR_LSECSSON                      RCC_BDCR_LSECSSON_Msk

+#define RCC_BDCR_LSECSSD_Pos                   (6U)

+#define RCC_BDCR_LSECSSD_Msk                   (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */

+#define RCC_BDCR_LSECSSD                       RCC_BDCR_LSECSSD_Msk

+

+#define RCC_BDCR_RTCSEL_Pos                    (8U)

+#define RCC_BDCR_RTCSEL_Msk                    (0x3UL << RCC_BDCR_RTCSEL_Pos)  /*!< 0x00000300 */

+#define RCC_BDCR_RTCSEL                        RCC_BDCR_RTCSEL_Msk

+#define RCC_BDCR_RTCSEL_0                      (0x1UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000100 */

+#define RCC_BDCR_RTCSEL_1                      (0x2UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000200 */

+

+#define RCC_BDCR_RTCEN_Pos                     (15U)

+#define RCC_BDCR_RTCEN_Msk                     (0x1UL << RCC_BDCR_RTCEN_Pos)   /*!< 0x00008000 */

+#define RCC_BDCR_RTCEN                         RCC_BDCR_RTCEN_Msk

+#define RCC_BDCR_BDRST_Pos                     (16U)

+#define RCC_BDCR_BDRST_Msk                     (0x1UL << RCC_BDCR_BDRST_Pos)   /*!< 0x00010000 */

+#define RCC_BDCR_BDRST                         RCC_BDCR_BDRST_Msk

+/********************  Bit definition for RCC_CSR register  *******************/

+#define RCC_CSR_LSION_Pos                      (0U)

+#define RCC_CSR_LSION_Msk                      (0x1UL << RCC_CSR_LSION_Pos)    /*!< 0x00000001 */

+#define RCC_CSR_LSION                          RCC_CSR_LSION_Msk

+#define RCC_CSR_LSIRDY_Pos                     (1U)

+#define RCC_CSR_LSIRDY_Msk                     (0x1UL << RCC_CSR_LSIRDY_Pos)   /*!< 0x00000002 */

+#define RCC_CSR_LSIRDY                         RCC_CSR_LSIRDY_Msk

+

+

+/********************  Bit definition for RCC_AHB3ENR register  **************/

+#define RCC_AHB3ENR_MDMAEN_Pos                 (0U)

+#define RCC_AHB3ENR_MDMAEN_Msk                 (0x1UL << RCC_AHB3ENR_MDMAEN_Pos)       /*!< 0x00000001 */

+#define RCC_AHB3ENR_MDMAEN                     RCC_AHB3ENR_MDMAEN_Msk

+#define RCC_AHB3ENR_DMA2DEN_Pos                (4U)

+#define RCC_AHB3ENR_DMA2DEN_Msk                (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos)      /*!< 0x00000010 */

+#define RCC_AHB3ENR_DMA2DEN                    RCC_AHB3ENR_DMA2DEN_Msk

+#define RCC_AHB3ENR_JPGDECEN_Pos               (5U)

+#define RCC_AHB3ENR_JPGDECEN_Msk               (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos)     /*!< 0x00000020 */

+#define RCC_AHB3ENR_JPGDECEN                   RCC_AHB3ENR_JPGDECEN_Msk

+#define RCC_AHB3ENR_FMCEN_Pos                  (12U)

+#define RCC_AHB3ENR_FMCEN_Msk                  (0x1UL << RCC_AHB3ENR_FMCEN_Pos)        /*!< 0x00001000 */

+#define RCC_AHB3ENR_FMCEN                      RCC_AHB3ENR_FMCEN_Msk

+#define RCC_AHB3ENR_QSPIEN_Pos                 (14U)

+#define RCC_AHB3ENR_QSPIEN_Msk                 (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)       /*!< 0x00004000 */

+#define RCC_AHB3ENR_QSPIEN                     RCC_AHB3ENR_QSPIEN_Msk

+#define RCC_AHB3ENR_SDMMC1EN_Pos               (16U)

+#define RCC_AHB3ENR_SDMMC1EN_Msk               (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos)     /*!< 0x00010000 */

+#define RCC_AHB3ENR_SDMMC1EN                   RCC_AHB3ENR_SDMMC1EN_Msk

+

+/********************  Bit definition for RCC_AHB1ENR register  ***************/

+#define RCC_AHB1ENR_DMA1EN_Pos                 (0U)

+#define RCC_AHB1ENR_DMA1EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)          /*!< 0x00000001 */

+#define RCC_AHB1ENR_DMA1EN                     RCC_AHB1ENR_DMA1EN_Msk

+#define RCC_AHB1ENR_DMA2EN_Pos                 (1U)

+#define RCC_AHB1ENR_DMA2EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)          /*!< 0x00000002 */

+#define RCC_AHB1ENR_DMA2EN                     RCC_AHB1ENR_DMA2EN_Msk

+#define RCC_AHB1ENR_ADC12EN_Pos                (5U)

+#define RCC_AHB1ENR_ADC12EN_Msk                (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)         /*!< 0x00000020 */

+#define RCC_AHB1ENR_ADC12EN                    RCC_AHB1ENR_ADC12EN_Msk

+#define RCC_AHB1ENR_ETH1MACEN_Pos              (15U)

+#define RCC_AHB1ENR_ETH1MACEN_Msk              (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos)       /*!< 0x00008000 */

+#define RCC_AHB1ENR_ETH1MACEN                  RCC_AHB1ENR_ETH1MACEN_Msk

+#define RCC_AHB1ENR_ETH1TXEN_Pos               (16U)

+#define RCC_AHB1ENR_ETH1TXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos)        /*!< 0x00010000 */

+#define RCC_AHB1ENR_ETH1TXEN                   RCC_AHB1ENR_ETH1TXEN_Msk

+#define RCC_AHB1ENR_ETH1RXEN_Pos               (17U)

+#define RCC_AHB1ENR_ETH1RXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos)        /*!< 0x00020000 */

+#define RCC_AHB1ENR_ETH1RXEN                   RCC_AHB1ENR_ETH1RXEN_Msk

+#define RCC_AHB1ENR_USB1OTGHSEN_Pos            (25U)

+#define RCC_AHB1ENR_USB1OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos)     /*!< 0x02000000 */

+#define RCC_AHB1ENR_USB1OTGHSEN                RCC_AHB1ENR_USB1OTGHSEN_Msk

+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos        (26U)

+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */

+#define RCC_AHB1ENR_USB1OTGHSULPIEN            RCC_AHB1ENR_USB1OTGHSULPIEN_Msk

+#define RCC_AHB1ENR_USB2OTGFSEN_Pos            (27U)

+#define RCC_AHB1ENR_USB2OTGFSEN_Msk            (0x1UL << RCC_AHB1ENR_USB2OTGFSEN_Pos)     /*!< 0x08000000 */

+#define RCC_AHB1ENR_USB2OTGFSEN                RCC_AHB1ENR_USB2OTGFSEN_Msk

+#define RCC_AHB1ENR_USB2OTGFSULPIEN_Pos        (28U)

+#define RCC_AHB1ENR_USB2OTGFSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB2OTGFSULPIEN_Pos) /*!< 0x10000000 */

+#define RCC_AHB1ENR_USB2OTGFSULPIEN            RCC_AHB1ENR_USB2OTGFSULPIEN_Msk

+

+/* Legacy define */

+#define RCC_AHB1ENR_USB2OTGHSEN_Pos            RCC_AHB1ENR_USB2OTGFSEN_Pos

+#define RCC_AHB1ENR_USB2OTGHSEN_Msk            RCC_AHB1ENR_USB2OTGFSEN_Msk

+#define RCC_AHB1ENR_USB2OTGHSEN                RCC_AHB1ENR_USB2OTGFSEN

+#define RCC_AHB1ENR_USB2OTGHSULPIEN_Pos        RCC_AHB1ENR_USB2OTGFSULPIEN_Pos

+#define RCC_AHB1ENR_USB2OTGHSULPIEN_Msk        RCC_AHB1ENR_USB2OTGFSULPIEN_Msk

+#define RCC_AHB1ENR_USB2OTGHSULPIEN            RCC_AHB1ENR_USB2OTGFSULPIEN

+

+

+/********************  Bit definition for RCC_AHB2ENR register  ***************/

+#define RCC_AHB2ENR_DCMIEN_Pos                 (0U)

+#define RCC_AHB2ENR_DCMIEN_Msk                 (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)          /*!< 0x00000001 */

+#define RCC_AHB2ENR_DCMIEN                     RCC_AHB2ENR_DCMIEN_Msk

+#define RCC_AHB2ENR_CRYPEN_Pos                 (4U)

+#define RCC_AHB2ENR_CRYPEN_Msk                 (0x1UL << RCC_AHB2ENR_CRYPEN_Pos)          /*!< 0x00000010 */

+#define RCC_AHB2ENR_CRYPEN                     RCC_AHB2ENR_CRYPEN_Msk

+#define RCC_AHB2ENR_HASHEN_Pos                 (5U)

+#define RCC_AHB2ENR_HASHEN_Msk                 (0x1UL << RCC_AHB2ENR_HASHEN_Pos)          /*!< 0x00000020 */

+#define RCC_AHB2ENR_HASHEN                     RCC_AHB2ENR_HASHEN_Msk

+#define RCC_AHB2ENR_RNGEN_Pos                  (6U)

+#define RCC_AHB2ENR_RNGEN_Msk                  (0x1UL << RCC_AHB2ENR_RNGEN_Pos)           /*!< 0x00000040 */

+#define RCC_AHB2ENR_RNGEN                      RCC_AHB2ENR_RNGEN_Msk

+#define RCC_AHB2ENR_SDMMC2EN_Pos               (9U)

+#define RCC_AHB2ENR_SDMMC2EN_Msk               (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)        /*!< 0x00000200 */

+#define RCC_AHB2ENR_SDMMC2EN                   RCC_AHB2ENR_SDMMC2EN_Msk

+#define RCC_AHB2ENR_SRAM1EN_Pos                (29U)

+#define RCC_AHB2ENR_SRAM1EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos)       /*!< 0x20000000 */

+#define RCC_AHB2ENR_SRAM1EN                    RCC_AHB2ENR_SRAM1EN_Msk

+#define RCC_AHB2ENR_SRAM2EN_Pos                (30U)

+#define RCC_AHB2ENR_SRAM2EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos)       /*!< 0x40000000 */

+#define RCC_AHB2ENR_SRAM2EN                    RCC_AHB2ENR_SRAM2EN_Msk

+#define RCC_AHB2ENR_SRAM3EN_Pos                (31U)

+#define RCC_AHB2ENR_SRAM3EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM3EN_Pos)       /*!< 0x80000000 */

+#define RCC_AHB2ENR_SRAM3EN                    RCC_AHB2ENR_SRAM3EN_Msk

+

+/* Legacy define */

+#define RCC_AHB2ENR_D2SRAM1EN_Pos              RCC_AHB2ENR_SRAM1EN_Pos

+#define RCC_AHB2ENR_D2SRAM1EN_Msk              RCC_AHB2ENR_SRAM1EN_Msk

+#define RCC_AHB2ENR_D2SRAM1EN                  RCC_AHB2ENR_SRAM1EN

+#define RCC_AHB2ENR_D2SRAM2EN_Pos              RCC_AHB2ENR_SRAM2EN_Pos

+#define RCC_AHB2ENR_D2SRAM2EN_Msk              RCC_AHB2ENR_SRAM2EN_Msk

+#define RCC_AHB2ENR_D2SRAM2EN                  RCC_AHB2ENR_SRAM2EN

+#define RCC_AHB2ENR_D2SRAM3EN_Pos              RCC_AHB2ENR_SRAM3EN_Pos

+#define RCC_AHB2ENR_D2SRAM3EN_Msk              RCC_AHB2ENR_SRAM3EN_Msk

+#define RCC_AHB2ENR_D2SRAM3EN                  RCC_AHB2ENR_SRAM3EN

+

+/********************  Bit definition for RCC_AHB4ENR register  ******************/

+#define RCC_AHB4ENR_GPIOAEN_Pos                (0U)

+#define RCC_AHB4ENR_GPIOAEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)         /*!< 0x00000001 */

+#define RCC_AHB4ENR_GPIOAEN                    RCC_AHB4ENR_GPIOAEN_Msk

+#define RCC_AHB4ENR_GPIOBEN_Pos                (1U)

+#define RCC_AHB4ENR_GPIOBEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)         /*!< 0x00000002 */

+#define RCC_AHB4ENR_GPIOBEN                    RCC_AHB4ENR_GPIOBEN_Msk

+#define RCC_AHB4ENR_GPIOCEN_Pos                (2U)

+#define RCC_AHB4ENR_GPIOCEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)         /*!< 0x00000004 */

+#define RCC_AHB4ENR_GPIOCEN                    RCC_AHB4ENR_GPIOCEN_Msk

+#define RCC_AHB4ENR_GPIODEN_Pos                (3U)

+#define RCC_AHB4ENR_GPIODEN_Msk                (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)         /*!< 0x00000008 */

+#define RCC_AHB4ENR_GPIODEN                    RCC_AHB4ENR_GPIODEN_Msk

+#define RCC_AHB4ENR_GPIOEEN_Pos                (4U)

+#define RCC_AHB4ENR_GPIOEEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)         /*!< 0x00000010 */

+#define RCC_AHB4ENR_GPIOEEN                    RCC_AHB4ENR_GPIOEEN_Msk

+#define RCC_AHB4ENR_GPIOFEN_Pos                (5U)

+#define RCC_AHB4ENR_GPIOFEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)         /*!< 0x00000020 */

+#define RCC_AHB4ENR_GPIOFEN                    RCC_AHB4ENR_GPIOFEN_Msk

+#define RCC_AHB4ENR_GPIOGEN_Pos                (6U)

+#define RCC_AHB4ENR_GPIOGEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)         /*!< 0x00000040 */

+#define RCC_AHB4ENR_GPIOGEN                    RCC_AHB4ENR_GPIOGEN_Msk

+#define RCC_AHB4ENR_GPIOHEN_Pos                (7U)

+#define RCC_AHB4ENR_GPIOHEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)         /*!< 0x00000080 */

+#define RCC_AHB4ENR_GPIOHEN                    RCC_AHB4ENR_GPIOHEN_Msk

+#define RCC_AHB4ENR_GPIOIEN_Pos                (8U)

+#define RCC_AHB4ENR_GPIOIEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos)         /*!< 0x00000100 */

+#define RCC_AHB4ENR_GPIOIEN                    RCC_AHB4ENR_GPIOIEN_Msk

+#define RCC_AHB4ENR_GPIOJEN_Pos                (9U)

+#define RCC_AHB4ENR_GPIOJEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos)         /*!< 0x00000200 */

+#define RCC_AHB4ENR_GPIOJEN                    RCC_AHB4ENR_GPIOJEN_Msk

+#define RCC_AHB4ENR_GPIOKEN_Pos                (10U)

+#define RCC_AHB4ENR_GPIOKEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos)         /*!< 0x00000400 */

+#define RCC_AHB4ENR_GPIOKEN                    RCC_AHB4ENR_GPIOKEN_Msk

+#define RCC_AHB4ENR_CRCEN_Pos                  (19U)

+#define RCC_AHB4ENR_CRCEN_Msk                  (0x1UL << RCC_AHB4ENR_CRCEN_Pos)           /*!< 0x00080000 */

+#define RCC_AHB4ENR_CRCEN                      RCC_AHB4ENR_CRCEN_Msk

+#define RCC_AHB4ENR_BDMAEN_Pos                 (21U)

+#define RCC_AHB4ENR_BDMAEN_Msk                 (0x1UL << RCC_AHB4ENR_BDMAEN_Pos)          /*!< 0x00200000 */

+#define RCC_AHB4ENR_BDMAEN                     RCC_AHB4ENR_BDMAEN_Msk

+#define RCC_AHB4ENR_ADC3EN_Pos                 (24U)

+#define RCC_AHB4ENR_ADC3EN_Msk                 (0x1UL << RCC_AHB4ENR_ADC3EN_Pos)          /*!< 0x01000000 */

+#define RCC_AHB4ENR_ADC3EN                     RCC_AHB4ENR_ADC3EN_Msk

+#define RCC_AHB4ENR_HSEMEN_Pos                 (25U)

+#define RCC_AHB4ENR_HSEMEN_Msk                 (0x1UL << RCC_AHB4ENR_HSEMEN_Pos)          /*!< 0x02000000 */

+#define RCC_AHB4ENR_HSEMEN                     RCC_AHB4ENR_HSEMEN_Msk

+#define RCC_AHB4ENR_BKPRAMEN_Pos               (28U)

+#define RCC_AHB4ENR_BKPRAMEN_Msk               (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)        /*!< 0x10000000 */

+#define RCC_AHB4ENR_BKPRAMEN                   RCC_AHB4ENR_BKPRAMEN_Msk

+

+/********************  Bit definition for RCC_APB3ENR register  ******************/

+#define RCC_APB3ENR_LTDCEN_Pos                 (3U)

+#define RCC_APB3ENR_LTDCEN_Msk                 (0x1UL << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */

+#define RCC_APB3ENR_LTDCEN                     RCC_APB3ENR_LTDCEN_Msk

+#define RCC_APB3ENR_WWDG1EN_Pos                (6U)

+#define RCC_APB3ENR_WWDG1EN_Msk                (0x1UL << RCC_APB3ENR_WWDG1EN_Pos) /*!< 0x00000040 */

+#define RCC_APB3ENR_WWDG1EN                    RCC_APB3ENR_WWDG1EN_Msk

+

+/********************  Bit definition for RCC_APB1LENR register  ******************/

+

+#define RCC_APB1LENR_TIM2EN_Pos                (0U)

+#define RCC_APB1LENR_TIM2EN_Msk                (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */

+#define RCC_APB1LENR_TIM2EN                    RCC_APB1LENR_TIM2EN_Msk

+#define RCC_APB1LENR_TIM3EN_Pos                (1U)

+#define RCC_APB1LENR_TIM3EN_Msk                (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */

+#define RCC_APB1LENR_TIM3EN                    RCC_APB1LENR_TIM3EN_Msk

+#define RCC_APB1LENR_TIM4EN_Pos                (2U)

+#define RCC_APB1LENR_TIM4EN_Msk                (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */

+#define RCC_APB1LENR_TIM4EN                    RCC_APB1LENR_TIM4EN_Msk

+#define RCC_APB1LENR_TIM5EN_Pos                (3U)

+#define RCC_APB1LENR_TIM5EN_Msk                (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */

+#define RCC_APB1LENR_TIM5EN                    RCC_APB1LENR_TIM5EN_Msk

+#define RCC_APB1LENR_TIM6EN_Pos                (4U)

+#define RCC_APB1LENR_TIM6EN_Msk                (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */

+#define RCC_APB1LENR_TIM6EN                    RCC_APB1LENR_TIM6EN_Msk

+#define RCC_APB1LENR_TIM7EN_Pos                (5U)

+#define RCC_APB1LENR_TIM7EN_Msk                (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */

+#define RCC_APB1LENR_TIM7EN                    RCC_APB1LENR_TIM7EN_Msk

+#define RCC_APB1LENR_TIM12EN_Pos               (6U)

+#define RCC_APB1LENR_TIM12EN_Msk               (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */

+#define RCC_APB1LENR_TIM12EN                   RCC_APB1LENR_TIM12EN_Msk

+#define RCC_APB1LENR_TIM13EN_Pos               (7U)

+#define RCC_APB1LENR_TIM13EN_Msk               (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */

+#define RCC_APB1LENR_TIM13EN                   RCC_APB1LENR_TIM13EN_Msk

+#define RCC_APB1LENR_TIM14EN_Pos               (8U)

+#define RCC_APB1LENR_TIM14EN_Msk               (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */

+#define RCC_APB1LENR_TIM14EN                   RCC_APB1LENR_TIM14EN_Msk

+#define RCC_APB1LENR_LPTIM1EN_Pos              (9U)

+#define RCC_APB1LENR_LPTIM1EN_Msk              (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */

+#define RCC_APB1LENR_LPTIM1EN                  RCC_APB1LENR_LPTIM1EN_Msk

+

+

+#define RCC_APB1LENR_SPI2EN_Pos                (14U)

+#define RCC_APB1LENR_SPI2EN_Msk                (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */

+#define RCC_APB1LENR_SPI2EN                    RCC_APB1LENR_SPI2EN_Msk

+#define RCC_APB1LENR_SPI3EN_Pos                (15U)

+#define RCC_APB1LENR_SPI3EN_Msk                (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */

+#define RCC_APB1LENR_SPI3EN                    RCC_APB1LENR_SPI3EN_Msk

+#define RCC_APB1LENR_SPDIFRXEN_Pos             (16U)

+#define RCC_APB1LENR_SPDIFRXEN_Msk             (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */

+#define RCC_APB1LENR_SPDIFRXEN                 RCC_APB1LENR_SPDIFRXEN_Msk

+#define RCC_APB1LENR_USART2EN_Pos              (17U)

+#define RCC_APB1LENR_USART2EN_Msk              (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */

+#define RCC_APB1LENR_USART2EN                  RCC_APB1LENR_USART2EN_Msk

+#define RCC_APB1LENR_USART3EN_Pos              (18U)

+#define RCC_APB1LENR_USART3EN_Msk              (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */

+#define RCC_APB1LENR_USART3EN                  RCC_APB1LENR_USART3EN_Msk

+#define RCC_APB1LENR_UART4EN_Pos               (19U)

+#define RCC_APB1LENR_UART4EN_Msk               (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */

+#define RCC_APB1LENR_UART4EN                   RCC_APB1LENR_UART4EN_Msk

+#define RCC_APB1LENR_UART5EN_Pos               (20U)

+#define RCC_APB1LENR_UART5EN_Msk               (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */

+#define RCC_APB1LENR_UART5EN                   RCC_APB1LENR_UART5EN_Msk

+#define RCC_APB1LENR_I2C1EN_Pos                (21U)

+#define RCC_APB1LENR_I2C1EN_Msk                (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */

+#define RCC_APB1LENR_I2C1EN                    RCC_APB1LENR_I2C1EN_Msk

+#define RCC_APB1LENR_I2C2EN_Pos                (22U)

+#define RCC_APB1LENR_I2C2EN_Msk                (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */

+#define RCC_APB1LENR_I2C2EN                    RCC_APB1LENR_I2C2EN_Msk

+#define RCC_APB1LENR_I2C3EN_Pos                (23U)

+#define RCC_APB1LENR_I2C3EN_Msk                (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */

+#define RCC_APB1LENR_I2C3EN                    RCC_APB1LENR_I2C3EN_Msk

+#define RCC_APB1LENR_CECEN_Pos                 (27U)

+#define RCC_APB1LENR_CECEN_Msk                 (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */

+#define RCC_APB1LENR_CECEN                     RCC_APB1LENR_CECEN_Msk

+#define RCC_APB1LENR_DAC12EN_Pos               (29U)

+#define RCC_APB1LENR_DAC12EN_Msk               (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */

+#define RCC_APB1LENR_DAC12EN                   RCC_APB1LENR_DAC12EN_Msk

+#define RCC_APB1LENR_UART7EN_Pos               (30U)

+#define RCC_APB1LENR_UART7EN_Msk               (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */

+#define RCC_APB1LENR_UART7EN                   RCC_APB1LENR_UART7EN_Msk

+#define RCC_APB1LENR_UART8EN_Pos               (31U)

+#define RCC_APB1LENR_UART8EN_Msk               (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */

+#define RCC_APB1LENR_UART8EN                   RCC_APB1LENR_UART8EN_Msk

+

+/* Legacy define */

+#define RCC_APB1LENR_HDMICECEN_Pos             RCC_APB1LENR_CECEN_Pos

+#define RCC_APB1LENR_HDMICECEN_Msk             RCC_APB1LENR_CECEN_Msk

+#define RCC_APB1LENR_HDMICECEN                 RCC_APB1LENR_CECEN

+/********************  Bit definition for RCC_APB1HENR register  ******************/

+#define RCC_APB1HENR_CRSEN_Pos                 (1U)

+#define RCC_APB1HENR_CRSEN_Msk                 (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1HENR_CRSEN                     RCC_APB1HENR_CRSEN_Msk

+#define RCC_APB1HENR_SWPMIEN_Pos               (2U)

+#define RCC_APB1HENR_SWPMIEN_Msk               (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1HENR_SWPMIEN                   RCC_APB1HENR_SWPMIEN_Msk

+#define RCC_APB1HENR_OPAMPEN_Pos               (4U)

+#define RCC_APB1HENR_OPAMPEN_Msk               (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1HENR_OPAMPEN                   RCC_APB1HENR_OPAMPEN_Msk

+#define RCC_APB1HENR_MDIOSEN_Pos               (5U)

+#define RCC_APB1HENR_MDIOSEN_Msk               (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1HENR_MDIOSEN                   RCC_APB1HENR_MDIOSEN_Msk

+#define RCC_APB1HENR_FDCANEN_Pos               (8U)

+#define RCC_APB1HENR_FDCANEN_Msk               (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1HENR_FDCANEN                   RCC_APB1HENR_FDCANEN_Msk

+

+/********************  Bit definition for RCC_APB2ENR register  ******************/

+#define RCC_APB2ENR_TIM1EN_Pos                 (0U)

+#define RCC_APB2ENR_TIM1EN_Msk                 (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */

+#define RCC_APB2ENR_TIM1EN                     RCC_APB2ENR_TIM1EN_Msk

+#define RCC_APB2ENR_TIM8EN_Pos                 (1U)

+#define RCC_APB2ENR_TIM8EN_Msk                 (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */

+#define RCC_APB2ENR_TIM8EN                     RCC_APB2ENR_TIM8EN_Msk

+#define RCC_APB2ENR_USART1EN_Pos               (4U)

+#define RCC_APB2ENR_USART1EN_Msk               (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */

+#define RCC_APB2ENR_USART1EN                   RCC_APB2ENR_USART1EN_Msk

+#define RCC_APB2ENR_USART6EN_Pos               (5U)

+#define RCC_APB2ENR_USART6EN_Msk               (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */

+#define RCC_APB2ENR_USART6EN                   RCC_APB2ENR_USART6EN_Msk

+#define RCC_APB2ENR_SPI1EN_Pos                 (12U)

+#define RCC_APB2ENR_SPI1EN_Msk                 (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */

+#define RCC_APB2ENR_SPI1EN                     RCC_APB2ENR_SPI1EN_Msk

+#define RCC_APB2ENR_SPI4EN_Pos                 (13U)

+#define RCC_APB2ENR_SPI4EN_Msk                 (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */

+#define RCC_APB2ENR_SPI4EN                     RCC_APB2ENR_SPI4EN_Msk

+#define RCC_APB2ENR_TIM15EN_Pos                (16U)

+#define RCC_APB2ENR_TIM15EN_Msk                (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */

+#define RCC_APB2ENR_TIM15EN                    RCC_APB2ENR_TIM15EN_Msk

+#define RCC_APB2ENR_TIM16EN_Pos                (17U)

+#define RCC_APB2ENR_TIM16EN_Msk                (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */

+#define RCC_APB2ENR_TIM16EN                    RCC_APB2ENR_TIM16EN_Msk

+#define RCC_APB2ENR_TIM17EN_Pos                (18U)

+#define RCC_APB2ENR_TIM17EN_Msk                (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */

+#define RCC_APB2ENR_TIM17EN                    RCC_APB2ENR_TIM17EN_Msk

+#define RCC_APB2ENR_SPI5EN_Pos                 (20U)

+#define RCC_APB2ENR_SPI5EN_Msk                 (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */

+#define RCC_APB2ENR_SPI5EN                     RCC_APB2ENR_SPI5EN_Msk

+#define RCC_APB2ENR_SAI1EN_Pos                 (22U)

+#define RCC_APB2ENR_SAI1EN_Msk                 (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */

+#define RCC_APB2ENR_SAI1EN                     RCC_APB2ENR_SAI1EN_Msk

+#define RCC_APB2ENR_SAI2EN_Pos                 (23U)

+#define RCC_APB2ENR_SAI2EN_Msk                 (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */

+#define RCC_APB2ENR_SAI2EN                     RCC_APB2ENR_SAI2EN_Msk

+#define RCC_APB2ENR_SAI3EN_Pos                 (24U)

+#define RCC_APB2ENR_SAI3EN_Msk                 (0x1UL << RCC_APB2ENR_SAI3EN_Pos) /*!< 0x01000000 */

+#define RCC_APB2ENR_SAI3EN                     RCC_APB2ENR_SAI3EN_Msk

+#define RCC_APB2ENR_DFSDM1EN_Pos               (28U)

+#define RCC_APB2ENR_DFSDM1EN_Msk               (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x10000000 */

+#define RCC_APB2ENR_DFSDM1EN                   RCC_APB2ENR_DFSDM1EN_Msk

+#define RCC_APB2ENR_HRTIMEN_Pos                (29U)

+#define RCC_APB2ENR_HRTIMEN_Msk                (0x1UL << RCC_APB2ENR_HRTIMEN_Pos) /*!< 0x20000000 */

+#define RCC_APB2ENR_HRTIMEN                    RCC_APB2ENR_HRTIMEN_Msk

+

+/********************  Bit definition for RCC_APB4ENR register  ******************/

+#define RCC_APB4ENR_SYSCFGEN_Pos               (1U)

+#define RCC_APB4ENR_SYSCFGEN_Msk               (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */

+#define RCC_APB4ENR_SYSCFGEN                   RCC_APB4ENR_SYSCFGEN_Msk

+#define RCC_APB4ENR_LPUART1EN_Pos              (3U)

+#define RCC_APB4ENR_LPUART1EN_Msk              (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */

+#define RCC_APB4ENR_LPUART1EN                  RCC_APB4ENR_LPUART1EN_Msk

+#define RCC_APB4ENR_SPI6EN_Pos                 (5U)

+#define RCC_APB4ENR_SPI6EN_Msk                 (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */

+#define RCC_APB4ENR_SPI6EN                     RCC_APB4ENR_SPI6EN_Msk

+#define RCC_APB4ENR_I2C4EN_Pos                 (7U)

+#define RCC_APB4ENR_I2C4EN_Msk                 (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */

+#define RCC_APB4ENR_I2C4EN                     RCC_APB4ENR_I2C4EN_Msk

+#define RCC_APB4ENR_LPTIM2EN_Pos               (9U)

+#define RCC_APB4ENR_LPTIM2EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */

+#define RCC_APB4ENR_LPTIM2EN                   RCC_APB4ENR_LPTIM2EN_Msk

+#define RCC_APB4ENR_LPTIM3EN_Pos               (10U)

+#define RCC_APB4ENR_LPTIM3EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */

+#define RCC_APB4ENR_LPTIM3EN                   RCC_APB4ENR_LPTIM3EN_Msk

+#define RCC_APB4ENR_LPTIM4EN_Pos               (11U)

+#define RCC_APB4ENR_LPTIM4EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos) /*!< 0x00000800 */

+#define RCC_APB4ENR_LPTIM4EN                   RCC_APB4ENR_LPTIM4EN_Msk

+#define RCC_APB4ENR_LPTIM5EN_Pos               (12U)

+#define RCC_APB4ENR_LPTIM5EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos) /*!< 0x00001000 */

+#define RCC_APB4ENR_LPTIM5EN                   RCC_APB4ENR_LPTIM5EN_Msk

+#define RCC_APB4ENR_COMP12EN_Pos               (14U)

+#define RCC_APB4ENR_COMP12EN_Msk               (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */

+#define RCC_APB4ENR_COMP12EN                   RCC_APB4ENR_COMP12EN_Msk

+#define RCC_APB4ENR_VREFEN_Pos                 (15U)

+#define RCC_APB4ENR_VREFEN_Msk                 (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */

+#define RCC_APB4ENR_VREFEN                     RCC_APB4ENR_VREFEN_Msk

+#define RCC_APB4ENR_RTCAPBEN_Pos               (16U)

+#define RCC_APB4ENR_RTCAPBEN_Msk               (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */

+#define RCC_APB4ENR_RTCAPBEN                   RCC_APB4ENR_RTCAPBEN_Msk

+#define RCC_APB4ENR_SAI4EN_Pos                 (21U)

+#define RCC_APB4ENR_SAI4EN_Msk                 (0x1UL << RCC_APB4ENR_SAI4EN_Pos) /*!< 0x00200000 */

+#define RCC_APB4ENR_SAI4EN                     RCC_APB4ENR_SAI4EN_Msk

+

+

+/********************  Bit definition for RCC_AHB3RSTR register  ***************/

+#define RCC_AHB3RSTR_MDMARST_Pos               (0U)

+#define RCC_AHB3RSTR_MDMARST_Msk               (0x1UL << RCC_AHB3RSTR_MDMARST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB3RSTR_MDMARST                   RCC_AHB3RSTR_MDMARST_Msk

+#define RCC_AHB3RSTR_DMA2DRST_Pos              (4U)

+#define RCC_AHB3RSTR_DMA2DRST_Msk              (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos)     /*!< 0x00000010 */

+#define RCC_AHB3RSTR_DMA2DRST                  RCC_AHB3RSTR_DMA2DRST_Msk

+#define RCC_AHB3RSTR_JPGDECRST_Pos             (5U)

+#define RCC_AHB3RSTR_JPGDECRST_Msk             (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos)    /*!< 0x00000020 */

+#define RCC_AHB3RSTR_JPGDECRST                 RCC_AHB3RSTR_JPGDECRST_Msk

+#define RCC_AHB3RSTR_FMCRST_Pos                (12U)

+#define RCC_AHB3RSTR_FMCRST_Msk                (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)      /*!< 0x00001000 */

+#define RCC_AHB3RSTR_FMCRST                    RCC_AHB3RSTR_FMCRST_Msk

+#define RCC_AHB3RSTR_QSPIRST_Pos               (14U)

+#define RCC_AHB3RSTR_QSPIRST_Msk               (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)     /*!< 0x00004000 */

+#define RCC_AHB3RSTR_QSPIRST                   RCC_AHB3RSTR_QSPIRST_Msk

+#define RCC_AHB3RSTR_SDMMC1RST_Pos             (16U)

+#define RCC_AHB3RSTR_SDMMC1RST_Msk             (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos)   /*!< 0x00010000 */

+#define RCC_AHB3RSTR_SDMMC1RST                 RCC_AHB3RSTR_SDMMC1RST_Msk

+

+

+/********************  Bit definition for RCC_AHB1RSTR register  ***************/

+#define RCC_AHB1RSTR_DMA1RST_Pos               (0U)

+#define RCC_AHB1RSTR_DMA1RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB1RSTR_DMA1RST                   RCC_AHB1RSTR_DMA1RST_Msk

+#define RCC_AHB1RSTR_DMA2RST_Pos               (1U)

+#define RCC_AHB1RSTR_DMA2RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)      /*!< 0x00000002 */

+#define RCC_AHB1RSTR_DMA2RST                   RCC_AHB1RSTR_DMA2RST_Msk

+#define RCC_AHB1RSTR_ADC12RST_Pos              (5U)

+#define RCC_AHB1RSTR_ADC12RST_Msk              (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)     /*!< 0x00000020 */

+#define RCC_AHB1RSTR_ADC12RST                  RCC_AHB1RSTR_ADC12RST_Msk

+#define RCC_AHB1RSTR_ETH1MACRST_Pos            (15U)

+#define RCC_AHB1RSTR_ETH1MACRST_Msk            (0x1UL << RCC_AHB1RSTR_ETH1MACRST_Pos)   /*!< 0x00008000 */

+#define RCC_AHB1RSTR_ETH1MACRST                RCC_AHB1RSTR_ETH1MACRST_Msk

+#define RCC_AHB1RSTR_USB1OTGHSRST_Pos          (25U)

+#define RCC_AHB1RSTR_USB1OTGHSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */

+#define RCC_AHB1RSTR_USB1OTGHSRST              RCC_AHB1RSTR_USB1OTGHSRST_Msk

+#define RCC_AHB1RSTR_USB2OTGFSRST_Pos          (27U)

+#define RCC_AHB1RSTR_USB2OTGFSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB2OTGFSRST_Pos) /*!< 0x08000000 */

+#define RCC_AHB1RSTR_USB2OTGFSRST              RCC_AHB1RSTR_USB2OTGFSRST_Msk

+

+/* Legacy define */

+#define RCC_AHB1RSTR_USB2OTGHSRST_Pos          RCC_AHB1RSTR_USB2OTGFSRST_Pos

+#define RCC_AHB1RSTR_USB2OTGHSRST_Msk          RCC_AHB1RSTR_USB2OTGFSRST_Msk

+#define RCC_AHB1RSTR_USB2OTGHSRST              RCC_AHB1RSTR_USB2OTGFSRST

+

+/********************  Bit definition for RCC_AHB2RSTR register  ***************/

+#define RCC_AHB2RSTR_DCMIRST_Pos               (0U)

+#define RCC_AHB2RSTR_DCMIRST_Msk               (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)       /*!< 0x00000001 */

+#define RCC_AHB2RSTR_DCMIRST                   RCC_AHB2RSTR_DCMIRST_Msk

+#define RCC_AHB2RSTR_CRYPRST_Pos               (4U)

+#define RCC_AHB2RSTR_CRYPRST_Msk               (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos)       /*!< 0x00000010 */

+#define RCC_AHB2RSTR_CRYPRST                   RCC_AHB2RSTR_CRYPRST_Msk

+#define RCC_AHB2RSTR_HASHRST_Pos               (5U)

+#define RCC_AHB2RSTR_HASHRST_Msk               (0x1UL << RCC_AHB2RSTR_HASHRST_Pos)       /*!< 0x00000020 */

+#define RCC_AHB2RSTR_HASHRST                   RCC_AHB2RSTR_HASHRST_Msk

+#define RCC_AHB2RSTR_RNGRST_Pos                (6U)

+#define RCC_AHB2RSTR_RNGRST_Msk                (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)        /*!< 0x00000040 */

+#define RCC_AHB2RSTR_RNGRST                    RCC_AHB2RSTR_RNGRST_Msk

+#define RCC_AHB2RSTR_SDMMC2RST_Pos             (9U)

+#define RCC_AHB2RSTR_SDMMC2RST_Msk             (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)     /*!< 0x00000200 */

+#define RCC_AHB2RSTR_SDMMC2RST                 RCC_AHB2RSTR_SDMMC2RST_Msk

+

+/********************  Bit definition for RCC_AHB4RSTR register  ******************/

+#define RCC_AHB4RSTR_GPIOARST_Pos              (0U)

+#define RCC_AHB4RSTR_GPIOARST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB4RSTR_GPIOARST                  RCC_AHB4RSTR_GPIOARST_Msk

+#define RCC_AHB4RSTR_GPIOBRST_Pos              (1U)

+#define RCC_AHB4RSTR_GPIOBRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)      /*!< 0x00000002 */

+#define RCC_AHB4RSTR_GPIOBRST                  RCC_AHB4RSTR_GPIOBRST_Msk

+#define RCC_AHB4RSTR_GPIOCRST_Pos              (2U)

+#define RCC_AHB4RSTR_GPIOCRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)      /*!< 0x00000004 */

+#define RCC_AHB4RSTR_GPIOCRST                  RCC_AHB4RSTR_GPIOCRST_Msk

+#define RCC_AHB4RSTR_GPIODRST_Pos              (3U)

+#define RCC_AHB4RSTR_GPIODRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)      /*!< 0x00000008 */

+#define RCC_AHB4RSTR_GPIODRST                  RCC_AHB4RSTR_GPIODRST_Msk

+#define RCC_AHB4RSTR_GPIOERST_Pos              (4U)

+#define RCC_AHB4RSTR_GPIOERST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)      /*!< 0x00000010 */

+#define RCC_AHB4RSTR_GPIOERST                  RCC_AHB4RSTR_GPIOERST_Msk

+#define RCC_AHB4RSTR_GPIOFRST_Pos              (5U)

+#define RCC_AHB4RSTR_GPIOFRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)       /*!< 0x00000020 */

+#define RCC_AHB4RSTR_GPIOFRST                  RCC_AHB4RSTR_GPIOFRST_Msk

+#define RCC_AHB4RSTR_GPIOGRST_Pos              (6U)

+#define RCC_AHB4RSTR_GPIOGRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)       /*!< 0x00000040 */

+#define RCC_AHB4RSTR_GPIOGRST                  RCC_AHB4RSTR_GPIOGRST_Msk

+#define RCC_AHB4RSTR_GPIOHRST_Pos              (7U)

+#define RCC_AHB4RSTR_GPIOHRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)       /*!< 0x00000080 */

+#define RCC_AHB4RSTR_GPIOHRST                  RCC_AHB4RSTR_GPIOHRST_Msk

+#define RCC_AHB4RSTR_GPIOIRST_Pos              (8U)

+#define RCC_AHB4RSTR_GPIOIRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos)       /*!< 0x00000100 */

+#define RCC_AHB4RSTR_GPIOIRST                  RCC_AHB4RSTR_GPIOIRST_Msk

+#define RCC_AHB4RSTR_GPIOJRST_Pos              (9U)

+#define RCC_AHB4RSTR_GPIOJRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos)       /*!< 0x00000200 */

+#define RCC_AHB4RSTR_GPIOJRST                  RCC_AHB4RSTR_GPIOJRST_Msk

+#define RCC_AHB4RSTR_GPIOKRST_Pos              (10U)

+#define RCC_AHB4RSTR_GPIOKRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos)       /*!< 0x00000400 */

+#define RCC_AHB4RSTR_GPIOKRST                  RCC_AHB4RSTR_GPIOKRST_Msk

+#define RCC_AHB4RSTR_CRCRST_Pos                (19U)

+#define RCC_AHB4RSTR_CRCRST_Msk                (0x1UL << RCC_AHB4RSTR_CRCRST_Pos)         /*!< 0x00080000 */

+#define RCC_AHB4RSTR_CRCRST                    RCC_AHB4RSTR_CRCRST_Msk

+#define RCC_AHB4RSTR_BDMARST_Pos               (21U)

+#define RCC_AHB4RSTR_BDMARST_Msk               (0x1UL << RCC_AHB4RSTR_BDMARST_Pos)        /*!< 0x00200000 */

+#define RCC_AHB4RSTR_BDMARST                   RCC_AHB4RSTR_BDMARST_Msk

+#define RCC_AHB4RSTR_ADC3RST_Pos               (24U)

+#define RCC_AHB4RSTR_ADC3RST_Msk               (0x1UL << RCC_AHB4RSTR_ADC3RST_Pos)        /*!< 0x01000000 */

+#define RCC_AHB4RSTR_ADC3RST                   RCC_AHB4RSTR_ADC3RST_Msk

+#define RCC_AHB4RSTR_HSEMRST_Pos               (25U)

+#define RCC_AHB4RSTR_HSEMRST_Msk               (0x1UL << RCC_AHB4RSTR_HSEMRST_Pos)        /*!< 0x02000000 */

+#define RCC_AHB4RSTR_HSEMRST                   RCC_AHB4RSTR_HSEMRST_Msk

+

+

+/********************  Bit definition for RCC_APB3RSTR register  ******************/

+#define RCC_APB3RSTR_LTDCRST_Pos               (3U)

+#define RCC_APB3RSTR_LTDCRST_Msk               (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */

+#define RCC_APB3RSTR_LTDCRST                   RCC_APB3RSTR_LTDCRST_Msk

+

+/********************  Bit definition for RCC_APB1LRSTR register  ******************/

+

+#define RCC_APB1LRSTR_TIM2RST_Pos              (0U)

+#define RCC_APB1LRSTR_TIM2RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */

+#define RCC_APB1LRSTR_TIM2RST                  RCC_APB1LRSTR_TIM2RST_Msk

+#define RCC_APB1LRSTR_TIM3RST_Pos              (1U)

+#define RCC_APB1LRSTR_TIM3RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */

+#define RCC_APB1LRSTR_TIM3RST                  RCC_APB1LRSTR_TIM3RST_Msk

+#define RCC_APB1LRSTR_TIM4RST_Pos              (2U)

+#define RCC_APB1LRSTR_TIM4RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */

+#define RCC_APB1LRSTR_TIM4RST                  RCC_APB1LRSTR_TIM4RST_Msk

+#define RCC_APB1LRSTR_TIM5RST_Pos              (3U)

+#define RCC_APB1LRSTR_TIM5RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */

+#define RCC_APB1LRSTR_TIM5RST                  RCC_APB1LRSTR_TIM5RST_Msk

+#define RCC_APB1LRSTR_TIM6RST_Pos              (4U)

+#define RCC_APB1LRSTR_TIM6RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */

+#define RCC_APB1LRSTR_TIM6RST                  RCC_APB1LRSTR_TIM6RST_Msk

+#define RCC_APB1LRSTR_TIM7RST_Pos              (5U)

+#define RCC_APB1LRSTR_TIM7RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */

+#define RCC_APB1LRSTR_TIM7RST                  RCC_APB1LRSTR_TIM7RST_Msk

+#define RCC_APB1LRSTR_TIM12RST_Pos             (6U)

+#define RCC_APB1LRSTR_TIM12RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */

+#define RCC_APB1LRSTR_TIM12RST                 RCC_APB1LRSTR_TIM12RST_Msk

+#define RCC_APB1LRSTR_TIM13RST_Pos             (7U)

+#define RCC_APB1LRSTR_TIM13RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */

+#define RCC_APB1LRSTR_TIM13RST                 RCC_APB1LRSTR_TIM13RST_Msk

+#define RCC_APB1LRSTR_TIM14RST_Pos             (8U)

+#define RCC_APB1LRSTR_TIM14RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */

+#define RCC_APB1LRSTR_TIM14RST                 RCC_APB1LRSTR_TIM14RST_Msk

+#define RCC_APB1LRSTR_LPTIM1RST_Pos            (9U)

+#define RCC_APB1LRSTR_LPTIM1RST_Msk            (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */

+#define RCC_APB1LRSTR_LPTIM1RST                RCC_APB1LRSTR_LPTIM1RST_Msk

+#define RCC_APB1LRSTR_SPI2RST_Pos              (14U)

+#define RCC_APB1LRSTR_SPI2RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */

+#define RCC_APB1LRSTR_SPI2RST                  RCC_APB1LRSTR_SPI2RST_Msk

+#define RCC_APB1LRSTR_SPI3RST_Pos              (15U)

+#define RCC_APB1LRSTR_SPI3RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */

+#define RCC_APB1LRSTR_SPI3RST                  RCC_APB1LRSTR_SPI3RST_Msk

+#define RCC_APB1LRSTR_SPDIFRXRST_Pos           (16U)

+#define RCC_APB1LRSTR_SPDIFRXRST_Msk           (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */

+#define RCC_APB1LRSTR_SPDIFRXRST               RCC_APB1LRSTR_SPDIFRXRST_Msk

+#define RCC_APB1LRSTR_USART2RST_Pos            (17U)

+#define RCC_APB1LRSTR_USART2RST_Msk            (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */

+#define RCC_APB1LRSTR_USART2RST                RCC_APB1LRSTR_USART2RST_Msk

+#define RCC_APB1LRSTR_USART3RST_Pos            (18U)

+#define RCC_APB1LRSTR_USART3RST_Msk            (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */

+#define RCC_APB1LRSTR_USART3RST                RCC_APB1LRSTR_USART3RST_Msk

+#define RCC_APB1LRSTR_UART4RST_Pos             (19U)

+#define RCC_APB1LRSTR_UART4RST_Msk             (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */

+#define RCC_APB1LRSTR_UART4RST                 RCC_APB1LRSTR_UART4RST_Msk

+#define RCC_APB1LRSTR_UART5RST_Pos             (20U)

+#define RCC_APB1LRSTR_UART5RST_Msk             (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */

+#define RCC_APB1LRSTR_UART5RST                 RCC_APB1LRSTR_UART5RST_Msk

+#define RCC_APB1LRSTR_I2C1RST_Pos              (21U)

+#define RCC_APB1LRSTR_I2C1RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */

+#define RCC_APB1LRSTR_I2C1RST                  RCC_APB1LRSTR_I2C1RST_Msk

+#define RCC_APB1LRSTR_I2C2RST_Pos              (22U)

+#define RCC_APB1LRSTR_I2C2RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */

+#define RCC_APB1LRSTR_I2C2RST                  RCC_APB1LRSTR_I2C2RST_Msk

+#define RCC_APB1LRSTR_I2C3RST_Pos              (23U)

+#define RCC_APB1LRSTR_I2C3RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */

+#define RCC_APB1LRSTR_I2C3RST                  RCC_APB1LRSTR_I2C3RST_Msk

+#define RCC_APB1LRSTR_CECRST_Pos               (27U)

+#define RCC_APB1LRSTR_CECRST_Msk               (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */

+#define RCC_APB1LRSTR_CECRST                   RCC_APB1LRSTR_CECRST_Msk

+#define RCC_APB1LRSTR_DAC12RST_Pos             (29U)

+#define RCC_APB1LRSTR_DAC12RST_Msk             (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */

+#define RCC_APB1LRSTR_DAC12RST                 RCC_APB1LRSTR_DAC12RST_Msk

+#define RCC_APB1LRSTR_UART7RST_Pos             (30U)

+#define RCC_APB1LRSTR_UART7RST_Msk             (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */

+#define RCC_APB1LRSTR_UART7RST                 RCC_APB1LRSTR_UART7RST_Msk

+#define RCC_APB1LRSTR_UART8RST_Pos             (31U)

+#define RCC_APB1LRSTR_UART8RST_Msk             (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */

+#define RCC_APB1LRSTR_UART8RST                 RCC_APB1LRSTR_UART8RST_Msk

+

+/* Legacy define */

+#define RCC_APB1LRSTR_HDMICECRST_Pos           RCC_APB1LRSTR_CECRST_Pos

+#define RCC_APB1LRSTR_HDMICECRST_Msk           RCC_APB1LRSTR_CECRST_Msk

+#define RCC_APB1LRSTR_HDMICECRST               RCC_APB1LRSTR_CECRST

+/********************  Bit definition for RCC_APB1HRSTR register  ******************/

+#define RCC_APB1HRSTR_CRSRST_Pos               (1U)

+#define RCC_APB1HRSTR_CRSRST_Msk               (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */

+#define RCC_APB1HRSTR_CRSRST                   RCC_APB1HRSTR_CRSRST_Msk

+#define RCC_APB1HRSTR_SWPMIRST_Pos             (2U)

+#define RCC_APB1HRSTR_SWPMIRST_Msk             (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */

+#define RCC_APB1HRSTR_SWPMIRST                 RCC_APB1HRSTR_SWPMIRST_Msk

+#define RCC_APB1HRSTR_OPAMPRST_Pos             (4U)

+#define RCC_APB1HRSTR_OPAMPRST_Msk             (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */

+#define RCC_APB1HRSTR_OPAMPRST                 RCC_APB1HRSTR_OPAMPRST_Msk

+#define RCC_APB1HRSTR_MDIOSRST_Pos             (5U)

+#define RCC_APB1HRSTR_MDIOSRST_Msk             (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */

+#define RCC_APB1HRSTR_MDIOSRST                 RCC_APB1HRSTR_MDIOSRST_Msk

+#define RCC_APB1HRSTR_FDCANRST_Pos             (8U)

+#define RCC_APB1HRSTR_FDCANRST_Msk             (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */

+#define RCC_APB1HRSTR_FDCANRST                 RCC_APB1HRSTR_FDCANRST_Msk

+

+/********************  Bit definition for RCC_APB2RSTR register  ******************/

+#define RCC_APB2RSTR_TIM1RST_Pos               (0U)

+#define RCC_APB2RSTR_TIM1RST_Msk               (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */

+#define RCC_APB2RSTR_TIM1RST                   RCC_APB2RSTR_TIM1RST_Msk

+#define RCC_APB2RSTR_TIM8RST_Pos               (1U)

+#define RCC_APB2RSTR_TIM8RST_Msk               (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */

+#define RCC_APB2RSTR_TIM8RST                   RCC_APB2RSTR_TIM8RST_Msk

+#define RCC_APB2RSTR_USART1RST_Pos             (4U)

+#define RCC_APB2RSTR_USART1RST_Msk             (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */

+#define RCC_APB2RSTR_USART1RST                 RCC_APB2RSTR_USART1RST_Msk

+#define RCC_APB2RSTR_USART6RST_Pos             (5U)

+#define RCC_APB2RSTR_USART6RST_Msk             (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */

+#define RCC_APB2RSTR_USART6RST                 RCC_APB2RSTR_USART6RST_Msk

+#define RCC_APB2RSTR_SPI1RST_Pos               (12U)

+#define RCC_APB2RSTR_SPI1RST_Msk               (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */

+#define RCC_APB2RSTR_SPI1RST                   RCC_APB2RSTR_SPI1RST_Msk

+#define RCC_APB2RSTR_SPI4RST_Pos               (13U)

+#define RCC_APB2RSTR_SPI4RST_Msk               (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */

+#define RCC_APB2RSTR_SPI4RST                   RCC_APB2RSTR_SPI4RST_Msk

+#define RCC_APB2RSTR_TIM15RST_Pos              (16U)

+#define RCC_APB2RSTR_TIM15RST_Msk              (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */

+#define RCC_APB2RSTR_TIM15RST                  RCC_APB2RSTR_TIM15RST_Msk

+#define RCC_APB2RSTR_TIM16RST_Pos              (17U)

+#define RCC_APB2RSTR_TIM16RST_Msk              (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */

+#define RCC_APB2RSTR_TIM16RST                  RCC_APB2RSTR_TIM16RST_Msk

+#define RCC_APB2RSTR_TIM17RST_Pos              (18U)

+#define RCC_APB2RSTR_TIM17RST_Msk              (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */

+#define RCC_APB2RSTR_TIM17RST                  RCC_APB2RSTR_TIM17RST_Msk

+#define RCC_APB2RSTR_SPI5RST_Pos               (20U)

+#define RCC_APB2RSTR_SPI5RST_Msk               (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */

+#define RCC_APB2RSTR_SPI5RST                   RCC_APB2RSTR_SPI5RST_Msk

+#define RCC_APB2RSTR_SAI1RST_Pos               (22U)

+#define RCC_APB2RSTR_SAI1RST_Msk               (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */

+#define RCC_APB2RSTR_SAI1RST                   RCC_APB2RSTR_SAI1RST_Msk

+#define RCC_APB2RSTR_SAI2RST_Pos               (23U)

+#define RCC_APB2RSTR_SAI2RST_Msk               (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */

+#define RCC_APB2RSTR_SAI2RST                   RCC_APB2RSTR_SAI2RST_Msk

+#define RCC_APB2RSTR_SAI3RST_Pos               (24U)

+#define RCC_APB2RSTR_SAI3RST_Msk               (0x1UL << RCC_APB2RSTR_SAI3RST_Pos) /*!< 0x01000000 */

+#define RCC_APB2RSTR_SAI3RST                   RCC_APB2RSTR_SAI3RST_Msk

+#define RCC_APB2RSTR_DFSDM1RST_Pos             (28U)

+#define RCC_APB2RSTR_DFSDM1RST_Msk             (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */

+#define RCC_APB2RSTR_DFSDM1RST                 RCC_APB2RSTR_DFSDM1RST_Msk

+#define RCC_APB2RSTR_HRTIMRST_Pos              (29U)

+#define RCC_APB2RSTR_HRTIMRST_Msk              (0x1UL << RCC_APB2RSTR_HRTIMRST_Pos) /*!< 0x20000000 */

+#define RCC_APB2RSTR_HRTIMRST                  RCC_APB2RSTR_HRTIMRST_Msk

+

+/********************  Bit definition for RCC_APB4RSTR register  ******************/

+#define RCC_APB4RSTR_SYSCFGRST_Pos             (1U)

+#define RCC_APB4RSTR_SYSCFGRST_Msk             (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */

+#define RCC_APB4RSTR_SYSCFGRST                 RCC_APB4RSTR_SYSCFGRST_Msk

+#define RCC_APB4RSTR_LPUART1RST_Pos            (3U)

+#define RCC_APB4RSTR_LPUART1RST_Msk            (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */

+#define RCC_APB4RSTR_LPUART1RST                RCC_APB4RSTR_LPUART1RST_Msk

+#define RCC_APB4RSTR_SPI6RST_Pos               (5U)

+#define RCC_APB4RSTR_SPI6RST_Msk               (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */

+#define RCC_APB4RSTR_SPI6RST                   RCC_APB4RSTR_SPI6RST_Msk

+#define RCC_APB4RSTR_I2C4RST_Pos               (7U)

+#define RCC_APB4RSTR_I2C4RST_Msk               (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */

+#define RCC_APB4RSTR_I2C4RST                   RCC_APB4RSTR_I2C4RST_Msk

+#define RCC_APB4RSTR_LPTIM2RST_Pos             (9U)

+#define RCC_APB4RSTR_LPTIM2RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */

+#define RCC_APB4RSTR_LPTIM2RST                 RCC_APB4RSTR_LPTIM2RST_Msk

+#define RCC_APB4RSTR_LPTIM3RST_Pos             (10U)

+#define RCC_APB4RSTR_LPTIM3RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */

+#define RCC_APB4RSTR_LPTIM3RST                 RCC_APB4RSTR_LPTIM3RST_Msk

+#define RCC_APB4RSTR_LPTIM4RST_Pos             (11U)

+#define RCC_APB4RSTR_LPTIM4RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos) /*!< 0x00000800 */

+#define RCC_APB4RSTR_LPTIM4RST                 RCC_APB4RSTR_LPTIM4RST_Msk

+#define RCC_APB4RSTR_LPTIM5RST_Pos             (12U)

+#define RCC_APB4RSTR_LPTIM5RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos) /*!< 0x00001000 */

+#define RCC_APB4RSTR_LPTIM5RST                 RCC_APB4RSTR_LPTIM5RST_Msk

+#define RCC_APB4RSTR_COMP12RST_Pos             (14U)

+#define RCC_APB4RSTR_COMP12RST_Msk             (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */

+#define RCC_APB4RSTR_COMP12RST                 RCC_APB4RSTR_COMP12RST_Msk

+#define RCC_APB4RSTR_VREFRST_Pos               (15U)

+#define RCC_APB4RSTR_VREFRST_Msk               (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */

+#define RCC_APB4RSTR_VREFRST                   RCC_APB4RSTR_VREFRST_Msk

+#define RCC_APB4RSTR_SAI4RST_Pos               (21U)

+#define RCC_APB4RSTR_SAI4RST_Msk               (0x1UL << RCC_APB4RSTR_SAI4RST_Pos) /*!< 0x00200000 */

+#define RCC_APB4RSTR_SAI4RST                   RCC_APB4RSTR_SAI4RST_Msk

+

+

+/********************  Bit definition for RCC_GCR register  ********************/

+#define RCC_GCR_WW1RSC_Pos                     (0U)

+#define RCC_GCR_WW1RSC_Msk                     (0x1UL << RCC_GCR_WW1RSC_Pos)   /*!< 0x00000001 */

+#define RCC_GCR_WW1RSC                         RCC_GCR_WW1RSC_Msk

+

+/********************  Bit definition for RCC_D3AMR register  ********************/

+#define RCC_D3AMR_BDMAAMEN_Pos                 (0U)

+#define RCC_D3AMR_BDMAAMEN_Msk                 (0x1UL << RCC_D3AMR_BDMAAMEN_Pos) /*!< 0x00000001 */

+#define RCC_D3AMR_BDMAAMEN                     RCC_D3AMR_BDMAAMEN_Msk

+#define RCC_D3AMR_LPUART1AMEN_Pos              (3U)

+#define RCC_D3AMR_LPUART1AMEN_Msk              (0x1UL << RCC_D3AMR_LPUART1AMEN_Pos) /*!< 0x00000008 */

+#define RCC_D3AMR_LPUART1AMEN                  RCC_D3AMR_LPUART1AMEN_Msk

+#define RCC_D3AMR_SPI6AMEN_Pos                 (5U)

+#define RCC_D3AMR_SPI6AMEN_Msk                 (0x1UL << RCC_D3AMR_SPI6AMEN_Pos) /*!< 0x00000020 */

+#define RCC_D3AMR_SPI6AMEN                     RCC_D3AMR_SPI6AMEN_Msk

+#define RCC_D3AMR_I2C4AMEN_Pos                 (7U)

+#define RCC_D3AMR_I2C4AMEN_Msk                 (0x1UL << RCC_D3AMR_I2C4AMEN_Pos) /*!< 0x00000080 */

+#define RCC_D3AMR_I2C4AMEN                     RCC_D3AMR_I2C4AMEN_Msk

+#define RCC_D3AMR_LPTIM2AMEN_Pos               (9U)

+#define RCC_D3AMR_LPTIM2AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */

+#define RCC_D3AMR_LPTIM2AMEN                   RCC_D3AMR_LPTIM2AMEN_Msk

+#define RCC_D3AMR_LPTIM3AMEN_Pos               (10U)

+#define RCC_D3AMR_LPTIM3AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */

+#define RCC_D3AMR_LPTIM3AMEN                   RCC_D3AMR_LPTIM3AMEN_Msk

+#define RCC_D3AMR_LPTIM4AMEN_Pos               (11U)

+#define RCC_D3AMR_LPTIM4AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM4AMEN_Pos) /*!< 0x00000800 */

+#define RCC_D3AMR_LPTIM4AMEN                   RCC_D3AMR_LPTIM4AMEN_Msk

+#define RCC_D3AMR_LPTIM5AMEN_Pos               (12U)

+#define RCC_D3AMR_LPTIM5AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM5AMEN_Pos) /*!< 0x00001000 */

+#define RCC_D3AMR_LPTIM5AMEN                   RCC_D3AMR_LPTIM5AMEN_Msk

+#define RCC_D3AMR_COMP12AMEN_Pos               (14U)

+#define RCC_D3AMR_COMP12AMEN_Msk               (0x1UL << RCC_D3AMR_COMP12AMEN_Pos) /*!< 0x00004000 */

+#define RCC_D3AMR_COMP12AMEN                   RCC_D3AMR_COMP12AMEN_Msk

+#define RCC_D3AMR_VREFAMEN_Pos                 (15U)

+#define RCC_D3AMR_VREFAMEN_Msk                 (0x1UL << RCC_D3AMR_VREFAMEN_Pos) /*!< 0x00008000 */

+#define RCC_D3AMR_VREFAMEN                     RCC_D3AMR_VREFAMEN_Msk

+#define RCC_D3AMR_RTCAMEN_Pos                  (16U)

+#define RCC_D3AMR_RTCAMEN_Msk                  (0x1UL << RCC_D3AMR_RTCAMEN_Pos) /*!< 0x00010000 */

+#define RCC_D3AMR_RTCAMEN                      RCC_D3AMR_RTCAMEN_Msk

+#define RCC_D3AMR_CRCAMEN_Pos                  (19U)

+#define RCC_D3AMR_CRCAMEN_Msk                  (0x1UL << RCC_D3AMR_CRCAMEN_Pos) /*!< 0x00080000 */

+#define RCC_D3AMR_CRCAMEN                      RCC_D3AMR_CRCAMEN_Msk

+#define RCC_D3AMR_SAI4AMEN_Pos                 (21U)

+#define RCC_D3AMR_SAI4AMEN_Msk                 (0x1UL << RCC_D3AMR_SAI4AMEN_Pos) /*!< 0x00200000 */

+#define RCC_D3AMR_SAI4AMEN                     RCC_D3AMR_SAI4AMEN_Msk

+#define RCC_D3AMR_ADC3AMEN_Pos                 (24U)

+#define RCC_D3AMR_ADC3AMEN_Msk                 (0x1UL << RCC_D3AMR_ADC3AMEN_Pos) /*!< 0x01000000 */

+#define RCC_D3AMR_ADC3AMEN                     RCC_D3AMR_ADC3AMEN_Msk

+

+

+#define RCC_D3AMR_BKPRAMAMEN_Pos               (28U)

+#define RCC_D3AMR_BKPRAMAMEN_Msk               (0x1UL << RCC_D3AMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */

+#define RCC_D3AMR_BKPRAMAMEN                   RCC_D3AMR_BKPRAMAMEN_Msk

+#define RCC_D3AMR_SRAM4AMEN_Pos                (29U)

+#define RCC_D3AMR_SRAM4AMEN_Msk                (0x1UL << RCC_D3AMR_SRAM4AMEN_Pos) /*!< 0x20000000 */

+#define RCC_D3AMR_SRAM4AMEN                    RCC_D3AMR_SRAM4AMEN_Msk

+/********************  Bit definition for RCC_AHB3LPENR register  **************/

+#define RCC_AHB3LPENR_MDMALPEN_Pos             (0U)

+#define RCC_AHB3LPENR_MDMALPEN_Msk             (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos)         /*!< 0x00000001 */

+#define RCC_AHB3LPENR_MDMALPEN                 RCC_AHB3LPENR_MDMALPEN_Msk

+#define RCC_AHB3LPENR_DMA2DLPEN_Pos            (4U)

+#define RCC_AHB3LPENR_DMA2DLPEN_Msk            (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos)        /*!< 0x00000010 */

+#define RCC_AHB3LPENR_DMA2DLPEN                RCC_AHB3LPENR_DMA2DLPEN_Msk

+#define RCC_AHB3LPENR_JPGDECLPEN_Pos           (5U)

+#define RCC_AHB3LPENR_JPGDECLPEN_Msk           (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos)       /*!< 0x00000020 */

+#define RCC_AHB3LPENR_JPGDECLPEN               RCC_AHB3LPENR_JPGDECLPEN_Msk

+#define RCC_AHB3LPENR_FLASHLPEN_Pos            (8U)

+#define RCC_AHB3LPENR_FLASHLPEN_Msk            (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos)        /*!< 0x00000100 */

+#define RCC_AHB3LPENR_FLASHLPEN                RCC_AHB3LPENR_FLASHLPEN_Msk

+#define RCC_AHB3LPENR_FMCLPEN_Pos              (12U)

+#define RCC_AHB3LPENR_FMCLPEN_Msk              (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)          /*!< 0x00001000 */

+#define RCC_AHB3LPENR_FMCLPEN                  RCC_AHB3LPENR_FMCLPEN_Msk

+#define RCC_AHB3LPENR_QSPILPEN_Pos             (14U)

+#define RCC_AHB3LPENR_QSPILPEN_Msk             (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos)         /*!< 0x00004000 */

+#define RCC_AHB3LPENR_QSPILPEN                 RCC_AHB3LPENR_QSPILPEN_Msk

+#define RCC_AHB3LPENR_SDMMC1LPEN_Pos           (16U)

+#define RCC_AHB3LPENR_SDMMC1LPEN_Msk           (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos)       /*!< 0x00010000 */

+#define RCC_AHB3LPENR_SDMMC1LPEN               RCC_AHB3LPENR_SDMMC1LPEN_Msk

+#define RCC_AHB3LPENR_DTCM1LPEN_Pos            (28U)

+#define RCC_AHB3LPENR_DTCM1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos)        /*!< 0x10000000 */

+#define RCC_AHB3LPENR_DTCM1LPEN                RCC_AHB3LPENR_DTCM1LPEN_Msk

+#define RCC_AHB3LPENR_DTCM2LPEN_Pos            (29U)

+#define RCC_AHB3LPENR_DTCM2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos)        /*!< 0x20000000 */

+#define RCC_AHB3LPENR_DTCM2LPEN                RCC_AHB3LPENR_DTCM2LPEN_Msk

+#define RCC_AHB3LPENR_ITCMLPEN_Pos             (30U)

+#define RCC_AHB3LPENR_ITCMLPEN_Msk             (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos)         /*!< 0x40000000 */

+#define RCC_AHB3LPENR_ITCMLPEN                 RCC_AHB3LPENR_ITCMLPEN_Msk

+#define RCC_AHB3LPENR_AXISRAMLPEN_Pos          (31U)

+#define RCC_AHB3LPENR_AXISRAMLPEN_Msk          (0x1UL << RCC_AHB3LPENR_AXISRAMLPEN_Pos)      /*!< 0x80000000 */

+#define RCC_AHB3LPENR_AXISRAMLPEN              RCC_AHB3LPENR_AXISRAMLPEN_Msk

+

+

+/********************  Bit definition for RCC_AHB1LPENR register  ***************/

+#define RCC_AHB1LPENR_DMA1LPEN_Pos             (0U)

+#define RCC_AHB1LPENR_DMA1LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB1LPENR_DMA1LPEN                 RCC_AHB1LPENR_DMA1LPEN_Msk

+#define RCC_AHB1LPENR_DMA2LPEN_Pos             (1U)

+#define RCC_AHB1LPENR_DMA2LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */

+#define RCC_AHB1LPENR_DMA2LPEN                 RCC_AHB1LPENR_DMA2LPEN_Msk

+#define RCC_AHB1LPENR_ADC12LPEN_Pos            (5U)

+#define RCC_AHB1LPENR_ADC12LPEN_Msk            (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB1LPENR_ADC12LPEN                RCC_AHB1LPENR_ADC12LPEN_Msk

+#define RCC_AHB1LPENR_ETH1MACLPEN_Pos          (15U)

+#define RCC_AHB1LPENR_ETH1MACLPEN_Msk          (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) /*!< 0x00008000 */

+#define RCC_AHB1LPENR_ETH1MACLPEN              RCC_AHB1LPENR_ETH1MACLPEN_Msk

+#define RCC_AHB1LPENR_ETH1TXLPEN_Pos           (16U)

+#define RCC_AHB1LPENR_ETH1TXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00010000 */

+#define RCC_AHB1LPENR_ETH1TXLPEN               RCC_AHB1LPENR_ETH1TXLPEN_Msk

+#define RCC_AHB1LPENR_ETH1RXLPEN_Pos           (17U)

+#define RCC_AHB1LPENR_ETH1RXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00020000 */

+#define RCC_AHB1LPENR_ETH1RXLPEN               RCC_AHB1LPENR_ETH1RXLPEN_Msk

+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos        (25U)

+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */

+#define RCC_AHB1LPENR_USB1OTGHSLPEN            RCC_AHB1LPENR_USB1OTGHSLPEN_Msk

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos    (26U)

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN        RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGFSLPEN_Pos        (27U)

+#define RCC_AHB1LPENR_USB2OTGFSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB2OTGFSLPEN_Pos) /*!< 0x08000000 */

+#define RCC_AHB1LPENR_USB2OTGFSLPEN            RCC_AHB1LPENR_USB2OTGFSLPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos    (28U)

+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos) /*!< 0x10000000 */

+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN        RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk

+

+/* Legacy define */

+#define RCC_AHB1LPENR_USB2OTGHSLPEN_Pos        RCC_AHB1LPENR_USB2OTGFSLPEN_Pos

+#define RCC_AHB1LPENR_USB2OTGHSLPEN_Msk        RCC_AHB1LPENR_USB2OTGFSLPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGHSLPEN            RCC_AHB1LPENR_USB2OTGFSLPEN

+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Pos    RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos

+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Msk    RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN        RCC_AHB1LPENR_USB2OTGFSULPILPEN

+

+/********************  Bit definition for RCC_AHB2LPENR register  ***************/

+#define RCC_AHB2LPENR_DCMILPEN_Pos             (0U)

+#define RCC_AHB2LPENR_DCMILPEN_Msk             (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB2LPENR_DCMILPEN                 RCC_AHB2LPENR_DCMILPEN_Msk

+#define RCC_AHB2LPENR_CRYPLPEN_Pos             (4U)

+#define RCC_AHB2LPENR_CRYPLPEN_Msk             (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */

+#define RCC_AHB2LPENR_CRYPLPEN                 RCC_AHB2LPENR_CRYPLPEN_Msk

+#define RCC_AHB2LPENR_HASHLPEN_Pos             (5U)

+#define RCC_AHB2LPENR_HASHLPEN_Msk             (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB2LPENR_HASHLPEN                 RCC_AHB2LPENR_HASHLPEN_Msk

+#define RCC_AHB2LPENR_RNGLPEN_Pos              (6U)

+#define RCC_AHB2LPENR_RNGLPEN_Msk              (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */

+#define RCC_AHB2LPENR_RNGLPEN                  RCC_AHB2LPENR_RNGLPEN_Msk

+#define RCC_AHB2LPENR_SDMMC2LPEN_Pos           (9U)

+#define RCC_AHB2LPENR_SDMMC2LPEN_Msk           (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */

+#define RCC_AHB2LPENR_SDMMC2LPEN               RCC_AHB2LPENR_SDMMC2LPEN_Msk

+#define RCC_AHB2LPENR_SRAM1LPEN_Pos          (29U)

+#define RCC_AHB2LPENR_SRAM1LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos) /*!< 0x20000000 */

+#define RCC_AHB2LPENR_SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN_Msk

+#define RCC_AHB2LPENR_SRAM2LPEN_Pos          (30U)

+#define RCC_AHB2LPENR_SRAM2LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */

+#define RCC_AHB2LPENR_SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN_Msk

+#define RCC_AHB2LPENR_SRAM3LPEN_Pos          (31U)

+#define RCC_AHB2LPENR_SRAM3LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM3LPEN_Pos) /*!< 0x80000000 */

+#define RCC_AHB2LPENR_SRAM3LPEN              RCC_AHB2LPENR_SRAM3LPEN_Msk

+

+/* Legacy define */

+#define RCC_AHB2LPENR_D2SRAM1LPEN_Pos          RCC_AHB2LPENR_SRAM1LPEN_Pos

+#define RCC_AHB2LPENR_D2SRAM1LPEN_Msk          RCC_AHB2LPENR_SRAM1LPEN_Msk

+#define RCC_AHB2LPENR_D2SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN

+#define RCC_AHB2LPENR_D2SRAM2LPEN_Pos          RCC_AHB2LPENR_SRAM2LPEN_Pos

+#define RCC_AHB2LPENR_D2SRAM2LPEN_Msk          RCC_AHB2LPENR_SRAM2LPEN_Msk

+#define RCC_AHB2LPENR_D2SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN

+#define RCC_AHB2LPENR_D2SRAM3LPEN_Pos          RCC_AHB2LPENR_SRAM3LPEN_Pos

+#define RCC_AHB2LPENR_D2SRAM3LPEN_Msk          RCC_AHB2LPENR_SRAM3LPEN_Msk

+#define RCC_AHB2LPENR_D2SRAM3LPEN              RCC_AHB2LPENR_SRAM3LPEN

+

+/********************  Bit definition for RCC_AHB4LPENR register  ******************/

+#define RCC_AHB4LPENR_GPIOALPEN_Pos            (0U)

+#define RCC_AHB4LPENR_GPIOALPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB4LPENR_GPIOALPEN                RCC_AHB4LPENR_GPIOALPEN_Msk

+#define RCC_AHB4LPENR_GPIOBLPEN_Pos            (1U)

+#define RCC_AHB4LPENR_GPIOBLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */

+#define RCC_AHB4LPENR_GPIOBLPEN                RCC_AHB4LPENR_GPIOBLPEN_Msk

+#define RCC_AHB4LPENR_GPIOCLPEN_Pos            (2U)

+#define RCC_AHB4LPENR_GPIOCLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */

+#define RCC_AHB4LPENR_GPIOCLPEN                RCC_AHB4LPENR_GPIOCLPEN_Msk

+#define RCC_AHB4LPENR_GPIODLPEN_Pos            (3U)

+#define RCC_AHB4LPENR_GPIODLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */

+#define RCC_AHB4LPENR_GPIODLPEN                RCC_AHB4LPENR_GPIODLPEN_Msk

+#define RCC_AHB4LPENR_GPIOELPEN_Pos            (4U)

+#define RCC_AHB4LPENR_GPIOELPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */

+#define RCC_AHB4LPENR_GPIOELPEN                RCC_AHB4LPENR_GPIOELPEN_Msk

+#define RCC_AHB4LPENR_GPIOFLPEN_Pos            (5U)

+#define RCC_AHB4LPENR_GPIOFLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB4LPENR_GPIOFLPEN                RCC_AHB4LPENR_GPIOFLPEN_Msk

+#define RCC_AHB4LPENR_GPIOGLPEN_Pos            (6U)

+#define RCC_AHB4LPENR_GPIOGLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */

+#define RCC_AHB4LPENR_GPIOGLPEN                RCC_AHB4LPENR_GPIOGLPEN_Msk

+#define RCC_AHB4LPENR_GPIOHLPEN_Pos            (7U)

+#define RCC_AHB4LPENR_GPIOHLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */

+#define RCC_AHB4LPENR_GPIOHLPEN                RCC_AHB4LPENR_GPIOHLPEN_Msk

+#define RCC_AHB4LPENR_GPIOILPEN_Pos            (8U)

+#define RCC_AHB4LPENR_GPIOILPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */

+#define RCC_AHB4LPENR_GPIOILPEN                RCC_AHB4LPENR_GPIOILPEN_Msk

+#define RCC_AHB4LPENR_GPIOJLPEN_Pos            (9U)

+#define RCC_AHB4LPENR_GPIOJLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */

+#define RCC_AHB4LPENR_GPIOJLPEN                RCC_AHB4LPENR_GPIOJLPEN_Msk

+#define RCC_AHB4LPENR_GPIOKLPEN_Pos            (10U)

+#define RCC_AHB4LPENR_GPIOKLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */

+#define RCC_AHB4LPENR_GPIOKLPEN                RCC_AHB4LPENR_GPIOKLPEN_Msk

+#define RCC_AHB4LPENR_CRCLPEN_Pos              (19U)

+#define RCC_AHB4LPENR_CRCLPEN_Msk              (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */

+#define RCC_AHB4LPENR_CRCLPEN                  RCC_AHB4LPENR_CRCLPEN_Msk

+#define RCC_AHB4LPENR_BDMALPEN_Pos             (21U)

+#define RCC_AHB4LPENR_BDMALPEN_Msk             (0x1UL << RCC_AHB4LPENR_BDMALPEN_Pos) /*!< 0x00200000 */

+#define RCC_AHB4LPENR_BDMALPEN                 RCC_AHB4LPENR_BDMALPEN_Msk

+#define RCC_AHB4LPENR_ADC3LPEN_Pos             (24U)

+#define RCC_AHB4LPENR_ADC3LPEN_Msk             (0x1UL << RCC_AHB4LPENR_ADC3LPEN_Pos) /*!< 0x01000000 */

+#define RCC_AHB4LPENR_ADC3LPEN                 RCC_AHB4LPENR_ADC3LPEN_Msk

+#define RCC_AHB4LPENR_BKPRAMLPEN_Pos           (28U)

+#define RCC_AHB4LPENR_BKPRAMLPEN_Msk           (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */

+#define RCC_AHB4LPENR_BKPRAMLPEN               RCC_AHB4LPENR_BKPRAMLPEN_Msk

+#define RCC_AHB4LPENR_SRAM4LPEN_Pos            (29U)

+#define RCC_AHB4LPENR_SRAM4LPEN_Msk            (0x1UL << RCC_AHB4LPENR_SRAM4LPEN_Pos) /*!< 0x20000000 */

+#define RCC_AHB4LPENR_SRAM4LPEN                RCC_AHB4LPENR_SRAM4LPEN_Msk

+

+/* Legacy define */

+#define RCC_AHB4LPENR_D3SRAM1LPEN_Pos          RCC_AHB4LPENR_SRAM4LPEN_Pos

+#define RCC_AHB4LPENR_D3SRAM1LPEN_Msk          RCC_AHB4LPENR_SRAM4LPEN_Msk

+#define RCC_AHB4LPENR_D3SRAM1LPEN              RCC_AHB4LPENR_SRAM4LPEN

+/********************  Bit definition for RCC_APB3LPENR register  ******************/

+#define RCC_APB3LPENR_LTDCLPEN_Pos             (3U)

+#define RCC_APB3LPENR_LTDCLPEN_Msk             (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB3LPENR_LTDCLPEN                 RCC_APB3LPENR_LTDCLPEN_Msk

+#define RCC_APB3LPENR_WWDG1LPEN_Pos            (6U)

+#define RCC_APB3LPENR_WWDG1LPEN_Msk            (0x1UL << RCC_APB3LPENR_WWDG1LPEN_Pos) /*!< 0x00000040 */

+#define RCC_APB3LPENR_WWDG1LPEN                RCC_APB3LPENR_WWDG1LPEN_Msk

+

+/********************  Bit definition for RCC_APB1LLPENR register  ******************/

+

+#define RCC_APB1LLPENR_TIM2LPEN_Pos            (0U)

+#define RCC_APB1LLPENR_TIM2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */

+#define RCC_APB1LLPENR_TIM2LPEN                RCC_APB1LLPENR_TIM2LPEN_Msk

+#define RCC_APB1LLPENR_TIM3LPEN_Pos            (1U)

+#define RCC_APB1LLPENR_TIM3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1LLPENR_TIM3LPEN                RCC_APB1LLPENR_TIM3LPEN_Msk

+#define RCC_APB1LLPENR_TIM4LPEN_Pos            (2U)

+#define RCC_APB1LLPENR_TIM4LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1LLPENR_TIM4LPEN                RCC_APB1LLPENR_TIM4LPEN_Msk

+#define RCC_APB1LLPENR_TIM5LPEN_Pos            (3U)

+#define RCC_APB1LLPENR_TIM5LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB1LLPENR_TIM5LPEN                RCC_APB1LLPENR_TIM5LPEN_Msk

+#define RCC_APB1LLPENR_TIM6LPEN_Pos            (4U)

+#define RCC_APB1LLPENR_TIM6LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1LLPENR_TIM6LPEN                RCC_APB1LLPENR_TIM6LPEN_Msk

+#define RCC_APB1LLPENR_TIM7LPEN_Pos            (5U)

+#define RCC_APB1LLPENR_TIM7LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1LLPENR_TIM7LPEN                RCC_APB1LLPENR_TIM7LPEN_Msk

+#define RCC_APB1LLPENR_TIM12LPEN_Pos           (6U)

+#define RCC_APB1LLPENR_TIM12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */

+#define RCC_APB1LLPENR_TIM12LPEN               RCC_APB1LLPENR_TIM12LPEN_Msk

+#define RCC_APB1LLPENR_TIM13LPEN_Pos           (7U)

+#define RCC_APB1LLPENR_TIM13LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB1LLPENR_TIM13LPEN               RCC_APB1LLPENR_TIM13LPEN_Msk

+#define RCC_APB1LLPENR_TIM14LPEN_Pos           (8U)

+#define RCC_APB1LLPENR_TIM14LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1LLPENR_TIM14LPEN               RCC_APB1LLPENR_TIM14LPEN_Msk

+#define RCC_APB1LLPENR_LPTIM1LPEN_Pos          (9U)

+#define RCC_APB1LLPENR_LPTIM1LPEN_Msk          (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */

+#define RCC_APB1LLPENR_LPTIM1LPEN              RCC_APB1LLPENR_LPTIM1LPEN_Msk

+

+

+#define RCC_APB1LLPENR_SPI2LPEN_Pos            (14U)

+#define RCC_APB1LLPENR_SPI2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */

+#define RCC_APB1LLPENR_SPI2LPEN                RCC_APB1LLPENR_SPI2LPEN_Msk

+#define RCC_APB1LLPENR_SPI3LPEN_Pos            (15U)

+#define RCC_APB1LLPENR_SPI3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */

+#define RCC_APB1LLPENR_SPI3LPEN                RCC_APB1LLPENR_SPI3LPEN_Msk

+#define RCC_APB1LLPENR_SPDIFRXLPEN_Pos         (16U)

+#define RCC_APB1LLPENR_SPDIFRXLPEN_Msk         (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB1LLPENR_SPDIFRXLPEN             RCC_APB1LLPENR_SPDIFRXLPEN_Msk

+#define RCC_APB1LLPENR_USART2LPEN_Pos          (17U)

+#define RCC_APB1LLPENR_USART2LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */

+#define RCC_APB1LLPENR_USART2LPEN              RCC_APB1LLPENR_USART2LPEN_Msk

+#define RCC_APB1LLPENR_USART3LPEN_Pos          (18U)

+#define RCC_APB1LLPENR_USART3LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */

+#define RCC_APB1LLPENR_USART3LPEN              RCC_APB1LLPENR_USART3LPEN_Msk

+#define RCC_APB1LLPENR_UART4LPEN_Pos           (19U)

+#define RCC_APB1LLPENR_UART4LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */

+#define RCC_APB1LLPENR_UART4LPEN               RCC_APB1LLPENR_UART4LPEN_Msk

+#define RCC_APB1LLPENR_UART5LPEN_Pos           (20U)

+#define RCC_APB1LLPENR_UART5LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */

+#define RCC_APB1LLPENR_UART5LPEN               RCC_APB1LLPENR_UART5LPEN_Msk

+#define RCC_APB1LLPENR_I2C1LPEN_Pos            (21U)

+#define RCC_APB1LLPENR_I2C1LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */

+#define RCC_APB1LLPENR_I2C1LPEN                RCC_APB1LLPENR_I2C1LPEN_Msk

+#define RCC_APB1LLPENR_I2C2LPEN_Pos            (22U)

+#define RCC_APB1LLPENR_I2C2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */

+#define RCC_APB1LLPENR_I2C2LPEN                RCC_APB1LLPENR_I2C2LPEN_Msk

+#define RCC_APB1LLPENR_I2C3LPEN_Pos            (23U)

+#define RCC_APB1LLPENR_I2C3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */

+#define RCC_APB1LLPENR_I2C3LPEN                RCC_APB1LLPENR_I2C3LPEN_Msk

+#define RCC_APB1LLPENR_CECLPEN_Pos             (27U)

+#define RCC_APB1LLPENR_CECLPEN_Msk             (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */

+#define RCC_APB1LLPENR_CECLPEN                 RCC_APB1LLPENR_CECLPEN_Msk

+#define RCC_APB1LLPENR_DAC12LPEN_Pos           (29U)

+#define RCC_APB1LLPENR_DAC12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */

+#define RCC_APB1LLPENR_DAC12LPEN               RCC_APB1LLPENR_DAC12LPEN_Msk

+#define RCC_APB1LLPENR_UART7LPEN_Pos           (30U)

+#define RCC_APB1LLPENR_UART7LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */

+#define RCC_APB1LLPENR_UART7LPEN               RCC_APB1LLPENR_UART7LPEN_Msk

+#define RCC_APB1LLPENR_UART8LPEN_Pos           (31U)

+#define RCC_APB1LLPENR_UART8LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */

+#define RCC_APB1LLPENR_UART8LPEN               RCC_APB1LLPENR_UART8LPEN_Msk

+

+/* Legacy define */

+#define RCC_APB1LLPENR_HDMICECEN_Pos           RCC_APB1LLPENR_CECLPEN_Pos

+#define RCC_APB1LLPENR_HDMICECEN_Msk           RCC_APB1LLPENR_CECLPEN_Msk

+#define RCC_APB1LLPENR_HDMICECEN               RCC_APB1LLPENR_CECLPEN

+/********************  Bit definition for RCC_APB1HLPENR register  ******************/

+#define RCC_APB1HLPENR_CRSLPEN_Pos             (1U)

+#define RCC_APB1HLPENR_CRSLPEN_Msk             (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1HLPENR_CRSLPEN                 RCC_APB1HLPENR_CRSLPEN_Msk

+#define RCC_APB1HLPENR_SWPMILPEN_Pos           (2U)

+#define RCC_APB1HLPENR_SWPMILPEN_Msk           (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1HLPENR_SWPMILPEN               RCC_APB1HLPENR_SWPMILPEN_Msk

+#define RCC_APB1HLPENR_OPAMPLPEN_Pos           (4U)

+#define RCC_APB1HLPENR_OPAMPLPEN_Msk           (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1HLPENR_OPAMPLPEN               RCC_APB1HLPENR_OPAMPLPEN_Msk

+#define RCC_APB1HLPENR_MDIOSLPEN_Pos           (5U)

+#define RCC_APB1HLPENR_MDIOSLPEN_Msk           (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1HLPENR_MDIOSLPEN               RCC_APB1HLPENR_MDIOSLPEN_Msk

+#define RCC_APB1HLPENR_FDCANLPEN_Pos           (8U)

+#define RCC_APB1HLPENR_FDCANLPEN_Msk           (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1HLPENR_FDCANLPEN               RCC_APB1HLPENR_FDCANLPEN_Msk

+

+/********************  Bit definition for RCC_APB2LPENR register  ******************/

+#define RCC_APB2LPENR_TIM1LPEN_Pos             (0U)

+#define RCC_APB2LPENR_TIM1LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */

+#define RCC_APB2LPENR_TIM1LPEN                 RCC_APB2LPENR_TIM1LPEN_Msk

+#define RCC_APB2LPENR_TIM8LPEN_Pos             (1U)

+#define RCC_APB2LPENR_TIM8LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB2LPENR_TIM8LPEN                 RCC_APB2LPENR_TIM8LPEN_Msk

+#define RCC_APB2LPENR_USART1LPEN_Pos           (4U)

+#define RCC_APB2LPENR_USART1LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB2LPENR_USART1LPEN               RCC_APB2LPENR_USART1LPEN_Msk

+#define RCC_APB2LPENR_USART6LPEN_Pos           (5U)

+#define RCC_APB2LPENR_USART6LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB2LPENR_USART6LPEN               RCC_APB2LPENR_USART6LPEN_Msk

+#define RCC_APB2LPENR_SPI1LPEN_Pos             (12U)

+#define RCC_APB2LPENR_SPI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */

+#define RCC_APB2LPENR_SPI1LPEN                 RCC_APB2LPENR_SPI1LPEN_Msk

+#define RCC_APB2LPENR_SPI4LPEN_Pos             (13U)

+#define RCC_APB2LPENR_SPI4LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */

+#define RCC_APB2LPENR_SPI4LPEN                 RCC_APB2LPENR_SPI4LPEN_Msk

+#define RCC_APB2LPENR_TIM15LPEN_Pos            (16U)

+#define RCC_APB2LPENR_TIM15LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB2LPENR_TIM15LPEN                RCC_APB2LPENR_TIM15LPEN_Msk

+#define RCC_APB2LPENR_TIM16LPEN_Pos            (17U)

+#define RCC_APB2LPENR_TIM16LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */

+#define RCC_APB2LPENR_TIM16LPEN                RCC_APB2LPENR_TIM16LPEN_Msk

+#define RCC_APB2LPENR_TIM17LPEN_Pos            (18U)

+#define RCC_APB2LPENR_TIM17LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */

+#define RCC_APB2LPENR_TIM17LPEN                RCC_APB2LPENR_TIM17LPEN_Msk

+#define RCC_APB2LPENR_SPI5LPEN_Pos             (20U)

+#define RCC_APB2LPENR_SPI5LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */

+#define RCC_APB2LPENR_SPI5LPEN                 RCC_APB2LPENR_SPI5LPEN_Msk

+#define RCC_APB2LPENR_SAI1LPEN_Pos             (22U)

+#define RCC_APB2LPENR_SAI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */

+#define RCC_APB2LPENR_SAI1LPEN                 RCC_APB2LPENR_SAI1LPEN_Msk

+#define RCC_APB2LPENR_SAI2LPEN_Pos             (23U)

+#define RCC_APB2LPENR_SAI2LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */

+#define RCC_APB2LPENR_SAI2LPEN                 RCC_APB2LPENR_SAI2LPEN_Msk

+#define RCC_APB2LPENR_SAI3LPEN_Pos             (24U)

+#define RCC_APB2LPENR_SAI3LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI3LPEN_Pos) /*!< 0x01000000 */

+#define RCC_APB2LPENR_SAI3LPEN                 RCC_APB2LPENR_SAI3LPEN_Msk

+#define RCC_APB2LPENR_DFSDM1LPEN_Pos           (28U)

+#define RCC_APB2LPENR_DFSDM1LPEN_Msk           (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x10000000 */

+#define RCC_APB2LPENR_DFSDM1LPEN               RCC_APB2LPENR_DFSDM1LPEN_Msk

+#define RCC_APB2LPENR_HRTIMLPEN_Pos            (29U)

+#define RCC_APB2LPENR_HRTIMLPEN_Msk            (0x1UL << RCC_APB2LPENR_HRTIMLPEN_Pos) /*!< 0x20000000 */

+#define RCC_APB2LPENR_HRTIMLPEN                RCC_APB2LPENR_HRTIMLPEN_Msk

+

+/********************  Bit definition for RCC_APB4LPENR register  ******************/

+#define RCC_APB4LPENR_SYSCFGLPEN_Pos           (1U)

+#define RCC_APB4LPENR_SYSCFGLPEN_Msk           (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB4LPENR_SYSCFGLPEN               RCC_APB4LPENR_SYSCFGLPEN_Msk

+#define RCC_APB4LPENR_LPUART1LPEN_Pos          (3U)

+#define RCC_APB4LPENR_LPUART1LPEN_Msk          (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB4LPENR_LPUART1LPEN              RCC_APB4LPENR_LPUART1LPEN_Msk

+#define RCC_APB4LPENR_SPI6LPEN_Pos             (5U)

+#define RCC_APB4LPENR_SPI6LPEN_Msk             (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB4LPENR_SPI6LPEN                 RCC_APB4LPENR_SPI6LPEN_Msk

+#define RCC_APB4LPENR_I2C4LPEN_Pos             (7U)

+#define RCC_APB4LPENR_I2C4LPEN_Msk             (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB4LPENR_I2C4LPEN                 RCC_APB4LPENR_I2C4LPEN_Msk

+#define RCC_APB4LPENR_LPTIM2LPEN_Pos           (9U)

+#define RCC_APB4LPENR_LPTIM2LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */

+#define RCC_APB4LPENR_LPTIM2LPEN               RCC_APB4LPENR_LPTIM2LPEN_Msk

+#define RCC_APB4LPENR_LPTIM3LPEN_Pos           (10U)

+#define RCC_APB4LPENR_LPTIM3LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */

+#define RCC_APB4LPENR_LPTIM3LPEN               RCC_APB4LPENR_LPTIM3LPEN_Msk

+#define RCC_APB4LPENR_LPTIM4LPEN_Pos           (11U)

+#define RCC_APB4LPENR_LPTIM4LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) /*!< 0x00000800 */

+#define RCC_APB4LPENR_LPTIM4LPEN               RCC_APB4LPENR_LPTIM4LPEN_Msk

+#define RCC_APB4LPENR_LPTIM5LPEN_Pos           (12U)

+#define RCC_APB4LPENR_LPTIM5LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) /*!< 0x00001000 */

+#define RCC_APB4LPENR_LPTIM5LPEN               RCC_APB4LPENR_LPTIM5LPEN_Msk

+#define RCC_APB4LPENR_COMP12LPEN_Pos           (14U)

+#define RCC_APB4LPENR_COMP12LPEN_Msk           (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */

+#define RCC_APB4LPENR_COMP12LPEN               RCC_APB4LPENR_COMP12LPEN_Msk

+#define RCC_APB4LPENR_VREFLPEN_Pos             (15U)

+#define RCC_APB4LPENR_VREFLPEN_Msk             (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */

+#define RCC_APB4LPENR_VREFLPEN                 RCC_APB4LPENR_VREFLPEN_Msk

+#define RCC_APB4LPENR_RTCAPBLPEN_Pos           (16U)

+#define RCC_APB4LPENR_RTCAPBLPEN_Msk           (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB4LPENR_RTCAPBLPEN               RCC_APB4LPENR_RTCAPBLPEN_Msk

+#define RCC_APB4LPENR_SAI4LPEN_Pos             (21U)

+#define RCC_APB4LPENR_SAI4LPEN_Msk             (0x1UL << RCC_APB4LPENR_SAI4LPEN_Pos) /*!< 0x00200000 */

+#define RCC_APB4LPENR_SAI4LPEN                 RCC_APB4LPENR_SAI4LPEN_Msk

+

+

+/********************  Bit definition for RCC_RSR register  *******************/

+#define RCC_RSR_RMVF_Pos                       (16U)

+#define RCC_RSR_RMVF_Msk                       (0x1UL << RCC_RSR_RMVF_Pos)     /*!< 0x00010000 */

+#define RCC_RSR_RMVF                           RCC_RSR_RMVF_Msk

+#define RCC_RSR_CPURSTF_Pos                    (17U)

+#define RCC_RSR_CPURSTF_Msk                    (0x1UL << RCC_RSR_CPURSTF_Pos)  /*!< 0x00020000 */

+#define RCC_RSR_CPURSTF                        RCC_RSR_CPURSTF_Msk

+#define RCC_RSR_D1RSTF_Pos                     (19U)

+#define RCC_RSR_D1RSTF_Msk                     (0x1UL << RCC_RSR_D1RSTF_Pos)   /*!< 0x00080000 */

+#define RCC_RSR_D1RSTF                         RCC_RSR_D1RSTF_Msk

+#define RCC_RSR_D2RSTF_Pos                     (20U)

+#define RCC_RSR_D2RSTF_Msk                     (0x1UL << RCC_RSR_D2RSTF_Pos)   /*!< 0x00100000 */

+#define RCC_RSR_D2RSTF                         RCC_RSR_D2RSTF_Msk

+#define RCC_RSR_BORRSTF_Pos                    (21U)

+#define RCC_RSR_BORRSTF_Msk                    (0x1UL << RCC_RSR_BORRSTF_Pos)  /*!< 0x00200000 */

+#define RCC_RSR_BORRSTF                        RCC_RSR_BORRSTF_Msk

+#define RCC_RSR_PINRSTF_Pos                    (22U)

+#define RCC_RSR_PINRSTF_Msk                    (0x1UL << RCC_RSR_PINRSTF_Pos)  /*!< 0x00400000 */

+#define RCC_RSR_PINRSTF                        RCC_RSR_PINRSTF_Msk

+#define RCC_RSR_PORRSTF_Pos                    (23U)

+#define RCC_RSR_PORRSTF_Msk                    (0x1UL << RCC_RSR_PORRSTF_Pos)  /*!< 0x00800000 */

+#define RCC_RSR_PORRSTF                        RCC_RSR_PORRSTF_Msk

+#define RCC_RSR_SFTRSTF_Pos                    (24U)

+#define RCC_RSR_SFTRSTF_Msk                    (0x1UL << RCC_RSR_SFTRSTF_Pos)  /*!< 0x01000000 */

+#define RCC_RSR_SFTRSTF                        RCC_RSR_SFTRSTF_Msk

+#define RCC_RSR_IWDG1RSTF_Pos                  (26U)

+#define RCC_RSR_IWDG1RSTF_Msk                  (0x1UL << RCC_RSR_IWDG1RSTF_Pos) /*!< 0x04000000 */

+#define RCC_RSR_IWDG1RSTF                      RCC_RSR_IWDG1RSTF_Msk

+#define RCC_RSR_WWDG1RSTF_Pos                  (28U)

+#define RCC_RSR_WWDG1RSTF_Msk                  (0x1UL << RCC_RSR_WWDG1RSTF_Pos) /*!< 0x10000000 */

+#define RCC_RSR_WWDG1RSTF                      RCC_RSR_WWDG1RSTF_Msk

+

+#define RCC_RSR_LPWRRSTF_Pos                   (30U)

+#define RCC_RSR_LPWRRSTF_Msk                   (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */

+#define RCC_RSR_LPWRRSTF                       RCC_RSR_LPWRRSTF_Msk

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    RNG                                     */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for RNG_CR register  *******************/

+#define RNG_CR_RNGEN_Pos    (2U)

+#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */

+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk

+#define RNG_CR_IE_Pos       (3U)

+#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */

+#define RNG_CR_IE           RNG_CR_IE_Msk

+#define RNG_CR_CED_Pos      (5U)

+#define RNG_CR_CED_Msk      (0x1UL << RNG_CR_CED_Pos)                          /*!< 0x00000020 */

+#define RNG_CR_CED          RNG_CR_CED_Msk

+

+/********************  Bits definition for RNG_SR register  *******************/

+#define RNG_SR_DRDY_Pos     (0U)

+#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */

+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk

+#define RNG_SR_CECS_Pos     (1U)

+#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */

+#define RNG_SR_CECS         RNG_SR_CECS_Msk

+#define RNG_SR_SECS_Pos     (2U)

+#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */

+#define RNG_SR_SECS         RNG_SR_SECS_Msk

+#define RNG_SR_CEIS_Pos     (5U)

+#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */

+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk

+#define RNG_SR_SEIS_Pos     (6U)

+#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */

+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                           Real-Time Clock (RTC)                            */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for RTC_TR register  *******************/

+#define RTC_TR_PM_Pos                  (22U)

+#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */

+#define RTC_TR_PM                      RTC_TR_PM_Msk

+#define RTC_TR_HT_Pos                  (20U)

+#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */

+#define RTC_TR_HT                      RTC_TR_HT_Msk

+#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */

+#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */

+#define RTC_TR_HU_Pos                  (16U)

+#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */

+#define RTC_TR_HU                      RTC_TR_HU_Msk

+#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */

+#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */

+#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */

+#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */

+#define RTC_TR_MNT_Pos                 (12U)

+#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */

+#define RTC_TR_MNT                     RTC_TR_MNT_Msk

+#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */

+#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */

+#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */

+#define RTC_TR_MNU_Pos                 (8U)

+#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */

+#define RTC_TR_MNU                     RTC_TR_MNU_Msk

+#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */

+#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */

+#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */

+#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */

+#define RTC_TR_ST_Pos                  (4U)

+#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */

+#define RTC_TR_ST                      RTC_TR_ST_Msk

+#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */

+#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */

+#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */

+#define RTC_TR_SU_Pos                  (0U)

+#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */

+#define RTC_TR_SU                      RTC_TR_SU_Msk

+#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */

+#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */

+#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */

+#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_DR register  *******************/

+#define RTC_DR_YT_Pos                  (20U)

+#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */

+#define RTC_DR_YT                      RTC_DR_YT_Msk

+#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */

+#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */

+#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */

+#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */

+#define RTC_DR_YU_Pos                  (16U)

+#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */

+#define RTC_DR_YU                      RTC_DR_YU_Msk

+#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */

+#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */

+#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */

+#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */

+#define RTC_DR_WDU_Pos                 (13U)

+#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */

+#define RTC_DR_WDU                     RTC_DR_WDU_Msk

+#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */

+#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */

+#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */

+#define RTC_DR_MT_Pos                  (12U)

+#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */

+#define RTC_DR_MT                      RTC_DR_MT_Msk

+#define RTC_DR_MU_Pos                  (8U)

+#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */

+#define RTC_DR_MU                      RTC_DR_MU_Msk

+#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */

+#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */

+#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */

+#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */

+#define RTC_DR_DT_Pos                  (4U)

+#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */

+#define RTC_DR_DT                      RTC_DR_DT_Msk

+#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */

+#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */

+#define RTC_DR_DU_Pos                  (0U)

+#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */

+#define RTC_DR_DU                      RTC_DR_DU_Msk

+#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */

+#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */

+#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */

+#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_CR register  *******************/

+#define RTC_CR_ITSE_Pos                (24U)

+#define RTC_CR_ITSE_Msk                (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */

+#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk

+#define RTC_CR_COE_Pos                 (23U)

+#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */

+#define RTC_CR_COE                     RTC_CR_COE_Msk

+#define RTC_CR_OSEL_Pos                (21U)

+#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */

+#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk

+#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */

+#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */

+#define RTC_CR_POL_Pos                 (20U)

+#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */

+#define RTC_CR_POL                     RTC_CR_POL_Msk

+#define RTC_CR_COSEL_Pos               (19U)

+#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */

+#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk

+#define RTC_CR_BKP_Pos                 (18U)

+#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */

+#define RTC_CR_BKP                     RTC_CR_BKP_Msk

+#define RTC_CR_SUB1H_Pos               (17U)

+#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */

+#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk

+#define RTC_CR_ADD1H_Pos               (16U)

+#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */

+#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk

+#define RTC_CR_TSIE_Pos                (15U)

+#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */

+#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk

+#define RTC_CR_WUTIE_Pos               (14U)

+#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */

+#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk

+#define RTC_CR_ALRBIE_Pos              (13U)

+#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */

+#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk

+#define RTC_CR_ALRAIE_Pos              (12U)

+#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */

+#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk

+#define RTC_CR_TSE_Pos                 (11U)

+#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */

+#define RTC_CR_TSE                     RTC_CR_TSE_Msk

+#define RTC_CR_WUTE_Pos                (10U)

+#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */

+#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk

+#define RTC_CR_ALRBE_Pos               (9U)

+#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */

+#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk

+#define RTC_CR_ALRAE_Pos               (8U)

+#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */

+#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk

+#define RTC_CR_FMT_Pos                 (6U)

+#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */

+#define RTC_CR_FMT                     RTC_CR_FMT_Msk

+#define RTC_CR_BYPSHAD_Pos             (5U)

+#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */

+#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk

+#define RTC_CR_REFCKON_Pos             (4U)

+#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */

+#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk

+#define RTC_CR_TSEDGE_Pos              (3U)

+#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */

+#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk

+#define RTC_CR_WUCKSEL_Pos             (0U)

+#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */

+#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk

+#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */

+#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */

+#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */

+

+/********************  Bits definition for RTC_ISR register  ******************/

+#define RTC_ISR_ITSF_Pos               (17U)

+#define RTC_ISR_ITSF_Msk               (0x1UL << RTC_ISR_ITSF_Pos)             /*!< 0x00020000 */

+#define RTC_ISR_ITSF                   RTC_ISR_ITSF_Msk

+#define RTC_ISR_RECALPF_Pos            (16U)

+#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)          /*!< 0x00010000 */

+#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk

+#define RTC_ISR_TAMP3F_Pos             (15U)

+#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)           /*!< 0x00008000 */

+#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk

+#define RTC_ISR_TAMP2F_Pos             (14U)

+#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)           /*!< 0x00004000 */

+#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk

+#define RTC_ISR_TAMP1F_Pos             (13U)

+#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)           /*!< 0x00002000 */

+#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk

+#define RTC_ISR_TSOVF_Pos              (12U)

+#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)            /*!< 0x00001000 */

+#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk

+#define RTC_ISR_TSF_Pos                (11U)

+#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)              /*!< 0x00000800 */

+#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk

+#define RTC_ISR_WUTF_Pos               (10U)

+#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)             /*!< 0x00000400 */

+#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk

+#define RTC_ISR_ALRBF_Pos              (9U)

+#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)            /*!< 0x00000200 */

+#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk

+#define RTC_ISR_ALRAF_Pos              (8U)

+#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)            /*!< 0x00000100 */

+#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk

+#define RTC_ISR_INIT_Pos               (7U)

+#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)             /*!< 0x00000080 */

+#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk

+#define RTC_ISR_INITF_Pos              (6U)

+#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)            /*!< 0x00000040 */

+#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk

+#define RTC_ISR_RSF_Pos                (5U)

+#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)              /*!< 0x00000020 */

+#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk

+#define RTC_ISR_INITS_Pos              (4U)

+#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)            /*!< 0x00000010 */

+#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk

+#define RTC_ISR_SHPF_Pos               (3U)

+#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)             /*!< 0x00000008 */

+#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk

+#define RTC_ISR_WUTWF_Pos              (2U)

+#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)            /*!< 0x00000004 */

+#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk

+#define RTC_ISR_ALRBWF_Pos             (1U)

+#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)           /*!< 0x00000002 */

+#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk

+#define RTC_ISR_ALRAWF_Pos             (0U)

+#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)           /*!< 0x00000001 */

+#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk

+

+/********************  Bits definition for RTC_PRER register  *****************/

+#define RTC_PRER_PREDIV_A_Pos          (16U)

+#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */

+#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk

+#define RTC_PRER_PREDIV_S_Pos          (0U)

+#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */

+#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk

+

+/********************  Bits definition for RTC_WUTR register  *****************/

+#define RTC_WUTR_WUT_Pos               (0U)

+#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */

+#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk

+

+/********************  Bits definition for RTC_ALRMAR register  ***************/

+#define RTC_ALRMAR_MSK4_Pos            (31U)

+#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */

+#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk

+#define RTC_ALRMAR_WDSEL_Pos           (30U)

+#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */

+#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk

+#define RTC_ALRMAR_DT_Pos              (28U)

+#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */

+#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk

+#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */

+#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */

+#define RTC_ALRMAR_DU_Pos              (24U)

+#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */

+#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk

+#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */

+#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */

+#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */

+#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */

+#define RTC_ALRMAR_MSK3_Pos            (23U)

+#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */

+#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk

+#define RTC_ALRMAR_PM_Pos              (22U)

+#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */

+#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk

+#define RTC_ALRMAR_HT_Pos              (20U)

+#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */

+#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk

+#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */

+#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */

+#define RTC_ALRMAR_HU_Pos              (16U)

+#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */

+#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk

+#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */

+#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */

+#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */

+#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */

+#define RTC_ALRMAR_MSK2_Pos            (15U)

+#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */

+#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk

+#define RTC_ALRMAR_MNT_Pos             (12U)

+#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */

+#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk

+#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */

+#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */

+#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */

+#define RTC_ALRMAR_MNU_Pos             (8U)

+#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */

+#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk

+#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */

+#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */

+#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */

+#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */

+#define RTC_ALRMAR_MSK1_Pos            (7U)

+#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */

+#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk

+#define RTC_ALRMAR_ST_Pos              (4U)

+#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */

+#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk

+#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */

+#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */

+#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */

+#define RTC_ALRMAR_SU_Pos              (0U)

+#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */

+#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk

+#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */

+#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */

+#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */

+#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_ALRMBR register  ***************/

+#define RTC_ALRMBR_MSK4_Pos            (31U)

+#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */

+#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk

+#define RTC_ALRMBR_WDSEL_Pos           (30U)

+#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */

+#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk

+#define RTC_ALRMBR_DT_Pos              (28U)

+#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */

+#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk

+#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */

+#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */

+#define RTC_ALRMBR_DU_Pos              (24U)

+#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */

+#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk

+#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */

+#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */

+#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */

+#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */

+#define RTC_ALRMBR_MSK3_Pos            (23U)

+#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */

+#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk

+#define RTC_ALRMBR_PM_Pos              (22U)

+#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */

+#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk

+#define RTC_ALRMBR_HT_Pos              (20U)

+#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */

+#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk

+#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */

+#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */

+#define RTC_ALRMBR_HU_Pos              (16U)

+#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */

+#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk

+#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */

+#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */

+#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */

+#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */

+#define RTC_ALRMBR_MSK2_Pos            (15U)

+#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */

+#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk

+#define RTC_ALRMBR_MNT_Pos             (12U)

+#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */

+#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk

+#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */

+#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */

+#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */

+#define RTC_ALRMBR_MNU_Pos             (8U)

+#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */

+#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk

+#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */

+#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */

+#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */

+#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */

+#define RTC_ALRMBR_MSK1_Pos            (7U)

+#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */

+#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk

+#define RTC_ALRMBR_ST_Pos              (4U)

+#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */

+#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk

+#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */

+#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */

+#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */

+#define RTC_ALRMBR_SU_Pos              (0U)

+#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */

+#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk

+#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */

+#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */

+#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */

+#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_WPR register  ******************/

+#define RTC_WPR_KEY_Pos                (0U)

+#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */

+#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk

+

+/********************  Bits definition for RTC_SSR register  ******************/

+#define RTC_SSR_SS_Pos                 (0U)

+#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)            /*!< 0x0000FFFF */

+#define RTC_SSR_SS                     RTC_SSR_SS_Msk

+

+/********************  Bits definition for RTC_SHIFTR register  ***************/

+#define RTC_SHIFTR_SUBFS_Pos           (0U)

+#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */

+#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk

+#define RTC_SHIFTR_ADD1S_Pos           (31U)

+#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */

+#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk

+

+/********************  Bits definition for RTC_TSTR register  *****************/

+#define RTC_TSTR_PM_Pos                (22U)

+#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */

+#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk

+#define RTC_TSTR_HT_Pos                (20U)

+#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */

+#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk

+#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */

+#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */

+#define RTC_TSTR_HU_Pos                (16U)

+#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */

+#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk

+#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */

+#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */

+#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */

+#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */

+#define RTC_TSTR_MNT_Pos               (12U)

+#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */

+#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk

+#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */

+#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */

+#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */

+#define RTC_TSTR_MNU_Pos               (8U)

+#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */

+#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk

+#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */

+#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */

+#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */

+#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */

+#define RTC_TSTR_ST_Pos                (4U)

+#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */

+#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk

+#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */

+#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */

+#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */

+#define RTC_TSTR_SU_Pos                (0U)

+#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */

+#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk

+#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */

+#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */

+#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */

+#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_TSDR register  *****************/

+#define RTC_TSDR_WDU_Pos               (13U)

+#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */

+#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk

+#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */

+#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */

+#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */

+#define RTC_TSDR_MT_Pos                (12U)

+#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */

+#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk

+#define RTC_TSDR_MU_Pos                (8U)

+#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */

+#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk

+#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */

+#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */

+#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */

+#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */

+#define RTC_TSDR_DT_Pos                (4U)

+#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */

+#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk

+#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */

+#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */

+#define RTC_TSDR_DU_Pos                (0U)

+#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */

+#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk

+#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */

+#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */

+#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */

+#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_TSSSR register  ****************/

+#define RTC_TSSSR_SS_Pos               (0U)

+#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)          /*!< 0x0000FFFF */

+#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk

+

+/********************  Bits definition for RTC_CALR register  *****************/

+#define RTC_CALR_CALP_Pos              (15U)

+#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */

+#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk

+#define RTC_CALR_CALW8_Pos             (14U)

+#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */

+#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk

+#define RTC_CALR_CALW16_Pos            (13U)

+#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */

+#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk

+#define RTC_CALR_CALM_Pos              (0U)

+#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */

+#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk

+#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */

+#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */

+#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */

+#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */

+#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */

+#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */

+#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */

+#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */

+#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */

+

+/********************  Bits definition for RTC_TAMPCR register  ***************/

+#define RTC_TAMPCR_TAMP3MF_Pos         (24U)

+#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)       /*!< 0x01000000 */

+#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk

+#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)

+#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)  /*!< 0x00800000 */

+#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk

+#define RTC_TAMPCR_TAMP3IE_Pos         (22U)

+#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)       /*!< 0x00400000 */

+#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk

+#define RTC_TAMPCR_TAMP2MF_Pos         (21U)

+#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)       /*!< 0x00200000 */

+#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk

+#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)

+#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)  /*!< 0x00100000 */

+#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk

+#define RTC_TAMPCR_TAMP2IE_Pos         (19U)

+#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)       /*!< 0x00080000 */

+#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk

+#define RTC_TAMPCR_TAMP1MF_Pos         (18U)

+#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)       /*!< 0x00040000 */

+#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk

+#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)

+#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)  /*!< 0x00020000 */

+#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk

+#define RTC_TAMPCR_TAMP1IE_Pos         (16U)

+#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)       /*!< 0x00010000 */

+#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk

+#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)

+#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)     /*!< 0x00008000 */

+#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk

+#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)

+#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)      /*!< 0x00006000 */

+#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk

+#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */

+#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */

+#define RTC_TAMPCR_TAMPFLT_Pos         (11U)

+#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)       /*!< 0x00001800 */

+#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk

+#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */

+#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */

+#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)

+#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)      /*!< 0x00000700 */

+#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk

+#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */

+#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */

+#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */

+#define RTC_TAMPCR_TAMPTS_Pos          (7U)

+#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)        /*!< 0x00000080 */

+#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk

+#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)

+#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)      /*!< 0x00000040 */

+#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk

+#define RTC_TAMPCR_TAMP3E_Pos          (5U)

+#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)        /*!< 0x00000020 */

+#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk

+#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)

+#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)      /*!< 0x00000010 */

+#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk

+#define RTC_TAMPCR_TAMP2E_Pos          (3U)

+#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)        /*!< 0x00000008 */

+#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk

+#define RTC_TAMPCR_TAMPIE_Pos          (2U)

+#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)        /*!< 0x00000004 */

+#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk

+#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)

+#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)      /*!< 0x00000002 */

+#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk

+#define RTC_TAMPCR_TAMP1E_Pos          (0U)

+#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)        /*!< 0x00000001 */

+#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk

+

+/********************  Bits definition for RTC_ALRMASSR register  *************/

+#define RTC_ALRMASSR_MASKSS_Pos        (24U)

+#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x0F000000 */

+#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk

+#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */

+#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */

+#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */

+#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */

+#define RTC_ALRMASSR_SS_Pos            (0U)

+#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */

+#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk

+

+/********************  Bits definition for RTC_ALRMBSSR register  *************/

+#define RTC_ALRMBSSR_MASKSS_Pos        (24U)

+#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x0F000000 */

+#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk

+#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */

+#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */

+#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */

+#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */

+#define RTC_ALRMBSSR_SS_Pos            (0U)

+#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */

+#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk

+

+/********************  Bits definition for RTC_OR register  *******************/

+#define RTC_OR_OUT_RMP_Pos             (1U)

+#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)           /*!< 0x00000002 */

+#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk

+#define RTC_OR_ALARMOUTTYPE_Pos        (0U)

+#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)      /*!< 0x00000001 */

+#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk

+

+/********************  Bits definition for RTC_BKP0R register  ****************/

+#define RTC_BKP0R_Pos                  (0U)

+#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP0R                      RTC_BKP0R_Msk

+

+/********************  Bits definition for RTC_BKP1R register  ****************/

+#define RTC_BKP1R_Pos                  (0U)

+#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP1R                      RTC_BKP1R_Msk

+

+/********************  Bits definition for RTC_BKP2R register  ****************/

+#define RTC_BKP2R_Pos                  (0U)

+#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP2R                      RTC_BKP2R_Msk

+

+/********************  Bits definition for RTC_BKP3R register  ****************/

+#define RTC_BKP3R_Pos                  (0U)

+#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP3R                      RTC_BKP3R_Msk

+

+/********************  Bits definition for RTC_BKP4R register  ****************/

+#define RTC_BKP4R_Pos                  (0U)

+#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP4R                      RTC_BKP4R_Msk

+

+/********************  Bits definition for RTC_BKP5R register  ****************/

+#define RTC_BKP5R_Pos                  (0U)

+#define RTC_BKP5R_Msk                  (0xFFFFFFFFUL << RTC_BKP5R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP5R                      RTC_BKP5R_Msk

+

+/********************  Bits definition for RTC_BKP6R register  ****************/

+#define RTC_BKP6R_Pos                  (0U)

+#define RTC_BKP6R_Msk                  (0xFFFFFFFFUL << RTC_BKP6R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP6R                      RTC_BKP6R_Msk

+

+/********************  Bits definition for RTC_BKP7R register  ****************/

+#define RTC_BKP7R_Pos                  (0U)

+#define RTC_BKP7R_Msk                  (0xFFFFFFFFUL << RTC_BKP7R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP7R                      RTC_BKP7R_Msk

+

+/********************  Bits definition for RTC_BKP8R register  ****************/

+#define RTC_BKP8R_Pos                  (0U)

+#define RTC_BKP8R_Msk                  (0xFFFFFFFFUL << RTC_BKP8R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP8R                      RTC_BKP8R_Msk

+

+/********************  Bits definition for RTC_BKP9R register  ****************/

+#define RTC_BKP9R_Pos                  (0U)

+#define RTC_BKP9R_Msk                  (0xFFFFFFFFUL << RTC_BKP9R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP9R                      RTC_BKP9R_Msk

+

+/********************  Bits definition for RTC_BKP10R register  ***************/

+#define RTC_BKP10R_Pos                 (0U)

+#define RTC_BKP10R_Msk                 (0xFFFFFFFFUL << RTC_BKP10R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP10R                     RTC_BKP10R_Msk

+

+/********************  Bits definition for RTC_BKP11R register  ***************/

+#define RTC_BKP11R_Pos                 (0U)

+#define RTC_BKP11R_Msk                 (0xFFFFFFFFUL << RTC_BKP11R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP11R                     RTC_BKP11R_Msk

+

+/********************  Bits definition for RTC_BKP12R register  ***************/

+#define RTC_BKP12R_Pos                 (0U)

+#define RTC_BKP12R_Msk                 (0xFFFFFFFFUL << RTC_BKP12R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP12R                     RTC_BKP12R_Msk

+

+/********************  Bits definition for RTC_BKP13R register  ***************/

+#define RTC_BKP13R_Pos                 (0U)

+#define RTC_BKP13R_Msk                 (0xFFFFFFFFUL << RTC_BKP13R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP13R                     RTC_BKP13R_Msk

+

+/********************  Bits definition for RTC_BKP14R register  ***************/

+#define RTC_BKP14R_Pos                 (0U)

+#define RTC_BKP14R_Msk                 (0xFFFFFFFFUL << RTC_BKP14R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP14R                     RTC_BKP14R_Msk

+

+/********************  Bits definition for RTC_BKP15R register  ***************/

+#define RTC_BKP15R_Pos                 (0U)

+#define RTC_BKP15R_Msk                 (0xFFFFFFFFUL << RTC_BKP15R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP15R                     RTC_BKP15R_Msk

+

+/********************  Bits definition for RTC_BKP16R register  ***************/

+#define RTC_BKP16R_Pos                 (0U)

+#define RTC_BKP16R_Msk                 (0xFFFFFFFFUL << RTC_BKP16R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP16R                     RTC_BKP16R_Msk

+

+/********************  Bits definition for RTC_BKP17R register  ***************/

+#define RTC_BKP17R_Pos                 (0U)

+#define RTC_BKP17R_Msk                 (0xFFFFFFFFUL << RTC_BKP17R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP17R                     RTC_BKP17R_Msk

+

+/********************  Bits definition for RTC_BKP18R register  ***************/

+#define RTC_BKP18R_Pos                 (0U)

+#define RTC_BKP18R_Msk                 (0xFFFFFFFFUL << RTC_BKP18R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP18R                     RTC_BKP18R_Msk

+

+/********************  Bits definition for RTC_BKP19R register  ***************/

+#define RTC_BKP19R_Pos                 (0U)

+#define RTC_BKP19R_Msk                 (0xFFFFFFFFUL << RTC_BKP19R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP19R                     RTC_BKP19R_Msk

+

+/********************  Bits definition for RTC_BKP20R register  ***************/

+#define RTC_BKP20R_Pos                 (0U)

+#define RTC_BKP20R_Msk                 (0xFFFFFFFFUL << RTC_BKP20R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP20R                     RTC_BKP20R_Msk

+

+/********************  Bits definition for RTC_BKP21R register  ***************/

+#define RTC_BKP21R_Pos                 (0U)

+#define RTC_BKP21R_Msk                 (0xFFFFFFFFUL << RTC_BKP21R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP21R                     RTC_BKP21R_Msk

+

+/********************  Bits definition for RTC_BKP22R register  ***************/

+#define RTC_BKP22R_Pos                 (0U)

+#define RTC_BKP22R_Msk                 (0xFFFFFFFFUL << RTC_BKP22R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP22R                     RTC_BKP22R_Msk

+

+/********************  Bits definition for RTC_BKP23R register  ***************/

+#define RTC_BKP23R_Pos                 (0U)

+#define RTC_BKP23R_Msk                 (0xFFFFFFFFUL << RTC_BKP23R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP23R                     RTC_BKP23R_Msk

+

+/********************  Bits definition for RTC_BKP24R register  ***************/

+#define RTC_BKP24R_Pos                 (0U)

+#define RTC_BKP24R_Msk                 (0xFFFFFFFFUL << RTC_BKP24R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP24R                     RTC_BKP24R_Msk

+

+/********************  Bits definition for RTC_BKP25R register  ***************/

+#define RTC_BKP25R_Pos                 (0U)

+#define RTC_BKP25R_Msk                 (0xFFFFFFFFUL << RTC_BKP25R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP25R                     RTC_BKP25R_Msk

+

+/********************  Bits definition for RTC_BKP26R register  ***************/

+#define RTC_BKP26R_Pos                 (0U)

+#define RTC_BKP26R_Msk                 (0xFFFFFFFFUL << RTC_BKP26R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP26R                     RTC_BKP26R_Msk

+

+/********************  Bits definition for RTC_BKP27R register  ***************/

+#define RTC_BKP27R_Pos                 (0U)

+#define RTC_BKP27R_Msk                 (0xFFFFFFFFUL << RTC_BKP27R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP27R                     RTC_BKP27R_Msk

+

+/********************  Bits definition for RTC_BKP28R register  ***************/

+#define RTC_BKP28R_Pos                 (0U)

+#define RTC_BKP28R_Msk                 (0xFFFFFFFFUL << RTC_BKP28R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP28R                     RTC_BKP28R_Msk

+

+/********************  Bits definition for RTC_BKP29R register  ***************/

+#define RTC_BKP29R_Pos                 (0U)

+#define RTC_BKP29R_Msk                 (0xFFFFFFFFUL << RTC_BKP29R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP29R                     RTC_BKP29R_Msk

+

+/********************  Bits definition for RTC_BKP30R register  ***************/

+#define RTC_BKP30R_Pos                 (0U)

+#define RTC_BKP30R_Msk                 (0xFFFFFFFFUL << RTC_BKP30R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP30R                     RTC_BKP30R_Msk

+

+/********************  Bits definition for RTC_BKP31R register  ***************/

+#define RTC_BKP31R_Pos                 (0U)

+#define RTC_BKP31R_Msk                 (0xFFFFFFFFUL << RTC_BKP31R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP31R                     RTC_BKP31R_Msk

+

+/******************** Number of backup registers ******************************/

+#define RTC_BKP_NUMBER_Pos             (5U)

+#define RTC_BKP_NUMBER_Msk             (0x1UL << RTC_BKP_NUMBER_Pos)           /*!< 0x00000020 */

+#define RTC_BKP_NUMBER                 RTC_BKP_NUMBER_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                              SPDIF-RX Interface                            */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for SPDIF_CR register  ******************/

+#define SPDIFRX_CR_SPDIFEN_Pos      (0U)

+#define SPDIFRX_CR_SPDIFEN_Msk      (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)          /*!< 0x00000003 */

+#define SPDIFRX_CR_SPDIFEN          SPDIFRX_CR_SPDIFEN_Msk                     /*!<Peripheral Block Enable                      */

+#define SPDIFRX_CR_RXDMAEN_Pos      (2U)

+#define SPDIFRX_CR_RXDMAEN_Msk      (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)          /*!< 0x00000004 */

+#define SPDIFRX_CR_RXDMAEN          SPDIFRX_CR_RXDMAEN_Msk                     /*!<Receiver DMA Enable for data flow            */

+#define SPDIFRX_CR_RXSTEO_Pos       (3U)

+#define SPDIFRX_CR_RXSTEO_Msk       (0x1UL << SPDIFRX_CR_RXSTEO_Pos)           /*!< 0x00000008 */

+#define SPDIFRX_CR_RXSTEO           SPDIFRX_CR_RXSTEO_Msk                      /*!<Stereo Mode                                  */

+#define SPDIFRX_CR_DRFMT_Pos        (4U)

+#define SPDIFRX_CR_DRFMT_Msk        (0x3UL << SPDIFRX_CR_DRFMT_Pos)            /*!< 0x00000030 */

+#define SPDIFRX_CR_DRFMT            SPDIFRX_CR_DRFMT_Msk                       /*!<RX Data format                               */

+#define SPDIFRX_CR_PMSK_Pos         (6U)

+#define SPDIFRX_CR_PMSK_Msk         (0x1UL << SPDIFRX_CR_PMSK_Pos)             /*!< 0x00000040 */

+#define SPDIFRX_CR_PMSK             SPDIFRX_CR_PMSK_Msk                        /*!<Mask Parity error bit                        */

+#define SPDIFRX_CR_VMSK_Pos         (7U)

+#define SPDIFRX_CR_VMSK_Msk         (0x1UL << SPDIFRX_CR_VMSK_Pos)             /*!< 0x00000080 */

+#define SPDIFRX_CR_VMSK             SPDIFRX_CR_VMSK_Msk                        /*!<Mask of Validity bit                         */

+#define SPDIFRX_CR_CUMSK_Pos        (8U)

+#define SPDIFRX_CR_CUMSK_Msk        (0x1UL << SPDIFRX_CR_CUMSK_Pos)            /*!< 0x00000100 */

+#define SPDIFRX_CR_CUMSK            SPDIFRX_CR_CUMSK_Msk                       /*!<Mask of channel status and user bits         */

+#define SPDIFRX_CR_PTMSK_Pos        (9U)

+#define SPDIFRX_CR_PTMSK_Msk        (0x1UL << SPDIFRX_CR_PTMSK_Pos)            /*!< 0x00000200 */

+#define SPDIFRX_CR_PTMSK            SPDIFRX_CR_PTMSK_Msk                       /*!<Mask of Preamble Type bits                   */

+#define SPDIFRX_CR_CBDMAEN_Pos      (10U)

+#define SPDIFRX_CR_CBDMAEN_Msk      (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)          /*!< 0x00000400 */

+#define SPDIFRX_CR_CBDMAEN          SPDIFRX_CR_CBDMAEN_Msk                     /*!<Control Buffer DMA ENable for control flow   */

+#define SPDIFRX_CR_CHSEL_Pos        (11U)

+#define SPDIFRX_CR_CHSEL_Msk        (0x1UL << SPDIFRX_CR_CHSEL_Pos)            /*!< 0x00000800 */

+#define SPDIFRX_CR_CHSEL            SPDIFRX_CR_CHSEL_Msk                       /*!<Channel Selection                            */

+#define SPDIFRX_CR_NBTR_Pos         (12U)

+#define SPDIFRX_CR_NBTR_Msk         (0x3UL << SPDIFRX_CR_NBTR_Pos)             /*!< 0x00003000 */

+#define SPDIFRX_CR_NBTR             SPDIFRX_CR_NBTR_Msk                        /*!<Maximum allowed re-tries during synchronization phase */

+#define SPDIFRX_CR_WFA_Pos          (14U)

+#define SPDIFRX_CR_WFA_Msk          (0x1UL << SPDIFRX_CR_WFA_Pos)              /*!< 0x00004000 */

+#define SPDIFRX_CR_WFA              SPDIFRX_CR_WFA_Msk                         /*!<Wait For Activity     */

+#define SPDIFRX_CR_INSEL_Pos        (16U)

+#define SPDIFRX_CR_INSEL_Msk        (0x7UL << SPDIFRX_CR_INSEL_Pos)            /*!< 0x00070000 */

+#define SPDIFRX_CR_INSEL            SPDIFRX_CR_INSEL_Msk                       /*!<SPDIF input selection */

+#define SPDIFRX_CR_CKSEN_Pos        (20U)

+#define SPDIFRX_CR_CKSEN_Msk        (0x1UL << SPDIFRX_CR_CKSEN_Pos)            /*!< 0x00100000 */

+#define SPDIFRX_CR_CKSEN            SPDIFRX_CR_CKSEN_Msk                       /*!<Symbol Clock Enable */

+#define SPDIFRX_CR_CKSBKPEN_Pos     (21U)

+#define SPDIFRX_CR_CKSBKPEN_Msk     (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)         /*!< 0x00200000 */

+#define SPDIFRX_CR_CKSBKPEN         SPDIFRX_CR_CKSBKPEN_Msk                    /*!<Backup Symbol Clock Enable */

+

+/*******************  Bit definition for SPDIFRX_IMR register  *******************/

+#define SPDIFRX_IMR_RXNEIE_Pos      (0U)

+#define SPDIFRX_IMR_RXNEIE_Msk      (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)          /*!< 0x00000001 */

+#define SPDIFRX_IMR_RXNEIE          SPDIFRX_IMR_RXNEIE_Msk                     /*!<RXNE interrupt enable                              */

+#define SPDIFRX_IMR_CSRNEIE_Pos     (1U)

+#define SPDIFRX_IMR_CSRNEIE_Msk     (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)         /*!< 0x00000002 */

+#define SPDIFRX_IMR_CSRNEIE         SPDIFRX_IMR_CSRNEIE_Msk                    /*!<Control Buffer Ready Interrupt Enable              */

+#define SPDIFRX_IMR_PERRIE_Pos      (2U)

+#define SPDIFRX_IMR_PERRIE_Msk      (0x1UL << SPDIFRX_IMR_PERRIE_Pos)          /*!< 0x00000004 */

+#define SPDIFRX_IMR_PERRIE          SPDIFRX_IMR_PERRIE_Msk                     /*!<Parity error interrupt enable                      */

+#define SPDIFRX_IMR_OVRIE_Pos       (3U)

+#define SPDIFRX_IMR_OVRIE_Msk       (0x1UL << SPDIFRX_IMR_OVRIE_Pos)           /*!< 0x00000008 */

+#define SPDIFRX_IMR_OVRIE           SPDIFRX_IMR_OVRIE_Msk                      /*!<Overrun error Interrupt Enable                     */

+#define SPDIFRX_IMR_SBLKIE_Pos      (4U)

+#define SPDIFRX_IMR_SBLKIE_Msk      (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)          /*!< 0x00000010 */

+#define SPDIFRX_IMR_SBLKIE          SPDIFRX_IMR_SBLKIE_Msk                     /*!<Synchronization Block Detected Interrupt Enable    */

+#define SPDIFRX_IMR_SYNCDIE_Pos     (5U)

+#define SPDIFRX_IMR_SYNCDIE_Msk     (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)         /*!< 0x00000020 */

+#define SPDIFRX_IMR_SYNCDIE         SPDIFRX_IMR_SYNCDIE_Msk                    /*!<Synchronization Done                               */

+#define SPDIFRX_IMR_IFEIE_Pos       (6U)

+#define SPDIFRX_IMR_IFEIE_Msk       (0x1UL << SPDIFRX_IMR_IFEIE_Pos)           /*!< 0x00000040 */

+#define SPDIFRX_IMR_IFEIE           SPDIFRX_IMR_IFEIE_Msk                      /*!<Serial Interface Error Interrupt Enable            */

+

+/*******************  Bit definition for SPDIFRX_SR register  *******************/

+#define SPDIFRX_SR_RXNE_Pos         (0U)

+#define SPDIFRX_SR_RXNE_Msk         (0x1UL << SPDIFRX_SR_RXNE_Pos)             /*!< 0x00000001 */

+#define SPDIFRX_SR_RXNE             SPDIFRX_SR_RXNE_Msk                        /*!<Read data register not empty                          */

+#define SPDIFRX_SR_CSRNE_Pos        (1U)

+#define SPDIFRX_SR_CSRNE_Msk        (0x1UL << SPDIFRX_SR_CSRNE_Pos)            /*!< 0x00000002 */

+#define SPDIFRX_SR_CSRNE            SPDIFRX_SR_CSRNE_Msk                       /*!<The Control Buffer register is not empty              */

+#define SPDIFRX_SR_PERR_Pos         (2U)

+#define SPDIFRX_SR_PERR_Msk         (0x1UL << SPDIFRX_SR_PERR_Pos)             /*!< 0x00000004 */

+#define SPDIFRX_SR_PERR             SPDIFRX_SR_PERR_Msk                        /*!<Parity error                                          */

+#define SPDIFRX_SR_OVR_Pos          (3U)

+#define SPDIFRX_SR_OVR_Msk          (0x1UL << SPDIFRX_SR_OVR_Pos)              /*!< 0x00000008 */

+#define SPDIFRX_SR_OVR              SPDIFRX_SR_OVR_Msk                         /*!<Overrun error                                         */

+#define SPDIFRX_SR_SBD_Pos          (4U)

+#define SPDIFRX_SR_SBD_Msk          (0x1UL << SPDIFRX_SR_SBD_Pos)              /*!< 0x00000010 */

+#define SPDIFRX_SR_SBD              SPDIFRX_SR_SBD_Msk                         /*!<Synchronization Block Detected                        */

+#define SPDIFRX_SR_SYNCD_Pos        (5U)

+#define SPDIFRX_SR_SYNCD_Msk        (0x1UL << SPDIFRX_SR_SYNCD_Pos)            /*!< 0x00000020 */

+#define SPDIFRX_SR_SYNCD            SPDIFRX_SR_SYNCD_Msk                       /*!<Synchronization Done                                  */

+#define SPDIFRX_SR_FERR_Pos         (6U)

+#define SPDIFRX_SR_FERR_Msk         (0x1UL << SPDIFRX_SR_FERR_Pos)             /*!< 0x00000040 */

+#define SPDIFRX_SR_FERR             SPDIFRX_SR_FERR_Msk                        /*!<Framing error                                         */

+#define SPDIFRX_SR_SERR_Pos         (7U)

+#define SPDIFRX_SR_SERR_Msk         (0x1UL << SPDIFRX_SR_SERR_Pos)             /*!< 0x00000080 */

+#define SPDIFRX_SR_SERR             SPDIFRX_SR_SERR_Msk                        /*!<Synchronization error                                 */

+#define SPDIFRX_SR_TERR_Pos         (8U)

+#define SPDIFRX_SR_TERR_Msk         (0x1UL << SPDIFRX_SR_TERR_Pos)             /*!< 0x00000100 */

+#define SPDIFRX_SR_TERR             SPDIFRX_SR_TERR_Msk                        /*!<Time-out error                                        */

+#define SPDIFRX_SR_WIDTH5_Pos       (16U)

+#define SPDIFRX_SR_WIDTH5_Msk       (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)        /*!< 0x7FFF0000 */

+#define SPDIFRX_SR_WIDTH5           SPDIFRX_SR_WIDTH5_Msk                      /*!<Duration of 5 symbols counted with spdif_clk          */

+

+/*******************  Bit definition for SPDIFRX_IFCR register  *******************/

+#define SPDIFRX_IFCR_PERRCF_Pos     (2U)

+#define SPDIFRX_IFCR_PERRCF_Msk     (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)         /*!< 0x00000004 */

+#define SPDIFRX_IFCR_PERRCF         SPDIFRX_IFCR_PERRCF_Msk                    /*!<Clears the Parity error flag                         */

+#define SPDIFRX_IFCR_OVRCF_Pos      (3U)

+#define SPDIFRX_IFCR_OVRCF_Msk      (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)          /*!< 0x00000008 */

+#define SPDIFRX_IFCR_OVRCF          SPDIFRX_IFCR_OVRCF_Msk                     /*!<Clears the Overrun error flag                        */

+#define SPDIFRX_IFCR_SBDCF_Pos      (4U)

+#define SPDIFRX_IFCR_SBDCF_Msk      (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)          /*!< 0x00000010 */

+#define SPDIFRX_IFCR_SBDCF          SPDIFRX_IFCR_SBDCF_Msk                     /*!<Clears the Synchronization Block Detected flag       */

+#define SPDIFRX_IFCR_SYNCDCF_Pos    (5U)

+#define SPDIFRX_IFCR_SYNCDCF_Msk    (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)        /*!< 0x00000020 */

+#define SPDIFRX_IFCR_SYNCDCF        SPDIFRX_IFCR_SYNCDCF_Msk                   /*!<Clears the Synchronization Done flag                 */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/

+#define SPDIFRX_DR0_DR_Pos          (0U)

+#define SPDIFRX_DR0_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)         /*!< 0x00FFFFFF */

+#define SPDIFRX_DR0_DR              SPDIFRX_DR0_DR_Msk                         /*!<Data value            */

+#define SPDIFRX_DR0_PE_Pos          (24U)

+#define SPDIFRX_DR0_PE_Msk          (0x1UL << SPDIFRX_DR0_PE_Pos)              /*!< 0x01000000 */

+#define SPDIFRX_DR0_PE              SPDIFRX_DR0_PE_Msk                         /*!<Parity Error bit      */

+#define SPDIFRX_DR0_V_Pos           (25U)

+#define SPDIFRX_DR0_V_Msk           (0x1UL << SPDIFRX_DR0_V_Pos)               /*!< 0x02000000 */

+#define SPDIFRX_DR0_V               SPDIFRX_DR0_V_Msk                          /*!<Validity bit          */

+#define SPDIFRX_DR0_U_Pos           (26U)

+#define SPDIFRX_DR0_U_Msk           (0x1UL << SPDIFRX_DR0_U_Pos)               /*!< 0x04000000 */

+#define SPDIFRX_DR0_U               SPDIFRX_DR0_U_Msk                          /*!<User bit              */

+#define SPDIFRX_DR0_C_Pos           (27U)

+#define SPDIFRX_DR0_C_Msk           (0x1UL << SPDIFRX_DR0_C_Pos)               /*!< 0x08000000 */

+#define SPDIFRX_DR0_C               SPDIFRX_DR0_C_Msk                          /*!<Channel Status bit    */

+#define SPDIFRX_DR0_PT_Pos          (28U)

+#define SPDIFRX_DR0_PT_Msk          (0x3UL << SPDIFRX_DR0_PT_Pos)              /*!< 0x30000000 */

+#define SPDIFRX_DR0_PT              SPDIFRX_DR0_PT_Msk                         /*!<Preamble Type         */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/

+#define SPDIFRX_DR1_DR_Pos          (8U)

+#define SPDIFRX_DR1_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)         /*!< 0xFFFFFF00 */

+#define SPDIFRX_DR1_DR              SPDIFRX_DR1_DR_Msk                         /*!<Data value            */

+#define SPDIFRX_DR1_PT_Pos          (4U)

+#define SPDIFRX_DR1_PT_Msk          (0x3UL << SPDIFRX_DR1_PT_Pos)              /*!< 0x00000030 */

+#define SPDIFRX_DR1_PT              SPDIFRX_DR1_PT_Msk                         /*!<Preamble Type         */

+#define SPDIFRX_DR1_C_Pos           (3U)

+#define SPDIFRX_DR1_C_Msk           (0x1UL << SPDIFRX_DR1_C_Pos)               /*!< 0x00000008 */

+#define SPDIFRX_DR1_C               SPDIFRX_DR1_C_Msk                          /*!<Channel Status bit    */

+#define SPDIFRX_DR1_U_Pos           (2U)

+#define SPDIFRX_DR1_U_Msk           (0x1UL << SPDIFRX_DR1_U_Pos)               /*!< 0x00000004 */

+#define SPDIFRX_DR1_U               SPDIFRX_DR1_U_Msk                          /*!<User bit              */

+#define SPDIFRX_DR1_V_Pos           (1U)

+#define SPDIFRX_DR1_V_Msk           (0x1UL << SPDIFRX_DR1_V_Pos)               /*!< 0x00000002 */

+#define SPDIFRX_DR1_V               SPDIFRX_DR1_V_Msk                          /*!<Validity bit          */

+#define SPDIFRX_DR1_PE_Pos          (0U)

+#define SPDIFRX_DR1_PE_Msk          (0x1UL << SPDIFRX_DR1_PE_Pos)              /*!< 0x00000001 */

+#define SPDIFRX_DR1_PE              SPDIFRX_DR1_PE_Msk                         /*!<Parity Error bit      */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/

+#define SPDIFRX_DR1_DRNL1_Pos       (16U)

+#define SPDIFRX_DR1_DRNL1_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)        /*!< 0xFFFF0000 */

+#define SPDIFRX_DR1_DRNL1           SPDIFRX_DR1_DRNL1_Msk                      /*!<Data value Channel B      */

+#define SPDIFRX_DR1_DRNL2_Pos       (0U)

+#define SPDIFRX_DR1_DRNL2_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)        /*!< 0x0000FFFF */

+#define SPDIFRX_DR1_DRNL2           SPDIFRX_DR1_DRNL2_Msk                      /*!<Data value Channel A      */

+

+/*******************  Bit definition for SPDIFRX_CSR register   *******************/

+#define SPDIFRX_CSR_USR_Pos         (0U)

+#define SPDIFRX_CSR_USR_Msk         (0xFFFFUL << SPDIFRX_CSR_USR_Pos)          /*!< 0x0000FFFF */

+#define SPDIFRX_CSR_USR             SPDIFRX_CSR_USR_Msk                        /*!<User data information           */

+#define SPDIFRX_CSR_CS_Pos          (16U)

+#define SPDIFRX_CSR_CS_Msk          (0xFFUL << SPDIFRX_CSR_CS_Pos)             /*!< 0x00FF0000 */

+#define SPDIFRX_CSR_CS              SPDIFRX_CSR_CS_Msk                         /*!<Channel A status information    */

+#define SPDIFRX_CSR_SOB_Pos         (24U)

+#define SPDIFRX_CSR_SOB_Msk         (0x1UL << SPDIFRX_CSR_SOB_Pos)             /*!< 0x01000000 */

+#define SPDIFRX_CSR_SOB             SPDIFRX_CSR_SOB_Msk                        /*!<Start Of Block                  */

+

+/*******************  Bit definition for SPDIFRX_DIR register    *******************/

+#define SPDIFRX_DIR_THI_Pos         (0U)

+#define SPDIFRX_DIR_THI_Msk         (0x1FFFUL << SPDIFRX_DIR_THI_Pos)          /*!< 0x00001FFF */

+#define SPDIFRX_DIR_THI             SPDIFRX_DIR_THI_Msk                        /*!<Threshold LOW      */

+#define SPDIFRX_DIR_TLO_Pos         (16U)

+#define SPDIFRX_DIR_TLO_Msk         (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)          /*!< 0x1FFF0000 */

+#define SPDIFRX_DIR_TLO             SPDIFRX_DIR_TLO_Msk                        /*!<Threshold HIGH     */

+

+/*******************  Bit definition for SPDIFRX_VERR register    *******************/

+#define SPDIFRX_VERR_MINREV_Pos     (0U)

+#define SPDIFRX_VERR_MINREV_Msk     (0xFUL << SPDIFRX_VERR_MINREV_Pos)         /*!< 0x0000000F */

+#define SPDIFRX_VERR_MINREV         SPDIFRX_VERR_MINREV_Msk                    /*!<SPDIFRX Minor revision     */

+#define SPDIFRX_VERR_MAJREV_Pos     (4U)

+#define SPDIFRX_VERR_MAJREV_Msk     (0xFUL << SPDIFRX_VERR_MAJREV_Pos)         /*!< 0x000000F0 */

+#define SPDIFRX_VERR_MAJREV         SPDIFRX_VERR_MAJREV_Msk                    /*!<SPDIFRX Major revision     */

+

+/*******************  Bit definition for SPDIFRX_IDR register    *******************/

+#define SPDIFRX_IDR_ID_Pos          (0U)

+#define SPDIFRX_IDR_ID_Msk          (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos)       /*!< 0xFFFFFFFF */

+#define SPDIFRX_IDR_ID              SPDIFRX_IDR_ID_Msk                         /*!<SPDIFRX identifier     */

+

+/*******************  Bit definition for SPDIFRX_SIDR register    *******************/

+#define SPDIFRX_SIDR_SID_Pos        (0U)

+#define SPDIFRX_SIDR_SID_Msk        (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos)     /*!< 0xFFFFFFFF */

+#define SPDIFRX_SIDR_SID            SPDIFRX_SIDR_SID_Msk                       /*!<Size of the memory region allocated to SPDIFRX registers */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          Serial Audio Interface                            */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  SAI VERSION  ********************************/

+#define SAI_VER_V2_X

+

+/********************  Bit definition for SAI_GCR register  *******************/

+#define SAI_GCR_SYNCIN_Pos         (0U)

+#define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000003 */

+#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */

+#define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */

+#define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */

+

+#define SAI_GCR_SYNCOUT_Pos        (4U)

+#define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000030 */

+#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */

+#define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */

+#define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */

+

+/*******************  Bit definition for SAI_xCR1 register  *******************/

+#define SAI_xCR1_MODE_Pos          (0U)

+#define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */

+#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */

+#define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */

+#define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */

+

+#define SAI_xCR1_PRTCFG_Pos        (2U)

+#define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */

+#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */

+#define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */

+#define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */

+

+#define SAI_xCR1_DS_Pos            (5U)

+#define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */

+#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */

+#define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */

+#define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */

+#define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */

+

+#define SAI_xCR1_LSBFIRST_Pos      (8U)

+#define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */

+#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */

+#define SAI_xCR1_CKSTR_Pos         (9U)

+#define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */

+#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */

+

+#define SAI_xCR1_SYNCEN_Pos        (10U)

+#define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */

+#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */

+#define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */

+#define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */

+

+#define SAI_xCR1_MONO_Pos          (12U)

+#define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */

+#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */

+#define SAI_xCR1_OUTDRIV_Pos       (13U)

+#define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */

+#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */

+#define SAI_xCR1_SAIEN_Pos         (16U)

+#define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */

+#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */

+#define SAI_xCR1_DMAEN_Pos         (17U)

+#define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */

+#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */

+#define SAI_xCR1_NODIV_Pos         (19U)

+#define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */

+#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */

+

+#define SAI_xCR1_MCKDIV_Pos        (20U)

+#define SAI_xCR1_MCKDIV_Msk        (0x3FUL << SAI_xCR1_MCKDIV_Pos)             /*!< 0x03F00000 */

+#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[5:0] (Master ClocK Divider)  */

+#define SAI_xCR1_MCKDIV_0          (0x01UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00100000 */

+#define SAI_xCR1_MCKDIV_1          (0x02UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00200000 */

+#define SAI_xCR1_MCKDIV_2          (0x04UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00400000 */

+#define SAI_xCR1_MCKDIV_3          (0x08UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00800000 */

+#define SAI_xCR1_MCKDIV_4          (0x10UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x01000000 */

+#define SAI_xCR1_MCKDIV_5          (0x20UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x02000000 */

+

+#define SAI_xCR1_MCKEN_Pos         (27U)

+#define SAI_xCR1_MCKEN_Msk         (0x1UL << SAI_xCR1_MCKEN_Pos)               /*!< 0x08000000 */

+#define SAI_xCR1_MCKEN             SAI_xCR1_MCKEN_Msk                          /*!<Master ClocK enable */

+

+#define SAI_xCR1_OSR_Pos           (26U)

+#define SAI_xCR1_OSR_Msk           (0x1UL << SAI_xCR1_OSR_Pos)                 /*!< 0x04000000 */

+#define SAI_xCR1_OSR               SAI_xCR1_OSR_Msk                            /*!<OverSampling Ratio for master clock  */

+

+/* Legacy define */

+#define  SAI_xCR1_NOMCK               SAI_xCR1_NODIV

+

+/*******************  Bit definition for SAI_xCR2 register  *******************/

+#define SAI_xCR2_FTH_Pos           (0U)

+#define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */

+#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */

+#define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */

+#define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */

+#define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */

+

+#define SAI_xCR2_FFLUSH_Pos        (3U)

+#define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */

+#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */

+#define SAI_xCR2_TRIS_Pos          (4U)

+#define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */

+#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */

+#define SAI_xCR2_MUTE_Pos          (5U)

+#define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */

+#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */

+#define SAI_xCR2_MUTEVAL_Pos       (6U)

+#define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */

+#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */

+

+#define SAI_xCR2_MUTECNT_Pos       (7U)

+#define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */

+#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */

+#define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */

+#define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */

+#define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */

+#define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */

+#define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */

+#define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */

+

+#define SAI_xCR2_CPL_Pos           (13U)

+#define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */

+#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */

+

+#define SAI_xCR2_COMP_Pos          (14U)

+#define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */

+#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */

+#define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */

+#define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */

+

+/******************  Bit definition for SAI_xFRCR register  *******************/

+#define SAI_xFRCR_FRL_Pos          (0U)

+#define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */

+#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](FRame Length)  */

+#define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */

+#define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */

+#define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */

+#define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */

+#define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */

+#define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */

+#define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */

+#define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */

+

+#define SAI_xFRCR_FSALL_Pos        (8U)

+#define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */

+#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FSALL[6:0] (Frame Synchronization Active Level Length)  */

+#define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */

+#define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */

+#define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */

+#define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */

+#define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */

+#define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */

+#define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */

+

+#define SAI_xFRCR_FSDEF_Pos        (16U)

+#define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */

+#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!<Frame Synchronization Definition  */

+#define SAI_xFRCR_FSPOL_Pos        (17U)

+#define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */

+#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */

+#define SAI_xFRCR_FSOFF_Pos        (18U)

+#define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */

+#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */

+

+/* Legacy define */

+#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL

+

+/******************  Bit definition for SAI_xSLOTR register  *******************/

+#define SAI_xSLOTR_FBOFF_Pos       (0U)

+#define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */

+#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FBOFF[4:0](First Bit Offset)  */

+#define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */

+#define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */

+#define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */

+#define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */

+#define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */

+

+#define SAI_xSLOTR_SLOTSZ_Pos      (6U)

+#define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */

+#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */

+#define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */

+#define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */

+

+#define SAI_xSLOTR_NBSLOT_Pos      (8U)

+#define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */

+#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */

+#define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */

+#define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */

+#define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */

+#define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */

+

+#define SAI_xSLOTR_SLOTEN_Pos      (16U)

+#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */

+#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */

+

+/*******************  Bit definition for SAI_xIMR register  *******************/

+#define SAI_xIMR_OVRUDRIE_Pos      (0U)

+#define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */

+#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */

+#define SAI_xIMR_MUTEDETIE_Pos     (1U)

+#define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */

+#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */

+#define SAI_xIMR_WCKCFGIE_Pos      (2U)

+#define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */

+#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */

+#define SAI_xIMR_FREQIE_Pos        (3U)

+#define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */

+#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */

+#define SAI_xIMR_CNRDYIE_Pos       (4U)

+#define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */

+#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */

+#define SAI_xIMR_AFSDETIE_Pos      (5U)

+#define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */

+#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */

+#define SAI_xIMR_LFSDETIE_Pos      (6U)

+#define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */

+#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */

+

+/********************  Bit definition for SAI_xSR register  *******************/

+#define SAI_xSR_OVRUDR_Pos         (0U)

+#define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */

+#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */

+#define SAI_xSR_MUTEDET_Pos        (1U)

+#define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */

+#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */

+#define SAI_xSR_WCKCFG_Pos         (2U)

+#define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */

+#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */

+#define SAI_xSR_FREQ_Pos           (3U)

+#define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */

+#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */

+#define SAI_xSR_CNRDY_Pos          (4U)

+#define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */

+#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */

+#define SAI_xSR_AFSDET_Pos         (5U)

+#define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */

+#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */

+#define SAI_xSR_LFSDET_Pos         (6U)

+#define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */

+#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */

+

+#define SAI_xSR_FLVL_Pos           (16U)

+#define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */

+#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */

+#define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */

+#define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */

+#define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */

+

+/******************  Bit definition for SAI_xCLRFR register  ******************/

+#define SAI_xCLRFR_COVRUDR_Pos     (0U)

+#define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */

+#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */

+#define SAI_xCLRFR_CMUTEDET_Pos    (1U)

+#define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */

+#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */

+#define SAI_xCLRFR_CWCKCFG_Pos     (2U)

+#define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */

+#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */

+#define SAI_xCLRFR_CFREQ_Pos       (3U)

+#define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */

+#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */

+#define SAI_xCLRFR_CCNRDY_Pos      (4U)

+#define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */

+#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */

+#define SAI_xCLRFR_CAFSDET_Pos     (5U)

+#define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */

+#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */

+#define SAI_xCLRFR_CLFSDET_Pos     (6U)

+#define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */

+#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */

+

+/******************  Bit definition for SAI_xDR register  *********************/

+#define SAI_xDR_DATA_Pos           (0U)

+#define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */

+#define SAI_xDR_DATA               SAI_xDR_DATA_Msk

+

+/*******************  Bit definition for SAI_PDMCR register  ******************/

+#define SAI_PDMCR_PDMEN_Pos        (0U)

+#define SAI_PDMCR_PDMEN_Msk        (0x1UL << SAI_PDMCR_PDMEN_Pos)              /*!< 0x00000001 */

+#define SAI_PDMCR_PDMEN            SAI_PDMCR_PDMEN_Msk                         /*!<PDM Enable                                          */

+

+#define SAI_PDMCR_MICNBR_Pos       (4U)

+#define SAI_PDMCR_MICNBR_Msk       (0x3UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000030 */

+#define SAI_PDMCR_MICNBR           SAI_PDMCR_MICNBR_Msk                        /*!<Number of microphones                               */

+#define SAI_PDMCR_MICNBR_0         (0x1UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000010 */

+#define SAI_PDMCR_MICNBR_1         (0x2UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000020 */

+

+#define SAI_PDMCR_CKEN1_Pos        (8U)

+#define SAI_PDMCR_CKEN1_Msk        (0x1UL << SAI_PDMCR_CKEN1_Pos)              /*!< 0x00000100 */

+#define SAI_PDMCR_CKEN1            SAI_PDMCR_CKEN1_Msk                         /*!<Clock enable of bitstream clock number 1            */

+#define SAI_PDMCR_CKEN2_Pos        (9U)

+#define SAI_PDMCR_CKEN2_Msk        (0x1UL << SAI_PDMCR_CKEN2_Pos)              /*!< 0x00000200 */

+#define SAI_PDMCR_CKEN2            SAI_PDMCR_CKEN2_Msk                         /*!<Clock enable of bitstream clock number 2            */

+#define SAI_PDMCR_CKEN3_Pos        (10U)

+#define SAI_PDMCR_CKEN3_Msk        (0x1UL << SAI_PDMCR_CKEN3_Pos)              /*!< 0x00000400 */

+#define SAI_PDMCR_CKEN3            SAI_PDMCR_CKEN3_Msk                         /*!<Clock enable of bitstream clock number 3            */

+#define SAI_PDMCR_CKEN4_Pos        (11U)

+#define SAI_PDMCR_CKEN4_Msk        (0x1UL << SAI_PDMCR_CKEN4_Pos)              /*!< 0x00000800 */

+#define SAI_PDMCR_CKEN4            SAI_PDMCR_CKEN4_Msk                         /*!<Clock enable of bitstream clock number 4            */

+

+/******************  Bit definition for SAI_PDMDLY register  ******************/

+#define SAI_PDMDLY_DLYM1L_Pos      (0U)

+#define SAI_PDMDLY_DLYM1L_Msk      (0x7UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000007 */

+#define SAI_PDMDLY_DLYM1L          SAI_PDMDLY_DLYM1L_Msk                       /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */

+#define SAI_PDMDLY_DLYM1L_0        (0x1UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000001 */

+#define SAI_PDMDLY_DLYM1L_1        (0x2UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000002 */

+#define SAI_PDMDLY_DLYM1L_2        (0x4UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000004 */

+

+#define SAI_PDMDLY_DLYM1R_Pos      (4U)

+#define SAI_PDMDLY_DLYM1R_Msk      (0x7UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000070 */

+#define SAI_PDMDLY_DLYM1R          SAI_PDMDLY_DLYM1R_Msk                       /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */

+#define SAI_PDMDLY_DLYM1R_0        (0x1UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000010 */

+#define SAI_PDMDLY_DLYM1R_1        (0x2UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000020 */

+#define SAI_PDMDLY_DLYM1R_2        (0x4UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000040 */

+

+#define SAI_PDMDLY_DLYM2L_Pos      (8U)

+#define SAI_PDMDLY_DLYM2L_Msk      (0x7UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000700 */

+#define SAI_PDMDLY_DLYM2L          SAI_PDMDLY_DLYM2L_Msk                       /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */

+#define SAI_PDMDLY_DLYM2L_0        (0x1UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000100 */

+#define SAI_PDMDLY_DLYM2L_1        (0x2UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000200 */

+#define SAI_PDMDLY_DLYM2L_2        (0x4UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000400 */

+

+#define SAI_PDMDLY_DLYM2R_Pos      (12U)

+#define SAI_PDMDLY_DLYM2R_Msk      (0x7UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00007000 */

+#define SAI_PDMDLY_DLYM2R          SAI_PDMDLY_DLYM2R_Msk                       /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/

+#define SAI_PDMDLY_DLYM2R_0        (0x1UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00001000 */

+#define SAI_PDMDLY_DLYM2R_1        (0x2UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00002000 */

+#define SAI_PDMDLY_DLYM2R_2        (0x4UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00004000 */

+

+#define SAI_PDMDLY_DLYM3L_Pos      (16U)

+#define SAI_PDMDLY_DLYM3L_Msk      (0x7UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00070000 */

+#define SAI_PDMDLY_DLYM3L          SAI_PDMDLY_DLYM3L_Msk                       /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/

+#define SAI_PDMDLY_DLYM3L_0        (0x1UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00010000 */

+#define SAI_PDMDLY_DLYM3L_1        (0x2UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00020000 */

+#define SAI_PDMDLY_DLYM3L_2        (0x4UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00040000 */

+

+#define SAI_PDMDLY_DLYM3R_Pos      (20U)

+#define SAI_PDMDLY_DLYM3R_Msk      (0x7UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00700000 */

+#define SAI_PDMDLY_DLYM3R          SAI_PDMDLY_DLYM3R_Msk                       /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/

+#define SAI_PDMDLY_DLYM3R_0        (0x1UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00100000 */

+#define SAI_PDMDLY_DLYM3R_1        (0x2UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00200000 */

+#define SAI_PDMDLY_DLYM3R_2        (0x4UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00400000 */

+

+#define SAI_PDMDLY_DLYM4L_Pos      (24U)

+#define SAI_PDMDLY_DLYM4L_Msk      (0x7UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x07000000 */

+#define SAI_PDMDLY_DLYM4L          SAI_PDMDLY_DLYM4L_Msk                       /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/

+#define SAI_PDMDLY_DLYM4L_0        (0x1UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x01000000 */

+#define SAI_PDMDLY_DLYM4L_1        (0x2UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x02000000 */

+#define SAI_PDMDLY_DLYM4L_2        (0x4UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x04000000 */

+

+#define SAI_PDMDLY_DLYM4R_Pos      (28U)

+#define SAI_PDMDLY_DLYM4R_Msk      (0x7UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x70000000 */

+#define SAI_PDMDLY_DLYM4R          SAI_PDMDLY_DLYM4R_Msk                       /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/

+#define SAI_PDMDLY_DLYM4R_0        (0x1UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x10000000 */

+#define SAI_PDMDLY_DLYM4R_1        (0x2UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x20000000 */

+#define SAI_PDMDLY_DLYM4R_2        (0x4UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x40000000 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           SDMMC Interface                                  */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for SDMMC_POWER register  ******************/

+#define SDMMC_POWER_PWRCTRL_Pos          (0U)

+#define SDMMC_POWER_PWRCTRL_Msk          (0x3UL << SDMMC_POWER_PWRCTRL_Pos)    /*!< 0x00000003 */

+#define SDMMC_POWER_PWRCTRL              SDMMC_POWER_PWRCTRL_Msk               /*!<PWRCTRL[1:0] bits (Power supply control bits) */

+#define SDMMC_POWER_PWRCTRL_0            (0x1UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000001 */

+#define SDMMC_POWER_PWRCTRL_1            (0x2UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000002 */

+#define SDMMC_POWER_VSWITCH_Pos          (2U)

+#define SDMMC_POWER_VSWITCH_Msk          (0x1UL << SDMMC_POWER_VSWITCH_Pos)    /*!< 0x00000004 */

+#define SDMMC_POWER_VSWITCH              SDMMC_POWER_VSWITCH_Msk               /*!<Voltage switch sequence start */

+#define SDMMC_POWER_VSWITCHEN_Pos        (3U)

+#define SDMMC_POWER_VSWITCHEN_Msk        (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)  /*!< 0x00000008 */

+#define SDMMC_POWER_VSWITCHEN            SDMMC_POWER_VSWITCHEN_Msk             /*!<Voltage switch procedure enable */

+#define SDMMC_POWER_DIRPOL_Pos           (4U)

+#define SDMMC_POWER_DIRPOL_Msk           (0x1UL << SDMMC_POWER_DIRPOL_Pos)     /*!< 0x00000010 */

+#define SDMMC_POWER_DIRPOL               SDMMC_POWER_DIRPOL_Msk                /*!<Data and Command direction signals polarity selection */

+

+/******************  Bit definition for SDMMC_CLKCR register  ******************/

+#define SDMMC_CLKCR_CLKDIV_Pos           (0U)

+#define SDMMC_CLKCR_CLKDIV_Msk           (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)   /*!< 0x000003FF */

+#define SDMMC_CLKCR_CLKDIV               SDMMC_CLKCR_CLKDIV_Msk                /*!<Clock divide factor             */

+#define SDMMC_CLKCR_PWRSAV_Pos           (12U)

+#define SDMMC_CLKCR_PWRSAV_Msk           (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)     /*!< 0x00001000 */

+#define SDMMC_CLKCR_PWRSAV               SDMMC_CLKCR_PWRSAV_Msk                /*!<Power saving configuration bit  */

+

+#define SDMMC_CLKCR_WIDBUS_Pos           (14U)

+#define SDMMC_CLKCR_WIDBUS_Msk           (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)     /*!< 0x0000C000 */

+#define SDMMC_CLKCR_WIDBUS               SDMMC_CLKCR_WIDBUS_Msk                /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */

+#define SDMMC_CLKCR_WIDBUS_0             (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00004000 */

+#define SDMMC_CLKCR_WIDBUS_1             (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00008000 */

+

+#define SDMMC_CLKCR_NEGEDGE_Pos          (16U)

+#define SDMMC_CLKCR_NEGEDGE_Msk          (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)    /*!< 0x00010000 */

+#define SDMMC_CLKCR_NEGEDGE              SDMMC_CLKCR_NEGEDGE_Msk               /*!<SDMMC_CK dephasing selection bit */

+#define SDMMC_CLKCR_HWFC_EN_Pos          (17U)

+#define SDMMC_CLKCR_HWFC_EN_Msk          (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)    /*!< 0x00020000 */

+#define SDMMC_CLKCR_HWFC_EN              SDMMC_CLKCR_HWFC_EN_Msk               /*!<HW Flow Control enable           */

+#define SDMMC_CLKCR_DDR_Pos              (18U)

+#define SDMMC_CLKCR_DDR_Msk              (0x1UL << SDMMC_CLKCR_DDR_Pos)        /*!< 0x00040000 */

+#define SDMMC_CLKCR_DDR                  SDMMC_CLKCR_DDR_Msk                   /*!<Data rate signaling selection    */

+#define SDMMC_CLKCR_BUSSPEED_Pos         (19U)

+#define SDMMC_CLKCR_BUSSPEED_Msk         (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)   /*!< 0x00080000 */

+#define SDMMC_CLKCR_BUSSPEED             SDMMC_CLKCR_BUSSPEED_Msk              /*!<Bus speed mode selection         */

+#define SDMMC_CLKCR_SELCLKRX_Pos         (20U)

+#define SDMMC_CLKCR_SELCLKRX_Msk         (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)   /*!< 0x00300000 */

+#define SDMMC_CLKCR_SELCLKRX             SDMMC_CLKCR_SELCLKRX_Msk              /*!<SELCLKRX[1:0] bits (Receive clock selection) */

+#define SDMMC_CLKCR_SELCLKRX_0           (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00100000 */

+#define SDMMC_CLKCR_SELCLKRX_1           (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00200000 */

+

+/*******************  Bit definition for SDMMC_ARG register  *******************/

+#define SDMMC_ARG_CMDARG_Pos             (0U)

+#define SDMMC_ARG_CMDARG_Msk             (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_ARG_CMDARG                 SDMMC_ARG_CMDARG_Msk                  /*!<Command argument */

+

+/*******************  Bit definition for SDMMC_CMD register  *******************/

+#define SDMMC_CMD_CMDINDEX_Pos           (0U)

+#define SDMMC_CMD_CMDINDEX_Msk           (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)    /*!< 0x0000003F */

+#define SDMMC_CMD_CMDINDEX               SDMMC_CMD_CMDINDEX_Msk                /*!<Command Index                               */

+#define SDMMC_CMD_CMDTRANS_Pos           (6U)

+#define SDMMC_CMD_CMDTRANS_Msk           (0x1UL << SDMMC_CMD_CMDTRANS_Pos)     /*!< 0x00000040 */

+#define SDMMC_CMD_CMDTRANS               SDMMC_CMD_CMDTRANS_Msk                /*!<CPSM Treats command as a Data Transfer      */

+#define SDMMC_CMD_CMDSTOP_Pos            (7U)

+#define SDMMC_CMD_CMDSTOP_Msk            (0x1UL << SDMMC_CMD_CMDSTOP_Pos)      /*!< 0x00000080 */

+#define SDMMC_CMD_CMDSTOP                SDMMC_CMD_CMDSTOP_Msk                 /*!<CPSM Treats command as a Stop               */

+

+#define SDMMC_CMD_WAITRESP_Pos           (8U)

+#define SDMMC_CMD_WAITRESP_Msk           (0x3UL << SDMMC_CMD_WAITRESP_Pos)     /*!< 0x00000300 */

+#define SDMMC_CMD_WAITRESP               SDMMC_CMD_WAITRESP_Msk                /*!<WAITRESP[1:0] bits (Wait for response bits) */

+#define SDMMC_CMD_WAITRESP_0             (0x1UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000100 */

+#define SDMMC_CMD_WAITRESP_1             (0x2UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000200 */

+

+#define SDMMC_CMD_WAITINT_Pos            (10U)

+#define SDMMC_CMD_WAITINT_Msk            (0x1UL << SDMMC_CMD_WAITINT_Pos)      /*!< 0x00000400 */

+#define SDMMC_CMD_WAITINT                SDMMC_CMD_WAITINT_Msk                 /*!<CPSM Waits for Interrupt Request                               */

+#define SDMMC_CMD_WAITPEND_Pos           (11U)

+#define SDMMC_CMD_WAITPEND_Msk           (0x1UL << SDMMC_CMD_WAITPEND_Pos)     /*!< 0x00000800 */

+#define SDMMC_CMD_WAITPEND               SDMMC_CMD_WAITPEND_Msk                /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */

+#define SDMMC_CMD_CPSMEN_Pos             (12U)

+#define SDMMC_CMD_CPSMEN_Msk             (0x1UL << SDMMC_CMD_CPSMEN_Pos)       /*!< 0x00001000 */

+#define SDMMC_CMD_CPSMEN                 SDMMC_CMD_CPSMEN_Msk                  /*!<Command path state machine (CPSM) Enable bit                   */

+#define SDMMC_CMD_DTHOLD_Pos             (13U)

+#define SDMMC_CMD_DTHOLD_Msk             (0x1UL << SDMMC_CMD_DTHOLD_Pos)       /*!< 0x00002000 */

+#define SDMMC_CMD_DTHOLD                 SDMMC_CMD_DTHOLD_Msk                  /*!<Hold new data block transmission and reception in the DPSM     */

+#define SDMMC_CMD_BOOTMODE_Pos           (14U)

+#define SDMMC_CMD_BOOTMODE_Msk           (0x1UL << SDMMC_CMD_BOOTMODE_Pos)     /*!< 0x00004000 */

+#define SDMMC_CMD_BOOTMODE               SDMMC_CMD_BOOTMODE_Msk                /*!<Boot mode                                                      */

+#define SDMMC_CMD_BOOTEN_Pos             (15U)

+#define SDMMC_CMD_BOOTEN_Msk             (0x1UL << SDMMC_CMD_BOOTEN_Pos)       /*!< 0x00008000 */

+#define SDMMC_CMD_BOOTEN                 SDMMC_CMD_BOOTEN_Msk                  /*!<Enable Boot mode procedure                                     */

+#define SDMMC_CMD_CMDSUSPEND_Pos         (16U)

+#define SDMMC_CMD_CMDSUSPEND_Msk         (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)   /*!< 0x00010000 */

+#define SDMMC_CMD_CMDSUSPEND             SDMMC_CMD_CMDSUSPEND_Msk              /*!<CPSM Treats command as a Suspend or Resume command             */

+

+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/

+#define SDMMC_RESPCMD_RESPCMD_Pos        (0U)

+#define SDMMC_RESPCMD_RESPCMD_Msk        (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */

+#define SDMMC_RESPCMD_RESPCMD            SDMMC_RESPCMD_RESPCMD_Msk             /*!<Response command index */

+

+/******************  Bit definition for SDMMC_RESP0 register  ******************/

+#define SDMMC_RESP0_CARDSTATUS0_Pos      (0U)

+#define SDMMC_RESP0_CARDSTATUS0_Msk      (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP0_CARDSTATUS0          SDMMC_RESP0_CARDSTATUS0_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP1 register  ******************/

+#define SDMMC_RESP1_CARDSTATUS1_Pos      (0U)

+#define SDMMC_RESP1_CARDSTATUS1_Msk      (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP1_CARDSTATUS1          SDMMC_RESP1_CARDSTATUS1_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP2 register  ******************/

+#define SDMMC_RESP2_CARDSTATUS2_Pos      (0U)

+#define SDMMC_RESP2_CARDSTATUS2_Msk      (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP2_CARDSTATUS2          SDMMC_RESP2_CARDSTATUS2_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP3 register  ******************/

+#define SDMMC_RESP3_CARDSTATUS3_Pos      (0U)

+#define SDMMC_RESP3_CARDSTATUS3_Msk      (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP3_CARDSTATUS3          SDMMC_RESP3_CARDSTATUS3_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP4 register  ******************/

+#define SDMMC_RESP4_CARDSTATUS4_Pos      (0U)

+#define SDMMC_RESP4_CARDSTATUS4_Msk      (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP4_CARDSTATUS4          SDMMC_RESP4_CARDSTATUS4_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_DTIMER register  *****************/

+#define SDMMC_DTIMER_DATATIME_Pos        (0U)

+#define SDMMC_DTIMER_DATATIME_Msk        (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_DTIMER_DATATIME            SDMMC_DTIMER_DATATIME_Msk             /*!<Data timeout period. */

+

+/******************  Bit definition for SDMMC_DLEN register  *******************/

+#define SDMMC_DLEN_DATALENGTH_Pos        (0U)

+#define SDMMC_DLEN_DATALENGTH_Msk        (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_DLEN_DATALENGTH            SDMMC_DLEN_DATALENGTH_Msk             /*!<Data length value    */

+

+/******************  Bit definition for SDMMC_DCTRL register  ******************/

+#define SDMMC_DCTRL_DTEN_Pos             (0U)

+#define SDMMC_DCTRL_DTEN_Msk             (0x1UL << SDMMC_DCTRL_DTEN_Pos)       /*!< 0x00000001 */

+#define SDMMC_DCTRL_DTEN                 SDMMC_DCTRL_DTEN_Msk                  /*!<Data transfer enabled bit                */

+#define SDMMC_DCTRL_DTDIR_Pos            (1U)

+#define SDMMC_DCTRL_DTDIR_Msk            (0x1UL << SDMMC_DCTRL_DTDIR_Pos)      /*!< 0x00000002 */

+#define SDMMC_DCTRL_DTDIR                SDMMC_DCTRL_DTDIR_Msk                 /*!<Data transfer direction selection        */

+#define SDMMC_DCTRL_DTMODE_Pos           (2U)

+#define SDMMC_DCTRL_DTMODE_Msk           (0x3UL << SDMMC_DCTRL_DTMODE_Pos)     /*!< 0x0000000C */

+#define SDMMC_DCTRL_DTMODE               SDMMC_DCTRL_DTMODE_Msk                /*!<DTMODE[1:0] Data transfer mode selection */

+#define SDMMC_DCTRL_DTMODE_0             (0x1UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000004 */

+#define SDMMC_DCTRL_DTMODE_1             (0x2UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000008 */

+

+#define SDMMC_DCTRL_DBLOCKSIZE_Pos       (4U)

+#define SDMMC_DCTRL_DBLOCKSIZE_Msk       (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */

+#define SDMMC_DCTRL_DBLOCKSIZE           SDMMC_DCTRL_DBLOCKSIZE_Msk            /*!<DBLOCKSIZE[3:0] bits (Data block size) */

+#define SDMMC_DCTRL_DBLOCKSIZE_0         (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000010 */

+#define SDMMC_DCTRL_DBLOCKSIZE_1         (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000020 */

+#define SDMMC_DCTRL_DBLOCKSIZE_2         (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000040 */

+#define SDMMC_DCTRL_DBLOCKSIZE_3         (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000080 */

+

+#define SDMMC_DCTRL_RWSTART_Pos          (8U)

+#define SDMMC_DCTRL_RWSTART_Msk          (0x1UL << SDMMC_DCTRL_RWSTART_Pos)    /*!< 0x00000100 */

+#define SDMMC_DCTRL_RWSTART              SDMMC_DCTRL_RWSTART_Msk               /*!<Read wait start                                 */

+#define SDMMC_DCTRL_RWSTOP_Pos           (9U)

+#define SDMMC_DCTRL_RWSTOP_Msk           (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)     /*!< 0x00000200 */

+#define SDMMC_DCTRL_RWSTOP               SDMMC_DCTRL_RWSTOP_Msk                /*!<Read wait stop                                  */

+#define SDMMC_DCTRL_RWMOD_Pos            (10U)

+#define SDMMC_DCTRL_RWMOD_Msk            (0x1UL << SDMMC_DCTRL_RWMOD_Pos)      /*!< 0x00000400 */

+#define SDMMC_DCTRL_RWMOD                SDMMC_DCTRL_RWMOD_Msk                 /*!<Read wait mode                                  */

+#define SDMMC_DCTRL_SDIOEN_Pos           (11U)

+#define SDMMC_DCTRL_SDIOEN_Msk           (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)     /*!< 0x00000800 */

+#define SDMMC_DCTRL_SDIOEN               SDMMC_DCTRL_SDIOEN_Msk                /*!<SD I/O enable functions                         */

+#define SDMMC_DCTRL_BOOTACKEN_Pos        (12U)

+#define SDMMC_DCTRL_BOOTACKEN_Msk        (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)  /*!< 0x00001000 */

+#define SDMMC_DCTRL_BOOTACKEN            SDMMC_DCTRL_BOOTACKEN_Msk             /*!<Enable the reception of the Boot Acknowledgment */

+#define SDMMC_DCTRL_FIFORST_Pos          (13U)

+#define SDMMC_DCTRL_FIFORST_Msk          (0x1UL << SDMMC_DCTRL_FIFORST_Pos)    /*!< 0x00002000 */

+#define SDMMC_DCTRL_FIFORST              SDMMC_DCTRL_FIFORST_Msk               /*!<FIFO reset                                      */

+

+/******************  Bit definition for SDMMC_DCOUNT register  *****************/

+#define SDMMC_DCOUNT_DATACOUNT_Pos       (0U)

+#define SDMMC_DCOUNT_DATACOUNT_Msk       (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_DCOUNT_DATACOUNT           SDMMC_DCOUNT_DATACOUNT_Msk            /*!<Data count value */

+

+/******************  Bit definition for SDMMC_STA register  ********************/

+#define SDMMC_STA_CCRCFAIL_Pos           (0U)

+#define SDMMC_STA_CCRCFAIL_Msk           (0x1UL << SDMMC_STA_CCRCFAIL_Pos)     /*!< 0x00000001 */

+#define SDMMC_STA_CCRCFAIL               SDMMC_STA_CCRCFAIL_Msk                /*!<Command response received (CRC check failed)  */

+#define SDMMC_STA_DCRCFAIL_Pos           (1U)

+#define SDMMC_STA_DCRCFAIL_Msk           (0x1UL << SDMMC_STA_DCRCFAIL_Pos)     /*!< 0x00000002 */

+#define SDMMC_STA_DCRCFAIL               SDMMC_STA_DCRCFAIL_Msk                /*!<Data block sent/received (CRC check failed)   */

+#define SDMMC_STA_CTIMEOUT_Pos           (2U)

+#define SDMMC_STA_CTIMEOUT_Msk           (0x1UL << SDMMC_STA_CTIMEOUT_Pos)     /*!< 0x00000004 */

+#define SDMMC_STA_CTIMEOUT               SDMMC_STA_CTIMEOUT_Msk                /*!<Command response timeout                      */

+#define SDMMC_STA_DTIMEOUT_Pos           (3U)

+#define SDMMC_STA_DTIMEOUT_Msk           (0x1UL << SDMMC_STA_DTIMEOUT_Pos)     /*!< 0x00000008 */

+#define SDMMC_STA_DTIMEOUT               SDMMC_STA_DTIMEOUT_Msk                /*!<Data timeout                                  */

+#define SDMMC_STA_TXUNDERR_Pos           (4U)

+#define SDMMC_STA_TXUNDERR_Msk           (0x1UL << SDMMC_STA_TXUNDERR_Pos)     /*!< 0x00000010 */

+#define SDMMC_STA_TXUNDERR               SDMMC_STA_TXUNDERR_Msk                /*!<Transmit FIFO underrun error                  */

+#define SDMMC_STA_RXOVERR_Pos            (5U)

+#define SDMMC_STA_RXOVERR_Msk            (0x1UL << SDMMC_STA_RXOVERR_Pos)      /*!< 0x00000020 */

+#define SDMMC_STA_RXOVERR                SDMMC_STA_RXOVERR_Msk                 /*!<Received FIFO overrun error                   */

+#define SDMMC_STA_CMDREND_Pos            (6U)

+#define SDMMC_STA_CMDREND_Msk            (0x1UL << SDMMC_STA_CMDREND_Pos)      /*!< 0x00000040 */

+#define SDMMC_STA_CMDREND                SDMMC_STA_CMDREND_Msk                 /*!<Command response received (CRC check passed)  */

+#define SDMMC_STA_CMDSENT_Pos            (7U)

+#define SDMMC_STA_CMDSENT_Msk            (0x1UL << SDMMC_STA_CMDSENT_Pos)      /*!< 0x00000080 */

+#define SDMMC_STA_CMDSENT                SDMMC_STA_CMDSENT_Msk                 /*!<Command sent (no response required)           */

+#define SDMMC_STA_DATAEND_Pos            (8U)

+#define SDMMC_STA_DATAEND_Msk            (0x1UL << SDMMC_STA_DATAEND_Pos)      /*!< 0x00000100 */

+#define SDMMC_STA_DATAEND                SDMMC_STA_DATAEND_Msk                 /*!<Data end (data counter, SDIDCOUNT, is zero)   */

+#define SDMMC_STA_DHOLD_Pos              (9U)

+#define SDMMC_STA_DHOLD_Msk              (0x1UL << SDMMC_STA_DHOLD_Pos)        /*!< 0x00000200 */

+#define SDMMC_STA_DHOLD                  SDMMC_STA_DHOLD_Msk                   /*!<Data transfer Hold                                                      */

+#define SDMMC_STA_DBCKEND_Pos            (10U)

+#define SDMMC_STA_DBCKEND_Msk            (0x1UL << SDMMC_STA_DBCKEND_Pos)      /*!< 0x00000400 */

+#define SDMMC_STA_DBCKEND                SDMMC_STA_DBCKEND_Msk                 /*!<Data block sent/received (CRC check passed)   */

+#define SDMMC_STA_DABORT_Pos             (11U)

+#define SDMMC_STA_DABORT_Msk             (0x1UL << SDMMC_STA_DABORT_Pos)       /*!< 0x00000800 */

+#define SDMMC_STA_DABORT                 SDMMC_STA_DABORT_Msk                  /*!<Data transfer aborted by CMD12                                          */

+#define SDMMC_STA_DPSMACT_Pos            (12U)

+#define SDMMC_STA_DPSMACT_Msk            (0x1UL << SDMMC_STA_DPSMACT_Pos)      /*!< 0x00001000 */

+#define SDMMC_STA_DPSMACT                SDMMC_STA_DPSMACT_Msk                 /*!<Data path state machine active                                       */

+#define SDMMC_STA_CPSMACT_Pos            (13U)

+#define SDMMC_STA_CPSMACT_Msk            (0x1UL << SDMMC_STA_CPSMACT_Pos)      /*!< 0x00002000 */

+#define SDMMC_STA_CPSMACT                SDMMC_STA_CPSMACT_Msk                 /*!<Command path state machine active                                          */

+#define SDMMC_STA_TXFIFOHE_Pos           (14U)

+#define SDMMC_STA_TXFIFOHE_Msk           (0x1UL << SDMMC_STA_TXFIFOHE_Pos)     /*!< 0x00004000 */

+#define SDMMC_STA_TXFIFOHE               SDMMC_STA_TXFIFOHE_Msk                /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */

+#define SDMMC_STA_RXFIFOHF_Pos           (15U)

+#define SDMMC_STA_RXFIFOHF_Msk           (0x1UL << SDMMC_STA_RXFIFOHF_Pos)     /*!< 0x00008000 */

+#define SDMMC_STA_RXFIFOHF               SDMMC_STA_RXFIFOHF_Msk                /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */

+#define SDMMC_STA_TXFIFOF_Pos            (16U)

+#define SDMMC_STA_TXFIFOF_Msk            (0x1UL << SDMMC_STA_TXFIFOF_Pos)      /*!< 0x00010000 */

+#define SDMMC_STA_TXFIFOF                SDMMC_STA_TXFIFOF_Msk                 /*!<Transmit FIFO full                            */

+#define SDMMC_STA_RXFIFOF_Pos            (17U)

+#define SDMMC_STA_RXFIFOF_Msk            (0x1UL << SDMMC_STA_RXFIFOF_Pos)      /*!< 0x00020000 */

+#define SDMMC_STA_RXFIFOF                SDMMC_STA_RXFIFOF_Msk                 /*!<Receive FIFO full                             */

+#define SDMMC_STA_TXFIFOE_Pos            (18U)

+#define SDMMC_STA_TXFIFOE_Msk            (0x1UL << SDMMC_STA_TXFIFOE_Pos)      /*!< 0x00040000 */

+#define SDMMC_STA_TXFIFOE                SDMMC_STA_TXFIFOE_Msk                 /*!<Transmit FIFO empty                           */

+#define SDMMC_STA_RXFIFOE_Pos            (19U)

+#define SDMMC_STA_RXFIFOE_Msk            (0x1UL << SDMMC_STA_RXFIFOE_Pos)      /*!< 0x00080000 */

+#define SDMMC_STA_RXFIFOE                SDMMC_STA_RXFIFOE_Msk                 /*!<Receive FIFO empty                            */

+#define SDMMC_STA_BUSYD0_Pos             (20U)

+#define SDMMC_STA_BUSYD0_Msk             (0x1UL << SDMMC_STA_BUSYD0_Pos)       /*!< 0x00100000 */

+#define SDMMC_STA_BUSYD0                 SDMMC_STA_BUSYD0_Msk                  /*!<Inverted value of SDMMC_D0 line (Busy)                                  */

+#define SDMMC_STA_BUSYD0END_Pos          (21U)

+#define SDMMC_STA_BUSYD0END_Msk          (0x1UL << SDMMC_STA_BUSYD0END_Pos)    /*!< 0x00200000 */

+#define SDMMC_STA_BUSYD0END              SDMMC_STA_BUSYD0END_Msk               /*!<End of SDMMC_D0 Busy following a CMD response detected                  */

+#define SDMMC_STA_SDIOIT_Pos             (22U)

+#define SDMMC_STA_SDIOIT_Msk             (0x1UL << SDMMC_STA_SDIOIT_Pos)       /*!< 0x00400000 */

+#define SDMMC_STA_SDIOIT                 SDMMC_STA_SDIOIT_Msk                  /*!<SDIO interrupt received                                                 */

+#define SDMMC_STA_ACKFAIL_Pos            (23U)

+#define SDMMC_STA_ACKFAIL_Msk            (0x1UL << SDMMC_STA_ACKFAIL_Pos)      /*!< 0x00800000 */

+#define SDMMC_STA_ACKFAIL                SDMMC_STA_ACKFAIL_Msk                 /*!<Boot Acknowledgment received (BootAck check fail)                       */

+#define SDMMC_STA_ACKTIMEOUT_Pos         (24U)

+#define SDMMC_STA_ACKTIMEOUT_Msk         (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)   /*!< 0x01000000 */

+#define SDMMC_STA_ACKTIMEOUT             SDMMC_STA_ACKTIMEOUT_Msk              /*!<Boot Acknowledgment timeout                                             */

+#define SDMMC_STA_VSWEND_Pos             (25U)

+#define SDMMC_STA_VSWEND_Msk             (0x1UL << SDMMC_STA_VSWEND_Pos)       /*!< 0x02000000 */

+#define SDMMC_STA_VSWEND                 SDMMC_STA_VSWEND_Msk                  /*!<Voltage switch critical timing section completion                       */

+#define SDMMC_STA_CKSTOP_Pos             (26U)

+#define SDMMC_STA_CKSTOP_Msk             (0x1UL << SDMMC_STA_CKSTOP_Pos)       /*!< 0x04000000 */

+#define SDMMC_STA_CKSTOP                 SDMMC_STA_CKSTOP_Msk                  /*!<SDMMC_CK stopped in Voltage switch procedure                            */

+#define SDMMC_STA_IDMATE_Pos             (27U)

+#define SDMMC_STA_IDMATE_Msk             (0x1UL << SDMMC_STA_IDMATE_Pos)       /*!< 0x08000000 */

+#define SDMMC_STA_IDMATE                 SDMMC_STA_IDMATE_Msk                  /*!<IDMA transfer error                                                     */

+#define SDMMC_STA_IDMABTC_Pos            (28U)

+#define SDMMC_STA_IDMABTC_Msk            (0x1UL << SDMMC_STA_IDMABTC_Pos)      /*!< 0x10000000 */

+#define SDMMC_STA_IDMABTC                SDMMC_STA_IDMABTC_Msk                 /*!<IDMA buffer transfer complete                                           */

+

+/*******************  Bit definition for SDMMC_ICR register  *******************/

+#define SDMMC_ICR_CCRCFAILC_Pos          (0U)

+#define SDMMC_ICR_CCRCFAILC_Msk          (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)    /*!< 0x00000001 */

+#define SDMMC_ICR_CCRCFAILC              SDMMC_ICR_CCRCFAILC_Msk               /*!<CCRCFAIL flag clear bit */

+#define SDMMC_ICR_DCRCFAILC_Pos          (1U)

+#define SDMMC_ICR_DCRCFAILC_Msk          (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)    /*!< 0x00000002 */

+#define SDMMC_ICR_DCRCFAILC              SDMMC_ICR_DCRCFAILC_Msk               /*!<DCRCFAIL flag clear bit */

+#define SDMMC_ICR_CTIMEOUTC_Pos          (2U)

+#define SDMMC_ICR_CTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)    /*!< 0x00000004 */

+#define SDMMC_ICR_CTIMEOUTC              SDMMC_ICR_CTIMEOUTC_Msk               /*!<CTIMEOUT flag clear bit */

+#define SDMMC_ICR_DTIMEOUTC_Pos          (3U)

+#define SDMMC_ICR_DTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)    /*!< 0x00000008 */

+#define SDMMC_ICR_DTIMEOUTC              SDMMC_ICR_DTIMEOUTC_Msk               /*!<DTIMEOUT flag clear bit */

+#define SDMMC_ICR_TXUNDERRC_Pos          (4U)

+#define SDMMC_ICR_TXUNDERRC_Msk          (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)    /*!< 0x00000010 */

+#define SDMMC_ICR_TXUNDERRC              SDMMC_ICR_TXUNDERRC_Msk               /*!<TXUNDERR flag clear bit */

+#define SDMMC_ICR_RXOVERRC_Pos           (5U)

+#define SDMMC_ICR_RXOVERRC_Msk           (0x1UL << SDMMC_ICR_RXOVERRC_Pos)     /*!< 0x00000020 */

+#define SDMMC_ICR_RXOVERRC               SDMMC_ICR_RXOVERRC_Msk                /*!<RXOVERR flag clear bit  */

+#define SDMMC_ICR_CMDRENDC_Pos           (6U)

+#define SDMMC_ICR_CMDRENDC_Msk           (0x1UL << SDMMC_ICR_CMDRENDC_Pos)     /*!< 0x00000040 */

+#define SDMMC_ICR_CMDRENDC               SDMMC_ICR_CMDRENDC_Msk                /*!<CMDREND flag clear bit  */

+#define SDMMC_ICR_CMDSENTC_Pos           (7U)

+#define SDMMC_ICR_CMDSENTC_Msk           (0x1UL << SDMMC_ICR_CMDSENTC_Pos)     /*!< 0x00000080 */

+#define SDMMC_ICR_CMDSENTC               SDMMC_ICR_CMDSENTC_Msk                /*!<CMDSENT flag clear bit  */

+#define SDMMC_ICR_DATAENDC_Pos           (8U)

+#define SDMMC_ICR_DATAENDC_Msk           (0x1UL << SDMMC_ICR_DATAENDC_Pos)     /*!< 0x00000100 */

+#define SDMMC_ICR_DATAENDC               SDMMC_ICR_DATAENDC_Msk                /*!<DATAEND flag clear bit  */

+#define SDMMC_ICR_DHOLDC_Pos             (9U)

+#define SDMMC_ICR_DHOLDC_Msk             (0x1UL << SDMMC_ICR_DHOLDC_Pos)       /*!< 0x00000200 */

+#define SDMMC_ICR_DHOLDC                 SDMMC_ICR_DHOLDC_Msk                  /*!<DHOLD flag clear bit       */

+#define SDMMC_ICR_DBCKENDC_Pos           (10U)

+#define SDMMC_ICR_DBCKENDC_Msk           (0x1UL << SDMMC_ICR_DBCKENDC_Pos)     /*!< 0x00000400 */

+#define SDMMC_ICR_DBCKENDC               SDMMC_ICR_DBCKENDC_Msk                /*!<DBCKEND flag clear bit  */

+#define SDMMC_ICR_DABORTC_Pos            (11U)

+#define SDMMC_ICR_DABORTC_Msk            (0x1UL << SDMMC_ICR_DABORTC_Pos)      /*!< 0x00000800 */

+#define SDMMC_ICR_DABORTC                SDMMC_ICR_DABORTC_Msk                 /*!<DABORTC flag clear bit     */

+#define SDMMC_ICR_BUSYD0ENDC_Pos         (21U)

+#define SDMMC_ICR_BUSYD0ENDC_Msk         (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)   /*!< 0x00200000 */

+#define SDMMC_ICR_BUSYD0ENDC             SDMMC_ICR_BUSYD0ENDC_Msk              /*!<BUSYD0ENDC flag clear bit  */

+#define SDMMC_ICR_SDIOITC_Pos            (22U)

+#define SDMMC_ICR_SDIOITC_Msk            (0x1UL << SDMMC_ICR_SDIOITC_Pos)      /*!< 0x00400000 */

+#define SDMMC_ICR_SDIOITC                SDMMC_ICR_SDIOITC_Msk                 /*!<SDIOIT flag clear bit      */

+#define SDMMC_ICR_ACKFAILC_Pos           (23U)

+#define SDMMC_ICR_ACKFAILC_Msk           (0x1UL << SDMMC_ICR_ACKFAILC_Pos)     /*!< 0x00800000 */

+#define SDMMC_ICR_ACKFAILC               SDMMC_ICR_ACKFAILC_Msk                /*!<ACKFAILC flag clear bit    */

+#define SDMMC_ICR_ACKTIMEOUTC_Pos        (24U)

+#define SDMMC_ICR_ACKTIMEOUTC_Msk        (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)  /*!< 0x01000000 */

+#define SDMMC_ICR_ACKTIMEOUTC            SDMMC_ICR_ACKTIMEOUTC_Msk             /*!<ACKTIMEOUTC flag clear bit */

+#define SDMMC_ICR_VSWENDC_Pos            (25U)

+#define SDMMC_ICR_VSWENDC_Msk            (0x1UL << SDMMC_ICR_VSWENDC_Pos)      /*!< 0x02000000 */

+#define SDMMC_ICR_VSWENDC                SDMMC_ICR_VSWENDC_Msk                 /*!<VSWENDC flag clear bit     */

+#define SDMMC_ICR_CKSTOPC_Pos            (26U)

+#define SDMMC_ICR_CKSTOPC_Msk            (0x1UL << SDMMC_ICR_CKSTOPC_Pos)      /*!< 0x04000000 */

+#define SDMMC_ICR_CKSTOPC                SDMMC_ICR_CKSTOPC_Msk                 /*!<CKSTOPC flag clear bit     */

+#define SDMMC_ICR_IDMATEC_Pos            (27U)

+#define SDMMC_ICR_IDMATEC_Msk            (0x1UL << SDMMC_ICR_IDMATEC_Pos)      /*!< 0x08000000 */

+#define SDMMC_ICR_IDMATEC                SDMMC_ICR_IDMATEC_Msk                 /*!<IDMATEC flag clear bit     */

+#define SDMMC_ICR_IDMABTCC_Pos           (28U)

+#define SDMMC_ICR_IDMABTCC_Msk           (0x1UL << SDMMC_ICR_IDMABTCC_Pos)     /*!< 0x10000000 */

+#define SDMMC_ICR_IDMABTCC               SDMMC_ICR_IDMABTCC_Msk                /*!<IDMABTCC flag clear bit    */

+

+/******************  Bit definition for SDMMC_MASK register  *******************/

+#define SDMMC_MASK_CCRCFAILIE_Pos        (0U)

+#define SDMMC_MASK_CCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)  /*!< 0x00000001 */

+#define SDMMC_MASK_CCRCFAILIE            SDMMC_MASK_CCRCFAILIE_Msk             /*!<Command CRC Fail Interrupt Enable          */

+#define SDMMC_MASK_DCRCFAILIE_Pos        (1U)

+#define SDMMC_MASK_DCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)  /*!< 0x00000002 */

+#define SDMMC_MASK_DCRCFAILIE            SDMMC_MASK_DCRCFAILIE_Msk             /*!<Data CRC Fail Interrupt Enable             */

+#define SDMMC_MASK_CTIMEOUTIE_Pos        (2U)

+#define SDMMC_MASK_CTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)  /*!< 0x00000004 */

+#define SDMMC_MASK_CTIMEOUTIE            SDMMC_MASK_CTIMEOUTIE_Msk             /*!<Command TimeOut Interrupt Enable           */

+#define SDMMC_MASK_DTIMEOUTIE_Pos        (3U)

+#define SDMMC_MASK_DTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)  /*!< 0x00000008 */

+#define SDMMC_MASK_DTIMEOUTIE            SDMMC_MASK_DTIMEOUTIE_Msk             /*!<Data TimeOut Interrupt Enable              */

+#define SDMMC_MASK_TXUNDERRIE_Pos        (4U)

+#define SDMMC_MASK_TXUNDERRIE_Msk        (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)  /*!< 0x00000010 */

+#define SDMMC_MASK_TXUNDERRIE            SDMMC_MASK_TXUNDERRIE_Msk             /*!<Tx FIFO UnderRun Error Interrupt Enable    */

+#define SDMMC_MASK_RXOVERRIE_Pos         (5U)

+#define SDMMC_MASK_RXOVERRIE_Msk         (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)   /*!< 0x00000020 */

+#define SDMMC_MASK_RXOVERRIE             SDMMC_MASK_RXOVERRIE_Msk              /*!<Rx FIFO OverRun Error Interrupt Enable     */

+#define SDMMC_MASK_CMDRENDIE_Pos         (6U)

+#define SDMMC_MASK_CMDRENDIE_Msk         (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)   /*!< 0x00000040 */

+#define SDMMC_MASK_CMDRENDIE             SDMMC_MASK_CMDRENDIE_Msk              /*!<Command Response Received Interrupt Enable */

+#define SDMMC_MASK_CMDSENTIE_Pos         (7U)

+#define SDMMC_MASK_CMDSENTIE_Msk         (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)   /*!< 0x00000080 */

+#define SDMMC_MASK_CMDSENTIE             SDMMC_MASK_CMDSENTIE_Msk              /*!<Command Sent Interrupt Enable              */

+#define SDMMC_MASK_DATAENDIE_Pos         (8U)

+#define SDMMC_MASK_DATAENDIE_Msk         (0x1UL << SDMMC_MASK_DATAENDIE_Pos)   /*!< 0x00000100 */

+#define SDMMC_MASK_DATAENDIE             SDMMC_MASK_DATAENDIE_Msk              /*!<Data End Interrupt Enable                  */

+#define SDMMC_MASK_DHOLDIE_Pos           (9U)

+#define SDMMC_MASK_DHOLDIE_Msk           (0x1UL << SDMMC_MASK_DHOLDIE_Pos)     /*!< 0x00000200 */

+#define SDMMC_MASK_DHOLDIE               SDMMC_MASK_DHOLDIE_Msk                /*!<Data Hold Interrupt Enable                 */

+#define SDMMC_MASK_DBCKENDIE_Pos         (10U)

+#define SDMMC_MASK_DBCKENDIE_Msk         (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)   /*!< 0x00000400 */

+#define SDMMC_MASK_DBCKENDIE             SDMMC_MASK_DBCKENDIE_Msk              /*!<Data Block End Interrupt Enable            */

+#define SDMMC_MASK_DABORTIE_Pos          (11U)

+#define SDMMC_MASK_DABORTIE_Msk          (0x1UL << SDMMC_MASK_DABORTIE_Pos)    /*!< 0x00000800 */

+#define SDMMC_MASK_DABORTIE              SDMMC_MASK_DABORTIE_Msk               /*!<Data transfer aborted interrupt enable     */

+

+#define SDMMC_MASK_TXFIFOHEIE_Pos        (14U)

+#define SDMMC_MASK_TXFIFOHEIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)  /*!< 0x00004000 */

+#define SDMMC_MASK_TXFIFOHEIE            SDMMC_MASK_TXFIFOHEIE_Msk             /*!<Tx FIFO Half Empty interrupt Enable        */

+#define SDMMC_MASK_RXFIFOHFIE_Pos        (15U)

+#define SDMMC_MASK_RXFIFOHFIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)  /*!< 0x00008000 */

+#define SDMMC_MASK_RXFIFOHFIE            SDMMC_MASK_RXFIFOHFIE_Msk             /*!<Rx FIFO Half Full interrupt Enable         */

+

+#define SDMMC_MASK_RXFIFOFIE_Pos         (17U)

+#define SDMMC_MASK_RXFIFOFIE_Msk         (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)   /*!< 0x00020000 */

+#define SDMMC_MASK_RXFIFOFIE             SDMMC_MASK_RXFIFOFIE_Msk              /*!<Rx FIFO Full interrupt Enable              */

+#define SDMMC_MASK_TXFIFOEIE_Pos         (18U)

+#define SDMMC_MASK_TXFIFOEIE_Msk         (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)   /*!< 0x00040000 */

+#define SDMMC_MASK_TXFIFOEIE             SDMMC_MASK_TXFIFOEIE_Msk              /*!<Tx FIFO Empty interrupt Enable             */

+

+#define SDMMC_MASK_BUSYD0ENDIE_Pos       (21U)

+#define SDMMC_MASK_BUSYD0ENDIE_Msk       (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */

+#define SDMMC_MASK_BUSYD0ENDIE           SDMMC_MASK_BUSYD0ENDIE_Msk            /*!<BUSYD0ENDIE interrupt Enable */

+#define SDMMC_MASK_SDIOITIE_Pos           (22U)

+#define SDMMC_MASK_SDIOITIE_Msk           (0x1UL << SDMMC_MASK_SDIOITIE_Pos)     /*!< 0x00400000 */

+#define SDMMC_MASK_SDIOITIE               SDMMC_MASK_SDIOITIE_Msk                /*!<SDMMC Mode Interrupt Received interrupt Enable */

+#define SDMMC_MASK_ACKFAILIE_Pos         (23U)

+#define SDMMC_MASK_ACKFAILIE_Msk         (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)   /*!< 0x00800000 */

+#define SDMMC_MASK_ACKFAILIE             SDMMC_MASK_ACKFAILIE_Msk              /*!<Acknowledgment Fail Interrupt Enable */

+#define SDMMC_MASK_ACKTIMEOUTIE_Pos      (24U)

+#define SDMMC_MASK_ACKTIMEOUTIE_Msk      (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */

+#define SDMMC_MASK_ACKTIMEOUTIE          SDMMC_MASK_ACKTIMEOUTIE_Msk           /*!<Acknowledgment timeout Interrupt Enable */

+#define SDMMC_MASK_VSWENDIE_Pos          (25U)

+#define SDMMC_MASK_VSWENDIE_Msk          (0x1UL << SDMMC_MASK_VSWENDIE_Pos)    /*!< 0x02000000 */

+#define SDMMC_MASK_VSWENDIE              SDMMC_MASK_VSWENDIE_Msk               /*!<Voltage switch critical timing section completion Interrupt Enable */

+#define SDMMC_MASK_CKSTOPIE_Pos          (26U)

+#define SDMMC_MASK_CKSTOPIE_Msk          (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)    /*!< 0x04000000 */

+#define SDMMC_MASK_CKSTOPIE              SDMMC_MASK_CKSTOPIE_Msk               /*!<Voltage Switch clock stopped Interrupt Enable */

+#define SDMMC_MASK_IDMABTCIE_Pos         (28U)

+#define SDMMC_MASK_IDMABTCIE_Msk         (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)   /*!< 0x10000000 */

+#define SDMMC_MASK_IDMABTCIE             SDMMC_MASK_IDMABTCIE_Msk              /*!<IDMA buffer transfer complete Interrupt Enable */

+

+/*****************  Bit definition for SDMMC_ACKTIME register  *****************/

+#define SDMMC_ACKTIME_ACKTIME_Pos        (0U)

+#define SDMMC_ACKTIME_ACKTIME_Msk        (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_ACKTIME_ACKTIME            SDMMC_ACKTIME_ACKTIME_Msk             /*!<Boot acknowledgment timeout period */

+

+/******************  Bit definition for SDMMC_FIFO register  *******************/

+#define SDMMC_FIFO_FIFODATA_Pos          (0U)

+#define SDMMC_FIFO_FIFODATA_Msk          (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_FIFO_FIFODATA              SDMMC_FIFO_FIFODATA_Msk               /*!<Receive and transmit FIFO data */

+

+/******************  Bit definition for SDMMC_IDMACTRL register ****************/

+#define SDMMC_IDMA_IDMAEN_Pos            (0U)

+#define SDMMC_IDMA_IDMAEN_Msk            (0x1UL << SDMMC_IDMA_IDMAEN_Pos)      /*!< 0x00000001 */

+#define SDMMC_IDMA_IDMAEN                SDMMC_IDMA_IDMAEN_Msk                 /*!< Enable the internal DMA of the SDMMC peripheral */

+#define SDMMC_IDMA_IDMABMODE_Pos         (1U)

+#define SDMMC_IDMA_IDMABMODE_Msk         (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)   /*!< 0x00000002 */

+#define SDMMC_IDMA_IDMABMODE             SDMMC_IDMA_IDMABMODE_Msk              /*!< Enable double buffer mode for IDMA */

+#define SDMMC_IDMA_IDMABACT_Pos          (2U)

+#define SDMMC_IDMA_IDMABACT_Msk          (0x1UL << SDMMC_IDMA_IDMABACT_Pos)    /*!< 0x00000004 */

+#define SDMMC_IDMA_IDMABACT              SDMMC_IDMA_IDMABACT_Msk               /*!< Uses buffer 1 when double buffer mode is selected */

+

+/*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/

+#define SDMMC_IDMABSIZE_IDMABNDT_Pos     (5U)

+#define SDMMC_IDMABSIZE_IDMABNDT_Msk     (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */

+#define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */

+

+/*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/

+#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */

+

+/*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/

+#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                        Delay Block Interface (DLYB)                        */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for DLYB_CR register  ********************/

+#define DLYB_CR_DEN_Pos         (0U)

+#define DLYB_CR_DEN_Msk         (0x1UL << DLYB_CR_DEN_Pos)                     /*!< 0x00000001 */

+#define DLYB_CR_DEN             DLYB_CR_DEN_Msk                                /*!<Delay Block enable */

+#define DLYB_CR_SEN_Pos         (1U)

+#define DLYB_CR_SEN_Msk         (0x1UL << DLYB_CR_SEN_Pos)                     /*!< 0x00000002 */

+#define DLYB_CR_SEN             DLYB_CR_SEN_Msk                                /*!<Sampler length enable */

+

+

+/*******************  Bit definition for DLYB_CFGR register  ********************/

+#define DLYB_CFGR_SEL_Pos       (0U)

+#define DLYB_CFGR_SEL_Msk       (0xFUL << DLYB_CFGR_SEL_Pos)                   /*!< 0x0000000F */

+#define DLYB_CFGR_SEL           DLYB_CFGR_SEL_Msk                              /*!<Select the phase for the Output clock[3:0] */

+#define DLYB_CFGR_SEL_0         (0x1UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000001 */

+#define DLYB_CFGR_SEL_1         (0x2UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000002 */

+#define DLYB_CFGR_SEL_2         (0x3UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000003 */

+#define DLYB_CFGR_SEL_3         (0x8UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000008 */

+

+#define DLYB_CFGR_UNIT_Pos      (8U)

+#define DLYB_CFGR_UNIT_Msk      (0x7FUL << DLYB_CFGR_UNIT_Pos)                 /*!< 0x00007F00 */

+#define DLYB_CFGR_UNIT          DLYB_CFGR_UNIT_Msk                             /*!<Delay Defines the delay of a Unit delay cell[6:0] */

+#define DLYB_CFGR_UNIT_0        (0x01UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000100 */

+#define DLYB_CFGR_UNIT_1        (0x02UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000200 */

+#define DLYB_CFGR_UNIT_2        (0x04UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000400 */

+#define DLYB_CFGR_UNIT_3        (0x08UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000800 */

+#define DLYB_CFGR_UNIT_4        (0x10UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00001000 */

+#define DLYB_CFGR_UNIT_5        (0x20UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00002000 */

+#define DLYB_CFGR_UNIT_6        (0x40UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00004000 */

+

+#define DLYB_CFGR_LNG_Pos       (16U)

+#define DLYB_CFGR_LNG_Msk       (0xFFFUL << DLYB_CFGR_LNG_Pos)                 /*!< 0x0FFF0000 */

+#define DLYB_CFGR_LNG           DLYB_CFGR_LNG_Msk                              /*!<Delay line length value[11:0] */

+#define DLYB_CFGR_LNG_0         (0x001UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00010000 */

+#define DLYB_CFGR_LNG_1         (0x002UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00020000 */

+#define DLYB_CFGR_LNG_2         (0x004UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00040000 */

+#define DLYB_CFGR_LNG_3         (0x008UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00080000 */

+#define DLYB_CFGR_LNG_4         (0x010UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00100000 */

+#define DLYB_CFGR_LNG_5         (0x020UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00200000 */

+#define DLYB_CFGR_LNG_6         (0x040UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00400000 */

+#define DLYB_CFGR_LNG_7         (0x080UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00800000 */

+#define DLYB_CFGR_LNG_8         (0x100UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x01000000 */

+#define DLYB_CFGR_LNG_9         (0x200UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x02000000 */

+#define DLYB_CFGR_LNG_10        (0x400UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x04000000 */

+#define DLYB_CFGR_LNG_11        (0x800UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x08000000 */

+

+#define DLYB_CFGR_LNGF_Pos      (31U)

+#define DLYB_CFGR_LNGF_Msk      (0x1UL << DLYB_CFGR_LNGF_Pos)                  /*!< 0x80000000 */

+#define DLYB_CFGR_LNGF          DLYB_CFGR_LNGF_Msk                             /*!<Length valid flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                   Serial Peripheral Interface (SPI/I2S)                    */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for SPI_CR1 register  ********************/

+#define SPI_CR1_SPE_Pos             (0U)

+#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000001 */

+#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<Serial Peripheral Enable                         */

+#define SPI_CR1_MASRX_Pos           (8U)

+#define SPI_CR1_MASRX_Msk           (0x1UL << SPI_CR1_MASRX_Pos)               /*!< 0x00000100 */

+#define SPI_CR1_MASRX               SPI_CR1_MASRX_Msk                          /*!<Master automatic SUSP in Receive mode            */

+#define SPI_CR1_CSTART_Pos          (9U)

+#define SPI_CR1_CSTART_Msk          (0x1UL << SPI_CR1_CSTART_Pos)              /*!< 0x00000200 */

+#define SPI_CR1_CSTART              SPI_CR1_CSTART_Msk                         /*!<Master transfer start                            */

+#define SPI_CR1_CSUSP_Pos           (10U)

+#define SPI_CR1_CSUSP_Msk           (0x1UL << SPI_CR1_CSUSP_Pos)               /*!< 0x00000400 */

+#define SPI_CR1_CSUSP               SPI_CR1_CSUSP_Msk                          /*!<Master SUSPend request                           */

+#define SPI_CR1_HDDIR_Pos           (11U)

+#define SPI_CR1_HDDIR_Msk           (0x1UL << SPI_CR1_HDDIR_Pos)               /*!< 0x00000800 */

+#define SPI_CR1_HDDIR               SPI_CR1_HDDIR_Msk                          /*!<Rx/Tx direction at Half-duplex mode              */

+#define SPI_CR1_SSI_Pos             (12U)

+#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00001000 */

+#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal SS signal input level                   */

+#define SPI_CR1_CRC33_17_Pos        (13U)

+#define SPI_CR1_CRC33_17_Msk        (0x1UL << SPI_CR1_CRC33_17_Pos)            /*!< 0x00002000 */

+#define SPI_CR1_CRC33_17             SPI_CR1_CRC33_17_Msk                      /*!<32-bit CRC polynomial configuration              */

+#define SPI_CR1_RCRCINI_Pos         (14U)

+#define SPI_CR1_RCRCINI_Msk         (0x1UL << SPI_CR1_RCRCINI_Pos)             /*!< 0x00004000 */

+#define SPI_CR1_RCRCINI             SPI_CR1_RCRCINI_Msk                        /*!<CRC init pattern control for receiver            */

+#define SPI_CR1_TCRCINI_Pos         (15U)

+#define SPI_CR1_TCRCINI_Msk         (0x1UL << SPI_CR1_TCRCINI_Pos)             /*!< 0x00008000 */

+#define SPI_CR1_TCRCINI             SPI_CR1_TCRCINI_Msk                        /*!<CRC init pattern control for transmitter         */

+#define SPI_CR1_IOLOCK_Pos          (16U)

+#define SPI_CR1_IOLOCK_Msk          (0x1UL << SPI_CR1_IOLOCK_Pos)              /*!< 0x00010000 */

+#define SPI_CR1_IOLOCK              SPI_CR1_IOLOCK_Msk                         /*!<Locking the AF configuration of associated IOs   */

+

+/*******************  Bit definition for SPI_CR2 register  ********************/

+#define SPI_CR2_TSER_Pos            (16U)

+#define SPI_CR2_TSER_Msk            (0xFFFFUL << SPI_CR2_TSER_Pos)             /*!< 0xFFFF0000 */

+#define SPI_CR2_TSER                SPI_CR2_TSER_Msk                           /*!<Number of data transfer extension                */

+#define SPI_CR2_TSIZE_Pos           (0U)

+#define SPI_CR2_TSIZE_Msk           (0xFFFFUL << SPI_CR2_TSIZE_Pos)            /*!< 0x0000FFFF */

+#define SPI_CR2_TSIZE               SPI_CR2_TSIZE_Msk                          /*!<Number of data at current transfer               */

+

+/*******************  Bit definition for SPI_CFG1 register  ********************/

+#define SPI_CFG1_DSIZE_Pos          (0U)

+#define SPI_CFG1_DSIZE_Msk          (0x1FUL << SPI_CFG1_DSIZE_Pos)             /*!< 0x0000001F */

+#define SPI_CFG1_DSIZE              SPI_CFG1_DSIZE_Msk                         /*!<DSIZE[4:0]: Bits number in single SPI data frame */

+#define SPI_CFG1_DSIZE_0            (0x01UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000001 */

+#define SPI_CFG1_DSIZE_1            (0x02UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000002 */

+#define SPI_CFG1_DSIZE_2            (0x04UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000004 */

+#define SPI_CFG1_DSIZE_3            (0x08UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000008 */

+#define SPI_CFG1_DSIZE_4            (0x10UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000010 */

+

+#define SPI_CFG1_FTHLV_Pos          (5U)

+#define SPI_CFG1_FTHLV_Msk          (0xFUL << SPI_CFG1_FTHLV_Pos)              /*!< 0x000001E0 */

+#define SPI_CFG1_FTHLV              SPI_CFG1_FTHLV_Msk                         /*!<FTHVL [3:0]: FIFO threshold level*/

+#define SPI_CFG1_FTHLV_0            (0x1UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000020 */

+#define SPI_CFG1_FTHLV_1            (0x2UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000040 */

+#define SPI_CFG1_FTHLV_2            (0x4UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000080 */

+#define SPI_CFG1_FTHLV_3            (0x8UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000100 */

+

+#define SPI_CFG1_UDRCFG_Pos         (9U)

+#define SPI_CFG1_UDRCFG_Msk         (0x3UL << SPI_CFG1_UDRCFG_Pos)             /*!< 0x00000600 */

+#define SPI_CFG1_UDRCFG             SPI_CFG1_UDRCFG_Msk                        /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */

+#define SPI_CFG1_UDRCFG_0           (0x1UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000200 */

+#define SPI_CFG1_UDRCFG_1           (0x2UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000400 */

+

+

+#define SPI_CFG1_UDRDET_Pos         (11U)

+#define SPI_CFG1_UDRDET_Msk         (0x3UL << SPI_CFG1_UDRDET_Pos)             /*!< 0x00001800 */

+#define SPI_CFG1_UDRDET             SPI_CFG1_UDRDET_Msk                        /*!<UDRDET[1:0]: Detection of underrun condition     */

+#define SPI_CFG1_UDRDET_0           (0x1UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00000800 */

+#define SPI_CFG1_UDRDET_1           (0x2UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00001000 */

+

+#define SPI_CFG1_RXDMAEN_Pos        (14U)

+#define SPI_CFG1_RXDMAEN_Msk        (0x1UL << SPI_CFG1_RXDMAEN_Pos)            /*!< 0x00004000 */

+#define SPI_CFG1_RXDMAEN            SPI_CFG1_RXDMAEN_Msk                       /*!<Rx DMA stream enable                */

+#define SPI_CFG1_TXDMAEN_Pos        (15U)

+#define SPI_CFG1_TXDMAEN_Msk        (0x1UL << SPI_CFG1_TXDMAEN_Pos)            /*!< 0x00008000 */

+#define SPI_CFG1_TXDMAEN            SPI_CFG1_TXDMAEN_Msk                       /*!<Tx DMA stream enable                */

+

+#define SPI_CFG1_CRCSIZE_Pos        (16U)

+#define SPI_CFG1_CRCSIZE_Msk        (0x1FUL << SPI_CFG1_CRCSIZE_Pos)           /*!< 0x001F0000 */

+#define SPI_CFG1_CRCSIZE            SPI_CFG1_CRCSIZE_Msk                       /*!<CRCSIZE [4:0]: Length of CRC frame*/

+#define SPI_CFG1_CRCSIZE_0          (0x01UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00010000 */

+#define SPI_CFG1_CRCSIZE_1          (0x02UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00020000 */

+#define SPI_CFG1_CRCSIZE_2          (0x04UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00040000 */

+#define SPI_CFG1_CRCSIZE_3          (0x08UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00080000 */

+#define SPI_CFG1_CRCSIZE_4          (0x10UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00100000 */

+

+#define SPI_CFG1_CRCEN_Pos          (22U)

+#define SPI_CFG1_CRCEN_Msk          (0x1UL << SPI_CFG1_CRCEN_Pos)              /*!< 0x00400000 */

+#define SPI_CFG1_CRCEN              SPI_CFG1_CRCEN_Msk                         /*!<Hardware CRC computation enable */

+

+#define SPI_CFG1_MBR_Pos            (28U)

+#define SPI_CFG1_MBR_Msk            (0x7UL << SPI_CFG1_MBR_Pos)                /*!< 0x70000000 */

+#define SPI_CFG1_MBR                SPI_CFG1_MBR_Msk                           /*!<Master baud rate                */

+#define SPI_CFG1_MBR_0              (0x1UL << SPI_CFG1_MBR_Pos)                 /*!< 0x10000000 */

+#define SPI_CFG1_MBR_1              (0x2UL << SPI_CFG1_MBR_Pos)                 /*!< 0x20000000 */

+#define SPI_CFG1_MBR_2              (0x4UL << SPI_CFG1_MBR_Pos)                 /*!< 0x40000000 */

+

+/*******************  Bit definition for SPI_CFG2 register  ********************/

+#define SPI_CFG2_MSSI_Pos           (0U)

+#define SPI_CFG2_MSSI_Msk           (0xFUL << SPI_CFG2_MSSI_Pos)               /*!< 0x0000000F */

+#define SPI_CFG2_MSSI               SPI_CFG2_MSSI_Msk                          /*!<Master SS Idleness */

+#define SPI_CFG2_MSSI_0             (0x1UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000001 */

+#define SPI_CFG2_MSSI_1             (0x2UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000002 */

+#define SPI_CFG2_MSSI_2             (0x4UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000004 */

+#define SPI_CFG2_MSSI_3             (0x8UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000008 */

+

+#define SPI_CFG2_MIDI_Pos           (4U)

+#define SPI_CFG2_MIDI_Msk           (0xFUL << SPI_CFG2_MIDI_Pos)               /*!< 0x000000F0 */

+#define SPI_CFG2_MIDI               SPI_CFG2_MIDI_Msk                          /*!<Master Inter-Data Idleness */

+#define SPI_CFG2_MIDI_0             (0x1UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000010 */

+#define SPI_CFG2_MIDI_1             (0x2UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000020 */

+#define SPI_CFG2_MIDI_2             (0x4UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000040 */

+#define SPI_CFG2_MIDI_3             (0x8UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000080 */

+

+#define SPI_CFG2_IOSWP_Pos          (15U)

+#define SPI_CFG2_IOSWP_Msk          (0x1UL << SPI_CFG2_IOSWP_Pos)              /*!< 0x00008000 */

+#define SPI_CFG2_IOSWP              SPI_CFG2_IOSWP_Msk                         /*!<Swap functionality of MISO and MOSI pins */

+

+#define SPI_CFG2_COMM_Pos           (17U)

+#define SPI_CFG2_COMM_Msk           (0x3UL << SPI_CFG2_COMM_Pos)               /*!< 0x00060000 */

+#define SPI_CFG2_COMM               SPI_CFG2_COMM_Msk                          /*!<COMM [1:0]: SPI Communication Mode*/

+#define SPI_CFG2_COMM_0             (0x1UL << SPI_CFG2_COMM_Pos)                /*!< 0x00020000 */

+#define SPI_CFG2_COMM_1             (0x2UL << SPI_CFG2_COMM_Pos)                /*!< 0x00040000 */

+

+#define SPI_CFG2_SP_Pos             (19U)

+#define SPI_CFG2_SP_Msk             (0x7UL << SPI_CFG2_SP_Pos)                 /*!< 0x00380000 */

+#define SPI_CFG2_SP                 SPI_CFG2_SP_Msk                            /*!<SP[2:0]: Serial Protocol */

+#define SPI_CFG2_SP_0               (0x1UL << SPI_CFG2_SP_Pos)                  /*!< 0x00080000 */

+#define SPI_CFG2_SP_1               (0x2UL << SPI_CFG2_SP_Pos)                  /*!< 0x00100000 */

+#define SPI_CFG2_SP_2               (0x4UL << SPI_CFG2_SP_Pos)                  /*!< 0x00200000 */

+

+#define SPI_CFG2_MASTER_Pos         (22U)

+#define SPI_CFG2_MASTER_Msk         (0x1UL << SPI_CFG2_MASTER_Pos)             /*!< 0x00400000 */

+#define SPI_CFG2_MASTER             SPI_CFG2_MASTER_Msk                        /*!<SPI Master           */

+#define SPI_CFG2_LSBFRST_Pos        (23U)

+#define SPI_CFG2_LSBFRST_Msk        (0x1UL << SPI_CFG2_LSBFRST_Pos)            /*!< 0x00800000 */

+#define SPI_CFG2_LSBFRST            SPI_CFG2_LSBFRST_Msk                       /*!<Data frame format               */

+#define SPI_CFG2_CPHA_Pos           (24U)

+#define SPI_CFG2_CPHA_Msk           (0x1UL << SPI_CFG2_CPHA_Pos)               /*!< 0x01000000 */

+#define SPI_CFG2_CPHA               SPI_CFG2_CPHA_Msk                          /*!<Clock Phase      */

+#define SPI_CFG2_CPOL_Pos           (25U)

+#define SPI_CFG2_CPOL_Msk           (0x1UL << SPI_CFG2_CPOL_Pos)               /*!< 0x02000000 */

+#define SPI_CFG2_CPOL               SPI_CFG2_CPOL_Msk                          /*!<Clock Polarity   */

+#define SPI_CFG2_SSM_Pos            (26U)

+#define SPI_CFG2_SSM_Msk            (0x1UL << SPI_CFG2_SSM_Pos)                /*!< 0x04000000 */

+#define SPI_CFG2_SSM                SPI_CFG2_SSM_Msk                           /*!<Software slave management */

+

+#define SPI_CFG2_SSIOP_Pos          (28U)

+#define SPI_CFG2_SSIOP_Msk          (0x1UL << SPI_CFG2_SSIOP_Pos)              /*!< 0x10000000 */

+#define SPI_CFG2_SSIOP              SPI_CFG2_SSIOP_Msk                         /*!<SS input/output polarity */

+#define SPI_CFG2_SSOE_Pos           (29U)

+#define SPI_CFG2_SSOE_Msk           (0x1UL << SPI_CFG2_SSOE_Pos)               /*!< 0x20000000 */

+#define SPI_CFG2_SSOE               SPI_CFG2_SSOE_Msk                          /*!<SS output enable */

+#define SPI_CFG2_SSOM_Pos           (30U)

+#define SPI_CFG2_SSOM_Msk           (0x1UL << SPI_CFG2_SSOM_Pos)               /*!< 0x40000000 */

+#define SPI_CFG2_SSOM               SPI_CFG2_SSOM_Msk                          /*!<SS output management in master mode */

+

+#define SPI_CFG2_AFCNTR_Pos         (31U)

+#define SPI_CFG2_AFCNTR_Msk         (0x1UL << SPI_CFG2_AFCNTR_Pos)             /*!< 0x80000000 */

+#define SPI_CFG2_AFCNTR             SPI_CFG2_AFCNTR_Msk                        /*!<Alternate function GPIOs control */

+

+/*******************  Bit definition for SPI_IER register  ********************/

+#define SPI_IER_RXPIE_Pos           (0U)

+#define SPI_IER_RXPIE_Msk           (0x1UL << SPI_IER_RXPIE_Pos)               /*!< 0x00000001 */

+#define SPI_IER_RXPIE               SPI_IER_RXPIE_Msk                          /*!<RXP Interrupt Enable            */

+#define SPI_IER_TXPIE_Pos           (1U)

+#define SPI_IER_TXPIE_Msk           (0x1UL << SPI_IER_TXPIE_Pos)               /*!< 0x00000002 */

+#define SPI_IER_TXPIE               SPI_IER_TXPIE_Msk                          /*!<TXP interrupt enable            */

+#define SPI_IER_DXPIE_Pos           (2U)

+#define SPI_IER_DXPIE_Msk           (0x1UL << SPI_IER_DXPIE_Pos)               /*!< 0x00000004 */

+#define SPI_IER_DXPIE               SPI_IER_DXPIE_Msk                          /*!<DXP interrupt enable            */

+#define SPI_IER_EOTIE_Pos           (3U)

+#define SPI_IER_EOTIE_Msk           (0x1UL << SPI_IER_EOTIE_Pos)               /*!< 0x00000008 */

+#define SPI_IER_EOTIE               SPI_IER_EOTIE_Msk                          /*!<EOT/SUSP/TXC interrupt enable   */

+#define SPI_IER_TXTFIE_Pos          (4U)

+#define SPI_IER_TXTFIE_Msk          (0x1UL << SPI_IER_TXTFIE_Pos)              /*!< 0x00000010 */

+#define SPI_IER_TXTFIE              SPI_IER_TXTFIE_Msk                         /*!<TXTF interrupt enable           */

+#define SPI_IER_UDRIE_Pos           (5U)

+#define SPI_IER_UDRIE_Msk           (0x1UL << SPI_IER_UDRIE_Pos)               /*!< 0x00000020 */

+#define SPI_IER_UDRIE               SPI_IER_UDRIE_Msk                          /*!<UDR interrupt enable            */

+#define SPI_IER_OVRIE_Pos           (6U)

+#define SPI_IER_OVRIE_Msk           (0x1UL << SPI_IER_OVRIE_Pos)               /*!< 0x00000040 */

+#define SPI_IER_OVRIE               SPI_IER_OVRIE_Msk                          /*!<OVR interrupt enable            */

+#define SPI_IER_CRCEIE_Pos          (7U)

+#define SPI_IER_CRCEIE_Msk          (0x1UL << SPI_IER_CRCEIE_Pos)               /*!< 0x00000080 */

+#define SPI_IER_CRCEIE              SPI_IER_CRCEIE_Msk                          /*!<CRCE interrupt enable           */

+#define SPI_IER_TIFREIE_Pos         (8U)

+#define SPI_IER_TIFREIE_Msk         (0x1UL << SPI_IER_TIFREIE_Pos)             /*!< 0x00000100 */

+#define SPI_IER_TIFREIE             SPI_IER_TIFREIE_Msk                        /*!<TI Frame Error interrupt enable */

+#define SPI_IER_MODFIE_Pos          (9U)

+#define SPI_IER_MODFIE_Msk          (0x1UL << SPI_IER_MODFIE_Pos)              /*!< 0x00000200 */

+#define SPI_IER_MODFIE              SPI_IER_MODFIE_Msk                         /*!<MODF interrupt enable           */

+#define SPI_IER_TSERFIE_Pos         (10U)

+#define SPI_IER_TSERFIE_Msk         (0x1UL << SPI_IER_TSERFIE_Pos)              /*!< 0x00000400 */

+#define SPI_IER_TSERFIE             SPI_IER_TSERFIE_Msk                        /*!<TSERF interrupt enable          */

+

+/*******************  Bit definition for SPI_SR register  ********************/

+#define SPI_SR_RXP_Pos              (0U)

+#define SPI_SR_RXP_Msk              (0x1UL << SPI_SR_RXP_Pos)                  /*!< 0x00000001 */

+#define SPI_SR_RXP                  SPI_SR_RXP_Msk                             /*!<Rx-Packet available             */

+#define SPI_SR_TXP_Pos              (1U)

+#define SPI_SR_TXP_Msk              (0x1UL << SPI_SR_TXP_Pos)                  /*!< 0x00000002 */

+#define SPI_SR_TXP                  SPI_SR_TXP_Msk                             /*!<Tx-Packet space available       */

+#define SPI_SR_DXP_Pos              (2U)

+#define SPI_SR_DXP_Msk              (0x1UL << SPI_SR_DXP_Pos)                  /*!< 0x00000004 */

+#define SPI_SR_DXP                  SPI_SR_DXP_Msk                             /*!<Duplex Packet available         */

+#define SPI_SR_EOT_Pos              (3U)

+#define SPI_SR_EOT_Msk              (0x1UL << SPI_SR_EOT_Pos)                  /*!< 0x00000008 */

+#define SPI_SR_EOT                  SPI_SR_EOT_Msk                             /*!<Duplex Packet available         */

+#define SPI_SR_TXTF_Pos             (4U)

+#define SPI_SR_TXTF_Msk             (0x1UL << SPI_SR_TXTF_Pos)                 /*!< 0x00000010 */

+#define SPI_SR_TXTF                 SPI_SR_TXTF_Msk                            /*!<Transmission Transfer Filled    */

+#define SPI_SR_UDR_Pos              (5U)

+#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000020 */

+#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<UDR at Slave transmission       */

+#define SPI_SR_OVR_Pos              (6U)

+#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */

+#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Rx-Packet available             */

+#define SPI_SR_CRCE_Pos             (7U)

+#define SPI_SR_CRCE_Msk             (0x1UL << SPI_SR_CRCE_Pos)                 /*!< 0x00000080 */

+#define SPI_SR_CRCE                 SPI_SR_CRCE_Msk                            /*!<CRC Error Detected              */

+#define SPI_SR_TIFRE_Pos            (8U)

+#define SPI_SR_TIFRE_Msk            (0x1UL << SPI_SR_TIFRE_Pos)                /*!< 0x00000100 */

+#define SPI_SR_TIFRE                SPI_SR_TIFRE_Msk                           /*!<TI frame format error Detected  */

+#define SPI_SR_MODF_Pos             (9U)

+#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000200 */

+#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode Fault Detected             */

+#define SPI_SR_TSERF_Pos            (10U)

+#define SPI_SR_TSERF_Msk            (0x1UL << SPI_SR_TSERF_Pos)                /*!< 0x00000400 */

+#define SPI_SR_TSERF                SPI_SR_TSERF_Msk                           /*!<Number of SPI data to be transacted reloaded     */

+#define SPI_SR_SUSP_Pos             (11U)

+#define SPI_SR_SUSP_Msk             (0x1UL << SPI_SR_SUSP_Pos)                 /*!< 0x00000800 */

+#define SPI_SR_SUSP                 SPI_SR_SUSP_Msk                            /*!<SUSP is set by hardware  */

+#define SPI_SR_TXC_Pos              (12U)

+#define SPI_SR_TXC_Msk              (0x1UL << SPI_SR_TXC_Pos)                  /*!< 0x00001000 */

+#define SPI_SR_TXC                  SPI_SR_TXC_Msk                             /*!<TxFIFO transmission complete */

+#define SPI_SR_RXPLVL_Pos           (13U)

+#define SPI_SR_RXPLVL_Msk           (0x3UL << SPI_SR_RXPLVL_Pos)               /*!< 0x00006000 */

+#define SPI_SR_RXPLVL               SPI_SR_RXPLVL_Msk                          /*!<RxFIFO Packing Level                             */

+#define SPI_SR_RXPLVL_0             (0x1UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00002000 */

+#define SPI_SR_RXPLVL_1             (0x2UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00004000 */

+#define SPI_SR_RXWNE_Pos            (15U)

+#define SPI_SR_RXWNE_Msk            (0x1UL << SPI_SR_RXWNE_Pos)                /*!< 0x00008000 */

+#define SPI_SR_RXWNE                SPI_SR_RXWNE_Msk                           /*!<Rx FIFO Word Not Empty                           */

+#define SPI_SR_CTSIZE_Pos           (16U)

+#define SPI_SR_CTSIZE_Msk           (0xFFFFUL << SPI_SR_CTSIZE_Pos)            /*!< 0xFFFF0000 */

+#define SPI_SR_CTSIZE               SPI_SR_CTSIZE_Msk                          /*!<Number of data frames remaining in TSIZE         */

+

+/*******************  Bit definition for SPI_IFCR register  ********************/

+#define SPI_IFCR_EOTC_Pos           (3U)

+#define SPI_IFCR_EOTC_Msk           (0x1UL << SPI_IFCR_EOTC_Pos)               /*!< 0x00000008 */

+#define SPI_IFCR_EOTC               SPI_IFCR_EOTC_Msk                          /*!<End Of Transfer flag clear              */

+#define SPI_IFCR_TXTFC_Pos          (4U)

+#define SPI_IFCR_TXTFC_Msk          (0x1UL << SPI_IFCR_TXTFC_Pos)              /*!< 0x00000010 */

+#define SPI_IFCR_TXTFC              SPI_IFCR_TXTFC_Msk                         /*!<Transmission Transfer Filled flag clear */

+#define SPI_IFCR_UDRC_Pos           (5U)

+#define SPI_IFCR_UDRC_Msk           (0x1UL << SPI_IFCR_UDRC_Pos)               /*!< 0x00000020 */

+#define SPI_IFCR_UDRC               SPI_IFCR_UDRC_Msk                          /*!<Underrun flag clear                     */

+#define SPI_IFCR_OVRC_Pos           (6U)

+#define SPI_IFCR_OVRC_Msk           (0x1UL << SPI_IFCR_OVRC_Pos)               /*!< 0x00000040 */

+#define SPI_IFCR_OVRC               SPI_IFCR_OVRC_Msk                          /*!<Overrun flag clear                      */

+#define SPI_IFCR_CRCEC_Pos          (7U)

+#define SPI_IFCR_CRCEC_Msk          (0x1UL << SPI_IFCR_CRCEC_Pos)              /*!< 0x00000080 */

+#define SPI_IFCR_CRCEC              SPI_IFCR_CRCEC_Msk                         /*!<CRC Error flag clear                    */

+#define SPI_IFCR_TIFREC_Pos         (8U)

+#define SPI_IFCR_TIFREC_Msk         (0x1UL << SPI_IFCR_TIFREC_Pos)             /*!< 0x00000100 */

+#define SPI_IFCR_TIFREC             SPI_IFCR_TIFREC_Msk                        /*!<TI frame format error flag clear        */

+#define SPI_IFCR_MODFC_Pos          (9U)

+#define SPI_IFCR_MODFC_Msk          (0x1UL << SPI_IFCR_MODFC_Pos)              /*!< 0x00000200 */

+#define SPI_IFCR_MODFC              SPI_IFCR_MODFC_Msk                         /*!<Mode Fault flag clear                   */

+#define SPI_IFCR_TSERFC_Pos         (10U)

+#define SPI_IFCR_TSERFC_Msk         (0x1UL << SPI_IFCR_TSERFC_Pos)             /*!< 0x00000400 */

+#define SPI_IFCR_TSERFC             SPI_IFCR_TSERFC_Msk                        /*!<TSERFC flag clear                       */

+#define SPI_IFCR_SUSPC_Pos          (11U)

+#define SPI_IFCR_SUSPC_Msk          (0x1UL << SPI_IFCR_SUSPC_Pos)              /*!< 0x00000800 */

+#define SPI_IFCR_SUSPC              SPI_IFCR_SUSPC_Msk                         /*!<SUSPend flag clear                      */

+

+/*******************  Bit definition for SPI_TXDR register  ********************/

+#define SPI_TXDR_TXDR_Pos           (0U)

+#define SPI_TXDR_TXDR_Msk           (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)        /*!< 0xFFFFFFFF */

+#define SPI_TXDR_TXDR               SPI_TXDR_TXDR_Msk                          /* Transmit Data Register */

+

+/*******************  Bit definition for SPI_RXDR register  ********************/

+#define SPI_RXDR_RXDR_Pos           (0U)

+#define SPI_RXDR_RXDR_Msk           (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)        /*!< 0xFFFFFFFF */

+#define SPI_RXDR_RXDR               SPI_RXDR_RXDR_Msk                          /* Receive Data Register  */

+

+/*******************  Bit definition for SPI_CRCPOLY register  ********************/

+#define SPI_CRCPOLY_CRCPOLY_Pos     (0U)

+#define SPI_CRCPOLY_CRCPOLY_Msk     (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)  /*!< 0xFFFFFFFF */

+#define SPI_CRCPOLY_CRCPOLY         SPI_CRCPOLY_CRCPOLY_Msk                    /* CRC Polynomial register  */

+

+/*******************  Bit definition for SPI_TXCRC register  ********************/

+#define SPI_TXCRC_TXCRC_Pos         (0U)

+#define SPI_TXCRC_TXCRC_Msk         (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_TXCRC_TXCRC             SPI_TXCRC_TXCRC_Msk                        /* CRCRegister for transmitter */

+

+/*******************  Bit definition for SPI_RXCRC register  ********************/

+#define SPI_RXCRC_RXCRC_Pos         (0U)

+#define SPI_RXCRC_RXCRC_Msk         (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_RXCRC_RXCRC             SPI_RXCRC_RXCRC_Msk                        /* CRCRegister for receiver */

+

+/*******************  Bit definition for SPI_UDRDR register  ********************/

+#define SPI_UDRDR_UDRDR_Pos         (0U)

+#define SPI_UDRDR_UDRDR_Msk         (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_UDRDR_UDRDR             SPI_UDRDR_UDRDR_Msk                        /* Data at slave underrun condition */

+

+/******************  Bit definition for SPI_I2SCFGR register  *****************/

+#define SPI_I2SCFGR_I2SMOD_Pos      (0U)

+#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000001 */

+#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */

+#define SPI_I2SCFGR_I2SCFG_Pos      (1U)

+#define SPI_I2SCFGR_I2SCFG_Msk      (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x0000000E */

+#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[2:0] I2S configuration mode                */

+#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000002 */

+#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000004 */

+#define SPI_I2SCFGR_I2SCFG_2        (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000008 */

+#define SPI_I2SCFGR_I2SSTD_Pos      (4U)

+#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */

+#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] I2S standard selection                */

+#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */

+#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */

+#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)

+#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */

+#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                         */

+#define SPI_I2SCFGR_DATLEN_Pos      (8U)

+#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000300 */

+#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] Data length to be transferred         */

+#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000100 */

+#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000200 */

+#define SPI_I2SCFGR_CHLEN_Pos       (10U)

+#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000400 */

+#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */

+#define SPI_I2SCFGR_CKPOL_Pos       (11U)

+#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000800 */

+#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<Steady state clock polarity                       */

+#define SPI_I2SCFGR_FIXCH_Pos       (12U)

+#define SPI_I2SCFGR_FIXCH_Msk       (0x1UL << SPI_I2SCFGR_FIXCH_Pos)           /*!< 0x00001000 */

+#define SPI_I2SCFGR_FIXCH           SPI_I2SCFGR_FIXCH_Msk                      /*!<Fixed channel length in SLAVE                     */

+#define SPI_I2SCFGR_WSINV_Pos       (13U)

+#define SPI_I2SCFGR_WSINV_Msk       (0x1UL << SPI_I2SCFGR_WSINV_Pos)           /*!< 0x00002000 */

+#define SPI_I2SCFGR_WSINV           SPI_I2SCFGR_WSINV_Msk                      /*!<Word select inversion                             */

+#define SPI_I2SCFGR_DATFMT_Pos      (14U)

+#define SPI_I2SCFGR_DATFMT_Msk      (0x1UL << SPI_I2SCFGR_DATFMT_Pos)          /*!< 0x00004000 */

+#define SPI_I2SCFGR_DATFMT          SPI_I2SCFGR_DATFMT_Msk                     /*!<Data format                                       */

+#define SPI_I2SCFGR_I2SDIV_Pos      (16U)

+#define SPI_I2SCFGR_I2SDIV_Msk      (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)         /*!< 0x00FF0000 */

+#define SPI_I2SCFGR_I2SDIV          SPI_I2SCFGR_I2SDIV_Msk                     /*!<I2S Linear prescaler */

+#define SPI_I2SCFGR_ODD_Pos         (24U)

+#define SPI_I2SCFGR_ODD_Msk         (0x1UL << SPI_I2SCFGR_ODD_Pos)             /*!< 0x01000000 */

+#define SPI_I2SCFGR_ODD             SPI_I2SCFGR_ODD_Msk                        /*!<Odd factor for the prescaler */

+#define SPI_I2SCFGR_MCKOE_Pos       (25U)

+#define SPI_I2SCFGR_MCKOE_Msk       (0x1UL << SPI_I2SCFGR_MCKOE_Pos)           /*!< 0x02000000 */

+#define SPI_I2SCFGR_MCKOE           SPI_I2SCFGR_MCKOE_Msk                      /*!<Master Clock Output Enable */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    QUADSPI                                 */

+/*                                                                            */

+/******************************************************************************/

+/*****************  Bit definition for QUADSPI_CR register  *******************/

+#define QUADSPI_CR_EN_Pos                (0U)

+#define QUADSPI_CR_EN_Msk                (0x1UL << QUADSPI_CR_EN_Pos)          /*!< 0x00000001 */

+#define QUADSPI_CR_EN                    QUADSPI_CR_EN_Msk                     /*!< Enable */

+#define QUADSPI_CR_ABORT_Pos             (1U)

+#define QUADSPI_CR_ABORT_Msk             (0x1UL << QUADSPI_CR_ABORT_Pos)       /*!< 0x00000002 */

+#define QUADSPI_CR_ABORT                 QUADSPI_CR_ABORT_Msk                  /*!< Abort request */

+#define QUADSPI_CR_DMAEN_Pos             (2U)

+#define QUADSPI_CR_DMAEN_Msk             (0x1UL << QUADSPI_CR_DMAEN_Pos)       /*!< 0x00000004 */

+#define QUADSPI_CR_DMAEN                 QUADSPI_CR_DMAEN_Msk                  /*!< DMA Enable */

+#define QUADSPI_CR_TCEN_Pos              (3U)

+#define QUADSPI_CR_TCEN_Msk              (0x1UL << QUADSPI_CR_TCEN_Pos)        /*!< 0x00000008 */

+#define QUADSPI_CR_TCEN                  QUADSPI_CR_TCEN_Msk                   /*!< Timeout Counter Enable */

+#define QUADSPI_CR_SSHIFT_Pos            (4U)

+#define QUADSPI_CR_SSHIFT_Msk            (0x1UL << QUADSPI_CR_SSHIFT_Pos)      /*!< 0x00000010 */

+#define QUADSPI_CR_SSHIFT                QUADSPI_CR_SSHIFT_Msk                 /*!< SSHIFT Sample Shift */

+#define QUADSPI_CR_DFM_Pos               (6U)

+#define QUADSPI_CR_DFM_Msk               (0x1UL << QUADSPI_CR_DFM_Pos)         /*!< 0x00000040 */

+#define QUADSPI_CR_DFM                   QUADSPI_CR_DFM_Msk                    /*!< Dual Flash Mode */

+#define QUADSPI_CR_FSEL_Pos              (7U)

+#define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)        /*!< 0x00000080 */

+#define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select */

+#define QUADSPI_CR_FTHRES_Pos            (8U)

+#define QUADSPI_CR_FTHRES_Msk            (0xFUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000F00 */

+#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level */

+#define QUADSPI_CR_FTHRES_0              (0x1UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */

+#define QUADSPI_CR_FTHRES_1              (0x2UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */

+#define QUADSPI_CR_FTHRES_2              (0x4UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */

+#define QUADSPI_CR_FTHRES_3              (0x8UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */

+#define QUADSPI_CR_TEIE_Pos              (16U)

+#define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)        /*!< 0x00010000 */

+#define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable */

+#define QUADSPI_CR_TCIE_Pos              (17U)

+#define QUADSPI_CR_TCIE_Msk              (0x1UL << QUADSPI_CR_TCIE_Pos)        /*!< 0x00020000 */

+#define QUADSPI_CR_TCIE                  QUADSPI_CR_TCIE_Msk                   /*!< Transfer Complete Interrupt Enable */

+#define QUADSPI_CR_FTIE_Pos              (18U)

+#define QUADSPI_CR_FTIE_Msk              (0x1UL << QUADSPI_CR_FTIE_Pos)        /*!< 0x00040000 */

+#define QUADSPI_CR_FTIE                  QUADSPI_CR_FTIE_Msk                   /*!< FIFO Threshold Interrupt Enable */

+#define QUADSPI_CR_SMIE_Pos              (19U)

+#define QUADSPI_CR_SMIE_Msk              (0x1UL << QUADSPI_CR_SMIE_Pos)        /*!< 0x00080000 */

+#define QUADSPI_CR_SMIE                  QUADSPI_CR_SMIE_Msk                   /*!< Status Match Interrupt Enable */

+#define QUADSPI_CR_TOIE_Pos              (20U)

+#define QUADSPI_CR_TOIE_Msk              (0x1UL << QUADSPI_CR_TOIE_Pos)        /*!< 0x00100000 */

+#define QUADSPI_CR_TOIE                  QUADSPI_CR_TOIE_Msk                   /*!< TimeOut Interrupt Enable */

+#define QUADSPI_CR_APMS_Pos              (22U)

+#define QUADSPI_CR_APMS_Msk              (0x1UL << QUADSPI_CR_APMS_Pos)        /*!< 0x00400000 */

+#define QUADSPI_CR_APMS                  QUADSPI_CR_APMS_Msk                   /*!< Bit 1 */

+#define QUADSPI_CR_PMM_Pos               (23U)

+#define QUADSPI_CR_PMM_Msk               (0x1UL << QUADSPI_CR_PMM_Pos)         /*!< 0x00800000 */

+#define QUADSPI_CR_PMM                   QUADSPI_CR_PMM_Msk                    /*!< Polling Match Mode */

+#define QUADSPI_CR_PRESCALER_Pos         (24U)

+#define QUADSPI_CR_PRESCALER_Msk         (0xFFUL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0xFF000000 */

+#define QUADSPI_CR_PRESCALER             QUADSPI_CR_PRESCALER_Msk              /*!< PRESCALER[7:0] Clock prescaler */

+#define QUADSPI_CR_PRESCALER_0           (0x01UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x01000000 */

+#define QUADSPI_CR_PRESCALER_1           (0x02UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x02000000 */

+#define QUADSPI_CR_PRESCALER_2           (0x04UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x04000000 */

+#define QUADSPI_CR_PRESCALER_3           (0x08UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x08000000 */

+#define QUADSPI_CR_PRESCALER_4           (0x10UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x10000000 */

+#define QUADSPI_CR_PRESCALER_5           (0x20UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x20000000 */

+#define QUADSPI_CR_PRESCALER_6           (0x40UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x40000000 */

+#define QUADSPI_CR_PRESCALER_7           (0x80UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x80000000 */

+

+/*****************  Bit definition for QUADSPI_DCR register  ******************/

+#define QUADSPI_DCR_CKMODE_Pos           (0U)

+#define QUADSPI_DCR_CKMODE_Msk           (0x1UL << QUADSPI_DCR_CKMODE_Pos)     /*!< 0x00000001 */

+#define QUADSPI_DCR_CKMODE               QUADSPI_DCR_CKMODE_Msk                /*!< Mode 0 / Mode 3 */

+#define QUADSPI_DCR_CSHT_Pos             (8U)

+#define QUADSPI_DCR_CSHT_Msk             (0x7UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000700 */

+#define QUADSPI_DCR_CSHT                 QUADSPI_DCR_CSHT_Msk                  /*!< CSHT[2:0]: ChipSelect High Time */

+#define QUADSPI_DCR_CSHT_0               (0x1UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000100 */

+#define QUADSPI_DCR_CSHT_1               (0x2UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000200 */

+#define QUADSPI_DCR_CSHT_2               (0x4UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000400 */

+#define QUADSPI_DCR_FSIZE_Pos            (16U)

+#define QUADSPI_DCR_FSIZE_Msk            (0x1FUL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x001F0000 */

+#define QUADSPI_DCR_FSIZE                QUADSPI_DCR_FSIZE_Msk                 /*!< FSIZE[4:0]: Flash Size */

+#define QUADSPI_DCR_FSIZE_0              (0x01UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00010000 */

+#define QUADSPI_DCR_FSIZE_1              (0x02UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00020000 */

+#define QUADSPI_DCR_FSIZE_2              (0x04UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00040000 */

+#define QUADSPI_DCR_FSIZE_3              (0x08UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00080000 */

+#define QUADSPI_DCR_FSIZE_4              (0x10UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00100000 */

+

+/******************  Bit definition for QUADSPI_SR register  *******************/

+#define QUADSPI_SR_TEF_Pos               (0U)

+#define QUADSPI_SR_TEF_Msk               (0x1UL << QUADSPI_SR_TEF_Pos)         /*!< 0x00000001 */

+#define QUADSPI_SR_TEF                   QUADSPI_SR_TEF_Msk                    /*!< Transfer Error Flag */

+#define QUADSPI_SR_TCF_Pos               (1U)

+#define QUADSPI_SR_TCF_Msk               (0x1UL << QUADSPI_SR_TCF_Pos)         /*!< 0x00000002 */

+#define QUADSPI_SR_TCF                   QUADSPI_SR_TCF_Msk                    /*!< Transfer Complete Flag */

+#define QUADSPI_SR_FTF_Pos               (2U)

+#define QUADSPI_SR_FTF_Msk               (0x1UL << QUADSPI_SR_FTF_Pos)         /*!< 0x00000004 */

+#define QUADSPI_SR_FTF                   QUADSPI_SR_FTF_Msk                    /*!< FIFO Threshlod Flag */

+#define QUADSPI_SR_SMF_Pos               (3U)

+#define QUADSPI_SR_SMF_Msk               (0x1UL << QUADSPI_SR_SMF_Pos)         /*!< 0x00000008 */

+#define QUADSPI_SR_SMF                   QUADSPI_SR_SMF_Msk                    /*!< Status Match Flag */

+#define QUADSPI_SR_TOF_Pos               (4U)

+#define QUADSPI_SR_TOF_Msk               (0x1UL << QUADSPI_SR_TOF_Pos)         /*!< 0x00000010 */

+#define QUADSPI_SR_TOF                   QUADSPI_SR_TOF_Msk                    /*!< Timeout Flag */

+#define QUADSPI_SR_BUSY_Pos              (5U)

+#define QUADSPI_SR_BUSY_Msk              (0x1UL << QUADSPI_SR_BUSY_Pos)        /*!< 0x00000020 */

+#define QUADSPI_SR_BUSY                  QUADSPI_SR_BUSY_Msk                   /*!< Busy */

+#define QUADSPI_SR_FLEVEL_Pos            (8U)

+#define QUADSPI_SR_FLEVEL_Msk            (0x3FUL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00003F00 */

+#define QUADSPI_SR_FLEVEL                QUADSPI_SR_FLEVEL_Msk                 /*!< FIFO Threshlod Flag */

+#define QUADSPI_SR_FLEVEL_0              (0x01UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000100 */

+#define QUADSPI_SR_FLEVEL_1              (0x02UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000200 */

+#define QUADSPI_SR_FLEVEL_2              (0x04UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000400 */

+#define QUADSPI_SR_FLEVEL_3              (0x08UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000800 */

+#define QUADSPI_SR_FLEVEL_4              (0x10UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00001000 */

+#define QUADSPI_SR_FLEVEL_5              (0x20UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00002000 */

+

+/******************  Bit definition for QUADSPI_FCR register  ******************/

+#define QUADSPI_FCR_CTEF_Pos             (0U)

+#define QUADSPI_FCR_CTEF_Msk             (0x1UL << QUADSPI_FCR_CTEF_Pos)       /*!< 0x00000001 */

+#define QUADSPI_FCR_CTEF                 QUADSPI_FCR_CTEF_Msk                  /*!< Clear Transfer Error Flag */

+#define QUADSPI_FCR_CTCF_Pos             (1U)

+#define QUADSPI_FCR_CTCF_Msk             (0x1UL << QUADSPI_FCR_CTCF_Pos)       /*!< 0x00000002 */

+#define QUADSPI_FCR_CTCF                 QUADSPI_FCR_CTCF_Msk                  /*!< Clear Transfer Complete Flag */

+#define QUADSPI_FCR_CSMF_Pos             (3U)

+#define QUADSPI_FCR_CSMF_Msk             (0x1UL << QUADSPI_FCR_CSMF_Pos)       /*!< 0x00000008 */

+#define QUADSPI_FCR_CSMF                 QUADSPI_FCR_CSMF_Msk                  /*!< Clear Status Match Flag */

+#define QUADSPI_FCR_CTOF_Pos             (4U)

+#define QUADSPI_FCR_CTOF_Msk             (0x1UL << QUADSPI_FCR_CTOF_Pos)       /*!< 0x00000010 */

+#define QUADSPI_FCR_CTOF                 QUADSPI_FCR_CTOF_Msk                  /*!< Clear Timeout Flag */

+

+/******************  Bit definition for QUADSPI_DLR register  ******************/

+#define QUADSPI_DLR_DL_Pos               (0U)

+#define QUADSPI_DLR_DL_Msk               (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)  /*!< 0xFFFFFFFF */

+#define QUADSPI_DLR_DL                   QUADSPI_DLR_DL_Msk                    /*!< DL[31:0]: Data Length */

+

+/******************  Bit definition for QUADSPI_CCR register  ******************/

+#define QUADSPI_CCR_INSTRUCTION_Pos      (0U)

+#define QUADSPI_CCR_INSTRUCTION_Msk      (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */

+#define QUADSPI_CCR_INSTRUCTION          QUADSPI_CCR_INSTRUCTION_Msk             /*!< INSTRUCTION[7:0]: Instruction */

+#define QUADSPI_CCR_INSTRUCTION_0        (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */

+#define QUADSPI_CCR_INSTRUCTION_1        (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */

+#define QUADSPI_CCR_INSTRUCTION_2        (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */

+#define QUADSPI_CCR_INSTRUCTION_3        (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */

+#define QUADSPI_CCR_INSTRUCTION_4        (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */

+#define QUADSPI_CCR_INSTRUCTION_5        (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */

+#define QUADSPI_CCR_INSTRUCTION_6        (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */

+#define QUADSPI_CCR_INSTRUCTION_7        (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */

+#define QUADSPI_CCR_IMODE_Pos            (8U)

+#define QUADSPI_CCR_IMODE_Msk            (0x3UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000300 */

+#define QUADSPI_CCR_IMODE                QUADSPI_CCR_IMODE_Msk                   /*!< IMODE[1:0]: Instruction Mode */

+#define QUADSPI_CCR_IMODE_0              (0x1UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000100 */

+#define QUADSPI_CCR_IMODE_1              (0x2UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000200 */

+#define QUADSPI_CCR_ADMODE_Pos           (10U)

+#define QUADSPI_CCR_ADMODE_Msk           (0x3UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000C00 */

+#define QUADSPI_CCR_ADMODE               QUADSPI_CCR_ADMODE_Msk                  /*!< ADMODE[1:0]: Address Mode */

+#define QUADSPI_CCR_ADMODE_0             (0x1UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000400 */

+#define QUADSPI_CCR_ADMODE_1             (0x2UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000800 */

+#define QUADSPI_CCR_ADSIZE_Pos           (12U)

+#define QUADSPI_CCR_ADSIZE_Msk           (0x3UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00003000 */

+#define QUADSPI_CCR_ADSIZE               QUADSPI_CCR_ADSIZE_Msk                  /*!< ADSIZE[1:0]: Address Size */

+#define QUADSPI_CCR_ADSIZE_0             (0x1UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00001000 */

+#define QUADSPI_CCR_ADSIZE_1             (0x2UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00002000 */

+#define QUADSPI_CCR_ABMODE_Pos           (14U)

+#define QUADSPI_CCR_ABMODE_Msk           (0x3UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x0000C000 */

+#define QUADSPI_CCR_ABMODE               QUADSPI_CCR_ABMODE_Msk                  /*!< ABMODE[1:0]: Alternate Bytes Mode */

+#define QUADSPI_CCR_ABMODE_0             (0x1UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00004000 */

+#define QUADSPI_CCR_ABMODE_1             (0x2UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00008000 */

+#define QUADSPI_CCR_ABSIZE_Pos           (16U)

+#define QUADSPI_CCR_ABSIZE_Msk           (0x3UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00030000 */

+#define QUADSPI_CCR_ABSIZE               QUADSPI_CCR_ABSIZE_Msk                  /*!< ABSIZE[1:0]: Instruction Mode */

+#define QUADSPI_CCR_ABSIZE_0             (0x1UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00010000 */

+#define QUADSPI_CCR_ABSIZE_1             (0x2UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00020000 */

+#define QUADSPI_CCR_DCYC_Pos             (18U)

+#define QUADSPI_CCR_DCYC_Msk             (0x1FUL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x007C0000 */

+#define QUADSPI_CCR_DCYC                 QUADSPI_CCR_DCYC_Msk                    /*!< DCYC[4:0]: Dummy Cycles */

+#define QUADSPI_CCR_DCYC_0               (0x01UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00040000 */

+#define QUADSPI_CCR_DCYC_1               (0x02UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00080000 */

+#define QUADSPI_CCR_DCYC_2               (0x04UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00100000 */

+#define QUADSPI_CCR_DCYC_3               (0x08UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00200000 */

+#define QUADSPI_CCR_DCYC_4               (0x10UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00400000 */

+#define QUADSPI_CCR_DMODE_Pos            (24U)

+#define QUADSPI_CCR_DMODE_Msk            (0x3UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x03000000 */

+#define QUADSPI_CCR_DMODE                QUADSPI_CCR_DMODE_Msk                   /*!< DMODE[1:0]: Data Mode */

+#define QUADSPI_CCR_DMODE_0              (0x1UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x01000000 */

+#define QUADSPI_CCR_DMODE_1              (0x2UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x02000000 */

+#define QUADSPI_CCR_FMODE_Pos            (26U)

+#define QUADSPI_CCR_FMODE_Msk            (0x3UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x0C000000 */

+#define QUADSPI_CCR_FMODE                QUADSPI_CCR_FMODE_Msk                   /*!< FMODE[1:0]: Functional Mode */

+#define QUADSPI_CCR_FMODE_0              (0x1UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x04000000 */

+#define QUADSPI_CCR_FMODE_1              (0x2UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x08000000 */

+#define QUADSPI_CCR_SIOO_Pos             (28U)

+#define QUADSPI_CCR_SIOO_Msk             (0x1UL << QUADSPI_CCR_SIOO_Pos)         /*!< 0x10000000 */

+#define QUADSPI_CCR_SIOO                 QUADSPI_CCR_SIOO_Msk                    /*!< SIOO: Send Instruction Only Once Mode */

+#define QUADSPI_CCR_DHHC_Pos             (30U)

+#define QUADSPI_CCR_DHHC_Msk             (0x1UL << QUADSPI_CCR_DHHC_Pos)         /*!< 0x40000000 */

+#define QUADSPI_CCR_DHHC                 QUADSPI_CCR_DHHC_Msk                    /*!< DHHC: DDR hold half cycle */

+#define QUADSPI_CCR_DDRM_Pos             (31U)

+#define QUADSPI_CCR_DDRM_Msk             (0x1UL << QUADSPI_CCR_DDRM_Pos)         /*!< 0x80000000 */

+#define QUADSPI_CCR_DDRM                 QUADSPI_CCR_DDRM_Msk                    /*!< DDRM: Double Data Rate Mode */

+

+/******************  Bit definition for QUADSPI_AR register  *******************/

+#define QUADSPI_AR_ADDRESS_Pos           (0U)

+#define QUADSPI_AR_ADDRESS_Msk           (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_AR_ADDRESS               QUADSPI_AR_ADDRESS_Msk                /*!< ADDRESS[31:0]: Address */

+

+/******************  Bit definition for QUADSPI_ABR register  ******************/

+#define QUADSPI_ABR_ALTERNATE_Pos        (0U)

+#define QUADSPI_ABR_ALTERNATE_Msk        (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_ABR_ALTERNATE            QUADSPI_ABR_ALTERNATE_Msk             /*!< ALTERNATE[31:0]: Alternate Bytes */

+

+/******************  Bit definition for QUADSPI_DR register  *******************/

+#define QUADSPI_DR_DATA_Pos              (0U)

+#define QUADSPI_DR_DATA_Msk              (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_DR_DATA                  QUADSPI_DR_DATA_Msk                   /*!< DATA[31:0]: Data */

+

+/******************  Bit definition for QUADSPI_PSMKR register  ****************/

+#define QUADSPI_PSMKR_MASK_Pos           (0U)

+#define QUADSPI_PSMKR_MASK_Msk           (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_PSMKR_MASK               QUADSPI_PSMKR_MASK_Msk                /*!< MASK[31:0]: Status Mask */

+

+/******************  Bit definition for QUADSPI_PSMAR register  ****************/

+#define QUADSPI_PSMAR_MATCH_Pos          (0U)

+#define QUADSPI_PSMAR_MATCH_Msk          (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_PSMAR_MATCH              QUADSPI_PSMAR_MATCH_Msk               /*!< MATCH[31:0]: Status Match */

+

+/******************  Bit definition for QUADSPI_PIR register  *****************/

+#define QUADSPI_PIR_INTERVAL_Pos         (0U)

+#define QUADSPI_PIR_INTERVAL_Msk         (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */

+#define QUADSPI_PIR_INTERVAL             QUADSPI_PIR_INTERVAL_Msk              /*!< INTERVAL[15:0]: Polling Interval */

+

+/******************  Bit definition for QUADSPI_LPTR register  *****************/

+#define QUADSPI_LPTR_TIMEOUT_Pos         (0U)

+#define QUADSPI_LPTR_TIMEOUT_Msk         (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */

+#define QUADSPI_LPTR_TIMEOUT             QUADSPI_LPTR_TIMEOUT_Msk              /*!< TIMEOUT[15:0]: Timeout period */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                 SYSCFG                                     */

+/*                                                                            */

+/******************************************************************************/

+

+/******************  Bit definition for SYSCFG_PMCR register  ******************/

+#define SYSCFG_PMCR_I2C1_FMP_Pos        (0U)

+#define SYSCFG_PMCR_I2C1_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos)    /*!< 0x00000001 */

+#define SYSCFG_PMCR_I2C1_FMP            SYSCFG_PMCR_I2C1_FMP_Msk               /*!< I2C1 Fast mode plus */

+#define SYSCFG_PMCR_I2C2_FMP_Pos        (1U)

+#define SYSCFG_PMCR_I2C2_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos)    /*!< 0x00000002 */

+#define SYSCFG_PMCR_I2C2_FMP            SYSCFG_PMCR_I2C2_FMP_Msk               /*!< I2C2 Fast mode plus */

+#define SYSCFG_PMCR_I2C3_FMP_Pos        (2U)

+#define SYSCFG_PMCR_I2C3_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos)    /*!< 0x00000004 */

+#define SYSCFG_PMCR_I2C3_FMP            SYSCFG_PMCR_I2C3_FMP_Msk               /*!< I2C3 Fast mode plus */

+#define SYSCFG_PMCR_I2C4_FMP_Pos        (3U)

+#define SYSCFG_PMCR_I2C4_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos)    /*!< 0x00000008 */

+#define SYSCFG_PMCR_I2C4_FMP            SYSCFG_PMCR_I2C4_FMP_Msk               /*!< I2C4 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB6_FMP_Pos     (4U)

+#define SYSCFG_PMCR_I2C_PB6_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */

+#define SYSCFG_PMCR_I2C_PB6_FMP         SYSCFG_PMCR_I2C_PB6_FMP_Msk            /*!< I2C PB6 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB7_FMP_Pos     (5U)

+#define SYSCFG_PMCR_I2C_PB7_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */

+#define SYSCFG_PMCR_I2C_PB7_FMP         SYSCFG_PMCR_I2C_PB7_FMP_Msk            /*!< I2C PB7 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB8_FMP_Pos     (6U)

+#define SYSCFG_PMCR_I2C_PB8_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */

+#define SYSCFG_PMCR_I2C_PB8_FMP         SYSCFG_PMCR_I2C_PB8_FMP_Msk            /*!< I2C PB8 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB9_FMP_Pos     (7U)

+#define SYSCFG_PMCR_I2C_PB9_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */

+#define SYSCFG_PMCR_I2C_PB9_FMP         SYSCFG_PMCR_I2C_PB9_FMP_Msk            /*!< I2C PB9 Fast mode plus */

+#define SYSCFG_PMCR_BOOSTEN_Pos         (8U)

+#define SYSCFG_PMCR_BOOSTEN_Msk         (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos)     /*!< 0x00000100 */

+#define SYSCFG_PMCR_BOOSTEN             SYSCFG_PMCR_BOOSTEN_Msk                /*!< I/O analog switch voltage booster enable */

+

+#define SYSCFG_PMCR_BOOSTVDDSEL_Pos     (9U)

+#define SYSCFG_PMCR_BOOSTVDDSEL_Msk     (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos) /*!< 0x00000200 */

+#define SYSCFG_PMCR_BOOSTVDDSEL         SYSCFG_PMCR_BOOSTVDDSEL_Msk            /*!< Analog switch supply source selection : VDD/VDDA */

+

+#define SYSCFG_PMCR_EPIS_SEL_Pos        (21U)

+#define SYSCFG_PMCR_EPIS_SEL_Msk        (0x7UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00E00000 */

+#define SYSCFG_PMCR_EPIS_SEL            SYSCFG_PMCR_EPIS_SEL_Msk               /*!< Ethernet PHY Interface Selection */

+#define SYSCFG_PMCR_EPIS_SEL_0          (0x1UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00200000 */

+#define SYSCFG_PMCR_EPIS_SEL_1          (0x2UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00400000 */

+#define SYSCFG_PMCR_EPIS_SEL_2          (0x4UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00800000 */

+#define SYSCFG_PMCR_PA0SO_Pos           (24U)

+#define SYSCFG_PMCR_PA0SO_Msk           (0x1UL << SYSCFG_PMCR_PA0SO_Pos)       /*!< 0x01000000 */

+#define SYSCFG_PMCR_PA0SO               SYSCFG_PMCR_PA0SO_Msk                  /*!< PA0 Switch Open */

+#define SYSCFG_PMCR_PA1SO_Pos           (25U)

+#define SYSCFG_PMCR_PA1SO_Msk           (0x1UL << SYSCFG_PMCR_PA1SO_Pos)       /*!< 0x02000000 */

+#define SYSCFG_PMCR_PA1SO               SYSCFG_PMCR_PA1SO_Msk                  /*!< PA1 Switch Open */

+#define SYSCFG_PMCR_PC2SO_Pos           (26U)

+#define SYSCFG_PMCR_PC2SO_Msk           (0x1UL << SYSCFG_PMCR_PC2SO_Pos)       /*!< 0x04000000 */

+#define SYSCFG_PMCR_PC2SO               SYSCFG_PMCR_PC2SO_Msk                  /*!< PC2 Switch Open */

+#define SYSCFG_PMCR_PC3SO_Pos           (27U)

+#define SYSCFG_PMCR_PC3SO_Msk           (0x1UL << SYSCFG_PMCR_PC3SO_Pos)       /*!< 0x08000000 */

+#define SYSCFG_PMCR_PC3SO               SYSCFG_PMCR_PC3SO_Msk                  /*!< PC3 Switch Open */

+

+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/

+#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)

+#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */

+#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)

+#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */

+#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)

+#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000F00 */

+#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */

+#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)

+#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x0000F000 */

+#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */

+/**

+  * @brief   EXTI0 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */

+

+/**

+  * @brief   EXTI1 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */

+/**

+  * @brief   EXTI2 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */

+

+/**

+  * @brief   EXTI3 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/

+#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)

+#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */

+#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)

+#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */

+#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)

+#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000F00 */

+#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */

+#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)

+#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x0000F000 */

+#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */

+/**

+  * @brief   EXTI4 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */

+/**

+  * @brief   EXTI5 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */

+/**

+  * @brief   EXTI6 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */

+

+/**

+  * @brief   EXTI7 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/

+#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)

+#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */

+#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)

+#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */

+#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)

+#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000F00 */

+#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */

+#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)

+#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x0000F000 */

+#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */

+

+/**

+  * @brief   EXTI8 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */

+

+/**

+  * @brief   EXTI9 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */

+

+/**

+  * @brief   EXTI10 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */

+

+/**

+  * @brief   EXTI11 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/

+#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)

+#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x0000000F */

+#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */

+#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)

+#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x000000F0 */

+#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */

+#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)

+#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000F00 */

+#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */

+#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)

+#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x0000F000 */

+#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */

+/**

+  * @brief   EXTI12 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */

+/**

+  * @brief   EXTI13 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */

+/**

+  * @brief   EXTI14 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */

+/**

+  * @brief   EXTI15 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */

+

+/******************  Bit definition for SYSCFG_CFGR register  ******************/

+#define SYSCFG_CFGR_PVDL_Pos            (2U)

+#define SYSCFG_CFGR_PVDL_Msk            (0x1UL << SYSCFG_CFGR_PVDL_Pos)        /*!< 0x00000004 */

+#define SYSCFG_CFGR_PVDL                SYSCFG_CFGR_PVDL_Msk                   /*!<PVD lock enable bit */

+#define SYSCFG_CFGR_FLASHL_Pos          (3U)

+#define SYSCFG_CFGR_FLASHL_Msk          (0x1UL << SYSCFG_CFGR_FLASHL_Pos)      /*!< 0x00000008 */

+#define SYSCFG_CFGR_FLASHL              SYSCFG_CFGR_FLASHL_Msk                 /*!<FLASH double ECC error lock bit */

+#define SYSCFG_CFGR_CM7L_Pos            (6U)

+#define SYSCFG_CFGR_CM7L_Msk            (0x1UL << SYSCFG_CFGR_CM7L_Pos)        /*!< 0x00000040 */

+#define SYSCFG_CFGR_CM7L                SYSCFG_CFGR_CM7L_Msk                   /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */

+#define SYSCFG_CFGR_BKRAML_Pos          (7U)

+#define SYSCFG_CFGR_BKRAML_Msk          (0x1UL << SYSCFG_CFGR_BKRAML_Pos)      /*!< 0x00000080 */

+#define SYSCFG_CFGR_BKRAML              SYSCFG_CFGR_BKRAML_Msk                 /*!<Backup SRAM double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM4L_Pos          (9U)

+#define SYSCFG_CFGR_SRAM4L_Msk          (0x1UL << SYSCFG_CFGR_SRAM4L_Pos)      /*!< 0x00000200 */

+#define SYSCFG_CFGR_SRAM4L              SYSCFG_CFGR_SRAM4L_Msk                 /*!<SRAM4 double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM3L_Pos          (10U)

+#define SYSCFG_CFGR_SRAM3L_Msk          (0x1UL << SYSCFG_CFGR_SRAM3L_Pos)      /*!< 0x00000400 */

+#define SYSCFG_CFGR_SRAM3L              SYSCFG_CFGR_SRAM3L_Msk                 /*!<SRAM3 double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM2L_Pos          (11U)

+#define SYSCFG_CFGR_SRAM2L_Msk          (0x1UL << SYSCFG_CFGR_SRAM2L_Pos)      /*!< 0x00000800 */

+#define SYSCFG_CFGR_SRAM2L              SYSCFG_CFGR_SRAM2L_Msk                 /*!<SRAM2 double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM1L_Pos          (12U)

+#define SYSCFG_CFGR_SRAM1L_Msk          (0x1UL << SYSCFG_CFGR_SRAM1L_Pos)      /*!< 0x00001000 */

+#define SYSCFG_CFGR_SRAM1L              SYSCFG_CFGR_SRAM1L_Msk                 /*!<SRAM1 double ECC error lock bit */

+#define SYSCFG_CFGR_DTCML_Pos           (13U)

+#define SYSCFG_CFGR_DTCML_Msk           (0x1UL << SYSCFG_CFGR_DTCML_Pos)       /*!< 0x00002000 */

+#define SYSCFG_CFGR_DTCML               SYSCFG_CFGR_DTCML_Msk                  /*!<DTCM double ECC error lock bit */

+#define SYSCFG_CFGR_ITCML_Pos           (14U)

+#define SYSCFG_CFGR_ITCML_Msk           (0x1UL << SYSCFG_CFGR_ITCML_Pos)       /*!< 0x00004000 */

+#define SYSCFG_CFGR_ITCML               SYSCFG_CFGR_ITCML_Msk                  /*!<ITCM double ECC error lock bit */

+#define SYSCFG_CFGR_AXISRAML_Pos        (15U)

+#define SYSCFG_CFGR_AXISRAML_Msk        (0x1UL << SYSCFG_CFGR_AXISRAML_Pos)    /*!< 0x00008000 */

+#define SYSCFG_CFGR_AXISRAML            SYSCFG_CFGR_AXISRAML_Msk               /*!<AXISRAM double ECC error lock bit */

+

+/******************  Bit definition for SYSCFG_CCCSR register  ******************/

+#define SYSCFG_CCCSR_EN_Pos             (0U)

+#define SYSCFG_CCCSR_EN_Msk             (0x1UL << SYSCFG_CCCSR_EN_Pos)         /*!< 0x00000001 */

+#define SYSCFG_CCCSR_EN                 SYSCFG_CCCSR_EN_Msk                    /*!< I/O compensation cell enable */

+#define SYSCFG_CCCSR_CS_Pos             (1U)

+#define SYSCFG_CCCSR_CS_Msk             (0x1UL << SYSCFG_CCCSR_CS_Pos)         /*!< 0x00000002 */

+#define SYSCFG_CCCSR_CS                 SYSCFG_CCCSR_CS_Msk                    /*!< I/O compensation cell code selection */

+#define SYSCFG_CCCSR_READY_Pos          (8U)

+#define SYSCFG_CCCSR_READY_Msk          (0x1UL << SYSCFG_CCCSR_READY_Pos)      /*!< 0x00000100 */

+#define SYSCFG_CCCSR_READY              SYSCFG_CCCSR_READY_Msk                 /*!< I/O compensation cell ready flag */

+#define SYSCFG_CCCSR_HSLV_Pos           (16U)

+#define SYSCFG_CCCSR_HSLV_Msk           (0x1UL << SYSCFG_CCCSR_HSLV_Pos)       /*!< 0x00010000 */

+#define SYSCFG_CCCSR_HSLV               SYSCFG_CCCSR_HSLV_Msk                  /*!< High-speed at low-voltage */

+

+/******************  Bit definition for SYSCFG_CCVR register  *******************/

+#define SYSCFG_CCVR_NCV_Pos             (0U)

+#define SYSCFG_CCVR_NCV_Msk             (0xFUL << SYSCFG_CCVR_NCV_Pos)         /*!< 0x0000000F */

+#define SYSCFG_CCVR_NCV                 SYSCFG_CCVR_NCV_Msk                    /*!< NMOS compensation value */

+#define SYSCFG_CCVR_PCV_Pos             (4U)

+#define SYSCFG_CCVR_PCV_Msk             (0xFUL << SYSCFG_CCVR_PCV_Pos)         /*!< 0x000000F0 */

+#define SYSCFG_CCVR_PCV                 SYSCFG_CCVR_PCV_Msk                    /*!< PMOS compensation value */

+

+/******************  Bit definition for SYSCFG_CCCR register  *******************/

+#define SYSCFG_CCCR_NCC_Pos             (0U)

+#define SYSCFG_CCCR_NCC_Msk             (0xFUL << SYSCFG_CCCR_NCC_Pos)         /*!< 0x0000000F */

+#define SYSCFG_CCCR_NCC                 SYSCFG_CCCR_NCC_Msk                    /*!< NMOS compensation code */

+#define SYSCFG_CCCR_PCC_Pos             (4U)

+#define SYSCFG_CCCR_PCC_Msk             (0xFUL << SYSCFG_CCCR_PCC_Pos)         /*!< 0x000000F0 */

+#define SYSCFG_CCCR_PCC                 SYSCFG_CCCR_PCC_Msk                    /*!< PMOS compensation code */

+/******************  Bit definition for SYSCFG_PWRCR register  *******************/

+#define SYSCFG_PWRCR_ODEN_Pos           (0U)

+#define SYSCFG_PWRCR_ODEN_Msk           (0x1UL << SYSCFG_PWRCR_ODEN_Pos)         /*!< 0x00000001 */

+#define SYSCFG_PWRCR_ODEN               SYSCFG_PWRCR_ODEN_Msk                    /*!< PWR overdrive enable */

+

+/******************  Bit definition for SYSCFG_PKGR register  *******************/

+#define SYSCFG_PKGR_PKG_Pos             (0U)

+#define SYSCFG_PKGR_PKG_Msk             (0xFUL << SYSCFG_PKGR_PKG_Pos)         /*!< 0x0000000F */

+#define SYSCFG_PKGR_PKG                 SYSCFG_PKGR_PKG_Msk                    /*!< Package type */

+

+/******************  Bit definition for SYSCFG_UR0 register  *******************/

+#define SYSCFG_UR0_BKS_Pos              (0U)

+#define SYSCFG_UR0_BKS_Msk              (0x1UL << SYSCFG_UR0_BKS_Pos)          /*!< 0x00000001 */

+#define SYSCFG_UR0_BKS                  SYSCFG_UR0_BKS_Msk                     /*!< Bank Swap */

+#define SYSCFG_UR0_RDP_Pos              (16U)

+#define SYSCFG_UR0_RDP_Msk              (0xFFUL << SYSCFG_UR0_RDP_Pos)         /*!< 0x00FF0000 */

+#define SYSCFG_UR0_RDP                  SYSCFG_UR0_RDP_Msk                     /*!< Readout protection */

+

+/******************  Bit definition for SYSCFG_UR2 register  *******************/

+#define SYSCFG_UR2_BORH_Pos             (0U)

+#define SYSCFG_UR2_BORH_Msk             (0x3UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000003 */

+#define SYSCFG_UR2_BORH                 SYSCFG_UR2_BORH_Msk                    /*!< Brown Out Reset High level */

+#define SYSCFG_UR2_BORH_0               (0x1UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000001 */

+#define SYSCFG_UR2_BORH_1               (0x2UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000002 */

+#define SYSCFG_UR2_BOOT_ADD0_Pos        (16U)

+#define SYSCFG_UR2_BOOT_ADD0_Msk        (0xFFFFUL << SYSCFG_UR2_BOOT_ADD0_Pos) /*!< 0xFFFF0000 */

+#define SYSCFG_UR2_BOOT_ADD0            SYSCFG_UR2_BOOT_ADD0_Msk               /*!< Core Boot Address 0 */

+/******************  Bit definition for SYSCFG_UR3 register  *******************/

+#define SYSCFG_UR3_BOOT_ADD1_Pos        (0U)

+#define SYSCFG_UR3_BOOT_ADD1_Msk        (0xFFFFUL << SYSCFG_UR3_BOOT_ADD1_Pos) /*!< 0x0000FFFF */

+#define SYSCFG_UR3_BOOT_ADD1            SYSCFG_UR3_BOOT_ADD1_Msk               /*!< Core Boot Address 1 */

+

+  /******************  Bit definition for SYSCFG_UR4 register  *******************/

+

+#define SYSCFG_UR4_MEPAD_BANK1_Pos      (16U)

+#define SYSCFG_UR4_MEPAD_BANK1_Msk      (0x1UL << SYSCFG_UR4_MEPAD_BANK1_Pos)  /*!< 0x00010000 */

+#define SYSCFG_UR4_MEPAD_BANK1          SYSCFG_UR4_MEPAD_BANK1_Msk             /*!< Mass Erase Protected Area Disabled for bank 1 */

+

+/******************  Bit definition for SYSCFG_UR5 register  *******************/

+#define SYSCFG_UR5_MESAD_BANK1_Pos      (0U)

+#define SYSCFG_UR5_MESAD_BANK1_Msk      (0x1UL << SYSCFG_UR5_MESAD_BANK1_Pos)  /*!< 0x00000001 */

+#define SYSCFG_UR5_MESAD_BANK1          SYSCFG_UR5_MESAD_BANK1_Msk             /*!< Mass erase secured area disabled for bank 1 */

+#define SYSCFG_UR5_WRPN_BANK1_Pos       (16U)

+#define SYSCFG_UR5_WRPN_BANK1_Msk       (0xFFUL << SYSCFG_UR5_WRPN_BANK1_Pos)  /*!< 0x00FF0000 */

+#define SYSCFG_UR5_WRPN_BANK1           SYSCFG_UR5_WRPN_BANK1_Msk              /*!< Write protection for flash bank 1 */

+

+/******************  Bit definition for SYSCFG_UR6 register  *******************/

+#define SYSCFG_UR6_PABEG_BANK1_Pos      (0U)

+#define SYSCFG_UR6_PABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PABEG_BANK1_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR6_PABEG_BANK1          SYSCFG_UR6_PABEG_BANK1_Msk             /*!< Protected area start address for bank 1 */

+#define SYSCFG_UR6_PAEND_BANK1_Pos      (16U)

+#define SYSCFG_UR6_PAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PAEND_BANK1_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR6_PAEND_BANK1          SYSCFG_UR6_PAEND_BANK1_Msk             /*!< Protected area end address for bank 1 */

+

+/******************  Bit definition for SYSCFG_UR7 register  *******************/

+#define SYSCFG_UR7_SABEG_BANK1_Pos      (0U)

+#define SYSCFG_UR7_SABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SABEG_BANK1_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR7_SABEG_BANK1          SYSCFG_UR7_SABEG_BANK1_Msk             /*!< Secured area start address for bank 1 */

+#define SYSCFG_UR7_SAEND_BANK1_Pos      (16U)

+#define SYSCFG_UR7_SAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SAEND_BANK1_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR7_SAEND_BANK1          SYSCFG_UR7_SAEND_BANK1_Msk             /*!< Secured area end address for bank 1 */

+

+/******************  Bit definition for SYSCFG_UR8 register  *******************/

+#define SYSCFG_UR8_MEPAD_BANK2_Pos      (0U)

+#define SYSCFG_UR8_MEPAD_BANK2_Msk      (0x1UL << SYSCFG_UR8_MEPAD_BANK2_Pos)  /*!< 0x00000001 */

+#define SYSCFG_UR8_MEPAD_BANK2          SYSCFG_UR8_MEPAD_BANK2_Msk             /*!< Mass erase Protected area disabled for bank 2 */

+#define SYSCFG_UR8_MESAD_BANK2_Pos      (16U)

+#define SYSCFG_UR8_MESAD_BANK2_Msk      (0x1UL << SYSCFG_UR8_MESAD_BANK2_Pos)  /*!< 0x00010000 */

+#define SYSCFG_UR8_MESAD_BANK2          SYSCFG_UR8_MESAD_BANK2_Msk             /*!< Mass Erase Secured Area Disabled for bank 2 */

+

+/******************  Bit definition for SYSCFG_UR9 register  *******************/

+#define SYSCFG_UR9_WRPN_BANK2_Pos       (0U)

+#define SYSCFG_UR9_WRPN_BANK2_Msk       (0xFFUL << SYSCFG_UR9_WRPN_BANK2_Pos)  /*!< 0x000000FF */

+#define SYSCFG_UR9_WRPN_BANK2           SYSCFG_UR9_WRPN_BANK2_Msk              /*!< Write protection for flash bank 2 */

+#define SYSCFG_UR9_PABEG_BANK2_Pos      (16U)

+#define SYSCFG_UR9_PABEG_BANK2_Msk      (0xFFFUL << SYSCFG_UR9_PABEG_BANK2_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR9_PABEG_BANK2          SYSCFG_UR9_PABEG_BANK2_Msk             /*!< Protected area start address for bank 2 */

+

+/******************  Bit definition for SYSCFG_UR10 register  *******************/

+#define SYSCFG_UR10_PAEND_BANK2_Pos     (0U)

+#define SYSCFG_UR10_PAEND_BANK2_Msk     (0xFFFUL << SYSCFG_UR10_PAEND_BANK2_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR10_PAEND_BANK2         SYSCFG_UR10_PAEND_BANK2_Msk            /*!< Protected area end address for bank 2 */

+#define SYSCFG_UR10_SABEG_BANK2_Pos     (16U)

+#define SYSCFG_UR10_SABEG_BANK2_Msk     (0xFFFUL << SYSCFG_UR10_SABEG_BANK2_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR10_SABEG_BANK2         SYSCFG_UR10_SABEG_BANK2_Msk            /*!< Secured area start address for bank 2 */

+

+/******************  Bit definition for SYSCFG_UR11 register  *******************/

+#define SYSCFG_UR11_SAEND_BANK2_Pos     (0U)

+#define SYSCFG_UR11_SAEND_BANK2_Msk     (0xFFFUL << SYSCFG_UR11_SAEND_BANK2_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR11_SAEND_BANK2         SYSCFG_UR11_SAEND_BANK2_Msk            /*!< Secured area end address for bank 2 */

+#define SYSCFG_UR11_IWDG1M_Pos          (16U)

+#define SYSCFG_UR11_IWDG1M_Msk          (0x1UL << SYSCFG_UR11_IWDG1M_Pos)      /*!< 0x00010000 */

+#define SYSCFG_UR11_IWDG1M              SYSCFG_UR11_IWDG1M_Msk                 /*!< Independent Watchdog 1 mode (SW or HW) */

+

+/******************  Bit definition for SYSCFG_UR12 register  *******************/

+

+#define SYSCFG_UR12_SECURE_Pos          (16U)

+#define SYSCFG_UR12_SECURE_Msk          (0x1UL << SYSCFG_UR12_SECURE_Pos)      /*!< 0x00010000 */

+#define SYSCFG_UR12_SECURE              SYSCFG_UR12_SECURE_Msk                 /*!< Secure mode status */

+

+/******************  Bit definition for SYSCFG_UR13 register  *******************/

+#define SYSCFG_UR13_SDRS_Pos            (0U)

+#define SYSCFG_UR13_SDRS_Msk            (0x3UL << SYSCFG_UR13_SDRS_Pos)        /*!< 0x00000003 */

+#define SYSCFG_UR13_SDRS                SYSCFG_UR13_SDRS_Msk                   /*!< Secured DTCM RAM Size */

+#define SYSCFG_UR13_D1SBRST_Pos         (16U)

+#define SYSCFG_UR13_D1SBRST_Msk         (0x1UL << SYSCFG_UR13_D1SBRST_Pos)     /*!< 0x00010000 */

+#define SYSCFG_UR13_D1SBRST             SYSCFG_UR13_D1SBRST_Msk                /*!< D1 Standby reset */

+

+/******************  Bit definition for SYSCFG_UR14 register  *******************/

+#define SYSCFG_UR14_D1STPRST_Pos        (0U)

+#define SYSCFG_UR14_D1STPRST_Msk        (0x1UL << SYSCFG_UR14_D1STPRST_Pos)    /*!< 0x00000001 */

+#define SYSCFG_UR14_D1STPRST            SYSCFG_UR14_D1STPRST_Msk               /*!< D1 Stop Reset */

+

+/******************  Bit definition for SYSCFG_UR15 register  *******************/

+#define SYSCFG_UR15_FZIWDGSTB_Pos       (16U)

+#define SYSCFG_UR15_FZIWDGSTB_Msk       (0x1UL << SYSCFG_UR15_FZIWDGSTB_Pos)   /*!< 0x00010000 */

+#define SYSCFG_UR15_FZIWDGSTB           SYSCFG_UR15_FZIWDGSTB_Msk              /*!< Freeze independent watchdogs in Standby mode */

+

+/******************  Bit definition for SYSCFG_UR16 register  *******************/

+#define SYSCFG_UR16_FZIWDGSTP_Pos       (0U)

+#define SYSCFG_UR16_FZIWDGSTP_Msk       (0x1UL << SYSCFG_UR16_FZIWDGSTP_Pos)   /*!< 0x00000001 */

+#define SYSCFG_UR16_FZIWDGSTP           SYSCFG_UR16_FZIWDGSTP_Msk              /*!< Freeze independent watchdogs in Stop mode */

+#define SYSCFG_UR16_PKP_Pos             (16U)

+#define SYSCFG_UR16_PKP_Msk             (0x1UL << SYSCFG_UR16_PKP_Pos)         /*!< 0x00010000 */

+#define SYSCFG_UR16_PKP                 SYSCFG_UR16_PKP_Msk                    /*!< Private key programmed */

+

+/******************  Bit definition for SYSCFG_UR17 register  *******************/

+#define SYSCFG_UR17_IOHSLV_Pos          (0U)

+#define SYSCFG_UR17_IOHSLV_Msk          (0x1UL << SYSCFG_UR17_IOHSLV_Pos)      /*!< 0x00000001 */

+#define SYSCFG_UR17_IOHSLV              SYSCFG_UR17_IOHSLV_Msk                 /*!< I/O high speed / low voltage */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    TIM                                     */

+/*                                                                            */

+/******************************************************************************/

+#define TIM_BREAK_INPUT_SUPPORT             /*!<TIM Break input feature */

+

+/*******************  Bit definition for TIM_CR1 register  ********************/

+#define TIM_CR1_CEN_Pos           (0U)

+#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */

+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */

+#define TIM_CR1_UDIS_Pos          (1U)

+#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */

+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */

+#define TIM_CR1_URS_Pos           (2U)

+#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */

+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */

+#define TIM_CR1_OPM_Pos           (3U)

+#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */

+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */

+#define TIM_CR1_DIR_Pos           (4U)

+#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */

+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */

+

+#define TIM_CR1_CMS_Pos           (5U)

+#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */

+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */

+#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */

+#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */

+

+#define TIM_CR1_ARPE_Pos          (7U)

+#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */

+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */

+

+#define TIM_CR1_CKD_Pos           (8U)

+#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */

+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */

+#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */

+#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */

+

+#define TIM_CR1_UIFREMAP_Pos      (11U)

+#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */

+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */

+

+/*******************  Bit definition for TIM_CR2 register  ********************/

+#define TIM_CR2_CCPC_Pos          (0U)

+#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */

+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */

+#define TIM_CR2_CCUS_Pos          (2U)

+#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */

+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */

+#define TIM_CR2_CCDS_Pos          (3U)

+#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */

+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */

+

+#define TIM_CR2_MMS_Pos           (4U)

+#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */

+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */

+#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */

+#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */

+#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */

+

+#define TIM_CR2_TI1S_Pos          (7U)

+#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */

+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */

+#define TIM_CR2_OIS1_Pos          (8U)

+#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */

+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */

+#define TIM_CR2_OIS1N_Pos         (9U)

+#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */

+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */

+#define TIM_CR2_OIS2_Pos          (10U)

+#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */

+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */

+#define TIM_CR2_OIS2N_Pos         (11U)

+#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */

+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */

+#define TIM_CR2_OIS3_Pos          (12U)

+#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */

+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */

+#define TIM_CR2_OIS3N_Pos         (13U)

+#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */

+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */

+#define TIM_CR2_OIS4_Pos          (14U)

+#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */

+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */

+#define TIM_CR2_OIS5_Pos          (16U)

+#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */

+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */

+#define TIM_CR2_OIS6_Pos          (17U)

+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */

+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */

+

+#define TIM_CR2_MMS2_Pos          (20U)

+#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */

+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */

+#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */

+#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */

+#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */

+#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */

+

+/*******************  Bit definition for TIM_SMCR register  *******************/

+#define TIM_SMCR_SMS_Pos          (0U)

+#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */

+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */

+#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */

+#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */

+#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */

+#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */

+

+#define TIM_SMCR_TS_Pos           (4U)

+#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */

+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[4:0] bits (Trigger selection) */

+#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)                /*!< 0x00000010 */

+#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)                /*!< 0x00000020 */

+#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)                /*!< 0x00000040 */

+#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)                /*!< 0x00100000 */

+#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)                /*!< 0x00200000 */

+

+#define TIM_SMCR_MSM_Pos          (7U)

+#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */

+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */

+

+#define TIM_SMCR_ETF_Pos          (8U)

+#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */

+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */

+#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */

+#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */

+#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */

+#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */

+

+#define TIM_SMCR_ETPS_Pos         (12U)

+#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */

+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */

+#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */

+#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */

+

+#define TIM_SMCR_ECE_Pos          (14U)

+#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */

+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */

+#define TIM_SMCR_ETP_Pos          (15U)

+#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */

+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */

+

+/*******************  Bit definition for TIM_DIER register  *******************/

+#define TIM_DIER_UIE_Pos          (0U)

+#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */

+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */

+#define TIM_DIER_CC1IE_Pos        (1U)

+#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */

+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */

+#define TIM_DIER_CC2IE_Pos        (2U)

+#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */

+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */

+#define TIM_DIER_CC3IE_Pos        (3U)

+#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */

+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */

+#define TIM_DIER_CC4IE_Pos        (4U)

+#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */

+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */

+#define TIM_DIER_COMIE_Pos        (5U)

+#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */

+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */

+#define TIM_DIER_TIE_Pos          (6U)

+#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */

+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */

+#define TIM_DIER_BIE_Pos          (7U)

+#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */

+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */

+#define TIM_DIER_UDE_Pos          (8U)

+#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */

+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */

+#define TIM_DIER_CC1DE_Pos        (9U)

+#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */

+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */

+#define TIM_DIER_CC2DE_Pos        (10U)

+#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */

+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */

+#define TIM_DIER_CC3DE_Pos        (11U)

+#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */

+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */

+#define TIM_DIER_CC4DE_Pos        (12U)

+#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */

+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */

+#define TIM_DIER_COMDE_Pos        (13U)

+#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */

+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */

+#define TIM_DIER_TDE_Pos          (14U)

+#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */

+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */

+

+/********************  Bit definition for TIM_SR register  ********************/

+#define TIM_SR_UIF_Pos            (0U)

+#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */

+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */

+#define TIM_SR_CC1IF_Pos          (1U)

+#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */

+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */

+#define TIM_SR_CC2IF_Pos          (2U)

+#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */

+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */

+#define TIM_SR_CC3IF_Pos          (3U)

+#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */

+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */

+#define TIM_SR_CC4IF_Pos          (4U)

+#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */

+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */

+#define TIM_SR_COMIF_Pos          (5U)

+#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */

+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */

+#define TIM_SR_TIF_Pos            (6U)

+#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */

+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */

+#define TIM_SR_BIF_Pos            (7U)

+#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */

+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */

+#define TIM_SR_B2IF_Pos           (8U)

+#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */

+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break2 interrupt Flag */

+#define TIM_SR_CC1OF_Pos          (9U)

+#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */

+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */

+#define TIM_SR_CC2OF_Pos          (10U)

+#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */

+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */

+#define TIM_SR_CC3OF_Pos          (11U)

+#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */

+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */

+#define TIM_SR_CC4OF_Pos          (12U)

+#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */

+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */

+#define TIM_SR_CC5IF_Pos          (16U)

+#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */

+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */

+#define TIM_SR_CC6IF_Pos          (17U)

+#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */

+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */

+#define TIM_SR_SBIF_Pos           (13U)

+#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */

+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!< System Break Flag */

+

+/*******************  Bit definition for TIM_EGR register  ********************/

+#define TIM_EGR_UG_Pos            (0U)

+#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */

+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */

+#define TIM_EGR_CC1G_Pos          (1U)

+#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */

+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */

+#define TIM_EGR_CC2G_Pos          (2U)

+#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */

+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */

+#define TIM_EGR_CC3G_Pos          (3U)

+#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */

+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */

+#define TIM_EGR_CC4G_Pos          (4U)

+#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */

+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */

+#define TIM_EGR_COMG_Pos          (5U)

+#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */

+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */

+#define TIM_EGR_TG_Pos            (6U)

+#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */

+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */

+#define TIM_EGR_BG_Pos            (7U)

+#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */

+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */

+#define TIM_EGR_B2G_Pos           (8U)

+#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */

+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break Generation */

+

+

+/******************  Bit definition for TIM_CCMR1 register  *******************/

+#define TIM_CCMR1_CC1S_Pos        (0U)

+#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */

+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */

+#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */

+#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */

+

+#define TIM_CCMR1_OC1FE_Pos       (2U)

+#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */

+#define TIM_CCMR1_OC1PE_Pos       (3U)

+#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */

+

+#define TIM_CCMR1_OC1M_Pos        (4U)

+#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */

+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */

+#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */

+#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */

+#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */

+#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR1_OC1CE_Pos       (7U)

+#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */

+

+#define TIM_CCMR1_CC2S_Pos        (8U)

+#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */

+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */

+#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */

+#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */

+

+#define TIM_CCMR1_OC2FE_Pos       (10U)

+#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */

+#define TIM_CCMR1_OC2PE_Pos       (11U)

+#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */

+

+#define TIM_CCMR1_OC2M_Pos        (12U)

+#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */

+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */

+#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */

+#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */

+#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */

+#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */

+

+#define TIM_CCMR1_OC2CE_Pos       (15U)

+#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */

+

+/*----------------------------------------------------------------------------*/

+

+#define TIM_CCMR1_IC1PSC_Pos      (2U)

+#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */

+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */

+#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */

+

+#define TIM_CCMR1_IC1F_Pos        (4U)

+#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */

+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */

+#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */

+

+#define TIM_CCMR1_IC2PSC_Pos      (10U)

+#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */

+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */

+#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */

+

+#define TIM_CCMR1_IC2F_Pos        (12U)

+#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */

+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */

+#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */

+

+/******************  Bit definition for TIM_CCMR2 register  *******************/

+#define TIM_CCMR2_CC3S_Pos        (0U)

+#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */

+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */

+#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */

+#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */

+

+#define TIM_CCMR2_OC3FE_Pos       (2U)

+#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */

+#define TIM_CCMR2_OC3PE_Pos       (3U)

+#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */

+

+#define TIM_CCMR2_OC3M_Pos        (4U)

+#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */

+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */

+#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR2_OC3CE_Pos       (7U)

+#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */

+

+#define TIM_CCMR2_CC4S_Pos        (8U)

+#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */

+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */

+#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */

+#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */

+

+#define TIM_CCMR2_OC4FE_Pos       (10U)

+#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */

+#define TIM_CCMR2_OC4PE_Pos       (11U)

+#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */

+

+#define TIM_CCMR2_OC4M_Pos        (12U)

+#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */

+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */

+#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */

+

+#define TIM_CCMR2_OC4CE_Pos       (15U)

+#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */

+

+/*----------------------------------------------------------------------------*/

+

+#define TIM_CCMR2_IC3PSC_Pos      (2U)

+#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */

+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */

+#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */

+

+#define TIM_CCMR2_IC3F_Pos        (4U)

+#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */

+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */

+#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */

+

+#define TIM_CCMR2_IC4PSC_Pos      (10U)

+#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */

+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */

+#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */

+

+#define TIM_CCMR2_IC4F_Pos        (12U)

+#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */

+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */

+#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */

+

+/*******************  Bit definition for TIM_CCER register  *******************/

+#define TIM_CCER_CC1E_Pos         (0U)

+#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */

+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */

+#define TIM_CCER_CC1P_Pos         (1U)

+#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */

+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */

+#define TIM_CCER_CC1NE_Pos        (2U)

+#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */

+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */

+#define TIM_CCER_CC1NP_Pos        (3U)

+#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */

+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */

+#define TIM_CCER_CC2E_Pos         (4U)

+#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */

+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */

+#define TIM_CCER_CC2P_Pos         (5U)

+#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */

+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */

+#define TIM_CCER_CC2NE_Pos        (6U)

+#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */

+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */

+#define TIM_CCER_CC2NP_Pos        (7U)

+#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */

+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */

+#define TIM_CCER_CC3E_Pos         (8U)

+#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */

+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */

+#define TIM_CCER_CC3P_Pos         (9U)

+#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */

+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */

+#define TIM_CCER_CC3NE_Pos        (10U)

+#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */

+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */

+#define TIM_CCER_CC3NP_Pos        (11U)

+#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */

+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */

+#define TIM_CCER_CC4E_Pos         (12U)

+#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */

+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */

+#define TIM_CCER_CC4P_Pos         (13U)

+#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */

+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */

+#define TIM_CCER_CC4NP_Pos        (15U)

+#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */

+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */

+#define TIM_CCER_CC5E_Pos         (16U)

+#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */

+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */

+#define TIM_CCER_CC5P_Pos         (17U)

+#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */

+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */

+#define TIM_CCER_CC6E_Pos         (20U)

+#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */

+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */

+#define TIM_CCER_CC6P_Pos         (21U)

+#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */

+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */

+/*******************  Bit definition for TIM_CNT register  ********************/

+#define TIM_CNT_CNT_Pos           (0U)

+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */

+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */

+#define TIM_CNT_UIFCPY_Pos        (31U)

+#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */

+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy */

+/*******************  Bit definition for TIM_PSC register  ********************/

+#define TIM_PSC_PSC_Pos           (0U)

+#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */

+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */

+

+/*******************  Bit definition for TIM_ARR register  ********************/

+#define TIM_ARR_ARR_Pos           (0U)

+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */

+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */

+

+/*******************  Bit definition for TIM_RCR register  ********************/

+#define TIM_RCR_REP_Pos           (0U)

+#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                  /*!< 0x000000FF */

+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */

+

+/*******************  Bit definition for TIM_CCR1 register  *******************/

+#define TIM_CCR1_CCR1_Pos         (0U)

+#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */

+

+/*******************  Bit definition for TIM_CCR2 register  *******************/

+#define TIM_CCR2_CCR2_Pos         (0U)

+#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */

+

+/*******************  Bit definition for TIM_CCR3 register  *******************/

+#define TIM_CCR3_CCR3_Pos         (0U)

+#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */

+

+/*******************  Bit definition for TIM_CCR4 register  *******************/

+#define TIM_CCR4_CCR4_Pos         (0U)

+#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */

+

+/*******************  Bit definition for TIM_CCR5 register  *******************/

+#define TIM_CCR5_CCR5_Pos         (0U)

+#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */

+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */

+#define TIM_CCR5_GC5C1_Pos        (29U)

+#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */

+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */

+#define TIM_CCR5_GC5C2_Pos        (30U)

+#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */

+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */

+#define TIM_CCR5_GC5C3_Pos        (31U)

+#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */

+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */

+

+/*******************  Bit definition for TIM_CCR6 register  *******************/

+#define TIM_CCR6_CCR6_Pos         (0U)

+#define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */

+

+/*******************  Bit definition for TIM_BDTR register  *******************/

+#define TIM_BDTR_DTG_Pos          (0U)

+#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */

+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */

+#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */

+#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */

+#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */

+#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */

+#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */

+#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */

+#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */

+#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */

+

+#define TIM_BDTR_LOCK_Pos         (8U)

+#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */

+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */

+#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */

+#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */

+

+#define TIM_BDTR_OSSI_Pos         (10U)

+#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */

+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */

+#define TIM_BDTR_OSSR_Pos         (11U)

+#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */

+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */

+#define TIM_BDTR_BKE_Pos          (12U)

+#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */

+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break1 */

+#define TIM_BDTR_BKP_Pos          (13U)

+#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */

+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break1 */

+#define TIM_BDTR_AOE_Pos          (14U)

+#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */

+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */

+#define TIM_BDTR_MOE_Pos          (15U)

+#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */

+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */

+

+#define TIM_BDTR_BKF_Pos          (16U)

+#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */

+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break1 */

+#define TIM_BDTR_BK2F_Pos         (20U)

+#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */

+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break2 */

+

+#define TIM_BDTR_BK2E_Pos         (24U)

+#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */

+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break2 */

+#define TIM_BDTR_BK2P_Pos         (25U)

+#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */

+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */

+

+/*******************  Bit definition for TIM_DCR register  ********************/

+#define TIM_DCR_DBA_Pos           (0U)

+#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */

+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */

+#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */

+#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */

+#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */

+#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */

+#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */

+

+#define TIM_DCR_DBL_Pos           (8U)

+#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */

+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */

+#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */

+#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */

+#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */

+#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */

+#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */

+

+/*******************  Bit definition for TIM_DMAR register  *******************/

+#define TIM_DMAR_DMAB_Pos         (0U)

+#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */

+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */

+

+/******************  Bit definition for TIM_CCMR3 register  *******************/

+#define TIM_CCMR3_OC5FE_Pos       (2U)

+#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */

+#define TIM_CCMR3_OC5PE_Pos       (3U)

+#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */

+

+#define TIM_CCMR3_OC5M_Pos        (4U)

+#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */

+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */

+#define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR3_OC5CE_Pos       (7U)

+#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */

+

+#define TIM_CCMR3_OC6FE_Pos       (10U)

+#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 4 Fast enable */

+#define TIM_CCMR3_OC6PE_Pos       (11U)

+#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */

+

+#define TIM_CCMR3_OC6M_Pos        (12U)

+#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */

+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */

+#define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */

+

+#define TIM_CCMR3_OC6CE_Pos       (15U)

+#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 4 Clear Enable */

+/*******************  Bit definition for TIM1_AF1 register  *********************/

+#define TIM1_AF1_BKINE_Pos        (0U)

+#define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */

+#define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */

+#define TIM1_AF1_BKCMP1E_Pos      (1U)

+#define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */

+#define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM1_AF1_BKCMP2E_Pos      (2U)

+#define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */

+#define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit */

+#define TIM1_AF1_BKDF1BK0E_Pos    (8U)

+#define TIM1_AF1_BKDF1BK0E_Msk    (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)            /*!< 0x00000100 */

+#define TIM1_AF1_BKDF1BK0E        TIM1_AF1_BKDF1BK0E_Msk                       /*!<BKDF1BK0E Break input DFSDM Break 0 */

+#define TIM1_AF1_BKINP_Pos        (9U)

+#define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */

+#define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */

+#define TIM1_AF1_BKCMP1P_Pos      (10U)

+#define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */

+#define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM1_AF1_BKCMP2P_Pos      (11U)

+#define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */

+#define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */

+

+#define TIM1_AF1_ETRSEL_Pos       (14U)

+#define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */

+#define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */

+#define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00004000 */

+#define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00008000 */

+#define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00010000 */

+#define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM1_AF2 register  *********************/

+#define TIM1_AF2_BK2INE_Pos       (0U)

+#define TIM1_AF2_BK2INE_Msk       (0x1UL << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */

+#define TIM1_AF2_BK2INE           TIM1_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */

+#define TIM1_AF2_BK2CMP1E_Pos     (1U)

+#define TIM1_AF2_BK2CMP1E_Msk     (0x1UL << TIM1_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */

+#define TIM1_AF2_BK2CMP1E         TIM1_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */

+#define TIM1_AF2_BK2CMP2E_Pos     (2U)

+#define TIM1_AF2_BK2CMP2E_Msk     (0x1UL << TIM1_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */

+#define TIM1_AF2_BK2CMP2E         TIM1_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */

+#define TIM1_AF2_BK2DFBK1E_Pos    (8U)

+#define TIM1_AF2_BK2DFBK1E_Msk    (0x1UL << TIM1_AF2_BK2DFBK1E_Pos)            /*!< 0x00000100 */

+#define TIM1_AF2_BK2DFBK1E        TIM1_AF2_BK2DFBK1E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 1 */

+#define TIM1_AF2_BK2INP_Pos       (9U)

+#define TIM1_AF2_BK2INP_Msk       (0x1UL << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */

+#define TIM1_AF2_BK2INP           TIM1_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */

+#define TIM1_AF2_BK2CMP1P_Pos     (10U)

+#define TIM1_AF2_BK2CMP1P_Msk     (0x1UL << TIM1_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */

+#define TIM1_AF2_BK2CMP1P         TIM1_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */

+#define TIM1_AF2_BK2CMP2P_Pos     (11U)

+#define TIM1_AF2_BK2CMP2P_Msk     (0x1UL << TIM1_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */

+#define TIM1_AF2_BK2CMP2P         TIM1_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */

+

+/*******************  Bit definition for TIM_TISEL register  *********************/

+#define TIM_TISEL_TI1SEL_Pos      (0U)

+#define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */

+#define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/

+#define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000001 */

+#define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000002 */

+#define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000004 */

+#define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000008 */

+

+#define TIM_TISEL_TI2SEL_Pos      (8U)

+#define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */

+#define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/

+#define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000100 */

+#define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000200 */

+#define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000400 */

+#define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000800 */

+

+#define TIM_TISEL_TI3SEL_Pos      (16U)

+#define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */

+#define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/

+#define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00010000 */

+#define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00020000 */

+#define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00040000 */

+#define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00080000 */

+

+#define TIM_TISEL_TI4SEL_Pos      (24U)

+#define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */

+#define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/

+#define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x01000000 */

+#define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x02000000 */

+#define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x04000000 */

+#define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x08000000 */

+

+/*******************  Bit definition for TIM8_AF1 register  *********************/

+#define TIM8_AF1_BKINE_Pos        (0U)

+#define TIM8_AF1_BKINE_Msk        (0x1UL << TIM8_AF1_BKINE_Pos)                /*!< 0x00000001 */

+#define TIM8_AF1_BKINE            TIM8_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */

+#define TIM8_AF1_BKCMP1E_Pos      (1U)

+#define TIM8_AF1_BKCMP1E_Msk      (0x1UL << TIM8_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */

+#define TIM8_AF1_BKCMP1E          TIM8_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM8_AF1_BKCMP2E_Pos      (2U)

+#define TIM8_AF1_BKCMP2E_Msk      (0x1UL << TIM8_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */

+#define TIM8_AF1_BKCMP2E          TIM8_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM8_AF1_BKDFBK2E_Pos     (8U)

+#define TIM8_AF1_BKDFBK2E_Msk     (0x1UL << TIM8_AF1_BKDFBK2E_Pos)             /*!< 0x00000100 */

+#define TIM8_AF1_BKDFBK2E         TIM8_AF1_BKDFBK2E_Msk                        /*!<BKDFBK2E Break input DFSDM Break 2 */

+#define TIM8_AF1_BKINP_Pos        (9U)

+#define TIM8_AF1_BKINP_Msk        (0x1UL << TIM8_AF1_BKINP_Pos)                /*!< 0x00000200 */

+#define TIM8_AF1_BKINP            TIM8_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */

+#define TIM8_AF1_BKCMP1P_Pos      (10U)

+#define TIM8_AF1_BKCMP1P_Msk      (0x1UL << TIM8_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */

+#define TIM8_AF1_BKCMP1P          TIM8_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM8_AF1_BKCMP2P_Pos      (11U)

+#define TIM8_AF1_BKCMP2P_Msk      (0x1UL << TIM8_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */

+#define TIM8_AF1_BKCMP2P          TIM8_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */

+

+#define TIM8_AF1_ETRSEL_Pos       (14U)

+#define TIM8_AF1_ETRSEL_Msk       (0xFUL << TIM8_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */

+#define TIM8_AF1_ETRSEL           TIM8_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */

+#define TIM8_AF1_ETRSEL_0         (0x1UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00004000 */

+#define TIM8_AF1_ETRSEL_1         (0x2UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00008000 */

+#define TIM8_AF1_ETRSEL_2         (0x4UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00010000 */

+#define TIM8_AF1_ETRSEL_3         (0x8UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00020000 */

+/*******************  Bit definition for TIM8_AF2 register  *********************/

+#define TIM8_AF2_BK2INE_Pos       (0U)

+#define TIM8_AF2_BK2INE_Msk       (0x1UL << TIM8_AF2_BK2INE_Pos)               /*!< 0x00000001 */

+#define TIM8_AF2_BK2INE           TIM8_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */

+#define TIM8_AF2_BK2CMP1E_Pos     (1U)

+#define TIM8_AF2_BK2CMP1E_Msk     (0x1UL << TIM8_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */

+#define TIM8_AF2_BK2CMP1E         TIM8_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */

+#define TIM8_AF2_BK2CMP2E_Pos     (2U)

+#define TIM8_AF2_BK2CMP2E_Msk     (0x1UL << TIM8_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */

+#define TIM8_AF2_BK2CMP2E         TIM8_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */

+#define TIM8_AF2_BK2DFBK3E_Pos    (8U)

+#define TIM8_AF2_BK2DFBK3E_Msk    (0x1UL << TIM8_AF2_BK2DFBK3E_Pos)            /*!< 0x00000100 */

+#define TIM8_AF2_BK2DFBK3E        TIM8_AF2_BK2DFBK3E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 3 */

+#define TIM8_AF2_BK2INP_Pos       (9U)

+#define TIM8_AF2_BK2INP_Msk       (0x1UL << TIM8_AF2_BK2INP_Pos)               /*!< 0x00000200 */

+#define TIM8_AF2_BK2INP           TIM8_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */

+#define TIM8_AF2_BK2CMP1P_Pos     (10U)

+#define TIM8_AF2_BK2CMP1P_Msk     (0x1UL << TIM8_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */

+#define TIM8_AF2_BK2CMP1P         TIM8_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */

+#define TIM8_AF2_BK2CMP2P_Pos     (11U)

+#define TIM8_AF2_BK2CMP2P_Msk     (0x1UL << TIM8_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */

+#define TIM8_AF2_BK2CMP2P         TIM8_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */

+

+/*******************  Bit definition for TIM2_AF1 register  *********************/

+#define TIM2_AF1_ETRSEL_Pos      (14U)

+#define TIM2_AF1_ETRSEL_Msk      (0xFUL << TIM2_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM2_AF1_ETRSEL          TIM2_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */

+#define TIM2_AF1_ETRSEL_0        (0x1UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM2_AF1_ETRSEL_1        (0x2UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM2_AF1_ETRSEL_2        (0x4UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM2_AF1_ETRSEL_3        (0x8UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM3_AF1 register  *********************/

+#define TIM3_AF1_ETRSEL_Pos      (14U)

+#define TIM3_AF1_ETRSEL_Msk      (0xFUL << TIM3_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM3_AF1_ETRSEL          TIM3_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */

+#define TIM3_AF1_ETRSEL_0        (0x1UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM3_AF1_ETRSEL_1        (0x2UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM3_AF1_ETRSEL_2        (0x4UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM3_AF1_ETRSEL_3        (0x8UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM5_AF1 register  *********************/

+#define TIM5_AF1_ETRSEL_Pos      (14U)

+#define TIM5_AF1_ETRSEL_Msk      (0xFUL << TIM5_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM5_AF1_ETRSEL          TIM5_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */

+#define TIM5_AF1_ETRSEL_0        (0x1UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM5_AF1_ETRSEL_1        (0x2UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM5_AF1_ETRSEL_2        (0x4UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM5_AF1_ETRSEL_3        (0x8UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM15_AF1 register  *********************/

+#define TIM15_AF1_BKINE_Pos        (0U)

+#define TIM15_AF1_BKINE_Msk        (0x1UL << TIM15_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM15_AF1_BKINE            TIM15_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM15_AF1_BKCMP1E_Pos      (1U)

+#define TIM15_AF1_BKCMP1E_Msk      (0x1UL << TIM15_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM15_AF1_BKCMP1E          TIM15_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM15_AF1_BKCMP2E_Pos      (2U)

+#define TIM15_AF1_BKCMP2E_Msk      (0x1UL << TIM15_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM15_AF1_BKCMP2E          TIM15_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM15_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM15_AF1_BKDF1BK2E_Msk    (0x1UL << TIM15_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM15_AF1_BKDF1BK2E        TIM15_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[0] enable */

+#define TIM15_AF1_BKINP_Pos        (9U)

+#define TIM15_AF1_BKINP_Msk        (0x1UL << TIM15_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM15_AF1_BKINP            TIM15_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM15_AF1_BKCMP1P_Pos      (10U)

+#define TIM15_AF1_BKCMP1P_Msk      (0x1UL << TIM15_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM15_AF1_BKCMP1P          TIM15_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM15_AF1_BKCMP2P_Pos      (11U)

+#define TIM15_AF1_BKCMP2P_Msk      (0x1UL << TIM15_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM15_AF1_BKCMP2P          TIM15_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/*******************  Bit definition for TIM16_ register  *********************/

+#define TIM16_AF1_BKINE_Pos        (0U)

+#define TIM16_AF1_BKINE_Msk        (0x1UL << TIM16_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM16_AF1_BKINE            TIM16_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM16_AF1_BKCMP1E_Pos      (1U)

+#define TIM16_AF1_BKCMP1E_Msk      (0x1UL << TIM16_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM16_AF1_BKCMP1E          TIM16_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM16_AF1_BKCMP2E_Pos      (2U)

+#define TIM16_AF1_BKCMP2E_Msk      (0x1UL << TIM16_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM16_AF1_BKCMP2E          TIM16_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM16_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM16_AF1_BKDF1BK2E_Msk    (0x1UL << TIM16_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM16_AF1_BKDF1BK2E        TIM16_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[1] enable */

+#define TIM16_AF1_BKINP_Pos        (9U)

+#define TIM16_AF1_BKINP_Msk        (0x1UL << TIM16_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM16_AF1_BKINP            TIM16_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM16_AF1_BKCMP1P_Pos      (10U)

+#define TIM16_AF1_BKCMP1P_Msk      (0x1UL << TIM16_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM16_AF1_BKCMP1P          TIM16_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM16_AF1_BKCMP2P_Pos      (11U)

+#define TIM16_AF1_BKCMP2P_Msk      (0x1UL << TIM16_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM16_AF1_BKCMP2P          TIM16_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/*******************  Bit definition for TIM17_AF1 register  *********************/

+#define TIM17_AF1_BKINE_Pos        (0U)

+#define TIM17_AF1_BKINE_Msk        (0x1UL << TIM17_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM17_AF1_BKINE            TIM17_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM17_AF1_BKCMP1E_Pos      (1U)

+#define TIM17_AF1_BKCMP1E_Msk      (0x1UL << TIM17_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM17_AF1_BKCMP1E          TIM17_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM17_AF1_BKCMP2E_Pos      (2U)

+#define TIM17_AF1_BKCMP2E_Msk      (0x1UL << TIM17_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM17_AF1_BKCMP2E          TIM17_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM17_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM17_AF1_BKDF1BK2E_Msk    (0x1UL << TIM17_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM17_AF1_BKDF1BK2E        TIM17_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[2] enable */

+#define TIM17_AF1_BKINP_Pos        (9U)

+#define TIM17_AF1_BKINP_Msk        (0x1UL << TIM17_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM17_AF1_BKINP            TIM17_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM17_AF1_BKCMP1P_Pos      (10U)

+#define TIM17_AF1_BKCMP1P_Msk      (0x1UL << TIM17_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM17_AF1_BKCMP1P          TIM17_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM17_AF1_BKCMP2P_Pos      (11U)

+#define TIM17_AF1_BKCMP2P_Msk      (0x1UL << TIM17_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM17_AF1_BKCMP2P          TIM17_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Low Power Timer (LPTTIM)                           */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for LPTIM_ISR register  *******************/

+#define LPTIM_ISR_CMPM_Pos          (0U)

+#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */

+#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */

+#define LPTIM_ISR_ARRM_Pos          (1U)

+#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */

+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */

+#define LPTIM_ISR_EXTTRIG_Pos       (2U)

+#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */

+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */

+#define LPTIM_ISR_CMPOK_Pos         (3U)

+#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */

+#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */

+#define LPTIM_ISR_ARROK_Pos         (4U)

+#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */

+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */

+#define LPTIM_ISR_UP_Pos            (5U)

+#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */

+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */

+#define LPTIM_ISR_DOWN_Pos          (6U)

+#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */

+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */

+

+/******************  Bit definition for LPTIM_ICR register  *******************/

+#define LPTIM_ICR_CMPMCF_Pos        (0U)

+#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */

+#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */

+#define LPTIM_ICR_ARRMCF_Pos        (1U)

+#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */

+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */

+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)

+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */

+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */

+#define LPTIM_ICR_CMPOKCF_Pos       (3U)

+#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */

+#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */

+#define LPTIM_ICR_ARROKCF_Pos       (4U)

+#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */

+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */

+#define LPTIM_ICR_UPCF_Pos          (5U)

+#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */

+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */

+#define LPTIM_ICR_DOWNCF_Pos        (6U)

+#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */

+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */

+

+/******************  Bit definition for LPTIM_IER register ********************/

+#define LPTIM_IER_CMPMIE_Pos        (0U)

+#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */

+#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */

+#define LPTIM_IER_ARRMIE_Pos        (1U)

+#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */

+#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */

+#define LPTIM_IER_EXTTRIGIE_Pos     (2U)

+#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */

+#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */

+#define LPTIM_IER_CMPOKIE_Pos       (3U)

+#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */

+#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */

+#define LPTIM_IER_ARROKIE_Pos       (4U)

+#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */

+#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */

+#define LPTIM_IER_UPIE_Pos          (5U)

+#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */

+#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */

+#define LPTIM_IER_DOWNIE_Pos        (6U)

+#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */

+#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */

+

+/******************  Bit definition for LPTIM_CFGR register *******************/

+#define LPTIM_CFGR_CKSEL_Pos        (0U)

+#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */

+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */

+

+#define LPTIM_CFGR_CKPOL_Pos        (1U)

+#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */

+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */

+#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */

+#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */

+

+#define LPTIM_CFGR_CKFLT_Pos        (3U)

+#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */

+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */

+#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */

+#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */

+

+#define LPTIM_CFGR_TRGFLT_Pos       (6U)

+#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */

+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */

+#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */

+#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */

+

+#define LPTIM_CFGR_PRESC_Pos        (9U)

+#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */

+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */

+#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */

+#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */

+#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */

+

+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)

+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */

+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */

+#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */

+#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */

+#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */

+

+#define LPTIM_CFGR_TRIGEN_Pos       (17U)

+#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */

+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */

+#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */

+#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */

+

+#define LPTIM_CFGR_TIMOUT_Pos       (19U)

+#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */

+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */

+#define LPTIM_CFGR_WAVE_Pos         (20U)

+#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */

+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */

+#define LPTIM_CFGR_WAVPOL_Pos       (21U)

+#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */

+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */

+#define LPTIM_CFGR_PRELOAD_Pos      (22U)

+#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */

+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */

+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)

+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */

+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */

+#define LPTIM_CFGR_ENC_Pos          (24U)

+#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */

+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */

+

+/******************  Bit definition for LPTIM_CR register  ********************/

+#define LPTIM_CR_ENABLE_Pos         (0U)

+#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */

+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */

+#define LPTIM_CR_SNGSTRT_Pos        (1U)

+#define LPTIM_CR_SNGSTRT_Msk        (0x40001UL << LPTIM_CR_SNGSTRT_Pos)        /*!< 0x00080002 */

+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */

+#define LPTIM_CR_CNTSTRT_Pos        (2U)

+#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */

+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */

+#define LPTIM_CR_COUNTRST_Pos       (3U)

+#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */

+#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Timer Counter reset in synchronous mode*/

+#define LPTIM_CR_RSTARE_Pos         (4U)

+#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */

+#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Timer Counter reset after read enable (asynchronously)*/

+

+

+/******************  Bit definition for LPTIM_CMP register  *******************/

+#define LPTIM_CMP_CMP_Pos           (0U)

+#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */

+

+/******************  Bit definition for LPTIM_ARR register  *******************/

+#define LPTIM_ARR_ARR_Pos           (0U)

+#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */

+

+/******************  Bit definition for LPTIM_CNT register  *******************/

+#define LPTIM_CNT_CNT_Pos           (0U)

+#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */

+

+/******************  Bit definition for LPTIM_CFGR2 register  *****************/

+#define LPTIM_CFGR2_IN1SEL_Pos      (0U)

+#define LPTIM_CFGR2_IN1SEL_Msk      (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000003 */

+#define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< IN1SEL[1:0] bits (Remap selection) */

+#define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000001 */

+#define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000002 */

+#define LPTIM_CFGR2_IN2SEL_Pos      (4U)

+#define LPTIM_CFGR2_IN2SEL_Msk      (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000030 */

+#define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< IN2SEL[5:4] bits (Remap selection) */

+#define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000010 */

+#define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000020 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      Analog Comparators (COMP)                             */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for COMP_SR register  ********************/

+#define COMP_SR_C1VAL_Pos            (0U)

+#define COMP_SR_C1VAL_Msk            (0x1UL << COMP_SR_C1VAL_Pos)              /*!< 0x00000001 */

+#define COMP_SR_C1VAL                COMP_SR_C1VAL_Msk

+#define COMP_SR_C2VAL_Pos            (1U)

+#define COMP_SR_C2VAL_Msk            (0x1UL << COMP_SR_C2VAL_Pos)              /*!< 0x00000002 */

+#define COMP_SR_C2VAL                COMP_SR_C2VAL_Msk

+#define COMP_SR_C1IF_Pos             (16U)

+#define COMP_SR_C1IF_Msk             (0x1UL << COMP_SR_C1IF_Pos)               /*!< 0x00010000 */

+#define COMP_SR_C1IF                 COMP_SR_C1IF_Msk

+#define COMP_SR_C2IF_Pos             (17U)

+#define COMP_SR_C2IF_Msk             (0x1UL << COMP_SR_C2IF_Pos)               /*!< 0x00020000 */

+#define COMP_SR_C2IF                 COMP_SR_C2IF_Msk

+/*******************  Bit definition for COMP_ICFR register  ********************/

+#define COMP_ICFR_C1IF_Pos           (16U)

+#define COMP_ICFR_C1IF_Msk           (0x1UL << COMP_ICFR_C1IF_Pos)             /*!< 0x00010000 */

+#define COMP_ICFR_C1IF               COMP_ICFR_C1IF_Msk

+#define COMP_ICFR_C2IF_Pos           (17U)

+#define COMP_ICFR_C2IF_Msk           (0x1UL << COMP_ICFR_C2IF_Pos)             /*!< 0x00020000 */

+#define COMP_ICFR_C2IF               COMP_ICFR_C2IF_Msk

+/*******************  Bit definition for COMP_OR register  ********************/

+#define COMP_OR_AFOPA6_Pos           (0U)

+#define COMP_OR_AFOPA6_Msk           (0x1UL << COMP_OR_AFOPA6_Pos)             /*!< 0x00000001 */

+#define COMP_OR_AFOPA6               COMP_OR_AFOPA6_Msk

+#define COMP_OR_AFOPA8_Pos           (1U)

+#define COMP_OR_AFOPA8_Msk           (0x1UL << COMP_OR_AFOPA8_Pos)             /*!< 0x00000002 */

+#define COMP_OR_AFOPA8               COMP_OR_AFOPA8_Msk

+#define COMP_OR_AFOPB12_Pos          (2U)

+#define COMP_OR_AFOPB12_Msk          (0x1UL << COMP_OR_AFOPB12_Pos)            /*!< 0x00000004 */

+#define COMP_OR_AFOPB12              COMP_OR_AFOPB12_Msk

+#define COMP_OR_AFOPE6_Pos           (3U)

+#define COMP_OR_AFOPE6_Msk           (0x1UL << COMP_OR_AFOPE6_Pos)             /*!< 0x00000008 */

+#define COMP_OR_AFOPE6               COMP_OR_AFOPE6_Msk

+#define COMP_OR_AFOPE15_Pos          (4U)

+#define COMP_OR_AFOPE15_Msk          (0x1UL << COMP_OR_AFOPE15_Pos)            /*!< 0x00000010 */

+#define COMP_OR_AFOPE15              COMP_OR_AFOPE15_Msk

+#define COMP_OR_AFOPG2_Pos           (5U)

+#define COMP_OR_AFOPG2_Msk           (0x1UL << COMP_OR_AFOPG2_Pos)             /*!< 0x00000020 */

+#define COMP_OR_AFOPG2               COMP_OR_AFOPG2_Msk

+#define COMP_OR_AFOPG3_Pos           (6U)

+#define COMP_OR_AFOPG3_Msk           (0x1UL << COMP_OR_AFOPG3_Pos)             /*!< 0x00000040 */

+#define COMP_OR_AFOPG3               COMP_OR_AFOPG3_Msk

+#define COMP_OR_AFOPG4_Pos           (7U)

+#define COMP_OR_AFOPG4_Msk           (0x1UL << COMP_OR_AFOPG4_Pos)             /*!< 0x00000080 */

+#define COMP_OR_AFOPG4               COMP_OR_AFOPG4_Msk

+#define COMP_OR_AFOPI1_Pos           (8U)

+#define COMP_OR_AFOPI1_Msk           (0x1UL << COMP_OR_AFOPI1_Pos)             /*!< 0x00000100 */

+#define COMP_OR_AFOPI1               COMP_OR_AFOPI1_Msk

+#define COMP_OR_AFOPI4_Pos           (9U)

+#define COMP_OR_AFOPI4_Msk           (0x1UL << COMP_OR_AFOPI4_Pos)             /*!< 0x00000200 */

+#define COMP_OR_AFOPI4               COMP_OR_AFOPI4_Msk

+#define COMP_OR_AFOPK2_Pos           (10U)

+#define COMP_OR_AFOPK2_Msk           (0x1UL << COMP_OR_AFOPK2_Pos)             /*!< 0x00000400 */

+#define COMP_OR_AFOPK2               COMP_OR_AFOPK2_Msk

+

+/*!< ******************  Bit definition for COMP_CFGRx register  ********************/

+#define COMP_CFGRx_EN_Pos            (0U)

+#define COMP_CFGRx_EN_Msk            (0x1UL << COMP_CFGRx_EN_Pos)              /*!< 0x00000001 */

+#define COMP_CFGRx_EN                COMP_CFGRx_EN_Msk                         /*!< COMPx enable bit                     */

+#define COMP_CFGRx_BRGEN_Pos         (1U)

+#define COMP_CFGRx_BRGEN_Msk         (0x1UL << COMP_CFGRx_BRGEN_Pos)           /*!< 0x00000002 */

+#define COMP_CFGRx_BRGEN             COMP_CFGRx_BRGEN_Msk                      /*!< COMPx Scaler bridge enable           */

+#define COMP_CFGRx_SCALEN_Pos        (2U)

+#define COMP_CFGRx_SCALEN_Msk        (0x1UL << COMP_CFGRx_SCALEN_Pos)          /*!< 0x00000004 */

+#define COMP_CFGRx_SCALEN            COMP_CFGRx_SCALEN_Msk                     /*!< COMPx Voltage scaler enable bit      */

+#define COMP_CFGRx_POLARITY_Pos      (3U)

+#define COMP_CFGRx_POLARITY_Msk      (0x1UL << COMP_CFGRx_POLARITY_Pos)        /*!< 0x00000008 */

+#define COMP_CFGRx_POLARITY          COMP_CFGRx_POLARITY_Msk                   /*!< COMPx  polarity selection bit        */

+#define COMP_CFGRx_WINMODE_Pos       (4U)

+#define COMP_CFGRx_WINMODE_Msk       (0x1UL << COMP_CFGRx_WINMODE_Pos)         /*!< 0x00000010 */

+#define COMP_CFGRx_WINMODE           COMP_CFGRx_WINMODE_Msk                    /*!< COMPx Windows mode selection bit     */

+#define COMP_CFGRx_ITEN_Pos          (6U)

+#define COMP_CFGRx_ITEN_Msk          (0x1UL << COMP_CFGRx_ITEN_Pos)            /*!< 0x00000040 */

+#define COMP_CFGRx_ITEN              COMP_CFGRx_ITEN_Msk                       /*!< COMPx  interrupt enable              */

+#define COMP_CFGRx_HYST_Pos          (8U)

+#define COMP_CFGRx_HYST_Msk          (0x3UL << COMP_CFGRx_HYST_Pos)            /*!< 0x00000300 */

+#define COMP_CFGRx_HYST              COMP_CFGRx_HYST_Msk                       /*!< COMPx  hysteresis selection bits     */

+#define COMP_CFGRx_HYST_0            (0x1UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000100 */

+#define COMP_CFGRx_HYST_1            (0x2UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000200 */

+#define COMP_CFGRx_PWRMODE_Pos       (12U)

+#define COMP_CFGRx_PWRMODE_Msk       (0x3UL << COMP_CFGRx_PWRMODE_Pos)         /*!< 0x00003000 */

+#define COMP_CFGRx_PWRMODE           COMP_CFGRx_PWRMODE_Msk                    /*!< COMPx Power Mode of the comparator   */

+#define COMP_CFGRx_PWRMODE_0         (0x1UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00001000 */

+#define COMP_CFGRx_PWRMODE_1         (0x2UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00002000 */

+#define COMP_CFGRx_INMSEL_Pos        (16U)

+#define COMP_CFGRx_INMSEL_Msk        (0x7UL << COMP_CFGRx_INMSEL_Pos)          /*!< 0x00070000 */

+#define COMP_CFGRx_INMSEL            COMP_CFGRx_INMSEL_Msk                     /*!< COMPx  input minus selection bit  */

+#define COMP_CFGRx_INMSEL_0          (0x1UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00010000 */

+#define COMP_CFGRx_INMSEL_1          (0x2UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00020000 */

+#define COMP_CFGRx_INMSEL_2          (0x4UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00040000 */

+#define COMP_CFGRx_INPSEL_Pos        (20U)

+#define COMP_CFGRx_INPSEL_Msk        (0x1UL << COMP_CFGRx_INPSEL_Pos)          /*!< 0x00100000 */

+#define COMP_CFGRx_INPSEL            COMP_CFGRx_INPSEL_Msk                     /*!< COMPx  input plus selection bit       */

+#define COMP_CFGRx_BLANKING_Pos      (24U)

+#define COMP_CFGRx_BLANKING_Msk      (0xFUL << COMP_CFGRx_BLANKING_Pos)        /*!< 0x0F000000 */

+#define COMP_CFGRx_BLANKING          COMP_CFGRx_BLANKING_Msk                   /*!< COMPx  blanking source selection bits */

+#define COMP_CFGRx_BLANKING_0        (0x1UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x01000000 */

+#define COMP_CFGRx_BLANKING_1        (0x2UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x02000000 */

+#define COMP_CFGRx_BLANKING_2        (0x4UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x04000000 */

+#define COMP_CFGRx_LOCK_Pos          (31U)

+#define COMP_CFGRx_LOCK_Msk          (0x1UL << COMP_CFGRx_LOCK_Pos)            /*!< 0x80000000 */

+#define COMP_CFGRx_LOCK              COMP_CFGRx_LOCK_Msk                       /*!< COMPx Lock Bit                        */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for USART_CR1 register  *******************/

+#define USART_CR1_UE_Pos                (0U)

+#define USART_CR1_UE_Msk                (0x1UL << USART_CR1_UE_Pos)            /*!< 0x00000001 */

+#define USART_CR1_UE                    USART_CR1_UE_Msk                       /*!< USART Enable */

+#define USART_CR1_UESM_Pos              (1U)

+#define USART_CR1_UESM_Msk              (0x1UL << USART_CR1_UESM_Pos)          /*!< 0x00000002 */

+#define USART_CR1_UESM                  USART_CR1_UESM_Msk                     /*!< USART Enable in STOP Mode */

+#define USART_CR1_RE_Pos                (2U)

+#define USART_CR1_RE_Msk                (0x1UL << USART_CR1_RE_Pos)            /*!< 0x00000004 */

+#define USART_CR1_RE                    USART_CR1_RE_Msk                       /*!< Receiver Enable */

+#define USART_CR1_TE_Pos                (3U)

+#define USART_CR1_TE_Msk                (0x1UL << USART_CR1_TE_Pos)            /*!< 0x00000008 */

+#define USART_CR1_TE                    USART_CR1_TE_Msk                       /*!< Transmitter Enable */

+#define USART_CR1_IDLEIE_Pos            (4U)

+#define USART_CR1_IDLEIE_Msk            (0x1UL << USART_CR1_IDLEIE_Pos)        /*!< 0x00000010 */

+#define USART_CR1_IDLEIE                USART_CR1_IDLEIE_Msk                   /*!< IDLE Interrupt Enable */

+#define USART_CR1_RXNEIE_RXFNEIE_Pos    (5U)

+#define USART_CR1_RXNEIE_RXFNEIE_Msk    (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */

+#define USART_CR1_RXNEIE_RXFNEIE        USART_CR1_RXNEIE_RXFNEIE_Msk           /*!< RXNE and RX FIFO Not Empty Interrupt Enable */

+#define USART_CR1_TCIE_Pos              (6U)

+#define USART_CR1_TCIE_Msk              (0x1UL << USART_CR1_TCIE_Pos)          /*!< 0x00000040 */

+#define USART_CR1_TCIE                  USART_CR1_TCIE_Msk                     /*!< Transmission Complete Interrupt Enable */

+#define USART_CR1_TXEIE_TXFNFIE_Pos     (7U)

+#define USART_CR1_TXEIE_TXFNFIE_Msk     (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */

+#define USART_CR1_TXEIE_TXFNFIE         USART_CR1_TXEIE_TXFNFIE_Msk            /*!< TXE and TX FIFO Not Full Interrupt Enable */

+#define USART_CR1_PEIE_Pos              (8U)

+#define USART_CR1_PEIE_Msk              (0x1UL << USART_CR1_PEIE_Pos)          /*!< 0x00000100 */

+#define USART_CR1_PEIE                  USART_CR1_PEIE_Msk                     /*!< PE Interrupt Enable */

+#define USART_CR1_PS_Pos                (9U)

+#define USART_CR1_PS_Msk                (0x1UL << USART_CR1_PS_Pos)            /*!< 0x00000200 */

+#define USART_CR1_PS                    USART_CR1_PS_Msk                       /*!< Parity Selection */

+#define USART_CR1_PCE_Pos               (10U)

+#define USART_CR1_PCE_Msk               (0x1UL << USART_CR1_PCE_Pos)           /*!< 0x00000400 */

+#define USART_CR1_PCE                   USART_CR1_PCE_Msk                      /*!< Parity Control Enable */

+#define USART_CR1_WAKE_Pos              (11U)

+#define USART_CR1_WAKE_Msk              (0x1UL << USART_CR1_WAKE_Pos)          /*!< 0x00000800 */

+#define USART_CR1_WAKE                  USART_CR1_WAKE_Msk                     /*!< Receiver Wakeup method */

+#define USART_CR1_M_Pos                 (12U)

+#define USART_CR1_M_Msk                 (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */

+#define USART_CR1_M                     USART_CR1_M_Msk                        /*!< Word length */

+#define USART_CR1_M0_Pos                (12U)

+#define USART_CR1_M0_Msk                (0x1UL << USART_CR1_M0_Pos)            /*!< 0x00001000 */

+#define USART_CR1_M0                    USART_CR1_M0_Msk                       /*!< Word length - Bit 0 */

+#define USART_CR1_MME_Pos               (13U)

+#define USART_CR1_MME_Msk               (0x1UL << USART_CR1_MME_Pos)           /*!< 0x00002000 */

+#define USART_CR1_MME                   USART_CR1_MME_Msk                      /*!< Mute Mode Enable */

+#define USART_CR1_CMIE_Pos              (14U)

+#define USART_CR1_CMIE_Msk              (0x1UL << USART_CR1_CMIE_Pos)          /*!< 0x00004000 */

+#define USART_CR1_CMIE                  USART_CR1_CMIE_Msk                     /*!< Character match interrupt enable */

+#define USART_CR1_OVER8_Pos             (15U)

+#define USART_CR1_OVER8_Msk             (0x1UL << USART_CR1_OVER8_Pos)         /*!< 0x00008000 */

+#define USART_CR1_OVER8                 USART_CR1_OVER8_Msk                    /*!< Oversampling by 8-bit or 16-bit mode */

+#define USART_CR1_DEDT_Pos              (16U)

+#define USART_CR1_DEDT_Msk              (0x1FUL << USART_CR1_DEDT_Pos)         /*!< 0x001F0000 */

+#define USART_CR1_DEDT                  USART_CR1_DEDT_Msk                     /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */

+#define USART_CR1_DEDT_0                (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */

+#define USART_CR1_DEDT_1                (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */

+#define USART_CR1_DEDT_2                (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */

+#define USART_CR1_DEDT_3                (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */

+#define USART_CR1_DEDT_4                (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */

+#define USART_CR1_DEAT_Pos              (21U)

+#define USART_CR1_DEAT_Msk              (0x1FUL << USART_CR1_DEAT_Pos)         /*!< 0x03E00000 */

+#define USART_CR1_DEAT                  USART_CR1_DEAT_Msk                     /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */

+#define USART_CR1_DEAT_0                (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */

+#define USART_CR1_DEAT_1                (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */

+#define USART_CR1_DEAT_2                (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */

+#define USART_CR1_DEAT_3                (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */

+#define USART_CR1_DEAT_4                (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */

+#define USART_CR1_RTOIE_Pos             (26U)

+#define USART_CR1_RTOIE_Msk             (0x1UL << USART_CR1_RTOIE_Pos)         /*!< 0x04000000 */

+#define USART_CR1_RTOIE                 USART_CR1_RTOIE_Msk                    /*!< Receive Time Out interrupt enable */

+#define USART_CR1_EOBIE_Pos             (27U)

+#define USART_CR1_EOBIE_Msk             (0x1UL << USART_CR1_EOBIE_Pos)         /*!< 0x08000000 */

+#define USART_CR1_EOBIE                 USART_CR1_EOBIE_Msk                    /*!< End of Block interrupt enable */

+#define USART_CR1_M1_Pos                (28U)

+#define USART_CR1_M1_Msk                (0x1UL << USART_CR1_M1_Pos)            /*!< 0x10000000 */

+#define USART_CR1_M1                    USART_CR1_M1_Msk                       /*!< Word length - Bit 1 */

+#define USART_CR1_FIFOEN_Pos            (29U)

+#define USART_CR1_FIFOEN_Msk            (0x1UL << USART_CR1_FIFOEN_Pos)        /*!< 0x20000000 */

+#define USART_CR1_FIFOEN                USART_CR1_FIFOEN_Msk                   /*!< FIFO mode enable */

+#define USART_CR1_TXFEIE_Pos            (30U)

+#define USART_CR1_TXFEIE_Msk            (0x1UL << USART_CR1_TXFEIE_Pos)        /*!< 0x40000000 */

+#define USART_CR1_TXFEIE                USART_CR1_TXFEIE_Msk                   /*!< TXFIFO empty interrupt enable */

+#define USART_CR1_RXFFIE_Pos            (31U)

+#define USART_CR1_RXFFIE_Msk            (0x1UL << USART_CR1_RXFFIE_Pos)        /*!< 0x80000000 */

+#define USART_CR1_RXFFIE                USART_CR1_RXFFIE_Msk                   /*!< RXFIFO Full interrupt enable */

+

+/* Legacy define */

+#define  USART_CR1_RXNEIE  USART_CR1_RXNEIE_RXFNEIE

+#define  USART_CR1_TXEIE   USART_CR1_TXEIE_TXFNFIE

+

+/******************  Bit definition for USART_CR2 register  *******************/

+#define USART_CR2_SLVEN_Pos             (0U)

+#define USART_CR2_SLVEN_Msk             (0x1UL << USART_CR2_SLVEN_Pos)         /*!< 0x00000001 */

+#define USART_CR2_SLVEN                 USART_CR2_SLVEN_Msk                    /*!< Synchronous Slave mode Enable */

+#define USART_CR2_DIS_NSS_Pos           (3U)

+#define USART_CR2_DIS_NSS_Msk           (0x1UL << USART_CR2_DIS_NSS_Pos)       /*!< 0x00000008 */

+#define USART_CR2_DIS_NSS               USART_CR2_DIS_NSS_Msk                  /*!< Negative Slave Select (NSS) pin management */

+#define USART_CR2_ADDM7_Pos             (4U)

+#define USART_CR2_ADDM7_Msk             (0x1UL << USART_CR2_ADDM7_Pos)         /*!< 0x00000010 */

+#define USART_CR2_ADDM7                 USART_CR2_ADDM7_Msk                    /*!< 7-bit or 4-bit Address Detection */

+#define USART_CR2_LBDL_Pos              (5U)

+#define USART_CR2_LBDL_Msk              (0x1UL << USART_CR2_LBDL_Pos)          /*!< 0x00000020 */

+#define USART_CR2_LBDL                  USART_CR2_LBDL_Msk                     /*!< LIN Break Detection Length */

+#define USART_CR2_LBDIE_Pos             (6U)

+#define USART_CR2_LBDIE_Msk             (0x1UL << USART_CR2_LBDIE_Pos)         /*!< 0x00000040 */

+#define USART_CR2_LBDIE                 USART_CR2_LBDIE_Msk                    /*!< LIN Break Detection Interrupt Enable */

+#define USART_CR2_LBCL_Pos              (8U)

+#define USART_CR2_LBCL_Msk              (0x1UL << USART_CR2_LBCL_Pos)          /*!< 0x00000100 */

+#define USART_CR2_LBCL                  USART_CR2_LBCL_Msk                     /*!< Last Bit Clock pulse */

+#define USART_CR2_CPHA_Pos              (9U)

+#define USART_CR2_CPHA_Msk              (0x1UL << USART_CR2_CPHA_Pos)          /*!< 0x00000200 */

+#define USART_CR2_CPHA                  USART_CR2_CPHA_Msk                     /*!< Clock Phase */

+#define USART_CR2_CPOL_Pos              (10U)

+#define USART_CR2_CPOL_Msk              (0x1UL << USART_CR2_CPOL_Pos)          /*!< 0x00000400 */

+#define USART_CR2_CPOL                  USART_CR2_CPOL_Msk                     /*!< Clock Polarity */

+#define USART_CR2_CLKEN_Pos             (11U)

+#define USART_CR2_CLKEN_Msk             (0x1UL << USART_CR2_CLKEN_Pos)         /*!< 0x00000800 */

+#define USART_CR2_CLKEN                 USART_CR2_CLKEN_Msk                    /*!< Clock Enable */

+#define USART_CR2_STOP_Pos              (12U)

+#define USART_CR2_STOP_Msk              (0x3UL << USART_CR2_STOP_Pos)          /*!< 0x00003000 */

+#define USART_CR2_STOP                  USART_CR2_STOP_Msk                     /*!< STOP[1:0] bits (STOP bits) */

+#define USART_CR2_STOP_0                (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */

+#define USART_CR2_STOP_1                (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */

+#define USART_CR2_LINEN_Pos             (14U)

+#define USART_CR2_LINEN_Msk             (0x1UL << USART_CR2_LINEN_Pos)         /*!< 0x00004000 */

+#define USART_CR2_LINEN                 USART_CR2_LINEN_Msk                    /*!< LIN mode enable */

+#define USART_CR2_SWAP_Pos              (15U)

+#define USART_CR2_SWAP_Msk              (0x1UL << USART_CR2_SWAP_Pos)          /*!< 0x00008000 */

+#define USART_CR2_SWAP                  USART_CR2_SWAP_Msk                     /*!< SWAP TX/RX pins */

+#define USART_CR2_RXINV_Pos             (16U)

+#define USART_CR2_RXINV_Msk             (0x1UL << USART_CR2_RXINV_Pos)         /*!< 0x00010000 */

+#define USART_CR2_RXINV                 USART_CR2_RXINV_Msk                    /*!< RX pin active level inversion */

+#define USART_CR2_TXINV_Pos             (17U)

+#define USART_CR2_TXINV_Msk             (0x1UL << USART_CR2_TXINV_Pos)         /*!< 0x00020000 */

+#define USART_CR2_TXINV                 USART_CR2_TXINV_Msk                    /*!< TX pin active level inversion */

+#define USART_CR2_DATAINV_Pos           (18U)

+#define USART_CR2_DATAINV_Msk           (0x1UL << USART_CR2_DATAINV_Pos)       /*!< 0x00040000 */

+#define USART_CR2_DATAINV               USART_CR2_DATAINV_Msk                  /*!< Binary data inversion */

+#define USART_CR2_MSBFIRST_Pos          (19U)

+#define USART_CR2_MSBFIRST_Msk          (0x1UL << USART_CR2_MSBFIRST_Pos)      /*!< 0x00080000 */

+#define USART_CR2_MSBFIRST              USART_CR2_MSBFIRST_Msk                 /*!< Most Significant Bit First */

+#define USART_CR2_ABREN_Pos             (20U)

+#define USART_CR2_ABREN_Msk             (0x1UL << USART_CR2_ABREN_Pos)         /*!< 0x00100000 */

+#define USART_CR2_ABREN                 USART_CR2_ABREN_Msk                    /*!< Auto Baud-Rate Enable*/

+#define USART_CR2_ABRMODE_Pos           (21U)

+#define USART_CR2_ABRMODE_Msk           (0x3UL << USART_CR2_ABRMODE_Pos)       /*!< 0x00600000 */

+#define USART_CR2_ABRMODE               USART_CR2_ABRMODE_Msk                  /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */

+#define USART_CR2_ABRMODE_0             (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */

+#define USART_CR2_ABRMODE_1             (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */

+#define USART_CR2_RTOEN_Pos             (23U)

+#define USART_CR2_RTOEN_Msk             (0x1UL << USART_CR2_RTOEN_Pos)         /*!< 0x00800000 */

+#define USART_CR2_RTOEN                 USART_CR2_RTOEN_Msk                    /*!< Receiver Time-Out enable */

+#define USART_CR2_ADD_Pos               (24U)

+#define USART_CR2_ADD_Msk               (0xFFUL << USART_CR2_ADD_Pos)          /*!< 0xFF000000 */

+#define USART_CR2_ADD                   USART_CR2_ADD_Msk                      /*!< Address of the USART node */

+

+/******************  Bit definition for USART_CR3 register  *******************/

+#define USART_CR3_EIE_Pos               (0U)

+#define USART_CR3_EIE_Msk               (0x1UL << USART_CR3_EIE_Pos)           /*!< 0x00000001 */

+#define USART_CR3_EIE                   USART_CR3_EIE_Msk                      /*!< Error Interrupt Enable */

+#define USART_CR3_IREN_Pos              (1U)

+#define USART_CR3_IREN_Msk              (0x1UL << USART_CR3_IREN_Pos)          /*!< 0x00000002 */

+#define USART_CR3_IREN                  USART_CR3_IREN_Msk                     /*!< IrDA mode Enable */

+#define USART_CR3_IRLP_Pos              (2U)

+#define USART_CR3_IRLP_Msk              (0x1UL << USART_CR3_IRLP_Pos)          /*!< 0x00000004 */

+#define USART_CR3_IRLP                  USART_CR3_IRLP_Msk                     /*!< IrDA Low-Power */

+#define USART_CR3_HDSEL_Pos             (3U)

+#define USART_CR3_HDSEL_Msk             (0x1UL << USART_CR3_HDSEL_Pos)         /*!< 0x00000008 */

+#define USART_CR3_HDSEL                 USART_CR3_HDSEL_Msk                    /*!< Half-Duplex Selection */

+#define USART_CR3_NACK_Pos              (4U)

+#define USART_CR3_NACK_Msk              (0x1UL << USART_CR3_NACK_Pos)          /*!< 0x00000010 */

+#define USART_CR3_NACK                  USART_CR3_NACK_Msk                     /*!< SmartCard NACK enable */

+#define USART_CR3_SCEN_Pos              (5U)

+#define USART_CR3_SCEN_Msk              (0x1UL << USART_CR3_SCEN_Pos)          /*!< 0x00000020 */

+#define USART_CR3_SCEN                  USART_CR3_SCEN_Msk                     /*!< SmartCard mode enable */

+#define USART_CR3_DMAR_Pos              (6U)

+#define USART_CR3_DMAR_Msk              (0x1UL << USART_CR3_DMAR_Pos)          /*!< 0x00000040 */

+#define USART_CR3_DMAR                  USART_CR3_DMAR_Msk                     /*!< DMA Enable Receiver */

+#define USART_CR3_DMAT_Pos              (7U)

+#define USART_CR3_DMAT_Msk              (0x1UL << USART_CR3_DMAT_Pos)          /*!< 0x00000080 */

+#define USART_CR3_DMAT                  USART_CR3_DMAT_Msk                     /*!< DMA Enable Transmitter */

+#define USART_CR3_RTSE_Pos              (8U)

+#define USART_CR3_RTSE_Msk              (0x1UL << USART_CR3_RTSE_Pos)          /*!< 0x00000100 */

+#define USART_CR3_RTSE                  USART_CR3_RTSE_Msk                     /*!< RTS Enable */

+#define USART_CR3_CTSE_Pos              (9U)

+#define USART_CR3_CTSE_Msk              (0x1UL << USART_CR3_CTSE_Pos)          /*!< 0x00000200 */

+#define USART_CR3_CTSE                  USART_CR3_CTSE_Msk                     /*!< CTS Enable */

+#define USART_CR3_CTSIE_Pos             (10U)

+#define USART_CR3_CTSIE_Msk             (0x1UL << USART_CR3_CTSIE_Pos)         /*!< 0x00000400 */

+#define USART_CR3_CTSIE                 USART_CR3_CTSIE_Msk                    /*!< CTS Interrupt Enable */

+#define USART_CR3_ONEBIT_Pos            (11U)

+#define USART_CR3_ONEBIT_Msk            (0x1UL << USART_CR3_ONEBIT_Pos)        /*!< 0x00000800 */

+#define USART_CR3_ONEBIT                USART_CR3_ONEBIT_Msk                   /*!< One sample bit method enable */

+#define USART_CR3_OVRDIS_Pos            (12U)

+#define USART_CR3_OVRDIS_Msk            (0x1UL << USART_CR3_OVRDIS_Pos)        /*!< 0x00001000 */

+#define USART_CR3_OVRDIS                USART_CR3_OVRDIS_Msk                   /*!< Overrun Disable */

+#define USART_CR3_DDRE_Pos              (13U)

+#define USART_CR3_DDRE_Msk              (0x1UL << USART_CR3_DDRE_Pos)          /*!< 0x00002000 */

+#define USART_CR3_DDRE                  USART_CR3_DDRE_Msk                     /*!< DMA Disable on Reception Error */

+#define USART_CR3_DEM_Pos               (14U)

+#define USART_CR3_DEM_Msk               (0x1UL << USART_CR3_DEM_Pos)           /*!< 0x00004000 */

+#define USART_CR3_DEM                   USART_CR3_DEM_Msk                      /*!< Driver Enable Mode */

+#define USART_CR3_DEP_Pos               (15U)

+#define USART_CR3_DEP_Msk               (0x1UL << USART_CR3_DEP_Pos)           /*!< 0x00008000 */

+#define USART_CR3_DEP                   USART_CR3_DEP_Msk                      /*!< Driver Enable Polarity Selection */

+#define USART_CR3_SCARCNT_Pos           (17U)

+#define USART_CR3_SCARCNT_Msk           (0x7UL << USART_CR3_SCARCNT_Pos)       /*!< 0x000E0000 */

+#define USART_CR3_SCARCNT               USART_CR3_SCARCNT_Msk                  /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */

+#define USART_CR3_SCARCNT_0             (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */

+#define USART_CR3_SCARCNT_1             (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */

+#define USART_CR3_SCARCNT_2             (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */

+#define USART_CR3_WUS_Pos               (20U)

+#define USART_CR3_WUS_Msk               (0x3UL << USART_CR3_WUS_Pos)           /*!< 0x00300000 */

+#define USART_CR3_WUS                   USART_CR3_WUS_Msk                      /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */

+#define USART_CR3_WUS_0                 (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */

+#define USART_CR3_WUS_1                 (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */

+#define USART_CR3_WUFIE_Pos             (22U)

+#define USART_CR3_WUFIE_Msk             (0x1UL << USART_CR3_WUFIE_Pos)         /*!< 0x00400000 */

+#define USART_CR3_WUFIE                 USART_CR3_WUFIE_Msk                    /*!< Wake Up Interrupt Enable */

+#define USART_CR3_TXFTIE_Pos            (23U)

+#define USART_CR3_TXFTIE_Msk            (0x1UL << USART_CR3_TXFTIE_Pos)        /*!< 0x00800000 */

+#define USART_CR3_TXFTIE                USART_CR3_TXFTIE_Msk                   /*!< TXFIFO threshold interrupt enable */

+#define USART_CR3_TCBGTIE_Pos           (24U)

+#define USART_CR3_TCBGTIE_Msk           (0x1UL << USART_CR3_TCBGTIE_Pos)       /*!< 0x01000000 */

+#define USART_CR3_TCBGTIE               USART_CR3_TCBGTIE_Msk                  /*!< Transmission Complete before guard time, interrupt enable */

+#define USART_CR3_RXFTCFG_Pos           (25U)

+#define USART_CR3_RXFTCFG_Msk           (0x7UL << USART_CR3_RXFTCFG_Pos)       /*!< 0x0E000000 */

+#define USART_CR3_RXFTCFG               USART_CR3_RXFTCFG_Msk                  /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */

+#define USART_CR3_RXFTCFG_0             (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */

+#define USART_CR3_RXFTCFG_1             (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */

+#define USART_CR3_RXFTCFG_2             (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */

+#define USART_CR3_RXFTIE_Pos            (28U)

+#define USART_CR3_RXFTIE_Msk            (0x1UL << USART_CR3_RXFTIE_Pos)        /*!< 0x10000000 */

+#define USART_CR3_RXFTIE                USART_CR3_RXFTIE_Msk                   /*!< RXFIFO threshold interrupt enable */

+#define USART_CR3_TXFTCFG_Pos           (29U)

+#define USART_CR3_TXFTCFG_Msk           (0x7UL << USART_CR3_TXFTCFG_Pos)       /*!< 0xE0000000 */

+#define USART_CR3_TXFTCFG               USART_CR3_TXFTCFG_Msk                  /*!< TXFIFO [2:0] threshold configuration */

+#define USART_CR3_TXFTCFG_0             (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */

+#define USART_CR3_TXFTCFG_1             (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */

+#define USART_CR3_TXFTCFG_2             (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */

+

+/******************  Bit definition for USART_BRR register  *******************/

+#define USART_BRR_DIV_FRACTION_Pos      (0U)

+#define USART_BRR_DIV_FRACTION_Msk      (0xFUL << USART_BRR_DIV_FRACTION_Pos)  /*!< 0x0000000F */

+#define USART_BRR_DIV_FRACTION          USART_BRR_DIV_FRACTION_Msk             /*!< Fraction of USARTDIV */

+#define USART_BRR_DIV_MANTISSA_Pos      (4U)

+#define USART_BRR_DIV_MANTISSA_Msk      (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */

+#define USART_BRR_DIV_MANTISSA          USART_BRR_DIV_MANTISSA_Msk             /*!< Mantissa of USARTDIV */

+

+/******************  Bit definition for USART_GTPR register  ******************/

+#define USART_GTPR_PSC_Pos              (0U)

+#define USART_GTPR_PSC_Msk              (0xFFUL << USART_GTPR_PSC_Pos)         /*!< 0x000000FF */

+#define USART_GTPR_PSC                  USART_GTPR_PSC_Msk                     /*!< PSC[7:0] bits (Prescaler value) */

+#define USART_GTPR_GT_Pos               (8U)

+#define USART_GTPR_GT_Msk               (0xFFUL << USART_GTPR_GT_Pos)          /*!< 0x0000FF00 */

+#define USART_GTPR_GT                   USART_GTPR_GT_Msk                      /*!< GT[7:0] bits (Guard time value) */

+

+/*******************  Bit definition for USART_RTOR register  *****************/

+#define USART_RTOR_RTO_Pos              (0U)

+#define USART_RTOR_RTO_Msk              (0xFFFFFFUL << USART_RTOR_RTO_Pos)     /*!< 0x00FFFFFF */

+#define USART_RTOR_RTO                  USART_RTOR_RTO_Msk                     /*!< Receiver Time Out Value */

+#define USART_RTOR_BLEN_Pos             (24U)

+#define USART_RTOR_BLEN_Msk             (0xFFUL << USART_RTOR_BLEN_Pos)        /*!< 0xFF000000 */

+#define USART_RTOR_BLEN                 USART_RTOR_BLEN_Msk                    /*!< Block Length */

+

+/*******************  Bit definition for USART_RQR register  ******************/

+#define USART_RQR_ABRRQ_Pos             (0U)

+#define USART_RQR_ABRRQ_Msk             (0x1UL << USART_RQR_ABRRQ_Pos)         /*!< 0x00000001 */

+#define USART_RQR_ABRRQ                 USART_RQR_ABRRQ_Msk                    /*!< Auto-Baud Rate Request */

+#define USART_RQR_SBKRQ_Pos             (1U)

+#define USART_RQR_SBKRQ_Msk             (0x1UL << USART_RQR_SBKRQ_Pos)         /*!< 0x00000002 */

+#define USART_RQR_SBKRQ                 USART_RQR_SBKRQ_Msk                    /*!< Send Break Request */

+#define USART_RQR_MMRQ_Pos              (2U)

+#define USART_RQR_MMRQ_Msk              (0x1UL << USART_RQR_MMRQ_Pos)          /*!< 0x00000004 */

+#define USART_RQR_MMRQ                  USART_RQR_MMRQ_Msk                     /*!< Mute Mode Request */

+#define USART_RQR_RXFRQ_Pos             (3U)

+#define USART_RQR_RXFRQ_Msk             (0x1UL << USART_RQR_RXFRQ_Pos)         /*!< 0x00000008 */

+#define USART_RQR_RXFRQ                 USART_RQR_RXFRQ_Msk                    /*!< Receive Data flush Request */

+#define USART_RQR_TXFRQ_Pos             (4U)

+#define USART_RQR_TXFRQ_Msk             (0x1UL << USART_RQR_TXFRQ_Pos)         /*!< 0x00000010 */

+#define USART_RQR_TXFRQ                 USART_RQR_TXFRQ_Msk                    /*!< Transmit data flush Request */

+

+/*******************  Bit definition for USART_ISR register  ******************/

+#define USART_ISR_PE_Pos                (0U)

+#define USART_ISR_PE_Msk                (0x1UL << USART_ISR_PE_Pos)            /*!< 0x00000001 */

+#define USART_ISR_PE                    USART_ISR_PE_Msk                       /*!< Parity Error */

+#define USART_ISR_FE_Pos                (1U)

+#define USART_ISR_FE_Msk                (0x1UL << USART_ISR_FE_Pos)            /*!< 0x00000002 */

+#define USART_ISR_FE                    USART_ISR_FE_Msk                       /*!< Framing Error */

+#define USART_ISR_NE_Pos                (2U)

+#define USART_ISR_NE_Msk                (0x1UL << USART_ISR_NE_Pos)            /*!< 0x00000004 */

+#define USART_ISR_NE                    USART_ISR_NE_Msk                       /*!< Noise detected Flag */

+#define USART_ISR_ORE_Pos               (3U)

+#define USART_ISR_ORE_Msk               (0x1UL << USART_ISR_ORE_Pos)           /*!< 0x00000008 */

+#define USART_ISR_ORE                   USART_ISR_ORE_Msk                      /*!< OverRun Error */

+#define USART_ISR_IDLE_Pos              (4U)

+#define USART_ISR_IDLE_Msk              (0x1UL << USART_ISR_IDLE_Pos)          /*!< 0x00000010 */

+#define USART_ISR_IDLE                  USART_ISR_IDLE_Msk                     /*!< IDLE line detected */

+#define USART_ISR_RXNE_RXFNE_Pos        (5U)

+#define USART_ISR_RXNE_RXFNE_Msk        (0x1UL << USART_ISR_RXNE_RXFNE_Pos)    /*!< 0x00000020 */

+#define USART_ISR_RXNE_RXFNE            USART_ISR_RXNE_RXFNE_Msk               /*!< Read Data Register or RX FIFO Not Empty */

+#define USART_ISR_TC_Pos                (6U)

+#define USART_ISR_TC_Msk                (0x1UL << USART_ISR_TC_Pos)            /*!< 0x00000040 */

+#define USART_ISR_TC                    USART_ISR_TC_Msk                       /*!< Transmission Complete */

+#define USART_ISR_TXE_TXFNF_Pos         (7U)

+#define USART_ISR_TXE_TXFNF_Msk         (0x1UL << USART_ISR_TXE_TXFNF_Pos)     /*!< 0x00000080 */

+#define USART_ISR_TXE_TXFNF             USART_ISR_TXE_TXFNF_Msk                /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */

+#define USART_ISR_LBDF_Pos              (8U)

+#define USART_ISR_LBDF_Msk              (0x1UL << USART_ISR_LBDF_Pos)          /*!< 0x00000100 */

+#define USART_ISR_LBDF                  USART_ISR_LBDF_Msk                     /*!< LIN Break Detection Flag */

+#define USART_ISR_CTSIF_Pos             (9U)

+#define USART_ISR_CTSIF_Msk             (0x1UL << USART_ISR_CTSIF_Pos)         /*!< 0x00000200 */

+#define USART_ISR_CTSIF                 USART_ISR_CTSIF_Msk                    /*!< CTS interrupt flag */

+#define USART_ISR_CTS_Pos               (10U)

+#define USART_ISR_CTS_Msk               (0x1UL << USART_ISR_CTS_Pos)           /*!< 0x00000400 */

+#define USART_ISR_CTS                   USART_ISR_CTS_Msk                      /*!< CTS flag */

+#define USART_ISR_RTOF_Pos              (11U)

+#define USART_ISR_RTOF_Msk              (0x1UL << USART_ISR_RTOF_Pos)          /*!< 0x00000800 */

+#define USART_ISR_RTOF                  USART_ISR_RTOF_Msk                     /*!< Receiver Time Out */

+#define USART_ISR_EOBF_Pos              (12U)

+#define USART_ISR_EOBF_Msk              (0x1UL << USART_ISR_EOBF_Pos)          /*!< 0x00001000 */

+#define USART_ISR_EOBF                  USART_ISR_EOBF_Msk                     /*!< End Of Block Flag */

+#define USART_ISR_UDR_Pos               (13U)

+#define USART_ISR_UDR_Msk               (0x1UL << USART_ISR_UDR_Pos)           /*!< 0x00002000 */

+#define USART_ISR_UDR                   USART_ISR_UDR_Msk                      /*!< SPI slave underrun error flag */

+#define USART_ISR_ABRE_Pos              (14U)

+#define USART_ISR_ABRE_Msk              (0x1UL << USART_ISR_ABRE_Pos)          /*!< 0x00004000 */

+#define USART_ISR_ABRE                  USART_ISR_ABRE_Msk                     /*!< Auto-Baud Rate Error */

+#define USART_ISR_ABRF_Pos              (15U)

+#define USART_ISR_ABRF_Msk              (0x1UL << USART_ISR_ABRF_Pos)          /*!< 0x00008000 */

+#define USART_ISR_ABRF                  USART_ISR_ABRF_Msk                     /*!< Auto-Baud Rate Flag */

+#define USART_ISR_BUSY_Pos              (16U)

+#define USART_ISR_BUSY_Msk              (0x1UL << USART_ISR_BUSY_Pos)          /*!< 0x00010000 */

+#define USART_ISR_BUSY                  USART_ISR_BUSY_Msk                     /*!< Busy Flag */

+#define USART_ISR_CMF_Pos               (17U)

+#define USART_ISR_CMF_Msk               (0x1UL << USART_ISR_CMF_Pos)           /*!< 0x00020000 */

+#define USART_ISR_CMF                   USART_ISR_CMF_Msk                      /*!< Character Match Flag */

+#define USART_ISR_SBKF_Pos              (18U)

+#define USART_ISR_SBKF_Msk              (0x1UL << USART_ISR_SBKF_Pos)          /*!< 0x00040000 */

+#define USART_ISR_SBKF                  USART_ISR_SBKF_Msk                     /*!< Send Break Flag */

+#define USART_ISR_RWU_Pos               (19U)

+#define USART_ISR_RWU_Msk               (0x1UL << USART_ISR_RWU_Pos)           /*!< 0x00080000 */

+#define USART_ISR_RWU                   USART_ISR_RWU_Msk                      /*!< Receive Wake Up from mute mode Flag */

+#define USART_ISR_WUF_Pos               (20U)

+#define USART_ISR_WUF_Msk               (0x1UL << USART_ISR_WUF_Pos)           /*!< 0x00100000 */

+#define USART_ISR_WUF                   USART_ISR_WUF_Msk                      /*!< Wake Up from stop mode Flag */

+#define USART_ISR_TEACK_Pos             (21U)

+#define USART_ISR_TEACK_Msk             (0x1UL << USART_ISR_TEACK_Pos)         /*!< 0x00200000 */

+#define USART_ISR_TEACK                 USART_ISR_TEACK_Msk                    /*!< Transmit Enable Acknowledge Flag */

+#define USART_ISR_REACK_Pos             (22U)

+#define USART_ISR_REACK_Msk             (0x1UL << USART_ISR_REACK_Pos)         /*!< 0x00400000 */

+#define USART_ISR_REACK                 USART_ISR_REACK_Msk                    /*!< Receive Enable Acknowledge Flag */

+#define USART_ISR_TXFE_Pos              (23U)

+#define USART_ISR_TXFE_Msk              (0x1UL << USART_ISR_TXFE_Pos)          /*!< 0x00800000 */

+#define USART_ISR_TXFE                  USART_ISR_TXFE_Msk                     /*!< TXFIFO Empty */

+#define USART_ISR_RXFF_Pos              (24U)

+#define USART_ISR_RXFF_Msk              (0x1UL << USART_ISR_RXFF_Pos)          /*!< 0x01000000 */

+#define USART_ISR_RXFF                  USART_ISR_RXFF_Msk                     /*!< RXFIFO Full Flag */

+#define USART_ISR_TCBGT_Pos             (25U)

+#define USART_ISR_TCBGT_Msk             (0x1UL << USART_ISR_TCBGT_Pos)         /*!< 0x02000000 */

+#define USART_ISR_TCBGT                 USART_ISR_TCBGT_Msk                    /*!< Transmission complete before guard time Flag */

+#define USART_ISR_RXFT_Pos              (26U)

+#define USART_ISR_RXFT_Msk              (0x1UL << USART_ISR_RXFT_Pos)          /*!< 0x04000000 */

+#define USART_ISR_RXFT                  USART_ISR_RXFT_Msk                     /*!< RXFIFO threshold Flag */

+#define USART_ISR_TXFT_Pos              (27U)

+#define USART_ISR_TXFT_Msk              (0x1UL << USART_ISR_TXFT_Pos)          /*!< 0x08000000 */

+#define USART_ISR_TXFT                  USART_ISR_TXFT_Msk                     /*!< TXFIFO threshold Flag */

+

+/*******************  Bit definition for USART_ICR register  ******************/

+#define USART_ICR_PECF_Pos              (0U)

+#define USART_ICR_PECF_Msk              (0x1UL << USART_ICR_PECF_Pos)          /*!< 0x00000001 */

+#define USART_ICR_PECF                  USART_ICR_PECF_Msk                     /*!< Parity Error Clear Flag */

+#define USART_ICR_FECF_Pos              (1U)

+#define USART_ICR_FECF_Msk              (0x1UL << USART_ICR_FECF_Pos)          /*!< 0x00000002 */

+#define USART_ICR_FECF                  USART_ICR_FECF_Msk                     /*!< Framing Error Clear Flag */

+#define USART_ICR_NECF_Pos              (2U)

+#define USART_ICR_NECF_Msk              (0x1UL << USART_ICR_NECF_Pos)          /*!< 0x00000004 */

+#define USART_ICR_NECF                  USART_ICR_NECF_Msk                     /*!< Noise detected Clear Flag */

+#define USART_ICR_ORECF_Pos             (3U)

+#define USART_ICR_ORECF_Msk             (0x1UL << USART_ICR_ORECF_Pos)         /*!< 0x00000008 */

+#define USART_ICR_ORECF                 USART_ICR_ORECF_Msk                    /*!< OverRun Error Clear Flag */

+#define USART_ICR_IDLECF_Pos            (4U)

+#define USART_ICR_IDLECF_Msk            (0x1UL << USART_ICR_IDLECF_Pos)        /*!< 0x00000010 */

+#define USART_ICR_IDLECF                USART_ICR_IDLECF_Msk                   /*!< IDLE line detected Clear Flag */

+#define USART_ICR_TXFECF_Pos            (5U)

+#define USART_ICR_TXFECF_Msk            (0x1UL << USART_ICR_TXFECF_Pos)        /*!< 0x00000020 */

+#define USART_ICR_TXFECF                USART_ICR_TXFECF_Msk                   /*!< TXFIFO empty clear flag */

+#define USART_ICR_TCCF_Pos              (6U)

+#define USART_ICR_TCCF_Msk              (0x1UL << USART_ICR_TCCF_Pos)          /*!< 0x00000040 */

+#define USART_ICR_TCCF                  USART_ICR_TCCF_Msk                     /*!< Transmission Complete Clear Flag */

+#define USART_ICR_TCBGTCF_Pos           (7U)

+#define USART_ICR_TCBGTCF_Msk           (0x1UL << USART_ICR_TCBGTCF_Pos)       /*!< 0x00000080 */

+#define USART_ICR_TCBGTCF               USART_ICR_TCBGTCF_Msk                  /*!< Transmission complete before guard time Clear Flag */

+#define USART_ICR_LBDCF_Pos             (8U)

+#define USART_ICR_LBDCF_Msk             (0x1UL << USART_ICR_LBDCF_Pos)         /*!< 0x00000100 */

+#define USART_ICR_LBDCF                 USART_ICR_LBDCF_Msk                    /*!< LIN Break Detection Clear Flag */

+#define USART_ICR_CTSCF_Pos             (9U)

+#define USART_ICR_CTSCF_Msk             (0x1UL << USART_ICR_CTSCF_Pos)         /*!< 0x00000200 */

+#define USART_ICR_CTSCF                 USART_ICR_CTSCF_Msk                    /*!< CTS Interrupt Clear Flag */

+#define USART_ICR_RTOCF_Pos             (11U)

+#define USART_ICR_RTOCF_Msk             (0x1UL << USART_ICR_RTOCF_Pos)         /*!< 0x00000800 */

+#define USART_ICR_RTOCF                 USART_ICR_RTOCF_Msk                    /*!< Receiver Time Out Clear Flag */

+#define USART_ICR_EOBCF_Pos             (12U)

+#define USART_ICR_EOBCF_Msk             (0x1UL << USART_ICR_EOBCF_Pos)         /*!< 0x00001000 */

+#define USART_ICR_EOBCF                 USART_ICR_EOBCF_Msk                    /*!< End Of Block Clear Flag */

+#define USART_ICR_UDRCF_Pos             (13U)

+#define USART_ICR_UDRCF_Msk             (0x1UL << USART_ICR_UDRCF_Pos)         /*!< 0x00002000 */

+#define USART_ICR_UDRCF                 USART_ICR_UDRCF_Msk                    /*!< SPI slave underrun clear flag */

+#define USART_ICR_CMCF_Pos              (17U)

+#define USART_ICR_CMCF_Msk              (0x1UL << USART_ICR_CMCF_Pos)          /*!< 0x00020000 */

+#define USART_ICR_CMCF                  USART_ICR_CMCF_Msk                     /*!< Character Match Clear Flag */

+#define USART_ICR_WUCF_Pos              (20U)

+#define USART_ICR_WUCF_Msk              (0x1UL << USART_ICR_WUCF_Pos)          /*!< 0x00100000 */

+#define USART_ICR_WUCF                  USART_ICR_WUCF_Msk                     /*!< Wake Up from stop mode Clear Flag */

+

+/*******************  Bit definition for USART_RDR register  ******************/

+#define USART_RDR_RDR_Pos               (0U)

+#define USART_RDR_RDR_Msk               (0x1FFUL << USART_RDR_RDR_Pos)         /*!< 0x000001FF */

+#define USART_RDR_RDR                   USART_RDR_RDR_Msk                      /*!< RDR[8:0] bits (Receive Data value) */

+

+/*******************  Bit definition for USART_TDR register  ******************/

+#define USART_TDR_TDR_Pos               (0U)

+#define USART_TDR_TDR_Msk               (0x1FFUL << USART_TDR_TDR_Pos)         /*!< 0x000001FF */

+#define USART_TDR_TDR                   USART_TDR_TDR_Msk                      /*!< TDR[8:0] bits (Transmit Data value) */

+

+/*******************  Bit definition for USART_PRESC register  ******************/

+#define USART_PRESC_PRESCALER_Pos       (0U)

+#define USART_PRESC_PRESCALER_Msk       (0xFUL << USART_PRESC_PRESCALER_Pos)   /*!< 0x0000000F */

+#define USART_PRESC_PRESCALER           USART_PRESC_PRESCALER_Msk              /*!< PRESCALER[3:0] bits (Clock prescaler) */

+#define USART_PRESC_PRESCALER_0         (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */

+#define USART_PRESC_PRESCALER_1         (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */

+#define USART_PRESC_PRESCALER_2         (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */

+#define USART_PRESC_PRESCALER_3         (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */

+

+/******************************************************************************/

+/*                                                                            */

+/*           Single Wire Protocol Master Interface (SWPMI)                    */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for SWPMI_CR register   ********************/

+#define SWPMI_CR_RXDMA_Pos       (0U)

+#define SWPMI_CR_RXDMA_Msk       (0x1UL << SWPMI_CR_RXDMA_Pos)                 /*!< 0x00000001 */

+#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */

+#define SWPMI_CR_TXDMA_Pos       (1U)

+#define SWPMI_CR_TXDMA_Msk       (0x1UL << SWPMI_CR_TXDMA_Pos)                 /*!< 0x00000002 */

+#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */

+#define SWPMI_CR_RXMODE_Pos      (2U)

+#define SWPMI_CR_RXMODE_Msk      (0x1UL << SWPMI_CR_RXMODE_Pos)                /*!< 0x00000004 */

+#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */

+#define SWPMI_CR_TXMODE_Pos      (3U)

+#define SWPMI_CR_TXMODE_Msk      (0x1UL << SWPMI_CR_TXMODE_Pos)                /*!< 0x00000008 */

+#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */

+#define SWPMI_CR_LPBK_Pos        (4U)

+#define SWPMI_CR_LPBK_Msk        (0x1UL << SWPMI_CR_LPBK_Pos)                  /*!< 0x00000010 */

+#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */

+#define SWPMI_CR_SWPACT_Pos      (5U)

+#define SWPMI_CR_SWPACT_Msk      (0x1UL << SWPMI_CR_SWPACT_Pos)                /*!< 0x00000020 */

+#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */

+#define SWPMI_CR_DEACT_Pos       (10U)

+#define SWPMI_CR_DEACT_Msk       (0x1UL << SWPMI_CR_DEACT_Pos)                 /*!< 0x00000400 */

+#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */

+#define SWPMI_CR_SWPEN_Pos       (11U)

+#define SWPMI_CR_SWPEN_Msk       (0x1UL << SWPMI_CR_SWPEN_Pos)                 /*!< 0x00000800 */

+#define SWPMI_CR_SWPEN           SWPMI_CR_SWPEN_Msk                            /*!<Single wire protocol master transceiver enable       */

+

+/*******************  Bit definition for SWPMI_BRR register  ********************/

+#define SWPMI_BRR_BR_Pos         (0U)

+#define SWPMI_BRR_BR_Msk         (0xFFUL << SWPMI_BRR_BR_Pos)                  /*!< 0x000000FF */

+#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[7:0] bits (Bitrate prescaler) */

+

+/*******************  Bit definition for SWPMI_ISR register  ********************/

+#define SWPMI_ISR_RXBFF_Pos      (0U)

+#define SWPMI_ISR_RXBFF_Msk      (0x1UL << SWPMI_ISR_RXBFF_Pos)                /*!< 0x00000001 */

+#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */

+#define SWPMI_ISR_TXBEF_Pos      (1U)

+#define SWPMI_ISR_TXBEF_Msk      (0x1UL << SWPMI_ISR_TXBEF_Pos)                /*!< 0x00000002 */

+#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */

+#define SWPMI_ISR_RXBERF_Pos     (2U)

+#define SWPMI_ISR_RXBERF_Msk     (0x1UL << SWPMI_ISR_RXBERF_Pos)               /*!< 0x00000004 */

+#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */

+#define SWPMI_ISR_RXOVRF_Pos     (3U)

+#define SWPMI_ISR_RXOVRF_Msk     (0x1UL << SWPMI_ISR_RXOVRF_Pos)               /*!< 0x00000008 */

+#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */

+#define SWPMI_ISR_TXUNRF_Pos     (4U)

+#define SWPMI_ISR_TXUNRF_Msk     (0x1UL << SWPMI_ISR_TXUNRF_Pos)               /*!< 0x00000010 */

+#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */

+#define SWPMI_ISR_RXNE_Pos       (5U)

+#define SWPMI_ISR_RXNE_Msk       (0x1UL << SWPMI_ISR_RXNE_Pos)                 /*!< 0x00000020 */

+#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */

+#define SWPMI_ISR_TXE_Pos        (6U)

+#define SWPMI_ISR_TXE_Msk        (0x1UL << SWPMI_ISR_TXE_Pos)                  /*!< 0x00000040 */

+#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */

+#define SWPMI_ISR_TCF_Pos        (7U)

+#define SWPMI_ISR_TCF_Msk        (0x1UL << SWPMI_ISR_TCF_Pos)                  /*!< 0x00000080 */

+#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */

+#define SWPMI_ISR_SRF_Pos        (8U)

+#define SWPMI_ISR_SRF_Msk        (0x1UL << SWPMI_ISR_SRF_Pos)                  /*!< 0x00000100 */

+#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */

+#define SWPMI_ISR_SUSP_Pos       (9U)

+#define SWPMI_ISR_SUSP_Msk       (0x1UL << SWPMI_ISR_SUSP_Pos)                 /*!< 0x00000200 */

+#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */

+#define SWPMI_ISR_DEACTF_Pos     (10U)

+#define SWPMI_ISR_DEACTF_Msk     (0x1UL << SWPMI_ISR_DEACTF_Pos)               /*!< 0x00000400 */

+#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */

+#define SWPMI_ISR_RDYF_Pos       (11U)

+#define SWPMI_ISR_RDYF_Msk       (0x1UL << SWPMI_ISR_RDYF_Pos)                 /*!< 0x00000800 */

+#define SWPMI_ISR_RDYF           SWPMI_ISR_RDYF_Msk                            /*!<Transceiver ready flag          */

+

+/*******************  Bit definition for SWPMI_ICR register  ********************/

+#define SWPMI_ICR_CRXBFF_Pos     (0U)

+#define SWPMI_ICR_CRXBFF_Msk     (0x1UL << SWPMI_ICR_CRXBFF_Pos)               /*!< 0x00000001 */

+#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */

+#define SWPMI_ICR_CTXBEF_Pos     (1U)

+#define SWPMI_ICR_CTXBEF_Msk     (0x1UL << SWPMI_ICR_CTXBEF_Pos)               /*!< 0x00000002 */

+#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */

+#define SWPMI_ICR_CRXBERF_Pos    (2U)

+#define SWPMI_ICR_CRXBERF_Msk    (0x1UL << SWPMI_ICR_CRXBERF_Pos)              /*!< 0x00000004 */

+#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */

+#define SWPMI_ICR_CRXOVRF_Pos    (3U)

+#define SWPMI_ICR_CRXOVRF_Msk    (0x1UL << SWPMI_ICR_CRXOVRF_Pos)              /*!< 0x00000008 */

+#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */

+#define SWPMI_ICR_CTXUNRF_Pos    (4U)

+#define SWPMI_ICR_CTXUNRF_Msk    (0x1UL << SWPMI_ICR_CTXUNRF_Pos)              /*!< 0x00000010 */

+#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */

+#define SWPMI_ICR_CTCF_Pos       (7U)

+#define SWPMI_ICR_CTCF_Msk       (0x1UL << SWPMI_ICR_CTCF_Pos)                 /*!< 0x00000080 */

+#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */

+#define SWPMI_ICR_CSRF_Pos       (8U)

+#define SWPMI_ICR_CSRF_Msk       (0x1UL << SWPMI_ICR_CSRF_Pos)                 /*!< 0x00000100 */

+#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */

+#define SWPMI_ICR_CRDYF_Pos      (11U)

+#define SWPMI_ICR_CRDYF_Msk      (0x1UL << SWPMI_ICR_CRDYF_Pos)                /*!< 0x00000800 */

+#define SWPMI_ICR_CRDYF          SWPMI_ICR_CRDYF_Msk                           /*!<Clear transceiver ready flag         */

+

+/*******************  Bit definition for SWPMI_IER register  ********************/

+#define SWPMI_IER_RXBFIE_Pos     (0U)

+#define SWPMI_IER_RXBFIE_Msk     (0x1UL << SWPMI_IER_RXBFIE_Pos)               /*!< 0x00000001 */

+#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */

+#define SWPMI_IER_TXBEIE_Pos     (1U)

+#define SWPMI_IER_TXBEIE_Msk     (0x1UL << SWPMI_IER_TXBEIE_Pos)               /*!< 0x00000002 */

+#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */

+#define SWPMI_IER_RXBERIE_Pos    (2U)

+#define SWPMI_IER_RXBERIE_Msk    (0x1UL << SWPMI_IER_RXBERIE_Pos)              /*!< 0x00000004 */

+#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */

+#define SWPMI_IER_RXOVRIE_Pos    (3U)

+#define SWPMI_IER_RXOVRIE_Msk    (0x1UL << SWPMI_IER_RXOVRIE_Pos)              /*!< 0x00000008 */

+#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */

+#define SWPMI_IER_TXUNRIE_Pos    (4U)

+#define SWPMI_IER_TXUNRIE_Msk    (0x1UL << SWPMI_IER_TXUNRIE_Pos)              /*!< 0x00000010 */

+#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */

+#define SWPMI_IER_RIE_Pos        (5U)

+#define SWPMI_IER_RIE_Msk        (0x1UL << SWPMI_IER_RIE_Pos)                  /*!< 0x00000020 */

+#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */

+#define SWPMI_IER_TIE_Pos        (6U)

+#define SWPMI_IER_TIE_Msk        (0x1UL << SWPMI_IER_TIE_Pos)                  /*!< 0x00000040 */

+#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */

+#define SWPMI_IER_TCIE_Pos       (7U)

+#define SWPMI_IER_TCIE_Msk       (0x1UL << SWPMI_IER_TCIE_Pos)                 /*!< 0x00000080 */

+#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */

+#define SWPMI_IER_SRIE_Pos       (8U)

+#define SWPMI_IER_SRIE_Msk       (0x1UL << SWPMI_IER_SRIE_Pos)                 /*!< 0x00000100 */

+#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */

+#define SWPMI_IER_RDYIE_Pos      (11U)

+#define SWPMI_IER_RDYIE_Msk      (0x1UL << SWPMI_IER_RDYIE_Pos)                /*!< 0x00000800 */

+#define SWPMI_IER_RDYIE          SWPMI_IER_RDYIE_Msk                           /*!<Transceiver ready interrupt enable          */

+

+/*******************  Bit definition for SWPMI_RFL register  ********************/

+#define SWPMI_RFL_RFL_Pos        (0U)

+#define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */

+#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */

+#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */

+

+/*******************  Bit definition for SWPMI_TDR register  ********************/

+#define SWPMI_TDR_TD_Pos         (0U)

+#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)            /*!< 0xFFFFFFFF */

+#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */

+

+/*******************  Bit definition for SWPMI_RDR register  ********************/

+#define SWPMI_RDR_RD_Pos         (0U)

+#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)            /*!< 0xFFFFFFFF */

+#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Recive Data Register           */

+

+

+/*******************  Bit definition for SWPMI_OR register  ********************/

+#define SWPMI_OR_TBYP_Pos        (0U)

+#define SWPMI_OR_TBYP_Msk        (0x1UL << SWPMI_OR_TBYP_Pos)                  /*!< 0x00000001 */

+#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */

+#define SWPMI_OR_CLASS_Pos       (1U)

+#define SWPMI_OR_CLASS_Msk       (0x1UL << SWPMI_OR_CLASS_Pos)                 /*!< 0x00000002 */

+#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP CLASS selection */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            Window WATCHDOG                                 */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for WWDG_CR register  ********************/

+#define WWDG_CR_T_Pos           (0U)

+#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */

+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */

+#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */

+#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */

+#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */

+#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */

+#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */

+#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */

+#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */

+

+#define WWDG_CR_WDGA_Pos        (7U)

+#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */

+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */

+

+/*******************  Bit definition for WWDG_CFR register  *******************/

+#define WWDG_CFR_W_Pos          (0U)

+#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */

+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */

+#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */

+#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */

+#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */

+#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */

+#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */

+#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */

+#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */

+

+#define WWDG_CFR_EWI_Pos        (9U)

+#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */

+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */

+

+#define WWDG_CFR_WDGTB_Pos      (11U)

+#define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */

+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */

+#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000800 */

+#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00001000 */

+#define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00002000 */

+

+/*******************  Bit definition for WWDG_SR register  ********************/

+#define WWDG_SR_EWIF_Pos        (0U)

+#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */

+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                DBG                                         */

+/*                                                                            */

+/******************************************************************************/

+/*********************************  DEVICE ID  ********************************/

+#define STM32H7_DEV_ID           0x450UL

+

+/********************  Bit definition for DBGMCU_IDCODE register  *************/

+#define DBGMCU_IDCODE_DEV_ID_Pos          (0U)

+#define DBGMCU_IDCODE_DEV_ID_Msk          (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */

+#define DBGMCU_IDCODE_DEV_ID              DBGMCU_IDCODE_DEV_ID_Msk

+#define DBGMCU_IDCODE_REV_ID_Pos          (16U)

+#define DBGMCU_IDCODE_REV_ID_Msk          (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */

+#define DBGMCU_IDCODE_REV_ID              DBGMCU_IDCODE_REV_ID_Msk

+

+/********************  Bit definition for DBGMCU_CR register  *****************/

+#define DBGMCU_CR_DBG_SLEEPD1_Pos         (0U)

+#define DBGMCU_CR_DBG_SLEEPD1_Msk         (0x1UL << DBGMCU_CR_DBG_SLEEPD1_Pos) /*!< 0x00000001 */

+#define DBGMCU_CR_DBG_SLEEPD1             DBGMCU_CR_DBG_SLEEPD1_Msk

+#define DBGMCU_CR_DBG_STOPD1_Pos          (1U)

+#define DBGMCU_CR_DBG_STOPD1_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD1_Pos)  /*!< 0x00000002 */

+#define DBGMCU_CR_DBG_STOPD1              DBGMCU_CR_DBG_STOPD1_Msk

+#define DBGMCU_CR_DBG_STANDBYD1_Pos       (2U)

+#define DBGMCU_CR_DBG_STANDBYD1_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos) /*!< 0x00000004 */

+#define DBGMCU_CR_DBG_STANDBYD1           DBGMCU_CR_DBG_STANDBYD1_Msk

+#define DBGMCU_CR_DBG_STOPD3_Pos          (7U)

+#define DBGMCU_CR_DBG_STOPD3_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos)  /*!< 0x00000080 */

+#define DBGMCU_CR_DBG_STOPD3              DBGMCU_CR_DBG_STOPD3_Msk

+#define DBGMCU_CR_DBG_STANDBYD3_Pos       (8U)

+#define DBGMCU_CR_DBG_STANDBYD3_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos) /*!< 0x00000100 */

+#define DBGMCU_CR_DBG_STANDBYD3           DBGMCU_CR_DBG_STANDBYD3_Msk

+#define DBGMCU_CR_DBG_TRACECKEN_Pos       (20U)

+#define DBGMCU_CR_DBG_TRACECKEN_Msk       (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */

+#define DBGMCU_CR_DBG_TRACECKEN           DBGMCU_CR_DBG_TRACECKEN_Msk

+#define DBGMCU_CR_DBG_CKD1EN_Pos          (21U)

+#define DBGMCU_CR_DBG_CKD1EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD1EN_Pos)  /*!< 0x00200000 */

+#define DBGMCU_CR_DBG_CKD1EN              DBGMCU_CR_DBG_CKD1EN_Msk

+#define DBGMCU_CR_DBG_CKD3EN_Pos          (22U)

+#define DBGMCU_CR_DBG_CKD3EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD3EN_Pos)  /*!< 0x00400000 */

+#define DBGMCU_CR_DBG_CKD3EN              DBGMCU_CR_DBG_CKD3EN_Msk

+#define DBGMCU_CR_DBG_TRGOEN_Pos          (28U)

+#define DBGMCU_CR_DBG_TRGOEN_Msk          (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)  /*!< 0x10000000 */

+#define DBGMCU_CR_DBG_TRGOEN              DBGMCU_CR_DBG_TRGOEN_Msk

+

+/********************  Bit definition for APB3FZ1 register  ************/

+#define DBGMCU_APB3FZ1_DBG_WWDG1_Pos      (6U)

+#define DBGMCU_APB3FZ1_DBG_WWDG1_Msk      (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB3FZ1_DBG_WWDG1          DBGMCU_APB3FZ1_DBG_WWDG1_Msk

+/********************  Bit definition for APB1LFZ1 register  ************/

+#define DBGMCU_APB1LFZ1_DBG_TIM2_Pos      (0U)

+#define DBGMCU_APB1LFZ1_DBG_TIM2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB1LFZ1_DBG_TIM2          DBGMCU_APB1LFZ1_DBG_TIM2_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM3_Pos      (1U)

+#define DBGMCU_APB1LFZ1_DBG_TIM3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB1LFZ1_DBG_TIM3          DBGMCU_APB1LFZ1_DBG_TIM3_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM4_Pos      (2U)

+#define DBGMCU_APB1LFZ1_DBG_TIM4_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */

+#define DBGMCU_APB1LFZ1_DBG_TIM4          DBGMCU_APB1LFZ1_DBG_TIM4_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM5_Pos      (3U)

+#define DBGMCU_APB1LFZ1_DBG_TIM5_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */

+#define DBGMCU_APB1LFZ1_DBG_TIM5          DBGMCU_APB1LFZ1_DBG_TIM5_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM6_Pos      (4U)

+#define DBGMCU_APB1LFZ1_DBG_TIM6_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */

+#define DBGMCU_APB1LFZ1_DBG_TIM6          DBGMCU_APB1LFZ1_DBG_TIM6_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM7_Pos      (5U)

+#define DBGMCU_APB1LFZ1_DBG_TIM7_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */

+#define DBGMCU_APB1LFZ1_DBG_TIM7          DBGMCU_APB1LFZ1_DBG_TIM7_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM12_Pos     (6U)

+#define DBGMCU_APB1LFZ1_DBG_TIM12_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB1LFZ1_DBG_TIM12         DBGMCU_APB1LFZ1_DBG_TIM12_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM13_Pos     (7U)

+#define DBGMCU_APB1LFZ1_DBG_TIM13_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB1LFZ1_DBG_TIM13         DBGMCU_APB1LFZ1_DBG_TIM13_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM14_Pos     (8U)

+#define DBGMCU_APB1LFZ1_DBG_TIM14_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */

+#define DBGMCU_APB1LFZ1_DBG_TIM14         DBGMCU_APB1LFZ1_DBG_TIM14_Msk

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos    (9U)

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1        DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C1_Pos      (21U)

+#define DBGMCU_APB1LFZ1_DBG_I2C1_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C1          DBGMCU_APB1LFZ1_DBG_I2C1_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C2_Pos      (22U)

+#define DBGMCU_APB1LFZ1_DBG_I2C2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C2          DBGMCU_APB1LFZ1_DBG_I2C2_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C3_Pos      (23U)

+#define DBGMCU_APB1LFZ1_DBG_I2C3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C3          DBGMCU_APB1LFZ1_DBG_I2C3_Msk

+

+/********************  Bit definition for APB1HFZ1 register  ************/

+#define DBGMCU_APB1HFZ1_DBG_FDCAN_Pos     (8U)

+#define DBGMCU_APB1HFZ1_DBG_FDCAN_Msk     (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_Pos) /*!< 0x00000100 */

+#define DBGMCU_APB1HFZ1_DBG_FDCAN         DBGMCU_APB1HFZ1_DBG_FDCAN_Msk

+/********************  Bit definition for APB2FZ1 register  ************/

+#define DBGMCU_APB2FZ1_DBG_TIM1_Pos       (0U)

+#define DBGMCU_APB2FZ1_DBG_TIM1_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB2FZ1_DBG_TIM1           DBGMCU_APB2FZ1_DBG_TIM1_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM8_Pos       (1U)

+#define DBGMCU_APB2FZ1_DBG_TIM8_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB2FZ1_DBG_TIM8           DBGMCU_APB2FZ1_DBG_TIM8_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM15_Pos      (16U)

+#define DBGMCU_APB2FZ1_DBG_TIM15_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB2FZ1_DBG_TIM15          DBGMCU_APB2FZ1_DBG_TIM15_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM16_Pos      (17U)

+#define DBGMCU_APB2FZ1_DBG_TIM16_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */

+#define DBGMCU_APB2FZ1_DBG_TIM16          DBGMCU_APB2FZ1_DBG_TIM16_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM17_Pos      (18U)

+#define DBGMCU_APB2FZ1_DBG_TIM17_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB2FZ1_DBG_TIM17          DBGMCU_APB2FZ1_DBG_TIM17_Msk

+#define DBGMCU_APB2FZ1_DBG_HRTIM_Pos      (29U)

+#define DBGMCU_APB2FZ1_DBG_HRTIM_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_HRTIM_Pos) /*!< 0x20000000 */

+#define DBGMCU_APB2FZ1_DBG_HRTIM          DBGMCU_APB2FZ1_DBG_HRTIM_Msk

+

+/********************  Bit definition for APB4FZ1 register  ************/

+#define DBGMCU_APB4FZ1_DBG_I2C4_Pos       (7U)

+#define DBGMCU_APB4FZ1_DBG_I2C4_Msk       (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB4FZ1_DBG_I2C4           DBGMCU_APB4FZ1_DBG_I2C4_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos     (9U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM2         DBGMCU_APB4FZ1_DBG_LPTIM2_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos     (10U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM3         DBGMCU_APB4FZ1_DBG_LPTIM3_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM4_Pos     (11U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM4_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos) /*!< 0x00000800 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM4         DBGMCU_APB4FZ1_DBG_LPTIM4_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM5_Pos     (12U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM5_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos) /*!< 0x00001000 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM5         DBGMCU_APB4FZ1_DBG_LPTIM5_Msk

+#define DBGMCU_APB4FZ1_DBG_RTC_Pos        (16U)

+#define DBGMCU_APB4FZ1_DBG_RTC_Msk        (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB4FZ1_DBG_RTC            DBGMCU_APB4FZ1_DBG_RTC_Msk

+#define DBGMCU_APB4FZ1_DBG_IWDG1_Pos      (18U)

+#define DBGMCU_APB4FZ1_DBG_IWDG1_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB4FZ1_DBG_IWDG1          DBGMCU_APB4FZ1_DBG_IWDG1_Msk

+/******************************************************************************/

+/*                                                                            */

+/*                        High Resolution Timer (HRTIM)                       */

+/*                                                                            */

+/******************************************************************************/

+/******************** Master Timer control register ***************************/

+#define HRTIM_MCR_CK_PSC_Pos          (0U)

+#define HRTIM_MCR_CK_PSC_Msk          (0x7UL << HRTIM_MCR_CK_PSC_Pos)          /*!< 0x00000007 */

+#define HRTIM_MCR_CK_PSC              HRTIM_MCR_CK_PSC_Msk                     /*!< Prescaler mask */

+#define HRTIM_MCR_CK_PSC_0            (0x1UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000001 */

+#define HRTIM_MCR_CK_PSC_1            (0x2UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000002 */

+#define HRTIM_MCR_CK_PSC_2            (0x4UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000004 */

+

+#define HRTIM_MCR_CONT_Pos            (3U)

+#define HRTIM_MCR_CONT_Msk            (0x1UL << HRTIM_MCR_CONT_Pos)            /*!< 0x00000008 */

+#define HRTIM_MCR_CONT                HRTIM_MCR_CONT_Msk                       /*!< Continuous mode */

+#define HRTIM_MCR_RETRIG_Pos          (4U)

+#define HRTIM_MCR_RETRIG_Msk          (0x1UL << HRTIM_MCR_RETRIG_Pos)          /*!< 0x00000010 */

+#define HRTIM_MCR_RETRIG              HRTIM_MCR_RETRIG_Msk                     /*!< Rettrigreable mode */

+#define HRTIM_MCR_HALF_Pos            (5U)

+#define HRTIM_MCR_HALF_Msk            (0x1UL << HRTIM_MCR_HALF_Pos)            /*!< 0x00000020 */

+#define HRTIM_MCR_HALF                HRTIM_MCR_HALF_Msk                       /*!< Half mode */

+

+#define HRTIM_MCR_SYNC_IN_Pos         (8U)

+#define HRTIM_MCR_SYNC_IN_Msk         (0x3UL << HRTIM_MCR_SYNC_IN_Pos)         /*!< 0x00000300 */

+#define HRTIM_MCR_SYNC_IN             HRTIM_MCR_SYNC_IN_Msk                    /*!< Synchronization input master */

+#define HRTIM_MCR_SYNC_IN_0           (0x1UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000100 */

+#define HRTIM_MCR_SYNC_IN_1           (0x2UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000200 */

+#define HRTIM_MCR_SYNCRSTM_Pos        (10U)

+#define HRTIM_MCR_SYNCRSTM_Msk        (0x1UL << HRTIM_MCR_SYNCRSTM_Pos)        /*!< 0x00000400 */

+#define HRTIM_MCR_SYNCRSTM            HRTIM_MCR_SYNCRSTM_Msk                   /*!< Synchronization reset master */

+#define HRTIM_MCR_SYNCSTRTM_Pos       (11U)

+#define HRTIM_MCR_SYNCSTRTM_Msk       (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos)       /*!< 0x00000800 */

+#define HRTIM_MCR_SYNCSTRTM           HRTIM_MCR_SYNCSTRTM_Msk                  /*!< Synchronization start master */

+#define HRTIM_MCR_SYNC_OUT_Pos        (12U)

+#define HRTIM_MCR_SYNC_OUT_Msk        (0x3UL << HRTIM_MCR_SYNC_OUT_Pos)        /*!< 0x00003000 */

+#define HRTIM_MCR_SYNC_OUT            HRTIM_MCR_SYNC_OUT_Msk                   /*!< Synchronization output master */

+#define HRTIM_MCR_SYNC_OUT_0          (0x1UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00001000 */

+#define HRTIM_MCR_SYNC_OUT_1          (0x2UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00002000 */

+#define HRTIM_MCR_SYNC_SRC_Pos        (14U)

+#define HRTIM_MCR_SYNC_SRC_Msk        (0x3UL << HRTIM_MCR_SYNC_SRC_Pos)        /*!< 0x0000C000 */

+#define HRTIM_MCR_SYNC_SRC            HRTIM_MCR_SYNC_SRC_Msk                   /*!< Synchronization source */

+#define HRTIM_MCR_SYNC_SRC_0          (0x1UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00004000 */

+#define HRTIM_MCR_SYNC_SRC_1          (0x2UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00008000 */

+

+#define HRTIM_MCR_MCEN_Pos            (16U)

+#define HRTIM_MCR_MCEN_Msk            (0x1UL << HRTIM_MCR_MCEN_Pos)            /*!< 0x00010000 */

+#define HRTIM_MCR_MCEN                HRTIM_MCR_MCEN_Msk                       /*!< Master counter enable */

+#define HRTIM_MCR_TACEN_Pos           (17U)

+#define HRTIM_MCR_TACEN_Msk           (0x1UL << HRTIM_MCR_TACEN_Pos)           /*!< 0x00020000 */

+#define HRTIM_MCR_TACEN               HRTIM_MCR_TACEN_Msk                      /*!< Timer A counter enable */

+#define HRTIM_MCR_TBCEN_Pos           (18U)

+#define HRTIM_MCR_TBCEN_Msk           (0x1UL << HRTIM_MCR_TBCEN_Pos)           /*!< 0x00040000 */

+#define HRTIM_MCR_TBCEN               HRTIM_MCR_TBCEN_Msk                      /*!< Timer B counter enable */

+#define HRTIM_MCR_TCCEN_Pos           (19U)

+#define HRTIM_MCR_TCCEN_Msk           (0x1UL << HRTIM_MCR_TCCEN_Pos)           /*!< 0x00080000 */

+#define HRTIM_MCR_TCCEN               HRTIM_MCR_TCCEN_Msk                      /*!< Timer C counter enable */

+#define HRTIM_MCR_TDCEN_Pos           (20U)

+#define HRTIM_MCR_TDCEN_Msk           (0x1UL << HRTIM_MCR_TDCEN_Pos)           /*!< 0x00100000 */

+#define HRTIM_MCR_TDCEN               HRTIM_MCR_TDCEN_Msk                      /*!< Timer D counter enable */

+#define HRTIM_MCR_TECEN_Pos           (21U)

+#define HRTIM_MCR_TECEN_Msk           (0x1UL << HRTIM_MCR_TECEN_Pos)           /*!< 0x00200000 */

+#define HRTIM_MCR_TECEN               HRTIM_MCR_TECEN_Msk                      /*!< Timer E counter enable */

+

+#define HRTIM_MCR_DACSYNC_Pos         (25U)

+#define HRTIM_MCR_DACSYNC_Msk         (0x3UL << HRTIM_MCR_DACSYNC_Pos)         /*!< 0x06000000 */

+#define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC sychronization mask */

+#define HRTIM_MCR_DACSYNC_0           (0x1UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x02000000 */

+#define HRTIM_MCR_DACSYNC_1           (0x2UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x04000000 */

+

+#define HRTIM_MCR_PREEN_Pos           (27U)

+#define HRTIM_MCR_PREEN_Msk           (0x1UL << HRTIM_MCR_PREEN_Pos)           /*!< 0x08000000 */

+#define HRTIM_MCR_PREEN               HRTIM_MCR_PREEN_Msk                      /*!< Master preload enable */

+#define HRTIM_MCR_MREPU_Pos           (29U)

+#define HRTIM_MCR_MREPU_Msk           (0x1UL << HRTIM_MCR_MREPU_Pos)           /*!< 0x20000000 */

+#define HRTIM_MCR_MREPU               HRTIM_MCR_MREPU_Msk                      /*!< Master repetition update */

+

+#define HRTIM_MCR_BRSTDMA_Pos         (30U)

+#define HRTIM_MCR_BRSTDMA_Msk         (0x3UL << HRTIM_MCR_BRSTDMA_Pos)         /*!< 0xC0000000 */

+#define HRTIM_MCR_BRSTDMA             HRTIM_MCR_BRSTDMA_Msk                    /*!< Burst DMA update */

+#define HRTIM_MCR_BRSTDMA_0           (0x1UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x40000000 */

+#define HRTIM_MCR_BRSTDMA_1           (0x2UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x80000000 */

+

+/******************** Master Timer Interrupt status register ******************/

+#define HRTIM_MISR_MCMP1_Pos          (0U)

+#define HRTIM_MISR_MCMP1_Msk          (0x1UL << HRTIM_MISR_MCMP1_Pos)          /*!< 0x00000001 */

+#define HRTIM_MISR_MCMP1              HRTIM_MISR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag */

+#define HRTIM_MISR_MCMP2_Pos          (1U)

+#define HRTIM_MISR_MCMP2_Msk          (0x1UL << HRTIM_MISR_MCMP2_Pos)          /*!< 0x00000002 */

+#define HRTIM_MISR_MCMP2              HRTIM_MISR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag */

+#define HRTIM_MISR_MCMP3_Pos          (2U)

+#define HRTIM_MISR_MCMP3_Msk          (0x1UL << HRTIM_MISR_MCMP3_Pos)          /*!< 0x00000004 */

+#define HRTIM_MISR_MCMP3              HRTIM_MISR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag */

+#define HRTIM_MISR_MCMP4_Pos          (3U)

+#define HRTIM_MISR_MCMP4_Msk          (0x1UL << HRTIM_MISR_MCMP4_Pos)          /*!< 0x00000008 */

+#define HRTIM_MISR_MCMP4              HRTIM_MISR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag */

+#define HRTIM_MISR_MREP_Pos           (4U)

+#define HRTIM_MISR_MREP_Msk           (0x1UL << HRTIM_MISR_MREP_Pos)           /*!< 0x00000010 */

+#define HRTIM_MISR_MREP               HRTIM_MISR_MREP_Msk                      /*!< Master Repetition interrupt flag */

+#define HRTIM_MISR_SYNC_Pos           (5U)

+#define HRTIM_MISR_SYNC_Msk           (0x1UL << HRTIM_MISR_SYNC_Pos)           /*!< 0x00000020 */

+#define HRTIM_MISR_SYNC               HRTIM_MISR_SYNC_Msk                      /*!< Synchronization input interrupt flag */

+#define HRTIM_MISR_MUPD_Pos           (6U)

+#define HRTIM_MISR_MUPD_Msk           (0x1UL << HRTIM_MISR_MUPD_Pos)           /*!< 0x00000040 */

+#define HRTIM_MISR_MUPD               HRTIM_MISR_MUPD_Msk                      /*!< Master update interrupt flag */

+

+/******************** Master Timer Interrupt clear register *******************/

+#define HRTIM_MICR_MCMP1_Pos          (0U)

+#define HRTIM_MICR_MCMP1_Msk          (0x1UL << HRTIM_MICR_MCMP1_Pos)          /*!< 0x00000001 */

+#define HRTIM_MICR_MCMP1              HRTIM_MICR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag clear */

+#define HRTIM_MICR_MCMP2_Pos          (1U)

+#define HRTIM_MICR_MCMP2_Msk          (0x1UL << HRTIM_MICR_MCMP2_Pos)          /*!< 0x00000002 */

+#define HRTIM_MICR_MCMP2              HRTIM_MICR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag clear */

+#define HRTIM_MICR_MCMP3_Pos          (2U)

+#define HRTIM_MICR_MCMP3_Msk          (0x1UL << HRTIM_MICR_MCMP3_Pos)          /*!< 0x00000004 */

+#define HRTIM_MICR_MCMP3              HRTIM_MICR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag clear */

+#define HRTIM_MICR_MCMP4_Pos          (3U)

+#define HRTIM_MICR_MCMP4_Msk          (0x1UL << HRTIM_MICR_MCMP4_Pos)          /*!< 0x00000008 */

+#define HRTIM_MICR_MCMP4              HRTIM_MICR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag clear */

+#define HRTIM_MICR_MREP_Pos           (4U)

+#define HRTIM_MICR_MREP_Msk           (0x1UL << HRTIM_MICR_MREP_Pos)           /*!< 0x00000010 */

+#define HRTIM_MICR_MREP               HRTIM_MICR_MREP_Msk                      /*!< Master Repetition interrupt flag clear */

+#define HRTIM_MICR_SYNC_Pos           (5U)

+#define HRTIM_MICR_SYNC_Msk           (0x1UL << HRTIM_MICR_SYNC_Pos)           /*!< 0x00000020 */

+#define HRTIM_MICR_SYNC               HRTIM_MICR_SYNC_Msk                      /*!< Synchronization input interrupt flag clear */

+#define HRTIM_MICR_MUPD_Pos           (6U)

+#define HRTIM_MICR_MUPD_Msk           (0x1UL << HRTIM_MICR_MUPD_Pos)           /*!< 0x00000040 */

+#define HRTIM_MICR_MUPD               HRTIM_MICR_MUPD_Msk                      /*!< Master update interrupt flag clear */

+

+/******************** Master Timer DMA/Interrupt enable register **************/

+#define HRTIM_MDIER_MCMP1IE_Pos       (0U)

+#define HRTIM_MDIER_MCMP1IE_Msk       (0x1UL << HRTIM_MDIER_MCMP1IE_Pos)       /*!< 0x00000001 */

+#define HRTIM_MDIER_MCMP1IE           HRTIM_MDIER_MCMP1IE_Msk                  /*!< Master compare 1 interrupt enable */

+#define HRTIM_MDIER_MCMP2IE_Pos       (1U)

+#define HRTIM_MDIER_MCMP2IE_Msk       (0x1UL << HRTIM_MDIER_MCMP2IE_Pos)       /*!< 0x00000002 */

+#define HRTIM_MDIER_MCMP2IE           HRTIM_MDIER_MCMP2IE_Msk                  /*!< Master compare 2 interrupt enable */

+#define HRTIM_MDIER_MCMP3IE_Pos       (2U)

+#define HRTIM_MDIER_MCMP3IE_Msk       (0x1UL << HRTIM_MDIER_MCMP3IE_Pos)       /*!< 0x00000004 */

+#define HRTIM_MDIER_MCMP3IE           HRTIM_MDIER_MCMP3IE_Msk                  /*!< Master compare 3 interrupt enable */

+#define HRTIM_MDIER_MCMP4IE_Pos       (3U)

+#define HRTIM_MDIER_MCMP4IE_Msk       (0x1UL << HRTIM_MDIER_MCMP4IE_Pos)       /*!< 0x00000008 */

+#define HRTIM_MDIER_MCMP4IE           HRTIM_MDIER_MCMP4IE_Msk                  /*!< Master compare 4 interrupt enable */

+#define HRTIM_MDIER_MREPIE_Pos        (4U)

+#define HRTIM_MDIER_MREPIE_Msk        (0x1UL << HRTIM_MDIER_MREPIE_Pos)        /*!< 0x00000010 */

+#define HRTIM_MDIER_MREPIE            HRTIM_MDIER_MREPIE_Msk                   /*!< Master Repetition interrupt enable */

+#define HRTIM_MDIER_SYNCIE_Pos        (5U)

+#define HRTIM_MDIER_SYNCIE_Msk        (0x1UL << HRTIM_MDIER_SYNCIE_Pos)        /*!< 0x00000020 */

+#define HRTIM_MDIER_SYNCIE            HRTIM_MDIER_SYNCIE_Msk                   /*!< Synchronization input interrupt enable */

+#define HRTIM_MDIER_MUPDIE_Pos        (6U)

+#define HRTIM_MDIER_MUPDIE_Msk        (0x1UL << HRTIM_MDIER_MUPDIE_Pos)        /*!< 0x00000040 */

+#define HRTIM_MDIER_MUPDIE            HRTIM_MDIER_MUPDIE_Msk                   /*!< Master update interrupt enable */

+

+#define HRTIM_MDIER_MCMP1DE_Pos       (16U)

+#define HRTIM_MDIER_MCMP1DE_Msk       (0x1UL << HRTIM_MDIER_MCMP1DE_Pos)       /*!< 0x00010000 */

+#define HRTIM_MDIER_MCMP1DE           HRTIM_MDIER_MCMP1DE_Msk                  /*!< Master compare 1 DMA enable */

+#define HRTIM_MDIER_MCMP2DE_Pos       (17U)

+#define HRTIM_MDIER_MCMP2DE_Msk       (0x1UL << HRTIM_MDIER_MCMP2DE_Pos)       /*!< 0x00020000 */

+#define HRTIM_MDIER_MCMP2DE           HRTIM_MDIER_MCMP2DE_Msk                  /*!< Master compare 2 DMA enable */

+#define HRTIM_MDIER_MCMP3DE_Pos       (18U)

+#define HRTIM_MDIER_MCMP3DE_Msk       (0x1UL << HRTIM_MDIER_MCMP3DE_Pos)       /*!< 0x00040000 */

+#define HRTIM_MDIER_MCMP3DE           HRTIM_MDIER_MCMP3DE_Msk                  /*!< Master compare 3 DMA enable */

+#define HRTIM_MDIER_MCMP4DE_Pos       (19U)

+#define HRTIM_MDIER_MCMP4DE_Msk       (0x1UL << HRTIM_MDIER_MCMP4DE_Pos)       /*!< 0x00080000 */

+#define HRTIM_MDIER_MCMP4DE           HRTIM_MDIER_MCMP4DE_Msk                  /*!< Master compare 4 DMA enable */

+#define HRTIM_MDIER_MREPDE_Pos        (20U)

+#define HRTIM_MDIER_MREPDE_Msk        (0x1UL << HRTIM_MDIER_MREPDE_Pos)        /*!< 0x00100000 */

+#define HRTIM_MDIER_MREPDE            HRTIM_MDIER_MREPDE_Msk                   /*!< Master Repetition DMA enable */

+#define HRTIM_MDIER_SYNCDE_Pos        (21U)

+#define HRTIM_MDIER_SYNCDE_Msk        (0x1UL << HRTIM_MDIER_SYNCDE_Pos)        /*!< 0x00200000 */

+#define HRTIM_MDIER_SYNCDE            HRTIM_MDIER_SYNCDE_Msk                   /*!< Synchronization input DMA enable */

+#define HRTIM_MDIER_MUPDDE_Pos        (22U)

+#define HRTIM_MDIER_MUPDDE_Msk        (0x1UL << HRTIM_MDIER_MUPDDE_Pos)        /*!< 0x00400000 */

+#define HRTIM_MDIER_MUPDDE            HRTIM_MDIER_MUPDDE_Msk                   /*!< Master update DMA enable */

+

+/*******************  Bit definition for HRTIM_MCNTR register  ****************/

+#define HRTIM_MCNTR_MCNTR_Pos         (0U)

+#define HRTIM_MCNTR_MCNTR_Msk         (0xFFFFUL << HRTIM_MCNTR_MCNTR_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_MCNTR_MCNTR             HRTIM_MCNTR_MCNTR_Msk                    /*!<Counter Value */

+

+/*******************  Bit definition for HRTIM_MPER register  *****************/

+#define HRTIM_MPER_MPER_Pos           (0U)

+#define HRTIM_MPER_MPER_Msk           (0xFFFFUL << HRTIM_MPER_MPER_Pos)        /*!< 0x0000FFFF */

+#define HRTIM_MPER_MPER               HRTIM_MPER_MPER_Msk                      /*!< Period Value */

+

+/*******************  Bit definition for HRTIM_MREP register  *****************/

+#define HRTIM_MREP_MREP_Pos           (0U)

+#define HRTIM_MREP_MREP_Msk           (0xFFUL << HRTIM_MREP_MREP_Pos)          /*!< 0x000000FF */

+#define HRTIM_MREP_MREP               HRTIM_MREP_MREP_Msk                      /*!<Repetition Value */

+

+/*******************  Bit definition for HRTIM_MCMP1R register  *****************/

+#define HRTIM_MCMP1R_MCMP1R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP1R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP1R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP1R           HRTIM_MCMP1R_MCMP1R_Msk                  /*!<Compare Value */

+

+/*******************  Bit definition for HRTIM_MCMP2R register  *****************/

+#define HRTIM_MCMP1R_MCMP2R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP2R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP2R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP2R           HRTIM_MCMP1R_MCMP2R_Msk                  /*!<Compare Value */

+

+/*******************  Bit definition for HRTIM_MCMP3R register  *****************/

+#define HRTIM_MCMP1R_MCMP3R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP3R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP3R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP3R           HRTIM_MCMP1R_MCMP3R_Msk                  /*!<Compare Value */

+

+/*******************  Bit definition for HRTIM_MCMP4R register  *****************/

+#define HRTIM_MCMP1R_MCMP4R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP4R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP4R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP4R           HRTIM_MCMP1R_MCMP4R_Msk                  /*!<Compare Value */

+

+/******************** Slave control register **********************************/

+#define HRTIM_TIMCR_CK_PSC_Pos        (0U)

+#define HRTIM_TIMCR_CK_PSC_Msk        (0x7UL << HRTIM_TIMCR_CK_PSC_Pos)        /*!< 0x00000007 */

+#define HRTIM_TIMCR_CK_PSC            HRTIM_TIMCR_CK_PSC_Msk                   /*!< Slave prescaler mask*/

+#define HRTIM_TIMCR_CK_PSC_0          (0x1UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000001 */

+#define HRTIM_TIMCR_CK_PSC_1          (0x2UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000002 */

+#define HRTIM_TIMCR_CK_PSC_2          (0x4UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000004 */

+

+#define HRTIM_TIMCR_CONT_Pos          (3U)

+#define HRTIM_TIMCR_CONT_Msk          (0x1UL << HRTIM_TIMCR_CONT_Pos)          /*!< 0x00000008 */

+#define HRTIM_TIMCR_CONT              HRTIM_TIMCR_CONT_Msk                     /*!< Slave continuous mode */

+#define HRTIM_TIMCR_RETRIG_Pos        (4U)

+#define HRTIM_TIMCR_RETRIG_Msk        (0x1UL << HRTIM_TIMCR_RETRIG_Pos)        /*!< 0x00000010 */

+#define HRTIM_TIMCR_RETRIG            HRTIM_TIMCR_RETRIG_Msk                   /*!< Slave Retrigreable mode */

+#define HRTIM_TIMCR_HALF_Pos          (5U)

+#define HRTIM_TIMCR_HALF_Msk          (0x1UL << HRTIM_TIMCR_HALF_Pos)          /*!< 0x00000020 */

+#define HRTIM_TIMCR_HALF              HRTIM_TIMCR_HALF_Msk                     /*!< Slave Half mode */

+#define HRTIM_TIMCR_PSHPLL_Pos        (6U)

+#define HRTIM_TIMCR_PSHPLL_Msk        (0x1UL << HRTIM_TIMCR_PSHPLL_Pos)        /*!< 0x00000040 */

+#define HRTIM_TIMCR_PSHPLL            HRTIM_TIMCR_PSHPLL_Msk                   /*!< Slave push-pull mode */

+

+#define HRTIM_TIMCR_SYNCRST_Pos       (10U)

+#define HRTIM_TIMCR_SYNCRST_Msk       (0x1UL << HRTIM_TIMCR_SYNCRST_Pos)       /*!< 0x00000400 */

+#define HRTIM_TIMCR_SYNCRST           HRTIM_TIMCR_SYNCRST_Msk                  /*!< Slave synchronization resets */

+#define HRTIM_TIMCR_SYNCSTRT_Pos      (11U)

+#define HRTIM_TIMCR_SYNCSTRT_Msk      (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos)      /*!< 0x00000800 */

+#define HRTIM_TIMCR_SYNCSTRT          HRTIM_TIMCR_SYNCSTRT_Msk                 /*!< Slave synchronization starts */

+

+#define HRTIM_TIMCR_DELCMP2_Pos       (12U)

+#define HRTIM_TIMCR_DELCMP2_Msk       (0x3UL << HRTIM_TIMCR_DELCMP2_Pos)       /*!< 0x00003000 */

+#define HRTIM_TIMCR_DELCMP2           HRTIM_TIMCR_DELCMP2_Msk                  /*!< Slave delayed compartor 2 mode mask */

+#define HRTIM_TIMCR_DELCMP2_0         (0x1UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00001000 */

+#define HRTIM_TIMCR_DELCMP2_1         (0x2UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00002000 */

+#define HRTIM_TIMCR_DELCMP4_Pos       (14U)

+#define HRTIM_TIMCR_DELCMP4_Msk       (0x3UL << HRTIM_TIMCR_DELCMP4_Pos)       /*!< 0x0000C000 */

+#define HRTIM_TIMCR_DELCMP4           HRTIM_TIMCR_DELCMP4_Msk                  /*!< Slave delayed compartor 4 mode mask */

+#define HRTIM_TIMCR_DELCMP4_0         (0x1UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00004000 */

+#define HRTIM_TIMCR_DELCMP4_1         (0x2UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00008000 */

+

+#define HRTIM_TIMCR_TREPU_Pos         (17U)

+#define HRTIM_TIMCR_TREPU_Msk         (0x1UL << HRTIM_TIMCR_TREPU_Pos)         /*!< 0x00020000 */

+#define HRTIM_TIMCR_TREPU             HRTIM_TIMCR_TREPU_Msk                    /*!< Slave repetition update */

+#define HRTIM_TIMCR_TRSTU_Pos         (18U)

+#define HRTIM_TIMCR_TRSTU_Msk         (0x1UL << HRTIM_TIMCR_TRSTU_Pos)         /*!< 0x00040000 */

+#define HRTIM_TIMCR_TRSTU             HRTIM_TIMCR_TRSTU_Msk                    /*!< Slave reset update */

+#define HRTIM_TIMCR_TAU_Pos           (19U)

+#define HRTIM_TIMCR_TAU_Msk           (0x1UL << HRTIM_TIMCR_TAU_Pos)           /*!< 0x00080000 */

+#define HRTIM_TIMCR_TAU               HRTIM_TIMCR_TAU_Msk                      /*!< Slave Timer A update reserved for TIM A */

+#define HRTIM_TIMCR_TBU_Pos           (20U)

+#define HRTIM_TIMCR_TBU_Msk           (0x1UL << HRTIM_TIMCR_TBU_Pos)           /*!< 0x00100000 */

+#define HRTIM_TIMCR_TBU               HRTIM_TIMCR_TBU_Msk                      /*!< Slave Timer B update reserved for TIM B */

+#define HRTIM_TIMCR_TCU_Pos           (21U)

+#define HRTIM_TIMCR_TCU_Msk           (0x1UL << HRTIM_TIMCR_TCU_Pos)           /*!< 0x00200000 */

+#define HRTIM_TIMCR_TCU               HRTIM_TIMCR_TCU_Msk                      /*!< Slave Timer C update reserved for TIM C */

+#define HRTIM_TIMCR_TDU_Pos           (22U)

+#define HRTIM_TIMCR_TDU_Msk           (0x1UL << HRTIM_TIMCR_TDU_Pos)           /*!< 0x00400000 */

+#define HRTIM_TIMCR_TDU               HRTIM_TIMCR_TDU_Msk                      /*!< Slave Timer D update reserved for TIM D */

+#define HRTIM_TIMCR_TEU_Pos           (23U)

+#define HRTIM_TIMCR_TEU_Msk           (0x1UL << HRTIM_TIMCR_TEU_Pos)           /*!< 0x00800000 */

+#define HRTIM_TIMCR_TEU               HRTIM_TIMCR_TEU_Msk                      /*!< Slave Timer E update reserved for TIM E */

+#define HRTIM_TIMCR_MSTU_Pos          (24U)

+#define HRTIM_TIMCR_MSTU_Msk          (0x1UL << HRTIM_TIMCR_MSTU_Pos)          /*!< 0x01000000 */

+#define HRTIM_TIMCR_MSTU              HRTIM_TIMCR_MSTU_Msk                     /*!< Master Update */

+

+#define HRTIM_TIMCR_DACSYNC_Pos       (25U)

+#define HRTIM_TIMCR_DACSYNC_Msk       (0x3UL << HRTIM_TIMCR_DACSYNC_Pos)       /*!< 0x06000000 */

+#define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC sychronization mask */

+#define HRTIM_TIMCR_DACSYNC_0         (0x1UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x02000000 */

+#define HRTIM_TIMCR_DACSYNC_1         (0x2UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x04000000 */

+#define HRTIM_TIMCR_PREEN_Pos         (27U)

+#define HRTIM_TIMCR_PREEN_Msk         (0x1UL << HRTIM_TIMCR_PREEN_Pos)         /*!< 0x08000000 */

+#define HRTIM_TIMCR_PREEN             HRTIM_TIMCR_PREEN_Msk                    /*!< Slave preload enable */

+

+#define HRTIM_TIMCR_UPDGAT_Pos        (28U)

+#define HRTIM_TIMCR_UPDGAT_Msk        (0xFUL << HRTIM_TIMCR_UPDGAT_Pos)        /*!< 0xF0000000 */

+#define HRTIM_TIMCR_UPDGAT            HRTIM_TIMCR_UPDGAT_Msk                   /*!< Slave update gating mask */

+#define HRTIM_TIMCR_UPDGAT_0          (0x1UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x10000000 */

+#define HRTIM_TIMCR_UPDGAT_1          (0x2UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x20000000 */

+#define HRTIM_TIMCR_UPDGAT_2          (0x4UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x40000000 */

+#define HRTIM_TIMCR_UPDGAT_3          (0x8UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x80000000 */

+

+/******************** Slave Interrupt status register **************************/

+#define HRTIM_TIMISR_CMP1_Pos         (0U)

+#define HRTIM_TIMISR_CMP1_Msk         (0x1UL << HRTIM_TIMISR_CMP1_Pos)         /*!< 0x00000001 */

+#define HRTIM_TIMISR_CMP1             HRTIM_TIMISR_CMP1_Msk                    /*!< Slave compare 1 interrupt flag */

+#define HRTIM_TIMISR_CMP2_Pos         (1U)

+#define HRTIM_TIMISR_CMP2_Msk         (0x1UL << HRTIM_TIMISR_CMP2_Pos)         /*!< 0x00000002 */

+#define HRTIM_TIMISR_CMP2             HRTIM_TIMISR_CMP2_Msk                    /*!< Slave compare 2 interrupt flag */

+#define HRTIM_TIMISR_CMP3_Pos         (2U)

+#define HRTIM_TIMISR_CMP3_Msk         (0x1UL << HRTIM_TIMISR_CMP3_Pos)         /*!< 0x00000004 */

+#define HRTIM_TIMISR_CMP3             HRTIM_TIMISR_CMP3_Msk                    /*!< Slave compare 3 interrupt flag */

+#define HRTIM_TIMISR_CMP4_Pos         (3U)

+#define HRTIM_TIMISR_CMP4_Msk         (0x1UL << HRTIM_TIMISR_CMP4_Pos)         /*!< 0x00000008 */

+#define HRTIM_TIMISR_CMP4             HRTIM_TIMISR_CMP4_Msk                    /*!< Slave compare 4 interrupt flag */

+#define HRTIM_TIMISR_REP_Pos          (4U)

+#define HRTIM_TIMISR_REP_Msk          (0x1UL << HRTIM_TIMISR_REP_Pos)          /*!< 0x00000010 */

+#define HRTIM_TIMISR_REP              HRTIM_TIMISR_REP_Msk                     /*!< Slave repetition interrupt flag */

+#define HRTIM_TIMISR_UPD_Pos          (6U)

+#define HRTIM_TIMISR_UPD_Msk          (0x1UL << HRTIM_TIMISR_UPD_Pos)          /*!< 0x00000040 */

+#define HRTIM_TIMISR_UPD              HRTIM_TIMISR_UPD_Msk                     /*!< Slave update interrupt flag */

+#define HRTIM_TIMISR_CPT1_Pos         (7U)

+#define HRTIM_TIMISR_CPT1_Msk         (0x1UL << HRTIM_TIMISR_CPT1_Pos)         /*!< 0x00000080 */

+#define HRTIM_TIMISR_CPT1             HRTIM_TIMISR_CPT1_Msk                    /*!< Slave capture 1 interrupt flag */

+#define HRTIM_TIMISR_CPT2_Pos         (8U)

+#define HRTIM_TIMISR_CPT2_Msk         (0x1UL << HRTIM_TIMISR_CPT2_Pos)         /*!< 0x00000100 */

+#define HRTIM_TIMISR_CPT2             HRTIM_TIMISR_CPT2_Msk                    /*!< Slave capture 2 interrupt flag */

+#define HRTIM_TIMISR_SET1_Pos         (9U)

+#define HRTIM_TIMISR_SET1_Msk         (0x1UL << HRTIM_TIMISR_SET1_Pos)         /*!< 0x00000200 */

+#define HRTIM_TIMISR_SET1             HRTIM_TIMISR_SET1_Msk                    /*!< Slave output 1 set interrupt flag */

+#define HRTIM_TIMISR_RST1_Pos         (10U)

+#define HRTIM_TIMISR_RST1_Msk         (0x1UL << HRTIM_TIMISR_RST1_Pos)         /*!< 0x00000400 */

+#define HRTIM_TIMISR_RST1             HRTIM_TIMISR_RST1_Msk                    /*!< Slave output 1 reset interrupt flag */

+#define HRTIM_TIMISR_SET2_Pos         (11U)

+#define HRTIM_TIMISR_SET2_Msk         (0x1UL << HRTIM_TIMISR_SET2_Pos)         /*!< 0x00000800 */

+#define HRTIM_TIMISR_SET2             HRTIM_TIMISR_SET2_Msk                    /*!< Slave output 2 set interrupt flag */

+#define HRTIM_TIMISR_RST2_Pos         (12U)

+#define HRTIM_TIMISR_RST2_Msk         (0x1UL << HRTIM_TIMISR_RST2_Pos)         /*!< 0x00001000 */

+#define HRTIM_TIMISR_RST2             HRTIM_TIMISR_RST2_Msk                    /*!< Slave output 2 reset interrupt flag */

+#define HRTIM_TIMISR_RST_Pos          (13U)

+#define HRTIM_TIMISR_RST_Msk          (0x1UL << HRTIM_TIMISR_RST_Pos)          /*!< 0x00002000 */

+#define HRTIM_TIMISR_RST              HRTIM_TIMISR_RST_Msk                     /*!< Slave reset interrupt flag */

+#define HRTIM_TIMISR_DLYPRT_Pos       (14U)

+#define HRTIM_TIMISR_DLYPRT_Msk       (0x1UL << HRTIM_TIMISR_DLYPRT_Pos)       /*!< 0x00004000 */

+#define HRTIM_TIMISR_DLYPRT           HRTIM_TIMISR_DLYPRT_Msk                  /*!< Slave output 1 delay protection interrupt flag */

+#define HRTIM_TIMISR_CPPSTAT_Pos      (16U)

+#define HRTIM_TIMISR_CPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos)      /*!< 0x00010000 */

+#define HRTIM_TIMISR_CPPSTAT          HRTIM_TIMISR_CPPSTAT_Msk                 /*!< Slave current push-pull flag */

+#define HRTIM_TIMISR_IPPSTAT_Pos      (17U)

+#define HRTIM_TIMISR_IPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos)      /*!< 0x00020000 */

+#define HRTIM_TIMISR_IPPSTAT          HRTIM_TIMISR_IPPSTAT_Msk                 /*!< Slave idle push-pull flag */

+#define HRTIM_TIMISR_O1STAT_Pos       (18U)

+#define HRTIM_TIMISR_O1STAT_Msk       (0x1UL << HRTIM_TIMISR_O1STAT_Pos)       /*!< 0x00040000 */

+#define HRTIM_TIMISR_O1STAT           HRTIM_TIMISR_O1STAT_Msk                  /*!< Slave output 1 state flag */

+#define HRTIM_TIMISR_O2STAT_Pos       (19U)

+#define HRTIM_TIMISR_O2STAT_Msk       (0x1UL << HRTIM_TIMISR_O2STAT_Pos)       /*!< 0x00080000 */

+#define HRTIM_TIMISR_O2STAT           HRTIM_TIMISR_O2STAT_Msk                  /*!< Slave output 2 state flag */

+#define HRTIM_TIMISR_O1CPY_Pos        (20U)

+#define HRTIM_TIMISR_O1CPY_Msk        (0x1UL << HRTIM_TIMISR_O1CPY_Pos)        /*!< 0x00100000 */

+#define HRTIM_TIMISR_O1CPY            HRTIM_TIMISR_O1CPY_Msk                   /*!< Slave output 1 copy flag */

+#define HRTIM_TIMISR_O2CPY_Pos        (21U)

+#define HRTIM_TIMISR_O2CPY_Msk        (0x1UL << HRTIM_TIMISR_O2CPY_Pos)        /*!< 0x00200000 */

+#define HRTIM_TIMISR_O2CPY            HRTIM_TIMISR_O2CPY_Msk                   /*!< Slave output 2 copy flag */

+

+/******************** Slave Interrupt clear register **************************/

+#define HRTIM_TIMICR_CMP1C_Pos        (0U)

+#define HRTIM_TIMICR_CMP1C_Msk        (0x1UL << HRTIM_TIMICR_CMP1C_Pos)        /*!< 0x00000001 */

+#define HRTIM_TIMICR_CMP1C            HRTIM_TIMICR_CMP1C_Msk                   /*!< Slave compare 1 clear flag */

+#define HRTIM_TIMICR_CMP2C_Pos        (1U)

+#define HRTIM_TIMICR_CMP2C_Msk        (0x1UL << HRTIM_TIMICR_CMP2C_Pos)        /*!< 0x00000002 */

+#define HRTIM_TIMICR_CMP2C            HRTIM_TIMICR_CMP2C_Msk                   /*!< Slave compare 2 clear flag */

+#define HRTIM_TIMICR_CMP3C_Pos        (2U)

+#define HRTIM_TIMICR_CMP3C_Msk        (0x1UL << HRTIM_TIMICR_CMP3C_Pos)        /*!< 0x00000004 */

+#define HRTIM_TIMICR_CMP3C            HRTIM_TIMICR_CMP3C_Msk                   /*!< Slave compare 3 clear flag */

+#define HRTIM_TIMICR_CMP4C_Pos        (3U)

+#define HRTIM_TIMICR_CMP4C_Msk        (0x1UL << HRTIM_TIMICR_CMP4C_Pos)        /*!< 0x00000008 */

+#define HRTIM_TIMICR_CMP4C            HRTIM_TIMICR_CMP4C_Msk                   /*!< Slave compare 4 clear flag */

+#define HRTIM_TIMICR_REPC_Pos         (4U)

+#define HRTIM_TIMICR_REPC_Msk         (0x1UL << HRTIM_TIMICR_REPC_Pos)         /*!< 0x00000010 */

+#define HRTIM_TIMICR_REPC             HRTIM_TIMICR_REPC_Msk                    /*!< Slave repetition clear flag */

+#define HRTIM_TIMICR_UPDC_Pos         (6U)

+#define HRTIM_TIMICR_UPDC_Msk         (0x1UL << HRTIM_TIMICR_UPDC_Pos)         /*!< 0x00000040 */

+#define HRTIM_TIMICR_UPDC             HRTIM_TIMICR_UPDC_Msk                    /*!< Slave update clear flag */

+#define HRTIM_TIMICR_CPT1C_Pos        (7U)

+#define HRTIM_TIMICR_CPT1C_Msk        (0x1UL << HRTIM_TIMICR_CPT1C_Pos)        /*!< 0x00000080 */

+#define HRTIM_TIMICR_CPT1C            HRTIM_TIMICR_CPT1C_Msk                   /*!< Slave capture 1 clear flag */

+#define HRTIM_TIMICR_CPT2C_Pos        (8U)

+#define HRTIM_TIMICR_CPT2C_Msk        (0x1UL << HRTIM_TIMICR_CPT2C_Pos)        /*!< 0x00000100 */

+#define HRTIM_TIMICR_CPT2C            HRTIM_TIMICR_CPT2C_Msk                   /*!< Slave capture 2 clear flag */

+#define HRTIM_TIMICR_SET1C_Pos        (9U)

+#define HRTIM_TIMICR_SET1C_Msk        (0x1UL << HRTIM_TIMICR_SET1C_Pos)        /*!< 0x00000200 */

+#define HRTIM_TIMICR_SET1C            HRTIM_TIMICR_SET1C_Msk                   /*!< Slave output 1 set clear flag */

+#define HRTIM_TIMICR_RST1C_Pos        (10U)

+#define HRTIM_TIMICR_RST1C_Msk        (0x1UL << HRTIM_TIMICR_RST1C_Pos)        /*!< 0x00000400 */

+#define HRTIM_TIMICR_RST1C            HRTIM_TIMICR_RST1C_Msk                   /*!< Slave output 1 reset clear flag */

+#define HRTIM_TIMICR_SET2C_Pos        (11U)

+#define HRTIM_TIMICR_SET2C_Msk        (0x1UL << HRTIM_TIMICR_SET2C_Pos)        /*!< 0x00000800 */

+#define HRTIM_TIMICR_SET2C            HRTIM_TIMICR_SET2C_Msk                   /*!< Slave output 2 set clear flag */

+#define HRTIM_TIMICR_RST2C_Pos        (12U)

+#define HRTIM_TIMICR_RST2C_Msk        (0x1UL << HRTIM_TIMICR_RST2C_Pos)        /*!< 0x00001000 */

+#define HRTIM_TIMICR_RST2C            HRTIM_TIMICR_RST2C_Msk                   /*!< Slave output 2 reset clear flag */

+#define HRTIM_TIMICR_RSTC_Pos         (13U)

+#define HRTIM_TIMICR_RSTC_Msk         (0x1UL << HRTIM_TIMICR_RSTC_Pos)         /*!< 0x00002000 */

+#define HRTIM_TIMICR_RSTC             HRTIM_TIMICR_RSTC_Msk                    /*!< Slave reset clear flag */

+#define HRTIM_TIMICR_DLYPRTC_Pos      (14U)

+#define HRTIM_TIMICR_DLYPRTC_Msk      (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos)      /*!< 0x00004000 */

+#define HRTIM_TIMICR_DLYPRTC          HRTIM_TIMICR_DLYPRTC_Msk                 /*!< Slave output 1 delay protection clear flag */

+

+/******************** Slave DMA/Interrupt enable register *********************/

+#define HRTIM_TIMDIER_CMP1IE_Pos      (0U)

+#define HRTIM_TIMDIER_CMP1IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos)      /*!< 0x00000001 */

+#define HRTIM_TIMDIER_CMP1IE          HRTIM_TIMDIER_CMP1IE_Msk                 /*!< Slave compare 1 interrupt enable */

+#define HRTIM_TIMDIER_CMP2IE_Pos      (1U)

+#define HRTIM_TIMDIER_CMP2IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos)      /*!< 0x00000002 */

+#define HRTIM_TIMDIER_CMP2IE          HRTIM_TIMDIER_CMP2IE_Msk                 /*!< Slave compare 2 interrupt enable */

+#define HRTIM_TIMDIER_CMP3IE_Pos      (2U)

+#define HRTIM_TIMDIER_CMP3IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos)      /*!< 0x00000004 */

+#define HRTIM_TIMDIER_CMP3IE          HRTIM_TIMDIER_CMP3IE_Msk                 /*!< Slave compare 3 interrupt enable */

+#define HRTIM_TIMDIER_CMP4IE_Pos      (3U)

+#define HRTIM_TIMDIER_CMP4IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos)      /*!< 0x00000008 */

+#define HRTIM_TIMDIER_CMP4IE          HRTIM_TIMDIER_CMP4IE_Msk                 /*!< Slave compare 4 interrupt enable */

+#define HRTIM_TIMDIER_REPIE_Pos       (4U)

+#define HRTIM_TIMDIER_REPIE_Msk       (0x1UL << HRTIM_TIMDIER_REPIE_Pos)       /*!< 0x00000010 */

+#define HRTIM_TIMDIER_REPIE           HRTIM_TIMDIER_REPIE_Msk                  /*!< Slave repetition interrupt enable */

+#define HRTIM_TIMDIER_UPDIE_Pos       (6U)

+#define HRTIM_TIMDIER_UPDIE_Msk       (0x1UL << HRTIM_TIMDIER_UPDIE_Pos)       /*!< 0x00000040 */

+#define HRTIM_TIMDIER_UPDIE           HRTIM_TIMDIER_UPDIE_Msk                  /*!< Slave update interrupt enable */

+#define HRTIM_TIMDIER_CPT1IE_Pos      (7U)

+#define HRTIM_TIMDIER_CPT1IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos)      /*!< 0x00000080 */

+#define HRTIM_TIMDIER_CPT1IE          HRTIM_TIMDIER_CPT1IE_Msk                 /*!< Slave capture 1 interrupt enable */

+#define HRTIM_TIMDIER_CPT2IE_Pos      (8U)

+#define HRTIM_TIMDIER_CPT2IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos)      /*!< 0x00000100 */

+#define HRTIM_TIMDIER_CPT2IE          HRTIM_TIMDIER_CPT2IE_Msk                 /*!< Slave capture 2 interrupt enable */

+#define HRTIM_TIMDIER_SET1IE_Pos      (9U)

+#define HRTIM_TIMDIER_SET1IE_Msk      (0x1UL << HRTIM_TIMDIER_SET1IE_Pos)      /*!< 0x00000200 */

+#define HRTIM_TIMDIER_SET1IE          HRTIM_TIMDIER_SET1IE_Msk                 /*!< Slave output 1 set interrupt enable */

+#define HRTIM_TIMDIER_RST1IE_Pos      (10U)

+#define HRTIM_TIMDIER_RST1IE_Msk      (0x1UL << HRTIM_TIMDIER_RST1IE_Pos)      /*!< 0x00000400 */

+#define HRTIM_TIMDIER_RST1IE          HRTIM_TIMDIER_RST1IE_Msk                 /*!< Slave output 1 reset interrupt enable */

+#define HRTIM_TIMDIER_SET2IE_Pos      (11U)

+#define HRTIM_TIMDIER_SET2IE_Msk      (0x1UL << HRTIM_TIMDIER_SET2IE_Pos)      /*!< 0x00000800 */

+#define HRTIM_TIMDIER_SET2IE          HRTIM_TIMDIER_SET2IE_Msk                 /*!< Slave output 2 set interrupt enable */

+#define HRTIM_TIMDIER_RST2IE_Pos      (12U)

+#define HRTIM_TIMDIER_RST2IE_Msk      (0x1UL << HRTIM_TIMDIER_RST2IE_Pos)      /*!< 0x00001000 */

+#define HRTIM_TIMDIER_RST2IE          HRTIM_TIMDIER_RST2IE_Msk                 /*!< Slave output 2 reset interrupt enable */

+#define HRTIM_TIMDIER_RSTIE_Pos       (13U)

+#define HRTIM_TIMDIER_RSTIE_Msk       (0x1UL << HRTIM_TIMDIER_RSTIE_Pos)       /*!< 0x00002000 */

+#define HRTIM_TIMDIER_RSTIE           HRTIM_TIMDIER_RSTIE_Msk                  /*!< Slave reset interrupt enable */

+#define HRTIM_TIMDIER_DLYPRTIE_Pos    (14U)

+#define HRTIM_TIMDIER_DLYPRTIE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos)    /*!< 0x00004000 */

+#define HRTIM_TIMDIER_DLYPRTIE        HRTIM_TIMDIER_DLYPRTIE_Msk               /*!< Slave delay protection interrupt enable */

+

+#define HRTIM_TIMDIER_CMP1DE_Pos      (16U)

+#define HRTIM_TIMDIER_CMP1DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos)      /*!< 0x00010000 */

+#define HRTIM_TIMDIER_CMP1DE          HRTIM_TIMDIER_CMP1DE_Msk                 /*!< Slave compare 1 request enable */

+#define HRTIM_TIMDIER_CMP2DE_Pos      (17U)

+#define HRTIM_TIMDIER_CMP2DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos)      /*!< 0x00020000 */

+#define HRTIM_TIMDIER_CMP2DE          HRTIM_TIMDIER_CMP2DE_Msk                 /*!< Slave compare 2 request enable */

+#define HRTIM_TIMDIER_CMP3DE_Pos      (18U)

+#define HRTIM_TIMDIER_CMP3DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos)      /*!< 0x00040000 */

+#define HRTIM_TIMDIER_CMP3DE          HRTIM_TIMDIER_CMP3DE_Msk                 /*!< Slave compare 3 request enable */

+#define HRTIM_TIMDIER_CMP4DE_Pos      (19U)

+#define HRTIM_TIMDIER_CMP4DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos)      /*!< 0x00080000 */

+#define HRTIM_TIMDIER_CMP4DE          HRTIM_TIMDIER_CMP4DE_Msk                 /*!< Slave compare 4 request enable */

+#define HRTIM_TIMDIER_REPDE_Pos       (20U)

+#define HRTIM_TIMDIER_REPDE_Msk       (0x1UL << HRTIM_TIMDIER_REPDE_Pos)       /*!< 0x00100000 */

+#define HRTIM_TIMDIER_REPDE           HRTIM_TIMDIER_REPDE_Msk                  /*!< Slave repetition request enable */

+#define HRTIM_TIMDIER_UPDDE_Pos       (22U)

+#define HRTIM_TIMDIER_UPDDE_Msk       (0x1UL << HRTIM_TIMDIER_UPDDE_Pos)       /*!< 0x00400000 */

+#define HRTIM_TIMDIER_UPDDE           HRTIM_TIMDIER_UPDDE_Msk                  /*!< Slave update request enable */

+#define HRTIM_TIMDIER_CPT1DE_Pos      (23U)

+#define HRTIM_TIMDIER_CPT1DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos)      /*!< 0x00800000 */

+#define HRTIM_TIMDIER_CPT1DE          HRTIM_TIMDIER_CPT1DE_Msk                 /*!< Slave capture 1 request enable */

+#define HRTIM_TIMDIER_CPT2DE_Pos      (24U)

+#define HRTIM_TIMDIER_CPT2DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos)      /*!< 0x01000000 */

+#define HRTIM_TIMDIER_CPT2DE          HRTIM_TIMDIER_CPT2DE_Msk                 /*!< Slave capture 2 request enable */

+#define HRTIM_TIMDIER_SET1DE_Pos      (25U)

+#define HRTIM_TIMDIER_SET1DE_Msk      (0x1UL << HRTIM_TIMDIER_SET1DE_Pos)      /*!< 0x02000000 */

+#define HRTIM_TIMDIER_SET1DE          HRTIM_TIMDIER_SET1DE_Msk                 /*!< Slave output 1 set request enable */

+#define HRTIM_TIMDIER_RST1DE_Pos      (26U)

+#define HRTIM_TIMDIER_RST1DE_Msk      (0x1UL << HRTIM_TIMDIER_RST1DE_Pos)      /*!< 0x04000000 */

+#define HRTIM_TIMDIER_RST1DE          HRTIM_TIMDIER_RST1DE_Msk                 /*!< Slave output 1 reset request enable */

+#define HRTIM_TIMDIER_SET2DE_Pos      (27U)

+#define HRTIM_TIMDIER_SET2DE_Msk      (0x1UL << HRTIM_TIMDIER_SET2DE_Pos)      /*!< 0x08000000 */

+#define HRTIM_TIMDIER_SET2DE          HRTIM_TIMDIER_SET2DE_Msk                 /*!< Slave output 2 set request enable */

+#define HRTIM_TIMDIER_RST2DE_Pos      (28U)

+#define HRTIM_TIMDIER_RST2DE_Msk      (0x1UL << HRTIM_TIMDIER_RST2DE_Pos)      /*!< 0x10000000 */

+#define HRTIM_TIMDIER_RST2DE          HRTIM_TIMDIER_RST2DE_Msk                 /*!< Slave output 2 reset request enable */

+#define HRTIM_TIMDIER_RSTDE_Pos       (29U)

+#define HRTIM_TIMDIER_RSTDE_Msk       (0x1UL << HRTIM_TIMDIER_RSTDE_Pos)       /*!< 0x20000000 */

+#define HRTIM_TIMDIER_RSTDE           HRTIM_TIMDIER_RSTDE_Msk                  /*!< Slave reset request enable */

+#define HRTIM_TIMDIER_DLYPRTDE_Pos    (30U)

+#define HRTIM_TIMDIER_DLYPRTDE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos)    /*!< 0x40000000 */

+#define HRTIM_TIMDIER_DLYPRTDE        HRTIM_TIMDIER_DLYPRTDE_Msk               /*!< Slavedelay protection request enable */

+

+/******************  Bit definition for HRTIM_CNTR register  ****************/

+#define HRTIM_CNTR_CNTR_Pos           (0U)

+#define HRTIM_CNTR_CNTR_Msk           (0xFFFFUL << HRTIM_CNTR_CNTR_Pos)        /*!< 0x0000FFFF */

+#define HRTIM_CNTR_CNTR               HRTIM_CNTR_CNTR_Msk                      /*!< Counter Value */

+

+/*******************  Bit definition for HRTIM_PER register  *****************/

+#define HRTIM_PER_PER_Pos             (0U)

+#define HRTIM_PER_PER_Msk             (0xFFFFUL << HRTIM_PER_PER_Pos)          /*!< 0x0000FFFF */

+#define HRTIM_PER_PER                 HRTIM_PER_PER_Msk                        /*!< Period Value */

+

+/*******************  Bit definition for HRTIM_REP register  *****************/

+#define HRTIM_REP_REP_Pos             (0U)

+#define HRTIM_REP_REP_Msk             (0xFFUL << HRTIM_REP_REP_Pos)            /*!< 0x000000FF */

+#define HRTIM_REP_REP                 HRTIM_REP_REP_Msk                        /*!< Repetition Value */

+

+/*******************  Bit definition for HRTIM_CMP1R register  *****************/

+#define HRTIM_CMP1R_CMP1R_Pos         (0U)

+#define HRTIM_CMP1R_CMP1R_Msk         (0xFFFFUL << HRTIM_CMP1R_CMP1R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP1R_CMP1R             HRTIM_CMP1R_CMP1R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP1CR register  *****************/

+#define HRTIM_CMP1CR_CMP1CR_Pos       (0U)

+#define HRTIM_CMP1CR_CMP1CR_Msk       (0xFFFFFFFFUL << HRTIM_CMP1CR_CMP1CR_Pos) /*!< 0xFFFFFFFF */

+#define HRTIM_CMP1CR_CMP1CR           HRTIM_CMP1CR_CMP1CR_Msk                  /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP2R register  *****************/

+#define HRTIM_CMP2R_CMP2R_Pos         (0U)

+#define HRTIM_CMP2R_CMP2R_Msk         (0xFFFFUL << HRTIM_CMP2R_CMP2R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP2R_CMP2R             HRTIM_CMP2R_CMP2R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP3R register  *****************/

+#define HRTIM_CMP3R_CMP3R_Pos         (0U)

+#define HRTIM_CMP3R_CMP3R_Msk         (0xFFFFUL << HRTIM_CMP3R_CMP3R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP3R_CMP3R             HRTIM_CMP3R_CMP3R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP4R register  *****************/

+#define HRTIM_CMP4R_CMP4R_Pos         (0U)

+#define HRTIM_CMP4R_CMP4R_Msk         (0xFFFFUL << HRTIM_CMP4R_CMP4R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP4R_CMP4R             HRTIM_CMP4R_CMP4R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CPT1R register  ****************/

+#define HRTIM_CPT1R_CPT1R_Pos         (0U)

+#define HRTIM_CPT1R_CPT1R_Msk         (0xFFFFUL << HRTIM_CPT1R_CPT1R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CPT1R_CPT1R             HRTIM_CPT1R_CPT1R_Msk                    /*!< Capture Value */

+

+/*******************  Bit definition for HRTIM_CPT2R register  ****************/

+#define HRTIM_CPT2R_CPT2R_Pos         (0U)

+#define HRTIM_CPT2R_CPT2R_Msk         (0xFFFFUL << HRTIM_CPT2R_CPT2R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CPT2R_CPT2R             HRTIM_CPT2R_CPT2R_Msk                    /*!< Capture Value */

+

+/******************** Bit definition for Slave Deadtime register **************/

+#define HRTIM_DTR_DTR_Pos             (0U)

+#define HRTIM_DTR_DTR_Msk             (0x1FFUL << HRTIM_DTR_DTR_Pos)           /*!< 0x000001FF */

+#define HRTIM_DTR_DTR                 HRTIM_DTR_DTR_Msk                        /*!< Dead time rising value */

+#define HRTIM_DTR_DTR_0               (0x001UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000001 */

+#define HRTIM_DTR_DTR_1               (0x002UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000002 */

+#define HRTIM_DTR_DTR_2               (0x004UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000004 */

+#define HRTIM_DTR_DTR_3               (0x008UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000008 */

+#define HRTIM_DTR_DTR_4               (0x010UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000010 */

+#define HRTIM_DTR_DTR_5               (0x020UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000020 */

+#define HRTIM_DTR_DTR_6               (0x040UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000040 */

+#define HRTIM_DTR_DTR_7               (0x080UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000080 */

+#define HRTIM_DTR_DTR_8               (0x100UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000100 */

+#define HRTIM_DTR_SDTR_Pos            (9U)

+#define HRTIM_DTR_SDTR_Msk            (0x1UL << HRTIM_DTR_SDTR_Pos)            /*!< 0x00000200 */

+#define HRTIM_DTR_SDTR                HRTIM_DTR_SDTR_Msk                       /*!< Sign dead time rising value */

+#define HRTIM_DTR_DTPRSC_Pos          (10U)

+#define HRTIM_DTR_DTPRSC_Msk          (0x7UL << HRTIM_DTR_DTPRSC_Pos)          /*!< 0x00001C00 */

+#define HRTIM_DTR_DTPRSC              HRTIM_DTR_DTPRSC_Msk                     /*!< Dead time prescaler */

+#define HRTIM_DTR_DTPRSC_0            (0x1UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000400 */

+#define HRTIM_DTR_DTPRSC_1            (0x2UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000800 */

+#define HRTIM_DTR_DTPRSC_2            (0x4UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00001000 */

+#define HRTIM_DTR_DTRSLK_Pos          (14U)

+#define HRTIM_DTR_DTRSLK_Msk          (0x1UL << HRTIM_DTR_DTRSLK_Pos)          /*!< 0x00004000 */

+#define HRTIM_DTR_DTRSLK              HRTIM_DTR_DTRSLK_Msk                     /*!< Dead time rising sign lock */

+#define HRTIM_DTR_DTRLK_Pos           (15U)

+#define HRTIM_DTR_DTRLK_Msk           (0x1UL << HRTIM_DTR_DTRLK_Pos)           /*!< 0x00008000 */

+#define HRTIM_DTR_DTRLK               HRTIM_DTR_DTRLK_Msk                      /*!< Dead time rising lock */

+#define HRTIM_DTR_DTF_Pos             (16U)

+#define HRTIM_DTR_DTF_Msk             (0x1FFUL << HRTIM_DTR_DTF_Pos)           /*!< 0x01FF0000 */

+#define HRTIM_DTR_DTF                 HRTIM_DTR_DTF_Msk                        /*!< Dead time falling value */

+#define HRTIM_DTR_DTF_0               (0x001UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00010000 */

+#define HRTIM_DTR_DTF_1               (0x002UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00020000 */

+#define HRTIM_DTR_DTF_2               (0x004UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00040000 */

+#define HRTIM_DTR_DTF_3               (0x008UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00080000 */

+#define HRTIM_DTR_DTF_4               (0x010UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00100000 */

+#define HRTIM_DTR_DTF_5               (0x020UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00200000 */

+#define HRTIM_DTR_DTF_6               (0x040UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00400000 */

+#define HRTIM_DTR_DTF_7               (0x080UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00800000 */

+#define HRTIM_DTR_DTF_8               (0x100UL << HRTIM_DTR_DTF_Pos)            /*!< 0x01000000 */

+#define HRTIM_DTR_SDTF_Pos            (25U)

+#define HRTIM_DTR_SDTF_Msk            (0x1UL << HRTIM_DTR_SDTF_Pos)            /*!< 0x02000000 */

+#define HRTIM_DTR_SDTF                HRTIM_DTR_SDTF_Msk                       /*!< Sign dead time falling value */

+#define HRTIM_DTR_DTFSLK_Pos          (30U)

+#define HRTIM_DTR_DTFSLK_Msk          (0x1UL << HRTIM_DTR_DTFSLK_Pos)          /*!< 0x40000000 */

+#define HRTIM_DTR_DTFSLK              HRTIM_DTR_DTFSLK_Msk                     /*!< Dead time falling sign lock */

+#define HRTIM_DTR_DTFLK_Pos           (31U)

+#define HRTIM_DTR_DTFLK_Msk           (0x1UL << HRTIM_DTR_DTFLK_Pos)           /*!< 0x80000000 */

+#define HRTIM_DTR_DTFLK               HRTIM_DTR_DTFLK_Msk                      /*!< Dead time falling lock */

+

+/**** Bit definition for Slave Output 1 set register **************************/

+#define HRTIM_SET1R_SST_Pos           (0U)

+#define HRTIM_SET1R_SST_Msk           (0x1UL << HRTIM_SET1R_SST_Pos)           /*!< 0x00000001 */

+#define HRTIM_SET1R_SST               HRTIM_SET1R_SST_Msk                      /*!< software set trigger */

+#define HRTIM_SET1R_RESYNC_Pos        (1U)

+#define HRTIM_SET1R_RESYNC_Msk        (0x1UL << HRTIM_SET1R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_SET1R_RESYNC            HRTIM_SET1R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_SET1R_PER_Pos           (2U)

+#define HRTIM_SET1R_PER_Msk           (0x1UL << HRTIM_SET1R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_SET1R_PER               HRTIM_SET1R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_SET1R_CMP1_Pos          (3U)

+#define HRTIM_SET1R_CMP1_Msk          (0x1UL << HRTIM_SET1R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_SET1R_CMP1              HRTIM_SET1R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_SET1R_CMP2_Pos          (4U)

+#define HRTIM_SET1R_CMP2_Msk          (0x1UL << HRTIM_SET1R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_SET1R_CMP2              HRTIM_SET1R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_SET1R_CMP3_Pos          (5U)

+#define HRTIM_SET1R_CMP3_Msk          (0x1UL << HRTIM_SET1R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_SET1R_CMP3              HRTIM_SET1R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_SET1R_CMP4_Pos          (6U)

+#define HRTIM_SET1R_CMP4_Msk          (0x1UL << HRTIM_SET1R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_SET1R_CMP4              HRTIM_SET1R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_SET1R_MSTPER_Pos        (7U)

+#define HRTIM_SET1R_MSTPER_Msk        (0x1UL << HRTIM_SET1R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_SET1R_MSTPER            HRTIM_SET1R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_SET1R_MSTCMP1_Pos       (8U)

+#define HRTIM_SET1R_MSTCMP1_Msk       (0x1UL << HRTIM_SET1R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_SET1R_MSTCMP1           HRTIM_SET1R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_SET1R_MSTCMP2_Pos       (9U)

+#define HRTIM_SET1R_MSTCMP2_Msk       (0x1UL << HRTIM_SET1R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_SET1R_MSTCMP2           HRTIM_SET1R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_SET1R_MSTCMP3_Pos       (10U)

+#define HRTIM_SET1R_MSTCMP3_Msk       (0x1UL << HRTIM_SET1R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_SET1R_MSTCMP3           HRTIM_SET1R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_SET1R_MSTCMP4_Pos       (11U)

+#define HRTIM_SET1R_MSTCMP4_Msk       (0x1UL << HRTIM_SET1R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_SET1R_MSTCMP4           HRTIM_SET1R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_SET1R_TIMEVNT1_Pos      (12U)

+#define HRTIM_SET1R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_SET1R_TIMEVNT1          HRTIM_SET1R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_SET1R_TIMEVNT2_Pos      (13U)

+#define HRTIM_SET1R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_SET1R_TIMEVNT2          HRTIM_SET1R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_SET1R_TIMEVNT3_Pos      (14U)

+#define HRTIM_SET1R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_SET1R_TIMEVNT3          HRTIM_SET1R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_SET1R_TIMEVNT4_Pos      (15U)

+#define HRTIM_SET1R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_SET1R_TIMEVNT4          HRTIM_SET1R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_SET1R_TIMEVNT5_Pos      (16U)

+#define HRTIM_SET1R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_SET1R_TIMEVNT5          HRTIM_SET1R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_SET1R_TIMEVNT6_Pos      (17U)

+#define HRTIM_SET1R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_SET1R_TIMEVNT6          HRTIM_SET1R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_SET1R_TIMEVNT7_Pos      (18U)

+#define HRTIM_SET1R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_SET1R_TIMEVNT7          HRTIM_SET1R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_SET1R_TIMEVNT8_Pos      (19U)

+#define HRTIM_SET1R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_SET1R_TIMEVNT8          HRTIM_SET1R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_SET1R_TIMEVNT9_Pos      (20U)

+#define HRTIM_SET1R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_SET1R_TIMEVNT9          HRTIM_SET1R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_SET1R_EXTVNT1_Pos       (21U)

+#define HRTIM_SET1R_EXTVNT1_Msk       (0x1UL << HRTIM_SET1R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_SET1R_EXTVNT1           HRTIM_SET1R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_SET1R_EXTVNT2_Pos       (22U)

+#define HRTIM_SET1R_EXTVNT2_Msk       (0x1UL << HRTIM_SET1R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_SET1R_EXTVNT2           HRTIM_SET1R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_SET1R_EXTVNT3_Pos       (23U)

+#define HRTIM_SET1R_EXTVNT3_Msk       (0x1UL << HRTIM_SET1R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_SET1R_EXTVNT3           HRTIM_SET1R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_SET1R_EXTVNT4_Pos       (24U)

+#define HRTIM_SET1R_EXTVNT4_Msk       (0x1UL << HRTIM_SET1R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_SET1R_EXTVNT4           HRTIM_SET1R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_SET1R_EXTVNT5_Pos       (25U)

+#define HRTIM_SET1R_EXTVNT5_Msk       (0x1UL << HRTIM_SET1R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_SET1R_EXTVNT5           HRTIM_SET1R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_SET1R_EXTVNT6_Pos       (26U)

+#define HRTIM_SET1R_EXTVNT6_Msk       (0x1UL << HRTIM_SET1R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_SET1R_EXTVNT6           HRTIM_SET1R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_SET1R_EXTVNT7_Pos       (27U)

+#define HRTIM_SET1R_EXTVNT7_Msk       (0x1UL << HRTIM_SET1R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_SET1R_EXTVNT7           HRTIM_SET1R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_SET1R_EXTVNT8_Pos       (28U)

+#define HRTIM_SET1R_EXTVNT8_Msk       (0x1UL << HRTIM_SET1R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_SET1R_EXTVNT8           HRTIM_SET1R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_SET1R_EXTVNT9_Pos       (29U)

+#define HRTIM_SET1R_EXTVNT9_Msk       (0x1UL << HRTIM_SET1R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_SET1R_EXTVNT9           HRTIM_SET1R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_SET1R_EXTVNT10_Pos      (30U)

+#define HRTIM_SET1R_EXTVNT10_Msk      (0x1UL << HRTIM_SET1R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_SET1R_EXTVNT10          HRTIM_SET1R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_SET1R_UPDATE_Pos        (31U)

+#define HRTIM_SET1R_UPDATE_Msk        (0x1UL << HRTIM_SET1R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_SET1R_UPDATE            HRTIM_SET1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+/**** Bit definition for Slave Output 1 reset register ************************/

+#define HRTIM_RST1R_SRT_Pos           (0U)

+#define HRTIM_RST1R_SRT_Msk           (0x1UL << HRTIM_RST1R_SRT_Pos)           /*!< 0x00000001 */

+#define HRTIM_RST1R_SRT               HRTIM_RST1R_SRT_Msk                      /*!< software reset trigger */

+#define HRTIM_RST1R_RESYNC_Pos        (1U)

+#define HRTIM_RST1R_RESYNC_Msk        (0x1UL << HRTIM_RST1R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_RST1R_RESYNC            HRTIM_RST1R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_RST1R_PER_Pos           (2U)

+#define HRTIM_RST1R_PER_Msk           (0x1UL << HRTIM_RST1R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_RST1R_PER               HRTIM_RST1R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_RST1R_CMP1_Pos          (3U)

+#define HRTIM_RST1R_CMP1_Msk          (0x1UL << HRTIM_RST1R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_RST1R_CMP1              HRTIM_RST1R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_RST1R_CMP2_Pos          (4U)

+#define HRTIM_RST1R_CMP2_Msk          (0x1UL << HRTIM_RST1R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_RST1R_CMP2              HRTIM_RST1R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_RST1R_CMP3_Pos          (5U)

+#define HRTIM_RST1R_CMP3_Msk          (0x1UL << HRTIM_RST1R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_RST1R_CMP3              HRTIM_RST1R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_RST1R_CMP4_Pos          (6U)

+#define HRTIM_RST1R_CMP4_Msk          (0x1UL << HRTIM_RST1R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_RST1R_CMP4              HRTIM_RST1R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_RST1R_MSTPER_Pos        (7U)

+#define HRTIM_RST1R_MSTPER_Msk        (0x1UL << HRTIM_RST1R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_RST1R_MSTPER            HRTIM_RST1R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_RST1R_MSTCMP1_Pos       (8U)

+#define HRTIM_RST1R_MSTCMP1_Msk       (0x1UL << HRTIM_RST1R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_RST1R_MSTCMP1           HRTIM_RST1R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_RST1R_MSTCMP2_Pos       (9U)

+#define HRTIM_RST1R_MSTCMP2_Msk       (0x1UL << HRTIM_RST1R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_RST1R_MSTCMP2           HRTIM_RST1R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_RST1R_MSTCMP3_Pos       (10U)

+#define HRTIM_RST1R_MSTCMP3_Msk       (0x1UL << HRTIM_RST1R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_RST1R_MSTCMP3           HRTIM_RST1R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_RST1R_MSTCMP4_Pos       (11U)

+#define HRTIM_RST1R_MSTCMP4_Msk       (0x1UL << HRTIM_RST1R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_RST1R_MSTCMP4           HRTIM_RST1R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_RST1R_TIMEVNT1_Pos      (12U)

+#define HRTIM_RST1R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_RST1R_TIMEVNT1          HRTIM_RST1R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_RST1R_TIMEVNT2_Pos      (13U)

+#define HRTIM_RST1R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_RST1R_TIMEVNT2          HRTIM_RST1R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_RST1R_TIMEVNT3_Pos      (14U)

+#define HRTIM_RST1R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_RST1R_TIMEVNT3          HRTIM_RST1R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_RST1R_TIMEVNT4_Pos      (15U)

+#define HRTIM_RST1R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_RST1R_TIMEVNT4          HRTIM_RST1R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_RST1R_TIMEVNT5_Pos      (16U)

+#define HRTIM_RST1R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_RST1R_TIMEVNT5          HRTIM_RST1R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_RST1R_TIMEVNT6_Pos      (17U)

+#define HRTIM_RST1R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_RST1R_TIMEVNT6          HRTIM_RST1R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_RST1R_TIMEVNT7_Pos      (18U)

+#define HRTIM_RST1R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_RST1R_TIMEVNT7          HRTIM_RST1R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_RST1R_TIMEVNT8_Pos      (19U)

+#define HRTIM_RST1R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_RST1R_TIMEVNT8          HRTIM_RST1R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_RST1R_TIMEVNT9_Pos      (20U)

+#define HRTIM_RST1R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_RST1R_TIMEVNT9          HRTIM_RST1R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_RST1R_EXTVNT1_Pos       (21U)

+#define HRTIM_RST1R_EXTVNT1_Msk       (0x1UL << HRTIM_RST1R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_RST1R_EXTVNT1           HRTIM_RST1R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_RST1R_EXTVNT2_Pos       (22U)

+#define HRTIM_RST1R_EXTVNT2_Msk       (0x1UL << HRTIM_RST1R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_RST1R_EXTVNT2           HRTIM_RST1R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_RST1R_EXTVNT3_Pos       (23U)

+#define HRTIM_RST1R_EXTVNT3_Msk       (0x1UL << HRTIM_RST1R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_RST1R_EXTVNT3           HRTIM_RST1R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_RST1R_EXTVNT4_Pos       (24U)

+#define HRTIM_RST1R_EXTVNT4_Msk       (0x1UL << HRTIM_RST1R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_RST1R_EXTVNT4           HRTIM_RST1R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_RST1R_EXTVNT5_Pos       (25U)

+#define HRTIM_RST1R_EXTVNT5_Msk       (0x1UL << HRTIM_RST1R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_RST1R_EXTVNT5           HRTIM_RST1R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_RST1R_EXTVNT6_Pos       (26U)

+#define HRTIM_RST1R_EXTVNT6_Msk       (0x1UL << HRTIM_RST1R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_RST1R_EXTVNT6           HRTIM_RST1R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_RST1R_EXTVNT7_Pos       (27U)

+#define HRTIM_RST1R_EXTVNT7_Msk       (0x1UL << HRTIM_RST1R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_RST1R_EXTVNT7           HRTIM_RST1R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_RST1R_EXTVNT8_Pos       (28U)

+#define HRTIM_RST1R_EXTVNT8_Msk       (0x1UL << HRTIM_RST1R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_RST1R_EXTVNT8           HRTIM_RST1R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_RST1R_EXTVNT9_Pos       (29U)

+#define HRTIM_RST1R_EXTVNT9_Msk       (0x1UL << HRTIM_RST1R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_RST1R_EXTVNT9           HRTIM_RST1R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_RST1R_EXTVNT10_Pos      (30U)

+#define HRTIM_RST1R_EXTVNT10_Msk      (0x1UL << HRTIM_RST1R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_RST1R_EXTVNT10          HRTIM_RST1R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_RST1R_UPDATE_Pos        (31U)

+#define HRTIM_RST1R_UPDATE_Msk        (0x1UL << HRTIM_RST1R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_RST1R_UPDATE            HRTIM_RST1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+

+/**** Bit definition for Slave Output 2 set register **************************/

+#define HRTIM_SET2R_SST_Pos           (0U)

+#define HRTIM_SET2R_SST_Msk           (0x1UL << HRTIM_SET2R_SST_Pos)           /*!< 0x00000001 */

+#define HRTIM_SET2R_SST               HRTIM_SET2R_SST_Msk                      /*!< software set trigger */

+#define HRTIM_SET2R_RESYNC_Pos        (1U)

+#define HRTIM_SET2R_RESYNC_Msk        (0x1UL << HRTIM_SET2R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_SET2R_RESYNC            HRTIM_SET2R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_SET2R_PER_Pos           (2U)

+#define HRTIM_SET2R_PER_Msk           (0x1UL << HRTIM_SET2R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_SET2R_PER               HRTIM_SET2R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_SET2R_CMP1_Pos          (3U)

+#define HRTIM_SET2R_CMP1_Msk          (0x1UL << HRTIM_SET2R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_SET2R_CMP1              HRTIM_SET2R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_SET2R_CMP2_Pos          (4U)

+#define HRTIM_SET2R_CMP2_Msk          (0x1UL << HRTIM_SET2R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_SET2R_CMP2              HRTIM_SET2R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_SET2R_CMP3_Pos          (5U)

+#define HRTIM_SET2R_CMP3_Msk          (0x1UL << HRTIM_SET2R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_SET2R_CMP3              HRTIM_SET2R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_SET2R_CMP4_Pos          (6U)

+#define HRTIM_SET2R_CMP4_Msk          (0x1UL << HRTIM_SET2R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_SET2R_CMP4              HRTIM_SET2R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_SET2R_MSTPER_Pos        (7U)

+#define HRTIM_SET2R_MSTPER_Msk        (0x1UL << HRTIM_SET2R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_SET2R_MSTPER            HRTIM_SET2R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_SET2R_MSTCMP1_Pos       (8U)

+#define HRTIM_SET2R_MSTCMP1_Msk       (0x1UL << HRTIM_SET2R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_SET2R_MSTCMP1           HRTIM_SET2R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_SET2R_MSTCMP2_Pos       (9U)

+#define HRTIM_SET2R_MSTCMP2_Msk       (0x1UL << HRTIM_SET2R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_SET2R_MSTCMP2           HRTIM_SET2R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_SET2R_MSTCMP3_Pos       (10U)

+#define HRTIM_SET2R_MSTCMP3_Msk       (0x1UL << HRTIM_SET2R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_SET2R_MSTCMP3           HRTIM_SET2R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_SET2R_MSTCMP4_Pos       (11U)

+#define HRTIM_SET2R_MSTCMP4_Msk       (0x1UL << HRTIM_SET2R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_SET2R_MSTCMP4           HRTIM_SET2R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_SET2R_TIMEVNT1_Pos      (12U)

+#define HRTIM_SET2R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_SET2R_TIMEVNT1          HRTIM_SET2R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_SET2R_TIMEVNT2_Pos      (13U)

+#define HRTIM_SET2R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_SET2R_TIMEVNT2          HRTIM_SET2R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_SET2R_TIMEVNT3_Pos      (14U)

+#define HRTIM_SET2R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_SET2R_TIMEVNT3          HRTIM_SET2R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_SET2R_TIMEVNT4_Pos      (15U)

+#define HRTIM_SET2R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_SET2R_TIMEVNT4          HRTIM_SET2R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_SET2R_TIMEVNT5_Pos      (16U)

+#define HRTIM_SET2R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_SET2R_TIMEVNT5          HRTIM_SET2R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_SET2R_TIMEVNT6_Pos      (17U)

+#define HRTIM_SET2R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_SET2R_TIMEVNT6          HRTIM_SET2R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_SET2R_TIMEVNT7_Pos      (18U)

+#define HRTIM_SET2R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_SET2R_TIMEVNT7          HRTIM_SET2R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_SET2R_TIMEVNT8_Pos      (19U)

+#define HRTIM_SET2R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_SET2R_TIMEVNT8          HRTIM_SET2R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_SET2R_TIMEVNT9_Pos      (20U)

+#define HRTIM_SET2R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_SET2R_TIMEVNT9          HRTIM_SET2R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_SET2R_EXTVNT1_Pos       (21U)

+#define HRTIM_SET2R_EXTVNT1_Msk       (0x1UL << HRTIM_SET2R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_SET2R_EXTVNT1           HRTIM_SET2R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_SET2R_EXTVNT2_Pos       (22U)

+#define HRTIM_SET2R_EXTVNT2_Msk       (0x1UL << HRTIM_SET2R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_SET2R_EXTVNT2           HRTIM_SET2R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_SET2R_EXTVNT3_Pos       (23U)

+#define HRTIM_SET2R_EXTVNT3_Msk       (0x1UL << HRTIM_SET2R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_SET2R_EXTVNT3           HRTIM_SET2R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_SET2R_EXTVNT4_Pos       (24U)

+#define HRTIM_SET2R_EXTVNT4_Msk       (0x1UL << HRTIM_SET2R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_SET2R_EXTVNT4           HRTIM_SET2R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_SET2R_EXTVNT5_Pos       (25U)

+#define HRTIM_SET2R_EXTVNT5_Msk       (0x1UL << HRTIM_SET2R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_SET2R_EXTVNT5           HRTIM_SET2R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_SET2R_EXTVNT6_Pos       (26U)

+#define HRTIM_SET2R_EXTVNT6_Msk       (0x1UL << HRTIM_SET2R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_SET2R_EXTVNT6           HRTIM_SET2R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_SET2R_EXTVNT7_Pos       (27U)

+#define HRTIM_SET2R_EXTVNT7_Msk       (0x1UL << HRTIM_SET2R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_SET2R_EXTVNT7           HRTIM_SET2R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_SET2R_EXTVNT8_Pos       (28U)

+#define HRTIM_SET2R_EXTVNT8_Msk       (0x1UL << HRTIM_SET2R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_SET2R_EXTVNT8           HRTIM_SET2R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_SET2R_EXTVNT9_Pos       (29U)

+#define HRTIM_SET2R_EXTVNT9_Msk       (0x1UL << HRTIM_SET2R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_SET2R_EXTVNT9           HRTIM_SET2R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_SET2R_EXTVNT10_Pos      (30U)

+#define HRTIM_SET2R_EXTVNT10_Msk      (0x1UL << HRTIM_SET2R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_SET2R_EXTVNT10          HRTIM_SET2R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_SET2R_UPDATE_Pos        (31U)

+#define HRTIM_SET2R_UPDATE_Msk        (0x1UL << HRTIM_SET2R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_SET2R_UPDATE            HRTIM_SET2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+/**** Bit definition for Slave Output 2 reset register ************************/

+#define HRTIM_RST2R_SRT_Pos           (0U)

+#define HRTIM_RST2R_SRT_Msk           (0x1UL << HRTIM_RST2R_SRT_Pos)           /*!< 0x00000001 */

+#define HRTIM_RST2R_SRT               HRTIM_RST2R_SRT_Msk                      /*!< software reset trigger */

+#define HRTIM_RST2R_RESYNC_Pos        (1U)

+#define HRTIM_RST2R_RESYNC_Msk        (0x1UL << HRTIM_RST2R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_RST2R_RESYNC            HRTIM_RST2R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_RST2R_PER_Pos           (2U)

+#define HRTIM_RST2R_PER_Msk           (0x1UL << HRTIM_RST2R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_RST2R_PER               HRTIM_RST2R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_RST2R_CMP1_Pos          (3U)

+#define HRTIM_RST2R_CMP1_Msk          (0x1UL << HRTIM_RST2R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_RST2R_CMP1              HRTIM_RST2R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_RST2R_CMP2_Pos          (4U)

+#define HRTIM_RST2R_CMP2_Msk          (0x1UL << HRTIM_RST2R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_RST2R_CMP2              HRTIM_RST2R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_RST2R_CMP3_Pos          (5U)

+#define HRTIM_RST2R_CMP3_Msk          (0x1UL << HRTIM_RST2R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_RST2R_CMP3              HRTIM_RST2R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_RST2R_CMP4_Pos          (6U)

+#define HRTIM_RST2R_CMP4_Msk          (0x1UL << HRTIM_RST2R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_RST2R_CMP4              HRTIM_RST2R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_RST2R_MSTPER_Pos        (7U)

+#define HRTIM_RST2R_MSTPER_Msk        (0x1UL << HRTIM_RST2R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_RST2R_MSTPER            HRTIM_RST2R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_RST2R_MSTCMP1_Pos       (8U)

+#define HRTIM_RST2R_MSTCMP1_Msk       (0x1UL << HRTIM_RST2R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_RST2R_MSTCMP1           HRTIM_RST2R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_RST2R_MSTCMP2_Pos       (9U)

+#define HRTIM_RST2R_MSTCMP2_Msk       (0x1UL << HRTIM_RST2R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_RST2R_MSTCMP2           HRTIM_RST2R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_RST2R_MSTCMP3_Pos       (10U)

+#define HRTIM_RST2R_MSTCMP3_Msk       (0x1UL << HRTIM_RST2R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_RST2R_MSTCMP3           HRTIM_RST2R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_RST2R_MSTCMP4_Pos       (11U)

+#define HRTIM_RST2R_MSTCMP4_Msk       (0x1UL << HRTIM_RST2R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_RST2R_MSTCMP4           HRTIM_RST2R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_RST2R_TIMEVNT1_Pos      (12U)

+#define HRTIM_RST2R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_RST2R_TIMEVNT1          HRTIM_RST2R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_RST2R_TIMEVNT2_Pos      (13U)

+#define HRTIM_RST2R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_RST2R_TIMEVNT2          HRTIM_RST2R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_RST2R_TIMEVNT3_Pos      (14U)

+#define HRTIM_RST2R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_RST2R_TIMEVNT3          HRTIM_RST2R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_RST2R_TIMEVNT4_Pos      (15U)

+#define HRTIM_RST2R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_RST2R_TIMEVNT4          HRTIM_RST2R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_RST2R_TIMEVNT5_Pos      (16U)

+#define HRTIM_RST2R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_RST2R_TIMEVNT5          HRTIM_RST2R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_RST2R_TIMEVNT6_Pos      (17U)

+#define HRTIM_RST2R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_RST2R_TIMEVNT6          HRTIM_RST2R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_RST2R_TIMEVNT7_Pos      (18U)

+#define HRTIM_RST2R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_RST2R_TIMEVNT7          HRTIM_RST2R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_RST2R_TIMEVNT8_Pos      (19U)

+#define HRTIM_RST2R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_RST2R_TIMEVNT8          HRTIM_RST2R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_RST2R_TIMEVNT9_Pos      (20U)

+#define HRTIM_RST2R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_RST2R_TIMEVNT9          HRTIM_RST2R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_RST2R_EXTVNT1_Pos       (21U)

+#define HRTIM_RST2R_EXTVNT1_Msk       (0x1UL << HRTIM_RST2R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_RST2R_EXTVNT1           HRTIM_RST2R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_RST2R_EXTVNT2_Pos       (22U)

+#define HRTIM_RST2R_EXTVNT2_Msk       (0x1UL << HRTIM_RST2R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_RST2R_EXTVNT2           HRTIM_RST2R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_RST2R_EXTVNT3_Pos       (23U)

+#define HRTIM_RST2R_EXTVNT3_Msk       (0x1UL << HRTIM_RST2R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_RST2R_EXTVNT3           HRTIM_RST2R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_RST2R_EXTVNT4_Pos       (24U)

+#define HRTIM_RST2R_EXTVNT4_Msk       (0x1UL << HRTIM_RST2R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_RST2R_EXTVNT4           HRTIM_RST2R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_RST2R_EXTVNT5_Pos       (25U)

+#define HRTIM_RST2R_EXTVNT5_Msk       (0x1UL << HRTIM_RST2R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_RST2R_EXTVNT5           HRTIM_RST2R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_RST2R_EXTVNT6_Pos       (26U)

+#define HRTIM_RST2R_EXTVNT6_Msk       (0x1UL << HRTIM_RST2R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_RST2R_EXTVNT6           HRTIM_RST2R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_RST2R_EXTVNT7_Pos       (27U)

+#define HRTIM_RST2R_EXTVNT7_Msk       (0x1UL << HRTIM_RST2R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_RST2R_EXTVNT7           HRTIM_RST2R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_RST2R_EXTVNT8_Pos       (28U)

+#define HRTIM_RST2R_EXTVNT8_Msk       (0x1UL << HRTIM_RST2R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_RST2R_EXTVNT8           HRTIM_RST2R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_RST2R_EXTVNT9_Pos       (29U)

+#define HRTIM_RST2R_EXTVNT9_Msk       (0x1UL << HRTIM_RST2R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_RST2R_EXTVNT9           HRTIM_RST2R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_RST2R_EXTVNT10_Pos      (30U)

+#define HRTIM_RST2R_EXTVNT10_Msk      (0x1UL << HRTIM_RST2R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_RST2R_EXTVNT10          HRTIM_RST2R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_RST2R_UPDATE_Pos        (31U)

+#define HRTIM_RST2R_UPDATE_Msk        (0x1UL << HRTIM_RST2R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_RST2R_UPDATE            HRTIM_RST2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+/**** Bit definition for Slave external event filtering  register 1 ***********/

+#define HRTIM_EEFR1_EE1LTCH_Pos       (0U)

+#define HRTIM_EEFR1_EE1LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos)       /*!< 0x00000001 */

+#define HRTIM_EEFR1_EE1LTCH           HRTIM_EEFR1_EE1LTCH_Msk                  /*!< External Event 1 latch */

+#define HRTIM_EEFR1_EE1FLTR_Pos       (1U)

+#define HRTIM_EEFR1_EE1FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos)       /*!< 0x0000001E */

+#define HRTIM_EEFR1_EE1FLTR           HRTIM_EEFR1_EE1FLTR_Msk                  /*!< External Event 1 filter mask */

+#define HRTIM_EEFR1_EE1FLTR_0         (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000002 */

+#define HRTIM_EEFR1_EE1FLTR_1         (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000004 */

+#define HRTIM_EEFR1_EE1FLTR_2         (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000008 */

+#define HRTIM_EEFR1_EE1FLTR_3         (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000010 */

+

+#define HRTIM_EEFR1_EE2LTCH_Pos       (6U)

+#define HRTIM_EEFR1_EE2LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos)       /*!< 0x00000040 */

+#define HRTIM_EEFR1_EE2LTCH           HRTIM_EEFR1_EE2LTCH_Msk                  /*!< External Event 2 latch */

+#define HRTIM_EEFR1_EE2FLTR_Pos       (7U)

+#define HRTIM_EEFR1_EE2FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos)       /*!< 0x00000780 */

+#define HRTIM_EEFR1_EE2FLTR           HRTIM_EEFR1_EE2FLTR_Msk                  /*!< External Event 2 filter mask */

+#define HRTIM_EEFR1_EE2FLTR_0         (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000080 */

+#define HRTIM_EEFR1_EE2FLTR_1         (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000100 */

+#define HRTIM_EEFR1_EE2FLTR_2         (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000200 */

+#define HRTIM_EEFR1_EE2FLTR_3         (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000400 */

+

+#define HRTIM_EEFR1_EE3LTCH_Pos       (12U)

+#define HRTIM_EEFR1_EE3LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos)       /*!< 0x00001000 */

+#define HRTIM_EEFR1_EE3LTCH           HRTIM_EEFR1_EE3LTCH_Msk                  /*!< External Event 3 latch */

+#define HRTIM_EEFR1_EE3FLTR_Pos       (13U)

+#define HRTIM_EEFR1_EE3FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos)       /*!< 0x0001E000 */

+#define HRTIM_EEFR1_EE3FLTR           HRTIM_EEFR1_EE3FLTR_Msk                  /*!< External Event 3 filter mask */

+#define HRTIM_EEFR1_EE3FLTR_0         (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00002000 */

+#define HRTIM_EEFR1_EE3FLTR_1         (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00004000 */

+#define HRTIM_EEFR1_EE3FLTR_2         (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00008000 */

+#define HRTIM_EEFR1_EE3FLTR_3         (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00010000 */

+

+#define HRTIM_EEFR1_EE4LTCH_Pos       (18U)

+#define HRTIM_EEFR1_EE4LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos)       /*!< 0x00040000 */

+#define HRTIM_EEFR1_EE4LTCH           HRTIM_EEFR1_EE4LTCH_Msk                  /*!< External Event 4 latch */

+#define HRTIM_EEFR1_EE4FLTR_Pos       (19U)

+#define HRTIM_EEFR1_EE4FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos)       /*!< 0x00780000 */

+#define HRTIM_EEFR1_EE4FLTR           HRTIM_EEFR1_EE4FLTR_Msk                  /*!< External Event 4 filter mask */

+#define HRTIM_EEFR1_EE4FLTR_0         (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00080000 */

+#define HRTIM_EEFR1_EE4FLTR_1         (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00100000 */

+#define HRTIM_EEFR1_EE4FLTR_2         (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00200000 */

+#define HRTIM_EEFR1_EE4FLTR_3         (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00400000 */

+

+#define HRTIM_EEFR1_EE5LTCH_Pos       (24U)

+#define HRTIM_EEFR1_EE5LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos)       /*!< 0x01000000 */

+#define HRTIM_EEFR1_EE5LTCH           HRTIM_EEFR1_EE5LTCH_Msk                  /*!< External Event 5 latch */

+#define HRTIM_EEFR1_EE5FLTR_Pos       (25U)

+#define HRTIM_EEFR1_EE5FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos)       /*!< 0x1E000000 */

+#define HRTIM_EEFR1_EE5FLTR           HRTIM_EEFR1_EE5FLTR_Msk                  /*!< External Event 5 filter mask */

+#define HRTIM_EEFR1_EE5FLTR_0         (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x02000000 */

+#define HRTIM_EEFR1_EE5FLTR_1         (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x04000000 */

+#define HRTIM_EEFR1_EE5FLTR_2         (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x08000000 */

+#define HRTIM_EEFR1_EE5FLTR_3         (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x10000000 */

+

+/**** Bit definition for Slave external event filtering  register 2 ***********/

+#define HRTIM_EEFR2_EE6LTCH_Pos       (0U)

+#define HRTIM_EEFR2_EE6LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos)       /*!< 0x00000001 */

+#define HRTIM_EEFR2_EE6LTCH           HRTIM_EEFR2_EE6LTCH_Msk                  /*!< External Event 6 latch */

+#define HRTIM_EEFR2_EE6FLTR_Pos       (1U)

+#define HRTIM_EEFR2_EE6FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos)       /*!< 0x0000001E */

+#define HRTIM_EEFR2_EE6FLTR           HRTIM_EEFR2_EE6FLTR_Msk                  /*!< External Event 6 filter mask */

+#define HRTIM_EEFR2_EE6FLTR_0         (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000002 */

+#define HRTIM_EEFR2_EE6FLTR_1         (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000004 */

+#define HRTIM_EEFR2_EE6FLTR_2         (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000008 */

+#define HRTIM_EEFR2_EE6FLTR_3         (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000010 */

+

+#define HRTIM_EEFR2_EE7LTCH_Pos       (6U)

+#define HRTIM_EEFR2_EE7LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos)       /*!< 0x00000040 */

+#define HRTIM_EEFR2_EE7LTCH           HRTIM_EEFR2_EE7LTCH_Msk                  /*!< External Event 7 latch */

+#define HRTIM_EEFR2_EE7FLTR_Pos       (7U)

+#define HRTIM_EEFR2_EE7FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos)       /*!< 0x00000780 */

+#define HRTIM_EEFR2_EE7FLTR           HRTIM_EEFR2_EE7FLTR_Msk                  /*!< External Event 7 filter mask */

+#define HRTIM_EEFR2_EE7FLTR_0         (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000080 */

+#define HRTIM_EEFR2_EE7FLTR_1         (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000100 */

+#define HRTIM_EEFR2_EE7FLTR_2         (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000200 */

+#define HRTIM_EEFR2_EE7FLTR_3         (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000400 */

+

+#define HRTIM_EEFR2_EE8LTCH_Pos       (12U)

+#define HRTIM_EEFR2_EE8LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos)       /*!< 0x00001000 */

+#define HRTIM_EEFR2_EE8LTCH           HRTIM_EEFR2_EE8LTCH_Msk                  /*!< External Event 8 latch */

+#define HRTIM_EEFR2_EE8FLTR_Pos       (13U)

+#define HRTIM_EEFR2_EE8FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos)       /*!< 0x0001E000 */

+#define HRTIM_EEFR2_EE8FLTR           HRTIM_EEFR2_EE8FLTR_Msk                  /*!< External Event 8 filter mask */

+#define HRTIM_EEFR2_EE8FLTR_0         (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00002000 */

+#define HRTIM_EEFR2_EE8FLTR_1         (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00004000 */

+#define HRTIM_EEFR2_EE8FLTR_2         (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00008000 */

+#define HRTIM_EEFR2_EE8FLTR_3         (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00010000 */

+

+#define HRTIM_EEFR2_EE9LTCH_Pos       (18U)

+#define HRTIM_EEFR2_EE9LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos)       /*!< 0x00040000 */

+#define HRTIM_EEFR2_EE9LTCH           HRTIM_EEFR2_EE9LTCH_Msk                  /*!< External Event 9 latch */

+#define HRTIM_EEFR2_EE9FLTR_Pos       (19U)

+#define HRTIM_EEFR2_EE9FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos)       /*!< 0x00780000 */

+#define HRTIM_EEFR2_EE9FLTR           HRTIM_EEFR2_EE9FLTR_Msk                  /*!< External Event 9 filter mask */

+#define HRTIM_EEFR2_EE9FLTR_0         (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00080000 */

+#define HRTIM_EEFR2_EE9FLTR_1         (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00100000 */

+#define HRTIM_EEFR2_EE9FLTR_2         (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00200000 */

+#define HRTIM_EEFR2_EE9FLTR_3         (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00400000 */

+

+#define HRTIM_EEFR2_EE10LTCH_Pos      (24U)

+#define HRTIM_EEFR2_EE10LTCH_Msk      (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos)      /*!< 0x01000000 */

+#define HRTIM_EEFR2_EE10LTCH          HRTIM_EEFR2_EE10LTCH_Msk                 /*!< External Event 10 latch */

+#define HRTIM_EEFR2_EE10FLTR_Pos      (25U)

+#define HRTIM_EEFR2_EE10FLTR_Msk      (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos)      /*!< 0x1E000000 */

+#define HRTIM_EEFR2_EE10FLTR          HRTIM_EEFR2_EE10FLTR_Msk                 /*!< External Event 10 filter mask */

+#define HRTIM_EEFR2_EE10FLTR_0        (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x02000000 */

+#define HRTIM_EEFR2_EE10FLTR_1        (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x04000000 */

+#define HRTIM_EEFR2_EE10FLTR_2        (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x08000000 */

+#define HRTIM_EEFR2_EE10FLTR_3        (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x10000000 */

+

+/**** Bit definition for Slave Timer reset register ***************************/

+#define HRTIM_RSTR_UPDATE_Pos         (1U)

+#define HRTIM_RSTR_UPDATE_Msk         (0x1UL << HRTIM_RSTR_UPDATE_Pos)         /*!< 0x00000002 */

+#define HRTIM_RSTR_UPDATE             HRTIM_RSTR_UPDATE_Msk                    /*!< Timer update */

+#define HRTIM_RSTR_CMP2_Pos           (2U)

+#define HRTIM_RSTR_CMP2_Msk           (0x1UL << HRTIM_RSTR_CMP2_Pos)           /*!< 0x00000004 */

+#define HRTIM_RSTR_CMP2               HRTIM_RSTR_CMP2_Msk                      /*!< Timer compare2 */

+#define HRTIM_RSTR_CMP4_Pos           (3U)

+#define HRTIM_RSTR_CMP4_Msk           (0x1UL << HRTIM_RSTR_CMP4_Pos)           /*!< 0x00000008 */

+#define HRTIM_RSTR_CMP4               HRTIM_RSTR_CMP4_Msk                      /*!< Timer compare4 */

+

+#define HRTIM_RSTR_MSTPER_Pos         (4U)

+#define HRTIM_RSTR_MSTPER_Msk         (0x1UL << HRTIM_RSTR_MSTPER_Pos)         /*!< 0x00000010 */

+#define HRTIM_RSTR_MSTPER             HRTIM_RSTR_MSTPER_Msk                    /*!< Master period */

+#define HRTIM_RSTR_MSTCMP1_Pos        (5U)

+#define HRTIM_RSTR_MSTCMP1_Msk        (0x1UL << HRTIM_RSTR_MSTCMP1_Pos)        /*!< 0x00000020 */

+#define HRTIM_RSTR_MSTCMP1            HRTIM_RSTR_MSTCMP1_Msk                   /*!< Master compare1 */

+#define HRTIM_RSTR_MSTCMP2_Pos        (6U)

+#define HRTIM_RSTR_MSTCMP2_Msk        (0x1UL << HRTIM_RSTR_MSTCMP2_Pos)        /*!< 0x00000040 */

+#define HRTIM_RSTR_MSTCMP2            HRTIM_RSTR_MSTCMP2_Msk                   /*!< Master compare2 */

+#define HRTIM_RSTR_MSTCMP3_Pos        (7U)

+#define HRTIM_RSTR_MSTCMP3_Msk        (0x1UL << HRTIM_RSTR_MSTCMP3_Pos)        /*!< 0x00000080 */

+#define HRTIM_RSTR_MSTCMP3            HRTIM_RSTR_MSTCMP3_Msk                   /*!< Master compare3 */

+#define HRTIM_RSTR_MSTCMP4_Pos        (8U)

+#define HRTIM_RSTR_MSTCMP4_Msk        (0x1UL << HRTIM_RSTR_MSTCMP4_Pos)        /*!< 0x00000100 */

+#define HRTIM_RSTR_MSTCMP4            HRTIM_RSTR_MSTCMP4_Msk                   /*!< Master compare4 */

+

+#define HRTIM_RSTR_EXTEVNT1_Pos       (9U)

+#define HRTIM_RSTR_EXTEVNT1_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos)       /*!< 0x00000200 */

+#define HRTIM_RSTR_EXTEVNT1           HRTIM_RSTR_EXTEVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_RSTR_EXTEVNT2_Pos       (10U)

+#define HRTIM_RSTR_EXTEVNT2_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos)       /*!< 0x00000400 */

+#define HRTIM_RSTR_EXTEVNT2           HRTIM_RSTR_EXTEVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_RSTR_EXTEVNT3_Pos       (11U)

+#define HRTIM_RSTR_EXTEVNT3_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos)       /*!< 0x00000800 */

+#define HRTIM_RSTR_EXTEVNT3           HRTIM_RSTR_EXTEVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_RSTR_EXTEVNT4_Pos       (12U)

+#define HRTIM_RSTR_EXTEVNT4_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos)       /*!< 0x00001000 */

+#define HRTIM_RSTR_EXTEVNT4           HRTIM_RSTR_EXTEVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_RSTR_EXTEVNT5_Pos       (13U)

+#define HRTIM_RSTR_EXTEVNT5_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos)       /*!< 0x00002000 */

+#define HRTIM_RSTR_EXTEVNT5           HRTIM_RSTR_EXTEVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_RSTR_EXTEVNT6_Pos       (14U)

+#define HRTIM_RSTR_EXTEVNT6_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos)       /*!< 0x00004000 */

+#define HRTIM_RSTR_EXTEVNT6           HRTIM_RSTR_EXTEVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_RSTR_EXTEVNT7_Pos       (15U)

+#define HRTIM_RSTR_EXTEVNT7_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos)       /*!< 0x00008000 */

+#define HRTIM_RSTR_EXTEVNT7           HRTIM_RSTR_EXTEVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_RSTR_EXTEVNT8_Pos       (16U)

+#define HRTIM_RSTR_EXTEVNT8_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos)       /*!< 0x00010000 */

+#define HRTIM_RSTR_EXTEVNT8           HRTIM_RSTR_EXTEVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_RSTR_EXTEVNT9_Pos       (17U)

+#define HRTIM_RSTR_EXTEVNT9_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos)       /*!< 0x00020000 */

+#define HRTIM_RSTR_EXTEVNT9           HRTIM_RSTR_EXTEVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_RSTR_EXTEVNT10_Pos      (18U)

+#define HRTIM_RSTR_EXTEVNT10_Msk      (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos)      /*!< 0x00040000 */

+#define HRTIM_RSTR_EXTEVNT10          HRTIM_RSTR_EXTEVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_RSTR_TIMBCMP1_Pos       (19U)

+#define HRTIM_RSTR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos)       /*!< 0x00080000 */

+#define HRTIM_RSTR_TIMBCMP1           HRTIM_RSTR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */

+#define HRTIM_RSTR_TIMBCMP2_Pos       (20U)

+#define HRTIM_RSTR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos)       /*!< 0x00100000 */

+#define HRTIM_RSTR_TIMBCMP2           HRTIM_RSTR_TIMBCMP2_Msk                  /*!< Timer B compare 2 */

+#define HRTIM_RSTR_TIMBCMP4_Pos       (21U)

+#define HRTIM_RSTR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos)       /*!< 0x00200000 */

+#define HRTIM_RSTR_TIMBCMP4           HRTIM_RSTR_TIMBCMP4_Msk                  /*!< Timer B compare 4 */

+

+#define HRTIM_RSTR_TIMCCMP1_Pos       (22U)

+#define HRTIM_RSTR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos)       /*!< 0x00400000 */

+#define HRTIM_RSTR_TIMCCMP1           HRTIM_RSTR_TIMCCMP1_Msk                  /*!< Timer C compare 1 */

+#define HRTIM_RSTR_TIMCCMP2_Pos       (23U)

+#define HRTIM_RSTR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos)       /*!< 0x00800000 */

+#define HRTIM_RSTR_TIMCCMP2           HRTIM_RSTR_TIMCCMP2_Msk                  /*!< Timer C compare 2 */

+#define HRTIM_RSTR_TIMCCMP4_Pos       (24U)

+#define HRTIM_RSTR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos)       /*!< 0x01000000 */

+#define HRTIM_RSTR_TIMCCMP4           HRTIM_RSTR_TIMCCMP4_Msk                  /*!< Timer C compare 4 */

+

+#define HRTIM_RSTR_TIMDCMP1_Pos       (25U)

+#define HRTIM_RSTR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos)       /*!< 0x02000000 */

+#define HRTIM_RSTR_TIMDCMP1           HRTIM_RSTR_TIMDCMP1_Msk                  /*!< Timer D compare 1 */

+#define HRTIM_RSTR_TIMDCMP2_Pos       (26U)

+#define HRTIM_RSTR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos)       /*!< 0x04000000 */

+#define HRTIM_RSTR_TIMDCMP2           HRTIM_RSTR_TIMDCMP2_Msk                  /*!< Timer D compare 2 */

+#define HRTIM_RSTR_TIMDCMP4_Pos       (27U)

+#define HRTIM_RSTR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos)       /*!< 0x08000000 */

+#define HRTIM_RSTR_TIMDCMP4           HRTIM_RSTR_TIMDCMP4_Msk                  /*!< Timer D compare 4 */

+

+#define HRTIM_RSTR_TIMECMP1_Pos       (28U)

+#define HRTIM_RSTR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTR_TIMECMP1_Pos)       /*!< 0x10000000 */

+#define HRTIM_RSTR_TIMECMP1           HRTIM_RSTR_TIMECMP1_Msk                  /*!< Timer E compare 1 */

+#define HRTIM_RSTR_TIMECMP2_Pos       (29U)

+#define HRTIM_RSTR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTR_TIMECMP2_Pos)       /*!< 0x20000000 */

+#define HRTIM_RSTR_TIMECMP2           HRTIM_RSTR_TIMECMP2_Msk                  /*!< Timer E compare 2 */

+#define HRTIM_RSTR_TIMECMP4_Pos       (30U)

+#define HRTIM_RSTR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTR_TIMECMP4_Pos)       /*!< 0x40000000 */

+#define HRTIM_RSTR_TIMECMP4           HRTIM_RSTR_TIMECMP4_Msk                  /*!< Timer E compare 4 */

+

+/**** Bit definition for Slave Timer Chopper register *************************/

+#define HRTIM_CHPR_CARFRQ_Pos         (0U)

+#define HRTIM_CHPR_CARFRQ_Msk         (0xFUL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x0000000F */

+#define HRTIM_CHPR_CARFRQ             HRTIM_CHPR_CARFRQ_Msk                    /*!< Timer carrier frequency value */

+#define HRTIM_CHPR_CARFRQ_0           (0x1UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000001 */

+#define HRTIM_CHPR_CARFRQ_1           (0x2UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000002 */

+#define HRTIM_CHPR_CARFRQ_2           (0x4UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000004 */

+#define HRTIM_CHPR_CARFRQ_3           (0x8UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000008 */

+

+#define HRTIM_CHPR_CARDTY_Pos         (4U)

+#define HRTIM_CHPR_CARDTY_Msk         (0x7UL << HRTIM_CHPR_CARDTY_Pos)         /*!< 0x00000070 */

+#define HRTIM_CHPR_CARDTY             HRTIM_CHPR_CARDTY_Msk                    /*!< Timer chopper duty cycle value */

+#define HRTIM_CHPR_CARDTY_0           (0x1UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000010 */

+#define HRTIM_CHPR_CARDTY_1           (0x2UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000020 */

+#define HRTIM_CHPR_CARDTY_2           (0x4UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000040 */

+

+#define HRTIM_CHPR_STRPW_Pos          (7U)

+#define HRTIM_CHPR_STRPW_Msk          (0xFUL << HRTIM_CHPR_STRPW_Pos)          /*!< 0x00000780 */

+#define HRTIM_CHPR_STRPW              HRTIM_CHPR_STRPW_Msk                     /*!< Timer start pulse width value */

+#define HRTIM_CHPR_STRPW_0            (0x1UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000080 */

+#define HRTIM_CHPR_STRPW_1            (0x2UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000100 */

+#define HRTIM_CHPR_STRPW_2            (0x4UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000200 */

+#define HRTIM_CHPR_STRPW_3            (0x8UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000400 */

+

+/**** Bit definition for Slave Timer Capture 1 control register ***************/

+#define HRTIM_CPT1CR_SWCPT_Pos        (0U)

+#define HRTIM_CPT1CR_SWCPT_Msk        (0x1UL << HRTIM_CPT1CR_SWCPT_Pos)        /*!< 0x00000001 */

+#define HRTIM_CPT1CR_SWCPT            HRTIM_CPT1CR_SWCPT_Msk                   /*!< Software capture */

+#define HRTIM_CPT1CR_UPDCPT_Pos       (1U)

+#define HRTIM_CPT1CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos)       /*!< 0x00000002 */

+#define HRTIM_CPT1CR_UPDCPT           HRTIM_CPT1CR_UPDCPT_Msk                  /*!< Update capture */

+#define HRTIM_CPT1CR_EXEV1CPT_Pos     (2U)

+#define HRTIM_CPT1CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos)     /*!< 0x00000004 */

+#define HRTIM_CPT1CR_EXEV1CPT         HRTIM_CPT1CR_EXEV1CPT_Msk                /*!< External event 1 capture */

+#define HRTIM_CPT1CR_EXEV2CPT_Pos     (3U)

+#define HRTIM_CPT1CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos)     /*!< 0x00000008 */

+#define HRTIM_CPT1CR_EXEV2CPT         HRTIM_CPT1CR_EXEV2CPT_Msk                /*!< External event 2 capture */

+#define HRTIM_CPT1CR_EXEV3CPT_Pos     (4U)

+#define HRTIM_CPT1CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos)     /*!< 0x00000010 */

+#define HRTIM_CPT1CR_EXEV3CPT         HRTIM_CPT1CR_EXEV3CPT_Msk                /*!< External event 3 capture */

+#define HRTIM_CPT1CR_EXEV4CPT_Pos     (5U)

+#define HRTIM_CPT1CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos)     /*!< 0x00000020 */

+#define HRTIM_CPT1CR_EXEV4CPT         HRTIM_CPT1CR_EXEV4CPT_Msk                /*!< External event 4 capture */

+#define HRTIM_CPT1CR_EXEV5CPT_Pos     (6U)

+#define HRTIM_CPT1CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos)     /*!< 0x00000040 */

+#define HRTIM_CPT1CR_EXEV5CPT         HRTIM_CPT1CR_EXEV5CPT_Msk                /*!< External event 5 capture */

+#define HRTIM_CPT1CR_EXEV6CPT_Pos     (7U)

+#define HRTIM_CPT1CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos)     /*!< 0x00000080 */

+#define HRTIM_CPT1CR_EXEV6CPT         HRTIM_CPT1CR_EXEV6CPT_Msk                /*!< External event 6 capture */

+#define HRTIM_CPT1CR_EXEV7CPT_Pos     (8U)

+#define HRTIM_CPT1CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos)     /*!< 0x00000100 */

+#define HRTIM_CPT1CR_EXEV7CPT         HRTIM_CPT1CR_EXEV7CPT_Msk                /*!< External event 7 capture */

+#define HRTIM_CPT1CR_EXEV8CPT_Pos     (9U)

+#define HRTIM_CPT1CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos)     /*!< 0x00000200 */

+#define HRTIM_CPT1CR_EXEV8CPT         HRTIM_CPT1CR_EXEV8CPT_Msk                /*!< External event 8 capture */

+#define HRTIM_CPT1CR_EXEV9CPT_Pos     (10U)

+#define HRTIM_CPT1CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos)     /*!< 0x00000400 */

+#define HRTIM_CPT1CR_EXEV9CPT         HRTIM_CPT1CR_EXEV9CPT_Msk                /*!< External event 9 capture */

+#define HRTIM_CPT1CR_EXEV10CPT_Pos    (11U)

+#define HRTIM_CPT1CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos)    /*!< 0x00000800 */

+#define HRTIM_CPT1CR_EXEV10CPT        HRTIM_CPT1CR_EXEV10CPT_Msk               /*!< External event 10 capture */

+

+#define HRTIM_CPT1CR_TA1SET_Pos       (12U)

+#define HRTIM_CPT1CR_TA1SET_Msk       (0x1UL << HRTIM_CPT1CR_TA1SET_Pos)       /*!< 0x00001000 */

+#define HRTIM_CPT1CR_TA1SET           HRTIM_CPT1CR_TA1SET_Msk                  /*!< Timer A output 1 set */

+#define HRTIM_CPT1CR_TA1RST_Pos       (13U)

+#define HRTIM_CPT1CR_TA1RST_Msk       (0x1UL << HRTIM_CPT1CR_TA1RST_Pos)       /*!< 0x00002000 */

+#define HRTIM_CPT1CR_TA1RST           HRTIM_CPT1CR_TA1RST_Msk                  /*!< Timer A output 1 reset */

+#define HRTIM_CPT1CR_TIMACMP1_Pos     (14U)

+#define HRTIM_CPT1CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos)     /*!< 0x00004000 */

+#define HRTIM_CPT1CR_TIMACMP1         HRTIM_CPT1CR_TIMACMP1_Msk                /*!< Timer A compare 1 */

+#define HRTIM_CPT1CR_TIMACMP2_Pos     (15U)

+#define HRTIM_CPT1CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos)     /*!< 0x00008000 */

+#define HRTIM_CPT1CR_TIMACMP2         HRTIM_CPT1CR_TIMACMP2_Msk                /*!< Timer A compare 2 */

+

+#define HRTIM_CPT1CR_TB1SET_Pos       (16U)

+#define HRTIM_CPT1CR_TB1SET_Msk       (0x1UL << HRTIM_CPT1CR_TB1SET_Pos)       /*!< 0x00010000 */

+#define HRTIM_CPT1CR_TB1SET           HRTIM_CPT1CR_TB1SET_Msk                  /*!< Timer B output 1 set */

+#define HRTIM_CPT1CR_TB1RST_Pos       (17U)

+#define HRTIM_CPT1CR_TB1RST_Msk       (0x1UL << HRTIM_CPT1CR_TB1RST_Pos)       /*!< 0x00020000 */

+#define HRTIM_CPT1CR_TB1RST           HRTIM_CPT1CR_TB1RST_Msk                  /*!< Timer B output 1 reset */

+#define HRTIM_CPT1CR_TIMBCMP1_Pos     (18U)

+#define HRTIM_CPT1CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos)     /*!< 0x00040000 */

+#define HRTIM_CPT1CR_TIMBCMP1         HRTIM_CPT1CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */

+#define HRTIM_CPT1CR_TIMBCMP2_Pos     (19U)

+#define HRTIM_CPT1CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos)     /*!< 0x00080000 */

+#define HRTIM_CPT1CR_TIMBCMP2         HRTIM_CPT1CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */

+

+#define HRTIM_CPT1CR_TC1SET_Pos       (20U)

+#define HRTIM_CPT1CR_TC1SET_Msk       (0x1UL << HRTIM_CPT1CR_TC1SET_Pos)       /*!< 0x00100000 */

+#define HRTIM_CPT1CR_TC1SET           HRTIM_CPT1CR_TC1SET_Msk                  /*!< Timer C output 1 set */

+#define HRTIM_CPT1CR_TC1RST_Pos       (21U)

+#define HRTIM_CPT1CR_TC1RST_Msk       (0x1UL << HRTIM_CPT1CR_TC1RST_Pos)       /*!< 0x00200000 */

+#define HRTIM_CPT1CR_TC1RST           HRTIM_CPT1CR_TC1RST_Msk                  /*!< Timer C output 1 reset */

+#define HRTIM_CPT1CR_TIMCCMP1_Pos     (22U)

+#define HRTIM_CPT1CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos)     /*!< 0x00400000 */

+#define HRTIM_CPT1CR_TIMCCMP1         HRTIM_CPT1CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */

+#define HRTIM_CPT1CR_TIMCCMP2_Pos     (23U)

+#define HRTIM_CPT1CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos)     /*!< 0x00800000 */

+#define HRTIM_CPT1CR_TIMCCMP2         HRTIM_CPT1CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */

+

+#define HRTIM_CPT1CR_TD1SET_Pos       (24U)

+#define HRTIM_CPT1CR_TD1SET_Msk       (0x1UL << HRTIM_CPT1CR_TD1SET_Pos)       /*!< 0x01000000 */

+#define HRTIM_CPT1CR_TD1SET           HRTIM_CPT1CR_TD1SET_Msk                  /*!< Timer D output 1 set */

+#define HRTIM_CPT1CR_TD1RST_Pos       (25U)

+#define HRTIM_CPT1CR_TD1RST_Msk       (0x1UL << HRTIM_CPT1CR_TD1RST_Pos)       /*!< 0x02000000 */

+#define HRTIM_CPT1CR_TD1RST           HRTIM_CPT1CR_TD1RST_Msk                  /*!< Timer D output 1 reset */

+#define HRTIM_CPT1CR_TIMDCMP1_Pos     (26U)

+#define HRTIM_CPT1CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos)     /*!< 0x04000000 */

+#define HRTIM_CPT1CR_TIMDCMP1         HRTIM_CPT1CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */

+#define HRTIM_CPT1CR_TIMDCMP2_Pos     (27U)

+#define HRTIM_CPT1CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos)     /*!< 0x08000000 */

+#define HRTIM_CPT1CR_TIMDCMP2         HRTIM_CPT1CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */

+

+#define HRTIM_CPT1CR_TE1SET_Pos       (28U)

+#define HRTIM_CPT1CR_TE1SET_Msk       (0x1UL << HRTIM_CPT1CR_TE1SET_Pos)       /*!< 0x10000000 */

+#define HRTIM_CPT1CR_TE1SET           HRTIM_CPT1CR_TE1SET_Msk                  /*!< Timer E output 1 set */

+#define HRTIM_CPT1CR_TE1RST_Pos       (29U)

+#define HRTIM_CPT1CR_TE1RST_Msk       (0x1UL << HRTIM_CPT1CR_TE1RST_Pos)       /*!< 0x20000000 */

+#define HRTIM_CPT1CR_TE1RST           HRTIM_CPT1CR_TE1RST_Msk                  /*!< Timer E output 1 reset */

+#define HRTIM_CPT1CR_TIMECMP1_Pos     (30U)

+#define HRTIM_CPT1CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos)     /*!< 0x40000000 */

+#define HRTIM_CPT1CR_TIMECMP1         HRTIM_CPT1CR_TIMECMP1_Msk                /*!< Timer E compare 1 */

+#define HRTIM_CPT1CR_TIMECMP2_Pos     (31U)

+#define HRTIM_CPT1CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos)     /*!< 0x80000000 */

+#define HRTIM_CPT1CR_TIMECMP2         HRTIM_CPT1CR_TIMECMP2_Msk                /*!< Timer E compare 2 */

+

+/**** Bit definition for Slave Timer Capture 2 control register ***************/

+#define HRTIM_CPT2CR_SWCPT_Pos        (0U)

+#define HRTIM_CPT2CR_SWCPT_Msk        (0x1UL << HRTIM_CPT2CR_SWCPT_Pos)        /*!< 0x00000001 */

+#define HRTIM_CPT2CR_SWCPT            HRTIM_CPT2CR_SWCPT_Msk                   /*!< Software capture */

+#define HRTIM_CPT2CR_UPDCPT_Pos       (1U)

+#define HRTIM_CPT2CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos)       /*!< 0x00000002 */

+#define HRTIM_CPT2CR_UPDCPT           HRTIM_CPT2CR_UPDCPT_Msk                  /*!< Update capture */

+#define HRTIM_CPT2CR_EXEV1CPT_Pos     (2U)

+#define HRTIM_CPT2CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos)     /*!< 0x00000004 */

+#define HRTIM_CPT2CR_EXEV1CPT         HRTIM_CPT2CR_EXEV1CPT_Msk                /*!< External event 1 capture */

+#define HRTIM_CPT2CR_EXEV2CPT_Pos     (3U)

+#define HRTIM_CPT2CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos)     /*!< 0x00000008 */

+#define HRTIM_CPT2CR_EXEV2CPT         HRTIM_CPT2CR_EXEV2CPT_Msk                /*!< External event 2 capture */

+#define HRTIM_CPT2CR_EXEV3CPT_Pos     (4U)

+#define HRTIM_CPT2CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos)     /*!< 0x00000010 */

+#define HRTIM_CPT2CR_EXEV3CPT         HRTIM_CPT2CR_EXEV3CPT_Msk                /*!< External event 3 capture */

+#define HRTIM_CPT2CR_EXEV4CPT_Pos     (5U)

+#define HRTIM_CPT2CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos)     /*!< 0x00000020 */

+#define HRTIM_CPT2CR_EXEV4CPT         HRTIM_CPT2CR_EXEV4CPT_Msk                /*!< External event 4 capture */

+#define HRTIM_CPT2CR_EXEV5CPT_Pos     (6U)

+#define HRTIM_CPT2CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos)     /*!< 0x00000040 */

+#define HRTIM_CPT2CR_EXEV5CPT         HRTIM_CPT2CR_EXEV5CPT_Msk                /*!< External event 5 capture */

+#define HRTIM_CPT2CR_EXEV6CPT_Pos     (7U)

+#define HRTIM_CPT2CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos)     /*!< 0x00000080 */

+#define HRTIM_CPT2CR_EXEV6CPT         HRTIM_CPT2CR_EXEV6CPT_Msk                /*!< External event 6 capture */

+#define HRTIM_CPT2CR_EXEV7CPT_Pos     (8U)

+#define HRTIM_CPT2CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos)     /*!< 0x00000100 */

+#define HRTIM_CPT2CR_EXEV7CPT         HRTIM_CPT2CR_EXEV7CPT_Msk                /*!< External event 7 capture */

+#define HRTIM_CPT2CR_EXEV8CPT_Pos     (9U)

+#define HRTIM_CPT2CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos)     /*!< 0x00000200 */

+#define HRTIM_CPT2CR_EXEV8CPT         HRTIM_CPT2CR_EXEV8CPT_Msk                /*!< External event 8 capture */

+#define HRTIM_CPT2CR_EXEV9CPT_Pos     (10U)

+#define HRTIM_CPT2CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos)     /*!< 0x00000400 */

+#define HRTIM_CPT2CR_EXEV9CPT         HRTIM_CPT2CR_EXEV9CPT_Msk                /*!< External event 9 capture */

+#define HRTIM_CPT2CR_EXEV10CPT_Pos    (11U)

+#define HRTIM_CPT2CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos)    /*!< 0x00000800 */

+#define HRTIM_CPT2CR_EXEV10CPT        HRTIM_CPT2CR_EXEV10CPT_Msk               /*!< External event 10 capture */

+

+#define HRTIM_CPT2CR_TA1SET_Pos       (12U)

+#define HRTIM_CPT2CR_TA1SET_Msk       (0x1UL << HRTIM_CPT2CR_TA1SET_Pos)       /*!< 0x00001000 */

+#define HRTIM_CPT2CR_TA1SET           HRTIM_CPT2CR_TA1SET_Msk                  /*!< Timer A output 1 set */

+#define HRTIM_CPT2CR_TA1RST_Pos       (13U)

+#define HRTIM_CPT2CR_TA1RST_Msk       (0x1UL << HRTIM_CPT2CR_TA1RST_Pos)       /*!< 0x00002000 */

+#define HRTIM_CPT2CR_TA1RST           HRTIM_CPT2CR_TA1RST_Msk                  /*!< Timer A output 1 reset */

+#define HRTIM_CPT2CR_TIMACMP1_Pos     (14U)

+#define HRTIM_CPT2CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos)     /*!< 0x00004000 */

+#define HRTIM_CPT2CR_TIMACMP1         HRTIM_CPT2CR_TIMACMP1_Msk                /*!< Timer A compare 1 */

+#define HRTIM_CPT2CR_TIMACMP2_Pos     (15U)

+#define HRTIM_CPT2CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos)     /*!< 0x00008000 */

+#define HRTIM_CPT2CR_TIMACMP2         HRTIM_CPT2CR_TIMACMP2_Msk                /*!< Timer A compare 2 */

+

+#define HRTIM_CPT2CR_TB1SET_Pos       (16U)

+#define HRTIM_CPT2CR_TB1SET_Msk       (0x1UL << HRTIM_CPT2CR_TB1SET_Pos)       /*!< 0x00010000 */

+#define HRTIM_CPT2CR_TB1SET           HRTIM_CPT2CR_TB1SET_Msk                  /*!< Timer B output 1 set */

+#define HRTIM_CPT2CR_TB1RST_Pos       (17U)

+#define HRTIM_CPT2CR_TB1RST_Msk       (0x1UL << HRTIM_CPT2CR_TB1RST_Pos)       /*!< 0x00020000 */

+#define HRTIM_CPT2CR_TB1RST           HRTIM_CPT2CR_TB1RST_Msk                  /*!< Timer B output 1 reset */

+#define HRTIM_CPT2CR_TIMBCMP1_Pos     (18U)

+#define HRTIM_CPT2CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos)     /*!< 0x00040000 */

+#define HRTIM_CPT2CR_TIMBCMP1         HRTIM_CPT2CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */

+#define HRTIM_CPT2CR_TIMBCMP2_Pos     (19U)

+#define HRTIM_CPT2CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos)     /*!< 0x00080000 */

+#define HRTIM_CPT2CR_TIMBCMP2         HRTIM_CPT2CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */

+

+#define HRTIM_CPT2CR_TC1SET_Pos       (20U)

+#define HRTIM_CPT2CR_TC1SET_Msk       (0x1UL << HRTIM_CPT2CR_TC1SET_Pos)       /*!< 0x00100000 */

+#define HRTIM_CPT2CR_TC1SET           HRTIM_CPT2CR_TC1SET_Msk                  /*!< Timer C output 1 set */

+#define HRTIM_CPT2CR_TC1RST_Pos       (21U)

+#define HRTIM_CPT2CR_TC1RST_Msk       (0x1UL << HRTIM_CPT2CR_TC1RST_Pos)       /*!< 0x00200000 */

+#define HRTIM_CPT2CR_TC1RST           HRTIM_CPT2CR_TC1RST_Msk                  /*!< Timer C output 1 reset */

+#define HRTIM_CPT2CR_TIMCCMP1_Pos     (22U)

+#define HRTIM_CPT2CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos)     /*!< 0x00400000 */

+#define HRTIM_CPT2CR_TIMCCMP1         HRTIM_CPT2CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */

+#define HRTIM_CPT2CR_TIMCCMP2_Pos     (23U)

+#define HRTIM_CPT2CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos)     /*!< 0x00800000 */

+#define HRTIM_CPT2CR_TIMCCMP2         HRTIM_CPT2CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */

+

+#define HRTIM_CPT2CR_TD1SET_Pos       (24U)

+#define HRTIM_CPT2CR_TD1SET_Msk       (0x1UL << HRTIM_CPT2CR_TD1SET_Pos)       /*!< 0x01000000 */

+#define HRTIM_CPT2CR_TD1SET           HRTIM_CPT2CR_TD1SET_Msk                  /*!< Timer D output 1 set */

+#define HRTIM_CPT2CR_TD1RST_Pos       (25U)

+#define HRTIM_CPT2CR_TD1RST_Msk       (0x1UL << HRTIM_CPT2CR_TD1RST_Pos)       /*!< 0x02000000 */

+#define HRTIM_CPT2CR_TD1RST           HRTIM_CPT2CR_TD1RST_Msk                  /*!< Timer D output 1 reset */

+#define HRTIM_CPT2CR_TIMDCMP1_Pos     (26U)

+#define HRTIM_CPT2CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos)     /*!< 0x04000000 */

+#define HRTIM_CPT2CR_TIMDCMP1         HRTIM_CPT2CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */

+#define HRTIM_CPT2CR_TIMDCMP2_Pos     (27U)

+#define HRTIM_CPT2CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos)     /*!< 0x08000000 */

+#define HRTIM_CPT2CR_TIMDCMP2         HRTIM_CPT2CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */

+

+#define HRTIM_CPT2CR_TE1SET_Pos       (28U)

+#define HRTIM_CPT2CR_TE1SET_Msk       (0x1UL << HRTIM_CPT2CR_TE1SET_Pos)       /*!< 0x10000000 */

+#define HRTIM_CPT2CR_TE1SET           HRTIM_CPT2CR_TE1SET_Msk                  /*!< Timer E output 1 set */

+#define HRTIM_CPT2CR_TE1RST_Pos       (29U)

+#define HRTIM_CPT2CR_TE1RST_Msk       (0x1UL << HRTIM_CPT2CR_TE1RST_Pos)       /*!< 0x20000000 */

+#define HRTIM_CPT2CR_TE1RST           HRTIM_CPT2CR_TE1RST_Msk                  /*!< Timer E output 1 reset */

+#define HRTIM_CPT2CR_TIMECMP1_Pos     (30U)

+#define HRTIM_CPT2CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos)     /*!< 0x40000000 */

+#define HRTIM_CPT2CR_TIMECMP1         HRTIM_CPT2CR_TIMECMP1_Msk                /*!< Timer E compare 1 */

+#define HRTIM_CPT2CR_TIMECMP2_Pos     (31U)

+#define HRTIM_CPT2CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos)     /*!< 0x80000000 */

+#define HRTIM_CPT2CR_TIMECMP2         HRTIM_CPT2CR_TIMECMP2_Msk                /*!< Timer E compare 2 */

+

+/**** Bit definition for Slave Timer Output register **************************/

+#define HRTIM_OUTR_POL1_Pos           (1U)

+#define HRTIM_OUTR_POL1_Msk           (0x1UL << HRTIM_OUTR_POL1_Pos)           /*!< 0x00000002 */

+#define HRTIM_OUTR_POL1               HRTIM_OUTR_POL1_Msk                      /*!< Slave output 1 polarity */

+#define HRTIM_OUTR_IDLM1_Pos          (2U)

+#define HRTIM_OUTR_IDLM1_Msk          (0x1UL << HRTIM_OUTR_IDLM1_Pos)          /*!< 0x00000004 */

+#define HRTIM_OUTR_IDLM1              HRTIM_OUTR_IDLM1_Msk                     /*!< Slave output 1 idle mode */

+#define HRTIM_OUTR_IDLES1_Pos         (3U)

+#define HRTIM_OUTR_IDLES1_Msk         (0x1UL << HRTIM_OUTR_IDLES1_Pos)         /*!< 0x00000008 */

+#define HRTIM_OUTR_IDLES1             HRTIM_OUTR_IDLES1_Msk                    /*!< Slave output 1 idle state */

+#define HRTIM_OUTR_FAULT1_Pos         (4U)

+#define HRTIM_OUTR_FAULT1_Msk         (0x3UL << HRTIM_OUTR_FAULT1_Pos)         /*!< 0x00000030 */

+#define HRTIM_OUTR_FAULT1             HRTIM_OUTR_FAULT1_Msk                    /*!< Slave output 1 fault state */

+#define HRTIM_OUTR_FAULT1_0           (0x1UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000010 */

+#define HRTIM_OUTR_FAULT1_1           (0x2UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000020 */

+#define HRTIM_OUTR_CHP1_Pos           (6U)

+#define HRTIM_OUTR_CHP1_Msk           (0x1UL << HRTIM_OUTR_CHP1_Pos)           /*!< 0x00000040 */

+#define HRTIM_OUTR_CHP1               HRTIM_OUTR_CHP1_Msk                      /*!< Slave output 1 chopper enable */

+#define HRTIM_OUTR_DIDL1_Pos          (7U)

+#define HRTIM_OUTR_DIDL1_Msk          (0x1UL << HRTIM_OUTR_DIDL1_Pos)          /*!< 0x00000080 */

+#define HRTIM_OUTR_DIDL1              HRTIM_OUTR_DIDL1_Msk                     /*!< Slave output 1 dead time idle */

+

+#define HRTIM_OUTR_DTEN_Pos           (8U)

+#define HRTIM_OUTR_DTEN_Msk           (0x1UL << HRTIM_OUTR_DTEN_Pos)           /*!< 0x00000100 */

+#define HRTIM_OUTR_DTEN               HRTIM_OUTR_DTEN_Msk                      /*!< Slave output deadtime enable */

+#define HRTIM_OUTR_DLYPRTEN_Pos       (9U)

+#define HRTIM_OUTR_DLYPRTEN_Msk       (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos)       /*!< 0x00000200 */

+#define HRTIM_OUTR_DLYPRTEN           HRTIM_OUTR_DLYPRTEN_Msk                  /*!< Slave output delay protection enable */

+#define HRTIM_OUTR_DLYPRT_Pos         (10U)

+#define HRTIM_OUTR_DLYPRT_Msk         (0x7UL << HRTIM_OUTR_DLYPRT_Pos)         /*!< 0x00001C00 */

+#define HRTIM_OUTR_DLYPRT             HRTIM_OUTR_DLYPRT_Msk                    /*!< Slave output delay protection */

+#define HRTIM_OUTR_DLYPRT_0           (0x1UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000400 */

+#define HRTIM_OUTR_DLYPRT_1           (0x2UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000800 */

+#define HRTIM_OUTR_DLYPRT_2           (0x4UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00001000 */

+

+#define HRTIM_OUTR_POL2_Pos           (17U)

+#define HRTIM_OUTR_POL2_Msk           (0x1UL << HRTIM_OUTR_POL2_Pos)           /*!< 0x00020000 */

+#define HRTIM_OUTR_POL2               HRTIM_OUTR_POL2_Msk                      /*!< Slave output 2 polarity */

+#define HRTIM_OUTR_IDLM2_Pos          (18U)

+#define HRTIM_OUTR_IDLM2_Msk          (0x1UL << HRTIM_OUTR_IDLM2_Pos)          /*!< 0x00040000 */

+#define HRTIM_OUTR_IDLM2              HRTIM_OUTR_IDLM2_Msk                     /*!< Slave output 2 idle mode */

+#define HRTIM_OUTR_IDLES2_Pos         (19U)

+#define HRTIM_OUTR_IDLES2_Msk         (0x1UL << HRTIM_OUTR_IDLES2_Pos)         /*!< 0x00080000 */

+#define HRTIM_OUTR_IDLES2             HRTIM_OUTR_IDLES2_Msk                    /*!< Slave output 2 idle state */

+#define HRTIM_OUTR_FAULT2_Pos         (20U)

+#define HRTIM_OUTR_FAULT2_Msk         (0x3UL << HRTIM_OUTR_FAULT2_Pos)         /*!< 0x00300000 */

+#define HRTIM_OUTR_FAULT2             HRTIM_OUTR_FAULT2_Msk                    /*!< Slave output 2 fault state */

+#define HRTIM_OUTR_FAULT2_0           (0x1UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00100000 */

+#define HRTIM_OUTR_FAULT2_1           (0x2UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00200000 */

+#define HRTIM_OUTR_CHP2_Pos           (22U)

+#define HRTIM_OUTR_CHP2_Msk           (0x1UL << HRTIM_OUTR_CHP2_Pos)           /*!< 0x00400000 */

+#define HRTIM_OUTR_CHP2               HRTIM_OUTR_CHP2_Msk                      /*!< Slave output 2 chopper enable */

+#define HRTIM_OUTR_DIDL2_Pos          (23U)

+#define HRTIM_OUTR_DIDL2_Msk          (0x1UL << HRTIM_OUTR_DIDL2_Pos)          /*!< 0x00800000 */

+#define HRTIM_OUTR_DIDL2              HRTIM_OUTR_DIDL2_Msk                     /*!< Slave output 2 dead time idle */

+

+/**** Bit definition for Slave Timer Fault register ***************************/

+#define HRTIM_FLTR_FLT1EN_Pos         (0U)

+#define HRTIM_FLTR_FLT1EN_Msk         (0x1UL << HRTIM_FLTR_FLT1EN_Pos)         /*!< 0x00000001 */

+#define HRTIM_FLTR_FLT1EN             HRTIM_FLTR_FLT1EN_Msk                    /*!< Fault 1 enable */

+#define HRTIM_FLTR_FLT2EN_Pos         (1U)

+#define HRTIM_FLTR_FLT2EN_Msk         (0x1UL << HRTIM_FLTR_FLT2EN_Pos)         /*!< 0x00000002 */

+#define HRTIM_FLTR_FLT2EN             HRTIM_FLTR_FLT2EN_Msk                    /*!< Fault 2 enable */

+#define HRTIM_FLTR_FLT3EN_Pos         (2U)

+#define HRTIM_FLTR_FLT3EN_Msk         (0x1UL << HRTIM_FLTR_FLT3EN_Pos)         /*!< 0x00000004 */

+#define HRTIM_FLTR_FLT3EN             HRTIM_FLTR_FLT3EN_Msk                    /*!< Fault 3 enable */

+#define HRTIM_FLTR_FLT4EN_Pos         (3U)

+#define HRTIM_FLTR_FLT4EN_Msk         (0x1UL << HRTIM_FLTR_FLT4EN_Pos)         /*!< 0x00000008 */

+#define HRTIM_FLTR_FLT4EN             HRTIM_FLTR_FLT4EN_Msk                    /*!< Fault 4 enable */

+#define HRTIM_FLTR_FLT5EN_Pos         (4U)

+#define HRTIM_FLTR_FLT5EN_Msk         (0x1UL << HRTIM_FLTR_FLT5EN_Pos)         /*!< 0x00000010 */

+#define HRTIM_FLTR_FLT5EN             HRTIM_FLTR_FLT5EN_Msk                    /*!< Fault 5 enable */

+#define HRTIM_FLTR_FLTLCK_Pos         (31U)

+#define HRTIM_FLTR_FLTLCK_Msk         (0x1UL << HRTIM_FLTR_FLTLCK_Pos)         /*!< 0x80000000 */

+#define HRTIM_FLTR_FLTLCK             HRTIM_FLTR_FLTLCK_Msk                    /*!< Fault sources lock */

+

+/**** Bit definition for Common HRTIM Timer control register 1 ****************/

+#define HRTIM_CR1_MUDIS_Pos           (0U)

+#define HRTIM_CR1_MUDIS_Msk           (0x1UL << HRTIM_CR1_MUDIS_Pos)           /*!< 0x00000001 */

+#define HRTIM_CR1_MUDIS               HRTIM_CR1_MUDIS_Msk                      /*!< Master update disable*/

+#define HRTIM_CR1_TAUDIS_Pos          (1U)

+#define HRTIM_CR1_TAUDIS_Msk          (0x1UL << HRTIM_CR1_TAUDIS_Pos)          /*!< 0x00000002 */

+#define HRTIM_CR1_TAUDIS              HRTIM_CR1_TAUDIS_Msk                     /*!< Timer A update disable*/

+#define HRTIM_CR1_TBUDIS_Pos          (2U)

+#define HRTIM_CR1_TBUDIS_Msk          (0x1UL << HRTIM_CR1_TBUDIS_Pos)          /*!< 0x00000004 */

+#define HRTIM_CR1_TBUDIS              HRTIM_CR1_TBUDIS_Msk                     /*!< Timer B update disable*/

+#define HRTIM_CR1_TCUDIS_Pos          (3U)

+#define HRTIM_CR1_TCUDIS_Msk          (0x1UL << HRTIM_CR1_TCUDIS_Pos)          /*!< 0x00000008 */

+#define HRTIM_CR1_TCUDIS              HRTIM_CR1_TCUDIS_Msk                     /*!< Timer C update disable*/

+#define HRTIM_CR1_TDUDIS_Pos          (4U)

+#define HRTIM_CR1_TDUDIS_Msk          (0x1UL << HRTIM_CR1_TDUDIS_Pos)          /*!< 0x00000010 */

+#define HRTIM_CR1_TDUDIS              HRTIM_CR1_TDUDIS_Msk                     /*!< Timer D update disable*/

+#define HRTIM_CR1_TEUDIS_Pos          (5U)

+#define HRTIM_CR1_TEUDIS_Msk          (0x1UL << HRTIM_CR1_TEUDIS_Pos)          /*!< 0x00000020 */

+#define HRTIM_CR1_TEUDIS              HRTIM_CR1_TEUDIS_Msk                     /*!< Timer E update disable*/

+#define HRTIM_CR1_ADC1USRC_Pos        (16U)

+#define HRTIM_CR1_ADC1USRC_Msk        (0x7UL << HRTIM_CR1_ADC1USRC_Pos)        /*!< 0x00070000 */

+#define HRTIM_CR1_ADC1USRC            HRTIM_CR1_ADC1USRC_Msk                   /*!< ADC Trigger 1 update source */

+#define HRTIM_CR1_ADC1USRC_0          (0x1UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00010000 */

+#define HRTIM_CR1_ADC1USRC_1          (0x2UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00020000 */

+#define HRTIM_CR1_ADC1USRC_2          (0x4UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00040000 */

+#define HRTIM_CR1_ADC2USRC_Pos        (19U)

+#define HRTIM_CR1_ADC2USRC_Msk        (0x7UL << HRTIM_CR1_ADC2USRC_Pos)        /*!< 0x00380000 */

+#define HRTIM_CR1_ADC2USRC            HRTIM_CR1_ADC2USRC_Msk                   /*!< ADC Trigger 2 update source */

+#define HRTIM_CR1_ADC2USRC_0          (0x1UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00080000 */

+#define HRTIM_CR1_ADC2USRC_1          (0x2UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00100000 */

+#define HRTIM_CR1_ADC2USRC_2          (0x4UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00200000 */

+#define HRTIM_CR1_ADC3USRC_Pos        (22U)

+#define HRTIM_CR1_ADC3USRC_Msk        (0x7UL << HRTIM_CR1_ADC3USRC_Pos)        /*!< 0x01C00000 */

+#define HRTIM_CR1_ADC3USRC            HRTIM_CR1_ADC3USRC_Msk                   /*!< ADC Trigger 3 update source */

+#define HRTIM_CR1_ADC3USRC_0          (0x1UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00400000 */

+#define HRTIM_CR1_ADC3USRC_1          (0x2UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00800000 */

+#define HRTIM_CR1_ADC3USRC_2          (0x4UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x01000000 */

+#define HRTIM_CR1_ADC4USRC_Pos        (25U)

+#define HRTIM_CR1_ADC4USRC_Msk        (0x7UL << HRTIM_CR1_ADC4USRC_Pos)        /*!< 0x0E000000 */

+#define HRTIM_CR1_ADC4USRC            HRTIM_CR1_ADC4USRC_Msk                   /*!< ADC Trigger 4 update source */

+#define HRTIM_CR1_ADC4USRC_0          (0x1UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x02000000 */

+#define HRTIM_CR1_ADC4USRC_1          (0x2UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x04000000 */

+#define HRTIM_CR1_ADC4USRC_2          (0x0UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x0800000 */

+

+/**** Bit definition for Common HRTIM Timer control register 2 ****************/

+#define HRTIM_CR2_MSWU_Pos            (0U)

+#define HRTIM_CR2_MSWU_Msk            (0x1UL << HRTIM_CR2_MSWU_Pos)            /*!< 0x00000001 */

+#define HRTIM_CR2_MSWU                HRTIM_CR2_MSWU_Msk                       /*!< Master software update */

+#define HRTIM_CR2_TASWU_Pos           (1U)

+#define HRTIM_CR2_TASWU_Msk           (0x1UL << HRTIM_CR2_TASWU_Pos)           /*!< 0x00000002 */

+#define HRTIM_CR2_TASWU               HRTIM_CR2_TASWU_Msk                      /*!< Timer A software update */

+#define HRTIM_CR2_TBSWU_Pos           (2U)

+#define HRTIM_CR2_TBSWU_Msk           (0x1UL << HRTIM_CR2_TBSWU_Pos)           /*!< 0x00000004 */

+#define HRTIM_CR2_TBSWU               HRTIM_CR2_TBSWU_Msk                      /*!< Timer B software update */

+#define HRTIM_CR2_TCSWU_Pos           (3U)

+#define HRTIM_CR2_TCSWU_Msk           (0x1UL << HRTIM_CR2_TCSWU_Pos)           /*!< 0x00000008 */

+#define HRTIM_CR2_TCSWU               HRTIM_CR2_TCSWU_Msk                      /*!< Timer C software update */

+#define HRTIM_CR2_TDSWU_Pos           (4U)

+#define HRTIM_CR2_TDSWU_Msk           (0x1UL << HRTIM_CR2_TDSWU_Pos)           /*!< 0x00000010 */

+#define HRTIM_CR2_TDSWU               HRTIM_CR2_TDSWU_Msk                      /*!< Timer D software update */

+#define HRTIM_CR2_TESWU_Pos           (5U)

+#define HRTIM_CR2_TESWU_Msk           (0x1UL << HRTIM_CR2_TESWU_Pos)           /*!< 0x00000020 */

+#define HRTIM_CR2_TESWU               HRTIM_CR2_TESWU_Msk                      /*!< Timer E software update */

+#define HRTIM_CR2_MRST_Pos            (8U)

+#define HRTIM_CR2_MRST_Msk            (0x1UL << HRTIM_CR2_MRST_Pos)            /*!< 0x00000100 */

+#define HRTIM_CR2_MRST                HRTIM_CR2_MRST_Msk                       /*!< Master count software reset */

+#define HRTIM_CR2_TARST_Pos           (9U)

+#define HRTIM_CR2_TARST_Msk           (0x1UL << HRTIM_CR2_TARST_Pos)           /*!< 0x00000200 */

+#define HRTIM_CR2_TARST               HRTIM_CR2_TARST_Msk                      /*!< Timer A count software reset */

+#define HRTIM_CR2_TBRST_Pos           (10U)

+#define HRTIM_CR2_TBRST_Msk           (0x1UL << HRTIM_CR2_TBRST_Pos)           /*!< 0x00000400 */

+#define HRTIM_CR2_TBRST               HRTIM_CR2_TBRST_Msk                      /*!< Timer B count software reset */

+#define HRTIM_CR2_TCRST_Pos           (11U)

+#define HRTIM_CR2_TCRST_Msk           (0x1UL << HRTIM_CR2_TCRST_Pos)           /*!< 0x00000800 */

+#define HRTIM_CR2_TCRST               HRTIM_CR2_TCRST_Msk                      /*!< Timer C count software reset */

+#define HRTIM_CR2_TDRST_Pos           (12U)

+#define HRTIM_CR2_TDRST_Msk           (0x1UL << HRTIM_CR2_TDRST_Pos)           /*!< 0x00001000 */

+#define HRTIM_CR2_TDRST               HRTIM_CR2_TDRST_Msk                      /*!< Timer D count software reset */

+#define HRTIM_CR2_TERST_Pos           (13U)

+#define HRTIM_CR2_TERST_Msk           (0x1UL << HRTIM_CR2_TERST_Pos)           /*!< 0x00002000 */

+#define HRTIM_CR2_TERST               HRTIM_CR2_TERST_Msk                      /*!< Timer E count software reset */

+

+/**** Bit definition for Common HRTIM Timer interrupt status register *********/

+#define HRTIM_ISR_FLT1_Pos            (0U)

+#define HRTIM_ISR_FLT1_Msk            (0x1UL << HRTIM_ISR_FLT1_Pos)            /*!< 0x00000001 */

+#define HRTIM_ISR_FLT1                HRTIM_ISR_FLT1_Msk                       /*!< Fault 1 interrupt flag */

+#define HRTIM_ISR_FLT2_Pos            (1U)

+#define HRTIM_ISR_FLT2_Msk            (0x1UL << HRTIM_ISR_FLT2_Pos)            /*!< 0x00000002 */

+#define HRTIM_ISR_FLT2                HRTIM_ISR_FLT2_Msk                       /*!< Fault 2 interrupt flag */

+#define HRTIM_ISR_FLT3_Pos            (2U)

+#define HRTIM_ISR_FLT3_Msk            (0x1UL << HRTIM_ISR_FLT3_Pos)            /*!< 0x00000004 */

+#define HRTIM_ISR_FLT3                HRTIM_ISR_FLT3_Msk                       /*!< Fault 3 interrupt flag */

+#define HRTIM_ISR_FLT4_Pos            (3U)

+#define HRTIM_ISR_FLT4_Msk            (0x1UL << HRTIM_ISR_FLT4_Pos)            /*!< 0x00000008 */

+#define HRTIM_ISR_FLT4                HRTIM_ISR_FLT4_Msk                       /*!< Fault 4 interrupt flag */

+#define HRTIM_ISR_FLT5_Pos            (4U)

+#define HRTIM_ISR_FLT5_Msk            (0x1UL << HRTIM_ISR_FLT5_Pos)            /*!< 0x00000010 */

+#define HRTIM_ISR_FLT5                HRTIM_ISR_FLT5_Msk                       /*!< Fault 5 interrupt flag */

+#define HRTIM_ISR_SYSFLT_Pos          (5U)

+#define HRTIM_ISR_SYSFLT_Msk          (0x1UL << HRTIM_ISR_SYSFLT_Pos)          /*!< 0x00000020 */

+#define HRTIM_ISR_SYSFLT              HRTIM_ISR_SYSFLT_Msk                     /*!< System Fault interrupt flag */

+#define HRTIM_ISR_BMPER_Pos           (17U)

+#define HRTIM_ISR_BMPER_Msk           (0x1UL << HRTIM_ISR_BMPER_Pos)           /*!< 0x00020000 */

+#define HRTIM_ISR_BMPER               HRTIM_ISR_BMPER_Msk                      /*!<  Burst mode period interrupt flag */

+

+/**** Bit definition for Common HRTIM Timer interrupt clear register **********/

+#define HRTIM_ICR_FLT1C_Pos           (0U)

+#define HRTIM_ICR_FLT1C_Msk           (0x1UL << HRTIM_ICR_FLT1C_Pos)           /*!< 0x00000001 */

+#define HRTIM_ICR_FLT1C               HRTIM_ICR_FLT1C_Msk                      /*!< Fault 1 interrupt flag clear */

+#define HRTIM_ICR_FLT2C_Pos           (1U)

+#define HRTIM_ICR_FLT2C_Msk           (0x1UL << HRTIM_ICR_FLT2C_Pos)           /*!< 0x00000002 */

+#define HRTIM_ICR_FLT2C               HRTIM_ICR_FLT2C_Msk                      /*!< Fault 2 interrupt flag clear */

+#define HRTIM_ICR_FLT3C_Pos           (2U)

+#define HRTIM_ICR_FLT3C_Msk           (0x1UL << HRTIM_ICR_FLT3C_Pos)           /*!< 0x00000004 */

+#define HRTIM_ICR_FLT3C               HRTIM_ICR_FLT3C_Msk                      /*!< Fault 3 interrupt flag clear */

+#define HRTIM_ICR_FLT4C_Pos           (3U)

+#define HRTIM_ICR_FLT4C_Msk           (0x1UL << HRTIM_ICR_FLT4C_Pos)           /*!< 0x00000008 */

+#define HRTIM_ICR_FLT4C               HRTIM_ICR_FLT4C_Msk                      /*!< Fault 4 interrupt flag clear */

+#define HRTIM_ICR_FLT5C_Pos           (4U)

+#define HRTIM_ICR_FLT5C_Msk           (0x1UL << HRTIM_ICR_FLT5C_Pos)           /*!< 0x00000010 */

+#define HRTIM_ICR_FLT5C               HRTIM_ICR_FLT5C_Msk                      /*!< Fault 5 interrupt flag clear */

+#define HRTIM_ICR_SYSFLTC_Pos         (5U)

+#define HRTIM_ICR_SYSFLTC_Msk         (0x1UL << HRTIM_ICR_SYSFLTC_Pos)         /*!< 0x00000020 */

+#define HRTIM_ICR_SYSFLTC             HRTIM_ICR_SYSFLTC_Msk                    /*!< System Fault interrupt flag clear */

+#define HRTIM_ICR_BMPERC_Pos          (17U)

+#define HRTIM_ICR_BMPERC_Msk          (0x1UL << HRTIM_ICR_BMPERC_Pos)          /*!< 0x00020000 */

+#define HRTIM_ICR_BMPERC              HRTIM_ICR_BMPERC_Msk                     /*!<  Burst mode period interrupt flag clear */

+

+/**** Bit definition for Common HRTIM Timer interrupt enable register *********/

+#define HRTIM_IER_FLT1_Pos            (0U)

+#define HRTIM_IER_FLT1_Msk            (0x1UL << HRTIM_IER_FLT1_Pos)            /*!< 0x00000001 */

+#define HRTIM_IER_FLT1                HRTIM_IER_FLT1_Msk                       /*!< Fault 1 interrupt enable */

+#define HRTIM_IER_FLT2_Pos            (1U)

+#define HRTIM_IER_FLT2_Msk            (0x1UL << HRTIM_IER_FLT2_Pos)            /*!< 0x00000002 */

+#define HRTIM_IER_FLT2                HRTIM_IER_FLT2_Msk                       /*!< Fault 2 interrupt enable */

+#define HRTIM_IER_FLT3_Pos            (2U)

+#define HRTIM_IER_FLT3_Msk            (0x1UL << HRTIM_IER_FLT3_Pos)            /*!< 0x00000004 */

+#define HRTIM_IER_FLT3                HRTIM_IER_FLT3_Msk                       /*!< Fault 3 interrupt enable */

+#define HRTIM_IER_FLT4_Pos            (3U)

+#define HRTIM_IER_FLT4_Msk            (0x1UL << HRTIM_IER_FLT4_Pos)            /*!< 0x00000008 */

+#define HRTIM_IER_FLT4                HRTIM_IER_FLT4_Msk                       /*!< Fault 4 interrupt enable */

+#define HRTIM_IER_FLT5_Pos            (4U)

+#define HRTIM_IER_FLT5_Msk            (0x1UL << HRTIM_IER_FLT5_Pos)            /*!< 0x00000010 */

+#define HRTIM_IER_FLT5                HRTIM_IER_FLT5_Msk                       /*!< Fault 5 interrupt enable */

+#define HRTIM_IER_SYSFLT_Pos          (5U)

+#define HRTIM_IER_SYSFLT_Msk          (0x1UL << HRTIM_IER_SYSFLT_Pos)          /*!< 0x00000020 */

+#define HRTIM_IER_SYSFLT              HRTIM_IER_SYSFLT_Msk                     /*!< System Fault interrupt enable */

+#define HRTIM_IER_BMPER_Pos           (17U)

+#define HRTIM_IER_BMPER_Msk           (0x1UL << HRTIM_IER_BMPER_Pos)           /*!< 0x00020000 */

+#define HRTIM_IER_BMPER               HRTIM_IER_BMPER_Msk                      /*!<  Burst mode period interrupt enable */

+

+/**** Bit definition for Common HRTIM Timer output enable register ************/

+#define HRTIM_OENR_TA1OEN_Pos         (0U)

+#define HRTIM_OENR_TA1OEN_Msk         (0x1UL << HRTIM_OENR_TA1OEN_Pos)         /*!< 0x00000001 */

+#define HRTIM_OENR_TA1OEN             HRTIM_OENR_TA1OEN_Msk                    /*!< Timer A Output 1 enable */

+#define HRTIM_OENR_TA2OEN_Pos         (1U)

+#define HRTIM_OENR_TA2OEN_Msk         (0x1UL << HRTIM_OENR_TA2OEN_Pos)         /*!< 0x00000002 */

+#define HRTIM_OENR_TA2OEN             HRTIM_OENR_TA2OEN_Msk                    /*!< Timer A Output 2 enable */

+#define HRTIM_OENR_TB1OEN_Pos         (2U)

+#define HRTIM_OENR_TB1OEN_Msk         (0x1UL << HRTIM_OENR_TB1OEN_Pos)         /*!< 0x00000004 */

+#define HRTIM_OENR_TB1OEN             HRTIM_OENR_TB1OEN_Msk                    /*!< Timer B Output 1 enable */

+#define HRTIM_OENR_TB2OEN_Pos         (3U)

+#define HRTIM_OENR_TB2OEN_Msk         (0x1UL << HRTIM_OENR_TB2OEN_Pos)         /*!< 0x00000008 */

+#define HRTIM_OENR_TB2OEN             HRTIM_OENR_TB2OEN_Msk                    /*!< Timer B Output 2 enable */

+#define HRTIM_OENR_TC1OEN_Pos         (4U)

+#define HRTIM_OENR_TC1OEN_Msk         (0x1UL << HRTIM_OENR_TC1OEN_Pos)         /*!< 0x00000010 */

+#define HRTIM_OENR_TC1OEN             HRTIM_OENR_TC1OEN_Msk                    /*!< Timer C Output 1 enable */

+#define HRTIM_OENR_TC2OEN_Pos         (5U)

+#define HRTIM_OENR_TC2OEN_Msk         (0x1UL << HRTIM_OENR_TC2OEN_Pos)         /*!< 0x00000020 */

+#define HRTIM_OENR_TC2OEN             HRTIM_OENR_TC2OEN_Msk                    /*!< Timer C Output 2 enable */

+#define HRTIM_OENR_TD1OEN_Pos         (6U)

+#define HRTIM_OENR_TD1OEN_Msk         (0x1UL << HRTIM_OENR_TD1OEN_Pos)         /*!< 0x00000040 */

+#define HRTIM_OENR_TD1OEN             HRTIM_OENR_TD1OEN_Msk                    /*!< Timer D Output 1 enable */

+#define HRTIM_OENR_TD2OEN_Pos         (7U)

+#define HRTIM_OENR_TD2OEN_Msk         (0x1UL << HRTIM_OENR_TD2OEN_Pos)         /*!< 0x00000080 */

+#define HRTIM_OENR_TD2OEN             HRTIM_OENR_TD2OEN_Msk                    /*!< Timer D Output 2 enable */

+#define HRTIM_OENR_TE1OEN_Pos         (8U)

+#define HRTIM_OENR_TE1OEN_Msk         (0x1UL << HRTIM_OENR_TE1OEN_Pos)         /*!< 0x00000100 */

+#define HRTIM_OENR_TE1OEN             HRTIM_OENR_TE1OEN_Msk                    /*!< Timer E Output 1 enable */

+#define HRTIM_OENR_TE2OEN_Pos         (9U)

+#define HRTIM_OENR_TE2OEN_Msk         (0x1UL << HRTIM_OENR_TE2OEN_Pos)         /*!< 0x00000200 */

+#define HRTIM_OENR_TE2OEN             HRTIM_OENR_TE2OEN_Msk                    /*!< Timer E Output 2 enable */

+

+/**** Bit definition for Common HRTIM Timer output disable register ***********/

+#define HRTIM_ODISR_TA1ODIS_Pos       (0U)

+#define HRTIM_ODISR_TA1ODIS_Msk       (0x1UL << HRTIM_ODISR_TA1ODIS_Pos)       /*!< 0x00000001 */

+#define HRTIM_ODISR_TA1ODIS           HRTIM_ODISR_TA1ODIS_Msk                  /*!< Timer A Output 1 disable */

+#define HRTIM_ODISR_TA2ODIS_Pos       (1U)

+#define HRTIM_ODISR_TA2ODIS_Msk       (0x1UL << HRTIM_ODISR_TA2ODIS_Pos)       /*!< 0x00000002 */

+#define HRTIM_ODISR_TA2ODIS           HRTIM_ODISR_TA2ODIS_Msk                  /*!< Timer A Output 2 disable */

+#define HRTIM_ODISR_TB1ODIS_Pos       (2U)

+#define HRTIM_ODISR_TB1ODIS_Msk       (0x1UL << HRTIM_ODISR_TB1ODIS_Pos)       /*!< 0x00000004 */

+#define HRTIM_ODISR_TB1ODIS           HRTIM_ODISR_TB1ODIS_Msk                  /*!< Timer B Output 1 disable */

+#define HRTIM_ODISR_TB2ODIS_Pos       (3U)

+#define HRTIM_ODISR_TB2ODIS_Msk       (0x1UL << HRTIM_ODISR_TB2ODIS_Pos)       /*!< 0x00000008 */

+#define HRTIM_ODISR_TB2ODIS           HRTIM_ODISR_TB2ODIS_Msk                  /*!< Timer B Output 2 disable */

+#define HRTIM_ODISR_TC1ODIS_Pos       (4U)

+#define HRTIM_ODISR_TC1ODIS_Msk       (0x1UL << HRTIM_ODISR_TC1ODIS_Pos)       /*!< 0x00000010 */

+#define HRTIM_ODISR_TC1ODIS           HRTIM_ODISR_TC1ODIS_Msk                  /*!< Timer C Output 1 disable */

+#define HRTIM_ODISR_TC2ODIS_Pos       (5U)

+#define HRTIM_ODISR_TC2ODIS_Msk       (0x1UL << HRTIM_ODISR_TC2ODIS_Pos)       /*!< 0x00000020 */

+#define HRTIM_ODISR_TC2ODIS           HRTIM_ODISR_TC2ODIS_Msk                  /*!< Timer C Output 2 disable */

+#define HRTIM_ODISR_TD1ODIS_Pos       (6U)

+#define HRTIM_ODISR_TD1ODIS_Msk       (0x1UL << HRTIM_ODISR_TD1ODIS_Pos)       /*!< 0x00000040 */

+#define HRTIM_ODISR_TD1ODIS           HRTIM_ODISR_TD1ODIS_Msk                  /*!< Timer D Output 1 disable */

+#define HRTIM_ODISR_TD2ODIS_Pos       (7U)

+#define HRTIM_ODISR_TD2ODIS_Msk       (0x1UL << HRTIM_ODISR_TD2ODIS_Pos)       /*!< 0x00000080 */

+#define HRTIM_ODISR_TD2ODIS           HRTIM_ODISR_TD2ODIS_Msk                  /*!< Timer D Output 2 disable */

+#define HRTIM_ODISR_TE1ODIS_Pos       (8U)

+#define HRTIM_ODISR_TE1ODIS_Msk       (0x1UL << HRTIM_ODISR_TE1ODIS_Pos)       /*!< 0x00000100 */

+#define HRTIM_ODISR_TE1ODIS           HRTIM_ODISR_TE1ODIS_Msk                  /*!< Timer E Output 1 disable */

+#define HRTIM_ODISR_TE2ODIS_Pos       (9U)

+#define HRTIM_ODISR_TE2ODIS_Msk       (0x1UL << HRTIM_ODISR_TE2ODIS_Pos)       /*!< 0x00000200 */

+#define HRTIM_ODISR_TE2ODIS           HRTIM_ODISR_TE2ODIS_Msk                  /*!< Timer E Output 2 disable */

+

+/**** Bit definition for Common HRTIM Timer output disable status register *****/

+#define HRTIM_ODSR_TA1ODS_Pos         (0U)

+#define HRTIM_ODSR_TA1ODS_Msk         (0x1UL << HRTIM_ODSR_TA1ODS_Pos)         /*!< 0x00000001 */

+#define HRTIM_ODSR_TA1ODS             HRTIM_ODSR_TA1ODS_Msk                    /*!< Timer A Output 1 disable status */

+#define HRTIM_ODSR_TA2ODS_Pos         (1U)

+#define HRTIM_ODSR_TA2ODS_Msk         (0x1UL << HRTIM_ODSR_TA2ODS_Pos)         /*!< 0x00000002 */

+#define HRTIM_ODSR_TA2ODS             HRTIM_ODSR_TA2ODS_Msk                    /*!< Timer A Output 2 disable status */

+#define HRTIM_ODSR_TB1ODS_Pos         (2U)

+#define HRTIM_ODSR_TB1ODS_Msk         (0x1UL << HRTIM_ODSR_TB1ODS_Pos)         /*!< 0x00000004 */

+#define HRTIM_ODSR_TB1ODS             HRTIM_ODSR_TB1ODS_Msk                    /*!< Timer B Output 1 disable status */

+#define HRTIM_ODSR_TB2ODS_Pos         (3U)

+#define HRTIM_ODSR_TB2ODS_Msk         (0x1UL << HRTIM_ODSR_TB2ODS_Pos)         /*!< 0x00000008 */

+#define HRTIM_ODSR_TB2ODS             HRTIM_ODSR_TB2ODS_Msk                    /*!< Timer B Output 2 disable status */

+#define HRTIM_ODSR_TC1ODS_Pos         (4U)

+#define HRTIM_ODSR_TC1ODS_Msk         (0x1UL << HRTIM_ODSR_TC1ODS_Pos)         /*!< 0x00000010 */

+#define HRTIM_ODSR_TC1ODS             HRTIM_ODSR_TC1ODS_Msk                    /*!< Timer C Output 1 disable status */

+#define HRTIM_ODSR_TC2ODS_Pos         (5U)

+#define HRTIM_ODSR_TC2ODS_Msk         (0x1UL << HRTIM_ODSR_TC2ODS_Pos)         /*!< 0x00000020 */

+#define HRTIM_ODSR_TC2ODS             HRTIM_ODSR_TC2ODS_Msk                    /*!< Timer C Output 2 disable status */

+#define HRTIM_ODSR_TD1ODS_Pos         (6U)

+#define HRTIM_ODSR_TD1ODS_Msk         (0x1UL << HRTIM_ODSR_TD1ODS_Pos)         /*!< 0x00000040 */

+#define HRTIM_ODSR_TD1ODS             HRTIM_ODSR_TD1ODS_Msk                    /*!< Timer D Output 1 disable status */

+#define HRTIM_ODSR_TD2ODS_Pos         (7U)

+#define HRTIM_ODSR_TD2ODS_Msk         (0x1UL << HRTIM_ODSR_TD2ODS_Pos)         /*!< 0x00000080 */

+#define HRTIM_ODSR_TD2ODS             HRTIM_ODSR_TD2ODS_Msk                    /*!< Timer D Output 2 disable status */

+#define HRTIM_ODSR_TE1ODS_Pos         (8U)

+#define HRTIM_ODSR_TE1ODS_Msk         (0x1UL << HRTIM_ODSR_TE1ODS_Pos)         /*!< 0x00000100 */

+#define HRTIM_ODSR_TE1ODS             HRTIM_ODSR_TE1ODS_Msk                    /*!< Timer E Output 1 disable status */

+#define HRTIM_ODSR_TE2ODS_Pos         (9U)

+#define HRTIM_ODSR_TE2ODS_Msk         (0x1UL << HRTIM_ODSR_TE2ODS_Pos)         /*!< 0x00000200 */

+#define HRTIM_ODSR_TE2ODS             HRTIM_ODSR_TE2ODS_Msk                    /*!< Timer E Output 2 disable status */

+

+/**** Bit definition for Common HRTIM Timer Burst mode control register ********/

+#define HRTIM_BMCR_BME_Pos            (0U)

+#define HRTIM_BMCR_BME_Msk            (0x1UL << HRTIM_BMCR_BME_Pos)            /*!< 0x00000001 */

+#define HRTIM_BMCR_BME                HRTIM_BMCR_BME_Msk                       /*!< Burst mode enbale */

+#define HRTIM_BMCR_BMOM_Pos           (1U)

+#define HRTIM_BMCR_BMOM_Msk           (0x1UL << HRTIM_BMCR_BMOM_Pos)           /*!< 0x00000002 */

+#define HRTIM_BMCR_BMOM               HRTIM_BMCR_BMOM_Msk                      /*!< Burst mode operating mode */

+#define HRTIM_BMCR_BMCLK_Pos          (2U)

+#define HRTIM_BMCR_BMCLK_Msk          (0xFUL << HRTIM_BMCR_BMCLK_Pos)          /*!< 0x0000003C */

+#define HRTIM_BMCR_BMCLK              HRTIM_BMCR_BMCLK_Msk                     /*!< Burst mode clock source */

+#define HRTIM_BMCR_BMCLK_0            (0x1UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000004 */

+#define HRTIM_BMCR_BMCLK_1            (0x2UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000008 */

+#define HRTIM_BMCR_BMCLK_2            (0x4UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000010 */

+#define HRTIM_BMCR_BMCLK_3            (0x8UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000020 */

+#define HRTIM_BMCR_BMPRSC_Pos         (6U)

+#define HRTIM_BMCR_BMPRSC_Msk         (0xFUL << HRTIM_BMCR_BMPRSC_Pos)         /*!< 0x000003C0 */

+#define HRTIM_BMCR_BMPRSC             HRTIM_BMCR_BMPRSC_Msk                    /*!< Burst mode prescaler */

+#define HRTIM_BMCR_BMPRSC_0           (0x1UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000040 */

+#define HRTIM_BMCR_BMPRSC_1           (0x2UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000080 */

+#define HRTIM_BMCR_BMPRSC_2           (0x4UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000100 */

+#define HRTIM_BMCR_BMPRSC_3           (0x8UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000200 */

+#define HRTIM_BMCR_BMPREN_Pos         (10U)

+#define HRTIM_BMCR_BMPREN_Msk         (0x1UL << HRTIM_BMCR_BMPREN_Pos)         /*!< 0x00000400 */

+#define HRTIM_BMCR_BMPREN             HRTIM_BMCR_BMPREN_Msk                    /*!< Burst mode Preload bit */

+#define HRTIM_BMCR_MTBM_Pos           (16U)

+#define HRTIM_BMCR_MTBM_Msk           (0x1UL << HRTIM_BMCR_MTBM_Pos)           /*!< 0x00010000 */

+#define HRTIM_BMCR_MTBM               HRTIM_BMCR_MTBM_Msk                      /*!< Master Timer Burst mode */

+#define HRTIM_BMCR_TABM_Pos           (17U)

+#define HRTIM_BMCR_TABM_Msk           (0x1UL << HRTIM_BMCR_TABM_Pos)           /*!< 0x00020000 */

+#define HRTIM_BMCR_TABM               HRTIM_BMCR_TABM_Msk                      /*!< Timer A Burst mode */

+#define HRTIM_BMCR_TBBM_Pos           (18U)

+#define HRTIM_BMCR_TBBM_Msk           (0x1UL << HRTIM_BMCR_TBBM_Pos)           /*!< 0x00040000 */

+#define HRTIM_BMCR_TBBM               HRTIM_BMCR_TBBM_Msk                      /*!< Timer B Burst mode */

+#define HRTIM_BMCR_TCBM_Pos           (19U)

+#define HRTIM_BMCR_TCBM_Msk           (0x1UL << HRTIM_BMCR_TCBM_Pos)           /*!< 0x00080000 */

+#define HRTIM_BMCR_TCBM               HRTIM_BMCR_TCBM_Msk                      /*!< Timer C Burst mode */

+#define HRTIM_BMCR_TDBM_Pos           (20U)

+#define HRTIM_BMCR_TDBM_Msk           (0x1UL << HRTIM_BMCR_TDBM_Pos)           /*!< 0x00100000 */

+#define HRTIM_BMCR_TDBM               HRTIM_BMCR_TDBM_Msk                      /*!< Timer D Burst mode */

+#define HRTIM_BMCR_TEBM_Pos           (21U)

+#define HRTIM_BMCR_TEBM_Msk           (0x1UL << HRTIM_BMCR_TEBM_Pos)           /*!< 0x00200000 */

+#define HRTIM_BMCR_TEBM               HRTIM_BMCR_TEBM_Msk                      /*!< Timer E Burst mode */

+#define HRTIM_BMCR_BMSTAT_Pos         (31U)

+#define HRTIM_BMCR_BMSTAT_Msk         (0x1UL << HRTIM_BMCR_BMSTAT_Pos)         /*!< 0x80000000 */

+#define HRTIM_BMCR_BMSTAT             HRTIM_BMCR_BMSTAT_Msk                    /*!< Burst mode status */

+

+/**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/

+#define HRTIM_BMTRGR_SW_Pos           (0U)

+#define HRTIM_BMTRGR_SW_Msk           (0x1UL << HRTIM_BMTRGR_SW_Pos)           /*!< 0x00000001 */

+#define HRTIM_BMTRGR_SW               HRTIM_BMTRGR_SW_Msk                      /*!< Software start */

+#define HRTIM_BMTRGR_MSTRST_Pos       (1U)

+#define HRTIM_BMTRGR_MSTRST_Msk       (0x1UL << HRTIM_BMTRGR_MSTRST_Pos)       /*!< 0x00000002 */

+#define HRTIM_BMTRGR_MSTRST           HRTIM_BMTRGR_MSTRST_Msk                  /*!<  Master reset */

+#define HRTIM_BMTRGR_MSTREP_Pos       (2U)

+#define HRTIM_BMTRGR_MSTREP_Msk       (0x1UL << HRTIM_BMTRGR_MSTREP_Pos)       /*!< 0x00000004 */

+#define HRTIM_BMTRGR_MSTREP           HRTIM_BMTRGR_MSTREP_Msk                  /*!<  Master repetition */

+#define HRTIM_BMTRGR_MSTCMP1_Pos      (3U)

+#define HRTIM_BMTRGR_MSTCMP1_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos)      /*!< 0x00000008 */

+#define HRTIM_BMTRGR_MSTCMP1          HRTIM_BMTRGR_MSTCMP1_Msk                 /*!<  Master compare 1 */

+#define HRTIM_BMTRGR_MSTCMP2_Pos      (4U)

+#define HRTIM_BMTRGR_MSTCMP2_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos)      /*!< 0x00000010 */

+#define HRTIM_BMTRGR_MSTCMP2          HRTIM_BMTRGR_MSTCMP2_Msk                 /*!< Master compare 2  */

+#define HRTIM_BMTRGR_MSTCMP3_Pos      (5U)

+#define HRTIM_BMTRGR_MSTCMP3_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos)      /*!< 0x00000020 */

+#define HRTIM_BMTRGR_MSTCMP3          HRTIM_BMTRGR_MSTCMP3_Msk                 /*!< Master compare 3 */

+#define HRTIM_BMTRGR_MSTCMP4_Pos      (6U)

+#define HRTIM_BMTRGR_MSTCMP4_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos)      /*!< 0x00000040 */

+#define HRTIM_BMTRGR_MSTCMP4          HRTIM_BMTRGR_MSTCMP4_Msk                 /*!< Master compare 4 */

+#define HRTIM_BMTRGR_TARST_Pos        (7U)

+#define HRTIM_BMTRGR_TARST_Msk        (0x1UL << HRTIM_BMTRGR_TARST_Pos)        /*!< 0x00000080 */

+#define HRTIM_BMTRGR_TARST            HRTIM_BMTRGR_TARST_Msk                   /*!< Timer A reset  */

+#define HRTIM_BMTRGR_TAREP_Pos        (8U)

+#define HRTIM_BMTRGR_TAREP_Msk        (0x1UL << HRTIM_BMTRGR_TAREP_Pos)        /*!< 0x00000100 */

+#define HRTIM_BMTRGR_TAREP            HRTIM_BMTRGR_TAREP_Msk                   /*!< Timer A repetition  */

+#define HRTIM_BMTRGR_TACMP1_Pos       (9U)

+#define HRTIM_BMTRGR_TACMP1_Msk       (0x1UL << HRTIM_BMTRGR_TACMP1_Pos)       /*!< 0x00000200 */

+#define HRTIM_BMTRGR_TACMP1           HRTIM_BMTRGR_TACMP1_Msk                  /*!< Timer A compare 1  */

+#define HRTIM_BMTRGR_TACMP2_Pos       (10U)

+#define HRTIM_BMTRGR_TACMP2_Msk       (0x1UL << HRTIM_BMTRGR_TACMP2_Pos)       /*!< 0x00000400 */

+#define HRTIM_BMTRGR_TACMP2           HRTIM_BMTRGR_TACMP2_Msk                  /*!< Timer A compare 2  */

+#define HRTIM_BMTRGR_TBRST_Pos        (11U)

+#define HRTIM_BMTRGR_TBRST_Msk        (0x1UL << HRTIM_BMTRGR_TBRST_Pos)        /*!< 0x00000800 */

+#define HRTIM_BMTRGR_TBRST            HRTIM_BMTRGR_TBRST_Msk                   /*!< Timer B reset  */

+#define HRTIM_BMTRGR_TBREP_Pos        (12U)

+#define HRTIM_BMTRGR_TBREP_Msk        (0x1UL << HRTIM_BMTRGR_TBREP_Pos)        /*!< 0x00001000 */

+#define HRTIM_BMTRGR_TBREP            HRTIM_BMTRGR_TBREP_Msk                   /*!< Timer B repetition  */

+#define HRTIM_BMTRGR_TBCMP1_Pos       (13U)

+#define HRTIM_BMTRGR_TBCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos)       /*!< 0x00002000 */

+#define HRTIM_BMTRGR_TBCMP1           HRTIM_BMTRGR_TBCMP1_Msk                  /*!< Timer B compare 1 */

+#define HRTIM_BMTRGR_TBCMP2_Pos       (14U)

+#define HRTIM_BMTRGR_TBCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos)       /*!< 0x00004000 */

+#define HRTIM_BMTRGR_TBCMP2           HRTIM_BMTRGR_TBCMP2_Msk                  /*!< Timer B compare 2 */

+#define HRTIM_BMTRGR_TCRST_Pos        (15U)

+#define HRTIM_BMTRGR_TCRST_Msk        (0x1UL << HRTIM_BMTRGR_TCRST_Pos)        /*!< 0x00008000 */

+#define HRTIM_BMTRGR_TCRST            HRTIM_BMTRGR_TCRST_Msk                   /*!< Timer C reset  */

+#define HRTIM_BMTRGR_TCREP_Pos        (16U)

+#define HRTIM_BMTRGR_TCREP_Msk        (0x1UL << HRTIM_BMTRGR_TCREP_Pos)        /*!< 0x00010000 */

+#define HRTIM_BMTRGR_TCREP            HRTIM_BMTRGR_TCREP_Msk                   /*!< Timer C repetition */

+#define HRTIM_BMTRGR_TCCMP1_Pos       (17U)

+#define HRTIM_BMTRGR_TCCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos)       /*!< 0x00020000 */

+#define HRTIM_BMTRGR_TCCMP1           HRTIM_BMTRGR_TCCMP1_Msk                  /*!< Timer C compare 1 */

+#define HRTIM_BMTRGR_TCCMP2_Pos       (18U)

+#define HRTIM_BMTRGR_TCCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP2_Pos)       /*!< 0x00040000 */

+#define HRTIM_BMTRGR_TCCMP2           HRTIM_BMTRGR_TCCMP2_Msk                  /*!< Timer C compare 2 */

+#define HRTIM_BMTRGR_TDRST_Pos        (19U)

+#define HRTIM_BMTRGR_TDRST_Msk        (0x1UL << HRTIM_BMTRGR_TDRST_Pos)        /*!< 0x00080000 */

+#define HRTIM_BMTRGR_TDRST            HRTIM_BMTRGR_TDRST_Msk                   /*!< Timer D reset  */

+#define HRTIM_BMTRGR_TDREP_Pos        (20U)

+#define HRTIM_BMTRGR_TDREP_Msk        (0x1UL << HRTIM_BMTRGR_TDREP_Pos)        /*!< 0x00100000 */

+#define HRTIM_BMTRGR_TDREP            HRTIM_BMTRGR_TDREP_Msk                   /*!< Timer D repetition  */

+#define HRTIM_BMTRGR_TDCMP1_Pos       (21U)

+#define HRTIM_BMTRGR_TDCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP1_Pos)       /*!< 0x00200000 */

+#define HRTIM_BMTRGR_TDCMP1           HRTIM_BMTRGR_TDCMP1_Msk                  /*!< Timer D compare 1 */

+#define HRTIM_BMTRGR_TDCMP2_Pos       (22U)

+#define HRTIM_BMTRGR_TDCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos)       /*!< 0x00400000 */

+#define HRTIM_BMTRGR_TDCMP2           HRTIM_BMTRGR_TDCMP2_Msk                  /*!< Timer D compare 2 */

+#define HRTIM_BMTRGR_TERST_Pos        (23U)

+#define HRTIM_BMTRGR_TERST_Msk        (0x1UL << HRTIM_BMTRGR_TERST_Pos)        /*!< 0x00800000 */

+#define HRTIM_BMTRGR_TERST            HRTIM_BMTRGR_TERST_Msk                   /*!< Timer E reset  */

+#define HRTIM_BMTRGR_TEREP_Pos        (24U)

+#define HRTIM_BMTRGR_TEREP_Msk        (0x1UL << HRTIM_BMTRGR_TEREP_Pos)        /*!< 0x01000000 */

+#define HRTIM_BMTRGR_TEREP            HRTIM_BMTRGR_TEREP_Msk                   /*!< Timer E repetition  */

+#define HRTIM_BMTRGR_TECMP1_Pos       (25U)

+#define HRTIM_BMTRGR_TECMP1_Msk       (0x1UL << HRTIM_BMTRGR_TECMP1_Pos)       /*!< 0x02000000 */

+#define HRTIM_BMTRGR_TECMP1           HRTIM_BMTRGR_TECMP1_Msk                  /*!< Timer E compare 1 */

+#define HRTIM_BMTRGR_TECMP2_Pos       (26U)

+#define HRTIM_BMTRGR_TECMP2_Msk       (0x1UL << HRTIM_BMTRGR_TECMP2_Pos)       /*!< 0x04000000 */

+#define HRTIM_BMTRGR_TECMP2           HRTIM_BMTRGR_TECMP2_Msk                  /*!< Timer E compare 2 */

+#define HRTIM_BMTRGR_TAEEV7_Pos       (27U)

+#define HRTIM_BMTRGR_TAEEV7_Msk       (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos)       /*!< 0x08000000 */

+#define HRTIM_BMTRGR_TAEEV7           HRTIM_BMTRGR_TAEEV7_Msk                  /*!< Timer A period following External Event7  */

+#define HRTIM_BMTRGR_TDEEV8_Pos       (28U)

+#define HRTIM_BMTRGR_TDEEV8_Msk       (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos)       /*!< 0x10000000 */

+#define HRTIM_BMTRGR_TDEEV8           HRTIM_BMTRGR_TDEEV8_Msk                  /*!< Timer D period following External Event8  */

+#define HRTIM_BMTRGR_EEV7_Pos         (29U)

+#define HRTIM_BMTRGR_EEV7_Msk         (0x1UL << HRTIM_BMTRGR_EEV7_Pos)         /*!< 0x20000000 */

+#define HRTIM_BMTRGR_EEV7             HRTIM_BMTRGR_EEV7_Msk                    /*!< External Event 7 */

+#define HRTIM_BMTRGR_EEV8_Pos         (30U)

+#define HRTIM_BMTRGR_EEV8_Msk         (0x1UL << HRTIM_BMTRGR_EEV8_Pos)         /*!< 0x40000000 */

+#define HRTIM_BMTRGR_EEV8             HRTIM_BMTRGR_EEV8_Msk                    /*!< External Event 8 */

+#define HRTIM_BMTRGR_OCHPEV_Pos       (31U)

+#define HRTIM_BMTRGR_OCHPEV_Msk       (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos)       /*!< 0x80000000 */

+#define HRTIM_BMTRGR_OCHPEV           HRTIM_BMTRGR_OCHPEV_Msk                  /*!< on-chip Event */

+

+/*******************  Bit definition for HRTIM_BMCMPR register  ***************/

+#define HRTIM_BMCMPR_BMCMPR_Pos       (0U)

+#define HRTIM_BMCMPR_BMCMPR_Msk       (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_BMCMPR_BMCMPR           HRTIM_BMCMPR_BMCMPR_Msk                  /*!<!<Burst Compare Value */

+

+/*******************  Bit definition for HRTIM_BMPER register  ****************/

+#define HRTIM_BMPER_BMPER_Pos         (0U)

+#define HRTIM_BMPER_BMPER_Msk         (0xFFFFUL << HRTIM_BMPER_BMPER_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_BMPER_BMPER             HRTIM_BMPER_BMPER_Msk                    /*!<!<Burst period Value */

+

+/*******************  Bit definition for HRTIM_EECR1 register  ****************/

+#define HRTIM_EECR1_EE1SRC_Pos        (0U)

+#define HRTIM_EECR1_EE1SRC_Msk        (0x3UL << HRTIM_EECR1_EE1SRC_Pos)        /*!< 0x00000003 */

+#define HRTIM_EECR1_EE1SRC            HRTIM_EECR1_EE1SRC_Msk                   /*!< External event 1 source */

+#define HRTIM_EECR1_EE1SRC_0          (0x1UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000001 */

+#define HRTIM_EECR1_EE1SRC_1          (0x2UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000002 */

+#define HRTIM_EECR1_EE1POL_Pos        (2U)

+#define HRTIM_EECR1_EE1POL_Msk        (0x1UL << HRTIM_EECR1_EE1POL_Pos)        /*!< 0x00000004 */

+#define HRTIM_EECR1_EE1POL            HRTIM_EECR1_EE1POL_Msk                   /*!< External event 1 Polarity */

+#define HRTIM_EECR1_EE1SNS_Pos        (3U)

+#define HRTIM_EECR1_EE1SNS_Msk        (0x3UL << HRTIM_EECR1_EE1SNS_Pos)        /*!< 0x00000018 */

+#define HRTIM_EECR1_EE1SNS            HRTIM_EECR1_EE1SNS_Msk                   /*!< External event 1 sensitivity */

+#define HRTIM_EECR1_EE1SNS_0          (0x1UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000008 */

+#define HRTIM_EECR1_EE1SNS_1          (0x2UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000010 */

+#define HRTIM_EECR1_EE1FAST_Pos       (5U)

+#define HRTIM_EECR1_EE1FAST_Msk       (0x1UL << HRTIM_EECR1_EE1FAST_Pos)       /*!< 0x00000020 */

+#define HRTIM_EECR1_EE1FAST           HRTIM_EECR1_EE1FAST_Msk                  /*!< External event 1 Fast mode */

+

+#define HRTIM_EECR1_EE2SRC_Pos        (6U)

+#define HRTIM_EECR1_EE2SRC_Msk        (0x3UL << HRTIM_EECR1_EE2SRC_Pos)        /*!< 0x000000C0 */

+#define HRTIM_EECR1_EE2SRC            HRTIM_EECR1_EE2SRC_Msk                   /*!< External event 2 source */

+#define HRTIM_EECR1_EE2SRC_0          (0x1UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000040 */

+#define HRTIM_EECR1_EE2SRC_1          (0x2UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000080 */

+#define HRTIM_EECR1_EE2POL_Pos        (8U)

+#define HRTIM_EECR1_EE2POL_Msk        (0x1UL << HRTIM_EECR1_EE2POL_Pos)        /*!< 0x00000100 */

+#define HRTIM_EECR1_EE2POL            HRTIM_EECR1_EE2POL_Msk                   /*!< External event 2 Polarity */

+#define HRTIM_EECR1_EE2SNS_Pos        (9U)

+#define HRTIM_EECR1_EE2SNS_Msk        (0x3UL << HRTIM_EECR1_EE2SNS_Pos)        /*!< 0x00000600 */

+#define HRTIM_EECR1_EE2SNS            HRTIM_EECR1_EE2SNS_Msk                   /*!< External event 2 sensitivity */

+#define HRTIM_EECR1_EE2SNS_0          (0x1UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000200 */

+#define HRTIM_EECR1_EE2SNS_1          (0x2UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000400 */

+#define HRTIM_EECR1_EE2FAST_Pos       (11U)

+#define HRTIM_EECR1_EE2FAST_Msk       (0x1UL << HRTIM_EECR1_EE2FAST_Pos)       /*!< 0x00000800 */

+#define HRTIM_EECR1_EE2FAST           HRTIM_EECR1_EE2FAST_Msk                  /*!< External event 2 Fast mode */

+

+#define HRTIM_EECR1_EE3SRC_Pos        (12U)

+#define HRTIM_EECR1_EE3SRC_Msk        (0x3UL << HRTIM_EECR1_EE3SRC_Pos)        /*!< 0x00003000 */

+#define HRTIM_EECR1_EE3SRC            HRTIM_EECR1_EE3SRC_Msk                   /*!< External event 3 source */

+#define HRTIM_EECR1_EE3SRC_0          (0x1UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00001000 */

+#define HRTIM_EECR1_EE3SRC_1          (0x2UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00002000 */

+#define HRTIM_EECR1_EE3POL_Pos        (14U)

+#define HRTIM_EECR1_EE3POL_Msk        (0x1UL << HRTIM_EECR1_EE3POL_Pos)        /*!< 0x00004000 */

+#define HRTIM_EECR1_EE3POL            HRTIM_EECR1_EE3POL_Msk                   /*!< External event 3 Polarity */

+#define HRTIM_EECR1_EE3SNS_Pos        (15U)

+#define HRTIM_EECR1_EE3SNS_Msk        (0x3UL << HRTIM_EECR1_EE3SNS_Pos)        /*!< 0x00018000 */

+#define HRTIM_EECR1_EE3SNS            HRTIM_EECR1_EE3SNS_Msk                   /*!< External event 3 sensitivity */

+#define HRTIM_EECR1_EE3SNS_0          (0x1UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00008000 */

+#define HRTIM_EECR1_EE3SNS_1          (0x2UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00010000 */

+#define HRTIM_EECR1_EE3FAST_Pos       (17U)

+#define HRTIM_EECR1_EE3FAST_Msk       (0x1UL << HRTIM_EECR1_EE3FAST_Pos)       /*!< 0x00020000 */

+#define HRTIM_EECR1_EE3FAST           HRTIM_EECR1_EE3FAST_Msk                  /*!< External event 3 Fast mode */

+

+#define HRTIM_EECR1_EE4SRC_Pos        (18U)

+#define HRTIM_EECR1_EE4SRC_Msk        (0x3UL << HRTIM_EECR1_EE4SRC_Pos)        /*!< 0x000C0000 */

+#define HRTIM_EECR1_EE4SRC            HRTIM_EECR1_EE4SRC_Msk                   /*!< External event 4 source */

+#define HRTIM_EECR1_EE4SRC_0          (0x1UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00040000 */

+#define HRTIM_EECR1_EE4SRC_1          (0x2UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00080000 */

+#define HRTIM_EECR1_EE4POL_Pos        (20U)

+#define HRTIM_EECR1_EE4POL_Msk        (0x1UL << HRTIM_EECR1_EE4POL_Pos)        /*!< 0x00100000 */

+#define HRTIM_EECR1_EE4POL            HRTIM_EECR1_EE4POL_Msk                   /*!< External event 4 Polarity */

+#define HRTIM_EECR1_EE4SNS_Pos        (21U)

+#define HRTIM_EECR1_EE4SNS_Msk        (0x3UL << HRTIM_EECR1_EE4SNS_Pos)        /*!< 0x00600000 */

+#define HRTIM_EECR1_EE4SNS            HRTIM_EECR1_EE4SNS_Msk                   /*!< External event 4 sensitivity */

+#define HRTIM_EECR1_EE4SNS_0          (0x1UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00200000 */

+#define HRTIM_EECR1_EE4SNS_1          (0x2UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00400000 */

+#define HRTIM_EECR1_EE4FAST_Pos       (23U)

+#define HRTIM_EECR1_EE4FAST_Msk       (0x1UL << HRTIM_EECR1_EE4FAST_Pos)       /*!< 0x00800000 */

+#define HRTIM_EECR1_EE4FAST           HRTIM_EECR1_EE4FAST_Msk                  /*!< External event 4 Fast mode */

+

+#define HRTIM_EECR1_EE5SRC_Pos        (24U)

+#define HRTIM_EECR1_EE5SRC_Msk        (0x3UL << HRTIM_EECR1_EE5SRC_Pos)        /*!< 0x03000000 */

+#define HRTIM_EECR1_EE5SRC            HRTIM_EECR1_EE5SRC_Msk                   /*!< External event 5 source */

+#define HRTIM_EECR1_EE5SRC_0          (0x1UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x01000000 */

+#define HRTIM_EECR1_EE5SRC_1          (0x2UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x02000000 */

+#define HRTIM_EECR1_EE5POL_Pos        (26U)

+#define HRTIM_EECR1_EE5POL_Msk        (0x1UL << HRTIM_EECR1_EE5POL_Pos)        /*!< 0x04000000 */

+#define HRTIM_EECR1_EE5POL            HRTIM_EECR1_EE5POL_Msk                   /*!< External event 5 Polarity */

+#define HRTIM_EECR1_EE5SNS_Pos        (27U)

+#define HRTIM_EECR1_EE5SNS_Msk        (0x3UL << HRTIM_EECR1_EE5SNS_Pos)        /*!< 0x18000000 */

+#define HRTIM_EECR1_EE5SNS            HRTIM_EECR1_EE5SNS_Msk                   /*!< External event 5 sensitivity */

+#define HRTIM_EECR1_EE5SNS_0          (0x1UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x08000000 */

+#define HRTIM_EECR1_EE5SNS_1          (0x2UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x10000000 */

+#define HRTIM_EECR1_EE5FAST_Pos       (29U)

+#define HRTIM_EECR1_EE5FAST_Msk       (0x1UL << HRTIM_EECR1_EE5FAST_Pos)       /*!< 0x20000000 */

+#define HRTIM_EECR1_EE5FAST           HRTIM_EECR1_EE5FAST_Msk                  /*!< External event 5 Fast mode */

+

+/*******************  Bit definition for HRTIM_EECR2 register  ****************/

+#define HRTIM_EECR2_EE6SRC_Pos        (0U)

+#define HRTIM_EECR2_EE6SRC_Msk        (0x3UL << HRTIM_EECR2_EE6SRC_Pos)        /*!< 0x00000003 */

+#define HRTIM_EECR2_EE6SRC            HRTIM_EECR2_EE6SRC_Msk                   /*!< External event 6 source */

+#define HRTIM_EECR2_EE6SRC_0          (0x1UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000001 */

+#define HRTIM_EECR2_EE6SRC_1          (0x2UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000002 */

+#define HRTIM_EECR2_EE6POL_Pos        (2U)

+#define HRTIM_EECR2_EE6POL_Msk        (0x1UL << HRTIM_EECR2_EE6POL_Pos)        /*!< 0x00000004 */

+#define HRTIM_EECR2_EE6POL            HRTIM_EECR2_EE6POL_Msk                   /*!< External event 6 Polarity */

+#define HRTIM_EECR2_EE6SNS_Pos        (3U)

+#define HRTIM_EECR2_EE6SNS_Msk        (0x3UL << HRTIM_EECR2_EE6SNS_Pos)        /*!< 0x00000018 */

+#define HRTIM_EECR2_EE6SNS            HRTIM_EECR2_EE6SNS_Msk                   /*!< External event 6 sensitivity */

+#define HRTIM_EECR2_EE6SNS_0          (0x1UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000008 */

+#define HRTIM_EECR2_EE6SNS_1          (0x2UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000010 */

+

+#define HRTIM_EECR2_EE7SRC_Pos        (6U)

+#define HRTIM_EECR2_EE7SRC_Msk        (0x3UL << HRTIM_EECR2_EE7SRC_Pos)        /*!< 0x000000C0 */

+#define HRTIM_EECR2_EE7SRC            HRTIM_EECR2_EE7SRC_Msk                   /*!< External event 7 source */

+#define HRTIM_EECR2_EE7SRC_0          (0x1UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000040 */

+#define HRTIM_EECR2_EE7SRC_1          (0x2UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000080 */

+#define HRTIM_EECR2_EE7POL_Pos        (8U)

+#define HRTIM_EECR2_EE7POL_Msk        (0x1UL << HRTIM_EECR2_EE7POL_Pos)        /*!< 0x00000100 */

+#define HRTIM_EECR2_EE7POL            HRTIM_EECR2_EE7POL_Msk                   /*!< External event 7 Polarity */

+#define HRTIM_EECR2_EE7SNS_Pos        (9U)

+#define HRTIM_EECR2_EE7SNS_Msk        (0x3UL << HRTIM_EECR2_EE7SNS_Pos)        /*!< 0x00000600 */

+#define HRTIM_EECR2_EE7SNS            HRTIM_EECR2_EE7SNS_Msk                   /*!< External event 7 sensitivity */

+#define HRTIM_EECR2_EE7SNS_0          (0x1UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000200 */

+#define HRTIM_EECR2_EE7SNS_1          (0x2UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000400 */

+

+#define HRTIM_EECR2_EE8SRC_Pos        (12U)

+#define HRTIM_EECR2_EE8SRC_Msk        (0x3UL << HRTIM_EECR2_EE8SRC_Pos)        /*!< 0x00003000 */

+#define HRTIM_EECR2_EE8SRC            HRTIM_EECR2_EE8SRC_Msk                   /*!< External event 8 source */

+#define HRTIM_EECR2_EE8SRC_0          (0x1UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00001000 */

+#define HRTIM_EECR2_EE8SRC_1          (0x2UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00002000 */

+#define HRTIM_EECR2_EE8POL_Pos        (14U)

+#define HRTIM_EECR2_EE8POL_Msk        (0x1UL << HRTIM_EECR2_EE8POL_Pos)        /*!< 0x00004000 */

+#define HRTIM_EECR2_EE8POL            HRTIM_EECR2_EE8POL_Msk                   /*!< External event 8 Polarity */

+#define HRTIM_EECR2_EE8SNS_Pos        (15U)

+#define HRTIM_EECR2_EE8SNS_Msk        (0x3UL << HRTIM_EECR2_EE8SNS_Pos)        /*!< 0x00018000 */

+#define HRTIM_EECR2_EE8SNS            HRTIM_EECR2_EE8SNS_Msk                   /*!< External event 8 sensitivity */

+#define HRTIM_EECR2_EE8SNS_0          (0x1UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00008000 */

+#define HRTIM_EECR2_EE8SNS_1          (0x2UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00010000 */

+

+#define HRTIM_EECR2_EE9SRC_Pos        (18U)

+#define HRTIM_EECR2_EE9SRC_Msk        (0x3UL << HRTIM_EECR2_EE9SRC_Pos)        /*!< 0x000C0000 */

+#define HRTIM_EECR2_EE9SRC            HRTIM_EECR2_EE9SRC_Msk                   /*!< External event 9 source */

+#define HRTIM_EECR2_EE9SRC_0          (0x1UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00040000 */

+#define HRTIM_EECR2_EE9SRC_1          (0x2UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00080000 */

+#define HRTIM_EECR2_EE9POL_Pos        (20U)

+#define HRTIM_EECR2_EE9POL_Msk        (0x1UL << HRTIM_EECR2_EE9POL_Pos)        /*!< 0x00100000 */

+#define HRTIM_EECR2_EE9POL            HRTIM_EECR2_EE9POL_Msk                   /*!< External event 9 Polarity */

+#define HRTIM_EECR2_EE9SNS_Pos        (21U)

+#define HRTIM_EECR2_EE9SNS_Msk        (0x3UL << HRTIM_EECR2_EE9SNS_Pos)        /*!< 0x00600000 */

+#define HRTIM_EECR2_EE9SNS            HRTIM_EECR2_EE9SNS_Msk                   /*!< External event 9 sensitivity */

+#define HRTIM_EECR2_EE9SNS_0          (0x1UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00200000 */

+#define HRTIM_EECR2_EE9SNS_1          (0x2UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00400000 */

+

+#define HRTIM_EECR2_EE10SRC_Pos       (24U)

+#define HRTIM_EECR2_EE10SRC_Msk       (0x3UL << HRTIM_EECR2_EE10SRC_Pos)       /*!< 0x03000000 */

+#define HRTIM_EECR2_EE10SRC           HRTIM_EECR2_EE10SRC_Msk                  /*!< External event 10 source */

+#define HRTIM_EECR2_EE10SRC_0         (0x1UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x01000000 */

+#define HRTIM_EECR2_EE10SRC_1         (0x2UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x02000000 */

+#define HRTIM_EECR2_EE10POL_Pos       (26U)

+#define HRTIM_EECR2_EE10POL_Msk       (0x1UL << HRTIM_EECR2_EE10POL_Pos)       /*!< 0x04000000 */

+#define HRTIM_EECR2_EE10POL           HRTIM_EECR2_EE10POL_Msk                  /*!< External event 10 Polarity */

+#define HRTIM_EECR2_EE10SNS_Pos       (27U)

+#define HRTIM_EECR2_EE10SNS_Msk       (0x3UL << HRTIM_EECR2_EE10SNS_Pos)       /*!< 0x18000000 */

+#define HRTIM_EECR2_EE10SNS           HRTIM_EECR2_EE10SNS_Msk                  /*!< External event 10 sensitivity */

+#define HRTIM_EECR2_EE10SNS_0         (0x1UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x08000000 */

+#define HRTIM_EECR2_EE10SNS_1         (0x2UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x10000000 */

+

+/*******************  Bit definition for HRTIM_EECR3 register  ****************/

+#define HRTIM_EECR3_EE6F_Pos          (0U)

+#define HRTIM_EECR3_EE6F_Msk          (0xFUL << HRTIM_EECR3_EE6F_Pos)          /*!< 0x0000000F */

+#define HRTIM_EECR3_EE6F              HRTIM_EECR3_EE6F_Msk                     /*!< External event 6 filter */

+#define HRTIM_EECR3_EE6F_0            (0x1UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000001 */

+#define HRTIM_EECR3_EE6F_1            (0x2UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000002 */

+#define HRTIM_EECR3_EE6F_2            (0x4UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000004 */

+#define HRTIM_EECR3_EE6F_3            (0x8UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000008 */

+#define HRTIM_EECR3_EE7F_Pos          (6U)

+#define HRTIM_EECR3_EE7F_Msk          (0xFUL << HRTIM_EECR3_EE7F_Pos)          /*!< 0x000003C0 */

+#define HRTIM_EECR3_EE7F              HRTIM_EECR3_EE7F_Msk                     /*!< External event 7 filter */

+#define HRTIM_EECR3_EE7F_0            (0x1UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000040 */

+#define HRTIM_EECR3_EE7F_1            (0x2UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000080 */

+#define HRTIM_EECR3_EE7F_2            (0x4UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000100 */

+#define HRTIM_EECR3_EE7F_3            (0x8UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000200 */

+#define HRTIM_EECR3_EE8F_Pos          (12U)

+#define HRTIM_EECR3_EE8F_Msk          (0xFUL << HRTIM_EECR3_EE8F_Pos)          /*!< 0x0000F000 */

+#define HRTIM_EECR3_EE8F              HRTIM_EECR3_EE8F_Msk                     /*!< External event 8 filter */

+#define HRTIM_EECR3_EE8F_0            (0x1UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00001000 */

+#define HRTIM_EECR3_EE8F_1            (0x2UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00002000 */

+#define HRTIM_EECR3_EE8F_2            (0x4UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00004000 */

+#define HRTIM_EECR3_EE8F_3            (0x8UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00008000 */

+#define HRTIM_EECR3_EE9F_Pos          (18U)

+#define HRTIM_EECR3_EE9F_Msk          (0xFUL << HRTIM_EECR3_EE9F_Pos)          /*!< 0x003C0000 */

+#define HRTIM_EECR3_EE9F              HRTIM_EECR3_EE9F_Msk                     /*!< External event 9 filter */

+#define HRTIM_EECR3_EE9F_0            (0x1UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00040000 */

+#define HRTIM_EECR3_EE9F_1            (0x2UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00080000 */

+#define HRTIM_EECR3_EE9F_2            (0x4UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00100000 */

+#define HRTIM_EECR3_EE9F_3            (0x8UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00200000 */

+#define HRTIM_EECR3_EE10F_Pos         (24U)

+#define HRTIM_EECR3_EE10F_Msk         (0xFUL << HRTIM_EECR3_EE10F_Pos)         /*!< 0x0F000000 */

+#define HRTIM_EECR3_EE10F             HRTIM_EECR3_EE10F_Msk                    /*!< External event 10 filter */

+#define HRTIM_EECR3_EE10F_0           (0x1UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x01000000 */

+#define HRTIM_EECR3_EE10F_1           (0x2UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x02000000 */

+#define HRTIM_EECR3_EE10F_2           (0x4UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x04000000 */

+#define HRTIM_EECR3_EE10F_3           (0x8UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x08000000 */

+#define HRTIM_EECR3_EEVSD_Pos         (30U)

+#define HRTIM_EECR3_EEVSD_Msk         (0x3UL << HRTIM_EECR3_EEVSD_Pos)         /*!< 0xC0000000 */

+#define HRTIM_EECR3_EEVSD             HRTIM_EECR3_EEVSD_Msk                    /*!< External event sampling clock division */

+#define HRTIM_EECR3_EEVSD_0           (0x1UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x40000000 */

+#define HRTIM_EECR3_EEVSD_1           (0x2UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x80000000 */

+

+/*******************  Bit definition for HRTIM_ADC1R register  ****************/

+#define HRTIM_ADC1R_AD1MC1_Pos        (0U)

+#define HRTIM_ADC1R_AD1MC1_Msk        (0x1UL << HRTIM_ADC1R_AD1MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC1R_AD1MC1            HRTIM_ADC1R_AD1MC1_Msk                   /*!< ADC Trigger 1 on master compare 1 */

+#define HRTIM_ADC1R_AD1MC2_Pos        (1U)

+#define HRTIM_ADC1R_AD1MC2_Msk        (0x1UL << HRTIM_ADC1R_AD1MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC1R_AD1MC2            HRTIM_ADC1R_AD1MC2_Msk                   /*!< ADC Trigger 1 on master compare 2 */

+#define HRTIM_ADC1R_AD1MC3_Pos        (2U)

+#define HRTIM_ADC1R_AD1MC3_Msk        (0x1UL << HRTIM_ADC1R_AD1MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC1R_AD1MC3            HRTIM_ADC1R_AD1MC3_Msk                   /*!< ADC Trigger 1 on master compare 3 */

+#define HRTIM_ADC1R_AD1MC4_Pos        (3U)

+#define HRTIM_ADC1R_AD1MC4_Msk        (0x1UL << HRTIM_ADC1R_AD1MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC1R_AD1MC4            HRTIM_ADC1R_AD1MC4_Msk                   /*!< ADC Trigger 1 on master compare 4 */

+#define HRTIM_ADC1R_AD1MPER_Pos       (4U)

+#define HRTIM_ADC1R_AD1MPER_Msk       (0x1UL << HRTIM_ADC1R_AD1MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC1R_AD1MPER           HRTIM_ADC1R_AD1MPER_Msk                  /*!< ADC Trigger 1 on master period */

+#define HRTIM_ADC1R_AD1EEV1_Pos       (5U)

+#define HRTIM_ADC1R_AD1EEV1_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC1R_AD1EEV1           HRTIM_ADC1R_AD1EEV1_Msk                  /*!< ADC Trigger 1 on external event 1 */

+#define HRTIM_ADC1R_AD1EEV2_Pos       (6U)

+#define HRTIM_ADC1R_AD1EEV2_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC1R_AD1EEV2           HRTIM_ADC1R_AD1EEV2_Msk                  /*!< ADC Trigger 1 on external event 2 */

+#define HRTIM_ADC1R_AD1EEV3_Pos       (7U)

+#define HRTIM_ADC1R_AD1EEV3_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC1R_AD1EEV3           HRTIM_ADC1R_AD1EEV3_Msk                  /*!< ADC Trigger 1 on external event 3 */

+#define HRTIM_ADC1R_AD1EEV4_Pos       (8U)

+#define HRTIM_ADC1R_AD1EEV4_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC1R_AD1EEV4           HRTIM_ADC1R_AD1EEV4_Msk                  /*!< ADC Trigger 1 on external event 4 */

+#define HRTIM_ADC1R_AD1EEV5_Pos       (9U)

+#define HRTIM_ADC1R_AD1EEV5_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos)       /*!< 0x00000200 */

+#define HRTIM_ADC1R_AD1EEV5           HRTIM_ADC1R_AD1EEV5_Msk                  /*!< ADC Trigger 1 on external event 5 */

+#define HRTIM_ADC1R_AD1TAC2_Pos       (10U)

+#define HRTIM_ADC1R_AD1TAC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC1R_AD1TAC2           HRTIM_ADC1R_AD1TAC2_Msk                  /*!< ADC Trigger 1 on Timer A compare 2 */

+#define HRTIM_ADC1R_AD1TAC3_Pos       (11U)

+#define HRTIM_ADC1R_AD1TAC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC1R_AD1TAC3           HRTIM_ADC1R_AD1TAC3_Msk                  /*!< ADC Trigger 1 on Timer A compare 3 */

+#define HRTIM_ADC1R_AD1TAC4_Pos       (12U)

+#define HRTIM_ADC1R_AD1TAC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC1R_AD1TAC4           HRTIM_ADC1R_AD1TAC4_Msk                  /*!< ADC Trigger 1 on Timer A compare 4 */

+#define HRTIM_ADC1R_AD1TAPER_Pos      (13U)

+#define HRTIM_ADC1R_AD1TAPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC1R_AD1TAPER          HRTIM_ADC1R_AD1TAPER_Msk                 /*!< ADC Trigger 1 on Timer A period */

+#define HRTIM_ADC1R_AD1TARST_Pos      (14U)

+#define HRTIM_ADC1R_AD1TARST_Msk      (0x1UL << HRTIM_ADC1R_AD1TARST_Pos)      /*!< 0x00004000 */

+#define HRTIM_ADC1R_AD1TARST          HRTIM_ADC1R_AD1TARST_Msk                 /*!< ADC Trigger 1 on Timer A reset */

+#define HRTIM_ADC1R_AD1TBC2_Pos       (15U)

+#define HRTIM_ADC1R_AD1TBC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC2_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC1R_AD1TBC2           HRTIM_ADC1R_AD1TBC2_Msk                  /*!< ADC Trigger 1 on Timer B compare 2 */

+#define HRTIM_ADC1R_AD1TBC3_Pos       (16U)

+#define HRTIM_ADC1R_AD1TBC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC1R_AD1TBC3           HRTIM_ADC1R_AD1TBC3_Msk                  /*!< ADC Trigger 1 on Timer B compare 3 */

+#define HRTIM_ADC1R_AD1TBC4_Pos       (17U)

+#define HRTIM_ADC1R_AD1TBC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos)       /*!< 0x00020000 */

+#define HRTIM_ADC1R_AD1TBC4           HRTIM_ADC1R_AD1TBC4_Msk                  /*!< ADC Trigger 1 on Timer B compare 4 */

+#define HRTIM_ADC1R_AD1TBPER_Pos      (18U)

+#define HRTIM_ADC1R_AD1TBPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos)      /*!< 0x00040000 */

+#define HRTIM_ADC1R_AD1TBPER          HRTIM_ADC1R_AD1TBPER_Msk                 /*!< ADC Trigger 1 on Timer B period */

+#define HRTIM_ADC1R_AD1TBRST_Pos      (19U)

+#define HRTIM_ADC1R_AD1TBRST_Msk      (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos)      /*!< 0x00080000 */

+#define HRTIM_ADC1R_AD1TBRST          HRTIM_ADC1R_AD1TBRST_Msk                 /*!< ADC Trigger 1 on Timer B reset */

+#define HRTIM_ADC1R_AD1TCC2_Pos       (20U)

+#define HRTIM_ADC1R_AD1TCC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC2_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC1R_AD1TCC2           HRTIM_ADC1R_AD1TCC2_Msk                  /*!< ADC Trigger 1 on Timer C compare 2 */

+#define HRTIM_ADC1R_AD1TCC3_Pos       (21U)

+#define HRTIM_ADC1R_AD1TCC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos)       /*!< 0x00200000 */

+#define HRTIM_ADC1R_AD1TCC3           HRTIM_ADC1R_AD1TCC3_Msk                  /*!< ADC Trigger 1 on Timer C compare 3 */

+#define HRTIM_ADC1R_AD1TCC4_Pos       (22U)

+#define HRTIM_ADC1R_AD1TCC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos)       /*!< 0x00400000 */

+#define HRTIM_ADC1R_AD1TCC4           HRTIM_ADC1R_AD1TCC4_Msk                  /*!< ADC Trigger 1 on Timer C compare 4 */

+#define HRTIM_ADC1R_AD1TCPER_Pos      (23U)

+#define HRTIM_ADC1R_AD1TCPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos)      /*!< 0x00800000 */

+#define HRTIM_ADC1R_AD1TCPER          HRTIM_ADC1R_AD1TCPER_Msk                 /*!< ADC Trigger 1 on Timer C period */

+#define HRTIM_ADC1R_AD1TDC2_Pos       (24U)

+#define HRTIM_ADC1R_AD1TDC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC2_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC1R_AD1TDC2           HRTIM_ADC1R_AD1TDC2_Msk                  /*!< ADC Trigger 1 on Timer D compare 2 */

+#define HRTIM_ADC1R_AD1TDC3_Pos       (25U)

+#define HRTIM_ADC1R_AD1TDC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC1R_AD1TDC3           HRTIM_ADC1R_AD1TDC3_Msk                  /*!< ADC Trigger 1 on Timer D compare 3 */

+#define HRTIM_ADC1R_AD1TDC4_Pos       (26U)

+#define HRTIM_ADC1R_AD1TDC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos)       /*!< 0x04000000 */

+#define HRTIM_ADC1R_AD1TDC4           HRTIM_ADC1R_AD1TDC4_Msk                  /*!< ADC Trigger 1 on Timer D compare 4 */

+#define HRTIM_ADC1R_AD1TDPER_Pos      (27U)

+#define HRTIM_ADC1R_AD1TDPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC1R_AD1TDPER          HRTIM_ADC1R_AD1TDPER_Msk                 /*!< ADC Trigger 1 on Timer D period */

+#define HRTIM_ADC1R_AD1TEC2_Pos       (28U)

+#define HRTIM_ADC1R_AD1TEC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC1R_AD1TEC2           HRTIM_ADC1R_AD1TEC2_Msk                  /*!< ADC Trigger 1 on Timer E compare 2 */

+#define HRTIM_ADC1R_AD1TEC3_Pos       (29U)

+#define HRTIM_ADC1R_AD1TEC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC1R_AD1TEC3           HRTIM_ADC1R_AD1TEC3_Msk                  /*!< ADC Trigger 1 on Timer E compare 3 */

+#define HRTIM_ADC1R_AD1TEC4_Pos       (30U)

+#define HRTIM_ADC1R_AD1TEC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC1R_AD1TEC4           HRTIM_ADC1R_AD1TEC4_Msk                  /*!< ADC Trigger 1 on Timer E compare 4 */

+#define HRTIM_ADC1R_AD1TEPER_Pos      (31U)

+#define HRTIM_ADC1R_AD1TEPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC1R_AD1TEPER          HRTIM_ADC1R_AD1TEPER_Msk                 /*!< ADC Trigger 1 on Timer E period */

+

+/*******************  Bit definition for HRTIM_ADC2R register  ****************/

+#define HRTIM_ADC2R_AD2MC1_Pos        (0U)

+#define HRTIM_ADC2R_AD2MC1_Msk        (0x1UL << HRTIM_ADC2R_AD2MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC2R_AD2MC1            HRTIM_ADC2R_AD2MC1_Msk                   /*!< ADC Trigger 2 on master compare 1 */

+#define HRTIM_ADC2R_AD2MC2_Pos        (1U)

+#define HRTIM_ADC2R_AD2MC2_Msk        (0x1UL << HRTIM_ADC2R_AD2MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC2R_AD2MC2            HRTIM_ADC2R_AD2MC2_Msk                   /*!< ADC Trigger 2 on master compare 2 */

+#define HRTIM_ADC2R_AD2MC3_Pos        (2U)

+#define HRTIM_ADC2R_AD2MC3_Msk        (0x1UL << HRTIM_ADC2R_AD2MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC2R_AD2MC3            HRTIM_ADC2R_AD2MC3_Msk                   /*!< ADC Trigger 2 on master compare 3 */

+#define HRTIM_ADC2R_AD2MC4_Pos        (3U)

+#define HRTIM_ADC2R_AD2MC4_Msk        (0x1UL << HRTIM_ADC2R_AD2MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC2R_AD2MC4            HRTIM_ADC2R_AD2MC4_Msk                   /*!< ADC Trigger 2 on master compare 4 */

+#define HRTIM_ADC2R_AD2MPER_Pos       (4U)

+#define HRTIM_ADC2R_AD2MPER_Msk       (0x1UL << HRTIM_ADC2R_AD2MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC2R_AD2MPER           HRTIM_ADC2R_AD2MPER_Msk                  /*!< ADC Trigger 2 on master period */

+#define HRTIM_ADC2R_AD2EEV6_Pos       (5U)

+#define HRTIM_ADC2R_AD2EEV6_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC2R_AD2EEV6           HRTIM_ADC2R_AD2EEV6_Msk                  /*!< ADC Trigger 2 on external event 6 */

+#define HRTIM_ADC2R_AD2EEV7_Pos       (6U)

+#define HRTIM_ADC2R_AD2EEV7_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC2R_AD2EEV7           HRTIM_ADC2R_AD2EEV7_Msk                  /*!< ADC Trigger 2 on external event 7 */

+#define HRTIM_ADC2R_AD2EEV8_Pos       (7U)

+#define HRTIM_ADC2R_AD2EEV8_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC2R_AD2EEV8           HRTIM_ADC2R_AD2EEV8_Msk                  /*!< ADC Trigger 2 on external event 8 */

+#define HRTIM_ADC2R_AD2EEV9_Pos       (8U)

+#define HRTIM_ADC2R_AD2EEV9_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC2R_AD2EEV9           HRTIM_ADC2R_AD2EEV9_Msk                  /*!< ADC Trigger 2 on external event 9 */

+#define HRTIM_ADC2R_AD2EEV10_Pos      (9U)

+#define HRTIM_ADC2R_AD2EEV10_Msk      (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos)      /*!< 0x00000200 */

+#define HRTIM_ADC2R_AD2EEV10          HRTIM_ADC2R_AD2EEV10_Msk                 /*!< ADC Trigger 2 on external event 10 */

+#define HRTIM_ADC2R_AD2TAC2_Pos       (10U)

+#define HRTIM_ADC2R_AD2TAC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC2R_AD2TAC2           HRTIM_ADC2R_AD2TAC2_Msk                  /*!< ADC Trigger 2 on Timer A compare 2 */

+#define HRTIM_ADC2R_AD2TAC3_Pos       (11U)

+#define HRTIM_ADC2R_AD2TAC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC2R_AD2TAC3           HRTIM_ADC2R_AD2TAC3_Msk                  /*!< ADC Trigger 2 on Timer A compare 3 */

+#define HRTIM_ADC2R_AD2TAC4_Pos       (12U)

+#define HRTIM_ADC2R_AD2TAC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC2R_AD2TAC4           HRTIM_ADC2R_AD2TAC4_Msk                  /*!< ADC Trigger 2 on Timer A compare 4*/

+#define HRTIM_ADC2R_AD2TAPER_Pos      (13U)

+#define HRTIM_ADC2R_AD2TAPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC2R_AD2TAPER          HRTIM_ADC2R_AD2TAPER_Msk                 /*!< ADC Trigger 2 on Timer A period */

+#define HRTIM_ADC2R_AD2TBC2_Pos       (14U)

+#define HRTIM_ADC2R_AD2TBC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos)       /*!< 0x00004000 */

+#define HRTIM_ADC2R_AD2TBC2           HRTIM_ADC2R_AD2TBC2_Msk                  /*!< ADC Trigger 2 on Timer B compare 2 */

+#define HRTIM_ADC2R_AD2TBC3_Pos       (15U)

+#define HRTIM_ADC2R_AD2TBC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC3_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC2R_AD2TBC3           HRTIM_ADC2R_AD2TBC3_Msk                  /*!< ADC Trigger 2 on Timer B compare 3 */

+#define HRTIM_ADC2R_AD2TBC4_Pos       (16U)

+#define HRTIM_ADC2R_AD2TBC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC2R_AD2TBC4           HRTIM_ADC2R_AD2TBC4_Msk                  /*!< ADC Trigger 2 on Timer B compare 4 */

+#define HRTIM_ADC2R_AD2TBPER_Pos      (17U)

+#define HRTIM_ADC2R_AD2TBPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos)      /*!< 0x00020000 */

+#define HRTIM_ADC2R_AD2TBPER          HRTIM_ADC2R_AD2TBPER_Msk                 /*!< ADC Trigger 2 on Timer B period */

+#define HRTIM_ADC2R_AD2TCC2_Pos       (18U)

+#define HRTIM_ADC2R_AD2TCC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos)       /*!< 0x00040000 */

+#define HRTIM_ADC2R_AD2TCC2           HRTIM_ADC2R_AD2TCC2_Msk                  /*!< ADC Trigger 2 on Timer C compare 2 */

+#define HRTIM_ADC2R_AD2TCC3_Pos       (19U)

+#define HRTIM_ADC2R_AD2TCC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC3_Pos)       /*!< 0x00080000 */

+#define HRTIM_ADC2R_AD2TCC3           HRTIM_ADC2R_AD2TCC3_Msk                  /*!< ADC Trigger 2 on Timer C compare 3 */

+#define HRTIM_ADC2R_AD2TCC4_Pos       (20U)

+#define HRTIM_ADC2R_AD2TCC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC2R_AD2TCC4           HRTIM_ADC2R_AD2TCC4_Msk                  /*!< ADC Trigger 2 on Timer C compare 4 */

+#define HRTIM_ADC2R_AD2TCPER_Pos      (21U)

+#define HRTIM_ADC2R_AD2TCPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos)      /*!< 0x00200000 */

+#define HRTIM_ADC2R_AD2TCPER          HRTIM_ADC2R_AD2TCPER_Msk                 /*!< ADC Trigger 2 on Timer C period */

+#define HRTIM_ADC2R_AD2TCRST_Pos      (22U)

+#define HRTIM_ADC2R_AD2TCRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos)      /*!< 0x00400000 */

+#define HRTIM_ADC2R_AD2TCRST          HRTIM_ADC2R_AD2TCRST_Msk                 /*!< ADC Trigger 2 on Timer C reset */

+#define HRTIM_ADC2R_AD2TDC2_Pos       (23U)

+#define HRTIM_ADC2R_AD2TDC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos)       /*!< 0x00800000 */

+#define HRTIM_ADC2R_AD2TDC2           HRTIM_ADC2R_AD2TDC2_Msk                  /*!< ADC Trigger 2 on Timer D compare 2 */

+#define HRTIM_ADC2R_AD2TDC3_Pos       (24U)

+#define HRTIM_ADC2R_AD2TDC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC3_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC2R_AD2TDC3           HRTIM_ADC2R_AD2TDC3_Msk                  /*!< ADC Trigger 2 on Timer D compare 3 */

+#define HRTIM_ADC2R_AD2TDC4_Pos       (25U)

+#define HRTIM_ADC2R_AD2TDC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC2R_AD2TDC4           HRTIM_ADC2R_AD2TDC4_Msk                  /*!< ADC Trigger 2 on Timer D compare 4*/

+#define HRTIM_ADC2R_AD2TDPER_Pos      (26U)

+#define HRTIM_ADC2R_AD2TDPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos)      /*!< 0x04000000 */

+#define HRTIM_ADC2R_AD2TDPER          HRTIM_ADC2R_AD2TDPER_Msk                 /*!< ADC Trigger 2 on Timer D period */

+#define HRTIM_ADC2R_AD2TDRST_Pos      (27U)

+#define HRTIM_ADC2R_AD2TDRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC2R_AD2TDRST          HRTIM_ADC2R_AD2TDRST_Msk                 /*!< ADC Trigger 2 on Timer D reset */

+#define HRTIM_ADC2R_AD2TEC2_Pos       (28U)

+#define HRTIM_ADC2R_AD2TEC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC2R_AD2TEC2           HRTIM_ADC2R_AD2TEC2_Msk                  /*!< ADC Trigger 2 on Timer E compare 2 */

+#define HRTIM_ADC2R_AD2TEC3_Pos       (29U)

+#define HRTIM_ADC2R_AD2TEC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC2R_AD2TEC3           HRTIM_ADC2R_AD2TEC3_Msk                  /*!< ADC Trigger 2 on Timer E compare 3 */

+#define HRTIM_ADC2R_AD2TEC4_Pos       (30U)

+#define HRTIM_ADC2R_AD2TEC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC2R_AD2TEC4           HRTIM_ADC2R_AD2TEC4_Msk                  /*!< ADC Trigger 2 on Timer E compare 4 */

+#define HRTIM_ADC2R_AD2TERST_Pos      (31U)

+#define HRTIM_ADC2R_AD2TERST_Msk      (0x1UL << HRTIM_ADC2R_AD2TERST_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC2R_AD2TERST          HRTIM_ADC2R_AD2TERST_Msk                 /*!< ADC Trigger 2 on Timer E reset */

+

+/*******************  Bit definition for HRTIM_ADC3R register  ****************/

+#define HRTIM_ADC3R_AD3MC1_Pos        (0U)

+#define HRTIM_ADC3R_AD3MC1_Msk        (0x1UL << HRTIM_ADC3R_AD3MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC3R_AD3MC1            HRTIM_ADC3R_AD3MC1_Msk                   /*!< ADC Trigger 3 on master compare 1 */

+#define HRTIM_ADC3R_AD3MC2_Pos        (1U)

+#define HRTIM_ADC3R_AD3MC2_Msk        (0x1UL << HRTIM_ADC3R_AD3MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC3R_AD3MC2            HRTIM_ADC3R_AD3MC2_Msk                   /*!< ADC Trigger 3 on master compare 2 */

+#define HRTIM_ADC3R_AD3MC3_Pos        (2U)

+#define HRTIM_ADC3R_AD3MC3_Msk        (0x1UL << HRTIM_ADC3R_AD3MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC3R_AD3MC3            HRTIM_ADC3R_AD3MC3_Msk                   /*!< ADC Trigger 3 on master compare 3 */

+#define HRTIM_ADC3R_AD3MC4_Pos        (3U)

+#define HRTIM_ADC3R_AD3MC4_Msk        (0x1UL << HRTIM_ADC3R_AD3MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC3R_AD3MC4            HRTIM_ADC3R_AD3MC4_Msk                   /*!< ADC Trigger 3 on master compare 4 */

+#define HRTIM_ADC3R_AD3MPER_Pos       (4U)

+#define HRTIM_ADC3R_AD3MPER_Msk       (0x1UL << HRTIM_ADC3R_AD3MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC3R_AD3MPER           HRTIM_ADC3R_AD3MPER_Msk                  /*!< ADC Trigger 3 on master period */

+#define HRTIM_ADC3R_AD3EEV1_Pos       (5U)

+#define HRTIM_ADC3R_AD3EEV1_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC3R_AD3EEV1           HRTIM_ADC3R_AD3EEV1_Msk                  /*!< ADC Trigger 3 on external event 1 */

+#define HRTIM_ADC3R_AD3EEV2_Pos       (6U)

+#define HRTIM_ADC3R_AD3EEV2_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC3R_AD3EEV2           HRTIM_ADC3R_AD3EEV2_Msk                  /*!< ADC Trigger 3 on external event 2 */

+#define HRTIM_ADC3R_AD3EEV3_Pos       (7U)

+#define HRTIM_ADC3R_AD3EEV3_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC3R_AD3EEV3           HRTIM_ADC3R_AD3EEV3_Msk                  /*!< ADC Trigger 3 on external event 3 */

+#define HRTIM_ADC3R_AD3EEV4_Pos       (8U)

+#define HRTIM_ADC3R_AD3EEV4_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC3R_AD3EEV4           HRTIM_ADC3R_AD3EEV4_Msk                  /*!< ADC Trigger 3 on external event 4 */

+#define HRTIM_ADC3R_AD3EEV5_Pos       (9U)

+#define HRTIM_ADC3R_AD3EEV5_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos)       /*!< 0x00000200 */

+#define HRTIM_ADC3R_AD3EEV5           HRTIM_ADC3R_AD3EEV5_Msk                  /*!< ADC Trigger 3 on external event 5 */

+#define HRTIM_ADC3R_AD3TAC2_Pos       (10U)

+#define HRTIM_ADC3R_AD3TAC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC3R_AD3TAC2           HRTIM_ADC3R_AD3TAC2_Msk                  /*!< ADC Trigger 3 on Timer A compare 2 */

+#define HRTIM_ADC3R_AD3TAC3_Pos       (11U)

+#define HRTIM_ADC3R_AD3TAC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC3R_AD3TAC3           HRTIM_ADC3R_AD3TAC3_Msk                  /*!< ADC Trigger 3 on Timer A compare 3 */

+#define HRTIM_ADC3R_AD3TAC4_Pos       (12U)

+#define HRTIM_ADC3R_AD3TAC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC3R_AD3TAC4           HRTIM_ADC3R_AD3TAC4_Msk                  /*!< ADC Trigger 3 on Timer A compare 4 */

+#define HRTIM_ADC3R_AD3TAPER_Pos      (13U)

+#define HRTIM_ADC3R_AD3TAPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC3R_AD3TAPER          HRTIM_ADC3R_AD3TAPER_Msk                 /*!< ADC Trigger 3 on Timer A period */

+#define HRTIM_ADC3R_AD3TARST_Pos      (14U)

+#define HRTIM_ADC3R_AD3TARST_Msk      (0x1UL << HRTIM_ADC3R_AD3TARST_Pos)      /*!< 0x00004000 */

+#define HRTIM_ADC3R_AD3TARST          HRTIM_ADC3R_AD3TARST_Msk                 /*!< ADC Trigger 3 on Timer A reset */

+#define HRTIM_ADC3R_AD3TBC2_Pos       (15U)

+#define HRTIM_ADC3R_AD3TBC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC2_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC3R_AD3TBC2           HRTIM_ADC3R_AD3TBC2_Msk                  /*!< ADC Trigger 3 on Timer B compare 2 */

+#define HRTIM_ADC3R_AD3TBC3_Pos       (16U)

+#define HRTIM_ADC3R_AD3TBC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC3R_AD3TBC3           HRTIM_ADC3R_AD3TBC3_Msk                  /*!< ADC Trigger 3 on Timer B compare 3 */

+#define HRTIM_ADC3R_AD3TBC4_Pos       (17U)

+#define HRTIM_ADC3R_AD3TBC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos)       /*!< 0x00020000 */

+#define HRTIM_ADC3R_AD3TBC4           HRTIM_ADC3R_AD3TBC4_Msk                  /*!< ADC Trigger 3 on Timer B compare 4 */

+#define HRTIM_ADC3R_AD3TBPER_Pos      (18U)

+#define HRTIM_ADC3R_AD3TBPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos)      /*!< 0x00040000 */

+#define HRTIM_ADC3R_AD3TBPER          HRTIM_ADC3R_AD3TBPER_Msk                 /*!< ADC Trigger 3 on Timer B period */

+#define HRTIM_ADC3R_AD3TBRST_Pos      (19U)

+#define HRTIM_ADC3R_AD3TBRST_Msk      (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos)      /*!< 0x00080000 */

+#define HRTIM_ADC3R_AD3TBRST          HRTIM_ADC3R_AD3TBRST_Msk                 /*!< ADC Trigger 3 on Timer B reset */

+#define HRTIM_ADC3R_AD3TCC2_Pos       (20U)

+#define HRTIM_ADC3R_AD3TCC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC2_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC3R_AD3TCC2           HRTIM_ADC3R_AD3TCC2_Msk                  /*!< ADC Trigger 3 on Timer C compare 2 */

+#define HRTIM_ADC3R_AD3TCC3_Pos       (21U)

+#define HRTIM_ADC3R_AD3TCC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos)       /*!< 0x00200000 */

+#define HRTIM_ADC3R_AD3TCC3           HRTIM_ADC3R_AD3TCC3_Msk                  /*!< ADC Trigger 3 on Timer C compare 3 */

+#define HRTIM_ADC3R_AD3TCC4_Pos       (22U)

+#define HRTIM_ADC3R_AD3TCC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos)       /*!< 0x00400000 */

+#define HRTIM_ADC3R_AD3TCC4           HRTIM_ADC3R_AD3TCC4_Msk                  /*!< ADC Trigger 3 on Timer C compare 4 */

+#define HRTIM_ADC3R_AD3TCPER_Pos      (23U)

+#define HRTIM_ADC3R_AD3TCPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos)      /*!< 0x00800000 */

+#define HRTIM_ADC3R_AD3TCPER          HRTIM_ADC3R_AD3TCPER_Msk                 /*!< ADC Trigger 3 on Timer C period */

+#define HRTIM_ADC3R_AD3TDC2_Pos       (24U)

+#define HRTIM_ADC3R_AD3TDC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC2_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC3R_AD3TDC2           HRTIM_ADC3R_AD3TDC2_Msk                  /*!< ADC Trigger 3 on Timer D compare 2 */

+#define HRTIM_ADC3R_AD3TDC3_Pos       (25U)

+#define HRTIM_ADC3R_AD3TDC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC3R_AD3TDC3           HRTIM_ADC3R_AD3TDC3_Msk                  /*!< ADC Trigger 3 on Timer D compare 3 */

+#define HRTIM_ADC3R_AD3TDC4_Pos       (26U)

+#define HRTIM_ADC3R_AD3TDC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos)       /*!< 0x04000000 */

+#define HRTIM_ADC3R_AD3TDC4           HRTIM_ADC3R_AD3TDC4_Msk                  /*!< ADC Trigger 3 on Timer D compare 4 */

+#define HRTIM_ADC3R_AD3TDPER_Pos      (27U)

+#define HRTIM_ADC3R_AD3TDPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC3R_AD3TDPER          HRTIM_ADC3R_AD3TDPER_Msk                 /*!< ADC Trigger 3 on Timer D period */

+#define HRTIM_ADC3R_AD3TEC2_Pos       (28U)

+#define HRTIM_ADC3R_AD3TEC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC3R_AD3TEC2           HRTIM_ADC3R_AD3TEC2_Msk                  /*!< ADC Trigger 3 on Timer E compare 2 */

+#define HRTIM_ADC3R_AD3TEC3_Pos       (29U)

+#define HRTIM_ADC3R_AD3TEC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC3R_AD3TEC3           HRTIM_ADC3R_AD3TEC3_Msk                  /*!< ADC Trigger 3 on Timer E compare 3 */

+#define HRTIM_ADC3R_AD3TEC4_Pos       (30U)

+#define HRTIM_ADC3R_AD3TEC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC3R_AD3TEC4           HRTIM_ADC3R_AD3TEC4_Msk                  /*!< ADC Trigger 3 on Timer E compare 4 */

+#define HRTIM_ADC3R_AD3TEPER_Pos      (31U)

+#define HRTIM_ADC3R_AD3TEPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC3R_AD3TEPER          HRTIM_ADC3R_AD3TEPER_Msk                 /*!< ADC Trigger 3 on Timer E period */

+

+/*******************  Bit definition for HRTIM_ADC4R register  ****************/

+#define HRTIM_ADC4R_AD4MC1_Pos        (0U)

+#define HRTIM_ADC4R_AD4MC1_Msk        (0x1UL << HRTIM_ADC4R_AD4MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC4R_AD4MC1            HRTIM_ADC4R_AD4MC1_Msk                   /*!< ADC Trigger 4 on master compare 1 */

+#define HRTIM_ADC4R_AD4MC2_Pos        (1U)

+#define HRTIM_ADC4R_AD4MC2_Msk        (0x1UL << HRTIM_ADC4R_AD4MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC4R_AD4MC2            HRTIM_ADC4R_AD4MC2_Msk                   /*!< ADC Trigger 4 on master compare 2 */

+#define HRTIM_ADC4R_AD4MC3_Pos        (2U)

+#define HRTIM_ADC4R_AD4MC3_Msk        (0x1UL << HRTIM_ADC4R_AD4MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC4R_AD4MC3            HRTIM_ADC4R_AD4MC3_Msk                   /*!< ADC Trigger 4 on master compare 3 */

+#define HRTIM_ADC4R_AD4MC4_Pos        (3U)

+#define HRTIM_ADC4R_AD4MC4_Msk        (0x1UL << HRTIM_ADC4R_AD4MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC4R_AD4MC4            HRTIM_ADC4R_AD4MC4_Msk                   /*!< ADC Trigger 4 on master compare 4 */

+#define HRTIM_ADC4R_AD4MPER_Pos       (4U)

+#define HRTIM_ADC4R_AD4MPER_Msk       (0x1UL << HRTIM_ADC4R_AD4MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC4R_AD4MPER           HRTIM_ADC4R_AD4MPER_Msk                  /*!< ADC Trigger 4 on master period */

+#define HRTIM_ADC4R_AD4EEV6_Pos       (5U)

+#define HRTIM_ADC4R_AD4EEV6_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC4R_AD4EEV6           HRTIM_ADC4R_AD4EEV6_Msk                  /*!< ADC Trigger 4 on external event 6 */

+#define HRTIM_ADC4R_AD4EEV7_Pos       (6U)

+#define HRTIM_ADC4R_AD4EEV7_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC4R_AD4EEV7           HRTIM_ADC4R_AD4EEV7_Msk                  /*!< ADC Trigger 4 on external event 7 */

+#define HRTIM_ADC4R_AD4EEV8_Pos       (7U)

+#define HRTIM_ADC4R_AD4EEV8_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC4R_AD4EEV8           HRTIM_ADC4R_AD4EEV8_Msk                  /*!< ADC Trigger 4 on external event 8 */

+#define HRTIM_ADC4R_AD4EEV9_Pos       (8U)

+#define HRTIM_ADC4R_AD4EEV9_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC4R_AD4EEV9           HRTIM_ADC4R_AD4EEV9_Msk                  /*!< ADC Trigger 4 on external event 9 */

+#define HRTIM_ADC4R_AD4EEV10_Pos      (9U)

+#define HRTIM_ADC4R_AD4EEV10_Msk      (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos)      /*!< 0x00000200 */

+#define HRTIM_ADC4R_AD4EEV10          HRTIM_ADC4R_AD4EEV10_Msk                 /*!< ADC Trigger 4 on external event 10 */

+#define HRTIM_ADC4R_AD4TAC2_Pos       (10U)

+#define HRTIM_ADC4R_AD4TAC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC4R_AD4TAC2           HRTIM_ADC4R_AD4TAC2_Msk                  /*!< ADC Trigger 4 on Timer A compare 2 */

+#define HRTIM_ADC4R_AD4TAC3_Pos       (11U)

+#define HRTIM_ADC4R_AD4TAC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC4R_AD4TAC3           HRTIM_ADC4R_AD4TAC3_Msk                  /*!< ADC Trigger 4 on Timer A compare 3 */

+#define HRTIM_ADC4R_AD4TAC4_Pos       (12U)

+#define HRTIM_ADC4R_AD4TAC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC4R_AD4TAC4           HRTIM_ADC4R_AD4TAC4_Msk                  /*!< ADC Trigger 4 on Timer A compare 4*/

+#define HRTIM_ADC4R_AD4TAPER_Pos      (13U)

+#define HRTIM_ADC4R_AD4TAPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC4R_AD4TAPER          HRTIM_ADC4R_AD4TAPER_Msk                 /*!< ADC Trigger 4 on Timer A period */

+#define HRTIM_ADC4R_AD4TBC2_Pos       (14U)

+#define HRTIM_ADC4R_AD4TBC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos)       /*!< 0x00004000 */

+#define HRTIM_ADC4R_AD4TBC2           HRTIM_ADC4R_AD4TBC2_Msk                  /*!< ADC Trigger 4 on Timer B compare 2 */

+#define HRTIM_ADC4R_AD4TBC3_Pos       (15U)

+#define HRTIM_ADC4R_AD4TBC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC3_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC4R_AD4TBC3           HRTIM_ADC4R_AD4TBC3_Msk                  /*!< ADC Trigger 4 on Timer B compare 3 */

+#define HRTIM_ADC4R_AD4TBC4_Pos       (16U)

+#define HRTIM_ADC4R_AD4TBC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC4R_AD4TBC4           HRTIM_ADC4R_AD4TBC4_Msk                  /*!< ADC Trigger 4 on Timer B compare 4 */

+#define HRTIM_ADC4R_AD4TBPER_Pos      (17U)

+#define HRTIM_ADC4R_AD4TBPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos)      /*!< 0x00020000 */

+#define HRTIM_ADC4R_AD4TBPER          HRTIM_ADC4R_AD4TBPER_Msk                 /*!< ADC Trigger 4 on Timer B period */

+#define HRTIM_ADC4R_AD4TCC2_Pos       (18U)

+#define HRTIM_ADC4R_AD4TCC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos)       /*!< 0x00040000 */

+#define HRTIM_ADC4R_AD4TCC2           HRTIM_ADC4R_AD4TCC2_Msk                  /*!< ADC Trigger 4 on Timer C compare 2 */

+#define HRTIM_ADC4R_AD4TCC3_Pos       (19U)

+#define HRTIM_ADC4R_AD4TCC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC3_Pos)       /*!< 0x00080000 */

+#define HRTIM_ADC4R_AD4TCC3           HRTIM_ADC4R_AD4TCC3_Msk                  /*!< ADC Trigger 4 on Timer C compare 3 */

+#define HRTIM_ADC4R_AD4TCC4_Pos       (20U)

+#define HRTIM_ADC4R_AD4TCC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC4R_AD4TCC4           HRTIM_ADC4R_AD4TCC4_Msk                  /*!< ADC Trigger 4 on Timer C compare 4 */

+#define HRTIM_ADC4R_AD4TCPER_Pos      (21U)

+#define HRTIM_ADC4R_AD4TCPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos)      /*!< 0x00200000 */

+#define HRTIM_ADC4R_AD4TCPER          HRTIM_ADC4R_AD4TCPER_Msk                 /*!< ADC Trigger 4 on Timer C period */

+#define HRTIM_ADC4R_AD4TCRST_Pos      (22U)

+#define HRTIM_ADC4R_AD4TCRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos)      /*!< 0x00400000 */

+#define HRTIM_ADC4R_AD4TCRST          HRTIM_ADC4R_AD4TCRST_Msk                 /*!< ADC Trigger 4 on Timer C reset */

+#define HRTIM_ADC4R_AD4TDC2_Pos       (23U)

+#define HRTIM_ADC4R_AD4TDC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos)       /*!< 0x00800000 */

+#define HRTIM_ADC4R_AD4TDC2           HRTIM_ADC4R_AD4TDC2_Msk                  /*!< ADC Trigger 4 on Timer D compare 2 */

+#define HRTIM_ADC4R_AD4TDC3_Pos       (24U)

+#define HRTIM_ADC4R_AD4TDC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC3_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC4R_AD4TDC3           HRTIM_ADC4R_AD4TDC3_Msk                  /*!< ADC Trigger 4 on Timer D compare 3 */

+#define HRTIM_ADC4R_AD4TDC4_Pos       (25U)

+#define HRTIM_ADC4R_AD4TDC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC4R_AD4TDC4           HRTIM_ADC4R_AD4TDC4_Msk                  /*!< ADC Trigger 4 on Timer D compare 4*/

+#define HRTIM_ADC4R_AD4TDPER_Pos      (26U)

+#define HRTIM_ADC4R_AD4TDPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos)      /*!< 0x04000000 */

+#define HRTIM_ADC4R_AD4TDPER          HRTIM_ADC4R_AD4TDPER_Msk                 /*!< ADC Trigger 4 on Timer D period */

+#define HRTIM_ADC4R_AD4TDRST_Pos      (27U)

+#define HRTIM_ADC4R_AD4TDRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC4R_AD4TDRST          HRTIM_ADC4R_AD4TDRST_Msk                 /*!< ADC Trigger 4 on Timer D reset */

+#define HRTIM_ADC4R_AD4TEC2_Pos       (28U)

+#define HRTIM_ADC4R_AD4TEC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC4R_AD4TEC2           HRTIM_ADC4R_AD4TEC2_Msk                  /*!< ADC Trigger 4 on Timer E compare 2 */

+#define HRTIM_ADC4R_AD4TEC3_Pos       (29U)

+#define HRTIM_ADC4R_AD4TEC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC4R_AD4TEC3           HRTIM_ADC4R_AD4TEC3_Msk                  /*!< ADC Trigger 4 on Timer E compare 3 */

+#define HRTIM_ADC4R_AD4TEC4_Pos       (30U)

+#define HRTIM_ADC4R_AD4TEC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC4R_AD4TEC4           HRTIM_ADC4R_AD4TEC4_Msk                  /*!< ADC Trigger 4 on Timer E compare 4 */

+#define HRTIM_ADC4R_AD4TERST_Pos      (31U)

+#define HRTIM_ADC4R_AD4TERST_Msk      (0x1UL << HRTIM_ADC4R_AD4TERST_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC4R_AD4TERST          HRTIM_ADC4R_AD4TERST_Msk                 /*!< ADC Trigger 4 on Timer E reset */

+

+/*******************  Bit definition for HRTIM_FLTINR1 register  ***************/

+#define HRTIM_FLTINR1_FLT1E_Pos       (0U)

+#define HRTIM_FLTINR1_FLT1E_Msk       (0x1UL << HRTIM_FLTINR1_FLT1E_Pos)       /*!< 0x00000001 */

+#define HRTIM_FLTINR1_FLT1E           HRTIM_FLTINR1_FLT1E_Msk                  /*!< Fault 1 enable */

+#define HRTIM_FLTINR1_FLT1P_Pos       (1U)

+#define HRTIM_FLTINR1_FLT1P_Msk       (0x1UL << HRTIM_FLTINR1_FLT1P_Pos)       /*!< 0x00000002 */

+#define HRTIM_FLTINR1_FLT1P           HRTIM_FLTINR1_FLT1P_Msk                  /*!< Fault 1 polarity */

+#define HRTIM_FLTINR1_FLT1SRC_Pos     (2U)

+#define HRTIM_FLTINR1_FLT1SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT1SRC_Pos)     /*!< 0x00000004 */

+#define HRTIM_FLTINR1_FLT1SRC         HRTIM_FLTINR1_FLT1SRC_Msk                /*!< Fault 1 source */

+#define HRTIM_FLTINR1_FLT1F_Pos       (3U)

+#define HRTIM_FLTINR1_FLT1F_Msk       (0xFUL << HRTIM_FLTINR1_FLT1F_Pos)       /*!< 0x00000078 */

+#define HRTIM_FLTINR1_FLT1F           HRTIM_FLTINR1_FLT1F_Msk                  /*!< Fault 1 filter */

+#define HRTIM_FLTINR1_FLT1F_0         (0x1UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000008 */

+#define HRTIM_FLTINR1_FLT1F_1         (0x2UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000010 */

+#define HRTIM_FLTINR1_FLT1F_2         (0x4UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000020 */

+#define HRTIM_FLTINR1_FLT1F_3         (0x8UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000040 */

+#define HRTIM_FLTINR1_FLT1LCK_Pos     (7U)

+#define HRTIM_FLTINR1_FLT1LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos)     /*!< 0x00000080 */

+#define HRTIM_FLTINR1_FLT1LCK         HRTIM_FLTINR1_FLT1LCK_Msk                /*!< Fault 1 lock */

+

+#define HRTIM_FLTINR1_FLT2E_Pos       (8U)

+#define HRTIM_FLTINR1_FLT2E_Msk       (0x1UL << HRTIM_FLTINR1_FLT2E_Pos)       /*!< 0x00000100 */

+#define HRTIM_FLTINR1_FLT2E           HRTIM_FLTINR1_FLT2E_Msk                  /*!< Fault 2 enable */

+#define HRTIM_FLTINR1_FLT2P_Pos       (9U)

+#define HRTIM_FLTINR1_FLT2P_Msk       (0x1UL << HRTIM_FLTINR1_FLT2P_Pos)       /*!< 0x00000200 */

+#define HRTIM_FLTINR1_FLT2P           HRTIM_FLTINR1_FLT2P_Msk                  /*!< Fault 2 polarity */

+#define HRTIM_FLTINR1_FLT2SRC_Pos     (10U)

+#define HRTIM_FLTINR1_FLT2SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT2SRC_Pos)     /*!< 0x00000400 */

+#define HRTIM_FLTINR1_FLT2SRC         HRTIM_FLTINR1_FLT2SRC_Msk                /*!< Fault 2 source */

+#define HRTIM_FLTINR1_FLT2F_Pos       (11U)

+#define HRTIM_FLTINR1_FLT2F_Msk       (0xFUL << HRTIM_FLTINR1_FLT2F_Pos)       /*!< 0x00007800 */

+#define HRTIM_FLTINR1_FLT2F           HRTIM_FLTINR1_FLT2F_Msk                  /*!< Fault 2 filter */

+#define HRTIM_FLTINR1_FLT2F_0         (0x1UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00000800 */

+#define HRTIM_FLTINR1_FLT2F_1         (0x2UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00001000 */

+#define HRTIM_FLTINR1_FLT2F_2         (0x4UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00002000 */

+#define HRTIM_FLTINR1_FLT2F_3         (0x8UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00004000 */

+#define HRTIM_FLTINR1_FLT2LCK_Pos     (15U)

+#define HRTIM_FLTINR1_FLT2LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos)     /*!< 0x00008000 */

+#define HRTIM_FLTINR1_FLT2LCK         HRTIM_FLTINR1_FLT2LCK_Msk                /*!< Fault 2 lock */

+

+#define HRTIM_FLTINR1_FLT3E_Pos       (16U)

+#define HRTIM_FLTINR1_FLT3E_Msk       (0x1UL << HRTIM_FLTINR1_FLT3E_Pos)       /*!< 0x00010000 */

+#define HRTIM_FLTINR1_FLT3E           HRTIM_FLTINR1_FLT3E_Msk                  /*!< Fault 3 enable */

+#define HRTIM_FLTINR1_FLT3P_Pos       (17U)

+#define HRTIM_FLTINR1_FLT3P_Msk       (0x1UL << HRTIM_FLTINR1_FLT3P_Pos)       /*!< 0x00020000 */

+#define HRTIM_FLTINR1_FLT3P           HRTIM_FLTINR1_FLT3P_Msk                  /*!< Fault 3 polarity */

+#define HRTIM_FLTINR1_FLT3SRC_Pos     (18U)

+#define HRTIM_FLTINR1_FLT3SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT3SRC_Pos)     /*!< 0x00040000 */

+#define HRTIM_FLTINR1_FLT3SRC         HRTIM_FLTINR1_FLT3SRC_Msk                /*!< Fault 3 source */

+#define HRTIM_FLTINR1_FLT3F_Pos       (19U)

+#define HRTIM_FLTINR1_FLT3F_Msk       (0xFUL << HRTIM_FLTINR1_FLT3F_Pos)       /*!< 0x00780000 */

+#define HRTIM_FLTINR1_FLT3F           HRTIM_FLTINR1_FLT3F_Msk                  /*!< Fault 3 filter */

+#define HRTIM_FLTINR1_FLT3F_0         (0x1UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00080000 */

+#define HRTIM_FLTINR1_FLT3F_1         (0x2UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00100000 */

+#define HRTIM_FLTINR1_FLT3F_2         (0x4UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00200000 */

+#define HRTIM_FLTINR1_FLT3F_3         (0x8UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00400000 */

+#define HRTIM_FLTINR1_FLT3LCK_Pos     (23U)

+#define HRTIM_FLTINR1_FLT3LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos)     /*!< 0x00800000 */

+#define HRTIM_FLTINR1_FLT3LCK         HRTIM_FLTINR1_FLT3LCK_Msk                /*!< Fault 3 lock */

+

+#define HRTIM_FLTINR1_FLT4E_Pos       (24U)

+#define HRTIM_FLTINR1_FLT4E_Msk       (0x1UL << HRTIM_FLTINR1_FLT4E_Pos)       /*!< 0x01000000 */

+#define HRTIM_FLTINR1_FLT4E           HRTIM_FLTINR1_FLT4E_Msk                  /*!< Fault 4 enable */

+#define HRTIM_FLTINR1_FLT4P_Pos       (25U)

+#define HRTIM_FLTINR1_FLT4P_Msk       (0x1UL << HRTIM_FLTINR1_FLT4P_Pos)       /*!< 0x02000000 */

+#define HRTIM_FLTINR1_FLT4P           HRTIM_FLTINR1_FLT4P_Msk                  /*!< Fault 4 polarity */

+#define HRTIM_FLTINR1_FLT4SRC_Pos     (26U)

+#define HRTIM_FLTINR1_FLT4SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT4SRC_Pos)     /*!< 0x04000000 */

+#define HRTIM_FLTINR1_FLT4SRC         HRTIM_FLTINR1_FLT4SRC_Msk                /*!< Fault 4 source */

+#define HRTIM_FLTINR1_FLT4F_Pos       (27U)

+#define HRTIM_FLTINR1_FLT4F_Msk       (0xFUL << HRTIM_FLTINR1_FLT4F_Pos)       /*!< 0x78000000 */

+#define HRTIM_FLTINR1_FLT4F           HRTIM_FLTINR1_FLT4F_Msk                  /*!< Fault 4 filter */

+#define HRTIM_FLTINR1_FLT4F_0         (0x1UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x08000000 */

+#define HRTIM_FLTINR1_FLT4F_1         (0x2UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x10000000 */

+#define HRTIM_FLTINR1_FLT4F_2         (0x4UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x20000000 */

+#define HRTIM_FLTINR1_FLT4F_3         (0x8UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x40000000 */

+#define HRTIM_FLTINR1_FLT4LCK_Pos     (31U)

+#define HRTIM_FLTINR1_FLT4LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos)     /*!< 0x80000000 */

+#define HRTIM_FLTINR1_FLT4LCK         HRTIM_FLTINR1_FLT4LCK_Msk                /*!< Fault 4 lock */

+

+/*******************  Bit definition for HRTIM_FLTINR2 register  ***************/

+#define HRTIM_FLTINR2_FLT5E_Pos       (0U)

+#define HRTIM_FLTINR2_FLT5E_Msk       (0x1UL << HRTIM_FLTINR2_FLT5E_Pos)       /*!< 0x00000001 */

+#define HRTIM_FLTINR2_FLT5E           HRTIM_FLTINR2_FLT5E_Msk                  /*!< Fault 5 enable */

+#define HRTIM_FLTINR2_FLT5P_Pos       (1U)

+#define HRTIM_FLTINR2_FLT5P_Msk       (0x1UL << HRTIM_FLTINR2_FLT5P_Pos)       /*!< 0x00000002 */

+#define HRTIM_FLTINR2_FLT5P           HRTIM_FLTINR2_FLT5P_Msk                  /*!< Fault 5 polarity */

+#define HRTIM_FLTINR2_FLT5SRC_Pos     (2U)

+#define HRTIM_FLTINR2_FLT5SRC_Msk     (0x1UL << HRTIM_FLTINR2_FLT5SRC_Pos)     /*!< 0x00000004 */

+#define HRTIM_FLTINR2_FLT5SRC         HRTIM_FLTINR2_FLT5SRC_Msk                /*!< Fault 5 source */

+#define HRTIM_FLTINR2_FLT5F_Pos       (3U)

+#define HRTIM_FLTINR2_FLT5F_Msk       (0xFUL << HRTIM_FLTINR2_FLT5F_Pos)       /*!< 0x00000078 */

+#define HRTIM_FLTINR2_FLT5F           HRTIM_FLTINR2_FLT5F_Msk                  /*!< Fault 5 filter */

+#define HRTIM_FLTINR2_FLT5F_0         (0x1UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000008 */

+#define HRTIM_FLTINR2_FLT5F_1         (0x2UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000010 */

+#define HRTIM_FLTINR2_FLT5F_2         (0x4UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000020 */

+#define HRTIM_FLTINR2_FLT5F_3         (0x8UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000040 */

+#define HRTIM_FLTINR2_FLT5LCK_Pos     (7U)

+#define HRTIM_FLTINR2_FLT5LCK_Msk     (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos)     /*!< 0x00000080 */

+#define HRTIM_FLTINR2_FLT5LCK         HRTIM_FLTINR2_FLT5LCK_Msk                /*!< Fault 5 lock */

+#define HRTIM_FLTINR2_FLTSD_Pos       (24U)

+#define HRTIM_FLTINR2_FLTSD_Msk       (0x3UL << HRTIM_FLTINR2_FLTSD_Pos)       /*!< 0x03000000 */

+#define HRTIM_FLTINR2_FLTSD           HRTIM_FLTINR2_FLTSD_Msk                  /*!< Fault sampling clock division */

+#define HRTIM_FLTINR2_FLTSD_0         (0x1UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x01000000 */

+#define HRTIM_FLTINR2_FLTSD_1         (0x2UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x02000000 */

+

+/*******************  Bit definition for HRTIM_BDMUPR register  ***************/

+#define HRTIM_BDMUPR_MCR_Pos          (0U)

+#define HRTIM_BDMUPR_MCR_Msk          (0x1UL << HRTIM_BDMUPR_MCR_Pos)          /*!< 0x00000001 */

+#define HRTIM_BDMUPR_MCR              HRTIM_BDMUPR_MCR_Msk                     /*!< MCR register update enable */

+#define HRTIM_BDMUPR_MICR_Pos         (1U)

+#define HRTIM_BDMUPR_MICR_Msk         (0x1UL << HRTIM_BDMUPR_MICR_Pos)         /*!< 0x00000002 */

+#define HRTIM_BDMUPR_MICR             HRTIM_BDMUPR_MICR_Msk                    /*!< MICR register update enable */

+#define HRTIM_BDMUPR_MDIER_Pos        (2U)

+#define HRTIM_BDMUPR_MDIER_Msk        (0x1UL << HRTIM_BDMUPR_MDIER_Pos)        /*!< 0x00000004 */

+#define HRTIM_BDMUPR_MDIER            HRTIM_BDMUPR_MDIER_Msk                   /*!< MDIER register update enable */

+#define HRTIM_BDMUPR_MCNT_Pos         (3U)

+#define HRTIM_BDMUPR_MCNT_Msk         (0x1UL << HRTIM_BDMUPR_MCNT_Pos)         /*!< 0x00000008 */

+#define HRTIM_BDMUPR_MCNT             HRTIM_BDMUPR_MCNT_Msk                    /*!< MCNT register update enable */

+#define HRTIM_BDMUPR_MPER_Pos         (4U)

+#define HRTIM_BDMUPR_MPER_Msk         (0x1UL << HRTIM_BDMUPR_MPER_Pos)         /*!< 0x00000010 */

+#define HRTIM_BDMUPR_MPER             HRTIM_BDMUPR_MPER_Msk                    /*!< MPER register update enable */

+#define HRTIM_BDMUPR_MREP_Pos         (5U)

+#define HRTIM_BDMUPR_MREP_Msk         (0x1UL << HRTIM_BDMUPR_MREP_Pos)         /*!< 0x00000020 */

+#define HRTIM_BDMUPR_MREP             HRTIM_BDMUPR_MREP_Msk                    /*!< MREP register update enable */

+#define HRTIM_BDMUPR_MCMP1_Pos        (6U)

+#define HRTIM_BDMUPR_MCMP1_Msk        (0x1UL << HRTIM_BDMUPR_MCMP1_Pos)        /*!< 0x00000040 */

+#define HRTIM_BDMUPR_MCMP1            HRTIM_BDMUPR_MCMP1_Msk                   /*!< MCMP1 register update enable */

+#define HRTIM_BDMUPR_MCMP2_Pos        (7U)

+#define HRTIM_BDMUPR_MCMP2_Msk        (0x1UL << HRTIM_BDMUPR_MCMP2_Pos)        /*!< 0x00000080 */

+#define HRTIM_BDMUPR_MCMP2            HRTIM_BDMUPR_MCMP2_Msk                   /*!< MCMP2 register update enable */

+#define HRTIM_BDMUPR_MCMP3_Pos        (8U)

+#define HRTIM_BDMUPR_MCMP3_Msk        (0x1UL << HRTIM_BDMUPR_MCMP3_Pos)        /*!< 0x00000100 */

+#define HRTIM_BDMUPR_MCMP3            HRTIM_BDMUPR_MCMP3_Msk                   /*!< MCMP3 register update enable */

+#define HRTIM_BDMUPR_MCMP4_Pos        (9U)

+#define HRTIM_BDMUPR_MCMP4_Msk        (0x1UL << HRTIM_BDMUPR_MCMP4_Pos)        /*!< 0x00000200 */

+#define HRTIM_BDMUPR_MCMP4            HRTIM_BDMUPR_MCMP4_Msk                   /*!< MPCMP4 register update enable */

+

+/*******************  Bit definition for HRTIM_BDTUPR register  ***************/

+#define HRTIM_BDTUPR_TIMCR_Pos        (0U)

+#define HRTIM_BDTUPR_TIMCR_Msk        (0x1UL << HRTIM_BDTUPR_TIMCR_Pos)        /*!< 0x00000001 */

+#define HRTIM_BDTUPR_TIMCR            HRTIM_BDTUPR_TIMCR_Msk                   /*!<  TIMCR register update enable */

+#define HRTIM_BDTUPR_TIMICR_Pos       (1U)

+#define HRTIM_BDTUPR_TIMICR_Msk       (0x1UL << HRTIM_BDTUPR_TIMICR_Pos)       /*!< 0x00000002 */

+#define HRTIM_BDTUPR_TIMICR           HRTIM_BDTUPR_TIMICR_Msk                  /*!<  TIMICR register update enable */

+#define HRTIM_BDTUPR_TIMDIER_Pos      (2U)

+#define HRTIM_BDTUPR_TIMDIER_Msk      (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos)      /*!< 0x00000004 */

+#define HRTIM_BDTUPR_TIMDIER          HRTIM_BDTUPR_TIMDIER_Msk                 /*!<  TIMDIER register update enable */

+#define HRTIM_BDTUPR_TIMCNT_Pos       (3U)

+#define HRTIM_BDTUPR_TIMCNT_Msk       (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos)       /*!< 0x00000008 */

+#define HRTIM_BDTUPR_TIMCNT           HRTIM_BDTUPR_TIMCNT_Msk                  /*!<  TIMCNT register update enable */

+#define HRTIM_BDTUPR_TIMPER_Pos       (4U)

+#define HRTIM_BDTUPR_TIMPER_Msk       (0x1UL << HRTIM_BDTUPR_TIMPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_BDTUPR_TIMPER           HRTIM_BDTUPR_TIMPER_Msk                  /*!<  TIMPER register update enable */

+#define HRTIM_BDTUPR_TIMREP_Pos       (5U)

+#define HRTIM_BDTUPR_TIMREP_Msk       (0x1UL << HRTIM_BDTUPR_TIMREP_Pos)       /*!< 0x00000020 */

+#define HRTIM_BDTUPR_TIMREP           HRTIM_BDTUPR_TIMREP_Msk                  /*!<  TIMREP register update enable */

+#define HRTIM_BDTUPR_TIMCMP1_Pos      (6U)

+#define HRTIM_BDTUPR_TIMCMP1_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos)      /*!< 0x00000040 */

+#define HRTIM_BDTUPR_TIMCMP1          HRTIM_BDTUPR_TIMCMP1_Msk                 /*!<  TIMCMP1 register update enable */

+#define HRTIM_BDTUPR_TIMCMP2_Pos      (7U)

+#define HRTIM_BDTUPR_TIMCMP2_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos)      /*!< 0x00000080 */

+#define HRTIM_BDTUPR_TIMCMP2          HRTIM_BDTUPR_TIMCMP2_Msk                 /*!<  TIMCMP2 register update enable */

+#define HRTIM_BDTUPR_TIMCMP3_Pos      (8U)

+#define HRTIM_BDTUPR_TIMCMP3_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos)      /*!< 0x00000100 */

+#define HRTIM_BDTUPR_TIMCMP3          HRTIM_BDTUPR_TIMCMP3_Msk                 /*!<  TIMCMP3 register update enable */

+#define HRTIM_BDTUPR_TIMCMP4_Pos      (9U)

+#define HRTIM_BDTUPR_TIMCMP4_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos)      /*!< 0x00000200 */

+#define HRTIM_BDTUPR_TIMCMP4          HRTIM_BDTUPR_TIMCMP4_Msk                 /*!<  TIMCMP4 register update enable */

+#define HRTIM_BDTUPR_TIMDTR_Pos       (10U)

+#define HRTIM_BDTUPR_TIMDTR_Msk       (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos)       /*!< 0x00000400 */

+#define HRTIM_BDTUPR_TIMDTR           HRTIM_BDTUPR_TIMDTR_Msk                  /*!<  TIMDTR register update enable */

+#define HRTIM_BDTUPR_TIMSET1R_Pos     (11U)

+#define HRTIM_BDTUPR_TIMSET1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos)     /*!< 0x00000800 */

+#define HRTIM_BDTUPR_TIMSET1R         HRTIM_BDTUPR_TIMSET1R_Msk                /*!<  TIMSET1R register update enable */

+#define HRTIM_BDTUPR_TIMRST1R_Pos     (12U)

+#define HRTIM_BDTUPR_TIMRST1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos)     /*!< 0x00001000 */

+#define HRTIM_BDTUPR_TIMRST1R         HRTIM_BDTUPR_TIMRST1R_Msk                /*!<  TIMRST1R register update enable */

+#define HRTIM_BDTUPR_TIMSET2R_Pos     (13U)

+#define HRTIM_BDTUPR_TIMSET2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos)     /*!< 0x00002000 */

+#define HRTIM_BDTUPR_TIMSET2R         HRTIM_BDTUPR_TIMSET2R_Msk                /*!<  TIMSET2R register update enable */

+#define HRTIM_BDTUPR_TIMRST2R_Pos     (14U)

+#define HRTIM_BDTUPR_TIMRST2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos)     /*!< 0x00004000 */

+#define HRTIM_BDTUPR_TIMRST2R         HRTIM_BDTUPR_TIMRST2R_Msk                /*!<  TIMRST2R register update enable */

+#define HRTIM_BDTUPR_TIMEEFR1_Pos     (15U)

+#define HRTIM_BDTUPR_TIMEEFR1_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos)     /*!< 0x00008000 */

+#define HRTIM_BDTUPR_TIMEEFR1         HRTIM_BDTUPR_TIMEEFR1_Msk                /*!<  TIMEEFR1 register update enable */

+#define HRTIM_BDTUPR_TIMEEFR2_Pos     (16U)

+#define HRTIM_BDTUPR_TIMEEFR2_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos)     /*!< 0x00010000 */

+#define HRTIM_BDTUPR_TIMEEFR2         HRTIM_BDTUPR_TIMEEFR2_Msk                /*!<  TIMEEFR2 register update enable */

+#define HRTIM_BDTUPR_TIMRSTR_Pos      (17U)

+#define HRTIM_BDTUPR_TIMRSTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos)      /*!< 0x00020000 */

+#define HRTIM_BDTUPR_TIMRSTR          HRTIM_BDTUPR_TIMRSTR_Msk                 /*!<  TIMRSTR register update enable */

+#define HRTIM_BDTUPR_TIMCHPR_Pos      (18U)

+#define HRTIM_BDTUPR_TIMCHPR_Msk      (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos)      /*!< 0x00040000 */

+#define HRTIM_BDTUPR_TIMCHPR          HRTIM_BDTUPR_TIMCHPR_Msk                 /*!<  TIMCHPR register update enable */

+#define HRTIM_BDTUPR_TIMOUTR_Pos      (19U)

+#define HRTIM_BDTUPR_TIMOUTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos)      /*!< 0x00080000 */

+#define HRTIM_BDTUPR_TIMOUTR          HRTIM_BDTUPR_TIMOUTR_Msk                 /*!<  TIMOUTR register update enable */

+#define HRTIM_BDTUPR_TIMFLTR_Pos      (20U)

+#define HRTIM_BDTUPR_TIMFLTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos)      /*!< 0x00100000 */

+#define HRTIM_BDTUPR_TIMFLTR          HRTIM_BDTUPR_TIMFLTR_Msk                 /*!<  TIMFLTR register update enable */

+

+/*******************  Bit definition for HRTIM_BDMADR register  ***************/

+#define HRTIM_BDMADR_BDMADR_Pos       (0U)

+#define HRTIM_BDMADR_BDMADR_Msk       (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos) /*!< 0xFFFFFFFF */

+#define HRTIM_BDMADR_BDMADR           HRTIM_BDMADR_BDMADR_Msk                  /*!<  Burst DMA Data register */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             RAM ECC monitoring                             */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for RAMECC_IER register  ******************/

+#define RAMECC_IER_GECCDEBWIE_Pos         (3U)

+#define RAMECC_IER_GECCDEBWIE_Msk         (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)  /*!< 0x00000008 */

+#define RAMECC_IER_GECCDEBWIE             RAMECC_IER_GECCDEBWIE_Msk             /*!< Global ECC double error on byte write (BW) interrupt enable */

+#define RAMECC_IER_GECCDEIE_Pos           (2U)

+#define RAMECC_IER_GECCDEIE_Msk           (0x1UL << RAMECC_IER_GECCDEIE_Pos)    /*!< 0x00000004 */

+#define RAMECC_IER_GECCDEIE               RAMECC_IER_GECCDEIE_Msk               /*!< Global ECC double error interrupt enable */

+#define RAMECC_IER_GECCSEIE_Pos           (1U)

+#define RAMECC_IER_GECCSEIE_Msk           (0x1UL << RAMECC_IER_GECCSEIE_Pos)    /*!< 0x00000002 */

+#define RAMECC_IER_GECCSEIE               RAMECC_IER_GECCSEIE_Msk               /*!< Global ECC single error interrupt enable */

+#define RAMECC_IER_GIE_Pos                (0U)

+#define RAMECC_IER_GIE_Msk                (0x1UL << RAMECC_IER_GIE_Pos)         /*!< 0x00000001 */

+#define RAMECC_IER_GIE                    RAMECC_IER_GIE_Msk                    /*!< Global interrupt enable */

+

+/*******************  Bit definition for RAMECC_CR register  ******************/

+#define RAMECC_CR_ECCELEN_Pos             (5U)

+#define RAMECC_CR_ECCELEN_Msk             (0x1UL << RAMECC_CR_ECCELEN_Pos)      /*!< 0x00000020 */

+#define RAMECC_CR_ECCELEN                 RAMECC_CR_ECCELEN_Msk                 /*!< ECC error latching enable */

+#define RAMECC_CR_ECCDEBWIE_Pos           (4U)

+#define RAMECC_CR_ECCDEBWIE_Msk           (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)    /*!< 0x00000010 */

+#define RAMECC_CR_ECCDEBWIE               RAMECC_CR_ECCDEBWIE_Msk               /*!< ECC double error on byte write (BW) interrupt enable */

+#define RAMECC_CR_ECCDEIE_Pos             (3U)

+#define RAMECC_CR_ECCDEIE_Msk             (0x1UL << RAMECC_CR_ECCDEIE_Pos)      /*!< 0x00000008 */

+#define RAMECC_CR_ECCDEIE                 RAMECC_CR_ECCDEIE_Msk                 /*!< ECC double error interrupt enable */

+#define RAMECC_CR_ECCSEIE_Pos             (2U)

+#define RAMECC_CR_ECCSEIE_Msk             (0x1UL << RAMECC_CR_ECCSEIE_Pos)      /*!< 0x00000004 */

+#define RAMECC_CR_ECCSEIE                 RAMECC_CR_ECCSEIE_Msk                 /*!< ECC single error interrupt enable */

+

+/*******************  Bit definition for RAMECC_SR register  ******************/

+#define RAMECC_SR_DEBWDF_Pos             (2U)

+#define RAMECC_SR_DEBWDF_Msk             (0x1UL << RAMECC_SR_DEBWDF_Pos)        /*!< 0x00000004 */

+#define RAMECC_SR_DEBWDF                 RAMECC_SR_DEBWDF_Msk                   /*!< ECC double error on byte write (BW) detected flag */

+#define RAMECC_SR_DEDF_Pos               (1U)

+#define RAMECC_SR_DEDF_Msk               (0x1UL << RAMECC_SR_DEDF_Pos)          /*!< 0x00000002 */

+#define RAMECC_SR_DEDF                   RAMECC_SR_DEDF_Msk                     /*!< ECC double error detected flag */

+#define RAMECC_SR_SEDCF_Pos              (0U)

+#define RAMECC_SR_SEDCF_Msk              (0x1UL << RAMECC_SR_SEDCF_Pos)         /*!< 0x00000001 */

+#define RAMECC_SR_SEDCF                  RAMECC_SR_SEDCF_Msk                    /*!< ECC single error detected and corrected flag */

+

+/******************  Bit definition for RAMECC_FAR register  ******************/

+#define RAMECC_FAR_FADD_Pos              (0U)

+#define RAMECC_FAR_FADD_Msk              (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)  /*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FADD                  RAMECC_FAR_FADD_Msk                    /*!< ECC error failing address */

+

+/******************  Bit definition for RAMECC_FDRL register  *****************/

+#define RAMECC_FAR_FDATAL_Pos            (0U)

+#define RAMECC_FAR_FDATAL_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FDATAL                RAMECC_FAR_FDATAL_Msk                  /*!< ECC error failing address */

+

+/******************  Bit definition for RAMECC_FDRH register  *****************/

+#define RAMECC_FAR_FDATAH_Pos            (0U)

+#define RAMECC_FAR_FDATAH_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FDATAH                RAMECC_FAR_FDATAH_Msk                  /* Failing data high (64-bit memory) */

+

+/*****************  Bit definition for RAMECC_FECR register  ******************/

+#define RAMECC_FECR_FEC_Pos              (0U)

+#define RAMECC_FECR_FEC_Msk              (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)  /*!< 0xFFFFFFFF */

+#define RAMECC_FECR_FEC                  RAMECC_FECR_FEC_Msk                    /*!< Failing error code */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                MDIOS                                        */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for MDIOS_CR register  *******************/

+#define MDIOS_CR_EN_Pos                (0U)

+#define MDIOS_CR_EN_Msk                (0x1UL << MDIOS_CR_EN_Pos)              /*!< 0x00000001 */

+#define MDIOS_CR_EN                    MDIOS_CR_EN_Msk                         /*!<  MDIOS slave peripheral enable */

+#define MDIOS_CR_WRIE_Pos              (1U)

+#define MDIOS_CR_WRIE_Msk              (0x1UL << MDIOS_CR_WRIE_Pos)            /*!< 0x00000002 */

+#define MDIOS_CR_WRIE                  MDIOS_CR_WRIE_Msk                       /*!<  MDIOS slave register write interrupt enable. */

+#define MDIOS_CR_RDIE_Pos              (2U)

+#define MDIOS_CR_RDIE_Msk              (0x1UL << MDIOS_CR_RDIE_Pos)            /*!< 0x00000004 */

+#define MDIOS_CR_RDIE                  MDIOS_CR_RDIE_Msk                       /*!<  MDIOS slave register read interrupt enable. */

+#define MDIOS_CR_EIE_Pos               (3U)

+#define MDIOS_CR_EIE_Msk               (0x1UL << MDIOS_CR_EIE_Pos)             /*!< 0x00000008 */

+#define MDIOS_CR_EIE                   MDIOS_CR_EIE_Msk                        /*!<  MDIOS slave register error interrupt enable. */

+#define MDIOS_CR_DPC_Pos               (7U)

+#define MDIOS_CR_DPC_Msk               (0x1UL << MDIOS_CR_DPC_Pos)             /*!< 0x00000080 */

+#define MDIOS_CR_DPC                   MDIOS_CR_DPC_Msk                        /*!<  MDIOS slave disable preamble check. */

+#define MDIOS_CR_PORT_ADDRESS_Pos      (8U)

+#define MDIOS_CR_PORT_ADDRESS_Msk      (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)   /*!< 0x00001F00 */

+#define MDIOS_CR_PORT_ADDRESS          MDIOS_CR_PORT_ADDRESS_Msk               /*!<  MDIOS slave port address mask. */

+#define MDIOS_CR_PORT_ADDRESS_0        (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000100 */

+#define MDIOS_CR_PORT_ADDRESS_1        (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000200 */

+#define MDIOS_CR_PORT_ADDRESS_2        (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000400 */

+#define MDIOS_CR_PORT_ADDRESS_3        (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000800 */

+#define MDIOS_CR_PORT_ADDRESS_4        (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001000 */

+

+/********************  Bit definition for MDIOS_SR register  *******************/

+#define MDIOS_SR_PERF_Pos              (0U)

+#define MDIOS_SR_PERF_Msk              (0x1UL << MDIOS_SR_PERF_Pos)            /*!< 0x00000001 */

+#define MDIOS_SR_PERF                  MDIOS_SR_PERF_Msk                       /*!<  MDIOS slave turnaround error flag*/

+#define MDIOS_SR_SERF_Pos              (1U)

+#define MDIOS_SR_SERF_Msk              (0x1UL << MDIOS_SR_SERF_Pos)            /*!< 0x00000002 */

+#define MDIOS_SR_SERF                  MDIOS_SR_SERF_Msk                       /*!<  MDIOS slave start error flag */

+#define MDIOS_SR_TERF_Pos              (2U)

+#define MDIOS_SR_TERF_Msk              (0x1UL << MDIOS_SR_TERF_Pos)            /*!< 0x00000004 */

+#define MDIOS_SR_TERF                  MDIOS_SR_TERF_Msk                       /*!<  MDIOS slave preamble error flag */

+

+/********************  Bit definition for MDIOS_CLRFR register  *******************/

+#define MDIOS_SR_CPERF_Pos             (0U)

+#define MDIOS_SR_CPERF_Msk             (0x1UL << MDIOS_SR_CPERF_Pos)           /*!< 0x00000001 */

+#define MDIOS_SR_CPERF                 MDIOS_SR_CPERF_Msk                      /*!<  MDIOS slave Clear the turnaround error flag */

+#define MDIOS_SR_CSERF_Pos             (1U)

+#define MDIOS_SR_CSERF_Msk             (0x1UL << MDIOS_SR_CSERF_Pos)           /*!< 0x00000002 */

+#define MDIOS_SR_CSERF                 MDIOS_SR_CSERF_Msk                      /*!<  MDIOS slave Clear the start error flag */

+#define MDIOS_SR_CTERF_Pos             (2U)

+#define MDIOS_SR_CTERF_Msk             (0x1UL << MDIOS_SR_CTERF_Pos)           /*!< 0x00000004 */

+#define MDIOS_SR_CTERF                 MDIOS_SR_CTERF_Msk                      /*!<  MDIOS slave Clear the preamble error flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                       USB_OTG                              */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/

+#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)

+#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */

+#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */

+#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)

+#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */

+#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */

+#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)

+#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */

+#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */

+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)

+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */

+#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */

+#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)

+#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */

+#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */

+#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)

+#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */

+#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */

+#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)

+#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */

+#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */

+#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)

+#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */

+#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */

+#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)

+#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */

+#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */

+#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)

+#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */

+#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */

+#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)

+#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */

+#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */

+#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)

+#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */

+#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */

+#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)

+#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */

+#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */

+#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)

+#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */

+#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */

+#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)

+#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */

+#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */

+#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)

+#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */

+#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */

+#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)

+#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */

+#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */

+#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)

+#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */

+#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */

+

+/********************  Bit definition forUSB_OTG_HCFG register  ********************/

+

+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)

+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */

+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */

+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)

+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */

+

+/********************  Bit definition forUSB_OTG_DCFG register  ********************/

+

+#define USB_OTG_DCFG_DSPD_Pos                    (0U)

+#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */

+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */

+#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */

+#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)

+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */

+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */

+

+#define USB_OTG_DCFG_DAD_Pos                     (4U)

+#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */

+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */

+#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */

+#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */

+#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */

+#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */

+#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */

+#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */

+#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */

+

+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)

+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */

+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */

+#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */

+#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */

+

+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)

+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */

+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */

+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */

+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */

+

+/********************  Bit definition forUSB_OTG_PCGCR register  ********************/

+#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)

+#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */

+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */

+#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)

+#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */

+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */

+#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)

+#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */

+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */

+

+/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/

+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)

+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */

+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */

+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)

+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */

+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */

+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)

+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */

+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */

+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)

+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */

+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */

+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)

+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */

+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */

+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)

+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */

+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */

+

+/********************  Bit definition forUSB_OTG_DCTL register  ********************/

+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)

+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */

+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */

+#define USB_OTG_DCTL_SDIS_Pos                    (1U)

+#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */

+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */

+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)

+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */

+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */

+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)

+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */

+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */

+

+#define USB_OTG_DCTL_TCTL_Pos                    (4U)

+#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */

+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */

+#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */

+#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */

+#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */

+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)

+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */

+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */

+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)

+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */

+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */

+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)

+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */

+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */

+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)

+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */

+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */

+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)

+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */

+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */

+

+/********************  Bit definition forUSB_OTG_HFIR register  ********************/

+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)

+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */

+

+/********************  Bit definition forUSB_OTG_HFNUM register  ********************/

+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)

+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */

+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)

+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */

+

+/********************  Bit definition forUSB_OTG_DSTS register  ********************/

+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)

+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */

+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */

+

+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)

+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */

+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */

+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */

+#define USB_OTG_DSTS_EERR_Pos                    (3U)

+#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */

+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */

+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)

+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */

+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */

+

+/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/

+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)

+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */

+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */

+

+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)

+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */

+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */

+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */

+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */

+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */

+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */

+#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */

+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)

+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */

+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */

+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)

+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */

+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */

+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)

+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */

+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */

+

+/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/

+

+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)

+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */

+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */

+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */

+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */

+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */

+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)

+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */

+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */

+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)

+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */

+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */

+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)

+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */

+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */

+

+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)

+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */

+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */

+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */

+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */

+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */

+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */

+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)

+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */

+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */

+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)

+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */

+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */

+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)

+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */

+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */

+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)

+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */

+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */

+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)

+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */

+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */

+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)

+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */

+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */

+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)

+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */

+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */

+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)

+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */

+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */

+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)

+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */

+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */

+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)

+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */

+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */

+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)

+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */

+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */

+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)

+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */

+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */

+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)

+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */

+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */

+

+/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/

+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)

+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */

+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */

+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)

+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */

+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */

+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)

+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */

+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */

+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)

+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */

+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */

+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)

+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */

+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */

+

+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)

+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */

+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */

+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */

+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */

+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */

+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */

+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */

+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)

+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */

+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */

+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)

+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */

+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */

+

+/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/

+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)

+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */

+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)

+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */

+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)

+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */

+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)

+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */

+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)

+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */

+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)

+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */

+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)

+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */

+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)

+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */

+

+/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/

+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)

+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */

+

+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)

+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */

+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */

+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */

+

+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)

+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */

+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */

+

+/********************  Bit definition forUSB_OTG_HAINT register  ********************/

+#define USB_OTG_HAINT_HAINT_Pos                  (0U)

+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */

+

+/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/

+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)

+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */

+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)

+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */

+#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)

+#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */

+#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask               */

+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)

+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */

+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)

+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */

+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)

+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */

+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)

+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */

+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)

+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */

+#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)

+#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */

+#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)

+#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask               */

+#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)

+#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask               */

+#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)

+#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                */

+

+/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/

+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)

+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */

+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */

+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)

+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */

+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */

+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)

+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */

+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */

+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)

+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */

+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */

+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)

+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */

+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */

+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)

+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */

+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */

+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)

+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */

+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */

+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)

+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */

+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */

+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)

+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */

+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */

+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)

+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */

+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */

+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)

+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */

+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */

+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)

+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */

+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */

+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)

+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */

+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */

+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)

+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */

+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */

+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)

+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */

+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */

+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)

+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */

+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */

+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)

+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */

+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */

+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)

+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */

+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */

+#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)

+#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */

+#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */

+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)

+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */

+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */

+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)

+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */

+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */

+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)

+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */

+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */

+#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)

+#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */

+#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */

+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)

+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */

+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */

+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)

+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */

+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */

+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)

+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */

+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */

+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)

+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */

+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */

+

+/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/

+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)

+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */

+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */

+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)

+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */

+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */

+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)

+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */

+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */

+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)

+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */

+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */

+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)

+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */

+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */

+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)

+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */

+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */

+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)

+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */

+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */

+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)

+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */

+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */

+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)

+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */

+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */

+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)

+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */

+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */

+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)

+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */

+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */

+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)

+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */

+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */

+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)

+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */

+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */

+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)

+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */

+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */

+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)

+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */

+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */

+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)

+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */

+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */

+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)

+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */

+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */

+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)

+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */

+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */

+#define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)

+#define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */

+#define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */

+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)

+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */

+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */

+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)

+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */

+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */

+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)

+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */

+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */

+#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)

+#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */

+#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */

+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)

+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */

+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */

+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)

+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */

+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */

+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)

+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */

+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */

+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)

+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */

+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */

+

+/********************  Bit definition forUSB_OTG_DAINT register  ********************/

+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)

+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */

+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)

+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */

+

+/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/

+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)

+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */

+

+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/

+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)

+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */

+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */

+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)

+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */

+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */

+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)

+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */

+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */

+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)

+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */

+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */

+

+/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/

+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)

+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */

+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)

+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */

+

+/********************  Bit definition for OTG register  ********************/

+

+#define USB_OTG_CHNUM_Pos                        (0U)

+#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)  /*!< 0x0000000F */

+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */

+#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */

+#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */

+#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */

+#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */

+#define USB_OTG_BCNT_Pos                         (4U)

+#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */

+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */

+

+#define USB_OTG_DPID_Pos                         (15U)

+#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)   /*!< 0x00018000 */

+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */

+#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */

+#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */

+

+#define USB_OTG_PKTSTS_Pos                       (17U)

+#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */

+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */

+#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */

+#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */

+#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */

+#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */

+

+#define USB_OTG_EPNUM_Pos                        (0U)

+#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)  /*!< 0x0000000F */

+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */

+#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */

+#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */

+#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */

+#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */

+

+#define USB_OTG_FRMNUM_Pos                       (21U)

+#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */

+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */

+#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */

+#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */

+#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */

+#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */

+

+/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/

+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)

+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/

+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)

+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */

+

+/********************  Bit definition for OTG register  ********************/

+#define USB_OTG_NPTXFSA_Pos                      (0U)

+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */

+#define USB_OTG_NPTXFD_Pos                       (16U)

+#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */

+#define USB_OTG_TX0FSA_Pos                       (0U)

+#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */

+#define USB_OTG_TX0FD_Pos                        (16U)

+#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */

+

+/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/

+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)

+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */

+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */

+

+/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/

+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)

+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */

+

+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)

+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */

+

+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)

+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/

+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)

+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */

+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */

+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)

+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */

+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */

+

+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)

+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */

+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */

+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */

+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)

+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */

+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */

+

+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)

+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */

+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */

+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)

+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */

+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */

+

+/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */

+

+/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/

+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)

+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */

+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */

+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)

+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */

+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */

+

+/********************  Bit definition forUSB_OTG_GCCFG register  ********************/

+#define USB_OTG_GCCFG_DCDET_Pos                  (0U)

+#define USB_OTG_GCCFG_DCDET_Msk                  (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */

+#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */

+#define USB_OTG_GCCFG_PDET_Pos                   (1U)

+#define USB_OTG_GCCFG_PDET_Msk                   (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */

+#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */

+#define USB_OTG_GCCFG_SDET_Pos                   (2U)

+#define USB_OTG_GCCFG_SDET_Msk                   (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */

+#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */

+#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)

+#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */

+#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */

+#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)

+#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */

+#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */

+#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)

+#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */

+#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */

+#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)

+#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */

+#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/

+#define USB_OTG_GCCFG_PDEN_Pos                   (19U)

+#define USB_OTG_GCCFG_PDEN_Msk                   (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */

+#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/

+#define USB_OTG_GCCFG_SDEN_Pos                   (20U)

+#define USB_OTG_GCCFG_SDEN_Msk                   (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */

+#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */

+#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)

+#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */

+#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */

+

+/********************  Bit definition forUSB_OTG_GPWRDN) register  ********************/

+#define USB_OTG_GPWRDN_ADPMEN_Pos                (0U)

+#define USB_OTG_GPWRDN_ADPMEN_Msk                (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */

+#define USB_OTG_GPWRDN_ADPMEN                    USB_OTG_GPWRDN_ADPMEN_Msk     /*!< ADP module enable */

+#define USB_OTG_GPWRDN_ADPIF_Pos                 (23U)

+#define USB_OTG_GPWRDN_ADPIF_Msk                 (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */

+#define USB_OTG_GPWRDN_ADPIF                     USB_OTG_GPWRDN_ADPIF_Msk      /*!< ADP Interrupt flag */

+

+/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/

+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)

+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */

+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)

+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */

+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */

+

+/********************  Bit definition forUSB_OTG_CID register  ********************/

+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)

+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */

+

+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/

+#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)

+#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */

+#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */

+#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)

+#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */

+#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */

+#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)

+#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */

+#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */

+#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)

+#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */

+#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */

+#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)

+#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */

+#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */

+#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)

+#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */

+#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */

+#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)

+#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */

+#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */

+#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)

+#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */

+#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */

+#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)

+#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */

+#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */

+#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)

+#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */

+#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */

+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)

+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */

+#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */

+#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)

+#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */

+#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */

+#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)

+#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */

+#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */

+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)

+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */

+#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */

+#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)

+#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */

+#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */

+

+/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/

+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)

+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */

+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)

+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */

+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)

+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */

+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)

+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */

+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)

+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */

+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)

+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */

+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)

+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */

+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)

+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */

+

+/********************  Bit definition forUSB_OTG_HPRT register  ********************/

+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)

+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */

+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */

+#define USB_OTG_HPRT_PCDET_Pos                   (1U)

+#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */

+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */

+#define USB_OTG_HPRT_PENA_Pos                    (2U)

+#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */

+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */

+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)

+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */

+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */

+#define USB_OTG_HPRT_POCA_Pos                    (4U)

+#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */

+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */

+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)

+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */

+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */

+#define USB_OTG_HPRT_PRES_Pos                    (6U)

+#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */

+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume   */

+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)

+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */

+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend  */

+#define USB_OTG_HPRT_PRST_Pos                    (8U)

+#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */

+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset    */

+

+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)

+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */

+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */

+#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */

+#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */

+#define USB_OTG_HPRT_PPWR_Pos                    (12U)

+#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */

+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */

+

+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)

+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */

+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */

+#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */

+#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */

+#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */

+#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */

+

+#define USB_OTG_HPRT_PSPD_Pos                    (17U)

+#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */

+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */

+#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */

+#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */

+

+/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/

+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)

+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)

+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)

+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */

+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)

+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */

+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)

+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */

+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)

+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */

+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)

+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)

+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)

+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)

+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */

+

+/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/

+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)

+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */

+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)

+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/

+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)

+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */

+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)

+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */

+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */

+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)

+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */

+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */

+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)

+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */

+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */

+

+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)

+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */

+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */

+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)

+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */

+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */

+

+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)

+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */

+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */

+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */

+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */

+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */

+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */

+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)

+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */

+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */

+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)

+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */

+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */

+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)

+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */

+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)

+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */

+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)

+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */

+

+/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/

+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)

+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */

+

+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)

+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */

+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */

+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */

+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */

+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */

+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */

+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)

+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */

+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */

+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)

+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */

+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */

+

+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)

+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */

+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */

+

+#define USB_OTG_HCCHAR_MC_Pos                    (20U)

+#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */

+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */

+#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */

+#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */

+

+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)

+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */

+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */

+#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */

+#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */

+#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */

+#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */

+#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */

+#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */

+#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */

+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)

+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */

+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)

+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */

+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)

+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */

+

+/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/

+

+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)

+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */

+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */

+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */

+

+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)

+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */

+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */

+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */

+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */

+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */

+

+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)

+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */

+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */

+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */

+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */

+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)

+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */

+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */

+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)

+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */

+

+/********************  Bit definition forUSB_OTG_HCINT register  ********************/

+#define USB_OTG_HCINT_XFRC_Pos                   (0U)

+#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */

+#define USB_OTG_HCINT_CHH_Pos                    (1U)

+#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */

+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)

+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */

+#define USB_OTG_HCINT_STALL_Pos                  (3U)

+#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */

+#define USB_OTG_HCINT_NAK_Pos                    (4U)

+#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */

+#define USB_OTG_HCINT_ACK_Pos                    (5U)

+#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */

+#define USB_OTG_HCINT_NYET_Pos                   (6U)

+#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */

+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */

+#define USB_OTG_HCINT_TXERR_Pos                  (7U)

+#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */

+#define USB_OTG_HCINT_BBERR_Pos                  (8U)

+#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */

+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)

+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */

+#define USB_OTG_HCINT_DTERR_Pos                  (10U)

+#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */

+

+/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/

+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)

+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */

+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)

+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */

+#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)

+#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */

+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)

+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */

+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)

+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */

+#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)

+#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */

+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)

+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */

+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)

+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */

+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */

+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)

+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */

+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)

+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */

+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)

+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */

+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */

+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)

+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */

+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */

+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)

+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */

+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */

+

+/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/

+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)

+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */

+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)

+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */

+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)

+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */

+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)

+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */

+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)

+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */

+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)

+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */

+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)

+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */

+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */

+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)

+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */

+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)

+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */

+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)

+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */

+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)

+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */

+

+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/

+

+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)

+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */

+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)

+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */

+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)

+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */

+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */

+/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/

+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)

+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */

+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)

+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */

+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)

+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */

+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)

+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */

+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */

+#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */

+#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/

+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)

+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */

+

+/********************  Bit definition forUSB_OTG_HCDMA register  ********************/

+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)

+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */

+

+/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/

+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)

+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */

+

+/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/

+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)

+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */

+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)

+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/

+

+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)

+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */

+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)

+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */

+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */

+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)

+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */

+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */

+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)

+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */

+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)

+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */

+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */

+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)

+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */

+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */

+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)

+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */

+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */

+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)

+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */

+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */

+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)

+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */

+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */

+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)

+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */

+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)

+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */

+

+/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/

+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)

+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */

+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)

+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */

+#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)

+#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */

+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)

+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */

+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)

+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */

+#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)

+#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< OUT Status Phase Received interrupt */

+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)

+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */

+#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)

+#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */

+#define USB_OTG_DOEPINT_BERR_Pos                 (12U)

+#define USB_OTG_DOEPINT_BERR_Msk                 (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPINT_BERR                      USB_OTG_DOEPINT_BERR_Msk   /*!< Babble error interrupt */

+#define USB_OTG_DOEPINT_NAK_Pos                  (13U)

+#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */

+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)

+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */

+#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)

+#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */

+#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */

+

+/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/

+

+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)

+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */

+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)

+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */

+

+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)

+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */

+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */

+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */

+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition for PCGCCTL register  ********************/

+#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)

+#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */

+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */

+#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)

+#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */

+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */

+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)

+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */

+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/** @addtogroup Exported_macros

+  * @{

+  */

+

+/******************************* ADC Instances ********************************/

+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \

+                                       ((INSTANCE) == ADC2) || \

+                                       ((INSTANCE) == ADC3))

+

+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)

+

+#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) ||\

+                                          ((INSTANCE) == ADC3_COMMON))

+

+/******************************** COMP Instances ******************************/

+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \

+                                       ((INSTANCE) == COMP2))

+

+#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)

+/******************** COMP Instances with window mode capability **************/

+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)

+

+

+/******************************* CRC Instances ********************************/

+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

+

+/******************************* DAC Instances ********************************/

+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)

+/******************************* DCMI Instances *******************************/

+#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)

+

+/******************************* DELAYBLOCK Instances *******************************/

+#define IS_DLYB_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DLYB_SDMMC1) || \

+                                         ((INSTANCE) == DLYB_SDMMC2) || \

+                                         ((INSTANCE) == DLYB_QUADSPI))

+/****************************** DFSDM Instances *******************************/

+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \

+                                               ((INSTANCE) == DFSDM1_Filter1) || \

+                                               ((INSTANCE) == DFSDM1_Filter2) || \

+                                               ((INSTANCE) == DFSDM1_Filter3))

+

+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \

+                                                 ((INSTANCE) == DFSDM1_Channel1) || \

+                                                 ((INSTANCE) == DFSDM1_Channel2) || \

+                                                 ((INSTANCE) == DFSDM1_Channel3) || \

+                                                 ((INSTANCE) == DFSDM1_Channel4) || \

+                                                 ((INSTANCE) == DFSDM1_Channel5) || \

+                                                 ((INSTANCE) == DFSDM1_Channel6) || \

+                                                 ((INSTANCE) == DFSDM1_Channel7))

+/****************************** RAMECC Instances ******************************/

+#define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC1_Monitor1)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor2)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor3)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor4)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor5)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor1)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor2)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor3)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor4)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor5)   || \

+                                                  ((INSTANCE) == RAMECC3_Monitor1)   || \

+                                                  ((INSTANCE) == RAMECC3_Monitor2))

+

+/******************************** DMA Instances *******************************/

+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \

+                                       ((INSTANCE) == DMA1_Stream1)   || \

+                                       ((INSTANCE) == DMA1_Stream2)   || \

+                                       ((INSTANCE) == DMA1_Stream3)   || \

+                                       ((INSTANCE) == DMA1_Stream4)   || \

+                                       ((INSTANCE) == DMA1_Stream5)   || \

+                                       ((INSTANCE) == DMA1_Stream6)   || \

+                                       ((INSTANCE) == DMA1_Stream7)   || \

+                                       ((INSTANCE) == DMA2_Stream0)   || \

+                                       ((INSTANCE) == DMA2_Stream1)   || \

+                                       ((INSTANCE) == DMA2_Stream2)   || \

+                                       ((INSTANCE) == DMA2_Stream3)   || \

+                                       ((INSTANCE) == DMA2_Stream4)   || \

+                                       ((INSTANCE) == DMA2_Stream5)   || \

+                                       ((INSTANCE) == DMA2_Stream6)   || \

+                                       ((INSTANCE) == DMA2_Stream7)   || \

+                                       ((INSTANCE) == BDMA_Channel0) || \

+                                       ((INSTANCE) == BDMA_Channel1) || \

+                                       ((INSTANCE) == BDMA_Channel2) || \

+                                       ((INSTANCE) == BDMA_Channel3) || \

+                                       ((INSTANCE) == BDMA_Channel4) || \

+                                       ((INSTANCE) == BDMA_Channel5) || \

+                                       ((INSTANCE) == BDMA_Channel6) || \

+                                       ((INSTANCE) == BDMA_Channel7))

+

+/****************************** BDMA CHANNEL Instances ***************************/

+#define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \

+                                            ((INSTANCE) == BDMA_Channel1) || \

+                                            ((INSTANCE) == BDMA_Channel2) || \

+                                            ((INSTANCE) == BDMA_Channel3) || \

+                                            ((INSTANCE) == BDMA_Channel4) || \

+                                            ((INSTANCE) == BDMA_Channel5) || \

+                                            ((INSTANCE) == BDMA_Channel6) || \

+                                            ((INSTANCE) == BDMA_Channel7))

+

+/****************************** DMA DMAMUX ALL Instances ***************************/

+#define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)    || \

+                                               ((INSTANCE) == DMA1_Stream1)    || \

+                                               ((INSTANCE) == DMA1_Stream2)    || \

+                                               ((INSTANCE) == DMA1_Stream3)    || \

+                                               ((INSTANCE) == DMA1_Stream4)    || \

+                                               ((INSTANCE) == DMA1_Stream5)    || \

+                                               ((INSTANCE) == DMA1_Stream6)    || \

+                                               ((INSTANCE) == DMA1_Stream7)    || \

+                                               ((INSTANCE) == DMA2_Stream0)    || \

+                                               ((INSTANCE) == DMA2_Stream1)    || \

+                                               ((INSTANCE) == DMA2_Stream2)    || \

+                                               ((INSTANCE) == DMA2_Stream3)    || \

+                                               ((INSTANCE) == DMA2_Stream4)    || \

+                                               ((INSTANCE) == DMA2_Stream5)    || \

+                                               ((INSTANCE) == DMA2_Stream6)    || \

+                                               ((INSTANCE) == DMA2_Stream7)    || \

+                                               ((INSTANCE) == BDMA_Channel0)   || \

+                                               ((INSTANCE) == BDMA_Channel1)   || \

+                                               ((INSTANCE) == BDMA_Channel2)   || \

+                                               ((INSTANCE) == BDMA_Channel3)   || \

+                                               ((INSTANCE) == BDMA_Channel4)   || \

+                                               ((INSTANCE) == BDMA_Channel5)   || \

+                                               ((INSTANCE) == BDMA_Channel6)   || \

+                                               ((INSTANCE) == BDMA_Channel7))

+

+/****************************** BDMA DMAMUX Instances ***************************/

+#define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == BDMA_Channel0) || \

+                                                    ((INSTANCE) == BDMA_Channel1) || \

+                                                    ((INSTANCE) == BDMA_Channel2) || \

+                                                    ((INSTANCE) == BDMA_Channel3) || \

+                                                    ((INSTANCE) == BDMA_Channel4) || \

+                                                    ((INSTANCE) == BDMA_Channel5) || \

+                                                    ((INSTANCE) == BDMA_Channel6) || \

+                                                    ((INSTANCE) == BDMA_Channel7))

+

+/****************************** DMA STREAM Instances ***************************/

+#define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \

+                                          ((INSTANCE) == DMA1_Stream1)   || \

+                                          ((INSTANCE) == DMA1_Stream2)   || \

+                                          ((INSTANCE) == DMA1_Stream3)   || \

+                                          ((INSTANCE) == DMA1_Stream4)   || \

+                                          ((INSTANCE) == DMA1_Stream5)   || \

+                                          ((INSTANCE) == DMA1_Stream6)   || \

+                                          ((INSTANCE) == DMA1_Stream7)   || \

+                                          ((INSTANCE) == DMA2_Stream0)   || \

+                                          ((INSTANCE) == DMA2_Stream1)   || \

+                                          ((INSTANCE) == DMA2_Stream2)   || \

+                                          ((INSTANCE) == DMA2_Stream3)   || \

+                                          ((INSTANCE) == DMA2_Stream4)   || \

+                                          ((INSTANCE) == DMA2_Stream5)   || \

+                                          ((INSTANCE) == DMA2_Stream6)   || \

+                                          ((INSTANCE) == DMA2_Stream7))

+

+/****************************** DMA DMAMUX Instances ***************************/

+#define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)   || \

+                                                  ((INSTANCE) == DMA1_Stream1)   || \

+                                                  ((INSTANCE) == DMA1_Stream2)   || \

+                                                  ((INSTANCE) == DMA1_Stream3)   || \

+                                                  ((INSTANCE) == DMA1_Stream4)   || \

+                                                  ((INSTANCE) == DMA1_Stream5)   || \

+                                                  ((INSTANCE) == DMA1_Stream6)   || \

+                                                  ((INSTANCE) == DMA1_Stream7)   || \

+                                                  ((INSTANCE) == DMA2_Stream0)   || \

+                                                  ((INSTANCE) == DMA2_Stream1)   || \

+                                                  ((INSTANCE) == DMA2_Stream2)   || \

+                                                  ((INSTANCE) == DMA2_Stream3)   || \

+                                                  ((INSTANCE) == DMA2_Stream4)   || \

+                                                  ((INSTANCE) == DMA2_Stream5)   || \

+                                                  ((INSTANCE) == DMA2_Stream6)   || \

+                                                  ((INSTANCE) == DMA2_Stream7))

+

+/******************************** DMA Request Generator Instances **************/

+#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator1) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator2) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator3) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator4) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator5) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator6) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator7) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator0) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator1) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator2) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator3) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator4) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator5) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator6) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator7))

+

+/******************************* DMA2D Instances *******************************/

+#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)

+

+/******************************** MDMA Request Generator Instances **************/

+#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0)  || \

+                                               ((INSTANCE) == MDMA_Channel1)  || \

+                                               ((INSTANCE) == MDMA_Channel2)  || \

+                                               ((INSTANCE) == MDMA_Channel3)  || \

+                                               ((INSTANCE) == MDMA_Channel4)  || \

+                                               ((INSTANCE) == MDMA_Channel5)  || \

+                                               ((INSTANCE) == MDMA_Channel6)  || \

+                                               ((INSTANCE) == MDMA_Channel7)  || \

+                                               ((INSTANCE) == MDMA_Channel8)  || \

+                                               ((INSTANCE) == MDMA_Channel9)  || \

+                                               ((INSTANCE) == MDMA_Channel10) || \

+                                               ((INSTANCE) == MDMA_Channel11) || \

+                                               ((INSTANCE) == MDMA_Channel12) || \

+                                               ((INSTANCE) == MDMA_Channel13) || \

+                                               ((INSTANCE) == MDMA_Channel14) || \

+                                               ((INSTANCE) == MDMA_Channel15))

+

+/******************************* QUADSPI Instances *******************************/

+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)

+

+/******************************* FDCAN Instances ******************************/

+#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \

+                                             ((__INSTANCE__) == FDCAN2))

+

+#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)

+

+/******************************* GPIO Instances *******************************/

+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \

+                                        ((INSTANCE) == GPIOB) || \

+                                        ((INSTANCE) == GPIOC) || \

+                                        ((INSTANCE) == GPIOD) || \

+                                        ((INSTANCE) == GPIOE) || \

+                                        ((INSTANCE) == GPIOF) || \

+                                        ((INSTANCE) == GPIOG) || \

+                                        ((INSTANCE) == GPIOH) || \

+                                        ((INSTANCE) == GPIOI) || \

+                                        ((INSTANCE) == GPIOJ) || \

+                                        ((INSTANCE) == GPIOK))

+

+/******************************* GPIO AF Instances ****************************/

+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)

+

+/**************************** GPIO Lock Instances *****************************/

+/* On H7, all GPIO Bank support the Lock mechanism */

+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)

+

+/******************************** HSEM Instances *******************************/

+#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)

+#define HSEM_CPU1_COREID         (0x00000003U) /* Semaphore Core CM7 ID */

+#define HSEM_CR_COREID_CPU1      (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)

+#define HSEM_CR_COREID_CURRENT   (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)

+

+#define HSEM_SEMID_MIN     (0U)       /* HSEM ID Min*/

+#define HSEM_SEMID_MAX     (31U)      /* HSEM ID Max */

+

+#define HSEM_PROCESSID_MIN (0U)       /* HSEM Process ID Min */

+#define HSEM_PROCESSID_MAX (255U)     /* HSEM Process ID Max */

+

+#define HSEM_CLEAR_KEY_MIN (0U)       /* HSEM clear Key Min value */

+#define HSEM_CLEAR_KEY_MAX (0xFFFFU)  /* HSEM clear Key Max value */

+

+/******************************** I2C Instances *******************************/

+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

+                                       ((INSTANCE) == I2C2) || \

+                                       ((INSTANCE) == I2C3) || \

+                                       ((INSTANCE) == I2C4))

+/************** I2C Instances : wakeup capability from stop modes *************/

+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)

+

+/****************************** SMBUS Instances *******************************/

+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

+                                         ((INSTANCE) == I2C2) || \

+                                         ((INSTANCE) == I2C3) || \

+                                         ((INSTANCE) == I2C4))

+/******************************** I2S Instances *******************************/

+#define IS_I2S_ALL_INSTANCE(INSTANCE)   (((INSTANCE) == SPI1) || \

+                                         ((INSTANCE) == SPI2) || \

+                                         ((INSTANCE) == SPI3))

+

+/****************************** LTDC Instances ********************************/

+#define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)

+

+/******************************* RNG Instances ********************************/

+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)

+

+/****************************** RTC Instances *********************************/

+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)

+

+/****************************** SDMMC Instances *********************************/

+#define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \

+                                           ((_INSTANCE_) == SDMMC2))

+

+/******************************** SMBUS Instances *****************************/

+#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)

+

+/******************************** SPI Instances *******************************/

+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \

+                                       ((INSTANCE) == SPI2) || \

+                                       ((INSTANCE) == SPI3) || \

+                                       ((INSTANCE) == SPI4) || \

+                                       ((INSTANCE) == SPI5) || \

+                                       ((INSTANCE) == SPI6))

+

+#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \

+                                           ((INSTANCE) == SPI2) || \

+                                           ((INSTANCE) == SPI3))

+

+/******************************** SWPMI Instances *****************************/

+#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)

+

+/****************** LPTIM Instances : All supported instances *****************/

+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \

+                                         ((INSTANCE) == LPTIM2) || \

+                                         ((INSTANCE) == LPTIM3) || \

+                                         ((INSTANCE) == LPTIM4) || \

+                                         ((INSTANCE) == LPTIM5))

+

+/****************** LPTIM Instances : supporting encoder interface **************/

+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \

+                                                           ((INSTANCE) == LPTIM2))

+

+/****************** TIM Instances : All supported instances *******************/

+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM6)   || \

+                                         ((INSTANCE) == TIM7)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM13)  || \

+                                         ((INSTANCE) == TIM14)  || \

+                                         ((INSTANCE) == TIM15)  || \

+                                         ((INSTANCE) == TIM16)  || \

+                                         ((INSTANCE) == TIM17))

+

+/************* TIM Instances : at least 1 capture/compare channel *************/

+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM13)  || \

+                                         ((INSTANCE) == TIM14)  || \

+                                         ((INSTANCE) == TIM15)  || \

+                                         ((INSTANCE) == TIM16)  || \

+                                         ((INSTANCE) == TIM17))

+

+/************ TIM Instances : at least 2 capture/compare channels *************/

+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM15))

+

+/************ TIM Instances : at least 3 capture/compare channels *************/

+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8))

+

+/************ TIM Instances : at least 4 capture/compare channels *************/

+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8))

+

+/************ TIM Instances : at least 5 capture/compare channels *************/

+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM8))

+/************ TIM Instances : at least 6 capture/compare channels *************/

+#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM8))

+

+/******************** TIM Instances : Advanced-control timers *****************/

+#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \

+                                                ((__INSTANCE__) == TIM8))

+

+/******************** TIM Instances : Advanced-control timers *****************/

+

+/******************* TIM Instances : Timer input XOR function *****************/

+#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : DMA requests generation (UDE) *************/

+#define IS_TIM_DMA_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM6)   || \

+                                           ((INSTANCE) == TIM7)   || \

+                                           ((INSTANCE) == TIM8)   || \

+                                           ((INSTANCE) == TIM15)  || \

+                                           ((INSTANCE) == TIM16)  || \

+                                           ((INSTANCE) == TIM17))

+

+/************ TIM Instances : DMA requests generation (CCxDE) *****************/

+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15)  || \

+                                            ((INSTANCE) == TIM16)  || \

+                                            ((INSTANCE) == TIM17))

+

+/************ TIM Instances : DMA requests generation (COMDE) *****************/

+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15))

+

+/******************** TIM Instances : DMA burst feature ***********************/

+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8))

+

+/*************** TIM Instances : external trigger reamp input available *******/

+#define IS_TIM_ETR_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : remapping capability **********************/

+#define IS_TIM_REMAP_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \

+                                          ((INSTANCE) == TIM2)  || \

+                                          ((INSTANCE) == TIM3)  || \

+                                          ((INSTANCE) == TIM5)  || \

+                                          ((INSTANCE) == TIM8)  || \

+                                          ((INSTANCE) == TIM16) || \

+                                          ((INSTANCE) == TIM17))

+

+/*************** TIM Instances : external trigger reamp input available *******/

+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                              ((INSTANCE) == TIM2)   || \

+                                              ((INSTANCE) == TIM3)   || \

+                                              ((INSTANCE) == TIM5)   || \

+                                              ((INSTANCE) == TIM8))

+

+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/

+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM6)   || \

+                                            ((INSTANCE) == TIM7)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15))

+

+/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/

+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM8)   || \

+                                           ((INSTANCE) == TIM12))

+

+/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/

+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM8))

+

+/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/

+#define IS_TIM_TISEL_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)   || \

+                                          ((INSTANCE) == TIM2)   || \

+                                          ((INSTANCE) == TIM3)   || \

+                                          ((INSTANCE) == TIM4)   || \

+                                          ((INSTANCE) == TIM5)   || \

+                                          ((INSTANCE) == TIM8)   || \

+                                          ((INSTANCE) == TIM15)  || \

+                                          ((INSTANCE) == TIM16)  || \

+                                          ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting commutation event *************/

+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \

+                                                     ((INSTANCE) == TIM8)    || \

+                                                     ((INSTANCE) == TIM15)   || \

+                                                     ((INSTANCE) == TIM16)   || \

+                                                     ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting encoder interface **************/

+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1)  || \

+                                                      ((__INSTANCE__) == TIM2)      || \

+                                                      ((__INSTANCE__) == TIM3)      || \

+                                                      ((__INSTANCE__) == TIM4)      || \

+                                                      ((__INSTANCE__) == TIM5)      || \

+                                                      ((__INSTANCE__) == TIM8))

+

+/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/

+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                                       ((INSTANCE) == TIM8))

+/******************* TIM Instances : output(s) available **********************/

+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \

+    ((((INSTANCE) == TIM1) &&                  \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4) ||          \

+      ((CHANNEL) == TIM_CHANNEL_5) ||          \

+      ((CHANNEL) == TIM_CHANNEL_6)))           \

+     ||                                        \

+     (((INSTANCE) == TIM2) &&                  \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM3) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1)||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM4) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM5) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM8) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4) ||          \

+      ((CHANNEL) == TIM_CHANNEL_5) ||          \

+      ((CHANNEL) == TIM_CHANNEL_6)))           \

+  ||                                           \

+     (((INSTANCE) == TIM12) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2)))           \

+  ||                                           \

+     (((INSTANCE) == TIM13) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM14) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM15) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+     ((CHANNEL) == TIM_CHANNEL_2)))            \

+  ||                                           \

+     (((INSTANCE) == TIM16) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM17) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1))))

+

+/****************** TIM Instances : supporting the break function *************/

+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\

+      (((INSTANCE) == TIM1)    || \

+      ((INSTANCE) == TIM8)     || \

+       ((INSTANCE) == TIM15)   || \

+       ((INSTANCE) == TIM16)   || \

+       ((INSTANCE) == TIM17))

+

+/************** TIM Instances : supporting Break source selection *************/

+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \

+                                               ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting complementary output(s) ********/

+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \

+   ((((INSTANCE) == TIM1) &&                    \

+     (((CHANNEL) == TIM_CHANNEL_1) ||           \

+      ((CHANNEL) == TIM_CHANNEL_2) ||           \

+      ((CHANNEL) == TIM_CHANNEL_3)))            \

+ ||                                             \

+      (((INSTANCE) == TIM8) &&                  \

+      (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||           \

+      ((CHANNEL) == TIM_CHANNEL_3)))            \

+    ||                                          \

+    (((INSTANCE) == TIM15) &&                   \

+      ((CHANNEL) == TIM_CHANNEL_1))             \

+    ||                                          \

+    (((INSTANCE) == TIM16) &&                   \

+     ((CHANNEL) == TIM_CHANNEL_1))              \

+    ||                                          \

+    (((INSTANCE) == TIM17) &&                   \

+     ((CHANNEL) == TIM_CHANNEL_1)))

+

+/****************** TIM Instances : supporting counting mode selection ********/

+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting repetition counter *************/

+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15)   || \

+   ((INSTANCE) == TIM16)   || \

+   ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting synchronization ****************/

+#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\

+    (((__INSTANCE__) == TIM1)    || \

+     ((__INSTANCE__) == TIM2)    || \

+     ((__INSTANCE__) == TIM3)    || \

+     ((__INSTANCE__) == TIM4)    || \

+     ((__INSTANCE__) == TIM5)    || \

+     ((__INSTANCE__) == TIM6)    || \

+     ((__INSTANCE__) == TIM8)    || \

+     ((__INSTANCE__) == TIM12)   || \

+     ((__INSTANCE__) == TIM15))

+

+/****************** TIM Instances : supporting clock division *****************/

+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15)   || \

+   ((INSTANCE) == TIM16)   || \

+   ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting external clock mode 1 for ETRF input */

+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting external clock mode 2 **********/

+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\

+ (((INSTANCE) == TIM1)     || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/

+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/

+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : supporting OCxREF clear *******************/

+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3))

+

+/****************** TIM Instances : TIM_32B_COUNTER ***************************/

+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM5))

+

+/****************** TIM Instances : TIM_BKIN2 ***************************/

+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting Hall sensor interface **********/

+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)  || \

+                                                             ((__INSTANCE__) == TIM2)  || \

+                                                             ((__INSTANCE__) == TIM3)  || \

+                                                             ((__INSTANCE__) == TIM4)  || \

+                                                             ((__INSTANCE__) == TIM5)  || \

+                                                             ((__INSTANCE__) == TIM15) || \

+                                                             ((__INSTANCE__) == TIM8))

+

+/****************************** HRTIM Instances *******************************/

+#define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))

+

+/******************** USART Instances : Synchronous mode **********************/

+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                     ((INSTANCE) == USART2) || \

+                                     ((INSTANCE) == USART3) || \

+                                     ((INSTANCE) == USART6))

+

+/******************** USART Instances : SPI slave mode ************************/

+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                              ((INSTANCE) == USART2) || \

+                                              ((INSTANCE) == USART3) || \

+                                              ((INSTANCE) == USART6))

+

+/******************** UART Instances : Asynchronous mode **********************/

+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                    ((INSTANCE) == USART2) || \

+                                    ((INSTANCE) == USART3) || \

+                                    ((INSTANCE) == UART4)  || \

+                                    ((INSTANCE) == UART5)  || \

+                                    ((INSTANCE) == USART6) || \

+                                    ((INSTANCE) == UART7)  || \

+                                    ((INSTANCE) == UART8))

+

+/******************** UART Instances : FIFO mode.******************************/

+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                         ((INSTANCE) == USART2) || \

+                                         ((INSTANCE) == USART3) || \

+                                         ((INSTANCE) == UART4)  || \

+                                         ((INSTANCE) == UART5)  || \

+                                         ((INSTANCE) == USART6) || \

+                                         ((INSTANCE) == UART7)  || \

+                                         ((INSTANCE) == UART8))

+

+/****************** UART Instances : Auto Baud Rate detection *****************/

+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                            ((INSTANCE) == USART2) || \

+                                                            ((INSTANCE) == USART3) || \

+                                                            ((INSTANCE) == UART4)  || \

+                                                            ((INSTANCE) == UART5)  || \

+                                                            ((INSTANCE) == USART6) || \

+                                                            ((INSTANCE) == UART7)  || \

+                                                            ((INSTANCE) == UART8))

+

+/*********************** UART Instances : Driver Enable ***********************/

+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                  ((INSTANCE) == USART2) || \

+                                                  ((INSTANCE) == USART3) || \

+                                                  ((INSTANCE) == UART4)  || \

+                                                  ((INSTANCE) == UART5)  || \

+                                                  ((INSTANCE) == USART6) || \

+                                                  ((INSTANCE) == UART7)  || \

+                                                  ((INSTANCE) == UART8)  || \

+                                                  ((INSTANCE) == LPUART1))

+

+/********************* UART Instances : Half-Duplex mode **********************/

+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                               ((INSTANCE) == USART2) || \

+                                               ((INSTANCE) == USART3) || \

+                                               ((INSTANCE) == UART4)  || \

+                                               ((INSTANCE) == UART5)  || \

+                                               ((INSTANCE) == USART6) || \

+                                               ((INSTANCE) == UART7)  || \

+                                               ((INSTANCE) == UART8)  || \

+                                               ((INSTANCE) == LPUART1))

+

+/******************* UART Instances : Hardware Flow control *******************/

+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                           ((INSTANCE) == USART2) || \

+                                           ((INSTANCE) == USART3) || \

+                                           ((INSTANCE) == UART4)  || \

+                                           ((INSTANCE) == UART5)  || \

+                                           ((INSTANCE) == USART6) || \

+                                           ((INSTANCE) == UART7)  || \

+                                           ((INSTANCE) == UART8)  || \

+                                           ((INSTANCE) == LPUART1))

+

+/************************* UART Instances : LIN mode **************************/

+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                        ((INSTANCE) == USART2) || \

+                                        ((INSTANCE) == USART3) || \

+                                        ((INSTANCE) == UART4)  || \

+                                        ((INSTANCE) == UART5)  || \

+                                        ((INSTANCE) == USART6) || \

+                                        ((INSTANCE) == UART7)  || \

+                                        ((INSTANCE) == UART8))

+

+/****************** UART Instances : Wake-up from Stop mode *******************/

+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                    ((INSTANCE) == USART2) || \

+                                                    ((INSTANCE) == USART3) || \

+                                                    ((INSTANCE) == UART4)  || \

+                                                    ((INSTANCE) == UART5)  || \

+                                                    ((INSTANCE) == USART6) || \

+                                                    ((INSTANCE) == UART7)  || \

+                                                    ((INSTANCE) == UART8)  || \

+                                                    ((INSTANCE) == LPUART1))

+

+/************************* UART Instances : IRDA mode *************************/

+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                    ((INSTANCE) == USART2) || \

+                                    ((INSTANCE) == USART3) || \

+                                    ((INSTANCE) == UART4)  || \

+                                    ((INSTANCE) == UART5)  || \

+                                    ((INSTANCE) == USART6) || \

+                                    ((INSTANCE) == UART7)  || \

+                                    ((INSTANCE) == UART8))

+

+/********************* USART Instances : Smard card mode **********************/

+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                         ((INSTANCE) == USART2) || \

+                                         ((INSTANCE) == USART3) || \

+                                         ((INSTANCE) == USART6))

+

+/****************************** LPUART Instance *******************************/

+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)

+

+/****************************** IWDG Instances ********************************/

+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG1)

+/****************************** USB Instances ********************************/

+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)

+

+/****************************** WWDG Instances ********************************/

+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG1)

+/****************************** MDIOS Instances ********************************/

+#define IS_MDIOS_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == MDIOS)

+

+/****************************** CEC Instances *********************************/

+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)

+

+/****************************** SAI Instances ********************************/

+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \

+                    ((INSTANCE) == SAI1_Block_B) || \

+                     ((INSTANCE) == SAI2_Block_A) || \

+                     ((INSTANCE) == SAI2_Block_B) || \

+                     ((INSTANCE) == SAI3_Block_A) || \

+                     ((INSTANCE) == SAI3_Block_B) || \

+                     ((INSTANCE) == SAI4_Block_A) || \

+                     ((INSTANCE) == SAI4_Block_B))

+

+/****************************** SPDIFRX Instances ********************************/

+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)

+

+/****************************** OPAMP Instances *******************************/

+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \

+                                         ((INSTANCE) == OPAMP2))

+

+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)

+

+/*********************** USB OTG PCD Instances ********************************/

+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \

+                                        ((INSTANCE) == USB_OTG_HS))

+

+/*********************** USB OTG HCD Instances ********************************/

+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \

+                                       ((INSTANCE) == USB_OTG_HS))

+

+/******************************************************************************/

+/*  For a painless codes migration between the STM32H7xx device product       */

+/*  lines, or with STM32F7xx devices the aliases defined below are put        */

+/*   in place to overcome the differences in the interrupt handlers and IRQn  */

+/*   definitions. No need to update developed interrupt code when moving      */

+/*  across product lines within the same STM32H7 Family                       */

+/******************************************************************************/

+

+/* Aliases for __IRQn */

+#define  RNG_IRQn                       HASH_RNG_IRQn

+#define  TIM1_BRK_TIM9_IRQn             TIM1_BRK_IRQn

+#define  TIM1_UP_TIM10_IRQn             TIM1_UP_IRQn

+#define  TIM1_TRG_COM_TIM11_IRQn        TIM1_TRG_COM_IRQn

+#define  PVD_IRQn                       PVD_AVD_IRQn

+

+

+

+/* Aliases for __IRQHandler */

+#define   RNG_IRQHandler               HASH_RNG_IRQHandler

+#define TIM1_BRK_TIM9_IRQHandler       TIM1_BRK_IRQHandler

+#define TIM1_UP_TIM9_IRQHandler        TIM1_UP_IRQHandler

+#define TIM1_TRG_COM_TIM11_IRQHandler  TIM1_TRG_COM_IRQHandler

+#define PVD_IRQHandler                 PVD_AVD_IRQHandler

+

+/* Aliases for COMP __IRQHandler */

+#define COMP_IRQHandler                COMP1_IRQHandler

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif /* __cplusplus */

+

+#endif /* STM32H753xx_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h755xx.h b/bsps/arm/stm32h7/include/stm32h755xx.h
new file mode 100644
index 0000000000..cb8a590da2
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h755xx.h
@@ -0,0 +1,27348 @@
+/**

+  ******************************************************************************

+  * @file    stm32h755xx.h

+  * @author  MCD Application Team

+  * @brief   CMSIS STM32H755xx Device Peripheral Access Layer Header File.

+  *

+  *          This file contains:

+  *           - Data structures and the address mapping for all peripherals

+  *           - Peripheral's registers declarations and bits definition

+  *           - Macros to access peripheral's registers hardware

+  *

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/** @addtogroup CMSIS_Device

+  * @{

+  */

+

+/** @addtogroup stm32h755xx

+  * @{

+  */

+

+#ifndef STM32H755xx_H

+#define STM32H755xx_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif /* __cplusplus */

+

+/** @addtogroup Peripheral_interrupt_number_definition

+  * @{

+  */

+

+/**

+ * @brief STM32H7XX Interrupt Number Definition, according to the selected device

+ *        in @ref Library_configuration_section

+ */

+typedef enum

+{

+/******  Cortex-M Processor Exceptions Numbers *****************************************************************/

+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */

+  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */

+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */

+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */

+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */

+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M SV Call Interrupt                                     */

+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M Debug Monitor Interrupt                               */

+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M Pend SV Interrupt                                     */

+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M System Tick Interrupt                                 */

+/******  STM32 specific Interrupt Numbers **********************************************************************/

+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)                   */

+  PVD_AVD_IRQn                = 1,      /*!< PVD/AVD through EXTI Line detection Interrupt                     */

+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */

+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */

+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */

+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */

+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */

+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */

+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */

+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */

+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */

+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */

+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */

+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */

+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */

+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */

+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */

+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */

+  ADC_IRQn                    = 18,     /*!< ADC1 and  ADC2 global Interrupts                                  */

+  FDCAN1_IT0_IRQn             = 19,     /*!< FDCAN1 Interrupt line 0                                           */

+  FDCAN2_IT0_IRQn             = 20,     /*!< FDCAN2 Interrupt line 0                                           */

+  FDCAN1_IT1_IRQn             = 21,     /*!< FDCAN1 Interrupt line 1                                           */

+  FDCAN2_IT1_IRQn             = 22,     /*!< FDCAN2 Interrupt line 1                                           */

+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */

+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                              */

+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                             */

+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt                            */

+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */

+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */

+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */

+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */

+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */

+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */

+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */

+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */

+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */

+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */

+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */

+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */

+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */

+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */

+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */

+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */

+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */

+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */

+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */

+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */

+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */

+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */

+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */

+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */

+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */

+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */

+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */

+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */

+  DMA2_Stream0_IRQn           = 56,     /*!<   DMA2 Stream 0 global Interrupt                                  */

+  DMA2_Stream1_IRQn           = 57,     /*!<   DMA2 Stream 1 global Interrupt                                  */

+  DMA2_Stream2_IRQn           = 58,     /*!<   DMA2 Stream 2 global Interrupt                                  */

+  DMA2_Stream3_IRQn           = 59,     /*!<   DMA2 Stream 3 global Interrupt                                  */

+  DMA2_Stream4_IRQn           = 60,     /*!<   DMA2 Stream 4 global Interrupt                                  */

+  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */

+  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */

+  FDCAN_CAL_IRQn              = 63,     /*!< FDCAN Calibration unit Interrupt                                  */

+  CM7_SEV_IRQn                = 64,     /*!< CM7 Send event interrupt for CM4                                  */

+  CM4_SEV_IRQn                = 65,     /*!< CM4 Send event interrupt for CM7                                  */

+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */

+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */

+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */

+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */

+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */

+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */

+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */

+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */

+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */

+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */

+  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */

+  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */

+  HASH_RNG_IRQn               = 80,     /*!< HASH and RNG global interrupt                                     */

+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */

+  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */

+  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */

+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */

+  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */

+  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */

+  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */

+  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */

+  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */

+  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */

+  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */

+  QUADSPI_IRQn                = 92,     /*!< Quad SPI global interrupt                                         */

+  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */

+  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */

+  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */

+  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */

+  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */

+  OTG_FS_EP1_OUT_IRQn         = 98,     /*!< USB OTG HS2 global interrupt                                      */

+  OTG_FS_EP1_IN_IRQn          = 99,     /*!< USB OTG HS2 End Point 1 Out global interrupt                      */

+  OTG_FS_WKUP_IRQn            = 100,    /*!< USB OTG HS2 End Point 1 In global interrupt                       */

+  OTG_FS_IRQn                 = 101,    /*!< USB OTG HS2 Wakeup through EXTI interrupt                         */

+  DMAMUX1_OVR_IRQn            = 102,    /*!<DMAMUX1 Overrun interrupt                                          */

+  HRTIM1_Master_IRQn          = 103,    /*!< HRTIM Master Timer global Interrupts                              */

+  HRTIM1_TIMA_IRQn            = 104,    /*!< HRTIM Timer A global Interrupt                                    */

+  HRTIM1_TIMB_IRQn            = 105,    /*!< HRTIM Timer B global Interrupt                                    */

+  HRTIM1_TIMC_IRQn            = 106,    /*!< HRTIM Timer C global Interrupt                                    */

+  HRTIM1_TIMD_IRQn            = 107,    /*!< HRTIM Timer D global Interrupt                                    */

+  HRTIM1_TIME_IRQn            = 108,    /*!< HRTIM Timer E global Interrupt                                    */

+  HRTIM1_FLT_IRQn             = 109,    /*!< HRTIM Fault global Interrupt                                      */

+  DFSDM1_FLT0_IRQn            = 110,    /*!<DFSDM Filter1 Interrupt                                            */

+  DFSDM1_FLT1_IRQn            = 111,    /*!<DFSDM Filter2 Interrupt                                            */

+  DFSDM1_FLT2_IRQn            = 112,    /*!<DFSDM Filter3 Interrupt                                            */

+  DFSDM1_FLT3_IRQn            = 113,    /*!<DFSDM Filter4 Interrupt                                            */

+  SAI3_IRQn                   = 114,    /*!< SAI3 global Interrupt                                             */

+  SWPMI1_IRQn                 = 115,    /*!< Serial Wire Interface 1 global interrupt                          */

+  TIM15_IRQn                  = 116,    /*!< TIM15 global Interrupt                                            */

+  TIM16_IRQn                  = 117,    /*!< TIM16 global Interrupt                                            */

+  TIM17_IRQn                  = 118,    /*!< TIM17 global Interrupt                                            */

+  MDIOS_WKUP_IRQn             = 119,    /*!< MDIOS Wakeup  Interrupt                                           */

+  MDIOS_IRQn                  = 120,    /*!< MDIOS global Interrupt                                            */

+  JPEG_IRQn                   = 121,    /*!< JPEG global Interrupt                                             */

+  MDMA_IRQn                   = 122,    /*!< MDMA global Interrupt                                             */

+  SDMMC2_IRQn                 = 124,    /*!< SDMMC2 global Interrupt                                           */

+  HSEM1_IRQn                  = 125,    /*!< HSEM1 global Interrupt                                            */

+  HSEM2_IRQn                  = 126,    /*!< HSEM2 global Interrupt                                            */

+  ADC3_IRQn                   = 127,    /*!< ADC3 global Interrupt                                             */

+  DMAMUX2_OVR_IRQn            = 128,    /*!<DMAMUX2 Overrun interrupt                                          */

+  BDMA_Channel0_IRQn          = 129,    /*!< BDMA Channel 0 global Interrupt                                   */

+  BDMA_Channel1_IRQn          = 130,    /*!< BDMA Channel 1 global Interrupt                                   */

+  BDMA_Channel2_IRQn          = 131,    /*!< BDMA Channel 2 global Interrupt                                   */

+  BDMA_Channel3_IRQn          = 132,    /*!< BDMA Channel 3 global Interrupt                                   */

+  BDMA_Channel4_IRQn          = 133,    /*!< BDMA Channel 4 global Interrupt                                   */

+  BDMA_Channel5_IRQn          = 134,    /*!< BDMA Channel 5 global Interrupt                                   */

+  BDMA_Channel6_IRQn          = 135,    /*!< BDMA Channel 6 global Interrupt                                   */

+  BDMA_Channel7_IRQn          = 136,    /*!< BDMA Channel 7 global Interrupt                                   */

+  COMP_IRQn                   = 137 ,   /*!< COMP global Interrupt                                             */

+  LPTIM2_IRQn                 = 138,    /*!< LP TIM2 global interrupt                                          */

+  LPTIM3_IRQn                 = 139,    /*!< LP TIM3 global interrupt                                          */

+  LPTIM4_IRQn                 = 140,    /*!< LP TIM4 global interrupt                                          */

+  LPTIM5_IRQn                 = 141,    /*!< LP TIM5 global interrupt                                          */

+  LPUART1_IRQn                = 142,    /*!< LP UART1 interrupt                                                */

+  WWDG_RST_IRQn               = 143,    /*!<Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */

+  CRS_IRQn                    = 144,    /*!< Clock Recovery Global Interrupt                                   */

+  ECC_IRQn                    = 145,    /*!< ECC diagnostic Global Interrupt                                   */

+  SAI4_IRQn                   = 146,    /*!< SAI4 global interrupt                                             */

+  HOLD_CORE_IRQn              = 148,    /*!< Hold core interrupt                                               */

+  WAKEUP_PIN_IRQn             = 149,    /*!< Interrupt for all 6 wake-up pins                                  */

+} IRQn_Type;

+

+/**

+  * @}

+  */

+

+/** @addtogroup Configuration_section_for_CMSIS

+  * @{

+  */

+#define DUAL_CORE  /*!< Dual core line feature */

+

+#define SMPS       /*!< Switched mode power supply feature */

+

+

+

+/**

+  * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals

+   */

+#ifdef CORE_CM4

+#define __CM4_REV                 0x0001  /*!< Cortex-M4 revision r0p1                       */

+#define __MPU_PRESENT             1       /*!< CM4 provides an MPU                           */

+#define __NVIC_PRIO_BITS          4       /*!< CM4 uses 4 Bits for the Priority Levels       */

+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */

+#define __FPU_PRESENT             1       /*!< FPU present                                   */

+

+#include "core_cm4.h"                     /*!< Cortex-M4 processor and core peripherals      */

+#else  /* CORE_CM7 */

+#ifdef CORE_CM7

+#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */

+#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */

+#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */

+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */

+#define __FPU_PRESENT             1       /*!< FPU present                                   */

+#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */

+#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */

+#include "core_cm7.h"                 /*!< Cortex-M7 processor and core peripherals          */

+#else  /* UNKNOWN_CORE */

+#error Please #define CORE_CM4 or CORE_CM7

+#endif /* CORE_CM7 */

+#endif /* CORE_CM4 */

+

+/**

+  * @}

+  */

+

+

+

+

+

+#include "system_stm32h7xx.h"

+#include <stdint.h>

+

+/** @addtogroup Peripheral_registers_structures

+  * @{

+  */

+

+/**

+  * @brief Analog to Digital Converter

+  */

+

+typedef struct

+{

+  __IO uint32_t ISR;              /*!< ADC Interrupt and Status Register,                          Address offset: 0x00 */

+  __IO uint32_t IER;              /*!< ADC Interrupt Enable Register,                              Address offset: 0x04 */

+  __IO uint32_t CR;               /*!< ADC control register,                                       Address offset: 0x08 */

+  __IO uint32_t CFGR;             /*!< ADC Configuration register,                                 Address offset: 0x0C */

+  __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                               Address offset: 0x10 */

+  __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                                 Address offset: 0x14 */

+  __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                                 Address offset: 0x18 */

+  __IO uint32_t PCSEL;            /*!< ADC pre-channel selection,                                  Address offset: 0x1C */

+  __IO uint32_t LTR1;             /*!< ADC watchdog Lower threshold register 1,                    Address offset: 0x20 */

+  __IO uint32_t HTR1;             /*!< ADC watchdog higher threshold register 1,                   Address offset: 0x24 */

+  uint32_t      RESERVED1;        /*!< Reserved, 0x028                                                                  */

+  uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                                  */

+  __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                            Address offset: 0x30 */

+  __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                            Address offset: 0x34 */

+  __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                            Address offset: 0x38 */

+  __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                            Address offset: 0x3C */

+  __IO uint32_t DR;               /*!< ADC regular data register,                                  Address offset: 0x40 */

+  uint32_t      RESERVED3;        /*!< Reserved, 0x044                                                                  */

+  uint32_t      RESERVED4;        /*!< Reserved, 0x048                                                                  */

+  __IO uint32_t JSQR;             /*!< ADC injected sequence register,                             Address offset: 0x4C */

+  uint32_t      RESERVED5[4];     /*!< Reserved, 0x050 - 0x05C                                                          */

+  __IO uint32_t OFR1;             /*!< ADC offset register 1,                                      Address offset: 0x60 */

+  __IO uint32_t OFR2;             /*!< ADC offset register 2,                                      Address offset: 0x64 */

+  __IO uint32_t OFR3;             /*!< ADC offset register 3,                                      Address offset: 0x68 */

+  __IO uint32_t OFR4;             /*!< ADC offset register 4,                                      Address offset: 0x6C */

+  uint32_t      RESERVED6[4];     /*!< Reserved, 0x070 - 0x07C                                                          */

+  __IO uint32_t JDR1;             /*!< ADC injected data register 1,                               Address offset: 0x80 */

+  __IO uint32_t JDR2;             /*!< ADC injected data register 2,                               Address offset: 0x84 */

+  __IO uint32_t JDR3;             /*!< ADC injected data register 3,                               Address offset: 0x88 */

+  __IO uint32_t JDR4;             /*!< ADC injected data register 4,                               Address offset: 0x8C */

+  uint32_t      RESERVED7[4];     /*!< Reserved, 0x090 - 0x09C                                                          */

+  __IO uint32_t AWD2CR;           /*!< ADC  Analog Watchdog 2 Configuration Register,              Address offset: 0xA0 */

+  __IO uint32_t AWD3CR;           /*!< ADC  Analog Watchdog 3 Configuration Register,              Address offset: 0xA4 */

+  uint32_t      RESERVED8;        /*!< Reserved, 0x0A8                                                                  */

+  uint32_t      RESERVED9;        /*!< Reserved, 0x0AC                                                                  */

+  __IO uint32_t LTR2;             /*!< ADC watchdog Lower threshold register 2,                    Address offset: 0xB0 */

+  __IO uint32_t HTR2;             /*!< ADC watchdog Higher threshold register 2,                   Address offset: 0xB4 */

+  __IO uint32_t LTR3;             /*!< ADC watchdog Lower threshold register 3,                    Address offset: 0xB8 */

+  __IO uint32_t HTR3;             /*!< ADC watchdog Higher threshold register 3,                   Address offset: 0xBC */

+  __IO uint32_t DIFSEL;           /*!< ADC  Differential Mode Selection Register,                  Address offset: 0xC0 */

+  __IO uint32_t CALFACT;          /*!< ADC  Calibration Factors,                                   Address offset: 0xC4 */

+  __IO uint32_t CALFACT2;         /*!< ADC  Linearity Calibration Factors,                         Address offset: 0xC8 */

+} ADC_TypeDef;

+

+

+typedef struct

+{

+__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */

+uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */

+__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */

+__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */

+__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */

+

+} ADC_Common_TypeDef;

+

+/**

+  * @brief ART

+  */

+

+typedef struct

+{

+  __IO uint32_t  CTR;        /*!< ART accelerator - control register */

+}ART_TypeDef;

+

+/**

+  * @brief VREFBUF

+  */

+

+typedef struct

+{

+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */

+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */

+} VREFBUF_TypeDef;

+

+

+/**

+  * @brief FD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */

+  __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */

+  __IO uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */

+  __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */

+  __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */

+  __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */

+  __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */

+  __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */

+  __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */

+  __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */

+  __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */

+  __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */

+  __IO uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */

+  __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */

+  __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */

+  __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */

+  __IO uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */

+  __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */

+  __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */

+  __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */

+  __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */

+  __IO uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */

+  __IO uint32_t GFC;          /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */

+  __IO uint32_t SIDFC;        /*!< FDCAN Standard ID Filter Configuration register,                 Address offset: 0x084 */

+  __IO uint32_t XIDFC;        /*!< FDCAN Extended ID Filter Configuration register,                 Address offset: 0x088 */

+  __IO uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */

+  __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x090 */

+  __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x094 */

+  __IO uint32_t NDAT1;        /*!< FDCAN New Data 1 register,                                       Address offset: 0x098 */

+  __IO uint32_t NDAT2;        /*!< FDCAN New Data 2 register,                                       Address offset: 0x09C */

+  __IO uint32_t RXF0C;        /*!< FDCAN Rx FIFO 0 Configuration register,                          Address offset: 0x0A0 */

+  __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x0A4 */

+  __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x0A8 */

+  __IO uint32_t RXBC;         /*!< FDCAN Rx Buffer Configuration register,                          Address offset: 0x0AC */

+  __IO uint32_t RXF1C;        /*!< FDCAN Rx FIFO 1 Configuration register,                          Address offset: 0x0B0 */

+  __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x0B4 */

+  __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x0B8 */

+  __IO uint32_t RXESC;        /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register,        Address offset: 0x0BC */

+  __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */

+  __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */

+  __IO uint32_t TXESC;        /*!< FDCAN Tx Buffer Element Size Configuration register,             Address offset: 0x0C8 */

+  __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0CC */

+  __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0D0 */

+  __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D4 */

+  __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D8 */

+  __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0DC */

+  __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0E0 */

+  __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */

+  __IO uint32_t RESERVED6[2]; /*!< Reserved,                                                                0x0E8 - 0x0EC */

+  __IO uint32_t TXEFC;        /*!< FDCAN Tx Event FIFO Configuration register,                      Address offset: 0x0F0 */

+  __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0F4 */

+  __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0F8 */

+  __IO uint32_t RESERVED7;    /*!< Reserved,                                                                        0x0FC */

+} FDCAN_GlobalTypeDef;

+

+/**

+  * @brief TTFD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t TTTMC;          /*!< TT Trigger Memory Configuration register,    Address offset: 0x100 */

+  __IO uint32_t TTRMC;          /*!< TT Reference Message Configuration register, Address offset: 0x104 */

+  __IO uint32_t TTOCF;          /*!< TT Operation Configuration register,         Address offset: 0x108 */

+  __IO uint32_t TTMLM;          /*!< TT Matrix Limits register,                   Address offset: 0x10C */

+  __IO uint32_t TURCF;          /*!< TUR Configuration register,                  Address offset: 0x110 */

+  __IO uint32_t TTOCN;          /*!< TT Operation Control register,               Address offset: 0x114 */

+  __IO uint32_t TTGTP;          /*!< TT Global Time Preset register,              Address offset: 0x118 */

+  __IO uint32_t TTTMK;          /*!< TT Time Mark register,                       Address offset: 0x11C */

+  __IO uint32_t TTIR;           /*!< TT Interrupt register,                       Address offset: 0x120 */

+  __IO uint32_t TTIE;           /*!< TT Interrupt Enable register,                Address offset: 0x124 */

+  __IO uint32_t TTILS;          /*!< TT Interrupt Line Select register,           Address offset: 0x128 */

+  __IO uint32_t TTOST;          /*!< TT Operation Status register,                Address offset: 0x12C */

+  __IO uint32_t TURNA;          /*!< TT TUR Numerator Actual register,            Address offset: 0x130 */

+  __IO uint32_t TTLGT;          /*!< TT Local and Global Time register,           Address offset: 0x134 */

+  __IO uint32_t TTCTC;          /*!< TT Cycle Time and Count register,            Address offset: 0x138 */

+  __IO uint32_t TTCPT;          /*!< TT Capture Time register,                    Address offset: 0x13C */

+  __IO uint32_t TTCSM;          /*!< TT Cycle Sync Mark register,                 Address offset: 0x140 */

+  __IO uint32_t RESERVED1[111]; /*!< Reserved,                                            0x144 - 0x2FC */

+  __IO uint32_t TTTS;           /*!< TT Trigger Select register,                  Address offset: 0x300 */

+} TTCAN_TypeDef;

+

+/**

+  * @brief FD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t CREL;  /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */

+  __IO uint32_t CCFG;  /*!< Calibration Configuration register,           Address offset: 0x04 */

+  __IO uint32_t CSTAT; /*!< Calibration Status register,                  Address offset: 0x08 */

+  __IO uint32_t CWD;   /*!< Calibration Watchdog register,                Address offset: 0x0C */

+  __IO uint32_t IR;    /*!< CCU Interrupt register,                       Address offset: 0x10 */

+  __IO uint32_t IE;    /*!< CCU Interrupt Enable register,                Address offset: 0x14 */

+} FDCAN_ClockCalibrationUnit_TypeDef;

+

+

+/**

+  * @brief Consumer Electronics Control

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;           /*!< CEC control register,              Address offset:0x00 */

+  __IO uint32_t CFGR;         /*!< CEC configuration register,        Address offset:0x04 */

+  __IO uint32_t TXDR;         /*!< CEC Tx data register ,             Address offset:0x08 */

+  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,              Address offset:0x0C */

+  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register, Address offset:0x10 */

+  __IO uint32_t IER;          /*!< CEC interrupt enable register,     Address offset:0x14 */

+}CEC_TypeDef;

+

+/**

+  * @brief CRC calculation unit

+  */

+

+typedef struct

+{

+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */

+  __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */

+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */

+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */

+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */

+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */

+} CRC_TypeDef;

+

+

+/**

+  * @brief Clock Recovery System

+  */

+typedef struct

+{

+__IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */

+__IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */

+__IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */

+__IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */

+} CRS_TypeDef;

+

+

+/**

+  * @brief Digital to Analog Converter

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */

+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */

+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */

+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */

+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */

+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */

+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */

+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */

+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */

+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */

+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */

+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */

+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */

+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */

+  __IO uint32_t CCR;      /*!< DAC calibration control register,                        Address offset: 0x38 */

+  __IO uint32_t MCR;      /*!< DAC mode control register,                               Address offset: 0x3C */

+  __IO uint32_t SHSR1;    /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */

+  __IO uint32_t SHSR2;    /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */

+  __IO uint32_t SHHR;     /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */

+  __IO uint32_t SHRR;     /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */

+} DAC_TypeDef;

+

+/**

+  * @brief DFSDM module registers

+  */

+typedef struct

+{

+  __IO uint32_t FLTCR1;          /*!< DFSDM control register1,                          Address offset: 0x100 */

+  __IO uint32_t FLTCR2;          /*!< DFSDM control register2,                          Address offset: 0x104 */

+  __IO uint32_t FLTISR;          /*!< DFSDM interrupt and status register,              Address offset: 0x108 */

+  __IO uint32_t FLTICR;          /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */

+  __IO uint32_t FLTJCHGR;        /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */

+  __IO uint32_t FLTFCR;          /*!< DFSDM filter control register,                    Address offset: 0x114 */

+  __IO uint32_t FLTJDATAR;       /*!< DFSDM data register for injected group,           Address offset: 0x118 */

+  __IO uint32_t FLTRDATAR;       /*!< DFSDM data register for regular group,            Address offset: 0x11C */

+  __IO uint32_t FLTAWHTR;        /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */

+  __IO uint32_t FLTAWLTR;        /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */

+  __IO uint32_t FLTAWSR;         /*!< DFSDM analog watchdog status register             Address offset: 0x128 */

+  __IO uint32_t FLTAWCFR;        /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */

+  __IO uint32_t FLTEXMAX;        /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */

+  __IO uint32_t FLTEXMIN;        /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */

+  __IO uint32_t FLTCNVTIMR;      /*!< DFSDM conversion timer,                           Address offset: 0x138 */

+} DFSDM_Filter_TypeDef;

+

+/**

+  * @brief DFSDM channel configuration registers

+  */

+typedef struct

+{

+  __IO uint32_t CHCFGR1;      /*!< DFSDM channel configuration register1,            Address offset: 0x00 */

+  __IO uint32_t CHCFGR2;      /*!< DFSDM channel configuration register2,            Address offset: 0x04 */

+  __IO uint32_t CHAWSCDR;     /*!< DFSDM channel analog watchdog and

+                                   short circuit detector register,                  Address offset: 0x08 */

+  __IO uint32_t CHWDATAR;     /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */

+  __IO uint32_t CHDATINR;     /*!< DFSDM channel data input register,                Address offset: 0x10 */

+} DFSDM_Channel_TypeDef;

+

+/**

+  * @brief Debug MCU

+  */

+typedef struct

+{

+  __IO uint32_t IDCODE;        /*!< MCU device ID code,                     Address offset: 0x00 */

+  __IO uint32_t CR;            /*!< Debug MCU configuration register,       Address offset: 0x04 */

+  __IO uint32_t  RESERVED4[11]; /*!< Reserved,                               Address offset: 0x08 */

+  __IO uint32_t APB3FZ1;     /*!< Debug MCU APB3FZ1 freeze register,    Address offset: 0x34 */

+  __IO uint32_t APB3FZ2;     /*!< Debug MCU APB3FZ2 freeze register,    Address offset: 0x38 */

+  __IO uint32_t APB1LFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x3C */

+  __IO uint32_t APB1LFZ2;    /*!< Debug MCU APB1LFZ2 freeze register,   Address offset: 0x40 */

+  __IO uint32_t APB1HFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x44 */

+  __IO uint32_t APB1HFZ2;    /*!< Debug MCU APB1LFZ2 freeze register,   Address offset: 0x48 */

+  __IO uint32_t APB2FZ1;     /*!< Debug MCU APB2FZ1 freeze register,    Address offset: 0x4C */

+  __IO uint32_t APB2FZ2;     /*!< Debug MCU APB2FZ2 freeze register,    Address offset: 0x50 */

+  __IO uint32_t APB4FZ1;     /*!< Debug MCU APB4FZ1 freeze register,    Address offset: 0x54 */

+  __IO uint32_t APB4FZ2;     /*!< Debug MCU APB4FZ2 freeze register,    Address offset: 0x58 */

+

+}DBGMCU_TypeDef;

+/**

+  * @brief DCMI

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */

+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */

+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */

+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */

+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */

+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */

+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */

+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */

+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */

+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */

+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */

+} DCMI_TypeDef;

+

+/**

+  * @brief DMA Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */

+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */

+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */

+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */

+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */

+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */

+} DMA_Stream_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */

+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */

+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */

+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */

+} DMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CCR;          /*!< DMA channel x configuration register          */

+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register         */

+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register     */

+  __IO uint32_t CM0AR;        /*!< DMA channel x memory 0 address register       */

+  __IO uint32_t CM1AR;        /*!< DMA channel x memory 1 address register       */

+} BDMA_Channel_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */

+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */

+} BDMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CCR;        /*!< DMA Multiplexer Channel x Control Register   */

+}DMAMUX_Channel_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CSR;      /*!< DMA Channel Status Register     */

+  __IO uint32_t  CFR;      /*!< DMA Channel Clear Flag Register */

+}DMAMUX_ChannelStatus_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  RGCR;        /*!< DMA Request Generator x Control Register   */

+}DMAMUX_RequestGen_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  RGSR;        /*!< DMA Request Generator Status Register       */

+  __IO uint32_t  RGCFR;       /*!< DMA Request Generator Clear Flag Register   */

+}DMAMUX_RequestGenStatus_TypeDef;

+

+/**

+  * @brief MDMA Controller

+  */

+typedef struct

+{

+  __IO uint32_t  GISR0;   /*!< MDMA Global Interrupt/Status Register 0,          Address offset: 0x00 */

+}MDMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CISR;      /*!< MDMA channel x interrupt/status register,             Address offset: 0x40 */

+  __IO uint32_t  CIFCR;     /*!< MDMA channel x interrupt flag clear register,         Address offset: 0x44 */

+  __IO uint32_t  CESR;      /*!< MDMA Channel x error status register,                 Address offset: 0x48 */

+  __IO uint32_t  CCR;       /*!< MDMA channel x control register,                      Address offset: 0x4C */

+  __IO uint32_t  CTCR;      /*!< MDMA channel x Transfer Configuration register,       Address offset: 0x50 */

+  __IO uint32_t  CBNDTR;    /*!< MDMA Channel x block number of data register,         Address offset: 0x54 */

+  __IO uint32_t  CSAR;      /*!< MDMA channel x source address register,               Address offset: 0x58 */

+  __IO uint32_t  CDAR;      /*!< MDMA channel x destination address register,          Address offset: 0x5C */

+  __IO uint32_t  CBRUR;     /*!< MDMA channel x Block Repeat address Update register,  Address offset: 0x60 */

+  __IO uint32_t  CLAR;      /*!< MDMA channel x Link Address register,                 Address offset: 0x64 */

+  __IO uint32_t  CTBR;      /*!< MDMA channel x Trigger and Bus selection Register,    Address offset: 0x68 */

+  uint32_t       RESERVED0; /*!< Reserved, 0x68                                                             */

+  __IO uint32_t  CMAR;      /*!< MDMA channel x Mask address register,                 Address offset: 0x70 */

+  __IO uint32_t  CMDR;      /*!< MDMA channel x Mask Data register,                    Address offset: 0x74 */

+}MDMA_Channel_TypeDef;

+

+/**

+  * @brief DMA2D Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */

+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */

+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */

+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */

+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */

+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */

+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */

+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */

+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */

+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */

+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */

+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */

+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */

+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */

+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */

+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */

+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */

+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */

+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */

+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */

+  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */

+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */

+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */

+} DMA2D_TypeDef;

+

+

+/**

+  * @brief Ethernet MAC

+  */

+typedef struct

+{

+  __IO uint32_t MACCR;

+  __IO uint32_t MACECR;

+  __IO uint32_t MACPFR;

+  __IO uint32_t MACWTR;

+  __IO uint32_t MACHT0R;

+  __IO uint32_t MACHT1R;

+  uint32_t      RESERVED1[14];

+  __IO uint32_t MACVTR;

+  uint32_t      RESERVED2;

+  __IO uint32_t MACVHTR;

+  uint32_t      RESERVED3;

+  __IO uint32_t MACVIR;

+  __IO uint32_t MACIVIR;

+  uint32_t      RESERVED4[2];

+  __IO uint32_t MACTFCR;

+  uint32_t      RESERVED5[7];

+  __IO uint32_t MACRFCR;

+  uint32_t      RESERVED6[7];

+  __IO uint32_t MACISR;

+  __IO uint32_t MACIER;

+  __IO uint32_t MACRXTXSR;

+  uint32_t      RESERVED7;

+  __IO uint32_t MACPCSR;

+  __IO uint32_t MACRWKPFR;

+  uint32_t      RESERVED8[2];

+  __IO uint32_t MACLCSR;

+  __IO uint32_t MACLTCR;

+  __IO uint32_t MACLETR;

+  __IO uint32_t MAC1USTCR;

+  uint32_t      RESERVED9[12];

+  __IO uint32_t MACVR;

+  __IO uint32_t MACDR;

+  uint32_t      RESERVED10;

+  __IO uint32_t MACHWF0R;

+  __IO uint32_t MACHWF1R;

+  __IO uint32_t MACHWF2R;

+  uint32_t      RESERVED11[54];

+  __IO uint32_t MACMDIOAR;

+  __IO uint32_t MACMDIODR;

+  uint32_t      RESERVED12[2];

+  __IO uint32_t MACARPAR;

+  uint32_t      RESERVED13[59];

+  __IO uint32_t MACA0HR;

+  __IO uint32_t MACA0LR;

+  __IO uint32_t MACA1HR;

+  __IO uint32_t MACA1LR;

+  __IO uint32_t MACA2HR;

+  __IO uint32_t MACA2LR;

+  __IO uint32_t MACA3HR;

+  __IO uint32_t MACA3LR;

+  uint32_t      RESERVED14[248];

+  __IO uint32_t MMCCR;

+  __IO uint32_t MMCRIR;

+  __IO uint32_t MMCTIR;

+  __IO uint32_t MMCRIMR;

+  __IO uint32_t MMCTIMR;

+  uint32_t      RESERVED15[14];

+  __IO uint32_t MMCTSCGPR;

+  __IO uint32_t MMCTMCGPR;

+  uint32_t      RESERVED16[5];

+  __IO uint32_t MMCTPCGR;

+  uint32_t      RESERVED17[10];

+  __IO uint32_t MMCRCRCEPR;

+  __IO uint32_t MMCRAEPR;

+  uint32_t      RESERVED18[10];

+  __IO uint32_t MMCRUPGR;

+  uint32_t      RESERVED19[9];

+  __IO uint32_t MMCTLPIMSTR;

+  __IO uint32_t MMCTLPITCR;

+  __IO uint32_t MMCRLPIMSTR;

+  __IO uint32_t MMCRLPITCR;

+  uint32_t      RESERVED20[65];

+  __IO uint32_t MACL3L4C0R;

+  __IO uint32_t MACL4A0R;

+  uint32_t      RESERVED21[2];

+  __IO uint32_t MACL3A0R0R;

+  __IO uint32_t MACL3A1R0R;

+  __IO uint32_t MACL3A2R0R;

+  __IO uint32_t MACL3A3R0R;

+  uint32_t      RESERVED22[4];

+  __IO uint32_t MACL3L4C1R;

+  __IO uint32_t MACL4A1R;

+  uint32_t      RESERVED23[2];

+  __IO uint32_t MACL3A0R1R;

+  __IO uint32_t MACL3A1R1R;

+  __IO uint32_t MACL3A2R1R;

+  __IO uint32_t MACL3A3R1R;

+  uint32_t      RESERVED24[108];

+  __IO uint32_t MACTSCR;

+  __IO uint32_t MACSSIR;

+  __IO uint32_t MACSTSR;

+  __IO uint32_t MACSTNR;

+  __IO uint32_t MACSTSUR;

+  __IO uint32_t MACSTNUR;

+  __IO uint32_t MACTSAR;

+  uint32_t      RESERVED25;

+  __IO uint32_t MACTSSR;

+  uint32_t      RESERVED26[3];

+  __IO uint32_t MACTTSSNR;

+  __IO uint32_t MACTTSSSR;

+  uint32_t      RESERVED27[2];

+  __IO uint32_t MACACR;

+  uint32_t      RESERVED28;

+  __IO uint32_t MACATSNR;

+  __IO uint32_t MACATSSR;

+  __IO uint32_t MACTSIACR;

+  __IO uint32_t MACTSEACR;

+  __IO uint32_t MACTSICNR;

+  __IO uint32_t MACTSECNR;

+  uint32_t      RESERVED29[4];

+  __IO uint32_t MACPPSCR;

+  uint32_t      RESERVED30[3];

+  __IO uint32_t MACPPSTTSR;

+  __IO uint32_t MACPPSTTNR;

+  __IO uint32_t MACPPSIR;

+  __IO uint32_t MACPPSWR;

+  uint32_t      RESERVED31[12];

+  __IO uint32_t MACPOCR;

+  __IO uint32_t MACSPI0R;

+  __IO uint32_t MACSPI1R;

+  __IO uint32_t MACSPI2R;

+  __IO uint32_t MACLMIR;

+  uint32_t      RESERVED32[11];

+  __IO uint32_t MTLOMR;

+  uint32_t      RESERVED33[7];

+  __IO uint32_t MTLISR;

+  uint32_t      RESERVED34[55];

+  __IO uint32_t MTLTQOMR;

+  __IO uint32_t MTLTQUR;

+  __IO uint32_t MTLTQDR;

+  uint32_t      RESERVED35[8];

+  __IO uint32_t MTLQICSR;

+  __IO uint32_t MTLRQOMR;

+  __IO uint32_t MTLRQMPOCR;

+  __IO uint32_t MTLRQDR;

+  uint32_t      RESERVED36[177];

+  __IO uint32_t DMAMR;

+  __IO uint32_t DMASBMR;

+  __IO uint32_t DMAISR;

+  __IO uint32_t DMADSR;

+  uint32_t      RESERVED37[60];

+  __IO uint32_t DMACCR;

+  __IO uint32_t DMACTCR;

+  __IO uint32_t DMACRCR;

+  uint32_t      RESERVED38[2];

+  __IO uint32_t DMACTDLAR;

+  uint32_t      RESERVED39;

+  __IO uint32_t DMACRDLAR;

+  __IO uint32_t DMACTDTPR;

+  uint32_t      RESERVED40;

+  __IO uint32_t DMACRDTPR;

+  __IO uint32_t DMACTDRLR;

+  __IO uint32_t DMACRDRLR;

+  __IO uint32_t DMACIER;

+  __IO uint32_t DMACRIWTR;

+__IO uint32_t DMACSFCSR;

+  uint32_t      RESERVED41;

+  __IO uint32_t DMACCATDR;

+  uint32_t      RESERVED42;

+  __IO uint32_t DMACCARDR;

+  uint32_t      RESERVED43;

+  __IO uint32_t DMACCATBR;

+  uint32_t      RESERVED44;

+  __IO uint32_t DMACCARBR;

+  __IO uint32_t DMACSR;

+uint32_t      RESERVED45[2];

+__IO uint32_t DMACMFCR;

+}ETH_TypeDef;

+/**

+  * @brief External Interrupt/Event Controller

+  */

+

+typedef struct

+{

+__IO uint32_t RTSR1;               /*!< EXTI Rising trigger selection register,          Address offset: 0x00 */

+__IO uint32_t FTSR1;               /*!< EXTI Falling trigger selection register,         Address offset: 0x04 */

+__IO uint32_t SWIER1;              /*!< EXTI Software interrupt event register,          Address offset: 0x08 */

+__IO uint32_t D3PMR1;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */

+__IO uint32_t D3PCR1L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L)     Address offset: 0x10 */

+__IO uint32_t D3PCR1H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H)   Address offset: 0x14 */

+uint32_t      RESERVED1[2];        /*!< Reserved,                                        0x18 to 0x1C         */

+__IO uint32_t RTSR2;               /*!< EXTI Rising trigger selection register,          Address offset: 0x20 */

+__IO uint32_t FTSR2;               /*!< EXTI Falling trigger selection register,         Address offset: 0x24 */

+__IO uint32_t SWIER2;              /*!< EXTI Software interrupt event register,          Address offset: 0x28 */

+__IO uint32_t D3PMR2;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */

+__IO uint32_t D3PCR2L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L)  Address offset: 0x30 */

+__IO uint32_t D3PCR2H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */

+uint32_t      RESERVED2[2];        /*!< Reserved,                                        0x38 to 0x3C         */

+__IO uint32_t RTSR3;               /*!< EXTI Rising trigger selection register,          Address offset: 0x40 */

+__IO uint32_t FTSR3;               /*!< EXTI Falling trigger selection register,         Address offset: 0x44 */

+__IO uint32_t SWIER3;              /*!< EXTI Software interrupt event register,          Address offset: 0x48 */

+__IO uint32_t D3PMR3;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */

+__IO uint32_t D3PCR3L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */

+__IO uint32_t D3PCR3H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */

+uint32_t      RESERVED3[10];       /*!< Reserved,                                        0x58 to 0x7C         */

+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                    Address offset: 0x80 */

+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                        Address offset: 0x84 */

+__IO uint32_t PR1;                 /*!< EXTI Pending register,                           Address offset: 0x88 */

+uint32_t      RESERVED4;           /*!< Reserved,                                        0x8C                 */

+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                    Address offset: 0x90 */

+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                        Address offset: 0x94 */

+__IO uint32_t PR2;                 /*!< EXTI Pending register,                           Address offset: 0x98 */

+uint32_t      RESERVED5;           /*!< Reserved,                                        0x9C                 */

+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                    Address offset: 0xA0 */

+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                        Address offset: 0xA4 */

+__IO uint32_t PR3;                 /*!< EXTI Pending register,                           Address offset: 0xA8 */

+uint32_t      RESERVED6[5];        /*!< Reserved,                                        0xAC to 0xBC         */

+__IO uint32_t C2IMR1;              /*!< EXTI Interrupt mask register,                    Address offset: 0xC0 */

+__IO uint32_t C2EMR1;              /*!< EXTI Event mask register,                        Address offset: 0xC4 */

+__IO uint32_t C2PR1;               /*!< EXTI Pending register,                           Address offset: 0xC8 */

+uint32_t      RESERVED7;           /*!< Reserved,                                        0xCC                 */

+__IO uint32_t C2IMR2;              /*!< EXTI Interrupt mask register,                    Address offset: 0xD0 */

+__IO uint32_t C2EMR2;              /*!< EXTI Event mask register,                        Address offset: 0xD4 */

+__IO uint32_t C2PR2;               /*!< EXTI Pending register,                           Address offset: 0xD8 */

+uint32_t      RESERVED8;           /*!< Reserved,                                        0xDC                 */

+__IO uint32_t C2IMR3;              /*!< EXTI Interrupt mask register,                    Address offset: 0xE0 */

+__IO uint32_t C2EMR3;              /*!< EXTI Event mask register,                        Address offset: 0xE4 */

+__IO uint32_t C2PR3;               /*!< EXTI Pending register,                           Address offset: 0xE8 */

+

+}EXTI_TypeDef;

+

+typedef struct

+{

+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                Address offset: 0x00 */

+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                    Address offset: 0x04 */

+__IO uint32_t PR1;                 /*!< EXTI Pending register,                       Address offset: 0x08 */

+uint32_t      RESERVED1;           /*!< Reserved, 0x0C                                                    */

+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                Address offset: 0x10 */

+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                    Address offset: 0x14 */

+__IO uint32_t PR2;                 /*!< EXTI Pending register,                       Address offset: 0x18 */

+uint32_t      RESERVED2;           /*!< Reserved, 0x1C                                                    */

+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                Address offset: 0x20 */

+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                    Address offset: 0x24 */

+__IO uint32_t PR3;                 /*!< EXTI Pending register,                       Address offset: 0x28 */

+}EXTI_Core_TypeDef;

+

+

+/**

+  * @brief FLASH Registers

+  */

+

+typedef struct

+{

+  __IO uint32_t ACR;             /*!< FLASH access control register,                            Address offset: 0x00  */

+  __IO uint32_t KEYR1;           /*!< Flash Key Register for bank1,                             Address offset: 0x04  */

+  __IO uint32_t OPTKEYR;         /*!< Flash Option Key Register,                                Address offset: 0x08  */

+  __IO uint32_t CR1;             /*!< Flash Control Register for bank1,                         Address offset: 0x0C  */

+  __IO uint32_t SR1;             /*!< Flash Status Register for bank1,                          Address offset: 0x10  */

+  __IO uint32_t CCR1;            /*!< Flash Control Register for bank1,                         Address offset: 0x14  */

+  __IO uint32_t OPTCR;           /*!< Flash Option Control Register,                            Address offset: 0x18  */

+  __IO uint32_t OPTSR_CUR;       /*!< Flash Option Status Current Register,                     Address offset: 0x1C  */

+  __IO uint32_t OPTSR_PRG;       /*!< Flash Option Status to Program Register,                  Address offset: 0x20  */

+  __IO uint32_t OPTCCR;          /*!< Flash Option Clear Control Register,                      Address offset: 0x24  */

+  __IO uint32_t PRAR_CUR1;       /*!< Flash Current Protection Address Register for bank1,      Address offset: 0x28  */

+  __IO uint32_t PRAR_PRG1;       /*!< Flash Protection Address to Program Register for bank1,   Address offset: 0x2C  */

+  __IO uint32_t SCAR_CUR1;       /*!< Flash Current Secure Address Register for bank1,          Address offset: 0x30  */

+  __IO uint32_t SCAR_PRG1;       /*!< Flash Secure Address to Program Register for bank1,       Address offset: 0x34  */

+  __IO uint32_t WPSN_CUR1;       /*!< Flash Current Write Protection Register on bank1,         Address offset: 0x38  */

+  __IO uint32_t WPSN_PRG1;       /*!< Flash Write Protection to Program Register on bank1,      Address offset: 0x3C  */

+  __IO uint32_t BOOT7_CUR;       /*!< Flash Current Boot Address for Pelican Core Register,     Address offset: 0x40  */

+  __IO uint32_t BOOT7_PRG;       /*!< Flash Boot Address to Program for Pelican Core Register,  Address offset: 0x44  */

+  __IO uint32_t BOOT4_CUR;       /*!< Flash Current Boot Address for M4 Core Register,          Address offset: 0x48  */

+  __IO uint32_t BOOT4_PRG;       /*!< Flash Boot Address to Program for M4 Core Register,       Address offset: 0x4C  */

+  __IO uint32_t CRCCR1;          /*!< Flash CRC Control register For Bank1 Register ,           Address offset: 0x50  */

+  __IO uint32_t CRCSADD1;        /*!< Flash CRC Start Address Register for Bank1 ,              Address offset: 0x54  */

+  __IO uint32_t CRCEADD1;        /*!< Flash CRC End Address Register for Bank1 ,                Address offset: 0x58  */

+  __IO uint32_t CRCDATA;         /*!< Flash CRC Data Register for Bank1 ,                       Address offset: 0x5C  */

+  __IO uint32_t ECC_FA1;         /*!< Flash ECC Fail Address For Bank1 Register ,               Address offset: 0x60  */

+  uint32_t      RESERVED1[40];   /*!< Reserved, 0x64 to 0x100                                                         */

+  __IO uint32_t KEYR2;           /*!< Flash Key Register for bank2,                             Address offset: 0x104 */

+  uint32_t      RESERVED2;       /*!< Reserved, 0x108                                                                 */

+  __IO uint32_t CR2;             /*!< Flash Control Register for bank2,                         Address offset: 0x10C */

+  __IO uint32_t SR2;             /*!< Flash Status Register for bank2,                          Address offset: 0x110 */

+  __IO uint32_t CCR2;            /*!< Flash Status Register for bank2,                          Address offset: 0x114 */

+  uint32_t      RESERVED3[4];    /*!< Reserved, 0x118 to 0x124                                                        */

+  __IO uint32_t PRAR_CUR2;       /*!< Flash Current Protection Address Register for bank2,      Address offset: 0x128 */

+  __IO uint32_t PRAR_PRG2;       /*!< Flash Protection Address to Program Register for bank2,   Address offset: 0x12C */

+  __IO uint32_t SCAR_CUR2;       /*!< Flash Current Secure Address Register for bank2,          Address offset: 0x130 */

+  __IO uint32_t SCAR_PRG2;       /*!< Flash Secure Address Register for bank2,                  Address offset: 0x134 */

+  __IO uint32_t WPSN_CUR2;       /*!< Flash Current Write Protection Register on bank2,         Address offset: 0x138 */

+  __IO uint32_t WPSN_PRG2;       /*!< Flash Write Protection to Program Register on bank2,      Address offset: 0x13C */

+  uint32_t      RESERVED4[4];    /*!< Reserved, 0x140 to 0x14C                                                        */

+  __IO uint32_t CRCCR2;          /*!< Flash CRC Control register For Bank2 Register ,           Address offset: 0x150 */

+  __IO uint32_t CRCSADD2;        /*!< Flash CRC Start Address Register for Bank2 ,              Address offset: 0x154 */

+  __IO uint32_t CRCEADD2;        /*!< Flash CRC End Address Register for Bank2 ,                Address offset: 0x158 */

+  __IO uint32_t CRCDATA2;        /*!< Flash CRC Data Register for Bank2 ,                       Address offset: 0x15C */

+  __IO uint32_t ECC_FA2;         /*!< Flash ECC Fail Address For Bank2 Register ,               Address offset: 0x160 */

+} FLASH_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */

+} FMC_Bank1_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank1E

+  */

+

+typedef struct

+{

+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */

+} FMC_Bank1E_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank2

+  */

+

+typedef struct

+{

+  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */

+  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */

+  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */

+  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */

+  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */

+  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */

+} FMC_Bank2_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank3

+  */

+

+typedef struct

+{

+  __IO uint32_t PCR;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */

+  __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */

+  __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */

+  __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */

+  uint32_t      RESERVED;  /*!< Reserved, 0x90                                                            */

+  __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */

+} FMC_Bank3_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank5 and 6

+  */

+

+

+typedef struct

+{

+  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */

+  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */

+  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */

+  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */

+  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */

+} FMC_Bank5_6_TypeDef;

+

+/**

+  * @brief General Purpose I/O

+  */

+

+typedef struct

+{

+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */

+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */

+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */

+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */

+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */

+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */

+  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset,               Address offset: 0x18      */

+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */

+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */

+} GPIO_TypeDef;

+

+/**

+  * @brief Operational Amplifier (OPAMP)

+  */

+

+typedef struct

+{

+  __IO uint32_t CSR;          /*!< OPAMP control/status register,                      Address offset: 0x00 */

+  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,     Address offset: 0x04 */

+  __IO uint32_t HSOTR;        /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */

+} OPAMP_TypeDef;

+

+/**

+  * @brief System configuration controller

+  */

+

+typedef struct

+{

+ uint32_t RESERVED1;           /*!< Reserved,                                           Address offset: 0x00        */

+ __IO uint32_t PMCR;           /*!< SYSCFG peripheral mode configuration register,      Address offset: 0x04        */

+ __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration registers,  Address offset: 0x08-0x14   */

+ __IO uint32_t CFGR;           /*!< SYSCFG configuration registers,                     Address offset: 0x18        */

+ uint32_t RESERVED2;           /*!< Reserved,                                           Address offset: 0x1C        */

+ __IO uint32_t CCCSR;          /*!< SYSCFG compensation cell control/status register,   Address offset: 0x20        */

+ __IO uint32_t CCVR;           /*!< SYSCFG compensation cell value register,            Address offset: 0x24        */

+ __IO uint32_t CCCR;           /*!< SYSCFG compensation cell code register,             Address offset: 0x28        */

+ __IO uint32_t PWRCR;          /*!< PWR control register,                               Address offset: 0x2C        */

+  uint32_t     RESERVED3[61];  /*!< Reserved, 0x30-0x120                                                            */

+  __IO uint32_t PKGR;          /*!< SYSCFG package register,                            Address offset: 0x124       */

+  uint32_t     RESERVED4[118]; /*!< Reserved, 0x128-0x2FC                                                           */

+ __IO uint32_t UR0;            /*!< SYSCFG user register 0,                             Address offset: 0x300       */

+ __IO uint32_t UR1;            /*!< SYSCFG user register 1,                             Address offset: 0x304       */

+ __IO uint32_t UR2;            /*!< SYSCFG user register 2,                             Address offset: 0x308       */

+ __IO uint32_t UR3;            /*!< SYSCFG user register 3,                             Address offset: 0x30C       */

+ __IO uint32_t UR4;            /*!< SYSCFG user register 4,                             Address offset: 0x310       */

+ __IO uint32_t UR5;            /*!< SYSCFG user register 5,                             Address offset: 0x314       */

+ __IO uint32_t UR6;            /*!< SYSCFG user register 6,                             Address offset: 0x318       */

+ __IO uint32_t UR7;            /*!< SYSCFG user register 7,                             Address offset: 0x31C       */

+ __IO uint32_t UR8;            /*!< SYSCFG user register 8,                             Address offset: 0x320       */

+ __IO uint32_t UR9;            /*!< SYSCFG user register 9,                             Address offset: 0x324       */

+ __IO uint32_t UR10;           /*!< SYSCFG user register 10,                            Address offset: 0x328       */

+ __IO uint32_t UR11;           /*!< SYSCFG user register 11,                            Address offset: 0x32C       */

+ __IO uint32_t UR12;           /*!< SYSCFG user register 12,                            Address offset: 0x330       */

+ __IO uint32_t UR13;           /*!< SYSCFG user register 13,                            Address offset: 0x334       */

+ __IO uint32_t UR14;           /*!< SYSCFG user register 14,                            Address offset: 0x338       */

+ __IO uint32_t UR15;           /*!< SYSCFG user register 15,                            Address offset: 0x33C       */

+ __IO uint32_t UR16;           /*!< SYSCFG user register 16,                            Address offset: 0x340       */

+ __IO uint32_t UR17;           /*!< SYSCFG user register 17,                            Address offset: 0x344       */

+

+} SYSCFG_TypeDef;

+

+/**

+  * @brief Inter-integrated Circuit Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */

+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */

+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */

+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */

+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */

+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */

+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */

+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */

+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */

+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */

+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */

+} I2C_TypeDef;

+

+/**

+  * @brief Independent WATCHDOG

+  */

+

+typedef struct

+{

+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */

+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */

+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */

+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */

+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */

+} IWDG_TypeDef;

+

+

+/**

+  * @brief JPEG Codec

+  */

+typedef struct

+{

+  __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */

+  __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */

+  __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */

+  __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */

+  __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */

+  __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */

+  __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */

+  __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */

+  uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */

+  __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */

+  __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */

+  __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */

+  uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */

+  __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */

+  __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */

+  uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */

+  __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */

+  __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */

+  __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */

+  __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */

+  __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */

+  __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */

+  __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */

+  __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */

+  uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */

+  __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0,                 Address offset: 500h-65Ch */

+  __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1,                 Address offset: 660h-7BCh */

+  __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encodor, DC Huffman table 0,                 Address offset: 7C0h-7DCh */

+  __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encodor, DC Huffman table 1,                 Address offset: 7E0h-7FCh */

+

+} JPEG_TypeDef;

+

+/**

+  * @brief LCD-TFT Display Controller

+  */

+

+typedef struct

+{

+  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04                                                       */

+  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */

+  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */

+  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */

+  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */

+  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */

+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20                                                       */

+  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */

+  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28                                                            */

+  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */

+  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30                                                            */

+  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */

+  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */

+  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */

+  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */

+  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */

+  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */

+} LTDC_TypeDef;

+

+/**

+  * @brief LCD-TFT Display layer x Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */

+  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */

+  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */

+  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */

+  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */

+  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */

+  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */

+  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */

+  uint32_t      RESERVED0[2];  /*!< Reserved */

+  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */

+  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */

+  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */

+  uint32_t      RESERVED1[3];  /*!< Reserved */

+  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */

+

+} LTDC_Layer_TypeDef;

+

+/**

+  * @brief Power Control

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;       /*!< PWR power control register 1,            Address offset: 0x00 */

+  __IO uint32_t CSR1;      /*!< PWR power control status register 1,     Address offset: 0x04 */

+  __IO uint32_t CR2;       /*!< PWR power control register 2,            Address offset: 0x08 */

+  __IO uint32_t CR3;       /*!< PWR power control register 3,            Address offset: 0x0C */

+  __IO uint32_t CPUCR;     /*!< PWR CPU control register,                Address offset: 0x10 */

+  __IO uint32_t CPU2CR;    /*!< PWR CPU2 control register,               Address offset: 0x14 */

+  __IO uint32_t D3CR;      /*!< PWR D3 domain control register,          Address offset: 0x18 */

+       uint32_t RESERVED1; /*!< Reserved,                                Address offset: 0x1C */

+  __IO uint32_t WKUPCR;    /*!< PWR wakeup clear register,               Address offset: 0x20 */

+  __IO uint32_t WKUPFR;    /*!< PWR wakeup flag register,                Address offset: 0x24 */

+  __IO uint32_t WKUPEPR;   /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */

+} PWR_TypeDef;

+

+/**

+  * @brief Reset and Clock Control

+  */

+

+typedef struct

+{

+ __IO uint32_t CR;             /*!< RCC clock control register,                                              Address offset: 0x00  */

+ __IO uint32_t HSICFGR;        /*!< HSI Clock Calibration Register,                                          Address offset: 0x04  */

+ __IO uint32_t CRRCR;          /*!< Clock Recovery RC  Register,                                             Address offset: 0x08  */

+ __IO uint32_t CSICFGR;        /*!< CSI Clock Calibration Register,                                          Address offset: 0x0C  */

+ __IO uint32_t CFGR;           /*!< RCC clock configuration register,                                        Address offset: 0x10  */

+ uint32_t     RESERVED1;       /*!< Reserved,                                                                Address offset: 0x14  */

+ __IO uint32_t D1CFGR;         /*!< RCC Domain 1 configuration register,                                     Address offset: 0x18  */

+ __IO uint32_t D2CFGR;         /*!< RCC Domain 2 configuration register,                                     Address offset: 0x1C  */

+ __IO uint32_t D3CFGR;         /*!< RCC Domain 3 configuration register,                                     Address offset: 0x20  */

+ uint32_t     RESERVED2;       /*!< Reserved,                                                                Address offset: 0x24  */

+ __IO uint32_t PLLCKSELR;      /*!< RCC PLLs Clock Source Selection Register,                                Address offset: 0x28  */

+ __IO uint32_t PLLCFGR;        /*!< RCC PLLs  Configuration Register,                                        Address offset: 0x2C  */

+ __IO uint32_t PLL1DIVR;       /*!< RCC PLL1 Dividers Configuration Register,                                Address offset: 0x30  */

+ __IO uint32_t PLL1FRACR;      /*!< RCC PLL1 Fractional Divider Configuration Register,                      Address offset: 0x34  */

+ __IO uint32_t PLL2DIVR;       /*!< RCC PLL2 Dividers Configuration Register,                                Address offset: 0x38  */

+ __IO uint32_t PLL2FRACR;      /*!< RCC PLL2 Fractional Divider Configuration Register,                      Address offset: 0x3C  */

+ __IO uint32_t PLL3DIVR;       /*!< RCC PLL3 Dividers Configuration Register,                                Address offset: 0x40  */

+ __IO uint32_t PLL3FRACR;      /*!< RCC PLL3 Fractional Divider Configuration Register,                      Address offset: 0x44  */

+ uint32_t      RESERVED3;      /*!< Reserved,                                                                Address offset: 0x48  */

+ __IO uint32_t  D1CCIPR;       /*!< RCC Domain 1 Kernel Clock Configuration Register                         Address offset: 0x4C  */

+ __IO uint32_t  D2CCIP1R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x50  */

+ __IO uint32_t  D2CCIP2R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x54  */

+ __IO uint32_t  D3CCIPR;       /*!< RCC Domain 3 Kernel Clock Configuration Register                         Address offset: 0x58  */

+ uint32_t      RESERVED4;      /*!< Reserved,                                                                Address offset: 0x5C  */

+ __IO uint32_t  CIER;          /*!< RCC Clock Source Interrupt Enable Register                               Address offset: 0x60  */

+ __IO uint32_t  CIFR;          /*!< RCC Clock Source Interrupt Flag Register                                 Address offset: 0x64  */

+ __IO uint32_t  CICR;          /*!< RCC Clock Source Interrupt Clear Register                                Address offset: 0x68  */

+ uint32_t     RESERVED5;       /*!< Reserved,                                                                Address offset: 0x6C  */

+ __IO uint32_t  BDCR;          /*!< RCC Vswitch Backup Domain Control Register,                              Address offset: 0x70  */

+ __IO uint32_t  CSR;           /*!< RCC clock control & status register,                                     Address offset: 0x74  */

+ uint32_t     RESERVED6;       /*!< Reserved,                                                                Address offset: 0x78  */

+ __IO uint32_t AHB3RSTR;       /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x7C  */

+ __IO uint32_t AHB1RSTR;       /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x80  */

+ __IO uint32_t AHB2RSTR;       /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x84  */

+ __IO uint32_t AHB4RSTR;       /*!< RCC AHB4 peripheral reset register,                                      Address offset: 0x88  */

+ __IO uint32_t APB3RSTR;       /*!< RCC APB3 peripheral reset register,                                      Address offset: 0x8C  */

+ __IO uint32_t APB1LRSTR;      /*!< RCC APB1 peripheral reset Low Word register,                             Address offset: 0x90  */

+ __IO uint32_t APB1HRSTR;      /*!< RCC APB1 peripheral reset High Word register,                            Address offset: 0x94  */

+ __IO uint32_t APB2RSTR;       /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x98  */

+ __IO uint32_t APB4RSTR;       /*!< RCC APB4 peripheral reset register,                                      Address offset: 0x9C  */

+ __IO uint32_t GCR;            /*!< RCC RCC Global Control  Register,                                        Address offset: 0xA0  */

+ uint32_t     RESERVED8;       /*!< Reserved,                                                                Address offset: 0xA4  */

+ __IO uint32_t D3AMR;          /*!< RCC Domain 3 Autonomous Mode Register,                                   Address offset: 0xA8  */

+ uint32_t     RESERVED11[9];    /*!< Reserved, 0xAC-0xCC                                                      Address offset: 0xAC  */

+ __IO uint32_t RSR;            /*!< RCC Reset status register,                                               Address offset: 0xD0  */

+ __IO uint32_t AHB3ENR;        /*!< RCC AHB3 peripheral clock  register,                                     Address offset: 0xD4  */

+ __IO uint32_t AHB1ENR;        /*!< RCC AHB1 peripheral clock  register,                                     Address offset: 0xD8  */

+ __IO uint32_t AHB2ENR;        /*!< RCC AHB2 peripheral clock  register,                                     Address offset: 0xDC  */

+ __IO uint32_t AHB4ENR;        /*!< RCC AHB4 peripheral clock  register,                                     Address offset: 0xE0  */

+ __IO uint32_t APB3ENR;        /*!< RCC APB3 peripheral clock  register,                                     Address offset: 0xE4  */

+ __IO uint32_t APB1LENR;       /*!< RCC APB1 peripheral clock  Low Word register,                            Address offset: 0xE8  */

+ __IO uint32_t APB1HENR;       /*!< RCC APB1 peripheral clock  High Word register,                           Address offset: 0xEC  */

+ __IO uint32_t APB2ENR;        /*!< RCC APB2 peripheral clock  register,                                     Address offset: 0xF0  */

+ __IO uint32_t APB4ENR;        /*!< RCC APB4 peripheral clock  register,                                     Address offset: 0xF4  */

+ uint32_t      RESERVED12;      /*!< Reserved,                                                                Address offset: 0xF8  */

+ __IO uint32_t AHB3LPENR;      /*!< RCC AHB3 peripheral sleep clock  register,                               Address offset: 0xFC  */

+ __IO uint32_t AHB1LPENR;      /*!< RCC AHB1 peripheral sleep clock  register,                               Address offset: 0x100 */

+ __IO uint32_t AHB2LPENR;      /*!< RCC AHB2 peripheral sleep clock  register,                               Address offset: 0x104 */

+ __IO uint32_t AHB4LPENR;      /*!< RCC AHB4 peripheral sleep clock  register,                               Address offset: 0x108 */

+ __IO uint32_t APB3LPENR;      /*!< RCC APB3 peripheral sleep clock  register,                               Address offset: 0x10C */

+ __IO uint32_t APB1LLPENR;     /*!< RCC APB1 peripheral sleep clock  Low Word register,                      Address offset: 0x110 */

+ __IO uint32_t APB1HLPENR;     /*!< RCC APB1 peripheral sleep clock  High Word register,                     Address offset: 0x114 */

+ __IO uint32_t APB2LPENR;      /*!< RCC APB2 peripheral sleep clock  register,                               Address offset: 0x118 */

+ __IO uint32_t APB4LPENR;      /*!< RCC APB4 peripheral sleep clock  register,                               Address offset: 0x11C */

+ uint32_t     RESERVED13[4];   /*!< Reserved, 0x120-0x12C                                                    Address offset: 0x120 */

+

+} RCC_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t RSR;          /*!< RCC Reset status register,                                               Address offset: 0x00 */

+  __IO uint32_t AHB3ENR;      /*!< RCC AHB3 peripheral clock  register,                            Address offset: 0x04 */

+  __IO uint32_t AHB1ENR;      /*!< RCC AHB1 peripheral clock  register,                            Address offset: 0x08 */

+  __IO uint32_t AHB2ENR;      /*!< RCC AHB2 peripheral clock  register,                            Address offset: 0x0C */

+  __IO uint32_t AHB4ENR;      /*!< RCC AHB4 peripheral clock  register,                            Address offset: 0x10 */

+  __IO uint32_t APB3ENR;      /*!< RCC APB3 peripheral clock  register,                            Address offset: 0x14 */

+  __IO uint32_t APB1LENR;     /*!< RCC APB1 peripheral clock  Low Word register,                   Address offset: 0x18 */

+  __IO uint32_t APB1HENR;     /*!< RCC APB1 peripheral clock  High Word register,                  Address offset: 0x1C */

+  __IO uint32_t APB2ENR;      /*!< RCC APB2 peripheral clock  register,                            Address offset: 0x20 */

+  __IO uint32_t APB4ENR;      /*!< RCC APB4 peripheral clock  register,                            Address offset: 0x24 */

+  uint32_t      RESERVED9;    /*!< Reserved,                                                       Address offset: 0x28 */

+  __IO uint32_t AHB3LPENR;    /*!< RCC AHB3 peripheral sleep clock  register,                      Address offset: 0x3C */

+  __IO uint32_t AHB1LPENR;    /*!< RCC AHB1 peripheral sleep clock  register,                      Address offset: 0x40 */

+  __IO uint32_t AHB2LPENR;    /*!< RCC AHB2 peripheral sleep clock  register,                      Address offset: 0x44 */

+  __IO uint32_t AHB4LPENR;    /*!< RCC AHB4 peripheral sleep clock  register,                      Address offset: 0x48 */

+  __IO uint32_t APB3LPENR;    /*!< RCC APB3 peripheral sleep clock  register,                      Address offset: 0x4C */

+  __IO uint32_t APB1LLPENR;   /*!< RCC APB1 peripheral sleep clock  Low Word register,             Address offset: 0x50 */

+  __IO uint32_t APB1HLPENR;   /*!< RCC APB1 peripheral sleep clock  High Word register,            Address offset: 0x54 */

+  __IO uint32_t APB2LPENR;    /*!< RCC APB2 peripheral sleep clock  register,                      Address offset: 0x58 */

+  __IO uint32_t APB4LPENR;    /*!< RCC APB4 peripheral sleep clock  register,                      Address offset: 0x5C */

+  uint32_t     RESERVED10[4]; /*!< Reserved, 0x60-0x6C                                             Address offset: 0x60 */

+

+} RCC_Core_TypeDef;

+

+/**

+  * @brief Real-Time Clock

+  */

+typedef struct

+{

+  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */

+  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */

+  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */

+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */

+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */

+  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */

+       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */

+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */

+  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */

+  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */

+  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */

+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */

+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */

+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */

+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */

+  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */

+  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */

+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */

+  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */

+  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset: 0x4C */

+  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */

+  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */

+  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */

+  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */

+  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */

+  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */

+  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */

+  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */

+  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */

+  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */

+  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */

+  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */

+  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */

+  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */

+  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */

+  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */

+  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */

+  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */

+  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */

+  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */

+  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */

+  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */

+  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */

+  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */

+  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */

+  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */

+  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */

+  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */

+  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */

+  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */

+  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */

+  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */

+} RTC_TypeDef;

+

+/**

+  * @brief Serial Audio Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t GCR;           /*!< SAI global configuration register, Address offset: 0x00 */

+  uint32_t      RESERVED0[16]; /*!< Reserved, 0x04 - 0x43                                   */

+  __IO uint32_t PDMCR;         /*!< SAI PDM control register,          Address offset: 0x44 */

+  __IO uint32_t PDMDLY;        /*!< SAI PDM delay register,            Address offset: 0x48 */

+} SAI_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */

+  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */

+  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */

+  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */

+  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */

+  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */

+  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */

+  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */

+} SAI_Block_TypeDef;

+

+/**

+  * @brief SPDIF-RX Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */

+  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */

+  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */

+  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */

+  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */

+  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */

+  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */

+  uint32_t        RESERVED2;    /*!< Reserved,  0x1A                                          */

+} SPDIFRX_TypeDef;

+

+

+/**

+  * @brief Secure digital input/output Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t POWER;          /*!< SDMMC power control register,             Address offset: 0x00  */

+  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,             Address offset: 0x04  */

+  __IO uint32_t ARG;            /*!< SDMMC argument register,                  Address offset: 0x08  */

+  __IO uint32_t CMD;            /*!< SDMMC command register,                   Address offset: 0x0C  */

+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register,          Address offset: 0x10  */

+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                Address offset: 0x14  */

+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                Address offset: 0x18  */

+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                Address offset: 0x1C  */

+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                Address offset: 0x20  */

+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                Address offset: 0x24  */

+  __IO uint32_t DLEN;           /*!< SDMMC data length register,               Address offset: 0x28  */

+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,              Address offset: 0x2C  */

+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,              Address offset: 0x30  */

+  __I uint32_t  STA;            /*!< SDMMC status register,                    Address offset: 0x34  */

+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,           Address offset: 0x38  */

+  __IO uint32_t MASK;           /*!< SDMMC mask register,                      Address offset: 0x3C  */

+  __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,     Address offset: 0x40  */

+  uint32_t      RESERVED0[3];   /*!< Reserved, 0x44 - 0x4C - 0x4C                                    */

+  __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,               Address offset: 0x50  */

+  __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,           Address offset: 0x54  */

+  __IO uint32_t IDMABASE0;      /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58  */

+  __IO uint32_t IDMABASE1;      /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C  */

+  uint32_t      RESERVED1[8];   /*!< Reserved, 0x60-0x7C                                             */

+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,                 Address offset: 0x80  */

+  uint32_t      RESERVED2[222]; /*!< Reserved, 0x84-0x3F8                                            */

+  __IO uint32_t IPVR;           /*!< SDMMC data FIFO register,                 Address offset: 0x3FC */

+} SDMMC_TypeDef;

+

+

+/**

+  * @brief Delay Block DLYB

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;          /*!< DELAY BLOCK control register,  Address offset: 0x00 */

+  __IO uint32_t CFGR;        /*!< DELAY BLOCK configuration register,  Address offset: 0x04 */

+} DLYB_TypeDef;

+

+/**

+  * @brief HW Semaphore HSEM

+  */

+

+typedef struct

+{

+  __IO uint32_t R[32];      /*!< 2-step write lock and read back registers,     Address offset: 00h-7Ch  */

+  __IO uint32_t RLR[32];    /*!< 1-step read lock registers,                    Address offset: 80h-FCh  */

+  __IO uint32_t C1IER;      /*!< HSEM Interrupt 0 enable register ,             Address offset: 100h     */

+  __IO uint32_t C1ICR;      /*!< HSEM Interrupt 0 clear register ,              Address offset: 104h     */

+  __IO uint32_t C1ISR;      /*!< HSEM Interrupt 0 Status register ,             Address offset: 108h     */

+  __IO uint32_t C1MISR;     /*!< HSEM Interrupt 0 Masked Status register ,      Address offset: 10Ch     */

+  __IO uint32_t C2IER;      /*!< HSEM Interrupt 1 enable register ,             Address offset: 110h     */

+  __IO uint32_t C2ICR;      /*!< HSEM Interrupt 1 clear register ,              Address offset: 114h     */

+  __IO uint32_t C2ISR;      /*!< HSEM Interrupt 1 Status register ,             Address offset: 118h     */

+  __IO uint32_t C2MISR;     /*!< HSEM Interrupt 1 Masked Status register ,      Address offset: 11Ch     */

+   uint32_t  Reserved[8];   /* Reserved                                         Address offset: 120h-13Ch*/

+  __IO uint32_t CR;         /*!< HSEM Semaphore clear register ,                Address offset: 140h      */

+  __IO uint32_t KEYR;       /*!< HSEM Semaphore clear key register ,            Address offset: 144h      */

+

+} HSEM_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t IER;        /*!< HSEM interrupt enable register ,                Address offset:   0h     */

+  __IO uint32_t ICR;        /*!< HSEM interrupt clear register ,                 Address offset:   4h     */

+  __IO uint32_t ISR;        /*!< HSEM interrupt status register ,                Address offset:   8h     */

+  __IO uint32_t MISR;       /*!< HSEM masked interrupt status register ,         Address offset:   Ch     */

+} HSEM_Common_TypeDef;

+

+/**

+  * @brief Serial Peripheral Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */

+  __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */

+  __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */

+  __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */

+  __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */

+  __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */

+  __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */

+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */

+  __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */

+  uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */

+  __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */

+  uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */

+  __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */

+  __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */

+  __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */

+  __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */

+  __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */

+

+} SPI_TypeDef;

+/**

+  * @brief QUAD Serial Peripheral Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */

+  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */

+  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */

+  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */

+  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */

+  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */

+  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */

+  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */

+  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */

+  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */

+  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */

+  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */

+  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */

+} QUADSPI_TypeDef;

+

+/**

+  * @brief TIM

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */

+  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */

+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */

+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */

+  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */

+  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */

+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */

+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */

+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */

+  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */

+  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */

+  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */

+  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */

+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */

+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */

+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */

+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */

+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */

+  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */

+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */

+  uint32_t      RESERVED1;   /*!< Reserved, 0x50                                                 */

+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */

+  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */

+  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */

+  __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */

+  __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */

+  __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x68 */

+} TIM_TypeDef;

+

+/**

+  * @brief LPTIMIMER

+  */

+typedef struct

+{

+  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,         Address offset: 0x00 */

+  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,              Address offset: 0x04 */

+  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,             Address offset: 0x08 */

+  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                Address offset: 0x0C */

+  __IO uint32_t CR;       /*!< LPTIM Control register,                      Address offset: 0x10 */

+  __IO uint32_t CMP;      /*!< LPTIM Compare register,                      Address offset: 0x14 */

+  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                   Address offset: 0x18 */

+  __IO uint32_t CNT;      /*!< LPTIM Counter register,                      Address offset: 0x1C */

+  uint32_t  RESERVED1;    /*!< Reserved, 0x20                                                    */

+  __IO uint32_t CFGR2;    /*!< LPTIM Configuration register,                Address offset: 0x24 */

+} LPTIM_TypeDef;

+

+/**

+  * @brief Comparator

+  */

+typedef struct

+{

+  __IO uint32_t SR;        /*!< Comparator status register,                    Address offset: 0x00 */

+  __IO uint32_t ICFR;      /*!< Comparator interrupt clear flag register,       Address offset: 0x04 */

+  __IO uint32_t OR;        /*!< Comparator option register,                  Address offset: 0x08 */

+} COMPOPT_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CFGR;      /*!< Comparator configuration register  ,           Address offset: 0x00 */

+} COMP_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CFGR;       /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */

+} COMP_Common_TypeDef;

+/**

+  * @brief Universal Synchronous Asynchronous Receiver Transmitter

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */

+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */

+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */

+  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */

+  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */

+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */

+  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */

+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */

+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */

+  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */

+  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */

+  __IO uint32_t PRESC;  /*!< USART clock Prescaler register,           Address offset: 0x2C */

+} USART_TypeDef;

+

+/**

+  * @brief Single Wire Protocol Master Interface SPWMI

+  */

+typedef struct

+{

+  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */

+  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */

+    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */

+  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */

+  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */

+  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */

+  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */

+  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */

+  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */

+  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */

+} SWPMI_TypeDef;

+

+/**

+  * @brief Window WATCHDOG

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */

+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */

+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */

+} WWDG_TypeDef;

+

+

+/**

+  * @brief RAM_ECC_Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t CR;           /*!< RAMECC monitor configuration register          */

+  __IO uint32_t SR;           /*!< RAMECC monitor status register                 */

+  __IO uint32_t FAR;          /*!< RAMECC monitor failing address register        */

+  __IO uint32_t FDRL;         /*!< RAMECC monitor failing data low register       */

+  __IO uint32_t FDRH;         /*!< RAMECC monitor failing data high register      */

+  __IO uint32_t FECR;         /*!< RAMECC monitor failing ECC error code register */

+} RAMECC_MonitorTypeDef;

+

+typedef struct

+{

+  __IO uint32_t IER;          /*!< RAMECC interrupt enable register */

+} RAMECC_TypeDef;

+/**

+  * @}

+  */

+

+

+/**

+  * @brief Crypto Processor

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */

+  __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */

+  __IO uint32_t DIN;         /*!< CRYP data input register,                                Address offset: 0x08 */

+  __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */

+  __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */

+  __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */

+  __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */

+  __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */

+  __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */

+  __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */

+  __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */

+  __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */

+  __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */

+  __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */

+  __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */

+  __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */

+  __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */

+  __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */

+  __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */

+  __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */

+  __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */

+  __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */

+  __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */

+  __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */

+  __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */

+  __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */

+  __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */

+  __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */

+  __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */

+  __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */

+  __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */

+  __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */

+  __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */

+  __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */

+  __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */

+  __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */

+} CRYP_TypeDef;

+

+/**

+  * @brief HASH

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */

+  __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */

+  __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */

+  __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */

+  __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */

+  __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */

+       uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */

+  __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */

+} HASH_TypeDef;

+

+/**

+  * @brief HASH_DIGEST

+  */

+

+typedef struct

+{

+  __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */

+} HASH_DIGEST_TypeDef;

+

+

+/**

+  * @brief High resolution Timer (HRTIM)

+  */

+/* HRTIM master registers definition */

+typedef struct

+{

+  __IO uint32_t MCR;            /*!< HRTIM Master Timer control register,                     Address offset: 0x00 */

+  __IO uint32_t MISR;           /*!< HRTIM Master Timer interrupt status register,            Address offset: 0x04 */

+  __IO uint32_t MICR;           /*!< HRTIM Master Timer interupt clear register,              Address offset: 0x08 */

+  __IO uint32_t MDIER;          /*!< HRTIM Master Timer DMA/interrupt enable register         Address offset: 0x0C */

+  __IO uint32_t MCNTR;          /*!< HRTIM Master Timer counter register,                     Address offset: 0x10 */

+  __IO uint32_t MPER;           /*!< HRTIM Master Timer period register,                      Address offset: 0x14 */

+  __IO uint32_t MREP;           /*!< HRTIM Master Timer repetition register,                  Address offset: 0x18 */

+  __IO uint32_t MCMP1R;         /*!< HRTIM Master Timer compare 1 register,                   Address offset: 0x1C */

+  uint32_t      RESERVED0;     /*!< Reserved,                                                                 0x20 */

+  __IO uint32_t MCMP2R;         /*!< HRTIM Master Timer compare 2 register,                   Address offset: 0x24 */

+  __IO uint32_t MCMP3R;         /*!< HRTIM Master Timer compare 3 register,                   Address offset: 0x28 */

+  __IO uint32_t MCMP4R;         /*!< HRTIM Master Timer compare 4 register,                   Address offset: 0x2C */

+  uint32_t      RESERVED1[20];  /*!< Reserved,                                                          0x30..0x7C */

+}HRTIM_Master_TypeDef;

+

+/* HRTIM Timer A to E registers definition */

+typedef struct

+{

+  __IO uint32_t TIMxCR;     /*!< HRTIM Timerx control register,                              Address offset: 0x00 */

+  __IO uint32_t TIMxISR;    /*!< HRTIM Timerx interrupt status register,                     Address offset: 0x04 */

+  __IO uint32_t TIMxICR;    /*!< HRTIM Timerx interrupt clear register,                      Address offset: 0x08 */

+  __IO uint32_t TIMxDIER;   /*!< HRTIM Timerx DMA/interrupt enable register,                 Address offset: 0x0C */

+  __IO uint32_t CNTxR;      /*!< HRTIM Timerx counter register,                              Address offset: 0x10 */

+  __IO uint32_t PERxR;      /*!< HRTIM Timerx period register,                               Address offset: 0x14 */

+  __IO uint32_t REPxR;      /*!< HRTIM Timerx repetition register,                           Address offset: 0x18 */

+  __IO uint32_t CMP1xR;     /*!< HRTIM Timerx compare 1 register,                            Address offset: 0x1C */

+  __IO uint32_t CMP1CxR;    /*!< HRTIM Timerx compare 1 compound register,                   Address offset: 0x20 */

+  __IO uint32_t CMP2xR;     /*!< HRTIM Timerx compare 2 register,                            Address offset: 0x24 */

+  __IO uint32_t CMP3xR;     /*!< HRTIM Timerx compare 3 register,                            Address offset: 0x28 */

+  __IO uint32_t CMP4xR;     /*!< HRTIM Timerx compare 4 register,                            Address offset: 0x2C */

+  __IO uint32_t CPT1xR;     /*!< HRTIM Timerx capture 1 register,                            Address offset: 0x30 */

+  __IO uint32_t CPT2xR;     /*!< HRTIM Timerx capture 2 register,                            Address offset: 0x34 */

+  __IO uint32_t DTxR;       /*!< HRTIM Timerx dead time register,                            Address offset: 0x38 */

+  __IO uint32_t SETx1R;     /*!< HRTIM Timerx output 1 set register,                         Address offset: 0x3C */

+  __IO uint32_t RSTx1R;     /*!< HRTIM Timerx output 1 reset register,                       Address offset: 0x40 */

+  __IO uint32_t SETx2R;     /*!< HRTIM Timerx output 2 set register,                         Address offset: 0x44 */

+  __IO uint32_t RSTx2R;     /*!< HRTIM Timerx output 2 reset register,                       Address offset: 0x48 */

+  __IO uint32_t EEFxR1;     /*!< HRTIM Timerx external event filtering 1 register,           Address offset: 0x4C */

+  __IO uint32_t EEFxR2;     /*!< HRTIM Timerx external event filtering 2 register,           Address offset: 0x50 */

+  __IO uint32_t RSTxR;      /*!< HRTIM Timerx Reset register,                                Address offset: 0x54 */

+  __IO uint32_t CHPxR;      /*!< HRTIM Timerx Chopper register,                              Address offset: 0x58 */

+  __IO uint32_t CPT1xCR;    /*!< HRTIM Timerx Capture 1 register,                            Address offset: 0x5C */

+  __IO uint32_t CPT2xCR;    /*!< HRTIM Timerx Capture 2 register,                            Address offset: 0x60 */

+  __IO uint32_t OUTxR;      /*!< HRTIM Timerx Output register,                               Address offset: 0x64 */

+  __IO uint32_t FLTxR;      /*!< HRTIM Timerx Fault register,                                Address offset: 0x68 */

+  uint32_t      RESERVED0[5];  /*!< Reserved,                                                          0x6C..0x7C */

+}HRTIM_Timerx_TypeDef;

+

+/* HRTIM common register definition */

+typedef struct

+{

+  __IO uint32_t CR1;        /*!< HRTIM control register1,                                    Address offset: 0x00 */

+  __IO uint32_t CR2;        /*!< HRTIM control register2,                                    Address offset: 0x04 */

+  __IO uint32_t ISR;        /*!< HRTIM interrupt status register,                            Address offset: 0x08 */

+  __IO uint32_t ICR;        /*!< HRTIM interrupt clear register,                             Address offset: 0x0C */

+  __IO uint32_t IER;        /*!< HRTIM interrupt enable register,                            Address offset: 0x10 */

+  __IO uint32_t OENR;       /*!< HRTIM Output enable register,                               Address offset: 0x14 */

+  __IO uint32_t ODISR;      /*!< HRTIM Output disable register,                              Address offset: 0x18 */

+  __IO uint32_t ODSR;       /*!< HRTIM Output disable status register,                       Address offset: 0x1C */

+  __IO uint32_t BMCR;       /*!< HRTIM Burst mode control register,                          Address offset: 0x20 */

+  __IO uint32_t BMTRGR;     /*!< HRTIM Busrt mode trigger register,                          Address offset: 0x24 */

+  __IO uint32_t BMCMPR;     /*!< HRTIM Burst mode compare register,                          Address offset: 0x28 */

+  __IO uint32_t BMPER;      /*!< HRTIM Burst mode period register,                           Address offset: 0x2C */

+  __IO uint32_t EECR1;      /*!< HRTIM Timer external event control register1,               Address offset: 0x30 */

+  __IO uint32_t EECR2;      /*!< HRTIM Timer external event control register2,               Address offset: 0x34 */

+  __IO uint32_t EECR3;      /*!< HRTIM Timer external event control register3,               Address offset: 0x38 */

+  __IO uint32_t ADC1R;      /*!< HRTIM ADC Trigger 1 register,                               Address offset: 0x3C */

+  __IO uint32_t ADC2R;      /*!< HRTIM ADC Trigger 2 register,                               Address offset: 0x40 */

+  __IO uint32_t ADC3R;      /*!< HRTIM ADC Trigger 3 register,                               Address offset: 0x44 */

+  __IO uint32_t ADC4R;      /*!< HRTIM ADC Trigger 4 register,                               Address offset: 0x48 */

+  __IO uint32_t RESERVED0;  /*!< Reserved,                                                   Address offset: 0x4C */

+  __IO uint32_t FLTINR1;    /*!< HRTIM Fault input register1,                                Address offset: 0x50 */

+  __IO uint32_t FLTINR2;    /*!< HRTIM Fault input register2,                                Address offset: 0x54 */

+  __IO uint32_t BDMUPR;     /*!< HRTIM Burst DMA Master Timer update register,               Address offset: 0x58 */

+  __IO uint32_t BDTAUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x5C */

+  __IO uint32_t BDTBUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x60 */

+  __IO uint32_t BDTCUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x64 */

+  __IO uint32_t BDTDUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x68 */

+  __IO uint32_t BDTEUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x6C */

+  __IO uint32_t BDMADR;     /*!< HRTIM Burst DMA Master Data register,                       Address offset: 0x70 */

+}HRTIM_Common_TypeDef;

+

+/* HRTIM  register definition */

+typedef struct {

+  HRTIM_Master_TypeDef sMasterRegs;

+  HRTIM_Timerx_TypeDef sTimerxRegs[5];

+  uint32_t             RESERVED0[32];

+  HRTIM_Common_TypeDef sCommonRegs;

+}HRTIM_TypeDef;

+/**

+  * @brief RNG

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */

+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */

+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */

+} RNG_TypeDef;

+

+/**

+  * @brief MDIOS

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;

+  __IO uint32_t WRFR;

+  __IO uint32_t CWRFR;

+  __IO uint32_t RDFR;

+  __IO uint32_t CRDFR;

+  __IO uint32_t SR;

+  __IO uint32_t CLRFR;

+  uint32_t RESERVED[57];

+  __IO uint32_t DINR0;

+  __IO uint32_t DINR1;

+  __IO uint32_t DINR2;

+  __IO uint32_t DINR3;

+  __IO uint32_t DINR4;

+  __IO uint32_t DINR5;

+  __IO uint32_t DINR6;

+  __IO uint32_t DINR7;

+  __IO uint32_t DINR8;

+  __IO uint32_t DINR9;

+  __IO uint32_t DINR10;

+  __IO uint32_t DINR11;

+  __IO uint32_t DINR12;

+  __IO uint32_t DINR13;

+  __IO uint32_t DINR14;

+  __IO uint32_t DINR15;

+  __IO uint32_t DINR16;

+  __IO uint32_t DINR17;

+  __IO uint32_t DINR18;

+  __IO uint32_t DINR19;

+  __IO uint32_t DINR20;

+  __IO uint32_t DINR21;

+  __IO uint32_t DINR22;

+  __IO uint32_t DINR23;

+  __IO uint32_t DINR24;

+  __IO uint32_t DINR25;

+  __IO uint32_t DINR26;

+  __IO uint32_t DINR27;

+  __IO uint32_t DINR28;

+  __IO uint32_t DINR29;

+  __IO uint32_t DINR30;

+  __IO uint32_t DINR31;

+  __IO uint32_t DOUTR0;

+  __IO uint32_t DOUTR1;

+  __IO uint32_t DOUTR2;

+  __IO uint32_t DOUTR3;

+  __IO uint32_t DOUTR4;

+  __IO uint32_t DOUTR5;

+  __IO uint32_t DOUTR6;

+  __IO uint32_t DOUTR7;

+  __IO uint32_t DOUTR8;

+  __IO uint32_t DOUTR9;

+  __IO uint32_t DOUTR10;

+  __IO uint32_t DOUTR11;

+  __IO uint32_t DOUTR12;

+  __IO uint32_t DOUTR13;

+  __IO uint32_t DOUTR14;

+  __IO uint32_t DOUTR15;

+  __IO uint32_t DOUTR16;

+  __IO uint32_t DOUTR17;

+  __IO uint32_t DOUTR18;

+  __IO uint32_t DOUTR19;

+  __IO uint32_t DOUTR20;

+  __IO uint32_t DOUTR21;

+  __IO uint32_t DOUTR22;

+  __IO uint32_t DOUTR23;

+  __IO uint32_t DOUTR24;

+  __IO uint32_t DOUTR25;

+  __IO uint32_t DOUTR26;

+  __IO uint32_t DOUTR27;

+  __IO uint32_t DOUTR28;

+  __IO uint32_t DOUTR29;

+  __IO uint32_t DOUTR30;

+  __IO uint32_t DOUTR31;

+} MDIOS_TypeDef;

+

+

+/**

+  * @brief USB_OTG_Core_Registers

+  */

+typedef struct

+{

+ __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */

+  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */

+  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */

+  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */

+  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */

+  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */

+  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */

+  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */

+  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */

+  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */

+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */

+  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */

+  uint32_t Reserved30[2];             /*!< Reserved                                     030h */

+  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */

+  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */

+  __IO uint32_t GSNPSID;              /* USB_OTG core ID                                040h*/

+  __IO uint32_t GHWCFG1;              /* User HW config1                                044h*/

+  __IO uint32_t GHWCFG2;              /* User HW config2                                048h*/

+  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */

+  uint32_t  Reserved6;                /*!< Reserved                                     050h */

+  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */

+  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */

+  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */

+   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */

+    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */

+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */

+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */

+} USB_OTG_GlobalTypeDef;

+

+

+/**

+  * @brief USB_OTG_device_Registers

+  */

+typedef struct

+{

+  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */

+  __IO uint32_t DCTL;            /*!< dev Control Register         804h */

+  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */

+  uint32_t Reserved0C;           /*!< Reserved                     80Ch */

+  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */

+  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */

+  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */

+  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */

+  uint32_t  Reserved20;          /*!< Reserved                     820h */

+  uint32_t Reserved9;            /*!< Reserved                     824h */

+  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */

+  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */

+  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */

+  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */

+  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */

+  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */

+  uint32_t Reserved40;           /*!< dedicated EP mask            840h */

+  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */

+  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */

+  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */

+} USB_OTG_DeviceTypeDef;

+

+

+/**

+  * @brief USB_OTG_IN_Endpoint-Specific_Register

+  */

+typedef struct

+{

+  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */

+  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */

+  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */

+  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */

+  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */

+  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */

+  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */

+  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */

+} USB_OTG_INEndpointTypeDef;

+

+

+/**

+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */

+  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */

+  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */

+  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */

+  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */

+  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */

+  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */

+} USB_OTG_OUTEndpointTypeDef;

+

+

+/**

+  * @brief USB_OTG_Host_Mode_Register_Structures

+  */

+typedef struct

+{

+  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */

+  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */

+  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */

+  uint32_t Reserved40C;           /*!< Reserved                             40Ch */

+  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */

+  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */

+  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */

+} USB_OTG_HostTypeDef;

+

+/**

+  * @brief USB_OTG_Host_Channel_Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */

+  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */

+  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */

+  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */

+  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */

+  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */

+  uint32_t Reserved[2];           /*!< Reserved                                      */

+} USB_OTG_HostChannelTypeDef;

+/**

+  * @}

+  */

+

+

+/** @addtogroup Peripheral_memory_map

+  * @{

+  */

+#define D1_ITCMRAM_BASE           (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM  */

+#define D1_ITCMICP_BASE           (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM         */

+#define D1_DTCMRAM_BASE           (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM                            */

+#define D1_AXIFLASH_BASE          (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI                */

+#define D1_AXIICP_BASE            (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI          */

+#define D1_AXISRAM_BASE           (0x24000000UL) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI                */

+

+#define D2_AXISRAM_BASE           (0x10000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI                */

+#define D2_AHBSRAM_BASE           (0x30000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge    */

+

+#define D3_BKPSRAM_BASE           (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge                                */

+#define D3_SRAM_BASE              (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge                               */

+

+#define PERIPH_BASE               (0x40000000UL) /*!< Base address of : AHB/APB Peripherals                                                   */

+#define QSPI_BASE                 (0x90000000UL) /*!< Base address of : QSPI memories  accessible over AXI                                    */

+

+#define FLASH_BANK1_BASE          (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI                          */

+#define FLASH_BANK2_BASE          (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI                          */

+#define FLASH_END                 (0x081FFFFFUL) /*!< FLASH end address                                                                       */

+

+/* Legacy define */

+#define FLASH_BASE                FLASH_BANK1_BASE

+

+/*!< Device electronic signature memory map */

+#define UID_BASE                  (0x1FF1E800UL)            /*!< Unique device ID register base address */

+#define FLASHSIZE_BASE            (0x1FF1E880UL)            /*!< FLASH Size register base address */

+

+

+/*!< Peripheral memory map */

+#define D2_APB1PERIPH_BASE        PERIPH_BASE

+#define D2_APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)

+#define D2_AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)

+#define D2_AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)

+

+#define D1_APB1PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)

+#define D1_AHB1PERIPH_BASE       (PERIPH_BASE + 0x12000000UL)

+

+#define D3_APB1PERIPH_BASE       (PERIPH_BASE + 0x18000000UL)

+#define D3_AHB1PERIPH_BASE       (PERIPH_BASE + 0x18020000UL)

+

+/*!< Legacy Peripheral memory map */

+#define APB1PERIPH_BASE        PERIPH_BASE

+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)

+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)

+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)

+

+

+/*!< D1_AHB1PERIPH peripherals */

+

+#define MDMA_BASE             (D1_AHB1PERIPH_BASE + 0x0000UL)

+#define DMA2D_BASE            (D1_AHB1PERIPH_BASE + 0x1000UL)

+#define JPGDEC_BASE           (D1_AHB1PERIPH_BASE + 0x3000UL)

+#define FLASH_R_BASE          (D1_AHB1PERIPH_BASE + 0x2000UL)

+#define FMC_R_BASE            (D1_AHB1PERIPH_BASE + 0x4000UL)

+#define QSPI_R_BASE           (D1_AHB1PERIPH_BASE + 0x5000UL)

+#define DLYB_QSPI_BASE        (D1_AHB1PERIPH_BASE + 0x6000UL)

+#define SDMMC1_BASE           (D1_AHB1PERIPH_BASE + 0x7000UL)

+#define DLYB_SDMMC1_BASE      (D1_AHB1PERIPH_BASE + 0x8000UL)

+#define RAMECC1_BASE          (D1_AHB1PERIPH_BASE + 0x9000UL)

+

+/*!< D2_AHB1PERIPH peripherals */

+

+#define DMA1_BASE               (D2_AHB1PERIPH_BASE + 0x0000UL)

+#define DMA2_BASE               (D2_AHB1PERIPH_BASE + 0x0400UL)

+#define DMAMUX1_BASE            (D2_AHB1PERIPH_BASE + 0x0800UL)

+#define ADC1_BASE               (D2_AHB1PERIPH_BASE + 0x2000UL)

+#define ADC2_BASE               (D2_AHB1PERIPH_BASE + 0x2100UL)

+#define ADC12_COMMON_BASE       (D2_AHB1PERIPH_BASE + 0x2300UL)

+#define ART_BASE                (D2_AHB1PERIPH_BASE + 0x4400UL)

+#define ETH_BASE                (D2_AHB1PERIPH_BASE + 0x8000UL)

+#define ETH_MAC_BASE            (ETH_BASE)

+

+/*!< USB registers base address */

+#define USB1_OTG_HS_PERIPH_BASE              (0x40040000UL)

+#define USB2_OTG_FS_PERIPH_BASE              (0x40080000UL)

+#define USB_OTG_GLOBAL_BASE                  (0x000UL)

+#define USB_OTG_DEVICE_BASE                  (0x800UL)

+#define USB_OTG_IN_ENDPOINT_BASE             (0x900UL)

+#define USB_OTG_OUT_ENDPOINT_BASE            (0xB00UL)

+#define USB_OTG_EP_REG_SIZE                  (0x20UL)

+#define USB_OTG_HOST_BASE                    (0x400UL)

+#define USB_OTG_HOST_PORT_BASE               (0x440UL)

+#define USB_OTG_HOST_CHANNEL_BASE            (0x500UL)

+#define USB_OTG_HOST_CHANNEL_SIZE            (0x20UL)

+#define USB_OTG_PCGCCTL_BASE                 (0xE00UL)

+#define USB_OTG_FIFO_BASE                    (0x1000UL)

+#define USB_OTG_FIFO_SIZE                    (0x1000UL)

+

+/*!< D2_AHB2PERIPH peripherals */

+

+#define DCMI_BASE              (D2_AHB2PERIPH_BASE + 0x0000UL)

+#define CRYP_BASE              (D2_AHB2PERIPH_BASE + 0x1000UL)

+#define HASH_BASE              (D2_AHB2PERIPH_BASE + 0x1400UL)

+#define HASH_DIGEST_BASE       (D2_AHB2PERIPH_BASE + 0x1710UL)

+#define RNG_BASE               (D2_AHB2PERIPH_BASE + 0x1800UL)

+#define SDMMC2_BASE            (D2_AHB2PERIPH_BASE + 0x2400UL)

+#define DLYB_SDMMC2_BASE       (D2_AHB2PERIPH_BASE + 0x2800UL)

+#define RAMECC2_BASE           (D2_AHB2PERIPH_BASE + 0x3000UL)

+

+/*!< D3_AHB1PERIPH peripherals */

+#define GPIOA_BASE            (D3_AHB1PERIPH_BASE + 0x0000UL)

+#define GPIOB_BASE            (D3_AHB1PERIPH_BASE + 0x0400UL)

+#define GPIOC_BASE            (D3_AHB1PERIPH_BASE + 0x0800UL)

+#define GPIOD_BASE            (D3_AHB1PERIPH_BASE + 0x0C00UL)

+#define GPIOE_BASE            (D3_AHB1PERIPH_BASE + 0x1000UL)

+#define GPIOF_BASE            (D3_AHB1PERIPH_BASE + 0x1400UL)

+#define GPIOG_BASE            (D3_AHB1PERIPH_BASE + 0x1800UL)

+#define GPIOH_BASE            (D3_AHB1PERIPH_BASE + 0x1C00UL)

+#define GPIOI_BASE            (D3_AHB1PERIPH_BASE + 0x2000UL)

+#define GPIOJ_BASE            (D3_AHB1PERIPH_BASE + 0x2400UL)

+#define GPIOK_BASE            (D3_AHB1PERIPH_BASE + 0x2800UL)

+#define RCC_BASE              (D3_AHB1PERIPH_BASE + 0x4400UL)

+#define RCC_C1_BASE           (RCC_BASE + 0x130UL)

+#define RCC_C2_BASE           (RCC_BASE + 0x190UL)

+#define PWR_BASE              (D3_AHB1PERIPH_BASE + 0x4800UL)

+#define CRC_BASE              (D3_AHB1PERIPH_BASE + 0x4C00UL)

+#define BDMA_BASE             (D3_AHB1PERIPH_BASE + 0x5400UL)

+#define DMAMUX2_BASE          (D3_AHB1PERIPH_BASE + 0x5800UL)

+#define ADC3_BASE             (D3_AHB1PERIPH_BASE + 0x6000UL)

+#define ADC3_COMMON_BASE      (D3_AHB1PERIPH_BASE + 0x6300UL)

+#define HSEM_BASE             (D3_AHB1PERIPH_BASE + 0x6400UL)

+#define RAMECC3_BASE          (D3_AHB1PERIPH_BASE + 0x7000UL)

+

+/*!< D1_APB1PERIPH peripherals */

+#define LTDC_BASE             (D1_APB1PERIPH_BASE + 0x1000UL)

+#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84UL)

+#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104UL)

+#define WWDG1_BASE            (D1_APB1PERIPH_BASE + 0x3000UL)

+

+/*!< D2_APB1PERIPH peripherals */

+#define TIM2_BASE             (D2_APB1PERIPH_BASE + 0x0000UL)

+#define TIM3_BASE             (D2_APB1PERIPH_BASE + 0x0400UL)

+#define TIM4_BASE             (D2_APB1PERIPH_BASE + 0x0800UL)

+#define TIM5_BASE             (D2_APB1PERIPH_BASE + 0x0C00UL)

+#define TIM6_BASE             (D2_APB1PERIPH_BASE + 0x1000UL)

+#define TIM7_BASE             (D2_APB1PERIPH_BASE + 0x1400UL)

+#define TIM12_BASE            (D2_APB1PERIPH_BASE + 0x1800UL)

+#define TIM13_BASE            (D2_APB1PERIPH_BASE + 0x1C00UL)

+#define TIM14_BASE            (D2_APB1PERIPH_BASE + 0x2000UL)

+#define LPTIM1_BASE           (D2_APB1PERIPH_BASE + 0x2400UL)

+

+#define WWDG2_BASE            (D2_APB1PERIPH_BASE + 0x2C00UL)

+

+#define SPI2_BASE             (D2_APB1PERIPH_BASE + 0x3800UL)

+#define SPI3_BASE             (D2_APB1PERIPH_BASE + 0x3C00UL)

+#define SPDIFRX_BASE          (D2_APB1PERIPH_BASE + 0x4000UL)

+#define USART2_BASE           (D2_APB1PERIPH_BASE + 0x4400UL)

+#define USART3_BASE           (D2_APB1PERIPH_BASE + 0x4800UL)

+#define UART4_BASE            (D2_APB1PERIPH_BASE + 0x4C00UL)

+#define UART5_BASE            (D2_APB1PERIPH_BASE + 0x5000UL)

+#define I2C1_BASE             (D2_APB1PERIPH_BASE + 0x5400UL)

+#define I2C2_BASE             (D2_APB1PERIPH_BASE + 0x5800UL)

+#define I2C3_BASE             (D2_APB1PERIPH_BASE + 0x5C00UL)

+#define CEC_BASE              (D2_APB1PERIPH_BASE + 0x6C00UL)

+#define DAC1_BASE             (D2_APB1PERIPH_BASE + 0x7400UL)

+#define UART7_BASE            (D2_APB1PERIPH_BASE + 0x7800UL)

+#define UART8_BASE            (D2_APB1PERIPH_BASE + 0x7C00UL)

+#define CRS_BASE              (D2_APB1PERIPH_BASE + 0x8400UL)

+#define SWPMI1_BASE           (D2_APB1PERIPH_BASE + 0x8800UL)

+#define OPAMP_BASE            (D2_APB1PERIPH_BASE + 0x9000UL)

+#define OPAMP1_BASE           (D2_APB1PERIPH_BASE + 0x9000UL)

+#define OPAMP2_BASE           (D2_APB1PERIPH_BASE + 0x9010UL)

+#define MDIOS_BASE            (D2_APB1PERIPH_BASE + 0x9400UL)

+#define FDCAN1_BASE           (D2_APB1PERIPH_BASE + 0xA000UL)

+#define FDCAN2_BASE           (D2_APB1PERIPH_BASE + 0xA400UL)

+#define FDCAN_CCU_BASE        (D2_APB1PERIPH_BASE + 0xA800UL)

+#define SRAMCAN_BASE          (D2_APB1PERIPH_BASE + 0xAC00UL)

+

+/*!< D2_APB2PERIPH peripherals */

+

+#define TIM1_BASE             (D2_APB2PERIPH_BASE + 0x0000UL)

+#define TIM8_BASE             (D2_APB2PERIPH_BASE + 0x0400UL)

+#define USART1_BASE           (D2_APB2PERIPH_BASE + 0x1000UL)

+#define USART6_BASE           (D2_APB2PERIPH_BASE + 0x1400UL)

+#define SPI1_BASE             (D2_APB2PERIPH_BASE + 0x3000UL)

+#define SPI4_BASE             (D2_APB2PERIPH_BASE + 0x3400UL)

+#define TIM15_BASE            (D2_APB2PERIPH_BASE + 0x4000UL)

+#define TIM16_BASE            (D2_APB2PERIPH_BASE + 0x4400UL)

+#define TIM17_BASE            (D2_APB2PERIPH_BASE + 0x4800UL)

+#define SPI5_BASE             (D2_APB2PERIPH_BASE + 0x5000UL)

+#define SAI1_BASE             (D2_APB2PERIPH_BASE + 0x5800UL)

+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)

+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)

+#define SAI2_BASE             (D2_APB2PERIPH_BASE + 0x5C00UL)

+#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004UL)

+#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024UL)

+#define SAI3_BASE             (D2_APB2PERIPH_BASE + 0x6000UL)

+#define SAI3_Block_A_BASE     (SAI3_BASE + 0x004UL)

+#define SAI3_Block_B_BASE     (SAI3_BASE + 0x024UL)

+#define DFSDM1_BASE           (D2_APB2PERIPH_BASE + 0x7000UL)

+#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00UL)

+#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20UL)

+#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40UL)

+#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60UL)

+#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80UL)

+#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0UL)

+#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0UL)

+#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0UL)

+#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)

+#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)

+#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)

+#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)

+#define HRTIM1_BASE           (D2_APB2PERIPH_BASE + 0x7400UL)

+#define HRTIM1_TIMA_BASE      (HRTIM1_BASE + 0x00000080UL)

+#define HRTIM1_TIMB_BASE      (HRTIM1_BASE + 0x00000100UL)

+#define HRTIM1_TIMC_BASE      (HRTIM1_BASE + 0x00000180UL)

+#define HRTIM1_TIMD_BASE      (HRTIM1_BASE + 0x00000200UL)

+#define HRTIM1_TIME_BASE      (HRTIM1_BASE + 0x00000280UL)

+#define HRTIM1_COMMON_BASE    (HRTIM1_BASE + 0x00000380UL)

+

+

+/*!< D3_APB1PERIPH peripherals */

+#define EXTI_BASE             (D3_APB1PERIPH_BASE + 0x0000UL)

+#define EXTI_D1_BASE          (EXTI_BASE + 0x0080UL)

+#define EXTI_D2_BASE          (EXTI_BASE + 0x00C0UL)

+#define SYSCFG_BASE           (D3_APB1PERIPH_BASE + 0x0400UL)

+#define LPUART1_BASE          (D3_APB1PERIPH_BASE + 0x0C00UL)

+#define SPI6_BASE             (D3_APB1PERIPH_BASE + 0x1400UL)

+#define I2C4_BASE             (D3_APB1PERIPH_BASE + 0x1C00UL)

+#define LPTIM2_BASE           (D3_APB1PERIPH_BASE + 0x2400UL)

+#define LPTIM3_BASE           (D3_APB1PERIPH_BASE + 0x2800UL)

+#define LPTIM4_BASE           (D3_APB1PERIPH_BASE + 0x2C00UL)

+#define LPTIM5_BASE           (D3_APB1PERIPH_BASE + 0x3000UL)

+#define COMP12_BASE           (D3_APB1PERIPH_BASE + 0x3800UL)

+#define COMP1_BASE            (COMP12_BASE + 0x0CUL)

+#define COMP2_BASE            (COMP12_BASE + 0x10UL)

+#define VREFBUF_BASE          (D3_APB1PERIPH_BASE + 0x3C00UL)

+#define RTC_BASE              (D3_APB1PERIPH_BASE + 0x4000UL)

+#define IWDG1_BASE            (D3_APB1PERIPH_BASE + 0x4800UL)

+

+#define IWDG2_BASE            (D3_APB1PERIPH_BASE + 0x4C00UL)

+

+#define SAI4_BASE             (D3_APB1PERIPH_BASE + 0x5400UL)

+#define SAI4_Block_A_BASE     (SAI4_BASE + 0x004UL)

+#define SAI4_Block_B_BASE     (SAI4_BASE + 0x024UL)

+

+

+

+

+#define BDMA_Channel0_BASE    (BDMA_BASE + 0x0008UL)

+#define BDMA_Channel1_BASE    (BDMA_BASE + 0x001CUL)

+#define BDMA_Channel2_BASE    (BDMA_BASE + 0x0030UL)

+#define BDMA_Channel3_BASE    (BDMA_BASE + 0x0044UL)

+#define BDMA_Channel4_BASE    (BDMA_BASE + 0x0058UL)

+#define BDMA_Channel5_BASE    (BDMA_BASE + 0x006CUL)

+#define BDMA_Channel6_BASE    (BDMA_BASE + 0x0080UL)

+#define BDMA_Channel7_BASE    (BDMA_BASE + 0x0094UL)

+

+#define DMAMUX2_Channel0_BASE    (DMAMUX2_BASE)

+#define DMAMUX2_Channel1_BASE    (DMAMUX2_BASE + 0x0004UL)

+#define DMAMUX2_Channel2_BASE    (DMAMUX2_BASE + 0x0008UL)

+#define DMAMUX2_Channel3_BASE    (DMAMUX2_BASE + 0x000CUL)

+#define DMAMUX2_Channel4_BASE    (DMAMUX2_BASE + 0x0010UL)

+#define DMAMUX2_Channel5_BASE    (DMAMUX2_BASE + 0x0014UL)

+#define DMAMUX2_Channel6_BASE    (DMAMUX2_BASE + 0x0018UL)

+#define DMAMUX2_Channel7_BASE    (DMAMUX2_BASE + 0x001CUL)

+

+#define DMAMUX2_RequestGenerator0_BASE  (DMAMUX2_BASE + 0x0100UL)

+#define DMAMUX2_RequestGenerator1_BASE  (DMAMUX2_BASE + 0x0104UL)

+#define DMAMUX2_RequestGenerator2_BASE  (DMAMUX2_BASE + 0x0108UL)

+#define DMAMUX2_RequestGenerator3_BASE  (DMAMUX2_BASE + 0x010CUL)

+#define DMAMUX2_RequestGenerator4_BASE  (DMAMUX2_BASE + 0x0110UL)

+#define DMAMUX2_RequestGenerator5_BASE  (DMAMUX2_BASE + 0x0114UL)

+#define DMAMUX2_RequestGenerator6_BASE  (DMAMUX2_BASE + 0x0118UL)

+#define DMAMUX2_RequestGenerator7_BASE  (DMAMUX2_BASE + 0x011CUL)

+

+#define DMAMUX2_ChannelStatus_BASE      (DMAMUX2_BASE + 0x0080UL)

+#define DMAMUX2_RequestGenStatus_BASE   (DMAMUX2_BASE + 0x0140UL)

+

+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)

+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)

+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)

+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)

+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)

+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)

+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)

+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)

+

+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)

+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)

+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)

+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)

+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)

+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)

+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)

+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)

+

+#define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)

+#define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)

+#define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)

+#define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)

+#define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)

+#define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)

+#define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0018UL)

+#define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x001CUL)

+#define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0020UL)

+#define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x0024UL)

+#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)

+#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)

+#define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)

+#define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)

+#define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)

+#define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)

+

+#define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)

+#define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)

+#define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)

+#define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)

+#define DMAMUX1_RequestGenerator4_BASE  (DMAMUX1_BASE + 0x0110UL)

+#define DMAMUX1_RequestGenerator5_BASE  (DMAMUX1_BASE + 0x0114UL)

+#define DMAMUX1_RequestGenerator6_BASE  (DMAMUX1_BASE + 0x0118UL)

+#define DMAMUX1_RequestGenerator7_BASE  (DMAMUX1_BASE + 0x011CUL)

+

+#define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)

+#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)

+

+/*!< FMC Banks registers base  address */

+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)

+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)

+#define FMC_Bank2_R_BASE      (FMC_R_BASE + 0x0060UL)

+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)

+#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)

+

+/* Debug MCU registers base address */

+#define DBGMCU_BASE           (0x5C001000UL)

+

+#define MDMA_Channel0_BASE    (MDMA_BASE + 0x00000040UL)

+#define MDMA_Channel1_BASE    (MDMA_BASE + 0x00000080UL)

+#define MDMA_Channel2_BASE    (MDMA_BASE + 0x000000C0UL)

+#define MDMA_Channel3_BASE    (MDMA_BASE + 0x00000100UL)

+#define MDMA_Channel4_BASE    (MDMA_BASE + 0x00000140UL)

+#define MDMA_Channel5_BASE    (MDMA_BASE + 0x00000180UL)

+#define MDMA_Channel6_BASE    (MDMA_BASE + 0x000001C0UL)

+#define MDMA_Channel7_BASE    (MDMA_BASE + 0x00000200UL)

+#define MDMA_Channel8_BASE    (MDMA_BASE + 0x00000240UL)

+#define MDMA_Channel9_BASE    (MDMA_BASE + 0x00000280UL)

+#define MDMA_Channel10_BASE   (MDMA_BASE + 0x000002C0UL)

+#define MDMA_Channel11_BASE   (MDMA_BASE + 0x00000300UL)

+#define MDMA_Channel12_BASE   (MDMA_BASE + 0x00000340UL)

+#define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)

+#define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)

+#define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)

+

+#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)

+#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)

+#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)

+#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)

+#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)

+

+#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)

+#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)

+#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)

+#define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL)

+#define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL)

+

+#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)

+#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)

+

+

+/**

+  * @}

+  */

+

+/** @addtogroup Peripheral_declaration

+  * @{

+  */

+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)

+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)

+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)

+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)

+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)

+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)

+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)

+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)

+#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)

+#define RTC                 ((RTC_TypeDef *) RTC_BASE)

+#define WWDG1               ((WWDG_TypeDef *) WWDG1_BASE)

+

+#define WWDG2               ((WWDG_TypeDef *) WWDG2_BASE)

+#define IWDG2               ((IWDG_TypeDef *) IWDG2_BASE)

+

+#define IWDG1               ((IWDG_TypeDef *) IWDG1_BASE)

+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)

+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)

+#define SPI4                ((SPI_TypeDef *) SPI4_BASE)

+#define SPI5                ((SPI_TypeDef *) SPI5_BASE)

+#define SPI6                ((SPI_TypeDef *) SPI6_BASE)

+#define USART2              ((USART_TypeDef *) USART2_BASE)

+#define USART3              ((USART_TypeDef *) USART3_BASE)

+#define USART6              ((USART_TypeDef *) USART6_BASE)

+#define UART7               ((USART_TypeDef *) UART7_BASE)

+#define UART8               ((USART_TypeDef *) UART8_BASE)

+#define CRS                 ((CRS_TypeDef *) CRS_BASE)

+#define UART4               ((USART_TypeDef *) UART4_BASE)

+#define UART5               ((USART_TypeDef *) UART5_BASE)

+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)

+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)

+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)

+#define I2C4                ((I2C_TypeDef *) I2C4_BASE)

+#define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

+#define FDCAN2              ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

+#define FDCAN_CCU           ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

+#define CEC                 ((CEC_TypeDef *) CEC_BASE)

+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)

+#define PWR                 ((PWR_TypeDef *) PWR_BASE)

+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)

+#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)

+#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)

+#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)

+#define LPTIM3              ((LPTIM_TypeDef *) LPTIM3_BASE)

+#define LPTIM4              ((LPTIM_TypeDef *) LPTIM4_BASE)

+#define LPTIM5              ((LPTIM_TypeDef *) LPTIM5_BASE)

+

+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)

+#define COMP12              ((COMPOPT_TypeDef *) COMP12_BASE)

+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)

+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)

+#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)

+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)

+#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)

+#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)

+

+

+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)

+#define EXTI_D1             ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

+#define EXTI_D2             ((EXTI_Core_TypeDef *) EXTI_D2_BASE)

+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)

+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)

+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)

+#define USART1              ((USART_TypeDef *) USART1_BASE)

+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)

+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)

+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)

+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)

+#define HRTIM1              ((HRTIM_TypeDef *) HRTIM1_BASE)

+#define HRTIM1_TIMA         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)

+#define HRTIM1_TIMB         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)

+#define HRTIM1_TIMC         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)

+#define HRTIM1_TIMD         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)

+#define HRTIM1_TIME         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)

+#define HRTIM1_COMMON       ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)

+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)

+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

+#define SAI2                ((SAI_TypeDef *) SAI2_BASE)

+#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)

+#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)

+#define SAI3                ((SAI_TypeDef *) SAI3_BASE)

+#define SAI3_Block_A        ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)

+#define SAI3_Block_B        ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)

+#define SAI4                ((SAI_TypeDef *) SAI4_BASE)

+#define SAI4_Block_A        ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)

+#define SAI4_Block_B        ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)

+

+#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

+#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

+#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

+#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

+#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

+#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

+#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

+#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

+#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

+#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

+#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

+#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

+#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

+#define DMA2D               ((DMA2D_TypeDef *) DMA2D_BASE)

+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)

+#define RCC                 ((RCC_TypeDef *) RCC_BASE)

+#define RCC_C1              ((RCC_Core_TypeDef *) RCC_C1_BASE)

+#define RCC_C2              ((RCC_Core_TypeDef *) RCC_C2_BASE)

+

+#define ART                 ((ART_TypeDef *)  ART_BASE)

+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)

+#define CRC                 ((CRC_TypeDef *) CRC_BASE)

+

+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)

+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)

+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)

+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)

+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)

+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)

+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)

+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)

+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)

+#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)

+#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)

+

+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)

+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)

+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)

+#define ADC3_COMMON         ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)

+#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

+

+#define CRYP                ((CRYP_TypeDef *) CRYP_BASE)

+#define HASH                ((HASH_TypeDef *) HASH_BASE)

+#define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)

+#define RNG                 ((RNG_TypeDef *) RNG_BASE)

+#define SDMMC2              ((SDMMC_TypeDef *) SDMMC2_BASE)

+#define DLYB_SDMMC2         ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

+

+#define BDMA                ((BDMA_TypeDef *) BDMA_BASE)

+#define BDMA_Channel0       ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)

+#define BDMA_Channel1       ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)

+#define BDMA_Channel2       ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)

+#define BDMA_Channel3       ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)

+#define BDMA_Channel4       ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)

+#define BDMA_Channel5       ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)

+#define BDMA_Channel6       ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)

+#define BDMA_Channel7       ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)

+

+#define RAMECC1              ((RAMECC_TypeDef *)RAMECC1_BASE)

+#define RAMECC1_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)

+#define RAMECC1_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)

+#define RAMECC1_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)

+#define RAMECC1_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)

+#define RAMECC1_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)

+

+#define RAMECC2              ((RAMECC_TypeDef *)RAMECC2_BASE)

+#define RAMECC2_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)

+#define RAMECC2_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)

+#define RAMECC2_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)

+#define RAMECC2_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)

+#define RAMECC2_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)

+

+#define RAMECC3              ((RAMECC_TypeDef *)RAMECC3_BASE)

+#define RAMECC3_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)

+#define RAMECC3_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)

+

+#define DMAMUX2                ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

+#define DMAMUX2_Channel0       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

+#define DMAMUX2_Channel1       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

+#define DMAMUX2_Channel2       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

+#define DMAMUX2_Channel3       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

+#define DMAMUX2_Channel4       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

+#define DMAMUX2_Channel5       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

+#define DMAMUX2_Channel6       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

+#define DMAMUX2_Channel7       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

+

+

+#define DMAMUX2_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

+#define DMAMUX2_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

+#define DMAMUX2_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

+#define DMAMUX2_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

+#define DMAMUX2_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

+#define DMAMUX2_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

+#define DMAMUX2_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

+#define DMAMUX2_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

+

+#define DMAMUX2_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

+#define DMAMUX2_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

+

+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)

+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

+

+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)

+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

+

+

+#define DMAMUX1              ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

+#define DMAMUX1_Channel0     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

+#define DMAMUX1_Channel1     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

+#define DMAMUX1_Channel2     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

+#define DMAMUX1_Channel3     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

+#define DMAMUX1_Channel4     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

+#define DMAMUX1_Channel5     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

+#define DMAMUX1_Channel6     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

+#define DMAMUX1_Channel7     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

+#define DMAMUX1_Channel8     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

+#define DMAMUX1_Channel9     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

+#define DMAMUX1_Channel10    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

+#define DMAMUX1_Channel11    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

+#define DMAMUX1_Channel12    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

+#define DMAMUX1_Channel13    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

+#define DMAMUX1_Channel14    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

+#define DMAMUX1_Channel15    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

+

+#define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

+#define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

+#define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

+#define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

+#define DMAMUX1_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

+#define DMAMUX1_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

+#define DMAMUX1_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

+#define DMAMUX1_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

+

+#define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *)    DMAMUX1_ChannelStatus_BASE)

+#define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

+

+

+#define FMC_Bank1_R           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

+#define FMC_Bank1E_R          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

+#define FMC_Bank2_R           ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

+#define FMC_Bank3_R           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

+#define FMC_Bank5_6_R         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

+

+

+#define QUADSPI               ((QUADSPI_TypeDef *) QSPI_R_BASE)

+#define DLYB_QUADSPI          ((DLYB_TypeDef *) DLYB_QSPI_BASE)

+#define SDMMC1                ((SDMMC_TypeDef *) SDMMC1_BASE)

+#define DLYB_SDMMC1           ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

+

+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)

+

+#define JPEG                ((JPEG_TypeDef *) JPGDEC_BASE)

+#define HSEM                ((HSEM_TypeDef *) HSEM_BASE)

+#if defined(CORE_CM4)

+#define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x110UL))

+#else  /* CORE_CM7 */

+#define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

+#endif /* CORE_CM4 */

+

+#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)

+#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

+#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

+

+#define MDIOS               ((MDIOS_TypeDef *) MDIOS_BASE)

+

+#define ETH                 ((ETH_TypeDef *)ETH_BASE)

+#define MDMA                ((MDMA_TypeDef *)MDMA_BASE)

+#define MDMA_Channel0       ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

+#define MDMA_Channel1       ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

+#define MDMA_Channel2       ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

+#define MDMA_Channel3       ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

+#define MDMA_Channel4       ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

+#define MDMA_Channel5       ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

+#define MDMA_Channel6       ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

+#define MDMA_Channel7       ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

+#define MDMA_Channel8       ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

+#define MDMA_Channel9       ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

+#define MDMA_Channel10      ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

+#define MDMA_Channel11      ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

+#define MDMA_Channel12      ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

+#define MDMA_Channel13      ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

+#define MDMA_Channel14      ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

+#define MDMA_Channel15      ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

+

+

+#define USB1_OTG_HS         ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

+#define USB2_OTG_FS         ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)

+

+/* Legacy defines */

+#define USB_OTG_HS                   USB1_OTG_HS

+#define USB_OTG_HS_PERIPH_BASE       USB1_OTG_HS_PERIPH_BASE

+#define USB_OTG_FS                   USB2_OTG_FS

+#define USB_OTG_FS_PERIPH_BASE       USB2_OTG_FS_PERIPH_BASE

+

+/**

+  * @}

+  */

+

+/** @addtogroup Exported_constants

+  * @{

+  */

+

+  /** @addtogroup Peripheral_Registers_Bits_Definition

+  * @{

+  */

+

+/******************************************************************************/

+/*                         Peripheral Registers_Bits_Definition               */

+/******************************************************************************/

+

+/******************************************************************************/

+/*                                                                            */

+/*                        Analog to Digital Converter                         */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  ADC VERSION  ********************************/

+#define ADC_VER_V5_X

+/********************  Bit definition for ADC_ISR register  ********************/

+#define ADC_ISR_ADRDY_Pos                 (0U)

+#define ADC_ISR_ADRDY_Msk                 (0x1UL << ADC_ISR_ADRDY_Pos)         /*!< 0x00000001 */

+#define ADC_ISR_ADRDY                     ADC_ISR_ADRDY_Msk                    /*!< ADC Ready (ADRDY) flag  */

+#define ADC_ISR_EOSMP_Pos                 (1U)

+#define ADC_ISR_EOSMP_Msk                 (0x1UL << ADC_ISR_EOSMP_Pos)         /*!< 0x00000002 */

+#define ADC_ISR_EOSMP                     ADC_ISR_EOSMP_Msk                    /*!< ADC End of Sampling flag */

+#define ADC_ISR_EOC_Pos                   (2U)

+#define ADC_ISR_EOC_Msk                   (0x1UL << ADC_ISR_EOC_Pos)           /*!< 0x00000004 */

+#define ADC_ISR_EOC                       ADC_ISR_EOC_Msk                      /*!< ADC End of Regular Conversion flag */

+#define ADC_ISR_EOS_Pos                   (3U)

+#define ADC_ISR_EOS_Msk                   (0x1UL << ADC_ISR_EOS_Pos)           /*!< 0x00000008 */

+#define ADC_ISR_EOS                       ADC_ISR_EOS_Msk                      /*!< ADC End of Regular sequence of Conversions flag */

+#define ADC_ISR_OVR_Pos                   (4U)

+#define ADC_ISR_OVR_Msk                   (0x1UL << ADC_ISR_OVR_Pos)           /*!< 0x00000010 */

+#define ADC_ISR_OVR                       ADC_ISR_OVR_Msk                      /*!< ADC overrun flag */

+#define ADC_ISR_JEOC_Pos                  (5U)

+#define ADC_ISR_JEOC_Msk                  (0x1UL << ADC_ISR_JEOC_Pos)          /*!< 0x00000020 */

+#define ADC_ISR_JEOC                      ADC_ISR_JEOC_Msk                     /*!< ADC End of Injected Conversion flag */

+#define ADC_ISR_JEOS_Pos                  (6U)

+#define ADC_ISR_JEOS_Msk                  (0x1UL << ADC_ISR_JEOS_Pos)          /*!< 0x00000040 */

+#define ADC_ISR_JEOS                      ADC_ISR_JEOS_Msk                     /*!< ADC End of Injected sequence of Conversions flag */

+#define ADC_ISR_AWD1_Pos                  (7U)

+#define ADC_ISR_AWD1_Msk                  (0x1UL << ADC_ISR_AWD1_Pos)          /*!< 0x00000080 */

+#define ADC_ISR_AWD1                      ADC_ISR_AWD1_Msk                     /*!< ADC Analog watchdog 1 flag */

+#define ADC_ISR_AWD2_Pos                  (8U)

+#define ADC_ISR_AWD2_Msk                  (0x1UL << ADC_ISR_AWD2_Pos)          /*!< 0x00000100 */

+#define ADC_ISR_AWD2                      ADC_ISR_AWD2_Msk                     /*!< ADC Analog watchdog 2 flag */

+#define ADC_ISR_AWD3_Pos                  (9U)

+#define ADC_ISR_AWD3_Msk                  (0x1UL << ADC_ISR_AWD3_Pos)          /*!< 0x00000200 */

+#define ADC_ISR_AWD3                      ADC_ISR_AWD3_Msk                     /*!< ADC Analog watchdog 3 flag */

+#define ADC_ISR_JQOVF_Pos                 (10U)

+#define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */

+#define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */

+

+/********************  Bit definition for ADC_IER register  ********************/

+#define ADC_IER_ADRDYIE_Pos               (0U)

+#define ADC_IER_ADRDYIE_Msk               (0x1UL << ADC_IER_ADRDYIE_Pos)       /*!< 0x00000001 */

+#define ADC_IER_ADRDYIE                   ADC_IER_ADRDYIE_Msk                  /*!< ADC Ready (ADRDY) interrupt source */

+#define ADC_IER_EOSMPIE_Pos               (1U)

+#define ADC_IER_EOSMPIE_Msk               (0x1UL << ADC_IER_EOSMPIE_Pos)       /*!< 0x00000002 */

+#define ADC_IER_EOSMPIE                   ADC_IER_EOSMPIE_Msk                  /*!< ADC End of Sampling interrupt source */

+#define ADC_IER_EOCIE_Pos                 (2U)

+#define ADC_IER_EOCIE_Msk                 (0x1UL << ADC_IER_EOCIE_Pos)         /*!< 0x00000004 */

+#define ADC_IER_EOCIE                     ADC_IER_EOCIE_Msk                    /*!< ADC End of Regular Conversion interrupt source */

+#define ADC_IER_EOSIE_Pos                 (3U)

+#define ADC_IER_EOSIE_Msk                 (0x1UL << ADC_IER_EOSIE_Pos)         /*!< 0x00000008 */

+#define ADC_IER_EOSIE                     ADC_IER_EOSIE_Msk                    /*!< ADC End of Regular sequence of Conversions interrupt source */

+#define ADC_IER_OVRIE_Pos                 (4U)

+#define ADC_IER_OVRIE_Msk                 (0x1UL << ADC_IER_OVRIE_Pos)         /*!< 0x00000010 */

+#define ADC_IER_OVRIE                     ADC_IER_OVRIE_Msk                    /*!< ADC overrun interrupt source */

+#define ADC_IER_JEOCIE_Pos                (5U)

+#define ADC_IER_JEOCIE_Msk                (0x1UL << ADC_IER_JEOCIE_Pos)        /*!< 0x00000020 */

+#define ADC_IER_JEOCIE                    ADC_IER_JEOCIE_Msk                   /*!< ADC End of Injected Conversion interrupt source */

+#define ADC_IER_JEOSIE_Pos                (6U)

+#define ADC_IER_JEOSIE_Msk                (0x1UL << ADC_IER_JEOSIE_Pos)        /*!< 0x00000040 */

+#define ADC_IER_JEOSIE                    ADC_IER_JEOSIE_Msk                   /*!< ADC End of Injected sequence of Conversions interrupt source */

+#define ADC_IER_AWD1IE_Pos                (7U)

+#define ADC_IER_AWD1IE_Msk                (0x1UL << ADC_IER_AWD1IE_Pos)        /*!< 0x00000080 */

+#define ADC_IER_AWD1IE                    ADC_IER_AWD1IE_Msk                   /*!< ADC Analog watchdog 1 interrupt source */

+#define ADC_IER_AWD2IE_Pos                (8U)

+#define ADC_IER_AWD2IE_Msk                (0x1UL << ADC_IER_AWD2IE_Pos)        /*!< 0x00000100 */

+#define ADC_IER_AWD2IE                    ADC_IER_AWD2IE_Msk                   /*!< ADC Analog watchdog 2 interrupt source */

+#define ADC_IER_AWD3IE_Pos                (9U)

+#define ADC_IER_AWD3IE_Msk                (0x1UL << ADC_IER_AWD3IE_Pos)        /*!< 0x00000200 */

+#define ADC_IER_AWD3IE                    ADC_IER_AWD3IE_Msk                   /*!< ADC Analog watchdog 3 interrupt source */

+#define ADC_IER_JQOVFIE_Pos               (10U)

+#define ADC_IER_JQOVFIE_Msk               (0x1UL << ADC_IER_JQOVFIE_Pos)       /*!< 0x00000400 */

+#define ADC_IER_JQOVFIE                   ADC_IER_JQOVFIE_Msk                  /*!< ADC Injected Context Queue Overflow interrupt source */

+

+/********************  Bit definition for ADC_CR register  ********************/

+#define ADC_CR_ADEN_Pos                   (0U)

+#define ADC_CR_ADEN_Msk                   (0x1UL << ADC_CR_ADEN_Pos)           /*!< 0x00000001 */

+#define ADC_CR_ADEN                       ADC_CR_ADEN_Msk                      /*!< ADC Enable control */

+#define ADC_CR_ADDIS_Pos                  (1U)

+#define ADC_CR_ADDIS_Msk                  (0x1UL << ADC_CR_ADDIS_Pos)          /*!< 0x00000002 */

+#define ADC_CR_ADDIS                      ADC_CR_ADDIS_Msk                     /*!< ADC Disable command */

+#define ADC_CR_ADSTART_Pos                (2U)

+#define ADC_CR_ADSTART_Msk                (0x1UL << ADC_CR_ADSTART_Pos)        /*!< 0x00000004 */

+#define ADC_CR_ADSTART                    ADC_CR_ADSTART_Msk                   /*!< ADC Start of Regular conversion */

+#define ADC_CR_JADSTART_Pos               (3U)

+#define ADC_CR_JADSTART_Msk               (0x1UL << ADC_CR_JADSTART_Pos)       /*!< 0x00000008 */

+#define ADC_CR_JADSTART                   ADC_CR_JADSTART_Msk                  /*!< ADC Start of injected conversion */

+#define ADC_CR_ADSTP_Pos                  (4U)

+#define ADC_CR_ADSTP_Msk                  (0x1UL << ADC_CR_ADSTP_Pos)          /*!< 0x00000010 */

+#define ADC_CR_ADSTP                      ADC_CR_ADSTP_Msk                     /*!< ADC Stop of Regular conversion */

+#define ADC_CR_JADSTP_Pos                 (5U)

+#define ADC_CR_JADSTP_Msk                 (0x1UL << ADC_CR_JADSTP_Pos)         /*!< 0x00000020 */

+#define ADC_CR_JADSTP                     ADC_CR_JADSTP_Msk                    /*!< ADC Stop of injected conversion */

+#define ADC_CR_BOOST_Pos                  (8U)

+#define ADC_CR_BOOST_Msk                  (0x3UL << ADC_CR_BOOST_Pos)          /*!< 0x00000300 */

+#define ADC_CR_BOOST                      ADC_CR_BOOST_Msk                     /*!< ADC Boost Mode configuration */

+#define ADC_CR_BOOST_0                    (0x1UL << ADC_CR_BOOST_Pos)           /*!< 0x00000100 */

+#define ADC_CR_BOOST_1                    (0x2UL << ADC_CR_BOOST_Pos)           /*!< 0x00000200 */

+#define ADC_CR_ADCALLIN_Pos               (16U)

+#define ADC_CR_ADCALLIN_Msk               (0x1UL << ADC_CR_ADCALLIN_Pos)       /*!< 0x00010000 */

+#define ADC_CR_ADCALLIN                   ADC_CR_ADCALLIN_Msk                  /*!< ADC Linearity calibration */

+#define ADC_CR_LINCALRDYW1_Pos            (22U)

+#define ADC_CR_LINCALRDYW1_Msk            (0x1UL << ADC_CR_LINCALRDYW1_Pos)    /*!< 0x00400000 */

+#define ADC_CR_LINCALRDYW1                ADC_CR_LINCALRDYW1_Msk               /*!< ADC Linearity calibration ready Word 1 */

+#define ADC_CR_LINCALRDYW2_Pos            (23U)

+#define ADC_CR_LINCALRDYW2_Msk            (0x1UL << ADC_CR_LINCALRDYW2_Pos)    /*!< 0x00800000 */

+#define ADC_CR_LINCALRDYW2                ADC_CR_LINCALRDYW2_Msk               /*!< ADC Linearity calibration ready Word 2 */

+#define ADC_CR_LINCALRDYW3_Pos            (24U)

+#define ADC_CR_LINCALRDYW3_Msk            (0x1UL << ADC_CR_LINCALRDYW3_Pos)    /*!< 0x01000000 */

+#define ADC_CR_LINCALRDYW3                ADC_CR_LINCALRDYW3_Msk               /*!< ADC Linearity calibration ready Word 3 */

+#define ADC_CR_LINCALRDYW4_Pos            (25U)

+#define ADC_CR_LINCALRDYW4_Msk            (0x1UL << ADC_CR_LINCALRDYW4_Pos)    /*!< 0x02000000 */

+#define ADC_CR_LINCALRDYW4                ADC_CR_LINCALRDYW4_Msk               /*!< ADC Linearity calibration ready Word 4 */

+#define ADC_CR_LINCALRDYW5_Pos            (26U)

+#define ADC_CR_LINCALRDYW5_Msk            (0x1UL << ADC_CR_LINCALRDYW5_Pos)    /*!< 0x04000000 */

+#define ADC_CR_LINCALRDYW5                ADC_CR_LINCALRDYW5_Msk               /*!< ADC Linearity calibration ready Word 5 */

+#define ADC_CR_LINCALRDYW6_Pos            (27U)

+#define ADC_CR_LINCALRDYW6_Msk            (0x1UL << ADC_CR_LINCALRDYW6_Pos)    /*!< 0x08000000 */

+#define ADC_CR_LINCALRDYW6                ADC_CR_LINCALRDYW6_Msk               /*!< ADC Linearity calibration ready Word 6 */

+#define ADC_CR_ADVREGEN_Pos               (28U)

+#define ADC_CR_ADVREGEN_Msk               (0x1UL << ADC_CR_ADVREGEN_Pos)       /*!< 0x10000000 */

+#define ADC_CR_ADVREGEN                   ADC_CR_ADVREGEN_Msk                  /*!< ADC Voltage regulator Enable */

+#define ADC_CR_DEEPPWD_Pos                (29U)

+#define ADC_CR_DEEPPWD_Msk                (0x1UL << ADC_CR_DEEPPWD_Pos)        /*!< 0x20000000 */

+#define ADC_CR_DEEPPWD                    ADC_CR_DEEPPWD_Msk                   /*!< ADC Deep power down Enable */

+#define ADC_CR_ADCALDIF_Pos               (30U)

+#define ADC_CR_ADCALDIF_Msk               (0x1UL << ADC_CR_ADCALDIF_Pos)       /*!< 0x40000000 */

+#define ADC_CR_ADCALDIF                   ADC_CR_ADCALDIF_Msk                  /*!< ADC Differential Mode for calibration */

+#define ADC_CR_ADCAL_Pos                  (31U)

+#define ADC_CR_ADCAL_Msk                  (0x1UL << ADC_CR_ADCAL_Pos)          /*!< 0x80000000 */

+#define ADC_CR_ADCAL                      ADC_CR_ADCAL_Msk                     /*!< ADC Calibration */

+

+/********************  Bit definition for ADC_CFGR register  ********************/

+#define ADC_CFGR_DMNGT_Pos                (0U)

+#define ADC_CFGR_DMNGT_Msk                (0x3UL << ADC_CFGR_DMNGT_Pos)        /*!< 0x00000003 */

+#define ADC_CFGR_DMNGT                    ADC_CFGR_DMNGT_Msk                   /*!< ADC Data Management configuration */

+#define ADC_CFGR_DMNGT_0                  (0x1UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000001 */

+#define ADC_CFGR_DMNGT_1                  (0x2UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000002 */

+

+#define ADC_CFGR_RES_Pos                  (2U)

+#define ADC_CFGR_RES_Msk                  (0x7UL << ADC_CFGR_RES_Pos)          /*!< 0x0000001C */

+#define ADC_CFGR_RES                      ADC_CFGR_RES_Msk                     /*!< ADC Data resolution */

+#define ADC_CFGR_RES_0                    (0x1UL << ADC_CFGR_RES_Pos)           /*!< 0x00000004 */

+#define ADC_CFGR_RES_1                    (0x2UL << ADC_CFGR_RES_Pos)           /*!< 0x00000008 */

+#define ADC_CFGR_RES_2                    (0x4UL << ADC_CFGR_RES_Pos)           /*!< 0x00000010 */

+

+#define ADC_CFGR_EXTSEL_Pos               (5U)

+#define ADC_CFGR_EXTSEL_Msk               (0x1FUL << ADC_CFGR_EXTSEL_Pos)      /*!< 0x000003E0 */

+#define ADC_CFGR_EXTSEL                   ADC_CFGR_EXTSEL_Msk                  /*!< ADC External trigger selection for regular group */

+#define ADC_CFGR_EXTSEL_0                 (0x01UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000020 */

+#define ADC_CFGR_EXTSEL_1                 (0x02UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000040 */

+#define ADC_CFGR_EXTSEL_2                 (0x04UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000080 */

+#define ADC_CFGR_EXTSEL_3                 (0x08UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000100 */

+#define ADC_CFGR_EXTSEL_4                 (0x10UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000200 */

+

+#define ADC_CFGR_EXTEN_Pos                (10U)

+#define ADC_CFGR_EXTEN_Msk                (0x3UL << ADC_CFGR_EXTEN_Pos)        /*!< 0x00000C00 */

+#define ADC_CFGR_EXTEN                    ADC_CFGR_EXTEN_Msk                   /*!< ADC External trigger enable and polarity selection for regular channels */

+#define ADC_CFGR_EXTEN_0                  (0x1UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000400 */

+#define ADC_CFGR_EXTEN_1                  (0x2UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000800 */

+

+#define ADC_CFGR_OVRMOD_Pos               (12U)

+#define ADC_CFGR_OVRMOD_Msk               (0x1UL << ADC_CFGR_OVRMOD_Pos)       /*!< 0x00001000 */

+#define ADC_CFGR_OVRMOD                   ADC_CFGR_OVRMOD_Msk                  /*!< ADC overrun mode */

+#define ADC_CFGR_CONT_Pos                 (13U)

+#define ADC_CFGR_CONT_Msk                 (0x1UL << ADC_CFGR_CONT_Pos)         /*!< 0x00002000 */

+#define ADC_CFGR_CONT                     ADC_CFGR_CONT_Msk                    /*!< ADC Single/continuous conversion mode for regular conversion */

+#define ADC_CFGR_AUTDLY_Pos               (14U)

+#define ADC_CFGR_AUTDLY_Msk               (0x1UL << ADC_CFGR_AUTDLY_Pos)       /*!< 0x00004000 */

+#define ADC_CFGR_AUTDLY                   ADC_CFGR_AUTDLY_Msk                  /*!< ADC Delayed conversion mode */

+

+#define ADC_CFGR_DISCEN_Pos               (16U)

+#define ADC_CFGR_DISCEN_Msk               (0x1UL << ADC_CFGR_DISCEN_Pos)       /*!< 0x00010000 */

+#define ADC_CFGR_DISCEN                   ADC_CFGR_DISCEN_Msk                  /*!< ADC Discontinuous mode for regular channels */

+

+#define ADC_CFGR_DISCNUM_Pos              (17U)

+#define ADC_CFGR_DISCNUM_Msk              (0x7UL << ADC_CFGR_DISCNUM_Pos)      /*!< 0x000E0000 */

+#define ADC_CFGR_DISCNUM                  ADC_CFGR_DISCNUM_Msk                 /*!< ADC Discontinuous mode channel count */

+#define ADC_CFGR_DISCNUM_0                (0x1UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00020000 */

+#define ADC_CFGR_DISCNUM_1                (0x2UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00040000 */

+#define ADC_CFGR_DISCNUM_2                (0x4UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00080000 */

+

+#define ADC_CFGR_JDISCEN_Pos              (20U)

+#define ADC_CFGR_JDISCEN_Msk              (0x1UL << ADC_CFGR_JDISCEN_Pos)      /*!< 0x00100000 */

+#define ADC_CFGR_JDISCEN                  ADC_CFGR_JDISCEN_Msk                 /*!< ADC Discontinuous mode on injected channels */

+#define ADC_CFGR_JQM_Pos                  (21U)

+#define ADC_CFGR_JQM_Msk                  (0x1UL << ADC_CFGR_JQM_Pos)          /*!< 0x00200000 */

+#define ADC_CFGR_JQM                      ADC_CFGR_JQM_Msk                     /*!< ADC JSQR Queue mode */

+#define ADC_CFGR_AWD1SGL_Pos              (22U)

+#define ADC_CFGR_AWD1SGL_Msk              (0x1UL << ADC_CFGR_AWD1SGL_Pos)      /*!< 0x00400000 */

+#define ADC_CFGR_AWD1SGL                  ADC_CFGR_AWD1SGL_Msk                 /*!< Enable the watchdog 1 on a single channel or on all channels */

+#define ADC_CFGR_AWD1EN_Pos               (23U)

+#define ADC_CFGR_AWD1EN_Msk               (0x1UL << ADC_CFGR_AWD1EN_Pos)       /*!< 0x00800000 */

+#define ADC_CFGR_AWD1EN                   ADC_CFGR_AWD1EN_Msk                  /*!< ADC Analog watchdog 1 enable on regular Channels */

+#define ADC_CFGR_JAWD1EN_Pos              (24U)

+#define ADC_CFGR_JAWD1EN_Msk              (0x1UL << ADC_CFGR_JAWD1EN_Pos)      /*!< 0x01000000 */

+#define ADC_CFGR_JAWD1EN                  ADC_CFGR_JAWD1EN_Msk                 /*!< ADC Analog watchdog 1 enable on injected Channels */

+#define ADC_CFGR_JAUTO_Pos                (25U)

+#define ADC_CFGR_JAUTO_Msk                (0x1UL << ADC_CFGR_JAUTO_Pos)        /*!< 0x02000000 */

+#define ADC_CFGR_JAUTO                    ADC_CFGR_JAUTO_Msk                   /*!< ADC Automatic injected group conversion */

+

+#define ADC_CFGR_AWD1CH_Pos               (26U)

+#define ADC_CFGR_AWD1CH_Msk               (0x1FUL << ADC_CFGR_AWD1CH_Pos)      /*!< 0x7C000000 */

+#define ADC_CFGR_AWD1CH                   ADC_CFGR_AWD1CH_Msk                  /*!< ADC Analog watchdog 1 Channel selection */

+#define ADC_CFGR_AWD1CH_0                 (0x01UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x04000000 */

+#define ADC_CFGR_AWD1CH_1                 (0x02UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x08000000 */

+#define ADC_CFGR_AWD1CH_2                 (0x04UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x10000000 */

+#define ADC_CFGR_AWD1CH_3                 (0x08UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x20000000 */

+#define ADC_CFGR_AWD1CH_4                 (0x10UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x40000000 */

+

+#define ADC_CFGR_JQDIS_Pos                (31U)

+#define ADC_CFGR_JQDIS_Msk                (0x1UL << ADC_CFGR_JQDIS_Pos)        /*!< 0x80000000 */

+#define ADC_CFGR_JQDIS                    ADC_CFGR_JQDIS_Msk                   /*!< ADC Injected queue disable */

+

+/********************  Bit definition for ADC_CFGR2 register  ********************/

+#define ADC_CFGR2_ROVSE_Pos               (0U)

+#define ADC_CFGR2_ROVSE_Msk               (0x1UL << ADC_CFGR2_ROVSE_Pos)       /*!< 0x00000001 */

+#define ADC_CFGR2_ROVSE                   ADC_CFGR2_ROVSE_Msk                  /*!< ADC Regular group oversampler enable */

+#define ADC_CFGR2_JOVSE_Pos               (1U)

+#define ADC_CFGR2_JOVSE_Msk               (0x1UL << ADC_CFGR2_JOVSE_Pos)       /*!< 0x00000002 */

+#define ADC_CFGR2_JOVSE                   ADC_CFGR2_JOVSE_Msk                  /*!< ADC Injected group oversampler enable */

+

+#define ADC_CFGR2_OVSS_Pos                (5U)

+#define ADC_CFGR2_OVSS_Msk                (0xFUL << ADC_CFGR2_OVSS_Pos)        /*!< 0x000001E0 */

+#define ADC_CFGR2_OVSS                    ADC_CFGR2_OVSS_Msk                   /*!< ADC Regular Oversampling shift */

+#define ADC_CFGR2_OVSS_0                  (0x1UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000020 */

+#define ADC_CFGR2_OVSS_1                  (0x2UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000040 */

+#define ADC_CFGR2_OVSS_2                  (0x4UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000080 */

+#define ADC_CFGR2_OVSS_3                  (0x8UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000100 */

+

+#define ADC_CFGR2_TROVS_Pos               (9U)

+#define ADC_CFGR2_TROVS_Msk               (0x1UL << ADC_CFGR2_TROVS_Pos)       /*!< 0x00000200 */

+#define ADC_CFGR2_TROVS                   ADC_CFGR2_TROVS_Msk                  /*!< ADC Triggered regular Oversampling */

+#define ADC_CFGR2_ROVSM_Pos               (10U)

+#define ADC_CFGR2_ROVSM_Msk               (0x1UL << ADC_CFGR2_ROVSM_Pos)       /*!< 0x00000400 */

+#define ADC_CFGR2_ROVSM                   ADC_CFGR2_ROVSM_Msk                  /*!< ADC Regular oversampling mode */

+

+#define ADC_CFGR2_RSHIFT1_Pos             (11U)

+#define ADC_CFGR2_RSHIFT1_Msk             (0x1UL << ADC_CFGR2_RSHIFT1_Pos)     /*!< 0x00000800 */

+#define ADC_CFGR2_RSHIFT1                 ADC_CFGR2_RSHIFT1_Msk                /*!< ADC Right-shift data after Offset 1 correction */

+#define ADC_CFGR2_RSHIFT2_Pos             (12U)

+#define ADC_CFGR2_RSHIFT2_Msk             (0x1UL << ADC_CFGR2_RSHIFT2_Pos)     /*!< 0x00001000 */

+#define ADC_CFGR2_RSHIFT2                 ADC_CFGR2_RSHIFT2_Msk                /*!< ADC Right-shift data after Offset 2 correction */

+#define ADC_CFGR2_RSHIFT3_Pos             (13U)

+#define ADC_CFGR2_RSHIFT3_Msk             (0x1UL << ADC_CFGR2_RSHIFT3_Pos)     /*!< 0x00002000 */

+#define ADC_CFGR2_RSHIFT3                 ADC_CFGR2_RSHIFT3_Msk                /*!< ADC Right-shift data after Offset 3 correction */

+#define ADC_CFGR2_RSHIFT4_Pos             (14U)

+#define ADC_CFGR2_RSHIFT4_Msk             (0x1UL << ADC_CFGR2_RSHIFT4_Pos)     /*!< 0x00004000 */

+#define ADC_CFGR2_RSHIFT4                 ADC_CFGR2_RSHIFT4_Msk                /*!< ADC Right-shift data after Offset 4 correction */

+

+#define ADC_CFGR2_OVSR_Pos                (16U)

+#define ADC_CFGR2_OVSR_Msk                (0x3FFUL << ADC_CFGR2_OVSR_Pos)      /*!< 0x03FF0000 */

+#define ADC_CFGR2_OVSR                    ADC_CFGR2_OVSR_Msk                   /*!< ADC oversampling Ratio */

+#define ADC_CFGR2_OVSR_0                  (0x001UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00010000 */

+#define ADC_CFGR2_OVSR_1                  (0x002UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00020000 */

+#define ADC_CFGR2_OVSR_2                  (0x004UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00040000 */

+#define ADC_CFGR2_OVSR_3                  (0x008UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00080000 */

+#define ADC_CFGR2_OVSR_4                  (0x010UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00100000 */

+#define ADC_CFGR2_OVSR_5                  (0x020UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00200000 */

+#define ADC_CFGR2_OVSR_6                  (0x040UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00400000 */

+#define ADC_CFGR2_OVSR_7                  (0x080UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00800000 */

+#define ADC_CFGR2_OVSR_8                  (0x100UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x01000000 */

+#define ADC_CFGR2_OVSR_9                  (0x200UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x02000000 */

+

+#define ADC_CFGR2_LSHIFT_Pos              (28U)

+#define ADC_CFGR2_LSHIFT_Msk              (0xFUL << ADC_CFGR2_LSHIFT_Pos)      /*!< 0xF0000000 */

+#define ADC_CFGR2_LSHIFT                  ADC_CFGR2_LSHIFT_Msk                 /*!< ADC Left shift factor */

+#define ADC_CFGR2_LSHIFT_0                (0x1UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x10000000 */

+#define ADC_CFGR2_LSHIFT_1                (0x2UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x20000000 */

+#define ADC_CFGR2_LSHIFT_2                (0x4UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x40000000 */

+#define ADC_CFGR2_LSHIFT_3                (0x8UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_SMPR1 register  ********************/

+#define ADC_SMPR1_SMP0_Pos                (0U)

+#define ADC_SMPR1_SMP0_Msk                (0x7UL << ADC_SMPR1_SMP0_Pos)        /*!< 0x00000007 */

+#define ADC_SMPR1_SMP0                    ADC_SMPR1_SMP0_Msk                   /*!< ADC Channel 0 Sampling time selection  */

+#define ADC_SMPR1_SMP0_0                  (0x1UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000001 */

+#define ADC_SMPR1_SMP0_1                  (0x2UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000002 */

+#define ADC_SMPR1_SMP0_2                  (0x4UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000004 */

+

+#define ADC_SMPR1_SMP1_Pos                (3U)

+#define ADC_SMPR1_SMP1_Msk                (0x7UL << ADC_SMPR1_SMP1_Pos)        /*!< 0x00000038 */

+#define ADC_SMPR1_SMP1                    ADC_SMPR1_SMP1_Msk                   /*!< ADC Channel 1 Sampling time selection  */

+#define ADC_SMPR1_SMP1_0                  (0x1UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000008 */

+#define ADC_SMPR1_SMP1_1                  (0x2UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000010 */

+#define ADC_SMPR1_SMP1_2                  (0x4UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000020 */

+

+#define ADC_SMPR1_SMP2_Pos                (6U)

+#define ADC_SMPR1_SMP2_Msk                (0x7UL << ADC_SMPR1_SMP2_Pos)        /*!< 0x000001C0 */

+#define ADC_SMPR1_SMP2                    ADC_SMPR1_SMP2_Msk                   /*!< ADC Channel 2 Sampling time selection  */

+#define ADC_SMPR1_SMP2_0                  (0x1UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000040 */

+#define ADC_SMPR1_SMP2_1                  (0x2UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000080 */

+#define ADC_SMPR1_SMP2_2                  (0x4UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000100 */

+

+#define ADC_SMPR1_SMP3_Pos                (9U)

+#define ADC_SMPR1_SMP3_Msk                (0x7UL << ADC_SMPR1_SMP3_Pos)        /*!< 0x00000E00 */

+#define ADC_SMPR1_SMP3                    ADC_SMPR1_SMP3_Msk                   /*!< ADC Channel 3 Sampling time selection  */

+#define ADC_SMPR1_SMP3_0                  (0x1UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000200 */

+#define ADC_SMPR1_SMP3_1                  (0x2UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000400 */

+#define ADC_SMPR1_SMP3_2                  (0x4UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000800 */

+

+#define ADC_SMPR1_SMP4_Pos                (12U)

+#define ADC_SMPR1_SMP4_Msk                (0x7UL << ADC_SMPR1_SMP4_Pos)        /*!< 0x00007000 */

+#define ADC_SMPR1_SMP4                    ADC_SMPR1_SMP4_Msk                   /*!< ADC Channel 4 Sampling time selection  */

+#define ADC_SMPR1_SMP4_0                  (0x1UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00001000 */

+#define ADC_SMPR1_SMP4_1                  (0x2UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00002000 */

+#define ADC_SMPR1_SMP4_2                  (0x4UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00004000 */

+

+#define ADC_SMPR1_SMP5_Pos                (15U)

+#define ADC_SMPR1_SMP5_Msk                (0x7UL << ADC_SMPR1_SMP5_Pos)        /*!< 0x00038000 */

+#define ADC_SMPR1_SMP5                    ADC_SMPR1_SMP5_Msk                   /*!< ADC Channel 5 Sampling time selection  */

+#define ADC_SMPR1_SMP5_0                  (0x1UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00008000 */

+#define ADC_SMPR1_SMP5_1                  (0x2UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00010000 */

+#define ADC_SMPR1_SMP5_2                  (0x4UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00020000 */

+

+#define ADC_SMPR1_SMP6_Pos                (18U)

+#define ADC_SMPR1_SMP6_Msk                (0x7UL << ADC_SMPR1_SMP6_Pos)        /*!< 0x001C0000 */

+#define ADC_SMPR1_SMP6                    ADC_SMPR1_SMP6_Msk                   /*!< ADC Channel 6 Sampling time selection  */

+#define ADC_SMPR1_SMP6_0                  (0x1UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00040000 */

+#define ADC_SMPR1_SMP6_1                  (0x2UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00080000 */

+#define ADC_SMPR1_SMP6_2                  (0x4UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00100000 */

+

+#define ADC_SMPR1_SMP7_Pos                (21U)

+#define ADC_SMPR1_SMP7_Msk                (0x7UL << ADC_SMPR1_SMP7_Pos)        /*!< 0x00E00000 */

+#define ADC_SMPR1_SMP7                    ADC_SMPR1_SMP7_Msk                   /*!< ADC Channel 7 Sampling time selection  */

+#define ADC_SMPR1_SMP7_0                  (0x1UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00200000 */

+#define ADC_SMPR1_SMP7_1                  (0x2UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00400000 */

+#define ADC_SMPR1_SMP7_2                  (0x4UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00800000 */

+

+#define ADC_SMPR1_SMP8_Pos                (24U)

+#define ADC_SMPR1_SMP8_Msk                (0x7UL << ADC_SMPR1_SMP8_Pos)        /*!< 0x07000000 */

+#define ADC_SMPR1_SMP8                    ADC_SMPR1_SMP8_Msk                   /*!< ADC Channel 8 Sampling time selection  */

+#define ADC_SMPR1_SMP8_0                  (0x1UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x01000000 */

+#define ADC_SMPR1_SMP8_1                  (0x2UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x02000000 */

+#define ADC_SMPR1_SMP8_2                  (0x4UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x04000000 */

+

+#define ADC_SMPR1_SMP9_Pos                (27U)

+#define ADC_SMPR1_SMP9_Msk                (0x7UL << ADC_SMPR1_SMP9_Pos)        /*!< 0x38000000 */

+#define ADC_SMPR1_SMP9                    ADC_SMPR1_SMP9_Msk                   /*!< ADC Channel 9 Sampling time selection  */

+#define ADC_SMPR1_SMP9_0                  (0x1UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x08000000 */

+#define ADC_SMPR1_SMP9_1                  (0x2UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x10000000 */

+#define ADC_SMPR1_SMP9_2                  (0x4UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x20000000 */

+

+/********************  Bit definition for ADC_SMPR2 register  ********************/

+#define ADC_SMPR2_SMP10_Pos               (0U)

+#define ADC_SMPR2_SMP10_Msk               (0x7UL << ADC_SMPR2_SMP10_Pos)       /*!< 0x00000007 */

+#define ADC_SMPR2_SMP10                   ADC_SMPR2_SMP10_Msk                  /*!< ADC Channel 10 Sampling time selection  */

+#define ADC_SMPR2_SMP10_0                 (0x1UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000001 */

+#define ADC_SMPR2_SMP10_1                 (0x2UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000002 */

+#define ADC_SMPR2_SMP10_2                 (0x4UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000004 */

+

+#define ADC_SMPR2_SMP11_Pos               (3U)

+#define ADC_SMPR2_SMP11_Msk               (0x7UL << ADC_SMPR2_SMP11_Pos)       /*!< 0x00000038 */

+#define ADC_SMPR2_SMP11                   ADC_SMPR2_SMP11_Msk                  /*!< ADC Channel 11 Sampling time selection  */

+#define ADC_SMPR2_SMP11_0                 (0x1UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000008 */

+#define ADC_SMPR2_SMP11_1                 (0x2UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000010 */

+#define ADC_SMPR2_SMP11_2                 (0x4UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000020 */

+

+#define ADC_SMPR2_SMP12_Pos               (6U)

+#define ADC_SMPR2_SMP12_Msk               (0x7UL << ADC_SMPR2_SMP12_Pos)       /*!< 0x000001C0 */

+#define ADC_SMPR2_SMP12                   ADC_SMPR2_SMP12_Msk                  /*!< ADC Channel 12 Sampling time selection  */

+#define ADC_SMPR2_SMP12_0                 (0x1UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000040 */

+#define ADC_SMPR2_SMP12_1                 (0x2UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000080 */

+#define ADC_SMPR2_SMP12_2                 (0x4UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000100 */

+

+#define ADC_SMPR2_SMP13_Pos               (9U)

+#define ADC_SMPR2_SMP13_Msk               (0x7UL << ADC_SMPR2_SMP13_Pos)       /*!< 0x00000E00 */

+#define ADC_SMPR2_SMP13                   ADC_SMPR2_SMP13_Msk                  /*!< ADC Channel 13 Sampling time selection  */

+#define ADC_SMPR2_SMP13_0                 (0x1UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000200 */

+#define ADC_SMPR2_SMP13_1                 (0x2UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000400 */

+#define ADC_SMPR2_SMP13_2                 (0x4UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000800 */

+

+#define ADC_SMPR2_SMP14_Pos               (12U)

+#define ADC_SMPR2_SMP14_Msk               (0x7UL << ADC_SMPR2_SMP14_Pos)       /*!< 0x00007000 */

+#define ADC_SMPR2_SMP14                   ADC_SMPR2_SMP14_Msk                  /*!< ADC Channel 14 Sampling time selection  */

+#define ADC_SMPR2_SMP14_0                 (0x1UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00001000 */

+#define ADC_SMPR2_SMP14_1                 (0x2UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00002000 */

+#define ADC_SMPR2_SMP14_2                 (0x4UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00004000 */

+

+#define ADC_SMPR2_SMP15_Pos               (15U)

+#define ADC_SMPR2_SMP15_Msk               (0x7UL << ADC_SMPR2_SMP15_Pos)       /*!< 0x00038000 */

+#define ADC_SMPR2_SMP15                   ADC_SMPR2_SMP15_Msk                  /*!< ADC Channel 15 Sampling time selection  */

+#define ADC_SMPR2_SMP15_0                 (0x1UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00008000 */

+#define ADC_SMPR2_SMP15_1                 (0x2UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00010000 */

+#define ADC_SMPR2_SMP15_2                 (0x4UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00020000 */

+

+#define ADC_SMPR2_SMP16_Pos               (18U)

+#define ADC_SMPR2_SMP16_Msk               (0x7UL << ADC_SMPR2_SMP16_Pos)       /*!< 0x001C0000 */

+#define ADC_SMPR2_SMP16                   ADC_SMPR2_SMP16_Msk                  /*!< ADC Channel 16 Sampling time selection  */

+#define ADC_SMPR2_SMP16_0                 (0x1UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00040000 */

+#define ADC_SMPR2_SMP16_1                 (0x2UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00080000 */

+#define ADC_SMPR2_SMP16_2                 (0x4UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00100000 */

+

+#define ADC_SMPR2_SMP17_Pos               (21U)

+#define ADC_SMPR2_SMP17_Msk               (0x7UL << ADC_SMPR2_SMP17_Pos)       /*!< 0x00E00000 */

+#define ADC_SMPR2_SMP17                   ADC_SMPR2_SMP17_Msk                  /*!< ADC Channel 17 Sampling time selection  */

+#define ADC_SMPR2_SMP17_0                 (0x1UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00200000 */

+#define ADC_SMPR2_SMP17_1                 (0x2UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00400000 */

+#define ADC_SMPR2_SMP17_2                 (0x4UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00800000 */

+

+#define ADC_SMPR2_SMP18_Pos               (24U)

+#define ADC_SMPR2_SMP18_Msk               (0x7UL << ADC_SMPR2_SMP18_Pos)       /*!< 0x07000000 */

+#define ADC_SMPR2_SMP18                   ADC_SMPR2_SMP18_Msk                  /*!< ADC Channel 18 Sampling time selection  */

+#define ADC_SMPR2_SMP18_0                 (0x1UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x01000000 */

+#define ADC_SMPR2_SMP18_1                 (0x2UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x02000000 */

+#define ADC_SMPR2_SMP18_2                 (0x4UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x04000000 */

+

+#define ADC_SMPR2_SMP19_Pos               (27U)

+#define ADC_SMPR2_SMP19_Msk               (0x7UL << ADC_SMPR2_SMP19_Pos)       /*!< 0x38000000 */

+#define ADC_SMPR2_SMP19                   ADC_SMPR2_SMP19_Msk                  /*!< ADC Channel 19 Sampling time selection  */

+#define ADC_SMPR2_SMP19_0                 (0x1UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x08000000 */

+#define ADC_SMPR2_SMP19_1                 (0x2UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x10000000 */

+#define ADC_SMPR2_SMP19_2                 (0x4UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x20000000 */

+

+/********************  Bit definition for ADC_PCSEL register  ********************/

+#define ADC_PCSEL_PCSEL_Pos               (0U)

+#define ADC_PCSEL_PCSEL_Msk               (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)   /*!< 0x000FFFFF */

+#define ADC_PCSEL_PCSEL                   ADC_PCSEL_PCSEL_Msk                  /*!< ADC pre channel selection */

+#define ADC_PCSEL_PCSEL_0                 (0x00001UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */

+#define ADC_PCSEL_PCSEL_1                 (0x00002UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */

+#define ADC_PCSEL_PCSEL_2                 (0x00004UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */

+#define ADC_PCSEL_PCSEL_3                 (0x00008UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */

+#define ADC_PCSEL_PCSEL_4                 (0x00010UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */

+#define ADC_PCSEL_PCSEL_5                 (0x00020UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */

+#define ADC_PCSEL_PCSEL_6                 (0x00040UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */

+#define ADC_PCSEL_PCSEL_7                 (0x00080UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */

+#define ADC_PCSEL_PCSEL_8                 (0x00100UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */

+#define ADC_PCSEL_PCSEL_9                 (0x00200UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */

+#define ADC_PCSEL_PCSEL_10                (0x00400UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */

+#define ADC_PCSEL_PCSEL_11                (0x00800UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */

+#define ADC_PCSEL_PCSEL_12                (0x01000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */

+#define ADC_PCSEL_PCSEL_13                (0x02000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */

+#define ADC_PCSEL_PCSEL_14                (0x04000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */

+#define ADC_PCSEL_PCSEL_15                (0x08000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */

+#define ADC_PCSEL_PCSEL_16                (0x10000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */

+#define ADC_PCSEL_PCSEL_17                (0x20000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */

+#define ADC_PCSEL_PCSEL_18                (0x40000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */

+#define ADC_PCSEL_PCSEL_19                (0x80000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00080000 */

+

+/*****************  Bit definition for ADC_LTR1, 2, 3 registers *****************/

+#define ADC_LTR_LT_Pos                    (0U)

+#define ADC_LTR_LT_Msk                    (0x3FFFFFFUL << ADC_LTR_LT_Pos)      /*!< 0x03FFFFFF */

+#define ADC_LTR_LT                        ADC_LTR_LT_Msk                       /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */

+

+/*****************  Bit definition for ADC_HTR1, 2, 3 registers  ****************/

+#define ADC_HTR_HT_Pos                    (0U)

+#define ADC_HTR_HT_Msk                    (0x3FFFFFFUL << ADC_HTR_HT_Pos)      /*!< 0x03FFFFFF */

+#define ADC_HTR_HT                        ADC_HTR_HT_Msk                       /*!< ADC Analog watchdog 1,2 and 3 higher threshold */

+

+

+/********************  Bit definition for ADC_SQR1 register  ********************/

+#define ADC_SQR1_L_Pos                    (0U)

+#define ADC_SQR1_L_Msk                    (0xFUL << ADC_SQR1_L_Pos)            /*!< 0x0000000F */

+#define ADC_SQR1_L                        ADC_SQR1_L_Msk                       /*!< ADC regular channel sequence lenght */

+#define ADC_SQR1_L_0                      (0x1UL << ADC_SQR1_L_Pos)             /*!< 0x00000001 */

+#define ADC_SQR1_L_1                      (0x2UL << ADC_SQR1_L_Pos)             /*!< 0x00000002 */

+#define ADC_SQR1_L_2                      (0x4UL << ADC_SQR1_L_Pos)             /*!< 0x00000004 */

+#define ADC_SQR1_L_3                      (0x8UL << ADC_SQR1_L_Pos)             /*!< 0x00000008 */

+

+#define ADC_SQR1_SQ1_Pos                  (6U)

+#define ADC_SQR1_SQ1_Msk                  (0x1FUL << ADC_SQR1_SQ1_Pos)         /*!< 0x000007C0 */

+#define ADC_SQR1_SQ1                      ADC_SQR1_SQ1_Msk                     /*!< ADC 1st conversion in regular sequence */

+#define ADC_SQR1_SQ1_0                    (0x01UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000040 */

+#define ADC_SQR1_SQ1_1                    (0x02UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000080 */

+#define ADC_SQR1_SQ1_2                    (0x04UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000100 */

+#define ADC_SQR1_SQ1_3                    (0x08UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000200 */

+#define ADC_SQR1_SQ1_4                    (0x10UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000400 */

+

+#define ADC_SQR1_SQ2_Pos                  (12U)

+#define ADC_SQR1_SQ2_Msk                  (0x1FUL << ADC_SQR1_SQ2_Pos)         /*!< 0x0001F000 */

+#define ADC_SQR1_SQ2                      ADC_SQR1_SQ2_Msk                     /*!< ADC 2nd conversion in regular sequence */

+#define ADC_SQR1_SQ2_0                    (0x01UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00001000 */

+#define ADC_SQR1_SQ2_1                    (0x02UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00002000 */

+#define ADC_SQR1_SQ2_2                    (0x04UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00004000 */

+#define ADC_SQR1_SQ2_3                    (0x08UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00008000 */

+#define ADC_SQR1_SQ2_4                    (0x10UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00010000 */

+

+#define ADC_SQR1_SQ3_Pos                  (18U)

+#define ADC_SQR1_SQ3_Msk                  (0x1FUL << ADC_SQR1_SQ3_Pos)         /*!< 0x007C0000 */

+#define ADC_SQR1_SQ3                      ADC_SQR1_SQ3_Msk                     /*!< ADC 3rd conversion in regular sequence */

+#define ADC_SQR1_SQ3_0                    (0x01UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00040000 */

+#define ADC_SQR1_SQ3_1                    (0x02UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00080000 */

+#define ADC_SQR1_SQ3_2                    (0x04UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00100000 */

+#define ADC_SQR1_SQ3_3                    (0x08UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00200000 */

+#define ADC_SQR1_SQ3_4                    (0x10UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00400000 */

+

+#define ADC_SQR1_SQ4_Pos                  (24U)

+#define ADC_SQR1_SQ4_Msk                  (0x1FUL << ADC_SQR1_SQ4_Pos)         /*!< 0x1F000000 */

+#define ADC_SQR1_SQ4                      ADC_SQR1_SQ4_Msk                     /*!< ADC 4th conversion in regular sequence */

+#define ADC_SQR1_SQ4_0                    (0x01UL << ADC_SQR1_SQ4_Pos)          /*!< 0x01000000 */

+#define ADC_SQR1_SQ4_1                    (0x02UL << ADC_SQR1_SQ4_Pos)          /*!< 0x02000000 */

+#define ADC_SQR1_SQ4_2                    (0x04UL << ADC_SQR1_SQ4_Pos)          /*!< 0x04000000 */

+#define ADC_SQR1_SQ4_3                    (0x08UL << ADC_SQR1_SQ4_Pos)          /*!< 0x08000000 */

+#define ADC_SQR1_SQ4_4                    (0x10UL << ADC_SQR1_SQ4_Pos)          /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR2 register  ********************/

+#define ADC_SQR2_SQ5_Pos                  (0U)

+#define ADC_SQR2_SQ5_Msk                  (0x1FUL << ADC_SQR2_SQ5_Pos)         /*!< 0x0000001F */

+#define ADC_SQR2_SQ5                      ADC_SQR2_SQ5_Msk                     /*!< ADC 5th conversion in regular sequence */

+#define ADC_SQR2_SQ5_0                    (0x01UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000001 */

+#define ADC_SQR2_SQ5_1                    (0x02UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000002 */

+#define ADC_SQR2_SQ5_2                    (0x04UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000004 */

+#define ADC_SQR2_SQ5_3                    (0x08UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000008 */

+#define ADC_SQR2_SQ5_4                    (0x10UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000010 */

+

+#define ADC_SQR2_SQ6_Pos                  (6U)

+#define ADC_SQR2_SQ6_Msk                  (0x1FUL << ADC_SQR2_SQ6_Pos)         /*!< 0x000007C0 */

+#define ADC_SQR2_SQ6                      ADC_SQR2_SQ6_Msk                     /*!< ADC 6th conversion in regular sequence */

+#define ADC_SQR2_SQ6_0                    (0x01UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000040 */

+#define ADC_SQR2_SQ6_1                    (0x02UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000080 */

+#define ADC_SQR2_SQ6_2                    (0x04UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000100 */

+#define ADC_SQR2_SQ6_3                    (0x08UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000200 */

+#define ADC_SQR2_SQ6_4                    (0x10UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000400 */

+

+#define ADC_SQR2_SQ7_Pos                  (12U)

+#define ADC_SQR2_SQ7_Msk                  (0x1FUL << ADC_SQR2_SQ7_Pos)         /*!< 0x0001F000 */

+#define ADC_SQR2_SQ7                      ADC_SQR2_SQ7_Msk                     /*!< ADC 7th conversion in regular sequence */

+#define ADC_SQR2_SQ7_0                    (0x01UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00001000 */

+#define ADC_SQR2_SQ7_1                    (0x02UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00002000 */

+#define ADC_SQR2_SQ7_2                    (0x04UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00004000 */

+#define ADC_SQR2_SQ7_3                    (0x08UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00008000 */

+#define ADC_SQR2_SQ7_4                    (0x10UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00010000 */

+

+#define ADC_SQR2_SQ8_Pos                  (18U)

+#define ADC_SQR2_SQ8_Msk                  (0x1FUL << ADC_SQR2_SQ8_Pos)         /*!< 0x007C0000 */

+#define ADC_SQR2_SQ8                      ADC_SQR2_SQ8_Msk                     /*!< ADC 8th conversion in regular sequence */

+#define ADC_SQR2_SQ8_0                    (0x01UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00040000 */

+#define ADC_SQR2_SQ8_1                    (0x02UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00080000 */

+#define ADC_SQR2_SQ8_2                    (0x04UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00100000 */

+#define ADC_SQR2_SQ8_3                    (0x08UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00200000 */

+#define ADC_SQR2_SQ8_4                    (0x10UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00400000 */

+

+#define ADC_SQR2_SQ9_Pos                  (24U)

+#define ADC_SQR2_SQ9_Msk                  (0x1FUL << ADC_SQR2_SQ9_Pos)         /*!< 0x1F000000 */

+#define ADC_SQR2_SQ9                      ADC_SQR2_SQ9_Msk                     /*!< ADC 9th conversion in regular sequence */

+#define ADC_SQR2_SQ9_0                    (0x01UL << ADC_SQR2_SQ9_Pos)          /*!< 0x01000000 */

+#define ADC_SQR2_SQ9_1                    (0x02UL << ADC_SQR2_SQ9_Pos)          /*!< 0x02000000 */

+#define ADC_SQR2_SQ9_2                    (0x04UL << ADC_SQR2_SQ9_Pos)          /*!< 0x04000000 */

+#define ADC_SQR2_SQ9_3                    (0x08UL << ADC_SQR2_SQ9_Pos)          /*!< 0x08000000 */

+#define ADC_SQR2_SQ9_4                    (0x10UL << ADC_SQR2_SQ9_Pos)          /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR3 register  ********************/

+#define ADC_SQR3_SQ10_Pos                 (0U)

+#define ADC_SQR3_SQ10_Msk                 (0x1FUL << ADC_SQR3_SQ10_Pos)        /*!< 0x0000001F */

+#define ADC_SQR3_SQ10                     ADC_SQR3_SQ10_Msk                    /*!< ADC 10th conversion in regular sequence */

+#define ADC_SQR3_SQ10_0                   (0x01UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000001 */

+#define ADC_SQR3_SQ10_1                   (0x02UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000002 */

+#define ADC_SQR3_SQ10_2                   (0x04UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000004 */

+#define ADC_SQR3_SQ10_3                   (0x08UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000008 */

+#define ADC_SQR3_SQ10_4                   (0x10UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000010 */

+

+#define ADC_SQR3_SQ11_Pos                 (6U)

+#define ADC_SQR3_SQ11_Msk                 (0x1FUL << ADC_SQR3_SQ11_Pos)        /*!< 0x000007C0 */

+#define ADC_SQR3_SQ11                     ADC_SQR3_SQ11_Msk                    /*!< ADC 11th conversion in regular sequence */

+#define ADC_SQR3_SQ11_0                   (0x01UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000040 */

+#define ADC_SQR3_SQ11_1                   (0x02UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000080 */

+#define ADC_SQR3_SQ11_2                   (0x04UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000100 */

+#define ADC_SQR3_SQ11_3                   (0x08UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000200 */

+#define ADC_SQR3_SQ11_4                   (0x10UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000400 */

+

+#define ADC_SQR3_SQ12_Pos                 (12U)

+#define ADC_SQR3_SQ12_Msk                 (0x1FUL << ADC_SQR3_SQ12_Pos)        /*!< 0x0001F000 */

+#define ADC_SQR3_SQ12                     ADC_SQR3_SQ12_Msk                    /*!< ADC 12th conversion in regular sequence */

+#define ADC_SQR3_SQ12_0                   (0x01UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00001000 */

+#define ADC_SQR3_SQ12_1                   (0x02UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00002000 */

+#define ADC_SQR3_SQ12_2                   (0x04UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00004000 */

+#define ADC_SQR3_SQ12_3                   (0x08UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00008000 */

+#define ADC_SQR3_SQ12_4                   (0x10UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00010000 */

+

+#define ADC_SQR3_SQ13_Pos                 (18U)

+#define ADC_SQR3_SQ13_Msk                 (0x1FUL << ADC_SQR3_SQ13_Pos)        /*!< 0x007C0000 */

+#define ADC_SQR3_SQ13                     ADC_SQR3_SQ13_Msk                    /*!< ADC 13th conversion in regular sequence */

+#define ADC_SQR3_SQ13_0                   (0x01UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00040000 */

+#define ADC_SQR3_SQ13_1                   (0x02UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00080000 */

+#define ADC_SQR3_SQ13_2                   (0x04UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00100000 */

+#define ADC_SQR3_SQ13_3                   (0x08UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00200000 */

+#define ADC_SQR3_SQ13_4                   (0x10UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00400000 */

+

+#define ADC_SQR3_SQ14_Pos                 (24U)

+#define ADC_SQR3_SQ14_Msk                 (0x1FUL << ADC_SQR3_SQ14_Pos)        /*!< 0x1F000000 */

+#define ADC_SQR3_SQ14                     ADC_SQR3_SQ14_Msk                    /*!< ADC 14th conversion in regular sequence */

+#define ADC_SQR3_SQ14_0                   (0x01UL << ADC_SQR3_SQ14_Pos)         /*!< 0x01000000 */

+#define ADC_SQR3_SQ14_1                   (0x02UL << ADC_SQR3_SQ14_Pos)         /*!< 0x02000000 */

+#define ADC_SQR3_SQ14_2                   (0x04UL << ADC_SQR3_SQ14_Pos)         /*!< 0x04000000 */

+#define ADC_SQR3_SQ14_3                   (0x08UL << ADC_SQR3_SQ14_Pos)         /*!< 0x08000000 */

+#define ADC_SQR3_SQ14_4                   (0x10UL << ADC_SQR3_SQ14_Pos)         /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR4 register  ********************/

+#define ADC_SQR4_SQ15_Pos                 (0U)

+#define ADC_SQR4_SQ15_Msk                 (0x1FUL << ADC_SQR4_SQ15_Pos)        /*!< 0x0000001F */

+#define ADC_SQR4_SQ15                     ADC_SQR4_SQ15_Msk                    /*!< ADC 15th conversion in regular sequence */

+#define ADC_SQR4_SQ15_0                   (0x01UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000001 */

+#define ADC_SQR4_SQ15_1                   (0x02UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000002 */

+#define ADC_SQR4_SQ15_2                   (0x04UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000004 */

+#define ADC_SQR4_SQ15_3                   (0x08UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000008 */

+#define ADC_SQR4_SQ15_4                   (0x10UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000010 */

+

+#define ADC_SQR4_SQ16_Pos                 (6U)

+#define ADC_SQR4_SQ16_Msk                 (0x1FUL << ADC_SQR4_SQ16_Pos)        /*!< 0x000007C0 */

+#define ADC_SQR4_SQ16                     ADC_SQR4_SQ16_Msk                    /*!< ADC 16th conversion in regular sequence */

+#define ADC_SQR4_SQ16_0                   (0x01UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000040 */

+#define ADC_SQR4_SQ16_1                   (0x02UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000080 */

+#define ADC_SQR4_SQ16_2                   (0x04UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000100 */

+#define ADC_SQR4_SQ16_3                   (0x08UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000200 */

+#define ADC_SQR4_SQ16_4                   (0x10UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000400 */

+/********************  Bit definition for ADC_DR register  ********************/

+#define ADC_DR_RDATA_Pos                  (0U)

+#define ADC_DR_RDATA_Msk                  (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)   /*!< 0xFFFFFFFF */

+#define ADC_DR_RDATA                      ADC_DR_RDATA_Msk                     /*!< ADC regular Data converted */

+

+/********************  Bit definition for ADC_JSQR register  ********************/

+#define ADC_JSQR_JL_Pos                   (0U)

+#define ADC_JSQR_JL_Msk                   (0x3UL << ADC_JSQR_JL_Pos)           /*!< 0x00000003 */

+#define ADC_JSQR_JL                       ADC_JSQR_JL_Msk                      /*!< ADC injected channel sequence length */

+#define ADC_JSQR_JL_0                     (0x1UL << ADC_JSQR_JL_Pos)           /*!< 0x00000001 */

+#define ADC_JSQR_JL_1                     (0x2UL << ADC_JSQR_JL_Pos)           /*!< 0x00000002 */

+

+#define ADC_JSQR_JEXTSEL_Pos              (2U)

+#define ADC_JSQR_JEXTSEL_Msk              (0x1FUL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x0000007C */

+#define ADC_JSQR_JEXTSEL                  ADC_JSQR_JEXTSEL_Msk                 /*!< ADC external trigger selection for injected group */

+#define ADC_JSQR_JEXTSEL_0                (0x01UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000004 */

+#define ADC_JSQR_JEXTSEL_1                (0x02UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000008 */

+#define ADC_JSQR_JEXTSEL_2                (0x04UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000010 */

+#define ADC_JSQR_JEXTSEL_3                (0x08UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000020 */

+#define ADC_JSQR_JEXTSEL_4                (0x10UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000040 */

+

+#define ADC_JSQR_JEXTEN_Pos               (7U)

+#define ADC_JSQR_JEXTEN_Msk               (0x3UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000180 */

+#define ADC_JSQR_JEXTEN                   ADC_JSQR_JEXTEN_Msk                  /*!< ADC external trigger enable and polarity selection for injected channels */

+#define ADC_JSQR_JEXTEN_0                 (0x1UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000080 */

+#define ADC_JSQR_JEXTEN_1                 (0x2UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000100 */

+

+#define ADC_JSQR_JSQ1_Pos                 (9U)

+#define ADC_JSQR_JSQ1_Msk                 (0x1FUL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00003E00 */

+#define ADC_JSQR_JSQ1                     ADC_JSQR_JSQ1_Msk                    /*!< ADC 1st conversion in injected sequence */

+#define ADC_JSQR_JSQ1_0                   (0x01UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000200 */

+#define ADC_JSQR_JSQ1_1                   (0x02UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000400 */

+#define ADC_JSQR_JSQ1_2                   (0x04UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000800 */

+#define ADC_JSQR_JSQ1_3                   (0x08UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00001000 */

+#define ADC_JSQR_JSQ1_4                   (0x10UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00002000 */

+

+#define ADC_JSQR_JSQ2_Pos                 (15U)

+#define ADC_JSQR_JSQ2_Msk                 (0x1FUL << ADC_JSQR_JSQ2_Pos)        /*!< 0x000F8000 */

+#define ADC_JSQR_JSQ2                     ADC_JSQR_JSQ2_Msk                    /*!< ADC 2nd conversion in injected sequence */

+#define ADC_JSQR_JSQ2_0                   (0x01UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00008000 */

+#define ADC_JSQR_JSQ2_1                   (0x02UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00010000 */

+#define ADC_JSQR_JSQ2_2                   (0x04UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00020000 */

+#define ADC_JSQR_JSQ2_3                   (0x08UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00040000 */

+#define ADC_JSQR_JSQ2_4                   (0x10UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00080000 */

+

+#define ADC_JSQR_JSQ3_Pos                 (21U)

+#define ADC_JSQR_JSQ3_Msk                 (0x1FUL << ADC_JSQR_JSQ3_Pos)        /*!< 0x03E00000 */

+#define ADC_JSQR_JSQ3                     ADC_JSQR_JSQ3_Msk                    /*!< ADC 3rd conversion in injected sequence */

+#define ADC_JSQR_JSQ3_0                   (0x01UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00200000 */

+#define ADC_JSQR_JSQ3_1                   (0x02UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00400000 */

+#define ADC_JSQR_JSQ3_2                   (0x04UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00800000 */

+#define ADC_JSQR_JSQ3_3                   (0x08UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x01000000 */

+#define ADC_JSQR_JSQ3_4                   (0x10UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x02000000 */

+

+#define ADC_JSQR_JSQ4_Pos                 (27U)

+#define ADC_JSQR_JSQ4_Msk                 (0x1FUL << ADC_JSQR_JSQ4_Pos)        /*!< 0xF8000000 */

+#define ADC_JSQR_JSQ4                     ADC_JSQR_JSQ4_Msk                    /*!< ADC 4th conversion in injected sequence */

+#define ADC_JSQR_JSQ4_0                   (0x01UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x08000000 */

+#define ADC_JSQR_JSQ4_1                   (0x02UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x10000000 */

+#define ADC_JSQR_JSQ4_2                   (0x04UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x20000000 */

+#define ADC_JSQR_JSQ4_3                   (0x08UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x40000000 */

+#define ADC_JSQR_JSQ4_4                   (0x10UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_OFR1 register  ********************/

+#define ADC_OFR1_OFFSET1_Pos              (0U)

+#define ADC_OFR1_OFFSET1_Msk              (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR1_OFFSET1                  ADC_OFR1_OFFSET1_Msk                  /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */

+#define ADC_OFR1_OFFSET1_0                (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */

+#define ADC_OFR1_OFFSET1_1                (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */

+#define ADC_OFR1_OFFSET1_2                (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */

+#define ADC_OFR1_OFFSET1_3                (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */

+#define ADC_OFR1_OFFSET1_4                (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */

+#define ADC_OFR1_OFFSET1_5                (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */

+#define ADC_OFR1_OFFSET1_6                (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */

+#define ADC_OFR1_OFFSET1_7                (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */

+#define ADC_OFR1_OFFSET1_8                (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */

+#define ADC_OFR1_OFFSET1_9                (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */

+#define ADC_OFR1_OFFSET1_10               (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */

+#define ADC_OFR1_OFFSET1_11               (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */

+#define ADC_OFR1_OFFSET1_12               (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */

+#define ADC_OFR1_OFFSET1_13               (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */

+#define ADC_OFR1_OFFSET1_14               (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */

+#define ADC_OFR1_OFFSET1_15               (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */

+#define ADC_OFR1_OFFSET1_16               (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */

+#define ADC_OFR1_OFFSET1_17               (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */

+#define ADC_OFR1_OFFSET1_18               (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */

+#define ADC_OFR1_OFFSET1_19               (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */

+#define ADC_OFR1_OFFSET1_20               (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */

+#define ADC_OFR1_OFFSET1_21               (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */

+#define ADC_OFR1_OFFSET1_22               (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */

+#define ADC_OFR1_OFFSET1_23               (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */

+#define ADC_OFR1_OFFSET1_24               (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */

+#define ADC_OFR1_OFFSET1_25               (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR1_OFFSET1_CH_Pos           (26U)

+#define ADC_OFR1_OFFSET1_CH_Msk           (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR1_OFFSET1_CH               ADC_OFR1_OFFSET1_CH_Msk               /*!< ADC Channel selection for the data offset 1 */

+#define ADC_OFR1_OFFSET1_CH_0             (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR1_OFFSET1_CH_1             (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR1_OFFSET1_CH_2             (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR1_OFFSET1_CH_3             (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR1_OFFSET1_CH_4             (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR1_SSATE_Pos                (31U)

+#define ADC_OFR1_SSATE_Msk                (0x1UL << ADC_OFR1_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR1_SSATE                    ADC_OFR1_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR2 register  ********************/

+#define ADC_OFR2_OFFSET2_Pos              (0U)

+#define ADC_OFR2_OFFSET2_Msk              (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR2_OFFSET2                  ADC_OFR2_OFFSET2_Msk                  /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */

+#define ADC_OFR2_OFFSET2_0                (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */

+#define ADC_OFR2_OFFSET2_1                (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */

+#define ADC_OFR2_OFFSET2_2                (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */

+#define ADC_OFR2_OFFSET2_3                (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */

+#define ADC_OFR2_OFFSET2_4                (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */

+#define ADC_OFR2_OFFSET2_5                (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */

+#define ADC_OFR2_OFFSET2_6                (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */

+#define ADC_OFR2_OFFSET2_7                (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */

+#define ADC_OFR2_OFFSET2_8                (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */

+#define ADC_OFR2_OFFSET2_9                (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */

+#define ADC_OFR2_OFFSET2_10               (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */

+#define ADC_OFR2_OFFSET2_11               (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */

+#define ADC_OFR2_OFFSET2_12               (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */

+#define ADC_OFR2_OFFSET2_13               (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */

+#define ADC_OFR2_OFFSET2_14               (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */

+#define ADC_OFR2_OFFSET2_15               (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */

+#define ADC_OFR2_OFFSET2_16               (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */

+#define ADC_OFR2_OFFSET2_17               (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */

+#define ADC_OFR2_OFFSET2_18               (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */

+#define ADC_OFR2_OFFSET2_19               (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */

+#define ADC_OFR2_OFFSET2_20               (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */

+#define ADC_OFR2_OFFSET2_21               (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */

+#define ADC_OFR2_OFFSET2_22               (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */

+#define ADC_OFR2_OFFSET2_23               (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */

+#define ADC_OFR2_OFFSET2_24               (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */

+#define ADC_OFR2_OFFSET2_25               (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR2_OFFSET2_CH_Pos           (26U)

+#define ADC_OFR2_OFFSET2_CH_Msk           (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR2_OFFSET2_CH               ADC_OFR2_OFFSET2_CH_Msk               /*!< ADC Channel selection for the data offset 2 */

+#define ADC_OFR2_OFFSET2_CH_0             (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR2_OFFSET2_CH_1             (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR2_OFFSET2_CH_2             (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR2_OFFSET2_CH_3             (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR2_OFFSET2_CH_4             (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR2_SSATE_Pos                (31U)

+#define ADC_OFR2_SSATE_Msk                (0x1UL << ADC_OFR2_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR2_SSATE                    ADC_OFR2_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR3 register  ********************/

+#define ADC_OFR3_OFFSET3_Pos              (0U)

+#define ADC_OFR3_OFFSET3_Msk              (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR3_OFFSET3                  ADC_OFR3_OFFSET3_Msk                  /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */

+#define ADC_OFR3_OFFSET3_0                (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */

+#define ADC_OFR3_OFFSET3_1                (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */

+#define ADC_OFR3_OFFSET3_2                (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */

+#define ADC_OFR3_OFFSET3_3                (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */

+#define ADC_OFR3_OFFSET3_4                (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */

+#define ADC_OFR3_OFFSET3_5                (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */

+#define ADC_OFR3_OFFSET3_6                (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */

+#define ADC_OFR3_OFFSET3_7                (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */

+#define ADC_OFR3_OFFSET3_8                (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */

+#define ADC_OFR3_OFFSET3_9                (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */

+#define ADC_OFR3_OFFSET3_10               (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */

+#define ADC_OFR3_OFFSET3_11               (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */

+#define ADC_OFR3_OFFSET3_12               (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */

+#define ADC_OFR3_OFFSET3_13               (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */

+#define ADC_OFR3_OFFSET3_14               (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */

+#define ADC_OFR3_OFFSET3_15               (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */

+#define ADC_OFR3_OFFSET3_16               (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */

+#define ADC_OFR3_OFFSET3_17               (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */

+#define ADC_OFR3_OFFSET3_18               (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */

+#define ADC_OFR3_OFFSET3_19               (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */

+#define ADC_OFR3_OFFSET3_20               (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */

+#define ADC_OFR3_OFFSET3_21               (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */

+#define ADC_OFR3_OFFSET3_22               (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */

+#define ADC_OFR3_OFFSET3_23               (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */

+#define ADC_OFR3_OFFSET3_24               (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */

+#define ADC_OFR3_OFFSET3_25               (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR3_OFFSET3_CH_Pos           (26U)

+#define ADC_OFR3_OFFSET3_CH_Msk           (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR3_OFFSET3_CH               ADC_OFR3_OFFSET3_CH_Msk               /*!< ADC Channel selection for the data offset 3 */

+#define ADC_OFR3_OFFSET3_CH_0             (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR3_OFFSET3_CH_1             (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR3_OFFSET3_CH_2             (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR3_OFFSET3_CH_3             (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR3_OFFSET3_CH_4             (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR3_SSATE_Pos                (31U)

+#define ADC_OFR3_SSATE_Msk                (0x1UL << ADC_OFR3_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR3_SSATE                    ADC_OFR3_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR4 register  ********************/

+#define ADC_OFR4_OFFSET4_Pos              (0U)

+#define ADC_OFR4_OFFSET4_Msk              (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR4_OFFSET4                  ADC_OFR4_OFFSET4_Msk                  /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */

+#define ADC_OFR4_OFFSET4_0                (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */

+#define ADC_OFR4_OFFSET4_1                (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */

+#define ADC_OFR4_OFFSET4_2                (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */

+#define ADC_OFR4_OFFSET4_3                (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */

+#define ADC_OFR4_OFFSET4_4                (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */

+#define ADC_OFR4_OFFSET4_5                (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */

+#define ADC_OFR4_OFFSET4_6                (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */

+#define ADC_OFR4_OFFSET4_7                (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */

+#define ADC_OFR4_OFFSET4_8                (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */

+#define ADC_OFR4_OFFSET4_9                (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */

+#define ADC_OFR4_OFFSET4_10               (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */

+#define ADC_OFR4_OFFSET4_11               (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */

+#define ADC_OFR4_OFFSET4_12               (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */

+#define ADC_OFR4_OFFSET4_13               (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */

+#define ADC_OFR4_OFFSET4_14               (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */

+#define ADC_OFR4_OFFSET4_15               (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */

+#define ADC_OFR4_OFFSET4_16               (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */

+#define ADC_OFR4_OFFSET4_17               (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */

+#define ADC_OFR4_OFFSET4_18               (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */

+#define ADC_OFR4_OFFSET4_19               (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */

+#define ADC_OFR4_OFFSET4_20               (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */

+#define ADC_OFR4_OFFSET4_21               (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */

+#define ADC_OFR4_OFFSET4_22               (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */

+#define ADC_OFR4_OFFSET4_23               (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */

+#define ADC_OFR4_OFFSET4_24               (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */

+#define ADC_OFR4_OFFSET4_25               (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR4_OFFSET4_CH_Pos           (26U)

+#define ADC_OFR4_OFFSET4_CH_Msk           (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR4_OFFSET4_CH               ADC_OFR4_OFFSET4_CH_Msk               /*!< ADC Channel selection for the data offset 4 */

+#define ADC_OFR4_OFFSET4_CH_0             (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR4_OFFSET4_CH_1             (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR4_OFFSET4_CH_2             (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR4_OFFSET4_CH_3             (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR4_OFFSET4_CH_4             (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR4_SSATE_Pos                (31U)

+#define ADC_OFR4_SSATE_Msk                (0x1UL << ADC_OFR4_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR4_SSATE                    ADC_OFR4_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_JDR1 register  ********************/

+#define ADC_JDR1_JDATA_Pos                (0U)

+#define ADC_JDR1_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR1_JDATA                    ADC_JDR1_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR1_JDATA_0                  (0x00000001UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR1_JDATA_1                  (0x00000002UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR1_JDATA_2                  (0x00000004UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR1_JDATA_3                  (0x00000008UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR1_JDATA_4                  (0x00000010UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR1_JDATA_5                  (0x00000020UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR1_JDATA_6                  (0x00000040UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR1_JDATA_7                  (0x00000080UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR1_JDATA_8                  (0x00000100UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR1_JDATA_9                  (0x00000200UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR1_JDATA_10                 (0x00000400UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR1_JDATA_11                 (0x00000800UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR1_JDATA_12                 (0x00001000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR1_JDATA_13                 (0x00002000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR1_JDATA_14                 (0x00004000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR1_JDATA_15                 (0x00008000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR1_JDATA_16                 (0x00010000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR1_JDATA_17                 (0x00020000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR1_JDATA_18                 (0x00040000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR1_JDATA_19                 (0x00080000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR1_JDATA_20                 (0x00100000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR1_JDATA_21                 (0x00200000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR1_JDATA_22                 (0x00400000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR1_JDATA_23                 (0x00800000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR1_JDATA_24                 (0x01000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR1_JDATA_25                 (0x02000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR1_JDATA_26                 (0x04000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR1_JDATA_27                 (0x08000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR1_JDATA_28                 (0x10000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR1_JDATA_29                 (0x20000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR1_JDATA_30                 (0x40000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR1_JDATA_31                 (0x80000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR2 register  ********************/

+#define ADC_JDR2_JDATA_Pos                (0U)

+#define ADC_JDR2_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR2_JDATA                    ADC_JDR2_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR2_JDATA_0                  (0x00000001UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR2_JDATA_1                  (0x00000002UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR2_JDATA_2                  (0x00000004UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR2_JDATA_3                  (0x00000008UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR2_JDATA_4                  (0x00000010UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR2_JDATA_5                  (0x00000020UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR2_JDATA_6                  (0x00000040UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR2_JDATA_7                  (0x00000080UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR2_JDATA_8                  (0x00000100UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR2_JDATA_9                  (0x00000200UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR2_JDATA_10                 (0x00000400UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR2_JDATA_11                 (0x00000800UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR2_JDATA_12                 (0x00001000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR2_JDATA_13                 (0x00002000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR2_JDATA_14                 (0x00004000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR2_JDATA_15                 (0x00008000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR2_JDATA_16                 (0x00010000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR2_JDATA_17                 (0x00020000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR2_JDATA_18                 (0x00040000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR2_JDATA_19                 (0x00080000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR2_JDATA_20                 (0x00100000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR2_JDATA_21                 (0x00200000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR2_JDATA_22                 (0x00400000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR2_JDATA_23                 (0x00800000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR2_JDATA_24                 (0x01000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR2_JDATA_25                 (0x02000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR2_JDATA_26                 (0x04000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR2_JDATA_27                 (0x08000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR2_JDATA_28                 (0x10000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR2_JDATA_29                 (0x20000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR2_JDATA_30                 (0x40000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR2_JDATA_31                 (0x80000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR3 register  ********************/

+#define ADC_JDR3_JDATA_Pos                (0U)

+#define ADC_JDR3_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR3_JDATA                    ADC_JDR3_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR3_JDATA_0                  (0x00000001UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR3_JDATA_1                  (0x00000002UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR3_JDATA_2                  (0x00000004UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR3_JDATA_3                  (0x00000008UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR3_JDATA_4                  (0x00000010UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR3_JDATA_5                  (0x00000020UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR3_JDATA_6                  (0x00000040UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR3_JDATA_7                  (0x00000080UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR3_JDATA_8                  (0x00000100UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR3_JDATA_9                  (0x00000200UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR3_JDATA_10                 (0x00000400UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR3_JDATA_11                 (0x00000800UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR3_JDATA_12                 (0x00001000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR3_JDATA_13                 (0x00002000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR3_JDATA_14                 (0x00004000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR3_JDATA_15                 (0x00008000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR3_JDATA_16                 (0x00010000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR3_JDATA_17                 (0x00020000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR3_JDATA_18                 (0x00040000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR3_JDATA_19                 (0x00080000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR3_JDATA_20                 (0x00100000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR3_JDATA_21                 (0x00200000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR3_JDATA_22                 (0x00400000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR3_JDATA_23                 (0x00800000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR3_JDATA_24                 (0x01000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR3_JDATA_25                 (0x02000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR3_JDATA_26                 (0x04000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR3_JDATA_27                 (0x08000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR3_JDATA_28                 (0x10000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR3_JDATA_29                 (0x20000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR3_JDATA_30                 (0x40000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR3_JDATA_31                 (0x80000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR4 register  ********************/

+#define ADC_JDR4_JDATA_Pos                (0U)

+#define ADC_JDR4_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR4_JDATA                    ADC_JDR4_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR4_JDATA_0                  (0x00000001UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR4_JDATA_1                  (0x00000002UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR4_JDATA_2                  (0x00000004UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR4_JDATA_3                  (0x00000008UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR4_JDATA_4                  (0x00000010UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR4_JDATA_5                  (0x00000020UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR4_JDATA_6                  (0x00000040UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR4_JDATA_7                  (0x00000080UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR4_JDATA_8                  (0x00000100UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR4_JDATA_9                  (0x00000200UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR4_JDATA_10                 (0x00000400UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR4_JDATA_11                 (0x00000800UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR4_JDATA_12                 (0x00001000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR4_JDATA_13                 (0x00002000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR4_JDATA_14                 (0x00004000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR4_JDATA_15                 (0x00008000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR4_JDATA_16                 (0x00010000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR4_JDATA_17                 (0x00020000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR4_JDATA_18                 (0x00040000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR4_JDATA_19                 (0x00080000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR4_JDATA_20                 (0x00100000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR4_JDATA_21                 (0x00200000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR4_JDATA_22                 (0x00400000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR4_JDATA_23                 (0x00800000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR4_JDATA_24                 (0x01000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR4_JDATA_25                 (0x02000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR4_JDATA_26                 (0x04000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR4_JDATA_27                 (0x08000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR4_JDATA_28                 (0x10000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR4_JDATA_29                 (0x20000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR4_JDATA_30                 (0x40000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR4_JDATA_31                 (0x80000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_AWD2CR register  ********************/

+#define ADC_AWD2CR_AWD2CH_Pos             (0U)

+#define ADC_AWD2CR_AWD2CH_Msk             (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x000FFFFF */

+#define ADC_AWD2CR_AWD2CH                 ADC_AWD2CR_AWD2CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */

+#define ADC_AWD2CR_AWD2CH_0               (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000001 */

+#define ADC_AWD2CR_AWD2CH_1               (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000002 */

+#define ADC_AWD2CR_AWD2CH_2               (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000004 */

+#define ADC_AWD2CR_AWD2CH_3               (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000008 */

+#define ADC_AWD2CR_AWD2CH_4               (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000010 */

+#define ADC_AWD2CR_AWD2CH_5               (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000020 */

+#define ADC_AWD2CR_AWD2CH_6               (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000040 */

+#define ADC_AWD2CR_AWD2CH_7               (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000080 */

+#define ADC_AWD2CR_AWD2CH_8               (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000100 */

+#define ADC_AWD2CR_AWD2CH_9               (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000200 */

+#define ADC_AWD2CR_AWD2CH_10              (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000400 */

+#define ADC_AWD2CR_AWD2CH_11              (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000800 */

+#define ADC_AWD2CR_AWD2CH_12              (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00001000 */

+#define ADC_AWD2CR_AWD2CH_13              (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00002000 */

+#define ADC_AWD2CR_AWD2CH_14              (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00004000 */

+#define ADC_AWD2CR_AWD2CH_15              (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00008000 */

+#define ADC_AWD2CR_AWD2CH_16              (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00010000 */

+#define ADC_AWD2CR_AWD2CH_17              (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00020000 */

+#define ADC_AWD2CR_AWD2CH_18              (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */

+#define ADC_AWD2CR_AWD2CH_19              (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_AWD3CR register  ********************/

+#define ADC_AWD3CR_AWD3CH_Pos             (0U)

+#define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x000FFFFF */

+#define ADC_AWD3CR_AWD3CH                 ADC_AWD3CR_AWD3CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */

+#define ADC_AWD3CR_AWD3CH_0               (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000001 */

+#define ADC_AWD3CR_AWD3CH_1               (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000002 */

+#define ADC_AWD3CR_AWD3CH_2               (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000004 */

+#define ADC_AWD3CR_AWD3CH_3               (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000008 */

+#define ADC_AWD3CR_AWD3CH_4               (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000010 */

+#define ADC_AWD3CR_AWD3CH_5               (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000020 */

+#define ADC_AWD3CR_AWD3CH_6               (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000040 */

+#define ADC_AWD3CR_AWD3CH_7               (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000080 */

+#define ADC_AWD3CR_AWD3CH_8               (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000100 */

+#define ADC_AWD3CR_AWD3CH_9               (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000200 */

+#define ADC_AWD3CR_AWD3CH_10              (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000400 */

+#define ADC_AWD3CR_AWD3CH_11              (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000800 */

+#define ADC_AWD3CR_AWD3CH_12              (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00001000 */

+#define ADC_AWD3CR_AWD3CH_13              (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00002000 */

+#define ADC_AWD3CR_AWD3CH_14              (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00004000 */

+#define ADC_AWD3CR_AWD3CH_15              (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00008000 */

+#define ADC_AWD3CR_AWD3CH_16              (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00010000 */

+#define ADC_AWD3CR_AWD3CH_17              (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00020000 */

+#define ADC_AWD3CR_AWD3CH_18              (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */

+#define ADC_AWD3CR_AWD3CH_19              (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_DIFSEL register  ********************/

+#define ADC_DIFSEL_DIFSEL_Pos             (0U)

+#define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */

+#define ADC_DIFSEL_DIFSEL                 ADC_DIFSEL_DIFSEL_Msk                 /*!< ADC differential modes for channels 1 to 18 */

+#define ADC_DIFSEL_DIFSEL_0               (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000001 */

+#define ADC_DIFSEL_DIFSEL_1               (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000002 */

+#define ADC_DIFSEL_DIFSEL_2               (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000004 */

+#define ADC_DIFSEL_DIFSEL_3               (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000008 */

+#define ADC_DIFSEL_DIFSEL_4               (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000010 */

+#define ADC_DIFSEL_DIFSEL_5               (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000020 */

+#define ADC_DIFSEL_DIFSEL_6               (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000040 */

+#define ADC_DIFSEL_DIFSEL_7               (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000080 */

+#define ADC_DIFSEL_DIFSEL_8               (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000100 */

+#define ADC_DIFSEL_DIFSEL_9               (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000200 */

+#define ADC_DIFSEL_DIFSEL_10              (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000400 */

+#define ADC_DIFSEL_DIFSEL_11              (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000800 */

+#define ADC_DIFSEL_DIFSEL_12              (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00001000 */

+#define ADC_DIFSEL_DIFSEL_13              (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00002000 */

+#define ADC_DIFSEL_DIFSEL_14              (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00004000 */

+#define ADC_DIFSEL_DIFSEL_15              (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00008000 */

+#define ADC_DIFSEL_DIFSEL_16              (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00010000 */

+#define ADC_DIFSEL_DIFSEL_17              (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00020000 */

+#define ADC_DIFSEL_DIFSEL_18              (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00040000 */

+#define ADC_DIFSEL_DIFSEL_19              (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_CALFACT register  ********************/

+#define ADC_CALFACT_CALFACT_S_Pos         (0U)

+#define ADC_CALFACT_CALFACT_S_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */

+#define ADC_CALFACT_CALFACT_S             ADC_CALFACT_CALFACT_S_Msk              /*!< ADC calibration factors in single-ended mode */

+#define ADC_CALFACT_CALFACT_S_0           (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */

+#define ADC_CALFACT_CALFACT_S_1           (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */

+#define ADC_CALFACT_CALFACT_S_2           (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */

+#define ADC_CALFACT_CALFACT_S_3           (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */

+#define ADC_CALFACT_CALFACT_S_4           (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */

+#define ADC_CALFACT_CALFACT_S_5           (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */

+#define ADC_CALFACT_CALFACT_S_6           (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */

+#define ADC_CALFACT_CALFACT_S_7           (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */

+#define ADC_CALFACT_CALFACT_S_8           (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */

+#define ADC_CALFACT_CALFACT_S_9           (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */

+#define ADC_CALFACT_CALFACT_S_10          (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */

+#define ADC_CALFACT_CALFACT_D_Pos         (16U)

+#define ADC_CALFACT_CALFACT_D_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */

+#define ADC_CALFACT_CALFACT_D             ADC_CALFACT_CALFACT_D_Msk              /*!< ADC calibration factors in differential mode */

+#define ADC_CALFACT_CALFACT_D_0           (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */

+#define ADC_CALFACT_CALFACT_D_1           (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */

+#define ADC_CALFACT_CALFACT_D_2           (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */

+#define ADC_CALFACT_CALFACT_D_3           (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */

+#define ADC_CALFACT_CALFACT_D_4           (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */

+#define ADC_CALFACT_CALFACT_D_5           (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */

+#define ADC_CALFACT_CALFACT_D_6           (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */

+#define ADC_CALFACT_CALFACT_D_7           (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */

+#define ADC_CALFACT_CALFACT_D_8           (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */

+#define ADC_CALFACT_CALFACT_D_9           (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */

+#define ADC_CALFACT_CALFACT_D_10          (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */

+

+/********************  Bit definition for ADC_CALFACT2 register  ********************/

+#define ADC_CALFACT2_LINCALFACT_Pos       (0U)

+#define ADC_CALFACT2_LINCALFACT_Msk       (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */

+#define ADC_CALFACT2_LINCALFACT           ADC_CALFACT2_LINCALFACT_Msk                   /*!< ADC Linearity calibration factors */

+#define ADC_CALFACT2_LINCALFACT_0         (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */

+#define ADC_CALFACT2_LINCALFACT_1         (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */

+#define ADC_CALFACT2_LINCALFACT_2         (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */

+#define ADC_CALFACT2_LINCALFACT_3         (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */

+#define ADC_CALFACT2_LINCALFACT_4         (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */

+#define ADC_CALFACT2_LINCALFACT_5         (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */

+#define ADC_CALFACT2_LINCALFACT_6         (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */

+#define ADC_CALFACT2_LINCALFACT_7         (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */

+#define ADC_CALFACT2_LINCALFACT_8         (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */

+#define ADC_CALFACT2_LINCALFACT_9         (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */

+#define ADC_CALFACT2_LINCALFACT_10        (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */

+#define ADC_CALFACT2_LINCALFACT_11        (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */

+#define ADC_CALFACT2_LINCALFACT_12        (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */

+#define ADC_CALFACT2_LINCALFACT_13        (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */

+#define ADC_CALFACT2_LINCALFACT_14        (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */

+#define ADC_CALFACT2_LINCALFACT_15        (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */

+#define ADC_CALFACT2_LINCALFACT_16        (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */

+#define ADC_CALFACT2_LINCALFACT_17        (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */

+#define ADC_CALFACT2_LINCALFACT_18        (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */

+#define ADC_CALFACT2_LINCALFACT_19        (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */

+#define ADC_CALFACT2_LINCALFACT_20        (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */

+#define ADC_CALFACT2_LINCALFACT_21        (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */

+#define ADC_CALFACT2_LINCALFACT_22        (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */

+#define ADC_CALFACT2_LINCALFACT_23        (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */

+#define ADC_CALFACT2_LINCALFACT_24        (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */

+#define ADC_CALFACT2_LINCALFACT_25        (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */

+#define ADC_CALFACT2_LINCALFACT_26        (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */

+#define ADC_CALFACT2_LINCALFACT_27        (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */

+#define ADC_CALFACT2_LINCALFACT_28        (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */

+#define ADC_CALFACT2_LINCALFACT_29        (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */

+

+/*************************  ADC Common registers  *****************************/

+/********************  Bit definition for ADC_CSR register  ********************/

+#define ADC_CSR_ADRDY_MST_Pos             (0U)

+#define ADC_CSR_ADRDY_MST_Msk             (0x1UL << ADC_CSR_ADRDY_MST_Pos)     /*!< 0x00000001 */

+#define ADC_CSR_ADRDY_MST                 ADC_CSR_ADRDY_MST_Msk                /*!< Master ADC ready */

+#define ADC_CSR_EOSMP_MST_Pos             (1U)

+#define ADC_CSR_EOSMP_MST_Msk             (0x1UL << ADC_CSR_EOSMP_MST_Pos)     /*!< 0x00000002 */

+#define ADC_CSR_EOSMP_MST                 ADC_CSR_EOSMP_MST_Msk                /*!< End of sampling phase flag of the master ADC */

+#define ADC_CSR_EOC_MST_Pos               (2U)

+#define ADC_CSR_EOC_MST_Msk               (0x1UL << ADC_CSR_EOC_MST_Pos)       /*!< 0x00000004 */

+#define ADC_CSR_EOC_MST                   ADC_CSR_EOC_MST_Msk                  /*!< End of regular conversion of the master ADC */

+#define ADC_CSR_EOS_MST_Pos               (3U)

+#define ADC_CSR_EOS_MST_Msk               (0x1UL << ADC_CSR_EOS_MST_Pos)       /*!< 0x00000008 */

+#define ADC_CSR_EOS_MST                   ADC_CSR_EOS_MST_Msk                  /*!< End of regular sequence flag of the master ADC */

+#define ADC_CSR_OVR_MST_Pos               (4U)

+#define ADC_CSR_OVR_MST_Msk               (0x1UL << ADC_CSR_OVR_MST_Pos)       /*!< 0x00000010 */

+#define ADC_CSR_OVR_MST                   ADC_CSR_OVR_MST_Msk                  /*!< Overrun flag of the master ADC */

+#define ADC_CSR_JEOC_MST_Pos              (5U)

+#define ADC_CSR_JEOC_MST_Msk              (0x1UL << ADC_CSR_JEOC_MST_Pos)      /*!< 0x00000020 */

+#define ADC_CSR_JEOC_MST                  ADC_CSR_JEOC_MST_Msk                 /*!< End of injected conversion of the master ADC */

+#define ADC_CSR_JEOS_MST_Pos              (6U)

+#define ADC_CSR_JEOS_MST_Msk              (0x1UL << ADC_CSR_JEOS_MST_Pos)      /*!< 0x00000040 */

+#define ADC_CSR_JEOS_MST                  ADC_CSR_JEOS_MST_Msk                 /*!< End of injected sequence flag of the master ADC */

+#define ADC_CSR_AWD1_MST_Pos              (7U)

+#define ADC_CSR_AWD1_MST_Msk              (0x1UL << ADC_CSR_AWD1_MST_Pos)      /*!< 0x00000080 */

+#define ADC_CSR_AWD1_MST                  ADC_CSR_AWD1_MST_Msk                 /*!< Analog watchdog 1 flag of the master ADC */

+#define ADC_CSR_AWD2_MST_Pos              (8U)

+#define ADC_CSR_AWD2_MST_Msk              (0x1UL << ADC_CSR_AWD2_MST_Pos)      /*!< 0x00000100 */

+#define ADC_CSR_AWD2_MST                  ADC_CSR_AWD2_MST_Msk                 /*!< Analog watchdog 2 flag of the master ADC */

+#define ADC_CSR_AWD3_MST_Pos              (9U)

+#define ADC_CSR_AWD3_MST_Msk              (0x1UL << ADC_CSR_AWD3_MST_Pos)      /*!< 0x00000200 */

+#define ADC_CSR_AWD3_MST                  ADC_CSR_AWD3_MST_Msk                 /*!< Analog watchdog 3 flag of the master ADC */

+#define ADC_CSR_JQOVF_MST_Pos             (10U)

+#define ADC_CSR_JQOVF_MST_Msk             (0x1UL << ADC_CSR_JQOVF_MST_Pos)     /*!< 0x00000400 */

+#define ADC_CSR_JQOVF_MST                 ADC_CSR_JQOVF_MST_Msk                /*!< Injected context queue overflow flag of the master ADC */

+#define ADC_CSR_ADRDY_SLV_Pos             (16U)

+#define ADC_CSR_ADRDY_SLV_Msk             (0x1UL << ADC_CSR_ADRDY_SLV_Pos)     /*!< 0x00010000 */

+#define ADC_CSR_ADRDY_SLV                 ADC_CSR_ADRDY_SLV_Msk                /*!< Slave ADC ready */

+#define ADC_CSR_EOSMP_SLV_Pos             (17U)

+#define ADC_CSR_EOSMP_SLV_Msk             (0x1UL << ADC_CSR_EOSMP_SLV_Pos)     /*!< 0x00020000 */

+#define ADC_CSR_EOSMP_SLV                 ADC_CSR_EOSMP_SLV_Msk                /*!< End of sampling phase flag of the slave ADC */

+#define ADC_CSR_EOC_SLV_Pos               (18U)

+#define ADC_CSR_EOC_SLV_Msk               (0x1UL << ADC_CSR_EOC_SLV_Pos)       /*!< 0x00040000 */

+#define ADC_CSR_EOC_SLV                   ADC_CSR_EOC_SLV_Msk                  /*!< End of regular conversion of the slave ADC */

+#define ADC_CSR_EOS_SLV_Pos               (19U)

+#define ADC_CSR_EOS_SLV_Msk               (0x1UL << ADC_CSR_EOS_SLV_Pos)       /*!< 0x00080000 */

+#define ADC_CSR_EOS_SLV                   ADC_CSR_EOS_SLV_Msk                  /*!< End of regular sequence flag of the slave ADC */

+#define ADC_CSR_OVR_SLV_Pos               (20U)

+#define ADC_CSR_OVR_SLV_Msk               (0x1UL << ADC_CSR_OVR_SLV_Pos)       /*!< 0x00100000 */

+#define ADC_CSR_OVR_SLV                   ADC_CSR_OVR_SLV_Msk                  /*!< Overrun flag of the slave ADC */

+#define ADC_CSR_JEOC_SLV_Pos              (21U)

+#define ADC_CSR_JEOC_SLV_Msk              (0x1UL << ADC_CSR_JEOC_SLV_Pos)      /*!< 0x00200000 */

+#define ADC_CSR_JEOC_SLV                  ADC_CSR_JEOC_SLV_Msk                 /*!< End of injected conversion of the slave ADC */

+#define ADC_CSR_JEOS_SLV_Pos              (22U)

+#define ADC_CSR_JEOS_SLV_Msk              (0x1UL << ADC_CSR_JEOS_SLV_Pos)      /*!< 0x00400000 */

+#define ADC_CSR_JEOS_SLV                  ADC_CSR_JEOS_SLV_Msk                 /*!< End of injected sequence flag of the slave ADC */

+#define ADC_CSR_AWD1_SLV_Pos              (23U)

+#define ADC_CSR_AWD1_SLV_Msk              (0x1UL << ADC_CSR_AWD1_SLV_Pos)      /*!< 0x00800000 */

+#define ADC_CSR_AWD1_SLV                  ADC_CSR_AWD1_SLV_Msk                 /*!< Analog watchdog 1 flag of the slave ADC */

+#define ADC_CSR_AWD2_SLV_Pos              (24U)

+#define ADC_CSR_AWD2_SLV_Msk              (0x1UL << ADC_CSR_AWD2_SLV_Pos)      /*!< 0x01000000 */

+#define ADC_CSR_AWD2_SLV                  ADC_CSR_AWD2_SLV_Msk                 /*!< Analog watchdog 2 flag of the slave ADC */

+#define ADC_CSR_AWD3_SLV_Pos              (25U)

+#define ADC_CSR_AWD3_SLV_Msk              (0x1UL << ADC_CSR_AWD3_SLV_Pos)      /*!< 0x02000000 */

+#define ADC_CSR_AWD3_SLV                  ADC_CSR_AWD3_SLV_Msk                 /*!< Analog watchdog 3 flag of the slave ADC */

+#define ADC_CSR_JQOVF_SLV_Pos             (26U)

+#define ADC_CSR_JQOVF_SLV_Msk             (0x1UL << ADC_CSR_JQOVF_SLV_Pos)     /*!< 0x04000000 */

+#define ADC_CSR_JQOVF_SLV                 ADC_CSR_JQOVF_SLV_Msk                /*!< Injected context queue overflow flag of the slave ADC */

+

+/********************  Bit definition for ADC_CCR register  ********************/

+#define ADC_CCR_DUAL_Pos                  (0U)

+#define ADC_CCR_DUAL_Msk                  (0x1FUL << ADC_CCR_DUAL_Pos)          /*!< 0x0000001F */

+#define ADC_CCR_DUAL                      ADC_CCR_DUAL_Msk                      /*!< Dual ADC mode selection */

+#define ADC_CCR_DUAL_0                    (0x01UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000001 */

+#define ADC_CCR_DUAL_1                    (0x02UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000002 */

+#define ADC_CCR_DUAL_2                    (0x04UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000004 */

+#define ADC_CCR_DUAL_3                    (0x08UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000008 */

+#define ADC_CCR_DUAL_4                    (0x10UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000010 */

+

+#define ADC_CCR_DELAY_Pos                 (8U)

+#define ADC_CCR_DELAY_Msk                 (0xFUL << ADC_CCR_DELAY_Pos)          /*!< 0x00000F00 */

+#define ADC_CCR_DELAY                     ADC_CCR_DELAY_Msk                     /*!< Delay between 2 sampling phases */

+#define ADC_CCR_DELAY_0                   (0x1UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000100 */

+#define ADC_CCR_DELAY_1                   (0x2UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000200 */

+#define ADC_CCR_DELAY_2                   (0x4UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000400 */

+#define ADC_CCR_DELAY_3                   (0x8UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000800 */

+

+

+#define ADC_CCR_DAMDF_Pos                 (14U)

+#define ADC_CCR_DAMDF_Msk                 (0x3UL << ADC_CCR_DAMDF_Pos)          /*!< 0x0000C000 */

+#define ADC_CCR_DAMDF                     ADC_CCR_DAMDF_Msk                     /*!< Dual ADC mode Data format */

+#define ADC_CCR_DAMDF_0                   (0x1UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00004000 */

+#define ADC_CCR_DAMDF_1                   (0x2UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00008000 */

+

+#define ADC_CCR_CKMODE_Pos                (16U)

+#define ADC_CCR_CKMODE_Msk                (0x3UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00030000 */

+#define ADC_CCR_CKMODE                    ADC_CCR_CKMODE_Msk                    /*!< ADC clock mode */

+#define ADC_CCR_CKMODE_0                  (0x1UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00010000 */

+#define ADC_CCR_CKMODE_1                  (0x2UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00020000 */

+

+#define ADC_CCR_PRESC_Pos                 (18U)

+#define ADC_CCR_PRESC_Msk                 (0xFUL << ADC_CCR_PRESC_Pos)          /*!< 0x003C0000 */

+#define ADC_CCR_PRESC                     ADC_CCR_PRESC_Msk                     /*!< ADC prescaler */

+#define ADC_CCR_PRESC_0                   (0x1UL << ADC_CCR_PRESC_Pos)          /*!< 0x00040000 */

+#define ADC_CCR_PRESC_1                   (0x2UL << ADC_CCR_PRESC_Pos)          /*!< 0x00080000 */

+#define ADC_CCR_PRESC_2                   (0x4UL << ADC_CCR_PRESC_Pos)          /*!< 0x00100000 */

+#define ADC_CCR_PRESC_3                   (0x8UL << ADC_CCR_PRESC_Pos)          /*!< 0x00200000 */

+

+#define ADC_CCR_VREFEN_Pos                (22U)

+#define ADC_CCR_VREFEN_Msk                (0x1UL << ADC_CCR_VREFEN_Pos)         /*!< 0x00400000 */

+#define ADC_CCR_VREFEN                    ADC_CCR_VREFEN_Msk                    /*!< VREFINT enable */

+#define ADC_CCR_TSEN_Pos                  (23U)

+#define ADC_CCR_TSEN_Msk                  (0x1UL << ADC_CCR_TSEN_Pos)           /*!< 0x00800000 */

+#define ADC_CCR_TSEN                      ADC_CCR_TSEN_Msk                      /*!< Temperature sensor enable */

+#define ADC_CCR_VBATEN_Pos                (24U)

+#define ADC_CCR_VBATEN_Msk                (0x1UL << ADC_CCR_VBATEN_Pos)         /*!< 0x01000000 */

+#define ADC_CCR_VBATEN                    ADC_CCR_VBATEN_Msk                    /*!< VBAT enable */

+

+/********************  Bit definition for ADC_CDR register  *******************/

+#define ADC_CDR_RDATA_MST_Pos             (0U)

+#define ADC_CDR_RDATA_MST_Msk             (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)   /*!< 0x0000FFFF */

+#define ADC_CDR_RDATA_MST                 ADC_CDR_RDATA_MST_Msk                 /*!< ADC multimode master group regular conversion data */

+

+#define ADC_CDR_RDATA_SLV_Pos             (16U)

+#define ADC_CDR_RDATA_SLV_Msk             (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)   /*!< 0xFFFF0000 */

+#define ADC_CDR_RDATA_SLV                 ADC_CDR_RDATA_SLV_Msk                 /*!< ADC multimode slave group regular conversion data */

+

+/********************  Bit definition for ADC_CDR2 register  ******************/

+#define ADC_CDR2_RDATA_ALT_Pos            (0U)

+#define ADC_CDR2_RDATA_ALT_Msk            (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */

+#define ADC_CDR2_RDATA_ALT                ADC_CDR2_RDATA_ALT_Msk                   /*!< Regular data of the master/slave alternated ADCs */

+

+/******************************************************************************/

+/*                                                                            */

+/*                        ART accelerator                                     */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for ART_CTR register  ********************/

+#define ART_CTR_EN_Pos              (0U)

+#define ART_CTR_EN_Msk              (0x1UL << ART_CTR_EN_Pos)                /*!< 0x00000001 */

+#define ART_CTR_EN                  ART_CTR_EN_Msk                           /*!< Cache enable*/

+

+#define ART_CTR_PCACHEADDR_Pos      (8U)

+#define ART_CTR_PCACHEADDR_Msk      (0xFFFUL << ART_CTR_PCACHEADDR_Pos)      /*!< 0x000FFF00 */

+#define ART_CTR_PCACHEADDR          ART_CTR_PCACHEADDR_Msk                   /*!< Cacheable page index */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                   VREFBUF                                  */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for VREFBUF_CSR register  ****************/

+#define VREFBUF_CSR_ENVR_Pos        (0U)

+#define VREFBUF_CSR_ENVR_Msk        (0x1UL << VREFBUF_CSR_ENVR_Pos)            /*!< 0x00000001 */

+#define VREFBUF_CSR_ENVR            VREFBUF_CSR_ENVR_Msk                       /*!<Voltage reference buffer enable */

+#define VREFBUF_CSR_HIZ_Pos         (1U)

+#define VREFBUF_CSR_HIZ_Msk         (0x1UL << VREFBUF_CSR_HIZ_Pos)             /*!< 0x00000002 */

+#define VREFBUF_CSR_HIZ             VREFBUF_CSR_HIZ_Msk                        /*!<High impedance mode             */

+#define VREFBUF_CSR_VRR_Pos         (3U)

+#define VREFBUF_CSR_VRR_Msk         (0x1UL << VREFBUF_CSR_VRR_Pos)             /*!< 0x00000008 */

+#define VREFBUF_CSR_VRR             VREFBUF_CSR_VRR_Msk                        /*!<Voltage reference buffer ready  */

+#define VREFBUF_CSR_VRS_Pos         (4U)

+#define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */

+#define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */

+

+#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */

+#define VREFBUF_CSR_VRS_OUT2_Pos    (4U)

+#define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */

+#define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */

+#define VREFBUF_CSR_VRS_OUT3_Pos    (5U)

+#define VREFBUF_CSR_VRS_OUT3_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)        /*!< 0x00000020 */

+#define VREFBUF_CSR_VRS_OUT3        VREFBUF_CSR_VRS_OUT3_Msk                   /*!<Voltage reference VREF_OUT3     */

+#define VREFBUF_CSR_VRS_OUT4_Pos    (4U)

+#define VREFBUF_CSR_VRS_OUT4_Msk    (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)        /*!< 0x00000030 */

+#define VREFBUF_CSR_VRS_OUT4        VREFBUF_CSR_VRS_OUT4_Msk                   /*!<Voltage reference VREF_OUT4     */

+

+/*******************  Bit definition for VREFBUF_CCR register  ****************/

+#define VREFBUF_CCR_TRIM_Pos        (0U)

+#define VREFBUF_CCR_TRIM_Msk        (0x3FUL << VREFBUF_CCR_TRIM_Pos)           /*!< 0x0000003F */

+#define VREFBUF_CCR_TRIM            VREFBUF_CCR_TRIM_Msk                       /*!<TRIM[5:0] bits (Trimming code)  */

+

+/******************************************************************************/

+/*                                                                            */

+/*                 Flexible Datarate Controller Area Network                  */

+/*                                                                            */

+/******************************************************************************/

+/*!<FDCAN control and status registers */

+/*****************  Bit definition for FDCAN_CREL register  *******************/

+#define FDCAN_CREL_DAY_Pos        (0U)

+#define FDCAN_CREL_DAY_Msk        (0xFFUL << FDCAN_CREL_DAY_Pos)               /*!< 0x000000FF */

+#define FDCAN_CREL_DAY            FDCAN_CREL_DAY_Msk                           /*!<Timestamp Day                           */

+#define FDCAN_CREL_MON_Pos        (8U)

+#define FDCAN_CREL_MON_Msk        (0xFFUL << FDCAN_CREL_MON_Pos)               /*!< 0x0000FF00 */

+#define FDCAN_CREL_MON            FDCAN_CREL_MON_Msk                           /*!<Timestamp Month                         */

+#define FDCAN_CREL_YEAR_Pos       (16U)

+#define FDCAN_CREL_YEAR_Msk       (0xFUL << FDCAN_CREL_YEAR_Pos)               /*!< 0x000F0000 */

+#define FDCAN_CREL_YEAR           FDCAN_CREL_YEAR_Msk                          /*!<Timestamp Year                          */

+#define FDCAN_CREL_SUBSTEP_Pos    (20U)

+#define FDCAN_CREL_SUBSTEP_Msk    (0xFUL << FDCAN_CREL_SUBSTEP_Pos)            /*!< 0x00F00000 */

+#define FDCAN_CREL_SUBSTEP        FDCAN_CREL_SUBSTEP_Msk                       /*!<Sub-step of Core release                */

+#define FDCAN_CREL_STEP_Pos       (24U)

+#define FDCAN_CREL_STEP_Msk       (0xFUL << FDCAN_CREL_STEP_Pos)               /*!< 0x0F000000 */

+#define FDCAN_CREL_STEP           FDCAN_CREL_STEP_Msk                          /*!<Step of Core release                    */

+#define FDCAN_CREL_REL_Pos        (28U)

+#define FDCAN_CREL_REL_Msk        (0xFUL << FDCAN_CREL_REL_Pos)                /*!< 0xF0000000 */

+#define FDCAN_CREL_REL            FDCAN_CREL_REL_Msk                           /*!<Core release                            */

+

+/*****************  Bit definition for FDCAN_ENDN register  *******************/

+#define FDCAN_ENDN_ETV_Pos        (0U)

+#define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endiannes Test Value                    */

+

+/*****************  Bit definition for FDCAN_DBTP register  *******************/

+#define FDCAN_DBTP_DSJW_Pos       (0U)

+#define FDCAN_DBTP_DSJW_Msk       (0xFUL << FDCAN_DBTP_DSJW_Pos)               /*!< 0x0000000F */

+#define FDCAN_DBTP_DSJW           FDCAN_DBTP_DSJW_Msk                          /*!<Synchronization Jump Width              */

+#define FDCAN_DBTP_DTSEG2_Pos     (4U)

+#define FDCAN_DBTP_DTSEG2_Msk     (0xFUL << FDCAN_DBTP_DTSEG2_Pos)             /*!< 0x000000F0 */

+#define FDCAN_DBTP_DTSEG2         FDCAN_DBTP_DTSEG2_Msk                        /*!<Data time segment after sample point    */

+#define FDCAN_DBTP_DTSEG1_Pos     (8U)

+#define FDCAN_DBTP_DTSEG1_Msk     (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)            /*!< 0x00001F00 */

+#define FDCAN_DBTP_DTSEG1         FDCAN_DBTP_DTSEG1_Msk                        /*!<Data time segment before sample point   */

+#define FDCAN_DBTP_DBRP_Pos       (16U)

+#define FDCAN_DBTP_DBRP_Msk       (0x1FUL << FDCAN_DBTP_DBRP_Pos)              /*!< 0x001F0000 */

+#define FDCAN_DBTP_DBRP           FDCAN_DBTP_DBRP_Msk                          /*!<Data BIt Rate Prescaler                 */

+#define FDCAN_DBTP_TDC_Pos        (23U)

+#define FDCAN_DBTP_TDC_Msk        (0x1UL << FDCAN_DBTP_TDC_Pos)                /*!< 0x00800000 */

+#define FDCAN_DBTP_TDC            FDCAN_DBTP_TDC_Msk                           /*!<Transceiver Delay Compensation          */

+

+/*****************  Bit definition for FDCAN_TEST register  *******************/

+#define FDCAN_TEST_LBCK_Pos       (4U)

+#define FDCAN_TEST_LBCK_Msk       (0x1UL << FDCAN_TEST_LBCK_Pos)               /*!< 0x00000010 */

+#define FDCAN_TEST_LBCK           FDCAN_TEST_LBCK_Msk                          /*!<Loop Back mode                           */

+#define FDCAN_TEST_TX_Pos         (5U)

+#define FDCAN_TEST_TX_Msk         (0x3UL << FDCAN_TEST_TX_Pos)                 /*!< 0x00000060 */

+#define FDCAN_TEST_TX             FDCAN_TEST_TX_Msk                            /*!<Control of Transmit Pin                  */

+#define FDCAN_TEST_RX_Pos         (7U)

+#define FDCAN_TEST_RX_Msk         (0x1UL << FDCAN_TEST_RX_Pos)                 /*!< 0x00000080 */

+#define FDCAN_TEST_RX             FDCAN_TEST_RX_Msk                            /*!<Receive Pin                              */

+

+/*****************  Bit definition for FDCAN_RWD register  ********************/

+#define FDCAN_RWD_WDC_Pos         (0U)

+#define FDCAN_RWD_WDC_Msk         (0xFFUL << FDCAN_RWD_WDC_Pos)                /*!< 0x000000FF */

+#define FDCAN_RWD_WDC             FDCAN_RWD_WDC_Msk                            /*!<Watchdog configuration                   */

+#define FDCAN_RWD_WDV_Pos         (8U)

+#define FDCAN_RWD_WDV_Msk         (0xFFUL << FDCAN_RWD_WDV_Pos)                /*!< 0x0000FF00 */

+#define FDCAN_RWD_WDV             FDCAN_RWD_WDV_Msk                            /*!<Watchdog value                           */

+

+/*****************  Bit definition for FDCAN_CCCR register  ********************/

+#define FDCAN_CCCR_INIT_Pos       (0U)

+#define FDCAN_CCCR_INIT_Msk       (0x1UL << FDCAN_CCCR_INIT_Pos)               /*!< 0x00000001 */

+#define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!<Initialization                           */

+#define FDCAN_CCCR_CCE_Pos        (1U)

+#define FDCAN_CCCR_CCE_Msk        (0x1UL << FDCAN_CCCR_CCE_Pos)                /*!< 0x00000002 */

+#define FDCAN_CCCR_CCE            FDCAN_CCCR_CCE_Msk                           /*!<Configuration Change Enable              */

+#define FDCAN_CCCR_ASM_Pos        (2U)

+#define FDCAN_CCCR_ASM_Msk        (0x1UL << FDCAN_CCCR_ASM_Pos)                /*!< 0x00000004 */

+#define FDCAN_CCCR_ASM            FDCAN_CCCR_ASM_Msk                           /*!<ASM Restricted Operation Mode            */

+#define FDCAN_CCCR_CSA_Pos        (3U)

+#define FDCAN_CCCR_CSA_Msk        (0x1UL << FDCAN_CCCR_CSA_Pos)                /*!< 0x00000008 */

+#define FDCAN_CCCR_CSA            FDCAN_CCCR_CSA_Msk                           /*!<Clock Stop Acknowledge                   */

+#define FDCAN_CCCR_CSR_Pos        (4U)

+#define FDCAN_CCCR_CSR_Msk        (0x1UL << FDCAN_CCCR_CSR_Pos)                /*!< 0x00000010 */

+#define FDCAN_CCCR_CSR            FDCAN_CCCR_CSR_Msk                           /*!<Clock Stop Request                       */

+#define FDCAN_CCCR_MON_Pos        (5U)

+#define FDCAN_CCCR_MON_Msk        (0x1UL << FDCAN_CCCR_MON_Pos)                /*!< 0x00000020 */

+#define FDCAN_CCCR_MON            FDCAN_CCCR_MON_Msk                           /*!<Bus Monitoring Mode                      */

+#define FDCAN_CCCR_DAR_Pos        (6U)

+#define FDCAN_CCCR_DAR_Msk        (0x1UL << FDCAN_CCCR_DAR_Pos)                /*!< 0x00000040 */

+#define FDCAN_CCCR_DAR            FDCAN_CCCR_DAR_Msk                           /*!<Disable Automatic Retransmission         */

+#define FDCAN_CCCR_TEST_Pos       (7U)

+#define FDCAN_CCCR_TEST_Msk       (0x1UL << FDCAN_CCCR_TEST_Pos)               /*!< 0x00000080 */

+#define FDCAN_CCCR_TEST           FDCAN_CCCR_TEST_Msk                          /*!<Test Mode Enable                         */

+#define FDCAN_CCCR_FDOE_Pos       (8U)

+#define FDCAN_CCCR_FDOE_Msk       (0x1UL << FDCAN_CCCR_FDOE_Pos)               /*!< 0x00000100 */

+#define FDCAN_CCCR_FDOE           FDCAN_CCCR_FDOE_Msk                          /*!<FD Operation Enable                      */

+#define FDCAN_CCCR_BRSE_Pos       (9U)

+#define FDCAN_CCCR_BRSE_Msk       (0x1UL << FDCAN_CCCR_BRSE_Pos)               /*!< 0x00000200 */

+#define FDCAN_CCCR_BRSE           FDCAN_CCCR_BRSE_Msk                          /*!<FDCAN Bit Rate Switching                 */

+#define FDCAN_CCCR_PXHD_Pos       (12U)

+#define FDCAN_CCCR_PXHD_Msk       (0x1UL << FDCAN_CCCR_PXHD_Pos)               /*!< 0x00001000 */

+#define FDCAN_CCCR_PXHD           FDCAN_CCCR_PXHD_Msk                          /*!<Protocol Exception Handling Disable      */

+#define FDCAN_CCCR_EFBI_Pos       (13U)

+#define FDCAN_CCCR_EFBI_Msk       (0x1UL << FDCAN_CCCR_EFBI_Pos)               /*!< 0x00002000 */

+#define FDCAN_CCCR_EFBI           FDCAN_CCCR_EFBI_Msk                          /*!<Edge Filtering during Bus Integration    */

+#define FDCAN_CCCR_TXP_Pos        (14U)

+#define FDCAN_CCCR_TXP_Msk        (0x1UL << FDCAN_CCCR_TXP_Pos)                /*!< 0x00004000 */

+#define FDCAN_CCCR_TXP            FDCAN_CCCR_TXP_Msk                           /*!<Two CAN bit times Pause                  */

+#define FDCAN_CCCR_NISO_Pos       (15U)

+#define FDCAN_CCCR_NISO_Msk       (0x1UL << FDCAN_CCCR_NISO_Pos)               /*!< 0x00008000 */

+#define FDCAN_CCCR_NISO           FDCAN_CCCR_NISO_Msk                          /*!<Non ISO Operation                        */

+

+/*****************  Bit definition for FDCAN_NBTP register  ********************/

+#define FDCAN_NBTP_NTSEG2_Pos     (0U)

+#define FDCAN_NBTP_NTSEG2_Msk     (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)            /*!< 0x0000007F */

+#define FDCAN_NBTP_NTSEG2         FDCAN_NBTP_NTSEG2_Msk                        /*!<Nominal Time segment after sample point  */

+#define FDCAN_NBTP_NTSEG1_Pos     (8U)

+#define FDCAN_NBTP_NTSEG1_Msk     (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)            /*!< 0x0000FF00 */

+#define FDCAN_NBTP_NTSEG1         FDCAN_NBTP_NTSEG1_Msk                        /*!<Nominal Time segment before sample point */

+#define FDCAN_NBTP_NBRP_Pos       (16U)

+#define FDCAN_NBTP_NBRP_Msk       (0x1FFUL << FDCAN_NBTP_NBRP_Pos)             /*!< 0x01FF0000 */

+#define FDCAN_NBTP_NBRP           FDCAN_NBTP_NBRP_Msk                          /*!<Bit Rate Prescaler                       */

+#define FDCAN_NBTP_NSJW_Pos       (25U)

+#define FDCAN_NBTP_NSJW_Msk       (0x7FUL << FDCAN_NBTP_NSJW_Pos)              /*!< 0xFE000000 */

+#define FDCAN_NBTP_NSJW           FDCAN_NBTP_NSJW_Msk                          /*!<Nominal (Re)Synchronization Jump Width   */

+

+/*****************  Bit definition for FDCAN_TSCC register  ********************/

+#define FDCAN_TSCC_TSS_Pos        (0U)

+#define FDCAN_TSCC_TSS_Msk        (0x3UL << FDCAN_TSCC_TSS_Pos)                /*!< 0x00000003 */

+#define FDCAN_TSCC_TSS            FDCAN_TSCC_TSS_Msk                           /*!<Timestamp Select                         */

+#define FDCAN_TSCC_TCP_Pos        (16U)

+#define FDCAN_TSCC_TCP_Msk        (0xFUL << FDCAN_TSCC_TCP_Pos)                /*!< 0x000F0000 */

+#define FDCAN_TSCC_TCP            FDCAN_TSCC_TCP_Msk                           /*!<Timestamp Counter Prescaler              */

+

+/*****************  Bit definition for FDCAN_TSCV register  ********************/

+#define FDCAN_TSCV_TSC_Pos        (0U)

+#define FDCAN_TSCV_TSC_Msk        (0xFFFFUL << FDCAN_TSCV_TSC_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TSCV_TSC            FDCAN_TSCV_TSC_Msk                           /*!<Timestamp Counter                        */

+

+/*****************  Bit definition for FDCAN_TOCC register  ********************/

+#define FDCAN_TOCC_ETOC_Pos       (0U)

+#define FDCAN_TOCC_ETOC_Msk       (0x1UL << FDCAN_TOCC_ETOC_Pos)               /*!< 0x00000001 */

+#define FDCAN_TOCC_ETOC           FDCAN_TOCC_ETOC_Msk                          /*!<Enable Timeout Counter                   */

+#define FDCAN_TOCC_TOS_Pos        (1U)

+#define FDCAN_TOCC_TOS_Msk        (0x3UL << FDCAN_TOCC_TOS_Pos)                /*!< 0x00000006 */

+#define FDCAN_TOCC_TOS            FDCAN_TOCC_TOS_Msk                           /*!<Timeout Select                           */

+#define FDCAN_TOCC_TOP_Pos        (16U)

+#define FDCAN_TOCC_TOP_Msk        (0xFFFFUL << FDCAN_TOCC_TOP_Pos)             /*!< 0xFFFF0000 */

+#define FDCAN_TOCC_TOP            FDCAN_TOCC_TOP_Msk                           /*!<Timeout Period                           */

+

+/*****************  Bit definition for FDCAN_TOCV register  ********************/

+#define FDCAN_TOCV_TOC_Pos        (0U)

+#define FDCAN_TOCV_TOC_Msk        (0xFFFFUL << FDCAN_TOCV_TOC_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TOCV_TOC            FDCAN_TOCV_TOC_Msk                           /*!<Timeout Counter                          */

+

+/*****************  Bit definition for FDCAN_ECR register  *********************/

+#define FDCAN_ECR_TEC_Pos         (0U)

+#define FDCAN_ECR_TEC_Msk         (0xFUL << FDCAN_ECR_TEC_Pos)                 /*!< 0x0000000F */

+#define FDCAN_ECR_TEC             FDCAN_ECR_TEC_Msk                            /*!<Transmit Error Counter                   */

+#define FDCAN_ECR_REC_Pos         (8U)

+#define FDCAN_ECR_REC_Msk         (0x7FUL << FDCAN_ECR_REC_Pos)                /*!< 0x00007F00 */

+#define FDCAN_ECR_REC             FDCAN_ECR_REC_Msk                            /*!<Receive Error Counter                    */

+#define FDCAN_ECR_RP_Pos          (15U)

+#define FDCAN_ECR_RP_Msk          (0x1UL << FDCAN_ECR_RP_Pos)                  /*!< 0x00008000 */

+#define FDCAN_ECR_RP              FDCAN_ECR_RP_Msk                             /*!<Receive Error Passive                    */

+#define FDCAN_ECR_CEL_Pos         (16U)

+#define FDCAN_ECR_CEL_Msk         (0xFFUL << FDCAN_ECR_CEL_Pos)                /*!< 0x00FF0000 */

+#define FDCAN_ECR_CEL             FDCAN_ECR_CEL_Msk                            /*!<CAN Error Logging                        */

+

+/*****************  Bit definition for FDCAN_PSR register  *********************/

+#define FDCAN_PSR_LEC_Pos         (0U)

+#define FDCAN_PSR_LEC_Msk         (0x7UL << FDCAN_PSR_LEC_Pos)                 /*!< 0x00000007 */

+#define FDCAN_PSR_LEC             FDCAN_PSR_LEC_Msk                            /*!<Last Error Code                          */

+#define FDCAN_PSR_ACT_Pos         (3U)

+#define FDCAN_PSR_ACT_Msk         (0x3UL << FDCAN_PSR_ACT_Pos)                 /*!< 0x00000018 */

+#define FDCAN_PSR_ACT             FDCAN_PSR_ACT_Msk                            /*!<Activity                                 */

+#define FDCAN_PSR_EP_Pos          (5U)

+#define FDCAN_PSR_EP_Msk          (0x1UL << FDCAN_PSR_EP_Pos)                  /*!< 0x00000020 */

+#define FDCAN_PSR_EP              FDCAN_PSR_EP_Msk                             /*!<Error Passive                            */

+#define FDCAN_PSR_EW_Pos          (6U)

+#define FDCAN_PSR_EW_Msk          (0x1UL << FDCAN_PSR_EW_Pos)                  /*!< 0x00000040 */

+#define FDCAN_PSR_EW              FDCAN_PSR_EW_Msk                             /*!<Warning Status                           */

+#define FDCAN_PSR_BO_Pos          (7U)

+#define FDCAN_PSR_BO_Msk          (0x1UL << FDCAN_PSR_BO_Pos)                  /*!< 0x00000080 */

+#define FDCAN_PSR_BO              FDCAN_PSR_BO_Msk                             /*!<Bus_Off Status                           */

+#define FDCAN_PSR_DLEC_Pos        (8U)

+#define FDCAN_PSR_DLEC_Msk        (0x7UL << FDCAN_PSR_DLEC_Pos)                /*!< 0x00000700 */

+#define FDCAN_PSR_DLEC            FDCAN_PSR_DLEC_Msk                           /*!<Data Last Error Code                     */

+#define FDCAN_PSR_RESI_Pos        (11U)

+#define FDCAN_PSR_RESI_Msk        (0x1UL << FDCAN_PSR_RESI_Pos)                /*!< 0x00000800 */

+#define FDCAN_PSR_RESI            FDCAN_PSR_RESI_Msk                           /*!<ESI flag of last received FDCAN Message  */

+#define FDCAN_PSR_RBRS_Pos        (12U)

+#define FDCAN_PSR_RBRS_Msk        (0x1UL << FDCAN_PSR_RBRS_Pos)                /*!< 0x00001000 */

+#define FDCAN_PSR_RBRS            FDCAN_PSR_RBRS_Msk                           /*!<BRS flag of last received FDCAN Message  */

+#define FDCAN_PSR_REDL_Pos        (13U)

+#define FDCAN_PSR_REDL_Msk        (0x1UL << FDCAN_PSR_REDL_Pos)                /*!< 0x00002000 */

+#define FDCAN_PSR_REDL            FDCAN_PSR_REDL_Msk                           /*!<Received FDCAN Message                   */

+#define FDCAN_PSR_PXE_Pos         (14U)

+#define FDCAN_PSR_PXE_Msk         (0x1UL << FDCAN_PSR_PXE_Pos)                 /*!< 0x00004000 */

+#define FDCAN_PSR_PXE             FDCAN_PSR_PXE_Msk                            /*!<Protocol Exception Event                 */

+#define FDCAN_PSR_TDCV_Pos        (16U)

+#define FDCAN_PSR_TDCV_Msk        (0x7FUL << FDCAN_PSR_TDCV_Pos)               /*!< 0x007F0000 */

+#define FDCAN_PSR_TDCV            FDCAN_PSR_TDCV_Msk                           /*!<Transmitter Delay Compensation Value     */

+

+/*****************  Bit definition for FDCAN_TDCR register  ********************/

+#define FDCAN_TDCR_TDCF_Pos       (0U)

+#define FDCAN_TDCR_TDCF_Msk       (0x7FUL << FDCAN_TDCR_TDCF_Pos)              /*!< 0x0000007F */

+#define FDCAN_TDCR_TDCF           FDCAN_TDCR_TDCF_Msk                          /*!<Transmitter Delay Compensation Filter    */

+#define FDCAN_TDCR_TDCO_Pos       (8U)

+#define FDCAN_TDCR_TDCO_Msk       (0x7FUL << FDCAN_TDCR_TDCO_Pos)              /*!< 0x00007F00 */

+#define FDCAN_TDCR_TDCO           FDCAN_TDCR_TDCO_Msk                          /*!<Transmitter Delay Compensation Offset    */

+

+/*****************  Bit definition for FDCAN_IR register  **********************/

+#define FDCAN_IR_RF0N_Pos         (0U)

+#define FDCAN_IR_RF0N_Msk         (0x1UL << FDCAN_IR_RF0N_Pos)                 /*!< 0x00000001 */

+#define FDCAN_IR_RF0N             FDCAN_IR_RF0N_Msk                            /*!<Rx FIFO 0 New Message                    */

+#define FDCAN_IR_RF0W_Pos         (1U)

+#define FDCAN_IR_RF0W_Msk         (0x1UL << FDCAN_IR_RF0W_Pos)                 /*!< 0x00000002 */

+#define FDCAN_IR_RF0W             FDCAN_IR_RF0W_Msk                            /*!<Rx FIFO 0 Watermark Reached              */

+#define FDCAN_IR_RF0F_Pos         (2U)

+#define FDCAN_IR_RF0F_Msk         (0x1UL << FDCAN_IR_RF0F_Pos)                 /*!< 0x00000004 */

+#define FDCAN_IR_RF0F             FDCAN_IR_RF0F_Msk                            /*!<Rx FIFO 0 Full                           */

+#define FDCAN_IR_RF0L_Pos         (3U)

+#define FDCAN_IR_RF0L_Msk         (0x1UL << FDCAN_IR_RF0L_Pos)                 /*!< 0x00000008 */

+#define FDCAN_IR_RF0L             FDCAN_IR_RF0L_Msk                            /*!<Rx FIFO 0 Message Lost                   */

+#define FDCAN_IR_RF1N_Pos         (4U)

+#define FDCAN_IR_RF1N_Msk         (0x1UL << FDCAN_IR_RF1N_Pos)                 /*!< 0x00000010 */

+#define FDCAN_IR_RF1N             FDCAN_IR_RF1N_Msk                            /*!<Rx FIFO 1 New Message                    */

+#define FDCAN_IR_RF1W_Pos         (5U)

+#define FDCAN_IR_RF1W_Msk         (0x1UL << FDCAN_IR_RF1W_Pos)                 /*!< 0x00000020 */

+#define FDCAN_IR_RF1W             FDCAN_IR_RF1W_Msk                            /*!<Rx FIFO 1 Watermark Reached              */

+#define FDCAN_IR_RF1F_Pos         (6U)

+#define FDCAN_IR_RF1F_Msk         (0x1UL << FDCAN_IR_RF1F_Pos)                 /*!< 0x00000040 */

+#define FDCAN_IR_RF1F             FDCAN_IR_RF1F_Msk                            /*!<Rx FIFO 1 Full                           */

+#define FDCAN_IR_RF1L_Pos         (7U)

+#define FDCAN_IR_RF1L_Msk         (0x1UL << FDCAN_IR_RF1L_Pos)                 /*!< 0x00000080 */

+#define FDCAN_IR_RF1L             FDCAN_IR_RF1L_Msk                            /*!<Rx FIFO 1 Message Lost                   */

+#define FDCAN_IR_HPM_Pos          (8U)

+#define FDCAN_IR_HPM_Msk          (0x1UL << FDCAN_IR_HPM_Pos)                  /*!< 0x00000100 */

+#define FDCAN_IR_HPM              FDCAN_IR_HPM_Msk                             /*!<High Priority Message                    */

+#define FDCAN_IR_TC_Pos           (9U)

+#define FDCAN_IR_TC_Msk           (0x1UL << FDCAN_IR_TC_Pos)                   /*!< 0x00000200 */

+#define FDCAN_IR_TC               FDCAN_IR_TC_Msk                              /*!<Transmission Completed                   */

+#define FDCAN_IR_TCF_Pos          (10U)

+#define FDCAN_IR_TCF_Msk          (0x1UL << FDCAN_IR_TCF_Pos)                  /*!< 0x00000400 */

+#define FDCAN_IR_TCF              FDCAN_IR_TCF_Msk                             /*!<Transmission Cancellation Finished       */

+#define FDCAN_IR_TFE_Pos          (11U)

+#define FDCAN_IR_TFE_Msk          (0x1UL << FDCAN_IR_TFE_Pos)                  /*!< 0x00000800 */

+#define FDCAN_IR_TFE              FDCAN_IR_TFE_Msk                             /*!<Tx FIFO Empty                            */

+#define FDCAN_IR_TEFN_Pos         (12U)

+#define FDCAN_IR_TEFN_Msk         (0x1UL << FDCAN_IR_TEFN_Pos)                 /*!< 0x00001000 */

+#define FDCAN_IR_TEFN             FDCAN_IR_TEFN_Msk                            /*!<Tx Event FIFO New Entry                  */

+#define FDCAN_IR_TEFW_Pos         (13U)

+#define FDCAN_IR_TEFW_Msk         (0x1UL << FDCAN_IR_TEFW_Pos)                 /*!< 0x00002000 */

+#define FDCAN_IR_TEFW             FDCAN_IR_TEFW_Msk                            /*!<Tx Event FIFO Watermark Reached          */

+#define FDCAN_IR_TEFF_Pos         (14U)

+#define FDCAN_IR_TEFF_Msk         (0x1UL << FDCAN_IR_TEFF_Pos)                 /*!< 0x00004000 */

+#define FDCAN_IR_TEFF             FDCAN_IR_TEFF_Msk                            /*!<Tx Event FIFO Full                       */

+#define FDCAN_IR_TEFL_Pos         (15U)

+#define FDCAN_IR_TEFL_Msk         (0x1UL << FDCAN_IR_TEFL_Pos)                 /*!< 0x00008000 */

+#define FDCAN_IR_TEFL             FDCAN_IR_TEFL_Msk                            /*!<Tx Event FIFO Element Lost               */

+#define FDCAN_IR_TSW_Pos          (16U)

+#define FDCAN_IR_TSW_Msk          (0x1UL << FDCAN_IR_TSW_Pos)                  /*!< 0x00010000 */

+#define FDCAN_IR_TSW              FDCAN_IR_TSW_Msk                             /*!<Timestamp Wraparound                     */

+#define FDCAN_IR_MRAF_Pos         (17U)

+#define FDCAN_IR_MRAF_Msk         (0x1UL << FDCAN_IR_MRAF_Pos)                 /*!< 0x00020000 */

+#define FDCAN_IR_MRAF             FDCAN_IR_MRAF_Msk                            /*!<Message RAM Access Failure               */

+#define FDCAN_IR_TOO_Pos          (18U)

+#define FDCAN_IR_TOO_Msk          (0x1UL << FDCAN_IR_TOO_Pos)                  /*!< 0x00040000 */

+#define FDCAN_IR_TOO              FDCAN_IR_TOO_Msk                             /*!<Timeout Occurred                         */

+#define FDCAN_IR_DRX_Pos          (19U)

+#define FDCAN_IR_DRX_Msk          (0x1UL << FDCAN_IR_DRX_Pos)                  /*!< 0x00080000 */

+#define FDCAN_IR_DRX              FDCAN_IR_DRX_Msk                             /*!<Message stored to Dedicated Rx Buffer    */

+#define FDCAN_IR_ELO_Pos          (22U)

+#define FDCAN_IR_ELO_Msk          (0x1UL << FDCAN_IR_ELO_Pos)                  /*!< 0x00400000 */

+#define FDCAN_IR_ELO              FDCAN_IR_ELO_Msk                             /*!<Error Logging Overflow                   */

+#define FDCAN_IR_EP_Pos           (23U)

+#define FDCAN_IR_EP_Msk           (0x1UL << FDCAN_IR_EP_Pos)                   /*!< 0x00800000 */

+#define FDCAN_IR_EP               FDCAN_IR_EP_Msk                              /*!<Error Passive                            */

+#define FDCAN_IR_EW_Pos           (24U)

+#define FDCAN_IR_EW_Msk           (0x1UL << FDCAN_IR_EW_Pos)                   /*!< 0x01000000 */

+#define FDCAN_IR_EW               FDCAN_IR_EW_Msk                              /*!<Warning Status                           */

+#define FDCAN_IR_BO_Pos           (25U)

+#define FDCAN_IR_BO_Msk           (0x1UL << FDCAN_IR_BO_Pos)                   /*!< 0x02000000 */

+#define FDCAN_IR_BO               FDCAN_IR_BO_Msk                              /*!<Bus_Off Status                           */

+#define FDCAN_IR_WDI_Pos          (26U)

+#define FDCAN_IR_WDI_Msk          (0x1UL << FDCAN_IR_WDI_Pos)                  /*!< 0x04000000 */

+#define FDCAN_IR_WDI              FDCAN_IR_WDI_Msk                             /*!<Watchdog Interrupt                       */

+#define FDCAN_IR_PEA_Pos          (27U)

+#define FDCAN_IR_PEA_Msk          (0x1UL << FDCAN_IR_PEA_Pos)                  /*!< 0x08000000 */

+#define FDCAN_IR_PEA              FDCAN_IR_PEA_Msk                             /*!<Protocol Error in Arbitration Phase      */

+#define FDCAN_IR_PED_Pos          (28U)

+#define FDCAN_IR_PED_Msk          (0x1UL << FDCAN_IR_PED_Pos)                  /*!< 0x10000000 */

+#define FDCAN_IR_PED              FDCAN_IR_PED_Msk                             /*!<Protocol Error in Data Phase             */

+#define FDCAN_IR_ARA_Pos          (29U)

+#define FDCAN_IR_ARA_Msk          (0x1UL << FDCAN_IR_ARA_Pos)                  /*!< 0x20000000 */

+#define FDCAN_IR_ARA              FDCAN_IR_ARA_Msk                             /*!<Access to Reserved Address               */

+

+/*****************  Bit definition for FDCAN_IE register  **********************/

+#define FDCAN_IE_RF0NE_Pos        (0U)

+#define FDCAN_IE_RF0NE_Msk        (0x1UL << FDCAN_IE_RF0NE_Pos)                /*!< 0x00000001 */

+#define FDCAN_IE_RF0NE            FDCAN_IE_RF0NE_Msk                           /*!<Rx FIFO 0 New Message Enable                 */

+#define FDCAN_IE_RF0WE_Pos        (1U)

+#define FDCAN_IE_RF0WE_Msk        (0x1UL << FDCAN_IE_RF0WE_Pos)                /*!< 0x00000002 */

+#define FDCAN_IE_RF0WE            FDCAN_IE_RF0WE_Msk                           /*!<Rx FIFO 0 Watermark Reached Enable           */

+#define FDCAN_IE_RF0FE_Pos        (2U)

+#define FDCAN_IE_RF0FE_Msk        (0x1UL << FDCAN_IE_RF0FE_Pos)                /*!< 0x00000004 */

+#define FDCAN_IE_RF0FE            FDCAN_IE_RF0FE_Msk                           /*!<Rx FIFO 0 Full Enable                        */

+#define FDCAN_IE_RF0LE_Pos        (3U)

+#define FDCAN_IE_RF0LE_Msk        (0x1UL << FDCAN_IE_RF0LE_Pos)                /*!< 0x00000008 */

+#define FDCAN_IE_RF0LE            FDCAN_IE_RF0LE_Msk                           /*!<Rx FIFO 0 Message Lost Enable                */

+#define FDCAN_IE_RF1NE_Pos        (4U)

+#define FDCAN_IE_RF1NE_Msk        (0x1UL << FDCAN_IE_RF1NE_Pos)                /*!< 0x00000010 */

+#define FDCAN_IE_RF1NE            FDCAN_IE_RF1NE_Msk                           /*!<Rx FIFO 1 New Message Enable                 */

+#define FDCAN_IE_RF1WE_Pos        (5U)

+#define FDCAN_IE_RF1WE_Msk        (0x1UL << FDCAN_IE_RF1WE_Pos)                /*!< 0x00000020 */

+#define FDCAN_IE_RF1WE            FDCAN_IE_RF1WE_Msk                           /*!<Rx FIFO 1 Watermark Reached Enable           */

+#define FDCAN_IE_RF1FE_Pos        (6U)

+#define FDCAN_IE_RF1FE_Msk        (0x1UL << FDCAN_IE_RF1FE_Pos)                /*!< 0x00000040 */

+#define FDCAN_IE_RF1FE            FDCAN_IE_RF1FE_Msk                           /*!<Rx FIFO 1 Full Enable                        */

+#define FDCAN_IE_RF1LE_Pos        (7U)

+#define FDCAN_IE_RF1LE_Msk        (0x1UL << FDCAN_IE_RF1LE_Pos)                /*!< 0x00000080 */

+#define FDCAN_IE_RF1LE            FDCAN_IE_RF1LE_Msk                           /*!<Rx FIFO 1 Message Lost Enable                */

+#define FDCAN_IE_HPME_Pos         (8U)

+#define FDCAN_IE_HPME_Msk         (0x1UL << FDCAN_IE_HPME_Pos)                 /*!< 0x00000100 */

+#define FDCAN_IE_HPME             FDCAN_IE_HPME_Msk                            /*!<High Priority Message Enable                 */

+#define FDCAN_IE_TCE_Pos          (9U)

+#define FDCAN_IE_TCE_Msk          (0x1UL << FDCAN_IE_TCE_Pos)                  /*!< 0x00000200 */

+#define FDCAN_IE_TCE              FDCAN_IE_TCE_Msk                             /*!<Transmission Completed Enable                */

+#define FDCAN_IE_TCFE_Pos         (10U)

+#define FDCAN_IE_TCFE_Msk         (0x1UL << FDCAN_IE_TCFE_Pos)                 /*!< 0x00000400 */

+#define FDCAN_IE_TCFE             FDCAN_IE_TCFE_Msk                            /*!<Transmission Cancellation Finished Enable    */

+#define FDCAN_IE_TFEE_Pos         (11U)

+#define FDCAN_IE_TFEE_Msk         (0x1UL << FDCAN_IE_TFEE_Pos)                 /*!< 0x00000800 */

+#define FDCAN_IE_TFEE             FDCAN_IE_TFEE_Msk                            /*!<Tx FIFO Empty Enable                         */

+#define FDCAN_IE_TEFNE_Pos        (12U)

+#define FDCAN_IE_TEFNE_Msk        (0x1UL << FDCAN_IE_TEFNE_Pos)                /*!< 0x00001000 */

+#define FDCAN_IE_TEFNE            FDCAN_IE_TEFNE_Msk                           /*!<Tx Event FIFO New Entry Enable               */

+#define FDCAN_IE_TEFWE_Pos        (13U)

+#define FDCAN_IE_TEFWE_Msk        (0x1UL << FDCAN_IE_TEFWE_Pos)                /*!< 0x00002000 */

+#define FDCAN_IE_TEFWE            FDCAN_IE_TEFWE_Msk                           /*!<Tx Event FIFO Watermark Reached Enable       */

+#define FDCAN_IE_TEFFE_Pos        (14U)

+#define FDCAN_IE_TEFFE_Msk        (0x1UL << FDCAN_IE_TEFFE_Pos)                /*!< 0x00004000 */

+#define FDCAN_IE_TEFFE            FDCAN_IE_TEFFE_Msk                           /*!<Tx Event FIFO Full Enable                    */

+#define FDCAN_IE_TEFLE_Pos        (15U)

+#define FDCAN_IE_TEFLE_Msk        (0x1UL << FDCAN_IE_TEFLE_Pos)                /*!< 0x00008000 */

+#define FDCAN_IE_TEFLE            FDCAN_IE_TEFLE_Msk                           /*!<Tx Event FIFO Element Lost Enable            */

+#define FDCAN_IE_TSWE_Pos         (16U)

+#define FDCAN_IE_TSWE_Msk         (0x1UL << FDCAN_IE_TSWE_Pos)                 /*!< 0x00010000 */

+#define FDCAN_IE_TSWE             FDCAN_IE_TSWE_Msk                            /*!<Timestamp Wraparound Enable                  */

+#define FDCAN_IE_MRAFE_Pos        (17U)

+#define FDCAN_IE_MRAFE_Msk        (0x1UL << FDCAN_IE_MRAFE_Pos)                /*!< 0x00020000 */

+#define FDCAN_IE_MRAFE            FDCAN_IE_MRAFE_Msk                           /*!<Message RAM Access Failure Enable            */

+#define FDCAN_IE_TOOE_Pos         (18U)

+#define FDCAN_IE_TOOE_Msk         (0x1UL << FDCAN_IE_TOOE_Pos)                 /*!< 0x00040000 */

+#define FDCAN_IE_TOOE             FDCAN_IE_TOOE_Msk                            /*!<Timeout Occurred Enable                      */

+#define FDCAN_IE_DRXE_Pos         (19U)

+#define FDCAN_IE_DRXE_Msk         (0x1UL << FDCAN_IE_DRXE_Pos)                 /*!< 0x00080000 */

+#define FDCAN_IE_DRXE             FDCAN_IE_DRXE_Msk                            /*!<Message stored to Dedicated Rx Buffer Enable */

+#define FDCAN_IE_BECE_Pos         (20U)

+#define FDCAN_IE_BECE_Msk         (0x1UL << FDCAN_IE_BECE_Pos)                 /*!< 0x00100000 */

+#define FDCAN_IE_BECE             FDCAN_IE_BECE_Msk                            /*!<Bit Error Corrected Interrupt Enable         */

+#define FDCAN_IE_BEUE_Pos         (21U)

+#define FDCAN_IE_BEUE_Msk         (0x1UL << FDCAN_IE_BEUE_Pos)                 /*!< 0x00200000 */

+#define FDCAN_IE_BEUE             FDCAN_IE_BEUE_Msk                            /*!<Bit Error Uncorrected Interrupt Enable       */

+#define FDCAN_IE_ELOE_Pos         (22U)

+#define FDCAN_IE_ELOE_Msk         (0x1UL << FDCAN_IE_ELOE_Pos)                 /*!< 0x00400000 */

+#define FDCAN_IE_ELOE             FDCAN_IE_ELOE_Msk                            /*!<Error Logging Overflow Enable                */

+#define FDCAN_IE_EPE_Pos          (23U)

+#define FDCAN_IE_EPE_Msk          (0x1UL << FDCAN_IE_EPE_Pos)                  /*!< 0x00800000 */

+#define FDCAN_IE_EPE              FDCAN_IE_EPE_Msk                             /*!<Error Passive Enable                         */

+#define FDCAN_IE_EWE_Pos          (24U)

+#define FDCAN_IE_EWE_Msk          (0x1UL << FDCAN_IE_EWE_Pos)                  /*!< 0x01000000 */

+#define FDCAN_IE_EWE              FDCAN_IE_EWE_Msk                             /*!<Warning Status Enable                        */

+#define FDCAN_IE_BOE_Pos          (25U)

+#define FDCAN_IE_BOE_Msk          (0x1UL << FDCAN_IE_BOE_Pos)                  /*!< 0x02000000 */

+#define FDCAN_IE_BOE              FDCAN_IE_BOE_Msk                             /*!<Bus_Off Status Enable                        */

+#define FDCAN_IE_WDIE_Pos         (26U)

+#define FDCAN_IE_WDIE_Msk         (0x1UL << FDCAN_IE_WDIE_Pos)                 /*!< 0x04000000 */

+#define FDCAN_IE_WDIE             FDCAN_IE_WDIE_Msk                            /*!<Watchdog Interrupt Enable                    */

+#define FDCAN_IE_PEAE_Pos         (27U)

+#define FDCAN_IE_PEAE_Msk         (0x1UL << FDCAN_IE_PEAE_Pos)                 /*!< 0x08000000 */

+#define FDCAN_IE_PEAE             FDCAN_IE_PEAE_Msk                            /*!<Protocol Error in Arbitration Phase Enable   */

+#define FDCAN_IE_PEDE_Pos         (28U)

+#define FDCAN_IE_PEDE_Msk         (0x1UL << FDCAN_IE_PEDE_Pos)                 /*!< 0x10000000 */

+#define FDCAN_IE_PEDE             FDCAN_IE_PEDE_Msk                            /*!<Protocol Error in Data Phase Enable          */

+#define FDCAN_IE_ARAE_Pos         (29U)

+#define FDCAN_IE_ARAE_Msk         (0x1UL << FDCAN_IE_ARAE_Pos)                 /*!< 0x20000000 */

+#define FDCAN_IE_ARAE             FDCAN_IE_ARAE_Msk                            /*!<Access to Reserved Address Enable            */

+

+/*****************  Bit definition for FDCAN_ILS register  **********************/

+#define FDCAN_ILS_RF0NL_Pos       (0U)

+#define FDCAN_ILS_RF0NL_Msk       (0x1UL << FDCAN_ILS_RF0NL_Pos)               /*!< 0x00000001 */

+#define FDCAN_ILS_RF0NL           FDCAN_ILS_RF0NL_Msk                          /*!<Rx FIFO 0 New Message Line                  */

+#define FDCAN_ILS_RF0WL_Pos       (1U)

+#define FDCAN_ILS_RF0WL_Msk       (0x1UL << FDCAN_ILS_RF0WL_Pos)               /*!< 0x00000002 */

+#define FDCAN_ILS_RF0WL           FDCAN_ILS_RF0WL_Msk                          /*!<Rx FIFO 0 Watermark Reached Line            */

+#define FDCAN_ILS_RF0FL_Pos       (2U)

+#define FDCAN_ILS_RF0FL_Msk       (0x1UL << FDCAN_ILS_RF0FL_Pos)               /*!< 0x00000004 */

+#define FDCAN_ILS_RF0FL           FDCAN_ILS_RF0FL_Msk                          /*!<Rx FIFO 0 Full Line                         */

+#define FDCAN_ILS_RF0LL_Pos       (3U)

+#define FDCAN_ILS_RF0LL_Msk       (0x1UL << FDCAN_ILS_RF0LL_Pos)               /*!< 0x00000008 */

+#define FDCAN_ILS_RF0LL           FDCAN_ILS_RF0LL_Msk                          /*!<Rx FIFO 0 Message Lost Line                 */

+#define FDCAN_ILS_RF1NL_Pos       (4U)

+#define FDCAN_ILS_RF1NL_Msk       (0x1UL << FDCAN_ILS_RF1NL_Pos)               /*!< 0x00000010 */

+#define FDCAN_ILS_RF1NL           FDCAN_ILS_RF1NL_Msk                          /*!<Rx FIFO 1 New Message Line                  */

+#define FDCAN_ILS_RF1WL_Pos       (5U)

+#define FDCAN_ILS_RF1WL_Msk       (0x1UL << FDCAN_ILS_RF1WL_Pos)               /*!< 0x00000020 */

+#define FDCAN_ILS_RF1WL           FDCAN_ILS_RF1WL_Msk                          /*!<Rx FIFO 1 Watermark Reached Line            */

+#define FDCAN_ILS_RF1FL_Pos       (6U)

+#define FDCAN_ILS_RF1FL_Msk       (0x1UL << FDCAN_ILS_RF1FL_Pos)               /*!< 0x00000040 */

+#define FDCAN_ILS_RF1FL           FDCAN_ILS_RF1FL_Msk                          /*!<Rx FIFO 1 Full Line                         */

+#define FDCAN_ILS_RF1LL_Pos       (7U)

+#define FDCAN_ILS_RF1LL_Msk       (0x1UL << FDCAN_ILS_RF1LL_Pos)               /*!< 0x00000080 */

+#define FDCAN_ILS_RF1LL           FDCAN_ILS_RF1LL_Msk                          /*!<Rx FIFO 1 Message Lost Line                 */

+#define FDCAN_ILS_HPML_Pos        (8U)

+#define FDCAN_ILS_HPML_Msk        (0x1UL << FDCAN_ILS_HPML_Pos)                /*!< 0x00000100 */

+#define FDCAN_ILS_HPML            FDCAN_ILS_HPML_Msk                           /*!<High Priority Message Line                  */

+#define FDCAN_ILS_TCL_Pos         (9U)

+#define FDCAN_ILS_TCL_Msk         (0x1UL << FDCAN_ILS_TCL_Pos)                 /*!< 0x00000200 */

+#define FDCAN_ILS_TCL             FDCAN_ILS_TCL_Msk                            /*!<Transmission Completed Line                 */

+#define FDCAN_ILS_TCFL_Pos        (10U)

+#define FDCAN_ILS_TCFL_Msk        (0x1UL << FDCAN_ILS_TCFL_Pos)                /*!< 0x00000400 */

+#define FDCAN_ILS_TCFL            FDCAN_ILS_TCFL_Msk                           /*!<Transmission Cancellation Finished Line     */

+#define FDCAN_ILS_TFEL_Pos        (11U)

+#define FDCAN_ILS_TFEL_Msk        (0x1UL << FDCAN_ILS_TFEL_Pos)                /*!< 0x00000800 */

+#define FDCAN_ILS_TFEL            FDCAN_ILS_TFEL_Msk                           /*!<Tx FIFO Empty Line                          */

+#define FDCAN_ILS_TEFNL_Pos       (12U)

+#define FDCAN_ILS_TEFNL_Msk       (0x1UL << FDCAN_ILS_TEFNL_Pos)               /*!< 0x00001000 */

+#define FDCAN_ILS_TEFNL           FDCAN_ILS_TEFNL_Msk                          /*!<Tx Event FIFO New Entry Line                */

+#define FDCAN_ILS_TEFWL_Pos       (13U)

+#define FDCAN_ILS_TEFWL_Msk       (0x1UL << FDCAN_ILS_TEFWL_Pos)               /*!< 0x00002000 */

+#define FDCAN_ILS_TEFWL           FDCAN_ILS_TEFWL_Msk                          /*!<Tx Event FIFO Watermark Reached Line        */

+#define FDCAN_ILS_TEFFL_Pos       (14U)

+#define FDCAN_ILS_TEFFL_Msk       (0x1UL << FDCAN_ILS_TEFFL_Pos)               /*!< 0x00004000 */

+#define FDCAN_ILS_TEFFL           FDCAN_ILS_TEFFL_Msk                          /*!<Tx Event FIFO Full Line                     */

+#define FDCAN_ILS_TEFLL_Pos       (15U)

+#define FDCAN_ILS_TEFLL_Msk       (0x1UL << FDCAN_ILS_TEFLL_Pos)               /*!< 0x00008000 */

+#define FDCAN_ILS_TEFLL           FDCAN_ILS_TEFLL_Msk                          /*!<Tx Event FIFO Element Lost Line             */

+#define FDCAN_ILS_TSWL_Pos        (16U)

+#define FDCAN_ILS_TSWL_Msk        (0x1UL << FDCAN_ILS_TSWL_Pos)                /*!< 0x00010000 */

+#define FDCAN_ILS_TSWL            FDCAN_ILS_TSWL_Msk                           /*!<Timestamp Wraparound Line                   */

+#define FDCAN_ILS_MRAFE_Pos       (17U)

+#define FDCAN_ILS_MRAFE_Msk       (0x1UL << FDCAN_ILS_MRAFE_Pos)               /*!< 0x00020000 */

+#define FDCAN_ILS_MRAFE           FDCAN_ILS_MRAFE_Msk                          /*!<Message RAM Access Failure Line             */

+#define FDCAN_ILS_TOOE_Pos        (18U)

+#define FDCAN_ILS_TOOE_Msk        (0x1UL << FDCAN_ILS_TOOE_Pos)                /*!< 0x00040000 */

+#define FDCAN_ILS_TOOE            FDCAN_ILS_TOOE_Msk                           /*!<Timeout Occurred Line                       */

+#define FDCAN_ILS_DRXE_Pos        (19U)

+#define FDCAN_ILS_DRXE_Msk        (0x1UL << FDCAN_ILS_DRXE_Pos)                /*!< 0x00080000 */

+#define FDCAN_ILS_DRXE            FDCAN_ILS_DRXE_Msk                           /*!<Message stored to Dedicated Rx Buffer Line  */

+#define FDCAN_ILS_BECE_Pos        (20U)

+#define FDCAN_ILS_BECE_Msk        (0x1UL << FDCAN_ILS_BECE_Pos)                /*!< 0x00100000 */

+#define FDCAN_ILS_BECE            FDCAN_ILS_BECE_Msk                           /*!<Bit Error Corrected Interrupt Line          */

+#define FDCAN_ILS_BEUE_Pos        (21U)

+#define FDCAN_ILS_BEUE_Msk        (0x1UL << FDCAN_ILS_BEUE_Pos)                /*!< 0x00200000 */

+#define FDCAN_ILS_BEUE            FDCAN_ILS_BEUE_Msk                           /*!<Bit Error Uncorrected Interrupt Line        */

+#define FDCAN_ILS_ELOE_Pos        (22U)

+#define FDCAN_ILS_ELOE_Msk        (0x1UL << FDCAN_ILS_ELOE_Pos)                /*!< 0x00400000 */

+#define FDCAN_ILS_ELOE            FDCAN_ILS_ELOE_Msk                           /*!<Error Logging Overflow Line                 */

+#define FDCAN_ILS_EPE_Pos         (23U)

+#define FDCAN_ILS_EPE_Msk         (0x1UL << FDCAN_ILS_EPE_Pos)                 /*!< 0x00800000 */

+#define FDCAN_ILS_EPE             FDCAN_ILS_EPE_Msk                            /*!<Error Passive Line                          */

+#define FDCAN_ILS_EWE_Pos         (24U)

+#define FDCAN_ILS_EWE_Msk         (0x1UL << FDCAN_ILS_EWE_Pos)                 /*!< 0x01000000 */

+#define FDCAN_ILS_EWE             FDCAN_ILS_EWE_Msk                            /*!<Warning Status Line                         */

+#define FDCAN_ILS_BOE_Pos         (25U)

+#define FDCAN_ILS_BOE_Msk         (0x1UL << FDCAN_ILS_BOE_Pos)                 /*!< 0x02000000 */

+#define FDCAN_ILS_BOE             FDCAN_ILS_BOE_Msk                            /*!<Bus_Off Status Line                         */

+#define FDCAN_ILS_WDIE_Pos        (26U)

+#define FDCAN_ILS_WDIE_Msk        (0x1UL << FDCAN_ILS_WDIE_Pos)                /*!< 0x04000000 */

+#define FDCAN_ILS_WDIE            FDCAN_ILS_WDIE_Msk                           /*!<Watchdog Interrupt Line                     */

+#define FDCAN_ILS_PEAE_Pos        (27U)

+#define FDCAN_ILS_PEAE_Msk        (0x1UL << FDCAN_ILS_PEAE_Pos)                /*!< 0x08000000 */

+#define FDCAN_ILS_PEAE            FDCAN_ILS_PEAE_Msk                           /*!<Protocol Error in Arbitration Phase Line    */

+#define FDCAN_ILS_PEDE_Pos        (28U)

+#define FDCAN_ILS_PEDE_Msk        (0x1UL << FDCAN_ILS_PEDE_Pos)                /*!< 0x10000000 */

+#define FDCAN_ILS_PEDE            FDCAN_ILS_PEDE_Msk                           /*!<Protocol Error in Data Phase Line           */

+#define FDCAN_ILS_ARAE_Pos        (29U)

+#define FDCAN_ILS_ARAE_Msk        (0x1UL << FDCAN_ILS_ARAE_Pos)                /*!< 0x20000000 */

+#define FDCAN_ILS_ARAE            FDCAN_ILS_ARAE_Msk                           /*!<Access to Reserved Address Line             */

+

+/*****************  Bit definition for FDCAN_ILE register  **********************/

+#define FDCAN_ILE_EINT0_Pos       (0U)

+#define FDCAN_ILE_EINT0_Msk       (0x1UL << FDCAN_ILE_EINT0_Pos)               /*!< 0x00000001 */

+#define FDCAN_ILE_EINT0           FDCAN_ILE_EINT0_Msk                          /*!<Enable Interrupt Line 0                   */

+#define FDCAN_ILE_EINT1_Pos       (1U)

+#define FDCAN_ILE_EINT1_Msk       (0x1UL << FDCAN_ILE_EINT1_Pos)               /*!< 0x00000002 */

+#define FDCAN_ILE_EINT1           FDCAN_ILE_EINT1_Msk                          /*!<Enable Interrupt Line 1                   */

+

+/*****************  Bit definition for FDCAN_GFC register  **********************/

+#define FDCAN_GFC_RRFE_Pos        (0U)

+#define FDCAN_GFC_RRFE_Msk        (0x1UL << FDCAN_GFC_RRFE_Pos)                /*!< 0x00000001 */

+#define FDCAN_GFC_RRFE            FDCAN_GFC_RRFE_Msk                           /*!<Reject Remote Frames Extended             */

+#define FDCAN_GFC_RRFS_Pos        (1U)

+#define FDCAN_GFC_RRFS_Msk        (0x1UL << FDCAN_GFC_RRFS_Pos)                /*!< 0x00000002 */

+#define FDCAN_GFC_RRFS            FDCAN_GFC_RRFS_Msk                           /*!<Reject Remote Frames Standard             */

+#define FDCAN_GFC_ANFE_Pos        (2U)

+#define FDCAN_GFC_ANFE_Msk        (0x3UL << FDCAN_GFC_ANFE_Pos)                /*!< 0x0000000C */

+#define FDCAN_GFC_ANFE            FDCAN_GFC_ANFE_Msk                           /*!<Accept Non-matching Frames Extended       */

+#define FDCAN_GFC_ANFS_Pos        (4U)

+#define FDCAN_GFC_ANFS_Msk        (0x3UL << FDCAN_GFC_ANFS_Pos)                /*!< 0x00000030 */

+#define FDCAN_GFC_ANFS            FDCAN_GFC_ANFS_Msk                           /*!<Accept Non-matching Frames Standard       */

+

+/*****************  Bit definition for FDCAN_SIDFC register  ********************/

+#define FDCAN_SIDFC_FLSSA_Pos     (2U)

+#define FDCAN_SIDFC_FLSSA_Msk     (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)          /*!< 0x0000FFFC */

+#define FDCAN_SIDFC_FLSSA         FDCAN_SIDFC_FLSSA_Msk                        /*!<Filter List Standard Start Address        */

+#define FDCAN_SIDFC_LSS_Pos       (16U)

+#define FDCAN_SIDFC_LSS_Msk       (0xFFUL << FDCAN_SIDFC_LSS_Pos)              /*!< 0x00FF0000 */

+#define FDCAN_SIDFC_LSS           FDCAN_SIDFC_LSS_Msk                          /*!<List Size Standard                        */

+

+/*****************  Bit definition for FDCAN_XIDFC register  ********************/

+#define FDCAN_XIDFC_FLESA_Pos     (2U)

+#define FDCAN_XIDFC_FLESA_Msk     (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)          /*!< 0x0000FFFC */

+#define FDCAN_XIDFC_FLESA         FDCAN_XIDFC_FLESA_Msk                        /*!<Filter List Standard Start Address        */

+#define FDCAN_XIDFC_LSE_Pos       (16U)

+#define FDCAN_XIDFC_LSE_Msk       (0x7FUL << FDCAN_XIDFC_LSE_Pos)              /*!< 0x007F0000 */

+#define FDCAN_XIDFC_LSE           FDCAN_XIDFC_LSE_Msk                          /*!<List Size Extended                        */

+

+/*****************  Bit definition for FDCAN_XIDAM register  ********************/

+#define FDCAN_XIDAM_EIDM_Pos      (0U)

+#define FDCAN_XIDAM_EIDM_Msk      (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)       /*!< 0x1FFFFFFF */

+#define FDCAN_XIDAM_EIDM          FDCAN_XIDAM_EIDM_Msk                         /*!<Extended ID Mask                          */

+

+/*****************  Bit definition for FDCAN_HPMS register  *********************/

+#define FDCAN_HPMS_BIDX_Pos       (0U)

+#define FDCAN_HPMS_BIDX_Msk       (0x3FUL << FDCAN_HPMS_BIDX_Pos)              /*!< 0x0000003F */

+#define FDCAN_HPMS_BIDX           FDCAN_HPMS_BIDX_Msk                          /*!<Buffer Index                              */

+#define FDCAN_HPMS_MSI_Pos        (6U)

+#define FDCAN_HPMS_MSI_Msk        (0x3UL << FDCAN_HPMS_MSI_Pos)                /*!< 0x000000C0 */

+#define FDCAN_HPMS_MSI            FDCAN_HPMS_MSI_Msk                           /*!<Message Storage Indicator                 */

+#define FDCAN_HPMS_FIDX_Pos       (8U)

+#define FDCAN_HPMS_FIDX_Msk       (0x7FUL << FDCAN_HPMS_FIDX_Pos)              /*!< 0x00007F00 */

+#define FDCAN_HPMS_FIDX           FDCAN_HPMS_FIDX_Msk                          /*!<Filter Index                              */

+#define FDCAN_HPMS_FLST_Pos       (15U)

+#define FDCAN_HPMS_FLST_Msk       (0x1UL << FDCAN_HPMS_FLST_Pos)               /*!< 0x00008000 */

+#define FDCAN_HPMS_FLST           FDCAN_HPMS_FLST_Msk                          /*!<Filter List                               */

+

+/*****************  Bit definition for FDCAN_NDAT1 register  ********************/

+#define FDCAN_NDAT1_ND0_Pos       (0U)

+#define FDCAN_NDAT1_ND0_Msk       (0x1UL << FDCAN_NDAT1_ND0_Pos)               /*!< 0x00000001 */

+#define FDCAN_NDAT1_ND0           FDCAN_NDAT1_ND0_Msk                          /*!<New Data flag of Rx Buffer 0              */

+#define FDCAN_NDAT1_ND1_Pos       (1U)

+#define FDCAN_NDAT1_ND1_Msk       (0x1UL << FDCAN_NDAT1_ND1_Pos)               /*!< 0x00000002 */

+#define FDCAN_NDAT1_ND1           FDCAN_NDAT1_ND1_Msk                          /*!<New Data flag of Rx Buffer 1              */

+#define FDCAN_NDAT1_ND2_Pos       (2U)

+#define FDCAN_NDAT1_ND2_Msk       (0x1UL << FDCAN_NDAT1_ND2_Pos)               /*!< 0x00000004 */

+#define FDCAN_NDAT1_ND2           FDCAN_NDAT1_ND2_Msk                          /*!<New Data flag of Rx Buffer 2              */

+#define FDCAN_NDAT1_ND3_Pos       (3U)

+#define FDCAN_NDAT1_ND3_Msk       (0x1UL << FDCAN_NDAT1_ND3_Pos)               /*!< 0x00000008 */

+#define FDCAN_NDAT1_ND3           FDCAN_NDAT1_ND3_Msk                          /*!<New Data flag of Rx Buffer 3              */

+#define FDCAN_NDAT1_ND4_Pos       (4U)

+#define FDCAN_NDAT1_ND4_Msk       (0x1UL << FDCAN_NDAT1_ND4_Pos)               /*!< 0x00000010 */

+#define FDCAN_NDAT1_ND4           FDCAN_NDAT1_ND4_Msk                          /*!<New Data flag of Rx Buffer 4              */

+#define FDCAN_NDAT1_ND5_Pos       (5U)

+#define FDCAN_NDAT1_ND5_Msk       (0x1UL << FDCAN_NDAT1_ND5_Pos)               /*!< 0x00000020 */

+#define FDCAN_NDAT1_ND5           FDCAN_NDAT1_ND5_Msk                          /*!<New Data flag of Rx Buffer 5              */

+#define FDCAN_NDAT1_ND6_Pos       (6U)

+#define FDCAN_NDAT1_ND6_Msk       (0x1UL << FDCAN_NDAT1_ND6_Pos)               /*!< 0x00000040 */

+#define FDCAN_NDAT1_ND6           FDCAN_NDAT1_ND6_Msk                          /*!<New Data flag of Rx Buffer 6              */

+#define FDCAN_NDAT1_ND7_Pos       (7U)

+#define FDCAN_NDAT1_ND7_Msk       (0x1UL << FDCAN_NDAT1_ND7_Pos)               /*!< 0x00000080 */

+#define FDCAN_NDAT1_ND7           FDCAN_NDAT1_ND7_Msk                          /*!<New Data flag of Rx Buffer 7              */

+#define FDCAN_NDAT1_ND8_Pos       (8U)

+#define FDCAN_NDAT1_ND8_Msk       (0x1UL << FDCAN_NDAT1_ND8_Pos)               /*!< 0x00000100 */

+#define FDCAN_NDAT1_ND8           FDCAN_NDAT1_ND8_Msk                          /*!<New Data flag of Rx Buffer 8              */

+#define FDCAN_NDAT1_ND9_Pos       (9U)

+#define FDCAN_NDAT1_ND9_Msk       (0x1UL << FDCAN_NDAT1_ND9_Pos)               /*!< 0x00000200 */

+#define FDCAN_NDAT1_ND9           FDCAN_NDAT1_ND9_Msk                          /*!<New Data flag of Rx Buffer 9              */

+#define FDCAN_NDAT1_ND10_Pos      (10U)

+#define FDCAN_NDAT1_ND10_Msk      (0x1UL << FDCAN_NDAT1_ND10_Pos)              /*!< 0x00000400 */

+#define FDCAN_NDAT1_ND10          FDCAN_NDAT1_ND10_Msk                         /*!<New Data flag of Rx Buffer 10             */

+#define FDCAN_NDAT1_ND11_Pos      (11U)

+#define FDCAN_NDAT1_ND11_Msk      (0x1UL << FDCAN_NDAT1_ND11_Pos)              /*!< 0x00000800 */

+#define FDCAN_NDAT1_ND11          FDCAN_NDAT1_ND11_Msk                         /*!<New Data flag of Rx Buffer 11             */

+#define FDCAN_NDAT1_ND12_Pos      (12U)

+#define FDCAN_NDAT1_ND12_Msk      (0x1UL << FDCAN_NDAT1_ND12_Pos)              /*!< 0x00001000 */

+#define FDCAN_NDAT1_ND12          FDCAN_NDAT1_ND12_Msk                         /*!<New Data flag of Rx Buffer 12             */

+#define FDCAN_NDAT1_ND13_Pos      (13U)

+#define FDCAN_NDAT1_ND13_Msk      (0x1UL << FDCAN_NDAT1_ND13_Pos)              /*!< 0x00002000 */

+#define FDCAN_NDAT1_ND13          FDCAN_NDAT1_ND13_Msk                         /*!<New Data flag of Rx Buffer 13             */

+#define FDCAN_NDAT1_ND14_Pos      (14U)

+#define FDCAN_NDAT1_ND14_Msk      (0x1UL << FDCAN_NDAT1_ND14_Pos)              /*!< 0x00004000 */

+#define FDCAN_NDAT1_ND14          FDCAN_NDAT1_ND14_Msk                         /*!<New Data flag of Rx Buffer 14             */

+#define FDCAN_NDAT1_ND15_Pos      (15U)

+#define FDCAN_NDAT1_ND15_Msk      (0x1UL << FDCAN_NDAT1_ND15_Pos)              /*!< 0x00008000 */

+#define FDCAN_NDAT1_ND15          FDCAN_NDAT1_ND15_Msk                         /*!<New Data flag of Rx Buffer 15             */

+#define FDCAN_NDAT1_ND16_Pos      (16U)

+#define FDCAN_NDAT1_ND16_Msk      (0x1UL << FDCAN_NDAT1_ND16_Pos)              /*!< 0x00010000 */

+#define FDCAN_NDAT1_ND16          FDCAN_NDAT1_ND16_Msk                         /*!<New Data flag of Rx Buffer 16             */

+#define FDCAN_NDAT1_ND17_Pos      (17U)

+#define FDCAN_NDAT1_ND17_Msk      (0x1UL << FDCAN_NDAT1_ND17_Pos)              /*!< 0x00020000 */

+#define FDCAN_NDAT1_ND17          FDCAN_NDAT1_ND17_Msk                         /*!<New Data flag of Rx Buffer 17             */

+#define FDCAN_NDAT1_ND18_Pos      (18U)

+#define FDCAN_NDAT1_ND18_Msk      (0x1UL << FDCAN_NDAT1_ND18_Pos)              /*!< 0x00040000 */

+#define FDCAN_NDAT1_ND18          FDCAN_NDAT1_ND18_Msk                         /*!<New Data flag of Rx Buffer 18             */

+#define FDCAN_NDAT1_ND19_Pos      (19U)

+#define FDCAN_NDAT1_ND19_Msk      (0x1UL << FDCAN_NDAT1_ND19_Pos)              /*!< 0x00080000 */

+#define FDCAN_NDAT1_ND19          FDCAN_NDAT1_ND19_Msk                         /*!<New Data flag of Rx Buffer 19             */

+#define FDCAN_NDAT1_ND20_Pos      (20U)

+#define FDCAN_NDAT1_ND20_Msk      (0x1UL << FDCAN_NDAT1_ND20_Pos)              /*!< 0x00100000 */

+#define FDCAN_NDAT1_ND20          FDCAN_NDAT1_ND20_Msk                         /*!<New Data flag of Rx Buffer 20             */

+#define FDCAN_NDAT1_ND21_Pos      (21U)

+#define FDCAN_NDAT1_ND21_Msk      (0x1UL << FDCAN_NDAT1_ND21_Pos)              /*!< 0x00200000 */

+#define FDCAN_NDAT1_ND21          FDCAN_NDAT1_ND21_Msk                         /*!<New Data flag of Rx Buffer 21             */

+#define FDCAN_NDAT1_ND22_Pos      (22U)

+#define FDCAN_NDAT1_ND22_Msk      (0x1UL << FDCAN_NDAT1_ND22_Pos)              /*!< 0x00400000 */

+#define FDCAN_NDAT1_ND22          FDCAN_NDAT1_ND22_Msk                         /*!<New Data flag of Rx Buffer 22             */

+#define FDCAN_NDAT1_ND23_Pos      (23U)

+#define FDCAN_NDAT1_ND23_Msk      (0x1UL << FDCAN_NDAT1_ND23_Pos)              /*!< 0x00800000 */

+#define FDCAN_NDAT1_ND23          FDCAN_NDAT1_ND23_Msk                         /*!<New Data flag of Rx Buffer 23             */

+#define FDCAN_NDAT1_ND24_Pos      (24U)

+#define FDCAN_NDAT1_ND24_Msk      (0x1UL << FDCAN_NDAT1_ND24_Pos)              /*!< 0x01000000 */

+#define FDCAN_NDAT1_ND24          FDCAN_NDAT1_ND24_Msk                         /*!<New Data flag of Rx Buffer 24             */

+#define FDCAN_NDAT1_ND25_Pos      (25U)

+#define FDCAN_NDAT1_ND25_Msk      (0x1UL << FDCAN_NDAT1_ND25_Pos)              /*!< 0x02000000 */

+#define FDCAN_NDAT1_ND25          FDCAN_NDAT1_ND25_Msk                         /*!<New Data flag of Rx Buffer 25             */

+#define FDCAN_NDAT1_ND26_Pos      (26U)

+#define FDCAN_NDAT1_ND26_Msk      (0x1UL << FDCAN_NDAT1_ND26_Pos)              /*!< 0x04000000 */

+#define FDCAN_NDAT1_ND26          FDCAN_NDAT1_ND26_Msk                         /*!<New Data flag of Rx Buffer 26             */

+#define FDCAN_NDAT1_ND27_Pos      (27U)

+#define FDCAN_NDAT1_ND27_Msk      (0x1UL << FDCAN_NDAT1_ND27_Pos)              /*!< 0x08000000 */

+#define FDCAN_NDAT1_ND27          FDCAN_NDAT1_ND27_Msk                         /*!<New Data flag of Rx Buffer 27             */

+#define FDCAN_NDAT1_ND28_Pos      (28U)

+#define FDCAN_NDAT1_ND28_Msk      (0x1UL << FDCAN_NDAT1_ND28_Pos)              /*!< 0x10000000 */

+#define FDCAN_NDAT1_ND28          FDCAN_NDAT1_ND28_Msk                         /*!<New Data flag of Rx Buffer 28             */

+#define FDCAN_NDAT1_ND29_Pos      (29U)

+#define FDCAN_NDAT1_ND29_Msk      (0x1UL << FDCAN_NDAT1_ND29_Pos)              /*!< 0x20000000 */

+#define FDCAN_NDAT1_ND29          FDCAN_NDAT1_ND29_Msk                         /*!<New Data flag of Rx Buffer 29             */

+#define FDCAN_NDAT1_ND30_Pos      (30U)

+#define FDCAN_NDAT1_ND30_Msk      (0x1UL << FDCAN_NDAT1_ND30_Pos)              /*!< 0x40000000 */

+#define FDCAN_NDAT1_ND30          FDCAN_NDAT1_ND30_Msk                         /*!<New Data flag of Rx Buffer 30             */

+#define FDCAN_NDAT1_ND31_Pos      (31U)

+#define FDCAN_NDAT1_ND31_Msk      (0x1UL << FDCAN_NDAT1_ND31_Pos)              /*!< 0x80000000 */

+#define FDCAN_NDAT1_ND31          FDCAN_NDAT1_ND31_Msk                         /*!<New Data flag of Rx Buffer 31             */

+

+/*****************  Bit definition for FDCAN_NDAT2 register  ********************/

+#define FDCAN_NDAT2_ND32_Pos      (0U)

+#define FDCAN_NDAT2_ND32_Msk      (0x1UL << FDCAN_NDAT2_ND32_Pos)              /*!< 0x00000001 */

+#define FDCAN_NDAT2_ND32          FDCAN_NDAT2_ND32_Msk                         /*!<New Data flag of Rx Buffer 32             */

+#define FDCAN_NDAT2_ND33_Pos      (1U)

+#define FDCAN_NDAT2_ND33_Msk      (0x1UL << FDCAN_NDAT2_ND33_Pos)              /*!< 0x00000002 */

+#define FDCAN_NDAT2_ND33          FDCAN_NDAT2_ND33_Msk                         /*!<New Data flag of Rx Buffer 33             */

+#define FDCAN_NDAT2_ND34_Pos      (2U)

+#define FDCAN_NDAT2_ND34_Msk      (0x1UL << FDCAN_NDAT2_ND34_Pos)              /*!< 0x00000004 */

+#define FDCAN_NDAT2_ND34          FDCAN_NDAT2_ND34_Msk                         /*!<New Data flag of Rx Buffer 34             */

+#define FDCAN_NDAT2_ND35_Pos      (3U)

+#define FDCAN_NDAT2_ND35_Msk      (0x1UL << FDCAN_NDAT2_ND35_Pos)              /*!< 0x00000008 */

+#define FDCAN_NDAT2_ND35          FDCAN_NDAT2_ND35_Msk                         /*!<New Data flag of Rx Buffer 35             */

+#define FDCAN_NDAT2_ND36_Pos      (4U)

+#define FDCAN_NDAT2_ND36_Msk      (0x1UL << FDCAN_NDAT2_ND36_Pos)              /*!< 0x00000010 */

+#define FDCAN_NDAT2_ND36          FDCAN_NDAT2_ND36_Msk                         /*!<New Data flag of Rx Buffer 36             */

+#define FDCAN_NDAT2_ND37_Pos      (5U)

+#define FDCAN_NDAT2_ND37_Msk      (0x1UL << FDCAN_NDAT2_ND37_Pos)              /*!< 0x00000020 */

+#define FDCAN_NDAT2_ND37          FDCAN_NDAT2_ND37_Msk                         /*!<New Data flag of Rx Buffer 37             */

+#define FDCAN_NDAT2_ND38_Pos      (6U)

+#define FDCAN_NDAT2_ND38_Msk      (0x1UL << FDCAN_NDAT2_ND38_Pos)              /*!< 0x00000040 */

+#define FDCAN_NDAT2_ND38          FDCAN_NDAT2_ND38_Msk                         /*!<New Data flag of Rx Buffer 38             */

+#define FDCAN_NDAT2_ND39_Pos      (7U)

+#define FDCAN_NDAT2_ND39_Msk      (0x1UL << FDCAN_NDAT2_ND39_Pos)              /*!< 0x00000080 */

+#define FDCAN_NDAT2_ND39          FDCAN_NDAT2_ND39_Msk                         /*!<New Data flag of Rx Buffer 39             */

+#define FDCAN_NDAT2_ND40_Pos      (8U)

+#define FDCAN_NDAT2_ND40_Msk      (0x1UL << FDCAN_NDAT2_ND40_Pos)              /*!< 0x00000100 */

+#define FDCAN_NDAT2_ND40          FDCAN_NDAT2_ND40_Msk                         /*!<New Data flag of Rx Buffer 40             */

+#define FDCAN_NDAT2_ND41_Pos      (9U)

+#define FDCAN_NDAT2_ND41_Msk      (0x1UL << FDCAN_NDAT2_ND41_Pos)              /*!< 0x00000200 */

+#define FDCAN_NDAT2_ND41          FDCAN_NDAT2_ND41_Msk                         /*!<New Data flag of Rx Buffer 41             */

+#define FDCAN_NDAT2_ND42_Pos      (10U)

+#define FDCAN_NDAT2_ND42_Msk      (0x1UL << FDCAN_NDAT2_ND42_Pos)              /*!< 0x00000400 */

+#define FDCAN_NDAT2_ND42          FDCAN_NDAT2_ND42_Msk                         /*!<New Data flag of Rx Buffer 42             */

+#define FDCAN_NDAT2_ND43_Pos      (11U)

+#define FDCAN_NDAT2_ND43_Msk      (0x1UL << FDCAN_NDAT2_ND43_Pos)              /*!< 0x00000800 */

+#define FDCAN_NDAT2_ND43          FDCAN_NDAT2_ND43_Msk                         /*!<New Data flag of Rx Buffer 43             */

+#define FDCAN_NDAT2_ND44_Pos      (12U)

+#define FDCAN_NDAT2_ND44_Msk      (0x1UL << FDCAN_NDAT2_ND44_Pos)              /*!< 0x00001000 */

+#define FDCAN_NDAT2_ND44          FDCAN_NDAT2_ND44_Msk                         /*!<New Data flag of Rx Buffer 44             */

+#define FDCAN_NDAT2_ND45_Pos      (13U)

+#define FDCAN_NDAT2_ND45_Msk      (0x1UL << FDCAN_NDAT2_ND45_Pos)              /*!< 0x00002000 */

+#define FDCAN_NDAT2_ND45          FDCAN_NDAT2_ND45_Msk                         /*!<New Data flag of Rx Buffer 45             */

+#define FDCAN_NDAT2_ND46_Pos      (14U)

+#define FDCAN_NDAT2_ND46_Msk      (0x1UL << FDCAN_NDAT2_ND46_Pos)              /*!< 0x00004000 */

+#define FDCAN_NDAT2_ND46          FDCAN_NDAT2_ND46_Msk                         /*!<New Data flag of Rx Buffer 46             */

+#define FDCAN_NDAT2_ND47_Pos      (15U)

+#define FDCAN_NDAT2_ND47_Msk      (0x1UL << FDCAN_NDAT2_ND47_Pos)              /*!< 0x00008000 */

+#define FDCAN_NDAT2_ND47          FDCAN_NDAT2_ND47_Msk                         /*!<New Data flag of Rx Buffer 47             */

+#define FDCAN_NDAT2_ND48_Pos      (16U)

+#define FDCAN_NDAT2_ND48_Msk      (0x1UL << FDCAN_NDAT2_ND48_Pos)              /*!< 0x00010000 */

+#define FDCAN_NDAT2_ND48          FDCAN_NDAT2_ND48_Msk                         /*!<New Data flag of Rx Buffer 48             */

+#define FDCAN_NDAT2_ND49_Pos      (17U)

+#define FDCAN_NDAT2_ND49_Msk      (0x1UL << FDCAN_NDAT2_ND49_Pos)              /*!< 0x00020000 */

+#define FDCAN_NDAT2_ND49          FDCAN_NDAT2_ND49_Msk                         /*!<New Data flag of Rx Buffer 49             */

+#define FDCAN_NDAT2_ND50_Pos      (18U)

+#define FDCAN_NDAT2_ND50_Msk      (0x1UL << FDCAN_NDAT2_ND50_Pos)              /*!< 0x00040000 */

+#define FDCAN_NDAT2_ND50          FDCAN_NDAT2_ND50_Msk                         /*!<New Data flag of Rx Buffer 50             */

+#define FDCAN_NDAT2_ND51_Pos      (19U)

+#define FDCAN_NDAT2_ND51_Msk      (0x1UL << FDCAN_NDAT2_ND51_Pos)              /*!< 0x00080000 */

+#define FDCAN_NDAT2_ND51          FDCAN_NDAT2_ND51_Msk                         /*!<New Data flag of Rx Buffer 51             */

+#define FDCAN_NDAT2_ND52_Pos      (20U)

+#define FDCAN_NDAT2_ND52_Msk      (0x1UL << FDCAN_NDAT2_ND52_Pos)              /*!< 0x00100000 */

+#define FDCAN_NDAT2_ND52          FDCAN_NDAT2_ND52_Msk                         /*!<New Data flag of Rx Buffer 52             */

+#define FDCAN_NDAT2_ND53_Pos      (21U)

+#define FDCAN_NDAT2_ND53_Msk      (0x1UL << FDCAN_NDAT2_ND53_Pos)              /*!< 0x00200000 */

+#define FDCAN_NDAT2_ND53          FDCAN_NDAT2_ND53_Msk                         /*!<New Data flag of Rx Buffer 53             */

+#define FDCAN_NDAT2_ND54_Pos      (22U)

+#define FDCAN_NDAT2_ND54_Msk      (0x1UL << FDCAN_NDAT2_ND54_Pos)              /*!< 0x00400000 */

+#define FDCAN_NDAT2_ND54          FDCAN_NDAT2_ND54_Msk                         /*!<New Data flag of Rx Buffer 54             */

+#define FDCAN_NDAT2_ND55_Pos      (23U)

+#define FDCAN_NDAT2_ND55_Msk      (0x1UL << FDCAN_NDAT2_ND55_Pos)              /*!< 0x00800000 */

+#define FDCAN_NDAT2_ND55          FDCAN_NDAT2_ND55_Msk                         /*!<New Data flag of Rx Buffer 55             */

+#define FDCAN_NDAT2_ND56_Pos      (24U)

+#define FDCAN_NDAT2_ND56_Msk      (0x1UL << FDCAN_NDAT2_ND56_Pos)              /*!< 0x01000000 */

+#define FDCAN_NDAT2_ND56          FDCAN_NDAT2_ND56_Msk                         /*!<New Data flag of Rx Buffer 56             */

+#define FDCAN_NDAT2_ND57_Pos      (25U)

+#define FDCAN_NDAT2_ND57_Msk      (0x1UL << FDCAN_NDAT2_ND57_Pos)              /*!< 0x02000000 */

+#define FDCAN_NDAT2_ND57          FDCAN_NDAT2_ND57_Msk                         /*!<New Data flag of Rx Buffer 57             */

+#define FDCAN_NDAT2_ND58_Pos      (26U)

+#define FDCAN_NDAT2_ND58_Msk      (0x1UL << FDCAN_NDAT2_ND58_Pos)              /*!< 0x04000000 */

+#define FDCAN_NDAT2_ND58          FDCAN_NDAT2_ND58_Msk                         /*!<New Data flag of Rx Buffer 58             */

+#define FDCAN_NDAT2_ND59_Pos      (27U)

+#define FDCAN_NDAT2_ND59_Msk      (0x1UL << FDCAN_NDAT2_ND59_Pos)              /*!< 0x08000000 */

+#define FDCAN_NDAT2_ND59          FDCAN_NDAT2_ND59_Msk                         /*!<New Data flag of Rx Buffer 59             */

+#define FDCAN_NDAT2_ND60_Pos      (28U)

+#define FDCAN_NDAT2_ND60_Msk      (0x1UL << FDCAN_NDAT2_ND60_Pos)              /*!< 0x10000000 */

+#define FDCAN_NDAT2_ND60          FDCAN_NDAT2_ND60_Msk                         /*!<New Data flag of Rx Buffer 60             */

+#define FDCAN_NDAT2_ND61_Pos      (29U)

+#define FDCAN_NDAT2_ND61_Msk      (0x1UL << FDCAN_NDAT2_ND61_Pos)              /*!< 0x20000000 */

+#define FDCAN_NDAT2_ND61          FDCAN_NDAT2_ND61_Msk                         /*!<New Data flag of Rx Buffer 61             */

+#define FDCAN_NDAT2_ND62_Pos      (30U)

+#define FDCAN_NDAT2_ND62_Msk      (0x1UL << FDCAN_NDAT2_ND62_Pos)              /*!< 0x40000000 */

+#define FDCAN_NDAT2_ND62          FDCAN_NDAT2_ND62_Msk                         /*!<New Data flag of Rx Buffer 62             */

+#define FDCAN_NDAT2_ND63_Pos      (31U)

+#define FDCAN_NDAT2_ND63_Msk      (0x1UL << FDCAN_NDAT2_ND63_Pos)              /*!< 0x80000000 */

+#define FDCAN_NDAT2_ND63          FDCAN_NDAT2_ND63_Msk                         /*!<New Data flag of Rx Buffer 63             */

+

+/*****************  Bit definition for FDCAN_RXF0C register  ********************/

+#define FDCAN_RXF0C_F0SA_Pos      (2U)

+#define FDCAN_RXF0C_F0SA_Msk      (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_RXF0C_F0SA          FDCAN_RXF0C_F0SA_Msk                         /*!<Rx FIFO 0 Start Address                   */

+#define FDCAN_RXF0C_F0S_Pos       (16U)

+#define FDCAN_RXF0C_F0S_Msk       (0x7FUL << FDCAN_RXF0C_F0S_Pos)              /*!< 0x007F0000 */

+#define FDCAN_RXF0C_F0S           FDCAN_RXF0C_F0S_Msk                          /*!<Number of Rx FIFO 0 elements              */

+#define FDCAN_RXF0C_F0WM_Pos      (24U)

+#define FDCAN_RXF0C_F0WM_Msk      (0x7FUL << FDCAN_RXF0C_F0WM_Pos)             /*!< 0x7F000000 */

+#define FDCAN_RXF0C_F0WM          FDCAN_RXF0C_F0WM_Msk                         /*!<FIFO 0 Watermark                          */

+#define FDCAN_RXF0C_F0OM_Pos      (31U)

+#define FDCAN_RXF0C_F0OM_Msk      (0x1UL << FDCAN_RXF0C_F0OM_Pos)              /*!< 0x80000000 */

+#define FDCAN_RXF0C_F0OM          FDCAN_RXF0C_F0OM_Msk                         /*!<FIFO 0 Operation Mode                     */

+

+/*****************  Bit definition for FDCAN_RXF0S register  ********************/

+#define FDCAN_RXF0S_F0FL_Pos      (0U)

+#define FDCAN_RXF0S_F0FL_Msk      (0x7FUL << FDCAN_RXF0S_F0FL_Pos)             /*!< 0x0000007F */

+#define FDCAN_RXF0S_F0FL          FDCAN_RXF0S_F0FL_Msk                         /*!<Rx FIFO 0 Fill Level                      */

+#define FDCAN_RXF0S_F0GI_Pos      (8U)

+#define FDCAN_RXF0S_F0GI_Msk      (0x3FUL << FDCAN_RXF0S_F0GI_Pos)             /*!< 0x00003F00 */

+#define FDCAN_RXF0S_F0GI          FDCAN_RXF0S_F0GI_Msk                         /*!<Rx FIFO 0 Get Index                       */

+#define FDCAN_RXF0S_F0PI_Pos      (16U)

+#define FDCAN_RXF0S_F0PI_Msk      (0x3FUL << FDCAN_RXF0S_F0PI_Pos)             /*!< 0x003F0000 */

+#define FDCAN_RXF0S_F0PI          FDCAN_RXF0S_F0PI_Msk                         /*!<Rx FIFO 0 Put Index                       */

+#define FDCAN_RXF0S_F0F_Pos       (24U)

+#define FDCAN_RXF0S_F0F_Msk       (0x1UL << FDCAN_RXF0S_F0F_Pos)               /*!< 0x01000000 */

+#define FDCAN_RXF0S_F0F           FDCAN_RXF0S_F0F_Msk                          /*!<Rx FIFO 0 Full                            */

+#define FDCAN_RXF0S_RF0L_Pos      (25U)

+#define FDCAN_RXF0S_RF0L_Msk      (0x1UL << FDCAN_RXF0S_RF0L_Pos)              /*!< 0x02000000 */

+#define FDCAN_RXF0S_RF0L          FDCAN_RXF0S_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                    */

+

+/*****************  Bit definition for FDCAN_RXF0A register  ********************/

+#define FDCAN_RXF0A_F0AI_Pos      (0U)

+#define FDCAN_RXF0A_F0AI_Msk      (0x3FUL << FDCAN_RXF0A_F0AI_Pos)             /*!< 0x0000003F */

+#define FDCAN_RXF0A_F0AI          FDCAN_RXF0A_F0AI_Msk                         /*!<Rx FIFO 0 Acknowledge Index               */

+

+/*****************  Bit definition for FDCAN_RXBC register  ********************/

+#define FDCAN_RXBC_RBSA_Pos       (2U)

+#define FDCAN_RXBC_RBSA_Msk       (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)            /*!< 0x0000FFFC */

+#define FDCAN_RXBC_RBSA           FDCAN_RXBC_RBSA_Msk                          /*!<Rx Buffer Start Address                   */

+

+/*****************  Bit definition for FDCAN_RXF1C register  ********************/

+#define FDCAN_RXF1C_F1SA_Pos      (2U)

+#define FDCAN_RXF1C_F1SA_Msk      (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_RXF1C_F1SA          FDCAN_RXF1C_F1SA_Msk                         /*!<Rx FIFO 1 Start Address                   */

+#define FDCAN_RXF1C_F1S_Pos       (16U)

+#define FDCAN_RXF1C_F1S_Msk       (0x7FUL << FDCAN_RXF1C_F1S_Pos)              /*!< 0x007F0000 */

+#define FDCAN_RXF1C_F1S           FDCAN_RXF1C_F1S_Msk                          /*!<Number of Rx FIFO 1 elements              */

+#define FDCAN_RXF1C_F1WM_Pos      (24U)

+#define FDCAN_RXF1C_F1WM_Msk      (0x7FUL << FDCAN_RXF1C_F1WM_Pos)             /*!< 0x7F000000 */

+#define FDCAN_RXF1C_F1WM          FDCAN_RXF1C_F1WM_Msk                         /*!<Rx FIFO 1 Watermark                       */

+#define FDCAN_RXF1C_F1OM_Pos      (31U)

+#define FDCAN_RXF1C_F1OM_Msk      (0x1UL << FDCAN_RXF1C_F1OM_Pos)              /*!< 0x80000000 */

+#define FDCAN_RXF1C_F1OM          FDCAN_RXF1C_F1OM_Msk                         /*!<FIFO 1 Operation Mode                     */

+

+/*****************  Bit definition for FDCAN_RXF1S register  ********************/

+#define FDCAN_RXF1S_F1FL_Pos      (0U)

+#define FDCAN_RXF1S_F1FL_Msk      (0x7FUL << FDCAN_RXF1S_F1FL_Pos)             /*!< 0x0000007F */

+#define FDCAN_RXF1S_F1FL          FDCAN_RXF1S_F1FL_Msk                         /*!<Rx FIFO 1 Fill Level                      */

+#define FDCAN_RXF1S_F1GI_Pos      (8U)

+#define FDCAN_RXF1S_F1GI_Msk      (0x3FUL << FDCAN_RXF1S_F1GI_Pos)             /*!< 0x00003F00 */

+#define FDCAN_RXF1S_F1GI          FDCAN_RXF1S_F1GI_Msk                         /*!<Rx FIFO 1 Get Index                       */

+#define FDCAN_RXF1S_F1PI_Pos      (16U)

+#define FDCAN_RXF1S_F1PI_Msk      (0x3FUL << FDCAN_RXF1S_F1PI_Pos)             /*!< 0x003F0000 */

+#define FDCAN_RXF1S_F1PI          FDCAN_RXF1S_F1PI_Msk                         /*!<Rx FIFO 1 Put Index                       */

+#define FDCAN_RXF1S_F1F_Pos       (24U)

+#define FDCAN_RXF1S_F1F_Msk       (0x1UL << FDCAN_RXF1S_F1F_Pos)               /*!< 0x01000000 */

+#define FDCAN_RXF1S_F1F           FDCAN_RXF1S_F1F_Msk                          /*!<Rx FIFO 1 Full                            */

+#define FDCAN_RXF1S_RF1L_Pos      (25U)

+#define FDCAN_RXF1S_RF1L_Msk      (0x1UL << FDCAN_RXF1S_RF1L_Pos)              /*!< 0x02000000 */

+#define FDCAN_RXF1S_RF1L          FDCAN_RXF1S_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                    */

+

+/*****************  Bit definition for FDCAN_RXF1A register  ********************/

+#define FDCAN_RXF1A_F1AI_Pos      (0U)

+#define FDCAN_RXF1A_F1AI_Msk      (0x3FUL << FDCAN_RXF1A_F1AI_Pos)             /*!< 0x0000003F */

+#define FDCAN_RXF1A_F1AI          FDCAN_RXF1A_F1AI_Msk                         /*!<Rx FIFO 1 Acknowledge Index               */

+

+/*****************  Bit definition for FDCAN_RXESC register  ********************/

+#define FDCAN_RXESC_F0DS_Pos      (0U)

+#define FDCAN_RXESC_F0DS_Msk      (0x7UL << FDCAN_RXESC_F0DS_Pos)              /*!< 0x00000007 */

+#define FDCAN_RXESC_F0DS          FDCAN_RXESC_F0DS_Msk                         /*!<Rx FIFO 1 Data Field Size                 */

+#define FDCAN_RXESC_F1DS_Pos      (4U)

+#define FDCAN_RXESC_F1DS_Msk      (0x7UL << FDCAN_RXESC_F1DS_Pos)              /*!< 0x00000070 */

+#define FDCAN_RXESC_F1DS          FDCAN_RXESC_F1DS_Msk                         /*!<Rx FIFO 0 Data Field Size                 */

+#define FDCAN_RXESC_RBDS_Pos      (8U)

+#define FDCAN_RXESC_RBDS_Msk      (0x7UL << FDCAN_RXESC_RBDS_Pos)              /*!< 0x00000700 */

+#define FDCAN_RXESC_RBDS          FDCAN_RXESC_RBDS_Msk                         /*!<Rx Buffer Data Field Size                 */

+

+/*****************  Bit definition for FDCAN_TXBC register  *********************/

+#define FDCAN_TXBC_TBSA_Pos       (2U)

+#define FDCAN_TXBC_TBSA_Msk       (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)            /*!< 0x0000FFFC */

+#define FDCAN_TXBC_TBSA           FDCAN_TXBC_TBSA_Msk                          /*!<Tx Buffers Start Address                  */

+#define FDCAN_TXBC_NDTB_Pos       (16U)

+#define FDCAN_TXBC_NDTB_Msk       (0x3FUL << FDCAN_TXBC_NDTB_Pos)              /*!< 0x003F0000 */

+#define FDCAN_TXBC_NDTB           FDCAN_TXBC_NDTB_Msk                          /*!<Number of Dedicated Transmit Buffers      */

+#define FDCAN_TXBC_TFQS_Pos       (24U)

+#define FDCAN_TXBC_TFQS_Msk       (0x3FUL << FDCAN_TXBC_TFQS_Pos)              /*!< 0x3F000000 */

+#define FDCAN_TXBC_TFQS           FDCAN_TXBC_TFQS_Msk                          /*!<Transmit FIFO/Queue Size                  */

+#define FDCAN_TXBC_TFQM_Pos       (30U)

+#define FDCAN_TXBC_TFQM_Msk       (0x1UL << FDCAN_TXBC_TFQM_Pos)               /*!< 0x40000000 */

+#define FDCAN_TXBC_TFQM           FDCAN_TXBC_TFQM_Msk                          /*!<Tx FIFO/Queue Mode                        */

+

+/*****************  Bit definition for FDCAN_TXFQS register  *********************/

+#define FDCAN_TXFQS_TFFL_Pos      (0U)

+#define FDCAN_TXFQS_TFFL_Msk      (0x3FUL << FDCAN_TXFQS_TFFL_Pos)             /*!< 0x0000003F */

+#define FDCAN_TXFQS_TFFL          FDCAN_TXFQS_TFFL_Msk                         /*!<Tx FIFO Free Level                        */

+#define FDCAN_TXFQS_TFGI_Pos      (8U)

+#define FDCAN_TXFQS_TFGI_Msk      (0x1FUL << FDCAN_TXFQS_TFGI_Pos)             /*!< 0x00001F00 */

+#define FDCAN_TXFQS_TFGI          FDCAN_TXFQS_TFGI_Msk                         /*!<Tx FIFO Get Index                         */

+#define FDCAN_TXFQS_TFQPI_Pos     (16U)

+#define FDCAN_TXFQS_TFQPI_Msk     (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)            /*!< 0x001F0000 */

+#define FDCAN_TXFQS_TFQPI         FDCAN_TXFQS_TFQPI_Msk                        /*!<Tx FIFO/Queue Put Index                   */

+#define FDCAN_TXFQS_TFQF_Pos      (21U)

+#define FDCAN_TXFQS_TFQF_Msk      (0x1UL << FDCAN_TXFQS_TFQF_Pos)              /*!< 0x00200000 */

+#define FDCAN_TXFQS_TFQF          FDCAN_TXFQS_TFQF_Msk                         /*!<Tx FIFO/Queue Full                        */

+

+/*****************  Bit definition for FDCAN_TXESC register  *********************/

+#define FDCAN_TXESC_TBDS_Pos      (0U)

+#define FDCAN_TXESC_TBDS_Msk      (0x7UL << FDCAN_TXESC_TBDS_Pos)              /*!< 0x00000007 */

+#define FDCAN_TXESC_TBDS          FDCAN_TXESC_TBDS_Msk                         /*!<Tx Buffer Data Field Size                 */

+

+/*****************  Bit definition for FDCAN_TXBRP register  *********************/

+#define FDCAN_TXBRP_TRP_Pos       (0U)

+#define FDCAN_TXBRP_TRP_Msk       (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)        /*!< 0xFFFFFFFF */

+#define FDCAN_TXBRP_TRP           FDCAN_TXBRP_TRP_Msk                          /*!<Transmission Request Pending              */

+

+/*****************  Bit definition for FDCAN_TXBAR register  *********************/

+#define FDCAN_TXBAR_AR_Pos        (0U)

+#define FDCAN_TXBAR_AR_Msk        (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBAR_AR            FDCAN_TXBAR_AR_Msk                           /*!<Add Request                               */

+

+/*****************  Bit definition for FDCAN_TXBCR register  *********************/

+#define FDCAN_TXBCR_CR_Pos        (0U)

+#define FDCAN_TXBCR_CR_Msk        (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCR_CR            FDCAN_TXBCR_CR_Msk                           /*!<Cancellation Request                      */

+

+/*****************  Bit definition for FDCAN_TXBTO register  *********************/

+#define FDCAN_TXBTO_TO_Pos        (0U)

+#define FDCAN_TXBTO_TO_Msk        (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBTO_TO            FDCAN_TXBTO_TO_Msk                           /*!<Transmission Occurred                     */

+

+/*****************  Bit definition for FDCAN_TXBCF register  *********************/

+#define FDCAN_TXBCF_CF_Pos        (0U)

+#define FDCAN_TXBCF_CF_Msk        (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCF_CF            FDCAN_TXBCF_CF_Msk                           /*!<Cancellation Finished                     */

+

+/*****************  Bit definition for FDCAN_TXBTIE register  ********************/

+#define FDCAN_TXBTIE_TIE_Pos      (0U)

+#define FDCAN_TXBTIE_TIE_Msk      (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)       /*!< 0xFFFFFFFF */

+#define FDCAN_TXBTIE_TIE          FDCAN_TXBTIE_TIE_Msk                         /*!<Transmission Interrupt Enable             */

+

+/*****************  Bit definition for FDCAN_ TXBCIE register  *******************/

+#define FDCAN_TXBCIE_CFIE_Pos     (0U)

+#define FDCAN_TXBCIE_CFIE_Msk     (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)      /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCIE_CFIE         FDCAN_TXBCIE_CFIE_Msk                        /*!<Cancellation Finished Interrupt Enable    */

+

+/*****************  Bit definition for FDCAN_TXEFC register  *********************/

+#define FDCAN_TXEFC_EFSA_Pos      (2U)

+#define FDCAN_TXEFC_EFSA_Msk      (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_TXEFC_EFSA          FDCAN_TXEFC_EFSA_Msk                         /*!<Event FIFO Start Address                  */

+#define FDCAN_TXEFC_EFS_Pos       (16U)

+#define FDCAN_TXEFC_EFS_Msk       (0x3FUL << FDCAN_TXEFC_EFS_Pos)              /*!< 0x003F0000 */

+#define FDCAN_TXEFC_EFS           FDCAN_TXEFC_EFS_Msk                          /*!<Event FIFO Size                           */

+#define FDCAN_TXEFC_EFWM_Pos      (24U)

+#define FDCAN_TXEFC_EFWM_Msk      (0x3FUL << FDCAN_TXEFC_EFWM_Pos)             /*!< 0x3F000000 */

+#define FDCAN_TXEFC_EFWM          FDCAN_TXEFC_EFWM_Msk                         /*!<Event FIFO Watermark                      */

+

+/*****************  Bit definition for FDCAN_TXEFS register  *********************/

+#define FDCAN_TXEFS_EFFL_Pos      (0U)

+#define FDCAN_TXEFS_EFFL_Msk      (0x3FUL << FDCAN_TXEFS_EFFL_Pos)             /*!< 0x0000003F */

+#define FDCAN_TXEFS_EFFL          FDCAN_TXEFS_EFFL_Msk                         /*!<Event FIFO Fill Level                     */

+#define FDCAN_TXEFS_EFGI_Pos      (8U)

+#define FDCAN_TXEFS_EFGI_Msk      (0x1FUL << FDCAN_TXEFS_EFGI_Pos)             /*!< 0x00001F00 */

+#define FDCAN_TXEFS_EFGI          FDCAN_TXEFS_EFGI_Msk                         /*!<Event FIFO Get Index                      */

+#define FDCAN_TXEFS_EFPI_Pos      (16U)

+#define FDCAN_TXEFS_EFPI_Msk      (0x1FUL << FDCAN_TXEFS_EFPI_Pos)             /*!< 0x001F0000 */

+#define FDCAN_TXEFS_EFPI          FDCAN_TXEFS_EFPI_Msk                         /*!<Event FIFO Put Index                      */

+#define FDCAN_TXEFS_EFF_Pos       (24U)

+#define FDCAN_TXEFS_EFF_Msk       (0x1UL << FDCAN_TXEFS_EFF_Pos)               /*!< 0x01000000 */

+#define FDCAN_TXEFS_EFF           FDCAN_TXEFS_EFF_Msk                          /*!<Event FIFO Full                           */

+#define FDCAN_TXEFS_TEFL_Pos      (25U)

+#define FDCAN_TXEFS_TEFL_Msk      (0x1UL << FDCAN_TXEFS_TEFL_Pos)              /*!< 0x02000000 */

+#define FDCAN_TXEFS_TEFL          FDCAN_TXEFS_TEFL_Msk                         /*!<Tx Event FIFO Element Lost                */

+

+/*****************  Bit definition for FDCAN_TXEFA register  *********************/

+#define FDCAN_TXEFA_EFAI_Pos      (0U)

+#define FDCAN_TXEFA_EFAI_Msk      (0x1FUL << FDCAN_TXEFA_EFAI_Pos)             /*!< 0x0000001F */

+#define FDCAN_TXEFA_EFAI          FDCAN_TXEFA_EFAI_Msk                         /*!<Event FIFO Acknowledge Index              */

+

+/*****************  Bit definition for FDCAN_TTTMC register  *********************/

+#define FDCAN_TTTMC_TMSA_Pos      (2U)

+#define FDCAN_TTTMC_TMSA_Msk      (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_TTTMC_TMSA          FDCAN_TTTMC_TMSA_Msk                         /*!<Trigger Memory Start Address              */

+#define FDCAN_TTTMC_TME_Pos       (16U)

+#define FDCAN_TTTMC_TME_Msk       (0x7FUL << FDCAN_TTTMC_TME_Pos)              /*!< 0x007F0000 */

+#define FDCAN_TTTMC_TME           FDCAN_TTTMC_TME_Msk                          /*!<Trigger Memory Elements                   */

+

+/*****************  Bit definition for FDCAN_TTRMC register  *********************/

+#define FDCAN_TTRMC_RID_Pos       (0U)

+#define FDCAN_TTRMC_RID_Msk       (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)        /*!< 0x1FFFFFFF */

+#define FDCAN_TTRMC_RID           FDCAN_TTRMC_RID_Msk                          /*!<Reference Identifier                      */

+#define FDCAN_TTRMC_XTD_Pos       (30U)

+#define FDCAN_TTRMC_XTD_Msk       (0x1UL << FDCAN_TTRMC_XTD_Pos)               /*!< 0x40000000 */

+#define FDCAN_TTRMC_XTD           FDCAN_TTRMC_XTD_Msk                          /*!< Extended Identifier                      */

+#define FDCAN_TTRMC_RMPS_Pos      (31U)

+#define FDCAN_TTRMC_RMPS_Msk      (0x1UL << FDCAN_TTRMC_RMPS_Pos)              /*!< 0x80000000 */

+#define FDCAN_TTRMC_RMPS          FDCAN_TTRMC_RMPS_Msk                         /*!<Reference Message Payload Select          */

+

+/*****************  Bit definition for FDCAN_TTOCF register  *********************/

+#define FDCAN_TTOCF_OM_Pos        (0U)

+#define FDCAN_TTOCF_OM_Msk        (0x3UL << FDCAN_TTOCF_OM_Pos)                /*!< 0x00000003 */

+#define FDCAN_TTOCF_OM            FDCAN_TTOCF_OM_Msk                           /*!<Operation Mode                            */

+#define FDCAN_TTOCF_GEN_Pos       (3U)

+#define FDCAN_TTOCF_GEN_Msk       (0x1UL << FDCAN_TTOCF_GEN_Pos)               /*!< 0x00000008 */

+#define FDCAN_TTOCF_GEN           FDCAN_TTOCF_GEN_Msk                          /*!<Gap Enable                                */

+#define FDCAN_TTOCF_TM_Pos        (4U)

+#define FDCAN_TTOCF_TM_Msk        (0x1UL << FDCAN_TTOCF_TM_Pos)                /*!< 0x00000010 */

+#define FDCAN_TTOCF_TM            FDCAN_TTOCF_TM_Msk                           /*!<Time Master                               */

+#define FDCAN_TTOCF_LDSDL_Pos     (5U)

+#define FDCAN_TTOCF_LDSDL_Msk     (0x7UL << FDCAN_TTOCF_LDSDL_Pos)             /*!< 0x000000E0 */

+#define FDCAN_TTOCF_LDSDL         FDCAN_TTOCF_LDSDL_Msk                        /*!<LD of Synchronization Deviation Limit     */

+#define FDCAN_TTOCF_IRTO_Pos      (8U)

+#define FDCAN_TTOCF_IRTO_Msk      (0x7FUL << FDCAN_TTOCF_IRTO_Pos)             /*!< 0x00007F00 */

+#define FDCAN_TTOCF_IRTO          FDCAN_TTOCF_IRTO_Msk                         /*!<Initial Reference Trigger Offset          */

+#define FDCAN_TTOCF_EECS_Pos      (15U)

+#define FDCAN_TTOCF_EECS_Msk      (0x1UL << FDCAN_TTOCF_EECS_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTOCF_EECS          FDCAN_TTOCF_EECS_Msk                         /*!<Enable External Clock Synchronization     */

+#define FDCAN_TTOCF_AWL_Pos       (16U)

+#define FDCAN_TTOCF_AWL_Msk       (0xFFUL << FDCAN_TTOCF_AWL_Pos)              /*!< 0x00FF0000 */

+#define FDCAN_TTOCF_AWL           FDCAN_TTOCF_AWL_Msk                          /*!<Application Watchdog Limit                */

+#define FDCAN_TTOCF_EGTF_Pos      (24U)

+#define FDCAN_TTOCF_EGTF_Msk      (0x1UL << FDCAN_TTOCF_EGTF_Pos)              /*!< 0x01000000 */

+#define FDCAN_TTOCF_EGTF          FDCAN_TTOCF_EGTF_Msk                         /*!<Enable Global Time Filtering              */

+#define FDCAN_TTOCF_ECC_Pos       (25U)

+#define FDCAN_TTOCF_ECC_Msk       (0x1UL << FDCAN_TTOCF_ECC_Pos)               /*!< 0x02000000 */

+#define FDCAN_TTOCF_ECC           FDCAN_TTOCF_ECC_Msk                          /*!<Enable Clock Calibration                  */

+#define FDCAN_TTOCF_EVTP_Pos      (26U)

+#define FDCAN_TTOCF_EVTP_Msk      (0x1UL << FDCAN_TTOCF_EVTP_Pos)              /*!< 0x04000000 */

+#define FDCAN_TTOCF_EVTP          FDCAN_TTOCF_EVTP_Msk                         /*!<Event Trigger Polarity                    */

+

+/*****************  Bit definition for FDCAN_TTMLM register  *********************/

+#define FDCAN_TTMLM_CCM_Pos       (0U)

+#define FDCAN_TTMLM_CCM_Msk       (0x3FUL << FDCAN_TTMLM_CCM_Pos)              /*!< 0x0000003F */

+#define FDCAN_TTMLM_CCM           FDCAN_TTMLM_CCM_Msk                          /*!<Cycle Count Max                           */

+#define FDCAN_TTMLM_CSS_Pos       (6U)

+#define FDCAN_TTMLM_CSS_Msk       (0x3UL << FDCAN_TTMLM_CSS_Pos)               /*!< 0x000000C0 */

+#define FDCAN_TTMLM_CSS           FDCAN_TTMLM_CSS_Msk                          /*!<Cycle Start Synchronization               */

+#define FDCAN_TTMLM_TXEW_Pos      (8U)

+#define FDCAN_TTMLM_TXEW_Msk      (0xFUL << FDCAN_TTMLM_TXEW_Pos)              /*!< 0x00000F00 */

+#define FDCAN_TTMLM_TXEW          FDCAN_TTMLM_TXEW_Msk                         /*!<Tx Enable Window                          */

+#define FDCAN_TTMLM_ENTT_Pos      (16U)

+#define FDCAN_TTMLM_ENTT_Msk      (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)            /*!< 0x0FFF0000 */

+#define FDCAN_TTMLM_ENTT          FDCAN_TTMLM_ENTT_Msk                         /*!<Expected Number of Tx Triggers            */

+

+/*****************  Bit definition for FDCAN_TURCF register  *********************/

+#define FDCAN_TURCF_NCL_Pos       (0U)

+#define FDCAN_TURCF_NCL_Msk       (0xFFFFUL << FDCAN_TURCF_NCL_Pos)            /*!< 0x0000FFFF */

+#define FDCAN_TURCF_NCL           FDCAN_TURCF_NCL_Msk                          /*!<Numerator Configuration Low               */

+#define FDCAN_TURCF_DC_Pos        (16U)

+#define FDCAN_TURCF_DC_Msk        (0x3FFFUL << FDCAN_TURCF_DC_Pos)             /*!< 0x3FFF0000 */

+#define FDCAN_TURCF_DC            FDCAN_TURCF_DC_Msk                           /*!<Denominator Configuration                 */

+#define FDCAN_TURCF_ELT_Pos       (31U)

+#define FDCAN_TURCF_ELT_Msk       (0x1UL << FDCAN_TURCF_ELT_Pos)               /*!< 0x80000000 */

+#define FDCAN_TURCF_ELT           FDCAN_TURCF_ELT_Msk                          /*!<Enable Local Time                         */

+

+/*****************  Bit definition for FDCAN_TTOCN register  ********************/

+#define FDCAN_TTOCN_SGT_Pos       (0U)

+#define FDCAN_TTOCN_SGT_Msk       (0x1UL << FDCAN_TTOCN_SGT_Pos)               /*!< 0x00000001 */

+#define FDCAN_TTOCN_SGT           FDCAN_TTOCN_SGT_Msk                          /*!<Set Global time                           */

+#define FDCAN_TTOCN_ECS_Pos       (1U)

+#define FDCAN_TTOCN_ECS_Msk       (0x1UL << FDCAN_TTOCN_ECS_Pos)               /*!< 0x00000002 */

+#define FDCAN_TTOCN_ECS           FDCAN_TTOCN_ECS_Msk                          /*!<External Clock Synchronization            */

+#define FDCAN_TTOCN_SWP_Pos       (2U)

+#define FDCAN_TTOCN_SWP_Msk       (0x1UL << FDCAN_TTOCN_SWP_Pos)               /*!< 0x00000004 */

+#define FDCAN_TTOCN_SWP           FDCAN_TTOCN_SWP_Msk                          /*!<Stop Watch Polarity                       */

+#define FDCAN_TTOCN_SWS_Pos       (3U)

+#define FDCAN_TTOCN_SWS_Msk       (0x3UL << FDCAN_TTOCN_SWS_Pos)               /*!< 0x00000018 */

+#define FDCAN_TTOCN_SWS           FDCAN_TTOCN_SWS_Msk                          /*!<Stop Watch Source                         */

+#define FDCAN_TTOCN_RTIE_Pos      (5U)

+#define FDCAN_TTOCN_RTIE_Msk      (0x1UL << FDCAN_TTOCN_RTIE_Pos)              /*!< 0x00000020 */

+#define FDCAN_TTOCN_RTIE          FDCAN_TTOCN_RTIE_Msk                         /*!<Register Time Mark Interrupt Pulse Enable */

+#define FDCAN_TTOCN_TMC_Pos       (6U)

+#define FDCAN_TTOCN_TMC_Msk       (0x3UL << FDCAN_TTOCN_TMC_Pos)               /*!< 0x000000C0 */

+#define FDCAN_TTOCN_TMC           FDCAN_TTOCN_TMC_Msk                          /*!<Register Time Mark Compare                */

+#define FDCAN_TTOCN_TTIE_Pos      (8U)

+#define FDCAN_TTOCN_TTIE_Msk      (0x1UL << FDCAN_TTOCN_TTIE_Pos)              /*!< 0x00000100 */

+#define FDCAN_TTOCN_TTIE          FDCAN_TTOCN_TTIE_Msk                         /*!<Trigger Time Mark Interrupt Pulse Enable  */

+#define FDCAN_TTOCN_GCS_Pos       (9U)

+#define FDCAN_TTOCN_GCS_Msk       (0x1UL << FDCAN_TTOCN_GCS_Pos)               /*!< 0x00000200 */

+#define FDCAN_TTOCN_GCS           FDCAN_TTOCN_GCS_Msk                          /*!<Gap Control Select                        */

+#define FDCAN_TTOCN_FGP_Pos       (10U)

+#define FDCAN_TTOCN_FGP_Msk       (0x1UL << FDCAN_TTOCN_FGP_Pos)               /*!< 0x00000400 */

+#define FDCAN_TTOCN_FGP           FDCAN_TTOCN_FGP_Msk                          /*!<Finish Gap                                */

+#define FDCAN_TTOCN_TMG_Pos       (11U)

+#define FDCAN_TTOCN_TMG_Msk       (0x1UL << FDCAN_TTOCN_TMG_Pos)               /*!< 0x00000800 */

+#define FDCAN_TTOCN_TMG           FDCAN_TTOCN_TMG_Msk                          /*!<Time Mark Gap                             */

+#define FDCAN_TTOCN_NIG_Pos       (12U)

+#define FDCAN_TTOCN_NIG_Msk       (0x1UL << FDCAN_TTOCN_NIG_Pos)               /*!< 0x00001000 */

+#define FDCAN_TTOCN_NIG           FDCAN_TTOCN_NIG_Msk                          /*!<Next is Gap                               */

+#define FDCAN_TTOCN_ESCN_Pos      (13U)

+#define FDCAN_TTOCN_ESCN_Msk      (0x1UL << FDCAN_TTOCN_ESCN_Pos)              /*!< 0x00002000 */

+#define FDCAN_TTOCN_ESCN          FDCAN_TTOCN_ESCN_Msk                         /*!<External Synchronization Control          */

+#define FDCAN_TTOCN_LCKC_Pos      (15U)

+#define FDCAN_TTOCN_LCKC_Msk      (0x1UL << FDCAN_TTOCN_LCKC_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTOCN_LCKC          FDCAN_TTOCN_LCKC_Msk                         /*!<TT Operation Control Register Locked      */

+

+/*****************  Bit definition for FDCAN_TTGTP register  ********************/

+#define FDCAN_TTGTP_TP_Pos        (0U)

+#define FDCAN_TTGTP_TP_Msk        (0xFFFFUL << FDCAN_TTGTP_TP_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTGTP_TP            FDCAN_TTGTP_TP_Msk                           /*!<Time Preset                               */

+#define FDCAN_TTGTP_CTP_Pos       (16U)

+#define FDCAN_TTGTP_CTP_Msk       (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)            /*!< 0xFFFF0000 */

+#define FDCAN_TTGTP_CTP           FDCAN_TTGTP_CTP_Msk                          /*!<Cycle Time Target Phase                   */

+

+/*****************  Bit definition for FDCAN_TTTMK register  ********************/

+#define FDCAN_TTTMK_TM_Pos        (0U)

+#define FDCAN_TTTMK_TM_Msk        (0xFFFFUL << FDCAN_TTTMK_TM_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTTMK_TM            FDCAN_TTTMK_TM_Msk                           /*!<Time Mark                                 */

+#define FDCAN_TTTMK_TICC_Pos      (16U)

+#define FDCAN_TTTMK_TICC_Msk      (0x7FUL << FDCAN_TTTMK_TICC_Pos)             /*!< 0x007F0000 */

+#define FDCAN_TTTMK_TICC          FDCAN_TTTMK_TICC_Msk                         /*!<Time Mark Cycle Code                      */

+#define FDCAN_TTTMK_LCKM_Pos      (31U)

+#define FDCAN_TTTMK_LCKM_Msk      (0x1UL << FDCAN_TTTMK_LCKM_Pos)              /*!< 0x80000000 */

+#define FDCAN_TTTMK_LCKM          FDCAN_TTTMK_LCKM_Msk                         /*!<TT Time Mark Register Locked              */

+

+/*****************  Bit definition for FDCAN_TTIR register  ********************/

+#define FDCAN_TTIR_SBC_Pos        (0U)

+#define FDCAN_TTIR_SBC_Msk        (0x1UL << FDCAN_TTIR_SBC_Pos)                /*!< 0x00000001 */

+#define FDCAN_TTIR_SBC            FDCAN_TTIR_SBC_Msk                           /*!<Start of Basic Cycle                      */

+#define FDCAN_TTIR_SMC_Pos        (1U)

+#define FDCAN_TTIR_SMC_Msk        (0x1UL << FDCAN_TTIR_SMC_Pos)                /*!< 0x00000002 */

+#define FDCAN_TTIR_SMC            FDCAN_TTIR_SMC_Msk                           /*!<Start of Matrix Cycle                     */

+#define FDCAN_TTIR_CSM_Pos        (2U)

+#define FDCAN_TTIR_CSM_Msk        (0x1UL << FDCAN_TTIR_CSM_Pos)                /*!< 0x00000004 */

+#define FDCAN_TTIR_CSM            FDCAN_TTIR_CSM_Msk                           /*!<Change of Synchronization Mode            */

+#define FDCAN_TTIR_SOG_Pos        (3U)

+#define FDCAN_TTIR_SOG_Msk        (0x1UL << FDCAN_TTIR_SOG_Pos)                /*!< 0x00000008 */

+#define FDCAN_TTIR_SOG            FDCAN_TTIR_SOG_Msk                           /*!<Start of Gap                              */

+#define FDCAN_TTIR_RTMI_Pos       (4U)

+#define FDCAN_TTIR_RTMI_Msk       (0x1UL << FDCAN_TTIR_RTMI_Pos)               /*!< 0x00000010 */

+#define FDCAN_TTIR_RTMI           FDCAN_TTIR_RTMI_Msk                          /*!<Register Time Mark Interrupt              */

+#define FDCAN_TTIR_TTMI_Pos       (5U)

+#define FDCAN_TTIR_TTMI_Msk       (0x1UL << FDCAN_TTIR_TTMI_Pos)               /*!< 0x00000020 */

+#define FDCAN_TTIR_TTMI           FDCAN_TTIR_TTMI_Msk                          /*!<Trigger Time Mark Event Internal          */

+#define FDCAN_TTIR_SWE_Pos        (6U)

+#define FDCAN_TTIR_SWE_Msk        (0x1UL << FDCAN_TTIR_SWE_Pos)                /*!< 0x00000040 */

+#define FDCAN_TTIR_SWE            FDCAN_TTIR_SWE_Msk                           /*!<Stop Watch Event                          */

+#define FDCAN_TTIR_GTW_Pos        (7U)

+#define FDCAN_TTIR_GTW_Msk        (0x1UL << FDCAN_TTIR_GTW_Pos)                /*!< 0x00000080 */

+#define FDCAN_TTIR_GTW            FDCAN_TTIR_GTW_Msk                           /*!<Global Time Wrap                          */

+#define FDCAN_TTIR_GTD_Pos        (8U)

+#define FDCAN_TTIR_GTD_Msk        (0x1UL << FDCAN_TTIR_GTD_Pos)                /*!< 0x00000100 */

+#define FDCAN_TTIR_GTD            FDCAN_TTIR_GTD_Msk                           /*!<Global Time Discontinuity                 */

+#define FDCAN_TTIR_GTE_Pos        (9U)

+#define FDCAN_TTIR_GTE_Msk        (0x1UL << FDCAN_TTIR_GTE_Pos)                /*!< 0x00000200 */

+#define FDCAN_TTIR_GTE            FDCAN_TTIR_GTE_Msk                           /*!<Global Time Error                         */

+#define FDCAN_TTIR_TXU_Pos        (10U)

+#define FDCAN_TTIR_TXU_Msk        (0x1UL << FDCAN_TTIR_TXU_Pos)                /*!< 0x00000400 */

+#define FDCAN_TTIR_TXU            FDCAN_TTIR_TXU_Msk                           /*!<Tx Count Underflow                        */

+#define FDCAN_TTIR_TXO_Pos        (11U)

+#define FDCAN_TTIR_TXO_Msk        (0x1UL << FDCAN_TTIR_TXO_Pos)                /*!< 0x00000800 */

+#define FDCAN_TTIR_TXO            FDCAN_TTIR_TXO_Msk                           /*!<Tx Count Overflow                         */

+#define FDCAN_TTIR_SE1_Pos        (12U)

+#define FDCAN_TTIR_SE1_Msk        (0x1UL << FDCAN_TTIR_SE1_Pos)                /*!< 0x00001000 */

+#define FDCAN_TTIR_SE1            FDCAN_TTIR_SE1_Msk                           /*!<Scheduling Error 1                        */

+#define FDCAN_TTIR_SE2_Pos        (13U)

+#define FDCAN_TTIR_SE2_Msk        (0x1UL << FDCAN_TTIR_SE2_Pos)                /*!< 0x00002000 */

+#define FDCAN_TTIR_SE2            FDCAN_TTIR_SE2_Msk                           /*!<Scheduling Error 2                        */

+#define FDCAN_TTIR_ELC_Pos        (14U)

+#define FDCAN_TTIR_ELC_Msk        (0x1UL << FDCAN_TTIR_ELC_Pos)                /*!< 0x00004000 */

+#define FDCAN_TTIR_ELC            FDCAN_TTIR_ELC_Msk                           /*!<Error Level Changed                       */

+#define FDCAN_TTIR_IWT_Pos        (15U)

+#define FDCAN_TTIR_IWT_Msk        (0x1UL << FDCAN_TTIR_IWT_Pos)                /*!< 0x00008000 */

+#define FDCAN_TTIR_IWT            FDCAN_TTIR_IWT_Msk                           /*!<Initialization Watch Trigger              */

+#define FDCAN_TTIR_WT_Pos         (16U)

+#define FDCAN_TTIR_WT_Msk         (0x1UL << FDCAN_TTIR_WT_Pos)                 /*!< 0x00010000 */

+#define FDCAN_TTIR_WT             FDCAN_TTIR_WT_Msk                            /*!<Watch Trigger                             */

+#define FDCAN_TTIR_AW_Pos         (17U)

+#define FDCAN_TTIR_AW_Msk         (0x1UL << FDCAN_TTIR_AW_Pos)                 /*!< 0x00020000 */

+#define FDCAN_TTIR_AW             FDCAN_TTIR_AW_Msk                            /*!<Application Watchdog                      */

+#define FDCAN_TTIR_CER_Pos        (18U)

+#define FDCAN_TTIR_CER_Msk        (0x1UL << FDCAN_TTIR_CER_Pos)                /*!< 0x00040000 */

+#define FDCAN_TTIR_CER            FDCAN_TTIR_CER_Msk                           /*!<Configuration Error                       */

+

+/*****************  Bit definition for FDCAN_TTIE register  ********************/

+#define FDCAN_TTIE_SBCE_Pos       (0U)

+#define FDCAN_TTIE_SBCE_Msk       (0x1UL << FDCAN_TTIE_SBCE_Pos)               /*!< 0x00000001 */

+#define FDCAN_TTIE_SBCE           FDCAN_TTIE_SBCE_Msk                          /*!<Start of Basic Cycle Interrupt Enable             */

+#define FDCAN_TTIE_SMCE_Pos       (1U)

+#define FDCAN_TTIE_SMCE_Msk       (0x1UL << FDCAN_TTIE_SMCE_Pos)               /*!< 0x00000002 */

+#define FDCAN_TTIE_SMCE           FDCAN_TTIE_SMCE_Msk                          /*!<Start of Matrix Cycle Interrupt Enable            */

+#define FDCAN_TTIE_CSME_Pos       (2U)

+#define FDCAN_TTIE_CSME_Msk       (0x1UL << FDCAN_TTIE_CSME_Pos)               /*!< 0x00000004 */

+#define FDCAN_TTIE_CSME           FDCAN_TTIE_CSME_Msk                          /*!<Change of Synchronization Mode Interrupt Enable   */

+#define FDCAN_TTIE_SOGE_Pos       (3U)

+#define FDCAN_TTIE_SOGE_Msk       (0x1UL << FDCAN_TTIE_SOGE_Pos)               /*!< 0x00000008 */

+#define FDCAN_TTIE_SOGE           FDCAN_TTIE_SOGE_Msk                          /*!<Start of Gap Interrupt Enable                     */

+#define FDCAN_TTIE_RTMIE_Pos      (4U)

+#define FDCAN_TTIE_RTMIE_Msk      (0x1UL << FDCAN_TTIE_RTMIE_Pos)              /*!< 0x00000010 */

+#define FDCAN_TTIE_RTMIE          FDCAN_TTIE_RTMIE_Msk                         /*!<Register Time Mark Interrupt Interrupt Enable     */

+#define FDCAN_TTIE_TTMIE_Pos      (5U)

+#define FDCAN_TTIE_TTMIE_Msk      (0x1UL << FDCAN_TTIE_TTMIE_Pos)              /*!< 0x00000020 */

+#define FDCAN_TTIE_TTMIE          FDCAN_TTIE_TTMIE_Msk                         /*!<Trigger Time Mark Event Internal Interrupt Enable */

+#define FDCAN_TTIE_SWEE_Pos       (6U)

+#define FDCAN_TTIE_SWEE_Msk       (0x1UL << FDCAN_TTIE_SWEE_Pos)               /*!< 0x00000040 */

+#define FDCAN_TTIE_SWEE           FDCAN_TTIE_SWEE_Msk                          /*!<Stop Watch Event Interrupt Enable                 */

+#define FDCAN_TTIE_GTWE_Pos       (7U)

+#define FDCAN_TTIE_GTWE_Msk       (0x1UL << FDCAN_TTIE_GTWE_Pos)               /*!< 0x00000080 */

+#define FDCAN_TTIE_GTWE           FDCAN_TTIE_GTWE_Msk                          /*!<Global Time Wrap Interrupt Enable                 */

+#define FDCAN_TTIE_GTDE_Pos       (8U)

+#define FDCAN_TTIE_GTDE_Msk       (0x1UL << FDCAN_TTIE_GTDE_Pos)               /*!< 0x00000100 */

+#define FDCAN_TTIE_GTDE           FDCAN_TTIE_GTDE_Msk                          /*!<Global Time Discontinuity Interrupt Enable        */

+#define FDCAN_TTIE_GTEE_Pos       (9U)

+#define FDCAN_TTIE_GTEE_Msk       (0x1UL << FDCAN_TTIE_GTEE_Pos)               /*!< 0x00000200 */

+#define FDCAN_TTIE_GTEE           FDCAN_TTIE_GTEE_Msk                          /*!<Global Time Error Interrupt Enable                */

+#define FDCAN_TTIE_TXUE_Pos       (10U)

+#define FDCAN_TTIE_TXUE_Msk       (0x1UL << FDCAN_TTIE_TXUE_Pos)               /*!< 0x00000400 */

+#define FDCAN_TTIE_TXUE           FDCAN_TTIE_TXUE_Msk                          /*!<Tx Count Underflow Interrupt Enable               */

+#define FDCAN_TTIE_TXOE_Pos       (11U)

+#define FDCAN_TTIE_TXOE_Msk       (0x1UL << FDCAN_TTIE_TXOE_Pos)               /*!< 0x00000800 */

+#define FDCAN_TTIE_TXOE           FDCAN_TTIE_TXOE_Msk                          /*!<Tx Count Overflow Interrupt Enable                */

+#define FDCAN_TTIE_SE1E_Pos       (12U)

+#define FDCAN_TTIE_SE1E_Msk       (0x1UL << FDCAN_TTIE_SE1E_Pos)               /*!< 0x00001000 */

+#define FDCAN_TTIE_SE1E           FDCAN_TTIE_SE1E_Msk                          /*!<Scheduling Error 1 Interrupt Enable               */

+#define FDCAN_TTIE_SE2E_Pos       (13U)

+#define FDCAN_TTIE_SE2E_Msk       (0x1UL << FDCAN_TTIE_SE2E_Pos)               /*!< 0x00002000 */

+#define FDCAN_TTIE_SE2E           FDCAN_TTIE_SE2E_Msk                          /*!<Scheduling Error 2 Interrupt Enable               */

+#define FDCAN_TTIE_ELCE_Pos       (14U)

+#define FDCAN_TTIE_ELCE_Msk       (0x1UL << FDCAN_TTIE_ELCE_Pos)               /*!< 0x00004000 */

+#define FDCAN_TTIE_ELCE           FDCAN_TTIE_ELCE_Msk                          /*!<Error Level Changed Interrupt Enable              */

+#define FDCAN_TTIE_IWTE_Pos       (15U)

+#define FDCAN_TTIE_IWTE_Msk       (0x1UL << FDCAN_TTIE_IWTE_Pos)               /*!< 0x00008000 */

+#define FDCAN_TTIE_IWTE           FDCAN_TTIE_IWTE_Msk                          /*!<Initialization Watch Trigger Interrupt Enable     */

+#define FDCAN_TTIE_WTE_Pos        (16U)

+#define FDCAN_TTIE_WTE_Msk        (0x1UL << FDCAN_TTIE_WTE_Pos)                /*!< 0x00010000 */

+#define FDCAN_TTIE_WTE            FDCAN_TTIE_WTE_Msk                           /*!<Watch Trigger Interrupt Enable                    */

+#define FDCAN_TTIE_AWE_Pos        (17U)

+#define FDCAN_TTIE_AWE_Msk        (0x1UL << FDCAN_TTIE_AWE_Pos)                /*!< 0x00020000 */

+#define FDCAN_TTIE_AWE            FDCAN_TTIE_AWE_Msk                           /*!<Application Watchdog Interrupt Enable             */

+#define FDCAN_TTIE_CERE_Pos       (18U)

+#define FDCAN_TTIE_CERE_Msk       (0x1UL << FDCAN_TTIE_CERE_Pos)               /*!< 0x00040000 */

+#define FDCAN_TTIE_CERE           FDCAN_TTIE_CERE_Msk                          /*!<Configuration Error Interrupt Enable              */

+

+/*****************  Bit definition for FDCAN_TTILS register  ********************/

+#define FDCAN_TTILS_SBCS_Pos      (0U)

+#define FDCAN_TTILS_SBCS_Msk      (0x1UL << FDCAN_TTILS_SBCS_Pos)              /*!< 0x00000001 */

+#define FDCAN_TTILS_SBCS          FDCAN_TTILS_SBCS_Msk                         /*!<Start of Basic Cycle Interrupt Line               */

+#define FDCAN_TTILS_SMCS_Pos      (1U)

+#define FDCAN_TTILS_SMCS_Msk      (0x1UL << FDCAN_TTILS_SMCS_Pos)              /*!< 0x00000002 */

+#define FDCAN_TTILS_SMCS          FDCAN_TTILS_SMCS_Msk                         /*!<Start of Matrix Cycle Interrupt Line              */

+#define FDCAN_TTILS_CSMS_Pos      (2U)

+#define FDCAN_TTILS_CSMS_Msk      (0x1UL << FDCAN_TTILS_CSMS_Pos)              /*!< 0x00000004 */

+#define FDCAN_TTILS_CSMS          FDCAN_TTILS_CSMS_Msk                         /*!<Change of Synchronization Mode Interrupt Line     */

+#define FDCAN_TTILS_SOGS_Pos      (3U)

+#define FDCAN_TTILS_SOGS_Msk      (0x1UL << FDCAN_TTILS_SOGS_Pos)              /*!< 0x00000008 */

+#define FDCAN_TTILS_SOGS          FDCAN_TTILS_SOGS_Msk                         /*!<Start of Gap Interrupt Line                       */

+#define FDCAN_TTILS_RTMIS_Pos     (4U)

+#define FDCAN_TTILS_RTMIS_Msk     (0x1UL << FDCAN_TTILS_RTMIS_Pos)             /*!< 0x00000010 */

+#define FDCAN_TTILS_RTMIS         FDCAN_TTILS_RTMIS_Msk                        /*!<Register Time Mark Interrupt Interrupt Line       */

+#define FDCAN_TTILS_TTMIS_Pos     (5U)

+#define FDCAN_TTILS_TTMIS_Msk     (0x1UL << FDCAN_TTILS_TTMIS_Pos)             /*!< 0x00000020 */

+#define FDCAN_TTILS_TTMIS         FDCAN_TTILS_TTMIS_Msk                        /*!<Trigger Time Mark Event Internal Interrupt Line   */

+#define FDCAN_TTILS_SWES_Pos      (6U)

+#define FDCAN_TTILS_SWES_Msk      (0x1UL << FDCAN_TTILS_SWES_Pos)              /*!< 0x00000040 */

+#define FDCAN_TTILS_SWES          FDCAN_TTILS_SWES_Msk                         /*!<Stop Watch Event Interrupt Line                   */

+#define FDCAN_TTILS_GTWS_Pos      (7U)

+#define FDCAN_TTILS_GTWS_Msk      (0x1UL << FDCAN_TTILS_GTWS_Pos)              /*!< 0x00000080 */

+#define FDCAN_TTILS_GTWS          FDCAN_TTILS_GTWS_Msk                         /*!<Global Time Wrap Interrupt Line                   */

+#define FDCAN_TTILS_GTDS_Pos      (8U)

+#define FDCAN_TTILS_GTDS_Msk      (0x1UL << FDCAN_TTILS_GTDS_Pos)              /*!< 0x00000100 */

+#define FDCAN_TTILS_GTDS          FDCAN_TTILS_GTDS_Msk                         /*!<Global Time Discontinuity Interrupt Line          */

+#define FDCAN_TTILS_GTES_Pos      (9U)

+#define FDCAN_TTILS_GTES_Msk      (0x1UL << FDCAN_TTILS_GTES_Pos)              /*!< 0x00000200 */

+#define FDCAN_TTILS_GTES          FDCAN_TTILS_GTES_Msk                         /*!<Global Time Error Interrupt Line                  */

+#define FDCAN_TTILS_TXUS_Pos      (10U)

+#define FDCAN_TTILS_TXUS_Msk      (0x1UL << FDCAN_TTILS_TXUS_Pos)              /*!< 0x00000400 */

+#define FDCAN_TTILS_TXUS          FDCAN_TTILS_TXUS_Msk                         /*!<Tx Count Underflow Interrupt Line                 */

+#define FDCAN_TTILS_TXOS_Pos      (11U)

+#define FDCAN_TTILS_TXOS_Msk      (0x1UL << FDCAN_TTILS_TXOS_Pos)              /*!< 0x00000800 */

+#define FDCAN_TTILS_TXOS          FDCAN_TTILS_TXOS_Msk                         /*!<Tx Count Overflow Interrupt Line                  */

+#define FDCAN_TTILS_SE1S_Pos      (12U)

+#define FDCAN_TTILS_SE1S_Msk      (0x1UL << FDCAN_TTILS_SE1S_Pos)              /*!< 0x00001000 */

+#define FDCAN_TTILS_SE1S          FDCAN_TTILS_SE1S_Msk                         /*!<Scheduling Error 1 Interrupt Line                 */

+#define FDCAN_TTILS_SE2S_Pos      (13U)

+#define FDCAN_TTILS_SE2S_Msk      (0x1UL << FDCAN_TTILS_SE2S_Pos)              /*!< 0x00002000 */

+#define FDCAN_TTILS_SE2S          FDCAN_TTILS_SE2S_Msk                         /*!<Scheduling Error 2 Interrupt Line                 */

+#define FDCAN_TTILS_ELCS_Pos      (14U)

+#define FDCAN_TTILS_ELCS_Msk      (0x1UL << FDCAN_TTILS_ELCS_Pos)              /*!< 0x00004000 */

+#define FDCAN_TTILS_ELCS          FDCAN_TTILS_ELCS_Msk                         /*!<Error Level Changed Interrupt Line                */

+#define FDCAN_TTILS_IWTS_Pos      (15U)

+#define FDCAN_TTILS_IWTS_Msk      (0x1UL << FDCAN_TTILS_IWTS_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTILS_IWTS          FDCAN_TTILS_IWTS_Msk                         /*!<Initialization Watch Trigger Interrupt Line       */

+#define FDCAN_TTILS_WTS_Pos       (16U)

+#define FDCAN_TTILS_WTS_Msk       (0x1UL << FDCAN_TTILS_WTS_Pos)               /*!< 0x00010000 */

+#define FDCAN_TTILS_WTS           FDCAN_TTILS_WTS_Msk                          /*!<Watch Trigger Interrupt Line                      */

+#define FDCAN_TTILS_AWS_Pos       (17U)

+#define FDCAN_TTILS_AWS_Msk       (0x1UL << FDCAN_TTILS_AWS_Pos)               /*!< 0x00020000 */

+#define FDCAN_TTILS_AWS           FDCAN_TTILS_AWS_Msk                          /*!<Application Watchdog Interrupt Line               */

+#define FDCAN_TTILS_CERS_Pos      (18U)

+#define FDCAN_TTILS_CERS_Msk      (0x1UL << FDCAN_TTILS_CERS_Pos)              /*!< 0x00040000 */

+#define FDCAN_TTILS_CERS          FDCAN_TTILS_CERS_Msk                         /*!<Configuration Error Interrupt Line                */

+

+/*****************  Bit definition for FDCAN_TTOST register  ********************/

+#define FDCAN_TTOST_EL_Pos        (0U)

+#define FDCAN_TTOST_EL_Msk        (0x3UL << FDCAN_TTOST_EL_Pos)                /*!< 0x00000003 */

+#define FDCAN_TTOST_EL            FDCAN_TTOST_EL_Msk                           /*!<Error Level                              */

+#define FDCAN_TTOST_MS_Pos        (2U)

+#define FDCAN_TTOST_MS_Msk        (0x3UL << FDCAN_TTOST_MS_Pos)                /*!< 0x0000000C */

+#define FDCAN_TTOST_MS            FDCAN_TTOST_MS_Msk                           /*!<Master State                             */

+#define FDCAN_TTOST_SYS_Pos       (4U)

+#define FDCAN_TTOST_SYS_Msk       (0x3UL << FDCAN_TTOST_SYS_Pos)               /*!< 0x00000030 */

+#define FDCAN_TTOST_SYS           FDCAN_TTOST_SYS_Msk                          /*!<Synchronization State                    */

+#define FDCAN_TTOST_QGTP_Pos      (6U)

+#define FDCAN_TTOST_QGTP_Msk      (0x1UL << FDCAN_TTOST_QGTP_Pos)              /*!< 0x00000040 */

+#define FDCAN_TTOST_QGTP          FDCAN_TTOST_QGTP_Msk                         /*!<Quality of Global Time Phase             */

+#define FDCAN_TTOST_QCS_Pos       (7U)

+#define FDCAN_TTOST_QCS_Msk       (0x1UL << FDCAN_TTOST_QCS_Pos)               /*!< 0x00000080 */

+#define FDCAN_TTOST_QCS           FDCAN_TTOST_QCS_Msk                          /*!<Quality of Clock Speed                   */

+#define FDCAN_TTOST_RTO_Pos       (8U)

+#define FDCAN_TTOST_RTO_Msk       (0xFFUL << FDCAN_TTOST_RTO_Pos)              /*!< 0x0000FF00 */

+#define FDCAN_TTOST_RTO           FDCAN_TTOST_RTO_Msk                          /*!<Reference Trigger Offset                 */

+#define FDCAN_TTOST_WGTD_Pos      (22U)

+#define FDCAN_TTOST_WGTD_Msk      (0x1UL << FDCAN_TTOST_WGTD_Pos)              /*!< 0x00400000 */

+#define FDCAN_TTOST_WGTD          FDCAN_TTOST_WGTD_Msk                         /*!<Wait for Global Time Discontinuity       */

+#define FDCAN_TTOST_GFI_Pos       (23U)

+#define FDCAN_TTOST_GFI_Msk       (0x1UL << FDCAN_TTOST_GFI_Pos)               /*!< 0x00800000 */

+#define FDCAN_TTOST_GFI           FDCAN_TTOST_GFI_Msk                          /*!<Gap Finished Indicator                   */

+#define FDCAN_TTOST_TMP_Pos       (24U)

+#define FDCAN_TTOST_TMP_Msk       (0x7UL << FDCAN_TTOST_TMP_Pos)               /*!< 0x07000000 */

+#define FDCAN_TTOST_TMP           FDCAN_TTOST_TMP_Msk                          /*!<Time Master Priority                     */

+#define FDCAN_TTOST_GSI_Pos       (27U)

+#define FDCAN_TTOST_GSI_Msk       (0x1UL << FDCAN_TTOST_GSI_Pos)               /*!< 0x08000000 */

+#define FDCAN_TTOST_GSI           FDCAN_TTOST_GSI_Msk                          /*!<Gap Started Indicator                    */

+#define FDCAN_TTOST_WFE_Pos       (28U)

+#define FDCAN_TTOST_WFE_Msk       (0x1UL << FDCAN_TTOST_WFE_Pos)               /*!< 0x10000000 */

+#define FDCAN_TTOST_WFE           FDCAN_TTOST_WFE_Msk                          /*!<Wait for Event                           */

+#define FDCAN_TTOST_AWE_Pos       (29U)

+#define FDCAN_TTOST_AWE_Msk       (0x1UL << FDCAN_TTOST_AWE_Pos)               /*!< 0x20000000 */

+#define FDCAN_TTOST_AWE           FDCAN_TTOST_AWE_Msk                          /*!<Application Watchdog Event               */

+#define FDCAN_TTOST_WECS_Pos      (30U)

+#define FDCAN_TTOST_WECS_Msk      (0x1UL << FDCAN_TTOST_WECS_Pos)              /*!< 0x40000000 */

+#define FDCAN_TTOST_WECS          FDCAN_TTOST_WECS_Msk                         /*!<Wait for External Clock Synchronization  */

+#define FDCAN_TTOST_SPL_Pos       (31U)

+#define FDCAN_TTOST_SPL_Msk       (0x1UL << FDCAN_TTOST_SPL_Pos)               /*!< 0x80000000 */

+#define FDCAN_TTOST_SPL           FDCAN_TTOST_SPL_Msk                          /*!<Schedule Phase Lock                      */

+

+/*****************  Bit definition for FDCAN_TURNA register  ********************/

+#define FDCAN_TURNA_NAV_Pos       (0U)

+#define FDCAN_TURNA_NAV_Msk       (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)           /*!< 0x0003FFFF */

+#define FDCAN_TURNA_NAV           FDCAN_TURNA_NAV_Msk                          /*!<Numerator Actual Value                   */

+

+/*****************  Bit definition for FDCAN_TTLGT register  ********************/

+#define FDCAN_TTLGT_LT_Pos        (0U)

+#define FDCAN_TTLGT_LT_Msk        (0xFFFFUL << FDCAN_TTLGT_LT_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTLGT_LT            FDCAN_TTLGT_LT_Msk                           /*!<Local Time                               */

+#define FDCAN_TTLGT_GT_Pos        (16U)

+#define FDCAN_TTLGT_GT_Msk        (0xFFFFUL << FDCAN_TTLGT_GT_Pos)             /*!< 0xFFFF0000 */

+#define FDCAN_TTLGT_GT            FDCAN_TTLGT_GT_Msk                           /*!<Global Time                              */

+

+/*****************  Bit definition for FDCAN_TTCTC register  ********************/

+#define FDCAN_TTCTC_CT_Pos        (0U)

+#define FDCAN_TTCTC_CT_Msk        (0xFFFFUL << FDCAN_TTCTC_CT_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTCTC_CT            FDCAN_TTCTC_CT_Msk                           /*!<Cycle Time                               */

+#define FDCAN_TTCTC_CC_Pos        (16U)

+#define FDCAN_TTCTC_CC_Msk        (0x3FUL << FDCAN_TTCTC_CC_Pos)               /*!< 0x003F0000 */

+#define FDCAN_TTCTC_CC            FDCAN_TTCTC_CC_Msk                           /*!<Cycle Count                              */

+

+/*****************  Bit definition for FDCAN_TTCPT register  ********************/

+#define FDCAN_TTCPT_CCV_Pos       (0U)

+#define FDCAN_TTCPT_CCV_Msk       (0x3FUL << FDCAN_TTCPT_CCV_Pos)              /*!< 0x0000003F */

+#define FDCAN_TTCPT_CCV           FDCAN_TTCPT_CCV_Msk                          /*!<Cycle Count Value                        */

+#define FDCAN_TTCPT_SWV_Pos       (16U)

+#define FDCAN_TTCPT_SWV_Msk       (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)            /*!< 0xFFFF0000 */

+#define FDCAN_TTCPT_SWV           FDCAN_TTCPT_SWV_Msk                          /*!<Stop Watch Value                         */

+

+/*****************  Bit definition for FDCAN_TTCSM register  ********************/

+#define FDCAN_TTCSM_CSM_Pos       (0U)

+#define FDCAN_TTCSM_CSM_Msk       (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)            /*!< 0x0000FFFF */

+#define FDCAN_TTCSM_CSM           FDCAN_TTCSM_CSM_Msk                          /*!<Cycle Sync Mark                          */

+

+/*****************  Bit definition for FDCAN_TTTS register  *********************/

+#define FDCAN_TTTS_SWTSEL_Pos     (0U)

+#define FDCAN_TTTS_SWTSEL_Msk     (0x3UL << FDCAN_TTTS_SWTSEL_Pos)             /*!< 0x00000003 */

+#define FDCAN_TTTS_SWTSEL         FDCAN_TTTS_SWTSEL_Msk                        /*!<Stop watch trigger input selection       */

+#define FDCAN_TTTS_EVTSEL_Pos     (4U)

+#define FDCAN_TTTS_EVTSEL_Msk     (0x3UL << FDCAN_TTTS_EVTSEL_Pos)             /*!< 0x00000030 */

+#define FDCAN_TTTS_EVTSEL         FDCAN_TTTS_EVTSEL_Msk                        /*!<Event trigger input selection            */

+

+/********************************************************************************/

+/*                                                                              */

+/*                      FDCANCCU (Clock Calibration unit)                       */

+/*                                                                              */

+/********************************************************************************/

+

+/*****************  Bit definition for FDCANCCU_CREL register  ******************/

+#define FDCANCCU_CREL_DAY_Pos        (0U)

+#define FDCANCCU_CREL_DAY_Msk        (0xFFUL << FDCANCCU_CREL_DAY_Pos)         /*!< 0x000000FF */

+#define FDCANCCU_CREL_DAY            FDCANCCU_CREL_DAY_Msk                     /*!<Timestamp Day                           */

+#define FDCANCCU_CREL_MON_Pos        (8U)

+#define FDCANCCU_CREL_MON_Msk        (0xFFUL << FDCANCCU_CREL_MON_Pos)         /*!< 0x0000FF00 */

+#define FDCANCCU_CREL_MON            FDCANCCU_CREL_MON_Msk                     /*!<Timestamp Month                         */

+#define FDCANCCU_CREL_YEAR_Pos       (16U)

+#define FDCANCCU_CREL_YEAR_Msk       (0xFUL << FDCANCCU_CREL_YEAR_Pos)         /*!< 0x000F0000 */

+#define FDCANCCU_CREL_YEAR           FDCANCCU_CREL_YEAR_Msk                    /*!<Timestamp Year                          */

+#define FDCANCCU_CREL_SUBSTEP_Pos    (20U)

+#define FDCANCCU_CREL_SUBSTEP_Msk    (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)      /*!< 0x00F00000 */

+#define FDCANCCU_CREL_SUBSTEP        FDCANCCU_CREL_SUBSTEP_Msk                 /*!<Sub-step of Core release                */

+#define FDCANCCU_CREL_STEP_Pos       (24U)

+#define FDCANCCU_CREL_STEP_Msk       (0xFUL << FDCANCCU_CREL_STEP_Pos)         /*!< 0x0F000000 */

+#define FDCANCCU_CREL_STEP           FDCANCCU_CREL_STEP_Msk                    /*!<Step of Core release                    */

+#define FDCANCCU_CREL_REL_Pos        (28U)

+#define FDCANCCU_CREL_REL_Msk        (0xFUL << FDCANCCU_CREL_REL_Pos)          /*!< 0xF0000000 */

+#define FDCANCCU_CREL_REL            FDCANCCU_CREL_REL_Msk                     /*!<Core release                            */

+

+/*****************  Bit definition for FDCANCCU_CCFG register  ******************/

+#define FDCANCCU_CCFG_TQBT_Pos       (0U)

+#define FDCANCCU_CCFG_TQBT_Msk       (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)        /*!< 0x0000001F */

+#define FDCANCCU_CCFG_TQBT           FDCANCCU_CCFG_TQBT_Msk                    /*!<Time Quanta per Bit Time                */

+#define FDCANCCU_CCFG_BCC_Pos        (6U)

+#define FDCANCCU_CCFG_BCC_Msk        (0x1UL << FDCANCCU_CCFG_BCC_Pos)          /*!< 0x00000040 */

+#define FDCANCCU_CCFG_BCC            FDCANCCU_CCFG_BCC_Msk                     /*!<Bypass Clock Calibration                */

+#define FDCANCCU_CCFG_CFL_Pos        (7U)

+#define FDCANCCU_CCFG_CFL_Msk        (0x1UL << FDCANCCU_CCFG_CFL_Pos)          /*!< 0x00000080 */

+#define FDCANCCU_CCFG_CFL            FDCANCCU_CCFG_CFL_Msk                     /*!<Calibration Field Length                */

+#define FDCANCCU_CCFG_OCPM_Pos       (8U)

+#define FDCANCCU_CCFG_OCPM_Msk       (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)        /*!< 0x0000FF00 */

+#define FDCANCCU_CCFG_OCPM           FDCANCCU_CCFG_OCPM_Msk                    /*!<Oscillator Clock Periods Minimum        */

+#define FDCANCCU_CCFG_CDIV_Pos       (16U)

+#define FDCANCCU_CCFG_CDIV_Msk       (0xFUL << FDCANCCU_CCFG_CDIV_Pos)         /*!< 0x000F0000 */

+#define FDCANCCU_CCFG_CDIV           FDCANCCU_CCFG_CDIV_Msk                    /*!<Clock Divider                           */

+#define FDCANCCU_CCFG_SWR_Pos        (31U)

+#define FDCANCCU_CCFG_SWR_Msk        (0x1UL << FDCANCCU_CCFG_SWR_Pos)          /*!< 0x80000000 */

+#define FDCANCCU_CCFG_SWR            FDCANCCU_CCFG_SWR_Msk                     /*!<Software Reset                          */

+

+/*****************  Bit definition for FDCANCCU_CSTAT register  *****************/

+#define FDCANCCU_CSTAT_OCPC_Pos      (0U)

+#define FDCANCCU_CSTAT_OCPC_Msk      (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)    /*!< 0x0003FFFF */

+#define FDCANCCU_CSTAT_OCPC          FDCANCCU_CSTAT_OCPC_Msk                   /*!<Oscillator Clock Period Counter        */

+#define FDCANCCU_CSTAT_TQC_Pos       (18U)

+#define FDCANCCU_CSTAT_TQC_Msk       (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)       /*!< 0x1FFC0000 */

+#define FDCANCCU_CSTAT_TQC           FDCANCCU_CSTAT_TQC_Msk                    /*!<Time Quanta Counter                    */

+#define FDCANCCU_CSTAT_CALS_Pos      (30U)

+#define FDCANCCU_CSTAT_CALS_Msk      (0x3UL << FDCANCCU_CSTAT_CALS_Pos)        /*!< 0xC0000000 */

+#define FDCANCCU_CSTAT_CALS          FDCANCCU_CSTAT_CALS_Msk                   /*!<Calibration State                      */

+

+/******************  Bit definition for FDCANCCU_CWD register  ******************/

+#define FDCANCCU_CWD_WDC_Pos         (0U)

+#define FDCANCCU_CWD_WDC_Msk         (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)        /*!< 0x0000FFFF */

+#define FDCANCCU_CWD_WDC             FDCANCCU_CWD_WDC_Msk                      /*!<Watchdog Configuration                 */

+#define FDCANCCU_CWD_WDV_Pos         (16U)

+#define FDCANCCU_CWD_WDV_Msk         (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)        /*!< 0xFFFF0000 */

+#define FDCANCCU_CWD_WDV             FDCANCCU_CWD_WDV_Msk                      /*!<Watchdog Value                         */

+

+/******************  Bit definition for FDCANCCU_IR register  *******************/

+#define FDCANCCU_IR_CWE_Pos          (0U)

+#define FDCANCCU_IR_CWE_Msk          (0x1UL << FDCANCCU_IR_CWE_Pos)            /*!< 0x00000001 */

+#define FDCANCCU_IR_CWE              FDCANCCU_IR_CWE_Msk                       /*!<Calibration Watchdog Event             */

+#define FDCANCCU_IR_CSC_Pos          (1U)

+#define FDCANCCU_IR_CSC_Msk          (0x1UL << FDCANCCU_IR_CSC_Pos)            /*!< 0x00000002 */

+#define FDCANCCU_IR_CSC              FDCANCCU_IR_CSC_Msk                       /*!<Calibration State Changed              */

+

+/******************  Bit definition for FDCANCCU_IE register  *******************/

+#define FDCANCCU_IE_CWEE_Pos         (0U)

+#define FDCANCCU_IE_CWEE_Msk         (0x1UL << FDCANCCU_IE_CWEE_Pos)           /*!< 0x00000001 */

+#define FDCANCCU_IE_CWEE             FDCANCCU_IE_CWEE_Msk                      /*!<Calibration Watchdog Event Enable      */

+#define FDCANCCU_IE_CSCE_Pos         (1U)

+#define FDCANCCU_IE_CSCE_Msk         (0x1UL << FDCANCCU_IE_CSCE_Pos)           /*!< 0x00000002 */

+#define FDCANCCU_IE_CSCE             FDCANCCU_IE_CSCE_Msk                      /*!<Calibration State Changed Enable       */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          HDMI-CEC (CEC)                                    */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for CEC_CR register  *********************/

+#define CEC_CR_CECEN_Pos         (0U)

+#define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                   /*!< 0x00000001 */

+#define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                                */

+#define CEC_CR_TXSOM_Pos         (1U)

+#define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                   /*!< 0x00000002 */

+#define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message                   */

+#define CEC_CR_TXEOM_Pos         (2U)

+#define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                   /*!< 0x00000004 */

+#define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message                     */

+

+/*******************  Bit definition for CEC_CFGR register  *******************/

+#define CEC_CFGR_SFT_Pos         (0U)

+#define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                   /*!< 0x00000007 */

+#define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time                      */

+#define CEC_CFGR_RXTOL_Pos       (3U)

+#define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                 /*!< 0x00000008 */

+#define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                             */

+#define CEC_CFGR_BRESTP_Pos      (4U)

+#define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                /*!< 0x00000010 */

+#define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                               */

+#define CEC_CFGR_BREGEN_Pos      (5U)

+#define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                /*!< 0x00000020 */

+#define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation           */

+#define CEC_CFGR_LBPEGEN_Pos     (6U)

+#define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)               /*!< 0x00000040 */

+#define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error generation      */

+#define CEC_CFGR_SFTOPT_Pos      (8U)

+#define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                /*!< 0x00000100 */

+#define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional             */

+#define CEC_CFGR_BRDNOGEN_Pos    (7U)

+#define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)              /*!< 0x00000080 */

+#define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No error generation         */

+#define CEC_CFGR_OAR_Pos         (16U)

+#define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                /*!< 0x7FFF0000 */

+#define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                           */

+#define CEC_CFGR_LSTN_Pos        (31U)

+#define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                  /*!< 0x80000000 */

+#define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                           */

+

+/*******************  Bit definition for CEC_TXDR register  *******************/

+#define CEC_TXDR_TXD_Pos         (0U)

+#define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                  /*!< 0x000000FF */

+#define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                               */

+

+/*******************  Bit definition for CEC_RXDR register  *******************/

+#define CEC_RXDR_RXD_Pos         (0U)

+#define CEC_RXDR_RXD_Msk         (0xFFUL << CEC_RXDR_RXD_Pos)                  /*!< 0x000000FF */

+#define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                              /*!< CEC Rx Data                               */

+

+/*******************  Bit definition for CEC_ISR register  ********************/

+#define CEC_ISR_RXBR_Pos         (0U)

+#define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                   /*!< 0x00000001 */

+#define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                      */

+#define CEC_ISR_RXEND_Pos        (1U)

+#define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                  /*!< 0x00000002 */

+#define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                      */

+#define CEC_ISR_RXOVR_Pos        (2U)

+#define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                  /*!< 0x00000004 */

+#define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                            */

+#define CEC_ISR_BRE_Pos          (3U)

+#define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                    /*!< 0x00000008 */

+#define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                   */

+#define CEC_ISR_SBPE_Pos         (4U)

+#define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                   /*!< 0x00000010 */

+#define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error             */

+#define CEC_ISR_LBPE_Pos         (5U)

+#define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                   /*!< 0x00000020 */

+#define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error              */

+#define CEC_ISR_RXACKE_Pos       (6U)

+#define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                 /*!< 0x00000040 */

+#define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge                */

+#define CEC_ISR_ARBLST_Pos       (7U)

+#define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                 /*!< 0x00000080 */

+#define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                      */

+#define CEC_ISR_TXBR_Pos         (8U)

+#define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                   /*!< 0x00000100 */

+#define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                       */

+#define CEC_ISR_TXEND_Pos        (9U)

+#define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                  /*!< 0x00000200 */

+#define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                   */

+#define CEC_ISR_TXUDR_Pos        (10U)

+#define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                  /*!< 0x00000400 */

+#define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                    */

+#define CEC_ISR_TXERR_Pos        (11U)

+#define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                  /*!< 0x00000800 */

+#define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                              */

+#define CEC_ISR_TXACKE_Pos       (12U)

+#define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                 /*!< 0x00001000 */

+#define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge                */

+

+/*******************  Bit definition for CEC_IER register  ********************/

+#define CEC_IER_RXBRIE_Pos       (0U)

+#define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                 /*!< 0x00000001 */

+#define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable            */

+#define CEC_IER_RXENDIE_Pos      (1U)

+#define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                /*!< 0x00000002 */

+#define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable            */

+#define CEC_IER_RXOVRIE_Pos      (2U)

+#define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                /*!< 0x00000004 */

+#define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable                  */

+#define CEC_IER_BREIE_Pos        (3U)

+#define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                  /*!< 0x00000008 */

+#define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable         */

+#define CEC_IER_SBPEIE_Pos       (4U)

+#define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                 /*!< 0x00000010 */

+#define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable   */

+#define CEC_IER_LBPEIE_Pos       (5U)

+#define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                 /*!< 0x00000020 */

+#define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable    */

+#define CEC_IER_RXACKEIE_Pos     (6U)

+#define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)               /*!< 0x00000040 */

+#define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable      */

+#define CEC_IER_ARBLSTIE_Pos     (7U)

+#define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)               /*!< 0x00000080 */

+#define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable            */

+#define CEC_IER_TXBRIE_Pos       (8U)

+#define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                 /*!< 0x00000100 */

+#define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable            */

+#define CEC_IER_TXENDIE_Pos      (9U)

+#define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                /*!< 0x00000200 */

+#define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable         */

+#define CEC_IER_TXUDRIE_Pos      (10U)

+#define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                /*!< 0x00000400 */

+#define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable          */

+#define CEC_IER_TXERRIE_Pos      (11U)

+#define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                /*!< 0x00000800 */

+#define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                    */

+#define CEC_IER_TXACKEIE_Pos     (12U)

+#define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)               /*!< 0x00001000 */

+#define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable      */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          CRC calculation unit                              */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for CRC_DR register  *********************/

+#define CRC_DR_DR_Pos            (0U)

+#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */

+#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */

+

+/*******************  Bit definition for CRC_IDR register  ********************/

+#define CRC_IDR_IDR_Pos          (0U)

+#define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */

+#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */

+

+/********************  Bit definition for CRC_CR register  ********************/

+#define CRC_CR_RESET_Pos         (0U)

+#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */

+#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */

+#define CRC_CR_POLYSIZE_Pos      (3U)

+#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */

+#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */

+#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */

+#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */

+#define CRC_CR_REV_IN_Pos        (5U)

+#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */

+#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */

+#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */

+#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */

+#define CRC_CR_REV_OUT_Pos       (7U)

+#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */

+#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */

+

+/*******************  Bit definition for CRC_INIT register  *******************/

+#define CRC_INIT_INIT_Pos        (0U)

+#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */

+#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */

+

+/*******************  Bit definition for CRC_POL register  ********************/

+#define CRC_POL_POL_Pos          (0U)

+#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */

+#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          CRS Clock Recovery System                         */

+/******************************************************************************/

+

+/*******************  Bit definition for CRS_CR register  *********************/

+#define CRS_CR_SYNCOKIE_Pos       (0U)

+#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */

+#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */

+#define CRS_CR_SYNCWARNIE_Pos     (1U)

+#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */

+#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */

+#define CRS_CR_ERRIE_Pos          (2U)

+#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */

+#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */

+#define CRS_CR_ESYNCIE_Pos        (3U)

+#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */

+#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */

+#define CRS_CR_CEN_Pos            (5U)

+#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */

+#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */

+#define CRS_CR_AUTOTRIMEN_Pos     (6U)

+#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */

+#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */

+#define CRS_CR_SWSYNC_Pos         (7U)

+#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */

+#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */

+#define CRS_CR_TRIM_Pos           (8U)

+#define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00003F00 */

+#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */

+

+/*******************  Bit definition for CRS_CFGR register  *********************/

+#define CRS_CFGR_RELOAD_Pos       (0U)

+#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */

+#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */

+#define CRS_CFGR_FELIM_Pos        (16U)

+#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */

+#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */

+

+#define CRS_CFGR_SYNCDIV_Pos      (24U)

+#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */

+#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */

+#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */

+#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */

+#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */

+

+#define CRS_CFGR_SYNCSRC_Pos      (28U)

+#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */

+#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */

+#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */

+#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */

+

+#define CRS_CFGR_SYNCPOL_Pos      (31U)

+#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */

+#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */

+

+/*******************  Bit definition for CRS_ISR register  *********************/

+#define CRS_ISR_SYNCOKF_Pos       (0U)

+#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */

+#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */

+#define CRS_ISR_SYNCWARNF_Pos     (1U)

+#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */

+#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */

+#define CRS_ISR_ERRF_Pos          (2U)

+#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */

+#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */

+#define CRS_ISR_ESYNCF_Pos        (3U)

+#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */

+#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */

+#define CRS_ISR_SYNCERR_Pos       (8U)

+#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */

+#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */

+#define CRS_ISR_SYNCMISS_Pos      (9U)

+#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */

+#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */

+#define CRS_ISR_TRIMOVF_Pos       (10U)

+#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */

+#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */

+#define CRS_ISR_FEDIR_Pos         (15U)

+#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */

+#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */

+#define CRS_ISR_FECAP_Pos         (16U)

+#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */

+#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */

+

+/*******************  Bit definition for CRS_ICR register  *********************/

+#define CRS_ICR_SYNCOKC_Pos       (0U)

+#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */

+#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */

+#define CRS_ICR_SYNCWARNC_Pos     (1U)

+#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */

+#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */

+#define CRS_ICR_ERRC_Pos          (2U)

+#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */

+#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */

+#define CRS_ICR_ESYNCC_Pos        (3U)

+#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */

+#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            Crypto Processor                                */

+/*                                                                            */

+/******************************************************************************/

+/******************* Bits definition for CRYP_CR register  ********************/

+#define CRYP_CR_ALGODIR_Pos              (2U)

+#define CRYP_CR_ALGODIR_Msk              (0x1UL << CRYP_CR_ALGODIR_Pos)        /*!< 0x00000004 */

+#define CRYP_CR_ALGODIR                  CRYP_CR_ALGODIR_Msk

+

+#define CRYP_CR_ALGOMODE_Pos             (3U)

+#define CRYP_CR_ALGOMODE_Msk             (0x10007UL << CRYP_CR_ALGOMODE_Pos)   /*!< 0x00080038 */

+#define CRYP_CR_ALGOMODE                 CRYP_CR_ALGOMODE_Msk

+#define CRYP_CR_ALGOMODE_0               (0x00001UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000008 */

+#define CRYP_CR_ALGOMODE_1               (0x00002UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000010 */

+#define CRYP_CR_ALGOMODE_2               (0x00004UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000020 */

+#define CRYP_CR_ALGOMODE_TDES_ECB        ((uint32_t)0x00000000)

+#define CRYP_CR_ALGOMODE_TDES_CBC_Pos    (3U)

+#define CRYP_CR_ALGOMODE_TDES_CBC_Msk    (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */

+#define CRYP_CR_ALGOMODE_TDES_CBC        CRYP_CR_ALGOMODE_TDES_CBC_Msk

+#define CRYP_CR_ALGOMODE_DES_ECB_Pos     (4U)

+#define CRYP_CR_ALGOMODE_DES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_DES_ECB_Pos) /*!< 0x00000010 */

+#define CRYP_CR_ALGOMODE_DES_ECB         CRYP_CR_ALGOMODE_DES_ECB_Msk

+#define CRYP_CR_ALGOMODE_DES_CBC_Pos     (3U)

+#define CRYP_CR_ALGOMODE_DES_CBC_Msk     (0x3UL << CRYP_CR_ALGOMODE_DES_CBC_Pos) /*!< 0x00000018 */

+#define CRYP_CR_ALGOMODE_DES_CBC         CRYP_CR_ALGOMODE_DES_CBC_Msk

+#define CRYP_CR_ALGOMODE_AES_ECB_Pos     (5U)

+#define CRYP_CR_ALGOMODE_AES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */

+#define CRYP_CR_ALGOMODE_AES_ECB         CRYP_CR_ALGOMODE_AES_ECB_Msk

+#define CRYP_CR_ALGOMODE_AES_CBC_Pos     (3U)

+#define CRYP_CR_ALGOMODE_AES_CBC_Msk     (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */

+#define CRYP_CR_ALGOMODE_AES_CBC         CRYP_CR_ALGOMODE_AES_CBC_Msk

+#define CRYP_CR_ALGOMODE_AES_CTR_Pos     (4U)

+#define CRYP_CR_ALGOMODE_AES_CTR_Msk     (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */

+#define CRYP_CR_ALGOMODE_AES_CTR         CRYP_CR_ALGOMODE_AES_CTR_Msk

+#define CRYP_CR_ALGOMODE_AES_KEY_Pos     (3U)

+#define CRYP_CR_ALGOMODE_AES_KEY_Msk     (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */

+#define CRYP_CR_ALGOMODE_AES_KEY         CRYP_CR_ALGOMODE_AES_KEY_Msk

+#define CRYP_CR_ALGOMODE_AES_GCM_Pos     (19U)

+#define CRYP_CR_ALGOMODE_AES_GCM_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_GCM_Pos) /*!< 0x00080000 */

+#define CRYP_CR_ALGOMODE_AES_GCM         CRYP_CR_ALGOMODE_AES_GCM_Msk

+#define CRYP_CR_ALGOMODE_AES_CCM_Pos     (3U)

+#define CRYP_CR_ALGOMODE_AES_CCM_Msk     (0x10001UL << CRYP_CR_ALGOMODE_AES_CCM_Pos) /*!< 0x00080008 */

+#define CRYP_CR_ALGOMODE_AES_CCM         CRYP_CR_ALGOMODE_AES_CCM_Msk

+

+#define CRYP_CR_DATATYPE_Pos             (6U)

+#define CRYP_CR_DATATYPE_Msk             (0x3UL << CRYP_CR_DATATYPE_Pos)       /*!< 0x000000C0 */

+#define CRYP_CR_DATATYPE                 CRYP_CR_DATATYPE_Msk

+#define CRYP_CR_DATATYPE_0               (0x1UL << CRYP_CR_DATATYPE_Pos)        /*!< 0x00000040 */

+#define CRYP_CR_DATATYPE_1               (0x2UL << CRYP_CR_DATATYPE_Pos)        /*!< 0x00000080 */

+#define CRYP_CR_KEYSIZE_Pos              (8U)

+#define CRYP_CR_KEYSIZE_Msk              (0x3UL << CRYP_CR_KEYSIZE_Pos)        /*!< 0x00000300 */

+#define CRYP_CR_KEYSIZE                  CRYP_CR_KEYSIZE_Msk

+#define CRYP_CR_KEYSIZE_0                (0x1UL << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000100 */

+#define CRYP_CR_KEYSIZE_1                (0x2UL << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000200 */

+#define CRYP_CR_FFLUSH_Pos               (14U)

+#define CRYP_CR_FFLUSH_Msk               (0x1UL << CRYP_CR_FFLUSH_Pos)         /*!< 0x00004000 */

+#define CRYP_CR_FFLUSH                   CRYP_CR_FFLUSH_Msk

+#define CRYP_CR_CRYPEN_Pos               (15U)

+#define CRYP_CR_CRYPEN_Msk               (0x1UL << CRYP_CR_CRYPEN_Pos)         /*!< 0x00008000 */

+#define CRYP_CR_CRYPEN                   CRYP_CR_CRYPEN_Msk

+

+#define CRYP_CR_GCM_CCMPH_Pos            (16U)

+#define CRYP_CR_GCM_CCMPH_Msk            (0x3UL << CRYP_CR_GCM_CCMPH_Pos)      /*!< 0x00030000 */

+#define CRYP_CR_GCM_CCMPH                CRYP_CR_GCM_CCMPH_Msk

+#define CRYP_CR_GCM_CCMPH_0              (0x1UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00010000 */

+#define CRYP_CR_GCM_CCMPH_1              (0x2UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00020000 */

+#define CRYP_CR_ALGOMODE_3               ((uint32_t)0x00080000)

+#define CRYP_CR_NPBLB_Pos                (20U)

+#define CRYP_CR_NPBLB_Msk                (0xFUL << CRYP_CR_NPBLB_Pos)          /*!< 0x00F00000 */

+#define CRYP_CR_NPBLB                    CRYP_CR_NPBLB_Msk

+

+/****************** Bits definition for CRYP_SR register  *********************/

+#define CRYP_SR_IFEM_Pos                 (0U)

+#define CRYP_SR_IFEM_Msk                 (0x1UL << CRYP_SR_IFEM_Pos)           /*!< 0x00000001 */

+#define CRYP_SR_IFEM                     CRYP_SR_IFEM_Msk

+#define CRYP_SR_IFNF_Pos                 (1U)

+#define CRYP_SR_IFNF_Msk                 (0x1UL << CRYP_SR_IFNF_Pos)           /*!< 0x00000002 */

+#define CRYP_SR_IFNF                     CRYP_SR_IFNF_Msk

+#define CRYP_SR_OFNE_Pos                 (2U)

+#define CRYP_SR_OFNE_Msk                 (0x1UL << CRYP_SR_OFNE_Pos)           /*!< 0x00000004 */

+#define CRYP_SR_OFNE                     CRYP_SR_OFNE_Msk

+#define CRYP_SR_OFFU_Pos                 (3U)

+#define CRYP_SR_OFFU_Msk                 (0x1UL << CRYP_SR_OFFU_Pos)           /*!< 0x00000008 */

+#define CRYP_SR_OFFU                     CRYP_SR_OFFU_Msk

+#define CRYP_SR_BUSY_Pos                 (4U)

+#define CRYP_SR_BUSY_Msk                 (0x1UL << CRYP_SR_BUSY_Pos)           /*!< 0x00000010 */

+#define CRYP_SR_BUSY                     CRYP_SR_BUSY_Msk

+/****************** Bits definition for CRYP_DMACR register  ******************/

+#define CRYP_DMACR_DIEN_Pos              (0U)

+#define CRYP_DMACR_DIEN_Msk              (0x1UL << CRYP_DMACR_DIEN_Pos)        /*!< 0x00000001 */

+#define CRYP_DMACR_DIEN                  CRYP_DMACR_DIEN_Msk

+#define CRYP_DMACR_DOEN_Pos              (1U)

+#define CRYP_DMACR_DOEN_Msk              (0x1UL << CRYP_DMACR_DOEN_Pos)        /*!< 0x00000002 */

+#define CRYP_DMACR_DOEN                  CRYP_DMACR_DOEN_Msk

+/*****************  Bits definition for CRYP_IMSCR register  ******************/

+#define CRYP_IMSCR_INIM_Pos              (0U)

+#define CRYP_IMSCR_INIM_Msk              (0x1UL << CRYP_IMSCR_INIM_Pos)        /*!< 0x00000001 */

+#define CRYP_IMSCR_INIM                  CRYP_IMSCR_INIM_Msk

+#define CRYP_IMSCR_OUTIM_Pos             (1U)

+#define CRYP_IMSCR_OUTIM_Msk             (0x1UL << CRYP_IMSCR_OUTIM_Pos)       /*!< 0x00000002 */

+#define CRYP_IMSCR_OUTIM                 CRYP_IMSCR_OUTIM_Msk

+/****************** Bits definition for CRYP_RISR register  *******************/

+#define CRYP_RISR_INRIS_Pos              (0U)

+#define CRYP_RISR_INRIS_Msk              (0x1UL << CRYP_RISR_INRIS_Pos)        /*!< 0x00000001 */

+#define CRYP_RISR_INRIS                  CRYP_RISR_INRIS_Msk

+#define CRYP_RISR_OUTRIS_Pos             (1U)

+#define CRYP_RISR_OUTRIS_Msk             (0x1UL << CRYP_RISR_OUTRIS_Pos)       /*!< 0x00000002 */

+#define CRYP_RISR_OUTRIS                 CRYP_RISR_OUTRIS_Msk

+/****************** Bits definition for CRYP_MISR register  *******************/

+#define CRYP_MISR_INMIS_Pos              (0U)

+#define CRYP_MISR_INMIS_Msk              (0x1UL << CRYP_MISR_INMIS_Pos)        /*!< 0x00000001 */

+#define CRYP_MISR_INMIS                  CRYP_MISR_INMIS_Msk

+#define CRYP_MISR_OUTMIS_Pos             (1U)

+#define CRYP_MISR_OUTMIS_Msk             (0x1UL << CRYP_MISR_OUTMIS_Pos)       /*!< 0x00000002 */

+#define CRYP_MISR_OUTMIS                 CRYP_MISR_OUTMIS_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                      Digital to Analog Converter                           */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for DAC_CR register  ********************/

+#define DAC_CR_EN1_Pos              (0U)

+#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */

+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */

+#define DAC_CR_TEN1_Pos             (1U)

+#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */

+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */

+

+#define DAC_CR_TSEL1_Pos            (2U)

+#define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */

+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */

+#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000004 */

+#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */

+#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */

+#define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */

+

+

+#define DAC_CR_WAVE1_Pos            (6U)

+#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */

+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */

+#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */

+#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */

+

+#define DAC_CR_MAMP1_Pos            (8U)

+#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */

+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */

+#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */

+#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */

+#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */

+#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */

+

+#define DAC_CR_DMAEN1_Pos           (12U)

+#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */

+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */

+#define DAC_CR_DMAUDRIE1_Pos        (13U)

+#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */

+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/

+#define DAC_CR_CEN1_Pos             (14U)

+#define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */

+#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/

+

+#define DAC_CR_EN2_Pos              (16U)

+#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */

+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */

+#define DAC_CR_TEN2_Pos             (17U)

+#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */

+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */

+

+#define DAC_CR_TSEL2_Pos            (18U)

+#define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */

+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */

+#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00040000 */

+#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */

+#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */

+#define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */

+

+

+#define DAC_CR_WAVE2_Pos            (22U)

+#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */

+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */

+#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */

+#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */

+

+#define DAC_CR_MAMP2_Pos            (24U)

+#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */

+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */

+#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */

+#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */

+#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */

+#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */

+

+#define DAC_CR_DMAEN2_Pos           (28U)

+#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */

+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */

+#define DAC_CR_DMAUDRIE2_Pos        (29U)

+#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */

+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/

+#define DAC_CR_CEN2_Pos             (30U)

+#define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */

+#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/

+

+/*****************  Bit definition for DAC_SWTRIGR register  ******************/

+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)

+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */

+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */

+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)

+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */

+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */

+

+/*****************  Bit definition for DAC_DHR12R1 register  ******************/

+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)

+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12L1 register  ******************/

+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)

+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8R1 register  ******************/

+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)

+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12R2 register  ******************/

+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)

+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12L2 register  ******************/

+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)

+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8R2 register  ******************/

+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)

+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12RD register  ******************/

+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)

+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */

+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)

+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */

+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12LD register  ******************/

+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)

+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */

+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)

+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */

+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8RD register  ******************/

+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)

+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */

+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)

+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */

+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */

+

+/*******************  Bit definition for DAC_DOR1 register  *******************/

+#define DAC_DOR1_DACC1DOR_Pos       (0U)

+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */

+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */

+

+/*******************  Bit definition for DAC_DOR2 register  *******************/

+#define DAC_DOR2_DACC2DOR_Pos       (0U)

+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */

+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */

+

+/********************  Bit definition for DAC_SR register  ********************/

+#define DAC_SR_DMAUDR1_Pos          (13U)

+#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */

+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */

+#define DAC_SR_CAL_FLAG1_Pos        (14U)

+#define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */

+#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */

+#define DAC_SR_BWST1_Pos            (15U)

+#define DAC_SR_BWST1_Msk            (0x4001UL << DAC_SR_BWST1_Pos)             /*!< 0x20008000 */

+#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */

+

+#define DAC_SR_DMAUDR2_Pos          (29U)

+#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */

+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */

+#define DAC_SR_CAL_FLAG2_Pos        (30U)

+#define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */

+#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */

+#define DAC_SR_BWST2_Pos            (31U)

+#define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */

+#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */

+

+/*******************  Bit definition for DAC_CCR register  ********************/

+#define DAC_CCR_OTRIM1_Pos          (0U)

+#define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */

+#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */

+#define DAC_CCR_OTRIM2_Pos          (16U)

+#define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */

+#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */

+

+/*******************  Bit definition for DAC_MCR register  *******************/

+#define DAC_MCR_MODE1_Pos           (0U)

+#define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */

+#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */

+#define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */

+#define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */

+#define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */

+

+#define DAC_MCR_MODE2_Pos           (16U)

+#define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */

+#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */

+#define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */

+#define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */

+#define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */

+

+/******************  Bit definition for DAC_SHSR1 register  ******************/

+#define DAC_SHSR1_TSAMPLE1_Pos      (0U)

+#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */

+#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */

+

+/******************  Bit definition for DAC_SHSR2 register  ******************/

+#define DAC_SHSR2_TSAMPLE2_Pos      (0U)

+#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */

+#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */

+

+/******************  Bit definition for DAC_SHHR register  ******************/

+#define DAC_SHHR_THOLD1_Pos         (0U)

+#define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */

+#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */

+#define DAC_SHHR_THOLD2_Pos         (16U)

+#define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */

+#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */

+

+/******************  Bit definition for DAC_SHRR register  ******************/

+#define DAC_SHRR_TREFRESH1_Pos      (0U)

+#define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */

+#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */

+#define DAC_SHRR_TREFRESH2_Pos      (16U)

+#define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */

+#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    DCMI                                    */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DCMI_CR register  ******************/

+#define DCMI_CR_CAPTURE_Pos        (0U)

+#define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)              /*!< 0x00000001 */

+#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk

+#define DCMI_CR_CM_Pos             (1U)

+#define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                   /*!< 0x00000002 */

+#define DCMI_CR_CM                 DCMI_CR_CM_Msk

+#define DCMI_CR_CROP_Pos           (2U)

+#define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                 /*!< 0x00000004 */

+#define DCMI_CR_CROP               DCMI_CR_CROP_Msk

+#define DCMI_CR_JPEG_Pos           (3U)

+#define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                 /*!< 0x00000008 */

+#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk

+#define DCMI_CR_ESS_Pos            (4U)

+#define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                  /*!< 0x00000010 */

+#define DCMI_CR_ESS                DCMI_CR_ESS_Msk

+#define DCMI_CR_PCKPOL_Pos         (5U)

+#define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)               /*!< 0x00000020 */

+#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk

+#define DCMI_CR_HSPOL_Pos          (6U)

+#define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                /*!< 0x00000040 */

+#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk

+#define DCMI_CR_VSPOL_Pos          (7U)

+#define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */

+#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk

+#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)

+#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)

+#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)

+#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)

+#define DCMI_CR_CRE_Pos            (12U)

+#define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */

+#define DCMI_CR_CRE                DCMI_CR_CRE_Msk

+#define DCMI_CR_ENABLE_Pos         (14U)

+#define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)               /*!< 0x00004000 */

+#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk

+#define DCMI_CR_BSM_Pos            (16U)

+#define DCMI_CR_BSM_Msk            (0x3UL << DCMI_CR_BSM_Pos)                  /*!< 0x00030000 */

+#define DCMI_CR_BSM                DCMI_CR_BSM_Msk

+#define DCMI_CR_BSM_0              (0x1UL << DCMI_CR_BSM_Pos)                   /*!< 0x00010000 */

+#define DCMI_CR_BSM_1              (0x2UL << DCMI_CR_BSM_Pos)                   /*!< 0x00020000 */

+#define DCMI_CR_OEBS_Pos           (18U)

+#define DCMI_CR_OEBS_Msk           (0x1UL << DCMI_CR_OEBS_Pos)                 /*!< 0x00040000 */

+#define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk

+#define DCMI_CR_LSM_Pos            (19U)

+#define DCMI_CR_LSM_Msk            (0x1UL << DCMI_CR_LSM_Pos)                  /*!< 0x00080000 */

+#define DCMI_CR_LSM                DCMI_CR_LSM_Msk

+#define DCMI_CR_OELS_Pos           (20U)

+#define DCMI_CR_OELS_Msk           (0x1UL << DCMI_CR_OELS_Pos)                 /*!< 0x00100000 */

+#define DCMI_CR_OELS               DCMI_CR_OELS_Msk

+

+/********************  Bits definition for DCMI_SR register  ******************/

+#define DCMI_SR_HSYNC_Pos          (0U)

+#define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                /*!< 0x00000001 */

+#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk

+#define DCMI_SR_VSYNC_Pos          (1U)

+#define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                /*!< 0x00000002 */

+#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk

+#define DCMI_SR_FNE_Pos            (2U)

+#define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                  /*!< 0x00000004 */

+#define DCMI_SR_FNE                DCMI_SR_FNE_Msk

+

+/********************  Bits definition for DCMI_RIS register   ****************/

+#define DCMI_RIS_FRAME_RIS_Pos     (0U)

+#define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)           /*!< 0x00000001 */

+#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk

+#define DCMI_RIS_OVR_RIS_Pos       (1U)

+#define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)             /*!< 0x00000002 */

+#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk

+#define DCMI_RIS_ERR_RIS_Pos       (2U)

+#define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)             /*!< 0x00000004 */

+#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk

+#define DCMI_RIS_VSYNC_RIS_Pos     (3U)

+#define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)           /*!< 0x00000008 */

+#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk

+#define DCMI_RIS_LINE_RIS_Pos      (4U)

+#define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)            /*!< 0x00000010 */

+#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk

+

+/********************  Bits definition for DCMI_IER register  *****************/

+#define DCMI_IER_FRAME_IE_Pos      (0U)

+#define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)            /*!< 0x00000001 */

+#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk

+#define DCMI_IER_OVR_IE_Pos        (1U)

+#define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)              /*!< 0x00000002 */

+#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk

+#define DCMI_IER_ERR_IE_Pos        (2U)

+#define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)              /*!< 0x00000004 */

+#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk

+#define DCMI_IER_VSYNC_IE_Pos      (3U)

+#define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)            /*!< 0x00000008 */

+#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk

+#define DCMI_IER_LINE_IE_Pos       (4U)

+#define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)             /*!< 0x00000010 */

+#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk

+

+

+/********************  Bits definition for DCMI_MIS register  *****************/

+#define DCMI_MIS_FRAME_MIS_Pos     (0U)

+#define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)           /*!< 0x00000001 */

+#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk

+#define DCMI_MIS_OVR_MIS_Pos       (1U)

+#define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)             /*!< 0x00000002 */

+#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk

+#define DCMI_MIS_ERR_MIS_Pos       (2U)

+#define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)             /*!< 0x00000004 */

+#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk

+#define DCMI_MIS_VSYNC_MIS_Pos     (3U)

+#define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)           /*!< 0x00000008 */

+#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk

+#define DCMI_MIS_LINE_MIS_Pos      (4U)

+#define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)            /*!< 0x00000010 */

+#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk

+

+

+/********************  Bits definition for DCMI_ICR register  *****************/

+#define DCMI_ICR_FRAME_ISC_Pos     (0U)

+#define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)           /*!< 0x00000001 */

+#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk

+#define DCMI_ICR_OVR_ISC_Pos       (1U)

+#define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)             /*!< 0x00000002 */

+#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk

+#define DCMI_ICR_ERR_ISC_Pos       (2U)

+#define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)             /*!< 0x00000004 */

+#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk

+#define DCMI_ICR_VSYNC_ISC_Pos     (3U)

+#define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)           /*!< 0x00000008 */

+#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk

+#define DCMI_ICR_LINE_ISC_Pos      (4U)

+#define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)            /*!< 0x00000010 */

+#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk

+

+

+/********************  Bits definition for DCMI_ESCR register  ******************/

+#define DCMI_ESCR_FSC_Pos          (0U)

+#define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)               /*!< 0x000000FF */

+#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk

+#define DCMI_ESCR_LSC_Pos          (8U)

+#define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)               /*!< 0x0000FF00 */

+#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk

+#define DCMI_ESCR_LEC_Pos          (16U)

+#define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)               /*!< 0x00FF0000 */

+#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk

+#define DCMI_ESCR_FEC_Pos          (24U)

+#define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)               /*!< 0xFF000000 */

+#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk

+

+/********************  Bits definition for DCMI_ESUR register  ******************/

+#define DCMI_ESUR_FSU_Pos          (0U)

+#define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)               /*!< 0x000000FF */

+#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk

+#define DCMI_ESUR_LSU_Pos          (8U)

+#define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)               /*!< 0x0000FF00 */

+#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk

+#define DCMI_ESUR_LEU_Pos          (16U)

+#define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)               /*!< 0x00FF0000 */

+#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk

+#define DCMI_ESUR_FEU_Pos          (24U)

+#define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)               /*!< 0xFF000000 */

+#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk

+

+/********************  Bits definition for DCMI_CWSTRT register  ******************/

+#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)

+#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)       /*!< 0x00003FFF */

+#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk

+#define DCMI_CWSTRT_VST_Pos        (16U)

+#define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)           /*!< 0x1FFF0000 */

+#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk

+

+/********************  Bits definition for DCMI_CWSIZE register  ******************/

+#define DCMI_CWSIZE_CAPCNT_Pos     (0U)

+#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)        /*!< 0x00003FFF */

+#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk

+#define DCMI_CWSIZE_VLINE_Pos      (16U)

+#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)         /*!< 0x3FFF0000 */

+#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk

+

+/********************  Bits definition for DCMI_DR register  ******************/

+#define DCMI_DR_BYTE0_Pos          (0U)

+#define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)               /*!< 0x000000FF */

+#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk

+#define DCMI_DR_BYTE1_Pos          (8U)

+#define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)               /*!< 0x0000FF00 */

+#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk

+#define DCMI_DR_BYTE2_Pos          (16U)

+#define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)               /*!< 0x00FF0000 */

+#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk

+#define DCMI_DR_BYTE3_Pos          (24U)

+#define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)               /*!< 0xFF000000 */

+#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                 Digital Filter for Sigma Delta Modulators                  */

+/*                                                                            */

+/******************************************************************************/

+

+/****************   DFSDM channel configuration registers  ********************/

+

+/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/

+#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)

+#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)   /*!< 0x80000000 */

+#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */

+#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)

+#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)  /*!< 0x40000000 */

+#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */

+#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)

+#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */

+#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */

+#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)

+#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x0000C000 */

+#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */

+#define DFSDM_CHCFGR1_DATPACK_1         (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */

+#define DFSDM_CHCFGR1_DATPACK_0         (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */

+#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)

+#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00003000 */

+#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */

+#define DFSDM_CHCFGR1_DATMPX_1          (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */

+#define DFSDM_CHCFGR1_DATMPX_0          (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */

+#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)

+#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)   /*!< 0x00000100 */

+#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */

+#define DFSDM_CHCFGR1_CHEN_Pos          (7U)

+#define DFSDM_CHCFGR1_CHEN_Msk          (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)      /*!< 0x00000080 */

+#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */

+#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)

+#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)    /*!< 0x00000040 */

+#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */

+#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)

+#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)     /*!< 0x00000020 */

+#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */

+#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)

+#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x0000000C */

+#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */

+#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */

+#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */

+#define DFSDM_CHCFGR1_SITP_Pos          (0U)

+#define DFSDM_CHCFGR1_SITP_Msk          (0x3UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000003 */

+#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */

+#define DFSDM_CHCFGR1_SITP_1            (0x2UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */

+#define DFSDM_CHCFGR1_SITP_0            (0x1UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */

+

+/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/

+#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)

+#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */

+#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)

+#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)    /*!< 0x000000F8 */

+#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */

+

+/******************  Bit definition for DFSDM_CHAWSCDR register *****************/

+#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)

+#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00C00000 */

+#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */

+#define DFSDM_CHAWSCDR_AWFORD_1         (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */

+#define DFSDM_CHAWSCDR_AWFORD_0         (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */

+#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)

+#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)  /*!< 0x001F0000 */

+#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */

+#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)

+#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)    /*!< 0x0000F000 */

+#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */

+#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)

+#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)    /*!< 0x000000FF */

+#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */

+

+/****************  Bit definition for DFSDM_CHWDATR register *******************/

+#define DFSDM_CHWDATR_WDATA_Pos         (0U)

+#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)  /*!< 0x0000FFFF */

+#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */

+

+/****************  Bit definition for DFSDM_CHDATINR register *****************/

+#define DFSDM_CHDATINR_INDAT0_Pos       (0U)

+#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */

+#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */

+#define DFSDM_CHDATINR_INDAT1_Pos       (16U)

+#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */

+#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */

+

+/************************   DFSDM module registers  ****************************/

+

+/********************  Bit definition for DFSDM_FLTCR1 register *******************/

+#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)

+#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)     /*!< 0x40000000 */

+#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */

+#define DFSDM_FLTCR1_FAST_Pos           (29U)

+#define DFSDM_FLTCR1_FAST_Msk           (0x1UL << DFSDM_FLTCR1_FAST_Pos)       /*!< 0x20000000 */

+#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */

+#define DFSDM_FLTCR1_RCH_Pos            (24U)

+#define DFSDM_FLTCR1_RCH_Msk            (0x7UL << DFSDM_FLTCR1_RCH_Pos)        /*!< 0x07000000 */

+#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */

+#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)

+#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)     /*!< 0x00200000 */

+#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */

+#define DFSDM_FLTCR1_RSYNC_Pos          (19U)

+#define DFSDM_FLTCR1_RSYNC_Msk          (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)      /*!< 0x00080000 */

+#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */

+#define DFSDM_FLTCR1_RCONT_Pos          (18U)

+#define DFSDM_FLTCR1_RCONT_Msk          (0x1UL << DFSDM_FLTCR1_RCONT_Pos)      /*!< 0x00040000 */

+#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */

+#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)

+#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)   /*!< 0x00020000 */

+#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */

+#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)

+#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00006000 */

+#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */

+#define DFSDM_FLTCR1_JEXTEN_1           (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */

+#define DFSDM_FLTCR1_JEXTEN_0           (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */

+#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)

+#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)   /*!< 0x00001F00 */

+#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */

+#define DFSDM_FLTCR1_JEXTSEL_0          (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000100 */

+#define DFSDM_FLTCR1_JEXTSEL_1          (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000200 */

+#define DFSDM_FLTCR1_JEXTSEL_2          (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000400 */

+#define DFSDM_FLTCR1_JEXTSEL_3          (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000800 */

+#define DFSDM_FLTCR1_JEXTSEL_4          (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00001000 */

+

+#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)

+#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)     /*!< 0x00000020 */

+#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */

+#define DFSDM_FLTCR1_JSCAN_Pos          (4U)

+#define DFSDM_FLTCR1_JSCAN_Msk          (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)      /*!< 0x00000010 */

+#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */

+#define DFSDM_FLTCR1_JSYNC_Pos          (3U)

+#define DFSDM_FLTCR1_JSYNC_Msk          (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)      /*!< 0x00000008 */

+#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */

+#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)

+#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)   /*!< 0x00000002 */

+#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */

+#define DFSDM_FLTCR1_DFEN_Pos           (0U)

+#define DFSDM_FLTCR1_DFEN_Msk           (0x1UL << DFSDM_FLTCR1_DFEN_Pos)       /*!< 0x00000001 */

+#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */

+

+/********************  Bit definition for DFSDM_FLTCR2 register *******************/

+#define DFSDM_FLTCR2_AWDCH_Pos          (16U)

+#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)     /*!< 0x00FF0000 */

+#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */

+#define DFSDM_FLTCR2_EXCH_Pos           (8U)

+#define DFSDM_FLTCR2_EXCH_Msk           (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)      /*!< 0x0000FF00 */

+#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */

+#define DFSDM_FLTCR2_CKABIE_Pos         (6U)

+#define DFSDM_FLTCR2_CKABIE_Msk         (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)     /*!< 0x00000040 */

+#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */

+#define DFSDM_FLTCR2_SCDIE_Pos          (5U)

+#define DFSDM_FLTCR2_SCDIE_Msk          (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)      /*!< 0x00000020 */

+#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */

+#define DFSDM_FLTCR2_AWDIE_Pos          (4U)

+#define DFSDM_FLTCR2_AWDIE_Msk          (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)      /*!< 0x00000010 */

+#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */

+#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)

+#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)     /*!< 0x00000008 */

+#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */

+#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)

+#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)     /*!< 0x00000004 */

+#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */

+#define DFSDM_FLTCR2_REOCIE_Pos         (1U)

+#define DFSDM_FLTCR2_REOCIE_Msk         (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)     /*!< 0x00000002 */

+#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */

+#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)

+#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)     /*!< 0x00000001 */

+#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */

+

+/********************  Bit definition for DFSDM_FLTISR register *******************/

+#define DFSDM_FLTISR_SCDF_Pos           (24U)

+#define DFSDM_FLTISR_SCDF_Msk           (0xFFUL << DFSDM_FLTISR_SCDF_Pos)      /*!< 0xFF000000 */

+#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */

+#define DFSDM_FLTISR_CKABF_Pos          (16U)

+#define DFSDM_FLTISR_CKABF_Msk          (0xFFUL << DFSDM_FLTISR_CKABF_Pos)     /*!< 0x00FF0000 */

+#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */

+#define DFSDM_FLTISR_RCIP_Pos           (14U)

+#define DFSDM_FLTISR_RCIP_Msk           (0x1UL << DFSDM_FLTISR_RCIP_Pos)       /*!< 0x00004000 */

+#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */

+#define DFSDM_FLTISR_JCIP_Pos           (13U)

+#define DFSDM_FLTISR_JCIP_Msk           (0x1UL << DFSDM_FLTISR_JCIP_Pos)       /*!< 0x00002000 */

+#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */

+#define DFSDM_FLTISR_AWDF_Pos           (4U)

+#define DFSDM_FLTISR_AWDF_Msk           (0x1UL << DFSDM_FLTISR_AWDF_Pos)       /*!< 0x00000010 */

+#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */

+#define DFSDM_FLTISR_ROVRF_Pos          (3U)

+#define DFSDM_FLTISR_ROVRF_Msk          (0x1UL << DFSDM_FLTISR_ROVRF_Pos)      /*!< 0x00000008 */

+#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */

+#define DFSDM_FLTISR_JOVRF_Pos          (2U)

+#define DFSDM_FLTISR_JOVRF_Msk          (0x1UL << DFSDM_FLTISR_JOVRF_Pos)      /*!< 0x00000004 */

+#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */

+#define DFSDM_FLTISR_REOCF_Pos          (1U)

+#define DFSDM_FLTISR_REOCF_Msk          (0x1UL << DFSDM_FLTISR_REOCF_Pos)      /*!< 0x00000002 */

+#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */

+#define DFSDM_FLTISR_JEOCF_Pos          (0U)

+#define DFSDM_FLTISR_JEOCF_Msk          (0x1UL << DFSDM_FLTISR_JEOCF_Pos)      /*!< 0x00000001 */

+#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */

+

+/********************  Bit definition for DFSDM_FLTICR register *******************/

+#define DFSDM_FLTICR_CLRSCDF_Pos        (24U)

+#define DFSDM_FLTICR_CLRSCDF_Msk        (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)   /*!< 0xFF000000 */

+#define DFSDM_FLTICR_CLRSCDF            DFSDM_FLTICR_CLRSCDF_Msk               /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */

+#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)

+#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)  /*!< 0x00FF0000 */

+#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */

+#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)

+#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)   /*!< 0x00000008 */

+#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */

+#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)

+#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)   /*!< 0x00000004 */

+#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */

+

+/*******************  Bit definition for DFSDM_FLTJCHGR register ******************/

+#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)

+#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)    /*!< 0x000000FF */

+#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */

+

+/********************  Bit definition for DFSDM_FLTFCR register *******************/

+#define DFSDM_FLTFCR_FORD_Pos           (29U)

+#define DFSDM_FLTFCR_FORD_Msk           (0x7UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0xE0000000 */

+#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */

+#define DFSDM_FLTFCR_FORD_2             (0x4UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */

+#define DFSDM_FLTFCR_FORD_1             (0x2UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */

+#define DFSDM_FLTFCR_FORD_0             (0x1UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */

+#define DFSDM_FLTFCR_FOSR_Pos           (16U)

+#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)     /*!< 0x03FF0000 */

+#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */

+#define DFSDM_FLTFCR_IOSR_Pos           (0U)

+#define DFSDM_FLTFCR_IOSR_Msk           (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)      /*!< 0x000000FF */

+#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */

+

+/******************  Bit definition for DFSDM_FLTJDATAR register *****************/

+#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)

+#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */

+#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)

+#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */

+#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */

+

+/******************  Bit definition for DFSDM_FLTRDATAR register *****************/

+#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)

+#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */

+#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)

+#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)   /*!< 0x00000010 */

+#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */

+#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)

+#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */

+#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */

+

+/******************  Bit definition for DFSDM_FLTAWHTR register ******************/

+#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)

+#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */

+#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)

+#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)    /*!< 0x0000000F */

+#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */

+

+/******************  Bit definition for DFSDM_FLTAWLTR register ******************/

+#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)

+#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWHT[23:0] Analog watchdog low threshold */

+#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)

+#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)    /*!< 0x0000000F */

+#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */

+

+/******************  Bit definition for DFSDM_FLTAWSR register ******************/

+#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)

+#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)    /*!< 0x0000FF00 */

+#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */

+#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)

+#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)    /*!< 0x000000FF */

+#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */

+

+/******************  Bit definition for DFSDM_FLTAWCFR) register *****************/

+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)

+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */

+#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */

+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)

+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */

+#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */

+

+/******************  Bit definition for DFSDM_FLTEXMAX register ******************/

+#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)

+#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */

+#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)

+#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)  /*!< 0x00000007 */

+#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */

+

+/******************  Bit definition for DFSDM_FLTEXMIN register ******************/

+#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)

+#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */

+#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)

+#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)  /*!< 0x00000007 */

+#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */

+

+/******************  Bit definition for DFSDM_FLTCNVTIMR register ******************/

+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)

+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */

+#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           BDMA Controller                                  */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for BDMA_ISR register  ********************/

+#define BDMA_ISR_GIF0_Pos       (0U)

+#define BDMA_ISR_GIF0_Msk       (0x1UL << BDMA_ISR_GIF0_Pos)                   /*!< 0x00000001 */

+#define BDMA_ISR_GIF0           BDMA_ISR_GIF0_Msk                              /*!< Channel 0 Global interrupt flag */

+#define BDMA_ISR_TCIF0_Pos      (1U)

+#define BDMA_ISR_TCIF0_Msk      (0x1UL << BDMA_ISR_TCIF0_Pos)                  /*!< 0x00000002 */

+#define BDMA_ISR_TCIF0          BDMA_ISR_TCIF0_Msk                             /*!< Channel 0 Transfer Complete flag */

+#define BDMA_ISR_HTIF0_Pos      (2U)

+#define BDMA_ISR_HTIF0_Msk      (0x1UL << BDMA_ISR_HTIF0_Pos)                  /*!< 0x00000004 */

+#define BDMA_ISR_HTIF0          BDMA_ISR_HTIF0_Msk                             /*!< Channel 0 Half Transfer flag */

+#define BDMA_ISR_TEIF0_Pos      (3U)

+#define BDMA_ISR_TEIF0_Msk      (0x1UL << BDMA_ISR_TEIF0_Pos)                  /*!< 0x00000008 */

+#define BDMA_ISR_TEIF0          BDMA_ISR_TEIF0_Msk                             /*!< Channel 0 Transfer Error flag */

+#define BDMA_ISR_GIF1_Pos       (4U)

+#define BDMA_ISR_GIF1_Msk       (0x1UL << BDMA_ISR_GIF1_Pos)                   /*!< 0x00000010 */

+#define BDMA_ISR_GIF1           BDMA_ISR_GIF1_Msk                              /*!< Channel 1 Global interrupt flag */

+#define BDMA_ISR_TCIF1_Pos      (5U)

+#define BDMA_ISR_TCIF1_Msk      (0x1UL << BDMA_ISR_TCIF1_Pos)                  /*!< 0x00000020 */

+#define BDMA_ISR_TCIF1          BDMA_ISR_TCIF1_Msk                             /*!< Channel 1 Transfer Complete flag */

+#define BDMA_ISR_HTIF1_Pos      (6U)

+#define BDMA_ISR_HTIF1_Msk      (0x1UL << BDMA_ISR_HTIF1_Pos)                  /*!< 0x00000040 */

+#define BDMA_ISR_HTIF1          BDMA_ISR_HTIF1_Msk                             /*!< Channel 1 Half Transfer flag */

+#define BDMA_ISR_TEIF1_Pos      (7U)

+#define BDMA_ISR_TEIF1_Msk      (0x1UL << BDMA_ISR_TEIF1_Pos)                  /*!< 0x00000080 */

+#define BDMA_ISR_TEIF1          BDMA_ISR_TEIF1_Msk                             /*!< Channel 1 Transfer Error flag */

+#define BDMA_ISR_GIF2_Pos       (8U)

+#define BDMA_ISR_GIF2_Msk       (0x1UL << BDMA_ISR_GIF2_Pos)                   /*!< 0x00000100 */

+#define BDMA_ISR_GIF2           BDMA_ISR_GIF2_Msk                              /*!< Channel 2 Global interrupt flag */

+#define BDMA_ISR_TCIF2_Pos      (9U)

+#define BDMA_ISR_TCIF2_Msk      (0x1UL << BDMA_ISR_TCIF2_Pos)                  /*!< 0x00000200 */

+#define BDMA_ISR_TCIF2          BDMA_ISR_TCIF2_Msk                             /*!< Channel 2 Transfer Complete flag */

+#define BDMA_ISR_HTIF2_Pos      (10U)

+#define BDMA_ISR_HTIF2_Msk      (0x1UL << BDMA_ISR_HTIF2_Pos)                  /*!< 0x00000400 */

+#define BDMA_ISR_HTIF2          BDMA_ISR_HTIF2_Msk                             /*!< Channel 2 Half Transfer flag */

+#define BDMA_ISR_TEIF2_Pos      (11U)

+#define BDMA_ISR_TEIF2_Msk      (0x1UL << BDMA_ISR_TEIF2_Pos)                  /*!< 0x00000800 */

+#define BDMA_ISR_TEIF2          BDMA_ISR_TEIF2_Msk                             /*!< Channel 2 Transfer Error flag */

+#define BDMA_ISR_GIF3_Pos       (12U)

+#define BDMA_ISR_GIF3_Msk       (0x1UL << BDMA_ISR_GIF3_Pos)                   /*!< 0x00001000 */

+#define BDMA_ISR_GIF3           BDMA_ISR_GIF3_Msk                              /*!< Channel 3 Global interrupt flag */

+#define BDMA_ISR_TCIF3_Pos      (13U)

+#define BDMA_ISR_TCIF3_Msk      (0x1UL << BDMA_ISR_TCIF3_Pos)                  /*!< 0x00002000 */

+#define BDMA_ISR_TCIF3          BDMA_ISR_TCIF3_Msk                             /*!< Channel 3 Transfer Complete flag */

+#define BDMA_ISR_HTIF3_Pos      (14U)

+#define BDMA_ISR_HTIF3_Msk      (0x1UL << BDMA_ISR_HTIF3_Pos)                  /*!< 0x00004000 */

+#define BDMA_ISR_HTIF3          BDMA_ISR_HTIF3_Msk                             /*!< Channel 3 Half Transfer flag */

+#define BDMA_ISR_TEIF3_Pos      (15U)

+#define BDMA_ISR_TEIF3_Msk      (0x1UL << BDMA_ISR_TEIF3_Pos)                  /*!< 0x00008000 */

+#define BDMA_ISR_TEIF3          BDMA_ISR_TEIF3_Msk                             /*!< Channel 3 Transfer Error flag */

+#define BDMA_ISR_GIF4_Pos       (16U)

+#define BDMA_ISR_GIF4_Msk       (0x1UL << BDMA_ISR_GIF4_Pos)                   /*!< 0x00010000 */

+#define BDMA_ISR_GIF4           BDMA_ISR_GIF4_Msk                              /*!< Channel 4 Global interrupt flag */

+#define BDMA_ISR_TCIF4_Pos      (17U)

+#define BDMA_ISR_TCIF4_Msk      (0x1UL << BDMA_ISR_TCIF4_Pos)                  /*!< 0x00020000 */

+#define BDMA_ISR_TCIF4          BDMA_ISR_TCIF4_Msk                             /*!< Channel 4 Transfer Complete flag */

+#define BDMA_ISR_HTIF4_Pos      (18U)

+#define BDMA_ISR_HTIF4_Msk      (0x1UL << BDMA_ISR_HTIF4_Pos)                  /*!< 0x00040000 */

+#define BDMA_ISR_HTIF4          BDMA_ISR_HTIF4_Msk                             /*!< Channel 4 Half Transfer flag */

+#define BDMA_ISR_TEIF4_Pos      (19U)

+#define BDMA_ISR_TEIF4_Msk      (0x1UL << BDMA_ISR_TEIF4_Pos)                  /*!< 0x00080000 */

+#define BDMA_ISR_TEIF4          BDMA_ISR_TEIF4_Msk                             /*!< Channel 4 Transfer Error flag */

+#define BDMA_ISR_GIF5_Pos       (20U)

+#define BDMA_ISR_GIF5_Msk       (0x1UL << BDMA_ISR_GIF5_Pos)                   /*!< 0x00100000 */

+#define BDMA_ISR_GIF5           BDMA_ISR_GIF5_Msk                              /*!< Channel 5 Global interrupt flag */

+#define BDMA_ISR_TCIF5_Pos      (21U)

+#define BDMA_ISR_TCIF5_Msk      (0x1UL << BDMA_ISR_TCIF5_Pos)                  /*!< 0x00200000 */

+#define BDMA_ISR_TCIF5          BDMA_ISR_TCIF5_Msk                             /*!< Channel 5 Transfer Complete flag */

+#define BDMA_ISR_HTIF5_Pos      (22U)

+#define BDMA_ISR_HTIF5_Msk      (0x1UL << BDMA_ISR_HTIF5_Pos)                  /*!< 0x00400000 */

+#define BDMA_ISR_HTIF5          BDMA_ISR_HTIF5_Msk                             /*!< Channel 5 Half Transfer flag */

+#define BDMA_ISR_TEIF5_Pos      (23U)

+#define BDMA_ISR_TEIF5_Msk      (0x1UL << BDMA_ISR_TEIF5_Pos)                  /*!< 0x00800000 */

+#define BDMA_ISR_TEIF5          BDMA_ISR_TEIF5_Msk                             /*!< Channel 5 Transfer Error flag */

+#define BDMA_ISR_GIF6_Pos       (24U)

+#define BDMA_ISR_GIF6_Msk       (0x1UL << BDMA_ISR_GIF6_Pos)                   /*!< 0x01000000 */

+#define BDMA_ISR_GIF6           BDMA_ISR_GIF6_Msk                              /*!< Channel 6 Global interrupt flag */

+#define BDMA_ISR_TCIF6_Pos      (25U)

+#define BDMA_ISR_TCIF6_Msk      (0x1UL << BDMA_ISR_TCIF6_Pos)                  /*!< 0x02000000 */

+#define BDMA_ISR_TCIF6          BDMA_ISR_TCIF6_Msk                             /*!< Channel 6 Transfer Complete flag */

+#define BDMA_ISR_HTIF6_Pos      (26U)

+#define BDMA_ISR_HTIF6_Msk      (0x1UL << BDMA_ISR_HTIF6_Pos)                  /*!< 0x04000000 */

+#define BDMA_ISR_HTIF6          BDMA_ISR_HTIF6_Msk                             /*!< Channel 6 Half Transfer flag */

+#define BDMA_ISR_TEIF6_Pos      (27U)

+#define BDMA_ISR_TEIF6_Msk      (0x1UL << BDMA_ISR_TEIF6_Pos)                  /*!< 0x08000000 */

+#define BDMA_ISR_TEIF6          BDMA_ISR_TEIF6_Msk                             /*!< Channel 6 Transfer Error flag */

+#define BDMA_ISR_GIF7_Pos       (28U)

+#define BDMA_ISR_GIF7_Msk       (0x1UL << BDMA_ISR_GIF7_Pos)                   /*!< 0x10000000 */

+#define BDMA_ISR_GIF7           BDMA_ISR_GIF7_Msk                              /*!< Channel 7 Global interrupt flag */

+#define BDMA_ISR_TCIF7_Pos      (29U)

+#define BDMA_ISR_TCIF7_Msk      (0x1UL << BDMA_ISR_TCIF7_Pos)                  /*!< 0x20000000 */

+#define BDMA_ISR_TCIF7          BDMA_ISR_TCIF7_Msk                             /*!< Channel 7 Transfer Complete flag */

+#define BDMA_ISR_HTIF7_Pos      (30U)

+#define BDMA_ISR_HTIF7_Msk      (0x1UL << BDMA_ISR_HTIF7_Pos)                  /*!< 0x40000000 */

+#define BDMA_ISR_HTIF7          BDMA_ISR_HTIF7_Msk                             /*!< Channel 7 Half Transfer flag */

+#define BDMA_ISR_TEIF7_Pos      (31U)

+#define BDMA_ISR_TEIF7_Msk      (0x1UL << BDMA_ISR_TEIF7_Pos)                  /*!< 0x80000000 */

+#define BDMA_ISR_TEIF7          BDMA_ISR_TEIF7_Msk                             /*!< Channel 7 Transfer Error flag */

+

+/*******************  Bit definition for BDMA_IFCR register  *******************/

+#define BDMA_IFCR_CGIF0_Pos     (0U)

+#define BDMA_IFCR_CGIF0_Msk     (0x1UL << BDMA_IFCR_CGIF0_Pos)                 /*!< 0x00000001 */

+#define BDMA_IFCR_CGIF0         BDMA_IFCR_CGIF0_Msk                            /*!< Channel 0 Global interrupt clearr */

+#define BDMA_IFCR_CTCIF0_Pos    (1U)

+#define BDMA_IFCR_CTCIF0_Msk    (0x1UL << BDMA_IFCR_CTCIF0_Pos)                /*!< 0x00000002 */

+#define BDMA_IFCR_CTCIF0        BDMA_IFCR_CTCIF0_Msk                           /*!< Channel 0 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF0_Pos    (2U)

+#define BDMA_IFCR_CHTIF0_Msk    (0x1UL << BDMA_IFCR_CHTIF0_Pos)                /*!< 0x00000004 */

+#define BDMA_IFCR_CHTIF0        BDMA_IFCR_CHTIF0_Msk                           /*!< Channel 0 Half Transfer clear */

+#define BDMA_IFCR_CTEIF0_Pos    (3U)

+#define BDMA_IFCR_CTEIF0_Msk    (0x1UL << BDMA_IFCR_CTEIF0_Pos)                /*!< 0x00000008 */

+#define BDMA_IFCR_CTEIF0        BDMA_IFCR_CTEIF0_Msk                           /*!< Channel 0 Transfer Error clear */

+#define BDMA_IFCR_CGIF1_Pos     (4U)

+#define BDMA_IFCR_CGIF1_Msk     (0x1UL << BDMA_IFCR_CGIF1_Pos)                 /*!< 0x00000010 */

+#define BDMA_IFCR_CGIF1         BDMA_IFCR_CGIF1_Msk                            /*!< Channel 1 Global interrupt clear */

+#define BDMA_IFCR_CTCIF1_Pos    (5U)

+#define BDMA_IFCR_CTCIF1_Msk    (0x1UL << BDMA_IFCR_CTCIF1_Pos)                /*!< 0x00000020 */

+#define BDMA_IFCR_CTCIF1        BDMA_IFCR_CTCIF1_Msk                           /*!< Channel 1 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF1_Pos    (6U)

+#define BDMA_IFCR_CHTIF1_Msk    (0x1UL << BDMA_IFCR_CHTIF1_Pos)                /*!< 0x00000040 */

+#define BDMA_IFCR_CHTIF1        BDMA_IFCR_CHTIF1_Msk                           /*!< Channel 1 Half Transfer clear */

+#define BDMA_IFCR_CTEIF1_Pos    (7U)

+#define BDMA_IFCR_CTEIF1_Msk    (0x1UL << BDMA_IFCR_CTEIF1_Pos)                /*!< 0x00000080 */

+#define BDMA_IFCR_CTEIF1        BDMA_IFCR_CTEIF1_Msk                           /*!< Channel 1 Transfer Error clear */

+#define BDMA_IFCR_CGIF2_Pos     (8U)

+#define BDMA_IFCR_CGIF2_Msk     (0x1UL << BDMA_IFCR_CGIF2_Pos)                 /*!< 0x00000100 */

+#define BDMA_IFCR_CGIF2         BDMA_IFCR_CGIF2_Msk                            /*!< Channel 2 Global interrupt clear */

+#define BDMA_IFCR_CTCIF2_Pos    (9U)

+#define BDMA_IFCR_CTCIF2_Msk    (0x1UL << BDMA_IFCR_CTCIF2_Pos)                /*!< 0x00000200 */

+#define BDMA_IFCR_CTCIF2        BDMA_IFCR_CTCIF2_Msk                           /*!< Channel 2 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF2_Pos    (10U)

+#define BDMA_IFCR_CHTIF2_Msk    (0x1UL << BDMA_IFCR_CHTIF2_Pos)                /*!< 0x00000400 */

+#define BDMA_IFCR_CHTIF2        BDMA_IFCR_CHTIF2_Msk                           /*!< Channel 2 Half Transfer clear */

+#define BDMA_IFCR_CTEIF2_Pos    (11U)

+#define BDMA_IFCR_CTEIF2_Msk    (0x1UL << BDMA_IFCR_CTEIF2_Pos)                /*!< 0x00000800 */

+#define BDMA_IFCR_CTEIF2        BDMA_IFCR_CTEIF2_Msk                           /*!< Channel 2 Transfer Error clear */

+#define BDMA_IFCR_CGIF3_Pos     (12U)

+#define BDMA_IFCR_CGIF3_Msk     (0x1UL << BDMA_IFCR_CGIF3_Pos)                 /*!< 0x00001000 */

+#define BDMA_IFCR_CGIF3         BDMA_IFCR_CGIF3_Msk                            /*!< Channel 3 Global interrupt clear */

+#define BDMA_IFCR_CTCIF3_Pos    (13U)

+#define BDMA_IFCR_CTCIF3_Msk    (0x1UL << BDMA_IFCR_CTCIF3_Pos)                /*!< 0x00002000 */

+#define BDMA_IFCR_CTCIF3        BDMA_IFCR_CTCIF3_Msk                           /*!< Channel 3 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF3_Pos    (14U)

+#define BDMA_IFCR_CHTIF3_Msk    (0x1UL << BDMA_IFCR_CHTIF3_Pos)                /*!< 0x00004000 */

+#define BDMA_IFCR_CHTIF3        BDMA_IFCR_CHTIF3_Msk                           /*!< Channel 3 Half Transfer clear */

+#define BDMA_IFCR_CTEIF3_Pos    (15U)

+#define BDMA_IFCR_CTEIF3_Msk    (0x1UL << BDMA_IFCR_CTEIF3_Pos)                /*!< 0x00008000 */

+#define BDMA_IFCR_CTEIF3        BDMA_IFCR_CTEIF3_Msk                           /*!< Channel 3 Transfer Error clear */

+#define BDMA_IFCR_CGIF4_Pos     (16U)

+#define BDMA_IFCR_CGIF4_Msk     (0x1UL << BDMA_IFCR_CGIF4_Pos)                 /*!< 0x00010000 */

+#define BDMA_IFCR_CGIF4         BDMA_IFCR_CGIF4_Msk                            /*!< Channel 4 Global interrupt clear */

+#define BDMA_IFCR_CTCIF4_Pos    (17U)

+#define BDMA_IFCR_CTCIF4_Msk    (0x1UL << BDMA_IFCR_CTCIF4_Pos)                /*!< 0x00020000 */

+#define BDMA_IFCR_CTCIF4        BDMA_IFCR_CTCIF4_Msk                           /*!< Channel 4 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF4_Pos    (18U)

+#define BDMA_IFCR_CHTIF4_Msk    (0x1UL << BDMA_IFCR_CHTIF4_Pos)                /*!< 0x00040000 */

+#define BDMA_IFCR_CHTIF4        BDMA_IFCR_CHTIF4_Msk                           /*!< Channel 4 Half Transfer clear */

+#define BDMA_IFCR_CTEIF4_Pos    (19U)

+#define BDMA_IFCR_CTEIF4_Msk    (0x1UL << BDMA_IFCR_CTEIF4_Pos)                /*!< 0x00080000 */

+#define BDMA_IFCR_CTEIF4        BDMA_IFCR_CTEIF4_Msk                           /*!< Channel 4 Transfer Error clear */

+#define BDMA_IFCR_CGIF5_Pos     (20U)

+#define BDMA_IFCR_CGIF5_Msk     (0x1UL << BDMA_IFCR_CGIF5_Pos)                 /*!< 0x00100000 */

+#define BDMA_IFCR_CGIF5         BDMA_IFCR_CGIF5_Msk                            /*!< Channel 5 Global interrupt clear */

+#define BDMA_IFCR_CTCIF5_Pos    (21U)

+#define BDMA_IFCR_CTCIF5_Msk    (0x1UL << BDMA_IFCR_CTCIF5_Pos)                /*!< 0x00200000 */

+#define BDMA_IFCR_CTCIF5        BDMA_IFCR_CTCIF5_Msk                           /*!< Channel 5 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF5_Pos    (22U)

+#define BDMA_IFCR_CHTIF5_Msk    (0x1UL << BDMA_IFCR_CHTIF5_Pos)                /*!< 0x00400000 */

+#define BDMA_IFCR_CHTIF5        BDMA_IFCR_CHTIF5_Msk                           /*!< Channel 5 Half Transfer clear */

+#define BDMA_IFCR_CTEIF5_Pos    (23U)

+#define BDMA_IFCR_CTEIF5_Msk    (0x1UL << BDMA_IFCR_CTEIF5_Pos)                /*!< 0x00800000 */

+#define BDMA_IFCR_CTEIF5        BDMA_IFCR_CTEIF5_Msk                           /*!< Channel 5 Transfer Error clear */

+#define BDMA_IFCR_CGIF6_Pos     (24U)

+#define BDMA_IFCR_CGIF6_Msk     (0x1UL << BDMA_IFCR_CGIF6_Pos)                 /*!< 0x01000000 */

+#define BDMA_IFCR_CGIF6         BDMA_IFCR_CGIF6_Msk                            /*!< Channel 6 Global interrupt clear */

+#define BDMA_IFCR_CTCIF6_Pos    (25U)

+#define BDMA_IFCR_CTCIF6_Msk    (0x1UL << BDMA_IFCR_CTCIF6_Pos)                /*!< 0x02000000 */

+#define BDMA_IFCR_CTCIF6        BDMA_IFCR_CTCIF6_Msk                           /*!< Channel 6 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF6_Pos    (26U)

+#define BDMA_IFCR_CHTIF6_Msk    (0x1UL << BDMA_IFCR_CHTIF6_Pos)                /*!< 0x04000000 */

+#define BDMA_IFCR_CHTIF6        BDMA_IFCR_CHTIF6_Msk                           /*!< Channel 6 Half Transfer clear */

+#define BDMA_IFCR_CTEIF6_Pos    (27U)

+#define BDMA_IFCR_CTEIF6_Msk    (0x1UL << BDMA_IFCR_CTEIF6_Pos)                /*!< 0x08000000 */

+#define BDMA_IFCR_CTEIF6        BDMA_IFCR_CTEIF6_Msk                           /*!< Channel 6 Transfer Error clear */

+#define BDMA_IFCR_CGIF7_Pos     (28U)

+#define BDMA_IFCR_CGIF7_Msk     (0x1UL << BDMA_IFCR_CGIF7_Pos)                 /*!< 0x10000000 */

+#define BDMA_IFCR_CGIF7         BDMA_IFCR_CGIF7_Msk                            /*!< Channel 7 Global interrupt clear */

+#define BDMA_IFCR_CTCIF7_Pos    (29U)

+#define BDMA_IFCR_CTCIF7_Msk    (0x1UL << BDMA_IFCR_CTCIF7_Pos)                /*!< 0x20000000 */

+#define BDMA_IFCR_CTCIF7        BDMA_IFCR_CTCIF7_Msk                           /*!< Channel 7 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF7_Pos    (30U)

+#define BDMA_IFCR_CHTIF7_Msk    (0x1UL << BDMA_IFCR_CHTIF7_Pos)                /*!< 0x40000000 */

+#define BDMA_IFCR_CHTIF7        BDMA_IFCR_CHTIF7_Msk                           /*!< Channel 7 Half Transfer clear */

+#define BDMA_IFCR_CTEIF7_Pos    (31U)

+#define BDMA_IFCR_CTEIF7_Msk    (0x1UL << BDMA_IFCR_CTEIF7_Pos)                /*!< 0x80000000 */

+#define BDMA_IFCR_CTEIF7        BDMA_IFCR_CTEIF7_Msk                           /*!< Channel 7 Transfer Error clear */

+

+/*******************  Bit definition for BDMA_CCR register  ********************/

+#define BDMA_CCR_EN_Pos         (0U)

+#define BDMA_CCR_EN_Msk         (0x1UL << BDMA_CCR_EN_Pos)                     /*!< 0x00000001 */

+#define BDMA_CCR_EN             BDMA_CCR_EN_Msk                                /*!< Channel enable                      */

+#define BDMA_CCR_TCIE_Pos       (1U)

+#define BDMA_CCR_TCIE_Msk       (0x1UL << BDMA_CCR_TCIE_Pos)                   /*!< 0x00000002 */

+#define BDMA_CCR_TCIE           BDMA_CCR_TCIE_Msk                              /*!< Transfer complete interrupt enable  */

+#define BDMA_CCR_HTIE_Pos       (2U)

+#define BDMA_CCR_HTIE_Msk       (0x1UL << BDMA_CCR_HTIE_Pos)                   /*!< 0x00000004 */

+#define BDMA_CCR_HTIE           BDMA_CCR_HTIE_Msk                              /*!< Half Transfer interrupt enable      */

+#define BDMA_CCR_TEIE_Pos       (3U)

+#define BDMA_CCR_TEIE_Msk       (0x1UL << BDMA_CCR_TEIE_Pos)                   /*!< 0x00000008 */

+#define BDMA_CCR_TEIE           BDMA_CCR_TEIE_Msk                              /*!< Transfer error interrupt enable     */

+#define BDMA_CCR_DIR_Pos        (4U)

+#define BDMA_CCR_DIR_Msk        (0x1UL << BDMA_CCR_DIR_Pos)                    /*!< 0x00000010 */

+#define BDMA_CCR_DIR            BDMA_CCR_DIR_Msk                               /*!< Data transfer direction             */

+#define BDMA_CCR_CIRC_Pos       (5U)

+#define BDMA_CCR_CIRC_Msk       (0x1UL << BDMA_CCR_CIRC_Pos)                   /*!< 0x00000020 */

+#define BDMA_CCR_CIRC           BDMA_CCR_CIRC_Msk                              /*!< Circular mode                       */

+#define BDMA_CCR_PINC_Pos       (6U)

+#define BDMA_CCR_PINC_Msk       (0x1UL << BDMA_CCR_PINC_Pos)                   /*!< 0x00000040 */

+#define BDMA_CCR_PINC           BDMA_CCR_PINC_Msk                              /*!< Peripheral increment mode           */

+#define BDMA_CCR_MINC_Pos       (7U)

+#define BDMA_CCR_MINC_Msk       (0x1UL << BDMA_CCR_MINC_Pos)                   /*!< 0x00000080 */

+#define BDMA_CCR_MINC           BDMA_CCR_MINC_Msk                              /*!< Memory increment mode               */

+

+#define BDMA_CCR_PSIZE_Pos      (8U)

+#define BDMA_CCR_PSIZE_Msk      (0x3UL << BDMA_CCR_PSIZE_Pos)                  /*!< 0x00000300 */

+#define BDMA_CCR_PSIZE          BDMA_CCR_PSIZE_Msk                             /*!< PSIZE[1:0] bits (Peripheral size)   */

+#define BDMA_CCR_PSIZE_0        (0x1UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000100 */

+#define BDMA_CCR_PSIZE_1        (0x2UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000200 */

+

+#define BDMA_CCR_MSIZE_Pos      (10U)

+#define BDMA_CCR_MSIZE_Msk      (0x3UL << BDMA_CCR_MSIZE_Pos)                  /*!< 0x00000C00 */

+#define BDMA_CCR_MSIZE          BDMA_CCR_MSIZE_Msk                             /*!< MSIZE[1:0] bits (Memory size)       */

+#define BDMA_CCR_MSIZE_0        (0x1UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000400 */

+#define BDMA_CCR_MSIZE_1        (0x2UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000800 */

+

+#define BDMA_CCR_PL_Pos         (12U)

+#define BDMA_CCR_PL_Msk         (0x3UL << BDMA_CCR_PL_Pos)                     /*!< 0x00003000 */

+#define BDMA_CCR_PL             BDMA_CCR_PL_Msk                                /*!< PL[1:0] bits(Channel Priority level)*/

+#define BDMA_CCR_PL_0           (0x1UL << BDMA_CCR_PL_Pos)                      /*!< 0x00001000 */

+#define BDMA_CCR_PL_1           (0x2UL << BDMA_CCR_PL_Pos)                      /*!< 0x00002000 */

+

+#define BDMA_CCR_MEM2MEM_Pos    (14U)

+#define BDMA_CCR_MEM2MEM_Msk    (0x1UL << BDMA_CCR_MEM2MEM_Pos)                /*!< 0x00004000 */

+#define BDMA_CCR_MEM2MEM        BDMA_CCR_MEM2MEM_Msk                           /*!< Memory to memory mode               */

+#define BDMA_CCR_DBM_Pos        (15U)

+#define BDMA_CCR_DBM_Msk        (0x1UL << BDMA_CCR_DBM_Pos)                    /*!< 0x0000A000 */

+#define BDMA_CCR_DBM            BDMA_CCR_DBM_Msk                               /*!< Memory to memory mode               */

+#define BDMA_CCR_CT_Pos         (16U)

+#define BDMA_CCR_CT_Msk         (0x1UL << BDMA_CCR_CT_Pos)                     /*!< 0x00010000 */

+#define BDMA_CCR_CT             BDMA_CCR_CT_Msk                                /*!< Memory to memory mode               */

+

+/******************  Bit definition for BDMA_CNDTR register  *******************/

+#define BDMA_CNDTR_NDT_Pos      (0U)

+#define BDMA_CNDTR_NDT_Msk      (0xFFFFUL << BDMA_CNDTR_NDT_Pos)               /*!< 0x0000FFFF */

+#define BDMA_CNDTR_NDT          BDMA_CNDTR_NDT_Msk                             /*!< Number of data to Transfer          */

+

+/******************  Bit definition for BDMA_CPAR register  ********************/

+#define BDMA_CPAR_PA_Pos        (0U)

+#define BDMA_CPAR_PA_Msk        (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CPAR_PA            BDMA_CPAR_PA_Msk                               /*!< Peripheral Address                  */

+

+/******************  Bit definition for BDMA_CM0AR register  ********************/

+#define BDMA_CM0AR_MA_Pos        (0U)

+#define BDMA_CM0AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CM0AR_MA            BDMA_CM0AR_MA_Msk                               /*!< Memory Address                      */

+

+/******************  Bit definition for BDMA_CM1AR register  ********************/

+#define BDMA_CM1AR_MA_Pos        (0U)

+#define BDMA_CM1AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CM1AR_MA            BDMA_CM1AR_MA_Msk                               /*!< Memory Address                      */

+

+/******************************************************************************/

+/*                                                                            */

+/*                Ethernet MAC Registers bits definitions                     */

+/*                                                                            */

+/******************************************************************************/

+/* Bit definition for Ethernet MAC Configuration Register register */

+#define ETH_MACCR_ARP_Pos                             (31U)

+#define ETH_MACCR_ARP_Msk                             (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */

+#define ETH_MACCR_ARP                                 ETH_MACCR_ARP_Msk        /* ARP Offload Enable */

+#define ETH_MACCR_SARC_Pos                            (28U)

+#define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */

+#define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */

+#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */

+#define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)

+#define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */

+#define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */

+#define ETH_MACCR_SARC_INSADDR1_Pos                   (29U)

+#define ETH_MACCR_SARC_INSADDR1_Msk                   (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */

+#define ETH_MACCR_SARC_INSADDR1                       ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */

+#define ETH_MACCR_SARC_REPADDR0_Pos                   (28U)

+#define ETH_MACCR_SARC_REPADDR0_Msk                   (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */

+#define ETH_MACCR_SARC_REPADDR0                       ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */

+#define ETH_MACCR_SARC_REPADDR1_Pos                   (28U)

+#define ETH_MACCR_SARC_REPADDR1_Msk                   (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */

+#define ETH_MACCR_SARC_REPADDR1                       ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */

+#define ETH_MACCR_IPC_Pos                             (27U)

+#define ETH_MACCR_IPC_Msk                             (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */

+#define ETH_MACCR_IPC                                 ETH_MACCR_IPC_Msk        /* Checksum Offload */

+#define ETH_MACCR_IPG_Pos                             (24U)

+#define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */

+#define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */

+#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */

+#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */

+#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */

+#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */

+#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */

+#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */

+#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */

+#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */

+#define ETH_MACCR_GPSLCE_Pos                          (23U)

+#define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */

+#define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */

+#define ETH_MACCR_S2KP_Pos                            (22U)

+#define ETH_MACCR_S2KP_Msk                            (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */

+#define ETH_MACCR_S2KP                                ETH_MACCR_S2KP_Msk       /* IEEE 802.3as Support for 2K Packets */

+#define ETH_MACCR_CST_Pos                             (21U)

+#define ETH_MACCR_CST_Msk                             (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */

+#define ETH_MACCR_CST                                 ETH_MACCR_CST_Msk        /* CRC stripping for Type packets */

+#define ETH_MACCR_ACS_Pos                             (20U)

+#define ETH_MACCR_ACS_Msk                             (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */

+#define ETH_MACCR_ACS                                 ETH_MACCR_ACS_Msk        /* Automatic Pad or CRC Stripping */

+#define ETH_MACCR_WD_Pos                              (19U)

+#define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */

+#define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */

+#define ETH_MACCR_JD_Pos                              (17U)

+#define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */

+#define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */

+#define ETH_MACCR_JE_Pos                              (16U)

+#define ETH_MACCR_JE_Msk                              (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */

+#define ETH_MACCR_JE                                  ETH_MACCR_JE_Msk         /* Jumbo Packet Enable */

+#define ETH_MACCR_FES_Pos                             (14U)

+#define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */

+#define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */

+#define ETH_MACCR_DM_Pos                              (13U)

+#define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */

+#define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */

+#define ETH_MACCR_LM_Pos                              (12U)

+#define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */

+#define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */

+#define ETH_MACCR_ECRSFD_Pos                          (11U)

+#define ETH_MACCR_ECRSFD_Msk                          (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */

+#define ETH_MACCR_ECRSFD                              ETH_MACCR_ECRSFD_Msk     /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */

+#define ETH_MACCR_DO_Pos                              (10U)

+#define ETH_MACCR_DO_Msk                              (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */

+#define ETH_MACCR_DO                                  ETH_MACCR_DO_Msk         /* Disable Receive own  */

+#define ETH_MACCR_DCRS_Pos                            (9U)

+#define ETH_MACCR_DCRS_Msk                            (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */

+#define ETH_MACCR_DCRS                                ETH_MACCR_DCRS_Msk       /* Disable Carrier Sense During Transmission */

+#define ETH_MACCR_DR_Pos                              (8U)

+#define ETH_MACCR_DR_Msk                              (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */

+#define ETH_MACCR_DR                                  ETH_MACCR_DR_Msk         /* Disable Retry */

+#define ETH_MACCR_BL_Pos                              (5U)

+#define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */

+#define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit mask */

+#define ETH_MACCR_BL_10                               (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */

+#define ETH_MACCR_BL_8                                (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */

+#define ETH_MACCR_BL_4                                (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */

+#define ETH_MACCR_BL_1                                (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */

+#define ETH_MACCR_DC_Pos                              (4U)

+#define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */

+#define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */

+#define ETH_MACCR_PRELEN_Pos                          (2U)

+#define ETH_MACCR_PRELEN_Msk                          (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */

+#define ETH_MACCR_PRELEN                              ETH_MACCR_PRELEN_Msk     /* Preamble Length for Transmit packets */

+#define ETH_MACCR_PRELEN_7                            (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */

+#define ETH_MACCR_PRELEN_5                            (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */

+#define ETH_MACCR_PRELEN_3                            (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */

+#define ETH_MACCR_TE_Pos                              (1U)

+#define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */

+#define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */

+#define ETH_MACCR_RE_Pos                              (0U)

+#define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */

+#define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */

+

+/* Bit definition for Ethernet MAC Extended Configuration Register register */

+#define ETH_MACECR_EIPG_Pos                           (25U)

+#define ETH_MACECR_EIPG_Msk                           (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */

+#define ETH_MACECR_EIPG                               ETH_MACECR_EIPG_Msk      /* Extended Inter-Packet Gap */

+#define ETH_MACECR_EIPGEN_Pos                         (24U)

+#define ETH_MACECR_EIPGEN_Msk                         (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */

+#define ETH_MACECR_EIPGEN                             ETH_MACECR_EIPGEN_Msk    /* Extended Inter-Packet Gap Enable */

+#define ETH_MACECR_USP_Pos                            (18U)

+#define ETH_MACECR_USP_Msk                            (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */

+#define ETH_MACECR_USP                                ETH_MACECR_USP_Msk       /* Unicast Slow Protocol Packet Detect */

+#define ETH_MACECR_SPEN_Pos                           (17U)

+#define ETH_MACECR_SPEN_Msk                           (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */

+#define ETH_MACECR_SPEN                               ETH_MACECR_SPEN_Msk      /* Slow Protocol Detection Enable */

+#define ETH_MACECR_DCRCC_Pos                          (16U)

+#define ETH_MACECR_DCRCC_Msk                          (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */

+#define ETH_MACECR_DCRCC                              ETH_MACECR_DCRCC_Msk     /* Disable CRC Checking for Received Packets */

+#define ETH_MACECR_GPSL_Pos                           (0U)

+#define ETH_MACECR_GPSL_Msk                           (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */

+#define ETH_MACECR_GPSL                               ETH_MACECR_GPSL_Msk      /* Giant Packet Size Limit */

+

+/* Bit definition for Ethernet MAC Packet Filter Register */

+#define ETH_MACPFR_RA_Pos                             (31U)

+#define ETH_MACPFR_RA_Msk                             (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */

+#define ETH_MACPFR_RA                                 ETH_MACPFR_RA_Msk        /* Receive all */

+#define ETH_MACPFR_DNTU_Pos                           (21U)

+#define ETH_MACPFR_DNTU_Msk                           (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */

+#define ETH_MACPFR_DNTU                               ETH_MACPFR_DNTU_Msk      /* Drop Non-TCP/UDP over IP Packets */

+#define ETH_MACPFR_IPFE_Pos                           (20U)

+#define ETH_MACPFR_IPFE_Msk                           (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */

+#define ETH_MACPFR_IPFE                               ETH_MACPFR_IPFE_Msk      /* Layer 3 and Layer 4 Filter Enable */

+#define ETH_MACPFR_VTFE_Pos                           (16U)

+#define ETH_MACPFR_VTFE_Msk                           (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */

+#define ETH_MACPFR_VTFE                               ETH_MACPFR_VTFE_Msk      /* VLAN Tag Filter Enable */

+#define ETH_MACPFR_HPF_Pos                            (10U)

+#define ETH_MACPFR_HPF_Msk                            (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */

+#define ETH_MACPFR_HPF                                ETH_MACPFR_HPF_Msk       /* Hash or perfect filter */

+#define ETH_MACPFR_SAF_Pos                            (9U)

+#define ETH_MACPFR_SAF_Msk                            (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */

+#define ETH_MACPFR_SAF                                ETH_MACPFR_SAF_Msk       /* Source address filter enable */

+#define ETH_MACPFR_SAIF_Pos                           (8U)

+#define ETH_MACPFR_SAIF_Msk                           (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */

+#define ETH_MACPFR_SAIF                               ETH_MACPFR_SAIF_Msk      /* SA inverse filtering */

+#define ETH_MACPFR_PCF_Pos                            (6U)

+#define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */

+#define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */

+#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */

+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)

+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */

+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */

+#define ETH_MACPFR_PCF_FORWARDALL_Pos                 (7U)

+#define ETH_MACPFR_PCF_FORWARDALL_Msk                 (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */

+#define ETH_MACPFR_PCF_FORWARDALL                     ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */

+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos    (6U)

+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk    (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */

+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER        ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */

+#define ETH_MACPFR_DBF_Pos                            (5U)

+#define ETH_MACPFR_DBF_Msk                            (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */

+#define ETH_MACPFR_DBF                                ETH_MACPFR_DBF_Msk       /* Disable Broadcast Packets */

+#define ETH_MACPFR_PM_Pos                             (4U)

+#define ETH_MACPFR_PM_Msk                             (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */

+#define ETH_MACPFR_PM                                 ETH_MACPFR_PM_Msk        /* Pass all mutlicast */

+#define ETH_MACPFR_DAIF_Pos                           (3U)

+#define ETH_MACPFR_DAIF_Msk                           (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */

+#define ETH_MACPFR_DAIF                               ETH_MACPFR_DAIF_Msk      /* DA Inverse filtering */

+#define ETH_MACPFR_HMC_Pos                            (2U)

+#define ETH_MACPFR_HMC_Msk                            (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */

+#define ETH_MACPFR_HMC                                ETH_MACPFR_HMC_Msk       /* Hash multicast */

+#define ETH_MACPFR_HUC_Pos                            (1U)

+#define ETH_MACPFR_HUC_Msk                            (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */

+#define ETH_MACPFR_HUC                                ETH_MACPFR_HUC_Msk       /* Hash unicast */

+#define ETH_MACPFR_PR_Pos                             (0U)

+#define ETH_MACPFR_PR_Msk                             (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */

+#define ETH_MACPFR_PR                                 ETH_MACPFR_PR_Msk        /* Promiscuous mode */

+

+/* Bit definition for Ethernet MAC Watchdog Timeout Register */

+#define ETH_MACWTR_PWE_Pos                            (8U)

+#define ETH_MACWTR_PWE_Msk                            (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */

+#define ETH_MACWTR_PWE                                ETH_MACWTR_PWE_Msk       /* Programmable Watchdog Enable */

+#define ETH_MACWTR_WTO_Pos                            (0U)

+#define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */

+#define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */

+#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/

+#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */

+#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */

+#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */

+#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */

+#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */

+#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */

+#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */

+#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */

+#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */

+#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */

+#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */

+#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */

+#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */

+#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */

+

+/* Bit definition for Ethernet MAC Hash Table High Register */

+#define ETH_MACHTHR_HTH_Pos                           (0U)

+#define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */

+

+/* Bit definition for Ethernet MAC Hash Table Low Register */

+#define ETH_MACHTLR_HTL_Pos                           (0U)

+#define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */

+

+/* Bit definition for Ethernet MAC VLAN Tag Register */

+#define ETH_MACVTR_EIVLRXS_Pos                        (31U)

+#define ETH_MACVTR_EIVLRXS_Msk                        (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */

+#define ETH_MACVTR_EIVLRXS                            ETH_MACVTR_EIVLRXS_Msk   /* Enable Inner VLAN Tag in Rx Status */

+#define ETH_MACVTR_EIVLS_Pos                          (28U)

+#define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */

+#define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */

+#define ETH_MACVTR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */

+#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)

+#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */

+#define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */

+#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos             (29U)

+#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk             (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */

+#define ETH_MACVTR_EIVLS_STRIPIFFAILS                 ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */

+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos              (28U)

+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk              (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */

+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP                  ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */

+#define ETH_MACVTR_ERIVLT_Pos                         (27U)

+#define ETH_MACVTR_ERIVLT_Msk                         (0x1UL << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */

+#define ETH_MACVTR_ERIVLT                             ETH_MACVTR_ERIVLT_Msk    /* Enable Inner VLAN Tag */

+#define ETH_MACVTR_EDVLP_Pos                          (26U)

+#define ETH_MACVTR_EDVLP_Msk                          (0x1UL << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */

+#define ETH_MACVTR_EDVLP                              ETH_MACVTR_EDVLP_Msk     /* Enable Double VLAN Processing */

+#define ETH_MACVTR_VTHM_Pos                           (25U)

+#define ETH_MACVTR_VTHM_Msk                           (0x1UL << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */

+#define ETH_MACVTR_VTHM                               ETH_MACVTR_VTHM_Msk      /* VLAN Tag Hash Table Match Enable */

+#define ETH_MACVTR_EVLRXS_Pos                         (24U)

+#define ETH_MACVTR_EVLRXS_Msk                         (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */

+#define ETH_MACVTR_EVLRXS                             ETH_MACVTR_EVLRXS_Msk    /* Enable VLAN Tag in Rx status */

+#define ETH_MACVTR_EVLS_Pos                           (21U)

+#define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */

+#define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */

+#define ETH_MACVTR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */

+#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)

+#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */

+#define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */

+#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos              (22U)

+#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk              (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */

+#define ETH_MACVTR_EVLS_STRIPIFFAILS                  ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */

+#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos               (21U)

+#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk               (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */

+#define ETH_MACVTR_EVLS_ALWAYSSTRIP                   ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */

+#define ETH_MACVTR_DOVLTC_Pos                         (20U)

+#define ETH_MACVTR_DOVLTC_Msk                         (0x1UL << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */

+#define ETH_MACVTR_DOVLTC                             ETH_MACVTR_DOVLTC_Msk    /* Disable VLAN Type Check */

+#define ETH_MACVTR_ERSVLM_Pos                         (19U)

+#define ETH_MACVTR_ERSVLM_Msk                         (0x1UL << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */

+#define ETH_MACVTR_ERSVLM                             ETH_MACVTR_ERSVLM_Msk    /* Enable Receive S-VLAN Match */

+#define ETH_MACVTR_ESVL_Pos                           (18U)

+#define ETH_MACVTR_ESVL_Msk                           (0x1UL << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */

+#define ETH_MACVTR_ESVL                               ETH_MACVTR_ESVL_Msk      /* Enable S-VLAN */

+#define ETH_MACVTR_VTIM_Pos                           (17U)

+#define ETH_MACVTR_VTIM_Msk                           (0x1UL << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */

+#define ETH_MACVTR_VTIM                               ETH_MACVTR_VTIM_Msk      /* VLAN Tag Inverse Match Enable */

+#define ETH_MACVTR_ETV_Pos                            (16U)

+#define ETH_MACVTR_ETV_Msk                            (0x1UL << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */

+#define ETH_MACVTR_ETV                                ETH_MACVTR_ETV_Msk       /* Enable 12-Bit VLAN Tag Comparison */

+#define ETH_MACVTR_VL_Pos                             (0U)

+#define ETH_MACVTR_VL_Msk                             (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */

+#define ETH_MACVTR_VL                                 ETH_MACVTR_VL_Msk        /* VLAN Tag Identifier for Receive Packets */

+#define ETH_MACVTR_VL_UP_Pos                          (13U)

+#define ETH_MACVTR_VL_UP_Msk                          (0x7UL << ETH_MACVTR_VL_UP_Pos) /*!< 0x0000E000 */

+#define ETH_MACVTR_VL_UP                              ETH_MACVTR_VL_UP_Msk     /* User Priority */

+#define ETH_MACVTR_VL_CFIDEI_Pos                      (12U)

+#define ETH_MACVTR_VL_CFIDEI_Msk                      (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos) /*!< 0x00001000 */

+#define ETH_MACVTR_VL_CFIDEI                          ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */

+#define ETH_MACVTR_VL_VID_Pos                         (0U)

+#define ETH_MACVTR_VL_VID_Msk                         (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */

+#define ETH_MACVTR_VL_VID                             ETH_MACVTR_VL_VID_Msk    /* VLAN Identifier field of VLAN tag */

+

+/* Bit definition for Ethernet MAC VLAN Hash Table Register */

+#define ETH_MACVHTR_VLHT_Pos                          (0U)

+#define ETH_MACVHTR_VLHT_Msk                          (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACVHTR_VLHT                              ETH_MACVHTR_VLHT_Msk     /* VLAN Hash Table */

+

+/* Bit definition for Ethernet MAC VLAN Incl Register */

+#define ETH_MACVIR_VLTI_Pos                           (20U)

+#define ETH_MACVIR_VLTI_Msk                           (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */

+#define ETH_MACVIR_VLTI                               ETH_MACVIR_VLTI_Msk      /* VLAN Tag Input */

+#define ETH_MACVIR_CSVL_Pos                           (19U)

+#define ETH_MACVIR_CSVL_Msk                           (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */

+#define ETH_MACVIR_CSVL                               ETH_MACVIR_CSVL_Msk      /* C-VLAN or S-VLAN */

+#define ETH_MACVIR_VLP_Pos                            (18U)

+#define ETH_MACVIR_VLP_Msk                            (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */

+#define ETH_MACVIR_VLP                                ETH_MACVIR_VLP_Msk       /* VLAN Priority Control */

+#define ETH_MACVIR_VLC_Pos                            (16U)

+#define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */

+#define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */

+#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */

+#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)

+#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */

+#define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */

+#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos              (17U)

+#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */

+#define ETH_MACVIR_VLC_VLANTAGINSERT                  ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */

+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos             (16U)

+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk             (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */

+#define ETH_MACVIR_VLC_VLANTAGREPLACE                 ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */

+#define ETH_MACVIR_VLT_Pos                            (0U)

+#define ETH_MACVIR_VLT_Msk                            (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACVIR_VLT                                ETH_MACVIR_VLT_Msk       /* VLAN Tag for Transmit Packets */

+#define ETH_MACVIR_VLT_UP_Pos                         (13U)

+#define ETH_MACVIR_VLT_UP_Msk                         (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */

+#define ETH_MACVIR_VLT_UP                             ETH_MACVIR_VLT_UP_Msk    /* User Priority */

+#define ETH_MACVIR_VLT_CFIDEI_Pos                     (12U)

+#define ETH_MACVIR_VLT_CFIDEI_Msk                     (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */

+#define ETH_MACVIR_VLT_CFIDEI                         ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */

+#define ETH_MACVIR_VLT_VID_Pos                        (0U)

+#define ETH_MACVIR_VLT_VID_Msk                        (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */

+#define ETH_MACVIR_VLT_VID                            ETH_MACVIR_VLT_VID_Msk   /* VLAN Identifier field of VLAN tag */

+

+/* Bit definition for Ethernet MAC Inner_VLAN Incl Register */

+#define ETH_MACIVIR_VLTI_Pos                          (20U)

+#define ETH_MACIVIR_VLTI_Msk                          (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */

+#define ETH_MACIVIR_VLTI                              ETH_MACIVIR_VLTI_Msk     /* VLAN Tag Input */

+#define ETH_MACIVIR_CSVL_Pos                          (19U)

+#define ETH_MACIVIR_CSVL_Msk                          (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */

+#define ETH_MACIVIR_CSVL                              ETH_MACIVIR_CSVL_Msk     /* C-VLAN or S-VLAN */

+#define ETH_MACIVIR_VLP_Pos                           (18U)

+#define ETH_MACIVIR_VLP_Msk                           (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */

+#define ETH_MACIVIR_VLP                               ETH_MACIVIR_VLP_Msk      /* VLAN Priority Control */

+#define ETH_MACIVIR_VLC_Pos                           (16U)

+#define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */

+#define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */

+#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */

+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)

+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */

+#define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */

+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos             (17U)

+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */

+#define ETH_MACIVIR_VLC_VLANTAGINSERT                 ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */

+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos            (16U)

+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk            (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */

+#define ETH_MACIVIR_VLC_VLANTAGREPLACE                ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */

+#define ETH_MACIVIR_VLT_Pos                           (0U)

+#define ETH_MACIVIR_VLT_Msk                           (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACIVIR_VLT                               ETH_MACIVIR_VLT_Msk      /* VLAN Tag for Transmit Packets */

+#define ETH_MACIVIR_VLT_UP_Pos                        (13U)

+#define ETH_MACIVIR_VLT_UP_Msk                        (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */

+#define ETH_MACIVIR_VLT_UP                            ETH_MACIVIR_VLT_UP_Msk   /* User Priority */

+#define ETH_MACIVIR_VLT_CFIDEI_Pos                    (12U)

+#define ETH_MACIVIR_VLT_CFIDEI_Msk                    (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */

+#define ETH_MACIVIR_VLT_CFIDEI                        ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */

+#define ETH_MACIVIR_VLT_VID_Pos                       (0U)

+#define ETH_MACIVIR_VLT_VID_Msk                       (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */

+#define ETH_MACIVIR_VLT_VID                           ETH_MACIVIR_VLT_VID_Msk  /* VLAN Identifier field of VLAN tag */

+

+/* Bit definition for Ethernet MAC Tx Flow Ctrl Register */

+#define ETH_MACTFCR_PT_Pos                            (16U)

+#define ETH_MACTFCR_PT_Msk                            (0xFFFFUL << ETH_MACTFCR_PT_Pos) /*!< 0xFFFF0000 */

+#define ETH_MACTFCR_PT                                ETH_MACTFCR_PT_Msk       /* Pause Time */

+#define ETH_MACTFCR_DZPQ_Pos                          (7U)

+#define ETH_MACTFCR_DZPQ_Msk                          (0x1UL << ETH_MACTFCR_DZPQ_Pos) /*!< 0x00000080 */

+#define ETH_MACTFCR_DZPQ                              ETH_MACTFCR_DZPQ_Msk     /* Disable Zero-Quanta Pause */

+#define ETH_MACTFCR_PLT_Pos                           (4U)

+#define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */

+#define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */

+#define ETH_MACTFCR_PLT_MINUS4                        ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */

+#define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)

+#define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */

+#define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */

+#define ETH_MACTFCR_PLT_MINUS36_Pos                   (5U)

+#define ETH_MACTFCR_PLT_MINUS36_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */

+#define ETH_MACTFCR_PLT_MINUS36                       ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */

+#define ETH_MACTFCR_PLT_MINUS144_Pos                  (4U)

+#define ETH_MACTFCR_PLT_MINUS144_Msk                  (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */

+#define ETH_MACTFCR_PLT_MINUS144                      ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */

+#define ETH_MACTFCR_PLT_MINUS256_Pos                  (6U)

+#define ETH_MACTFCR_PLT_MINUS256_Msk                  (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */

+#define ETH_MACTFCR_PLT_MINUS256                      ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */

+#define ETH_MACTFCR_PLT_MINUS512_Pos                  (4U)

+#define ETH_MACTFCR_PLT_MINUS512_Msk                  (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */

+#define ETH_MACTFCR_PLT_MINUS512                      ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */

+#define ETH_MACTFCR_TFE_Pos                           (1U)

+#define ETH_MACTFCR_TFE_Msk                           (0x1UL << ETH_MACTFCR_TFE_Pos) /*!< 0x00000002 */

+#define ETH_MACTFCR_TFE                               ETH_MACTFCR_TFE_Msk      /* Transmit Flow Control Enable */

+#define ETH_MACTFCR_FCB_Pos                           (0U)

+#define ETH_MACTFCR_FCB_Msk                           (0x1UL << ETH_MACTFCR_FCB_Pos) /*!< 0x00000001 */

+#define ETH_MACTFCR_FCB                               ETH_MACTFCR_FCB_Msk      /* Flow Control Busy or Backpressure Activate */

+

+/* Bit definition for Ethernet MAC Rx Flow Ctrl Register */

+#define ETH_MACRFCR_UP_Pos                            (1U)

+#define ETH_MACRFCR_UP_Msk                            (0x1UL << ETH_MACRFCR_UP_Pos) /*!< 0x00000002 */

+#define ETH_MACRFCR_UP                                ETH_MACRFCR_UP_Msk       /* Unicast Pause Packet Detect */

+#define ETH_MACRFCR_RFE_Pos                           (0U)

+#define ETH_MACRFCR_RFE_Msk                           (0x1UL << ETH_MACRFCR_RFE_Pos) /*!< 0x00000001 */

+#define ETH_MACRFCR_RFE                               ETH_MACRFCR_RFE_Msk      /* Receive Flow Control Enable */

+

+/* Bit definition for Ethernet MAC Interrupt Status Register */

+#define ETH_MACISR_RXSTSIS_Pos                        (14U)

+#define ETH_MACISR_RXSTSIS_Msk                        (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */

+#define ETH_MACISR_RXSTSIS                            ETH_MACISR_RXSTSIS_Msk   /* Receive Status Interrupt */

+#define ETH_MACISR_TXSTSIS_Pos                        (13U)

+#define ETH_MACISR_TXSTSIS_Msk                        (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */

+#define ETH_MACISR_TXSTSIS                            ETH_MACISR_TXSTSIS_Msk   /* Transmit Status Interrupt */

+#define ETH_MACISR_TSIS_Pos                           (12U)

+#define ETH_MACISR_TSIS_Msk                           (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */

+#define ETH_MACISR_TSIS                               ETH_MACISR_TSIS_Msk      /* Timestamp Interrupt Status */

+#define ETH_MACISR_MMCTXIS_Pos                        (10U)

+#define ETH_MACISR_MMCTXIS_Msk                        (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */

+#define ETH_MACISR_MMCTXIS                            ETH_MACISR_MMCTXIS_Msk   /* MMC Transmit Interrupt Status */

+#define ETH_MACISR_MMCRXIS_Pos                        (9U)

+#define ETH_MACISR_MMCRXIS_Msk                        (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */

+#define ETH_MACISR_MMCRXIS                            ETH_MACISR_MMCRXIS_Msk   /* MMC Receive Interrupt Status */

+#define ETH_MACISR_MMCIS_Pos                          (8U)

+#define ETH_MACISR_MMCIS_Msk                          (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */

+#define ETH_MACISR_MMCIS                              ETH_MACISR_MMCIS_Msk     /* MMC Interrupt Status */

+#define ETH_MACISR_LPIIS_Pos                          (5U)

+#define ETH_MACISR_LPIIS_Msk                          (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */

+#define ETH_MACISR_LPIIS                              ETH_MACISR_LPIIS_Msk     /* LPI Interrupt Status */

+#define ETH_MACISR_PMTIS_Pos                          (4U)

+#define ETH_MACISR_PMTIS_Msk                          (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */

+#define ETH_MACISR_PMTIS                              ETH_MACISR_PMTIS_Msk     /* PMT Interrupt Status */

+#define ETH_MACISR_PHYIS_Pos                          (3U)

+#define ETH_MACISR_PHYIS_Msk                          (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */

+#define ETH_MACISR_PHYIS                              ETH_MACISR_PHYIS_Msk     /* PHY Interrupt */

+

+/* Bit definition for Ethernet MAC Interrupt Enable Register */

+#define ETH_MACIER_RXSTSIE_Pos                        (14U)

+#define ETH_MACIER_RXSTSIE_Msk                        (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */

+#define ETH_MACIER_RXSTSIE                            ETH_MACIER_RXSTSIE_Msk   /* Receive Status Interrupt Enable */

+#define ETH_MACIER_TXSTSIE_Pos                        (13U)

+#define ETH_MACIER_TXSTSIE_Msk                        (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */

+#define ETH_MACIER_TXSTSIE                            ETH_MACIER_TXSTSIE_Msk   /* Transmit Status Interrupt Enable */

+#define ETH_MACIER_TSIE_Pos                           (12U)

+#define ETH_MACIER_TSIE_Msk                           (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */

+#define ETH_MACIER_TSIE                               ETH_MACIER_TSIE_Msk      /* Timestamp Interrupt Enable */

+#define ETH_MACIER_LPIIE_Pos                          (5U)

+#define ETH_MACIER_LPIIE_Msk                          (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */

+#define ETH_MACIER_LPIIE                              ETH_MACIER_LPIIE_Msk     /* LPI Interrupt Enable */

+#define ETH_MACIER_PMTIE_Pos                          (4U)

+#define ETH_MACIER_PMTIE_Msk                          (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */

+#define ETH_MACIER_PMTIE                              ETH_MACIER_PMTIE_Msk     /* PMT Interrupt Enable */

+#define ETH_MACIER_PHYIE_Pos                          (3U)

+#define ETH_MACIER_PHYIE_Msk                          (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */

+#define ETH_MACIER_PHYIE                              ETH_MACIER_PHYIE_Msk     /* PHY Interrupt Enable */

+

+/* Bit definition for Ethernet MAC Rx Tx Status Register */

+#define ETH_MACRXTXSR_RWT_Pos                         (8U)

+#define ETH_MACRXTXSR_RWT_Msk                         (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */

+#define ETH_MACRXTXSR_RWT                             ETH_MACRXTXSR_RWT_Msk    /* Receive Watchdog Timeout */

+#define ETH_MACRXTXSR_EXCOL_Pos                       (5U)

+#define ETH_MACRXTXSR_EXCOL_Msk                       (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */

+#define ETH_MACRXTXSR_EXCOL                           ETH_MACRXTXSR_EXCOL_Msk  /* Excessive Collisions */

+#define ETH_MACRXTXSR_LCOL_Pos                        (4U)

+#define ETH_MACRXTXSR_LCOL_Msk                        (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */

+#define ETH_MACRXTXSR_LCOL                            ETH_MACRXTXSR_LCOL_Msk   /* Late Collision */

+#define ETH_MACRXTXSR_EXDEF_Pos                       (3U)

+#define ETH_MACRXTXSR_EXDEF_Msk                       (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */

+#define ETH_MACRXTXSR_EXDEF                           ETH_MACRXTXSR_EXDEF_Msk  /* Excessive Deferral */

+#define ETH_MACRXTXSR_LCARR_Pos                       (2U)

+#define ETH_MACRXTXSR_LCARR_Msk                       (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */

+#define ETH_MACRXTXSR_LCARR                           ETH_MACRXTXSR_LCARR_Msk  /* Loss of Carrier */

+#define ETH_MACRXTXSR_NCARR_Pos                       (1U)

+#define ETH_MACRXTXSR_NCARR_Msk                       (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */

+#define ETH_MACRXTXSR_NCARR                           ETH_MACRXTXSR_NCARR_Msk  /* No Carrier */

+#define ETH_MACRXTXSR_TJT_Pos                         (0U)

+#define ETH_MACRXTXSR_TJT_Msk                         (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */

+#define ETH_MACRXTXSR_TJT                             ETH_MACRXTXSR_TJT_Msk    /* Transmit Jabber Timeout */

+

+/* Bit definition for Ethernet MAC PMT Control Status Register */

+#define ETH_MACPCSR_RWKFILTRST_Pos                    (31U)

+#define ETH_MACPCSR_RWKFILTRST_Msk                    (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */

+#define ETH_MACPCSR_RWKFILTRST                        ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */

+#define ETH_MACPCSR_RWKPTR_Pos                        (24U)

+#define ETH_MACPCSR_RWKPTR_Msk                        (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */

+#define ETH_MACPCSR_RWKPTR                            ETH_MACPCSR_RWKPTR_Msk   /* Remote Wake-up FIFO Pointer */

+#define ETH_MACPCSR_RWKPFE_Pos                        (10U)

+#define ETH_MACPCSR_RWKPFE_Msk                        (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */

+#define ETH_MACPCSR_RWKPFE                            ETH_MACPCSR_RWKPFE_Msk   /* Remote Wake-up Packet Forwarding Enable */

+#define ETH_MACPCSR_GLBLUCAST_Pos                     (9U)

+#define ETH_MACPCSR_GLBLUCAST_Msk                     (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */

+#define ETH_MACPCSR_GLBLUCAST                         ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */

+#define ETH_MACPCSR_RWKPRCVD_Pos                      (6U)

+#define ETH_MACPCSR_RWKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */

+#define ETH_MACPCSR_RWKPRCVD                          ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */

+#define ETH_MACPCSR_MGKPRCVD_Pos                      (5U)

+#define ETH_MACPCSR_MGKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */

+#define ETH_MACPCSR_MGKPRCVD                          ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */

+#define ETH_MACPCSR_RWKPKTEN_Pos                      (2U)

+#define ETH_MACPCSR_RWKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */

+#define ETH_MACPCSR_RWKPKTEN                          ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */

+#define ETH_MACPCSR_MGKPKTEN_Pos                      (1U)

+#define ETH_MACPCSR_MGKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */

+#define ETH_MACPCSR_MGKPKTEN                          ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */

+#define ETH_MACPCSR_PWRDWN_Pos                        (0U)

+#define ETH_MACPCSR_PWRDWN_Msk                        (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */

+#define ETH_MACPCSR_PWRDWN                            ETH_MACPCSR_PWRDWN_Msk   /* Power Down */

+

+/* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */

+#define ETH_MACRWUPFR_D_Pos                           (0U)

+#define ETH_MACRWUPFR_D_Msk                           (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACRWUPFR_D                               ETH_MACRWUPFR_D_Msk      /* Wake-up Packet filter register data */

+

+/* Bit definition for Ethernet MAC LPI Control Status Register */

+#define ETH_MACLCSR_LPITCSE_Pos                       (21U)

+#define ETH_MACLCSR_LPITCSE_Msk                       (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */

+#define ETH_MACLCSR_LPITCSE                           ETH_MACLCSR_LPITCSE_Msk  /* LPI Tx Clock Stop Enable */

+#define ETH_MACLCSR_LPITE_Pos                         (20U)

+#define ETH_MACLCSR_LPITE_Msk                         (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */

+#define ETH_MACLCSR_LPITE                             ETH_MACLCSR_LPITE_Msk    /* LPI Timer Enable */

+#define ETH_MACLCSR_LPITXA_Pos                        (19U)

+#define ETH_MACLCSR_LPITXA_Msk                        (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */

+#define ETH_MACLCSR_LPITXA                            ETH_MACLCSR_LPITXA_Msk   /* LPI Tx Automate */

+#define ETH_MACLCSR_PLS_Pos                           (17U)

+#define ETH_MACLCSR_PLS_Msk                           (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */

+#define ETH_MACLCSR_PLS                               ETH_MACLCSR_PLS_Msk      /* PHY Link Status */

+#define ETH_MACLCSR_LPIEN_Pos                         (16U)

+#define ETH_MACLCSR_LPIEN_Msk                         (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */

+#define ETH_MACLCSR_LPIEN                             ETH_MACLCSR_LPIEN_Msk    /* LPI Enable */

+#define ETH_MACLCSR_RLPIST_Pos                        (9U)

+#define ETH_MACLCSR_RLPIST_Msk                        (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */

+#define ETH_MACLCSR_RLPIST                            ETH_MACLCSR_RLPIST_Msk   /* Receive LPI State */

+#define ETH_MACLCSR_TLPIST_Pos                        (8U)

+#define ETH_MACLCSR_TLPIST_Msk                        (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */

+#define ETH_MACLCSR_TLPIST                            ETH_MACLCSR_TLPIST_Msk   /* Transmit LPI State */

+#define ETH_MACLCSR_RLPIEX_Pos                        (3U)

+#define ETH_MACLCSR_RLPIEX_Msk                        (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */

+#define ETH_MACLCSR_RLPIEX                            ETH_MACLCSR_RLPIEX_Msk   /* Receive LPI Exit */

+#define ETH_MACLCSR_RLPIEN_Pos                        (2U)

+#define ETH_MACLCSR_RLPIEN_Msk                        (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */

+#define ETH_MACLCSR_RLPIEN                            ETH_MACLCSR_RLPIEN_Msk   /* Receive LPI Entry */

+#define ETH_MACLCSR_TLPIEX_Pos                        (1U)

+#define ETH_MACLCSR_TLPIEX_Msk                        (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */

+#define ETH_MACLCSR_TLPIEX                            ETH_MACLCSR_TLPIEX_Msk   /* Transmit LPI Exit */

+#define ETH_MACLCSR_TLPIEN_Pos                        (0U)

+#define ETH_MACLCSR_TLPIEN_Msk                        (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */

+#define ETH_MACLCSR_TLPIEN                            ETH_MACLCSR_TLPIEN_Msk   /* Transmit LPI Entry */

+

+/* Bit definition for Ethernet MAC LPI Timers Control Register */

+#define ETH_MACLTCR_LST_Pos                           (16U)

+#define ETH_MACLTCR_LST_Msk                           (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */

+#define ETH_MACLTCR_LST                               ETH_MACLTCR_LST_Msk      /* LPI LS TIMER */

+#define ETH_MACLTCR_TWT_Pos                           (0U)

+#define ETH_MACLTCR_TWT_Msk                           (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACLTCR_TWT                               ETH_MACLTCR_TWT_Msk      /* LPI TW TIMER */

+

+/* Bit definition for Ethernet MAC LPI Entry Timer Register */

+#define ETH_MACLETR_LPIET_Pos                         (0U)

+#define ETH_MACLETR_LPIET_Msk                         (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */

+#define ETH_MACLETR_LPIET                             ETH_MACLETR_LPIET_Msk    /* LPI Entry Timer */

+

+/* Bit definition for Ethernet MAC 1US Tic Counter Register */

+#define ETH_MAC1USTCR_TIC1USCNTR_Pos                  (0U)

+#define ETH_MAC1USTCR_TIC1USCNTR_Msk                  (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */

+#define ETH_MAC1USTCR_TIC1USCNTR                      ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */

+

+/* Bit definition for Ethernet MAC Version Register */

+#define ETH_MACVR_USERVER_Pos                         (8U)

+#define ETH_MACVR_USERVER_Msk                         (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */

+#define ETH_MACVR_USERVER                             ETH_MACVR_USERVER_Msk    /* User-defined Version */

+#define ETH_MACVR_SNPSVER_Pos                         (0U)

+#define ETH_MACVR_SNPSVER_Msk                         (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */

+#define ETH_MACVR_SNPSVER                             ETH_MACVR_SNPSVER_Msk    /* Synopsys-defined Version */

+

+/* Bit definition for Ethernet MAC Debug Register */

+#define ETH_MACDR_TFCSTS_Pos                          (17U)

+#define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */

+#define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */

+#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */

+#define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)

+#define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */

+#define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */

+#define ETH_MACDR_TFCSTS_GENERATEPCP_Pos              (18U)

+#define ETH_MACDR_TFCSTS_GENERATEPCP_Msk              (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */

+#define ETH_MACDR_TFCSTS_GENERATEPCP                  ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */

+#define ETH_MACDR_TFCSTS_TRASFERIP_Pos                (17U)

+#define ETH_MACDR_TFCSTS_TRASFERIP_Msk                (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */

+#define ETH_MACDR_TFCSTS_TRASFERIP                    ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */

+#define ETH_MACDR_TPESTS_Pos                          (16U)

+#define ETH_MACDR_TPESTS_Msk                          (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */

+#define ETH_MACDR_TPESTS                              ETH_MACDR_TPESTS_Msk     /* MAC Receive Packet Controller FIFO Status */

+#define ETH_MACDR_RFCFCSTS_Pos                        (1U)

+#define ETH_MACDR_RFCFCSTS_Msk                        (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */

+#define ETH_MACDR_RFCFCSTS                            ETH_MACDR_RFCFCSTS_Msk   /* MAC MII Transmit Protocol Engine Status */

+#define ETH_MACDR_RPESTS_Pos                          (0U)

+#define ETH_MACDR_RPESTS_Msk                          (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */

+#define ETH_MACDR_RPESTS                              ETH_MACDR_RPESTS_Msk     /* MAC MII Receive Protocol Engine Status */

+

+/* Bit definition for Ethernet MAC HW Feature0 Register */

+#define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)

+#define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */

+#define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */

+#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */

+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)

+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */

+#define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */

+#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos             (28U)

+#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk             (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos) /*!< 0x70000000 */

+#define ETH_MACHWF0R_ACTPHYSEL_REVMII                 ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */

+#define ETH_MACHWF0R_SAVLANINS_Pos                    (27U)

+#define ETH_MACHWF0R_SAVLANINS_Msk                    (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */

+#define ETH_MACHWF0R_SAVLANINS                        ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */

+#define ETH_MACHWF0R_TSSTSSEL_Pos                     (25U)

+#define ETH_MACHWF0R_TSSTSSEL_Msk                     (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */

+#define ETH_MACHWF0R_TSSTSSEL                         ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */

+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos            (25U)

+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */

+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL                ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */

+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos            (26U)

+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */

+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL                ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */

+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos                (25U)

+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk                (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */

+#define ETH_MACHWF0R_TSSTSSEL_BOTH                    ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */

+#define ETH_MACHWF0R_MACADR64SEL_Pos                  (24U)

+#define ETH_MACHWF0R_MACADR64SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */

+#define ETH_MACHWF0R_MACADR64SEL                      ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */

+#define ETH_MACHWF0R_MACADR32SEL_Pos                  (23U)

+#define ETH_MACHWF0R_MACADR32SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */

+#define ETH_MACHWF0R_MACADR32SEL                      ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */

+#define ETH_MACHWF0R_ADDMACADRSEL_Pos                 (18U)

+#define ETH_MACHWF0R_ADDMACADRSEL_Msk                 (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */

+#define ETH_MACHWF0R_ADDMACADRSEL                     ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */

+#define ETH_MACHWF0R_RXCOESEL_Pos                     (16U)

+#define ETH_MACHWF0R_RXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */

+#define ETH_MACHWF0R_RXCOESEL                         ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */

+#define ETH_MACHWF0R_TXCOESEL_Pos                     (14U)

+#define ETH_MACHWF0R_TXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */

+#define ETH_MACHWF0R_TXCOESEL                         ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */

+#define ETH_MACHWF0R_EEESEL_Pos                       (13U)

+#define ETH_MACHWF0R_EEESEL_Msk                       (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */

+#define ETH_MACHWF0R_EEESEL                           ETH_MACHWF0R_EEESEL_Msk  /* Energy Efficient Ethernet Enabled */

+#define ETH_MACHWF0R_TSSEL_Pos                        (12U)

+#define ETH_MACHWF0R_TSSEL_Msk                        (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */

+#define ETH_MACHWF0R_TSSEL                            ETH_MACHWF0R_TSSEL_Msk   /* IEEE 1588-2008 Timestamp Enabled */

+#define ETH_MACHWF0R_ARPOFFSEL_Pos                    (9U)

+#define ETH_MACHWF0R_ARPOFFSEL_Msk                    (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */

+#define ETH_MACHWF0R_ARPOFFSEL                        ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */

+#define ETH_MACHWF0R_MMCSEL_Pos                       (8U)

+#define ETH_MACHWF0R_MMCSEL_Msk                       (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */

+#define ETH_MACHWF0R_MMCSEL                           ETH_MACHWF0R_MMCSEL_Msk  /* RMON Module Enable */

+#define ETH_MACHWF0R_MGKSEL_Pos                       (7U)

+#define ETH_MACHWF0R_MGKSEL_Msk                       (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */

+#define ETH_MACHWF0R_MGKSEL                           ETH_MACHWF0R_MGKSEL_Msk  /* PMT Magic Packet Enable */

+#define ETH_MACHWF0R_RWKSEL_Pos                       (6U)

+#define ETH_MACHWF0R_RWKSEL_Msk                       (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */

+#define ETH_MACHWF0R_RWKSEL                           ETH_MACHWF0R_RWKSEL_Msk  /* PMT Remote Wake-up Packet Enable */

+#define ETH_MACHWF0R_SMASEL_Pos                       (5U)

+#define ETH_MACHWF0R_SMASEL_Msk                       (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */

+#define ETH_MACHWF0R_SMASEL                           ETH_MACHWF0R_SMASEL_Msk  /* SMA (MDIO) Interface */

+#define ETH_MACHWF0R_VLHASH_Pos                       (4U)

+#define ETH_MACHWF0R_VLHASH_Msk                       (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */

+#define ETH_MACHWF0R_VLHASH                           ETH_MACHWF0R_VLHASH_Msk  /* VLAN Hash Filter Selected */

+#define ETH_MACHWF0R_PCSSEL_Pos                       (3U)

+#define ETH_MACHWF0R_PCSSEL_Msk                       (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */

+#define ETH_MACHWF0R_PCSSEL                           ETH_MACHWF0R_PCSSEL_Msk  /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */

+#define ETH_MACHWF0R_HDSEL_Pos                        (2U)

+#define ETH_MACHWF0R_HDSEL_Msk                        (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */

+#define ETH_MACHWF0R_HDSEL                            ETH_MACHWF0R_HDSEL_Msk   /* Half-duplex Support */

+#define ETH_MACHWF0R_GMIISEL_Pos                      (1U)

+#define ETH_MACHWF0R_GMIISEL_Msk                      (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */

+#define ETH_MACHWF0R_GMIISEL                          ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */

+#define ETH_MACHWF0R_MIISEL_Pos                       (0U)

+#define ETH_MACHWF0R_MIISEL_Msk                       (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */

+#define ETH_MACHWF0R_MIISEL                           ETH_MACHWF0R_MIISEL_Msk  /* 10 or 100 Mbps Support */

+

+/* Bit definition for Ethernet MAC HW Feature1 Register */

+#define ETH_MACHWF1R_L3L4FNUM_Pos                     (27U)

+#define ETH_MACHWF1R_L3L4FNUM_Msk                     (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */

+#define ETH_MACHWF1R_L3L4FNUM                         ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */

+#define ETH_MACHWF1R_HASHTBLSZ_Pos                    (24U)

+#define ETH_MACHWF1R_HASHTBLSZ_Msk                    (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */

+#define ETH_MACHWF1R_HASHTBLSZ                        ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */

+#define ETH_MACHWF1R_AVSEL_Pos                        (20U)

+#define ETH_MACHWF1R_AVSEL_Msk                        (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */

+#define ETH_MACHWF1R_AVSEL                            ETH_MACHWF1R_AVSEL_Msk   /* AV Feature Enabled */

+#define ETH_MACHWF1R_DBGMEMA_Pos                      (19U)

+#define ETH_MACHWF1R_DBGMEMA_Msk                      (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */

+#define ETH_MACHWF1R_DBGMEMA                          ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */

+#define ETH_MACHWF1R_TSOEN_Pos                        (18U)

+#define ETH_MACHWF1R_TSOEN_Msk                        (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */

+#define ETH_MACHWF1R_TSOEN                            ETH_MACHWF1R_TSOEN_Msk   /* TCP Segmentation Offload Enable */

+#define ETH_MACHWF1R_SPHEN_Pos                        (17U)

+#define ETH_MACHWF1R_SPHEN_Msk                        (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */

+#define ETH_MACHWF1R_SPHEN                            ETH_MACHWF1R_SPHEN_Msk   /* Split Header Feature Enable */

+#define ETH_MACHWF1R_DCBEN_Pos                        (16U)

+#define ETH_MACHWF1R_DCBEN_Msk                        (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */

+#define ETH_MACHWF1R_DCBEN                            ETH_MACHWF1R_DCBEN_Msk   /* DCB Feature Enable */

+#define ETH_MACHWF1R_ADDR64_Pos                       (14U)

+#define ETH_MACHWF1R_ADDR64_Msk                       (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */

+#define ETH_MACHWF1R_ADDR64                           ETH_MACHWF1R_ADDR64_Msk  /* Address Width */

+#define ETH_MACHWF1R_ADDR64_32                        (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */

+#define ETH_MACHWF1R_ADDR64_40                        (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */

+#define ETH_MACHWF1R_ADDR64_48                        (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */

+#define ETH_MACHWF1R_ADVTHWORD_Pos                    (13U)

+#define ETH_MACHWF1R_ADVTHWORD_Msk                    (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */

+#define ETH_MACHWF1R_ADVTHWORD                        ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */

+#define ETH_MACHWF1R_PTOEN_Pos                        (12U)

+#define ETH_MACHWF1R_PTOEN_Msk                        (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */

+#define ETH_MACHWF1R_PTOEN                            ETH_MACHWF1R_PTOEN_Msk   /* PTP Offload Enable */

+#define ETH_MACHWF1R_OSTEN_Pos                        (11U)

+#define ETH_MACHWF1R_OSTEN_Msk                        (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */

+#define ETH_MACHWF1R_OSTEN                            ETH_MACHWF1R_OSTEN_Msk   /* One-Step Timestamping Enable */

+#define ETH_MACHWF1R_TXFIFOSIZE_Pos                   (6U)

+#define ETH_MACHWF1R_TXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */

+#define ETH_MACHWF1R_TXFIFOSIZE                       ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */

+#define ETH_MACHWF1R_RXFIFOSIZE_Pos                   (0U)

+#define ETH_MACHWF1R_RXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */

+#define ETH_MACHWF1R_RXFIFOSIZE                       ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */

+

+/* Bit definition for Ethernet MAC HW Feature2 Register */

+#define ETH_MACHWF2R_AUXSNAPNUM_Pos                   (28U)

+#define ETH_MACHWF2R_AUXSNAPNUM_Msk                   (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */

+#define ETH_MACHWF2R_AUXSNAPNUM                       ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */

+#define ETH_MACHWF2R_PPSOUTNUM_Pos                    (24U)

+#define ETH_MACHWF2R_PPSOUTNUM_Msk                    (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */

+#define ETH_MACHWF2R_PPSOUTNUM                        ETH_MACHWF2R_PPSOUTNUM_Msk /*  Number of PPS Outputs */

+#define ETH_MACHWF2R_TXCHCNT_Pos                      (18U)

+#define ETH_MACHWF2R_TXCHCNT_Msk                      (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */

+#define ETH_MACHWF2R_TXCHCNT                          ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */

+#define ETH_MACHWF2R_RXCHCNT_Pos                      (13U)

+#define ETH_MACHWF2R_RXCHCNT_Msk                      (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000E000 */

+#define ETH_MACHWF2R_RXCHCNT                          ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */

+#define ETH_MACHWF2R_TXQCNT_Pos                       (6U)

+#define ETH_MACHWF2R_TXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */

+#define ETH_MACHWF2R_TXQCNT                           ETH_MACHWF2R_TXQCNT_Msk  /* Number of MTL Transmit Queues */

+#define ETH_MACHWF2R_RXQCNT_Pos                       (0U)

+#define ETH_MACHWF2R_RXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */

+#define ETH_MACHWF2R_RXQCNT                           ETH_MACHWF2R_RXQCNT_Msk  /* Number of MTL Receive Queues */

+

+/* Bit definition for Ethernet MAC MDIO Address Register */

+#define ETH_MACMDIOAR_PSE_Pos                         (27U)

+#define ETH_MACMDIOAR_PSE_Msk                         (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */

+#define ETH_MACMDIOAR_PSE                             ETH_MACMDIOAR_PSE_Msk    /* Preamble Suppression Enable */

+#define ETH_MACMDIOAR_BTB_Pos                         (26U)

+#define ETH_MACMDIOAR_BTB_Msk                         (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */

+#define ETH_MACMDIOAR_BTB                             ETH_MACMDIOAR_BTB_Msk    /* Back to Back transactions */

+#define ETH_MACMDIOAR_PA_Pos                          (21U)

+#define ETH_MACMDIOAR_PA_Msk                          (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */

+#define ETH_MACMDIOAR_PA                              ETH_MACMDIOAR_PA_Msk     /* Physical Layer Address */

+#define ETH_MACMDIOAR_RDA_Pos                         (16U)

+#define ETH_MACMDIOAR_RDA_Msk                         (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */

+#define ETH_MACMDIOAR_RDA                             ETH_MACMDIOAR_RDA_Msk    /* Register/Device Address */

+#define ETH_MACMDIOAR_NTC_Pos                         (12U)

+#define ETH_MACMDIOAR_NTC_Msk                         (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */

+#define ETH_MACMDIOAR_NTC                             ETH_MACMDIOAR_NTC_Msk    /* Number of Trailing Clocks */

+#define ETH_MACMDIOAR_CR_Pos                          (8U)

+#define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */

+#define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */

+#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */

+#define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)

+#define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */

+#define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */

+#define ETH_MACMDIOAR_CR_DIV16_Pos                    (9U)

+#define ETH_MACMDIOAR_CR_DIV16_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */

+#define ETH_MACMDIOAR_CR_DIV16                        ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */

+#define ETH_MACMDIOAR_CR_DIV26_Pos                    (8U)

+#define ETH_MACMDIOAR_CR_DIV26_Msk                    (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */

+#define ETH_MACMDIOAR_CR_DIV26                        ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */

+#define ETH_MACMDIOAR_CR_DIV102_Pos                   (10U)

+#define ETH_MACMDIOAR_CR_DIV102_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */

+#define ETH_MACMDIOAR_CR_DIV102                       ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */

+#define ETH_MACMDIOAR_CR_DIV124_Pos                   (8U)

+#define ETH_MACMDIOAR_CR_DIV124_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */

+#define ETH_MACMDIOAR_CR_DIV124                       ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */

+#define ETH_MACMDIOAR_CR_DIV4AR_Pos                   (11U)

+#define ETH_MACMDIOAR_CR_DIV4AR_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */

+#define ETH_MACMDIOAR_CR_DIV4AR                       ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV6AR_Pos                   (8U)

+#define ETH_MACMDIOAR_CR_DIV6AR_Msk                   (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */

+#define ETH_MACMDIOAR_CR_DIV6AR                       ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV8AR_Pos                   (9U)

+#define ETH_MACMDIOAR_CR_DIV8AR_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */

+#define ETH_MACMDIOAR_CR_DIV8AR                       ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV10AR_Pos                  (8U)

+#define ETH_MACMDIOAR_CR_DIV10AR_Msk                  (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */

+#define ETH_MACMDIOAR_CR_DIV10AR                      ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV12AR_Pos                  (10U)

+#define ETH_MACMDIOAR_CR_DIV12AR_Msk                  (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */

+#define ETH_MACMDIOAR_CR_DIV12AR                      ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV14AR_Pos                  (8U)

+#define ETH_MACMDIOAR_CR_DIV14AR_Msk                  (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */

+#define ETH_MACMDIOAR_CR_DIV14AR                      ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV16AR_Pos                  (9U)

+#define ETH_MACMDIOAR_CR_DIV16AR_Msk                  (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */

+#define ETH_MACMDIOAR_CR_DIV16AR                      ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV18AR_Pos                  (8U)

+#define ETH_MACMDIOAR_CR_DIV18AR_Msk                  (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */

+#define ETH_MACMDIOAR_CR_DIV18AR                      ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_SKAP_Pos                        (4U)

+#define ETH_MACMDIOAR_SKAP_Msk                        (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */

+#define ETH_MACMDIOAR_SKAP                            ETH_MACMDIOAR_SKAP_Msk   /* Skip Address Packet */

+#define ETH_MACMDIOAR_MOC_Pos                         (2U)

+#define ETH_MACMDIOAR_MOC_Msk                         (0x3UL << ETH_MACMDIOAR_MOC_Pos) /*!< 0x0000000C */

+#define ETH_MACMDIOAR_MOC                             ETH_MACMDIOAR_MOC_Msk    /* MII Operation Command */

+#define ETH_MACMDIOAR_MOC_WR_Pos                      (2U)

+#define ETH_MACMDIOAR_MOC_WR_Msk                      (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos) /*!< 0x00000004 */

+#define ETH_MACMDIOAR_MOC_WR                          ETH_MACMDIOAR_MOC_WR_Msk /* Write */

+#define ETH_MACMDIOAR_MOC_PRDIA_Pos                   (3U)

+#define ETH_MACMDIOAR_MOC_PRDIA_Msk                   (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos) /*!< 0x00000008 */

+#define ETH_MACMDIOAR_MOC_PRDIA                       ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */

+#define ETH_MACMDIOAR_MOC_RD_Pos                      (2U)

+#define ETH_MACMDIOAR_MOC_RD_Msk                      (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos) /*!< 0x0000000C */

+#define ETH_MACMDIOAR_MOC_RD                          ETH_MACMDIOAR_MOC_RD_Msk /* Read */

+#define ETH_MACMDIOAR_C45E_Pos                        (1U)

+#define ETH_MACMDIOAR_C45E_Msk                        (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */

+#define ETH_MACMDIOAR_C45E                            ETH_MACMDIOAR_C45E_Msk   /* Clause 45 PHY Enable */

+#define ETH_MACMDIOAR_MB_Pos                          (0U)

+#define ETH_MACMDIOAR_MB_Msk                          (0x1UL << ETH_MACMDIOAR_MB_Pos) /*!< 0x00000001 */

+#define ETH_MACMDIOAR_MB                              ETH_MACMDIOAR_MB_Msk     /* MII Busy */

+

+/* Bit definition for Ethernet MAC MDIO Data Register */

+#define ETH_MACMDIODR_RA_Pos                          (16U)

+#define ETH_MACMDIODR_RA_Msk                          (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */

+#define ETH_MACMDIODR_RA                              ETH_MACMDIODR_RA_Msk     /* Register Address */

+#define ETH_MACMDIODR_MD_Pos                          (0U)

+#define ETH_MACMDIODR_MD_Msk                          (0xFFFFUL << ETH_MACMDIODR_MD_Pos) /*!< 0x0000FFFF */

+#define ETH_MACMDIODR_MD                              ETH_MACMDIODR_MD_Msk     /* MII Data */

+

+/* Bit definition for Ethernet ARP Address Register */

+#define ETH_MACARPAR_ARPPA_Pos                         (0U)

+#define ETH_MACARPAR_ARPPA_Msk                         (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACARPAR_ARPPA                             ETH_MACARPAR_ARPPA_Msk     /* ARP Protocol Address */

+

+/* Bit definition for Ethernet MAC Address 0 High Register */

+#define ETH_MACA0HR_AE_Pos                            (31U)

+#define ETH_MACA0HR_AE_Msk                            (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA0HR_AE                                ETH_MACA0HR_AE_Msk /* Address Enable*/

+#define ETH_MACA0HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA0HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA0HR_ADDRHI                            ETH_MACA0HR_ADDRHI_Msk   /* MAC Address 0*/

+

+/* Bit definition for Ethernet MAC Address 0 Low Register */

+#define ETH_MACA0LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA0LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA0LR_ADDRLO                            ETH_MACA0LR_ADDRLO_Msk   /* MAC Address 0*/

+

+/* Bit definition for Ethernet MAC Address 1 High Register */

+#define ETH_MACA1HR_AE_Pos                            (31U)

+#define ETH_MACA1HR_AE_Msk                            (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk /* Address Enable*/

+#define ETH_MACA1HR_SA_Pos                            (30U)

+#define ETH_MACA1HR_SA_Msk                            (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk /* Source Address */

+#define ETH_MACA1HR_MBC_Pos                           (24U)

+#define ETH_MACA1HR_MBC_Msk                           (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk /* Mask Byte Control */

+#define ETH_MACA1HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA1HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA1HR_ADDRHI                            ETH_MACA1HR_ADDRHI_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 1 Low Register */

+#define ETH_MACA1LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA1LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA1LR_ADDRLO                            ETH_MACA1LR_ADDRLO_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 2 High Register */

+#define ETH_MACA2HR_AE_Pos                            (31U)

+#define ETH_MACA2HR_AE_Msk                            (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk /* Address Enable*/

+#define ETH_MACA2HR_SA_Pos                            (30U)

+#define ETH_MACA2HR_SA_Msk                            (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk /* Source Address */

+#define ETH_MACA2HR_MBC_Pos                           (24U)

+#define ETH_MACA2HR_MBC_Msk                           (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk /* Mask Byte Control */

+#define ETH_MACA2HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA2HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA2HR_ADDRHI                            ETH_MACA2HR_ADDRHI_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 2 Low Register */

+#define ETH_MACA2LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA2LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA2LR_ADDRLO                            ETH_MACA2LR_ADDRLO_Msk   /* MAC Address 2*/

+

+/* Bit definition for Ethernet MAC Address 3 High Register */

+#define ETH_MACA3HR_AE_Pos                            (31U)

+#define ETH_MACA3HR_AE_Msk                            (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk /* Address Enable*/

+#define ETH_MACA3HR_SA_Pos                            (30U)

+#define ETH_MACA3HR_SA_Msk                            (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk /* Source Address */

+#define ETH_MACA3HR_MBC_Pos                           (24U)

+#define ETH_MACA3HR_MBC_Msk                           (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk /* Mask Byte Control */

+#define ETH_MACA3HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA3HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA3HR_ADDRHI                            ETH_MACA3HR_ADDRHI_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 3 Low Register */

+#define ETH_MACA3LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA3LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA3LR_ADDRLO                            ETH_MACA3LR_ADDRLO_Msk   /* MAC Address 3*/

+

+/* Bit definition for Ethernet MAC Address High Register */

+#define ETH_MACAHR_AE_Pos                             (31U)

+#define ETH_MACAHR_AE_Msk                             (0x1UL << ETH_MACAHR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACAHR_AE                                 ETH_MACAHR_AE_Msk        /* Address enable */

+#define ETH_MACAHR_SA_Pos                             (30U)

+#define ETH_MACAHR_SA_Msk                             (0x1UL << ETH_MACAHR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACAHR_SA                                 ETH_MACAHR_SA_Msk        /* Source address */

+#define ETH_MACAHR_MBC_Pos                            (24U)

+#define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */

+#define ETH_MACAHR_MBC_HBITS15_8                      ((uint32_t)0x20000000)   /* Mask MAC Address high reg bits [15:8] */

+#define ETH_MACAHR_MBC_HBITS7_0                       ((uint32_t)0x10000000)   /* Mask MAC Address high reg bits [7:0] */

+#define ETH_MACAHR_MBC_LBITS31_24                     ((uint32_t)0x08000000)   /* Mask MAC Address low reg bits [31:24] */

+#define ETH_MACAHR_MBC_LBITS23_16                     ((uint32_t)0x04000000)   /* Mask MAC Address low reg bits [23:16] */

+#define ETH_MACAHR_MBC_LBITS15_8                      ((uint32_t)0x02000000)   /* Mask MAC Address low reg bits [15:8] */

+#define ETH_MACAHR_MBC_LBITS7_0                       ((uint32_t)0x01000000)   /* Mask MAC Address low reg bits [7:0] */

+#define ETH_MACAHR_MACAH_Pos                          (0U)

+#define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */

+#define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */

+

+/* Bit definition for Ethernet MAC Address Low Register */

+#define ETH_MACALR_MACAL_Pos                          (0U)

+#define ETH_MACALR_MACAL_Msk                          (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACALR_MACAL                              ETH_MACALR_MACAL_Msk     /* MAC address low */

+

+/* Bit definition for Ethernet MMC Control Register */

+#define ETH_MMCCR_UCDBC_Pos                           (8U)

+#define ETH_MMCCR_UCDBC_Msk                           (0x1UL << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */

+#define ETH_MMCCR_UCDBC                               ETH_MMCCR_UCDBC_Msk  /* Update MMC Counters for Dropped Broadcast Packets */

+#define ETH_MMCCR_CNTPRSTLVL_Pos                      (5U)

+#define ETH_MMCCR_CNTPRSTLVL_Msk                      (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */

+#define ETH_MMCCR_CNTPRSTLVL                          ETH_MMCCR_CNTPRSTLVL_Msk  /* Full-Half Preset */

+#define ETH_MMCCR_CNTPRST_Pos                         (4U)

+#define ETH_MMCCR_CNTPRST_Msk                         (0x1UL << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */

+#define ETH_MMCCR_CNTPRST                             ETH_MMCCR_CNTPRST_Msk  /* Counters Reset */

+#define ETH_MMCCR_CNTFREEZ_Pos                        (3U)

+#define ETH_MMCCR_CNTFREEZ_Msk                        (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */

+#define ETH_MMCCR_CNTFREEZ                            ETH_MMCCR_CNTFREEZ_Msk  /* MMC Counter Freeze */

+#define ETH_MMCCR_RSTONRD_Pos                         (2U)

+#define ETH_MMCCR_RSTONRD_Msk                         (0x1UL << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */

+#define ETH_MMCCR_RSTONRD                             ETH_MMCCR_RSTONRD_Msk  /* Reset On Read */

+#define ETH_MMCCR_CNTSTOPRO_Pos                       (1U)

+#define ETH_MMCCR_CNTSTOPRO_Msk                       (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */

+#define ETH_MMCCR_CNTSTOPRO                           ETH_MMCCR_CNTSTOPRO_Msk  /* Counter Stop Rollover */

+#define ETH_MMCCR_CNTRST_Pos                          (0U)

+#define ETH_MMCCR_CNTRST_Msk                          (0x1UL << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */

+#define ETH_MMCCR_CNTRST                              ETH_MMCCR_CNTRST_Msk  /* Counters Reset */

+

+/* Bit definition for Ethernet MMC Rx Interrupt Register */

+#define ETH_MMCRIR_RXLPITRCIS_Pos                     (27U)

+#define ETH_MMCRIR_RXLPITRCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) /*!< 0x08000000 */

+#define ETH_MMCRIR_RXLPITRCIS                         ETH_MMCRIR_RXLPITRCIS_Msk  /* MMC Receive LPI transition counter interrupt status */

+#define ETH_MMCRIR_RXLPIUSCIS_Pos                     (26U)

+#define ETH_MMCRIR_RXLPIUSCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */

+#define ETH_MMCRIR_RXLPIUSCIS                         ETH_MMCRIR_RXLPIUSCIS_Msk  /* MMC Receive LPI microsecond counter interrupt status */

+#define ETH_MMCRIR_RXUCGPIS_Pos                       (17U)

+#define ETH_MMCRIR_RXUCGPIS_Msk                       (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) /*!< 0x00020000 */

+#define ETH_MMCRIR_RXUCGPIS                           ETH_MMCRIR_RXUCGPIS_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Status */

+#define ETH_MMCRIR_RXALGNERPIS_Pos                    (6U)

+#define ETH_MMCRIR_RXALGNERPIS_Msk                    (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) /*!< 0x00000040 */

+#define ETH_MMCRIR_RXALGNERPIS                        ETH_MMCRIR_RXALGNERPIS_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Status */

+#define ETH_MMCRIR_RXCRCERPIS_Pos                     (5U)

+#define ETH_MMCRIR_RXCRCERPIS_Msk                     (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) /*!< 0x00000020 */

+#define ETH_MMCRIR_RXCRCERPIS                         ETH_MMCRIR_RXCRCERPIS_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Status */

+

+/* Bit definition for Ethernet MMC Tx Interrupt Register */

+#define ETH_MMCTIR_TXLPITRCIS_Pos                     (27U)

+#define ETH_MMCTIR_TXLPITRCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) /*!< 0x08000000 */

+#define ETH_MMCTIR_TXLPITRCIS                         ETH_MMCTIR_TXLPITRCIS_Msk  /* MMC Transmit LPI transition counter interrupt status */

+#define ETH_MMCTIR_TXLPIUSCIS_Pos                     (26U)

+#define ETH_MMCTIR_TXLPIUSCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */

+#define ETH_MMCTIR_TXLPIUSCIS                         ETH_MMCTIR_TXLPIUSCIS_Msk  /* MMC Transmit LPI microsecond counter interrupt status */

+#define ETH_MMCTIR_TXGPKTIS_Pos                       (21U)

+#define ETH_MMCTIR_TXGPKTIS_Msk                       (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) /*!< 0x00200000 */

+#define ETH_MMCTIR_TXGPKTIS                           ETH_MMCTIR_TXGPKTIS_Msk  /* MMC Transmit Good Packet Counter Interrupt Status */

+#define ETH_MMCTIR_TXMCOLGPIS_Pos                     (15U)

+#define ETH_MMCTIR_TXMCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */

+#define ETH_MMCTIR_TXMCOLGPIS                         ETH_MMCTIR_TXMCOLGPIS_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */

+#define ETH_MMCTIR_TXSCOLGPIS_Pos                     (14U)

+#define ETH_MMCTIR_TXSCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */

+#define ETH_MMCTIR_TXSCOLGPIS                         ETH_MMCTIR_TXSCOLGPIS_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */

+

+/* Bit definition for Ethernet MMC Rx interrupt Mask register */

+#define ETH_MMCRIMR_RXLPITRCIM_Pos                    (27U)

+#define ETH_MMCRIMR_RXLPITRCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */

+#define ETH_MMCRIMR_RXLPITRCIM                        ETH_MMCRIMR_RXLPITRCIM_Msk  /* MMC Receive LPI transition counter interrupt Mask */

+#define ETH_MMCRIMR_RXLPIUSCIM_Pos                    (26U)

+#define ETH_MMCRIMR_RXLPIUSCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */

+#define ETH_MMCRIMR_RXLPIUSCIM                        ETH_MMCRIMR_RXLPIUSCIM_Msk  /* MMC Receive LPI microsecond counter interrupt Mask */

+#define ETH_MMCRIMR_RXUCGPIM_Pos                      (17U)

+#define ETH_MMCRIMR_RXUCGPIM_Msk                      (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) /*!< 0x00020000 */

+#define ETH_MMCRIMR_RXUCGPIM                          ETH_MMCRIMR_RXUCGPIM_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Mask */

+#define ETH_MMCRIMR_RXALGNERPIM_Pos                   (6U)

+#define ETH_MMCRIMR_RXALGNERPIM_Msk                   (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */

+#define ETH_MMCRIMR_RXALGNERPIM                       ETH_MMCRIMR_RXALGNERPIM_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Mask */

+#define ETH_MMCRIMR_RXCRCERPIM_Pos                    (5U)

+#define ETH_MMCRIMR_RXCRCERPIM_Msk                    (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */

+#define ETH_MMCRIMR_RXCRCERPIM                        ETH_MMCRIMR_RXCRCERPIM_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Mask */

+

+/* Bit definition for Ethernet MMC Tx Interrupt Mask Register */

+#define ETH_MMCTIMR_TXLPITRCIM_Pos                    (27U)

+#define ETH_MMCTIMR_TXLPITRCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */

+#define ETH_MMCTIMR_TXLPITRCIM                        ETH_MMCTIMR_TXLPITRCIM_Msk  /* MMC Transmit LPI transition counter interrupt Mask*/

+#define ETH_MMCTIMR_TXLPIUSCIM_Pos                    (26U)

+#define ETH_MMCTIMR_TXLPIUSCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */

+#define ETH_MMCTIMR_TXLPIUSCIM                        ETH_MMCTIMR_TXLPIUSCIM_Msk  /* MMC Transmit LPI microsecond counter interrupt Mask*/

+#define ETH_MMCTIMR_TXGPKTIM_Pos                      (21U)

+#define ETH_MMCTIMR_TXGPKTIM_Msk                      (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) /*!< 0x00200000 */

+#define ETH_MMCTIMR_TXGPKTIM                          ETH_MMCTIMR_TXGPKTIM_Msk  /* MMC Transmit Good Packet Counter Interrupt Mask*/

+#define ETH_MMCTIMR_TXMCOLGPIM_Pos                    (15U)

+#define ETH_MMCTIMR_TXMCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */

+#define ETH_MMCTIMR_TXMCOLGPIM                        ETH_MMCTIMR_TXMCOLGPIM_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */

+#define ETH_MMCTIMR_TXSCOLGPIM_Pos                    (14U)

+#define ETH_MMCTIMR_TXSCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */

+#define ETH_MMCTIMR_TXSCOLGPIM                        ETH_MMCTIMR_TXSCOLGPIM_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */

+

+/* Bit definition for Ethernet MMC Tx Single Collision Good Packets Register */

+#define ETH_MMCTSCGPR_TXSNGLCOLG_Pos                  (0U)

+#define ETH_MMCTSCGPR_TXSNGLCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTSCGPR_TXSNGLCOLG                      ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */

+

+/* Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register */

+#define ETH_MMCTMCGPR_TXMULTCOLG_Pos                  (0U)

+#define ETH_MMCTMCGPR_TXMULTCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTMCGPR_TXMULTCOLG                      ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */

+

+/* Bit definition for Ethernet MMC Tx Packet Count Good Register */

+#define ETH_MMCTPCGR_TXPKTG_Pos                       (0U)

+#define ETH_MMCTPCGR_TXPKTG_msk                       (0xFFFFFFFFUL <<  ETH_MMCTPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTPCGR_TXPKTG                           ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */

+

+/* Bit definition for Ethernet MMC Rx CRC Error Packets Register */

+#define ETH_MMCRCRCEPR_RXCRCERR_Pos                   (0U)

+#define ETH_MMCRCRCEPR_RXCRCERR_msk                   (0xFFFFFFFFUL <<  ETH_MMCRCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRCRCEPR_RXCRCERR                       ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */

+

+/* Bit definition for Ethernet MMC Rx alignment error packets register */

+#define ETH_MMCRAEPR_RXALGNERR_Pos                    (0U)

+#define ETH_MMCRAEPR_RXALGNERR_msk                    (0xFFFFFFFFUL <<  ETH_MMCRAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRAEPR_RXALGNERR                        ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */

+

+/* Bit definition for Ethernet MMC Rx Unicast Packets Good Register */

+#define ETH_MMCRUPGR_RXUCASTG_Pos                     (0U)

+#define ETH_MMCRUPGR_RXUCASTG_msk                     (0xFFFFFFFFUL <<  ETH_MMCRUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRUPGR_RXUCASTG                         ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */

+

+/* Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register */

+#define ETH_MMCTLPIMSTR_TXLPIUSC_Pos                  (0U)

+#define ETH_MMCTLPIMSTR_TXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCTLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTLPIMSTR_TXLPIUSC                      ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */

+

+/* Bit definition for Ethernet MMC Tx LPI Transition Counter Register */

+#define ETH_MMCTLPITCR_TXLPITRC_Pos                   (0U)

+#define ETH_MMCTLPITCR_TXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCTLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTLPITCR_TXLPITRC                       ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */

+

+/* Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register */

+#define ETH_MMCRLPIMSTR_RXLPIUSC_Pos                  (0U)

+#define ETH_MMCRLPIMSTR_RXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCRLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRLPIMSTR_RXLPIUSC                      ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */

+

+/* Bit definition for Ethernet MMC Rx LPI Transition Counter Register */

+#define ETH_MMCRLPITCR_RXLPITRC_Pos                   (0U)

+#define ETH_MMCRLPITCR_RXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCRLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRLPITCR_RXLPITRC                       ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */

+

+/* Bit definition for Ethernet MAC L3 L4 Control Register */

+#define ETH_MACL3L4CR_L4DPIM_Pos                      (21U)

+#define ETH_MACL3L4CR_L4DPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos) /*!< 0x00200000 */

+#define ETH_MACL3L4CR_L4DPIM                          ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */

+#define ETH_MACL3L4CR_L4DPM_Pos                       (20U)

+#define ETH_MACL3L4CR_L4DPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4DPM_Pos) /*!< 0x00100000 */

+#define ETH_MACL3L4CR_L4DPM                           ETH_MACL3L4CR_L4DPM_Msk  /* Layer 4 Destination Port Match Enable */

+#define ETH_MACL3L4CR_L4SPIM_Pos                      (19U)

+#define ETH_MACL3L4CR_L4SPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos) /*!< 0x00080000 */

+#define ETH_MACL3L4CR_L4SPIM                          ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */

+#define ETH_MACL3L4CR_L4SPM_Pos                       (18U)

+#define ETH_MACL3L4CR_L4SPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4SPM_Pos) /*!< 0x00040000 */

+#define ETH_MACL3L4CR_L4SPM                           ETH_MACL3L4CR_L4SPM_Msk  /* Layer 4 Source Port Match Enable */

+#define ETH_MACL3L4CR_L4PEN_Pos                       (16U)

+#define ETH_MACL3L4CR_L4PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L4PEN_Pos) /*!< 0x00010000 */

+#define ETH_MACL3L4CR_L4PEN                           ETH_MACL3L4CR_L4PEN_Msk  /* Layer 4 Protocol Enable */

+#define ETH_MACL3L4CR_L3HDBM_Pos                      (11U)

+#define ETH_MACL3L4CR_L3HDBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos) /*!< 0x0000F800 */

+#define ETH_MACL3L4CR_L3HDBM                          ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */

+#define ETH_MACL3L4CR_L3HSBM_Pos                      (6U)

+#define ETH_MACL3L4CR_L3HSBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos) /*!< 0x000007C0 */

+#define ETH_MACL3L4CR_L3HSBM                          ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */

+#define ETH_MACL3L4CR_L3DAIM_Pos                      (5U)

+#define ETH_MACL3L4CR_L3DAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos) /*!< 0x00000020 */

+#define ETH_MACL3L4CR_L3DAIM                          ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */

+#define ETH_MACL3L4CR_L3DAM_Pos                       (4U)

+#define ETH_MACL3L4CR_L3DAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3DAM_Pos) /*!< 0x00000010 */

+#define ETH_MACL3L4CR_L3DAM                           ETH_MACL3L4CR_L3DAM_Msk  /* Layer 3 IP DA Match Enable */

+#define ETH_MACL3L4CR_L3SAIM_Pos                      (3U)

+#define ETH_MACL3L4CR_L3SAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos) /*!< 0x00000008 */

+#define ETH_MACL3L4CR_L3SAIM                          ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */

+#define ETH_MACL3L4CR_L3SAM_Pos                       (2U)

+#define ETH_MACL3L4CR_L3SAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3SAM_Pos) /*!< 0x00000004 */

+#define ETH_MACL3L4CR_L3SAM                           ETH_MACL3L4CR_L3SAM_Msk  /* Layer 3 IP SA Match Enable*/

+#define ETH_MACL3L4CR_L3PEN_Pos                       (0U)

+#define ETH_MACL3L4CR_L3PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L3PEN_Pos) /*!< 0x00000001 */

+#define ETH_MACL3L4CR_L3PEN                           ETH_MACL3L4CR_L3PEN_Msk  /* Layer 3 Protocol Enable */

+

+/* Bit definition for Ethernet MAC L4 Address Register */

+#define ETH_MACL4AR_L4DP_Pos                          (16U)

+#define ETH_MACL4AR_L4DP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4DP_Pos) /*!< 0xFFFF0000 */

+#define ETH_MACL4AR_L4DP                              ETH_MACL4AR_L4DP_Msk     /* Layer 4 Destination Port Number Field */

+#define ETH_MACL4AR_L4SP_Pos                          (0U)

+#define ETH_MACL4AR_L4SP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4SP_Pos) /*!< 0x0000FFFF */

+#define ETH_MACL4AR_L4SP                              ETH_MACL4AR_L4SP_Msk     /* Layer 4 Source Port Number Field */

+

+/* Bit definition for Ethernet MAC L3 Address0 Register */

+#define ETH_MACL3A0R_L3A0_Pos                         (0U)

+#define ETH_MACL3A0R_L3A0_Msk                         (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A0R_L3A0                             ETH_MACL3A0R_L3A0_Msk    /* Layer 3 Address 0 Field */

+

+/* Bit definition for Ethernet MAC L4 Address1 Register */

+#define ETH_MACL3A1R_L3A1_Pos                         (0U)

+#define ETH_MACL3A1R_L3A1_Msk                         (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A1R_L3A1                             ETH_MACL3A1R_L3A1_Msk    /* Layer 3 Address 1 Field */

+

+/* Bit definition for Ethernet MAC L4 Address2 Register */

+#define ETH_MACL3A2R_L3A2_Pos                         (0U)

+#define ETH_MACL3A2R_L3A2_Msk                         (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A2R_L3A2                             ETH_MACL3A2R_L3A2_Msk    /* Layer 3 Address 2 Field */

+

+/* Bit definition for Ethernet MAC L4 Address3 Register */

+#define ETH_MACL3A3R_L3A3_Pos                         (0U)

+#define ETH_MACL3A3R_L3A3_Msk                         (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A3R_L3A3                             ETH_MACL3A3R_L3A3_Msk    /* Layer 3 Address 3 Field */

+

+/* Bit definition for Ethernet MAC Timestamp Control Register */

+#define ETH_MACTSCR_TXTSSTSM_Pos                      (24U)

+#define ETH_MACTSCR_TXTSSTSM_Msk                      (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */

+#define ETH_MACTSCR_TXTSSTSM                          ETH_MACTSCR_TXTSSTSM_Msk  /* Transmit Timestamp Status Mode */

+#define ETH_MACTSCR_CSC_Pos                           (19U)

+#define ETH_MACTSCR_CSC_Msk                           (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */

+#define ETH_MACTSCR_CSC                               ETH_MACTSCR_CSC_Msk  /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */

+#define ETH_MACTSCR_TSENMACADDR_Pos                   (18U)

+#define ETH_MACTSCR_TSENMACADDR_Msk                   (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */

+#define ETH_MACTSCR_TSENMACADDR                       ETH_MACTSCR_TSENMACADDR_Msk  /* Enable MAC Address for PTP Packet Filtering */

+#define ETH_MACTSCR_SNAPTYPSEL_Pos                    (16U)

+#define ETH_MACTSCR_SNAPTYPSEL_Msk                    (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */

+#define ETH_MACTSCR_SNAPTYPSEL                        ETH_MACTSCR_SNAPTYPSEL_Msk  /* Select PTP packets for Taking Snapshots */

+#define ETH_MACTSCR_TSMSTRENA_Pos                     (15U)

+#define ETH_MACTSCR_TSMSTRENA_Msk                     (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */

+#define ETH_MACTSCR_TSMSTRENA                         ETH_MACTSCR_TSMSTRENA_Msk  /* Enable Snapshot for Messages Relevant to Master */

+#define ETH_MACTSCR_TSEVNTENA_Pos                     (14U)

+#define ETH_MACTSCR_TSEVNTENA_Msk                     (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */

+#define ETH_MACTSCR_TSEVNTENA                         ETH_MACTSCR_TSEVNTENA_Msk  /* Enable Timestamp Snapshot for Event Messages */

+#define ETH_MACTSCR_TSIPV4ENA_Pos                     (13U)

+#define ETH_MACTSCR_TSIPV4ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */

+#define ETH_MACTSCR_TSIPV4ENA                         ETH_MACTSCR_TSIPV4ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv4-UDP */

+#define ETH_MACTSCR_TSIPV6ENA_Pos                     (12U)

+#define ETH_MACTSCR_TSIPV6ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */

+#define ETH_MACTSCR_TSIPV6ENA                         ETH_MACTSCR_TSIPV6ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv6-UDP */

+#define ETH_MACTSCR_TSIPENA_Pos                       (11U)

+#define ETH_MACTSCR_TSIPENA_Msk                       (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */

+#define ETH_MACTSCR_TSIPENA                           ETH_MACTSCR_TSIPENA_Msk  /* Enable Processing of PTP over Ethernet Packets */

+#define ETH_MACTSCR_TSVER2ENA_Pos                     (10U)

+#define ETH_MACTSCR_TSVER2ENA_Msk                     (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */

+#define ETH_MACTSCR_TSVER2ENA                         ETH_MACTSCR_TSVER2ENA_Msk  /* Enable PTP Packet Processing for Version 2 Format */

+#define ETH_MACTSCR_TSCTRLSSR_Pos                     (9U)

+#define ETH_MACTSCR_TSCTRLSSR_Msk                     (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */

+#define ETH_MACTSCR_TSCTRLSSR                         ETH_MACTSCR_TSCTRLSSR_Msk  /* Timestamp Digital or Binary Rollover Control */

+#define ETH_MACTSCR_TSENALL_Pos                       (8U)

+#define ETH_MACTSCR_TSENALL_Msk                       (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */

+#define ETH_MACTSCR_TSENALL                           ETH_MACTSCR_TSENALL_Msk  /* Enable Timestamp for All Packets */

+#define ETH_MACTSCR_TSADDREG_Pos                      (5U)

+#define ETH_MACTSCR_TSADDREG_Msk                      (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */

+#define ETH_MACTSCR_TSADDREG                          ETH_MACTSCR_TSADDREG_Msk  /* Update Addend Register */

+#define ETH_MACTSCR_TSUPDT_Pos                        (3U)

+#define ETH_MACTSCR_TSUPDT_Msk                        (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */

+#define ETH_MACTSCR_TSUPDT                            ETH_MACTSCR_TSUPDT_Msk  /* Update Timestamp */

+#define ETH_MACTSCR_TSINIT_Pos                        (2U)

+#define ETH_MACTSCR_TSINIT_Msk                        (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */

+#define ETH_MACTSCR_TSINIT                             ETH_MACTSCR_TSINIT_Msk  /* Initialize Timestamp */

+#define ETH_MACTSCR_TSCFUPDT_Pos                      (1U)

+#define ETH_MACTSCR_TSCFUPDT_Msk                      (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */

+#define ETH_MACTSCR_TSCFUPDT                          ETH_MACTSCR_TSCFUPDT_Msk  /* Fine or Coarse Timestamp Update*/

+#define ETH_MACTSCR_TSENA_Pos                         (0U)

+#define ETH_MACTSCR_TSENA_Msk                         (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */

+#define ETH_MACTSCR_TSENA                             ETH_MACTSCR_TSENA_Msk  /* Enable Timestamp */

+

+/* Bit definition for Ethernet MAC Sub-second Increment Register */

+#define ETH_MACMACSSIR_SSINC_Pos                      (16U)

+#define ETH_MACMACSSIR_SSINC_Msk                      (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) /*!< 0x0000FF00 */

+#define ETH_MACMACSSIR_SSINC                          ETH_MACMACSSIR_SSINC_Msk  /* Sub-second Increment Value */

+#define ETH_MACMACSSIR_SNSINC_Pos                     (8U)

+#define ETH_MACMACSSIR_SNSINC_Msk                     (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos) /*!< 0x000000FF */

+#define ETH_MACMACSSIR_SNSINC                         ETH_MACMACSSIR_SNSINC_Msk  /* Sub-nanosecond Increment Value */

+

+/* Bit definition for Ethernet MAC System Time Seconds Register */

+#define ETH_MACSTSR_TSS_Pos                           (0U)

+#define ETH_MACSTSR_TSS_Msk                           (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSTSR_TSS                               ETH_MACSTSR_TSS_Msk  /* Timestamp Second */

+

+/* Bit definition for Ethernet MAC System Time Nanoseconds Register */

+#define ETH_MACSTNR_TSSS_Pos                          (0U)

+#define ETH_MACSTNR_TSSS_Msk                          (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACSTNR_TSSS                              ETH_MACSTNR_TSSS_Msk  /* Timestamp Sub-seconds */

+

+/* Bit definition for Ethernet MAC System Time Seconds Update Register */

+#define ETH_MACSTSUR_TSS_Pos                          (0U)

+#define ETH_MACSTSUR_TSS_Msk                          (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSTSUR_TSS                              ETH_MACSTSUR_TSS_Msk  /* Timestamp Seconds */

+

+/* Bit definition for Ethernet MAC System Time Nanoseconds Update Register */

+#define ETH_MACSTNUR_ADDSUB_Pos                       (31U)

+#define ETH_MACSTNUR_ADDSUB_Msk                       (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */

+#define ETH_MACSTNUR_ADDSUB                           ETH_MACSTNUR_ADDSUB_Msk  /* Add or Subtract Time */

+#define ETH_MACSTNUR_TSSS_Pos                         (0U)

+#define ETH_MACSTNUR_TSSS_Msk                         (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACSTNUR_TSSS                             ETH_MACSTNUR_TSSS_Msk  /* Timestamp Sub-seconds */

+

+/* Bit definition for Ethernet MAC Timestamp Addend Register */

+#define ETH_MACTSAR_TSAR_Pos                          (0U)

+#define ETH_MACTSAR_TSAR_Msk                          (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSAR_TSAR                              ETH_MACTSAR_TSAR_Msk  /* Timestamp Addend Register */

+

+/* Bit definition for Ethernet MAC Timestamp Status Register */

+#define ETH_MACTSSR_ATSNS_Pos                         (25U)

+#define ETH_MACTSSR_ATSNS_Msk                         (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */

+#define ETH_MACTSSR_ATSNS                             ETH_MACTSSR_ATSNS_Msk  /* Number of Auxiliary Timestamp Snapshots */

+#define ETH_MACTSSR_ATSSTM_Pos                        (24U)

+#define ETH_MACTSSR_ATSSTM_Msk                        (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */

+#define ETH_MACTSSR_ATSSTM                            ETH_MACTSSR_ATSSTM_Msk  /* Auxiliary Timestamp Snapshot Trigger Missed */

+#define ETH_MACTSSR_ATSSTN_Pos                        (16U)

+#define ETH_MACTSSR_ATSSTN_Msk                        (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */

+#define ETH_MACTSSR_ATSSTN                            ETH_MACTSSR_ATSSTN_Msk  /* Auxiliary Timestamp Snapshot Trigger Identifier */

+#define ETH_MACTSSR_TXTSSIS_Pos                       (15U)

+#define ETH_MACTSSR_TXTSSIS_Msk                       (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */

+#define ETH_MACTSSR_TXTSSIS                           ETH_MACTSSR_TXTSSIS_Msk  /* Tx Timestamp Status Interrupt Status */

+#define ETH_MACTSSR_TSTRGTERR0_Pos                    (3U)

+#define ETH_MACTSSR_TSTRGTERR0_Msk                    (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */

+#define ETH_MACTSSR_TSTRGTERR0                        ETH_MACTSSR_TSTRGTERR0_Msk  /* Timestamp Target Time Error */

+#define ETH_MACTSSR_AUXTSTRIG_Pos                     (2U)

+#define ETH_MACTSSR_AUXTSTRIG_Msk                     (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */

+#define ETH_MACTSSR_AUXTSTRIG                         ETH_MACTSSR_AUXTSTRIG_Msk  /* Auxiliary Timestamp Trigger Snapshot*/

+#define ETH_MACTSSR_TSTARGT0_Pos                      (1U)

+#define ETH_MACTSSR_TSTARGT0_Msk                      (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */

+#define ETH_MACTSSR_TSTARGT0                          ETH_MACTSSR_TSTARGT0_Msk  /* Timestamp Target Time Reached */

+#define ETH_MACTSSR_TSSOVF_Pos                        (0U)

+#define ETH_MACTSSR_TSSOVF_Msk                        (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */

+#define ETH_MACTSSR_TSSOVF                            ETH_MACTSSR_TSSOVF_Msk  /* Timestamp Seconds Overflow */

+

+/* Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register */

+#define ETH_MACTTSSNR_TXTSSMIS_Pos                    (31U)

+#define ETH_MACTTSSNR_TXTSSMIS_Msk                    (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */

+#define ETH_MACTTSSNR_TXTSSMIS                        ETH_MACTTSSNR_TXTSSMIS_Msk  /* Transmit Timestamp Status Missed */

+#define ETH_MACTTSSNR_TXTSSLO_Pos                     (0U)

+#define ETH_MACTTSSNR_TXTSSLO_Msk                     (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACTTSSNR_TXTSSLO                         ETH_MACTTSSNR_TXTSSLO_Msk  /* Transmit Timestamp Status Low */

+

+/* Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register */

+#define ETH_MACTTSSSR_TXTSSHI_Pos                     (0U)

+#define ETH_MACTTSSSR_TXTSSHI_Msk                     (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTTSSSR_TXTSSHI                         ETH_MACTTSSSR_TXTSSHI_Msk  /* Transmit Timestamp Status High */

+

+/* Bit definition for Ethernet MAC Auxiliary Control Register*/

+#define ETH_MACACR_ATSEN3_Pos                         (7U)

+#define ETH_MACACR_ATSEN3_Msk                         (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */

+#define ETH_MACACR_ATSEN3                             ETH_MACACR_ATSEN3_Msk  /* Auxiliary Snapshot 3 Enable */

+#define ETH_MACACR_ATSEN2_Pos                         (6U)

+#define ETH_MACACR_ATSEN2_Msk                         (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */

+#define ETH_MACACR_ATSEN2                             ETH_MACACR_ATSEN2_Msk  /* Auxiliary Snapshot 2 Enable */

+#define ETH_MACACR_ATSEN1_Pos                         (5U)

+#define ETH_MACACR_ATSEN1_Msk                         (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */

+#define ETH_MACACR_ATSEN1                             ETH_MACACR_ATSEN1_Msk  /* Auxiliary Snapshot 1 Enable */

+#define ETH_MACACR_ATSEN0_Pos                         (4U)

+#define ETH_MACACR_ATSEN0_Msk                         (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */

+#define ETH_MACACR_ATSEN0                             ETH_MACACR_ATSEN0_Msk  /* Auxiliary Snapshot 0 Enable */

+#define ETH_MACACR_ATSFC_Pos                          (0U)

+#define ETH_MACACR_ATSFC_Msk                          (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */

+#define ETH_MACACR_ATSFC                              ETH_MACACR_ATSFC_Msk  /* Auxiliary Snapshot FIFO Clear */

+

+/* Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register */

+#define ETH_MACATSNR_AUXTSLO_Pos                      (0U)

+#define ETH_MACATSNR_AUXTSLO_Msk                      (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACATSNR_AUXTSLO                          ETH_MACATSNR_AUXTSLO_Msk  /* Auxiliary Timestamp */

+

+/* Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register */

+#define ETH_MACATSSR_AUXTSHI_Pos                      (0U)

+#define ETH_MACATSSR_AUXTSHI_Msk                      (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACATSSR_AUXTSHI                          ETH_MACATSSR_AUXTSHI_Msk  /* Auxiliary Timestamp */

+

+/* Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register */

+#define ETH_MACTSIACR_OSTIAC_Pos                      (0U)

+#define ETH_MACTSIACR_OSTIAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSIACR_OSTIAC                          ETH_MACTSIACR_OSTIAC_Msk  /* One-Step Timestamp Ingress Asymmetry Correction */

+

+/* Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction Register */

+#define ETH_MACTSEACR_OSTEAC_Pos                      (0U)

+#define ETH_MACTSEACR_OSTEAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSEACR_OSTEAC                          ETH_MACTSEACR_OSTEAC_Msk  /* One-Step Timestamp Egress Asymmetry Correction */

+

+/* Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond Register */

+#define ETH_MACTSICNR_TSIC_Pos                        (0U)

+#define ETH_MACTSICNR_TSIC_Msk                        (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSICNR_TSIC                            ETH_MACTSICNR_TSIC_Msk  /* Timestamp Ingress Correction */

+

+/* Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond Register */

+#define ETH_MACTSECNR_TSEC_Pos                        (0U)

+#define ETH_MACTSECNR_TSEC_Msk                        (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSECNR_TSEC                            ETH_MACTSECNR_TSEC_Msk  /* Timestamp Egress Correction */

+

+/* Bit definition for Ethernet MAC PPS Control Register */

+#define ETH_MACPPSCR_TRGTMODSEL0_Pos                  (5U)

+#define ETH_MACPPSCR_TRGTMODSEL0_Msk                  (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */

+#define ETH_MACPPSCR_TRGTMODSEL0                      ETH_MACPPSCR_TRGTMODSEL0_Msk  /* Target Time Register Mode for PPS Output */

+#define ETH_MACPPSCR_PPSEN0_Pos                       (4U)

+#define ETH_MACPPSCR_PPSEN0_Msk                       (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */

+#define ETH_MACPPSCR_PPSEN0                           ETH_MACPPSCR_PPSEN0_Msk  /* Flexible PPS Output Mode Enable */

+#define ETH_MACPPSCR_PPSCTRL_Pos                      (0U)

+#define ETH_MACPPSCR_PPSCTRL_Msk                      (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */

+#define ETH_MACPPSCR_PPSCTRL                          ETH_MACPPSCR_PPSCTRL_Msk  /* PPS Output Frequency Control */

+

+/* Bit definition for Ethernet MAC PPS Target Time Seconds Register */

+#define ETH_MACPPSTTSR_TSTRH0_Pos                     (0U)

+#define ETH_MACPPSTTSR_TSTRH0_Msk                     (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACPPSTTSR_TSTRH0                         ETH_MACPPSTTSR_TSTRH0_Msk  /* PPS Target Time Seconds Register */

+

+/* Bit definition for Ethernet MAC PPS Target Time Nanoseconds Register */

+#define ETH_MACPPSTTNR_TRGTBUSY0_Pos                  (31U)

+#define ETH_MACPPSTTNR_TRGTBUSY0_Msk                  (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos) /*!< 0x80000000 */

+#define ETH_MACPPSTTNR_TRGTBUSY0                      ETH_MACPPSTTNR_TRGTBUSY0_Msk  /* PPS Target Time Register Busy */

+#define ETH_MACPPSTTNR_TTSL0_Pos                      (0U)

+#define ETH_MACPPSTTNR_TTSL0_Msk                      (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACPPSTTNR_TTSL0                          ETH_MACPPSTTNR_TTSL0_Msk  /* Target Time Low for PPS Register */

+

+/* Bit definition for Ethernet MAC PPS Interval Register */

+#define ETH_MACPPSIR_PPSINT0_Pos                      (0U)

+#define ETH_MACPPSIR_PPSINT0_Msk                      (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACPPSIR_PPSINT0                          ETH_MACPPSIR_PPSINT0_Msk  /* PPS Output Signal Interval */

+

+/* Bit definition for Ethernet MAC PPS Width Register */

+#define ETH_MACPPSWR_PPSWIDTH0_Pos                    (0U)

+#define ETH_MACPPSWR_PPSWIDTH0_Msk                    (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACPPSWR_PPSWIDTH0                        ETH_MACPPSWR_PPSWIDTH0_Msk  /* PPS Output Signal Width */

+

+/* Bit definition for Ethernet MAC PTP Offload Control Register */

+#define ETH_MACPOCR_DN_Pos                            (8U)

+#define ETH_MACPOCR_DN_Msk                            (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */

+#define ETH_MACPOCR_DN                                ETH_MACPOCR_DN_Msk  /* Domain Number */

+#define ETH_MACPOCR_DRRDIS_Pos                        (6U)

+#define ETH_MACPOCR_DRRDIS_Msk                        (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */

+#define ETH_MACPOCR_DRRDIS                            ETH_MACPOCR_DRRDIS_Msk  /* Disable PTO Delay Request/Response response generation */

+#define ETH_MACPOCR_APDREQTRIG_Pos                    (5U)

+#define ETH_MACPOCR_APDREQTRIG_Msk                    (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */

+#define ETH_MACPOCR_APDREQTRIG                        ETH_MACPOCR_APDREQTRIG_Msk  /* Automatic PTP Pdelay_Req message Trigger */

+#define ETH_MACPOCR_ASYNCTRIG_Pos                     (4U)

+#define ETH_MACPOCR_ASYNCTRIG_Msk                     (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */

+#define ETH_MACPOCR_ASYNCTRIG                         ETH_MACPOCR_ASYNCTRIG_Msk  /* Automatic PTP SYNC message Trigger */

+#define ETH_MACPOCR_APDREQEN_Pos                      (2U)

+#define ETH_MACPOCR_APDREQEN_Msk                      (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */

+#define ETH_MACPOCR_APDREQEN                          ETH_MACPOCR_APDREQEN_Msk  /* Automatic PTP Pdelay_Req message Enable */

+#define ETH_MACPOCR_ASYNCEN_Pos                       (1U)

+#define ETH_MACPOCR_ASYNCEN_Msk                       (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */

+#define ETH_MACPOCR_ASYNCEN                           ETH_MACPOCR_ASYNCEN_Msk  /* Automatic PTP SYNC message Enable */

+#define ETH_MACPOCR_PTOEN_Pos                         (0U)

+#define ETH_MACPOCR_PTOEN_Msk                         (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */

+#define ETH_MACPOCR_PTOEN                             ETH_MACPOCR_PTOEN_Msk  /* PTP Offload Enable */

+

+/* Bit definition for Ethernet MAC PTP Source Port Identity 0 Register */

+#define ETH_MACSPI0R_SPI0_Pos                         (0U)

+#define ETH_MACSPI0R_SPI0_Msk                         (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSPI0R_SPI0                             ETH_MACSPI0R_SPI0_Msk  /* Source Port Identity 0 */

+

+/* Bit definition for Ethernet MAC PTP Source Port Identity 1 Register */

+#define ETH_MACSPI1R_SPI1_Pos                         (0U)

+#define ETH_MACSPI1R_SPI1_Msk                         (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSPI1R_SPI1                             ETH_MACSPI1R_SPI1_Msk  /* Source Port Identity 1 */

+

+/* Bit definition for Ethernet MAC PTP Source Port Identity 2 Register */

+#define ETH_MACSPI2R_SPI2_Pos                         (0U)

+#define ETH_MACSPI2R_SPI2_Msk                         (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */

+#define ETH_MACSPI2R_SPI2                             ETH_MACSPI2R_SPI2_Msk  /* Source Port Identity 2 */

+

+/* Bit definition for Ethernet MAC Log Message Interval Register */

+#define ETH_MACLMIR_LMPDRI_Pos                        (24U)

+#define ETH_MACLMIR_LMPDRI_Msk                        (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */

+#define ETH_MACLMIR_LMPDRI                             ETH_MACLMIR_LMPDRI_Msk  /* Log Min Pdelay_Req Interval */

+#define ETH_MACLMIR_DRSYNCR_Pos                       (8U)

+#define ETH_MACLMIR_DRSYNCR_Msk                       (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */

+#define ETH_MACLMIR_DRSYNCR                           ETH_MACLMIR_DRSYNCR_Msk  /* Delay_Req to SYNC Ratio */

+#define ETH_MACLMIR_LSI_Pos                           (0U)

+#define ETH_MACLMIR_LSI_Msk                           (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */

+#define ETH_MACLMIR_LSI                               ETH_MACLMIR_LSI_Msk  /* Log Sync Interval */

+

+/* Bit definition for Ethernet MTL Operation Mode Register */

+#define ETH_MTLOMR_CNTCLR_Pos                         (9U)

+#define ETH_MTLOMR_CNTCLR_Msk                         (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */

+#define ETH_MTLOMR_CNTCLR                             ETH_MTLOMR_CNTCLR_Msk    /* Counters Reset */

+#define ETH_MTLOMR_CNTPRST_Pos                        (8U)

+#define ETH_MTLOMR_CNTPRST_Msk                        (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */

+#define ETH_MTLOMR_CNTPRST                            ETH_MTLOMR_CNTPRST_Msk   /* Counters Preset */

+#define ETH_MTLOMR_DTXSTS_Pos                         (1U)

+#define ETH_MTLOMR_DTXSTS_Msk                         (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */

+#define ETH_MTLOMR_DTXSTS                             ETH_MTLOMR_DTXSTS_Msk  /* Drop Transmit Status */

+

+/* Bit definition for Ethernet MTL Interrupt Status Register */

+#define ETH_MTLISR_MACIS_Pos                          (16U)

+#define ETH_MTLISR_MACIS_Msk                          (0x1UL << ETH_MTLISR_MACIS_Pos) /*!< 0x00010000 */

+#define ETH_MTLISR_MACIS                              ETH_MTLISR_MACIS_Msk     /* MAC Interrupt Status */

+#define ETH_MTLISR_QIS_Pos                            (0U)

+#define ETH_MTLISR_QIS_Msk                            (0x1UL << ETH_MTLISR_QIS_Pos) /*!< 0x00000001 */

+#define ETH_MTLISR_QIS                                ETH_MTLISR_QIS_Msk       /* Queue Interrupt status */

+

+/* Bit definition for Ethernet MTL Tx Queue Operation Mode Register */

+#define ETH_MTLTQOMR_TTC_Pos                          (4U)

+#define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */

+#define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */

+#define ETH_MTLTQOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */

+#define ETH_MTLTQOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */

+#define ETH_MTLTQOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */

+#define ETH_MTLTQOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */

+#define ETH_MTLTQOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */

+#define ETH_MTLTQOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */

+#define ETH_MTLTQOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */

+#define ETH_MTLTQOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */

+#define ETH_MTLTQOMR_TSF_Pos                          (1U)

+#define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */

+#define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */

+#define ETH_MTLTQOMR_FTQ_Pos                          (0U)

+#define ETH_MTLTQOMR_FTQ_Msk                          (0x1UL << ETH_MTLTQOMR_FTQ_Pos) /*!< 0x00000001 */

+#define ETH_MTLTQOMR_FTQ                              ETH_MTLTQOMR_FTQ_Msk     /* Flush Transmit Queue */

+

+/* Bit definition for Ethernet MTL Tx Queue Underflow Register */

+#define ETH_MTLTQUR_UFCNTOVF_Pos                      (11U)

+#define ETH_MTLTQUR_UFCNTOVF_Msk                      (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos) /*!< 0x00000800 */

+#define ETH_MTLTQUR_UFCNTOVF                          ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */

+#define ETH_MTLTQUR_UFPKTCNT_Pos                      (0U)

+#define ETH_MTLTQUR_UFPKTCNT_Msk                      (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos) /*!< 0x000007FF */

+#define ETH_MTLTQUR_UFPKTCNT                          ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */

+

+/* Bit definition for Ethernet MTL Tx Queue Debug Register */

+#define ETH_MTLTQDR_STXSTSF_Pos                       (20U)

+#define ETH_MTLTQDR_STXSTSF_Msk                       (0x7UL << ETH_MTLTQDR_STXSTSF_Pos) /*!< 0x00700000 */

+#define ETH_MTLTQDR_STXSTSF                           ETH_MTLTQDR_STXSTSF_Msk  /* Number of Status Words in the Tx Status FIFO of Queue */

+#define ETH_MTLTQDR_PTXQ_Pos                          (16U)

+#define ETH_MTLTQDR_PTXQ_Msk                          (0x7UL << ETH_MTLTQDR_PTXQ_Pos) /*!< 0x00070000 */

+#define ETH_MTLTQDR_PTXQ                              ETH_MTLTQDR_PTXQ_Msk     /* Number of Packets in the Transmit Queue */

+#define ETH_MTLTQDR_TXSTSFSTS_Pos                     (5U)

+#define ETH_MTLTQDR_TXSTSFSTS_Msk                     (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos) /*!< 0x00000020 */

+#define ETH_MTLTQDR_TXSTSFSTS                         ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */

+#define ETH_MTLTQDR_TXQSTS_Pos                        (4U)

+#define ETH_MTLTQDR_TXQSTS_Msk                        (0x1UL << ETH_MTLTQDR_TXQSTS_Pos) /*!< 0x00000010 */

+#define ETH_MTLTQDR_TXQSTS                            ETH_MTLTQDR_TXQSTS_Msk   /* MTL Tx Queue Not Empty Status */

+#define ETH_MTLTQDR_TWCSTS_Pos                        (3U)

+#define ETH_MTLTQDR_TWCSTS_Msk                        (0x1UL << ETH_MTLTQDR_TWCSTS_Pos) /*!< 0x00000008 */

+#define ETH_MTLTQDR_TWCSTS                            ETH_MTLTQDR_TWCSTS_Msk   /* MTL Tx Queue Write Controller Status */

+#define ETH_MTLTQDR_TRCSTS_Pos                        (1U)

+#define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */

+#define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */

+#define ETH_MTLTQDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */

+#define ETH_MTLTQDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */

+#define ETH_MTLTQDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */

+#define ETH_MTLTQDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */

+#define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)

+#define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */

+#define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */

+

+/* Bit definition for Ethernet MTL Queue Interrupt Control Status Register */

+#define ETH_MTLQICSR_RXOIE_Pos                        (24U)

+#define ETH_MTLQICSR_RXOIE_Msk                        (0x1UL << ETH_MTLQICSR_RXOIE_Pos) /*!< 0x01000000 */

+#define ETH_MTLQICSR_RXOIE                            ETH_MTLQICSR_RXOIE_Msk   /* Receive Queue Overflow Interrupt Enable */

+#define ETH_MTLQICSR_RXOVFIS_Pos                      (16U)

+#define ETH_MTLQICSR_RXOVFIS_Msk                      (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos) /*!< 0x00010000 */

+#define ETH_MTLQICSR_RXOVFIS                          ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */

+#define ETH_MTLQICSR_TXUIE_Pos                        (8U)

+#define ETH_MTLQICSR_TXUIE_Msk                        (0x1UL << ETH_MTLQICSR_TXUIE_Pos) /*!< 0x00000100 */

+#define ETH_MTLQICSR_TXUIE                            ETH_MTLQICSR_TXUIE_Msk   /* Transmit Queue Underflow Interrupt Enable */

+#define ETH_MTLQICSR_TXUNFIS_Pos                      (0U)

+#define ETH_MTLQICSR_TXUNFIS_Msk                      (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos) /*!< 0x00000001 */

+#define ETH_MTLQICSR_TXUNFIS                          ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */

+

+/* Bit definition for Ethernet MTL Rx Queue Operation Mode Register */

+#define ETH_MTLRQOMR_RQS_Pos                          (20U)

+#define ETH_MTLRQOMR_RQS_Msk                          (0x7UL << ETH_MTLRQOMR_RQS_Pos) /*!< 0x00700000 */

+#define ETH_MTLRQOMR_RQS                              ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */

+#define ETH_MTLRQOMR_RFD_Pos                          (14U)

+#define ETH_MTLRQOMR_RFD_Msk                          (0x7UL << ETH_MTLRQOMR_RFD_Pos) /*!< 0x0001C000 */

+#define ETH_MTLRQOMR_RFD                              ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */

+#define ETH_MTLRQOMR_RFA_Pos                          (8U)

+#define ETH_MTLRQOMR_RFA_Msk                          (0x7UL << ETH_MTLRQOMR_RFA_Pos) /*!< 0x00000700 */

+#define ETH_MTLRQOMR_RFA                              ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */

+#define ETH_MTLRQOMR_EHFC_Pos                         (7U)

+#define ETH_MTLRQOMR_EHFC_Msk                         (0x1UL << ETH_MTLRQOMR_EHFC_Pos) /*!< 0x00000080 */

+#define ETH_MTLRQOMR_EHFC                             ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */

+#define ETH_MTLRQOMR_DISTCPEF_Pos                     (6U)

+#define ETH_MTLRQOMR_DISTCPEF_Msk                     (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos) /*!< 0x00000040 */

+#define ETH_MTLRQOMR_DISTCPEF                         ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */

+#define ETH_MTLRQOMR_RSF_Pos                          (5U)

+#define ETH_MTLRQOMR_RSF_Msk                          (0x1UL << ETH_MTLRQOMR_RSF_Pos) /*!< 0x00000020 */

+#define ETH_MTLRQOMR_RSF                              ETH_MTLRQOMR_RSF_Msk     /* Receive Queue Store and Forward */

+#define ETH_MTLRQOMR_FEP_Pos                          (4U)

+#define ETH_MTLRQOMR_FEP_Msk                          (0x1UL << ETH_MTLRQOMR_FEP_Pos) /*!< 0x00000010 */

+#define ETH_MTLRQOMR_FEP                              ETH_MTLRQOMR_FEP_Msk     /* Forward Error Packets */

+#define ETH_MTLRQOMR_FUP_Pos                          (3U)

+#define ETH_MTLRQOMR_FUP_Msk                          (0x1UL << ETH_MTLRQOMR_FUP_Pos) /*!< 0x00000008 */

+#define ETH_MTLRQOMR_FUP                              ETH_MTLRQOMR_FUP_Msk     /* Forward Undersized Good Packets */

+#define ETH_MTLRQOMR_RTC_Pos                          (0U)

+#define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */

+#define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */

+#define ETH_MTLRQOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */

+#define ETH_MTLRQOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */

+#define ETH_MTLRQOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */

+#define ETH_MTLRQOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */

+

+/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */

+#define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)

+#define ETH_MTLRQMPOCR_MISCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */

+#define ETH_MTLRQMPOCR_MISCNTOVF                      ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */

+#define ETH_MTLRQMPOCR_MISPKTCNT_Pos                  (16U)

+#define ETH_MTLRQMPOCR_MISPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */

+#define ETH_MTLRQMPOCR_MISPKTCNT                      ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */

+#define ETH_MTLRQMPOCR_OVFCNTOVF_Pos                  (11U)

+#define ETH_MTLRQMPOCR_OVFCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */

+#define ETH_MTLRQMPOCR_OVFCNTOVF                      ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */

+#define ETH_MTLRQMPOCR_OVFPKTCNT_Pos                  (0U)

+#define ETH_MTLRQMPOCR_OVFPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */

+#define ETH_MTLRQMPOCR_OVFPKTCNT                      ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */

+

+/* Bit definition for Ethernet MTL Rx Queue Debug Register */

+#define ETH_MTLRQDR_PRXQ_Pos                          (16U)

+#define ETH_MTLRQDR_PRXQ_Msk                          (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos) /*!< 0x3FFF0000 */

+#define ETH_MTLRQDR_PRXQ                              ETH_MTLRQDR_PRXQ_Msk     /* Number of Packets in Receive Queue */

+#define ETH_MTLRQDR_RXQSTS_Pos                        (4U)

+#define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */

+#define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */

+#define ETH_MTLRQDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */

+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)

+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */

+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */

+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos         (5U)

+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */

+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD             ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */

+#define ETH_MTLRQDR_RXQSTS_FULL_Pos                   (4U)

+#define ETH_MTLRQDR_RXQSTS_FULL_Msk                   (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */

+#define ETH_MTLRQDR_RXQSTS_FULL                       ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */

+#define ETH_MTLRQDR_RRCSTS_Pos                        (1U)

+#define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */

+#define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */

+#define ETH_MTLRQDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */

+#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)

+#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */

+#define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */

+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos          (2U)

+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk          (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */

+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS              ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */

+#define ETH_MTLRQDR_RRCSTS_FLUSHING_Pos               (1U)

+#define ETH_MTLRQDR_RRCSTS_FLUSHING_Msk               (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */

+#define ETH_MTLRQDR_RRCSTS_FLUSHING                   ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */

+#define ETH_MTLRQDR_RWCSTS_Pos                        (0U)

+#define ETH_MTLRQDR_RWCSTS_Msk                        (0x1UL << ETH_MTLRQDR_RWCSTS_Pos) /*!< 0x00000001 */

+#define ETH_MTLRQDR_RWCSTS                            ETH_MTLRQDR_RWCSTS_Msk   /* MTL Rx Queue Write Controller Active Status */

+

+/* Bit definition for Ethernet MTL Rx Queue Control Register */

+#define ETH_MTLRQCR_RQPA_Pos                          (3U)

+#define ETH_MTLRQCR_RQPA_Msk                          (0x1UL << ETH_MTLRQCR_RQPA_Pos) /*!< 0x00000008 */

+#define ETH_MTLRQCR_RQPA                              ETH_MTLRQCR_RQPA_Msk     /* Receive Queue Packet Arbitration */

+#define ETH_MTLRQCR_RQW_Pos                           (0U)

+#define ETH_MTLRQCR_RQW_Msk                           (0x7UL << ETH_MTLRQCR_RQW_Pos) /*!< 0x00000007 */

+#define ETH_MTLRQCR_RQW                               ETH_MTLRQCR_RQW_Msk      /* Receive Queue Weight */

+

+/* Bit definition for Ethernet DMA Mode Register */

+#define ETH_DMAMR_INTM_Pos                            (16U)

+#define ETH_DMAMR_INTM_Msk                            (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */

+#define ETH_DMAMR_INTM                                ETH_DMAMR_INTM_Msk       /* This field defines the interrupt mode */

+#define ETH_DMAMR_INTM_0                              (0x0UL << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */

+#define ETH_DMAMR_INTM_1                              (0x1UL << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */

+#define ETH_DMAMR_INTM_2                              (0x2UL << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */

+#define ETH_DMAMR_PR_Pos                              (12U)

+#define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */

+#define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */

+#define ETH_DMAMR_PR_1_1                              ((uint32_t)0x00000000)   /* The priority ratio is 1:1 */

+#define ETH_DMAMR_PR_2_1                              ((uint32_t)0x00001000)   /* The priority ratio is 2:1 */

+#define ETH_DMAMR_PR_3_1                              ((uint32_t)0x00002000)   /* The priority ratio is 3:1 */

+#define ETH_DMAMR_PR_4_1                              ((uint32_t)0x00003000)   /* The priority ratio is 4:1 */

+#define ETH_DMAMR_PR_5_1                              ((uint32_t)0x00004000)   /* The priority ratio is 5:1 */

+#define ETH_DMAMR_PR_6_1                              ((uint32_t)0x00005000)   /* The priority ratio is 6:1 */

+#define ETH_DMAMR_PR_7_1                              ((uint32_t)0x00006000)   /* The priority ratio is 7:1 */

+#define ETH_DMAMR_PR_8_1                              ((uint32_t)0x00007000)   /* The priority ratio is 8:1 */

+#define ETH_DMAMR_TXPR_Pos                            (11U)

+#define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */

+#define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */

+#define ETH_DMAMR_DA_Pos                              (1U)

+#define ETH_DMAMR_DA_Msk                              (0x1UL << ETH_DMAMR_DA_Pos) /*!< 0x00000002 */

+#define ETH_DMAMR_DA                                  ETH_DMAMR_DA_Msk         /* DMA Tx or Rx Arbitration Scheme */

+#define ETH_DMAMR_SWR_Pos                             (0U)

+#define ETH_DMAMR_SWR_Msk                             (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */

+#define ETH_DMAMR_SWR                                 ETH_DMAMR_SWR_Msk        /* Software Reset */

+

+/* Bit definition for Ethernet DMA SysBus Mode Register */

+#define ETH_DMASBMR_RB_Pos                            (15U)

+#define ETH_DMASBMR_RB_Msk                            (0x1UL << ETH_DMASBMR_RB_Pos) /*!< 0x00008000 */

+#define ETH_DMASBMR_RB                                ETH_DMASBMR_RB_Msk       /* Rebuild INCRx Burst */

+#define ETH_DMASBMR_MB_Pos                            (14U)

+#define ETH_DMASBMR_MB_Msk                            (0x1UL << ETH_DMASBMR_MB_Pos) /*!< 0x00004000 */

+#define ETH_DMASBMR_MB                                ETH_DMASBMR_MB_Msk       /* Mixed Burst */

+#define ETH_DMASBMR_AAL_Pos                           (12U)

+#define ETH_DMASBMR_AAL_Msk                           (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */

+#define ETH_DMASBMR_AAL                               ETH_DMASBMR_AAL_Msk      /* Address-Aligned Beats */

+#define ETH_DMASBMR_FB_Pos                            (0U)

+#define ETH_DMASBMR_FB_Msk                            (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */

+#define ETH_DMASBMR_FB                                ETH_DMASBMR_FB_Msk       /* Fixed Burst Length */

+

+/* Bit definition for Ethernet DMA Interrupt Status Register */

+#define ETH_DMAISR_MACIS_Pos                          (17U)

+#define ETH_DMAISR_MACIS_Msk                          (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */

+#define ETH_DMAISR_MACIS                              ETH_DMAISR_MACIS_Msk     /* MAC Interrupt Status */

+#define ETH_DMAISR_MTLIS_Pos                          (16U)

+#define ETH_DMAISR_MTLIS_Msk                          (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */

+#define ETH_DMAISR_MTLIS                              ETH_DMAISR_MTLIS_Msk     /* MAC Interrupt Status */

+#define ETH_DMAISR_DMACIS_Pos                         (0U)

+#define ETH_DMAISR_DMACIS_Msk                         (0x1UL << ETH_DMAISR_DMACIS_Pos) /*!< 0x00000001 */

+#define ETH_DMAISR_DMACIS                             ETH_DMAISR_DMACIS_Msk    /* DMA Channel Interrupt Status */

+

+/* Bit definition for Ethernet DMA Debug Status Register */

+#define ETH_DMADSR_TPS_Pos                            (12U)

+#define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */

+#define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */

+#define ETH_DMADSR_TPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */

+#define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)

+#define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */

+#define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */

+#define ETH_DMADSR_TPS_WAITING_Pos                    (13U)

+#define ETH_DMADSR_TPS_WAITING_Msk                    (0x1UL << ETH_DMADSR_TPS_WAITING_Pos) /*!< 0x00002000 */

+#define ETH_DMADSR_TPS_WAITING                        ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */

+#define ETH_DMADSR_TPS_READING_Pos                    (12U)

+#define ETH_DMADSR_TPS_READING_Msk                    (0x3UL << ETH_DMADSR_TPS_READING_Pos) /*!< 0x00003000 */

+#define ETH_DMADSR_TPS_READING                        ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */

+#define ETH_DMADSR_TPS_TIMESTAMP_WR_Pos               (14U)

+#define ETH_DMADSR_TPS_TIMESTAMP_WR_Msk               (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos) /*!< 0x00004000 */

+#define ETH_DMADSR_TPS_TIMESTAMP_WR                   ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */

+#define ETH_DMADSR_TPS_SUSPENDED_Pos                  (13U)

+#define ETH_DMADSR_TPS_SUSPENDED_Msk                  (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos) /*!< 0x00006000 */

+#define ETH_DMADSR_TPS_SUSPENDED                      ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */

+#define ETH_DMADSR_TPS_CLOSING_Pos                    (12U)

+#define ETH_DMADSR_TPS_CLOSING_Msk                    (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos) /*!< 0x00007000 */

+#define ETH_DMADSR_TPS_CLOSING                        ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */

+#define ETH_DMADSR_RPS_Pos                            (8U)

+#define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */

+#define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */

+#define ETH_DMADSR_RPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */

+#define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)

+#define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */

+#define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */

+#define ETH_DMADSR_RPS_WAITING_Pos                    (12U)

+#define ETH_DMADSR_RPS_WAITING_Msk                    (0x3UL << ETH_DMADSR_RPS_WAITING_Pos) /*!< 0x00003000 */

+#define ETH_DMADSR_RPS_WAITING                        ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */

+#define ETH_DMADSR_RPS_SUSPENDED_Pos                  (14U)

+#define ETH_DMADSR_RPS_SUSPENDED_Msk                  (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos) /*!< 0x00004000 */

+#define ETH_DMADSR_RPS_SUSPENDED                      ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */

+#define ETH_DMADSR_RPS_CLOSING_Pos                    (12U)

+#define ETH_DMADSR_RPS_CLOSING_Msk                    (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos) /*!< 0x00005000 */

+#define ETH_DMADSR_RPS_CLOSING                        ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */

+#define ETH_DMADSR_RPS_TIMESTAMP_WR_Pos               (13U)

+#define ETH_DMADSR_RPS_TIMESTAMP_WR_Msk               (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos) /*!< 0x00006000 */

+#define ETH_DMADSR_RPS_TIMESTAMP_WR                   ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */

+#define ETH_DMADSR_RPS_TRANSFERRING_Pos               (12U)

+#define ETH_DMADSR_RPS_TRANSFERRING_Msk               (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos) /*!< 0x00007000 */

+#define ETH_DMADSR_RPS_TRANSFERRING                   ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */

+

+/* Bit definition for Ethernet DMA Channel Control Register */

+#define ETH_DMACCR_DSL_Pos                            (18U)

+#define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */

+#define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */

+#define ETH_DMACCR_DSL_0BIT                           ((uint32_t)0x00000000)

+#define ETH_DMACCR_DSL_32BIT                          ((uint32_t)0x00040000)

+#define ETH_DMACCR_DSL_64BIT                          ((uint32_t)0x00080000)

+#define ETH_DMACCR_DSL_128BIT                         ((uint32_t)0x00100000)

+#define ETH_DMACCR_8PBL                               ((uint32_t)0x00010000)   /* 8xPBL mode */

+#define ETH_DMACCR_MSS_Pos                            (0U)

+#define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */

+#define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */

+

+/* Bit definition for Ethernet DMA Channel Tx Control Register */

+#define ETH_DMACTCR_TPBL_Pos                          (16U)

+#define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */

+#define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */

+#define ETH_DMACTCR_TPBL_1PBL                         ((uint32_t)0x00010000)   /* Transmit Programmable Burst Length 1 */

+#define ETH_DMACTCR_TPBL_2PBL                         ((uint32_t)0x00020000)   /* Transmit Programmable Burst Length 2 */

+#define ETH_DMACTCR_TPBL_4PBL                         ((uint32_t)0x00040000)   /* Transmit Programmable Burst Length 4 */

+#define ETH_DMACTCR_TPBL_8PBL                         ((uint32_t)0x00080000)   /* Transmit Programmable Burst Length 8 */

+#define ETH_DMACTCR_TPBL_16PBL                        ((uint32_t)0x00100000)   /* Transmit Programmable Burst Length 16 */

+#define ETH_DMACTCR_TPBL_32PBL                        ((uint32_t)0x00200000)   /* Transmit Programmable Burst Length 32 */

+#define ETH_DMACTCR_TSE_Pos                           (12U)

+#define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */

+#define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */

+#define ETH_DMACTCR_OSP_Pos                           (4U)

+#define ETH_DMACTCR_OSP_Msk                           (0x1UL << ETH_DMACTCR_OSP_Pos) /*!< 0x00000010 */

+#define ETH_DMACTCR_OSP                               ETH_DMACTCR_OSP_Msk      /* Operate on Second Packet */

+#define ETH_DMACTCR_ST_Pos                            (0U)

+#define ETH_DMACTCR_ST_Msk                            (0x1UL << ETH_DMACTCR_ST_Pos) /*!< 0x00000001 */

+#define ETH_DMACTCR_ST                                ETH_DMACTCR_ST_Msk       /* Start or Stop Transmission Command */

+

+/* Bit definition for Ethernet DMA Channel Rx Control Register */

+#define ETH_DMACRCR_RPF_Pos                           (31U)

+#define ETH_DMACRCR_RPF_Msk                           (0x1UL << ETH_DMACRCR_RPF_Pos) /*!< 0x80000000 */

+#define ETH_DMACRCR_RPF                               ETH_DMACRCR_RPF_Msk      /* Rx Packet Flush */

+#define ETH_DMACRCR_RPBL_Pos                          (16U)

+#define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */

+#define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */

+#define ETH_DMACRCR_RPBL_1PBL                         ((uint32_t)0x00010000)   /* Receive Programmable Burst Length 1 */

+#define ETH_DMACRCR_RPBL_2PBL                         ((uint32_t)0x00020000)   /* Receive Programmable Burst Length 2 */

+#define ETH_DMACRCR_RPBL_4PBL                         ((uint32_t)0x00040000)   /* Receive Programmable Burst Length 4 */

+#define ETH_DMACRCR_RPBL_8PBL                         ((uint32_t)0x00080000)   /* Receive Programmable Burst Length 8 */

+#define ETH_DMACRCR_RPBL_16PBL                        ((uint32_t)0x00100000)   /* Receive Programmable Burst Length 16 */

+#define ETH_DMACRCR_RPBL_32PBL                        ((uint32_t)0x00200000)   /* Receive Programmable Burst Length 32 */

+#define ETH_DMACRCR_RBSZ_Pos                          (1U)

+#define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */

+#define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */

+#define ETH_DMACRCR_SR_Pos                            (0U)

+#define ETH_DMACRCR_SR_Msk                            (0x1UL << ETH_DMACRCR_SR_Pos) /*!< 0x00000001 */

+#define ETH_DMACRCR_SR                                ETH_DMACRCR_SR_Msk       /* Start or Stop Receive */

+

+/* Bit definition for Ethernet DMA CH Tx Desc List Address Register */

+#define ETH_DMACTDLAR_TDESLA_Pos                      (2U)

+#define ETH_DMACTDLAR_TDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACTDLAR_TDESLA                          ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */

+

+/* Bit definition for Ethernet DMA CH Rx Desc List Address Register */

+#define ETH_DMACRDLAR_RDESLA_Pos                      (2U)

+#define ETH_DMACRDLAR_RDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACRDLAR_RDESLA                          ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */

+

+/* Bit definition for Ethernet DMA CH Tx Desc Tail Pointer Register */

+#define ETH_DMACTDTPR_TDT_Pos                         (2U)

+#define ETH_DMACTDTPR_TDT_Msk                         (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACTDTPR_TDT                             ETH_DMACTDTPR_TDT_Msk    /* Transmit Descriptor Tail Pointer */

+

+/* Bit definition for Ethernet DMA CH Rx Desc Tail Pointer Register */

+#define ETH_DMACRDTPR_RDT_Pos                         (2U)

+#define ETH_DMACRDTPR_RDT_Msk                         (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACRDTPR_RDT                             ETH_DMACRDTPR_RDT_Msk    /* Receive Descriptor Tail Pointer */

+

+/* Bit definition for Ethernet DMA CH Tx Desc Ring Length Register */

+#define ETH_DMACTDRLR_TDRL_Pos                        (0U)

+#define ETH_DMACTDRLR_TDRL_Msk                        (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos) /*!< 0x000003FF */

+#define ETH_DMACTDRLR_TDRL                            ETH_DMACTDRLR_TDRL_Msk   /* Transmit Descriptor Ring Length */

+

+/* Bit definition for Ethernet DMA CH Rx Desc Ring Length Register */

+#define ETH_DMACRDRLR_RDRL_Pos                        (0U)

+#define ETH_DMACRDRLR_RDRL_Msk                        (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos) /*!< 0x000003FF */

+#define ETH_DMACRDRLR_RDRL                            ETH_DMACRDRLR_RDRL_Msk   /* Receive Descriptor Ring Length */

+

+/* Bit definition for Ethernet DMA Channel Interrupt Enable Register */

+#define ETH_DMACIER_NIE_Pos                           (15U)

+#define ETH_DMACIER_NIE_Msk                           (0x1UL << ETH_DMACIER_NIE_Pos) /*!< 0x00008000 */

+#define ETH_DMACIER_NIE                               ETH_DMACIER_NIE_Msk      /* Normal Interrupt Summary Enable */

+#define ETH_DMACIER_AIE_Pos                           (14U)

+#define ETH_DMACIER_AIE_Msk                           (0x1UL << ETH_DMACIER_AIE_Pos) /*!< 0x00004000 */

+#define ETH_DMACIER_AIE                               ETH_DMACIER_AIE_Msk      /* Abnormal Interrupt Summary Enable */

+#define ETH_DMACIER_CDEE_Pos                          (13U)

+#define ETH_DMACIER_CDEE_Msk                          (0x1UL << ETH_DMACIER_CDEE_Pos) /*!< 0x00002000 */

+#define ETH_DMACIER_CDEE                              ETH_DMACIER_CDEE_Msk     /* Context Descriptor Error Enable */

+#define ETH_DMACIER_FBEE_Pos                          (12U)

+#define ETH_DMACIER_FBEE_Msk                          (0x1UL << ETH_DMACIER_FBEE_Pos) /*!< 0x00001000 */

+#define ETH_DMACIER_FBEE                              ETH_DMACIER_FBEE_Msk     /* Fatal Bus Error Enable */

+#define ETH_DMACIER_ERIE_Pos                          (11U)

+#define ETH_DMACIER_ERIE_Msk                          (0x1UL << ETH_DMACIER_ERIE_Pos) /*!< 0x00000800 */

+#define ETH_DMACIER_ERIE                              ETH_DMACIER_ERIE_Msk     /* Early Receive Interrupt Enable */

+#define ETH_DMACIER_ETIE_Pos                          (10U)

+#define ETH_DMACIER_ETIE_Msk                          (0x1UL << ETH_DMACIER_ETIE_Pos) /*!< 0x00000400 */

+#define ETH_DMACIER_ETIE                              ETH_DMACIER_ETIE_Msk     /* Early Transmit Interrupt Enable */

+#define ETH_DMACIER_RWTE_Pos                          (9U)

+#define ETH_DMACIER_RWTE_Msk                          (0x1UL << ETH_DMACIER_RWTE_Pos) /*!< 0x00000200 */

+#define ETH_DMACIER_RWTE                              ETH_DMACIER_RWTE_Msk     /* Receive Watchdog Timeout Enable */

+#define ETH_DMACIER_RSE_Pos                           (8U)

+#define ETH_DMACIER_RSE_Msk                           (0x1UL << ETH_DMACIER_RSE_Pos) /*!< 0x00000100 */

+#define ETH_DMACIER_RSE                               ETH_DMACIER_RSE_Msk      /* Receive Stopped Enable */

+#define ETH_DMACIER_RBUE_Pos                          (7U)

+#define ETH_DMACIER_RBUE_Msk                          (0x1UL << ETH_DMACIER_RBUE_Pos) /*!< 0x00000080 */

+#define ETH_DMACIER_RBUE                              ETH_DMACIER_RBUE_Msk     /* Receive Buffer Unavailable Enable */

+#define ETH_DMACIER_RIE_Pos                           (6U)

+#define ETH_DMACIER_RIE_Msk                           (0x1UL << ETH_DMACIER_RIE_Pos) /*!< 0x00000040 */

+#define ETH_DMACIER_RIE                               ETH_DMACIER_RIE_Msk      /* Receive Interrupt Enable */

+#define ETH_DMACIER_TBUE_Pos                          (2U)

+#define ETH_DMACIER_TBUE_Msk                          (0x1UL << ETH_DMACIER_TBUE_Pos) /*!< 0x00000004 */

+#define ETH_DMACIER_TBUE                              ETH_DMACIER_TBUE_Msk     /* Transmit Buffer Unavailable Enable */

+#define ETH_DMACIER_TXSE_Pos                          (1U)

+#define ETH_DMACIER_TXSE_Msk                          (0x1UL << ETH_DMACIER_TXSE_Pos) /*!< 0x00000002 */

+#define ETH_DMACIER_TXSE                              ETH_DMACIER_TXSE_Msk     /* Transmit Stopped Enable */

+#define ETH_DMACIER_TIE_Pos                           (0U)

+#define ETH_DMACIER_TIE_Msk                           (0x1UL << ETH_DMACIER_TIE_Pos) /*!< 0x00000001 */

+#define ETH_DMACIER_TIE                               ETH_DMACIER_TIE_Msk      /* Transmit Interrupt Enable */

+

+/* Bit definition for Ethernet DMA Channel Rx Interrupt Watchdog Timer Register */

+#define ETH_DMACRIWTR_RWT_Pos                         (0U)

+#define ETH_DMACRIWTR_RWT_Msk                         (0xFFUL << ETH_DMACRIWTR_RWT_Pos) /*!< 0x000000FF */

+#define ETH_DMACRIWTR_RWT                             ETH_DMACRIWTR_RWT_Msk    /* Receive Interrupt Watchdog Timer Count */

+

+/* Bit definition for Ethernet DMA Channel Current App Tx Desc Register */

+#define ETH_DMACCATDR_CURTDESAPTR_Pos                 (0U)

+#define ETH_DMACCATDR_CURTDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCATDR_CURTDESAPTR                     ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Current App Rx Desc Register */

+#define ETH_DMACCARDR_CURRDESAPTR_Pos                 (0U)

+#define ETH_DMACCARDR_CURRDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCARDR_CURRDESAPTR                     ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Current App Tx Buffer Register */

+#define ETH_DMACCATBR_CURTBUFAPTR_Pos                 (0U)

+#define ETH_DMACCATBR_CURTBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCATBR_CURTBUFAPTR                     ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Current App Rx Buffer Register */

+#define ETH_DMACCARBR_CURRBUFAPTR_Pos                 (0U)

+#define ETH_DMACCARBR_CURRBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCARBR_CURRBUFAPTR                     ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Status Register */

+#define ETH_DMACSR_REB_Pos                            (19U)

+#define ETH_DMACSR_REB_Msk                            (0x7UL << ETH_DMACSR_REB_Pos) /*!< 0x00380000 */

+#define ETH_DMACSR_REB                                ETH_DMACSR_REB_Msk       /* Rx DMA Error Bits */

+#define ETH_DMACSR_TEB_Pos                            (16U)

+#define ETH_DMACSR_TEB_Msk                            (0x7UL << ETH_DMACSR_TEB_Pos) /*!< 0x00070000 */

+#define ETH_DMACSR_TEB                                ETH_DMACSR_TEB_Msk       /* Tx DMA Error Bits */

+#define ETH_DMACSR_NIS_Pos                            (15U)

+#define ETH_DMACSR_NIS_Msk                            (0x1UL << ETH_DMACSR_NIS_Pos) /*!< 0x00008000 */

+#define ETH_DMACSR_NIS                                ETH_DMACSR_NIS_Msk       /* Normal Interrupt Summary */

+#define ETH_DMACSR_AIS_Pos                            (14U)

+#define ETH_DMACSR_AIS_Msk                            (0x1UL << ETH_DMACSR_AIS_Pos) /*!< 0x00004000 */

+#define ETH_DMACSR_AIS                                ETH_DMACSR_AIS_Msk       /* Abnormal Interrupt Summary */

+#define ETH_DMACSR_CDE_Pos                            (13U)

+#define ETH_DMACSR_CDE_Msk                            (0x1UL << ETH_DMACSR_CDE_Pos) /*!< 0x00002000 */

+#define ETH_DMACSR_CDE                                ETH_DMACSR_CDE_Msk       /* Context Descriptor Error */

+#define ETH_DMACSR_FBE_Pos                            (12U)

+#define ETH_DMACSR_FBE_Msk                            (0x1UL << ETH_DMACSR_FBE_Pos) /*!< 0x00001000 */

+#define ETH_DMACSR_FBE                                ETH_DMACSR_FBE_Msk       /* Fatal Bus Error */

+#define ETH_DMACSR_ERI_Pos                            (11U)

+#define ETH_DMACSR_ERI_Msk                            (0x1UL << ETH_DMACSR_ERI_Pos) /*!< 0x00000800 */

+#define ETH_DMACSR_ERI                                ETH_DMACSR_ERI_Msk       /* Early Receive Interrupt */

+#define ETH_DMACSR_ETI_Pos                            (10U)

+#define ETH_DMACSR_ETI_Msk                            (0x1UL << ETH_DMACSR_ETI_Pos) /*!< 0x00000400 */

+#define ETH_DMACSR_ETI                                ETH_DMACSR_ETI_Msk       /* Early Transmit Interrupt */

+#define ETH_DMACSR_RWT_Pos                            (9U)

+#define ETH_DMACSR_RWT_Msk                            (0x1UL << ETH_DMACSR_RWT_Pos) /*!< 0x00000200 */

+#define ETH_DMACSR_RWT                                ETH_DMACSR_RWT_Msk       /* Receive Watchdog Timeout */

+#define ETH_DMACSR_RPS_Pos                            (8U)

+#define ETH_DMACSR_RPS_Msk                            (0x1UL << ETH_DMACSR_RPS_Pos) /*!< 0x00000100 */

+#define ETH_DMACSR_RPS                                ETH_DMACSR_RPS_Msk       /* Receive Process Stopped */

+#define ETH_DMACSR_RBU_Pos                            (7U)

+#define ETH_DMACSR_RBU_Msk                            (0x1UL << ETH_DMACSR_RBU_Pos) /*!< 0x00000080 */

+#define ETH_DMACSR_RBU                                ETH_DMACSR_RBU_Msk       /* Receive Buffer Unavailable */

+#define ETH_DMACSR_RI_Pos                             (6U)

+#define ETH_DMACSR_RI_Msk                             (0x1UL << ETH_DMACSR_RI_Pos) /*!< 0x00000040 */

+#define ETH_DMACSR_RI                                 ETH_DMACSR_RI_Msk        /* Receive Interrupt */

+#define ETH_DMACSR_TBU_Pos                            (2U)

+#define ETH_DMACSR_TBU_Msk                            (0x1UL << ETH_DMACSR_TBU_Pos) /*!< 0x00000004 */

+#define ETH_DMACSR_TBU                                ETH_DMACSR_TBU_Msk       /* Transmit Buffer Unavailable */

+#define ETH_DMACSR_TPS_Pos                            (1U)

+#define ETH_DMACSR_TPS_Msk                            (0x1UL << ETH_DMACSR_TPS_Pos) /*!< 0x00000002 */

+#define ETH_DMACSR_TPS                                ETH_DMACSR_TPS_Msk       /* Transmit Process Stopped */

+#define ETH_DMACSR_TI_Pos                             (0U)

+#define ETH_DMACSR_TI_Msk                             (0x1UL << ETH_DMACSR_TI_Pos) /*!< 0x00000001 */

+#define ETH_DMACSR_TI                                 ETH_DMACSR_TI_Msk        /* Transmit Interrupt */

+

+/* Bit definition for Ethernet DMA Channel missed frame count register */

+#define ETH_DMACMFCR_MFCO_Pos                         (15U)

+#define ETH_DMACMFCR_MFCO_Msk                         (0x1UL << ETH_DMACMFCR_MFCO_Pos) /*!< 0x00008000 */

+#define ETH_DMACMFCR_MFCO                             ETH_DMACMFCR_MFCO_Msk    /* Overflow status of the MFC Counter */

+#define ETH_DMACMFCR_MFC_Pos                          (0U)

+#define ETH_DMACMFCR_MFC_Msk                          (0x7FFUL << ETH_DMACMFCR_MFC_Pos) /*!< 0x000007FF */

+#define ETH_DMACMFCR_MFC                              ETH_DMACMFCR_MFC_Msk     /* The number of packet counters dropped by the DMA */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             DMA Controller                                 */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DMA_SxCR register  *****************/

+#define DMA_SxCR_MBURST_Pos      (23U)

+#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                /*!< 0x01800000 */

+#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk                           /*!< Memory burst transfer configuration */

+#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */

+#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */

+#define DMA_SxCR_PBURST_Pos      (21U)

+#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                /*!< 0x00600000 */

+#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk                           /*!< Peripheral burst transfer configuration */

+#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */

+#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */

+#define DMA_SxCR_TRBUFF_Pos      (20U)

+#define DMA_SxCR_TRBUFF_Msk      (0x1UL << DMA_SxCR_TRBUFF_Pos)                 /*!< 0x00100000 */

+#define DMA_SxCR_TRBUFF          DMA_SxCR_TRBUFF_Msk                            /*!< bufferable transfers enabled/disable */

+#define DMA_SxCR_CT_Pos          (19U)

+#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                    /*!< 0x00080000 */

+#define DMA_SxCR_CT              DMA_SxCR_CT_Msk                               /*!< Current target (only in double buffer mode) */

+#define DMA_SxCR_DBM_Pos         (18U)

+#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                   /*!< 0x00040000 */

+#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk                              /*!< Double buffer mode */

+#define DMA_SxCR_PL_Pos          (16U)

+#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                    /*!< 0x00030000 */

+#define DMA_SxCR_PL              DMA_SxCR_PL_Msk                               /*!< Priority level */

+#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */

+#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */

+#define DMA_SxCR_PINCOS_Pos      (15U)

+#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                /*!< 0x00008000 */

+#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk                           /*!< Peripheral increment offset size */

+#define DMA_SxCR_MSIZE_Pos       (13U)

+#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                 /*!< 0x00006000 */

+#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk                            /*!< Memory data size */

+#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */

+#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */

+#define DMA_SxCR_PSIZE_Pos       (11U)

+#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                 /*!< 0x00001800 */

+#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk                            /*< Peripheral data size */

+#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */

+#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */

+#define DMA_SxCR_MINC_Pos        (10U)

+#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                  /*!< 0x00000400 */

+#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk                             /*!< Memory increment mode */

+#define DMA_SxCR_PINC_Pos        (9U)

+#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                  /*!< 0x00000200 */

+#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk                             /*!< Peripheral increment mode */

+#define DMA_SxCR_CIRC_Pos        (8U)

+#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                  /*!< 0x00000100 */

+#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk                             /*!< Circular mode */

+#define DMA_SxCR_DIR_Pos         (6U)

+#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                   /*!< 0x000000C0 */

+#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk                              /*!< Data transfer direction */

+#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */

+#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */

+#define DMA_SxCR_PFCTRL_Pos      (5U)

+#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                /*!< 0x00000020 */

+#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk                           /*!< Peripheral flow controller */

+#define DMA_SxCR_TCIE_Pos        (4U)

+#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                  /*!< 0x00000010 */

+#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk                             /*!< Transfer complete interrupt enable */

+#define DMA_SxCR_HTIE_Pos        (3U)

+#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                  /*!< 0x00000008 */

+#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk                             /*!< Half transfer interrupt enable */

+#define DMA_SxCR_TEIE_Pos        (2U)

+#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                  /*!< 0x00000004 */

+#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk                             /*!< Transfer error interrupt enable */

+#define DMA_SxCR_DMEIE_Pos       (1U)

+#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                 /*!< 0x00000002 */

+#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk                            /*!< Direct mode error interrupt enable */

+#define DMA_SxCR_EN_Pos          (0U)

+#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                    /*!< 0x00000001 */

+#define DMA_SxCR_EN              DMA_SxCR_EN_Msk                               /*!< Stream enable / flag stream ready when read low */

+

+/********************  Bits definition for DMA_SxCNDTR register  **************/

+#define DMA_SxNDT_Pos            (0U)

+#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                   /*!< 0x0000FFFF */

+#define DMA_SxNDT                DMA_SxNDT_Msk                                 /*!< Number of data items to transfer */

+#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */

+#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */

+#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */

+#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */

+#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */

+#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */

+#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */

+#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */

+#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */

+#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */

+#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */

+#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */

+#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */

+#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */

+#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */

+#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */

+

+/********************  Bits definition for DMA_SxFCR register  ****************/

+#define DMA_SxFCR_FEIE_Pos       (7U)

+#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                 /*!< 0x00000080 */

+#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk                            /*!< FIFO error interrupt enable */

+#define DMA_SxFCR_FS_Pos         (3U)

+#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                   /*!< 0x00000038 */

+#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk                              /*!< FIFO status */

+#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */

+#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */

+#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */

+#define DMA_SxFCR_DMDIS_Pos      (2U)

+#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                /*!< 0x00000004 */

+#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk                           /*!< Direct mode disable */

+#define DMA_SxFCR_FTH_Pos        (0U)

+#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                  /*!< 0x00000003 */

+#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk                             /*!< FIFO threshold selection */

+#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */

+#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */

+

+/********************  Bits definition for DMA_LISR register  *****************/

+#define DMA_LISR_TCIF3_Pos       (27U)

+#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                 /*!< 0x08000000 */

+#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk                            /*!<  Stream 3 transfer complete interrupt flag */

+#define DMA_LISR_HTIF3_Pos       (26U)

+#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                 /*!< 0x04000000 */

+#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk                            /*!<  Stream 3 half transfer interrupt flag */

+#define DMA_LISR_TEIF3_Pos       (25U)

+#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                 /*!< 0x02000000 */

+#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk                            /*!<  Stream 3 transfer error interrupt flag */

+#define DMA_LISR_DMEIF3_Pos      (24U)

+#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                /*!< 0x01000000 */

+#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk                           /*!<  Stream 3 direct mode error interrupt flag */

+#define DMA_LISR_FEIF3_Pos       (22U)

+#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                 /*!< 0x00400000 */

+#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk                            /*!<  Stream 3 FIFO error interrupt flag */

+#define DMA_LISR_TCIF2_Pos       (21U)

+#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                 /*!< 0x00200000 */

+#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk                            /*!<  Stream 2 transfer complete interrupt flag */

+#define DMA_LISR_HTIF2_Pos       (20U)

+#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                 /*!< 0x00100000 */

+#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk                            /*!<  Stream 2 half transfer interrupt flag */

+#define DMA_LISR_TEIF2_Pos       (19U)

+#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                 /*!< 0x00080000 */

+#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk                            /*!<  Stream 2 transfer error interrupt flag */

+#define DMA_LISR_DMEIF2_Pos      (18U)

+#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                /*!< 0x00040000 */

+#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk                           /*!<  Stream 2 direct mode error interrupt flag */

+#define DMA_LISR_FEIF2_Pos       (16U)

+#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                 /*!< 0x00010000 */

+#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk                            /*!<  Stream 2 FIFO error interrupt flag */

+#define DMA_LISR_TCIF1_Pos       (11U)

+#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                 /*!< 0x00000800 */

+#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk                            /*!<  Stream 1 transfer complete interrupt flag */

+#define DMA_LISR_HTIF1_Pos       (10U)

+#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                 /*!< 0x00000400 */

+#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk                            /*!<  Stream 1 half transfer interrupt flag */

+#define DMA_LISR_TEIF1_Pos       (9U)

+#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                 /*!< 0x00000200 */

+#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk                            /*!<  Stream 1 transfer error interrupt flag */

+#define DMA_LISR_DMEIF1_Pos      (8U)

+#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                /*!< 0x00000100 */

+#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk                           /*!<  Stream 1 direct mode error interrupt flag */

+#define DMA_LISR_FEIF1_Pos       (6U)

+#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                 /*!< 0x00000040 */

+#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk                            /*!<  Stream 1 FIFO error interrupt flag */

+#define DMA_LISR_TCIF0_Pos       (5U)

+#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                 /*!< 0x00000020 */

+#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk                            /*!<  Stream 0 transfer complete interrupt flag */

+#define DMA_LISR_HTIF0_Pos       (4U)

+#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                 /*!< 0x00000010 */

+#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk                            /*!<  Stream 0 half transfer interrupt flag */

+#define DMA_LISR_TEIF0_Pos       (3U)

+#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                 /*!< 0x00000008 */

+#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk                            /*!<  Stream 0 transfer error interrupt flag */

+#define DMA_LISR_DMEIF0_Pos      (2U)

+#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                /*!< 0x00000004 */

+#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk                           /*!<  Stream 0 direct mode error interrupt flag */

+#define DMA_LISR_FEIF0_Pos       (0U)

+#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                 /*!< 0x00000001 */

+#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk                            /*!<  Stream 0 FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_HISR register  *****************/

+#define DMA_HISR_TCIF7_Pos       (27U)

+#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                 /*!< 0x08000000 */

+#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk                            /*!<  Stream 7 transfer complete interrupt flag */

+#define DMA_HISR_HTIF7_Pos       (26U)

+#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                 /*!< 0x04000000 */

+#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk                            /*!<  Stream 7 half transfer interrupt flag */

+#define DMA_HISR_TEIF7_Pos       (25U)

+#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                 /*!< 0x02000000 */

+#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk                            /*!<  Stream 7 transfer error interrupt flag */

+#define DMA_HISR_DMEIF7_Pos      (24U)

+#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                /*!< 0x01000000 */

+#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk                           /*!<  Stream 7 direct mode error interrupt flag */

+#define DMA_HISR_FEIF7_Pos       (22U)

+#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                 /*!< 0x00400000 */

+#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk                            /*!<  Stream 7 FIFO error interrupt flag */

+#define DMA_HISR_TCIF6_Pos       (21U)

+#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                 /*!< 0x00200000 */

+#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk                            /*!<  Stream 6 transfer complete interrupt flag */

+#define DMA_HISR_HTIF6_Pos       (20U)

+#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                 /*!< 0x00100000 */

+#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk                            /*!<  Stream 6 half transfer interrupt flag */

+#define DMA_HISR_TEIF6_Pos       (19U)

+#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                 /*!< 0x00080000 */

+#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk                            /*!<  Stream 6 transfer error interrupt flag */

+#define DMA_HISR_DMEIF6_Pos      (18U)

+#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                /*!< 0x00040000 */

+#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk                           /*!<  Stream 6 direct mode error interrupt flag */

+#define DMA_HISR_FEIF6_Pos       (16U)

+#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                 /*!< 0x00010000 */

+#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk                            /*!<  Stream 6 FIFO error interrupt flag */

+#define DMA_HISR_TCIF5_Pos       (11U)

+#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                 /*!< 0x00000800 */

+#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk                            /*!<  Stream 5 transfer complete interrupt flag */

+#define DMA_HISR_HTIF5_Pos       (10U)

+#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                 /*!< 0x00000400 */

+#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk                            /*!<  Stream 5 half transfer interrupt flag */

+#define DMA_HISR_TEIF5_Pos       (9U)

+#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                 /*!< 0x00000200 */

+#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk                            /*!<  Stream 5 transfer error interrupt flag */

+#define DMA_HISR_DMEIF5_Pos      (8U)

+#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                /*!< 0x00000100 */

+#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk                           /*!<  Stream 5 direct mode error interrupt flag */

+#define DMA_HISR_FEIF5_Pos       (6U)

+#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                 /*!< 0x00000040 */

+#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk                            /*!<  Stream 5 FIFO error interrupt flag */

+#define DMA_HISR_TCIF4_Pos       (5U)

+#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                 /*!< 0x00000020 */

+#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk                            /*!<  Stream 4 transfer complete interrupt flag */

+#define DMA_HISR_HTIF4_Pos       (4U)

+#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                 /*!< 0x00000010 */

+#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk                            /*!<  Stream 4 half transfer interrupt flag */

+#define DMA_HISR_TEIF4_Pos       (3U)

+#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                 /*!< 0x00000008 */

+#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk                            /*!<  Stream 4 transfer error interrupt flag */

+#define DMA_HISR_DMEIF4_Pos      (2U)

+#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                /*!< 0x00000004 */

+#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk                           /*!<  Stream 4 direct mode error interrupt flag */

+#define DMA_HISR_FEIF4_Pos       (0U)

+#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                 /*!< 0x00000001 */

+#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk                            /*!<  Stream 4 FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_LIFCR register  ****************/

+#define DMA_LIFCR_CTCIF3_Pos     (27U)

+#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)               /*!< 0x08000000 */

+#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk                          /*!<  Stream 3 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF3_Pos     (26U)

+#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)               /*!< 0x04000000 */

+#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk                          /*!<  Stream 3 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF3_Pos     (25U)

+#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)               /*!< 0x02000000 */

+#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk                          /*!<  Stream 3 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF3_Pos    (24U)

+#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)              /*!< 0x01000000 */

+#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk                         /*!<  Stream 3 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF3_Pos     (22U)

+#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)               /*!< 0x00400000 */

+#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk                          /*!<  Stream 3 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF2_Pos     (21U)

+#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)               /*!< 0x00200000 */

+#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk                          /*!<  Stream 2 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF2_Pos     (20U)

+#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)               /*!< 0x00100000 */

+#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk                          /*!<  Stream 2 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF2_Pos     (19U)

+#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)               /*!< 0x00080000 */

+#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk                          /*!<  Stream 2 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF2_Pos    (18U)

+#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)              /*!< 0x00040000 */

+#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk                         /*!<  Stream 2 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF2_Pos     (16U)

+#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)               /*!< 0x00010000 */

+#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk                          /*!<  Stream 2 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF1_Pos     (11U)

+#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)               /*!< 0x00000800 */

+#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk                          /*!<  Stream 1 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF1_Pos     (10U)

+#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)               /*!< 0x00000400 */

+#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk                          /*!<  Stream 1 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF1_Pos     (9U)

+#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)               /*!< 0x00000200 */

+#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk                          /*!<  Stream 1 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF1_Pos    (8U)

+#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)              /*!< 0x00000100 */

+#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk                         /*!<  Stream 1 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF1_Pos     (6U)

+#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)               /*!< 0x00000040 */

+#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk                          /*!<  Stream 1 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF0_Pos     (5U)

+#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)               /*!< 0x00000020 */

+#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk                          /*!<  Stream 0 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF0_Pos     (4U)

+#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)               /*!< 0x00000010 */

+#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk                          /*!<  Stream 0 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF0_Pos     (3U)

+#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)               /*!< 0x00000008 */

+#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk                          /*!<  Stream 0 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF0_Pos    (2U)

+#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)              /*!< 0x00000004 */

+#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk                         /*!<  Stream 0 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF0_Pos     (0U)

+#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)               /*!< 0x00000001 */

+#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk                          /*!<  Stream 0 clear FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_HIFCR  register  ****************/

+#define DMA_HIFCR_CTCIF7_Pos     (27U)

+#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)               /*!< 0x08000000 */

+#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk                          /*!<  Stream 7 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF7_Pos     (26U)

+#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)               /*!< 0x04000000 */

+#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk                          /*!<  Stream 7 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF7_Pos     (25U)

+#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)               /*!< 0x02000000 */

+#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk                          /*!<  Stream 7 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF7_Pos    (24U)

+#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)              /*!< 0x01000000 */

+#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk                         /*!<  Stream 7 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF7_Pos     (22U)

+#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)               /*!< 0x00400000 */

+#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk                          /*!<  Stream 7 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF6_Pos     (21U)

+#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)               /*!< 0x00200000 */

+#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk                          /*!<  Stream 6 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF6_Pos     (20U)

+#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)               /*!< 0x00100000 */

+#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk                          /*!<  Stream 6 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF6_Pos     (19U)

+#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)               /*!< 0x00080000 */

+#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk                          /*!<  Stream 6 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF6_Pos    (18U)

+#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)              /*!< 0x00040000 */

+#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk                         /*!<  Stream 6 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF6_Pos     (16U)

+#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)               /*!< 0x00010000 */

+#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk                          /*!<  Stream 6 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF5_Pos     (11U)

+#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)               /*!< 0x00000800 */

+#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk                          /*!<  Stream 5 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF5_Pos     (10U)

+#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)               /*!< 0x00000400 */

+#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk                          /*!<  Stream 5 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF5_Pos     (9U)

+#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)               /*!< 0x00000200 */

+#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk                          /*!<  Stream 5 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF5_Pos    (8U)

+#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)              /*!< 0x00000100 */

+#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk                         /*!<  Stream 5 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF5_Pos     (6U)

+#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)               /*!< 0x00000040 */

+#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk                          /*!<  Stream 5 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF4_Pos     (5U)

+#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)               /*!< 0x00000020 */

+#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk                          /*!<  Stream 4 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF4_Pos     (4U)

+#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)               /*!< 0x00000010 */

+#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk                          /*!<  Stream 4 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF4_Pos     (3U)

+#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)               /*!< 0x00000008 */

+#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk                          /*!<  Stream 4 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF4_Pos    (2U)

+#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)              /*!< 0x00000004 */

+#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk                         /*!<  Stream 4 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF4_Pos     (0U)

+#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)               /*!< 0x00000001 */

+#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk                          /*!<  Stream 4 clear FIFO error interrupt flag */

+

+/******************  Bit definition for DMA_SxPAR register  ********************/

+#define DMA_SxPAR_PA_Pos         (0U)

+#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)            /*!< 0xFFFFFFFF */

+#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */

+

+/******************  Bit definition for DMA_SxM0AR register  ********************/

+#define DMA_SxM0AR_M0A_Pos       (0U)

+#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)          /*!< 0xFFFFFFFF */

+#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory 0 Address */

+

+/******************  Bit definition for DMA_SxM1AR register  ********************/

+#define DMA_SxM1AR_M1A_Pos       (0U)

+#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)          /*!< 0xFFFFFFFF */

+#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory 1 Address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             DMAMUX Controller                              */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DMAMUX_CxCR register  **************/

+#define DMAMUX_CxCR_DMAREQ_ID_Pos      (0U)

+#define DMAMUX_CxCR_DMAREQ_ID_Msk      (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)   /*!< 0x000000FF */

+#define DMAMUX_CxCR_DMAREQ_ID          DMAMUX_CxCR_DMAREQ_ID_Msk               /*!<  DMA request identification */

+#define DMAMUX_CxCR_DMAREQ_ID_0        (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000001 */

+#define DMAMUX_CxCR_DMAREQ_ID_1        (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000002 */

+#define DMAMUX_CxCR_DMAREQ_ID_2        (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000004 */

+#define DMAMUX_CxCR_DMAREQ_ID_3        (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000008 */

+#define DMAMUX_CxCR_DMAREQ_ID_4        (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000010 */

+#define DMAMUX_CxCR_DMAREQ_ID_5        (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000020 */

+#define DMAMUX_CxCR_DMAREQ_ID_6        (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000040 */

+#define DMAMUX_CxCR_DMAREQ_ID_7        (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000080 */

+#define DMAMUX_CxCR_SOIE_Pos           (8U)

+#define DMAMUX_CxCR_SOIE_Msk           (0x1UL << DMAMUX_CxCR_SOIE_Pos)         /*!< 0x00000100 */

+#define DMAMUX_CxCR_SOIE               DMAMUX_CxCR_SOIE_Msk                    /*!<  Synchronization overrun interrupt enable */

+#define DMAMUX_CxCR_EGE_Pos            (9U)

+#define DMAMUX_CxCR_EGE_Msk            (0x1UL << DMAMUX_CxCR_EGE_Pos)          /*!< 0x00000200 */

+#define DMAMUX_CxCR_EGE                DMAMUX_CxCR_EGE_Msk                     /*!<  Event generation enable */

+#define DMAMUX_CxCR_SE_Pos             (16U)

+#define DMAMUX_CxCR_SE_Msk             (0x1UL << DMAMUX_CxCR_SE_Pos)           /*!< 0x00010000 */

+#define DMAMUX_CxCR_SE                 DMAMUX_CxCR_SE_Msk                      /*!<  Synchronization enable */

+#define DMAMUX_CxCR_SPOL_Pos           (17U)

+#define DMAMUX_CxCR_SPOL_Msk           (0x3UL << DMAMUX_CxCR_SPOL_Pos)         /*!< 0x00060000 */

+#define DMAMUX_CxCR_SPOL               DMAMUX_CxCR_SPOL_Msk                    /*!<  Synchronization polarity */

+#define DMAMUX_CxCR_SPOL_0             (0x1UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00020000 */

+#define DMAMUX_CxCR_SPOL_1             (0x2UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00040000 */

+#define DMAMUX_CxCR_NBREQ_Pos          (19U)

+#define DMAMUX_CxCR_NBREQ_Msk          (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)       /*!< 0x00F80000 */

+#define DMAMUX_CxCR_NBREQ              DMAMUX_CxCR_NBREQ_Msk                   /*!<  Number of DMA requests minus 1 to forward */

+#define DMAMUX_CxCR_NBREQ_0            (0x01UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00080000 */

+#define DMAMUX_CxCR_NBREQ_1            (0x02UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00100000 */

+#define DMAMUX_CxCR_NBREQ_2            (0x04UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00200000 */

+#define DMAMUX_CxCR_NBREQ_3            (0x08UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00400000 */

+#define DMAMUX_CxCR_NBREQ_4            (0x10UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00800000 */

+#define DMAMUX_CxCR_SYNC_ID_Pos        (24U)

+#define DMAMUX_CxCR_SYNC_ID_Msk        (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)     /*!< 0x1F000000 */

+#define DMAMUX_CxCR_SYNC_ID            DMAMUX_CxCR_SYNC_ID_Msk                 /*!<  Synchronization identification */

+#define DMAMUX_CxCR_SYNC_ID_0          (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x01000000 */

+#define DMAMUX_CxCR_SYNC_ID_1          (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x02000000 */

+#define DMAMUX_CxCR_SYNC_ID_2          (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x04000000 */

+#define DMAMUX_CxCR_SYNC_ID_3          (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x08000000 */

+#define DMAMUX_CxCR_SYNC_ID_4          (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x10000000 */

+

+/********************  Bits definition for DMAMUX_CSR register  **************/

+#define DMAMUX_CSR_SOF0_Pos            (0U)

+#define DMAMUX_CSR_SOF0_Msk            (0x1UL << DMAMUX_CSR_SOF0_Pos)          /*!< 0x00000001 */

+#define DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0_Msk                     /*!< Channel 0 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF1_Pos            (1U)

+#define DMAMUX_CSR_SOF1_Msk            (0x1UL << DMAMUX_CSR_SOF1_Pos)          /*!< 0x00000002 */

+#define DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1_Msk                     /*!< Channel 1 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF2_Pos            (2U)

+#define DMAMUX_CSR_SOF2_Msk            (0x1UL << DMAMUX_CSR_SOF2_Pos)          /*!< 0x00000004 */

+#define DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2_Msk                     /*!< Channel 2 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF3_Pos            (3U)

+#define DMAMUX_CSR_SOF3_Msk            (0x1UL << DMAMUX_CSR_SOF3_Pos)          /*!< 0x00000008 */

+#define DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3_Msk                     /*!< Channel 3 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF4_Pos            (4U)

+#define DMAMUX_CSR_SOF4_Msk            (0x1UL << DMAMUX_CSR_SOF4_Pos)          /*!< 0x00000010 */

+#define DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4_Msk                     /*!< Channel 4 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF5_Pos            (5U)

+#define DMAMUX_CSR_SOF5_Msk            (0x1UL << DMAMUX_CSR_SOF5_Pos)          /*!< 0x00000020 */

+#define DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5_Msk                     /*!< Channel 5 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF6_Pos            (6U)

+#define DMAMUX_CSR_SOF6_Msk            (0x1UL << DMAMUX_CSR_SOF6_Pos)          /*!< 0x00000040 */

+#define DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6_Msk                     /*!< Channel 6 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF7_Pos            (7U)

+#define DMAMUX_CSR_SOF7_Msk            (0x1UL << DMAMUX_CSR_SOF7_Pos)          /*!< 0x00000080 */

+#define DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7_Msk                     /*!< Channel 7 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF8_Pos            (8U)

+#define DMAMUX_CSR_SOF8_Msk            (0x1UL << DMAMUX_CSR_SOF8_Pos)          /*!< 0x00000100 */

+#define DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8_Msk                     /*!< Channel 8 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF9_Pos            (9U)

+#define DMAMUX_CSR_SOF9_Msk            (0x1UL << DMAMUX_CSR_SOF9_Pos)          /*!< 0x00000200 */

+#define DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9_Msk                     /*!< Channel 9 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF10_Pos           (10U)

+#define DMAMUX_CSR_SOF10_Msk           (0x1UL << DMAMUX_CSR_SOF10_Pos)         /*!< 0x00000400 */

+#define DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10_Msk                    /*!< Channel 10 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF11_Pos           (11U)

+#define DMAMUX_CSR_SOF11_Msk           (0x1UL << DMAMUX_CSR_SOF11_Pos)         /*!< 0x00000800 */

+#define DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11_Msk                    /*!< Channel 11 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF12_Pos           (12U)

+#define DMAMUX_CSR_SOF12_Msk           (0x1UL << DMAMUX_CSR_SOF12_Pos)         /*!< 0x00001000 */

+#define DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12_Msk                    /*!< Channel 12 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF13_Pos           (13U)

+#define DMAMUX_CSR_SOF13_Msk           (0x1UL << DMAMUX_CSR_SOF13_Pos)         /*!< 0x00002000 */

+#define DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13_Msk                    /*!< Channel 13 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF14_Pos           (14U)

+#define DMAMUX_CSR_SOF14_Msk           (0x1UL << DMAMUX_CSR_SOF14_Pos)         /*!< 0x00004000 */

+#define DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14_Msk                    /*!< Channel 14 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF15_Pos           (15U)

+#define DMAMUX_CSR_SOF15_Msk           (0x1UL << DMAMUX_CSR_SOF15_Pos)         /*!< 0x00008000 */

+#define DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15_Msk                    /*!< Channel 15 Synchronization overrun event flag */

+

+/********************  Bits definition for DMAMUX_CFR register  **************/

+#define DMAMUX_CFR_CSOF0_Pos           (0U)

+#define DMAMUX_CFR_CSOF0_Msk           (0x1UL << DMAMUX_CFR_CSOF0_Pos)         /*!< 0x00000001 */

+#define DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0_Msk                    /*!< Channel 0 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF1_Pos           (1U)

+#define DMAMUX_CFR_CSOF1_Msk           (0x1UL << DMAMUX_CFR_CSOF1_Pos)         /*!< 0x00000002 */

+#define DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1_Msk                    /*!< Channel 1 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF2_Pos           (2U)

+#define DMAMUX_CFR_CSOF2_Msk           (0x1UL << DMAMUX_CFR_CSOF2_Pos)         /*!< 0x00000004 */

+#define DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2_Msk                    /*!< Channel 2 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF3_Pos           (3U)

+#define DMAMUX_CFR_CSOF3_Msk           (0x1UL << DMAMUX_CFR_CSOF3_Pos)         /*!< 0x00000008 */

+#define DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3_Msk                    /*!< Channel 3 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF4_Pos           (4U)

+#define DMAMUX_CFR_CSOF4_Msk           (0x1UL << DMAMUX_CFR_CSOF4_Pos)         /*!< 0x00000010 */

+#define DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4_Msk                    /*!< Channel 4 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF5_Pos           (5U)

+#define DMAMUX_CFR_CSOF5_Msk           (0x1UL << DMAMUX_CFR_CSOF5_Pos)         /*!< 0x00000020 */

+#define DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5_Msk                    /*!< Channel 5 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF6_Pos           (6U)

+#define DMAMUX_CFR_CSOF6_Msk           (0x1UL << DMAMUX_CFR_CSOF6_Pos)         /*!< 0x00000040 */

+#define DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6_Msk                    /*!< Channel 6 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF7_Pos           (7U)

+#define DMAMUX_CFR_CSOF7_Msk           (0x1UL << DMAMUX_CFR_CSOF7_Pos)         /*!< 0x00000080 */

+#define DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7_Msk                    /*!< Channel 7 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF8_Pos           (8U)

+#define DMAMUX_CFR_CSOF8_Msk           (0x1UL << DMAMUX_CFR_CSOF8_Pos)         /*!< 0x00000100 */

+#define DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8_Msk                    /*!< Channel 8 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF9_Pos           (9U)

+#define DMAMUX_CFR_CSOF9_Msk           (0x1UL << DMAMUX_CFR_CSOF9_Pos)         /*!< 0x00000200 */

+#define DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9_Msk                    /*!< Channel 9 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF10_Pos          (10U)

+#define DMAMUX_CFR_CSOF10_Msk          (0x1UL << DMAMUX_CFR_CSOF10_Pos)        /*!< 0x00000400 */

+#define DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10_Msk                   /*!< Channel 10 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF11_Pos          (11U)

+#define DMAMUX_CFR_CSOF11_Msk          (0x1UL << DMAMUX_CFR_CSOF11_Pos)        /*!< 0x00000800 */

+#define DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11_Msk                   /*!< Channel 11 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF12_Pos          (12U)

+#define DMAMUX_CFR_CSOF12_Msk          (0x1UL << DMAMUX_CFR_CSOF12_Pos)        /*!< 0x00001000 */

+#define DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12_Msk                   /*!< Channel 12 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF13_Pos          (13U)

+#define DMAMUX_CFR_CSOF13_Msk          (0x1UL << DMAMUX_CFR_CSOF13_Pos)        /*!< 0x00002000 */

+#define DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13_Msk                   /*!< Channel 13 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF14_Pos          (14U)

+#define DMAMUX_CFR_CSOF14_Msk          (0x1UL << DMAMUX_CFR_CSOF14_Pos)        /*!< 0x00004000 */

+#define DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14_Msk                   /*!< Channel 14 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF15_Pos          (15U)

+#define DMAMUX_CFR_CSOF15_Msk          (0x1UL << DMAMUX_CFR_CSOF15_Pos)        /*!< 0x00008000 */

+#define DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15_Msk                   /*!< Channel 15 Clear synchronization overrun event flag */

+

+/********************  Bits definition for DMAMUX_RGxCR register  ************/

+#define DMAMUX_RGxCR_SIG_ID_Pos        (0U)

+#define DMAMUX_RGxCR_SIG_ID_Msk        (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)     /*!< 0x0000001F */

+#define DMAMUX_RGxCR_SIG_ID            DMAMUX_RGxCR_SIG_ID_Msk                 /*!< Signal identification */

+#define DMAMUX_RGxCR_SIG_ID_0          (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000001 */

+#define DMAMUX_RGxCR_SIG_ID_1          (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000002 */

+#define DMAMUX_RGxCR_SIG_ID_2          (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000004 */

+#define DMAMUX_RGxCR_SIG_ID_3          (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000008 */

+#define DMAMUX_RGxCR_SIG_ID_4          (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000010 */

+#define DMAMUX_RGxCR_OIE_Pos           (8U)

+#define DMAMUX_RGxCR_OIE_Msk           (0x1UL << DMAMUX_RGxCR_OIE_Pos)         /*!< 0x00000100 */

+#define DMAMUX_RGxCR_OIE               DMAMUX_RGxCR_OIE_Msk                    /*!< Trigger overrun interrupt enable */

+#define DMAMUX_RGxCR_GE_Pos            (16U)

+#define DMAMUX_RGxCR_GE_Msk            (0x1UL << DMAMUX_RGxCR_GE_Pos)          /*!< 0x00010000 */

+#define DMAMUX_RGxCR_GE                DMAMUX_RGxCR_GE_Msk                     /*!< DMA request generator enable */

+#define DMAMUX_RGxCR_GPOL_Pos          (17U)

+#define DMAMUX_RGxCR_GPOL_Msk          (0x3UL << DMAMUX_RGxCR_GPOL_Pos)        /*!< 0x00060000 */

+#define DMAMUX_RGxCR_GPOL              DMAMUX_RGxCR_GPOL_Msk                   /*!< DMA request generator trigger polarity */

+#define DMAMUX_RGxCR_GPOL_0            (0x1UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00020000 */

+#define DMAMUX_RGxCR_GPOL_1            (0x2UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00040000 */

+#define DMAMUX_RGxCR_GNBREQ_Pos        (19U)

+#define DMAMUX_RGxCR_GNBREQ_Msk        (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)     /*!< 0x00F80000 */

+#define DMAMUX_RGxCR_GNBREQ            DMAMUX_RGxCR_GNBREQ_Msk                 /*!< Number of DMA requests to be generated */

+#define DMAMUX_RGxCR_GNBREQ_0          (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00080000 */

+#define DMAMUX_RGxCR_GNBREQ_1          (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00100000 */

+#define DMAMUX_RGxCR_GNBREQ_2          (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00200000 */

+#define DMAMUX_RGxCR_GNBREQ_3          (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00400000 */

+#define DMAMUX_RGxCR_GNBREQ_4          (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00800000 */

+

+/********************  Bits definition for DMAMUX_RGSR register  **************/

+#define DMAMUX_RGSR_OF0_Pos            (0U)

+#define DMAMUX_RGSR_OF0_Msk            (0x1UL << DMAMUX_RGSR_OF0_Pos)          /*!< 0x00000001 */

+#define DMAMUX_RGSR_OF0                DMAMUX_RGSR_OF0_Msk                     /*!< Request generator channel 0 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF1_Pos            (1U)

+#define DMAMUX_RGSR_OF1_Msk            (0x1UL << DMAMUX_RGSR_OF1_Pos)          /*!< 0x00000002 */

+#define DMAMUX_RGSR_OF1                DMAMUX_RGSR_OF1_Msk                     /*!< Request generator channel 1 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF2_Pos            (2U)

+#define DMAMUX_RGSR_OF2_Msk            (0x1UL << DMAMUX_RGSR_OF2_Pos)          /*!< 0x00000004 */

+#define DMAMUX_RGSR_OF2                DMAMUX_RGSR_OF2_Msk                     /*!< Request generator channel 2 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF3_Pos            (3U)

+#define DMAMUX_RGSR_OF3_Msk            (0x1UL << DMAMUX_RGSR_OF3_Pos)          /*!< 0x00000008 */

+#define DMAMUX_RGSR_OF3                DMAMUX_RGSR_OF3_Msk                     /*!< Request generator channel 3 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF4_Pos            (4U)

+#define DMAMUX_RGSR_OF4_Msk            (0x1UL << DMAMUX_RGSR_OF4_Pos)          /*!< 0x00000010 */

+#define DMAMUX_RGSR_OF4                DMAMUX_RGSR_OF4_Msk                     /*!< Request generator channel 4 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF5_Pos            (5U)

+#define DMAMUX_RGSR_OF5_Msk            (0x1UL << DMAMUX_RGSR_OF5_Pos)          /*!< 0x00000020 */

+#define DMAMUX_RGSR_OF5                DMAMUX_RGSR_OF5_Msk                     /*!< Request generator channel 5 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF6_Pos            (6U)

+#define DMAMUX_RGSR_OF6_Msk            (0x1UL << DMAMUX_RGSR_OF6_Pos)          /*!< 0x00000040 */

+#define DMAMUX_RGSR_OF6                DMAMUX_RGSR_OF6_Msk                     /*!< Request generator channel 6 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF7_Pos            (7U)

+#define DMAMUX_RGSR_OF7_Msk            (0x1UL << DMAMUX_RGSR_OF7_Pos)          /*!< 0x00000080 */

+#define DMAMUX_RGSR_OF7                DMAMUX_RGSR_OF7_Msk                     /*!< Request generator channel 7 Trigger overrun event flag */

+

+/********************  Bits definition for DMAMUX_RGCFR register  **************/

+#define DMAMUX_RGCFR_COF0_Pos          (0U)

+#define DMAMUX_RGCFR_COF0_Msk          (0x1UL << DMAMUX_RGCFR_COF0_Pos)        /*!< 0x00000001 */

+#define DMAMUX_RGCFR_COF0              DMAMUX_RGCFR_COF0_Msk                   /*!< Request generator channel 0 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF1_Pos          (1U)

+#define DMAMUX_RGCFR_COF1_Msk          (0x1UL << DMAMUX_RGCFR_COF1_Pos)        /*!< 0x00000002 */

+#define DMAMUX_RGCFR_COF1              DMAMUX_RGCFR_COF1_Msk                   /*!< Request generator channel 1 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF2_Pos          (2U)

+#define DMAMUX_RGCFR_COF2_Msk          (0x1UL << DMAMUX_RGCFR_COF2_Pos)        /*!< 0x00000004 */

+#define DMAMUX_RGCFR_COF2              DMAMUX_RGCFR_COF2_Msk                   /*!< Request generator channel 2 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF3_Pos          (3U)

+#define DMAMUX_RGCFR_COF3_Msk          (0x1UL << DMAMUX_RGCFR_COF3_Pos)        /*!< 0x00000008 */

+#define DMAMUX_RGCFR_COF3              DMAMUX_RGCFR_COF3_Msk                   /*!< Request generator channel 3 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF4_Pos          (4U)

+#define DMAMUX_RGCFR_COF4_Msk          (0x1UL << DMAMUX_RGCFR_COF4_Pos)        /*!< 0x00000010 */

+#define DMAMUX_RGCFR_COF4              DMAMUX_RGCFR_COF4_Msk                   /*!< Request generator channel 4 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF5_Pos          (5U)

+#define DMAMUX_RGCFR_COF5_Msk          (0x1UL << DMAMUX_RGCFR_COF5_Pos)        /*!< 0x00000020 */

+#define DMAMUX_RGCFR_COF5              DMAMUX_RGCFR_COF5_Msk                   /*!< Request generator channel 5 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF6_Pos          (6U)

+#define DMAMUX_RGCFR_COF6_Msk          (0x1UL << DMAMUX_RGCFR_COF6_Pos)        /*!< 0x00000040 */

+#define DMAMUX_RGCFR_COF6              DMAMUX_RGCFR_COF6_Msk                   /*!< Request generator channel 6 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF7_Pos          (7U)

+#define DMAMUX_RGCFR_COF7_Msk          (0x1UL << DMAMUX_RGCFR_COF7_Pos)        /*!< 0x00000080 */

+#define DMAMUX_RGCFR_COF7              DMAMUX_RGCFR_COF7_Msk                   /*!< Request generator channel 7 Clear trigger overrun event flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         AHB Master DMA2D Controller (DMA2D)                */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for DMA2D_CR register  ******************/

+

+#define DMA2D_CR_START_Pos         (0U)

+#define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)               /*!< 0x00000001 */

+#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer                          */

+#define DMA2D_CR_SUSP_Pos          (1U)

+#define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                /*!< 0x00000002 */

+#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer                        */

+#define DMA2D_CR_ABORT_Pos         (2U)

+#define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)               /*!< 0x00000004 */

+#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer                          */

+#define DMA2D_CR_LOM_Pos           (6U)

+#define DMA2D_CR_LOM_Msk           (0x1UL << DMA2D_CR_LOM_Pos)                 /*!< 0x00000040 */

+#define DMA2D_CR_LOM               DMA2D_CR_LOM_Msk                            /*!< Line Offset Mode                         */

+#define DMA2D_CR_TEIE_Pos          (8U)

+#define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                /*!< 0x00000100 */

+#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable         */

+#define DMA2D_CR_TCIE_Pos          (9U)

+#define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                /*!< 0x00000200 */

+#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable      */

+#define DMA2D_CR_TWIE_Pos          (10U)

+#define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                /*!< 0x00000400 */

+#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable     */

+#define DMA2D_CR_CAEIE_Pos         (11U)

+#define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)               /*!< 0x00000800 */

+#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable      */

+#define DMA2D_CR_CTCIE_Pos         (12U)

+#define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)               /*!< 0x00001000 */

+#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */

+#define DMA2D_CR_CEIE_Pos          (13U)

+#define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                /*!< 0x00002000 */

+#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable    */

+#define DMA2D_CR_MODE_Pos          (16U)

+#define DMA2D_CR_MODE_Msk          (0x7UL << DMA2D_CR_MODE_Pos)                /*!< 0x00070000 */

+#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[2:0]                         */

+#define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */

+#define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */

+#define DMA2D_CR_MODE_2            (0x4UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00040000 */

+

+/********************  Bit definition for DMA2D_ISR register  *****************/

+

+#define DMA2D_ISR_TEIF_Pos         (0U)

+#define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)               /*!< 0x00000001 */

+#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag         */

+#define DMA2D_ISR_TCIF_Pos         (1U)

+#define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)               /*!< 0x00000002 */

+#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag      */

+#define DMA2D_ISR_TWIF_Pos         (2U)

+#define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)               /*!< 0x00000004 */

+#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag     */

+#define DMA2D_ISR_CAEIF_Pos        (3U)

+#define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)              /*!< 0x00000008 */

+#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag      */

+#define DMA2D_ISR_CTCIF_Pos        (4U)

+#define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)              /*!< 0x00000010 */

+#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */

+#define DMA2D_ISR_CEIF_Pos         (5U)

+#define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)               /*!< 0x00000020 */

+#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag    */

+

+/********************  Bit definition for DMA2D_IFCR register  ****************/

+

+#define DMA2D_IFCR_CTEIF_Pos       (0U)

+#define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)             /*!< 0x00000001 */

+#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */

+#define DMA2D_IFCR_CTCIF_Pos       (1U)

+#define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)             /*!< 0x00000002 */

+#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */

+#define DMA2D_IFCR_CTWIF_Pos       (2U)

+#define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)             /*!< 0x00000004 */

+#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */

+#define DMA2D_IFCR_CAECIF_Pos      (3U)

+#define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)            /*!< 0x00000008 */

+#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */

+#define DMA2D_IFCR_CCTCIF_Pos      (4U)

+#define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)            /*!< 0x00000010 */

+#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */

+#define DMA2D_IFCR_CCEIF_Pos       (5U)

+#define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)             /*!< 0x00000020 */

+#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */

+

+/********************  Bit definition for DMA2D_FGMAR register  ***************/

+

+#define DMA2D_FGMAR_MA_Pos         (0U)

+#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)        /*!< 0xFFFFFFFF */

+#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Foreground Memory Address */

+

+/********************  Bit definition for DMA2D_FGOR register  ****************/

+

+#define DMA2D_FGOR_LO_Pos          (0U)

+#define DMA2D_FGOR_LO_Msk          (0xFFFFUL << DMA2D_FGOR_LO_Pos)             /*!< 0x0000FFFF */

+#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */

+

+/********************  Bit definition for DMA2D_BGMAR register  ***************/

+

+#define DMA2D_BGMAR_MA_Pos         (0U)

+#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)        /*!< 0xFFFFFFFF */

+#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Background Memory Address */

+

+/********************  Bit definition for DMA2D_BGOR register  ****************/

+

+#define DMA2D_BGOR_LO_Pos          (0U)

+#define DMA2D_BGOR_LO_Msk          (0xFFFFUL << DMA2D_BGOR_LO_Pos)             /*!< 0x0000FFFF */

+#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */

+

+/********************  Bit definition for DMA2D_FGPFCCR register  *************/

+

+#define DMA2D_FGPFCCR_CM_Pos       (0U)

+#define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x0000000F */

+#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */

+#define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */

+#define DMA2D_FGPFCCR_CCM_Pos      (4U)

+#define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)            /*!< 0x00000010 */

+#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */

+#define DMA2D_FGPFCCR_START_Pos    (5U)

+#define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)          /*!< 0x00000020 */

+#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */

+#define DMA2D_FGPFCCR_CS_Pos       (8U)

+#define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)            /*!< 0x0000FF00 */

+#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */

+#define DMA2D_FGPFCCR_AM_Pos       (16U)

+#define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00030000 */

+#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */

+#define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */

+#define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */

+#define DMA2D_FGPFCCR_CSS_Pos      (18U)

+#define DMA2D_FGPFCCR_CSS_Msk      (0x3UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x000C0000 */

+#define DMA2D_FGPFCCR_CSS          DMA2D_FGPFCCR_CSS_Msk                       /* !< Chroma Sub-Sampling */

+#define DMA2D_FGPFCCR_CSS_0        (0x1UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00040000 */

+#define DMA2D_FGPFCCR_CSS_1        (0x2UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00080000 */

+#define DMA2D_FGPFCCR_AI_Pos       (20U)

+#define DMA2D_FGPFCCR_AI_Msk       (0x1UL << DMA2D_FGPFCCR_AI_Pos)             /*!< 0x00100000 */

+#define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Foreground Input Alpha Inverted */

+#define DMA2D_FGPFCCR_RBS_Pos      (21U)

+#define DMA2D_FGPFCCR_RBS_Msk      (0x1UL << DMA2D_FGPFCCR_RBS_Pos)            /*!< 0x00200000 */

+#define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Foreground Input Red Blue Swap */

+#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)

+#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */

+#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */

+

+/********************  Bit definition for DMA2D_FGCOLR register  **************/

+

+#define DMA2D_FGCOLR_BLUE_Pos      (0U)

+#define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)           /*!< 0x000000FF */

+#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Foreground Blue Value */

+#define DMA2D_FGCOLR_GREEN_Pos     (8U)

+#define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */

+#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Foreground Green Value */

+#define DMA2D_FGCOLR_RED_Pos       (16U)

+#define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)            /*!< 0x00FF0000 */

+#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Foreground Red Value */

+

+/********************  Bit definition for DMA2D_BGPFCCR register  *************/

+

+#define DMA2D_BGPFCCR_CM_Pos       (0U)

+#define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x0000000F */

+#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */

+#define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_BGPFCCR_CM_3         (0x8UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000008 */

+#define DMA2D_BGPFCCR_CCM_Pos      (4U)

+#define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)            /*!< 0x00000010 */

+#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */

+#define DMA2D_BGPFCCR_START_Pos    (5U)

+#define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)          /*!< 0x00000020 */

+#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */

+#define DMA2D_BGPFCCR_CS_Pos       (8U)

+#define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)            /*!< 0x0000FF00 */

+#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */

+#define DMA2D_BGPFCCR_AM_Pos       (16U)

+#define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00030000 */

+#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */

+#define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */

+#define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */

+#define DMA2D_BGPFCCR_AI_Pos       (20U)

+#define DMA2D_BGPFCCR_AI_Msk       (0x1UL << DMA2D_BGPFCCR_AI_Pos)             /*!< 0x00100000 */

+#define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< background Input Alpha Inverted */

+#define DMA2D_BGPFCCR_RBS_Pos      (21U)

+#define DMA2D_BGPFCCR_RBS_Msk      (0x1UL << DMA2D_BGPFCCR_RBS_Pos)            /*!< 0x00200000 */

+#define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Background Input Red Blue Swap */

+#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)

+#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */

+#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */

+

+/********************  Bit definition for DMA2D_BGCOLR register  **************/

+

+#define DMA2D_BGCOLR_BLUE_Pos      (0U)

+#define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)           /*!< 0x000000FF */

+#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Background Blue Value */

+#define DMA2D_BGCOLR_GREEN_Pos     (8U)

+#define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */

+#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Background Green Value */

+#define DMA2D_BGCOLR_RED_Pos       (16U)

+#define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)            /*!< 0x00FF0000 */

+#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Background Red Value */

+

+/********************  Bit definition for DMA2D_FGCMAR register  **************/

+

+#define DMA2D_FGCMAR_MA_Pos        (0U)

+#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */

+#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Foreground CLUT Memory Address */

+

+/********************  Bit definition for DMA2D_BGCMAR register  **************/

+

+#define DMA2D_BGCMAR_MA_Pos        (0U)

+#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */

+#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Background CLUT Memory Address */

+

+/********************  Bit definition for DMA2D_OPFCCR register  **************/

+

+#define DMA2D_OPFCCR_CM_Pos        (0U)

+#define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000007 */

+#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Output Color mode CM[2:0] */

+#define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_OPFCCR_SB_Pos        (8U)

+#define DMA2D_OPFCCR_SB_Msk        (0x1UL << DMA2D_OPFCCR_SB_Pos)              /*!< 0x00000100 */

+#define DMA2D_OPFCCR_SB            DMA2D_OPFCCR_SB_Msk                         /*!< Swap Bytes */

+#define DMA2D_OPFCCR_AI_Pos        (20U)

+#define DMA2D_OPFCCR_AI_Msk        (0x1UL << DMA2D_OPFCCR_AI_Pos)              /*!< 0x00100000 */

+#define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Output Alpha Inverted */

+#define DMA2D_OPFCCR_RBS_Pos       (21U)

+#define DMA2D_OPFCCR_RBS_Msk       (0x1UL << DMA2D_OPFCCR_RBS_Pos)             /*!< 0x00200000 */

+#define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Output Red Blue Swap */

+

+/********************  Bit definition for DMA2D_OCOLR register  ***************/

+

+/*!<Mode_ARGB8888/RGB888 */

+

+#define DMA2D_OCOLR_BLUE_1_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_1_Msk     (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos)            /*0x000000FFU*/

+#define DMA2D_OCOLR_BLUE_1         DMA2D_OCOLR_BLUE_1_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_1_Pos    (8U)

+#define DMA2D_OCOLR_GREEN_1_Msk    (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos)            /*0x0000FF00U)*/

+#define DMA2D_OCOLR_GREEN_1        DMA2D_OCOLR_GREEN_1_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_1_Pos      (16U)

+#define DMA2D_OCOLR_RED_1_Msk      (0xFFUL << DMA2D_OCOLR_RED_1_Pos)            /*0x00FF0000U */

+#define DMA2D_OCOLR_RED_1          DMA2D_OCOLR_RED_1_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_1_Pos    (24U)

+#define DMA2D_OCOLR_ALPHA_1_Msk    (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos)          /*0xFF000000U*/

+#define DMA2D_OCOLR_ALPHA_1        DMA2D_OCOLR_ALPHA_1_Msk                     /*!< Output Alpha Channel Value */

+

+/*!<Mode_RGB565 */

+#define DMA2D_OCOLR_BLUE_2_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_2_Msk     (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos)            /*0x0000001FU*/

+#define DMA2D_OCOLR_BLUE_2         DMA2D_OCOLR_BLUE_2_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_2_Pos    (5U)

+#define DMA2D_OCOLR_GREEN_2_Msk    (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos)          /* 0x000007E0U */

+#define DMA2D_OCOLR_GREEN_2        DMA2D_OCOLR_GREEN_2_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_2_Pos      (11U)

+#define DMA2D_OCOLR_RED_2_Msk      (0xF8UL<<DMA2D_OCOLR_RED_2_Pos)              /*0x0000F800U*/

+#define DMA2D_OCOLR_RED_2          DMA2D_OCOLR_RED_2_Msk                       /*!< Output Red Value */

+

+/*!<Mode_ARGB1555 */

+#define DMA2D_OCOLR_BLUE_3_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_3_Msk     (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos)           /*0x0000001FU*/

+#define DMA2D_OCOLR_BLUE_3         DMA2D_OCOLR_BLUE_3_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_3_Pos    (5U)

+#define DMA2D_OCOLR_GREEN_3_Msk    (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos)          /*0x000003E0U*/

+#define DMA2D_OCOLR_GREEN_3        DMA2D_OCOLR_GREEN_3_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_3_Pos      (10U)

+#define DMA2D_OCOLR_RED_3_Msk      (0x7CUL << DMA2D_OCOLR_RED_3_Pos)            /* 0x00007C00U*/

+#define DMA2D_OCOLR_RED_3          DMA2D_OCOLR_RED_3_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_3_Pos    (15U)

+#define DMA2D_OCOLR_ALPHA_3_Msk    (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos)           /*0x00008000U*/

+#define DMA2D_OCOLR_ALPHA_3        DMA2D_OCOLR_ALPHA_3_Msk                     /*!< Output Alpha Channel Value */

+

+/*!<Mode_ARGB4444 */

+#define DMA2D_OCOLR_BLUE_4_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_4_Msk     (0xFUL << DMA2D_OCOLR_BLUE_4_Pos)            /*0x0000000FU*/

+#define DMA2D_OCOLR_BLUE_4         DMA2D_OCOLR_BLUE_4_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_4_Pos    (4U)

+#define DMA2D_OCOLR_GREEN_4_Msk    (0xFUL << DMA2D_OCOLR_GREEN_4_Pos)           /*0x000000F0U*/

+#define DMA2D_OCOLR_GREEN_4        DMA2D_OCOLR_GREEN_4_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_4_Pos      (8U)

+#define DMA2D_OCOLR_RED_4_Msk      (0xFUL << DMA2D_OCOLR_RED_4_Pos)             /*0x00000F00U*/

+#define DMA2D_OCOLR_RED_4          DMA2D_OCOLR_RED_4_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_4_Pos    (12U)

+#define DMA2D_OCOLR_ALPHA_4_Msk    (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos)            /*0x0000F000U*/

+#define DMA2D_OCOLR_ALPHA_4        DMA2D_OCOLR_ALPHA_4_Msk                     /*!< Output Alpha Channel Value */

+

+/********************  Bit definition for DMA2D_OMAR register  ****************/

+

+#define DMA2D_OMAR_MA_Pos          (0U)

+#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)         /*!< 0xFFFFFFFF */

+#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Output Memory Address */

+

+/********************  Bit definition for DMA2D_OOR register  *****************/

+

+#define DMA2D_OOR_LO_Pos           (0U)

+#define DMA2D_OOR_LO_Msk           (0xFFFFUL << DMA2D_OOR_LO_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Output Line Offset */

+

+/********************  Bit definition for DMA2D_NLR register  *****************/

+

+#define DMA2D_NLR_NL_Pos           (0U)

+#define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */

+#define DMA2D_NLR_PL_Pos           (16U)

+#define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)              /*!< 0x3FFF0000 */

+#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */

+

+/********************  Bit definition for DMA2D_LWR register  *****************/

+

+#define DMA2D_LWR_LW_Pos           (0U)

+#define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */

+

+/********************  Bit definition for DMA2D_AMTCR register  ***************/

+

+#define DMA2D_AMTCR_EN_Pos         (0U)

+#define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)               /*!< 0x00000001 */

+#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */

+#define DMA2D_AMTCR_DT_Pos         (8U)

+#define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)              /*!< 0x0000FF00 */

+#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */

+

+

+/********************  Bit definition for DMA2D_FGCLUT register  **************/

+

+/********************  Bit definition for DMA2D_BGCLUT register  **************/

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                    External Interrupt/Event Controller                     */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for EXTI_RTSR1 register  *******************/

+#define EXTI_RTSR1_TR_Pos          (0U)

+#define EXTI_RTSR1_TR_Msk          (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)           /*!< 0x003FFFFF */

+#define EXTI_RTSR1_TR              EXTI_RTSR1_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR1_TR0_Pos         (0U)

+#define EXTI_RTSR1_TR0_Msk         (0x1UL << EXTI_RTSR1_TR0_Pos)               /*!< 0x00000001 */

+#define EXTI_RTSR1_TR0             EXTI_RTSR1_TR0_Msk                          /*!< Rising trigger event configuration bit of line 0 */

+#define EXTI_RTSR1_TR1_Pos         (1U)

+#define EXTI_RTSR1_TR1_Msk         (0x1UL << EXTI_RTSR1_TR1_Pos)               /*!< 0x00000002 */

+#define EXTI_RTSR1_TR1             EXTI_RTSR1_TR1_Msk                          /*!< Rising trigger event configuration bit of line 1 */

+#define EXTI_RTSR1_TR2_Pos         (2U)

+#define EXTI_RTSR1_TR2_Msk         (0x1UL << EXTI_RTSR1_TR2_Pos)               /*!< 0x00000004 */

+#define EXTI_RTSR1_TR2             EXTI_RTSR1_TR2_Msk                          /*!< Rising trigger event configuration bit of line 2 */

+#define EXTI_RTSR1_TR3_Pos         (3U)

+#define EXTI_RTSR1_TR3_Msk         (0x1UL << EXTI_RTSR1_TR3_Pos)               /*!< 0x00000008 */

+#define EXTI_RTSR1_TR3             EXTI_RTSR1_TR3_Msk                          /*!< Rising trigger event configuration bit of line 3 */

+#define EXTI_RTSR1_TR4_Pos         (4U)

+#define EXTI_RTSR1_TR4_Msk         (0x1UL << EXTI_RTSR1_TR4_Pos)               /*!< 0x00000010 */

+#define EXTI_RTSR1_TR4             EXTI_RTSR1_TR4_Msk                          /*!< Rising trigger event configuration bit of line 4 */

+#define EXTI_RTSR1_TR5_Pos         (5U)

+#define EXTI_RTSR1_TR5_Msk         (0x1UL << EXTI_RTSR1_TR5_Pos)               /*!< 0x00000020 */

+#define EXTI_RTSR1_TR5             EXTI_RTSR1_TR5_Msk                          /*!< Rising trigger event configuration bit of line 5 */

+#define EXTI_RTSR1_TR6_Pos         (6U)

+#define EXTI_RTSR1_TR6_Msk         (0x1UL << EXTI_RTSR1_TR6_Pos)               /*!< 0x00000040 */

+#define EXTI_RTSR1_TR6             EXTI_RTSR1_TR6_Msk                          /*!< Rising trigger event configuration bit of line 6 */

+#define EXTI_RTSR1_TR7_Pos         (7U)

+#define EXTI_RTSR1_TR7_Msk         (0x1UL << EXTI_RTSR1_TR7_Pos)               /*!< 0x00000080 */

+#define EXTI_RTSR1_TR7             EXTI_RTSR1_TR7_Msk                          /*!< Rising trigger event configuration bit of line 7 */

+#define EXTI_RTSR1_TR8_Pos         (8U)

+#define EXTI_RTSR1_TR8_Msk         (0x1UL << EXTI_RTSR1_TR8_Pos)               /*!< 0x00000100 */

+#define EXTI_RTSR1_TR8             EXTI_RTSR1_TR8_Msk                          /*!< Rising trigger event configuration bit of line 8 */

+#define EXTI_RTSR1_TR9_Pos         (9U)

+#define EXTI_RTSR1_TR9_Msk         (0x1UL << EXTI_RTSR1_TR9_Pos)               /*!< 0x00000200 */

+#define EXTI_RTSR1_TR9             EXTI_RTSR1_TR9_Msk                          /*!< Rising trigger event configuration bit of line 9 */

+#define EXTI_RTSR1_TR10_Pos        (10U)

+#define EXTI_RTSR1_TR10_Msk        (0x1UL << EXTI_RTSR1_TR10_Pos)              /*!< 0x00000400 */

+#define EXTI_RTSR1_TR10            EXTI_RTSR1_TR10_Msk                         /*!< Rising trigger event configuration bit of line 10 */

+#define EXTI_RTSR1_TR11_Pos        (11U)

+#define EXTI_RTSR1_TR11_Msk        (0x1UL << EXTI_RTSR1_TR11_Pos)              /*!< 0x00000800 */

+#define EXTI_RTSR1_TR11            EXTI_RTSR1_TR11_Msk                         /*!< Rising trigger event configuration bit of line 11 */

+#define EXTI_RTSR1_TR12_Pos        (12U)

+#define EXTI_RTSR1_TR12_Msk        (0x1UL << EXTI_RTSR1_TR12_Pos)              /*!< 0x00001000 */

+#define EXTI_RTSR1_TR12            EXTI_RTSR1_TR12_Msk                         /*!< Rising trigger event configuration bit of line 12 */

+#define EXTI_RTSR1_TR13_Pos        (13U)

+#define EXTI_RTSR1_TR13_Msk        (0x1UL << EXTI_RTSR1_TR13_Pos)              /*!< 0x00002000 */

+#define EXTI_RTSR1_TR13            EXTI_RTSR1_TR13_Msk                         /*!< Rising trigger event configuration bit of line 13 */

+#define EXTI_RTSR1_TR14_Pos        (14U)

+#define EXTI_RTSR1_TR14_Msk        (0x1UL << EXTI_RTSR1_TR14_Pos)              /*!< 0x00004000 */

+#define EXTI_RTSR1_TR14            EXTI_RTSR1_TR14_Msk                         /*!< Rising trigger event configuration bit of line 14 */

+#define EXTI_RTSR1_TR15_Pos        (15U)

+#define EXTI_RTSR1_TR15_Msk        (0x1UL << EXTI_RTSR1_TR15_Pos)              /*!< 0x00008000 */

+#define EXTI_RTSR1_TR15            EXTI_RTSR1_TR15_Msk                         /*!< Rising trigger event configuration bit of line 15 */

+#define EXTI_RTSR1_TR16_Pos        (16U)

+#define EXTI_RTSR1_TR16_Msk        (0x1UL << EXTI_RTSR1_TR16_Pos)              /*!< 0x00010000 */

+#define EXTI_RTSR1_TR16            EXTI_RTSR1_TR16_Msk                         /*!< Rising trigger event configuration bit of line 16 */

+#define EXTI_RTSR1_TR17_Pos        (17U)

+#define EXTI_RTSR1_TR17_Msk        (0x1UL << EXTI_RTSR1_TR17_Pos)              /*!< 0x00020000 */

+#define EXTI_RTSR1_TR17            EXTI_RTSR1_TR17_Msk                         /*!< Rising trigger event configuration bit of line 17 */

+#define EXTI_RTSR1_TR18_Pos        (18U)

+#define EXTI_RTSR1_TR18_Msk        (0x1UL << EXTI_RTSR1_TR18_Pos)              /*!< 0x00040000 */

+#define EXTI_RTSR1_TR18            EXTI_RTSR1_TR18_Msk                         /*!< Rising trigger event configuration bit of line 18 */

+#define EXTI_RTSR1_TR19_Pos        (19U)

+#define EXTI_RTSR1_TR19_Msk        (0x1UL << EXTI_RTSR1_TR19_Pos)              /*!< 0x00080000 */

+#define EXTI_RTSR1_TR19            EXTI_RTSR1_TR19_Msk                         /*!< Rising trigger event configuration bit of line 19 */

+#define EXTI_RTSR1_TR20_Pos        (20U)

+#define EXTI_RTSR1_TR20_Msk        (0x1UL << EXTI_RTSR1_TR20_Pos)              /*!< 0x00100000 */

+#define EXTI_RTSR1_TR20            EXTI_RTSR1_TR20_Msk                         /*!< Rising trigger event configuration bit of line 20 */

+#define EXTI_RTSR1_TR21_Pos        (21U)

+#define EXTI_RTSR1_TR21_Msk        (0x1UL << EXTI_RTSR1_TR21_Pos)              /*!< 0x00200000 */

+#define EXTI_RTSR1_TR21            EXTI_RTSR1_TR21_Msk                         /*!< Rising trigger event configuration bit of line 21 */

+

+/******************  Bit definition for EXTI_FTSR1 register  *******************/

+#define EXTI_FTSR1_TR_Pos          (0U)

+#define EXTI_FTSR1_TR_Msk          (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)           /*!< 0x003FFFFF */

+#define EXTI_FTSR1_TR              EXTI_FTSR1_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR1_TR0_Pos         (0U)

+#define EXTI_FTSR1_TR0_Msk         (0x1UL << EXTI_FTSR1_TR0_Pos)               /*!< 0x00000001 */

+#define EXTI_FTSR1_TR0             EXTI_FTSR1_TR0_Msk                          /*!< Falling trigger event configuration bit of line 0 */

+#define EXTI_FTSR1_TR1_Pos         (1U)

+#define EXTI_FTSR1_TR1_Msk         (0x1UL << EXTI_FTSR1_TR1_Pos)               /*!< 0x00000002 */

+#define EXTI_FTSR1_TR1             EXTI_FTSR1_TR1_Msk                          /*!< Falling trigger event configuration bit of line 1 */

+#define EXTI_FTSR1_TR2_Pos         (2U)

+#define EXTI_FTSR1_TR2_Msk         (0x1UL << EXTI_FTSR1_TR2_Pos)               /*!< 0x00000004 */

+#define EXTI_FTSR1_TR2             EXTI_FTSR1_TR2_Msk                          /*!< Falling trigger event configuration bit of line 2 */

+#define EXTI_FTSR1_TR3_Pos         (3U)

+#define EXTI_FTSR1_TR3_Msk         (0x1UL << EXTI_FTSR1_TR3_Pos)               /*!< 0x00000008 */

+#define EXTI_FTSR1_TR3             EXTI_FTSR1_TR3_Msk                          /*!< Falling trigger event configuration bit of line 3 */

+#define EXTI_FTSR1_TR4_Pos         (4U)

+#define EXTI_FTSR1_TR4_Msk         (0x1UL << EXTI_FTSR1_TR4_Pos)               /*!< 0x00000010 */

+#define EXTI_FTSR1_TR4             EXTI_FTSR1_TR4_Msk                          /*!< Falling trigger event configuration bit of line 4 */

+#define EXTI_FTSR1_TR5_Pos         (5U)

+#define EXTI_FTSR1_TR5_Msk         (0x1UL << EXTI_FTSR1_TR5_Pos)               /*!< 0x00000020 */

+#define EXTI_FTSR1_TR5             EXTI_FTSR1_TR5_Msk                          /*!< Falling trigger event configuration bit of line 5 */

+#define EXTI_FTSR1_TR6_Pos         (6U)

+#define EXTI_FTSR1_TR6_Msk         (0x1UL << EXTI_FTSR1_TR6_Pos)               /*!< 0x00000040 */

+#define EXTI_FTSR1_TR6             EXTI_FTSR1_TR6_Msk                          /*!< Falling trigger event configuration bit of line 6 */

+#define EXTI_FTSR1_TR7_Pos         (7U)

+#define EXTI_FTSR1_TR7_Msk         (0x1UL << EXTI_FTSR1_TR7_Pos)               /*!< 0x00000080 */

+#define EXTI_FTSR1_TR7             EXTI_FTSR1_TR7_Msk                          /*!< Falling trigger event configuration bit of line 7 */

+#define EXTI_FTSR1_TR8_Pos         (8U)

+#define EXTI_FTSR1_TR8_Msk         (0x1UL << EXTI_FTSR1_TR8_Pos)               /*!< 0x00000100 */

+#define EXTI_FTSR1_TR8             EXTI_FTSR1_TR8_Msk                          /*!< Falling trigger event configuration bit of line 8 */

+#define EXTI_FTSR1_TR9_Pos         (9U)

+#define EXTI_FTSR1_TR9_Msk         (0x1UL << EXTI_FTSR1_TR9_Pos)               /*!< 0x00000200 */

+#define EXTI_FTSR1_TR9             EXTI_FTSR1_TR9_Msk                          /*!< Falling trigger event configuration bit of line 9 */

+#define EXTI_FTSR1_TR10_Pos        (10U)

+#define EXTI_FTSR1_TR10_Msk        (0x1UL << EXTI_FTSR1_TR10_Pos)              /*!< 0x00000400 */

+#define EXTI_FTSR1_TR10            EXTI_FTSR1_TR10_Msk                         /*!< Falling trigger event configuration bit of line 10 */

+#define EXTI_FTSR1_TR11_Pos        (11U)

+#define EXTI_FTSR1_TR11_Msk        (0x1UL << EXTI_FTSR1_TR11_Pos)              /*!< 0x00000800 */

+#define EXTI_FTSR1_TR11            EXTI_FTSR1_TR11_Msk                         /*!< Falling trigger event configuration bit of line 11 */

+#define EXTI_FTSR1_TR12_Pos        (12U)

+#define EXTI_FTSR1_TR12_Msk        (0x1UL << EXTI_FTSR1_TR12_Pos)              /*!< 0x00001000 */

+#define EXTI_FTSR1_TR12            EXTI_FTSR1_TR12_Msk                         /*!< Falling trigger event configuration bit of line 12 */

+#define EXTI_FTSR1_TR13_Pos        (13U)

+#define EXTI_FTSR1_TR13_Msk        (0x1UL << EXTI_FTSR1_TR13_Pos)              /*!< 0x00002000 */

+#define EXTI_FTSR1_TR13            EXTI_FTSR1_TR13_Msk                         /*!< Falling trigger event configuration bit of line 13 */

+#define EXTI_FTSR1_TR14_Pos        (14U)

+#define EXTI_FTSR1_TR14_Msk        (0x1UL << EXTI_FTSR1_TR14_Pos)              /*!< 0x00004000 */

+#define EXTI_FTSR1_TR14            EXTI_FTSR1_TR14_Msk                         /*!< Falling trigger event configuration bit of line 14 */

+#define EXTI_FTSR1_TR15_Pos        (15U)

+#define EXTI_FTSR1_TR15_Msk        (0x1UL << EXTI_FTSR1_TR15_Pos)              /*!< 0x00008000 */

+#define EXTI_FTSR1_TR15            EXTI_FTSR1_TR15_Msk                         /*!< Falling trigger event configuration bit of line 15 */

+#define EXTI_FTSR1_TR16_Pos        (16U)

+#define EXTI_FTSR1_TR16_Msk        (0x1UL << EXTI_FTSR1_TR16_Pos)              /*!< 0x00010000 */

+#define EXTI_FTSR1_TR16            EXTI_FTSR1_TR16_Msk                         /*!< Falling trigger event configuration bit of line 16 */

+#define EXTI_FTSR1_TR17_Pos        (17U)

+#define EXTI_FTSR1_TR17_Msk        (0x1UL << EXTI_FTSR1_TR17_Pos)              /*!< 0x00020000 */

+#define EXTI_FTSR1_TR17            EXTI_FTSR1_TR17_Msk                         /*!< Falling trigger event configuration bit of line 17 */

+#define EXTI_FTSR1_TR18_Pos        (18U)

+#define EXTI_FTSR1_TR18_Msk        (0x1UL << EXTI_FTSR1_TR18_Pos)              /*!< 0x00040000 */

+#define EXTI_FTSR1_TR18            EXTI_FTSR1_TR18_Msk                         /*!< Falling trigger event configuration bit of line 18 */

+#define EXTI_FTSR1_TR19_Pos        (19U)

+#define EXTI_FTSR1_TR19_Msk        (0x1UL << EXTI_FTSR1_TR19_Pos)              /*!< 0x00080000 */

+#define EXTI_FTSR1_TR19            EXTI_FTSR1_TR19_Msk                         /*!< Falling trigger event configuration bit of line 19 */

+#define EXTI_FTSR1_TR20_Pos        (20U)

+#define EXTI_FTSR1_TR20_Msk        (0x1UL << EXTI_FTSR1_TR20_Pos)              /*!< 0x00100000 */

+#define EXTI_FTSR1_TR20            EXTI_FTSR1_TR20_Msk                         /*!< Falling trigger event configuration bit of line 20 */

+#define EXTI_FTSR1_TR21_Pos        (21U)

+#define EXTI_FTSR1_TR21_Msk        (0x1UL << EXTI_FTSR1_TR21_Pos)              /*!< 0x00200000 */

+#define EXTI_FTSR1_TR21            EXTI_FTSR1_TR21_Msk                         /*!< Falling trigger event configuration bit of line 21 */

+

+/******************  Bit definition for EXTI_SWIER1 register  ******************/

+#define EXTI_SWIER1_SWIER0_Pos     (0U)

+#define EXTI_SWIER1_SWIER0_Msk     (0x1UL << EXTI_SWIER1_SWIER0_Pos)           /*!< 0x00000001 */

+#define EXTI_SWIER1_SWIER0         EXTI_SWIER1_SWIER0_Msk                      /*!< Software Interrupt on line 0 */

+#define EXTI_SWIER1_SWIER1_Pos     (1U)

+#define EXTI_SWIER1_SWIER1_Msk     (0x1UL << EXTI_SWIER1_SWIER1_Pos)           /*!< 0x00000002 */

+#define EXTI_SWIER1_SWIER1         EXTI_SWIER1_SWIER1_Msk                      /*!< Software Interrupt on line 1 */

+#define EXTI_SWIER1_SWIER2_Pos     (2U)

+#define EXTI_SWIER1_SWIER2_Msk     (0x1UL << EXTI_SWIER1_SWIER2_Pos)           /*!< 0x00000004 */

+#define EXTI_SWIER1_SWIER2         EXTI_SWIER1_SWIER2_Msk                      /*!< Software Interrupt on line 2 */

+#define EXTI_SWIER1_SWIER3_Pos     (3U)

+#define EXTI_SWIER1_SWIER3_Msk     (0x1UL << EXTI_SWIER1_SWIER3_Pos)           /*!< 0x00000008 */

+#define EXTI_SWIER1_SWIER3         EXTI_SWIER1_SWIER3_Msk                      /*!< Software Interrupt on line 3 */

+#define EXTI_SWIER1_SWIER4_Pos     (4U)

+#define EXTI_SWIER1_SWIER4_Msk     (0x1UL << EXTI_SWIER1_SWIER4_Pos)           /*!< 0x00000010 */

+#define EXTI_SWIER1_SWIER4         EXTI_SWIER1_SWIER4_Msk                      /*!< Software Interrupt on line 4 */

+#define EXTI_SWIER1_SWIER5_Pos     (5U)

+#define EXTI_SWIER1_SWIER5_Msk     (0x1UL << EXTI_SWIER1_SWIER5_Pos)           /*!< 0x00000020 */

+#define EXTI_SWIER1_SWIER5         EXTI_SWIER1_SWIER5_Msk                      /*!< Software Interrupt on line 5 */

+#define EXTI_SWIER1_SWIER6_Pos     (6U)

+#define EXTI_SWIER1_SWIER6_Msk     (0x1UL << EXTI_SWIER1_SWIER6_Pos)           /*!< 0x00000040 */

+#define EXTI_SWIER1_SWIER6         EXTI_SWIER1_SWIER6_Msk                      /*!< Software Interrupt on line 6 */

+#define EXTI_SWIER1_SWIER7_Pos     (7U)

+#define EXTI_SWIER1_SWIER7_Msk     (0x1UL << EXTI_SWIER1_SWIER7_Pos)           /*!< 0x00000080 */

+#define EXTI_SWIER1_SWIER7         EXTI_SWIER1_SWIER7_Msk                      /*!< Software Interrupt on line 7 */

+#define EXTI_SWIER1_SWIER8_Pos     (8U)

+#define EXTI_SWIER1_SWIER8_Msk     (0x1UL << EXTI_SWIER1_SWIER8_Pos)           /*!< 0x00000100 */

+#define EXTI_SWIER1_SWIER8         EXTI_SWIER1_SWIER8_Msk                      /*!< Software Interrupt on line 8 */

+#define EXTI_SWIER1_SWIER9_Pos     (9U)

+#define EXTI_SWIER1_SWIER9_Msk     (0x1UL << EXTI_SWIER1_SWIER9_Pos)           /*!< 0x00000200 */

+#define EXTI_SWIER1_SWIER9         EXTI_SWIER1_SWIER9_Msk                      /*!< Software Interrupt on line 9 */

+#define EXTI_SWIER1_SWIER10_Pos    (10U)

+#define EXTI_SWIER1_SWIER10_Msk    (0x1UL << EXTI_SWIER1_SWIER10_Pos)          /*!< 0x00000400 */

+#define EXTI_SWIER1_SWIER10        EXTI_SWIER1_SWIER10_Msk                     /*!< Software Interrupt on line 10 */

+#define EXTI_SWIER1_SWIER11_Pos    (11U)

+#define EXTI_SWIER1_SWIER11_Msk    (0x1UL << EXTI_SWIER1_SWIER11_Pos)          /*!< 0x00000800 */

+#define EXTI_SWIER1_SWIER11        EXTI_SWIER1_SWIER11_Msk                     /*!< Software Interrupt on line 11 */

+#define EXTI_SWIER1_SWIER12_Pos    (12U)

+#define EXTI_SWIER1_SWIER12_Msk    (0x1UL << EXTI_SWIER1_SWIER12_Pos)          /*!< 0x00001000 */

+#define EXTI_SWIER1_SWIER12        EXTI_SWIER1_SWIER12_Msk                     /*!< Software Interrupt on line 12 */

+#define EXTI_SWIER1_SWIER13_Pos    (13U)

+#define EXTI_SWIER1_SWIER13_Msk    (0x1UL << EXTI_SWIER1_SWIER13_Pos)          /*!< 0x00002000 */

+#define EXTI_SWIER1_SWIER13        EXTI_SWIER1_SWIER13_Msk                     /*!< Software Interrupt on line 13 */

+#define EXTI_SWIER1_SWIER14_Pos    (14U)

+#define EXTI_SWIER1_SWIER14_Msk    (0x1UL << EXTI_SWIER1_SWIER14_Pos)          /*!< 0x00004000 */

+#define EXTI_SWIER1_SWIER14        EXTI_SWIER1_SWIER14_Msk                     /*!< Software Interrupt on line 14 */

+#define EXTI_SWIER1_SWIER15_Pos    (15U)

+#define EXTI_SWIER1_SWIER15_Msk    (0x1UL << EXTI_SWIER1_SWIER15_Pos)          /*!< 0x00008000 */

+#define EXTI_SWIER1_SWIER15        EXTI_SWIER1_SWIER15_Msk                     /*!< Software Interrupt on line 15 */

+#define EXTI_SWIER1_SWIER16_Pos    (16U)

+#define EXTI_SWIER1_SWIER16_Msk    (0x1UL << EXTI_SWIER1_SWIER16_Pos)          /*!< 0x00010000 */

+#define EXTI_SWIER1_SWIER16        EXTI_SWIER1_SWIER16_Msk                     /*!< Software Interrupt on line 16 */

+#define EXTI_SWIER1_SWIER17_Pos    (17U)

+#define EXTI_SWIER1_SWIER17_Msk    (0x1UL << EXTI_SWIER1_SWIER17_Pos)          /*!< 0x00020000 */

+#define EXTI_SWIER1_SWIER17        EXTI_SWIER1_SWIER17_Msk                     /*!< Software Interrupt on line 17 */

+#define EXTI_SWIER1_SWIER18_Pos    (18U)

+#define EXTI_SWIER1_SWIER18_Msk    (0x1UL << EXTI_SWIER1_SWIER18_Pos)          /*!< 0x00040000 */

+#define EXTI_SWIER1_SWIER18        EXTI_SWIER1_SWIER18_Msk                     /*!< Software Interrupt on line 18 */

+#define EXTI_SWIER1_SWIER19_Pos    (19U)

+#define EXTI_SWIER1_SWIER19_Msk    (0x1UL << EXTI_SWIER1_SWIER19_Pos)          /*!< 0x00080000 */

+#define EXTI_SWIER1_SWIER19        EXTI_SWIER1_SWIER19_Msk                     /*!< Software Interrupt on line 19 */

+#define EXTI_SWIER1_SWIER20_Pos    (20U)

+#define EXTI_SWIER1_SWIER20_Msk    (0x1UL << EXTI_SWIER1_SWIER20_Pos)          /*!< 0x00100000 */

+#define EXTI_SWIER1_SWIER20        EXTI_SWIER1_SWIER20_Msk                     /*!< Software Interrupt on line 20 */

+#define EXTI_SWIER1_SWIER21_Pos    (21U)

+#define EXTI_SWIER1_SWIER21_Msk    (0x1UL << EXTI_SWIER1_SWIER21_Pos)          /*!< 0x00200000 */

+#define EXTI_SWIER1_SWIER21        EXTI_SWIER1_SWIER21_Msk                     /*!< Software Interrupt on line 21 */

+

+/******************  Bit definition for EXTI_D3PMR1 register  ******************/

+#define EXTI_D3PMR1_MR0_Pos        (0U)

+#define EXTI_D3PMR1_MR0_Msk        (0x1UL << EXTI_D3PMR1_MR0_Pos)              /*!< 0x00000001 */

+#define EXTI_D3PMR1_MR0            EXTI_D3PMR1_MR0_Msk                         /*!< Pending Mask Event for line 0  */

+#define EXTI_D3PMR1_MR1_Pos        (1U)

+#define EXTI_D3PMR1_MR1_Msk        (0x1UL << EXTI_D3PMR1_MR1_Pos)              /*!< 0x00000002 */

+#define EXTI_D3PMR1_MR1            EXTI_D3PMR1_MR1_Msk                         /*!< Pending Mask Event for line 1  */

+#define EXTI_D3PMR1_MR2_Pos        (2U)

+#define EXTI_D3PMR1_MR2_Msk        (0x1UL << EXTI_D3PMR1_MR2_Pos)              /*!< 0x00000004 */

+#define EXTI_D3PMR1_MR2            EXTI_D3PMR1_MR2_Msk                         /*!< Pending Mask Event for line 2  */

+#define EXTI_D3PMR1_MR3_Pos        (3U)

+#define EXTI_D3PMR1_MR3_Msk        (0x1UL << EXTI_D3PMR1_MR3_Pos)              /*!< 0x00000008 */

+#define EXTI_D3PMR1_MR3            EXTI_D3PMR1_MR3_Msk                         /*!< Pending Mask Event for line 3  */

+#define EXTI_D3PMR1_MR4_Pos        (4U)

+#define EXTI_D3PMR1_MR4_Msk        (0x1UL << EXTI_D3PMR1_MR4_Pos)              /*!< 0x00000010 */

+#define EXTI_D3PMR1_MR4            EXTI_D3PMR1_MR4_Msk                         /*!< Pending Mask Event for line 4  */

+#define EXTI_D3PMR1_MR5_Pos        (5U)

+#define EXTI_D3PMR1_MR5_Msk        (0x1UL << EXTI_D3PMR1_MR5_Pos)              /*!< 0x00000020 */

+#define EXTI_D3PMR1_MR5            EXTI_D3PMR1_MR5_Msk                         /*!< Pending Mask Event for line 5  */

+#define EXTI_D3PMR1_MR6_Pos        (6U)

+#define EXTI_D3PMR1_MR6_Msk        (0x1UL << EXTI_D3PMR1_MR6_Pos)              /*!< 0x00000040 */

+#define EXTI_D3PMR1_MR6            EXTI_D3PMR1_MR6_Msk                         /*!< Pending Mask Event for line 6  */

+#define EXTI_D3PMR1_MR7_Pos        (7U)

+#define EXTI_D3PMR1_MR7_Msk        (0x1UL << EXTI_D3PMR1_MR7_Pos)              /*!< 0x00000080 */

+#define EXTI_D3PMR1_MR7            EXTI_D3PMR1_MR7_Msk                         /*!< Pending Mask Event for line 7  */

+#define EXTI_D3PMR1_MR8_Pos        (8U)

+#define EXTI_D3PMR1_MR8_Msk        (0x1UL << EXTI_D3PMR1_MR8_Pos)              /*!< 0x00000100 */

+#define EXTI_D3PMR1_MR8            EXTI_D3PMR1_MR8_Msk                         /*!< Pending Mask Event for line 8  */

+#define EXTI_D3PMR1_MR9_Pos        (9U)

+#define EXTI_D3PMR1_MR9_Msk        (0x1UL << EXTI_D3PMR1_MR9_Pos)              /*!< 0x00000200 */

+#define EXTI_D3PMR1_MR9            EXTI_D3PMR1_MR9_Msk                         /*!< Pending Mask Event for line 9  */

+#define EXTI_D3PMR1_MR10_Pos       (10U)

+#define EXTI_D3PMR1_MR10_Msk       (0x1UL << EXTI_D3PMR1_MR10_Pos)             /*!< 0x00000400 */

+#define EXTI_D3PMR1_MR10           EXTI_D3PMR1_MR10_Msk                        /*!< Pending Mask Event for line 10 */

+#define EXTI_D3PMR1_MR11_Pos       (11U)

+#define EXTI_D3PMR1_MR11_Msk       (0x1UL << EXTI_D3PMR1_MR11_Pos)             /*!< 0x00000800 */

+#define EXTI_D3PMR1_MR11           EXTI_D3PMR1_MR11_Msk                        /*!< Pending Mask Event for line 11 */

+#define EXTI_D3PMR1_MR12_Pos       (12U)

+#define EXTI_D3PMR1_MR12_Msk       (0x1UL << EXTI_D3PMR1_MR12_Pos)             /*!< 0x00001000 */

+#define EXTI_D3PMR1_MR12           EXTI_D3PMR1_MR12_Msk                        /*!< Pending Mask Event for line 12 */

+#define EXTI_D3PMR1_MR13_Pos       (13U)

+#define EXTI_D3PMR1_MR13_Msk       (0x1UL << EXTI_D3PMR1_MR13_Pos)             /*!< 0x00002000 */

+#define EXTI_D3PMR1_MR13           EXTI_D3PMR1_MR13_Msk                        /*!< Pending Mask Event for line 13 */

+#define EXTI_D3PMR1_MR14_Pos       (14U)

+#define EXTI_D3PMR1_MR14_Msk       (0x1UL << EXTI_D3PMR1_MR14_Pos)             /*!< 0x00004000 */

+#define EXTI_D3PMR1_MR14           EXTI_D3PMR1_MR14_Msk                        /*!< Pending Mask Event for line 14 */

+#define EXTI_D3PMR1_MR15_Pos       (15U)

+#define EXTI_D3PMR1_MR15_Msk       (0x1UL << EXTI_D3PMR1_MR15_Pos)             /*!< 0x00008000 */

+#define EXTI_D3PMR1_MR15           EXTI_D3PMR1_MR15_Msk                        /*!< Pending Mask Event for line 15 */

+#define EXTI_D3PMR1_MR19_Pos       (19U)

+#define EXTI_D3PMR1_MR19_Msk       (0x1UL << EXTI_D3PMR1_MR19_Pos)             /*!< 0x00080000 */

+#define EXTI_D3PMR1_MR19           EXTI_D3PMR1_MR19_Msk                        /*!< Pending Mask Event for line 19 */

+#define EXTI_D3PMR1_MR20_Pos       (20U)

+#define EXTI_D3PMR1_MR20_Msk       (0x1UL << EXTI_D3PMR1_MR20_Pos)             /*!< 0x00100000 */

+#define EXTI_D3PMR1_MR20           EXTI_D3PMR1_MR20_Msk                        /*!< Pending Mask Event for line 20 */

+#define EXTI_D3PMR1_MR21_Pos       (21U)

+#define EXTI_D3PMR1_MR21_Msk       (0x1UL << EXTI_D3PMR1_MR21_Pos)             /*!< 0x00200000 */

+#define EXTI_D3PMR1_MR21           EXTI_D3PMR1_MR21_Msk                        /*!< Pending Mask Event for line 21 */

+#define EXTI_D3PMR1_MR25_Pos       (24U)

+#define EXTI_D3PMR1_MR25_Msk       (0x1UL << EXTI_D3PMR1_MR25_Pos)             /*!< 0x01000000 */

+#define EXTI_D3PMR1_MR25           EXTI_D3PMR1_MR25_Msk                        /*!< Pending Mask Event for line 25 */

+

+/*******************  Bit definition for EXTI_D3PCR1L register  ****************/

+#define EXTI_D3PCR1L_PCS0_Pos       (0U)

+#define EXTI_D3PCR1L_PCS0_Msk       (0x3UL << EXTI_D3PCR1L_PCS0_Pos)           /*!< 0x00000003 */

+#define EXTI_D3PCR1L_PCS0           EXTI_D3PCR1L_PCS0_Msk                      /*!< D3 Pending request clear input signal selection on line 0 */

+#define EXTI_D3PCR1L_PCS1_Pos       (2U)

+#define EXTI_D3PCR1L_PCS1_Msk       (0x3UL << EXTI_D3PCR1L_PCS1_Pos)           /*!< 0x000000C0 */

+#define EXTI_D3PCR1L_PCS1           EXTI_D3PCR1L_PCS1_Msk                      /*!< D3 Pending request clear input signal selection on line 1 */

+#define EXTI_D3PCR1L_PCS2_Pos       (4U)

+#define EXTI_D3PCR1L_PCS2_Msk       (0x3UL << EXTI_D3PCR1L_PCS2_Pos)           /*!< 0x00000030 */

+#define EXTI_D3PCR1L_PCS2           EXTI_D3PCR1L_PCS2_Msk                      /*!< D3 Pending request clear input signal selection on line 2 */

+#define EXTI_D3PCR1L_PCS3_Pos       (6U)

+#define EXTI_D3PCR1L_PCS3_Msk       (0x3UL << EXTI_D3PCR1L_PCS3_Pos)           /*!< 0x000000C0 */

+#define EXTI_D3PCR1L_PCS3           EXTI_D3PCR1L_PCS3_Msk                      /*!< D3 Pending request clear input signal selection on line 3 */

+#define EXTI_D3PCR1L_PCS4_Pos       (8U)

+#define EXTI_D3PCR1L_PCS4_Msk       (0x3UL << EXTI_D3PCR1L_PCS4_Pos)           /*!< 0x00000300 */

+#define EXTI_D3PCR1L_PCS4           EXTI_D3PCR1L_PCS4_Msk                      /*!< D3 Pending request clear input signal selection on line 4 */

+#define EXTI_D3PCR1L_PCS5_Pos       (10U)

+#define EXTI_D3PCR1L_PCS5_Msk       (0x3UL << EXTI_D3PCR1L_PCS5_Pos)           /*!< 0x00000C00 */

+#define EXTI_D3PCR1L_PCS5           EXTI_D3PCR1L_PCS5_Msk                      /*!< D3 Pending request clear input signal selection on line 5 */

+#define EXTI_D3PCR1L_PCS6_Pos       (12U)

+#define EXTI_D3PCR1L_PCS6_Msk       (0x3UL << EXTI_D3PCR1L_PCS6_Pos)           /*!< 0x00003000 */

+#define EXTI_D3PCR1L_PCS6           EXTI_D3PCR1L_PCS6_Msk                      /*!< D3 Pending request clear input signal selection on line 6 */

+#define EXTI_D3PCR1L_PCS7_Pos       (14U)

+#define EXTI_D3PCR1L_PCS7_Msk       (0x3UL << EXTI_D3PCR1L_PCS7_Pos)           /*!< 0x0000C000 */

+#define EXTI_D3PCR1L_PCS7           EXTI_D3PCR1L_PCS7_Msk                      /*!< D3 Pending request clear input signal selection on line 7 */

+#define EXTI_D3PCR1L_PCS8_Pos       (16U)

+#define EXTI_D3PCR1L_PCS8_Msk       (0x3UL << EXTI_D3PCR1L_PCS8_Pos)           /*!< 0x00030000 */

+#define EXTI_D3PCR1L_PCS8           EXTI_D3PCR1L_PCS8_Msk                      /*!< D3 Pending request clear input signal selection on line 8 */

+#define EXTI_D3PCR1L_PCS9_Pos       (18U)

+#define EXTI_D3PCR1L_PCS9_Msk       (0x3UL << EXTI_D3PCR1L_PCS9_Pos)           /*!< 0x000C0000 */

+#define EXTI_D3PCR1L_PCS9           EXTI_D3PCR1L_PCS9_Msk                      /*!< D3 Pending request clear input signal selection on line 9 */

+#define EXTI_D3PCR1L_PCS10_Pos      (20U)

+#define EXTI_D3PCR1L_PCS10_Msk      (0x3UL << EXTI_D3PCR1L_PCS10_Pos)          /*!< 0x00300000 */

+#define EXTI_D3PCR1L_PCS10          EXTI_D3PCR1L_PCS10_Msk                     /*!< D3 Pending request clear input signal selection on line 10*/

+#define EXTI_D3PCR1L_PCS11_Pos      (22U)

+#define EXTI_D3PCR1L_PCS11_Msk      (0x3UL << EXTI_D3PCR1L_PCS11_Pos)          /*!< 0x00C00000 */

+#define EXTI_D3PCR1L_PCS11          EXTI_D3PCR1L_PCS11_Msk                     /*!< D3 Pending request clear input signal selection on line 11*/

+#define EXTI_D3PCR1L_PCS12_Pos      (24U)

+#define EXTI_D3PCR1L_PCS12_Msk      (0x3UL << EXTI_D3PCR1L_PCS12_Pos)          /*!< 0x03000000 */

+#define EXTI_D3PCR1L_PCS12          EXTI_D3PCR1L_PCS12_Msk                     /*!< D3 Pending request clear input signal selection on line 12*/

+#define EXTI_D3PCR1L_PCS13_Pos      (26U)

+#define EXTI_D3PCR1L_PCS13_Msk      (0x3UL << EXTI_D3PCR1L_PCS13_Pos)          /*!< 0x0C000000 */

+#define EXTI_D3PCR1L_PCS13          EXTI_D3PCR1L_PCS13_Msk                     /*!< D3 Pending request clear input signal selection on line 13*/

+#define EXTI_D3PCR1L_PCS14_Pos      (28U)

+#define EXTI_D3PCR1L_PCS14_Msk      (0x3UL << EXTI_D3PCR1L_PCS14_Pos)          /*!< 0x30000000 */

+#define EXTI_D3PCR1L_PCS14          EXTI_D3PCR1L_PCS14_Msk                     /*!< D3 Pending request clear input signal selection on line 14*/

+#define EXTI_D3PCR1L_PCS15_Pos      (30U)

+#define EXTI_D3PCR1L_PCS15_Msk      (0x3UL << EXTI_D3PCR1L_PCS15_Pos)          /*!< 0xC0000000 */

+#define EXTI_D3PCR1L_PCS15          EXTI_D3PCR1L_PCS15_Msk                     /*!< D3 Pending request clear input signal selection on line 15*/

+

+/*******************  Bit definition for EXTI_D3PCR1H register  ****************/

+#define EXTI_D3PCR1H_PCS19_Pos       (6U)

+#define EXTI_D3PCR1H_PCS19_Msk       (0x3UL << EXTI_D3PCR1H_PCS19_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR1H_PCS19           EXTI_D3PCR1H_PCS19_Msk                    /*!< D3 Pending request clear input signal selection on line 19 */

+#define EXTI_D3PCR1H_PCS20_Pos       (8U)

+#define EXTI_D3PCR1H_PCS20_Msk       (0x3UL << EXTI_D3PCR1H_PCS20_Pos)         /*!< 0x00000300 */

+#define EXTI_D3PCR1H_PCS20           EXTI_D3PCR1H_PCS20_Msk                    /*!< D3 Pending request clear input signal selection on line 20 */

+#define EXTI_D3PCR1H_PCS21_Pos       (10U)

+#define EXTI_D3PCR1H_PCS21_Msk       (0x3UL << EXTI_D3PCR1H_PCS21_Pos)         /*!< 0x00000C00 */

+#define EXTI_D3PCR1H_PCS21           EXTI_D3PCR1H_PCS21_Msk                    /*!< D3 Pending request clear input signal selection on line 21 */

+#define EXTI_D3PCR1H_PCS25_Pos       (18U)

+#define EXTI_D3PCR1H_PCS25_Msk       (0x3UL << EXTI_D3PCR1H_PCS25_Pos)         /*!< 0x000C0000 */

+#define EXTI_D3PCR1H_PCS25           EXTI_D3PCR1H_PCS25_Msk                    /*!< D3 Pending request clear input signal selection on line 25 */

+

+/******************  Bit definition for EXTI_RTSR2 register  *******************/

+#define EXTI_RTSR2_TR_Pos          (17U)

+#define EXTI_RTSR2_TR_Msk          (0x5UL << EXTI_RTSR2_TR_Pos)                /*!< 0x000A0000 */

+#define EXTI_RTSR2_TR              EXTI_RTSR2_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR2_TR49_Pos        (17U)

+#define EXTI_RTSR2_TR49_Msk        (0x1UL << EXTI_RTSR2_TR49_Pos)              /*!< 0x00020000 */

+#define EXTI_RTSR2_TR49            EXTI_RTSR2_TR49_Msk                         /*!< Rising trigger event configuration bit of line 49 */

+#define EXTI_RTSR2_TR51_Pos        (19U)

+#define EXTI_RTSR2_TR51_Msk        (0x1UL << EXTI_RTSR2_TR51_Pos)              /*!< 0x00080000 */

+#define EXTI_RTSR2_TR51            EXTI_RTSR2_TR51_Msk                         /*!< Rising trigger event configuration bit of line 51 */

+

+/******************  Bit definition for EXTI_FTSR2 register  *******************/

+#define EXTI_FTSR2_TR_Pos          (17U)

+#define EXTI_FTSR2_TR_Msk          (0x5UL << EXTI_FTSR2_TR_Pos)                /*!< 0x000A0000 */

+#define EXTI_FTSR2_TR              EXTI_FTSR2_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR2_TR49_Pos        (17U)

+#define EXTI_FTSR2_TR49_Msk        (0x1UL << EXTI_FTSR2_TR49_Pos)              /*!< 0x00020000 */

+#define EXTI_FTSR2_TR49            EXTI_FTSR2_TR49_Msk                         /*!< Falling trigger event configuration bit of line 49 */

+#define EXTI_FTSR2_TR51_Pos        (19U)

+#define EXTI_FTSR2_TR51_Msk        (0x1UL << EXTI_FTSR2_TR51_Pos)              /*!< 0x00080000 */

+#define EXTI_FTSR2_TR51            EXTI_FTSR2_TR51_Msk                         /*!< Falling trigger event configuration bit of line 51 */

+

+/******************  Bit definition for EXTI_SWIER2 register  ******************/

+#define EXTI_SWIER2_SWIER49_Pos    (17U)

+#define EXTI_SWIER2_SWIER49_Msk    (0x1UL << EXTI_SWIER2_SWIER49_Pos)          /*!< 0x00020000 */

+#define EXTI_SWIER2_SWIER49        EXTI_SWIER2_SWIER49_Msk                     /*!< Software Interrupt on line 49 */

+#define EXTI_SWIER2_SWIER51_Pos    (19U)

+#define EXTI_SWIER2_SWIER51_Msk    (0x1UL << EXTI_SWIER2_SWIER51_Pos)          /*!< 0x00080000 */

+#define EXTI_SWIER2_SWIER51        EXTI_SWIER2_SWIER51_Msk                     /*!< Software Interrupt on line 51 */

+

+/******************  Bit definition for EXTI_D3PMR2 register  ******************/

+#define EXTI_D3PMR2_MR34_Pos       (2U)

+#define EXTI_D3PMR2_MR34_Msk       (0x1UL << EXTI_D3PMR2_MR34_Pos)             /*!< 0x00000004 */

+#define EXTI_D3PMR2_MR34           EXTI_D3PMR2_MR34_Msk                        /*!< Pending Mask Event for line 34  */

+#define EXTI_D3PMR2_MR35_Pos       (3U)

+#define EXTI_D3PMR2_MR35_Msk       (0x1UL << EXTI_D3PMR2_MR35_Pos)             /*!< 0x00000008 */

+#define EXTI_D3PMR2_MR35           EXTI_D3PMR2_MR35_Msk                        /*!< Pending Mask Event for line 35  */

+#define EXTI_D3PMR2_MR41_Pos       (9U)

+#define EXTI_D3PMR2_MR41_Msk       (0x1UL << EXTI_D3PMR2_MR41_Pos)             /*!< 0x00000200 */

+#define EXTI_D3PMR2_MR41           EXTI_D3PMR2_MR41_Msk                        /*!< Pending Mask Event for line 41  */

+#define EXTI_D3PMR2_MR48_Pos       (16U)

+#define EXTI_D3PMR2_MR48_Msk       (0x1UL << EXTI_D3PMR2_MR48_Pos)             /*!< 0x00010000 */

+#define EXTI_D3PMR2_MR48           EXTI_D3PMR2_MR48_Msk                        /*!< Pending Mask Event for line 48  */

+#define EXTI_D3PMR2_MR49_Pos       (17U)

+#define EXTI_D3PMR2_MR49_Msk       (0x1UL << EXTI_D3PMR2_MR49_Pos)             /*!< 0x00020000 */

+#define EXTI_D3PMR2_MR49           EXTI_D3PMR2_MR49_Msk                        /*!< Pending Mask Event for line 49  */

+#define EXTI_D3PMR2_MR50_Pos       (18U)

+#define EXTI_D3PMR2_MR50_Msk       (0x1UL << EXTI_D3PMR2_MR50_Pos)             /*!< 0x00040000 */

+#define EXTI_D3PMR2_MR50           EXTI_D3PMR2_MR50_Msk                        /*!< Pending Mask Event for line 50  */

+#define EXTI_D3PMR2_MR51_Pos       (19U)

+#define EXTI_D3PMR2_MR51_Msk       (0x1UL << EXTI_D3PMR2_MR51_Pos)             /*!< 0x00080000 */

+#define EXTI_D3PMR2_MR51           EXTI_D3PMR2_MR51_Msk                        /*!< Pending Mask Event for line 51  */

+#define EXTI_D3PMR2_MR52_Pos       (20U)

+#define EXTI_D3PMR2_MR52_Msk       (0x1UL << EXTI_D3PMR2_MR52_Pos)             /*!< 0x00100000 */

+#define EXTI_D3PMR2_MR52           EXTI_D3PMR2_MR52_Msk                        /*!< Pending Mask Event for line 52  */

+#define EXTI_D3PMR2_MR53_Pos       (21U)

+#define EXTI_D3PMR2_MR53_Msk       (0x1UL << EXTI_D3PMR2_MR53_Pos)             /*!< 0x00200000 */

+#define EXTI_D3PMR2_MR53           EXTI_D3PMR2_MR53_Msk                        /*!< Pending Mask Event for line 53  */

+/*******************  Bit definition for EXTI_D3PCR2L register  ****************/

+#define EXTI_D3PCR2L_PCS34_Pos       (4U)

+#define EXTI_D3PCR2L_PCS34_Msk       (0x3UL << EXTI_D3PCR2L_PCS34_Pos)         /*!< 0x00000030 */

+#define EXTI_D3PCR2L_PCS34           EXTI_D3PCR2L_PCS34_Msk                    /*!< D3 Pending request clear input signal selection on line 34 */

+#define EXTI_D3PCR2L_PCS35_Pos       (6U)

+#define EXTI_D3PCR2L_PCS35_Msk       (0x3UL << EXTI_D3PCR2L_PCS35_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR2L_PCS35           EXTI_D3PCR2L_PCS35_Msk                    /*!< D3 Pending request clear input signal selection on line 35 */

+#define EXTI_D3PCR2L_PCS41_Pos       (18U)

+#define EXTI_D3PCR2L_PCS41_Msk       (0x3UL << EXTI_D3PCR2L_PCS41_Pos)         /*!< 0x000C0000 */

+#define EXTI_D3PCR2L_PCS41           EXTI_D3PCR2L_PCS41_Msk                    /*!< D3 Pending request clear input signal selection on line 41 */

+

+

+/*******************  Bit definition for EXTI_D3PCR2H register  ****************/

+#define EXTI_D3PCR2H_PCS48_Pos       (0U)

+#define EXTI_D3PCR2H_PCS48_Msk       (0x3UL << EXTI_D3PCR2H_PCS48_Pos)         /*!< 0x00000003 */

+#define EXTI_D3PCR2H_PCS48           EXTI_D3PCR2H_PCS48_Msk                    /*!< D3 Pending request clear input signal selection on line 48 */

+#define EXTI_D3PCR2H_PCS49_Pos       (2U)

+#define EXTI_D3PCR2H_PCS49_Msk       (0x3UL << EXTI_D3PCR2H_PCS49_Pos)         /*!< 0x0000000C */

+#define EXTI_D3PCR2H_PCS49           EXTI_D3PCR2H_PCS49_Msk                    /*!< D3 Pending request clear input signal selection on line 49 */

+#define EXTI_D3PCR2H_PCS50_Pos       (4U)

+#define EXTI_D3PCR2H_PCS50_Msk       (0x3UL << EXTI_D3PCR2H_PCS50_Pos)         /*!< 0x00000030 */

+#define EXTI_D3PCR2H_PCS50           EXTI_D3PCR2H_PCS50_Msk                    /*!< D3 Pending request clear input signal selection on line 50 */

+#define EXTI_D3PCR2H_PCS51_Pos       (6U)

+#define EXTI_D3PCR2H_PCS51_Msk       (0x3UL << EXTI_D3PCR2H_PCS51_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR2H_PCS51           EXTI_D3PCR2H_PCS51_Msk                    /*!< D3 Pending request clear input signal selection on line 51 */

+#define EXTI_D3PCR2H_PCS52_Pos       (8U)

+#define EXTI_D3PCR2H_PCS52_Msk       (0x3UL << EXTI_D3PCR2H_PCS52_Pos)         /*!< 0x00000300 */

+#define EXTI_D3PCR2H_PCS52           EXTI_D3PCR2H_PCS52_Msk                    /*!< D3 Pending request clear input signal selection on line 52 */

+#define EXTI_D3PCR2H_PCS53_Pos       (10U)

+#define EXTI_D3PCR2H_PCS53_Msk       (0x3UL << EXTI_D3PCR2H_PCS53_Pos)         /*!< 0x00000C00 */

+#define EXTI_D3PCR2H_PCS53           EXTI_D3PCR2H_PCS53_Msk                    /*!< D3 Pending request clear input signal selection on line 53 */

+/******************  Bit definition for EXTI_RTSR3 register  *******************/

+#define EXTI_RTSR3_TR_Pos          (18U)

+#define EXTI_RTSR3_TR_Msk          (0x1DUL << EXTI_RTSR3_TR_Pos)               /*!< 0x00740000 */

+#define EXTI_RTSR3_TR              EXTI_RTSR3_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR3_TR82_Pos        (18U)

+#define EXTI_RTSR3_TR82_Msk        (0x1UL << EXTI_RTSR3_TR82_Pos)              /*!< 0x00040000 */

+#define EXTI_RTSR3_TR82            EXTI_RTSR3_TR82_Msk                         /*!< Rising trigger event configuration bit of line 82 */

+#define EXTI_RTSR3_TR84_Pos        (20U)

+#define EXTI_RTSR3_TR84_Msk        (0x1UL << EXTI_RTSR3_TR84_Pos)              /*!< 0x00100000 */

+#define EXTI_RTSR3_TR84            EXTI_RTSR3_TR84_Msk                         /*!< Rising trigger event configuration bit of line 84 */

+#define EXTI_RTSR3_TR85_Pos        (21U)

+#define EXTI_RTSR3_TR85_Msk        (0x1UL << EXTI_RTSR3_TR85_Pos)              /*!< 0x00200000 */

+#define EXTI_RTSR3_TR85            EXTI_RTSR3_TR85_Msk                         /*!< Rising trigger event configuration bit of line 85 */

+#define EXTI_RTSR3_TR86_Pos        (22U)

+#define EXTI_RTSR3_TR86_Msk        (0x1UL << EXTI_RTSR3_TR86_Pos)              /*!< 0x00400000 */

+#define EXTI_RTSR3_TR86            EXTI_RTSR3_TR86_Msk                         /*!< Rising trigger event configuration bit of line 86 */

+

+/******************  Bit definition for EXTI_FTSR3 register  *******************/

+#define EXTI_FTSR3_TR_Pos          (18U)

+#define EXTI_FTSR3_TR_Msk          (0x1DUL << EXTI_FTSR3_TR_Pos)               /*!< 0x00740000 */

+#define EXTI_FTSR3_TR              EXTI_FTSR3_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR3_TR82_Pos        (18U)

+#define EXTI_FTSR3_TR82_Msk        (0x1UL << EXTI_FTSR3_TR82_Pos)              /*!< 0x00040000 */

+#define EXTI_FTSR3_TR82            EXTI_FTSR3_TR82_Msk                         /*!< Falling trigger event configuration bit of line 82 */

+#define EXTI_FTSR3_TR84_Pos        (20U)

+#define EXTI_FTSR3_TR84_Msk        (0x1UL << EXTI_FTSR3_TR84_Pos)              /*!< 0x00100000 */

+#define EXTI_FTSR3_TR84            EXTI_FTSR3_TR84_Msk                         /*!< Falling trigger event configuration bit of line 84 */

+#define EXTI_FTSR3_TR85_Pos        (21U)

+#define EXTI_FTSR3_TR85_Msk        (0x1UL << EXTI_FTSR3_TR85_Pos)              /*!< 0x00200000 */

+#define EXTI_FTSR3_TR85            EXTI_FTSR3_TR85_Msk                         /*!< Falling trigger event configuration bit of line 85 */

+#define EXTI_FTSR3_TR86_Pos        (22U)

+#define EXTI_FTSR3_TR86_Msk        (0x1UL << EXTI_FTSR3_TR86_Pos)              /*!< 0x00400000 */

+#define EXTI_FTSR3_TR86            EXTI_FTSR3_TR86_Msk                         /*!< Falling trigger event configuration bit of line 86 */

+

+/******************  Bit definition for EXTI_SWIER3 register  ******************/

+#define EXTI_SWIER3_SWI_Pos        (18U)

+#define EXTI_SWIER3_SWI_Msk        (0x1DUL << EXTI_SWIER3_SWI_Pos)             /*!< 0x00740000 */

+#define EXTI_SWIER3_SWI            EXTI_SWIER3_SWI_Msk                         /*!< Software Interrupt event bit */

+#define EXTI_SWIER3_SWIER82_Pos    (18U)

+#define EXTI_SWIER3_SWIER82_Msk    (0x1UL << EXTI_SWIER3_SWIER82_Pos)          /*!< 0x00040000 */

+#define EXTI_SWIER3_SWIER82        EXTI_SWIER3_SWIER82_Msk                     /*!< Software Interrupt on line 82 */

+#define EXTI_SWIER3_SWIER84_Pos    (20U)

+#define EXTI_SWIER3_SWIER84_Msk    (0x1UL << EXTI_SWIER3_SWIER84_Pos)          /*!< 0x00100000 */

+#define EXTI_SWIER3_SWIER84        EXTI_SWIER3_SWIER84_Msk                     /*!< Software Interrupt on line 84 */

+#define EXTI_SWIER3_SWIER85_Pos    (21U)

+#define EXTI_SWIER3_SWIER85_Msk    (0x1UL << EXTI_SWIER3_SWIER85_Pos)          /*!< 0x00200000 */

+#define EXTI_SWIER3_SWIER85        EXTI_SWIER3_SWIER85_Msk                     /*!< Software Interrupt on line 85 */

+#define EXTI_SWIER3_SWIER86_Pos    (22U)

+#define EXTI_SWIER3_SWIER86_Msk    (0x1UL << EXTI_SWIER3_SWIER86_Pos)          /*!< 0x00400000 */

+#define EXTI_SWIER3_SWIER86        EXTI_SWIER3_SWIER86_Msk                     /*!< Software Interrupt on line 86 */

+

+/*******************  Bit definition for EXTI_IMR1 register  *******************/

+#define EXTI_IMR1_IM_Pos           (0U)

+#define EXTI_IMR1_IM_Msk           (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)          /*!< 0xFFFFFFFF */

+#define EXTI_IMR1_IM               EXTI_IMR1_IM_Msk                            /*!< Interrupt Mask */

+#define EXTI_IMR1_IM0_Pos          (0U)

+#define EXTI_IMR1_IM0_Msk          (0x1UL << EXTI_IMR1_IM0_Pos)                /*!< 0x00000001 */

+#define EXTI_IMR1_IM0              EXTI_IMR1_IM0_Msk                           /*!< Interrupt Mask on line 0 */

+#define EXTI_IMR1_IM1_Pos          (1U)

+#define EXTI_IMR1_IM1_Msk          (0x1UL << EXTI_IMR1_IM1_Pos)                /*!< 0x00000002 */

+#define EXTI_IMR1_IM1              EXTI_IMR1_IM1_Msk                           /*!< Interrupt Mask on line 1 */

+#define EXTI_IMR1_IM2_Pos          (2U)

+#define EXTI_IMR1_IM2_Msk          (0x1UL << EXTI_IMR1_IM2_Pos)                /*!< 0x00000004 */

+#define EXTI_IMR1_IM2              EXTI_IMR1_IM2_Msk                           /*!< Interrupt Mask on line 2 */

+#define EXTI_IMR1_IM3_Pos          (3U)

+#define EXTI_IMR1_IM3_Msk          (0x1UL << EXTI_IMR1_IM3_Pos)                /*!< 0x00000008 */

+#define EXTI_IMR1_IM3              EXTI_IMR1_IM3_Msk                           /*!< Interrupt Mask on line 3 */

+#define EXTI_IMR1_IM4_Pos          (4U)

+#define EXTI_IMR1_IM4_Msk          (0x1UL << EXTI_IMR1_IM4_Pos)                /*!< 0x00000010 */

+#define EXTI_IMR1_IM4              EXTI_IMR1_IM4_Msk                           /*!< Interrupt Mask on line 4 */

+#define EXTI_IMR1_IM5_Pos          (5U)

+#define EXTI_IMR1_IM5_Msk          (0x1UL << EXTI_IMR1_IM5_Pos)                /*!< 0x00000020 */

+#define EXTI_IMR1_IM5              EXTI_IMR1_IM5_Msk                           /*!< Interrupt Mask on line 5 */

+#define EXTI_IMR1_IM6_Pos          (6U)

+#define EXTI_IMR1_IM6_Msk          (0x1UL << EXTI_IMR1_IM6_Pos)                /*!< 0x00000040 */

+#define EXTI_IMR1_IM6              EXTI_IMR1_IM6_Msk                           /*!< Interrupt Mask on line 6 */

+#define EXTI_IMR1_IM7_Pos          (7U)

+#define EXTI_IMR1_IM7_Msk          (0x1UL << EXTI_IMR1_IM7_Pos)                /*!< 0x00000080 */

+#define EXTI_IMR1_IM7              EXTI_IMR1_IM7_Msk                           /*!< Interrupt Mask on line 7 */

+#define EXTI_IMR1_IM8_Pos          (8U)

+#define EXTI_IMR1_IM8_Msk          (0x1UL << EXTI_IMR1_IM8_Pos)                /*!< 0x00000100 */

+#define EXTI_IMR1_IM8              EXTI_IMR1_IM8_Msk                           /*!< Interrupt Mask on line 8 */

+#define EXTI_IMR1_IM9_Pos          (9U)

+#define EXTI_IMR1_IM9_Msk          (0x1UL << EXTI_IMR1_IM9_Pos)                /*!< 0x00000200 */

+#define EXTI_IMR1_IM9              EXTI_IMR1_IM9_Msk                           /*!< Interrupt Mask on line 9 */

+#define EXTI_IMR1_IM10_Pos         (10U)

+#define EXTI_IMR1_IM10_Msk         (0x1UL << EXTI_IMR1_IM10_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR1_IM10             EXTI_IMR1_IM10_Msk                          /*!< Interrupt Mask on line 10 */

+#define EXTI_IMR1_IM11_Pos         (11U)

+#define EXTI_IMR1_IM11_Msk         (0x1UL << EXTI_IMR1_IM11_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR1_IM11             EXTI_IMR1_IM11_Msk                          /*!< Interrupt Mask on line 11 */

+#define EXTI_IMR1_IM12_Pos         (12U)

+#define EXTI_IMR1_IM12_Msk         (0x1UL << EXTI_IMR1_IM12_Pos)               /*!< 0x00001000 */

+#define EXTI_IMR1_IM12             EXTI_IMR1_IM12_Msk                          /*!< Interrupt Mask on line 12 */

+#define EXTI_IMR1_IM13_Pos         (13U)

+#define EXTI_IMR1_IM13_Msk         (0x1UL << EXTI_IMR1_IM13_Pos)               /*!< 0x00002000 */

+#define EXTI_IMR1_IM13             EXTI_IMR1_IM13_Msk                          /*!< Interrupt Mask on line 13 */

+#define EXTI_IMR1_IM14_Pos         (14U)

+#define EXTI_IMR1_IM14_Msk         (0x1UL << EXTI_IMR1_IM14_Pos)               /*!< 0x00004000 */

+#define EXTI_IMR1_IM14             EXTI_IMR1_IM14_Msk                          /*!< Interrupt Mask on line 14 */

+#define EXTI_IMR1_IM15_Pos         (15U)

+#define EXTI_IMR1_IM15_Msk         (0x1UL << EXTI_IMR1_IM15_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR1_IM15             EXTI_IMR1_IM15_Msk                          /*!< Interrupt Mask on line 15 */

+#define EXTI_IMR1_IM16_Pos         (16U)

+#define EXTI_IMR1_IM16_Msk         (0x1UL << EXTI_IMR1_IM16_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR1_IM16             EXTI_IMR1_IM16_Msk                          /*!< Interrupt Mask on line 16 */

+#define EXTI_IMR1_IM17_Pos         (17U)

+#define EXTI_IMR1_IM17_Msk         (0x1UL << EXTI_IMR1_IM17_Pos)               /*!< 0x00020000 */

+#define EXTI_IMR1_IM17             EXTI_IMR1_IM17_Msk                          /*!< Interrupt Mask on line 17 */

+#define EXTI_IMR1_IM18_Pos         (18U)

+#define EXTI_IMR1_IM18_Msk         (0x1UL << EXTI_IMR1_IM18_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR1_IM18             EXTI_IMR1_IM18_Msk                          /*!< Interrupt Mask on line 18 */

+#define EXTI_IMR1_IM19_Pos         (19U)

+#define EXTI_IMR1_IM19_Msk         (0x1UL << EXTI_IMR1_IM19_Pos)               /*!< 0x00080000 */

+#define EXTI_IMR1_IM19             EXTI_IMR1_IM19_Msk                          /*!< Interrupt Mask on line 19 */

+#define EXTI_IMR1_IM20_Pos         (20U)

+#define EXTI_IMR1_IM20_Msk         (0x1UL << EXTI_IMR1_IM20_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR1_IM20             EXTI_IMR1_IM20_Msk                          /*!< Interrupt Mask on line 20 */

+#define EXTI_IMR1_IM21_Pos         (21U)

+#define EXTI_IMR1_IM21_Msk         (0x1UL << EXTI_IMR1_IM21_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR1_IM21             EXTI_IMR1_IM21_Msk                          /*!< Interrupt Mask on line 21 */

+#define EXTI_IMR1_IM22_Pos         (22U)

+#define EXTI_IMR1_IM22_Msk         (0x1UL << EXTI_IMR1_IM22_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR1_IM22             EXTI_IMR1_IM22_Msk                          /*!< Interrupt Mask on line 22 */

+#define EXTI_IMR1_IM23_Pos         (23U)

+#define EXTI_IMR1_IM23_Msk         (0x1UL << EXTI_IMR1_IM23_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR1_IM23             EXTI_IMR1_IM23_Msk                          /*!< Interrupt Mask on line 23 */

+#define EXTI_IMR1_IM24_Pos         (24U)

+#define EXTI_IMR1_IM24_Msk         (0x1UL << EXTI_IMR1_IM24_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR1_IM24             EXTI_IMR1_IM24_Msk                          /*!< Interrupt Mask on line 24 */

+#define EXTI_IMR1_IM25_Pos         (25U)

+#define EXTI_IMR1_IM25_Msk         (0x1UL << EXTI_IMR1_IM25_Pos)               /*!< 0x02000000 */

+#define EXTI_IMR1_IM25             EXTI_IMR1_IM25_Msk                          /*!< Interrupt Mask on line 25 */

+#define EXTI_IMR1_IM26_Pos         (26U)

+#define EXTI_IMR1_IM26_Msk         (0x1UL << EXTI_IMR1_IM26_Pos)               /*!< 0x04000000 */

+#define EXTI_IMR1_IM26             EXTI_IMR1_IM26_Msk                          /*!< Interrupt Mask on line 26 */

+#define EXTI_IMR1_IM27_Pos         (27U)

+#define EXTI_IMR1_IM27_Msk         (0x1UL << EXTI_IMR1_IM27_Pos)               /*!< 0x08000000 */

+#define EXTI_IMR1_IM27             EXTI_IMR1_IM27_Msk                          /*!< Interrupt Mask on line 27 */

+#define EXTI_IMR1_IM28_Pos         (28U)

+#define EXTI_IMR1_IM28_Msk         (0x1UL << EXTI_IMR1_IM28_Pos)               /*!< 0x10000000 */

+#define EXTI_IMR1_IM28             EXTI_IMR1_IM28_Msk                          /*!< Interrupt Mask on line 28 */

+#define EXTI_IMR1_IM29_Pos         (29U)

+#define EXTI_IMR1_IM29_Msk         (0x1UL << EXTI_IMR1_IM29_Pos)               /*!< 0x20000000 */

+#define EXTI_IMR1_IM29             EXTI_IMR1_IM29_Msk                          /*!< Interrupt Mask on line 29 */

+#define EXTI_IMR1_IM30_Pos         (30U)

+#define EXTI_IMR1_IM30_Msk         (0x1UL << EXTI_IMR1_IM30_Pos)               /*!< 0x40000000 */

+#define EXTI_IMR1_IM30             EXTI_IMR1_IM30_Msk                          /*!< Interrupt Mask on line 30 */

+#define EXTI_IMR1_IM31_Pos         (31U)

+#define EXTI_IMR1_IM31_Msk         (0x1UL << EXTI_IMR1_IM31_Pos)               /*!< 0x80000000 */

+#define EXTI_IMR1_IM31             EXTI_IMR1_IM31_Msk                          /*!< Interrupt Mask on line 31 */

+

+/*******************  Bit definition for EXTI_EMR1 register  *******************/

+#define EXTI_EMR1_EM_Pos           (0U)

+#define EXTI_EMR1_EM_Msk           (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)          /*!< 0xFFFFFFFF */

+#define EXTI_EMR1_EM               EXTI_EMR1_EM_Msk                            /*!< Event Mask */

+#define EXTI_EMR1_EM0_Pos          (0U)

+#define EXTI_EMR1_EM0_Msk          (0x1UL << EXTI_EMR1_EM0_Pos)                /*!< 0x00000001 */

+#define EXTI_EMR1_EM0              EXTI_EMR1_EM0_Msk                           /*!< Event Mask on line 0 */

+#define EXTI_EMR1_EM1_Pos          (1U)

+#define EXTI_EMR1_EM1_Msk          (0x1UL << EXTI_EMR1_EM1_Pos)                /*!< 0x00000002 */

+#define EXTI_EMR1_EM1              EXTI_EMR1_EM1_Msk                           /*!< Event Mask on line 1 */

+#define EXTI_EMR1_EM2_Pos          (2U)

+#define EXTI_EMR1_EM2_Msk          (0x1UL << EXTI_EMR1_EM2_Pos)                /*!< 0x00000004 */

+#define EXTI_EMR1_EM2              EXTI_EMR1_EM2_Msk                           /*!< Event Mask on line 2 */

+#define EXTI_EMR1_EM3_Pos          (3U)

+#define EXTI_EMR1_EM3_Msk          (0x1UL << EXTI_EMR1_EM3_Pos)                /*!< 0x00000008 */

+#define EXTI_EMR1_EM3              EXTI_EMR1_EM3_Msk                           /*!< Event Mask on line 3 */

+#define EXTI_EMR1_EM4_Pos          (4U)

+#define EXTI_EMR1_EM4_Msk          (0x1UL << EXTI_EMR1_EM4_Pos)                /*!< 0x00000010 */

+#define EXTI_EMR1_EM4              EXTI_EMR1_EM4_Msk                           /*!< Event Mask on line 4 */

+#define EXTI_EMR1_EM5_Pos          (5U)

+#define EXTI_EMR1_EM5_Msk          (0x1UL << EXTI_EMR1_EM5_Pos)                /*!< 0x00000020 */

+#define EXTI_EMR1_EM5              EXTI_EMR1_EM5_Msk                           /*!< Event Mask on line 5 */

+#define EXTI_EMR1_EM6_Pos          (6U)

+#define EXTI_EMR1_EM6_Msk          (0x1UL << EXTI_EMR1_EM6_Pos)                /*!< 0x00000040 */

+#define EXTI_EMR1_EM6              EXTI_EMR1_EM6_Msk                           /*!< Event Mask on line 6 */

+#define EXTI_EMR1_EM7_Pos          (7U)

+#define EXTI_EMR1_EM7_Msk          (0x1UL << EXTI_EMR1_EM7_Pos)                /*!< 0x00000080 */

+#define EXTI_EMR1_EM7              EXTI_EMR1_EM7_Msk                           /*!< Event Mask on line 7 */

+#define EXTI_EMR1_EM8_Pos          (8U)

+#define EXTI_EMR1_EM8_Msk          (0x1UL << EXTI_EMR1_EM8_Pos)                /*!< 0x00000100 */

+#define EXTI_EMR1_EM8              EXTI_EMR1_EM8_Msk                           /*!< Event Mask on line 8 */

+#define EXTI_EMR1_EM9_Pos          (9U)

+#define EXTI_EMR1_EM9_Msk          (0x1UL << EXTI_EMR1_EM9_Pos)                /*!< 0x00000200 */

+#define EXTI_EMR1_EM9              EXTI_EMR1_EM9_Msk                           /*!< Event Mask on line 9 */

+#define EXTI_EMR1_EM10_Pos         (10U)

+#define EXTI_EMR1_EM10_Msk         (0x1UL << EXTI_EMR1_EM10_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR1_EM10             EXTI_EMR1_EM10_Msk                          /*!< Event Mask on line 10 */

+#define EXTI_EMR1_EM11_Pos         (11U)

+#define EXTI_EMR1_EM11_Msk         (0x1UL << EXTI_EMR1_EM11_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR1_EM11             EXTI_EMR1_EM11_Msk                          /*!< Event Mask on line 11 */

+#define EXTI_EMR1_EM12_Pos         (12U)

+#define EXTI_EMR1_EM12_Msk         (0x1UL << EXTI_EMR1_EM12_Pos)               /*!< 0x00001000 */

+#define EXTI_EMR1_EM12             EXTI_EMR1_EM12_Msk                          /*!< Event Mask on line 12 */

+#define EXTI_EMR1_EM13_Pos         (13U)

+#define EXTI_EMR1_EM13_Msk         (0x1UL << EXTI_EMR1_EM13_Pos)               /*!< 0x00002000 */

+#define EXTI_EMR1_EM13             EXTI_EMR1_EM13_Msk                          /*!< Event Mask on line 13 */

+#define EXTI_EMR1_EM14_Pos         (14U)

+#define EXTI_EMR1_EM14_Msk         (0x1UL << EXTI_EMR1_EM14_Pos)               /*!< 0x00004000 */

+#define EXTI_EMR1_EM14             EXTI_EMR1_EM14_Msk                          /*!< Event Mask on line 14 */

+#define EXTI_EMR1_EM15_Pos         (15U)

+#define EXTI_EMR1_EM15_Msk         (0x1UL << EXTI_EMR1_EM15_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR1_EM15             EXTI_EMR1_EM15_Msk                          /*!< Event Mask on line 15 */

+#define EXTI_EMR1_EM16_Pos         (16U)

+#define EXTI_EMR1_EM16_Msk         (0x1UL << EXTI_EMR1_EM16_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR1_EM16             EXTI_EMR1_EM16_Msk                          /*!< Event Mask on line 16 */

+#define EXTI_EMR1_EM17_Pos         (17U)

+#define EXTI_EMR1_EM17_Msk         (0x1UL << EXTI_EMR1_EM17_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR1_EM17             EXTI_EMR1_EM17_Msk                          /*!< Event Mask on line 17 */

+#define EXTI_EMR1_EM18_Pos         (18U)

+#define EXTI_EMR1_EM18_Msk         (0x1UL << EXTI_EMR1_EM18_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR1_EM18             EXTI_EMR1_EM18_Msk                          /*!< Event Mask on line 18 */

+#define EXTI_EMR1_EM20_Pos         (20U)

+#define EXTI_EMR1_EM20_Msk         (0x1UL << EXTI_EMR1_EM20_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR1_EM20             EXTI_EMR1_EM20_Msk                          /*!< Event Mask on line 20 */

+#define EXTI_EMR1_EM21_Pos         (21U)

+#define EXTI_EMR1_EM21_Msk         (0x1UL << EXTI_EMR1_EM21_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR1_EM21             EXTI_EMR1_EM21_Msk                          /*!< Event Mask on line 21 */

+#define EXTI_EMR1_EM22_Pos         (22U)

+#define EXTI_EMR1_EM22_Msk         (0x1UL << EXTI_EMR1_EM22_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR1_EM22             EXTI_EMR1_EM22_Msk                          /*!< Event Mask on line 22 */

+#define EXTI_EMR1_EM23_Pos         (23U)

+#define EXTI_EMR1_EM23_Msk         (0x1UL << EXTI_EMR1_EM23_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR1_EM23             EXTI_EMR1_EM23_Msk                          /*!< Event Mask on line 23 */

+#define EXTI_EMR1_EM24_Pos         (24U)

+#define EXTI_EMR1_EM24_Msk         (0x1UL << EXTI_EMR1_EM24_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR1_EM24             EXTI_EMR1_EM24_Msk                          /*!< Event Mask on line 24 */

+#define EXTI_EMR1_EM25_Pos         (25U)

+#define EXTI_EMR1_EM25_Msk         (0x1UL << EXTI_EMR1_EM25_Pos)               /*!< 0x02000000 */

+#define EXTI_EMR1_EM25             EXTI_EMR1_EM25_Msk                          /*!< Event Mask on line 25 */

+#define EXTI_EMR1_EM26_Pos         (26U)

+#define EXTI_EMR1_EM26_Msk         (0x1UL << EXTI_EMR1_EM26_Pos)               /*!< 0x04000000 */

+#define EXTI_EMR1_EM26             EXTI_EMR1_EM26_Msk                          /*!< Event Mask on line 26 */

+#define EXTI_EMR1_EM27_Pos         (27U)

+#define EXTI_EMR1_EM27_Msk         (0x1UL << EXTI_EMR1_EM27_Pos)               /*!< 0x08000000 */

+#define EXTI_EMR1_EM27             EXTI_EMR1_EM27_Msk                          /*!< Event Mask on line 27 */

+#define EXTI_EMR1_EM28_Pos         (28U)

+#define EXTI_EMR1_EM28_Msk         (0x1UL << EXTI_EMR1_EM28_Pos)               /*!< 0x10000000 */

+#define EXTI_EMR1_EM28             EXTI_EMR1_EM28_Msk                          /*!< Event Mask on line 28 */

+#define EXTI_EMR1_EM29_Pos         (29U)

+#define EXTI_EMR1_EM29_Msk         (0x1UL << EXTI_EMR1_EM29_Pos)               /*!< 0x20000000 */

+#define EXTI_EMR1_EM29             EXTI_EMR1_EM29_Msk                          /*!< Event Mask on line 29 */

+#define EXTI_EMR1_EM30_Pos         (30U)

+#define EXTI_EMR1_EM30_Msk         (0x1UL << EXTI_EMR1_EM30_Pos)               /*!< 0x40000000 */

+#define EXTI_EMR1_EM30             EXTI_EMR1_EM30_Msk                          /*!< Event Mask on line 30 */

+#define EXTI_EMR1_EM31_Pos         (31U)

+#define EXTI_EMR1_EM31_Msk         (0x1UL << EXTI_EMR1_EM31_Pos)               /*!< 0x80000000 */

+#define EXTI_EMR1_EM31             EXTI_EMR1_EM31_Msk                          /*!< Event Mask on line 31 */

+

+/*******************  Bit definition for EXTI_PR1 register  ********************/

+#define EXTI_PR1_PR_Pos            (0U)

+#define EXTI_PR1_PR_Msk            (0x3FFFFFUL << EXTI_PR1_PR_Pos)             /*!< 0x003FFFFF */

+#define EXTI_PR1_PR                EXTI_PR1_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR1_PR0_Pos           (0U)

+#define EXTI_PR1_PR0_Msk           (0x1UL << EXTI_PR1_PR0_Pos)                 /*!< 0x00000001 */

+#define EXTI_PR1_PR0               EXTI_PR1_PR0_Msk                            /*!< Pending bit for line 0 */

+#define EXTI_PR1_PR1_Pos           (1U)

+#define EXTI_PR1_PR1_Msk           (0x1UL << EXTI_PR1_PR1_Pos)                 /*!< 0x00000002 */

+#define EXTI_PR1_PR1               EXTI_PR1_PR1_Msk                            /*!< Pending bit for line 1 */

+#define EXTI_PR1_PR2_Pos           (2U)

+#define EXTI_PR1_PR2_Msk           (0x1UL << EXTI_PR1_PR2_Pos)                 /*!< 0x00000004 */

+#define EXTI_PR1_PR2               EXTI_PR1_PR2_Msk                            /*!< Pending bit for line 2 */

+#define EXTI_PR1_PR3_Pos           (3U)

+#define EXTI_PR1_PR3_Msk           (0x1UL << EXTI_PR1_PR3_Pos)                 /*!< 0x00000008 */

+#define EXTI_PR1_PR3               EXTI_PR1_PR3_Msk                            /*!< Pending bit for line 3 */

+#define EXTI_PR1_PR4_Pos           (4U)

+#define EXTI_PR1_PR4_Msk           (0x1UL << EXTI_PR1_PR4_Pos)                 /*!< 0x00000010 */

+#define EXTI_PR1_PR4               EXTI_PR1_PR4_Msk                            /*!< Pending bit for line 4 */

+#define EXTI_PR1_PR5_Pos           (5U)

+#define EXTI_PR1_PR5_Msk           (0x1UL << EXTI_PR1_PR5_Pos)                 /*!< 0x00000020 */

+#define EXTI_PR1_PR5               EXTI_PR1_PR5_Msk                            /*!< Pending bit for line 5 */

+#define EXTI_PR1_PR6_Pos           (6U)

+#define EXTI_PR1_PR6_Msk           (0x1UL << EXTI_PR1_PR6_Pos)                 /*!< 0x00000040 */

+#define EXTI_PR1_PR6               EXTI_PR1_PR6_Msk                            /*!< Pending bit for line 6 */

+#define EXTI_PR1_PR7_Pos           (7U)

+#define EXTI_PR1_PR7_Msk           (0x1UL << EXTI_PR1_PR7_Pos)                 /*!< 0x00000080 */

+#define EXTI_PR1_PR7               EXTI_PR1_PR7_Msk                            /*!< Pending bit for line 7 */

+#define EXTI_PR1_PR8_Pos           (8U)

+#define EXTI_PR1_PR8_Msk           (0x1UL << EXTI_PR1_PR8_Pos)                 /*!< 0x00000100 */

+#define EXTI_PR1_PR8               EXTI_PR1_PR8_Msk                            /*!< Pending bit for line 8 */

+#define EXTI_PR1_PR9_Pos           (9U)

+#define EXTI_PR1_PR9_Msk           (0x1UL << EXTI_PR1_PR9_Pos)                 /*!< 0x00000200 */

+#define EXTI_PR1_PR9               EXTI_PR1_PR9_Msk                            /*!< Pending bit for line 9 */

+#define EXTI_PR1_PR10_Pos          (10U)

+#define EXTI_PR1_PR10_Msk          (0x1UL << EXTI_PR1_PR10_Pos)                /*!< 0x00000400 */

+#define EXTI_PR1_PR10              EXTI_PR1_PR10_Msk                           /*!< Pending bit for line 10 */

+#define EXTI_PR1_PR11_Pos          (11U)

+#define EXTI_PR1_PR11_Msk          (0x1UL << EXTI_PR1_PR11_Pos)                /*!< 0x00000800 */

+#define EXTI_PR1_PR11              EXTI_PR1_PR11_Msk                           /*!< Pending bit for line 11 */

+#define EXTI_PR1_PR12_Pos          (12U)

+#define EXTI_PR1_PR12_Msk          (0x1UL << EXTI_PR1_PR12_Pos)                /*!< 0x00001000 */

+#define EXTI_PR1_PR12              EXTI_PR1_PR12_Msk                           /*!< Pending bit for line 12 */

+#define EXTI_PR1_PR13_Pos          (13U)

+#define EXTI_PR1_PR13_Msk          (0x1UL << EXTI_PR1_PR13_Pos)                /*!< 0x00002000 */

+#define EXTI_PR1_PR13              EXTI_PR1_PR13_Msk                           /*!< Pending bit for line 13 */

+#define EXTI_PR1_PR14_Pos          (14U)

+#define EXTI_PR1_PR14_Msk          (0x1UL << EXTI_PR1_PR14_Pos)                /*!< 0x00004000 */

+#define EXTI_PR1_PR14              EXTI_PR1_PR14_Msk                           /*!< Pending bit for line 14 */

+#define EXTI_PR1_PR15_Pos          (15U)

+#define EXTI_PR1_PR15_Msk          (0x1UL << EXTI_PR1_PR15_Pos)                /*!< 0x00008000 */

+#define EXTI_PR1_PR15              EXTI_PR1_PR15_Msk                           /*!< Pending bit for line 15 */

+#define EXTI_PR1_PR16_Pos          (16U)

+#define EXTI_PR1_PR16_Msk          (0x1UL << EXTI_PR1_PR16_Pos)                /*!< 0x00010000 */

+#define EXTI_PR1_PR16              EXTI_PR1_PR16_Msk                           /*!< Pending bit for line 16 */

+#define EXTI_PR1_PR17_Pos          (17U)

+#define EXTI_PR1_PR17_Msk          (0x1UL << EXTI_PR1_PR17_Pos)                /*!< 0x00020000 */

+#define EXTI_PR1_PR17              EXTI_PR1_PR17_Msk                           /*!< Pending bit for line 17 */

+#define EXTI_PR1_PR18_Pos          (18U)

+#define EXTI_PR1_PR18_Msk          (0x1UL << EXTI_PR1_PR18_Pos)                /*!< 0x00040000 */

+#define EXTI_PR1_PR18              EXTI_PR1_PR18_Msk                           /*!< Pending bit for line 18 */

+#define EXTI_PR1_PR19_Pos          (19U)

+#define EXTI_PR1_PR19_Msk          (0x1UL << EXTI_PR1_PR19_Pos)                /*!< 0x00080000 */

+#define EXTI_PR1_PR19              EXTI_PR1_PR19_Msk                           /*!< Pending bit for line 19 */

+#define EXTI_PR1_PR20_Pos          (20U)

+#define EXTI_PR1_PR20_Msk          (0x1UL << EXTI_PR1_PR20_Pos)                /*!< 0x00100000 */

+#define EXTI_PR1_PR20              EXTI_PR1_PR20_Msk                           /*!< Pending bit for line 20 */

+#define EXTI_PR1_PR21_Pos          (21U)

+#define EXTI_PR1_PR21_Msk          (0x1UL << EXTI_PR1_PR21_Pos)                /*!< 0x00200000 */

+#define EXTI_PR1_PR21              EXTI_PR1_PR21_Msk                           /*!< Pending bit for line 21 */

+

+/*******************  Bit definition for EXTI_IMR2 register  *******************/

+#define EXTI_IMR2_IM_Pos           (0U)

+#define EXTI_IMR2_IM_Msk           (0xFFFFDFFFUL << EXTI_IMR2_IM_Pos)          /*!< 0xFFFFDFFF */

+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            /*!< Interrupt Mask */

+#define EXTI_IMR2_IM32_Pos         (0U)

+#define EXTI_IMR2_IM32_Msk         (0x1UL << EXTI_IMR2_IM32_Pos)               /*!< 0x00000001 */

+#define EXTI_IMR2_IM32             EXTI_IMR2_IM32_Msk                          /*!< Interrupt Mask on line 32 */

+#define EXTI_IMR2_IM33_Pos         (1U)

+#define EXTI_IMR2_IM33_Msk         (0x1UL << EXTI_IMR2_IM33_Pos)               /*!< 0x00000002 */

+#define EXTI_IMR2_IM33             EXTI_IMR2_IM33_Msk                          /*!< Interrupt Mask on line 33 */

+#define EXTI_IMR2_IM34_Pos         (2U)

+#define EXTI_IMR2_IM34_Msk         (0x1UL << EXTI_IMR2_IM34_Pos)               /*!< 0x00000004 */

+#define EXTI_IMR2_IM34             EXTI_IMR2_IM34_Msk                          /*!< Interrupt Mask on line 34 */

+#define EXTI_IMR2_IM35_Pos         (3U)

+#define EXTI_IMR2_IM35_Msk         (0x1UL << EXTI_IMR2_IM35_Pos)               /*!< 0x00000008 */

+#define EXTI_IMR2_IM35             EXTI_IMR2_IM35_Msk                          /*!< Interrupt Mask on line 35 */

+#define EXTI_IMR2_IM36_Pos         (4U)

+#define EXTI_IMR2_IM36_Msk         (0x1UL << EXTI_IMR2_IM36_Pos)               /*!< 0x00000010 */

+#define EXTI_IMR2_IM36             EXTI_IMR2_IM36_Msk                          /*!< Interrupt Mask on line 36 */

+#define EXTI_IMR2_IM37_Pos         (5U)

+#define EXTI_IMR2_IM37_Msk         (0x1UL << EXTI_IMR2_IM37_Pos)               /*!< 0x00000020 */

+#define EXTI_IMR2_IM37             EXTI_IMR2_IM37_Msk                          /*!< Interrupt Mask on line 37 */

+#define EXTI_IMR2_IM38_Pos         (6U)

+#define EXTI_IMR2_IM38_Msk         (0x1UL << EXTI_IMR2_IM38_Pos)               /*!< 0x00000040 */

+#define EXTI_IMR2_IM38             EXTI_IMR2_IM38_Msk                          /*!< Interrupt Mask on line 38 */

+#define EXTI_IMR2_IM39_Pos         (7U)

+#define EXTI_IMR2_IM39_Msk         (0x1UL << EXTI_IMR2_IM39_Pos)               /*!< 0x00000080 */

+#define EXTI_IMR2_IM39             EXTI_IMR2_IM39_Msk                          /*!< Interrupt Mask on line 39 */

+#define EXTI_IMR2_IM40_Pos         (8U)

+#define EXTI_IMR2_IM40_Msk         (0x1UL << EXTI_IMR2_IM40_Pos)               /*!< 0x00000100 */

+#define EXTI_IMR2_IM40             EXTI_IMR2_IM40_Msk                          /*!< Interrupt Mask on line 40 */

+#define EXTI_IMR2_IM41_Pos         (9U)

+#define EXTI_IMR2_IM41_Msk         (0x1UL << EXTI_IMR2_IM41_Pos)               /*!< 0x00000200 */

+#define EXTI_IMR2_IM41             EXTI_IMR2_IM41_Msk                          /*!< Interrupt Mask on line 41 */

+#define EXTI_IMR2_IM42_Pos         (10U)

+#define EXTI_IMR2_IM42_Msk         (0x1UL << EXTI_IMR2_IM42_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR2_IM42             EXTI_IMR2_IM42_Msk                          /*!< Interrupt Mask on line 42 */

+#define EXTI_IMR2_IM43_Pos         (11U)

+#define EXTI_IMR2_IM43_Msk         (0x1UL << EXTI_IMR2_IM43_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR2_IM43             EXTI_IMR2_IM43_Msk                          /*!< Interrupt Mask on line 43 */

+#define EXTI_IMR2_IM44_Pos         (12U)

+#define EXTI_IMR2_IM44_Msk         (0x1UL << EXTI_IMR2_IM44_Pos)               /*!< 0x00001000 */

+#define EXTI_IMR2_IM44             EXTI_IMR2_IM44_Msk                          /*!< Interrupt Mask on line 44 */

+#define EXTI_IMR2_IM46_Pos         (14U)

+#define EXTI_IMR2_IM46_Msk         (0x1UL << EXTI_IMR2_IM46_Pos)               /*!< 0x00004000 */

+#define EXTI_IMR2_IM46             EXTI_IMR2_IM46_Msk                          /*!< Interrupt Mask on line 46 */

+#define EXTI_IMR2_IM47_Pos         (15U)

+#define EXTI_IMR2_IM47_Msk         (0x1UL << EXTI_IMR2_IM47_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR2_IM47             EXTI_IMR2_IM47_Msk                          /*!< Interrupt Mask on line 47 */

+#define EXTI_IMR2_IM48_Pos         (16U)

+#define EXTI_IMR2_IM48_Msk         (0x1UL << EXTI_IMR2_IM48_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR2_IM48             EXTI_IMR2_IM48_Msk                          /*!< Interrupt Mask on line 48 */

+#define EXTI_IMR2_IM49_Pos         (17U)

+#define EXTI_IMR2_IM49_Msk         (0x1UL << EXTI_IMR2_IM49_Pos)               /*!< 0x00020000 */

+#define EXTI_IMR2_IM49             EXTI_IMR2_IM49_Msk                          /*!< Interrupt Mask on line 49 */

+#define EXTI_IMR2_IM50_Pos         (18U)

+#define EXTI_IMR2_IM50_Msk         (0x1UL << EXTI_IMR2_IM50_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR2_IM50             EXTI_IMR2_IM50_Msk                          /*!< Interrupt Mask on line 50 */

+#define EXTI_IMR2_IM51_Pos         (19U)

+#define EXTI_IMR2_IM51_Msk         (0x1UL << EXTI_IMR2_IM51_Pos)               /*!< 0x00080000 */

+#define EXTI_IMR2_IM51             EXTI_IMR2_IM51_Msk                          /*!< Interrupt Mask on line 51 */

+#define EXTI_IMR2_IM52_Pos         (20U)

+#define EXTI_IMR2_IM52_Msk         (0x1UL << EXTI_IMR2_IM52_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR2_IM52             EXTI_IMR2_IM52_Msk                          /*!< Interrupt Mask on line 52 */

+#define EXTI_IMR2_IM53_Pos         (21U)

+#define EXTI_IMR2_IM53_Msk         (0x1UL << EXTI_IMR2_IM53_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR2_IM53             EXTI_IMR2_IM53_Msk                          /*!< Interrupt Mask on line 53 */

+#define EXTI_IMR2_IM54_Pos         (22U)

+#define EXTI_IMR2_IM54_Msk         (0x1UL << EXTI_IMR2_IM54_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR2_IM54             EXTI_IMR2_IM54_Msk                          /*!< Interrupt Mask on line 54 */

+#define EXTI_IMR2_IM55_Pos         (23U)

+#define EXTI_IMR2_IM55_Msk         (0x1UL << EXTI_IMR2_IM55_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR2_IM55             EXTI_IMR2_IM55_Msk                          /*!< Interrupt Mask on line 55 */

+#define EXTI_IMR2_IM56_Pos         (24U)

+#define EXTI_IMR2_IM56_Msk         (0x1UL << EXTI_IMR2_IM56_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR2_IM56             EXTI_IMR2_IM56_Msk                          /*!< Interrupt Mask on line 56 */

+#define EXTI_IMR2_IM57_Pos         (25U)

+#define EXTI_IMR2_IM57_Msk         (0x1UL << EXTI_IMR2_IM57_Pos)               /*!< 0x02000000 */

+#define EXTI_IMR2_IM57             EXTI_IMR2_IM57_Msk                          /*!< Interrupt Mask on line 57 */

+#define EXTI_IMR2_IM58_Pos         (26U)

+#define EXTI_IMR2_IM58_Msk         (0x1UL << EXTI_IMR2_IM58_Pos)               /*!< 0x04000000 */

+#define EXTI_IMR2_IM58             EXTI_IMR2_IM58_Msk                          /*!< Interrupt Mask on line 58 */

+#define EXTI_IMR2_IM59_Pos         (27U)

+#define EXTI_IMR2_IM59_Msk         (0x1UL << EXTI_IMR2_IM59_Pos)               /*!< 0x08000000 */

+#define EXTI_IMR2_IM59             EXTI_IMR2_IM59_Msk                          /*!< Interrupt Mask on line 59 */

+#define EXTI_IMR2_IM60_Pos         (28U)

+#define EXTI_IMR2_IM60_Msk         (0x1UL << EXTI_IMR2_IM60_Pos)               /*!< 0x10000000 */

+#define EXTI_IMR2_IM60             EXTI_IMR2_IM60_Msk                          /*!< Interrupt Mask on line 60 */

+#define EXTI_IMR2_IM61_Pos         (29U)

+#define EXTI_IMR2_IM61_Msk         (0x1UL << EXTI_IMR2_IM61_Pos)               /*!< 0x20000000 */

+#define EXTI_IMR2_IM61             EXTI_IMR2_IM61_Msk                          /*!< Interrupt Mask on line 61 */

+#define EXTI_IMR2_IM62_Pos         (30U)

+#define EXTI_IMR2_IM62_Msk         (0x1UL << EXTI_IMR2_IM62_Pos)               /*!< 0x40000000 */

+#define EXTI_IMR2_IM62             EXTI_IMR2_IM62_Msk                          /*!< Interrupt Mask on line 62 */

+#define EXTI_IMR2_IM63_Pos         (31U)

+#define EXTI_IMR2_IM63_Msk         (0x1UL << EXTI_IMR2_IM63_Pos)               /*!< 0x80000000 */

+#define EXTI_IMR2_IM63             EXTI_IMR2_IM63_Msk                          /*!< Interrupt Mask on line 63 */

+

+/*******************  Bit definition for EXTI_EMR2 register  *******************/

+#define EXTI_EMR2_EM_Pos           (0U)

+#define EXTI_EMR2_EM_Msk           (0xFFFFDFFFUL << EXTI_EMR2_EM_Pos)          /*!< 0xFFFFDFFF */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            /*!< Event Mask */

+#define EXTI_EMR2_EM32_Pos         (0U)

+#define EXTI_EMR2_EM32_Msk         (0x1UL << EXTI_EMR2_EM32_Pos)               /*!< 0x00000001 */

+#define EXTI_EMR2_EM32             EXTI_EMR2_EM32_Msk                          /*!< Event Mask on line 32*/

+#define EXTI_EMR2_EM33_Pos         (1U)

+#define EXTI_EMR2_EM33_Msk         (0x1UL << EXTI_EMR2_EM33_Pos)               /*!< 0x00000002 */

+#define EXTI_EMR2_EM33             EXTI_EMR2_EM33_Msk                          /*!< Event Mask on line 33*/

+#define EXTI_EMR2_EM34_Pos         (2U)

+#define EXTI_EMR2_EM34_Msk         (0x1UL << EXTI_EMR2_EM34_Pos)               /*!< 0x00000004 */

+#define EXTI_EMR2_EM34             EXTI_EMR2_EM34_Msk                          /*!< Event Mask on line 34*/

+#define EXTI_EMR2_EM35_Pos         (3U)

+#define EXTI_EMR2_EM35_Msk         (0x1UL << EXTI_EMR2_EM35_Pos)               /*!< 0x00000008 */

+#define EXTI_EMR2_EM35             EXTI_EMR2_EM35_Msk                          /*!< Event Mask on line 35*/

+#define EXTI_EMR2_EM36_Pos         (4U)

+#define EXTI_EMR2_EM36_Msk         (0x1UL << EXTI_EMR2_EM36_Pos)               /*!< 0x00000010 */

+#define EXTI_EMR2_EM36             EXTI_EMR2_EM36_Msk                          /*!< Event Mask on line 36*/

+#define EXTI_EMR2_EM37_Pos         (5U)

+#define EXTI_EMR2_EM37_Msk         (0x1UL << EXTI_EMR2_EM37_Pos)               /*!< 0x00000020 */

+#define EXTI_EMR2_EM37             EXTI_EMR2_EM37_Msk                          /*!< Event Mask on line 37*/

+#define EXTI_EMR2_EM38_Pos         (6U)

+#define EXTI_EMR2_EM38_Msk         (0x1UL << EXTI_EMR2_EM38_Pos)               /*!< 0x00000040 */

+#define EXTI_EMR2_EM38             EXTI_EMR2_EM38_Msk                          /*!< Event Mask on line 38*/

+#define EXTI_EMR2_EM39_Pos         (7U)

+#define EXTI_EMR2_EM39_Msk         (0x1UL << EXTI_EMR2_EM39_Pos)               /*!< 0x00000080 */

+#define EXTI_EMR2_EM39             EXTI_EMR2_EM39_Msk                          /*!< Event Mask on line 39*/

+#define EXTI_EMR2_EM40_Pos         (8U)

+#define EXTI_EMR2_EM40_Msk         (0x1UL << EXTI_EMR2_EM40_Pos)               /*!< 0x00000100 */

+#define EXTI_EMR2_EM40             EXTI_EMR2_EM40_Msk                          /*!< Event Mask on line 40*/

+#define EXTI_EMR2_EM41_Pos         (9U)

+#define EXTI_EMR2_EM41_Msk         (0x1UL << EXTI_EMR2_EM41_Pos)               /*!< 0x00000200 */

+#define EXTI_EMR2_EM41             EXTI_EMR2_EM41_Msk                          /*!< Event Mask on line 41*/

+#define EXTI_EMR2_EM42_Pos         (10U)

+#define EXTI_EMR2_EM42_Msk         (0x1UL << EXTI_EMR2_EM42_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR2_EM42             EXTI_EMR2_EM42_Msk                          /*!< Event Mask on line 42 */

+#define EXTI_EMR2_EM43_Pos         (11U)

+#define EXTI_EMR2_EM43_Msk         (0x1UL << EXTI_EMR2_EM43_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR2_EM43             EXTI_EMR2_EM43_Msk                          /*!< Event Mask on line 43 */

+#define EXTI_EMR2_EM44_Pos         (12U)

+#define EXTI_EMR2_EM44_Msk         (0x1UL << EXTI_EMR2_EM44_Pos)               /*!< 0x00001000 */

+#define EXTI_EMR2_EM44             EXTI_EMR2_EM44_Msk                          /*!< Event Mask on line 44 */

+#define EXTI_EMR2_EM46_Pos         (14U)

+#define EXTI_EMR2_EM46_Msk         (0x1UL << EXTI_EMR2_EM46_Pos)               /*!< 0x00004000 */

+#define EXTI_EMR2_EM46             EXTI_EMR2_EM46_Msk                          /*!< Event Mask on line 46 */

+#define EXTI_EMR2_EM47_Pos         (15U)

+#define EXTI_EMR2_EM47_Msk         (0x1UL << EXTI_EMR2_EM47_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR2_EM47             EXTI_EMR2_EM47_Msk                          /*!< Event Mask on line 47 */

+#define EXTI_EMR2_EM48_Pos         (16U)

+#define EXTI_EMR2_EM48_Msk         (0x1UL << EXTI_EMR2_EM48_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR2_EM48             EXTI_EMR2_EM48_Msk                          /*!< Event Mask on line 48 */

+#define EXTI_EMR2_EM49_Pos         (17U)

+#define EXTI_EMR2_EM49_Msk         (0x1UL << EXTI_EMR2_EM49_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR2_EM49             EXTI_EMR2_EM49_Msk                          /*!< Event Mask on line 49 */

+#define EXTI_EMR2_EM50_Pos         (18U)

+#define EXTI_EMR2_EM50_Msk         (0x1UL << EXTI_EMR2_EM50_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR2_EM50             EXTI_EMR2_EM50_Msk                          /*!< Event Mask on line 50 */

+#define EXTI_EMR2_EM51_Pos         (19U)

+#define EXTI_EMR2_EM51_Msk         (0x1UL << EXTI_EMR2_EM51_Pos)               /*!< 0x00080000 */

+#define EXTI_EMR2_EM51             EXTI_EMR2_EM51_Msk                          /*!< Event Mask on line 51 */

+#define EXTI_EMR2_EM52_Pos         (20U)

+#define EXTI_EMR2_EM52_Msk         (0x1UL << EXTI_EMR2_EM52_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR2_EM52             EXTI_EMR2_EM52_Msk                          /*!< Event Mask on line 52 */

+#define EXTI_EMR2_EM53_Pos         (21U)

+#define EXTI_EMR2_EM53_Msk         (0x1UL << EXTI_EMR2_EM53_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR2_EM53             EXTI_EMR2_EM53_Msk                          /*!< Event Mask on line 53 */

+#define EXTI_EMR2_EM54_Pos         (22U)

+#define EXTI_EMR2_EM54_Msk         (0x1UL << EXTI_EMR2_EM54_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR2_EM54             EXTI_EMR2_EM54_Msk                          /*!< Event Mask on line 54 */

+#define EXTI_EMR2_EM55_Pos         (23U)

+#define EXTI_EMR2_EM55_Msk         (0x1UL << EXTI_EMR2_EM55_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR2_EM55             EXTI_EMR2_EM55_Msk                          /*!< Event Mask on line 55 */

+#define EXTI_EMR2_EM56_Pos         (24U)

+#define EXTI_EMR2_EM56_Msk         (0x1UL << EXTI_EMR2_EM56_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR2_EM56             EXTI_EMR2_EM56_Msk                          /*!< Event Mask on line 56 */

+#define EXTI_EMR2_EM57_Pos         (25U)

+#define EXTI_EMR2_EM57_Msk         (0x1UL << EXTI_EMR2_EM57_Pos)               /*!< 0x02000000 */

+#define EXTI_EMR2_EM57             EXTI_EMR2_EM57_Msk                          /*!< Event Mask on line 57 */

+#define EXTI_EMR2_EM58_Pos         (26U)

+#define EXTI_EMR2_EM58_Msk         (0x1UL << EXTI_EMR2_EM58_Pos)               /*!< 0x04000000 */

+#define EXTI_EMR2_EM58             EXTI_EMR2_EM58_Msk                          /*!< Event Mask on line 58 */

+#define EXTI_EMR2_EM59_Pos         (27U)

+#define EXTI_EMR2_EM59_Msk         (0x1UL << EXTI_EMR2_EM59_Pos)               /*!< 0x08000000 */

+#define EXTI_EMR2_EM59             EXTI_EMR2_EM59_Msk                          /*!< Event Mask on line 59 */

+#define EXTI_EMR2_EM60_Pos         (28U)

+#define EXTI_EMR2_EM60_Msk         (0x1UL << EXTI_EMR2_EM60_Pos)               /*!< 0x10000000 */

+#define EXTI_EMR2_EM60             EXTI_EMR2_EM60_Msk                          /*!< Event Mask on line 60 */

+#define EXTI_EMR2_EM61_Pos         (29U)

+#define EXTI_EMR2_EM61_Msk         (0x1UL << EXTI_EMR2_EM61_Pos)               /*!< 0x20000000 */

+#define EXTI_EMR2_EM61             EXTI_EMR2_EM61_Msk                          /*!< Event Mask on line 61 */

+#define EXTI_EMR2_EM62_Pos         (30U)

+#define EXTI_EMR2_EM62_Msk         (0x1UL << EXTI_EMR2_EM62_Pos)               /*!< 0x40000000 */

+#define EXTI_EMR2_EM62             EXTI_EMR2_EM62_Msk                          /*!< Event Mask on line 62 */

+#define EXTI_EMR2_EM63_Pos         (31U)

+#define EXTI_EMR2_EM63_Msk         (0x1UL << EXTI_EMR2_EM63_Pos)               /*!< 0x80000000 */

+#define EXTI_EMR2_EM63             EXTI_EMR2_EM63_Msk                          /*!< Event Mask on line 63 */

+

+/*******************  Bit definition for EXTI_PR2 register  ********************/

+#define EXTI_PR2_PR_Pos            (17U)

+#define EXTI_PR2_PR_Msk            (0x5UL << EXTI_PR2_PR_Pos)                  /*!< 0x000A0000 */

+#define EXTI_PR2_PR                EXTI_PR2_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR2_PR49_Pos          (17U)

+#define EXTI_PR2_PR49_Msk          (0x1UL << EXTI_PR2_PR49_Pos)                /*!< 0x00020000 */

+#define EXTI_PR2_PR49              EXTI_PR2_PR49_Msk                           /*!< Pending bit for line 49 */

+#define EXTI_PR2_PR51_Pos          (19U)

+#define EXTI_PR2_PR51_Msk          (0x1UL << EXTI_PR2_PR51_Pos)                /*!< 0x00080000 */

+#define EXTI_PR2_PR51              EXTI_PR2_PR51_Msk                           /*!< Pending bit for line 51 */

+

+/*******************  Bit definition for EXTI_IMR3 register  *******************/

+#define EXTI_IMR3_IM_Pos           (0U)

+#define EXTI_IMR3_IM_Msk           (0x00F5FFFFUL << EXTI_IMR3_IM_Pos)          /*!< 0x00F5FFFF */

+#define EXTI_IMR3_IM               EXTI_IMR3_IM_Msk                            /*!< Interrupt Mask */

+#define EXTI_IMR3_IM64_Pos         (0U)

+#define EXTI_IMR3_IM64_Msk         (0x1UL << EXTI_IMR3_IM64_Pos)               /*!< 0x00000001 */

+#define EXTI_IMR3_IM64             EXTI_IMR3_IM64_Msk                          /*!< Interrupt Mask on line 64 */

+#define EXTI_IMR3_IM65_Pos         (1U)

+#define EXTI_IMR3_IM65_Msk         (0x1UL << EXTI_IMR3_IM65_Pos)               /*!< 0x00000002 */

+#define EXTI_IMR3_IM65             EXTI_IMR3_IM65_Msk                          /*!< Interrupt Mask on line 65 */

+#define EXTI_IMR3_IM66_Pos         (2U)

+#define EXTI_IMR3_IM66_Msk         (0x1UL << EXTI_IMR3_IM66_Pos)               /*!< 0x00000004 */

+#define EXTI_IMR3_IM66             EXTI_IMR3_IM66_Msk                          /*!< Interrupt Mask on line 66 */

+#define EXTI_IMR3_IM67_Pos         (3U)

+#define EXTI_IMR3_IM67_Msk         (0x1UL << EXTI_IMR3_IM67_Pos)               /*!< 0x00000008 */

+#define EXTI_IMR3_IM67             EXTI_IMR3_IM67_Msk                          /*!< Interrupt Mask on line 67 */

+#define EXTI_IMR3_IM68_Pos         (4U)

+#define EXTI_IMR3_IM68_Msk         (0x1UL << EXTI_IMR3_IM68_Pos)               /*!< 0x00000010 */

+#define EXTI_IMR3_IM68             EXTI_IMR3_IM68_Msk                          /*!< Interrupt Mask on line 68 */

+#define EXTI_IMR3_IM69_Pos         (5U)

+#define EXTI_IMR3_IM69_Msk         (0x1UL << EXTI_IMR3_IM69_Pos)               /*!< 0x00000020 */

+#define EXTI_IMR3_IM69             EXTI_IMR3_IM69_Msk                          /*!< Interrupt Mask on line 69 */

+#define EXTI_IMR3_IM70_Pos         (6U)

+#define EXTI_IMR3_IM70_Msk         (0x1UL << EXTI_IMR3_IM70_Pos)               /*!< 0x00000040 */

+#define EXTI_IMR3_IM70             EXTI_IMR3_IM70_Msk                          /*!< Interrupt Mask on line 70 */

+#define EXTI_IMR3_IM71_Pos         (7U)

+#define EXTI_IMR3_IM71_Msk         (0x1UL << EXTI_IMR3_IM71_Pos)               /*!< 0x00000080 */

+#define EXTI_IMR3_IM71             EXTI_IMR3_IM71_Msk                          /*!< Interrupt Mask on line 71 */

+#define EXTI_IMR3_IM72_Pos         (8U)

+#define EXTI_IMR3_IM72_Msk         (0x1UL << EXTI_IMR3_IM72_Pos)               /*!< 0x00000100 */

+#define EXTI_IMR3_IM72             EXTI_IMR3_IM72_Msk                          /*!< Interrupt Mask on line 72 */

+#define EXTI_IMR3_IM73_Pos         (9U)

+#define EXTI_IMR3_IM73_Msk         (0x1UL << EXTI_IMR3_IM73_Pos)               /*!< 0x00000200 */

+#define EXTI_IMR3_IM73             EXTI_IMR3_IM73_Msk                          /*!< Interrupt Mask on line 73 */

+#define EXTI_IMR3_IM74_Pos         (10U)

+#define EXTI_IMR3_IM74_Msk         (0x1UL << EXTI_IMR3_IM74_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR3_IM74             EXTI_IMR3_IM74_Msk                          /*!< Interrupt Mask on line 74 */

+#define EXTI_IMR3_IM75_Pos         (11U)

+#define EXTI_IMR3_IM75_Msk         (0x1UL << EXTI_IMR3_IM75_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR3_IM75             EXTI_IMR3_IM75_Msk                          /*!< Interrupt Mask on line 75 */

+#define EXTI_IMR3_IM76_Pos         (12U)

+#define EXTI_IMR3_IM76_Msk         (0x1UL << EXTI_IMR3_IM76_Pos)               /*!< 0x00001000 */

+#define EXTI_IMR3_IM76             EXTI_IMR3_IM76_Msk                          /*!< Interrupt Mask on line 76 */

+#define EXTI_IMR3_IM77_Pos         (13U)

+#define EXTI_IMR3_IM77_Msk         (0x1UL << EXTI_IMR3_IM77_Pos)               /*!< 0x00002000 */

+#define EXTI_IMR3_IM77             EXTI_IMR3_IM77_Msk                          /*!< Interrupt Mask on line 77 */

+#define EXTI_IMR3_IM78_Pos         (14U)

+#define EXTI_IMR3_IM78_Msk         (0x1UL << EXTI_IMR3_IM78_Pos)               /*!< 0x00004000 */

+#define EXTI_IMR3_IM78             EXTI_IMR3_IM78_Msk                          /*!< Interrupt Mask on line 78 */

+#define EXTI_IMR3_IM79_Pos         (15U)

+#define EXTI_IMR3_IM79_Msk         (0x1UL << EXTI_IMR3_IM79_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR3_IM79             EXTI_IMR3_IM79_Msk                          /*!< Interrupt Mask on line 79 */

+#define EXTI_IMR3_IM80_Pos         (16U)

+#define EXTI_IMR3_IM80_Msk         (0x1UL << EXTI_IMR3_IM80_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR3_IM80             EXTI_IMR3_IM80_Msk                          /*!< Interrupt Mask on line 80 */

+#define EXTI_IMR3_IM82_Pos         (18U)

+#define EXTI_IMR3_IM82_Msk         (0x1UL << EXTI_IMR3_IM82_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR3_IM82             EXTI_IMR3_IM82_Msk                          /*!< Interrupt Mask on line 82 */

+#define EXTI_IMR3_IM84_Pos         (20U)

+#define EXTI_IMR3_IM84_Msk         (0x1UL << EXTI_IMR3_IM84_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR3_IM84             EXTI_IMR3_IM84_Msk                          /*!< Interrupt Mask on line 84 */

+#define EXTI_IMR3_IM85_Pos         (21U)

+#define EXTI_IMR3_IM85_Msk         (0x1UL << EXTI_IMR3_IM85_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR3_IM85             EXTI_IMR3_IM85_Msk                          /*!< Interrupt Mask on line 85 */

+#define EXTI_IMR3_IM86_Pos         (22U)

+#define EXTI_IMR3_IM86_Msk         (0x1UL << EXTI_IMR3_IM86_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR3_IM86             EXTI_IMR3_IM86_Msk                          /*!< Interrupt Mask on line 86 */

+#define EXTI_IMR3_IM87_Pos         (23U)

+#define EXTI_IMR3_IM87_Msk         (0x1UL << EXTI_IMR3_IM87_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR3_IM87             EXTI_IMR3_IM87_Msk                          /*!< Interrupt Mask on line 87 */

+

+

+/*******************  Bit definition for EXTI_EMR3 register  *******************/

+#define EXTI_EMR3_EM_Pos           (0U)

+#define EXTI_EMR3_EM_Msk           (0x00F5FFFFUL << EXTI_EMR3_EM_Pos)          /*!< 0x00F5FFFF */

+#define EXTI_EMR3_EM               EXTI_EMR3_EM_Msk                            /*!< Event Mask           */

+#define EXTI_EMR3_EM64_Pos         (0U)

+#define EXTI_EMR3_EM64_Msk         (0x1UL << EXTI_EMR3_EM64_Pos)               /*!< 0x00000001 */

+#define EXTI_EMR3_EM64             EXTI_EMR3_EM64_Msk                          /*!< Event Mask on line 64*/

+#define EXTI_EMR3_EM65_Pos         (1U)

+#define EXTI_EMR3_EM65_Msk         (0x1UL << EXTI_EMR3_EM65_Pos)               /*!< 0x00000002 */

+#define EXTI_EMR3_EM65             EXTI_EMR3_EM65_Msk                          /*!< Event Mask on line 65*/

+#define EXTI_EMR3_EM66_Pos         (2U)

+#define EXTI_EMR3_EM66_Msk         (0x1UL << EXTI_EMR3_EM66_Pos)               /*!< 0x00000004 */

+#define EXTI_EMR3_EM66             EXTI_EMR3_EM66_Msk                          /*!< Event Mask on line 66*/

+#define EXTI_EMR3_EM67_Pos         (3U)

+#define EXTI_EMR3_EM67_Msk         (0x1UL << EXTI_EMR3_EM67_Pos)               /*!< 0x00000008 */

+#define EXTI_EMR3_EM67             EXTI_EMR3_EM67_Msk                          /*!< Event Mask on line 67*/

+#define EXTI_EMR3_EM68_Pos         (4U)

+#define EXTI_EMR3_EM68_Msk         (0x1UL << EXTI_EMR3_EM68_Pos)               /*!< 0x00000010 */

+#define EXTI_EMR3_EM68             EXTI_EMR3_EM68_Msk                          /*!< Event Mask on line 68*/

+#define EXTI_EMR3_EM69_Pos         (5U)

+#define EXTI_EMR3_EM69_Msk         (0x1UL << EXTI_EMR3_EM69_Pos)               /*!< 0x00000020 */

+#define EXTI_EMR3_EM69             EXTI_EMR3_EM69_Msk                          /*!< Event Mask on line 69*/

+#define EXTI_EMR3_EM70_Pos         (6U)

+#define EXTI_EMR3_EM70_Msk         (0x1UL << EXTI_EMR3_EM70_Pos)               /*!< 0x00000040 */

+#define EXTI_EMR3_EM70             EXTI_EMR3_EM70_Msk                          /*!< Event Mask on line 70*/

+#define EXTI_EMR3_EM71_Pos         (7U)

+#define EXTI_EMR3_EM71_Msk         (0x1UL << EXTI_EMR3_EM71_Pos)               /*!< 0x00000080 */

+#define EXTI_EMR3_EM71             EXTI_EMR3_EM71_Msk                          /*!< Event Mask on line 71*/

+#define EXTI_EMR3_EM72_Pos         (8U)

+#define EXTI_EMR3_EM72_Msk         (0x1UL << EXTI_EMR3_EM72_Pos)               /*!< 0x00000100 */

+#define EXTI_EMR3_EM72             EXTI_EMR3_EM72_Msk                          /*!< Event Mask on line 72*/

+#define EXTI_EMR3_EM73_Pos         (9U)

+#define EXTI_EMR3_EM73_Msk         (0x1UL << EXTI_EMR3_EM73_Pos)               /*!< 0x00000200 */

+#define EXTI_EMR3_EM73             EXTI_EMR3_EM73_Msk                          /*!< Event Mask on line 73*/

+#define EXTI_EMR3_EM74_Pos         (10U)

+#define EXTI_EMR3_EM74_Msk         (0x1UL << EXTI_EMR3_EM74_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR3_EM74             EXTI_EMR3_EM74_Msk                          /*!< Event Mask on line 74 */

+#define EXTI_EMR3_EM75_Pos         (11U)

+#define EXTI_EMR3_EM75_Msk         (0x1UL << EXTI_EMR3_EM75_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR3_EM75             EXTI_EMR3_EM75_Msk                          /*!< Event Mask on line 75 */

+#define EXTI_EMR3_EM76_Pos         (12U)

+#define EXTI_EMR3_EM76_Msk         (0x1UL << EXTI_EMR3_EM76_Pos)               /*!< 0x00001000 */

+#define EXTI_EMR3_EM76             EXTI_EMR3_EM76_Msk                          /*!< Event Mask on line 76 */

+#define EXTI_EMR3_EM77_Pos         (13U)

+#define EXTI_EMR3_EM77_Msk         (0x1UL << EXTI_EMR3_EM77_Pos)               /*!< 0x00002000 */

+#define EXTI_EMR3_EM77             EXTI_EMR3_EM77_Msk                          /*!< Event Mask on line 77 */

+#define EXTI_EMR3_EM78_Pos         (14U)

+#define EXTI_EMR3_EM78_Msk         (0x1UL << EXTI_EMR3_EM78_Pos)               /*!< 0x00004000 */

+#define EXTI_EMR3_EM78             EXTI_EMR3_EM78_Msk                          /*!< Event Mask on line 78 */

+#define EXTI_EMR3_EM79_Pos         (15U)

+#define EXTI_EMR3_EM79_Msk         (0x1UL << EXTI_EMR3_EM79_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR3_EM79             EXTI_EMR3_EM79_Msk                          /*!< Event Mask on line 79 */

+#define EXTI_EMR3_EM80_Pos         (16U)

+#define EXTI_EMR3_EM80_Msk         (0x1UL << EXTI_EMR3_EM80_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR3_EM80             EXTI_EMR3_EM80_Msk                          /*!< Event Mask on line 80 */

+#define EXTI_EMR3_EM81_Pos         (17U)

+#define EXTI_EMR3_EM81_Msk         (0x1UL << EXTI_EMR3_EM81_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR3_EM81             EXTI_EMR3_EM81_Msk                          /*!< Event Mask on line 81 */

+#define EXTI_EMR3_EM82_Pos         (18U)

+#define EXTI_EMR3_EM82_Msk         (0x1UL << EXTI_EMR3_EM82_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR3_EM82             EXTI_EMR3_EM82_Msk                          /*!< Event Mask on line 82 */

+#define EXTI_EMR3_EM84_Pos         (20U)

+#define EXTI_EMR3_EM84_Msk         (0x1UL << EXTI_EMR3_EM84_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR3_EM84             EXTI_EMR3_EM84_Msk                          /*!< Event Mask on line 84 */

+#define EXTI_EMR3_EM85_Pos         (21U)

+#define EXTI_EMR3_EM85_Msk         (0x1UL << EXTI_EMR3_EM85_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR3_EM85             EXTI_EMR3_EM85_Msk                          /*!< Event Mask on line 85 */

+#define EXTI_EMR3_EM86_Pos         (22U)

+#define EXTI_EMR3_EM86_Msk         (0x1UL << EXTI_EMR3_EM86_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR3_EM86             EXTI_EMR3_EM86_Msk                          /*!< Event Mask on line 86 */

+#define EXTI_EMR3_EM87_Pos         (23U)

+#define EXTI_EMR3_EM87_Msk         (0x1UL << EXTI_EMR3_EM87_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR3_EM87             EXTI_EMR3_EM87_Msk                          /*!< Event Mask on line 87 */

+

+/*******************  Bit definition for EXTI_PR3 register  ********************/

+#define EXTI_PR3_PR_Pos            (18U)

+#define EXTI_PR3_PR_Msk            (0x1DUL << EXTI_PR3_PR_Pos)                 /*!< 0x00740000 */

+#define EXTI_PR3_PR                EXTI_PR3_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR3_PR82_Pos          (18U)

+#define EXTI_PR3_PR82_Msk          (0x1UL << EXTI_PR3_PR82_Pos)                /*!< 0x00040000 */

+#define EXTI_PR3_PR82              EXTI_PR3_PR82_Msk                           /*!< Pending bit for line 82 */

+#define EXTI_PR3_PR84_Pos          (20U)

+#define EXTI_PR3_PR84_Msk          (0x1UL << EXTI_PR3_PR84_Pos)                /*!< 0x00100000 */

+#define EXTI_PR3_PR84              EXTI_PR3_PR84_Msk                           /*!< Pending bit for line 84 */

+#define EXTI_PR3_PR85_Pos          (21U)

+#define EXTI_PR3_PR85_Msk          (0x1UL << EXTI_PR3_PR85_Pos)                /*!< 0x00200000 */

+#define EXTI_PR3_PR85              EXTI_PR3_PR85_Msk                           /*!< Pending bit for line 85 */

+#define EXTI_PR3_PR86_Pos          (22U)

+#define EXTI_PR3_PR86_Msk          (0x1UL << EXTI_PR3_PR86_Pos)                /*!< 0x00400000 */

+#define EXTI_PR3_PR86              EXTI_PR3_PR86_Msk                           /*!< Pending bit for line 86 */

+/******************************************************************************/

+/*                                                                            */

+/*                                    FLASH                                   */

+/*                                                                            */

+/******************************************************************************/

+/*

+* @brief FLASH Global Defines

+*/

+#define FLASH_SECTOR_TOTAL                   8U                    /* 8 sectors */

+#define FLASH_SIZE                           0x200000UL            /* 2 MB   */

+#define FLASH_BANK_SIZE                      (FLASH_SIZE >> 1)     /* 1 MB   */

+#define FLASH_SECTOR_SIZE                    0x00020000UL          /* 128 KB */

+#define FLASH_LATENCY_DEFAULT                FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */

+#define FLASH_NB_32BITWORD_IN_FLASHWORD      8U                    /* 256 bits */

+#define DUAL_BANK                                                  /* Dual-bank Flash */

+

+/*******************  Bits definition for FLASH_ACR register  **********************/

+#define FLASH_ACR_LATENCY_Pos                (0U)

+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */

+#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */

+#define FLASH_ACR_LATENCY_0WS                (0x00000000UL)

+#define FLASH_ACR_LATENCY_1WS                (0x00000001UL)

+#define FLASH_ACR_LATENCY_2WS                (0x00000002UL)

+#define FLASH_ACR_LATENCY_3WS                (0x00000003UL)

+#define FLASH_ACR_LATENCY_4WS                (0x00000004UL)

+#define FLASH_ACR_LATENCY_5WS                (0x00000005UL)

+#define FLASH_ACR_LATENCY_6WS                (0x00000006UL)

+#define FLASH_ACR_LATENCY_7WS                (0x00000007UL)

+#define FLASH_ACR_LATENCY_8WS                (0x00000008UL)

+#define FLASH_ACR_LATENCY_9WS                (0x00000009UL)

+#define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)

+#define FLASH_ACR_LATENCY_11WS               (0x0000000BUL)

+#define FLASH_ACR_LATENCY_12WS               (0x0000000CUL)

+#define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)

+#define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)

+#define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)

+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)

+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */

+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */

+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */

+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */

+

+/*******************  Bits definition for FLASH_CR register  ***********************/

+#define FLASH_CR_LOCK_Pos                    (0U)

+#define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */

+#define FLASH_CR_LOCK                        FLASH_CR_LOCK_Msk                 /*!< Configuration lock bit */

+#define FLASH_CR_PG_Pos                      (1U)

+#define FLASH_CR_PG_Msk                      (0x1UL << FLASH_CR_PG_Pos)        /*!< 0x00000002 */

+#define FLASH_CR_PG                          FLASH_CR_PG_Msk                   /*!< Internal buffer control bit */

+#define FLASH_CR_SER_Pos                     (2U)

+#define FLASH_CR_SER_Msk                     (0x1UL << FLASH_CR_SER_Pos)       /*!< 0x00000004 */

+#define FLASH_CR_SER                         FLASH_CR_SER_Msk                  /*!< Sector erase request */

+#define FLASH_CR_BER_Pos                     (3U)

+#define FLASH_CR_BER_Msk                     (0x1UL << FLASH_CR_BER_Pos)       /*!< 0x00000008 */

+#define FLASH_CR_BER                         FLASH_CR_BER_Msk                  /*!< Bank erase request */

+#define FLASH_CR_PSIZE_Pos                   (4U)

+#define FLASH_CR_PSIZE_Msk                   (0x3UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000030 */

+#define FLASH_CR_PSIZE                       FLASH_CR_PSIZE_Msk                /*!< Program size */

+#define FLASH_CR_PSIZE_0                     (0x1UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000010 */

+#define FLASH_CR_PSIZE_1                     (0x2UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000020 */

+#define FLASH_CR_FW_Pos                      (6U)

+#define FLASH_CR_FW_Msk                      (0x1UL << FLASH_CR_FW_Pos)        /*!< 0x00000040 */

+#define FLASH_CR_FW                          FLASH_CR_FW_Msk                   /*!< Write forcing control bit */

+#define FLASH_CR_START_Pos                   (7U)

+#define FLASH_CR_START_Msk                   (0x1UL << FLASH_CR_START_Pos)     /*!< 0x00000080 */

+#define FLASH_CR_START                       FLASH_CR_START_Msk                /*!< Erase start control bit */

+#define FLASH_CR_SNB_Pos                     (8U)

+#define FLASH_CR_SNB_Msk                     (0x7UL << FLASH_CR_SNB_Pos)       /*!< 0x00000700 */

+#define FLASH_CR_SNB                         FLASH_CR_SNB_Msk                  /*!< Sector erase selection number */

+#define FLASH_CR_SNB_0                       (0x1UL << FLASH_CR_SNB_Pos)       /*!< 0x00000100 */

+#define FLASH_CR_SNB_1                       (0x2UL << FLASH_CR_SNB_Pos)       /*!< 0x00000200 */

+#define FLASH_CR_SNB_2                       (0x4UL << FLASH_CR_SNB_Pos)       /*!< 0x00000400 */

+#define FLASH_CR_CRC_EN_Pos                  (15U)

+#define FLASH_CR_CRC_EN_Msk                  (0x1UL << FLASH_CR_CRC_EN_Pos)    /*!< 0x00008000 */

+#define FLASH_CR_CRC_EN                      FLASH_CR_CRC_EN_Msk               /*!< CRC control bit */

+#define FLASH_CR_EOPIE_Pos                   (16U)

+#define FLASH_CR_EOPIE_Msk                   (0x1UL << FLASH_CR_EOPIE_Pos)     /*!< 0x00010000 */

+#define FLASH_CR_EOPIE                       FLASH_CR_EOPIE_Msk                /*!< End-of-program interrupt control bit */

+#define FLASH_CR_WRPERRIE_Pos                (17U)

+#define FLASH_CR_WRPERRIE_Msk                (0x1UL << FLASH_CR_WRPERRIE_Pos)  /*!< 0x00020000 */

+#define FLASH_CR_WRPERRIE                    FLASH_CR_WRPERRIE_Msk             /*!< Write protection error interrupt enable bit */

+#define FLASH_CR_PGSERRIE_Pos                (18U)

+#define FLASH_CR_PGSERRIE_Msk                (0x1UL << FLASH_CR_PGSERRIE_Pos)  /*!< 0x00040000 */

+#define FLASH_CR_PGSERRIE                    FLASH_CR_PGSERRIE_Msk             /*!< Programming sequence error interrupt enable bit */

+#define FLASH_CR_STRBERRIE_Pos               (19U)

+#define FLASH_CR_STRBERRIE_Msk               (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */

+#define FLASH_CR_STRBERRIE                   FLASH_CR_STRBERRIE_Msk            /*!< Strobe error interrupt enable bit */

+#define FLASH_CR_INCERRIE_Pos                (21U)

+#define FLASH_CR_INCERRIE_Msk                (0x1UL << FLASH_CR_INCERRIE_Pos)  /*!< 0x00200000 */

+#define FLASH_CR_INCERRIE                    FLASH_CR_INCERRIE_Msk             /*!< Inconsistency error interrupt enable bit */

+#define FLASH_CR_OPERRIE_Pos                 (22U)

+#define FLASH_CR_OPERRIE_Msk                 (0x1UL << FLASH_CR_OPERRIE_Pos)   /*!< 0x00400000 */

+#define FLASH_CR_OPERRIE                     FLASH_CR_OPERRIE_Msk              /*!< Write/erase error interrupt enable bit */

+#define FLASH_CR_RDPERRIE_Pos                (23U)

+#define FLASH_CR_RDPERRIE_Msk                (0x1UL << FLASH_CR_RDPERRIE_Pos)  /*!< 0x00800000 */

+#define FLASH_CR_RDPERRIE                    FLASH_CR_RDPERRIE_Msk             /*!< Read protection error interrupt enable bit */

+#define FLASH_CR_RDSERRIE_Pos                (24U)

+#define FLASH_CR_RDSERRIE_Msk                (0x1UL << FLASH_CR_RDSERRIE_Pos)  /*!< 0x01000000 */

+#define FLASH_CR_RDSERRIE                    FLASH_CR_RDSERRIE_Msk             /*!< Secure error interrupt enable bit */

+#define FLASH_CR_SNECCERRIE_Pos              (25U)

+#define FLASH_CR_SNECCERRIE_Msk              (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */

+#define FLASH_CR_SNECCERRIE                  FLASH_CR_SNECCERRIE_Msk            /*!< ECC single correction error interrupt enable bit */

+#define FLASH_CR_DBECCERRIE_Pos              (26U)

+#define FLASH_CR_DBECCERRIE_Msk              (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */

+#define FLASH_CR_DBECCERRIE                  FLASH_CR_DBECCERRIE_Msk            /*!< ECC double detection error interrupt enable bit */

+#define FLASH_CR_CRCENDIE_Pos                (27U)

+#define FLASH_CR_CRCENDIE_Msk                (0x1UL << FLASH_CR_CRCENDIE_Pos)  /*!< 0x08000000 */

+#define FLASH_CR_CRCENDIE                    FLASH_CR_CRCENDIE_Msk             /*!< CRC end of calculation interrupt enable bit */

+#define FLASH_CR_CRCRDERRIE_Pos              (28U)

+#define FLASH_CR_CRCRDERRIE_Msk              (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */

+#define FLASH_CR_CRCRDERRIE                  FLASH_CR_CRCRDERRIE_Msk            /*!< CRC read error interrupt enable bit */

+

+/*******************  Bits definition for FLASH_SR register  ***********************/

+#define FLASH_SR_BSY_Pos                     (0U)

+#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)       /*!< 0x00000001 */

+#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy flag */

+#define FLASH_SR_WBNE_Pos                    (1U)

+#define FLASH_SR_WBNE_Msk                    (0x1UL << FLASH_SR_WBNE_Pos)      /*!< 0x00000002 */

+#define FLASH_SR_WBNE                        FLASH_SR_WBNE_Msk                 /*!< Write buffer not empty flag */

+#define FLASH_SR_QW_Pos                      (2U)

+#define FLASH_SR_QW_Msk                      (0x1UL << FLASH_SR_QW_Pos)        /*!< 0x00000004 */

+#define FLASH_SR_QW                          FLASH_SR_QW_Msk                   /*!< Wait queue flag */

+#define FLASH_SR_CRC_BUSY_Pos                (3U)

+#define FLASH_SR_CRC_BUSY_Msk                (0x1UL << FLASH_SR_CRC_BUSY_Pos)  /*!< 0x00000008 */

+#define FLASH_SR_CRC_BUSY                    FLASH_SR_CRC_BUSY_Msk             /*!< CRC busy flag */

+#define FLASH_SR_EOP_Pos                     (16U)

+#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)       /*!< 0x00010000 */

+#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End-of-program flag */

+#define FLASH_SR_WRPERR_Pos                  (17U)

+#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)    /*!< 0x00020000 */

+#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protection error flag */

+#define FLASH_SR_PGSERR_Pos                  (18U)

+#define FLASH_SR_PGSERR_Msk                  (0x1UL << FLASH_SR_PGSERR_Pos)    /*!< 0x00040000 */

+#define FLASH_SR_PGSERR                      FLASH_SR_PGSERR_Msk               /*!< Programming sequence error flag */

+#define FLASH_SR_STRBERR_Pos                 (19U)

+#define FLASH_SR_STRBERR_Msk                 (0x1UL << FLASH_SR_STRBERR_Pos)   /*!< 0x00080000 */

+#define FLASH_SR_STRBERR                     FLASH_SR_STRBERR_Msk              /*!< Strobe error flag */

+#define FLASH_SR_INCERR_Pos                  (21U)

+#define FLASH_SR_INCERR_Msk                  (0x1UL << FLASH_SR_INCERR_Pos)    /*!< 0x00200000 */

+#define FLASH_SR_INCERR                      FLASH_SR_INCERR_Msk               /*!< Inconsistency error flag */

+#define FLASH_SR_OPERR_Pos                   (22U)

+#define FLASH_SR_OPERR_Msk                   (0x1UL << FLASH_SR_OPERR_Pos)     /*!< 0x00400000 */

+#define FLASH_SR_OPERR                       FLASH_SR_OPERR_Msk                /*!< Write/erase error flag */

+#define FLASH_SR_RDPERR_Pos                  (23U)

+#define FLASH_SR_RDPERR_Msk                  (0x1UL << FLASH_SR_RDPERR_Pos)    /*!< 0x00800000 */

+#define FLASH_SR_RDPERR                      FLASH_SR_RDPERR_Msk               /*!< Read protection error flag */

+#define FLASH_SR_RDSERR_Pos                  (24U)

+#define FLASH_SR_RDSERR_Msk                  (0x1UL << FLASH_SR_RDSERR_Pos)    /*!< 0x01000000 */

+#define FLASH_SR_RDSERR                      FLASH_SR_RDSERR_Msk               /*!< Secure error flag */

+#define FLASH_SR_SNECCERR_Pos                (25U)

+#define FLASH_SR_SNECCERR_Msk                (0x1UL << FLASH_SR_SNECCERR_Pos)  /*!< 0x02000000 */

+#define FLASH_SR_SNECCERR                    FLASH_SR_SNECCERR_Msk             /*!< Single correction error flag */

+#define FLASH_SR_DBECCERR_Pos                (26U)

+#define FLASH_SR_DBECCERR_Msk                (0x1UL << FLASH_SR_DBECCERR_Pos)  /*!< 0x04000000 */

+#define FLASH_SR_DBECCERR                    FLASH_SR_DBECCERR_Msk             /*!< ECC double detection error flag */

+#define FLASH_SR_CRCEND_Pos                  (27U)

+#define FLASH_SR_CRCEND_Msk                  (0x1UL << FLASH_SR_CRCEND_Pos)    /*!< 0x08000000 */

+#define FLASH_SR_CRCEND                      FLASH_SR_CRCEND_Msk               /*!< CRC end of calculation flag */

+#define FLASH_SR_CRCRDERR_Pos                (28U)

+#define FLASH_SR_CRCRDERR_Msk                (0x1UL << FLASH_SR_CRCRDERR_Pos)  /*!< 0x10000000 */

+#define FLASH_SR_CRCRDERR                    FLASH_SR_CRCRDERR_Msk             /*!< CRC read error flag */

+

+/*******************  Bits definition for FLASH_CCR register  *******************/

+#define FLASH_CCR_CLR_EOP_Pos                (16U)

+#define FLASH_CCR_CLR_EOP_Msk                (0x1UL << FLASH_CCR_CLR_EOP_Pos)  /*!< 0x00010000 */

+#define FLASH_CCR_CLR_EOP                    FLASH_CCR_CLR_EOP_Msk             /*!< EOP flag clear bit */

+#define FLASH_CCR_CLR_WRPERR_Pos             (17U)

+#define FLASH_CCR_CLR_WRPERR_Msk             (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */

+#define FLASH_CCR_CLR_WRPERR                 FLASH_CCR_CLR_WRPERR_Msk            /*!< WRPERR flag clear bit */

+#define FLASH_CCR_CLR_PGSERR_Pos             (18U)

+#define FLASH_CCR_CLR_PGSERR_Msk             (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */

+#define FLASH_CCR_CLR_PGSERR                 FLASH_CCR_CLR_PGSERR_Msk            /*!< PGSERR flag clear bit */

+#define FLASH_CCR_CLR_STRBERR_Pos            (19U)

+#define FLASH_CCR_CLR_STRBERR_Msk            (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */

+#define FLASH_CCR_CLR_STRBERR                FLASH_CCR_CLR_STRBERR_Msk            /*!< STRBERR flag clear bit */

+#define FLASH_CCR_CLR_INCERR_Pos             (21U)

+#define FLASH_CCR_CLR_INCERR_Msk             (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */

+#define FLASH_CCR_CLR_INCERR                 FLASH_CCR_CLR_INCERR_Msk            /*!< INCERR flag clear bit */

+#define FLASH_CCR_CLR_OPERR_Pos              (22U)

+#define FLASH_CCR_CLR_OPERR_Msk              (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */

+#define FLASH_CCR_CLR_OPERR                  FLASH_CCR_CLR_OPERR_Msk            /*!< OPERR flag clear bit */

+#define FLASH_CCR_CLR_RDPERR_Pos             (23U)

+#define FLASH_CCR_CLR_RDPERR_Msk             (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */

+#define FLASH_CCR_CLR_RDPERR                 FLASH_CCR_CLR_RDPERR_Msk            /*!< RDPERR flag clear bit */

+#define FLASH_CCR_CLR_RDSERR_Pos             (24U)

+#define FLASH_CCR_CLR_RDSERR_Msk             (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */

+#define FLASH_CCR_CLR_RDSERR                 FLASH_CCR_CLR_RDSERR_Msk            /*!< RDSERR flag clear bit */

+#define FLASH_CCR_CLR_SNECCERR_Pos           (25U)

+#define FLASH_CCR_CLR_SNECCERR_Msk           (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */

+#define FLASH_CCR_CLR_SNECCERR               FLASH_CCR_CLR_SNECCERR_Msk            /*!< SNECCERR flag clear bit */

+#define FLASH_CCR_CLR_DBECCERR_Pos           (26U)

+#define FLASH_CCR_CLR_DBECCERR_Msk           (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */

+#define FLASH_CCR_CLR_DBECCERR               FLASH_CCR_CLR_DBECCERR_Msk            /*!< DBECCERR flag clear bit */

+#define FLASH_CCR_CLR_CRCEND_Pos             (27U)

+#define FLASH_CCR_CLR_CRCEND_Msk             (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */

+#define FLASH_CCR_CLR_CRCEND                 FLASH_CCR_CLR_CRCEND_Msk            /*!< CRCEND flag clear bit */

+#define FLASH_CCR_CLR_CRCRDERR_Pos           (28U)

+#define FLASH_CCR_CLR_CRCRDERR_Msk           (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */

+#define FLASH_CCR_CLR_CRCRDERR               FLASH_CCR_CLR_CRCRDERR_Msk            /*!< CRCRDERR flag clear bit */

+

+/*******************  Bits definition for FLASH_OPTCR register  *******************/

+#define FLASH_OPTCR_OPTLOCK_Pos              (0U)

+#define FLASH_OPTCR_OPTLOCK_Msk              (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)  /*!< 0x00000001 */

+#define FLASH_OPTCR_OPTLOCK                  FLASH_OPTCR_OPTLOCK_Msk             /*!< FLASH_OPTCR lock option configuration bit */

+#define FLASH_OPTCR_OPTSTART_Pos             (1U)

+#define FLASH_OPTCR_OPTSTART_Msk             (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */

+#define FLASH_OPTCR_OPTSTART                 FLASH_OPTCR_OPTSTART_Msk            /*!< Option byte start change option configuration bit */

+#define FLASH_OPTCR_MER_Pos                  (4U)

+#define FLASH_OPTCR_MER_Msk                  (0x1UL << FLASH_OPTCR_MER_Pos)      /*!< 0x00000010 */

+#define FLASH_OPTCR_MER                      FLASH_OPTCR_MER_Msk                 /*!< Mass erase request */

+#define FLASH_OPTCR_OPTCHANGEERRIE_Pos       (30U)

+#define FLASH_OPTCR_OPTCHANGEERRIE_Msk       (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */

+#define FLASH_OPTCR_OPTCHANGEERRIE           FLASH_OPTCR_OPTCHANGEERRIE_Msk            /*!< Option byte change error interrupt enable bit */

+#define FLASH_OPTCR_SWAP_BANK_Pos            (31U)

+#define FLASH_OPTCR_SWAP_BANK_Msk            (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */

+#define FLASH_OPTCR_SWAP_BANK                FLASH_OPTCR_SWAP_BANK_Msk            /*!< Bank swapping option configuration bit */

+

+/*******************  Bits definition for FLASH_OPTSR register  ***************/

+#define FLASH_OPTSR_OPT_BUSY_Pos             (0U)

+#define FLASH_OPTSR_OPT_BUSY_Msk             (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */

+#define FLASH_OPTSR_OPT_BUSY                 FLASH_OPTSR_OPT_BUSY_Msk            /*!< Option byte change ongoing flag */

+#define FLASH_OPTSR_BOR_LEV_Pos              (2U)

+#define FLASH_OPTSR_BOR_LEV_Msk              (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */

+#define FLASH_OPTSR_BOR_LEV                  FLASH_OPTSR_BOR_LEV_Msk            /*!< Brownout level option status bit */

+#define FLASH_OPTSR_BOR_LEV_0                (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */

+#define FLASH_OPTSR_BOR_LEV_1                (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */

+#define FLASH_OPTSR_IWDG1_SW_Pos             (4U)

+#define FLASH_OPTSR_IWDG1_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */

+#define FLASH_OPTSR_IWDG1_SW                 FLASH_OPTSR_IWDG1_SW_Msk            /*!< IWDG1 control mode option status bit */

+#define FLASH_OPTSR_IWDG2_SW_Pos             (5U)

+#define FLASH_OPTSR_IWDG2_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG2_SW_Pos) /*!< 0x00000020 */

+#define FLASH_OPTSR_IWDG2_SW                 FLASH_OPTSR_IWDG2_SW_Msk            /*!< IWDG2 control mode option status bit */

+#define FLASH_OPTSR_NRST_STOP_D1_Pos         (6U)

+#define FLASH_OPTSR_NRST_STOP_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */

+#define FLASH_OPTSR_NRST_STOP_D1             FLASH_OPTSR_NRST_STOP_D1_Msk            /*!< D1 domain DStop entry reset option status bit */

+#define FLASH_OPTSR_NRST_STBY_D1_Pos         (7U)

+#define FLASH_OPTSR_NRST_STBY_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */

+#define FLASH_OPTSR_NRST_STBY_D1             FLASH_OPTSR_NRST_STBY_D1_Msk            /*!< D1 domain DStandby entry reset option status bit */

+#define FLASH_OPTSR_RDP_Pos                  (8U)

+#define FLASH_OPTSR_RDP_Msk                  (0xFFUL << FLASH_OPTSR_RDP_Pos)   /*!< 0x0000FF00 */

+#define FLASH_OPTSR_RDP                      FLASH_OPTSR_RDP_Msk               /*!< Readout protection level option status byte */

+#define FLASH_OPTSR_FZ_IWDG_STOP_Pos         (17U)

+#define FLASH_OPTSR_FZ_IWDG_STOP_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */

+#define FLASH_OPTSR_FZ_IWDG_STOP             FLASH_OPTSR_FZ_IWDG_STOP_Msk            /*!< IWDG Stop mode freeze option status bit */

+#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos         (18U)

+#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */

+#define FLASH_OPTSR_FZ_IWDG_SDBY             FLASH_OPTSR_FZ_IWDG_SDBY_Msk            /*!< IWDG Standby mode freeze option status bit */

+#define FLASH_OPTSR_ST_RAM_SIZE_Pos          (19U)

+#define FLASH_OPTSR_ST_RAM_SIZE_Msk          (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */

+#define FLASH_OPTSR_ST_RAM_SIZE              FLASH_OPTSR_ST_RAM_SIZE_Msk            /*!< ST RAM size option status */

+#define FLASH_OPTSR_ST_RAM_SIZE_0            (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */

+#define FLASH_OPTSR_ST_RAM_SIZE_1            (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */

+#define FLASH_OPTSR_SECURITY_Pos             (21U)

+#define FLASH_OPTSR_SECURITY_Msk             (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */

+#define FLASH_OPTSR_SECURITY                 FLASH_OPTSR_SECURITY_Msk            /*!< Security enable option status bit */

+#define FLASH_OPTSR_BCM4_Pos                 (22U)

+#define FLASH_OPTSR_BCM4_Msk                 (0x1UL << FLASH_OPTSR_BCM4_Pos)   /*!< 0x00400000 */

+#define FLASH_OPTSR_BCM4                     FLASH_OPTSR_BCM4_Msk              /*!< Arm Cortex-M4 boot option status bit */

+#define FLASH_OPTSR_BCM7_Pos                 (23U)

+#define FLASH_OPTSR_BCM7_Msk                 (0x1UL << FLASH_OPTSR_BCM7_Pos)   /*!< 0x00800000 */

+#define FLASH_OPTSR_BCM7                     FLASH_OPTSR_BCM7_Msk              /*!< Arm Cortex-M7 boot option status bit */

+#define FLASH_OPTSR_NRST_STOP_D2_Pos         (24U)

+#define FLASH_OPTSR_NRST_STOP_D2_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D2_Pos) /*!< 0x01000000 */

+#define FLASH_OPTSR_NRST_STOP_D2             FLASH_OPTSR_NRST_STOP_D2_Msk            /*!< D2 domain DStop entry reset option status bit */

+#define FLASH_OPTSR_NRST_STBY_D2_Pos         (25U)

+#define FLASH_OPTSR_NRST_STBY_D2_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D2_Pos) /*!< 0x02000000 */

+#define FLASH_OPTSR_NRST_STBY_D2             FLASH_OPTSR_NRST_STBY_D2_Msk            /*!< D2 domain DStandby entry reset option status bit */

+#define FLASH_OPTSR_IO_HSLV_Pos              (29U)

+#define FLASH_OPTSR_IO_HSLV_Msk              (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */

+#define FLASH_OPTSR_IO_HSLV                  FLASH_OPTSR_IO_HSLV_Msk            /*!< I/O high-speed at low-voltage status bit */

+#define FLASH_OPTSR_OPTCHANGEERR_Pos         (30U)

+#define FLASH_OPTSR_OPTCHANGEERR_Msk         (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */

+#define FLASH_OPTSR_OPTCHANGEERR             FLASH_OPTSR_OPTCHANGEERR_Msk            /*!< Option byte change error flag */

+#define FLASH_OPTSR_SWAP_BANK_OPT_Pos        (31U)

+#define FLASH_OPTSR_SWAP_BANK_OPT_Msk        (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */

+#define FLASH_OPTSR_SWAP_BANK_OPT            FLASH_OPTSR_SWAP_BANK_OPT_Msk            /*!< Bank swapping option status bit */

+

+/*******************  Bits definition for FLASH_OPTCCR register  *******************/

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos    (30U)

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk    (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR        FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk            /*!< OPTCHANGEERR reset bit */

+

+/*******************  Bits definition for FLASH_PRAR register  *********************/

+#define FLASH_PRAR_PROT_AREA_START_Pos       (0U)

+#define FLASH_PRAR_PROT_AREA_START_Msk       (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */

+#define FLASH_PRAR_PROT_AREA_START           FLASH_PRAR_PROT_AREA_START_Msk              /*!< PCROP area start status bits */

+#define FLASH_PRAR_PROT_AREA_END_Pos         (16U)

+#define FLASH_PRAR_PROT_AREA_END_Msk         (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */

+#define FLASH_PRAR_PROT_AREA_END             FLASH_PRAR_PROT_AREA_END_Msk              /*!< PCROP area end status bits */

+#define FLASH_PRAR_DMEP_Pos                  (31U)

+#define FLASH_PRAR_DMEP_Msk                  (0x1UL << FLASH_PRAR_DMEP_Pos)    /*!< 0x80000000 */

+#define FLASH_PRAR_DMEP                      FLASH_PRAR_DMEP_Msk               /*!< PCROP protected erase enable option status bit */

+

+/*******************  Bits definition for FLASH_SCAR register  *********************/

+#define FLASH_SCAR_SEC_AREA_START_Pos        (0U)

+#define FLASH_SCAR_SEC_AREA_START_Msk        (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */

+#define FLASH_SCAR_SEC_AREA_START            FLASH_SCAR_SEC_AREA_START_Msk              /*!< Secure-only area start status bits */

+#define FLASH_SCAR_SEC_AREA_END_Pos          (16U)

+#define FLASH_SCAR_SEC_AREA_END_Msk          (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */

+#define FLASH_SCAR_SEC_AREA_END              FLASH_SCAR_SEC_AREA_END_Msk              /*!< Secure-only area end status bits */

+#define FLASH_SCAR_DMES_Pos                  (31U)

+#define FLASH_SCAR_DMES_Msk                  (0x1UL << FLASH_SCAR_DMES_Pos)    /*!< 0x80000000 */

+#define FLASH_SCAR_DMES                      FLASH_SCAR_DMES_Msk               /*!< Secure access protected erase enable option status bit */

+

+/*******************  Bits definition for FLASH_WPSN register  *********************/

+#define FLASH_WPSN_WRPSN_Pos                 (0U)

+#define FLASH_WPSN_WRPSN_Msk                 (0xFFUL << FLASH_WPSN_WRPSN_Pos)  /*!< 0x000000FF */

+#define FLASH_WPSN_WRPSN                     FLASH_WPSN_WRPSN_Msk              /*!< Sector write protection option status byte */

+

+/*******************  Bits definition for FLASH_BOOT7_CUR register  ****************/

+#define FLASH_BOOT7_BCM7_ADD0_Pos            (0U)

+#define FLASH_BOOT7_BCM7_ADD0_Msk            (0xFFFFUL << FLASH_BOOT7_BCM7_ADD0_Pos) /*!< 0x0000FFFF */

+#define FLASH_BOOT7_BCM7_ADD0                FLASH_BOOT7_BCM7_ADD0_Msk               /*!< Arm Cortex-M7 boot address 0 */

+#define FLASH_BOOT7_BCM7_ADD1_Pos            (16U)

+#define FLASH_BOOT7_BCM7_ADD1_Msk            (0xFFFFUL << FLASH_BOOT7_BCM7_ADD1_Pos) /*!< 0xFFFF0000 */

+#define FLASH_BOOT7_BCM7_ADD1                FLASH_BOOT7_BCM7_ADD1_Msk               /*!< Arm Cortex-M7 boot address 1 */

+

+/*******************  Bits definition for FLASH_BOOT4 register  ********************/

+#define FLASH_BOOT4_BCM4_ADD0_Pos            (0U)

+#define FLASH_BOOT4_BCM4_ADD0_Msk            (0xFFFFUL << FLASH_BOOT4_BCM4_ADD0_Pos) /*!< 0x0000FFFF */

+#define FLASH_BOOT4_BCM4_ADD0                FLASH_BOOT4_BCM4_ADD0_Msk               /*!< Arm Cortex-M4 boot address 0 */

+#define FLASH_BOOT4_BCM4_ADD1_Pos            (16U)

+#define FLASH_BOOT4_BCM4_ADD1_Msk            (0xFFFFUL << FLASH_BOOT4_BCM4_ADD1_Pos) /*!< 0xFFFF0000 */

+#define FLASH_BOOT4_BCM4_ADD1                FLASH_BOOT4_BCM4_ADD1_Msk               /*!< Arm Cortex-M4 boot address 1 */

+

+/*******************  Bits definition for FLASH_CRCCR register  ********************/

+#define FLASH_CRCCR_CRC_SECT_Pos             (0U)

+#define FLASH_CRCCR_CRC_SECT_Msk             (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */

+#define FLASH_CRCCR_CRC_SECT                 FLASH_CRCCR_CRC_SECT_Msk            /*!< CRC sector number */

+#define FLASH_CRCCR_CRC_BY_SECT_Pos          (8U)

+#define FLASH_CRCCR_CRC_BY_SECT_Msk          (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */

+#define FLASH_CRCCR_CRC_BY_SECT              FLASH_CRCCR_CRC_BY_SECT_Msk            /*!< CRC sector mode select bit */

+#define FLASH_CRCCR_ADD_SECT_Pos             (9U)

+#define FLASH_CRCCR_ADD_SECT_Msk             (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */

+#define FLASH_CRCCR_ADD_SECT                 FLASH_CRCCR_ADD_SECT_Msk            /*!< CRC sector select bit */

+#define FLASH_CRCCR_CLEAN_SECT_Pos           (10U)

+#define FLASH_CRCCR_CLEAN_SECT_Msk           (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */

+#define FLASH_CRCCR_CLEAN_SECT               FLASH_CRCCR_CLEAN_SECT_Msk            /*!< CRC sector list clear bit */

+#define FLASH_CRCCR_START_CRC_Pos            (16U)

+#define FLASH_CRCCR_START_CRC_Msk            (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */

+#define FLASH_CRCCR_START_CRC                FLASH_CRCCR_START_CRC_Msk            /*!< CRC start bit */

+#define FLASH_CRCCR_CLEAN_CRC_Pos            (17U)

+#define FLASH_CRCCR_CLEAN_CRC_Msk            (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */

+#define FLASH_CRCCR_CLEAN_CRC                FLASH_CRCCR_CLEAN_CRC_Msk            /*!< CRC clear bit */

+#define FLASH_CRCCR_CRC_BURST_Pos            (20U)

+#define FLASH_CRCCR_CRC_BURST_Msk            (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */

+#define FLASH_CRCCR_CRC_BURST                FLASH_CRCCR_CRC_BURST_Msk            /*!< CRC burst size */

+#define FLASH_CRCCR_CRC_BURST_0              (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */

+#define FLASH_CRCCR_CRC_BURST_1              (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */

+#define FLASH_CRCCR_ALL_BANK_Pos             (22U)

+#define FLASH_CRCCR_ALL_BANK_Msk             (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */

+#define FLASH_CRCCR_ALL_BANK                 FLASH_CRCCR_ALL_BANK_Msk            /*!< CRC select bit */

+

+/*******************  Bits definition for FLASH_CRCSADD register  ****************/

+#define FLASH_CRCSADD_CRC_START_ADDR_Pos     (0U)

+#define FLASH_CRCSADD_CRC_START_ADDR_Msk     (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCSADD_CRC_START_ADDR         FLASH_CRCSADD_CRC_START_ADDR_Msk                   /*!< CRC start address */

+

+/*******************  Bits definition for FLASH_CRCEADD register  ****************/

+#define FLASH_CRCEADD_CRC_END_ADDR_Pos       (0U)

+#define FLASH_CRCEADD_CRC_END_ADDR_Msk       (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCEADD_CRC_END_ADDR           FLASH_CRCEADD_CRC_END_ADDR_Msk                   /*!< CRC end address */

+

+/*******************  Bits definition for FLASH_CRCDATA register  ***************/

+#define FLASH_CRCDATA_CRC_DATA_Pos           (0U)

+#define FLASH_CRCDATA_CRC_DATA_Msk           (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCDATA_CRC_DATA               FLASH_CRCDATA_CRC_DATA_Msk                   /*!< CRC result */

+

+/*******************  Bits definition for FLASH_ECC_FA register  *******************/

+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos       (0U)

+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk       (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */

+#define FLASH_ECC_FA_FAIL_ECC_ADDR           FLASH_ECC_FA_FAIL_ECC_ADDR_Msk               /*!< ECC error address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          Flexible Memory Controller                        */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for FMC_BCR1 register  *******************/

+#define FMC_BCR1_CCLKEN_Pos        (20U)

+#define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */

+#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continous clock enable     */

+#define FMC_BCR1_WFDIS_Pos         (21U)

+#define FMC_BCR1_WFDIS_Msk         (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */

+#define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */

+

+#define FMC_BCR1_BMAP_Pos          (24U)

+#define FMC_BCR1_BMAP_Msk          (0x3UL << FMC_BCR1_BMAP_Pos)                /*!< 0x03000000 */

+#define FMC_BCR1_BMAP              FMC_BCR1_BMAP_Msk                           /*!<BMAP[1:0] FMC bank mapping */

+#define FMC_BCR1_BMAP_0            (0x1UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x01000000 */

+#define FMC_BCR1_BMAP_1            (0x2UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x02000000 */

+

+#define FMC_BCR1_FMCEN_Pos         (31U)

+#define FMC_BCR1_FMCEN_Msk         (0x1UL << FMC_BCR1_FMCEN_Pos)               /*!< 0x80000000 */

+#define FMC_BCR1_FMCEN             FMC_BCR1_FMCEN_Msk                          /*!<FMC controller Enable */

+/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/

+#define FMC_BCRx_MBKEN_Pos         (0U)

+#define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */

+#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */

+#define FMC_BCRx_MUXEN_Pos         (1U)

+#define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */

+#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */

+

+#define FMC_BCRx_MTYP_Pos          (2U)

+#define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */

+#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */

+#define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000004 */

+#define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000008 */

+

+#define FMC_BCRx_MWID_Pos          (4U)

+#define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */

+#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */

+#define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000010 */

+#define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000020 */

+

+#define FMC_BCRx_FACCEN_Pos        (6U)

+#define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */

+#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */

+#define FMC_BCRx_BURSTEN_Pos       (8U)

+#define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */

+#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */

+#define FMC_BCRx_WAITPOL_Pos       (9U)

+#define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */

+#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */

+#define FMC_BCRx_WAITCFG_Pos       (11U)

+#define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */

+#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */

+#define FMC_BCRx_WREN_Pos          (12U)

+#define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */

+#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */

+#define FMC_BCRx_WAITEN_Pos        (13U)

+#define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */

+#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */

+#define FMC_BCRx_EXTMOD_Pos        (14U)

+#define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */

+#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */

+#define FMC_BCRx_ASYNCWAIT_Pos     (15U)

+#define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */

+#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */

+

+#define FMC_BCRx_CPSIZE_Pos        (16U)

+#define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */

+#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<PSIZE[2:0] bits CRAM Page Size */

+#define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00010000 */

+#define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00020000 */

+#define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00040000 */

+

+#define FMC_BCRx_CBURSTRW_Pos      (19U)

+#define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */

+#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */

+

+/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/

+#define FMC_BTRx_ADDSET_Pos        (0U)

+#define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */

+#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */

+#define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000001 */

+#define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000002 */

+#define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000004 */

+#define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000008 */

+

+#define FMC_BTRx_ADDHLD_Pos        (4U)

+#define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */

+#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */

+#define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000010 */

+#define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000020 */

+#define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000040 */

+#define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000080 */

+

+#define FMC_BTRx_DATAST_Pos        (8U)

+#define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */

+#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */

+#define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000100 */

+#define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000200 */

+#define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000400 */

+#define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000800 */

+#define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00001000 */

+#define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00002000 */

+#define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00004000 */

+#define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00008000 */

+

+#define FMC_BTRx_BUSTURN_Pos       (16U)

+#define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */

+#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */

+#define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00010000 */

+#define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00020000 */

+#define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00040000 */

+#define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00080000 */

+

+#define FMC_BTRx_CLKDIV_Pos        (20U)

+#define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */

+#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */

+#define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00100000 */

+#define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00200000 */

+#define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00400000 */

+#define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00800000 */

+

+#define FMC_BTRx_DATLAT_Pos        (24U)

+#define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */

+#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */

+#define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x01000000 */

+#define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x02000000 */

+#define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x04000000 */

+#define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x08000000 */

+

+#define FMC_BTRx_ACCMOD_Pos        (28U)

+#define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */

+#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */

+#define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x10000000 */

+#define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x20000000 */

+

+/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/

+#define FMC_BWTRx_ADDSET_Pos       (0U)

+#define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */

+#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */

+#define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000001 */

+#define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000002 */

+#define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000004 */

+#define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000008 */

+

+#define FMC_BWTRx_ADDHLD_Pos       (4U)

+#define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */

+#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */

+#define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000010 */

+#define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000020 */

+#define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000040 */

+#define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000080 */

+

+#define FMC_BWTRx_DATAST_Pos       (8U)

+#define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */

+#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */

+#define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000100 */

+#define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000200 */

+#define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000400 */

+#define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000800 */

+#define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00001000 */

+#define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00002000 */

+#define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00004000 */

+#define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00008000 */

+

+#define FMC_BWTRx_BUSTURN_Pos      (16U)

+#define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */

+#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */

+#define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00010000 */

+#define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00020000 */

+#define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00040000 */

+#define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00080000 */

+

+#define FMC_BWTRx_ACCMOD_Pos       (28U)

+#define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */

+#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */

+#define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x10000000 */

+#define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x20000000 */

+

+/******************  Bit definition for FMC_PCR register  *******************/

+#define FMC_PCR_PWAITEN_Pos        (1U)

+#define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */

+#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */

+#define FMC_PCR_PBKEN_Pos          (2U)

+#define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */

+#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */

+

+#define FMC_PCR_PWID_Pos           (4U)

+#define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */

+#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */

+#define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */

+#define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */

+

+#define FMC_PCR_ECCEN_Pos          (6U)

+#define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */

+#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */

+

+#define FMC_PCR_TCLR_Pos           (9U)

+#define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */

+#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */

+#define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */

+#define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */

+#define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */

+#define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */

+

+#define FMC_PCR_TAR_Pos            (13U)

+#define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */

+#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */

+#define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */

+#define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */

+#define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */

+#define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */

+

+#define FMC_PCR_ECCPS_Pos          (17U)

+#define FMC_PCR_ECCPS_Msk          (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */

+#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */

+#define FMC_PCR_ECCPS_0            (0x1UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */

+#define FMC_PCR_ECCPS_1            (0x2UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */

+#define FMC_PCR_ECCPS_2            (0x4UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */

+

+/*******************  Bit definition for FMC_SR register  *******************/

+#define FMC_SR_IRS_Pos             (0U)

+#define FMC_SR_IRS_Msk             (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */

+#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */

+#define FMC_SR_ILS_Pos             (1U)

+#define FMC_SR_ILS_Msk             (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */

+#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */

+#define FMC_SR_IFS_Pos             (2U)

+#define FMC_SR_IFS_Msk             (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */

+#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */

+#define FMC_SR_IREN_Pos            (3U)

+#define FMC_SR_IREN_Msk            (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */

+#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */

+#define FMC_SR_ILEN_Pos            (4U)

+#define FMC_SR_ILEN_Msk            (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */

+#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */

+#define FMC_SR_IFEN_Pos            (5U)

+#define FMC_SR_IFEN_Msk            (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */

+#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */

+#define FMC_SR_FEMPT_Pos           (6U)

+#define FMC_SR_FEMPT_Msk           (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */

+#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */

+

+/******************  Bit definition for FMC_PMEM register  ******************/

+#define FMC_PMEM_MEMSET_Pos       (0U)

+#define FMC_PMEM_MEMSET_Msk       (0xFFUL << FMC_PMEM_MEMSET_Pos)            /*!< 0x000000FF */

+#define FMC_PMEM_MEMSET           FMC_PMEM_MEMSET_Msk                        /*!<MEMSET[7:0] bits (Common memory setup time) */

+#define FMC_PMEM_MEMSET_0         (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */

+#define FMC_PMEM_MEMSET_1         (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */

+#define FMC_PMEM_MEMSET_2         (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */

+#define FMC_PMEM_MEMSET_3         (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */

+#define FMC_PMEM_MEMSET_4         (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */

+#define FMC_PMEM_MEMSET_5         (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */

+#define FMC_PMEM_MEMSET_6         (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */

+#define FMC_PMEM_MEMSET_7         (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */

+

+#define FMC_PMEM_MEMWAIT_Pos      (8U)

+#define FMC_PMEM_MEMWAIT_Msk      (0xFFUL << FMC_PMEM_MEMWAIT_Pos)           /*!< 0x0000FF00 */

+#define FMC_PMEM_MEMWAIT          FMC_PMEM_MEMWAIT_Msk                       /*!<MEMWAIT[7:0] bits (Common memory wait time) */

+#define FMC_PMEM_MEMWAIT_0        (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */

+#define FMC_PMEM_MEMWAIT_1        (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */

+#define FMC_PMEM_MEMWAIT_2        (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */

+#define FMC_PMEM_MEMWAIT_3        (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */

+#define FMC_PMEM_MEMWAIT_4        (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */

+#define FMC_PMEM_MEMWAIT_5        (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */

+#define FMC_PMEM_MEMWAIT_6        (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */

+#define FMC_PMEM_MEMWAIT_7        (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */

+

+#define FMC_PMEM_MEMHOLD_Pos      (16U)

+#define FMC_PMEM_MEMHOLD_Msk      (0xFFUL << FMC_PMEM_MEMHOLD_Pos)           /*!< 0x00FF0000 */

+#define FMC_PMEM_MEMHOLD          FMC_PMEM_MEMHOLD_Msk                       /*!<MEMHOLD[7:0] bits (Common memory hold time) */

+#define FMC_PMEM_MEMHOLD_0        (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */

+#define FMC_PMEM_MEMHOLD_1        (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */

+#define FMC_PMEM_MEMHOLD_2        (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */

+#define FMC_PMEM_MEMHOLD_3        (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */

+#define FMC_PMEM_MEMHOLD_4        (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */

+#define FMC_PMEM_MEMHOLD_5        (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */

+#define FMC_PMEM_MEMHOLD_6        (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */

+#define FMC_PMEM_MEMHOLD_7        (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */

+

+#define FMC_PMEM_MEMHIZ_Pos       (24U)

+#define FMC_PMEM_MEMHIZ_Msk       (0xFFUL << FMC_PMEM_MEMHIZ_Pos)            /*!< 0xFF000000 */

+#define FMC_PMEM_MEMHIZ           FMC_PMEM_MEMHIZ_Msk                        /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */

+#define FMC_PMEM_MEMHIZ_0         (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */

+#define FMC_PMEM_MEMHIZ_1         (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */

+#define FMC_PMEM_MEMHIZ_2         (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */

+#define FMC_PMEM_MEMHIZ_3         (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */

+#define FMC_PMEM_MEMHIZ_4         (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */

+#define FMC_PMEM_MEMHIZ_5         (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */

+#define FMC_PMEM_MEMHIZ_6         (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */

+#define FMC_PMEM_MEMHIZ_7         (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */

+

+/******************  Bit definition for FMC_PATT register  ******************/

+#define FMC_PATT_ATTSET_Pos       (0U)

+#define FMC_PATT_ATTSET_Msk       (0xFFUL << FMC_PATT_ATTSET_Pos)            /*!< 0x000000FF */

+#define FMC_PATT_ATTSET           FMC_PATT_ATTSET_Msk                        /*!<ATTSET[7:0] bits (Attribute memory setup time) */

+#define FMC_PATT_ATTSET_0         (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */

+#define FMC_PATT_ATTSET_1         (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */

+#define FMC_PATT_ATTSET_2         (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */

+#define FMC_PATT_ATTSET_3         (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */

+#define FMC_PATT_ATTSET_4         (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */

+#define FMC_PATT_ATTSET_5         (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */

+#define FMC_PATT_ATTSET_6         (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */

+#define FMC_PATT_ATTSET_7         (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */

+

+#define FMC_PATT_ATTWAIT_Pos      (8U)

+#define FMC_PATT_ATTWAIT_Msk      (0xFFUL << FMC_PATT_ATTWAIT_Pos)           /*!< 0x0000FF00 */

+#define FMC_PATT_ATTWAIT          FMC_PATT_ATTWAIT_Msk                       /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */

+#define FMC_PATT_ATTWAIT_0        (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */

+#define FMC_PATT_ATTWAIT_1        (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */

+#define FMC_PATT_ATTWAIT_2        (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */

+#define FMC_PATT_ATTWAIT_3        (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */

+#define FMC_PATT_ATTWAIT_4        (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */

+#define FMC_PATT_ATTWAIT_5        (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */

+#define FMC_PATT_ATTWAIT_6        (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */

+#define FMC_PATT_ATTWAIT_7        (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */

+

+#define FMC_PATT_ATTHOLD_Pos      (16U)

+#define FMC_PATT_ATTHOLD_Msk      (0xFFUL << FMC_PATT_ATTHOLD_Pos)           /*!< 0x00FF0000 */

+#define FMC_PATT_ATTHOLD          FMC_PATT_ATTHOLD_Msk                       /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */

+#define FMC_PATT_ATTHOLD_0        (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */

+#define FMC_PATT_ATTHOLD_1        (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */

+#define FMC_PATT_ATTHOLD_2        (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */

+#define FMC_PATT_ATTHOLD_3        (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */

+#define FMC_PATT_ATTHOLD_4        (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */

+#define FMC_PATT_ATTHOLD_5        (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */

+#define FMC_PATT_ATTHOLD_6        (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */

+#define FMC_PATT_ATTHOLD_7        (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */

+

+#define FMC_PATT_ATTHIZ_Pos       (24U)

+#define FMC_PATT_ATTHIZ_Msk       (0xFFUL << FMC_PATT_ATTHIZ_Pos)            /*!< 0xFF000000 */

+#define FMC_PATT_ATTHIZ           FMC_PATT_ATTHIZ_Msk                        /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */

+#define FMC_PATT_ATTHIZ_0         (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */

+#define FMC_PATT_ATTHIZ_1         (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */

+#define FMC_PATT_ATTHIZ_2         (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */

+#define FMC_PATT_ATTHIZ_3         (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */

+#define FMC_PATT_ATTHIZ_4         (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */

+#define FMC_PATT_ATTHIZ_5         (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */

+#define FMC_PATT_ATTHIZ_6         (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */

+#define FMC_PATT_ATTHIZ_7         (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */

+

+/******************  Bit definition for FMC_ECCR3 register  ******************/

+#define FMC_ECCR3_ECC3_Pos         (0U)

+#define FMC_ECCR3_ECC3_Msk         (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)        /*!< 0xFFFFFFFF */

+#define FMC_ECCR3_ECC3             FMC_ECCR3_ECC3_Msk                          /*!<ECC result */

+

+/******************  Bit definition for FMC_SDCRx registers (x=1..4)  *********/

+#define FMC_SDCRx_NC_Pos           (0U)

+#define FMC_SDCRx_NC_Msk           (0x3UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000003 */

+#define FMC_SDCRx_NC               FMC_SDCRx_NC_Msk                            /*!<NC[1:0] bits (Number of column bits) */

+#define FMC_SDCRx_NC_0             (0x1UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000001 */

+#define FMC_SDCRx_NC_1             (0x2UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000002 */

+

+#define FMC_SDCRx_NR_Pos           (2U)

+#define FMC_SDCRx_NR_Msk           (0x3UL << FMC_SDCRx_NR_Pos)                 /*!< 0x0000000C */

+#define FMC_SDCRx_NR               FMC_SDCRx_NR_Msk                            /*!<NR[1:0] bits (Number of row bits) */

+#define FMC_SDCRx_NR_0             (0x1UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000004 */

+#define FMC_SDCRx_NR_1             (0x2UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000008 */

+

+#define FMC_SDCRx_MWID_Pos         (4U)

+#define FMC_SDCRx_MWID_Msk         (0x3UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000030 */

+#define FMC_SDCRx_MWID             FMC_SDCRx_MWID_Msk                          /*!<NR[1:0] bits (Number of row bits) */

+#define FMC_SDCRx_MWID_0           (0x1UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000010 */

+#define FMC_SDCRx_MWID_1           (0x2UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000020 */

+

+#define FMC_SDCRx_NB_Pos           (6U)

+#define FMC_SDCRx_NB_Msk           (0x1UL << FMC_SDCRx_NB_Pos)                 /*!< 0x00000040 */

+#define FMC_SDCRx_NB               FMC_SDCRx_NB_Msk                            /*!<Number of internal bank */

+

+#define FMC_SDCRx_CAS_Pos          (7U)

+#define FMC_SDCRx_CAS_Msk          (0x3UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000180 */

+#define FMC_SDCRx_CAS              FMC_SDCRx_CAS_Msk                           /*!<CAS[1:0] bits (CAS latency) */

+#define FMC_SDCRx_CAS_0            (0x1UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000080 */

+#define FMC_SDCRx_CAS_1            (0x2UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000100 */

+

+#define FMC_SDCRx_WP_Pos           (9U)

+#define FMC_SDCRx_WP_Msk           (0x1UL << FMC_SDCRx_WP_Pos)                 /*!< 0x00000200 */

+#define FMC_SDCRx_WP               FMC_SDCRx_WP_Msk                            /*!<Write protection */

+

+#define FMC_SDCRx_SDCLK_Pos        (10U)

+#define FMC_SDCRx_SDCLK_Msk        (0x3UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000C00 */

+#define FMC_SDCRx_SDCLK            FMC_SDCRx_SDCLK_Msk                         /*!<SDRAM clock configuration */

+#define FMC_SDCRx_SDCLK_0          (0x1UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000400 */

+#define FMC_SDCRx_SDCLK_1          (0x2UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000800 */

+

+#define FMC_SDCRx_RBURST_Pos       (12U)

+#define FMC_SDCRx_RBURST_Msk       (0x1UL << FMC_SDCRx_RBURST_Pos)             /*!< 0x00001000 */

+#define FMC_SDCRx_RBURST           FMC_SDCRx_RBURST_Msk                        /*!<Read burst */

+

+#define FMC_SDCRx_RPIPE_Pos        (13U)

+#define FMC_SDCRx_RPIPE_Msk        (0x3UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00006000 */

+#define FMC_SDCRx_RPIPE            FMC_SDCRx_RPIPE_Msk                         /*!<Write protection */

+#define FMC_SDCRx_RPIPE_0          (0x1UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00002000 */

+#define FMC_SDCRx_RPIPE_1          (0x2UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00004000 */

+

+/******************  Bit definition for FMC_SDTRx(1,2) register  ******************/

+#define FMC_SDTRx_TMRD_Pos         (0U)

+#define FMC_SDTRx_TMRD_Msk         (0xFUL << FMC_SDTRx_TMRD_Pos)               /*!< 0x0000000F */

+#define FMC_SDTRx_TMRD             FMC_SDTRx_TMRD_Msk                          /*!<TMRD[3:0] bits (Load mode register to active) */

+#define FMC_SDTRx_TMRD_0           (0x1UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000001 */

+#define FMC_SDTRx_TMRD_1           (0x2UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000002 */

+#define FMC_SDTRx_TMRD_2           (0x4UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000004 */

+#define FMC_SDTRx_TMRD_3           (0x8UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000008 */

+

+#define FMC_SDTRx_TXSR_Pos         (4U)

+#define FMC_SDTRx_TXSR_Msk         (0xFUL << FMC_SDTRx_TXSR_Pos)               /*!< 0x000000F0 */

+#define FMC_SDTRx_TXSR             FMC_SDTRx_TXSR_Msk                          /*!<TXSR[3:0] bits (Exit self refresh) */

+#define FMC_SDTRx_TXSR_0           (0x1UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000010 */

+#define FMC_SDTRx_TXSR_1           (0x2UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000020 */

+#define FMC_SDTRx_TXSR_2           (0x4UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000040 */

+#define FMC_SDTRx_TXSR_3           (0x8UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000080 */

+

+#define FMC_SDTRx_TRAS_Pos         (8U)

+#define FMC_SDTRx_TRAS_Msk         (0xFUL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000F00 */

+#define FMC_SDTRx_TRAS             FMC_SDTRx_TRAS_Msk                          /*!<TRAS[3:0] bits (Self refresh time) */

+#define FMC_SDTRx_TRAS_0           (0x1UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000100 */

+#define FMC_SDTRx_TRAS_1           (0x2UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000200 */

+#define FMC_SDTRx_TRAS_2           (0x4UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000400 */

+#define FMC_SDTRx_TRAS_3           (0x8UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000800 */

+

+#define FMC_SDTRx_TRC_Pos          (12U)

+#define FMC_SDTRx_TRC_Msk          (0xFUL << FMC_SDTRx_TRC_Pos)                /*!< 0x0000F000 */

+#define FMC_SDTRx_TRC              FMC_SDTRx_TRC_Msk                           /*!<TRC[2:0] bits (Row cycle delay) */

+#define FMC_SDTRx_TRC_0            (0x1UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00001000 */

+#define FMC_SDTRx_TRC_1            (0x2UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00002000 */

+#define FMC_SDTRx_TRC_2            (0x4UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00004000 */

+

+#define FMC_SDTRx_TWR_Pos          (16U)

+#define FMC_SDTRx_TWR_Msk          (0xFUL << FMC_SDTRx_TWR_Pos)                /*!< 0x000F0000 */

+#define FMC_SDTRx_TWR              FMC_SDTRx_TWR_Msk                           /*!<TRC[2:0] bits (Write recovery delay) */

+#define FMC_SDTRx_TWR_0            (0x1UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00010000 */

+#define FMC_SDTRx_TWR_1            (0x2UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00020000 */

+#define FMC_SDTRx_TWR_2            (0x4UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00040000 */

+

+#define FMC_SDTRx_TRP_Pos          (20U)

+#define FMC_SDTRx_TRP_Msk          (0xFUL << FMC_SDTRx_TRP_Pos)                /*!< 0x00F00000 */

+#define FMC_SDTRx_TRP              FMC_SDTRx_TRP_Msk                           /*!<TRP[2:0] bits (Row precharge delay) */

+#define FMC_SDTRx_TRP_0            (0x1UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00100000 */

+#define FMC_SDTRx_TRP_1            (0x2UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00200000 */

+#define FMC_SDTRx_TRP_2            (0x4UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00400000 */

+

+#define FMC_SDTRx_TRCD_Pos         (24U)

+#define FMC_SDTRx_TRCD_Msk         (0xFUL << FMC_SDTRx_TRCD_Pos)               /*!< 0x0F000000 */

+#define FMC_SDTRx_TRCD             FMC_SDTRx_TRCD_Msk                          /*!<TRP[2:0] bits (Row to column delay) */

+#define FMC_SDTRx_TRCD_0           (0x1UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x01000000 */

+#define FMC_SDTRx_TRCD_1           (0x2UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x02000000 */

+#define FMC_SDTRx_TRCD_2           (0x4UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x04000000 */

+

+/******************  Bit definition for FMC_SDCMR register  ******************/

+#define FMC_SDCMR_MODE_Pos         (0U)

+#define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */

+#define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */

+#define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */

+#define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */

+#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */

+

+#define FMC_SDCMR_CTB2_Pos         (3U)

+#define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */

+#define FMC_SDCMR_CTB2             FMC_SDCMR_CTB2_Msk                          /*!<Command target 2 */

+

+#define FMC_SDCMR_CTB1_Pos         (4U)

+#define FMC_SDCMR_CTB1_Msk         (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */

+#define FMC_SDCMR_CTB1             FMC_SDCMR_CTB1_Msk                          /*!<Command target 1 */

+

+#define FMC_SDCMR_NRFS_Pos         (5U)

+#define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */

+#define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!<NRFS[3:0] bits (Number of auto-refresh) */

+#define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000020 */

+#define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000040 */

+#define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000080 */

+#define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000100 */

+

+#define FMC_SDCMR_MRD_Pos          (9U)

+#define FMC_SDCMR_MRD_Msk          (0x1FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */

+#define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!<MRD[12:0] bits (Mode register definition) */

+

+/******************  Bit definition for FMC_SDRTR register  ******************/

+#define FMC_SDRTR_CRE_Pos          (0U)

+#define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */

+#define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!<Clear refresh error flag */

+

+#define FMC_SDRTR_COUNT_Pos        (1U)

+#define FMC_SDRTR_COUNT_Msk        (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */

+#define FMC_SDRTR_COUNT            FMC_SDRTR_COUNT_Msk                         /*!<COUNT[12:0] bits (Refresh timer count) */

+

+#define FMC_SDRTR_REIE_Pos         (14U)

+#define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */

+#define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!<RES interupt enable */

+

+/******************  Bit definition for FMC_SDSR register  ******************/

+#define FMC_SDSR_RE_Pos            (0U)

+#define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */

+#define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!<Refresh error flag */

+

+#define FMC_SDSR_MODES1_Pos        (1U)

+#define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */

+#define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!<MODES1[1:0]bits (Status mode for bank 1) */

+#define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000002 */

+#define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000004 */

+

+#define FMC_SDSR_MODES2_Pos        (3U)

+#define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */

+#define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!<MODES2[1:0]bits (Status mode for bank 2) */

+#define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000008 */

+#define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000010 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            General Purpose I/O                             */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bits definition for GPIO_MODER register  *****************/

+#define GPIO_MODER_MODE0_Pos           (0U)

+#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */

+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk

+#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */

+#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */

+

+#define GPIO_MODER_MODE1_Pos           (2U)

+#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */

+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk

+#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */

+#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */

+

+#define GPIO_MODER_MODE2_Pos           (4U)

+#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */

+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk

+#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */

+#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */

+

+#define GPIO_MODER_MODE3_Pos           (6U)

+#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */

+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk

+#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */

+#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */

+

+#define GPIO_MODER_MODE4_Pos           (8U)

+#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */

+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk

+#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */

+#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */

+

+#define GPIO_MODER_MODE5_Pos           (10U)

+#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */

+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk

+#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */

+#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */

+

+#define GPIO_MODER_MODE6_Pos           (12U)

+#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */

+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk

+#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */

+#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */

+

+#define GPIO_MODER_MODE7_Pos           (14U)

+#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */

+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk

+#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */

+#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */

+

+#define GPIO_MODER_MODE8_Pos           (16U)

+#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */

+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk

+#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */

+#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */

+

+#define GPIO_MODER_MODE9_Pos           (18U)

+#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */

+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk

+#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */

+#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */

+

+#define GPIO_MODER_MODE10_Pos          (20U)

+#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */

+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk

+#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */

+#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */

+

+#define GPIO_MODER_MODE11_Pos          (22U)

+#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */

+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk

+#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */

+#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */

+

+#define GPIO_MODER_MODE12_Pos          (24U)

+#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */

+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk

+#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */

+#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */

+

+#define GPIO_MODER_MODE13_Pos          (26U)

+#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */

+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk

+#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */

+#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */

+

+#define GPIO_MODER_MODE14_Pos          (28U)

+#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */

+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk

+#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */

+#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */

+

+#define GPIO_MODER_MODE15_Pos          (30U)

+#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */

+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk

+#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */

+#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_OTYPER register  ****************/

+#define GPIO_OTYPER_OT0_Pos            (0U)

+#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */

+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk

+#define GPIO_OTYPER_OT1_Pos            (1U)

+#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */

+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk

+#define GPIO_OTYPER_OT2_Pos            (2U)

+#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */

+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk

+#define GPIO_OTYPER_OT3_Pos            (3U)

+#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */

+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk

+#define GPIO_OTYPER_OT4_Pos            (4U)

+#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */

+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk

+#define GPIO_OTYPER_OT5_Pos            (5U)

+#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */

+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk

+#define GPIO_OTYPER_OT6_Pos            (6U)

+#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */

+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk

+#define GPIO_OTYPER_OT7_Pos            (7U)

+#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */

+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk

+#define GPIO_OTYPER_OT8_Pos            (8U)

+#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */

+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk

+#define GPIO_OTYPER_OT9_Pos            (9U)

+#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */

+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk

+#define GPIO_OTYPER_OT10_Pos           (10U)

+#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */

+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk

+#define GPIO_OTYPER_OT11_Pos           (11U)

+#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */

+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk

+#define GPIO_OTYPER_OT12_Pos           (12U)

+#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */

+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk

+#define GPIO_OTYPER_OT13_Pos           (13U)

+#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */

+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk

+#define GPIO_OTYPER_OT14_Pos           (14U)

+#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */

+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk

+#define GPIO_OTYPER_OT15_Pos           (15U)

+#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */

+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk

+

+/******************  Bits definition for GPIO_OSPEEDR register  ***************/

+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)

+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */

+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk

+#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */

+#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */

+

+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)

+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */

+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk

+#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */

+#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */

+

+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)

+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */

+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk

+#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */

+#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */

+

+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)

+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */

+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk

+#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */

+#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */

+

+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)

+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */

+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk

+#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */

+#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */

+

+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)

+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */

+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk

+#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */

+#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */

+

+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)

+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */

+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk

+#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */

+#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */

+

+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)

+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */

+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk

+#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */

+#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */

+

+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)

+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */

+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk

+#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */

+#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */

+

+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)

+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */

+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk

+#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */

+#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */

+

+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)

+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */

+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk

+#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */

+#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */

+

+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)

+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */

+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk

+#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */

+#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */

+

+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)

+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */

+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk

+#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */

+#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */

+

+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)

+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */

+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk

+#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */

+#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */

+

+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)

+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */

+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk

+#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */

+#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */

+

+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)

+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */

+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk

+#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */

+#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_PUPDR register  *****************/

+#define GPIO_PUPDR_PUPD0_Pos           (0U)

+#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */

+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk

+#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */

+#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */

+

+#define GPIO_PUPDR_PUPD1_Pos           (2U)

+#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */

+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk

+#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */

+#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */

+

+#define GPIO_PUPDR_PUPD2_Pos           (4U)

+#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */

+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk

+#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */

+#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */

+

+#define GPIO_PUPDR_PUPD3_Pos           (6U)

+#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */

+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk

+#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */

+#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */

+

+#define GPIO_PUPDR_PUPD4_Pos           (8U)

+#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */

+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk

+#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */

+#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */

+

+#define GPIO_PUPDR_PUPD5_Pos           (10U)

+#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */

+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk

+#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */

+#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */

+

+#define GPIO_PUPDR_PUPD6_Pos           (12U)

+#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */

+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk

+#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */

+#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */

+

+#define GPIO_PUPDR_PUPD7_Pos           (14U)

+#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */

+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk

+#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */

+#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */

+

+#define GPIO_PUPDR_PUPD8_Pos           (16U)

+#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */

+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk

+#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */

+#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */

+

+#define GPIO_PUPDR_PUPD9_Pos           (18U)

+#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */

+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk

+#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */

+#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */

+

+#define GPIO_PUPDR_PUPD10_Pos          (20U)

+#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */

+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk

+#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */

+#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */

+

+#define GPIO_PUPDR_PUPD11_Pos          (22U)

+#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */

+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk

+#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */

+#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */

+

+#define GPIO_PUPDR_PUPD12_Pos          (24U)

+#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */

+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk

+#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */

+#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */

+

+#define GPIO_PUPDR_PUPD13_Pos          (26U)

+#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */

+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk

+#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */

+#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */

+

+#define GPIO_PUPDR_PUPD14_Pos          (28U)

+#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */

+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk

+#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */

+#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */

+

+#define GPIO_PUPDR_PUPD15_Pos          (30U)

+#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */

+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk

+#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */

+#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_IDR register  *******************/

+#define GPIO_IDR_ID0_Pos               (0U)

+#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */

+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk

+#define GPIO_IDR_ID1_Pos               (1U)

+#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */

+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk

+#define GPIO_IDR_ID2_Pos               (2U)

+#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */

+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk

+#define GPIO_IDR_ID3_Pos               (3U)

+#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */

+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk

+#define GPIO_IDR_ID4_Pos               (4U)

+#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */

+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk

+#define GPIO_IDR_ID5_Pos               (5U)

+#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */

+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk

+#define GPIO_IDR_ID6_Pos               (6U)

+#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */

+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk

+#define GPIO_IDR_ID7_Pos               (7U)

+#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */

+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk

+#define GPIO_IDR_ID8_Pos               (8U)

+#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */

+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk

+#define GPIO_IDR_ID9_Pos               (9U)

+#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */

+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk

+#define GPIO_IDR_ID10_Pos              (10U)

+#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */

+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk

+#define GPIO_IDR_ID11_Pos              (11U)

+#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */

+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk

+#define GPIO_IDR_ID12_Pos              (12U)

+#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */

+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk

+#define GPIO_IDR_ID13_Pos              (13U)

+#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */

+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk

+#define GPIO_IDR_ID14_Pos              (14U)

+#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */

+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk

+#define GPIO_IDR_ID15_Pos              (15U)

+#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */

+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk

+

+/******************  Bits definition for GPIO_ODR register  *******************/

+#define GPIO_ODR_OD0_Pos               (0U)

+#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */

+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk

+#define GPIO_ODR_OD1_Pos               (1U)

+#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */

+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk

+#define GPIO_ODR_OD2_Pos               (2U)

+#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */

+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk

+#define GPIO_ODR_OD3_Pos               (3U)

+#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */

+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk

+#define GPIO_ODR_OD4_Pos               (4U)

+#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */

+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk

+#define GPIO_ODR_OD5_Pos               (5U)

+#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */

+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk

+#define GPIO_ODR_OD6_Pos               (6U)

+#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */

+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk

+#define GPIO_ODR_OD7_Pos               (7U)

+#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */

+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk

+#define GPIO_ODR_OD8_Pos               (8U)

+#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */

+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk

+#define GPIO_ODR_OD9_Pos               (9U)

+#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */

+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk

+#define GPIO_ODR_OD10_Pos              (10U)

+#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */

+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk

+#define GPIO_ODR_OD11_Pos              (11U)

+#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */

+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk

+#define GPIO_ODR_OD12_Pos              (12U)

+#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */

+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk

+#define GPIO_ODR_OD13_Pos              (13U)

+#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */

+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk

+#define GPIO_ODR_OD14_Pos              (14U)

+#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */

+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk

+#define GPIO_ODR_OD15_Pos              (15U)

+#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */

+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk

+

+/******************  Bits definition for GPIO_BSRR register  ******************/

+#define GPIO_BSRR_BS0_Pos              (0U)

+#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */

+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk

+#define GPIO_BSRR_BS1_Pos              (1U)

+#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */

+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk

+#define GPIO_BSRR_BS2_Pos              (2U)

+#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */

+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk

+#define GPIO_BSRR_BS3_Pos              (3U)

+#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */

+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk

+#define GPIO_BSRR_BS4_Pos              (4U)

+#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */

+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk

+#define GPIO_BSRR_BS5_Pos              (5U)

+#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */

+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk

+#define GPIO_BSRR_BS6_Pos              (6U)

+#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */

+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk

+#define GPIO_BSRR_BS7_Pos              (7U)

+#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */

+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk

+#define GPIO_BSRR_BS8_Pos              (8U)

+#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */

+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk

+#define GPIO_BSRR_BS9_Pos              (9U)

+#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */

+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk

+#define GPIO_BSRR_BS10_Pos             (10U)

+#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */

+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk

+#define GPIO_BSRR_BS11_Pos             (11U)

+#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */

+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk

+#define GPIO_BSRR_BS12_Pos             (12U)

+#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */

+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk

+#define GPIO_BSRR_BS13_Pos             (13U)

+#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */

+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk

+#define GPIO_BSRR_BS14_Pos             (14U)

+#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */

+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk

+#define GPIO_BSRR_BS15_Pos             (15U)

+#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */

+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk

+#define GPIO_BSRR_BR0_Pos              (16U)

+#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */

+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk

+#define GPIO_BSRR_BR1_Pos              (17U)

+#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */

+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk

+#define GPIO_BSRR_BR2_Pos              (18U)

+#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */

+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk

+#define GPIO_BSRR_BR3_Pos              (19U)

+#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */

+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk

+#define GPIO_BSRR_BR4_Pos              (20U)

+#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */

+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk

+#define GPIO_BSRR_BR5_Pos              (21U)

+#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */

+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk

+#define GPIO_BSRR_BR6_Pos              (22U)

+#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */

+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk

+#define GPIO_BSRR_BR7_Pos              (23U)

+#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */

+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk

+#define GPIO_BSRR_BR8_Pos              (24U)

+#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */

+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk

+#define GPIO_BSRR_BR9_Pos              (25U)

+#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */

+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk

+#define GPIO_BSRR_BR10_Pos             (26U)

+#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */

+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk

+#define GPIO_BSRR_BR11_Pos             (27U)

+#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */

+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk

+#define GPIO_BSRR_BR12_Pos             (28U)

+#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */

+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk

+#define GPIO_BSRR_BR13_Pos             (29U)

+#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */

+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk

+#define GPIO_BSRR_BR14_Pos             (30U)

+#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */

+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk

+#define GPIO_BSRR_BR15_Pos             (31U)

+#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */

+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk

+

+/****************** Bit definition for GPIO_LCKR register *********************/

+#define GPIO_LCKR_LCK0_Pos             (0U)

+#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */

+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk

+#define GPIO_LCKR_LCK1_Pos             (1U)

+#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */

+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk

+#define GPIO_LCKR_LCK2_Pos             (2U)

+#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */

+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk

+#define GPIO_LCKR_LCK3_Pos             (3U)

+#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */

+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk

+#define GPIO_LCKR_LCK4_Pos             (4U)

+#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */

+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk

+#define GPIO_LCKR_LCK5_Pos             (5U)

+#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */

+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk

+#define GPIO_LCKR_LCK6_Pos             (6U)

+#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */

+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk

+#define GPIO_LCKR_LCK7_Pos             (7U)

+#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */

+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk

+#define GPIO_LCKR_LCK8_Pos             (8U)

+#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */

+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk

+#define GPIO_LCKR_LCK9_Pos             (9U)

+#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */

+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk

+#define GPIO_LCKR_LCK10_Pos            (10U)

+#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */

+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk

+#define GPIO_LCKR_LCK11_Pos            (11U)

+#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */

+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk

+#define GPIO_LCKR_LCK12_Pos            (12U)

+#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */

+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk

+#define GPIO_LCKR_LCK13_Pos            (13U)

+#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */

+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk

+#define GPIO_LCKR_LCK14_Pos            (14U)

+#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */

+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk

+#define GPIO_LCKR_LCK15_Pos            (15U)

+#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */

+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk

+#define GPIO_LCKR_LCKK_Pos             (16U)

+#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */

+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk

+

+/****************** Bit definition for GPIO_AFRL register  ********************/

+#define GPIO_AFRL_AFSEL0_Pos           (0U)

+#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */

+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk

+#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */

+#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */

+#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */

+#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */

+#define GPIO_AFRL_AFSEL1_Pos           (4U)

+#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */

+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk

+#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */

+#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */

+#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */

+#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */

+#define GPIO_AFRL_AFSEL2_Pos           (8U)

+#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */

+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk

+#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */

+#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */

+#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */

+#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */

+#define GPIO_AFRL_AFSEL3_Pos           (12U)

+#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */

+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk

+#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */

+#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */

+#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */

+#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */

+#define GPIO_AFRL_AFSEL4_Pos           (16U)

+#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */

+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk

+#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */

+#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */

+#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */

+#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */

+#define GPIO_AFRL_AFSEL5_Pos           (20U)

+#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */

+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk

+#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */

+#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */

+#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */

+#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */

+#define GPIO_AFRL_AFSEL6_Pos           (24U)

+#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */

+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk

+#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */

+#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */

+#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */

+#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */

+#define GPIO_AFRL_AFSEL7_Pos           (28U)

+#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */

+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk

+#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */

+#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */

+#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */

+#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */

+

+/* Legacy defines */

+#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0

+#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1

+#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2

+#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3

+#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4

+#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5

+#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6

+#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7

+

+/****************** Bit definition for GPIO_AFRH register  ********************/

+#define GPIO_AFRH_AFSEL8_Pos           (0U)

+#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */

+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk

+#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */

+#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */

+#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */

+#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */

+#define GPIO_AFRH_AFSEL9_Pos           (4U)

+#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */

+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk

+#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */

+#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */

+#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */

+#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */

+#define GPIO_AFRH_AFSEL10_Pos          (8U)

+#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */

+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk

+#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */

+#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */

+#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */

+#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */

+#define GPIO_AFRH_AFSEL11_Pos          (12U)

+#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */

+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk

+#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */

+#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */

+#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */

+#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */

+#define GPIO_AFRH_AFSEL12_Pos          (16U)

+#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */

+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk

+#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */

+#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */

+#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */

+#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */

+#define GPIO_AFRH_AFSEL13_Pos          (20U)

+#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */

+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk

+#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */

+#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */

+#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */

+#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */

+#define GPIO_AFRH_AFSEL14_Pos          (24U)

+#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */

+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk

+#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */

+#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */

+#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */

+#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */

+#define GPIO_AFRH_AFSEL15_Pos          (28U)

+#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */

+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk

+#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */

+#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */

+#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */

+#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */

+

+/* Legacy defines */

+#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8

+#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9

+#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10

+#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11

+#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12

+#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13

+#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14

+#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15

+

+/******************************************************************************/

+/*                                                                            */

+/*                        HSEM HW Semaphore                                   */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for HSEM_R register  ********************/

+#define HSEM_R_PROCID_Pos         (0U)

+#define HSEM_R_PROCID_Msk         (0xFFUL << HSEM_R_PROCID_Pos)                /*!< 0x000000FF */

+#define HSEM_R_PROCID             HSEM_R_PROCID_Msk                            /*!<Semaphore ProcessID */

+#define HSEM_R_COREID_Pos         (8U)

+#define HSEM_R_COREID_Msk         (0xFFUL << HSEM_R_COREID_Pos)                /*!< 0x0000FF00 */

+#define HSEM_R_COREID             HSEM_R_COREID_Msk                            /*!<Semaphore CoreID.   */

+#define HSEM_R_LOCK_Pos           (31U)

+#define HSEM_R_LOCK_Msk           (0x1UL << HSEM_R_LOCK_Pos)                   /*!< 0x80000000 */

+#define HSEM_R_LOCK               HSEM_R_LOCK_Msk                              /*!<Lock indication.    */

+

+/********************  Bit definition for HSEM_RLR register  ******************/

+#define HSEM_RLR_PROCID_Pos       (0U)

+#define HSEM_RLR_PROCID_Msk       (0xFFUL << HSEM_RLR_PROCID_Pos)              /*!< 0x000000FF */

+#define HSEM_RLR_PROCID           HSEM_RLR_PROCID_Msk                          /*!<Semaphore ProcessID */

+#define HSEM_RLR_COREID_Pos       (8U)

+#define HSEM_RLR_COREID_Msk       (0xFFUL << HSEM_RLR_COREID_Pos)              /*!< 0x0000FF00 */

+#define HSEM_RLR_COREID           HSEM_RLR_COREID_Msk                          /*!<Semaphore CoreID.   */

+#define HSEM_RLR_LOCK_Pos         (31U)

+#define HSEM_RLR_LOCK_Msk         (0x1UL << HSEM_RLR_LOCK_Pos)                 /*!< 0x80000000 */

+#define HSEM_RLR_LOCK             HSEM_RLR_LOCK_Msk                            /*!<Lock indication.    */

+

+/********************  Bit definition for HSEM_C1IER register  *****************/

+#define HSEM_C1IER_ISE0_Pos       (0U)

+#define HSEM_C1IER_ISE0_Msk       (0x1UL << HSEM_C1IER_ISE0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1IER_ISE0           HSEM_C1IER_ISE0_Msk                          /*!<semaphore 0 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE1_Pos       (1U)

+#define HSEM_C1IER_ISE1_Msk       (0x1UL << HSEM_C1IER_ISE1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1IER_ISE1           HSEM_C1IER_ISE1_Msk                          /*!<semaphore 1 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE2_Pos       (2U)

+#define HSEM_C1IER_ISE2_Msk       (0x1UL << HSEM_C1IER_ISE2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1IER_ISE2           HSEM_C1IER_ISE2_Msk                          /*!<semaphore 2 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE3_Pos       (3U)

+#define HSEM_C1IER_ISE3_Msk       (0x1UL << HSEM_C1IER_ISE3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1IER_ISE3           HSEM_C1IER_ISE3_Msk                          /*!<semaphore 3 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE4_Pos       (4U)

+#define HSEM_C1IER_ISE4_Msk       (0x1UL << HSEM_C1IER_ISE4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1IER_ISE4           HSEM_C1IER_ISE4_Msk                          /*!<semaphore 4 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE5_Pos       (5U)

+#define HSEM_C1IER_ISE5_Msk       (0x1UL << HSEM_C1IER_ISE5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1IER_ISE5           HSEM_C1IER_ISE5_Msk                          /*!<semaphore 5 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE6_Pos       (6U)

+#define HSEM_C1IER_ISE6_Msk       (0x1UL << HSEM_C1IER_ISE6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1IER_ISE6           HSEM_C1IER_ISE6_Msk                          /*!<semaphore 6 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE7_Pos       (7U)

+#define HSEM_C1IER_ISE7_Msk       (0x1UL << HSEM_C1IER_ISE7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1IER_ISE7           HSEM_C1IER_ISE7_Msk                          /*!<semaphore 7 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE8_Pos       (8U)

+#define HSEM_C1IER_ISE8_Msk       (0x1UL << HSEM_C1IER_ISE8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1IER_ISE8           HSEM_C1IER_ISE8_Msk                          /*!<semaphore 8 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE9_Pos       (9U)

+#define HSEM_C1IER_ISE9_Msk       (0x1UL << HSEM_C1IER_ISE9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1IER_ISE9           HSEM_C1IER_ISE9_Msk                          /*!<semaphore 9 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE10_Pos      (10U)

+#define HSEM_C1IER_ISE10_Msk      (0x1UL << HSEM_C1IER_ISE10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1IER_ISE10          HSEM_C1IER_ISE10_Msk                         /*!<semaphore 10 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE11_Pos      (11U)

+#define HSEM_C1IER_ISE11_Msk      (0x1UL << HSEM_C1IER_ISE11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1IER_ISE11          HSEM_C1IER_ISE11_Msk                         /*!<semaphore 11 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE12_Pos      (12U)

+#define HSEM_C1IER_ISE12_Msk      (0x1UL << HSEM_C1IER_ISE12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1IER_ISE12          HSEM_C1IER_ISE12_Msk                         /*!<semaphore 12 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE13_Pos      (13U)

+#define HSEM_C1IER_ISE13_Msk      (0x1UL << HSEM_C1IER_ISE13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1IER_ISE13          HSEM_C1IER_ISE13_Msk                         /*!<semaphore 13 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE14_Pos      (14U)

+#define HSEM_C1IER_ISE14_Msk      (0x1UL << HSEM_C1IER_ISE14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1IER_ISE14          HSEM_C1IER_ISE14_Msk                         /*!<semaphore 14 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE15_Pos      (15U)

+#define HSEM_C1IER_ISE15_Msk      (0x1UL << HSEM_C1IER_ISE15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1IER_ISE15          HSEM_C1IER_ISE15_Msk                         /*!<semaphore 15 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE16_Pos      (16U)

+#define HSEM_C1IER_ISE16_Msk      (0x1UL << HSEM_C1IER_ISE16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1IER_ISE16          HSEM_C1IER_ISE16_Msk                         /*!<semaphore 16 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE17_Pos      (17U)

+#define HSEM_C1IER_ISE17_Msk      (0x1UL << HSEM_C1IER_ISE17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1IER_ISE17          HSEM_C1IER_ISE17_Msk                         /*!<semaphore 17 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE18_Pos      (18U)

+#define HSEM_C1IER_ISE18_Msk      (0x1UL << HSEM_C1IER_ISE18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1IER_ISE18          HSEM_C1IER_ISE18_Msk                         /*!<semaphore 18 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE19_Pos      (19U)

+#define HSEM_C1IER_ISE19_Msk      (0x1UL << HSEM_C1IER_ISE19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1IER_ISE19          HSEM_C1IER_ISE19_Msk                         /*!<semaphore 19 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE20_Pos      (20U)

+#define HSEM_C1IER_ISE20_Msk      (0x1UL << HSEM_C1IER_ISE20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1IER_ISE20          HSEM_C1IER_ISE20_Msk                         /*!<semaphore 20 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE21_Pos      (21U)

+#define HSEM_C1IER_ISE21_Msk      (0x1UL << HSEM_C1IER_ISE21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1IER_ISE21          HSEM_C1IER_ISE21_Msk                         /*!<semaphore 21 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE22_Pos      (22U)

+#define HSEM_C1IER_ISE22_Msk      (0x1UL << HSEM_C1IER_ISE22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1IER_ISE22          HSEM_C1IER_ISE22_Msk                         /*!<semaphore 22 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE23_Pos      (23U)

+#define HSEM_C1IER_ISE23_Msk      (0x1UL << HSEM_C1IER_ISE23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1IER_ISE23          HSEM_C1IER_ISE23_Msk                         /*!<semaphore 23 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE24_Pos      (24U)

+#define HSEM_C1IER_ISE24_Msk      (0x1UL << HSEM_C1IER_ISE24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1IER_ISE24          HSEM_C1IER_ISE24_Msk                         /*!<semaphore 24 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE25_Pos      (25U)

+#define HSEM_C1IER_ISE25_Msk      (0x1UL << HSEM_C1IER_ISE25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1IER_ISE25          HSEM_C1IER_ISE25_Msk                         /*!<semaphore 25 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE26_Pos      (26U)

+#define HSEM_C1IER_ISE26_Msk      (0x1UL << HSEM_C1IER_ISE26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1IER_ISE26          HSEM_C1IER_ISE26_Msk                         /*!<semaphore 26 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE27_Pos      (27U)

+#define HSEM_C1IER_ISE27_Msk      (0x1UL << HSEM_C1IER_ISE27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1IER_ISE27          HSEM_C1IER_ISE27_Msk                         /*!<semaphore 27 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE28_Pos      (28U)

+#define HSEM_C1IER_ISE28_Msk      (0x1UL << HSEM_C1IER_ISE28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1IER_ISE28          HSEM_C1IER_ISE28_Msk                         /*!<semaphore 28 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE29_Pos      (29U)

+#define HSEM_C1IER_ISE29_Msk      (0x1UL << HSEM_C1IER_ISE29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1IER_ISE29          HSEM_C1IER_ISE29_Msk                         /*!<semaphore 29 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE30_Pos      (30U)

+#define HSEM_C1IER_ISE30_Msk      (0x1UL << HSEM_C1IER_ISE30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1IER_ISE30          HSEM_C1IER_ISE30_Msk                         /*!<semaphore 30 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE31_Pos      (31U)

+#define HSEM_C1IER_ISE31_Msk      (0x1UL << HSEM_C1IER_ISE31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1IER_ISE31          HSEM_C1IER_ISE31_Msk                         /*!<semaphore 31 interrupt 0 enable bit. */

+

+/********************  Bit definition for HSEM_C1ICR register  *****************/

+#define HSEM_C1ICR_ISC0_Pos       (0U)

+#define HSEM_C1ICR_ISC0_Msk       (0x1UL << HSEM_C1ICR_ISC0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1ICR_ISC0           HSEM_C1ICR_ISC0_Msk                          /*!<semaphore 0 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC1_Pos       (1U)

+#define HSEM_C1ICR_ISC1_Msk       (0x1UL << HSEM_C1ICR_ISC1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1ICR_ISC1           HSEM_C1ICR_ISC1_Msk                          /*!<semaphore 1 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC2_Pos       (2U)

+#define HSEM_C1ICR_ISC2_Msk       (0x1UL << HSEM_C1ICR_ISC2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1ICR_ISC2           HSEM_C1ICR_ISC2_Msk                          /*!<semaphore 2 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC3_Pos       (3U)

+#define HSEM_C1ICR_ISC3_Msk       (0x1UL << HSEM_C1ICR_ISC3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1ICR_ISC3           HSEM_C1ICR_ISC3_Msk                          /*!<semaphore 3 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC4_Pos       (4U)

+#define HSEM_C1ICR_ISC4_Msk       (0x1UL << HSEM_C1ICR_ISC4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1ICR_ISC4           HSEM_C1ICR_ISC4_Msk                          /*!<semaphore 4 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC5_Pos       (5U)

+#define HSEM_C1ICR_ISC5_Msk       (0x1UL << HSEM_C1ICR_ISC5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1ICR_ISC5           HSEM_C1ICR_ISC5_Msk                          /*!<semaphore 5 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC6_Pos       (6U)

+#define HSEM_C1ICR_ISC6_Msk       (0x1UL << HSEM_C1ICR_ISC6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1ICR_ISC6           HSEM_C1ICR_ISC6_Msk                          /*!<semaphore 6 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC7_Pos       (7U)

+#define HSEM_C1ICR_ISC7_Msk       (0x1UL << HSEM_C1ICR_ISC7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1ICR_ISC7           HSEM_C1ICR_ISC7_Msk                          /*!<semaphore 7 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC8_Pos       (8U)

+#define HSEM_C1ICR_ISC8_Msk       (0x1UL << HSEM_C1ICR_ISC8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1ICR_ISC8           HSEM_C1ICR_ISC8_Msk                          /*!<semaphore 8 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC9_Pos       (9U)

+#define HSEM_C1ICR_ISC9_Msk       (0x1UL << HSEM_C1ICR_ISC9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1ICR_ISC9           HSEM_C1ICR_ISC9_Msk                          /*!<semaphore 9 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC10_Pos      (10U)

+#define HSEM_C1ICR_ISC10_Msk      (0x1UL << HSEM_C1ICR_ISC10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1ICR_ISC10          HSEM_C1ICR_ISC10_Msk                         /*!<semaphore 10 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC11_Pos      (11U)

+#define HSEM_C1ICR_ISC11_Msk      (0x1UL << HSEM_C1ICR_ISC11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1ICR_ISC11          HSEM_C1ICR_ISC11_Msk                         /*!<semaphore 11 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC12_Pos      (12U)

+#define HSEM_C1ICR_ISC12_Msk      (0x1UL << HSEM_C1ICR_ISC12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1ICR_ISC12          HSEM_C1ICR_ISC12_Msk                         /*!<semaphore 12 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC13_Pos      (13U)

+#define HSEM_C1ICR_ISC13_Msk      (0x1UL << HSEM_C1ICR_ISC13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1ICR_ISC13          HSEM_C1ICR_ISC13_Msk                         /*!<semaphore 13 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC14_Pos      (14U)

+#define HSEM_C1ICR_ISC14_Msk      (0x1UL << HSEM_C1ICR_ISC14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1ICR_ISC14          HSEM_C1ICR_ISC14_Msk                         /*!<semaphore 14 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC15_Pos      (15U)

+#define HSEM_C1ICR_ISC15_Msk      (0x1UL << HSEM_C1ICR_ISC15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1ICR_ISC15          HSEM_C1ICR_ISC15_Msk                         /*!<semaphore 15 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC16_Pos      (16U)

+#define HSEM_C1ICR_ISC16_Msk      (0x1UL << HSEM_C1ICR_ISC16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1ICR_ISC16          HSEM_C1ICR_ISC16_Msk                         /*!<semaphore 16 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC17_Pos      (17U)

+#define HSEM_C1ICR_ISC17_Msk      (0x1UL << HSEM_C1ICR_ISC17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1ICR_ISC17          HSEM_C1ICR_ISC17_Msk                         /*!<semaphore 17 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC18_Pos      (18U)

+#define HSEM_C1ICR_ISC18_Msk      (0x1UL << HSEM_C1ICR_ISC18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1ICR_ISC18          HSEM_C1ICR_ISC18_Msk                         /*!<semaphore 18 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC19_Pos      (19U)

+#define HSEM_C1ICR_ISC19_Msk      (0x1UL << HSEM_C1ICR_ISC19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1ICR_ISC19          HSEM_C1ICR_ISC19_Msk                         /*!<semaphore 19 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC20_Pos      (20U)

+#define HSEM_C1ICR_ISC20_Msk      (0x1UL << HSEM_C1ICR_ISC20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1ICR_ISC20          HSEM_C1ICR_ISC20_Msk                         /*!<semaphore 20 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC21_Pos      (21U)

+#define HSEM_C1ICR_ISC21_Msk      (0x1UL << HSEM_C1ICR_ISC21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1ICR_ISC21          HSEM_C1ICR_ISC21_Msk                         /*!<semaphore 21 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC22_Pos      (22U)

+#define HSEM_C1ICR_ISC22_Msk      (0x1UL << HSEM_C1ICR_ISC22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1ICR_ISC22          HSEM_C1ICR_ISC22_Msk                         /*!<semaphore 22 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC23_Pos      (23U)

+#define HSEM_C1ICR_ISC23_Msk      (0x1UL << HSEM_C1ICR_ISC23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1ICR_ISC23          HSEM_C1ICR_ISC23_Msk                         /*!<semaphore 23 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC24_Pos      (24U)

+#define HSEM_C1ICR_ISC24_Msk      (0x1UL << HSEM_C1ICR_ISC24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1ICR_ISC24          HSEM_C1ICR_ISC24_Msk                         /*!<semaphore 24 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC25_Pos      (25U)

+#define HSEM_C1ICR_ISC25_Msk      (0x1UL << HSEM_C1ICR_ISC25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1ICR_ISC25          HSEM_C1ICR_ISC25_Msk                         /*!<semaphore 25 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC26_Pos      (26U)

+#define HSEM_C1ICR_ISC26_Msk      (0x1UL << HSEM_C1ICR_ISC26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1ICR_ISC26          HSEM_C1ICR_ISC26_Msk                         /*!<semaphore 26 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC27_Pos      (27U)

+#define HSEM_C1ICR_ISC27_Msk      (0x1UL << HSEM_C1ICR_ISC27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1ICR_ISC27          HSEM_C1ICR_ISC27_Msk                         /*!<semaphore 27 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC28_Pos      (28U)

+#define HSEM_C1ICR_ISC28_Msk      (0x1UL << HSEM_C1ICR_ISC28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1ICR_ISC28          HSEM_C1ICR_ISC28_Msk                         /*!<semaphore 28 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC29_Pos      (29U)

+#define HSEM_C1ICR_ISC29_Msk      (0x1UL << HSEM_C1ICR_ISC29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1ICR_ISC29          HSEM_C1ICR_ISC29_Msk                         /*!<semaphore 29 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC30_Pos      (30U)

+#define HSEM_C1ICR_ISC30_Msk      (0x1UL << HSEM_C1ICR_ISC30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1ICR_ISC30          HSEM_C1ICR_ISC30_Msk                         /*!<semaphore 30 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC31_Pos      (31U)

+#define HSEM_C1ICR_ISC31_Msk      (0x1UL << HSEM_C1ICR_ISC31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1ICR_ISC31          HSEM_C1ICR_ISC31_Msk                         /*!<semaphore 31 interrupt 0 clear bit. */

+

+/********************  Bit definition for HSEM_C1ISR register  *****************/

+#define HSEM_C1ISR_ISF0_Pos       (0U)

+#define HSEM_C1ISR_ISF0_Msk       (0x1UL << HSEM_C1ISR_ISF0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1ISR_ISF0           HSEM_C1ISR_ISF0_Msk                          /*!<semaphore 0 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF1_Pos       (1U)

+#define HSEM_C1ISR_ISF1_Msk       (0x1UL << HSEM_C1ISR_ISF1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1ISR_ISF1           HSEM_C1ISR_ISF1_Msk                          /*!<semaphore 1 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF2_Pos       (2U)

+#define HSEM_C1ISR_ISF2_Msk       (0x1UL << HSEM_C1ISR_ISF2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1ISR_ISF2           HSEM_C1ISR_ISF2_Msk                          /*!<semaphore 2 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF3_Pos       (3U)

+#define HSEM_C1ISR_ISF3_Msk       (0x1UL << HSEM_C1ISR_ISF3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1ISR_ISF3           HSEM_C1ISR_ISF3_Msk                          /*!<semaphore 3 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF4_Pos       (4U)

+#define HSEM_C1ISR_ISF4_Msk       (0x1UL << HSEM_C1ISR_ISF4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1ISR_ISF4           HSEM_C1ISR_ISF4_Msk                          /*!<semaphore 4 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF5_Pos       (5U)

+#define HSEM_C1ISR_ISF5_Msk       (0x1UL << HSEM_C1ISR_ISF5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1ISR_ISF5           HSEM_C1ISR_ISF5_Msk                          /*!<semaphore 5 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF6_Pos       (6U)

+#define HSEM_C1ISR_ISF6_Msk       (0x1UL << HSEM_C1ISR_ISF6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1ISR_ISF6           HSEM_C1ISR_ISF6_Msk                          /*!<semaphore 6 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF7_Pos       (7U)

+#define HSEM_C1ISR_ISF7_Msk       (0x1UL << HSEM_C1ISR_ISF7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1ISR_ISF7           HSEM_C1ISR_ISF7_Msk                          /*!<semaphore 7 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF8_Pos       (8U)

+#define HSEM_C1ISR_ISF8_Msk       (0x1UL << HSEM_C1ISR_ISF8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1ISR_ISF8           HSEM_C1ISR_ISF8_Msk                          /*!<semaphore 8 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF9_Pos       (9U)

+#define HSEM_C1ISR_ISF9_Msk       (0x1UL << HSEM_C1ISR_ISF9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1ISR_ISF9           HSEM_C1ISR_ISF9_Msk                          /*!<semaphore 9 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF10_Pos      (10U)

+#define HSEM_C1ISR_ISF10_Msk      (0x1UL << HSEM_C1ISR_ISF10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1ISR_ISF10          HSEM_C1ISR_ISF10_Msk                         /*!<semaphore 10 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF11_Pos      (11U)

+#define HSEM_C1ISR_ISF11_Msk      (0x1UL << HSEM_C1ISR_ISF11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1ISR_ISF11          HSEM_C1ISR_ISF11_Msk                         /*!<semaphore 11 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF12_Pos      (12U)

+#define HSEM_C1ISR_ISF12_Msk      (0x1UL << HSEM_C1ISR_ISF12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1ISR_ISF12          HSEM_C1ISR_ISF12_Msk                         /*!<semaphore 12 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF13_Pos      (13U)

+#define HSEM_C1ISR_ISF13_Msk      (0x1UL << HSEM_C1ISR_ISF13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1ISR_ISF13          HSEM_C1ISR_ISF13_Msk                         /*!<semaphore 13 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF14_Pos      (14U)

+#define HSEM_C1ISR_ISF14_Msk      (0x1UL << HSEM_C1ISR_ISF14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1ISR_ISF14          HSEM_C1ISR_ISF14_Msk                         /*!<semaphore 14 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF15_Pos      (15U)

+#define HSEM_C1ISR_ISF15_Msk      (0x1UL << HSEM_C1ISR_ISF15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1ISR_ISF15          HSEM_C1ISR_ISF15_Msk                         /*!<semaphore 15 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF16_Pos      (16U)

+#define HSEM_C1ISR_ISF16_Msk      (0x1UL << HSEM_C1ISR_ISF16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1ISR_ISF16          HSEM_C1ISR_ISF16_Msk                         /*!<semaphore 16 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF17_Pos      (17U)

+#define HSEM_C1ISR_ISF17_Msk      (0x1UL << HSEM_C1ISR_ISF17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1ISR_ISF17          HSEM_C1ISR_ISF17_Msk                         /*!<semaphore 17 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF18_Pos      (18U)

+#define HSEM_C1ISR_ISF18_Msk      (0x1UL << HSEM_C1ISR_ISF18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1ISR_ISF18          HSEM_C1ISR_ISF18_Msk                         /*!<semaphore 18 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF19_Pos      (19U)

+#define HSEM_C1ISR_ISF19_Msk      (0x1UL << HSEM_C1ISR_ISF19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1ISR_ISF19          HSEM_C1ISR_ISF19_Msk                         /*!<semaphore 19 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF20_Pos      (20U)

+#define HSEM_C1ISR_ISF20_Msk      (0x1UL << HSEM_C1ISR_ISF20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1ISR_ISF20          HSEM_C1ISR_ISF20_Msk                         /*!<semaphore 20 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF21_Pos      (21U)

+#define HSEM_C1ISR_ISF21_Msk      (0x1UL << HSEM_C1ISR_ISF21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1ISR_ISF21          HSEM_C1ISR_ISF21_Msk                         /*!<semaphore 21 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF22_Pos      (22U)

+#define HSEM_C1ISR_ISF22_Msk      (0x1UL << HSEM_C1ISR_ISF22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1ISR_ISF22          HSEM_C1ISR_ISF22_Msk                         /*!<semaphore 22 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF23_Pos      (23U)

+#define HSEM_C1ISR_ISF23_Msk      (0x1UL << HSEM_C1ISR_ISF23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1ISR_ISF23          HSEM_C1ISR_ISF23_Msk                         /*!<semaphore 23 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF24_Pos      (24U)

+#define HSEM_C1ISR_ISF24_Msk      (0x1UL << HSEM_C1ISR_ISF24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1ISR_ISF24          HSEM_C1ISR_ISF24_Msk                         /*!<semaphore 24 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF25_Pos      (25U)

+#define HSEM_C1ISR_ISF25_Msk      (0x1UL << HSEM_C1ISR_ISF25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1ISR_ISF25          HSEM_C1ISR_ISF25_Msk                         /*!<semaphore 25 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF26_Pos      (26U)

+#define HSEM_C1ISR_ISF26_Msk      (0x1UL << HSEM_C1ISR_ISF26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1ISR_ISF26          HSEM_C1ISR_ISF26_Msk                         /*!<semaphore 26 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF27_Pos      (27U)

+#define HSEM_C1ISR_ISF27_Msk      (0x1UL << HSEM_C1ISR_ISF27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1ISR_ISF27          HSEM_C1ISR_ISF27_Msk                         /*!<semaphore 27 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF28_Pos      (28U)

+#define HSEM_C1ISR_ISF28_Msk      (0x1UL << HSEM_C1ISR_ISF28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1ISR_ISF28          HSEM_C1ISR_ISF28_Msk                         /*!<semaphore 28 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF29_Pos      (29U)

+#define HSEM_C1ISR_ISF29_Msk      (0x1UL << HSEM_C1ISR_ISF29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1ISR_ISF29          HSEM_C1ISR_ISF29_Msk                         /*!<semaphore 29 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF30_Pos      (30U)

+#define HSEM_C1ISR_ISF30_Msk      (0x1UL << HSEM_C1ISR_ISF30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1ISR_ISF30          HSEM_C1ISR_ISF30_Msk                         /*!<semaphore 30 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF31_Pos      (31U)

+#define HSEM_C1ISR_ISF31_Msk      (0x1UL << HSEM_C1ISR_ISF31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1ISR_ISF31          HSEM_C1ISR_ISF31_Msk                         /*!<semaphore 31 interrupt 0 status bit. */

+

+/********************  Bit definition for HSEM_C1MISR register  *****************/

+#define HSEM_C1MISR_MISF0_Pos     (0U)

+#define HSEM_C1MISR_MISF0_Msk     (0x1UL << HSEM_C1MISR_MISF0_Pos)             /*!< 0x00000001 */

+#define HSEM_C1MISR_MISF0         HSEM_C1MISR_MISF0_Msk                        /*!<semaphore 0 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF1_Pos     (1U)

+#define HSEM_C1MISR_MISF1_Msk     (0x1UL << HSEM_C1MISR_MISF1_Pos)             /*!< 0x00000002 */

+#define HSEM_C1MISR_MISF1         HSEM_C1MISR_MISF1_Msk                        /*!<semaphore 1 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF2_Pos     (2U)

+#define HSEM_C1MISR_MISF2_Msk     (0x1UL << HSEM_C1MISR_MISF2_Pos)             /*!< 0x00000004 */

+#define HSEM_C1MISR_MISF2         HSEM_C1MISR_MISF2_Msk                        /*!<semaphore 2 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF3_Pos     (3U)

+#define HSEM_C1MISR_MISF3_Msk     (0x1UL << HSEM_C1MISR_MISF3_Pos)             /*!< 0x00000008 */

+#define HSEM_C1MISR_MISF3         HSEM_C1MISR_MISF3_Msk                        /*!<semaphore 3 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF4_Pos     (4U)

+#define HSEM_C1MISR_MISF4_Msk     (0x1UL << HSEM_C1MISR_MISF4_Pos)             /*!< 0x00000010 */

+#define HSEM_C1MISR_MISF4         HSEM_C1MISR_MISF4_Msk                        /*!<semaphore 4 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF5_Pos     (5U)

+#define HSEM_C1MISR_MISF5_Msk     (0x1UL << HSEM_C1MISR_MISF5_Pos)             /*!< 0x00000020 */

+#define HSEM_C1MISR_MISF5         HSEM_C1MISR_MISF5_Msk                        /*!<semaphore 5 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF6_Pos     (6U)

+#define HSEM_C1MISR_MISF6_Msk     (0x1UL << HSEM_C1MISR_MISF6_Pos)             /*!< 0x00000040 */

+#define HSEM_C1MISR_MISF6         HSEM_C1MISR_MISF6_Msk                        /*!<semaphore 6 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF7_Pos     (7U)

+#define HSEM_C1MISR_MISF7_Msk     (0x1UL << HSEM_C1MISR_MISF7_Pos)             /*!< 0x00000080 */

+#define HSEM_C1MISR_MISF7         HSEM_C1MISR_MISF7_Msk                        /*!<semaphore 7 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF8_Pos     (8U)

+#define HSEM_C1MISR_MISF8_Msk     (0x1UL << HSEM_C1MISR_MISF8_Pos)             /*!< 0x00000100 */

+#define HSEM_C1MISR_MISF8         HSEM_C1MISR_MISF8_Msk                        /*!<semaphore 8 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF9_Pos     (9U)

+#define HSEM_C1MISR_MISF9_Msk     (0x1UL << HSEM_C1MISR_MISF9_Pos)             /*!< 0x00000200 */

+#define HSEM_C1MISR_MISF9         HSEM_C1MISR_MISF9_Msk                        /*!<semaphore 9 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF10_Pos    (10U)

+#define HSEM_C1MISR_MISF10_Msk    (0x1UL << HSEM_C1MISR_MISF10_Pos)            /*!< 0x00000400 */

+#define HSEM_C1MISR_MISF10        HSEM_C1MISR_MISF10_Msk                       /*!<semaphore 10 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF11_Pos    (11U)

+#define HSEM_C1MISR_MISF11_Msk    (0x1UL << HSEM_C1MISR_MISF11_Pos)            /*!< 0x00000800 */

+#define HSEM_C1MISR_MISF11        HSEM_C1MISR_MISF11_Msk                       /*!<semaphore 11 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF12_Pos    (12U)

+#define HSEM_C1MISR_MISF12_Msk    (0x1UL << HSEM_C1MISR_MISF12_Pos)            /*!< 0x00001000 */

+#define HSEM_C1MISR_MISF12        HSEM_C1MISR_MISF12_Msk                       /*!<semaphore 12 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF13_Pos    (13U)

+#define HSEM_C1MISR_MISF13_Msk    (0x1UL << HSEM_C1MISR_MISF13_Pos)            /*!< 0x00002000 */

+#define HSEM_C1MISR_MISF13        HSEM_C1MISR_MISF13_Msk                       /*!<semaphore 13 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF14_Pos    (14U)

+#define HSEM_C1MISR_MISF14_Msk    (0x1UL << HSEM_C1MISR_MISF14_Pos)            /*!< 0x00004000 */

+#define HSEM_C1MISR_MISF14        HSEM_C1MISR_MISF14_Msk                       /*!<semaphore 14 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF15_Pos    (15U)

+#define HSEM_C1MISR_MISF15_Msk    (0x1UL << HSEM_C1MISR_MISF15_Pos)            /*!< 0x00008000 */

+#define HSEM_C1MISR_MISF15        HSEM_C1MISR_MISF15_Msk                       /*!<semaphore 15 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF16_Pos    (16U)

+#define HSEM_C1MISR_MISF16_Msk    (0x1UL << HSEM_C1MISR_MISF16_Pos)            /*!< 0x00010000 */

+#define HSEM_C1MISR_MISF16        HSEM_C1MISR_MISF16_Msk                       /*!<semaphore 16 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF17_Pos    (17U)

+#define HSEM_C1MISR_MISF17_Msk    (0x1UL << HSEM_C1MISR_MISF17_Pos)            /*!< 0x00020000 */

+#define HSEM_C1MISR_MISF17        HSEM_C1MISR_MISF17_Msk                       /*!<semaphore 17 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF18_Pos    (18U)

+#define HSEM_C1MISR_MISF18_Msk    (0x1UL << HSEM_C1MISR_MISF18_Pos)            /*!< 0x00040000 */

+#define HSEM_C1MISR_MISF18        HSEM_C1MISR_MISF18_Msk                       /*!<semaphore 18 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF19_Pos    (19U)

+#define HSEM_C1MISR_MISF19_Msk    (0x1UL << HSEM_C1MISR_MISF19_Pos)            /*!< 0x00080000 */

+#define HSEM_C1MISR_MISF19        HSEM_C1MISR_MISF19_Msk                       /*!<semaphore 19 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF20_Pos    (20U)

+#define HSEM_C1MISR_MISF20_Msk    (0x1UL << HSEM_C1MISR_MISF20_Pos)            /*!< 0x00100000 */

+#define HSEM_C1MISR_MISF20        HSEM_C1MISR_MISF20_Msk                       /*!<semaphore 20 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF21_Pos    (21U)

+#define HSEM_C1MISR_MISF21_Msk    (0x1UL << HSEM_C1MISR_MISF21_Pos)            /*!< 0x00200000 */

+#define HSEM_C1MISR_MISF21        HSEM_C1MISR_MISF21_Msk                       /*!<semaphore 21 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF22_Pos    (22U)

+#define HSEM_C1MISR_MISF22_Msk    (0x1UL << HSEM_C1MISR_MISF22_Pos)            /*!< 0x00400000 */

+#define HSEM_C1MISR_MISF22        HSEM_C1MISR_MISF22_Msk                       /*!<semaphore 22 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF23_Pos    (23U)

+#define HSEM_C1MISR_MISF23_Msk    (0x1UL << HSEM_C1MISR_MISF23_Pos)            /*!< 0x00800000 */

+#define HSEM_C1MISR_MISF23        HSEM_C1MISR_MISF23_Msk                       /*!<semaphore 23 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF24_Pos    (24U)

+#define HSEM_C1MISR_MISF24_Msk    (0x1UL << HSEM_C1MISR_MISF24_Pos)            /*!< 0x01000000 */

+#define HSEM_C1MISR_MISF24        HSEM_C1MISR_MISF24_Msk                       /*!<semaphore 24 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF25_Pos    (25U)

+#define HSEM_C1MISR_MISF25_Msk    (0x1UL << HSEM_C1MISR_MISF25_Pos)            /*!< 0x02000000 */

+#define HSEM_C1MISR_MISF25        HSEM_C1MISR_MISF25_Msk                       /*!<semaphore 25 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF26_Pos    (26U)

+#define HSEM_C1MISR_MISF26_Msk    (0x1UL << HSEM_C1MISR_MISF26_Pos)            /*!< 0x04000000 */

+#define HSEM_C1MISR_MISF26        HSEM_C1MISR_MISF26_Msk                       /*!<semaphore 26 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF27_Pos    (27U)

+#define HSEM_C1MISR_MISF27_Msk    (0x1UL << HSEM_C1MISR_MISF27_Pos)            /*!< 0x08000000 */

+#define HSEM_C1MISR_MISF27        HSEM_C1MISR_MISF27_Msk                       /*!<semaphore 27 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF28_Pos    (28U)

+#define HSEM_C1MISR_MISF28_Msk    (0x1UL << HSEM_C1MISR_MISF28_Pos)            /*!< 0x10000000 */

+#define HSEM_C1MISR_MISF28        HSEM_C1MISR_MISF28_Msk                       /*!<semaphore 28 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF29_Pos    (29U)

+#define HSEM_C1MISR_MISF29_Msk    (0x1UL << HSEM_C1MISR_MISF29_Pos)            /*!< 0x20000000 */

+#define HSEM_C1MISR_MISF29        HSEM_C1MISR_MISF29_Msk                       /*!<semaphore 29 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF30_Pos    (30U)

+#define HSEM_C1MISR_MISF30_Msk    (0x1UL << HSEM_C1MISR_MISF30_Pos)            /*!< 0x40000000 */

+#define HSEM_C1MISR_MISF30        HSEM_C1MISR_MISF30_Msk                       /*!<semaphore 30 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF31_Pos    (31U)

+#define HSEM_C1MISR_MISF31_Msk    (0x1UL << HSEM_C1MISR_MISF31_Pos)            /*!< 0x80000000 */

+#define HSEM_C1MISR_MISF31        HSEM_C1MISR_MISF31_Msk                       /*!<semaphore 31 interrupt 0 masked status bit. */

+

+/********************  Bit definition for HSEM_C2IER register  *****************/

+#define HSEM_C2IER_ISE0_Pos       (0U)

+#define HSEM_C2IER_ISE0_Msk       (0x1UL << HSEM_C2IER_ISE0_Pos)               /*!< 0x00000001 */

+#define HSEM_C2IER_ISE0           HSEM_C2IER_ISE0_Msk                          /*!<semaphore 0 , interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE1_Pos       (1U)

+#define HSEM_C2IER_ISE1_Msk       (0x1UL << HSEM_C2IER_ISE1_Pos)               /*!< 0x00000002 */

+#define HSEM_C2IER_ISE1           HSEM_C2IER_ISE1_Msk                          /*!<semaphore 1 , interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE2_Pos       (2U)

+#define HSEM_C2IER_ISE2_Msk       (0x1UL << HSEM_C2IER_ISE2_Pos)               /*!< 0x00000004 */

+#define HSEM_C2IER_ISE2           HSEM_C2IER_ISE2_Msk                          /*!<semaphore 2 , interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE3_Pos       (3U)

+#define HSEM_C2IER_ISE3_Msk       (0x1UL << HSEM_C2IER_ISE3_Pos)               /*!< 0x00000008 */

+#define HSEM_C2IER_ISE3           HSEM_C2IER_ISE3_Msk                          /*!<semaphore 3 , interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE4_Pos       (4U)

+#define HSEM_C2IER_ISE4_Msk       (0x1UL << HSEM_C2IER_ISE4_Pos)               /*!< 0x00000010 */

+#define HSEM_C2IER_ISE4           HSEM_C2IER_ISE4_Msk                          /*!<semaphore 4 , interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE5_Pos       (5U)

+#define HSEM_C2IER_ISE5_Msk       (0x1UL << HSEM_C2IER_ISE5_Pos)               /*!< 0x00000020 */

+#define HSEM_C2IER_ISE5           HSEM_C2IER_ISE5_Msk                          /*!<semaphore 5 interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE6_Pos       (6U)

+#define HSEM_C2IER_ISE6_Msk       (0x1UL << HSEM_C2IER_ISE6_Pos)               /*!< 0x00000040 */

+#define HSEM_C2IER_ISE6           HSEM_C2IER_ISE6_Msk                          /*!<semaphore 6 interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE7_Pos       (7U)

+#define HSEM_C2IER_ISE7_Msk       (0x1UL << HSEM_C2IER_ISE7_Pos)               /*!< 0x00000080 */

+#define HSEM_C2IER_ISE7           HSEM_C2IER_ISE7_Msk                          /*!<semaphore 7 interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE8_Pos       (8U)

+#define HSEM_C2IER_ISE8_Msk       (0x1UL << HSEM_C2IER_ISE8_Pos)               /*!< 0x00000100 */

+#define HSEM_C2IER_ISE8           HSEM_C2IER_ISE8_Msk                          /*!<semaphore 8 interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE9_Pos       (9U)

+#define HSEM_C2IER_ISE9_Msk       (0x1UL << HSEM_C2IER_ISE9_Pos)               /*!< 0x00000200 */

+#define HSEM_C2IER_ISE9           HSEM_C2IER_ISE9_Msk                          /*!<semaphore 9 interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE10_Pos      (10U)

+#define HSEM_C2IER_ISE10_Msk      (0x1UL << HSEM_C2IER_ISE10_Pos)              /*!< 0x00000400 */

+#define HSEM_C2IER_ISE10          HSEM_C2IER_ISE10_Msk                         /*!<semaphore 10 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE11_Pos      (11U)

+#define HSEM_C2IER_ISE11_Msk      (0x1UL << HSEM_C2IER_ISE11_Pos)              /*!< 0x00000800 */

+#define HSEM_C2IER_ISE11          HSEM_C2IER_ISE11_Msk                         /*!<semaphore 11 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE12_Pos      (12U)

+#define HSEM_C2IER_ISE12_Msk      (0x1UL << HSEM_C2IER_ISE12_Pos)              /*!< 0x00001000 */

+#define HSEM_C2IER_ISE12          HSEM_C2IER_ISE12_Msk                         /*!<semaphore 12 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE13_Pos      (13U)

+#define HSEM_C2IER_ISE13_Msk      (0x1UL << HSEM_C2IER_ISE13_Pos)              /*!< 0x00002000 */

+#define HSEM_C2IER_ISE13          HSEM_C2IER_ISE13_Msk                         /*!<semaphore 13 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE14_Pos      (14U)

+#define HSEM_C2IER_ISE14_Msk      (0x1UL << HSEM_C2IER_ISE14_Pos)              /*!< 0x00004000 */

+#define HSEM_C2IER_ISE14          HSEM_C2IER_ISE14_Msk                         /*!<semaphore 14 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE15_Pos      (15U)

+#define HSEM_C2IER_ISE15_Msk      (0x1UL << HSEM_C2IER_ISE15_Pos)              /*!< 0x00008000 */

+#define HSEM_C2IER_ISE15          HSEM_C2IER_ISE15_Msk                         /*!<semaphore 15 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE16_Pos      (16U)

+#define HSEM_C2IER_ISE16_Msk      (0x1UL << HSEM_C2IER_ISE16_Pos)              /*!< 0x00010000 */

+#define HSEM_C2IER_ISE16          HSEM_C2IER_ISE16_Msk                         /*!<semaphore 16 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE17_Pos      (17U)

+#define HSEM_C2IER_ISE17_Msk      (0x1UL << HSEM_C2IER_ISE17_Pos)              /*!< 0x00020000 */

+#define HSEM_C2IER_ISE17          HSEM_C2IER_ISE17_Msk                         /*!<semaphore 17 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE18_Pos      (18U)

+#define HSEM_C2IER_ISE18_Msk      (0x1UL << HSEM_C2IER_ISE18_Pos)              /*!< 0x00040000 */

+#define HSEM_C2IER_ISE18          HSEM_C2IER_ISE18_Msk                         /*!<semaphore 18 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE19_Pos      (19U)

+#define HSEM_C2IER_ISE19_Msk      (0x1UL << HSEM_C2IER_ISE19_Pos)              /*!< 0x00080000 */

+#define HSEM_C2IER_ISE19          HSEM_C2IER_ISE19_Msk                         /*!<semaphore 19 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE20_Pos      (20U)

+#define HSEM_C2IER_ISE20_Msk      (0x1UL << HSEM_C2IER_ISE20_Pos)              /*!< 0x00100000 */

+#define HSEM_C2IER_ISE20          HSEM_C2IER_ISE20_Msk                         /*!<semaphore 20 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE21_Pos      (21U)

+#define HSEM_C2IER_ISE21_Msk      (0x1UL << HSEM_C2IER_ISE21_Pos)              /*!< 0x00200000 */

+#define HSEM_C2IER_ISE21          HSEM_C2IER_ISE21_Msk                         /*!<semaphore 21 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE22_Pos      (22U)

+#define HSEM_C2IER_ISE22_Msk      (0x1UL << HSEM_C2IER_ISE22_Pos)              /*!< 0x00400000 */

+#define HSEM_C2IER_ISE22          HSEM_C2IER_ISE22_Msk                         /*!<semaphore 22 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE23_Pos      (23U)

+#define HSEM_C2IER_ISE23_Msk      (0x1UL << HSEM_C2IER_ISE23_Pos)              /*!< 0x00800000 */

+#define HSEM_C2IER_ISE23          HSEM_C2IER_ISE23_Msk                         /*!<semaphore 23 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE24_Pos      (24U)

+#define HSEM_C2IER_ISE24_Msk      (0x1UL << HSEM_C2IER_ISE24_Pos)              /*!< 0x01000000 */

+#define HSEM_C2IER_ISE24          HSEM_C2IER_ISE24_Msk                         /*!<semaphore 24 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE25_Pos      (25U)

+#define HSEM_C2IER_ISE25_Msk      (0x1UL << HSEM_C2IER_ISE25_Pos)              /*!< 0x02000000 */

+#define HSEM_C2IER_ISE25          HSEM_C2IER_ISE25_Msk                         /*!<semaphore 25 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE26_Pos      (26U)

+#define HSEM_C2IER_ISE26_Msk      (0x1UL << HSEM_C2IER_ISE26_Pos)              /*!< 0x04000000 */

+#define HSEM_C2IER_ISE26          HSEM_C2IER_ISE26_Msk                         /*!<semaphore 26 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE27_Pos      (27U)

+#define HSEM_C2IER_ISE27_Msk      (0x1UL << HSEM_C2IER_ISE27_Pos)              /*!< 0x08000000 */

+#define HSEM_C2IER_ISE27          HSEM_C2IER_ISE27_Msk                         /*!<semaphore 27 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE28_Pos      (28U)

+#define HSEM_C2IER_ISE28_Msk      (0x1UL << HSEM_C2IER_ISE28_Pos)              /*!< 0x10000000 */

+#define HSEM_C2IER_ISE28          HSEM_C2IER_ISE28_Msk                         /*!<semaphore 28 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE29_Pos      (29U)

+#define HSEM_C2IER_ISE29_Msk      (0x1UL << HSEM_C2IER_ISE29_Pos)              /*!< 0x20000000 */

+#define HSEM_C2IER_ISE29          HSEM_C2IER_ISE29_Msk                         /*!<semaphore 29 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE30_Pos      (30U)

+#define HSEM_C2IER_ISE30_Msk      (0x1UL << HSEM_C2IER_ISE30_Pos)              /*!< 0x40000000 */

+#define HSEM_C2IER_ISE30          HSEM_C2IER_ISE30_Msk                         /*!<semaphore 30 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE31_Pos      (31U)

+#define HSEM_C2IER_ISE31_Msk      (0x1UL << HSEM_C2IER_ISE31_Pos)              /*!< 0x80000000 */

+#define HSEM_C2IER_ISE31          HSEM_C2IER_ISE31_Msk                         /*!<semaphore 31 interrupt 1 enable bit. */

+

+/********************  Bit definition for HSEM_C2ICR register  *****************/

+#define HSEM_C2ICR_ISC0_Pos       (0U)

+#define HSEM_C2ICR_ISC0_Msk       (0x1UL << HSEM_C2ICR_ISC0_Pos)               /*!< 0x00000001 */

+#define HSEM_C2ICR_ISC0           HSEM_C2ICR_ISC0_Msk                          /*!<semaphore 0 , interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC1_Pos       (1U)

+#define HSEM_C2ICR_ISC1_Msk       (0x1UL << HSEM_C2ICR_ISC1_Pos)               /*!< 0x00000002 */

+#define HSEM_C2ICR_ISC1           HSEM_C2ICR_ISC1_Msk                          /*!<semaphore 1 , interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC2_Pos       (2U)

+#define HSEM_C2ICR_ISC2_Msk       (0x1UL << HSEM_C2ICR_ISC2_Pos)               /*!< 0x00000004 */

+#define HSEM_C2ICR_ISC2           HSEM_C2ICR_ISC2_Msk                          /*!<semaphore 2 , interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC3_Pos       (3U)

+#define HSEM_C2ICR_ISC3_Msk       (0x1UL << HSEM_C2ICR_ISC3_Pos)               /*!< 0x00000008 */

+#define HSEM_C2ICR_ISC3           HSEM_C2ICR_ISC3_Msk                          /*!<semaphore 3 , interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC4_Pos       (4U)

+#define HSEM_C2ICR_ISC4_Msk       (0x1UL << HSEM_C2ICR_ISC4_Pos)               /*!< 0x00000010 */

+#define HSEM_C2ICR_ISC4           HSEM_C2ICR_ISC4_Msk                          /*!<semaphore 4 , interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC5_Pos       (5U)

+#define HSEM_C2ICR_ISC5_Msk       (0x1UL << HSEM_C2ICR_ISC5_Pos)               /*!< 0x00000020 */

+#define HSEM_C2ICR_ISC5           HSEM_C2ICR_ISC5_Msk                          /*!<semaphore 5 interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC6_Pos       (6U)

+#define HSEM_C2ICR_ISC6_Msk       (0x1UL << HSEM_C2ICR_ISC6_Pos)               /*!< 0x00000040 */

+#define HSEM_C2ICR_ISC6           HSEM_C2ICR_ISC6_Msk                          /*!<semaphore 6 interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC7_Pos       (7U)

+#define HSEM_C2ICR_ISC7_Msk       (0x1UL << HSEM_C2ICR_ISC7_Pos)               /*!< 0x00000080 */

+#define HSEM_C2ICR_ISC7           HSEM_C2ICR_ISC7_Msk                          /*!<semaphore 7 interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC8_Pos       (8U)

+#define HSEM_C2ICR_ISC8_Msk       (0x1UL << HSEM_C2ICR_ISC8_Pos)               /*!< 0x00000100 */

+#define HSEM_C2ICR_ISC8           HSEM_C2ICR_ISC8_Msk                          /*!<semaphore 8 interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC9_Pos       (9U)

+#define HSEM_C2ICR_ISC9_Msk       (0x1UL << HSEM_C2ICR_ISC9_Pos)               /*!< 0x00000200 */

+#define HSEM_C2ICR_ISC9           HSEM_C2ICR_ISC9_Msk                          /*!<semaphore 9 interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC10_Pos      (10U)

+#define HSEM_C2ICR_ISC10_Msk      (0x1UL << HSEM_C2ICR_ISC10_Pos)              /*!< 0x00000400 */

+#define HSEM_C2ICR_ISC10          HSEM_C2ICR_ISC10_Msk                         /*!<semaphore 10 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC11_Pos      (11U)

+#define HSEM_C2ICR_ISC11_Msk      (0x1UL << HSEM_C2ICR_ISC11_Pos)              /*!< 0x00000800 */

+#define HSEM_C2ICR_ISC11          HSEM_C2ICR_ISC11_Msk                         /*!<semaphore 11 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC12_Pos      (12U)

+#define HSEM_C2ICR_ISC12_Msk      (0x1UL << HSEM_C2ICR_ISC12_Pos)              /*!< 0x00001000 */

+#define HSEM_C2ICR_ISC12          HSEM_C2ICR_ISC12_Msk                         /*!<semaphore 12 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC13_Pos      (13U)

+#define HSEM_C2ICR_ISC13_Msk      (0x1UL << HSEM_C2ICR_ISC13_Pos)              /*!< 0x00002000 */

+#define HSEM_C2ICR_ISC13          HSEM_C2ICR_ISC13_Msk                         /*!<semaphore 13 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC14_Pos      (14U)

+#define HSEM_C2ICR_ISC14_Msk      (0x1UL << HSEM_C2ICR_ISC14_Pos)              /*!< 0x00004000 */

+#define HSEM_C2ICR_ISC14          HSEM_C2ICR_ISC14_Msk                         /*!<semaphore 14 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC15_Pos      (15U)

+#define HSEM_C2ICR_ISC15_Msk      (0x1UL << HSEM_C2ICR_ISC15_Pos)              /*!< 0x00008000 */

+#define HSEM_C2ICR_ISC15          HSEM_C2ICR_ISC15_Msk                         /*!<semaphore 15 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC16_Pos      (16U)

+#define HSEM_C2ICR_ISC16_Msk      (0x1UL << HSEM_C2ICR_ISC16_Pos)              /*!< 0x00010000 */

+#define HSEM_C2ICR_ISC16          HSEM_C2ICR_ISC16_Msk                         /*!<semaphore 16 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC17_Pos      (17U)

+#define HSEM_C2ICR_ISC17_Msk      (0x1UL << HSEM_C2ICR_ISC17_Pos)              /*!< 0x00020000 */

+#define HSEM_C2ICR_ISC17          HSEM_C2ICR_ISC17_Msk                         /*!<semaphore 17 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC18_Pos      (18U)

+#define HSEM_C2ICR_ISC18_Msk      (0x1UL << HSEM_C2ICR_ISC18_Pos)              /*!< 0x00040000 */

+#define HSEM_C2ICR_ISC18          HSEM_C2ICR_ISC18_Msk                         /*!<semaphore 18 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC19_Pos      (19U)

+#define HSEM_C2ICR_ISC19_Msk      (0x1UL << HSEM_C2ICR_ISC19_Pos)              /*!< 0x00080000 */

+#define HSEM_C2ICR_ISC19          HSEM_C2ICR_ISC19_Msk                         /*!<semaphore 19 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC20_Pos      (20U)

+#define HSEM_C2ICR_ISC20_Msk      (0x1UL << HSEM_C2ICR_ISC20_Pos)              /*!< 0x00100000 */

+#define HSEM_C2ICR_ISC20          HSEM_C2ICR_ISC20_Msk                         /*!<semaphore 20 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC21_Pos      (21U)

+#define HSEM_C2ICR_ISC21_Msk      (0x1UL << HSEM_C2ICR_ISC21_Pos)              /*!< 0x00200000 */

+#define HSEM_C2ICR_ISC21          HSEM_C2ICR_ISC21_Msk                         /*!<semaphore 21 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC22_Pos      (22U)

+#define HSEM_C2ICR_ISC22_Msk      (0x1UL << HSEM_C2ICR_ISC22_Pos)              /*!< 0x00400000 */

+#define HSEM_C2ICR_ISC22          HSEM_C2ICR_ISC22_Msk                         /*!<semaphore 22 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC23_Pos      (23U)

+#define HSEM_C2ICR_ISC23_Msk      (0x1UL << HSEM_C2ICR_ISC23_Pos)              /*!< 0x00800000 */

+#define HSEM_C2ICR_ISC23          HSEM_C2ICR_ISC23_Msk                         /*!<semaphore 23 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC24_Pos      (24U)

+#define HSEM_C2ICR_ISC24_Msk      (0x1UL << HSEM_C2ICR_ISC24_Pos)              /*!< 0x01000000 */

+#define HSEM_C2ICR_ISC24          HSEM_C2ICR_ISC24_Msk                         /*!<semaphore 24 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC25_Pos      (25U)

+#define HSEM_C2ICR_ISC25_Msk      (0x1UL << HSEM_C2ICR_ISC25_Pos)              /*!< 0x02000000 */

+#define HSEM_C2ICR_ISC25          HSEM_C2ICR_ISC25_Msk                         /*!<semaphore 25 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC26_Pos      (26U)

+#define HSEM_C2ICR_ISC26_Msk      (0x1UL << HSEM_C2ICR_ISC26_Pos)              /*!< 0x04000000 */

+#define HSEM_C2ICR_ISC26          HSEM_C2ICR_ISC26_Msk                         /*!<semaphore 26 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC27_Pos      (27U)

+#define HSEM_C2ICR_ISC27_Msk      (0x1UL << HSEM_C2ICR_ISC27_Pos)              /*!< 0x08000000 */

+#define HSEM_C2ICR_ISC27          HSEM_C2ICR_ISC27_Msk                         /*!<semaphore 27 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC28_Pos      (28U)

+#define HSEM_C2ICR_ISC28_Msk      (0x1UL << HSEM_C2ICR_ISC28_Pos)              /*!< 0x10000000 */

+#define HSEM_C2ICR_ISC28          HSEM_C2ICR_ISC28_Msk                         /*!<semaphore 28 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC29_Pos      (29U)

+#define HSEM_C2ICR_ISC29_Msk      (0x1UL << HSEM_C2ICR_ISC29_Pos)              /*!< 0x20000000 */

+#define HSEM_C2ICR_ISC29          HSEM_C2ICR_ISC29_Msk                         /*!<semaphore 29 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC30_Pos      (30U)

+#define HSEM_C2ICR_ISC30_Msk      (0x1UL << HSEM_C2ICR_ISC30_Pos)              /*!< 0x40000000 */

+#define HSEM_C2ICR_ISC30          HSEM_C2ICR_ISC30_Msk                         /*!<semaphore 30 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC31_Pos      (31U)

+#define HSEM_C2ICR_ISC31_Msk      (0x1UL << HSEM_C2ICR_ISC31_Pos)              /*!< 0x80000000 */

+#define HSEM_C2ICR_ISC31          HSEM_C2ICR_ISC31_Msk                         /*!<semaphore 31 interrupt 1 clear bit. */

+

+/********************  Bit definition for HSEM_C2ISR register  *****************/

+#define HSEM_C2ISR_ISF0_Pos       (0U)

+#define HSEM_C2ISR_ISF0_Msk       (0x1UL << HSEM_C2ISR_ISF0_Pos)               /*!< 0x00000001 */

+#define HSEM_C2ISR_ISF0           HSEM_C2ISR_ISF0_Msk                          /*!<semaphore 0 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF1_Pos       (1U)

+#define HSEM_C2ISR_ISF1_Msk       (0x1UL << HSEM_C2ISR_ISF1_Pos)               /*!< 0x00000002 */

+#define HSEM_C2ISR_ISF1           HSEM_C2ISR_ISF1_Msk                          /*!<semaphore 1 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF2_Pos       (2U)

+#define HSEM_C2ISR_ISF2_Msk       (0x1UL << HSEM_C2ISR_ISF2_Pos)               /*!< 0x00000004 */

+#define HSEM_C2ISR_ISF2           HSEM_C2ISR_ISF2_Msk                          /*!<semaphore 2 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF3_Pos       (3U)

+#define HSEM_C2ISR_ISF3_Msk       (0x1UL << HSEM_C2ISR_ISF3_Pos)               /*!< 0x00000008 */

+#define HSEM_C2ISR_ISF3           HSEM_C2ISR_ISF3_Msk                          /*!<semaphore 3 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF4_Pos       (4U)

+#define HSEM_C2ISR_ISF4_Msk       (0x1UL << HSEM_C2ISR_ISF4_Pos)               /*!< 0x00000010 */

+#define HSEM_C2ISR_ISF4           HSEM_C2ISR_ISF4_Msk                          /*!<semaphore 4 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF5_Pos       (5U)

+#define HSEM_C2ISR_ISF5_Msk       (0x1UL << HSEM_C2ISR_ISF5_Pos)               /*!< 0x00000020 */

+#define HSEM_C2ISR_ISF5           HSEM_C2ISR_ISF5_Msk                          /*!<semaphore 5 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF6_Pos       (6U)

+#define HSEM_C2ISR_ISF6_Msk       (0x1UL << HSEM_C2ISR_ISF6_Pos)               /*!< 0x00000040 */

+#define HSEM_C2ISR_ISF6           HSEM_C2ISR_ISF6_Msk                          /*!<semaphore 6 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF7_Pos       (7U)

+#define HSEM_C2ISR_ISF7_Msk       (0x1UL << HSEM_C2ISR_ISF7_Pos)               /*!< 0x00000080 */

+#define HSEM_C2ISR_ISF7           HSEM_C2ISR_ISF7_Msk                          /*!<semaphore 7 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF8_Pos       (8U)

+#define HSEM_C2ISR_ISF8_Msk       (0x1UL << HSEM_C2ISR_ISF8_Pos)               /*!< 0x00000100 */

+#define HSEM_C2ISR_ISF8           HSEM_C2ISR_ISF8_Msk                          /*!<semaphore 8 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF9_Pos       (9U)

+#define HSEM_C2ISR_ISF9_Msk       (0x1UL << HSEM_C2ISR_ISF9_Pos)               /*!< 0x00000200 */

+#define HSEM_C2ISR_ISF9           HSEM_C2ISR_ISF9_Msk                          /*!<semaphore 9 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF10_Pos      (10U)

+#define HSEM_C2ISR_ISF10_Msk      (0x1UL << HSEM_C2ISR_ISF10_Pos)              /*!< 0x00000400 */

+#define HSEM_C2ISR_ISF10          HSEM_C2ISR_ISF10_Msk                         /*!<semaphore 10 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF11_Pos      (11U)

+#define HSEM_C2ISR_ISF11_Msk      (0x1UL << HSEM_C2ISR_ISF11_Pos)              /*!< 0x00000800 */

+#define HSEM_C2ISR_ISF11          HSEM_C2ISR_ISF11_Msk                         /*!<semaphore 11 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF12_Pos      (12U)

+#define HSEM_C2ISR_ISF12_Msk      (0x1UL << HSEM_C2ISR_ISF12_Pos)              /*!< 0x00001000 */

+#define HSEM_C2ISR_ISF12          HSEM_C2ISR_ISF12_Msk                         /*!<semaphore 12 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF13_Pos      (13U)

+#define HSEM_C2ISR_ISF13_Msk      (0x1UL << HSEM_C2ISR_ISF13_Pos)              /*!< 0x00002000 */

+#define HSEM_C2ISR_ISF13          HSEM_C2ISR_ISF13_Msk                         /*!<semaphore 13 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF14_Pos      (14U)

+#define HSEM_C2ISR_ISF14_Msk      (0x1UL << HSEM_C2ISR_ISF14_Pos)              /*!< 0x00004000 */

+#define HSEM_C2ISR_ISF14          HSEM_C2ISR_ISF14_Msk                         /*!<semaphore 14 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF15_Pos      (15U)

+#define HSEM_C2ISR_ISF15_Msk      (0x1UL << HSEM_C2ISR_ISF15_Pos)              /*!< 0x00008000 */

+#define HSEM_C2ISR_ISF15          HSEM_C2ISR_ISF15_Msk                         /*!<semaphore 15 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF16_Pos      (16U)

+#define HSEM_C2ISR_ISF16_Msk      (0x1UL << HSEM_C2ISR_ISF16_Pos)              /*!< 0x00010000 */

+#define HSEM_C2ISR_ISF16          HSEM_C2ISR_ISF16_Msk                         /*!<semaphore 16 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF17_Pos      (17U)

+#define HSEM_C2ISR_ISF17_Msk      (0x1UL << HSEM_C2ISR_ISF17_Pos)              /*!< 0x00020000 */

+#define HSEM_C2ISR_ISF17          HSEM_C2ISR_ISF17_Msk                         /*!<semaphore 17 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF18_Pos      (18U)

+#define HSEM_C2ISR_ISF18_Msk      (0x1UL << HSEM_C2ISR_ISF18_Pos)              /*!< 0x00040000 */

+#define HSEM_C2ISR_ISF18          HSEM_C2ISR_ISF18_Msk                         /*!<semaphore 18 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF19_Pos      (19U)

+#define HSEM_C2ISR_ISF19_Msk      (0x1UL << HSEM_C2ISR_ISF19_Pos)              /*!< 0x00080000 */

+#define HSEM_C2ISR_ISF19          HSEM_C2ISR_ISF19_Msk                         /*!<semaphore 19 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF20_Pos      (20U)

+#define HSEM_C2ISR_ISF20_Msk      (0x1UL << HSEM_C2ISR_ISF20_Pos)              /*!< 0x00100000 */

+#define HSEM_C2ISR_ISF20          HSEM_C2ISR_ISF20_Msk                         /*!<semaphore 20 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF21_Pos      (21U)

+#define HSEM_C2ISR_ISF21_Msk      (0x1UL << HSEM_C2ISR_ISF21_Pos)              /*!< 0x00200000 */

+#define HSEM_C2ISR_ISF21          HSEM_C2ISR_ISF21_Msk                         /*!<semaphore 21 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF22_Pos      (22U)

+#define HSEM_C2ISR_ISF22_Msk      (0x1UL << HSEM_C2ISR_ISF22_Pos)              /*!< 0x00400000 */

+#define HSEM_C2ISR_ISF22          HSEM_C2ISR_ISF22_Msk                         /*!<semaphore 22 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF23_Pos      (23U)

+#define HSEM_C2ISR_ISF23_Msk      (0x1UL << HSEM_C2ISR_ISF23_Pos)              /*!< 0x00800000 */

+#define HSEM_C2ISR_ISF23          HSEM_C2ISR_ISF23_Msk                         /*!<semaphore 23 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF24_Pos      (24U)

+#define HSEM_C2ISR_ISF24_Msk      (0x1UL << HSEM_C2ISR_ISF24_Pos)              /*!< 0x01000000 */

+#define HSEM_C2ISR_ISF24          HSEM_C2ISR_ISF24_Msk                         /*!<semaphore 24 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF25_Pos      (25U)

+#define HSEM_C2ISR_ISF25_Msk      (0x1UL << HSEM_C2ISR_ISF25_Pos)              /*!< 0x02000000 */

+#define HSEM_C2ISR_ISF25          HSEM_C2ISR_ISF25_Msk                         /*!<semaphore 25 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF26_Pos      (26U)

+#define HSEM_C2ISR_ISF26_Msk      (0x1UL << HSEM_C2ISR_ISF26_Pos)              /*!< 0x04000000 */

+#define HSEM_C2ISR_ISF26          HSEM_C2ISR_ISF26_Msk                         /*!<semaphore 26 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF27_Pos      (27U)

+#define HSEM_C2ISR_ISF27_Msk      (0x1UL << HSEM_C2ISR_ISF27_Pos)              /*!< 0x08000000 */

+#define HSEM_C2ISR_ISF27          HSEM_C2ISR_ISF27_Msk                         /*!<semaphore 27 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF28_Pos      (28U)

+#define HSEM_C2ISR_ISF28_Msk      (0x1UL << HSEM_C2ISR_ISF28_Pos)              /*!< 0x10000000 */

+#define HSEM_C2ISR_ISF28          HSEM_C2ISR_ISF28_Msk                         /*!<semaphore 28 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF29_Pos      (29U)

+#define HSEM_C2ISR_ISF29_Msk      (0x1UL << HSEM_C2ISR_ISF29_Pos)              /*!< 0x20000000 */

+#define HSEM_C2ISR_ISF29          HSEM_C2ISR_ISF29_Msk                         /*!<semaphore 29 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF30_Pos      (30U)

+#define HSEM_C2ISR_ISF30_Msk      (0x1UL << HSEM_C2ISR_ISF30_Pos)              /*!< 0x40000000 */

+#define HSEM_C2ISR_ISF30          HSEM_C2ISR_ISF30_Msk                         /*!<semaphore 30 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF31_Pos      (31U)

+#define HSEM_C2ISR_ISF31_Msk      (0x1UL << HSEM_C2ISR_ISF31_Pos)              /*!< 0x80000000 */

+#define HSEM_C2ISR_ISF31          HSEM_C2ISR_ISF31_Msk                         /*!<semaphore 31 interrupt 1 status bit. */

+

+/********************  Bit definition for HSEM_C2MISR register  *****************/

+#define HSEM_C2MISR_MISF0_Pos     (0U)

+#define HSEM_C2MISR_MISF0_Msk     (0x1UL << HSEM_C2MISR_MISF0_Pos)             /*!< 0x00000001 */

+#define HSEM_C2MISR_MISF0         HSEM_C2MISR_MISF0_Msk                        /*!<semaphore 0 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF1_Pos     (1U)

+#define HSEM_C2MISR_MISF1_Msk     (0x1UL << HSEM_C2MISR_MISF1_Pos)             /*!< 0x00000002 */

+#define HSEM_C2MISR_MISF1         HSEM_C2MISR_MISF1_Msk                        /*!<semaphore 1 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF2_Pos     (2U)

+#define HSEM_C2MISR_MISF2_Msk     (0x1UL << HSEM_C2MISR_MISF2_Pos)             /*!< 0x00000004 */

+#define HSEM_C2MISR_MISF2         HSEM_C2MISR_MISF2_Msk                        /*!<semaphore 2 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF3_Pos     (3U)

+#define HSEM_C2MISR_MISF3_Msk     (0x1UL << HSEM_C2MISR_MISF3_Pos)             /*!< 0x00000008 */

+#define HSEM_C2MISR_MISF3         HSEM_C2MISR_MISF3_Msk                        /*!<semaphore 3 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF4_Pos     (4U)

+#define HSEM_C2MISR_MISF4_Msk     (0x1UL << HSEM_C2MISR_MISF4_Pos)             /*!< 0x00000010 */

+#define HSEM_C2MISR_MISF4         HSEM_C2MISR_MISF4_Msk                        /*!<semaphore 4 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF5_Pos     (5U)

+#define HSEM_C2MISR_MISF5_Msk     (0x1UL << HSEM_C2MISR_MISF5_Pos)             /*!< 0x00000020 */

+#define HSEM_C2MISR_MISF5         HSEM_C2MISR_MISF5_Msk                        /*!<semaphore 5 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF6_Pos     (6U)

+#define HSEM_C2MISR_MISF6_Msk     (0x1UL << HSEM_C2MISR_MISF6_Pos)             /*!< 0x00000040 */

+#define HSEM_C2MISR_MISF6         HSEM_C2MISR_MISF6_Msk                        /*!<semaphore 6 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF7_Pos     (7U)

+#define HSEM_C2MISR_MISF7_Msk     (0x1UL << HSEM_C2MISR_MISF7_Pos)             /*!< 0x00000080 */

+#define HSEM_C2MISR_MISF7         HSEM_C2MISR_MISF7_Msk                        /*!<semaphore 7 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF8_Pos     (8U)

+#define HSEM_C2MISR_MISF8_Msk     (0x1UL << HSEM_C2MISR_MISF8_Pos)             /*!< 0x00000100 */

+#define HSEM_C2MISR_MISF8         HSEM_C2MISR_MISF8_Msk                        /*!<semaphore 8 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF9_Pos     (9U)

+#define HSEM_C2MISR_MISF9_Msk     (0x1UL << HSEM_C2MISR_MISF9_Pos)             /*!< 0x00000200 */

+#define HSEM_C2MISR_MISF9         HSEM_C2MISR_MISF9_Msk                        /*!<semaphore 9 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF10_Pos    (10U)

+#define HSEM_C2MISR_MISF10_Msk    (0x1UL << HSEM_C2MISR_MISF10_Pos)            /*!< 0x00000400 */

+#define HSEM_C2MISR_MISF10        HSEM_C2MISR_MISF10_Msk                       /*!<semaphore 10 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF11_Pos    (11U)

+#define HSEM_C2MISR_MISF11_Msk    (0x1UL << HSEM_C2MISR_MISF11_Pos)            /*!< 0x00000800 */

+#define HSEM_C2MISR_MISF11        HSEM_C2MISR_MISF11_Msk                       /*!<semaphore 11 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF12_Pos    (12U)

+#define HSEM_C2MISR_MISF12_Msk    (0x1UL << HSEM_C2MISR_MISF12_Pos)            /*!< 0x00001000 */

+#define HSEM_C2MISR_MISF12        HSEM_C2MISR_MISF12_Msk                       /*!<semaphore 12 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF13_Pos    (13U)

+#define HSEM_C2MISR_MISF13_Msk    (0x1UL << HSEM_C2MISR_MISF13_Pos)            /*!< 0x00002000 */

+#define HSEM_C2MISR_MISF13        HSEM_C2MISR_MISF13_Msk                       /*!<semaphore 13 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF14_Pos    (14U)

+#define HSEM_C2MISR_MISF14_Msk    (0x1UL << HSEM_C2MISR_MISF14_Pos)            /*!< 0x00004000 */

+#define HSEM_C2MISR_MISF14        HSEM_C2MISR_MISF14_Msk                       /*!<semaphore 14 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF15_Pos    (15U)

+#define HSEM_C2MISR_MISF15_Msk    (0x1UL << HSEM_C2MISR_MISF15_Pos)            /*!< 0x00008000 */

+#define HSEM_C2MISR_MISF15        HSEM_C2MISR_MISF15_Msk                       /*!<semaphore 15 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF16_Pos    (16U)

+#define HSEM_C2MISR_MISF16_Msk    (0x1UL << HSEM_C2MISR_MISF16_Pos)            /*!< 0x00010000 */

+#define HSEM_C2MISR_MISF16        HSEM_C2MISR_MISF16_Msk                       /*!<semaphore 16 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF17_Pos    (17U)

+#define HSEM_C2MISR_MISF17_Msk    (0x1UL << HSEM_C2MISR_MISF17_Pos)            /*!< 0x00020000 */

+#define HSEM_C2MISR_MISF17        HSEM_C2MISR_MISF17_Msk                       /*!<semaphore 17 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF18_Pos    (18U)

+#define HSEM_C2MISR_MISF18_Msk    (0x1UL << HSEM_C2MISR_MISF18_Pos)            /*!< 0x00040000 */

+#define HSEM_C2MISR_MISF18        HSEM_C2MISR_MISF18_Msk                       /*!<semaphore 18 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF19_Pos    (19U)

+#define HSEM_C2MISR_MISF19_Msk    (0x1UL << HSEM_C2MISR_MISF19_Pos)            /*!< 0x00080000 */

+#define HSEM_C2MISR_MISF19        HSEM_C2MISR_MISF19_Msk                       /*!<semaphore 19 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF20_Pos    (20U)

+#define HSEM_C2MISR_MISF20_Msk    (0x1UL << HSEM_C2MISR_MISF20_Pos)            /*!< 0x00100000 */

+#define HSEM_C2MISR_MISF20        HSEM_C2MISR_MISF20_Msk                       /*!<semaphore 20 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF21_Pos    (21U)

+#define HSEM_C2MISR_MISF21_Msk    (0x1UL << HSEM_C2MISR_MISF21_Pos)            /*!< 0x00200000 */

+#define HSEM_C2MISR_MISF21        HSEM_C2MISR_MISF21_Msk                       /*!<semaphore 21 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF22_Pos    (22U)

+#define HSEM_C2MISR_MISF22_Msk    (0x1UL << HSEM_C2MISR_MISF22_Pos)            /*!< 0x00400000 */

+#define HSEM_C2MISR_MISF22        HSEM_C2MISR_MISF22_Msk                       /*!<semaphore 22 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF23_Pos    (23U)

+#define HSEM_C2MISR_MISF23_Msk    (0x1UL << HSEM_C2MISR_MISF23_Pos)            /*!< 0x00800000 */

+#define HSEM_C2MISR_MISF23        HSEM_C2MISR_MISF23_Msk                       /*!<semaphore 23 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF24_Pos    (24U)

+#define HSEM_C2MISR_MISF24_Msk    (0x1UL << HSEM_C2MISR_MISF24_Pos)            /*!< 0x01000000 */

+#define HSEM_C2MISR_MISF24        HSEM_C2MISR_MISF24_Msk                       /*!<semaphore 24 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF25_Pos    (25U)

+#define HSEM_C2MISR_MISF25_Msk    (0x1UL << HSEM_C2MISR_MISF25_Pos)            /*!< 0x02000000 */

+#define HSEM_C2MISR_MISF25        HSEM_C2MISR_MISF25_Msk                       /*!<semaphore 25 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF26_Pos    (26U)

+#define HSEM_C2MISR_MISF26_Msk    (0x1UL << HSEM_C2MISR_MISF26_Pos)            /*!< 0x04000000 */

+#define HSEM_C2MISR_MISF26        HSEM_C2MISR_MISF26_Msk                       /*!<semaphore 26 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF27_Pos    (27U)

+#define HSEM_C2MISR_MISF27_Msk    (0x1UL << HSEM_C2MISR_MISF27_Pos)            /*!< 0x08000000 */

+#define HSEM_C2MISR_MISF27        HSEM_C2MISR_MISF27_Msk                       /*!<semaphore 27 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF28_Pos    (28U)

+#define HSEM_C2MISR_MISF28_Msk    (0x1UL << HSEM_C2MISR_MISF28_Pos)            /*!< 0x10000000 */

+#define HSEM_C2MISR_MISF28        HSEM_C2MISR_MISF28_Msk                       /*!<semaphore 28 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF29_Pos    (29U)

+#define HSEM_C2MISR_MISF29_Msk    (0x1UL << HSEM_C2MISR_MISF29_Pos)            /*!< 0x20000000 */

+#define HSEM_C2MISR_MISF29        HSEM_C2MISR_MISF29_Msk                       /*!<semaphore 29 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF30_Pos    (30U)

+#define HSEM_C2MISR_MISF30_Msk    (0x1UL << HSEM_C2MISR_MISF30_Pos)            /*!< 0x40000000 */

+#define HSEM_C2MISR_MISF30        HSEM_C2MISR_MISF30_Msk                       /*!<semaphore 30 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF31_Pos    (31U)

+#define HSEM_C2MISR_MISF31_Msk    (0x1UL << HSEM_C2MISR_MISF31_Pos)            /*!< 0x80000000 */

+#define HSEM_C2MISR_MISF31        HSEM_C2MISR_MISF31_Msk                       /*!<semaphore 31 interrupt 1 masked status bit. */

+/********************  Bit definition for HSEM_CR register  *****************/

+#define HSEM_CR_COREID_Pos        (8U)

+#define HSEM_CR_COREID_Msk        (0xFFUL << HSEM_CR_COREID_Pos)               /*!< 0x0000FF00 */

+#define HSEM_CR_COREID            HSEM_CR_COREID_Msk                           /*!<CoreID of semaphores to be cleared. */

+#define HSEM_CR_KEY_Pos           (16U)

+#define HSEM_CR_KEY_Msk           (0xFFFFUL << HSEM_CR_KEY_Pos)                /*!< 0xFFFF0000 */

+#define HSEM_CR_KEY               HSEM_CR_KEY_Msk                              /*!<semaphores clear key. */

+

+/********************  Bit definition for HSEM_KEYR register  *****************/

+#define HSEM_KEYR_KEY_Pos         (16U)

+#define HSEM_KEYR_KEY_Msk         (0xFFFFUL << HSEM_KEYR_KEY_Pos)              /*!< 0xFFFF0000 */

+#define HSEM_KEYR_KEY             HSEM_KEYR_KEY_Msk                            /*!<semaphores clear key. */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    HASH                                    */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bits definition for HASH_CR register  ********************/

+#define HASH_CR_INIT_Pos          (2U)

+#define HASH_CR_INIT_Msk          (0x1UL << HASH_CR_INIT_Pos)                  /*!< 0x00000004 */

+#define HASH_CR_INIT              HASH_CR_INIT_Msk

+#define HASH_CR_DMAE_Pos          (3U)

+#define HASH_CR_DMAE_Msk          (0x1UL << HASH_CR_DMAE_Pos)                  /*!< 0x00000008 */

+#define HASH_CR_DMAE              HASH_CR_DMAE_Msk

+#define HASH_CR_DATATYPE_Pos      (4U)

+#define HASH_CR_DATATYPE_Msk      (0x3UL << HASH_CR_DATATYPE_Pos)              /*!< 0x00000030 */

+#define HASH_CR_DATATYPE          HASH_CR_DATATYPE_Msk

+#define HASH_CR_DATATYPE_0        (0x1UL << HASH_CR_DATATYPE_Pos)               /*!< 0x00000010 */

+#define HASH_CR_DATATYPE_1        (0x2UL << HASH_CR_DATATYPE_Pos)               /*!< 0x00000020 */

+#define HASH_CR_MODE_Pos          (6U)

+#define HASH_CR_MODE_Msk          (0x1UL << HASH_CR_MODE_Pos)                  /*!< 0x00000040 */

+#define HASH_CR_MODE              HASH_CR_MODE_Msk

+#define HASH_CR_ALGO_Pos          (7U)

+#define HASH_CR_ALGO_Msk          (0x801UL << HASH_CR_ALGO_Pos)                /*!< 0x00040080 */

+#define HASH_CR_ALGO              HASH_CR_ALGO_Msk

+#define HASH_CR_ALGO_0            (0x001UL << HASH_CR_ALGO_Pos)                 /*!< 0x00000080 */

+#define HASH_CR_ALGO_1            (0x800UL << HASH_CR_ALGO_Pos)                 /*!< 0x00040000 */

+#define HASH_CR_NBW_Pos           (8U)

+#define HASH_CR_NBW_Msk           (0xFUL << HASH_CR_NBW_Pos)                   /*!< 0x00000F00 */

+#define HASH_CR_NBW               HASH_CR_NBW_Msk

+#define HASH_CR_NBW_0             (0x1UL << HASH_CR_NBW_Pos)                    /*!< 0x00000100 */

+#define HASH_CR_NBW_1             (0x2UL << HASH_CR_NBW_Pos)                    /*!< 0x00000200 */

+#define HASH_CR_NBW_2             (0x4UL << HASH_CR_NBW_Pos)                    /*!< 0x00000400 */

+#define HASH_CR_NBW_3             (0x8UL << HASH_CR_NBW_Pos)                    /*!< 0x00000800 */

+#define HASH_CR_DINNE_Pos         (12U)

+#define HASH_CR_DINNE_Msk         (0x1UL << HASH_CR_DINNE_Pos)                 /*!< 0x00001000 */

+#define HASH_CR_DINNE             HASH_CR_DINNE_Msk

+#define HASH_CR_MDMAT_Pos         (13U)

+#define HASH_CR_MDMAT_Msk         (0x1UL << HASH_CR_MDMAT_Pos)                 /*!< 0x00002000 */

+#define HASH_CR_MDMAT             HASH_CR_MDMAT_Msk

+#define HASH_CR_LKEY_Pos          (16U)

+#define HASH_CR_LKEY_Msk          (0x1UL << HASH_CR_LKEY_Pos)                  /*!< 0x00010000 */

+#define HASH_CR_LKEY              HASH_CR_LKEY_Msk

+

+/******************  Bits definition for HASH_STR register  *******************/

+#define HASH_STR_NBLW_Pos         (0U)

+#define HASH_STR_NBLW_Msk         (0x1FUL << HASH_STR_NBLW_Pos)                /*!< 0x0000001F */

+#define HASH_STR_NBLW             HASH_STR_NBLW_Msk

+#define HASH_STR_NBLW_0           (0x01UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000001 */

+#define HASH_STR_NBLW_1           (0x02UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000002 */

+#define HASH_STR_NBLW_2           (0x04UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000004 */

+#define HASH_STR_NBLW_3           (0x08UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000008 */

+#define HASH_STR_NBLW_4           (0x10UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000010 */

+#define HASH_STR_DCAL_Pos         (8U)

+#define HASH_STR_DCAL_Msk         (0x1UL << HASH_STR_DCAL_Pos)                 /*!< 0x00000100 */

+#define HASH_STR_DCAL             HASH_STR_DCAL_Msk

+

+/******************  Bits definition for HASH_IMR register  *******************/

+#define HASH_IMR_DINIE_Pos        (0U)

+#define HASH_IMR_DINIE_Msk        (0x1UL << HASH_IMR_DINIE_Pos)                /*!< 0x00000001 */

+#define HASH_IMR_DINIE            HASH_IMR_DINIE_Msk

+#define HASH_IMR_DCIE_Pos         (1U)

+#define HASH_IMR_DCIE_Msk         (0x1UL << HASH_IMR_DCIE_Pos)                 /*!< 0x00000002 */

+#define HASH_IMR_DCIE             HASH_IMR_DCIE_Msk

+

+/******************  Bits definition for HASH_SR register  ********************/

+#define HASH_SR_DINIS_Pos         (0U)

+#define HASH_SR_DINIS_Msk         (0x1UL << HASH_SR_DINIS_Pos)                 /*!< 0x00000001 */

+#define HASH_SR_DINIS             HASH_SR_DINIS_Msk

+#define HASH_SR_DCIS_Pos          (1U)

+#define HASH_SR_DCIS_Msk          (0x1UL << HASH_SR_DCIS_Pos)                  /*!< 0x00000002 */

+#define HASH_SR_DCIS              HASH_SR_DCIS_Msk

+#define HASH_SR_DMAS_Pos          (2U)

+#define HASH_SR_DMAS_Msk          (0x1UL << HASH_SR_DMAS_Pos)                  /*!< 0x00000004 */

+#define HASH_SR_DMAS              HASH_SR_DMAS_Msk

+#define HASH_SR_BUSY_Pos          (3U)

+#define HASH_SR_BUSY_Msk          (0x1UL << HASH_SR_BUSY_Pos)                  /*!< 0x00000008 */

+#define HASH_SR_BUSY              HASH_SR_BUSY_Msk

+/******************************************************************************/

+/*                                                                            */

+/*                      Inter-integrated Circuit Interface (I2C)              */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for I2C_CR1 register  *******************/

+#define I2C_CR1_PE_Pos               (0U)

+#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */

+#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */

+#define I2C_CR1_TXIE_Pos             (1U)

+#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */

+#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */

+#define I2C_CR1_RXIE_Pos             (2U)

+#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */

+#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */

+#define I2C_CR1_ADDRIE_Pos           (3U)

+#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */

+#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */

+#define I2C_CR1_NACKIE_Pos           (4U)

+#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */

+#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */

+#define I2C_CR1_STOPIE_Pos           (5U)

+#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */

+#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */

+#define I2C_CR1_TCIE_Pos             (6U)

+#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */

+#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */

+#define I2C_CR1_ERRIE_Pos            (7U)

+#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */

+#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */

+#define I2C_CR1_DNF_Pos              (8U)

+#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */

+#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */

+#define I2C_CR1_ANFOFF_Pos           (12U)

+#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */

+#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */

+#define I2C_CR1_TXDMAEN_Pos          (14U)

+#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */

+#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */

+#define I2C_CR1_RXDMAEN_Pos          (15U)

+#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */

+#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */

+#define I2C_CR1_SBC_Pos              (16U)

+#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */

+#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */

+#define I2C_CR1_NOSTRETCH_Pos        (17U)

+#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */

+#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */

+#define I2C_CR1_WUPEN_Pos            (18U)

+#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */

+#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */

+#define I2C_CR1_GCEN_Pos             (19U)

+#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */

+#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */

+#define I2C_CR1_SMBHEN_Pos           (20U)

+#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */

+#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */

+#define I2C_CR1_SMBDEN_Pos           (21U)

+#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */

+#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */

+#define I2C_CR1_ALERTEN_Pos          (22U)

+#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */

+#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */

+#define I2C_CR1_PECEN_Pos            (23U)

+#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */

+#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */

+

+/******************  Bit definition for I2C_CR2 register  ********************/

+#define I2C_CR2_SADD_Pos             (0U)

+#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */

+#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */

+#define I2C_CR2_RD_WRN_Pos           (10U)

+#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */

+#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */

+#define I2C_CR2_ADD10_Pos            (11U)

+#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */

+#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */

+#define I2C_CR2_HEAD10R_Pos          (12U)

+#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */

+#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */

+#define I2C_CR2_START_Pos            (13U)

+#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */

+#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */

+#define I2C_CR2_STOP_Pos             (14U)

+#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */

+#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */

+#define I2C_CR2_NACK_Pos             (15U)

+#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */

+#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */

+#define I2C_CR2_NBYTES_Pos           (16U)

+#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */

+#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */

+#define I2C_CR2_RELOAD_Pos           (24U)

+#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */

+#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */

+#define I2C_CR2_AUTOEND_Pos          (25U)

+#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */

+#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */

+#define I2C_CR2_PECBYTE_Pos          (26U)

+#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */

+#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */

+

+/*******************  Bit definition for I2C_OAR1 register  ******************/

+#define I2C_OAR1_OA1_Pos             (0U)

+#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */

+#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */

+#define I2C_OAR1_OA1MODE_Pos         (10U)

+#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */

+#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */

+#define I2C_OAR1_OA1EN_Pos           (15U)

+#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */

+#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */

+

+/*******************  Bit definition for I2C_OAR2 register  ******************/

+#define I2C_OAR2_OA2_Pos             (1U)

+#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */

+#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */

+#define I2C_OAR2_OA2MSK_Pos          (8U)

+#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */

+#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */

+#define I2C_OAR2_OA2NOMASK           0x00000000UL                              /*!< No mask */

+#define I2C_OAR2_OA2MASK01_Pos       (8U)

+#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */

+#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared */

+#define I2C_OAR2_OA2MASK02_Pos       (9U)

+#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */

+#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */

+#define I2C_OAR2_OA2MASK03_Pos       (8U)

+#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */

+#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */

+#define I2C_OAR2_OA2MASK04_Pos       (10U)

+#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */

+#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */

+#define I2C_OAR2_OA2MASK05_Pos       (8U)

+#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */

+#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */

+#define I2C_OAR2_OA2MASK06_Pos       (9U)

+#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */

+#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared */

+#define I2C_OAR2_OA2MASK07_Pos       (8U)

+#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */

+#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done */

+#define I2C_OAR2_OA2EN_Pos           (15U)

+#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */

+#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */

+

+/*******************  Bit definition for I2C_TIMINGR register *******************/

+#define I2C_TIMINGR_SCLL_Pos         (0U)

+#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */

+#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */

+#define I2C_TIMINGR_SCLH_Pos         (8U)

+#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */

+#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */

+#define I2C_TIMINGR_SDADEL_Pos       (16U)

+#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */

+#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */

+#define I2C_TIMINGR_SCLDEL_Pos       (20U)

+#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */

+#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */

+#define I2C_TIMINGR_PRESC_Pos        (28U)

+#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */

+#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */

+

+/******************* Bit definition for I2C_TIMEOUTR register *******************/

+#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)

+#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */

+#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */

+#define I2C_TIMEOUTR_TIDLE_Pos       (12U)

+#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */

+#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */

+#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)

+#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */

+#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */

+#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)

+#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */

+#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/

+#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)

+#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */

+#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */

+

+/******************  Bit definition for I2C_ISR register  *********************/

+#define I2C_ISR_TXE_Pos              (0U)

+#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */

+#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */

+#define I2C_ISR_TXIS_Pos             (1U)

+#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */

+#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */

+#define I2C_ISR_RXNE_Pos             (2U)

+#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */

+#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */

+#define I2C_ISR_ADDR_Pos             (3U)

+#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */

+#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/

+#define I2C_ISR_NACKF_Pos            (4U)

+#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */

+#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */

+#define I2C_ISR_STOPF_Pos            (5U)

+#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */

+#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */

+#define I2C_ISR_TC_Pos               (6U)

+#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */

+#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */

+#define I2C_ISR_TCR_Pos              (7U)

+#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */

+#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */

+#define I2C_ISR_BERR_Pos             (8U)

+#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */

+#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */

+#define I2C_ISR_ARLO_Pos             (9U)

+#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */

+#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */

+#define I2C_ISR_OVR_Pos              (10U)

+#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */

+#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */

+#define I2C_ISR_PECERR_Pos           (11U)

+#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */

+#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */

+#define I2C_ISR_TIMEOUT_Pos          (12U)

+#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */

+#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */

+#define I2C_ISR_ALERT_Pos            (13U)

+#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */

+#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */

+#define I2C_ISR_BUSY_Pos             (15U)

+#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */

+#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */

+#define I2C_ISR_DIR_Pos              (16U)

+#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */

+#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */

+#define I2C_ISR_ADDCODE_Pos          (17U)

+#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */

+#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */

+

+/******************  Bit definition for I2C_ICR register  *********************/

+#define I2C_ICR_ADDRCF_Pos           (3U)

+#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */

+#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */

+#define I2C_ICR_NACKCF_Pos           (4U)

+#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */

+#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */

+#define I2C_ICR_STOPCF_Pos           (5U)

+#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */

+#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */

+#define I2C_ICR_BERRCF_Pos           (8U)

+#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */

+#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */

+#define I2C_ICR_ARLOCF_Pos           (9U)

+#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */

+#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */

+#define I2C_ICR_OVRCF_Pos            (10U)

+#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */

+#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */

+#define I2C_ICR_PECCF_Pos            (11U)

+#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */

+#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */

+#define I2C_ICR_TIMOUTCF_Pos         (12U)

+#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */

+#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */

+#define I2C_ICR_ALERTCF_Pos          (13U)

+#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */

+#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */

+

+/******************  Bit definition for I2C_PECR register  *********************/

+#define I2C_PECR_PEC_Pos             (0U)

+#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */

+#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */

+

+/******************  Bit definition for I2C_RXDR register  *********************/

+#define I2C_RXDR_RXDATA_Pos          (0U)

+#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */

+#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */

+

+/******************  Bit definition for I2C_TXDR register  *********************/

+#define I2C_TXDR_TXDATA_Pos          (0U)

+#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */

+#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           Independent WATCHDOG                             */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for IWDG_KR register  ********************/

+#define IWDG_KR_KEY_Pos      (0U)

+#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */

+#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */

+

+/*******************  Bit definition for IWDG_PR register  ********************/

+#define IWDG_PR_PR_Pos       (0U)

+#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */

+#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */

+#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */

+#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */

+#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */

+

+/*******************  Bit definition for IWDG_RLR register  *******************/

+#define IWDG_RLR_RL_Pos      (0U)

+#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */

+#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */

+

+/*******************  Bit definition for IWDG_SR register  ********************/

+#define IWDG_SR_PVU_Pos      (0U)

+#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */

+#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */

+#define IWDG_SR_RVU_Pos      (1U)

+#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */

+#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */

+#define IWDG_SR_WVU_Pos      (2U)

+#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */

+#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */

+

+/*******************  Bit definition for IWDG_KR register  ********************/

+#define IWDG_WINR_WIN_Pos    (0U)

+#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */

+#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */

+

+/******************************************************************************/

+/*                                                                            */

+/*                        JPEG Encoder/Decoder                                */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for CONFR0 register  ********************/

+#define JPEG_CONFR0_START_Pos           (0U)

+#define JPEG_CONFR0_START_Msk           (0x1UL << JPEG_CONFR0_START_Pos)       /*!< 0x00000001 */

+#define JPEG_CONFR0_START               JPEG_CONFR0_START_Msk                  /*!<Start/Stop bit */

+

+/********************  Bit definition for CONFR1 register  ********************/

+#define JPEG_CONFR1_NF_Pos              (0U)

+#define JPEG_CONFR1_NF_Msk              (0x3UL << JPEG_CONFR1_NF_Pos)          /*!< 0x00000003 */

+#define JPEG_CONFR1_NF                  JPEG_CONFR1_NF_Msk                     /*!<Number of color components */

+#define JPEG_CONFR1_NF_0                (0x1UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000001 */

+#define JPEG_CONFR1_NF_1                (0x2UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000002 */

+#define JPEG_CONFR1_DE_Pos              (3U)

+#define JPEG_CONFR1_DE_Msk              (0x1UL << JPEG_CONFR1_DE_Pos)          /*!< 0x00000008 */

+#define JPEG_CONFR1_DE                  JPEG_CONFR1_DE_Msk                     /*!<Decoding Enable */

+#define JPEG_CONFR1_COLORSPACE_Pos      (4U)

+#define JPEG_CONFR1_COLORSPACE_Msk      (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)  /*!< 0x00000030 */

+#define JPEG_CONFR1_COLORSPACE          JPEG_CONFR1_COLORSPACE_Msk             /*!<Color Space */

+#define JPEG_CONFR1_COLORSPACE_0        (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000010 */

+#define JPEG_CONFR1_COLORSPACE_1        (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000020 */

+#define JPEG_CONFR1_NS_Pos              (6U)

+#define JPEG_CONFR1_NS_Msk              (0x3UL << JPEG_CONFR1_NS_Pos)          /*!< 0x000000C0 */

+#define JPEG_CONFR1_NS                  JPEG_CONFR1_NS_Msk                     /*!<Number of components for Scan */

+#define JPEG_CONFR1_NS_0                (0x1UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR1_NS_1                (0x2UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR1_HDR_Pos             (8U)

+#define JPEG_CONFR1_HDR_Msk             (0x1UL << JPEG_CONFR1_HDR_Pos)         /*!< 0x00000100 */

+#define JPEG_CONFR1_HDR                 JPEG_CONFR1_HDR_Msk                    /*!<Header Processing On/Off */

+#define JPEG_CONFR1_YSIZE_Pos           (16U)

+#define JPEG_CONFR1_YSIZE_Msk           (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)    /*!< 0xFFFF0000 */

+#define JPEG_CONFR1_YSIZE               JPEG_CONFR1_YSIZE_Msk                  /*!<Number of lines in source image */

+

+/********************  Bit definition for CONFR2 register  ********************/

+#define JPEG_CONFR2_NMCU_Pos            (0U)

+#define JPEG_CONFR2_NMCU_Msk            (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)  /*!< 0x03FFFFFF */

+#define JPEG_CONFR2_NMCU                JPEG_CONFR2_NMCU_Msk                   /*!<Number of MCU units minus 1 to encode */

+

+/********************  Bit definition for CONFR3 register  ********************/

+#define JPEG_CONFR3_XSIZE_Pos           (16U)

+#define JPEG_CONFR3_XSIZE_Msk           (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)    /*!< 0xFFFF0000 */

+#define JPEG_CONFR3_XSIZE               JPEG_CONFR3_XSIZE_Msk                  /*!<Number of pixels per line */

+

+/********************  Bit definition for CONFR4 register  ********************/

+#define JPEG_CONFR4_HD_Pos              (0U)

+#define JPEG_CONFR4_HD_Msk              (0x1UL << JPEG_CONFR4_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR4_HD                  JPEG_CONFR4_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR4_HA_Pos              (1U)

+#define JPEG_CONFR4_HA_Msk              (0x1UL << JPEG_CONFR4_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR4_HA                  JPEG_CONFR4_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR4_QT_Pos              (2U)

+#define JPEG_CONFR4_QT_Msk              (0x3UL << JPEG_CONFR4_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR4_QT                  JPEG_CONFR4_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR4_QT_0                (0x1UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR4_QT_1                (0x2UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR4_NB_Pos              (4U)

+#define JPEG_CONFR4_NB_Msk              (0xFUL << JPEG_CONFR4_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR4_NB                  JPEG_CONFR4_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR4_NB_0                (0x1UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR4_NB_1                (0x2UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR4_NB_2                (0x4UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR4_NB_3                (0x8UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR4_VSF_Pos             (8U)

+#define JPEG_CONFR4_VSF_Msk             (0xFUL << JPEG_CONFR4_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR4_VSF                 JPEG_CONFR4_VSF_Msk                    /*!<Vertical sampling factor for component 1 */

+#define JPEG_CONFR4_VSF_0               (0x1UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR4_VSF_1               (0x2UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR4_VSF_2               (0x4UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR4_VSF_3               (0x8UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR4_HSF_Pos             (12U)

+#define JPEG_CONFR4_HSF_Msk             (0xFUL << JPEG_CONFR4_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR4_HSF                 JPEG_CONFR4_HSF_Msk                    /*!<Horizontal sampling factor for component 1 */

+#define JPEG_CONFR4_HSF_0               (0x1UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR4_HSF_1               (0x2UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR4_HSF_2               (0x4UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR4_HSF_3               (0x8UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR5 register  ********************/

+#define JPEG_CONFR5_HD_Pos              (0U)

+#define JPEG_CONFR5_HD_Msk              (0x1UL << JPEG_CONFR5_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR5_HD                  JPEG_CONFR5_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR5_HA_Pos              (1U)

+#define JPEG_CONFR5_HA_Msk              (0x1UL << JPEG_CONFR5_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR5_HA                  JPEG_CONFR5_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR5_QT_Pos              (2U)

+#define JPEG_CONFR5_QT_Msk              (0x3UL << JPEG_CONFR5_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR5_QT                  JPEG_CONFR5_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR5_QT_0                (0x1UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR5_QT_1                (0x2UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR5_NB_Pos              (4U)

+#define JPEG_CONFR5_NB_Msk              (0xFUL << JPEG_CONFR5_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR5_NB                  JPEG_CONFR5_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR5_NB_0                (0x1UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR5_NB_1                (0x2UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR5_NB_2                (0x4UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR5_NB_3                (0x8UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR5_VSF_Pos             (8U)

+#define JPEG_CONFR5_VSF_Msk             (0xFUL << JPEG_CONFR5_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR5_VSF                 JPEG_CONFR5_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR5_VSF_0               (0x1UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR5_VSF_1               (0x2UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR5_VSF_2               (0x4UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR5_VSF_3               (0x8UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR5_HSF_Pos             (12U)

+#define JPEG_CONFR5_HSF_Msk             (0xFUL << JPEG_CONFR5_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR5_HSF                 JPEG_CONFR5_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR5_HSF_0               (0x1UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR5_HSF_1               (0x2UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR5_HSF_2               (0x4UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR5_HSF_3               (0x8UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR6 register  ********************/

+#define JPEG_CONFR6_HD_Pos              (0U)

+#define JPEG_CONFR6_HD_Msk              (0x1UL << JPEG_CONFR6_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR6_HD                  JPEG_CONFR6_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR6_HA_Pos              (1U)

+#define JPEG_CONFR6_HA_Msk              (0x1UL << JPEG_CONFR6_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR6_HA                  JPEG_CONFR6_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR6_QT_Pos              (2U)

+#define JPEG_CONFR6_QT_Msk              (0x3UL << JPEG_CONFR6_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR6_QT                  JPEG_CONFR6_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR6_QT_0                (0x1UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR6_QT_1                (0x2UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR6_NB_Pos              (4U)

+#define JPEG_CONFR6_NB_Msk              (0xFUL << JPEG_CONFR6_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR6_NB                  JPEG_CONFR6_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR6_NB_0                (0x1UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR6_NB_1                (0x2UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR6_NB_2                (0x4UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR6_NB_3                (0x8UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR6_VSF_Pos             (8U)

+#define JPEG_CONFR6_VSF_Msk             (0xFUL << JPEG_CONFR6_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR6_VSF                 JPEG_CONFR6_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR6_VSF_0               (0x1UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR6_VSF_1               (0x2UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR6_VSF_2               (0x4UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR6_VSF_3               (0x8UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR6_HSF_Pos             (12U)

+#define JPEG_CONFR6_HSF_Msk             (0xFUL << JPEG_CONFR6_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR6_HSF                 JPEG_CONFR6_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR6_HSF_0               (0x1UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR6_HSF_1               (0x2UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR6_HSF_2               (0x4UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR6_HSF_3               (0x8UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR7 register  ********************/

+#define JPEG_CONFR7_HD_Pos              (0U)

+#define JPEG_CONFR7_HD_Msk              (0x1UL << JPEG_CONFR7_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR7_HD                  JPEG_CONFR7_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR7_HA_Pos              (1U)

+#define JPEG_CONFR7_HA_Msk              (0x1UL << JPEG_CONFR7_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR7_HA                  JPEG_CONFR7_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR7_QT_Pos              (2U)

+#define JPEG_CONFR7_QT_Msk              (0x3UL << JPEG_CONFR7_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR7_QT                  JPEG_CONFR7_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR7_QT_0                (0x1UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR7_QT_1                (0x2UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR7_NB_Pos              (4U)

+#define JPEG_CONFR7_NB_Msk              (0xFUL << JPEG_CONFR7_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR7_NB                  JPEG_CONFR7_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR7_NB_0                (0x1UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR7_NB_1                (0x2UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR7_NB_2                (0x4UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR7_NB_3                (0x8UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR7_VSF_Pos             (8U)

+#define JPEG_CONFR7_VSF_Msk             (0xFUL << JPEG_CONFR7_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR7_VSF                 JPEG_CONFR7_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR7_VSF_0               (0x1UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR7_VSF_1               (0x2UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR7_VSF_2               (0x4UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR7_VSF_3               (0x8UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR7_HSF_Pos             (12U)

+#define JPEG_CONFR7_HSF_Msk             (0xFUL << JPEG_CONFR7_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR7_HSF                 JPEG_CONFR7_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR7_HSF_0               (0x1UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR7_HSF_1               (0x2UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR7_HSF_2               (0x4UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR7_HSF_3               (0x8UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CR register  ********************/

+#define JPEG_CR_JCEN_Pos                (0U)

+#define JPEG_CR_JCEN_Msk                (0x1UL << JPEG_CR_JCEN_Pos)            /*!< 0x00000001 */

+#define JPEG_CR_JCEN                    JPEG_CR_JCEN_Msk                       /*!<Enable the JPEG Codec Core */

+#define JPEG_CR_IFTIE_Pos               (1U)

+#define JPEG_CR_IFTIE_Msk               (0x1UL << JPEG_CR_IFTIE_Pos)           /*!< 0x00000002 */

+#define JPEG_CR_IFTIE                   JPEG_CR_IFTIE_Msk                      /*!<Input FIFO Threshold Interrupt Enable */

+#define JPEG_CR_IFNFIE_Pos              (2U)

+#define JPEG_CR_IFNFIE_Msk              (0x1UL << JPEG_CR_IFNFIE_Pos)          /*!< 0x00000004 */

+#define JPEG_CR_IFNFIE                  JPEG_CR_IFNFIE_Msk                     /*!<Input FIFO Not Full Interrupt Enable */

+#define JPEG_CR_OFTIE_Pos               (3U)

+#define JPEG_CR_OFTIE_Msk               (0x1UL << JPEG_CR_OFTIE_Pos)           /*!< 0x00000008 */

+#define JPEG_CR_OFTIE                   JPEG_CR_OFTIE_Msk                      /*!<Output FIFO Threshold Interrupt Enable */

+#define JPEG_CR_OFNEIE_Pos              (4U)

+#define JPEG_CR_OFNEIE_Msk              (0x1UL << JPEG_CR_OFNEIE_Pos)          /*!< 0x00000010 */

+#define JPEG_CR_OFNEIE                  JPEG_CR_OFNEIE_Msk                     /*!<Output FIFO Not Empty Interrupt Enable */

+#define JPEG_CR_EOCIE_Pos               (5U)

+#define JPEG_CR_EOCIE_Msk               (0x1UL << JPEG_CR_EOCIE_Pos)           /*!< 0x00000020 */

+#define JPEG_CR_EOCIE                   JPEG_CR_EOCIE_Msk                      /*!<End of Conversion Interrupt Enable */

+#define JPEG_CR_HPDIE_Pos               (6U)

+#define JPEG_CR_HPDIE_Msk               (0x1UL << JPEG_CR_HPDIE_Pos)           /*!< 0x00000040 */

+#define JPEG_CR_HPDIE                   JPEG_CR_HPDIE_Msk                      /*!<Header Parsing Done Interrupt Enable */

+#define JPEG_CR_IFF_Pos                 (13U)

+#define JPEG_CR_IFF_Msk                 (0x1UL << JPEG_CR_IFF_Pos)             /*!< 0x00002000 */

+#define JPEG_CR_IFF                     JPEG_CR_IFF_Msk                        /*!<Flush the input FIFO */

+#define JPEG_CR_OFF_Pos                 (14U)

+#define JPEG_CR_OFF_Msk                 (0x1UL << JPEG_CR_OFF_Pos)             /*!< 0x00004000 */

+#define JPEG_CR_OFF                     JPEG_CR_OFF_Msk                        /*!<Flush the output FIFO */

+

+/********************  Bit definition for SR register  ********************/

+#define JPEG_SR_IFTF_Pos                (1U)

+#define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */

+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is bellow its threshold flag */

+#define JPEG_SR_IFNFF_Pos               (2U)

+#define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */

+#define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */

+#define JPEG_SR_OFTF_Pos                (3U)

+#define JPEG_SR_OFTF_Msk                (0x1UL << JPEG_SR_OFTF_Pos)            /*!< 0x00000008 */

+#define JPEG_SR_OFTF                    JPEG_SR_OFTF_Msk                       /*!<Output FIFO is not empty and has reach its threshold */

+#define JPEG_SR_OFNEF_Pos               (4U)

+#define JPEG_SR_OFNEF_Msk               (0x1UL << JPEG_SR_OFNEF_Pos)           /*!< 0x00000010 */

+#define JPEG_SR_OFNEF                   JPEG_SR_OFNEF_Msk                      /*!<Output FIFO is not empty, a data is available */

+#define JPEG_SR_EOCF_Pos                (5U)

+#define JPEG_SR_EOCF_Msk                (0x1UL << JPEG_SR_EOCF_Pos)            /*!< 0x00000020 */

+#define JPEG_SR_EOCF                    JPEG_SR_EOCF_Msk                       /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */

+#define JPEG_SR_HPDF_Pos                (6U)

+#define JPEG_SR_HPDF_Msk                (0x1UL << JPEG_SR_HPDF_Pos)            /*!< 0x00000040 */

+#define JPEG_SR_HPDF                    JPEG_SR_HPDF_Msk                       /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */

+#define JPEG_SR_COF_Pos                 (7U)

+#define JPEG_SR_COF_Msk                 (0x1UL << JPEG_SR_COF_Pos)             /*!< 0x00000080 */

+#define JPEG_SR_COF                     JPEG_SR_COF_Msk                        /*!<JPEG Codec operation on going flag */

+

+/********************  Bit definition for CFR register  ********************/

+#define JPEG_CFR_CEOCF_Pos              (4U)

+#define JPEG_CFR_CEOCF_Msk              (0x1UL << JPEG_CFR_CEOCF_Pos)          /*!< 0x00000010 */

+#define JPEG_CFR_CEOCF                  JPEG_CFR_CEOCF_Msk                     /*!<Clear End of Conversion Flag */

+#define JPEG_CFR_CHPDF_Pos              (5U)

+#define JPEG_CFR_CHPDF_Msk              (0x1UL << JPEG_CFR_CHPDF_Pos)          /*!< 0x00000020 */

+#define JPEG_CFR_CHPDF                  JPEG_CFR_CHPDF_Msk                     /*!<Clear Header Parsing Done Flag */

+

+/********************  Bit definition for DIR register  ********************/

+#define JPEG_DIR_DATAIN_Pos             (0U)

+#define JPEG_DIR_DATAIN_Msk             (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)  /*!< 0xFFFFFFFF */

+#define JPEG_DIR_DATAIN                 JPEG_DIR_DATAIN_Msk                    /*!<Data Input FIFO */

+

+/********************  Bit definition for DOR register  ********************/

+#define JPEG_DOR_DATAOUT_Pos            (0U)

+#define JPEG_DOR_DATAOUT_Msk            (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */

+#define JPEG_DOR_DATAOUT                JPEG_DOR_DATAOUT_Msk                   /*!<Data Output FIFO */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      LCD-TFT Display Controller (LTDC)                     */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for LTDC_SSCR register  *****************/

+

+#define LTDC_SSCR_VSH_Pos            (0U)

+#define LTDC_SSCR_VSH_Msk            (0x7FFUL << LTDC_SSCR_VSH_Pos)            /*!< 0x000007FF */

+#define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height  */

+#define LTDC_SSCR_HSW_Pos            (16U)

+#define LTDC_SSCR_HSW_Msk            (0xFFFUL << LTDC_SSCR_HSW_Pos)            /*!< 0x0FFF0000 */

+#define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */

+

+/********************  Bit definition for LTDC_BPCR register  *****************/

+

+#define LTDC_BPCR_AVBP_Pos           (0U)

+#define LTDC_BPCR_AVBP_Msk           (0x7FFUL << LTDC_BPCR_AVBP_Pos)           /*!< 0x000007FF */

+#define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch   */

+#define LTDC_BPCR_AHBP_Pos           (16U)

+#define LTDC_BPCR_AHBP_Msk           (0xFFFUL << LTDC_BPCR_AHBP_Pos)           /*!< 0x0FFF0000 */

+#define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */

+

+/********************  Bit definition for LTDC_AWCR register  *****************/

+

+#define LTDC_AWCR_AAH_Pos            (0U)

+#define LTDC_AWCR_AAH_Msk            (0x7FFUL << LTDC_AWCR_AAH_Pos)            /*!< 0x000007FF */

+#define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active heigh */

+#define LTDC_AWCR_AAW_Pos            (16U)

+#define LTDC_AWCR_AAW_Msk            (0xFFFUL << LTDC_AWCR_AAW_Pos)            /*!< 0x0FFF0000 */

+#define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */

+

+/********************  Bit definition for LTDC_TWCR register  *****************/

+

+#define LTDC_TWCR_TOTALH_Pos         (0U)

+#define LTDC_TWCR_TOTALH_Msk         (0x7FFUL << LTDC_TWCR_TOTALH_Pos)         /*!< 0x000007FF */

+#define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total Heigh */

+#define LTDC_TWCR_TOTALW_Pos         (16U)

+#define LTDC_TWCR_TOTALW_Msk         (0xFFFUL << LTDC_TWCR_TOTALW_Pos)         /*!< 0x0FFF0000 */

+#define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */

+

+/********************  Bit definition for LTDC_GCR register  ******************/

+

+#define LTDC_GCR_LTDCEN_Pos          (0U)

+#define LTDC_GCR_LTDCEN_Msk          (0x1UL << LTDC_GCR_LTDCEN_Pos)            /*!< 0x00000001 */

+#define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit       */

+#define LTDC_GCR_DBW_Pos             (4U)

+#define LTDC_GCR_DBW_Msk             (0x7UL << LTDC_GCR_DBW_Pos)               /*!< 0x00000070 */

+#define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width                   */

+#define LTDC_GCR_DGW_Pos             (8U)

+#define LTDC_GCR_DGW_Msk             (0x7UL << LTDC_GCR_DGW_Pos)               /*!< 0x00000700 */

+#define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width                  */

+#define LTDC_GCR_DRW_Pos             (12U)

+#define LTDC_GCR_DRW_Msk             (0x7UL << LTDC_GCR_DRW_Pos)               /*!< 0x00007000 */

+#define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width                    */

+#define LTDC_GCR_DEN_Pos             (16U)

+#define LTDC_GCR_DEN_Msk             (0x1UL << LTDC_GCR_DEN_Pos)               /*!< 0x00010000 */

+#define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable                       */

+#define LTDC_GCR_PCPOL_Pos           (28U)

+#define LTDC_GCR_PCPOL_Msk           (0x1UL << LTDC_GCR_PCPOL_Pos)             /*!< 0x10000000 */

+#define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity                */

+#define LTDC_GCR_DEPOL_Pos           (29U)

+#define LTDC_GCR_DEPOL_Msk           (0x1UL << LTDC_GCR_DEPOL_Pos)             /*!< 0x20000000 */

+#define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity                */

+#define LTDC_GCR_VSPOL_Pos           (30U)

+#define LTDC_GCR_VSPOL_Msk           (0x1UL << LTDC_GCR_VSPOL_Pos)             /*!< 0x40000000 */

+#define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity   */

+#define LTDC_GCR_HSPOL_Pos           (31U)

+#define LTDC_GCR_HSPOL_Msk           (0x1UL << LTDC_GCR_HSPOL_Pos)             /*!< 0x80000000 */

+#define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */

+

+

+/********************  Bit definition for LTDC_SRCR register  *****************/

+

+#define LTDC_SRCR_IMR_Pos            (0U)

+#define LTDC_SRCR_IMR_Msk            (0x1UL << LTDC_SRCR_IMR_Pos)              /*!< 0x00000001 */

+#define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload         */

+#define LTDC_SRCR_VBR_Pos            (1U)

+#define LTDC_SRCR_VBR_Msk            (0x1UL << LTDC_SRCR_VBR_Pos)              /*!< 0x00000002 */

+#define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */

+

+/********************  Bit definition for LTDC_BCCR register  *****************/

+

+#define LTDC_BCCR_BCBLUE_Pos         (0U)

+#define LTDC_BCCR_BCBLUE_Msk         (0xFFUL << LTDC_BCCR_BCBLUE_Pos)          /*!< 0x000000FF */

+#define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value  */

+#define LTDC_BCCR_BCGREEN_Pos        (8U)

+#define LTDC_BCCR_BCGREEN_Msk        (0xFFUL << LTDC_BCCR_BCGREEN_Pos)         /*!< 0x0000FF00 */

+#define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */

+#define LTDC_BCCR_BCRED_Pos          (16U)

+#define LTDC_BCCR_BCRED_Msk          (0xFFUL << LTDC_BCCR_BCRED_Pos)           /*!< 0x00FF0000 */

+#define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value   */

+

+/********************  Bit definition for LTDC_IER register  ******************/

+

+#define LTDC_IER_LIE_Pos             (0U)

+#define LTDC_IER_LIE_Msk             (0x1UL << LTDC_IER_LIE_Pos)               /*!< 0x00000001 */

+#define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable            */

+#define LTDC_IER_FUIE_Pos            (1U)

+#define LTDC_IER_FUIE_Msk            (0x1UL << LTDC_IER_FUIE_Pos)              /*!< 0x00000002 */

+#define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable   */

+#define LTDC_IER_TERRIE_Pos          (2U)

+#define LTDC_IER_TERRIE_Msk          (0x1UL << LTDC_IER_TERRIE_Pos)            /*!< 0x00000004 */

+#define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable  */

+#define LTDC_IER_RRIE_Pos            (3U)

+#define LTDC_IER_RRIE_Msk            (0x1UL << LTDC_IER_RRIE_Pos)              /*!< 0x00000008 */

+#define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */

+

+/********************  Bit definition for LTDC_ISR register  ******************/

+

+#define LTDC_ISR_LIF_Pos             (0U)

+#define LTDC_ISR_LIF_Msk             (0x1UL << LTDC_ISR_LIF_Pos)               /*!< 0x00000001 */

+#define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */

+#define LTDC_ISR_FUIF_Pos            (1U)

+#define LTDC_ISR_FUIF_Msk            (0x1UL << LTDC_ISR_FUIF_Pos)              /*!< 0x00000002 */

+#define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */

+#define LTDC_ISR_TERRIF_Pos          (2U)

+#define LTDC_ISR_TERRIF_Msk          (0x1UL << LTDC_ISR_TERRIF_Pos)            /*!< 0x00000004 */

+#define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */

+#define LTDC_ISR_RRIF_Pos            (3U)

+#define LTDC_ISR_RRIF_Msk            (0x1UL << LTDC_ISR_RRIF_Pos)              /*!< 0x00000008 */

+#define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */

+

+/********************  Bit definition for LTDC_ICR register  ******************/

+

+#define LTDC_ICR_CLIF_Pos            (0U)

+#define LTDC_ICR_CLIF_Msk            (0x1UL << LTDC_ICR_CLIF_Pos)              /*!< 0x00000001 */

+#define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */

+#define LTDC_ICR_CFUIF_Pos           (1U)

+#define LTDC_ICR_CFUIF_Msk           (0x1UL << LTDC_ICR_CFUIF_Pos)             /*!< 0x00000002 */

+#define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */

+#define LTDC_ICR_CTERRIF_Pos         (2U)

+#define LTDC_ICR_CTERRIF_Msk         (0x1UL << LTDC_ICR_CTERRIF_Pos)           /*!< 0x00000004 */

+#define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */

+#define LTDC_ICR_CRRIF_Pos           (3U)

+#define LTDC_ICR_CRRIF_Msk           (0x1UL << LTDC_ICR_CRRIF_Pos)             /*!< 0x00000008 */

+#define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */

+

+/********************  Bit definition for LTDC_LIPCR register  ****************/

+

+#define LTDC_LIPCR_LIPOS_Pos         (0U)

+#define LTDC_LIPCR_LIPOS_Msk         (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)         /*!< 0x000007FF */

+#define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */

+

+/********************  Bit definition for LTDC_CPSR register  *****************/

+

+#define LTDC_CPSR_CYPOS_Pos          (0U)

+#define LTDC_CPSR_CYPOS_Msk          (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)         /*!< 0x0000FFFF */

+#define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */

+#define LTDC_CPSR_CXPOS_Pos          (16U)

+#define LTDC_CPSR_CXPOS_Msk          (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)         /*!< 0xFFFF0000 */

+#define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */

+

+/********************  Bit definition for LTDC_CDSR register  *****************/

+

+#define LTDC_CDSR_VDES_Pos           (0U)

+#define LTDC_CDSR_VDES_Msk           (0x1UL << LTDC_CDSR_VDES_Pos)             /*!< 0x00000001 */

+#define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status       */

+#define LTDC_CDSR_HDES_Pos           (1U)

+#define LTDC_CDSR_HDES_Msk           (0x1UL << LTDC_CDSR_HDES_Pos)             /*!< 0x00000002 */

+#define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status     */

+#define LTDC_CDSR_VSYNCS_Pos         (2U)

+#define LTDC_CDSR_VSYNCS_Msk         (0x1UL << LTDC_CDSR_VSYNCS_Pos)           /*!< 0x00000004 */

+#define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status   */

+#define LTDC_CDSR_HSYNCS_Pos         (3U)

+#define LTDC_CDSR_HSYNCS_Msk         (0x1UL << LTDC_CDSR_HSYNCS_Pos)           /*!< 0x00000008 */

+#define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */

+

+/********************  Bit definition for LTDC_LxCR register  *****************/

+

+#define LTDC_LxCR_LEN_Pos            (0U)

+#define LTDC_LxCR_LEN_Msk            (0x1UL << LTDC_LxCR_LEN_Pos)              /*!< 0x00000001 */

+#define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable              */

+#define LTDC_LxCR_COLKEN_Pos         (1U)

+#define LTDC_LxCR_COLKEN_Msk         (0x1UL << LTDC_LxCR_COLKEN_Pos)           /*!< 0x00000002 */

+#define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable       */

+#define LTDC_LxCR_CLUTEN_Pos         (4U)

+#define LTDC_LxCR_CLUTEN_Msk         (0x1UL << LTDC_LxCR_CLUTEN_Pos)           /*!< 0x00000010 */

+#define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */

+

+/********************  Bit definition for LTDC_LxWHPCR register  **************/

+

+#define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)

+#define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)     /*!< 0x00000FFF */

+#define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */

+#define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)

+#define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)    /*!< 0xFFFF0000 */

+#define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position  */

+

+/********************  Bit definition for LTDC_LxWVPCR register  **************/

+

+#define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)

+#define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)     /*!< 0x00000FFF */

+#define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */

+#define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)

+#define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)    /*!< 0xFFFF0000 */

+#define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position  */

+

+/********************  Bit definition for LTDC_LxCKCR register  ***************/

+

+#define LTDC_LxCKCR_CKBLUE_Pos       (0U)

+#define LTDC_LxCKCR_CKBLUE_Msk       (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value  */

+#define LTDC_LxCKCR_CKGREEN_Pos      (8U)

+#define LTDC_LxCKCR_CKGREEN_Msk      (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */

+#define LTDC_LxCKCR_CKRED_Pos        (16U)

+#define LTDC_LxCKCR_CKRED_Msk        (0xFFUL << LTDC_LxCKCR_CKRED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value   */

+

+/********************  Bit definition for LTDC_LxPFCR register  ***************/

+

+#define LTDC_LxPFCR_PF_Pos           (0U)

+#define LTDC_LxPFCR_PF_Msk           (0x7UL << LTDC_LxPFCR_PF_Pos)             /*!< 0x00000007 */

+#define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */

+

+/********************  Bit definition for LTDC_LxCACR register  ***************/

+

+#define LTDC_LxCACR_CONSTA_Pos       (0U)

+#define LTDC_LxCACR_CONSTA_Msk       (0xFFUL << LTDC_LxCACR_CONSTA_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */

+

+/********************  Bit definition for LTDC_LxDCCR register  ***************/

+

+#define LTDC_LxDCCR_DCBLUE_Pos       (0U)

+#define LTDC_LxDCCR_DCBLUE_Msk       (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue  */

+#define LTDC_LxDCCR_DCGREEN_Pos      (8U)

+#define LTDC_LxDCCR_DCGREEN_Msk      (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */

+#define LTDC_LxDCCR_DCRED_Pos        (16U)

+#define LTDC_LxDCCR_DCRED_Msk        (0xFFUL << LTDC_LxDCCR_DCRED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red   */

+#define LTDC_LxDCCR_DCALPHA_Pos      (24U)

+#define LTDC_LxDCCR_DCALPHA_Msk      (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)       /*!< 0xFF000000 */

+#define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */

+

+/********************  Bit definition for LTDC_LxBFCR register  ***************/

+

+#define LTDC_LxBFCR_BF2_Pos          (0U)

+#define LTDC_LxBFCR_BF2_Msk          (0x7UL << LTDC_LxBFCR_BF2_Pos)            /*!< 0x00000007 */

+#define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */

+#define LTDC_LxBFCR_BF1_Pos          (8U)

+#define LTDC_LxBFCR_BF1_Msk          (0x7UL << LTDC_LxBFCR_BF1_Pos)            /*!< 0x00000700 */

+#define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */

+

+/********************  Bit definition for LTDC_LxCFBAR register  **************/

+

+#define LTDC_LxCFBAR_CFBADD_Pos      (0U)

+#define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */

+#define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */

+

+/********************  Bit definition for LTDC_LxCFBLR register  **************/

+

+#define LTDC_LxCFBLR_CFBLL_Pos       (0U)

+#define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)      /*!< 0x00001FFF */

+#define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length    */

+#define LTDC_LxCFBLR_CFBP_Pos        (16U)

+#define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)       /*!< 0x1FFF0000 */

+#define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */

+

+/********************  Bit definition for LTDC_LxCFBLNR register  *************/

+

+#define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)

+#define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)    /*!< 0x000007FF */

+#define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */

+

+/********************  Bit definition for LTDC_LxCLUTWR register  *************/

+

+#define LTDC_LxCLUTWR_BLUE_Pos       (0U)

+#define LTDC_LxCLUTWR_BLUE_Msk       (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value   */

+#define LTDC_LxCLUTWR_GREEN_Pos      (8U)

+#define LTDC_LxCLUTWR_GREEN_Msk      (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value  */

+#define LTDC_LxCLUTWR_RED_Pos        (16U)

+#define LTDC_LxCLUTWR_RED_Msk        (0xFFUL << LTDC_LxCLUTWR_RED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value    */

+#define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)

+#define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)     /*!< 0xFF000000 */

+#define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                     MDMA                                   */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for MDMA_GISR0 register  ****************/

+#define MDMA_GISR0_GIF0_Pos       (0U)

+#define MDMA_GISR0_GIF0_Msk       (0x1UL << MDMA_GISR0_GIF0_Pos)               /*!< 0x00000001 */

+#define MDMA_GISR0_GIF0           MDMA_GISR0_GIF0_Msk                          /*!< Channel 0 global interrupt flag */

+#define MDMA_GISR0_GIF1_Pos       (1U)

+#define MDMA_GISR0_GIF1_Msk       (0x1UL << MDMA_GISR0_GIF1_Pos)               /*!< 0x00000002 */

+#define MDMA_GISR0_GIF1           MDMA_GISR0_GIF1_Msk                          /*!< Channel 1 global interrupt flag */

+#define MDMA_GISR0_GIF2_Pos       (2U)

+#define MDMA_GISR0_GIF2_Msk       (0x1UL << MDMA_GISR0_GIF2_Pos)               /*!< 0x00000004 */

+#define MDMA_GISR0_GIF2           MDMA_GISR0_GIF2_Msk                          /*!< Channel 2 global interrupt flag */

+#define MDMA_GISR0_GIF3_Pos       (3U)

+#define MDMA_GISR0_GIF3_Msk       (0x1UL << MDMA_GISR0_GIF3_Pos)               /*!< 0x00000008 */

+#define MDMA_GISR0_GIF3           MDMA_GISR0_GIF3_Msk                          /*!< Channel 3 global interrupt flag */

+#define MDMA_GISR0_GIF4_Pos       (4U)

+#define MDMA_GISR0_GIF4_Msk       (0x1UL << MDMA_GISR0_GIF4_Pos)               /*!< 0x00000010 */

+#define MDMA_GISR0_GIF4           MDMA_GISR0_GIF4_Msk                          /*!< Channel 4 global interrupt flag */

+#define MDMA_GISR0_GIF5_Pos       (5U)

+#define MDMA_GISR0_GIF5_Msk       (0x1UL << MDMA_GISR0_GIF5_Pos)               /*!< 0x00000020 */

+#define MDMA_GISR0_GIF5           MDMA_GISR0_GIF5_Msk                          /*!< Channel 5 global interrupt flag */

+#define MDMA_GISR0_GIF6_Pos       (6U)

+#define MDMA_GISR0_GIF6_Msk       (0x1UL << MDMA_GISR0_GIF6_Pos)               /*!< 0x00000040 */

+#define MDMA_GISR0_GIF6           MDMA_GISR0_GIF6_Msk                          /*!< Channel 6 global interrupt flag */

+#define MDMA_GISR0_GIF7_Pos       (7U)

+#define MDMA_GISR0_GIF7_Msk       (0x1UL << MDMA_GISR0_GIF7_Pos)               /*!< 0x00000080 */

+#define MDMA_GISR0_GIF7           MDMA_GISR0_GIF7_Msk                          /*!< Channel 7 global interrupt flag */

+#define MDMA_GISR0_GIF8_Pos       (8U)

+#define MDMA_GISR0_GIF8_Msk       (0x1UL << MDMA_GISR0_GIF8_Pos)               /*!< 0x00000100 */

+#define MDMA_GISR0_GIF8           MDMA_GISR0_GIF8_Msk                          /*!< Channel 8 global interrupt flag */

+#define MDMA_GISR0_GIF9_Pos       (9U)

+#define MDMA_GISR0_GIF9_Msk       (0x1UL << MDMA_GISR0_GIF9_Pos)               /*!< 0x00000200 */

+#define MDMA_GISR0_GIF9           MDMA_GISR0_GIF9_Msk                          /*!< Channel 9 global interrupt flag */

+#define MDMA_GISR0_GIF10_Pos      (10U)

+#define MDMA_GISR0_GIF10_Msk      (0x1UL << MDMA_GISR0_GIF10_Pos)              /*!< 0x00000400 */

+#define MDMA_GISR0_GIF10          MDMA_GISR0_GIF10_Msk                         /*!< Channel 10 global interrupt flag */

+#define MDMA_GISR0_GIF11_Pos      (11U)

+#define MDMA_GISR0_GIF11_Msk      (0x1UL << MDMA_GISR0_GIF11_Pos)              /*!< 0x00000800 */

+#define MDMA_GISR0_GIF11          MDMA_GISR0_GIF11_Msk                         /*!< Channel 11 global interrupt flag */

+#define MDMA_GISR0_GIF12_Pos      (12U)

+#define MDMA_GISR0_GIF12_Msk      (0x1UL << MDMA_GISR0_GIF12_Pos)              /*!< 0x00001000 */

+#define MDMA_GISR0_GIF12          MDMA_GISR0_GIF12_Msk                         /*!< Channel 12 global interrupt flag */

+#define MDMA_GISR0_GIF13_Pos      (13U)

+#define MDMA_GISR0_GIF13_Msk      (0x1UL << MDMA_GISR0_GIF13_Pos)              /*!< 0x00002000 */

+#define MDMA_GISR0_GIF13          MDMA_GISR0_GIF13_Msk                         /*!< Channel 13 global interrupt flag */

+#define MDMA_GISR0_GIF14_Pos      (14U)

+#define MDMA_GISR0_GIF14_Msk      (0x1UL << MDMA_GISR0_GIF14_Pos)              /*!< 0x00004000 */

+#define MDMA_GISR0_GIF14          MDMA_GISR0_GIF14_Msk                         /*!< Channel 14 global interrupt flag */

+#define MDMA_GISR0_GIF15_Pos      (15U)

+#define MDMA_GISR0_GIF15_Msk      (0x1UL << MDMA_GISR0_GIF15_Pos)              /*!< 0x00008000 */

+#define MDMA_GISR0_GIF15          MDMA_GISR0_GIF15_Msk                         /*!< Channel 15 global interrupt flag */

+

+/********************  Bit definition for MDMA_CxISR register  ****************/

+#define MDMA_CISR_TEIF_Pos        (0U)

+#define MDMA_CISR_TEIF_Msk        (0x1UL << MDMA_CISR_TEIF_Pos)                /*!< 0x00000001 */

+#define MDMA_CISR_TEIF            MDMA_CISR_TEIF_Msk                           /*!< Channel x transfer error interrupt flag */

+#define MDMA_CISR_CTCIF_Pos       (1U)

+#define MDMA_CISR_CTCIF_Msk       (0x1UL << MDMA_CISR_CTCIF_Pos)               /*!< 0x00000002 */

+#define MDMA_CISR_CTCIF           MDMA_CISR_CTCIF_Msk                          /*!< Channel x Channel Transfer Complete interrupt flag */

+#define MDMA_CISR_BRTIF_Pos       (2U)

+#define MDMA_CISR_BRTIF_Msk       (0x1UL << MDMA_CISR_BRTIF_Pos)               /*!< 0x00000004 */

+#define MDMA_CISR_BRTIF           MDMA_CISR_BRTIF_Msk                          /*!< Channel x block repeat transfer complete interrupt flag */

+#define MDMA_CISR_BTIF_Pos        (3U)

+#define MDMA_CISR_BTIF_Msk        (0x1UL << MDMA_CISR_BTIF_Pos)                /*!< 0x00000008 */

+#define MDMA_CISR_BTIF            MDMA_CISR_BTIF_Msk                           /*!< Channel x block transfer complete interrupt flag */

+#define MDMA_CISR_TCIF_Pos        (4U)

+#define MDMA_CISR_TCIF_Msk        (0x1UL << MDMA_CISR_TCIF_Pos)                /*!< 0x00000010 */

+#define MDMA_CISR_TCIF            MDMA_CISR_TCIF_Msk                           /*!< Channel x buffer transfer complete interrupt flag */

+#define MDMA_CISR_CRQA_Pos        (16U)

+#define MDMA_CISR_CRQA_Msk        (0x1UL << MDMA_CISR_CRQA_Pos)                /*!< 0x00010000 */

+#define MDMA_CISR_CRQA            MDMA_CISR_CRQA_Msk                           /*!< Channel x ReQest Active flag */

+

+/********************  Bit definition for MDMA_CxIFCR register  ****************/

+#define MDMA_CIFCR_CTEIF_Pos      (0U)

+#define MDMA_CIFCR_CTEIF_Msk      (0x1UL << MDMA_CIFCR_CTEIF_Pos)              /*!< 0x00000001 */

+#define MDMA_CIFCR_CTEIF          MDMA_CIFCR_CTEIF_Msk                         /*!< Channel x clear transfer error interrupt flag */

+#define MDMA_CIFCR_CCTCIF_Pos     (1U)

+#define MDMA_CIFCR_CCTCIF_Msk     (0x1UL << MDMA_CIFCR_CCTCIF_Pos)             /*!< 0x00000002 */

+#define MDMA_CIFCR_CCTCIF         MDMA_CIFCR_CCTCIF_Msk                        /*!< Clear Channel transfer complete interrupt flag for channel x */

+#define MDMA_CIFCR_CBRTIF_Pos     (2U)

+#define MDMA_CIFCR_CBRTIF_Msk     (0x1UL << MDMA_CIFCR_CBRTIF_Pos)             /*!< 0x00000004 */

+#define MDMA_CIFCR_CBRTIF         MDMA_CIFCR_CBRTIF_Msk                        /*!< Channel x clear block repeat transfer complete interrupt flag */

+#define MDMA_CIFCR_CBTIF_Pos      (3U)

+#define MDMA_CIFCR_CBTIF_Msk      (0x1UL << MDMA_CIFCR_CBTIF_Pos)              /*!< 0x00000008 */

+#define MDMA_CIFCR_CBTIF          MDMA_CIFCR_CBTIF_Msk                         /*!< Channel x Clear block transfer complete interrupt flag */

+#define MDMA_CIFCR_CLTCIF_Pos     (4U)

+#define MDMA_CIFCR_CLTCIF_Msk     (0x1UL << MDMA_CIFCR_CLTCIF_Pos)             /*!< 0x00000010 */

+#define MDMA_CIFCR_CLTCIF         MDMA_CIFCR_CLTCIF_Msk                        /*!< CLear Transfer buffer Complete Interrupt Flag for channel */

+

+/********************  Bit definition for MDMA_CxESR register  ****************/

+#define MDMA_CESR_TEA_Pos         (0U)

+#define MDMA_CESR_TEA_Msk         (0x7FUL << MDMA_CESR_TEA_Pos)                /*!< 0x0000007F */

+#define MDMA_CESR_TEA             MDMA_CESR_TEA_Msk                            /*!< Transfer Error Address */

+#define MDMA_CESR_TED_Pos         (7U)

+#define MDMA_CESR_TED_Msk         (0x1UL << MDMA_CESR_TED_Pos)                 /*!< 0x00000080 */

+#define MDMA_CESR_TED             MDMA_CESR_TED_Msk                            /*!< Transfer Error Direction */

+#define MDMA_CESR_TELD_Pos        (8U)

+#define MDMA_CESR_TELD_Msk        (0x1UL << MDMA_CESR_TELD_Pos)                /*!< 0x00000100 */

+#define MDMA_CESR_TELD            MDMA_CESR_TELD_Msk                           /*!< Transfer Error Link Data */

+#define MDMA_CESR_TEMD_Pos        (9U)

+#define MDMA_CESR_TEMD_Msk        (0x1UL << MDMA_CESR_TEMD_Pos)                /*!< 0x00000200 */

+#define MDMA_CESR_TEMD            MDMA_CESR_TEMD_Msk                           /*!< Transfer Error Mask Data */

+#define MDMA_CESR_ASE_Pos         (10U)

+#define MDMA_CESR_ASE_Msk         (0x1UL << MDMA_CESR_ASE_Pos)                 /*!< 0x00000400 */

+#define MDMA_CESR_ASE             MDMA_CESR_ASE_Msk                            /*!< Address/Size Error       */

+#define MDMA_CESR_BSE_Pos         (11U)

+#define MDMA_CESR_BSE_Msk         (0x1UL << MDMA_CESR_BSE_Pos)                 /*!< 0x00000800 */

+#define MDMA_CESR_BSE             MDMA_CESR_BSE_Msk                            /*!< Block Size Error         */

+

+/********************  Bit definition for MDMA_CxCR register  ****************/

+#define MDMA_CCR_EN_Pos           (0U)

+#define MDMA_CCR_EN_Msk           (0x1UL << MDMA_CCR_EN_Pos)                   /*!< 0x00000001 */

+#define MDMA_CCR_EN               MDMA_CCR_EN_Msk                              /*!< Channel enable / flag channel ready when read low */

+#define MDMA_CCR_TEIE_Pos         (1U)

+#define MDMA_CCR_TEIE_Msk         (0x1UL << MDMA_CCR_TEIE_Pos)                 /*!< 0x00000002 */

+#define MDMA_CCR_TEIE             MDMA_CCR_TEIE_Msk                            /*!< Transfer error interrupt enable */

+#define MDMA_CCR_CTCIE_Pos        (2U)

+#define MDMA_CCR_CTCIE_Msk        (0x1UL << MDMA_CCR_CTCIE_Pos)                /*!< 0x00000004 */

+#define MDMA_CCR_CTCIE            MDMA_CCR_CTCIE_Msk                           /*!< Channel Transfer Complete interrupt enable */

+#define MDMA_CCR_BRTIE_Pos        (3U)

+#define MDMA_CCR_BRTIE_Msk        (0x1UL << MDMA_CCR_BRTIE_Pos)                /*!< 0x00000008 */

+#define MDMA_CCR_BRTIE            MDMA_CCR_BRTIE_Msk                           /*!< Block Repeat transfer interrupt enable */

+#define MDMA_CCR_BTIE_Pos         (4U)

+#define MDMA_CCR_BTIE_Msk         (0x1UL << MDMA_CCR_BTIE_Pos)                 /*!< 0x00000010 */

+#define MDMA_CCR_BTIE             MDMA_CCR_BTIE_Msk                            /*!< Block Transfer interrupt enable */

+#define MDMA_CCR_TCIE_Pos         (5U)

+#define MDMA_CCR_TCIE_Msk         (0x1UL << MDMA_CCR_TCIE_Pos)                 /*!< 0x00000020 */

+#define MDMA_CCR_TCIE             MDMA_CCR_TCIE_Msk                            /*!< buffer Transfer Complete interrupt enable */

+#define MDMA_CCR_PL_Pos           (6U)

+#define MDMA_CCR_PL_Msk           (0x3UL << MDMA_CCR_PL_Pos)                   /*!< 0x000000C0 */

+#define MDMA_CCR_PL               MDMA_CCR_PL_Msk                              /*!< Priority level */

+#define MDMA_CCR_PL_0             (0x1UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000040 */

+#define MDMA_CCR_PL_1             (0x2UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000080 */

+#define MDMA_CCR_BEX_Pos          (12U)

+#define MDMA_CCR_BEX_Msk          (0x1UL << MDMA_CCR_BEX_Pos)                  /*!< 0x00001000 */

+#define MDMA_CCR_BEX              MDMA_CCR_BEX_Msk                             /*!< Byte Endianess eXchange */

+#define MDMA_CCR_HEX_Pos          (13U)

+#define MDMA_CCR_HEX_Msk          (0x1UL << MDMA_CCR_HEX_Pos)                  /*!< 0x00002000 */

+#define MDMA_CCR_HEX              MDMA_CCR_HEX_Msk                             /*!< Half word Endianess eXchange */

+#define MDMA_CCR_WEX_Pos          (14U)

+#define MDMA_CCR_WEX_Msk          (0x1UL << MDMA_CCR_WEX_Pos)                  /*!< 0x00004000 */

+#define MDMA_CCR_WEX              MDMA_CCR_WEX_Msk                             /*!< Word Endianess eXchange */

+#define MDMA_CCR_SWRQ_Pos         (16U)

+#define MDMA_CCR_SWRQ_Msk         (0x1UL << MDMA_CCR_SWRQ_Pos)                 /*!< 0x00010000 */

+#define MDMA_CCR_SWRQ             MDMA_CCR_SWRQ_Msk                            /*!< SW ReQuest */

+

+/********************  Bit definition for MDMA_CxTCR register  ****************/

+#define MDMA_CTCR_SINC_Pos        (0U)

+#define MDMA_CTCR_SINC_Msk        (0x3UL << MDMA_CTCR_SINC_Pos)                /*!< 0x00000003 */

+#define MDMA_CTCR_SINC            MDMA_CTCR_SINC_Msk                           /*!< Source increment mode */

+#define MDMA_CTCR_SINC_0          (0x1UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000001 */

+#define MDMA_CTCR_SINC_1          (0x2UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000002 */

+#define MDMA_CTCR_DINC_Pos        (2U)

+#define MDMA_CTCR_DINC_Msk        (0x3UL << MDMA_CTCR_DINC_Pos)                /*!< 0x0000000C */

+#define MDMA_CTCR_DINC            MDMA_CTCR_DINC_Msk                           /*!< Source increment mode */

+#define MDMA_CTCR_DINC_0          (0x1UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000004 */

+#define MDMA_CTCR_DINC_1          (0x2UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000008 */

+#define MDMA_CTCR_SSIZE_Pos       (4U)

+#define MDMA_CTCR_SSIZE_Msk       (0x3UL << MDMA_CTCR_SSIZE_Pos)               /*!< 0x00000030 */

+#define MDMA_CTCR_SSIZE           MDMA_CTCR_SSIZE_Msk                          /*!< Source data size */

+#define MDMA_CTCR_SSIZE_0         (0x1UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000010 */

+#define MDMA_CTCR_SSIZE_1         (0x2UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000020 */

+#define MDMA_CTCR_DSIZE_Pos       (6U)

+#define MDMA_CTCR_DSIZE_Msk       (0x3UL << MDMA_CTCR_DSIZE_Pos)               /*!< 0x000000C0 */

+#define MDMA_CTCR_DSIZE           MDMA_CTCR_DSIZE_Msk                          /*!< Destination data size */

+#define MDMA_CTCR_DSIZE_0         (0x1UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000040 */

+#define MDMA_CTCR_DSIZE_1         (0x2UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000080 */

+#define MDMA_CTCR_SINCOS_Pos      (8U)

+#define MDMA_CTCR_SINCOS_Msk      (0x3UL << MDMA_CTCR_SINCOS_Pos)              /*!< 0x00000300 */

+#define MDMA_CTCR_SINCOS          MDMA_CTCR_SINCOS_Msk                         /*!< Source increment offset size */

+#define MDMA_CTCR_SINCOS_0        (0x1UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000100 */

+#define MDMA_CTCR_SINCOS_1        (0x2UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000200 */

+#define MDMA_CTCR_DINCOS_Pos      (10U)

+#define MDMA_CTCR_DINCOS_Msk      (0x3UL << MDMA_CTCR_DINCOS_Pos)              /*!< 0x00000C00 */

+#define MDMA_CTCR_DINCOS          MDMA_CTCR_DINCOS_Msk                         /*!< Destination increment offset size */

+#define MDMA_CTCR_DINCOS_0        (0x1UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000400 */

+#define MDMA_CTCR_DINCOS_1        (0x2UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000800 */

+#define MDMA_CTCR_SBURST_Pos      (12U)

+#define MDMA_CTCR_SBURST_Msk      (0x7UL << MDMA_CTCR_SBURST_Pos)              /*!< 0x00007000 */

+#define MDMA_CTCR_SBURST          MDMA_CTCR_SBURST_Msk                         /*!< Source burst transfer configuration */

+#define MDMA_CTCR_SBURST_0        (0x1UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00001000 */

+#define MDMA_CTCR_SBURST_1        (0x2UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00002000 */

+#define MDMA_CTCR_SBURST_2        (0x4UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00004000 */

+#define MDMA_CTCR_DBURST_Pos      (15U)

+#define MDMA_CTCR_DBURST_Msk      (0x7UL << MDMA_CTCR_DBURST_Pos)              /*!< 0x00038000 */

+#define MDMA_CTCR_DBURST          MDMA_CTCR_DBURST_Msk                         /*!< Destination burst transfer configuration */

+#define MDMA_CTCR_DBURST_0        (0x1UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00008000 */

+#define MDMA_CTCR_DBURST_1        (0x2UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00010000 */

+#define MDMA_CTCR_DBURST_2        (0x4UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00020000 */

+#define MDMA_CTCR_TLEN_Pos        (18U)

+#define MDMA_CTCR_TLEN_Msk        (0x7FUL << MDMA_CTCR_TLEN_Pos)               /*!< 0x01FC0000 */

+#define MDMA_CTCR_TLEN            MDMA_CTCR_TLEN_Msk                           /*!< buffer Transfer Length (number of bytes - 1) */

+#define MDMA_CTCR_PKE_Pos         (25U)

+#define MDMA_CTCR_PKE_Msk         (0x1UL << MDMA_CTCR_PKE_Pos)                 /*!< 0x02000000 */

+#define MDMA_CTCR_PKE             MDMA_CTCR_PKE_Msk                            /*!< PacK Enable */

+#define MDMA_CTCR_PAM_Pos         (26U)

+#define MDMA_CTCR_PAM_Msk         (0x3UL << MDMA_CTCR_PAM_Pos)                 /*!< 0x0C000000 */

+#define MDMA_CTCR_PAM             MDMA_CTCR_PAM_Msk                            /*!< Padding/Alignement Mode */

+#define MDMA_CTCR_PAM_0           (0x1UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x4000000 */

+#define MDMA_CTCR_PAM_1           (0x2UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x8000000 */

+#define MDMA_CTCR_TRGM_Pos        (28U)

+#define MDMA_CTCR_TRGM_Msk        (0x3UL << MDMA_CTCR_TRGM_Pos)                /*!< 0x30000000 */

+#define MDMA_CTCR_TRGM            MDMA_CTCR_TRGM_Msk                           /*!< Trigger Mode */

+#define MDMA_CTCR_TRGM_0          (0x1UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x10000000 */

+#define MDMA_CTCR_TRGM_1          (0x2UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x20000000 */

+#define MDMA_CTCR_SWRM_Pos        (30U)

+#define MDMA_CTCR_SWRM_Msk        (0x1UL << MDMA_CTCR_SWRM_Pos)                /*!< 0x40000000 */

+#define MDMA_CTCR_SWRM            MDMA_CTCR_SWRM_Msk                           /*!< SW Request Mode */

+#define MDMA_CTCR_BWM_Pos         (31U)

+#define MDMA_CTCR_BWM_Msk         (0x1UL << MDMA_CTCR_BWM_Pos)                 /*!< 0x80000000 */

+#define MDMA_CTCR_BWM             MDMA_CTCR_BWM_Msk                            /*!< Bufferable Write Mode */

+

+/********************  Bit definition for MDMA_CxBNDTR register  ****************/

+#define MDMA_CBNDTR_BNDT_Pos      (0U)

+#define MDMA_CBNDTR_BNDT_Msk      (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos)          /*!< 0x0001FFFF */

+#define MDMA_CBNDTR_BNDT          MDMA_CBNDTR_BNDT_Msk                         /*!< Block Number of data bytes to transfer */

+#define MDMA_CBNDTR_BRSUM_Pos     (18U)

+#define MDMA_CBNDTR_BRSUM_Msk     (0x1UL << MDMA_CBNDTR_BRSUM_Pos)             /*!< 0x00040000 */

+#define MDMA_CBNDTR_BRSUM         MDMA_CBNDTR_BRSUM_Msk                        /*!< Block Repeat Source address Update Mode */

+#define MDMA_CBNDTR_BRDUM_Pos     (19U)

+#define MDMA_CBNDTR_BRDUM_Msk     (0x1UL << MDMA_CBNDTR_BRDUM_Pos)             /*!< 0x00080000 */

+#define MDMA_CBNDTR_BRDUM         MDMA_CBNDTR_BRDUM_Msk                        /*!< Block Repeat Destination address Update Mode */

+#define MDMA_CBNDTR_BRC_Pos       (20U)

+#define MDMA_CBNDTR_BRC_Msk       (0xFFFUL << MDMA_CBNDTR_BRC_Pos)             /*!< 0xFFF00000 */

+#define MDMA_CBNDTR_BRC           MDMA_CBNDTR_BRC_Msk                          /*!< Block Repeat Count */

+

+/********************  Bit definition for MDMA_CxSAR register  ****************/

+#define MDMA_CSAR_SAR_Pos         (0U)

+#define MDMA_CSAR_SAR_Msk         (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CSAR_SAR             MDMA_CSAR_SAR_Msk                            /*!< Source address */

+

+/********************  Bit definition for MDMA_CxDAR register  ****************/

+#define MDMA_CDAR_DAR_Pos         (0U)

+#define MDMA_CDAR_DAR_Msk         (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CDAR_DAR             MDMA_CDAR_DAR_Msk                            /*!< Destination address */

+

+/********************  Bit definition for MDMA_CxBRUR  ************************/

+#define MDMA_CBRUR_SUV_Pos        (0U)

+#define MDMA_CBRUR_SUV_Msk        (0xFFFFUL << MDMA_CBRUR_SUV_Pos)             /*!< 0x0000FFFF */

+#define MDMA_CBRUR_SUV            MDMA_CBRUR_SUV_Msk                           /*!< Source address Update Value */

+#define MDMA_CBRUR_DUV_Pos        (16U)

+#define MDMA_CBRUR_DUV_Msk        (0xFFFFUL << MDMA_CBRUR_DUV_Pos)             /*!< 0xFFFF0000 */

+#define MDMA_CBRUR_DUV            MDMA_CBRUR_DUV_Msk                           /*!< Destination address Update Value */

+

+/********************  Bit definition for MDMA_CxLAR  *************************/

+#define MDMA_CLAR_LAR_Pos         (0U)

+#define MDMA_CLAR_LAR_Msk         (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CLAR_LAR             MDMA_CLAR_LAR_Msk                            /*!< Link Address Register */

+

+/********************  Bit definition for MDMA_CxTBR)  ************************/

+#define MDMA_CTBR_TSEL_Pos        (0U)

+#define MDMA_CTBR_TSEL_Msk        (0xFFUL << MDMA_CTBR_TSEL_Pos)               /*!< 0x000000FF */

+#define MDMA_CTBR_TSEL            MDMA_CTBR_TSEL_Msk                           /*!< Trigger SELection */

+#define MDMA_CTBR_SBUS_Pos        (16U)

+#define MDMA_CTBR_SBUS_Msk        (0x1UL << MDMA_CTBR_SBUS_Pos)                /*!< 0x00010000 */

+#define MDMA_CTBR_SBUS            MDMA_CTBR_SBUS_Msk                           /*!< Source BUS select */

+#define MDMA_CTBR_DBUS_Pos        (17U)

+#define MDMA_CTBR_DBUS_Msk        (0x1UL << MDMA_CTBR_DBUS_Pos)                /*!< 0x00020000 */

+#define MDMA_CTBR_DBUS            MDMA_CTBR_DBUS_Msk                           /*!< Destination BUS select */

+

+/********************  Bit definition for MDMA_CxMAR)  ************************/

+#define MDMA_CMAR_MAR_Pos         (0U)

+#define MDMA_CMAR_MAR_Msk         (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CMAR_MAR             MDMA_CMAR_MAR_Msk                            /*!< Mask address */

+

+/********************  Bit definition for MDMA_CxMDR)  ************************/

+#define MDMA_CMDR_MDR_Pos         (0U)

+#define MDMA_CMDR_MDR_Msk         (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CMDR_MDR             MDMA_CMDR_MDR_Msk                            /*!< Mask Data */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Operational Amplifier (OPAMP)                      */

+/*                                                                            */

+/******************************************************************************/

+/*********************  Bit definition for OPAMPx_CSR register  ***************/

+#define OPAMP_CSR_OPAMPxEN_Pos           (0U)

+#define OPAMP_CSR_OPAMPxEN_Msk           (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)     /*!< 0x00000001 */

+#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */

+#define OPAMP_CSR_FORCEVP_Pos            (1U)

+#define OPAMP_CSR_FORCEVP_Msk            (0x1UL << OPAMP_CSR_FORCEVP_Pos)      /*!< 0x00000002 */

+#define OPAMP_CSR_FORCEVP                OPAMP_CSR_FORCEVP_Msk                 /*!< Force internal reference on VP */

+

+#define OPAMP_CSR_VPSEL_Pos              (2U)

+#define OPAMP_CSR_VPSEL_Msk              (0x3UL << OPAMP_CSR_VPSEL_Pos)        /*!< 0x0000000C */

+#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */

+#define OPAMP_CSR_VPSEL_0                (0x1UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000004 */

+#define OPAMP_CSR_VPSEL_1                (0x2UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000008 */

+

+#define OPAMP_CSR_VMSEL_Pos              (5U)

+#define OPAMP_CSR_VMSEL_Msk              (0x3UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000060 */

+#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */

+#define OPAMP_CSR_VMSEL_0                (0x1UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000020 */

+#define OPAMP_CSR_VMSEL_1                (0x2UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000040 */

+

+#define OPAMP_CSR_OPAHSM_Pos             (8U)

+#define OPAMP_CSR_OPAHSM_Msk             (0x1UL << OPAMP_CSR_OPAHSM_Pos)       /*!< 0x00000100 */

+#define OPAMP_CSR_OPAHSM                 OPAMP_CSR_OPAHSM_Msk                  /*!< Operational amplifier high speed mode */

+#define OPAMP_CSR_CALON_Pos              (11U)

+#define OPAMP_CSR_CALON_Msk              (0x1UL << OPAMP_CSR_CALON_Pos)        /*!< 0x00000800 */

+#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */

+

+#define OPAMP_CSR_CALSEL_Pos             (12U)

+#define OPAMP_CSR_CALSEL_Msk             (0x3UL << OPAMP_CSR_CALSEL_Pos)       /*!< 0x00003000 */

+#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */

+#define OPAMP_CSR_CALSEL_0               (0x1UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00001000 */

+#define OPAMP_CSR_CALSEL_1               (0x2UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */

+

+#define OPAMP_CSR_PGGAIN_Pos             (14U)

+#define OPAMP_CSR_PGGAIN_Msk             (0xFUL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x0003C000 */

+#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */

+#define OPAMP_CSR_PGGAIN_0               (0x1UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00004000 */

+#define OPAMP_CSR_PGGAIN_1               (0x2UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00008000 */

+#define OPAMP_CSR_PGGAIN_2               (0x4UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00010000 */

+#define OPAMP_CSR_PGGAIN_3               (0x8UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00020000 */

+

+#define OPAMP_CSR_USERTRIM_Pos           (18U)

+#define OPAMP_CSR_USERTRIM_Msk           (0x1UL << OPAMP_CSR_USERTRIM_Pos)     /*!< 0x00040000 */

+#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */

+#define OPAMP_CSR_TSTREF_Pos             (29U)

+#define OPAMP_CSR_TSTREF_Msk             (0x1UL << OPAMP_CSR_TSTREF_Pos)       /*!< 0x20000000 */

+#define OPAMP_CSR_TSTREF                 OPAMP_CSR_TSTREF_Msk                  /*!< OpAmp calibration reference voltage output control */

+#define OPAMP_CSR_CALOUT_Pos             (30U)

+#define OPAMP_CSR_CALOUT_Msk             (0x1UL << OPAMP_CSR_CALOUT_Pos)       /*!< 0x40000000 */

+#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier calibration output */

+

+/*********************  Bit definition for OPAMP1_CSR register  ***************/

+#define OPAMP1_CSR_OPAEN_Pos              (0U)

+#define OPAMP1_CSR_OPAEN_Msk              (0x1UL << OPAMP1_CSR_OPAEN_Pos)      /*!< 0x00000001 */

+#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */

+#define OPAMP1_CSR_FORCEVP_Pos            (1U)

+#define OPAMP1_CSR_FORCEVP_Msk            (0x1UL << OPAMP1_CSR_FORCEVP_Pos)    /*!< 0x00000002 */

+#define OPAMP1_CSR_FORCEVP                OPAMP1_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */

+

+#define OPAMP1_CSR_VPSEL_Pos              (2U)

+#define OPAMP1_CSR_VPSEL_Msk              (0x3UL << OPAMP1_CSR_VPSEL_Pos)      /*!< 0x0000000C */

+#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */

+#define OPAMP1_CSR_VPSEL_0                (0x1UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000004 */

+#define OPAMP1_CSR_VPSEL_1                (0x2UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000008 */

+

+#define OPAMP1_CSR_VMSEL_Pos              (5U)

+#define OPAMP1_CSR_VMSEL_Msk              (0x3UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000060 */

+#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */

+#define OPAMP1_CSR_VMSEL_0                (0x1UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000020 */

+#define OPAMP1_CSR_VMSEL_1                (0x2UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000040 */

+

+#define OPAMP1_CSR_OPAHSM_Pos             (8U)

+#define OPAMP1_CSR_OPAHSM_Msk             (0x1UL << OPAMP1_CSR_OPAHSM_Pos)     /*!< 0x00000100 */

+#define OPAMP1_CSR_OPAHSM                 OPAMP1_CSR_OPAHSM_Msk                /*!< Operational amplifier1 high speed mode */

+#define OPAMP1_CSR_CALON_Pos              (11U)

+#define OPAMP1_CSR_CALON_Msk              (0x1UL << OPAMP1_CSR_CALON_Pos)      /*!< 0x00000800 */

+#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */

+

+#define OPAMP1_CSR_CALSEL_Pos             (12U)

+#define OPAMP1_CSR_CALSEL_Msk             (0x3UL << OPAMP1_CSR_CALSEL_Pos)     /*!< 0x00003000 */

+#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */

+#define OPAMP1_CSR_CALSEL_0               (0x1UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00001000 */

+#define OPAMP1_CSR_CALSEL_1               (0x2UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */

+

+#define OPAMP1_CSR_PGGAIN_Pos             (14U)

+#define OPAMP1_CSR_PGGAIN_Msk             (0xFUL << OPAMP1_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */

+#define OPAMP1_CSR_PGGAIN                 OPAMP1_CSR_PGGAIN_Msk                /*!< Operational amplifier1 Programmable amplifier gain value */

+#define OPAMP1_CSR_PGGAIN_0               (0x1UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00004000 */

+#define OPAMP1_CSR_PGGAIN_1               (0x2UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00008000 */

+#define OPAMP1_CSR_PGGAIN_2               (0x4UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00010000 */

+#define OPAMP1_CSR_PGGAIN_3               (0x8UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00020000 */

+

+#define OPAMP1_CSR_USERTRIM_Pos           (18U)

+#define OPAMP1_CSR_USERTRIM_Msk           (0x1UL << OPAMP1_CSR_USERTRIM_Pos)   /*!< 0x00040000 */

+#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */

+#define OPAMP1_CSR_TSTREF_Pos             (29U)

+#define OPAMP1_CSR_TSTREF_Msk             (0x1UL << OPAMP1_CSR_TSTREF_Pos)     /*!< 0x20000000 */

+#define OPAMP1_CSR_TSTREF                 OPAMP1_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */

+#define OPAMP1_CSR_CALOUT_Pos             (30U)

+#define OPAMP1_CSR_CALOUT_Msk             (0x1UL << OPAMP1_CSR_CALOUT_Pos)     /*!< 0x40000000 */

+#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */

+

+/*********************  Bit definition for OPAMP2_CSR register  ***************/

+#define OPAMP2_CSR_OPAEN_Pos              (0U)

+#define OPAMP2_CSR_OPAEN_Msk              (0x1UL << OPAMP2_CSR_OPAEN_Pos)      /*!< 0x00000001 */

+#define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */

+#define OPAMP2_CSR_FORCEVP_Pos            (1U)

+#define OPAMP2_CSR_FORCEVP_Msk            (0x1UL << OPAMP2_CSR_FORCEVP_Pos)    /*!< 0x00000002 */

+#define OPAMP2_CSR_FORCEVP                OPAMP2_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */

+

+#define OPAMP2_CSR_VPSEL_Pos              (2U)

+#define OPAMP2_CSR_VPSEL_Msk              (0x3UL << OPAMP2_CSR_VPSEL_Pos)      /*!< 0x0000000C */

+#define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */

+#define OPAMP2_CSR_VPSEL_0                (0x1UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000004 */

+#define OPAMP2_CSR_VPSEL_1                (0x2UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000008 */

+

+#define OPAMP2_CSR_VMSEL_Pos              (5U)

+#define OPAMP2_CSR_VMSEL_Msk              (0x3UL << OPAMP2_CSR_VMSEL_Pos)      /*!< 0x00000060 */

+#define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */

+#define OPAMP2_CSR_VMSEL_0                (0x1UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000020 */

+#define OPAMP2_CSR_VMSEL_1                (0x2UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000040 */

+

+#define OPAMP2_CSR_OPAHSM_Pos             (8U)

+#define OPAMP2_CSR_OPAHSM_Msk             (0x1UL << OPAMP2_CSR_OPAHSM_Pos)     /*!< 0x00000100 */

+#define OPAMP2_CSR_OPAHSM                 OPAMP2_CSR_OPAHSM_Msk                /*!< Operational amplifier2 high speed mode */

+#define OPAMP2_CSR_CALON_Pos              (11U)

+#define OPAMP2_CSR_CALON_Msk              (0x1UL << OPAMP2_CSR_CALON_Pos)      /*!< 0x00000800 */

+#define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */

+

+#define OPAMP2_CSR_CALSEL_Pos             (12U)

+#define OPAMP2_CSR_CALSEL_Msk             (0x3UL << OPAMP2_CSR_CALSEL_Pos)     /*!< 0x00003000 */

+#define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */

+#define OPAMP2_CSR_CALSEL_0               (0x1UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00001000 */

+#define OPAMP2_CSR_CALSEL_1               (0x2UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */

+

+#define OPAMP2_CSR_PGGAIN_Pos             (14U)

+#define OPAMP2_CSR_PGGAIN_Msk             (0xFUL << OPAMP2_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */

+#define OPAMP2_CSR_PGGAIN                 OPAMP2_CSR_PGGAIN_Msk                /*!< Operational amplifier2 Programmable amplifier gain value */

+#define OPAMP2_CSR_PGGAIN_0               (0x1UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00004000 */

+#define OPAMP2_CSR_PGGAIN_1               (0x2UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00008000 */

+#define OPAMP2_CSR_PGGAIN_2               (0x4UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00010000 */

+#define OPAMP2_CSR_PGGAIN_3               (0x8UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00020000 */

+

+#define OPAMP2_CSR_USERTRIM_Pos           (18U)

+#define OPAMP2_CSR_USERTRIM_Msk           (0x1UL << OPAMP2_CSR_USERTRIM_Pos)   /*!< 0x00040000 */

+#define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */

+#define OPAMP2_CSR_TSTREF_Pos             (29U)

+#define OPAMP2_CSR_TSTREF_Msk             (0x1UL << OPAMP2_CSR_TSTREF_Pos)     /*!< 0x20000000 */

+#define OPAMP2_CSR_TSTREF                 OPAMP2_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */

+#define OPAMP2_CSR_CALOUT_Pos             (30U)

+#define OPAMP2_CSR_CALOUT_Msk             (0x1UL << OPAMP2_CSR_CALOUT_Pos)     /*!< 0x40000000 */

+#define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */

+

+/*******************  Bit definition for OPAMP_OTR register  ******************/

+#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */

+#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP1_OTR register  ******************/

+#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */

+#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP2_OTR register  ******************/

+#define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */

+#define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP_HSOTR register  ****************/

+#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP_HSOTR_TRIMHSOFFSETN        OPAMP_HSOTR_TRIMHSOFFSETN_Msk         /*!< Trim for NMOS differential pairs */

+#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP_HSOTR_TRIMHSOFFSETP        OPAMP_HSOTR_TRIMHSOFFSETP_Msk         /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP1_HSOTR register  ****************/

+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP1_HSOTR_TRIMHSOFFSETN        OPAMP1_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */

+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP1_HSOTR_TRIMHSOFFSETP        OPAMP1_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP2_HSOTR register  ****************/

+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP2_HSOTR_TRIMHSOFFSETN        OPAMP2_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */

+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP2_HSOTR_TRIMHSOFFSETP        OPAMP2_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             Power Control                                  */

+/*                                                                            */

+/******************************************************************************/

+/*************************  NUMBER OF POWER DOMAINS  **************************/

+#define POWER_DOMAINS_NUMBER           3U                                      /*!< 3 Domains */

+

+/********************  Bit definition for PWR_CR1 register  *******************/

+#define PWR_CR1_ALS_Pos                (17U)

+#define PWR_CR1_ALS_Msk                (0x3UL << PWR_CR1_ALS_Pos)              /*!< 0x00060000 */

+#define PWR_CR1_ALS                    PWR_CR1_ALS_Msk                         /*!< Analog Voltage Detector level selection */

+#define PWR_CR1_ALS_0                  (0x1UL << PWR_CR1_ALS_Pos)              /*!< 0x00020000 */

+#define PWR_CR1_ALS_1                  (0x2UL << PWR_CR1_ALS_Pos)              /*!< 0x00040000 */

+#define PWR_CR1_AVDEN_Pos              (16U)

+#define PWR_CR1_AVDEN_Msk              (0x1UL << PWR_CR1_AVDEN_Pos)            /*!< 0x00010000 */

+#define PWR_CR1_AVDEN                  PWR_CR1_AVDEN_Msk                       /*!< Analog Voltage Detector Enable */

+#define PWR_CR1_SVOS_Pos               (14U)

+#define PWR_CR1_SVOS_Msk               (0x3UL << PWR_CR1_SVOS_Pos)             /*!< 0x0000C000 */

+#define PWR_CR1_SVOS                   PWR_CR1_SVOS_Msk                        /*!< System STOP mode Voltage Scaling selection */

+#define PWR_CR1_SVOS_0                 (0x1UL << PWR_CR1_SVOS_Pos)             /*!< 0x00004000 */

+#define PWR_CR1_SVOS_1                 (0x2UL << PWR_CR1_SVOS_Pos)             /*!< 0x00008000 */

+#define PWR_CR1_FLPS_Pos               (9U)

+#define PWR_CR1_FLPS_Msk               (0x1UL << PWR_CR1_FLPS_Pos)             /*!< 0x00000200 */

+#define PWR_CR1_FLPS                   PWR_CR1_FLPS_Msk                        /*!< Flash low power mode in DSTOP */

+#define PWR_CR1_DBP_Pos                (8U)

+#define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */

+#define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable Back-up domain Protection */

+#define PWR_CR1_PLS_Pos                (5U)

+#define PWR_CR1_PLS_Msk                (0x7UL << PWR_CR1_PLS_Pos)              /*!< 0x000000E0 */

+#define PWR_CR1_PLS                    PWR_CR1_PLS_Msk                         /*!< Programmable Voltage Detector level selection */

+#define PWR_CR1_PLS_0                  (0x1UL << PWR_CR1_PLS_Pos)              /*!< 0x00000020 */

+#define PWR_CR1_PLS_1                  (0x2UL << PWR_CR1_PLS_Pos)              /*!< 0x00000040 */

+#define PWR_CR1_PLS_2                  (0x4UL << PWR_CR1_PLS_Pos)              /*!< 0x00000080 */

+#define PWR_CR1_PVDEN_Pos              (4U)

+#define PWR_CR1_PVDEN_Msk              (0x1UL << PWR_CR1_PVDEN_Pos)            /*!< 0x00000010 */

+#define PWR_CR1_PVDEN                  PWR_CR1_PVDEN_Msk                       /*!< Programmable Voltage detector enable */

+#define PWR_CR1_LPDS_Pos               (0U)

+#define PWR_CR1_LPDS_Msk               (0x1UL << PWR_CR1_LPDS_Pos)             /*!< 0x00000001 */

+#define PWR_CR1_LPDS                   PWR_CR1_LPDS_Msk                        /*!< Low Power Deepsleep with SVOS3 */

+

+/*!< PVD level configuration */

+#define PWR_CR1_PLS_LEV0               (0UL)                                   /*!< PVD level 0 */

+#define PWR_CR1_PLS_LEV1_Pos           (5U)

+#define PWR_CR1_PLS_LEV1_Msk           (0x1UL << PWR_CR1_PLS_LEV1_Pos)         /*!< 0x00000020 */

+#define PWR_CR1_PLS_LEV1               PWR_CR1_PLS_LEV1_Msk                    /*!< PVD level 1 */

+#define PWR_CR1_PLS_LEV2_Pos           (6U)

+#define PWR_CR1_PLS_LEV2_Msk           (0x1UL << PWR_CR1_PLS_LEV2_Pos)         /*!< 0x00000040 */

+#define PWR_CR1_PLS_LEV2               PWR_CR1_PLS_LEV2_Msk                    /*!< PVD level 2 */

+#define PWR_CR1_PLS_LEV3_Pos           (5U)

+#define PWR_CR1_PLS_LEV3_Msk           (0x3UL << PWR_CR1_PLS_LEV3_Pos)         /*!< 0x00000060 */

+#define PWR_CR1_PLS_LEV3               PWR_CR1_PLS_LEV3_Msk                    /*!< PVD level 3 */

+#define PWR_CR1_PLS_LEV4_Pos           (7U)

+#define PWR_CR1_PLS_LEV4_Msk           (0x1UL << PWR_CR1_PLS_LEV4_Pos)         /*!< 0x00000080 */

+#define PWR_CR1_PLS_LEV4               PWR_CR1_PLS_LEV4_Msk                    /*!< PVD level 4 */

+#define PWR_CR1_PLS_LEV5_Pos           (5U)

+#define PWR_CR1_PLS_LEV5_Msk           (0x5UL << PWR_CR1_PLS_LEV5_Pos)         /*!< 0x000000A0 */

+#define PWR_CR1_PLS_LEV5               PWR_CR1_PLS_LEV5_Msk                    /*!< PVD level 5 */

+#define PWR_CR1_PLS_LEV6_Pos           (6U)

+#define PWR_CR1_PLS_LEV6_Msk           (0x3UL << PWR_CR1_PLS_LEV6_Pos)         /*!< 0x000000C0 */

+#define PWR_CR1_PLS_LEV6               PWR_CR1_PLS_LEV6_Msk                    /*!< PVD level 6 */

+#define PWR_CR1_PLS_LEV7_Pos           (5U)

+#define PWR_CR1_PLS_LEV7_Msk           (0x7UL << PWR_CR1_PLS_LEV7_Pos)         /*!< 0x000000E0 */

+#define PWR_CR1_PLS_LEV7               PWR_CR1_PLS_LEV7_Msk                    /*!< PVD level 7 */

+

+/*!< AVD level configuration */

+#define PWR_CR1_ALS_LEV0               (0UL)                                   /*!< AVD level 0 */

+#define PWR_CR1_ALS_LEV1_Pos           (17U)

+#define PWR_CR1_ALS_LEV1_Msk           (0x1UL << PWR_CR1_ALS_LEV1_Pos)         /*!< 0x00020000 */

+#define PWR_CR1_ALS_LEV1               PWR_CR1_ALS_LEV1_Msk                    /*!< AVD level 1 */

+#define PWR_CR1_ALS_LEV2_Pos           (18U)

+#define PWR_CR1_ALS_LEV2_Msk           (0x1UL << PWR_CR1_ALS_LEV2_Pos)         /*!< 0x00040000 */

+#define PWR_CR1_ALS_LEV2               PWR_CR1_ALS_LEV2_Msk                    /*!< AVD level 2 */

+#define PWR_CR1_ALS_LEV3_Pos           (17U)

+#define PWR_CR1_ALS_LEV3_Msk           (0x3UL << PWR_CR1_ALS_LEV3_Pos)         /*!< 0x00060000 */

+#define PWR_CR1_ALS_LEV3               PWR_CR1_ALS_LEV3_Msk                    /*!< AVD level 3 */

+

+/********************  Bit definition for PWR_CSR1 register  ******************/

+#define PWR_CSR1_AVDO_Pos              (16U)

+#define PWR_CSR1_AVDO_Msk              (0x1UL << PWR_CSR1_AVDO_Pos)            /*!< 0x00010000 */

+#define PWR_CSR1_AVDO                  PWR_CSR1_AVDO_Msk                       /*!< Analog Voltage Detect Output */

+#define PWR_CSR1_ACTVOS_Pos            (14U)

+#define PWR_CSR1_ACTVOS_Msk            (0x3UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x0000C000 */

+#define PWR_CSR1_ACTVOS                PWR_CSR1_ACTVOS_Msk                     /*!< Current actual used VOS for VDD11 Voltage Scaling */

+#define PWR_CSR1_ACTVOS_0              (0x1UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00004000 */

+#define PWR_CSR1_ACTVOS_1              (0x2UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00008000 */

+#define PWR_CSR1_ACTVOSRDY_Pos         (13U)

+#define PWR_CSR1_ACTVOSRDY_Msk         (0x1UL << PWR_CSR1_ACTVOSRDY_Pos)       /*!< 0x00002000 */

+#define PWR_CSR1_ACTVOSRDY             PWR_CSR1_ACTVOSRDY_Msk                  /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling  */

+#define PWR_CSR1_PVDO_Pos              (4U)

+#define PWR_CSR1_PVDO_Msk              (0x1UL << PWR_CSR1_PVDO_Pos)            /*!< 0x00000010 */

+#define PWR_CSR1_PVDO                  PWR_CSR1_PVDO_Msk                       /*!< Programmable Voltage Detect Output */

+

+/********************  Bit definition for PWR_CR2 register  *******************/

+#define PWR_CR2_TEMPH_Pos              (23U)

+#define PWR_CR2_TEMPH_Msk              (0x1UL << PWR_CR2_TEMPH_Pos)            /*!< 0x00800000 */

+#define PWR_CR2_TEMPH                  PWR_CR2_TEMPH_Msk                       /*!< Monitored temperature level above high threshold */

+#define PWR_CR2_TEMPL_Pos              (22U)

+#define PWR_CR2_TEMPL_Msk              (0x1UL << PWR_CR2_TEMPL_Pos)            /*!< 0x00400000 */

+#define PWR_CR2_TEMPL                  PWR_CR2_TEMPL_Msk                       /*!< Monitored temperature level above low threshold */

+#define PWR_CR2_VBATH_Pos              (21U)

+#define PWR_CR2_VBATH_Msk              (0x1UL << PWR_CR2_VBATH_Pos)            /*!< 0x00200000 */

+#define PWR_CR2_VBATH                  PWR_CR2_VBATH_Msk                       /*!< Monitored VBAT level above high threshold */

+#define PWR_CR2_VBATL_Pos              (20U)

+#define PWR_CR2_VBATL_Msk              (0x1UL << PWR_CR2_VBATL_Pos)            /*!< 0x00100000 */

+#define PWR_CR2_VBATL                  PWR_CR2_VBATL_Msk                       /*!< Monitored VBAT level above low threshold */

+#define PWR_CR2_BRRDY_Pos              (16U)

+#define PWR_CR2_BRRDY_Msk              (0x1UL << PWR_CR2_BRRDY_Pos)            /*!< 0x00010000 */

+#define PWR_CR2_BRRDY                  PWR_CR2_BRRDY_Msk                       /*!< Backup regulator ready */

+#define PWR_CR2_MONEN_Pos              (4U)

+#define PWR_CR2_MONEN_Msk              (0x1UL << PWR_CR2_MONEN_Pos)            /*!< 0x00000010 */

+#define PWR_CR2_MONEN                  PWR_CR2_MONEN_Msk                       /*!< VBAT and temperature monitoring enable */

+#define PWR_CR2_BREN_Pos               (0U)

+#define PWR_CR2_BREN_Msk               (0x1UL << PWR_CR2_BREN_Pos)             /*!< 0x00000001 */

+#define PWR_CR2_BREN                   PWR_CR2_BREN_Msk                        /*!< Backup regulator enable */

+

+/********************  Bit definition for PWR_CR3 register  *******************/

+#define PWR_CR3_USB33RDY_Pos           (26U)

+#define PWR_CR3_USB33RDY_Msk           (0x1UL << PWR_CR3_USB33RDY_Pos)         /*!< 0x04000000 */

+#define PWR_CR3_USB33RDY               PWR_CR3_USB33RDY_Msk                    /*!< USB supply ready */

+#define PWR_CR3_USBREGEN_Pos           (25U)

+#define PWR_CR3_USBREGEN_Msk           (0x1UL << PWR_CR3_USBREGEN_Pos)         /*!< 0x02000000 */

+#define PWR_CR3_USBREGEN               PWR_CR3_USBREGEN_Msk                    /*!< USB regulator enable */

+#define PWR_CR3_USB33DEN_Pos           (24U)

+#define PWR_CR3_USB33DEN_Msk           (0x1UL << PWR_CR3_USB33DEN_Pos)         /*!< 0x01000000 */

+#define PWR_CR3_USB33DEN               PWR_CR3_USB33DEN_Msk                    /*!< VDD33_USB voltage level detector enable */

+#define PWR_CR3_SMPSEXTRDY_Pos         (16U)

+#define PWR_CR3_SMPSEXTRDY_Msk         (0x1UL << PWR_CR3_SMPSEXTRDY_Pos)       /*!< 0x00010000 */

+#define PWR_CR3_SMPSEXTRDY             PWR_CR3_SMPSEXTRDY_Msk                  /*!< SMPS External supply ready */

+#define PWR_CR3_VBRS_Pos               (9U)

+#define PWR_CR3_VBRS_Msk               (0x1UL << PWR_CR3_VBRS_Pos)             /*!< 0x00000200 */

+#define PWR_CR3_VBRS                   PWR_CR3_VBRS_Msk                        /*!< VBAT charging resistor selection */

+#define PWR_CR3_VBE_Pos                (8U)

+#define PWR_CR3_VBE_Msk                (0x1UL << PWR_CR3_VBE_Pos)              /*!< 0x00000100 */

+#define PWR_CR3_VBE                    PWR_CR3_VBE_Msk                         /*!< VBAT charging enable */

+#define PWR_CR3_SMPSLEVEL_Pos          (4U)

+#define PWR_CR3_SMPSLEVEL_Msk          (0x3UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000030 */

+#define PWR_CR3_SMPSLEVEL              PWR_CR3_SMPSLEVEL_Msk                   /*!< SMPS output Voltage */

+#define PWR_CR3_SMPSLEVEL_0            (0x1UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000010 */

+#define PWR_CR3_SMPSLEVEL_1            (0x2UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000020 */

+#define PWR_CR3_SMPSEXTHP_Pos          (3U)

+#define PWR_CR3_SMPSEXTHP_Msk          (0x1UL << PWR_CR3_SMPSEXTHP_Pos)        /*!< 0x00000008 */

+#define PWR_CR3_SMPSEXTHP              PWR_CR3_SMPSEXTHP_Msk                   /*!< SMPS forced ON and in High Power MR mode */

+#define PWR_CR3_SMPSEN_Pos             (2U)

+#define PWR_CR3_SMPSEN_Msk             (0x1UL << PWR_CR3_SMPSEN_Pos)           /*!< 0x00000004 */

+#define PWR_CR3_SMPSEN                 PWR_CR3_SMPSEN_Msk                      /*!< SMPS Enable */

+#define PWR_CR3_LDOEN_Pos              (1U)

+#define PWR_CR3_LDOEN_Msk              (0x1UL << PWR_CR3_LDOEN_Pos)            /*!< 0x00000002 */

+#define PWR_CR3_LDOEN                  PWR_CR3_LDOEN_Msk                       /*!< Low Drop Output regulator enable */

+#define PWR_CR3_BYPASS_Pos             (0U)

+#define PWR_CR3_BYPASS_Msk             (0x1UL << PWR_CR3_BYPASS_Pos)           /*!< 0x00000001 */

+#define PWR_CR3_BYPASS                 PWR_CR3_BYPASS_Msk                      /*!< Power Management Unit bypass */

+

+/********************  Bit definition for PWR_CPUCR register  *****************/

+#define PWR_CPUCR_RUN_D3_Pos           (11U)

+#define PWR_CPUCR_RUN_D3_Msk           (0x1UL << PWR_CPUCR_RUN_D3_Pos)         /*!< 0x00000800 */

+#define PWR_CPUCR_RUN_D3               PWR_CPUCR_RUN_D3_Msk                    /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */

+#define PWR_CPUCR_HOLD2_Pos            (10U)

+#define PWR_CPUCR_HOLD2_Msk            (0x1UL << PWR_CPUCR_HOLD2_Pos)          /*!< 0x00000400 */

+#define PWR_CPUCR_HOLD2                PWR_CPUCR_HOLD2_Msk                     /*!< Hold the CPU2 and allocated peripherals when exiting STOP mode */

+#define PWR_CPUCR_CSSF_Pos             (9U)

+#define PWR_CPUCR_CSSF_Msk             (0x1UL << PWR_CPUCR_CSSF_Pos)           /*!< 0x00000200 */

+#define PWR_CPUCR_CSSF                 PWR_CPUCR_CSSF_Msk                      /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */

+#define PWR_CPUCR_SBF_D2_Pos           (8U)

+#define PWR_CPUCR_SBF_D2_Msk           (0x1UL << PWR_CPUCR_SBF_D2_Pos)         /*!< 0x00000100 */

+#define PWR_CPUCR_SBF_D2               PWR_CPUCR_SBF_D2_Msk                    /*!< D2 domain DSTANDBY Flag */

+#define PWR_CPUCR_SBF_D1_Pos           (7U)

+#define PWR_CPUCR_SBF_D1_Msk           (0x1UL << PWR_CPUCR_SBF_D1_Pos)         /*!< 0x00000080 */

+#define PWR_CPUCR_SBF_D1               PWR_CPUCR_SBF_D1_Msk                    /*!< D1 domain DSTANDBY Flag */

+#define PWR_CPUCR_SBF_Pos              (6U)

+#define PWR_CPUCR_SBF_Msk              (0x1UL << PWR_CPUCR_SBF_Pos)            /*!< 0x00000040 */

+#define PWR_CPUCR_SBF                  PWR_CPUCR_SBF_Msk                       /*!< System STANDBY Flag */

+#define PWR_CPUCR_STOPF_Pos            (5U)

+#define PWR_CPUCR_STOPF_Msk            (0x1UL << PWR_CPUCR_STOPF_Pos)          /*!< 0x00000020 */

+#define PWR_CPUCR_STOPF                PWR_CPUCR_STOPF_Msk                     /*!< STOP Flag */

+#define PWR_CPUCR_HOLD2F_Pos           (4U)

+#define PWR_CPUCR_HOLD2F_Msk           (0x1UL << PWR_CPUCR_HOLD2F_Pos)         /*!< 0x00000010 */

+#define PWR_CPUCR_HOLD2F               PWR_CPUCR_HOLD2F_Msk                    /*!< CPU2 in hold wakeup flag */

+#define PWR_CPUCR_PDDS_D3_Pos          (2U)

+#define PWR_CPUCR_PDDS_D3_Msk          (0x1UL << PWR_CPUCR_PDDS_D3_Pos)        /*!< 0x00000004 */

+#define PWR_CPUCR_PDDS_D3              PWR_CPUCR_PDDS_D3_Msk                   /*!< System D3 domain Power Down Deepsleep */

+#define PWR_CPUCR_PDDS_D2_Pos          (1U)

+#define PWR_CPUCR_PDDS_D2_Msk          (0x1UL << PWR_CPUCR_PDDS_D2_Pos)        /*!< 0x00000002 */

+#define PWR_CPUCR_PDDS_D2              PWR_CPUCR_PDDS_D2_Msk                   /*!< D2 domain Power Down Deepsleep */

+#define PWR_CPUCR_PDDS_D1_Pos          (0U)

+#define PWR_CPUCR_PDDS_D1_Msk          (0x1UL << PWR_CPUCR_PDDS_D1_Pos)        /*!< 0x00000001 */

+#define PWR_CPUCR_PDDS_D1              PWR_CPUCR_PDDS_D1_Msk                   /*!< D1 domain Power Down Deepsleep selection */

+

+/********************  Bit definition for PWR_CPU2CR register  ****************/

+#define PWR_CPU2CR_RUN_D3_Pos          (11U)

+#define PWR_CPU2CR_RUN_D3_Msk          (0x1UL << PWR_CPU2CR_RUN_D3_Pos)        /*!< 0x00000800 */

+#define PWR_CPU2CR_RUN_D3              PWR_CPU2CR_RUN_D3_Msk                   /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */

+#define PWR_CPU2CR_HOLD1_Pos           (10U)

+#define PWR_CPU2CR_HOLD1_Msk           (0x1UL << PWR_CPU2CR_HOLD1_Pos)         /*!< 0x00000400 */

+#define PWR_CPU2CR_HOLD1               PWR_CPU2CR_HOLD1_Msk                    /*!< Hold the CPU1 and allocated peripherals when exiting STOP mode */

+#define PWR_CPU2CR_CSSF_Pos            (9U)

+#define PWR_CPU2CR_CSSF_Msk            (0x1UL << PWR_CPU2CR_CSSF_Pos)          /*!< 0x00000200 */

+#define PWR_CPU2CR_CSSF                PWR_CPU2CR_CSSF_Msk                     /*!< Clear D2 domain CPU2 STANDBY, STOP and HOLD flags */

+#define PWR_CPU2CR_SBF_D2_Pos          (8U)

+#define PWR_CPU2CR_SBF_D2_Msk          (0x1UL << PWR_CPU2CR_SBF_D2_Pos)        /*!< 0x00000100 */

+#define PWR_CPU2CR_SBF_D2              PWR_CPU2CR_SBF_D2_Msk                   /*!< D2 domain DSTANDBY Flag */

+#define PWR_CPU2CR_SBF_D1_Pos          (7U)

+#define PWR_CPU2CR_SBF_D1_Msk          (0x1UL << PWR_CPU2CR_SBF_D1_Pos)        /*!< 0x00000080 */

+#define PWR_CPU2CR_SBF_D1              PWR_CPU2CR_SBF_D1_Msk                   /*!< D1 domain DSTANDBY Flag */

+#define PWR_CPU2CR_SBF_Pos             (6U)

+#define PWR_CPU2CR_SBF_Msk             (0x1UL << PWR_CPU2CR_SBF_Pos)           /*!< 0x00000040 */

+#define PWR_CPU2CR_SBF                 PWR_CPU2CR_SBF_Msk                      /*!< System STANDBY Flag */

+#define PWR_CPU2CR_STOPF_Pos           (5U)

+#define PWR_CPU2CR_STOPF_Msk           (0x1UL << PWR_CPU2CR_STOPF_Pos)         /*!< 0x00000020 */

+#define PWR_CPU2CR_STOPF               PWR_CPU2CR_STOPF_Msk                    /*!< STOP Flag */

+#define PWR_CPU2CR_HOLD1F_Pos          (4U)

+#define PWR_CPU2CR_HOLD1F_Msk          (0x1UL << PWR_CPU2CR_HOLD1F_Pos)        /*!< 0x00000010 */

+#define PWR_CPU2CR_HOLD1F              PWR_CPU2CR_HOLD1F_Msk                   /*!< CPU1 in hold wakeup flag */

+#define PWR_CPU2CR_PDDS_D3_Pos         (2U)

+#define PWR_CPU2CR_PDDS_D3_Msk         (0x1UL << PWR_CPU2CR_PDDS_D3_Pos)       /*!< 0x00000004 */

+#define PWR_CPU2CR_PDDS_D3             PWR_CPU2CR_PDDS_D3_Msk                  /*!< System D3 domain Power Down Deepsleep */

+#define PWR_CPU2CR_PDDS_D2_Pos         (1U)

+#define PWR_CPU2CR_PDDS_D2_Msk         (0x1UL << PWR_CPU2CR_PDDS_D2_Pos)       /*!< 0x00000002 */

+#define PWR_CPU2CR_PDDS_D2             PWR_CPU2CR_PDDS_D2_Msk                  /*!< D2 domain Power Down Deepsleep */

+#define PWR_CPU2CR_PDDS_D1_Pos         (0U)

+#define PWR_CPU2CR_PDDS_D1_Msk         (0x1UL << PWR_CPU2CR_PDDS_D1_Pos)       /*!< 0x00000001 */

+#define PWR_CPU2CR_PDDS_D1             PWR_CPU2CR_PDDS_D1_Msk                  /*!< D1 domain Power Down Deepsleep selection */

+

+

+/********************  Bit definition for PWR_D3CR register  ******************/

+#define PWR_D3CR_VOS_Pos               (14U)

+#define PWR_D3CR_VOS_Msk               (0x3UL << PWR_D3CR_VOS_Pos)             /*!< 0x0000C000 */

+#define PWR_D3CR_VOS                   PWR_D3CR_VOS_Msk                        /*!< Voltage Scaling selection according performance */

+#define PWR_D3CR_VOS_0                 (0x1UL << PWR_D3CR_VOS_Pos)             /*!< 0x00004000 */

+#define PWR_D3CR_VOS_1                 (0x2UL << PWR_D3CR_VOS_Pos)             /*!< 0x00008000 */

+#define PWR_D3CR_VOSRDY_Pos            (13U)

+#define PWR_D3CR_VOSRDY_Msk            (0x1UL << PWR_D3CR_VOSRDY_Pos)          /*!< 0x00002000 */

+#define PWR_D3CR_VOSRDY                PWR_D3CR_VOSRDY_Msk                     /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */

+

+/******************  Bit definition for PWR_WKUPCR register  ******************/

+#define PWR_WKUPCR_WKUPC6_Pos          (5U)

+#define PWR_WKUPCR_WKUPC6_Msk          (0x1UL << PWR_WKUPCR_WKUPC6_Pos)        /*!< 0x00000020 */

+#define PWR_WKUPCR_WKUPC6              PWR_WKUPCR_WKUPC6_Msk                   /*!< Clear Wakeup Pin Flag 6 */

+#define PWR_WKUPCR_WKUPC5_Pos          (4U)

+#define PWR_WKUPCR_WKUPC5_Msk          (0x1UL << PWR_WKUPCR_WKUPC5_Pos)        /*!< 0x00000010 */

+#define PWR_WKUPCR_WKUPC5              PWR_WKUPCR_WKUPC5_Msk                   /*!< Clear Wakeup Pin Flag 5 */

+#define PWR_WKUPCR_WKUPC4_Pos          (3U)

+#define PWR_WKUPCR_WKUPC4_Msk          (0x1UL << PWR_WKUPCR_WKUPC4_Pos)        /*!< 0x00000008 */

+#define PWR_WKUPCR_WKUPC4              PWR_WKUPCR_WKUPC4_Msk                   /*!< Clear Wakeup Pin Flag 4 */

+#define PWR_WKUPCR_WKUPC3_Pos          (2U)

+#define PWR_WKUPCR_WKUPC3_Msk          (0x1UL << PWR_WKUPCR_WKUPC3_Pos)        /*!< 0x00000004 */

+#define PWR_WKUPCR_WKUPC3              PWR_WKUPCR_WKUPC3_Msk                   /*!< Clear Wakeup Pin Flag 3 */

+#define PWR_WKUPCR_WKUPC2_Pos          (1U)

+#define PWR_WKUPCR_WKUPC2_Msk          (0x1UL << PWR_WKUPCR_WKUPC2_Pos)        /*!< 0x00000002 */

+#define PWR_WKUPCR_WKUPC2              PWR_WKUPCR_WKUPC2_Msk                   /*!< Clear Wakeup Pin Flag 2 */

+#define PWR_WKUPCR_WKUPC1_Pos          (0U)

+#define PWR_WKUPCR_WKUPC1_Msk          (0x1UL << PWR_WKUPCR_WKUPC1_Pos)        /*!< 0x00000001 */

+#define PWR_WKUPCR_WKUPC1              PWR_WKUPCR_WKUPC1_Msk                   /*!< Clear Wakeup Pin Flag 1 */

+

+/********************  Bit definition for PWR_WKUPFR register  ****************/

+#define PWR_WKUPFR_WKUPF6_Pos          (5U)

+#define PWR_WKUPFR_WKUPF6_Msk          (0x1UL << PWR_WKUPFR_WKUPF6_Pos)        /*!< 0x00000020 */

+#define PWR_WKUPFR_WKUPF6              PWR_WKUPFR_WKUPF6_Msk                   /*!< Wakeup Pin Flag 6 */

+#define PWR_WKUPFR_WKUPF5_Pos          (4U)

+#define PWR_WKUPFR_WKUPF5_Msk          (0x1UL << PWR_WKUPFR_WKUPF5_Pos)        /*!< 0x00000010 */

+#define PWR_WKUPFR_WKUPF5              PWR_WKUPFR_WKUPF5_Msk                   /*!< Wakeup Pin Flag 5 */

+#define PWR_WKUPFR_WKUPF4_Pos          (3U)

+#define PWR_WKUPFR_WKUPF4_Msk          (0x1UL << PWR_WKUPFR_WKUPF4_Pos)        /*!< 0x00000008 */

+#define PWR_WKUPFR_WKUPF4              PWR_WKUPFR_WKUPF4_Msk                   /*!< Wakeup Pin Flag 4 */

+#define PWR_WKUPFR_WKUPF3_Pos          (2U)

+#define PWR_WKUPFR_WKUPF3_Msk          (0x1UL << PWR_WKUPFR_WKUPF3_Pos)        /*!< 0x00000004 */

+#define PWR_WKUPFR_WKUPF3              PWR_WKUPFR_WKUPF3_Msk                   /*!< Wakeup Pin Flag 3 */

+#define PWR_WKUPFR_WKUPF2_Pos          (1U)

+#define PWR_WKUPFR_WKUPF2_Msk          (0x1UL << PWR_WKUPFR_WKUPF2_Pos)        /*!< 0x00000002 */

+#define PWR_WKUPFR_WKUPF2              PWR_WKUPFR_WKUPF2_Msk                   /*!< Wakeup Pin Flag 2 */

+#define PWR_WKUPFR_WKUPF1_Pos          (0U)

+#define PWR_WKUPFR_WKUPF1_Msk          (0x1UL << PWR_WKUPFR_WKUPF1_Pos)        /*!< 0x00000001 */

+#define PWR_WKUPFR_WKUPF1              PWR_WKUPFR_WKUPF1_Msk                   /*!< Wakeup Pin Flag 1 */

+

+/******************  Bit definition for PWR_WKUPEPR register  *****************/

+#define PWR_WKUPEPR_WKUPPUPD6_Pos      (26U)

+#define PWR_WKUPEPR_WKUPPUPD6_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x0C000000 */

+#define PWR_WKUPEPR_WKUPPUPD6          PWR_WKUPEPR_WKUPPUPD6_Msk               /*!< Wakeup Pin pull configuration for WKUP6 */

+#define PWR_WKUPEPR_WKUPPUPD6_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x04000000 */

+#define PWR_WKUPEPR_WKUPPUPD6_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x08000000 */

+#define PWR_WKUPEPR_WKUPPUPD5_Pos      (24U)

+#define PWR_WKUPEPR_WKUPPUPD5_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x03000000 */

+#define PWR_WKUPEPR_WKUPPUPD5          PWR_WKUPEPR_WKUPPUPD5_Msk               /*!< Wakeup Pin pull configuration for WKUP5 */

+#define PWR_WKUPEPR_WKUPPUPD5_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x01000000 */

+#define PWR_WKUPEPR_WKUPPUPD5_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x02000000 */

+#define PWR_WKUPEPR_WKUPPUPD4_Pos      (22U)

+#define PWR_WKUPEPR_WKUPPUPD4_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00C00000 */

+#define PWR_WKUPEPR_WKUPPUPD4          PWR_WKUPEPR_WKUPPUPD4_Msk               /*!< Wakeup Pin pull configuration for WKUP4 */

+#define PWR_WKUPEPR_WKUPPUPD4_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00400000 */

+#define PWR_WKUPEPR_WKUPPUPD4_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00800000 */

+#define PWR_WKUPEPR_WKUPPUPD3_Pos      (20U)

+#define PWR_WKUPEPR_WKUPPUPD3_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00300000 */

+#define PWR_WKUPEPR_WKUPPUPD3          PWR_WKUPEPR_WKUPPUPD3_Msk               /*!< Wakeup Pin pull configuration for WKUP3 */

+#define PWR_WKUPEPR_WKUPPUPD3_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00100000 */

+#define PWR_WKUPEPR_WKUPPUPD3_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00200000 */

+#define PWR_WKUPEPR_WKUPPUPD2_Pos      (18U)

+#define PWR_WKUPEPR_WKUPPUPD2_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x000C0000 */

+#define PWR_WKUPEPR_WKUPPUPD2          PWR_WKUPEPR_WKUPPUPD2_Msk               /*!< Wakeup Pin pull configuration for WKUP2 */

+#define PWR_WKUPEPR_WKUPPUPD2_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00040000 */

+#define PWR_WKUPEPR_WKUPPUPD2_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00080000 */

+#define PWR_WKUPEPR_WKUPPUPD1_Pos      (16U)

+#define PWR_WKUPEPR_WKUPPUPD1_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00030000 */

+#define PWR_WKUPEPR_WKUPPUPD1          PWR_WKUPEPR_WKUPPUPD1_Msk               /*!< Wakeup Pin pull configuration for WKUP1 */

+#define PWR_WKUPEPR_WKUPPUPD1_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00010000 */

+#define PWR_WKUPEPR_WKUPPUPD1_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00020000 */

+#define PWR_WKUPEPR_WKUPP6_Pos         (13U)

+#define PWR_WKUPEPR_WKUPP6_Msk         (0x1UL << PWR_WKUPEPR_WKUPP6_Pos)       /*!< 0x00002000 */

+#define PWR_WKUPEPR_WKUPP6             PWR_WKUPEPR_WKUPP6_Msk                  /*!< Wakeup Pin Polarity for WKUP6 */

+#define PWR_WKUPEPR_WKUPP5_Pos         (12U)

+#define PWR_WKUPEPR_WKUPP5_Msk         (0x1UL << PWR_WKUPEPR_WKUPP5_Pos)       /*!< 0x00001000 */

+#define PWR_WKUPEPR_WKUPP5             PWR_WKUPEPR_WKUPP5_Msk                  /*!< Wakeup Pin Polarity for WKUP5 */

+#define PWR_WKUPEPR_WKUPP4_Pos         (11U)

+#define PWR_WKUPEPR_WKUPP4_Msk         (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)       /*!< 0x00000800 */

+#define PWR_WKUPEPR_WKUPP4             PWR_WKUPEPR_WKUPP4_Msk                  /*!< Wakeup Pin Polarity for WKUP4 */

+#define PWR_WKUPEPR_WKUPP3_Pos         (10U)

+#define PWR_WKUPEPR_WKUPP3_Msk         (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)       /*!< 0x00000400 */

+#define PWR_WKUPEPR_WKUPP3             PWR_WKUPEPR_WKUPP3_Msk                  /*!< Wakeup Pin Polarity for WKUP3 */

+#define PWR_WKUPEPR_WKUPP2_Pos         (9U)

+#define PWR_WKUPEPR_WKUPP2_Msk         (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)       /*!< 0x00000200 */

+#define PWR_WKUPEPR_WKUPP2             PWR_WKUPEPR_WKUPP2_Msk                  /*!< Wakeup Pin Polarity for WKUP2 */

+#define PWR_WKUPEPR_WKUPP1_Pos         (8U)

+#define PWR_WKUPEPR_WKUPP1_Msk         (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)       /*!< 0x00000100 */

+#define PWR_WKUPEPR_WKUPP1             PWR_WKUPEPR_WKUPP1_Msk                  /*!< Wakeup Pin Polarity for WKUP1 */

+#define PWR_WKUPEPR_WKUPEN6_Pos        (5U)

+#define PWR_WKUPEPR_WKUPEN6_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos)      /*!< 0x00000020 */

+#define PWR_WKUPEPR_WKUPEN6            PWR_WKUPEPR_WKUPEN6_Msk                 /*!< Enable Wakeup Pin WKUP6 */

+#define PWR_WKUPEPR_WKUPEN5_Pos        (4U)

+#define PWR_WKUPEPR_WKUPEN5_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos)      /*!< 0x00000010 */

+#define PWR_WKUPEPR_WKUPEN5            PWR_WKUPEPR_WKUPEN5_Msk                 /*!< Enable Wakeup Pin WKUP5 */

+#define PWR_WKUPEPR_WKUPEN4_Pos        (3U)

+#define PWR_WKUPEPR_WKUPEN4_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)      /*!< 0x00000008 */

+#define PWR_WKUPEPR_WKUPEN4            PWR_WKUPEPR_WKUPEN4_Msk                 /*!< Enable Wakeup Pin WKUP4 */

+#define PWR_WKUPEPR_WKUPEN3_Pos        (2U)

+#define PWR_WKUPEPR_WKUPEN3_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)      /*!< 0x00000004 */

+#define PWR_WKUPEPR_WKUPEN3            PWR_WKUPEPR_WKUPEN3_Msk                 /*!< Enable Wakeup Pin WKUP3 */

+#define PWR_WKUPEPR_WKUPEN2_Pos        (1U)

+#define PWR_WKUPEPR_WKUPEN2_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)      /*!< 0x00000002 */

+#define PWR_WKUPEPR_WKUPEN2            PWR_WKUPEPR_WKUPEN2_Msk                 /*!< Enable Wakeup Pin WKUP2 */

+#define PWR_WKUPEPR_WKUPEN1_Pos        (0U)

+#define PWR_WKUPEPR_WKUPEN1_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)      /*!< 0x00000001 */

+#define PWR_WKUPEPR_WKUPEN1            PWR_WKUPEPR_WKUPEN1_Msk                 /*!< Enable Wakeup Pin WKUP1 */

+#define PWR_WKUPEPR_WKUPEN_Pos         (0U)

+#define PWR_WKUPEPR_WKUPEN_Msk         (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos)      /*!< 0x0000003F */

+#define PWR_WKUPEPR_WKUPEN             PWR_WKUPEPR_WKUPEN_Msk                  /*!< Enable all Wakeup Pin */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Reset and Clock Control                            */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  RCC VERSION  ********************************/

+#define RCC_VER_X

+

+/********************  Bit definition for RCC_CR register  ********************/

+#define RCC_CR_HSION_Pos                       (0U)

+#define RCC_CR_HSION_Msk                       (0x1UL << RCC_CR_HSION_Pos)     /*!< 0x00000001 */

+#define RCC_CR_HSION                           RCC_CR_HSION_Msk                /*!< Internal High Speed clock enable */

+#define RCC_CR_HSIKERON_Pos                    (1U)

+#define RCC_CR_HSIKERON_Msk                    (0x1UL << RCC_CR_HSIKERON_Pos)  /*!< 0x00000002 */

+#define RCC_CR_HSIKERON                        RCC_CR_HSIKERON_Msk             /*!< Internal High Speed clock enable for some IPs Kernel */

+#define RCC_CR_HSIRDY_Pos                      (2U)

+#define RCC_CR_HSIRDY_Msk                      (0x1UL << RCC_CR_HSIRDY_Pos)    /*!< 0x00000004 */

+#define RCC_CR_HSIRDY                          RCC_CR_HSIRDY_Msk               /*!< Internal High Speed clock ready flag */

+#define RCC_CR_HSIDIV_Pos                      (3U)

+#define RCC_CR_HSIDIV_Msk                      (0x3UL << RCC_CR_HSIDIV_Pos)    /*!< 0x00000018 */

+#define RCC_CR_HSIDIV                          RCC_CR_HSIDIV_Msk               /*!< Internal High Speed clock divider selection */

+#define RCC_CR_HSIDIV_1                        (0x0UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000000 */

+#define RCC_CR_HSIDIV_2                        (0x1UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000008 */

+#define RCC_CR_HSIDIV_4                        (0x2UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000010 */

+#define RCC_CR_HSIDIV_8                        (0x3UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000018 */

+

+#define RCC_CR_HSIDIVF_Pos                     (5U)

+#define RCC_CR_HSIDIVF_Msk                     (0x1UL << RCC_CR_HSIDIVF_Pos)   /*!< 0x00000020 */

+#define RCC_CR_HSIDIVF                         RCC_CR_HSIDIVF_Msk              /*!< HSI Divider flag */

+#define RCC_CR_CSION_Pos                       (7U)

+#define RCC_CR_CSION_Msk                       (0x1UL << RCC_CR_CSION_Pos)     /*!< 0x00000080 */

+#define RCC_CR_CSION                           RCC_CR_CSION_Msk                /*!< The Internal RC 4MHz oscillator clock enable */

+#define RCC_CR_CSIRDY_Pos                      (8U)

+#define RCC_CR_CSIRDY_Msk                      (0x1UL << RCC_CR_CSIRDY_Pos)    /*!< 0x00000100 */

+#define RCC_CR_CSIRDY                          RCC_CR_CSIRDY_Msk               /*!< The Internal RC 4MHz oscillator clock ready */

+#define RCC_CR_CSIKERON_Pos                    (9U)

+#define RCC_CR_CSIKERON_Msk                    (0x1UL << RCC_CR_CSIKERON_Pos)  /*!< 0x00000200 */

+#define RCC_CR_CSIKERON                        RCC_CR_CSIKERON_Msk             /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */

+#define RCC_CR_HSI48ON_Pos                     (12U)

+#define RCC_CR_HSI48ON_Msk                     (0x1UL << RCC_CR_HSI48ON_Pos)   /*!< 0x00001000 */

+#define RCC_CR_HSI48ON                         RCC_CR_HSI48ON_Msk              /*!< HSI48 clock enable clock enable  */

+#define RCC_CR_HSI48RDY_Pos                    (13U)

+#define RCC_CR_HSI48RDY_Msk                    (0x1UL << RCC_CR_HSI48RDY_Pos)  /*!< 0x00002000 */

+#define RCC_CR_HSI48RDY                        RCC_CR_HSI48RDY_Msk             /*!< HSI48 clock ready */

+

+#define RCC_CR_D1CKRDY_Pos                     (14U)

+#define RCC_CR_D1CKRDY_Msk                     (0x1UL << RCC_CR_D1CKRDY_Pos)   /*!< 0x00004000 */

+#define RCC_CR_D1CKRDY                         RCC_CR_D1CKRDY_Msk              /*!< D1 domain clocks ready flag  */

+#define RCC_CR_D2CKRDY_Pos                     (15U)

+#define RCC_CR_D2CKRDY_Msk                     (0x1UL << RCC_CR_D2CKRDY_Pos)   /*!< 0x00008000 */

+#define RCC_CR_D2CKRDY                         RCC_CR_D2CKRDY_Msk              /*!< D2 domain clocks ready flag */

+

+#define RCC_CR_HSEON_Pos                       (16U)

+#define RCC_CR_HSEON_Msk                       (0x1UL << RCC_CR_HSEON_Pos)     /*!< 0x00010000 */

+#define RCC_CR_HSEON                           RCC_CR_HSEON_Msk                /*!< External High Speed clock enable */

+#define RCC_CR_HSERDY_Pos                      (17U)

+#define RCC_CR_HSERDY_Msk                      (0x1UL << RCC_CR_HSERDY_Pos)    /*!< 0x00020000 */

+#define RCC_CR_HSERDY                          RCC_CR_HSERDY_Msk               /*!< External High Speed clock ready */

+#define RCC_CR_HSEBYP_Pos                      (18U)

+#define RCC_CR_HSEBYP_Msk                      (0x1UL << RCC_CR_HSEBYP_Pos)    /*!< 0x00040000 */

+#define RCC_CR_HSEBYP                          RCC_CR_HSEBYP_Msk               /*!< External High Speed clock Bypass */

+#define RCC_CR_CSSHSEON_Pos                    (19U)

+#define RCC_CR_CSSHSEON_Msk                    (0x1UL << RCC_CR_CSSHSEON_Pos)  /*!< 0x00080000 */

+#define RCC_CR_CSSHSEON                        RCC_CR_CSSHSEON_Msk             /*!< HSE Clock security System enable */

+

+

+#define RCC_CR_PLL1ON_Pos                      (24U)

+#define RCC_CR_PLL1ON_Msk                      (0x1UL << RCC_CR_PLL1ON_Pos)    /*!< 0x01000000 */

+#define RCC_CR_PLL1ON                          RCC_CR_PLL1ON_Msk               /*!< System PLL1 clock enable */

+#define RCC_CR_PLL1RDY_Pos                     (25U)

+#define RCC_CR_PLL1RDY_Msk                     (0x1UL << RCC_CR_PLL1RDY_Pos)   /*!< 0x02000000 */

+#define RCC_CR_PLL1RDY                         RCC_CR_PLL1RDY_Msk              /*!< System PLL1 clock ready */

+#define RCC_CR_PLL2ON_Pos                      (26U)

+#define RCC_CR_PLL2ON_Msk                      (0x1UL << RCC_CR_PLL2ON_Pos)    /*!< 0x04000000 */

+#define RCC_CR_PLL2ON                          RCC_CR_PLL2ON_Msk               /*!< System PLL2 clock enable */

+#define RCC_CR_PLL2RDY_Pos                     (27U)

+#define RCC_CR_PLL2RDY_Msk                     (0x1UL << RCC_CR_PLL2RDY_Pos)   /*!< 0x08000000 */

+#define RCC_CR_PLL2RDY                         RCC_CR_PLL2RDY_Msk              /*!< System PLL2 clock ready */

+#define RCC_CR_PLL3ON_Pos                      (28U)

+#define RCC_CR_PLL3ON_Msk                      (0x1UL << RCC_CR_PLL3ON_Pos)    /*!< 0x10000000 */

+#define RCC_CR_PLL3ON                          RCC_CR_PLL3ON_Msk               /*!< System PLL3 clock enable */

+#define RCC_CR_PLL3RDY_Pos                     (29U)

+#define RCC_CR_PLL3RDY_Msk                     (0x1UL << RCC_CR_PLL3RDY_Pos)   /*!< 0x20000000 */

+#define RCC_CR_PLL3RDY                         RCC_CR_PLL3RDY_Msk              /*!< System PLL3 clock ready */

+

+/*Legacy */

+#define RCC_CR_PLLON_Pos                       (24U)

+#define RCC_CR_PLLON_Msk                       (0x1UL << RCC_CR_PLLON_Pos)     /*!< 0x01000000 */

+#define RCC_CR_PLLON                           RCC_CR_PLLON_Msk                /*!< System PLL clock enable */

+#define RCC_CR_PLLRDY_Pos                      (25U)

+#define RCC_CR_PLLRDY_Msk                      (0x1UL << RCC_CR_PLLRDY_Pos)    /*!< 0x02000000 */

+#define RCC_CR_PLLRDY                          RCC_CR_PLLRDY_Msk               /*!< System PLL clock ready */

+

+/********************  Bit definition for RCC_HSICFGR register  ***************/

+/*!< HSICAL configuration */

+#define RCC_HSICFGR_HSICAL_Pos                 (0U)

+#define RCC_HSICFGR_HSICAL_Msk                 (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */

+#define RCC_HSICFGR_HSICAL                     RCC_HSICFGR_HSICAL_Msk          /*!< HSICAL[11:0] bits */

+#define RCC_HSICFGR_HSICAL_0                   (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */

+#define RCC_HSICFGR_HSICAL_1                   (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */

+#define RCC_HSICFGR_HSICAL_2                   (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */

+#define RCC_HSICFGR_HSICAL_3                   (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */

+#define RCC_HSICFGR_HSICAL_4                   (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */

+#define RCC_HSICFGR_HSICAL_5                   (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */

+#define RCC_HSICFGR_HSICAL_6                   (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */

+#define RCC_HSICFGR_HSICAL_7                   (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */

+#define RCC_HSICFGR_HSICAL_8                   (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */

+#define RCC_HSICFGR_HSICAL_9                   (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */

+#define RCC_HSICFGR_HSICAL_10                  (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */

+#define RCC_HSICFGR_HSICAL_11                  (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */

+

+/*!< HSITRIM configuration */

+#define RCC_HSICFGR_HSITRIM_Pos                (24U)

+#define RCC_HSICFGR_HSITRIM_Msk                (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */

+#define RCC_HSICFGR_HSITRIM                    RCC_HSICFGR_HSITRIM_Msk         /*!< HSITRIM[6:0] bits */

+#define RCC_HSICFGR_HSITRIM_0                  (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */

+#define RCC_HSICFGR_HSITRIM_1                  (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */

+#define RCC_HSICFGR_HSITRIM_2                  (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */

+#define RCC_HSICFGR_HSITRIM_3                  (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */

+#define RCC_HSICFGR_HSITRIM_4                  (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */

+#define RCC_HSICFGR_HSITRIM_5                  (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */

+#define RCC_HSICFGR_HSITRIM_6                  (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */

+

+

+/********************  Bit definition for RCC_CRRCR register  *****************/

+

+/*!< HSI48CAL configuration */

+#define RCC_CRRCR_HSI48CAL_Pos                 (0U)

+#define RCC_CRRCR_HSI48CAL_Msk                 (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */

+#define RCC_CRRCR_HSI48CAL                     RCC_CRRCR_HSI48CAL_Msk          /*!< HSI48CAL[9:0] bits */

+#define RCC_CRRCR_HSI48CAL_0                   (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */

+#define RCC_CRRCR_HSI48CAL_1                   (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */

+#define RCC_CRRCR_HSI48CAL_2                   (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */

+#define RCC_CRRCR_HSI48CAL_3                   (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */

+#define RCC_CRRCR_HSI48CAL_4                   (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */

+#define RCC_CRRCR_HSI48CAL_5                   (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */

+#define RCC_CRRCR_HSI48CAL_6                   (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */

+#define RCC_CRRCR_HSI48CAL_7                   (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */

+#define RCC_CRRCR_HSI48CAL_8                   (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */

+#define RCC_CRRCR_HSI48CAL_9                   (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */

+

+

+/********************  Bit definition for RCC_CSICFGR register  *****************/

+/*!< CSICAL configuration */

+#define RCC_CSICFGR_CSICAL_Pos                 (0U)

+#define RCC_CSICFGR_CSICAL_Msk                 (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */

+#define RCC_CSICFGR_CSICAL                     RCC_CSICFGR_CSICAL_Msk          /*!< CSICAL[7:0] bits */

+#define RCC_CSICFGR_CSICAL_0                   (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */

+#define RCC_CSICFGR_CSICAL_1                   (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */

+#define RCC_CSICFGR_CSICAL_2                   (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */

+#define RCC_CSICFGR_CSICAL_3                   (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */

+#define RCC_CSICFGR_CSICAL_4                   (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */

+#define RCC_CSICFGR_CSICAL_5                   (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */

+#define RCC_CSICFGR_CSICAL_6                   (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */

+#define RCC_CSICFGR_CSICAL_7                   (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */

+

+/*!< CSITRIM configuration */

+#define RCC_CSICFGR_CSITRIM_Pos                (24U)

+#define RCC_CSICFGR_CSITRIM_Msk                (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */

+#define RCC_CSICFGR_CSITRIM                    RCC_CSICFGR_CSITRIM_Msk         /*!< CSITRIM[5:0] bits */

+#define RCC_CSICFGR_CSITRIM_0                  (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */

+#define RCC_CSICFGR_CSITRIM_1                  (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */

+#define RCC_CSICFGR_CSITRIM_2                  (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */

+#define RCC_CSICFGR_CSITRIM_3                  (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */

+#define RCC_CSICFGR_CSITRIM_4                  (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */

+#define RCC_CSICFGR_CSITRIM_5                  (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */

+

+/********************  Bit definition for RCC_CFGR register  ******************/

+/*!< SW configuration */

+#define RCC_CFGR_SW_Pos                        (0U)

+#define RCC_CFGR_SW_Msk                        (0x7UL << RCC_CFGR_SW_Pos)           /*!< 0x00000007 */

+#define RCC_CFGR_SW                            RCC_CFGR_SW_Msk                     /*!< SW[2:0] bits (System clock Switch) */

+#define RCC_CFGR_SW_0                          (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */

+#define RCC_CFGR_SW_1                          (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */

+#define RCC_CFGR_SW_2                          (0x4UL << RCC_CFGR_SW_Pos)           /*!< 0x00000004 */

+

+#define RCC_CFGR_SW_HSI                        (0x00000000UL)                       /*!< HSI selection as system clock */

+#define RCC_CFGR_SW_CSI                        (0x00000001UL)                       /*!< CSI selection as system clock */

+#define RCC_CFGR_SW_HSE                        (0x00000002UL)                       /*!< HSE selection as system clock */

+#define RCC_CFGR_SW_PLL1                       (0x00000003UL)                       /*!< PLL1 selection as system clock */

+

+/*!< SWS configuration */

+#define RCC_CFGR_SWS_Pos                       (3U)

+#define RCC_CFGR_SWS_Msk                       (0x7UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000038 */

+#define RCC_CFGR_SWS                           RCC_CFGR_SWS_Msk                    /*!< SWS[2:0] bits (System Clock Switch Status) */

+#define RCC_CFGR_SWS_0                         (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */

+#define RCC_CFGR_SWS_1                         (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000010 */

+#define RCC_CFGR_SWS_2                         (0x4UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000020 */

+

+#define RCC_CFGR_SWS_HSI                       (0x00000000UL)                       /*!< HSI used as system clock */

+#define RCC_CFGR_SWS_CSI                       (0x00000008UL)                       /*!< CSI used as system clock */

+#define RCC_CFGR_SWS_HSE                       (0x00000010UL)                       /*!< HSE used as system clock */

+#define RCC_CFGR_SWS_PLL1                      (0x00000018UL)                       /*!< PLL1 used as system clock */

+

+#define RCC_CFGR_STOPWUCK_Pos                  (6U)

+#define RCC_CFGR_STOPWUCK_Msk                  (0x1UL << RCC_CFGR_STOPWUCK_Pos)     /*!< 0x00000040 */

+#define RCC_CFGR_STOPWUCK                      RCC_CFGR_STOPWUCK_Msk                /*!< Wake Up from stop and CSS backup clock selection */

+

+#define RCC_CFGR_STOPKERWUCK_Pos               (7U)

+#define RCC_CFGR_STOPKERWUCK_Msk               (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)  /*!< 0x00000080 */

+#define RCC_CFGR_STOPKERWUCK                   RCC_CFGR_STOPKERWUCK_Msk             /*!< Kernel Clock Selection after a Wake Up from STOP */

+

+/*!< RTCPRE configuration */

+#define RCC_CFGR_RTCPRE_Pos                    (8U)

+#define RCC_CFGR_RTCPRE_Msk                    (0x3FUL << RCC_CFGR_RTCPRE_Pos)

+#define RCC_CFGR_RTCPRE                        RCC_CFGR_RTCPRE_Msk                  /*!< 0x00003F00 */

+#define RCC_CFGR_RTCPRE_0                      (0x1UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000100 */

+#define RCC_CFGR_RTCPRE_1                      (0x2UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000200 */

+#define RCC_CFGR_RTCPRE_2                      (0x4UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000400 */

+#define RCC_CFGR_RTCPRE_3                      (0x8UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000800 */

+#define RCC_CFGR_RTCPRE_4                      (0x10UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00001000 */

+#define RCC_CFGR_RTCPRE_5                      (0x20UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00002000 */

+

+/*!< HRTIMSEL configuration */

+#define RCC_CFGR_HRTIMSEL_Pos                  (14U)

+#define RCC_CFGR_HRTIMSEL_Msk                  (0x1UL << RCC_CFGR_HRTIMSEL_Pos)

+#define RCC_CFGR_HRTIMSEL                      RCC_CFGR_HRTIMSEL_Msk                /*!< 0x00004000 */

+

+/*!< TIMPRE configuration */

+#define RCC_CFGR_TIMPRE_Pos                    (15U)

+#define RCC_CFGR_TIMPRE_Msk                    (0x1UL << RCC_CFGR_TIMPRE_Pos)

+#define RCC_CFGR_TIMPRE                        RCC_CFGR_TIMPRE_Msk                  /*!< 0x00008000 */

+

+/*!< MCO1 configuration */

+#define RCC_CFGR_MCO1_Pos                      (22U)

+#define RCC_CFGR_MCO1_Msk                      (0x7UL << RCC_CFGR_MCO1_Pos)

+#define RCC_CFGR_MCO1                          RCC_CFGR_MCO1_Msk                       /*!< 0x01C00000 */

+#define RCC_CFGR_MCO1_0                        (0x1UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00400000 */

+#define RCC_CFGR_MCO1_1                        (0x2UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00800000 */

+#define RCC_CFGR_MCO1_2                        (0x4UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x01000000 */

+

+#define RCC_CFGR_MCO1PRE_Pos                   (18U)

+#define RCC_CFGR_MCO1PRE_Msk                   (0xFUL << RCC_CFGR_MCO1PRE_Pos)

+#define RCC_CFGR_MCO1PRE                       RCC_CFGR_MCO1PRE_Msk                    /*!< 0x003C0000 */

+#define RCC_CFGR_MCO1PRE_0                     (0x1UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00040000 */

+#define RCC_CFGR_MCO1PRE_1                     (0x2UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00080000 */

+#define RCC_CFGR_MCO1PRE_2                     (0x4UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00100000 */

+#define RCC_CFGR_MCO1PRE_3                     (0x8UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00200000 */

+

+#define RCC_CFGR_MCO2PRE_Pos                   (25U)

+#define RCC_CFGR_MCO2PRE_Msk                   (0xFUL << RCC_CFGR_MCO2PRE_Pos)

+#define RCC_CFGR_MCO2PRE                       RCC_CFGR_MCO2PRE_Msk                    /*!< 0x1E000000 */

+#define RCC_CFGR_MCO2PRE_0                     (0x1UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x02000000 */

+#define RCC_CFGR_MCO2PRE_1                     (0x2UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x04000000 */

+#define RCC_CFGR_MCO2PRE_2                     (0x4UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x08000000 */

+#define RCC_CFGR_MCO2PRE_3                     (0x8UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x10000000 */

+

+#define RCC_CFGR_MCO2_Pos                      (29U)

+#define RCC_CFGR_MCO2_Msk                      (0x7UL << RCC_CFGR_MCO2_Pos)

+#define RCC_CFGR_MCO2                          RCC_CFGR_MCO2_Msk                       /*!< 0xE0000000 */

+#define RCC_CFGR_MCO2_0                        (0x1UL << RCC_CFGR_MCO2_Pos)             /*!< 0x20000000 */

+#define RCC_CFGR_MCO2_1                        (0x2UL << RCC_CFGR_MCO2_Pos)             /*!< 0x40000000 */

+#define RCC_CFGR_MCO2_2                        (0x4UL << RCC_CFGR_MCO2_Pos)             /*!< 0x80000000 */

+

+/********************  Bit definition for RCC_D1CFGR register  ******************/

+/*!< D1HPRE configuration */

+#define RCC_D1CFGR_HPRE_Pos                    (0U)

+#define RCC_D1CFGR_HPRE_Msk                    (0xFUL << RCC_D1CFGR_HPRE_Pos)  /*!< 0x0000000F */

+#define RCC_D1CFGR_HPRE                        RCC_D1CFGR_HPRE_Msk             /*!< HPRE[3:0] bits (AHB3 prescaler) */

+#define RCC_D1CFGR_HPRE_0                      (0x1UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000001 */

+#define RCC_D1CFGR_HPRE_1                      (0x2UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000002 */

+#define RCC_D1CFGR_HPRE_2                      (0x4UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000004 */

+#define RCC_D1CFGR_HPRE_3                      (0x8UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000008 */

+

+

+#define RCC_D1CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)          /*!< AHB3 Clock not divided */

+#define RCC_D1CFGR_HPRE_DIV2_Pos               (3U)

+#define RCC_D1CFGR_HPRE_DIV2_Msk               (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */

+#define RCC_D1CFGR_HPRE_DIV2                   RCC_D1CFGR_HPRE_DIV2_Msk        /*!< AHB3 Clock divided by 2 */

+#define RCC_D1CFGR_HPRE_DIV4_Pos               (0U)

+#define RCC_D1CFGR_HPRE_DIV4_Msk               (0x9UL << RCC_D1CFGR_HPRE_DIV4_Pos) /*!< 0x00000009 */

+#define RCC_D1CFGR_HPRE_DIV4                   RCC_D1CFGR_HPRE_DIV4_Msk        /*!< AHB3 Clock divided by 4 */

+#define RCC_D1CFGR_HPRE_DIV8_Pos               (1U)

+#define RCC_D1CFGR_HPRE_DIV8_Msk               (0x5UL << RCC_D1CFGR_HPRE_DIV8_Pos) /*!< 0x0000000A */

+#define RCC_D1CFGR_HPRE_DIV8                   RCC_D1CFGR_HPRE_DIV8_Msk        /*!< AHB3 Clock divided by 8 */

+#define RCC_D1CFGR_HPRE_DIV16_Pos              (0U)

+#define RCC_D1CFGR_HPRE_DIV16_Msk              (0xBUL << RCC_D1CFGR_HPRE_DIV16_Pos) /*!< 0x0000000B */

+#define RCC_D1CFGR_HPRE_DIV16                  RCC_D1CFGR_HPRE_DIV16_Msk       /*!< AHB3 Clock divided by 16 */

+#define RCC_D1CFGR_HPRE_DIV64_Pos              (2U)

+#define RCC_D1CFGR_HPRE_DIV64_Msk              (0x3UL << RCC_D1CFGR_HPRE_DIV64_Pos) /*!< 0x0000000C */

+#define RCC_D1CFGR_HPRE_DIV64                  RCC_D1CFGR_HPRE_DIV64_Msk       /*!< AHB3 Clock divided by 64 */

+#define RCC_D1CFGR_HPRE_DIV128_Pos             (0U)

+#define RCC_D1CFGR_HPRE_DIV128_Msk             (0xDUL << RCC_D1CFGR_HPRE_DIV128_Pos) /*!< 0x0000000D */

+#define RCC_D1CFGR_HPRE_DIV128                 RCC_D1CFGR_HPRE_DIV128_Msk      /*!< AHB3 Clock divided by 128 */

+#define RCC_D1CFGR_HPRE_DIV256_Pos             (1U)

+#define RCC_D1CFGR_HPRE_DIV256_Msk             (0x7UL << RCC_D1CFGR_HPRE_DIV256_Pos) /*!< 0x0000000E */

+#define RCC_D1CFGR_HPRE_DIV256                 RCC_D1CFGR_HPRE_DIV256_Msk      /*!< AHB3 Clock divided by 256 */

+#define RCC_D1CFGR_HPRE_DIV512_Pos             (0U)

+#define RCC_D1CFGR_HPRE_DIV512_Msk             (0xFUL << RCC_D1CFGR_HPRE_DIV512_Pos) /*!< 0x0000000F */

+#define RCC_D1CFGR_HPRE_DIV512                 RCC_D1CFGR_HPRE_DIV512_Msk      /*!< AHB3 Clock divided by 512 */

+

+/*!< D1PPRE configuration */

+#define RCC_D1CFGR_D1PPRE_Pos                  (4U)

+#define RCC_D1CFGR_D1PPRE_Msk                  (0x7UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000070 */

+#define RCC_D1CFGR_D1PPRE                      RCC_D1CFGR_D1PPRE_Msk           /*!< D1PRE[2:0] bits (APB3 prescaler) */

+#define RCC_D1CFGR_D1PPRE_0                    (0x1UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000010 */

+#define RCC_D1CFGR_D1PPRE_1                    (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */

+#define RCC_D1CFGR_D1PPRE_2                    (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */

+

+#define RCC_D1CFGR_D1PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB3 clock not divided */

+#define RCC_D1CFGR_D1PPRE_DIV2_Pos             (6U)

+#define RCC_D1CFGR_D1PPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_D1CFGR_D1PPRE_DIV2                 RCC_D1CFGR_D1PPRE_DIV2_Msk      /*!< APB3 clock divided by 2 */

+#define RCC_D1CFGR_D1PPRE_DIV4_Pos             (4U)

+#define RCC_D1CFGR_D1PPRE_DIV4_Msk             (0x5UL << RCC_D1CFGR_D1PPRE_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_D1CFGR_D1PPRE_DIV4                 RCC_D1CFGR_D1PPRE_DIV4_Msk      /*!< APB3 clock divided by 4 */

+#define RCC_D1CFGR_D1PPRE_DIV8_Pos             (5U)

+#define RCC_D1CFGR_D1PPRE_DIV8_Msk             (0x3UL << RCC_D1CFGR_D1PPRE_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_D1CFGR_D1PPRE_DIV8                 RCC_D1CFGR_D1PPRE_DIV8_Msk      /*!< APB3 clock divided by 8 */

+#define RCC_D1CFGR_D1PPRE_DIV16_Pos            (4U)

+#define RCC_D1CFGR_D1PPRE_DIV16_Msk            (0x7UL << RCC_D1CFGR_D1PPRE_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_D1CFGR_D1PPRE_DIV16                RCC_D1CFGR_D1PPRE_DIV16_Msk     /*!< APB3 clock divided by 16 */

+

+#define RCC_D1CFGR_D1CPRE_Pos                  (8U)

+#define RCC_D1CFGR_D1CPRE_Msk                  (0xFUL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000F00 */

+#define RCC_D1CFGR_D1CPRE                      RCC_D1CFGR_D1CPRE_Msk           /*!< D1CPRE[2:0] bits (Domain 1 Core prescaler) */

+#define RCC_D1CFGR_D1CPRE_0                    (0x1UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000100 */

+#define RCC_D1CFGR_D1CPRE_1                    (0x2UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000200 */

+#define RCC_D1CFGR_D1CPRE_2                    (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */

+#define RCC_D1CFGR_D1CPRE_3                    (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */

+

+#define RCC_D1CFGR_D1CPRE_DIV1                 ((uint32_t)0x00000000)          /*!< Domain 1 Core clock not divided */

+#define RCC_D1CFGR_D1CPRE_DIV2_Pos             (11U)

+#define RCC_D1CFGR_D1CPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */

+#define RCC_D1CFGR_D1CPRE_DIV2                 RCC_D1CFGR_D1CPRE_DIV2_Msk      /*!< Domain 1 Core clock divided by 2 */

+#define RCC_D1CFGR_D1CPRE_DIV4_Pos             (8U)

+#define RCC_D1CFGR_D1CPRE_DIV4_Msk             (0x9UL << RCC_D1CFGR_D1CPRE_DIV4_Pos) /*!< 0x00000900 */

+#define RCC_D1CFGR_D1CPRE_DIV4                 RCC_D1CFGR_D1CPRE_DIV4_Msk      /*!< Domain 1 Core clock divided by 4 */

+#define RCC_D1CFGR_D1CPRE_DIV8_Pos             (9U)

+#define RCC_D1CFGR_D1CPRE_DIV8_Msk             (0x5UL << RCC_D1CFGR_D1CPRE_DIV8_Pos) /*!< 0x00000A00 */

+#define RCC_D1CFGR_D1CPRE_DIV8                 RCC_D1CFGR_D1CPRE_DIV8_Msk      /*!< Domain 1 Core clock divided by 8 */

+#define RCC_D1CFGR_D1CPRE_DIV16_Pos            (8U)

+#define RCC_D1CFGR_D1CPRE_DIV16_Msk            (0xBUL << RCC_D1CFGR_D1CPRE_DIV16_Pos) /*!< 0x00000B00 */

+#define RCC_D1CFGR_D1CPRE_DIV16                RCC_D1CFGR_D1CPRE_DIV16_Msk     /*!< Domain 1 Core clock divided by 16 */

+#define RCC_D1CFGR_D1CPRE_DIV64_Pos            (10U)

+#define RCC_D1CFGR_D1CPRE_DIV64_Msk            (0x3UL << RCC_D1CFGR_D1CPRE_DIV64_Pos) /*!< 0x00000C00 */

+#define RCC_D1CFGR_D1CPRE_DIV64                RCC_D1CFGR_D1CPRE_DIV64_Msk     /*!< Domain 1 Core clock divided by 64 */

+#define RCC_D1CFGR_D1CPRE_DIV128_Pos           (8U)

+#define RCC_D1CFGR_D1CPRE_DIV128_Msk           (0xDUL << RCC_D1CFGR_D1CPRE_DIV128_Pos) /*!< 0x00000D00 */

+#define RCC_D1CFGR_D1CPRE_DIV128               RCC_D1CFGR_D1CPRE_DIV128_Msk    /*!< Domain 1 Core clock divided by 128 */

+#define RCC_D1CFGR_D1CPRE_DIV256_Pos           (9U)

+#define RCC_D1CFGR_D1CPRE_DIV256_Msk           (0x7UL << RCC_D1CFGR_D1CPRE_DIV256_Pos) /*!< 0x00000E00 */

+#define RCC_D1CFGR_D1CPRE_DIV256               RCC_D1CFGR_D1CPRE_DIV256_Msk    /*!< Domain 1 Core clock divided by 256 */

+#define RCC_D1CFGR_D1CPRE_DIV512_Pos           (8U)

+#define RCC_D1CFGR_D1CPRE_DIV512_Msk           (0xFUL << RCC_D1CFGR_D1CPRE_DIV512_Pos) /*!< 0x00000F00 */

+#define RCC_D1CFGR_D1CPRE_DIV512               RCC_D1CFGR_D1CPRE_DIV512_Msk    /*!< Domain 1 Core clock divided by 512 */

+

+/********************  Bit definition for RCC_D2CFGR register  ******************/

+/*!< D2PPRE1 configuration */

+#define RCC_D2CFGR_D2PPRE1_Pos                 (4U)

+#define RCC_D2CFGR_D2PPRE1_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000070 */

+#define RCC_D2CFGR_D2PPRE1                     RCC_D2CFGR_D2PPRE1_Msk          /*!< D1PPRE1[2:0] bits (APB1 prescaler) */

+#define RCC_D2CFGR_D2PPRE1_0                   (0x1UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000010 */

+#define RCC_D2CFGR_D2PPRE1_1                   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */

+#define RCC_D2CFGR_D2PPRE1_2                   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */

+

+#define RCC_D2CFGR_D2PPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */

+#define RCC_D2CFGR_D2PPRE1_DIV2_Pos            (6U)

+#define RCC_D2CFGR_D2PPRE1_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_D2CFGR_D2PPRE1_DIV2                RCC_D2CFGR_D2PPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */

+#define RCC_D2CFGR_D2PPRE1_DIV4_Pos            (4U)

+#define RCC_D2CFGR_D2PPRE1_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE1_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_D2CFGR_D2PPRE1_DIV4                RCC_D2CFGR_D2PPRE1_DIV4_Msk     /*!< APB1 clock divided by 4 */

+#define RCC_D2CFGR_D2PPRE1_DIV8_Pos            (5U)

+#define RCC_D2CFGR_D2PPRE1_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE1_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_D2CFGR_D2PPRE1_DIV8                RCC_D2CFGR_D2PPRE1_DIV8_Msk     /*!< APB1 clock divided by 8 */

+#define RCC_D2CFGR_D2PPRE1_DIV16_Pos           (4U)

+#define RCC_D2CFGR_D2PPRE1_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE1_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_D2CFGR_D2PPRE1_DIV16               RCC_D2CFGR_D2PPRE1_DIV16_Msk    /*!< APB1 clock divided by 16 */

+

+/*!< D2PPRE2 configuration */

+#define RCC_D2CFGR_D2PPRE2_Pos                 (8U)

+#define RCC_D2CFGR_D2PPRE2_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000700 */

+#define RCC_D2CFGR_D2PPRE2                     RCC_D2CFGR_D2PPRE2_Msk          /*!< D2PPRE2[2:0] bits (APB2 prescaler) */

+#define RCC_D2CFGR_D2PPRE2_0                   (0x1UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000100 */

+#define RCC_D2CFGR_D2PPRE2_1                   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */

+#define RCC_D2CFGR_D2PPRE2_2                   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */

+

+#define RCC_D2CFGR_D2PPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */

+#define RCC_D2CFGR_D2PPRE2_DIV2_Pos            (10U)

+#define RCC_D2CFGR_D2PPRE2_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */

+#define RCC_D2CFGR_D2PPRE2_DIV2                RCC_D2CFGR_D2PPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */

+#define RCC_D2CFGR_D2PPRE2_DIV4_Pos            (8U)

+#define RCC_D2CFGR_D2PPRE2_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE2_DIV4_Pos) /*!< 0x00000500 */

+#define RCC_D2CFGR_D2PPRE2_DIV4                RCC_D2CFGR_D2PPRE2_DIV4_Msk     /*!< APB2 clock divided by 4 */

+#define RCC_D2CFGR_D2PPRE2_DIV8_Pos            (9U)

+#define RCC_D2CFGR_D2PPRE2_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE2_DIV8_Pos) /*!< 0x00000600 */

+#define RCC_D2CFGR_D2PPRE2_DIV8                RCC_D2CFGR_D2PPRE2_DIV8_Msk     /*!< APB2 clock divided by 8 */

+#define RCC_D2CFGR_D2PPRE2_DIV16_Pos           (8U)

+#define RCC_D2CFGR_D2PPRE2_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE2_DIV16_Pos) /*!< 0x00000700 */

+#define RCC_D2CFGR_D2PPRE2_DIV16               RCC_D2CFGR_D2PPRE2_DIV16_Msk    /*!< APB2 clock divided by 16 */

+

+/********************  Bit definition for RCC_D3CFGR register  ******************/

+/*!< D3PPRE configuration */

+#define RCC_D3CFGR_D3PPRE_Pos                  (4U)

+#define RCC_D3CFGR_D3PPRE_Msk                  (0x7UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000070 */

+#define RCC_D3CFGR_D3PPRE                      RCC_D3CFGR_D3PPRE_Msk           /*!< D3PPRE1[2:0] bits (APB4 prescaler) */

+#define RCC_D3CFGR_D3PPRE_0                    (0x1UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000010 */

+#define RCC_D3CFGR_D3PPRE_1                    (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */

+#define RCC_D3CFGR_D3PPRE_2                    (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */

+

+#define RCC_D3CFGR_D3PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */

+#define RCC_D3CFGR_D3PPRE_DIV2_Pos             (6U)

+#define RCC_D3CFGR_D3PPRE_DIV2_Msk             (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_D3CFGR_D3PPRE_DIV2                 RCC_D3CFGR_D3PPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */

+#define RCC_D3CFGR_D3PPRE_DIV4_Pos             (4U)

+#define RCC_D3CFGR_D3PPRE_DIV4_Msk             (0x5UL << RCC_D3CFGR_D3PPRE_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_D3CFGR_D3PPRE_DIV4                 RCC_D3CFGR_D3PPRE_DIV4_Msk      /*!< APB4 clock divided by 4 */

+#define RCC_D3CFGR_D3PPRE_DIV8_Pos             (5U)

+#define RCC_D3CFGR_D3PPRE_DIV8_Msk             (0x3UL << RCC_D3CFGR_D3PPRE_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_D3CFGR_D3PPRE_DIV8                 RCC_D3CFGR_D3PPRE_DIV8_Msk      /*!< APB4 clock divided by 8 */

+#define RCC_D3CFGR_D3PPRE_DIV16_Pos            (4U)

+#define RCC_D3CFGR_D3PPRE_DIV16_Msk            (0x7UL << RCC_D3CFGR_D3PPRE_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_D3CFGR_D3PPRE_DIV16                RCC_D3CFGR_D3PPRE_DIV16_Msk     /*!< APB4 clock divided by 16 */

+

+/********************  Bit definition for RCC_PLLCKSELR register  *************/

+

+#define RCC_PLLCKSELR_PLLSRC_Pos               (0U)

+#define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */

+#define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk

+

+#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)

+#define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */

+#define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_HSE_Pos           (1U)

+#define RCC_PLLCKSELR_PLLSRC_HSE_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */

+#define RCC_PLLCKSELR_PLLSRC_HSE               RCC_PLLCKSELR_PLLSRC_HSE_Msk    /*!< HSE source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_NONE_Pos          (0U)

+#define RCC_PLLCKSELR_PLLSRC_NONE_Msk          (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */

+#define RCC_PLLCKSELR_PLLSRC_NONE              RCC_PLLCKSELR_PLLSRC_NONE_Msk   /*!< No source clock selected  */

+

+#define RCC_PLLCKSELR_DIVM1_Pos                (4U)

+#define RCC_PLLCKSELR_DIVM1_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */

+#define RCC_PLLCKSELR_DIVM1                    RCC_PLLCKSELR_DIVM1_Msk

+#define RCC_PLLCKSELR_DIVM1_0                  (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */

+#define RCC_PLLCKSELR_DIVM1_1                  (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */

+#define RCC_PLLCKSELR_DIVM1_2                  (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */

+#define RCC_PLLCKSELR_DIVM1_3                  (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */

+#define RCC_PLLCKSELR_DIVM1_4                  (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */

+#define RCC_PLLCKSELR_DIVM1_5                  (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */

+

+#define RCC_PLLCKSELR_DIVM2_Pos                (12U)

+#define RCC_PLLCKSELR_DIVM2_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */

+#define RCC_PLLCKSELR_DIVM2                    RCC_PLLCKSELR_DIVM2_Msk

+#define RCC_PLLCKSELR_DIVM2_0                  (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */

+#define RCC_PLLCKSELR_DIVM2_1                  (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */

+#define RCC_PLLCKSELR_DIVM2_2                  (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */

+#define RCC_PLLCKSELR_DIVM2_3                  (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */

+#define RCC_PLLCKSELR_DIVM2_4                  (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */

+#define RCC_PLLCKSELR_DIVM2_5                  (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */

+

+#define RCC_PLLCKSELR_DIVM3_Pos                (20U)

+#define RCC_PLLCKSELR_DIVM3_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */

+#define RCC_PLLCKSELR_DIVM3                    RCC_PLLCKSELR_DIVM3_Msk

+#define RCC_PLLCKSELR_DIVM3_0                  (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */

+#define RCC_PLLCKSELR_DIVM3_1                  (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */

+#define RCC_PLLCKSELR_DIVM3_2                  (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */

+#define RCC_PLLCKSELR_DIVM3_3                  (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */

+#define RCC_PLLCKSELR_DIVM3_4                  (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */

+#define RCC_PLLCKSELR_DIVM3_5                  (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */

+

+/********************  Bit definition for RCC_PLLCFGR register  ***************/

+

+#define RCC_PLLCFGR_PLL1FRACEN_Pos             (0U)

+#define RCC_PLLCFGR_PLL1FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */

+#define RCC_PLLCFGR_PLL1FRACEN                 RCC_PLLCFGR_PLL1FRACEN_Msk

+#define RCC_PLLCFGR_PLL1VCOSEL_Pos             (1U)

+#define RCC_PLLCFGR_PLL1VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */

+#define RCC_PLLCFGR_PLL1VCOSEL                 RCC_PLLCFGR_PLL1VCOSEL_Msk

+#define RCC_PLLCFGR_PLL1RGE_Pos                (2U)

+#define RCC_PLLCFGR_PLL1RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */

+#define RCC_PLLCFGR_PLL1RGE                    RCC_PLLCFGR_PLL1RGE_Msk

+#define RCC_PLLCFGR_PLL1RGE_0                  (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL1RGE_1                  (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */

+#define RCC_PLLCFGR_PLL1RGE_2                  (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */

+#define RCC_PLLCFGR_PLL1RGE_3                  (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */

+

+#define RCC_PLLCFGR_PLL2FRACEN_Pos             (4U)

+#define RCC_PLLCFGR_PLL2FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */

+#define RCC_PLLCFGR_PLL2FRACEN                 RCC_PLLCFGR_PLL2FRACEN_Msk

+#define RCC_PLLCFGR_PLL2VCOSEL_Pos             (5U)

+#define RCC_PLLCFGR_PLL2VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */

+#define RCC_PLLCFGR_PLL2VCOSEL                 RCC_PLLCFGR_PLL2VCOSEL_Msk

+#define RCC_PLLCFGR_PLL2RGE_Pos                (6U)

+#define RCC_PLLCFGR_PLL2RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */

+#define RCC_PLLCFGR_PLL2RGE                    RCC_PLLCFGR_PLL2RGE_Msk

+#define RCC_PLLCFGR_PLL2RGE_0                  (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL2RGE_1                  (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */

+#define RCC_PLLCFGR_PLL2RGE_2                  (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */

+#define RCC_PLLCFGR_PLL2RGE_3                  (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */

+

+#define RCC_PLLCFGR_PLL3FRACEN_Pos             (8U)

+#define RCC_PLLCFGR_PLL3FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */

+#define RCC_PLLCFGR_PLL3FRACEN                 RCC_PLLCFGR_PLL3FRACEN_Msk

+#define RCC_PLLCFGR_PLL3VCOSEL_Pos             (9U)

+#define RCC_PLLCFGR_PLL3VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */

+#define RCC_PLLCFGR_PLL3VCOSEL                 RCC_PLLCFGR_PLL3VCOSEL_Msk

+#define RCC_PLLCFGR_PLL3RGE_Pos                (10U)

+#define RCC_PLLCFGR_PLL3RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */

+#define RCC_PLLCFGR_PLL3RGE                    RCC_PLLCFGR_PLL3RGE_Msk

+#define RCC_PLLCFGR_PLL3RGE_0                  (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL3RGE_1                  (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */

+#define RCC_PLLCFGR_PLL3RGE_2                  (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */

+#define RCC_PLLCFGR_PLL3RGE_3                  (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */

+

+#define RCC_PLLCFGR_DIVP1EN_Pos                (16U)

+#define RCC_PLLCFGR_DIVP1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */

+#define RCC_PLLCFGR_DIVP1EN                    RCC_PLLCFGR_DIVP1EN_Msk

+#define RCC_PLLCFGR_DIVQ1EN_Pos                (17U)

+#define RCC_PLLCFGR_DIVQ1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */

+#define RCC_PLLCFGR_DIVQ1EN                    RCC_PLLCFGR_DIVQ1EN_Msk

+#define RCC_PLLCFGR_DIVR1EN_Pos                (18U)

+#define RCC_PLLCFGR_DIVR1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */

+#define RCC_PLLCFGR_DIVR1EN                    RCC_PLLCFGR_DIVR1EN_Msk

+

+#define RCC_PLLCFGR_DIVP2EN_Pos                (19U)

+#define RCC_PLLCFGR_DIVP2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */

+#define RCC_PLLCFGR_DIVP2EN                    RCC_PLLCFGR_DIVP2EN_Msk

+#define RCC_PLLCFGR_DIVQ2EN_Pos                (20U)

+#define RCC_PLLCFGR_DIVQ2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */

+#define RCC_PLLCFGR_DIVQ2EN                    RCC_PLLCFGR_DIVQ2EN_Msk

+#define RCC_PLLCFGR_DIVR2EN_Pos                (21U)

+#define RCC_PLLCFGR_DIVR2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */

+#define RCC_PLLCFGR_DIVR2EN                    RCC_PLLCFGR_DIVR2EN_Msk

+

+#define RCC_PLLCFGR_DIVP3EN_Pos                (22U)

+#define RCC_PLLCFGR_DIVP3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */

+#define RCC_PLLCFGR_DIVP3EN                    RCC_PLLCFGR_DIVP3EN_Msk

+#define RCC_PLLCFGR_DIVQ3EN_Pos                (23U)

+#define RCC_PLLCFGR_DIVQ3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */

+#define RCC_PLLCFGR_DIVQ3EN                    RCC_PLLCFGR_DIVQ3EN_Msk

+#define RCC_PLLCFGR_DIVR3EN_Pos                (24U)

+#define RCC_PLLCFGR_DIVR3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */

+#define RCC_PLLCFGR_DIVR3EN                    RCC_PLLCFGR_DIVR3EN_Msk

+

+

+/********************  Bit definition for RCC_PLL1DIVR register  ***************/

+#define RCC_PLL1DIVR_N1_Pos                    (0U)

+#define RCC_PLL1DIVR_N1_Msk                    (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */

+#define RCC_PLL1DIVR_N1                        RCC_PLL1DIVR_N1_Msk

+#define RCC_PLL1DIVR_P1_Pos                    (9U)

+#define RCC_PLL1DIVR_P1_Msk                    (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL1DIVR_P1                        RCC_PLL1DIVR_P1_Msk

+#define RCC_PLL1DIVR_Q1_Pos                    (16U)

+#define RCC_PLL1DIVR_Q1_Msk                    (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */

+#define RCC_PLL1DIVR_Q1                        RCC_PLL1DIVR_Q1_Msk

+#define RCC_PLL1DIVR_R1_Pos                    (24U)

+#define RCC_PLL1DIVR_R1_Msk                    (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */

+#define RCC_PLL1DIVR_R1                        RCC_PLL1DIVR_R1_Msk

+

+/********************  Bit definition for RCC_PLL1FRACR register  ***************/

+#define RCC_PLL1FRACR_FRACN1_Pos               (3U)

+#define RCC_PLL1FRACR_FRACN1_Msk               (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL1FRACR_FRACN1                   RCC_PLL1FRACR_FRACN1_Msk

+

+/********************  Bit definition for RCC_PLL2DIVR register  ***************/

+#define RCC_PLL2DIVR_N2_Pos                    (0U)

+#define RCC_PLL2DIVR_N2_Msk                    (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */

+#define RCC_PLL2DIVR_N2                        RCC_PLL2DIVR_N2_Msk

+#define RCC_PLL2DIVR_P2_Pos                    (9U)

+#define RCC_PLL2DIVR_P2_Msk                    (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL2DIVR_P2                        RCC_PLL2DIVR_P2_Msk

+#define RCC_PLL2DIVR_Q2_Pos                    (16U)

+#define RCC_PLL2DIVR_Q2_Msk                    (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */

+#define RCC_PLL2DIVR_Q2                        RCC_PLL2DIVR_Q2_Msk

+#define RCC_PLL2DIVR_R2_Pos                    (24U)

+#define RCC_PLL2DIVR_R2_Msk                    (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */

+#define RCC_PLL2DIVR_R2                        RCC_PLL2DIVR_R2_Msk

+

+/********************  Bit definition for RCC_PLL2FRACR register  ***************/

+#define RCC_PLL2FRACR_FRACN2_Pos               (3U)

+#define RCC_PLL2FRACR_FRACN2_Msk               (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL2FRACR_FRACN2                   RCC_PLL2FRACR_FRACN2_Msk

+

+/********************  Bit definition for RCC_PLL3DIVR register  ***************/

+#define RCC_PLL3DIVR_N3_Pos                    (0U)

+#define RCC_PLL3DIVR_N3_Msk                    (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */

+#define RCC_PLL3DIVR_N3                        RCC_PLL3DIVR_N3_Msk

+#define RCC_PLL3DIVR_P3_Pos                    (9U)

+#define RCC_PLL3DIVR_P3_Msk                    (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL3DIVR_P3                        RCC_PLL3DIVR_P3_Msk

+#define RCC_PLL3DIVR_Q3_Pos                    (16U)

+#define RCC_PLL3DIVR_Q3_Msk                    (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */

+#define RCC_PLL3DIVR_Q3                        RCC_PLL3DIVR_Q3_Msk

+#define RCC_PLL3DIVR_R3_Pos                    (24U)

+#define RCC_PLL3DIVR_R3_Msk                    (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */

+#define RCC_PLL3DIVR_R3                        RCC_PLL3DIVR_R3_Msk

+

+/********************  Bit definition for RCC_PLL3FRACR register  ***************/

+#define RCC_PLL3FRACR_FRACN3_Pos               (3U)

+#define RCC_PLL3FRACR_FRACN3_Msk               (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL3FRACR_FRACN3                   RCC_PLL3FRACR_FRACN3_Msk

+

+/********************  Bit definition for RCC_D1CCIPR register  ***************/

+#define RCC_D1CCIPR_FMCSEL_Pos                 (0U)

+#define RCC_D1CCIPR_FMCSEL_Msk                 (0x3UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000003 */

+#define RCC_D1CCIPR_FMCSEL                     RCC_D1CCIPR_FMCSEL_Msk

+#define RCC_D1CCIPR_FMCSEL_0                   (0x1UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000001 */

+#define RCC_D1CCIPR_FMCSEL_1                   (0x2UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000002 */

+#define RCC_D1CCIPR_QSPISEL_Pos                (4U)

+#define RCC_D1CCIPR_QSPISEL_Msk                (0x3UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000030 */

+#define RCC_D1CCIPR_QSPISEL                    RCC_D1CCIPR_QSPISEL_Msk

+#define RCC_D1CCIPR_QSPISEL_0                  (0x1UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000010 */

+#define RCC_D1CCIPR_QSPISEL_1                  (0x2UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000020 */

+#define RCC_D1CCIPR_SDMMCSEL_Pos               (16U)

+#define RCC_D1CCIPR_SDMMCSEL_Msk               (0x1UL << RCC_D1CCIPR_SDMMCSEL_Pos) /*!< 0x00010000 */

+#define RCC_D1CCIPR_SDMMCSEL                   RCC_D1CCIPR_SDMMCSEL_Msk

+#define RCC_D1CCIPR_CKPERSEL_Pos               (28U)

+#define RCC_D1CCIPR_CKPERSEL_Msk               (0x3UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x30000000 */

+#define RCC_D1CCIPR_CKPERSEL                   RCC_D1CCIPR_CKPERSEL_Msk

+#define RCC_D1CCIPR_CKPERSEL_0                 (0x1UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x10000000 */

+#define RCC_D1CCIPR_CKPERSEL_1                 (0x2UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x20000000 */

+

+/********************  Bit definition for RCC_D2CCIP1R register  ***************/

+#define RCC_D2CCIP1R_SAI1SEL_Pos               (0U)

+#define RCC_D2CCIP1R_SAI1SEL_Msk               (0x7UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000007 */

+#define RCC_D2CCIP1R_SAI1SEL                   RCC_D2CCIP1R_SAI1SEL_Msk

+#define RCC_D2CCIP1R_SAI1SEL_0                 (0x1UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000001 */

+#define RCC_D2CCIP1R_SAI1SEL_1                 (0x2UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000002 */

+#define RCC_D2CCIP1R_SAI1SEL_2                 (0x4UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000004 */

+

+#define RCC_D2CCIP1R_SAI23SEL_Pos              (6U)

+#define RCC_D2CCIP1R_SAI23SEL_Msk              (0x7UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x000001C0 */

+#define RCC_D2CCIP1R_SAI23SEL                  RCC_D2CCIP1R_SAI23SEL_Msk

+#define RCC_D2CCIP1R_SAI23SEL_0                (0x1UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000040 */

+#define RCC_D2CCIP1R_SAI23SEL_1                (0x2UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000080 */

+#define RCC_D2CCIP1R_SAI23SEL_2                (0x4UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000100 */

+

+#define RCC_D2CCIP1R_SPI123SEL_Pos             (12U)

+#define RCC_D2CCIP1R_SPI123SEL_Msk             (0x7UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */

+#define RCC_D2CCIP1R_SPI123SEL                 RCC_D2CCIP1R_SPI123SEL_Msk

+#define RCC_D2CCIP1R_SPI123SEL_0               (0x1UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */

+#define RCC_D2CCIP1R_SPI123SEL_1               (0x2UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */

+#define RCC_D2CCIP1R_SPI123SEL_2               (0x4UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */

+

+#define RCC_D2CCIP1R_SPI45SEL_Pos              (16U)

+#define RCC_D2CCIP1R_SPI45SEL_Msk              (0x7UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00070000 */

+#define RCC_D2CCIP1R_SPI45SEL                  RCC_D2CCIP1R_SPI45SEL_Msk

+#define RCC_D2CCIP1R_SPI45SEL_0                (0x1UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00010000 */

+#define RCC_D2CCIP1R_SPI45SEL_1                (0x2UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00020000 */

+#define RCC_D2CCIP1R_SPI45SEL_2                (0x4UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00040000 */

+

+#define RCC_D2CCIP1R_SPDIFSEL_Pos              (20U)

+#define RCC_D2CCIP1R_SPDIFSEL_Msk              (0x3UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00300000 */

+#define RCC_D2CCIP1R_SPDIFSEL                  RCC_D2CCIP1R_SPDIFSEL_Msk

+#define RCC_D2CCIP1R_SPDIFSEL_0                (0x1UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00100000 */

+#define RCC_D2CCIP1R_SPDIFSEL_1                (0x2UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00200000 */

+

+#define RCC_D2CCIP1R_DFSDM1SEL_Pos             (24U)

+#define RCC_D2CCIP1R_DFSDM1SEL_Msk             (0x1UL << RCC_D2CCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */

+#define RCC_D2CCIP1R_DFSDM1SEL                 RCC_D2CCIP1R_DFSDM1SEL_Msk

+

+#define RCC_D2CCIP1R_FDCANSEL_Pos              (28U)

+#define RCC_D2CCIP1R_FDCANSEL_Msk              (0x3UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x30000000 */

+#define RCC_D2CCIP1R_FDCANSEL                  RCC_D2CCIP1R_FDCANSEL_Msk

+#define RCC_D2CCIP1R_FDCANSEL_0                (0x1UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x10000000 */

+#define RCC_D2CCIP1R_FDCANSEL_1                (0x2UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x20000000 */

+

+#define RCC_D2CCIP1R_SWPSEL_Pos                (31U)

+#define RCC_D2CCIP1R_SWPSEL_Msk                (0x1UL << RCC_D2CCIP1R_SWPSEL_Pos) /*!< 0x80000000 */

+#define RCC_D2CCIP1R_SWPSEL                    RCC_D2CCIP1R_SWPSEL_Msk

+

+/********************  Bit definition for RCC_D2CCIP2R register  ***************/

+#define RCC_D2CCIP2R_USART16SEL_Pos            (3U)

+#define RCC_D2CCIP2R_USART16SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000038 */

+#define RCC_D2CCIP2R_USART16SEL                RCC_D2CCIP2R_USART16SEL_Msk

+#define RCC_D2CCIP2R_USART16SEL_0              (0x1UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000008 */

+#define RCC_D2CCIP2R_USART16SEL_1              (0x2UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000010 */

+#define RCC_D2CCIP2R_USART16SEL_2              (0x4UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000020 */

+

+#define RCC_D2CCIP2R_USART28SEL_Pos            (0U)

+#define RCC_D2CCIP2R_USART28SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000007 */

+#define RCC_D2CCIP2R_USART28SEL                RCC_D2CCIP2R_USART28SEL_Msk

+#define RCC_D2CCIP2R_USART28SEL_0              (0x1UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000001 */

+#define RCC_D2CCIP2R_USART28SEL_1              (0x2UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000002 */

+#define RCC_D2CCIP2R_USART28SEL_2              (0x4UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000004 */

+

+#define RCC_D2CCIP2R_RNGSEL_Pos                (8U)

+#define RCC_D2CCIP2R_RNGSEL_Msk                (0x3UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000300 */

+#define RCC_D2CCIP2R_RNGSEL                    RCC_D2CCIP2R_RNGSEL_Msk

+#define RCC_D2CCIP2R_RNGSEL_0                  (0x1UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000100 */

+#define RCC_D2CCIP2R_RNGSEL_1                  (0x2UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000200 */

+

+#define RCC_D2CCIP2R_I2C123SEL_Pos             (12U)

+#define RCC_D2CCIP2R_I2C123SEL_Msk             (0x3UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00003000 */

+#define RCC_D2CCIP2R_I2C123SEL                 RCC_D2CCIP2R_I2C123SEL_Msk

+#define RCC_D2CCIP2R_I2C123SEL_0               (0x1UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00001000 */

+#define RCC_D2CCIP2R_I2C123SEL_1               (0x2UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00002000 */

+

+#define RCC_D2CCIP2R_USBSEL_Pos                (20U)

+#define RCC_D2CCIP2R_USBSEL_Msk                (0x3UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00300000 */

+#define RCC_D2CCIP2R_USBSEL                    RCC_D2CCIP2R_USBSEL_Msk

+#define RCC_D2CCIP2R_USBSEL_0                  (0x1UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00100000 */

+#define RCC_D2CCIP2R_USBSEL_1                  (0x2UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00200000 */

+

+#define RCC_D2CCIP2R_CECSEL_Pos                (22U)

+#define RCC_D2CCIP2R_CECSEL_Msk                (0x3UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00C00000 */

+#define RCC_D2CCIP2R_CECSEL                    RCC_D2CCIP2R_CECSEL_Msk

+#define RCC_D2CCIP2R_CECSEL_0                  (0x1UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00400000 */

+#define RCC_D2CCIP2R_CECSEL_1                  (0x2UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00800000 */

+

+#define RCC_D2CCIP2R_LPTIM1SEL_Pos             (28U)

+#define RCC_D2CCIP2R_LPTIM1SEL_Msk             (0x7UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x70000000 */

+#define RCC_D2CCIP2R_LPTIM1SEL                 RCC_D2CCIP2R_LPTIM1SEL_Msk

+#define RCC_D2CCIP2R_LPTIM1SEL_0               (0x1UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x10000000 */

+#define RCC_D2CCIP2R_LPTIM1SEL_1               (0x2UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x20000000 */

+#define RCC_D2CCIP2R_LPTIM1SEL_2               (0x4UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition for RCC_D3CCIPR register  ***************/

+#define RCC_D3CCIPR_LPUART1SEL_Pos             (0U)

+#define RCC_D3CCIPR_LPUART1SEL_Msk             (0x7UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000007 */

+#define RCC_D3CCIPR_LPUART1SEL                 RCC_D3CCIPR_LPUART1SEL_Msk

+#define RCC_D3CCIPR_LPUART1SEL_0               (0x1UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000001 */

+#define RCC_D3CCIPR_LPUART1SEL_1               (0x2UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000002 */

+#define RCC_D3CCIPR_LPUART1SEL_2               (0x4UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000004 */

+

+#define RCC_D3CCIPR_I2C4SEL_Pos                (8U)

+#define RCC_D3CCIPR_I2C4SEL_Msk                (0x3UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000300 */

+#define RCC_D3CCIPR_I2C4SEL                    RCC_D3CCIPR_I2C4SEL_Msk

+#define RCC_D3CCIPR_I2C4SEL_0                  (0x1UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000100 */

+#define RCC_D3CCIPR_I2C4SEL_1                  (0x2UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000200 */

+

+#define RCC_D3CCIPR_LPTIM2SEL_Pos              (10U)

+#define RCC_D3CCIPR_LPTIM2SEL_Msk              (0x7UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001C00 */

+#define RCC_D3CCIPR_LPTIM2SEL                  RCC_D3CCIPR_LPTIM2SEL_Msk

+#define RCC_D3CCIPR_LPTIM2SEL_0                (0x1UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000400 */

+#define RCC_D3CCIPR_LPTIM2SEL_1                (0x2UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000800 */

+#define RCC_D3CCIPR_LPTIM2SEL_2                (0x4UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001000 */

+

+#define RCC_D3CCIPR_LPTIM345SEL_Pos            (13U)

+#define RCC_D3CCIPR_LPTIM345SEL_Msk            (0x7UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x0000E000 */

+#define RCC_D3CCIPR_LPTIM345SEL                RCC_D3CCIPR_LPTIM345SEL_Msk

+#define RCC_D3CCIPR_LPTIM345SEL_0              (0x1UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00002000 */

+#define RCC_D3CCIPR_LPTIM345SEL_1              (0x2UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00004000 */

+#define RCC_D3CCIPR_LPTIM345SEL_2              (0x4UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00008000 */

+

+#define RCC_D3CCIPR_SAI4ASEL_Pos               (21U)

+#define RCC_D3CCIPR_SAI4ASEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00E00000 */

+#define RCC_D3CCIPR_SAI4ASEL                   RCC_D3CCIPR_SAI4ASEL_Msk

+#define RCC_D3CCIPR_SAI4ASEL_0                 (0x1UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00200000 */

+#define RCC_D3CCIPR_SAI4ASEL_1                 (0x2UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00400000 */

+#define RCC_D3CCIPR_SAI4ASEL_2                 (0x4UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00800000 */

+

+#define RCC_D3CCIPR_SAI4BSEL_Pos               (24U)

+#define RCC_D3CCIPR_SAI4BSEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x07000000 */

+#define RCC_D3CCIPR_SAI4BSEL                   RCC_D3CCIPR_SAI4BSEL_Msk

+#define RCC_D3CCIPR_SAI4BSEL_0                 (0x1UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x01000000 */

+#define RCC_D3CCIPR_SAI4BSEL_1                 (0x2UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x02000000 */

+#define RCC_D3CCIPR_SAI4BSEL_2                 (0x4UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x04000000 */

+

+#define RCC_D3CCIPR_ADCSEL_Pos                 (16U)

+#define RCC_D3CCIPR_ADCSEL_Msk                 (0x3UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00030000 */

+#define RCC_D3CCIPR_ADCSEL                     RCC_D3CCIPR_ADCSEL_Msk

+#define RCC_D3CCIPR_ADCSEL_0                   (0x1UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00010000 */

+#define RCC_D3CCIPR_ADCSEL_1                   (0x2UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00020000 */

+

+#define RCC_D3CCIPR_SPI6SEL_Pos                (28U)

+#define RCC_D3CCIPR_SPI6SEL_Msk                (0x7UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x70000000 */

+#define RCC_D3CCIPR_SPI6SEL                    RCC_D3CCIPR_SPI6SEL_Msk

+#define RCC_D3CCIPR_SPI6SEL_0                  (0x1UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x10000000 */

+#define RCC_D3CCIPR_SPI6SEL_1                  (0x2UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x20000000 */

+#define RCC_D3CCIPR_SPI6SEL_2                  (0x4UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x40000000 */

+/********************  Bit definition for RCC_CIER register  ******************/

+#define RCC_CIER_LSIRDYIE_Pos                  (0U)

+#define RCC_CIER_LSIRDYIE_Msk                  (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */

+#define RCC_CIER_LSIRDYIE                      RCC_CIER_LSIRDYIE_Msk

+#define RCC_CIER_LSERDYIE_Pos                  (1U)

+#define RCC_CIER_LSERDYIE_Msk                  (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */

+#define RCC_CIER_LSERDYIE                      RCC_CIER_LSERDYIE_Msk

+#define RCC_CIER_HSIRDYIE_Pos                  (2U)

+#define RCC_CIER_HSIRDYIE_Msk                  (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */

+#define RCC_CIER_HSIRDYIE                      RCC_CIER_HSIRDYIE_Msk

+#define RCC_CIER_HSERDYIE_Pos                  (3U)

+#define RCC_CIER_HSERDYIE_Msk                  (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */

+#define RCC_CIER_HSERDYIE                      RCC_CIER_HSERDYIE_Msk

+#define RCC_CIER_CSIRDYIE_Pos                  (4U)

+#define RCC_CIER_CSIRDYIE_Msk                  (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */

+#define RCC_CIER_CSIRDYIE                      RCC_CIER_CSIRDYIE_Msk

+#define RCC_CIER_HSI48RDYIE_Pos                (5U)

+#define RCC_CIER_HSI48RDYIE_Msk                (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */

+#define RCC_CIER_HSI48RDYIE                    RCC_CIER_HSI48RDYIE_Msk

+#define RCC_CIER_PLL1RDYIE_Pos                 (6U)

+#define RCC_CIER_PLL1RDYIE_Msk                 (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */

+#define RCC_CIER_PLL1RDYIE                     RCC_CIER_PLL1RDYIE_Msk

+#define RCC_CIER_PLL2RDYIE_Pos                 (7U)

+#define RCC_CIER_PLL2RDYIE_Msk                 (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */

+#define RCC_CIER_PLL2RDYIE                     RCC_CIER_PLL2RDYIE_Msk

+#define RCC_CIER_PLL3RDYIE_Pos                 (8U)

+#define RCC_CIER_PLL3RDYIE_Msk                 (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */

+#define RCC_CIER_PLL3RDYIE                     RCC_CIER_PLL3RDYIE_Msk

+#define RCC_CIER_LSECSSIE_Pos                  (9U)

+#define RCC_CIER_LSECSSIE_Msk                  (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */

+#define RCC_CIER_LSECSSIE                      RCC_CIER_LSECSSIE_Msk

+

+/********************  Bit definition for RCC_CIFR register  ******************/

+#define RCC_CIFR_LSIRDYF_Pos                   (0U)

+#define RCC_CIFR_LSIRDYF_Msk                   (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */

+#define RCC_CIFR_LSIRDYF                       RCC_CIFR_LSIRDYF_Msk

+#define RCC_CIFR_LSERDYF_Pos                   (1U)

+#define RCC_CIFR_LSERDYF_Msk                   (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */

+#define RCC_CIFR_LSERDYF                       RCC_CIFR_LSERDYF_Msk

+#define RCC_CIFR_HSIRDYF_Pos                   (2U)

+#define RCC_CIFR_HSIRDYF_Msk                   (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */

+#define RCC_CIFR_HSIRDYF                       RCC_CIFR_HSIRDYF_Msk

+#define RCC_CIFR_HSERDYF_Pos                   (3U)

+#define RCC_CIFR_HSERDYF_Msk                   (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */

+#define RCC_CIFR_HSERDYF                       RCC_CIFR_HSERDYF_Msk

+#define RCC_CIFR_CSIRDYF_Pos                   (4U)

+#define RCC_CIFR_CSIRDYF_Msk                   (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */

+#define RCC_CIFR_CSIRDYF                       RCC_CIFR_CSIRDYF_Msk

+#define RCC_CIFR_HSI48RDYF_Pos                 (5U)

+#define RCC_CIFR_HSI48RDYF_Msk                 (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */

+#define RCC_CIFR_HSI48RDYF                     RCC_CIFR_HSI48RDYF_Msk

+#define RCC_CIFR_PLLRDYF_Pos                   (6U)

+#define RCC_CIFR_PLLRDYF_Msk                   (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */

+#define RCC_CIFR_PLLRDYF                       RCC_CIFR_PLLRDYF_Msk

+#define RCC_CIFR_PLL2RDYF_Pos                  (7U)

+#define RCC_CIFR_PLL2RDYF_Msk                  (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */

+#define RCC_CIFR_PLL2RDYF                      RCC_CIFR_PLL2RDYF_Msk

+#define RCC_CIFR_PLL3RDYF_Pos                  (8U)

+#define RCC_CIFR_PLL3RDYF_Msk                  (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */

+#define RCC_CIFR_PLL3RDYF                      RCC_CIFR_PLL3RDYF_Msk

+#define RCC_CIFR_LSECSSF_Pos                   (9U)

+#define RCC_CIFR_LSECSSF_Msk                   (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */

+#define RCC_CIFR_LSECSSF                       RCC_CIFR_LSECSSF_Msk

+#define RCC_CIFR_HSECSSF_Pos                   (10U)

+#define RCC_CIFR_HSECSSF_Msk                   (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */

+#define RCC_CIFR_HSECSSF                       RCC_CIFR_HSECSSF_Msk

+

+/********************  Bit definition for RCC_CICR register  ******************/

+#define RCC_CICR_LSIRDYC_Pos                   (0U)

+#define RCC_CICR_LSIRDYC_Msk                   (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */

+#define RCC_CICR_LSIRDYC                       RCC_CICR_LSIRDYC_Msk

+#define RCC_CICR_LSERDYC_Pos                   (1U)

+#define RCC_CICR_LSERDYC_Msk                   (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */

+#define RCC_CICR_LSERDYC                       RCC_CICR_LSERDYC_Msk

+#define RCC_CICR_HSIRDYC_Pos                   (2U)

+#define RCC_CICR_HSIRDYC_Msk                   (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */

+#define RCC_CICR_HSIRDYC                       RCC_CICR_HSIRDYC_Msk

+#define RCC_CICR_HSERDYC_Pos                   (3U)

+#define RCC_CICR_HSERDYC_Msk                   (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */

+#define RCC_CICR_HSERDYC                       RCC_CICR_HSERDYC_Msk

+#define RCC_CICR_CSIRDYC_Pos                   (4U)

+#define RCC_CICR_CSIRDYC_Msk                   (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */

+#define RCC_CICR_CSIRDYC                       RCC_CICR_CSIRDYC_Msk

+#define RCC_CICR_HSI48RDYC_Pos                 (5U)

+#define RCC_CICR_HSI48RDYC_Msk                 (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */

+#define RCC_CICR_HSI48RDYC                     RCC_CICR_HSI48RDYC_Msk

+#define RCC_CICR_PLLRDYC_Pos                   (6U)

+#define RCC_CICR_PLLRDYC_Msk                   (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */

+#define RCC_CICR_PLLRDYC                       RCC_CICR_PLLRDYC_Msk

+#define RCC_CICR_PLL2RDYC_Pos                  (7U)

+#define RCC_CICR_PLL2RDYC_Msk                  (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */

+#define RCC_CICR_PLL2RDYC                      RCC_CICR_PLL2RDYC_Msk

+#define RCC_CICR_PLL3RDYC_Pos                  (8U)

+#define RCC_CICR_PLL3RDYC_Msk                  (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */

+#define RCC_CICR_PLL3RDYC                      RCC_CICR_PLL3RDYC_Msk

+#define RCC_CICR_LSECSSC_Pos                   (9U)

+#define RCC_CICR_LSECSSC_Msk                   (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */

+#define RCC_CICR_LSECSSC                       RCC_CICR_LSECSSC_Msk

+#define RCC_CICR_HSECSSC_Pos                   (10U)

+#define RCC_CICR_HSECSSC_Msk                   (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */

+#define RCC_CICR_HSECSSC                       RCC_CICR_HSECSSC_Msk

+

+/********************  Bit definition for RCC_BDCR register  ******************/

+#define RCC_BDCR_LSEON_Pos                     (0U)

+#define RCC_BDCR_LSEON_Msk                     (0x1UL << RCC_BDCR_LSEON_Pos)   /*!< 0x00000001 */

+#define RCC_BDCR_LSEON                         RCC_BDCR_LSEON_Msk

+#define RCC_BDCR_LSERDY_Pos                    (1U)

+#define RCC_BDCR_LSERDY_Msk                    (0x1UL << RCC_BDCR_LSERDY_Pos)  /*!< 0x00000002 */

+#define RCC_BDCR_LSERDY                        RCC_BDCR_LSERDY_Msk

+#define RCC_BDCR_LSEBYP_Pos                    (2U)

+#define RCC_BDCR_LSEBYP_Msk                    (0x1UL << RCC_BDCR_LSEBYP_Pos)  /*!< 0x00000004 */

+#define RCC_BDCR_LSEBYP                        RCC_BDCR_LSEBYP_Msk

+

+#define RCC_BDCR_LSEDRV_Pos                    (3U)

+#define RCC_BDCR_LSEDRV_Msk                    (0x3UL << RCC_BDCR_LSEDRV_Pos)  /*!< 0x00000018 */

+#define RCC_BDCR_LSEDRV                        RCC_BDCR_LSEDRV_Msk

+#define RCC_BDCR_LSEDRV_0                      (0x1UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000008 */

+#define RCC_BDCR_LSEDRV_1                      (0x2UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000010 */

+

+#define RCC_BDCR_LSECSSON_Pos                  (5U)

+#define RCC_BDCR_LSECSSON_Msk                  (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */

+#define RCC_BDCR_LSECSSON                      RCC_BDCR_LSECSSON_Msk

+#define RCC_BDCR_LSECSSD_Pos                   (6U)

+#define RCC_BDCR_LSECSSD_Msk                   (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */

+#define RCC_BDCR_LSECSSD                       RCC_BDCR_LSECSSD_Msk

+

+#define RCC_BDCR_RTCSEL_Pos                    (8U)

+#define RCC_BDCR_RTCSEL_Msk                    (0x3UL << RCC_BDCR_RTCSEL_Pos)  /*!< 0x00000300 */

+#define RCC_BDCR_RTCSEL                        RCC_BDCR_RTCSEL_Msk

+#define RCC_BDCR_RTCSEL_0                      (0x1UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000100 */

+#define RCC_BDCR_RTCSEL_1                      (0x2UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000200 */

+

+#define RCC_BDCR_RTCEN_Pos                     (15U)

+#define RCC_BDCR_RTCEN_Msk                     (0x1UL << RCC_BDCR_RTCEN_Pos)   /*!< 0x00008000 */

+#define RCC_BDCR_RTCEN                         RCC_BDCR_RTCEN_Msk

+#define RCC_BDCR_BDRST_Pos                     (16U)

+#define RCC_BDCR_BDRST_Msk                     (0x1UL << RCC_BDCR_BDRST_Pos)   /*!< 0x00010000 */

+#define RCC_BDCR_BDRST                         RCC_BDCR_BDRST_Msk

+/********************  Bit definition for RCC_CSR register  *******************/

+#define RCC_CSR_LSION_Pos                      (0U)

+#define RCC_CSR_LSION_Msk                      (0x1UL << RCC_CSR_LSION_Pos)    /*!< 0x00000001 */

+#define RCC_CSR_LSION                          RCC_CSR_LSION_Msk

+#define RCC_CSR_LSIRDY_Pos                     (1U)

+#define RCC_CSR_LSIRDY_Msk                     (0x1UL << RCC_CSR_LSIRDY_Pos)   /*!< 0x00000002 */

+#define RCC_CSR_LSIRDY                         RCC_CSR_LSIRDY_Msk

+

+

+/********************  Bit definition for RCC_AHB3ENR register  **************/

+#define RCC_AHB3ENR_MDMAEN_Pos                 (0U)

+#define RCC_AHB3ENR_MDMAEN_Msk                 (0x1UL << RCC_AHB3ENR_MDMAEN_Pos)       /*!< 0x00000001 */

+#define RCC_AHB3ENR_MDMAEN                     RCC_AHB3ENR_MDMAEN_Msk

+#define RCC_AHB3ENR_DMA2DEN_Pos                (4U)

+#define RCC_AHB3ENR_DMA2DEN_Msk                (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos)      /*!< 0x00000010 */

+#define RCC_AHB3ENR_DMA2DEN                    RCC_AHB3ENR_DMA2DEN_Msk

+#define RCC_AHB3ENR_JPGDECEN_Pos               (5U)

+#define RCC_AHB3ENR_JPGDECEN_Msk               (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos)     /*!< 0x00000020 */

+#define RCC_AHB3ENR_JPGDECEN                   RCC_AHB3ENR_JPGDECEN_Msk

+#define RCC_AHB3ENR_FMCEN_Pos                  (12U)

+#define RCC_AHB3ENR_FMCEN_Msk                  (0x1UL << RCC_AHB3ENR_FMCEN_Pos)        /*!< 0x00001000 */

+#define RCC_AHB3ENR_FMCEN                      RCC_AHB3ENR_FMCEN_Msk

+#define RCC_AHB3ENR_QSPIEN_Pos                 (14U)

+#define RCC_AHB3ENR_QSPIEN_Msk                 (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)       /*!< 0x00004000 */

+#define RCC_AHB3ENR_QSPIEN                     RCC_AHB3ENR_QSPIEN_Msk

+#define RCC_AHB3ENR_SDMMC1EN_Pos               (16U)

+#define RCC_AHB3ENR_SDMMC1EN_Msk               (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos)     /*!< 0x00010000 */

+#define RCC_AHB3ENR_SDMMC1EN                   RCC_AHB3ENR_SDMMC1EN_Msk

+#define RCC_AHB3ENR_FLASHEN_Pos                (8U)

+#define RCC_AHB3ENR_FLASHEN_Msk                (0x1UL << RCC_AHB3ENR_FLASHEN_Pos)      /*!< 0x00000100 */

+#define RCC_AHB3ENR_FLASHEN                    RCC_AHB3ENR_FLASHEN_Msk

+#define RCC_AHB3ENR_DTCM1EN_Pos                (28U)

+#define RCC_AHB3ENR_DTCM1EN_Msk                (0x1UL << RCC_AHB3ENR_DTCM1EN_Pos)      /*!< 0x10000000 */

+#define RCC_AHB3ENR_DTCM1EN                    RCC_AHB3ENR_DTCM1EN_Msk

+#define RCC_AHB3ENR_DTCM2EN_Pos                (29U)

+#define RCC_AHB3ENR_DTCM2EN_Msk                (0x1UL << RCC_AHB3ENR_DTCM2EN_Pos)      /*!< 0x20000000 */

+#define RCC_AHB3ENR_DTCM2EN                    RCC_AHB3ENR_DTCM2EN_Msk

+#define RCC_AHB3ENR_ITCMEN_Pos                 (30U)

+#define RCC_AHB3ENR_ITCMEN_Msk                 (0x1UL << RCC_AHB3ENR_ITCMEN_Pos)       /*!< 0x40000000 */

+#define RCC_AHB3ENR_ITCMEN                     RCC_AHB3ENR_ITCMEN_Msk

+#define RCC_AHB3ENR_AXISRAMEN_Pos              (31U)

+#define RCC_AHB3ENR_AXISRAMEN_Msk              (0x1UL << RCC_AHB3ENR_AXISRAMEN_Pos)    /*!< 0x80000000 */

+#define RCC_AHB3ENR_AXISRAMEN                  RCC_AHB3ENR_AXISRAMEN_Msk

+

+/* Legacy define */

+#define RCC_AHB3ENR_D1SRAM1EN_Pos              RCC_AHB3ENR_AXISRAMEN_Pos

+#define RCC_AHB3ENR_D1SRAM1EN_Msk              RCC_AHB3ENR_AXISRAMEN_Msk

+#define RCC_AHB3ENR_D1SRAM1EN                  RCC_AHB3ENR_AXISRAMEN

+

+/********************  Bit definition for RCC_AHB1ENR register  ***************/

+#define RCC_AHB1ENR_DMA1EN_Pos                 (0U)

+#define RCC_AHB1ENR_DMA1EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)          /*!< 0x00000001 */

+#define RCC_AHB1ENR_DMA1EN                     RCC_AHB1ENR_DMA1EN_Msk

+#define RCC_AHB1ENR_DMA2EN_Pos                 (1U)

+#define RCC_AHB1ENR_DMA2EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)          /*!< 0x00000002 */

+#define RCC_AHB1ENR_DMA2EN                     RCC_AHB1ENR_DMA2EN_Msk

+#define RCC_AHB1ENR_ADC12EN_Pos                (5U)

+#define RCC_AHB1ENR_ADC12EN_Msk                (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)         /*!< 0x00000020 */

+#define RCC_AHB1ENR_ADC12EN                    RCC_AHB1ENR_ADC12EN_Msk

+#define RCC_AHB1ENR_ARTEN_Pos                  (14U)

+#define RCC_AHB1ENR_ARTEN_Msk                  (0x1UL << RCC_AHB1ENR_ARTEN_Pos)           /*!< 0x00004000 */

+#define RCC_AHB1ENR_ARTEN                      RCC_AHB1ENR_ARTEN_Msk

+#define RCC_AHB1ENR_ETH1MACEN_Pos              (15U)

+#define RCC_AHB1ENR_ETH1MACEN_Msk              (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos)       /*!< 0x00008000 */

+#define RCC_AHB1ENR_ETH1MACEN                  RCC_AHB1ENR_ETH1MACEN_Msk

+#define RCC_AHB1ENR_ETH1TXEN_Pos               (16U)

+#define RCC_AHB1ENR_ETH1TXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos)        /*!< 0x00010000 */

+#define RCC_AHB1ENR_ETH1TXEN                   RCC_AHB1ENR_ETH1TXEN_Msk

+#define RCC_AHB1ENR_ETH1RXEN_Pos               (17U)

+#define RCC_AHB1ENR_ETH1RXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos)        /*!< 0x00020000 */

+#define RCC_AHB1ENR_ETH1RXEN                   RCC_AHB1ENR_ETH1RXEN_Msk

+#define RCC_AHB1ENR_USB1OTGHSEN_Pos            (25U)

+#define RCC_AHB1ENR_USB1OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos)     /*!< 0x02000000 */

+#define RCC_AHB1ENR_USB1OTGHSEN                RCC_AHB1ENR_USB1OTGHSEN_Msk

+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos        (26U)

+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */

+#define RCC_AHB1ENR_USB1OTGHSULPIEN            RCC_AHB1ENR_USB1OTGHSULPIEN_Msk

+#define RCC_AHB1ENR_USB2OTGFSEN_Pos            (27U)

+#define RCC_AHB1ENR_USB2OTGFSEN_Msk            (0x1UL << RCC_AHB1ENR_USB2OTGFSEN_Pos)     /*!< 0x08000000 */

+#define RCC_AHB1ENR_USB2OTGFSEN                RCC_AHB1ENR_USB2OTGFSEN_Msk

+#define RCC_AHB1ENR_USB2OTGFSULPIEN_Pos        (28U)

+#define RCC_AHB1ENR_USB2OTGFSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB2OTGFSULPIEN_Pos) /*!< 0x10000000 */

+#define RCC_AHB1ENR_USB2OTGFSULPIEN            RCC_AHB1ENR_USB2OTGFSULPIEN_Msk

+

+/* Legacy define */

+#define RCC_AHB1ENR_USB2OTGHSEN_Pos            RCC_AHB1ENR_USB2OTGFSEN_Pos

+#define RCC_AHB1ENR_USB2OTGHSEN_Msk            RCC_AHB1ENR_USB2OTGFSEN_Msk

+#define RCC_AHB1ENR_USB2OTGHSEN                RCC_AHB1ENR_USB2OTGFSEN

+#define RCC_AHB1ENR_USB2OTGHSULPIEN_Pos        RCC_AHB1ENR_USB2OTGFSULPIEN_Pos

+#define RCC_AHB1ENR_USB2OTGHSULPIEN_Msk        RCC_AHB1ENR_USB2OTGFSULPIEN_Msk

+#define RCC_AHB1ENR_USB2OTGHSULPIEN            RCC_AHB1ENR_USB2OTGFSULPIEN

+

+

+/********************  Bit definition for RCC_AHB2ENR register  ***************/

+#define RCC_AHB2ENR_DCMIEN_Pos                 (0U)

+#define RCC_AHB2ENR_DCMIEN_Msk                 (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)          /*!< 0x00000001 */

+#define RCC_AHB2ENR_DCMIEN                     RCC_AHB2ENR_DCMIEN_Msk

+#define RCC_AHB2ENR_CRYPEN_Pos                 (4U)

+#define RCC_AHB2ENR_CRYPEN_Msk                 (0x1UL << RCC_AHB2ENR_CRYPEN_Pos)          /*!< 0x00000010 */

+#define RCC_AHB2ENR_CRYPEN                     RCC_AHB2ENR_CRYPEN_Msk

+#define RCC_AHB2ENR_HASHEN_Pos                 (5U)

+#define RCC_AHB2ENR_HASHEN_Msk                 (0x1UL << RCC_AHB2ENR_HASHEN_Pos)          /*!< 0x00000020 */

+#define RCC_AHB2ENR_HASHEN                     RCC_AHB2ENR_HASHEN_Msk

+#define RCC_AHB2ENR_RNGEN_Pos                  (6U)

+#define RCC_AHB2ENR_RNGEN_Msk                  (0x1UL << RCC_AHB2ENR_RNGEN_Pos)           /*!< 0x00000040 */

+#define RCC_AHB2ENR_RNGEN                      RCC_AHB2ENR_RNGEN_Msk

+#define RCC_AHB2ENR_SDMMC2EN_Pos               (9U)

+#define RCC_AHB2ENR_SDMMC2EN_Msk               (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)        /*!< 0x00000200 */

+#define RCC_AHB2ENR_SDMMC2EN                   RCC_AHB2ENR_SDMMC2EN_Msk

+#define RCC_AHB2ENR_SRAM1EN_Pos                (29U)

+#define RCC_AHB2ENR_SRAM1EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos)       /*!< 0x20000000 */

+#define RCC_AHB2ENR_SRAM1EN                    RCC_AHB2ENR_SRAM1EN_Msk

+#define RCC_AHB2ENR_SRAM2EN_Pos                (30U)

+#define RCC_AHB2ENR_SRAM2EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos)       /*!< 0x40000000 */

+#define RCC_AHB2ENR_SRAM2EN                    RCC_AHB2ENR_SRAM2EN_Msk

+#define RCC_AHB2ENR_SRAM3EN_Pos                (31U)

+#define RCC_AHB2ENR_SRAM3EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM3EN_Pos)       /*!< 0x80000000 */

+#define RCC_AHB2ENR_SRAM3EN                    RCC_AHB2ENR_SRAM3EN_Msk

+

+/* Legacy define */

+#define RCC_AHB2ENR_D2SRAM1EN_Pos              RCC_AHB2ENR_SRAM1EN_Pos

+#define RCC_AHB2ENR_D2SRAM1EN_Msk              RCC_AHB2ENR_SRAM1EN_Msk

+#define RCC_AHB2ENR_D2SRAM1EN                  RCC_AHB2ENR_SRAM1EN

+#define RCC_AHB2ENR_D2SRAM2EN_Pos              RCC_AHB2ENR_SRAM2EN_Pos

+#define RCC_AHB2ENR_D2SRAM2EN_Msk              RCC_AHB2ENR_SRAM2EN_Msk

+#define RCC_AHB2ENR_D2SRAM2EN                  RCC_AHB2ENR_SRAM2EN

+#define RCC_AHB2ENR_D2SRAM3EN_Pos              RCC_AHB2ENR_SRAM3EN_Pos

+#define RCC_AHB2ENR_D2SRAM3EN_Msk              RCC_AHB2ENR_SRAM3EN_Msk

+#define RCC_AHB2ENR_D2SRAM3EN                  RCC_AHB2ENR_SRAM3EN

+

+/********************  Bit definition for RCC_AHB4ENR register  ******************/

+#define RCC_AHB4ENR_GPIOAEN_Pos                (0U)

+#define RCC_AHB4ENR_GPIOAEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)         /*!< 0x00000001 */

+#define RCC_AHB4ENR_GPIOAEN                    RCC_AHB4ENR_GPIOAEN_Msk

+#define RCC_AHB4ENR_GPIOBEN_Pos                (1U)

+#define RCC_AHB4ENR_GPIOBEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)         /*!< 0x00000002 */

+#define RCC_AHB4ENR_GPIOBEN                    RCC_AHB4ENR_GPIOBEN_Msk

+#define RCC_AHB4ENR_GPIOCEN_Pos                (2U)

+#define RCC_AHB4ENR_GPIOCEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)         /*!< 0x00000004 */

+#define RCC_AHB4ENR_GPIOCEN                    RCC_AHB4ENR_GPIOCEN_Msk

+#define RCC_AHB4ENR_GPIODEN_Pos                (3U)

+#define RCC_AHB4ENR_GPIODEN_Msk                (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)         /*!< 0x00000008 */

+#define RCC_AHB4ENR_GPIODEN                    RCC_AHB4ENR_GPIODEN_Msk

+#define RCC_AHB4ENR_GPIOEEN_Pos                (4U)

+#define RCC_AHB4ENR_GPIOEEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)         /*!< 0x00000010 */

+#define RCC_AHB4ENR_GPIOEEN                    RCC_AHB4ENR_GPIOEEN_Msk

+#define RCC_AHB4ENR_GPIOFEN_Pos                (5U)

+#define RCC_AHB4ENR_GPIOFEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)         /*!< 0x00000020 */

+#define RCC_AHB4ENR_GPIOFEN                    RCC_AHB4ENR_GPIOFEN_Msk

+#define RCC_AHB4ENR_GPIOGEN_Pos                (6U)

+#define RCC_AHB4ENR_GPIOGEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)         /*!< 0x00000040 */

+#define RCC_AHB4ENR_GPIOGEN                    RCC_AHB4ENR_GPIOGEN_Msk

+#define RCC_AHB4ENR_GPIOHEN_Pos                (7U)

+#define RCC_AHB4ENR_GPIOHEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)         /*!< 0x00000080 */

+#define RCC_AHB4ENR_GPIOHEN                    RCC_AHB4ENR_GPIOHEN_Msk

+#define RCC_AHB4ENR_GPIOIEN_Pos                (8U)

+#define RCC_AHB4ENR_GPIOIEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos)         /*!< 0x00000100 */

+#define RCC_AHB4ENR_GPIOIEN                    RCC_AHB4ENR_GPIOIEN_Msk

+#define RCC_AHB4ENR_GPIOJEN_Pos                (9U)

+#define RCC_AHB4ENR_GPIOJEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos)         /*!< 0x00000200 */

+#define RCC_AHB4ENR_GPIOJEN                    RCC_AHB4ENR_GPIOJEN_Msk

+#define RCC_AHB4ENR_GPIOKEN_Pos                (10U)

+#define RCC_AHB4ENR_GPIOKEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos)         /*!< 0x00000400 */

+#define RCC_AHB4ENR_GPIOKEN                    RCC_AHB4ENR_GPIOKEN_Msk

+#define RCC_AHB4ENR_CRCEN_Pos                  (19U)

+#define RCC_AHB4ENR_CRCEN_Msk                  (0x1UL << RCC_AHB4ENR_CRCEN_Pos)           /*!< 0x00080000 */

+#define RCC_AHB4ENR_CRCEN                      RCC_AHB4ENR_CRCEN_Msk

+#define RCC_AHB4ENR_BDMAEN_Pos                 (21U)

+#define RCC_AHB4ENR_BDMAEN_Msk                 (0x1UL << RCC_AHB4ENR_BDMAEN_Pos)          /*!< 0x00200000 */

+#define RCC_AHB4ENR_BDMAEN                     RCC_AHB4ENR_BDMAEN_Msk

+#define RCC_AHB4ENR_ADC3EN_Pos                 (24U)

+#define RCC_AHB4ENR_ADC3EN_Msk                 (0x1UL << RCC_AHB4ENR_ADC3EN_Pos)          /*!< 0x01000000 */

+#define RCC_AHB4ENR_ADC3EN                     RCC_AHB4ENR_ADC3EN_Msk

+#define RCC_AHB4ENR_HSEMEN_Pos                 (25U)

+#define RCC_AHB4ENR_HSEMEN_Msk                 (0x1UL << RCC_AHB4ENR_HSEMEN_Pos)          /*!< 0x02000000 */

+#define RCC_AHB4ENR_HSEMEN                     RCC_AHB4ENR_HSEMEN_Msk

+#define RCC_AHB4ENR_BKPRAMEN_Pos               (28U)

+#define RCC_AHB4ENR_BKPRAMEN_Msk               (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)        /*!< 0x10000000 */

+#define RCC_AHB4ENR_BKPRAMEN                   RCC_AHB4ENR_BKPRAMEN_Msk

+

+/********************  Bit definition for RCC_APB3ENR register  ******************/

+#define RCC_APB3ENR_LTDCEN_Pos                 (3U)

+#define RCC_APB3ENR_LTDCEN_Msk                 (0x1UL << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */

+#define RCC_APB3ENR_LTDCEN                     RCC_APB3ENR_LTDCEN_Msk

+#define RCC_APB3ENR_WWDG1EN_Pos                (6U)

+#define RCC_APB3ENR_WWDG1EN_Msk                (0x1UL << RCC_APB3ENR_WWDG1EN_Pos) /*!< 0x00000040 */

+#define RCC_APB3ENR_WWDG1EN                    RCC_APB3ENR_WWDG1EN_Msk

+

+/********************  Bit definition for RCC_APB1LENR register  ******************/

+

+#define RCC_APB1LENR_TIM2EN_Pos                (0U)

+#define RCC_APB1LENR_TIM2EN_Msk                (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */

+#define RCC_APB1LENR_TIM2EN                    RCC_APB1LENR_TIM2EN_Msk

+#define RCC_APB1LENR_TIM3EN_Pos                (1U)

+#define RCC_APB1LENR_TIM3EN_Msk                (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */

+#define RCC_APB1LENR_TIM3EN                    RCC_APB1LENR_TIM3EN_Msk

+#define RCC_APB1LENR_TIM4EN_Pos                (2U)

+#define RCC_APB1LENR_TIM4EN_Msk                (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */

+#define RCC_APB1LENR_TIM4EN                    RCC_APB1LENR_TIM4EN_Msk

+#define RCC_APB1LENR_TIM5EN_Pos                (3U)

+#define RCC_APB1LENR_TIM5EN_Msk                (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */

+#define RCC_APB1LENR_TIM5EN                    RCC_APB1LENR_TIM5EN_Msk

+#define RCC_APB1LENR_TIM6EN_Pos                (4U)

+#define RCC_APB1LENR_TIM6EN_Msk                (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */

+#define RCC_APB1LENR_TIM6EN                    RCC_APB1LENR_TIM6EN_Msk

+#define RCC_APB1LENR_TIM7EN_Pos                (5U)

+#define RCC_APB1LENR_TIM7EN_Msk                (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */

+#define RCC_APB1LENR_TIM7EN                    RCC_APB1LENR_TIM7EN_Msk

+#define RCC_APB1LENR_TIM12EN_Pos               (6U)

+#define RCC_APB1LENR_TIM12EN_Msk               (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */

+#define RCC_APB1LENR_TIM12EN                   RCC_APB1LENR_TIM12EN_Msk

+#define RCC_APB1LENR_TIM13EN_Pos               (7U)

+#define RCC_APB1LENR_TIM13EN_Msk               (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */

+#define RCC_APB1LENR_TIM13EN                   RCC_APB1LENR_TIM13EN_Msk

+#define RCC_APB1LENR_TIM14EN_Pos               (8U)

+#define RCC_APB1LENR_TIM14EN_Msk               (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */

+#define RCC_APB1LENR_TIM14EN                   RCC_APB1LENR_TIM14EN_Msk

+#define RCC_APB1LENR_LPTIM1EN_Pos              (9U)

+#define RCC_APB1LENR_LPTIM1EN_Msk              (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */

+#define RCC_APB1LENR_LPTIM1EN                  RCC_APB1LENR_LPTIM1EN_Msk

+

+#define RCC_APB1LENR_WWDG2EN_Pos               (11U)

+#define RCC_APB1LENR_WWDG2EN_Msk               (0x1UL << RCC_APB1LENR_WWDG2EN_Pos) /*!< 0x00000800 */

+#define RCC_APB1LENR_WWDG2EN                   RCC_APB1LENR_WWDG2EN_Msk

+

+#define RCC_APB1LENR_SPI2EN_Pos                (14U)

+#define RCC_APB1LENR_SPI2EN_Msk                (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */

+#define RCC_APB1LENR_SPI2EN                    RCC_APB1LENR_SPI2EN_Msk

+#define RCC_APB1LENR_SPI3EN_Pos                (15U)

+#define RCC_APB1LENR_SPI3EN_Msk                (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */

+#define RCC_APB1LENR_SPI3EN                    RCC_APB1LENR_SPI3EN_Msk

+#define RCC_APB1LENR_SPDIFRXEN_Pos             (16U)

+#define RCC_APB1LENR_SPDIFRXEN_Msk             (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */

+#define RCC_APB1LENR_SPDIFRXEN                 RCC_APB1LENR_SPDIFRXEN_Msk

+#define RCC_APB1LENR_USART2EN_Pos              (17U)

+#define RCC_APB1LENR_USART2EN_Msk              (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */

+#define RCC_APB1LENR_USART2EN                  RCC_APB1LENR_USART2EN_Msk

+#define RCC_APB1LENR_USART3EN_Pos              (18U)

+#define RCC_APB1LENR_USART3EN_Msk              (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */

+#define RCC_APB1LENR_USART3EN                  RCC_APB1LENR_USART3EN_Msk

+#define RCC_APB1LENR_UART4EN_Pos               (19U)

+#define RCC_APB1LENR_UART4EN_Msk               (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */

+#define RCC_APB1LENR_UART4EN                   RCC_APB1LENR_UART4EN_Msk

+#define RCC_APB1LENR_UART5EN_Pos               (20U)

+#define RCC_APB1LENR_UART5EN_Msk               (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */

+#define RCC_APB1LENR_UART5EN                   RCC_APB1LENR_UART5EN_Msk

+#define RCC_APB1LENR_I2C1EN_Pos                (21U)

+#define RCC_APB1LENR_I2C1EN_Msk                (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */

+#define RCC_APB1LENR_I2C1EN                    RCC_APB1LENR_I2C1EN_Msk

+#define RCC_APB1LENR_I2C2EN_Pos                (22U)

+#define RCC_APB1LENR_I2C2EN_Msk                (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */

+#define RCC_APB1LENR_I2C2EN                    RCC_APB1LENR_I2C2EN_Msk

+#define RCC_APB1LENR_I2C3EN_Pos                (23U)

+#define RCC_APB1LENR_I2C3EN_Msk                (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */

+#define RCC_APB1LENR_I2C3EN                    RCC_APB1LENR_I2C3EN_Msk

+#define RCC_APB1LENR_CECEN_Pos                 (27U)

+#define RCC_APB1LENR_CECEN_Msk                 (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */

+#define RCC_APB1LENR_CECEN                     RCC_APB1LENR_CECEN_Msk

+#define RCC_APB1LENR_DAC12EN_Pos               (29U)

+#define RCC_APB1LENR_DAC12EN_Msk               (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */

+#define RCC_APB1LENR_DAC12EN                   RCC_APB1LENR_DAC12EN_Msk

+#define RCC_APB1LENR_UART7EN_Pos               (30U)

+#define RCC_APB1LENR_UART7EN_Msk               (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */

+#define RCC_APB1LENR_UART7EN                   RCC_APB1LENR_UART7EN_Msk

+#define RCC_APB1LENR_UART8EN_Pos               (31U)

+#define RCC_APB1LENR_UART8EN_Msk               (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */

+#define RCC_APB1LENR_UART8EN                   RCC_APB1LENR_UART8EN_Msk

+

+/* Legacy define */

+#define RCC_APB1LENR_HDMICECEN_Pos             RCC_APB1LENR_CECEN_Pos

+#define RCC_APB1LENR_HDMICECEN_Msk             RCC_APB1LENR_CECEN_Msk

+#define RCC_APB1LENR_HDMICECEN                 RCC_APB1LENR_CECEN

+/********************  Bit definition for RCC_APB1HENR register  ******************/

+#define RCC_APB1HENR_CRSEN_Pos                 (1U)

+#define RCC_APB1HENR_CRSEN_Msk                 (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1HENR_CRSEN                     RCC_APB1HENR_CRSEN_Msk

+#define RCC_APB1HENR_SWPMIEN_Pos               (2U)

+#define RCC_APB1HENR_SWPMIEN_Msk               (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1HENR_SWPMIEN                   RCC_APB1HENR_SWPMIEN_Msk

+#define RCC_APB1HENR_OPAMPEN_Pos               (4U)

+#define RCC_APB1HENR_OPAMPEN_Msk               (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1HENR_OPAMPEN                   RCC_APB1HENR_OPAMPEN_Msk

+#define RCC_APB1HENR_MDIOSEN_Pos               (5U)

+#define RCC_APB1HENR_MDIOSEN_Msk               (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1HENR_MDIOSEN                   RCC_APB1HENR_MDIOSEN_Msk

+#define RCC_APB1HENR_FDCANEN_Pos               (8U)

+#define RCC_APB1HENR_FDCANEN_Msk               (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1HENR_FDCANEN                   RCC_APB1HENR_FDCANEN_Msk

+

+/********************  Bit definition for RCC_APB2ENR register  ******************/

+#define RCC_APB2ENR_TIM1EN_Pos                 (0U)

+#define RCC_APB2ENR_TIM1EN_Msk                 (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */

+#define RCC_APB2ENR_TIM1EN                     RCC_APB2ENR_TIM1EN_Msk

+#define RCC_APB2ENR_TIM8EN_Pos                 (1U)

+#define RCC_APB2ENR_TIM8EN_Msk                 (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */

+#define RCC_APB2ENR_TIM8EN                     RCC_APB2ENR_TIM8EN_Msk

+#define RCC_APB2ENR_USART1EN_Pos               (4U)

+#define RCC_APB2ENR_USART1EN_Msk               (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */

+#define RCC_APB2ENR_USART1EN                   RCC_APB2ENR_USART1EN_Msk

+#define RCC_APB2ENR_USART6EN_Pos               (5U)

+#define RCC_APB2ENR_USART6EN_Msk               (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */

+#define RCC_APB2ENR_USART6EN                   RCC_APB2ENR_USART6EN_Msk

+#define RCC_APB2ENR_SPI1EN_Pos                 (12U)

+#define RCC_APB2ENR_SPI1EN_Msk                 (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */

+#define RCC_APB2ENR_SPI1EN                     RCC_APB2ENR_SPI1EN_Msk

+#define RCC_APB2ENR_SPI4EN_Pos                 (13U)

+#define RCC_APB2ENR_SPI4EN_Msk                 (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */

+#define RCC_APB2ENR_SPI4EN                     RCC_APB2ENR_SPI4EN_Msk

+#define RCC_APB2ENR_TIM15EN_Pos                (16U)

+#define RCC_APB2ENR_TIM15EN_Msk                (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */

+#define RCC_APB2ENR_TIM15EN                    RCC_APB2ENR_TIM15EN_Msk

+#define RCC_APB2ENR_TIM16EN_Pos                (17U)

+#define RCC_APB2ENR_TIM16EN_Msk                (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */

+#define RCC_APB2ENR_TIM16EN                    RCC_APB2ENR_TIM16EN_Msk

+#define RCC_APB2ENR_TIM17EN_Pos                (18U)

+#define RCC_APB2ENR_TIM17EN_Msk                (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */

+#define RCC_APB2ENR_TIM17EN                    RCC_APB2ENR_TIM17EN_Msk

+#define RCC_APB2ENR_SPI5EN_Pos                 (20U)

+#define RCC_APB2ENR_SPI5EN_Msk                 (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */

+#define RCC_APB2ENR_SPI5EN                     RCC_APB2ENR_SPI5EN_Msk

+#define RCC_APB2ENR_SAI1EN_Pos                 (22U)

+#define RCC_APB2ENR_SAI1EN_Msk                 (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */

+#define RCC_APB2ENR_SAI1EN                     RCC_APB2ENR_SAI1EN_Msk

+#define RCC_APB2ENR_SAI2EN_Pos                 (23U)

+#define RCC_APB2ENR_SAI2EN_Msk                 (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */

+#define RCC_APB2ENR_SAI2EN                     RCC_APB2ENR_SAI2EN_Msk

+#define RCC_APB2ENR_SAI3EN_Pos                 (24U)

+#define RCC_APB2ENR_SAI3EN_Msk                 (0x1UL << RCC_APB2ENR_SAI3EN_Pos) /*!< 0x01000000 */

+#define RCC_APB2ENR_SAI3EN                     RCC_APB2ENR_SAI3EN_Msk

+#define RCC_APB2ENR_DFSDM1EN_Pos               (28U)

+#define RCC_APB2ENR_DFSDM1EN_Msk               (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x10000000 */

+#define RCC_APB2ENR_DFSDM1EN                   RCC_APB2ENR_DFSDM1EN_Msk

+#define RCC_APB2ENR_HRTIMEN_Pos                (29U)

+#define RCC_APB2ENR_HRTIMEN_Msk                (0x1UL << RCC_APB2ENR_HRTIMEN_Pos) /*!< 0x20000000 */

+#define RCC_APB2ENR_HRTIMEN                    RCC_APB2ENR_HRTIMEN_Msk

+

+/********************  Bit definition for RCC_APB4ENR register  ******************/

+#define RCC_APB4ENR_SYSCFGEN_Pos               (1U)

+#define RCC_APB4ENR_SYSCFGEN_Msk               (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */

+#define RCC_APB4ENR_SYSCFGEN                   RCC_APB4ENR_SYSCFGEN_Msk

+#define RCC_APB4ENR_LPUART1EN_Pos              (3U)

+#define RCC_APB4ENR_LPUART1EN_Msk              (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */

+#define RCC_APB4ENR_LPUART1EN                  RCC_APB4ENR_LPUART1EN_Msk

+#define RCC_APB4ENR_SPI6EN_Pos                 (5U)

+#define RCC_APB4ENR_SPI6EN_Msk                 (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */

+#define RCC_APB4ENR_SPI6EN                     RCC_APB4ENR_SPI6EN_Msk

+#define RCC_APB4ENR_I2C4EN_Pos                 (7U)

+#define RCC_APB4ENR_I2C4EN_Msk                 (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */

+#define RCC_APB4ENR_I2C4EN                     RCC_APB4ENR_I2C4EN_Msk

+#define RCC_APB4ENR_LPTIM2EN_Pos               (9U)

+#define RCC_APB4ENR_LPTIM2EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */

+#define RCC_APB4ENR_LPTIM2EN                   RCC_APB4ENR_LPTIM2EN_Msk

+#define RCC_APB4ENR_LPTIM3EN_Pos               (10U)

+#define RCC_APB4ENR_LPTIM3EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */

+#define RCC_APB4ENR_LPTIM3EN                   RCC_APB4ENR_LPTIM3EN_Msk

+#define RCC_APB4ENR_LPTIM4EN_Pos               (11U)

+#define RCC_APB4ENR_LPTIM4EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos) /*!< 0x00000800 */

+#define RCC_APB4ENR_LPTIM4EN                   RCC_APB4ENR_LPTIM4EN_Msk

+#define RCC_APB4ENR_LPTIM5EN_Pos               (12U)

+#define RCC_APB4ENR_LPTIM5EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos) /*!< 0x00001000 */

+#define RCC_APB4ENR_LPTIM5EN                   RCC_APB4ENR_LPTIM5EN_Msk

+#define RCC_APB4ENR_COMP12EN_Pos               (14U)

+#define RCC_APB4ENR_COMP12EN_Msk               (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */

+#define RCC_APB4ENR_COMP12EN                   RCC_APB4ENR_COMP12EN_Msk

+#define RCC_APB4ENR_VREFEN_Pos                 (15U)

+#define RCC_APB4ENR_VREFEN_Msk                 (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */

+#define RCC_APB4ENR_VREFEN                     RCC_APB4ENR_VREFEN_Msk

+#define RCC_APB4ENR_RTCAPBEN_Pos               (16U)

+#define RCC_APB4ENR_RTCAPBEN_Msk               (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */

+#define RCC_APB4ENR_RTCAPBEN                   RCC_APB4ENR_RTCAPBEN_Msk

+#define RCC_APB4ENR_SAI4EN_Pos                 (21U)

+#define RCC_APB4ENR_SAI4EN_Msk                 (0x1UL << RCC_APB4ENR_SAI4EN_Pos) /*!< 0x00200000 */

+#define RCC_APB4ENR_SAI4EN                     RCC_APB4ENR_SAI4EN_Msk

+

+

+/********************  Bit definition for RCC_AHB3RSTR register  ***************/

+#define RCC_AHB3RSTR_MDMARST_Pos               (0U)

+#define RCC_AHB3RSTR_MDMARST_Msk               (0x1UL << RCC_AHB3RSTR_MDMARST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB3RSTR_MDMARST                   RCC_AHB3RSTR_MDMARST_Msk

+#define RCC_AHB3RSTR_DMA2DRST_Pos              (4U)

+#define RCC_AHB3RSTR_DMA2DRST_Msk              (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos)     /*!< 0x00000010 */

+#define RCC_AHB3RSTR_DMA2DRST                  RCC_AHB3RSTR_DMA2DRST_Msk

+#define RCC_AHB3RSTR_JPGDECRST_Pos             (5U)

+#define RCC_AHB3RSTR_JPGDECRST_Msk             (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos)    /*!< 0x00000020 */

+#define RCC_AHB3RSTR_JPGDECRST                 RCC_AHB3RSTR_JPGDECRST_Msk

+#define RCC_AHB3RSTR_FMCRST_Pos                (12U)

+#define RCC_AHB3RSTR_FMCRST_Msk                (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)      /*!< 0x00001000 */

+#define RCC_AHB3RSTR_FMCRST                    RCC_AHB3RSTR_FMCRST_Msk

+#define RCC_AHB3RSTR_QSPIRST_Pos               (14U)

+#define RCC_AHB3RSTR_QSPIRST_Msk               (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)     /*!< 0x00004000 */

+#define RCC_AHB3RSTR_QSPIRST                   RCC_AHB3RSTR_QSPIRST_Msk

+#define RCC_AHB3RSTR_SDMMC1RST_Pos             (16U)

+#define RCC_AHB3RSTR_SDMMC1RST_Msk             (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos)   /*!< 0x00010000 */

+#define RCC_AHB3RSTR_SDMMC1RST                 RCC_AHB3RSTR_SDMMC1RST_Msk

+

+

+/********************  Bit definition for RCC_AHB1RSTR register  ***************/

+#define RCC_AHB1RSTR_DMA1RST_Pos               (0U)

+#define RCC_AHB1RSTR_DMA1RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB1RSTR_DMA1RST                   RCC_AHB1RSTR_DMA1RST_Msk

+#define RCC_AHB1RSTR_DMA2RST_Pos               (1U)

+#define RCC_AHB1RSTR_DMA2RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)      /*!< 0x00000002 */

+#define RCC_AHB1RSTR_DMA2RST                   RCC_AHB1RSTR_DMA2RST_Msk

+#define RCC_AHB1RSTR_ADC12RST_Pos              (5U)

+#define RCC_AHB1RSTR_ADC12RST_Msk              (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)     /*!< 0x00000020 */

+#define RCC_AHB1RSTR_ADC12RST                  RCC_AHB1RSTR_ADC12RST_Msk

+#define RCC_AHB1RSTR_ARTRST_Pos                (14U)

+#define RCC_AHB1RSTR_ARTRST_Msk                (0x1UL << RCC_AHB1RSTR_ARTRST_Pos)       /*!< 0x00004000 */

+#define RCC_AHB1RSTR_ARTRST                    RCC_AHB1RSTR_ARTRST_Msk

+#define RCC_AHB1RSTR_ETH1MACRST_Pos            (15U)

+#define RCC_AHB1RSTR_ETH1MACRST_Msk            (0x1UL << RCC_AHB1RSTR_ETH1MACRST_Pos)   /*!< 0x00008000 */

+#define RCC_AHB1RSTR_ETH1MACRST                RCC_AHB1RSTR_ETH1MACRST_Msk

+#define RCC_AHB1RSTR_USB1OTGHSRST_Pos          (25U)

+#define RCC_AHB1RSTR_USB1OTGHSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */

+#define RCC_AHB1RSTR_USB1OTGHSRST              RCC_AHB1RSTR_USB1OTGHSRST_Msk

+#define RCC_AHB1RSTR_USB2OTGFSRST_Pos          (27U)

+#define RCC_AHB1RSTR_USB2OTGFSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB2OTGFSRST_Pos) /*!< 0x08000000 */

+#define RCC_AHB1RSTR_USB2OTGFSRST              RCC_AHB1RSTR_USB2OTGFSRST_Msk

+

+/* Legacy define */

+#define RCC_AHB1RSTR_USB2OTGHSRST_Pos          RCC_AHB1RSTR_USB2OTGFSRST_Pos

+#define RCC_AHB1RSTR_USB2OTGHSRST_Msk          RCC_AHB1RSTR_USB2OTGFSRST_Msk

+#define RCC_AHB1RSTR_USB2OTGHSRST              RCC_AHB1RSTR_USB2OTGFSRST

+

+/********************  Bit definition for RCC_AHB2RSTR register  ***************/

+#define RCC_AHB2RSTR_DCMIRST_Pos               (0U)

+#define RCC_AHB2RSTR_DCMIRST_Msk               (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)       /*!< 0x00000001 */

+#define RCC_AHB2RSTR_DCMIRST                   RCC_AHB2RSTR_DCMIRST_Msk

+#define RCC_AHB2RSTR_CRYPRST_Pos               (4U)

+#define RCC_AHB2RSTR_CRYPRST_Msk               (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos)       /*!< 0x00000010 */

+#define RCC_AHB2RSTR_CRYPRST                   RCC_AHB2RSTR_CRYPRST_Msk

+#define RCC_AHB2RSTR_HASHRST_Pos               (5U)

+#define RCC_AHB2RSTR_HASHRST_Msk               (0x1UL << RCC_AHB2RSTR_HASHRST_Pos)       /*!< 0x00000020 */

+#define RCC_AHB2RSTR_HASHRST                   RCC_AHB2RSTR_HASHRST_Msk

+#define RCC_AHB2RSTR_RNGRST_Pos                (6U)

+#define RCC_AHB2RSTR_RNGRST_Msk                (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)        /*!< 0x00000040 */

+#define RCC_AHB2RSTR_RNGRST                    RCC_AHB2RSTR_RNGRST_Msk

+#define RCC_AHB2RSTR_SDMMC2RST_Pos             (9U)

+#define RCC_AHB2RSTR_SDMMC2RST_Msk             (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)     /*!< 0x00000200 */

+#define RCC_AHB2RSTR_SDMMC2RST                 RCC_AHB2RSTR_SDMMC2RST_Msk

+

+/********************  Bit definition for RCC_AHB4RSTR register  ******************/

+#define RCC_AHB4RSTR_GPIOARST_Pos              (0U)

+#define RCC_AHB4RSTR_GPIOARST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB4RSTR_GPIOARST                  RCC_AHB4RSTR_GPIOARST_Msk

+#define RCC_AHB4RSTR_GPIOBRST_Pos              (1U)

+#define RCC_AHB4RSTR_GPIOBRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)      /*!< 0x00000002 */

+#define RCC_AHB4RSTR_GPIOBRST                  RCC_AHB4RSTR_GPIOBRST_Msk

+#define RCC_AHB4RSTR_GPIOCRST_Pos              (2U)

+#define RCC_AHB4RSTR_GPIOCRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)      /*!< 0x00000004 */

+#define RCC_AHB4RSTR_GPIOCRST                  RCC_AHB4RSTR_GPIOCRST_Msk

+#define RCC_AHB4RSTR_GPIODRST_Pos              (3U)

+#define RCC_AHB4RSTR_GPIODRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)      /*!< 0x00000008 */

+#define RCC_AHB4RSTR_GPIODRST                  RCC_AHB4RSTR_GPIODRST_Msk

+#define RCC_AHB4RSTR_GPIOERST_Pos              (4U)

+#define RCC_AHB4RSTR_GPIOERST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)      /*!< 0x00000010 */

+#define RCC_AHB4RSTR_GPIOERST                  RCC_AHB4RSTR_GPIOERST_Msk

+#define RCC_AHB4RSTR_GPIOFRST_Pos              (5U)

+#define RCC_AHB4RSTR_GPIOFRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)       /*!< 0x00000020 */

+#define RCC_AHB4RSTR_GPIOFRST                  RCC_AHB4RSTR_GPIOFRST_Msk

+#define RCC_AHB4RSTR_GPIOGRST_Pos              (6U)

+#define RCC_AHB4RSTR_GPIOGRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)       /*!< 0x00000040 */

+#define RCC_AHB4RSTR_GPIOGRST                  RCC_AHB4RSTR_GPIOGRST_Msk

+#define RCC_AHB4RSTR_GPIOHRST_Pos              (7U)

+#define RCC_AHB4RSTR_GPIOHRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)       /*!< 0x00000080 */

+#define RCC_AHB4RSTR_GPIOHRST                  RCC_AHB4RSTR_GPIOHRST_Msk

+#define RCC_AHB4RSTR_GPIOIRST_Pos              (8U)

+#define RCC_AHB4RSTR_GPIOIRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos)       /*!< 0x00000100 */

+#define RCC_AHB4RSTR_GPIOIRST                  RCC_AHB4RSTR_GPIOIRST_Msk

+#define RCC_AHB4RSTR_GPIOJRST_Pos              (9U)

+#define RCC_AHB4RSTR_GPIOJRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos)       /*!< 0x00000200 */

+#define RCC_AHB4RSTR_GPIOJRST                  RCC_AHB4RSTR_GPIOJRST_Msk

+#define RCC_AHB4RSTR_GPIOKRST_Pos              (10U)

+#define RCC_AHB4RSTR_GPIOKRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos)       /*!< 0x00000400 */

+#define RCC_AHB4RSTR_GPIOKRST                  RCC_AHB4RSTR_GPIOKRST_Msk

+#define RCC_AHB4RSTR_CRCRST_Pos                (19U)

+#define RCC_AHB4RSTR_CRCRST_Msk                (0x1UL << RCC_AHB4RSTR_CRCRST_Pos)         /*!< 0x00080000 */

+#define RCC_AHB4RSTR_CRCRST                    RCC_AHB4RSTR_CRCRST_Msk

+#define RCC_AHB4RSTR_BDMARST_Pos               (21U)

+#define RCC_AHB4RSTR_BDMARST_Msk               (0x1UL << RCC_AHB4RSTR_BDMARST_Pos)        /*!< 0x00200000 */

+#define RCC_AHB4RSTR_BDMARST                   RCC_AHB4RSTR_BDMARST_Msk

+#define RCC_AHB4RSTR_ADC3RST_Pos               (24U)

+#define RCC_AHB4RSTR_ADC3RST_Msk               (0x1UL << RCC_AHB4RSTR_ADC3RST_Pos)        /*!< 0x01000000 */

+#define RCC_AHB4RSTR_ADC3RST                   RCC_AHB4RSTR_ADC3RST_Msk

+#define RCC_AHB4RSTR_HSEMRST_Pos               (25U)

+#define RCC_AHB4RSTR_HSEMRST_Msk               (0x1UL << RCC_AHB4RSTR_HSEMRST_Pos)        /*!< 0x02000000 */

+#define RCC_AHB4RSTR_HSEMRST                   RCC_AHB4RSTR_HSEMRST_Msk

+

+

+/********************  Bit definition for RCC_APB3RSTR register  ******************/

+#define RCC_APB3RSTR_LTDCRST_Pos               (3U)

+#define RCC_APB3RSTR_LTDCRST_Msk               (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */

+#define RCC_APB3RSTR_LTDCRST                   RCC_APB3RSTR_LTDCRST_Msk

+

+/********************  Bit definition for RCC_APB1LRSTR register  ******************/

+

+#define RCC_APB1LRSTR_TIM2RST_Pos              (0U)

+#define RCC_APB1LRSTR_TIM2RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */

+#define RCC_APB1LRSTR_TIM2RST                  RCC_APB1LRSTR_TIM2RST_Msk

+#define RCC_APB1LRSTR_TIM3RST_Pos              (1U)

+#define RCC_APB1LRSTR_TIM3RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */

+#define RCC_APB1LRSTR_TIM3RST                  RCC_APB1LRSTR_TIM3RST_Msk

+#define RCC_APB1LRSTR_TIM4RST_Pos              (2U)

+#define RCC_APB1LRSTR_TIM4RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */

+#define RCC_APB1LRSTR_TIM4RST                  RCC_APB1LRSTR_TIM4RST_Msk

+#define RCC_APB1LRSTR_TIM5RST_Pos              (3U)

+#define RCC_APB1LRSTR_TIM5RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */

+#define RCC_APB1LRSTR_TIM5RST                  RCC_APB1LRSTR_TIM5RST_Msk

+#define RCC_APB1LRSTR_TIM6RST_Pos              (4U)

+#define RCC_APB1LRSTR_TIM6RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */

+#define RCC_APB1LRSTR_TIM6RST                  RCC_APB1LRSTR_TIM6RST_Msk

+#define RCC_APB1LRSTR_TIM7RST_Pos              (5U)

+#define RCC_APB1LRSTR_TIM7RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */

+#define RCC_APB1LRSTR_TIM7RST                  RCC_APB1LRSTR_TIM7RST_Msk

+#define RCC_APB1LRSTR_TIM12RST_Pos             (6U)

+#define RCC_APB1LRSTR_TIM12RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */

+#define RCC_APB1LRSTR_TIM12RST                 RCC_APB1LRSTR_TIM12RST_Msk

+#define RCC_APB1LRSTR_TIM13RST_Pos             (7U)

+#define RCC_APB1LRSTR_TIM13RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */

+#define RCC_APB1LRSTR_TIM13RST                 RCC_APB1LRSTR_TIM13RST_Msk

+#define RCC_APB1LRSTR_TIM14RST_Pos             (8U)

+#define RCC_APB1LRSTR_TIM14RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */

+#define RCC_APB1LRSTR_TIM14RST                 RCC_APB1LRSTR_TIM14RST_Msk

+#define RCC_APB1LRSTR_LPTIM1RST_Pos            (9U)

+#define RCC_APB1LRSTR_LPTIM1RST_Msk            (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */

+#define RCC_APB1LRSTR_LPTIM1RST                RCC_APB1LRSTR_LPTIM1RST_Msk

+#define RCC_APB1LRSTR_SPI2RST_Pos              (14U)

+#define RCC_APB1LRSTR_SPI2RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */

+#define RCC_APB1LRSTR_SPI2RST                  RCC_APB1LRSTR_SPI2RST_Msk

+#define RCC_APB1LRSTR_SPI3RST_Pos              (15U)

+#define RCC_APB1LRSTR_SPI3RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */

+#define RCC_APB1LRSTR_SPI3RST                  RCC_APB1LRSTR_SPI3RST_Msk

+#define RCC_APB1LRSTR_SPDIFRXRST_Pos           (16U)

+#define RCC_APB1LRSTR_SPDIFRXRST_Msk           (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */

+#define RCC_APB1LRSTR_SPDIFRXRST               RCC_APB1LRSTR_SPDIFRXRST_Msk

+#define RCC_APB1LRSTR_USART2RST_Pos            (17U)

+#define RCC_APB1LRSTR_USART2RST_Msk            (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */

+#define RCC_APB1LRSTR_USART2RST                RCC_APB1LRSTR_USART2RST_Msk

+#define RCC_APB1LRSTR_USART3RST_Pos            (18U)

+#define RCC_APB1LRSTR_USART3RST_Msk            (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */

+#define RCC_APB1LRSTR_USART3RST                RCC_APB1LRSTR_USART3RST_Msk

+#define RCC_APB1LRSTR_UART4RST_Pos             (19U)

+#define RCC_APB1LRSTR_UART4RST_Msk             (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */

+#define RCC_APB1LRSTR_UART4RST                 RCC_APB1LRSTR_UART4RST_Msk

+#define RCC_APB1LRSTR_UART5RST_Pos             (20U)

+#define RCC_APB1LRSTR_UART5RST_Msk             (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */

+#define RCC_APB1LRSTR_UART5RST                 RCC_APB1LRSTR_UART5RST_Msk

+#define RCC_APB1LRSTR_I2C1RST_Pos              (21U)

+#define RCC_APB1LRSTR_I2C1RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */

+#define RCC_APB1LRSTR_I2C1RST                  RCC_APB1LRSTR_I2C1RST_Msk

+#define RCC_APB1LRSTR_I2C2RST_Pos              (22U)

+#define RCC_APB1LRSTR_I2C2RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */

+#define RCC_APB1LRSTR_I2C2RST                  RCC_APB1LRSTR_I2C2RST_Msk

+#define RCC_APB1LRSTR_I2C3RST_Pos              (23U)

+#define RCC_APB1LRSTR_I2C3RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */

+#define RCC_APB1LRSTR_I2C3RST                  RCC_APB1LRSTR_I2C3RST_Msk

+#define RCC_APB1LRSTR_CECRST_Pos               (27U)

+#define RCC_APB1LRSTR_CECRST_Msk               (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */

+#define RCC_APB1LRSTR_CECRST                   RCC_APB1LRSTR_CECRST_Msk

+#define RCC_APB1LRSTR_DAC12RST_Pos             (29U)

+#define RCC_APB1LRSTR_DAC12RST_Msk             (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */

+#define RCC_APB1LRSTR_DAC12RST                 RCC_APB1LRSTR_DAC12RST_Msk

+#define RCC_APB1LRSTR_UART7RST_Pos             (30U)

+#define RCC_APB1LRSTR_UART7RST_Msk             (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */

+#define RCC_APB1LRSTR_UART7RST                 RCC_APB1LRSTR_UART7RST_Msk

+#define RCC_APB1LRSTR_UART8RST_Pos             (31U)

+#define RCC_APB1LRSTR_UART8RST_Msk             (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */

+#define RCC_APB1LRSTR_UART8RST                 RCC_APB1LRSTR_UART8RST_Msk

+

+/* Legacy define */

+#define RCC_APB1LRSTR_HDMICECRST_Pos           RCC_APB1LRSTR_CECRST_Pos

+#define RCC_APB1LRSTR_HDMICECRST_Msk           RCC_APB1LRSTR_CECRST_Msk

+#define RCC_APB1LRSTR_HDMICECRST               RCC_APB1LRSTR_CECRST

+/********************  Bit definition for RCC_APB1HRSTR register  ******************/

+#define RCC_APB1HRSTR_CRSRST_Pos               (1U)

+#define RCC_APB1HRSTR_CRSRST_Msk               (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */

+#define RCC_APB1HRSTR_CRSRST                   RCC_APB1HRSTR_CRSRST_Msk

+#define RCC_APB1HRSTR_SWPMIRST_Pos             (2U)

+#define RCC_APB1HRSTR_SWPMIRST_Msk             (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */

+#define RCC_APB1HRSTR_SWPMIRST                 RCC_APB1HRSTR_SWPMIRST_Msk

+#define RCC_APB1HRSTR_OPAMPRST_Pos             (4U)

+#define RCC_APB1HRSTR_OPAMPRST_Msk             (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */

+#define RCC_APB1HRSTR_OPAMPRST                 RCC_APB1HRSTR_OPAMPRST_Msk

+#define RCC_APB1HRSTR_MDIOSRST_Pos             (5U)

+#define RCC_APB1HRSTR_MDIOSRST_Msk             (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */

+#define RCC_APB1HRSTR_MDIOSRST                 RCC_APB1HRSTR_MDIOSRST_Msk

+#define RCC_APB1HRSTR_FDCANRST_Pos             (8U)

+#define RCC_APB1HRSTR_FDCANRST_Msk             (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */

+#define RCC_APB1HRSTR_FDCANRST                 RCC_APB1HRSTR_FDCANRST_Msk

+

+/********************  Bit definition for RCC_APB2RSTR register  ******************/

+#define RCC_APB2RSTR_TIM1RST_Pos               (0U)

+#define RCC_APB2RSTR_TIM1RST_Msk               (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */

+#define RCC_APB2RSTR_TIM1RST                   RCC_APB2RSTR_TIM1RST_Msk

+#define RCC_APB2RSTR_TIM8RST_Pos               (1U)

+#define RCC_APB2RSTR_TIM8RST_Msk               (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */

+#define RCC_APB2RSTR_TIM8RST                   RCC_APB2RSTR_TIM8RST_Msk

+#define RCC_APB2RSTR_USART1RST_Pos             (4U)

+#define RCC_APB2RSTR_USART1RST_Msk             (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */

+#define RCC_APB2RSTR_USART1RST                 RCC_APB2RSTR_USART1RST_Msk

+#define RCC_APB2RSTR_USART6RST_Pos             (5U)

+#define RCC_APB2RSTR_USART6RST_Msk             (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */

+#define RCC_APB2RSTR_USART6RST                 RCC_APB2RSTR_USART6RST_Msk

+#define RCC_APB2RSTR_SPI1RST_Pos               (12U)

+#define RCC_APB2RSTR_SPI1RST_Msk               (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */

+#define RCC_APB2RSTR_SPI1RST                   RCC_APB2RSTR_SPI1RST_Msk

+#define RCC_APB2RSTR_SPI4RST_Pos               (13U)

+#define RCC_APB2RSTR_SPI4RST_Msk               (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */

+#define RCC_APB2RSTR_SPI4RST                   RCC_APB2RSTR_SPI4RST_Msk

+#define RCC_APB2RSTR_TIM15RST_Pos              (16U)

+#define RCC_APB2RSTR_TIM15RST_Msk              (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */

+#define RCC_APB2RSTR_TIM15RST                  RCC_APB2RSTR_TIM15RST_Msk

+#define RCC_APB2RSTR_TIM16RST_Pos              (17U)

+#define RCC_APB2RSTR_TIM16RST_Msk              (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */

+#define RCC_APB2RSTR_TIM16RST                  RCC_APB2RSTR_TIM16RST_Msk

+#define RCC_APB2RSTR_TIM17RST_Pos              (18U)

+#define RCC_APB2RSTR_TIM17RST_Msk              (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */

+#define RCC_APB2RSTR_TIM17RST                  RCC_APB2RSTR_TIM17RST_Msk

+#define RCC_APB2RSTR_SPI5RST_Pos               (20U)

+#define RCC_APB2RSTR_SPI5RST_Msk               (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */

+#define RCC_APB2RSTR_SPI5RST                   RCC_APB2RSTR_SPI5RST_Msk

+#define RCC_APB2RSTR_SAI1RST_Pos               (22U)

+#define RCC_APB2RSTR_SAI1RST_Msk               (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */

+#define RCC_APB2RSTR_SAI1RST                   RCC_APB2RSTR_SAI1RST_Msk

+#define RCC_APB2RSTR_SAI2RST_Pos               (23U)

+#define RCC_APB2RSTR_SAI2RST_Msk               (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */

+#define RCC_APB2RSTR_SAI2RST                   RCC_APB2RSTR_SAI2RST_Msk

+#define RCC_APB2RSTR_SAI3RST_Pos               (24U)

+#define RCC_APB2RSTR_SAI3RST_Msk               (0x1UL << RCC_APB2RSTR_SAI3RST_Pos) /*!< 0x01000000 */

+#define RCC_APB2RSTR_SAI3RST                   RCC_APB2RSTR_SAI3RST_Msk

+#define RCC_APB2RSTR_DFSDM1RST_Pos             (28U)

+#define RCC_APB2RSTR_DFSDM1RST_Msk             (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */

+#define RCC_APB2RSTR_DFSDM1RST                 RCC_APB2RSTR_DFSDM1RST_Msk

+#define RCC_APB2RSTR_HRTIMRST_Pos              (29U)

+#define RCC_APB2RSTR_HRTIMRST_Msk              (0x1UL << RCC_APB2RSTR_HRTIMRST_Pos) /*!< 0x20000000 */

+#define RCC_APB2RSTR_HRTIMRST                  RCC_APB2RSTR_HRTIMRST_Msk

+

+/********************  Bit definition for RCC_APB4RSTR register  ******************/

+#define RCC_APB4RSTR_SYSCFGRST_Pos             (1U)

+#define RCC_APB4RSTR_SYSCFGRST_Msk             (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */

+#define RCC_APB4RSTR_SYSCFGRST                 RCC_APB4RSTR_SYSCFGRST_Msk

+#define RCC_APB4RSTR_LPUART1RST_Pos            (3U)

+#define RCC_APB4RSTR_LPUART1RST_Msk            (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */

+#define RCC_APB4RSTR_LPUART1RST                RCC_APB4RSTR_LPUART1RST_Msk

+#define RCC_APB4RSTR_SPI6RST_Pos               (5U)

+#define RCC_APB4RSTR_SPI6RST_Msk               (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */

+#define RCC_APB4RSTR_SPI6RST                   RCC_APB4RSTR_SPI6RST_Msk

+#define RCC_APB4RSTR_I2C4RST_Pos               (7U)

+#define RCC_APB4RSTR_I2C4RST_Msk               (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */

+#define RCC_APB4RSTR_I2C4RST                   RCC_APB4RSTR_I2C4RST_Msk

+#define RCC_APB4RSTR_LPTIM2RST_Pos             (9U)

+#define RCC_APB4RSTR_LPTIM2RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */

+#define RCC_APB4RSTR_LPTIM2RST                 RCC_APB4RSTR_LPTIM2RST_Msk

+#define RCC_APB4RSTR_LPTIM3RST_Pos             (10U)

+#define RCC_APB4RSTR_LPTIM3RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */

+#define RCC_APB4RSTR_LPTIM3RST                 RCC_APB4RSTR_LPTIM3RST_Msk

+#define RCC_APB4RSTR_LPTIM4RST_Pos             (11U)

+#define RCC_APB4RSTR_LPTIM4RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos) /*!< 0x00000800 */

+#define RCC_APB4RSTR_LPTIM4RST                 RCC_APB4RSTR_LPTIM4RST_Msk

+#define RCC_APB4RSTR_LPTIM5RST_Pos             (12U)

+#define RCC_APB4RSTR_LPTIM5RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos) /*!< 0x00001000 */

+#define RCC_APB4RSTR_LPTIM5RST                 RCC_APB4RSTR_LPTIM5RST_Msk

+#define RCC_APB4RSTR_COMP12RST_Pos             (14U)

+#define RCC_APB4RSTR_COMP12RST_Msk             (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */

+#define RCC_APB4RSTR_COMP12RST                 RCC_APB4RSTR_COMP12RST_Msk

+#define RCC_APB4RSTR_VREFRST_Pos               (15U)

+#define RCC_APB4RSTR_VREFRST_Msk               (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */

+#define RCC_APB4RSTR_VREFRST                   RCC_APB4RSTR_VREFRST_Msk

+#define RCC_APB4RSTR_SAI4RST_Pos               (21U)

+#define RCC_APB4RSTR_SAI4RST_Msk               (0x1UL << RCC_APB4RSTR_SAI4RST_Pos) /*!< 0x00200000 */

+#define RCC_APB4RSTR_SAI4RST                   RCC_APB4RSTR_SAI4RST_Msk

+

+

+/********************  Bit definition for RCC_GCR register  ********************/

+#define RCC_GCR_WW1RSC_Pos                     (0U)

+#define RCC_GCR_WW1RSC_Msk                     (0x1UL << RCC_GCR_WW1RSC_Pos)   /*!< 0x00000001 */

+#define RCC_GCR_WW1RSC                         RCC_GCR_WW1RSC_Msk

+#define RCC_GCR_WW2RSC_Pos                     (1U)

+#define RCC_GCR_WW2RSC_Msk                     (0x1UL << RCC_GCR_WW2RSC_Pos)   /*!< 0x00000002 */

+#define RCC_GCR_WW2RSC                         RCC_GCR_WW2RSC_Msk

+#define RCC_GCR_BOOT_C1_Pos                    (2U)

+#define RCC_GCR_BOOT_C1_Msk                    (0x1UL << RCC_GCR_BOOT_C1_Pos)  /*!< 0x00000004 */

+#define RCC_GCR_BOOT_C1                        RCC_GCR_BOOT_C1_Msk

+#define RCC_GCR_BOOT_C2_Pos                    (3U)

+#define RCC_GCR_BOOT_C2_Msk                    (0x1UL << RCC_GCR_BOOT_C2_Pos)  /*!< 0x00000008 */

+#define RCC_GCR_BOOT_C2                        RCC_GCR_BOOT_C2_Msk

+

+/********************  Bit definition for RCC_D3AMR register  ********************/

+#define RCC_D3AMR_BDMAAMEN_Pos                 (0U)

+#define RCC_D3AMR_BDMAAMEN_Msk                 (0x1UL << RCC_D3AMR_BDMAAMEN_Pos) /*!< 0x00000001 */

+#define RCC_D3AMR_BDMAAMEN                     RCC_D3AMR_BDMAAMEN_Msk

+#define RCC_D3AMR_LPUART1AMEN_Pos              (3U)

+#define RCC_D3AMR_LPUART1AMEN_Msk              (0x1UL << RCC_D3AMR_LPUART1AMEN_Pos) /*!< 0x00000008 */

+#define RCC_D3AMR_LPUART1AMEN                  RCC_D3AMR_LPUART1AMEN_Msk

+#define RCC_D3AMR_SPI6AMEN_Pos                 (5U)

+#define RCC_D3AMR_SPI6AMEN_Msk                 (0x1UL << RCC_D3AMR_SPI6AMEN_Pos) /*!< 0x00000020 */

+#define RCC_D3AMR_SPI6AMEN                     RCC_D3AMR_SPI6AMEN_Msk

+#define RCC_D3AMR_I2C4AMEN_Pos                 (7U)

+#define RCC_D3AMR_I2C4AMEN_Msk                 (0x1UL << RCC_D3AMR_I2C4AMEN_Pos) /*!< 0x00000080 */

+#define RCC_D3AMR_I2C4AMEN                     RCC_D3AMR_I2C4AMEN_Msk

+#define RCC_D3AMR_LPTIM2AMEN_Pos               (9U)

+#define RCC_D3AMR_LPTIM2AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */

+#define RCC_D3AMR_LPTIM2AMEN                   RCC_D3AMR_LPTIM2AMEN_Msk

+#define RCC_D3AMR_LPTIM3AMEN_Pos               (10U)

+#define RCC_D3AMR_LPTIM3AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */

+#define RCC_D3AMR_LPTIM3AMEN                   RCC_D3AMR_LPTIM3AMEN_Msk

+#define RCC_D3AMR_LPTIM4AMEN_Pos               (11U)

+#define RCC_D3AMR_LPTIM4AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM4AMEN_Pos) /*!< 0x00000800 */

+#define RCC_D3AMR_LPTIM4AMEN                   RCC_D3AMR_LPTIM4AMEN_Msk

+#define RCC_D3AMR_LPTIM5AMEN_Pos               (12U)

+#define RCC_D3AMR_LPTIM5AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM5AMEN_Pos) /*!< 0x00001000 */

+#define RCC_D3AMR_LPTIM5AMEN                   RCC_D3AMR_LPTIM5AMEN_Msk

+#define RCC_D3AMR_COMP12AMEN_Pos               (14U)

+#define RCC_D3AMR_COMP12AMEN_Msk               (0x1UL << RCC_D3AMR_COMP12AMEN_Pos) /*!< 0x00004000 */

+#define RCC_D3AMR_COMP12AMEN                   RCC_D3AMR_COMP12AMEN_Msk

+#define RCC_D3AMR_VREFAMEN_Pos                 (15U)

+#define RCC_D3AMR_VREFAMEN_Msk                 (0x1UL << RCC_D3AMR_VREFAMEN_Pos) /*!< 0x00008000 */

+#define RCC_D3AMR_VREFAMEN                     RCC_D3AMR_VREFAMEN_Msk

+#define RCC_D3AMR_RTCAMEN_Pos                  (16U)

+#define RCC_D3AMR_RTCAMEN_Msk                  (0x1UL << RCC_D3AMR_RTCAMEN_Pos) /*!< 0x00010000 */

+#define RCC_D3AMR_RTCAMEN                      RCC_D3AMR_RTCAMEN_Msk

+#define RCC_D3AMR_CRCAMEN_Pos                  (19U)

+#define RCC_D3AMR_CRCAMEN_Msk                  (0x1UL << RCC_D3AMR_CRCAMEN_Pos) /*!< 0x00080000 */

+#define RCC_D3AMR_CRCAMEN                      RCC_D3AMR_CRCAMEN_Msk

+#define RCC_D3AMR_SAI4AMEN_Pos                 (21U)

+#define RCC_D3AMR_SAI4AMEN_Msk                 (0x1UL << RCC_D3AMR_SAI4AMEN_Pos) /*!< 0x00200000 */

+#define RCC_D3AMR_SAI4AMEN                     RCC_D3AMR_SAI4AMEN_Msk

+#define RCC_D3AMR_ADC3AMEN_Pos                 (24U)

+#define RCC_D3AMR_ADC3AMEN_Msk                 (0x1UL << RCC_D3AMR_ADC3AMEN_Pos) /*!< 0x01000000 */

+#define RCC_D3AMR_ADC3AMEN                     RCC_D3AMR_ADC3AMEN_Msk

+

+

+#define RCC_D3AMR_BKPRAMAMEN_Pos               (28U)

+#define RCC_D3AMR_BKPRAMAMEN_Msk               (0x1UL << RCC_D3AMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */

+#define RCC_D3AMR_BKPRAMAMEN                   RCC_D3AMR_BKPRAMAMEN_Msk

+#define RCC_D3AMR_SRAM4AMEN_Pos                (29U)

+#define RCC_D3AMR_SRAM4AMEN_Msk                (0x1UL << RCC_D3AMR_SRAM4AMEN_Pos) /*!< 0x20000000 */

+#define RCC_D3AMR_SRAM4AMEN                    RCC_D3AMR_SRAM4AMEN_Msk

+/********************  Bit definition for RCC_AHB3LPENR register  **************/

+#define RCC_AHB3LPENR_MDMALPEN_Pos             (0U)

+#define RCC_AHB3LPENR_MDMALPEN_Msk             (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos)         /*!< 0x00000001 */

+#define RCC_AHB3LPENR_MDMALPEN                 RCC_AHB3LPENR_MDMALPEN_Msk

+#define RCC_AHB3LPENR_DMA2DLPEN_Pos            (4U)

+#define RCC_AHB3LPENR_DMA2DLPEN_Msk            (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos)        /*!< 0x00000010 */

+#define RCC_AHB3LPENR_DMA2DLPEN                RCC_AHB3LPENR_DMA2DLPEN_Msk

+#define RCC_AHB3LPENR_JPGDECLPEN_Pos           (5U)

+#define RCC_AHB3LPENR_JPGDECLPEN_Msk           (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos)       /*!< 0x00000020 */

+#define RCC_AHB3LPENR_JPGDECLPEN               RCC_AHB3LPENR_JPGDECLPEN_Msk

+#define RCC_AHB3LPENR_FLASHLPEN_Pos            (8U)

+#define RCC_AHB3LPENR_FLASHLPEN_Msk            (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos)        /*!< 0x00000100 */

+#define RCC_AHB3LPENR_FLASHLPEN                RCC_AHB3LPENR_FLASHLPEN_Msk

+#define RCC_AHB3LPENR_FMCLPEN_Pos              (12U)

+#define RCC_AHB3LPENR_FMCLPEN_Msk              (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)          /*!< 0x00001000 */

+#define RCC_AHB3LPENR_FMCLPEN                  RCC_AHB3LPENR_FMCLPEN_Msk

+#define RCC_AHB3LPENR_QSPILPEN_Pos             (14U)

+#define RCC_AHB3LPENR_QSPILPEN_Msk             (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos)         /*!< 0x00004000 */

+#define RCC_AHB3LPENR_QSPILPEN                 RCC_AHB3LPENR_QSPILPEN_Msk

+#define RCC_AHB3LPENR_SDMMC1LPEN_Pos           (16U)

+#define RCC_AHB3LPENR_SDMMC1LPEN_Msk           (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos)       /*!< 0x00010000 */

+#define RCC_AHB3LPENR_SDMMC1LPEN               RCC_AHB3LPENR_SDMMC1LPEN_Msk

+#define RCC_AHB3LPENR_DTCM1LPEN_Pos            (28U)

+#define RCC_AHB3LPENR_DTCM1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos)        /*!< 0x10000000 */

+#define RCC_AHB3LPENR_DTCM1LPEN                RCC_AHB3LPENR_DTCM1LPEN_Msk

+#define RCC_AHB3LPENR_DTCM2LPEN_Pos            (29U)

+#define RCC_AHB3LPENR_DTCM2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos)        /*!< 0x20000000 */

+#define RCC_AHB3LPENR_DTCM2LPEN                RCC_AHB3LPENR_DTCM2LPEN_Msk

+#define RCC_AHB3LPENR_ITCMLPEN_Pos             (30U)

+#define RCC_AHB3LPENR_ITCMLPEN_Msk             (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos)         /*!< 0x40000000 */

+#define RCC_AHB3LPENR_ITCMLPEN                 RCC_AHB3LPENR_ITCMLPEN_Msk

+#define RCC_AHB3LPENR_AXISRAMLPEN_Pos          (31U)

+#define RCC_AHB3LPENR_AXISRAMLPEN_Msk          (0x1UL << RCC_AHB3LPENR_AXISRAMLPEN_Pos)      /*!< 0x80000000 */

+#define RCC_AHB3LPENR_AXISRAMLPEN              RCC_AHB3LPENR_AXISRAMLPEN_Msk

+

+

+/********************  Bit definition for RCC_AHB1LPENR register  ***************/

+#define RCC_AHB1LPENR_DMA1LPEN_Pos             (0U)

+#define RCC_AHB1LPENR_DMA1LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB1LPENR_DMA1LPEN                 RCC_AHB1LPENR_DMA1LPEN_Msk

+#define RCC_AHB1LPENR_DMA2LPEN_Pos             (1U)

+#define RCC_AHB1LPENR_DMA2LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */

+#define RCC_AHB1LPENR_DMA2LPEN                 RCC_AHB1LPENR_DMA2LPEN_Msk

+#define RCC_AHB1LPENR_ADC12LPEN_Pos            (5U)

+#define RCC_AHB1LPENR_ADC12LPEN_Msk            (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB1LPENR_ADC12LPEN                RCC_AHB1LPENR_ADC12LPEN_Msk

+#define RCC_AHB1LPENR_ARTLPEN_Pos              (14U)

+#define RCC_AHB1LPENR_ARTLPEN_Msk              (0x1UL << RCC_AHB1LPENR_ARTLPEN_Pos) /*!< 0x00004000 */

+#define RCC_AHB1LPENR_ARTLPEN                  RCC_AHB1LPENR_ARTLPEN_Msk

+#define RCC_AHB1LPENR_ETH1MACLPEN_Pos          (15U)

+#define RCC_AHB1LPENR_ETH1MACLPEN_Msk          (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) /*!< 0x00008000 */

+#define RCC_AHB1LPENR_ETH1MACLPEN              RCC_AHB1LPENR_ETH1MACLPEN_Msk

+#define RCC_AHB1LPENR_ETH1TXLPEN_Pos           (16U)

+#define RCC_AHB1LPENR_ETH1TXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00010000 */

+#define RCC_AHB1LPENR_ETH1TXLPEN               RCC_AHB1LPENR_ETH1TXLPEN_Msk

+#define RCC_AHB1LPENR_ETH1RXLPEN_Pos           (17U)

+#define RCC_AHB1LPENR_ETH1RXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00020000 */

+#define RCC_AHB1LPENR_ETH1RXLPEN               RCC_AHB1LPENR_ETH1RXLPEN_Msk

+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos        (25U)

+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */

+#define RCC_AHB1LPENR_USB1OTGHSLPEN            RCC_AHB1LPENR_USB1OTGHSLPEN_Msk

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos    (26U)

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN        RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGFSLPEN_Pos        (27U)

+#define RCC_AHB1LPENR_USB2OTGFSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB2OTGFSLPEN_Pos) /*!< 0x08000000 */

+#define RCC_AHB1LPENR_USB2OTGFSLPEN            RCC_AHB1LPENR_USB2OTGFSLPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos    (28U)

+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos) /*!< 0x10000000 */

+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN        RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk

+

+/* Legacy define */

+#define RCC_AHB1LPENR_USB2OTGHSLPEN_Pos        RCC_AHB1LPENR_USB2OTGFSLPEN_Pos

+#define RCC_AHB1LPENR_USB2OTGHSLPEN_Msk        RCC_AHB1LPENR_USB2OTGFSLPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGHSLPEN            RCC_AHB1LPENR_USB2OTGFSLPEN

+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Pos    RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos

+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Msk    RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN        RCC_AHB1LPENR_USB2OTGFSULPILPEN

+

+/********************  Bit definition for RCC_AHB2LPENR register  ***************/

+#define RCC_AHB2LPENR_DCMILPEN_Pos             (0U)

+#define RCC_AHB2LPENR_DCMILPEN_Msk             (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB2LPENR_DCMILPEN                 RCC_AHB2LPENR_DCMILPEN_Msk

+#define RCC_AHB2LPENR_CRYPLPEN_Pos             (4U)

+#define RCC_AHB2LPENR_CRYPLPEN_Msk             (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */

+#define RCC_AHB2LPENR_CRYPLPEN                 RCC_AHB2LPENR_CRYPLPEN_Msk

+#define RCC_AHB2LPENR_HASHLPEN_Pos             (5U)

+#define RCC_AHB2LPENR_HASHLPEN_Msk             (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB2LPENR_HASHLPEN                 RCC_AHB2LPENR_HASHLPEN_Msk

+#define RCC_AHB2LPENR_RNGLPEN_Pos              (6U)

+#define RCC_AHB2LPENR_RNGLPEN_Msk              (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */

+#define RCC_AHB2LPENR_RNGLPEN                  RCC_AHB2LPENR_RNGLPEN_Msk

+#define RCC_AHB2LPENR_SDMMC2LPEN_Pos           (9U)

+#define RCC_AHB2LPENR_SDMMC2LPEN_Msk           (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */

+#define RCC_AHB2LPENR_SDMMC2LPEN               RCC_AHB2LPENR_SDMMC2LPEN_Msk

+#define RCC_AHB2LPENR_SRAM1LPEN_Pos          (29U)

+#define RCC_AHB2LPENR_SRAM1LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos) /*!< 0x20000000 */

+#define RCC_AHB2LPENR_SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN_Msk

+#define RCC_AHB2LPENR_SRAM2LPEN_Pos          (30U)

+#define RCC_AHB2LPENR_SRAM2LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */

+#define RCC_AHB2LPENR_SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN_Msk

+#define RCC_AHB2LPENR_SRAM3LPEN_Pos          (31U)

+#define RCC_AHB2LPENR_SRAM3LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM3LPEN_Pos) /*!< 0x80000000 */

+#define RCC_AHB2LPENR_SRAM3LPEN              RCC_AHB2LPENR_SRAM3LPEN_Msk

+

+/* Legacy define */

+#define RCC_AHB2LPENR_D2SRAM1LPEN_Pos          RCC_AHB2LPENR_SRAM1LPEN_Pos

+#define RCC_AHB2LPENR_D2SRAM1LPEN_Msk          RCC_AHB2LPENR_SRAM1LPEN_Msk

+#define RCC_AHB2LPENR_D2SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN

+#define RCC_AHB2LPENR_D2SRAM2LPEN_Pos          RCC_AHB2LPENR_SRAM2LPEN_Pos

+#define RCC_AHB2LPENR_D2SRAM2LPEN_Msk          RCC_AHB2LPENR_SRAM2LPEN_Msk

+#define RCC_AHB2LPENR_D2SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN

+#define RCC_AHB2LPENR_D2SRAM3LPEN_Pos          RCC_AHB2LPENR_SRAM3LPEN_Pos

+#define RCC_AHB2LPENR_D2SRAM3LPEN_Msk          RCC_AHB2LPENR_SRAM3LPEN_Msk

+#define RCC_AHB2LPENR_D2SRAM3LPEN              RCC_AHB2LPENR_SRAM3LPEN

+

+/********************  Bit definition for RCC_AHB4LPENR register  ******************/

+#define RCC_AHB4LPENR_GPIOALPEN_Pos            (0U)

+#define RCC_AHB4LPENR_GPIOALPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB4LPENR_GPIOALPEN                RCC_AHB4LPENR_GPIOALPEN_Msk

+#define RCC_AHB4LPENR_GPIOBLPEN_Pos            (1U)

+#define RCC_AHB4LPENR_GPIOBLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */

+#define RCC_AHB4LPENR_GPIOBLPEN                RCC_AHB4LPENR_GPIOBLPEN_Msk

+#define RCC_AHB4LPENR_GPIOCLPEN_Pos            (2U)

+#define RCC_AHB4LPENR_GPIOCLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */

+#define RCC_AHB4LPENR_GPIOCLPEN                RCC_AHB4LPENR_GPIOCLPEN_Msk

+#define RCC_AHB4LPENR_GPIODLPEN_Pos            (3U)

+#define RCC_AHB4LPENR_GPIODLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */

+#define RCC_AHB4LPENR_GPIODLPEN                RCC_AHB4LPENR_GPIODLPEN_Msk

+#define RCC_AHB4LPENR_GPIOELPEN_Pos            (4U)

+#define RCC_AHB4LPENR_GPIOELPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */

+#define RCC_AHB4LPENR_GPIOELPEN                RCC_AHB4LPENR_GPIOELPEN_Msk

+#define RCC_AHB4LPENR_GPIOFLPEN_Pos            (5U)

+#define RCC_AHB4LPENR_GPIOFLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB4LPENR_GPIOFLPEN                RCC_AHB4LPENR_GPIOFLPEN_Msk

+#define RCC_AHB4LPENR_GPIOGLPEN_Pos            (6U)

+#define RCC_AHB4LPENR_GPIOGLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */

+#define RCC_AHB4LPENR_GPIOGLPEN                RCC_AHB4LPENR_GPIOGLPEN_Msk

+#define RCC_AHB4LPENR_GPIOHLPEN_Pos            (7U)

+#define RCC_AHB4LPENR_GPIOHLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */

+#define RCC_AHB4LPENR_GPIOHLPEN                RCC_AHB4LPENR_GPIOHLPEN_Msk

+#define RCC_AHB4LPENR_GPIOILPEN_Pos            (8U)

+#define RCC_AHB4LPENR_GPIOILPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */

+#define RCC_AHB4LPENR_GPIOILPEN                RCC_AHB4LPENR_GPIOILPEN_Msk

+#define RCC_AHB4LPENR_GPIOJLPEN_Pos            (9U)

+#define RCC_AHB4LPENR_GPIOJLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */

+#define RCC_AHB4LPENR_GPIOJLPEN                RCC_AHB4LPENR_GPIOJLPEN_Msk

+#define RCC_AHB4LPENR_GPIOKLPEN_Pos            (10U)

+#define RCC_AHB4LPENR_GPIOKLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */

+#define RCC_AHB4LPENR_GPIOKLPEN                RCC_AHB4LPENR_GPIOKLPEN_Msk

+#define RCC_AHB4LPENR_CRCLPEN_Pos              (19U)

+#define RCC_AHB4LPENR_CRCLPEN_Msk              (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */

+#define RCC_AHB4LPENR_CRCLPEN                  RCC_AHB4LPENR_CRCLPEN_Msk

+#define RCC_AHB4LPENR_BDMALPEN_Pos             (21U)

+#define RCC_AHB4LPENR_BDMALPEN_Msk             (0x1UL << RCC_AHB4LPENR_BDMALPEN_Pos) /*!< 0x00200000 */

+#define RCC_AHB4LPENR_BDMALPEN                 RCC_AHB4LPENR_BDMALPEN_Msk

+#define RCC_AHB4LPENR_ADC3LPEN_Pos             (24U)

+#define RCC_AHB4LPENR_ADC3LPEN_Msk             (0x1UL << RCC_AHB4LPENR_ADC3LPEN_Pos) /*!< 0x01000000 */

+#define RCC_AHB4LPENR_ADC3LPEN                 RCC_AHB4LPENR_ADC3LPEN_Msk

+#define RCC_AHB4LPENR_BKPRAMLPEN_Pos           (28U)

+#define RCC_AHB4LPENR_BKPRAMLPEN_Msk           (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */

+#define RCC_AHB4LPENR_BKPRAMLPEN               RCC_AHB4LPENR_BKPRAMLPEN_Msk

+#define RCC_AHB4LPENR_SRAM4LPEN_Pos            (29U)

+#define RCC_AHB4LPENR_SRAM4LPEN_Msk            (0x1UL << RCC_AHB4LPENR_SRAM4LPEN_Pos) /*!< 0x20000000 */

+#define RCC_AHB4LPENR_SRAM4LPEN                RCC_AHB4LPENR_SRAM4LPEN_Msk

+

+/* Legacy define */

+#define RCC_AHB4LPENR_D3SRAM1LPEN_Pos          RCC_AHB4LPENR_SRAM4LPEN_Pos

+#define RCC_AHB4LPENR_D3SRAM1LPEN_Msk          RCC_AHB4LPENR_SRAM4LPEN_Msk

+#define RCC_AHB4LPENR_D3SRAM1LPEN              RCC_AHB4LPENR_SRAM4LPEN

+/********************  Bit definition for RCC_APB3LPENR register  ******************/

+#define RCC_APB3LPENR_LTDCLPEN_Pos             (3U)

+#define RCC_APB3LPENR_LTDCLPEN_Msk             (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB3LPENR_LTDCLPEN                 RCC_APB3LPENR_LTDCLPEN_Msk

+#define RCC_APB3LPENR_WWDG1LPEN_Pos            (6U)

+#define RCC_APB3LPENR_WWDG1LPEN_Msk            (0x1UL << RCC_APB3LPENR_WWDG1LPEN_Pos) /*!< 0x00000040 */

+#define RCC_APB3LPENR_WWDG1LPEN                RCC_APB3LPENR_WWDG1LPEN_Msk

+

+/********************  Bit definition for RCC_APB1LLPENR register  ******************/

+

+#define RCC_APB1LLPENR_TIM2LPEN_Pos            (0U)

+#define RCC_APB1LLPENR_TIM2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */

+#define RCC_APB1LLPENR_TIM2LPEN                RCC_APB1LLPENR_TIM2LPEN_Msk

+#define RCC_APB1LLPENR_TIM3LPEN_Pos            (1U)

+#define RCC_APB1LLPENR_TIM3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1LLPENR_TIM3LPEN                RCC_APB1LLPENR_TIM3LPEN_Msk

+#define RCC_APB1LLPENR_TIM4LPEN_Pos            (2U)

+#define RCC_APB1LLPENR_TIM4LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1LLPENR_TIM4LPEN                RCC_APB1LLPENR_TIM4LPEN_Msk

+#define RCC_APB1LLPENR_TIM5LPEN_Pos            (3U)

+#define RCC_APB1LLPENR_TIM5LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB1LLPENR_TIM5LPEN                RCC_APB1LLPENR_TIM5LPEN_Msk

+#define RCC_APB1LLPENR_TIM6LPEN_Pos            (4U)

+#define RCC_APB1LLPENR_TIM6LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1LLPENR_TIM6LPEN                RCC_APB1LLPENR_TIM6LPEN_Msk

+#define RCC_APB1LLPENR_TIM7LPEN_Pos            (5U)

+#define RCC_APB1LLPENR_TIM7LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1LLPENR_TIM7LPEN                RCC_APB1LLPENR_TIM7LPEN_Msk

+#define RCC_APB1LLPENR_TIM12LPEN_Pos           (6U)

+#define RCC_APB1LLPENR_TIM12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */

+#define RCC_APB1LLPENR_TIM12LPEN               RCC_APB1LLPENR_TIM12LPEN_Msk

+#define RCC_APB1LLPENR_TIM13LPEN_Pos           (7U)

+#define RCC_APB1LLPENR_TIM13LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB1LLPENR_TIM13LPEN               RCC_APB1LLPENR_TIM13LPEN_Msk

+#define RCC_APB1LLPENR_TIM14LPEN_Pos           (8U)

+#define RCC_APB1LLPENR_TIM14LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1LLPENR_TIM14LPEN               RCC_APB1LLPENR_TIM14LPEN_Msk

+#define RCC_APB1LLPENR_LPTIM1LPEN_Pos          (9U)

+#define RCC_APB1LLPENR_LPTIM1LPEN_Msk          (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */

+#define RCC_APB1LLPENR_LPTIM1LPEN              RCC_APB1LLPENR_LPTIM1LPEN_Msk

+

+#define RCC_APB1LLPENR_WWDG2LPEN_Pos           (11U)

+#define RCC_APB1LLPENR_WWDG2LPEN_Msk           (0x1UL << RCC_APB1LLPENR_WWDG2LPEN_Pos) /*!< 0x00000800 */

+#define RCC_APB1LLPENR_WWDG2LPEN               RCC_APB1LLPENR_WWDG2LPEN_Msk

+

+#define RCC_APB1LLPENR_SPI2LPEN_Pos            (14U)

+#define RCC_APB1LLPENR_SPI2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */

+#define RCC_APB1LLPENR_SPI2LPEN                RCC_APB1LLPENR_SPI2LPEN_Msk

+#define RCC_APB1LLPENR_SPI3LPEN_Pos            (15U)

+#define RCC_APB1LLPENR_SPI3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */

+#define RCC_APB1LLPENR_SPI3LPEN                RCC_APB1LLPENR_SPI3LPEN_Msk

+#define RCC_APB1LLPENR_SPDIFRXLPEN_Pos         (16U)

+#define RCC_APB1LLPENR_SPDIFRXLPEN_Msk         (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB1LLPENR_SPDIFRXLPEN             RCC_APB1LLPENR_SPDIFRXLPEN_Msk

+#define RCC_APB1LLPENR_USART2LPEN_Pos          (17U)

+#define RCC_APB1LLPENR_USART2LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */

+#define RCC_APB1LLPENR_USART2LPEN              RCC_APB1LLPENR_USART2LPEN_Msk

+#define RCC_APB1LLPENR_USART3LPEN_Pos          (18U)

+#define RCC_APB1LLPENR_USART3LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */

+#define RCC_APB1LLPENR_USART3LPEN              RCC_APB1LLPENR_USART3LPEN_Msk

+#define RCC_APB1LLPENR_UART4LPEN_Pos           (19U)

+#define RCC_APB1LLPENR_UART4LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */

+#define RCC_APB1LLPENR_UART4LPEN               RCC_APB1LLPENR_UART4LPEN_Msk

+#define RCC_APB1LLPENR_UART5LPEN_Pos           (20U)

+#define RCC_APB1LLPENR_UART5LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */

+#define RCC_APB1LLPENR_UART5LPEN               RCC_APB1LLPENR_UART5LPEN_Msk

+#define RCC_APB1LLPENR_I2C1LPEN_Pos            (21U)

+#define RCC_APB1LLPENR_I2C1LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */

+#define RCC_APB1LLPENR_I2C1LPEN                RCC_APB1LLPENR_I2C1LPEN_Msk

+#define RCC_APB1LLPENR_I2C2LPEN_Pos            (22U)

+#define RCC_APB1LLPENR_I2C2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */

+#define RCC_APB1LLPENR_I2C2LPEN                RCC_APB1LLPENR_I2C2LPEN_Msk

+#define RCC_APB1LLPENR_I2C3LPEN_Pos            (23U)

+#define RCC_APB1LLPENR_I2C3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */

+#define RCC_APB1LLPENR_I2C3LPEN                RCC_APB1LLPENR_I2C3LPEN_Msk

+#define RCC_APB1LLPENR_CECLPEN_Pos             (27U)

+#define RCC_APB1LLPENR_CECLPEN_Msk             (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */

+#define RCC_APB1LLPENR_CECLPEN                 RCC_APB1LLPENR_CECLPEN_Msk

+#define RCC_APB1LLPENR_DAC12LPEN_Pos           (29U)

+#define RCC_APB1LLPENR_DAC12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */

+#define RCC_APB1LLPENR_DAC12LPEN               RCC_APB1LLPENR_DAC12LPEN_Msk

+#define RCC_APB1LLPENR_UART7LPEN_Pos           (30U)

+#define RCC_APB1LLPENR_UART7LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */

+#define RCC_APB1LLPENR_UART7LPEN               RCC_APB1LLPENR_UART7LPEN_Msk

+#define RCC_APB1LLPENR_UART8LPEN_Pos           (31U)

+#define RCC_APB1LLPENR_UART8LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */

+#define RCC_APB1LLPENR_UART8LPEN               RCC_APB1LLPENR_UART8LPEN_Msk

+

+/* Legacy define */

+#define RCC_APB1LLPENR_HDMICECEN_Pos           RCC_APB1LLPENR_CECLPEN_Pos

+#define RCC_APB1LLPENR_HDMICECEN_Msk           RCC_APB1LLPENR_CECLPEN_Msk

+#define RCC_APB1LLPENR_HDMICECEN               RCC_APB1LLPENR_CECLPEN

+/********************  Bit definition for RCC_APB1HLPENR register  ******************/

+#define RCC_APB1HLPENR_CRSLPEN_Pos             (1U)

+#define RCC_APB1HLPENR_CRSLPEN_Msk             (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1HLPENR_CRSLPEN                 RCC_APB1HLPENR_CRSLPEN_Msk

+#define RCC_APB1HLPENR_SWPMILPEN_Pos           (2U)

+#define RCC_APB1HLPENR_SWPMILPEN_Msk           (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1HLPENR_SWPMILPEN               RCC_APB1HLPENR_SWPMILPEN_Msk

+#define RCC_APB1HLPENR_OPAMPLPEN_Pos           (4U)

+#define RCC_APB1HLPENR_OPAMPLPEN_Msk           (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1HLPENR_OPAMPLPEN               RCC_APB1HLPENR_OPAMPLPEN_Msk

+#define RCC_APB1HLPENR_MDIOSLPEN_Pos           (5U)

+#define RCC_APB1HLPENR_MDIOSLPEN_Msk           (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1HLPENR_MDIOSLPEN               RCC_APB1HLPENR_MDIOSLPEN_Msk

+#define RCC_APB1HLPENR_FDCANLPEN_Pos           (8U)

+#define RCC_APB1HLPENR_FDCANLPEN_Msk           (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1HLPENR_FDCANLPEN               RCC_APB1HLPENR_FDCANLPEN_Msk

+

+/********************  Bit definition for RCC_APB2LPENR register  ******************/

+#define RCC_APB2LPENR_TIM1LPEN_Pos             (0U)

+#define RCC_APB2LPENR_TIM1LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */

+#define RCC_APB2LPENR_TIM1LPEN                 RCC_APB2LPENR_TIM1LPEN_Msk

+#define RCC_APB2LPENR_TIM8LPEN_Pos             (1U)

+#define RCC_APB2LPENR_TIM8LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB2LPENR_TIM8LPEN                 RCC_APB2LPENR_TIM8LPEN_Msk

+#define RCC_APB2LPENR_USART1LPEN_Pos           (4U)

+#define RCC_APB2LPENR_USART1LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB2LPENR_USART1LPEN               RCC_APB2LPENR_USART1LPEN_Msk

+#define RCC_APB2LPENR_USART6LPEN_Pos           (5U)

+#define RCC_APB2LPENR_USART6LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB2LPENR_USART6LPEN               RCC_APB2LPENR_USART6LPEN_Msk

+#define RCC_APB2LPENR_SPI1LPEN_Pos             (12U)

+#define RCC_APB2LPENR_SPI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */

+#define RCC_APB2LPENR_SPI1LPEN                 RCC_APB2LPENR_SPI1LPEN_Msk

+#define RCC_APB2LPENR_SPI4LPEN_Pos             (13U)

+#define RCC_APB2LPENR_SPI4LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */

+#define RCC_APB2LPENR_SPI4LPEN                 RCC_APB2LPENR_SPI4LPEN_Msk

+#define RCC_APB2LPENR_TIM15LPEN_Pos            (16U)

+#define RCC_APB2LPENR_TIM15LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB2LPENR_TIM15LPEN                RCC_APB2LPENR_TIM15LPEN_Msk

+#define RCC_APB2LPENR_TIM16LPEN_Pos            (17U)

+#define RCC_APB2LPENR_TIM16LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */

+#define RCC_APB2LPENR_TIM16LPEN                RCC_APB2LPENR_TIM16LPEN_Msk

+#define RCC_APB2LPENR_TIM17LPEN_Pos            (18U)

+#define RCC_APB2LPENR_TIM17LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */

+#define RCC_APB2LPENR_TIM17LPEN                RCC_APB2LPENR_TIM17LPEN_Msk

+#define RCC_APB2LPENR_SPI5LPEN_Pos             (20U)

+#define RCC_APB2LPENR_SPI5LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */

+#define RCC_APB2LPENR_SPI5LPEN                 RCC_APB2LPENR_SPI5LPEN_Msk

+#define RCC_APB2LPENR_SAI1LPEN_Pos             (22U)

+#define RCC_APB2LPENR_SAI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */

+#define RCC_APB2LPENR_SAI1LPEN                 RCC_APB2LPENR_SAI1LPEN_Msk

+#define RCC_APB2LPENR_SAI2LPEN_Pos             (23U)

+#define RCC_APB2LPENR_SAI2LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */

+#define RCC_APB2LPENR_SAI2LPEN                 RCC_APB2LPENR_SAI2LPEN_Msk

+#define RCC_APB2LPENR_SAI3LPEN_Pos             (24U)

+#define RCC_APB2LPENR_SAI3LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI3LPEN_Pos) /*!< 0x01000000 */

+#define RCC_APB2LPENR_SAI3LPEN                 RCC_APB2LPENR_SAI3LPEN_Msk

+#define RCC_APB2LPENR_DFSDM1LPEN_Pos           (28U)

+#define RCC_APB2LPENR_DFSDM1LPEN_Msk           (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x10000000 */

+#define RCC_APB2LPENR_DFSDM1LPEN               RCC_APB2LPENR_DFSDM1LPEN_Msk

+#define RCC_APB2LPENR_HRTIMLPEN_Pos            (29U)

+#define RCC_APB2LPENR_HRTIMLPEN_Msk            (0x1UL << RCC_APB2LPENR_HRTIMLPEN_Pos) /*!< 0x20000000 */

+#define RCC_APB2LPENR_HRTIMLPEN                RCC_APB2LPENR_HRTIMLPEN_Msk

+

+/********************  Bit definition for RCC_APB4LPENR register  ******************/

+#define RCC_APB4LPENR_SYSCFGLPEN_Pos           (1U)

+#define RCC_APB4LPENR_SYSCFGLPEN_Msk           (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB4LPENR_SYSCFGLPEN               RCC_APB4LPENR_SYSCFGLPEN_Msk

+#define RCC_APB4LPENR_LPUART1LPEN_Pos          (3U)

+#define RCC_APB4LPENR_LPUART1LPEN_Msk          (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB4LPENR_LPUART1LPEN              RCC_APB4LPENR_LPUART1LPEN_Msk

+#define RCC_APB4LPENR_SPI6LPEN_Pos             (5U)

+#define RCC_APB4LPENR_SPI6LPEN_Msk             (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB4LPENR_SPI6LPEN                 RCC_APB4LPENR_SPI6LPEN_Msk

+#define RCC_APB4LPENR_I2C4LPEN_Pos             (7U)

+#define RCC_APB4LPENR_I2C4LPEN_Msk             (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB4LPENR_I2C4LPEN                 RCC_APB4LPENR_I2C4LPEN_Msk

+#define RCC_APB4LPENR_LPTIM2LPEN_Pos           (9U)

+#define RCC_APB4LPENR_LPTIM2LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */

+#define RCC_APB4LPENR_LPTIM2LPEN               RCC_APB4LPENR_LPTIM2LPEN_Msk

+#define RCC_APB4LPENR_LPTIM3LPEN_Pos           (10U)

+#define RCC_APB4LPENR_LPTIM3LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */

+#define RCC_APB4LPENR_LPTIM3LPEN               RCC_APB4LPENR_LPTIM3LPEN_Msk

+#define RCC_APB4LPENR_LPTIM4LPEN_Pos           (11U)

+#define RCC_APB4LPENR_LPTIM4LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) /*!< 0x00000800 */

+#define RCC_APB4LPENR_LPTIM4LPEN               RCC_APB4LPENR_LPTIM4LPEN_Msk

+#define RCC_APB4LPENR_LPTIM5LPEN_Pos           (12U)

+#define RCC_APB4LPENR_LPTIM5LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) /*!< 0x00001000 */

+#define RCC_APB4LPENR_LPTIM5LPEN               RCC_APB4LPENR_LPTIM5LPEN_Msk

+#define RCC_APB4LPENR_COMP12LPEN_Pos           (14U)

+#define RCC_APB4LPENR_COMP12LPEN_Msk           (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */

+#define RCC_APB4LPENR_COMP12LPEN               RCC_APB4LPENR_COMP12LPEN_Msk

+#define RCC_APB4LPENR_VREFLPEN_Pos             (15U)

+#define RCC_APB4LPENR_VREFLPEN_Msk             (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */

+#define RCC_APB4LPENR_VREFLPEN                 RCC_APB4LPENR_VREFLPEN_Msk

+#define RCC_APB4LPENR_RTCAPBLPEN_Pos           (16U)

+#define RCC_APB4LPENR_RTCAPBLPEN_Msk           (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB4LPENR_RTCAPBLPEN               RCC_APB4LPENR_RTCAPBLPEN_Msk

+#define RCC_APB4LPENR_SAI4LPEN_Pos             (21U)

+#define RCC_APB4LPENR_SAI4LPEN_Msk             (0x1UL << RCC_APB4LPENR_SAI4LPEN_Pos) /*!< 0x00200000 */

+#define RCC_APB4LPENR_SAI4LPEN                 RCC_APB4LPENR_SAI4LPEN_Msk

+

+

+/********************  Bit definition for RCC_RSR register  *******************/

+#define RCC_RSR_RMVF_Pos                       (16U)

+#define RCC_RSR_RMVF_Msk                       (0x1UL << RCC_RSR_RMVF_Pos)     /*!< 0x00010000 */

+#define RCC_RSR_RMVF                           RCC_RSR_RMVF_Msk

+#define RCC_RSR_C1RSTF_Pos                     (17U)

+#define RCC_RSR_C1RSTF_Msk                     (0x1UL << RCC_RSR_C1RSTF_Pos)   /*!< 0x00020000 */

+#define RCC_RSR_C1RSTF                         RCC_RSR_C1RSTF_Msk

+#define RCC_RSR_D1RSTF_Pos                     (19U)

+#define RCC_RSR_D1RSTF_Msk                     (0x1UL << RCC_RSR_D1RSTF_Pos)   /*!< 0x00080000 */

+#define RCC_RSR_D1RSTF                         RCC_RSR_D1RSTF_Msk

+#define RCC_RSR_D2RSTF_Pos                     (20U)

+#define RCC_RSR_D2RSTF_Msk                     (0x1UL << RCC_RSR_D2RSTF_Pos)   /*!< 0x00100000 */

+#define RCC_RSR_D2RSTF                         RCC_RSR_D2RSTF_Msk

+#define RCC_RSR_BORRSTF_Pos                    (21U)

+#define RCC_RSR_BORRSTF_Msk                    (0x1UL << RCC_RSR_BORRSTF_Pos)  /*!< 0x00200000 */

+#define RCC_RSR_BORRSTF                        RCC_RSR_BORRSTF_Msk

+#define RCC_RSR_PINRSTF_Pos                    (22U)

+#define RCC_RSR_PINRSTF_Msk                    (0x1UL << RCC_RSR_PINRSTF_Pos)  /*!< 0x00400000 */

+#define RCC_RSR_PINRSTF                        RCC_RSR_PINRSTF_Msk

+#define RCC_RSR_PORRSTF_Pos                    (23U)

+#define RCC_RSR_PORRSTF_Msk                    (0x1UL << RCC_RSR_PORRSTF_Pos)  /*!< 0x00800000 */

+#define RCC_RSR_PORRSTF                        RCC_RSR_PORRSTF_Msk

+#define RCC_RSR_SFT1RSTF_Pos                   (24U)

+#define RCC_RSR_SFT1RSTF_Msk                   (0x1UL << RCC_RSR_SFT1RSTF_Pos) /*!< 0x01000000 */

+#define RCC_RSR_SFT1RSTF                       RCC_RSR_SFT1RSTF_Msk

+#define RCC_RSR_IWDG1RSTF_Pos                  (26U)

+#define RCC_RSR_IWDG1RSTF_Msk                  (0x1UL << RCC_RSR_IWDG1RSTF_Pos) /*!< 0x04000000 */

+#define RCC_RSR_IWDG1RSTF                      RCC_RSR_IWDG1RSTF_Msk

+#define RCC_RSR_WWDG1RSTF_Pos                  (28U)

+#define RCC_RSR_WWDG1RSTF_Msk                  (0x1UL << RCC_RSR_WWDG1RSTF_Pos) /*!< 0x10000000 */

+#define RCC_RSR_WWDG1RSTF                      RCC_RSR_WWDG1RSTF_Msk

+

+#define RCC_RSR_WWDG2RSTF_Pos                  (29U)

+#define RCC_RSR_WWDG2RSTF_Msk                  (0x1UL << RCC_RSR_WWDG2RSTF_Pos) /*!< 0x20000000 */

+#define RCC_RSR_WWDG2RSTF                      RCC_RSR_WWDG2RSTF_Msk

+#define RCC_RSR_IWDG2RSTF_Pos                  (27U)

+#define RCC_RSR_IWDG2RSTF_Msk                  (0x1UL << RCC_RSR_IWDG2RSTF_Pos) /*!< 0x08000000 */

+#define RCC_RSR_IWDG2RSTF                      RCC_RSR_IWDG2RSTF_Msk

+#define RCC_RSR_SFT2RSTF_Pos                   (25U)

+#define RCC_RSR_SFT2RSTF_Msk                   (0x1UL << RCC_RSR_SFT2RSTF_Pos) /*!< 0x02000000 */

+#define RCC_RSR_SFT2RSTF                       RCC_RSR_SFT2RSTF_Msk

+#define RCC_RSR_C2RSTF_Pos                     (18U)

+#define RCC_RSR_C2RSTF_Msk                     (0x1UL << RCC_RSR_C2RSTF_Pos)   /*!< 0x00040000 */

+#define RCC_RSR_C2RSTF                         RCC_RSR_C2RSTF_Msk

+#define RCC_RSR_LPWR1RSTF_Pos                  (30U)

+#define RCC_RSR_LPWR1RSTF_Msk                  (0x1UL << RCC_RSR_LPWR1RSTF_Pos) /*!< 0x40000000 */

+#define RCC_RSR_LPWR1RSTF                      RCC_RSR_LPWR1RSTF_Msk

+#define RCC_RSR_LPWR2RSTF_Pos                  (31U)

+#define RCC_RSR_LPWR2RSTF_Msk                  (0x1UL << RCC_RSR_LPWR2RSTF_Pos) /*!< 0x80000000 */

+#define RCC_RSR_LPWR2RSTF                      RCC_RSR_LPWR2RSTF_Msk

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    RNG                                     */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for RNG_CR register  *******************/

+#define RNG_CR_RNGEN_Pos    (2U)

+#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */

+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk

+#define RNG_CR_IE_Pos       (3U)

+#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */

+#define RNG_CR_IE           RNG_CR_IE_Msk

+#define RNG_CR_CED_Pos      (5U)

+#define RNG_CR_CED_Msk      (0x1UL << RNG_CR_CED_Pos)                          /*!< 0x00000020 */

+#define RNG_CR_CED          RNG_CR_CED_Msk

+

+/********************  Bits definition for RNG_SR register  *******************/

+#define RNG_SR_DRDY_Pos     (0U)

+#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */

+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk

+#define RNG_SR_CECS_Pos     (1U)

+#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */

+#define RNG_SR_CECS         RNG_SR_CECS_Msk

+#define RNG_SR_SECS_Pos     (2U)

+#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */

+#define RNG_SR_SECS         RNG_SR_SECS_Msk

+#define RNG_SR_CEIS_Pos     (5U)

+#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */

+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk

+#define RNG_SR_SEIS_Pos     (6U)

+#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */

+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                           Real-Time Clock (RTC)                            */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for RTC_TR register  *******************/

+#define RTC_TR_PM_Pos                  (22U)

+#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */

+#define RTC_TR_PM                      RTC_TR_PM_Msk

+#define RTC_TR_HT_Pos                  (20U)

+#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */

+#define RTC_TR_HT                      RTC_TR_HT_Msk

+#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */

+#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */

+#define RTC_TR_HU_Pos                  (16U)

+#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */

+#define RTC_TR_HU                      RTC_TR_HU_Msk

+#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */

+#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */

+#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */

+#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */

+#define RTC_TR_MNT_Pos                 (12U)

+#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */

+#define RTC_TR_MNT                     RTC_TR_MNT_Msk

+#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */

+#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */

+#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */

+#define RTC_TR_MNU_Pos                 (8U)

+#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */

+#define RTC_TR_MNU                     RTC_TR_MNU_Msk

+#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */

+#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */

+#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */

+#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */

+#define RTC_TR_ST_Pos                  (4U)

+#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */

+#define RTC_TR_ST                      RTC_TR_ST_Msk

+#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */

+#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */

+#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */

+#define RTC_TR_SU_Pos                  (0U)

+#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */

+#define RTC_TR_SU                      RTC_TR_SU_Msk

+#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */

+#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */

+#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */

+#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_DR register  *******************/

+#define RTC_DR_YT_Pos                  (20U)

+#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */

+#define RTC_DR_YT                      RTC_DR_YT_Msk

+#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */

+#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */

+#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */

+#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */

+#define RTC_DR_YU_Pos                  (16U)

+#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */

+#define RTC_DR_YU                      RTC_DR_YU_Msk

+#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */

+#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */

+#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */

+#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */

+#define RTC_DR_WDU_Pos                 (13U)

+#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */

+#define RTC_DR_WDU                     RTC_DR_WDU_Msk

+#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */

+#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */

+#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */

+#define RTC_DR_MT_Pos                  (12U)

+#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */

+#define RTC_DR_MT                      RTC_DR_MT_Msk

+#define RTC_DR_MU_Pos                  (8U)

+#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */

+#define RTC_DR_MU                      RTC_DR_MU_Msk

+#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */

+#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */

+#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */

+#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */

+#define RTC_DR_DT_Pos                  (4U)

+#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */

+#define RTC_DR_DT                      RTC_DR_DT_Msk

+#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */

+#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */

+#define RTC_DR_DU_Pos                  (0U)

+#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */

+#define RTC_DR_DU                      RTC_DR_DU_Msk

+#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */

+#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */

+#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */

+#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_CR register  *******************/

+#define RTC_CR_ITSE_Pos                (24U)

+#define RTC_CR_ITSE_Msk                (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */

+#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk

+#define RTC_CR_COE_Pos                 (23U)

+#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */

+#define RTC_CR_COE                     RTC_CR_COE_Msk

+#define RTC_CR_OSEL_Pos                (21U)

+#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */

+#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk

+#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */

+#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */

+#define RTC_CR_POL_Pos                 (20U)

+#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */

+#define RTC_CR_POL                     RTC_CR_POL_Msk

+#define RTC_CR_COSEL_Pos               (19U)

+#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */

+#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk

+#define RTC_CR_BKP_Pos                 (18U)

+#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */

+#define RTC_CR_BKP                     RTC_CR_BKP_Msk

+#define RTC_CR_SUB1H_Pos               (17U)

+#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */

+#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk

+#define RTC_CR_ADD1H_Pos               (16U)

+#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */

+#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk

+#define RTC_CR_TSIE_Pos                (15U)

+#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */

+#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk

+#define RTC_CR_WUTIE_Pos               (14U)

+#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */

+#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk

+#define RTC_CR_ALRBIE_Pos              (13U)

+#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */

+#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk

+#define RTC_CR_ALRAIE_Pos              (12U)

+#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */

+#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk

+#define RTC_CR_TSE_Pos                 (11U)

+#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */

+#define RTC_CR_TSE                     RTC_CR_TSE_Msk

+#define RTC_CR_WUTE_Pos                (10U)

+#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */

+#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk

+#define RTC_CR_ALRBE_Pos               (9U)

+#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */

+#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk

+#define RTC_CR_ALRAE_Pos               (8U)

+#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */

+#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk

+#define RTC_CR_FMT_Pos                 (6U)

+#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */

+#define RTC_CR_FMT                     RTC_CR_FMT_Msk

+#define RTC_CR_BYPSHAD_Pos             (5U)

+#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */

+#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk

+#define RTC_CR_REFCKON_Pos             (4U)

+#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */

+#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk

+#define RTC_CR_TSEDGE_Pos              (3U)

+#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */

+#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk

+#define RTC_CR_WUCKSEL_Pos             (0U)

+#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */

+#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk

+#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */

+#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */

+#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */

+

+/********************  Bits definition for RTC_ISR register  ******************/

+#define RTC_ISR_ITSF_Pos               (17U)

+#define RTC_ISR_ITSF_Msk               (0x1UL << RTC_ISR_ITSF_Pos)             /*!< 0x00020000 */

+#define RTC_ISR_ITSF                   RTC_ISR_ITSF_Msk

+#define RTC_ISR_RECALPF_Pos            (16U)

+#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)          /*!< 0x00010000 */

+#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk

+#define RTC_ISR_TAMP3F_Pos             (15U)

+#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)           /*!< 0x00008000 */

+#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk

+#define RTC_ISR_TAMP2F_Pos             (14U)

+#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)           /*!< 0x00004000 */

+#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk

+#define RTC_ISR_TAMP1F_Pos             (13U)

+#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)           /*!< 0x00002000 */

+#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk

+#define RTC_ISR_TSOVF_Pos              (12U)

+#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)            /*!< 0x00001000 */

+#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk

+#define RTC_ISR_TSF_Pos                (11U)

+#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)              /*!< 0x00000800 */

+#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk

+#define RTC_ISR_WUTF_Pos               (10U)

+#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)             /*!< 0x00000400 */

+#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk

+#define RTC_ISR_ALRBF_Pos              (9U)

+#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)            /*!< 0x00000200 */

+#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk

+#define RTC_ISR_ALRAF_Pos              (8U)

+#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)            /*!< 0x00000100 */

+#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk

+#define RTC_ISR_INIT_Pos               (7U)

+#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)             /*!< 0x00000080 */

+#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk

+#define RTC_ISR_INITF_Pos              (6U)

+#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)            /*!< 0x00000040 */

+#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk

+#define RTC_ISR_RSF_Pos                (5U)

+#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)              /*!< 0x00000020 */

+#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk

+#define RTC_ISR_INITS_Pos              (4U)

+#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)            /*!< 0x00000010 */

+#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk

+#define RTC_ISR_SHPF_Pos               (3U)

+#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)             /*!< 0x00000008 */

+#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk

+#define RTC_ISR_WUTWF_Pos              (2U)

+#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)            /*!< 0x00000004 */

+#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk

+#define RTC_ISR_ALRBWF_Pos             (1U)

+#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)           /*!< 0x00000002 */

+#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk

+#define RTC_ISR_ALRAWF_Pos             (0U)

+#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)           /*!< 0x00000001 */

+#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk

+

+/********************  Bits definition for RTC_PRER register  *****************/

+#define RTC_PRER_PREDIV_A_Pos          (16U)

+#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */

+#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk

+#define RTC_PRER_PREDIV_S_Pos          (0U)

+#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */

+#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk

+

+/********************  Bits definition for RTC_WUTR register  *****************/

+#define RTC_WUTR_WUT_Pos               (0U)

+#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */

+#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk

+

+/********************  Bits definition for RTC_ALRMAR register  ***************/

+#define RTC_ALRMAR_MSK4_Pos            (31U)

+#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */

+#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk

+#define RTC_ALRMAR_WDSEL_Pos           (30U)

+#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */

+#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk

+#define RTC_ALRMAR_DT_Pos              (28U)

+#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */

+#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk

+#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */

+#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */

+#define RTC_ALRMAR_DU_Pos              (24U)

+#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */

+#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk

+#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */

+#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */

+#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */

+#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */

+#define RTC_ALRMAR_MSK3_Pos            (23U)

+#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */

+#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk

+#define RTC_ALRMAR_PM_Pos              (22U)

+#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */

+#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk

+#define RTC_ALRMAR_HT_Pos              (20U)

+#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */

+#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk

+#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */

+#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */

+#define RTC_ALRMAR_HU_Pos              (16U)

+#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */

+#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk

+#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */

+#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */

+#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */

+#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */

+#define RTC_ALRMAR_MSK2_Pos            (15U)

+#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */

+#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk

+#define RTC_ALRMAR_MNT_Pos             (12U)

+#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */

+#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk

+#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */

+#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */

+#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */

+#define RTC_ALRMAR_MNU_Pos             (8U)

+#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */

+#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk

+#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */

+#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */

+#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */

+#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */

+#define RTC_ALRMAR_MSK1_Pos            (7U)

+#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */

+#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk

+#define RTC_ALRMAR_ST_Pos              (4U)

+#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */

+#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk

+#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */

+#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */

+#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */

+#define RTC_ALRMAR_SU_Pos              (0U)

+#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */

+#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk

+#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */

+#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */

+#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */

+#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_ALRMBR register  ***************/

+#define RTC_ALRMBR_MSK4_Pos            (31U)

+#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */

+#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk

+#define RTC_ALRMBR_WDSEL_Pos           (30U)

+#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */

+#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk

+#define RTC_ALRMBR_DT_Pos              (28U)

+#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */

+#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk

+#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */

+#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */

+#define RTC_ALRMBR_DU_Pos              (24U)

+#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */

+#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk

+#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */

+#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */

+#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */

+#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */

+#define RTC_ALRMBR_MSK3_Pos            (23U)

+#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */

+#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk

+#define RTC_ALRMBR_PM_Pos              (22U)

+#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */

+#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk

+#define RTC_ALRMBR_HT_Pos              (20U)

+#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */

+#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk

+#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */

+#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */

+#define RTC_ALRMBR_HU_Pos              (16U)

+#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */

+#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk

+#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */

+#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */

+#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */

+#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */

+#define RTC_ALRMBR_MSK2_Pos            (15U)

+#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */

+#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk

+#define RTC_ALRMBR_MNT_Pos             (12U)

+#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */

+#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk

+#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */

+#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */

+#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */

+#define RTC_ALRMBR_MNU_Pos             (8U)

+#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */

+#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk

+#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */

+#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */

+#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */

+#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */

+#define RTC_ALRMBR_MSK1_Pos            (7U)

+#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */

+#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk

+#define RTC_ALRMBR_ST_Pos              (4U)

+#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */

+#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk

+#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */

+#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */

+#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */

+#define RTC_ALRMBR_SU_Pos              (0U)

+#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */

+#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk

+#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */

+#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */

+#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */

+#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_WPR register  ******************/

+#define RTC_WPR_KEY_Pos                (0U)

+#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */

+#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk

+

+/********************  Bits definition for RTC_SSR register  ******************/

+#define RTC_SSR_SS_Pos                 (0U)

+#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)            /*!< 0x0000FFFF */

+#define RTC_SSR_SS                     RTC_SSR_SS_Msk

+

+/********************  Bits definition for RTC_SHIFTR register  ***************/

+#define RTC_SHIFTR_SUBFS_Pos           (0U)

+#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */

+#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk

+#define RTC_SHIFTR_ADD1S_Pos           (31U)

+#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */

+#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk

+

+/********************  Bits definition for RTC_TSTR register  *****************/

+#define RTC_TSTR_PM_Pos                (22U)

+#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */

+#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk

+#define RTC_TSTR_HT_Pos                (20U)

+#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */

+#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk

+#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */

+#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */

+#define RTC_TSTR_HU_Pos                (16U)

+#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */

+#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk

+#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */

+#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */

+#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */

+#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */

+#define RTC_TSTR_MNT_Pos               (12U)

+#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */

+#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk

+#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */

+#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */

+#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */

+#define RTC_TSTR_MNU_Pos               (8U)

+#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */

+#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk

+#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */

+#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */

+#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */

+#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */

+#define RTC_TSTR_ST_Pos                (4U)

+#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */

+#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk

+#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */

+#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */

+#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */

+#define RTC_TSTR_SU_Pos                (0U)

+#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */

+#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk

+#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */

+#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */

+#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */

+#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_TSDR register  *****************/

+#define RTC_TSDR_WDU_Pos               (13U)

+#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */

+#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk

+#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */

+#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */

+#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */

+#define RTC_TSDR_MT_Pos                (12U)

+#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */

+#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk

+#define RTC_TSDR_MU_Pos                (8U)

+#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */

+#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk

+#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */

+#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */

+#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */

+#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */

+#define RTC_TSDR_DT_Pos                (4U)

+#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */

+#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk

+#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */

+#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */

+#define RTC_TSDR_DU_Pos                (0U)

+#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */

+#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk

+#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */

+#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */

+#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */

+#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_TSSSR register  ****************/

+#define RTC_TSSSR_SS_Pos               (0U)

+#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)          /*!< 0x0000FFFF */

+#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk

+

+/********************  Bits definition for RTC_CALR register  *****************/

+#define RTC_CALR_CALP_Pos              (15U)

+#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */

+#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk

+#define RTC_CALR_CALW8_Pos             (14U)

+#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */

+#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk

+#define RTC_CALR_CALW16_Pos            (13U)

+#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */

+#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk

+#define RTC_CALR_CALM_Pos              (0U)

+#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */

+#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk

+#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */

+#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */

+#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */

+#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */

+#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */

+#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */

+#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */

+#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */

+#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */

+

+/********************  Bits definition for RTC_TAMPCR register  ***************/

+#define RTC_TAMPCR_TAMP3MF_Pos         (24U)

+#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)       /*!< 0x01000000 */

+#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk

+#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)

+#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)  /*!< 0x00800000 */

+#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk

+#define RTC_TAMPCR_TAMP3IE_Pos         (22U)

+#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)       /*!< 0x00400000 */

+#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk

+#define RTC_TAMPCR_TAMP2MF_Pos         (21U)

+#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)       /*!< 0x00200000 */

+#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk

+#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)

+#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)  /*!< 0x00100000 */

+#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk

+#define RTC_TAMPCR_TAMP2IE_Pos         (19U)

+#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)       /*!< 0x00080000 */

+#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk

+#define RTC_TAMPCR_TAMP1MF_Pos         (18U)

+#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)       /*!< 0x00040000 */

+#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk

+#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)

+#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)  /*!< 0x00020000 */

+#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk

+#define RTC_TAMPCR_TAMP1IE_Pos         (16U)

+#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)       /*!< 0x00010000 */

+#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk

+#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)

+#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)     /*!< 0x00008000 */

+#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk

+#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)

+#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)      /*!< 0x00006000 */

+#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk

+#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */

+#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */

+#define RTC_TAMPCR_TAMPFLT_Pos         (11U)

+#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)       /*!< 0x00001800 */

+#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk

+#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */

+#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */

+#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)

+#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)      /*!< 0x00000700 */

+#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk

+#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */

+#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */

+#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */

+#define RTC_TAMPCR_TAMPTS_Pos          (7U)

+#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)        /*!< 0x00000080 */

+#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk

+#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)

+#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)      /*!< 0x00000040 */

+#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk

+#define RTC_TAMPCR_TAMP3E_Pos          (5U)

+#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)        /*!< 0x00000020 */

+#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk

+#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)

+#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)      /*!< 0x00000010 */

+#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk

+#define RTC_TAMPCR_TAMP2E_Pos          (3U)

+#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)        /*!< 0x00000008 */

+#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk

+#define RTC_TAMPCR_TAMPIE_Pos          (2U)

+#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)        /*!< 0x00000004 */

+#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk

+#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)

+#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)      /*!< 0x00000002 */

+#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk

+#define RTC_TAMPCR_TAMP1E_Pos          (0U)

+#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)        /*!< 0x00000001 */

+#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk

+

+/********************  Bits definition for RTC_ALRMASSR register  *************/

+#define RTC_ALRMASSR_MASKSS_Pos        (24U)

+#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x0F000000 */

+#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk

+#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */

+#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */

+#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */

+#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */

+#define RTC_ALRMASSR_SS_Pos            (0U)

+#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */

+#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk

+

+/********************  Bits definition for RTC_ALRMBSSR register  *************/

+#define RTC_ALRMBSSR_MASKSS_Pos        (24U)

+#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x0F000000 */

+#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk

+#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */

+#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */

+#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */

+#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */

+#define RTC_ALRMBSSR_SS_Pos            (0U)

+#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */

+#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk

+

+/********************  Bits definition for RTC_OR register  *******************/

+#define RTC_OR_OUT_RMP_Pos             (1U)

+#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)           /*!< 0x00000002 */

+#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk

+#define RTC_OR_ALARMOUTTYPE_Pos        (0U)

+#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)      /*!< 0x00000001 */

+#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk

+

+/********************  Bits definition for RTC_BKP0R register  ****************/

+#define RTC_BKP0R_Pos                  (0U)

+#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP0R                      RTC_BKP0R_Msk

+

+/********************  Bits definition for RTC_BKP1R register  ****************/

+#define RTC_BKP1R_Pos                  (0U)

+#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP1R                      RTC_BKP1R_Msk

+

+/********************  Bits definition for RTC_BKP2R register  ****************/

+#define RTC_BKP2R_Pos                  (0U)

+#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP2R                      RTC_BKP2R_Msk

+

+/********************  Bits definition for RTC_BKP3R register  ****************/

+#define RTC_BKP3R_Pos                  (0U)

+#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP3R                      RTC_BKP3R_Msk

+

+/********************  Bits definition for RTC_BKP4R register  ****************/

+#define RTC_BKP4R_Pos                  (0U)

+#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP4R                      RTC_BKP4R_Msk

+

+/********************  Bits definition for RTC_BKP5R register  ****************/

+#define RTC_BKP5R_Pos                  (0U)

+#define RTC_BKP5R_Msk                  (0xFFFFFFFFUL << RTC_BKP5R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP5R                      RTC_BKP5R_Msk

+

+/********************  Bits definition for RTC_BKP6R register  ****************/

+#define RTC_BKP6R_Pos                  (0U)

+#define RTC_BKP6R_Msk                  (0xFFFFFFFFUL << RTC_BKP6R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP6R                      RTC_BKP6R_Msk

+

+/********************  Bits definition for RTC_BKP7R register  ****************/

+#define RTC_BKP7R_Pos                  (0U)

+#define RTC_BKP7R_Msk                  (0xFFFFFFFFUL << RTC_BKP7R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP7R                      RTC_BKP7R_Msk

+

+/********************  Bits definition for RTC_BKP8R register  ****************/

+#define RTC_BKP8R_Pos                  (0U)

+#define RTC_BKP8R_Msk                  (0xFFFFFFFFUL << RTC_BKP8R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP8R                      RTC_BKP8R_Msk

+

+/********************  Bits definition for RTC_BKP9R register  ****************/

+#define RTC_BKP9R_Pos                  (0U)

+#define RTC_BKP9R_Msk                  (0xFFFFFFFFUL << RTC_BKP9R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP9R                      RTC_BKP9R_Msk

+

+/********************  Bits definition for RTC_BKP10R register  ***************/

+#define RTC_BKP10R_Pos                 (0U)

+#define RTC_BKP10R_Msk                 (0xFFFFFFFFUL << RTC_BKP10R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP10R                     RTC_BKP10R_Msk

+

+/********************  Bits definition for RTC_BKP11R register  ***************/

+#define RTC_BKP11R_Pos                 (0U)

+#define RTC_BKP11R_Msk                 (0xFFFFFFFFUL << RTC_BKP11R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP11R                     RTC_BKP11R_Msk

+

+/********************  Bits definition for RTC_BKP12R register  ***************/

+#define RTC_BKP12R_Pos                 (0U)

+#define RTC_BKP12R_Msk                 (0xFFFFFFFFUL << RTC_BKP12R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP12R                     RTC_BKP12R_Msk

+

+/********************  Bits definition for RTC_BKP13R register  ***************/

+#define RTC_BKP13R_Pos                 (0U)

+#define RTC_BKP13R_Msk                 (0xFFFFFFFFUL << RTC_BKP13R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP13R                     RTC_BKP13R_Msk

+

+/********************  Bits definition for RTC_BKP14R register  ***************/

+#define RTC_BKP14R_Pos                 (0U)

+#define RTC_BKP14R_Msk                 (0xFFFFFFFFUL << RTC_BKP14R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP14R                     RTC_BKP14R_Msk

+

+/********************  Bits definition for RTC_BKP15R register  ***************/

+#define RTC_BKP15R_Pos                 (0U)

+#define RTC_BKP15R_Msk                 (0xFFFFFFFFUL << RTC_BKP15R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP15R                     RTC_BKP15R_Msk

+

+/********************  Bits definition for RTC_BKP16R register  ***************/

+#define RTC_BKP16R_Pos                 (0U)

+#define RTC_BKP16R_Msk                 (0xFFFFFFFFUL << RTC_BKP16R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP16R                     RTC_BKP16R_Msk

+

+/********************  Bits definition for RTC_BKP17R register  ***************/

+#define RTC_BKP17R_Pos                 (0U)

+#define RTC_BKP17R_Msk                 (0xFFFFFFFFUL << RTC_BKP17R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP17R                     RTC_BKP17R_Msk

+

+/********************  Bits definition for RTC_BKP18R register  ***************/

+#define RTC_BKP18R_Pos                 (0U)

+#define RTC_BKP18R_Msk                 (0xFFFFFFFFUL << RTC_BKP18R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP18R                     RTC_BKP18R_Msk

+

+/********************  Bits definition for RTC_BKP19R register  ***************/

+#define RTC_BKP19R_Pos                 (0U)

+#define RTC_BKP19R_Msk                 (0xFFFFFFFFUL << RTC_BKP19R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP19R                     RTC_BKP19R_Msk

+

+/********************  Bits definition for RTC_BKP20R register  ***************/

+#define RTC_BKP20R_Pos                 (0U)

+#define RTC_BKP20R_Msk                 (0xFFFFFFFFUL << RTC_BKP20R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP20R                     RTC_BKP20R_Msk

+

+/********************  Bits definition for RTC_BKP21R register  ***************/

+#define RTC_BKP21R_Pos                 (0U)

+#define RTC_BKP21R_Msk                 (0xFFFFFFFFUL << RTC_BKP21R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP21R                     RTC_BKP21R_Msk

+

+/********************  Bits definition for RTC_BKP22R register  ***************/

+#define RTC_BKP22R_Pos                 (0U)

+#define RTC_BKP22R_Msk                 (0xFFFFFFFFUL << RTC_BKP22R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP22R                     RTC_BKP22R_Msk

+

+/********************  Bits definition for RTC_BKP23R register  ***************/

+#define RTC_BKP23R_Pos                 (0U)

+#define RTC_BKP23R_Msk                 (0xFFFFFFFFUL << RTC_BKP23R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP23R                     RTC_BKP23R_Msk

+

+/********************  Bits definition for RTC_BKP24R register  ***************/

+#define RTC_BKP24R_Pos                 (0U)

+#define RTC_BKP24R_Msk                 (0xFFFFFFFFUL << RTC_BKP24R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP24R                     RTC_BKP24R_Msk

+

+/********************  Bits definition for RTC_BKP25R register  ***************/

+#define RTC_BKP25R_Pos                 (0U)

+#define RTC_BKP25R_Msk                 (0xFFFFFFFFUL << RTC_BKP25R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP25R                     RTC_BKP25R_Msk

+

+/********************  Bits definition for RTC_BKP26R register  ***************/

+#define RTC_BKP26R_Pos                 (0U)

+#define RTC_BKP26R_Msk                 (0xFFFFFFFFUL << RTC_BKP26R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP26R                     RTC_BKP26R_Msk

+

+/********************  Bits definition for RTC_BKP27R register  ***************/

+#define RTC_BKP27R_Pos                 (0U)

+#define RTC_BKP27R_Msk                 (0xFFFFFFFFUL << RTC_BKP27R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP27R                     RTC_BKP27R_Msk

+

+/********************  Bits definition for RTC_BKP28R register  ***************/

+#define RTC_BKP28R_Pos                 (0U)

+#define RTC_BKP28R_Msk                 (0xFFFFFFFFUL << RTC_BKP28R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP28R                     RTC_BKP28R_Msk

+

+/********************  Bits definition for RTC_BKP29R register  ***************/

+#define RTC_BKP29R_Pos                 (0U)

+#define RTC_BKP29R_Msk                 (0xFFFFFFFFUL << RTC_BKP29R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP29R                     RTC_BKP29R_Msk

+

+/********************  Bits definition for RTC_BKP30R register  ***************/

+#define RTC_BKP30R_Pos                 (0U)

+#define RTC_BKP30R_Msk                 (0xFFFFFFFFUL << RTC_BKP30R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP30R                     RTC_BKP30R_Msk

+

+/********************  Bits definition for RTC_BKP31R register  ***************/

+#define RTC_BKP31R_Pos                 (0U)

+#define RTC_BKP31R_Msk                 (0xFFFFFFFFUL << RTC_BKP31R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP31R                     RTC_BKP31R_Msk

+

+/******************** Number of backup registers ******************************/

+#define RTC_BKP_NUMBER_Pos             (5U)

+#define RTC_BKP_NUMBER_Msk             (0x1UL << RTC_BKP_NUMBER_Pos)           /*!< 0x00000020 */

+#define RTC_BKP_NUMBER                 RTC_BKP_NUMBER_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                              SPDIF-RX Interface                            */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for SPDIF_CR register  ******************/

+#define SPDIFRX_CR_SPDIFEN_Pos      (0U)

+#define SPDIFRX_CR_SPDIFEN_Msk      (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)          /*!< 0x00000003 */

+#define SPDIFRX_CR_SPDIFEN          SPDIFRX_CR_SPDIFEN_Msk                     /*!<Peripheral Block Enable                      */

+#define SPDIFRX_CR_RXDMAEN_Pos      (2U)

+#define SPDIFRX_CR_RXDMAEN_Msk      (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)          /*!< 0x00000004 */

+#define SPDIFRX_CR_RXDMAEN          SPDIFRX_CR_RXDMAEN_Msk                     /*!<Receiver DMA Enable for data flow            */

+#define SPDIFRX_CR_RXSTEO_Pos       (3U)

+#define SPDIFRX_CR_RXSTEO_Msk       (0x1UL << SPDIFRX_CR_RXSTEO_Pos)           /*!< 0x00000008 */

+#define SPDIFRX_CR_RXSTEO           SPDIFRX_CR_RXSTEO_Msk                      /*!<Stereo Mode                                  */

+#define SPDIFRX_CR_DRFMT_Pos        (4U)

+#define SPDIFRX_CR_DRFMT_Msk        (0x3UL << SPDIFRX_CR_DRFMT_Pos)            /*!< 0x00000030 */

+#define SPDIFRX_CR_DRFMT            SPDIFRX_CR_DRFMT_Msk                       /*!<RX Data format                               */

+#define SPDIFRX_CR_PMSK_Pos         (6U)

+#define SPDIFRX_CR_PMSK_Msk         (0x1UL << SPDIFRX_CR_PMSK_Pos)             /*!< 0x00000040 */

+#define SPDIFRX_CR_PMSK             SPDIFRX_CR_PMSK_Msk                        /*!<Mask Parity error bit                        */

+#define SPDIFRX_CR_VMSK_Pos         (7U)

+#define SPDIFRX_CR_VMSK_Msk         (0x1UL << SPDIFRX_CR_VMSK_Pos)             /*!< 0x00000080 */

+#define SPDIFRX_CR_VMSK             SPDIFRX_CR_VMSK_Msk                        /*!<Mask of Validity bit                         */

+#define SPDIFRX_CR_CUMSK_Pos        (8U)

+#define SPDIFRX_CR_CUMSK_Msk        (0x1UL << SPDIFRX_CR_CUMSK_Pos)            /*!< 0x00000100 */

+#define SPDIFRX_CR_CUMSK            SPDIFRX_CR_CUMSK_Msk                       /*!<Mask of channel status and user bits         */

+#define SPDIFRX_CR_PTMSK_Pos        (9U)

+#define SPDIFRX_CR_PTMSK_Msk        (0x1UL << SPDIFRX_CR_PTMSK_Pos)            /*!< 0x00000200 */

+#define SPDIFRX_CR_PTMSK            SPDIFRX_CR_PTMSK_Msk                       /*!<Mask of Preamble Type bits                   */

+#define SPDIFRX_CR_CBDMAEN_Pos      (10U)

+#define SPDIFRX_CR_CBDMAEN_Msk      (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)          /*!< 0x00000400 */

+#define SPDIFRX_CR_CBDMAEN          SPDIFRX_CR_CBDMAEN_Msk                     /*!<Control Buffer DMA ENable for control flow   */

+#define SPDIFRX_CR_CHSEL_Pos        (11U)

+#define SPDIFRX_CR_CHSEL_Msk        (0x1UL << SPDIFRX_CR_CHSEL_Pos)            /*!< 0x00000800 */

+#define SPDIFRX_CR_CHSEL            SPDIFRX_CR_CHSEL_Msk                       /*!<Channel Selection                            */

+#define SPDIFRX_CR_NBTR_Pos         (12U)

+#define SPDIFRX_CR_NBTR_Msk         (0x3UL << SPDIFRX_CR_NBTR_Pos)             /*!< 0x00003000 */

+#define SPDIFRX_CR_NBTR             SPDIFRX_CR_NBTR_Msk                        /*!<Maximum allowed re-tries during synchronization phase */

+#define SPDIFRX_CR_WFA_Pos          (14U)

+#define SPDIFRX_CR_WFA_Msk          (0x1UL << SPDIFRX_CR_WFA_Pos)              /*!< 0x00004000 */

+#define SPDIFRX_CR_WFA              SPDIFRX_CR_WFA_Msk                         /*!<Wait For Activity     */

+#define SPDIFRX_CR_INSEL_Pos        (16U)

+#define SPDIFRX_CR_INSEL_Msk        (0x7UL << SPDIFRX_CR_INSEL_Pos)            /*!< 0x00070000 */

+#define SPDIFRX_CR_INSEL            SPDIFRX_CR_INSEL_Msk                       /*!<SPDIF input selection */

+#define SPDIFRX_CR_CKSEN_Pos        (20U)

+#define SPDIFRX_CR_CKSEN_Msk        (0x1UL << SPDIFRX_CR_CKSEN_Pos)            /*!< 0x00100000 */

+#define SPDIFRX_CR_CKSEN            SPDIFRX_CR_CKSEN_Msk                       /*!<Symbol Clock Enable */

+#define SPDIFRX_CR_CKSBKPEN_Pos     (21U)

+#define SPDIFRX_CR_CKSBKPEN_Msk     (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)         /*!< 0x00200000 */

+#define SPDIFRX_CR_CKSBKPEN         SPDIFRX_CR_CKSBKPEN_Msk                    /*!<Backup Symbol Clock Enable */

+

+/*******************  Bit definition for SPDIFRX_IMR register  *******************/

+#define SPDIFRX_IMR_RXNEIE_Pos      (0U)

+#define SPDIFRX_IMR_RXNEIE_Msk      (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)          /*!< 0x00000001 */

+#define SPDIFRX_IMR_RXNEIE          SPDIFRX_IMR_RXNEIE_Msk                     /*!<RXNE interrupt enable                              */

+#define SPDIFRX_IMR_CSRNEIE_Pos     (1U)

+#define SPDIFRX_IMR_CSRNEIE_Msk     (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)         /*!< 0x00000002 */

+#define SPDIFRX_IMR_CSRNEIE         SPDIFRX_IMR_CSRNEIE_Msk                    /*!<Control Buffer Ready Interrupt Enable              */

+#define SPDIFRX_IMR_PERRIE_Pos      (2U)

+#define SPDIFRX_IMR_PERRIE_Msk      (0x1UL << SPDIFRX_IMR_PERRIE_Pos)          /*!< 0x00000004 */

+#define SPDIFRX_IMR_PERRIE          SPDIFRX_IMR_PERRIE_Msk                     /*!<Parity error interrupt enable                      */

+#define SPDIFRX_IMR_OVRIE_Pos       (3U)

+#define SPDIFRX_IMR_OVRIE_Msk       (0x1UL << SPDIFRX_IMR_OVRIE_Pos)           /*!< 0x00000008 */

+#define SPDIFRX_IMR_OVRIE           SPDIFRX_IMR_OVRIE_Msk                      /*!<Overrun error Interrupt Enable                     */

+#define SPDIFRX_IMR_SBLKIE_Pos      (4U)

+#define SPDIFRX_IMR_SBLKIE_Msk      (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)          /*!< 0x00000010 */

+#define SPDIFRX_IMR_SBLKIE          SPDIFRX_IMR_SBLKIE_Msk                     /*!<Synchronization Block Detected Interrupt Enable    */

+#define SPDIFRX_IMR_SYNCDIE_Pos     (5U)

+#define SPDIFRX_IMR_SYNCDIE_Msk     (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)         /*!< 0x00000020 */

+#define SPDIFRX_IMR_SYNCDIE         SPDIFRX_IMR_SYNCDIE_Msk                    /*!<Synchronization Done                               */

+#define SPDIFRX_IMR_IFEIE_Pos       (6U)

+#define SPDIFRX_IMR_IFEIE_Msk       (0x1UL << SPDIFRX_IMR_IFEIE_Pos)           /*!< 0x00000040 */

+#define SPDIFRX_IMR_IFEIE           SPDIFRX_IMR_IFEIE_Msk                      /*!<Serial Interface Error Interrupt Enable            */

+

+/*******************  Bit definition for SPDIFRX_SR register  *******************/

+#define SPDIFRX_SR_RXNE_Pos         (0U)

+#define SPDIFRX_SR_RXNE_Msk         (0x1UL << SPDIFRX_SR_RXNE_Pos)             /*!< 0x00000001 */

+#define SPDIFRX_SR_RXNE             SPDIFRX_SR_RXNE_Msk                        /*!<Read data register not empty                          */

+#define SPDIFRX_SR_CSRNE_Pos        (1U)

+#define SPDIFRX_SR_CSRNE_Msk        (0x1UL << SPDIFRX_SR_CSRNE_Pos)            /*!< 0x00000002 */

+#define SPDIFRX_SR_CSRNE            SPDIFRX_SR_CSRNE_Msk                       /*!<The Control Buffer register is not empty              */

+#define SPDIFRX_SR_PERR_Pos         (2U)

+#define SPDIFRX_SR_PERR_Msk         (0x1UL << SPDIFRX_SR_PERR_Pos)             /*!< 0x00000004 */

+#define SPDIFRX_SR_PERR             SPDIFRX_SR_PERR_Msk                        /*!<Parity error                                          */

+#define SPDIFRX_SR_OVR_Pos          (3U)

+#define SPDIFRX_SR_OVR_Msk          (0x1UL << SPDIFRX_SR_OVR_Pos)              /*!< 0x00000008 */

+#define SPDIFRX_SR_OVR              SPDIFRX_SR_OVR_Msk                         /*!<Overrun error                                         */

+#define SPDIFRX_SR_SBD_Pos          (4U)

+#define SPDIFRX_SR_SBD_Msk          (0x1UL << SPDIFRX_SR_SBD_Pos)              /*!< 0x00000010 */

+#define SPDIFRX_SR_SBD              SPDIFRX_SR_SBD_Msk                         /*!<Synchronization Block Detected                        */

+#define SPDIFRX_SR_SYNCD_Pos        (5U)

+#define SPDIFRX_SR_SYNCD_Msk        (0x1UL << SPDIFRX_SR_SYNCD_Pos)            /*!< 0x00000020 */

+#define SPDIFRX_SR_SYNCD            SPDIFRX_SR_SYNCD_Msk                       /*!<Synchronization Done                                  */

+#define SPDIFRX_SR_FERR_Pos         (6U)

+#define SPDIFRX_SR_FERR_Msk         (0x1UL << SPDIFRX_SR_FERR_Pos)             /*!< 0x00000040 */

+#define SPDIFRX_SR_FERR             SPDIFRX_SR_FERR_Msk                        /*!<Framing error                                         */

+#define SPDIFRX_SR_SERR_Pos         (7U)

+#define SPDIFRX_SR_SERR_Msk         (0x1UL << SPDIFRX_SR_SERR_Pos)             /*!< 0x00000080 */

+#define SPDIFRX_SR_SERR             SPDIFRX_SR_SERR_Msk                        /*!<Synchronization error                                 */

+#define SPDIFRX_SR_TERR_Pos         (8U)

+#define SPDIFRX_SR_TERR_Msk         (0x1UL << SPDIFRX_SR_TERR_Pos)             /*!< 0x00000100 */

+#define SPDIFRX_SR_TERR             SPDIFRX_SR_TERR_Msk                        /*!<Time-out error                                        */

+#define SPDIFRX_SR_WIDTH5_Pos       (16U)

+#define SPDIFRX_SR_WIDTH5_Msk       (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)        /*!< 0x7FFF0000 */

+#define SPDIFRX_SR_WIDTH5           SPDIFRX_SR_WIDTH5_Msk                      /*!<Duration of 5 symbols counted with spdif_clk          */

+

+/*******************  Bit definition for SPDIFRX_IFCR register  *******************/

+#define SPDIFRX_IFCR_PERRCF_Pos     (2U)

+#define SPDIFRX_IFCR_PERRCF_Msk     (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)         /*!< 0x00000004 */

+#define SPDIFRX_IFCR_PERRCF         SPDIFRX_IFCR_PERRCF_Msk                    /*!<Clears the Parity error flag                         */

+#define SPDIFRX_IFCR_OVRCF_Pos      (3U)

+#define SPDIFRX_IFCR_OVRCF_Msk      (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)          /*!< 0x00000008 */

+#define SPDIFRX_IFCR_OVRCF          SPDIFRX_IFCR_OVRCF_Msk                     /*!<Clears the Overrun error flag                        */

+#define SPDIFRX_IFCR_SBDCF_Pos      (4U)

+#define SPDIFRX_IFCR_SBDCF_Msk      (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)          /*!< 0x00000010 */

+#define SPDIFRX_IFCR_SBDCF          SPDIFRX_IFCR_SBDCF_Msk                     /*!<Clears the Synchronization Block Detected flag       */

+#define SPDIFRX_IFCR_SYNCDCF_Pos    (5U)

+#define SPDIFRX_IFCR_SYNCDCF_Msk    (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)        /*!< 0x00000020 */

+#define SPDIFRX_IFCR_SYNCDCF        SPDIFRX_IFCR_SYNCDCF_Msk                   /*!<Clears the Synchronization Done flag                 */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/

+#define SPDIFRX_DR0_DR_Pos          (0U)

+#define SPDIFRX_DR0_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)         /*!< 0x00FFFFFF */

+#define SPDIFRX_DR0_DR              SPDIFRX_DR0_DR_Msk                         /*!<Data value            */

+#define SPDIFRX_DR0_PE_Pos          (24U)

+#define SPDIFRX_DR0_PE_Msk          (0x1UL << SPDIFRX_DR0_PE_Pos)              /*!< 0x01000000 */

+#define SPDIFRX_DR0_PE              SPDIFRX_DR0_PE_Msk                         /*!<Parity Error bit      */

+#define SPDIFRX_DR0_V_Pos           (25U)

+#define SPDIFRX_DR0_V_Msk           (0x1UL << SPDIFRX_DR0_V_Pos)               /*!< 0x02000000 */

+#define SPDIFRX_DR0_V               SPDIFRX_DR0_V_Msk                          /*!<Validity bit          */

+#define SPDIFRX_DR0_U_Pos           (26U)

+#define SPDIFRX_DR0_U_Msk           (0x1UL << SPDIFRX_DR0_U_Pos)               /*!< 0x04000000 */

+#define SPDIFRX_DR0_U               SPDIFRX_DR0_U_Msk                          /*!<User bit              */

+#define SPDIFRX_DR0_C_Pos           (27U)

+#define SPDIFRX_DR0_C_Msk           (0x1UL << SPDIFRX_DR0_C_Pos)               /*!< 0x08000000 */

+#define SPDIFRX_DR0_C               SPDIFRX_DR0_C_Msk                          /*!<Channel Status bit    */

+#define SPDIFRX_DR0_PT_Pos          (28U)

+#define SPDIFRX_DR0_PT_Msk          (0x3UL << SPDIFRX_DR0_PT_Pos)              /*!< 0x30000000 */

+#define SPDIFRX_DR0_PT              SPDIFRX_DR0_PT_Msk                         /*!<Preamble Type         */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/

+#define SPDIFRX_DR1_DR_Pos          (8U)

+#define SPDIFRX_DR1_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)         /*!< 0xFFFFFF00 */

+#define SPDIFRX_DR1_DR              SPDIFRX_DR1_DR_Msk                         /*!<Data value            */

+#define SPDIFRX_DR1_PT_Pos          (4U)

+#define SPDIFRX_DR1_PT_Msk          (0x3UL << SPDIFRX_DR1_PT_Pos)              /*!< 0x00000030 */

+#define SPDIFRX_DR1_PT              SPDIFRX_DR1_PT_Msk                         /*!<Preamble Type         */

+#define SPDIFRX_DR1_C_Pos           (3U)

+#define SPDIFRX_DR1_C_Msk           (0x1UL << SPDIFRX_DR1_C_Pos)               /*!< 0x00000008 */

+#define SPDIFRX_DR1_C               SPDIFRX_DR1_C_Msk                          /*!<Channel Status bit    */

+#define SPDIFRX_DR1_U_Pos           (2U)

+#define SPDIFRX_DR1_U_Msk           (0x1UL << SPDIFRX_DR1_U_Pos)               /*!< 0x00000004 */

+#define SPDIFRX_DR1_U               SPDIFRX_DR1_U_Msk                          /*!<User bit              */

+#define SPDIFRX_DR1_V_Pos           (1U)

+#define SPDIFRX_DR1_V_Msk           (0x1UL << SPDIFRX_DR1_V_Pos)               /*!< 0x00000002 */

+#define SPDIFRX_DR1_V               SPDIFRX_DR1_V_Msk                          /*!<Validity bit          */

+#define SPDIFRX_DR1_PE_Pos          (0U)

+#define SPDIFRX_DR1_PE_Msk          (0x1UL << SPDIFRX_DR1_PE_Pos)              /*!< 0x00000001 */

+#define SPDIFRX_DR1_PE              SPDIFRX_DR1_PE_Msk                         /*!<Parity Error bit      */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/

+#define SPDIFRX_DR1_DRNL1_Pos       (16U)

+#define SPDIFRX_DR1_DRNL1_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)        /*!< 0xFFFF0000 */

+#define SPDIFRX_DR1_DRNL1           SPDIFRX_DR1_DRNL1_Msk                      /*!<Data value Channel B      */

+#define SPDIFRX_DR1_DRNL2_Pos       (0U)

+#define SPDIFRX_DR1_DRNL2_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)        /*!< 0x0000FFFF */

+#define SPDIFRX_DR1_DRNL2           SPDIFRX_DR1_DRNL2_Msk                      /*!<Data value Channel A      */

+

+/*******************  Bit definition for SPDIFRX_CSR register   *******************/

+#define SPDIFRX_CSR_USR_Pos         (0U)

+#define SPDIFRX_CSR_USR_Msk         (0xFFFFUL << SPDIFRX_CSR_USR_Pos)          /*!< 0x0000FFFF */

+#define SPDIFRX_CSR_USR             SPDIFRX_CSR_USR_Msk                        /*!<User data information           */

+#define SPDIFRX_CSR_CS_Pos          (16U)

+#define SPDIFRX_CSR_CS_Msk          (0xFFUL << SPDIFRX_CSR_CS_Pos)             /*!< 0x00FF0000 */

+#define SPDIFRX_CSR_CS              SPDIFRX_CSR_CS_Msk                         /*!<Channel A status information    */

+#define SPDIFRX_CSR_SOB_Pos         (24U)

+#define SPDIFRX_CSR_SOB_Msk         (0x1UL << SPDIFRX_CSR_SOB_Pos)             /*!< 0x01000000 */

+#define SPDIFRX_CSR_SOB             SPDIFRX_CSR_SOB_Msk                        /*!<Start Of Block                  */

+

+/*******************  Bit definition for SPDIFRX_DIR register    *******************/

+#define SPDIFRX_DIR_THI_Pos         (0U)

+#define SPDIFRX_DIR_THI_Msk         (0x1FFFUL << SPDIFRX_DIR_THI_Pos)          /*!< 0x00001FFF */

+#define SPDIFRX_DIR_THI             SPDIFRX_DIR_THI_Msk                        /*!<Threshold LOW      */

+#define SPDIFRX_DIR_TLO_Pos         (16U)

+#define SPDIFRX_DIR_TLO_Msk         (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)          /*!< 0x1FFF0000 */

+#define SPDIFRX_DIR_TLO             SPDIFRX_DIR_TLO_Msk                        /*!<Threshold HIGH     */

+

+/*******************  Bit definition for SPDIFRX_VERR register    *******************/

+#define SPDIFRX_VERR_MINREV_Pos     (0U)

+#define SPDIFRX_VERR_MINREV_Msk     (0xFUL << SPDIFRX_VERR_MINREV_Pos)         /*!< 0x0000000F */

+#define SPDIFRX_VERR_MINREV         SPDIFRX_VERR_MINREV_Msk                    /*!<SPDIFRX Minor revision     */

+#define SPDIFRX_VERR_MAJREV_Pos     (4U)

+#define SPDIFRX_VERR_MAJREV_Msk     (0xFUL << SPDIFRX_VERR_MAJREV_Pos)         /*!< 0x000000F0 */

+#define SPDIFRX_VERR_MAJREV         SPDIFRX_VERR_MAJREV_Msk                    /*!<SPDIFRX Major revision     */

+

+/*******************  Bit definition for SPDIFRX_IDR register    *******************/

+#define SPDIFRX_IDR_ID_Pos          (0U)

+#define SPDIFRX_IDR_ID_Msk          (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos)       /*!< 0xFFFFFFFF */

+#define SPDIFRX_IDR_ID              SPDIFRX_IDR_ID_Msk                         /*!<SPDIFRX identifier     */

+

+/*******************  Bit definition for SPDIFRX_SIDR register    *******************/

+#define SPDIFRX_SIDR_SID_Pos        (0U)

+#define SPDIFRX_SIDR_SID_Msk        (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos)     /*!< 0xFFFFFFFF */

+#define SPDIFRX_SIDR_SID            SPDIFRX_SIDR_SID_Msk                       /*!<Size of the memory region allocated to SPDIFRX registers */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          Serial Audio Interface                            */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  SAI VERSION  ********************************/

+#define SAI_VER_V2_X

+

+/********************  Bit definition for SAI_GCR register  *******************/

+#define SAI_GCR_SYNCIN_Pos         (0U)

+#define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000003 */

+#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */

+#define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */

+#define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */

+

+#define SAI_GCR_SYNCOUT_Pos        (4U)

+#define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000030 */

+#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */

+#define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */

+#define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */

+

+/*******************  Bit definition for SAI_xCR1 register  *******************/

+#define SAI_xCR1_MODE_Pos          (0U)

+#define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */

+#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */

+#define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */

+#define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */

+

+#define SAI_xCR1_PRTCFG_Pos        (2U)

+#define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */

+#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */

+#define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */

+#define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */

+

+#define SAI_xCR1_DS_Pos            (5U)

+#define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */

+#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */

+#define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */

+#define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */

+#define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */

+

+#define SAI_xCR1_LSBFIRST_Pos      (8U)

+#define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */

+#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */

+#define SAI_xCR1_CKSTR_Pos         (9U)

+#define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */

+#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */

+

+#define SAI_xCR1_SYNCEN_Pos        (10U)

+#define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */

+#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */

+#define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */

+#define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */

+

+#define SAI_xCR1_MONO_Pos          (12U)

+#define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */

+#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */

+#define SAI_xCR1_OUTDRIV_Pos       (13U)

+#define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */

+#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */

+#define SAI_xCR1_SAIEN_Pos         (16U)

+#define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */

+#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */

+#define SAI_xCR1_DMAEN_Pos         (17U)

+#define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */

+#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */

+#define SAI_xCR1_NODIV_Pos         (19U)

+#define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */

+#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */

+

+#define SAI_xCR1_MCKDIV_Pos        (20U)

+#define SAI_xCR1_MCKDIV_Msk        (0x3FUL << SAI_xCR1_MCKDIV_Pos)             /*!< 0x03F00000 */

+#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[5:0] (Master ClocK Divider)  */

+#define SAI_xCR1_MCKDIV_0          (0x01UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00100000 */

+#define SAI_xCR1_MCKDIV_1          (0x02UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00200000 */

+#define SAI_xCR1_MCKDIV_2          (0x04UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00400000 */

+#define SAI_xCR1_MCKDIV_3          (0x08UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00800000 */

+#define SAI_xCR1_MCKDIV_4          (0x10UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x01000000 */

+#define SAI_xCR1_MCKDIV_5          (0x20UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x02000000 */

+

+#define SAI_xCR1_MCKEN_Pos         (27U)

+#define SAI_xCR1_MCKEN_Msk         (0x1UL << SAI_xCR1_MCKEN_Pos)               /*!< 0x08000000 */

+#define SAI_xCR1_MCKEN             SAI_xCR1_MCKEN_Msk                          /*!<Master ClocK enable */

+

+#define SAI_xCR1_OSR_Pos           (26U)

+#define SAI_xCR1_OSR_Msk           (0x1UL << SAI_xCR1_OSR_Pos)                 /*!< 0x04000000 */

+#define SAI_xCR1_OSR               SAI_xCR1_OSR_Msk                            /*!<OverSampling Ratio for master clock  */

+

+/* Legacy define */

+#define  SAI_xCR1_NOMCK               SAI_xCR1_NODIV

+

+/*******************  Bit definition for SAI_xCR2 register  *******************/

+#define SAI_xCR2_FTH_Pos           (0U)

+#define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */

+#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */

+#define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */

+#define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */

+#define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */

+

+#define SAI_xCR2_FFLUSH_Pos        (3U)

+#define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */

+#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */

+#define SAI_xCR2_TRIS_Pos          (4U)

+#define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */

+#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */

+#define SAI_xCR2_MUTE_Pos          (5U)

+#define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */

+#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */

+#define SAI_xCR2_MUTEVAL_Pos       (6U)

+#define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */

+#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */

+

+#define SAI_xCR2_MUTECNT_Pos       (7U)

+#define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */

+#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */

+#define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */

+#define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */

+#define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */

+#define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */

+#define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */

+#define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */

+

+#define SAI_xCR2_CPL_Pos           (13U)

+#define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */

+#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */

+

+#define SAI_xCR2_COMP_Pos          (14U)

+#define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */

+#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */

+#define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */

+#define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */

+

+/******************  Bit definition for SAI_xFRCR register  *******************/

+#define SAI_xFRCR_FRL_Pos          (0U)

+#define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */

+#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](FRame Length)  */

+#define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */

+#define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */

+#define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */

+#define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */

+#define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */

+#define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */

+#define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */

+#define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */

+

+#define SAI_xFRCR_FSALL_Pos        (8U)

+#define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */

+#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FSALL[6:0] (Frame Synchronization Active Level Length)  */

+#define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */

+#define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */

+#define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */

+#define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */

+#define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */

+#define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */

+#define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */

+

+#define SAI_xFRCR_FSDEF_Pos        (16U)

+#define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */

+#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!<Frame Synchronization Definition  */

+#define SAI_xFRCR_FSPOL_Pos        (17U)

+#define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */

+#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */

+#define SAI_xFRCR_FSOFF_Pos        (18U)

+#define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */

+#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */

+

+/* Legacy define */

+#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL

+

+/******************  Bit definition for SAI_xSLOTR register  *******************/

+#define SAI_xSLOTR_FBOFF_Pos       (0U)

+#define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */

+#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FBOFF[4:0](First Bit Offset)  */

+#define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */

+#define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */

+#define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */

+#define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */

+#define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */

+

+#define SAI_xSLOTR_SLOTSZ_Pos      (6U)

+#define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */

+#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */

+#define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */

+#define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */

+

+#define SAI_xSLOTR_NBSLOT_Pos      (8U)

+#define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */

+#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */

+#define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */

+#define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */

+#define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */

+#define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */

+

+#define SAI_xSLOTR_SLOTEN_Pos      (16U)

+#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */

+#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */

+

+/*******************  Bit definition for SAI_xIMR register  *******************/

+#define SAI_xIMR_OVRUDRIE_Pos      (0U)

+#define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */

+#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */

+#define SAI_xIMR_MUTEDETIE_Pos     (1U)

+#define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */

+#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */

+#define SAI_xIMR_WCKCFGIE_Pos      (2U)

+#define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */

+#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */

+#define SAI_xIMR_FREQIE_Pos        (3U)

+#define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */

+#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */

+#define SAI_xIMR_CNRDYIE_Pos       (4U)

+#define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */

+#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */

+#define SAI_xIMR_AFSDETIE_Pos      (5U)

+#define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */

+#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */

+#define SAI_xIMR_LFSDETIE_Pos      (6U)

+#define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */

+#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */

+

+/********************  Bit definition for SAI_xSR register  *******************/

+#define SAI_xSR_OVRUDR_Pos         (0U)

+#define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */

+#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */

+#define SAI_xSR_MUTEDET_Pos        (1U)

+#define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */

+#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */

+#define SAI_xSR_WCKCFG_Pos         (2U)

+#define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */

+#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */

+#define SAI_xSR_FREQ_Pos           (3U)

+#define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */

+#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */

+#define SAI_xSR_CNRDY_Pos          (4U)

+#define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */

+#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */

+#define SAI_xSR_AFSDET_Pos         (5U)

+#define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */

+#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */

+#define SAI_xSR_LFSDET_Pos         (6U)

+#define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */

+#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */

+

+#define SAI_xSR_FLVL_Pos           (16U)

+#define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */

+#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */

+#define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */

+#define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */

+#define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */

+

+/******************  Bit definition for SAI_xCLRFR register  ******************/

+#define SAI_xCLRFR_COVRUDR_Pos     (0U)

+#define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */

+#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */

+#define SAI_xCLRFR_CMUTEDET_Pos    (1U)

+#define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */

+#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */

+#define SAI_xCLRFR_CWCKCFG_Pos     (2U)

+#define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */

+#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */

+#define SAI_xCLRFR_CFREQ_Pos       (3U)

+#define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */

+#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */

+#define SAI_xCLRFR_CCNRDY_Pos      (4U)

+#define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */

+#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */

+#define SAI_xCLRFR_CAFSDET_Pos     (5U)

+#define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */

+#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */

+#define SAI_xCLRFR_CLFSDET_Pos     (6U)

+#define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */

+#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */

+

+/******************  Bit definition for SAI_xDR register  *********************/

+#define SAI_xDR_DATA_Pos           (0U)

+#define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */

+#define SAI_xDR_DATA               SAI_xDR_DATA_Msk

+

+/*******************  Bit definition for SAI_PDMCR register  ******************/

+#define SAI_PDMCR_PDMEN_Pos        (0U)

+#define SAI_PDMCR_PDMEN_Msk        (0x1UL << SAI_PDMCR_PDMEN_Pos)              /*!< 0x00000001 */

+#define SAI_PDMCR_PDMEN            SAI_PDMCR_PDMEN_Msk                         /*!<PDM Enable                                          */

+

+#define SAI_PDMCR_MICNBR_Pos       (4U)

+#define SAI_PDMCR_MICNBR_Msk       (0x3UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000030 */

+#define SAI_PDMCR_MICNBR           SAI_PDMCR_MICNBR_Msk                        /*!<Number of microphones                               */

+#define SAI_PDMCR_MICNBR_0         (0x1UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000010 */

+#define SAI_PDMCR_MICNBR_1         (0x2UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000020 */

+

+#define SAI_PDMCR_CKEN1_Pos        (8U)

+#define SAI_PDMCR_CKEN1_Msk        (0x1UL << SAI_PDMCR_CKEN1_Pos)              /*!< 0x00000100 */

+#define SAI_PDMCR_CKEN1            SAI_PDMCR_CKEN1_Msk                         /*!<Clock enable of bitstream clock number 1            */

+#define SAI_PDMCR_CKEN2_Pos        (9U)

+#define SAI_PDMCR_CKEN2_Msk        (0x1UL << SAI_PDMCR_CKEN2_Pos)              /*!< 0x00000200 */

+#define SAI_PDMCR_CKEN2            SAI_PDMCR_CKEN2_Msk                         /*!<Clock enable of bitstream clock number 2            */

+#define SAI_PDMCR_CKEN3_Pos        (10U)

+#define SAI_PDMCR_CKEN3_Msk        (0x1UL << SAI_PDMCR_CKEN3_Pos)              /*!< 0x00000400 */

+#define SAI_PDMCR_CKEN3            SAI_PDMCR_CKEN3_Msk                         /*!<Clock enable of bitstream clock number 3            */

+#define SAI_PDMCR_CKEN4_Pos        (11U)

+#define SAI_PDMCR_CKEN4_Msk        (0x1UL << SAI_PDMCR_CKEN4_Pos)              /*!< 0x00000800 */

+#define SAI_PDMCR_CKEN4            SAI_PDMCR_CKEN4_Msk                         /*!<Clock enable of bitstream clock number 4            */

+

+/******************  Bit definition for SAI_PDMDLY register  ******************/

+#define SAI_PDMDLY_DLYM1L_Pos      (0U)

+#define SAI_PDMDLY_DLYM1L_Msk      (0x7UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000007 */

+#define SAI_PDMDLY_DLYM1L          SAI_PDMDLY_DLYM1L_Msk                       /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */

+#define SAI_PDMDLY_DLYM1L_0        (0x1UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000001 */

+#define SAI_PDMDLY_DLYM1L_1        (0x2UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000002 */

+#define SAI_PDMDLY_DLYM1L_2        (0x4UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000004 */

+

+#define SAI_PDMDLY_DLYM1R_Pos      (4U)

+#define SAI_PDMDLY_DLYM1R_Msk      (0x7UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000070 */

+#define SAI_PDMDLY_DLYM1R          SAI_PDMDLY_DLYM1R_Msk                       /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */

+#define SAI_PDMDLY_DLYM1R_0        (0x1UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000010 */

+#define SAI_PDMDLY_DLYM1R_1        (0x2UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000020 */

+#define SAI_PDMDLY_DLYM1R_2        (0x4UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000040 */

+

+#define SAI_PDMDLY_DLYM2L_Pos      (8U)

+#define SAI_PDMDLY_DLYM2L_Msk      (0x7UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000700 */

+#define SAI_PDMDLY_DLYM2L          SAI_PDMDLY_DLYM2L_Msk                       /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */

+#define SAI_PDMDLY_DLYM2L_0        (0x1UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000100 */

+#define SAI_PDMDLY_DLYM2L_1        (0x2UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000200 */

+#define SAI_PDMDLY_DLYM2L_2        (0x4UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000400 */

+

+#define SAI_PDMDLY_DLYM2R_Pos      (12U)

+#define SAI_PDMDLY_DLYM2R_Msk      (0x7UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00007000 */

+#define SAI_PDMDLY_DLYM2R          SAI_PDMDLY_DLYM2R_Msk                       /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/

+#define SAI_PDMDLY_DLYM2R_0        (0x1UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00001000 */

+#define SAI_PDMDLY_DLYM2R_1        (0x2UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00002000 */

+#define SAI_PDMDLY_DLYM2R_2        (0x4UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00004000 */

+

+#define SAI_PDMDLY_DLYM3L_Pos      (16U)

+#define SAI_PDMDLY_DLYM3L_Msk      (0x7UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00070000 */

+#define SAI_PDMDLY_DLYM3L          SAI_PDMDLY_DLYM3L_Msk                       /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/

+#define SAI_PDMDLY_DLYM3L_0        (0x1UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00010000 */

+#define SAI_PDMDLY_DLYM3L_1        (0x2UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00020000 */

+#define SAI_PDMDLY_DLYM3L_2        (0x4UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00040000 */

+

+#define SAI_PDMDLY_DLYM3R_Pos      (20U)

+#define SAI_PDMDLY_DLYM3R_Msk      (0x7UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00700000 */

+#define SAI_PDMDLY_DLYM3R          SAI_PDMDLY_DLYM3R_Msk                       /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/

+#define SAI_PDMDLY_DLYM3R_0        (0x1UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00100000 */

+#define SAI_PDMDLY_DLYM3R_1        (0x2UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00200000 */

+#define SAI_PDMDLY_DLYM3R_2        (0x4UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00400000 */

+

+#define SAI_PDMDLY_DLYM4L_Pos      (24U)

+#define SAI_PDMDLY_DLYM4L_Msk      (0x7UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x07000000 */

+#define SAI_PDMDLY_DLYM4L          SAI_PDMDLY_DLYM4L_Msk                       /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/

+#define SAI_PDMDLY_DLYM4L_0        (0x1UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x01000000 */

+#define SAI_PDMDLY_DLYM4L_1        (0x2UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x02000000 */

+#define SAI_PDMDLY_DLYM4L_2        (0x4UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x04000000 */

+

+#define SAI_PDMDLY_DLYM4R_Pos      (28U)

+#define SAI_PDMDLY_DLYM4R_Msk      (0x7UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x70000000 */

+#define SAI_PDMDLY_DLYM4R          SAI_PDMDLY_DLYM4R_Msk                       /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/

+#define SAI_PDMDLY_DLYM4R_0        (0x1UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x10000000 */

+#define SAI_PDMDLY_DLYM4R_1        (0x2UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x20000000 */

+#define SAI_PDMDLY_DLYM4R_2        (0x4UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x40000000 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           SDMMC Interface                                  */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for SDMMC_POWER register  ******************/

+#define SDMMC_POWER_PWRCTRL_Pos          (0U)

+#define SDMMC_POWER_PWRCTRL_Msk          (0x3UL << SDMMC_POWER_PWRCTRL_Pos)    /*!< 0x00000003 */

+#define SDMMC_POWER_PWRCTRL              SDMMC_POWER_PWRCTRL_Msk               /*!<PWRCTRL[1:0] bits (Power supply control bits) */

+#define SDMMC_POWER_PWRCTRL_0            (0x1UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000001 */

+#define SDMMC_POWER_PWRCTRL_1            (0x2UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000002 */

+#define SDMMC_POWER_VSWITCH_Pos          (2U)

+#define SDMMC_POWER_VSWITCH_Msk          (0x1UL << SDMMC_POWER_VSWITCH_Pos)    /*!< 0x00000004 */

+#define SDMMC_POWER_VSWITCH              SDMMC_POWER_VSWITCH_Msk               /*!<Voltage switch sequence start */

+#define SDMMC_POWER_VSWITCHEN_Pos        (3U)

+#define SDMMC_POWER_VSWITCHEN_Msk        (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)  /*!< 0x00000008 */

+#define SDMMC_POWER_VSWITCHEN            SDMMC_POWER_VSWITCHEN_Msk             /*!<Voltage switch procedure enable */

+#define SDMMC_POWER_DIRPOL_Pos           (4U)

+#define SDMMC_POWER_DIRPOL_Msk           (0x1UL << SDMMC_POWER_DIRPOL_Pos)     /*!< 0x00000010 */

+#define SDMMC_POWER_DIRPOL               SDMMC_POWER_DIRPOL_Msk                /*!<Data and Command direction signals polarity selection */

+

+/******************  Bit definition for SDMMC_CLKCR register  ******************/

+#define SDMMC_CLKCR_CLKDIV_Pos           (0U)

+#define SDMMC_CLKCR_CLKDIV_Msk           (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)   /*!< 0x000003FF */

+#define SDMMC_CLKCR_CLKDIV               SDMMC_CLKCR_CLKDIV_Msk                /*!<Clock divide factor             */

+#define SDMMC_CLKCR_PWRSAV_Pos           (12U)

+#define SDMMC_CLKCR_PWRSAV_Msk           (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)     /*!< 0x00001000 */

+#define SDMMC_CLKCR_PWRSAV               SDMMC_CLKCR_PWRSAV_Msk                /*!<Power saving configuration bit  */

+

+#define SDMMC_CLKCR_WIDBUS_Pos           (14U)

+#define SDMMC_CLKCR_WIDBUS_Msk           (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)     /*!< 0x0000C000 */

+#define SDMMC_CLKCR_WIDBUS               SDMMC_CLKCR_WIDBUS_Msk                /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */

+#define SDMMC_CLKCR_WIDBUS_0             (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00004000 */

+#define SDMMC_CLKCR_WIDBUS_1             (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00008000 */

+

+#define SDMMC_CLKCR_NEGEDGE_Pos          (16U)

+#define SDMMC_CLKCR_NEGEDGE_Msk          (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)    /*!< 0x00010000 */

+#define SDMMC_CLKCR_NEGEDGE              SDMMC_CLKCR_NEGEDGE_Msk               /*!<SDMMC_CK dephasing selection bit */

+#define SDMMC_CLKCR_HWFC_EN_Pos          (17U)

+#define SDMMC_CLKCR_HWFC_EN_Msk          (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)    /*!< 0x00020000 */

+#define SDMMC_CLKCR_HWFC_EN              SDMMC_CLKCR_HWFC_EN_Msk               /*!<HW Flow Control enable           */

+#define SDMMC_CLKCR_DDR_Pos              (18U)

+#define SDMMC_CLKCR_DDR_Msk              (0x1UL << SDMMC_CLKCR_DDR_Pos)        /*!< 0x00040000 */

+#define SDMMC_CLKCR_DDR                  SDMMC_CLKCR_DDR_Msk                   /*!<Data rate signaling selection    */

+#define SDMMC_CLKCR_BUSSPEED_Pos         (19U)

+#define SDMMC_CLKCR_BUSSPEED_Msk         (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)   /*!< 0x00080000 */

+#define SDMMC_CLKCR_BUSSPEED             SDMMC_CLKCR_BUSSPEED_Msk              /*!<Bus speed mode selection         */

+#define SDMMC_CLKCR_SELCLKRX_Pos         (20U)

+#define SDMMC_CLKCR_SELCLKRX_Msk         (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)   /*!< 0x00300000 */

+#define SDMMC_CLKCR_SELCLKRX             SDMMC_CLKCR_SELCLKRX_Msk              /*!<SELCLKRX[1:0] bits (Receive clock selection) */

+#define SDMMC_CLKCR_SELCLKRX_0           (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00100000 */

+#define SDMMC_CLKCR_SELCLKRX_1           (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00200000 */

+

+/*******************  Bit definition for SDMMC_ARG register  *******************/

+#define SDMMC_ARG_CMDARG_Pos             (0U)

+#define SDMMC_ARG_CMDARG_Msk             (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_ARG_CMDARG                 SDMMC_ARG_CMDARG_Msk                  /*!<Command argument */

+

+/*******************  Bit definition for SDMMC_CMD register  *******************/

+#define SDMMC_CMD_CMDINDEX_Pos           (0U)

+#define SDMMC_CMD_CMDINDEX_Msk           (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)    /*!< 0x0000003F */

+#define SDMMC_CMD_CMDINDEX               SDMMC_CMD_CMDINDEX_Msk                /*!<Command Index                               */

+#define SDMMC_CMD_CMDTRANS_Pos           (6U)

+#define SDMMC_CMD_CMDTRANS_Msk           (0x1UL << SDMMC_CMD_CMDTRANS_Pos)     /*!< 0x00000040 */

+#define SDMMC_CMD_CMDTRANS               SDMMC_CMD_CMDTRANS_Msk                /*!<CPSM Treats command as a Data Transfer      */

+#define SDMMC_CMD_CMDSTOP_Pos            (7U)

+#define SDMMC_CMD_CMDSTOP_Msk            (0x1UL << SDMMC_CMD_CMDSTOP_Pos)      /*!< 0x00000080 */

+#define SDMMC_CMD_CMDSTOP                SDMMC_CMD_CMDSTOP_Msk                 /*!<CPSM Treats command as a Stop               */

+

+#define SDMMC_CMD_WAITRESP_Pos           (8U)

+#define SDMMC_CMD_WAITRESP_Msk           (0x3UL << SDMMC_CMD_WAITRESP_Pos)     /*!< 0x00000300 */

+#define SDMMC_CMD_WAITRESP               SDMMC_CMD_WAITRESP_Msk                /*!<WAITRESP[1:0] bits (Wait for response bits) */

+#define SDMMC_CMD_WAITRESP_0             (0x1UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000100 */

+#define SDMMC_CMD_WAITRESP_1             (0x2UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000200 */

+

+#define SDMMC_CMD_WAITINT_Pos            (10U)

+#define SDMMC_CMD_WAITINT_Msk            (0x1UL << SDMMC_CMD_WAITINT_Pos)      /*!< 0x00000400 */

+#define SDMMC_CMD_WAITINT                SDMMC_CMD_WAITINT_Msk                 /*!<CPSM Waits for Interrupt Request                               */

+#define SDMMC_CMD_WAITPEND_Pos           (11U)

+#define SDMMC_CMD_WAITPEND_Msk           (0x1UL << SDMMC_CMD_WAITPEND_Pos)     /*!< 0x00000800 */

+#define SDMMC_CMD_WAITPEND               SDMMC_CMD_WAITPEND_Msk                /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */

+#define SDMMC_CMD_CPSMEN_Pos             (12U)

+#define SDMMC_CMD_CPSMEN_Msk             (0x1UL << SDMMC_CMD_CPSMEN_Pos)       /*!< 0x00001000 */

+#define SDMMC_CMD_CPSMEN                 SDMMC_CMD_CPSMEN_Msk                  /*!<Command path state machine (CPSM) Enable bit                   */

+#define SDMMC_CMD_DTHOLD_Pos             (13U)

+#define SDMMC_CMD_DTHOLD_Msk             (0x1UL << SDMMC_CMD_DTHOLD_Pos)       /*!< 0x00002000 */

+#define SDMMC_CMD_DTHOLD                 SDMMC_CMD_DTHOLD_Msk                  /*!<Hold new data block transmission and reception in the DPSM     */

+#define SDMMC_CMD_BOOTMODE_Pos           (14U)

+#define SDMMC_CMD_BOOTMODE_Msk           (0x1UL << SDMMC_CMD_BOOTMODE_Pos)     /*!< 0x00004000 */

+#define SDMMC_CMD_BOOTMODE               SDMMC_CMD_BOOTMODE_Msk                /*!<Boot mode                                                      */

+#define SDMMC_CMD_BOOTEN_Pos             (15U)

+#define SDMMC_CMD_BOOTEN_Msk             (0x1UL << SDMMC_CMD_BOOTEN_Pos)       /*!< 0x00008000 */

+#define SDMMC_CMD_BOOTEN                 SDMMC_CMD_BOOTEN_Msk                  /*!<Enable Boot mode procedure                                     */

+#define SDMMC_CMD_CMDSUSPEND_Pos         (16U)

+#define SDMMC_CMD_CMDSUSPEND_Msk         (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)   /*!< 0x00010000 */

+#define SDMMC_CMD_CMDSUSPEND             SDMMC_CMD_CMDSUSPEND_Msk              /*!<CPSM Treats command as a Suspend or Resume command             */

+

+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/

+#define SDMMC_RESPCMD_RESPCMD_Pos        (0U)

+#define SDMMC_RESPCMD_RESPCMD_Msk        (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */

+#define SDMMC_RESPCMD_RESPCMD            SDMMC_RESPCMD_RESPCMD_Msk             /*!<Response command index */

+

+/******************  Bit definition for SDMMC_RESP0 register  ******************/

+#define SDMMC_RESP0_CARDSTATUS0_Pos      (0U)

+#define SDMMC_RESP0_CARDSTATUS0_Msk      (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP0_CARDSTATUS0          SDMMC_RESP0_CARDSTATUS0_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP1 register  ******************/

+#define SDMMC_RESP1_CARDSTATUS1_Pos      (0U)

+#define SDMMC_RESP1_CARDSTATUS1_Msk      (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP1_CARDSTATUS1          SDMMC_RESP1_CARDSTATUS1_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP2 register  ******************/

+#define SDMMC_RESP2_CARDSTATUS2_Pos      (0U)

+#define SDMMC_RESP2_CARDSTATUS2_Msk      (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP2_CARDSTATUS2          SDMMC_RESP2_CARDSTATUS2_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP3 register  ******************/

+#define SDMMC_RESP3_CARDSTATUS3_Pos      (0U)

+#define SDMMC_RESP3_CARDSTATUS3_Msk      (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP3_CARDSTATUS3          SDMMC_RESP3_CARDSTATUS3_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP4 register  ******************/

+#define SDMMC_RESP4_CARDSTATUS4_Pos      (0U)

+#define SDMMC_RESP4_CARDSTATUS4_Msk      (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP4_CARDSTATUS4          SDMMC_RESP4_CARDSTATUS4_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_DTIMER register  *****************/

+#define SDMMC_DTIMER_DATATIME_Pos        (0U)

+#define SDMMC_DTIMER_DATATIME_Msk        (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_DTIMER_DATATIME            SDMMC_DTIMER_DATATIME_Msk             /*!<Data timeout period. */

+

+/******************  Bit definition for SDMMC_DLEN register  *******************/

+#define SDMMC_DLEN_DATALENGTH_Pos        (0U)

+#define SDMMC_DLEN_DATALENGTH_Msk        (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_DLEN_DATALENGTH            SDMMC_DLEN_DATALENGTH_Msk             /*!<Data length value    */

+

+/******************  Bit definition for SDMMC_DCTRL register  ******************/

+#define SDMMC_DCTRL_DTEN_Pos             (0U)

+#define SDMMC_DCTRL_DTEN_Msk             (0x1UL << SDMMC_DCTRL_DTEN_Pos)       /*!< 0x00000001 */

+#define SDMMC_DCTRL_DTEN                 SDMMC_DCTRL_DTEN_Msk                  /*!<Data transfer enabled bit                */

+#define SDMMC_DCTRL_DTDIR_Pos            (1U)

+#define SDMMC_DCTRL_DTDIR_Msk            (0x1UL << SDMMC_DCTRL_DTDIR_Pos)      /*!< 0x00000002 */

+#define SDMMC_DCTRL_DTDIR                SDMMC_DCTRL_DTDIR_Msk                 /*!<Data transfer direction selection        */

+#define SDMMC_DCTRL_DTMODE_Pos           (2U)

+#define SDMMC_DCTRL_DTMODE_Msk           (0x3UL << SDMMC_DCTRL_DTMODE_Pos)     /*!< 0x0000000C */

+#define SDMMC_DCTRL_DTMODE               SDMMC_DCTRL_DTMODE_Msk                /*!<DTMODE[1:0] Data transfer mode selection */

+#define SDMMC_DCTRL_DTMODE_0             (0x1UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000004 */

+#define SDMMC_DCTRL_DTMODE_1             (0x2UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000008 */

+

+#define SDMMC_DCTRL_DBLOCKSIZE_Pos       (4U)

+#define SDMMC_DCTRL_DBLOCKSIZE_Msk       (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */

+#define SDMMC_DCTRL_DBLOCKSIZE           SDMMC_DCTRL_DBLOCKSIZE_Msk            /*!<DBLOCKSIZE[3:0] bits (Data block size) */

+#define SDMMC_DCTRL_DBLOCKSIZE_0         (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000010 */

+#define SDMMC_DCTRL_DBLOCKSIZE_1         (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000020 */

+#define SDMMC_DCTRL_DBLOCKSIZE_2         (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000040 */

+#define SDMMC_DCTRL_DBLOCKSIZE_3         (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000080 */

+

+#define SDMMC_DCTRL_RWSTART_Pos          (8U)

+#define SDMMC_DCTRL_RWSTART_Msk          (0x1UL << SDMMC_DCTRL_RWSTART_Pos)    /*!< 0x00000100 */

+#define SDMMC_DCTRL_RWSTART              SDMMC_DCTRL_RWSTART_Msk               /*!<Read wait start                                 */

+#define SDMMC_DCTRL_RWSTOP_Pos           (9U)

+#define SDMMC_DCTRL_RWSTOP_Msk           (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)     /*!< 0x00000200 */

+#define SDMMC_DCTRL_RWSTOP               SDMMC_DCTRL_RWSTOP_Msk                /*!<Read wait stop                                  */

+#define SDMMC_DCTRL_RWMOD_Pos            (10U)

+#define SDMMC_DCTRL_RWMOD_Msk            (0x1UL << SDMMC_DCTRL_RWMOD_Pos)      /*!< 0x00000400 */

+#define SDMMC_DCTRL_RWMOD                SDMMC_DCTRL_RWMOD_Msk                 /*!<Read wait mode                                  */

+#define SDMMC_DCTRL_SDIOEN_Pos           (11U)

+#define SDMMC_DCTRL_SDIOEN_Msk           (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)     /*!< 0x00000800 */

+#define SDMMC_DCTRL_SDIOEN               SDMMC_DCTRL_SDIOEN_Msk                /*!<SD I/O enable functions                         */

+#define SDMMC_DCTRL_BOOTACKEN_Pos        (12U)

+#define SDMMC_DCTRL_BOOTACKEN_Msk        (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)  /*!< 0x00001000 */

+#define SDMMC_DCTRL_BOOTACKEN            SDMMC_DCTRL_BOOTACKEN_Msk             /*!<Enable the reception of the Boot Acknowledgment */

+#define SDMMC_DCTRL_FIFORST_Pos          (13U)

+#define SDMMC_DCTRL_FIFORST_Msk          (0x1UL << SDMMC_DCTRL_FIFORST_Pos)    /*!< 0x00002000 */

+#define SDMMC_DCTRL_FIFORST              SDMMC_DCTRL_FIFORST_Msk               /*!<FIFO reset                                      */

+

+/******************  Bit definition for SDMMC_DCOUNT register  *****************/

+#define SDMMC_DCOUNT_DATACOUNT_Pos       (0U)

+#define SDMMC_DCOUNT_DATACOUNT_Msk       (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_DCOUNT_DATACOUNT           SDMMC_DCOUNT_DATACOUNT_Msk            /*!<Data count value */

+

+/******************  Bit definition for SDMMC_STA register  ********************/

+#define SDMMC_STA_CCRCFAIL_Pos           (0U)

+#define SDMMC_STA_CCRCFAIL_Msk           (0x1UL << SDMMC_STA_CCRCFAIL_Pos)     /*!< 0x00000001 */

+#define SDMMC_STA_CCRCFAIL               SDMMC_STA_CCRCFAIL_Msk                /*!<Command response received (CRC check failed)  */

+#define SDMMC_STA_DCRCFAIL_Pos           (1U)

+#define SDMMC_STA_DCRCFAIL_Msk           (0x1UL << SDMMC_STA_DCRCFAIL_Pos)     /*!< 0x00000002 */

+#define SDMMC_STA_DCRCFAIL               SDMMC_STA_DCRCFAIL_Msk                /*!<Data block sent/received (CRC check failed)   */

+#define SDMMC_STA_CTIMEOUT_Pos           (2U)

+#define SDMMC_STA_CTIMEOUT_Msk           (0x1UL << SDMMC_STA_CTIMEOUT_Pos)     /*!< 0x00000004 */

+#define SDMMC_STA_CTIMEOUT               SDMMC_STA_CTIMEOUT_Msk                /*!<Command response timeout                      */

+#define SDMMC_STA_DTIMEOUT_Pos           (3U)

+#define SDMMC_STA_DTIMEOUT_Msk           (0x1UL << SDMMC_STA_DTIMEOUT_Pos)     /*!< 0x00000008 */

+#define SDMMC_STA_DTIMEOUT               SDMMC_STA_DTIMEOUT_Msk                /*!<Data timeout                                  */

+#define SDMMC_STA_TXUNDERR_Pos           (4U)

+#define SDMMC_STA_TXUNDERR_Msk           (0x1UL << SDMMC_STA_TXUNDERR_Pos)     /*!< 0x00000010 */

+#define SDMMC_STA_TXUNDERR               SDMMC_STA_TXUNDERR_Msk                /*!<Transmit FIFO underrun error                  */

+#define SDMMC_STA_RXOVERR_Pos            (5U)

+#define SDMMC_STA_RXOVERR_Msk            (0x1UL << SDMMC_STA_RXOVERR_Pos)      /*!< 0x00000020 */

+#define SDMMC_STA_RXOVERR                SDMMC_STA_RXOVERR_Msk                 /*!<Received FIFO overrun error                   */

+#define SDMMC_STA_CMDREND_Pos            (6U)

+#define SDMMC_STA_CMDREND_Msk            (0x1UL << SDMMC_STA_CMDREND_Pos)      /*!< 0x00000040 */

+#define SDMMC_STA_CMDREND                SDMMC_STA_CMDREND_Msk                 /*!<Command response received (CRC check passed)  */

+#define SDMMC_STA_CMDSENT_Pos            (7U)

+#define SDMMC_STA_CMDSENT_Msk            (0x1UL << SDMMC_STA_CMDSENT_Pos)      /*!< 0x00000080 */

+#define SDMMC_STA_CMDSENT                SDMMC_STA_CMDSENT_Msk                 /*!<Command sent (no response required)           */

+#define SDMMC_STA_DATAEND_Pos            (8U)

+#define SDMMC_STA_DATAEND_Msk            (0x1UL << SDMMC_STA_DATAEND_Pos)      /*!< 0x00000100 */

+#define SDMMC_STA_DATAEND                SDMMC_STA_DATAEND_Msk                 /*!<Data end (data counter, SDIDCOUNT, is zero)   */

+#define SDMMC_STA_DHOLD_Pos              (9U)

+#define SDMMC_STA_DHOLD_Msk              (0x1UL << SDMMC_STA_DHOLD_Pos)        /*!< 0x00000200 */

+#define SDMMC_STA_DHOLD                  SDMMC_STA_DHOLD_Msk                   /*!<Data transfer Hold                                                      */

+#define SDMMC_STA_DBCKEND_Pos            (10U)

+#define SDMMC_STA_DBCKEND_Msk            (0x1UL << SDMMC_STA_DBCKEND_Pos)      /*!< 0x00000400 */

+#define SDMMC_STA_DBCKEND                SDMMC_STA_DBCKEND_Msk                 /*!<Data block sent/received (CRC check passed)   */

+#define SDMMC_STA_DABORT_Pos             (11U)

+#define SDMMC_STA_DABORT_Msk             (0x1UL << SDMMC_STA_DABORT_Pos)       /*!< 0x00000800 */

+#define SDMMC_STA_DABORT                 SDMMC_STA_DABORT_Msk                  /*!<Data transfer aborted by CMD12                                          */

+#define SDMMC_STA_DPSMACT_Pos            (12U)

+#define SDMMC_STA_DPSMACT_Msk            (0x1UL << SDMMC_STA_DPSMACT_Pos)      /*!< 0x00001000 */

+#define SDMMC_STA_DPSMACT                SDMMC_STA_DPSMACT_Msk                 /*!<Data path state machine active                                       */

+#define SDMMC_STA_CPSMACT_Pos            (13U)

+#define SDMMC_STA_CPSMACT_Msk            (0x1UL << SDMMC_STA_CPSMACT_Pos)      /*!< 0x00002000 */

+#define SDMMC_STA_CPSMACT                SDMMC_STA_CPSMACT_Msk                 /*!<Command path state machine active                                          */

+#define SDMMC_STA_TXFIFOHE_Pos           (14U)

+#define SDMMC_STA_TXFIFOHE_Msk           (0x1UL << SDMMC_STA_TXFIFOHE_Pos)     /*!< 0x00004000 */

+#define SDMMC_STA_TXFIFOHE               SDMMC_STA_TXFIFOHE_Msk                /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */

+#define SDMMC_STA_RXFIFOHF_Pos           (15U)

+#define SDMMC_STA_RXFIFOHF_Msk           (0x1UL << SDMMC_STA_RXFIFOHF_Pos)     /*!< 0x00008000 */

+#define SDMMC_STA_RXFIFOHF               SDMMC_STA_RXFIFOHF_Msk                /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */

+#define SDMMC_STA_TXFIFOF_Pos            (16U)

+#define SDMMC_STA_TXFIFOF_Msk            (0x1UL << SDMMC_STA_TXFIFOF_Pos)      /*!< 0x00010000 */

+#define SDMMC_STA_TXFIFOF                SDMMC_STA_TXFIFOF_Msk                 /*!<Transmit FIFO full                            */

+#define SDMMC_STA_RXFIFOF_Pos            (17U)

+#define SDMMC_STA_RXFIFOF_Msk            (0x1UL << SDMMC_STA_RXFIFOF_Pos)      /*!< 0x00020000 */

+#define SDMMC_STA_RXFIFOF                SDMMC_STA_RXFIFOF_Msk                 /*!<Receive FIFO full                             */

+#define SDMMC_STA_TXFIFOE_Pos            (18U)

+#define SDMMC_STA_TXFIFOE_Msk            (0x1UL << SDMMC_STA_TXFIFOE_Pos)      /*!< 0x00040000 */

+#define SDMMC_STA_TXFIFOE                SDMMC_STA_TXFIFOE_Msk                 /*!<Transmit FIFO empty                           */

+#define SDMMC_STA_RXFIFOE_Pos            (19U)

+#define SDMMC_STA_RXFIFOE_Msk            (0x1UL << SDMMC_STA_RXFIFOE_Pos)      /*!< 0x00080000 */

+#define SDMMC_STA_RXFIFOE                SDMMC_STA_RXFIFOE_Msk                 /*!<Receive FIFO empty                            */

+#define SDMMC_STA_BUSYD0_Pos             (20U)

+#define SDMMC_STA_BUSYD0_Msk             (0x1UL << SDMMC_STA_BUSYD0_Pos)       /*!< 0x00100000 */

+#define SDMMC_STA_BUSYD0                 SDMMC_STA_BUSYD0_Msk                  /*!<Inverted value of SDMMC_D0 line (Busy)                                  */

+#define SDMMC_STA_BUSYD0END_Pos          (21U)

+#define SDMMC_STA_BUSYD0END_Msk          (0x1UL << SDMMC_STA_BUSYD0END_Pos)    /*!< 0x00200000 */

+#define SDMMC_STA_BUSYD0END              SDMMC_STA_BUSYD0END_Msk               /*!<End of SDMMC_D0 Busy following a CMD response detected                  */

+#define SDMMC_STA_SDIOIT_Pos             (22U)

+#define SDMMC_STA_SDIOIT_Msk             (0x1UL << SDMMC_STA_SDIOIT_Pos)       /*!< 0x00400000 */

+#define SDMMC_STA_SDIOIT                 SDMMC_STA_SDIOIT_Msk                  /*!<SDIO interrupt received                                                 */

+#define SDMMC_STA_ACKFAIL_Pos            (23U)

+#define SDMMC_STA_ACKFAIL_Msk            (0x1UL << SDMMC_STA_ACKFAIL_Pos)      /*!< 0x00800000 */

+#define SDMMC_STA_ACKFAIL                SDMMC_STA_ACKFAIL_Msk                 /*!<Boot Acknowledgment received (BootAck check fail)                       */

+#define SDMMC_STA_ACKTIMEOUT_Pos         (24U)

+#define SDMMC_STA_ACKTIMEOUT_Msk         (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)   /*!< 0x01000000 */

+#define SDMMC_STA_ACKTIMEOUT             SDMMC_STA_ACKTIMEOUT_Msk              /*!<Boot Acknowledgment timeout                                             */

+#define SDMMC_STA_VSWEND_Pos             (25U)

+#define SDMMC_STA_VSWEND_Msk             (0x1UL << SDMMC_STA_VSWEND_Pos)       /*!< 0x02000000 */

+#define SDMMC_STA_VSWEND                 SDMMC_STA_VSWEND_Msk                  /*!<Voltage switch critical timing section completion                       */

+#define SDMMC_STA_CKSTOP_Pos             (26U)

+#define SDMMC_STA_CKSTOP_Msk             (0x1UL << SDMMC_STA_CKSTOP_Pos)       /*!< 0x04000000 */

+#define SDMMC_STA_CKSTOP                 SDMMC_STA_CKSTOP_Msk                  /*!<SDMMC_CK stopped in Voltage switch procedure                            */

+#define SDMMC_STA_IDMATE_Pos             (27U)

+#define SDMMC_STA_IDMATE_Msk             (0x1UL << SDMMC_STA_IDMATE_Pos)       /*!< 0x08000000 */

+#define SDMMC_STA_IDMATE                 SDMMC_STA_IDMATE_Msk                  /*!<IDMA transfer error                                                     */

+#define SDMMC_STA_IDMABTC_Pos            (28U)

+#define SDMMC_STA_IDMABTC_Msk            (0x1UL << SDMMC_STA_IDMABTC_Pos)      /*!< 0x10000000 */

+#define SDMMC_STA_IDMABTC                SDMMC_STA_IDMABTC_Msk                 /*!<IDMA buffer transfer complete                                           */

+

+/*******************  Bit definition for SDMMC_ICR register  *******************/

+#define SDMMC_ICR_CCRCFAILC_Pos          (0U)

+#define SDMMC_ICR_CCRCFAILC_Msk          (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)    /*!< 0x00000001 */

+#define SDMMC_ICR_CCRCFAILC              SDMMC_ICR_CCRCFAILC_Msk               /*!<CCRCFAIL flag clear bit */

+#define SDMMC_ICR_DCRCFAILC_Pos          (1U)

+#define SDMMC_ICR_DCRCFAILC_Msk          (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)    /*!< 0x00000002 */

+#define SDMMC_ICR_DCRCFAILC              SDMMC_ICR_DCRCFAILC_Msk               /*!<DCRCFAIL flag clear bit */

+#define SDMMC_ICR_CTIMEOUTC_Pos          (2U)

+#define SDMMC_ICR_CTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)    /*!< 0x00000004 */

+#define SDMMC_ICR_CTIMEOUTC              SDMMC_ICR_CTIMEOUTC_Msk               /*!<CTIMEOUT flag clear bit */

+#define SDMMC_ICR_DTIMEOUTC_Pos          (3U)

+#define SDMMC_ICR_DTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)    /*!< 0x00000008 */

+#define SDMMC_ICR_DTIMEOUTC              SDMMC_ICR_DTIMEOUTC_Msk               /*!<DTIMEOUT flag clear bit */

+#define SDMMC_ICR_TXUNDERRC_Pos          (4U)

+#define SDMMC_ICR_TXUNDERRC_Msk          (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)    /*!< 0x00000010 */

+#define SDMMC_ICR_TXUNDERRC              SDMMC_ICR_TXUNDERRC_Msk               /*!<TXUNDERR flag clear bit */

+#define SDMMC_ICR_RXOVERRC_Pos           (5U)

+#define SDMMC_ICR_RXOVERRC_Msk           (0x1UL << SDMMC_ICR_RXOVERRC_Pos)     /*!< 0x00000020 */

+#define SDMMC_ICR_RXOVERRC               SDMMC_ICR_RXOVERRC_Msk                /*!<RXOVERR flag clear bit  */

+#define SDMMC_ICR_CMDRENDC_Pos           (6U)

+#define SDMMC_ICR_CMDRENDC_Msk           (0x1UL << SDMMC_ICR_CMDRENDC_Pos)     /*!< 0x00000040 */

+#define SDMMC_ICR_CMDRENDC               SDMMC_ICR_CMDRENDC_Msk                /*!<CMDREND flag clear bit  */

+#define SDMMC_ICR_CMDSENTC_Pos           (7U)

+#define SDMMC_ICR_CMDSENTC_Msk           (0x1UL << SDMMC_ICR_CMDSENTC_Pos)     /*!< 0x00000080 */

+#define SDMMC_ICR_CMDSENTC               SDMMC_ICR_CMDSENTC_Msk                /*!<CMDSENT flag clear bit  */

+#define SDMMC_ICR_DATAENDC_Pos           (8U)

+#define SDMMC_ICR_DATAENDC_Msk           (0x1UL << SDMMC_ICR_DATAENDC_Pos)     /*!< 0x00000100 */

+#define SDMMC_ICR_DATAENDC               SDMMC_ICR_DATAENDC_Msk                /*!<DATAEND flag clear bit  */

+#define SDMMC_ICR_DHOLDC_Pos             (9U)

+#define SDMMC_ICR_DHOLDC_Msk             (0x1UL << SDMMC_ICR_DHOLDC_Pos)       /*!< 0x00000200 */

+#define SDMMC_ICR_DHOLDC                 SDMMC_ICR_DHOLDC_Msk                  /*!<DHOLD flag clear bit       */

+#define SDMMC_ICR_DBCKENDC_Pos           (10U)

+#define SDMMC_ICR_DBCKENDC_Msk           (0x1UL << SDMMC_ICR_DBCKENDC_Pos)     /*!< 0x00000400 */

+#define SDMMC_ICR_DBCKENDC               SDMMC_ICR_DBCKENDC_Msk                /*!<DBCKEND flag clear bit  */

+#define SDMMC_ICR_DABORTC_Pos            (11U)

+#define SDMMC_ICR_DABORTC_Msk            (0x1UL << SDMMC_ICR_DABORTC_Pos)      /*!< 0x00000800 */

+#define SDMMC_ICR_DABORTC                SDMMC_ICR_DABORTC_Msk                 /*!<DABORTC flag clear bit     */

+#define SDMMC_ICR_BUSYD0ENDC_Pos         (21U)

+#define SDMMC_ICR_BUSYD0ENDC_Msk         (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)   /*!< 0x00200000 */

+#define SDMMC_ICR_BUSYD0ENDC             SDMMC_ICR_BUSYD0ENDC_Msk              /*!<BUSYD0ENDC flag clear bit  */

+#define SDMMC_ICR_SDIOITC_Pos            (22U)

+#define SDMMC_ICR_SDIOITC_Msk            (0x1UL << SDMMC_ICR_SDIOITC_Pos)      /*!< 0x00400000 */

+#define SDMMC_ICR_SDIOITC                SDMMC_ICR_SDIOITC_Msk                 /*!<SDIOIT flag clear bit      */

+#define SDMMC_ICR_ACKFAILC_Pos           (23U)

+#define SDMMC_ICR_ACKFAILC_Msk           (0x1UL << SDMMC_ICR_ACKFAILC_Pos)     /*!< 0x00800000 */

+#define SDMMC_ICR_ACKFAILC               SDMMC_ICR_ACKFAILC_Msk                /*!<ACKFAILC flag clear bit    */

+#define SDMMC_ICR_ACKTIMEOUTC_Pos        (24U)

+#define SDMMC_ICR_ACKTIMEOUTC_Msk        (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)  /*!< 0x01000000 */

+#define SDMMC_ICR_ACKTIMEOUTC            SDMMC_ICR_ACKTIMEOUTC_Msk             /*!<ACKTIMEOUTC flag clear bit */

+#define SDMMC_ICR_VSWENDC_Pos            (25U)

+#define SDMMC_ICR_VSWENDC_Msk            (0x1UL << SDMMC_ICR_VSWENDC_Pos)      /*!< 0x02000000 */

+#define SDMMC_ICR_VSWENDC                SDMMC_ICR_VSWENDC_Msk                 /*!<VSWENDC flag clear bit     */

+#define SDMMC_ICR_CKSTOPC_Pos            (26U)

+#define SDMMC_ICR_CKSTOPC_Msk            (0x1UL << SDMMC_ICR_CKSTOPC_Pos)      /*!< 0x04000000 */

+#define SDMMC_ICR_CKSTOPC                SDMMC_ICR_CKSTOPC_Msk                 /*!<CKSTOPC flag clear bit     */

+#define SDMMC_ICR_IDMATEC_Pos            (27U)

+#define SDMMC_ICR_IDMATEC_Msk            (0x1UL << SDMMC_ICR_IDMATEC_Pos)      /*!< 0x08000000 */

+#define SDMMC_ICR_IDMATEC                SDMMC_ICR_IDMATEC_Msk                 /*!<IDMATEC flag clear bit     */

+#define SDMMC_ICR_IDMABTCC_Pos           (28U)

+#define SDMMC_ICR_IDMABTCC_Msk           (0x1UL << SDMMC_ICR_IDMABTCC_Pos)     /*!< 0x10000000 */

+#define SDMMC_ICR_IDMABTCC               SDMMC_ICR_IDMABTCC_Msk                /*!<IDMABTCC flag clear bit    */

+

+/******************  Bit definition for SDMMC_MASK register  *******************/

+#define SDMMC_MASK_CCRCFAILIE_Pos        (0U)

+#define SDMMC_MASK_CCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)  /*!< 0x00000001 */

+#define SDMMC_MASK_CCRCFAILIE            SDMMC_MASK_CCRCFAILIE_Msk             /*!<Command CRC Fail Interrupt Enable          */

+#define SDMMC_MASK_DCRCFAILIE_Pos        (1U)

+#define SDMMC_MASK_DCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)  /*!< 0x00000002 */

+#define SDMMC_MASK_DCRCFAILIE            SDMMC_MASK_DCRCFAILIE_Msk             /*!<Data CRC Fail Interrupt Enable             */

+#define SDMMC_MASK_CTIMEOUTIE_Pos        (2U)

+#define SDMMC_MASK_CTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)  /*!< 0x00000004 */

+#define SDMMC_MASK_CTIMEOUTIE            SDMMC_MASK_CTIMEOUTIE_Msk             /*!<Command TimeOut Interrupt Enable           */

+#define SDMMC_MASK_DTIMEOUTIE_Pos        (3U)

+#define SDMMC_MASK_DTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)  /*!< 0x00000008 */

+#define SDMMC_MASK_DTIMEOUTIE            SDMMC_MASK_DTIMEOUTIE_Msk             /*!<Data TimeOut Interrupt Enable              */

+#define SDMMC_MASK_TXUNDERRIE_Pos        (4U)

+#define SDMMC_MASK_TXUNDERRIE_Msk        (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)  /*!< 0x00000010 */

+#define SDMMC_MASK_TXUNDERRIE            SDMMC_MASK_TXUNDERRIE_Msk             /*!<Tx FIFO UnderRun Error Interrupt Enable    */

+#define SDMMC_MASK_RXOVERRIE_Pos         (5U)

+#define SDMMC_MASK_RXOVERRIE_Msk         (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)   /*!< 0x00000020 */

+#define SDMMC_MASK_RXOVERRIE             SDMMC_MASK_RXOVERRIE_Msk              /*!<Rx FIFO OverRun Error Interrupt Enable     */

+#define SDMMC_MASK_CMDRENDIE_Pos         (6U)

+#define SDMMC_MASK_CMDRENDIE_Msk         (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)   /*!< 0x00000040 */

+#define SDMMC_MASK_CMDRENDIE             SDMMC_MASK_CMDRENDIE_Msk              /*!<Command Response Received Interrupt Enable */

+#define SDMMC_MASK_CMDSENTIE_Pos         (7U)

+#define SDMMC_MASK_CMDSENTIE_Msk         (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)   /*!< 0x00000080 */

+#define SDMMC_MASK_CMDSENTIE             SDMMC_MASK_CMDSENTIE_Msk              /*!<Command Sent Interrupt Enable              */

+#define SDMMC_MASK_DATAENDIE_Pos         (8U)

+#define SDMMC_MASK_DATAENDIE_Msk         (0x1UL << SDMMC_MASK_DATAENDIE_Pos)   /*!< 0x00000100 */

+#define SDMMC_MASK_DATAENDIE             SDMMC_MASK_DATAENDIE_Msk              /*!<Data End Interrupt Enable                  */

+#define SDMMC_MASK_DHOLDIE_Pos           (9U)

+#define SDMMC_MASK_DHOLDIE_Msk           (0x1UL << SDMMC_MASK_DHOLDIE_Pos)     /*!< 0x00000200 */

+#define SDMMC_MASK_DHOLDIE               SDMMC_MASK_DHOLDIE_Msk                /*!<Data Hold Interrupt Enable                 */

+#define SDMMC_MASK_DBCKENDIE_Pos         (10U)

+#define SDMMC_MASK_DBCKENDIE_Msk         (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)   /*!< 0x00000400 */

+#define SDMMC_MASK_DBCKENDIE             SDMMC_MASK_DBCKENDIE_Msk              /*!<Data Block End Interrupt Enable            */

+#define SDMMC_MASK_DABORTIE_Pos          (11U)

+#define SDMMC_MASK_DABORTIE_Msk          (0x1UL << SDMMC_MASK_DABORTIE_Pos)    /*!< 0x00000800 */

+#define SDMMC_MASK_DABORTIE              SDMMC_MASK_DABORTIE_Msk               /*!<Data transfer aborted interrupt enable     */

+

+#define SDMMC_MASK_TXFIFOHEIE_Pos        (14U)

+#define SDMMC_MASK_TXFIFOHEIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)  /*!< 0x00004000 */

+#define SDMMC_MASK_TXFIFOHEIE            SDMMC_MASK_TXFIFOHEIE_Msk             /*!<Tx FIFO Half Empty interrupt Enable        */

+#define SDMMC_MASK_RXFIFOHFIE_Pos        (15U)

+#define SDMMC_MASK_RXFIFOHFIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)  /*!< 0x00008000 */

+#define SDMMC_MASK_RXFIFOHFIE            SDMMC_MASK_RXFIFOHFIE_Msk             /*!<Rx FIFO Half Full interrupt Enable         */

+

+#define SDMMC_MASK_RXFIFOFIE_Pos         (17U)

+#define SDMMC_MASK_RXFIFOFIE_Msk         (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)   /*!< 0x00020000 */

+#define SDMMC_MASK_RXFIFOFIE             SDMMC_MASK_RXFIFOFIE_Msk              /*!<Rx FIFO Full interrupt Enable              */

+#define SDMMC_MASK_TXFIFOEIE_Pos         (18U)

+#define SDMMC_MASK_TXFIFOEIE_Msk         (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)   /*!< 0x00040000 */

+#define SDMMC_MASK_TXFIFOEIE             SDMMC_MASK_TXFIFOEIE_Msk              /*!<Tx FIFO Empty interrupt Enable             */

+

+#define SDMMC_MASK_BUSYD0ENDIE_Pos       (21U)

+#define SDMMC_MASK_BUSYD0ENDIE_Msk       (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */

+#define SDMMC_MASK_BUSYD0ENDIE           SDMMC_MASK_BUSYD0ENDIE_Msk            /*!<BUSYD0ENDIE interrupt Enable */

+#define SDMMC_MASK_SDIOITIE_Pos           (22U)

+#define SDMMC_MASK_SDIOITIE_Msk           (0x1UL << SDMMC_MASK_SDIOITIE_Pos)     /*!< 0x00400000 */

+#define SDMMC_MASK_SDIOITIE               SDMMC_MASK_SDIOITIE_Msk                /*!<SDMMC Mode Interrupt Received interrupt Enable */

+#define SDMMC_MASK_ACKFAILIE_Pos         (23U)

+#define SDMMC_MASK_ACKFAILIE_Msk         (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)   /*!< 0x00800000 */

+#define SDMMC_MASK_ACKFAILIE             SDMMC_MASK_ACKFAILIE_Msk              /*!<Acknowledgment Fail Interrupt Enable */

+#define SDMMC_MASK_ACKTIMEOUTIE_Pos      (24U)

+#define SDMMC_MASK_ACKTIMEOUTIE_Msk      (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */

+#define SDMMC_MASK_ACKTIMEOUTIE          SDMMC_MASK_ACKTIMEOUTIE_Msk           /*!<Acknowledgment timeout Interrupt Enable */

+#define SDMMC_MASK_VSWENDIE_Pos          (25U)

+#define SDMMC_MASK_VSWENDIE_Msk          (0x1UL << SDMMC_MASK_VSWENDIE_Pos)    /*!< 0x02000000 */

+#define SDMMC_MASK_VSWENDIE              SDMMC_MASK_VSWENDIE_Msk               /*!<Voltage switch critical timing section completion Interrupt Enable */

+#define SDMMC_MASK_CKSTOPIE_Pos          (26U)

+#define SDMMC_MASK_CKSTOPIE_Msk          (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)    /*!< 0x04000000 */

+#define SDMMC_MASK_CKSTOPIE              SDMMC_MASK_CKSTOPIE_Msk               /*!<Voltage Switch clock stopped Interrupt Enable */

+#define SDMMC_MASK_IDMABTCIE_Pos         (28U)

+#define SDMMC_MASK_IDMABTCIE_Msk         (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)   /*!< 0x10000000 */

+#define SDMMC_MASK_IDMABTCIE             SDMMC_MASK_IDMABTCIE_Msk              /*!<IDMA buffer transfer complete Interrupt Enable */

+

+/*****************  Bit definition for SDMMC_ACKTIME register  *****************/

+#define SDMMC_ACKTIME_ACKTIME_Pos        (0U)

+#define SDMMC_ACKTIME_ACKTIME_Msk        (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_ACKTIME_ACKTIME            SDMMC_ACKTIME_ACKTIME_Msk             /*!<Boot acknowledgment timeout period */

+

+/******************  Bit definition for SDMMC_FIFO register  *******************/

+#define SDMMC_FIFO_FIFODATA_Pos          (0U)

+#define SDMMC_FIFO_FIFODATA_Msk          (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_FIFO_FIFODATA              SDMMC_FIFO_FIFODATA_Msk               /*!<Receive and transmit FIFO data */

+

+/******************  Bit definition for SDMMC_IDMACTRL register ****************/

+#define SDMMC_IDMA_IDMAEN_Pos            (0U)

+#define SDMMC_IDMA_IDMAEN_Msk            (0x1UL << SDMMC_IDMA_IDMAEN_Pos)      /*!< 0x00000001 */

+#define SDMMC_IDMA_IDMAEN                SDMMC_IDMA_IDMAEN_Msk                 /*!< Enable the internal DMA of the SDMMC peripheral */

+#define SDMMC_IDMA_IDMABMODE_Pos         (1U)

+#define SDMMC_IDMA_IDMABMODE_Msk         (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)   /*!< 0x00000002 */

+#define SDMMC_IDMA_IDMABMODE             SDMMC_IDMA_IDMABMODE_Msk              /*!< Enable double buffer mode for IDMA */

+#define SDMMC_IDMA_IDMABACT_Pos          (2U)

+#define SDMMC_IDMA_IDMABACT_Msk          (0x1UL << SDMMC_IDMA_IDMABACT_Pos)    /*!< 0x00000004 */

+#define SDMMC_IDMA_IDMABACT              SDMMC_IDMA_IDMABACT_Msk               /*!< Uses buffer 1 when double buffer mode is selected */

+

+/*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/

+#define SDMMC_IDMABSIZE_IDMABNDT_Pos     (5U)

+#define SDMMC_IDMABSIZE_IDMABNDT_Msk     (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */

+#define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */

+

+/*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/

+#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */

+

+/*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/

+#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                        Delay Block Interface (DLYB)                        */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for DLYB_CR register  ********************/

+#define DLYB_CR_DEN_Pos         (0U)

+#define DLYB_CR_DEN_Msk         (0x1UL << DLYB_CR_DEN_Pos)                     /*!< 0x00000001 */

+#define DLYB_CR_DEN             DLYB_CR_DEN_Msk                                /*!<Delay Block enable */

+#define DLYB_CR_SEN_Pos         (1U)

+#define DLYB_CR_SEN_Msk         (0x1UL << DLYB_CR_SEN_Pos)                     /*!< 0x00000002 */

+#define DLYB_CR_SEN             DLYB_CR_SEN_Msk                                /*!<Sampler length enable */

+

+

+/*******************  Bit definition for DLYB_CFGR register  ********************/

+#define DLYB_CFGR_SEL_Pos       (0U)

+#define DLYB_CFGR_SEL_Msk       (0xFUL << DLYB_CFGR_SEL_Pos)                   /*!< 0x0000000F */

+#define DLYB_CFGR_SEL           DLYB_CFGR_SEL_Msk                              /*!<Select the phase for the Output clock[3:0] */

+#define DLYB_CFGR_SEL_0         (0x1UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000001 */

+#define DLYB_CFGR_SEL_1         (0x2UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000002 */

+#define DLYB_CFGR_SEL_2         (0x3UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000003 */

+#define DLYB_CFGR_SEL_3         (0x8UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000008 */

+

+#define DLYB_CFGR_UNIT_Pos      (8U)

+#define DLYB_CFGR_UNIT_Msk      (0x7FUL << DLYB_CFGR_UNIT_Pos)                 /*!< 0x00007F00 */

+#define DLYB_CFGR_UNIT          DLYB_CFGR_UNIT_Msk                             /*!<Delay Defines the delay of a Unit delay cell[6:0] */

+#define DLYB_CFGR_UNIT_0        (0x01UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000100 */

+#define DLYB_CFGR_UNIT_1        (0x02UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000200 */

+#define DLYB_CFGR_UNIT_2        (0x04UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000400 */

+#define DLYB_CFGR_UNIT_3        (0x08UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000800 */

+#define DLYB_CFGR_UNIT_4        (0x10UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00001000 */

+#define DLYB_CFGR_UNIT_5        (0x20UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00002000 */

+#define DLYB_CFGR_UNIT_6        (0x40UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00004000 */

+

+#define DLYB_CFGR_LNG_Pos       (16U)

+#define DLYB_CFGR_LNG_Msk       (0xFFFUL << DLYB_CFGR_LNG_Pos)                 /*!< 0x0FFF0000 */

+#define DLYB_CFGR_LNG           DLYB_CFGR_LNG_Msk                              /*!<Delay line length value[11:0] */

+#define DLYB_CFGR_LNG_0         (0x001UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00010000 */

+#define DLYB_CFGR_LNG_1         (0x002UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00020000 */

+#define DLYB_CFGR_LNG_2         (0x004UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00040000 */

+#define DLYB_CFGR_LNG_3         (0x008UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00080000 */

+#define DLYB_CFGR_LNG_4         (0x010UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00100000 */

+#define DLYB_CFGR_LNG_5         (0x020UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00200000 */

+#define DLYB_CFGR_LNG_6         (0x040UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00400000 */

+#define DLYB_CFGR_LNG_7         (0x080UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00800000 */

+#define DLYB_CFGR_LNG_8         (0x100UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x01000000 */

+#define DLYB_CFGR_LNG_9         (0x200UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x02000000 */

+#define DLYB_CFGR_LNG_10        (0x400UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x04000000 */

+#define DLYB_CFGR_LNG_11        (0x800UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x08000000 */

+

+#define DLYB_CFGR_LNGF_Pos      (31U)

+#define DLYB_CFGR_LNGF_Msk      (0x1UL << DLYB_CFGR_LNGF_Pos)                  /*!< 0x80000000 */

+#define DLYB_CFGR_LNGF          DLYB_CFGR_LNGF_Msk                             /*!<Length valid flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                   Serial Peripheral Interface (SPI/I2S)                    */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for SPI_CR1 register  ********************/

+#define SPI_CR1_SPE_Pos             (0U)

+#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000001 */

+#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<Serial Peripheral Enable                         */

+#define SPI_CR1_MASRX_Pos           (8U)

+#define SPI_CR1_MASRX_Msk           (0x1UL << SPI_CR1_MASRX_Pos)               /*!< 0x00000100 */

+#define SPI_CR1_MASRX               SPI_CR1_MASRX_Msk                          /*!<Master automatic SUSP in Receive mode            */

+#define SPI_CR1_CSTART_Pos          (9U)

+#define SPI_CR1_CSTART_Msk          (0x1UL << SPI_CR1_CSTART_Pos)              /*!< 0x00000200 */

+#define SPI_CR1_CSTART              SPI_CR1_CSTART_Msk                         /*!<Master transfer start                            */

+#define SPI_CR1_CSUSP_Pos           (10U)

+#define SPI_CR1_CSUSP_Msk           (0x1UL << SPI_CR1_CSUSP_Pos)               /*!< 0x00000400 */

+#define SPI_CR1_CSUSP               SPI_CR1_CSUSP_Msk                          /*!<Master SUSPend request                           */

+#define SPI_CR1_HDDIR_Pos           (11U)

+#define SPI_CR1_HDDIR_Msk           (0x1UL << SPI_CR1_HDDIR_Pos)               /*!< 0x00000800 */

+#define SPI_CR1_HDDIR               SPI_CR1_HDDIR_Msk                          /*!<Rx/Tx direction at Half-duplex mode              */

+#define SPI_CR1_SSI_Pos             (12U)

+#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00001000 */

+#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal SS signal input level                   */

+#define SPI_CR1_CRC33_17_Pos        (13U)

+#define SPI_CR1_CRC33_17_Msk        (0x1UL << SPI_CR1_CRC33_17_Pos)            /*!< 0x00002000 */

+#define SPI_CR1_CRC33_17             SPI_CR1_CRC33_17_Msk                      /*!<32-bit CRC polynomial configuration              */

+#define SPI_CR1_RCRCINI_Pos         (14U)

+#define SPI_CR1_RCRCINI_Msk         (0x1UL << SPI_CR1_RCRCINI_Pos)             /*!< 0x00004000 */

+#define SPI_CR1_RCRCINI             SPI_CR1_RCRCINI_Msk                        /*!<CRC init pattern control for receiver            */

+#define SPI_CR1_TCRCINI_Pos         (15U)

+#define SPI_CR1_TCRCINI_Msk         (0x1UL << SPI_CR1_TCRCINI_Pos)             /*!< 0x00008000 */

+#define SPI_CR1_TCRCINI             SPI_CR1_TCRCINI_Msk                        /*!<CRC init pattern control for transmitter         */

+#define SPI_CR1_IOLOCK_Pos          (16U)

+#define SPI_CR1_IOLOCK_Msk          (0x1UL << SPI_CR1_IOLOCK_Pos)              /*!< 0x00010000 */

+#define SPI_CR1_IOLOCK              SPI_CR1_IOLOCK_Msk                         /*!<Locking the AF configuration of associated IOs   */

+

+/*******************  Bit definition for SPI_CR2 register  ********************/

+#define SPI_CR2_TSER_Pos            (16U)

+#define SPI_CR2_TSER_Msk            (0xFFFFUL << SPI_CR2_TSER_Pos)             /*!< 0xFFFF0000 */

+#define SPI_CR2_TSER                SPI_CR2_TSER_Msk                           /*!<Number of data transfer extension                */

+#define SPI_CR2_TSIZE_Pos           (0U)

+#define SPI_CR2_TSIZE_Msk           (0xFFFFUL << SPI_CR2_TSIZE_Pos)            /*!< 0x0000FFFF */

+#define SPI_CR2_TSIZE               SPI_CR2_TSIZE_Msk                          /*!<Number of data at current transfer               */

+

+/*******************  Bit definition for SPI_CFG1 register  ********************/

+#define SPI_CFG1_DSIZE_Pos          (0U)

+#define SPI_CFG1_DSIZE_Msk          (0x1FUL << SPI_CFG1_DSIZE_Pos)             /*!< 0x0000001F */

+#define SPI_CFG1_DSIZE              SPI_CFG1_DSIZE_Msk                         /*!<DSIZE[4:0]: Bits number in single SPI data frame */

+#define SPI_CFG1_DSIZE_0            (0x01UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000001 */

+#define SPI_CFG1_DSIZE_1            (0x02UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000002 */

+#define SPI_CFG1_DSIZE_2            (0x04UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000004 */

+#define SPI_CFG1_DSIZE_3            (0x08UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000008 */

+#define SPI_CFG1_DSIZE_4            (0x10UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000010 */

+

+#define SPI_CFG1_FTHLV_Pos          (5U)

+#define SPI_CFG1_FTHLV_Msk          (0xFUL << SPI_CFG1_FTHLV_Pos)              /*!< 0x000001E0 */

+#define SPI_CFG1_FTHLV              SPI_CFG1_FTHLV_Msk                         /*!<FTHVL [3:0]: FIFO threshold level*/

+#define SPI_CFG1_FTHLV_0            (0x1UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000020 */

+#define SPI_CFG1_FTHLV_1            (0x2UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000040 */

+#define SPI_CFG1_FTHLV_2            (0x4UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000080 */

+#define SPI_CFG1_FTHLV_3            (0x8UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000100 */

+

+#define SPI_CFG1_UDRCFG_Pos         (9U)

+#define SPI_CFG1_UDRCFG_Msk         (0x3UL << SPI_CFG1_UDRCFG_Pos)             /*!< 0x00000600 */

+#define SPI_CFG1_UDRCFG             SPI_CFG1_UDRCFG_Msk                        /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */

+#define SPI_CFG1_UDRCFG_0           (0x1UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000200 */

+#define SPI_CFG1_UDRCFG_1           (0x2UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000400 */

+

+

+#define SPI_CFG1_UDRDET_Pos         (11U)

+#define SPI_CFG1_UDRDET_Msk         (0x3UL << SPI_CFG1_UDRDET_Pos)             /*!< 0x00001800 */

+#define SPI_CFG1_UDRDET             SPI_CFG1_UDRDET_Msk                        /*!<UDRDET[1:0]: Detection of underrun condition     */

+#define SPI_CFG1_UDRDET_0           (0x1UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00000800 */

+#define SPI_CFG1_UDRDET_1           (0x2UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00001000 */

+

+#define SPI_CFG1_RXDMAEN_Pos        (14U)

+#define SPI_CFG1_RXDMAEN_Msk        (0x1UL << SPI_CFG1_RXDMAEN_Pos)            /*!< 0x00004000 */

+#define SPI_CFG1_RXDMAEN            SPI_CFG1_RXDMAEN_Msk                       /*!<Rx DMA stream enable                */

+#define SPI_CFG1_TXDMAEN_Pos        (15U)

+#define SPI_CFG1_TXDMAEN_Msk        (0x1UL << SPI_CFG1_TXDMAEN_Pos)            /*!< 0x00008000 */

+#define SPI_CFG1_TXDMAEN            SPI_CFG1_TXDMAEN_Msk                       /*!<Tx DMA stream enable                */

+

+#define SPI_CFG1_CRCSIZE_Pos        (16U)

+#define SPI_CFG1_CRCSIZE_Msk        (0x1FUL << SPI_CFG1_CRCSIZE_Pos)           /*!< 0x001F0000 */

+#define SPI_CFG1_CRCSIZE            SPI_CFG1_CRCSIZE_Msk                       /*!<CRCSIZE [4:0]: Length of CRC frame*/

+#define SPI_CFG1_CRCSIZE_0          (0x01UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00010000 */

+#define SPI_CFG1_CRCSIZE_1          (0x02UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00020000 */

+#define SPI_CFG1_CRCSIZE_2          (0x04UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00040000 */

+#define SPI_CFG1_CRCSIZE_3          (0x08UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00080000 */

+#define SPI_CFG1_CRCSIZE_4          (0x10UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00100000 */

+

+#define SPI_CFG1_CRCEN_Pos          (22U)

+#define SPI_CFG1_CRCEN_Msk          (0x1UL << SPI_CFG1_CRCEN_Pos)              /*!< 0x00400000 */

+#define SPI_CFG1_CRCEN              SPI_CFG1_CRCEN_Msk                         /*!<Hardware CRC computation enable */

+

+#define SPI_CFG1_MBR_Pos            (28U)

+#define SPI_CFG1_MBR_Msk            (0x7UL << SPI_CFG1_MBR_Pos)                /*!< 0x70000000 */

+#define SPI_CFG1_MBR                SPI_CFG1_MBR_Msk                           /*!<Master baud rate                */

+#define SPI_CFG1_MBR_0              (0x1UL << SPI_CFG1_MBR_Pos)                 /*!< 0x10000000 */

+#define SPI_CFG1_MBR_1              (0x2UL << SPI_CFG1_MBR_Pos)                 /*!< 0x20000000 */

+#define SPI_CFG1_MBR_2              (0x4UL << SPI_CFG1_MBR_Pos)                 /*!< 0x40000000 */

+

+/*******************  Bit definition for SPI_CFG2 register  ********************/

+#define SPI_CFG2_MSSI_Pos           (0U)

+#define SPI_CFG2_MSSI_Msk           (0xFUL << SPI_CFG2_MSSI_Pos)               /*!< 0x0000000F */

+#define SPI_CFG2_MSSI               SPI_CFG2_MSSI_Msk                          /*!<Master SS Idleness */

+#define SPI_CFG2_MSSI_0             (0x1UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000001 */

+#define SPI_CFG2_MSSI_1             (0x2UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000002 */

+#define SPI_CFG2_MSSI_2             (0x4UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000004 */

+#define SPI_CFG2_MSSI_3             (0x8UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000008 */

+

+#define SPI_CFG2_MIDI_Pos           (4U)

+#define SPI_CFG2_MIDI_Msk           (0xFUL << SPI_CFG2_MIDI_Pos)               /*!< 0x000000F0 */

+#define SPI_CFG2_MIDI               SPI_CFG2_MIDI_Msk                          /*!<Master Inter-Data Idleness */

+#define SPI_CFG2_MIDI_0             (0x1UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000010 */

+#define SPI_CFG2_MIDI_1             (0x2UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000020 */

+#define SPI_CFG2_MIDI_2             (0x4UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000040 */

+#define SPI_CFG2_MIDI_3             (0x8UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000080 */

+

+#define SPI_CFG2_IOSWP_Pos          (15U)

+#define SPI_CFG2_IOSWP_Msk          (0x1UL << SPI_CFG2_IOSWP_Pos)              /*!< 0x00008000 */

+#define SPI_CFG2_IOSWP              SPI_CFG2_IOSWP_Msk                         /*!<Swap functionality of MISO and MOSI pins */

+

+#define SPI_CFG2_COMM_Pos           (17U)

+#define SPI_CFG2_COMM_Msk           (0x3UL << SPI_CFG2_COMM_Pos)               /*!< 0x00060000 */

+#define SPI_CFG2_COMM               SPI_CFG2_COMM_Msk                          /*!<COMM [1:0]: SPI Communication Mode*/

+#define SPI_CFG2_COMM_0             (0x1UL << SPI_CFG2_COMM_Pos)                /*!< 0x00020000 */

+#define SPI_CFG2_COMM_1             (0x2UL << SPI_CFG2_COMM_Pos)                /*!< 0x00040000 */

+

+#define SPI_CFG2_SP_Pos             (19U)

+#define SPI_CFG2_SP_Msk             (0x7UL << SPI_CFG2_SP_Pos)                 /*!< 0x00380000 */

+#define SPI_CFG2_SP                 SPI_CFG2_SP_Msk                            /*!<SP[2:0]: Serial Protocol */

+#define SPI_CFG2_SP_0               (0x1UL << SPI_CFG2_SP_Pos)                  /*!< 0x00080000 */

+#define SPI_CFG2_SP_1               (0x2UL << SPI_CFG2_SP_Pos)                  /*!< 0x00100000 */

+#define SPI_CFG2_SP_2               (0x4UL << SPI_CFG2_SP_Pos)                  /*!< 0x00200000 */

+

+#define SPI_CFG2_MASTER_Pos         (22U)

+#define SPI_CFG2_MASTER_Msk         (0x1UL << SPI_CFG2_MASTER_Pos)             /*!< 0x00400000 */

+#define SPI_CFG2_MASTER             SPI_CFG2_MASTER_Msk                        /*!<SPI Master           */

+#define SPI_CFG2_LSBFRST_Pos        (23U)

+#define SPI_CFG2_LSBFRST_Msk        (0x1UL << SPI_CFG2_LSBFRST_Pos)            /*!< 0x00800000 */

+#define SPI_CFG2_LSBFRST            SPI_CFG2_LSBFRST_Msk                       /*!<Data frame format               */

+#define SPI_CFG2_CPHA_Pos           (24U)

+#define SPI_CFG2_CPHA_Msk           (0x1UL << SPI_CFG2_CPHA_Pos)               /*!< 0x01000000 */

+#define SPI_CFG2_CPHA               SPI_CFG2_CPHA_Msk                          /*!<Clock Phase      */

+#define SPI_CFG2_CPOL_Pos           (25U)

+#define SPI_CFG2_CPOL_Msk           (0x1UL << SPI_CFG2_CPOL_Pos)               /*!< 0x02000000 */

+#define SPI_CFG2_CPOL               SPI_CFG2_CPOL_Msk                          /*!<Clock Polarity   */

+#define SPI_CFG2_SSM_Pos            (26U)

+#define SPI_CFG2_SSM_Msk            (0x1UL << SPI_CFG2_SSM_Pos)                /*!< 0x04000000 */

+#define SPI_CFG2_SSM                SPI_CFG2_SSM_Msk                           /*!<Software slave management */

+

+#define SPI_CFG2_SSIOP_Pos          (28U)

+#define SPI_CFG2_SSIOP_Msk          (0x1UL << SPI_CFG2_SSIOP_Pos)              /*!< 0x10000000 */

+#define SPI_CFG2_SSIOP              SPI_CFG2_SSIOP_Msk                         /*!<SS input/output polarity */

+#define SPI_CFG2_SSOE_Pos           (29U)

+#define SPI_CFG2_SSOE_Msk           (0x1UL << SPI_CFG2_SSOE_Pos)               /*!< 0x20000000 */

+#define SPI_CFG2_SSOE               SPI_CFG2_SSOE_Msk                          /*!<SS output enable */

+#define SPI_CFG2_SSOM_Pos           (30U)

+#define SPI_CFG2_SSOM_Msk           (0x1UL << SPI_CFG2_SSOM_Pos)               /*!< 0x40000000 */

+#define SPI_CFG2_SSOM               SPI_CFG2_SSOM_Msk                          /*!<SS output management in master mode */

+

+#define SPI_CFG2_AFCNTR_Pos         (31U)

+#define SPI_CFG2_AFCNTR_Msk         (0x1UL << SPI_CFG2_AFCNTR_Pos)             /*!< 0x80000000 */

+#define SPI_CFG2_AFCNTR             SPI_CFG2_AFCNTR_Msk                        /*!<Alternate function GPIOs control */

+

+/*******************  Bit definition for SPI_IER register  ********************/

+#define SPI_IER_RXPIE_Pos           (0U)

+#define SPI_IER_RXPIE_Msk           (0x1UL << SPI_IER_RXPIE_Pos)               /*!< 0x00000001 */

+#define SPI_IER_RXPIE               SPI_IER_RXPIE_Msk                          /*!<RXP Interrupt Enable            */

+#define SPI_IER_TXPIE_Pos           (1U)

+#define SPI_IER_TXPIE_Msk           (0x1UL << SPI_IER_TXPIE_Pos)               /*!< 0x00000002 */

+#define SPI_IER_TXPIE               SPI_IER_TXPIE_Msk                          /*!<TXP interrupt enable            */

+#define SPI_IER_DXPIE_Pos           (2U)

+#define SPI_IER_DXPIE_Msk           (0x1UL << SPI_IER_DXPIE_Pos)               /*!< 0x00000004 */

+#define SPI_IER_DXPIE               SPI_IER_DXPIE_Msk                          /*!<DXP interrupt enable            */

+#define SPI_IER_EOTIE_Pos           (3U)

+#define SPI_IER_EOTIE_Msk           (0x1UL << SPI_IER_EOTIE_Pos)               /*!< 0x00000008 */

+#define SPI_IER_EOTIE               SPI_IER_EOTIE_Msk                          /*!<EOT/SUSP/TXC interrupt enable   */

+#define SPI_IER_TXTFIE_Pos          (4U)

+#define SPI_IER_TXTFIE_Msk          (0x1UL << SPI_IER_TXTFIE_Pos)              /*!< 0x00000010 */

+#define SPI_IER_TXTFIE              SPI_IER_TXTFIE_Msk                         /*!<TXTF interrupt enable           */

+#define SPI_IER_UDRIE_Pos           (5U)

+#define SPI_IER_UDRIE_Msk           (0x1UL << SPI_IER_UDRIE_Pos)               /*!< 0x00000020 */

+#define SPI_IER_UDRIE               SPI_IER_UDRIE_Msk                          /*!<UDR interrupt enable            */

+#define SPI_IER_OVRIE_Pos           (6U)

+#define SPI_IER_OVRIE_Msk           (0x1UL << SPI_IER_OVRIE_Pos)               /*!< 0x00000040 */

+#define SPI_IER_OVRIE               SPI_IER_OVRIE_Msk                          /*!<OVR interrupt enable            */

+#define SPI_IER_CRCEIE_Pos          (7U)

+#define SPI_IER_CRCEIE_Msk          (0x1UL << SPI_IER_CRCEIE_Pos)               /*!< 0x00000080 */

+#define SPI_IER_CRCEIE              SPI_IER_CRCEIE_Msk                          /*!<CRCE interrupt enable           */

+#define SPI_IER_TIFREIE_Pos         (8U)

+#define SPI_IER_TIFREIE_Msk         (0x1UL << SPI_IER_TIFREIE_Pos)             /*!< 0x00000100 */

+#define SPI_IER_TIFREIE             SPI_IER_TIFREIE_Msk                        /*!<TI Frame Error interrupt enable */

+#define SPI_IER_MODFIE_Pos          (9U)

+#define SPI_IER_MODFIE_Msk          (0x1UL << SPI_IER_MODFIE_Pos)              /*!< 0x00000200 */

+#define SPI_IER_MODFIE              SPI_IER_MODFIE_Msk                         /*!<MODF interrupt enable           */

+#define SPI_IER_TSERFIE_Pos         (10U)

+#define SPI_IER_TSERFIE_Msk         (0x1UL << SPI_IER_TSERFIE_Pos)              /*!< 0x00000400 */

+#define SPI_IER_TSERFIE             SPI_IER_TSERFIE_Msk                        /*!<TSERF interrupt enable          */

+

+/*******************  Bit definition for SPI_SR register  ********************/

+#define SPI_SR_RXP_Pos              (0U)

+#define SPI_SR_RXP_Msk              (0x1UL << SPI_SR_RXP_Pos)                  /*!< 0x00000001 */

+#define SPI_SR_RXP                  SPI_SR_RXP_Msk                             /*!<Rx-Packet available             */

+#define SPI_SR_TXP_Pos              (1U)

+#define SPI_SR_TXP_Msk              (0x1UL << SPI_SR_TXP_Pos)                  /*!< 0x00000002 */

+#define SPI_SR_TXP                  SPI_SR_TXP_Msk                             /*!<Tx-Packet space available       */

+#define SPI_SR_DXP_Pos              (2U)

+#define SPI_SR_DXP_Msk              (0x1UL << SPI_SR_DXP_Pos)                  /*!< 0x00000004 */

+#define SPI_SR_DXP                  SPI_SR_DXP_Msk                             /*!<Duplex Packet available         */

+#define SPI_SR_EOT_Pos              (3U)

+#define SPI_SR_EOT_Msk              (0x1UL << SPI_SR_EOT_Pos)                  /*!< 0x00000008 */

+#define SPI_SR_EOT                  SPI_SR_EOT_Msk                             /*!<Duplex Packet available         */

+#define SPI_SR_TXTF_Pos             (4U)

+#define SPI_SR_TXTF_Msk             (0x1UL << SPI_SR_TXTF_Pos)                 /*!< 0x00000010 */

+#define SPI_SR_TXTF                 SPI_SR_TXTF_Msk                            /*!<Transmission Transfer Filled    */

+#define SPI_SR_UDR_Pos              (5U)

+#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000020 */

+#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<UDR at Slave transmission       */

+#define SPI_SR_OVR_Pos              (6U)

+#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */

+#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Rx-Packet available             */

+#define SPI_SR_CRCE_Pos             (7U)

+#define SPI_SR_CRCE_Msk             (0x1UL << SPI_SR_CRCE_Pos)                 /*!< 0x00000080 */

+#define SPI_SR_CRCE                 SPI_SR_CRCE_Msk                            /*!<CRC Error Detected              */

+#define SPI_SR_TIFRE_Pos            (8U)

+#define SPI_SR_TIFRE_Msk            (0x1UL << SPI_SR_TIFRE_Pos)                /*!< 0x00000100 */

+#define SPI_SR_TIFRE                SPI_SR_TIFRE_Msk                           /*!<TI frame format error Detected  */

+#define SPI_SR_MODF_Pos             (9U)

+#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000200 */

+#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode Fault Detected             */

+#define SPI_SR_TSERF_Pos            (10U)

+#define SPI_SR_TSERF_Msk            (0x1UL << SPI_SR_TSERF_Pos)                /*!< 0x00000400 */

+#define SPI_SR_TSERF                SPI_SR_TSERF_Msk                           /*!<Number of SPI data to be transacted reloaded     */

+#define SPI_SR_SUSP_Pos             (11U)

+#define SPI_SR_SUSP_Msk             (0x1UL << SPI_SR_SUSP_Pos)                 /*!< 0x00000800 */

+#define SPI_SR_SUSP                 SPI_SR_SUSP_Msk                            /*!<SUSP is set by hardware  */

+#define SPI_SR_TXC_Pos              (12U)

+#define SPI_SR_TXC_Msk              (0x1UL << SPI_SR_TXC_Pos)                  /*!< 0x00001000 */

+#define SPI_SR_TXC                  SPI_SR_TXC_Msk                             /*!<TxFIFO transmission complete */

+#define SPI_SR_RXPLVL_Pos           (13U)

+#define SPI_SR_RXPLVL_Msk           (0x3UL << SPI_SR_RXPLVL_Pos)               /*!< 0x00006000 */

+#define SPI_SR_RXPLVL               SPI_SR_RXPLVL_Msk                          /*!<RxFIFO Packing Level                             */

+#define SPI_SR_RXPLVL_0             (0x1UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00002000 */

+#define SPI_SR_RXPLVL_1             (0x2UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00004000 */

+#define SPI_SR_RXWNE_Pos            (15U)

+#define SPI_SR_RXWNE_Msk            (0x1UL << SPI_SR_RXWNE_Pos)                /*!< 0x00008000 */

+#define SPI_SR_RXWNE                SPI_SR_RXWNE_Msk                           /*!<Rx FIFO Word Not Empty                           */

+#define SPI_SR_CTSIZE_Pos           (16U)

+#define SPI_SR_CTSIZE_Msk           (0xFFFFUL << SPI_SR_CTSIZE_Pos)            /*!< 0xFFFF0000 */

+#define SPI_SR_CTSIZE               SPI_SR_CTSIZE_Msk                          /*!<Number of data frames remaining in TSIZE         */

+

+/*******************  Bit definition for SPI_IFCR register  ********************/

+#define SPI_IFCR_EOTC_Pos           (3U)

+#define SPI_IFCR_EOTC_Msk           (0x1UL << SPI_IFCR_EOTC_Pos)               /*!< 0x00000008 */

+#define SPI_IFCR_EOTC               SPI_IFCR_EOTC_Msk                          /*!<End Of Transfer flag clear              */

+#define SPI_IFCR_TXTFC_Pos          (4U)

+#define SPI_IFCR_TXTFC_Msk          (0x1UL << SPI_IFCR_TXTFC_Pos)              /*!< 0x00000010 */

+#define SPI_IFCR_TXTFC              SPI_IFCR_TXTFC_Msk                         /*!<Transmission Transfer Filled flag clear */

+#define SPI_IFCR_UDRC_Pos           (5U)

+#define SPI_IFCR_UDRC_Msk           (0x1UL << SPI_IFCR_UDRC_Pos)               /*!< 0x00000020 */

+#define SPI_IFCR_UDRC               SPI_IFCR_UDRC_Msk                          /*!<Underrun flag clear                     */

+#define SPI_IFCR_OVRC_Pos           (6U)

+#define SPI_IFCR_OVRC_Msk           (0x1UL << SPI_IFCR_OVRC_Pos)               /*!< 0x00000040 */

+#define SPI_IFCR_OVRC               SPI_IFCR_OVRC_Msk                          /*!<Overrun flag clear                      */

+#define SPI_IFCR_CRCEC_Pos          (7U)

+#define SPI_IFCR_CRCEC_Msk          (0x1UL << SPI_IFCR_CRCEC_Pos)              /*!< 0x00000080 */

+#define SPI_IFCR_CRCEC              SPI_IFCR_CRCEC_Msk                         /*!<CRC Error flag clear                    */

+#define SPI_IFCR_TIFREC_Pos         (8U)

+#define SPI_IFCR_TIFREC_Msk         (0x1UL << SPI_IFCR_TIFREC_Pos)             /*!< 0x00000100 */

+#define SPI_IFCR_TIFREC             SPI_IFCR_TIFREC_Msk                        /*!<TI frame format error flag clear        */

+#define SPI_IFCR_MODFC_Pos          (9U)

+#define SPI_IFCR_MODFC_Msk          (0x1UL << SPI_IFCR_MODFC_Pos)              /*!< 0x00000200 */

+#define SPI_IFCR_MODFC              SPI_IFCR_MODFC_Msk                         /*!<Mode Fault flag clear                   */

+#define SPI_IFCR_TSERFC_Pos         (10U)

+#define SPI_IFCR_TSERFC_Msk         (0x1UL << SPI_IFCR_TSERFC_Pos)             /*!< 0x00000400 */

+#define SPI_IFCR_TSERFC             SPI_IFCR_TSERFC_Msk                        /*!<TSERFC flag clear                       */

+#define SPI_IFCR_SUSPC_Pos          (11U)

+#define SPI_IFCR_SUSPC_Msk          (0x1UL << SPI_IFCR_SUSPC_Pos)              /*!< 0x00000800 */

+#define SPI_IFCR_SUSPC              SPI_IFCR_SUSPC_Msk                         /*!<SUSPend flag clear                      */

+

+/*******************  Bit definition for SPI_TXDR register  ********************/

+#define SPI_TXDR_TXDR_Pos           (0U)

+#define SPI_TXDR_TXDR_Msk           (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)        /*!< 0xFFFFFFFF */

+#define SPI_TXDR_TXDR               SPI_TXDR_TXDR_Msk                          /* Transmit Data Register */

+

+/*******************  Bit definition for SPI_RXDR register  ********************/

+#define SPI_RXDR_RXDR_Pos           (0U)

+#define SPI_RXDR_RXDR_Msk           (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)        /*!< 0xFFFFFFFF */

+#define SPI_RXDR_RXDR               SPI_RXDR_RXDR_Msk                          /* Receive Data Register  */

+

+/*******************  Bit definition for SPI_CRCPOLY register  ********************/

+#define SPI_CRCPOLY_CRCPOLY_Pos     (0U)

+#define SPI_CRCPOLY_CRCPOLY_Msk     (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)  /*!< 0xFFFFFFFF */

+#define SPI_CRCPOLY_CRCPOLY         SPI_CRCPOLY_CRCPOLY_Msk                    /* CRC Polynomial register  */

+

+/*******************  Bit definition for SPI_TXCRC register  ********************/

+#define SPI_TXCRC_TXCRC_Pos         (0U)

+#define SPI_TXCRC_TXCRC_Msk         (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_TXCRC_TXCRC             SPI_TXCRC_TXCRC_Msk                        /* CRCRegister for transmitter */

+

+/*******************  Bit definition for SPI_RXCRC register  ********************/

+#define SPI_RXCRC_RXCRC_Pos         (0U)

+#define SPI_RXCRC_RXCRC_Msk         (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_RXCRC_RXCRC             SPI_RXCRC_RXCRC_Msk                        /* CRCRegister for receiver */

+

+/*******************  Bit definition for SPI_UDRDR register  ********************/

+#define SPI_UDRDR_UDRDR_Pos         (0U)

+#define SPI_UDRDR_UDRDR_Msk         (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_UDRDR_UDRDR             SPI_UDRDR_UDRDR_Msk                        /* Data at slave underrun condition */

+

+/******************  Bit definition for SPI_I2SCFGR register  *****************/

+#define SPI_I2SCFGR_I2SMOD_Pos      (0U)

+#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000001 */

+#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */

+#define SPI_I2SCFGR_I2SCFG_Pos      (1U)

+#define SPI_I2SCFGR_I2SCFG_Msk      (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x0000000E */

+#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[2:0] I2S configuration mode                */

+#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000002 */

+#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000004 */

+#define SPI_I2SCFGR_I2SCFG_2        (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000008 */

+#define SPI_I2SCFGR_I2SSTD_Pos      (4U)

+#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */

+#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] I2S standard selection                */

+#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */

+#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */

+#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)

+#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */

+#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                         */

+#define SPI_I2SCFGR_DATLEN_Pos      (8U)

+#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000300 */

+#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] Data length to be transferred         */

+#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000100 */

+#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000200 */

+#define SPI_I2SCFGR_CHLEN_Pos       (10U)

+#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000400 */

+#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */

+#define SPI_I2SCFGR_CKPOL_Pos       (11U)

+#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000800 */

+#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<Steady state clock polarity                       */

+#define SPI_I2SCFGR_FIXCH_Pos       (12U)

+#define SPI_I2SCFGR_FIXCH_Msk       (0x1UL << SPI_I2SCFGR_FIXCH_Pos)           /*!< 0x00001000 */

+#define SPI_I2SCFGR_FIXCH           SPI_I2SCFGR_FIXCH_Msk                      /*!<Fixed channel length in SLAVE                     */

+#define SPI_I2SCFGR_WSINV_Pos       (13U)

+#define SPI_I2SCFGR_WSINV_Msk       (0x1UL << SPI_I2SCFGR_WSINV_Pos)           /*!< 0x00002000 */

+#define SPI_I2SCFGR_WSINV           SPI_I2SCFGR_WSINV_Msk                      /*!<Word select inversion                             */

+#define SPI_I2SCFGR_DATFMT_Pos      (14U)

+#define SPI_I2SCFGR_DATFMT_Msk      (0x1UL << SPI_I2SCFGR_DATFMT_Pos)          /*!< 0x00004000 */

+#define SPI_I2SCFGR_DATFMT          SPI_I2SCFGR_DATFMT_Msk                     /*!<Data format                                       */

+#define SPI_I2SCFGR_I2SDIV_Pos      (16U)

+#define SPI_I2SCFGR_I2SDIV_Msk      (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)         /*!< 0x00FF0000 */

+#define SPI_I2SCFGR_I2SDIV          SPI_I2SCFGR_I2SDIV_Msk                     /*!<I2S Linear prescaler */

+#define SPI_I2SCFGR_ODD_Pos         (24U)

+#define SPI_I2SCFGR_ODD_Msk         (0x1UL << SPI_I2SCFGR_ODD_Pos)             /*!< 0x01000000 */

+#define SPI_I2SCFGR_ODD             SPI_I2SCFGR_ODD_Msk                        /*!<Odd factor for the prescaler */

+#define SPI_I2SCFGR_MCKOE_Pos       (25U)

+#define SPI_I2SCFGR_MCKOE_Msk       (0x1UL << SPI_I2SCFGR_MCKOE_Pos)           /*!< 0x02000000 */

+#define SPI_I2SCFGR_MCKOE           SPI_I2SCFGR_MCKOE_Msk                      /*!<Master Clock Output Enable */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    QUADSPI                                 */

+/*                                                                            */

+/******************************************************************************/

+/*****************  Bit definition for QUADSPI_CR register  *******************/

+#define QUADSPI_CR_EN_Pos                (0U)

+#define QUADSPI_CR_EN_Msk                (0x1UL << QUADSPI_CR_EN_Pos)          /*!< 0x00000001 */

+#define QUADSPI_CR_EN                    QUADSPI_CR_EN_Msk                     /*!< Enable */

+#define QUADSPI_CR_ABORT_Pos             (1U)

+#define QUADSPI_CR_ABORT_Msk             (0x1UL << QUADSPI_CR_ABORT_Pos)       /*!< 0x00000002 */

+#define QUADSPI_CR_ABORT                 QUADSPI_CR_ABORT_Msk                  /*!< Abort request */

+#define QUADSPI_CR_DMAEN_Pos             (2U)

+#define QUADSPI_CR_DMAEN_Msk             (0x1UL << QUADSPI_CR_DMAEN_Pos)       /*!< 0x00000004 */

+#define QUADSPI_CR_DMAEN                 QUADSPI_CR_DMAEN_Msk                  /*!< DMA Enable */

+#define QUADSPI_CR_TCEN_Pos              (3U)

+#define QUADSPI_CR_TCEN_Msk              (0x1UL << QUADSPI_CR_TCEN_Pos)        /*!< 0x00000008 */

+#define QUADSPI_CR_TCEN                  QUADSPI_CR_TCEN_Msk                   /*!< Timeout Counter Enable */

+#define QUADSPI_CR_SSHIFT_Pos            (4U)

+#define QUADSPI_CR_SSHIFT_Msk            (0x1UL << QUADSPI_CR_SSHIFT_Pos)      /*!< 0x00000010 */

+#define QUADSPI_CR_SSHIFT                QUADSPI_CR_SSHIFT_Msk                 /*!< SSHIFT Sample Shift */

+#define QUADSPI_CR_DFM_Pos               (6U)

+#define QUADSPI_CR_DFM_Msk               (0x1UL << QUADSPI_CR_DFM_Pos)         /*!< 0x00000040 */

+#define QUADSPI_CR_DFM                   QUADSPI_CR_DFM_Msk                    /*!< Dual Flash Mode */

+#define QUADSPI_CR_FSEL_Pos              (7U)

+#define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)        /*!< 0x00000080 */

+#define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select */

+#define QUADSPI_CR_FTHRES_Pos            (8U)

+#define QUADSPI_CR_FTHRES_Msk            (0xFUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000F00 */

+#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level */

+#define QUADSPI_CR_FTHRES_0              (0x1UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */

+#define QUADSPI_CR_FTHRES_1              (0x2UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */

+#define QUADSPI_CR_FTHRES_2              (0x4UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */

+#define QUADSPI_CR_FTHRES_3              (0x8UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */

+#define QUADSPI_CR_TEIE_Pos              (16U)

+#define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)        /*!< 0x00010000 */

+#define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable */

+#define QUADSPI_CR_TCIE_Pos              (17U)

+#define QUADSPI_CR_TCIE_Msk              (0x1UL << QUADSPI_CR_TCIE_Pos)        /*!< 0x00020000 */

+#define QUADSPI_CR_TCIE                  QUADSPI_CR_TCIE_Msk                   /*!< Transfer Complete Interrupt Enable */

+#define QUADSPI_CR_FTIE_Pos              (18U)

+#define QUADSPI_CR_FTIE_Msk              (0x1UL << QUADSPI_CR_FTIE_Pos)        /*!< 0x00040000 */

+#define QUADSPI_CR_FTIE                  QUADSPI_CR_FTIE_Msk                   /*!< FIFO Threshold Interrupt Enable */

+#define QUADSPI_CR_SMIE_Pos              (19U)

+#define QUADSPI_CR_SMIE_Msk              (0x1UL << QUADSPI_CR_SMIE_Pos)        /*!< 0x00080000 */

+#define QUADSPI_CR_SMIE                  QUADSPI_CR_SMIE_Msk                   /*!< Status Match Interrupt Enable */

+#define QUADSPI_CR_TOIE_Pos              (20U)

+#define QUADSPI_CR_TOIE_Msk              (0x1UL << QUADSPI_CR_TOIE_Pos)        /*!< 0x00100000 */

+#define QUADSPI_CR_TOIE                  QUADSPI_CR_TOIE_Msk                   /*!< TimeOut Interrupt Enable */

+#define QUADSPI_CR_APMS_Pos              (22U)

+#define QUADSPI_CR_APMS_Msk              (0x1UL << QUADSPI_CR_APMS_Pos)        /*!< 0x00400000 */

+#define QUADSPI_CR_APMS                  QUADSPI_CR_APMS_Msk                   /*!< Bit 1 */

+#define QUADSPI_CR_PMM_Pos               (23U)

+#define QUADSPI_CR_PMM_Msk               (0x1UL << QUADSPI_CR_PMM_Pos)         /*!< 0x00800000 */

+#define QUADSPI_CR_PMM                   QUADSPI_CR_PMM_Msk                    /*!< Polling Match Mode */

+#define QUADSPI_CR_PRESCALER_Pos         (24U)

+#define QUADSPI_CR_PRESCALER_Msk         (0xFFUL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0xFF000000 */

+#define QUADSPI_CR_PRESCALER             QUADSPI_CR_PRESCALER_Msk              /*!< PRESCALER[7:0] Clock prescaler */

+#define QUADSPI_CR_PRESCALER_0           (0x01UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x01000000 */

+#define QUADSPI_CR_PRESCALER_1           (0x02UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x02000000 */

+#define QUADSPI_CR_PRESCALER_2           (0x04UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x04000000 */

+#define QUADSPI_CR_PRESCALER_3           (0x08UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x08000000 */

+#define QUADSPI_CR_PRESCALER_4           (0x10UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x10000000 */

+#define QUADSPI_CR_PRESCALER_5           (0x20UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x20000000 */

+#define QUADSPI_CR_PRESCALER_6           (0x40UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x40000000 */

+#define QUADSPI_CR_PRESCALER_7           (0x80UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x80000000 */

+

+/*****************  Bit definition for QUADSPI_DCR register  ******************/

+#define QUADSPI_DCR_CKMODE_Pos           (0U)

+#define QUADSPI_DCR_CKMODE_Msk           (0x1UL << QUADSPI_DCR_CKMODE_Pos)     /*!< 0x00000001 */

+#define QUADSPI_DCR_CKMODE               QUADSPI_DCR_CKMODE_Msk                /*!< Mode 0 / Mode 3 */

+#define QUADSPI_DCR_CSHT_Pos             (8U)

+#define QUADSPI_DCR_CSHT_Msk             (0x7UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000700 */

+#define QUADSPI_DCR_CSHT                 QUADSPI_DCR_CSHT_Msk                  /*!< CSHT[2:0]: ChipSelect High Time */

+#define QUADSPI_DCR_CSHT_0               (0x1UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000100 */

+#define QUADSPI_DCR_CSHT_1               (0x2UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000200 */

+#define QUADSPI_DCR_CSHT_2               (0x4UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000400 */

+#define QUADSPI_DCR_FSIZE_Pos            (16U)

+#define QUADSPI_DCR_FSIZE_Msk            (0x1FUL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x001F0000 */

+#define QUADSPI_DCR_FSIZE                QUADSPI_DCR_FSIZE_Msk                 /*!< FSIZE[4:0]: Flash Size */

+#define QUADSPI_DCR_FSIZE_0              (0x01UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00010000 */

+#define QUADSPI_DCR_FSIZE_1              (0x02UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00020000 */

+#define QUADSPI_DCR_FSIZE_2              (0x04UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00040000 */

+#define QUADSPI_DCR_FSIZE_3              (0x08UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00080000 */

+#define QUADSPI_DCR_FSIZE_4              (0x10UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00100000 */

+

+/******************  Bit definition for QUADSPI_SR register  *******************/

+#define QUADSPI_SR_TEF_Pos               (0U)

+#define QUADSPI_SR_TEF_Msk               (0x1UL << QUADSPI_SR_TEF_Pos)         /*!< 0x00000001 */

+#define QUADSPI_SR_TEF                   QUADSPI_SR_TEF_Msk                    /*!< Transfer Error Flag */

+#define QUADSPI_SR_TCF_Pos               (1U)

+#define QUADSPI_SR_TCF_Msk               (0x1UL << QUADSPI_SR_TCF_Pos)         /*!< 0x00000002 */

+#define QUADSPI_SR_TCF                   QUADSPI_SR_TCF_Msk                    /*!< Transfer Complete Flag */

+#define QUADSPI_SR_FTF_Pos               (2U)

+#define QUADSPI_SR_FTF_Msk               (0x1UL << QUADSPI_SR_FTF_Pos)         /*!< 0x00000004 */

+#define QUADSPI_SR_FTF                   QUADSPI_SR_FTF_Msk                    /*!< FIFO Threshlod Flag */

+#define QUADSPI_SR_SMF_Pos               (3U)

+#define QUADSPI_SR_SMF_Msk               (0x1UL << QUADSPI_SR_SMF_Pos)         /*!< 0x00000008 */

+#define QUADSPI_SR_SMF                   QUADSPI_SR_SMF_Msk                    /*!< Status Match Flag */

+#define QUADSPI_SR_TOF_Pos               (4U)

+#define QUADSPI_SR_TOF_Msk               (0x1UL << QUADSPI_SR_TOF_Pos)         /*!< 0x00000010 */

+#define QUADSPI_SR_TOF                   QUADSPI_SR_TOF_Msk                    /*!< Timeout Flag */

+#define QUADSPI_SR_BUSY_Pos              (5U)

+#define QUADSPI_SR_BUSY_Msk              (0x1UL << QUADSPI_SR_BUSY_Pos)        /*!< 0x00000020 */

+#define QUADSPI_SR_BUSY                  QUADSPI_SR_BUSY_Msk                   /*!< Busy */

+#define QUADSPI_SR_FLEVEL_Pos            (8U)

+#define QUADSPI_SR_FLEVEL_Msk            (0x3FUL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00003F00 */

+#define QUADSPI_SR_FLEVEL                QUADSPI_SR_FLEVEL_Msk                 /*!< FIFO Threshlod Flag */

+#define QUADSPI_SR_FLEVEL_0              (0x01UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000100 */

+#define QUADSPI_SR_FLEVEL_1              (0x02UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000200 */

+#define QUADSPI_SR_FLEVEL_2              (0x04UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000400 */

+#define QUADSPI_SR_FLEVEL_3              (0x08UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000800 */

+#define QUADSPI_SR_FLEVEL_4              (0x10UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00001000 */

+#define QUADSPI_SR_FLEVEL_5              (0x20UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00002000 */

+

+/******************  Bit definition for QUADSPI_FCR register  ******************/

+#define QUADSPI_FCR_CTEF_Pos             (0U)

+#define QUADSPI_FCR_CTEF_Msk             (0x1UL << QUADSPI_FCR_CTEF_Pos)       /*!< 0x00000001 */

+#define QUADSPI_FCR_CTEF                 QUADSPI_FCR_CTEF_Msk                  /*!< Clear Transfer Error Flag */

+#define QUADSPI_FCR_CTCF_Pos             (1U)

+#define QUADSPI_FCR_CTCF_Msk             (0x1UL << QUADSPI_FCR_CTCF_Pos)       /*!< 0x00000002 */

+#define QUADSPI_FCR_CTCF                 QUADSPI_FCR_CTCF_Msk                  /*!< Clear Transfer Complete Flag */

+#define QUADSPI_FCR_CSMF_Pos             (3U)

+#define QUADSPI_FCR_CSMF_Msk             (0x1UL << QUADSPI_FCR_CSMF_Pos)       /*!< 0x00000008 */

+#define QUADSPI_FCR_CSMF                 QUADSPI_FCR_CSMF_Msk                  /*!< Clear Status Match Flag */

+#define QUADSPI_FCR_CTOF_Pos             (4U)

+#define QUADSPI_FCR_CTOF_Msk             (0x1UL << QUADSPI_FCR_CTOF_Pos)       /*!< 0x00000010 */

+#define QUADSPI_FCR_CTOF                 QUADSPI_FCR_CTOF_Msk                  /*!< Clear Timeout Flag */

+

+/******************  Bit definition for QUADSPI_DLR register  ******************/

+#define QUADSPI_DLR_DL_Pos               (0U)

+#define QUADSPI_DLR_DL_Msk               (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)  /*!< 0xFFFFFFFF */

+#define QUADSPI_DLR_DL                   QUADSPI_DLR_DL_Msk                    /*!< DL[31:0]: Data Length */

+

+/******************  Bit definition for QUADSPI_CCR register  ******************/

+#define QUADSPI_CCR_INSTRUCTION_Pos      (0U)

+#define QUADSPI_CCR_INSTRUCTION_Msk      (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */

+#define QUADSPI_CCR_INSTRUCTION          QUADSPI_CCR_INSTRUCTION_Msk             /*!< INSTRUCTION[7:0]: Instruction */

+#define QUADSPI_CCR_INSTRUCTION_0        (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */

+#define QUADSPI_CCR_INSTRUCTION_1        (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */

+#define QUADSPI_CCR_INSTRUCTION_2        (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */

+#define QUADSPI_CCR_INSTRUCTION_3        (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */

+#define QUADSPI_CCR_INSTRUCTION_4        (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */

+#define QUADSPI_CCR_INSTRUCTION_5        (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */

+#define QUADSPI_CCR_INSTRUCTION_6        (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */

+#define QUADSPI_CCR_INSTRUCTION_7        (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */

+#define QUADSPI_CCR_IMODE_Pos            (8U)

+#define QUADSPI_CCR_IMODE_Msk            (0x3UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000300 */

+#define QUADSPI_CCR_IMODE                QUADSPI_CCR_IMODE_Msk                   /*!< IMODE[1:0]: Instruction Mode */

+#define QUADSPI_CCR_IMODE_0              (0x1UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000100 */

+#define QUADSPI_CCR_IMODE_1              (0x2UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000200 */

+#define QUADSPI_CCR_ADMODE_Pos           (10U)

+#define QUADSPI_CCR_ADMODE_Msk           (0x3UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000C00 */

+#define QUADSPI_CCR_ADMODE               QUADSPI_CCR_ADMODE_Msk                  /*!< ADMODE[1:0]: Address Mode */

+#define QUADSPI_CCR_ADMODE_0             (0x1UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000400 */

+#define QUADSPI_CCR_ADMODE_1             (0x2UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000800 */

+#define QUADSPI_CCR_ADSIZE_Pos           (12U)

+#define QUADSPI_CCR_ADSIZE_Msk           (0x3UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00003000 */

+#define QUADSPI_CCR_ADSIZE               QUADSPI_CCR_ADSIZE_Msk                  /*!< ADSIZE[1:0]: Address Size */

+#define QUADSPI_CCR_ADSIZE_0             (0x1UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00001000 */

+#define QUADSPI_CCR_ADSIZE_1             (0x2UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00002000 */

+#define QUADSPI_CCR_ABMODE_Pos           (14U)

+#define QUADSPI_CCR_ABMODE_Msk           (0x3UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x0000C000 */

+#define QUADSPI_CCR_ABMODE               QUADSPI_CCR_ABMODE_Msk                  /*!< ABMODE[1:0]: Alternate Bytes Mode */

+#define QUADSPI_CCR_ABMODE_0             (0x1UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00004000 */

+#define QUADSPI_CCR_ABMODE_1             (0x2UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00008000 */

+#define QUADSPI_CCR_ABSIZE_Pos           (16U)

+#define QUADSPI_CCR_ABSIZE_Msk           (0x3UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00030000 */

+#define QUADSPI_CCR_ABSIZE               QUADSPI_CCR_ABSIZE_Msk                  /*!< ABSIZE[1:0]: Instruction Mode */

+#define QUADSPI_CCR_ABSIZE_0             (0x1UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00010000 */

+#define QUADSPI_CCR_ABSIZE_1             (0x2UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00020000 */

+#define QUADSPI_CCR_DCYC_Pos             (18U)

+#define QUADSPI_CCR_DCYC_Msk             (0x1FUL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x007C0000 */

+#define QUADSPI_CCR_DCYC                 QUADSPI_CCR_DCYC_Msk                    /*!< DCYC[4:0]: Dummy Cycles */

+#define QUADSPI_CCR_DCYC_0               (0x01UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00040000 */

+#define QUADSPI_CCR_DCYC_1               (0x02UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00080000 */

+#define QUADSPI_CCR_DCYC_2               (0x04UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00100000 */

+#define QUADSPI_CCR_DCYC_3               (0x08UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00200000 */

+#define QUADSPI_CCR_DCYC_4               (0x10UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00400000 */

+#define QUADSPI_CCR_DMODE_Pos            (24U)

+#define QUADSPI_CCR_DMODE_Msk            (0x3UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x03000000 */

+#define QUADSPI_CCR_DMODE                QUADSPI_CCR_DMODE_Msk                   /*!< DMODE[1:0]: Data Mode */

+#define QUADSPI_CCR_DMODE_0              (0x1UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x01000000 */

+#define QUADSPI_CCR_DMODE_1              (0x2UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x02000000 */

+#define QUADSPI_CCR_FMODE_Pos            (26U)

+#define QUADSPI_CCR_FMODE_Msk            (0x3UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x0C000000 */

+#define QUADSPI_CCR_FMODE                QUADSPI_CCR_FMODE_Msk                   /*!< FMODE[1:0]: Functional Mode */

+#define QUADSPI_CCR_FMODE_0              (0x1UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x04000000 */

+#define QUADSPI_CCR_FMODE_1              (0x2UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x08000000 */

+#define QUADSPI_CCR_SIOO_Pos             (28U)

+#define QUADSPI_CCR_SIOO_Msk             (0x1UL << QUADSPI_CCR_SIOO_Pos)         /*!< 0x10000000 */

+#define QUADSPI_CCR_SIOO                 QUADSPI_CCR_SIOO_Msk                    /*!< SIOO: Send Instruction Only Once Mode */

+#define QUADSPI_CCR_DHHC_Pos             (30U)

+#define QUADSPI_CCR_DHHC_Msk             (0x1UL << QUADSPI_CCR_DHHC_Pos)         /*!< 0x40000000 */

+#define QUADSPI_CCR_DHHC                 QUADSPI_CCR_DHHC_Msk                    /*!< DHHC: DDR hold half cycle */

+#define QUADSPI_CCR_DDRM_Pos             (31U)

+#define QUADSPI_CCR_DDRM_Msk             (0x1UL << QUADSPI_CCR_DDRM_Pos)         /*!< 0x80000000 */

+#define QUADSPI_CCR_DDRM                 QUADSPI_CCR_DDRM_Msk                    /*!< DDRM: Double Data Rate Mode */

+

+/******************  Bit definition for QUADSPI_AR register  *******************/

+#define QUADSPI_AR_ADDRESS_Pos           (0U)

+#define QUADSPI_AR_ADDRESS_Msk           (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_AR_ADDRESS               QUADSPI_AR_ADDRESS_Msk                /*!< ADDRESS[31:0]: Address */

+

+/******************  Bit definition for QUADSPI_ABR register  ******************/

+#define QUADSPI_ABR_ALTERNATE_Pos        (0U)

+#define QUADSPI_ABR_ALTERNATE_Msk        (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_ABR_ALTERNATE            QUADSPI_ABR_ALTERNATE_Msk             /*!< ALTERNATE[31:0]: Alternate Bytes */

+

+/******************  Bit definition for QUADSPI_DR register  *******************/

+#define QUADSPI_DR_DATA_Pos              (0U)

+#define QUADSPI_DR_DATA_Msk              (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_DR_DATA                  QUADSPI_DR_DATA_Msk                   /*!< DATA[31:0]: Data */

+

+/******************  Bit definition for QUADSPI_PSMKR register  ****************/

+#define QUADSPI_PSMKR_MASK_Pos           (0U)

+#define QUADSPI_PSMKR_MASK_Msk           (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_PSMKR_MASK               QUADSPI_PSMKR_MASK_Msk                /*!< MASK[31:0]: Status Mask */

+

+/******************  Bit definition for QUADSPI_PSMAR register  ****************/

+#define QUADSPI_PSMAR_MATCH_Pos          (0U)

+#define QUADSPI_PSMAR_MATCH_Msk          (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_PSMAR_MATCH              QUADSPI_PSMAR_MATCH_Msk               /*!< MATCH[31:0]: Status Match */

+

+/******************  Bit definition for QUADSPI_PIR register  *****************/

+#define QUADSPI_PIR_INTERVAL_Pos         (0U)

+#define QUADSPI_PIR_INTERVAL_Msk         (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */

+#define QUADSPI_PIR_INTERVAL             QUADSPI_PIR_INTERVAL_Msk              /*!< INTERVAL[15:0]: Polling Interval */

+

+/******************  Bit definition for QUADSPI_LPTR register  *****************/

+#define QUADSPI_LPTR_TIMEOUT_Pos         (0U)

+#define QUADSPI_LPTR_TIMEOUT_Msk         (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */

+#define QUADSPI_LPTR_TIMEOUT             QUADSPI_LPTR_TIMEOUT_Msk              /*!< TIMEOUT[15:0]: Timeout period */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                 SYSCFG                                     */

+/*                                                                            */

+/******************************************************************************/

+

+/******************  Bit definition for SYSCFG_PMCR register  ******************/

+#define SYSCFG_PMCR_I2C1_FMP_Pos        (0U)

+#define SYSCFG_PMCR_I2C1_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos)    /*!< 0x00000001 */

+#define SYSCFG_PMCR_I2C1_FMP            SYSCFG_PMCR_I2C1_FMP_Msk               /*!< I2C1 Fast mode plus */

+#define SYSCFG_PMCR_I2C2_FMP_Pos        (1U)

+#define SYSCFG_PMCR_I2C2_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos)    /*!< 0x00000002 */

+#define SYSCFG_PMCR_I2C2_FMP            SYSCFG_PMCR_I2C2_FMP_Msk               /*!< I2C2 Fast mode plus */

+#define SYSCFG_PMCR_I2C3_FMP_Pos        (2U)

+#define SYSCFG_PMCR_I2C3_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos)    /*!< 0x00000004 */

+#define SYSCFG_PMCR_I2C3_FMP            SYSCFG_PMCR_I2C3_FMP_Msk               /*!< I2C3 Fast mode plus */

+#define SYSCFG_PMCR_I2C4_FMP_Pos        (3U)

+#define SYSCFG_PMCR_I2C4_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos)    /*!< 0x00000008 */

+#define SYSCFG_PMCR_I2C4_FMP            SYSCFG_PMCR_I2C4_FMP_Msk               /*!< I2C4 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB6_FMP_Pos     (4U)

+#define SYSCFG_PMCR_I2C_PB6_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */

+#define SYSCFG_PMCR_I2C_PB6_FMP         SYSCFG_PMCR_I2C_PB6_FMP_Msk            /*!< I2C PB6 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB7_FMP_Pos     (5U)

+#define SYSCFG_PMCR_I2C_PB7_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */

+#define SYSCFG_PMCR_I2C_PB7_FMP         SYSCFG_PMCR_I2C_PB7_FMP_Msk            /*!< I2C PB7 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB8_FMP_Pos     (6U)

+#define SYSCFG_PMCR_I2C_PB8_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */

+#define SYSCFG_PMCR_I2C_PB8_FMP         SYSCFG_PMCR_I2C_PB8_FMP_Msk            /*!< I2C PB8 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB9_FMP_Pos     (7U)

+#define SYSCFG_PMCR_I2C_PB9_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */

+#define SYSCFG_PMCR_I2C_PB9_FMP         SYSCFG_PMCR_I2C_PB9_FMP_Msk            /*!< I2C PB9 Fast mode plus */

+#define SYSCFG_PMCR_BOOSTEN_Pos         (8U)

+#define SYSCFG_PMCR_BOOSTEN_Msk         (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos)     /*!< 0x00000100 */

+#define SYSCFG_PMCR_BOOSTEN             SYSCFG_PMCR_BOOSTEN_Msk                /*!< I/O analog switch voltage booster enable */

+

+#define SYSCFG_PMCR_BOOSTVDDSEL_Pos     (9U)

+#define SYSCFG_PMCR_BOOSTVDDSEL_Msk     (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos) /*!< 0x00000200 */

+#define SYSCFG_PMCR_BOOSTVDDSEL         SYSCFG_PMCR_BOOSTVDDSEL_Msk            /*!< Analog switch supply source selection : VDD/VDDA */

+

+#define SYSCFG_PMCR_EPIS_SEL_Pos        (21U)

+#define SYSCFG_PMCR_EPIS_SEL_Msk        (0x7UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00E00000 */

+#define SYSCFG_PMCR_EPIS_SEL            SYSCFG_PMCR_EPIS_SEL_Msk               /*!< Ethernet PHY Interface Selection */

+#define SYSCFG_PMCR_EPIS_SEL_0          (0x1UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00200000 */

+#define SYSCFG_PMCR_EPIS_SEL_1          (0x2UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00400000 */

+#define SYSCFG_PMCR_EPIS_SEL_2          (0x4UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00800000 */

+#define SYSCFG_PMCR_PA0SO_Pos           (24U)

+#define SYSCFG_PMCR_PA0SO_Msk           (0x1UL << SYSCFG_PMCR_PA0SO_Pos)       /*!< 0x01000000 */

+#define SYSCFG_PMCR_PA0SO               SYSCFG_PMCR_PA0SO_Msk                  /*!< PA0 Switch Open */

+#define SYSCFG_PMCR_PA1SO_Pos           (25U)

+#define SYSCFG_PMCR_PA1SO_Msk           (0x1UL << SYSCFG_PMCR_PA1SO_Pos)       /*!< 0x02000000 */

+#define SYSCFG_PMCR_PA1SO               SYSCFG_PMCR_PA1SO_Msk                  /*!< PA1 Switch Open */

+#define SYSCFG_PMCR_PC2SO_Pos           (26U)

+#define SYSCFG_PMCR_PC2SO_Msk           (0x1UL << SYSCFG_PMCR_PC2SO_Pos)       /*!< 0x04000000 */

+#define SYSCFG_PMCR_PC2SO               SYSCFG_PMCR_PC2SO_Msk                  /*!< PC2 Switch Open */

+#define SYSCFG_PMCR_PC3SO_Pos           (27U)

+#define SYSCFG_PMCR_PC3SO_Msk           (0x1UL << SYSCFG_PMCR_PC3SO_Pos)       /*!< 0x08000000 */

+#define SYSCFG_PMCR_PC3SO               SYSCFG_PMCR_PC3SO_Msk                  /*!< PC3 Switch Open */

+

+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/

+#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)

+#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */

+#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)

+#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */

+#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)

+#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000F00 */

+#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */

+#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)

+#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x0000F000 */

+#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */

+/**

+  * @brief   EXTI0 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */

+

+/**

+  * @brief   EXTI1 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */

+/**

+  * @brief   EXTI2 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */

+

+/**

+  * @brief   EXTI3 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/

+#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)

+#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */

+#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)

+#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */

+#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)

+#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000F00 */

+#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */

+#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)

+#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x0000F000 */

+#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */

+/**

+  * @brief   EXTI4 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */

+/**

+  * @brief   EXTI5 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */

+/**

+  * @brief   EXTI6 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */

+

+/**

+  * @brief   EXTI7 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/

+#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)

+#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */

+#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)

+#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */

+#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)

+#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000F00 */

+#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */

+#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)

+#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x0000F000 */

+#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */

+

+/**

+  * @brief   EXTI8 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */

+

+/**

+  * @brief   EXTI9 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */

+

+/**

+  * @brief   EXTI10 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */

+

+/**

+  * @brief   EXTI11 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/

+#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)

+#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x0000000F */

+#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */

+#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)

+#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x000000F0 */

+#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */

+#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)

+#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000F00 */

+#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */

+#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)

+#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x0000F000 */

+#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */

+/**

+  * @brief   EXTI12 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */

+/**

+  * @brief   EXTI13 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */

+/**

+  * @brief   EXTI14 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */

+/**

+  * @brief   EXTI15 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */

+

+/******************  Bit definition for SYSCFG_CFGR register  ******************/

+#define SYSCFG_CFGR_CM4L_Pos            (0U)

+#define SYSCFG_CFGR_CM4L_Msk            (0x1UL << SYSCFG_CFGR_CM4L_Pos)        /*!< 0x00000001 */

+#define SYSCFG_CFGR_CM4L                SYSCFG_CFGR_CM4L_Msk                   /*!<Cortex-M4 LOCKUP (Hardfault) output enable bit */

+#define SYSCFG_CFGR_PVDL_Pos            (2U)

+#define SYSCFG_CFGR_PVDL_Msk            (0x1UL << SYSCFG_CFGR_PVDL_Pos)        /*!< 0x00000004 */

+#define SYSCFG_CFGR_PVDL                SYSCFG_CFGR_PVDL_Msk                   /*!<PVD lock enable bit */

+#define SYSCFG_CFGR_FLASHL_Pos          (3U)

+#define SYSCFG_CFGR_FLASHL_Msk          (0x1UL << SYSCFG_CFGR_FLASHL_Pos)      /*!< 0x00000008 */

+#define SYSCFG_CFGR_FLASHL              SYSCFG_CFGR_FLASHL_Msk                 /*!<FLASH double ECC error lock bit */

+#define SYSCFG_CFGR_CM7L_Pos            (6U)

+#define SYSCFG_CFGR_CM7L_Msk            (0x1UL << SYSCFG_CFGR_CM7L_Pos)        /*!< 0x00000040 */

+#define SYSCFG_CFGR_CM7L                SYSCFG_CFGR_CM7L_Msk                   /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */

+#define SYSCFG_CFGR_BKRAML_Pos          (7U)

+#define SYSCFG_CFGR_BKRAML_Msk          (0x1UL << SYSCFG_CFGR_BKRAML_Pos)      /*!< 0x00000080 */

+#define SYSCFG_CFGR_BKRAML              SYSCFG_CFGR_BKRAML_Msk                 /*!<Backup SRAM double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM4L_Pos          (9U)

+#define SYSCFG_CFGR_SRAM4L_Msk          (0x1UL << SYSCFG_CFGR_SRAM4L_Pos)      /*!< 0x00000200 */

+#define SYSCFG_CFGR_SRAM4L              SYSCFG_CFGR_SRAM4L_Msk                 /*!<SRAM4 double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM3L_Pos          (10U)

+#define SYSCFG_CFGR_SRAM3L_Msk          (0x1UL << SYSCFG_CFGR_SRAM3L_Pos)      /*!< 0x00000400 */

+#define SYSCFG_CFGR_SRAM3L              SYSCFG_CFGR_SRAM3L_Msk                 /*!<SRAM3 double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM2L_Pos          (11U)

+#define SYSCFG_CFGR_SRAM2L_Msk          (0x1UL << SYSCFG_CFGR_SRAM2L_Pos)      /*!< 0x00000800 */

+#define SYSCFG_CFGR_SRAM2L              SYSCFG_CFGR_SRAM2L_Msk                 /*!<SRAM2 double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM1L_Pos          (12U)

+#define SYSCFG_CFGR_SRAM1L_Msk          (0x1UL << SYSCFG_CFGR_SRAM1L_Pos)      /*!< 0x00001000 */

+#define SYSCFG_CFGR_SRAM1L              SYSCFG_CFGR_SRAM1L_Msk                 /*!<SRAM1 double ECC error lock bit */

+#define SYSCFG_CFGR_DTCML_Pos           (13U)

+#define SYSCFG_CFGR_DTCML_Msk           (0x1UL << SYSCFG_CFGR_DTCML_Pos)       /*!< 0x00002000 */

+#define SYSCFG_CFGR_DTCML               SYSCFG_CFGR_DTCML_Msk                  /*!<DTCM double ECC error lock bit */

+#define SYSCFG_CFGR_ITCML_Pos           (14U)

+#define SYSCFG_CFGR_ITCML_Msk           (0x1UL << SYSCFG_CFGR_ITCML_Pos)       /*!< 0x00004000 */

+#define SYSCFG_CFGR_ITCML               SYSCFG_CFGR_ITCML_Msk                  /*!<ITCM double ECC error lock bit */

+#define SYSCFG_CFGR_AXISRAML_Pos        (15U)

+#define SYSCFG_CFGR_AXISRAML_Msk        (0x1UL << SYSCFG_CFGR_AXISRAML_Pos)    /*!< 0x00008000 */

+#define SYSCFG_CFGR_AXISRAML            SYSCFG_CFGR_AXISRAML_Msk               /*!<AXISRAM double ECC error lock bit */

+

+/******************  Bit definition for SYSCFG_CCCSR register  ******************/

+#define SYSCFG_CCCSR_EN_Pos             (0U)

+#define SYSCFG_CCCSR_EN_Msk             (0x1UL << SYSCFG_CCCSR_EN_Pos)         /*!< 0x00000001 */

+#define SYSCFG_CCCSR_EN                 SYSCFG_CCCSR_EN_Msk                    /*!< I/O compensation cell enable */

+#define SYSCFG_CCCSR_CS_Pos             (1U)

+#define SYSCFG_CCCSR_CS_Msk             (0x1UL << SYSCFG_CCCSR_CS_Pos)         /*!< 0x00000002 */

+#define SYSCFG_CCCSR_CS                 SYSCFG_CCCSR_CS_Msk                    /*!< I/O compensation cell code selection */

+#define SYSCFG_CCCSR_READY_Pos          (8U)

+#define SYSCFG_CCCSR_READY_Msk          (0x1UL << SYSCFG_CCCSR_READY_Pos)      /*!< 0x00000100 */

+#define SYSCFG_CCCSR_READY              SYSCFG_CCCSR_READY_Msk                 /*!< I/O compensation cell ready flag */

+#define SYSCFG_CCCSR_HSLV_Pos           (16U)

+#define SYSCFG_CCCSR_HSLV_Msk           (0x1UL << SYSCFG_CCCSR_HSLV_Pos)       /*!< 0x00010000 */

+#define SYSCFG_CCCSR_HSLV               SYSCFG_CCCSR_HSLV_Msk                  /*!< High-speed at low-voltage */

+

+/******************  Bit definition for SYSCFG_CCVR register  *******************/

+#define SYSCFG_CCVR_NCV_Pos             (0U)

+#define SYSCFG_CCVR_NCV_Msk             (0xFUL << SYSCFG_CCVR_NCV_Pos)         /*!< 0x0000000F */

+#define SYSCFG_CCVR_NCV                 SYSCFG_CCVR_NCV_Msk                    /*!< NMOS compensation value */

+#define SYSCFG_CCVR_PCV_Pos             (4U)

+#define SYSCFG_CCVR_PCV_Msk             (0xFUL << SYSCFG_CCVR_PCV_Pos)         /*!< 0x000000F0 */

+#define SYSCFG_CCVR_PCV                 SYSCFG_CCVR_PCV_Msk                    /*!< PMOS compensation value */

+

+/******************  Bit definition for SYSCFG_CCCR register  *******************/

+#define SYSCFG_CCCR_NCC_Pos             (0U)

+#define SYSCFG_CCCR_NCC_Msk             (0xFUL << SYSCFG_CCCR_NCC_Pos)         /*!< 0x0000000F */

+#define SYSCFG_CCCR_NCC                 SYSCFG_CCCR_NCC_Msk                    /*!< NMOS compensation code */

+#define SYSCFG_CCCR_PCC_Pos             (4U)

+#define SYSCFG_CCCR_PCC_Msk             (0xFUL << SYSCFG_CCCR_PCC_Pos)         /*!< 0x000000F0 */

+#define SYSCFG_CCCR_PCC                 SYSCFG_CCCR_PCC_Msk                    /*!< PMOS compensation code */

+/******************  Bit definition for SYSCFG_PWRCR register  *******************/

+#define SYSCFG_PWRCR_ODEN_Pos           (0U)

+#define SYSCFG_PWRCR_ODEN_Msk           (0x1UL << SYSCFG_PWRCR_ODEN_Pos)         /*!< 0x00000001 */

+#define SYSCFG_PWRCR_ODEN               SYSCFG_PWRCR_ODEN_Msk                    /*!< PWR overdrive enable */

+

+/******************  Bit definition for SYSCFG_PKGR register  *******************/

+#define SYSCFG_PKGR_PKG_Pos             (0U)

+#define SYSCFG_PKGR_PKG_Msk             (0xFUL << SYSCFG_PKGR_PKG_Pos)         /*!< 0x0000000F */

+#define SYSCFG_PKGR_PKG                 SYSCFG_PKGR_PKG_Msk                    /*!< Package type */

+

+/******************  Bit definition for SYSCFG_UR0 register  *******************/

+#define SYSCFG_UR0_BKS_Pos              (0U)

+#define SYSCFG_UR0_BKS_Msk              (0x1UL << SYSCFG_UR0_BKS_Pos)          /*!< 0x00000001 */

+#define SYSCFG_UR0_BKS                  SYSCFG_UR0_BKS_Msk                     /*!< Bank Swap */

+#define SYSCFG_UR0_RDP_Pos              (16U)

+#define SYSCFG_UR0_RDP_Msk              (0xFFUL << SYSCFG_UR0_RDP_Pos)         /*!< 0x00FF0000 */

+#define SYSCFG_UR0_RDP                  SYSCFG_UR0_RDP_Msk                     /*!< Readout protection */

+

+/******************  Bit definition for SYSCFG_UR1 register  *******************/

+#define SYSCFG_UR1_BCM4_Pos             (0U)

+#define SYSCFG_UR1_BCM4_Msk             (0x1UL << SYSCFG_UR1_BCM4_Pos)         /*!< 0x00000001 */

+#define SYSCFG_UR1_BCM4                 SYSCFG_UR1_BCM4_Msk                    /*!< Boot Cortex-M4 */

+#define SYSCFG_UR1_BCM7_Pos             (16U)

+#define SYSCFG_UR1_BCM7_Msk             (0x1UL << SYSCFG_UR1_BCM7_Pos)         /*!< 0x00010000 */

+#define SYSCFG_UR1_BCM7                 SYSCFG_UR1_BCM7_Msk                    /*!< Boot Cortex-M7 */

+/******************  Bit definition for SYSCFG_UR2 register  *******************/

+#define SYSCFG_UR2_BORH_Pos             (0U)

+#define SYSCFG_UR2_BORH_Msk             (0x3UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000003 */

+#define SYSCFG_UR2_BORH                 SYSCFG_UR2_BORH_Msk                    /*!< Brown Out Reset High level */

+#define SYSCFG_UR2_BORH_0               (0x1UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000001 */

+#define SYSCFG_UR2_BORH_1               (0x2UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000002 */

+#define SYSCFG_UR2_BCM7_ADD0_Pos        (16U)

+#define SYSCFG_UR2_BCM7_ADD0_Msk        (0xFFFFUL << SYSCFG_UR2_BCM7_ADD0_Pos) /*!< 0xFFFF0000 */

+#define SYSCFG_UR2_BCM7_ADD0            SYSCFG_UR2_BCM7_ADD0_Msk               /*!< Boot Cortex-M7 Address 0 */

+/******************  Bit definition for SYSCFG_UR3 register  *******************/

+#define SYSCFG_UR3_BCM7_ADD1_Pos        (0U)

+#define SYSCFG_UR3_BCM7_ADD1_Msk        (0xFFFFUL << SYSCFG_UR3_BCM7_ADD1_Pos) /*!< 0x0000FFFF */

+#define SYSCFG_UR3_BCM7_ADD1            SYSCFG_UR3_BCM7_ADD1_Msk               /*!< Boot Cortex-M7 Address 1 */

+

+#define SYSCFG_UR3_BCM4_ADD0_Pos        (16U)

+#define SYSCFG_UR3_BCM4_ADD0_Msk        (0xFFFFUL << SYSCFG_UR3_BCM4_ADD0_Pos) /*!< 0xFFFF0000 */

+#define SYSCFG_UR3_BCM4_ADD0            SYSCFG_UR3_BCM4_ADD0_Msk               /*!< Boot Cortex-M4 Address 0 */

+

+/******************  Bit definition for SYSCFG_UR4 register  *******************/

+

+#define SYSCFG_UR4_BCM4_ADD1_Pos        (0U)

+#define SYSCFG_UR4_BCM4_ADD1_Msk        (0xFFFFUL << SYSCFG_UR4_BCM4_ADD1_Pos) /*!< 0x0000FFFF */

+#define SYSCFG_UR4_BCM4_ADD1            SYSCFG_UR4_BCM4_ADD1_Msk               /*!< Boot Cortex-M4 Address 1 */

+

+#define SYSCFG_UR4_MEPAD_BANK1_Pos      (16U)

+#define SYSCFG_UR4_MEPAD_BANK1_Msk      (0x1UL << SYSCFG_UR4_MEPAD_BANK1_Pos)  /*!< 0x00010000 */

+#define SYSCFG_UR4_MEPAD_BANK1          SYSCFG_UR4_MEPAD_BANK1_Msk             /*!< Mass Erase Protected Area Disabled for bank 1 */

+

+/******************  Bit definition for SYSCFG_UR5 register  *******************/

+#define SYSCFG_UR5_MESAD_BANK1_Pos      (0U)

+#define SYSCFG_UR5_MESAD_BANK1_Msk      (0x1UL << SYSCFG_UR5_MESAD_BANK1_Pos)  /*!< 0x00000001 */

+#define SYSCFG_UR5_MESAD_BANK1          SYSCFG_UR5_MESAD_BANK1_Msk             /*!< Mass erase secured area disabled for bank 1 */

+#define SYSCFG_UR5_WRPN_BANK1_Pos       (16U)

+#define SYSCFG_UR5_WRPN_BANK1_Msk       (0xFFUL << SYSCFG_UR5_WRPN_BANK1_Pos)  /*!< 0x00FF0000 */

+#define SYSCFG_UR5_WRPN_BANK1           SYSCFG_UR5_WRPN_BANK1_Msk              /*!< Write protection for flash bank 1 */

+

+/******************  Bit definition for SYSCFG_UR6 register  *******************/

+#define SYSCFG_UR6_PABEG_BANK1_Pos      (0U)

+#define SYSCFG_UR6_PABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PABEG_BANK1_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR6_PABEG_BANK1          SYSCFG_UR6_PABEG_BANK1_Msk             /*!< Protected area start address for bank 1 */

+#define SYSCFG_UR6_PAEND_BANK1_Pos      (16U)

+#define SYSCFG_UR6_PAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PAEND_BANK1_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR6_PAEND_BANK1          SYSCFG_UR6_PAEND_BANK1_Msk             /*!< Protected area end address for bank 1 */

+

+/******************  Bit definition for SYSCFG_UR7 register  *******************/

+#define SYSCFG_UR7_SABEG_BANK1_Pos      (0U)

+#define SYSCFG_UR7_SABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SABEG_BANK1_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR7_SABEG_BANK1          SYSCFG_UR7_SABEG_BANK1_Msk             /*!< Secured area start address for bank 1 */

+#define SYSCFG_UR7_SAEND_BANK1_Pos      (16U)

+#define SYSCFG_UR7_SAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SAEND_BANK1_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR7_SAEND_BANK1          SYSCFG_UR7_SAEND_BANK1_Msk             /*!< Secured area end address for bank 1 */

+

+/******************  Bit definition for SYSCFG_UR8 register  *******************/

+#define SYSCFG_UR8_MEPAD_BANK2_Pos      (0U)

+#define SYSCFG_UR8_MEPAD_BANK2_Msk      (0x1UL << SYSCFG_UR8_MEPAD_BANK2_Pos)  /*!< 0x00000001 */

+#define SYSCFG_UR8_MEPAD_BANK2          SYSCFG_UR8_MEPAD_BANK2_Msk             /*!< Mass erase Protected area disabled for bank 2 */

+#define SYSCFG_UR8_MESAD_BANK2_Pos      (16U)

+#define SYSCFG_UR8_MESAD_BANK2_Msk      (0x1UL << SYSCFG_UR8_MESAD_BANK2_Pos)  /*!< 0x00010000 */

+#define SYSCFG_UR8_MESAD_BANK2          SYSCFG_UR8_MESAD_BANK2_Msk             /*!< Mass Erase Secured Area Disabled for bank 2 */

+

+/******************  Bit definition for SYSCFG_UR9 register  *******************/

+#define SYSCFG_UR9_WRPN_BANK2_Pos       (0U)

+#define SYSCFG_UR9_WRPN_BANK2_Msk       (0xFFUL << SYSCFG_UR9_WRPN_BANK2_Pos)  /*!< 0x000000FF */

+#define SYSCFG_UR9_WRPN_BANK2           SYSCFG_UR9_WRPN_BANK2_Msk              /*!< Write protection for flash bank 2 */

+#define SYSCFG_UR9_PABEG_BANK2_Pos      (16U)

+#define SYSCFG_UR9_PABEG_BANK2_Msk      (0xFFFUL << SYSCFG_UR9_PABEG_BANK2_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR9_PABEG_BANK2          SYSCFG_UR9_PABEG_BANK2_Msk             /*!< Protected area start address for bank 2 */

+

+/******************  Bit definition for SYSCFG_UR10 register  *******************/

+#define SYSCFG_UR10_PAEND_BANK2_Pos     (0U)

+#define SYSCFG_UR10_PAEND_BANK2_Msk     (0xFFFUL << SYSCFG_UR10_PAEND_BANK2_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR10_PAEND_BANK2         SYSCFG_UR10_PAEND_BANK2_Msk            /*!< Protected area end address for bank 2 */

+#define SYSCFG_UR10_SABEG_BANK2_Pos     (16U)

+#define SYSCFG_UR10_SABEG_BANK2_Msk     (0xFFFUL << SYSCFG_UR10_SABEG_BANK2_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR10_SABEG_BANK2         SYSCFG_UR10_SABEG_BANK2_Msk            /*!< Secured area start address for bank 2 */

+

+/******************  Bit definition for SYSCFG_UR11 register  *******************/

+#define SYSCFG_UR11_SAEND_BANK2_Pos     (0U)

+#define SYSCFG_UR11_SAEND_BANK2_Msk     (0xFFFUL << SYSCFG_UR11_SAEND_BANK2_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR11_SAEND_BANK2         SYSCFG_UR11_SAEND_BANK2_Msk            /*!< Secured area end address for bank 2 */

+#define SYSCFG_UR11_IWDG1M_Pos          (16U)

+#define SYSCFG_UR11_IWDG1M_Msk          (0x1UL << SYSCFG_UR11_IWDG1M_Pos)      /*!< 0x00010000 */

+#define SYSCFG_UR11_IWDG1M              SYSCFG_UR11_IWDG1M_Msk                 /*!< Independent Watchdog 1 mode (SW or HW) */

+

+/******************  Bit definition for SYSCFG_UR12 register  *******************/

+#define SYSCFG_UR12_IWDG2M_Pos          (0U)

+#define SYSCFG_UR12_IWDG2M_Msk          (0x1UL << SYSCFG_UR12_IWDG2M_Pos)      /*!< 0x00000001 */

+#define SYSCFG_UR12_IWDG2M              SYSCFG_UR12_IWDG2M_Msk                 /*!< Independent Watchdog 2 mode (SW or HW) */

+

+#define SYSCFG_UR12_SECURE_Pos          (16U)

+#define SYSCFG_UR12_SECURE_Msk          (0x1UL << SYSCFG_UR12_SECURE_Pos)      /*!< 0x00010000 */

+#define SYSCFG_UR12_SECURE              SYSCFG_UR12_SECURE_Msk                 /*!< Secure mode status */

+

+/******************  Bit definition for SYSCFG_UR13 register  *******************/

+#define SYSCFG_UR13_SDRS_Pos            (0U)

+#define SYSCFG_UR13_SDRS_Msk            (0x3UL << SYSCFG_UR13_SDRS_Pos)        /*!< 0x00000003 */

+#define SYSCFG_UR13_SDRS                SYSCFG_UR13_SDRS_Msk                   /*!< Secured DTCM RAM Size */

+#define SYSCFG_UR13_D1SBRST_Pos         (16U)

+#define SYSCFG_UR13_D1SBRST_Msk         (0x1UL << SYSCFG_UR13_D1SBRST_Pos)     /*!< 0x00010000 */

+#define SYSCFG_UR13_D1SBRST             SYSCFG_UR13_D1SBRST_Msk                /*!< D1 Standby reset */

+

+/******************  Bit definition for SYSCFG_UR14 register  *******************/

+#define SYSCFG_UR14_D1STPRST_Pos        (0U)

+#define SYSCFG_UR14_D1STPRST_Msk        (0x1UL << SYSCFG_UR14_D1STPRST_Pos)    /*!< 0x00000001 */

+#define SYSCFG_UR14_D1STPRST            SYSCFG_UR14_D1STPRST_Msk               /*!< D1 Stop Reset */

+#define SYSCFG_UR14_D2SBRST_Pos         (16U)

+#define SYSCFG_UR14_D2SBRST_Msk         (0x1UL << SYSCFG_UR14_D2SBRST_Pos)     /*!< 0x00010000 */

+#define SYSCFG_UR14_D2SBRST             SYSCFG_UR14_D2SBRST_Msk                /*!< D2 Standby Reset */

+

+/******************  Bit definition for SYSCFG_UR15 register  *******************/

+#define SYSCFG_UR15_D2STPRST_Pos        (0U)

+#define SYSCFG_UR15_D2STPRST_Msk        (0x1UL << SYSCFG_UR15_D2STPRST_Pos)    /*!< 0x00000001 */

+#define SYSCFG_UR15_D2STPRST            SYSCFG_UR15_D2STPRST_Msk               /*!< D2 Stop Reset */

+#define SYSCFG_UR15_FZIWDGSTB_Pos       (16U)

+#define SYSCFG_UR15_FZIWDGSTB_Msk       (0x1UL << SYSCFG_UR15_FZIWDGSTB_Pos)   /*!< 0x00010000 */

+#define SYSCFG_UR15_FZIWDGSTB           SYSCFG_UR15_FZIWDGSTB_Msk              /*!< Freeze independent watchdogs in Standby mode */

+

+/******************  Bit definition for SYSCFG_UR16 register  *******************/

+#define SYSCFG_UR16_FZIWDGSTP_Pos       (0U)

+#define SYSCFG_UR16_FZIWDGSTP_Msk       (0x1UL << SYSCFG_UR16_FZIWDGSTP_Pos)   /*!< 0x00000001 */

+#define SYSCFG_UR16_FZIWDGSTP           SYSCFG_UR16_FZIWDGSTP_Msk              /*!< Freeze independent watchdogs in Stop mode */

+#define SYSCFG_UR16_PKP_Pos             (16U)

+#define SYSCFG_UR16_PKP_Msk             (0x1UL << SYSCFG_UR16_PKP_Pos)         /*!< 0x00010000 */

+#define SYSCFG_UR16_PKP                 SYSCFG_UR16_PKP_Msk                    /*!< Private key programmed */

+

+/******************  Bit definition for SYSCFG_UR17 register  *******************/

+#define SYSCFG_UR17_IOHSLV_Pos          (0U)

+#define SYSCFG_UR17_IOHSLV_Msk          (0x1UL << SYSCFG_UR17_IOHSLV_Pos)      /*!< 0x00000001 */

+#define SYSCFG_UR17_IOHSLV              SYSCFG_UR17_IOHSLV_Msk                 /*!< I/O high speed / low voltage */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    TIM                                     */

+/*                                                                            */

+/******************************************************************************/

+#define TIM_BREAK_INPUT_SUPPORT             /*!<TIM Break input feature */

+

+/*******************  Bit definition for TIM_CR1 register  ********************/

+#define TIM_CR1_CEN_Pos           (0U)

+#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */

+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */

+#define TIM_CR1_UDIS_Pos          (1U)

+#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */

+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */

+#define TIM_CR1_URS_Pos           (2U)

+#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */

+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */

+#define TIM_CR1_OPM_Pos           (3U)

+#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */

+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */

+#define TIM_CR1_DIR_Pos           (4U)

+#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */

+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */

+

+#define TIM_CR1_CMS_Pos           (5U)

+#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */

+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */

+#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */

+#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */

+

+#define TIM_CR1_ARPE_Pos          (7U)

+#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */

+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */

+

+#define TIM_CR1_CKD_Pos           (8U)

+#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */

+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */

+#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */

+#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */

+

+#define TIM_CR1_UIFREMAP_Pos      (11U)

+#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */

+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */

+

+/*******************  Bit definition for TIM_CR2 register  ********************/

+#define TIM_CR2_CCPC_Pos          (0U)

+#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */

+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */

+#define TIM_CR2_CCUS_Pos          (2U)

+#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */

+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */

+#define TIM_CR2_CCDS_Pos          (3U)

+#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */

+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */

+

+#define TIM_CR2_MMS_Pos           (4U)

+#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */

+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */

+#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */

+#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */

+#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */

+

+#define TIM_CR2_TI1S_Pos          (7U)

+#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */

+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */

+#define TIM_CR2_OIS1_Pos          (8U)

+#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */

+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */

+#define TIM_CR2_OIS1N_Pos         (9U)

+#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */

+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */

+#define TIM_CR2_OIS2_Pos          (10U)

+#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */

+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */

+#define TIM_CR2_OIS2N_Pos         (11U)

+#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */

+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */

+#define TIM_CR2_OIS3_Pos          (12U)

+#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */

+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */

+#define TIM_CR2_OIS3N_Pos         (13U)

+#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */

+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */

+#define TIM_CR2_OIS4_Pos          (14U)

+#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */

+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */

+#define TIM_CR2_OIS5_Pos          (16U)

+#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */

+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */

+#define TIM_CR2_OIS6_Pos          (17U)

+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */

+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */

+

+#define TIM_CR2_MMS2_Pos          (20U)

+#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */

+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */

+#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */

+#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */

+#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */

+#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */

+

+/*******************  Bit definition for TIM_SMCR register  *******************/

+#define TIM_SMCR_SMS_Pos          (0U)

+#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */

+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */

+#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */

+#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */

+#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */

+#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */

+

+#define TIM_SMCR_TS_Pos           (4U)

+#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */

+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[4:0] bits (Trigger selection) */

+#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)                /*!< 0x00000010 */

+#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)                /*!< 0x00000020 */

+#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)                /*!< 0x00000040 */

+#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)                /*!< 0x00100000 */

+#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)                /*!< 0x00200000 */

+

+#define TIM_SMCR_MSM_Pos          (7U)

+#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */

+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */

+

+#define TIM_SMCR_ETF_Pos          (8U)

+#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */

+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */

+#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */

+#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */

+#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */

+#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */

+

+#define TIM_SMCR_ETPS_Pos         (12U)

+#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */

+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */

+#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */

+#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */

+

+#define TIM_SMCR_ECE_Pos          (14U)

+#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */

+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */

+#define TIM_SMCR_ETP_Pos          (15U)

+#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */

+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */

+

+/*******************  Bit definition for TIM_DIER register  *******************/

+#define TIM_DIER_UIE_Pos          (0U)

+#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */

+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */

+#define TIM_DIER_CC1IE_Pos        (1U)

+#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */

+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */

+#define TIM_DIER_CC2IE_Pos        (2U)

+#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */

+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */

+#define TIM_DIER_CC3IE_Pos        (3U)

+#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */

+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */

+#define TIM_DIER_CC4IE_Pos        (4U)

+#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */

+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */

+#define TIM_DIER_COMIE_Pos        (5U)

+#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */

+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */

+#define TIM_DIER_TIE_Pos          (6U)

+#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */

+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */

+#define TIM_DIER_BIE_Pos          (7U)

+#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */

+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */

+#define TIM_DIER_UDE_Pos          (8U)

+#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */

+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */

+#define TIM_DIER_CC1DE_Pos        (9U)

+#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */

+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */

+#define TIM_DIER_CC2DE_Pos        (10U)

+#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */

+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */

+#define TIM_DIER_CC3DE_Pos        (11U)

+#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */

+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */

+#define TIM_DIER_CC4DE_Pos        (12U)

+#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */

+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */

+#define TIM_DIER_COMDE_Pos        (13U)

+#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */

+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */

+#define TIM_DIER_TDE_Pos          (14U)

+#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */

+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */

+

+/********************  Bit definition for TIM_SR register  ********************/

+#define TIM_SR_UIF_Pos            (0U)

+#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */

+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */

+#define TIM_SR_CC1IF_Pos          (1U)

+#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */

+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */

+#define TIM_SR_CC2IF_Pos          (2U)

+#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */

+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */

+#define TIM_SR_CC3IF_Pos          (3U)

+#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */

+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */

+#define TIM_SR_CC4IF_Pos          (4U)

+#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */

+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */

+#define TIM_SR_COMIF_Pos          (5U)

+#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */

+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */

+#define TIM_SR_TIF_Pos            (6U)

+#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */

+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */

+#define TIM_SR_BIF_Pos            (7U)

+#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */

+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */

+#define TIM_SR_B2IF_Pos           (8U)

+#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */

+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break2 interrupt Flag */

+#define TIM_SR_CC1OF_Pos          (9U)

+#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */

+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */

+#define TIM_SR_CC2OF_Pos          (10U)

+#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */

+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */

+#define TIM_SR_CC3OF_Pos          (11U)

+#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */

+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */

+#define TIM_SR_CC4OF_Pos          (12U)

+#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */

+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */

+#define TIM_SR_CC5IF_Pos          (16U)

+#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */

+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */

+#define TIM_SR_CC6IF_Pos          (17U)

+#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */

+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */

+#define TIM_SR_SBIF_Pos           (13U)

+#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */

+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!< System Break Flag */

+

+/*******************  Bit definition for TIM_EGR register  ********************/

+#define TIM_EGR_UG_Pos            (0U)

+#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */

+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */

+#define TIM_EGR_CC1G_Pos          (1U)

+#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */

+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */

+#define TIM_EGR_CC2G_Pos          (2U)

+#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */

+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */

+#define TIM_EGR_CC3G_Pos          (3U)

+#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */

+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */

+#define TIM_EGR_CC4G_Pos          (4U)

+#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */

+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */

+#define TIM_EGR_COMG_Pos          (5U)

+#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */

+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */

+#define TIM_EGR_TG_Pos            (6U)

+#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */

+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */

+#define TIM_EGR_BG_Pos            (7U)

+#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */

+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */

+#define TIM_EGR_B2G_Pos           (8U)

+#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */

+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break Generation */

+

+

+/******************  Bit definition for TIM_CCMR1 register  *******************/

+#define TIM_CCMR1_CC1S_Pos        (0U)

+#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */

+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */

+#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */

+#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */

+

+#define TIM_CCMR1_OC1FE_Pos       (2U)

+#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */

+#define TIM_CCMR1_OC1PE_Pos       (3U)

+#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */

+

+#define TIM_CCMR1_OC1M_Pos        (4U)

+#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */

+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */

+#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */

+#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */

+#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */

+#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR1_OC1CE_Pos       (7U)

+#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */

+

+#define TIM_CCMR1_CC2S_Pos        (8U)

+#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */

+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */

+#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */

+#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */

+

+#define TIM_CCMR1_OC2FE_Pos       (10U)

+#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */

+#define TIM_CCMR1_OC2PE_Pos       (11U)

+#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */

+

+#define TIM_CCMR1_OC2M_Pos        (12U)

+#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */

+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */

+#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */

+#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */

+#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */

+#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */

+

+#define TIM_CCMR1_OC2CE_Pos       (15U)

+#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */

+

+/*----------------------------------------------------------------------------*/

+

+#define TIM_CCMR1_IC1PSC_Pos      (2U)

+#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */

+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */

+#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */

+

+#define TIM_CCMR1_IC1F_Pos        (4U)

+#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */

+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */

+#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */

+

+#define TIM_CCMR1_IC2PSC_Pos      (10U)

+#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */

+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */

+#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */

+

+#define TIM_CCMR1_IC2F_Pos        (12U)

+#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */

+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */

+#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */

+

+/******************  Bit definition for TIM_CCMR2 register  *******************/

+#define TIM_CCMR2_CC3S_Pos        (0U)

+#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */

+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */

+#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */

+#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */

+

+#define TIM_CCMR2_OC3FE_Pos       (2U)

+#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */

+#define TIM_CCMR2_OC3PE_Pos       (3U)

+#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */

+

+#define TIM_CCMR2_OC3M_Pos        (4U)

+#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */

+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */

+#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR2_OC3CE_Pos       (7U)

+#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */

+

+#define TIM_CCMR2_CC4S_Pos        (8U)

+#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */

+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */

+#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */

+#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */

+

+#define TIM_CCMR2_OC4FE_Pos       (10U)

+#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */

+#define TIM_CCMR2_OC4PE_Pos       (11U)

+#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */

+

+#define TIM_CCMR2_OC4M_Pos        (12U)

+#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */

+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */

+#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */

+

+#define TIM_CCMR2_OC4CE_Pos       (15U)

+#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */

+

+/*----------------------------------------------------------------------------*/

+

+#define TIM_CCMR2_IC3PSC_Pos      (2U)

+#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */

+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */

+#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */

+

+#define TIM_CCMR2_IC3F_Pos        (4U)

+#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */

+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */

+#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */

+

+#define TIM_CCMR2_IC4PSC_Pos      (10U)

+#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */

+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */

+#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */

+

+#define TIM_CCMR2_IC4F_Pos        (12U)

+#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */

+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */

+#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */

+

+/*******************  Bit definition for TIM_CCER register  *******************/

+#define TIM_CCER_CC1E_Pos         (0U)

+#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */

+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */

+#define TIM_CCER_CC1P_Pos         (1U)

+#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */

+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */

+#define TIM_CCER_CC1NE_Pos        (2U)

+#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */

+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */

+#define TIM_CCER_CC1NP_Pos        (3U)

+#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */

+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */

+#define TIM_CCER_CC2E_Pos         (4U)

+#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */

+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */

+#define TIM_CCER_CC2P_Pos         (5U)

+#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */

+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */

+#define TIM_CCER_CC2NE_Pos        (6U)

+#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */

+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */

+#define TIM_CCER_CC2NP_Pos        (7U)

+#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */

+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */

+#define TIM_CCER_CC3E_Pos         (8U)

+#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */

+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */

+#define TIM_CCER_CC3P_Pos         (9U)

+#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */

+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */

+#define TIM_CCER_CC3NE_Pos        (10U)

+#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */

+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */

+#define TIM_CCER_CC3NP_Pos        (11U)

+#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */

+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */

+#define TIM_CCER_CC4E_Pos         (12U)

+#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */

+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */

+#define TIM_CCER_CC4P_Pos         (13U)

+#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */

+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */

+#define TIM_CCER_CC4NP_Pos        (15U)

+#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */

+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */

+#define TIM_CCER_CC5E_Pos         (16U)

+#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */

+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */

+#define TIM_CCER_CC5P_Pos         (17U)

+#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */

+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */

+#define TIM_CCER_CC6E_Pos         (20U)

+#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */

+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */

+#define TIM_CCER_CC6P_Pos         (21U)

+#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */

+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */

+/*******************  Bit definition for TIM_CNT register  ********************/

+#define TIM_CNT_CNT_Pos           (0U)

+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */

+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */

+#define TIM_CNT_UIFCPY_Pos        (31U)

+#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */

+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy */

+/*******************  Bit definition for TIM_PSC register  ********************/

+#define TIM_PSC_PSC_Pos           (0U)

+#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */

+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */

+

+/*******************  Bit definition for TIM_ARR register  ********************/

+#define TIM_ARR_ARR_Pos           (0U)

+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */

+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */

+

+/*******************  Bit definition for TIM_RCR register  ********************/

+#define TIM_RCR_REP_Pos           (0U)

+#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                  /*!< 0x000000FF */

+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */

+

+/*******************  Bit definition for TIM_CCR1 register  *******************/

+#define TIM_CCR1_CCR1_Pos         (0U)

+#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */

+

+/*******************  Bit definition for TIM_CCR2 register  *******************/

+#define TIM_CCR2_CCR2_Pos         (0U)

+#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */

+

+/*******************  Bit definition for TIM_CCR3 register  *******************/

+#define TIM_CCR3_CCR3_Pos         (0U)

+#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */

+

+/*******************  Bit definition for TIM_CCR4 register  *******************/

+#define TIM_CCR4_CCR4_Pos         (0U)

+#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */

+

+/*******************  Bit definition for TIM_CCR5 register  *******************/

+#define TIM_CCR5_CCR5_Pos         (0U)

+#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */

+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */

+#define TIM_CCR5_GC5C1_Pos        (29U)

+#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */

+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */

+#define TIM_CCR5_GC5C2_Pos        (30U)

+#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */

+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */

+#define TIM_CCR5_GC5C3_Pos        (31U)

+#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */

+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */

+

+/*******************  Bit definition for TIM_CCR6 register  *******************/

+#define TIM_CCR6_CCR6_Pos         (0U)

+#define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */

+

+/*******************  Bit definition for TIM_BDTR register  *******************/

+#define TIM_BDTR_DTG_Pos          (0U)

+#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */

+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */

+#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */

+#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */

+#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */

+#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */

+#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */

+#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */

+#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */

+#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */

+

+#define TIM_BDTR_LOCK_Pos         (8U)

+#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */

+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */

+#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */

+#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */

+

+#define TIM_BDTR_OSSI_Pos         (10U)

+#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */

+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */

+#define TIM_BDTR_OSSR_Pos         (11U)

+#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */

+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */

+#define TIM_BDTR_BKE_Pos          (12U)

+#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */

+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break1 */

+#define TIM_BDTR_BKP_Pos          (13U)

+#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */

+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break1 */

+#define TIM_BDTR_AOE_Pos          (14U)

+#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */

+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */

+#define TIM_BDTR_MOE_Pos          (15U)

+#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */

+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */

+

+#define TIM_BDTR_BKF_Pos          (16U)

+#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */

+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break1 */

+#define TIM_BDTR_BK2F_Pos         (20U)

+#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */

+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break2 */

+

+#define TIM_BDTR_BK2E_Pos         (24U)

+#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */

+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break2 */

+#define TIM_BDTR_BK2P_Pos         (25U)

+#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */

+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */

+

+/*******************  Bit definition for TIM_DCR register  ********************/

+#define TIM_DCR_DBA_Pos           (0U)

+#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */

+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */

+#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */

+#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */

+#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */

+#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */

+#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */

+

+#define TIM_DCR_DBL_Pos           (8U)

+#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */

+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */

+#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */

+#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */

+#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */

+#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */

+#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */

+

+/*******************  Bit definition for TIM_DMAR register  *******************/

+#define TIM_DMAR_DMAB_Pos         (0U)

+#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */

+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */

+

+/******************  Bit definition for TIM_CCMR3 register  *******************/

+#define TIM_CCMR3_OC5FE_Pos       (2U)

+#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */

+#define TIM_CCMR3_OC5PE_Pos       (3U)

+#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */

+

+#define TIM_CCMR3_OC5M_Pos        (4U)

+#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */

+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */

+#define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR3_OC5CE_Pos       (7U)

+#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */

+

+#define TIM_CCMR3_OC6FE_Pos       (10U)

+#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 4 Fast enable */

+#define TIM_CCMR3_OC6PE_Pos       (11U)

+#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */

+

+#define TIM_CCMR3_OC6M_Pos        (12U)

+#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */

+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */

+#define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */

+

+#define TIM_CCMR3_OC6CE_Pos       (15U)

+#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 4 Clear Enable */

+/*******************  Bit definition for TIM1_AF1 register  *********************/

+#define TIM1_AF1_BKINE_Pos        (0U)

+#define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */

+#define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */

+#define TIM1_AF1_BKCMP1E_Pos      (1U)

+#define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */

+#define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM1_AF1_BKCMP2E_Pos      (2U)

+#define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */

+#define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit */

+#define TIM1_AF1_BKDF1BK0E_Pos    (8U)

+#define TIM1_AF1_BKDF1BK0E_Msk    (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)            /*!< 0x00000100 */

+#define TIM1_AF1_BKDF1BK0E        TIM1_AF1_BKDF1BK0E_Msk                       /*!<BKDF1BK0E Break input DFSDM Break 0 */

+#define TIM1_AF1_BKINP_Pos        (9U)

+#define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */

+#define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */

+#define TIM1_AF1_BKCMP1P_Pos      (10U)

+#define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */

+#define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM1_AF1_BKCMP2P_Pos      (11U)

+#define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */

+#define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */

+

+#define TIM1_AF1_ETRSEL_Pos       (14U)

+#define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */

+#define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */

+#define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00004000 */

+#define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00008000 */

+#define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00010000 */

+#define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM1_AF2 register  *********************/

+#define TIM1_AF2_BK2INE_Pos       (0U)

+#define TIM1_AF2_BK2INE_Msk       (0x1UL << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */

+#define TIM1_AF2_BK2INE           TIM1_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */

+#define TIM1_AF2_BK2CMP1E_Pos     (1U)

+#define TIM1_AF2_BK2CMP1E_Msk     (0x1UL << TIM1_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */

+#define TIM1_AF2_BK2CMP1E         TIM1_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */

+#define TIM1_AF2_BK2CMP2E_Pos     (2U)

+#define TIM1_AF2_BK2CMP2E_Msk     (0x1UL << TIM1_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */

+#define TIM1_AF2_BK2CMP2E         TIM1_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */

+#define TIM1_AF2_BK2DFBK1E_Pos    (8U)

+#define TIM1_AF2_BK2DFBK1E_Msk    (0x1UL << TIM1_AF2_BK2DFBK1E_Pos)            /*!< 0x00000100 */

+#define TIM1_AF2_BK2DFBK1E        TIM1_AF2_BK2DFBK1E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 1 */

+#define TIM1_AF2_BK2INP_Pos       (9U)

+#define TIM1_AF2_BK2INP_Msk       (0x1UL << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */

+#define TIM1_AF2_BK2INP           TIM1_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */

+#define TIM1_AF2_BK2CMP1P_Pos     (10U)

+#define TIM1_AF2_BK2CMP1P_Msk     (0x1UL << TIM1_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */

+#define TIM1_AF2_BK2CMP1P         TIM1_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */

+#define TIM1_AF2_BK2CMP2P_Pos     (11U)

+#define TIM1_AF2_BK2CMP2P_Msk     (0x1UL << TIM1_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */

+#define TIM1_AF2_BK2CMP2P         TIM1_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */

+

+/*******************  Bit definition for TIM_TISEL register  *********************/

+#define TIM_TISEL_TI1SEL_Pos      (0U)

+#define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */

+#define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/

+#define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000001 */

+#define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000002 */

+#define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000004 */

+#define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000008 */

+

+#define TIM_TISEL_TI2SEL_Pos      (8U)

+#define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */

+#define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/

+#define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000100 */

+#define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000200 */

+#define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000400 */

+#define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000800 */

+

+#define TIM_TISEL_TI3SEL_Pos      (16U)

+#define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */

+#define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/

+#define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00010000 */

+#define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00020000 */

+#define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00040000 */

+#define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00080000 */

+

+#define TIM_TISEL_TI4SEL_Pos      (24U)

+#define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */

+#define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/

+#define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x01000000 */

+#define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x02000000 */

+#define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x04000000 */

+#define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x08000000 */

+

+/*******************  Bit definition for TIM8_AF1 register  *********************/

+#define TIM8_AF1_BKINE_Pos        (0U)

+#define TIM8_AF1_BKINE_Msk        (0x1UL << TIM8_AF1_BKINE_Pos)                /*!< 0x00000001 */

+#define TIM8_AF1_BKINE            TIM8_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */

+#define TIM8_AF1_BKCMP1E_Pos      (1U)

+#define TIM8_AF1_BKCMP1E_Msk      (0x1UL << TIM8_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */

+#define TIM8_AF1_BKCMP1E          TIM8_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM8_AF1_BKCMP2E_Pos      (2U)

+#define TIM8_AF1_BKCMP2E_Msk      (0x1UL << TIM8_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */

+#define TIM8_AF1_BKCMP2E          TIM8_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM8_AF1_BKDFBK2E_Pos     (8U)

+#define TIM8_AF1_BKDFBK2E_Msk     (0x1UL << TIM8_AF1_BKDFBK2E_Pos)             /*!< 0x00000100 */

+#define TIM8_AF1_BKDFBK2E         TIM8_AF1_BKDFBK2E_Msk                        /*!<BKDFBK2E Break input DFSDM Break 2 */

+#define TIM8_AF1_BKINP_Pos        (9U)

+#define TIM8_AF1_BKINP_Msk        (0x1UL << TIM8_AF1_BKINP_Pos)                /*!< 0x00000200 */

+#define TIM8_AF1_BKINP            TIM8_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */

+#define TIM8_AF1_BKCMP1P_Pos      (10U)

+#define TIM8_AF1_BKCMP1P_Msk      (0x1UL << TIM8_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */

+#define TIM8_AF1_BKCMP1P          TIM8_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM8_AF1_BKCMP2P_Pos      (11U)

+#define TIM8_AF1_BKCMP2P_Msk      (0x1UL << TIM8_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */

+#define TIM8_AF1_BKCMP2P          TIM8_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */

+

+#define TIM8_AF1_ETRSEL_Pos       (14U)

+#define TIM8_AF1_ETRSEL_Msk       (0xFUL << TIM8_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */

+#define TIM8_AF1_ETRSEL           TIM8_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */

+#define TIM8_AF1_ETRSEL_0         (0x1UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00004000 */

+#define TIM8_AF1_ETRSEL_1         (0x2UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00008000 */

+#define TIM8_AF1_ETRSEL_2         (0x4UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00010000 */

+#define TIM8_AF1_ETRSEL_3         (0x8UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00020000 */

+/*******************  Bit definition for TIM8_AF2 register  *********************/

+#define TIM8_AF2_BK2INE_Pos       (0U)

+#define TIM8_AF2_BK2INE_Msk       (0x1UL << TIM8_AF2_BK2INE_Pos)               /*!< 0x00000001 */

+#define TIM8_AF2_BK2INE           TIM8_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */

+#define TIM8_AF2_BK2CMP1E_Pos     (1U)

+#define TIM8_AF2_BK2CMP1E_Msk     (0x1UL << TIM8_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */

+#define TIM8_AF2_BK2CMP1E         TIM8_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */

+#define TIM8_AF2_BK2CMP2E_Pos     (2U)

+#define TIM8_AF2_BK2CMP2E_Msk     (0x1UL << TIM8_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */

+#define TIM8_AF2_BK2CMP2E         TIM8_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */

+#define TIM8_AF2_BK2DFBK3E_Pos    (8U)

+#define TIM8_AF2_BK2DFBK3E_Msk    (0x1UL << TIM8_AF2_BK2DFBK3E_Pos)            /*!< 0x00000100 */

+#define TIM8_AF2_BK2DFBK3E        TIM8_AF2_BK2DFBK3E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 3 */

+#define TIM8_AF2_BK2INP_Pos       (9U)

+#define TIM8_AF2_BK2INP_Msk       (0x1UL << TIM8_AF2_BK2INP_Pos)               /*!< 0x00000200 */

+#define TIM8_AF2_BK2INP           TIM8_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */

+#define TIM8_AF2_BK2CMP1P_Pos     (10U)

+#define TIM8_AF2_BK2CMP1P_Msk     (0x1UL << TIM8_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */

+#define TIM8_AF2_BK2CMP1P         TIM8_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */

+#define TIM8_AF2_BK2CMP2P_Pos     (11U)

+#define TIM8_AF2_BK2CMP2P_Msk     (0x1UL << TIM8_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */

+#define TIM8_AF2_BK2CMP2P         TIM8_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */

+

+/*******************  Bit definition for TIM2_AF1 register  *********************/

+#define TIM2_AF1_ETRSEL_Pos      (14U)

+#define TIM2_AF1_ETRSEL_Msk      (0xFUL << TIM2_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM2_AF1_ETRSEL          TIM2_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */

+#define TIM2_AF1_ETRSEL_0        (0x1UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM2_AF1_ETRSEL_1        (0x2UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM2_AF1_ETRSEL_2        (0x4UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM2_AF1_ETRSEL_3        (0x8UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM3_AF1 register  *********************/

+#define TIM3_AF1_ETRSEL_Pos      (14U)

+#define TIM3_AF1_ETRSEL_Msk      (0xFUL << TIM3_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM3_AF1_ETRSEL          TIM3_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */

+#define TIM3_AF1_ETRSEL_0        (0x1UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM3_AF1_ETRSEL_1        (0x2UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM3_AF1_ETRSEL_2        (0x4UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM3_AF1_ETRSEL_3        (0x8UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM5_AF1 register  *********************/

+#define TIM5_AF1_ETRSEL_Pos      (14U)

+#define TIM5_AF1_ETRSEL_Msk      (0xFUL << TIM5_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM5_AF1_ETRSEL          TIM5_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */

+#define TIM5_AF1_ETRSEL_0        (0x1UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM5_AF1_ETRSEL_1        (0x2UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM5_AF1_ETRSEL_2        (0x4UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM5_AF1_ETRSEL_3        (0x8UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM15_AF1 register  *********************/

+#define TIM15_AF1_BKINE_Pos        (0U)

+#define TIM15_AF1_BKINE_Msk        (0x1UL << TIM15_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM15_AF1_BKINE            TIM15_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM15_AF1_BKCMP1E_Pos      (1U)

+#define TIM15_AF1_BKCMP1E_Msk      (0x1UL << TIM15_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM15_AF1_BKCMP1E          TIM15_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM15_AF1_BKCMP2E_Pos      (2U)

+#define TIM15_AF1_BKCMP2E_Msk      (0x1UL << TIM15_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM15_AF1_BKCMP2E          TIM15_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM15_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM15_AF1_BKDF1BK2E_Msk    (0x1UL << TIM15_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM15_AF1_BKDF1BK2E        TIM15_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[0] enable */

+#define TIM15_AF1_BKINP_Pos        (9U)

+#define TIM15_AF1_BKINP_Msk        (0x1UL << TIM15_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM15_AF1_BKINP            TIM15_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM15_AF1_BKCMP1P_Pos      (10U)

+#define TIM15_AF1_BKCMP1P_Msk      (0x1UL << TIM15_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM15_AF1_BKCMP1P          TIM15_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM15_AF1_BKCMP2P_Pos      (11U)

+#define TIM15_AF1_BKCMP2P_Msk      (0x1UL << TIM15_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM15_AF1_BKCMP2P          TIM15_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/*******************  Bit definition for TIM16_ register  *********************/

+#define TIM16_AF1_BKINE_Pos        (0U)

+#define TIM16_AF1_BKINE_Msk        (0x1UL << TIM16_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM16_AF1_BKINE            TIM16_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM16_AF1_BKCMP1E_Pos      (1U)

+#define TIM16_AF1_BKCMP1E_Msk      (0x1UL << TIM16_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM16_AF1_BKCMP1E          TIM16_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM16_AF1_BKCMP2E_Pos      (2U)

+#define TIM16_AF1_BKCMP2E_Msk      (0x1UL << TIM16_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM16_AF1_BKCMP2E          TIM16_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM16_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM16_AF1_BKDF1BK2E_Msk    (0x1UL << TIM16_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM16_AF1_BKDF1BK2E        TIM16_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[1] enable */

+#define TIM16_AF1_BKINP_Pos        (9U)

+#define TIM16_AF1_BKINP_Msk        (0x1UL << TIM16_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM16_AF1_BKINP            TIM16_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM16_AF1_BKCMP1P_Pos      (10U)

+#define TIM16_AF1_BKCMP1P_Msk      (0x1UL << TIM16_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM16_AF1_BKCMP1P          TIM16_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM16_AF1_BKCMP2P_Pos      (11U)

+#define TIM16_AF1_BKCMP2P_Msk      (0x1UL << TIM16_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM16_AF1_BKCMP2P          TIM16_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/*******************  Bit definition for TIM17_AF1 register  *********************/

+#define TIM17_AF1_BKINE_Pos        (0U)

+#define TIM17_AF1_BKINE_Msk        (0x1UL << TIM17_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM17_AF1_BKINE            TIM17_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM17_AF1_BKCMP1E_Pos      (1U)

+#define TIM17_AF1_BKCMP1E_Msk      (0x1UL << TIM17_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM17_AF1_BKCMP1E          TIM17_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM17_AF1_BKCMP2E_Pos      (2U)

+#define TIM17_AF1_BKCMP2E_Msk      (0x1UL << TIM17_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM17_AF1_BKCMP2E          TIM17_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM17_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM17_AF1_BKDF1BK2E_Msk    (0x1UL << TIM17_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM17_AF1_BKDF1BK2E        TIM17_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[2] enable */

+#define TIM17_AF1_BKINP_Pos        (9U)

+#define TIM17_AF1_BKINP_Msk        (0x1UL << TIM17_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM17_AF1_BKINP            TIM17_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM17_AF1_BKCMP1P_Pos      (10U)

+#define TIM17_AF1_BKCMP1P_Msk      (0x1UL << TIM17_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM17_AF1_BKCMP1P          TIM17_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM17_AF1_BKCMP2P_Pos      (11U)

+#define TIM17_AF1_BKCMP2P_Msk      (0x1UL << TIM17_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM17_AF1_BKCMP2P          TIM17_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Low Power Timer (LPTTIM)                           */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for LPTIM_ISR register  *******************/

+#define LPTIM_ISR_CMPM_Pos          (0U)

+#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */

+#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */

+#define LPTIM_ISR_ARRM_Pos          (1U)

+#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */

+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */

+#define LPTIM_ISR_EXTTRIG_Pos       (2U)

+#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */

+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */

+#define LPTIM_ISR_CMPOK_Pos         (3U)

+#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */

+#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */

+#define LPTIM_ISR_ARROK_Pos         (4U)

+#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */

+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */

+#define LPTIM_ISR_UP_Pos            (5U)

+#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */

+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */

+#define LPTIM_ISR_DOWN_Pos          (6U)

+#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */

+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */

+

+/******************  Bit definition for LPTIM_ICR register  *******************/

+#define LPTIM_ICR_CMPMCF_Pos        (0U)

+#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */

+#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */

+#define LPTIM_ICR_ARRMCF_Pos        (1U)

+#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */

+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */

+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)

+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */

+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */

+#define LPTIM_ICR_CMPOKCF_Pos       (3U)

+#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */

+#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */

+#define LPTIM_ICR_ARROKCF_Pos       (4U)

+#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */

+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */

+#define LPTIM_ICR_UPCF_Pos          (5U)

+#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */

+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */

+#define LPTIM_ICR_DOWNCF_Pos        (6U)

+#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */

+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */

+

+/******************  Bit definition for LPTIM_IER register ********************/

+#define LPTIM_IER_CMPMIE_Pos        (0U)

+#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */

+#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */

+#define LPTIM_IER_ARRMIE_Pos        (1U)

+#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */

+#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */

+#define LPTIM_IER_EXTTRIGIE_Pos     (2U)

+#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */

+#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */

+#define LPTIM_IER_CMPOKIE_Pos       (3U)

+#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */

+#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */

+#define LPTIM_IER_ARROKIE_Pos       (4U)

+#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */

+#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */

+#define LPTIM_IER_UPIE_Pos          (5U)

+#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */

+#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */

+#define LPTIM_IER_DOWNIE_Pos        (6U)

+#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */

+#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */

+

+/******************  Bit definition for LPTIM_CFGR register *******************/

+#define LPTIM_CFGR_CKSEL_Pos        (0U)

+#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */

+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */

+

+#define LPTIM_CFGR_CKPOL_Pos        (1U)

+#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */

+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */

+#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */

+#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */

+

+#define LPTIM_CFGR_CKFLT_Pos        (3U)

+#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */

+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */

+#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */

+#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */

+

+#define LPTIM_CFGR_TRGFLT_Pos       (6U)

+#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */

+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */

+#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */

+#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */

+

+#define LPTIM_CFGR_PRESC_Pos        (9U)

+#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */

+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */

+#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */

+#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */

+#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */

+

+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)

+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */

+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */

+#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */

+#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */

+#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */

+

+#define LPTIM_CFGR_TRIGEN_Pos       (17U)

+#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */

+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */

+#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */

+#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */

+

+#define LPTIM_CFGR_TIMOUT_Pos       (19U)

+#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */

+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */

+#define LPTIM_CFGR_WAVE_Pos         (20U)

+#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */

+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */

+#define LPTIM_CFGR_WAVPOL_Pos       (21U)

+#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */

+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */

+#define LPTIM_CFGR_PRELOAD_Pos      (22U)

+#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */

+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */

+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)

+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */

+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */

+#define LPTIM_CFGR_ENC_Pos          (24U)

+#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */

+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */

+

+/******************  Bit definition for LPTIM_CR register  ********************/

+#define LPTIM_CR_ENABLE_Pos         (0U)

+#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */

+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */

+#define LPTIM_CR_SNGSTRT_Pos        (1U)

+#define LPTIM_CR_SNGSTRT_Msk        (0x40001UL << LPTIM_CR_SNGSTRT_Pos)        /*!< 0x00080002 */

+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */

+#define LPTIM_CR_CNTSTRT_Pos        (2U)

+#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */

+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */

+#define LPTIM_CR_COUNTRST_Pos       (3U)

+#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */

+#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Timer Counter reset in synchronous mode*/

+#define LPTIM_CR_RSTARE_Pos         (4U)

+#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */

+#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Timer Counter reset after read enable (asynchronously)*/

+

+

+/******************  Bit definition for LPTIM_CMP register  *******************/

+#define LPTIM_CMP_CMP_Pos           (0U)

+#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */

+

+/******************  Bit definition for LPTIM_ARR register  *******************/

+#define LPTIM_ARR_ARR_Pos           (0U)

+#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */

+

+/******************  Bit definition for LPTIM_CNT register  *******************/

+#define LPTIM_CNT_CNT_Pos           (0U)

+#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */

+

+/******************  Bit definition for LPTIM_CFGR2 register  *****************/

+#define LPTIM_CFGR2_IN1SEL_Pos      (0U)

+#define LPTIM_CFGR2_IN1SEL_Msk      (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000003 */

+#define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< IN1SEL[1:0] bits (Remap selection) */

+#define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000001 */

+#define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000002 */

+#define LPTIM_CFGR2_IN2SEL_Pos      (4U)

+#define LPTIM_CFGR2_IN2SEL_Msk      (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000030 */

+#define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< IN2SEL[5:4] bits (Remap selection) */

+#define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000010 */

+#define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000020 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      Analog Comparators (COMP)                             */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for COMP_SR register  ********************/

+#define COMP_SR_C1VAL_Pos            (0U)

+#define COMP_SR_C1VAL_Msk            (0x1UL << COMP_SR_C1VAL_Pos)              /*!< 0x00000001 */

+#define COMP_SR_C1VAL                COMP_SR_C1VAL_Msk

+#define COMP_SR_C2VAL_Pos            (1U)

+#define COMP_SR_C2VAL_Msk            (0x1UL << COMP_SR_C2VAL_Pos)              /*!< 0x00000002 */

+#define COMP_SR_C2VAL                COMP_SR_C2VAL_Msk

+#define COMP_SR_C1IF_Pos             (16U)

+#define COMP_SR_C1IF_Msk             (0x1UL << COMP_SR_C1IF_Pos)               /*!< 0x00010000 */

+#define COMP_SR_C1IF                 COMP_SR_C1IF_Msk

+#define COMP_SR_C2IF_Pos             (17U)

+#define COMP_SR_C2IF_Msk             (0x1UL << COMP_SR_C2IF_Pos)               /*!< 0x00020000 */

+#define COMP_SR_C2IF                 COMP_SR_C2IF_Msk

+/*******************  Bit definition for COMP_ICFR register  ********************/

+#define COMP_ICFR_C1IF_Pos           (16U)

+#define COMP_ICFR_C1IF_Msk           (0x1UL << COMP_ICFR_C1IF_Pos)             /*!< 0x00010000 */

+#define COMP_ICFR_C1IF               COMP_ICFR_C1IF_Msk

+#define COMP_ICFR_C2IF_Pos           (17U)

+#define COMP_ICFR_C2IF_Msk           (0x1UL << COMP_ICFR_C2IF_Pos)             /*!< 0x00020000 */

+#define COMP_ICFR_C2IF               COMP_ICFR_C2IF_Msk

+/*******************  Bit definition for COMP_OR register  ********************/

+#define COMP_OR_AFOPA6_Pos           (0U)

+#define COMP_OR_AFOPA6_Msk           (0x1UL << COMP_OR_AFOPA6_Pos)             /*!< 0x00000001 */

+#define COMP_OR_AFOPA6               COMP_OR_AFOPA6_Msk

+#define COMP_OR_AFOPA8_Pos           (1U)

+#define COMP_OR_AFOPA8_Msk           (0x1UL << COMP_OR_AFOPA8_Pos)             /*!< 0x00000002 */

+#define COMP_OR_AFOPA8               COMP_OR_AFOPA8_Msk

+#define COMP_OR_AFOPB12_Pos          (2U)

+#define COMP_OR_AFOPB12_Msk          (0x1UL << COMP_OR_AFOPB12_Pos)            /*!< 0x00000004 */

+#define COMP_OR_AFOPB12              COMP_OR_AFOPB12_Msk

+#define COMP_OR_AFOPE6_Pos           (3U)

+#define COMP_OR_AFOPE6_Msk           (0x1UL << COMP_OR_AFOPE6_Pos)             /*!< 0x00000008 */

+#define COMP_OR_AFOPE6               COMP_OR_AFOPE6_Msk

+#define COMP_OR_AFOPE15_Pos          (4U)

+#define COMP_OR_AFOPE15_Msk          (0x1UL << COMP_OR_AFOPE15_Pos)            /*!< 0x00000010 */

+#define COMP_OR_AFOPE15              COMP_OR_AFOPE15_Msk

+#define COMP_OR_AFOPG2_Pos           (5U)

+#define COMP_OR_AFOPG2_Msk           (0x1UL << COMP_OR_AFOPG2_Pos)             /*!< 0x00000020 */

+#define COMP_OR_AFOPG2               COMP_OR_AFOPG2_Msk

+#define COMP_OR_AFOPG3_Pos           (6U)

+#define COMP_OR_AFOPG3_Msk           (0x1UL << COMP_OR_AFOPG3_Pos)             /*!< 0x00000040 */

+#define COMP_OR_AFOPG3               COMP_OR_AFOPG3_Msk

+#define COMP_OR_AFOPG4_Pos           (7U)

+#define COMP_OR_AFOPG4_Msk           (0x1UL << COMP_OR_AFOPG4_Pos)             /*!< 0x00000080 */

+#define COMP_OR_AFOPG4               COMP_OR_AFOPG4_Msk

+#define COMP_OR_AFOPI1_Pos           (8U)

+#define COMP_OR_AFOPI1_Msk           (0x1UL << COMP_OR_AFOPI1_Pos)             /*!< 0x00000100 */

+#define COMP_OR_AFOPI1               COMP_OR_AFOPI1_Msk

+#define COMP_OR_AFOPI4_Pos           (9U)

+#define COMP_OR_AFOPI4_Msk           (0x1UL << COMP_OR_AFOPI4_Pos)             /*!< 0x00000200 */

+#define COMP_OR_AFOPI4               COMP_OR_AFOPI4_Msk

+#define COMP_OR_AFOPK2_Pos           (10U)

+#define COMP_OR_AFOPK2_Msk           (0x1UL << COMP_OR_AFOPK2_Pos)             /*!< 0x00000400 */

+#define COMP_OR_AFOPK2               COMP_OR_AFOPK2_Msk

+

+/*!< ******************  Bit definition for COMP_CFGRx register  ********************/

+#define COMP_CFGRx_EN_Pos            (0U)

+#define COMP_CFGRx_EN_Msk            (0x1UL << COMP_CFGRx_EN_Pos)              /*!< 0x00000001 */

+#define COMP_CFGRx_EN                COMP_CFGRx_EN_Msk                         /*!< COMPx enable bit                     */

+#define COMP_CFGRx_BRGEN_Pos         (1U)

+#define COMP_CFGRx_BRGEN_Msk         (0x1UL << COMP_CFGRx_BRGEN_Pos)           /*!< 0x00000002 */

+#define COMP_CFGRx_BRGEN             COMP_CFGRx_BRGEN_Msk                      /*!< COMPx Scaler bridge enable           */

+#define COMP_CFGRx_SCALEN_Pos        (2U)

+#define COMP_CFGRx_SCALEN_Msk        (0x1UL << COMP_CFGRx_SCALEN_Pos)          /*!< 0x00000004 */

+#define COMP_CFGRx_SCALEN            COMP_CFGRx_SCALEN_Msk                     /*!< COMPx Voltage scaler enable bit      */

+#define COMP_CFGRx_POLARITY_Pos      (3U)

+#define COMP_CFGRx_POLARITY_Msk      (0x1UL << COMP_CFGRx_POLARITY_Pos)        /*!< 0x00000008 */

+#define COMP_CFGRx_POLARITY          COMP_CFGRx_POLARITY_Msk                   /*!< COMPx  polarity selection bit        */

+#define COMP_CFGRx_WINMODE_Pos       (4U)

+#define COMP_CFGRx_WINMODE_Msk       (0x1UL << COMP_CFGRx_WINMODE_Pos)         /*!< 0x00000010 */

+#define COMP_CFGRx_WINMODE           COMP_CFGRx_WINMODE_Msk                    /*!< COMPx Windows mode selection bit     */

+#define COMP_CFGRx_ITEN_Pos          (6U)

+#define COMP_CFGRx_ITEN_Msk          (0x1UL << COMP_CFGRx_ITEN_Pos)            /*!< 0x00000040 */

+#define COMP_CFGRx_ITEN              COMP_CFGRx_ITEN_Msk                       /*!< COMPx  interrupt enable              */

+#define COMP_CFGRx_HYST_Pos          (8U)

+#define COMP_CFGRx_HYST_Msk          (0x3UL << COMP_CFGRx_HYST_Pos)            /*!< 0x00000300 */

+#define COMP_CFGRx_HYST              COMP_CFGRx_HYST_Msk                       /*!< COMPx  hysteresis selection bits     */

+#define COMP_CFGRx_HYST_0            (0x1UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000100 */

+#define COMP_CFGRx_HYST_1            (0x2UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000200 */

+#define COMP_CFGRx_PWRMODE_Pos       (12U)

+#define COMP_CFGRx_PWRMODE_Msk       (0x3UL << COMP_CFGRx_PWRMODE_Pos)         /*!< 0x00003000 */

+#define COMP_CFGRx_PWRMODE           COMP_CFGRx_PWRMODE_Msk                    /*!< COMPx Power Mode of the comparator   */

+#define COMP_CFGRx_PWRMODE_0         (0x1UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00001000 */

+#define COMP_CFGRx_PWRMODE_1         (0x2UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00002000 */

+#define COMP_CFGRx_INMSEL_Pos        (16U)

+#define COMP_CFGRx_INMSEL_Msk        (0x7UL << COMP_CFGRx_INMSEL_Pos)          /*!< 0x00070000 */

+#define COMP_CFGRx_INMSEL            COMP_CFGRx_INMSEL_Msk                     /*!< COMPx  input minus selection bit  */

+#define COMP_CFGRx_INMSEL_0          (0x1UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00010000 */

+#define COMP_CFGRx_INMSEL_1          (0x2UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00020000 */

+#define COMP_CFGRx_INMSEL_2          (0x4UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00040000 */

+#define COMP_CFGRx_INPSEL_Pos        (20U)

+#define COMP_CFGRx_INPSEL_Msk        (0x1UL << COMP_CFGRx_INPSEL_Pos)          /*!< 0x00100000 */

+#define COMP_CFGRx_INPSEL            COMP_CFGRx_INPSEL_Msk                     /*!< COMPx  input plus selection bit       */

+#define COMP_CFGRx_BLANKING_Pos      (24U)

+#define COMP_CFGRx_BLANKING_Msk      (0xFUL << COMP_CFGRx_BLANKING_Pos)        /*!< 0x0F000000 */

+#define COMP_CFGRx_BLANKING          COMP_CFGRx_BLANKING_Msk                   /*!< COMPx  blanking source selection bits */

+#define COMP_CFGRx_BLANKING_0        (0x1UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x01000000 */

+#define COMP_CFGRx_BLANKING_1        (0x2UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x02000000 */

+#define COMP_CFGRx_BLANKING_2        (0x4UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x04000000 */

+#define COMP_CFGRx_LOCK_Pos          (31U)

+#define COMP_CFGRx_LOCK_Msk          (0x1UL << COMP_CFGRx_LOCK_Pos)            /*!< 0x80000000 */

+#define COMP_CFGRx_LOCK              COMP_CFGRx_LOCK_Msk                       /*!< COMPx Lock Bit                        */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for USART_CR1 register  *******************/

+#define USART_CR1_UE_Pos                (0U)

+#define USART_CR1_UE_Msk                (0x1UL << USART_CR1_UE_Pos)            /*!< 0x00000001 */

+#define USART_CR1_UE                    USART_CR1_UE_Msk                       /*!< USART Enable */

+#define USART_CR1_UESM_Pos              (1U)

+#define USART_CR1_UESM_Msk              (0x1UL << USART_CR1_UESM_Pos)          /*!< 0x00000002 */

+#define USART_CR1_UESM                  USART_CR1_UESM_Msk                     /*!< USART Enable in STOP Mode */

+#define USART_CR1_RE_Pos                (2U)

+#define USART_CR1_RE_Msk                (0x1UL << USART_CR1_RE_Pos)            /*!< 0x00000004 */

+#define USART_CR1_RE                    USART_CR1_RE_Msk                       /*!< Receiver Enable */

+#define USART_CR1_TE_Pos                (3U)

+#define USART_CR1_TE_Msk                (0x1UL << USART_CR1_TE_Pos)            /*!< 0x00000008 */

+#define USART_CR1_TE                    USART_CR1_TE_Msk                       /*!< Transmitter Enable */

+#define USART_CR1_IDLEIE_Pos            (4U)

+#define USART_CR1_IDLEIE_Msk            (0x1UL << USART_CR1_IDLEIE_Pos)        /*!< 0x00000010 */

+#define USART_CR1_IDLEIE                USART_CR1_IDLEIE_Msk                   /*!< IDLE Interrupt Enable */

+#define USART_CR1_RXNEIE_RXFNEIE_Pos    (5U)

+#define USART_CR1_RXNEIE_RXFNEIE_Msk    (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */

+#define USART_CR1_RXNEIE_RXFNEIE        USART_CR1_RXNEIE_RXFNEIE_Msk           /*!< RXNE and RX FIFO Not Empty Interrupt Enable */

+#define USART_CR1_TCIE_Pos              (6U)

+#define USART_CR1_TCIE_Msk              (0x1UL << USART_CR1_TCIE_Pos)          /*!< 0x00000040 */

+#define USART_CR1_TCIE                  USART_CR1_TCIE_Msk                     /*!< Transmission Complete Interrupt Enable */

+#define USART_CR1_TXEIE_TXFNFIE_Pos     (7U)

+#define USART_CR1_TXEIE_TXFNFIE_Msk     (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */

+#define USART_CR1_TXEIE_TXFNFIE         USART_CR1_TXEIE_TXFNFIE_Msk            /*!< TXE and TX FIFO Not Full Interrupt Enable */

+#define USART_CR1_PEIE_Pos              (8U)

+#define USART_CR1_PEIE_Msk              (0x1UL << USART_CR1_PEIE_Pos)          /*!< 0x00000100 */

+#define USART_CR1_PEIE                  USART_CR1_PEIE_Msk                     /*!< PE Interrupt Enable */

+#define USART_CR1_PS_Pos                (9U)

+#define USART_CR1_PS_Msk                (0x1UL << USART_CR1_PS_Pos)            /*!< 0x00000200 */

+#define USART_CR1_PS                    USART_CR1_PS_Msk                       /*!< Parity Selection */

+#define USART_CR1_PCE_Pos               (10U)

+#define USART_CR1_PCE_Msk               (0x1UL << USART_CR1_PCE_Pos)           /*!< 0x00000400 */

+#define USART_CR1_PCE                   USART_CR1_PCE_Msk                      /*!< Parity Control Enable */

+#define USART_CR1_WAKE_Pos              (11U)

+#define USART_CR1_WAKE_Msk              (0x1UL << USART_CR1_WAKE_Pos)          /*!< 0x00000800 */

+#define USART_CR1_WAKE                  USART_CR1_WAKE_Msk                     /*!< Receiver Wakeup method */

+#define USART_CR1_M_Pos                 (12U)

+#define USART_CR1_M_Msk                 (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */

+#define USART_CR1_M                     USART_CR1_M_Msk                        /*!< Word length */

+#define USART_CR1_M0_Pos                (12U)

+#define USART_CR1_M0_Msk                (0x1UL << USART_CR1_M0_Pos)            /*!< 0x00001000 */

+#define USART_CR1_M0                    USART_CR1_M0_Msk                       /*!< Word length - Bit 0 */

+#define USART_CR1_MME_Pos               (13U)

+#define USART_CR1_MME_Msk               (0x1UL << USART_CR1_MME_Pos)           /*!< 0x00002000 */

+#define USART_CR1_MME                   USART_CR1_MME_Msk                      /*!< Mute Mode Enable */

+#define USART_CR1_CMIE_Pos              (14U)

+#define USART_CR1_CMIE_Msk              (0x1UL << USART_CR1_CMIE_Pos)          /*!< 0x00004000 */

+#define USART_CR1_CMIE                  USART_CR1_CMIE_Msk                     /*!< Character match interrupt enable */

+#define USART_CR1_OVER8_Pos             (15U)

+#define USART_CR1_OVER8_Msk             (0x1UL << USART_CR1_OVER8_Pos)         /*!< 0x00008000 */

+#define USART_CR1_OVER8                 USART_CR1_OVER8_Msk                    /*!< Oversampling by 8-bit or 16-bit mode */

+#define USART_CR1_DEDT_Pos              (16U)

+#define USART_CR1_DEDT_Msk              (0x1FUL << USART_CR1_DEDT_Pos)         /*!< 0x001F0000 */

+#define USART_CR1_DEDT                  USART_CR1_DEDT_Msk                     /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */

+#define USART_CR1_DEDT_0                (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */

+#define USART_CR1_DEDT_1                (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */

+#define USART_CR1_DEDT_2                (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */

+#define USART_CR1_DEDT_3                (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */

+#define USART_CR1_DEDT_4                (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */

+#define USART_CR1_DEAT_Pos              (21U)

+#define USART_CR1_DEAT_Msk              (0x1FUL << USART_CR1_DEAT_Pos)         /*!< 0x03E00000 */

+#define USART_CR1_DEAT                  USART_CR1_DEAT_Msk                     /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */

+#define USART_CR1_DEAT_0                (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */

+#define USART_CR1_DEAT_1                (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */

+#define USART_CR1_DEAT_2                (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */

+#define USART_CR1_DEAT_3                (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */

+#define USART_CR1_DEAT_4                (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */

+#define USART_CR1_RTOIE_Pos             (26U)

+#define USART_CR1_RTOIE_Msk             (0x1UL << USART_CR1_RTOIE_Pos)         /*!< 0x04000000 */

+#define USART_CR1_RTOIE                 USART_CR1_RTOIE_Msk                    /*!< Receive Time Out interrupt enable */

+#define USART_CR1_EOBIE_Pos             (27U)

+#define USART_CR1_EOBIE_Msk             (0x1UL << USART_CR1_EOBIE_Pos)         /*!< 0x08000000 */

+#define USART_CR1_EOBIE                 USART_CR1_EOBIE_Msk                    /*!< End of Block interrupt enable */

+#define USART_CR1_M1_Pos                (28U)

+#define USART_CR1_M1_Msk                (0x1UL << USART_CR1_M1_Pos)            /*!< 0x10000000 */

+#define USART_CR1_M1                    USART_CR1_M1_Msk                       /*!< Word length - Bit 1 */

+#define USART_CR1_FIFOEN_Pos            (29U)

+#define USART_CR1_FIFOEN_Msk            (0x1UL << USART_CR1_FIFOEN_Pos)        /*!< 0x20000000 */

+#define USART_CR1_FIFOEN                USART_CR1_FIFOEN_Msk                   /*!< FIFO mode enable */

+#define USART_CR1_TXFEIE_Pos            (30U)

+#define USART_CR1_TXFEIE_Msk            (0x1UL << USART_CR1_TXFEIE_Pos)        /*!< 0x40000000 */

+#define USART_CR1_TXFEIE                USART_CR1_TXFEIE_Msk                   /*!< TXFIFO empty interrupt enable */

+#define USART_CR1_RXFFIE_Pos            (31U)

+#define USART_CR1_RXFFIE_Msk            (0x1UL << USART_CR1_RXFFIE_Pos)        /*!< 0x80000000 */

+#define USART_CR1_RXFFIE                USART_CR1_RXFFIE_Msk                   /*!< RXFIFO Full interrupt enable */

+

+/* Legacy define */

+#define  USART_CR1_RXNEIE  USART_CR1_RXNEIE_RXFNEIE

+#define  USART_CR1_TXEIE   USART_CR1_TXEIE_TXFNFIE

+

+/******************  Bit definition for USART_CR2 register  *******************/

+#define USART_CR2_SLVEN_Pos             (0U)

+#define USART_CR2_SLVEN_Msk             (0x1UL << USART_CR2_SLVEN_Pos)         /*!< 0x00000001 */

+#define USART_CR2_SLVEN                 USART_CR2_SLVEN_Msk                    /*!< Synchronous Slave mode Enable */

+#define USART_CR2_DIS_NSS_Pos           (3U)

+#define USART_CR2_DIS_NSS_Msk           (0x1UL << USART_CR2_DIS_NSS_Pos)       /*!< 0x00000008 */

+#define USART_CR2_DIS_NSS               USART_CR2_DIS_NSS_Msk                  /*!< Negative Slave Select (NSS) pin management */

+#define USART_CR2_ADDM7_Pos             (4U)

+#define USART_CR2_ADDM7_Msk             (0x1UL << USART_CR2_ADDM7_Pos)         /*!< 0x00000010 */

+#define USART_CR2_ADDM7                 USART_CR2_ADDM7_Msk                    /*!< 7-bit or 4-bit Address Detection */

+#define USART_CR2_LBDL_Pos              (5U)

+#define USART_CR2_LBDL_Msk              (0x1UL << USART_CR2_LBDL_Pos)          /*!< 0x00000020 */

+#define USART_CR2_LBDL                  USART_CR2_LBDL_Msk                     /*!< LIN Break Detection Length */

+#define USART_CR2_LBDIE_Pos             (6U)

+#define USART_CR2_LBDIE_Msk             (0x1UL << USART_CR2_LBDIE_Pos)         /*!< 0x00000040 */

+#define USART_CR2_LBDIE                 USART_CR2_LBDIE_Msk                    /*!< LIN Break Detection Interrupt Enable */

+#define USART_CR2_LBCL_Pos              (8U)

+#define USART_CR2_LBCL_Msk              (0x1UL << USART_CR2_LBCL_Pos)          /*!< 0x00000100 */

+#define USART_CR2_LBCL                  USART_CR2_LBCL_Msk                     /*!< Last Bit Clock pulse */

+#define USART_CR2_CPHA_Pos              (9U)

+#define USART_CR2_CPHA_Msk              (0x1UL << USART_CR2_CPHA_Pos)          /*!< 0x00000200 */

+#define USART_CR2_CPHA                  USART_CR2_CPHA_Msk                     /*!< Clock Phase */

+#define USART_CR2_CPOL_Pos              (10U)

+#define USART_CR2_CPOL_Msk              (0x1UL << USART_CR2_CPOL_Pos)          /*!< 0x00000400 */

+#define USART_CR2_CPOL                  USART_CR2_CPOL_Msk                     /*!< Clock Polarity */

+#define USART_CR2_CLKEN_Pos             (11U)

+#define USART_CR2_CLKEN_Msk             (0x1UL << USART_CR2_CLKEN_Pos)         /*!< 0x00000800 */

+#define USART_CR2_CLKEN                 USART_CR2_CLKEN_Msk                    /*!< Clock Enable */

+#define USART_CR2_STOP_Pos              (12U)

+#define USART_CR2_STOP_Msk              (0x3UL << USART_CR2_STOP_Pos)          /*!< 0x00003000 */

+#define USART_CR2_STOP                  USART_CR2_STOP_Msk                     /*!< STOP[1:0] bits (STOP bits) */

+#define USART_CR2_STOP_0                (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */

+#define USART_CR2_STOP_1                (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */

+#define USART_CR2_LINEN_Pos             (14U)

+#define USART_CR2_LINEN_Msk             (0x1UL << USART_CR2_LINEN_Pos)         /*!< 0x00004000 */

+#define USART_CR2_LINEN                 USART_CR2_LINEN_Msk                    /*!< LIN mode enable */

+#define USART_CR2_SWAP_Pos              (15U)

+#define USART_CR2_SWAP_Msk              (0x1UL << USART_CR2_SWAP_Pos)          /*!< 0x00008000 */

+#define USART_CR2_SWAP                  USART_CR2_SWAP_Msk                     /*!< SWAP TX/RX pins */

+#define USART_CR2_RXINV_Pos             (16U)

+#define USART_CR2_RXINV_Msk             (0x1UL << USART_CR2_RXINV_Pos)         /*!< 0x00010000 */

+#define USART_CR2_RXINV                 USART_CR2_RXINV_Msk                    /*!< RX pin active level inversion */

+#define USART_CR2_TXINV_Pos             (17U)

+#define USART_CR2_TXINV_Msk             (0x1UL << USART_CR2_TXINV_Pos)         /*!< 0x00020000 */

+#define USART_CR2_TXINV                 USART_CR2_TXINV_Msk                    /*!< TX pin active level inversion */

+#define USART_CR2_DATAINV_Pos           (18U)

+#define USART_CR2_DATAINV_Msk           (0x1UL << USART_CR2_DATAINV_Pos)       /*!< 0x00040000 */

+#define USART_CR2_DATAINV               USART_CR2_DATAINV_Msk                  /*!< Binary data inversion */

+#define USART_CR2_MSBFIRST_Pos          (19U)

+#define USART_CR2_MSBFIRST_Msk          (0x1UL << USART_CR2_MSBFIRST_Pos)      /*!< 0x00080000 */

+#define USART_CR2_MSBFIRST              USART_CR2_MSBFIRST_Msk                 /*!< Most Significant Bit First */

+#define USART_CR2_ABREN_Pos             (20U)

+#define USART_CR2_ABREN_Msk             (0x1UL << USART_CR2_ABREN_Pos)         /*!< 0x00100000 */

+#define USART_CR2_ABREN                 USART_CR2_ABREN_Msk                    /*!< Auto Baud-Rate Enable*/

+#define USART_CR2_ABRMODE_Pos           (21U)

+#define USART_CR2_ABRMODE_Msk           (0x3UL << USART_CR2_ABRMODE_Pos)       /*!< 0x00600000 */

+#define USART_CR2_ABRMODE               USART_CR2_ABRMODE_Msk                  /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */

+#define USART_CR2_ABRMODE_0             (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */

+#define USART_CR2_ABRMODE_1             (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */

+#define USART_CR2_RTOEN_Pos             (23U)

+#define USART_CR2_RTOEN_Msk             (0x1UL << USART_CR2_RTOEN_Pos)         /*!< 0x00800000 */

+#define USART_CR2_RTOEN                 USART_CR2_RTOEN_Msk                    /*!< Receiver Time-Out enable */

+#define USART_CR2_ADD_Pos               (24U)

+#define USART_CR2_ADD_Msk               (0xFFUL << USART_CR2_ADD_Pos)          /*!< 0xFF000000 */

+#define USART_CR2_ADD                   USART_CR2_ADD_Msk                      /*!< Address of the USART node */

+

+/******************  Bit definition for USART_CR3 register  *******************/

+#define USART_CR3_EIE_Pos               (0U)

+#define USART_CR3_EIE_Msk               (0x1UL << USART_CR3_EIE_Pos)           /*!< 0x00000001 */

+#define USART_CR3_EIE                   USART_CR3_EIE_Msk                      /*!< Error Interrupt Enable */

+#define USART_CR3_IREN_Pos              (1U)

+#define USART_CR3_IREN_Msk              (0x1UL << USART_CR3_IREN_Pos)          /*!< 0x00000002 */

+#define USART_CR3_IREN                  USART_CR3_IREN_Msk                     /*!< IrDA mode Enable */

+#define USART_CR3_IRLP_Pos              (2U)

+#define USART_CR3_IRLP_Msk              (0x1UL << USART_CR3_IRLP_Pos)          /*!< 0x00000004 */

+#define USART_CR3_IRLP                  USART_CR3_IRLP_Msk                     /*!< IrDA Low-Power */

+#define USART_CR3_HDSEL_Pos             (3U)

+#define USART_CR3_HDSEL_Msk             (0x1UL << USART_CR3_HDSEL_Pos)         /*!< 0x00000008 */

+#define USART_CR3_HDSEL                 USART_CR3_HDSEL_Msk                    /*!< Half-Duplex Selection */

+#define USART_CR3_NACK_Pos              (4U)

+#define USART_CR3_NACK_Msk              (0x1UL << USART_CR3_NACK_Pos)          /*!< 0x00000010 */

+#define USART_CR3_NACK                  USART_CR3_NACK_Msk                     /*!< SmartCard NACK enable */

+#define USART_CR3_SCEN_Pos              (5U)

+#define USART_CR3_SCEN_Msk              (0x1UL << USART_CR3_SCEN_Pos)          /*!< 0x00000020 */

+#define USART_CR3_SCEN                  USART_CR3_SCEN_Msk                     /*!< SmartCard mode enable */

+#define USART_CR3_DMAR_Pos              (6U)

+#define USART_CR3_DMAR_Msk              (0x1UL << USART_CR3_DMAR_Pos)          /*!< 0x00000040 */

+#define USART_CR3_DMAR                  USART_CR3_DMAR_Msk                     /*!< DMA Enable Receiver */

+#define USART_CR3_DMAT_Pos              (7U)

+#define USART_CR3_DMAT_Msk              (0x1UL << USART_CR3_DMAT_Pos)          /*!< 0x00000080 */

+#define USART_CR3_DMAT                  USART_CR3_DMAT_Msk                     /*!< DMA Enable Transmitter */

+#define USART_CR3_RTSE_Pos              (8U)

+#define USART_CR3_RTSE_Msk              (0x1UL << USART_CR3_RTSE_Pos)          /*!< 0x00000100 */

+#define USART_CR3_RTSE                  USART_CR3_RTSE_Msk                     /*!< RTS Enable */

+#define USART_CR3_CTSE_Pos              (9U)

+#define USART_CR3_CTSE_Msk              (0x1UL << USART_CR3_CTSE_Pos)          /*!< 0x00000200 */

+#define USART_CR3_CTSE                  USART_CR3_CTSE_Msk                     /*!< CTS Enable */

+#define USART_CR3_CTSIE_Pos             (10U)

+#define USART_CR3_CTSIE_Msk             (0x1UL << USART_CR3_CTSIE_Pos)         /*!< 0x00000400 */

+#define USART_CR3_CTSIE                 USART_CR3_CTSIE_Msk                    /*!< CTS Interrupt Enable */

+#define USART_CR3_ONEBIT_Pos            (11U)

+#define USART_CR3_ONEBIT_Msk            (0x1UL << USART_CR3_ONEBIT_Pos)        /*!< 0x00000800 */

+#define USART_CR3_ONEBIT                USART_CR3_ONEBIT_Msk                   /*!< One sample bit method enable */

+#define USART_CR3_OVRDIS_Pos            (12U)

+#define USART_CR3_OVRDIS_Msk            (0x1UL << USART_CR3_OVRDIS_Pos)        /*!< 0x00001000 */

+#define USART_CR3_OVRDIS                USART_CR3_OVRDIS_Msk                   /*!< Overrun Disable */

+#define USART_CR3_DDRE_Pos              (13U)

+#define USART_CR3_DDRE_Msk              (0x1UL << USART_CR3_DDRE_Pos)          /*!< 0x00002000 */

+#define USART_CR3_DDRE                  USART_CR3_DDRE_Msk                     /*!< DMA Disable on Reception Error */

+#define USART_CR3_DEM_Pos               (14U)

+#define USART_CR3_DEM_Msk               (0x1UL << USART_CR3_DEM_Pos)           /*!< 0x00004000 */

+#define USART_CR3_DEM                   USART_CR3_DEM_Msk                      /*!< Driver Enable Mode */

+#define USART_CR3_DEP_Pos               (15U)

+#define USART_CR3_DEP_Msk               (0x1UL << USART_CR3_DEP_Pos)           /*!< 0x00008000 */

+#define USART_CR3_DEP                   USART_CR3_DEP_Msk                      /*!< Driver Enable Polarity Selection */

+#define USART_CR3_SCARCNT_Pos           (17U)

+#define USART_CR3_SCARCNT_Msk           (0x7UL << USART_CR3_SCARCNT_Pos)       /*!< 0x000E0000 */

+#define USART_CR3_SCARCNT               USART_CR3_SCARCNT_Msk                  /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */

+#define USART_CR3_SCARCNT_0             (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */

+#define USART_CR3_SCARCNT_1             (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */

+#define USART_CR3_SCARCNT_2             (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */

+#define USART_CR3_WUS_Pos               (20U)

+#define USART_CR3_WUS_Msk               (0x3UL << USART_CR3_WUS_Pos)           /*!< 0x00300000 */

+#define USART_CR3_WUS                   USART_CR3_WUS_Msk                      /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */

+#define USART_CR3_WUS_0                 (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */

+#define USART_CR3_WUS_1                 (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */

+#define USART_CR3_WUFIE_Pos             (22U)

+#define USART_CR3_WUFIE_Msk             (0x1UL << USART_CR3_WUFIE_Pos)         /*!< 0x00400000 */

+#define USART_CR3_WUFIE                 USART_CR3_WUFIE_Msk                    /*!< Wake Up Interrupt Enable */

+#define USART_CR3_TXFTIE_Pos            (23U)

+#define USART_CR3_TXFTIE_Msk            (0x1UL << USART_CR3_TXFTIE_Pos)        /*!< 0x00800000 */

+#define USART_CR3_TXFTIE                USART_CR3_TXFTIE_Msk                   /*!< TXFIFO threshold interrupt enable */

+#define USART_CR3_TCBGTIE_Pos           (24U)

+#define USART_CR3_TCBGTIE_Msk           (0x1UL << USART_CR3_TCBGTIE_Pos)       /*!< 0x01000000 */

+#define USART_CR3_TCBGTIE               USART_CR3_TCBGTIE_Msk                  /*!< Transmission Complete before guard time, interrupt enable */

+#define USART_CR3_RXFTCFG_Pos           (25U)

+#define USART_CR3_RXFTCFG_Msk           (0x7UL << USART_CR3_RXFTCFG_Pos)       /*!< 0x0E000000 */

+#define USART_CR3_RXFTCFG               USART_CR3_RXFTCFG_Msk                  /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */

+#define USART_CR3_RXFTCFG_0             (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */

+#define USART_CR3_RXFTCFG_1             (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */

+#define USART_CR3_RXFTCFG_2             (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */

+#define USART_CR3_RXFTIE_Pos            (28U)

+#define USART_CR3_RXFTIE_Msk            (0x1UL << USART_CR3_RXFTIE_Pos)        /*!< 0x10000000 */

+#define USART_CR3_RXFTIE                USART_CR3_RXFTIE_Msk                   /*!< RXFIFO threshold interrupt enable */

+#define USART_CR3_TXFTCFG_Pos           (29U)

+#define USART_CR3_TXFTCFG_Msk           (0x7UL << USART_CR3_TXFTCFG_Pos)       /*!< 0xE0000000 */

+#define USART_CR3_TXFTCFG               USART_CR3_TXFTCFG_Msk                  /*!< TXFIFO [2:0] threshold configuration */

+#define USART_CR3_TXFTCFG_0             (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */

+#define USART_CR3_TXFTCFG_1             (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */

+#define USART_CR3_TXFTCFG_2             (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */

+

+/******************  Bit definition for USART_BRR register  *******************/

+#define USART_BRR_DIV_FRACTION_Pos      (0U)

+#define USART_BRR_DIV_FRACTION_Msk      (0xFUL << USART_BRR_DIV_FRACTION_Pos)  /*!< 0x0000000F */

+#define USART_BRR_DIV_FRACTION          USART_BRR_DIV_FRACTION_Msk             /*!< Fraction of USARTDIV */

+#define USART_BRR_DIV_MANTISSA_Pos      (4U)

+#define USART_BRR_DIV_MANTISSA_Msk      (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */

+#define USART_BRR_DIV_MANTISSA          USART_BRR_DIV_MANTISSA_Msk             /*!< Mantissa of USARTDIV */

+

+/******************  Bit definition for USART_GTPR register  ******************/

+#define USART_GTPR_PSC_Pos              (0U)

+#define USART_GTPR_PSC_Msk              (0xFFUL << USART_GTPR_PSC_Pos)         /*!< 0x000000FF */

+#define USART_GTPR_PSC                  USART_GTPR_PSC_Msk                     /*!< PSC[7:0] bits (Prescaler value) */

+#define USART_GTPR_GT_Pos               (8U)

+#define USART_GTPR_GT_Msk               (0xFFUL << USART_GTPR_GT_Pos)          /*!< 0x0000FF00 */

+#define USART_GTPR_GT                   USART_GTPR_GT_Msk                      /*!< GT[7:0] bits (Guard time value) */

+

+/*******************  Bit definition for USART_RTOR register  *****************/

+#define USART_RTOR_RTO_Pos              (0U)

+#define USART_RTOR_RTO_Msk              (0xFFFFFFUL << USART_RTOR_RTO_Pos)     /*!< 0x00FFFFFF */

+#define USART_RTOR_RTO                  USART_RTOR_RTO_Msk                     /*!< Receiver Time Out Value */

+#define USART_RTOR_BLEN_Pos             (24U)

+#define USART_RTOR_BLEN_Msk             (0xFFUL << USART_RTOR_BLEN_Pos)        /*!< 0xFF000000 */

+#define USART_RTOR_BLEN                 USART_RTOR_BLEN_Msk                    /*!< Block Length */

+

+/*******************  Bit definition for USART_RQR register  ******************/

+#define USART_RQR_ABRRQ_Pos             (0U)

+#define USART_RQR_ABRRQ_Msk             (0x1UL << USART_RQR_ABRRQ_Pos)         /*!< 0x00000001 */

+#define USART_RQR_ABRRQ                 USART_RQR_ABRRQ_Msk                    /*!< Auto-Baud Rate Request */

+#define USART_RQR_SBKRQ_Pos             (1U)

+#define USART_RQR_SBKRQ_Msk             (0x1UL << USART_RQR_SBKRQ_Pos)         /*!< 0x00000002 */

+#define USART_RQR_SBKRQ                 USART_RQR_SBKRQ_Msk                    /*!< Send Break Request */

+#define USART_RQR_MMRQ_Pos              (2U)

+#define USART_RQR_MMRQ_Msk              (0x1UL << USART_RQR_MMRQ_Pos)          /*!< 0x00000004 */

+#define USART_RQR_MMRQ                  USART_RQR_MMRQ_Msk                     /*!< Mute Mode Request */

+#define USART_RQR_RXFRQ_Pos             (3U)

+#define USART_RQR_RXFRQ_Msk             (0x1UL << USART_RQR_RXFRQ_Pos)         /*!< 0x00000008 */

+#define USART_RQR_RXFRQ                 USART_RQR_RXFRQ_Msk                    /*!< Receive Data flush Request */

+#define USART_RQR_TXFRQ_Pos             (4U)

+#define USART_RQR_TXFRQ_Msk             (0x1UL << USART_RQR_TXFRQ_Pos)         /*!< 0x00000010 */

+#define USART_RQR_TXFRQ                 USART_RQR_TXFRQ_Msk                    /*!< Transmit data flush Request */

+

+/*******************  Bit definition for USART_ISR register  ******************/

+#define USART_ISR_PE_Pos                (0U)

+#define USART_ISR_PE_Msk                (0x1UL << USART_ISR_PE_Pos)            /*!< 0x00000001 */

+#define USART_ISR_PE                    USART_ISR_PE_Msk                       /*!< Parity Error */

+#define USART_ISR_FE_Pos                (1U)

+#define USART_ISR_FE_Msk                (0x1UL << USART_ISR_FE_Pos)            /*!< 0x00000002 */

+#define USART_ISR_FE                    USART_ISR_FE_Msk                       /*!< Framing Error */

+#define USART_ISR_NE_Pos                (2U)

+#define USART_ISR_NE_Msk                (0x1UL << USART_ISR_NE_Pos)            /*!< 0x00000004 */

+#define USART_ISR_NE                    USART_ISR_NE_Msk                       /*!< Noise detected Flag */

+#define USART_ISR_ORE_Pos               (3U)

+#define USART_ISR_ORE_Msk               (0x1UL << USART_ISR_ORE_Pos)           /*!< 0x00000008 */

+#define USART_ISR_ORE                   USART_ISR_ORE_Msk                      /*!< OverRun Error */

+#define USART_ISR_IDLE_Pos              (4U)

+#define USART_ISR_IDLE_Msk              (0x1UL << USART_ISR_IDLE_Pos)          /*!< 0x00000010 */

+#define USART_ISR_IDLE                  USART_ISR_IDLE_Msk                     /*!< IDLE line detected */

+#define USART_ISR_RXNE_RXFNE_Pos        (5U)

+#define USART_ISR_RXNE_RXFNE_Msk        (0x1UL << USART_ISR_RXNE_RXFNE_Pos)    /*!< 0x00000020 */

+#define USART_ISR_RXNE_RXFNE            USART_ISR_RXNE_RXFNE_Msk               /*!< Read Data Register or RX FIFO Not Empty */

+#define USART_ISR_TC_Pos                (6U)

+#define USART_ISR_TC_Msk                (0x1UL << USART_ISR_TC_Pos)            /*!< 0x00000040 */

+#define USART_ISR_TC                    USART_ISR_TC_Msk                       /*!< Transmission Complete */

+#define USART_ISR_TXE_TXFNF_Pos         (7U)

+#define USART_ISR_TXE_TXFNF_Msk         (0x1UL << USART_ISR_TXE_TXFNF_Pos)     /*!< 0x00000080 */

+#define USART_ISR_TXE_TXFNF             USART_ISR_TXE_TXFNF_Msk                /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */

+#define USART_ISR_LBDF_Pos              (8U)

+#define USART_ISR_LBDF_Msk              (0x1UL << USART_ISR_LBDF_Pos)          /*!< 0x00000100 */

+#define USART_ISR_LBDF                  USART_ISR_LBDF_Msk                     /*!< LIN Break Detection Flag */

+#define USART_ISR_CTSIF_Pos             (9U)

+#define USART_ISR_CTSIF_Msk             (0x1UL << USART_ISR_CTSIF_Pos)         /*!< 0x00000200 */

+#define USART_ISR_CTSIF                 USART_ISR_CTSIF_Msk                    /*!< CTS interrupt flag */

+#define USART_ISR_CTS_Pos               (10U)

+#define USART_ISR_CTS_Msk               (0x1UL << USART_ISR_CTS_Pos)           /*!< 0x00000400 */

+#define USART_ISR_CTS                   USART_ISR_CTS_Msk                      /*!< CTS flag */

+#define USART_ISR_RTOF_Pos              (11U)

+#define USART_ISR_RTOF_Msk              (0x1UL << USART_ISR_RTOF_Pos)          /*!< 0x00000800 */

+#define USART_ISR_RTOF                  USART_ISR_RTOF_Msk                     /*!< Receiver Time Out */

+#define USART_ISR_EOBF_Pos              (12U)

+#define USART_ISR_EOBF_Msk              (0x1UL << USART_ISR_EOBF_Pos)          /*!< 0x00001000 */

+#define USART_ISR_EOBF                  USART_ISR_EOBF_Msk                     /*!< End Of Block Flag */

+#define USART_ISR_UDR_Pos               (13U)

+#define USART_ISR_UDR_Msk               (0x1UL << USART_ISR_UDR_Pos)           /*!< 0x00002000 */

+#define USART_ISR_UDR                   USART_ISR_UDR_Msk                      /*!< SPI slave underrun error flag */

+#define USART_ISR_ABRE_Pos              (14U)

+#define USART_ISR_ABRE_Msk              (0x1UL << USART_ISR_ABRE_Pos)          /*!< 0x00004000 */

+#define USART_ISR_ABRE                  USART_ISR_ABRE_Msk                     /*!< Auto-Baud Rate Error */

+#define USART_ISR_ABRF_Pos              (15U)

+#define USART_ISR_ABRF_Msk              (0x1UL << USART_ISR_ABRF_Pos)          /*!< 0x00008000 */

+#define USART_ISR_ABRF                  USART_ISR_ABRF_Msk                     /*!< Auto-Baud Rate Flag */

+#define USART_ISR_BUSY_Pos              (16U)

+#define USART_ISR_BUSY_Msk              (0x1UL << USART_ISR_BUSY_Pos)          /*!< 0x00010000 */

+#define USART_ISR_BUSY                  USART_ISR_BUSY_Msk                     /*!< Busy Flag */

+#define USART_ISR_CMF_Pos               (17U)

+#define USART_ISR_CMF_Msk               (0x1UL << USART_ISR_CMF_Pos)           /*!< 0x00020000 */

+#define USART_ISR_CMF                   USART_ISR_CMF_Msk                      /*!< Character Match Flag */

+#define USART_ISR_SBKF_Pos              (18U)

+#define USART_ISR_SBKF_Msk              (0x1UL << USART_ISR_SBKF_Pos)          /*!< 0x00040000 */

+#define USART_ISR_SBKF                  USART_ISR_SBKF_Msk                     /*!< Send Break Flag */

+#define USART_ISR_RWU_Pos               (19U)

+#define USART_ISR_RWU_Msk               (0x1UL << USART_ISR_RWU_Pos)           /*!< 0x00080000 */

+#define USART_ISR_RWU                   USART_ISR_RWU_Msk                      /*!< Receive Wake Up from mute mode Flag */

+#define USART_ISR_WUF_Pos               (20U)

+#define USART_ISR_WUF_Msk               (0x1UL << USART_ISR_WUF_Pos)           /*!< 0x00100000 */

+#define USART_ISR_WUF                   USART_ISR_WUF_Msk                      /*!< Wake Up from stop mode Flag */

+#define USART_ISR_TEACK_Pos             (21U)

+#define USART_ISR_TEACK_Msk             (0x1UL << USART_ISR_TEACK_Pos)         /*!< 0x00200000 */

+#define USART_ISR_TEACK                 USART_ISR_TEACK_Msk                    /*!< Transmit Enable Acknowledge Flag */

+#define USART_ISR_REACK_Pos             (22U)

+#define USART_ISR_REACK_Msk             (0x1UL << USART_ISR_REACK_Pos)         /*!< 0x00400000 */

+#define USART_ISR_REACK                 USART_ISR_REACK_Msk                    /*!< Receive Enable Acknowledge Flag */

+#define USART_ISR_TXFE_Pos              (23U)

+#define USART_ISR_TXFE_Msk              (0x1UL << USART_ISR_TXFE_Pos)          /*!< 0x00800000 */

+#define USART_ISR_TXFE                  USART_ISR_TXFE_Msk                     /*!< TXFIFO Empty */

+#define USART_ISR_RXFF_Pos              (24U)

+#define USART_ISR_RXFF_Msk              (0x1UL << USART_ISR_RXFF_Pos)          /*!< 0x01000000 */

+#define USART_ISR_RXFF                  USART_ISR_RXFF_Msk                     /*!< RXFIFO Full Flag */

+#define USART_ISR_TCBGT_Pos             (25U)

+#define USART_ISR_TCBGT_Msk             (0x1UL << USART_ISR_TCBGT_Pos)         /*!< 0x02000000 */

+#define USART_ISR_TCBGT                 USART_ISR_TCBGT_Msk                    /*!< Transmission complete before guard time Flag */

+#define USART_ISR_RXFT_Pos              (26U)

+#define USART_ISR_RXFT_Msk              (0x1UL << USART_ISR_RXFT_Pos)          /*!< 0x04000000 */

+#define USART_ISR_RXFT                  USART_ISR_RXFT_Msk                     /*!< RXFIFO threshold Flag */

+#define USART_ISR_TXFT_Pos              (27U)

+#define USART_ISR_TXFT_Msk              (0x1UL << USART_ISR_TXFT_Pos)          /*!< 0x08000000 */

+#define USART_ISR_TXFT                  USART_ISR_TXFT_Msk                     /*!< TXFIFO threshold Flag */

+

+/*******************  Bit definition for USART_ICR register  ******************/

+#define USART_ICR_PECF_Pos              (0U)

+#define USART_ICR_PECF_Msk              (0x1UL << USART_ICR_PECF_Pos)          /*!< 0x00000001 */

+#define USART_ICR_PECF                  USART_ICR_PECF_Msk                     /*!< Parity Error Clear Flag */

+#define USART_ICR_FECF_Pos              (1U)

+#define USART_ICR_FECF_Msk              (0x1UL << USART_ICR_FECF_Pos)          /*!< 0x00000002 */

+#define USART_ICR_FECF                  USART_ICR_FECF_Msk                     /*!< Framing Error Clear Flag */

+#define USART_ICR_NECF_Pos              (2U)

+#define USART_ICR_NECF_Msk              (0x1UL << USART_ICR_NECF_Pos)          /*!< 0x00000004 */

+#define USART_ICR_NECF                  USART_ICR_NECF_Msk                     /*!< Noise detected Clear Flag */

+#define USART_ICR_ORECF_Pos             (3U)

+#define USART_ICR_ORECF_Msk             (0x1UL << USART_ICR_ORECF_Pos)         /*!< 0x00000008 */

+#define USART_ICR_ORECF                 USART_ICR_ORECF_Msk                    /*!< OverRun Error Clear Flag */

+#define USART_ICR_IDLECF_Pos            (4U)

+#define USART_ICR_IDLECF_Msk            (0x1UL << USART_ICR_IDLECF_Pos)        /*!< 0x00000010 */

+#define USART_ICR_IDLECF                USART_ICR_IDLECF_Msk                   /*!< IDLE line detected Clear Flag */

+#define USART_ICR_TXFECF_Pos            (5U)

+#define USART_ICR_TXFECF_Msk            (0x1UL << USART_ICR_TXFECF_Pos)        /*!< 0x00000020 */

+#define USART_ICR_TXFECF                USART_ICR_TXFECF_Msk                   /*!< TXFIFO empty clear flag */

+#define USART_ICR_TCCF_Pos              (6U)

+#define USART_ICR_TCCF_Msk              (0x1UL << USART_ICR_TCCF_Pos)          /*!< 0x00000040 */

+#define USART_ICR_TCCF                  USART_ICR_TCCF_Msk                     /*!< Transmission Complete Clear Flag */

+#define USART_ICR_TCBGTCF_Pos           (7U)

+#define USART_ICR_TCBGTCF_Msk           (0x1UL << USART_ICR_TCBGTCF_Pos)       /*!< 0x00000080 */

+#define USART_ICR_TCBGTCF               USART_ICR_TCBGTCF_Msk                  /*!< Transmission complete before guard time Clear Flag */

+#define USART_ICR_LBDCF_Pos             (8U)

+#define USART_ICR_LBDCF_Msk             (0x1UL << USART_ICR_LBDCF_Pos)         /*!< 0x00000100 */

+#define USART_ICR_LBDCF                 USART_ICR_LBDCF_Msk                    /*!< LIN Break Detection Clear Flag */

+#define USART_ICR_CTSCF_Pos             (9U)

+#define USART_ICR_CTSCF_Msk             (0x1UL << USART_ICR_CTSCF_Pos)         /*!< 0x00000200 */

+#define USART_ICR_CTSCF                 USART_ICR_CTSCF_Msk                    /*!< CTS Interrupt Clear Flag */

+#define USART_ICR_RTOCF_Pos             (11U)

+#define USART_ICR_RTOCF_Msk             (0x1UL << USART_ICR_RTOCF_Pos)         /*!< 0x00000800 */

+#define USART_ICR_RTOCF                 USART_ICR_RTOCF_Msk                    /*!< Receiver Time Out Clear Flag */

+#define USART_ICR_EOBCF_Pos             (12U)

+#define USART_ICR_EOBCF_Msk             (0x1UL << USART_ICR_EOBCF_Pos)         /*!< 0x00001000 */

+#define USART_ICR_EOBCF                 USART_ICR_EOBCF_Msk                    /*!< End Of Block Clear Flag */

+#define USART_ICR_UDRCF_Pos             (13U)

+#define USART_ICR_UDRCF_Msk             (0x1UL << USART_ICR_UDRCF_Pos)         /*!< 0x00002000 */

+#define USART_ICR_UDRCF                 USART_ICR_UDRCF_Msk                    /*!< SPI slave underrun clear flag */

+#define USART_ICR_CMCF_Pos              (17U)

+#define USART_ICR_CMCF_Msk              (0x1UL << USART_ICR_CMCF_Pos)          /*!< 0x00020000 */

+#define USART_ICR_CMCF                  USART_ICR_CMCF_Msk                     /*!< Character Match Clear Flag */

+#define USART_ICR_WUCF_Pos              (20U)

+#define USART_ICR_WUCF_Msk              (0x1UL << USART_ICR_WUCF_Pos)          /*!< 0x00100000 */

+#define USART_ICR_WUCF                  USART_ICR_WUCF_Msk                     /*!< Wake Up from stop mode Clear Flag */

+

+/*******************  Bit definition for USART_RDR register  ******************/

+#define USART_RDR_RDR_Pos               (0U)

+#define USART_RDR_RDR_Msk               (0x1FFUL << USART_RDR_RDR_Pos)         /*!< 0x000001FF */

+#define USART_RDR_RDR                   USART_RDR_RDR_Msk                      /*!< RDR[8:0] bits (Receive Data value) */

+

+/*******************  Bit definition for USART_TDR register  ******************/

+#define USART_TDR_TDR_Pos               (0U)

+#define USART_TDR_TDR_Msk               (0x1FFUL << USART_TDR_TDR_Pos)         /*!< 0x000001FF */

+#define USART_TDR_TDR                   USART_TDR_TDR_Msk                      /*!< TDR[8:0] bits (Transmit Data value) */

+

+/*******************  Bit definition for USART_PRESC register  ******************/

+#define USART_PRESC_PRESCALER_Pos       (0U)

+#define USART_PRESC_PRESCALER_Msk       (0xFUL << USART_PRESC_PRESCALER_Pos)   /*!< 0x0000000F */

+#define USART_PRESC_PRESCALER           USART_PRESC_PRESCALER_Msk              /*!< PRESCALER[3:0] bits (Clock prescaler) */

+#define USART_PRESC_PRESCALER_0         (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */

+#define USART_PRESC_PRESCALER_1         (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */

+#define USART_PRESC_PRESCALER_2         (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */

+#define USART_PRESC_PRESCALER_3         (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */

+

+/******************************************************************************/

+/*                                                                            */

+/*           Single Wire Protocol Master Interface (SWPMI)                    */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for SWPMI_CR register   ********************/

+#define SWPMI_CR_RXDMA_Pos       (0U)

+#define SWPMI_CR_RXDMA_Msk       (0x1UL << SWPMI_CR_RXDMA_Pos)                 /*!< 0x00000001 */

+#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */

+#define SWPMI_CR_TXDMA_Pos       (1U)

+#define SWPMI_CR_TXDMA_Msk       (0x1UL << SWPMI_CR_TXDMA_Pos)                 /*!< 0x00000002 */

+#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */

+#define SWPMI_CR_RXMODE_Pos      (2U)

+#define SWPMI_CR_RXMODE_Msk      (0x1UL << SWPMI_CR_RXMODE_Pos)                /*!< 0x00000004 */

+#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */

+#define SWPMI_CR_TXMODE_Pos      (3U)

+#define SWPMI_CR_TXMODE_Msk      (0x1UL << SWPMI_CR_TXMODE_Pos)                /*!< 0x00000008 */

+#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */

+#define SWPMI_CR_LPBK_Pos        (4U)

+#define SWPMI_CR_LPBK_Msk        (0x1UL << SWPMI_CR_LPBK_Pos)                  /*!< 0x00000010 */

+#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */

+#define SWPMI_CR_SWPACT_Pos      (5U)

+#define SWPMI_CR_SWPACT_Msk      (0x1UL << SWPMI_CR_SWPACT_Pos)                /*!< 0x00000020 */

+#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */

+#define SWPMI_CR_DEACT_Pos       (10U)

+#define SWPMI_CR_DEACT_Msk       (0x1UL << SWPMI_CR_DEACT_Pos)                 /*!< 0x00000400 */

+#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */

+#define SWPMI_CR_SWPEN_Pos       (11U)

+#define SWPMI_CR_SWPEN_Msk       (0x1UL << SWPMI_CR_SWPEN_Pos)                 /*!< 0x00000800 */

+#define SWPMI_CR_SWPEN           SWPMI_CR_SWPEN_Msk                            /*!<Single wire protocol master transceiver enable       */

+

+/*******************  Bit definition for SWPMI_BRR register  ********************/

+#define SWPMI_BRR_BR_Pos         (0U)

+#define SWPMI_BRR_BR_Msk         (0xFFUL << SWPMI_BRR_BR_Pos)                  /*!< 0x000000FF */

+#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[7:0] bits (Bitrate prescaler) */

+

+/*******************  Bit definition for SWPMI_ISR register  ********************/

+#define SWPMI_ISR_RXBFF_Pos      (0U)

+#define SWPMI_ISR_RXBFF_Msk      (0x1UL << SWPMI_ISR_RXBFF_Pos)                /*!< 0x00000001 */

+#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */

+#define SWPMI_ISR_TXBEF_Pos      (1U)

+#define SWPMI_ISR_TXBEF_Msk      (0x1UL << SWPMI_ISR_TXBEF_Pos)                /*!< 0x00000002 */

+#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */

+#define SWPMI_ISR_RXBERF_Pos     (2U)

+#define SWPMI_ISR_RXBERF_Msk     (0x1UL << SWPMI_ISR_RXBERF_Pos)               /*!< 0x00000004 */

+#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */

+#define SWPMI_ISR_RXOVRF_Pos     (3U)

+#define SWPMI_ISR_RXOVRF_Msk     (0x1UL << SWPMI_ISR_RXOVRF_Pos)               /*!< 0x00000008 */

+#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */

+#define SWPMI_ISR_TXUNRF_Pos     (4U)

+#define SWPMI_ISR_TXUNRF_Msk     (0x1UL << SWPMI_ISR_TXUNRF_Pos)               /*!< 0x00000010 */

+#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */

+#define SWPMI_ISR_RXNE_Pos       (5U)

+#define SWPMI_ISR_RXNE_Msk       (0x1UL << SWPMI_ISR_RXNE_Pos)                 /*!< 0x00000020 */

+#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */

+#define SWPMI_ISR_TXE_Pos        (6U)

+#define SWPMI_ISR_TXE_Msk        (0x1UL << SWPMI_ISR_TXE_Pos)                  /*!< 0x00000040 */

+#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */

+#define SWPMI_ISR_TCF_Pos        (7U)

+#define SWPMI_ISR_TCF_Msk        (0x1UL << SWPMI_ISR_TCF_Pos)                  /*!< 0x00000080 */

+#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */

+#define SWPMI_ISR_SRF_Pos        (8U)

+#define SWPMI_ISR_SRF_Msk        (0x1UL << SWPMI_ISR_SRF_Pos)                  /*!< 0x00000100 */

+#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */

+#define SWPMI_ISR_SUSP_Pos       (9U)

+#define SWPMI_ISR_SUSP_Msk       (0x1UL << SWPMI_ISR_SUSP_Pos)                 /*!< 0x00000200 */

+#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */

+#define SWPMI_ISR_DEACTF_Pos     (10U)

+#define SWPMI_ISR_DEACTF_Msk     (0x1UL << SWPMI_ISR_DEACTF_Pos)               /*!< 0x00000400 */

+#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */

+#define SWPMI_ISR_RDYF_Pos       (11U)

+#define SWPMI_ISR_RDYF_Msk       (0x1UL << SWPMI_ISR_RDYF_Pos)                 /*!< 0x00000800 */

+#define SWPMI_ISR_RDYF           SWPMI_ISR_RDYF_Msk                            /*!<Transceiver ready flag          */

+

+/*******************  Bit definition for SWPMI_ICR register  ********************/

+#define SWPMI_ICR_CRXBFF_Pos     (0U)

+#define SWPMI_ICR_CRXBFF_Msk     (0x1UL << SWPMI_ICR_CRXBFF_Pos)               /*!< 0x00000001 */

+#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */

+#define SWPMI_ICR_CTXBEF_Pos     (1U)

+#define SWPMI_ICR_CTXBEF_Msk     (0x1UL << SWPMI_ICR_CTXBEF_Pos)               /*!< 0x00000002 */

+#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */

+#define SWPMI_ICR_CRXBERF_Pos    (2U)

+#define SWPMI_ICR_CRXBERF_Msk    (0x1UL << SWPMI_ICR_CRXBERF_Pos)              /*!< 0x00000004 */

+#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */

+#define SWPMI_ICR_CRXOVRF_Pos    (3U)

+#define SWPMI_ICR_CRXOVRF_Msk    (0x1UL << SWPMI_ICR_CRXOVRF_Pos)              /*!< 0x00000008 */

+#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */

+#define SWPMI_ICR_CTXUNRF_Pos    (4U)

+#define SWPMI_ICR_CTXUNRF_Msk    (0x1UL << SWPMI_ICR_CTXUNRF_Pos)              /*!< 0x00000010 */

+#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */

+#define SWPMI_ICR_CTCF_Pos       (7U)

+#define SWPMI_ICR_CTCF_Msk       (0x1UL << SWPMI_ICR_CTCF_Pos)                 /*!< 0x00000080 */

+#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */

+#define SWPMI_ICR_CSRF_Pos       (8U)

+#define SWPMI_ICR_CSRF_Msk       (0x1UL << SWPMI_ICR_CSRF_Pos)                 /*!< 0x00000100 */

+#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */

+#define SWPMI_ICR_CRDYF_Pos      (11U)

+#define SWPMI_ICR_CRDYF_Msk      (0x1UL << SWPMI_ICR_CRDYF_Pos)                /*!< 0x00000800 */

+#define SWPMI_ICR_CRDYF          SWPMI_ICR_CRDYF_Msk                           /*!<Clear transceiver ready flag         */

+

+/*******************  Bit definition for SWPMI_IER register  ********************/

+#define SWPMI_IER_RXBFIE_Pos     (0U)

+#define SWPMI_IER_RXBFIE_Msk     (0x1UL << SWPMI_IER_RXBFIE_Pos)               /*!< 0x00000001 */

+#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */

+#define SWPMI_IER_TXBEIE_Pos     (1U)

+#define SWPMI_IER_TXBEIE_Msk     (0x1UL << SWPMI_IER_TXBEIE_Pos)               /*!< 0x00000002 */

+#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */

+#define SWPMI_IER_RXBERIE_Pos    (2U)

+#define SWPMI_IER_RXBERIE_Msk    (0x1UL << SWPMI_IER_RXBERIE_Pos)              /*!< 0x00000004 */

+#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */

+#define SWPMI_IER_RXOVRIE_Pos    (3U)

+#define SWPMI_IER_RXOVRIE_Msk    (0x1UL << SWPMI_IER_RXOVRIE_Pos)              /*!< 0x00000008 */

+#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */

+#define SWPMI_IER_TXUNRIE_Pos    (4U)

+#define SWPMI_IER_TXUNRIE_Msk    (0x1UL << SWPMI_IER_TXUNRIE_Pos)              /*!< 0x00000010 */

+#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */

+#define SWPMI_IER_RIE_Pos        (5U)

+#define SWPMI_IER_RIE_Msk        (0x1UL << SWPMI_IER_RIE_Pos)                  /*!< 0x00000020 */

+#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */

+#define SWPMI_IER_TIE_Pos        (6U)

+#define SWPMI_IER_TIE_Msk        (0x1UL << SWPMI_IER_TIE_Pos)                  /*!< 0x00000040 */

+#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */

+#define SWPMI_IER_TCIE_Pos       (7U)

+#define SWPMI_IER_TCIE_Msk       (0x1UL << SWPMI_IER_TCIE_Pos)                 /*!< 0x00000080 */

+#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */

+#define SWPMI_IER_SRIE_Pos       (8U)

+#define SWPMI_IER_SRIE_Msk       (0x1UL << SWPMI_IER_SRIE_Pos)                 /*!< 0x00000100 */

+#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */

+#define SWPMI_IER_RDYIE_Pos      (11U)

+#define SWPMI_IER_RDYIE_Msk      (0x1UL << SWPMI_IER_RDYIE_Pos)                /*!< 0x00000800 */

+#define SWPMI_IER_RDYIE          SWPMI_IER_RDYIE_Msk                           /*!<Transceiver ready interrupt enable          */

+

+/*******************  Bit definition for SWPMI_RFL register  ********************/

+#define SWPMI_RFL_RFL_Pos        (0U)

+#define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */

+#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */

+#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */

+

+/*******************  Bit definition for SWPMI_TDR register  ********************/

+#define SWPMI_TDR_TD_Pos         (0U)

+#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)            /*!< 0xFFFFFFFF */

+#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */

+

+/*******************  Bit definition for SWPMI_RDR register  ********************/

+#define SWPMI_RDR_RD_Pos         (0U)

+#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)            /*!< 0xFFFFFFFF */

+#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Recive Data Register           */

+

+

+/*******************  Bit definition for SWPMI_OR register  ********************/

+#define SWPMI_OR_TBYP_Pos        (0U)

+#define SWPMI_OR_TBYP_Msk        (0x1UL << SWPMI_OR_TBYP_Pos)                  /*!< 0x00000001 */

+#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */

+#define SWPMI_OR_CLASS_Pos       (1U)

+#define SWPMI_OR_CLASS_Msk       (0x1UL << SWPMI_OR_CLASS_Pos)                 /*!< 0x00000002 */

+#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP CLASS selection */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            Window WATCHDOG                                 */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for WWDG_CR register  ********************/

+#define WWDG_CR_T_Pos           (0U)

+#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */

+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */

+#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */

+#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */

+#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */

+#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */

+#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */

+#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */

+#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */

+

+#define WWDG_CR_WDGA_Pos        (7U)

+#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */

+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */

+

+/*******************  Bit definition for WWDG_CFR register  *******************/

+#define WWDG_CFR_W_Pos          (0U)

+#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */

+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */

+#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */

+#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */

+#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */

+#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */

+#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */

+#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */

+#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */

+

+#define WWDG_CFR_EWI_Pos        (9U)

+#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */

+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */

+

+#define WWDG_CFR_WDGTB_Pos      (11U)

+#define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */

+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */

+#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000800 */

+#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00001000 */

+#define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00002000 */

+

+/*******************  Bit definition for WWDG_SR register  ********************/

+#define WWDG_SR_EWIF_Pos        (0U)

+#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */

+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                DBG                                         */

+/*                                                                            */

+/******************************************************************************/

+/*********************************  DEVICE ID  ********************************/

+#define STM32H7_DEV_ID           0x450UL

+

+/********************  Bit definition for DBGMCU_IDCODE register  *************/

+#define DBGMCU_IDCODE_DEV_ID_Pos          (0U)

+#define DBGMCU_IDCODE_DEV_ID_Msk          (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */

+#define DBGMCU_IDCODE_DEV_ID              DBGMCU_IDCODE_DEV_ID_Msk

+#define DBGMCU_IDCODE_REV_ID_Pos          (16U)

+#define DBGMCU_IDCODE_REV_ID_Msk          (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */

+#define DBGMCU_IDCODE_REV_ID              DBGMCU_IDCODE_REV_ID_Msk

+

+/********************  Bit definition for DBGMCU_CR register  *****************/

+#define DBGMCU_CR_DBG_SLEEPD1_Pos         (0U)

+#define DBGMCU_CR_DBG_SLEEPD1_Msk         (0x1UL << DBGMCU_CR_DBG_SLEEPD1_Pos) /*!< 0x00000001 */

+#define DBGMCU_CR_DBG_SLEEPD1             DBGMCU_CR_DBG_SLEEPD1_Msk

+#define DBGMCU_CR_DBG_STOPD1_Pos          (1U)

+#define DBGMCU_CR_DBG_STOPD1_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD1_Pos)  /*!< 0x00000002 */

+#define DBGMCU_CR_DBG_STOPD1              DBGMCU_CR_DBG_STOPD1_Msk

+#define DBGMCU_CR_DBG_STANDBYD1_Pos       (2U)

+#define DBGMCU_CR_DBG_STANDBYD1_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos) /*!< 0x00000004 */

+#define DBGMCU_CR_DBG_STANDBYD1           DBGMCU_CR_DBG_STANDBYD1_Msk

+#define DBGMCU_CR_DBG_SLEEPD2_Pos         (3U)

+#define DBGMCU_CR_DBG_SLEEPD2_Msk         (0x1UL << DBGMCU_CR_DBG_SLEEPD2_Pos) /*!< 0x00000008 */

+#define DBGMCU_CR_DBG_SLEEPD2             DBGMCU_CR_DBG_SLEEPD2_Msk

+#define DBGMCU_CR_DBG_STOPD2_Pos          (4U)

+#define DBGMCU_CR_DBG_STOPD2_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD2_Pos)  /*!< 0x00000010 */

+#define DBGMCU_CR_DBG_STOPD2              DBGMCU_CR_DBG_STOPD2_Msk

+#define DBGMCU_CR_DBG_STANDBYD2_Pos       (5U)

+#define DBGMCU_CR_DBG_STANDBYD2_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD2_Pos) /*!< 0x00000020 */

+#define DBGMCU_CR_DBG_STANDBYD2           DBGMCU_CR_DBG_STANDBYD2_Msk

+#define DBGMCU_CR_DBG_STOPD3_Pos          (7U)

+#define DBGMCU_CR_DBG_STOPD3_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos)  /*!< 0x00000080 */

+#define DBGMCU_CR_DBG_STOPD3              DBGMCU_CR_DBG_STOPD3_Msk

+#define DBGMCU_CR_DBG_STANDBYD3_Pos       (8U)

+#define DBGMCU_CR_DBG_STANDBYD3_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos) /*!< 0x00000100 */

+#define DBGMCU_CR_DBG_STANDBYD3           DBGMCU_CR_DBG_STANDBYD3_Msk

+#define DBGMCU_CR_DBG_TRACECKEN_Pos       (20U)

+#define DBGMCU_CR_DBG_TRACECKEN_Msk       (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */

+#define DBGMCU_CR_DBG_TRACECKEN           DBGMCU_CR_DBG_TRACECKEN_Msk

+#define DBGMCU_CR_DBG_CKD1EN_Pos          (21U)

+#define DBGMCU_CR_DBG_CKD1EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD1EN_Pos)  /*!< 0x00200000 */

+#define DBGMCU_CR_DBG_CKD1EN              DBGMCU_CR_DBG_CKD1EN_Msk

+#define DBGMCU_CR_DBG_CKD3EN_Pos          (22U)

+#define DBGMCU_CR_DBG_CKD3EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD3EN_Pos)  /*!< 0x00400000 */

+#define DBGMCU_CR_DBG_CKD3EN              DBGMCU_CR_DBG_CKD3EN_Msk

+#define DBGMCU_CR_DBG_TRGOEN_Pos          (28U)

+#define DBGMCU_CR_DBG_TRGOEN_Msk          (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)  /*!< 0x10000000 */

+#define DBGMCU_CR_DBG_TRGOEN              DBGMCU_CR_DBG_TRGOEN_Msk

+

+/********************  Bit definition for APB3FZ1 register  ************/

+#define DBGMCU_APB3FZ1_DBG_WWDG1_Pos      (6U)

+#define DBGMCU_APB3FZ1_DBG_WWDG1_Msk      (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB3FZ1_DBG_WWDG1          DBGMCU_APB3FZ1_DBG_WWDG1_Msk

+/********************  Bit definition for APB3FZ2 register  ************/

+#define DBGMCU_APB3FZ2_DBG_WWDG1_Pos      (6U)

+#define DBGMCU_APB3FZ2_DBG_WWDG1_Msk      (0x1UL << DBGMCU_APB3FZ2_DBG_WWDG1_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB3FZ2_DBG_WWDG1          DBGMCU_APB3FZ2_DBG_WWDG1_Msk

+/********************  Bit definition for APB1LFZ1 register  ************/

+#define DBGMCU_APB1LFZ1_DBG_TIM2_Pos      (0U)

+#define DBGMCU_APB1LFZ1_DBG_TIM2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB1LFZ1_DBG_TIM2          DBGMCU_APB1LFZ1_DBG_TIM2_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM3_Pos      (1U)

+#define DBGMCU_APB1LFZ1_DBG_TIM3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB1LFZ1_DBG_TIM3          DBGMCU_APB1LFZ1_DBG_TIM3_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM4_Pos      (2U)

+#define DBGMCU_APB1LFZ1_DBG_TIM4_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */

+#define DBGMCU_APB1LFZ1_DBG_TIM4          DBGMCU_APB1LFZ1_DBG_TIM4_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM5_Pos      (3U)

+#define DBGMCU_APB1LFZ1_DBG_TIM5_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */

+#define DBGMCU_APB1LFZ1_DBG_TIM5          DBGMCU_APB1LFZ1_DBG_TIM5_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM6_Pos      (4U)

+#define DBGMCU_APB1LFZ1_DBG_TIM6_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */

+#define DBGMCU_APB1LFZ1_DBG_TIM6          DBGMCU_APB1LFZ1_DBG_TIM6_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM7_Pos      (5U)

+#define DBGMCU_APB1LFZ1_DBG_TIM7_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */

+#define DBGMCU_APB1LFZ1_DBG_TIM7          DBGMCU_APB1LFZ1_DBG_TIM7_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM12_Pos     (6U)

+#define DBGMCU_APB1LFZ1_DBG_TIM12_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB1LFZ1_DBG_TIM12         DBGMCU_APB1LFZ1_DBG_TIM12_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM13_Pos     (7U)

+#define DBGMCU_APB1LFZ1_DBG_TIM13_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB1LFZ1_DBG_TIM13         DBGMCU_APB1LFZ1_DBG_TIM13_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM14_Pos     (8U)

+#define DBGMCU_APB1LFZ1_DBG_TIM14_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */

+#define DBGMCU_APB1LFZ1_DBG_TIM14         DBGMCU_APB1LFZ1_DBG_TIM14_Msk

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos    (9U)

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1        DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk

+#define DBGMCU_APB1LFZ1_DBG_WWDG2_Pos     (11U)

+#define DBGMCU_APB1LFZ1_DBG_WWDG2_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_WWDG2_Pos) /*!< 0x00000800 */

+#define DBGMCU_APB1LFZ1_DBG_WWDG2         DBGMCU_APB1LFZ1_DBG_WWDG2_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C1_Pos      (21U)

+#define DBGMCU_APB1LFZ1_DBG_I2C1_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C1          DBGMCU_APB1LFZ1_DBG_I2C1_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C2_Pos      (22U)

+#define DBGMCU_APB1LFZ1_DBG_I2C2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C2          DBGMCU_APB1LFZ1_DBG_I2C2_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C3_Pos      (23U)

+#define DBGMCU_APB1LFZ1_DBG_I2C3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C3          DBGMCU_APB1LFZ1_DBG_I2C3_Msk

+

+/********************  Bit definition for APB1LFZ2 register  ************/

+#define DBGMCU_APB1LFZ2_DBG_TIM2_Pos      (0U)

+#define DBGMCU_APB1LFZ2_DBG_TIM2_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM2_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB1LFZ2_DBG_TIM2          DBGMCU_APB1LFZ2_DBG_TIM2_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM3_Pos      (1U)

+#define DBGMCU_APB1LFZ2_DBG_TIM3_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM3_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB1LFZ2_DBG_TIM3          DBGMCU_APB1LFZ2_DBG_TIM3_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM4_Pos      (2U)

+#define DBGMCU_APB1LFZ2_DBG_TIM4_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM4_Pos) /*!< 0x00000004 */

+#define DBGMCU_APB1LFZ2_DBG_TIM4          DBGMCU_APB1LFZ2_DBG_TIM4_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM5_Pos      (3U)

+#define DBGMCU_APB1LFZ2_DBG_TIM5_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM5_Pos) /*!< 0x00000008 */

+#define DBGMCU_APB1LFZ2_DBG_TIM5          DBGMCU_APB1LFZ2_DBG_TIM5_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM6_Pos      (4U)

+#define DBGMCU_APB1LFZ2_DBG_TIM6_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM6_Pos) /*!< 0x00000010 */

+#define DBGMCU_APB1LFZ2_DBG_TIM6          DBGMCU_APB1LFZ2_DBG_TIM6_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM7_Pos      (5U)

+#define DBGMCU_APB1LFZ2_DBG_TIM7_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM7_Pos) /*!< 0x00000020 */

+#define DBGMCU_APB1LFZ2_DBG_TIM7          DBGMCU_APB1LFZ2_DBG_TIM7_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM12_Pos     (6U)

+#define DBGMCU_APB1LFZ2_DBG_TIM12_Msk     (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM12_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB1LFZ2_DBG_TIM12         DBGMCU_APB1LFZ2_DBG_TIM12_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM13_Pos     (7U)

+#define DBGMCU_APB1LFZ2_DBG_TIM13_Msk     (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM13_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB1LFZ2_DBG_TIM13         DBGMCU_APB1LFZ2_DBG_TIM13_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM14_Pos     (8U)

+#define DBGMCU_APB1LFZ2_DBG_TIM14_Msk     (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM14_Pos) /*!< 0x00000100 */

+#define DBGMCU_APB1LFZ2_DBG_TIM14         DBGMCU_APB1LFZ2_DBG_TIM14_Msk

+#define DBGMCU_APB1LFZ2_DBG_LPTIM1_Pos    (9U)

+#define DBGMCU_APB1LFZ2_DBG_LPTIM1_Msk    (0x1UL << DBGMCU_APB1LFZ2_DBG_LPTIM1_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB1LFZ2_DBG_LPTIM1        DBGMCU_APB1LFZ2_DBG_LPTIM1_Msk

+#define DBGMCU_APB1LFZ2_DBG_WWDG2_Pos     (11U)

+#define DBGMCU_APB1LFZ2_DBG_WWDG2_Msk     (0x1UL << DBGMCU_APB1LFZ2_DBG_WWDG2_Pos) /*!< 0x00000800 */

+#define DBGMCU_APB1LFZ2_DBG_WWDG2         DBGMCU_APB1LFZ2_DBG_WWDG2_Msk

+#define DBGMCU_APB1LFZ2_DBG_I2C1_Pos      (21U)

+#define DBGMCU_APB1LFZ2_DBG_I2C1_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C1_Pos) /*!< 0x00200000 */

+#define DBGMCU_APB1LFZ2_DBG_I2C1          DBGMCU_APB1LFZ2_DBG_I2C1_Msk

+#define DBGMCU_APB1LFZ2_DBG_I2C2_Pos      (22U)

+#define DBGMCU_APB1LFZ2_DBG_I2C2_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C2_Pos) /*!< 0x00400000 */

+#define DBGMCU_APB1LFZ2_DBG_I2C2          DBGMCU_APB1LFZ2_DBG_I2C2_Msk

+#define DBGMCU_APB1LFZ2_DBG_I2C3_Pos      (23U)

+#define DBGMCU_APB1LFZ2_DBG_I2C3_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C3_Pos) /*!< 0x00800000 */

+#define DBGMCU_APB1LFZ2_DBG_I2C3          DBGMCU_APB1LFZ2_DBG_I2C3_Msk

+/********************  Bit definition for APB1HFZ1 register  ************/

+#define DBGMCU_APB1HFZ1_DBG_FDCAN_Pos     (8U)

+#define DBGMCU_APB1HFZ1_DBG_FDCAN_Msk     (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_Pos) /*!< 0x00000100 */

+#define DBGMCU_APB1HFZ1_DBG_FDCAN         DBGMCU_APB1HFZ1_DBG_FDCAN_Msk

+/********************  Bit definition for APB1HFZ2 register  ************/

+#define DBGMCU_APB1HFZ2_DBG_FDCAN_Pos     (8U)

+#define DBGMCU_APB1HFZ2_DBG_FDCAN_Msk     (0x1UL << DBGMCU_APB1HFZ2_DBG_FDCAN_Pos) /*!< 0x00000100 */

+#define DBGMCU_APB1HFZ2_DBG_FDCAN         DBGMCU_APB1HFZ2_DBG_FDCAN_Msk

+

+/********************  Bit definition for APB2FZ1 register  ************/

+#define DBGMCU_APB2FZ1_DBG_TIM1_Pos       (0U)

+#define DBGMCU_APB2FZ1_DBG_TIM1_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB2FZ1_DBG_TIM1           DBGMCU_APB2FZ1_DBG_TIM1_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM8_Pos       (1U)

+#define DBGMCU_APB2FZ1_DBG_TIM8_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB2FZ1_DBG_TIM8           DBGMCU_APB2FZ1_DBG_TIM8_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM15_Pos      (16U)

+#define DBGMCU_APB2FZ1_DBG_TIM15_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB2FZ1_DBG_TIM15          DBGMCU_APB2FZ1_DBG_TIM15_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM16_Pos      (17U)

+#define DBGMCU_APB2FZ1_DBG_TIM16_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */

+#define DBGMCU_APB2FZ1_DBG_TIM16          DBGMCU_APB2FZ1_DBG_TIM16_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM17_Pos      (18U)

+#define DBGMCU_APB2FZ1_DBG_TIM17_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB2FZ1_DBG_TIM17          DBGMCU_APB2FZ1_DBG_TIM17_Msk

+#define DBGMCU_APB2FZ1_DBG_HRTIM_Pos      (29U)

+#define DBGMCU_APB2FZ1_DBG_HRTIM_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_HRTIM_Pos) /*!< 0x20000000 */

+#define DBGMCU_APB2FZ1_DBG_HRTIM          DBGMCU_APB2FZ1_DBG_HRTIM_Msk

+

+/********************  Bit definition for APB2FZ2 register  ************/

+#define DBGMCU_APB2FZ2_DBG_TIM1_Pos       (0U)

+#define DBGMCU_APB2FZ2_DBG_TIM1_Msk       (0x1UL << DBGMCU_APB2FZ2_DBG_TIM1_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB2FZ2_DBG_TIM1           DBGMCU_APB2FZ2_DBG_TIM1_Msk

+#define DBGMCU_APB2FZ2_DBG_TIM8_Pos       (1U)

+#define DBGMCU_APB2FZ2_DBG_TIM8_Msk       (0x1UL << DBGMCU_APB2FZ2_DBG_TIM8_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB2FZ2_DBG_TIM8           DBGMCU_APB2FZ2_DBG_TIM8_Msk

+#define DBGMCU_APB2FZ2_DBG_TIM15_Pos      (16U)

+#define DBGMCU_APB2FZ2_DBG_TIM15_Msk      (0x1UL << DBGMCU_APB2FZ2_DBG_TIM15_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB2FZ2_DBG_TIM15          DBGMCU_APB2FZ2_DBG_TIM15_Msk

+#define DBGMCU_APB2FZ2_DBG_TIM16_Pos      (17U)

+#define DBGMCU_APB2FZ2_DBG_TIM16_Msk      (0x1UL << DBGMCU_APB2FZ2_DBG_TIM16_Pos) /*!< 0x00020000 */

+#define DBGMCU_APB2FZ2_DBG_TIM16          DBGMCU_APB2FZ2_DBG_TIM16_Msk

+#define DBGMCU_APB2FZ2_DBG_TIM17_Pos      (18U)

+#define DBGMCU_APB2FZ2_DBG_TIM17_Msk      (0x1UL << DBGMCU_APB2FZ2_DBG_TIM17_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB2FZ2_DBG_TIM17          DBGMCU_APB2FZ2_DBG_TIM17_Msk

+#define DBGMCU_APB2FZ2_DBG_HRTIM_Pos      (29U)

+#define DBGMCU_APB2FZ2_DBG_HRTIM_Msk      (0x1UL << DBGMCU_APB2FZ2_DBG_HRTIM_Pos) /*!< 0x20000000 */

+#define DBGMCU_APB2FZ2_DBG_HRTIM          DBGMCU_APB2FZ2_DBG_HRTIM_Msk

+/********************  Bit definition for APB4FZ1 register  ************/

+#define DBGMCU_APB4FZ1_DBG_I2C4_Pos       (7U)

+#define DBGMCU_APB4FZ1_DBG_I2C4_Msk       (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB4FZ1_DBG_I2C4           DBGMCU_APB4FZ1_DBG_I2C4_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos     (9U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM2         DBGMCU_APB4FZ1_DBG_LPTIM2_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos     (10U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM3         DBGMCU_APB4FZ1_DBG_LPTIM3_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM4_Pos     (11U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM4_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos) /*!< 0x00000800 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM4         DBGMCU_APB4FZ1_DBG_LPTIM4_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM5_Pos     (12U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM5_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos) /*!< 0x00001000 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM5         DBGMCU_APB4FZ1_DBG_LPTIM5_Msk

+#define DBGMCU_APB4FZ1_DBG_RTC_Pos        (16U)

+#define DBGMCU_APB4FZ1_DBG_RTC_Msk        (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB4FZ1_DBG_RTC            DBGMCU_APB4FZ1_DBG_RTC_Msk

+#define DBGMCU_APB4FZ1_DBG_IWDG1_Pos      (18U)

+#define DBGMCU_APB4FZ1_DBG_IWDG1_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB4FZ1_DBG_IWDG1          DBGMCU_APB4FZ1_DBG_IWDG1_Msk

+#define DBGMCU_APB4FZ1_DBG_IWDG2_Pos      (19U)

+#define DBGMCU_APB4FZ1_DBG_IWDG2_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG2_Pos) /*!< 0x00080000 */

+#define DBGMCU_APB4FZ1_DBG_IWDG2          DBGMCU_APB4FZ1_DBG_IWDG2_Msk

+/********************  Bit definition for APB4FZ2 register  ************/

+#define DBGMCU_APB4FZ2_DBG_I2C4_Pos       (7U)

+#define DBGMCU_APB4FZ2_DBG_I2C4_Msk       (0x1UL << DBGMCU_APB4FZ2_DBG_I2C4_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB4FZ2_DBG_I2C4           DBGMCU_APB4FZ2_DBG_I2C4_Msk

+#define DBGMCU_APB4FZ2_DBG_LPTIM2_Pos     (9U)

+#define DBGMCU_APB4FZ2_DBG_LPTIM2_Msk     (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM2_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB4FZ2_DBG_LPTIM2         DBGMCU_APB4FZ2_DBG_LPTIM2_Msk

+#define DBGMCU_APB4FZ2_DBG_LPTIM3_Pos     (10U)

+#define DBGMCU_APB4FZ2_DBG_LPTIM3_Msk     (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM3_Pos) /*!< 0x00000400 */

+#define DBGMCU_APB4FZ2_DBG_LPTIM3         DBGMCU_APB4FZ2_DBG_LPTIM3_Msk

+#define DBGMCU_APB4FZ2_DBG_LPTIM4_Pos     (11U)

+#define DBGMCU_APB4FZ2_DBG_LPTIM4_Msk     (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM4_Pos) /*!< 0x00000800 */

+#define DBGMCU_APB4FZ2_DBG_LPTIM4         DBGMCU_APB4FZ2_DBG_LPTIM4_Msk

+#define DBGMCU_APB4FZ2_DBG_LPTIM5_Pos     (12U)

+#define DBGMCU_APB4FZ2_DBG_LPTIM5_Msk     (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM5_Pos) /*!< 0x00001000 */

+#define DBGMCU_APB4FZ2_DBG_LPTIM5         DBGMCU_APB4FZ2_DBG_LPTIM5_Msk

+#define DBGMCU_APB4FZ2_DBG_RTC_Pos        (16U)

+#define DBGMCU_APB4FZ2_DBG_RTC_Msk        (0x1UL << DBGMCU_APB4FZ2_DBG_RTC_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB4FZ2_DBG_RTC            DBGMCU_APB4FZ2_DBG_RTC_Msk

+#define DBGMCU_APB4FZ2_DBG_IWDG1_Pos      (18U)

+#define DBGMCU_APB4FZ2_DBG_IWDG1_Msk      (0x1UL << DBGMCU_APB4FZ2_DBG_IWDG1_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB4FZ2_DBG_IWDG1          DBGMCU_APB4FZ2_DBG_IWDG1_Msk

+#define DBGMCU_APB4FZ2_DBG_IWDG2_Pos      (19U)

+#define DBGMCU_APB4FZ2_DBG_IWDG2_Msk      (0x1UL << DBGMCU_APB4FZ2_DBG_IWDG2_Pos) /*!< 0x00080000 */

+#define DBGMCU_APB4FZ2_DBG_IWDG2          DBGMCU_APB4FZ2_DBG_IWDG2_Msk

+/******************************************************************************/

+/*                                                                            */

+/*                        High Resolution Timer (HRTIM)                       */

+/*                                                                            */

+/******************************************************************************/

+/******************** Master Timer control register ***************************/

+#define HRTIM_MCR_CK_PSC_Pos          (0U)

+#define HRTIM_MCR_CK_PSC_Msk          (0x7UL << HRTIM_MCR_CK_PSC_Pos)          /*!< 0x00000007 */

+#define HRTIM_MCR_CK_PSC              HRTIM_MCR_CK_PSC_Msk                     /*!< Prescaler mask */

+#define HRTIM_MCR_CK_PSC_0            (0x1UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000001 */

+#define HRTIM_MCR_CK_PSC_1            (0x2UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000002 */

+#define HRTIM_MCR_CK_PSC_2            (0x4UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000004 */

+

+#define HRTIM_MCR_CONT_Pos            (3U)

+#define HRTIM_MCR_CONT_Msk            (0x1UL << HRTIM_MCR_CONT_Pos)            /*!< 0x00000008 */

+#define HRTIM_MCR_CONT                HRTIM_MCR_CONT_Msk                       /*!< Continuous mode */

+#define HRTIM_MCR_RETRIG_Pos          (4U)

+#define HRTIM_MCR_RETRIG_Msk          (0x1UL << HRTIM_MCR_RETRIG_Pos)          /*!< 0x00000010 */

+#define HRTIM_MCR_RETRIG              HRTIM_MCR_RETRIG_Msk                     /*!< Rettrigreable mode */

+#define HRTIM_MCR_HALF_Pos            (5U)

+#define HRTIM_MCR_HALF_Msk            (0x1UL << HRTIM_MCR_HALF_Pos)            /*!< 0x00000020 */

+#define HRTIM_MCR_HALF                HRTIM_MCR_HALF_Msk                       /*!< Half mode */

+

+#define HRTIM_MCR_SYNC_IN_Pos         (8U)

+#define HRTIM_MCR_SYNC_IN_Msk         (0x3UL << HRTIM_MCR_SYNC_IN_Pos)         /*!< 0x00000300 */

+#define HRTIM_MCR_SYNC_IN             HRTIM_MCR_SYNC_IN_Msk                    /*!< Synchronization input master */

+#define HRTIM_MCR_SYNC_IN_0           (0x1UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000100 */

+#define HRTIM_MCR_SYNC_IN_1           (0x2UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000200 */

+#define HRTIM_MCR_SYNCRSTM_Pos        (10U)

+#define HRTIM_MCR_SYNCRSTM_Msk        (0x1UL << HRTIM_MCR_SYNCRSTM_Pos)        /*!< 0x00000400 */

+#define HRTIM_MCR_SYNCRSTM            HRTIM_MCR_SYNCRSTM_Msk                   /*!< Synchronization reset master */

+#define HRTIM_MCR_SYNCSTRTM_Pos       (11U)

+#define HRTIM_MCR_SYNCSTRTM_Msk       (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos)       /*!< 0x00000800 */

+#define HRTIM_MCR_SYNCSTRTM           HRTIM_MCR_SYNCSTRTM_Msk                  /*!< Synchronization start master */

+#define HRTIM_MCR_SYNC_OUT_Pos        (12U)

+#define HRTIM_MCR_SYNC_OUT_Msk        (0x3UL << HRTIM_MCR_SYNC_OUT_Pos)        /*!< 0x00003000 */

+#define HRTIM_MCR_SYNC_OUT            HRTIM_MCR_SYNC_OUT_Msk                   /*!< Synchronization output master */

+#define HRTIM_MCR_SYNC_OUT_0          (0x1UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00001000 */

+#define HRTIM_MCR_SYNC_OUT_1          (0x2UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00002000 */

+#define HRTIM_MCR_SYNC_SRC_Pos        (14U)

+#define HRTIM_MCR_SYNC_SRC_Msk        (0x3UL << HRTIM_MCR_SYNC_SRC_Pos)        /*!< 0x0000C000 */

+#define HRTIM_MCR_SYNC_SRC            HRTIM_MCR_SYNC_SRC_Msk                   /*!< Synchronization source */

+#define HRTIM_MCR_SYNC_SRC_0          (0x1UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00004000 */

+#define HRTIM_MCR_SYNC_SRC_1          (0x2UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00008000 */

+

+#define HRTIM_MCR_MCEN_Pos            (16U)

+#define HRTIM_MCR_MCEN_Msk            (0x1UL << HRTIM_MCR_MCEN_Pos)            /*!< 0x00010000 */

+#define HRTIM_MCR_MCEN                HRTIM_MCR_MCEN_Msk                       /*!< Master counter enable */

+#define HRTIM_MCR_TACEN_Pos           (17U)

+#define HRTIM_MCR_TACEN_Msk           (0x1UL << HRTIM_MCR_TACEN_Pos)           /*!< 0x00020000 */

+#define HRTIM_MCR_TACEN               HRTIM_MCR_TACEN_Msk                      /*!< Timer A counter enable */

+#define HRTIM_MCR_TBCEN_Pos           (18U)

+#define HRTIM_MCR_TBCEN_Msk           (0x1UL << HRTIM_MCR_TBCEN_Pos)           /*!< 0x00040000 */

+#define HRTIM_MCR_TBCEN               HRTIM_MCR_TBCEN_Msk                      /*!< Timer B counter enable */

+#define HRTIM_MCR_TCCEN_Pos           (19U)

+#define HRTIM_MCR_TCCEN_Msk           (0x1UL << HRTIM_MCR_TCCEN_Pos)           /*!< 0x00080000 */

+#define HRTIM_MCR_TCCEN               HRTIM_MCR_TCCEN_Msk                      /*!< Timer C counter enable */

+#define HRTIM_MCR_TDCEN_Pos           (20U)

+#define HRTIM_MCR_TDCEN_Msk           (0x1UL << HRTIM_MCR_TDCEN_Pos)           /*!< 0x00100000 */

+#define HRTIM_MCR_TDCEN               HRTIM_MCR_TDCEN_Msk                      /*!< Timer D counter enable */

+#define HRTIM_MCR_TECEN_Pos           (21U)

+#define HRTIM_MCR_TECEN_Msk           (0x1UL << HRTIM_MCR_TECEN_Pos)           /*!< 0x00200000 */

+#define HRTIM_MCR_TECEN               HRTIM_MCR_TECEN_Msk                      /*!< Timer E counter enable */

+

+#define HRTIM_MCR_DACSYNC_Pos         (25U)

+#define HRTIM_MCR_DACSYNC_Msk         (0x3UL << HRTIM_MCR_DACSYNC_Pos)         /*!< 0x06000000 */

+#define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC sychronization mask */

+#define HRTIM_MCR_DACSYNC_0           (0x1UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x02000000 */

+#define HRTIM_MCR_DACSYNC_1           (0x2UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x04000000 */

+

+#define HRTIM_MCR_PREEN_Pos           (27U)

+#define HRTIM_MCR_PREEN_Msk           (0x1UL << HRTIM_MCR_PREEN_Pos)           /*!< 0x08000000 */

+#define HRTIM_MCR_PREEN               HRTIM_MCR_PREEN_Msk                      /*!< Master preload enable */

+#define HRTIM_MCR_MREPU_Pos           (29U)

+#define HRTIM_MCR_MREPU_Msk           (0x1UL << HRTIM_MCR_MREPU_Pos)           /*!< 0x20000000 */

+#define HRTIM_MCR_MREPU               HRTIM_MCR_MREPU_Msk                      /*!< Master repetition update */

+

+#define HRTIM_MCR_BRSTDMA_Pos         (30U)

+#define HRTIM_MCR_BRSTDMA_Msk         (0x3UL << HRTIM_MCR_BRSTDMA_Pos)         /*!< 0xC0000000 */

+#define HRTIM_MCR_BRSTDMA             HRTIM_MCR_BRSTDMA_Msk                    /*!< Burst DMA update */

+#define HRTIM_MCR_BRSTDMA_0           (0x1UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x40000000 */

+#define HRTIM_MCR_BRSTDMA_1           (0x2UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x80000000 */

+

+/******************** Master Timer Interrupt status register ******************/

+#define HRTIM_MISR_MCMP1_Pos          (0U)

+#define HRTIM_MISR_MCMP1_Msk          (0x1UL << HRTIM_MISR_MCMP1_Pos)          /*!< 0x00000001 */

+#define HRTIM_MISR_MCMP1              HRTIM_MISR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag */

+#define HRTIM_MISR_MCMP2_Pos          (1U)

+#define HRTIM_MISR_MCMP2_Msk          (0x1UL << HRTIM_MISR_MCMP2_Pos)          /*!< 0x00000002 */

+#define HRTIM_MISR_MCMP2              HRTIM_MISR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag */

+#define HRTIM_MISR_MCMP3_Pos          (2U)

+#define HRTIM_MISR_MCMP3_Msk          (0x1UL << HRTIM_MISR_MCMP3_Pos)          /*!< 0x00000004 */

+#define HRTIM_MISR_MCMP3              HRTIM_MISR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag */

+#define HRTIM_MISR_MCMP4_Pos          (3U)

+#define HRTIM_MISR_MCMP4_Msk          (0x1UL << HRTIM_MISR_MCMP4_Pos)          /*!< 0x00000008 */

+#define HRTIM_MISR_MCMP4              HRTIM_MISR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag */

+#define HRTIM_MISR_MREP_Pos           (4U)

+#define HRTIM_MISR_MREP_Msk           (0x1UL << HRTIM_MISR_MREP_Pos)           /*!< 0x00000010 */

+#define HRTIM_MISR_MREP               HRTIM_MISR_MREP_Msk                      /*!< Master Repetition interrupt flag */

+#define HRTIM_MISR_SYNC_Pos           (5U)

+#define HRTIM_MISR_SYNC_Msk           (0x1UL << HRTIM_MISR_SYNC_Pos)           /*!< 0x00000020 */

+#define HRTIM_MISR_SYNC               HRTIM_MISR_SYNC_Msk                      /*!< Synchronization input interrupt flag */

+#define HRTIM_MISR_MUPD_Pos           (6U)

+#define HRTIM_MISR_MUPD_Msk           (0x1UL << HRTIM_MISR_MUPD_Pos)           /*!< 0x00000040 */

+#define HRTIM_MISR_MUPD               HRTIM_MISR_MUPD_Msk                      /*!< Master update interrupt flag */

+

+/******************** Master Timer Interrupt clear register *******************/

+#define HRTIM_MICR_MCMP1_Pos          (0U)

+#define HRTIM_MICR_MCMP1_Msk          (0x1UL << HRTIM_MICR_MCMP1_Pos)          /*!< 0x00000001 */

+#define HRTIM_MICR_MCMP1              HRTIM_MICR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag clear */

+#define HRTIM_MICR_MCMP2_Pos          (1U)

+#define HRTIM_MICR_MCMP2_Msk          (0x1UL << HRTIM_MICR_MCMP2_Pos)          /*!< 0x00000002 */

+#define HRTIM_MICR_MCMP2              HRTIM_MICR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag clear */

+#define HRTIM_MICR_MCMP3_Pos          (2U)

+#define HRTIM_MICR_MCMP3_Msk          (0x1UL << HRTIM_MICR_MCMP3_Pos)          /*!< 0x00000004 */

+#define HRTIM_MICR_MCMP3              HRTIM_MICR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag clear */

+#define HRTIM_MICR_MCMP4_Pos          (3U)

+#define HRTIM_MICR_MCMP4_Msk          (0x1UL << HRTIM_MICR_MCMP4_Pos)          /*!< 0x00000008 */

+#define HRTIM_MICR_MCMP4              HRTIM_MICR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag clear */

+#define HRTIM_MICR_MREP_Pos           (4U)

+#define HRTIM_MICR_MREP_Msk           (0x1UL << HRTIM_MICR_MREP_Pos)           /*!< 0x00000010 */

+#define HRTIM_MICR_MREP               HRTIM_MICR_MREP_Msk                      /*!< Master Repetition interrupt flag clear */

+#define HRTIM_MICR_SYNC_Pos           (5U)

+#define HRTIM_MICR_SYNC_Msk           (0x1UL << HRTIM_MICR_SYNC_Pos)           /*!< 0x00000020 */

+#define HRTIM_MICR_SYNC               HRTIM_MICR_SYNC_Msk                      /*!< Synchronization input interrupt flag clear */

+#define HRTIM_MICR_MUPD_Pos           (6U)

+#define HRTIM_MICR_MUPD_Msk           (0x1UL << HRTIM_MICR_MUPD_Pos)           /*!< 0x00000040 */

+#define HRTIM_MICR_MUPD               HRTIM_MICR_MUPD_Msk                      /*!< Master update interrupt flag clear */

+

+/******************** Master Timer DMA/Interrupt enable register **************/

+#define HRTIM_MDIER_MCMP1IE_Pos       (0U)

+#define HRTIM_MDIER_MCMP1IE_Msk       (0x1UL << HRTIM_MDIER_MCMP1IE_Pos)       /*!< 0x00000001 */

+#define HRTIM_MDIER_MCMP1IE           HRTIM_MDIER_MCMP1IE_Msk                  /*!< Master compare 1 interrupt enable */

+#define HRTIM_MDIER_MCMP2IE_Pos       (1U)

+#define HRTIM_MDIER_MCMP2IE_Msk       (0x1UL << HRTIM_MDIER_MCMP2IE_Pos)       /*!< 0x00000002 */

+#define HRTIM_MDIER_MCMP2IE           HRTIM_MDIER_MCMP2IE_Msk                  /*!< Master compare 2 interrupt enable */

+#define HRTIM_MDIER_MCMP3IE_Pos       (2U)

+#define HRTIM_MDIER_MCMP3IE_Msk       (0x1UL << HRTIM_MDIER_MCMP3IE_Pos)       /*!< 0x00000004 */

+#define HRTIM_MDIER_MCMP3IE           HRTIM_MDIER_MCMP3IE_Msk                  /*!< Master compare 3 interrupt enable */

+#define HRTIM_MDIER_MCMP4IE_Pos       (3U)

+#define HRTIM_MDIER_MCMP4IE_Msk       (0x1UL << HRTIM_MDIER_MCMP4IE_Pos)       /*!< 0x00000008 */

+#define HRTIM_MDIER_MCMP4IE           HRTIM_MDIER_MCMP4IE_Msk                  /*!< Master compare 4 interrupt enable */

+#define HRTIM_MDIER_MREPIE_Pos        (4U)

+#define HRTIM_MDIER_MREPIE_Msk        (0x1UL << HRTIM_MDIER_MREPIE_Pos)        /*!< 0x00000010 */

+#define HRTIM_MDIER_MREPIE            HRTIM_MDIER_MREPIE_Msk                   /*!< Master Repetition interrupt enable */

+#define HRTIM_MDIER_SYNCIE_Pos        (5U)

+#define HRTIM_MDIER_SYNCIE_Msk        (0x1UL << HRTIM_MDIER_SYNCIE_Pos)        /*!< 0x00000020 */

+#define HRTIM_MDIER_SYNCIE            HRTIM_MDIER_SYNCIE_Msk                   /*!< Synchronization input interrupt enable */

+#define HRTIM_MDIER_MUPDIE_Pos        (6U)

+#define HRTIM_MDIER_MUPDIE_Msk        (0x1UL << HRTIM_MDIER_MUPDIE_Pos)        /*!< 0x00000040 */

+#define HRTIM_MDIER_MUPDIE            HRTIM_MDIER_MUPDIE_Msk                   /*!< Master update interrupt enable */

+

+#define HRTIM_MDIER_MCMP1DE_Pos       (16U)

+#define HRTIM_MDIER_MCMP1DE_Msk       (0x1UL << HRTIM_MDIER_MCMP1DE_Pos)       /*!< 0x00010000 */

+#define HRTIM_MDIER_MCMP1DE           HRTIM_MDIER_MCMP1DE_Msk                  /*!< Master compare 1 DMA enable */

+#define HRTIM_MDIER_MCMP2DE_Pos       (17U)

+#define HRTIM_MDIER_MCMP2DE_Msk       (0x1UL << HRTIM_MDIER_MCMP2DE_Pos)       /*!< 0x00020000 */

+#define HRTIM_MDIER_MCMP2DE           HRTIM_MDIER_MCMP2DE_Msk                  /*!< Master compare 2 DMA enable */

+#define HRTIM_MDIER_MCMP3DE_Pos       (18U)

+#define HRTIM_MDIER_MCMP3DE_Msk       (0x1UL << HRTIM_MDIER_MCMP3DE_Pos)       /*!< 0x00040000 */

+#define HRTIM_MDIER_MCMP3DE           HRTIM_MDIER_MCMP3DE_Msk                  /*!< Master compare 3 DMA enable */

+#define HRTIM_MDIER_MCMP4DE_Pos       (19U)

+#define HRTIM_MDIER_MCMP4DE_Msk       (0x1UL << HRTIM_MDIER_MCMP4DE_Pos)       /*!< 0x00080000 */

+#define HRTIM_MDIER_MCMP4DE           HRTIM_MDIER_MCMP4DE_Msk                  /*!< Master compare 4 DMA enable */

+#define HRTIM_MDIER_MREPDE_Pos        (20U)

+#define HRTIM_MDIER_MREPDE_Msk        (0x1UL << HRTIM_MDIER_MREPDE_Pos)        /*!< 0x00100000 */

+#define HRTIM_MDIER_MREPDE            HRTIM_MDIER_MREPDE_Msk                   /*!< Master Repetition DMA enable */

+#define HRTIM_MDIER_SYNCDE_Pos        (21U)

+#define HRTIM_MDIER_SYNCDE_Msk        (0x1UL << HRTIM_MDIER_SYNCDE_Pos)        /*!< 0x00200000 */

+#define HRTIM_MDIER_SYNCDE            HRTIM_MDIER_SYNCDE_Msk                   /*!< Synchronization input DMA enable */

+#define HRTIM_MDIER_MUPDDE_Pos        (22U)

+#define HRTIM_MDIER_MUPDDE_Msk        (0x1UL << HRTIM_MDIER_MUPDDE_Pos)        /*!< 0x00400000 */

+#define HRTIM_MDIER_MUPDDE            HRTIM_MDIER_MUPDDE_Msk                   /*!< Master update DMA enable */

+

+/*******************  Bit definition for HRTIM_MCNTR register  ****************/

+#define HRTIM_MCNTR_MCNTR_Pos         (0U)

+#define HRTIM_MCNTR_MCNTR_Msk         (0xFFFFUL << HRTIM_MCNTR_MCNTR_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_MCNTR_MCNTR             HRTIM_MCNTR_MCNTR_Msk                    /*!<Counter Value */

+

+/*******************  Bit definition for HRTIM_MPER register  *****************/

+#define HRTIM_MPER_MPER_Pos           (0U)

+#define HRTIM_MPER_MPER_Msk           (0xFFFFUL << HRTIM_MPER_MPER_Pos)        /*!< 0x0000FFFF */

+#define HRTIM_MPER_MPER               HRTIM_MPER_MPER_Msk                      /*!< Period Value */

+

+/*******************  Bit definition for HRTIM_MREP register  *****************/

+#define HRTIM_MREP_MREP_Pos           (0U)

+#define HRTIM_MREP_MREP_Msk           (0xFFUL << HRTIM_MREP_MREP_Pos)          /*!< 0x000000FF */

+#define HRTIM_MREP_MREP               HRTIM_MREP_MREP_Msk                      /*!<Repetition Value */

+

+/*******************  Bit definition for HRTIM_MCMP1R register  *****************/

+#define HRTIM_MCMP1R_MCMP1R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP1R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP1R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP1R           HRTIM_MCMP1R_MCMP1R_Msk                  /*!<Compare Value */

+

+/*******************  Bit definition for HRTIM_MCMP2R register  *****************/

+#define HRTIM_MCMP1R_MCMP2R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP2R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP2R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP2R           HRTIM_MCMP1R_MCMP2R_Msk                  /*!<Compare Value */

+

+/*******************  Bit definition for HRTIM_MCMP3R register  *****************/

+#define HRTIM_MCMP1R_MCMP3R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP3R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP3R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP3R           HRTIM_MCMP1R_MCMP3R_Msk                  /*!<Compare Value */

+

+/*******************  Bit definition for HRTIM_MCMP4R register  *****************/

+#define HRTIM_MCMP1R_MCMP4R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP4R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP4R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP4R           HRTIM_MCMP1R_MCMP4R_Msk                  /*!<Compare Value */

+

+/******************** Slave control register **********************************/

+#define HRTIM_TIMCR_CK_PSC_Pos        (0U)

+#define HRTIM_TIMCR_CK_PSC_Msk        (0x7UL << HRTIM_TIMCR_CK_PSC_Pos)        /*!< 0x00000007 */

+#define HRTIM_TIMCR_CK_PSC            HRTIM_TIMCR_CK_PSC_Msk                   /*!< Slave prescaler mask*/

+#define HRTIM_TIMCR_CK_PSC_0          (0x1UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000001 */

+#define HRTIM_TIMCR_CK_PSC_1          (0x2UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000002 */

+#define HRTIM_TIMCR_CK_PSC_2          (0x4UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000004 */

+

+#define HRTIM_TIMCR_CONT_Pos          (3U)

+#define HRTIM_TIMCR_CONT_Msk          (0x1UL << HRTIM_TIMCR_CONT_Pos)          /*!< 0x00000008 */

+#define HRTIM_TIMCR_CONT              HRTIM_TIMCR_CONT_Msk                     /*!< Slave continuous mode */

+#define HRTIM_TIMCR_RETRIG_Pos        (4U)

+#define HRTIM_TIMCR_RETRIG_Msk        (0x1UL << HRTIM_TIMCR_RETRIG_Pos)        /*!< 0x00000010 */

+#define HRTIM_TIMCR_RETRIG            HRTIM_TIMCR_RETRIG_Msk                   /*!< Slave Retrigreable mode */

+#define HRTIM_TIMCR_HALF_Pos          (5U)

+#define HRTIM_TIMCR_HALF_Msk          (0x1UL << HRTIM_TIMCR_HALF_Pos)          /*!< 0x00000020 */

+#define HRTIM_TIMCR_HALF              HRTIM_TIMCR_HALF_Msk                     /*!< Slave Half mode */

+#define HRTIM_TIMCR_PSHPLL_Pos        (6U)

+#define HRTIM_TIMCR_PSHPLL_Msk        (0x1UL << HRTIM_TIMCR_PSHPLL_Pos)        /*!< 0x00000040 */

+#define HRTIM_TIMCR_PSHPLL            HRTIM_TIMCR_PSHPLL_Msk                   /*!< Slave push-pull mode */

+

+#define HRTIM_TIMCR_SYNCRST_Pos       (10U)

+#define HRTIM_TIMCR_SYNCRST_Msk       (0x1UL << HRTIM_TIMCR_SYNCRST_Pos)       /*!< 0x00000400 */

+#define HRTIM_TIMCR_SYNCRST           HRTIM_TIMCR_SYNCRST_Msk                  /*!< Slave synchronization resets */

+#define HRTIM_TIMCR_SYNCSTRT_Pos      (11U)

+#define HRTIM_TIMCR_SYNCSTRT_Msk      (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos)      /*!< 0x00000800 */

+#define HRTIM_TIMCR_SYNCSTRT          HRTIM_TIMCR_SYNCSTRT_Msk                 /*!< Slave synchronization starts */

+

+#define HRTIM_TIMCR_DELCMP2_Pos       (12U)

+#define HRTIM_TIMCR_DELCMP2_Msk       (0x3UL << HRTIM_TIMCR_DELCMP2_Pos)       /*!< 0x00003000 */

+#define HRTIM_TIMCR_DELCMP2           HRTIM_TIMCR_DELCMP2_Msk                  /*!< Slave delayed compartor 2 mode mask */

+#define HRTIM_TIMCR_DELCMP2_0         (0x1UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00001000 */

+#define HRTIM_TIMCR_DELCMP2_1         (0x2UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00002000 */

+#define HRTIM_TIMCR_DELCMP4_Pos       (14U)

+#define HRTIM_TIMCR_DELCMP4_Msk       (0x3UL << HRTIM_TIMCR_DELCMP4_Pos)       /*!< 0x0000C000 */

+#define HRTIM_TIMCR_DELCMP4           HRTIM_TIMCR_DELCMP4_Msk                  /*!< Slave delayed compartor 4 mode mask */

+#define HRTIM_TIMCR_DELCMP4_0         (0x1UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00004000 */

+#define HRTIM_TIMCR_DELCMP4_1         (0x2UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00008000 */

+

+#define HRTIM_TIMCR_TREPU_Pos         (17U)

+#define HRTIM_TIMCR_TREPU_Msk         (0x1UL << HRTIM_TIMCR_TREPU_Pos)         /*!< 0x00020000 */

+#define HRTIM_TIMCR_TREPU             HRTIM_TIMCR_TREPU_Msk                    /*!< Slave repetition update */

+#define HRTIM_TIMCR_TRSTU_Pos         (18U)

+#define HRTIM_TIMCR_TRSTU_Msk         (0x1UL << HRTIM_TIMCR_TRSTU_Pos)         /*!< 0x00040000 */

+#define HRTIM_TIMCR_TRSTU             HRTIM_TIMCR_TRSTU_Msk                    /*!< Slave reset update */

+#define HRTIM_TIMCR_TAU_Pos           (19U)

+#define HRTIM_TIMCR_TAU_Msk           (0x1UL << HRTIM_TIMCR_TAU_Pos)           /*!< 0x00080000 */

+#define HRTIM_TIMCR_TAU               HRTIM_TIMCR_TAU_Msk                      /*!< Slave Timer A update reserved for TIM A */

+#define HRTIM_TIMCR_TBU_Pos           (20U)

+#define HRTIM_TIMCR_TBU_Msk           (0x1UL << HRTIM_TIMCR_TBU_Pos)           /*!< 0x00100000 */

+#define HRTIM_TIMCR_TBU               HRTIM_TIMCR_TBU_Msk                      /*!< Slave Timer B update reserved for TIM B */

+#define HRTIM_TIMCR_TCU_Pos           (21U)

+#define HRTIM_TIMCR_TCU_Msk           (0x1UL << HRTIM_TIMCR_TCU_Pos)           /*!< 0x00200000 */

+#define HRTIM_TIMCR_TCU               HRTIM_TIMCR_TCU_Msk                      /*!< Slave Timer C update reserved for TIM C */

+#define HRTIM_TIMCR_TDU_Pos           (22U)

+#define HRTIM_TIMCR_TDU_Msk           (0x1UL << HRTIM_TIMCR_TDU_Pos)           /*!< 0x00400000 */

+#define HRTIM_TIMCR_TDU               HRTIM_TIMCR_TDU_Msk                      /*!< Slave Timer D update reserved for TIM D */

+#define HRTIM_TIMCR_TEU_Pos           (23U)

+#define HRTIM_TIMCR_TEU_Msk           (0x1UL << HRTIM_TIMCR_TEU_Pos)           /*!< 0x00800000 */

+#define HRTIM_TIMCR_TEU               HRTIM_TIMCR_TEU_Msk                      /*!< Slave Timer E update reserved for TIM E */

+#define HRTIM_TIMCR_MSTU_Pos          (24U)

+#define HRTIM_TIMCR_MSTU_Msk          (0x1UL << HRTIM_TIMCR_MSTU_Pos)          /*!< 0x01000000 */

+#define HRTIM_TIMCR_MSTU              HRTIM_TIMCR_MSTU_Msk                     /*!< Master Update */

+

+#define HRTIM_TIMCR_DACSYNC_Pos       (25U)

+#define HRTIM_TIMCR_DACSYNC_Msk       (0x3UL << HRTIM_TIMCR_DACSYNC_Pos)       /*!< 0x06000000 */

+#define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC sychronization mask */

+#define HRTIM_TIMCR_DACSYNC_0         (0x1UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x02000000 */

+#define HRTIM_TIMCR_DACSYNC_1         (0x2UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x04000000 */

+#define HRTIM_TIMCR_PREEN_Pos         (27U)

+#define HRTIM_TIMCR_PREEN_Msk         (0x1UL << HRTIM_TIMCR_PREEN_Pos)         /*!< 0x08000000 */

+#define HRTIM_TIMCR_PREEN             HRTIM_TIMCR_PREEN_Msk                    /*!< Slave preload enable */

+

+#define HRTIM_TIMCR_UPDGAT_Pos        (28U)

+#define HRTIM_TIMCR_UPDGAT_Msk        (0xFUL << HRTIM_TIMCR_UPDGAT_Pos)        /*!< 0xF0000000 */

+#define HRTIM_TIMCR_UPDGAT            HRTIM_TIMCR_UPDGAT_Msk                   /*!< Slave update gating mask */

+#define HRTIM_TIMCR_UPDGAT_0          (0x1UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x10000000 */

+#define HRTIM_TIMCR_UPDGAT_1          (0x2UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x20000000 */

+#define HRTIM_TIMCR_UPDGAT_2          (0x4UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x40000000 */

+#define HRTIM_TIMCR_UPDGAT_3          (0x8UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x80000000 */

+

+/******************** Slave Interrupt status register **************************/

+#define HRTIM_TIMISR_CMP1_Pos         (0U)

+#define HRTIM_TIMISR_CMP1_Msk         (0x1UL << HRTIM_TIMISR_CMP1_Pos)         /*!< 0x00000001 */

+#define HRTIM_TIMISR_CMP1             HRTIM_TIMISR_CMP1_Msk                    /*!< Slave compare 1 interrupt flag */

+#define HRTIM_TIMISR_CMP2_Pos         (1U)

+#define HRTIM_TIMISR_CMP2_Msk         (0x1UL << HRTIM_TIMISR_CMP2_Pos)         /*!< 0x00000002 */

+#define HRTIM_TIMISR_CMP2             HRTIM_TIMISR_CMP2_Msk                    /*!< Slave compare 2 interrupt flag */

+#define HRTIM_TIMISR_CMP3_Pos         (2U)

+#define HRTIM_TIMISR_CMP3_Msk         (0x1UL << HRTIM_TIMISR_CMP3_Pos)         /*!< 0x00000004 */

+#define HRTIM_TIMISR_CMP3             HRTIM_TIMISR_CMP3_Msk                    /*!< Slave compare 3 interrupt flag */

+#define HRTIM_TIMISR_CMP4_Pos         (3U)

+#define HRTIM_TIMISR_CMP4_Msk         (0x1UL << HRTIM_TIMISR_CMP4_Pos)         /*!< 0x00000008 */

+#define HRTIM_TIMISR_CMP4             HRTIM_TIMISR_CMP4_Msk                    /*!< Slave compare 4 interrupt flag */

+#define HRTIM_TIMISR_REP_Pos          (4U)

+#define HRTIM_TIMISR_REP_Msk          (0x1UL << HRTIM_TIMISR_REP_Pos)          /*!< 0x00000010 */

+#define HRTIM_TIMISR_REP              HRTIM_TIMISR_REP_Msk                     /*!< Slave repetition interrupt flag */

+#define HRTIM_TIMISR_UPD_Pos          (6U)

+#define HRTIM_TIMISR_UPD_Msk          (0x1UL << HRTIM_TIMISR_UPD_Pos)          /*!< 0x00000040 */

+#define HRTIM_TIMISR_UPD              HRTIM_TIMISR_UPD_Msk                     /*!< Slave update interrupt flag */

+#define HRTIM_TIMISR_CPT1_Pos         (7U)

+#define HRTIM_TIMISR_CPT1_Msk         (0x1UL << HRTIM_TIMISR_CPT1_Pos)         /*!< 0x00000080 */

+#define HRTIM_TIMISR_CPT1             HRTIM_TIMISR_CPT1_Msk                    /*!< Slave capture 1 interrupt flag */

+#define HRTIM_TIMISR_CPT2_Pos         (8U)

+#define HRTIM_TIMISR_CPT2_Msk         (0x1UL << HRTIM_TIMISR_CPT2_Pos)         /*!< 0x00000100 */

+#define HRTIM_TIMISR_CPT2             HRTIM_TIMISR_CPT2_Msk                    /*!< Slave capture 2 interrupt flag */

+#define HRTIM_TIMISR_SET1_Pos         (9U)

+#define HRTIM_TIMISR_SET1_Msk         (0x1UL << HRTIM_TIMISR_SET1_Pos)         /*!< 0x00000200 */

+#define HRTIM_TIMISR_SET1             HRTIM_TIMISR_SET1_Msk                    /*!< Slave output 1 set interrupt flag */

+#define HRTIM_TIMISR_RST1_Pos         (10U)

+#define HRTIM_TIMISR_RST1_Msk         (0x1UL << HRTIM_TIMISR_RST1_Pos)         /*!< 0x00000400 */

+#define HRTIM_TIMISR_RST1             HRTIM_TIMISR_RST1_Msk                    /*!< Slave output 1 reset interrupt flag */

+#define HRTIM_TIMISR_SET2_Pos         (11U)

+#define HRTIM_TIMISR_SET2_Msk         (0x1UL << HRTIM_TIMISR_SET2_Pos)         /*!< 0x00000800 */

+#define HRTIM_TIMISR_SET2             HRTIM_TIMISR_SET2_Msk                    /*!< Slave output 2 set interrupt flag */

+#define HRTIM_TIMISR_RST2_Pos         (12U)

+#define HRTIM_TIMISR_RST2_Msk         (0x1UL << HRTIM_TIMISR_RST2_Pos)         /*!< 0x00001000 */

+#define HRTIM_TIMISR_RST2             HRTIM_TIMISR_RST2_Msk                    /*!< Slave output 2 reset interrupt flag */

+#define HRTIM_TIMISR_RST_Pos          (13U)

+#define HRTIM_TIMISR_RST_Msk          (0x1UL << HRTIM_TIMISR_RST_Pos)          /*!< 0x00002000 */

+#define HRTIM_TIMISR_RST              HRTIM_TIMISR_RST_Msk                     /*!< Slave reset interrupt flag */

+#define HRTIM_TIMISR_DLYPRT_Pos       (14U)

+#define HRTIM_TIMISR_DLYPRT_Msk       (0x1UL << HRTIM_TIMISR_DLYPRT_Pos)       /*!< 0x00004000 */

+#define HRTIM_TIMISR_DLYPRT           HRTIM_TIMISR_DLYPRT_Msk                  /*!< Slave output 1 delay protection interrupt flag */

+#define HRTIM_TIMISR_CPPSTAT_Pos      (16U)

+#define HRTIM_TIMISR_CPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos)      /*!< 0x00010000 */

+#define HRTIM_TIMISR_CPPSTAT          HRTIM_TIMISR_CPPSTAT_Msk                 /*!< Slave current push-pull flag */

+#define HRTIM_TIMISR_IPPSTAT_Pos      (17U)

+#define HRTIM_TIMISR_IPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos)      /*!< 0x00020000 */

+#define HRTIM_TIMISR_IPPSTAT          HRTIM_TIMISR_IPPSTAT_Msk                 /*!< Slave idle push-pull flag */

+#define HRTIM_TIMISR_O1STAT_Pos       (18U)

+#define HRTIM_TIMISR_O1STAT_Msk       (0x1UL << HRTIM_TIMISR_O1STAT_Pos)       /*!< 0x00040000 */

+#define HRTIM_TIMISR_O1STAT           HRTIM_TIMISR_O1STAT_Msk                  /*!< Slave output 1 state flag */

+#define HRTIM_TIMISR_O2STAT_Pos       (19U)

+#define HRTIM_TIMISR_O2STAT_Msk       (0x1UL << HRTIM_TIMISR_O2STAT_Pos)       /*!< 0x00080000 */

+#define HRTIM_TIMISR_O2STAT           HRTIM_TIMISR_O2STAT_Msk                  /*!< Slave output 2 state flag */

+#define HRTIM_TIMISR_O1CPY_Pos        (20U)

+#define HRTIM_TIMISR_O1CPY_Msk        (0x1UL << HRTIM_TIMISR_O1CPY_Pos)        /*!< 0x00100000 */

+#define HRTIM_TIMISR_O1CPY            HRTIM_TIMISR_O1CPY_Msk                   /*!< Slave output 1 copy flag */

+#define HRTIM_TIMISR_O2CPY_Pos        (21U)

+#define HRTIM_TIMISR_O2CPY_Msk        (0x1UL << HRTIM_TIMISR_O2CPY_Pos)        /*!< 0x00200000 */

+#define HRTIM_TIMISR_O2CPY            HRTIM_TIMISR_O2CPY_Msk                   /*!< Slave output 2 copy flag */

+

+/******************** Slave Interrupt clear register **************************/

+#define HRTIM_TIMICR_CMP1C_Pos        (0U)

+#define HRTIM_TIMICR_CMP1C_Msk        (0x1UL << HRTIM_TIMICR_CMP1C_Pos)        /*!< 0x00000001 */

+#define HRTIM_TIMICR_CMP1C            HRTIM_TIMICR_CMP1C_Msk                   /*!< Slave compare 1 clear flag */

+#define HRTIM_TIMICR_CMP2C_Pos        (1U)

+#define HRTIM_TIMICR_CMP2C_Msk        (0x1UL << HRTIM_TIMICR_CMP2C_Pos)        /*!< 0x00000002 */

+#define HRTIM_TIMICR_CMP2C            HRTIM_TIMICR_CMP2C_Msk                   /*!< Slave compare 2 clear flag */

+#define HRTIM_TIMICR_CMP3C_Pos        (2U)

+#define HRTIM_TIMICR_CMP3C_Msk        (0x1UL << HRTIM_TIMICR_CMP3C_Pos)        /*!< 0x00000004 */

+#define HRTIM_TIMICR_CMP3C            HRTIM_TIMICR_CMP3C_Msk                   /*!< Slave compare 3 clear flag */

+#define HRTIM_TIMICR_CMP4C_Pos        (3U)

+#define HRTIM_TIMICR_CMP4C_Msk        (0x1UL << HRTIM_TIMICR_CMP4C_Pos)        /*!< 0x00000008 */

+#define HRTIM_TIMICR_CMP4C            HRTIM_TIMICR_CMP4C_Msk                   /*!< Slave compare 4 clear flag */

+#define HRTIM_TIMICR_REPC_Pos         (4U)

+#define HRTIM_TIMICR_REPC_Msk         (0x1UL << HRTIM_TIMICR_REPC_Pos)         /*!< 0x00000010 */

+#define HRTIM_TIMICR_REPC             HRTIM_TIMICR_REPC_Msk                    /*!< Slave repetition clear flag */

+#define HRTIM_TIMICR_UPDC_Pos         (6U)

+#define HRTIM_TIMICR_UPDC_Msk         (0x1UL << HRTIM_TIMICR_UPDC_Pos)         /*!< 0x00000040 */

+#define HRTIM_TIMICR_UPDC             HRTIM_TIMICR_UPDC_Msk                    /*!< Slave update clear flag */

+#define HRTIM_TIMICR_CPT1C_Pos        (7U)

+#define HRTIM_TIMICR_CPT1C_Msk        (0x1UL << HRTIM_TIMICR_CPT1C_Pos)        /*!< 0x00000080 */

+#define HRTIM_TIMICR_CPT1C            HRTIM_TIMICR_CPT1C_Msk                   /*!< Slave capture 1 clear flag */

+#define HRTIM_TIMICR_CPT2C_Pos        (8U)

+#define HRTIM_TIMICR_CPT2C_Msk        (0x1UL << HRTIM_TIMICR_CPT2C_Pos)        /*!< 0x00000100 */

+#define HRTIM_TIMICR_CPT2C            HRTIM_TIMICR_CPT2C_Msk                   /*!< Slave capture 2 clear flag */

+#define HRTIM_TIMICR_SET1C_Pos        (9U)

+#define HRTIM_TIMICR_SET1C_Msk        (0x1UL << HRTIM_TIMICR_SET1C_Pos)        /*!< 0x00000200 */

+#define HRTIM_TIMICR_SET1C            HRTIM_TIMICR_SET1C_Msk                   /*!< Slave output 1 set clear flag */

+#define HRTIM_TIMICR_RST1C_Pos        (10U)

+#define HRTIM_TIMICR_RST1C_Msk        (0x1UL << HRTIM_TIMICR_RST1C_Pos)        /*!< 0x00000400 */

+#define HRTIM_TIMICR_RST1C            HRTIM_TIMICR_RST1C_Msk                   /*!< Slave output 1 reset clear flag */

+#define HRTIM_TIMICR_SET2C_Pos        (11U)

+#define HRTIM_TIMICR_SET2C_Msk        (0x1UL << HRTIM_TIMICR_SET2C_Pos)        /*!< 0x00000800 */

+#define HRTIM_TIMICR_SET2C            HRTIM_TIMICR_SET2C_Msk                   /*!< Slave output 2 set clear flag */

+#define HRTIM_TIMICR_RST2C_Pos        (12U)

+#define HRTIM_TIMICR_RST2C_Msk        (0x1UL << HRTIM_TIMICR_RST2C_Pos)        /*!< 0x00001000 */

+#define HRTIM_TIMICR_RST2C            HRTIM_TIMICR_RST2C_Msk                   /*!< Slave output 2 reset clear flag */

+#define HRTIM_TIMICR_RSTC_Pos         (13U)

+#define HRTIM_TIMICR_RSTC_Msk         (0x1UL << HRTIM_TIMICR_RSTC_Pos)         /*!< 0x00002000 */

+#define HRTIM_TIMICR_RSTC             HRTIM_TIMICR_RSTC_Msk                    /*!< Slave reset clear flag */

+#define HRTIM_TIMICR_DLYPRTC_Pos      (14U)

+#define HRTIM_TIMICR_DLYPRTC_Msk      (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos)      /*!< 0x00004000 */

+#define HRTIM_TIMICR_DLYPRTC          HRTIM_TIMICR_DLYPRTC_Msk                 /*!< Slave output 1 delay protection clear flag */

+

+/******************** Slave DMA/Interrupt enable register *********************/

+#define HRTIM_TIMDIER_CMP1IE_Pos      (0U)

+#define HRTIM_TIMDIER_CMP1IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos)      /*!< 0x00000001 */

+#define HRTIM_TIMDIER_CMP1IE          HRTIM_TIMDIER_CMP1IE_Msk                 /*!< Slave compare 1 interrupt enable */

+#define HRTIM_TIMDIER_CMP2IE_Pos      (1U)

+#define HRTIM_TIMDIER_CMP2IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos)      /*!< 0x00000002 */

+#define HRTIM_TIMDIER_CMP2IE          HRTIM_TIMDIER_CMP2IE_Msk                 /*!< Slave compare 2 interrupt enable */

+#define HRTIM_TIMDIER_CMP3IE_Pos      (2U)

+#define HRTIM_TIMDIER_CMP3IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos)      /*!< 0x00000004 */

+#define HRTIM_TIMDIER_CMP3IE          HRTIM_TIMDIER_CMP3IE_Msk                 /*!< Slave compare 3 interrupt enable */

+#define HRTIM_TIMDIER_CMP4IE_Pos      (3U)

+#define HRTIM_TIMDIER_CMP4IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos)      /*!< 0x00000008 */

+#define HRTIM_TIMDIER_CMP4IE          HRTIM_TIMDIER_CMP4IE_Msk                 /*!< Slave compare 4 interrupt enable */

+#define HRTIM_TIMDIER_REPIE_Pos       (4U)

+#define HRTIM_TIMDIER_REPIE_Msk       (0x1UL << HRTIM_TIMDIER_REPIE_Pos)       /*!< 0x00000010 */

+#define HRTIM_TIMDIER_REPIE           HRTIM_TIMDIER_REPIE_Msk                  /*!< Slave repetition interrupt enable */

+#define HRTIM_TIMDIER_UPDIE_Pos       (6U)

+#define HRTIM_TIMDIER_UPDIE_Msk       (0x1UL << HRTIM_TIMDIER_UPDIE_Pos)       /*!< 0x00000040 */

+#define HRTIM_TIMDIER_UPDIE           HRTIM_TIMDIER_UPDIE_Msk                  /*!< Slave update interrupt enable */

+#define HRTIM_TIMDIER_CPT1IE_Pos      (7U)

+#define HRTIM_TIMDIER_CPT1IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos)      /*!< 0x00000080 */

+#define HRTIM_TIMDIER_CPT1IE          HRTIM_TIMDIER_CPT1IE_Msk                 /*!< Slave capture 1 interrupt enable */

+#define HRTIM_TIMDIER_CPT2IE_Pos      (8U)

+#define HRTIM_TIMDIER_CPT2IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos)      /*!< 0x00000100 */

+#define HRTIM_TIMDIER_CPT2IE          HRTIM_TIMDIER_CPT2IE_Msk                 /*!< Slave capture 2 interrupt enable */

+#define HRTIM_TIMDIER_SET1IE_Pos      (9U)

+#define HRTIM_TIMDIER_SET1IE_Msk      (0x1UL << HRTIM_TIMDIER_SET1IE_Pos)      /*!< 0x00000200 */

+#define HRTIM_TIMDIER_SET1IE          HRTIM_TIMDIER_SET1IE_Msk                 /*!< Slave output 1 set interrupt enable */

+#define HRTIM_TIMDIER_RST1IE_Pos      (10U)

+#define HRTIM_TIMDIER_RST1IE_Msk      (0x1UL << HRTIM_TIMDIER_RST1IE_Pos)      /*!< 0x00000400 */

+#define HRTIM_TIMDIER_RST1IE          HRTIM_TIMDIER_RST1IE_Msk                 /*!< Slave output 1 reset interrupt enable */

+#define HRTIM_TIMDIER_SET2IE_Pos      (11U)

+#define HRTIM_TIMDIER_SET2IE_Msk      (0x1UL << HRTIM_TIMDIER_SET2IE_Pos)      /*!< 0x00000800 */

+#define HRTIM_TIMDIER_SET2IE          HRTIM_TIMDIER_SET2IE_Msk                 /*!< Slave output 2 set interrupt enable */

+#define HRTIM_TIMDIER_RST2IE_Pos      (12U)

+#define HRTIM_TIMDIER_RST2IE_Msk      (0x1UL << HRTIM_TIMDIER_RST2IE_Pos)      /*!< 0x00001000 */

+#define HRTIM_TIMDIER_RST2IE          HRTIM_TIMDIER_RST2IE_Msk                 /*!< Slave output 2 reset interrupt enable */

+#define HRTIM_TIMDIER_RSTIE_Pos       (13U)

+#define HRTIM_TIMDIER_RSTIE_Msk       (0x1UL << HRTIM_TIMDIER_RSTIE_Pos)       /*!< 0x00002000 */

+#define HRTIM_TIMDIER_RSTIE           HRTIM_TIMDIER_RSTIE_Msk                  /*!< Slave reset interrupt enable */

+#define HRTIM_TIMDIER_DLYPRTIE_Pos    (14U)

+#define HRTIM_TIMDIER_DLYPRTIE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos)    /*!< 0x00004000 */

+#define HRTIM_TIMDIER_DLYPRTIE        HRTIM_TIMDIER_DLYPRTIE_Msk               /*!< Slave delay protection interrupt enable */

+

+#define HRTIM_TIMDIER_CMP1DE_Pos      (16U)

+#define HRTIM_TIMDIER_CMP1DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos)      /*!< 0x00010000 */

+#define HRTIM_TIMDIER_CMP1DE          HRTIM_TIMDIER_CMP1DE_Msk                 /*!< Slave compare 1 request enable */

+#define HRTIM_TIMDIER_CMP2DE_Pos      (17U)

+#define HRTIM_TIMDIER_CMP2DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos)      /*!< 0x00020000 */

+#define HRTIM_TIMDIER_CMP2DE          HRTIM_TIMDIER_CMP2DE_Msk                 /*!< Slave compare 2 request enable */

+#define HRTIM_TIMDIER_CMP3DE_Pos      (18U)

+#define HRTIM_TIMDIER_CMP3DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos)      /*!< 0x00040000 */

+#define HRTIM_TIMDIER_CMP3DE          HRTIM_TIMDIER_CMP3DE_Msk                 /*!< Slave compare 3 request enable */

+#define HRTIM_TIMDIER_CMP4DE_Pos      (19U)

+#define HRTIM_TIMDIER_CMP4DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos)      /*!< 0x00080000 */

+#define HRTIM_TIMDIER_CMP4DE          HRTIM_TIMDIER_CMP4DE_Msk                 /*!< Slave compare 4 request enable */

+#define HRTIM_TIMDIER_REPDE_Pos       (20U)

+#define HRTIM_TIMDIER_REPDE_Msk       (0x1UL << HRTIM_TIMDIER_REPDE_Pos)       /*!< 0x00100000 */

+#define HRTIM_TIMDIER_REPDE           HRTIM_TIMDIER_REPDE_Msk                  /*!< Slave repetition request enable */

+#define HRTIM_TIMDIER_UPDDE_Pos       (22U)

+#define HRTIM_TIMDIER_UPDDE_Msk       (0x1UL << HRTIM_TIMDIER_UPDDE_Pos)       /*!< 0x00400000 */

+#define HRTIM_TIMDIER_UPDDE           HRTIM_TIMDIER_UPDDE_Msk                  /*!< Slave update request enable */

+#define HRTIM_TIMDIER_CPT1DE_Pos      (23U)

+#define HRTIM_TIMDIER_CPT1DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos)      /*!< 0x00800000 */

+#define HRTIM_TIMDIER_CPT1DE          HRTIM_TIMDIER_CPT1DE_Msk                 /*!< Slave capture 1 request enable */

+#define HRTIM_TIMDIER_CPT2DE_Pos      (24U)

+#define HRTIM_TIMDIER_CPT2DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos)      /*!< 0x01000000 */

+#define HRTIM_TIMDIER_CPT2DE          HRTIM_TIMDIER_CPT2DE_Msk                 /*!< Slave capture 2 request enable */

+#define HRTIM_TIMDIER_SET1DE_Pos      (25U)

+#define HRTIM_TIMDIER_SET1DE_Msk      (0x1UL << HRTIM_TIMDIER_SET1DE_Pos)      /*!< 0x02000000 */

+#define HRTIM_TIMDIER_SET1DE          HRTIM_TIMDIER_SET1DE_Msk                 /*!< Slave output 1 set request enable */

+#define HRTIM_TIMDIER_RST1DE_Pos      (26U)

+#define HRTIM_TIMDIER_RST1DE_Msk      (0x1UL << HRTIM_TIMDIER_RST1DE_Pos)      /*!< 0x04000000 */

+#define HRTIM_TIMDIER_RST1DE          HRTIM_TIMDIER_RST1DE_Msk                 /*!< Slave output 1 reset request enable */

+#define HRTIM_TIMDIER_SET2DE_Pos      (27U)

+#define HRTIM_TIMDIER_SET2DE_Msk      (0x1UL << HRTIM_TIMDIER_SET2DE_Pos)      /*!< 0x08000000 */

+#define HRTIM_TIMDIER_SET2DE          HRTIM_TIMDIER_SET2DE_Msk                 /*!< Slave output 2 set request enable */

+#define HRTIM_TIMDIER_RST2DE_Pos      (28U)

+#define HRTIM_TIMDIER_RST2DE_Msk      (0x1UL << HRTIM_TIMDIER_RST2DE_Pos)      /*!< 0x10000000 */

+#define HRTIM_TIMDIER_RST2DE          HRTIM_TIMDIER_RST2DE_Msk                 /*!< Slave output 2 reset request enable */

+#define HRTIM_TIMDIER_RSTDE_Pos       (29U)

+#define HRTIM_TIMDIER_RSTDE_Msk       (0x1UL << HRTIM_TIMDIER_RSTDE_Pos)       /*!< 0x20000000 */

+#define HRTIM_TIMDIER_RSTDE           HRTIM_TIMDIER_RSTDE_Msk                  /*!< Slave reset request enable */

+#define HRTIM_TIMDIER_DLYPRTDE_Pos    (30U)

+#define HRTIM_TIMDIER_DLYPRTDE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos)    /*!< 0x40000000 */

+#define HRTIM_TIMDIER_DLYPRTDE        HRTIM_TIMDIER_DLYPRTDE_Msk               /*!< Slavedelay protection request enable */

+

+/******************  Bit definition for HRTIM_CNTR register  ****************/

+#define HRTIM_CNTR_CNTR_Pos           (0U)

+#define HRTIM_CNTR_CNTR_Msk           (0xFFFFUL << HRTIM_CNTR_CNTR_Pos)        /*!< 0x0000FFFF */

+#define HRTIM_CNTR_CNTR               HRTIM_CNTR_CNTR_Msk                      /*!< Counter Value */

+

+/*******************  Bit definition for HRTIM_PER register  *****************/

+#define HRTIM_PER_PER_Pos             (0U)

+#define HRTIM_PER_PER_Msk             (0xFFFFUL << HRTIM_PER_PER_Pos)          /*!< 0x0000FFFF */

+#define HRTIM_PER_PER                 HRTIM_PER_PER_Msk                        /*!< Period Value */

+

+/*******************  Bit definition for HRTIM_REP register  *****************/

+#define HRTIM_REP_REP_Pos             (0U)

+#define HRTIM_REP_REP_Msk             (0xFFUL << HRTIM_REP_REP_Pos)            /*!< 0x000000FF */

+#define HRTIM_REP_REP                 HRTIM_REP_REP_Msk                        /*!< Repetition Value */

+

+/*******************  Bit definition for HRTIM_CMP1R register  *****************/

+#define HRTIM_CMP1R_CMP1R_Pos         (0U)

+#define HRTIM_CMP1R_CMP1R_Msk         (0xFFFFUL << HRTIM_CMP1R_CMP1R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP1R_CMP1R             HRTIM_CMP1R_CMP1R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP1CR register  *****************/

+#define HRTIM_CMP1CR_CMP1CR_Pos       (0U)

+#define HRTIM_CMP1CR_CMP1CR_Msk       (0xFFFFFFFFUL << HRTIM_CMP1CR_CMP1CR_Pos) /*!< 0xFFFFFFFF */

+#define HRTIM_CMP1CR_CMP1CR           HRTIM_CMP1CR_CMP1CR_Msk                  /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP2R register  *****************/

+#define HRTIM_CMP2R_CMP2R_Pos         (0U)

+#define HRTIM_CMP2R_CMP2R_Msk         (0xFFFFUL << HRTIM_CMP2R_CMP2R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP2R_CMP2R             HRTIM_CMP2R_CMP2R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP3R register  *****************/

+#define HRTIM_CMP3R_CMP3R_Pos         (0U)

+#define HRTIM_CMP3R_CMP3R_Msk         (0xFFFFUL << HRTIM_CMP3R_CMP3R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP3R_CMP3R             HRTIM_CMP3R_CMP3R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP4R register  *****************/

+#define HRTIM_CMP4R_CMP4R_Pos         (0U)

+#define HRTIM_CMP4R_CMP4R_Msk         (0xFFFFUL << HRTIM_CMP4R_CMP4R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP4R_CMP4R             HRTIM_CMP4R_CMP4R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CPT1R register  ****************/

+#define HRTIM_CPT1R_CPT1R_Pos         (0U)

+#define HRTIM_CPT1R_CPT1R_Msk         (0xFFFFUL << HRTIM_CPT1R_CPT1R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CPT1R_CPT1R             HRTIM_CPT1R_CPT1R_Msk                    /*!< Capture Value */

+

+/*******************  Bit definition for HRTIM_CPT2R register  ****************/

+#define HRTIM_CPT2R_CPT2R_Pos         (0U)

+#define HRTIM_CPT2R_CPT2R_Msk         (0xFFFFUL << HRTIM_CPT2R_CPT2R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CPT2R_CPT2R             HRTIM_CPT2R_CPT2R_Msk                    /*!< Capture Value */

+

+/******************** Bit definition for Slave Deadtime register **************/

+#define HRTIM_DTR_DTR_Pos             (0U)

+#define HRTIM_DTR_DTR_Msk             (0x1FFUL << HRTIM_DTR_DTR_Pos)           /*!< 0x000001FF */

+#define HRTIM_DTR_DTR                 HRTIM_DTR_DTR_Msk                        /*!< Dead time rising value */

+#define HRTIM_DTR_DTR_0               (0x001UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000001 */

+#define HRTIM_DTR_DTR_1               (0x002UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000002 */

+#define HRTIM_DTR_DTR_2               (0x004UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000004 */

+#define HRTIM_DTR_DTR_3               (0x008UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000008 */

+#define HRTIM_DTR_DTR_4               (0x010UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000010 */

+#define HRTIM_DTR_DTR_5               (0x020UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000020 */

+#define HRTIM_DTR_DTR_6               (0x040UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000040 */

+#define HRTIM_DTR_DTR_7               (0x080UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000080 */

+#define HRTIM_DTR_DTR_8               (0x100UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000100 */

+#define HRTIM_DTR_SDTR_Pos            (9U)

+#define HRTIM_DTR_SDTR_Msk            (0x1UL << HRTIM_DTR_SDTR_Pos)            /*!< 0x00000200 */

+#define HRTIM_DTR_SDTR                HRTIM_DTR_SDTR_Msk                       /*!< Sign dead time rising value */

+#define HRTIM_DTR_DTPRSC_Pos          (10U)

+#define HRTIM_DTR_DTPRSC_Msk          (0x7UL << HRTIM_DTR_DTPRSC_Pos)          /*!< 0x00001C00 */

+#define HRTIM_DTR_DTPRSC              HRTIM_DTR_DTPRSC_Msk                     /*!< Dead time prescaler */

+#define HRTIM_DTR_DTPRSC_0            (0x1UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000400 */

+#define HRTIM_DTR_DTPRSC_1            (0x2UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000800 */

+#define HRTIM_DTR_DTPRSC_2            (0x4UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00001000 */

+#define HRTIM_DTR_DTRSLK_Pos          (14U)

+#define HRTIM_DTR_DTRSLK_Msk          (0x1UL << HRTIM_DTR_DTRSLK_Pos)          /*!< 0x00004000 */

+#define HRTIM_DTR_DTRSLK              HRTIM_DTR_DTRSLK_Msk                     /*!< Dead time rising sign lock */

+#define HRTIM_DTR_DTRLK_Pos           (15U)

+#define HRTIM_DTR_DTRLK_Msk           (0x1UL << HRTIM_DTR_DTRLK_Pos)           /*!< 0x00008000 */

+#define HRTIM_DTR_DTRLK               HRTIM_DTR_DTRLK_Msk                      /*!< Dead time rising lock */

+#define HRTIM_DTR_DTF_Pos             (16U)

+#define HRTIM_DTR_DTF_Msk             (0x1FFUL << HRTIM_DTR_DTF_Pos)           /*!< 0x01FF0000 */

+#define HRTIM_DTR_DTF                 HRTIM_DTR_DTF_Msk                        /*!< Dead time falling value */

+#define HRTIM_DTR_DTF_0               (0x001UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00010000 */

+#define HRTIM_DTR_DTF_1               (0x002UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00020000 */

+#define HRTIM_DTR_DTF_2               (0x004UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00040000 */

+#define HRTIM_DTR_DTF_3               (0x008UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00080000 */

+#define HRTIM_DTR_DTF_4               (0x010UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00100000 */

+#define HRTIM_DTR_DTF_5               (0x020UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00200000 */

+#define HRTIM_DTR_DTF_6               (0x040UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00400000 */

+#define HRTIM_DTR_DTF_7               (0x080UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00800000 */

+#define HRTIM_DTR_DTF_8               (0x100UL << HRTIM_DTR_DTF_Pos)            /*!< 0x01000000 */

+#define HRTIM_DTR_SDTF_Pos            (25U)

+#define HRTIM_DTR_SDTF_Msk            (0x1UL << HRTIM_DTR_SDTF_Pos)            /*!< 0x02000000 */

+#define HRTIM_DTR_SDTF                HRTIM_DTR_SDTF_Msk                       /*!< Sign dead time falling value */

+#define HRTIM_DTR_DTFSLK_Pos          (30U)

+#define HRTIM_DTR_DTFSLK_Msk          (0x1UL << HRTIM_DTR_DTFSLK_Pos)          /*!< 0x40000000 */

+#define HRTIM_DTR_DTFSLK              HRTIM_DTR_DTFSLK_Msk                     /*!< Dead time falling sign lock */

+#define HRTIM_DTR_DTFLK_Pos           (31U)

+#define HRTIM_DTR_DTFLK_Msk           (0x1UL << HRTIM_DTR_DTFLK_Pos)           /*!< 0x80000000 */

+#define HRTIM_DTR_DTFLK               HRTIM_DTR_DTFLK_Msk                      /*!< Dead time falling lock */

+

+/**** Bit definition for Slave Output 1 set register **************************/

+#define HRTIM_SET1R_SST_Pos           (0U)

+#define HRTIM_SET1R_SST_Msk           (0x1UL << HRTIM_SET1R_SST_Pos)           /*!< 0x00000001 */

+#define HRTIM_SET1R_SST               HRTIM_SET1R_SST_Msk                      /*!< software set trigger */

+#define HRTIM_SET1R_RESYNC_Pos        (1U)

+#define HRTIM_SET1R_RESYNC_Msk        (0x1UL << HRTIM_SET1R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_SET1R_RESYNC            HRTIM_SET1R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_SET1R_PER_Pos           (2U)

+#define HRTIM_SET1R_PER_Msk           (0x1UL << HRTIM_SET1R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_SET1R_PER               HRTIM_SET1R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_SET1R_CMP1_Pos          (3U)

+#define HRTIM_SET1R_CMP1_Msk          (0x1UL << HRTIM_SET1R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_SET1R_CMP1              HRTIM_SET1R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_SET1R_CMP2_Pos          (4U)

+#define HRTIM_SET1R_CMP2_Msk          (0x1UL << HRTIM_SET1R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_SET1R_CMP2              HRTIM_SET1R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_SET1R_CMP3_Pos          (5U)

+#define HRTIM_SET1R_CMP3_Msk          (0x1UL << HRTIM_SET1R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_SET1R_CMP3              HRTIM_SET1R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_SET1R_CMP4_Pos          (6U)

+#define HRTIM_SET1R_CMP4_Msk          (0x1UL << HRTIM_SET1R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_SET1R_CMP4              HRTIM_SET1R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_SET1R_MSTPER_Pos        (7U)

+#define HRTIM_SET1R_MSTPER_Msk        (0x1UL << HRTIM_SET1R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_SET1R_MSTPER            HRTIM_SET1R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_SET1R_MSTCMP1_Pos       (8U)

+#define HRTIM_SET1R_MSTCMP1_Msk       (0x1UL << HRTIM_SET1R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_SET1R_MSTCMP1           HRTIM_SET1R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_SET1R_MSTCMP2_Pos       (9U)

+#define HRTIM_SET1R_MSTCMP2_Msk       (0x1UL << HRTIM_SET1R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_SET1R_MSTCMP2           HRTIM_SET1R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_SET1R_MSTCMP3_Pos       (10U)

+#define HRTIM_SET1R_MSTCMP3_Msk       (0x1UL << HRTIM_SET1R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_SET1R_MSTCMP3           HRTIM_SET1R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_SET1R_MSTCMP4_Pos       (11U)

+#define HRTIM_SET1R_MSTCMP4_Msk       (0x1UL << HRTIM_SET1R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_SET1R_MSTCMP4           HRTIM_SET1R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_SET1R_TIMEVNT1_Pos      (12U)

+#define HRTIM_SET1R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_SET1R_TIMEVNT1          HRTIM_SET1R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_SET1R_TIMEVNT2_Pos      (13U)

+#define HRTIM_SET1R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_SET1R_TIMEVNT2          HRTIM_SET1R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_SET1R_TIMEVNT3_Pos      (14U)

+#define HRTIM_SET1R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_SET1R_TIMEVNT3          HRTIM_SET1R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_SET1R_TIMEVNT4_Pos      (15U)

+#define HRTIM_SET1R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_SET1R_TIMEVNT4          HRTIM_SET1R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_SET1R_TIMEVNT5_Pos      (16U)

+#define HRTIM_SET1R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_SET1R_TIMEVNT5          HRTIM_SET1R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_SET1R_TIMEVNT6_Pos      (17U)

+#define HRTIM_SET1R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_SET1R_TIMEVNT6          HRTIM_SET1R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_SET1R_TIMEVNT7_Pos      (18U)

+#define HRTIM_SET1R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_SET1R_TIMEVNT7          HRTIM_SET1R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_SET1R_TIMEVNT8_Pos      (19U)

+#define HRTIM_SET1R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_SET1R_TIMEVNT8          HRTIM_SET1R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_SET1R_TIMEVNT9_Pos      (20U)

+#define HRTIM_SET1R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_SET1R_TIMEVNT9          HRTIM_SET1R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_SET1R_EXTVNT1_Pos       (21U)

+#define HRTIM_SET1R_EXTVNT1_Msk       (0x1UL << HRTIM_SET1R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_SET1R_EXTVNT1           HRTIM_SET1R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_SET1R_EXTVNT2_Pos       (22U)

+#define HRTIM_SET1R_EXTVNT2_Msk       (0x1UL << HRTIM_SET1R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_SET1R_EXTVNT2           HRTIM_SET1R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_SET1R_EXTVNT3_Pos       (23U)

+#define HRTIM_SET1R_EXTVNT3_Msk       (0x1UL << HRTIM_SET1R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_SET1R_EXTVNT3           HRTIM_SET1R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_SET1R_EXTVNT4_Pos       (24U)

+#define HRTIM_SET1R_EXTVNT4_Msk       (0x1UL << HRTIM_SET1R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_SET1R_EXTVNT4           HRTIM_SET1R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_SET1R_EXTVNT5_Pos       (25U)

+#define HRTIM_SET1R_EXTVNT5_Msk       (0x1UL << HRTIM_SET1R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_SET1R_EXTVNT5           HRTIM_SET1R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_SET1R_EXTVNT6_Pos       (26U)

+#define HRTIM_SET1R_EXTVNT6_Msk       (0x1UL << HRTIM_SET1R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_SET1R_EXTVNT6           HRTIM_SET1R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_SET1R_EXTVNT7_Pos       (27U)

+#define HRTIM_SET1R_EXTVNT7_Msk       (0x1UL << HRTIM_SET1R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_SET1R_EXTVNT7           HRTIM_SET1R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_SET1R_EXTVNT8_Pos       (28U)

+#define HRTIM_SET1R_EXTVNT8_Msk       (0x1UL << HRTIM_SET1R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_SET1R_EXTVNT8           HRTIM_SET1R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_SET1R_EXTVNT9_Pos       (29U)

+#define HRTIM_SET1R_EXTVNT9_Msk       (0x1UL << HRTIM_SET1R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_SET1R_EXTVNT9           HRTIM_SET1R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_SET1R_EXTVNT10_Pos      (30U)

+#define HRTIM_SET1R_EXTVNT10_Msk      (0x1UL << HRTIM_SET1R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_SET1R_EXTVNT10          HRTIM_SET1R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_SET1R_UPDATE_Pos        (31U)

+#define HRTIM_SET1R_UPDATE_Msk        (0x1UL << HRTIM_SET1R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_SET1R_UPDATE            HRTIM_SET1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+/**** Bit definition for Slave Output 1 reset register ************************/

+#define HRTIM_RST1R_SRT_Pos           (0U)

+#define HRTIM_RST1R_SRT_Msk           (0x1UL << HRTIM_RST1R_SRT_Pos)           /*!< 0x00000001 */

+#define HRTIM_RST1R_SRT               HRTIM_RST1R_SRT_Msk                      /*!< software reset trigger */

+#define HRTIM_RST1R_RESYNC_Pos        (1U)

+#define HRTIM_RST1R_RESYNC_Msk        (0x1UL << HRTIM_RST1R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_RST1R_RESYNC            HRTIM_RST1R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_RST1R_PER_Pos           (2U)

+#define HRTIM_RST1R_PER_Msk           (0x1UL << HRTIM_RST1R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_RST1R_PER               HRTIM_RST1R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_RST1R_CMP1_Pos          (3U)

+#define HRTIM_RST1R_CMP1_Msk          (0x1UL << HRTIM_RST1R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_RST1R_CMP1              HRTIM_RST1R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_RST1R_CMP2_Pos          (4U)

+#define HRTIM_RST1R_CMP2_Msk          (0x1UL << HRTIM_RST1R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_RST1R_CMP2              HRTIM_RST1R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_RST1R_CMP3_Pos          (5U)

+#define HRTIM_RST1R_CMP3_Msk          (0x1UL << HRTIM_RST1R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_RST1R_CMP3              HRTIM_RST1R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_RST1R_CMP4_Pos          (6U)

+#define HRTIM_RST1R_CMP4_Msk          (0x1UL << HRTIM_RST1R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_RST1R_CMP4              HRTIM_RST1R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_RST1R_MSTPER_Pos        (7U)

+#define HRTIM_RST1R_MSTPER_Msk        (0x1UL << HRTIM_RST1R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_RST1R_MSTPER            HRTIM_RST1R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_RST1R_MSTCMP1_Pos       (8U)

+#define HRTIM_RST1R_MSTCMP1_Msk       (0x1UL << HRTIM_RST1R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_RST1R_MSTCMP1           HRTIM_RST1R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_RST1R_MSTCMP2_Pos       (9U)

+#define HRTIM_RST1R_MSTCMP2_Msk       (0x1UL << HRTIM_RST1R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_RST1R_MSTCMP2           HRTIM_RST1R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_RST1R_MSTCMP3_Pos       (10U)

+#define HRTIM_RST1R_MSTCMP3_Msk       (0x1UL << HRTIM_RST1R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_RST1R_MSTCMP3           HRTIM_RST1R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_RST1R_MSTCMP4_Pos       (11U)

+#define HRTIM_RST1R_MSTCMP4_Msk       (0x1UL << HRTIM_RST1R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_RST1R_MSTCMP4           HRTIM_RST1R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_RST1R_TIMEVNT1_Pos      (12U)

+#define HRTIM_RST1R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_RST1R_TIMEVNT1          HRTIM_RST1R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_RST1R_TIMEVNT2_Pos      (13U)

+#define HRTIM_RST1R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_RST1R_TIMEVNT2          HRTIM_RST1R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_RST1R_TIMEVNT3_Pos      (14U)

+#define HRTIM_RST1R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_RST1R_TIMEVNT3          HRTIM_RST1R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_RST1R_TIMEVNT4_Pos      (15U)

+#define HRTIM_RST1R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_RST1R_TIMEVNT4          HRTIM_RST1R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_RST1R_TIMEVNT5_Pos      (16U)

+#define HRTIM_RST1R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_RST1R_TIMEVNT5          HRTIM_RST1R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_RST1R_TIMEVNT6_Pos      (17U)

+#define HRTIM_RST1R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_RST1R_TIMEVNT6          HRTIM_RST1R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_RST1R_TIMEVNT7_Pos      (18U)

+#define HRTIM_RST1R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_RST1R_TIMEVNT7          HRTIM_RST1R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_RST1R_TIMEVNT8_Pos      (19U)

+#define HRTIM_RST1R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_RST1R_TIMEVNT8          HRTIM_RST1R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_RST1R_TIMEVNT9_Pos      (20U)

+#define HRTIM_RST1R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_RST1R_TIMEVNT9          HRTIM_RST1R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_RST1R_EXTVNT1_Pos       (21U)

+#define HRTIM_RST1R_EXTVNT1_Msk       (0x1UL << HRTIM_RST1R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_RST1R_EXTVNT1           HRTIM_RST1R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_RST1R_EXTVNT2_Pos       (22U)

+#define HRTIM_RST1R_EXTVNT2_Msk       (0x1UL << HRTIM_RST1R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_RST1R_EXTVNT2           HRTIM_RST1R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_RST1R_EXTVNT3_Pos       (23U)

+#define HRTIM_RST1R_EXTVNT3_Msk       (0x1UL << HRTIM_RST1R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_RST1R_EXTVNT3           HRTIM_RST1R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_RST1R_EXTVNT4_Pos       (24U)

+#define HRTIM_RST1R_EXTVNT4_Msk       (0x1UL << HRTIM_RST1R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_RST1R_EXTVNT4           HRTIM_RST1R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_RST1R_EXTVNT5_Pos       (25U)

+#define HRTIM_RST1R_EXTVNT5_Msk       (0x1UL << HRTIM_RST1R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_RST1R_EXTVNT5           HRTIM_RST1R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_RST1R_EXTVNT6_Pos       (26U)

+#define HRTIM_RST1R_EXTVNT6_Msk       (0x1UL << HRTIM_RST1R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_RST1R_EXTVNT6           HRTIM_RST1R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_RST1R_EXTVNT7_Pos       (27U)

+#define HRTIM_RST1R_EXTVNT7_Msk       (0x1UL << HRTIM_RST1R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_RST1R_EXTVNT7           HRTIM_RST1R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_RST1R_EXTVNT8_Pos       (28U)

+#define HRTIM_RST1R_EXTVNT8_Msk       (0x1UL << HRTIM_RST1R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_RST1R_EXTVNT8           HRTIM_RST1R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_RST1R_EXTVNT9_Pos       (29U)

+#define HRTIM_RST1R_EXTVNT9_Msk       (0x1UL << HRTIM_RST1R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_RST1R_EXTVNT9           HRTIM_RST1R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_RST1R_EXTVNT10_Pos      (30U)

+#define HRTIM_RST1R_EXTVNT10_Msk      (0x1UL << HRTIM_RST1R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_RST1R_EXTVNT10          HRTIM_RST1R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_RST1R_UPDATE_Pos        (31U)

+#define HRTIM_RST1R_UPDATE_Msk        (0x1UL << HRTIM_RST1R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_RST1R_UPDATE            HRTIM_RST1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+

+/**** Bit definition for Slave Output 2 set register **************************/

+#define HRTIM_SET2R_SST_Pos           (0U)

+#define HRTIM_SET2R_SST_Msk           (0x1UL << HRTIM_SET2R_SST_Pos)           /*!< 0x00000001 */

+#define HRTIM_SET2R_SST               HRTIM_SET2R_SST_Msk                      /*!< software set trigger */

+#define HRTIM_SET2R_RESYNC_Pos        (1U)

+#define HRTIM_SET2R_RESYNC_Msk        (0x1UL << HRTIM_SET2R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_SET2R_RESYNC            HRTIM_SET2R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_SET2R_PER_Pos           (2U)

+#define HRTIM_SET2R_PER_Msk           (0x1UL << HRTIM_SET2R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_SET2R_PER               HRTIM_SET2R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_SET2R_CMP1_Pos          (3U)

+#define HRTIM_SET2R_CMP1_Msk          (0x1UL << HRTIM_SET2R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_SET2R_CMP1              HRTIM_SET2R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_SET2R_CMP2_Pos          (4U)

+#define HRTIM_SET2R_CMP2_Msk          (0x1UL << HRTIM_SET2R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_SET2R_CMP2              HRTIM_SET2R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_SET2R_CMP3_Pos          (5U)

+#define HRTIM_SET2R_CMP3_Msk          (0x1UL << HRTIM_SET2R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_SET2R_CMP3              HRTIM_SET2R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_SET2R_CMP4_Pos          (6U)

+#define HRTIM_SET2R_CMP4_Msk          (0x1UL << HRTIM_SET2R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_SET2R_CMP4              HRTIM_SET2R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_SET2R_MSTPER_Pos        (7U)

+#define HRTIM_SET2R_MSTPER_Msk        (0x1UL << HRTIM_SET2R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_SET2R_MSTPER            HRTIM_SET2R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_SET2R_MSTCMP1_Pos       (8U)

+#define HRTIM_SET2R_MSTCMP1_Msk       (0x1UL << HRTIM_SET2R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_SET2R_MSTCMP1           HRTIM_SET2R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_SET2R_MSTCMP2_Pos       (9U)

+#define HRTIM_SET2R_MSTCMP2_Msk       (0x1UL << HRTIM_SET2R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_SET2R_MSTCMP2           HRTIM_SET2R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_SET2R_MSTCMP3_Pos       (10U)

+#define HRTIM_SET2R_MSTCMP3_Msk       (0x1UL << HRTIM_SET2R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_SET2R_MSTCMP3           HRTIM_SET2R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_SET2R_MSTCMP4_Pos       (11U)

+#define HRTIM_SET2R_MSTCMP4_Msk       (0x1UL << HRTIM_SET2R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_SET2R_MSTCMP4           HRTIM_SET2R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_SET2R_TIMEVNT1_Pos      (12U)

+#define HRTIM_SET2R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_SET2R_TIMEVNT1          HRTIM_SET2R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_SET2R_TIMEVNT2_Pos      (13U)

+#define HRTIM_SET2R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_SET2R_TIMEVNT2          HRTIM_SET2R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_SET2R_TIMEVNT3_Pos      (14U)

+#define HRTIM_SET2R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_SET2R_TIMEVNT3          HRTIM_SET2R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_SET2R_TIMEVNT4_Pos      (15U)

+#define HRTIM_SET2R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_SET2R_TIMEVNT4          HRTIM_SET2R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_SET2R_TIMEVNT5_Pos      (16U)

+#define HRTIM_SET2R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_SET2R_TIMEVNT5          HRTIM_SET2R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_SET2R_TIMEVNT6_Pos      (17U)

+#define HRTIM_SET2R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_SET2R_TIMEVNT6          HRTIM_SET2R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_SET2R_TIMEVNT7_Pos      (18U)

+#define HRTIM_SET2R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_SET2R_TIMEVNT7          HRTIM_SET2R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_SET2R_TIMEVNT8_Pos      (19U)

+#define HRTIM_SET2R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_SET2R_TIMEVNT8          HRTIM_SET2R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_SET2R_TIMEVNT9_Pos      (20U)

+#define HRTIM_SET2R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_SET2R_TIMEVNT9          HRTIM_SET2R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_SET2R_EXTVNT1_Pos       (21U)

+#define HRTIM_SET2R_EXTVNT1_Msk       (0x1UL << HRTIM_SET2R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_SET2R_EXTVNT1           HRTIM_SET2R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_SET2R_EXTVNT2_Pos       (22U)

+#define HRTIM_SET2R_EXTVNT2_Msk       (0x1UL << HRTIM_SET2R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_SET2R_EXTVNT2           HRTIM_SET2R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_SET2R_EXTVNT3_Pos       (23U)

+#define HRTIM_SET2R_EXTVNT3_Msk       (0x1UL << HRTIM_SET2R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_SET2R_EXTVNT3           HRTIM_SET2R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_SET2R_EXTVNT4_Pos       (24U)

+#define HRTIM_SET2R_EXTVNT4_Msk       (0x1UL << HRTIM_SET2R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_SET2R_EXTVNT4           HRTIM_SET2R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_SET2R_EXTVNT5_Pos       (25U)

+#define HRTIM_SET2R_EXTVNT5_Msk       (0x1UL << HRTIM_SET2R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_SET2R_EXTVNT5           HRTIM_SET2R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_SET2R_EXTVNT6_Pos       (26U)

+#define HRTIM_SET2R_EXTVNT6_Msk       (0x1UL << HRTIM_SET2R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_SET2R_EXTVNT6           HRTIM_SET2R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_SET2R_EXTVNT7_Pos       (27U)

+#define HRTIM_SET2R_EXTVNT7_Msk       (0x1UL << HRTIM_SET2R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_SET2R_EXTVNT7           HRTIM_SET2R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_SET2R_EXTVNT8_Pos       (28U)

+#define HRTIM_SET2R_EXTVNT8_Msk       (0x1UL << HRTIM_SET2R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_SET2R_EXTVNT8           HRTIM_SET2R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_SET2R_EXTVNT9_Pos       (29U)

+#define HRTIM_SET2R_EXTVNT9_Msk       (0x1UL << HRTIM_SET2R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_SET2R_EXTVNT9           HRTIM_SET2R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_SET2R_EXTVNT10_Pos      (30U)

+#define HRTIM_SET2R_EXTVNT10_Msk      (0x1UL << HRTIM_SET2R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_SET2R_EXTVNT10          HRTIM_SET2R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_SET2R_UPDATE_Pos        (31U)

+#define HRTIM_SET2R_UPDATE_Msk        (0x1UL << HRTIM_SET2R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_SET2R_UPDATE            HRTIM_SET2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+/**** Bit definition for Slave Output 2 reset register ************************/

+#define HRTIM_RST2R_SRT_Pos           (0U)

+#define HRTIM_RST2R_SRT_Msk           (0x1UL << HRTIM_RST2R_SRT_Pos)           /*!< 0x00000001 */

+#define HRTIM_RST2R_SRT               HRTIM_RST2R_SRT_Msk                      /*!< software reset trigger */

+#define HRTIM_RST2R_RESYNC_Pos        (1U)

+#define HRTIM_RST2R_RESYNC_Msk        (0x1UL << HRTIM_RST2R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_RST2R_RESYNC            HRTIM_RST2R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_RST2R_PER_Pos           (2U)

+#define HRTIM_RST2R_PER_Msk           (0x1UL << HRTIM_RST2R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_RST2R_PER               HRTIM_RST2R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_RST2R_CMP1_Pos          (3U)

+#define HRTIM_RST2R_CMP1_Msk          (0x1UL << HRTIM_RST2R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_RST2R_CMP1              HRTIM_RST2R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_RST2R_CMP2_Pos          (4U)

+#define HRTIM_RST2R_CMP2_Msk          (0x1UL << HRTIM_RST2R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_RST2R_CMP2              HRTIM_RST2R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_RST2R_CMP3_Pos          (5U)

+#define HRTIM_RST2R_CMP3_Msk          (0x1UL << HRTIM_RST2R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_RST2R_CMP3              HRTIM_RST2R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_RST2R_CMP4_Pos          (6U)

+#define HRTIM_RST2R_CMP4_Msk          (0x1UL << HRTIM_RST2R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_RST2R_CMP4              HRTIM_RST2R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_RST2R_MSTPER_Pos        (7U)

+#define HRTIM_RST2R_MSTPER_Msk        (0x1UL << HRTIM_RST2R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_RST2R_MSTPER            HRTIM_RST2R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_RST2R_MSTCMP1_Pos       (8U)

+#define HRTIM_RST2R_MSTCMP1_Msk       (0x1UL << HRTIM_RST2R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_RST2R_MSTCMP1           HRTIM_RST2R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_RST2R_MSTCMP2_Pos       (9U)

+#define HRTIM_RST2R_MSTCMP2_Msk       (0x1UL << HRTIM_RST2R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_RST2R_MSTCMP2           HRTIM_RST2R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_RST2R_MSTCMP3_Pos       (10U)

+#define HRTIM_RST2R_MSTCMP3_Msk       (0x1UL << HRTIM_RST2R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_RST2R_MSTCMP3           HRTIM_RST2R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_RST2R_MSTCMP4_Pos       (11U)

+#define HRTIM_RST2R_MSTCMP4_Msk       (0x1UL << HRTIM_RST2R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_RST2R_MSTCMP4           HRTIM_RST2R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_RST2R_TIMEVNT1_Pos      (12U)

+#define HRTIM_RST2R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_RST2R_TIMEVNT1          HRTIM_RST2R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_RST2R_TIMEVNT2_Pos      (13U)

+#define HRTIM_RST2R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_RST2R_TIMEVNT2          HRTIM_RST2R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_RST2R_TIMEVNT3_Pos      (14U)

+#define HRTIM_RST2R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_RST2R_TIMEVNT3          HRTIM_RST2R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_RST2R_TIMEVNT4_Pos      (15U)

+#define HRTIM_RST2R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_RST2R_TIMEVNT4          HRTIM_RST2R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_RST2R_TIMEVNT5_Pos      (16U)

+#define HRTIM_RST2R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_RST2R_TIMEVNT5          HRTIM_RST2R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_RST2R_TIMEVNT6_Pos      (17U)

+#define HRTIM_RST2R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_RST2R_TIMEVNT6          HRTIM_RST2R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_RST2R_TIMEVNT7_Pos      (18U)

+#define HRTIM_RST2R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_RST2R_TIMEVNT7          HRTIM_RST2R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_RST2R_TIMEVNT8_Pos      (19U)

+#define HRTIM_RST2R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_RST2R_TIMEVNT8          HRTIM_RST2R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_RST2R_TIMEVNT9_Pos      (20U)

+#define HRTIM_RST2R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_RST2R_TIMEVNT9          HRTIM_RST2R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_RST2R_EXTVNT1_Pos       (21U)

+#define HRTIM_RST2R_EXTVNT1_Msk       (0x1UL << HRTIM_RST2R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_RST2R_EXTVNT1           HRTIM_RST2R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_RST2R_EXTVNT2_Pos       (22U)

+#define HRTIM_RST2R_EXTVNT2_Msk       (0x1UL << HRTIM_RST2R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_RST2R_EXTVNT2           HRTIM_RST2R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_RST2R_EXTVNT3_Pos       (23U)

+#define HRTIM_RST2R_EXTVNT3_Msk       (0x1UL << HRTIM_RST2R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_RST2R_EXTVNT3           HRTIM_RST2R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_RST2R_EXTVNT4_Pos       (24U)

+#define HRTIM_RST2R_EXTVNT4_Msk       (0x1UL << HRTIM_RST2R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_RST2R_EXTVNT4           HRTIM_RST2R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_RST2R_EXTVNT5_Pos       (25U)

+#define HRTIM_RST2R_EXTVNT5_Msk       (0x1UL << HRTIM_RST2R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_RST2R_EXTVNT5           HRTIM_RST2R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_RST2R_EXTVNT6_Pos       (26U)

+#define HRTIM_RST2R_EXTVNT6_Msk       (0x1UL << HRTIM_RST2R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_RST2R_EXTVNT6           HRTIM_RST2R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_RST2R_EXTVNT7_Pos       (27U)

+#define HRTIM_RST2R_EXTVNT7_Msk       (0x1UL << HRTIM_RST2R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_RST2R_EXTVNT7           HRTIM_RST2R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_RST2R_EXTVNT8_Pos       (28U)

+#define HRTIM_RST2R_EXTVNT8_Msk       (0x1UL << HRTIM_RST2R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_RST2R_EXTVNT8           HRTIM_RST2R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_RST2R_EXTVNT9_Pos       (29U)

+#define HRTIM_RST2R_EXTVNT9_Msk       (0x1UL << HRTIM_RST2R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_RST2R_EXTVNT9           HRTIM_RST2R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_RST2R_EXTVNT10_Pos      (30U)

+#define HRTIM_RST2R_EXTVNT10_Msk      (0x1UL << HRTIM_RST2R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_RST2R_EXTVNT10          HRTIM_RST2R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_RST2R_UPDATE_Pos        (31U)

+#define HRTIM_RST2R_UPDATE_Msk        (0x1UL << HRTIM_RST2R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_RST2R_UPDATE            HRTIM_RST2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+/**** Bit definition for Slave external event filtering  register 1 ***********/

+#define HRTIM_EEFR1_EE1LTCH_Pos       (0U)

+#define HRTIM_EEFR1_EE1LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos)       /*!< 0x00000001 */

+#define HRTIM_EEFR1_EE1LTCH           HRTIM_EEFR1_EE1LTCH_Msk                  /*!< External Event 1 latch */

+#define HRTIM_EEFR1_EE1FLTR_Pos       (1U)

+#define HRTIM_EEFR1_EE1FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos)       /*!< 0x0000001E */

+#define HRTIM_EEFR1_EE1FLTR           HRTIM_EEFR1_EE1FLTR_Msk                  /*!< External Event 1 filter mask */

+#define HRTIM_EEFR1_EE1FLTR_0         (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000002 */

+#define HRTIM_EEFR1_EE1FLTR_1         (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000004 */

+#define HRTIM_EEFR1_EE1FLTR_2         (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000008 */

+#define HRTIM_EEFR1_EE1FLTR_3         (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000010 */

+

+#define HRTIM_EEFR1_EE2LTCH_Pos       (6U)

+#define HRTIM_EEFR1_EE2LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos)       /*!< 0x00000040 */

+#define HRTIM_EEFR1_EE2LTCH           HRTIM_EEFR1_EE2LTCH_Msk                  /*!< External Event 2 latch */

+#define HRTIM_EEFR1_EE2FLTR_Pos       (7U)

+#define HRTIM_EEFR1_EE2FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos)       /*!< 0x00000780 */

+#define HRTIM_EEFR1_EE2FLTR           HRTIM_EEFR1_EE2FLTR_Msk                  /*!< External Event 2 filter mask */

+#define HRTIM_EEFR1_EE2FLTR_0         (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000080 */

+#define HRTIM_EEFR1_EE2FLTR_1         (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000100 */

+#define HRTIM_EEFR1_EE2FLTR_2         (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000200 */

+#define HRTIM_EEFR1_EE2FLTR_3         (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000400 */

+

+#define HRTIM_EEFR1_EE3LTCH_Pos       (12U)

+#define HRTIM_EEFR1_EE3LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos)       /*!< 0x00001000 */

+#define HRTIM_EEFR1_EE3LTCH           HRTIM_EEFR1_EE3LTCH_Msk                  /*!< External Event 3 latch */

+#define HRTIM_EEFR1_EE3FLTR_Pos       (13U)

+#define HRTIM_EEFR1_EE3FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos)       /*!< 0x0001E000 */

+#define HRTIM_EEFR1_EE3FLTR           HRTIM_EEFR1_EE3FLTR_Msk                  /*!< External Event 3 filter mask */

+#define HRTIM_EEFR1_EE3FLTR_0         (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00002000 */

+#define HRTIM_EEFR1_EE3FLTR_1         (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00004000 */

+#define HRTIM_EEFR1_EE3FLTR_2         (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00008000 */

+#define HRTIM_EEFR1_EE3FLTR_3         (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00010000 */

+

+#define HRTIM_EEFR1_EE4LTCH_Pos       (18U)

+#define HRTIM_EEFR1_EE4LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos)       /*!< 0x00040000 */

+#define HRTIM_EEFR1_EE4LTCH           HRTIM_EEFR1_EE4LTCH_Msk                  /*!< External Event 4 latch */

+#define HRTIM_EEFR1_EE4FLTR_Pos       (19U)

+#define HRTIM_EEFR1_EE4FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos)       /*!< 0x00780000 */

+#define HRTIM_EEFR1_EE4FLTR           HRTIM_EEFR1_EE4FLTR_Msk                  /*!< External Event 4 filter mask */

+#define HRTIM_EEFR1_EE4FLTR_0         (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00080000 */

+#define HRTIM_EEFR1_EE4FLTR_1         (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00100000 */

+#define HRTIM_EEFR1_EE4FLTR_2         (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00200000 */

+#define HRTIM_EEFR1_EE4FLTR_3         (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00400000 */

+

+#define HRTIM_EEFR1_EE5LTCH_Pos       (24U)

+#define HRTIM_EEFR1_EE5LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos)       /*!< 0x01000000 */

+#define HRTIM_EEFR1_EE5LTCH           HRTIM_EEFR1_EE5LTCH_Msk                  /*!< External Event 5 latch */

+#define HRTIM_EEFR1_EE5FLTR_Pos       (25U)

+#define HRTIM_EEFR1_EE5FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos)       /*!< 0x1E000000 */

+#define HRTIM_EEFR1_EE5FLTR           HRTIM_EEFR1_EE5FLTR_Msk                  /*!< External Event 5 filter mask */

+#define HRTIM_EEFR1_EE5FLTR_0         (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x02000000 */

+#define HRTIM_EEFR1_EE5FLTR_1         (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x04000000 */

+#define HRTIM_EEFR1_EE5FLTR_2         (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x08000000 */

+#define HRTIM_EEFR1_EE5FLTR_3         (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x10000000 */

+

+/**** Bit definition for Slave external event filtering  register 2 ***********/

+#define HRTIM_EEFR2_EE6LTCH_Pos       (0U)

+#define HRTIM_EEFR2_EE6LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos)       /*!< 0x00000001 */

+#define HRTIM_EEFR2_EE6LTCH           HRTIM_EEFR2_EE6LTCH_Msk                  /*!< External Event 6 latch */

+#define HRTIM_EEFR2_EE6FLTR_Pos       (1U)

+#define HRTIM_EEFR2_EE6FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos)       /*!< 0x0000001E */

+#define HRTIM_EEFR2_EE6FLTR           HRTIM_EEFR2_EE6FLTR_Msk                  /*!< External Event 6 filter mask */

+#define HRTIM_EEFR2_EE6FLTR_0         (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000002 */

+#define HRTIM_EEFR2_EE6FLTR_1         (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000004 */

+#define HRTIM_EEFR2_EE6FLTR_2         (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000008 */

+#define HRTIM_EEFR2_EE6FLTR_3         (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000010 */

+

+#define HRTIM_EEFR2_EE7LTCH_Pos       (6U)

+#define HRTIM_EEFR2_EE7LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos)       /*!< 0x00000040 */

+#define HRTIM_EEFR2_EE7LTCH           HRTIM_EEFR2_EE7LTCH_Msk                  /*!< External Event 7 latch */

+#define HRTIM_EEFR2_EE7FLTR_Pos       (7U)

+#define HRTIM_EEFR2_EE7FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos)       /*!< 0x00000780 */

+#define HRTIM_EEFR2_EE7FLTR           HRTIM_EEFR2_EE7FLTR_Msk                  /*!< External Event 7 filter mask */

+#define HRTIM_EEFR2_EE7FLTR_0         (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000080 */

+#define HRTIM_EEFR2_EE7FLTR_1         (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000100 */

+#define HRTIM_EEFR2_EE7FLTR_2         (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000200 */

+#define HRTIM_EEFR2_EE7FLTR_3         (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000400 */

+

+#define HRTIM_EEFR2_EE8LTCH_Pos       (12U)

+#define HRTIM_EEFR2_EE8LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos)       /*!< 0x00001000 */

+#define HRTIM_EEFR2_EE8LTCH           HRTIM_EEFR2_EE8LTCH_Msk                  /*!< External Event 8 latch */

+#define HRTIM_EEFR2_EE8FLTR_Pos       (13U)

+#define HRTIM_EEFR2_EE8FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos)       /*!< 0x0001E000 */

+#define HRTIM_EEFR2_EE8FLTR           HRTIM_EEFR2_EE8FLTR_Msk                  /*!< External Event 8 filter mask */

+#define HRTIM_EEFR2_EE8FLTR_0         (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00002000 */

+#define HRTIM_EEFR2_EE8FLTR_1         (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00004000 */

+#define HRTIM_EEFR2_EE8FLTR_2         (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00008000 */

+#define HRTIM_EEFR2_EE8FLTR_3         (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00010000 */

+

+#define HRTIM_EEFR2_EE9LTCH_Pos       (18U)

+#define HRTIM_EEFR2_EE9LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos)       /*!< 0x00040000 */

+#define HRTIM_EEFR2_EE9LTCH           HRTIM_EEFR2_EE9LTCH_Msk                  /*!< External Event 9 latch */

+#define HRTIM_EEFR2_EE9FLTR_Pos       (19U)

+#define HRTIM_EEFR2_EE9FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos)       /*!< 0x00780000 */

+#define HRTIM_EEFR2_EE9FLTR           HRTIM_EEFR2_EE9FLTR_Msk                  /*!< External Event 9 filter mask */

+#define HRTIM_EEFR2_EE9FLTR_0         (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00080000 */

+#define HRTIM_EEFR2_EE9FLTR_1         (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00100000 */

+#define HRTIM_EEFR2_EE9FLTR_2         (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00200000 */

+#define HRTIM_EEFR2_EE9FLTR_3         (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00400000 */

+

+#define HRTIM_EEFR2_EE10LTCH_Pos      (24U)

+#define HRTIM_EEFR2_EE10LTCH_Msk      (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos)      /*!< 0x01000000 */

+#define HRTIM_EEFR2_EE10LTCH          HRTIM_EEFR2_EE10LTCH_Msk                 /*!< External Event 10 latch */

+#define HRTIM_EEFR2_EE10FLTR_Pos      (25U)

+#define HRTIM_EEFR2_EE10FLTR_Msk      (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos)      /*!< 0x1E000000 */

+#define HRTIM_EEFR2_EE10FLTR          HRTIM_EEFR2_EE10FLTR_Msk                 /*!< External Event 10 filter mask */

+#define HRTIM_EEFR2_EE10FLTR_0        (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x02000000 */

+#define HRTIM_EEFR2_EE10FLTR_1        (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x04000000 */

+#define HRTIM_EEFR2_EE10FLTR_2        (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x08000000 */

+#define HRTIM_EEFR2_EE10FLTR_3        (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x10000000 */

+

+/**** Bit definition for Slave Timer reset register ***************************/

+#define HRTIM_RSTR_UPDATE_Pos         (1U)

+#define HRTIM_RSTR_UPDATE_Msk         (0x1UL << HRTIM_RSTR_UPDATE_Pos)         /*!< 0x00000002 */

+#define HRTIM_RSTR_UPDATE             HRTIM_RSTR_UPDATE_Msk                    /*!< Timer update */

+#define HRTIM_RSTR_CMP2_Pos           (2U)

+#define HRTIM_RSTR_CMP2_Msk           (0x1UL << HRTIM_RSTR_CMP2_Pos)           /*!< 0x00000004 */

+#define HRTIM_RSTR_CMP2               HRTIM_RSTR_CMP2_Msk                      /*!< Timer compare2 */

+#define HRTIM_RSTR_CMP4_Pos           (3U)

+#define HRTIM_RSTR_CMP4_Msk           (0x1UL << HRTIM_RSTR_CMP4_Pos)           /*!< 0x00000008 */

+#define HRTIM_RSTR_CMP4               HRTIM_RSTR_CMP4_Msk                      /*!< Timer compare4 */

+

+#define HRTIM_RSTR_MSTPER_Pos         (4U)

+#define HRTIM_RSTR_MSTPER_Msk         (0x1UL << HRTIM_RSTR_MSTPER_Pos)         /*!< 0x00000010 */

+#define HRTIM_RSTR_MSTPER             HRTIM_RSTR_MSTPER_Msk                    /*!< Master period */

+#define HRTIM_RSTR_MSTCMP1_Pos        (5U)

+#define HRTIM_RSTR_MSTCMP1_Msk        (0x1UL << HRTIM_RSTR_MSTCMP1_Pos)        /*!< 0x00000020 */

+#define HRTIM_RSTR_MSTCMP1            HRTIM_RSTR_MSTCMP1_Msk                   /*!< Master compare1 */

+#define HRTIM_RSTR_MSTCMP2_Pos        (6U)

+#define HRTIM_RSTR_MSTCMP2_Msk        (0x1UL << HRTIM_RSTR_MSTCMP2_Pos)        /*!< 0x00000040 */

+#define HRTIM_RSTR_MSTCMP2            HRTIM_RSTR_MSTCMP2_Msk                   /*!< Master compare2 */

+#define HRTIM_RSTR_MSTCMP3_Pos        (7U)

+#define HRTIM_RSTR_MSTCMP3_Msk        (0x1UL << HRTIM_RSTR_MSTCMP3_Pos)        /*!< 0x00000080 */

+#define HRTIM_RSTR_MSTCMP3            HRTIM_RSTR_MSTCMP3_Msk                   /*!< Master compare3 */

+#define HRTIM_RSTR_MSTCMP4_Pos        (8U)

+#define HRTIM_RSTR_MSTCMP4_Msk        (0x1UL << HRTIM_RSTR_MSTCMP4_Pos)        /*!< 0x00000100 */

+#define HRTIM_RSTR_MSTCMP4            HRTIM_RSTR_MSTCMP4_Msk                   /*!< Master compare4 */

+

+#define HRTIM_RSTR_EXTEVNT1_Pos       (9U)

+#define HRTIM_RSTR_EXTEVNT1_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos)       /*!< 0x00000200 */

+#define HRTIM_RSTR_EXTEVNT1           HRTIM_RSTR_EXTEVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_RSTR_EXTEVNT2_Pos       (10U)

+#define HRTIM_RSTR_EXTEVNT2_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos)       /*!< 0x00000400 */

+#define HRTIM_RSTR_EXTEVNT2           HRTIM_RSTR_EXTEVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_RSTR_EXTEVNT3_Pos       (11U)

+#define HRTIM_RSTR_EXTEVNT3_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos)       /*!< 0x00000800 */

+#define HRTIM_RSTR_EXTEVNT3           HRTIM_RSTR_EXTEVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_RSTR_EXTEVNT4_Pos       (12U)

+#define HRTIM_RSTR_EXTEVNT4_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos)       /*!< 0x00001000 */

+#define HRTIM_RSTR_EXTEVNT4           HRTIM_RSTR_EXTEVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_RSTR_EXTEVNT5_Pos       (13U)

+#define HRTIM_RSTR_EXTEVNT5_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos)       /*!< 0x00002000 */

+#define HRTIM_RSTR_EXTEVNT5           HRTIM_RSTR_EXTEVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_RSTR_EXTEVNT6_Pos       (14U)

+#define HRTIM_RSTR_EXTEVNT6_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos)       /*!< 0x00004000 */

+#define HRTIM_RSTR_EXTEVNT6           HRTIM_RSTR_EXTEVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_RSTR_EXTEVNT7_Pos       (15U)

+#define HRTIM_RSTR_EXTEVNT7_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos)       /*!< 0x00008000 */

+#define HRTIM_RSTR_EXTEVNT7           HRTIM_RSTR_EXTEVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_RSTR_EXTEVNT8_Pos       (16U)

+#define HRTIM_RSTR_EXTEVNT8_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos)       /*!< 0x00010000 */

+#define HRTIM_RSTR_EXTEVNT8           HRTIM_RSTR_EXTEVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_RSTR_EXTEVNT9_Pos       (17U)

+#define HRTIM_RSTR_EXTEVNT9_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos)       /*!< 0x00020000 */

+#define HRTIM_RSTR_EXTEVNT9           HRTIM_RSTR_EXTEVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_RSTR_EXTEVNT10_Pos      (18U)

+#define HRTIM_RSTR_EXTEVNT10_Msk      (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos)      /*!< 0x00040000 */

+#define HRTIM_RSTR_EXTEVNT10          HRTIM_RSTR_EXTEVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_RSTR_TIMBCMP1_Pos       (19U)

+#define HRTIM_RSTR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos)       /*!< 0x00080000 */

+#define HRTIM_RSTR_TIMBCMP1           HRTIM_RSTR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */

+#define HRTIM_RSTR_TIMBCMP2_Pos       (20U)

+#define HRTIM_RSTR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos)       /*!< 0x00100000 */

+#define HRTIM_RSTR_TIMBCMP2           HRTIM_RSTR_TIMBCMP2_Msk                  /*!< Timer B compare 2 */

+#define HRTIM_RSTR_TIMBCMP4_Pos       (21U)

+#define HRTIM_RSTR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos)       /*!< 0x00200000 */

+#define HRTIM_RSTR_TIMBCMP4           HRTIM_RSTR_TIMBCMP4_Msk                  /*!< Timer B compare 4 */

+

+#define HRTIM_RSTR_TIMCCMP1_Pos       (22U)

+#define HRTIM_RSTR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos)       /*!< 0x00400000 */

+#define HRTIM_RSTR_TIMCCMP1           HRTIM_RSTR_TIMCCMP1_Msk                  /*!< Timer C compare 1 */

+#define HRTIM_RSTR_TIMCCMP2_Pos       (23U)

+#define HRTIM_RSTR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos)       /*!< 0x00800000 */

+#define HRTIM_RSTR_TIMCCMP2           HRTIM_RSTR_TIMCCMP2_Msk                  /*!< Timer C compare 2 */

+#define HRTIM_RSTR_TIMCCMP4_Pos       (24U)

+#define HRTIM_RSTR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos)       /*!< 0x01000000 */

+#define HRTIM_RSTR_TIMCCMP4           HRTIM_RSTR_TIMCCMP4_Msk                  /*!< Timer C compare 4 */

+

+#define HRTIM_RSTR_TIMDCMP1_Pos       (25U)

+#define HRTIM_RSTR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos)       /*!< 0x02000000 */

+#define HRTIM_RSTR_TIMDCMP1           HRTIM_RSTR_TIMDCMP1_Msk                  /*!< Timer D compare 1 */

+#define HRTIM_RSTR_TIMDCMP2_Pos       (26U)

+#define HRTIM_RSTR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos)       /*!< 0x04000000 */

+#define HRTIM_RSTR_TIMDCMP2           HRTIM_RSTR_TIMDCMP2_Msk                  /*!< Timer D compare 2 */

+#define HRTIM_RSTR_TIMDCMP4_Pos       (27U)

+#define HRTIM_RSTR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos)       /*!< 0x08000000 */

+#define HRTIM_RSTR_TIMDCMP4           HRTIM_RSTR_TIMDCMP4_Msk                  /*!< Timer D compare 4 */

+

+#define HRTIM_RSTR_TIMECMP1_Pos       (28U)

+#define HRTIM_RSTR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTR_TIMECMP1_Pos)       /*!< 0x10000000 */

+#define HRTIM_RSTR_TIMECMP1           HRTIM_RSTR_TIMECMP1_Msk                  /*!< Timer E compare 1 */

+#define HRTIM_RSTR_TIMECMP2_Pos       (29U)

+#define HRTIM_RSTR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTR_TIMECMP2_Pos)       /*!< 0x20000000 */

+#define HRTIM_RSTR_TIMECMP2           HRTIM_RSTR_TIMECMP2_Msk                  /*!< Timer E compare 2 */

+#define HRTIM_RSTR_TIMECMP4_Pos       (30U)

+#define HRTIM_RSTR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTR_TIMECMP4_Pos)       /*!< 0x40000000 */

+#define HRTIM_RSTR_TIMECMP4           HRTIM_RSTR_TIMECMP4_Msk                  /*!< Timer E compare 4 */

+

+/**** Bit definition for Slave Timer Chopper register *************************/

+#define HRTIM_CHPR_CARFRQ_Pos         (0U)

+#define HRTIM_CHPR_CARFRQ_Msk         (0xFUL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x0000000F */

+#define HRTIM_CHPR_CARFRQ             HRTIM_CHPR_CARFRQ_Msk                    /*!< Timer carrier frequency value */

+#define HRTIM_CHPR_CARFRQ_0           (0x1UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000001 */

+#define HRTIM_CHPR_CARFRQ_1           (0x2UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000002 */

+#define HRTIM_CHPR_CARFRQ_2           (0x4UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000004 */

+#define HRTIM_CHPR_CARFRQ_3           (0x8UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000008 */

+

+#define HRTIM_CHPR_CARDTY_Pos         (4U)

+#define HRTIM_CHPR_CARDTY_Msk         (0x7UL << HRTIM_CHPR_CARDTY_Pos)         /*!< 0x00000070 */

+#define HRTIM_CHPR_CARDTY             HRTIM_CHPR_CARDTY_Msk                    /*!< Timer chopper duty cycle value */

+#define HRTIM_CHPR_CARDTY_0           (0x1UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000010 */

+#define HRTIM_CHPR_CARDTY_1           (0x2UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000020 */

+#define HRTIM_CHPR_CARDTY_2           (0x4UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000040 */

+

+#define HRTIM_CHPR_STRPW_Pos          (7U)

+#define HRTIM_CHPR_STRPW_Msk          (0xFUL << HRTIM_CHPR_STRPW_Pos)          /*!< 0x00000780 */

+#define HRTIM_CHPR_STRPW              HRTIM_CHPR_STRPW_Msk                     /*!< Timer start pulse width value */

+#define HRTIM_CHPR_STRPW_0            (0x1UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000080 */

+#define HRTIM_CHPR_STRPW_1            (0x2UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000100 */

+#define HRTIM_CHPR_STRPW_2            (0x4UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000200 */

+#define HRTIM_CHPR_STRPW_3            (0x8UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000400 */

+

+/**** Bit definition for Slave Timer Capture 1 control register ***************/

+#define HRTIM_CPT1CR_SWCPT_Pos        (0U)

+#define HRTIM_CPT1CR_SWCPT_Msk        (0x1UL << HRTIM_CPT1CR_SWCPT_Pos)        /*!< 0x00000001 */

+#define HRTIM_CPT1CR_SWCPT            HRTIM_CPT1CR_SWCPT_Msk                   /*!< Software capture */

+#define HRTIM_CPT1CR_UPDCPT_Pos       (1U)

+#define HRTIM_CPT1CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos)       /*!< 0x00000002 */

+#define HRTIM_CPT1CR_UPDCPT           HRTIM_CPT1CR_UPDCPT_Msk                  /*!< Update capture */

+#define HRTIM_CPT1CR_EXEV1CPT_Pos     (2U)

+#define HRTIM_CPT1CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos)     /*!< 0x00000004 */

+#define HRTIM_CPT1CR_EXEV1CPT         HRTIM_CPT1CR_EXEV1CPT_Msk                /*!< External event 1 capture */

+#define HRTIM_CPT1CR_EXEV2CPT_Pos     (3U)

+#define HRTIM_CPT1CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos)     /*!< 0x00000008 */

+#define HRTIM_CPT1CR_EXEV2CPT         HRTIM_CPT1CR_EXEV2CPT_Msk                /*!< External event 2 capture */

+#define HRTIM_CPT1CR_EXEV3CPT_Pos     (4U)

+#define HRTIM_CPT1CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos)     /*!< 0x00000010 */

+#define HRTIM_CPT1CR_EXEV3CPT         HRTIM_CPT1CR_EXEV3CPT_Msk                /*!< External event 3 capture */

+#define HRTIM_CPT1CR_EXEV4CPT_Pos     (5U)

+#define HRTIM_CPT1CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos)     /*!< 0x00000020 */

+#define HRTIM_CPT1CR_EXEV4CPT         HRTIM_CPT1CR_EXEV4CPT_Msk                /*!< External event 4 capture */

+#define HRTIM_CPT1CR_EXEV5CPT_Pos     (6U)

+#define HRTIM_CPT1CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos)     /*!< 0x00000040 */

+#define HRTIM_CPT1CR_EXEV5CPT         HRTIM_CPT1CR_EXEV5CPT_Msk                /*!< External event 5 capture */

+#define HRTIM_CPT1CR_EXEV6CPT_Pos     (7U)

+#define HRTIM_CPT1CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos)     /*!< 0x00000080 */

+#define HRTIM_CPT1CR_EXEV6CPT         HRTIM_CPT1CR_EXEV6CPT_Msk                /*!< External event 6 capture */

+#define HRTIM_CPT1CR_EXEV7CPT_Pos     (8U)

+#define HRTIM_CPT1CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos)     /*!< 0x00000100 */

+#define HRTIM_CPT1CR_EXEV7CPT         HRTIM_CPT1CR_EXEV7CPT_Msk                /*!< External event 7 capture */

+#define HRTIM_CPT1CR_EXEV8CPT_Pos     (9U)

+#define HRTIM_CPT1CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos)     /*!< 0x00000200 */

+#define HRTIM_CPT1CR_EXEV8CPT         HRTIM_CPT1CR_EXEV8CPT_Msk                /*!< External event 8 capture */

+#define HRTIM_CPT1CR_EXEV9CPT_Pos     (10U)

+#define HRTIM_CPT1CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos)     /*!< 0x00000400 */

+#define HRTIM_CPT1CR_EXEV9CPT         HRTIM_CPT1CR_EXEV9CPT_Msk                /*!< External event 9 capture */

+#define HRTIM_CPT1CR_EXEV10CPT_Pos    (11U)

+#define HRTIM_CPT1CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos)    /*!< 0x00000800 */

+#define HRTIM_CPT1CR_EXEV10CPT        HRTIM_CPT1CR_EXEV10CPT_Msk               /*!< External event 10 capture */

+

+#define HRTIM_CPT1CR_TA1SET_Pos       (12U)

+#define HRTIM_CPT1CR_TA1SET_Msk       (0x1UL << HRTIM_CPT1CR_TA1SET_Pos)       /*!< 0x00001000 */

+#define HRTIM_CPT1CR_TA1SET           HRTIM_CPT1CR_TA1SET_Msk                  /*!< Timer A output 1 set */

+#define HRTIM_CPT1CR_TA1RST_Pos       (13U)

+#define HRTIM_CPT1CR_TA1RST_Msk       (0x1UL << HRTIM_CPT1CR_TA1RST_Pos)       /*!< 0x00002000 */

+#define HRTIM_CPT1CR_TA1RST           HRTIM_CPT1CR_TA1RST_Msk                  /*!< Timer A output 1 reset */

+#define HRTIM_CPT1CR_TIMACMP1_Pos     (14U)

+#define HRTIM_CPT1CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos)     /*!< 0x00004000 */

+#define HRTIM_CPT1CR_TIMACMP1         HRTIM_CPT1CR_TIMACMP1_Msk                /*!< Timer A compare 1 */

+#define HRTIM_CPT1CR_TIMACMP2_Pos     (15U)

+#define HRTIM_CPT1CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos)     /*!< 0x00008000 */

+#define HRTIM_CPT1CR_TIMACMP2         HRTIM_CPT1CR_TIMACMP2_Msk                /*!< Timer A compare 2 */

+

+#define HRTIM_CPT1CR_TB1SET_Pos       (16U)

+#define HRTIM_CPT1CR_TB1SET_Msk       (0x1UL << HRTIM_CPT1CR_TB1SET_Pos)       /*!< 0x00010000 */

+#define HRTIM_CPT1CR_TB1SET           HRTIM_CPT1CR_TB1SET_Msk                  /*!< Timer B output 1 set */

+#define HRTIM_CPT1CR_TB1RST_Pos       (17U)

+#define HRTIM_CPT1CR_TB1RST_Msk       (0x1UL << HRTIM_CPT1CR_TB1RST_Pos)       /*!< 0x00020000 */

+#define HRTIM_CPT1CR_TB1RST           HRTIM_CPT1CR_TB1RST_Msk                  /*!< Timer B output 1 reset */

+#define HRTIM_CPT1CR_TIMBCMP1_Pos     (18U)

+#define HRTIM_CPT1CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos)     /*!< 0x00040000 */

+#define HRTIM_CPT1CR_TIMBCMP1         HRTIM_CPT1CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */

+#define HRTIM_CPT1CR_TIMBCMP2_Pos     (19U)

+#define HRTIM_CPT1CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos)     /*!< 0x00080000 */

+#define HRTIM_CPT1CR_TIMBCMP2         HRTIM_CPT1CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */

+

+#define HRTIM_CPT1CR_TC1SET_Pos       (20U)

+#define HRTIM_CPT1CR_TC1SET_Msk       (0x1UL << HRTIM_CPT1CR_TC1SET_Pos)       /*!< 0x00100000 */

+#define HRTIM_CPT1CR_TC1SET           HRTIM_CPT1CR_TC1SET_Msk                  /*!< Timer C output 1 set */

+#define HRTIM_CPT1CR_TC1RST_Pos       (21U)

+#define HRTIM_CPT1CR_TC1RST_Msk       (0x1UL << HRTIM_CPT1CR_TC1RST_Pos)       /*!< 0x00200000 */

+#define HRTIM_CPT1CR_TC1RST           HRTIM_CPT1CR_TC1RST_Msk                  /*!< Timer C output 1 reset */

+#define HRTIM_CPT1CR_TIMCCMP1_Pos     (22U)

+#define HRTIM_CPT1CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos)     /*!< 0x00400000 */

+#define HRTIM_CPT1CR_TIMCCMP1         HRTIM_CPT1CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */

+#define HRTIM_CPT1CR_TIMCCMP2_Pos     (23U)

+#define HRTIM_CPT1CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos)     /*!< 0x00800000 */

+#define HRTIM_CPT1CR_TIMCCMP2         HRTIM_CPT1CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */

+

+#define HRTIM_CPT1CR_TD1SET_Pos       (24U)

+#define HRTIM_CPT1CR_TD1SET_Msk       (0x1UL << HRTIM_CPT1CR_TD1SET_Pos)       /*!< 0x01000000 */

+#define HRTIM_CPT1CR_TD1SET           HRTIM_CPT1CR_TD1SET_Msk                  /*!< Timer D output 1 set */

+#define HRTIM_CPT1CR_TD1RST_Pos       (25U)

+#define HRTIM_CPT1CR_TD1RST_Msk       (0x1UL << HRTIM_CPT1CR_TD1RST_Pos)       /*!< 0x02000000 */

+#define HRTIM_CPT1CR_TD1RST           HRTIM_CPT1CR_TD1RST_Msk                  /*!< Timer D output 1 reset */

+#define HRTIM_CPT1CR_TIMDCMP1_Pos     (26U)

+#define HRTIM_CPT1CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos)     /*!< 0x04000000 */

+#define HRTIM_CPT1CR_TIMDCMP1         HRTIM_CPT1CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */

+#define HRTIM_CPT1CR_TIMDCMP2_Pos     (27U)

+#define HRTIM_CPT1CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos)     /*!< 0x08000000 */

+#define HRTIM_CPT1CR_TIMDCMP2         HRTIM_CPT1CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */

+

+#define HRTIM_CPT1CR_TE1SET_Pos       (28U)

+#define HRTIM_CPT1CR_TE1SET_Msk       (0x1UL << HRTIM_CPT1CR_TE1SET_Pos)       /*!< 0x10000000 */

+#define HRTIM_CPT1CR_TE1SET           HRTIM_CPT1CR_TE1SET_Msk                  /*!< Timer E output 1 set */

+#define HRTIM_CPT1CR_TE1RST_Pos       (29U)

+#define HRTIM_CPT1CR_TE1RST_Msk       (0x1UL << HRTIM_CPT1CR_TE1RST_Pos)       /*!< 0x20000000 */

+#define HRTIM_CPT1CR_TE1RST           HRTIM_CPT1CR_TE1RST_Msk                  /*!< Timer E output 1 reset */

+#define HRTIM_CPT1CR_TIMECMP1_Pos     (30U)

+#define HRTIM_CPT1CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos)     /*!< 0x40000000 */

+#define HRTIM_CPT1CR_TIMECMP1         HRTIM_CPT1CR_TIMECMP1_Msk                /*!< Timer E compare 1 */

+#define HRTIM_CPT1CR_TIMECMP2_Pos     (31U)

+#define HRTIM_CPT1CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos)     /*!< 0x80000000 */

+#define HRTIM_CPT1CR_TIMECMP2         HRTIM_CPT1CR_TIMECMP2_Msk                /*!< Timer E compare 2 */

+

+/**** Bit definition for Slave Timer Capture 2 control register ***************/

+#define HRTIM_CPT2CR_SWCPT_Pos        (0U)

+#define HRTIM_CPT2CR_SWCPT_Msk        (0x1UL << HRTIM_CPT2CR_SWCPT_Pos)        /*!< 0x00000001 */

+#define HRTIM_CPT2CR_SWCPT            HRTIM_CPT2CR_SWCPT_Msk                   /*!< Software capture */

+#define HRTIM_CPT2CR_UPDCPT_Pos       (1U)

+#define HRTIM_CPT2CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos)       /*!< 0x00000002 */

+#define HRTIM_CPT2CR_UPDCPT           HRTIM_CPT2CR_UPDCPT_Msk                  /*!< Update capture */

+#define HRTIM_CPT2CR_EXEV1CPT_Pos     (2U)

+#define HRTIM_CPT2CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos)     /*!< 0x00000004 */

+#define HRTIM_CPT2CR_EXEV1CPT         HRTIM_CPT2CR_EXEV1CPT_Msk                /*!< External event 1 capture */

+#define HRTIM_CPT2CR_EXEV2CPT_Pos     (3U)

+#define HRTIM_CPT2CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos)     /*!< 0x00000008 */

+#define HRTIM_CPT2CR_EXEV2CPT         HRTIM_CPT2CR_EXEV2CPT_Msk                /*!< External event 2 capture */

+#define HRTIM_CPT2CR_EXEV3CPT_Pos     (4U)

+#define HRTIM_CPT2CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos)     /*!< 0x00000010 */

+#define HRTIM_CPT2CR_EXEV3CPT         HRTIM_CPT2CR_EXEV3CPT_Msk                /*!< External event 3 capture */

+#define HRTIM_CPT2CR_EXEV4CPT_Pos     (5U)

+#define HRTIM_CPT2CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos)     /*!< 0x00000020 */

+#define HRTIM_CPT2CR_EXEV4CPT         HRTIM_CPT2CR_EXEV4CPT_Msk                /*!< External event 4 capture */

+#define HRTIM_CPT2CR_EXEV5CPT_Pos     (6U)

+#define HRTIM_CPT2CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos)     /*!< 0x00000040 */

+#define HRTIM_CPT2CR_EXEV5CPT         HRTIM_CPT2CR_EXEV5CPT_Msk                /*!< External event 5 capture */

+#define HRTIM_CPT2CR_EXEV6CPT_Pos     (7U)

+#define HRTIM_CPT2CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos)     /*!< 0x00000080 */

+#define HRTIM_CPT2CR_EXEV6CPT         HRTIM_CPT2CR_EXEV6CPT_Msk                /*!< External event 6 capture */

+#define HRTIM_CPT2CR_EXEV7CPT_Pos     (8U)

+#define HRTIM_CPT2CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos)     /*!< 0x00000100 */

+#define HRTIM_CPT2CR_EXEV7CPT         HRTIM_CPT2CR_EXEV7CPT_Msk                /*!< External event 7 capture */

+#define HRTIM_CPT2CR_EXEV8CPT_Pos     (9U)

+#define HRTIM_CPT2CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos)     /*!< 0x00000200 */

+#define HRTIM_CPT2CR_EXEV8CPT         HRTIM_CPT2CR_EXEV8CPT_Msk                /*!< External event 8 capture */

+#define HRTIM_CPT2CR_EXEV9CPT_Pos     (10U)

+#define HRTIM_CPT2CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos)     /*!< 0x00000400 */

+#define HRTIM_CPT2CR_EXEV9CPT         HRTIM_CPT2CR_EXEV9CPT_Msk                /*!< External event 9 capture */

+#define HRTIM_CPT2CR_EXEV10CPT_Pos    (11U)

+#define HRTIM_CPT2CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos)    /*!< 0x00000800 */

+#define HRTIM_CPT2CR_EXEV10CPT        HRTIM_CPT2CR_EXEV10CPT_Msk               /*!< External event 10 capture */

+

+#define HRTIM_CPT2CR_TA1SET_Pos       (12U)

+#define HRTIM_CPT2CR_TA1SET_Msk       (0x1UL << HRTIM_CPT2CR_TA1SET_Pos)       /*!< 0x00001000 */

+#define HRTIM_CPT2CR_TA1SET           HRTIM_CPT2CR_TA1SET_Msk                  /*!< Timer A output 1 set */

+#define HRTIM_CPT2CR_TA1RST_Pos       (13U)

+#define HRTIM_CPT2CR_TA1RST_Msk       (0x1UL << HRTIM_CPT2CR_TA1RST_Pos)       /*!< 0x00002000 */

+#define HRTIM_CPT2CR_TA1RST           HRTIM_CPT2CR_TA1RST_Msk                  /*!< Timer A output 1 reset */

+#define HRTIM_CPT2CR_TIMACMP1_Pos     (14U)

+#define HRTIM_CPT2CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos)     /*!< 0x00004000 */

+#define HRTIM_CPT2CR_TIMACMP1         HRTIM_CPT2CR_TIMACMP1_Msk                /*!< Timer A compare 1 */

+#define HRTIM_CPT2CR_TIMACMP2_Pos     (15U)

+#define HRTIM_CPT2CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos)     /*!< 0x00008000 */

+#define HRTIM_CPT2CR_TIMACMP2         HRTIM_CPT2CR_TIMACMP2_Msk                /*!< Timer A compare 2 */

+

+#define HRTIM_CPT2CR_TB1SET_Pos       (16U)

+#define HRTIM_CPT2CR_TB1SET_Msk       (0x1UL << HRTIM_CPT2CR_TB1SET_Pos)       /*!< 0x00010000 */

+#define HRTIM_CPT2CR_TB1SET           HRTIM_CPT2CR_TB1SET_Msk                  /*!< Timer B output 1 set */

+#define HRTIM_CPT2CR_TB1RST_Pos       (17U)

+#define HRTIM_CPT2CR_TB1RST_Msk       (0x1UL << HRTIM_CPT2CR_TB1RST_Pos)       /*!< 0x00020000 */

+#define HRTIM_CPT2CR_TB1RST           HRTIM_CPT2CR_TB1RST_Msk                  /*!< Timer B output 1 reset */

+#define HRTIM_CPT2CR_TIMBCMP1_Pos     (18U)

+#define HRTIM_CPT2CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos)     /*!< 0x00040000 */

+#define HRTIM_CPT2CR_TIMBCMP1         HRTIM_CPT2CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */

+#define HRTIM_CPT2CR_TIMBCMP2_Pos     (19U)

+#define HRTIM_CPT2CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos)     /*!< 0x00080000 */

+#define HRTIM_CPT2CR_TIMBCMP2         HRTIM_CPT2CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */

+

+#define HRTIM_CPT2CR_TC1SET_Pos       (20U)

+#define HRTIM_CPT2CR_TC1SET_Msk       (0x1UL << HRTIM_CPT2CR_TC1SET_Pos)       /*!< 0x00100000 */

+#define HRTIM_CPT2CR_TC1SET           HRTIM_CPT2CR_TC1SET_Msk                  /*!< Timer C output 1 set */

+#define HRTIM_CPT2CR_TC1RST_Pos       (21U)

+#define HRTIM_CPT2CR_TC1RST_Msk       (0x1UL << HRTIM_CPT2CR_TC1RST_Pos)       /*!< 0x00200000 */

+#define HRTIM_CPT2CR_TC1RST           HRTIM_CPT2CR_TC1RST_Msk                  /*!< Timer C output 1 reset */

+#define HRTIM_CPT2CR_TIMCCMP1_Pos     (22U)

+#define HRTIM_CPT2CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos)     /*!< 0x00400000 */

+#define HRTIM_CPT2CR_TIMCCMP1         HRTIM_CPT2CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */

+#define HRTIM_CPT2CR_TIMCCMP2_Pos     (23U)

+#define HRTIM_CPT2CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos)     /*!< 0x00800000 */

+#define HRTIM_CPT2CR_TIMCCMP2         HRTIM_CPT2CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */

+

+#define HRTIM_CPT2CR_TD1SET_Pos       (24U)

+#define HRTIM_CPT2CR_TD1SET_Msk       (0x1UL << HRTIM_CPT2CR_TD1SET_Pos)       /*!< 0x01000000 */

+#define HRTIM_CPT2CR_TD1SET           HRTIM_CPT2CR_TD1SET_Msk                  /*!< Timer D output 1 set */

+#define HRTIM_CPT2CR_TD1RST_Pos       (25U)

+#define HRTIM_CPT2CR_TD1RST_Msk       (0x1UL << HRTIM_CPT2CR_TD1RST_Pos)       /*!< 0x02000000 */

+#define HRTIM_CPT2CR_TD1RST           HRTIM_CPT2CR_TD1RST_Msk                  /*!< Timer D output 1 reset */

+#define HRTIM_CPT2CR_TIMDCMP1_Pos     (26U)

+#define HRTIM_CPT2CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos)     /*!< 0x04000000 */

+#define HRTIM_CPT2CR_TIMDCMP1         HRTIM_CPT2CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */

+#define HRTIM_CPT2CR_TIMDCMP2_Pos     (27U)

+#define HRTIM_CPT2CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos)     /*!< 0x08000000 */

+#define HRTIM_CPT2CR_TIMDCMP2         HRTIM_CPT2CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */

+

+#define HRTIM_CPT2CR_TE1SET_Pos       (28U)

+#define HRTIM_CPT2CR_TE1SET_Msk       (0x1UL << HRTIM_CPT2CR_TE1SET_Pos)       /*!< 0x10000000 */

+#define HRTIM_CPT2CR_TE1SET           HRTIM_CPT2CR_TE1SET_Msk                  /*!< Timer E output 1 set */

+#define HRTIM_CPT2CR_TE1RST_Pos       (29U)

+#define HRTIM_CPT2CR_TE1RST_Msk       (0x1UL << HRTIM_CPT2CR_TE1RST_Pos)       /*!< 0x20000000 */

+#define HRTIM_CPT2CR_TE1RST           HRTIM_CPT2CR_TE1RST_Msk                  /*!< Timer E output 1 reset */

+#define HRTIM_CPT2CR_TIMECMP1_Pos     (30U)

+#define HRTIM_CPT2CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos)     /*!< 0x40000000 */

+#define HRTIM_CPT2CR_TIMECMP1         HRTIM_CPT2CR_TIMECMP1_Msk                /*!< Timer E compare 1 */

+#define HRTIM_CPT2CR_TIMECMP2_Pos     (31U)

+#define HRTIM_CPT2CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos)     /*!< 0x80000000 */

+#define HRTIM_CPT2CR_TIMECMP2         HRTIM_CPT2CR_TIMECMP2_Msk                /*!< Timer E compare 2 */

+

+/**** Bit definition for Slave Timer Output register **************************/

+#define HRTIM_OUTR_POL1_Pos           (1U)

+#define HRTIM_OUTR_POL1_Msk           (0x1UL << HRTIM_OUTR_POL1_Pos)           /*!< 0x00000002 */

+#define HRTIM_OUTR_POL1               HRTIM_OUTR_POL1_Msk                      /*!< Slave output 1 polarity */

+#define HRTIM_OUTR_IDLM1_Pos          (2U)

+#define HRTIM_OUTR_IDLM1_Msk          (0x1UL << HRTIM_OUTR_IDLM1_Pos)          /*!< 0x00000004 */

+#define HRTIM_OUTR_IDLM1              HRTIM_OUTR_IDLM1_Msk                     /*!< Slave output 1 idle mode */

+#define HRTIM_OUTR_IDLES1_Pos         (3U)

+#define HRTIM_OUTR_IDLES1_Msk         (0x1UL << HRTIM_OUTR_IDLES1_Pos)         /*!< 0x00000008 */

+#define HRTIM_OUTR_IDLES1             HRTIM_OUTR_IDLES1_Msk                    /*!< Slave output 1 idle state */

+#define HRTIM_OUTR_FAULT1_Pos         (4U)

+#define HRTIM_OUTR_FAULT1_Msk         (0x3UL << HRTIM_OUTR_FAULT1_Pos)         /*!< 0x00000030 */

+#define HRTIM_OUTR_FAULT1             HRTIM_OUTR_FAULT1_Msk                    /*!< Slave output 1 fault state */

+#define HRTIM_OUTR_FAULT1_0           (0x1UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000010 */

+#define HRTIM_OUTR_FAULT1_1           (0x2UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000020 */

+#define HRTIM_OUTR_CHP1_Pos           (6U)

+#define HRTIM_OUTR_CHP1_Msk           (0x1UL << HRTIM_OUTR_CHP1_Pos)           /*!< 0x00000040 */

+#define HRTIM_OUTR_CHP1               HRTIM_OUTR_CHP1_Msk                      /*!< Slave output 1 chopper enable */

+#define HRTIM_OUTR_DIDL1_Pos          (7U)

+#define HRTIM_OUTR_DIDL1_Msk          (0x1UL << HRTIM_OUTR_DIDL1_Pos)          /*!< 0x00000080 */

+#define HRTIM_OUTR_DIDL1              HRTIM_OUTR_DIDL1_Msk                     /*!< Slave output 1 dead time idle */

+

+#define HRTIM_OUTR_DTEN_Pos           (8U)

+#define HRTIM_OUTR_DTEN_Msk           (0x1UL << HRTIM_OUTR_DTEN_Pos)           /*!< 0x00000100 */

+#define HRTIM_OUTR_DTEN               HRTIM_OUTR_DTEN_Msk                      /*!< Slave output deadtime enable */

+#define HRTIM_OUTR_DLYPRTEN_Pos       (9U)

+#define HRTIM_OUTR_DLYPRTEN_Msk       (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos)       /*!< 0x00000200 */

+#define HRTIM_OUTR_DLYPRTEN           HRTIM_OUTR_DLYPRTEN_Msk                  /*!< Slave output delay protection enable */

+#define HRTIM_OUTR_DLYPRT_Pos         (10U)

+#define HRTIM_OUTR_DLYPRT_Msk         (0x7UL << HRTIM_OUTR_DLYPRT_Pos)         /*!< 0x00001C00 */

+#define HRTIM_OUTR_DLYPRT             HRTIM_OUTR_DLYPRT_Msk                    /*!< Slave output delay protection */

+#define HRTIM_OUTR_DLYPRT_0           (0x1UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000400 */

+#define HRTIM_OUTR_DLYPRT_1           (0x2UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000800 */

+#define HRTIM_OUTR_DLYPRT_2           (0x4UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00001000 */

+

+#define HRTIM_OUTR_POL2_Pos           (17U)

+#define HRTIM_OUTR_POL2_Msk           (0x1UL << HRTIM_OUTR_POL2_Pos)           /*!< 0x00020000 */

+#define HRTIM_OUTR_POL2               HRTIM_OUTR_POL2_Msk                      /*!< Slave output 2 polarity */

+#define HRTIM_OUTR_IDLM2_Pos          (18U)

+#define HRTIM_OUTR_IDLM2_Msk          (0x1UL << HRTIM_OUTR_IDLM2_Pos)          /*!< 0x00040000 */

+#define HRTIM_OUTR_IDLM2              HRTIM_OUTR_IDLM2_Msk                     /*!< Slave output 2 idle mode */

+#define HRTIM_OUTR_IDLES2_Pos         (19U)

+#define HRTIM_OUTR_IDLES2_Msk         (0x1UL << HRTIM_OUTR_IDLES2_Pos)         /*!< 0x00080000 */

+#define HRTIM_OUTR_IDLES2             HRTIM_OUTR_IDLES2_Msk                    /*!< Slave output 2 idle state */

+#define HRTIM_OUTR_FAULT2_Pos         (20U)

+#define HRTIM_OUTR_FAULT2_Msk         (0x3UL << HRTIM_OUTR_FAULT2_Pos)         /*!< 0x00300000 */

+#define HRTIM_OUTR_FAULT2             HRTIM_OUTR_FAULT2_Msk                    /*!< Slave output 2 fault state */

+#define HRTIM_OUTR_FAULT2_0           (0x1UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00100000 */

+#define HRTIM_OUTR_FAULT2_1           (0x2UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00200000 */

+#define HRTIM_OUTR_CHP2_Pos           (22U)

+#define HRTIM_OUTR_CHP2_Msk           (0x1UL << HRTIM_OUTR_CHP2_Pos)           /*!< 0x00400000 */

+#define HRTIM_OUTR_CHP2               HRTIM_OUTR_CHP2_Msk                      /*!< Slave output 2 chopper enable */

+#define HRTIM_OUTR_DIDL2_Pos          (23U)

+#define HRTIM_OUTR_DIDL2_Msk          (0x1UL << HRTIM_OUTR_DIDL2_Pos)          /*!< 0x00800000 */

+#define HRTIM_OUTR_DIDL2              HRTIM_OUTR_DIDL2_Msk                     /*!< Slave output 2 dead time idle */

+

+/**** Bit definition for Slave Timer Fault register ***************************/

+#define HRTIM_FLTR_FLT1EN_Pos         (0U)

+#define HRTIM_FLTR_FLT1EN_Msk         (0x1UL << HRTIM_FLTR_FLT1EN_Pos)         /*!< 0x00000001 */

+#define HRTIM_FLTR_FLT1EN             HRTIM_FLTR_FLT1EN_Msk                    /*!< Fault 1 enable */

+#define HRTIM_FLTR_FLT2EN_Pos         (1U)

+#define HRTIM_FLTR_FLT2EN_Msk         (0x1UL << HRTIM_FLTR_FLT2EN_Pos)         /*!< 0x00000002 */

+#define HRTIM_FLTR_FLT2EN             HRTIM_FLTR_FLT2EN_Msk                    /*!< Fault 2 enable */

+#define HRTIM_FLTR_FLT3EN_Pos         (2U)

+#define HRTIM_FLTR_FLT3EN_Msk         (0x1UL << HRTIM_FLTR_FLT3EN_Pos)         /*!< 0x00000004 */

+#define HRTIM_FLTR_FLT3EN             HRTIM_FLTR_FLT3EN_Msk                    /*!< Fault 3 enable */

+#define HRTIM_FLTR_FLT4EN_Pos         (3U)

+#define HRTIM_FLTR_FLT4EN_Msk         (0x1UL << HRTIM_FLTR_FLT4EN_Pos)         /*!< 0x00000008 */

+#define HRTIM_FLTR_FLT4EN             HRTIM_FLTR_FLT4EN_Msk                    /*!< Fault 4 enable */

+#define HRTIM_FLTR_FLT5EN_Pos         (4U)

+#define HRTIM_FLTR_FLT5EN_Msk         (0x1UL << HRTIM_FLTR_FLT5EN_Pos)         /*!< 0x00000010 */

+#define HRTIM_FLTR_FLT5EN             HRTIM_FLTR_FLT5EN_Msk                    /*!< Fault 5 enable */

+#define HRTIM_FLTR_FLTLCK_Pos         (31U)

+#define HRTIM_FLTR_FLTLCK_Msk         (0x1UL << HRTIM_FLTR_FLTLCK_Pos)         /*!< 0x80000000 */

+#define HRTIM_FLTR_FLTLCK             HRTIM_FLTR_FLTLCK_Msk                    /*!< Fault sources lock */

+

+/**** Bit definition for Common HRTIM Timer control register 1 ****************/

+#define HRTIM_CR1_MUDIS_Pos           (0U)

+#define HRTIM_CR1_MUDIS_Msk           (0x1UL << HRTIM_CR1_MUDIS_Pos)           /*!< 0x00000001 */

+#define HRTIM_CR1_MUDIS               HRTIM_CR1_MUDIS_Msk                      /*!< Master update disable*/

+#define HRTIM_CR1_TAUDIS_Pos          (1U)

+#define HRTIM_CR1_TAUDIS_Msk          (0x1UL << HRTIM_CR1_TAUDIS_Pos)          /*!< 0x00000002 */

+#define HRTIM_CR1_TAUDIS              HRTIM_CR1_TAUDIS_Msk                     /*!< Timer A update disable*/

+#define HRTIM_CR1_TBUDIS_Pos          (2U)

+#define HRTIM_CR1_TBUDIS_Msk          (0x1UL << HRTIM_CR1_TBUDIS_Pos)          /*!< 0x00000004 */

+#define HRTIM_CR1_TBUDIS              HRTIM_CR1_TBUDIS_Msk                     /*!< Timer B update disable*/

+#define HRTIM_CR1_TCUDIS_Pos          (3U)

+#define HRTIM_CR1_TCUDIS_Msk          (0x1UL << HRTIM_CR1_TCUDIS_Pos)          /*!< 0x00000008 */

+#define HRTIM_CR1_TCUDIS              HRTIM_CR1_TCUDIS_Msk                     /*!< Timer C update disable*/

+#define HRTIM_CR1_TDUDIS_Pos          (4U)

+#define HRTIM_CR1_TDUDIS_Msk          (0x1UL << HRTIM_CR1_TDUDIS_Pos)          /*!< 0x00000010 */

+#define HRTIM_CR1_TDUDIS              HRTIM_CR1_TDUDIS_Msk                     /*!< Timer D update disable*/

+#define HRTIM_CR1_TEUDIS_Pos          (5U)

+#define HRTIM_CR1_TEUDIS_Msk          (0x1UL << HRTIM_CR1_TEUDIS_Pos)          /*!< 0x00000020 */

+#define HRTIM_CR1_TEUDIS              HRTIM_CR1_TEUDIS_Msk                     /*!< Timer E update disable*/

+#define HRTIM_CR1_ADC1USRC_Pos        (16U)

+#define HRTIM_CR1_ADC1USRC_Msk        (0x7UL << HRTIM_CR1_ADC1USRC_Pos)        /*!< 0x00070000 */

+#define HRTIM_CR1_ADC1USRC            HRTIM_CR1_ADC1USRC_Msk                   /*!< ADC Trigger 1 update source */

+#define HRTIM_CR1_ADC1USRC_0          (0x1UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00010000 */

+#define HRTIM_CR1_ADC1USRC_1          (0x2UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00020000 */

+#define HRTIM_CR1_ADC1USRC_2          (0x4UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00040000 */

+#define HRTIM_CR1_ADC2USRC_Pos        (19U)

+#define HRTIM_CR1_ADC2USRC_Msk        (0x7UL << HRTIM_CR1_ADC2USRC_Pos)        /*!< 0x00380000 */

+#define HRTIM_CR1_ADC2USRC            HRTIM_CR1_ADC2USRC_Msk                   /*!< ADC Trigger 2 update source */

+#define HRTIM_CR1_ADC2USRC_0          (0x1UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00080000 */

+#define HRTIM_CR1_ADC2USRC_1          (0x2UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00100000 */

+#define HRTIM_CR1_ADC2USRC_2          (0x4UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00200000 */

+#define HRTIM_CR1_ADC3USRC_Pos        (22U)

+#define HRTIM_CR1_ADC3USRC_Msk        (0x7UL << HRTIM_CR1_ADC3USRC_Pos)        /*!< 0x01C00000 */

+#define HRTIM_CR1_ADC3USRC            HRTIM_CR1_ADC3USRC_Msk                   /*!< ADC Trigger 3 update source */

+#define HRTIM_CR1_ADC3USRC_0          (0x1UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00400000 */

+#define HRTIM_CR1_ADC3USRC_1          (0x2UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00800000 */

+#define HRTIM_CR1_ADC3USRC_2          (0x4UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x01000000 */

+#define HRTIM_CR1_ADC4USRC_Pos        (25U)

+#define HRTIM_CR1_ADC4USRC_Msk        (0x7UL << HRTIM_CR1_ADC4USRC_Pos)        /*!< 0x0E000000 */

+#define HRTIM_CR1_ADC4USRC            HRTIM_CR1_ADC4USRC_Msk                   /*!< ADC Trigger 4 update source */

+#define HRTIM_CR1_ADC4USRC_0          (0x1UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x02000000 */

+#define HRTIM_CR1_ADC4USRC_1          (0x2UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x04000000 */

+#define HRTIM_CR1_ADC4USRC_2          (0x0UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x0800000 */

+

+/**** Bit definition for Common HRTIM Timer control register 2 ****************/

+#define HRTIM_CR2_MSWU_Pos            (0U)

+#define HRTIM_CR2_MSWU_Msk            (0x1UL << HRTIM_CR2_MSWU_Pos)            /*!< 0x00000001 */

+#define HRTIM_CR2_MSWU                HRTIM_CR2_MSWU_Msk                       /*!< Master software update */

+#define HRTIM_CR2_TASWU_Pos           (1U)

+#define HRTIM_CR2_TASWU_Msk           (0x1UL << HRTIM_CR2_TASWU_Pos)           /*!< 0x00000002 */

+#define HRTIM_CR2_TASWU               HRTIM_CR2_TASWU_Msk                      /*!< Timer A software update */

+#define HRTIM_CR2_TBSWU_Pos           (2U)

+#define HRTIM_CR2_TBSWU_Msk           (0x1UL << HRTIM_CR2_TBSWU_Pos)           /*!< 0x00000004 */

+#define HRTIM_CR2_TBSWU               HRTIM_CR2_TBSWU_Msk                      /*!< Timer B software update */

+#define HRTIM_CR2_TCSWU_Pos           (3U)

+#define HRTIM_CR2_TCSWU_Msk           (0x1UL << HRTIM_CR2_TCSWU_Pos)           /*!< 0x00000008 */

+#define HRTIM_CR2_TCSWU               HRTIM_CR2_TCSWU_Msk                      /*!< Timer C software update */

+#define HRTIM_CR2_TDSWU_Pos           (4U)

+#define HRTIM_CR2_TDSWU_Msk           (0x1UL << HRTIM_CR2_TDSWU_Pos)           /*!< 0x00000010 */

+#define HRTIM_CR2_TDSWU               HRTIM_CR2_TDSWU_Msk                      /*!< Timer D software update */

+#define HRTIM_CR2_TESWU_Pos           (5U)

+#define HRTIM_CR2_TESWU_Msk           (0x1UL << HRTIM_CR2_TESWU_Pos)           /*!< 0x00000020 */

+#define HRTIM_CR2_TESWU               HRTIM_CR2_TESWU_Msk                      /*!< Timer E software update */

+#define HRTIM_CR2_MRST_Pos            (8U)

+#define HRTIM_CR2_MRST_Msk            (0x1UL << HRTIM_CR2_MRST_Pos)            /*!< 0x00000100 */

+#define HRTIM_CR2_MRST                HRTIM_CR2_MRST_Msk                       /*!< Master count software reset */

+#define HRTIM_CR2_TARST_Pos           (9U)

+#define HRTIM_CR2_TARST_Msk           (0x1UL << HRTIM_CR2_TARST_Pos)           /*!< 0x00000200 */

+#define HRTIM_CR2_TARST               HRTIM_CR2_TARST_Msk                      /*!< Timer A count software reset */

+#define HRTIM_CR2_TBRST_Pos           (10U)

+#define HRTIM_CR2_TBRST_Msk           (0x1UL << HRTIM_CR2_TBRST_Pos)           /*!< 0x00000400 */

+#define HRTIM_CR2_TBRST               HRTIM_CR2_TBRST_Msk                      /*!< Timer B count software reset */

+#define HRTIM_CR2_TCRST_Pos           (11U)

+#define HRTIM_CR2_TCRST_Msk           (0x1UL << HRTIM_CR2_TCRST_Pos)           /*!< 0x00000800 */

+#define HRTIM_CR2_TCRST               HRTIM_CR2_TCRST_Msk                      /*!< Timer C count software reset */

+#define HRTIM_CR2_TDRST_Pos           (12U)

+#define HRTIM_CR2_TDRST_Msk           (0x1UL << HRTIM_CR2_TDRST_Pos)           /*!< 0x00001000 */

+#define HRTIM_CR2_TDRST               HRTIM_CR2_TDRST_Msk                      /*!< Timer D count software reset */

+#define HRTIM_CR2_TERST_Pos           (13U)

+#define HRTIM_CR2_TERST_Msk           (0x1UL << HRTIM_CR2_TERST_Pos)           /*!< 0x00002000 */

+#define HRTIM_CR2_TERST               HRTIM_CR2_TERST_Msk                      /*!< Timer E count software reset */

+

+/**** Bit definition for Common HRTIM Timer interrupt status register *********/

+#define HRTIM_ISR_FLT1_Pos            (0U)

+#define HRTIM_ISR_FLT1_Msk            (0x1UL << HRTIM_ISR_FLT1_Pos)            /*!< 0x00000001 */

+#define HRTIM_ISR_FLT1                HRTIM_ISR_FLT1_Msk                       /*!< Fault 1 interrupt flag */

+#define HRTIM_ISR_FLT2_Pos            (1U)

+#define HRTIM_ISR_FLT2_Msk            (0x1UL << HRTIM_ISR_FLT2_Pos)            /*!< 0x00000002 */

+#define HRTIM_ISR_FLT2                HRTIM_ISR_FLT2_Msk                       /*!< Fault 2 interrupt flag */

+#define HRTIM_ISR_FLT3_Pos            (2U)

+#define HRTIM_ISR_FLT3_Msk            (0x1UL << HRTIM_ISR_FLT3_Pos)            /*!< 0x00000004 */

+#define HRTIM_ISR_FLT3                HRTIM_ISR_FLT3_Msk                       /*!< Fault 3 interrupt flag */

+#define HRTIM_ISR_FLT4_Pos            (3U)

+#define HRTIM_ISR_FLT4_Msk            (0x1UL << HRTIM_ISR_FLT4_Pos)            /*!< 0x00000008 */

+#define HRTIM_ISR_FLT4                HRTIM_ISR_FLT4_Msk                       /*!< Fault 4 interrupt flag */

+#define HRTIM_ISR_FLT5_Pos            (4U)

+#define HRTIM_ISR_FLT5_Msk            (0x1UL << HRTIM_ISR_FLT5_Pos)            /*!< 0x00000010 */

+#define HRTIM_ISR_FLT5                HRTIM_ISR_FLT5_Msk                       /*!< Fault 5 interrupt flag */

+#define HRTIM_ISR_SYSFLT_Pos          (5U)

+#define HRTIM_ISR_SYSFLT_Msk          (0x1UL << HRTIM_ISR_SYSFLT_Pos)          /*!< 0x00000020 */

+#define HRTIM_ISR_SYSFLT              HRTIM_ISR_SYSFLT_Msk                     /*!< System Fault interrupt flag */

+#define HRTIM_ISR_BMPER_Pos           (17U)

+#define HRTIM_ISR_BMPER_Msk           (0x1UL << HRTIM_ISR_BMPER_Pos)           /*!< 0x00020000 */

+#define HRTIM_ISR_BMPER               HRTIM_ISR_BMPER_Msk                      /*!<  Burst mode period interrupt flag */

+

+/**** Bit definition for Common HRTIM Timer interrupt clear register **********/

+#define HRTIM_ICR_FLT1C_Pos           (0U)

+#define HRTIM_ICR_FLT1C_Msk           (0x1UL << HRTIM_ICR_FLT1C_Pos)           /*!< 0x00000001 */

+#define HRTIM_ICR_FLT1C               HRTIM_ICR_FLT1C_Msk                      /*!< Fault 1 interrupt flag clear */

+#define HRTIM_ICR_FLT2C_Pos           (1U)

+#define HRTIM_ICR_FLT2C_Msk           (0x1UL << HRTIM_ICR_FLT2C_Pos)           /*!< 0x00000002 */

+#define HRTIM_ICR_FLT2C               HRTIM_ICR_FLT2C_Msk                      /*!< Fault 2 interrupt flag clear */

+#define HRTIM_ICR_FLT3C_Pos           (2U)

+#define HRTIM_ICR_FLT3C_Msk           (0x1UL << HRTIM_ICR_FLT3C_Pos)           /*!< 0x00000004 */

+#define HRTIM_ICR_FLT3C               HRTIM_ICR_FLT3C_Msk                      /*!< Fault 3 interrupt flag clear */

+#define HRTIM_ICR_FLT4C_Pos           (3U)

+#define HRTIM_ICR_FLT4C_Msk           (0x1UL << HRTIM_ICR_FLT4C_Pos)           /*!< 0x00000008 */

+#define HRTIM_ICR_FLT4C               HRTIM_ICR_FLT4C_Msk                      /*!< Fault 4 interrupt flag clear */

+#define HRTIM_ICR_FLT5C_Pos           (4U)

+#define HRTIM_ICR_FLT5C_Msk           (0x1UL << HRTIM_ICR_FLT5C_Pos)           /*!< 0x00000010 */

+#define HRTIM_ICR_FLT5C               HRTIM_ICR_FLT5C_Msk                      /*!< Fault 5 interrupt flag clear */

+#define HRTIM_ICR_SYSFLTC_Pos         (5U)

+#define HRTIM_ICR_SYSFLTC_Msk         (0x1UL << HRTIM_ICR_SYSFLTC_Pos)         /*!< 0x00000020 */

+#define HRTIM_ICR_SYSFLTC             HRTIM_ICR_SYSFLTC_Msk                    /*!< System Fault interrupt flag clear */

+#define HRTIM_ICR_BMPERC_Pos          (17U)

+#define HRTIM_ICR_BMPERC_Msk          (0x1UL << HRTIM_ICR_BMPERC_Pos)          /*!< 0x00020000 */

+#define HRTIM_ICR_BMPERC              HRTIM_ICR_BMPERC_Msk                     /*!<  Burst mode period interrupt flag clear */

+

+/**** Bit definition for Common HRTIM Timer interrupt enable register *********/

+#define HRTIM_IER_FLT1_Pos            (0U)

+#define HRTIM_IER_FLT1_Msk            (0x1UL << HRTIM_IER_FLT1_Pos)            /*!< 0x00000001 */

+#define HRTIM_IER_FLT1                HRTIM_IER_FLT1_Msk                       /*!< Fault 1 interrupt enable */

+#define HRTIM_IER_FLT2_Pos            (1U)

+#define HRTIM_IER_FLT2_Msk            (0x1UL << HRTIM_IER_FLT2_Pos)            /*!< 0x00000002 */

+#define HRTIM_IER_FLT2                HRTIM_IER_FLT2_Msk                       /*!< Fault 2 interrupt enable */

+#define HRTIM_IER_FLT3_Pos            (2U)

+#define HRTIM_IER_FLT3_Msk            (0x1UL << HRTIM_IER_FLT3_Pos)            /*!< 0x00000004 */

+#define HRTIM_IER_FLT3                HRTIM_IER_FLT3_Msk                       /*!< Fault 3 interrupt enable */

+#define HRTIM_IER_FLT4_Pos            (3U)

+#define HRTIM_IER_FLT4_Msk            (0x1UL << HRTIM_IER_FLT4_Pos)            /*!< 0x00000008 */

+#define HRTIM_IER_FLT4                HRTIM_IER_FLT4_Msk                       /*!< Fault 4 interrupt enable */

+#define HRTIM_IER_FLT5_Pos            (4U)

+#define HRTIM_IER_FLT5_Msk            (0x1UL << HRTIM_IER_FLT5_Pos)            /*!< 0x00000010 */

+#define HRTIM_IER_FLT5                HRTIM_IER_FLT5_Msk                       /*!< Fault 5 interrupt enable */

+#define HRTIM_IER_SYSFLT_Pos          (5U)

+#define HRTIM_IER_SYSFLT_Msk          (0x1UL << HRTIM_IER_SYSFLT_Pos)          /*!< 0x00000020 */

+#define HRTIM_IER_SYSFLT              HRTIM_IER_SYSFLT_Msk                     /*!< System Fault interrupt enable */

+#define HRTIM_IER_BMPER_Pos           (17U)

+#define HRTIM_IER_BMPER_Msk           (0x1UL << HRTIM_IER_BMPER_Pos)           /*!< 0x00020000 */

+#define HRTIM_IER_BMPER               HRTIM_IER_BMPER_Msk                      /*!<  Burst mode period interrupt enable */

+

+/**** Bit definition for Common HRTIM Timer output enable register ************/

+#define HRTIM_OENR_TA1OEN_Pos         (0U)

+#define HRTIM_OENR_TA1OEN_Msk         (0x1UL << HRTIM_OENR_TA1OEN_Pos)         /*!< 0x00000001 */

+#define HRTIM_OENR_TA1OEN             HRTIM_OENR_TA1OEN_Msk                    /*!< Timer A Output 1 enable */

+#define HRTIM_OENR_TA2OEN_Pos         (1U)

+#define HRTIM_OENR_TA2OEN_Msk         (0x1UL << HRTIM_OENR_TA2OEN_Pos)         /*!< 0x00000002 */

+#define HRTIM_OENR_TA2OEN             HRTIM_OENR_TA2OEN_Msk                    /*!< Timer A Output 2 enable */

+#define HRTIM_OENR_TB1OEN_Pos         (2U)

+#define HRTIM_OENR_TB1OEN_Msk         (0x1UL << HRTIM_OENR_TB1OEN_Pos)         /*!< 0x00000004 */

+#define HRTIM_OENR_TB1OEN             HRTIM_OENR_TB1OEN_Msk                    /*!< Timer B Output 1 enable */

+#define HRTIM_OENR_TB2OEN_Pos         (3U)

+#define HRTIM_OENR_TB2OEN_Msk         (0x1UL << HRTIM_OENR_TB2OEN_Pos)         /*!< 0x00000008 */

+#define HRTIM_OENR_TB2OEN             HRTIM_OENR_TB2OEN_Msk                    /*!< Timer B Output 2 enable */

+#define HRTIM_OENR_TC1OEN_Pos         (4U)

+#define HRTIM_OENR_TC1OEN_Msk         (0x1UL << HRTIM_OENR_TC1OEN_Pos)         /*!< 0x00000010 */

+#define HRTIM_OENR_TC1OEN             HRTIM_OENR_TC1OEN_Msk                    /*!< Timer C Output 1 enable */

+#define HRTIM_OENR_TC2OEN_Pos         (5U)

+#define HRTIM_OENR_TC2OEN_Msk         (0x1UL << HRTIM_OENR_TC2OEN_Pos)         /*!< 0x00000020 */

+#define HRTIM_OENR_TC2OEN             HRTIM_OENR_TC2OEN_Msk                    /*!< Timer C Output 2 enable */

+#define HRTIM_OENR_TD1OEN_Pos         (6U)

+#define HRTIM_OENR_TD1OEN_Msk         (0x1UL << HRTIM_OENR_TD1OEN_Pos)         /*!< 0x00000040 */

+#define HRTIM_OENR_TD1OEN             HRTIM_OENR_TD1OEN_Msk                    /*!< Timer D Output 1 enable */

+#define HRTIM_OENR_TD2OEN_Pos         (7U)

+#define HRTIM_OENR_TD2OEN_Msk         (0x1UL << HRTIM_OENR_TD2OEN_Pos)         /*!< 0x00000080 */

+#define HRTIM_OENR_TD2OEN             HRTIM_OENR_TD2OEN_Msk                    /*!< Timer D Output 2 enable */

+#define HRTIM_OENR_TE1OEN_Pos         (8U)

+#define HRTIM_OENR_TE1OEN_Msk         (0x1UL << HRTIM_OENR_TE1OEN_Pos)         /*!< 0x00000100 */

+#define HRTIM_OENR_TE1OEN             HRTIM_OENR_TE1OEN_Msk                    /*!< Timer E Output 1 enable */

+#define HRTIM_OENR_TE2OEN_Pos         (9U)

+#define HRTIM_OENR_TE2OEN_Msk         (0x1UL << HRTIM_OENR_TE2OEN_Pos)         /*!< 0x00000200 */

+#define HRTIM_OENR_TE2OEN             HRTIM_OENR_TE2OEN_Msk                    /*!< Timer E Output 2 enable */

+

+/**** Bit definition for Common HRTIM Timer output disable register ***********/

+#define HRTIM_ODISR_TA1ODIS_Pos       (0U)

+#define HRTIM_ODISR_TA1ODIS_Msk       (0x1UL << HRTIM_ODISR_TA1ODIS_Pos)       /*!< 0x00000001 */

+#define HRTIM_ODISR_TA1ODIS           HRTIM_ODISR_TA1ODIS_Msk                  /*!< Timer A Output 1 disable */

+#define HRTIM_ODISR_TA2ODIS_Pos       (1U)

+#define HRTIM_ODISR_TA2ODIS_Msk       (0x1UL << HRTIM_ODISR_TA2ODIS_Pos)       /*!< 0x00000002 */

+#define HRTIM_ODISR_TA2ODIS           HRTIM_ODISR_TA2ODIS_Msk                  /*!< Timer A Output 2 disable */

+#define HRTIM_ODISR_TB1ODIS_Pos       (2U)

+#define HRTIM_ODISR_TB1ODIS_Msk       (0x1UL << HRTIM_ODISR_TB1ODIS_Pos)       /*!< 0x00000004 */

+#define HRTIM_ODISR_TB1ODIS           HRTIM_ODISR_TB1ODIS_Msk                  /*!< Timer B Output 1 disable */

+#define HRTIM_ODISR_TB2ODIS_Pos       (3U)

+#define HRTIM_ODISR_TB2ODIS_Msk       (0x1UL << HRTIM_ODISR_TB2ODIS_Pos)       /*!< 0x00000008 */

+#define HRTIM_ODISR_TB2ODIS           HRTIM_ODISR_TB2ODIS_Msk                  /*!< Timer B Output 2 disable */

+#define HRTIM_ODISR_TC1ODIS_Pos       (4U)

+#define HRTIM_ODISR_TC1ODIS_Msk       (0x1UL << HRTIM_ODISR_TC1ODIS_Pos)       /*!< 0x00000010 */

+#define HRTIM_ODISR_TC1ODIS           HRTIM_ODISR_TC1ODIS_Msk                  /*!< Timer C Output 1 disable */

+#define HRTIM_ODISR_TC2ODIS_Pos       (5U)

+#define HRTIM_ODISR_TC2ODIS_Msk       (0x1UL << HRTIM_ODISR_TC2ODIS_Pos)       /*!< 0x00000020 */

+#define HRTIM_ODISR_TC2ODIS           HRTIM_ODISR_TC2ODIS_Msk                  /*!< Timer C Output 2 disable */

+#define HRTIM_ODISR_TD1ODIS_Pos       (6U)

+#define HRTIM_ODISR_TD1ODIS_Msk       (0x1UL << HRTIM_ODISR_TD1ODIS_Pos)       /*!< 0x00000040 */

+#define HRTIM_ODISR_TD1ODIS           HRTIM_ODISR_TD1ODIS_Msk                  /*!< Timer D Output 1 disable */

+#define HRTIM_ODISR_TD2ODIS_Pos       (7U)

+#define HRTIM_ODISR_TD2ODIS_Msk       (0x1UL << HRTIM_ODISR_TD2ODIS_Pos)       /*!< 0x00000080 */

+#define HRTIM_ODISR_TD2ODIS           HRTIM_ODISR_TD2ODIS_Msk                  /*!< Timer D Output 2 disable */

+#define HRTIM_ODISR_TE1ODIS_Pos       (8U)

+#define HRTIM_ODISR_TE1ODIS_Msk       (0x1UL << HRTIM_ODISR_TE1ODIS_Pos)       /*!< 0x00000100 */

+#define HRTIM_ODISR_TE1ODIS           HRTIM_ODISR_TE1ODIS_Msk                  /*!< Timer E Output 1 disable */

+#define HRTIM_ODISR_TE2ODIS_Pos       (9U)

+#define HRTIM_ODISR_TE2ODIS_Msk       (0x1UL << HRTIM_ODISR_TE2ODIS_Pos)       /*!< 0x00000200 */

+#define HRTIM_ODISR_TE2ODIS           HRTIM_ODISR_TE2ODIS_Msk                  /*!< Timer E Output 2 disable */

+

+/**** Bit definition for Common HRTIM Timer output disable status register *****/

+#define HRTIM_ODSR_TA1ODS_Pos         (0U)

+#define HRTIM_ODSR_TA1ODS_Msk         (0x1UL << HRTIM_ODSR_TA1ODS_Pos)         /*!< 0x00000001 */

+#define HRTIM_ODSR_TA1ODS             HRTIM_ODSR_TA1ODS_Msk                    /*!< Timer A Output 1 disable status */

+#define HRTIM_ODSR_TA2ODS_Pos         (1U)

+#define HRTIM_ODSR_TA2ODS_Msk         (0x1UL << HRTIM_ODSR_TA2ODS_Pos)         /*!< 0x00000002 */

+#define HRTIM_ODSR_TA2ODS             HRTIM_ODSR_TA2ODS_Msk                    /*!< Timer A Output 2 disable status */

+#define HRTIM_ODSR_TB1ODS_Pos         (2U)

+#define HRTIM_ODSR_TB1ODS_Msk         (0x1UL << HRTIM_ODSR_TB1ODS_Pos)         /*!< 0x00000004 */

+#define HRTIM_ODSR_TB1ODS             HRTIM_ODSR_TB1ODS_Msk                    /*!< Timer B Output 1 disable status */

+#define HRTIM_ODSR_TB2ODS_Pos         (3U)

+#define HRTIM_ODSR_TB2ODS_Msk         (0x1UL << HRTIM_ODSR_TB2ODS_Pos)         /*!< 0x00000008 */

+#define HRTIM_ODSR_TB2ODS             HRTIM_ODSR_TB2ODS_Msk                    /*!< Timer B Output 2 disable status */

+#define HRTIM_ODSR_TC1ODS_Pos         (4U)

+#define HRTIM_ODSR_TC1ODS_Msk         (0x1UL << HRTIM_ODSR_TC1ODS_Pos)         /*!< 0x00000010 */

+#define HRTIM_ODSR_TC1ODS             HRTIM_ODSR_TC1ODS_Msk                    /*!< Timer C Output 1 disable status */

+#define HRTIM_ODSR_TC2ODS_Pos         (5U)

+#define HRTIM_ODSR_TC2ODS_Msk         (0x1UL << HRTIM_ODSR_TC2ODS_Pos)         /*!< 0x00000020 */

+#define HRTIM_ODSR_TC2ODS             HRTIM_ODSR_TC2ODS_Msk                    /*!< Timer C Output 2 disable status */

+#define HRTIM_ODSR_TD1ODS_Pos         (6U)

+#define HRTIM_ODSR_TD1ODS_Msk         (0x1UL << HRTIM_ODSR_TD1ODS_Pos)         /*!< 0x00000040 */

+#define HRTIM_ODSR_TD1ODS             HRTIM_ODSR_TD1ODS_Msk                    /*!< Timer D Output 1 disable status */

+#define HRTIM_ODSR_TD2ODS_Pos         (7U)

+#define HRTIM_ODSR_TD2ODS_Msk         (0x1UL << HRTIM_ODSR_TD2ODS_Pos)         /*!< 0x00000080 */

+#define HRTIM_ODSR_TD2ODS             HRTIM_ODSR_TD2ODS_Msk                    /*!< Timer D Output 2 disable status */

+#define HRTIM_ODSR_TE1ODS_Pos         (8U)

+#define HRTIM_ODSR_TE1ODS_Msk         (0x1UL << HRTIM_ODSR_TE1ODS_Pos)         /*!< 0x00000100 */

+#define HRTIM_ODSR_TE1ODS             HRTIM_ODSR_TE1ODS_Msk                    /*!< Timer E Output 1 disable status */

+#define HRTIM_ODSR_TE2ODS_Pos         (9U)

+#define HRTIM_ODSR_TE2ODS_Msk         (0x1UL << HRTIM_ODSR_TE2ODS_Pos)         /*!< 0x00000200 */

+#define HRTIM_ODSR_TE2ODS             HRTIM_ODSR_TE2ODS_Msk                    /*!< Timer E Output 2 disable status */

+

+/**** Bit definition for Common HRTIM Timer Burst mode control register ********/

+#define HRTIM_BMCR_BME_Pos            (0U)

+#define HRTIM_BMCR_BME_Msk            (0x1UL << HRTIM_BMCR_BME_Pos)            /*!< 0x00000001 */

+#define HRTIM_BMCR_BME                HRTIM_BMCR_BME_Msk                       /*!< Burst mode enbale */

+#define HRTIM_BMCR_BMOM_Pos           (1U)

+#define HRTIM_BMCR_BMOM_Msk           (0x1UL << HRTIM_BMCR_BMOM_Pos)           /*!< 0x00000002 */

+#define HRTIM_BMCR_BMOM               HRTIM_BMCR_BMOM_Msk                      /*!< Burst mode operating mode */

+#define HRTIM_BMCR_BMCLK_Pos          (2U)

+#define HRTIM_BMCR_BMCLK_Msk          (0xFUL << HRTIM_BMCR_BMCLK_Pos)          /*!< 0x0000003C */

+#define HRTIM_BMCR_BMCLK              HRTIM_BMCR_BMCLK_Msk                     /*!< Burst mode clock source */

+#define HRTIM_BMCR_BMCLK_0            (0x1UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000004 */

+#define HRTIM_BMCR_BMCLK_1            (0x2UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000008 */

+#define HRTIM_BMCR_BMCLK_2            (0x4UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000010 */

+#define HRTIM_BMCR_BMCLK_3            (0x8UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000020 */

+#define HRTIM_BMCR_BMPRSC_Pos         (6U)

+#define HRTIM_BMCR_BMPRSC_Msk         (0xFUL << HRTIM_BMCR_BMPRSC_Pos)         /*!< 0x000003C0 */

+#define HRTIM_BMCR_BMPRSC             HRTIM_BMCR_BMPRSC_Msk                    /*!< Burst mode prescaler */

+#define HRTIM_BMCR_BMPRSC_0           (0x1UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000040 */

+#define HRTIM_BMCR_BMPRSC_1           (0x2UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000080 */

+#define HRTIM_BMCR_BMPRSC_2           (0x4UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000100 */

+#define HRTIM_BMCR_BMPRSC_3           (0x8UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000200 */

+#define HRTIM_BMCR_BMPREN_Pos         (10U)

+#define HRTIM_BMCR_BMPREN_Msk         (0x1UL << HRTIM_BMCR_BMPREN_Pos)         /*!< 0x00000400 */

+#define HRTIM_BMCR_BMPREN             HRTIM_BMCR_BMPREN_Msk                    /*!< Burst mode Preload bit */

+#define HRTIM_BMCR_MTBM_Pos           (16U)

+#define HRTIM_BMCR_MTBM_Msk           (0x1UL << HRTIM_BMCR_MTBM_Pos)           /*!< 0x00010000 */

+#define HRTIM_BMCR_MTBM               HRTIM_BMCR_MTBM_Msk                      /*!< Master Timer Burst mode */

+#define HRTIM_BMCR_TABM_Pos           (17U)

+#define HRTIM_BMCR_TABM_Msk           (0x1UL << HRTIM_BMCR_TABM_Pos)           /*!< 0x00020000 */

+#define HRTIM_BMCR_TABM               HRTIM_BMCR_TABM_Msk                      /*!< Timer A Burst mode */

+#define HRTIM_BMCR_TBBM_Pos           (18U)

+#define HRTIM_BMCR_TBBM_Msk           (0x1UL << HRTIM_BMCR_TBBM_Pos)           /*!< 0x00040000 */

+#define HRTIM_BMCR_TBBM               HRTIM_BMCR_TBBM_Msk                      /*!< Timer B Burst mode */

+#define HRTIM_BMCR_TCBM_Pos           (19U)

+#define HRTIM_BMCR_TCBM_Msk           (0x1UL << HRTIM_BMCR_TCBM_Pos)           /*!< 0x00080000 */

+#define HRTIM_BMCR_TCBM               HRTIM_BMCR_TCBM_Msk                      /*!< Timer C Burst mode */

+#define HRTIM_BMCR_TDBM_Pos           (20U)

+#define HRTIM_BMCR_TDBM_Msk           (0x1UL << HRTIM_BMCR_TDBM_Pos)           /*!< 0x00100000 */

+#define HRTIM_BMCR_TDBM               HRTIM_BMCR_TDBM_Msk                      /*!< Timer D Burst mode */

+#define HRTIM_BMCR_TEBM_Pos           (21U)

+#define HRTIM_BMCR_TEBM_Msk           (0x1UL << HRTIM_BMCR_TEBM_Pos)           /*!< 0x00200000 */

+#define HRTIM_BMCR_TEBM               HRTIM_BMCR_TEBM_Msk                      /*!< Timer E Burst mode */

+#define HRTIM_BMCR_BMSTAT_Pos         (31U)

+#define HRTIM_BMCR_BMSTAT_Msk         (0x1UL << HRTIM_BMCR_BMSTAT_Pos)         /*!< 0x80000000 */

+#define HRTIM_BMCR_BMSTAT             HRTIM_BMCR_BMSTAT_Msk                    /*!< Burst mode status */

+

+/**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/

+#define HRTIM_BMTRGR_SW_Pos           (0U)

+#define HRTIM_BMTRGR_SW_Msk           (0x1UL << HRTIM_BMTRGR_SW_Pos)           /*!< 0x00000001 */

+#define HRTIM_BMTRGR_SW               HRTIM_BMTRGR_SW_Msk                      /*!< Software start */

+#define HRTIM_BMTRGR_MSTRST_Pos       (1U)

+#define HRTIM_BMTRGR_MSTRST_Msk       (0x1UL << HRTIM_BMTRGR_MSTRST_Pos)       /*!< 0x00000002 */

+#define HRTIM_BMTRGR_MSTRST           HRTIM_BMTRGR_MSTRST_Msk                  /*!<  Master reset */

+#define HRTIM_BMTRGR_MSTREP_Pos       (2U)

+#define HRTIM_BMTRGR_MSTREP_Msk       (0x1UL << HRTIM_BMTRGR_MSTREP_Pos)       /*!< 0x00000004 */

+#define HRTIM_BMTRGR_MSTREP           HRTIM_BMTRGR_MSTREP_Msk                  /*!<  Master repetition */

+#define HRTIM_BMTRGR_MSTCMP1_Pos      (3U)

+#define HRTIM_BMTRGR_MSTCMP1_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos)      /*!< 0x00000008 */

+#define HRTIM_BMTRGR_MSTCMP1          HRTIM_BMTRGR_MSTCMP1_Msk                 /*!<  Master compare 1 */

+#define HRTIM_BMTRGR_MSTCMP2_Pos      (4U)

+#define HRTIM_BMTRGR_MSTCMP2_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos)      /*!< 0x00000010 */

+#define HRTIM_BMTRGR_MSTCMP2          HRTIM_BMTRGR_MSTCMP2_Msk                 /*!< Master compare 2  */

+#define HRTIM_BMTRGR_MSTCMP3_Pos      (5U)

+#define HRTIM_BMTRGR_MSTCMP3_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos)      /*!< 0x00000020 */

+#define HRTIM_BMTRGR_MSTCMP3          HRTIM_BMTRGR_MSTCMP3_Msk                 /*!< Master compare 3 */

+#define HRTIM_BMTRGR_MSTCMP4_Pos      (6U)

+#define HRTIM_BMTRGR_MSTCMP4_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos)      /*!< 0x00000040 */

+#define HRTIM_BMTRGR_MSTCMP4          HRTIM_BMTRGR_MSTCMP4_Msk                 /*!< Master compare 4 */

+#define HRTIM_BMTRGR_TARST_Pos        (7U)

+#define HRTIM_BMTRGR_TARST_Msk        (0x1UL << HRTIM_BMTRGR_TARST_Pos)        /*!< 0x00000080 */

+#define HRTIM_BMTRGR_TARST            HRTIM_BMTRGR_TARST_Msk                   /*!< Timer A reset  */

+#define HRTIM_BMTRGR_TAREP_Pos        (8U)

+#define HRTIM_BMTRGR_TAREP_Msk        (0x1UL << HRTIM_BMTRGR_TAREP_Pos)        /*!< 0x00000100 */

+#define HRTIM_BMTRGR_TAREP            HRTIM_BMTRGR_TAREP_Msk                   /*!< Timer A repetition  */

+#define HRTIM_BMTRGR_TACMP1_Pos       (9U)

+#define HRTIM_BMTRGR_TACMP1_Msk       (0x1UL << HRTIM_BMTRGR_TACMP1_Pos)       /*!< 0x00000200 */

+#define HRTIM_BMTRGR_TACMP1           HRTIM_BMTRGR_TACMP1_Msk                  /*!< Timer A compare 1  */

+#define HRTIM_BMTRGR_TACMP2_Pos       (10U)

+#define HRTIM_BMTRGR_TACMP2_Msk       (0x1UL << HRTIM_BMTRGR_TACMP2_Pos)       /*!< 0x00000400 */

+#define HRTIM_BMTRGR_TACMP2           HRTIM_BMTRGR_TACMP2_Msk                  /*!< Timer A compare 2  */

+#define HRTIM_BMTRGR_TBRST_Pos        (11U)

+#define HRTIM_BMTRGR_TBRST_Msk        (0x1UL << HRTIM_BMTRGR_TBRST_Pos)        /*!< 0x00000800 */

+#define HRTIM_BMTRGR_TBRST            HRTIM_BMTRGR_TBRST_Msk                   /*!< Timer B reset  */

+#define HRTIM_BMTRGR_TBREP_Pos        (12U)

+#define HRTIM_BMTRGR_TBREP_Msk        (0x1UL << HRTIM_BMTRGR_TBREP_Pos)        /*!< 0x00001000 */

+#define HRTIM_BMTRGR_TBREP            HRTIM_BMTRGR_TBREP_Msk                   /*!< Timer B repetition  */

+#define HRTIM_BMTRGR_TBCMP1_Pos       (13U)

+#define HRTIM_BMTRGR_TBCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos)       /*!< 0x00002000 */

+#define HRTIM_BMTRGR_TBCMP1           HRTIM_BMTRGR_TBCMP1_Msk                  /*!< Timer B compare 1 */

+#define HRTIM_BMTRGR_TBCMP2_Pos       (14U)

+#define HRTIM_BMTRGR_TBCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos)       /*!< 0x00004000 */

+#define HRTIM_BMTRGR_TBCMP2           HRTIM_BMTRGR_TBCMP2_Msk                  /*!< Timer B compare 2 */

+#define HRTIM_BMTRGR_TCRST_Pos        (15U)

+#define HRTIM_BMTRGR_TCRST_Msk        (0x1UL << HRTIM_BMTRGR_TCRST_Pos)        /*!< 0x00008000 */

+#define HRTIM_BMTRGR_TCRST            HRTIM_BMTRGR_TCRST_Msk                   /*!< Timer C reset  */

+#define HRTIM_BMTRGR_TCREP_Pos        (16U)

+#define HRTIM_BMTRGR_TCREP_Msk        (0x1UL << HRTIM_BMTRGR_TCREP_Pos)        /*!< 0x00010000 */

+#define HRTIM_BMTRGR_TCREP            HRTIM_BMTRGR_TCREP_Msk                   /*!< Timer C repetition */

+#define HRTIM_BMTRGR_TCCMP1_Pos       (17U)

+#define HRTIM_BMTRGR_TCCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos)       /*!< 0x00020000 */

+#define HRTIM_BMTRGR_TCCMP1           HRTIM_BMTRGR_TCCMP1_Msk                  /*!< Timer C compare 1 */

+#define HRTIM_BMTRGR_TCCMP2_Pos       (18U)

+#define HRTIM_BMTRGR_TCCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP2_Pos)       /*!< 0x00040000 */

+#define HRTIM_BMTRGR_TCCMP2           HRTIM_BMTRGR_TCCMP2_Msk                  /*!< Timer C compare 2 */

+#define HRTIM_BMTRGR_TDRST_Pos        (19U)

+#define HRTIM_BMTRGR_TDRST_Msk        (0x1UL << HRTIM_BMTRGR_TDRST_Pos)        /*!< 0x00080000 */

+#define HRTIM_BMTRGR_TDRST            HRTIM_BMTRGR_TDRST_Msk                   /*!< Timer D reset  */

+#define HRTIM_BMTRGR_TDREP_Pos        (20U)

+#define HRTIM_BMTRGR_TDREP_Msk        (0x1UL << HRTIM_BMTRGR_TDREP_Pos)        /*!< 0x00100000 */

+#define HRTIM_BMTRGR_TDREP            HRTIM_BMTRGR_TDREP_Msk                   /*!< Timer D repetition  */

+#define HRTIM_BMTRGR_TDCMP1_Pos       (21U)

+#define HRTIM_BMTRGR_TDCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP1_Pos)       /*!< 0x00200000 */

+#define HRTIM_BMTRGR_TDCMP1           HRTIM_BMTRGR_TDCMP1_Msk                  /*!< Timer D compare 1 */

+#define HRTIM_BMTRGR_TDCMP2_Pos       (22U)

+#define HRTIM_BMTRGR_TDCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos)       /*!< 0x00400000 */

+#define HRTIM_BMTRGR_TDCMP2           HRTIM_BMTRGR_TDCMP2_Msk                  /*!< Timer D compare 2 */

+#define HRTIM_BMTRGR_TERST_Pos        (23U)

+#define HRTIM_BMTRGR_TERST_Msk        (0x1UL << HRTIM_BMTRGR_TERST_Pos)        /*!< 0x00800000 */

+#define HRTIM_BMTRGR_TERST            HRTIM_BMTRGR_TERST_Msk                   /*!< Timer E reset  */

+#define HRTIM_BMTRGR_TEREP_Pos        (24U)

+#define HRTIM_BMTRGR_TEREP_Msk        (0x1UL << HRTIM_BMTRGR_TEREP_Pos)        /*!< 0x01000000 */

+#define HRTIM_BMTRGR_TEREP            HRTIM_BMTRGR_TEREP_Msk                   /*!< Timer E repetition  */

+#define HRTIM_BMTRGR_TECMP1_Pos       (25U)

+#define HRTIM_BMTRGR_TECMP1_Msk       (0x1UL << HRTIM_BMTRGR_TECMP1_Pos)       /*!< 0x02000000 */

+#define HRTIM_BMTRGR_TECMP1           HRTIM_BMTRGR_TECMP1_Msk                  /*!< Timer E compare 1 */

+#define HRTIM_BMTRGR_TECMP2_Pos       (26U)

+#define HRTIM_BMTRGR_TECMP2_Msk       (0x1UL << HRTIM_BMTRGR_TECMP2_Pos)       /*!< 0x04000000 */

+#define HRTIM_BMTRGR_TECMP2           HRTIM_BMTRGR_TECMP2_Msk                  /*!< Timer E compare 2 */

+#define HRTIM_BMTRGR_TAEEV7_Pos       (27U)

+#define HRTIM_BMTRGR_TAEEV7_Msk       (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos)       /*!< 0x08000000 */

+#define HRTIM_BMTRGR_TAEEV7           HRTIM_BMTRGR_TAEEV7_Msk                  /*!< Timer A period following External Event7  */

+#define HRTIM_BMTRGR_TDEEV8_Pos       (28U)

+#define HRTIM_BMTRGR_TDEEV8_Msk       (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos)       /*!< 0x10000000 */

+#define HRTIM_BMTRGR_TDEEV8           HRTIM_BMTRGR_TDEEV8_Msk                  /*!< Timer D period following External Event8  */

+#define HRTIM_BMTRGR_EEV7_Pos         (29U)

+#define HRTIM_BMTRGR_EEV7_Msk         (0x1UL << HRTIM_BMTRGR_EEV7_Pos)         /*!< 0x20000000 */

+#define HRTIM_BMTRGR_EEV7             HRTIM_BMTRGR_EEV7_Msk                    /*!< External Event 7 */

+#define HRTIM_BMTRGR_EEV8_Pos         (30U)

+#define HRTIM_BMTRGR_EEV8_Msk         (0x1UL << HRTIM_BMTRGR_EEV8_Pos)         /*!< 0x40000000 */

+#define HRTIM_BMTRGR_EEV8             HRTIM_BMTRGR_EEV8_Msk                    /*!< External Event 8 */

+#define HRTIM_BMTRGR_OCHPEV_Pos       (31U)

+#define HRTIM_BMTRGR_OCHPEV_Msk       (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos)       /*!< 0x80000000 */

+#define HRTIM_BMTRGR_OCHPEV           HRTIM_BMTRGR_OCHPEV_Msk                  /*!< on-chip Event */

+

+/*******************  Bit definition for HRTIM_BMCMPR register  ***************/

+#define HRTIM_BMCMPR_BMCMPR_Pos       (0U)

+#define HRTIM_BMCMPR_BMCMPR_Msk       (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_BMCMPR_BMCMPR           HRTIM_BMCMPR_BMCMPR_Msk                  /*!<!<Burst Compare Value */

+

+/*******************  Bit definition for HRTIM_BMPER register  ****************/

+#define HRTIM_BMPER_BMPER_Pos         (0U)

+#define HRTIM_BMPER_BMPER_Msk         (0xFFFFUL << HRTIM_BMPER_BMPER_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_BMPER_BMPER             HRTIM_BMPER_BMPER_Msk                    /*!<!<Burst period Value */

+

+/*******************  Bit definition for HRTIM_EECR1 register  ****************/

+#define HRTIM_EECR1_EE1SRC_Pos        (0U)

+#define HRTIM_EECR1_EE1SRC_Msk        (0x3UL << HRTIM_EECR1_EE1SRC_Pos)        /*!< 0x00000003 */

+#define HRTIM_EECR1_EE1SRC            HRTIM_EECR1_EE1SRC_Msk                   /*!< External event 1 source */

+#define HRTIM_EECR1_EE1SRC_0          (0x1UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000001 */

+#define HRTIM_EECR1_EE1SRC_1          (0x2UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000002 */

+#define HRTIM_EECR1_EE1POL_Pos        (2U)

+#define HRTIM_EECR1_EE1POL_Msk        (0x1UL << HRTIM_EECR1_EE1POL_Pos)        /*!< 0x00000004 */

+#define HRTIM_EECR1_EE1POL            HRTIM_EECR1_EE1POL_Msk                   /*!< External event 1 Polarity */

+#define HRTIM_EECR1_EE1SNS_Pos        (3U)

+#define HRTIM_EECR1_EE1SNS_Msk        (0x3UL << HRTIM_EECR1_EE1SNS_Pos)        /*!< 0x00000018 */

+#define HRTIM_EECR1_EE1SNS            HRTIM_EECR1_EE1SNS_Msk                   /*!< External event 1 sensitivity */

+#define HRTIM_EECR1_EE1SNS_0          (0x1UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000008 */

+#define HRTIM_EECR1_EE1SNS_1          (0x2UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000010 */

+#define HRTIM_EECR1_EE1FAST_Pos       (5U)

+#define HRTIM_EECR1_EE1FAST_Msk       (0x1UL << HRTIM_EECR1_EE1FAST_Pos)       /*!< 0x00000020 */

+#define HRTIM_EECR1_EE1FAST           HRTIM_EECR1_EE1FAST_Msk                  /*!< External event 1 Fast mode */

+

+#define HRTIM_EECR1_EE2SRC_Pos        (6U)

+#define HRTIM_EECR1_EE2SRC_Msk        (0x3UL << HRTIM_EECR1_EE2SRC_Pos)        /*!< 0x000000C0 */

+#define HRTIM_EECR1_EE2SRC            HRTIM_EECR1_EE2SRC_Msk                   /*!< External event 2 source */

+#define HRTIM_EECR1_EE2SRC_0          (0x1UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000040 */

+#define HRTIM_EECR1_EE2SRC_1          (0x2UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000080 */

+#define HRTIM_EECR1_EE2POL_Pos        (8U)

+#define HRTIM_EECR1_EE2POL_Msk        (0x1UL << HRTIM_EECR1_EE2POL_Pos)        /*!< 0x00000100 */

+#define HRTIM_EECR1_EE2POL            HRTIM_EECR1_EE2POL_Msk                   /*!< External event 2 Polarity */

+#define HRTIM_EECR1_EE2SNS_Pos        (9U)

+#define HRTIM_EECR1_EE2SNS_Msk        (0x3UL << HRTIM_EECR1_EE2SNS_Pos)        /*!< 0x00000600 */

+#define HRTIM_EECR1_EE2SNS            HRTIM_EECR1_EE2SNS_Msk                   /*!< External event 2 sensitivity */

+#define HRTIM_EECR1_EE2SNS_0          (0x1UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000200 */

+#define HRTIM_EECR1_EE2SNS_1          (0x2UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000400 */

+#define HRTIM_EECR1_EE2FAST_Pos       (11U)

+#define HRTIM_EECR1_EE2FAST_Msk       (0x1UL << HRTIM_EECR1_EE2FAST_Pos)       /*!< 0x00000800 */

+#define HRTIM_EECR1_EE2FAST           HRTIM_EECR1_EE2FAST_Msk                  /*!< External event 2 Fast mode */

+

+#define HRTIM_EECR1_EE3SRC_Pos        (12U)

+#define HRTIM_EECR1_EE3SRC_Msk        (0x3UL << HRTIM_EECR1_EE3SRC_Pos)        /*!< 0x00003000 */

+#define HRTIM_EECR1_EE3SRC            HRTIM_EECR1_EE3SRC_Msk                   /*!< External event 3 source */

+#define HRTIM_EECR1_EE3SRC_0          (0x1UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00001000 */

+#define HRTIM_EECR1_EE3SRC_1          (0x2UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00002000 */

+#define HRTIM_EECR1_EE3POL_Pos        (14U)

+#define HRTIM_EECR1_EE3POL_Msk        (0x1UL << HRTIM_EECR1_EE3POL_Pos)        /*!< 0x00004000 */

+#define HRTIM_EECR1_EE3POL            HRTIM_EECR1_EE3POL_Msk                   /*!< External event 3 Polarity */

+#define HRTIM_EECR1_EE3SNS_Pos        (15U)

+#define HRTIM_EECR1_EE3SNS_Msk        (0x3UL << HRTIM_EECR1_EE3SNS_Pos)        /*!< 0x00018000 */

+#define HRTIM_EECR1_EE3SNS            HRTIM_EECR1_EE3SNS_Msk                   /*!< External event 3 sensitivity */

+#define HRTIM_EECR1_EE3SNS_0          (0x1UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00008000 */

+#define HRTIM_EECR1_EE3SNS_1          (0x2UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00010000 */

+#define HRTIM_EECR1_EE3FAST_Pos       (17U)

+#define HRTIM_EECR1_EE3FAST_Msk       (0x1UL << HRTIM_EECR1_EE3FAST_Pos)       /*!< 0x00020000 */

+#define HRTIM_EECR1_EE3FAST           HRTIM_EECR1_EE3FAST_Msk                  /*!< External event 3 Fast mode */

+

+#define HRTIM_EECR1_EE4SRC_Pos        (18U)

+#define HRTIM_EECR1_EE4SRC_Msk        (0x3UL << HRTIM_EECR1_EE4SRC_Pos)        /*!< 0x000C0000 */

+#define HRTIM_EECR1_EE4SRC            HRTIM_EECR1_EE4SRC_Msk                   /*!< External event 4 source */

+#define HRTIM_EECR1_EE4SRC_0          (0x1UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00040000 */

+#define HRTIM_EECR1_EE4SRC_1          (0x2UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00080000 */

+#define HRTIM_EECR1_EE4POL_Pos        (20U)

+#define HRTIM_EECR1_EE4POL_Msk        (0x1UL << HRTIM_EECR1_EE4POL_Pos)        /*!< 0x00100000 */

+#define HRTIM_EECR1_EE4POL            HRTIM_EECR1_EE4POL_Msk                   /*!< External event 4 Polarity */

+#define HRTIM_EECR1_EE4SNS_Pos        (21U)

+#define HRTIM_EECR1_EE4SNS_Msk        (0x3UL << HRTIM_EECR1_EE4SNS_Pos)        /*!< 0x00600000 */

+#define HRTIM_EECR1_EE4SNS            HRTIM_EECR1_EE4SNS_Msk                   /*!< External event 4 sensitivity */

+#define HRTIM_EECR1_EE4SNS_0          (0x1UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00200000 */

+#define HRTIM_EECR1_EE4SNS_1          (0x2UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00400000 */

+#define HRTIM_EECR1_EE4FAST_Pos       (23U)

+#define HRTIM_EECR1_EE4FAST_Msk       (0x1UL << HRTIM_EECR1_EE4FAST_Pos)       /*!< 0x00800000 */

+#define HRTIM_EECR1_EE4FAST           HRTIM_EECR1_EE4FAST_Msk                  /*!< External event 4 Fast mode */

+

+#define HRTIM_EECR1_EE5SRC_Pos        (24U)

+#define HRTIM_EECR1_EE5SRC_Msk        (0x3UL << HRTIM_EECR1_EE5SRC_Pos)        /*!< 0x03000000 */

+#define HRTIM_EECR1_EE5SRC            HRTIM_EECR1_EE5SRC_Msk                   /*!< External event 5 source */

+#define HRTIM_EECR1_EE5SRC_0          (0x1UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x01000000 */

+#define HRTIM_EECR1_EE5SRC_1          (0x2UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x02000000 */

+#define HRTIM_EECR1_EE5POL_Pos        (26U)

+#define HRTIM_EECR1_EE5POL_Msk        (0x1UL << HRTIM_EECR1_EE5POL_Pos)        /*!< 0x04000000 */

+#define HRTIM_EECR1_EE5POL            HRTIM_EECR1_EE5POL_Msk                   /*!< External event 5 Polarity */

+#define HRTIM_EECR1_EE5SNS_Pos        (27U)

+#define HRTIM_EECR1_EE5SNS_Msk        (0x3UL << HRTIM_EECR1_EE5SNS_Pos)        /*!< 0x18000000 */

+#define HRTIM_EECR1_EE5SNS            HRTIM_EECR1_EE5SNS_Msk                   /*!< External event 5 sensitivity */

+#define HRTIM_EECR1_EE5SNS_0          (0x1UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x08000000 */

+#define HRTIM_EECR1_EE5SNS_1          (0x2UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x10000000 */

+#define HRTIM_EECR1_EE5FAST_Pos       (29U)

+#define HRTIM_EECR1_EE5FAST_Msk       (0x1UL << HRTIM_EECR1_EE5FAST_Pos)       /*!< 0x20000000 */

+#define HRTIM_EECR1_EE5FAST           HRTIM_EECR1_EE5FAST_Msk                  /*!< External event 5 Fast mode */

+

+/*******************  Bit definition for HRTIM_EECR2 register  ****************/

+#define HRTIM_EECR2_EE6SRC_Pos        (0U)

+#define HRTIM_EECR2_EE6SRC_Msk        (0x3UL << HRTIM_EECR2_EE6SRC_Pos)        /*!< 0x00000003 */

+#define HRTIM_EECR2_EE6SRC            HRTIM_EECR2_EE6SRC_Msk                   /*!< External event 6 source */

+#define HRTIM_EECR2_EE6SRC_0          (0x1UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000001 */

+#define HRTIM_EECR2_EE6SRC_1          (0x2UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000002 */

+#define HRTIM_EECR2_EE6POL_Pos        (2U)

+#define HRTIM_EECR2_EE6POL_Msk        (0x1UL << HRTIM_EECR2_EE6POL_Pos)        /*!< 0x00000004 */

+#define HRTIM_EECR2_EE6POL            HRTIM_EECR2_EE6POL_Msk                   /*!< External event 6 Polarity */

+#define HRTIM_EECR2_EE6SNS_Pos        (3U)

+#define HRTIM_EECR2_EE6SNS_Msk        (0x3UL << HRTIM_EECR2_EE6SNS_Pos)        /*!< 0x00000018 */

+#define HRTIM_EECR2_EE6SNS            HRTIM_EECR2_EE6SNS_Msk                   /*!< External event 6 sensitivity */

+#define HRTIM_EECR2_EE6SNS_0          (0x1UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000008 */

+#define HRTIM_EECR2_EE6SNS_1          (0x2UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000010 */

+

+#define HRTIM_EECR2_EE7SRC_Pos        (6U)

+#define HRTIM_EECR2_EE7SRC_Msk        (0x3UL << HRTIM_EECR2_EE7SRC_Pos)        /*!< 0x000000C0 */

+#define HRTIM_EECR2_EE7SRC            HRTIM_EECR2_EE7SRC_Msk                   /*!< External event 7 source */

+#define HRTIM_EECR2_EE7SRC_0          (0x1UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000040 */

+#define HRTIM_EECR2_EE7SRC_1          (0x2UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000080 */

+#define HRTIM_EECR2_EE7POL_Pos        (8U)

+#define HRTIM_EECR2_EE7POL_Msk        (0x1UL << HRTIM_EECR2_EE7POL_Pos)        /*!< 0x00000100 */

+#define HRTIM_EECR2_EE7POL            HRTIM_EECR2_EE7POL_Msk                   /*!< External event 7 Polarity */

+#define HRTIM_EECR2_EE7SNS_Pos        (9U)

+#define HRTIM_EECR2_EE7SNS_Msk        (0x3UL << HRTIM_EECR2_EE7SNS_Pos)        /*!< 0x00000600 */

+#define HRTIM_EECR2_EE7SNS            HRTIM_EECR2_EE7SNS_Msk                   /*!< External event 7 sensitivity */

+#define HRTIM_EECR2_EE7SNS_0          (0x1UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000200 */

+#define HRTIM_EECR2_EE7SNS_1          (0x2UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000400 */

+

+#define HRTIM_EECR2_EE8SRC_Pos        (12U)

+#define HRTIM_EECR2_EE8SRC_Msk        (0x3UL << HRTIM_EECR2_EE8SRC_Pos)        /*!< 0x00003000 */

+#define HRTIM_EECR2_EE8SRC            HRTIM_EECR2_EE8SRC_Msk                   /*!< External event 8 source */

+#define HRTIM_EECR2_EE8SRC_0          (0x1UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00001000 */

+#define HRTIM_EECR2_EE8SRC_1          (0x2UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00002000 */

+#define HRTIM_EECR2_EE8POL_Pos        (14U)

+#define HRTIM_EECR2_EE8POL_Msk        (0x1UL << HRTIM_EECR2_EE8POL_Pos)        /*!< 0x00004000 */

+#define HRTIM_EECR2_EE8POL            HRTIM_EECR2_EE8POL_Msk                   /*!< External event 8 Polarity */

+#define HRTIM_EECR2_EE8SNS_Pos        (15U)

+#define HRTIM_EECR2_EE8SNS_Msk        (0x3UL << HRTIM_EECR2_EE8SNS_Pos)        /*!< 0x00018000 */

+#define HRTIM_EECR2_EE8SNS            HRTIM_EECR2_EE8SNS_Msk                   /*!< External event 8 sensitivity */

+#define HRTIM_EECR2_EE8SNS_0          (0x1UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00008000 */

+#define HRTIM_EECR2_EE8SNS_1          (0x2UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00010000 */

+

+#define HRTIM_EECR2_EE9SRC_Pos        (18U)

+#define HRTIM_EECR2_EE9SRC_Msk        (0x3UL << HRTIM_EECR2_EE9SRC_Pos)        /*!< 0x000C0000 */

+#define HRTIM_EECR2_EE9SRC            HRTIM_EECR2_EE9SRC_Msk                   /*!< External event 9 source */

+#define HRTIM_EECR2_EE9SRC_0          (0x1UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00040000 */

+#define HRTIM_EECR2_EE9SRC_1          (0x2UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00080000 */

+#define HRTIM_EECR2_EE9POL_Pos        (20U)

+#define HRTIM_EECR2_EE9POL_Msk        (0x1UL << HRTIM_EECR2_EE9POL_Pos)        /*!< 0x00100000 */

+#define HRTIM_EECR2_EE9POL            HRTIM_EECR2_EE9POL_Msk                   /*!< External event 9 Polarity */

+#define HRTIM_EECR2_EE9SNS_Pos        (21U)

+#define HRTIM_EECR2_EE9SNS_Msk        (0x3UL << HRTIM_EECR2_EE9SNS_Pos)        /*!< 0x00600000 */

+#define HRTIM_EECR2_EE9SNS            HRTIM_EECR2_EE9SNS_Msk                   /*!< External event 9 sensitivity */

+#define HRTIM_EECR2_EE9SNS_0          (0x1UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00200000 */

+#define HRTIM_EECR2_EE9SNS_1          (0x2UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00400000 */

+

+#define HRTIM_EECR2_EE10SRC_Pos       (24U)

+#define HRTIM_EECR2_EE10SRC_Msk       (0x3UL << HRTIM_EECR2_EE10SRC_Pos)       /*!< 0x03000000 */

+#define HRTIM_EECR2_EE10SRC           HRTIM_EECR2_EE10SRC_Msk                  /*!< External event 10 source */

+#define HRTIM_EECR2_EE10SRC_0         (0x1UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x01000000 */

+#define HRTIM_EECR2_EE10SRC_1         (0x2UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x02000000 */

+#define HRTIM_EECR2_EE10POL_Pos       (26U)

+#define HRTIM_EECR2_EE10POL_Msk       (0x1UL << HRTIM_EECR2_EE10POL_Pos)       /*!< 0x04000000 */

+#define HRTIM_EECR2_EE10POL           HRTIM_EECR2_EE10POL_Msk                  /*!< External event 10 Polarity */

+#define HRTIM_EECR2_EE10SNS_Pos       (27U)

+#define HRTIM_EECR2_EE10SNS_Msk       (0x3UL << HRTIM_EECR2_EE10SNS_Pos)       /*!< 0x18000000 */

+#define HRTIM_EECR2_EE10SNS           HRTIM_EECR2_EE10SNS_Msk                  /*!< External event 10 sensitivity */

+#define HRTIM_EECR2_EE10SNS_0         (0x1UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x08000000 */

+#define HRTIM_EECR2_EE10SNS_1         (0x2UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x10000000 */

+

+/*******************  Bit definition for HRTIM_EECR3 register  ****************/

+#define HRTIM_EECR3_EE6F_Pos          (0U)

+#define HRTIM_EECR3_EE6F_Msk          (0xFUL << HRTIM_EECR3_EE6F_Pos)          /*!< 0x0000000F */

+#define HRTIM_EECR3_EE6F              HRTIM_EECR3_EE6F_Msk                     /*!< External event 6 filter */

+#define HRTIM_EECR3_EE6F_0            (0x1UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000001 */

+#define HRTIM_EECR3_EE6F_1            (0x2UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000002 */

+#define HRTIM_EECR3_EE6F_2            (0x4UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000004 */

+#define HRTIM_EECR3_EE6F_3            (0x8UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000008 */

+#define HRTIM_EECR3_EE7F_Pos          (6U)

+#define HRTIM_EECR3_EE7F_Msk          (0xFUL << HRTIM_EECR3_EE7F_Pos)          /*!< 0x000003C0 */

+#define HRTIM_EECR3_EE7F              HRTIM_EECR3_EE7F_Msk                     /*!< External event 7 filter */

+#define HRTIM_EECR3_EE7F_0            (0x1UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000040 */

+#define HRTIM_EECR3_EE7F_1            (0x2UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000080 */

+#define HRTIM_EECR3_EE7F_2            (0x4UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000100 */

+#define HRTIM_EECR3_EE7F_3            (0x8UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000200 */

+#define HRTIM_EECR3_EE8F_Pos          (12U)

+#define HRTIM_EECR3_EE8F_Msk          (0xFUL << HRTIM_EECR3_EE8F_Pos)          /*!< 0x0000F000 */

+#define HRTIM_EECR3_EE8F              HRTIM_EECR3_EE8F_Msk                     /*!< External event 8 filter */

+#define HRTIM_EECR3_EE8F_0            (0x1UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00001000 */

+#define HRTIM_EECR3_EE8F_1            (0x2UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00002000 */

+#define HRTIM_EECR3_EE8F_2            (0x4UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00004000 */

+#define HRTIM_EECR3_EE8F_3            (0x8UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00008000 */

+#define HRTIM_EECR3_EE9F_Pos          (18U)

+#define HRTIM_EECR3_EE9F_Msk          (0xFUL << HRTIM_EECR3_EE9F_Pos)          /*!< 0x003C0000 */

+#define HRTIM_EECR3_EE9F              HRTIM_EECR3_EE9F_Msk                     /*!< External event 9 filter */

+#define HRTIM_EECR3_EE9F_0            (0x1UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00040000 */

+#define HRTIM_EECR3_EE9F_1            (0x2UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00080000 */

+#define HRTIM_EECR3_EE9F_2            (0x4UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00100000 */

+#define HRTIM_EECR3_EE9F_3            (0x8UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00200000 */

+#define HRTIM_EECR3_EE10F_Pos         (24U)

+#define HRTIM_EECR3_EE10F_Msk         (0xFUL << HRTIM_EECR3_EE10F_Pos)         /*!< 0x0F000000 */

+#define HRTIM_EECR3_EE10F             HRTIM_EECR3_EE10F_Msk                    /*!< External event 10 filter */

+#define HRTIM_EECR3_EE10F_0           (0x1UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x01000000 */

+#define HRTIM_EECR3_EE10F_1           (0x2UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x02000000 */

+#define HRTIM_EECR3_EE10F_2           (0x4UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x04000000 */

+#define HRTIM_EECR3_EE10F_3           (0x8UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x08000000 */

+#define HRTIM_EECR3_EEVSD_Pos         (30U)

+#define HRTIM_EECR3_EEVSD_Msk         (0x3UL << HRTIM_EECR3_EEVSD_Pos)         /*!< 0xC0000000 */

+#define HRTIM_EECR3_EEVSD             HRTIM_EECR3_EEVSD_Msk                    /*!< External event sampling clock division */

+#define HRTIM_EECR3_EEVSD_0           (0x1UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x40000000 */

+#define HRTIM_EECR3_EEVSD_1           (0x2UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x80000000 */

+

+/*******************  Bit definition for HRTIM_ADC1R register  ****************/

+#define HRTIM_ADC1R_AD1MC1_Pos        (0U)

+#define HRTIM_ADC1R_AD1MC1_Msk        (0x1UL << HRTIM_ADC1R_AD1MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC1R_AD1MC1            HRTIM_ADC1R_AD1MC1_Msk                   /*!< ADC Trigger 1 on master compare 1 */

+#define HRTIM_ADC1R_AD1MC2_Pos        (1U)

+#define HRTIM_ADC1R_AD1MC2_Msk        (0x1UL << HRTIM_ADC1R_AD1MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC1R_AD1MC2            HRTIM_ADC1R_AD1MC2_Msk                   /*!< ADC Trigger 1 on master compare 2 */

+#define HRTIM_ADC1R_AD1MC3_Pos        (2U)

+#define HRTIM_ADC1R_AD1MC3_Msk        (0x1UL << HRTIM_ADC1R_AD1MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC1R_AD1MC3            HRTIM_ADC1R_AD1MC3_Msk                   /*!< ADC Trigger 1 on master compare 3 */

+#define HRTIM_ADC1R_AD1MC4_Pos        (3U)

+#define HRTIM_ADC1R_AD1MC4_Msk        (0x1UL << HRTIM_ADC1R_AD1MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC1R_AD1MC4            HRTIM_ADC1R_AD1MC4_Msk                   /*!< ADC Trigger 1 on master compare 4 */

+#define HRTIM_ADC1R_AD1MPER_Pos       (4U)

+#define HRTIM_ADC1R_AD1MPER_Msk       (0x1UL << HRTIM_ADC1R_AD1MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC1R_AD1MPER           HRTIM_ADC1R_AD1MPER_Msk                  /*!< ADC Trigger 1 on master period */

+#define HRTIM_ADC1R_AD1EEV1_Pos       (5U)

+#define HRTIM_ADC1R_AD1EEV1_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC1R_AD1EEV1           HRTIM_ADC1R_AD1EEV1_Msk                  /*!< ADC Trigger 1 on external event 1 */

+#define HRTIM_ADC1R_AD1EEV2_Pos       (6U)

+#define HRTIM_ADC1R_AD1EEV2_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC1R_AD1EEV2           HRTIM_ADC1R_AD1EEV2_Msk                  /*!< ADC Trigger 1 on external event 2 */

+#define HRTIM_ADC1R_AD1EEV3_Pos       (7U)

+#define HRTIM_ADC1R_AD1EEV3_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC1R_AD1EEV3           HRTIM_ADC1R_AD1EEV3_Msk                  /*!< ADC Trigger 1 on external event 3 */

+#define HRTIM_ADC1R_AD1EEV4_Pos       (8U)

+#define HRTIM_ADC1R_AD1EEV4_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC1R_AD1EEV4           HRTIM_ADC1R_AD1EEV4_Msk                  /*!< ADC Trigger 1 on external event 4 */

+#define HRTIM_ADC1R_AD1EEV5_Pos       (9U)

+#define HRTIM_ADC1R_AD1EEV5_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos)       /*!< 0x00000200 */

+#define HRTIM_ADC1R_AD1EEV5           HRTIM_ADC1R_AD1EEV5_Msk                  /*!< ADC Trigger 1 on external event 5 */

+#define HRTIM_ADC1R_AD1TAC2_Pos       (10U)

+#define HRTIM_ADC1R_AD1TAC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC1R_AD1TAC2           HRTIM_ADC1R_AD1TAC2_Msk                  /*!< ADC Trigger 1 on Timer A compare 2 */

+#define HRTIM_ADC1R_AD1TAC3_Pos       (11U)

+#define HRTIM_ADC1R_AD1TAC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC1R_AD1TAC3           HRTIM_ADC1R_AD1TAC3_Msk                  /*!< ADC Trigger 1 on Timer A compare 3 */

+#define HRTIM_ADC1R_AD1TAC4_Pos       (12U)

+#define HRTIM_ADC1R_AD1TAC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC1R_AD1TAC4           HRTIM_ADC1R_AD1TAC4_Msk                  /*!< ADC Trigger 1 on Timer A compare 4 */

+#define HRTIM_ADC1R_AD1TAPER_Pos      (13U)

+#define HRTIM_ADC1R_AD1TAPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC1R_AD1TAPER          HRTIM_ADC1R_AD1TAPER_Msk                 /*!< ADC Trigger 1 on Timer A period */

+#define HRTIM_ADC1R_AD1TARST_Pos      (14U)

+#define HRTIM_ADC1R_AD1TARST_Msk      (0x1UL << HRTIM_ADC1R_AD1TARST_Pos)      /*!< 0x00004000 */

+#define HRTIM_ADC1R_AD1TARST          HRTIM_ADC1R_AD1TARST_Msk                 /*!< ADC Trigger 1 on Timer A reset */

+#define HRTIM_ADC1R_AD1TBC2_Pos       (15U)

+#define HRTIM_ADC1R_AD1TBC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC2_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC1R_AD1TBC2           HRTIM_ADC1R_AD1TBC2_Msk                  /*!< ADC Trigger 1 on Timer B compare 2 */

+#define HRTIM_ADC1R_AD1TBC3_Pos       (16U)

+#define HRTIM_ADC1R_AD1TBC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC1R_AD1TBC3           HRTIM_ADC1R_AD1TBC3_Msk                  /*!< ADC Trigger 1 on Timer B compare 3 */

+#define HRTIM_ADC1R_AD1TBC4_Pos       (17U)

+#define HRTIM_ADC1R_AD1TBC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos)       /*!< 0x00020000 */

+#define HRTIM_ADC1R_AD1TBC4           HRTIM_ADC1R_AD1TBC4_Msk                  /*!< ADC Trigger 1 on Timer B compare 4 */

+#define HRTIM_ADC1R_AD1TBPER_Pos      (18U)

+#define HRTIM_ADC1R_AD1TBPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos)      /*!< 0x00040000 */

+#define HRTIM_ADC1R_AD1TBPER          HRTIM_ADC1R_AD1TBPER_Msk                 /*!< ADC Trigger 1 on Timer B period */

+#define HRTIM_ADC1R_AD1TBRST_Pos      (19U)

+#define HRTIM_ADC1R_AD1TBRST_Msk      (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos)      /*!< 0x00080000 */

+#define HRTIM_ADC1R_AD1TBRST          HRTIM_ADC1R_AD1TBRST_Msk                 /*!< ADC Trigger 1 on Timer B reset */

+#define HRTIM_ADC1R_AD1TCC2_Pos       (20U)

+#define HRTIM_ADC1R_AD1TCC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC2_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC1R_AD1TCC2           HRTIM_ADC1R_AD1TCC2_Msk                  /*!< ADC Trigger 1 on Timer C compare 2 */

+#define HRTIM_ADC1R_AD1TCC3_Pos       (21U)

+#define HRTIM_ADC1R_AD1TCC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos)       /*!< 0x00200000 */

+#define HRTIM_ADC1R_AD1TCC3           HRTIM_ADC1R_AD1TCC3_Msk                  /*!< ADC Trigger 1 on Timer C compare 3 */

+#define HRTIM_ADC1R_AD1TCC4_Pos       (22U)

+#define HRTIM_ADC1R_AD1TCC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos)       /*!< 0x00400000 */

+#define HRTIM_ADC1R_AD1TCC4           HRTIM_ADC1R_AD1TCC4_Msk                  /*!< ADC Trigger 1 on Timer C compare 4 */

+#define HRTIM_ADC1R_AD1TCPER_Pos      (23U)

+#define HRTIM_ADC1R_AD1TCPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos)      /*!< 0x00800000 */

+#define HRTIM_ADC1R_AD1TCPER          HRTIM_ADC1R_AD1TCPER_Msk                 /*!< ADC Trigger 1 on Timer C period */

+#define HRTIM_ADC1R_AD1TDC2_Pos       (24U)

+#define HRTIM_ADC1R_AD1TDC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC2_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC1R_AD1TDC2           HRTIM_ADC1R_AD1TDC2_Msk                  /*!< ADC Trigger 1 on Timer D compare 2 */

+#define HRTIM_ADC1R_AD1TDC3_Pos       (25U)

+#define HRTIM_ADC1R_AD1TDC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC1R_AD1TDC3           HRTIM_ADC1R_AD1TDC3_Msk                  /*!< ADC Trigger 1 on Timer D compare 3 */

+#define HRTIM_ADC1R_AD1TDC4_Pos       (26U)

+#define HRTIM_ADC1R_AD1TDC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos)       /*!< 0x04000000 */

+#define HRTIM_ADC1R_AD1TDC4           HRTIM_ADC1R_AD1TDC4_Msk                  /*!< ADC Trigger 1 on Timer D compare 4 */

+#define HRTIM_ADC1R_AD1TDPER_Pos      (27U)

+#define HRTIM_ADC1R_AD1TDPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC1R_AD1TDPER          HRTIM_ADC1R_AD1TDPER_Msk                 /*!< ADC Trigger 1 on Timer D period */

+#define HRTIM_ADC1R_AD1TEC2_Pos       (28U)

+#define HRTIM_ADC1R_AD1TEC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC1R_AD1TEC2           HRTIM_ADC1R_AD1TEC2_Msk                  /*!< ADC Trigger 1 on Timer E compare 2 */

+#define HRTIM_ADC1R_AD1TEC3_Pos       (29U)

+#define HRTIM_ADC1R_AD1TEC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC1R_AD1TEC3           HRTIM_ADC1R_AD1TEC3_Msk                  /*!< ADC Trigger 1 on Timer E compare 3 */

+#define HRTIM_ADC1R_AD1TEC4_Pos       (30U)

+#define HRTIM_ADC1R_AD1TEC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC1R_AD1TEC4           HRTIM_ADC1R_AD1TEC4_Msk                  /*!< ADC Trigger 1 on Timer E compare 4 */

+#define HRTIM_ADC1R_AD1TEPER_Pos      (31U)

+#define HRTIM_ADC1R_AD1TEPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC1R_AD1TEPER          HRTIM_ADC1R_AD1TEPER_Msk                 /*!< ADC Trigger 1 on Timer E period */

+

+/*******************  Bit definition for HRTIM_ADC2R register  ****************/

+#define HRTIM_ADC2R_AD2MC1_Pos        (0U)

+#define HRTIM_ADC2R_AD2MC1_Msk        (0x1UL << HRTIM_ADC2R_AD2MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC2R_AD2MC1            HRTIM_ADC2R_AD2MC1_Msk                   /*!< ADC Trigger 2 on master compare 1 */

+#define HRTIM_ADC2R_AD2MC2_Pos        (1U)

+#define HRTIM_ADC2R_AD2MC2_Msk        (0x1UL << HRTIM_ADC2R_AD2MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC2R_AD2MC2            HRTIM_ADC2R_AD2MC2_Msk                   /*!< ADC Trigger 2 on master compare 2 */

+#define HRTIM_ADC2R_AD2MC3_Pos        (2U)

+#define HRTIM_ADC2R_AD2MC3_Msk        (0x1UL << HRTIM_ADC2R_AD2MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC2R_AD2MC3            HRTIM_ADC2R_AD2MC3_Msk                   /*!< ADC Trigger 2 on master compare 3 */

+#define HRTIM_ADC2R_AD2MC4_Pos        (3U)

+#define HRTIM_ADC2R_AD2MC4_Msk        (0x1UL << HRTIM_ADC2R_AD2MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC2R_AD2MC4            HRTIM_ADC2R_AD2MC4_Msk                   /*!< ADC Trigger 2 on master compare 4 */

+#define HRTIM_ADC2R_AD2MPER_Pos       (4U)

+#define HRTIM_ADC2R_AD2MPER_Msk       (0x1UL << HRTIM_ADC2R_AD2MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC2R_AD2MPER           HRTIM_ADC2R_AD2MPER_Msk                  /*!< ADC Trigger 2 on master period */

+#define HRTIM_ADC2R_AD2EEV6_Pos       (5U)

+#define HRTIM_ADC2R_AD2EEV6_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC2R_AD2EEV6           HRTIM_ADC2R_AD2EEV6_Msk                  /*!< ADC Trigger 2 on external event 6 */

+#define HRTIM_ADC2R_AD2EEV7_Pos       (6U)

+#define HRTIM_ADC2R_AD2EEV7_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC2R_AD2EEV7           HRTIM_ADC2R_AD2EEV7_Msk                  /*!< ADC Trigger 2 on external event 7 */

+#define HRTIM_ADC2R_AD2EEV8_Pos       (7U)

+#define HRTIM_ADC2R_AD2EEV8_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC2R_AD2EEV8           HRTIM_ADC2R_AD2EEV8_Msk                  /*!< ADC Trigger 2 on external event 8 */

+#define HRTIM_ADC2R_AD2EEV9_Pos       (8U)

+#define HRTIM_ADC2R_AD2EEV9_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC2R_AD2EEV9           HRTIM_ADC2R_AD2EEV9_Msk                  /*!< ADC Trigger 2 on external event 9 */

+#define HRTIM_ADC2R_AD2EEV10_Pos      (9U)

+#define HRTIM_ADC2R_AD2EEV10_Msk      (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos)      /*!< 0x00000200 */

+#define HRTIM_ADC2R_AD2EEV10          HRTIM_ADC2R_AD2EEV10_Msk                 /*!< ADC Trigger 2 on external event 10 */

+#define HRTIM_ADC2R_AD2TAC2_Pos       (10U)

+#define HRTIM_ADC2R_AD2TAC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC2R_AD2TAC2           HRTIM_ADC2R_AD2TAC2_Msk                  /*!< ADC Trigger 2 on Timer A compare 2 */

+#define HRTIM_ADC2R_AD2TAC3_Pos       (11U)

+#define HRTIM_ADC2R_AD2TAC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC2R_AD2TAC3           HRTIM_ADC2R_AD2TAC3_Msk                  /*!< ADC Trigger 2 on Timer A compare 3 */

+#define HRTIM_ADC2R_AD2TAC4_Pos       (12U)

+#define HRTIM_ADC2R_AD2TAC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC2R_AD2TAC4           HRTIM_ADC2R_AD2TAC4_Msk                  /*!< ADC Trigger 2 on Timer A compare 4*/

+#define HRTIM_ADC2R_AD2TAPER_Pos      (13U)

+#define HRTIM_ADC2R_AD2TAPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC2R_AD2TAPER          HRTIM_ADC2R_AD2TAPER_Msk                 /*!< ADC Trigger 2 on Timer A period */

+#define HRTIM_ADC2R_AD2TBC2_Pos       (14U)

+#define HRTIM_ADC2R_AD2TBC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos)       /*!< 0x00004000 */

+#define HRTIM_ADC2R_AD2TBC2           HRTIM_ADC2R_AD2TBC2_Msk                  /*!< ADC Trigger 2 on Timer B compare 2 */

+#define HRTIM_ADC2R_AD2TBC3_Pos       (15U)

+#define HRTIM_ADC2R_AD2TBC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC3_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC2R_AD2TBC3           HRTIM_ADC2R_AD2TBC3_Msk                  /*!< ADC Trigger 2 on Timer B compare 3 */

+#define HRTIM_ADC2R_AD2TBC4_Pos       (16U)

+#define HRTIM_ADC2R_AD2TBC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC2R_AD2TBC4           HRTIM_ADC2R_AD2TBC4_Msk                  /*!< ADC Trigger 2 on Timer B compare 4 */

+#define HRTIM_ADC2R_AD2TBPER_Pos      (17U)

+#define HRTIM_ADC2R_AD2TBPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos)      /*!< 0x00020000 */

+#define HRTIM_ADC2R_AD2TBPER          HRTIM_ADC2R_AD2TBPER_Msk                 /*!< ADC Trigger 2 on Timer B period */

+#define HRTIM_ADC2R_AD2TCC2_Pos       (18U)

+#define HRTIM_ADC2R_AD2TCC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos)       /*!< 0x00040000 */

+#define HRTIM_ADC2R_AD2TCC2           HRTIM_ADC2R_AD2TCC2_Msk                  /*!< ADC Trigger 2 on Timer C compare 2 */

+#define HRTIM_ADC2R_AD2TCC3_Pos       (19U)

+#define HRTIM_ADC2R_AD2TCC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC3_Pos)       /*!< 0x00080000 */

+#define HRTIM_ADC2R_AD2TCC3           HRTIM_ADC2R_AD2TCC3_Msk                  /*!< ADC Trigger 2 on Timer C compare 3 */

+#define HRTIM_ADC2R_AD2TCC4_Pos       (20U)

+#define HRTIM_ADC2R_AD2TCC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC2R_AD2TCC4           HRTIM_ADC2R_AD2TCC4_Msk                  /*!< ADC Trigger 2 on Timer C compare 4 */

+#define HRTIM_ADC2R_AD2TCPER_Pos      (21U)

+#define HRTIM_ADC2R_AD2TCPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos)      /*!< 0x00200000 */

+#define HRTIM_ADC2R_AD2TCPER          HRTIM_ADC2R_AD2TCPER_Msk                 /*!< ADC Trigger 2 on Timer C period */

+#define HRTIM_ADC2R_AD2TCRST_Pos      (22U)

+#define HRTIM_ADC2R_AD2TCRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos)      /*!< 0x00400000 */

+#define HRTIM_ADC2R_AD2TCRST          HRTIM_ADC2R_AD2TCRST_Msk                 /*!< ADC Trigger 2 on Timer C reset */

+#define HRTIM_ADC2R_AD2TDC2_Pos       (23U)

+#define HRTIM_ADC2R_AD2TDC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos)       /*!< 0x00800000 */

+#define HRTIM_ADC2R_AD2TDC2           HRTIM_ADC2R_AD2TDC2_Msk                  /*!< ADC Trigger 2 on Timer D compare 2 */

+#define HRTIM_ADC2R_AD2TDC3_Pos       (24U)

+#define HRTIM_ADC2R_AD2TDC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC3_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC2R_AD2TDC3           HRTIM_ADC2R_AD2TDC3_Msk                  /*!< ADC Trigger 2 on Timer D compare 3 */

+#define HRTIM_ADC2R_AD2TDC4_Pos       (25U)

+#define HRTIM_ADC2R_AD2TDC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC2R_AD2TDC4           HRTIM_ADC2R_AD2TDC4_Msk                  /*!< ADC Trigger 2 on Timer D compare 4*/

+#define HRTIM_ADC2R_AD2TDPER_Pos      (26U)

+#define HRTIM_ADC2R_AD2TDPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos)      /*!< 0x04000000 */

+#define HRTIM_ADC2R_AD2TDPER          HRTIM_ADC2R_AD2TDPER_Msk                 /*!< ADC Trigger 2 on Timer D period */

+#define HRTIM_ADC2R_AD2TDRST_Pos      (27U)

+#define HRTIM_ADC2R_AD2TDRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC2R_AD2TDRST          HRTIM_ADC2R_AD2TDRST_Msk                 /*!< ADC Trigger 2 on Timer D reset */

+#define HRTIM_ADC2R_AD2TEC2_Pos       (28U)

+#define HRTIM_ADC2R_AD2TEC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC2R_AD2TEC2           HRTIM_ADC2R_AD2TEC2_Msk                  /*!< ADC Trigger 2 on Timer E compare 2 */

+#define HRTIM_ADC2R_AD2TEC3_Pos       (29U)

+#define HRTIM_ADC2R_AD2TEC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC2R_AD2TEC3           HRTIM_ADC2R_AD2TEC3_Msk                  /*!< ADC Trigger 2 on Timer E compare 3 */

+#define HRTIM_ADC2R_AD2TEC4_Pos       (30U)

+#define HRTIM_ADC2R_AD2TEC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC2R_AD2TEC4           HRTIM_ADC2R_AD2TEC4_Msk                  /*!< ADC Trigger 2 on Timer E compare 4 */

+#define HRTIM_ADC2R_AD2TERST_Pos      (31U)

+#define HRTIM_ADC2R_AD2TERST_Msk      (0x1UL << HRTIM_ADC2R_AD2TERST_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC2R_AD2TERST          HRTIM_ADC2R_AD2TERST_Msk                 /*!< ADC Trigger 2 on Timer E reset */

+

+/*******************  Bit definition for HRTIM_ADC3R register  ****************/

+#define HRTIM_ADC3R_AD3MC1_Pos        (0U)

+#define HRTIM_ADC3R_AD3MC1_Msk        (0x1UL << HRTIM_ADC3R_AD3MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC3R_AD3MC1            HRTIM_ADC3R_AD3MC1_Msk                   /*!< ADC Trigger 3 on master compare 1 */

+#define HRTIM_ADC3R_AD3MC2_Pos        (1U)

+#define HRTIM_ADC3R_AD3MC2_Msk        (0x1UL << HRTIM_ADC3R_AD3MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC3R_AD3MC2            HRTIM_ADC3R_AD3MC2_Msk                   /*!< ADC Trigger 3 on master compare 2 */

+#define HRTIM_ADC3R_AD3MC3_Pos        (2U)

+#define HRTIM_ADC3R_AD3MC3_Msk        (0x1UL << HRTIM_ADC3R_AD3MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC3R_AD3MC3            HRTIM_ADC3R_AD3MC3_Msk                   /*!< ADC Trigger 3 on master compare 3 */

+#define HRTIM_ADC3R_AD3MC4_Pos        (3U)

+#define HRTIM_ADC3R_AD3MC4_Msk        (0x1UL << HRTIM_ADC3R_AD3MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC3R_AD3MC4            HRTIM_ADC3R_AD3MC4_Msk                   /*!< ADC Trigger 3 on master compare 4 */

+#define HRTIM_ADC3R_AD3MPER_Pos       (4U)

+#define HRTIM_ADC3R_AD3MPER_Msk       (0x1UL << HRTIM_ADC3R_AD3MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC3R_AD3MPER           HRTIM_ADC3R_AD3MPER_Msk                  /*!< ADC Trigger 3 on master period */

+#define HRTIM_ADC3R_AD3EEV1_Pos       (5U)

+#define HRTIM_ADC3R_AD3EEV1_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC3R_AD3EEV1           HRTIM_ADC3R_AD3EEV1_Msk                  /*!< ADC Trigger 3 on external event 1 */

+#define HRTIM_ADC3R_AD3EEV2_Pos       (6U)

+#define HRTIM_ADC3R_AD3EEV2_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC3R_AD3EEV2           HRTIM_ADC3R_AD3EEV2_Msk                  /*!< ADC Trigger 3 on external event 2 */

+#define HRTIM_ADC3R_AD3EEV3_Pos       (7U)

+#define HRTIM_ADC3R_AD3EEV3_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC3R_AD3EEV3           HRTIM_ADC3R_AD3EEV3_Msk                  /*!< ADC Trigger 3 on external event 3 */

+#define HRTIM_ADC3R_AD3EEV4_Pos       (8U)

+#define HRTIM_ADC3R_AD3EEV4_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC3R_AD3EEV4           HRTIM_ADC3R_AD3EEV4_Msk                  /*!< ADC Trigger 3 on external event 4 */

+#define HRTIM_ADC3R_AD3EEV5_Pos       (9U)

+#define HRTIM_ADC3R_AD3EEV5_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos)       /*!< 0x00000200 */

+#define HRTIM_ADC3R_AD3EEV5           HRTIM_ADC3R_AD3EEV5_Msk                  /*!< ADC Trigger 3 on external event 5 */

+#define HRTIM_ADC3R_AD3TAC2_Pos       (10U)

+#define HRTIM_ADC3R_AD3TAC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC3R_AD3TAC2           HRTIM_ADC3R_AD3TAC2_Msk                  /*!< ADC Trigger 3 on Timer A compare 2 */

+#define HRTIM_ADC3R_AD3TAC3_Pos       (11U)

+#define HRTIM_ADC3R_AD3TAC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC3R_AD3TAC3           HRTIM_ADC3R_AD3TAC3_Msk                  /*!< ADC Trigger 3 on Timer A compare 3 */

+#define HRTIM_ADC3R_AD3TAC4_Pos       (12U)

+#define HRTIM_ADC3R_AD3TAC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC3R_AD3TAC4           HRTIM_ADC3R_AD3TAC4_Msk                  /*!< ADC Trigger 3 on Timer A compare 4 */

+#define HRTIM_ADC3R_AD3TAPER_Pos      (13U)

+#define HRTIM_ADC3R_AD3TAPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC3R_AD3TAPER          HRTIM_ADC3R_AD3TAPER_Msk                 /*!< ADC Trigger 3 on Timer A period */

+#define HRTIM_ADC3R_AD3TARST_Pos      (14U)

+#define HRTIM_ADC3R_AD3TARST_Msk      (0x1UL << HRTIM_ADC3R_AD3TARST_Pos)      /*!< 0x00004000 */

+#define HRTIM_ADC3R_AD3TARST          HRTIM_ADC3R_AD3TARST_Msk                 /*!< ADC Trigger 3 on Timer A reset */

+#define HRTIM_ADC3R_AD3TBC2_Pos       (15U)

+#define HRTIM_ADC3R_AD3TBC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC2_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC3R_AD3TBC2           HRTIM_ADC3R_AD3TBC2_Msk                  /*!< ADC Trigger 3 on Timer B compare 2 */

+#define HRTIM_ADC3R_AD3TBC3_Pos       (16U)

+#define HRTIM_ADC3R_AD3TBC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC3R_AD3TBC3           HRTIM_ADC3R_AD3TBC3_Msk                  /*!< ADC Trigger 3 on Timer B compare 3 */

+#define HRTIM_ADC3R_AD3TBC4_Pos       (17U)

+#define HRTIM_ADC3R_AD3TBC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos)       /*!< 0x00020000 */

+#define HRTIM_ADC3R_AD3TBC4           HRTIM_ADC3R_AD3TBC4_Msk                  /*!< ADC Trigger 3 on Timer B compare 4 */

+#define HRTIM_ADC3R_AD3TBPER_Pos      (18U)

+#define HRTIM_ADC3R_AD3TBPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos)      /*!< 0x00040000 */

+#define HRTIM_ADC3R_AD3TBPER          HRTIM_ADC3R_AD3TBPER_Msk                 /*!< ADC Trigger 3 on Timer B period */

+#define HRTIM_ADC3R_AD3TBRST_Pos      (19U)

+#define HRTIM_ADC3R_AD3TBRST_Msk      (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos)      /*!< 0x00080000 */

+#define HRTIM_ADC3R_AD3TBRST          HRTIM_ADC3R_AD3TBRST_Msk                 /*!< ADC Trigger 3 on Timer B reset */

+#define HRTIM_ADC3R_AD3TCC2_Pos       (20U)

+#define HRTIM_ADC3R_AD3TCC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC2_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC3R_AD3TCC2           HRTIM_ADC3R_AD3TCC2_Msk                  /*!< ADC Trigger 3 on Timer C compare 2 */

+#define HRTIM_ADC3R_AD3TCC3_Pos       (21U)

+#define HRTIM_ADC3R_AD3TCC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos)       /*!< 0x00200000 */

+#define HRTIM_ADC3R_AD3TCC3           HRTIM_ADC3R_AD3TCC3_Msk                  /*!< ADC Trigger 3 on Timer C compare 3 */

+#define HRTIM_ADC3R_AD3TCC4_Pos       (22U)

+#define HRTIM_ADC3R_AD3TCC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos)       /*!< 0x00400000 */

+#define HRTIM_ADC3R_AD3TCC4           HRTIM_ADC3R_AD3TCC4_Msk                  /*!< ADC Trigger 3 on Timer C compare 4 */

+#define HRTIM_ADC3R_AD3TCPER_Pos      (23U)

+#define HRTIM_ADC3R_AD3TCPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos)      /*!< 0x00800000 */

+#define HRTIM_ADC3R_AD3TCPER          HRTIM_ADC3R_AD3TCPER_Msk                 /*!< ADC Trigger 3 on Timer C period */

+#define HRTIM_ADC3R_AD3TDC2_Pos       (24U)

+#define HRTIM_ADC3R_AD3TDC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC2_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC3R_AD3TDC2           HRTIM_ADC3R_AD3TDC2_Msk                  /*!< ADC Trigger 3 on Timer D compare 2 */

+#define HRTIM_ADC3R_AD3TDC3_Pos       (25U)

+#define HRTIM_ADC3R_AD3TDC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC3R_AD3TDC3           HRTIM_ADC3R_AD3TDC3_Msk                  /*!< ADC Trigger 3 on Timer D compare 3 */

+#define HRTIM_ADC3R_AD3TDC4_Pos       (26U)

+#define HRTIM_ADC3R_AD3TDC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos)       /*!< 0x04000000 */

+#define HRTIM_ADC3R_AD3TDC4           HRTIM_ADC3R_AD3TDC4_Msk                  /*!< ADC Trigger 3 on Timer D compare 4 */

+#define HRTIM_ADC3R_AD3TDPER_Pos      (27U)

+#define HRTIM_ADC3R_AD3TDPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC3R_AD3TDPER          HRTIM_ADC3R_AD3TDPER_Msk                 /*!< ADC Trigger 3 on Timer D period */

+#define HRTIM_ADC3R_AD3TEC2_Pos       (28U)

+#define HRTIM_ADC3R_AD3TEC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC3R_AD3TEC2           HRTIM_ADC3R_AD3TEC2_Msk                  /*!< ADC Trigger 3 on Timer E compare 2 */

+#define HRTIM_ADC3R_AD3TEC3_Pos       (29U)

+#define HRTIM_ADC3R_AD3TEC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC3R_AD3TEC3           HRTIM_ADC3R_AD3TEC3_Msk                  /*!< ADC Trigger 3 on Timer E compare 3 */

+#define HRTIM_ADC3R_AD3TEC4_Pos       (30U)

+#define HRTIM_ADC3R_AD3TEC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC3R_AD3TEC4           HRTIM_ADC3R_AD3TEC4_Msk                  /*!< ADC Trigger 3 on Timer E compare 4 */

+#define HRTIM_ADC3R_AD3TEPER_Pos      (31U)

+#define HRTIM_ADC3R_AD3TEPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC3R_AD3TEPER          HRTIM_ADC3R_AD3TEPER_Msk                 /*!< ADC Trigger 3 on Timer E period */

+

+/*******************  Bit definition for HRTIM_ADC4R register  ****************/

+#define HRTIM_ADC4R_AD4MC1_Pos        (0U)

+#define HRTIM_ADC4R_AD4MC1_Msk        (0x1UL << HRTIM_ADC4R_AD4MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC4R_AD4MC1            HRTIM_ADC4R_AD4MC1_Msk                   /*!< ADC Trigger 4 on master compare 1 */

+#define HRTIM_ADC4R_AD4MC2_Pos        (1U)

+#define HRTIM_ADC4R_AD4MC2_Msk        (0x1UL << HRTIM_ADC4R_AD4MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC4R_AD4MC2            HRTIM_ADC4R_AD4MC2_Msk                   /*!< ADC Trigger 4 on master compare 2 */

+#define HRTIM_ADC4R_AD4MC3_Pos        (2U)

+#define HRTIM_ADC4R_AD4MC3_Msk        (0x1UL << HRTIM_ADC4R_AD4MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC4R_AD4MC3            HRTIM_ADC4R_AD4MC3_Msk                   /*!< ADC Trigger 4 on master compare 3 */

+#define HRTIM_ADC4R_AD4MC4_Pos        (3U)

+#define HRTIM_ADC4R_AD4MC4_Msk        (0x1UL << HRTIM_ADC4R_AD4MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC4R_AD4MC4            HRTIM_ADC4R_AD4MC4_Msk                   /*!< ADC Trigger 4 on master compare 4 */

+#define HRTIM_ADC4R_AD4MPER_Pos       (4U)

+#define HRTIM_ADC4R_AD4MPER_Msk       (0x1UL << HRTIM_ADC4R_AD4MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC4R_AD4MPER           HRTIM_ADC4R_AD4MPER_Msk                  /*!< ADC Trigger 4 on master period */

+#define HRTIM_ADC4R_AD4EEV6_Pos       (5U)

+#define HRTIM_ADC4R_AD4EEV6_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC4R_AD4EEV6           HRTIM_ADC4R_AD4EEV6_Msk                  /*!< ADC Trigger 4 on external event 6 */

+#define HRTIM_ADC4R_AD4EEV7_Pos       (6U)

+#define HRTIM_ADC4R_AD4EEV7_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC4R_AD4EEV7           HRTIM_ADC4R_AD4EEV7_Msk                  /*!< ADC Trigger 4 on external event 7 */

+#define HRTIM_ADC4R_AD4EEV8_Pos       (7U)

+#define HRTIM_ADC4R_AD4EEV8_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC4R_AD4EEV8           HRTIM_ADC4R_AD4EEV8_Msk                  /*!< ADC Trigger 4 on external event 8 */

+#define HRTIM_ADC4R_AD4EEV9_Pos       (8U)

+#define HRTIM_ADC4R_AD4EEV9_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC4R_AD4EEV9           HRTIM_ADC4R_AD4EEV9_Msk                  /*!< ADC Trigger 4 on external event 9 */

+#define HRTIM_ADC4R_AD4EEV10_Pos      (9U)

+#define HRTIM_ADC4R_AD4EEV10_Msk      (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos)      /*!< 0x00000200 */

+#define HRTIM_ADC4R_AD4EEV10          HRTIM_ADC4R_AD4EEV10_Msk                 /*!< ADC Trigger 4 on external event 10 */

+#define HRTIM_ADC4R_AD4TAC2_Pos       (10U)

+#define HRTIM_ADC4R_AD4TAC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC4R_AD4TAC2           HRTIM_ADC4R_AD4TAC2_Msk                  /*!< ADC Trigger 4 on Timer A compare 2 */

+#define HRTIM_ADC4R_AD4TAC3_Pos       (11U)

+#define HRTIM_ADC4R_AD4TAC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC4R_AD4TAC3           HRTIM_ADC4R_AD4TAC3_Msk                  /*!< ADC Trigger 4 on Timer A compare 3 */

+#define HRTIM_ADC4R_AD4TAC4_Pos       (12U)

+#define HRTIM_ADC4R_AD4TAC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC4R_AD4TAC4           HRTIM_ADC4R_AD4TAC4_Msk                  /*!< ADC Trigger 4 on Timer A compare 4*/

+#define HRTIM_ADC4R_AD4TAPER_Pos      (13U)

+#define HRTIM_ADC4R_AD4TAPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC4R_AD4TAPER          HRTIM_ADC4R_AD4TAPER_Msk                 /*!< ADC Trigger 4 on Timer A period */

+#define HRTIM_ADC4R_AD4TBC2_Pos       (14U)

+#define HRTIM_ADC4R_AD4TBC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos)       /*!< 0x00004000 */

+#define HRTIM_ADC4R_AD4TBC2           HRTIM_ADC4R_AD4TBC2_Msk                  /*!< ADC Trigger 4 on Timer B compare 2 */

+#define HRTIM_ADC4R_AD4TBC3_Pos       (15U)

+#define HRTIM_ADC4R_AD4TBC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC3_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC4R_AD4TBC3           HRTIM_ADC4R_AD4TBC3_Msk                  /*!< ADC Trigger 4 on Timer B compare 3 */

+#define HRTIM_ADC4R_AD4TBC4_Pos       (16U)

+#define HRTIM_ADC4R_AD4TBC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC4R_AD4TBC4           HRTIM_ADC4R_AD4TBC4_Msk                  /*!< ADC Trigger 4 on Timer B compare 4 */

+#define HRTIM_ADC4R_AD4TBPER_Pos      (17U)

+#define HRTIM_ADC4R_AD4TBPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos)      /*!< 0x00020000 */

+#define HRTIM_ADC4R_AD4TBPER          HRTIM_ADC4R_AD4TBPER_Msk                 /*!< ADC Trigger 4 on Timer B period */

+#define HRTIM_ADC4R_AD4TCC2_Pos       (18U)

+#define HRTIM_ADC4R_AD4TCC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos)       /*!< 0x00040000 */

+#define HRTIM_ADC4R_AD4TCC2           HRTIM_ADC4R_AD4TCC2_Msk                  /*!< ADC Trigger 4 on Timer C compare 2 */

+#define HRTIM_ADC4R_AD4TCC3_Pos       (19U)

+#define HRTIM_ADC4R_AD4TCC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC3_Pos)       /*!< 0x00080000 */

+#define HRTIM_ADC4R_AD4TCC3           HRTIM_ADC4R_AD4TCC3_Msk                  /*!< ADC Trigger 4 on Timer C compare 3 */

+#define HRTIM_ADC4R_AD4TCC4_Pos       (20U)

+#define HRTIM_ADC4R_AD4TCC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC4R_AD4TCC4           HRTIM_ADC4R_AD4TCC4_Msk                  /*!< ADC Trigger 4 on Timer C compare 4 */

+#define HRTIM_ADC4R_AD4TCPER_Pos      (21U)

+#define HRTIM_ADC4R_AD4TCPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos)      /*!< 0x00200000 */

+#define HRTIM_ADC4R_AD4TCPER          HRTIM_ADC4R_AD4TCPER_Msk                 /*!< ADC Trigger 4 on Timer C period */

+#define HRTIM_ADC4R_AD4TCRST_Pos      (22U)

+#define HRTIM_ADC4R_AD4TCRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos)      /*!< 0x00400000 */

+#define HRTIM_ADC4R_AD4TCRST          HRTIM_ADC4R_AD4TCRST_Msk                 /*!< ADC Trigger 4 on Timer C reset */

+#define HRTIM_ADC4R_AD4TDC2_Pos       (23U)

+#define HRTIM_ADC4R_AD4TDC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos)       /*!< 0x00800000 */

+#define HRTIM_ADC4R_AD4TDC2           HRTIM_ADC4R_AD4TDC2_Msk                  /*!< ADC Trigger 4 on Timer D compare 2 */

+#define HRTIM_ADC4R_AD4TDC3_Pos       (24U)

+#define HRTIM_ADC4R_AD4TDC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC3_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC4R_AD4TDC3           HRTIM_ADC4R_AD4TDC3_Msk                  /*!< ADC Trigger 4 on Timer D compare 3 */

+#define HRTIM_ADC4R_AD4TDC4_Pos       (25U)

+#define HRTIM_ADC4R_AD4TDC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC4R_AD4TDC4           HRTIM_ADC4R_AD4TDC4_Msk                  /*!< ADC Trigger 4 on Timer D compare 4*/

+#define HRTIM_ADC4R_AD4TDPER_Pos      (26U)

+#define HRTIM_ADC4R_AD4TDPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos)      /*!< 0x04000000 */

+#define HRTIM_ADC4R_AD4TDPER          HRTIM_ADC4R_AD4TDPER_Msk                 /*!< ADC Trigger 4 on Timer D period */

+#define HRTIM_ADC4R_AD4TDRST_Pos      (27U)

+#define HRTIM_ADC4R_AD4TDRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC4R_AD4TDRST          HRTIM_ADC4R_AD4TDRST_Msk                 /*!< ADC Trigger 4 on Timer D reset */

+#define HRTIM_ADC4R_AD4TEC2_Pos       (28U)

+#define HRTIM_ADC4R_AD4TEC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC4R_AD4TEC2           HRTIM_ADC4R_AD4TEC2_Msk                  /*!< ADC Trigger 4 on Timer E compare 2 */

+#define HRTIM_ADC4R_AD4TEC3_Pos       (29U)

+#define HRTIM_ADC4R_AD4TEC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC4R_AD4TEC3           HRTIM_ADC4R_AD4TEC3_Msk                  /*!< ADC Trigger 4 on Timer E compare 3 */

+#define HRTIM_ADC4R_AD4TEC4_Pos       (30U)

+#define HRTIM_ADC4R_AD4TEC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC4R_AD4TEC4           HRTIM_ADC4R_AD4TEC4_Msk                  /*!< ADC Trigger 4 on Timer E compare 4 */

+#define HRTIM_ADC4R_AD4TERST_Pos      (31U)

+#define HRTIM_ADC4R_AD4TERST_Msk      (0x1UL << HRTIM_ADC4R_AD4TERST_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC4R_AD4TERST          HRTIM_ADC4R_AD4TERST_Msk                 /*!< ADC Trigger 4 on Timer E reset */

+

+/*******************  Bit definition for HRTIM_FLTINR1 register  ***************/

+#define HRTIM_FLTINR1_FLT1E_Pos       (0U)

+#define HRTIM_FLTINR1_FLT1E_Msk       (0x1UL << HRTIM_FLTINR1_FLT1E_Pos)       /*!< 0x00000001 */

+#define HRTIM_FLTINR1_FLT1E           HRTIM_FLTINR1_FLT1E_Msk                  /*!< Fault 1 enable */

+#define HRTIM_FLTINR1_FLT1P_Pos       (1U)

+#define HRTIM_FLTINR1_FLT1P_Msk       (0x1UL << HRTIM_FLTINR1_FLT1P_Pos)       /*!< 0x00000002 */

+#define HRTIM_FLTINR1_FLT1P           HRTIM_FLTINR1_FLT1P_Msk                  /*!< Fault 1 polarity */

+#define HRTIM_FLTINR1_FLT1SRC_Pos     (2U)

+#define HRTIM_FLTINR1_FLT1SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT1SRC_Pos)     /*!< 0x00000004 */

+#define HRTIM_FLTINR1_FLT1SRC         HRTIM_FLTINR1_FLT1SRC_Msk                /*!< Fault 1 source */

+#define HRTIM_FLTINR1_FLT1F_Pos       (3U)

+#define HRTIM_FLTINR1_FLT1F_Msk       (0xFUL << HRTIM_FLTINR1_FLT1F_Pos)       /*!< 0x00000078 */

+#define HRTIM_FLTINR1_FLT1F           HRTIM_FLTINR1_FLT1F_Msk                  /*!< Fault 1 filter */

+#define HRTIM_FLTINR1_FLT1F_0         (0x1UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000008 */

+#define HRTIM_FLTINR1_FLT1F_1         (0x2UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000010 */

+#define HRTIM_FLTINR1_FLT1F_2         (0x4UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000020 */

+#define HRTIM_FLTINR1_FLT1F_3         (0x8UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000040 */

+#define HRTIM_FLTINR1_FLT1LCK_Pos     (7U)

+#define HRTIM_FLTINR1_FLT1LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos)     /*!< 0x00000080 */

+#define HRTIM_FLTINR1_FLT1LCK         HRTIM_FLTINR1_FLT1LCK_Msk                /*!< Fault 1 lock */

+

+#define HRTIM_FLTINR1_FLT2E_Pos       (8U)

+#define HRTIM_FLTINR1_FLT2E_Msk       (0x1UL << HRTIM_FLTINR1_FLT2E_Pos)       /*!< 0x00000100 */

+#define HRTIM_FLTINR1_FLT2E           HRTIM_FLTINR1_FLT2E_Msk                  /*!< Fault 2 enable */

+#define HRTIM_FLTINR1_FLT2P_Pos       (9U)

+#define HRTIM_FLTINR1_FLT2P_Msk       (0x1UL << HRTIM_FLTINR1_FLT2P_Pos)       /*!< 0x00000200 */

+#define HRTIM_FLTINR1_FLT2P           HRTIM_FLTINR1_FLT2P_Msk                  /*!< Fault 2 polarity */

+#define HRTIM_FLTINR1_FLT2SRC_Pos     (10U)

+#define HRTIM_FLTINR1_FLT2SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT2SRC_Pos)     /*!< 0x00000400 */

+#define HRTIM_FLTINR1_FLT2SRC         HRTIM_FLTINR1_FLT2SRC_Msk                /*!< Fault 2 source */

+#define HRTIM_FLTINR1_FLT2F_Pos       (11U)

+#define HRTIM_FLTINR1_FLT2F_Msk       (0xFUL << HRTIM_FLTINR1_FLT2F_Pos)       /*!< 0x00007800 */

+#define HRTIM_FLTINR1_FLT2F           HRTIM_FLTINR1_FLT2F_Msk                  /*!< Fault 2 filter */

+#define HRTIM_FLTINR1_FLT2F_0         (0x1UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00000800 */

+#define HRTIM_FLTINR1_FLT2F_1         (0x2UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00001000 */

+#define HRTIM_FLTINR1_FLT2F_2         (0x4UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00002000 */

+#define HRTIM_FLTINR1_FLT2F_3         (0x8UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00004000 */

+#define HRTIM_FLTINR1_FLT2LCK_Pos     (15U)

+#define HRTIM_FLTINR1_FLT2LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos)     /*!< 0x00008000 */

+#define HRTIM_FLTINR1_FLT2LCK         HRTIM_FLTINR1_FLT2LCK_Msk                /*!< Fault 2 lock */

+

+#define HRTIM_FLTINR1_FLT3E_Pos       (16U)

+#define HRTIM_FLTINR1_FLT3E_Msk       (0x1UL << HRTIM_FLTINR1_FLT3E_Pos)       /*!< 0x00010000 */

+#define HRTIM_FLTINR1_FLT3E           HRTIM_FLTINR1_FLT3E_Msk                  /*!< Fault 3 enable */

+#define HRTIM_FLTINR1_FLT3P_Pos       (17U)

+#define HRTIM_FLTINR1_FLT3P_Msk       (0x1UL << HRTIM_FLTINR1_FLT3P_Pos)       /*!< 0x00020000 */

+#define HRTIM_FLTINR1_FLT3P           HRTIM_FLTINR1_FLT3P_Msk                  /*!< Fault 3 polarity */

+#define HRTIM_FLTINR1_FLT3SRC_Pos     (18U)

+#define HRTIM_FLTINR1_FLT3SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT3SRC_Pos)     /*!< 0x00040000 */

+#define HRTIM_FLTINR1_FLT3SRC         HRTIM_FLTINR1_FLT3SRC_Msk                /*!< Fault 3 source */

+#define HRTIM_FLTINR1_FLT3F_Pos       (19U)

+#define HRTIM_FLTINR1_FLT3F_Msk       (0xFUL << HRTIM_FLTINR1_FLT3F_Pos)       /*!< 0x00780000 */

+#define HRTIM_FLTINR1_FLT3F           HRTIM_FLTINR1_FLT3F_Msk                  /*!< Fault 3 filter */

+#define HRTIM_FLTINR1_FLT3F_0         (0x1UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00080000 */

+#define HRTIM_FLTINR1_FLT3F_1         (0x2UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00100000 */

+#define HRTIM_FLTINR1_FLT3F_2         (0x4UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00200000 */

+#define HRTIM_FLTINR1_FLT3F_3         (0x8UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00400000 */

+#define HRTIM_FLTINR1_FLT3LCK_Pos     (23U)

+#define HRTIM_FLTINR1_FLT3LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos)     /*!< 0x00800000 */

+#define HRTIM_FLTINR1_FLT3LCK         HRTIM_FLTINR1_FLT3LCK_Msk                /*!< Fault 3 lock */

+

+#define HRTIM_FLTINR1_FLT4E_Pos       (24U)

+#define HRTIM_FLTINR1_FLT4E_Msk       (0x1UL << HRTIM_FLTINR1_FLT4E_Pos)       /*!< 0x01000000 */

+#define HRTIM_FLTINR1_FLT4E           HRTIM_FLTINR1_FLT4E_Msk                  /*!< Fault 4 enable */

+#define HRTIM_FLTINR1_FLT4P_Pos       (25U)

+#define HRTIM_FLTINR1_FLT4P_Msk       (0x1UL << HRTIM_FLTINR1_FLT4P_Pos)       /*!< 0x02000000 */

+#define HRTIM_FLTINR1_FLT4P           HRTIM_FLTINR1_FLT4P_Msk                  /*!< Fault 4 polarity */

+#define HRTIM_FLTINR1_FLT4SRC_Pos     (26U)

+#define HRTIM_FLTINR1_FLT4SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT4SRC_Pos)     /*!< 0x04000000 */

+#define HRTIM_FLTINR1_FLT4SRC         HRTIM_FLTINR1_FLT4SRC_Msk                /*!< Fault 4 source */

+#define HRTIM_FLTINR1_FLT4F_Pos       (27U)

+#define HRTIM_FLTINR1_FLT4F_Msk       (0xFUL << HRTIM_FLTINR1_FLT4F_Pos)       /*!< 0x78000000 */

+#define HRTIM_FLTINR1_FLT4F           HRTIM_FLTINR1_FLT4F_Msk                  /*!< Fault 4 filter */

+#define HRTIM_FLTINR1_FLT4F_0         (0x1UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x08000000 */

+#define HRTIM_FLTINR1_FLT4F_1         (0x2UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x10000000 */

+#define HRTIM_FLTINR1_FLT4F_2         (0x4UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x20000000 */

+#define HRTIM_FLTINR1_FLT4F_3         (0x8UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x40000000 */

+#define HRTIM_FLTINR1_FLT4LCK_Pos     (31U)

+#define HRTIM_FLTINR1_FLT4LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos)     /*!< 0x80000000 */

+#define HRTIM_FLTINR1_FLT4LCK         HRTIM_FLTINR1_FLT4LCK_Msk                /*!< Fault 4 lock */

+

+/*******************  Bit definition for HRTIM_FLTINR2 register  ***************/

+#define HRTIM_FLTINR2_FLT5E_Pos       (0U)

+#define HRTIM_FLTINR2_FLT5E_Msk       (0x1UL << HRTIM_FLTINR2_FLT5E_Pos)       /*!< 0x00000001 */

+#define HRTIM_FLTINR2_FLT5E           HRTIM_FLTINR2_FLT5E_Msk                  /*!< Fault 5 enable */

+#define HRTIM_FLTINR2_FLT5P_Pos       (1U)

+#define HRTIM_FLTINR2_FLT5P_Msk       (0x1UL << HRTIM_FLTINR2_FLT5P_Pos)       /*!< 0x00000002 */

+#define HRTIM_FLTINR2_FLT5P           HRTIM_FLTINR2_FLT5P_Msk                  /*!< Fault 5 polarity */

+#define HRTIM_FLTINR2_FLT5SRC_Pos     (2U)

+#define HRTIM_FLTINR2_FLT5SRC_Msk     (0x1UL << HRTIM_FLTINR2_FLT5SRC_Pos)     /*!< 0x00000004 */

+#define HRTIM_FLTINR2_FLT5SRC         HRTIM_FLTINR2_FLT5SRC_Msk                /*!< Fault 5 source */

+#define HRTIM_FLTINR2_FLT5F_Pos       (3U)

+#define HRTIM_FLTINR2_FLT5F_Msk       (0xFUL << HRTIM_FLTINR2_FLT5F_Pos)       /*!< 0x00000078 */

+#define HRTIM_FLTINR2_FLT5F           HRTIM_FLTINR2_FLT5F_Msk                  /*!< Fault 5 filter */

+#define HRTIM_FLTINR2_FLT5F_0         (0x1UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000008 */

+#define HRTIM_FLTINR2_FLT5F_1         (0x2UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000010 */

+#define HRTIM_FLTINR2_FLT5F_2         (0x4UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000020 */

+#define HRTIM_FLTINR2_FLT5F_3         (0x8UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000040 */

+#define HRTIM_FLTINR2_FLT5LCK_Pos     (7U)

+#define HRTIM_FLTINR2_FLT5LCK_Msk     (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos)     /*!< 0x00000080 */

+#define HRTIM_FLTINR2_FLT5LCK         HRTIM_FLTINR2_FLT5LCK_Msk                /*!< Fault 5 lock */

+#define HRTIM_FLTINR2_FLTSD_Pos       (24U)

+#define HRTIM_FLTINR2_FLTSD_Msk       (0x3UL << HRTIM_FLTINR2_FLTSD_Pos)       /*!< 0x03000000 */

+#define HRTIM_FLTINR2_FLTSD           HRTIM_FLTINR2_FLTSD_Msk                  /*!< Fault sampling clock division */

+#define HRTIM_FLTINR2_FLTSD_0         (0x1UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x01000000 */

+#define HRTIM_FLTINR2_FLTSD_1         (0x2UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x02000000 */

+

+/*******************  Bit definition for HRTIM_BDMUPR register  ***************/

+#define HRTIM_BDMUPR_MCR_Pos          (0U)

+#define HRTIM_BDMUPR_MCR_Msk          (0x1UL << HRTIM_BDMUPR_MCR_Pos)          /*!< 0x00000001 */

+#define HRTIM_BDMUPR_MCR              HRTIM_BDMUPR_MCR_Msk                     /*!< MCR register update enable */

+#define HRTIM_BDMUPR_MICR_Pos         (1U)

+#define HRTIM_BDMUPR_MICR_Msk         (0x1UL << HRTIM_BDMUPR_MICR_Pos)         /*!< 0x00000002 */

+#define HRTIM_BDMUPR_MICR             HRTIM_BDMUPR_MICR_Msk                    /*!< MICR register update enable */

+#define HRTIM_BDMUPR_MDIER_Pos        (2U)

+#define HRTIM_BDMUPR_MDIER_Msk        (0x1UL << HRTIM_BDMUPR_MDIER_Pos)        /*!< 0x00000004 */

+#define HRTIM_BDMUPR_MDIER            HRTIM_BDMUPR_MDIER_Msk                   /*!< MDIER register update enable */

+#define HRTIM_BDMUPR_MCNT_Pos         (3U)

+#define HRTIM_BDMUPR_MCNT_Msk         (0x1UL << HRTIM_BDMUPR_MCNT_Pos)         /*!< 0x00000008 */

+#define HRTIM_BDMUPR_MCNT             HRTIM_BDMUPR_MCNT_Msk                    /*!< MCNT register update enable */

+#define HRTIM_BDMUPR_MPER_Pos         (4U)

+#define HRTIM_BDMUPR_MPER_Msk         (0x1UL << HRTIM_BDMUPR_MPER_Pos)         /*!< 0x00000010 */

+#define HRTIM_BDMUPR_MPER             HRTIM_BDMUPR_MPER_Msk                    /*!< MPER register update enable */

+#define HRTIM_BDMUPR_MREP_Pos         (5U)

+#define HRTIM_BDMUPR_MREP_Msk         (0x1UL << HRTIM_BDMUPR_MREP_Pos)         /*!< 0x00000020 */

+#define HRTIM_BDMUPR_MREP             HRTIM_BDMUPR_MREP_Msk                    /*!< MREP register update enable */

+#define HRTIM_BDMUPR_MCMP1_Pos        (6U)

+#define HRTIM_BDMUPR_MCMP1_Msk        (0x1UL << HRTIM_BDMUPR_MCMP1_Pos)        /*!< 0x00000040 */

+#define HRTIM_BDMUPR_MCMP1            HRTIM_BDMUPR_MCMP1_Msk                   /*!< MCMP1 register update enable */

+#define HRTIM_BDMUPR_MCMP2_Pos        (7U)

+#define HRTIM_BDMUPR_MCMP2_Msk        (0x1UL << HRTIM_BDMUPR_MCMP2_Pos)        /*!< 0x00000080 */

+#define HRTIM_BDMUPR_MCMP2            HRTIM_BDMUPR_MCMP2_Msk                   /*!< MCMP2 register update enable */

+#define HRTIM_BDMUPR_MCMP3_Pos        (8U)

+#define HRTIM_BDMUPR_MCMP3_Msk        (0x1UL << HRTIM_BDMUPR_MCMP3_Pos)        /*!< 0x00000100 */

+#define HRTIM_BDMUPR_MCMP3            HRTIM_BDMUPR_MCMP3_Msk                   /*!< MCMP3 register update enable */

+#define HRTIM_BDMUPR_MCMP4_Pos        (9U)

+#define HRTIM_BDMUPR_MCMP4_Msk        (0x1UL << HRTIM_BDMUPR_MCMP4_Pos)        /*!< 0x00000200 */

+#define HRTIM_BDMUPR_MCMP4            HRTIM_BDMUPR_MCMP4_Msk                   /*!< MPCMP4 register update enable */

+

+/*******************  Bit definition for HRTIM_BDTUPR register  ***************/

+#define HRTIM_BDTUPR_TIMCR_Pos        (0U)

+#define HRTIM_BDTUPR_TIMCR_Msk        (0x1UL << HRTIM_BDTUPR_TIMCR_Pos)        /*!< 0x00000001 */

+#define HRTIM_BDTUPR_TIMCR            HRTIM_BDTUPR_TIMCR_Msk                   /*!<  TIMCR register update enable */

+#define HRTIM_BDTUPR_TIMICR_Pos       (1U)

+#define HRTIM_BDTUPR_TIMICR_Msk       (0x1UL << HRTIM_BDTUPR_TIMICR_Pos)       /*!< 0x00000002 */

+#define HRTIM_BDTUPR_TIMICR           HRTIM_BDTUPR_TIMICR_Msk                  /*!<  TIMICR register update enable */

+#define HRTIM_BDTUPR_TIMDIER_Pos      (2U)

+#define HRTIM_BDTUPR_TIMDIER_Msk      (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos)      /*!< 0x00000004 */

+#define HRTIM_BDTUPR_TIMDIER          HRTIM_BDTUPR_TIMDIER_Msk                 /*!<  TIMDIER register update enable */

+#define HRTIM_BDTUPR_TIMCNT_Pos       (3U)

+#define HRTIM_BDTUPR_TIMCNT_Msk       (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos)       /*!< 0x00000008 */

+#define HRTIM_BDTUPR_TIMCNT           HRTIM_BDTUPR_TIMCNT_Msk                  /*!<  TIMCNT register update enable */

+#define HRTIM_BDTUPR_TIMPER_Pos       (4U)

+#define HRTIM_BDTUPR_TIMPER_Msk       (0x1UL << HRTIM_BDTUPR_TIMPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_BDTUPR_TIMPER           HRTIM_BDTUPR_TIMPER_Msk                  /*!<  TIMPER register update enable */

+#define HRTIM_BDTUPR_TIMREP_Pos       (5U)

+#define HRTIM_BDTUPR_TIMREP_Msk       (0x1UL << HRTIM_BDTUPR_TIMREP_Pos)       /*!< 0x00000020 */

+#define HRTIM_BDTUPR_TIMREP           HRTIM_BDTUPR_TIMREP_Msk                  /*!<  TIMREP register update enable */

+#define HRTIM_BDTUPR_TIMCMP1_Pos      (6U)

+#define HRTIM_BDTUPR_TIMCMP1_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos)      /*!< 0x00000040 */

+#define HRTIM_BDTUPR_TIMCMP1          HRTIM_BDTUPR_TIMCMP1_Msk                 /*!<  TIMCMP1 register update enable */

+#define HRTIM_BDTUPR_TIMCMP2_Pos      (7U)

+#define HRTIM_BDTUPR_TIMCMP2_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos)      /*!< 0x00000080 */

+#define HRTIM_BDTUPR_TIMCMP2          HRTIM_BDTUPR_TIMCMP2_Msk                 /*!<  TIMCMP2 register update enable */

+#define HRTIM_BDTUPR_TIMCMP3_Pos      (8U)

+#define HRTIM_BDTUPR_TIMCMP3_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos)      /*!< 0x00000100 */

+#define HRTIM_BDTUPR_TIMCMP3          HRTIM_BDTUPR_TIMCMP3_Msk                 /*!<  TIMCMP3 register update enable */

+#define HRTIM_BDTUPR_TIMCMP4_Pos      (9U)

+#define HRTIM_BDTUPR_TIMCMP4_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos)      /*!< 0x00000200 */

+#define HRTIM_BDTUPR_TIMCMP4          HRTIM_BDTUPR_TIMCMP4_Msk                 /*!<  TIMCMP4 register update enable */

+#define HRTIM_BDTUPR_TIMDTR_Pos       (10U)

+#define HRTIM_BDTUPR_TIMDTR_Msk       (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos)       /*!< 0x00000400 */

+#define HRTIM_BDTUPR_TIMDTR           HRTIM_BDTUPR_TIMDTR_Msk                  /*!<  TIMDTR register update enable */

+#define HRTIM_BDTUPR_TIMSET1R_Pos     (11U)

+#define HRTIM_BDTUPR_TIMSET1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos)     /*!< 0x00000800 */

+#define HRTIM_BDTUPR_TIMSET1R         HRTIM_BDTUPR_TIMSET1R_Msk                /*!<  TIMSET1R register update enable */

+#define HRTIM_BDTUPR_TIMRST1R_Pos     (12U)

+#define HRTIM_BDTUPR_TIMRST1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos)     /*!< 0x00001000 */

+#define HRTIM_BDTUPR_TIMRST1R         HRTIM_BDTUPR_TIMRST1R_Msk                /*!<  TIMRST1R register update enable */

+#define HRTIM_BDTUPR_TIMSET2R_Pos     (13U)

+#define HRTIM_BDTUPR_TIMSET2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos)     /*!< 0x00002000 */

+#define HRTIM_BDTUPR_TIMSET2R         HRTIM_BDTUPR_TIMSET2R_Msk                /*!<  TIMSET2R register update enable */

+#define HRTIM_BDTUPR_TIMRST2R_Pos     (14U)

+#define HRTIM_BDTUPR_TIMRST2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos)     /*!< 0x00004000 */

+#define HRTIM_BDTUPR_TIMRST2R         HRTIM_BDTUPR_TIMRST2R_Msk                /*!<  TIMRST2R register update enable */

+#define HRTIM_BDTUPR_TIMEEFR1_Pos     (15U)

+#define HRTIM_BDTUPR_TIMEEFR1_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos)     /*!< 0x00008000 */

+#define HRTIM_BDTUPR_TIMEEFR1         HRTIM_BDTUPR_TIMEEFR1_Msk                /*!<  TIMEEFR1 register update enable */

+#define HRTIM_BDTUPR_TIMEEFR2_Pos     (16U)

+#define HRTIM_BDTUPR_TIMEEFR2_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos)     /*!< 0x00010000 */

+#define HRTIM_BDTUPR_TIMEEFR2         HRTIM_BDTUPR_TIMEEFR2_Msk                /*!<  TIMEEFR2 register update enable */

+#define HRTIM_BDTUPR_TIMRSTR_Pos      (17U)

+#define HRTIM_BDTUPR_TIMRSTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos)      /*!< 0x00020000 */

+#define HRTIM_BDTUPR_TIMRSTR          HRTIM_BDTUPR_TIMRSTR_Msk                 /*!<  TIMRSTR register update enable */

+#define HRTIM_BDTUPR_TIMCHPR_Pos      (18U)

+#define HRTIM_BDTUPR_TIMCHPR_Msk      (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos)      /*!< 0x00040000 */

+#define HRTIM_BDTUPR_TIMCHPR          HRTIM_BDTUPR_TIMCHPR_Msk                 /*!<  TIMCHPR register update enable */

+#define HRTIM_BDTUPR_TIMOUTR_Pos      (19U)

+#define HRTIM_BDTUPR_TIMOUTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos)      /*!< 0x00080000 */

+#define HRTIM_BDTUPR_TIMOUTR          HRTIM_BDTUPR_TIMOUTR_Msk                 /*!<  TIMOUTR register update enable */

+#define HRTIM_BDTUPR_TIMFLTR_Pos      (20U)

+#define HRTIM_BDTUPR_TIMFLTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos)      /*!< 0x00100000 */

+#define HRTIM_BDTUPR_TIMFLTR          HRTIM_BDTUPR_TIMFLTR_Msk                 /*!<  TIMFLTR register update enable */

+

+/*******************  Bit definition for HRTIM_BDMADR register  ***************/

+#define HRTIM_BDMADR_BDMADR_Pos       (0U)

+#define HRTIM_BDMADR_BDMADR_Msk       (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos) /*!< 0xFFFFFFFF */

+#define HRTIM_BDMADR_BDMADR           HRTIM_BDMADR_BDMADR_Msk                  /*!<  Burst DMA Data register */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             RAM ECC monitoring                             */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for RAMECC_IER register  ******************/

+#define RAMECC_IER_GECCDEBWIE_Pos         (3U)

+#define RAMECC_IER_GECCDEBWIE_Msk         (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)  /*!< 0x00000008 */

+#define RAMECC_IER_GECCDEBWIE             RAMECC_IER_GECCDEBWIE_Msk             /*!< Global ECC double error on byte write (BW) interrupt enable */

+#define RAMECC_IER_GECCDEIE_Pos           (2U)

+#define RAMECC_IER_GECCDEIE_Msk           (0x1UL << RAMECC_IER_GECCDEIE_Pos)    /*!< 0x00000004 */

+#define RAMECC_IER_GECCDEIE               RAMECC_IER_GECCDEIE_Msk               /*!< Global ECC double error interrupt enable */

+#define RAMECC_IER_GECCSEIE_Pos           (1U)

+#define RAMECC_IER_GECCSEIE_Msk           (0x1UL << RAMECC_IER_GECCSEIE_Pos)    /*!< 0x00000002 */

+#define RAMECC_IER_GECCSEIE               RAMECC_IER_GECCSEIE_Msk               /*!< Global ECC single error interrupt enable */

+#define RAMECC_IER_GIE_Pos                (0U)

+#define RAMECC_IER_GIE_Msk                (0x1UL << RAMECC_IER_GIE_Pos)         /*!< 0x00000001 */

+#define RAMECC_IER_GIE                    RAMECC_IER_GIE_Msk                    /*!< Global interrupt enable */

+

+/*******************  Bit definition for RAMECC_CR register  ******************/

+#define RAMECC_CR_ECCELEN_Pos             (5U)

+#define RAMECC_CR_ECCELEN_Msk             (0x1UL << RAMECC_CR_ECCELEN_Pos)      /*!< 0x00000020 */

+#define RAMECC_CR_ECCELEN                 RAMECC_CR_ECCELEN_Msk                 /*!< ECC error latching enable */

+#define RAMECC_CR_ECCDEBWIE_Pos           (4U)

+#define RAMECC_CR_ECCDEBWIE_Msk           (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)    /*!< 0x00000010 */

+#define RAMECC_CR_ECCDEBWIE               RAMECC_CR_ECCDEBWIE_Msk               /*!< ECC double error on byte write (BW) interrupt enable */

+#define RAMECC_CR_ECCDEIE_Pos             (3U)

+#define RAMECC_CR_ECCDEIE_Msk             (0x1UL << RAMECC_CR_ECCDEIE_Pos)      /*!< 0x00000008 */

+#define RAMECC_CR_ECCDEIE                 RAMECC_CR_ECCDEIE_Msk                 /*!< ECC double error interrupt enable */

+#define RAMECC_CR_ECCSEIE_Pos             (2U)

+#define RAMECC_CR_ECCSEIE_Msk             (0x1UL << RAMECC_CR_ECCSEIE_Pos)      /*!< 0x00000004 */

+#define RAMECC_CR_ECCSEIE                 RAMECC_CR_ECCSEIE_Msk                 /*!< ECC single error interrupt enable */

+

+/*******************  Bit definition for RAMECC_SR register  ******************/

+#define RAMECC_SR_DEBWDF_Pos             (2U)

+#define RAMECC_SR_DEBWDF_Msk             (0x1UL << RAMECC_SR_DEBWDF_Pos)        /*!< 0x00000004 */

+#define RAMECC_SR_DEBWDF                 RAMECC_SR_DEBWDF_Msk                   /*!< ECC double error on byte write (BW) detected flag */

+#define RAMECC_SR_DEDF_Pos               (1U)

+#define RAMECC_SR_DEDF_Msk               (0x1UL << RAMECC_SR_DEDF_Pos)          /*!< 0x00000002 */

+#define RAMECC_SR_DEDF                   RAMECC_SR_DEDF_Msk                     /*!< ECC double error detected flag */

+#define RAMECC_SR_SEDCF_Pos              (0U)

+#define RAMECC_SR_SEDCF_Msk              (0x1UL << RAMECC_SR_SEDCF_Pos)         /*!< 0x00000001 */

+#define RAMECC_SR_SEDCF                  RAMECC_SR_SEDCF_Msk                    /*!< ECC single error detected and corrected flag */

+

+/******************  Bit definition for RAMECC_FAR register  ******************/

+#define RAMECC_FAR_FADD_Pos              (0U)

+#define RAMECC_FAR_FADD_Msk              (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)  /*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FADD                  RAMECC_FAR_FADD_Msk                    /*!< ECC error failing address */

+

+/******************  Bit definition for RAMECC_FDRL register  *****************/

+#define RAMECC_FAR_FDATAL_Pos            (0U)

+#define RAMECC_FAR_FDATAL_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FDATAL                RAMECC_FAR_FDATAL_Msk                  /*!< ECC error failing address */

+

+/******************  Bit definition for RAMECC_FDRH register  *****************/

+#define RAMECC_FAR_FDATAH_Pos            (0U)

+#define RAMECC_FAR_FDATAH_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FDATAH                RAMECC_FAR_FDATAH_Msk                  /* Failing data high (64-bit memory) */

+

+/*****************  Bit definition for RAMECC_FECR register  ******************/

+#define RAMECC_FECR_FEC_Pos              (0U)

+#define RAMECC_FECR_FEC_Msk              (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)  /*!< 0xFFFFFFFF */

+#define RAMECC_FECR_FEC                  RAMECC_FECR_FEC_Msk                    /*!< Failing error code */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                MDIOS                                        */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for MDIOS_CR register  *******************/

+#define MDIOS_CR_EN_Pos                (0U)

+#define MDIOS_CR_EN_Msk                (0x1UL << MDIOS_CR_EN_Pos)              /*!< 0x00000001 */

+#define MDIOS_CR_EN                    MDIOS_CR_EN_Msk                         /*!<  MDIOS slave peripheral enable */

+#define MDIOS_CR_WRIE_Pos              (1U)

+#define MDIOS_CR_WRIE_Msk              (0x1UL << MDIOS_CR_WRIE_Pos)            /*!< 0x00000002 */

+#define MDIOS_CR_WRIE                  MDIOS_CR_WRIE_Msk                       /*!<  MDIOS slave register write interrupt enable. */

+#define MDIOS_CR_RDIE_Pos              (2U)

+#define MDIOS_CR_RDIE_Msk              (0x1UL << MDIOS_CR_RDIE_Pos)            /*!< 0x00000004 */

+#define MDIOS_CR_RDIE                  MDIOS_CR_RDIE_Msk                       /*!<  MDIOS slave register read interrupt enable. */

+#define MDIOS_CR_EIE_Pos               (3U)

+#define MDIOS_CR_EIE_Msk               (0x1UL << MDIOS_CR_EIE_Pos)             /*!< 0x00000008 */

+#define MDIOS_CR_EIE                   MDIOS_CR_EIE_Msk                        /*!<  MDIOS slave register error interrupt enable. */

+#define MDIOS_CR_DPC_Pos               (7U)

+#define MDIOS_CR_DPC_Msk               (0x1UL << MDIOS_CR_DPC_Pos)             /*!< 0x00000080 */

+#define MDIOS_CR_DPC                   MDIOS_CR_DPC_Msk                        /*!<  MDIOS slave disable preamble check. */

+#define MDIOS_CR_PORT_ADDRESS_Pos      (8U)

+#define MDIOS_CR_PORT_ADDRESS_Msk      (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)   /*!< 0x00001F00 */

+#define MDIOS_CR_PORT_ADDRESS          MDIOS_CR_PORT_ADDRESS_Msk               /*!<  MDIOS slave port address mask. */

+#define MDIOS_CR_PORT_ADDRESS_0        (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000100 */

+#define MDIOS_CR_PORT_ADDRESS_1        (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000200 */

+#define MDIOS_CR_PORT_ADDRESS_2        (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000400 */

+#define MDIOS_CR_PORT_ADDRESS_3        (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000800 */

+#define MDIOS_CR_PORT_ADDRESS_4        (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001000 */

+

+/********************  Bit definition for MDIOS_SR register  *******************/

+#define MDIOS_SR_PERF_Pos              (0U)

+#define MDIOS_SR_PERF_Msk              (0x1UL << MDIOS_SR_PERF_Pos)            /*!< 0x00000001 */

+#define MDIOS_SR_PERF                  MDIOS_SR_PERF_Msk                       /*!<  MDIOS slave turnaround error flag*/

+#define MDIOS_SR_SERF_Pos              (1U)

+#define MDIOS_SR_SERF_Msk              (0x1UL << MDIOS_SR_SERF_Pos)            /*!< 0x00000002 */

+#define MDIOS_SR_SERF                  MDIOS_SR_SERF_Msk                       /*!<  MDIOS slave start error flag */

+#define MDIOS_SR_TERF_Pos              (2U)

+#define MDIOS_SR_TERF_Msk              (0x1UL << MDIOS_SR_TERF_Pos)            /*!< 0x00000004 */

+#define MDIOS_SR_TERF                  MDIOS_SR_TERF_Msk                       /*!<  MDIOS slave preamble error flag */

+

+/********************  Bit definition for MDIOS_CLRFR register  *******************/

+#define MDIOS_SR_CPERF_Pos             (0U)

+#define MDIOS_SR_CPERF_Msk             (0x1UL << MDIOS_SR_CPERF_Pos)           /*!< 0x00000001 */

+#define MDIOS_SR_CPERF                 MDIOS_SR_CPERF_Msk                      /*!<  MDIOS slave Clear the turnaround error flag */

+#define MDIOS_SR_CSERF_Pos             (1U)

+#define MDIOS_SR_CSERF_Msk             (0x1UL << MDIOS_SR_CSERF_Pos)           /*!< 0x00000002 */

+#define MDIOS_SR_CSERF                 MDIOS_SR_CSERF_Msk                      /*!<  MDIOS slave Clear the start error flag */

+#define MDIOS_SR_CTERF_Pos             (2U)

+#define MDIOS_SR_CTERF_Msk             (0x1UL << MDIOS_SR_CTERF_Pos)           /*!< 0x00000004 */

+#define MDIOS_SR_CTERF                 MDIOS_SR_CTERF_Msk                      /*!<  MDIOS slave Clear the preamble error flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                       USB_OTG                              */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/

+#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)

+#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */

+#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */

+#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)

+#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */

+#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */

+#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)

+#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */

+#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */

+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)

+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */

+#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */

+#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)

+#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */

+#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */

+#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)

+#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */

+#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */

+#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)

+#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */

+#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */

+#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)

+#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */

+#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */

+#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)

+#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */

+#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */

+#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)

+#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */

+#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */

+#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)

+#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */

+#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */

+#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)

+#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */

+#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */

+#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)

+#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */

+#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */

+#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)

+#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */

+#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */

+#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)

+#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */

+#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */

+#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)

+#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */

+#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */

+#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)

+#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */

+#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */

+#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)

+#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */

+#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */

+

+/********************  Bit definition forUSB_OTG_HCFG register  ********************/

+

+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)

+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */

+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */

+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)

+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */

+

+/********************  Bit definition forUSB_OTG_DCFG register  ********************/

+

+#define USB_OTG_DCFG_DSPD_Pos                    (0U)

+#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */

+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */

+#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */

+#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)

+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */

+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */

+

+#define USB_OTG_DCFG_DAD_Pos                     (4U)

+#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */

+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */

+#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */

+#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */

+#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */

+#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */

+#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */

+#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */

+#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */

+

+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)

+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */

+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */

+#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */

+#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */

+

+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)

+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */

+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */

+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */

+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */

+

+/********************  Bit definition forUSB_OTG_PCGCR register  ********************/

+#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)

+#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */

+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */

+#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)

+#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */

+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */

+#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)

+#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */

+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */

+

+/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/

+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)

+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */

+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */

+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)

+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */

+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */

+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)

+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */

+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */

+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)

+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */

+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */

+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)

+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */

+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */

+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)

+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */

+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */

+

+/********************  Bit definition forUSB_OTG_DCTL register  ********************/

+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)

+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */

+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */

+#define USB_OTG_DCTL_SDIS_Pos                    (1U)

+#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */

+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */

+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)

+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */

+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */

+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)

+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */

+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */

+

+#define USB_OTG_DCTL_TCTL_Pos                    (4U)

+#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */

+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */

+#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */

+#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */

+#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */

+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)

+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */

+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */

+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)

+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */

+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */

+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)

+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */

+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */

+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)

+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */

+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */

+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)

+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */

+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */

+

+/********************  Bit definition forUSB_OTG_HFIR register  ********************/

+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)

+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */

+

+/********************  Bit definition forUSB_OTG_HFNUM register  ********************/

+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)

+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */

+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)

+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */

+

+/********************  Bit definition forUSB_OTG_DSTS register  ********************/

+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)

+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */

+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */

+

+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)

+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */

+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */

+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */

+#define USB_OTG_DSTS_EERR_Pos                    (3U)

+#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */

+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */

+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)

+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */

+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */

+

+/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/

+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)

+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */

+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */

+

+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)

+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */

+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */

+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */

+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */

+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */

+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */

+#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */

+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)

+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */

+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */

+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)

+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */

+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */

+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)

+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */

+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */

+

+/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/

+

+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)

+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */

+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */

+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */

+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */

+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */

+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)

+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */

+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */

+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)

+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */

+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */

+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)

+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */

+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */

+

+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)

+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */

+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */

+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */

+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */

+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */

+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */

+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)

+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */

+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */

+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)

+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */

+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */

+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)

+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */

+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */

+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)

+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */

+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */

+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)

+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */

+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */

+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)

+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */

+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */

+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)

+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */

+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */

+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)

+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */

+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */

+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)

+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */

+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */

+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)

+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */

+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */

+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)

+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */

+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */

+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)

+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */

+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */

+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)

+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */

+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */

+

+/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/

+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)

+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */

+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */

+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)

+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */

+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */

+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)

+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */

+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */

+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)

+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */

+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */

+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)

+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */

+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */

+

+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)

+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */

+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */

+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */

+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */

+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */

+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */

+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */

+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)

+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */

+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */

+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)

+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */

+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */

+

+/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/

+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)

+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */

+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)

+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */

+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)

+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */

+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)

+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */

+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)

+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */

+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)

+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */

+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)

+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */

+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)

+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */

+

+/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/

+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)

+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */

+

+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)

+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */

+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */

+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */

+

+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)

+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */

+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */

+

+/********************  Bit definition forUSB_OTG_HAINT register  ********************/

+#define USB_OTG_HAINT_HAINT_Pos                  (0U)

+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */

+

+/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/

+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)

+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */

+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)

+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */

+#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)

+#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */

+#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask               */

+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)

+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */

+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)

+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */

+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)

+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */

+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)

+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */

+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)

+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */

+#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)

+#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */

+#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)

+#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask               */

+#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)

+#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask               */

+#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)

+#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                */

+

+/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/

+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)

+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */

+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */

+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)

+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */

+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */

+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)

+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */

+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */

+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)

+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */

+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */

+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)

+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */

+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */

+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)

+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */

+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */

+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)

+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */

+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */

+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)

+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */

+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */

+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)

+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */

+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */

+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)

+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */

+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */

+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)

+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */

+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */

+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)

+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */

+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */

+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)

+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */

+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */

+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)

+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */

+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */

+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)

+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */

+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */

+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)

+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */

+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */

+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)

+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */

+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */

+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)

+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */

+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */

+#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)

+#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */

+#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */

+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)

+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */

+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */

+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)

+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */

+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */

+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)

+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */

+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */

+#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)

+#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */

+#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */

+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)

+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */

+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */

+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)

+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */

+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */

+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)

+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */

+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */

+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)

+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */

+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */

+

+/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/

+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)

+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */

+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */

+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)

+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */

+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */

+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)

+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */

+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */

+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)

+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */

+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */

+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)

+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */

+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */

+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)

+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */

+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */

+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)

+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */

+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */

+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)

+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */

+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */

+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)

+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */

+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */

+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)

+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */

+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */

+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)

+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */

+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */

+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)

+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */

+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */

+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)

+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */

+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */

+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)

+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */

+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */

+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)

+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */

+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */

+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)

+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */

+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */

+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)

+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */

+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */

+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)

+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */

+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */

+#define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)

+#define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */

+#define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */

+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)

+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */

+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */

+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)

+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */

+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */

+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)

+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */

+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */

+#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)

+#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */

+#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */

+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)

+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */

+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */

+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)

+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */

+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */

+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)

+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */

+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */

+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)

+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */

+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */

+

+/********************  Bit definition forUSB_OTG_DAINT register  ********************/

+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)

+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */

+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)

+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */

+

+/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/

+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)

+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */

+

+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/

+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)

+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */

+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */

+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)

+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */

+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */

+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)

+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */

+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */

+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)

+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */

+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */

+

+/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/

+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)

+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */

+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)

+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */

+

+/********************  Bit definition for OTG register  ********************/

+

+#define USB_OTG_CHNUM_Pos                        (0U)

+#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)  /*!< 0x0000000F */

+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */

+#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */

+#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */

+#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */

+#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */

+#define USB_OTG_BCNT_Pos                         (4U)

+#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */

+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */

+

+#define USB_OTG_DPID_Pos                         (15U)

+#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)   /*!< 0x00018000 */

+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */

+#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */

+#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */

+

+#define USB_OTG_PKTSTS_Pos                       (17U)

+#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */

+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */

+#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */

+#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */

+#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */

+#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */

+

+#define USB_OTG_EPNUM_Pos                        (0U)

+#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)  /*!< 0x0000000F */

+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */

+#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */

+#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */

+#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */

+#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */

+

+#define USB_OTG_FRMNUM_Pos                       (21U)

+#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */

+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */

+#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */

+#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */

+#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */

+#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */

+

+/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/

+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)

+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/

+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)

+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */

+

+/********************  Bit definition for OTG register  ********************/

+#define USB_OTG_NPTXFSA_Pos                      (0U)

+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */

+#define USB_OTG_NPTXFD_Pos                       (16U)

+#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */

+#define USB_OTG_TX0FSA_Pos                       (0U)

+#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */

+#define USB_OTG_TX0FD_Pos                        (16U)

+#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */

+

+/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/

+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)

+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */

+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */

+

+/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/

+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)

+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */

+

+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)

+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */

+

+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)

+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/

+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)

+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */

+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */

+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)

+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */

+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */

+

+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)

+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */

+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */

+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */

+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)

+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */

+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */

+

+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)

+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */

+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */

+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)

+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */

+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */

+

+/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */

+

+/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/

+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)

+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */

+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */

+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)

+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */

+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */

+

+/********************  Bit definition forUSB_OTG_GCCFG register  ********************/

+#define USB_OTG_GCCFG_DCDET_Pos                  (0U)

+#define USB_OTG_GCCFG_DCDET_Msk                  (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */

+#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */

+#define USB_OTG_GCCFG_PDET_Pos                   (1U)

+#define USB_OTG_GCCFG_PDET_Msk                   (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */

+#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */

+#define USB_OTG_GCCFG_SDET_Pos                   (2U)

+#define USB_OTG_GCCFG_SDET_Msk                   (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */

+#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */

+#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)

+#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */

+#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */

+#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)

+#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */

+#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */

+#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)

+#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */

+#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */

+#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)

+#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */

+#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/

+#define USB_OTG_GCCFG_PDEN_Pos                   (19U)

+#define USB_OTG_GCCFG_PDEN_Msk                   (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */

+#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/

+#define USB_OTG_GCCFG_SDEN_Pos                   (20U)

+#define USB_OTG_GCCFG_SDEN_Msk                   (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */

+#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */

+#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)

+#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */

+#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */

+

+/********************  Bit definition forUSB_OTG_GPWRDN) register  ********************/

+#define USB_OTG_GPWRDN_ADPMEN_Pos                (0U)

+#define USB_OTG_GPWRDN_ADPMEN_Msk                (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */

+#define USB_OTG_GPWRDN_ADPMEN                    USB_OTG_GPWRDN_ADPMEN_Msk     /*!< ADP module enable */

+#define USB_OTG_GPWRDN_ADPIF_Pos                 (23U)

+#define USB_OTG_GPWRDN_ADPIF_Msk                 (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */

+#define USB_OTG_GPWRDN_ADPIF                     USB_OTG_GPWRDN_ADPIF_Msk      /*!< ADP Interrupt flag */

+

+/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/

+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)

+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */

+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)

+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */

+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */

+

+/********************  Bit definition forUSB_OTG_CID register  ********************/

+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)

+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */

+

+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/

+#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)

+#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */

+#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */

+#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)

+#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */

+#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */

+#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)

+#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */

+#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */

+#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)

+#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */

+#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */

+#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)

+#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */

+#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */

+#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)

+#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */

+#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */

+#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)

+#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */

+#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */

+#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)

+#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */

+#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */

+#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)

+#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */

+#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */

+#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)

+#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */

+#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */

+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)

+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */

+#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */

+#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)

+#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */

+#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */

+#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)

+#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */

+#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */

+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)

+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */

+#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */

+#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)

+#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */

+#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */

+

+/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/

+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)

+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */

+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)

+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */

+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)

+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */

+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)

+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */

+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)

+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */

+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)

+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */

+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)

+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */

+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)

+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */

+

+/********************  Bit definition forUSB_OTG_HPRT register  ********************/

+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)

+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */

+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */

+#define USB_OTG_HPRT_PCDET_Pos                   (1U)

+#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */

+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */

+#define USB_OTG_HPRT_PENA_Pos                    (2U)

+#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */

+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */

+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)

+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */

+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */

+#define USB_OTG_HPRT_POCA_Pos                    (4U)

+#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */

+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */

+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)

+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */

+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */

+#define USB_OTG_HPRT_PRES_Pos                    (6U)

+#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */

+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume   */

+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)

+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */

+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend  */

+#define USB_OTG_HPRT_PRST_Pos                    (8U)

+#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */

+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset    */

+

+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)

+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */

+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */

+#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */

+#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */

+#define USB_OTG_HPRT_PPWR_Pos                    (12U)

+#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */

+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */

+

+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)

+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */

+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */

+#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */

+#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */

+#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */

+#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */

+

+#define USB_OTG_HPRT_PSPD_Pos                    (17U)

+#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */

+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */

+#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */

+#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */

+

+/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/

+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)

+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)

+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)

+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */

+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)

+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */

+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)

+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */

+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)

+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */

+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)

+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)

+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)

+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)

+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */

+

+/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/

+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)

+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */

+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)

+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/

+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)

+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */

+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)

+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */

+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */

+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)

+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */

+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */

+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)

+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */

+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */

+

+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)

+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */

+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */

+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)

+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */

+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */

+

+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)

+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */

+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */

+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */

+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */

+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */

+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */

+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)

+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */

+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */

+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)

+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */

+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */

+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)

+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */

+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)

+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */

+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)

+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */

+

+/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/

+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)

+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */

+

+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)

+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */

+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */

+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */

+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */

+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */

+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */

+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)

+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */

+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */

+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)

+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */

+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */

+

+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)

+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */

+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */

+

+#define USB_OTG_HCCHAR_MC_Pos                    (20U)

+#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */

+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */

+#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */

+#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */

+

+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)

+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */

+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */

+#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */

+#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */

+#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */

+#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */

+#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */

+#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */

+#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */

+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)

+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */

+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)

+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */

+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)

+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */

+

+/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/

+

+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)

+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */

+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */

+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */

+

+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)

+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */

+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */

+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */

+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */

+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */

+

+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)

+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */

+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */

+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */

+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */

+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)

+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */

+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */

+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)

+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */

+

+/********************  Bit definition forUSB_OTG_HCINT register  ********************/

+#define USB_OTG_HCINT_XFRC_Pos                   (0U)

+#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */

+#define USB_OTG_HCINT_CHH_Pos                    (1U)

+#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */

+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)

+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */

+#define USB_OTG_HCINT_STALL_Pos                  (3U)

+#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */

+#define USB_OTG_HCINT_NAK_Pos                    (4U)

+#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */

+#define USB_OTG_HCINT_ACK_Pos                    (5U)

+#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */

+#define USB_OTG_HCINT_NYET_Pos                   (6U)

+#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */

+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */

+#define USB_OTG_HCINT_TXERR_Pos                  (7U)

+#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */

+#define USB_OTG_HCINT_BBERR_Pos                  (8U)

+#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */

+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)

+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */

+#define USB_OTG_HCINT_DTERR_Pos                  (10U)

+#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */

+

+/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/

+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)

+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */

+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)

+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */

+#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)

+#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */

+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)

+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */

+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)

+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */

+#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)

+#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */

+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)

+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */

+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)

+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */

+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */

+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)

+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */

+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)

+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */

+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)

+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */

+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */

+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)

+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */

+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */

+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)

+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */

+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */

+

+/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/

+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)

+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */

+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)

+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */

+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)

+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */

+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)

+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */

+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)

+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */

+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)

+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */

+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)

+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */

+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */

+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)

+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */

+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)

+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */

+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)

+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */

+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)

+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */

+

+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/

+

+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)

+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */

+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)

+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */

+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)

+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */

+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */

+/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/

+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)

+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */

+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)

+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */

+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)

+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */

+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)

+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */

+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */

+#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */

+#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/

+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)

+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */

+

+/********************  Bit definition forUSB_OTG_HCDMA register  ********************/

+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)

+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */

+

+/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/

+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)

+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */

+

+/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/

+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)

+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */

+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)

+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/

+

+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)

+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */

+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)

+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */

+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */

+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)

+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */

+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */

+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)

+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */

+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)

+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */

+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */

+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)

+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */

+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */

+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)

+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */

+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */

+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)

+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */

+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */

+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)

+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */

+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */

+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)

+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */

+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)

+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */

+

+/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/

+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)

+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */

+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)

+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */

+#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)

+#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */

+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)

+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */

+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)

+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */

+#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)

+#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< OUT Status Phase Received interrupt */

+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)

+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */

+#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)

+#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */

+#define USB_OTG_DOEPINT_BERR_Pos                 (12U)

+#define USB_OTG_DOEPINT_BERR_Msk                 (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPINT_BERR                      USB_OTG_DOEPINT_BERR_Msk   /*!< Babble error interrupt */

+#define USB_OTG_DOEPINT_NAK_Pos                  (13U)

+#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */

+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)

+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */

+#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)

+#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */

+#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */

+

+/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/

+

+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)

+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */

+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)

+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */

+

+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)

+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */

+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */

+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */

+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition for PCGCCTL register  ********************/

+#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)

+#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */

+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */

+#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)

+#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */

+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */

+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)

+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */

+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/** @addtogroup Exported_macros

+  * @{

+  */

+

+/******************************* ADC Instances ********************************/

+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \

+                                       ((INSTANCE) == ADC2) || \

+                                       ((INSTANCE) == ADC3))

+

+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)

+

+#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) ||\

+                                          ((INSTANCE) == ADC3_COMMON))

+

+/******************************** COMP Instances ******************************/

+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \

+                                       ((INSTANCE) == COMP2))

+

+#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)

+/******************** COMP Instances with window mode capability **************/

+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)

+

+

+/******************************* CRC Instances ********************************/

+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

+

+/******************************* DAC Instances ********************************/

+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)

+/******************************* DCMI Instances *******************************/

+#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)

+

+/******************************* DELAYBLOCK Instances *******************************/

+#define IS_DLYB_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DLYB_SDMMC1) || \

+                                         ((INSTANCE) == DLYB_SDMMC2) || \

+                                         ((INSTANCE) == DLYB_QUADSPI))

+/****************************** DFSDM Instances *******************************/

+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \

+                                               ((INSTANCE) == DFSDM1_Filter1) || \

+                                               ((INSTANCE) == DFSDM1_Filter2) || \

+                                               ((INSTANCE) == DFSDM1_Filter3))

+

+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \

+                                                 ((INSTANCE) == DFSDM1_Channel1) || \

+                                                 ((INSTANCE) == DFSDM1_Channel2) || \

+                                                 ((INSTANCE) == DFSDM1_Channel3) || \

+                                                 ((INSTANCE) == DFSDM1_Channel4) || \

+                                                 ((INSTANCE) == DFSDM1_Channel5) || \

+                                                 ((INSTANCE) == DFSDM1_Channel6) || \

+                                                 ((INSTANCE) == DFSDM1_Channel7))

+/****************************** RAMECC Instances ******************************/

+#define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC1_Monitor1)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor2)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor3)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor4)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor5)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor1)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor2)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor3)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor4)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor5)   || \

+                                                  ((INSTANCE) == RAMECC3_Monitor1)   || \

+                                                  ((INSTANCE) == RAMECC3_Monitor2))

+

+/******************************** DMA Instances *******************************/

+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \

+                                       ((INSTANCE) == DMA1_Stream1)   || \

+                                       ((INSTANCE) == DMA1_Stream2)   || \

+                                       ((INSTANCE) == DMA1_Stream3)   || \

+                                       ((INSTANCE) == DMA1_Stream4)   || \

+                                       ((INSTANCE) == DMA1_Stream5)   || \

+                                       ((INSTANCE) == DMA1_Stream6)   || \

+                                       ((INSTANCE) == DMA1_Stream7)   || \

+                                       ((INSTANCE) == DMA2_Stream0)   || \

+                                       ((INSTANCE) == DMA2_Stream1)   || \

+                                       ((INSTANCE) == DMA2_Stream2)   || \

+                                       ((INSTANCE) == DMA2_Stream3)   || \

+                                       ((INSTANCE) == DMA2_Stream4)   || \

+                                       ((INSTANCE) == DMA2_Stream5)   || \

+                                       ((INSTANCE) == DMA2_Stream6)   || \

+                                       ((INSTANCE) == DMA2_Stream7)   || \

+                                       ((INSTANCE) == BDMA_Channel0) || \

+                                       ((INSTANCE) == BDMA_Channel1) || \

+                                       ((INSTANCE) == BDMA_Channel2) || \

+                                       ((INSTANCE) == BDMA_Channel3) || \

+                                       ((INSTANCE) == BDMA_Channel4) || \

+                                       ((INSTANCE) == BDMA_Channel5) || \

+                                       ((INSTANCE) == BDMA_Channel6) || \

+                                       ((INSTANCE) == BDMA_Channel7))

+

+/****************************** BDMA CHANNEL Instances ***************************/

+#define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \

+                                            ((INSTANCE) == BDMA_Channel1) || \

+                                            ((INSTANCE) == BDMA_Channel2) || \

+                                            ((INSTANCE) == BDMA_Channel3) || \

+                                            ((INSTANCE) == BDMA_Channel4) || \

+                                            ((INSTANCE) == BDMA_Channel5) || \

+                                            ((INSTANCE) == BDMA_Channel6) || \

+                                            ((INSTANCE) == BDMA_Channel7))

+

+/****************************** DMA DMAMUX ALL Instances ***************************/

+#define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)    || \

+                                               ((INSTANCE) == DMA1_Stream1)    || \

+                                               ((INSTANCE) == DMA1_Stream2)    || \

+                                               ((INSTANCE) == DMA1_Stream3)    || \

+                                               ((INSTANCE) == DMA1_Stream4)    || \

+                                               ((INSTANCE) == DMA1_Stream5)    || \

+                                               ((INSTANCE) == DMA1_Stream6)    || \

+                                               ((INSTANCE) == DMA1_Stream7)    || \

+                                               ((INSTANCE) == DMA2_Stream0)    || \

+                                               ((INSTANCE) == DMA2_Stream1)    || \

+                                               ((INSTANCE) == DMA2_Stream2)    || \

+                                               ((INSTANCE) == DMA2_Stream3)    || \

+                                               ((INSTANCE) == DMA2_Stream4)    || \

+                                               ((INSTANCE) == DMA2_Stream5)    || \

+                                               ((INSTANCE) == DMA2_Stream6)    || \

+                                               ((INSTANCE) == DMA2_Stream7)    || \

+                                               ((INSTANCE) == BDMA_Channel0)   || \

+                                               ((INSTANCE) == BDMA_Channel1)   || \

+                                               ((INSTANCE) == BDMA_Channel2)   || \

+                                               ((INSTANCE) == BDMA_Channel3)   || \

+                                               ((INSTANCE) == BDMA_Channel4)   || \

+                                               ((INSTANCE) == BDMA_Channel5)   || \

+                                               ((INSTANCE) == BDMA_Channel6)   || \

+                                               ((INSTANCE) == BDMA_Channel7))

+

+/****************************** BDMA DMAMUX Instances ***************************/

+#define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == BDMA_Channel0) || \

+                                                    ((INSTANCE) == BDMA_Channel1) || \

+                                                    ((INSTANCE) == BDMA_Channel2) || \

+                                                    ((INSTANCE) == BDMA_Channel3) || \

+                                                    ((INSTANCE) == BDMA_Channel4) || \

+                                                    ((INSTANCE) == BDMA_Channel5) || \

+                                                    ((INSTANCE) == BDMA_Channel6) || \

+                                                    ((INSTANCE) == BDMA_Channel7))

+

+/****************************** DMA STREAM Instances ***************************/

+#define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \

+                                          ((INSTANCE) == DMA1_Stream1)   || \

+                                          ((INSTANCE) == DMA1_Stream2)   || \

+                                          ((INSTANCE) == DMA1_Stream3)   || \

+                                          ((INSTANCE) == DMA1_Stream4)   || \

+                                          ((INSTANCE) == DMA1_Stream5)   || \

+                                          ((INSTANCE) == DMA1_Stream6)   || \

+                                          ((INSTANCE) == DMA1_Stream7)   || \

+                                          ((INSTANCE) == DMA2_Stream0)   || \

+                                          ((INSTANCE) == DMA2_Stream1)   || \

+                                          ((INSTANCE) == DMA2_Stream2)   || \

+                                          ((INSTANCE) == DMA2_Stream3)   || \

+                                          ((INSTANCE) == DMA2_Stream4)   || \

+                                          ((INSTANCE) == DMA2_Stream5)   || \

+                                          ((INSTANCE) == DMA2_Stream6)   || \

+                                          ((INSTANCE) == DMA2_Stream7))

+

+/****************************** DMA DMAMUX Instances ***************************/

+#define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)   || \

+                                                  ((INSTANCE) == DMA1_Stream1)   || \

+                                                  ((INSTANCE) == DMA1_Stream2)   || \

+                                                  ((INSTANCE) == DMA1_Stream3)   || \

+                                                  ((INSTANCE) == DMA1_Stream4)   || \

+                                                  ((INSTANCE) == DMA1_Stream5)   || \

+                                                  ((INSTANCE) == DMA1_Stream6)   || \

+                                                  ((INSTANCE) == DMA1_Stream7)   || \

+                                                  ((INSTANCE) == DMA2_Stream0)   || \

+                                                  ((INSTANCE) == DMA2_Stream1)   || \

+                                                  ((INSTANCE) == DMA2_Stream2)   || \

+                                                  ((INSTANCE) == DMA2_Stream3)   || \

+                                                  ((INSTANCE) == DMA2_Stream4)   || \

+                                                  ((INSTANCE) == DMA2_Stream5)   || \

+                                                  ((INSTANCE) == DMA2_Stream6)   || \

+                                                  ((INSTANCE) == DMA2_Stream7))

+

+/******************************** DMA Request Generator Instances **************/

+#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator1) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator2) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator3) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator4) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator5) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator6) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator7) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator0) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator1) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator2) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator3) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator4) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator5) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator6) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator7))

+

+/******************************* DMA2D Instances *******************************/

+#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)

+

+/******************************** MDMA Request Generator Instances **************/

+#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0)  || \

+                                               ((INSTANCE) == MDMA_Channel1)  || \

+                                               ((INSTANCE) == MDMA_Channel2)  || \

+                                               ((INSTANCE) == MDMA_Channel3)  || \

+                                               ((INSTANCE) == MDMA_Channel4)  || \

+                                               ((INSTANCE) == MDMA_Channel5)  || \

+                                               ((INSTANCE) == MDMA_Channel6)  || \

+                                               ((INSTANCE) == MDMA_Channel7)  || \

+                                               ((INSTANCE) == MDMA_Channel8)  || \

+                                               ((INSTANCE) == MDMA_Channel9)  || \

+                                               ((INSTANCE) == MDMA_Channel10) || \

+                                               ((INSTANCE) == MDMA_Channel11) || \

+                                               ((INSTANCE) == MDMA_Channel12) || \

+                                               ((INSTANCE) == MDMA_Channel13) || \

+                                               ((INSTANCE) == MDMA_Channel14) || \

+                                               ((INSTANCE) == MDMA_Channel15))

+

+/******************************* QUADSPI Instances *******************************/

+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)

+

+/******************************* FDCAN Instances ******************************/

+#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \

+                                             ((__INSTANCE__) == FDCAN2))

+

+#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)

+

+/******************************* GPIO Instances *******************************/

+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \

+                                        ((INSTANCE) == GPIOB) || \

+                                        ((INSTANCE) == GPIOC) || \

+                                        ((INSTANCE) == GPIOD) || \

+                                        ((INSTANCE) == GPIOE) || \

+                                        ((INSTANCE) == GPIOF) || \

+                                        ((INSTANCE) == GPIOG) || \

+                                        ((INSTANCE) == GPIOH) || \

+                                        ((INSTANCE) == GPIOI) || \

+                                        ((INSTANCE) == GPIOJ) || \

+                                        ((INSTANCE) == GPIOK))

+

+/******************************* GPIO AF Instances ****************************/

+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)

+

+/**************************** GPIO Lock Instances *****************************/

+/* On H7, all GPIO Bank support the Lock mechanism */

+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)

+

+/******************************** HSEM Instances *******************************/

+#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)

+/********************  Bit definition for HSEM_CR register  *****************/

+#define HSEM_CPU1_COREID    (0x00000003U) /* Semaphore Core CM7 ID */

+#define HSEM_CPU2_COREID    (0x00000001U) /* Semaphore Core CM4 ID */

+#define HSEM_CR_COREID_CPU1      (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)

+#define HSEM_CR_COREID_CPU2      (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos)

+#if defined(CORE_CM4)

+#define HSEM_CR_COREID_CURRENT   (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos)

+#else  /* CORE_CM7 */

+#define HSEM_CR_COREID_CURRENT   (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)

+#endif /* CORE_CM4 */

+

+#define HSEM_SEMID_MIN     (0U)       /* HSEM ID Min*/

+#define HSEM_SEMID_MAX     (31U)      /* HSEM ID Max */

+

+#define HSEM_PROCESSID_MIN (0U)       /* HSEM Process ID Min */

+#define HSEM_PROCESSID_MAX (255U)     /* HSEM Process ID Max */

+

+#define HSEM_CLEAR_KEY_MIN (0U)       /* HSEM clear Key Min value */

+#define HSEM_CLEAR_KEY_MAX (0xFFFFU)  /* HSEM clear Key Max value */

+

+/******************************** I2C Instances *******************************/

+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

+                                       ((INSTANCE) == I2C2) || \

+                                       ((INSTANCE) == I2C3) || \

+                                       ((INSTANCE) == I2C4))

+/************** I2C Instances : wakeup capability from stop modes *************/

+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)

+

+/****************************** SMBUS Instances *******************************/

+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

+                                         ((INSTANCE) == I2C2) || \

+                                         ((INSTANCE) == I2C3) || \

+                                         ((INSTANCE) == I2C4))

+/******************************** I2S Instances *******************************/

+#define IS_I2S_ALL_INSTANCE(INSTANCE)   (((INSTANCE) == SPI1) || \

+                                         ((INSTANCE) == SPI2) || \

+                                         ((INSTANCE) == SPI3))

+

+/****************************** LTDC Instances ********************************/

+#define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)

+

+/******************************* RNG Instances ********************************/

+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)

+

+/****************************** RTC Instances *********************************/

+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)

+

+/****************************** SDMMC Instances *********************************/

+#define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \

+                                           ((_INSTANCE_) == SDMMC2))

+

+/******************************** SMBUS Instances *****************************/

+#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)

+

+/******************************** SPI Instances *******************************/

+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \

+                                       ((INSTANCE) == SPI2) || \

+                                       ((INSTANCE) == SPI3) || \

+                                       ((INSTANCE) == SPI4) || \

+                                       ((INSTANCE) == SPI5) || \

+                                       ((INSTANCE) == SPI6))

+

+#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \

+                                           ((INSTANCE) == SPI2) || \

+                                           ((INSTANCE) == SPI3))

+

+/******************************** SWPMI Instances *****************************/

+#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)

+

+/****************** LPTIM Instances : All supported instances *****************/

+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \

+                                         ((INSTANCE) == LPTIM2) || \

+                                         ((INSTANCE) == LPTIM3) || \

+                                         ((INSTANCE) == LPTIM4) || \

+                                         ((INSTANCE) == LPTIM5))

+

+/****************** LPTIM Instances : supporting encoder interface **************/

+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \

+                                                           ((INSTANCE) == LPTIM2))

+

+/****************** TIM Instances : All supported instances *******************/

+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM6)   || \

+                                         ((INSTANCE) == TIM7)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM13)  || \

+                                         ((INSTANCE) == TIM14)  || \

+                                         ((INSTANCE) == TIM15)  || \

+                                         ((INSTANCE) == TIM16)  || \

+                                         ((INSTANCE) == TIM17))

+

+/************* TIM Instances : at least 1 capture/compare channel *************/

+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM13)  || \

+                                         ((INSTANCE) == TIM14)  || \

+                                         ((INSTANCE) == TIM15)  || \

+                                         ((INSTANCE) == TIM16)  || \

+                                         ((INSTANCE) == TIM17))

+

+/************ TIM Instances : at least 2 capture/compare channels *************/

+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM15))

+

+/************ TIM Instances : at least 3 capture/compare channels *************/

+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8))

+

+/************ TIM Instances : at least 4 capture/compare channels *************/

+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8))

+

+/************ TIM Instances : at least 5 capture/compare channels *************/

+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM8))

+/************ TIM Instances : at least 6 capture/compare channels *************/

+#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM8))

+

+/******************** TIM Instances : Advanced-control timers *****************/

+#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \

+                                                ((__INSTANCE__) == TIM8))

+

+/******************** TIM Instances : Advanced-control timers *****************/

+

+/******************* TIM Instances : Timer input XOR function *****************/

+#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : DMA requests generation (UDE) *************/

+#define IS_TIM_DMA_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM6)   || \

+                                           ((INSTANCE) == TIM7)   || \

+                                           ((INSTANCE) == TIM8)   || \

+                                           ((INSTANCE) == TIM15)  || \

+                                           ((INSTANCE) == TIM16)  || \

+                                           ((INSTANCE) == TIM17))

+

+/************ TIM Instances : DMA requests generation (CCxDE) *****************/

+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15)  || \

+                                            ((INSTANCE) == TIM16)  || \

+                                            ((INSTANCE) == TIM17))

+

+/************ TIM Instances : DMA requests generation (COMDE) *****************/

+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15))

+

+/******************** TIM Instances : DMA burst feature ***********************/

+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8))

+

+/*************** TIM Instances : external trigger reamp input available *******/

+#define IS_TIM_ETR_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : remapping capability **********************/

+#define IS_TIM_REMAP_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \

+                                          ((INSTANCE) == TIM2)  || \

+                                          ((INSTANCE) == TIM3)  || \

+                                          ((INSTANCE) == TIM5)  || \

+                                          ((INSTANCE) == TIM8)  || \

+                                          ((INSTANCE) == TIM16) || \

+                                          ((INSTANCE) == TIM17))

+

+/*************** TIM Instances : external trigger reamp input available *******/

+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                              ((INSTANCE) == TIM2)   || \

+                                              ((INSTANCE) == TIM3)   || \

+                                              ((INSTANCE) == TIM5)   || \

+                                              ((INSTANCE) == TIM8))

+

+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/

+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM6)   || \

+                                            ((INSTANCE) == TIM7)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15))

+

+/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/

+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM8)   || \

+                                           ((INSTANCE) == TIM12))

+

+/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/

+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM8))

+

+/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/

+#define IS_TIM_TISEL_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)   || \

+                                          ((INSTANCE) == TIM2)   || \

+                                          ((INSTANCE) == TIM3)   || \

+                                          ((INSTANCE) == TIM4)   || \

+                                          ((INSTANCE) == TIM5)   || \

+                                          ((INSTANCE) == TIM8)   || \

+                                          ((INSTANCE) == TIM15)  || \

+                                          ((INSTANCE) == TIM16)  || \

+                                          ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting commutation event *************/

+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \

+                                                     ((INSTANCE) == TIM8)    || \

+                                                     ((INSTANCE) == TIM15)   || \

+                                                     ((INSTANCE) == TIM16)   || \

+                                                     ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting encoder interface **************/

+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1)  || \

+                                                      ((__INSTANCE__) == TIM2)      || \

+                                                      ((__INSTANCE__) == TIM3)      || \

+                                                      ((__INSTANCE__) == TIM4)      || \

+                                                      ((__INSTANCE__) == TIM5)      || \

+                                                      ((__INSTANCE__) == TIM8))

+

+/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/

+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                                       ((INSTANCE) == TIM8))

+/******************* TIM Instances : output(s) available **********************/

+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \

+    ((((INSTANCE) == TIM1) &&                  \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4) ||          \

+      ((CHANNEL) == TIM_CHANNEL_5) ||          \

+      ((CHANNEL) == TIM_CHANNEL_6)))           \

+     ||                                        \

+     (((INSTANCE) == TIM2) &&                  \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM3) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1)||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM4) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM5) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM8) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4) ||          \

+      ((CHANNEL) == TIM_CHANNEL_5) ||          \

+      ((CHANNEL) == TIM_CHANNEL_6)))           \

+  ||                                           \

+     (((INSTANCE) == TIM12) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2)))           \

+  ||                                           \

+     (((INSTANCE) == TIM13) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM14) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM15) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+     ((CHANNEL) == TIM_CHANNEL_2)))            \

+  ||                                           \

+     (((INSTANCE) == TIM16) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM17) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1))))

+

+/****************** TIM Instances : supporting the break function *************/

+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\

+      (((INSTANCE) == TIM1)    || \

+      ((INSTANCE) == TIM8)     || \

+       ((INSTANCE) == TIM15)   || \

+       ((INSTANCE) == TIM16)   || \

+       ((INSTANCE) == TIM17))

+

+/************** TIM Instances : supporting Break source selection *************/

+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \

+                                               ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting complementary output(s) ********/

+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \

+   ((((INSTANCE) == TIM1) &&                    \

+     (((CHANNEL) == TIM_CHANNEL_1) ||           \

+      ((CHANNEL) == TIM_CHANNEL_2) ||           \

+      ((CHANNEL) == TIM_CHANNEL_3)))            \

+ ||                                             \

+      (((INSTANCE) == TIM8) &&                  \

+      (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||           \

+      ((CHANNEL) == TIM_CHANNEL_3)))            \

+    ||                                          \

+    (((INSTANCE) == TIM15) &&                   \

+      ((CHANNEL) == TIM_CHANNEL_1))             \

+    ||                                          \

+    (((INSTANCE) == TIM16) &&                   \

+     ((CHANNEL) == TIM_CHANNEL_1))              \

+    ||                                          \

+    (((INSTANCE) == TIM17) &&                   \

+     ((CHANNEL) == TIM_CHANNEL_1)))

+

+/****************** TIM Instances : supporting counting mode selection ********/

+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting repetition counter *************/

+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15)   || \

+   ((INSTANCE) == TIM16)   || \

+   ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting synchronization ****************/

+#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\

+    (((__INSTANCE__) == TIM1)    || \

+     ((__INSTANCE__) == TIM2)    || \

+     ((__INSTANCE__) == TIM3)    || \

+     ((__INSTANCE__) == TIM4)    || \

+     ((__INSTANCE__) == TIM5)    || \

+     ((__INSTANCE__) == TIM6)    || \

+     ((__INSTANCE__) == TIM8)    || \

+     ((__INSTANCE__) == TIM12)   || \

+     ((__INSTANCE__) == TIM15))

+

+/****************** TIM Instances : supporting clock division *****************/

+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15)   || \

+   ((INSTANCE) == TIM16)   || \

+   ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting external clock mode 1 for ETRF input */

+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting external clock mode 2 **********/

+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\

+ (((INSTANCE) == TIM1)     || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/

+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/

+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : supporting OCxREF clear *******************/

+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3))

+

+/****************** TIM Instances : TIM_32B_COUNTER ***************************/

+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM5))

+

+/****************** TIM Instances : TIM_BKIN2 ***************************/

+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting Hall sensor interface **********/

+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)  || \

+                                                             ((__INSTANCE__) == TIM2)  || \

+                                                             ((__INSTANCE__) == TIM3)  || \

+                                                             ((__INSTANCE__) == TIM4)  || \

+                                                             ((__INSTANCE__) == TIM5)  || \

+                                                             ((__INSTANCE__) == TIM15) || \

+                                                             ((__INSTANCE__) == TIM8))

+

+/****************************** HRTIM Instances *******************************/

+#define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))

+

+/******************** USART Instances : Synchronous mode **********************/

+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                     ((INSTANCE) == USART2) || \

+                                     ((INSTANCE) == USART3) || \

+                                     ((INSTANCE) == USART6))

+

+/******************** USART Instances : SPI slave mode ************************/

+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                              ((INSTANCE) == USART2) || \

+                                              ((INSTANCE) == USART3) || \

+                                              ((INSTANCE) == USART6))

+

+/******************** UART Instances : Asynchronous mode **********************/

+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                    ((INSTANCE) == USART2) || \

+                                    ((INSTANCE) == USART3) || \

+                                    ((INSTANCE) == UART4)  || \

+                                    ((INSTANCE) == UART5)  || \

+                                    ((INSTANCE) == USART6) || \

+                                    ((INSTANCE) == UART7)  || \

+                                    ((INSTANCE) == UART8))

+

+/******************** UART Instances : FIFO mode.******************************/

+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                         ((INSTANCE) == USART2) || \

+                                         ((INSTANCE) == USART3) || \

+                                         ((INSTANCE) == UART4)  || \

+                                         ((INSTANCE) == UART5)  || \

+                                         ((INSTANCE) == USART6) || \

+                                         ((INSTANCE) == UART7)  || \

+                                         ((INSTANCE) == UART8))

+

+/****************** UART Instances : Auto Baud Rate detection *****************/

+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                            ((INSTANCE) == USART2) || \

+                                                            ((INSTANCE) == USART3) || \

+                                                            ((INSTANCE) == UART4)  || \

+                                                            ((INSTANCE) == UART5)  || \

+                                                            ((INSTANCE) == USART6) || \

+                                                            ((INSTANCE) == UART7)  || \

+                                                            ((INSTANCE) == UART8))

+

+/*********************** UART Instances : Driver Enable ***********************/

+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                  ((INSTANCE) == USART2) || \

+                                                  ((INSTANCE) == USART3) || \

+                                                  ((INSTANCE) == UART4)  || \

+                                                  ((INSTANCE) == UART5)  || \

+                                                  ((INSTANCE) == USART6) || \

+                                                  ((INSTANCE) == UART7)  || \

+                                                  ((INSTANCE) == UART8)  || \

+                                                  ((INSTANCE) == LPUART1))

+

+/********************* UART Instances : Half-Duplex mode **********************/

+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                               ((INSTANCE) == USART2) || \

+                                               ((INSTANCE) == USART3) || \

+                                               ((INSTANCE) == UART4)  || \

+                                               ((INSTANCE) == UART5)  || \

+                                               ((INSTANCE) == USART6) || \

+                                               ((INSTANCE) == UART7)  || \

+                                               ((INSTANCE) == UART8)  || \

+                                               ((INSTANCE) == LPUART1))

+

+/******************* UART Instances : Hardware Flow control *******************/

+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                           ((INSTANCE) == USART2) || \

+                                           ((INSTANCE) == USART3) || \

+                                           ((INSTANCE) == UART4)  || \

+                                           ((INSTANCE) == UART5)  || \

+                                           ((INSTANCE) == USART6) || \

+                                           ((INSTANCE) == UART7)  || \

+                                           ((INSTANCE) == UART8)  || \

+                                           ((INSTANCE) == LPUART1))

+

+/************************* UART Instances : LIN mode **************************/

+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                        ((INSTANCE) == USART2) || \

+                                        ((INSTANCE) == USART3) || \

+                                        ((INSTANCE) == UART4)  || \

+                                        ((INSTANCE) == UART5)  || \

+                                        ((INSTANCE) == USART6) || \

+                                        ((INSTANCE) == UART7)  || \

+                                        ((INSTANCE) == UART8))

+

+/****************** UART Instances : Wake-up from Stop mode *******************/

+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                    ((INSTANCE) == USART2) || \

+                                                    ((INSTANCE) == USART3) || \

+                                                    ((INSTANCE) == UART4)  || \

+                                                    ((INSTANCE) == UART5)  || \

+                                                    ((INSTANCE) == USART6) || \

+                                                    ((INSTANCE) == UART7)  || \

+                                                    ((INSTANCE) == UART8)  || \

+                                                    ((INSTANCE) == LPUART1))

+

+/************************* UART Instances : IRDA mode *************************/

+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                    ((INSTANCE) == USART2) || \

+                                    ((INSTANCE) == USART3) || \

+                                    ((INSTANCE) == UART4)  || \

+                                    ((INSTANCE) == UART5)  || \

+                                    ((INSTANCE) == USART6) || \

+                                    ((INSTANCE) == UART7)  || \

+                                    ((INSTANCE) == UART8))

+

+/********************* USART Instances : Smard card mode **********************/

+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                         ((INSTANCE) == USART2) || \

+                                         ((INSTANCE) == USART3) || \

+                                         ((INSTANCE) == USART6))

+

+/****************************** LPUART Instance *******************************/

+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)

+

+/****************************** IWDG Instances ********************************/

+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2))

+/****************************** USB Instances ********************************/

+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)

+

+/****************************** WWDG Instances ********************************/

+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == WWDG1) || \

+                                         ((INSTANCE) == WWDG2))

+/****************************** MDIOS Instances ********************************/

+#define IS_MDIOS_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == MDIOS)

+

+/****************************** CEC Instances *********************************/

+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)

+

+/****************************** SAI Instances ********************************/

+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \

+                    ((INSTANCE) == SAI1_Block_B) || \

+                     ((INSTANCE) == SAI2_Block_A) || \

+                     ((INSTANCE) == SAI2_Block_B) || \

+                     ((INSTANCE) == SAI3_Block_A) || \

+                     ((INSTANCE) == SAI3_Block_B) || \

+                     ((INSTANCE) == SAI4_Block_A) || \

+                     ((INSTANCE) == SAI4_Block_B))

+

+/****************************** SPDIFRX Instances ********************************/

+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)

+

+/****************************** OPAMP Instances *******************************/

+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \

+                                         ((INSTANCE) == OPAMP2))

+

+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)

+

+/*********************** USB OTG PCD Instances ********************************/

+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \

+                                        ((INSTANCE) == USB_OTG_HS))

+

+/*********************** USB OTG HCD Instances ********************************/

+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \

+                                       ((INSTANCE) == USB_OTG_HS))

+

+/******************************************************************************/

+/*  For a painless codes migration between the STM32H7xx device product       */

+/*  lines, or with STM32F7xx devices the aliases defined below are put        */

+/*   in place to overcome the differences in the interrupt handlers and IRQn  */

+/*   definitions. No need to update developed interrupt code when moving      */

+/*  across product lines within the same STM32H7 Family                       */

+/******************************************************************************/

+

+/* Aliases for __IRQn */

+#define  RNG_IRQn                       HASH_RNG_IRQn

+#define  TIM1_BRK_TIM9_IRQn             TIM1_BRK_IRQn

+#define  TIM1_UP_TIM10_IRQn             TIM1_UP_IRQn

+#define  TIM1_TRG_COM_TIM11_IRQn        TIM1_TRG_COM_IRQn

+#define  PVD_IRQn                       PVD_AVD_IRQn

+

+

+

+/* Aliases for __IRQHandler */

+#define   RNG_IRQHandler               HASH_RNG_IRQHandler

+#define TIM1_BRK_TIM9_IRQHandler       TIM1_BRK_IRQHandler

+#define TIM1_UP_TIM9_IRQHandler        TIM1_UP_IRQHandler

+#define TIM1_TRG_COM_TIM11_IRQHandler  TIM1_TRG_COM_IRQHandler

+#define PVD_IRQHandler                 PVD_AVD_IRQHandler

+

+/* Aliases for COMP __IRQHandler */

+#define COMP_IRQHandler                COMP1_IRQHandler

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif /* __cplusplus */

+

+#endif /* STM32H755xx_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h757xx.h b/bsps/arm/stm32h7/include/stm32h757xx.h
new file mode 100644
index 0000000000..48fbcff97f
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h757xx.h
@@ -0,0 +1,30521 @@
+/**

+  ******************************************************************************

+  * @file    stm32h757xx.h

+  * @author  MCD Application Team

+  * @brief   CMSIS STM32H757xx Device Peripheral Access Layer Header File.

+  *

+  *          This file contains:

+  *           - Data structures and the address mapping for all peripherals

+  *           - Peripheral's registers declarations and bits definition

+  *           - Macros to access peripheral's registers hardware

+  *

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/** @addtogroup CMSIS_Device

+  * @{

+  */

+

+/** @addtogroup stm32h757xx

+  * @{

+  */

+

+#ifndef STM32H757xx_H

+#define STM32H757xx_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif /* __cplusplus */

+

+/** @addtogroup Peripheral_interrupt_number_definition

+  * @{

+  */

+

+/**

+ * @brief STM32H7XX Interrupt Number Definition, according to the selected device

+ *        in @ref Library_configuration_section

+ */

+typedef enum

+{

+/******  Cortex-M Processor Exceptions Numbers *****************************************************************/

+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */

+  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */

+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */

+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */

+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */

+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M SV Call Interrupt                                     */

+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M Debug Monitor Interrupt                               */

+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M Pend SV Interrupt                                     */

+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M System Tick Interrupt                                 */

+/******  STM32 specific Interrupt Numbers **********************************************************************/

+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)                   */

+  PVD_AVD_IRQn                = 1,      /*!< PVD/AVD through EXTI Line detection Interrupt                     */

+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */

+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */

+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */

+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */

+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */

+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */

+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */

+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */

+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */

+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */

+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */

+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */

+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */

+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */

+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */

+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */

+  ADC_IRQn                    = 18,     /*!< ADC1 and  ADC2 global Interrupts                                  */

+  FDCAN1_IT0_IRQn             = 19,     /*!< FDCAN1 Interrupt line 0                                           */

+  FDCAN2_IT0_IRQn             = 20,     /*!< FDCAN2 Interrupt line 0                                           */

+  FDCAN1_IT1_IRQn             = 21,     /*!< FDCAN1 Interrupt line 1                                           */

+  FDCAN2_IT1_IRQn             = 22,     /*!< FDCAN2 Interrupt line 1                                           */

+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */

+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                              */

+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                             */

+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt                            */

+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */

+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */

+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */

+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */

+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */

+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */

+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */

+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */

+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */

+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */

+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */

+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */

+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */

+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */

+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */

+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */

+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */

+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */

+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */

+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */

+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */

+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */

+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */

+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */

+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */

+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */

+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */

+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */

+  DMA2_Stream0_IRQn           = 56,     /*!<   DMA2 Stream 0 global Interrupt                                  */

+  DMA2_Stream1_IRQn           = 57,     /*!<   DMA2 Stream 1 global Interrupt                                  */

+  DMA2_Stream2_IRQn           = 58,     /*!<   DMA2 Stream 2 global Interrupt                                  */

+  DMA2_Stream3_IRQn           = 59,     /*!<   DMA2 Stream 3 global Interrupt                                  */

+  DMA2_Stream4_IRQn           = 60,     /*!<   DMA2 Stream 4 global Interrupt                                  */

+  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */

+  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */

+  FDCAN_CAL_IRQn              = 63,     /*!< FDCAN Calibration unit Interrupt                                  */

+  CM7_SEV_IRQn                = 64,     /*!< CM7 Send event interrupt for CM4                                  */

+  CM4_SEV_IRQn                = 65,     /*!< CM4 Send event interrupt for CM7                                  */

+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */

+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */

+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */

+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */

+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */

+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */

+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */

+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */

+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */

+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */

+  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */

+  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */

+  HASH_RNG_IRQn               = 80,     /*!< HASH and RNG global interrupt                                     */

+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */

+  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */

+  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */

+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */

+  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */

+  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */

+  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */

+  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */

+  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */

+  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */

+  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */

+  QUADSPI_IRQn                = 92,     /*!< Quad SPI global interrupt                                         */

+  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */

+  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */

+  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */

+  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */

+  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */

+  OTG_FS_EP1_OUT_IRQn         = 98,     /*!< USB OTG HS2 global interrupt                                      */

+  OTG_FS_EP1_IN_IRQn          = 99,     /*!< USB OTG HS2 End Point 1 Out global interrupt                      */

+  OTG_FS_WKUP_IRQn            = 100,    /*!< USB OTG HS2 End Point 1 In global interrupt                       */

+  OTG_FS_IRQn                 = 101,    /*!< USB OTG HS2 Wakeup through EXTI interrupt                         */

+  DMAMUX1_OVR_IRQn            = 102,    /*!<DMAMUX1 Overrun interrupt                                          */

+  HRTIM1_Master_IRQn          = 103,    /*!< HRTIM Master Timer global Interrupts                              */

+  HRTIM1_TIMA_IRQn            = 104,    /*!< HRTIM Timer A global Interrupt                                    */

+  HRTIM1_TIMB_IRQn            = 105,    /*!< HRTIM Timer B global Interrupt                                    */

+  HRTIM1_TIMC_IRQn            = 106,    /*!< HRTIM Timer C global Interrupt                                    */

+  HRTIM1_TIMD_IRQn            = 107,    /*!< HRTIM Timer D global Interrupt                                    */

+  HRTIM1_TIME_IRQn            = 108,    /*!< HRTIM Timer E global Interrupt                                    */

+  HRTIM1_FLT_IRQn             = 109,    /*!< HRTIM Fault global Interrupt                                      */

+  DFSDM1_FLT0_IRQn            = 110,    /*!<DFSDM Filter1 Interrupt                                            */

+  DFSDM1_FLT1_IRQn            = 111,    /*!<DFSDM Filter2 Interrupt                                            */

+  DFSDM1_FLT2_IRQn            = 112,    /*!<DFSDM Filter3 Interrupt                                            */

+  DFSDM1_FLT3_IRQn            = 113,    /*!<DFSDM Filter4 Interrupt                                            */

+  SAI3_IRQn                   = 114,    /*!< SAI3 global Interrupt                                             */

+  SWPMI1_IRQn                 = 115,    /*!< Serial Wire Interface 1 global interrupt                          */

+  TIM15_IRQn                  = 116,    /*!< TIM15 global Interrupt                                            */

+  TIM16_IRQn                  = 117,    /*!< TIM16 global Interrupt                                            */

+  TIM17_IRQn                  = 118,    /*!< TIM17 global Interrupt                                            */

+  MDIOS_WKUP_IRQn             = 119,    /*!< MDIOS Wakeup  Interrupt                                           */

+  MDIOS_IRQn                  = 120,    /*!< MDIOS global Interrupt                                            */

+  JPEG_IRQn                   = 121,    /*!< JPEG global Interrupt                                             */

+  MDMA_IRQn                   = 122,    /*!< MDMA global Interrupt                                             */

+  DSI_IRQn                    = 123,    /*!< DSI global Interrupt                                              */

+  SDMMC2_IRQn                 = 124,    /*!< SDMMC2 global Interrupt                                           */

+  HSEM1_IRQn                  = 125,    /*!< HSEM1 global Interrupt                                            */

+  HSEM2_IRQn                  = 126,    /*!< HSEM2 global Interrupt                                            */

+  ADC3_IRQn                   = 127,    /*!< ADC3 global Interrupt                                             */

+  DMAMUX2_OVR_IRQn            = 128,    /*!<DMAMUX2 Overrun interrupt                                          */

+  BDMA_Channel0_IRQn          = 129,    /*!< BDMA Channel 0 global Interrupt                                   */

+  BDMA_Channel1_IRQn          = 130,    /*!< BDMA Channel 1 global Interrupt                                   */

+  BDMA_Channel2_IRQn          = 131,    /*!< BDMA Channel 2 global Interrupt                                   */

+  BDMA_Channel3_IRQn          = 132,    /*!< BDMA Channel 3 global Interrupt                                   */

+  BDMA_Channel4_IRQn          = 133,    /*!< BDMA Channel 4 global Interrupt                                   */

+  BDMA_Channel5_IRQn          = 134,    /*!< BDMA Channel 5 global Interrupt                                   */

+  BDMA_Channel6_IRQn          = 135,    /*!< BDMA Channel 6 global Interrupt                                   */

+  BDMA_Channel7_IRQn          = 136,    /*!< BDMA Channel 7 global Interrupt                                   */

+  COMP_IRQn                   = 137 ,   /*!< COMP global Interrupt                                             */

+  LPTIM2_IRQn                 = 138,    /*!< LP TIM2 global interrupt                                          */

+  LPTIM3_IRQn                 = 139,    /*!< LP TIM3 global interrupt                                          */

+  LPTIM4_IRQn                 = 140,    /*!< LP TIM4 global interrupt                                          */

+  LPTIM5_IRQn                 = 141,    /*!< LP TIM5 global interrupt                                          */

+  LPUART1_IRQn                = 142,    /*!< LP UART1 interrupt                                                */

+  WWDG_RST_IRQn               = 143,    /*!<Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */

+  CRS_IRQn                    = 144,    /*!< Clock Recovery Global Interrupt                                   */

+  ECC_IRQn                    = 145,    /*!< ECC diagnostic Global Interrupt                                   */

+  SAI4_IRQn                   = 146,    /*!< SAI4 global interrupt                                             */

+  HOLD_CORE_IRQn              = 148,    /*!< Hold core interrupt                                               */

+  WAKEUP_PIN_IRQn             = 149,    /*!< Interrupt for all 6 wake-up pins                                  */

+} IRQn_Type;

+

+/**

+  * @}

+  */

+

+/** @addtogroup Configuration_section_for_CMSIS

+  * @{

+  */

+#define DUAL_CORE  /*!< Dual core line feature */

+

+#define SMPS       /*!< Switched mode power supply feature */

+

+

+

+/**

+  * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals

+   */

+#ifdef CORE_CM4

+#define __CM4_REV                 0x0001  /*!< Cortex-M4 revision r0p1                       */

+#define __MPU_PRESENT             1       /*!< CM4 provides an MPU                           */

+#define __NVIC_PRIO_BITS          4       /*!< CM4 uses 4 Bits for the Priority Levels       */

+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */

+#define __FPU_PRESENT             1       /*!< FPU present                                   */

+

+#include "core_cm4.h"                     /*!< Cortex-M4 processor and core peripherals      */

+#else  /* CORE_CM7 */

+#ifdef CORE_CM7

+#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */

+#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */

+#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */

+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */

+#define __FPU_PRESENT             1       /*!< FPU present                                   */

+#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */

+#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */

+#include "core_cm7.h"                 /*!< Cortex-M7 processor and core peripherals          */

+#else  /* UNKNOWN_CORE */

+#error Please #define CORE_CM4 or CORE_CM7

+#endif /* CORE_CM7 */

+#endif /* CORE_CM4 */

+

+/**

+  * @}

+  */

+

+

+

+

+

+#include "system_stm32h7xx.h"

+#include <stdint.h>

+

+/** @addtogroup Peripheral_registers_structures

+  * @{

+  */

+

+/**

+  * @brief Analog to Digital Converter

+  */

+

+typedef struct

+{

+  __IO uint32_t ISR;              /*!< ADC Interrupt and Status Register,                          Address offset: 0x00 */

+  __IO uint32_t IER;              /*!< ADC Interrupt Enable Register,                              Address offset: 0x04 */

+  __IO uint32_t CR;               /*!< ADC control register,                                       Address offset: 0x08 */

+  __IO uint32_t CFGR;             /*!< ADC Configuration register,                                 Address offset: 0x0C */

+  __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                               Address offset: 0x10 */

+  __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                                 Address offset: 0x14 */

+  __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                                 Address offset: 0x18 */

+  __IO uint32_t PCSEL;            /*!< ADC pre-channel selection,                                  Address offset: 0x1C */

+  __IO uint32_t LTR1;             /*!< ADC watchdog Lower threshold register 1,                    Address offset: 0x20 */

+  __IO uint32_t HTR1;             /*!< ADC watchdog higher threshold register 1,                   Address offset: 0x24 */

+  uint32_t      RESERVED1;        /*!< Reserved, 0x028                                                                  */

+  uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                                  */

+  __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                            Address offset: 0x30 */

+  __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                            Address offset: 0x34 */

+  __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                            Address offset: 0x38 */

+  __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                            Address offset: 0x3C */

+  __IO uint32_t DR;               /*!< ADC regular data register,                                  Address offset: 0x40 */

+  uint32_t      RESERVED3;        /*!< Reserved, 0x044                                                                  */

+  uint32_t      RESERVED4;        /*!< Reserved, 0x048                                                                  */

+  __IO uint32_t JSQR;             /*!< ADC injected sequence register,                             Address offset: 0x4C */

+  uint32_t      RESERVED5[4];     /*!< Reserved, 0x050 - 0x05C                                                          */

+  __IO uint32_t OFR1;             /*!< ADC offset register 1,                                      Address offset: 0x60 */

+  __IO uint32_t OFR2;             /*!< ADC offset register 2,                                      Address offset: 0x64 */

+  __IO uint32_t OFR3;             /*!< ADC offset register 3,                                      Address offset: 0x68 */

+  __IO uint32_t OFR4;             /*!< ADC offset register 4,                                      Address offset: 0x6C */

+  uint32_t      RESERVED6[4];     /*!< Reserved, 0x070 - 0x07C                                                          */

+  __IO uint32_t JDR1;             /*!< ADC injected data register 1,                               Address offset: 0x80 */

+  __IO uint32_t JDR2;             /*!< ADC injected data register 2,                               Address offset: 0x84 */

+  __IO uint32_t JDR3;             /*!< ADC injected data register 3,                               Address offset: 0x88 */

+  __IO uint32_t JDR4;             /*!< ADC injected data register 4,                               Address offset: 0x8C */

+  uint32_t      RESERVED7[4];     /*!< Reserved, 0x090 - 0x09C                                                          */

+  __IO uint32_t AWD2CR;           /*!< ADC  Analog Watchdog 2 Configuration Register,              Address offset: 0xA0 */

+  __IO uint32_t AWD3CR;           /*!< ADC  Analog Watchdog 3 Configuration Register,              Address offset: 0xA4 */

+  uint32_t      RESERVED8;        /*!< Reserved, 0x0A8                                                                  */

+  uint32_t      RESERVED9;        /*!< Reserved, 0x0AC                                                                  */

+  __IO uint32_t LTR2;             /*!< ADC watchdog Lower threshold register 2,                    Address offset: 0xB0 */

+  __IO uint32_t HTR2;             /*!< ADC watchdog Higher threshold register 2,                   Address offset: 0xB4 */

+  __IO uint32_t LTR3;             /*!< ADC watchdog Lower threshold register 3,                    Address offset: 0xB8 */

+  __IO uint32_t HTR3;             /*!< ADC watchdog Higher threshold register 3,                   Address offset: 0xBC */

+  __IO uint32_t DIFSEL;           /*!< ADC  Differential Mode Selection Register,                  Address offset: 0xC0 */

+  __IO uint32_t CALFACT;          /*!< ADC  Calibration Factors,                                   Address offset: 0xC4 */

+  __IO uint32_t CALFACT2;         /*!< ADC  Linearity Calibration Factors,                         Address offset: 0xC8 */

+} ADC_TypeDef;

+

+

+typedef struct

+{

+__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */

+uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */

+__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */

+__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */

+__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */

+

+} ADC_Common_TypeDef;

+

+/**

+  * @brief ART

+  */

+

+typedef struct

+{

+  __IO uint32_t  CTR;        /*!< ART accelerator - control register */

+}ART_TypeDef;

+

+/**

+  * @brief VREFBUF

+  */

+

+typedef struct

+{

+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */

+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */

+} VREFBUF_TypeDef;

+

+

+/**

+  * @brief FD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */

+  __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */

+  __IO uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */

+  __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */

+  __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */

+  __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */

+  __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */

+  __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */

+  __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */

+  __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */

+  __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */

+  __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */

+  __IO uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */

+  __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */

+  __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */

+  __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */

+  __IO uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */

+  __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */

+  __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */

+  __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */

+  __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */

+  __IO uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */

+  __IO uint32_t GFC;          /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */

+  __IO uint32_t SIDFC;        /*!< FDCAN Standard ID Filter Configuration register,                 Address offset: 0x084 */

+  __IO uint32_t XIDFC;        /*!< FDCAN Extended ID Filter Configuration register,                 Address offset: 0x088 */

+  __IO uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */

+  __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x090 */

+  __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x094 */

+  __IO uint32_t NDAT1;        /*!< FDCAN New Data 1 register,                                       Address offset: 0x098 */

+  __IO uint32_t NDAT2;        /*!< FDCAN New Data 2 register,                                       Address offset: 0x09C */

+  __IO uint32_t RXF0C;        /*!< FDCAN Rx FIFO 0 Configuration register,                          Address offset: 0x0A0 */

+  __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x0A4 */

+  __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x0A8 */

+  __IO uint32_t RXBC;         /*!< FDCAN Rx Buffer Configuration register,                          Address offset: 0x0AC */

+  __IO uint32_t RXF1C;        /*!< FDCAN Rx FIFO 1 Configuration register,                          Address offset: 0x0B0 */

+  __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x0B4 */

+  __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x0B8 */

+  __IO uint32_t RXESC;        /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register,        Address offset: 0x0BC */

+  __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */

+  __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */

+  __IO uint32_t TXESC;        /*!< FDCAN Tx Buffer Element Size Configuration register,             Address offset: 0x0C8 */

+  __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0CC */

+  __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0D0 */

+  __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D4 */

+  __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D8 */

+  __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0DC */

+  __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0E0 */

+  __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */

+  __IO uint32_t RESERVED6[2]; /*!< Reserved,                                                                0x0E8 - 0x0EC */

+  __IO uint32_t TXEFC;        /*!< FDCAN Tx Event FIFO Configuration register,                      Address offset: 0x0F0 */

+  __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0F4 */

+  __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0F8 */

+  __IO uint32_t RESERVED7;    /*!< Reserved,                                                                        0x0FC */

+} FDCAN_GlobalTypeDef;

+

+/**

+  * @brief TTFD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t TTTMC;          /*!< TT Trigger Memory Configuration register,    Address offset: 0x100 */

+  __IO uint32_t TTRMC;          /*!< TT Reference Message Configuration register, Address offset: 0x104 */

+  __IO uint32_t TTOCF;          /*!< TT Operation Configuration register,         Address offset: 0x108 */

+  __IO uint32_t TTMLM;          /*!< TT Matrix Limits register,                   Address offset: 0x10C */

+  __IO uint32_t TURCF;          /*!< TUR Configuration register,                  Address offset: 0x110 */

+  __IO uint32_t TTOCN;          /*!< TT Operation Control register,               Address offset: 0x114 */

+  __IO uint32_t TTGTP;          /*!< TT Global Time Preset register,              Address offset: 0x118 */

+  __IO uint32_t TTTMK;          /*!< TT Time Mark register,                       Address offset: 0x11C */

+  __IO uint32_t TTIR;           /*!< TT Interrupt register,                       Address offset: 0x120 */

+  __IO uint32_t TTIE;           /*!< TT Interrupt Enable register,                Address offset: 0x124 */

+  __IO uint32_t TTILS;          /*!< TT Interrupt Line Select register,           Address offset: 0x128 */

+  __IO uint32_t TTOST;          /*!< TT Operation Status register,                Address offset: 0x12C */

+  __IO uint32_t TURNA;          /*!< TT TUR Numerator Actual register,            Address offset: 0x130 */

+  __IO uint32_t TTLGT;          /*!< TT Local and Global Time register,           Address offset: 0x134 */

+  __IO uint32_t TTCTC;          /*!< TT Cycle Time and Count register,            Address offset: 0x138 */

+  __IO uint32_t TTCPT;          /*!< TT Capture Time register,                    Address offset: 0x13C */

+  __IO uint32_t TTCSM;          /*!< TT Cycle Sync Mark register,                 Address offset: 0x140 */

+  __IO uint32_t RESERVED1[111]; /*!< Reserved,                                            0x144 - 0x2FC */

+  __IO uint32_t TTTS;           /*!< TT Trigger Select register,                  Address offset: 0x300 */

+} TTCAN_TypeDef;

+

+/**

+  * @brief FD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t CREL;  /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */

+  __IO uint32_t CCFG;  /*!< Calibration Configuration register,           Address offset: 0x04 */

+  __IO uint32_t CSTAT; /*!< Calibration Status register,                  Address offset: 0x08 */

+  __IO uint32_t CWD;   /*!< Calibration Watchdog register,                Address offset: 0x0C */

+  __IO uint32_t IR;    /*!< CCU Interrupt register,                       Address offset: 0x10 */

+  __IO uint32_t IE;    /*!< CCU Interrupt Enable register,                Address offset: 0x14 */

+} FDCAN_ClockCalibrationUnit_TypeDef;

+

+

+/**

+  * @brief Consumer Electronics Control

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;           /*!< CEC control register,              Address offset:0x00 */

+  __IO uint32_t CFGR;         /*!< CEC configuration register,        Address offset:0x04 */

+  __IO uint32_t TXDR;         /*!< CEC Tx data register ,             Address offset:0x08 */

+  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,              Address offset:0x0C */

+  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register, Address offset:0x10 */

+  __IO uint32_t IER;          /*!< CEC interrupt enable register,     Address offset:0x14 */

+}CEC_TypeDef;

+

+/**

+  * @brief CRC calculation unit

+  */

+

+typedef struct

+{

+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */

+  __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */

+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */

+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */

+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */

+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */

+} CRC_TypeDef;

+

+

+/**

+  * @brief Clock Recovery System

+  */

+typedef struct

+{

+__IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */

+__IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */

+__IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */

+__IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */

+} CRS_TypeDef;

+

+

+/**

+  * @brief Digital to Analog Converter

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */

+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */

+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */

+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */

+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */

+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */

+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */

+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */

+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */

+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */

+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */

+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */

+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */

+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */

+  __IO uint32_t CCR;      /*!< DAC calibration control register,                        Address offset: 0x38 */

+  __IO uint32_t MCR;      /*!< DAC mode control register,                               Address offset: 0x3C */

+  __IO uint32_t SHSR1;    /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */

+  __IO uint32_t SHSR2;    /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */

+  __IO uint32_t SHHR;     /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */

+  __IO uint32_t SHRR;     /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */

+} DAC_TypeDef;

+

+/**

+  * @brief DFSDM module registers

+  */

+typedef struct

+{

+  __IO uint32_t FLTCR1;          /*!< DFSDM control register1,                          Address offset: 0x100 */

+  __IO uint32_t FLTCR2;          /*!< DFSDM control register2,                          Address offset: 0x104 */

+  __IO uint32_t FLTISR;          /*!< DFSDM interrupt and status register,              Address offset: 0x108 */

+  __IO uint32_t FLTICR;          /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */

+  __IO uint32_t FLTJCHGR;        /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */

+  __IO uint32_t FLTFCR;          /*!< DFSDM filter control register,                    Address offset: 0x114 */

+  __IO uint32_t FLTJDATAR;       /*!< DFSDM data register for injected group,           Address offset: 0x118 */

+  __IO uint32_t FLTRDATAR;       /*!< DFSDM data register for regular group,            Address offset: 0x11C */

+  __IO uint32_t FLTAWHTR;        /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */

+  __IO uint32_t FLTAWLTR;        /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */

+  __IO uint32_t FLTAWSR;         /*!< DFSDM analog watchdog status register             Address offset: 0x128 */

+  __IO uint32_t FLTAWCFR;        /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */

+  __IO uint32_t FLTEXMAX;        /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */

+  __IO uint32_t FLTEXMIN;        /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */

+  __IO uint32_t FLTCNVTIMR;      /*!< DFSDM conversion timer,                           Address offset: 0x138 */

+} DFSDM_Filter_TypeDef;

+

+/**

+  * @brief DFSDM channel configuration registers

+  */

+typedef struct

+{

+  __IO uint32_t CHCFGR1;      /*!< DFSDM channel configuration register1,            Address offset: 0x00 */

+  __IO uint32_t CHCFGR2;      /*!< DFSDM channel configuration register2,            Address offset: 0x04 */

+  __IO uint32_t CHAWSCDR;     /*!< DFSDM channel analog watchdog and

+                                   short circuit detector register,                  Address offset: 0x08 */

+  __IO uint32_t CHWDATAR;     /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */

+  __IO uint32_t CHDATINR;     /*!< DFSDM channel data input register,                Address offset: 0x10 */

+} DFSDM_Channel_TypeDef;

+

+/**

+  * @brief Debug MCU

+  */

+typedef struct

+{

+  __IO uint32_t IDCODE;        /*!< MCU device ID code,                     Address offset: 0x00 */

+  __IO uint32_t CR;            /*!< Debug MCU configuration register,       Address offset: 0x04 */

+  __IO uint32_t  RESERVED4[11]; /*!< Reserved,                               Address offset: 0x08 */

+  __IO uint32_t APB3FZ1;     /*!< Debug MCU APB3FZ1 freeze register,    Address offset: 0x34 */

+  __IO uint32_t APB3FZ2;     /*!< Debug MCU APB3FZ2 freeze register,    Address offset: 0x38 */

+  __IO uint32_t APB1LFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x3C */

+  __IO uint32_t APB1LFZ2;    /*!< Debug MCU APB1LFZ2 freeze register,   Address offset: 0x40 */

+  __IO uint32_t APB1HFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x44 */

+  __IO uint32_t APB1HFZ2;    /*!< Debug MCU APB1LFZ2 freeze register,   Address offset: 0x48 */

+  __IO uint32_t APB2FZ1;     /*!< Debug MCU APB2FZ1 freeze register,    Address offset: 0x4C */

+  __IO uint32_t APB2FZ2;     /*!< Debug MCU APB2FZ2 freeze register,    Address offset: 0x50 */

+  __IO uint32_t APB4FZ1;     /*!< Debug MCU APB4FZ1 freeze register,    Address offset: 0x54 */

+  __IO uint32_t APB4FZ2;     /*!< Debug MCU APB4FZ2 freeze register,    Address offset: 0x58 */

+

+}DBGMCU_TypeDef;

+/**

+  * @brief DCMI

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */

+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */

+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */

+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */

+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */

+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */

+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */

+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */

+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */

+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */

+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */

+} DCMI_TypeDef;

+

+/**

+  * @brief DMA Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */

+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */

+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */

+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */

+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */

+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */

+} DMA_Stream_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */

+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */

+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */

+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */

+} DMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CCR;          /*!< DMA channel x configuration register          */

+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register         */

+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register     */

+  __IO uint32_t CM0AR;        /*!< DMA channel x memory 0 address register       */

+  __IO uint32_t CM1AR;        /*!< DMA channel x memory 1 address register       */

+} BDMA_Channel_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */

+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */

+} BDMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CCR;        /*!< DMA Multiplexer Channel x Control Register   */

+}DMAMUX_Channel_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CSR;      /*!< DMA Channel Status Register     */

+  __IO uint32_t  CFR;      /*!< DMA Channel Clear Flag Register */

+}DMAMUX_ChannelStatus_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  RGCR;        /*!< DMA Request Generator x Control Register   */

+}DMAMUX_RequestGen_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  RGSR;        /*!< DMA Request Generator Status Register       */

+  __IO uint32_t  RGCFR;       /*!< DMA Request Generator Clear Flag Register   */

+}DMAMUX_RequestGenStatus_TypeDef;

+

+/**

+  * @brief MDMA Controller

+  */

+typedef struct

+{

+  __IO uint32_t  GISR0;   /*!< MDMA Global Interrupt/Status Register 0,          Address offset: 0x00 */

+}MDMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CISR;      /*!< MDMA channel x interrupt/status register,             Address offset: 0x40 */

+  __IO uint32_t  CIFCR;     /*!< MDMA channel x interrupt flag clear register,         Address offset: 0x44 */

+  __IO uint32_t  CESR;      /*!< MDMA Channel x error status register,                 Address offset: 0x48 */

+  __IO uint32_t  CCR;       /*!< MDMA channel x control register,                      Address offset: 0x4C */

+  __IO uint32_t  CTCR;      /*!< MDMA channel x Transfer Configuration register,       Address offset: 0x50 */

+  __IO uint32_t  CBNDTR;    /*!< MDMA Channel x block number of data register,         Address offset: 0x54 */

+  __IO uint32_t  CSAR;      /*!< MDMA channel x source address register,               Address offset: 0x58 */

+  __IO uint32_t  CDAR;      /*!< MDMA channel x destination address register,          Address offset: 0x5C */

+  __IO uint32_t  CBRUR;     /*!< MDMA channel x Block Repeat address Update register,  Address offset: 0x60 */

+  __IO uint32_t  CLAR;      /*!< MDMA channel x Link Address register,                 Address offset: 0x64 */

+  __IO uint32_t  CTBR;      /*!< MDMA channel x Trigger and Bus selection Register,    Address offset: 0x68 */

+  uint32_t       RESERVED0; /*!< Reserved, 0x68                                                             */

+  __IO uint32_t  CMAR;      /*!< MDMA channel x Mask address register,                 Address offset: 0x70 */

+  __IO uint32_t  CMDR;      /*!< MDMA channel x Mask Data register,                    Address offset: 0x74 */

+}MDMA_Channel_TypeDef;

+

+/**

+  * @brief DMA2D Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */

+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */

+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */

+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */

+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */

+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */

+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */

+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */

+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */

+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */

+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */

+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */

+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */

+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */

+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */

+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */

+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */

+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */

+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */

+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */

+  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */

+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */

+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */

+} DMA2D_TypeDef;

+

+/**

+  * @brief DSI Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t VR;            /*!< DSI Host Version Register,                                 Address offset: 0x00      */

+  __IO uint32_t CR;            /*!< DSI Host Control Register,                                 Address offset: 0x04      */

+  __IO uint32_t CCR;           /*!< DSI HOST Clock Control Register,                           Address offset: 0x08      */

+  __IO uint32_t LVCIDR;        /*!< DSI Host LTDC VCID Register,                               Address offset: 0x0C      */

+  __IO uint32_t LCOLCR;        /*!< DSI Host LTDC Color Coding Register,                       Address offset: 0x10      */

+  __IO uint32_t LPCR;          /*!< DSI Host LTDC Polarity Configuration Register,             Address offset: 0x14      */

+  __IO uint32_t LPMCR;         /*!< DSI Host Low-Power Mode Configuration Register,            Address offset: 0x18      */

+  uint32_t      RESERVED0[4];  /*!< Reserved, 0x1C - 0x2B                                                                */

+  __IO uint32_t PCR;           /*!< DSI Host Protocol Configuration Register,                  Address offset: 0x2C      */

+  __IO uint32_t GVCIDR;        /*!< DSI Host Generic VCID Register,                            Address offset: 0x30      */

+  __IO uint32_t MCR;           /*!< DSI Host Mode Configuration Register,                      Address offset: 0x34      */

+  __IO uint32_t VMCR;          /*!< DSI Host Video Mode Configuration Register,                Address offset: 0x38      */

+  __IO uint32_t VPCR;          /*!< DSI Host Video Packet Configuration Register,              Address offset: 0x3C      */

+  __IO uint32_t VCCR;          /*!< DSI Host Video Chunks Configuration Register,              Address offset: 0x40      */

+  __IO uint32_t VNPCR;         /*!< DSI Host Video Null Packet Configuration Register,         Address offset: 0x44      */

+  __IO uint32_t VHSACR;        /*!< DSI Host Video HSA Configuration Register,                 Address offset: 0x48      */

+  __IO uint32_t VHBPCR;        /*!< DSI Host Video HBP Configuration Register,                 Address offset: 0x4C      */

+  __IO uint32_t VLCR;          /*!< DSI Host Video Line Configuration Register,                Address offset: 0x50      */

+  __IO uint32_t VVSACR;        /*!< DSI Host Video VSA Configuration Register,                 Address offset: 0x54      */

+  __IO uint32_t VVBPCR;        /*!< DSI Host Video VBP Configuration Register,                 Address offset: 0x58      */

+  __IO uint32_t VVFPCR;        /*!< DSI Host Video VFP Configuration Register,                 Address offset: 0x5C      */

+  __IO uint32_t VVACR;         /*!< DSI Host Video VA Configuration Register,                  Address offset: 0x60      */

+  __IO uint32_t LCCR;          /*!< DSI Host LTDC Command Configuration Register,              Address offset: 0x64      */

+  __IO uint32_t CMCR;          /*!< DSI Host Command Mode Configuration Register,              Address offset: 0x68      */

+  __IO uint32_t GHCR;          /*!< DSI Host Generic Header Configuration Register,            Address offset: 0x6C      */

+  __IO uint32_t GPDR;          /*!< DSI Host Generic Payload Data Register,                    Address offset: 0x70      */

+  __IO uint32_t GPSR;          /*!< DSI Host Generic Packet Status Register,                   Address offset: 0x74      */

+  __IO uint32_t TCCR[6];       /*!< DSI Host Timeout Counter Configuration Register,           Address offset: 0x78-0x8F */

+  __IO uint32_t TDCR;          /*!< DSI Host 3D Configuration Register,                        Address offset: 0x90      */

+  __IO uint32_t CLCR;          /*!< DSI Host Clock Lane Configuration Register,                Address offset: 0x94      */

+  __IO uint32_t CLTCR;         /*!< DSI Host Clock Lane Timer Configuration Register,          Address offset: 0x98      */

+  __IO uint32_t DLTCR;         /*!< DSI Host Data Lane Timer Configuration Register,           Address offset: 0x9C      */

+  __IO uint32_t PCTLR;         /*!< DSI Host PHY Control Register,                             Address offset: 0xA0      */

+  __IO uint32_t PCONFR;        /*!< DSI Host PHY Configuration Register,                       Address offset: 0xA4      */

+  __IO uint32_t PUCR;          /*!< DSI Host PHY ULPS Control Register,                        Address offset: 0xA8      */

+  __IO uint32_t PTTCR;         /*!< DSI Host PHY TX Triggers Configuration Register,           Address offset: 0xAC      */

+  __IO uint32_t PSR;           /*!< DSI Host PHY Status Register,                              Address offset: 0xB0      */

+  uint32_t      RESERVED1[2];  /*!< Reserved, 0xB4 - 0xBB                                                                */

+  __IO uint32_t ISR[2];        /*!< DSI Host Interrupt & Status Register,                      Address offset: 0xBC-0xC3 */

+  __IO uint32_t IER[2];        /*!< DSI Host Interrupt Enable Register,                        Address offset: 0xC4-0xCB */

+  uint32_t      RESERVED2[3];  /*!< Reserved, 0xD0 - 0xD7                                                                */

+  __IO uint32_t FIR[2];        /*!< DSI Host Force Interrupt Register,                         Address offset: 0xD8-0xDF */

+  uint32_t      RESERVED3[8];  /*!< Reserved, 0xE0 - 0xFF                                                                */

+  __IO uint32_t VSCR;          /*!< DSI Host Video Shadow Control Register,                    Address offset: 0x100     */

+  uint32_t      RESERVED4[2];  /*!< Reserved, 0x104 - 0x10B                                                              */

+  __IO uint32_t LCVCIDR;       /*!< DSI Host LTDC Current VCID Register,                       Address offset: 0x10C     */

+  __IO uint32_t LCCCR;         /*!< DSI Host LTDC Current Color Coding Register,               Address offset: 0x110     */

+  uint32_t      RESERVED5;     /*!< Reserved, 0x114                                                                      */

+  __IO uint32_t LPMCCR;        /*!< DSI Host Low-power Mode Current Configuration Register,    Address offset: 0x118     */

+  uint32_t      RESERVED6[7];  /*!< Reserved, 0x11C - 0x137                                                              */

+  __IO uint32_t VMCCR;         /*!< DSI Host Video Mode Current Configuration Register,        Address offset: 0x138     */

+  __IO uint32_t VPCCR;         /*!< DSI Host Video Packet Current Configuration Register,      Address offset: 0x13C     */

+  __IO uint32_t VCCCR;         /*!< DSI Host Video Chuncks Current Configuration Register,     Address offset: 0x140     */

+  __IO uint32_t VNPCCR;        /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144     */

+  __IO uint32_t VHSACCR;       /*!< DSI Host Video HSA Current Configuration Register,         Address offset: 0x148     */

+  __IO uint32_t VHBPCCR;       /*!< DSI Host Video HBP Current Configuration Register,         Address offset: 0x14C     */

+  __IO uint32_t VLCCR;         /*!< DSI Host Video Line Current Configuration Register,        Address offset: 0x150     */

+  __IO uint32_t VVSACCR;       /*!< DSI Host Video VSA Current Configuration Register,         Address offset: 0x154     */

+  __IO uint32_t VVBPCCR;       /*!< DSI Host Video VBP Current Configuration Register,         Address offset: 0x158     */

+  __IO uint32_t VVFPCCR;       /*!< DSI Host Video VFP Current Configuration Register,         Address offset: 0x15C     */

+  __IO uint32_t VVACCR;        /*!< DSI Host Video VA Current Configuration Register,          Address offset: 0x160     */

+  uint32_t      RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F                                                              */

+  __IO uint32_t TDCCR;         /*!< DSI Host 3D Current Configuration Register,                Address offset: 0x190     */

+  uint32_t      RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF                                                                */

+  __IO uint32_t WCFGR;          /*!< DSI Wrapper Configuration Register,                        Address offset: 0x400       */

+  __IO uint32_t WCR;            /*!< DSI Wrapper Control Register,                              Address offset: 0x404       */

+  __IO uint32_t WIER;           /*!< DSI Wrapper Interrupt Enable Register,                     Address offset: 0x408       */

+  __IO uint32_t WISR;           /*!< DSI Wrapper Interrupt and Status Register,                 Address offset: 0x40C       */

+  __IO uint32_t WIFCR;          /*!< DSI Wrapper Interrupt Flag Clear Register,                 Address offset: 0x410       */

+  uint32_t      RESERVED9;      /*!< Reserved, 0x414                                                                        */

+  __IO uint32_t WPCR[5];        /*!< DSI Wrapper PHY Configuration Register,                    Address offset: 0x418-0x42B */

+  uint32_t      RESERVED10;     /*!< Reserved, 0x42C                                                                        */

+  __IO uint32_t WRPCR;          /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430                  */

+} DSI_TypeDef;

+

+/**

+  * @brief Ethernet MAC

+  */

+typedef struct

+{

+  __IO uint32_t MACCR;

+  __IO uint32_t MACECR;

+  __IO uint32_t MACPFR;

+  __IO uint32_t MACWTR;

+  __IO uint32_t MACHT0R;

+  __IO uint32_t MACHT1R;

+  uint32_t      RESERVED1[14];

+  __IO uint32_t MACVTR;

+  uint32_t      RESERVED2;

+  __IO uint32_t MACVHTR;

+  uint32_t      RESERVED3;

+  __IO uint32_t MACVIR;

+  __IO uint32_t MACIVIR;

+  uint32_t      RESERVED4[2];

+  __IO uint32_t MACTFCR;

+  uint32_t      RESERVED5[7];

+  __IO uint32_t MACRFCR;

+  uint32_t      RESERVED6[7];

+  __IO uint32_t MACISR;

+  __IO uint32_t MACIER;

+  __IO uint32_t MACRXTXSR;

+  uint32_t      RESERVED7;

+  __IO uint32_t MACPCSR;

+  __IO uint32_t MACRWKPFR;

+  uint32_t      RESERVED8[2];

+  __IO uint32_t MACLCSR;

+  __IO uint32_t MACLTCR;

+  __IO uint32_t MACLETR;

+  __IO uint32_t MAC1USTCR;

+  uint32_t      RESERVED9[12];

+  __IO uint32_t MACVR;

+  __IO uint32_t MACDR;

+  uint32_t      RESERVED10;

+  __IO uint32_t MACHWF0R;

+  __IO uint32_t MACHWF1R;

+  __IO uint32_t MACHWF2R;

+  uint32_t      RESERVED11[54];

+  __IO uint32_t MACMDIOAR;

+  __IO uint32_t MACMDIODR;

+  uint32_t      RESERVED12[2];

+  __IO uint32_t MACARPAR;

+  uint32_t      RESERVED13[59];

+  __IO uint32_t MACA0HR;

+  __IO uint32_t MACA0LR;

+  __IO uint32_t MACA1HR;

+  __IO uint32_t MACA1LR;

+  __IO uint32_t MACA2HR;

+  __IO uint32_t MACA2LR;

+  __IO uint32_t MACA3HR;

+  __IO uint32_t MACA3LR;

+  uint32_t      RESERVED14[248];

+  __IO uint32_t MMCCR;

+  __IO uint32_t MMCRIR;

+  __IO uint32_t MMCTIR;

+  __IO uint32_t MMCRIMR;

+  __IO uint32_t MMCTIMR;

+  uint32_t      RESERVED15[14];

+  __IO uint32_t MMCTSCGPR;

+  __IO uint32_t MMCTMCGPR;

+  uint32_t      RESERVED16[5];

+  __IO uint32_t MMCTPCGR;

+  uint32_t      RESERVED17[10];

+  __IO uint32_t MMCRCRCEPR;

+  __IO uint32_t MMCRAEPR;

+  uint32_t      RESERVED18[10];

+  __IO uint32_t MMCRUPGR;

+  uint32_t      RESERVED19[9];

+  __IO uint32_t MMCTLPIMSTR;

+  __IO uint32_t MMCTLPITCR;

+  __IO uint32_t MMCRLPIMSTR;

+  __IO uint32_t MMCRLPITCR;

+  uint32_t      RESERVED20[65];

+  __IO uint32_t MACL3L4C0R;

+  __IO uint32_t MACL4A0R;

+  uint32_t      RESERVED21[2];

+  __IO uint32_t MACL3A0R0R;

+  __IO uint32_t MACL3A1R0R;

+  __IO uint32_t MACL3A2R0R;

+  __IO uint32_t MACL3A3R0R;

+  uint32_t      RESERVED22[4];

+  __IO uint32_t MACL3L4C1R;

+  __IO uint32_t MACL4A1R;

+  uint32_t      RESERVED23[2];

+  __IO uint32_t MACL3A0R1R;

+  __IO uint32_t MACL3A1R1R;

+  __IO uint32_t MACL3A2R1R;

+  __IO uint32_t MACL3A3R1R;

+  uint32_t      RESERVED24[108];

+  __IO uint32_t MACTSCR;

+  __IO uint32_t MACSSIR;

+  __IO uint32_t MACSTSR;

+  __IO uint32_t MACSTNR;

+  __IO uint32_t MACSTSUR;

+  __IO uint32_t MACSTNUR;

+  __IO uint32_t MACTSAR;

+  uint32_t      RESERVED25;

+  __IO uint32_t MACTSSR;

+  uint32_t      RESERVED26[3];

+  __IO uint32_t MACTTSSNR;

+  __IO uint32_t MACTTSSSR;

+  uint32_t      RESERVED27[2];

+  __IO uint32_t MACACR;

+  uint32_t      RESERVED28;

+  __IO uint32_t MACATSNR;

+  __IO uint32_t MACATSSR;

+  __IO uint32_t MACTSIACR;

+  __IO uint32_t MACTSEACR;

+  __IO uint32_t MACTSICNR;

+  __IO uint32_t MACTSECNR;

+  uint32_t      RESERVED29[4];

+  __IO uint32_t MACPPSCR;

+  uint32_t      RESERVED30[3];

+  __IO uint32_t MACPPSTTSR;

+  __IO uint32_t MACPPSTTNR;

+  __IO uint32_t MACPPSIR;

+  __IO uint32_t MACPPSWR;

+  uint32_t      RESERVED31[12];

+  __IO uint32_t MACPOCR;

+  __IO uint32_t MACSPI0R;

+  __IO uint32_t MACSPI1R;

+  __IO uint32_t MACSPI2R;

+  __IO uint32_t MACLMIR;

+  uint32_t      RESERVED32[11];

+  __IO uint32_t MTLOMR;

+  uint32_t      RESERVED33[7];

+  __IO uint32_t MTLISR;

+  uint32_t      RESERVED34[55];

+  __IO uint32_t MTLTQOMR;

+  __IO uint32_t MTLTQUR;

+  __IO uint32_t MTLTQDR;

+  uint32_t      RESERVED35[8];

+  __IO uint32_t MTLQICSR;

+  __IO uint32_t MTLRQOMR;

+  __IO uint32_t MTLRQMPOCR;

+  __IO uint32_t MTLRQDR;

+  uint32_t      RESERVED36[177];

+  __IO uint32_t DMAMR;

+  __IO uint32_t DMASBMR;

+  __IO uint32_t DMAISR;

+  __IO uint32_t DMADSR;

+  uint32_t      RESERVED37[60];

+  __IO uint32_t DMACCR;

+  __IO uint32_t DMACTCR;

+  __IO uint32_t DMACRCR;

+  uint32_t      RESERVED38[2];

+  __IO uint32_t DMACTDLAR;

+  uint32_t      RESERVED39;

+  __IO uint32_t DMACRDLAR;

+  __IO uint32_t DMACTDTPR;

+  uint32_t      RESERVED40;

+  __IO uint32_t DMACRDTPR;

+  __IO uint32_t DMACTDRLR;

+  __IO uint32_t DMACRDRLR;

+  __IO uint32_t DMACIER;

+  __IO uint32_t DMACRIWTR;

+__IO uint32_t DMACSFCSR;

+  uint32_t      RESERVED41;

+  __IO uint32_t DMACCATDR;

+  uint32_t      RESERVED42;

+  __IO uint32_t DMACCARDR;

+  uint32_t      RESERVED43;

+  __IO uint32_t DMACCATBR;

+  uint32_t      RESERVED44;

+  __IO uint32_t DMACCARBR;

+  __IO uint32_t DMACSR;

+uint32_t      RESERVED45[2];

+__IO uint32_t DMACMFCR;

+}ETH_TypeDef;

+/**

+  * @brief External Interrupt/Event Controller

+  */

+

+typedef struct

+{

+__IO uint32_t RTSR1;               /*!< EXTI Rising trigger selection register,          Address offset: 0x00 */

+__IO uint32_t FTSR1;               /*!< EXTI Falling trigger selection register,         Address offset: 0x04 */

+__IO uint32_t SWIER1;              /*!< EXTI Software interrupt event register,          Address offset: 0x08 */

+__IO uint32_t D3PMR1;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */

+__IO uint32_t D3PCR1L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L)     Address offset: 0x10 */

+__IO uint32_t D3PCR1H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H)   Address offset: 0x14 */

+uint32_t      RESERVED1[2];        /*!< Reserved,                                        0x18 to 0x1C         */

+__IO uint32_t RTSR2;               /*!< EXTI Rising trigger selection register,          Address offset: 0x20 */

+__IO uint32_t FTSR2;               /*!< EXTI Falling trigger selection register,         Address offset: 0x24 */

+__IO uint32_t SWIER2;              /*!< EXTI Software interrupt event register,          Address offset: 0x28 */

+__IO uint32_t D3PMR2;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */

+__IO uint32_t D3PCR2L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L)  Address offset: 0x30 */

+__IO uint32_t D3PCR2H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */

+uint32_t      RESERVED2[2];        /*!< Reserved,                                        0x38 to 0x3C         */

+__IO uint32_t RTSR3;               /*!< EXTI Rising trigger selection register,          Address offset: 0x40 */

+__IO uint32_t FTSR3;               /*!< EXTI Falling trigger selection register,         Address offset: 0x44 */

+__IO uint32_t SWIER3;              /*!< EXTI Software interrupt event register,          Address offset: 0x48 */

+__IO uint32_t D3PMR3;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */

+__IO uint32_t D3PCR3L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */

+__IO uint32_t D3PCR3H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */

+uint32_t      RESERVED3[10];       /*!< Reserved,                                        0x58 to 0x7C         */

+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                    Address offset: 0x80 */

+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                        Address offset: 0x84 */

+__IO uint32_t PR1;                 /*!< EXTI Pending register,                           Address offset: 0x88 */

+uint32_t      RESERVED4;           /*!< Reserved,                                        0x8C                 */

+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                    Address offset: 0x90 */

+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                        Address offset: 0x94 */

+__IO uint32_t PR2;                 /*!< EXTI Pending register,                           Address offset: 0x98 */

+uint32_t      RESERVED5;           /*!< Reserved,                                        0x9C                 */

+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                    Address offset: 0xA0 */

+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                        Address offset: 0xA4 */

+__IO uint32_t PR3;                 /*!< EXTI Pending register,                           Address offset: 0xA8 */

+uint32_t      RESERVED6[5];        /*!< Reserved,                                        0xAC to 0xBC         */

+__IO uint32_t C2IMR1;              /*!< EXTI Interrupt mask register,                    Address offset: 0xC0 */

+__IO uint32_t C2EMR1;              /*!< EXTI Event mask register,                        Address offset: 0xC4 */

+__IO uint32_t C2PR1;               /*!< EXTI Pending register,                           Address offset: 0xC8 */

+uint32_t      RESERVED7;           /*!< Reserved,                                        0xCC                 */

+__IO uint32_t C2IMR2;              /*!< EXTI Interrupt mask register,                    Address offset: 0xD0 */

+__IO uint32_t C2EMR2;              /*!< EXTI Event mask register,                        Address offset: 0xD4 */

+__IO uint32_t C2PR2;               /*!< EXTI Pending register,                           Address offset: 0xD8 */

+uint32_t      RESERVED8;           /*!< Reserved,                                        0xDC                 */

+__IO uint32_t C2IMR3;              /*!< EXTI Interrupt mask register,                    Address offset: 0xE0 */

+__IO uint32_t C2EMR3;              /*!< EXTI Event mask register,                        Address offset: 0xE4 */

+__IO uint32_t C2PR3;               /*!< EXTI Pending register,                           Address offset: 0xE8 */

+

+}EXTI_TypeDef;

+

+typedef struct

+{

+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                Address offset: 0x00 */

+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                    Address offset: 0x04 */

+__IO uint32_t PR1;                 /*!< EXTI Pending register,                       Address offset: 0x08 */

+uint32_t      RESERVED1;           /*!< Reserved, 0x0C                                                    */

+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                Address offset: 0x10 */

+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                    Address offset: 0x14 */

+__IO uint32_t PR2;                 /*!< EXTI Pending register,                       Address offset: 0x18 */

+uint32_t      RESERVED2;           /*!< Reserved, 0x1C                                                    */

+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                Address offset: 0x20 */

+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                    Address offset: 0x24 */

+__IO uint32_t PR3;                 /*!< EXTI Pending register,                       Address offset: 0x28 */

+}EXTI_Core_TypeDef;

+

+

+/**

+  * @brief FLASH Registers

+  */

+

+typedef struct

+{

+  __IO uint32_t ACR;             /*!< FLASH access control register,                            Address offset: 0x00  */

+  __IO uint32_t KEYR1;           /*!< Flash Key Register for bank1,                             Address offset: 0x04  */

+  __IO uint32_t OPTKEYR;         /*!< Flash Option Key Register,                                Address offset: 0x08  */

+  __IO uint32_t CR1;             /*!< Flash Control Register for bank1,                         Address offset: 0x0C  */

+  __IO uint32_t SR1;             /*!< Flash Status Register for bank1,                          Address offset: 0x10  */

+  __IO uint32_t CCR1;            /*!< Flash Control Register for bank1,                         Address offset: 0x14  */

+  __IO uint32_t OPTCR;           /*!< Flash Option Control Register,                            Address offset: 0x18  */

+  __IO uint32_t OPTSR_CUR;       /*!< Flash Option Status Current Register,                     Address offset: 0x1C  */

+  __IO uint32_t OPTSR_PRG;       /*!< Flash Option Status to Program Register,                  Address offset: 0x20  */

+  __IO uint32_t OPTCCR;          /*!< Flash Option Clear Control Register,                      Address offset: 0x24  */

+  __IO uint32_t PRAR_CUR1;       /*!< Flash Current Protection Address Register for bank1,      Address offset: 0x28  */

+  __IO uint32_t PRAR_PRG1;       /*!< Flash Protection Address to Program Register for bank1,   Address offset: 0x2C  */

+  __IO uint32_t SCAR_CUR1;       /*!< Flash Current Secure Address Register for bank1,          Address offset: 0x30  */

+  __IO uint32_t SCAR_PRG1;       /*!< Flash Secure Address to Program Register for bank1,       Address offset: 0x34  */

+  __IO uint32_t WPSN_CUR1;       /*!< Flash Current Write Protection Register on bank1,         Address offset: 0x38  */

+  __IO uint32_t WPSN_PRG1;       /*!< Flash Write Protection to Program Register on bank1,      Address offset: 0x3C  */

+  __IO uint32_t BOOT7_CUR;       /*!< Flash Current Boot Address for Pelican Core Register,     Address offset: 0x40  */

+  __IO uint32_t BOOT7_PRG;       /*!< Flash Boot Address to Program for Pelican Core Register,  Address offset: 0x44  */

+  __IO uint32_t BOOT4_CUR;       /*!< Flash Current Boot Address for M4 Core Register,          Address offset: 0x48  */

+  __IO uint32_t BOOT4_PRG;       /*!< Flash Boot Address to Program for M4 Core Register,       Address offset: 0x4C  */

+  __IO uint32_t CRCCR1;          /*!< Flash CRC Control register For Bank1 Register ,           Address offset: 0x50  */

+  __IO uint32_t CRCSADD1;        /*!< Flash CRC Start Address Register for Bank1 ,              Address offset: 0x54  */

+  __IO uint32_t CRCEADD1;        /*!< Flash CRC End Address Register for Bank1 ,                Address offset: 0x58  */

+  __IO uint32_t CRCDATA;         /*!< Flash CRC Data Register for Bank1 ,                       Address offset: 0x5C  */

+  __IO uint32_t ECC_FA1;         /*!< Flash ECC Fail Address For Bank1 Register ,               Address offset: 0x60  */

+  uint32_t      RESERVED1[40];   /*!< Reserved, 0x64 to 0x100                                                         */

+  __IO uint32_t KEYR2;           /*!< Flash Key Register for bank2,                             Address offset: 0x104 */

+  uint32_t      RESERVED2;       /*!< Reserved, 0x108                                                                 */

+  __IO uint32_t CR2;             /*!< Flash Control Register for bank2,                         Address offset: 0x10C */

+  __IO uint32_t SR2;             /*!< Flash Status Register for bank2,                          Address offset: 0x110 */

+  __IO uint32_t CCR2;            /*!< Flash Status Register for bank2,                          Address offset: 0x114 */

+  uint32_t      RESERVED3[4];    /*!< Reserved, 0x118 to 0x124                                                        */

+  __IO uint32_t PRAR_CUR2;       /*!< Flash Current Protection Address Register for bank2,      Address offset: 0x128 */

+  __IO uint32_t PRAR_PRG2;       /*!< Flash Protection Address to Program Register for bank2,   Address offset: 0x12C */

+  __IO uint32_t SCAR_CUR2;       /*!< Flash Current Secure Address Register for bank2,          Address offset: 0x130 */

+  __IO uint32_t SCAR_PRG2;       /*!< Flash Secure Address Register for bank2,                  Address offset: 0x134 */

+  __IO uint32_t WPSN_CUR2;       /*!< Flash Current Write Protection Register on bank2,         Address offset: 0x138 */

+  __IO uint32_t WPSN_PRG2;       /*!< Flash Write Protection to Program Register on bank2,      Address offset: 0x13C */

+  uint32_t      RESERVED4[4];    /*!< Reserved, 0x140 to 0x14C                                                        */

+  __IO uint32_t CRCCR2;          /*!< Flash CRC Control register For Bank2 Register ,           Address offset: 0x150 */

+  __IO uint32_t CRCSADD2;        /*!< Flash CRC Start Address Register for Bank2 ,              Address offset: 0x154 */

+  __IO uint32_t CRCEADD2;        /*!< Flash CRC End Address Register for Bank2 ,                Address offset: 0x158 */

+  __IO uint32_t CRCDATA2;        /*!< Flash CRC Data Register for Bank2 ,                       Address offset: 0x15C */

+  __IO uint32_t ECC_FA2;         /*!< Flash ECC Fail Address For Bank2 Register ,               Address offset: 0x160 */

+} FLASH_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */

+} FMC_Bank1_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank1E

+  */

+

+typedef struct

+{

+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */

+} FMC_Bank1E_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank2

+  */

+

+typedef struct

+{

+  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */

+  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */

+  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */

+  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */

+  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */

+  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */

+} FMC_Bank2_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank3

+  */

+

+typedef struct

+{

+  __IO uint32_t PCR;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */

+  __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */

+  __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */

+  __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */

+  uint32_t      RESERVED;  /*!< Reserved, 0x90                                                            */

+  __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */

+} FMC_Bank3_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank5 and 6

+  */

+

+

+typedef struct

+{

+  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */

+  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */

+  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */

+  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */

+  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */

+} FMC_Bank5_6_TypeDef;

+

+/**

+  * @brief General Purpose I/O

+  */

+

+typedef struct

+{

+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */

+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */

+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */

+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */

+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */

+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */

+  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset,               Address offset: 0x18      */

+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */

+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */

+} GPIO_TypeDef;

+

+/**

+  * @brief Operational Amplifier (OPAMP)

+  */

+

+typedef struct

+{

+  __IO uint32_t CSR;          /*!< OPAMP control/status register,                      Address offset: 0x00 */

+  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,     Address offset: 0x04 */

+  __IO uint32_t HSOTR;        /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */

+} OPAMP_TypeDef;

+

+/**

+  * @brief System configuration controller

+  */

+

+typedef struct

+{

+ uint32_t RESERVED1;           /*!< Reserved,                                           Address offset: 0x00        */

+ __IO uint32_t PMCR;           /*!< SYSCFG peripheral mode configuration register,      Address offset: 0x04        */

+ __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration registers,  Address offset: 0x08-0x14   */

+ __IO uint32_t CFGR;           /*!< SYSCFG configuration registers,                     Address offset: 0x18        */

+ uint32_t RESERVED2;           /*!< Reserved,                                           Address offset: 0x1C        */

+ __IO uint32_t CCCSR;          /*!< SYSCFG compensation cell control/status register,   Address offset: 0x20        */

+ __IO uint32_t CCVR;           /*!< SYSCFG compensation cell value register,            Address offset: 0x24        */

+ __IO uint32_t CCCR;           /*!< SYSCFG compensation cell code register,             Address offset: 0x28        */

+ __IO uint32_t PWRCR;          /*!< PWR control register,                               Address offset: 0x2C        */

+  uint32_t     RESERVED3[61];  /*!< Reserved, 0x30-0x120                                                            */

+  __IO uint32_t PKGR;          /*!< SYSCFG package register,                            Address offset: 0x124       */

+  uint32_t     RESERVED4[118]; /*!< Reserved, 0x128-0x2FC                                                           */

+ __IO uint32_t UR0;            /*!< SYSCFG user register 0,                             Address offset: 0x300       */

+ __IO uint32_t UR1;            /*!< SYSCFG user register 1,                             Address offset: 0x304       */

+ __IO uint32_t UR2;            /*!< SYSCFG user register 2,                             Address offset: 0x308       */

+ __IO uint32_t UR3;            /*!< SYSCFG user register 3,                             Address offset: 0x30C       */

+ __IO uint32_t UR4;            /*!< SYSCFG user register 4,                             Address offset: 0x310       */

+ __IO uint32_t UR5;            /*!< SYSCFG user register 5,                             Address offset: 0x314       */

+ __IO uint32_t UR6;            /*!< SYSCFG user register 6,                             Address offset: 0x318       */

+ __IO uint32_t UR7;            /*!< SYSCFG user register 7,                             Address offset: 0x31C       */

+ __IO uint32_t UR8;            /*!< SYSCFG user register 8,                             Address offset: 0x320       */

+ __IO uint32_t UR9;            /*!< SYSCFG user register 9,                             Address offset: 0x324       */

+ __IO uint32_t UR10;           /*!< SYSCFG user register 10,                            Address offset: 0x328       */

+ __IO uint32_t UR11;           /*!< SYSCFG user register 11,                            Address offset: 0x32C       */

+ __IO uint32_t UR12;           /*!< SYSCFG user register 12,                            Address offset: 0x330       */

+ __IO uint32_t UR13;           /*!< SYSCFG user register 13,                            Address offset: 0x334       */

+ __IO uint32_t UR14;           /*!< SYSCFG user register 14,                            Address offset: 0x338       */

+ __IO uint32_t UR15;           /*!< SYSCFG user register 15,                            Address offset: 0x33C       */

+ __IO uint32_t UR16;           /*!< SYSCFG user register 16,                            Address offset: 0x340       */

+ __IO uint32_t UR17;           /*!< SYSCFG user register 17,                            Address offset: 0x344       */

+

+} SYSCFG_TypeDef;

+

+/**

+  * @brief Inter-integrated Circuit Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */

+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */

+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */

+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */

+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */

+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */

+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */

+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */

+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */

+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */

+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */

+} I2C_TypeDef;

+

+/**

+  * @brief Independent WATCHDOG

+  */

+

+typedef struct

+{

+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */

+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */

+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */

+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */

+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */

+} IWDG_TypeDef;

+

+

+/**

+  * @brief JPEG Codec

+  */

+typedef struct

+{

+  __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */

+  __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */

+  __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */

+  __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */

+  __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */

+  __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */

+  __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */

+  __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */

+  uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */

+  __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */

+  __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */

+  __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */

+  uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */

+  __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */

+  __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */

+  uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */

+  __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */

+  __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */

+  __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */

+  __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */

+  __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */

+  __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */

+  __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */

+  __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */

+  uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */

+  __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0,                 Address offset: 500h-65Ch */

+  __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1,                 Address offset: 660h-7BCh */

+  __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encodor, DC Huffman table 0,                 Address offset: 7C0h-7DCh */

+  __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encodor, DC Huffman table 1,                 Address offset: 7E0h-7FCh */

+

+} JPEG_TypeDef;

+

+/**

+  * @brief LCD-TFT Display Controller

+  */

+

+typedef struct

+{

+  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04                                                       */

+  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */

+  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */

+  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */

+  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */

+  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */

+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20                                                       */

+  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */

+  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28                                                            */

+  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */

+  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30                                                            */

+  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */

+  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */

+  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */

+  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */

+  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */

+  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */

+} LTDC_TypeDef;

+

+/**

+  * @brief LCD-TFT Display layer x Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */

+  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */

+  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */

+  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */

+  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */

+  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */

+  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */

+  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */

+  uint32_t      RESERVED0[2];  /*!< Reserved */

+  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */

+  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */

+  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */

+  uint32_t      RESERVED1[3];  /*!< Reserved */

+  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */

+

+} LTDC_Layer_TypeDef;

+

+/**

+  * @brief Power Control

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;       /*!< PWR power control register 1,            Address offset: 0x00 */

+  __IO uint32_t CSR1;      /*!< PWR power control status register 1,     Address offset: 0x04 */

+  __IO uint32_t CR2;       /*!< PWR power control register 2,            Address offset: 0x08 */

+  __IO uint32_t CR3;       /*!< PWR power control register 3,            Address offset: 0x0C */

+  __IO uint32_t CPUCR;     /*!< PWR CPU control register,                Address offset: 0x10 */

+  __IO uint32_t CPU2CR;    /*!< PWR CPU2 control register,               Address offset: 0x14 */

+  __IO uint32_t D3CR;      /*!< PWR D3 domain control register,          Address offset: 0x18 */

+       uint32_t RESERVED1; /*!< Reserved,                                Address offset: 0x1C */

+  __IO uint32_t WKUPCR;    /*!< PWR wakeup clear register,               Address offset: 0x20 */

+  __IO uint32_t WKUPFR;    /*!< PWR wakeup flag register,                Address offset: 0x24 */

+  __IO uint32_t WKUPEPR;   /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */

+} PWR_TypeDef;

+

+/**

+  * @brief Reset and Clock Control

+  */

+

+typedef struct

+{

+ __IO uint32_t CR;             /*!< RCC clock control register,                                              Address offset: 0x00  */

+ __IO uint32_t HSICFGR;        /*!< HSI Clock Calibration Register,                                          Address offset: 0x04  */

+ __IO uint32_t CRRCR;          /*!< Clock Recovery RC  Register,                                             Address offset: 0x08  */

+ __IO uint32_t CSICFGR;        /*!< CSI Clock Calibration Register,                                          Address offset: 0x0C  */

+ __IO uint32_t CFGR;           /*!< RCC clock configuration register,                                        Address offset: 0x10  */

+ uint32_t     RESERVED1;       /*!< Reserved,                                                                Address offset: 0x14  */

+ __IO uint32_t D1CFGR;         /*!< RCC Domain 1 configuration register,                                     Address offset: 0x18  */

+ __IO uint32_t D2CFGR;         /*!< RCC Domain 2 configuration register,                                     Address offset: 0x1C  */

+ __IO uint32_t D3CFGR;         /*!< RCC Domain 3 configuration register,                                     Address offset: 0x20  */

+ uint32_t     RESERVED2;       /*!< Reserved,                                                                Address offset: 0x24  */

+ __IO uint32_t PLLCKSELR;      /*!< RCC PLLs Clock Source Selection Register,                                Address offset: 0x28  */

+ __IO uint32_t PLLCFGR;        /*!< RCC PLLs  Configuration Register,                                        Address offset: 0x2C  */

+ __IO uint32_t PLL1DIVR;       /*!< RCC PLL1 Dividers Configuration Register,                                Address offset: 0x30  */

+ __IO uint32_t PLL1FRACR;      /*!< RCC PLL1 Fractional Divider Configuration Register,                      Address offset: 0x34  */

+ __IO uint32_t PLL2DIVR;       /*!< RCC PLL2 Dividers Configuration Register,                                Address offset: 0x38  */

+ __IO uint32_t PLL2FRACR;      /*!< RCC PLL2 Fractional Divider Configuration Register,                      Address offset: 0x3C  */

+ __IO uint32_t PLL3DIVR;       /*!< RCC PLL3 Dividers Configuration Register,                                Address offset: 0x40  */

+ __IO uint32_t PLL3FRACR;      /*!< RCC PLL3 Fractional Divider Configuration Register,                      Address offset: 0x44  */

+ uint32_t      RESERVED3;      /*!< Reserved,                                                                Address offset: 0x48  */

+ __IO uint32_t  D1CCIPR;       /*!< RCC Domain 1 Kernel Clock Configuration Register                         Address offset: 0x4C  */

+ __IO uint32_t  D2CCIP1R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x50  */

+ __IO uint32_t  D2CCIP2R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x54  */

+ __IO uint32_t  D3CCIPR;       /*!< RCC Domain 3 Kernel Clock Configuration Register                         Address offset: 0x58  */

+ uint32_t      RESERVED4;      /*!< Reserved,                                                                Address offset: 0x5C  */

+ __IO uint32_t  CIER;          /*!< RCC Clock Source Interrupt Enable Register                               Address offset: 0x60  */

+ __IO uint32_t  CIFR;          /*!< RCC Clock Source Interrupt Flag Register                                 Address offset: 0x64  */

+ __IO uint32_t  CICR;          /*!< RCC Clock Source Interrupt Clear Register                                Address offset: 0x68  */

+ uint32_t     RESERVED5;       /*!< Reserved,                                                                Address offset: 0x6C  */

+ __IO uint32_t  BDCR;          /*!< RCC Vswitch Backup Domain Control Register,                              Address offset: 0x70  */

+ __IO uint32_t  CSR;           /*!< RCC clock control & status register,                                     Address offset: 0x74  */

+ uint32_t     RESERVED6;       /*!< Reserved,                                                                Address offset: 0x78  */

+ __IO uint32_t AHB3RSTR;       /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x7C  */

+ __IO uint32_t AHB1RSTR;       /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x80  */

+ __IO uint32_t AHB2RSTR;       /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x84  */

+ __IO uint32_t AHB4RSTR;       /*!< RCC AHB4 peripheral reset register,                                      Address offset: 0x88  */

+ __IO uint32_t APB3RSTR;       /*!< RCC APB3 peripheral reset register,                                      Address offset: 0x8C  */

+ __IO uint32_t APB1LRSTR;      /*!< RCC APB1 peripheral reset Low Word register,                             Address offset: 0x90  */

+ __IO uint32_t APB1HRSTR;      /*!< RCC APB1 peripheral reset High Word register,                            Address offset: 0x94  */

+ __IO uint32_t APB2RSTR;       /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x98  */

+ __IO uint32_t APB4RSTR;       /*!< RCC APB4 peripheral reset register,                                      Address offset: 0x9C  */

+ __IO uint32_t GCR;            /*!< RCC RCC Global Control  Register,                                        Address offset: 0xA0  */

+ uint32_t     RESERVED8;       /*!< Reserved,                                                                Address offset: 0xA4  */

+ __IO uint32_t D3AMR;          /*!< RCC Domain 3 Autonomous Mode Register,                                   Address offset: 0xA8  */

+ uint32_t     RESERVED11[9];    /*!< Reserved, 0xAC-0xCC                                                      Address offset: 0xAC  */

+ __IO uint32_t RSR;            /*!< RCC Reset status register,                                               Address offset: 0xD0  */

+ __IO uint32_t AHB3ENR;        /*!< RCC AHB3 peripheral clock  register,                                     Address offset: 0xD4  */

+ __IO uint32_t AHB1ENR;        /*!< RCC AHB1 peripheral clock  register,                                     Address offset: 0xD8  */

+ __IO uint32_t AHB2ENR;        /*!< RCC AHB2 peripheral clock  register,                                     Address offset: 0xDC  */

+ __IO uint32_t AHB4ENR;        /*!< RCC AHB4 peripheral clock  register,                                     Address offset: 0xE0  */

+ __IO uint32_t APB3ENR;        /*!< RCC APB3 peripheral clock  register,                                     Address offset: 0xE4  */

+ __IO uint32_t APB1LENR;       /*!< RCC APB1 peripheral clock  Low Word register,                            Address offset: 0xE8  */

+ __IO uint32_t APB1HENR;       /*!< RCC APB1 peripheral clock  High Word register,                           Address offset: 0xEC  */

+ __IO uint32_t APB2ENR;        /*!< RCC APB2 peripheral clock  register,                                     Address offset: 0xF0  */

+ __IO uint32_t APB4ENR;        /*!< RCC APB4 peripheral clock  register,                                     Address offset: 0xF4  */

+ uint32_t      RESERVED12;      /*!< Reserved,                                                                Address offset: 0xF8  */

+ __IO uint32_t AHB3LPENR;      /*!< RCC AHB3 peripheral sleep clock  register,                               Address offset: 0xFC  */

+ __IO uint32_t AHB1LPENR;      /*!< RCC AHB1 peripheral sleep clock  register,                               Address offset: 0x100 */

+ __IO uint32_t AHB2LPENR;      /*!< RCC AHB2 peripheral sleep clock  register,                               Address offset: 0x104 */

+ __IO uint32_t AHB4LPENR;      /*!< RCC AHB4 peripheral sleep clock  register,                               Address offset: 0x108 */

+ __IO uint32_t APB3LPENR;      /*!< RCC APB3 peripheral sleep clock  register,                               Address offset: 0x10C */

+ __IO uint32_t APB1LLPENR;     /*!< RCC APB1 peripheral sleep clock  Low Word register,                      Address offset: 0x110 */

+ __IO uint32_t APB1HLPENR;     /*!< RCC APB1 peripheral sleep clock  High Word register,                     Address offset: 0x114 */

+ __IO uint32_t APB2LPENR;      /*!< RCC APB2 peripheral sleep clock  register,                               Address offset: 0x118 */

+ __IO uint32_t APB4LPENR;      /*!< RCC APB4 peripheral sleep clock  register,                               Address offset: 0x11C */

+ uint32_t     RESERVED13[4];   /*!< Reserved, 0x120-0x12C                                                    Address offset: 0x120 */

+

+} RCC_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t RSR;          /*!< RCC Reset status register,                                               Address offset: 0x00 */

+  __IO uint32_t AHB3ENR;      /*!< RCC AHB3 peripheral clock  register,                            Address offset: 0x04 */

+  __IO uint32_t AHB1ENR;      /*!< RCC AHB1 peripheral clock  register,                            Address offset: 0x08 */

+  __IO uint32_t AHB2ENR;      /*!< RCC AHB2 peripheral clock  register,                            Address offset: 0x0C */

+  __IO uint32_t AHB4ENR;      /*!< RCC AHB4 peripheral clock  register,                            Address offset: 0x10 */

+  __IO uint32_t APB3ENR;      /*!< RCC APB3 peripheral clock  register,                            Address offset: 0x14 */

+  __IO uint32_t APB1LENR;     /*!< RCC APB1 peripheral clock  Low Word register,                   Address offset: 0x18 */

+  __IO uint32_t APB1HENR;     /*!< RCC APB1 peripheral clock  High Word register,                  Address offset: 0x1C */

+  __IO uint32_t APB2ENR;      /*!< RCC APB2 peripheral clock  register,                            Address offset: 0x20 */

+  __IO uint32_t APB4ENR;      /*!< RCC APB4 peripheral clock  register,                            Address offset: 0x24 */

+  uint32_t      RESERVED9;    /*!< Reserved,                                                       Address offset: 0x28 */

+  __IO uint32_t AHB3LPENR;    /*!< RCC AHB3 peripheral sleep clock  register,                      Address offset: 0x3C */

+  __IO uint32_t AHB1LPENR;    /*!< RCC AHB1 peripheral sleep clock  register,                      Address offset: 0x40 */

+  __IO uint32_t AHB2LPENR;    /*!< RCC AHB2 peripheral sleep clock  register,                      Address offset: 0x44 */

+  __IO uint32_t AHB4LPENR;    /*!< RCC AHB4 peripheral sleep clock  register,                      Address offset: 0x48 */

+  __IO uint32_t APB3LPENR;    /*!< RCC APB3 peripheral sleep clock  register,                      Address offset: 0x4C */

+  __IO uint32_t APB1LLPENR;   /*!< RCC APB1 peripheral sleep clock  Low Word register,             Address offset: 0x50 */

+  __IO uint32_t APB1HLPENR;   /*!< RCC APB1 peripheral sleep clock  High Word register,            Address offset: 0x54 */

+  __IO uint32_t APB2LPENR;    /*!< RCC APB2 peripheral sleep clock  register,                      Address offset: 0x58 */

+  __IO uint32_t APB4LPENR;    /*!< RCC APB4 peripheral sleep clock  register,                      Address offset: 0x5C */

+  uint32_t     RESERVED10[4]; /*!< Reserved, 0x60-0x6C                                             Address offset: 0x60 */

+

+} RCC_Core_TypeDef;

+

+/**

+  * @brief Real-Time Clock

+  */

+typedef struct

+{

+  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */

+  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */

+  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */

+  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */

+  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */

+  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */

+       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */

+  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */

+  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */

+  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */

+  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */

+  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */

+  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */

+  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */

+  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */

+  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */

+  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */

+  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */

+  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */

+  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset: 0x4C */

+  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */

+  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */

+  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */

+  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */

+  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */

+  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */

+  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */

+  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */

+  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */

+  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */

+  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */

+  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */

+  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */

+  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */

+  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */

+  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */

+  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */

+  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */

+  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */

+  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */

+  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */

+  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */

+  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */

+  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */

+  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */

+  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */

+  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */

+  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */

+  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */

+  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */

+  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */

+  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */

+} RTC_TypeDef;

+

+/**

+  * @brief Serial Audio Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t GCR;           /*!< SAI global configuration register, Address offset: 0x00 */

+  uint32_t      RESERVED0[16]; /*!< Reserved, 0x04 - 0x43                                   */

+  __IO uint32_t PDMCR;         /*!< SAI PDM control register,          Address offset: 0x44 */

+  __IO uint32_t PDMDLY;        /*!< SAI PDM delay register,            Address offset: 0x48 */

+} SAI_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */

+  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */

+  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */

+  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */

+  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */

+  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */

+  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */

+  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */

+} SAI_Block_TypeDef;

+

+/**

+  * @brief SPDIF-RX Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */

+  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */

+  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */

+  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */

+  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */

+  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */

+  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */

+  uint32_t        RESERVED2;    /*!< Reserved,  0x1A                                          */

+} SPDIFRX_TypeDef;

+

+

+/**

+  * @brief Secure digital input/output Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t POWER;          /*!< SDMMC power control register,             Address offset: 0x00  */

+  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,             Address offset: 0x04  */

+  __IO uint32_t ARG;            /*!< SDMMC argument register,                  Address offset: 0x08  */

+  __IO uint32_t CMD;            /*!< SDMMC command register,                   Address offset: 0x0C  */

+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register,          Address offset: 0x10  */

+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                Address offset: 0x14  */

+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                Address offset: 0x18  */

+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                Address offset: 0x1C  */

+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                Address offset: 0x20  */

+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                Address offset: 0x24  */

+  __IO uint32_t DLEN;           /*!< SDMMC data length register,               Address offset: 0x28  */

+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,              Address offset: 0x2C  */

+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,              Address offset: 0x30  */

+  __I uint32_t  STA;            /*!< SDMMC status register,                    Address offset: 0x34  */

+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,           Address offset: 0x38  */

+  __IO uint32_t MASK;           /*!< SDMMC mask register,                      Address offset: 0x3C  */

+  __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,     Address offset: 0x40  */

+  uint32_t      RESERVED0[3];   /*!< Reserved, 0x44 - 0x4C - 0x4C                                    */

+  __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,               Address offset: 0x50  */

+  __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,           Address offset: 0x54  */

+  __IO uint32_t IDMABASE0;      /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58  */

+  __IO uint32_t IDMABASE1;      /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C  */

+  uint32_t      RESERVED1[8];   /*!< Reserved, 0x60-0x7C                                             */

+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,                 Address offset: 0x80  */

+  uint32_t      RESERVED2[222]; /*!< Reserved, 0x84-0x3F8                                            */

+  __IO uint32_t IPVR;           /*!< SDMMC data FIFO register,                 Address offset: 0x3FC */

+} SDMMC_TypeDef;

+

+

+/**

+  * @brief Delay Block DLYB

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;          /*!< DELAY BLOCK control register,  Address offset: 0x00 */

+  __IO uint32_t CFGR;        /*!< DELAY BLOCK configuration register,  Address offset: 0x04 */

+} DLYB_TypeDef;

+

+/**

+  * @brief HW Semaphore HSEM

+  */

+

+typedef struct

+{

+  __IO uint32_t R[32];      /*!< 2-step write lock and read back registers,     Address offset: 00h-7Ch  */

+  __IO uint32_t RLR[32];    /*!< 1-step read lock registers,                    Address offset: 80h-FCh  */

+  __IO uint32_t C1IER;      /*!< HSEM Interrupt 0 enable register ,             Address offset: 100h     */

+  __IO uint32_t C1ICR;      /*!< HSEM Interrupt 0 clear register ,              Address offset: 104h     */

+  __IO uint32_t C1ISR;      /*!< HSEM Interrupt 0 Status register ,             Address offset: 108h     */

+  __IO uint32_t C1MISR;     /*!< HSEM Interrupt 0 Masked Status register ,      Address offset: 10Ch     */

+  __IO uint32_t C2IER;      /*!< HSEM Interrupt 1 enable register ,             Address offset: 110h     */

+  __IO uint32_t C2ICR;      /*!< HSEM Interrupt 1 clear register ,              Address offset: 114h     */

+  __IO uint32_t C2ISR;      /*!< HSEM Interrupt 1 Status register ,             Address offset: 118h     */

+  __IO uint32_t C2MISR;     /*!< HSEM Interrupt 1 Masked Status register ,      Address offset: 11Ch     */

+   uint32_t  Reserved[8];   /* Reserved                                         Address offset: 120h-13Ch*/

+  __IO uint32_t CR;         /*!< HSEM Semaphore clear register ,                Address offset: 140h      */

+  __IO uint32_t KEYR;       /*!< HSEM Semaphore clear key register ,            Address offset: 144h      */

+

+} HSEM_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t IER;        /*!< HSEM interrupt enable register ,                Address offset:   0h     */

+  __IO uint32_t ICR;        /*!< HSEM interrupt clear register ,                 Address offset:   4h     */

+  __IO uint32_t ISR;        /*!< HSEM interrupt status register ,                Address offset:   8h     */

+  __IO uint32_t MISR;       /*!< HSEM masked interrupt status register ,         Address offset:   Ch     */

+} HSEM_Common_TypeDef;

+

+/**

+  * @brief Serial Peripheral Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */

+  __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */

+  __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */

+  __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */

+  __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */

+  __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */

+  __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */

+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */

+  __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */

+  uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */

+  __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */

+  uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */

+  __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */

+  __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */

+  __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */

+  __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */

+  __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */

+

+} SPI_TypeDef;

+/**

+  * @brief QUAD Serial Peripheral Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< QUADSPI Control register,                           Address offset: 0x00 */

+  __IO uint32_t DCR;      /*!< QUADSPI Device Configuration register,              Address offset: 0x04 */

+  __IO uint32_t SR;       /*!< QUADSPI Status register,                            Address offset: 0x08 */

+  __IO uint32_t FCR;      /*!< QUADSPI Flag Clear register,                        Address offset: 0x0C */

+  __IO uint32_t DLR;      /*!< QUADSPI Data Length register,                       Address offset: 0x10 */

+  __IO uint32_t CCR;      /*!< QUADSPI Communication Configuration register,       Address offset: 0x14 */

+  __IO uint32_t AR;       /*!< QUADSPI Address register,                           Address offset: 0x18 */

+  __IO uint32_t ABR;      /*!< QUADSPI Alternate Bytes register,                   Address offset: 0x1C */

+  __IO uint32_t DR;       /*!< QUADSPI Data register,                              Address offset: 0x20 */

+  __IO uint32_t PSMKR;    /*!< QUADSPI Polling Status Mask register,               Address offset: 0x24 */

+  __IO uint32_t PSMAR;    /*!< QUADSPI Polling Status Match register,              Address offset: 0x28 */

+  __IO uint32_t PIR;      /*!< QUADSPI Polling Interval register,                  Address offset: 0x2C */

+  __IO uint32_t LPTR;     /*!< QUADSPI Low Power Timeout register,                 Address offset: 0x30 */

+} QUADSPI_TypeDef;

+

+/**

+  * @brief TIM

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */

+  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */

+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */

+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */

+  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */

+  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */

+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */

+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */

+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */

+  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */

+  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */

+  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */

+  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */

+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */

+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */

+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */

+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */

+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */

+  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */

+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */

+  uint32_t      RESERVED1;   /*!< Reserved, 0x50                                                 */

+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */

+  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */

+  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */

+  __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */

+  __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */

+  __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x68 */

+} TIM_TypeDef;

+

+/**

+  * @brief LPTIMIMER

+  */

+typedef struct

+{

+  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,         Address offset: 0x00 */

+  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,              Address offset: 0x04 */

+  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,             Address offset: 0x08 */

+  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                Address offset: 0x0C */

+  __IO uint32_t CR;       /*!< LPTIM Control register,                      Address offset: 0x10 */

+  __IO uint32_t CMP;      /*!< LPTIM Compare register,                      Address offset: 0x14 */

+  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                   Address offset: 0x18 */

+  __IO uint32_t CNT;      /*!< LPTIM Counter register,                      Address offset: 0x1C */

+  uint32_t  RESERVED1;    /*!< Reserved, 0x20                                                    */

+  __IO uint32_t CFGR2;    /*!< LPTIM Configuration register,                Address offset: 0x24 */

+} LPTIM_TypeDef;

+

+/**

+  * @brief Comparator

+  */

+typedef struct

+{

+  __IO uint32_t SR;        /*!< Comparator status register,                    Address offset: 0x00 */

+  __IO uint32_t ICFR;      /*!< Comparator interrupt clear flag register,       Address offset: 0x04 */

+  __IO uint32_t OR;        /*!< Comparator option register,                  Address offset: 0x08 */

+} COMPOPT_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CFGR;      /*!< Comparator configuration register  ,           Address offset: 0x00 */

+} COMP_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CFGR;       /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */

+} COMP_Common_TypeDef;

+/**

+  * @brief Universal Synchronous Asynchronous Receiver Transmitter

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */

+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */

+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */

+  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */

+  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */

+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */

+  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */

+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */

+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */

+  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */

+  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */

+  __IO uint32_t PRESC;  /*!< USART clock Prescaler register,           Address offset: 0x2C */

+} USART_TypeDef;

+

+/**

+  * @brief Single Wire Protocol Master Interface SPWMI

+  */

+typedef struct

+{

+  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */

+  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */

+    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */

+  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */

+  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */

+  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */

+  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */

+  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */

+  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */

+  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */

+} SWPMI_TypeDef;

+

+/**

+  * @brief Window WATCHDOG

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */

+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */

+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */

+} WWDG_TypeDef;

+

+

+/**

+  * @brief RAM_ECC_Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t CR;           /*!< RAMECC monitor configuration register          */

+  __IO uint32_t SR;           /*!< RAMECC monitor status register                 */

+  __IO uint32_t FAR;          /*!< RAMECC monitor failing address register        */

+  __IO uint32_t FDRL;         /*!< RAMECC monitor failing data low register       */

+  __IO uint32_t FDRH;         /*!< RAMECC monitor failing data high register      */

+  __IO uint32_t FECR;         /*!< RAMECC monitor failing ECC error code register */

+} RAMECC_MonitorTypeDef;

+

+typedef struct

+{

+  __IO uint32_t IER;          /*!< RAMECC interrupt enable register */

+} RAMECC_TypeDef;

+/**

+  * @}

+  */

+

+

+/**

+  * @brief Crypto Processor

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */

+  __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */

+  __IO uint32_t DIN;         /*!< CRYP data input register,                                Address offset: 0x08 */

+  __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */

+  __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */

+  __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */

+  __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */

+  __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */

+  __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */

+  __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */

+  __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */

+  __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */

+  __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */

+  __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */

+  __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */

+  __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */

+  __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */

+  __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */

+  __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */

+  __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */

+  __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */

+  __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */

+  __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */

+  __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */

+  __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */

+  __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */

+  __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */

+  __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */

+  __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */

+  __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */

+  __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */

+  __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */

+  __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */

+  __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */

+  __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */

+  __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */

+} CRYP_TypeDef;

+

+/**

+  * @brief HASH

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */

+  __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */

+  __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */

+  __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */

+  __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */

+  __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */

+       uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */

+  __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */

+} HASH_TypeDef;

+

+/**

+  * @brief HASH_DIGEST

+  */

+

+typedef struct

+{

+  __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */

+} HASH_DIGEST_TypeDef;

+

+

+/**

+  * @brief High resolution Timer (HRTIM)

+  */

+/* HRTIM master registers definition */

+typedef struct

+{

+  __IO uint32_t MCR;            /*!< HRTIM Master Timer control register,                     Address offset: 0x00 */

+  __IO uint32_t MISR;           /*!< HRTIM Master Timer interrupt status register,            Address offset: 0x04 */

+  __IO uint32_t MICR;           /*!< HRTIM Master Timer interupt clear register,              Address offset: 0x08 */

+  __IO uint32_t MDIER;          /*!< HRTIM Master Timer DMA/interrupt enable register         Address offset: 0x0C */

+  __IO uint32_t MCNTR;          /*!< HRTIM Master Timer counter register,                     Address offset: 0x10 */

+  __IO uint32_t MPER;           /*!< HRTIM Master Timer period register,                      Address offset: 0x14 */

+  __IO uint32_t MREP;           /*!< HRTIM Master Timer repetition register,                  Address offset: 0x18 */

+  __IO uint32_t MCMP1R;         /*!< HRTIM Master Timer compare 1 register,                   Address offset: 0x1C */

+  uint32_t      RESERVED0;     /*!< Reserved,                                                                 0x20 */

+  __IO uint32_t MCMP2R;         /*!< HRTIM Master Timer compare 2 register,                   Address offset: 0x24 */

+  __IO uint32_t MCMP3R;         /*!< HRTIM Master Timer compare 3 register,                   Address offset: 0x28 */

+  __IO uint32_t MCMP4R;         /*!< HRTIM Master Timer compare 4 register,                   Address offset: 0x2C */

+  uint32_t      RESERVED1[20];  /*!< Reserved,                                                          0x30..0x7C */

+}HRTIM_Master_TypeDef;

+

+/* HRTIM Timer A to E registers definition */

+typedef struct

+{

+  __IO uint32_t TIMxCR;     /*!< HRTIM Timerx control register,                              Address offset: 0x00 */

+  __IO uint32_t TIMxISR;    /*!< HRTIM Timerx interrupt status register,                     Address offset: 0x04 */

+  __IO uint32_t TIMxICR;    /*!< HRTIM Timerx interrupt clear register,                      Address offset: 0x08 */

+  __IO uint32_t TIMxDIER;   /*!< HRTIM Timerx DMA/interrupt enable register,                 Address offset: 0x0C */

+  __IO uint32_t CNTxR;      /*!< HRTIM Timerx counter register,                              Address offset: 0x10 */

+  __IO uint32_t PERxR;      /*!< HRTIM Timerx period register,                               Address offset: 0x14 */

+  __IO uint32_t REPxR;      /*!< HRTIM Timerx repetition register,                           Address offset: 0x18 */

+  __IO uint32_t CMP1xR;     /*!< HRTIM Timerx compare 1 register,                            Address offset: 0x1C */

+  __IO uint32_t CMP1CxR;    /*!< HRTIM Timerx compare 1 compound register,                   Address offset: 0x20 */

+  __IO uint32_t CMP2xR;     /*!< HRTIM Timerx compare 2 register,                            Address offset: 0x24 */

+  __IO uint32_t CMP3xR;     /*!< HRTIM Timerx compare 3 register,                            Address offset: 0x28 */

+  __IO uint32_t CMP4xR;     /*!< HRTIM Timerx compare 4 register,                            Address offset: 0x2C */

+  __IO uint32_t CPT1xR;     /*!< HRTIM Timerx capture 1 register,                            Address offset: 0x30 */

+  __IO uint32_t CPT2xR;     /*!< HRTIM Timerx capture 2 register,                            Address offset: 0x34 */

+  __IO uint32_t DTxR;       /*!< HRTIM Timerx dead time register,                            Address offset: 0x38 */

+  __IO uint32_t SETx1R;     /*!< HRTIM Timerx output 1 set register,                         Address offset: 0x3C */

+  __IO uint32_t RSTx1R;     /*!< HRTIM Timerx output 1 reset register,                       Address offset: 0x40 */

+  __IO uint32_t SETx2R;     /*!< HRTIM Timerx output 2 set register,                         Address offset: 0x44 */

+  __IO uint32_t RSTx2R;     /*!< HRTIM Timerx output 2 reset register,                       Address offset: 0x48 */

+  __IO uint32_t EEFxR1;     /*!< HRTIM Timerx external event filtering 1 register,           Address offset: 0x4C */

+  __IO uint32_t EEFxR2;     /*!< HRTIM Timerx external event filtering 2 register,           Address offset: 0x50 */

+  __IO uint32_t RSTxR;      /*!< HRTIM Timerx Reset register,                                Address offset: 0x54 */

+  __IO uint32_t CHPxR;      /*!< HRTIM Timerx Chopper register,                              Address offset: 0x58 */

+  __IO uint32_t CPT1xCR;    /*!< HRTIM Timerx Capture 1 register,                            Address offset: 0x5C */

+  __IO uint32_t CPT2xCR;    /*!< HRTIM Timerx Capture 2 register,                            Address offset: 0x60 */

+  __IO uint32_t OUTxR;      /*!< HRTIM Timerx Output register,                               Address offset: 0x64 */

+  __IO uint32_t FLTxR;      /*!< HRTIM Timerx Fault register,                                Address offset: 0x68 */

+  uint32_t      RESERVED0[5];  /*!< Reserved,                                                          0x6C..0x7C */

+}HRTIM_Timerx_TypeDef;

+

+/* HRTIM common register definition */

+typedef struct

+{

+  __IO uint32_t CR1;        /*!< HRTIM control register1,                                    Address offset: 0x00 */

+  __IO uint32_t CR2;        /*!< HRTIM control register2,                                    Address offset: 0x04 */

+  __IO uint32_t ISR;        /*!< HRTIM interrupt status register,                            Address offset: 0x08 */

+  __IO uint32_t ICR;        /*!< HRTIM interrupt clear register,                             Address offset: 0x0C */

+  __IO uint32_t IER;        /*!< HRTIM interrupt enable register,                            Address offset: 0x10 */

+  __IO uint32_t OENR;       /*!< HRTIM Output enable register,                               Address offset: 0x14 */

+  __IO uint32_t ODISR;      /*!< HRTIM Output disable register,                              Address offset: 0x18 */

+  __IO uint32_t ODSR;       /*!< HRTIM Output disable status register,                       Address offset: 0x1C */

+  __IO uint32_t BMCR;       /*!< HRTIM Burst mode control register,                          Address offset: 0x20 */

+  __IO uint32_t BMTRGR;     /*!< HRTIM Busrt mode trigger register,                          Address offset: 0x24 */

+  __IO uint32_t BMCMPR;     /*!< HRTIM Burst mode compare register,                          Address offset: 0x28 */

+  __IO uint32_t BMPER;      /*!< HRTIM Burst mode period register,                           Address offset: 0x2C */

+  __IO uint32_t EECR1;      /*!< HRTIM Timer external event control register1,               Address offset: 0x30 */

+  __IO uint32_t EECR2;      /*!< HRTIM Timer external event control register2,               Address offset: 0x34 */

+  __IO uint32_t EECR3;      /*!< HRTIM Timer external event control register3,               Address offset: 0x38 */

+  __IO uint32_t ADC1R;      /*!< HRTIM ADC Trigger 1 register,                               Address offset: 0x3C */

+  __IO uint32_t ADC2R;      /*!< HRTIM ADC Trigger 2 register,                               Address offset: 0x40 */

+  __IO uint32_t ADC3R;      /*!< HRTIM ADC Trigger 3 register,                               Address offset: 0x44 */

+  __IO uint32_t ADC4R;      /*!< HRTIM ADC Trigger 4 register,                               Address offset: 0x48 */

+  __IO uint32_t RESERVED0;  /*!< Reserved,                                                   Address offset: 0x4C */

+  __IO uint32_t FLTINR1;    /*!< HRTIM Fault input register1,                                Address offset: 0x50 */

+  __IO uint32_t FLTINR2;    /*!< HRTIM Fault input register2,                                Address offset: 0x54 */

+  __IO uint32_t BDMUPR;     /*!< HRTIM Burst DMA Master Timer update register,               Address offset: 0x58 */

+  __IO uint32_t BDTAUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x5C */

+  __IO uint32_t BDTBUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x60 */

+  __IO uint32_t BDTCUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x64 */

+  __IO uint32_t BDTDUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x68 */

+  __IO uint32_t BDTEUPR;    /*!< HRTIM Burst DMA Timerx update register,                     Address offset: 0x6C */

+  __IO uint32_t BDMADR;     /*!< HRTIM Burst DMA Master Data register,                       Address offset: 0x70 */

+}HRTIM_Common_TypeDef;

+

+/* HRTIM  register definition */

+typedef struct {

+  HRTIM_Master_TypeDef sMasterRegs;

+  HRTIM_Timerx_TypeDef sTimerxRegs[5];

+  uint32_t             RESERVED0[32];

+  HRTIM_Common_TypeDef sCommonRegs;

+}HRTIM_TypeDef;

+/**

+  * @brief RNG

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */

+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */

+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */

+} RNG_TypeDef;

+

+/**

+  * @brief MDIOS

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;

+  __IO uint32_t WRFR;

+  __IO uint32_t CWRFR;

+  __IO uint32_t RDFR;

+  __IO uint32_t CRDFR;

+  __IO uint32_t SR;

+  __IO uint32_t CLRFR;

+  uint32_t RESERVED[57];

+  __IO uint32_t DINR0;

+  __IO uint32_t DINR1;

+  __IO uint32_t DINR2;

+  __IO uint32_t DINR3;

+  __IO uint32_t DINR4;

+  __IO uint32_t DINR5;

+  __IO uint32_t DINR6;

+  __IO uint32_t DINR7;

+  __IO uint32_t DINR8;

+  __IO uint32_t DINR9;

+  __IO uint32_t DINR10;

+  __IO uint32_t DINR11;

+  __IO uint32_t DINR12;

+  __IO uint32_t DINR13;

+  __IO uint32_t DINR14;

+  __IO uint32_t DINR15;

+  __IO uint32_t DINR16;

+  __IO uint32_t DINR17;

+  __IO uint32_t DINR18;

+  __IO uint32_t DINR19;

+  __IO uint32_t DINR20;

+  __IO uint32_t DINR21;

+  __IO uint32_t DINR22;

+  __IO uint32_t DINR23;

+  __IO uint32_t DINR24;

+  __IO uint32_t DINR25;

+  __IO uint32_t DINR26;

+  __IO uint32_t DINR27;

+  __IO uint32_t DINR28;

+  __IO uint32_t DINR29;

+  __IO uint32_t DINR30;

+  __IO uint32_t DINR31;

+  __IO uint32_t DOUTR0;

+  __IO uint32_t DOUTR1;

+  __IO uint32_t DOUTR2;

+  __IO uint32_t DOUTR3;

+  __IO uint32_t DOUTR4;

+  __IO uint32_t DOUTR5;

+  __IO uint32_t DOUTR6;

+  __IO uint32_t DOUTR7;

+  __IO uint32_t DOUTR8;

+  __IO uint32_t DOUTR9;

+  __IO uint32_t DOUTR10;

+  __IO uint32_t DOUTR11;

+  __IO uint32_t DOUTR12;

+  __IO uint32_t DOUTR13;

+  __IO uint32_t DOUTR14;

+  __IO uint32_t DOUTR15;

+  __IO uint32_t DOUTR16;

+  __IO uint32_t DOUTR17;

+  __IO uint32_t DOUTR18;

+  __IO uint32_t DOUTR19;

+  __IO uint32_t DOUTR20;

+  __IO uint32_t DOUTR21;

+  __IO uint32_t DOUTR22;

+  __IO uint32_t DOUTR23;

+  __IO uint32_t DOUTR24;

+  __IO uint32_t DOUTR25;

+  __IO uint32_t DOUTR26;

+  __IO uint32_t DOUTR27;

+  __IO uint32_t DOUTR28;

+  __IO uint32_t DOUTR29;

+  __IO uint32_t DOUTR30;

+  __IO uint32_t DOUTR31;

+} MDIOS_TypeDef;

+

+

+/**

+  * @brief USB_OTG_Core_Registers

+  */

+typedef struct

+{

+ __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */

+  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */

+  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */

+  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */

+  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */

+  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */

+  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */

+  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */

+  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */

+  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */

+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */

+  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */

+  uint32_t Reserved30[2];             /*!< Reserved                                     030h */

+  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */

+  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */

+  __IO uint32_t GSNPSID;              /* USB_OTG core ID                                040h*/

+  __IO uint32_t GHWCFG1;              /* User HW config1                                044h*/

+  __IO uint32_t GHWCFG2;              /* User HW config2                                048h*/

+  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */

+  uint32_t  Reserved6;                /*!< Reserved                                     050h */

+  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */

+  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */

+  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */

+   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */

+    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */

+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */

+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */

+} USB_OTG_GlobalTypeDef;

+

+

+/**

+  * @brief USB_OTG_device_Registers

+  */

+typedef struct

+{

+  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */

+  __IO uint32_t DCTL;            /*!< dev Control Register         804h */

+  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */

+  uint32_t Reserved0C;           /*!< Reserved                     80Ch */

+  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */

+  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */

+  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */

+  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */

+  uint32_t  Reserved20;          /*!< Reserved                     820h */

+  uint32_t Reserved9;            /*!< Reserved                     824h */

+  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */

+  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */

+  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */

+  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */

+  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */

+  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */

+  uint32_t Reserved40;           /*!< dedicated EP mask            840h */

+  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */

+  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */

+  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */

+} USB_OTG_DeviceTypeDef;

+

+

+/**

+  * @brief USB_OTG_IN_Endpoint-Specific_Register

+  */

+typedef struct

+{

+  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */

+  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */

+  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */

+  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */

+  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */

+  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */

+  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */

+  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */

+} USB_OTG_INEndpointTypeDef;

+

+

+/**

+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */

+  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */

+  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */

+  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */

+  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */

+  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */

+  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */

+} USB_OTG_OUTEndpointTypeDef;

+

+

+/**

+  * @brief USB_OTG_Host_Mode_Register_Structures

+  */

+typedef struct

+{

+  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */

+  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */

+  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */

+  uint32_t Reserved40C;           /*!< Reserved                             40Ch */

+  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */

+  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */

+  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */

+} USB_OTG_HostTypeDef;

+

+/**

+  * @brief USB_OTG_Host_Channel_Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */

+  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */

+  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */

+  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */

+  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */

+  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */

+  uint32_t Reserved[2];           /*!< Reserved                                      */

+} USB_OTG_HostChannelTypeDef;

+/**

+  * @}

+  */

+

+

+/** @addtogroup Peripheral_memory_map

+  * @{

+  */

+#define D1_ITCMRAM_BASE           (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM  */

+#define D1_ITCMICP_BASE           (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM         */

+#define D1_DTCMRAM_BASE           (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM                            */

+#define D1_AXIFLASH_BASE          (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI                */

+#define D1_AXIICP_BASE            (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI          */

+#define D1_AXISRAM_BASE           (0x24000000UL) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI                */

+

+#define D2_AXISRAM_BASE           (0x10000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI                */

+#define D2_AHBSRAM_BASE           (0x30000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge    */

+

+#define D3_BKPSRAM_BASE           (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge                                */

+#define D3_SRAM_BASE              (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge                               */

+

+#define PERIPH_BASE               (0x40000000UL) /*!< Base address of : AHB/APB Peripherals                                                   */

+#define QSPI_BASE                 (0x90000000UL) /*!< Base address of : QSPI memories  accessible over AXI                                    */

+

+#define FLASH_BANK1_BASE          (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI                          */

+#define FLASH_BANK2_BASE          (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI                          */

+#define FLASH_END                 (0x081FFFFFUL) /*!< FLASH end address                                                                       */

+

+/* Legacy define */

+#define FLASH_BASE                FLASH_BANK1_BASE

+

+/*!< Device electronic signature memory map */

+#define UID_BASE                  (0x1FF1E800UL)            /*!< Unique device ID register base address */

+#define FLASHSIZE_BASE            (0x1FF1E880UL)            /*!< FLASH Size register base address */

+

+

+/*!< Peripheral memory map */

+#define D2_APB1PERIPH_BASE        PERIPH_BASE

+#define D2_APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)

+#define D2_AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)

+#define D2_AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)

+

+#define D1_APB1PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)

+#define D1_AHB1PERIPH_BASE       (PERIPH_BASE + 0x12000000UL)

+

+#define D3_APB1PERIPH_BASE       (PERIPH_BASE + 0x18000000UL)

+#define D3_AHB1PERIPH_BASE       (PERIPH_BASE + 0x18020000UL)

+

+/*!< Legacy Peripheral memory map */

+#define APB1PERIPH_BASE        PERIPH_BASE

+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)

+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)

+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08000000UL)

+

+

+/*!< D1_AHB1PERIPH peripherals */

+

+#define MDMA_BASE             (D1_AHB1PERIPH_BASE + 0x0000UL)

+#define DMA2D_BASE            (D1_AHB1PERIPH_BASE + 0x1000UL)

+#define JPGDEC_BASE           (D1_AHB1PERIPH_BASE + 0x3000UL)

+#define FLASH_R_BASE          (D1_AHB1PERIPH_BASE + 0x2000UL)

+#define FMC_R_BASE            (D1_AHB1PERIPH_BASE + 0x4000UL)

+#define QSPI_R_BASE           (D1_AHB1PERIPH_BASE + 0x5000UL)

+#define DLYB_QSPI_BASE        (D1_AHB1PERIPH_BASE + 0x6000UL)

+#define SDMMC1_BASE           (D1_AHB1PERIPH_BASE + 0x7000UL)

+#define DLYB_SDMMC1_BASE      (D1_AHB1PERIPH_BASE + 0x8000UL)

+#define RAMECC1_BASE          (D1_AHB1PERIPH_BASE + 0x9000UL)

+

+/*!< D2_AHB1PERIPH peripherals */

+

+#define DMA1_BASE               (D2_AHB1PERIPH_BASE + 0x0000UL)

+#define DMA2_BASE               (D2_AHB1PERIPH_BASE + 0x0400UL)

+#define DMAMUX1_BASE            (D2_AHB1PERIPH_BASE + 0x0800UL)

+#define ADC1_BASE               (D2_AHB1PERIPH_BASE + 0x2000UL)

+#define ADC2_BASE               (D2_AHB1PERIPH_BASE + 0x2100UL)

+#define ADC12_COMMON_BASE       (D2_AHB1PERIPH_BASE + 0x2300UL)

+#define ART_BASE                (D2_AHB1PERIPH_BASE + 0x4400UL)

+#define ETH_BASE                (D2_AHB1PERIPH_BASE + 0x8000UL)

+#define ETH_MAC_BASE            (ETH_BASE)

+

+/*!< USB registers base address */

+#define USB1_OTG_HS_PERIPH_BASE              (0x40040000UL)

+#define USB2_OTG_FS_PERIPH_BASE              (0x40080000UL)

+#define USB_OTG_GLOBAL_BASE                  (0x000UL)

+#define USB_OTG_DEVICE_BASE                  (0x800UL)

+#define USB_OTG_IN_ENDPOINT_BASE             (0x900UL)

+#define USB_OTG_OUT_ENDPOINT_BASE            (0xB00UL)

+#define USB_OTG_EP_REG_SIZE                  (0x20UL)

+#define USB_OTG_HOST_BASE                    (0x400UL)

+#define USB_OTG_HOST_PORT_BASE               (0x440UL)

+#define USB_OTG_HOST_CHANNEL_BASE            (0x500UL)

+#define USB_OTG_HOST_CHANNEL_SIZE            (0x20UL)

+#define USB_OTG_PCGCCTL_BASE                 (0xE00UL)

+#define USB_OTG_FIFO_BASE                    (0x1000UL)

+#define USB_OTG_FIFO_SIZE                    (0x1000UL)

+

+/*!< D2_AHB2PERIPH peripherals */

+

+#define DCMI_BASE              (D2_AHB2PERIPH_BASE + 0x0000UL)

+#define CRYP_BASE              (D2_AHB2PERIPH_BASE + 0x1000UL)

+#define HASH_BASE              (D2_AHB2PERIPH_BASE + 0x1400UL)

+#define HASH_DIGEST_BASE       (D2_AHB2PERIPH_BASE + 0x1710UL)

+#define RNG_BASE               (D2_AHB2PERIPH_BASE + 0x1800UL)

+#define SDMMC2_BASE            (D2_AHB2PERIPH_BASE + 0x2400UL)

+#define DLYB_SDMMC2_BASE       (D2_AHB2PERIPH_BASE + 0x2800UL)

+#define RAMECC2_BASE           (D2_AHB2PERIPH_BASE + 0x3000UL)

+

+/*!< D3_AHB1PERIPH peripherals */

+#define GPIOA_BASE            (D3_AHB1PERIPH_BASE + 0x0000UL)

+#define GPIOB_BASE            (D3_AHB1PERIPH_BASE + 0x0400UL)

+#define GPIOC_BASE            (D3_AHB1PERIPH_BASE + 0x0800UL)

+#define GPIOD_BASE            (D3_AHB1PERIPH_BASE + 0x0C00UL)

+#define GPIOE_BASE            (D3_AHB1PERIPH_BASE + 0x1000UL)

+#define GPIOF_BASE            (D3_AHB1PERIPH_BASE + 0x1400UL)

+#define GPIOG_BASE            (D3_AHB1PERIPH_BASE + 0x1800UL)

+#define GPIOH_BASE            (D3_AHB1PERIPH_BASE + 0x1C00UL)

+#define GPIOI_BASE            (D3_AHB1PERIPH_BASE + 0x2000UL)

+#define GPIOJ_BASE            (D3_AHB1PERIPH_BASE + 0x2400UL)

+#define GPIOK_BASE            (D3_AHB1PERIPH_BASE + 0x2800UL)

+#define RCC_BASE              (D3_AHB1PERIPH_BASE + 0x4400UL)

+#define RCC_C1_BASE           (RCC_BASE + 0x130UL)

+#define RCC_C2_BASE           (RCC_BASE + 0x190UL)

+#define PWR_BASE              (D3_AHB1PERIPH_BASE + 0x4800UL)

+#define CRC_BASE              (D3_AHB1PERIPH_BASE + 0x4C00UL)

+#define BDMA_BASE             (D3_AHB1PERIPH_BASE + 0x5400UL)

+#define DMAMUX2_BASE          (D3_AHB1PERIPH_BASE + 0x5800UL)

+#define ADC3_BASE             (D3_AHB1PERIPH_BASE + 0x6000UL)

+#define ADC3_COMMON_BASE      (D3_AHB1PERIPH_BASE + 0x6300UL)

+#define HSEM_BASE             (D3_AHB1PERIPH_BASE + 0x6400UL)

+#define RAMECC3_BASE          (D3_AHB1PERIPH_BASE + 0x7000UL)

+

+/*!< D1_APB1PERIPH peripherals */

+#define LTDC_BASE             (D1_APB1PERIPH_BASE + 0x1000UL)

+#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84UL)

+#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104UL)

+#define DSI_BASE              (D1_APB1PERIPH_BASE)

+#define WWDG1_BASE            (D1_APB1PERIPH_BASE + 0x3000UL)

+

+/*!< D2_APB1PERIPH peripherals */

+#define TIM2_BASE             (D2_APB1PERIPH_BASE + 0x0000UL)

+#define TIM3_BASE             (D2_APB1PERIPH_BASE + 0x0400UL)

+#define TIM4_BASE             (D2_APB1PERIPH_BASE + 0x0800UL)

+#define TIM5_BASE             (D2_APB1PERIPH_BASE + 0x0C00UL)

+#define TIM6_BASE             (D2_APB1PERIPH_BASE + 0x1000UL)

+#define TIM7_BASE             (D2_APB1PERIPH_BASE + 0x1400UL)

+#define TIM12_BASE            (D2_APB1PERIPH_BASE + 0x1800UL)

+#define TIM13_BASE            (D2_APB1PERIPH_BASE + 0x1C00UL)

+#define TIM14_BASE            (D2_APB1PERIPH_BASE + 0x2000UL)

+#define LPTIM1_BASE           (D2_APB1PERIPH_BASE + 0x2400UL)

+

+#define WWDG2_BASE            (D2_APB1PERIPH_BASE + 0x2C00UL)

+

+#define SPI2_BASE             (D2_APB1PERIPH_BASE + 0x3800UL)

+#define SPI3_BASE             (D2_APB1PERIPH_BASE + 0x3C00UL)

+#define SPDIFRX_BASE          (D2_APB1PERIPH_BASE + 0x4000UL)

+#define USART2_BASE           (D2_APB1PERIPH_BASE + 0x4400UL)

+#define USART3_BASE           (D2_APB1PERIPH_BASE + 0x4800UL)

+#define UART4_BASE            (D2_APB1PERIPH_BASE + 0x4C00UL)

+#define UART5_BASE            (D2_APB1PERIPH_BASE + 0x5000UL)

+#define I2C1_BASE             (D2_APB1PERIPH_BASE + 0x5400UL)

+#define I2C2_BASE             (D2_APB1PERIPH_BASE + 0x5800UL)

+#define I2C3_BASE             (D2_APB1PERIPH_BASE + 0x5C00UL)

+#define CEC_BASE              (D2_APB1PERIPH_BASE + 0x6C00UL)

+#define DAC1_BASE             (D2_APB1PERIPH_BASE + 0x7400UL)

+#define UART7_BASE            (D2_APB1PERIPH_BASE + 0x7800UL)

+#define UART8_BASE            (D2_APB1PERIPH_BASE + 0x7C00UL)

+#define CRS_BASE              (D2_APB1PERIPH_BASE + 0x8400UL)

+#define SWPMI1_BASE           (D2_APB1PERIPH_BASE + 0x8800UL)

+#define OPAMP_BASE            (D2_APB1PERIPH_BASE + 0x9000UL)

+#define OPAMP1_BASE           (D2_APB1PERIPH_BASE + 0x9000UL)

+#define OPAMP2_BASE           (D2_APB1PERIPH_BASE + 0x9010UL)

+#define MDIOS_BASE            (D2_APB1PERIPH_BASE + 0x9400UL)

+#define FDCAN1_BASE           (D2_APB1PERIPH_BASE + 0xA000UL)

+#define FDCAN2_BASE           (D2_APB1PERIPH_BASE + 0xA400UL)

+#define FDCAN_CCU_BASE        (D2_APB1PERIPH_BASE + 0xA800UL)

+#define SRAMCAN_BASE          (D2_APB1PERIPH_BASE + 0xAC00UL)

+

+/*!< D2_APB2PERIPH peripherals */

+

+#define TIM1_BASE             (D2_APB2PERIPH_BASE + 0x0000UL)

+#define TIM8_BASE             (D2_APB2PERIPH_BASE + 0x0400UL)

+#define USART1_BASE           (D2_APB2PERIPH_BASE + 0x1000UL)

+#define USART6_BASE           (D2_APB2PERIPH_BASE + 0x1400UL)

+#define SPI1_BASE             (D2_APB2PERIPH_BASE + 0x3000UL)

+#define SPI4_BASE             (D2_APB2PERIPH_BASE + 0x3400UL)

+#define TIM15_BASE            (D2_APB2PERIPH_BASE + 0x4000UL)

+#define TIM16_BASE            (D2_APB2PERIPH_BASE + 0x4400UL)

+#define TIM17_BASE            (D2_APB2PERIPH_BASE + 0x4800UL)

+#define SPI5_BASE             (D2_APB2PERIPH_BASE + 0x5000UL)

+#define SAI1_BASE             (D2_APB2PERIPH_BASE + 0x5800UL)

+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)

+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)

+#define SAI2_BASE             (D2_APB2PERIPH_BASE + 0x5C00UL)

+#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004UL)

+#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024UL)

+#define SAI3_BASE             (D2_APB2PERIPH_BASE + 0x6000UL)

+#define SAI3_Block_A_BASE     (SAI3_BASE + 0x004UL)

+#define SAI3_Block_B_BASE     (SAI3_BASE + 0x024UL)

+#define DFSDM1_BASE           (D2_APB2PERIPH_BASE + 0x7000UL)

+#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00UL)

+#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20UL)

+#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40UL)

+#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60UL)

+#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80UL)

+#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0UL)

+#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0UL)

+#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0UL)

+#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)

+#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)

+#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)

+#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)

+#define HRTIM1_BASE           (D2_APB2PERIPH_BASE + 0x7400UL)

+#define HRTIM1_TIMA_BASE      (HRTIM1_BASE + 0x00000080UL)

+#define HRTIM1_TIMB_BASE      (HRTIM1_BASE + 0x00000100UL)

+#define HRTIM1_TIMC_BASE      (HRTIM1_BASE + 0x00000180UL)

+#define HRTIM1_TIMD_BASE      (HRTIM1_BASE + 0x00000200UL)

+#define HRTIM1_TIME_BASE      (HRTIM1_BASE + 0x00000280UL)

+#define HRTIM1_COMMON_BASE    (HRTIM1_BASE + 0x00000380UL)

+

+

+/*!< D3_APB1PERIPH peripherals */

+#define EXTI_BASE             (D3_APB1PERIPH_BASE + 0x0000UL)

+#define EXTI_D1_BASE          (EXTI_BASE + 0x0080UL)

+#define EXTI_D2_BASE          (EXTI_BASE + 0x00C0UL)

+#define SYSCFG_BASE           (D3_APB1PERIPH_BASE + 0x0400UL)

+#define LPUART1_BASE          (D3_APB1PERIPH_BASE + 0x0C00UL)

+#define SPI6_BASE             (D3_APB1PERIPH_BASE + 0x1400UL)

+#define I2C4_BASE             (D3_APB1PERIPH_BASE + 0x1C00UL)

+#define LPTIM2_BASE           (D3_APB1PERIPH_BASE + 0x2400UL)

+#define LPTIM3_BASE           (D3_APB1PERIPH_BASE + 0x2800UL)

+#define LPTIM4_BASE           (D3_APB1PERIPH_BASE + 0x2C00UL)

+#define LPTIM5_BASE           (D3_APB1PERIPH_BASE + 0x3000UL)

+#define COMP12_BASE           (D3_APB1PERIPH_BASE + 0x3800UL)

+#define COMP1_BASE            (COMP12_BASE + 0x0CUL)

+#define COMP2_BASE            (COMP12_BASE + 0x10UL)

+#define VREFBUF_BASE          (D3_APB1PERIPH_BASE + 0x3C00UL)

+#define RTC_BASE              (D3_APB1PERIPH_BASE + 0x4000UL)

+#define IWDG1_BASE            (D3_APB1PERIPH_BASE + 0x4800UL)

+

+#define IWDG2_BASE            (D3_APB1PERIPH_BASE + 0x4C00UL)

+

+#define SAI4_BASE             (D3_APB1PERIPH_BASE + 0x5400UL)

+#define SAI4_Block_A_BASE     (SAI4_BASE + 0x004UL)

+#define SAI4_Block_B_BASE     (SAI4_BASE + 0x024UL)

+

+

+

+

+#define BDMA_Channel0_BASE    (BDMA_BASE + 0x0008UL)

+#define BDMA_Channel1_BASE    (BDMA_BASE + 0x001CUL)

+#define BDMA_Channel2_BASE    (BDMA_BASE + 0x0030UL)

+#define BDMA_Channel3_BASE    (BDMA_BASE + 0x0044UL)

+#define BDMA_Channel4_BASE    (BDMA_BASE + 0x0058UL)

+#define BDMA_Channel5_BASE    (BDMA_BASE + 0x006CUL)

+#define BDMA_Channel6_BASE    (BDMA_BASE + 0x0080UL)

+#define BDMA_Channel7_BASE    (BDMA_BASE + 0x0094UL)

+

+#define DMAMUX2_Channel0_BASE    (DMAMUX2_BASE)

+#define DMAMUX2_Channel1_BASE    (DMAMUX2_BASE + 0x0004UL)

+#define DMAMUX2_Channel2_BASE    (DMAMUX2_BASE + 0x0008UL)

+#define DMAMUX2_Channel3_BASE    (DMAMUX2_BASE + 0x000CUL)

+#define DMAMUX2_Channel4_BASE    (DMAMUX2_BASE + 0x0010UL)

+#define DMAMUX2_Channel5_BASE    (DMAMUX2_BASE + 0x0014UL)

+#define DMAMUX2_Channel6_BASE    (DMAMUX2_BASE + 0x0018UL)

+#define DMAMUX2_Channel7_BASE    (DMAMUX2_BASE + 0x001CUL)

+

+#define DMAMUX2_RequestGenerator0_BASE  (DMAMUX2_BASE + 0x0100UL)

+#define DMAMUX2_RequestGenerator1_BASE  (DMAMUX2_BASE + 0x0104UL)

+#define DMAMUX2_RequestGenerator2_BASE  (DMAMUX2_BASE + 0x0108UL)

+#define DMAMUX2_RequestGenerator3_BASE  (DMAMUX2_BASE + 0x010CUL)

+#define DMAMUX2_RequestGenerator4_BASE  (DMAMUX2_BASE + 0x0110UL)

+#define DMAMUX2_RequestGenerator5_BASE  (DMAMUX2_BASE + 0x0114UL)

+#define DMAMUX2_RequestGenerator6_BASE  (DMAMUX2_BASE + 0x0118UL)

+#define DMAMUX2_RequestGenerator7_BASE  (DMAMUX2_BASE + 0x011CUL)

+

+#define DMAMUX2_ChannelStatus_BASE      (DMAMUX2_BASE + 0x0080UL)

+#define DMAMUX2_RequestGenStatus_BASE   (DMAMUX2_BASE + 0x0140UL)

+

+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)

+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)

+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)

+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)

+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)

+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)

+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)

+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)

+

+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)

+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)

+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)

+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)

+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)

+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)

+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)

+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)

+

+#define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)

+#define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)

+#define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)

+#define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)

+#define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)

+#define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)

+#define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0018UL)

+#define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x001CUL)

+#define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0020UL)

+#define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x0024UL)

+#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)

+#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)

+#define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)

+#define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)

+#define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)

+#define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)

+

+#define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)

+#define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)

+#define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)

+#define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)

+#define DMAMUX1_RequestGenerator4_BASE  (DMAMUX1_BASE + 0x0110UL)

+#define DMAMUX1_RequestGenerator5_BASE  (DMAMUX1_BASE + 0x0114UL)

+#define DMAMUX1_RequestGenerator6_BASE  (DMAMUX1_BASE + 0x0118UL)

+#define DMAMUX1_RequestGenerator7_BASE  (DMAMUX1_BASE + 0x011CUL)

+

+#define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)

+#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)

+

+/*!< FMC Banks registers base  address */

+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)

+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)

+#define FMC_Bank2_R_BASE      (FMC_R_BASE + 0x0060UL)

+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)

+#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)

+

+/* Debug MCU registers base address */

+#define DBGMCU_BASE           (0x5C001000UL)

+

+#define MDMA_Channel0_BASE    (MDMA_BASE + 0x00000040UL)

+#define MDMA_Channel1_BASE    (MDMA_BASE + 0x00000080UL)

+#define MDMA_Channel2_BASE    (MDMA_BASE + 0x000000C0UL)

+#define MDMA_Channel3_BASE    (MDMA_BASE + 0x00000100UL)

+#define MDMA_Channel4_BASE    (MDMA_BASE + 0x00000140UL)

+#define MDMA_Channel5_BASE    (MDMA_BASE + 0x00000180UL)

+#define MDMA_Channel6_BASE    (MDMA_BASE + 0x000001C0UL)

+#define MDMA_Channel7_BASE    (MDMA_BASE + 0x00000200UL)

+#define MDMA_Channel8_BASE    (MDMA_BASE + 0x00000240UL)

+#define MDMA_Channel9_BASE    (MDMA_BASE + 0x00000280UL)

+#define MDMA_Channel10_BASE   (MDMA_BASE + 0x000002C0UL)

+#define MDMA_Channel11_BASE   (MDMA_BASE + 0x00000300UL)

+#define MDMA_Channel12_BASE   (MDMA_BASE + 0x00000340UL)

+#define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)

+#define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)

+#define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)

+

+#define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)

+#define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)

+#define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)

+#define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)

+#define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)

+

+#define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)

+#define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)

+#define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)

+#define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL)

+#define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL)

+

+#define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)

+#define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)

+

+

+/**

+  * @}

+  */

+

+/** @addtogroup Peripheral_declaration

+  * @{

+  */

+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)

+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)

+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)

+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)

+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)

+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)

+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)

+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)

+#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)

+#define RTC                 ((RTC_TypeDef *) RTC_BASE)

+#define WWDG1               ((WWDG_TypeDef *) WWDG1_BASE)

+

+#define WWDG2               ((WWDG_TypeDef *) WWDG2_BASE)

+#define IWDG2               ((IWDG_TypeDef *) IWDG2_BASE)

+

+#define IWDG1               ((IWDG_TypeDef *) IWDG1_BASE)

+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)

+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)

+#define SPI4                ((SPI_TypeDef *) SPI4_BASE)

+#define SPI5                ((SPI_TypeDef *) SPI5_BASE)

+#define SPI6                ((SPI_TypeDef *) SPI6_BASE)

+#define USART2              ((USART_TypeDef *) USART2_BASE)

+#define USART3              ((USART_TypeDef *) USART3_BASE)

+#define USART6              ((USART_TypeDef *) USART6_BASE)

+#define UART7               ((USART_TypeDef *) UART7_BASE)

+#define UART8               ((USART_TypeDef *) UART8_BASE)

+#define CRS                 ((CRS_TypeDef *) CRS_BASE)

+#define UART4               ((USART_TypeDef *) UART4_BASE)

+#define UART5               ((USART_TypeDef *) UART5_BASE)

+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)

+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)

+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)

+#define I2C4                ((I2C_TypeDef *) I2C4_BASE)

+#define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

+#define FDCAN2              ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

+#define FDCAN_CCU           ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

+#define CEC                 ((CEC_TypeDef *) CEC_BASE)

+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)

+#define PWR                 ((PWR_TypeDef *) PWR_BASE)

+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)

+#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)

+#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)

+#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)

+#define LPTIM3              ((LPTIM_TypeDef *) LPTIM3_BASE)

+#define LPTIM4              ((LPTIM_TypeDef *) LPTIM4_BASE)

+#define LPTIM5              ((LPTIM_TypeDef *) LPTIM5_BASE)

+

+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)

+#define COMP12              ((COMPOPT_TypeDef *) COMP12_BASE)

+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)

+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)

+#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)

+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)

+#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)

+#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)

+

+

+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)

+#define EXTI_D1             ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

+#define EXTI_D2             ((EXTI_Core_TypeDef *) EXTI_D2_BASE)

+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)

+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)

+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)

+#define USART1              ((USART_TypeDef *) USART1_BASE)

+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)

+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)

+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)

+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)

+#define HRTIM1              ((HRTIM_TypeDef *) HRTIM1_BASE)

+#define HRTIM1_TIMA         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)

+#define HRTIM1_TIMB         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)

+#define HRTIM1_TIMC         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)

+#define HRTIM1_TIMD         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)

+#define HRTIM1_TIME         ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)

+#define HRTIM1_COMMON       ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)

+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)

+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

+#define SAI2                ((SAI_TypeDef *) SAI2_BASE)

+#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)

+#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)

+#define SAI3                ((SAI_TypeDef *) SAI3_BASE)

+#define SAI3_Block_A        ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)

+#define SAI3_Block_B        ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)

+#define SAI4                ((SAI_TypeDef *) SAI4_BASE)

+#define SAI4_Block_A        ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)

+#define SAI4_Block_B        ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)

+

+#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

+#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

+#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

+#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

+#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

+#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

+#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

+#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

+#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

+#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

+#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

+#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

+#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

+#define DMA2D               ((DMA2D_TypeDef *) DMA2D_BASE)

+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)

+#define RCC                 ((RCC_TypeDef *) RCC_BASE)

+#define RCC_C1              ((RCC_Core_TypeDef *) RCC_C1_BASE)

+#define RCC_C2              ((RCC_Core_TypeDef *) RCC_C2_BASE)

+

+#define ART                 ((ART_TypeDef *)  ART_BASE)

+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)

+#define CRC                 ((CRC_TypeDef *) CRC_BASE)

+

+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)

+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)

+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)

+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)

+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)

+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)

+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)

+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)

+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)

+#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)

+#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)

+

+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)

+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)

+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)

+#define ADC3_COMMON         ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)

+#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

+

+#define CRYP                ((CRYP_TypeDef *) CRYP_BASE)

+#define HASH                ((HASH_TypeDef *) HASH_BASE)

+#define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)

+#define RNG                 ((RNG_TypeDef *) RNG_BASE)

+#define SDMMC2              ((SDMMC_TypeDef *) SDMMC2_BASE)

+#define DLYB_SDMMC2         ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

+

+#define BDMA                ((BDMA_TypeDef *) BDMA_BASE)

+#define BDMA_Channel0       ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)

+#define BDMA_Channel1       ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)

+#define BDMA_Channel2       ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)

+#define BDMA_Channel3       ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)

+#define BDMA_Channel4       ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)

+#define BDMA_Channel5       ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)

+#define BDMA_Channel6       ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)

+#define BDMA_Channel7       ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)

+

+#define RAMECC1              ((RAMECC_TypeDef *)RAMECC1_BASE)

+#define RAMECC1_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)

+#define RAMECC1_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)

+#define RAMECC1_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)

+#define RAMECC1_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)

+#define RAMECC1_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)

+

+#define RAMECC2              ((RAMECC_TypeDef *)RAMECC2_BASE)

+#define RAMECC2_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)

+#define RAMECC2_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)

+#define RAMECC2_Monitor3     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)

+#define RAMECC2_Monitor4     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)

+#define RAMECC2_Monitor5     ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)

+

+#define RAMECC3              ((RAMECC_TypeDef *)RAMECC3_BASE)

+#define RAMECC3_Monitor1     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)

+#define RAMECC3_Monitor2     ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)

+

+#define DMAMUX2                ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

+#define DMAMUX2_Channel0       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

+#define DMAMUX2_Channel1       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

+#define DMAMUX2_Channel2       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

+#define DMAMUX2_Channel3       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

+#define DMAMUX2_Channel4       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

+#define DMAMUX2_Channel5       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

+#define DMAMUX2_Channel6       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

+#define DMAMUX2_Channel7       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

+

+

+#define DMAMUX2_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

+#define DMAMUX2_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

+#define DMAMUX2_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

+#define DMAMUX2_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

+#define DMAMUX2_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

+#define DMAMUX2_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

+#define DMAMUX2_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

+#define DMAMUX2_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

+

+#define DMAMUX2_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

+#define DMAMUX2_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

+

+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)

+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

+

+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)

+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

+

+

+#define DMAMUX1              ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

+#define DMAMUX1_Channel0     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

+#define DMAMUX1_Channel1     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

+#define DMAMUX1_Channel2     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

+#define DMAMUX1_Channel3     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

+#define DMAMUX1_Channel4     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

+#define DMAMUX1_Channel5     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

+#define DMAMUX1_Channel6     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

+#define DMAMUX1_Channel7     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

+#define DMAMUX1_Channel8     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

+#define DMAMUX1_Channel9     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

+#define DMAMUX1_Channel10    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

+#define DMAMUX1_Channel11    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

+#define DMAMUX1_Channel12    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

+#define DMAMUX1_Channel13    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

+#define DMAMUX1_Channel14    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

+#define DMAMUX1_Channel15    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

+

+#define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

+#define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

+#define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

+#define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

+#define DMAMUX1_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

+#define DMAMUX1_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

+#define DMAMUX1_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

+#define DMAMUX1_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

+

+#define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *)    DMAMUX1_ChannelStatus_BASE)

+#define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

+

+

+#define FMC_Bank1_R           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

+#define FMC_Bank1E_R          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

+#define FMC_Bank2_R           ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

+#define FMC_Bank3_R           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

+#define FMC_Bank5_6_R         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

+

+

+#define QUADSPI               ((QUADSPI_TypeDef *) QSPI_R_BASE)

+#define DLYB_QUADSPI          ((DLYB_TypeDef *) DLYB_QSPI_BASE)

+#define SDMMC1                ((SDMMC_TypeDef *) SDMMC1_BASE)

+#define DLYB_SDMMC1           ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

+

+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)

+

+#define JPEG                ((JPEG_TypeDef *) JPGDEC_BASE)

+#define HSEM                ((HSEM_TypeDef *) HSEM_BASE)

+#if defined(CORE_CM4)

+#define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x110UL))

+#else  /* CORE_CM7 */

+#define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

+#endif /* CORE_CM4 */

+

+#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)

+#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

+#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

+#define DSI                 ((DSI_TypeDef *)DSI_BASE)

+

+#define MDIOS               ((MDIOS_TypeDef *) MDIOS_BASE)

+

+#define ETH                 ((ETH_TypeDef *)ETH_BASE)

+#define MDMA                ((MDMA_TypeDef *)MDMA_BASE)

+#define MDMA_Channel0       ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

+#define MDMA_Channel1       ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

+#define MDMA_Channel2       ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

+#define MDMA_Channel3       ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

+#define MDMA_Channel4       ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

+#define MDMA_Channel5       ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

+#define MDMA_Channel6       ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

+#define MDMA_Channel7       ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

+#define MDMA_Channel8       ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

+#define MDMA_Channel9       ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

+#define MDMA_Channel10      ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

+#define MDMA_Channel11      ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

+#define MDMA_Channel12      ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

+#define MDMA_Channel13      ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

+#define MDMA_Channel14      ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

+#define MDMA_Channel15      ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

+

+

+#define USB1_OTG_HS         ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

+#define USB2_OTG_FS         ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)

+

+/* Legacy defines */

+#define USB_OTG_HS                   USB1_OTG_HS

+#define USB_OTG_HS_PERIPH_BASE       USB1_OTG_HS_PERIPH_BASE

+#define USB_OTG_FS                   USB2_OTG_FS

+#define USB_OTG_FS_PERIPH_BASE       USB2_OTG_FS_PERIPH_BASE

+

+/**

+  * @}

+  */

+

+/** @addtogroup Exported_constants

+  * @{

+  */

+

+  /** @addtogroup Peripheral_Registers_Bits_Definition

+  * @{

+  */

+

+/******************************************************************************/

+/*                         Peripheral Registers_Bits_Definition               */

+/******************************************************************************/

+

+/******************************************************************************/

+/*                                                                            */

+/*                        Analog to Digital Converter                         */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  ADC VERSION  ********************************/

+#define ADC_VER_V5_X

+/********************  Bit definition for ADC_ISR register  ********************/

+#define ADC_ISR_ADRDY_Pos                 (0U)

+#define ADC_ISR_ADRDY_Msk                 (0x1UL << ADC_ISR_ADRDY_Pos)         /*!< 0x00000001 */

+#define ADC_ISR_ADRDY                     ADC_ISR_ADRDY_Msk                    /*!< ADC Ready (ADRDY) flag  */

+#define ADC_ISR_EOSMP_Pos                 (1U)

+#define ADC_ISR_EOSMP_Msk                 (0x1UL << ADC_ISR_EOSMP_Pos)         /*!< 0x00000002 */

+#define ADC_ISR_EOSMP                     ADC_ISR_EOSMP_Msk                    /*!< ADC End of Sampling flag */

+#define ADC_ISR_EOC_Pos                   (2U)

+#define ADC_ISR_EOC_Msk                   (0x1UL << ADC_ISR_EOC_Pos)           /*!< 0x00000004 */

+#define ADC_ISR_EOC                       ADC_ISR_EOC_Msk                      /*!< ADC End of Regular Conversion flag */

+#define ADC_ISR_EOS_Pos                   (3U)

+#define ADC_ISR_EOS_Msk                   (0x1UL << ADC_ISR_EOS_Pos)           /*!< 0x00000008 */

+#define ADC_ISR_EOS                       ADC_ISR_EOS_Msk                      /*!< ADC End of Regular sequence of Conversions flag */

+#define ADC_ISR_OVR_Pos                   (4U)

+#define ADC_ISR_OVR_Msk                   (0x1UL << ADC_ISR_OVR_Pos)           /*!< 0x00000010 */

+#define ADC_ISR_OVR                       ADC_ISR_OVR_Msk                      /*!< ADC overrun flag */

+#define ADC_ISR_JEOC_Pos                  (5U)

+#define ADC_ISR_JEOC_Msk                  (0x1UL << ADC_ISR_JEOC_Pos)          /*!< 0x00000020 */

+#define ADC_ISR_JEOC                      ADC_ISR_JEOC_Msk                     /*!< ADC End of Injected Conversion flag */

+#define ADC_ISR_JEOS_Pos                  (6U)

+#define ADC_ISR_JEOS_Msk                  (0x1UL << ADC_ISR_JEOS_Pos)          /*!< 0x00000040 */

+#define ADC_ISR_JEOS                      ADC_ISR_JEOS_Msk                     /*!< ADC End of Injected sequence of Conversions flag */

+#define ADC_ISR_AWD1_Pos                  (7U)

+#define ADC_ISR_AWD1_Msk                  (0x1UL << ADC_ISR_AWD1_Pos)          /*!< 0x00000080 */

+#define ADC_ISR_AWD1                      ADC_ISR_AWD1_Msk                     /*!< ADC Analog watchdog 1 flag */

+#define ADC_ISR_AWD2_Pos                  (8U)

+#define ADC_ISR_AWD2_Msk                  (0x1UL << ADC_ISR_AWD2_Pos)          /*!< 0x00000100 */

+#define ADC_ISR_AWD2                      ADC_ISR_AWD2_Msk                     /*!< ADC Analog watchdog 2 flag */

+#define ADC_ISR_AWD3_Pos                  (9U)

+#define ADC_ISR_AWD3_Msk                  (0x1UL << ADC_ISR_AWD3_Pos)          /*!< 0x00000200 */

+#define ADC_ISR_AWD3                      ADC_ISR_AWD3_Msk                     /*!< ADC Analog watchdog 3 flag */

+#define ADC_ISR_JQOVF_Pos                 (10U)

+#define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */

+#define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */

+

+/********************  Bit definition for ADC_IER register  ********************/

+#define ADC_IER_ADRDYIE_Pos               (0U)

+#define ADC_IER_ADRDYIE_Msk               (0x1UL << ADC_IER_ADRDYIE_Pos)       /*!< 0x00000001 */

+#define ADC_IER_ADRDYIE                   ADC_IER_ADRDYIE_Msk                  /*!< ADC Ready (ADRDY) interrupt source */

+#define ADC_IER_EOSMPIE_Pos               (1U)

+#define ADC_IER_EOSMPIE_Msk               (0x1UL << ADC_IER_EOSMPIE_Pos)       /*!< 0x00000002 */

+#define ADC_IER_EOSMPIE                   ADC_IER_EOSMPIE_Msk                  /*!< ADC End of Sampling interrupt source */

+#define ADC_IER_EOCIE_Pos                 (2U)

+#define ADC_IER_EOCIE_Msk                 (0x1UL << ADC_IER_EOCIE_Pos)         /*!< 0x00000004 */

+#define ADC_IER_EOCIE                     ADC_IER_EOCIE_Msk                    /*!< ADC End of Regular Conversion interrupt source */

+#define ADC_IER_EOSIE_Pos                 (3U)

+#define ADC_IER_EOSIE_Msk                 (0x1UL << ADC_IER_EOSIE_Pos)         /*!< 0x00000008 */

+#define ADC_IER_EOSIE                     ADC_IER_EOSIE_Msk                    /*!< ADC End of Regular sequence of Conversions interrupt source */

+#define ADC_IER_OVRIE_Pos                 (4U)

+#define ADC_IER_OVRIE_Msk                 (0x1UL << ADC_IER_OVRIE_Pos)         /*!< 0x00000010 */

+#define ADC_IER_OVRIE                     ADC_IER_OVRIE_Msk                    /*!< ADC overrun interrupt source */

+#define ADC_IER_JEOCIE_Pos                (5U)

+#define ADC_IER_JEOCIE_Msk                (0x1UL << ADC_IER_JEOCIE_Pos)        /*!< 0x00000020 */

+#define ADC_IER_JEOCIE                    ADC_IER_JEOCIE_Msk                   /*!< ADC End of Injected Conversion interrupt source */

+#define ADC_IER_JEOSIE_Pos                (6U)

+#define ADC_IER_JEOSIE_Msk                (0x1UL << ADC_IER_JEOSIE_Pos)        /*!< 0x00000040 */

+#define ADC_IER_JEOSIE                    ADC_IER_JEOSIE_Msk                   /*!< ADC End of Injected sequence of Conversions interrupt source */

+#define ADC_IER_AWD1IE_Pos                (7U)

+#define ADC_IER_AWD1IE_Msk                (0x1UL << ADC_IER_AWD1IE_Pos)        /*!< 0x00000080 */

+#define ADC_IER_AWD1IE                    ADC_IER_AWD1IE_Msk                   /*!< ADC Analog watchdog 1 interrupt source */

+#define ADC_IER_AWD2IE_Pos                (8U)

+#define ADC_IER_AWD2IE_Msk                (0x1UL << ADC_IER_AWD2IE_Pos)        /*!< 0x00000100 */

+#define ADC_IER_AWD2IE                    ADC_IER_AWD2IE_Msk                   /*!< ADC Analog watchdog 2 interrupt source */

+#define ADC_IER_AWD3IE_Pos                (9U)

+#define ADC_IER_AWD3IE_Msk                (0x1UL << ADC_IER_AWD3IE_Pos)        /*!< 0x00000200 */

+#define ADC_IER_AWD3IE                    ADC_IER_AWD3IE_Msk                   /*!< ADC Analog watchdog 3 interrupt source */

+#define ADC_IER_JQOVFIE_Pos               (10U)

+#define ADC_IER_JQOVFIE_Msk               (0x1UL << ADC_IER_JQOVFIE_Pos)       /*!< 0x00000400 */

+#define ADC_IER_JQOVFIE                   ADC_IER_JQOVFIE_Msk                  /*!< ADC Injected Context Queue Overflow interrupt source */

+

+/********************  Bit definition for ADC_CR register  ********************/

+#define ADC_CR_ADEN_Pos                   (0U)

+#define ADC_CR_ADEN_Msk                   (0x1UL << ADC_CR_ADEN_Pos)           /*!< 0x00000001 */

+#define ADC_CR_ADEN                       ADC_CR_ADEN_Msk                      /*!< ADC Enable control */

+#define ADC_CR_ADDIS_Pos                  (1U)

+#define ADC_CR_ADDIS_Msk                  (0x1UL << ADC_CR_ADDIS_Pos)          /*!< 0x00000002 */

+#define ADC_CR_ADDIS                      ADC_CR_ADDIS_Msk                     /*!< ADC Disable command */

+#define ADC_CR_ADSTART_Pos                (2U)

+#define ADC_CR_ADSTART_Msk                (0x1UL << ADC_CR_ADSTART_Pos)        /*!< 0x00000004 */

+#define ADC_CR_ADSTART                    ADC_CR_ADSTART_Msk                   /*!< ADC Start of Regular conversion */

+#define ADC_CR_JADSTART_Pos               (3U)

+#define ADC_CR_JADSTART_Msk               (0x1UL << ADC_CR_JADSTART_Pos)       /*!< 0x00000008 */

+#define ADC_CR_JADSTART                   ADC_CR_JADSTART_Msk                  /*!< ADC Start of injected conversion */

+#define ADC_CR_ADSTP_Pos                  (4U)

+#define ADC_CR_ADSTP_Msk                  (0x1UL << ADC_CR_ADSTP_Pos)          /*!< 0x00000010 */

+#define ADC_CR_ADSTP                      ADC_CR_ADSTP_Msk                     /*!< ADC Stop of Regular conversion */

+#define ADC_CR_JADSTP_Pos                 (5U)

+#define ADC_CR_JADSTP_Msk                 (0x1UL << ADC_CR_JADSTP_Pos)         /*!< 0x00000020 */

+#define ADC_CR_JADSTP                     ADC_CR_JADSTP_Msk                    /*!< ADC Stop of injected conversion */

+#define ADC_CR_BOOST_Pos                  (8U)

+#define ADC_CR_BOOST_Msk                  (0x3UL << ADC_CR_BOOST_Pos)          /*!< 0x00000300 */

+#define ADC_CR_BOOST                      ADC_CR_BOOST_Msk                     /*!< ADC Boost Mode configuration */

+#define ADC_CR_BOOST_0                    (0x1UL << ADC_CR_BOOST_Pos)           /*!< 0x00000100 */

+#define ADC_CR_BOOST_1                    (0x2UL << ADC_CR_BOOST_Pos)           /*!< 0x00000200 */

+#define ADC_CR_ADCALLIN_Pos               (16U)

+#define ADC_CR_ADCALLIN_Msk               (0x1UL << ADC_CR_ADCALLIN_Pos)       /*!< 0x00010000 */

+#define ADC_CR_ADCALLIN                   ADC_CR_ADCALLIN_Msk                  /*!< ADC Linearity calibration */

+#define ADC_CR_LINCALRDYW1_Pos            (22U)

+#define ADC_CR_LINCALRDYW1_Msk            (0x1UL << ADC_CR_LINCALRDYW1_Pos)    /*!< 0x00400000 */

+#define ADC_CR_LINCALRDYW1                ADC_CR_LINCALRDYW1_Msk               /*!< ADC Linearity calibration ready Word 1 */

+#define ADC_CR_LINCALRDYW2_Pos            (23U)

+#define ADC_CR_LINCALRDYW2_Msk            (0x1UL << ADC_CR_LINCALRDYW2_Pos)    /*!< 0x00800000 */

+#define ADC_CR_LINCALRDYW2                ADC_CR_LINCALRDYW2_Msk               /*!< ADC Linearity calibration ready Word 2 */

+#define ADC_CR_LINCALRDYW3_Pos            (24U)

+#define ADC_CR_LINCALRDYW3_Msk            (0x1UL << ADC_CR_LINCALRDYW3_Pos)    /*!< 0x01000000 */

+#define ADC_CR_LINCALRDYW3                ADC_CR_LINCALRDYW3_Msk               /*!< ADC Linearity calibration ready Word 3 */

+#define ADC_CR_LINCALRDYW4_Pos            (25U)

+#define ADC_CR_LINCALRDYW4_Msk            (0x1UL << ADC_CR_LINCALRDYW4_Pos)    /*!< 0x02000000 */

+#define ADC_CR_LINCALRDYW4                ADC_CR_LINCALRDYW4_Msk               /*!< ADC Linearity calibration ready Word 4 */

+#define ADC_CR_LINCALRDYW5_Pos            (26U)

+#define ADC_CR_LINCALRDYW5_Msk            (0x1UL << ADC_CR_LINCALRDYW5_Pos)    /*!< 0x04000000 */

+#define ADC_CR_LINCALRDYW5                ADC_CR_LINCALRDYW5_Msk               /*!< ADC Linearity calibration ready Word 5 */

+#define ADC_CR_LINCALRDYW6_Pos            (27U)

+#define ADC_CR_LINCALRDYW6_Msk            (0x1UL << ADC_CR_LINCALRDYW6_Pos)    /*!< 0x08000000 */

+#define ADC_CR_LINCALRDYW6                ADC_CR_LINCALRDYW6_Msk               /*!< ADC Linearity calibration ready Word 6 */

+#define ADC_CR_ADVREGEN_Pos               (28U)

+#define ADC_CR_ADVREGEN_Msk               (0x1UL << ADC_CR_ADVREGEN_Pos)       /*!< 0x10000000 */

+#define ADC_CR_ADVREGEN                   ADC_CR_ADVREGEN_Msk                  /*!< ADC Voltage regulator Enable */

+#define ADC_CR_DEEPPWD_Pos                (29U)

+#define ADC_CR_DEEPPWD_Msk                (0x1UL << ADC_CR_DEEPPWD_Pos)        /*!< 0x20000000 */

+#define ADC_CR_DEEPPWD                    ADC_CR_DEEPPWD_Msk                   /*!< ADC Deep power down Enable */

+#define ADC_CR_ADCALDIF_Pos               (30U)

+#define ADC_CR_ADCALDIF_Msk               (0x1UL << ADC_CR_ADCALDIF_Pos)       /*!< 0x40000000 */

+#define ADC_CR_ADCALDIF                   ADC_CR_ADCALDIF_Msk                  /*!< ADC Differential Mode for calibration */

+#define ADC_CR_ADCAL_Pos                  (31U)

+#define ADC_CR_ADCAL_Msk                  (0x1UL << ADC_CR_ADCAL_Pos)          /*!< 0x80000000 */

+#define ADC_CR_ADCAL                      ADC_CR_ADCAL_Msk                     /*!< ADC Calibration */

+

+/********************  Bit definition for ADC_CFGR register  ********************/

+#define ADC_CFGR_DMNGT_Pos                (0U)

+#define ADC_CFGR_DMNGT_Msk                (0x3UL << ADC_CFGR_DMNGT_Pos)        /*!< 0x00000003 */

+#define ADC_CFGR_DMNGT                    ADC_CFGR_DMNGT_Msk                   /*!< ADC Data Management configuration */

+#define ADC_CFGR_DMNGT_0                  (0x1UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000001 */

+#define ADC_CFGR_DMNGT_1                  (0x2UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000002 */

+

+#define ADC_CFGR_RES_Pos                  (2U)

+#define ADC_CFGR_RES_Msk                  (0x7UL << ADC_CFGR_RES_Pos)          /*!< 0x0000001C */

+#define ADC_CFGR_RES                      ADC_CFGR_RES_Msk                     /*!< ADC Data resolution */

+#define ADC_CFGR_RES_0                    (0x1UL << ADC_CFGR_RES_Pos)           /*!< 0x00000004 */

+#define ADC_CFGR_RES_1                    (0x2UL << ADC_CFGR_RES_Pos)           /*!< 0x00000008 */

+#define ADC_CFGR_RES_2                    (0x4UL << ADC_CFGR_RES_Pos)           /*!< 0x00000010 */

+

+#define ADC_CFGR_EXTSEL_Pos               (5U)

+#define ADC_CFGR_EXTSEL_Msk               (0x1FUL << ADC_CFGR_EXTSEL_Pos)      /*!< 0x000003E0 */

+#define ADC_CFGR_EXTSEL                   ADC_CFGR_EXTSEL_Msk                  /*!< ADC External trigger selection for regular group */

+#define ADC_CFGR_EXTSEL_0                 (0x01UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000020 */

+#define ADC_CFGR_EXTSEL_1                 (0x02UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000040 */

+#define ADC_CFGR_EXTSEL_2                 (0x04UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000080 */

+#define ADC_CFGR_EXTSEL_3                 (0x08UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000100 */

+#define ADC_CFGR_EXTSEL_4                 (0x10UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000200 */

+

+#define ADC_CFGR_EXTEN_Pos                (10U)

+#define ADC_CFGR_EXTEN_Msk                (0x3UL << ADC_CFGR_EXTEN_Pos)        /*!< 0x00000C00 */

+#define ADC_CFGR_EXTEN                    ADC_CFGR_EXTEN_Msk                   /*!< ADC External trigger enable and polarity selection for regular channels */

+#define ADC_CFGR_EXTEN_0                  (0x1UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000400 */

+#define ADC_CFGR_EXTEN_1                  (0x2UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000800 */

+

+#define ADC_CFGR_OVRMOD_Pos               (12U)

+#define ADC_CFGR_OVRMOD_Msk               (0x1UL << ADC_CFGR_OVRMOD_Pos)       /*!< 0x00001000 */

+#define ADC_CFGR_OVRMOD                   ADC_CFGR_OVRMOD_Msk                  /*!< ADC overrun mode */

+#define ADC_CFGR_CONT_Pos                 (13U)

+#define ADC_CFGR_CONT_Msk                 (0x1UL << ADC_CFGR_CONT_Pos)         /*!< 0x00002000 */

+#define ADC_CFGR_CONT                     ADC_CFGR_CONT_Msk                    /*!< ADC Single/continuous conversion mode for regular conversion */

+#define ADC_CFGR_AUTDLY_Pos               (14U)

+#define ADC_CFGR_AUTDLY_Msk               (0x1UL << ADC_CFGR_AUTDLY_Pos)       /*!< 0x00004000 */

+#define ADC_CFGR_AUTDLY                   ADC_CFGR_AUTDLY_Msk                  /*!< ADC Delayed conversion mode */

+

+#define ADC_CFGR_DISCEN_Pos               (16U)

+#define ADC_CFGR_DISCEN_Msk               (0x1UL << ADC_CFGR_DISCEN_Pos)       /*!< 0x00010000 */

+#define ADC_CFGR_DISCEN                   ADC_CFGR_DISCEN_Msk                  /*!< ADC Discontinuous mode for regular channels */

+

+#define ADC_CFGR_DISCNUM_Pos              (17U)

+#define ADC_CFGR_DISCNUM_Msk              (0x7UL << ADC_CFGR_DISCNUM_Pos)      /*!< 0x000E0000 */

+#define ADC_CFGR_DISCNUM                  ADC_CFGR_DISCNUM_Msk                 /*!< ADC Discontinuous mode channel count */

+#define ADC_CFGR_DISCNUM_0                (0x1UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00020000 */

+#define ADC_CFGR_DISCNUM_1                (0x2UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00040000 */

+#define ADC_CFGR_DISCNUM_2                (0x4UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00080000 */

+

+#define ADC_CFGR_JDISCEN_Pos              (20U)

+#define ADC_CFGR_JDISCEN_Msk              (0x1UL << ADC_CFGR_JDISCEN_Pos)      /*!< 0x00100000 */

+#define ADC_CFGR_JDISCEN                  ADC_CFGR_JDISCEN_Msk                 /*!< ADC Discontinuous mode on injected channels */

+#define ADC_CFGR_JQM_Pos                  (21U)

+#define ADC_CFGR_JQM_Msk                  (0x1UL << ADC_CFGR_JQM_Pos)          /*!< 0x00200000 */

+#define ADC_CFGR_JQM                      ADC_CFGR_JQM_Msk                     /*!< ADC JSQR Queue mode */

+#define ADC_CFGR_AWD1SGL_Pos              (22U)

+#define ADC_CFGR_AWD1SGL_Msk              (0x1UL << ADC_CFGR_AWD1SGL_Pos)      /*!< 0x00400000 */

+#define ADC_CFGR_AWD1SGL                  ADC_CFGR_AWD1SGL_Msk                 /*!< Enable the watchdog 1 on a single channel or on all channels */

+#define ADC_CFGR_AWD1EN_Pos               (23U)

+#define ADC_CFGR_AWD1EN_Msk               (0x1UL << ADC_CFGR_AWD1EN_Pos)       /*!< 0x00800000 */

+#define ADC_CFGR_AWD1EN                   ADC_CFGR_AWD1EN_Msk                  /*!< ADC Analog watchdog 1 enable on regular Channels */

+#define ADC_CFGR_JAWD1EN_Pos              (24U)

+#define ADC_CFGR_JAWD1EN_Msk              (0x1UL << ADC_CFGR_JAWD1EN_Pos)      /*!< 0x01000000 */

+#define ADC_CFGR_JAWD1EN                  ADC_CFGR_JAWD1EN_Msk                 /*!< ADC Analog watchdog 1 enable on injected Channels */

+#define ADC_CFGR_JAUTO_Pos                (25U)

+#define ADC_CFGR_JAUTO_Msk                (0x1UL << ADC_CFGR_JAUTO_Pos)        /*!< 0x02000000 */

+#define ADC_CFGR_JAUTO                    ADC_CFGR_JAUTO_Msk                   /*!< ADC Automatic injected group conversion */

+

+#define ADC_CFGR_AWD1CH_Pos               (26U)

+#define ADC_CFGR_AWD1CH_Msk               (0x1FUL << ADC_CFGR_AWD1CH_Pos)      /*!< 0x7C000000 */

+#define ADC_CFGR_AWD1CH                   ADC_CFGR_AWD1CH_Msk                  /*!< ADC Analog watchdog 1 Channel selection */

+#define ADC_CFGR_AWD1CH_0                 (0x01UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x04000000 */

+#define ADC_CFGR_AWD1CH_1                 (0x02UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x08000000 */

+#define ADC_CFGR_AWD1CH_2                 (0x04UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x10000000 */

+#define ADC_CFGR_AWD1CH_3                 (0x08UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x20000000 */

+#define ADC_CFGR_AWD1CH_4                 (0x10UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x40000000 */

+

+#define ADC_CFGR_JQDIS_Pos                (31U)

+#define ADC_CFGR_JQDIS_Msk                (0x1UL << ADC_CFGR_JQDIS_Pos)        /*!< 0x80000000 */

+#define ADC_CFGR_JQDIS                    ADC_CFGR_JQDIS_Msk                   /*!< ADC Injected queue disable */

+

+/********************  Bit definition for ADC_CFGR2 register  ********************/

+#define ADC_CFGR2_ROVSE_Pos               (0U)

+#define ADC_CFGR2_ROVSE_Msk               (0x1UL << ADC_CFGR2_ROVSE_Pos)       /*!< 0x00000001 */

+#define ADC_CFGR2_ROVSE                   ADC_CFGR2_ROVSE_Msk                  /*!< ADC Regular group oversampler enable */

+#define ADC_CFGR2_JOVSE_Pos               (1U)

+#define ADC_CFGR2_JOVSE_Msk               (0x1UL << ADC_CFGR2_JOVSE_Pos)       /*!< 0x00000002 */

+#define ADC_CFGR2_JOVSE                   ADC_CFGR2_JOVSE_Msk                  /*!< ADC Injected group oversampler enable */

+

+#define ADC_CFGR2_OVSS_Pos                (5U)

+#define ADC_CFGR2_OVSS_Msk                (0xFUL << ADC_CFGR2_OVSS_Pos)        /*!< 0x000001E0 */

+#define ADC_CFGR2_OVSS                    ADC_CFGR2_OVSS_Msk                   /*!< ADC Regular Oversampling shift */

+#define ADC_CFGR2_OVSS_0                  (0x1UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000020 */

+#define ADC_CFGR2_OVSS_1                  (0x2UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000040 */

+#define ADC_CFGR2_OVSS_2                  (0x4UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000080 */

+#define ADC_CFGR2_OVSS_3                  (0x8UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000100 */

+

+#define ADC_CFGR2_TROVS_Pos               (9U)

+#define ADC_CFGR2_TROVS_Msk               (0x1UL << ADC_CFGR2_TROVS_Pos)       /*!< 0x00000200 */

+#define ADC_CFGR2_TROVS                   ADC_CFGR2_TROVS_Msk                  /*!< ADC Triggered regular Oversampling */

+#define ADC_CFGR2_ROVSM_Pos               (10U)

+#define ADC_CFGR2_ROVSM_Msk               (0x1UL << ADC_CFGR2_ROVSM_Pos)       /*!< 0x00000400 */

+#define ADC_CFGR2_ROVSM                   ADC_CFGR2_ROVSM_Msk                  /*!< ADC Regular oversampling mode */

+

+#define ADC_CFGR2_RSHIFT1_Pos             (11U)

+#define ADC_CFGR2_RSHIFT1_Msk             (0x1UL << ADC_CFGR2_RSHIFT1_Pos)     /*!< 0x00000800 */

+#define ADC_CFGR2_RSHIFT1                 ADC_CFGR2_RSHIFT1_Msk                /*!< ADC Right-shift data after Offset 1 correction */

+#define ADC_CFGR2_RSHIFT2_Pos             (12U)

+#define ADC_CFGR2_RSHIFT2_Msk             (0x1UL << ADC_CFGR2_RSHIFT2_Pos)     /*!< 0x00001000 */

+#define ADC_CFGR2_RSHIFT2                 ADC_CFGR2_RSHIFT2_Msk                /*!< ADC Right-shift data after Offset 2 correction */

+#define ADC_CFGR2_RSHIFT3_Pos             (13U)

+#define ADC_CFGR2_RSHIFT3_Msk             (0x1UL << ADC_CFGR2_RSHIFT3_Pos)     /*!< 0x00002000 */

+#define ADC_CFGR2_RSHIFT3                 ADC_CFGR2_RSHIFT3_Msk                /*!< ADC Right-shift data after Offset 3 correction */

+#define ADC_CFGR2_RSHIFT4_Pos             (14U)

+#define ADC_CFGR2_RSHIFT4_Msk             (0x1UL << ADC_CFGR2_RSHIFT4_Pos)     /*!< 0x00004000 */

+#define ADC_CFGR2_RSHIFT4                 ADC_CFGR2_RSHIFT4_Msk                /*!< ADC Right-shift data after Offset 4 correction */

+

+#define ADC_CFGR2_OVSR_Pos                (16U)

+#define ADC_CFGR2_OVSR_Msk                (0x3FFUL << ADC_CFGR2_OVSR_Pos)      /*!< 0x03FF0000 */

+#define ADC_CFGR2_OVSR                    ADC_CFGR2_OVSR_Msk                   /*!< ADC oversampling Ratio */

+#define ADC_CFGR2_OVSR_0                  (0x001UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00010000 */

+#define ADC_CFGR2_OVSR_1                  (0x002UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00020000 */

+#define ADC_CFGR2_OVSR_2                  (0x004UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00040000 */

+#define ADC_CFGR2_OVSR_3                  (0x008UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00080000 */

+#define ADC_CFGR2_OVSR_4                  (0x010UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00100000 */

+#define ADC_CFGR2_OVSR_5                  (0x020UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00200000 */

+#define ADC_CFGR2_OVSR_6                  (0x040UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00400000 */

+#define ADC_CFGR2_OVSR_7                  (0x080UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00800000 */

+#define ADC_CFGR2_OVSR_8                  (0x100UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x01000000 */

+#define ADC_CFGR2_OVSR_9                  (0x200UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x02000000 */

+

+#define ADC_CFGR2_LSHIFT_Pos              (28U)

+#define ADC_CFGR2_LSHIFT_Msk              (0xFUL << ADC_CFGR2_LSHIFT_Pos)      /*!< 0xF0000000 */

+#define ADC_CFGR2_LSHIFT                  ADC_CFGR2_LSHIFT_Msk                 /*!< ADC Left shift factor */

+#define ADC_CFGR2_LSHIFT_0                (0x1UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x10000000 */

+#define ADC_CFGR2_LSHIFT_1                (0x2UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x20000000 */

+#define ADC_CFGR2_LSHIFT_2                (0x4UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x40000000 */

+#define ADC_CFGR2_LSHIFT_3                (0x8UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_SMPR1 register  ********************/

+#define ADC_SMPR1_SMP0_Pos                (0U)

+#define ADC_SMPR1_SMP0_Msk                (0x7UL << ADC_SMPR1_SMP0_Pos)        /*!< 0x00000007 */

+#define ADC_SMPR1_SMP0                    ADC_SMPR1_SMP0_Msk                   /*!< ADC Channel 0 Sampling time selection  */

+#define ADC_SMPR1_SMP0_0                  (0x1UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000001 */

+#define ADC_SMPR1_SMP0_1                  (0x2UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000002 */

+#define ADC_SMPR1_SMP0_2                  (0x4UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000004 */

+

+#define ADC_SMPR1_SMP1_Pos                (3U)

+#define ADC_SMPR1_SMP1_Msk                (0x7UL << ADC_SMPR1_SMP1_Pos)        /*!< 0x00000038 */

+#define ADC_SMPR1_SMP1                    ADC_SMPR1_SMP1_Msk                   /*!< ADC Channel 1 Sampling time selection  */

+#define ADC_SMPR1_SMP1_0                  (0x1UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000008 */

+#define ADC_SMPR1_SMP1_1                  (0x2UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000010 */

+#define ADC_SMPR1_SMP1_2                  (0x4UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000020 */

+

+#define ADC_SMPR1_SMP2_Pos                (6U)

+#define ADC_SMPR1_SMP2_Msk                (0x7UL << ADC_SMPR1_SMP2_Pos)        /*!< 0x000001C0 */

+#define ADC_SMPR1_SMP2                    ADC_SMPR1_SMP2_Msk                   /*!< ADC Channel 2 Sampling time selection  */

+#define ADC_SMPR1_SMP2_0                  (0x1UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000040 */

+#define ADC_SMPR1_SMP2_1                  (0x2UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000080 */

+#define ADC_SMPR1_SMP2_2                  (0x4UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000100 */

+

+#define ADC_SMPR1_SMP3_Pos                (9U)

+#define ADC_SMPR1_SMP3_Msk                (0x7UL << ADC_SMPR1_SMP3_Pos)        /*!< 0x00000E00 */

+#define ADC_SMPR1_SMP3                    ADC_SMPR1_SMP3_Msk                   /*!< ADC Channel 3 Sampling time selection  */

+#define ADC_SMPR1_SMP3_0                  (0x1UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000200 */

+#define ADC_SMPR1_SMP3_1                  (0x2UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000400 */

+#define ADC_SMPR1_SMP3_2                  (0x4UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000800 */

+

+#define ADC_SMPR1_SMP4_Pos                (12U)

+#define ADC_SMPR1_SMP4_Msk                (0x7UL << ADC_SMPR1_SMP4_Pos)        /*!< 0x00007000 */

+#define ADC_SMPR1_SMP4                    ADC_SMPR1_SMP4_Msk                   /*!< ADC Channel 4 Sampling time selection  */

+#define ADC_SMPR1_SMP4_0                  (0x1UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00001000 */

+#define ADC_SMPR1_SMP4_1                  (0x2UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00002000 */

+#define ADC_SMPR1_SMP4_2                  (0x4UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00004000 */

+

+#define ADC_SMPR1_SMP5_Pos                (15U)

+#define ADC_SMPR1_SMP5_Msk                (0x7UL << ADC_SMPR1_SMP5_Pos)        /*!< 0x00038000 */

+#define ADC_SMPR1_SMP5                    ADC_SMPR1_SMP5_Msk                   /*!< ADC Channel 5 Sampling time selection  */

+#define ADC_SMPR1_SMP5_0                  (0x1UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00008000 */

+#define ADC_SMPR1_SMP5_1                  (0x2UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00010000 */

+#define ADC_SMPR1_SMP5_2                  (0x4UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00020000 */

+

+#define ADC_SMPR1_SMP6_Pos                (18U)

+#define ADC_SMPR1_SMP6_Msk                (0x7UL << ADC_SMPR1_SMP6_Pos)        /*!< 0x001C0000 */

+#define ADC_SMPR1_SMP6                    ADC_SMPR1_SMP6_Msk                   /*!< ADC Channel 6 Sampling time selection  */

+#define ADC_SMPR1_SMP6_0                  (0x1UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00040000 */

+#define ADC_SMPR1_SMP6_1                  (0x2UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00080000 */

+#define ADC_SMPR1_SMP6_2                  (0x4UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00100000 */

+

+#define ADC_SMPR1_SMP7_Pos                (21U)

+#define ADC_SMPR1_SMP7_Msk                (0x7UL << ADC_SMPR1_SMP7_Pos)        /*!< 0x00E00000 */

+#define ADC_SMPR1_SMP7                    ADC_SMPR1_SMP7_Msk                   /*!< ADC Channel 7 Sampling time selection  */

+#define ADC_SMPR1_SMP7_0                  (0x1UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00200000 */

+#define ADC_SMPR1_SMP7_1                  (0x2UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00400000 */

+#define ADC_SMPR1_SMP7_2                  (0x4UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00800000 */

+

+#define ADC_SMPR1_SMP8_Pos                (24U)

+#define ADC_SMPR1_SMP8_Msk                (0x7UL << ADC_SMPR1_SMP8_Pos)        /*!< 0x07000000 */

+#define ADC_SMPR1_SMP8                    ADC_SMPR1_SMP8_Msk                   /*!< ADC Channel 8 Sampling time selection  */

+#define ADC_SMPR1_SMP8_0                  (0x1UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x01000000 */

+#define ADC_SMPR1_SMP8_1                  (0x2UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x02000000 */

+#define ADC_SMPR1_SMP8_2                  (0x4UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x04000000 */

+

+#define ADC_SMPR1_SMP9_Pos                (27U)

+#define ADC_SMPR1_SMP9_Msk                (0x7UL << ADC_SMPR1_SMP9_Pos)        /*!< 0x38000000 */

+#define ADC_SMPR1_SMP9                    ADC_SMPR1_SMP9_Msk                   /*!< ADC Channel 9 Sampling time selection  */

+#define ADC_SMPR1_SMP9_0                  (0x1UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x08000000 */

+#define ADC_SMPR1_SMP9_1                  (0x2UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x10000000 */

+#define ADC_SMPR1_SMP9_2                  (0x4UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x20000000 */

+

+/********************  Bit definition for ADC_SMPR2 register  ********************/

+#define ADC_SMPR2_SMP10_Pos               (0U)

+#define ADC_SMPR2_SMP10_Msk               (0x7UL << ADC_SMPR2_SMP10_Pos)       /*!< 0x00000007 */

+#define ADC_SMPR2_SMP10                   ADC_SMPR2_SMP10_Msk                  /*!< ADC Channel 10 Sampling time selection  */

+#define ADC_SMPR2_SMP10_0                 (0x1UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000001 */

+#define ADC_SMPR2_SMP10_1                 (0x2UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000002 */

+#define ADC_SMPR2_SMP10_2                 (0x4UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000004 */

+

+#define ADC_SMPR2_SMP11_Pos               (3U)

+#define ADC_SMPR2_SMP11_Msk               (0x7UL << ADC_SMPR2_SMP11_Pos)       /*!< 0x00000038 */

+#define ADC_SMPR2_SMP11                   ADC_SMPR2_SMP11_Msk                  /*!< ADC Channel 11 Sampling time selection  */

+#define ADC_SMPR2_SMP11_0                 (0x1UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000008 */

+#define ADC_SMPR2_SMP11_1                 (0x2UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000010 */

+#define ADC_SMPR2_SMP11_2                 (0x4UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000020 */

+

+#define ADC_SMPR2_SMP12_Pos               (6U)

+#define ADC_SMPR2_SMP12_Msk               (0x7UL << ADC_SMPR2_SMP12_Pos)       /*!< 0x000001C0 */

+#define ADC_SMPR2_SMP12                   ADC_SMPR2_SMP12_Msk                  /*!< ADC Channel 12 Sampling time selection  */

+#define ADC_SMPR2_SMP12_0                 (0x1UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000040 */

+#define ADC_SMPR2_SMP12_1                 (0x2UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000080 */

+#define ADC_SMPR2_SMP12_2                 (0x4UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000100 */

+

+#define ADC_SMPR2_SMP13_Pos               (9U)

+#define ADC_SMPR2_SMP13_Msk               (0x7UL << ADC_SMPR2_SMP13_Pos)       /*!< 0x00000E00 */

+#define ADC_SMPR2_SMP13                   ADC_SMPR2_SMP13_Msk                  /*!< ADC Channel 13 Sampling time selection  */

+#define ADC_SMPR2_SMP13_0                 (0x1UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000200 */

+#define ADC_SMPR2_SMP13_1                 (0x2UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000400 */

+#define ADC_SMPR2_SMP13_2                 (0x4UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000800 */

+

+#define ADC_SMPR2_SMP14_Pos               (12U)

+#define ADC_SMPR2_SMP14_Msk               (0x7UL << ADC_SMPR2_SMP14_Pos)       /*!< 0x00007000 */

+#define ADC_SMPR2_SMP14                   ADC_SMPR2_SMP14_Msk                  /*!< ADC Channel 14 Sampling time selection  */

+#define ADC_SMPR2_SMP14_0                 (0x1UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00001000 */

+#define ADC_SMPR2_SMP14_1                 (0x2UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00002000 */

+#define ADC_SMPR2_SMP14_2                 (0x4UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00004000 */

+

+#define ADC_SMPR2_SMP15_Pos               (15U)

+#define ADC_SMPR2_SMP15_Msk               (0x7UL << ADC_SMPR2_SMP15_Pos)       /*!< 0x00038000 */

+#define ADC_SMPR2_SMP15                   ADC_SMPR2_SMP15_Msk                  /*!< ADC Channel 15 Sampling time selection  */

+#define ADC_SMPR2_SMP15_0                 (0x1UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00008000 */

+#define ADC_SMPR2_SMP15_1                 (0x2UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00010000 */

+#define ADC_SMPR2_SMP15_2                 (0x4UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00020000 */

+

+#define ADC_SMPR2_SMP16_Pos               (18U)

+#define ADC_SMPR2_SMP16_Msk               (0x7UL << ADC_SMPR2_SMP16_Pos)       /*!< 0x001C0000 */

+#define ADC_SMPR2_SMP16                   ADC_SMPR2_SMP16_Msk                  /*!< ADC Channel 16 Sampling time selection  */

+#define ADC_SMPR2_SMP16_0                 (0x1UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00040000 */

+#define ADC_SMPR2_SMP16_1                 (0x2UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00080000 */

+#define ADC_SMPR2_SMP16_2                 (0x4UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00100000 */

+

+#define ADC_SMPR2_SMP17_Pos               (21U)

+#define ADC_SMPR2_SMP17_Msk               (0x7UL << ADC_SMPR2_SMP17_Pos)       /*!< 0x00E00000 */

+#define ADC_SMPR2_SMP17                   ADC_SMPR2_SMP17_Msk                  /*!< ADC Channel 17 Sampling time selection  */

+#define ADC_SMPR2_SMP17_0                 (0x1UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00200000 */

+#define ADC_SMPR2_SMP17_1                 (0x2UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00400000 */

+#define ADC_SMPR2_SMP17_2                 (0x4UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00800000 */

+

+#define ADC_SMPR2_SMP18_Pos               (24U)

+#define ADC_SMPR2_SMP18_Msk               (0x7UL << ADC_SMPR2_SMP18_Pos)       /*!< 0x07000000 */

+#define ADC_SMPR2_SMP18                   ADC_SMPR2_SMP18_Msk                  /*!< ADC Channel 18 Sampling time selection  */

+#define ADC_SMPR2_SMP18_0                 (0x1UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x01000000 */

+#define ADC_SMPR2_SMP18_1                 (0x2UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x02000000 */

+#define ADC_SMPR2_SMP18_2                 (0x4UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x04000000 */

+

+#define ADC_SMPR2_SMP19_Pos               (27U)

+#define ADC_SMPR2_SMP19_Msk               (0x7UL << ADC_SMPR2_SMP19_Pos)       /*!< 0x38000000 */

+#define ADC_SMPR2_SMP19                   ADC_SMPR2_SMP19_Msk                  /*!< ADC Channel 19 Sampling time selection  */

+#define ADC_SMPR2_SMP19_0                 (0x1UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x08000000 */

+#define ADC_SMPR2_SMP19_1                 (0x2UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x10000000 */

+#define ADC_SMPR2_SMP19_2                 (0x4UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x20000000 */

+

+/********************  Bit definition for ADC_PCSEL register  ********************/

+#define ADC_PCSEL_PCSEL_Pos               (0U)

+#define ADC_PCSEL_PCSEL_Msk               (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)   /*!< 0x000FFFFF */

+#define ADC_PCSEL_PCSEL                   ADC_PCSEL_PCSEL_Msk                  /*!< ADC pre channel selection */

+#define ADC_PCSEL_PCSEL_0                 (0x00001UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */

+#define ADC_PCSEL_PCSEL_1                 (0x00002UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */

+#define ADC_PCSEL_PCSEL_2                 (0x00004UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */

+#define ADC_PCSEL_PCSEL_3                 (0x00008UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */

+#define ADC_PCSEL_PCSEL_4                 (0x00010UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */

+#define ADC_PCSEL_PCSEL_5                 (0x00020UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */

+#define ADC_PCSEL_PCSEL_6                 (0x00040UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */

+#define ADC_PCSEL_PCSEL_7                 (0x00080UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */

+#define ADC_PCSEL_PCSEL_8                 (0x00100UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */

+#define ADC_PCSEL_PCSEL_9                 (0x00200UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */

+#define ADC_PCSEL_PCSEL_10                (0x00400UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */

+#define ADC_PCSEL_PCSEL_11                (0x00800UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */

+#define ADC_PCSEL_PCSEL_12                (0x01000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */

+#define ADC_PCSEL_PCSEL_13                (0x02000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */

+#define ADC_PCSEL_PCSEL_14                (0x04000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */

+#define ADC_PCSEL_PCSEL_15                (0x08000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */

+#define ADC_PCSEL_PCSEL_16                (0x10000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */

+#define ADC_PCSEL_PCSEL_17                (0x20000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */

+#define ADC_PCSEL_PCSEL_18                (0x40000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */

+#define ADC_PCSEL_PCSEL_19                (0x80000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00080000 */

+

+/*****************  Bit definition for ADC_LTR1, 2, 3 registers *****************/

+#define ADC_LTR_LT_Pos                    (0U)

+#define ADC_LTR_LT_Msk                    (0x3FFFFFFUL << ADC_LTR_LT_Pos)      /*!< 0x03FFFFFF */

+#define ADC_LTR_LT                        ADC_LTR_LT_Msk                       /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */

+

+/*****************  Bit definition for ADC_HTR1, 2, 3 registers  ****************/

+#define ADC_HTR_HT_Pos                    (0U)

+#define ADC_HTR_HT_Msk                    (0x3FFFFFFUL << ADC_HTR_HT_Pos)      /*!< 0x03FFFFFF */

+#define ADC_HTR_HT                        ADC_HTR_HT_Msk                       /*!< ADC Analog watchdog 1,2 and 3 higher threshold */

+

+

+/********************  Bit definition for ADC_SQR1 register  ********************/

+#define ADC_SQR1_L_Pos                    (0U)

+#define ADC_SQR1_L_Msk                    (0xFUL << ADC_SQR1_L_Pos)            /*!< 0x0000000F */

+#define ADC_SQR1_L                        ADC_SQR1_L_Msk                       /*!< ADC regular channel sequence lenght */

+#define ADC_SQR1_L_0                      (0x1UL << ADC_SQR1_L_Pos)             /*!< 0x00000001 */

+#define ADC_SQR1_L_1                      (0x2UL << ADC_SQR1_L_Pos)             /*!< 0x00000002 */

+#define ADC_SQR1_L_2                      (0x4UL << ADC_SQR1_L_Pos)             /*!< 0x00000004 */

+#define ADC_SQR1_L_3                      (0x8UL << ADC_SQR1_L_Pos)             /*!< 0x00000008 */

+

+#define ADC_SQR1_SQ1_Pos                  (6U)

+#define ADC_SQR1_SQ1_Msk                  (0x1FUL << ADC_SQR1_SQ1_Pos)         /*!< 0x000007C0 */

+#define ADC_SQR1_SQ1                      ADC_SQR1_SQ1_Msk                     /*!< ADC 1st conversion in regular sequence */

+#define ADC_SQR1_SQ1_0                    (0x01UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000040 */

+#define ADC_SQR1_SQ1_1                    (0x02UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000080 */

+#define ADC_SQR1_SQ1_2                    (0x04UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000100 */

+#define ADC_SQR1_SQ1_3                    (0x08UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000200 */

+#define ADC_SQR1_SQ1_4                    (0x10UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000400 */

+

+#define ADC_SQR1_SQ2_Pos                  (12U)

+#define ADC_SQR1_SQ2_Msk                  (0x1FUL << ADC_SQR1_SQ2_Pos)         /*!< 0x0001F000 */

+#define ADC_SQR1_SQ2                      ADC_SQR1_SQ2_Msk                     /*!< ADC 2nd conversion in regular sequence */

+#define ADC_SQR1_SQ2_0                    (0x01UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00001000 */

+#define ADC_SQR1_SQ2_1                    (0x02UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00002000 */

+#define ADC_SQR1_SQ2_2                    (0x04UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00004000 */

+#define ADC_SQR1_SQ2_3                    (0x08UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00008000 */

+#define ADC_SQR1_SQ2_4                    (0x10UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00010000 */

+

+#define ADC_SQR1_SQ3_Pos                  (18U)

+#define ADC_SQR1_SQ3_Msk                  (0x1FUL << ADC_SQR1_SQ3_Pos)         /*!< 0x007C0000 */

+#define ADC_SQR1_SQ3                      ADC_SQR1_SQ3_Msk                     /*!< ADC 3rd conversion in regular sequence */

+#define ADC_SQR1_SQ3_0                    (0x01UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00040000 */

+#define ADC_SQR1_SQ3_1                    (0x02UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00080000 */

+#define ADC_SQR1_SQ3_2                    (0x04UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00100000 */

+#define ADC_SQR1_SQ3_3                    (0x08UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00200000 */

+#define ADC_SQR1_SQ3_4                    (0x10UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00400000 */

+

+#define ADC_SQR1_SQ4_Pos                  (24U)

+#define ADC_SQR1_SQ4_Msk                  (0x1FUL << ADC_SQR1_SQ4_Pos)         /*!< 0x1F000000 */

+#define ADC_SQR1_SQ4                      ADC_SQR1_SQ4_Msk                     /*!< ADC 4th conversion in regular sequence */

+#define ADC_SQR1_SQ4_0                    (0x01UL << ADC_SQR1_SQ4_Pos)          /*!< 0x01000000 */

+#define ADC_SQR1_SQ4_1                    (0x02UL << ADC_SQR1_SQ4_Pos)          /*!< 0x02000000 */

+#define ADC_SQR1_SQ4_2                    (0x04UL << ADC_SQR1_SQ4_Pos)          /*!< 0x04000000 */

+#define ADC_SQR1_SQ4_3                    (0x08UL << ADC_SQR1_SQ4_Pos)          /*!< 0x08000000 */

+#define ADC_SQR1_SQ4_4                    (0x10UL << ADC_SQR1_SQ4_Pos)          /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR2 register  ********************/

+#define ADC_SQR2_SQ5_Pos                  (0U)

+#define ADC_SQR2_SQ5_Msk                  (0x1FUL << ADC_SQR2_SQ5_Pos)         /*!< 0x0000001F */

+#define ADC_SQR2_SQ5                      ADC_SQR2_SQ5_Msk                     /*!< ADC 5th conversion in regular sequence */

+#define ADC_SQR2_SQ5_0                    (0x01UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000001 */

+#define ADC_SQR2_SQ5_1                    (0x02UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000002 */

+#define ADC_SQR2_SQ5_2                    (0x04UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000004 */

+#define ADC_SQR2_SQ5_3                    (0x08UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000008 */

+#define ADC_SQR2_SQ5_4                    (0x10UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000010 */

+

+#define ADC_SQR2_SQ6_Pos                  (6U)

+#define ADC_SQR2_SQ6_Msk                  (0x1FUL << ADC_SQR2_SQ6_Pos)         /*!< 0x000007C0 */

+#define ADC_SQR2_SQ6                      ADC_SQR2_SQ6_Msk                     /*!< ADC 6th conversion in regular sequence */

+#define ADC_SQR2_SQ6_0                    (0x01UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000040 */

+#define ADC_SQR2_SQ6_1                    (0x02UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000080 */

+#define ADC_SQR2_SQ6_2                    (0x04UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000100 */

+#define ADC_SQR2_SQ6_3                    (0x08UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000200 */

+#define ADC_SQR2_SQ6_4                    (0x10UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000400 */

+

+#define ADC_SQR2_SQ7_Pos                  (12U)

+#define ADC_SQR2_SQ7_Msk                  (0x1FUL << ADC_SQR2_SQ7_Pos)         /*!< 0x0001F000 */

+#define ADC_SQR2_SQ7                      ADC_SQR2_SQ7_Msk                     /*!< ADC 7th conversion in regular sequence */

+#define ADC_SQR2_SQ7_0                    (0x01UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00001000 */

+#define ADC_SQR2_SQ7_1                    (0x02UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00002000 */

+#define ADC_SQR2_SQ7_2                    (0x04UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00004000 */

+#define ADC_SQR2_SQ7_3                    (0x08UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00008000 */

+#define ADC_SQR2_SQ7_4                    (0x10UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00010000 */

+

+#define ADC_SQR2_SQ8_Pos                  (18U)

+#define ADC_SQR2_SQ8_Msk                  (0x1FUL << ADC_SQR2_SQ8_Pos)         /*!< 0x007C0000 */

+#define ADC_SQR2_SQ8                      ADC_SQR2_SQ8_Msk                     /*!< ADC 8th conversion in regular sequence */

+#define ADC_SQR2_SQ8_0                    (0x01UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00040000 */

+#define ADC_SQR2_SQ8_1                    (0x02UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00080000 */

+#define ADC_SQR2_SQ8_2                    (0x04UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00100000 */

+#define ADC_SQR2_SQ8_3                    (0x08UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00200000 */

+#define ADC_SQR2_SQ8_4                    (0x10UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00400000 */

+

+#define ADC_SQR2_SQ9_Pos                  (24U)

+#define ADC_SQR2_SQ9_Msk                  (0x1FUL << ADC_SQR2_SQ9_Pos)         /*!< 0x1F000000 */

+#define ADC_SQR2_SQ9                      ADC_SQR2_SQ9_Msk                     /*!< ADC 9th conversion in regular sequence */

+#define ADC_SQR2_SQ9_0                    (0x01UL << ADC_SQR2_SQ9_Pos)          /*!< 0x01000000 */

+#define ADC_SQR2_SQ9_1                    (0x02UL << ADC_SQR2_SQ9_Pos)          /*!< 0x02000000 */

+#define ADC_SQR2_SQ9_2                    (0x04UL << ADC_SQR2_SQ9_Pos)          /*!< 0x04000000 */

+#define ADC_SQR2_SQ9_3                    (0x08UL << ADC_SQR2_SQ9_Pos)          /*!< 0x08000000 */

+#define ADC_SQR2_SQ9_4                    (0x10UL << ADC_SQR2_SQ9_Pos)          /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR3 register  ********************/

+#define ADC_SQR3_SQ10_Pos                 (0U)

+#define ADC_SQR3_SQ10_Msk                 (0x1FUL << ADC_SQR3_SQ10_Pos)        /*!< 0x0000001F */

+#define ADC_SQR3_SQ10                     ADC_SQR3_SQ10_Msk                    /*!< ADC 10th conversion in regular sequence */

+#define ADC_SQR3_SQ10_0                   (0x01UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000001 */

+#define ADC_SQR3_SQ10_1                   (0x02UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000002 */

+#define ADC_SQR3_SQ10_2                   (0x04UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000004 */

+#define ADC_SQR3_SQ10_3                   (0x08UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000008 */

+#define ADC_SQR3_SQ10_4                   (0x10UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000010 */

+

+#define ADC_SQR3_SQ11_Pos                 (6U)

+#define ADC_SQR3_SQ11_Msk                 (0x1FUL << ADC_SQR3_SQ11_Pos)        /*!< 0x000007C0 */

+#define ADC_SQR3_SQ11                     ADC_SQR3_SQ11_Msk                    /*!< ADC 11th conversion in regular sequence */

+#define ADC_SQR3_SQ11_0                   (0x01UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000040 */

+#define ADC_SQR3_SQ11_1                   (0x02UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000080 */

+#define ADC_SQR3_SQ11_2                   (0x04UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000100 */

+#define ADC_SQR3_SQ11_3                   (0x08UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000200 */

+#define ADC_SQR3_SQ11_4                   (0x10UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000400 */

+

+#define ADC_SQR3_SQ12_Pos                 (12U)

+#define ADC_SQR3_SQ12_Msk                 (0x1FUL << ADC_SQR3_SQ12_Pos)        /*!< 0x0001F000 */

+#define ADC_SQR3_SQ12                     ADC_SQR3_SQ12_Msk                    /*!< ADC 12th conversion in regular sequence */

+#define ADC_SQR3_SQ12_0                   (0x01UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00001000 */

+#define ADC_SQR3_SQ12_1                   (0x02UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00002000 */

+#define ADC_SQR3_SQ12_2                   (0x04UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00004000 */

+#define ADC_SQR3_SQ12_3                   (0x08UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00008000 */

+#define ADC_SQR3_SQ12_4                   (0x10UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00010000 */

+

+#define ADC_SQR3_SQ13_Pos                 (18U)

+#define ADC_SQR3_SQ13_Msk                 (0x1FUL << ADC_SQR3_SQ13_Pos)        /*!< 0x007C0000 */

+#define ADC_SQR3_SQ13                     ADC_SQR3_SQ13_Msk                    /*!< ADC 13th conversion in regular sequence */

+#define ADC_SQR3_SQ13_0                   (0x01UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00040000 */

+#define ADC_SQR3_SQ13_1                   (0x02UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00080000 */

+#define ADC_SQR3_SQ13_2                   (0x04UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00100000 */

+#define ADC_SQR3_SQ13_3                   (0x08UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00200000 */

+#define ADC_SQR3_SQ13_4                   (0x10UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00400000 */

+

+#define ADC_SQR3_SQ14_Pos                 (24U)

+#define ADC_SQR3_SQ14_Msk                 (0x1FUL << ADC_SQR3_SQ14_Pos)        /*!< 0x1F000000 */

+#define ADC_SQR3_SQ14                     ADC_SQR3_SQ14_Msk                    /*!< ADC 14th conversion in regular sequence */

+#define ADC_SQR3_SQ14_0                   (0x01UL << ADC_SQR3_SQ14_Pos)         /*!< 0x01000000 */

+#define ADC_SQR3_SQ14_1                   (0x02UL << ADC_SQR3_SQ14_Pos)         /*!< 0x02000000 */

+#define ADC_SQR3_SQ14_2                   (0x04UL << ADC_SQR3_SQ14_Pos)         /*!< 0x04000000 */

+#define ADC_SQR3_SQ14_3                   (0x08UL << ADC_SQR3_SQ14_Pos)         /*!< 0x08000000 */

+#define ADC_SQR3_SQ14_4                   (0x10UL << ADC_SQR3_SQ14_Pos)         /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR4 register  ********************/

+#define ADC_SQR4_SQ15_Pos                 (0U)

+#define ADC_SQR4_SQ15_Msk                 (0x1FUL << ADC_SQR4_SQ15_Pos)        /*!< 0x0000001F */

+#define ADC_SQR4_SQ15                     ADC_SQR4_SQ15_Msk                    /*!< ADC 15th conversion in regular sequence */

+#define ADC_SQR4_SQ15_0                   (0x01UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000001 */

+#define ADC_SQR4_SQ15_1                   (0x02UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000002 */

+#define ADC_SQR4_SQ15_2                   (0x04UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000004 */

+#define ADC_SQR4_SQ15_3                   (0x08UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000008 */

+#define ADC_SQR4_SQ15_4                   (0x10UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000010 */

+

+#define ADC_SQR4_SQ16_Pos                 (6U)

+#define ADC_SQR4_SQ16_Msk                 (0x1FUL << ADC_SQR4_SQ16_Pos)        /*!< 0x000007C0 */

+#define ADC_SQR4_SQ16                     ADC_SQR4_SQ16_Msk                    /*!< ADC 16th conversion in regular sequence */

+#define ADC_SQR4_SQ16_0                   (0x01UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000040 */

+#define ADC_SQR4_SQ16_1                   (0x02UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000080 */

+#define ADC_SQR4_SQ16_2                   (0x04UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000100 */

+#define ADC_SQR4_SQ16_3                   (0x08UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000200 */

+#define ADC_SQR4_SQ16_4                   (0x10UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000400 */

+/********************  Bit definition for ADC_DR register  ********************/

+#define ADC_DR_RDATA_Pos                  (0U)

+#define ADC_DR_RDATA_Msk                  (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)   /*!< 0xFFFFFFFF */

+#define ADC_DR_RDATA                      ADC_DR_RDATA_Msk                     /*!< ADC regular Data converted */

+

+/********************  Bit definition for ADC_JSQR register  ********************/

+#define ADC_JSQR_JL_Pos                   (0U)

+#define ADC_JSQR_JL_Msk                   (0x3UL << ADC_JSQR_JL_Pos)           /*!< 0x00000003 */

+#define ADC_JSQR_JL                       ADC_JSQR_JL_Msk                      /*!< ADC injected channel sequence length */

+#define ADC_JSQR_JL_0                     (0x1UL << ADC_JSQR_JL_Pos)           /*!< 0x00000001 */

+#define ADC_JSQR_JL_1                     (0x2UL << ADC_JSQR_JL_Pos)           /*!< 0x00000002 */

+

+#define ADC_JSQR_JEXTSEL_Pos              (2U)

+#define ADC_JSQR_JEXTSEL_Msk              (0x1FUL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x0000007C */

+#define ADC_JSQR_JEXTSEL                  ADC_JSQR_JEXTSEL_Msk                 /*!< ADC external trigger selection for injected group */

+#define ADC_JSQR_JEXTSEL_0                (0x01UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000004 */

+#define ADC_JSQR_JEXTSEL_1                (0x02UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000008 */

+#define ADC_JSQR_JEXTSEL_2                (0x04UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000010 */

+#define ADC_JSQR_JEXTSEL_3                (0x08UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000020 */

+#define ADC_JSQR_JEXTSEL_4                (0x10UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000040 */

+

+#define ADC_JSQR_JEXTEN_Pos               (7U)

+#define ADC_JSQR_JEXTEN_Msk               (0x3UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000180 */

+#define ADC_JSQR_JEXTEN                   ADC_JSQR_JEXTEN_Msk                  /*!< ADC external trigger enable and polarity selection for injected channels */

+#define ADC_JSQR_JEXTEN_0                 (0x1UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000080 */

+#define ADC_JSQR_JEXTEN_1                 (0x2UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000100 */

+

+#define ADC_JSQR_JSQ1_Pos                 (9U)

+#define ADC_JSQR_JSQ1_Msk                 (0x1FUL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00003E00 */

+#define ADC_JSQR_JSQ1                     ADC_JSQR_JSQ1_Msk                    /*!< ADC 1st conversion in injected sequence */

+#define ADC_JSQR_JSQ1_0                   (0x01UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000200 */

+#define ADC_JSQR_JSQ1_1                   (0x02UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000400 */

+#define ADC_JSQR_JSQ1_2                   (0x04UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000800 */

+#define ADC_JSQR_JSQ1_3                   (0x08UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00001000 */

+#define ADC_JSQR_JSQ1_4                   (0x10UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00002000 */

+

+#define ADC_JSQR_JSQ2_Pos                 (15U)

+#define ADC_JSQR_JSQ2_Msk                 (0x1FUL << ADC_JSQR_JSQ2_Pos)        /*!< 0x000F8000 */

+#define ADC_JSQR_JSQ2                     ADC_JSQR_JSQ2_Msk                    /*!< ADC 2nd conversion in injected sequence */

+#define ADC_JSQR_JSQ2_0                   (0x01UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00008000 */

+#define ADC_JSQR_JSQ2_1                   (0x02UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00010000 */

+#define ADC_JSQR_JSQ2_2                   (0x04UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00020000 */

+#define ADC_JSQR_JSQ2_3                   (0x08UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00040000 */

+#define ADC_JSQR_JSQ2_4                   (0x10UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00080000 */

+

+#define ADC_JSQR_JSQ3_Pos                 (21U)

+#define ADC_JSQR_JSQ3_Msk                 (0x1FUL << ADC_JSQR_JSQ3_Pos)        /*!< 0x03E00000 */

+#define ADC_JSQR_JSQ3                     ADC_JSQR_JSQ3_Msk                    /*!< ADC 3rd conversion in injected sequence */

+#define ADC_JSQR_JSQ3_0                   (0x01UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00200000 */

+#define ADC_JSQR_JSQ3_1                   (0x02UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00400000 */

+#define ADC_JSQR_JSQ3_2                   (0x04UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00800000 */

+#define ADC_JSQR_JSQ3_3                   (0x08UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x01000000 */

+#define ADC_JSQR_JSQ3_4                   (0x10UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x02000000 */

+

+#define ADC_JSQR_JSQ4_Pos                 (27U)

+#define ADC_JSQR_JSQ4_Msk                 (0x1FUL << ADC_JSQR_JSQ4_Pos)        /*!< 0xF8000000 */

+#define ADC_JSQR_JSQ4                     ADC_JSQR_JSQ4_Msk                    /*!< ADC 4th conversion in injected sequence */

+#define ADC_JSQR_JSQ4_0                   (0x01UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x08000000 */

+#define ADC_JSQR_JSQ4_1                   (0x02UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x10000000 */

+#define ADC_JSQR_JSQ4_2                   (0x04UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x20000000 */

+#define ADC_JSQR_JSQ4_3                   (0x08UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x40000000 */

+#define ADC_JSQR_JSQ4_4                   (0x10UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_OFR1 register  ********************/

+#define ADC_OFR1_OFFSET1_Pos              (0U)

+#define ADC_OFR1_OFFSET1_Msk              (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR1_OFFSET1                  ADC_OFR1_OFFSET1_Msk                  /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */

+#define ADC_OFR1_OFFSET1_0                (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */

+#define ADC_OFR1_OFFSET1_1                (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */

+#define ADC_OFR1_OFFSET1_2                (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */

+#define ADC_OFR1_OFFSET1_3                (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */

+#define ADC_OFR1_OFFSET1_4                (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */

+#define ADC_OFR1_OFFSET1_5                (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */

+#define ADC_OFR1_OFFSET1_6                (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */

+#define ADC_OFR1_OFFSET1_7                (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */

+#define ADC_OFR1_OFFSET1_8                (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */

+#define ADC_OFR1_OFFSET1_9                (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */

+#define ADC_OFR1_OFFSET1_10               (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */

+#define ADC_OFR1_OFFSET1_11               (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */

+#define ADC_OFR1_OFFSET1_12               (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */

+#define ADC_OFR1_OFFSET1_13               (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */

+#define ADC_OFR1_OFFSET1_14               (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */

+#define ADC_OFR1_OFFSET1_15               (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */

+#define ADC_OFR1_OFFSET1_16               (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */

+#define ADC_OFR1_OFFSET1_17               (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */

+#define ADC_OFR1_OFFSET1_18               (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */

+#define ADC_OFR1_OFFSET1_19               (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */

+#define ADC_OFR1_OFFSET1_20               (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */

+#define ADC_OFR1_OFFSET1_21               (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */

+#define ADC_OFR1_OFFSET1_22               (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */

+#define ADC_OFR1_OFFSET1_23               (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */

+#define ADC_OFR1_OFFSET1_24               (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */

+#define ADC_OFR1_OFFSET1_25               (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR1_OFFSET1_CH_Pos           (26U)

+#define ADC_OFR1_OFFSET1_CH_Msk           (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR1_OFFSET1_CH               ADC_OFR1_OFFSET1_CH_Msk               /*!< ADC Channel selection for the data offset 1 */

+#define ADC_OFR1_OFFSET1_CH_0             (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR1_OFFSET1_CH_1             (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR1_OFFSET1_CH_2             (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR1_OFFSET1_CH_3             (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR1_OFFSET1_CH_4             (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR1_SSATE_Pos                (31U)

+#define ADC_OFR1_SSATE_Msk                (0x1UL << ADC_OFR1_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR1_SSATE                    ADC_OFR1_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR2 register  ********************/

+#define ADC_OFR2_OFFSET2_Pos              (0U)

+#define ADC_OFR2_OFFSET2_Msk              (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR2_OFFSET2                  ADC_OFR2_OFFSET2_Msk                  /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */

+#define ADC_OFR2_OFFSET2_0                (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */

+#define ADC_OFR2_OFFSET2_1                (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */

+#define ADC_OFR2_OFFSET2_2                (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */

+#define ADC_OFR2_OFFSET2_3                (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */

+#define ADC_OFR2_OFFSET2_4                (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */

+#define ADC_OFR2_OFFSET2_5                (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */

+#define ADC_OFR2_OFFSET2_6                (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */

+#define ADC_OFR2_OFFSET2_7                (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */

+#define ADC_OFR2_OFFSET2_8                (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */

+#define ADC_OFR2_OFFSET2_9                (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */

+#define ADC_OFR2_OFFSET2_10               (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */

+#define ADC_OFR2_OFFSET2_11               (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */

+#define ADC_OFR2_OFFSET2_12               (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */

+#define ADC_OFR2_OFFSET2_13               (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */

+#define ADC_OFR2_OFFSET2_14               (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */

+#define ADC_OFR2_OFFSET2_15               (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */

+#define ADC_OFR2_OFFSET2_16               (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */

+#define ADC_OFR2_OFFSET2_17               (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */

+#define ADC_OFR2_OFFSET2_18               (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */

+#define ADC_OFR2_OFFSET2_19               (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */

+#define ADC_OFR2_OFFSET2_20               (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */

+#define ADC_OFR2_OFFSET2_21               (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */

+#define ADC_OFR2_OFFSET2_22               (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */

+#define ADC_OFR2_OFFSET2_23               (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */

+#define ADC_OFR2_OFFSET2_24               (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */

+#define ADC_OFR2_OFFSET2_25               (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR2_OFFSET2_CH_Pos           (26U)

+#define ADC_OFR2_OFFSET2_CH_Msk           (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR2_OFFSET2_CH               ADC_OFR2_OFFSET2_CH_Msk               /*!< ADC Channel selection for the data offset 2 */

+#define ADC_OFR2_OFFSET2_CH_0             (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR2_OFFSET2_CH_1             (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR2_OFFSET2_CH_2             (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR2_OFFSET2_CH_3             (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR2_OFFSET2_CH_4             (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR2_SSATE_Pos                (31U)

+#define ADC_OFR2_SSATE_Msk                (0x1UL << ADC_OFR2_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR2_SSATE                    ADC_OFR2_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR3 register  ********************/

+#define ADC_OFR3_OFFSET3_Pos              (0U)

+#define ADC_OFR3_OFFSET3_Msk              (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR3_OFFSET3                  ADC_OFR3_OFFSET3_Msk                  /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */

+#define ADC_OFR3_OFFSET3_0                (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */

+#define ADC_OFR3_OFFSET3_1                (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */

+#define ADC_OFR3_OFFSET3_2                (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */

+#define ADC_OFR3_OFFSET3_3                (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */

+#define ADC_OFR3_OFFSET3_4                (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */

+#define ADC_OFR3_OFFSET3_5                (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */

+#define ADC_OFR3_OFFSET3_6                (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */

+#define ADC_OFR3_OFFSET3_7                (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */

+#define ADC_OFR3_OFFSET3_8                (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */

+#define ADC_OFR3_OFFSET3_9                (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */

+#define ADC_OFR3_OFFSET3_10               (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */

+#define ADC_OFR3_OFFSET3_11               (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */

+#define ADC_OFR3_OFFSET3_12               (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */

+#define ADC_OFR3_OFFSET3_13               (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */

+#define ADC_OFR3_OFFSET3_14               (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */

+#define ADC_OFR3_OFFSET3_15               (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */

+#define ADC_OFR3_OFFSET3_16               (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */

+#define ADC_OFR3_OFFSET3_17               (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */

+#define ADC_OFR3_OFFSET3_18               (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */

+#define ADC_OFR3_OFFSET3_19               (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */

+#define ADC_OFR3_OFFSET3_20               (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */

+#define ADC_OFR3_OFFSET3_21               (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */

+#define ADC_OFR3_OFFSET3_22               (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */

+#define ADC_OFR3_OFFSET3_23               (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */

+#define ADC_OFR3_OFFSET3_24               (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */

+#define ADC_OFR3_OFFSET3_25               (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR3_OFFSET3_CH_Pos           (26U)

+#define ADC_OFR3_OFFSET3_CH_Msk           (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR3_OFFSET3_CH               ADC_OFR3_OFFSET3_CH_Msk               /*!< ADC Channel selection for the data offset 3 */

+#define ADC_OFR3_OFFSET3_CH_0             (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR3_OFFSET3_CH_1             (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR3_OFFSET3_CH_2             (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR3_OFFSET3_CH_3             (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR3_OFFSET3_CH_4             (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR3_SSATE_Pos                (31U)

+#define ADC_OFR3_SSATE_Msk                (0x1UL << ADC_OFR3_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR3_SSATE                    ADC_OFR3_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR4 register  ********************/

+#define ADC_OFR4_OFFSET4_Pos              (0U)

+#define ADC_OFR4_OFFSET4_Msk              (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR4_OFFSET4                  ADC_OFR4_OFFSET4_Msk                  /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */

+#define ADC_OFR4_OFFSET4_0                (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */

+#define ADC_OFR4_OFFSET4_1                (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */

+#define ADC_OFR4_OFFSET4_2                (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */

+#define ADC_OFR4_OFFSET4_3                (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */

+#define ADC_OFR4_OFFSET4_4                (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */

+#define ADC_OFR4_OFFSET4_5                (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */

+#define ADC_OFR4_OFFSET4_6                (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */

+#define ADC_OFR4_OFFSET4_7                (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */

+#define ADC_OFR4_OFFSET4_8                (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */

+#define ADC_OFR4_OFFSET4_9                (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */

+#define ADC_OFR4_OFFSET4_10               (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */

+#define ADC_OFR4_OFFSET4_11               (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */

+#define ADC_OFR4_OFFSET4_12               (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */

+#define ADC_OFR4_OFFSET4_13               (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */

+#define ADC_OFR4_OFFSET4_14               (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */

+#define ADC_OFR4_OFFSET4_15               (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */

+#define ADC_OFR4_OFFSET4_16               (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */

+#define ADC_OFR4_OFFSET4_17               (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */

+#define ADC_OFR4_OFFSET4_18               (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */

+#define ADC_OFR4_OFFSET4_19               (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */

+#define ADC_OFR4_OFFSET4_20               (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */

+#define ADC_OFR4_OFFSET4_21               (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */

+#define ADC_OFR4_OFFSET4_22               (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */

+#define ADC_OFR4_OFFSET4_23               (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */

+#define ADC_OFR4_OFFSET4_24               (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */

+#define ADC_OFR4_OFFSET4_25               (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR4_OFFSET4_CH_Pos           (26U)

+#define ADC_OFR4_OFFSET4_CH_Msk           (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR4_OFFSET4_CH               ADC_OFR4_OFFSET4_CH_Msk               /*!< ADC Channel selection for the data offset 4 */

+#define ADC_OFR4_OFFSET4_CH_0             (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR4_OFFSET4_CH_1             (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR4_OFFSET4_CH_2             (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR4_OFFSET4_CH_3             (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR4_OFFSET4_CH_4             (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR4_SSATE_Pos                (31U)

+#define ADC_OFR4_SSATE_Msk                (0x1UL << ADC_OFR4_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR4_SSATE                    ADC_OFR4_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_JDR1 register  ********************/

+#define ADC_JDR1_JDATA_Pos                (0U)

+#define ADC_JDR1_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR1_JDATA                    ADC_JDR1_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR1_JDATA_0                  (0x00000001UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR1_JDATA_1                  (0x00000002UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR1_JDATA_2                  (0x00000004UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR1_JDATA_3                  (0x00000008UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR1_JDATA_4                  (0x00000010UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR1_JDATA_5                  (0x00000020UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR1_JDATA_6                  (0x00000040UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR1_JDATA_7                  (0x00000080UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR1_JDATA_8                  (0x00000100UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR1_JDATA_9                  (0x00000200UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR1_JDATA_10                 (0x00000400UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR1_JDATA_11                 (0x00000800UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR1_JDATA_12                 (0x00001000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR1_JDATA_13                 (0x00002000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR1_JDATA_14                 (0x00004000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR1_JDATA_15                 (0x00008000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR1_JDATA_16                 (0x00010000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR1_JDATA_17                 (0x00020000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR1_JDATA_18                 (0x00040000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR1_JDATA_19                 (0x00080000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR1_JDATA_20                 (0x00100000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR1_JDATA_21                 (0x00200000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR1_JDATA_22                 (0x00400000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR1_JDATA_23                 (0x00800000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR1_JDATA_24                 (0x01000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR1_JDATA_25                 (0x02000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR1_JDATA_26                 (0x04000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR1_JDATA_27                 (0x08000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR1_JDATA_28                 (0x10000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR1_JDATA_29                 (0x20000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR1_JDATA_30                 (0x40000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR1_JDATA_31                 (0x80000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR2 register  ********************/

+#define ADC_JDR2_JDATA_Pos                (0U)

+#define ADC_JDR2_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR2_JDATA                    ADC_JDR2_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR2_JDATA_0                  (0x00000001UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR2_JDATA_1                  (0x00000002UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR2_JDATA_2                  (0x00000004UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR2_JDATA_3                  (0x00000008UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR2_JDATA_4                  (0x00000010UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR2_JDATA_5                  (0x00000020UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR2_JDATA_6                  (0x00000040UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR2_JDATA_7                  (0x00000080UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR2_JDATA_8                  (0x00000100UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR2_JDATA_9                  (0x00000200UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR2_JDATA_10                 (0x00000400UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR2_JDATA_11                 (0x00000800UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR2_JDATA_12                 (0x00001000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR2_JDATA_13                 (0x00002000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR2_JDATA_14                 (0x00004000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR2_JDATA_15                 (0x00008000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR2_JDATA_16                 (0x00010000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR2_JDATA_17                 (0x00020000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR2_JDATA_18                 (0x00040000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR2_JDATA_19                 (0x00080000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR2_JDATA_20                 (0x00100000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR2_JDATA_21                 (0x00200000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR2_JDATA_22                 (0x00400000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR2_JDATA_23                 (0x00800000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR2_JDATA_24                 (0x01000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR2_JDATA_25                 (0x02000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR2_JDATA_26                 (0x04000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR2_JDATA_27                 (0x08000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR2_JDATA_28                 (0x10000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR2_JDATA_29                 (0x20000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR2_JDATA_30                 (0x40000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR2_JDATA_31                 (0x80000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR3 register  ********************/

+#define ADC_JDR3_JDATA_Pos                (0U)

+#define ADC_JDR3_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR3_JDATA                    ADC_JDR3_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR3_JDATA_0                  (0x00000001UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR3_JDATA_1                  (0x00000002UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR3_JDATA_2                  (0x00000004UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR3_JDATA_3                  (0x00000008UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR3_JDATA_4                  (0x00000010UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR3_JDATA_5                  (0x00000020UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR3_JDATA_6                  (0x00000040UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR3_JDATA_7                  (0x00000080UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR3_JDATA_8                  (0x00000100UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR3_JDATA_9                  (0x00000200UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR3_JDATA_10                 (0x00000400UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR3_JDATA_11                 (0x00000800UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR3_JDATA_12                 (0x00001000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR3_JDATA_13                 (0x00002000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR3_JDATA_14                 (0x00004000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR3_JDATA_15                 (0x00008000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR3_JDATA_16                 (0x00010000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR3_JDATA_17                 (0x00020000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR3_JDATA_18                 (0x00040000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR3_JDATA_19                 (0x00080000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR3_JDATA_20                 (0x00100000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR3_JDATA_21                 (0x00200000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR3_JDATA_22                 (0x00400000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR3_JDATA_23                 (0x00800000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR3_JDATA_24                 (0x01000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR3_JDATA_25                 (0x02000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR3_JDATA_26                 (0x04000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR3_JDATA_27                 (0x08000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR3_JDATA_28                 (0x10000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR3_JDATA_29                 (0x20000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR3_JDATA_30                 (0x40000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR3_JDATA_31                 (0x80000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR4 register  ********************/

+#define ADC_JDR4_JDATA_Pos                (0U)

+#define ADC_JDR4_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR4_JDATA                    ADC_JDR4_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR4_JDATA_0                  (0x00000001UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR4_JDATA_1                  (0x00000002UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR4_JDATA_2                  (0x00000004UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR4_JDATA_3                  (0x00000008UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR4_JDATA_4                  (0x00000010UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR4_JDATA_5                  (0x00000020UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR4_JDATA_6                  (0x00000040UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR4_JDATA_7                  (0x00000080UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR4_JDATA_8                  (0x00000100UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR4_JDATA_9                  (0x00000200UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR4_JDATA_10                 (0x00000400UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR4_JDATA_11                 (0x00000800UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR4_JDATA_12                 (0x00001000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR4_JDATA_13                 (0x00002000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR4_JDATA_14                 (0x00004000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR4_JDATA_15                 (0x00008000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR4_JDATA_16                 (0x00010000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR4_JDATA_17                 (0x00020000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR4_JDATA_18                 (0x00040000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR4_JDATA_19                 (0x00080000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR4_JDATA_20                 (0x00100000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR4_JDATA_21                 (0x00200000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR4_JDATA_22                 (0x00400000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR4_JDATA_23                 (0x00800000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR4_JDATA_24                 (0x01000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR4_JDATA_25                 (0x02000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR4_JDATA_26                 (0x04000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR4_JDATA_27                 (0x08000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR4_JDATA_28                 (0x10000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR4_JDATA_29                 (0x20000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR4_JDATA_30                 (0x40000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR4_JDATA_31                 (0x80000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_AWD2CR register  ********************/

+#define ADC_AWD2CR_AWD2CH_Pos             (0U)

+#define ADC_AWD2CR_AWD2CH_Msk             (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x000FFFFF */

+#define ADC_AWD2CR_AWD2CH                 ADC_AWD2CR_AWD2CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */

+#define ADC_AWD2CR_AWD2CH_0               (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000001 */

+#define ADC_AWD2CR_AWD2CH_1               (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000002 */

+#define ADC_AWD2CR_AWD2CH_2               (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000004 */

+#define ADC_AWD2CR_AWD2CH_3               (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000008 */

+#define ADC_AWD2CR_AWD2CH_4               (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000010 */

+#define ADC_AWD2CR_AWD2CH_5               (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000020 */

+#define ADC_AWD2CR_AWD2CH_6               (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000040 */

+#define ADC_AWD2CR_AWD2CH_7               (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000080 */

+#define ADC_AWD2CR_AWD2CH_8               (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000100 */

+#define ADC_AWD2CR_AWD2CH_9               (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000200 */

+#define ADC_AWD2CR_AWD2CH_10              (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000400 */

+#define ADC_AWD2CR_AWD2CH_11              (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000800 */

+#define ADC_AWD2CR_AWD2CH_12              (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00001000 */

+#define ADC_AWD2CR_AWD2CH_13              (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00002000 */

+#define ADC_AWD2CR_AWD2CH_14              (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00004000 */

+#define ADC_AWD2CR_AWD2CH_15              (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00008000 */

+#define ADC_AWD2CR_AWD2CH_16              (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00010000 */

+#define ADC_AWD2CR_AWD2CH_17              (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00020000 */

+#define ADC_AWD2CR_AWD2CH_18              (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */

+#define ADC_AWD2CR_AWD2CH_19              (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_AWD3CR register  ********************/

+#define ADC_AWD3CR_AWD3CH_Pos             (0U)

+#define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x000FFFFF */

+#define ADC_AWD3CR_AWD3CH                 ADC_AWD3CR_AWD3CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */

+#define ADC_AWD3CR_AWD3CH_0               (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000001 */

+#define ADC_AWD3CR_AWD3CH_1               (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000002 */

+#define ADC_AWD3CR_AWD3CH_2               (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000004 */

+#define ADC_AWD3CR_AWD3CH_3               (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000008 */

+#define ADC_AWD3CR_AWD3CH_4               (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000010 */

+#define ADC_AWD3CR_AWD3CH_5               (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000020 */

+#define ADC_AWD3CR_AWD3CH_6               (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000040 */

+#define ADC_AWD3CR_AWD3CH_7               (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000080 */

+#define ADC_AWD3CR_AWD3CH_8               (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000100 */

+#define ADC_AWD3CR_AWD3CH_9               (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000200 */

+#define ADC_AWD3CR_AWD3CH_10              (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000400 */

+#define ADC_AWD3CR_AWD3CH_11              (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000800 */

+#define ADC_AWD3CR_AWD3CH_12              (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00001000 */

+#define ADC_AWD3CR_AWD3CH_13              (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00002000 */

+#define ADC_AWD3CR_AWD3CH_14              (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00004000 */

+#define ADC_AWD3CR_AWD3CH_15              (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00008000 */

+#define ADC_AWD3CR_AWD3CH_16              (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00010000 */

+#define ADC_AWD3CR_AWD3CH_17              (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00020000 */

+#define ADC_AWD3CR_AWD3CH_18              (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */

+#define ADC_AWD3CR_AWD3CH_19              (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_DIFSEL register  ********************/

+#define ADC_DIFSEL_DIFSEL_Pos             (0U)

+#define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */

+#define ADC_DIFSEL_DIFSEL                 ADC_DIFSEL_DIFSEL_Msk                 /*!< ADC differential modes for channels 1 to 18 */

+#define ADC_DIFSEL_DIFSEL_0               (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000001 */

+#define ADC_DIFSEL_DIFSEL_1               (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000002 */

+#define ADC_DIFSEL_DIFSEL_2               (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000004 */

+#define ADC_DIFSEL_DIFSEL_3               (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000008 */

+#define ADC_DIFSEL_DIFSEL_4               (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000010 */

+#define ADC_DIFSEL_DIFSEL_5               (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000020 */

+#define ADC_DIFSEL_DIFSEL_6               (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000040 */

+#define ADC_DIFSEL_DIFSEL_7               (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000080 */

+#define ADC_DIFSEL_DIFSEL_8               (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000100 */

+#define ADC_DIFSEL_DIFSEL_9               (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000200 */

+#define ADC_DIFSEL_DIFSEL_10              (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000400 */

+#define ADC_DIFSEL_DIFSEL_11              (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000800 */

+#define ADC_DIFSEL_DIFSEL_12              (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00001000 */

+#define ADC_DIFSEL_DIFSEL_13              (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00002000 */

+#define ADC_DIFSEL_DIFSEL_14              (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00004000 */

+#define ADC_DIFSEL_DIFSEL_15              (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00008000 */

+#define ADC_DIFSEL_DIFSEL_16              (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00010000 */

+#define ADC_DIFSEL_DIFSEL_17              (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00020000 */

+#define ADC_DIFSEL_DIFSEL_18              (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00040000 */

+#define ADC_DIFSEL_DIFSEL_19              (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_CALFACT register  ********************/

+#define ADC_CALFACT_CALFACT_S_Pos         (0U)

+#define ADC_CALFACT_CALFACT_S_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */

+#define ADC_CALFACT_CALFACT_S             ADC_CALFACT_CALFACT_S_Msk              /*!< ADC calibration factors in single-ended mode */

+#define ADC_CALFACT_CALFACT_S_0           (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */

+#define ADC_CALFACT_CALFACT_S_1           (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */

+#define ADC_CALFACT_CALFACT_S_2           (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */

+#define ADC_CALFACT_CALFACT_S_3           (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */

+#define ADC_CALFACT_CALFACT_S_4           (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */

+#define ADC_CALFACT_CALFACT_S_5           (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */

+#define ADC_CALFACT_CALFACT_S_6           (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */

+#define ADC_CALFACT_CALFACT_S_7           (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */

+#define ADC_CALFACT_CALFACT_S_8           (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */

+#define ADC_CALFACT_CALFACT_S_9           (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */

+#define ADC_CALFACT_CALFACT_S_10          (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */

+#define ADC_CALFACT_CALFACT_D_Pos         (16U)

+#define ADC_CALFACT_CALFACT_D_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */

+#define ADC_CALFACT_CALFACT_D             ADC_CALFACT_CALFACT_D_Msk              /*!< ADC calibration factors in differential mode */

+#define ADC_CALFACT_CALFACT_D_0           (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */

+#define ADC_CALFACT_CALFACT_D_1           (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */

+#define ADC_CALFACT_CALFACT_D_2           (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */

+#define ADC_CALFACT_CALFACT_D_3           (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */

+#define ADC_CALFACT_CALFACT_D_4           (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */

+#define ADC_CALFACT_CALFACT_D_5           (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */

+#define ADC_CALFACT_CALFACT_D_6           (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */

+#define ADC_CALFACT_CALFACT_D_7           (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */

+#define ADC_CALFACT_CALFACT_D_8           (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */

+#define ADC_CALFACT_CALFACT_D_9           (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */

+#define ADC_CALFACT_CALFACT_D_10          (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */

+

+/********************  Bit definition for ADC_CALFACT2 register  ********************/

+#define ADC_CALFACT2_LINCALFACT_Pos       (0U)

+#define ADC_CALFACT2_LINCALFACT_Msk       (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */

+#define ADC_CALFACT2_LINCALFACT           ADC_CALFACT2_LINCALFACT_Msk                   /*!< ADC Linearity calibration factors */

+#define ADC_CALFACT2_LINCALFACT_0         (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */

+#define ADC_CALFACT2_LINCALFACT_1         (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */

+#define ADC_CALFACT2_LINCALFACT_2         (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */

+#define ADC_CALFACT2_LINCALFACT_3         (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */

+#define ADC_CALFACT2_LINCALFACT_4         (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */

+#define ADC_CALFACT2_LINCALFACT_5         (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */

+#define ADC_CALFACT2_LINCALFACT_6         (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */

+#define ADC_CALFACT2_LINCALFACT_7         (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */

+#define ADC_CALFACT2_LINCALFACT_8         (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */

+#define ADC_CALFACT2_LINCALFACT_9         (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */

+#define ADC_CALFACT2_LINCALFACT_10        (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */

+#define ADC_CALFACT2_LINCALFACT_11        (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */

+#define ADC_CALFACT2_LINCALFACT_12        (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */

+#define ADC_CALFACT2_LINCALFACT_13        (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */

+#define ADC_CALFACT2_LINCALFACT_14        (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */

+#define ADC_CALFACT2_LINCALFACT_15        (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */

+#define ADC_CALFACT2_LINCALFACT_16        (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */

+#define ADC_CALFACT2_LINCALFACT_17        (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */

+#define ADC_CALFACT2_LINCALFACT_18        (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */

+#define ADC_CALFACT2_LINCALFACT_19        (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */

+#define ADC_CALFACT2_LINCALFACT_20        (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */

+#define ADC_CALFACT2_LINCALFACT_21        (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */

+#define ADC_CALFACT2_LINCALFACT_22        (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */

+#define ADC_CALFACT2_LINCALFACT_23        (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */

+#define ADC_CALFACT2_LINCALFACT_24        (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */

+#define ADC_CALFACT2_LINCALFACT_25        (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */

+#define ADC_CALFACT2_LINCALFACT_26        (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */

+#define ADC_CALFACT2_LINCALFACT_27        (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */

+#define ADC_CALFACT2_LINCALFACT_28        (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */

+#define ADC_CALFACT2_LINCALFACT_29        (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */

+

+/*************************  ADC Common registers  *****************************/

+/********************  Bit definition for ADC_CSR register  ********************/

+#define ADC_CSR_ADRDY_MST_Pos             (0U)

+#define ADC_CSR_ADRDY_MST_Msk             (0x1UL << ADC_CSR_ADRDY_MST_Pos)     /*!< 0x00000001 */

+#define ADC_CSR_ADRDY_MST                 ADC_CSR_ADRDY_MST_Msk                /*!< Master ADC ready */

+#define ADC_CSR_EOSMP_MST_Pos             (1U)

+#define ADC_CSR_EOSMP_MST_Msk             (0x1UL << ADC_CSR_EOSMP_MST_Pos)     /*!< 0x00000002 */

+#define ADC_CSR_EOSMP_MST                 ADC_CSR_EOSMP_MST_Msk                /*!< End of sampling phase flag of the master ADC */

+#define ADC_CSR_EOC_MST_Pos               (2U)

+#define ADC_CSR_EOC_MST_Msk               (0x1UL << ADC_CSR_EOC_MST_Pos)       /*!< 0x00000004 */

+#define ADC_CSR_EOC_MST                   ADC_CSR_EOC_MST_Msk                  /*!< End of regular conversion of the master ADC */

+#define ADC_CSR_EOS_MST_Pos               (3U)

+#define ADC_CSR_EOS_MST_Msk               (0x1UL << ADC_CSR_EOS_MST_Pos)       /*!< 0x00000008 */

+#define ADC_CSR_EOS_MST                   ADC_CSR_EOS_MST_Msk                  /*!< End of regular sequence flag of the master ADC */

+#define ADC_CSR_OVR_MST_Pos               (4U)

+#define ADC_CSR_OVR_MST_Msk               (0x1UL << ADC_CSR_OVR_MST_Pos)       /*!< 0x00000010 */

+#define ADC_CSR_OVR_MST                   ADC_CSR_OVR_MST_Msk                  /*!< Overrun flag of the master ADC */

+#define ADC_CSR_JEOC_MST_Pos              (5U)

+#define ADC_CSR_JEOC_MST_Msk              (0x1UL << ADC_CSR_JEOC_MST_Pos)      /*!< 0x00000020 */

+#define ADC_CSR_JEOC_MST                  ADC_CSR_JEOC_MST_Msk                 /*!< End of injected conversion of the master ADC */

+#define ADC_CSR_JEOS_MST_Pos              (6U)

+#define ADC_CSR_JEOS_MST_Msk              (0x1UL << ADC_CSR_JEOS_MST_Pos)      /*!< 0x00000040 */

+#define ADC_CSR_JEOS_MST                  ADC_CSR_JEOS_MST_Msk                 /*!< End of injected sequence flag of the master ADC */

+#define ADC_CSR_AWD1_MST_Pos              (7U)

+#define ADC_CSR_AWD1_MST_Msk              (0x1UL << ADC_CSR_AWD1_MST_Pos)      /*!< 0x00000080 */

+#define ADC_CSR_AWD1_MST                  ADC_CSR_AWD1_MST_Msk                 /*!< Analog watchdog 1 flag of the master ADC */

+#define ADC_CSR_AWD2_MST_Pos              (8U)

+#define ADC_CSR_AWD2_MST_Msk              (0x1UL << ADC_CSR_AWD2_MST_Pos)      /*!< 0x00000100 */

+#define ADC_CSR_AWD2_MST                  ADC_CSR_AWD2_MST_Msk                 /*!< Analog watchdog 2 flag of the master ADC */

+#define ADC_CSR_AWD3_MST_Pos              (9U)

+#define ADC_CSR_AWD3_MST_Msk              (0x1UL << ADC_CSR_AWD3_MST_Pos)      /*!< 0x00000200 */

+#define ADC_CSR_AWD3_MST                  ADC_CSR_AWD3_MST_Msk                 /*!< Analog watchdog 3 flag of the master ADC */

+#define ADC_CSR_JQOVF_MST_Pos             (10U)

+#define ADC_CSR_JQOVF_MST_Msk             (0x1UL << ADC_CSR_JQOVF_MST_Pos)     /*!< 0x00000400 */

+#define ADC_CSR_JQOVF_MST                 ADC_CSR_JQOVF_MST_Msk                /*!< Injected context queue overflow flag of the master ADC */

+#define ADC_CSR_ADRDY_SLV_Pos             (16U)

+#define ADC_CSR_ADRDY_SLV_Msk             (0x1UL << ADC_CSR_ADRDY_SLV_Pos)     /*!< 0x00010000 */

+#define ADC_CSR_ADRDY_SLV                 ADC_CSR_ADRDY_SLV_Msk                /*!< Slave ADC ready */

+#define ADC_CSR_EOSMP_SLV_Pos             (17U)

+#define ADC_CSR_EOSMP_SLV_Msk             (0x1UL << ADC_CSR_EOSMP_SLV_Pos)     /*!< 0x00020000 */

+#define ADC_CSR_EOSMP_SLV                 ADC_CSR_EOSMP_SLV_Msk                /*!< End of sampling phase flag of the slave ADC */

+#define ADC_CSR_EOC_SLV_Pos               (18U)

+#define ADC_CSR_EOC_SLV_Msk               (0x1UL << ADC_CSR_EOC_SLV_Pos)       /*!< 0x00040000 */

+#define ADC_CSR_EOC_SLV                   ADC_CSR_EOC_SLV_Msk                  /*!< End of regular conversion of the slave ADC */

+#define ADC_CSR_EOS_SLV_Pos               (19U)

+#define ADC_CSR_EOS_SLV_Msk               (0x1UL << ADC_CSR_EOS_SLV_Pos)       /*!< 0x00080000 */

+#define ADC_CSR_EOS_SLV                   ADC_CSR_EOS_SLV_Msk                  /*!< End of regular sequence flag of the slave ADC */

+#define ADC_CSR_OVR_SLV_Pos               (20U)

+#define ADC_CSR_OVR_SLV_Msk               (0x1UL << ADC_CSR_OVR_SLV_Pos)       /*!< 0x00100000 */

+#define ADC_CSR_OVR_SLV                   ADC_CSR_OVR_SLV_Msk                  /*!< Overrun flag of the slave ADC */

+#define ADC_CSR_JEOC_SLV_Pos              (21U)

+#define ADC_CSR_JEOC_SLV_Msk              (0x1UL << ADC_CSR_JEOC_SLV_Pos)      /*!< 0x00200000 */

+#define ADC_CSR_JEOC_SLV                  ADC_CSR_JEOC_SLV_Msk                 /*!< End of injected conversion of the slave ADC */

+#define ADC_CSR_JEOS_SLV_Pos              (22U)

+#define ADC_CSR_JEOS_SLV_Msk              (0x1UL << ADC_CSR_JEOS_SLV_Pos)      /*!< 0x00400000 */

+#define ADC_CSR_JEOS_SLV                  ADC_CSR_JEOS_SLV_Msk                 /*!< End of injected sequence flag of the slave ADC */

+#define ADC_CSR_AWD1_SLV_Pos              (23U)

+#define ADC_CSR_AWD1_SLV_Msk              (0x1UL << ADC_CSR_AWD1_SLV_Pos)      /*!< 0x00800000 */

+#define ADC_CSR_AWD1_SLV                  ADC_CSR_AWD1_SLV_Msk                 /*!< Analog watchdog 1 flag of the slave ADC */

+#define ADC_CSR_AWD2_SLV_Pos              (24U)

+#define ADC_CSR_AWD2_SLV_Msk              (0x1UL << ADC_CSR_AWD2_SLV_Pos)      /*!< 0x01000000 */

+#define ADC_CSR_AWD2_SLV                  ADC_CSR_AWD2_SLV_Msk                 /*!< Analog watchdog 2 flag of the slave ADC */

+#define ADC_CSR_AWD3_SLV_Pos              (25U)

+#define ADC_CSR_AWD3_SLV_Msk              (0x1UL << ADC_CSR_AWD3_SLV_Pos)      /*!< 0x02000000 */

+#define ADC_CSR_AWD3_SLV                  ADC_CSR_AWD3_SLV_Msk                 /*!< Analog watchdog 3 flag of the slave ADC */

+#define ADC_CSR_JQOVF_SLV_Pos             (26U)

+#define ADC_CSR_JQOVF_SLV_Msk             (0x1UL << ADC_CSR_JQOVF_SLV_Pos)     /*!< 0x04000000 */

+#define ADC_CSR_JQOVF_SLV                 ADC_CSR_JQOVF_SLV_Msk                /*!< Injected context queue overflow flag of the slave ADC */

+

+/********************  Bit definition for ADC_CCR register  ********************/

+#define ADC_CCR_DUAL_Pos                  (0U)

+#define ADC_CCR_DUAL_Msk                  (0x1FUL << ADC_CCR_DUAL_Pos)          /*!< 0x0000001F */

+#define ADC_CCR_DUAL                      ADC_CCR_DUAL_Msk                      /*!< Dual ADC mode selection */

+#define ADC_CCR_DUAL_0                    (0x01UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000001 */

+#define ADC_CCR_DUAL_1                    (0x02UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000002 */

+#define ADC_CCR_DUAL_2                    (0x04UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000004 */

+#define ADC_CCR_DUAL_3                    (0x08UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000008 */

+#define ADC_CCR_DUAL_4                    (0x10UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000010 */

+

+#define ADC_CCR_DELAY_Pos                 (8U)

+#define ADC_CCR_DELAY_Msk                 (0xFUL << ADC_CCR_DELAY_Pos)          /*!< 0x00000F00 */

+#define ADC_CCR_DELAY                     ADC_CCR_DELAY_Msk                     /*!< Delay between 2 sampling phases */

+#define ADC_CCR_DELAY_0                   (0x1UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000100 */

+#define ADC_CCR_DELAY_1                   (0x2UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000200 */

+#define ADC_CCR_DELAY_2                   (0x4UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000400 */

+#define ADC_CCR_DELAY_3                   (0x8UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000800 */

+

+

+#define ADC_CCR_DAMDF_Pos                 (14U)

+#define ADC_CCR_DAMDF_Msk                 (0x3UL << ADC_CCR_DAMDF_Pos)          /*!< 0x0000C000 */

+#define ADC_CCR_DAMDF                     ADC_CCR_DAMDF_Msk                     /*!< Dual ADC mode Data format */

+#define ADC_CCR_DAMDF_0                   (0x1UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00004000 */

+#define ADC_CCR_DAMDF_1                   (0x2UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00008000 */

+

+#define ADC_CCR_CKMODE_Pos                (16U)

+#define ADC_CCR_CKMODE_Msk                (0x3UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00030000 */

+#define ADC_CCR_CKMODE                    ADC_CCR_CKMODE_Msk                    /*!< ADC clock mode */

+#define ADC_CCR_CKMODE_0                  (0x1UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00010000 */

+#define ADC_CCR_CKMODE_1                  (0x2UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00020000 */

+

+#define ADC_CCR_PRESC_Pos                 (18U)

+#define ADC_CCR_PRESC_Msk                 (0xFUL << ADC_CCR_PRESC_Pos)          /*!< 0x003C0000 */

+#define ADC_CCR_PRESC                     ADC_CCR_PRESC_Msk                     /*!< ADC prescaler */

+#define ADC_CCR_PRESC_0                   (0x1UL << ADC_CCR_PRESC_Pos)          /*!< 0x00040000 */

+#define ADC_CCR_PRESC_1                   (0x2UL << ADC_CCR_PRESC_Pos)          /*!< 0x00080000 */

+#define ADC_CCR_PRESC_2                   (0x4UL << ADC_CCR_PRESC_Pos)          /*!< 0x00100000 */

+#define ADC_CCR_PRESC_3                   (0x8UL << ADC_CCR_PRESC_Pos)          /*!< 0x00200000 */

+

+#define ADC_CCR_VREFEN_Pos                (22U)

+#define ADC_CCR_VREFEN_Msk                (0x1UL << ADC_CCR_VREFEN_Pos)         /*!< 0x00400000 */

+#define ADC_CCR_VREFEN                    ADC_CCR_VREFEN_Msk                    /*!< VREFINT enable */

+#define ADC_CCR_TSEN_Pos                  (23U)

+#define ADC_CCR_TSEN_Msk                  (0x1UL << ADC_CCR_TSEN_Pos)           /*!< 0x00800000 */

+#define ADC_CCR_TSEN                      ADC_CCR_TSEN_Msk                      /*!< Temperature sensor enable */

+#define ADC_CCR_VBATEN_Pos                (24U)

+#define ADC_CCR_VBATEN_Msk                (0x1UL << ADC_CCR_VBATEN_Pos)         /*!< 0x01000000 */

+#define ADC_CCR_VBATEN                    ADC_CCR_VBATEN_Msk                    /*!< VBAT enable */

+

+/********************  Bit definition for ADC_CDR register  *******************/

+#define ADC_CDR_RDATA_MST_Pos             (0U)

+#define ADC_CDR_RDATA_MST_Msk             (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)   /*!< 0x0000FFFF */

+#define ADC_CDR_RDATA_MST                 ADC_CDR_RDATA_MST_Msk                 /*!< ADC multimode master group regular conversion data */

+

+#define ADC_CDR_RDATA_SLV_Pos             (16U)

+#define ADC_CDR_RDATA_SLV_Msk             (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)   /*!< 0xFFFF0000 */

+#define ADC_CDR_RDATA_SLV                 ADC_CDR_RDATA_SLV_Msk                 /*!< ADC multimode slave group regular conversion data */

+

+/********************  Bit definition for ADC_CDR2 register  ******************/

+#define ADC_CDR2_RDATA_ALT_Pos            (0U)

+#define ADC_CDR2_RDATA_ALT_Msk            (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */

+#define ADC_CDR2_RDATA_ALT                ADC_CDR2_RDATA_ALT_Msk                   /*!< Regular data of the master/slave alternated ADCs */

+

+/******************************************************************************/

+/*                                                                            */

+/*                        ART accelerator                                     */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for ART_CTR register  ********************/

+#define ART_CTR_EN_Pos              (0U)

+#define ART_CTR_EN_Msk              (0x1UL << ART_CTR_EN_Pos)                /*!< 0x00000001 */

+#define ART_CTR_EN                  ART_CTR_EN_Msk                           /*!< Cache enable*/

+

+#define ART_CTR_PCACHEADDR_Pos      (8U)

+#define ART_CTR_PCACHEADDR_Msk      (0xFFFUL << ART_CTR_PCACHEADDR_Pos)      /*!< 0x000FFF00 */

+#define ART_CTR_PCACHEADDR          ART_CTR_PCACHEADDR_Msk                   /*!< Cacheable page index */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                   VREFBUF                                  */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for VREFBUF_CSR register  ****************/

+#define VREFBUF_CSR_ENVR_Pos        (0U)

+#define VREFBUF_CSR_ENVR_Msk        (0x1UL << VREFBUF_CSR_ENVR_Pos)            /*!< 0x00000001 */

+#define VREFBUF_CSR_ENVR            VREFBUF_CSR_ENVR_Msk                       /*!<Voltage reference buffer enable */

+#define VREFBUF_CSR_HIZ_Pos         (1U)

+#define VREFBUF_CSR_HIZ_Msk         (0x1UL << VREFBUF_CSR_HIZ_Pos)             /*!< 0x00000002 */

+#define VREFBUF_CSR_HIZ             VREFBUF_CSR_HIZ_Msk                        /*!<High impedance mode             */

+#define VREFBUF_CSR_VRR_Pos         (3U)

+#define VREFBUF_CSR_VRR_Msk         (0x1UL << VREFBUF_CSR_VRR_Pos)             /*!< 0x00000008 */

+#define VREFBUF_CSR_VRR             VREFBUF_CSR_VRR_Msk                        /*!<Voltage reference buffer ready  */

+#define VREFBUF_CSR_VRS_Pos         (4U)

+#define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */

+#define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */

+

+#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */

+#define VREFBUF_CSR_VRS_OUT2_Pos    (4U)

+#define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */

+#define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */

+#define VREFBUF_CSR_VRS_OUT3_Pos    (5U)

+#define VREFBUF_CSR_VRS_OUT3_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)        /*!< 0x00000020 */

+#define VREFBUF_CSR_VRS_OUT3        VREFBUF_CSR_VRS_OUT3_Msk                   /*!<Voltage reference VREF_OUT3     */

+#define VREFBUF_CSR_VRS_OUT4_Pos    (4U)

+#define VREFBUF_CSR_VRS_OUT4_Msk    (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)        /*!< 0x00000030 */

+#define VREFBUF_CSR_VRS_OUT4        VREFBUF_CSR_VRS_OUT4_Msk                   /*!<Voltage reference VREF_OUT4     */

+

+/*******************  Bit definition for VREFBUF_CCR register  ****************/

+#define VREFBUF_CCR_TRIM_Pos        (0U)

+#define VREFBUF_CCR_TRIM_Msk        (0x3FUL << VREFBUF_CCR_TRIM_Pos)           /*!< 0x0000003F */

+#define VREFBUF_CCR_TRIM            VREFBUF_CCR_TRIM_Msk                       /*!<TRIM[5:0] bits (Trimming code)  */

+

+/******************************************************************************/

+/*                                                                            */

+/*                 Flexible Datarate Controller Area Network                  */

+/*                                                                            */

+/******************************************************************************/

+/*!<FDCAN control and status registers */

+/*****************  Bit definition for FDCAN_CREL register  *******************/

+#define FDCAN_CREL_DAY_Pos        (0U)

+#define FDCAN_CREL_DAY_Msk        (0xFFUL << FDCAN_CREL_DAY_Pos)               /*!< 0x000000FF */

+#define FDCAN_CREL_DAY            FDCAN_CREL_DAY_Msk                           /*!<Timestamp Day                           */

+#define FDCAN_CREL_MON_Pos        (8U)

+#define FDCAN_CREL_MON_Msk        (0xFFUL << FDCAN_CREL_MON_Pos)               /*!< 0x0000FF00 */

+#define FDCAN_CREL_MON            FDCAN_CREL_MON_Msk                           /*!<Timestamp Month                         */

+#define FDCAN_CREL_YEAR_Pos       (16U)

+#define FDCAN_CREL_YEAR_Msk       (0xFUL << FDCAN_CREL_YEAR_Pos)               /*!< 0x000F0000 */

+#define FDCAN_CREL_YEAR           FDCAN_CREL_YEAR_Msk                          /*!<Timestamp Year                          */

+#define FDCAN_CREL_SUBSTEP_Pos    (20U)

+#define FDCAN_CREL_SUBSTEP_Msk    (0xFUL << FDCAN_CREL_SUBSTEP_Pos)            /*!< 0x00F00000 */

+#define FDCAN_CREL_SUBSTEP        FDCAN_CREL_SUBSTEP_Msk                       /*!<Sub-step of Core release                */

+#define FDCAN_CREL_STEP_Pos       (24U)

+#define FDCAN_CREL_STEP_Msk       (0xFUL << FDCAN_CREL_STEP_Pos)               /*!< 0x0F000000 */

+#define FDCAN_CREL_STEP           FDCAN_CREL_STEP_Msk                          /*!<Step of Core release                    */

+#define FDCAN_CREL_REL_Pos        (28U)

+#define FDCAN_CREL_REL_Msk        (0xFUL << FDCAN_CREL_REL_Pos)                /*!< 0xF0000000 */

+#define FDCAN_CREL_REL            FDCAN_CREL_REL_Msk                           /*!<Core release                            */

+

+/*****************  Bit definition for FDCAN_ENDN register  *******************/

+#define FDCAN_ENDN_ETV_Pos        (0U)

+#define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endiannes Test Value                    */

+

+/*****************  Bit definition for FDCAN_DBTP register  *******************/

+#define FDCAN_DBTP_DSJW_Pos       (0U)

+#define FDCAN_DBTP_DSJW_Msk       (0xFUL << FDCAN_DBTP_DSJW_Pos)               /*!< 0x0000000F */

+#define FDCAN_DBTP_DSJW           FDCAN_DBTP_DSJW_Msk                          /*!<Synchronization Jump Width              */

+#define FDCAN_DBTP_DTSEG2_Pos     (4U)

+#define FDCAN_DBTP_DTSEG2_Msk     (0xFUL << FDCAN_DBTP_DTSEG2_Pos)             /*!< 0x000000F0 */

+#define FDCAN_DBTP_DTSEG2         FDCAN_DBTP_DTSEG2_Msk                        /*!<Data time segment after sample point    */

+#define FDCAN_DBTP_DTSEG1_Pos     (8U)

+#define FDCAN_DBTP_DTSEG1_Msk     (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)            /*!< 0x00001F00 */

+#define FDCAN_DBTP_DTSEG1         FDCAN_DBTP_DTSEG1_Msk                        /*!<Data time segment before sample point   */

+#define FDCAN_DBTP_DBRP_Pos       (16U)

+#define FDCAN_DBTP_DBRP_Msk       (0x1FUL << FDCAN_DBTP_DBRP_Pos)              /*!< 0x001F0000 */

+#define FDCAN_DBTP_DBRP           FDCAN_DBTP_DBRP_Msk                          /*!<Data BIt Rate Prescaler                 */

+#define FDCAN_DBTP_TDC_Pos        (23U)

+#define FDCAN_DBTP_TDC_Msk        (0x1UL << FDCAN_DBTP_TDC_Pos)                /*!< 0x00800000 */

+#define FDCAN_DBTP_TDC            FDCAN_DBTP_TDC_Msk                           /*!<Transceiver Delay Compensation          */

+

+/*****************  Bit definition for FDCAN_TEST register  *******************/

+#define FDCAN_TEST_LBCK_Pos       (4U)

+#define FDCAN_TEST_LBCK_Msk       (0x1UL << FDCAN_TEST_LBCK_Pos)               /*!< 0x00000010 */

+#define FDCAN_TEST_LBCK           FDCAN_TEST_LBCK_Msk                          /*!<Loop Back mode                           */

+#define FDCAN_TEST_TX_Pos         (5U)

+#define FDCAN_TEST_TX_Msk         (0x3UL << FDCAN_TEST_TX_Pos)                 /*!< 0x00000060 */

+#define FDCAN_TEST_TX             FDCAN_TEST_TX_Msk                            /*!<Control of Transmit Pin                  */

+#define FDCAN_TEST_RX_Pos         (7U)

+#define FDCAN_TEST_RX_Msk         (0x1UL << FDCAN_TEST_RX_Pos)                 /*!< 0x00000080 */

+#define FDCAN_TEST_RX             FDCAN_TEST_RX_Msk                            /*!<Receive Pin                              */

+

+/*****************  Bit definition for FDCAN_RWD register  ********************/

+#define FDCAN_RWD_WDC_Pos         (0U)

+#define FDCAN_RWD_WDC_Msk         (0xFFUL << FDCAN_RWD_WDC_Pos)                /*!< 0x000000FF */

+#define FDCAN_RWD_WDC             FDCAN_RWD_WDC_Msk                            /*!<Watchdog configuration                   */

+#define FDCAN_RWD_WDV_Pos         (8U)

+#define FDCAN_RWD_WDV_Msk         (0xFFUL << FDCAN_RWD_WDV_Pos)                /*!< 0x0000FF00 */

+#define FDCAN_RWD_WDV             FDCAN_RWD_WDV_Msk                            /*!<Watchdog value                           */

+

+/*****************  Bit definition for FDCAN_CCCR register  ********************/

+#define FDCAN_CCCR_INIT_Pos       (0U)

+#define FDCAN_CCCR_INIT_Msk       (0x1UL << FDCAN_CCCR_INIT_Pos)               /*!< 0x00000001 */

+#define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!<Initialization                           */

+#define FDCAN_CCCR_CCE_Pos        (1U)

+#define FDCAN_CCCR_CCE_Msk        (0x1UL << FDCAN_CCCR_CCE_Pos)                /*!< 0x00000002 */

+#define FDCAN_CCCR_CCE            FDCAN_CCCR_CCE_Msk                           /*!<Configuration Change Enable              */

+#define FDCAN_CCCR_ASM_Pos        (2U)

+#define FDCAN_CCCR_ASM_Msk        (0x1UL << FDCAN_CCCR_ASM_Pos)                /*!< 0x00000004 */

+#define FDCAN_CCCR_ASM            FDCAN_CCCR_ASM_Msk                           /*!<ASM Restricted Operation Mode            */

+#define FDCAN_CCCR_CSA_Pos        (3U)

+#define FDCAN_CCCR_CSA_Msk        (0x1UL << FDCAN_CCCR_CSA_Pos)                /*!< 0x00000008 */

+#define FDCAN_CCCR_CSA            FDCAN_CCCR_CSA_Msk                           /*!<Clock Stop Acknowledge                   */

+#define FDCAN_CCCR_CSR_Pos        (4U)

+#define FDCAN_CCCR_CSR_Msk        (0x1UL << FDCAN_CCCR_CSR_Pos)                /*!< 0x00000010 */

+#define FDCAN_CCCR_CSR            FDCAN_CCCR_CSR_Msk                           /*!<Clock Stop Request                       */

+#define FDCAN_CCCR_MON_Pos        (5U)

+#define FDCAN_CCCR_MON_Msk        (0x1UL << FDCAN_CCCR_MON_Pos)                /*!< 0x00000020 */

+#define FDCAN_CCCR_MON            FDCAN_CCCR_MON_Msk                           /*!<Bus Monitoring Mode                      */

+#define FDCAN_CCCR_DAR_Pos        (6U)

+#define FDCAN_CCCR_DAR_Msk        (0x1UL << FDCAN_CCCR_DAR_Pos)                /*!< 0x00000040 */

+#define FDCAN_CCCR_DAR            FDCAN_CCCR_DAR_Msk                           /*!<Disable Automatic Retransmission         */

+#define FDCAN_CCCR_TEST_Pos       (7U)

+#define FDCAN_CCCR_TEST_Msk       (0x1UL << FDCAN_CCCR_TEST_Pos)               /*!< 0x00000080 */

+#define FDCAN_CCCR_TEST           FDCAN_CCCR_TEST_Msk                          /*!<Test Mode Enable                         */

+#define FDCAN_CCCR_FDOE_Pos       (8U)

+#define FDCAN_CCCR_FDOE_Msk       (0x1UL << FDCAN_CCCR_FDOE_Pos)               /*!< 0x00000100 */

+#define FDCAN_CCCR_FDOE           FDCAN_CCCR_FDOE_Msk                          /*!<FD Operation Enable                      */

+#define FDCAN_CCCR_BRSE_Pos       (9U)

+#define FDCAN_CCCR_BRSE_Msk       (0x1UL << FDCAN_CCCR_BRSE_Pos)               /*!< 0x00000200 */

+#define FDCAN_CCCR_BRSE           FDCAN_CCCR_BRSE_Msk                          /*!<FDCAN Bit Rate Switching                 */

+#define FDCAN_CCCR_PXHD_Pos       (12U)

+#define FDCAN_CCCR_PXHD_Msk       (0x1UL << FDCAN_CCCR_PXHD_Pos)               /*!< 0x00001000 */

+#define FDCAN_CCCR_PXHD           FDCAN_CCCR_PXHD_Msk                          /*!<Protocol Exception Handling Disable      */

+#define FDCAN_CCCR_EFBI_Pos       (13U)

+#define FDCAN_CCCR_EFBI_Msk       (0x1UL << FDCAN_CCCR_EFBI_Pos)               /*!< 0x00002000 */

+#define FDCAN_CCCR_EFBI           FDCAN_CCCR_EFBI_Msk                          /*!<Edge Filtering during Bus Integration    */

+#define FDCAN_CCCR_TXP_Pos        (14U)

+#define FDCAN_CCCR_TXP_Msk        (0x1UL << FDCAN_CCCR_TXP_Pos)                /*!< 0x00004000 */

+#define FDCAN_CCCR_TXP            FDCAN_CCCR_TXP_Msk                           /*!<Two CAN bit times Pause                  */

+#define FDCAN_CCCR_NISO_Pos       (15U)

+#define FDCAN_CCCR_NISO_Msk       (0x1UL << FDCAN_CCCR_NISO_Pos)               /*!< 0x00008000 */

+#define FDCAN_CCCR_NISO           FDCAN_CCCR_NISO_Msk                          /*!<Non ISO Operation                        */

+

+/*****************  Bit definition for FDCAN_NBTP register  ********************/

+#define FDCAN_NBTP_NTSEG2_Pos     (0U)

+#define FDCAN_NBTP_NTSEG2_Msk     (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)            /*!< 0x0000007F */

+#define FDCAN_NBTP_NTSEG2         FDCAN_NBTP_NTSEG2_Msk                        /*!<Nominal Time segment after sample point  */

+#define FDCAN_NBTP_NTSEG1_Pos     (8U)

+#define FDCAN_NBTP_NTSEG1_Msk     (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)            /*!< 0x0000FF00 */

+#define FDCAN_NBTP_NTSEG1         FDCAN_NBTP_NTSEG1_Msk                        /*!<Nominal Time segment before sample point */

+#define FDCAN_NBTP_NBRP_Pos       (16U)

+#define FDCAN_NBTP_NBRP_Msk       (0x1FFUL << FDCAN_NBTP_NBRP_Pos)             /*!< 0x01FF0000 */

+#define FDCAN_NBTP_NBRP           FDCAN_NBTP_NBRP_Msk                          /*!<Bit Rate Prescaler                       */

+#define FDCAN_NBTP_NSJW_Pos       (25U)

+#define FDCAN_NBTP_NSJW_Msk       (0x7FUL << FDCAN_NBTP_NSJW_Pos)              /*!< 0xFE000000 */

+#define FDCAN_NBTP_NSJW           FDCAN_NBTP_NSJW_Msk                          /*!<Nominal (Re)Synchronization Jump Width   */

+

+/*****************  Bit definition for FDCAN_TSCC register  ********************/

+#define FDCAN_TSCC_TSS_Pos        (0U)

+#define FDCAN_TSCC_TSS_Msk        (0x3UL << FDCAN_TSCC_TSS_Pos)                /*!< 0x00000003 */

+#define FDCAN_TSCC_TSS            FDCAN_TSCC_TSS_Msk                           /*!<Timestamp Select                         */

+#define FDCAN_TSCC_TCP_Pos        (16U)

+#define FDCAN_TSCC_TCP_Msk        (0xFUL << FDCAN_TSCC_TCP_Pos)                /*!< 0x000F0000 */

+#define FDCAN_TSCC_TCP            FDCAN_TSCC_TCP_Msk                           /*!<Timestamp Counter Prescaler              */

+

+/*****************  Bit definition for FDCAN_TSCV register  ********************/

+#define FDCAN_TSCV_TSC_Pos        (0U)

+#define FDCAN_TSCV_TSC_Msk        (0xFFFFUL << FDCAN_TSCV_TSC_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TSCV_TSC            FDCAN_TSCV_TSC_Msk                           /*!<Timestamp Counter                        */

+

+/*****************  Bit definition for FDCAN_TOCC register  ********************/

+#define FDCAN_TOCC_ETOC_Pos       (0U)

+#define FDCAN_TOCC_ETOC_Msk       (0x1UL << FDCAN_TOCC_ETOC_Pos)               /*!< 0x00000001 */

+#define FDCAN_TOCC_ETOC           FDCAN_TOCC_ETOC_Msk                          /*!<Enable Timeout Counter                   */

+#define FDCAN_TOCC_TOS_Pos        (1U)

+#define FDCAN_TOCC_TOS_Msk        (0x3UL << FDCAN_TOCC_TOS_Pos)                /*!< 0x00000006 */

+#define FDCAN_TOCC_TOS            FDCAN_TOCC_TOS_Msk                           /*!<Timeout Select                           */

+#define FDCAN_TOCC_TOP_Pos        (16U)

+#define FDCAN_TOCC_TOP_Msk        (0xFFFFUL << FDCAN_TOCC_TOP_Pos)             /*!< 0xFFFF0000 */

+#define FDCAN_TOCC_TOP            FDCAN_TOCC_TOP_Msk                           /*!<Timeout Period                           */

+

+/*****************  Bit definition for FDCAN_TOCV register  ********************/

+#define FDCAN_TOCV_TOC_Pos        (0U)

+#define FDCAN_TOCV_TOC_Msk        (0xFFFFUL << FDCAN_TOCV_TOC_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TOCV_TOC            FDCAN_TOCV_TOC_Msk                           /*!<Timeout Counter                          */

+

+/*****************  Bit definition for FDCAN_ECR register  *********************/

+#define FDCAN_ECR_TEC_Pos         (0U)

+#define FDCAN_ECR_TEC_Msk         (0xFUL << FDCAN_ECR_TEC_Pos)                 /*!< 0x0000000F */

+#define FDCAN_ECR_TEC             FDCAN_ECR_TEC_Msk                            /*!<Transmit Error Counter                   */

+#define FDCAN_ECR_REC_Pos         (8U)

+#define FDCAN_ECR_REC_Msk         (0x7FUL << FDCAN_ECR_REC_Pos)                /*!< 0x00007F00 */

+#define FDCAN_ECR_REC             FDCAN_ECR_REC_Msk                            /*!<Receive Error Counter                    */

+#define FDCAN_ECR_RP_Pos          (15U)

+#define FDCAN_ECR_RP_Msk          (0x1UL << FDCAN_ECR_RP_Pos)                  /*!< 0x00008000 */

+#define FDCAN_ECR_RP              FDCAN_ECR_RP_Msk                             /*!<Receive Error Passive                    */

+#define FDCAN_ECR_CEL_Pos         (16U)

+#define FDCAN_ECR_CEL_Msk         (0xFFUL << FDCAN_ECR_CEL_Pos)                /*!< 0x00FF0000 */

+#define FDCAN_ECR_CEL             FDCAN_ECR_CEL_Msk                            /*!<CAN Error Logging                        */

+

+/*****************  Bit definition for FDCAN_PSR register  *********************/

+#define FDCAN_PSR_LEC_Pos         (0U)

+#define FDCAN_PSR_LEC_Msk         (0x7UL << FDCAN_PSR_LEC_Pos)                 /*!< 0x00000007 */

+#define FDCAN_PSR_LEC             FDCAN_PSR_LEC_Msk                            /*!<Last Error Code                          */

+#define FDCAN_PSR_ACT_Pos         (3U)

+#define FDCAN_PSR_ACT_Msk         (0x3UL << FDCAN_PSR_ACT_Pos)                 /*!< 0x00000018 */

+#define FDCAN_PSR_ACT             FDCAN_PSR_ACT_Msk                            /*!<Activity                                 */

+#define FDCAN_PSR_EP_Pos          (5U)

+#define FDCAN_PSR_EP_Msk          (0x1UL << FDCAN_PSR_EP_Pos)                  /*!< 0x00000020 */

+#define FDCAN_PSR_EP              FDCAN_PSR_EP_Msk                             /*!<Error Passive                            */

+#define FDCAN_PSR_EW_Pos          (6U)

+#define FDCAN_PSR_EW_Msk          (0x1UL << FDCAN_PSR_EW_Pos)                  /*!< 0x00000040 */

+#define FDCAN_PSR_EW              FDCAN_PSR_EW_Msk                             /*!<Warning Status                           */

+#define FDCAN_PSR_BO_Pos          (7U)

+#define FDCAN_PSR_BO_Msk          (0x1UL << FDCAN_PSR_BO_Pos)                  /*!< 0x00000080 */

+#define FDCAN_PSR_BO              FDCAN_PSR_BO_Msk                             /*!<Bus_Off Status                           */

+#define FDCAN_PSR_DLEC_Pos        (8U)

+#define FDCAN_PSR_DLEC_Msk        (0x7UL << FDCAN_PSR_DLEC_Pos)                /*!< 0x00000700 */

+#define FDCAN_PSR_DLEC            FDCAN_PSR_DLEC_Msk                           /*!<Data Last Error Code                     */

+#define FDCAN_PSR_RESI_Pos        (11U)

+#define FDCAN_PSR_RESI_Msk        (0x1UL << FDCAN_PSR_RESI_Pos)                /*!< 0x00000800 */

+#define FDCAN_PSR_RESI            FDCAN_PSR_RESI_Msk                           /*!<ESI flag of last received FDCAN Message  */

+#define FDCAN_PSR_RBRS_Pos        (12U)

+#define FDCAN_PSR_RBRS_Msk        (0x1UL << FDCAN_PSR_RBRS_Pos)                /*!< 0x00001000 */

+#define FDCAN_PSR_RBRS            FDCAN_PSR_RBRS_Msk                           /*!<BRS flag of last received FDCAN Message  */

+#define FDCAN_PSR_REDL_Pos        (13U)

+#define FDCAN_PSR_REDL_Msk        (0x1UL << FDCAN_PSR_REDL_Pos)                /*!< 0x00002000 */

+#define FDCAN_PSR_REDL            FDCAN_PSR_REDL_Msk                           /*!<Received FDCAN Message                   */

+#define FDCAN_PSR_PXE_Pos         (14U)

+#define FDCAN_PSR_PXE_Msk         (0x1UL << FDCAN_PSR_PXE_Pos)                 /*!< 0x00004000 */

+#define FDCAN_PSR_PXE             FDCAN_PSR_PXE_Msk                            /*!<Protocol Exception Event                 */

+#define FDCAN_PSR_TDCV_Pos        (16U)

+#define FDCAN_PSR_TDCV_Msk        (0x7FUL << FDCAN_PSR_TDCV_Pos)               /*!< 0x007F0000 */

+#define FDCAN_PSR_TDCV            FDCAN_PSR_TDCV_Msk                           /*!<Transmitter Delay Compensation Value     */

+

+/*****************  Bit definition for FDCAN_TDCR register  ********************/

+#define FDCAN_TDCR_TDCF_Pos       (0U)

+#define FDCAN_TDCR_TDCF_Msk       (0x7FUL << FDCAN_TDCR_TDCF_Pos)              /*!< 0x0000007F */

+#define FDCAN_TDCR_TDCF           FDCAN_TDCR_TDCF_Msk                          /*!<Transmitter Delay Compensation Filter    */

+#define FDCAN_TDCR_TDCO_Pos       (8U)

+#define FDCAN_TDCR_TDCO_Msk       (0x7FUL << FDCAN_TDCR_TDCO_Pos)              /*!< 0x00007F00 */

+#define FDCAN_TDCR_TDCO           FDCAN_TDCR_TDCO_Msk                          /*!<Transmitter Delay Compensation Offset    */

+

+/*****************  Bit definition for FDCAN_IR register  **********************/

+#define FDCAN_IR_RF0N_Pos         (0U)

+#define FDCAN_IR_RF0N_Msk         (0x1UL << FDCAN_IR_RF0N_Pos)                 /*!< 0x00000001 */

+#define FDCAN_IR_RF0N             FDCAN_IR_RF0N_Msk                            /*!<Rx FIFO 0 New Message                    */

+#define FDCAN_IR_RF0W_Pos         (1U)

+#define FDCAN_IR_RF0W_Msk         (0x1UL << FDCAN_IR_RF0W_Pos)                 /*!< 0x00000002 */

+#define FDCAN_IR_RF0W             FDCAN_IR_RF0W_Msk                            /*!<Rx FIFO 0 Watermark Reached              */

+#define FDCAN_IR_RF0F_Pos         (2U)

+#define FDCAN_IR_RF0F_Msk         (0x1UL << FDCAN_IR_RF0F_Pos)                 /*!< 0x00000004 */

+#define FDCAN_IR_RF0F             FDCAN_IR_RF0F_Msk                            /*!<Rx FIFO 0 Full                           */

+#define FDCAN_IR_RF0L_Pos         (3U)

+#define FDCAN_IR_RF0L_Msk         (0x1UL << FDCAN_IR_RF0L_Pos)                 /*!< 0x00000008 */

+#define FDCAN_IR_RF0L             FDCAN_IR_RF0L_Msk                            /*!<Rx FIFO 0 Message Lost                   */

+#define FDCAN_IR_RF1N_Pos         (4U)

+#define FDCAN_IR_RF1N_Msk         (0x1UL << FDCAN_IR_RF1N_Pos)                 /*!< 0x00000010 */

+#define FDCAN_IR_RF1N             FDCAN_IR_RF1N_Msk                            /*!<Rx FIFO 1 New Message                    */

+#define FDCAN_IR_RF1W_Pos         (5U)

+#define FDCAN_IR_RF1W_Msk         (0x1UL << FDCAN_IR_RF1W_Pos)                 /*!< 0x00000020 */

+#define FDCAN_IR_RF1W             FDCAN_IR_RF1W_Msk                            /*!<Rx FIFO 1 Watermark Reached              */

+#define FDCAN_IR_RF1F_Pos         (6U)

+#define FDCAN_IR_RF1F_Msk         (0x1UL << FDCAN_IR_RF1F_Pos)                 /*!< 0x00000040 */

+#define FDCAN_IR_RF1F             FDCAN_IR_RF1F_Msk                            /*!<Rx FIFO 1 Full                           */

+#define FDCAN_IR_RF1L_Pos         (7U)

+#define FDCAN_IR_RF1L_Msk         (0x1UL << FDCAN_IR_RF1L_Pos)                 /*!< 0x00000080 */

+#define FDCAN_IR_RF1L             FDCAN_IR_RF1L_Msk                            /*!<Rx FIFO 1 Message Lost                   */

+#define FDCAN_IR_HPM_Pos          (8U)

+#define FDCAN_IR_HPM_Msk          (0x1UL << FDCAN_IR_HPM_Pos)                  /*!< 0x00000100 */

+#define FDCAN_IR_HPM              FDCAN_IR_HPM_Msk                             /*!<High Priority Message                    */

+#define FDCAN_IR_TC_Pos           (9U)

+#define FDCAN_IR_TC_Msk           (0x1UL << FDCAN_IR_TC_Pos)                   /*!< 0x00000200 */

+#define FDCAN_IR_TC               FDCAN_IR_TC_Msk                              /*!<Transmission Completed                   */

+#define FDCAN_IR_TCF_Pos          (10U)

+#define FDCAN_IR_TCF_Msk          (0x1UL << FDCAN_IR_TCF_Pos)                  /*!< 0x00000400 */

+#define FDCAN_IR_TCF              FDCAN_IR_TCF_Msk                             /*!<Transmission Cancellation Finished       */

+#define FDCAN_IR_TFE_Pos          (11U)

+#define FDCAN_IR_TFE_Msk          (0x1UL << FDCAN_IR_TFE_Pos)                  /*!< 0x00000800 */

+#define FDCAN_IR_TFE              FDCAN_IR_TFE_Msk                             /*!<Tx FIFO Empty                            */

+#define FDCAN_IR_TEFN_Pos         (12U)

+#define FDCAN_IR_TEFN_Msk         (0x1UL << FDCAN_IR_TEFN_Pos)                 /*!< 0x00001000 */

+#define FDCAN_IR_TEFN             FDCAN_IR_TEFN_Msk                            /*!<Tx Event FIFO New Entry                  */

+#define FDCAN_IR_TEFW_Pos         (13U)

+#define FDCAN_IR_TEFW_Msk         (0x1UL << FDCAN_IR_TEFW_Pos)                 /*!< 0x00002000 */

+#define FDCAN_IR_TEFW             FDCAN_IR_TEFW_Msk                            /*!<Tx Event FIFO Watermark Reached          */

+#define FDCAN_IR_TEFF_Pos         (14U)

+#define FDCAN_IR_TEFF_Msk         (0x1UL << FDCAN_IR_TEFF_Pos)                 /*!< 0x00004000 */

+#define FDCAN_IR_TEFF             FDCAN_IR_TEFF_Msk                            /*!<Tx Event FIFO Full                       */

+#define FDCAN_IR_TEFL_Pos         (15U)

+#define FDCAN_IR_TEFL_Msk         (0x1UL << FDCAN_IR_TEFL_Pos)                 /*!< 0x00008000 */

+#define FDCAN_IR_TEFL             FDCAN_IR_TEFL_Msk                            /*!<Tx Event FIFO Element Lost               */

+#define FDCAN_IR_TSW_Pos          (16U)

+#define FDCAN_IR_TSW_Msk          (0x1UL << FDCAN_IR_TSW_Pos)                  /*!< 0x00010000 */

+#define FDCAN_IR_TSW              FDCAN_IR_TSW_Msk                             /*!<Timestamp Wraparound                     */

+#define FDCAN_IR_MRAF_Pos         (17U)

+#define FDCAN_IR_MRAF_Msk         (0x1UL << FDCAN_IR_MRAF_Pos)                 /*!< 0x00020000 */

+#define FDCAN_IR_MRAF             FDCAN_IR_MRAF_Msk                            /*!<Message RAM Access Failure               */

+#define FDCAN_IR_TOO_Pos          (18U)

+#define FDCAN_IR_TOO_Msk          (0x1UL << FDCAN_IR_TOO_Pos)                  /*!< 0x00040000 */

+#define FDCAN_IR_TOO              FDCAN_IR_TOO_Msk                             /*!<Timeout Occurred                         */

+#define FDCAN_IR_DRX_Pos          (19U)

+#define FDCAN_IR_DRX_Msk          (0x1UL << FDCAN_IR_DRX_Pos)                  /*!< 0x00080000 */

+#define FDCAN_IR_DRX              FDCAN_IR_DRX_Msk                             /*!<Message stored to Dedicated Rx Buffer    */

+#define FDCAN_IR_ELO_Pos          (22U)

+#define FDCAN_IR_ELO_Msk          (0x1UL << FDCAN_IR_ELO_Pos)                  /*!< 0x00400000 */

+#define FDCAN_IR_ELO              FDCAN_IR_ELO_Msk                             /*!<Error Logging Overflow                   */

+#define FDCAN_IR_EP_Pos           (23U)

+#define FDCAN_IR_EP_Msk           (0x1UL << FDCAN_IR_EP_Pos)                   /*!< 0x00800000 */

+#define FDCAN_IR_EP               FDCAN_IR_EP_Msk                              /*!<Error Passive                            */

+#define FDCAN_IR_EW_Pos           (24U)

+#define FDCAN_IR_EW_Msk           (0x1UL << FDCAN_IR_EW_Pos)                   /*!< 0x01000000 */

+#define FDCAN_IR_EW               FDCAN_IR_EW_Msk                              /*!<Warning Status                           */

+#define FDCAN_IR_BO_Pos           (25U)

+#define FDCAN_IR_BO_Msk           (0x1UL << FDCAN_IR_BO_Pos)                   /*!< 0x02000000 */

+#define FDCAN_IR_BO               FDCAN_IR_BO_Msk                              /*!<Bus_Off Status                           */

+#define FDCAN_IR_WDI_Pos          (26U)

+#define FDCAN_IR_WDI_Msk          (0x1UL << FDCAN_IR_WDI_Pos)                  /*!< 0x04000000 */

+#define FDCAN_IR_WDI              FDCAN_IR_WDI_Msk                             /*!<Watchdog Interrupt                       */

+#define FDCAN_IR_PEA_Pos          (27U)

+#define FDCAN_IR_PEA_Msk          (0x1UL << FDCAN_IR_PEA_Pos)                  /*!< 0x08000000 */

+#define FDCAN_IR_PEA              FDCAN_IR_PEA_Msk                             /*!<Protocol Error in Arbitration Phase      */

+#define FDCAN_IR_PED_Pos          (28U)

+#define FDCAN_IR_PED_Msk          (0x1UL << FDCAN_IR_PED_Pos)                  /*!< 0x10000000 */

+#define FDCAN_IR_PED              FDCAN_IR_PED_Msk                             /*!<Protocol Error in Data Phase             */

+#define FDCAN_IR_ARA_Pos          (29U)

+#define FDCAN_IR_ARA_Msk          (0x1UL << FDCAN_IR_ARA_Pos)                  /*!< 0x20000000 */

+#define FDCAN_IR_ARA              FDCAN_IR_ARA_Msk                             /*!<Access to Reserved Address               */

+

+/*****************  Bit definition for FDCAN_IE register  **********************/

+#define FDCAN_IE_RF0NE_Pos        (0U)

+#define FDCAN_IE_RF0NE_Msk        (0x1UL << FDCAN_IE_RF0NE_Pos)                /*!< 0x00000001 */

+#define FDCAN_IE_RF0NE            FDCAN_IE_RF0NE_Msk                           /*!<Rx FIFO 0 New Message Enable                 */

+#define FDCAN_IE_RF0WE_Pos        (1U)

+#define FDCAN_IE_RF0WE_Msk        (0x1UL << FDCAN_IE_RF0WE_Pos)                /*!< 0x00000002 */

+#define FDCAN_IE_RF0WE            FDCAN_IE_RF0WE_Msk                           /*!<Rx FIFO 0 Watermark Reached Enable           */

+#define FDCAN_IE_RF0FE_Pos        (2U)

+#define FDCAN_IE_RF0FE_Msk        (0x1UL << FDCAN_IE_RF0FE_Pos)                /*!< 0x00000004 */

+#define FDCAN_IE_RF0FE            FDCAN_IE_RF0FE_Msk                           /*!<Rx FIFO 0 Full Enable                        */

+#define FDCAN_IE_RF0LE_Pos        (3U)

+#define FDCAN_IE_RF0LE_Msk        (0x1UL << FDCAN_IE_RF0LE_Pos)                /*!< 0x00000008 */

+#define FDCAN_IE_RF0LE            FDCAN_IE_RF0LE_Msk                           /*!<Rx FIFO 0 Message Lost Enable                */

+#define FDCAN_IE_RF1NE_Pos        (4U)

+#define FDCAN_IE_RF1NE_Msk        (0x1UL << FDCAN_IE_RF1NE_Pos)                /*!< 0x00000010 */

+#define FDCAN_IE_RF1NE            FDCAN_IE_RF1NE_Msk                           /*!<Rx FIFO 1 New Message Enable                 */

+#define FDCAN_IE_RF1WE_Pos        (5U)

+#define FDCAN_IE_RF1WE_Msk        (0x1UL << FDCAN_IE_RF1WE_Pos)                /*!< 0x00000020 */

+#define FDCAN_IE_RF1WE            FDCAN_IE_RF1WE_Msk                           /*!<Rx FIFO 1 Watermark Reached Enable           */

+#define FDCAN_IE_RF1FE_Pos        (6U)

+#define FDCAN_IE_RF1FE_Msk        (0x1UL << FDCAN_IE_RF1FE_Pos)                /*!< 0x00000040 */

+#define FDCAN_IE_RF1FE            FDCAN_IE_RF1FE_Msk                           /*!<Rx FIFO 1 Full Enable                        */

+#define FDCAN_IE_RF1LE_Pos        (7U)

+#define FDCAN_IE_RF1LE_Msk        (0x1UL << FDCAN_IE_RF1LE_Pos)                /*!< 0x00000080 */

+#define FDCAN_IE_RF1LE            FDCAN_IE_RF1LE_Msk                           /*!<Rx FIFO 1 Message Lost Enable                */

+#define FDCAN_IE_HPME_Pos         (8U)

+#define FDCAN_IE_HPME_Msk         (0x1UL << FDCAN_IE_HPME_Pos)                 /*!< 0x00000100 */

+#define FDCAN_IE_HPME             FDCAN_IE_HPME_Msk                            /*!<High Priority Message Enable                 */

+#define FDCAN_IE_TCE_Pos          (9U)

+#define FDCAN_IE_TCE_Msk          (0x1UL << FDCAN_IE_TCE_Pos)                  /*!< 0x00000200 */

+#define FDCAN_IE_TCE              FDCAN_IE_TCE_Msk                             /*!<Transmission Completed Enable                */

+#define FDCAN_IE_TCFE_Pos         (10U)

+#define FDCAN_IE_TCFE_Msk         (0x1UL << FDCAN_IE_TCFE_Pos)                 /*!< 0x00000400 */

+#define FDCAN_IE_TCFE             FDCAN_IE_TCFE_Msk                            /*!<Transmission Cancellation Finished Enable    */

+#define FDCAN_IE_TFEE_Pos         (11U)

+#define FDCAN_IE_TFEE_Msk         (0x1UL << FDCAN_IE_TFEE_Pos)                 /*!< 0x00000800 */

+#define FDCAN_IE_TFEE             FDCAN_IE_TFEE_Msk                            /*!<Tx FIFO Empty Enable                         */

+#define FDCAN_IE_TEFNE_Pos        (12U)

+#define FDCAN_IE_TEFNE_Msk        (0x1UL << FDCAN_IE_TEFNE_Pos)                /*!< 0x00001000 */

+#define FDCAN_IE_TEFNE            FDCAN_IE_TEFNE_Msk                           /*!<Tx Event FIFO New Entry Enable               */

+#define FDCAN_IE_TEFWE_Pos        (13U)

+#define FDCAN_IE_TEFWE_Msk        (0x1UL << FDCAN_IE_TEFWE_Pos)                /*!< 0x00002000 */

+#define FDCAN_IE_TEFWE            FDCAN_IE_TEFWE_Msk                           /*!<Tx Event FIFO Watermark Reached Enable       */

+#define FDCAN_IE_TEFFE_Pos        (14U)

+#define FDCAN_IE_TEFFE_Msk        (0x1UL << FDCAN_IE_TEFFE_Pos)                /*!< 0x00004000 */

+#define FDCAN_IE_TEFFE            FDCAN_IE_TEFFE_Msk                           /*!<Tx Event FIFO Full Enable                    */

+#define FDCAN_IE_TEFLE_Pos        (15U)

+#define FDCAN_IE_TEFLE_Msk        (0x1UL << FDCAN_IE_TEFLE_Pos)                /*!< 0x00008000 */

+#define FDCAN_IE_TEFLE            FDCAN_IE_TEFLE_Msk                           /*!<Tx Event FIFO Element Lost Enable            */

+#define FDCAN_IE_TSWE_Pos         (16U)

+#define FDCAN_IE_TSWE_Msk         (0x1UL << FDCAN_IE_TSWE_Pos)                 /*!< 0x00010000 */

+#define FDCAN_IE_TSWE             FDCAN_IE_TSWE_Msk                            /*!<Timestamp Wraparound Enable                  */

+#define FDCAN_IE_MRAFE_Pos        (17U)

+#define FDCAN_IE_MRAFE_Msk        (0x1UL << FDCAN_IE_MRAFE_Pos)                /*!< 0x00020000 */

+#define FDCAN_IE_MRAFE            FDCAN_IE_MRAFE_Msk                           /*!<Message RAM Access Failure Enable            */

+#define FDCAN_IE_TOOE_Pos         (18U)

+#define FDCAN_IE_TOOE_Msk         (0x1UL << FDCAN_IE_TOOE_Pos)                 /*!< 0x00040000 */

+#define FDCAN_IE_TOOE             FDCAN_IE_TOOE_Msk                            /*!<Timeout Occurred Enable                      */

+#define FDCAN_IE_DRXE_Pos         (19U)

+#define FDCAN_IE_DRXE_Msk         (0x1UL << FDCAN_IE_DRXE_Pos)                 /*!< 0x00080000 */

+#define FDCAN_IE_DRXE             FDCAN_IE_DRXE_Msk                            /*!<Message stored to Dedicated Rx Buffer Enable */

+#define FDCAN_IE_BECE_Pos         (20U)

+#define FDCAN_IE_BECE_Msk         (0x1UL << FDCAN_IE_BECE_Pos)                 /*!< 0x00100000 */

+#define FDCAN_IE_BECE             FDCAN_IE_BECE_Msk                            /*!<Bit Error Corrected Interrupt Enable         */

+#define FDCAN_IE_BEUE_Pos         (21U)

+#define FDCAN_IE_BEUE_Msk         (0x1UL << FDCAN_IE_BEUE_Pos)                 /*!< 0x00200000 */

+#define FDCAN_IE_BEUE             FDCAN_IE_BEUE_Msk                            /*!<Bit Error Uncorrected Interrupt Enable       */

+#define FDCAN_IE_ELOE_Pos         (22U)

+#define FDCAN_IE_ELOE_Msk         (0x1UL << FDCAN_IE_ELOE_Pos)                 /*!< 0x00400000 */

+#define FDCAN_IE_ELOE             FDCAN_IE_ELOE_Msk                            /*!<Error Logging Overflow Enable                */

+#define FDCAN_IE_EPE_Pos          (23U)

+#define FDCAN_IE_EPE_Msk          (0x1UL << FDCAN_IE_EPE_Pos)                  /*!< 0x00800000 */

+#define FDCAN_IE_EPE              FDCAN_IE_EPE_Msk                             /*!<Error Passive Enable                         */

+#define FDCAN_IE_EWE_Pos          (24U)

+#define FDCAN_IE_EWE_Msk          (0x1UL << FDCAN_IE_EWE_Pos)                  /*!< 0x01000000 */

+#define FDCAN_IE_EWE              FDCAN_IE_EWE_Msk                             /*!<Warning Status Enable                        */

+#define FDCAN_IE_BOE_Pos          (25U)

+#define FDCAN_IE_BOE_Msk          (0x1UL << FDCAN_IE_BOE_Pos)                  /*!< 0x02000000 */

+#define FDCAN_IE_BOE              FDCAN_IE_BOE_Msk                             /*!<Bus_Off Status Enable                        */

+#define FDCAN_IE_WDIE_Pos         (26U)

+#define FDCAN_IE_WDIE_Msk         (0x1UL << FDCAN_IE_WDIE_Pos)                 /*!< 0x04000000 */

+#define FDCAN_IE_WDIE             FDCAN_IE_WDIE_Msk                            /*!<Watchdog Interrupt Enable                    */

+#define FDCAN_IE_PEAE_Pos         (27U)

+#define FDCAN_IE_PEAE_Msk         (0x1UL << FDCAN_IE_PEAE_Pos)                 /*!< 0x08000000 */

+#define FDCAN_IE_PEAE             FDCAN_IE_PEAE_Msk                            /*!<Protocol Error in Arbitration Phase Enable   */

+#define FDCAN_IE_PEDE_Pos         (28U)

+#define FDCAN_IE_PEDE_Msk         (0x1UL << FDCAN_IE_PEDE_Pos)                 /*!< 0x10000000 */

+#define FDCAN_IE_PEDE             FDCAN_IE_PEDE_Msk                            /*!<Protocol Error in Data Phase Enable          */

+#define FDCAN_IE_ARAE_Pos         (29U)

+#define FDCAN_IE_ARAE_Msk         (0x1UL << FDCAN_IE_ARAE_Pos)                 /*!< 0x20000000 */

+#define FDCAN_IE_ARAE             FDCAN_IE_ARAE_Msk                            /*!<Access to Reserved Address Enable            */

+

+/*****************  Bit definition for FDCAN_ILS register  **********************/

+#define FDCAN_ILS_RF0NL_Pos       (0U)

+#define FDCAN_ILS_RF0NL_Msk       (0x1UL << FDCAN_ILS_RF0NL_Pos)               /*!< 0x00000001 */

+#define FDCAN_ILS_RF0NL           FDCAN_ILS_RF0NL_Msk                          /*!<Rx FIFO 0 New Message Line                  */

+#define FDCAN_ILS_RF0WL_Pos       (1U)

+#define FDCAN_ILS_RF0WL_Msk       (0x1UL << FDCAN_ILS_RF0WL_Pos)               /*!< 0x00000002 */

+#define FDCAN_ILS_RF0WL           FDCAN_ILS_RF0WL_Msk                          /*!<Rx FIFO 0 Watermark Reached Line            */

+#define FDCAN_ILS_RF0FL_Pos       (2U)

+#define FDCAN_ILS_RF0FL_Msk       (0x1UL << FDCAN_ILS_RF0FL_Pos)               /*!< 0x00000004 */

+#define FDCAN_ILS_RF0FL           FDCAN_ILS_RF0FL_Msk                          /*!<Rx FIFO 0 Full Line                         */

+#define FDCAN_ILS_RF0LL_Pos       (3U)

+#define FDCAN_ILS_RF0LL_Msk       (0x1UL << FDCAN_ILS_RF0LL_Pos)               /*!< 0x00000008 */

+#define FDCAN_ILS_RF0LL           FDCAN_ILS_RF0LL_Msk                          /*!<Rx FIFO 0 Message Lost Line                 */

+#define FDCAN_ILS_RF1NL_Pos       (4U)

+#define FDCAN_ILS_RF1NL_Msk       (0x1UL << FDCAN_ILS_RF1NL_Pos)               /*!< 0x00000010 */

+#define FDCAN_ILS_RF1NL           FDCAN_ILS_RF1NL_Msk                          /*!<Rx FIFO 1 New Message Line                  */

+#define FDCAN_ILS_RF1WL_Pos       (5U)

+#define FDCAN_ILS_RF1WL_Msk       (0x1UL << FDCAN_ILS_RF1WL_Pos)               /*!< 0x00000020 */

+#define FDCAN_ILS_RF1WL           FDCAN_ILS_RF1WL_Msk                          /*!<Rx FIFO 1 Watermark Reached Line            */

+#define FDCAN_ILS_RF1FL_Pos       (6U)

+#define FDCAN_ILS_RF1FL_Msk       (0x1UL << FDCAN_ILS_RF1FL_Pos)               /*!< 0x00000040 */

+#define FDCAN_ILS_RF1FL           FDCAN_ILS_RF1FL_Msk                          /*!<Rx FIFO 1 Full Line                         */

+#define FDCAN_ILS_RF1LL_Pos       (7U)

+#define FDCAN_ILS_RF1LL_Msk       (0x1UL << FDCAN_ILS_RF1LL_Pos)               /*!< 0x00000080 */

+#define FDCAN_ILS_RF1LL           FDCAN_ILS_RF1LL_Msk                          /*!<Rx FIFO 1 Message Lost Line                 */

+#define FDCAN_ILS_HPML_Pos        (8U)

+#define FDCAN_ILS_HPML_Msk        (0x1UL << FDCAN_ILS_HPML_Pos)                /*!< 0x00000100 */

+#define FDCAN_ILS_HPML            FDCAN_ILS_HPML_Msk                           /*!<High Priority Message Line                  */

+#define FDCAN_ILS_TCL_Pos         (9U)

+#define FDCAN_ILS_TCL_Msk         (0x1UL << FDCAN_ILS_TCL_Pos)                 /*!< 0x00000200 */

+#define FDCAN_ILS_TCL             FDCAN_ILS_TCL_Msk                            /*!<Transmission Completed Line                 */

+#define FDCAN_ILS_TCFL_Pos        (10U)

+#define FDCAN_ILS_TCFL_Msk        (0x1UL << FDCAN_ILS_TCFL_Pos)                /*!< 0x00000400 */

+#define FDCAN_ILS_TCFL            FDCAN_ILS_TCFL_Msk                           /*!<Transmission Cancellation Finished Line     */

+#define FDCAN_ILS_TFEL_Pos        (11U)

+#define FDCAN_ILS_TFEL_Msk        (0x1UL << FDCAN_ILS_TFEL_Pos)                /*!< 0x00000800 */

+#define FDCAN_ILS_TFEL            FDCAN_ILS_TFEL_Msk                           /*!<Tx FIFO Empty Line                          */

+#define FDCAN_ILS_TEFNL_Pos       (12U)

+#define FDCAN_ILS_TEFNL_Msk       (0x1UL << FDCAN_ILS_TEFNL_Pos)               /*!< 0x00001000 */

+#define FDCAN_ILS_TEFNL           FDCAN_ILS_TEFNL_Msk                          /*!<Tx Event FIFO New Entry Line                */

+#define FDCAN_ILS_TEFWL_Pos       (13U)

+#define FDCAN_ILS_TEFWL_Msk       (0x1UL << FDCAN_ILS_TEFWL_Pos)               /*!< 0x00002000 */

+#define FDCAN_ILS_TEFWL           FDCAN_ILS_TEFWL_Msk                          /*!<Tx Event FIFO Watermark Reached Line        */

+#define FDCAN_ILS_TEFFL_Pos       (14U)

+#define FDCAN_ILS_TEFFL_Msk       (0x1UL << FDCAN_ILS_TEFFL_Pos)               /*!< 0x00004000 */

+#define FDCAN_ILS_TEFFL           FDCAN_ILS_TEFFL_Msk                          /*!<Tx Event FIFO Full Line                     */

+#define FDCAN_ILS_TEFLL_Pos       (15U)

+#define FDCAN_ILS_TEFLL_Msk       (0x1UL << FDCAN_ILS_TEFLL_Pos)               /*!< 0x00008000 */

+#define FDCAN_ILS_TEFLL           FDCAN_ILS_TEFLL_Msk                          /*!<Tx Event FIFO Element Lost Line             */

+#define FDCAN_ILS_TSWL_Pos        (16U)

+#define FDCAN_ILS_TSWL_Msk        (0x1UL << FDCAN_ILS_TSWL_Pos)                /*!< 0x00010000 */

+#define FDCAN_ILS_TSWL            FDCAN_ILS_TSWL_Msk                           /*!<Timestamp Wraparound Line                   */

+#define FDCAN_ILS_MRAFE_Pos       (17U)

+#define FDCAN_ILS_MRAFE_Msk       (0x1UL << FDCAN_ILS_MRAFE_Pos)               /*!< 0x00020000 */

+#define FDCAN_ILS_MRAFE           FDCAN_ILS_MRAFE_Msk                          /*!<Message RAM Access Failure Line             */

+#define FDCAN_ILS_TOOE_Pos        (18U)

+#define FDCAN_ILS_TOOE_Msk        (0x1UL << FDCAN_ILS_TOOE_Pos)                /*!< 0x00040000 */

+#define FDCAN_ILS_TOOE            FDCAN_ILS_TOOE_Msk                           /*!<Timeout Occurred Line                       */

+#define FDCAN_ILS_DRXE_Pos        (19U)

+#define FDCAN_ILS_DRXE_Msk        (0x1UL << FDCAN_ILS_DRXE_Pos)                /*!< 0x00080000 */

+#define FDCAN_ILS_DRXE            FDCAN_ILS_DRXE_Msk                           /*!<Message stored to Dedicated Rx Buffer Line  */

+#define FDCAN_ILS_BECE_Pos        (20U)

+#define FDCAN_ILS_BECE_Msk        (0x1UL << FDCAN_ILS_BECE_Pos)                /*!< 0x00100000 */

+#define FDCAN_ILS_BECE            FDCAN_ILS_BECE_Msk                           /*!<Bit Error Corrected Interrupt Line          */

+#define FDCAN_ILS_BEUE_Pos        (21U)

+#define FDCAN_ILS_BEUE_Msk        (0x1UL << FDCAN_ILS_BEUE_Pos)                /*!< 0x00200000 */

+#define FDCAN_ILS_BEUE            FDCAN_ILS_BEUE_Msk                           /*!<Bit Error Uncorrected Interrupt Line        */

+#define FDCAN_ILS_ELOE_Pos        (22U)

+#define FDCAN_ILS_ELOE_Msk        (0x1UL << FDCAN_ILS_ELOE_Pos)                /*!< 0x00400000 */

+#define FDCAN_ILS_ELOE            FDCAN_ILS_ELOE_Msk                           /*!<Error Logging Overflow Line                 */

+#define FDCAN_ILS_EPE_Pos         (23U)

+#define FDCAN_ILS_EPE_Msk         (0x1UL << FDCAN_ILS_EPE_Pos)                 /*!< 0x00800000 */

+#define FDCAN_ILS_EPE             FDCAN_ILS_EPE_Msk                            /*!<Error Passive Line                          */

+#define FDCAN_ILS_EWE_Pos         (24U)

+#define FDCAN_ILS_EWE_Msk         (0x1UL << FDCAN_ILS_EWE_Pos)                 /*!< 0x01000000 */

+#define FDCAN_ILS_EWE             FDCAN_ILS_EWE_Msk                            /*!<Warning Status Line                         */

+#define FDCAN_ILS_BOE_Pos         (25U)

+#define FDCAN_ILS_BOE_Msk         (0x1UL << FDCAN_ILS_BOE_Pos)                 /*!< 0x02000000 */

+#define FDCAN_ILS_BOE             FDCAN_ILS_BOE_Msk                            /*!<Bus_Off Status Line                         */

+#define FDCAN_ILS_WDIE_Pos        (26U)

+#define FDCAN_ILS_WDIE_Msk        (0x1UL << FDCAN_ILS_WDIE_Pos)                /*!< 0x04000000 */

+#define FDCAN_ILS_WDIE            FDCAN_ILS_WDIE_Msk                           /*!<Watchdog Interrupt Line                     */

+#define FDCAN_ILS_PEAE_Pos        (27U)

+#define FDCAN_ILS_PEAE_Msk        (0x1UL << FDCAN_ILS_PEAE_Pos)                /*!< 0x08000000 */

+#define FDCAN_ILS_PEAE            FDCAN_ILS_PEAE_Msk                           /*!<Protocol Error in Arbitration Phase Line    */

+#define FDCAN_ILS_PEDE_Pos        (28U)

+#define FDCAN_ILS_PEDE_Msk        (0x1UL << FDCAN_ILS_PEDE_Pos)                /*!< 0x10000000 */

+#define FDCAN_ILS_PEDE            FDCAN_ILS_PEDE_Msk                           /*!<Protocol Error in Data Phase Line           */

+#define FDCAN_ILS_ARAE_Pos        (29U)

+#define FDCAN_ILS_ARAE_Msk        (0x1UL << FDCAN_ILS_ARAE_Pos)                /*!< 0x20000000 */

+#define FDCAN_ILS_ARAE            FDCAN_ILS_ARAE_Msk                           /*!<Access to Reserved Address Line             */

+

+/*****************  Bit definition for FDCAN_ILE register  **********************/

+#define FDCAN_ILE_EINT0_Pos       (0U)

+#define FDCAN_ILE_EINT0_Msk       (0x1UL << FDCAN_ILE_EINT0_Pos)               /*!< 0x00000001 */

+#define FDCAN_ILE_EINT0           FDCAN_ILE_EINT0_Msk                          /*!<Enable Interrupt Line 0                   */

+#define FDCAN_ILE_EINT1_Pos       (1U)

+#define FDCAN_ILE_EINT1_Msk       (0x1UL << FDCAN_ILE_EINT1_Pos)               /*!< 0x00000002 */

+#define FDCAN_ILE_EINT1           FDCAN_ILE_EINT1_Msk                          /*!<Enable Interrupt Line 1                   */

+

+/*****************  Bit definition for FDCAN_GFC register  **********************/

+#define FDCAN_GFC_RRFE_Pos        (0U)

+#define FDCAN_GFC_RRFE_Msk        (0x1UL << FDCAN_GFC_RRFE_Pos)                /*!< 0x00000001 */

+#define FDCAN_GFC_RRFE            FDCAN_GFC_RRFE_Msk                           /*!<Reject Remote Frames Extended             */

+#define FDCAN_GFC_RRFS_Pos        (1U)

+#define FDCAN_GFC_RRFS_Msk        (0x1UL << FDCAN_GFC_RRFS_Pos)                /*!< 0x00000002 */

+#define FDCAN_GFC_RRFS            FDCAN_GFC_RRFS_Msk                           /*!<Reject Remote Frames Standard             */

+#define FDCAN_GFC_ANFE_Pos        (2U)

+#define FDCAN_GFC_ANFE_Msk        (0x3UL << FDCAN_GFC_ANFE_Pos)                /*!< 0x0000000C */

+#define FDCAN_GFC_ANFE            FDCAN_GFC_ANFE_Msk                           /*!<Accept Non-matching Frames Extended       */

+#define FDCAN_GFC_ANFS_Pos        (4U)

+#define FDCAN_GFC_ANFS_Msk        (0x3UL << FDCAN_GFC_ANFS_Pos)                /*!< 0x00000030 */

+#define FDCAN_GFC_ANFS            FDCAN_GFC_ANFS_Msk                           /*!<Accept Non-matching Frames Standard       */

+

+/*****************  Bit definition for FDCAN_SIDFC register  ********************/

+#define FDCAN_SIDFC_FLSSA_Pos     (2U)

+#define FDCAN_SIDFC_FLSSA_Msk     (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)          /*!< 0x0000FFFC */

+#define FDCAN_SIDFC_FLSSA         FDCAN_SIDFC_FLSSA_Msk                        /*!<Filter List Standard Start Address        */

+#define FDCAN_SIDFC_LSS_Pos       (16U)

+#define FDCAN_SIDFC_LSS_Msk       (0xFFUL << FDCAN_SIDFC_LSS_Pos)              /*!< 0x00FF0000 */

+#define FDCAN_SIDFC_LSS           FDCAN_SIDFC_LSS_Msk                          /*!<List Size Standard                        */

+

+/*****************  Bit definition for FDCAN_XIDFC register  ********************/

+#define FDCAN_XIDFC_FLESA_Pos     (2U)

+#define FDCAN_XIDFC_FLESA_Msk     (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)          /*!< 0x0000FFFC */

+#define FDCAN_XIDFC_FLESA         FDCAN_XIDFC_FLESA_Msk                        /*!<Filter List Standard Start Address        */

+#define FDCAN_XIDFC_LSE_Pos       (16U)

+#define FDCAN_XIDFC_LSE_Msk       (0x7FUL << FDCAN_XIDFC_LSE_Pos)              /*!< 0x007F0000 */

+#define FDCAN_XIDFC_LSE           FDCAN_XIDFC_LSE_Msk                          /*!<List Size Extended                        */

+

+/*****************  Bit definition for FDCAN_XIDAM register  ********************/

+#define FDCAN_XIDAM_EIDM_Pos      (0U)

+#define FDCAN_XIDAM_EIDM_Msk      (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)       /*!< 0x1FFFFFFF */

+#define FDCAN_XIDAM_EIDM          FDCAN_XIDAM_EIDM_Msk                         /*!<Extended ID Mask                          */

+

+/*****************  Bit definition for FDCAN_HPMS register  *********************/

+#define FDCAN_HPMS_BIDX_Pos       (0U)

+#define FDCAN_HPMS_BIDX_Msk       (0x3FUL << FDCAN_HPMS_BIDX_Pos)              /*!< 0x0000003F */

+#define FDCAN_HPMS_BIDX           FDCAN_HPMS_BIDX_Msk                          /*!<Buffer Index                              */

+#define FDCAN_HPMS_MSI_Pos        (6U)

+#define FDCAN_HPMS_MSI_Msk        (0x3UL << FDCAN_HPMS_MSI_Pos)                /*!< 0x000000C0 */

+#define FDCAN_HPMS_MSI            FDCAN_HPMS_MSI_Msk                           /*!<Message Storage Indicator                 */

+#define FDCAN_HPMS_FIDX_Pos       (8U)

+#define FDCAN_HPMS_FIDX_Msk       (0x7FUL << FDCAN_HPMS_FIDX_Pos)              /*!< 0x00007F00 */

+#define FDCAN_HPMS_FIDX           FDCAN_HPMS_FIDX_Msk                          /*!<Filter Index                              */

+#define FDCAN_HPMS_FLST_Pos       (15U)

+#define FDCAN_HPMS_FLST_Msk       (0x1UL << FDCAN_HPMS_FLST_Pos)               /*!< 0x00008000 */

+#define FDCAN_HPMS_FLST           FDCAN_HPMS_FLST_Msk                          /*!<Filter List                               */

+

+/*****************  Bit definition for FDCAN_NDAT1 register  ********************/

+#define FDCAN_NDAT1_ND0_Pos       (0U)

+#define FDCAN_NDAT1_ND0_Msk       (0x1UL << FDCAN_NDAT1_ND0_Pos)               /*!< 0x00000001 */

+#define FDCAN_NDAT1_ND0           FDCAN_NDAT1_ND0_Msk                          /*!<New Data flag of Rx Buffer 0              */

+#define FDCAN_NDAT1_ND1_Pos       (1U)

+#define FDCAN_NDAT1_ND1_Msk       (0x1UL << FDCAN_NDAT1_ND1_Pos)               /*!< 0x00000002 */

+#define FDCAN_NDAT1_ND1           FDCAN_NDAT1_ND1_Msk                          /*!<New Data flag of Rx Buffer 1              */

+#define FDCAN_NDAT1_ND2_Pos       (2U)

+#define FDCAN_NDAT1_ND2_Msk       (0x1UL << FDCAN_NDAT1_ND2_Pos)               /*!< 0x00000004 */

+#define FDCAN_NDAT1_ND2           FDCAN_NDAT1_ND2_Msk                          /*!<New Data flag of Rx Buffer 2              */

+#define FDCAN_NDAT1_ND3_Pos       (3U)

+#define FDCAN_NDAT1_ND3_Msk       (0x1UL << FDCAN_NDAT1_ND3_Pos)               /*!< 0x00000008 */

+#define FDCAN_NDAT1_ND3           FDCAN_NDAT1_ND3_Msk                          /*!<New Data flag of Rx Buffer 3              */

+#define FDCAN_NDAT1_ND4_Pos       (4U)

+#define FDCAN_NDAT1_ND4_Msk       (0x1UL << FDCAN_NDAT1_ND4_Pos)               /*!< 0x00000010 */

+#define FDCAN_NDAT1_ND4           FDCAN_NDAT1_ND4_Msk                          /*!<New Data flag of Rx Buffer 4              */

+#define FDCAN_NDAT1_ND5_Pos       (5U)

+#define FDCAN_NDAT1_ND5_Msk       (0x1UL << FDCAN_NDAT1_ND5_Pos)               /*!< 0x00000020 */

+#define FDCAN_NDAT1_ND5           FDCAN_NDAT1_ND5_Msk                          /*!<New Data flag of Rx Buffer 5              */

+#define FDCAN_NDAT1_ND6_Pos       (6U)

+#define FDCAN_NDAT1_ND6_Msk       (0x1UL << FDCAN_NDAT1_ND6_Pos)               /*!< 0x00000040 */

+#define FDCAN_NDAT1_ND6           FDCAN_NDAT1_ND6_Msk                          /*!<New Data flag of Rx Buffer 6              */

+#define FDCAN_NDAT1_ND7_Pos       (7U)

+#define FDCAN_NDAT1_ND7_Msk       (0x1UL << FDCAN_NDAT1_ND7_Pos)               /*!< 0x00000080 */

+#define FDCAN_NDAT1_ND7           FDCAN_NDAT1_ND7_Msk                          /*!<New Data flag of Rx Buffer 7              */

+#define FDCAN_NDAT1_ND8_Pos       (8U)

+#define FDCAN_NDAT1_ND8_Msk       (0x1UL << FDCAN_NDAT1_ND8_Pos)               /*!< 0x00000100 */

+#define FDCAN_NDAT1_ND8           FDCAN_NDAT1_ND8_Msk                          /*!<New Data flag of Rx Buffer 8              */

+#define FDCAN_NDAT1_ND9_Pos       (9U)

+#define FDCAN_NDAT1_ND9_Msk       (0x1UL << FDCAN_NDAT1_ND9_Pos)               /*!< 0x00000200 */

+#define FDCAN_NDAT1_ND9           FDCAN_NDAT1_ND9_Msk                          /*!<New Data flag of Rx Buffer 9              */

+#define FDCAN_NDAT1_ND10_Pos      (10U)

+#define FDCAN_NDAT1_ND10_Msk      (0x1UL << FDCAN_NDAT1_ND10_Pos)              /*!< 0x00000400 */

+#define FDCAN_NDAT1_ND10          FDCAN_NDAT1_ND10_Msk                         /*!<New Data flag of Rx Buffer 10             */

+#define FDCAN_NDAT1_ND11_Pos      (11U)

+#define FDCAN_NDAT1_ND11_Msk      (0x1UL << FDCAN_NDAT1_ND11_Pos)              /*!< 0x00000800 */

+#define FDCAN_NDAT1_ND11          FDCAN_NDAT1_ND11_Msk                         /*!<New Data flag of Rx Buffer 11             */

+#define FDCAN_NDAT1_ND12_Pos      (12U)

+#define FDCAN_NDAT1_ND12_Msk      (0x1UL << FDCAN_NDAT1_ND12_Pos)              /*!< 0x00001000 */

+#define FDCAN_NDAT1_ND12          FDCAN_NDAT1_ND12_Msk                         /*!<New Data flag of Rx Buffer 12             */

+#define FDCAN_NDAT1_ND13_Pos      (13U)

+#define FDCAN_NDAT1_ND13_Msk      (0x1UL << FDCAN_NDAT1_ND13_Pos)              /*!< 0x00002000 */

+#define FDCAN_NDAT1_ND13          FDCAN_NDAT1_ND13_Msk                         /*!<New Data flag of Rx Buffer 13             */

+#define FDCAN_NDAT1_ND14_Pos      (14U)

+#define FDCAN_NDAT1_ND14_Msk      (0x1UL << FDCAN_NDAT1_ND14_Pos)              /*!< 0x00004000 */

+#define FDCAN_NDAT1_ND14          FDCAN_NDAT1_ND14_Msk                         /*!<New Data flag of Rx Buffer 14             */

+#define FDCAN_NDAT1_ND15_Pos      (15U)

+#define FDCAN_NDAT1_ND15_Msk      (0x1UL << FDCAN_NDAT1_ND15_Pos)              /*!< 0x00008000 */

+#define FDCAN_NDAT1_ND15          FDCAN_NDAT1_ND15_Msk                         /*!<New Data flag of Rx Buffer 15             */

+#define FDCAN_NDAT1_ND16_Pos      (16U)

+#define FDCAN_NDAT1_ND16_Msk      (0x1UL << FDCAN_NDAT1_ND16_Pos)              /*!< 0x00010000 */

+#define FDCAN_NDAT1_ND16          FDCAN_NDAT1_ND16_Msk                         /*!<New Data flag of Rx Buffer 16             */

+#define FDCAN_NDAT1_ND17_Pos      (17U)

+#define FDCAN_NDAT1_ND17_Msk      (0x1UL << FDCAN_NDAT1_ND17_Pos)              /*!< 0x00020000 */

+#define FDCAN_NDAT1_ND17          FDCAN_NDAT1_ND17_Msk                         /*!<New Data flag of Rx Buffer 17             */

+#define FDCAN_NDAT1_ND18_Pos      (18U)

+#define FDCAN_NDAT1_ND18_Msk      (0x1UL << FDCAN_NDAT1_ND18_Pos)              /*!< 0x00040000 */

+#define FDCAN_NDAT1_ND18          FDCAN_NDAT1_ND18_Msk                         /*!<New Data flag of Rx Buffer 18             */

+#define FDCAN_NDAT1_ND19_Pos      (19U)

+#define FDCAN_NDAT1_ND19_Msk      (0x1UL << FDCAN_NDAT1_ND19_Pos)              /*!< 0x00080000 */

+#define FDCAN_NDAT1_ND19          FDCAN_NDAT1_ND19_Msk                         /*!<New Data flag of Rx Buffer 19             */

+#define FDCAN_NDAT1_ND20_Pos      (20U)

+#define FDCAN_NDAT1_ND20_Msk      (0x1UL << FDCAN_NDAT1_ND20_Pos)              /*!< 0x00100000 */

+#define FDCAN_NDAT1_ND20          FDCAN_NDAT1_ND20_Msk                         /*!<New Data flag of Rx Buffer 20             */

+#define FDCAN_NDAT1_ND21_Pos      (21U)

+#define FDCAN_NDAT1_ND21_Msk      (0x1UL << FDCAN_NDAT1_ND21_Pos)              /*!< 0x00200000 */

+#define FDCAN_NDAT1_ND21          FDCAN_NDAT1_ND21_Msk                         /*!<New Data flag of Rx Buffer 21             */

+#define FDCAN_NDAT1_ND22_Pos      (22U)

+#define FDCAN_NDAT1_ND22_Msk      (0x1UL << FDCAN_NDAT1_ND22_Pos)              /*!< 0x00400000 */

+#define FDCAN_NDAT1_ND22          FDCAN_NDAT1_ND22_Msk                         /*!<New Data flag of Rx Buffer 22             */

+#define FDCAN_NDAT1_ND23_Pos      (23U)

+#define FDCAN_NDAT1_ND23_Msk      (0x1UL << FDCAN_NDAT1_ND23_Pos)              /*!< 0x00800000 */

+#define FDCAN_NDAT1_ND23          FDCAN_NDAT1_ND23_Msk                         /*!<New Data flag of Rx Buffer 23             */

+#define FDCAN_NDAT1_ND24_Pos      (24U)

+#define FDCAN_NDAT1_ND24_Msk      (0x1UL << FDCAN_NDAT1_ND24_Pos)              /*!< 0x01000000 */

+#define FDCAN_NDAT1_ND24          FDCAN_NDAT1_ND24_Msk                         /*!<New Data flag of Rx Buffer 24             */

+#define FDCAN_NDAT1_ND25_Pos      (25U)

+#define FDCAN_NDAT1_ND25_Msk      (0x1UL << FDCAN_NDAT1_ND25_Pos)              /*!< 0x02000000 */

+#define FDCAN_NDAT1_ND25          FDCAN_NDAT1_ND25_Msk                         /*!<New Data flag of Rx Buffer 25             */

+#define FDCAN_NDAT1_ND26_Pos      (26U)

+#define FDCAN_NDAT1_ND26_Msk      (0x1UL << FDCAN_NDAT1_ND26_Pos)              /*!< 0x04000000 */

+#define FDCAN_NDAT1_ND26          FDCAN_NDAT1_ND26_Msk                         /*!<New Data flag of Rx Buffer 26             */

+#define FDCAN_NDAT1_ND27_Pos      (27U)

+#define FDCAN_NDAT1_ND27_Msk      (0x1UL << FDCAN_NDAT1_ND27_Pos)              /*!< 0x08000000 */

+#define FDCAN_NDAT1_ND27          FDCAN_NDAT1_ND27_Msk                         /*!<New Data flag of Rx Buffer 27             */

+#define FDCAN_NDAT1_ND28_Pos      (28U)

+#define FDCAN_NDAT1_ND28_Msk      (0x1UL << FDCAN_NDAT1_ND28_Pos)              /*!< 0x10000000 */

+#define FDCAN_NDAT1_ND28          FDCAN_NDAT1_ND28_Msk                         /*!<New Data flag of Rx Buffer 28             */

+#define FDCAN_NDAT1_ND29_Pos      (29U)

+#define FDCAN_NDAT1_ND29_Msk      (0x1UL << FDCAN_NDAT1_ND29_Pos)              /*!< 0x20000000 */

+#define FDCAN_NDAT1_ND29          FDCAN_NDAT1_ND29_Msk                         /*!<New Data flag of Rx Buffer 29             */

+#define FDCAN_NDAT1_ND30_Pos      (30U)

+#define FDCAN_NDAT1_ND30_Msk      (0x1UL << FDCAN_NDAT1_ND30_Pos)              /*!< 0x40000000 */

+#define FDCAN_NDAT1_ND30          FDCAN_NDAT1_ND30_Msk                         /*!<New Data flag of Rx Buffer 30             */

+#define FDCAN_NDAT1_ND31_Pos      (31U)

+#define FDCAN_NDAT1_ND31_Msk      (0x1UL << FDCAN_NDAT1_ND31_Pos)              /*!< 0x80000000 */

+#define FDCAN_NDAT1_ND31          FDCAN_NDAT1_ND31_Msk                         /*!<New Data flag of Rx Buffer 31             */

+

+/*****************  Bit definition for FDCAN_NDAT2 register  ********************/

+#define FDCAN_NDAT2_ND32_Pos      (0U)

+#define FDCAN_NDAT2_ND32_Msk      (0x1UL << FDCAN_NDAT2_ND32_Pos)              /*!< 0x00000001 */

+#define FDCAN_NDAT2_ND32          FDCAN_NDAT2_ND32_Msk                         /*!<New Data flag of Rx Buffer 32             */

+#define FDCAN_NDAT2_ND33_Pos      (1U)

+#define FDCAN_NDAT2_ND33_Msk      (0x1UL << FDCAN_NDAT2_ND33_Pos)              /*!< 0x00000002 */

+#define FDCAN_NDAT2_ND33          FDCAN_NDAT2_ND33_Msk                         /*!<New Data flag of Rx Buffer 33             */

+#define FDCAN_NDAT2_ND34_Pos      (2U)

+#define FDCAN_NDAT2_ND34_Msk      (0x1UL << FDCAN_NDAT2_ND34_Pos)              /*!< 0x00000004 */

+#define FDCAN_NDAT2_ND34          FDCAN_NDAT2_ND34_Msk                         /*!<New Data flag of Rx Buffer 34             */

+#define FDCAN_NDAT2_ND35_Pos      (3U)

+#define FDCAN_NDAT2_ND35_Msk      (0x1UL << FDCAN_NDAT2_ND35_Pos)              /*!< 0x00000008 */

+#define FDCAN_NDAT2_ND35          FDCAN_NDAT2_ND35_Msk                         /*!<New Data flag of Rx Buffer 35             */

+#define FDCAN_NDAT2_ND36_Pos      (4U)

+#define FDCAN_NDAT2_ND36_Msk      (0x1UL << FDCAN_NDAT2_ND36_Pos)              /*!< 0x00000010 */

+#define FDCAN_NDAT2_ND36          FDCAN_NDAT2_ND36_Msk                         /*!<New Data flag of Rx Buffer 36             */

+#define FDCAN_NDAT2_ND37_Pos      (5U)

+#define FDCAN_NDAT2_ND37_Msk      (0x1UL << FDCAN_NDAT2_ND37_Pos)              /*!< 0x00000020 */

+#define FDCAN_NDAT2_ND37          FDCAN_NDAT2_ND37_Msk                         /*!<New Data flag of Rx Buffer 37             */

+#define FDCAN_NDAT2_ND38_Pos      (6U)

+#define FDCAN_NDAT2_ND38_Msk      (0x1UL << FDCAN_NDAT2_ND38_Pos)              /*!< 0x00000040 */

+#define FDCAN_NDAT2_ND38          FDCAN_NDAT2_ND38_Msk                         /*!<New Data flag of Rx Buffer 38             */

+#define FDCAN_NDAT2_ND39_Pos      (7U)

+#define FDCAN_NDAT2_ND39_Msk      (0x1UL << FDCAN_NDAT2_ND39_Pos)              /*!< 0x00000080 */

+#define FDCAN_NDAT2_ND39          FDCAN_NDAT2_ND39_Msk                         /*!<New Data flag of Rx Buffer 39             */

+#define FDCAN_NDAT2_ND40_Pos      (8U)

+#define FDCAN_NDAT2_ND40_Msk      (0x1UL << FDCAN_NDAT2_ND40_Pos)              /*!< 0x00000100 */

+#define FDCAN_NDAT2_ND40          FDCAN_NDAT2_ND40_Msk                         /*!<New Data flag of Rx Buffer 40             */

+#define FDCAN_NDAT2_ND41_Pos      (9U)

+#define FDCAN_NDAT2_ND41_Msk      (0x1UL << FDCAN_NDAT2_ND41_Pos)              /*!< 0x00000200 */

+#define FDCAN_NDAT2_ND41          FDCAN_NDAT2_ND41_Msk                         /*!<New Data flag of Rx Buffer 41             */

+#define FDCAN_NDAT2_ND42_Pos      (10U)

+#define FDCAN_NDAT2_ND42_Msk      (0x1UL << FDCAN_NDAT2_ND42_Pos)              /*!< 0x00000400 */

+#define FDCAN_NDAT2_ND42          FDCAN_NDAT2_ND42_Msk                         /*!<New Data flag of Rx Buffer 42             */

+#define FDCAN_NDAT2_ND43_Pos      (11U)

+#define FDCAN_NDAT2_ND43_Msk      (0x1UL << FDCAN_NDAT2_ND43_Pos)              /*!< 0x00000800 */

+#define FDCAN_NDAT2_ND43          FDCAN_NDAT2_ND43_Msk                         /*!<New Data flag of Rx Buffer 43             */

+#define FDCAN_NDAT2_ND44_Pos      (12U)

+#define FDCAN_NDAT2_ND44_Msk      (0x1UL << FDCAN_NDAT2_ND44_Pos)              /*!< 0x00001000 */

+#define FDCAN_NDAT2_ND44          FDCAN_NDAT2_ND44_Msk                         /*!<New Data flag of Rx Buffer 44             */

+#define FDCAN_NDAT2_ND45_Pos      (13U)

+#define FDCAN_NDAT2_ND45_Msk      (0x1UL << FDCAN_NDAT2_ND45_Pos)              /*!< 0x00002000 */

+#define FDCAN_NDAT2_ND45          FDCAN_NDAT2_ND45_Msk                         /*!<New Data flag of Rx Buffer 45             */

+#define FDCAN_NDAT2_ND46_Pos      (14U)

+#define FDCAN_NDAT2_ND46_Msk      (0x1UL << FDCAN_NDAT2_ND46_Pos)              /*!< 0x00004000 */

+#define FDCAN_NDAT2_ND46          FDCAN_NDAT2_ND46_Msk                         /*!<New Data flag of Rx Buffer 46             */

+#define FDCAN_NDAT2_ND47_Pos      (15U)

+#define FDCAN_NDAT2_ND47_Msk      (0x1UL << FDCAN_NDAT2_ND47_Pos)              /*!< 0x00008000 */

+#define FDCAN_NDAT2_ND47          FDCAN_NDAT2_ND47_Msk                         /*!<New Data flag of Rx Buffer 47             */

+#define FDCAN_NDAT2_ND48_Pos      (16U)

+#define FDCAN_NDAT2_ND48_Msk      (0x1UL << FDCAN_NDAT2_ND48_Pos)              /*!< 0x00010000 */

+#define FDCAN_NDAT2_ND48          FDCAN_NDAT2_ND48_Msk                         /*!<New Data flag of Rx Buffer 48             */

+#define FDCAN_NDAT2_ND49_Pos      (17U)

+#define FDCAN_NDAT2_ND49_Msk      (0x1UL << FDCAN_NDAT2_ND49_Pos)              /*!< 0x00020000 */

+#define FDCAN_NDAT2_ND49          FDCAN_NDAT2_ND49_Msk                         /*!<New Data flag of Rx Buffer 49             */

+#define FDCAN_NDAT2_ND50_Pos      (18U)

+#define FDCAN_NDAT2_ND50_Msk      (0x1UL << FDCAN_NDAT2_ND50_Pos)              /*!< 0x00040000 */

+#define FDCAN_NDAT2_ND50          FDCAN_NDAT2_ND50_Msk                         /*!<New Data flag of Rx Buffer 50             */

+#define FDCAN_NDAT2_ND51_Pos      (19U)

+#define FDCAN_NDAT2_ND51_Msk      (0x1UL << FDCAN_NDAT2_ND51_Pos)              /*!< 0x00080000 */

+#define FDCAN_NDAT2_ND51          FDCAN_NDAT2_ND51_Msk                         /*!<New Data flag of Rx Buffer 51             */

+#define FDCAN_NDAT2_ND52_Pos      (20U)

+#define FDCAN_NDAT2_ND52_Msk      (0x1UL << FDCAN_NDAT2_ND52_Pos)              /*!< 0x00100000 */

+#define FDCAN_NDAT2_ND52          FDCAN_NDAT2_ND52_Msk                         /*!<New Data flag of Rx Buffer 52             */

+#define FDCAN_NDAT2_ND53_Pos      (21U)

+#define FDCAN_NDAT2_ND53_Msk      (0x1UL << FDCAN_NDAT2_ND53_Pos)              /*!< 0x00200000 */

+#define FDCAN_NDAT2_ND53          FDCAN_NDAT2_ND53_Msk                         /*!<New Data flag of Rx Buffer 53             */

+#define FDCAN_NDAT2_ND54_Pos      (22U)

+#define FDCAN_NDAT2_ND54_Msk      (0x1UL << FDCAN_NDAT2_ND54_Pos)              /*!< 0x00400000 */

+#define FDCAN_NDAT2_ND54          FDCAN_NDAT2_ND54_Msk                         /*!<New Data flag of Rx Buffer 54             */

+#define FDCAN_NDAT2_ND55_Pos      (23U)

+#define FDCAN_NDAT2_ND55_Msk      (0x1UL << FDCAN_NDAT2_ND55_Pos)              /*!< 0x00800000 */

+#define FDCAN_NDAT2_ND55          FDCAN_NDAT2_ND55_Msk                         /*!<New Data flag of Rx Buffer 55             */

+#define FDCAN_NDAT2_ND56_Pos      (24U)

+#define FDCAN_NDAT2_ND56_Msk      (0x1UL << FDCAN_NDAT2_ND56_Pos)              /*!< 0x01000000 */

+#define FDCAN_NDAT2_ND56          FDCAN_NDAT2_ND56_Msk                         /*!<New Data flag of Rx Buffer 56             */

+#define FDCAN_NDAT2_ND57_Pos      (25U)

+#define FDCAN_NDAT2_ND57_Msk      (0x1UL << FDCAN_NDAT2_ND57_Pos)              /*!< 0x02000000 */

+#define FDCAN_NDAT2_ND57          FDCAN_NDAT2_ND57_Msk                         /*!<New Data flag of Rx Buffer 57             */

+#define FDCAN_NDAT2_ND58_Pos      (26U)

+#define FDCAN_NDAT2_ND58_Msk      (0x1UL << FDCAN_NDAT2_ND58_Pos)              /*!< 0x04000000 */

+#define FDCAN_NDAT2_ND58          FDCAN_NDAT2_ND58_Msk                         /*!<New Data flag of Rx Buffer 58             */

+#define FDCAN_NDAT2_ND59_Pos      (27U)

+#define FDCAN_NDAT2_ND59_Msk      (0x1UL << FDCAN_NDAT2_ND59_Pos)              /*!< 0x08000000 */

+#define FDCAN_NDAT2_ND59          FDCAN_NDAT2_ND59_Msk                         /*!<New Data flag of Rx Buffer 59             */

+#define FDCAN_NDAT2_ND60_Pos      (28U)

+#define FDCAN_NDAT2_ND60_Msk      (0x1UL << FDCAN_NDAT2_ND60_Pos)              /*!< 0x10000000 */

+#define FDCAN_NDAT2_ND60          FDCAN_NDAT2_ND60_Msk                         /*!<New Data flag of Rx Buffer 60             */

+#define FDCAN_NDAT2_ND61_Pos      (29U)

+#define FDCAN_NDAT2_ND61_Msk      (0x1UL << FDCAN_NDAT2_ND61_Pos)              /*!< 0x20000000 */

+#define FDCAN_NDAT2_ND61          FDCAN_NDAT2_ND61_Msk                         /*!<New Data flag of Rx Buffer 61             */

+#define FDCAN_NDAT2_ND62_Pos      (30U)

+#define FDCAN_NDAT2_ND62_Msk      (0x1UL << FDCAN_NDAT2_ND62_Pos)              /*!< 0x40000000 */

+#define FDCAN_NDAT2_ND62          FDCAN_NDAT2_ND62_Msk                         /*!<New Data flag of Rx Buffer 62             */

+#define FDCAN_NDAT2_ND63_Pos      (31U)

+#define FDCAN_NDAT2_ND63_Msk      (0x1UL << FDCAN_NDAT2_ND63_Pos)              /*!< 0x80000000 */

+#define FDCAN_NDAT2_ND63          FDCAN_NDAT2_ND63_Msk                         /*!<New Data flag of Rx Buffer 63             */

+

+/*****************  Bit definition for FDCAN_RXF0C register  ********************/

+#define FDCAN_RXF0C_F0SA_Pos      (2U)

+#define FDCAN_RXF0C_F0SA_Msk      (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_RXF0C_F0SA          FDCAN_RXF0C_F0SA_Msk                         /*!<Rx FIFO 0 Start Address                   */

+#define FDCAN_RXF0C_F0S_Pos       (16U)

+#define FDCAN_RXF0C_F0S_Msk       (0x7FUL << FDCAN_RXF0C_F0S_Pos)              /*!< 0x007F0000 */

+#define FDCAN_RXF0C_F0S           FDCAN_RXF0C_F0S_Msk                          /*!<Number of Rx FIFO 0 elements              */

+#define FDCAN_RXF0C_F0WM_Pos      (24U)

+#define FDCAN_RXF0C_F0WM_Msk      (0x7FUL << FDCAN_RXF0C_F0WM_Pos)             /*!< 0x7F000000 */

+#define FDCAN_RXF0C_F0WM          FDCAN_RXF0C_F0WM_Msk                         /*!<FIFO 0 Watermark                          */

+#define FDCAN_RXF0C_F0OM_Pos      (31U)

+#define FDCAN_RXF0C_F0OM_Msk      (0x1UL << FDCAN_RXF0C_F0OM_Pos)              /*!< 0x80000000 */

+#define FDCAN_RXF0C_F0OM          FDCAN_RXF0C_F0OM_Msk                         /*!<FIFO 0 Operation Mode                     */

+

+/*****************  Bit definition for FDCAN_RXF0S register  ********************/

+#define FDCAN_RXF0S_F0FL_Pos      (0U)

+#define FDCAN_RXF0S_F0FL_Msk      (0x7FUL << FDCAN_RXF0S_F0FL_Pos)             /*!< 0x0000007F */

+#define FDCAN_RXF0S_F0FL          FDCAN_RXF0S_F0FL_Msk                         /*!<Rx FIFO 0 Fill Level                      */

+#define FDCAN_RXF0S_F0GI_Pos      (8U)

+#define FDCAN_RXF0S_F0GI_Msk      (0x3FUL << FDCAN_RXF0S_F0GI_Pos)             /*!< 0x00003F00 */

+#define FDCAN_RXF0S_F0GI          FDCAN_RXF0S_F0GI_Msk                         /*!<Rx FIFO 0 Get Index                       */

+#define FDCAN_RXF0S_F0PI_Pos      (16U)

+#define FDCAN_RXF0S_F0PI_Msk      (0x3FUL << FDCAN_RXF0S_F0PI_Pos)             /*!< 0x003F0000 */

+#define FDCAN_RXF0S_F0PI          FDCAN_RXF0S_F0PI_Msk                         /*!<Rx FIFO 0 Put Index                       */

+#define FDCAN_RXF0S_F0F_Pos       (24U)

+#define FDCAN_RXF0S_F0F_Msk       (0x1UL << FDCAN_RXF0S_F0F_Pos)               /*!< 0x01000000 */

+#define FDCAN_RXF0S_F0F           FDCAN_RXF0S_F0F_Msk                          /*!<Rx FIFO 0 Full                            */

+#define FDCAN_RXF0S_RF0L_Pos      (25U)

+#define FDCAN_RXF0S_RF0L_Msk      (0x1UL << FDCAN_RXF0S_RF0L_Pos)              /*!< 0x02000000 */

+#define FDCAN_RXF0S_RF0L          FDCAN_RXF0S_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                    */

+

+/*****************  Bit definition for FDCAN_RXF0A register  ********************/

+#define FDCAN_RXF0A_F0AI_Pos      (0U)

+#define FDCAN_RXF0A_F0AI_Msk      (0x3FUL << FDCAN_RXF0A_F0AI_Pos)             /*!< 0x0000003F */

+#define FDCAN_RXF0A_F0AI          FDCAN_RXF0A_F0AI_Msk                         /*!<Rx FIFO 0 Acknowledge Index               */

+

+/*****************  Bit definition for FDCAN_RXBC register  ********************/

+#define FDCAN_RXBC_RBSA_Pos       (2U)

+#define FDCAN_RXBC_RBSA_Msk       (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)            /*!< 0x0000FFFC */

+#define FDCAN_RXBC_RBSA           FDCAN_RXBC_RBSA_Msk                          /*!<Rx Buffer Start Address                   */

+

+/*****************  Bit definition for FDCAN_RXF1C register  ********************/

+#define FDCAN_RXF1C_F1SA_Pos      (2U)

+#define FDCAN_RXF1C_F1SA_Msk      (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_RXF1C_F1SA          FDCAN_RXF1C_F1SA_Msk                         /*!<Rx FIFO 1 Start Address                   */

+#define FDCAN_RXF1C_F1S_Pos       (16U)

+#define FDCAN_RXF1C_F1S_Msk       (0x7FUL << FDCAN_RXF1C_F1S_Pos)              /*!< 0x007F0000 */

+#define FDCAN_RXF1C_F1S           FDCAN_RXF1C_F1S_Msk                          /*!<Number of Rx FIFO 1 elements              */

+#define FDCAN_RXF1C_F1WM_Pos      (24U)

+#define FDCAN_RXF1C_F1WM_Msk      (0x7FUL << FDCAN_RXF1C_F1WM_Pos)             /*!< 0x7F000000 */

+#define FDCAN_RXF1C_F1WM          FDCAN_RXF1C_F1WM_Msk                         /*!<Rx FIFO 1 Watermark                       */

+#define FDCAN_RXF1C_F1OM_Pos      (31U)

+#define FDCAN_RXF1C_F1OM_Msk      (0x1UL << FDCAN_RXF1C_F1OM_Pos)              /*!< 0x80000000 */

+#define FDCAN_RXF1C_F1OM          FDCAN_RXF1C_F1OM_Msk                         /*!<FIFO 1 Operation Mode                     */

+

+/*****************  Bit definition for FDCAN_RXF1S register  ********************/

+#define FDCAN_RXF1S_F1FL_Pos      (0U)

+#define FDCAN_RXF1S_F1FL_Msk      (0x7FUL << FDCAN_RXF1S_F1FL_Pos)             /*!< 0x0000007F */

+#define FDCAN_RXF1S_F1FL          FDCAN_RXF1S_F1FL_Msk                         /*!<Rx FIFO 1 Fill Level                      */

+#define FDCAN_RXF1S_F1GI_Pos      (8U)

+#define FDCAN_RXF1S_F1GI_Msk      (0x3FUL << FDCAN_RXF1S_F1GI_Pos)             /*!< 0x00003F00 */

+#define FDCAN_RXF1S_F1GI          FDCAN_RXF1S_F1GI_Msk                         /*!<Rx FIFO 1 Get Index                       */

+#define FDCAN_RXF1S_F1PI_Pos      (16U)

+#define FDCAN_RXF1S_F1PI_Msk      (0x3FUL << FDCAN_RXF1S_F1PI_Pos)             /*!< 0x003F0000 */

+#define FDCAN_RXF1S_F1PI          FDCAN_RXF1S_F1PI_Msk                         /*!<Rx FIFO 1 Put Index                       */

+#define FDCAN_RXF1S_F1F_Pos       (24U)

+#define FDCAN_RXF1S_F1F_Msk       (0x1UL << FDCAN_RXF1S_F1F_Pos)               /*!< 0x01000000 */

+#define FDCAN_RXF1S_F1F           FDCAN_RXF1S_F1F_Msk                          /*!<Rx FIFO 1 Full                            */

+#define FDCAN_RXF1S_RF1L_Pos      (25U)

+#define FDCAN_RXF1S_RF1L_Msk      (0x1UL << FDCAN_RXF1S_RF1L_Pos)              /*!< 0x02000000 */

+#define FDCAN_RXF1S_RF1L          FDCAN_RXF1S_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                    */

+

+/*****************  Bit definition for FDCAN_RXF1A register  ********************/

+#define FDCAN_RXF1A_F1AI_Pos      (0U)

+#define FDCAN_RXF1A_F1AI_Msk      (0x3FUL << FDCAN_RXF1A_F1AI_Pos)             /*!< 0x0000003F */

+#define FDCAN_RXF1A_F1AI          FDCAN_RXF1A_F1AI_Msk                         /*!<Rx FIFO 1 Acknowledge Index               */

+

+/*****************  Bit definition for FDCAN_RXESC register  ********************/

+#define FDCAN_RXESC_F0DS_Pos      (0U)

+#define FDCAN_RXESC_F0DS_Msk      (0x7UL << FDCAN_RXESC_F0DS_Pos)              /*!< 0x00000007 */

+#define FDCAN_RXESC_F0DS          FDCAN_RXESC_F0DS_Msk                         /*!<Rx FIFO 1 Data Field Size                 */

+#define FDCAN_RXESC_F1DS_Pos      (4U)

+#define FDCAN_RXESC_F1DS_Msk      (0x7UL << FDCAN_RXESC_F1DS_Pos)              /*!< 0x00000070 */

+#define FDCAN_RXESC_F1DS          FDCAN_RXESC_F1DS_Msk                         /*!<Rx FIFO 0 Data Field Size                 */

+#define FDCAN_RXESC_RBDS_Pos      (8U)

+#define FDCAN_RXESC_RBDS_Msk      (0x7UL << FDCAN_RXESC_RBDS_Pos)              /*!< 0x00000700 */

+#define FDCAN_RXESC_RBDS          FDCAN_RXESC_RBDS_Msk                         /*!<Rx Buffer Data Field Size                 */

+

+/*****************  Bit definition for FDCAN_TXBC register  *********************/

+#define FDCAN_TXBC_TBSA_Pos       (2U)

+#define FDCAN_TXBC_TBSA_Msk       (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)            /*!< 0x0000FFFC */

+#define FDCAN_TXBC_TBSA           FDCAN_TXBC_TBSA_Msk                          /*!<Tx Buffers Start Address                  */

+#define FDCAN_TXBC_NDTB_Pos       (16U)

+#define FDCAN_TXBC_NDTB_Msk       (0x3FUL << FDCAN_TXBC_NDTB_Pos)              /*!< 0x003F0000 */

+#define FDCAN_TXBC_NDTB           FDCAN_TXBC_NDTB_Msk                          /*!<Number of Dedicated Transmit Buffers      */

+#define FDCAN_TXBC_TFQS_Pos       (24U)

+#define FDCAN_TXBC_TFQS_Msk       (0x3FUL << FDCAN_TXBC_TFQS_Pos)              /*!< 0x3F000000 */

+#define FDCAN_TXBC_TFQS           FDCAN_TXBC_TFQS_Msk                          /*!<Transmit FIFO/Queue Size                  */

+#define FDCAN_TXBC_TFQM_Pos       (30U)

+#define FDCAN_TXBC_TFQM_Msk       (0x1UL << FDCAN_TXBC_TFQM_Pos)               /*!< 0x40000000 */

+#define FDCAN_TXBC_TFQM           FDCAN_TXBC_TFQM_Msk                          /*!<Tx FIFO/Queue Mode                        */

+

+/*****************  Bit definition for FDCAN_TXFQS register  *********************/

+#define FDCAN_TXFQS_TFFL_Pos      (0U)

+#define FDCAN_TXFQS_TFFL_Msk      (0x3FUL << FDCAN_TXFQS_TFFL_Pos)             /*!< 0x0000003F */

+#define FDCAN_TXFQS_TFFL          FDCAN_TXFQS_TFFL_Msk                         /*!<Tx FIFO Free Level                        */

+#define FDCAN_TXFQS_TFGI_Pos      (8U)

+#define FDCAN_TXFQS_TFGI_Msk      (0x1FUL << FDCAN_TXFQS_TFGI_Pos)             /*!< 0x00001F00 */

+#define FDCAN_TXFQS_TFGI          FDCAN_TXFQS_TFGI_Msk                         /*!<Tx FIFO Get Index                         */

+#define FDCAN_TXFQS_TFQPI_Pos     (16U)

+#define FDCAN_TXFQS_TFQPI_Msk     (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)            /*!< 0x001F0000 */

+#define FDCAN_TXFQS_TFQPI         FDCAN_TXFQS_TFQPI_Msk                        /*!<Tx FIFO/Queue Put Index                   */

+#define FDCAN_TXFQS_TFQF_Pos      (21U)

+#define FDCAN_TXFQS_TFQF_Msk      (0x1UL << FDCAN_TXFQS_TFQF_Pos)              /*!< 0x00200000 */

+#define FDCAN_TXFQS_TFQF          FDCAN_TXFQS_TFQF_Msk                         /*!<Tx FIFO/Queue Full                        */

+

+/*****************  Bit definition for FDCAN_TXESC register  *********************/

+#define FDCAN_TXESC_TBDS_Pos      (0U)

+#define FDCAN_TXESC_TBDS_Msk      (0x7UL << FDCAN_TXESC_TBDS_Pos)              /*!< 0x00000007 */

+#define FDCAN_TXESC_TBDS          FDCAN_TXESC_TBDS_Msk                         /*!<Tx Buffer Data Field Size                 */

+

+/*****************  Bit definition for FDCAN_TXBRP register  *********************/

+#define FDCAN_TXBRP_TRP_Pos       (0U)

+#define FDCAN_TXBRP_TRP_Msk       (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)        /*!< 0xFFFFFFFF */

+#define FDCAN_TXBRP_TRP           FDCAN_TXBRP_TRP_Msk                          /*!<Transmission Request Pending              */

+

+/*****************  Bit definition for FDCAN_TXBAR register  *********************/

+#define FDCAN_TXBAR_AR_Pos        (0U)

+#define FDCAN_TXBAR_AR_Msk        (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBAR_AR            FDCAN_TXBAR_AR_Msk                           /*!<Add Request                               */

+

+/*****************  Bit definition for FDCAN_TXBCR register  *********************/

+#define FDCAN_TXBCR_CR_Pos        (0U)

+#define FDCAN_TXBCR_CR_Msk        (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCR_CR            FDCAN_TXBCR_CR_Msk                           /*!<Cancellation Request                      */

+

+/*****************  Bit definition for FDCAN_TXBTO register  *********************/

+#define FDCAN_TXBTO_TO_Pos        (0U)

+#define FDCAN_TXBTO_TO_Msk        (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBTO_TO            FDCAN_TXBTO_TO_Msk                           /*!<Transmission Occurred                     */

+

+/*****************  Bit definition for FDCAN_TXBCF register  *********************/

+#define FDCAN_TXBCF_CF_Pos        (0U)

+#define FDCAN_TXBCF_CF_Msk        (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCF_CF            FDCAN_TXBCF_CF_Msk                           /*!<Cancellation Finished                     */

+

+/*****************  Bit definition for FDCAN_TXBTIE register  ********************/

+#define FDCAN_TXBTIE_TIE_Pos      (0U)

+#define FDCAN_TXBTIE_TIE_Msk      (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)       /*!< 0xFFFFFFFF */

+#define FDCAN_TXBTIE_TIE          FDCAN_TXBTIE_TIE_Msk                         /*!<Transmission Interrupt Enable             */

+

+/*****************  Bit definition for FDCAN_ TXBCIE register  *******************/

+#define FDCAN_TXBCIE_CFIE_Pos     (0U)

+#define FDCAN_TXBCIE_CFIE_Msk     (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)      /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCIE_CFIE         FDCAN_TXBCIE_CFIE_Msk                        /*!<Cancellation Finished Interrupt Enable    */

+

+/*****************  Bit definition for FDCAN_TXEFC register  *********************/

+#define FDCAN_TXEFC_EFSA_Pos      (2U)

+#define FDCAN_TXEFC_EFSA_Msk      (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_TXEFC_EFSA          FDCAN_TXEFC_EFSA_Msk                         /*!<Event FIFO Start Address                  */

+#define FDCAN_TXEFC_EFS_Pos       (16U)

+#define FDCAN_TXEFC_EFS_Msk       (0x3FUL << FDCAN_TXEFC_EFS_Pos)              /*!< 0x003F0000 */

+#define FDCAN_TXEFC_EFS           FDCAN_TXEFC_EFS_Msk                          /*!<Event FIFO Size                           */

+#define FDCAN_TXEFC_EFWM_Pos      (24U)

+#define FDCAN_TXEFC_EFWM_Msk      (0x3FUL << FDCAN_TXEFC_EFWM_Pos)             /*!< 0x3F000000 */

+#define FDCAN_TXEFC_EFWM          FDCAN_TXEFC_EFWM_Msk                         /*!<Event FIFO Watermark                      */

+

+/*****************  Bit definition for FDCAN_TXEFS register  *********************/

+#define FDCAN_TXEFS_EFFL_Pos      (0U)

+#define FDCAN_TXEFS_EFFL_Msk      (0x3FUL << FDCAN_TXEFS_EFFL_Pos)             /*!< 0x0000003F */

+#define FDCAN_TXEFS_EFFL          FDCAN_TXEFS_EFFL_Msk                         /*!<Event FIFO Fill Level                     */

+#define FDCAN_TXEFS_EFGI_Pos      (8U)

+#define FDCAN_TXEFS_EFGI_Msk      (0x1FUL << FDCAN_TXEFS_EFGI_Pos)             /*!< 0x00001F00 */

+#define FDCAN_TXEFS_EFGI          FDCAN_TXEFS_EFGI_Msk                         /*!<Event FIFO Get Index                      */

+#define FDCAN_TXEFS_EFPI_Pos      (16U)

+#define FDCAN_TXEFS_EFPI_Msk      (0x1FUL << FDCAN_TXEFS_EFPI_Pos)             /*!< 0x001F0000 */

+#define FDCAN_TXEFS_EFPI          FDCAN_TXEFS_EFPI_Msk                         /*!<Event FIFO Put Index                      */

+#define FDCAN_TXEFS_EFF_Pos       (24U)

+#define FDCAN_TXEFS_EFF_Msk       (0x1UL << FDCAN_TXEFS_EFF_Pos)               /*!< 0x01000000 */

+#define FDCAN_TXEFS_EFF           FDCAN_TXEFS_EFF_Msk                          /*!<Event FIFO Full                           */

+#define FDCAN_TXEFS_TEFL_Pos      (25U)

+#define FDCAN_TXEFS_TEFL_Msk      (0x1UL << FDCAN_TXEFS_TEFL_Pos)              /*!< 0x02000000 */

+#define FDCAN_TXEFS_TEFL          FDCAN_TXEFS_TEFL_Msk                         /*!<Tx Event FIFO Element Lost                */

+

+/*****************  Bit definition for FDCAN_TXEFA register  *********************/

+#define FDCAN_TXEFA_EFAI_Pos      (0U)

+#define FDCAN_TXEFA_EFAI_Msk      (0x1FUL << FDCAN_TXEFA_EFAI_Pos)             /*!< 0x0000001F */

+#define FDCAN_TXEFA_EFAI          FDCAN_TXEFA_EFAI_Msk                         /*!<Event FIFO Acknowledge Index              */

+

+/*****************  Bit definition for FDCAN_TTTMC register  *********************/

+#define FDCAN_TTTMC_TMSA_Pos      (2U)

+#define FDCAN_TTTMC_TMSA_Msk      (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_TTTMC_TMSA          FDCAN_TTTMC_TMSA_Msk                         /*!<Trigger Memory Start Address              */

+#define FDCAN_TTTMC_TME_Pos       (16U)

+#define FDCAN_TTTMC_TME_Msk       (0x7FUL << FDCAN_TTTMC_TME_Pos)              /*!< 0x007F0000 */

+#define FDCAN_TTTMC_TME           FDCAN_TTTMC_TME_Msk                          /*!<Trigger Memory Elements                   */

+

+/*****************  Bit definition for FDCAN_TTRMC register  *********************/

+#define FDCAN_TTRMC_RID_Pos       (0U)

+#define FDCAN_TTRMC_RID_Msk       (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)        /*!< 0x1FFFFFFF */

+#define FDCAN_TTRMC_RID           FDCAN_TTRMC_RID_Msk                          /*!<Reference Identifier                      */

+#define FDCAN_TTRMC_XTD_Pos       (30U)

+#define FDCAN_TTRMC_XTD_Msk       (0x1UL << FDCAN_TTRMC_XTD_Pos)               /*!< 0x40000000 */

+#define FDCAN_TTRMC_XTD           FDCAN_TTRMC_XTD_Msk                          /*!< Extended Identifier                      */

+#define FDCAN_TTRMC_RMPS_Pos      (31U)

+#define FDCAN_TTRMC_RMPS_Msk      (0x1UL << FDCAN_TTRMC_RMPS_Pos)              /*!< 0x80000000 */

+#define FDCAN_TTRMC_RMPS          FDCAN_TTRMC_RMPS_Msk                         /*!<Reference Message Payload Select          */

+

+/*****************  Bit definition for FDCAN_TTOCF register  *********************/

+#define FDCAN_TTOCF_OM_Pos        (0U)

+#define FDCAN_TTOCF_OM_Msk        (0x3UL << FDCAN_TTOCF_OM_Pos)                /*!< 0x00000003 */

+#define FDCAN_TTOCF_OM            FDCAN_TTOCF_OM_Msk                           /*!<Operation Mode                            */

+#define FDCAN_TTOCF_GEN_Pos       (3U)

+#define FDCAN_TTOCF_GEN_Msk       (0x1UL << FDCAN_TTOCF_GEN_Pos)               /*!< 0x00000008 */

+#define FDCAN_TTOCF_GEN           FDCAN_TTOCF_GEN_Msk                          /*!<Gap Enable                                */

+#define FDCAN_TTOCF_TM_Pos        (4U)

+#define FDCAN_TTOCF_TM_Msk        (0x1UL << FDCAN_TTOCF_TM_Pos)                /*!< 0x00000010 */

+#define FDCAN_TTOCF_TM            FDCAN_TTOCF_TM_Msk                           /*!<Time Master                               */

+#define FDCAN_TTOCF_LDSDL_Pos     (5U)

+#define FDCAN_TTOCF_LDSDL_Msk     (0x7UL << FDCAN_TTOCF_LDSDL_Pos)             /*!< 0x000000E0 */

+#define FDCAN_TTOCF_LDSDL         FDCAN_TTOCF_LDSDL_Msk                        /*!<LD of Synchronization Deviation Limit     */

+#define FDCAN_TTOCF_IRTO_Pos      (8U)

+#define FDCAN_TTOCF_IRTO_Msk      (0x7FUL << FDCAN_TTOCF_IRTO_Pos)             /*!< 0x00007F00 */

+#define FDCAN_TTOCF_IRTO          FDCAN_TTOCF_IRTO_Msk                         /*!<Initial Reference Trigger Offset          */

+#define FDCAN_TTOCF_EECS_Pos      (15U)

+#define FDCAN_TTOCF_EECS_Msk      (0x1UL << FDCAN_TTOCF_EECS_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTOCF_EECS          FDCAN_TTOCF_EECS_Msk                         /*!<Enable External Clock Synchronization     */

+#define FDCAN_TTOCF_AWL_Pos       (16U)

+#define FDCAN_TTOCF_AWL_Msk       (0xFFUL << FDCAN_TTOCF_AWL_Pos)              /*!< 0x00FF0000 */

+#define FDCAN_TTOCF_AWL           FDCAN_TTOCF_AWL_Msk                          /*!<Application Watchdog Limit                */

+#define FDCAN_TTOCF_EGTF_Pos      (24U)

+#define FDCAN_TTOCF_EGTF_Msk      (0x1UL << FDCAN_TTOCF_EGTF_Pos)              /*!< 0x01000000 */

+#define FDCAN_TTOCF_EGTF          FDCAN_TTOCF_EGTF_Msk                         /*!<Enable Global Time Filtering              */

+#define FDCAN_TTOCF_ECC_Pos       (25U)

+#define FDCAN_TTOCF_ECC_Msk       (0x1UL << FDCAN_TTOCF_ECC_Pos)               /*!< 0x02000000 */

+#define FDCAN_TTOCF_ECC           FDCAN_TTOCF_ECC_Msk                          /*!<Enable Clock Calibration                  */

+#define FDCAN_TTOCF_EVTP_Pos      (26U)

+#define FDCAN_TTOCF_EVTP_Msk      (0x1UL << FDCAN_TTOCF_EVTP_Pos)              /*!< 0x04000000 */

+#define FDCAN_TTOCF_EVTP          FDCAN_TTOCF_EVTP_Msk                         /*!<Event Trigger Polarity                    */

+

+/*****************  Bit definition for FDCAN_TTMLM register  *********************/

+#define FDCAN_TTMLM_CCM_Pos       (0U)

+#define FDCAN_TTMLM_CCM_Msk       (0x3FUL << FDCAN_TTMLM_CCM_Pos)              /*!< 0x0000003F */

+#define FDCAN_TTMLM_CCM           FDCAN_TTMLM_CCM_Msk                          /*!<Cycle Count Max                           */

+#define FDCAN_TTMLM_CSS_Pos       (6U)

+#define FDCAN_TTMLM_CSS_Msk       (0x3UL << FDCAN_TTMLM_CSS_Pos)               /*!< 0x000000C0 */

+#define FDCAN_TTMLM_CSS           FDCAN_TTMLM_CSS_Msk                          /*!<Cycle Start Synchronization               */

+#define FDCAN_TTMLM_TXEW_Pos      (8U)

+#define FDCAN_TTMLM_TXEW_Msk      (0xFUL << FDCAN_TTMLM_TXEW_Pos)              /*!< 0x00000F00 */

+#define FDCAN_TTMLM_TXEW          FDCAN_TTMLM_TXEW_Msk                         /*!<Tx Enable Window                          */

+#define FDCAN_TTMLM_ENTT_Pos      (16U)

+#define FDCAN_TTMLM_ENTT_Msk      (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)            /*!< 0x0FFF0000 */

+#define FDCAN_TTMLM_ENTT          FDCAN_TTMLM_ENTT_Msk                         /*!<Expected Number of Tx Triggers            */

+

+/*****************  Bit definition for FDCAN_TURCF register  *********************/

+#define FDCAN_TURCF_NCL_Pos       (0U)

+#define FDCAN_TURCF_NCL_Msk       (0xFFFFUL << FDCAN_TURCF_NCL_Pos)            /*!< 0x0000FFFF */

+#define FDCAN_TURCF_NCL           FDCAN_TURCF_NCL_Msk                          /*!<Numerator Configuration Low               */

+#define FDCAN_TURCF_DC_Pos        (16U)

+#define FDCAN_TURCF_DC_Msk        (0x3FFFUL << FDCAN_TURCF_DC_Pos)             /*!< 0x3FFF0000 */

+#define FDCAN_TURCF_DC            FDCAN_TURCF_DC_Msk                           /*!<Denominator Configuration                 */

+#define FDCAN_TURCF_ELT_Pos       (31U)

+#define FDCAN_TURCF_ELT_Msk       (0x1UL << FDCAN_TURCF_ELT_Pos)               /*!< 0x80000000 */

+#define FDCAN_TURCF_ELT           FDCAN_TURCF_ELT_Msk                          /*!<Enable Local Time                         */

+

+/*****************  Bit definition for FDCAN_TTOCN register  ********************/

+#define FDCAN_TTOCN_SGT_Pos       (0U)

+#define FDCAN_TTOCN_SGT_Msk       (0x1UL << FDCAN_TTOCN_SGT_Pos)               /*!< 0x00000001 */

+#define FDCAN_TTOCN_SGT           FDCAN_TTOCN_SGT_Msk                          /*!<Set Global time                           */

+#define FDCAN_TTOCN_ECS_Pos       (1U)

+#define FDCAN_TTOCN_ECS_Msk       (0x1UL << FDCAN_TTOCN_ECS_Pos)               /*!< 0x00000002 */

+#define FDCAN_TTOCN_ECS           FDCAN_TTOCN_ECS_Msk                          /*!<External Clock Synchronization            */

+#define FDCAN_TTOCN_SWP_Pos       (2U)

+#define FDCAN_TTOCN_SWP_Msk       (0x1UL << FDCAN_TTOCN_SWP_Pos)               /*!< 0x00000004 */

+#define FDCAN_TTOCN_SWP           FDCAN_TTOCN_SWP_Msk                          /*!<Stop Watch Polarity                       */

+#define FDCAN_TTOCN_SWS_Pos       (3U)

+#define FDCAN_TTOCN_SWS_Msk       (0x3UL << FDCAN_TTOCN_SWS_Pos)               /*!< 0x00000018 */

+#define FDCAN_TTOCN_SWS           FDCAN_TTOCN_SWS_Msk                          /*!<Stop Watch Source                         */

+#define FDCAN_TTOCN_RTIE_Pos      (5U)

+#define FDCAN_TTOCN_RTIE_Msk      (0x1UL << FDCAN_TTOCN_RTIE_Pos)              /*!< 0x00000020 */

+#define FDCAN_TTOCN_RTIE          FDCAN_TTOCN_RTIE_Msk                         /*!<Register Time Mark Interrupt Pulse Enable */

+#define FDCAN_TTOCN_TMC_Pos       (6U)

+#define FDCAN_TTOCN_TMC_Msk       (0x3UL << FDCAN_TTOCN_TMC_Pos)               /*!< 0x000000C0 */

+#define FDCAN_TTOCN_TMC           FDCAN_TTOCN_TMC_Msk                          /*!<Register Time Mark Compare                */

+#define FDCAN_TTOCN_TTIE_Pos      (8U)

+#define FDCAN_TTOCN_TTIE_Msk      (0x1UL << FDCAN_TTOCN_TTIE_Pos)              /*!< 0x00000100 */

+#define FDCAN_TTOCN_TTIE          FDCAN_TTOCN_TTIE_Msk                         /*!<Trigger Time Mark Interrupt Pulse Enable  */

+#define FDCAN_TTOCN_GCS_Pos       (9U)

+#define FDCAN_TTOCN_GCS_Msk       (0x1UL << FDCAN_TTOCN_GCS_Pos)               /*!< 0x00000200 */

+#define FDCAN_TTOCN_GCS           FDCAN_TTOCN_GCS_Msk                          /*!<Gap Control Select                        */

+#define FDCAN_TTOCN_FGP_Pos       (10U)

+#define FDCAN_TTOCN_FGP_Msk       (0x1UL << FDCAN_TTOCN_FGP_Pos)               /*!< 0x00000400 */

+#define FDCAN_TTOCN_FGP           FDCAN_TTOCN_FGP_Msk                          /*!<Finish Gap                                */

+#define FDCAN_TTOCN_TMG_Pos       (11U)

+#define FDCAN_TTOCN_TMG_Msk       (0x1UL << FDCAN_TTOCN_TMG_Pos)               /*!< 0x00000800 */

+#define FDCAN_TTOCN_TMG           FDCAN_TTOCN_TMG_Msk                          /*!<Time Mark Gap                             */

+#define FDCAN_TTOCN_NIG_Pos       (12U)

+#define FDCAN_TTOCN_NIG_Msk       (0x1UL << FDCAN_TTOCN_NIG_Pos)               /*!< 0x00001000 */

+#define FDCAN_TTOCN_NIG           FDCAN_TTOCN_NIG_Msk                          /*!<Next is Gap                               */

+#define FDCAN_TTOCN_ESCN_Pos      (13U)

+#define FDCAN_TTOCN_ESCN_Msk      (0x1UL << FDCAN_TTOCN_ESCN_Pos)              /*!< 0x00002000 */

+#define FDCAN_TTOCN_ESCN          FDCAN_TTOCN_ESCN_Msk                         /*!<External Synchronization Control          */

+#define FDCAN_TTOCN_LCKC_Pos      (15U)

+#define FDCAN_TTOCN_LCKC_Msk      (0x1UL << FDCAN_TTOCN_LCKC_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTOCN_LCKC          FDCAN_TTOCN_LCKC_Msk                         /*!<TT Operation Control Register Locked      */

+

+/*****************  Bit definition for FDCAN_TTGTP register  ********************/

+#define FDCAN_TTGTP_TP_Pos        (0U)

+#define FDCAN_TTGTP_TP_Msk        (0xFFFFUL << FDCAN_TTGTP_TP_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTGTP_TP            FDCAN_TTGTP_TP_Msk                           /*!<Time Preset                               */

+#define FDCAN_TTGTP_CTP_Pos       (16U)

+#define FDCAN_TTGTP_CTP_Msk       (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)            /*!< 0xFFFF0000 */

+#define FDCAN_TTGTP_CTP           FDCAN_TTGTP_CTP_Msk                          /*!<Cycle Time Target Phase                   */

+

+/*****************  Bit definition for FDCAN_TTTMK register  ********************/

+#define FDCAN_TTTMK_TM_Pos        (0U)

+#define FDCAN_TTTMK_TM_Msk        (0xFFFFUL << FDCAN_TTTMK_TM_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTTMK_TM            FDCAN_TTTMK_TM_Msk                           /*!<Time Mark                                 */

+#define FDCAN_TTTMK_TICC_Pos      (16U)

+#define FDCAN_TTTMK_TICC_Msk      (0x7FUL << FDCAN_TTTMK_TICC_Pos)             /*!< 0x007F0000 */

+#define FDCAN_TTTMK_TICC          FDCAN_TTTMK_TICC_Msk                         /*!<Time Mark Cycle Code                      */

+#define FDCAN_TTTMK_LCKM_Pos      (31U)

+#define FDCAN_TTTMK_LCKM_Msk      (0x1UL << FDCAN_TTTMK_LCKM_Pos)              /*!< 0x80000000 */

+#define FDCAN_TTTMK_LCKM          FDCAN_TTTMK_LCKM_Msk                         /*!<TT Time Mark Register Locked              */

+

+/*****************  Bit definition for FDCAN_TTIR register  ********************/

+#define FDCAN_TTIR_SBC_Pos        (0U)

+#define FDCAN_TTIR_SBC_Msk        (0x1UL << FDCAN_TTIR_SBC_Pos)                /*!< 0x00000001 */

+#define FDCAN_TTIR_SBC            FDCAN_TTIR_SBC_Msk                           /*!<Start of Basic Cycle                      */

+#define FDCAN_TTIR_SMC_Pos        (1U)

+#define FDCAN_TTIR_SMC_Msk        (0x1UL << FDCAN_TTIR_SMC_Pos)                /*!< 0x00000002 */

+#define FDCAN_TTIR_SMC            FDCAN_TTIR_SMC_Msk                           /*!<Start of Matrix Cycle                     */

+#define FDCAN_TTIR_CSM_Pos        (2U)

+#define FDCAN_TTIR_CSM_Msk        (0x1UL << FDCAN_TTIR_CSM_Pos)                /*!< 0x00000004 */

+#define FDCAN_TTIR_CSM            FDCAN_TTIR_CSM_Msk                           /*!<Change of Synchronization Mode            */

+#define FDCAN_TTIR_SOG_Pos        (3U)

+#define FDCAN_TTIR_SOG_Msk        (0x1UL << FDCAN_TTIR_SOG_Pos)                /*!< 0x00000008 */

+#define FDCAN_TTIR_SOG            FDCAN_TTIR_SOG_Msk                           /*!<Start of Gap                              */

+#define FDCAN_TTIR_RTMI_Pos       (4U)

+#define FDCAN_TTIR_RTMI_Msk       (0x1UL << FDCAN_TTIR_RTMI_Pos)               /*!< 0x00000010 */

+#define FDCAN_TTIR_RTMI           FDCAN_TTIR_RTMI_Msk                          /*!<Register Time Mark Interrupt              */

+#define FDCAN_TTIR_TTMI_Pos       (5U)

+#define FDCAN_TTIR_TTMI_Msk       (0x1UL << FDCAN_TTIR_TTMI_Pos)               /*!< 0x00000020 */

+#define FDCAN_TTIR_TTMI           FDCAN_TTIR_TTMI_Msk                          /*!<Trigger Time Mark Event Internal          */

+#define FDCAN_TTIR_SWE_Pos        (6U)

+#define FDCAN_TTIR_SWE_Msk        (0x1UL << FDCAN_TTIR_SWE_Pos)                /*!< 0x00000040 */

+#define FDCAN_TTIR_SWE            FDCAN_TTIR_SWE_Msk                           /*!<Stop Watch Event                          */

+#define FDCAN_TTIR_GTW_Pos        (7U)

+#define FDCAN_TTIR_GTW_Msk        (0x1UL << FDCAN_TTIR_GTW_Pos)                /*!< 0x00000080 */

+#define FDCAN_TTIR_GTW            FDCAN_TTIR_GTW_Msk                           /*!<Global Time Wrap                          */

+#define FDCAN_TTIR_GTD_Pos        (8U)

+#define FDCAN_TTIR_GTD_Msk        (0x1UL << FDCAN_TTIR_GTD_Pos)                /*!< 0x00000100 */

+#define FDCAN_TTIR_GTD            FDCAN_TTIR_GTD_Msk                           /*!<Global Time Discontinuity                 */

+#define FDCAN_TTIR_GTE_Pos        (9U)

+#define FDCAN_TTIR_GTE_Msk        (0x1UL << FDCAN_TTIR_GTE_Pos)                /*!< 0x00000200 */

+#define FDCAN_TTIR_GTE            FDCAN_TTIR_GTE_Msk                           /*!<Global Time Error                         */

+#define FDCAN_TTIR_TXU_Pos        (10U)

+#define FDCAN_TTIR_TXU_Msk        (0x1UL << FDCAN_TTIR_TXU_Pos)                /*!< 0x00000400 */

+#define FDCAN_TTIR_TXU            FDCAN_TTIR_TXU_Msk                           /*!<Tx Count Underflow                        */

+#define FDCAN_TTIR_TXO_Pos        (11U)

+#define FDCAN_TTIR_TXO_Msk        (0x1UL << FDCAN_TTIR_TXO_Pos)                /*!< 0x00000800 */

+#define FDCAN_TTIR_TXO            FDCAN_TTIR_TXO_Msk                           /*!<Tx Count Overflow                         */

+#define FDCAN_TTIR_SE1_Pos        (12U)

+#define FDCAN_TTIR_SE1_Msk        (0x1UL << FDCAN_TTIR_SE1_Pos)                /*!< 0x00001000 */

+#define FDCAN_TTIR_SE1            FDCAN_TTIR_SE1_Msk                           /*!<Scheduling Error 1                        */

+#define FDCAN_TTIR_SE2_Pos        (13U)

+#define FDCAN_TTIR_SE2_Msk        (0x1UL << FDCAN_TTIR_SE2_Pos)                /*!< 0x00002000 */

+#define FDCAN_TTIR_SE2            FDCAN_TTIR_SE2_Msk                           /*!<Scheduling Error 2                        */

+#define FDCAN_TTIR_ELC_Pos        (14U)

+#define FDCAN_TTIR_ELC_Msk        (0x1UL << FDCAN_TTIR_ELC_Pos)                /*!< 0x00004000 */

+#define FDCAN_TTIR_ELC            FDCAN_TTIR_ELC_Msk                           /*!<Error Level Changed                       */

+#define FDCAN_TTIR_IWT_Pos        (15U)

+#define FDCAN_TTIR_IWT_Msk        (0x1UL << FDCAN_TTIR_IWT_Pos)                /*!< 0x00008000 */

+#define FDCAN_TTIR_IWT            FDCAN_TTIR_IWT_Msk                           /*!<Initialization Watch Trigger              */

+#define FDCAN_TTIR_WT_Pos         (16U)

+#define FDCAN_TTIR_WT_Msk         (0x1UL << FDCAN_TTIR_WT_Pos)                 /*!< 0x00010000 */

+#define FDCAN_TTIR_WT             FDCAN_TTIR_WT_Msk                            /*!<Watch Trigger                             */

+#define FDCAN_TTIR_AW_Pos         (17U)

+#define FDCAN_TTIR_AW_Msk         (0x1UL << FDCAN_TTIR_AW_Pos)                 /*!< 0x00020000 */

+#define FDCAN_TTIR_AW             FDCAN_TTIR_AW_Msk                            /*!<Application Watchdog                      */

+#define FDCAN_TTIR_CER_Pos        (18U)

+#define FDCAN_TTIR_CER_Msk        (0x1UL << FDCAN_TTIR_CER_Pos)                /*!< 0x00040000 */

+#define FDCAN_TTIR_CER            FDCAN_TTIR_CER_Msk                           /*!<Configuration Error                       */

+

+/*****************  Bit definition for FDCAN_TTIE register  ********************/

+#define FDCAN_TTIE_SBCE_Pos       (0U)

+#define FDCAN_TTIE_SBCE_Msk       (0x1UL << FDCAN_TTIE_SBCE_Pos)               /*!< 0x00000001 */

+#define FDCAN_TTIE_SBCE           FDCAN_TTIE_SBCE_Msk                          /*!<Start of Basic Cycle Interrupt Enable             */

+#define FDCAN_TTIE_SMCE_Pos       (1U)

+#define FDCAN_TTIE_SMCE_Msk       (0x1UL << FDCAN_TTIE_SMCE_Pos)               /*!< 0x00000002 */

+#define FDCAN_TTIE_SMCE           FDCAN_TTIE_SMCE_Msk                          /*!<Start of Matrix Cycle Interrupt Enable            */

+#define FDCAN_TTIE_CSME_Pos       (2U)

+#define FDCAN_TTIE_CSME_Msk       (0x1UL << FDCAN_TTIE_CSME_Pos)               /*!< 0x00000004 */

+#define FDCAN_TTIE_CSME           FDCAN_TTIE_CSME_Msk                          /*!<Change of Synchronization Mode Interrupt Enable   */

+#define FDCAN_TTIE_SOGE_Pos       (3U)

+#define FDCAN_TTIE_SOGE_Msk       (0x1UL << FDCAN_TTIE_SOGE_Pos)               /*!< 0x00000008 */

+#define FDCAN_TTIE_SOGE           FDCAN_TTIE_SOGE_Msk                          /*!<Start of Gap Interrupt Enable                     */

+#define FDCAN_TTIE_RTMIE_Pos      (4U)

+#define FDCAN_TTIE_RTMIE_Msk      (0x1UL << FDCAN_TTIE_RTMIE_Pos)              /*!< 0x00000010 */

+#define FDCAN_TTIE_RTMIE          FDCAN_TTIE_RTMIE_Msk                         /*!<Register Time Mark Interrupt Interrupt Enable     */

+#define FDCAN_TTIE_TTMIE_Pos      (5U)

+#define FDCAN_TTIE_TTMIE_Msk      (0x1UL << FDCAN_TTIE_TTMIE_Pos)              /*!< 0x00000020 */

+#define FDCAN_TTIE_TTMIE          FDCAN_TTIE_TTMIE_Msk                         /*!<Trigger Time Mark Event Internal Interrupt Enable */

+#define FDCAN_TTIE_SWEE_Pos       (6U)

+#define FDCAN_TTIE_SWEE_Msk       (0x1UL << FDCAN_TTIE_SWEE_Pos)               /*!< 0x00000040 */

+#define FDCAN_TTIE_SWEE           FDCAN_TTIE_SWEE_Msk                          /*!<Stop Watch Event Interrupt Enable                 */

+#define FDCAN_TTIE_GTWE_Pos       (7U)

+#define FDCAN_TTIE_GTWE_Msk       (0x1UL << FDCAN_TTIE_GTWE_Pos)               /*!< 0x00000080 */

+#define FDCAN_TTIE_GTWE           FDCAN_TTIE_GTWE_Msk                          /*!<Global Time Wrap Interrupt Enable                 */

+#define FDCAN_TTIE_GTDE_Pos       (8U)

+#define FDCAN_TTIE_GTDE_Msk       (0x1UL << FDCAN_TTIE_GTDE_Pos)               /*!< 0x00000100 */

+#define FDCAN_TTIE_GTDE           FDCAN_TTIE_GTDE_Msk                          /*!<Global Time Discontinuity Interrupt Enable        */

+#define FDCAN_TTIE_GTEE_Pos       (9U)

+#define FDCAN_TTIE_GTEE_Msk       (0x1UL << FDCAN_TTIE_GTEE_Pos)               /*!< 0x00000200 */

+#define FDCAN_TTIE_GTEE           FDCAN_TTIE_GTEE_Msk                          /*!<Global Time Error Interrupt Enable                */

+#define FDCAN_TTIE_TXUE_Pos       (10U)

+#define FDCAN_TTIE_TXUE_Msk       (0x1UL << FDCAN_TTIE_TXUE_Pos)               /*!< 0x00000400 */

+#define FDCAN_TTIE_TXUE           FDCAN_TTIE_TXUE_Msk                          /*!<Tx Count Underflow Interrupt Enable               */

+#define FDCAN_TTIE_TXOE_Pos       (11U)

+#define FDCAN_TTIE_TXOE_Msk       (0x1UL << FDCAN_TTIE_TXOE_Pos)               /*!< 0x00000800 */

+#define FDCAN_TTIE_TXOE           FDCAN_TTIE_TXOE_Msk                          /*!<Tx Count Overflow Interrupt Enable                */

+#define FDCAN_TTIE_SE1E_Pos       (12U)

+#define FDCAN_TTIE_SE1E_Msk       (0x1UL << FDCAN_TTIE_SE1E_Pos)               /*!< 0x00001000 */

+#define FDCAN_TTIE_SE1E           FDCAN_TTIE_SE1E_Msk                          /*!<Scheduling Error 1 Interrupt Enable               */

+#define FDCAN_TTIE_SE2E_Pos       (13U)

+#define FDCAN_TTIE_SE2E_Msk       (0x1UL << FDCAN_TTIE_SE2E_Pos)               /*!< 0x00002000 */

+#define FDCAN_TTIE_SE2E           FDCAN_TTIE_SE2E_Msk                          /*!<Scheduling Error 2 Interrupt Enable               */

+#define FDCAN_TTIE_ELCE_Pos       (14U)

+#define FDCAN_TTIE_ELCE_Msk       (0x1UL << FDCAN_TTIE_ELCE_Pos)               /*!< 0x00004000 */

+#define FDCAN_TTIE_ELCE           FDCAN_TTIE_ELCE_Msk                          /*!<Error Level Changed Interrupt Enable              */

+#define FDCAN_TTIE_IWTE_Pos       (15U)

+#define FDCAN_TTIE_IWTE_Msk       (0x1UL << FDCAN_TTIE_IWTE_Pos)               /*!< 0x00008000 */

+#define FDCAN_TTIE_IWTE           FDCAN_TTIE_IWTE_Msk                          /*!<Initialization Watch Trigger Interrupt Enable     */

+#define FDCAN_TTIE_WTE_Pos        (16U)

+#define FDCAN_TTIE_WTE_Msk        (0x1UL << FDCAN_TTIE_WTE_Pos)                /*!< 0x00010000 */

+#define FDCAN_TTIE_WTE            FDCAN_TTIE_WTE_Msk                           /*!<Watch Trigger Interrupt Enable                    */

+#define FDCAN_TTIE_AWE_Pos        (17U)

+#define FDCAN_TTIE_AWE_Msk        (0x1UL << FDCAN_TTIE_AWE_Pos)                /*!< 0x00020000 */

+#define FDCAN_TTIE_AWE            FDCAN_TTIE_AWE_Msk                           /*!<Application Watchdog Interrupt Enable             */

+#define FDCAN_TTIE_CERE_Pos       (18U)

+#define FDCAN_TTIE_CERE_Msk       (0x1UL << FDCAN_TTIE_CERE_Pos)               /*!< 0x00040000 */

+#define FDCAN_TTIE_CERE           FDCAN_TTIE_CERE_Msk                          /*!<Configuration Error Interrupt Enable              */

+

+/*****************  Bit definition for FDCAN_TTILS register  ********************/

+#define FDCAN_TTILS_SBCS_Pos      (0U)

+#define FDCAN_TTILS_SBCS_Msk      (0x1UL << FDCAN_TTILS_SBCS_Pos)              /*!< 0x00000001 */

+#define FDCAN_TTILS_SBCS          FDCAN_TTILS_SBCS_Msk                         /*!<Start of Basic Cycle Interrupt Line               */

+#define FDCAN_TTILS_SMCS_Pos      (1U)

+#define FDCAN_TTILS_SMCS_Msk      (0x1UL << FDCAN_TTILS_SMCS_Pos)              /*!< 0x00000002 */

+#define FDCAN_TTILS_SMCS          FDCAN_TTILS_SMCS_Msk                         /*!<Start of Matrix Cycle Interrupt Line              */

+#define FDCAN_TTILS_CSMS_Pos      (2U)

+#define FDCAN_TTILS_CSMS_Msk      (0x1UL << FDCAN_TTILS_CSMS_Pos)              /*!< 0x00000004 */

+#define FDCAN_TTILS_CSMS          FDCAN_TTILS_CSMS_Msk                         /*!<Change of Synchronization Mode Interrupt Line     */

+#define FDCAN_TTILS_SOGS_Pos      (3U)

+#define FDCAN_TTILS_SOGS_Msk      (0x1UL << FDCAN_TTILS_SOGS_Pos)              /*!< 0x00000008 */

+#define FDCAN_TTILS_SOGS          FDCAN_TTILS_SOGS_Msk                         /*!<Start of Gap Interrupt Line                       */

+#define FDCAN_TTILS_RTMIS_Pos     (4U)

+#define FDCAN_TTILS_RTMIS_Msk     (0x1UL << FDCAN_TTILS_RTMIS_Pos)             /*!< 0x00000010 */

+#define FDCAN_TTILS_RTMIS         FDCAN_TTILS_RTMIS_Msk                        /*!<Register Time Mark Interrupt Interrupt Line       */

+#define FDCAN_TTILS_TTMIS_Pos     (5U)

+#define FDCAN_TTILS_TTMIS_Msk     (0x1UL << FDCAN_TTILS_TTMIS_Pos)             /*!< 0x00000020 */

+#define FDCAN_TTILS_TTMIS         FDCAN_TTILS_TTMIS_Msk                        /*!<Trigger Time Mark Event Internal Interrupt Line   */

+#define FDCAN_TTILS_SWES_Pos      (6U)

+#define FDCAN_TTILS_SWES_Msk      (0x1UL << FDCAN_TTILS_SWES_Pos)              /*!< 0x00000040 */

+#define FDCAN_TTILS_SWES          FDCAN_TTILS_SWES_Msk                         /*!<Stop Watch Event Interrupt Line                   */

+#define FDCAN_TTILS_GTWS_Pos      (7U)

+#define FDCAN_TTILS_GTWS_Msk      (0x1UL << FDCAN_TTILS_GTWS_Pos)              /*!< 0x00000080 */

+#define FDCAN_TTILS_GTWS          FDCAN_TTILS_GTWS_Msk                         /*!<Global Time Wrap Interrupt Line                   */

+#define FDCAN_TTILS_GTDS_Pos      (8U)

+#define FDCAN_TTILS_GTDS_Msk      (0x1UL << FDCAN_TTILS_GTDS_Pos)              /*!< 0x00000100 */

+#define FDCAN_TTILS_GTDS          FDCAN_TTILS_GTDS_Msk                         /*!<Global Time Discontinuity Interrupt Line          */

+#define FDCAN_TTILS_GTES_Pos      (9U)

+#define FDCAN_TTILS_GTES_Msk      (0x1UL << FDCAN_TTILS_GTES_Pos)              /*!< 0x00000200 */

+#define FDCAN_TTILS_GTES          FDCAN_TTILS_GTES_Msk                         /*!<Global Time Error Interrupt Line                  */

+#define FDCAN_TTILS_TXUS_Pos      (10U)

+#define FDCAN_TTILS_TXUS_Msk      (0x1UL << FDCAN_TTILS_TXUS_Pos)              /*!< 0x00000400 */

+#define FDCAN_TTILS_TXUS          FDCAN_TTILS_TXUS_Msk                         /*!<Tx Count Underflow Interrupt Line                 */

+#define FDCAN_TTILS_TXOS_Pos      (11U)

+#define FDCAN_TTILS_TXOS_Msk      (0x1UL << FDCAN_TTILS_TXOS_Pos)              /*!< 0x00000800 */

+#define FDCAN_TTILS_TXOS          FDCAN_TTILS_TXOS_Msk                         /*!<Tx Count Overflow Interrupt Line                  */

+#define FDCAN_TTILS_SE1S_Pos      (12U)

+#define FDCAN_TTILS_SE1S_Msk      (0x1UL << FDCAN_TTILS_SE1S_Pos)              /*!< 0x00001000 */

+#define FDCAN_TTILS_SE1S          FDCAN_TTILS_SE1S_Msk                         /*!<Scheduling Error 1 Interrupt Line                 */

+#define FDCAN_TTILS_SE2S_Pos      (13U)

+#define FDCAN_TTILS_SE2S_Msk      (0x1UL << FDCAN_TTILS_SE2S_Pos)              /*!< 0x00002000 */

+#define FDCAN_TTILS_SE2S          FDCAN_TTILS_SE2S_Msk                         /*!<Scheduling Error 2 Interrupt Line                 */

+#define FDCAN_TTILS_ELCS_Pos      (14U)

+#define FDCAN_TTILS_ELCS_Msk      (0x1UL << FDCAN_TTILS_ELCS_Pos)              /*!< 0x00004000 */

+#define FDCAN_TTILS_ELCS          FDCAN_TTILS_ELCS_Msk                         /*!<Error Level Changed Interrupt Line                */

+#define FDCAN_TTILS_IWTS_Pos      (15U)

+#define FDCAN_TTILS_IWTS_Msk      (0x1UL << FDCAN_TTILS_IWTS_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTILS_IWTS          FDCAN_TTILS_IWTS_Msk                         /*!<Initialization Watch Trigger Interrupt Line       */

+#define FDCAN_TTILS_WTS_Pos       (16U)

+#define FDCAN_TTILS_WTS_Msk       (0x1UL << FDCAN_TTILS_WTS_Pos)               /*!< 0x00010000 */

+#define FDCAN_TTILS_WTS           FDCAN_TTILS_WTS_Msk                          /*!<Watch Trigger Interrupt Line                      */

+#define FDCAN_TTILS_AWS_Pos       (17U)

+#define FDCAN_TTILS_AWS_Msk       (0x1UL << FDCAN_TTILS_AWS_Pos)               /*!< 0x00020000 */

+#define FDCAN_TTILS_AWS           FDCAN_TTILS_AWS_Msk                          /*!<Application Watchdog Interrupt Line               */

+#define FDCAN_TTILS_CERS_Pos      (18U)

+#define FDCAN_TTILS_CERS_Msk      (0x1UL << FDCAN_TTILS_CERS_Pos)              /*!< 0x00040000 */

+#define FDCAN_TTILS_CERS          FDCAN_TTILS_CERS_Msk                         /*!<Configuration Error Interrupt Line                */

+

+/*****************  Bit definition for FDCAN_TTOST register  ********************/

+#define FDCAN_TTOST_EL_Pos        (0U)

+#define FDCAN_TTOST_EL_Msk        (0x3UL << FDCAN_TTOST_EL_Pos)                /*!< 0x00000003 */

+#define FDCAN_TTOST_EL            FDCAN_TTOST_EL_Msk                           /*!<Error Level                              */

+#define FDCAN_TTOST_MS_Pos        (2U)

+#define FDCAN_TTOST_MS_Msk        (0x3UL << FDCAN_TTOST_MS_Pos)                /*!< 0x0000000C */

+#define FDCAN_TTOST_MS            FDCAN_TTOST_MS_Msk                           /*!<Master State                             */

+#define FDCAN_TTOST_SYS_Pos       (4U)

+#define FDCAN_TTOST_SYS_Msk       (0x3UL << FDCAN_TTOST_SYS_Pos)               /*!< 0x00000030 */

+#define FDCAN_TTOST_SYS           FDCAN_TTOST_SYS_Msk                          /*!<Synchronization State                    */

+#define FDCAN_TTOST_QGTP_Pos      (6U)

+#define FDCAN_TTOST_QGTP_Msk      (0x1UL << FDCAN_TTOST_QGTP_Pos)              /*!< 0x00000040 */

+#define FDCAN_TTOST_QGTP          FDCAN_TTOST_QGTP_Msk                         /*!<Quality of Global Time Phase             */

+#define FDCAN_TTOST_QCS_Pos       (7U)

+#define FDCAN_TTOST_QCS_Msk       (0x1UL << FDCAN_TTOST_QCS_Pos)               /*!< 0x00000080 */

+#define FDCAN_TTOST_QCS           FDCAN_TTOST_QCS_Msk                          /*!<Quality of Clock Speed                   */

+#define FDCAN_TTOST_RTO_Pos       (8U)

+#define FDCAN_TTOST_RTO_Msk       (0xFFUL << FDCAN_TTOST_RTO_Pos)              /*!< 0x0000FF00 */

+#define FDCAN_TTOST_RTO           FDCAN_TTOST_RTO_Msk                          /*!<Reference Trigger Offset                 */

+#define FDCAN_TTOST_WGTD_Pos      (22U)

+#define FDCAN_TTOST_WGTD_Msk      (0x1UL << FDCAN_TTOST_WGTD_Pos)              /*!< 0x00400000 */

+#define FDCAN_TTOST_WGTD          FDCAN_TTOST_WGTD_Msk                         /*!<Wait for Global Time Discontinuity       */

+#define FDCAN_TTOST_GFI_Pos       (23U)

+#define FDCAN_TTOST_GFI_Msk       (0x1UL << FDCAN_TTOST_GFI_Pos)               /*!< 0x00800000 */

+#define FDCAN_TTOST_GFI           FDCAN_TTOST_GFI_Msk                          /*!<Gap Finished Indicator                   */

+#define FDCAN_TTOST_TMP_Pos       (24U)

+#define FDCAN_TTOST_TMP_Msk       (0x7UL << FDCAN_TTOST_TMP_Pos)               /*!< 0x07000000 */

+#define FDCAN_TTOST_TMP           FDCAN_TTOST_TMP_Msk                          /*!<Time Master Priority                     */

+#define FDCAN_TTOST_GSI_Pos       (27U)

+#define FDCAN_TTOST_GSI_Msk       (0x1UL << FDCAN_TTOST_GSI_Pos)               /*!< 0x08000000 */

+#define FDCAN_TTOST_GSI           FDCAN_TTOST_GSI_Msk                          /*!<Gap Started Indicator                    */

+#define FDCAN_TTOST_WFE_Pos       (28U)

+#define FDCAN_TTOST_WFE_Msk       (0x1UL << FDCAN_TTOST_WFE_Pos)               /*!< 0x10000000 */

+#define FDCAN_TTOST_WFE           FDCAN_TTOST_WFE_Msk                          /*!<Wait for Event                           */

+#define FDCAN_TTOST_AWE_Pos       (29U)

+#define FDCAN_TTOST_AWE_Msk       (0x1UL << FDCAN_TTOST_AWE_Pos)               /*!< 0x20000000 */

+#define FDCAN_TTOST_AWE           FDCAN_TTOST_AWE_Msk                          /*!<Application Watchdog Event               */

+#define FDCAN_TTOST_WECS_Pos      (30U)

+#define FDCAN_TTOST_WECS_Msk      (0x1UL << FDCAN_TTOST_WECS_Pos)              /*!< 0x40000000 */

+#define FDCAN_TTOST_WECS          FDCAN_TTOST_WECS_Msk                         /*!<Wait for External Clock Synchronization  */

+#define FDCAN_TTOST_SPL_Pos       (31U)

+#define FDCAN_TTOST_SPL_Msk       (0x1UL << FDCAN_TTOST_SPL_Pos)               /*!< 0x80000000 */

+#define FDCAN_TTOST_SPL           FDCAN_TTOST_SPL_Msk                          /*!<Schedule Phase Lock                      */

+

+/*****************  Bit definition for FDCAN_TURNA register  ********************/

+#define FDCAN_TURNA_NAV_Pos       (0U)

+#define FDCAN_TURNA_NAV_Msk       (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)           /*!< 0x0003FFFF */

+#define FDCAN_TURNA_NAV           FDCAN_TURNA_NAV_Msk                          /*!<Numerator Actual Value                   */

+

+/*****************  Bit definition for FDCAN_TTLGT register  ********************/

+#define FDCAN_TTLGT_LT_Pos        (0U)

+#define FDCAN_TTLGT_LT_Msk        (0xFFFFUL << FDCAN_TTLGT_LT_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTLGT_LT            FDCAN_TTLGT_LT_Msk                           /*!<Local Time                               */

+#define FDCAN_TTLGT_GT_Pos        (16U)

+#define FDCAN_TTLGT_GT_Msk        (0xFFFFUL << FDCAN_TTLGT_GT_Pos)             /*!< 0xFFFF0000 */

+#define FDCAN_TTLGT_GT            FDCAN_TTLGT_GT_Msk                           /*!<Global Time                              */

+

+/*****************  Bit definition for FDCAN_TTCTC register  ********************/

+#define FDCAN_TTCTC_CT_Pos        (0U)

+#define FDCAN_TTCTC_CT_Msk        (0xFFFFUL << FDCAN_TTCTC_CT_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTCTC_CT            FDCAN_TTCTC_CT_Msk                           /*!<Cycle Time                               */

+#define FDCAN_TTCTC_CC_Pos        (16U)

+#define FDCAN_TTCTC_CC_Msk        (0x3FUL << FDCAN_TTCTC_CC_Pos)               /*!< 0x003F0000 */

+#define FDCAN_TTCTC_CC            FDCAN_TTCTC_CC_Msk                           /*!<Cycle Count                              */

+

+/*****************  Bit definition for FDCAN_TTCPT register  ********************/

+#define FDCAN_TTCPT_CCV_Pos       (0U)

+#define FDCAN_TTCPT_CCV_Msk       (0x3FUL << FDCAN_TTCPT_CCV_Pos)              /*!< 0x0000003F */

+#define FDCAN_TTCPT_CCV           FDCAN_TTCPT_CCV_Msk                          /*!<Cycle Count Value                        */

+#define FDCAN_TTCPT_SWV_Pos       (16U)

+#define FDCAN_TTCPT_SWV_Msk       (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)            /*!< 0xFFFF0000 */

+#define FDCAN_TTCPT_SWV           FDCAN_TTCPT_SWV_Msk                          /*!<Stop Watch Value                         */

+

+/*****************  Bit definition for FDCAN_TTCSM register  ********************/

+#define FDCAN_TTCSM_CSM_Pos       (0U)

+#define FDCAN_TTCSM_CSM_Msk       (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)            /*!< 0x0000FFFF */

+#define FDCAN_TTCSM_CSM           FDCAN_TTCSM_CSM_Msk                          /*!<Cycle Sync Mark                          */

+

+/*****************  Bit definition for FDCAN_TTTS register  *********************/

+#define FDCAN_TTTS_SWTSEL_Pos     (0U)

+#define FDCAN_TTTS_SWTSEL_Msk     (0x3UL << FDCAN_TTTS_SWTSEL_Pos)             /*!< 0x00000003 */

+#define FDCAN_TTTS_SWTSEL         FDCAN_TTTS_SWTSEL_Msk                        /*!<Stop watch trigger input selection       */

+#define FDCAN_TTTS_EVTSEL_Pos     (4U)

+#define FDCAN_TTTS_EVTSEL_Msk     (0x3UL << FDCAN_TTTS_EVTSEL_Pos)             /*!< 0x00000030 */

+#define FDCAN_TTTS_EVTSEL         FDCAN_TTTS_EVTSEL_Msk                        /*!<Event trigger input selection            */

+

+/********************************************************************************/

+/*                                                                              */

+/*                      FDCANCCU (Clock Calibration unit)                       */

+/*                                                                              */

+/********************************************************************************/

+

+/*****************  Bit definition for FDCANCCU_CREL register  ******************/

+#define FDCANCCU_CREL_DAY_Pos        (0U)

+#define FDCANCCU_CREL_DAY_Msk        (0xFFUL << FDCANCCU_CREL_DAY_Pos)         /*!< 0x000000FF */

+#define FDCANCCU_CREL_DAY            FDCANCCU_CREL_DAY_Msk                     /*!<Timestamp Day                           */

+#define FDCANCCU_CREL_MON_Pos        (8U)

+#define FDCANCCU_CREL_MON_Msk        (0xFFUL << FDCANCCU_CREL_MON_Pos)         /*!< 0x0000FF00 */

+#define FDCANCCU_CREL_MON            FDCANCCU_CREL_MON_Msk                     /*!<Timestamp Month                         */

+#define FDCANCCU_CREL_YEAR_Pos       (16U)

+#define FDCANCCU_CREL_YEAR_Msk       (0xFUL << FDCANCCU_CREL_YEAR_Pos)         /*!< 0x000F0000 */

+#define FDCANCCU_CREL_YEAR           FDCANCCU_CREL_YEAR_Msk                    /*!<Timestamp Year                          */

+#define FDCANCCU_CREL_SUBSTEP_Pos    (20U)

+#define FDCANCCU_CREL_SUBSTEP_Msk    (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)      /*!< 0x00F00000 */

+#define FDCANCCU_CREL_SUBSTEP        FDCANCCU_CREL_SUBSTEP_Msk                 /*!<Sub-step of Core release                */

+#define FDCANCCU_CREL_STEP_Pos       (24U)

+#define FDCANCCU_CREL_STEP_Msk       (0xFUL << FDCANCCU_CREL_STEP_Pos)         /*!< 0x0F000000 */

+#define FDCANCCU_CREL_STEP           FDCANCCU_CREL_STEP_Msk                    /*!<Step of Core release                    */

+#define FDCANCCU_CREL_REL_Pos        (28U)

+#define FDCANCCU_CREL_REL_Msk        (0xFUL << FDCANCCU_CREL_REL_Pos)          /*!< 0xF0000000 */

+#define FDCANCCU_CREL_REL            FDCANCCU_CREL_REL_Msk                     /*!<Core release                            */

+

+/*****************  Bit definition for FDCANCCU_CCFG register  ******************/

+#define FDCANCCU_CCFG_TQBT_Pos       (0U)

+#define FDCANCCU_CCFG_TQBT_Msk       (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)        /*!< 0x0000001F */

+#define FDCANCCU_CCFG_TQBT           FDCANCCU_CCFG_TQBT_Msk                    /*!<Time Quanta per Bit Time                */

+#define FDCANCCU_CCFG_BCC_Pos        (6U)

+#define FDCANCCU_CCFG_BCC_Msk        (0x1UL << FDCANCCU_CCFG_BCC_Pos)          /*!< 0x00000040 */

+#define FDCANCCU_CCFG_BCC            FDCANCCU_CCFG_BCC_Msk                     /*!<Bypass Clock Calibration                */

+#define FDCANCCU_CCFG_CFL_Pos        (7U)

+#define FDCANCCU_CCFG_CFL_Msk        (0x1UL << FDCANCCU_CCFG_CFL_Pos)          /*!< 0x00000080 */

+#define FDCANCCU_CCFG_CFL            FDCANCCU_CCFG_CFL_Msk                     /*!<Calibration Field Length                */

+#define FDCANCCU_CCFG_OCPM_Pos       (8U)

+#define FDCANCCU_CCFG_OCPM_Msk       (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)        /*!< 0x0000FF00 */

+#define FDCANCCU_CCFG_OCPM           FDCANCCU_CCFG_OCPM_Msk                    /*!<Oscillator Clock Periods Minimum        */

+#define FDCANCCU_CCFG_CDIV_Pos       (16U)

+#define FDCANCCU_CCFG_CDIV_Msk       (0xFUL << FDCANCCU_CCFG_CDIV_Pos)         /*!< 0x000F0000 */

+#define FDCANCCU_CCFG_CDIV           FDCANCCU_CCFG_CDIV_Msk                    /*!<Clock Divider                           */

+#define FDCANCCU_CCFG_SWR_Pos        (31U)

+#define FDCANCCU_CCFG_SWR_Msk        (0x1UL << FDCANCCU_CCFG_SWR_Pos)          /*!< 0x80000000 */

+#define FDCANCCU_CCFG_SWR            FDCANCCU_CCFG_SWR_Msk                     /*!<Software Reset                          */

+

+/*****************  Bit definition for FDCANCCU_CSTAT register  *****************/

+#define FDCANCCU_CSTAT_OCPC_Pos      (0U)

+#define FDCANCCU_CSTAT_OCPC_Msk      (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)    /*!< 0x0003FFFF */

+#define FDCANCCU_CSTAT_OCPC          FDCANCCU_CSTAT_OCPC_Msk                   /*!<Oscillator Clock Period Counter        */

+#define FDCANCCU_CSTAT_TQC_Pos       (18U)

+#define FDCANCCU_CSTAT_TQC_Msk       (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)       /*!< 0x1FFC0000 */

+#define FDCANCCU_CSTAT_TQC           FDCANCCU_CSTAT_TQC_Msk                    /*!<Time Quanta Counter                    */

+#define FDCANCCU_CSTAT_CALS_Pos      (30U)

+#define FDCANCCU_CSTAT_CALS_Msk      (0x3UL << FDCANCCU_CSTAT_CALS_Pos)        /*!< 0xC0000000 */

+#define FDCANCCU_CSTAT_CALS          FDCANCCU_CSTAT_CALS_Msk                   /*!<Calibration State                      */

+

+/******************  Bit definition for FDCANCCU_CWD register  ******************/

+#define FDCANCCU_CWD_WDC_Pos         (0U)

+#define FDCANCCU_CWD_WDC_Msk         (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)        /*!< 0x0000FFFF */

+#define FDCANCCU_CWD_WDC             FDCANCCU_CWD_WDC_Msk                      /*!<Watchdog Configuration                 */

+#define FDCANCCU_CWD_WDV_Pos         (16U)

+#define FDCANCCU_CWD_WDV_Msk         (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)        /*!< 0xFFFF0000 */

+#define FDCANCCU_CWD_WDV             FDCANCCU_CWD_WDV_Msk                      /*!<Watchdog Value                         */

+

+/******************  Bit definition for FDCANCCU_IR register  *******************/

+#define FDCANCCU_IR_CWE_Pos          (0U)

+#define FDCANCCU_IR_CWE_Msk          (0x1UL << FDCANCCU_IR_CWE_Pos)            /*!< 0x00000001 */

+#define FDCANCCU_IR_CWE              FDCANCCU_IR_CWE_Msk                       /*!<Calibration Watchdog Event             */

+#define FDCANCCU_IR_CSC_Pos          (1U)

+#define FDCANCCU_IR_CSC_Msk          (0x1UL << FDCANCCU_IR_CSC_Pos)            /*!< 0x00000002 */

+#define FDCANCCU_IR_CSC              FDCANCCU_IR_CSC_Msk                       /*!<Calibration State Changed              */

+

+/******************  Bit definition for FDCANCCU_IE register  *******************/

+#define FDCANCCU_IE_CWEE_Pos         (0U)

+#define FDCANCCU_IE_CWEE_Msk         (0x1UL << FDCANCCU_IE_CWEE_Pos)           /*!< 0x00000001 */

+#define FDCANCCU_IE_CWEE             FDCANCCU_IE_CWEE_Msk                      /*!<Calibration Watchdog Event Enable      */

+#define FDCANCCU_IE_CSCE_Pos         (1U)

+#define FDCANCCU_IE_CSCE_Msk         (0x1UL << FDCANCCU_IE_CSCE_Pos)           /*!< 0x00000002 */

+#define FDCANCCU_IE_CSCE             FDCANCCU_IE_CSCE_Msk                      /*!<Calibration State Changed Enable       */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          HDMI-CEC (CEC)                                    */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for CEC_CR register  *********************/

+#define CEC_CR_CECEN_Pos         (0U)

+#define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                   /*!< 0x00000001 */

+#define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                                */

+#define CEC_CR_TXSOM_Pos         (1U)

+#define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                   /*!< 0x00000002 */

+#define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message                   */

+#define CEC_CR_TXEOM_Pos         (2U)

+#define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                   /*!< 0x00000004 */

+#define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message                     */

+

+/*******************  Bit definition for CEC_CFGR register  *******************/

+#define CEC_CFGR_SFT_Pos         (0U)

+#define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                   /*!< 0x00000007 */

+#define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time                      */

+#define CEC_CFGR_RXTOL_Pos       (3U)

+#define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                 /*!< 0x00000008 */

+#define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                             */

+#define CEC_CFGR_BRESTP_Pos      (4U)

+#define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                /*!< 0x00000010 */

+#define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                               */

+#define CEC_CFGR_BREGEN_Pos      (5U)

+#define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                /*!< 0x00000020 */

+#define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation           */

+#define CEC_CFGR_LBPEGEN_Pos     (6U)

+#define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)               /*!< 0x00000040 */

+#define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error generation      */

+#define CEC_CFGR_SFTOPT_Pos      (8U)

+#define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                /*!< 0x00000100 */

+#define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional             */

+#define CEC_CFGR_BRDNOGEN_Pos    (7U)

+#define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)              /*!< 0x00000080 */

+#define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No error generation         */

+#define CEC_CFGR_OAR_Pos         (16U)

+#define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                /*!< 0x7FFF0000 */

+#define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                           */

+#define CEC_CFGR_LSTN_Pos        (31U)

+#define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                  /*!< 0x80000000 */

+#define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                           */

+

+/*******************  Bit definition for CEC_TXDR register  *******************/

+#define CEC_TXDR_TXD_Pos         (0U)

+#define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                  /*!< 0x000000FF */

+#define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                               */

+

+/*******************  Bit definition for CEC_RXDR register  *******************/

+#define CEC_RXDR_RXD_Pos         (0U)

+#define CEC_RXDR_RXD_Msk         (0xFFUL << CEC_RXDR_RXD_Pos)                  /*!< 0x000000FF */

+#define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                              /*!< CEC Rx Data                               */

+

+/*******************  Bit definition for CEC_ISR register  ********************/

+#define CEC_ISR_RXBR_Pos         (0U)

+#define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                   /*!< 0x00000001 */

+#define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                      */

+#define CEC_ISR_RXEND_Pos        (1U)

+#define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                  /*!< 0x00000002 */

+#define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                      */

+#define CEC_ISR_RXOVR_Pos        (2U)

+#define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                  /*!< 0x00000004 */

+#define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                            */

+#define CEC_ISR_BRE_Pos          (3U)

+#define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                    /*!< 0x00000008 */

+#define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                   */

+#define CEC_ISR_SBPE_Pos         (4U)

+#define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                   /*!< 0x00000010 */

+#define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error             */

+#define CEC_ISR_LBPE_Pos         (5U)

+#define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                   /*!< 0x00000020 */

+#define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error              */

+#define CEC_ISR_RXACKE_Pos       (6U)

+#define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                 /*!< 0x00000040 */

+#define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge                */

+#define CEC_ISR_ARBLST_Pos       (7U)

+#define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                 /*!< 0x00000080 */

+#define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                      */

+#define CEC_ISR_TXBR_Pos         (8U)

+#define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                   /*!< 0x00000100 */

+#define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                       */

+#define CEC_ISR_TXEND_Pos        (9U)

+#define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                  /*!< 0x00000200 */

+#define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                   */

+#define CEC_ISR_TXUDR_Pos        (10U)

+#define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                  /*!< 0x00000400 */

+#define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                    */

+#define CEC_ISR_TXERR_Pos        (11U)

+#define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                  /*!< 0x00000800 */

+#define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                              */

+#define CEC_ISR_TXACKE_Pos       (12U)

+#define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                 /*!< 0x00001000 */

+#define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge                */

+

+/*******************  Bit definition for CEC_IER register  ********************/

+#define CEC_IER_RXBRIE_Pos       (0U)

+#define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                 /*!< 0x00000001 */

+#define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable            */

+#define CEC_IER_RXENDIE_Pos      (1U)

+#define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                /*!< 0x00000002 */

+#define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable            */

+#define CEC_IER_RXOVRIE_Pos      (2U)

+#define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                /*!< 0x00000004 */

+#define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable                  */

+#define CEC_IER_BREIE_Pos        (3U)

+#define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                  /*!< 0x00000008 */

+#define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable         */

+#define CEC_IER_SBPEIE_Pos       (4U)

+#define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                 /*!< 0x00000010 */

+#define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable   */

+#define CEC_IER_LBPEIE_Pos       (5U)

+#define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                 /*!< 0x00000020 */

+#define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable    */

+#define CEC_IER_RXACKEIE_Pos     (6U)

+#define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)               /*!< 0x00000040 */

+#define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable      */

+#define CEC_IER_ARBLSTIE_Pos     (7U)

+#define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)               /*!< 0x00000080 */

+#define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable            */

+#define CEC_IER_TXBRIE_Pos       (8U)

+#define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                 /*!< 0x00000100 */

+#define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable            */

+#define CEC_IER_TXENDIE_Pos      (9U)

+#define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                /*!< 0x00000200 */

+#define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable         */

+#define CEC_IER_TXUDRIE_Pos      (10U)

+#define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                /*!< 0x00000400 */

+#define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable          */

+#define CEC_IER_TXERRIE_Pos      (11U)

+#define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                /*!< 0x00000800 */

+#define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                    */

+#define CEC_IER_TXACKEIE_Pos     (12U)

+#define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)               /*!< 0x00001000 */

+#define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable      */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          CRC calculation unit                              */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for CRC_DR register  *********************/

+#define CRC_DR_DR_Pos            (0U)

+#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */

+#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */

+

+/*******************  Bit definition for CRC_IDR register  ********************/

+#define CRC_IDR_IDR_Pos          (0U)

+#define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */

+#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */

+

+/********************  Bit definition for CRC_CR register  ********************/

+#define CRC_CR_RESET_Pos         (0U)

+#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */

+#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */

+#define CRC_CR_POLYSIZE_Pos      (3U)

+#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */

+#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */

+#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */

+#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */

+#define CRC_CR_REV_IN_Pos        (5U)

+#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */

+#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */

+#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */

+#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */

+#define CRC_CR_REV_OUT_Pos       (7U)

+#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */

+#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */

+

+/*******************  Bit definition for CRC_INIT register  *******************/

+#define CRC_INIT_INIT_Pos        (0U)

+#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */

+#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */

+

+/*******************  Bit definition for CRC_POL register  ********************/

+#define CRC_POL_POL_Pos          (0U)

+#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */

+#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          CRS Clock Recovery System                         */

+/******************************************************************************/

+

+/*******************  Bit definition for CRS_CR register  *********************/

+#define CRS_CR_SYNCOKIE_Pos       (0U)

+#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */

+#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */

+#define CRS_CR_SYNCWARNIE_Pos     (1U)

+#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */

+#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */

+#define CRS_CR_ERRIE_Pos          (2U)

+#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */

+#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */

+#define CRS_CR_ESYNCIE_Pos        (3U)

+#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */

+#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */

+#define CRS_CR_CEN_Pos            (5U)

+#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */

+#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */

+#define CRS_CR_AUTOTRIMEN_Pos     (6U)

+#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */

+#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */

+#define CRS_CR_SWSYNC_Pos         (7U)

+#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */

+#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */

+#define CRS_CR_TRIM_Pos           (8U)

+#define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00003F00 */

+#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */

+

+/*******************  Bit definition for CRS_CFGR register  *********************/

+#define CRS_CFGR_RELOAD_Pos       (0U)

+#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */

+#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */

+#define CRS_CFGR_FELIM_Pos        (16U)

+#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */

+#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */

+

+#define CRS_CFGR_SYNCDIV_Pos      (24U)

+#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */

+#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */

+#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */

+#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */

+#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */

+

+#define CRS_CFGR_SYNCSRC_Pos      (28U)

+#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */

+#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */

+#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */

+#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */

+

+#define CRS_CFGR_SYNCPOL_Pos      (31U)

+#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */

+#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */

+

+/*******************  Bit definition for CRS_ISR register  *********************/

+#define CRS_ISR_SYNCOKF_Pos       (0U)

+#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */

+#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */

+#define CRS_ISR_SYNCWARNF_Pos     (1U)

+#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */

+#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */

+#define CRS_ISR_ERRF_Pos          (2U)

+#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */

+#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */

+#define CRS_ISR_ESYNCF_Pos        (3U)

+#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */

+#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */

+#define CRS_ISR_SYNCERR_Pos       (8U)

+#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */

+#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */

+#define CRS_ISR_SYNCMISS_Pos      (9U)

+#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */

+#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */

+#define CRS_ISR_TRIMOVF_Pos       (10U)

+#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */

+#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */

+#define CRS_ISR_FEDIR_Pos         (15U)

+#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */

+#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */

+#define CRS_ISR_FECAP_Pos         (16U)

+#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */

+#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */

+

+/*******************  Bit definition for CRS_ICR register  *********************/

+#define CRS_ICR_SYNCOKC_Pos       (0U)

+#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */

+#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */

+#define CRS_ICR_SYNCWARNC_Pos     (1U)

+#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */

+#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */

+#define CRS_ICR_ERRC_Pos          (2U)

+#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */

+#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */

+#define CRS_ICR_ESYNCC_Pos        (3U)

+#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */

+#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            Crypto Processor                                */

+/*                                                                            */

+/******************************************************************************/

+/******************* Bits definition for CRYP_CR register  ********************/

+#define CRYP_CR_ALGODIR_Pos              (2U)

+#define CRYP_CR_ALGODIR_Msk              (0x1UL << CRYP_CR_ALGODIR_Pos)        /*!< 0x00000004 */

+#define CRYP_CR_ALGODIR                  CRYP_CR_ALGODIR_Msk

+

+#define CRYP_CR_ALGOMODE_Pos             (3U)

+#define CRYP_CR_ALGOMODE_Msk             (0x10007UL << CRYP_CR_ALGOMODE_Pos)   /*!< 0x00080038 */

+#define CRYP_CR_ALGOMODE                 CRYP_CR_ALGOMODE_Msk

+#define CRYP_CR_ALGOMODE_0               (0x00001UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000008 */

+#define CRYP_CR_ALGOMODE_1               (0x00002UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000010 */

+#define CRYP_CR_ALGOMODE_2               (0x00004UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000020 */

+#define CRYP_CR_ALGOMODE_TDES_ECB        ((uint32_t)0x00000000)

+#define CRYP_CR_ALGOMODE_TDES_CBC_Pos    (3U)

+#define CRYP_CR_ALGOMODE_TDES_CBC_Msk    (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */

+#define CRYP_CR_ALGOMODE_TDES_CBC        CRYP_CR_ALGOMODE_TDES_CBC_Msk

+#define CRYP_CR_ALGOMODE_DES_ECB_Pos     (4U)

+#define CRYP_CR_ALGOMODE_DES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_DES_ECB_Pos) /*!< 0x00000010 */

+#define CRYP_CR_ALGOMODE_DES_ECB         CRYP_CR_ALGOMODE_DES_ECB_Msk

+#define CRYP_CR_ALGOMODE_DES_CBC_Pos     (3U)

+#define CRYP_CR_ALGOMODE_DES_CBC_Msk     (0x3UL << CRYP_CR_ALGOMODE_DES_CBC_Pos) /*!< 0x00000018 */

+#define CRYP_CR_ALGOMODE_DES_CBC         CRYP_CR_ALGOMODE_DES_CBC_Msk

+#define CRYP_CR_ALGOMODE_AES_ECB_Pos     (5U)

+#define CRYP_CR_ALGOMODE_AES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */

+#define CRYP_CR_ALGOMODE_AES_ECB         CRYP_CR_ALGOMODE_AES_ECB_Msk

+#define CRYP_CR_ALGOMODE_AES_CBC_Pos     (3U)

+#define CRYP_CR_ALGOMODE_AES_CBC_Msk     (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */

+#define CRYP_CR_ALGOMODE_AES_CBC         CRYP_CR_ALGOMODE_AES_CBC_Msk

+#define CRYP_CR_ALGOMODE_AES_CTR_Pos     (4U)

+#define CRYP_CR_ALGOMODE_AES_CTR_Msk     (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */

+#define CRYP_CR_ALGOMODE_AES_CTR         CRYP_CR_ALGOMODE_AES_CTR_Msk

+#define CRYP_CR_ALGOMODE_AES_KEY_Pos     (3U)

+#define CRYP_CR_ALGOMODE_AES_KEY_Msk     (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */

+#define CRYP_CR_ALGOMODE_AES_KEY         CRYP_CR_ALGOMODE_AES_KEY_Msk

+#define CRYP_CR_ALGOMODE_AES_GCM_Pos     (19U)

+#define CRYP_CR_ALGOMODE_AES_GCM_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_GCM_Pos) /*!< 0x00080000 */

+#define CRYP_CR_ALGOMODE_AES_GCM         CRYP_CR_ALGOMODE_AES_GCM_Msk

+#define CRYP_CR_ALGOMODE_AES_CCM_Pos     (3U)

+#define CRYP_CR_ALGOMODE_AES_CCM_Msk     (0x10001UL << CRYP_CR_ALGOMODE_AES_CCM_Pos) /*!< 0x00080008 */

+#define CRYP_CR_ALGOMODE_AES_CCM         CRYP_CR_ALGOMODE_AES_CCM_Msk

+

+#define CRYP_CR_DATATYPE_Pos             (6U)

+#define CRYP_CR_DATATYPE_Msk             (0x3UL << CRYP_CR_DATATYPE_Pos)       /*!< 0x000000C0 */

+#define CRYP_CR_DATATYPE                 CRYP_CR_DATATYPE_Msk

+#define CRYP_CR_DATATYPE_0               (0x1UL << CRYP_CR_DATATYPE_Pos)        /*!< 0x00000040 */

+#define CRYP_CR_DATATYPE_1               (0x2UL << CRYP_CR_DATATYPE_Pos)        /*!< 0x00000080 */

+#define CRYP_CR_KEYSIZE_Pos              (8U)

+#define CRYP_CR_KEYSIZE_Msk              (0x3UL << CRYP_CR_KEYSIZE_Pos)        /*!< 0x00000300 */

+#define CRYP_CR_KEYSIZE                  CRYP_CR_KEYSIZE_Msk

+#define CRYP_CR_KEYSIZE_0                (0x1UL << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000100 */

+#define CRYP_CR_KEYSIZE_1                (0x2UL << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000200 */

+#define CRYP_CR_FFLUSH_Pos               (14U)

+#define CRYP_CR_FFLUSH_Msk               (0x1UL << CRYP_CR_FFLUSH_Pos)         /*!< 0x00004000 */

+#define CRYP_CR_FFLUSH                   CRYP_CR_FFLUSH_Msk

+#define CRYP_CR_CRYPEN_Pos               (15U)

+#define CRYP_CR_CRYPEN_Msk               (0x1UL << CRYP_CR_CRYPEN_Pos)         /*!< 0x00008000 */

+#define CRYP_CR_CRYPEN                   CRYP_CR_CRYPEN_Msk

+

+#define CRYP_CR_GCM_CCMPH_Pos            (16U)

+#define CRYP_CR_GCM_CCMPH_Msk            (0x3UL << CRYP_CR_GCM_CCMPH_Pos)      /*!< 0x00030000 */

+#define CRYP_CR_GCM_CCMPH                CRYP_CR_GCM_CCMPH_Msk

+#define CRYP_CR_GCM_CCMPH_0              (0x1UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00010000 */

+#define CRYP_CR_GCM_CCMPH_1              (0x2UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00020000 */

+#define CRYP_CR_ALGOMODE_3               ((uint32_t)0x00080000)

+#define CRYP_CR_NPBLB_Pos                (20U)

+#define CRYP_CR_NPBLB_Msk                (0xFUL << CRYP_CR_NPBLB_Pos)          /*!< 0x00F00000 */

+#define CRYP_CR_NPBLB                    CRYP_CR_NPBLB_Msk

+

+/****************** Bits definition for CRYP_SR register  *********************/

+#define CRYP_SR_IFEM_Pos                 (0U)

+#define CRYP_SR_IFEM_Msk                 (0x1UL << CRYP_SR_IFEM_Pos)           /*!< 0x00000001 */

+#define CRYP_SR_IFEM                     CRYP_SR_IFEM_Msk

+#define CRYP_SR_IFNF_Pos                 (1U)

+#define CRYP_SR_IFNF_Msk                 (0x1UL << CRYP_SR_IFNF_Pos)           /*!< 0x00000002 */

+#define CRYP_SR_IFNF                     CRYP_SR_IFNF_Msk

+#define CRYP_SR_OFNE_Pos                 (2U)

+#define CRYP_SR_OFNE_Msk                 (0x1UL << CRYP_SR_OFNE_Pos)           /*!< 0x00000004 */

+#define CRYP_SR_OFNE                     CRYP_SR_OFNE_Msk

+#define CRYP_SR_OFFU_Pos                 (3U)

+#define CRYP_SR_OFFU_Msk                 (0x1UL << CRYP_SR_OFFU_Pos)           /*!< 0x00000008 */

+#define CRYP_SR_OFFU                     CRYP_SR_OFFU_Msk

+#define CRYP_SR_BUSY_Pos                 (4U)

+#define CRYP_SR_BUSY_Msk                 (0x1UL << CRYP_SR_BUSY_Pos)           /*!< 0x00000010 */

+#define CRYP_SR_BUSY                     CRYP_SR_BUSY_Msk

+/****************** Bits definition for CRYP_DMACR register  ******************/

+#define CRYP_DMACR_DIEN_Pos              (0U)

+#define CRYP_DMACR_DIEN_Msk              (0x1UL << CRYP_DMACR_DIEN_Pos)        /*!< 0x00000001 */

+#define CRYP_DMACR_DIEN                  CRYP_DMACR_DIEN_Msk

+#define CRYP_DMACR_DOEN_Pos              (1U)

+#define CRYP_DMACR_DOEN_Msk              (0x1UL << CRYP_DMACR_DOEN_Pos)        /*!< 0x00000002 */

+#define CRYP_DMACR_DOEN                  CRYP_DMACR_DOEN_Msk

+/*****************  Bits definition for CRYP_IMSCR register  ******************/

+#define CRYP_IMSCR_INIM_Pos              (0U)

+#define CRYP_IMSCR_INIM_Msk              (0x1UL << CRYP_IMSCR_INIM_Pos)        /*!< 0x00000001 */

+#define CRYP_IMSCR_INIM                  CRYP_IMSCR_INIM_Msk

+#define CRYP_IMSCR_OUTIM_Pos             (1U)

+#define CRYP_IMSCR_OUTIM_Msk             (0x1UL << CRYP_IMSCR_OUTIM_Pos)       /*!< 0x00000002 */

+#define CRYP_IMSCR_OUTIM                 CRYP_IMSCR_OUTIM_Msk

+/****************** Bits definition for CRYP_RISR register  *******************/

+#define CRYP_RISR_INRIS_Pos              (0U)

+#define CRYP_RISR_INRIS_Msk              (0x1UL << CRYP_RISR_INRIS_Pos)        /*!< 0x00000001 */

+#define CRYP_RISR_INRIS                  CRYP_RISR_INRIS_Msk

+#define CRYP_RISR_OUTRIS_Pos             (1U)

+#define CRYP_RISR_OUTRIS_Msk             (0x1UL << CRYP_RISR_OUTRIS_Pos)       /*!< 0x00000002 */

+#define CRYP_RISR_OUTRIS                 CRYP_RISR_OUTRIS_Msk

+/****************** Bits definition for CRYP_MISR register  *******************/

+#define CRYP_MISR_INMIS_Pos              (0U)

+#define CRYP_MISR_INMIS_Msk              (0x1UL << CRYP_MISR_INMIS_Pos)        /*!< 0x00000001 */

+#define CRYP_MISR_INMIS                  CRYP_MISR_INMIS_Msk

+#define CRYP_MISR_OUTMIS_Pos             (1U)

+#define CRYP_MISR_OUTMIS_Msk             (0x1UL << CRYP_MISR_OUTMIS_Pos)       /*!< 0x00000002 */

+#define CRYP_MISR_OUTMIS                 CRYP_MISR_OUTMIS_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                      Digital to Analog Converter                           */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for DAC_CR register  ********************/

+#define DAC_CR_EN1_Pos              (0U)

+#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */

+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */

+#define DAC_CR_TEN1_Pos             (1U)

+#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */

+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */

+

+#define DAC_CR_TSEL1_Pos            (2U)

+#define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */

+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */

+#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000004 */

+#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */

+#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */

+#define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */

+

+

+#define DAC_CR_WAVE1_Pos            (6U)

+#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */

+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */

+#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */

+#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */

+

+#define DAC_CR_MAMP1_Pos            (8U)

+#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */

+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */

+#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */

+#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */

+#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */

+#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */

+

+#define DAC_CR_DMAEN1_Pos           (12U)

+#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */

+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */

+#define DAC_CR_DMAUDRIE1_Pos        (13U)

+#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */

+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/

+#define DAC_CR_CEN1_Pos             (14U)

+#define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */

+#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/

+

+#define DAC_CR_EN2_Pos              (16U)

+#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */

+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */

+#define DAC_CR_TEN2_Pos             (17U)

+#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */

+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */

+

+#define DAC_CR_TSEL2_Pos            (18U)

+#define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */

+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */

+#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00040000 */

+#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */

+#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */

+#define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */

+

+

+#define DAC_CR_WAVE2_Pos            (22U)

+#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */

+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */

+#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */

+#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */

+

+#define DAC_CR_MAMP2_Pos            (24U)

+#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */

+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */

+#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */

+#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */

+#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */

+#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */

+

+#define DAC_CR_DMAEN2_Pos           (28U)

+#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */

+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */

+#define DAC_CR_DMAUDRIE2_Pos        (29U)

+#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */

+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/

+#define DAC_CR_CEN2_Pos             (30U)

+#define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */

+#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/

+

+/*****************  Bit definition for DAC_SWTRIGR register  ******************/

+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)

+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */

+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */

+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)

+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */

+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */

+

+/*****************  Bit definition for DAC_DHR12R1 register  ******************/

+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)

+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12L1 register  ******************/

+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)

+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8R1 register  ******************/

+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)

+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12R2 register  ******************/

+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)

+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12L2 register  ******************/

+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)

+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8R2 register  ******************/

+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)

+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12RD register  ******************/

+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)

+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */

+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)

+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */

+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12LD register  ******************/

+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)

+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */

+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)

+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */

+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8RD register  ******************/

+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)

+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */

+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)

+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */

+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */

+

+/*******************  Bit definition for DAC_DOR1 register  *******************/

+#define DAC_DOR1_DACC1DOR_Pos       (0U)

+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */

+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */

+

+/*******************  Bit definition for DAC_DOR2 register  *******************/

+#define DAC_DOR2_DACC2DOR_Pos       (0U)

+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */

+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */

+

+/********************  Bit definition for DAC_SR register  ********************/

+#define DAC_SR_DMAUDR1_Pos          (13U)

+#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */

+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */

+#define DAC_SR_CAL_FLAG1_Pos        (14U)

+#define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */

+#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */

+#define DAC_SR_BWST1_Pos            (15U)

+#define DAC_SR_BWST1_Msk            (0x4001UL << DAC_SR_BWST1_Pos)             /*!< 0x20008000 */

+#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */

+

+#define DAC_SR_DMAUDR2_Pos          (29U)

+#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */

+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */

+#define DAC_SR_CAL_FLAG2_Pos        (30U)

+#define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */

+#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */

+#define DAC_SR_BWST2_Pos            (31U)

+#define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */

+#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */

+

+/*******************  Bit definition for DAC_CCR register  ********************/

+#define DAC_CCR_OTRIM1_Pos          (0U)

+#define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */

+#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */

+#define DAC_CCR_OTRIM2_Pos          (16U)

+#define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */

+#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */

+

+/*******************  Bit definition for DAC_MCR register  *******************/

+#define DAC_MCR_MODE1_Pos           (0U)

+#define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */

+#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */

+#define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */

+#define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */

+#define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */

+

+#define DAC_MCR_MODE2_Pos           (16U)

+#define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */

+#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */

+#define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */

+#define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */

+#define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */

+

+/******************  Bit definition for DAC_SHSR1 register  ******************/

+#define DAC_SHSR1_TSAMPLE1_Pos      (0U)

+#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */

+#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */

+

+/******************  Bit definition for DAC_SHSR2 register  ******************/

+#define DAC_SHSR2_TSAMPLE2_Pos      (0U)

+#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */

+#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */

+

+/******************  Bit definition for DAC_SHHR register  ******************/

+#define DAC_SHHR_THOLD1_Pos         (0U)

+#define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */

+#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */

+#define DAC_SHHR_THOLD2_Pos         (16U)

+#define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */

+#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */

+

+/******************  Bit definition for DAC_SHRR register  ******************/

+#define DAC_SHRR_TREFRESH1_Pos      (0U)

+#define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */

+#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */

+#define DAC_SHRR_TREFRESH2_Pos      (16U)

+#define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */

+#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    DCMI                                    */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DCMI_CR register  ******************/

+#define DCMI_CR_CAPTURE_Pos        (0U)

+#define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)              /*!< 0x00000001 */

+#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk

+#define DCMI_CR_CM_Pos             (1U)

+#define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                   /*!< 0x00000002 */

+#define DCMI_CR_CM                 DCMI_CR_CM_Msk

+#define DCMI_CR_CROP_Pos           (2U)

+#define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                 /*!< 0x00000004 */

+#define DCMI_CR_CROP               DCMI_CR_CROP_Msk

+#define DCMI_CR_JPEG_Pos           (3U)

+#define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                 /*!< 0x00000008 */

+#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk

+#define DCMI_CR_ESS_Pos            (4U)

+#define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                  /*!< 0x00000010 */

+#define DCMI_CR_ESS                DCMI_CR_ESS_Msk

+#define DCMI_CR_PCKPOL_Pos         (5U)

+#define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)               /*!< 0x00000020 */

+#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk

+#define DCMI_CR_HSPOL_Pos          (6U)

+#define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                /*!< 0x00000040 */

+#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk

+#define DCMI_CR_VSPOL_Pos          (7U)

+#define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */

+#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk

+#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)

+#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)

+#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)

+#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)

+#define DCMI_CR_CRE_Pos            (12U)

+#define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */

+#define DCMI_CR_CRE                DCMI_CR_CRE_Msk

+#define DCMI_CR_ENABLE_Pos         (14U)

+#define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)               /*!< 0x00004000 */

+#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk

+#define DCMI_CR_BSM_Pos            (16U)

+#define DCMI_CR_BSM_Msk            (0x3UL << DCMI_CR_BSM_Pos)                  /*!< 0x00030000 */

+#define DCMI_CR_BSM                DCMI_CR_BSM_Msk

+#define DCMI_CR_BSM_0              (0x1UL << DCMI_CR_BSM_Pos)                   /*!< 0x00010000 */

+#define DCMI_CR_BSM_1              (0x2UL << DCMI_CR_BSM_Pos)                   /*!< 0x00020000 */

+#define DCMI_CR_OEBS_Pos           (18U)

+#define DCMI_CR_OEBS_Msk           (0x1UL << DCMI_CR_OEBS_Pos)                 /*!< 0x00040000 */

+#define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk

+#define DCMI_CR_LSM_Pos            (19U)

+#define DCMI_CR_LSM_Msk            (0x1UL << DCMI_CR_LSM_Pos)                  /*!< 0x00080000 */

+#define DCMI_CR_LSM                DCMI_CR_LSM_Msk

+#define DCMI_CR_OELS_Pos           (20U)

+#define DCMI_CR_OELS_Msk           (0x1UL << DCMI_CR_OELS_Pos)                 /*!< 0x00100000 */

+#define DCMI_CR_OELS               DCMI_CR_OELS_Msk

+

+/********************  Bits definition for DCMI_SR register  ******************/

+#define DCMI_SR_HSYNC_Pos          (0U)

+#define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                /*!< 0x00000001 */

+#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk

+#define DCMI_SR_VSYNC_Pos          (1U)

+#define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                /*!< 0x00000002 */

+#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk

+#define DCMI_SR_FNE_Pos            (2U)

+#define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                  /*!< 0x00000004 */

+#define DCMI_SR_FNE                DCMI_SR_FNE_Msk

+

+/********************  Bits definition for DCMI_RIS register   ****************/

+#define DCMI_RIS_FRAME_RIS_Pos     (0U)

+#define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)           /*!< 0x00000001 */

+#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk

+#define DCMI_RIS_OVR_RIS_Pos       (1U)

+#define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)             /*!< 0x00000002 */

+#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk

+#define DCMI_RIS_ERR_RIS_Pos       (2U)

+#define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)             /*!< 0x00000004 */

+#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk

+#define DCMI_RIS_VSYNC_RIS_Pos     (3U)

+#define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)           /*!< 0x00000008 */

+#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk

+#define DCMI_RIS_LINE_RIS_Pos      (4U)

+#define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)            /*!< 0x00000010 */

+#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk

+

+/********************  Bits definition for DCMI_IER register  *****************/

+#define DCMI_IER_FRAME_IE_Pos      (0U)

+#define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)            /*!< 0x00000001 */

+#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk

+#define DCMI_IER_OVR_IE_Pos        (1U)

+#define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)              /*!< 0x00000002 */

+#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk

+#define DCMI_IER_ERR_IE_Pos        (2U)

+#define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)              /*!< 0x00000004 */

+#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk

+#define DCMI_IER_VSYNC_IE_Pos      (3U)

+#define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)            /*!< 0x00000008 */

+#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk

+#define DCMI_IER_LINE_IE_Pos       (4U)

+#define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)             /*!< 0x00000010 */

+#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk

+

+

+/********************  Bits definition for DCMI_MIS register  *****************/

+#define DCMI_MIS_FRAME_MIS_Pos     (0U)

+#define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)           /*!< 0x00000001 */

+#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk

+#define DCMI_MIS_OVR_MIS_Pos       (1U)

+#define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)             /*!< 0x00000002 */

+#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk

+#define DCMI_MIS_ERR_MIS_Pos       (2U)

+#define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)             /*!< 0x00000004 */

+#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk

+#define DCMI_MIS_VSYNC_MIS_Pos     (3U)

+#define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)           /*!< 0x00000008 */

+#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk

+#define DCMI_MIS_LINE_MIS_Pos      (4U)

+#define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)            /*!< 0x00000010 */

+#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk

+

+

+/********************  Bits definition for DCMI_ICR register  *****************/

+#define DCMI_ICR_FRAME_ISC_Pos     (0U)

+#define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)           /*!< 0x00000001 */

+#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk

+#define DCMI_ICR_OVR_ISC_Pos       (1U)

+#define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)             /*!< 0x00000002 */

+#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk

+#define DCMI_ICR_ERR_ISC_Pos       (2U)

+#define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)             /*!< 0x00000004 */

+#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk

+#define DCMI_ICR_VSYNC_ISC_Pos     (3U)

+#define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)           /*!< 0x00000008 */

+#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk

+#define DCMI_ICR_LINE_ISC_Pos      (4U)

+#define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)            /*!< 0x00000010 */

+#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk

+

+

+/********************  Bits definition for DCMI_ESCR register  ******************/

+#define DCMI_ESCR_FSC_Pos          (0U)

+#define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)               /*!< 0x000000FF */

+#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk

+#define DCMI_ESCR_LSC_Pos          (8U)

+#define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)               /*!< 0x0000FF00 */

+#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk

+#define DCMI_ESCR_LEC_Pos          (16U)

+#define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)               /*!< 0x00FF0000 */

+#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk

+#define DCMI_ESCR_FEC_Pos          (24U)

+#define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)               /*!< 0xFF000000 */

+#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk

+

+/********************  Bits definition for DCMI_ESUR register  ******************/

+#define DCMI_ESUR_FSU_Pos          (0U)

+#define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)               /*!< 0x000000FF */

+#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk

+#define DCMI_ESUR_LSU_Pos          (8U)

+#define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)               /*!< 0x0000FF00 */

+#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk

+#define DCMI_ESUR_LEU_Pos          (16U)

+#define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)               /*!< 0x00FF0000 */

+#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk

+#define DCMI_ESUR_FEU_Pos          (24U)

+#define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)               /*!< 0xFF000000 */

+#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk

+

+/********************  Bits definition for DCMI_CWSTRT register  ******************/

+#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)

+#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)       /*!< 0x00003FFF */

+#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk

+#define DCMI_CWSTRT_VST_Pos        (16U)

+#define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)           /*!< 0x1FFF0000 */

+#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk

+

+/********************  Bits definition for DCMI_CWSIZE register  ******************/

+#define DCMI_CWSIZE_CAPCNT_Pos     (0U)

+#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)        /*!< 0x00003FFF */

+#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk

+#define DCMI_CWSIZE_VLINE_Pos      (16U)

+#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)         /*!< 0x3FFF0000 */

+#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk

+

+/********************  Bits definition for DCMI_DR register  ******************/

+#define DCMI_DR_BYTE0_Pos          (0U)

+#define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)               /*!< 0x000000FF */

+#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk

+#define DCMI_DR_BYTE1_Pos          (8U)

+#define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)               /*!< 0x0000FF00 */

+#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk

+#define DCMI_DR_BYTE2_Pos          (16U)

+#define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)               /*!< 0x00FF0000 */

+#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk

+#define DCMI_DR_BYTE3_Pos          (24U)

+#define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)               /*!< 0xFF000000 */

+#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                 Digital Filter for Sigma Delta Modulators                  */

+/*                                                                            */

+/******************************************************************************/

+

+/****************   DFSDM channel configuration registers  ********************/

+

+/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/

+#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)

+#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)   /*!< 0x80000000 */

+#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */

+#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)

+#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)  /*!< 0x40000000 */

+#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */

+#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)

+#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */

+#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */

+#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)

+#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x0000C000 */

+#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */

+#define DFSDM_CHCFGR1_DATPACK_1         (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */

+#define DFSDM_CHCFGR1_DATPACK_0         (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */

+#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)

+#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00003000 */

+#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */

+#define DFSDM_CHCFGR1_DATMPX_1          (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */

+#define DFSDM_CHCFGR1_DATMPX_0          (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */

+#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)

+#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)   /*!< 0x00000100 */

+#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */

+#define DFSDM_CHCFGR1_CHEN_Pos          (7U)

+#define DFSDM_CHCFGR1_CHEN_Msk          (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)      /*!< 0x00000080 */

+#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */

+#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)

+#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)    /*!< 0x00000040 */

+#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */

+#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)

+#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)     /*!< 0x00000020 */

+#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */

+#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)

+#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x0000000C */

+#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */

+#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */

+#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */

+#define DFSDM_CHCFGR1_SITP_Pos          (0U)

+#define DFSDM_CHCFGR1_SITP_Msk          (0x3UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000003 */

+#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */

+#define DFSDM_CHCFGR1_SITP_1            (0x2UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */

+#define DFSDM_CHCFGR1_SITP_0            (0x1UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */

+

+/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/

+#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)

+#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */

+#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)

+#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)    /*!< 0x000000F8 */

+#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */

+

+/******************  Bit definition for DFSDM_CHAWSCDR register *****************/

+#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)

+#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00C00000 */

+#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */

+#define DFSDM_CHAWSCDR_AWFORD_1         (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */

+#define DFSDM_CHAWSCDR_AWFORD_0         (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */

+#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)

+#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)  /*!< 0x001F0000 */

+#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */

+#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)

+#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)    /*!< 0x0000F000 */

+#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */

+#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)

+#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)    /*!< 0x000000FF */

+#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */

+

+/****************  Bit definition for DFSDM_CHWDATR register *******************/

+#define DFSDM_CHWDATR_WDATA_Pos         (0U)

+#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)  /*!< 0x0000FFFF */

+#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */

+

+/****************  Bit definition for DFSDM_CHDATINR register *****************/

+#define DFSDM_CHDATINR_INDAT0_Pos       (0U)

+#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */

+#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */

+#define DFSDM_CHDATINR_INDAT1_Pos       (16U)

+#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */

+#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */

+

+/************************   DFSDM module registers  ****************************/

+

+/********************  Bit definition for DFSDM_FLTCR1 register *******************/

+#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)

+#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)     /*!< 0x40000000 */

+#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */

+#define DFSDM_FLTCR1_FAST_Pos           (29U)

+#define DFSDM_FLTCR1_FAST_Msk           (0x1UL << DFSDM_FLTCR1_FAST_Pos)       /*!< 0x20000000 */

+#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */

+#define DFSDM_FLTCR1_RCH_Pos            (24U)

+#define DFSDM_FLTCR1_RCH_Msk            (0x7UL << DFSDM_FLTCR1_RCH_Pos)        /*!< 0x07000000 */

+#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */

+#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)

+#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)     /*!< 0x00200000 */

+#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */

+#define DFSDM_FLTCR1_RSYNC_Pos          (19U)

+#define DFSDM_FLTCR1_RSYNC_Msk          (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)      /*!< 0x00080000 */

+#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */

+#define DFSDM_FLTCR1_RCONT_Pos          (18U)

+#define DFSDM_FLTCR1_RCONT_Msk          (0x1UL << DFSDM_FLTCR1_RCONT_Pos)      /*!< 0x00040000 */

+#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */

+#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)

+#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)   /*!< 0x00020000 */

+#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */

+#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)

+#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00006000 */

+#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */

+#define DFSDM_FLTCR1_JEXTEN_1           (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */

+#define DFSDM_FLTCR1_JEXTEN_0           (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */

+#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)

+#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)   /*!< 0x00001F00 */

+#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */

+#define DFSDM_FLTCR1_JEXTSEL_0          (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000100 */

+#define DFSDM_FLTCR1_JEXTSEL_1          (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000200 */

+#define DFSDM_FLTCR1_JEXTSEL_2          (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000400 */

+#define DFSDM_FLTCR1_JEXTSEL_3          (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000800 */

+#define DFSDM_FLTCR1_JEXTSEL_4          (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00001000 */

+

+#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)

+#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)     /*!< 0x00000020 */

+#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */

+#define DFSDM_FLTCR1_JSCAN_Pos          (4U)

+#define DFSDM_FLTCR1_JSCAN_Msk          (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)      /*!< 0x00000010 */

+#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */

+#define DFSDM_FLTCR1_JSYNC_Pos          (3U)

+#define DFSDM_FLTCR1_JSYNC_Msk          (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)      /*!< 0x00000008 */

+#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */

+#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)

+#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)   /*!< 0x00000002 */

+#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */

+#define DFSDM_FLTCR1_DFEN_Pos           (0U)

+#define DFSDM_FLTCR1_DFEN_Msk           (0x1UL << DFSDM_FLTCR1_DFEN_Pos)       /*!< 0x00000001 */

+#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */

+

+/********************  Bit definition for DFSDM_FLTCR2 register *******************/

+#define DFSDM_FLTCR2_AWDCH_Pos          (16U)

+#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)     /*!< 0x00FF0000 */

+#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */

+#define DFSDM_FLTCR2_EXCH_Pos           (8U)

+#define DFSDM_FLTCR2_EXCH_Msk           (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)      /*!< 0x0000FF00 */

+#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */

+#define DFSDM_FLTCR2_CKABIE_Pos         (6U)

+#define DFSDM_FLTCR2_CKABIE_Msk         (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)     /*!< 0x00000040 */

+#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */

+#define DFSDM_FLTCR2_SCDIE_Pos          (5U)

+#define DFSDM_FLTCR2_SCDIE_Msk          (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)      /*!< 0x00000020 */

+#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */

+#define DFSDM_FLTCR2_AWDIE_Pos          (4U)

+#define DFSDM_FLTCR2_AWDIE_Msk          (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)      /*!< 0x00000010 */

+#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */

+#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)

+#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)     /*!< 0x00000008 */

+#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */

+#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)

+#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)     /*!< 0x00000004 */

+#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */

+#define DFSDM_FLTCR2_REOCIE_Pos         (1U)

+#define DFSDM_FLTCR2_REOCIE_Msk         (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)     /*!< 0x00000002 */

+#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */

+#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)

+#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)     /*!< 0x00000001 */

+#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */

+

+/********************  Bit definition for DFSDM_FLTISR register *******************/

+#define DFSDM_FLTISR_SCDF_Pos           (24U)

+#define DFSDM_FLTISR_SCDF_Msk           (0xFFUL << DFSDM_FLTISR_SCDF_Pos)      /*!< 0xFF000000 */

+#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */

+#define DFSDM_FLTISR_CKABF_Pos          (16U)

+#define DFSDM_FLTISR_CKABF_Msk          (0xFFUL << DFSDM_FLTISR_CKABF_Pos)     /*!< 0x00FF0000 */

+#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */

+#define DFSDM_FLTISR_RCIP_Pos           (14U)

+#define DFSDM_FLTISR_RCIP_Msk           (0x1UL << DFSDM_FLTISR_RCIP_Pos)       /*!< 0x00004000 */

+#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */

+#define DFSDM_FLTISR_JCIP_Pos           (13U)

+#define DFSDM_FLTISR_JCIP_Msk           (0x1UL << DFSDM_FLTISR_JCIP_Pos)       /*!< 0x00002000 */

+#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */

+#define DFSDM_FLTISR_AWDF_Pos           (4U)

+#define DFSDM_FLTISR_AWDF_Msk           (0x1UL << DFSDM_FLTISR_AWDF_Pos)       /*!< 0x00000010 */

+#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */

+#define DFSDM_FLTISR_ROVRF_Pos          (3U)

+#define DFSDM_FLTISR_ROVRF_Msk          (0x1UL << DFSDM_FLTISR_ROVRF_Pos)      /*!< 0x00000008 */

+#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */

+#define DFSDM_FLTISR_JOVRF_Pos          (2U)

+#define DFSDM_FLTISR_JOVRF_Msk          (0x1UL << DFSDM_FLTISR_JOVRF_Pos)      /*!< 0x00000004 */

+#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */

+#define DFSDM_FLTISR_REOCF_Pos          (1U)

+#define DFSDM_FLTISR_REOCF_Msk          (0x1UL << DFSDM_FLTISR_REOCF_Pos)      /*!< 0x00000002 */

+#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */

+#define DFSDM_FLTISR_JEOCF_Pos          (0U)

+#define DFSDM_FLTISR_JEOCF_Msk          (0x1UL << DFSDM_FLTISR_JEOCF_Pos)      /*!< 0x00000001 */

+#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */

+

+/********************  Bit definition for DFSDM_FLTICR register *******************/

+#define DFSDM_FLTICR_CLRSCDF_Pos        (24U)

+#define DFSDM_FLTICR_CLRSCDF_Msk        (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)   /*!< 0xFF000000 */

+#define DFSDM_FLTICR_CLRSCDF            DFSDM_FLTICR_CLRSCDF_Msk               /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */

+#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)

+#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)  /*!< 0x00FF0000 */

+#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */

+#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)

+#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)   /*!< 0x00000008 */

+#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */

+#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)

+#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)   /*!< 0x00000004 */

+#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */

+

+/*******************  Bit definition for DFSDM_FLTJCHGR register ******************/

+#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)

+#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)    /*!< 0x000000FF */

+#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */

+

+/********************  Bit definition for DFSDM_FLTFCR register *******************/

+#define DFSDM_FLTFCR_FORD_Pos           (29U)

+#define DFSDM_FLTFCR_FORD_Msk           (0x7UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0xE0000000 */

+#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */

+#define DFSDM_FLTFCR_FORD_2             (0x4UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */

+#define DFSDM_FLTFCR_FORD_1             (0x2UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */

+#define DFSDM_FLTFCR_FORD_0             (0x1UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */

+#define DFSDM_FLTFCR_FOSR_Pos           (16U)

+#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)     /*!< 0x03FF0000 */

+#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */

+#define DFSDM_FLTFCR_IOSR_Pos           (0U)

+#define DFSDM_FLTFCR_IOSR_Msk           (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)      /*!< 0x000000FF */

+#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */

+

+/******************  Bit definition for DFSDM_FLTJDATAR register *****************/

+#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)

+#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */

+#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)

+#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */

+#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */

+

+/******************  Bit definition for DFSDM_FLTRDATAR register *****************/

+#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)

+#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */

+#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)

+#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)   /*!< 0x00000010 */

+#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */

+#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)

+#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */

+#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */

+

+/******************  Bit definition for DFSDM_FLTAWHTR register ******************/

+#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)

+#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */

+#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)

+#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)    /*!< 0x0000000F */

+#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */

+

+/******************  Bit definition for DFSDM_FLTAWLTR register ******************/

+#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)

+#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWHT[23:0] Analog watchdog low threshold */

+#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)

+#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)    /*!< 0x0000000F */

+#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */

+

+/******************  Bit definition for DFSDM_FLTAWSR register ******************/

+#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)

+#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)    /*!< 0x0000FF00 */

+#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */

+#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)

+#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)    /*!< 0x000000FF */

+#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */

+

+/******************  Bit definition for DFSDM_FLTAWCFR) register *****************/

+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)

+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */

+#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */

+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)

+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */

+#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */

+

+/******************  Bit definition for DFSDM_FLTEXMAX register ******************/

+#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)

+#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */

+#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)

+#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)  /*!< 0x00000007 */

+#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */

+

+/******************  Bit definition for DFSDM_FLTEXMIN register ******************/

+#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)

+#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */

+#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)

+#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)  /*!< 0x00000007 */

+#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */

+

+/******************  Bit definition for DFSDM_FLTCNVTIMR register ******************/

+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)

+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */

+#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           BDMA Controller                                  */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for BDMA_ISR register  ********************/

+#define BDMA_ISR_GIF0_Pos       (0U)

+#define BDMA_ISR_GIF0_Msk       (0x1UL << BDMA_ISR_GIF0_Pos)                   /*!< 0x00000001 */

+#define BDMA_ISR_GIF0           BDMA_ISR_GIF0_Msk                              /*!< Channel 0 Global interrupt flag */

+#define BDMA_ISR_TCIF0_Pos      (1U)

+#define BDMA_ISR_TCIF0_Msk      (0x1UL << BDMA_ISR_TCIF0_Pos)                  /*!< 0x00000002 */

+#define BDMA_ISR_TCIF0          BDMA_ISR_TCIF0_Msk                             /*!< Channel 0 Transfer Complete flag */

+#define BDMA_ISR_HTIF0_Pos      (2U)

+#define BDMA_ISR_HTIF0_Msk      (0x1UL << BDMA_ISR_HTIF0_Pos)                  /*!< 0x00000004 */

+#define BDMA_ISR_HTIF0          BDMA_ISR_HTIF0_Msk                             /*!< Channel 0 Half Transfer flag */

+#define BDMA_ISR_TEIF0_Pos      (3U)

+#define BDMA_ISR_TEIF0_Msk      (0x1UL << BDMA_ISR_TEIF0_Pos)                  /*!< 0x00000008 */

+#define BDMA_ISR_TEIF0          BDMA_ISR_TEIF0_Msk                             /*!< Channel 0 Transfer Error flag */

+#define BDMA_ISR_GIF1_Pos       (4U)

+#define BDMA_ISR_GIF1_Msk       (0x1UL << BDMA_ISR_GIF1_Pos)                   /*!< 0x00000010 */

+#define BDMA_ISR_GIF1           BDMA_ISR_GIF1_Msk                              /*!< Channel 1 Global interrupt flag */

+#define BDMA_ISR_TCIF1_Pos      (5U)

+#define BDMA_ISR_TCIF1_Msk      (0x1UL << BDMA_ISR_TCIF1_Pos)                  /*!< 0x00000020 */

+#define BDMA_ISR_TCIF1          BDMA_ISR_TCIF1_Msk                             /*!< Channel 1 Transfer Complete flag */

+#define BDMA_ISR_HTIF1_Pos      (6U)

+#define BDMA_ISR_HTIF1_Msk      (0x1UL << BDMA_ISR_HTIF1_Pos)                  /*!< 0x00000040 */

+#define BDMA_ISR_HTIF1          BDMA_ISR_HTIF1_Msk                             /*!< Channel 1 Half Transfer flag */

+#define BDMA_ISR_TEIF1_Pos      (7U)

+#define BDMA_ISR_TEIF1_Msk      (0x1UL << BDMA_ISR_TEIF1_Pos)                  /*!< 0x00000080 */

+#define BDMA_ISR_TEIF1          BDMA_ISR_TEIF1_Msk                             /*!< Channel 1 Transfer Error flag */

+#define BDMA_ISR_GIF2_Pos       (8U)

+#define BDMA_ISR_GIF2_Msk       (0x1UL << BDMA_ISR_GIF2_Pos)                   /*!< 0x00000100 */

+#define BDMA_ISR_GIF2           BDMA_ISR_GIF2_Msk                              /*!< Channel 2 Global interrupt flag */

+#define BDMA_ISR_TCIF2_Pos      (9U)

+#define BDMA_ISR_TCIF2_Msk      (0x1UL << BDMA_ISR_TCIF2_Pos)                  /*!< 0x00000200 */

+#define BDMA_ISR_TCIF2          BDMA_ISR_TCIF2_Msk                             /*!< Channel 2 Transfer Complete flag */

+#define BDMA_ISR_HTIF2_Pos      (10U)

+#define BDMA_ISR_HTIF2_Msk      (0x1UL << BDMA_ISR_HTIF2_Pos)                  /*!< 0x00000400 */

+#define BDMA_ISR_HTIF2          BDMA_ISR_HTIF2_Msk                             /*!< Channel 2 Half Transfer flag */

+#define BDMA_ISR_TEIF2_Pos      (11U)

+#define BDMA_ISR_TEIF2_Msk      (0x1UL << BDMA_ISR_TEIF2_Pos)                  /*!< 0x00000800 */

+#define BDMA_ISR_TEIF2          BDMA_ISR_TEIF2_Msk                             /*!< Channel 2 Transfer Error flag */

+#define BDMA_ISR_GIF3_Pos       (12U)

+#define BDMA_ISR_GIF3_Msk       (0x1UL << BDMA_ISR_GIF3_Pos)                   /*!< 0x00001000 */

+#define BDMA_ISR_GIF3           BDMA_ISR_GIF3_Msk                              /*!< Channel 3 Global interrupt flag */

+#define BDMA_ISR_TCIF3_Pos      (13U)

+#define BDMA_ISR_TCIF3_Msk      (0x1UL << BDMA_ISR_TCIF3_Pos)                  /*!< 0x00002000 */

+#define BDMA_ISR_TCIF3          BDMA_ISR_TCIF3_Msk                             /*!< Channel 3 Transfer Complete flag */

+#define BDMA_ISR_HTIF3_Pos      (14U)

+#define BDMA_ISR_HTIF3_Msk      (0x1UL << BDMA_ISR_HTIF3_Pos)                  /*!< 0x00004000 */

+#define BDMA_ISR_HTIF3          BDMA_ISR_HTIF3_Msk                             /*!< Channel 3 Half Transfer flag */

+#define BDMA_ISR_TEIF3_Pos      (15U)

+#define BDMA_ISR_TEIF3_Msk      (0x1UL << BDMA_ISR_TEIF3_Pos)                  /*!< 0x00008000 */

+#define BDMA_ISR_TEIF3          BDMA_ISR_TEIF3_Msk                             /*!< Channel 3 Transfer Error flag */

+#define BDMA_ISR_GIF4_Pos       (16U)

+#define BDMA_ISR_GIF4_Msk       (0x1UL << BDMA_ISR_GIF4_Pos)                   /*!< 0x00010000 */

+#define BDMA_ISR_GIF4           BDMA_ISR_GIF4_Msk                              /*!< Channel 4 Global interrupt flag */

+#define BDMA_ISR_TCIF4_Pos      (17U)

+#define BDMA_ISR_TCIF4_Msk      (0x1UL << BDMA_ISR_TCIF4_Pos)                  /*!< 0x00020000 */

+#define BDMA_ISR_TCIF4          BDMA_ISR_TCIF4_Msk                             /*!< Channel 4 Transfer Complete flag */

+#define BDMA_ISR_HTIF4_Pos      (18U)

+#define BDMA_ISR_HTIF4_Msk      (0x1UL << BDMA_ISR_HTIF4_Pos)                  /*!< 0x00040000 */

+#define BDMA_ISR_HTIF4          BDMA_ISR_HTIF4_Msk                             /*!< Channel 4 Half Transfer flag */

+#define BDMA_ISR_TEIF4_Pos      (19U)

+#define BDMA_ISR_TEIF4_Msk      (0x1UL << BDMA_ISR_TEIF4_Pos)                  /*!< 0x00080000 */

+#define BDMA_ISR_TEIF4          BDMA_ISR_TEIF4_Msk                             /*!< Channel 4 Transfer Error flag */

+#define BDMA_ISR_GIF5_Pos       (20U)

+#define BDMA_ISR_GIF5_Msk       (0x1UL << BDMA_ISR_GIF5_Pos)                   /*!< 0x00100000 */

+#define BDMA_ISR_GIF5           BDMA_ISR_GIF5_Msk                              /*!< Channel 5 Global interrupt flag */

+#define BDMA_ISR_TCIF5_Pos      (21U)

+#define BDMA_ISR_TCIF5_Msk      (0x1UL << BDMA_ISR_TCIF5_Pos)                  /*!< 0x00200000 */

+#define BDMA_ISR_TCIF5          BDMA_ISR_TCIF5_Msk                             /*!< Channel 5 Transfer Complete flag */

+#define BDMA_ISR_HTIF5_Pos      (22U)

+#define BDMA_ISR_HTIF5_Msk      (0x1UL << BDMA_ISR_HTIF5_Pos)                  /*!< 0x00400000 */

+#define BDMA_ISR_HTIF5          BDMA_ISR_HTIF5_Msk                             /*!< Channel 5 Half Transfer flag */

+#define BDMA_ISR_TEIF5_Pos      (23U)

+#define BDMA_ISR_TEIF5_Msk      (0x1UL << BDMA_ISR_TEIF5_Pos)                  /*!< 0x00800000 */

+#define BDMA_ISR_TEIF5          BDMA_ISR_TEIF5_Msk                             /*!< Channel 5 Transfer Error flag */

+#define BDMA_ISR_GIF6_Pos       (24U)

+#define BDMA_ISR_GIF6_Msk       (0x1UL << BDMA_ISR_GIF6_Pos)                   /*!< 0x01000000 */

+#define BDMA_ISR_GIF6           BDMA_ISR_GIF6_Msk                              /*!< Channel 6 Global interrupt flag */

+#define BDMA_ISR_TCIF6_Pos      (25U)

+#define BDMA_ISR_TCIF6_Msk      (0x1UL << BDMA_ISR_TCIF6_Pos)                  /*!< 0x02000000 */

+#define BDMA_ISR_TCIF6          BDMA_ISR_TCIF6_Msk                             /*!< Channel 6 Transfer Complete flag */

+#define BDMA_ISR_HTIF6_Pos      (26U)

+#define BDMA_ISR_HTIF6_Msk      (0x1UL << BDMA_ISR_HTIF6_Pos)                  /*!< 0x04000000 */

+#define BDMA_ISR_HTIF6          BDMA_ISR_HTIF6_Msk                             /*!< Channel 6 Half Transfer flag */

+#define BDMA_ISR_TEIF6_Pos      (27U)

+#define BDMA_ISR_TEIF6_Msk      (0x1UL << BDMA_ISR_TEIF6_Pos)                  /*!< 0x08000000 */

+#define BDMA_ISR_TEIF6          BDMA_ISR_TEIF6_Msk                             /*!< Channel 6 Transfer Error flag */

+#define BDMA_ISR_GIF7_Pos       (28U)

+#define BDMA_ISR_GIF7_Msk       (0x1UL << BDMA_ISR_GIF7_Pos)                   /*!< 0x10000000 */

+#define BDMA_ISR_GIF7           BDMA_ISR_GIF7_Msk                              /*!< Channel 7 Global interrupt flag */

+#define BDMA_ISR_TCIF7_Pos      (29U)

+#define BDMA_ISR_TCIF7_Msk      (0x1UL << BDMA_ISR_TCIF7_Pos)                  /*!< 0x20000000 */

+#define BDMA_ISR_TCIF7          BDMA_ISR_TCIF7_Msk                             /*!< Channel 7 Transfer Complete flag */

+#define BDMA_ISR_HTIF7_Pos      (30U)

+#define BDMA_ISR_HTIF7_Msk      (0x1UL << BDMA_ISR_HTIF7_Pos)                  /*!< 0x40000000 */

+#define BDMA_ISR_HTIF7          BDMA_ISR_HTIF7_Msk                             /*!< Channel 7 Half Transfer flag */

+#define BDMA_ISR_TEIF7_Pos      (31U)

+#define BDMA_ISR_TEIF7_Msk      (0x1UL << BDMA_ISR_TEIF7_Pos)                  /*!< 0x80000000 */

+#define BDMA_ISR_TEIF7          BDMA_ISR_TEIF7_Msk                             /*!< Channel 7 Transfer Error flag */

+

+/*******************  Bit definition for BDMA_IFCR register  *******************/

+#define BDMA_IFCR_CGIF0_Pos     (0U)

+#define BDMA_IFCR_CGIF0_Msk     (0x1UL << BDMA_IFCR_CGIF0_Pos)                 /*!< 0x00000001 */

+#define BDMA_IFCR_CGIF0         BDMA_IFCR_CGIF0_Msk                            /*!< Channel 0 Global interrupt clearr */

+#define BDMA_IFCR_CTCIF0_Pos    (1U)

+#define BDMA_IFCR_CTCIF0_Msk    (0x1UL << BDMA_IFCR_CTCIF0_Pos)                /*!< 0x00000002 */

+#define BDMA_IFCR_CTCIF0        BDMA_IFCR_CTCIF0_Msk                           /*!< Channel 0 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF0_Pos    (2U)

+#define BDMA_IFCR_CHTIF0_Msk    (0x1UL << BDMA_IFCR_CHTIF0_Pos)                /*!< 0x00000004 */

+#define BDMA_IFCR_CHTIF0        BDMA_IFCR_CHTIF0_Msk                           /*!< Channel 0 Half Transfer clear */

+#define BDMA_IFCR_CTEIF0_Pos    (3U)

+#define BDMA_IFCR_CTEIF0_Msk    (0x1UL << BDMA_IFCR_CTEIF0_Pos)                /*!< 0x00000008 */

+#define BDMA_IFCR_CTEIF0        BDMA_IFCR_CTEIF0_Msk                           /*!< Channel 0 Transfer Error clear */

+#define BDMA_IFCR_CGIF1_Pos     (4U)

+#define BDMA_IFCR_CGIF1_Msk     (0x1UL << BDMA_IFCR_CGIF1_Pos)                 /*!< 0x00000010 */

+#define BDMA_IFCR_CGIF1         BDMA_IFCR_CGIF1_Msk                            /*!< Channel 1 Global interrupt clear */

+#define BDMA_IFCR_CTCIF1_Pos    (5U)

+#define BDMA_IFCR_CTCIF1_Msk    (0x1UL << BDMA_IFCR_CTCIF1_Pos)                /*!< 0x00000020 */

+#define BDMA_IFCR_CTCIF1        BDMA_IFCR_CTCIF1_Msk                           /*!< Channel 1 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF1_Pos    (6U)

+#define BDMA_IFCR_CHTIF1_Msk    (0x1UL << BDMA_IFCR_CHTIF1_Pos)                /*!< 0x00000040 */

+#define BDMA_IFCR_CHTIF1        BDMA_IFCR_CHTIF1_Msk                           /*!< Channel 1 Half Transfer clear */

+#define BDMA_IFCR_CTEIF1_Pos    (7U)

+#define BDMA_IFCR_CTEIF1_Msk    (0x1UL << BDMA_IFCR_CTEIF1_Pos)                /*!< 0x00000080 */

+#define BDMA_IFCR_CTEIF1        BDMA_IFCR_CTEIF1_Msk                           /*!< Channel 1 Transfer Error clear */

+#define BDMA_IFCR_CGIF2_Pos     (8U)

+#define BDMA_IFCR_CGIF2_Msk     (0x1UL << BDMA_IFCR_CGIF2_Pos)                 /*!< 0x00000100 */

+#define BDMA_IFCR_CGIF2         BDMA_IFCR_CGIF2_Msk                            /*!< Channel 2 Global interrupt clear */

+#define BDMA_IFCR_CTCIF2_Pos    (9U)

+#define BDMA_IFCR_CTCIF2_Msk    (0x1UL << BDMA_IFCR_CTCIF2_Pos)                /*!< 0x00000200 */

+#define BDMA_IFCR_CTCIF2        BDMA_IFCR_CTCIF2_Msk                           /*!< Channel 2 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF2_Pos    (10U)

+#define BDMA_IFCR_CHTIF2_Msk    (0x1UL << BDMA_IFCR_CHTIF2_Pos)                /*!< 0x00000400 */

+#define BDMA_IFCR_CHTIF2        BDMA_IFCR_CHTIF2_Msk                           /*!< Channel 2 Half Transfer clear */

+#define BDMA_IFCR_CTEIF2_Pos    (11U)

+#define BDMA_IFCR_CTEIF2_Msk    (0x1UL << BDMA_IFCR_CTEIF2_Pos)                /*!< 0x00000800 */

+#define BDMA_IFCR_CTEIF2        BDMA_IFCR_CTEIF2_Msk                           /*!< Channel 2 Transfer Error clear */

+#define BDMA_IFCR_CGIF3_Pos     (12U)

+#define BDMA_IFCR_CGIF3_Msk     (0x1UL << BDMA_IFCR_CGIF3_Pos)                 /*!< 0x00001000 */

+#define BDMA_IFCR_CGIF3         BDMA_IFCR_CGIF3_Msk                            /*!< Channel 3 Global interrupt clear */

+#define BDMA_IFCR_CTCIF3_Pos    (13U)

+#define BDMA_IFCR_CTCIF3_Msk    (0x1UL << BDMA_IFCR_CTCIF3_Pos)                /*!< 0x00002000 */

+#define BDMA_IFCR_CTCIF3        BDMA_IFCR_CTCIF3_Msk                           /*!< Channel 3 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF3_Pos    (14U)

+#define BDMA_IFCR_CHTIF3_Msk    (0x1UL << BDMA_IFCR_CHTIF3_Pos)                /*!< 0x00004000 */

+#define BDMA_IFCR_CHTIF3        BDMA_IFCR_CHTIF3_Msk                           /*!< Channel 3 Half Transfer clear */

+#define BDMA_IFCR_CTEIF3_Pos    (15U)

+#define BDMA_IFCR_CTEIF3_Msk    (0x1UL << BDMA_IFCR_CTEIF3_Pos)                /*!< 0x00008000 */

+#define BDMA_IFCR_CTEIF3        BDMA_IFCR_CTEIF3_Msk                           /*!< Channel 3 Transfer Error clear */

+#define BDMA_IFCR_CGIF4_Pos     (16U)

+#define BDMA_IFCR_CGIF4_Msk     (0x1UL << BDMA_IFCR_CGIF4_Pos)                 /*!< 0x00010000 */

+#define BDMA_IFCR_CGIF4         BDMA_IFCR_CGIF4_Msk                            /*!< Channel 4 Global interrupt clear */

+#define BDMA_IFCR_CTCIF4_Pos    (17U)

+#define BDMA_IFCR_CTCIF4_Msk    (0x1UL << BDMA_IFCR_CTCIF4_Pos)                /*!< 0x00020000 */

+#define BDMA_IFCR_CTCIF4        BDMA_IFCR_CTCIF4_Msk                           /*!< Channel 4 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF4_Pos    (18U)

+#define BDMA_IFCR_CHTIF4_Msk    (0x1UL << BDMA_IFCR_CHTIF4_Pos)                /*!< 0x00040000 */

+#define BDMA_IFCR_CHTIF4        BDMA_IFCR_CHTIF4_Msk                           /*!< Channel 4 Half Transfer clear */

+#define BDMA_IFCR_CTEIF4_Pos    (19U)

+#define BDMA_IFCR_CTEIF4_Msk    (0x1UL << BDMA_IFCR_CTEIF4_Pos)                /*!< 0x00080000 */

+#define BDMA_IFCR_CTEIF4        BDMA_IFCR_CTEIF4_Msk                           /*!< Channel 4 Transfer Error clear */

+#define BDMA_IFCR_CGIF5_Pos     (20U)

+#define BDMA_IFCR_CGIF5_Msk     (0x1UL << BDMA_IFCR_CGIF5_Pos)                 /*!< 0x00100000 */

+#define BDMA_IFCR_CGIF5         BDMA_IFCR_CGIF5_Msk                            /*!< Channel 5 Global interrupt clear */

+#define BDMA_IFCR_CTCIF5_Pos    (21U)

+#define BDMA_IFCR_CTCIF5_Msk    (0x1UL << BDMA_IFCR_CTCIF5_Pos)                /*!< 0x00200000 */

+#define BDMA_IFCR_CTCIF5        BDMA_IFCR_CTCIF5_Msk                           /*!< Channel 5 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF5_Pos    (22U)

+#define BDMA_IFCR_CHTIF5_Msk    (0x1UL << BDMA_IFCR_CHTIF5_Pos)                /*!< 0x00400000 */

+#define BDMA_IFCR_CHTIF5        BDMA_IFCR_CHTIF5_Msk                           /*!< Channel 5 Half Transfer clear */

+#define BDMA_IFCR_CTEIF5_Pos    (23U)

+#define BDMA_IFCR_CTEIF5_Msk    (0x1UL << BDMA_IFCR_CTEIF5_Pos)                /*!< 0x00800000 */

+#define BDMA_IFCR_CTEIF5        BDMA_IFCR_CTEIF5_Msk                           /*!< Channel 5 Transfer Error clear */

+#define BDMA_IFCR_CGIF6_Pos     (24U)

+#define BDMA_IFCR_CGIF6_Msk     (0x1UL << BDMA_IFCR_CGIF6_Pos)                 /*!< 0x01000000 */

+#define BDMA_IFCR_CGIF6         BDMA_IFCR_CGIF6_Msk                            /*!< Channel 6 Global interrupt clear */

+#define BDMA_IFCR_CTCIF6_Pos    (25U)

+#define BDMA_IFCR_CTCIF6_Msk    (0x1UL << BDMA_IFCR_CTCIF6_Pos)                /*!< 0x02000000 */

+#define BDMA_IFCR_CTCIF6        BDMA_IFCR_CTCIF6_Msk                           /*!< Channel 6 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF6_Pos    (26U)

+#define BDMA_IFCR_CHTIF6_Msk    (0x1UL << BDMA_IFCR_CHTIF6_Pos)                /*!< 0x04000000 */

+#define BDMA_IFCR_CHTIF6        BDMA_IFCR_CHTIF6_Msk                           /*!< Channel 6 Half Transfer clear */

+#define BDMA_IFCR_CTEIF6_Pos    (27U)

+#define BDMA_IFCR_CTEIF6_Msk    (0x1UL << BDMA_IFCR_CTEIF6_Pos)                /*!< 0x08000000 */

+#define BDMA_IFCR_CTEIF6        BDMA_IFCR_CTEIF6_Msk                           /*!< Channel 6 Transfer Error clear */

+#define BDMA_IFCR_CGIF7_Pos     (28U)

+#define BDMA_IFCR_CGIF7_Msk     (0x1UL << BDMA_IFCR_CGIF7_Pos)                 /*!< 0x10000000 */

+#define BDMA_IFCR_CGIF7         BDMA_IFCR_CGIF7_Msk                            /*!< Channel 7 Global interrupt clear */

+#define BDMA_IFCR_CTCIF7_Pos    (29U)

+#define BDMA_IFCR_CTCIF7_Msk    (0x1UL << BDMA_IFCR_CTCIF7_Pos)                /*!< 0x20000000 */

+#define BDMA_IFCR_CTCIF7        BDMA_IFCR_CTCIF7_Msk                           /*!< Channel 7 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF7_Pos    (30U)

+#define BDMA_IFCR_CHTIF7_Msk    (0x1UL << BDMA_IFCR_CHTIF7_Pos)                /*!< 0x40000000 */

+#define BDMA_IFCR_CHTIF7        BDMA_IFCR_CHTIF7_Msk                           /*!< Channel 7 Half Transfer clear */

+#define BDMA_IFCR_CTEIF7_Pos    (31U)

+#define BDMA_IFCR_CTEIF7_Msk    (0x1UL << BDMA_IFCR_CTEIF7_Pos)                /*!< 0x80000000 */

+#define BDMA_IFCR_CTEIF7        BDMA_IFCR_CTEIF7_Msk                           /*!< Channel 7 Transfer Error clear */

+

+/*******************  Bit definition for BDMA_CCR register  ********************/

+#define BDMA_CCR_EN_Pos         (0U)

+#define BDMA_CCR_EN_Msk         (0x1UL << BDMA_CCR_EN_Pos)                     /*!< 0x00000001 */

+#define BDMA_CCR_EN             BDMA_CCR_EN_Msk                                /*!< Channel enable                      */

+#define BDMA_CCR_TCIE_Pos       (1U)

+#define BDMA_CCR_TCIE_Msk       (0x1UL << BDMA_CCR_TCIE_Pos)                   /*!< 0x00000002 */

+#define BDMA_CCR_TCIE           BDMA_CCR_TCIE_Msk                              /*!< Transfer complete interrupt enable  */

+#define BDMA_CCR_HTIE_Pos       (2U)

+#define BDMA_CCR_HTIE_Msk       (0x1UL << BDMA_CCR_HTIE_Pos)                   /*!< 0x00000004 */

+#define BDMA_CCR_HTIE           BDMA_CCR_HTIE_Msk                              /*!< Half Transfer interrupt enable      */

+#define BDMA_CCR_TEIE_Pos       (3U)

+#define BDMA_CCR_TEIE_Msk       (0x1UL << BDMA_CCR_TEIE_Pos)                   /*!< 0x00000008 */

+#define BDMA_CCR_TEIE           BDMA_CCR_TEIE_Msk                              /*!< Transfer error interrupt enable     */

+#define BDMA_CCR_DIR_Pos        (4U)

+#define BDMA_CCR_DIR_Msk        (0x1UL << BDMA_CCR_DIR_Pos)                    /*!< 0x00000010 */

+#define BDMA_CCR_DIR            BDMA_CCR_DIR_Msk                               /*!< Data transfer direction             */

+#define BDMA_CCR_CIRC_Pos       (5U)

+#define BDMA_CCR_CIRC_Msk       (0x1UL << BDMA_CCR_CIRC_Pos)                   /*!< 0x00000020 */

+#define BDMA_CCR_CIRC           BDMA_CCR_CIRC_Msk                              /*!< Circular mode                       */

+#define BDMA_CCR_PINC_Pos       (6U)

+#define BDMA_CCR_PINC_Msk       (0x1UL << BDMA_CCR_PINC_Pos)                   /*!< 0x00000040 */

+#define BDMA_CCR_PINC           BDMA_CCR_PINC_Msk                              /*!< Peripheral increment mode           */

+#define BDMA_CCR_MINC_Pos       (7U)

+#define BDMA_CCR_MINC_Msk       (0x1UL << BDMA_CCR_MINC_Pos)                   /*!< 0x00000080 */

+#define BDMA_CCR_MINC           BDMA_CCR_MINC_Msk                              /*!< Memory increment mode               */

+

+#define BDMA_CCR_PSIZE_Pos      (8U)

+#define BDMA_CCR_PSIZE_Msk      (0x3UL << BDMA_CCR_PSIZE_Pos)                  /*!< 0x00000300 */

+#define BDMA_CCR_PSIZE          BDMA_CCR_PSIZE_Msk                             /*!< PSIZE[1:0] bits (Peripheral size)   */

+#define BDMA_CCR_PSIZE_0        (0x1UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000100 */

+#define BDMA_CCR_PSIZE_1        (0x2UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000200 */

+

+#define BDMA_CCR_MSIZE_Pos      (10U)

+#define BDMA_CCR_MSIZE_Msk      (0x3UL << BDMA_CCR_MSIZE_Pos)                  /*!< 0x00000C00 */

+#define BDMA_CCR_MSIZE          BDMA_CCR_MSIZE_Msk                             /*!< MSIZE[1:0] bits (Memory size)       */

+#define BDMA_CCR_MSIZE_0        (0x1UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000400 */

+#define BDMA_CCR_MSIZE_1        (0x2UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000800 */

+

+#define BDMA_CCR_PL_Pos         (12U)

+#define BDMA_CCR_PL_Msk         (0x3UL << BDMA_CCR_PL_Pos)                     /*!< 0x00003000 */

+#define BDMA_CCR_PL             BDMA_CCR_PL_Msk                                /*!< PL[1:0] bits(Channel Priority level)*/

+#define BDMA_CCR_PL_0           (0x1UL << BDMA_CCR_PL_Pos)                      /*!< 0x00001000 */

+#define BDMA_CCR_PL_1           (0x2UL << BDMA_CCR_PL_Pos)                      /*!< 0x00002000 */

+

+#define BDMA_CCR_MEM2MEM_Pos    (14U)

+#define BDMA_CCR_MEM2MEM_Msk    (0x1UL << BDMA_CCR_MEM2MEM_Pos)                /*!< 0x00004000 */

+#define BDMA_CCR_MEM2MEM        BDMA_CCR_MEM2MEM_Msk                           /*!< Memory to memory mode               */

+#define BDMA_CCR_DBM_Pos        (15U)

+#define BDMA_CCR_DBM_Msk        (0x1UL << BDMA_CCR_DBM_Pos)                    /*!< 0x0000A000 */

+#define BDMA_CCR_DBM            BDMA_CCR_DBM_Msk                               /*!< Memory to memory mode               */

+#define BDMA_CCR_CT_Pos         (16U)

+#define BDMA_CCR_CT_Msk         (0x1UL << BDMA_CCR_CT_Pos)                     /*!< 0x00010000 */

+#define BDMA_CCR_CT             BDMA_CCR_CT_Msk                                /*!< Memory to memory mode               */

+

+/******************  Bit definition for BDMA_CNDTR register  *******************/

+#define BDMA_CNDTR_NDT_Pos      (0U)

+#define BDMA_CNDTR_NDT_Msk      (0xFFFFUL << BDMA_CNDTR_NDT_Pos)               /*!< 0x0000FFFF */

+#define BDMA_CNDTR_NDT          BDMA_CNDTR_NDT_Msk                             /*!< Number of data to Transfer          */

+

+/******************  Bit definition for BDMA_CPAR register  ********************/

+#define BDMA_CPAR_PA_Pos        (0U)

+#define BDMA_CPAR_PA_Msk        (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CPAR_PA            BDMA_CPAR_PA_Msk                               /*!< Peripheral Address                  */

+

+/******************  Bit definition for BDMA_CM0AR register  ********************/

+#define BDMA_CM0AR_MA_Pos        (0U)

+#define BDMA_CM0AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CM0AR_MA            BDMA_CM0AR_MA_Msk                               /*!< Memory Address                      */

+

+/******************  Bit definition for BDMA_CM1AR register  ********************/

+#define BDMA_CM1AR_MA_Pos        (0U)

+#define BDMA_CM1AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CM1AR_MA            BDMA_CM1AR_MA_Msk                               /*!< Memory Address                      */

+

+/******************************************************************************/

+/*                                                                            */

+/*                Ethernet MAC Registers bits definitions                     */

+/*                                                                            */

+/******************************************************************************/

+/* Bit definition for Ethernet MAC Configuration Register register */

+#define ETH_MACCR_ARP_Pos                             (31U)

+#define ETH_MACCR_ARP_Msk                             (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */

+#define ETH_MACCR_ARP                                 ETH_MACCR_ARP_Msk        /* ARP Offload Enable */

+#define ETH_MACCR_SARC_Pos                            (28U)

+#define ETH_MACCR_SARC_Msk                            (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */

+#define ETH_MACCR_SARC                                ETH_MACCR_SARC_Msk       /* Source Address Insertion or Replacement Control */

+#define ETH_MACCR_SARC_MTIATI                         ((uint32_t)0x00000000)   /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */

+#define ETH_MACCR_SARC_INSADDR0_Pos                   (29U)

+#define ETH_MACCR_SARC_INSADDR0_Msk                   (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */

+#define ETH_MACCR_SARC_INSADDR0                       ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */

+#define ETH_MACCR_SARC_INSADDR1_Pos                   (29U)

+#define ETH_MACCR_SARC_INSADDR1_Msk                   (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */

+#define ETH_MACCR_SARC_INSADDR1                       ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */

+#define ETH_MACCR_SARC_REPADDR0_Pos                   (28U)

+#define ETH_MACCR_SARC_REPADDR0_Msk                   (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */

+#define ETH_MACCR_SARC_REPADDR0                       ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */

+#define ETH_MACCR_SARC_REPADDR1_Pos                   (28U)

+#define ETH_MACCR_SARC_REPADDR1_Msk                   (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */

+#define ETH_MACCR_SARC_REPADDR1                       ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */

+#define ETH_MACCR_IPC_Pos                             (27U)

+#define ETH_MACCR_IPC_Msk                             (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */

+#define ETH_MACCR_IPC                                 ETH_MACCR_IPC_Msk        /* Checksum Offload */

+#define ETH_MACCR_IPG_Pos                             (24U)

+#define ETH_MACCR_IPG_Msk                             (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */

+#define ETH_MACCR_IPG                                 ETH_MACCR_IPG_Msk        /* Inter-Packet Gap */

+#define ETH_MACCR_IPG_96BIT                           ((uint32_t)0x00000000)   /* Minimum IFG between Packets during transmission is 96Bit */

+#define ETH_MACCR_IPG_88BIT                           ((uint32_t)0x01000000)   /* Minimum IFG between Packets during transmission is 88Bit */

+#define ETH_MACCR_IPG_80BIT                           ((uint32_t)0x02000000)   /* Minimum IFG between Packets during transmission is 80Bit */

+#define ETH_MACCR_IPG_72BIT                           ((uint32_t)0x03000000)   /* Minimum IFG between Packets during transmission is 72Bit */

+#define ETH_MACCR_IPG_64BIT                           ((uint32_t)0x04000000)   /* Minimum IFG between Packets during transmission is 64Bit */

+#define ETH_MACCR_IPG_56BIT                           ((uint32_t)0x05000000)   /* Minimum IFG between Packets during transmission is 56Bit */

+#define ETH_MACCR_IPG_48BIT                           ((uint32_t)0x06000000)   /* Minimum IFG between Packets during transmission is 48Bit */

+#define ETH_MACCR_IPG_40BIT                           ((uint32_t)0x07000000)   /* Minimum IFG between Packets during transmission is 40Bit */

+#define ETH_MACCR_GPSLCE_Pos                          (23U)

+#define ETH_MACCR_GPSLCE_Msk                          (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */

+#define ETH_MACCR_GPSLCE                              ETH_MACCR_GPSLCE_Msk     /* Giant Packet Size Limit Control Enable */

+#define ETH_MACCR_S2KP_Pos                            (22U)

+#define ETH_MACCR_S2KP_Msk                            (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */

+#define ETH_MACCR_S2KP                                ETH_MACCR_S2KP_Msk       /* IEEE 802.3as Support for 2K Packets */

+#define ETH_MACCR_CST_Pos                             (21U)

+#define ETH_MACCR_CST_Msk                             (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */

+#define ETH_MACCR_CST                                 ETH_MACCR_CST_Msk        /* CRC stripping for Type packets */

+#define ETH_MACCR_ACS_Pos                             (20U)

+#define ETH_MACCR_ACS_Msk                             (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */

+#define ETH_MACCR_ACS                                 ETH_MACCR_ACS_Msk        /* Automatic Pad or CRC Stripping */

+#define ETH_MACCR_WD_Pos                              (19U)

+#define ETH_MACCR_WD_Msk                              (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */

+#define ETH_MACCR_WD                                  ETH_MACCR_WD_Msk         /* Watchdog disable */

+#define ETH_MACCR_JD_Pos                              (17U)

+#define ETH_MACCR_JD_Msk                              (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */

+#define ETH_MACCR_JD                                  ETH_MACCR_JD_Msk         /* Jabber disable */

+#define ETH_MACCR_JE_Pos                              (16U)

+#define ETH_MACCR_JE_Msk                              (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */

+#define ETH_MACCR_JE                                  ETH_MACCR_JE_Msk         /* Jumbo Packet Enable */

+#define ETH_MACCR_FES_Pos                             (14U)

+#define ETH_MACCR_FES_Msk                             (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */

+#define ETH_MACCR_FES                                 ETH_MACCR_FES_Msk        /* Fast ethernet speed */

+#define ETH_MACCR_DM_Pos                              (13U)

+#define ETH_MACCR_DM_Msk                              (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */

+#define ETH_MACCR_DM                                  ETH_MACCR_DM_Msk         /* Duplex mode */

+#define ETH_MACCR_LM_Pos                              (12U)

+#define ETH_MACCR_LM_Msk                              (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */

+#define ETH_MACCR_LM                                  ETH_MACCR_LM_Msk         /* loopback mode */

+#define ETH_MACCR_ECRSFD_Pos                          (11U)

+#define ETH_MACCR_ECRSFD_Msk                          (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */

+#define ETH_MACCR_ECRSFD                              ETH_MACCR_ECRSFD_Msk     /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */

+#define ETH_MACCR_DO_Pos                              (10U)

+#define ETH_MACCR_DO_Msk                              (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */

+#define ETH_MACCR_DO                                  ETH_MACCR_DO_Msk         /* Disable Receive own  */

+#define ETH_MACCR_DCRS_Pos                            (9U)

+#define ETH_MACCR_DCRS_Msk                            (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */

+#define ETH_MACCR_DCRS                                ETH_MACCR_DCRS_Msk       /* Disable Carrier Sense During Transmission */

+#define ETH_MACCR_DR_Pos                              (8U)

+#define ETH_MACCR_DR_Msk                              (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */

+#define ETH_MACCR_DR                                  ETH_MACCR_DR_Msk         /* Disable Retry */

+#define ETH_MACCR_BL_Pos                              (5U)

+#define ETH_MACCR_BL_Msk                              (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */

+#define ETH_MACCR_BL                                  ETH_MACCR_BL_Msk         /* Back-off limit mask */

+#define ETH_MACCR_BL_10                               (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */

+#define ETH_MACCR_BL_8                                (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */

+#define ETH_MACCR_BL_4                                (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */

+#define ETH_MACCR_BL_1                                (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */

+#define ETH_MACCR_DC_Pos                              (4U)

+#define ETH_MACCR_DC_Msk                              (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */

+#define ETH_MACCR_DC                                  ETH_MACCR_DC_Msk         /* Defferal check */

+#define ETH_MACCR_PRELEN_Pos                          (2U)

+#define ETH_MACCR_PRELEN_Msk                          (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */

+#define ETH_MACCR_PRELEN                              ETH_MACCR_PRELEN_Msk     /* Preamble Length for Transmit packets */

+#define ETH_MACCR_PRELEN_7                            (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */

+#define ETH_MACCR_PRELEN_5                            (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */

+#define ETH_MACCR_PRELEN_3                            (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */

+#define ETH_MACCR_TE_Pos                              (1U)

+#define ETH_MACCR_TE_Msk                              (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */

+#define ETH_MACCR_TE                                  ETH_MACCR_TE_Msk         /* Transmitter enable */

+#define ETH_MACCR_RE_Pos                              (0U)

+#define ETH_MACCR_RE_Msk                              (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */

+#define ETH_MACCR_RE                                  ETH_MACCR_RE_Msk         /* Receiver enable */

+

+/* Bit definition for Ethernet MAC Extended Configuration Register register */

+#define ETH_MACECR_EIPG_Pos                           (25U)

+#define ETH_MACECR_EIPG_Msk                           (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */

+#define ETH_MACECR_EIPG                               ETH_MACECR_EIPG_Msk      /* Extended Inter-Packet Gap */

+#define ETH_MACECR_EIPGEN_Pos                         (24U)

+#define ETH_MACECR_EIPGEN_Msk                         (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */

+#define ETH_MACECR_EIPGEN                             ETH_MACECR_EIPGEN_Msk    /* Extended Inter-Packet Gap Enable */

+#define ETH_MACECR_USP_Pos                            (18U)

+#define ETH_MACECR_USP_Msk                            (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */

+#define ETH_MACECR_USP                                ETH_MACECR_USP_Msk       /* Unicast Slow Protocol Packet Detect */

+#define ETH_MACECR_SPEN_Pos                           (17U)

+#define ETH_MACECR_SPEN_Msk                           (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */

+#define ETH_MACECR_SPEN                               ETH_MACECR_SPEN_Msk      /* Slow Protocol Detection Enable */

+#define ETH_MACECR_DCRCC_Pos                          (16U)

+#define ETH_MACECR_DCRCC_Msk                          (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */

+#define ETH_MACECR_DCRCC                              ETH_MACECR_DCRCC_Msk     /* Disable CRC Checking for Received Packets */

+#define ETH_MACECR_GPSL_Pos                           (0U)

+#define ETH_MACECR_GPSL_Msk                           (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */

+#define ETH_MACECR_GPSL                               ETH_MACECR_GPSL_Msk      /* Giant Packet Size Limit */

+

+/* Bit definition for Ethernet MAC Packet Filter Register */

+#define ETH_MACPFR_RA_Pos                             (31U)

+#define ETH_MACPFR_RA_Msk                             (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */

+#define ETH_MACPFR_RA                                 ETH_MACPFR_RA_Msk        /* Receive all */

+#define ETH_MACPFR_DNTU_Pos                           (21U)

+#define ETH_MACPFR_DNTU_Msk                           (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */

+#define ETH_MACPFR_DNTU                               ETH_MACPFR_DNTU_Msk      /* Drop Non-TCP/UDP over IP Packets */

+#define ETH_MACPFR_IPFE_Pos                           (20U)

+#define ETH_MACPFR_IPFE_Msk                           (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */

+#define ETH_MACPFR_IPFE                               ETH_MACPFR_IPFE_Msk      /* Layer 3 and Layer 4 Filter Enable */

+#define ETH_MACPFR_VTFE_Pos                           (16U)

+#define ETH_MACPFR_VTFE_Msk                           (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */

+#define ETH_MACPFR_VTFE                               ETH_MACPFR_VTFE_Msk      /* VLAN Tag Filter Enable */

+#define ETH_MACPFR_HPF_Pos                            (10U)

+#define ETH_MACPFR_HPF_Msk                            (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */

+#define ETH_MACPFR_HPF                                ETH_MACPFR_HPF_Msk       /* Hash or perfect filter */

+#define ETH_MACPFR_SAF_Pos                            (9U)

+#define ETH_MACPFR_SAF_Msk                            (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */

+#define ETH_MACPFR_SAF                                ETH_MACPFR_SAF_Msk       /* Source address filter enable */

+#define ETH_MACPFR_SAIF_Pos                           (8U)

+#define ETH_MACPFR_SAIF_Msk                           (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */

+#define ETH_MACPFR_SAIF                               ETH_MACPFR_SAIF_Msk      /* SA inverse filtering */

+#define ETH_MACPFR_PCF_Pos                            (6U)

+#define ETH_MACPFR_PCF_Msk                            (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */

+#define ETH_MACPFR_PCF                                ETH_MACPFR_PCF_Msk       /* Pass control frames: 4 cases */

+#define ETH_MACPFR_PCF_BLOCKALL                       ((uint32_t)0x00000000)   /* MAC filters all control frames from reaching the application */

+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos         (6U)

+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk         (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */

+#define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA             ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */

+#define ETH_MACPFR_PCF_FORWARDALL_Pos                 (7U)

+#define ETH_MACPFR_PCF_FORWARDALL_Msk                 (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */

+#define ETH_MACPFR_PCF_FORWARDALL                     ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */

+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos    (6U)

+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk    (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */

+#define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER        ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */

+#define ETH_MACPFR_DBF_Pos                            (5U)

+#define ETH_MACPFR_DBF_Msk                            (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */

+#define ETH_MACPFR_DBF                                ETH_MACPFR_DBF_Msk       /* Disable Broadcast Packets */

+#define ETH_MACPFR_PM_Pos                             (4U)

+#define ETH_MACPFR_PM_Msk                             (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */

+#define ETH_MACPFR_PM                                 ETH_MACPFR_PM_Msk        /* Pass all mutlicast */

+#define ETH_MACPFR_DAIF_Pos                           (3U)

+#define ETH_MACPFR_DAIF_Msk                           (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */

+#define ETH_MACPFR_DAIF                               ETH_MACPFR_DAIF_Msk      /* DA Inverse filtering */

+#define ETH_MACPFR_HMC_Pos                            (2U)

+#define ETH_MACPFR_HMC_Msk                            (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */

+#define ETH_MACPFR_HMC                                ETH_MACPFR_HMC_Msk       /* Hash multicast */

+#define ETH_MACPFR_HUC_Pos                            (1U)

+#define ETH_MACPFR_HUC_Msk                            (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */

+#define ETH_MACPFR_HUC                                ETH_MACPFR_HUC_Msk       /* Hash unicast */

+#define ETH_MACPFR_PR_Pos                             (0U)

+#define ETH_MACPFR_PR_Msk                             (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */

+#define ETH_MACPFR_PR                                 ETH_MACPFR_PR_Msk        /* Promiscuous mode */

+

+/* Bit definition for Ethernet MAC Watchdog Timeout Register */

+#define ETH_MACWTR_PWE_Pos                            (8U)

+#define ETH_MACWTR_PWE_Msk                            (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */

+#define ETH_MACWTR_PWE                                ETH_MACWTR_PWE_Msk       /* Programmable Watchdog Enable */

+#define ETH_MACWTR_WTO_Pos                            (0U)

+#define ETH_MACWTR_WTO_Msk                            (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */

+#define ETH_MACWTR_WTO                                ETH_MACWTR_WTO_Msk       /* Watchdog Timeout */

+#define ETH_MACWTR_WTO_2KB                            ((uint32_t)0x00000000)   /* Maximum received packet length 2KB*/

+#define ETH_MACWTR_WTO_3KB                            ((uint32_t)0x00000001)   /* Maximum received packet length 3KB */

+#define ETH_MACWTR_WTO_4KB                            ((uint32_t)0x00000002)   /* Maximum received packet length 4KB */

+#define ETH_MACWTR_WTO_5KB                            ((uint32_t)0x00000003)   /* Maximum received packet length 5KB */

+#define ETH_MACWTR_WTO_6KB                            ((uint32_t)0x00000004)   /* Maximum received packet length 6KB */

+#define ETH_MACWTR_WTO_7KB                            ((uint32_t)0x00000005)   /* Maximum received packet length 7KB */

+#define ETH_MACWTR_WTO_8KB                            ((uint32_t)0x00000006)   /* Maximum received packet length 8KB */

+#define ETH_MACWTR_WTO_9KB                            ((uint32_t)0x00000007)   /* Maximum received packet length 9KB */

+#define ETH_MACWTR_WTO_10KB                           ((uint32_t)0x00000008)   /* Maximum received packet length 10KB */

+#define ETH_MACWTR_WTO_11KB                           ((uint32_t)0x00000009)   /* Maximum received packet length 11KB */

+#define ETH_MACWTR_WTO_12KB                           ((uint32_t)0x0000000A)   /* Maximum received packet length 12KB */

+#define ETH_MACWTR_WTO_13KB                           ((uint32_t)0x0000000B)   /* Maximum received packet length 13KB */

+#define ETH_MACWTR_WTO_14KB                           ((uint32_t)0x0000000C)   /* Maximum received packet length 14KB */

+#define ETH_MACWTR_WTO_15KB                           ((uint32_t)0x0000000D)   /* Maximum received packet length 15KB */

+#define ETH_MACWTR_WTO_16KB                           ((uint32_t)0x0000000E)   /* Maximum received packet length 16KB */

+

+/* Bit definition for Ethernet MAC Hash Table High Register */

+#define ETH_MACHTHR_HTH_Pos                           (0U)

+#define ETH_MACHTHR_HTH_Msk                           (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACHTHR_HTH                               ETH_MACHTHR_HTH_Msk      /* Hash table high */

+

+/* Bit definition for Ethernet MAC Hash Table Low Register */

+#define ETH_MACHTLR_HTL_Pos                           (0U)

+#define ETH_MACHTLR_HTL_Msk                           (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACHTLR_HTL                               ETH_MACHTLR_HTL_Msk      /* Hash table low */

+

+/* Bit definition for Ethernet MAC VLAN Tag Register */

+#define ETH_MACVTR_EIVLRXS_Pos                        (31U)

+#define ETH_MACVTR_EIVLRXS_Msk                        (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */

+#define ETH_MACVTR_EIVLRXS                            ETH_MACVTR_EIVLRXS_Msk   /* Enable Inner VLAN Tag in Rx Status */

+#define ETH_MACVTR_EIVLS_Pos                          (28U)

+#define ETH_MACVTR_EIVLS_Msk                          (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */

+#define ETH_MACVTR_EIVLS                              ETH_MACVTR_EIVLS_Msk     /* Enable Inner VLAN Tag Stripping on Receive */

+#define ETH_MACVTR_EIVLS_DONOTSTRIP                   ((uint32_t)0x00000000)   /* Do not strip */

+#define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos              (28U)

+#define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk              (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */

+#define ETH_MACVTR_EIVLS_STRIPIFPASS                  ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */

+#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos             (29U)

+#define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk             (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */

+#define ETH_MACVTR_EIVLS_STRIPIFFAILS                 ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */

+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos              (28U)

+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk              (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */

+#define ETH_MACVTR_EIVLS_ALWAYSSTRIP                  ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */

+#define ETH_MACVTR_ERIVLT_Pos                         (27U)

+#define ETH_MACVTR_ERIVLT_Msk                         (0x1UL << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */

+#define ETH_MACVTR_ERIVLT                             ETH_MACVTR_ERIVLT_Msk    /* Enable Inner VLAN Tag */

+#define ETH_MACVTR_EDVLP_Pos                          (26U)

+#define ETH_MACVTR_EDVLP_Msk                          (0x1UL << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */

+#define ETH_MACVTR_EDVLP                              ETH_MACVTR_EDVLP_Msk     /* Enable Double VLAN Processing */

+#define ETH_MACVTR_VTHM_Pos                           (25U)

+#define ETH_MACVTR_VTHM_Msk                           (0x1UL << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */

+#define ETH_MACVTR_VTHM                               ETH_MACVTR_VTHM_Msk      /* VLAN Tag Hash Table Match Enable */

+#define ETH_MACVTR_EVLRXS_Pos                         (24U)

+#define ETH_MACVTR_EVLRXS_Msk                         (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */

+#define ETH_MACVTR_EVLRXS                             ETH_MACVTR_EVLRXS_Msk    /* Enable VLAN Tag in Rx status */

+#define ETH_MACVTR_EVLS_Pos                           (21U)

+#define ETH_MACVTR_EVLS_Msk                           (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */

+#define ETH_MACVTR_EVLS                               ETH_MACVTR_EVLS_Msk      /* Enable VLAN Tag Stripping on Receive */

+#define ETH_MACVTR_EVLS_DONOTSTRIP                    ((uint32_t)0x00000000)   /* Do not strip */

+#define ETH_MACVTR_EVLS_STRIPIFPASS_Pos               (21U)

+#define ETH_MACVTR_EVLS_STRIPIFPASS_Msk               (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */

+#define ETH_MACVTR_EVLS_STRIPIFPASS                   ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */

+#define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos              (22U)

+#define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk              (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */

+#define ETH_MACVTR_EVLS_STRIPIFFAILS                  ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */

+#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos               (21U)

+#define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk               (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */

+#define ETH_MACVTR_EVLS_ALWAYSSTRIP                   ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */

+#define ETH_MACVTR_DOVLTC_Pos                         (20U)

+#define ETH_MACVTR_DOVLTC_Msk                         (0x1UL << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */

+#define ETH_MACVTR_DOVLTC                             ETH_MACVTR_DOVLTC_Msk    /* Disable VLAN Type Check */

+#define ETH_MACVTR_ERSVLM_Pos                         (19U)

+#define ETH_MACVTR_ERSVLM_Msk                         (0x1UL << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */

+#define ETH_MACVTR_ERSVLM                             ETH_MACVTR_ERSVLM_Msk    /* Enable Receive S-VLAN Match */

+#define ETH_MACVTR_ESVL_Pos                           (18U)

+#define ETH_MACVTR_ESVL_Msk                           (0x1UL << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */

+#define ETH_MACVTR_ESVL                               ETH_MACVTR_ESVL_Msk      /* Enable S-VLAN */

+#define ETH_MACVTR_VTIM_Pos                           (17U)

+#define ETH_MACVTR_VTIM_Msk                           (0x1UL << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */

+#define ETH_MACVTR_VTIM                               ETH_MACVTR_VTIM_Msk      /* VLAN Tag Inverse Match Enable */

+#define ETH_MACVTR_ETV_Pos                            (16U)

+#define ETH_MACVTR_ETV_Msk                            (0x1UL << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */

+#define ETH_MACVTR_ETV                                ETH_MACVTR_ETV_Msk       /* Enable 12-Bit VLAN Tag Comparison */

+#define ETH_MACVTR_VL_Pos                             (0U)

+#define ETH_MACVTR_VL_Msk                             (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */

+#define ETH_MACVTR_VL                                 ETH_MACVTR_VL_Msk        /* VLAN Tag Identifier for Receive Packets */

+#define ETH_MACVTR_VL_UP_Pos                          (13U)

+#define ETH_MACVTR_VL_UP_Msk                          (0x7UL << ETH_MACVTR_VL_UP_Pos) /*!< 0x0000E000 */

+#define ETH_MACVTR_VL_UP                              ETH_MACVTR_VL_UP_Msk     /* User Priority */

+#define ETH_MACVTR_VL_CFIDEI_Pos                      (12U)

+#define ETH_MACVTR_VL_CFIDEI_Msk                      (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos) /*!< 0x00001000 */

+#define ETH_MACVTR_VL_CFIDEI                          ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */

+#define ETH_MACVTR_VL_VID_Pos                         (0U)

+#define ETH_MACVTR_VL_VID_Msk                         (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */

+#define ETH_MACVTR_VL_VID                             ETH_MACVTR_VL_VID_Msk    /* VLAN Identifier field of VLAN tag */

+

+/* Bit definition for Ethernet MAC VLAN Hash Table Register */

+#define ETH_MACVHTR_VLHT_Pos                          (0U)

+#define ETH_MACVHTR_VLHT_Msk                          (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACVHTR_VLHT                              ETH_MACVHTR_VLHT_Msk     /* VLAN Hash Table */

+

+/* Bit definition for Ethernet MAC VLAN Incl Register */

+#define ETH_MACVIR_VLTI_Pos                           (20U)

+#define ETH_MACVIR_VLTI_Msk                           (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */

+#define ETH_MACVIR_VLTI                               ETH_MACVIR_VLTI_Msk      /* VLAN Tag Input */

+#define ETH_MACVIR_CSVL_Pos                           (19U)

+#define ETH_MACVIR_CSVL_Msk                           (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */

+#define ETH_MACVIR_CSVL                               ETH_MACVIR_CSVL_Msk      /* C-VLAN or S-VLAN */

+#define ETH_MACVIR_VLP_Pos                            (18U)

+#define ETH_MACVIR_VLP_Msk                            (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */

+#define ETH_MACVIR_VLP                                ETH_MACVIR_VLP_Msk       /* VLAN Priority Control */

+#define ETH_MACVIR_VLC_Pos                            (16U)

+#define ETH_MACVIR_VLC_Msk                            (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */

+#define ETH_MACVIR_VLC                                ETH_MACVIR_VLC_Msk       /* VLAN Tag Control in Transmit Packets */

+#define ETH_MACVIR_VLC_NOVLANTAG                      ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */

+#define ETH_MACVIR_VLC_VLANTAGDELETE_Pos              (16U)

+#define ETH_MACVIR_VLC_VLANTAGDELETE_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */

+#define ETH_MACVIR_VLC_VLANTAGDELETE                  ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */

+#define ETH_MACVIR_VLC_VLANTAGINSERT_Pos              (17U)

+#define ETH_MACVIR_VLC_VLANTAGINSERT_Msk              (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */

+#define ETH_MACVIR_VLC_VLANTAGINSERT                  ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */

+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos             (16U)

+#define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk             (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */

+#define ETH_MACVIR_VLC_VLANTAGREPLACE                 ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */

+#define ETH_MACVIR_VLT_Pos                            (0U)

+#define ETH_MACVIR_VLT_Msk                            (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACVIR_VLT                                ETH_MACVIR_VLT_Msk       /* VLAN Tag for Transmit Packets */

+#define ETH_MACVIR_VLT_UP_Pos                         (13U)

+#define ETH_MACVIR_VLT_UP_Msk                         (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */

+#define ETH_MACVIR_VLT_UP                             ETH_MACVIR_VLT_UP_Msk    /* User Priority */

+#define ETH_MACVIR_VLT_CFIDEI_Pos                     (12U)

+#define ETH_MACVIR_VLT_CFIDEI_Msk                     (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */

+#define ETH_MACVIR_VLT_CFIDEI                         ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */

+#define ETH_MACVIR_VLT_VID_Pos                        (0U)

+#define ETH_MACVIR_VLT_VID_Msk                        (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */

+#define ETH_MACVIR_VLT_VID                            ETH_MACVIR_VLT_VID_Msk   /* VLAN Identifier field of VLAN tag */

+

+/* Bit definition for Ethernet MAC Inner_VLAN Incl Register */

+#define ETH_MACIVIR_VLTI_Pos                          (20U)

+#define ETH_MACIVIR_VLTI_Msk                          (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */

+#define ETH_MACIVIR_VLTI                              ETH_MACIVIR_VLTI_Msk     /* VLAN Tag Input */

+#define ETH_MACIVIR_CSVL_Pos                          (19U)

+#define ETH_MACIVIR_CSVL_Msk                          (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */

+#define ETH_MACIVIR_CSVL                              ETH_MACIVIR_CSVL_Msk     /* C-VLAN or S-VLAN */

+#define ETH_MACIVIR_VLP_Pos                           (18U)

+#define ETH_MACIVIR_VLP_Msk                           (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */

+#define ETH_MACIVIR_VLP                               ETH_MACIVIR_VLP_Msk      /* VLAN Priority Control */

+#define ETH_MACIVIR_VLC_Pos                           (16U)

+#define ETH_MACIVIR_VLC_Msk                           (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */

+#define ETH_MACIVIR_VLC                               ETH_MACIVIR_VLC_Msk      /* VLAN Tag Control in Transmit Packets */

+#define ETH_MACIVIR_VLC_NOVLANTAG                     ((uint32_t)0x00000000)   /* No VLAN tag deletion, insertion, or replacement */

+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos             (16U)

+#define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */

+#define ETH_MACIVIR_VLC_VLANTAGDELETE                 ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */

+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos             (17U)

+#define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk             (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */

+#define ETH_MACIVIR_VLC_VLANTAGINSERT                 ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */

+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos            (16U)

+#define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk            (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */

+#define ETH_MACIVIR_VLC_VLANTAGREPLACE                ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */

+#define ETH_MACIVIR_VLT_Pos                           (0U)

+#define ETH_MACIVIR_VLT_Msk                           (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACIVIR_VLT                               ETH_MACIVIR_VLT_Msk      /* VLAN Tag for Transmit Packets */

+#define ETH_MACIVIR_VLT_UP_Pos                        (13U)

+#define ETH_MACIVIR_VLT_UP_Msk                        (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */

+#define ETH_MACIVIR_VLT_UP                            ETH_MACIVIR_VLT_UP_Msk   /* User Priority */

+#define ETH_MACIVIR_VLT_CFIDEI_Pos                    (12U)

+#define ETH_MACIVIR_VLT_CFIDEI_Msk                    (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */

+#define ETH_MACIVIR_VLT_CFIDEI                        ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */

+#define ETH_MACIVIR_VLT_VID_Pos                       (0U)

+#define ETH_MACIVIR_VLT_VID_Msk                       (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */

+#define ETH_MACIVIR_VLT_VID                           ETH_MACIVIR_VLT_VID_Msk  /* VLAN Identifier field of VLAN tag */

+

+/* Bit definition for Ethernet MAC Tx Flow Ctrl Register */

+#define ETH_MACTFCR_PT_Pos                            (16U)

+#define ETH_MACTFCR_PT_Msk                            (0xFFFFUL << ETH_MACTFCR_PT_Pos) /*!< 0xFFFF0000 */

+#define ETH_MACTFCR_PT                                ETH_MACTFCR_PT_Msk       /* Pause Time */

+#define ETH_MACTFCR_DZPQ_Pos                          (7U)

+#define ETH_MACTFCR_DZPQ_Msk                          (0x1UL << ETH_MACTFCR_DZPQ_Pos) /*!< 0x00000080 */

+#define ETH_MACTFCR_DZPQ                              ETH_MACTFCR_DZPQ_Msk     /* Disable Zero-Quanta Pause */

+#define ETH_MACTFCR_PLT_Pos                           (4U)

+#define ETH_MACTFCR_PLT_Msk                           (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */

+#define ETH_MACTFCR_PLT                               ETH_MACTFCR_PLT_Msk      /* Pause Low Threshold */

+#define ETH_MACTFCR_PLT_MINUS4                        ((uint32_t)0x00000000)   /* Pause time minus 4 slot times */

+#define ETH_MACTFCR_PLT_MINUS28_Pos                   (4U)

+#define ETH_MACTFCR_PLT_MINUS28_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */

+#define ETH_MACTFCR_PLT_MINUS28                       ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */

+#define ETH_MACTFCR_PLT_MINUS36_Pos                   (5U)

+#define ETH_MACTFCR_PLT_MINUS36_Msk                   (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */

+#define ETH_MACTFCR_PLT_MINUS36                       ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */

+#define ETH_MACTFCR_PLT_MINUS144_Pos                  (4U)

+#define ETH_MACTFCR_PLT_MINUS144_Msk                  (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */

+#define ETH_MACTFCR_PLT_MINUS144                      ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */

+#define ETH_MACTFCR_PLT_MINUS256_Pos                  (6U)

+#define ETH_MACTFCR_PLT_MINUS256_Msk                  (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */

+#define ETH_MACTFCR_PLT_MINUS256                      ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */

+#define ETH_MACTFCR_PLT_MINUS512_Pos                  (4U)

+#define ETH_MACTFCR_PLT_MINUS512_Msk                  (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */

+#define ETH_MACTFCR_PLT_MINUS512                      ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */

+#define ETH_MACTFCR_TFE_Pos                           (1U)

+#define ETH_MACTFCR_TFE_Msk                           (0x1UL << ETH_MACTFCR_TFE_Pos) /*!< 0x00000002 */

+#define ETH_MACTFCR_TFE                               ETH_MACTFCR_TFE_Msk      /* Transmit Flow Control Enable */

+#define ETH_MACTFCR_FCB_Pos                           (0U)

+#define ETH_MACTFCR_FCB_Msk                           (0x1UL << ETH_MACTFCR_FCB_Pos) /*!< 0x00000001 */

+#define ETH_MACTFCR_FCB                               ETH_MACTFCR_FCB_Msk      /* Flow Control Busy or Backpressure Activate */

+

+/* Bit definition for Ethernet MAC Rx Flow Ctrl Register */

+#define ETH_MACRFCR_UP_Pos                            (1U)

+#define ETH_MACRFCR_UP_Msk                            (0x1UL << ETH_MACRFCR_UP_Pos) /*!< 0x00000002 */

+#define ETH_MACRFCR_UP                                ETH_MACRFCR_UP_Msk       /* Unicast Pause Packet Detect */

+#define ETH_MACRFCR_RFE_Pos                           (0U)

+#define ETH_MACRFCR_RFE_Msk                           (0x1UL << ETH_MACRFCR_RFE_Pos) /*!< 0x00000001 */

+#define ETH_MACRFCR_RFE                               ETH_MACRFCR_RFE_Msk      /* Receive Flow Control Enable */

+

+/* Bit definition for Ethernet MAC Interrupt Status Register */

+#define ETH_MACISR_RXSTSIS_Pos                        (14U)

+#define ETH_MACISR_RXSTSIS_Msk                        (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */

+#define ETH_MACISR_RXSTSIS                            ETH_MACISR_RXSTSIS_Msk   /* Receive Status Interrupt */

+#define ETH_MACISR_TXSTSIS_Pos                        (13U)

+#define ETH_MACISR_TXSTSIS_Msk                        (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */

+#define ETH_MACISR_TXSTSIS                            ETH_MACISR_TXSTSIS_Msk   /* Transmit Status Interrupt */

+#define ETH_MACISR_TSIS_Pos                           (12U)

+#define ETH_MACISR_TSIS_Msk                           (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */

+#define ETH_MACISR_TSIS                               ETH_MACISR_TSIS_Msk      /* Timestamp Interrupt Status */

+#define ETH_MACISR_MMCTXIS_Pos                        (10U)

+#define ETH_MACISR_MMCTXIS_Msk                        (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */

+#define ETH_MACISR_MMCTXIS                            ETH_MACISR_MMCTXIS_Msk   /* MMC Transmit Interrupt Status */

+#define ETH_MACISR_MMCRXIS_Pos                        (9U)

+#define ETH_MACISR_MMCRXIS_Msk                        (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */

+#define ETH_MACISR_MMCRXIS                            ETH_MACISR_MMCRXIS_Msk   /* MMC Receive Interrupt Status */

+#define ETH_MACISR_MMCIS_Pos                          (8U)

+#define ETH_MACISR_MMCIS_Msk                          (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */

+#define ETH_MACISR_MMCIS                              ETH_MACISR_MMCIS_Msk     /* MMC Interrupt Status */

+#define ETH_MACISR_LPIIS_Pos                          (5U)

+#define ETH_MACISR_LPIIS_Msk                          (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */

+#define ETH_MACISR_LPIIS                              ETH_MACISR_LPIIS_Msk     /* LPI Interrupt Status */

+#define ETH_MACISR_PMTIS_Pos                          (4U)

+#define ETH_MACISR_PMTIS_Msk                          (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */

+#define ETH_MACISR_PMTIS                              ETH_MACISR_PMTIS_Msk     /* PMT Interrupt Status */

+#define ETH_MACISR_PHYIS_Pos                          (3U)

+#define ETH_MACISR_PHYIS_Msk                          (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */

+#define ETH_MACISR_PHYIS                              ETH_MACISR_PHYIS_Msk     /* PHY Interrupt */

+

+/* Bit definition for Ethernet MAC Interrupt Enable Register */

+#define ETH_MACIER_RXSTSIE_Pos                        (14U)

+#define ETH_MACIER_RXSTSIE_Msk                        (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */

+#define ETH_MACIER_RXSTSIE                            ETH_MACIER_RXSTSIE_Msk   /* Receive Status Interrupt Enable */

+#define ETH_MACIER_TXSTSIE_Pos                        (13U)

+#define ETH_MACIER_TXSTSIE_Msk                        (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */

+#define ETH_MACIER_TXSTSIE                            ETH_MACIER_TXSTSIE_Msk   /* Transmit Status Interrupt Enable */

+#define ETH_MACIER_TSIE_Pos                           (12U)

+#define ETH_MACIER_TSIE_Msk                           (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */

+#define ETH_MACIER_TSIE                               ETH_MACIER_TSIE_Msk      /* Timestamp Interrupt Enable */

+#define ETH_MACIER_LPIIE_Pos                          (5U)

+#define ETH_MACIER_LPIIE_Msk                          (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */

+#define ETH_MACIER_LPIIE                              ETH_MACIER_LPIIE_Msk     /* LPI Interrupt Enable */

+#define ETH_MACIER_PMTIE_Pos                          (4U)

+#define ETH_MACIER_PMTIE_Msk                          (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */

+#define ETH_MACIER_PMTIE                              ETH_MACIER_PMTIE_Msk     /* PMT Interrupt Enable */

+#define ETH_MACIER_PHYIE_Pos                          (3U)

+#define ETH_MACIER_PHYIE_Msk                          (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */

+#define ETH_MACIER_PHYIE                              ETH_MACIER_PHYIE_Msk     /* PHY Interrupt Enable */

+

+/* Bit definition for Ethernet MAC Rx Tx Status Register */

+#define ETH_MACRXTXSR_RWT_Pos                         (8U)

+#define ETH_MACRXTXSR_RWT_Msk                         (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */

+#define ETH_MACRXTXSR_RWT                             ETH_MACRXTXSR_RWT_Msk    /* Receive Watchdog Timeout */

+#define ETH_MACRXTXSR_EXCOL_Pos                       (5U)

+#define ETH_MACRXTXSR_EXCOL_Msk                       (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */

+#define ETH_MACRXTXSR_EXCOL                           ETH_MACRXTXSR_EXCOL_Msk  /* Excessive Collisions */

+#define ETH_MACRXTXSR_LCOL_Pos                        (4U)

+#define ETH_MACRXTXSR_LCOL_Msk                        (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */

+#define ETH_MACRXTXSR_LCOL                            ETH_MACRXTXSR_LCOL_Msk   /* Late Collision */

+#define ETH_MACRXTXSR_EXDEF_Pos                       (3U)

+#define ETH_MACRXTXSR_EXDEF_Msk                       (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */

+#define ETH_MACRXTXSR_EXDEF                           ETH_MACRXTXSR_EXDEF_Msk  /* Excessive Deferral */

+#define ETH_MACRXTXSR_LCARR_Pos                       (2U)

+#define ETH_MACRXTXSR_LCARR_Msk                       (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */

+#define ETH_MACRXTXSR_LCARR                           ETH_MACRXTXSR_LCARR_Msk  /* Loss of Carrier */

+#define ETH_MACRXTXSR_NCARR_Pos                       (1U)

+#define ETH_MACRXTXSR_NCARR_Msk                       (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */

+#define ETH_MACRXTXSR_NCARR                           ETH_MACRXTXSR_NCARR_Msk  /* No Carrier */

+#define ETH_MACRXTXSR_TJT_Pos                         (0U)

+#define ETH_MACRXTXSR_TJT_Msk                         (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */

+#define ETH_MACRXTXSR_TJT                             ETH_MACRXTXSR_TJT_Msk    /* Transmit Jabber Timeout */

+

+/* Bit definition for Ethernet MAC PMT Control Status Register */

+#define ETH_MACPCSR_RWKFILTRST_Pos                    (31U)

+#define ETH_MACPCSR_RWKFILTRST_Msk                    (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */

+#define ETH_MACPCSR_RWKFILTRST                        ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */

+#define ETH_MACPCSR_RWKPTR_Pos                        (24U)

+#define ETH_MACPCSR_RWKPTR_Msk                        (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */

+#define ETH_MACPCSR_RWKPTR                            ETH_MACPCSR_RWKPTR_Msk   /* Remote Wake-up FIFO Pointer */

+#define ETH_MACPCSR_RWKPFE_Pos                        (10U)

+#define ETH_MACPCSR_RWKPFE_Msk                        (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */

+#define ETH_MACPCSR_RWKPFE                            ETH_MACPCSR_RWKPFE_Msk   /* Remote Wake-up Packet Forwarding Enable */

+#define ETH_MACPCSR_GLBLUCAST_Pos                     (9U)

+#define ETH_MACPCSR_GLBLUCAST_Msk                     (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */

+#define ETH_MACPCSR_GLBLUCAST                         ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */

+#define ETH_MACPCSR_RWKPRCVD_Pos                      (6U)

+#define ETH_MACPCSR_RWKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */

+#define ETH_MACPCSR_RWKPRCVD                          ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */

+#define ETH_MACPCSR_MGKPRCVD_Pos                      (5U)

+#define ETH_MACPCSR_MGKPRCVD_Msk                      (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */

+#define ETH_MACPCSR_MGKPRCVD                          ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */

+#define ETH_MACPCSR_RWKPKTEN_Pos                      (2U)

+#define ETH_MACPCSR_RWKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */

+#define ETH_MACPCSR_RWKPKTEN                          ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */

+#define ETH_MACPCSR_MGKPKTEN_Pos                      (1U)

+#define ETH_MACPCSR_MGKPKTEN_Msk                      (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */

+#define ETH_MACPCSR_MGKPKTEN                          ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */

+#define ETH_MACPCSR_PWRDWN_Pos                        (0U)

+#define ETH_MACPCSR_PWRDWN_Msk                        (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */

+#define ETH_MACPCSR_PWRDWN                            ETH_MACPCSR_PWRDWN_Msk   /* Power Down */

+

+/* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */

+#define ETH_MACRWUPFR_D_Pos                           (0U)

+#define ETH_MACRWUPFR_D_Msk                           (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACRWUPFR_D                               ETH_MACRWUPFR_D_Msk      /* Wake-up Packet filter register data */

+

+/* Bit definition for Ethernet MAC LPI Control Status Register */

+#define ETH_MACLCSR_LPITCSE_Pos                       (21U)

+#define ETH_MACLCSR_LPITCSE_Msk                       (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */

+#define ETH_MACLCSR_LPITCSE                           ETH_MACLCSR_LPITCSE_Msk  /* LPI Tx Clock Stop Enable */

+#define ETH_MACLCSR_LPITE_Pos                         (20U)

+#define ETH_MACLCSR_LPITE_Msk                         (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */

+#define ETH_MACLCSR_LPITE                             ETH_MACLCSR_LPITE_Msk    /* LPI Timer Enable */

+#define ETH_MACLCSR_LPITXA_Pos                        (19U)

+#define ETH_MACLCSR_LPITXA_Msk                        (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */

+#define ETH_MACLCSR_LPITXA                            ETH_MACLCSR_LPITXA_Msk   /* LPI Tx Automate */

+#define ETH_MACLCSR_PLS_Pos                           (17U)

+#define ETH_MACLCSR_PLS_Msk                           (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */

+#define ETH_MACLCSR_PLS                               ETH_MACLCSR_PLS_Msk      /* PHY Link Status */

+#define ETH_MACLCSR_LPIEN_Pos                         (16U)

+#define ETH_MACLCSR_LPIEN_Msk                         (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */

+#define ETH_MACLCSR_LPIEN                             ETH_MACLCSR_LPIEN_Msk    /* LPI Enable */

+#define ETH_MACLCSR_RLPIST_Pos                        (9U)

+#define ETH_MACLCSR_RLPIST_Msk                        (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */

+#define ETH_MACLCSR_RLPIST                            ETH_MACLCSR_RLPIST_Msk   /* Receive LPI State */

+#define ETH_MACLCSR_TLPIST_Pos                        (8U)

+#define ETH_MACLCSR_TLPIST_Msk                        (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */

+#define ETH_MACLCSR_TLPIST                            ETH_MACLCSR_TLPIST_Msk   /* Transmit LPI State */

+#define ETH_MACLCSR_RLPIEX_Pos                        (3U)

+#define ETH_MACLCSR_RLPIEX_Msk                        (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */

+#define ETH_MACLCSR_RLPIEX                            ETH_MACLCSR_RLPIEX_Msk   /* Receive LPI Exit */

+#define ETH_MACLCSR_RLPIEN_Pos                        (2U)

+#define ETH_MACLCSR_RLPIEN_Msk                        (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */

+#define ETH_MACLCSR_RLPIEN                            ETH_MACLCSR_RLPIEN_Msk   /* Receive LPI Entry */

+#define ETH_MACLCSR_TLPIEX_Pos                        (1U)

+#define ETH_MACLCSR_TLPIEX_Msk                        (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */

+#define ETH_MACLCSR_TLPIEX                            ETH_MACLCSR_TLPIEX_Msk   /* Transmit LPI Exit */

+#define ETH_MACLCSR_TLPIEN_Pos                        (0U)

+#define ETH_MACLCSR_TLPIEN_Msk                        (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */

+#define ETH_MACLCSR_TLPIEN                            ETH_MACLCSR_TLPIEN_Msk   /* Transmit LPI Entry */

+

+/* Bit definition for Ethernet MAC LPI Timers Control Register */

+#define ETH_MACLTCR_LST_Pos                           (16U)

+#define ETH_MACLTCR_LST_Msk                           (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */

+#define ETH_MACLTCR_LST                               ETH_MACLTCR_LST_Msk      /* LPI LS TIMER */

+#define ETH_MACLTCR_TWT_Pos                           (0U)

+#define ETH_MACLTCR_TWT_Msk                           (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */

+#define ETH_MACLTCR_TWT                               ETH_MACLTCR_TWT_Msk      /* LPI TW TIMER */

+

+/* Bit definition for Ethernet MAC LPI Entry Timer Register */

+#define ETH_MACLETR_LPIET_Pos                         (0U)

+#define ETH_MACLETR_LPIET_Msk                         (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */

+#define ETH_MACLETR_LPIET                             ETH_MACLETR_LPIET_Msk    /* LPI Entry Timer */

+

+/* Bit definition for Ethernet MAC 1US Tic Counter Register */

+#define ETH_MAC1USTCR_TIC1USCNTR_Pos                  (0U)

+#define ETH_MAC1USTCR_TIC1USCNTR_Msk                  (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */

+#define ETH_MAC1USTCR_TIC1USCNTR                      ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */

+

+/* Bit definition for Ethernet MAC Version Register */

+#define ETH_MACVR_USERVER_Pos                         (8U)

+#define ETH_MACVR_USERVER_Msk                         (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */

+#define ETH_MACVR_USERVER                             ETH_MACVR_USERVER_Msk    /* User-defined Version */

+#define ETH_MACVR_SNPSVER_Pos                         (0U)

+#define ETH_MACVR_SNPSVER_Msk                         (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */

+#define ETH_MACVR_SNPSVER                             ETH_MACVR_SNPSVER_Msk    /* Synopsys-defined Version */

+

+/* Bit definition for Ethernet MAC Debug Register */

+#define ETH_MACDR_TFCSTS_Pos                          (17U)

+#define ETH_MACDR_TFCSTS_Msk                          (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */

+#define ETH_MACDR_TFCSTS                              ETH_MACDR_TFCSTS_Msk     /* MAC Transmit Packet Controller Status */

+#define ETH_MACDR_TFCSTS_IDLE                         ((uint32_t)0x00000000)   /* Idle state */

+#define ETH_MACDR_TFCSTS_WAIT_Pos                     (17U)

+#define ETH_MACDR_TFCSTS_WAIT_Msk                     (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */

+#define ETH_MACDR_TFCSTS_WAIT                         ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */

+#define ETH_MACDR_TFCSTS_GENERATEPCP_Pos              (18U)

+#define ETH_MACDR_TFCSTS_GENERATEPCP_Msk              (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */

+#define ETH_MACDR_TFCSTS_GENERATEPCP                  ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */

+#define ETH_MACDR_TFCSTS_TRASFERIP_Pos                (17U)

+#define ETH_MACDR_TFCSTS_TRASFERIP_Msk                (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */

+#define ETH_MACDR_TFCSTS_TRASFERIP                    ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */

+#define ETH_MACDR_TPESTS_Pos                          (16U)

+#define ETH_MACDR_TPESTS_Msk                          (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */

+#define ETH_MACDR_TPESTS                              ETH_MACDR_TPESTS_Msk     /* MAC Receive Packet Controller FIFO Status */

+#define ETH_MACDR_RFCFCSTS_Pos                        (1U)

+#define ETH_MACDR_RFCFCSTS_Msk                        (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */

+#define ETH_MACDR_RFCFCSTS                            ETH_MACDR_RFCFCSTS_Msk   /* MAC MII Transmit Protocol Engine Status */

+#define ETH_MACDR_RPESTS_Pos                          (0U)

+#define ETH_MACDR_RPESTS_Msk                          (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */

+#define ETH_MACDR_RPESTS                              ETH_MACDR_RPESTS_Msk     /* MAC MII Receive Protocol Engine Status */

+

+/* Bit definition for Ethernet MAC HW Feature0 Register */

+#define ETH_MACHWF0R_ACTPHYSEL_Pos                    (28U)

+#define ETH_MACHWF0R_ACTPHYSEL_Msk                    (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */

+#define ETH_MACHWF0R_ACTPHYSEL                        ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */

+#define ETH_MACHWF0R_ACTPHYSEL_MII                    ((uint32_t)0x00000000)   /* MII */

+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos               (30U)

+#define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk               (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */

+#define ETH_MACHWF0R_ACTPHYSEL_RMII                   ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */

+#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos             (28U)

+#define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk             (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos) /*!< 0x70000000 */

+#define ETH_MACHWF0R_ACTPHYSEL_REVMII                 ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */

+#define ETH_MACHWF0R_SAVLANINS_Pos                    (27U)

+#define ETH_MACHWF0R_SAVLANINS_Msk                    (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */

+#define ETH_MACHWF0R_SAVLANINS                        ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */

+#define ETH_MACHWF0R_TSSTSSEL_Pos                     (25U)

+#define ETH_MACHWF0R_TSSTSSEL_Msk                     (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */

+#define ETH_MACHWF0R_TSSTSSEL                         ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */

+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos            (25U)

+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */

+#define ETH_MACHWF0R_TSSTSSEL_INTERNAL                ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */

+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos            (26U)

+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk            (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */

+#define ETH_MACHWF0R_TSSTSSEL_EXTERNAL                ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */

+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos                (25U)

+#define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk                (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */

+#define ETH_MACHWF0R_TSSTSSEL_BOTH                    ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */

+#define ETH_MACHWF0R_MACADR64SEL_Pos                  (24U)

+#define ETH_MACHWF0R_MACADR64SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */

+#define ETH_MACHWF0R_MACADR64SEL                      ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */

+#define ETH_MACHWF0R_MACADR32SEL_Pos                  (23U)

+#define ETH_MACHWF0R_MACADR32SEL_Msk                  (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */

+#define ETH_MACHWF0R_MACADR32SEL                      ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */

+#define ETH_MACHWF0R_ADDMACADRSEL_Pos                 (18U)

+#define ETH_MACHWF0R_ADDMACADRSEL_Msk                 (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */

+#define ETH_MACHWF0R_ADDMACADRSEL                     ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */

+#define ETH_MACHWF0R_RXCOESEL_Pos                     (16U)

+#define ETH_MACHWF0R_RXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */

+#define ETH_MACHWF0R_RXCOESEL                         ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */

+#define ETH_MACHWF0R_TXCOESEL_Pos                     (14U)

+#define ETH_MACHWF0R_TXCOESEL_Msk                     (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */

+#define ETH_MACHWF0R_TXCOESEL                         ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */

+#define ETH_MACHWF0R_EEESEL_Pos                       (13U)

+#define ETH_MACHWF0R_EEESEL_Msk                       (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */

+#define ETH_MACHWF0R_EEESEL                           ETH_MACHWF0R_EEESEL_Msk  /* Energy Efficient Ethernet Enabled */

+#define ETH_MACHWF0R_TSSEL_Pos                        (12U)

+#define ETH_MACHWF0R_TSSEL_Msk                        (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */

+#define ETH_MACHWF0R_TSSEL                            ETH_MACHWF0R_TSSEL_Msk   /* IEEE 1588-2008 Timestamp Enabled */

+#define ETH_MACHWF0R_ARPOFFSEL_Pos                    (9U)

+#define ETH_MACHWF0R_ARPOFFSEL_Msk                    (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */

+#define ETH_MACHWF0R_ARPOFFSEL                        ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */

+#define ETH_MACHWF0R_MMCSEL_Pos                       (8U)

+#define ETH_MACHWF0R_MMCSEL_Msk                       (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */

+#define ETH_MACHWF0R_MMCSEL                           ETH_MACHWF0R_MMCSEL_Msk  /* RMON Module Enable */

+#define ETH_MACHWF0R_MGKSEL_Pos                       (7U)

+#define ETH_MACHWF0R_MGKSEL_Msk                       (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */

+#define ETH_MACHWF0R_MGKSEL                           ETH_MACHWF0R_MGKSEL_Msk  /* PMT Magic Packet Enable */

+#define ETH_MACHWF0R_RWKSEL_Pos                       (6U)

+#define ETH_MACHWF0R_RWKSEL_Msk                       (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */

+#define ETH_MACHWF0R_RWKSEL                           ETH_MACHWF0R_RWKSEL_Msk  /* PMT Remote Wake-up Packet Enable */

+#define ETH_MACHWF0R_SMASEL_Pos                       (5U)

+#define ETH_MACHWF0R_SMASEL_Msk                       (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */

+#define ETH_MACHWF0R_SMASEL                           ETH_MACHWF0R_SMASEL_Msk  /* SMA (MDIO) Interface */

+#define ETH_MACHWF0R_VLHASH_Pos                       (4U)

+#define ETH_MACHWF0R_VLHASH_Msk                       (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */

+#define ETH_MACHWF0R_VLHASH                           ETH_MACHWF0R_VLHASH_Msk  /* VLAN Hash Filter Selected */

+#define ETH_MACHWF0R_PCSSEL_Pos                       (3U)

+#define ETH_MACHWF0R_PCSSEL_Msk                       (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */

+#define ETH_MACHWF0R_PCSSEL                           ETH_MACHWF0R_PCSSEL_Msk  /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */

+#define ETH_MACHWF0R_HDSEL_Pos                        (2U)

+#define ETH_MACHWF0R_HDSEL_Msk                        (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */

+#define ETH_MACHWF0R_HDSEL                            ETH_MACHWF0R_HDSEL_Msk   /* Half-duplex Support */

+#define ETH_MACHWF0R_GMIISEL_Pos                      (1U)

+#define ETH_MACHWF0R_GMIISEL_Msk                      (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */

+#define ETH_MACHWF0R_GMIISEL                          ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */

+#define ETH_MACHWF0R_MIISEL_Pos                       (0U)

+#define ETH_MACHWF0R_MIISEL_Msk                       (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */

+#define ETH_MACHWF0R_MIISEL                           ETH_MACHWF0R_MIISEL_Msk  /* 10 or 100 Mbps Support */

+

+/* Bit definition for Ethernet MAC HW Feature1 Register */

+#define ETH_MACHWF1R_L3L4FNUM_Pos                     (27U)

+#define ETH_MACHWF1R_L3L4FNUM_Msk                     (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */

+#define ETH_MACHWF1R_L3L4FNUM                         ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */

+#define ETH_MACHWF1R_HASHTBLSZ_Pos                    (24U)

+#define ETH_MACHWF1R_HASHTBLSZ_Msk                    (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */

+#define ETH_MACHWF1R_HASHTBLSZ                        ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */

+#define ETH_MACHWF1R_AVSEL_Pos                        (20U)

+#define ETH_MACHWF1R_AVSEL_Msk                        (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */

+#define ETH_MACHWF1R_AVSEL                            ETH_MACHWF1R_AVSEL_Msk   /* AV Feature Enabled */

+#define ETH_MACHWF1R_DBGMEMA_Pos                      (19U)

+#define ETH_MACHWF1R_DBGMEMA_Msk                      (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */

+#define ETH_MACHWF1R_DBGMEMA                          ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */

+#define ETH_MACHWF1R_TSOEN_Pos                        (18U)

+#define ETH_MACHWF1R_TSOEN_Msk                        (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */

+#define ETH_MACHWF1R_TSOEN                            ETH_MACHWF1R_TSOEN_Msk   /* TCP Segmentation Offload Enable */

+#define ETH_MACHWF1R_SPHEN_Pos                        (17U)

+#define ETH_MACHWF1R_SPHEN_Msk                        (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */

+#define ETH_MACHWF1R_SPHEN                            ETH_MACHWF1R_SPHEN_Msk   /* Split Header Feature Enable */

+#define ETH_MACHWF1R_DCBEN_Pos                        (16U)

+#define ETH_MACHWF1R_DCBEN_Msk                        (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */

+#define ETH_MACHWF1R_DCBEN                            ETH_MACHWF1R_DCBEN_Msk   /* DCB Feature Enable */

+#define ETH_MACHWF1R_ADDR64_Pos                       (14U)

+#define ETH_MACHWF1R_ADDR64_Msk                       (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */

+#define ETH_MACHWF1R_ADDR64                           ETH_MACHWF1R_ADDR64_Msk  /* Address Width */

+#define ETH_MACHWF1R_ADDR64_32                        (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */

+#define ETH_MACHWF1R_ADDR64_40                        (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */

+#define ETH_MACHWF1R_ADDR64_48                        (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */

+#define ETH_MACHWF1R_ADVTHWORD_Pos                    (13U)

+#define ETH_MACHWF1R_ADVTHWORD_Msk                    (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */

+#define ETH_MACHWF1R_ADVTHWORD                        ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */

+#define ETH_MACHWF1R_PTOEN_Pos                        (12U)

+#define ETH_MACHWF1R_PTOEN_Msk                        (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */

+#define ETH_MACHWF1R_PTOEN                            ETH_MACHWF1R_PTOEN_Msk   /* PTP Offload Enable */

+#define ETH_MACHWF1R_OSTEN_Pos                        (11U)

+#define ETH_MACHWF1R_OSTEN_Msk                        (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */

+#define ETH_MACHWF1R_OSTEN                            ETH_MACHWF1R_OSTEN_Msk   /* One-Step Timestamping Enable */

+#define ETH_MACHWF1R_TXFIFOSIZE_Pos                   (6U)

+#define ETH_MACHWF1R_TXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */

+#define ETH_MACHWF1R_TXFIFOSIZE                       ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */

+#define ETH_MACHWF1R_RXFIFOSIZE_Pos                   (0U)

+#define ETH_MACHWF1R_RXFIFOSIZE_Msk                   (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */

+#define ETH_MACHWF1R_RXFIFOSIZE                       ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */

+

+/* Bit definition for Ethernet MAC HW Feature2 Register */

+#define ETH_MACHWF2R_AUXSNAPNUM_Pos                   (28U)

+#define ETH_MACHWF2R_AUXSNAPNUM_Msk                   (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */

+#define ETH_MACHWF2R_AUXSNAPNUM                       ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */

+#define ETH_MACHWF2R_PPSOUTNUM_Pos                    (24U)

+#define ETH_MACHWF2R_PPSOUTNUM_Msk                    (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */

+#define ETH_MACHWF2R_PPSOUTNUM                        ETH_MACHWF2R_PPSOUTNUM_Msk /*  Number of PPS Outputs */

+#define ETH_MACHWF2R_TXCHCNT_Pos                      (18U)

+#define ETH_MACHWF2R_TXCHCNT_Msk                      (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */

+#define ETH_MACHWF2R_TXCHCNT                          ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */

+#define ETH_MACHWF2R_RXCHCNT_Pos                      (13U)

+#define ETH_MACHWF2R_RXCHCNT_Msk                      (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000E000 */

+#define ETH_MACHWF2R_RXCHCNT                          ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */

+#define ETH_MACHWF2R_TXQCNT_Pos                       (6U)

+#define ETH_MACHWF2R_TXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */

+#define ETH_MACHWF2R_TXQCNT                           ETH_MACHWF2R_TXQCNT_Msk  /* Number of MTL Transmit Queues */

+#define ETH_MACHWF2R_RXQCNT_Pos                       (0U)

+#define ETH_MACHWF2R_RXQCNT_Msk                       (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */

+#define ETH_MACHWF2R_RXQCNT                           ETH_MACHWF2R_RXQCNT_Msk  /* Number of MTL Receive Queues */

+

+/* Bit definition for Ethernet MAC MDIO Address Register */

+#define ETH_MACMDIOAR_PSE_Pos                         (27U)

+#define ETH_MACMDIOAR_PSE_Msk                         (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */

+#define ETH_MACMDIOAR_PSE                             ETH_MACMDIOAR_PSE_Msk    /* Preamble Suppression Enable */

+#define ETH_MACMDIOAR_BTB_Pos                         (26U)

+#define ETH_MACMDIOAR_BTB_Msk                         (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */

+#define ETH_MACMDIOAR_BTB                             ETH_MACMDIOAR_BTB_Msk    /* Back to Back transactions */

+#define ETH_MACMDIOAR_PA_Pos                          (21U)

+#define ETH_MACMDIOAR_PA_Msk                          (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */

+#define ETH_MACMDIOAR_PA                              ETH_MACMDIOAR_PA_Msk     /* Physical Layer Address */

+#define ETH_MACMDIOAR_RDA_Pos                         (16U)

+#define ETH_MACMDIOAR_RDA_Msk                         (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */

+#define ETH_MACMDIOAR_RDA                             ETH_MACMDIOAR_RDA_Msk    /* Register/Device Address */

+#define ETH_MACMDIOAR_NTC_Pos                         (12U)

+#define ETH_MACMDIOAR_NTC_Msk                         (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */

+#define ETH_MACMDIOAR_NTC                             ETH_MACMDIOAR_NTC_Msk    /* Number of Trailing Clocks */

+#define ETH_MACMDIOAR_CR_Pos                          (8U)

+#define ETH_MACMDIOAR_CR_Msk                          (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */

+#define ETH_MACMDIOAR_CR                              ETH_MACMDIOAR_CR_Msk     /* CSR Clock Range */

+#define ETH_MACMDIOAR_CR_DIV42                        ((uint32_t)0x00000000)   /* CSR clock/42 */

+#define ETH_MACMDIOAR_CR_DIV62_Pos                    (8U)

+#define ETH_MACMDIOAR_CR_DIV62_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */

+#define ETH_MACMDIOAR_CR_DIV62                        ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */

+#define ETH_MACMDIOAR_CR_DIV16_Pos                    (9U)

+#define ETH_MACMDIOAR_CR_DIV16_Msk                    (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */

+#define ETH_MACMDIOAR_CR_DIV16                        ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */

+#define ETH_MACMDIOAR_CR_DIV26_Pos                    (8U)

+#define ETH_MACMDIOAR_CR_DIV26_Msk                    (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */

+#define ETH_MACMDIOAR_CR_DIV26                        ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */

+#define ETH_MACMDIOAR_CR_DIV102_Pos                   (10U)

+#define ETH_MACMDIOAR_CR_DIV102_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */

+#define ETH_MACMDIOAR_CR_DIV102                       ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */

+#define ETH_MACMDIOAR_CR_DIV124_Pos                   (8U)

+#define ETH_MACMDIOAR_CR_DIV124_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */

+#define ETH_MACMDIOAR_CR_DIV124                       ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */

+#define ETH_MACMDIOAR_CR_DIV4AR_Pos                   (11U)

+#define ETH_MACMDIOAR_CR_DIV4AR_Msk                   (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */

+#define ETH_MACMDIOAR_CR_DIV4AR                       ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV6AR_Pos                   (8U)

+#define ETH_MACMDIOAR_CR_DIV6AR_Msk                   (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */

+#define ETH_MACMDIOAR_CR_DIV6AR                       ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV8AR_Pos                   (9U)

+#define ETH_MACMDIOAR_CR_DIV8AR_Msk                   (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */

+#define ETH_MACMDIOAR_CR_DIV8AR                       ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV10AR_Pos                  (8U)

+#define ETH_MACMDIOAR_CR_DIV10AR_Msk                  (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */

+#define ETH_MACMDIOAR_CR_DIV10AR                      ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV12AR_Pos                  (10U)

+#define ETH_MACMDIOAR_CR_DIV12AR_Msk                  (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */

+#define ETH_MACMDIOAR_CR_DIV12AR                      ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV14AR_Pos                  (8U)

+#define ETH_MACMDIOAR_CR_DIV14AR_Msk                  (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */

+#define ETH_MACMDIOAR_CR_DIV14AR                      ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV16AR_Pos                  (9U)

+#define ETH_MACMDIOAR_CR_DIV16AR_Msk                  (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */

+#define ETH_MACMDIOAR_CR_DIV16AR                      ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_CR_DIV18AR_Pos                  (8U)

+#define ETH_MACMDIOAR_CR_DIV18AR_Msk                  (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */

+#define ETH_MACMDIOAR_CR_DIV18AR                      ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */

+#define ETH_MACMDIOAR_SKAP_Pos                        (4U)

+#define ETH_MACMDIOAR_SKAP_Msk                        (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */

+#define ETH_MACMDIOAR_SKAP                            ETH_MACMDIOAR_SKAP_Msk   /* Skip Address Packet */

+#define ETH_MACMDIOAR_MOC_Pos                         (2U)

+#define ETH_MACMDIOAR_MOC_Msk                         (0x3UL << ETH_MACMDIOAR_MOC_Pos) /*!< 0x0000000C */

+#define ETH_MACMDIOAR_MOC                             ETH_MACMDIOAR_MOC_Msk    /* MII Operation Command */

+#define ETH_MACMDIOAR_MOC_WR_Pos                      (2U)

+#define ETH_MACMDIOAR_MOC_WR_Msk                      (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos) /*!< 0x00000004 */

+#define ETH_MACMDIOAR_MOC_WR                          ETH_MACMDIOAR_MOC_WR_Msk /* Write */

+#define ETH_MACMDIOAR_MOC_PRDIA_Pos                   (3U)

+#define ETH_MACMDIOAR_MOC_PRDIA_Msk                   (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos) /*!< 0x00000008 */

+#define ETH_MACMDIOAR_MOC_PRDIA                       ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */

+#define ETH_MACMDIOAR_MOC_RD_Pos                      (2U)

+#define ETH_MACMDIOAR_MOC_RD_Msk                      (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos) /*!< 0x0000000C */

+#define ETH_MACMDIOAR_MOC_RD                          ETH_MACMDIOAR_MOC_RD_Msk /* Read */

+#define ETH_MACMDIOAR_C45E_Pos                        (1U)

+#define ETH_MACMDIOAR_C45E_Msk                        (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */

+#define ETH_MACMDIOAR_C45E                            ETH_MACMDIOAR_C45E_Msk   /* Clause 45 PHY Enable */

+#define ETH_MACMDIOAR_MB_Pos                          (0U)

+#define ETH_MACMDIOAR_MB_Msk                          (0x1UL << ETH_MACMDIOAR_MB_Pos) /*!< 0x00000001 */

+#define ETH_MACMDIOAR_MB                              ETH_MACMDIOAR_MB_Msk     /* MII Busy */

+

+/* Bit definition for Ethernet MAC MDIO Data Register */

+#define ETH_MACMDIODR_RA_Pos                          (16U)

+#define ETH_MACMDIODR_RA_Msk                          (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */

+#define ETH_MACMDIODR_RA                              ETH_MACMDIODR_RA_Msk     /* Register Address */

+#define ETH_MACMDIODR_MD_Pos                          (0U)

+#define ETH_MACMDIODR_MD_Msk                          (0xFFFFUL << ETH_MACMDIODR_MD_Pos) /*!< 0x0000FFFF */

+#define ETH_MACMDIODR_MD                              ETH_MACMDIODR_MD_Msk     /* MII Data */

+

+/* Bit definition for Ethernet ARP Address Register */

+#define ETH_MACARPAR_ARPPA_Pos                         (0U)

+#define ETH_MACARPAR_ARPPA_Msk                         (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACARPAR_ARPPA                             ETH_MACARPAR_ARPPA_Msk     /* ARP Protocol Address */

+

+/* Bit definition for Ethernet MAC Address 0 High Register */

+#define ETH_MACA0HR_AE_Pos                            (31U)

+#define ETH_MACA0HR_AE_Msk                            (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA0HR_AE                                ETH_MACA0HR_AE_Msk /* Address Enable*/

+#define ETH_MACA0HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA0HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA0HR_ADDRHI                            ETH_MACA0HR_ADDRHI_Msk   /* MAC Address 0*/

+

+/* Bit definition for Ethernet MAC Address 0 Low Register */

+#define ETH_MACA0LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA0LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA0LR_ADDRLO                            ETH_MACA0LR_ADDRLO_Msk   /* MAC Address 0*/

+

+/* Bit definition for Ethernet MAC Address 1 High Register */

+#define ETH_MACA1HR_AE_Pos                            (31U)

+#define ETH_MACA1HR_AE_Msk                            (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA1HR_AE                                ETH_MACA1HR_AE_Msk /* Address Enable*/

+#define ETH_MACA1HR_SA_Pos                            (30U)

+#define ETH_MACA1HR_SA_Msk                            (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACA1HR_SA                                ETH_MACA1HR_SA_Msk /* Source Address */

+#define ETH_MACA1HR_MBC_Pos                           (24U)

+#define ETH_MACA1HR_MBC_Msk                           (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACA1HR_MBC                               ETH_MACA1HR_MBC_Msk /* Mask Byte Control */

+#define ETH_MACA1HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA1HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA1HR_ADDRHI                            ETH_MACA1HR_ADDRHI_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 1 Low Register */

+#define ETH_MACA1LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA1LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA1LR_ADDRLO                            ETH_MACA1LR_ADDRLO_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 2 High Register */

+#define ETH_MACA2HR_AE_Pos                            (31U)

+#define ETH_MACA2HR_AE_Msk                            (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA2HR_AE                                ETH_MACA2HR_AE_Msk /* Address Enable*/

+#define ETH_MACA2HR_SA_Pos                            (30U)

+#define ETH_MACA2HR_SA_Msk                            (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACA2HR_SA                                ETH_MACA2HR_SA_Msk /* Source Address */

+#define ETH_MACA2HR_MBC_Pos                           (24U)

+#define ETH_MACA2HR_MBC_Msk                           (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACA2HR_MBC                               ETH_MACA2HR_MBC_Msk /* Mask Byte Control */

+#define ETH_MACA2HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA2HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA2HR_ADDRHI                            ETH_MACA2HR_ADDRHI_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 2 Low Register */

+#define ETH_MACA2LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA2LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA2LR_ADDRLO                            ETH_MACA2LR_ADDRLO_Msk   /* MAC Address 2*/

+

+/* Bit definition for Ethernet MAC Address 3 High Register */

+#define ETH_MACA3HR_AE_Pos                            (31U)

+#define ETH_MACA3HR_AE_Msk                            (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACA3HR_AE                                ETH_MACA3HR_AE_Msk /* Address Enable*/

+#define ETH_MACA3HR_SA_Pos                            (30U)

+#define ETH_MACA3HR_SA_Msk                            (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACA3HR_SA                                ETH_MACA3HR_SA_Msk /* Source Address */

+#define ETH_MACA3HR_MBC_Pos                           (24U)

+#define ETH_MACA3HR_MBC_Msk                           (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACA3HR_MBC                               ETH_MACA3HR_MBC_Msk /* Mask Byte Control */

+#define ETH_MACA3HR_ADDRHI_Pos                        (0U)

+#define ETH_MACA3HR_ADDRHI_Msk                        (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x0000FFFF */

+#define ETH_MACA3HR_ADDRHI                            ETH_MACA3HR_ADDRHI_Msk   /* MAC Address 1*/

+

+/* Bit definition for Ethernet MAC Address 3 Low Register */

+#define ETH_MACA3LR_ADDRLO_Pos                        (0U)

+#define ETH_MACA3LR_ADDRLO_Msk                        (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACA3LR_ADDRLO                            ETH_MACA3LR_ADDRLO_Msk   /* MAC Address 3*/

+

+/* Bit definition for Ethernet MAC Address High Register */

+#define ETH_MACAHR_AE_Pos                             (31U)

+#define ETH_MACAHR_AE_Msk                             (0x1UL << ETH_MACAHR_AE_Pos) /*!< 0x80000000 */

+#define ETH_MACAHR_AE                                 ETH_MACAHR_AE_Msk        /* Address enable */

+#define ETH_MACAHR_SA_Pos                             (30U)

+#define ETH_MACAHR_SA_Msk                             (0x1UL << ETH_MACAHR_SA_Pos) /*!< 0x40000000 */

+#define ETH_MACAHR_SA                                 ETH_MACAHR_SA_Msk        /* Source address */

+#define ETH_MACAHR_MBC_Pos                            (24U)

+#define ETH_MACAHR_MBC_Msk                            (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */

+#define ETH_MACAHR_MBC                                ETH_MACAHR_MBC_Msk       /* Mask byte control: bits to mask for comparison of the MAC Address bytes */

+#define ETH_MACAHR_MBC_HBITS15_8                      ((uint32_t)0x20000000)   /* Mask MAC Address high reg bits [15:8] */

+#define ETH_MACAHR_MBC_HBITS7_0                       ((uint32_t)0x10000000)   /* Mask MAC Address high reg bits [7:0] */

+#define ETH_MACAHR_MBC_LBITS31_24                     ((uint32_t)0x08000000)   /* Mask MAC Address low reg bits [31:24] */

+#define ETH_MACAHR_MBC_LBITS23_16                     ((uint32_t)0x04000000)   /* Mask MAC Address low reg bits [23:16] */

+#define ETH_MACAHR_MBC_LBITS15_8                      ((uint32_t)0x02000000)   /* Mask MAC Address low reg bits [15:8] */

+#define ETH_MACAHR_MBC_LBITS7_0                       ((uint32_t)0x01000000)   /* Mask MAC Address low reg bits [7:0] */

+#define ETH_MACAHR_MACAH_Pos                          (0U)

+#define ETH_MACAHR_MACAH_Msk                          (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */

+#define ETH_MACAHR_MACAH                              ETH_MACAHR_MACAH_Msk     /* MAC address high */

+

+/* Bit definition for Ethernet MAC Address Low Register */

+#define ETH_MACALR_MACAL_Pos                          (0U)

+#define ETH_MACALR_MACAL_Msk                          (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACALR_MACAL                              ETH_MACALR_MACAL_Msk     /* MAC address low */

+

+/* Bit definition for Ethernet MMC Control Register */

+#define ETH_MMCCR_UCDBC_Pos                           (8U)

+#define ETH_MMCCR_UCDBC_Msk                           (0x1UL << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */

+#define ETH_MMCCR_UCDBC                               ETH_MMCCR_UCDBC_Msk  /* Update MMC Counters for Dropped Broadcast Packets */

+#define ETH_MMCCR_CNTPRSTLVL_Pos                      (5U)

+#define ETH_MMCCR_CNTPRSTLVL_Msk                      (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */

+#define ETH_MMCCR_CNTPRSTLVL                          ETH_MMCCR_CNTPRSTLVL_Msk  /* Full-Half Preset */

+#define ETH_MMCCR_CNTPRST_Pos                         (4U)

+#define ETH_MMCCR_CNTPRST_Msk                         (0x1UL << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */

+#define ETH_MMCCR_CNTPRST                             ETH_MMCCR_CNTPRST_Msk  /* Counters Reset */

+#define ETH_MMCCR_CNTFREEZ_Pos                        (3U)

+#define ETH_MMCCR_CNTFREEZ_Msk                        (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */

+#define ETH_MMCCR_CNTFREEZ                            ETH_MMCCR_CNTFREEZ_Msk  /* MMC Counter Freeze */

+#define ETH_MMCCR_RSTONRD_Pos                         (2U)

+#define ETH_MMCCR_RSTONRD_Msk                         (0x1UL << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */

+#define ETH_MMCCR_RSTONRD                             ETH_MMCCR_RSTONRD_Msk  /* Reset On Read */

+#define ETH_MMCCR_CNTSTOPRO_Pos                       (1U)

+#define ETH_MMCCR_CNTSTOPRO_Msk                       (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */

+#define ETH_MMCCR_CNTSTOPRO                           ETH_MMCCR_CNTSTOPRO_Msk  /* Counter Stop Rollover */

+#define ETH_MMCCR_CNTRST_Pos                          (0U)

+#define ETH_MMCCR_CNTRST_Msk                          (0x1UL << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */

+#define ETH_MMCCR_CNTRST                              ETH_MMCCR_CNTRST_Msk  /* Counters Reset */

+

+/* Bit definition for Ethernet MMC Rx Interrupt Register */

+#define ETH_MMCRIR_RXLPITRCIS_Pos                     (27U)

+#define ETH_MMCRIR_RXLPITRCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) /*!< 0x08000000 */

+#define ETH_MMCRIR_RXLPITRCIS                         ETH_MMCRIR_RXLPITRCIS_Msk  /* MMC Receive LPI transition counter interrupt status */

+#define ETH_MMCRIR_RXLPIUSCIS_Pos                     (26U)

+#define ETH_MMCRIR_RXLPIUSCIS_Msk                     (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */

+#define ETH_MMCRIR_RXLPIUSCIS                         ETH_MMCRIR_RXLPIUSCIS_Msk  /* MMC Receive LPI microsecond counter interrupt status */

+#define ETH_MMCRIR_RXUCGPIS_Pos                       (17U)

+#define ETH_MMCRIR_RXUCGPIS_Msk                       (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) /*!< 0x00020000 */

+#define ETH_MMCRIR_RXUCGPIS                           ETH_MMCRIR_RXUCGPIS_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Status */

+#define ETH_MMCRIR_RXALGNERPIS_Pos                    (6U)

+#define ETH_MMCRIR_RXALGNERPIS_Msk                    (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) /*!< 0x00000040 */

+#define ETH_MMCRIR_RXALGNERPIS                        ETH_MMCRIR_RXALGNERPIS_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Status */

+#define ETH_MMCRIR_RXCRCERPIS_Pos                     (5U)

+#define ETH_MMCRIR_RXCRCERPIS_Msk                     (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) /*!< 0x00000020 */

+#define ETH_MMCRIR_RXCRCERPIS                         ETH_MMCRIR_RXCRCERPIS_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Status */

+

+/* Bit definition for Ethernet MMC Tx Interrupt Register */

+#define ETH_MMCTIR_TXLPITRCIS_Pos                     (27U)

+#define ETH_MMCTIR_TXLPITRCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) /*!< 0x08000000 */

+#define ETH_MMCTIR_TXLPITRCIS                         ETH_MMCTIR_TXLPITRCIS_Msk  /* MMC Transmit LPI transition counter interrupt status */

+#define ETH_MMCTIR_TXLPIUSCIS_Pos                     (26U)

+#define ETH_MMCTIR_TXLPIUSCIS_Msk                     (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */

+#define ETH_MMCTIR_TXLPIUSCIS                         ETH_MMCTIR_TXLPIUSCIS_Msk  /* MMC Transmit LPI microsecond counter interrupt status */

+#define ETH_MMCTIR_TXGPKTIS_Pos                       (21U)

+#define ETH_MMCTIR_TXGPKTIS_Msk                       (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) /*!< 0x00200000 */

+#define ETH_MMCTIR_TXGPKTIS                           ETH_MMCTIR_TXGPKTIS_Msk  /* MMC Transmit Good Packet Counter Interrupt Status */

+#define ETH_MMCTIR_TXMCOLGPIS_Pos                     (15U)

+#define ETH_MMCTIR_TXMCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */

+#define ETH_MMCTIR_TXMCOLGPIS                         ETH_MMCTIR_TXMCOLGPIS_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */

+#define ETH_MMCTIR_TXSCOLGPIS_Pos                     (14U)

+#define ETH_MMCTIR_TXSCOLGPIS_Msk                     (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */

+#define ETH_MMCTIR_TXSCOLGPIS                         ETH_MMCTIR_TXSCOLGPIS_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */

+

+/* Bit definition for Ethernet MMC Rx interrupt Mask register */

+#define ETH_MMCRIMR_RXLPITRCIM_Pos                    (27U)

+#define ETH_MMCRIMR_RXLPITRCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */

+#define ETH_MMCRIMR_RXLPITRCIM                        ETH_MMCRIMR_RXLPITRCIM_Msk  /* MMC Receive LPI transition counter interrupt Mask */

+#define ETH_MMCRIMR_RXLPIUSCIM_Pos                    (26U)

+#define ETH_MMCRIMR_RXLPIUSCIM_Msk                    (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */

+#define ETH_MMCRIMR_RXLPIUSCIM                        ETH_MMCRIMR_RXLPIUSCIM_Msk  /* MMC Receive LPI microsecond counter interrupt Mask */

+#define ETH_MMCRIMR_RXUCGPIM_Pos                      (17U)

+#define ETH_MMCRIMR_RXUCGPIM_Msk                      (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) /*!< 0x00020000 */

+#define ETH_MMCRIMR_RXUCGPIM                          ETH_MMCRIMR_RXUCGPIM_Msk  /* MMC Receive Unicast Good Packet Counter Interrupt Mask */

+#define ETH_MMCRIMR_RXALGNERPIM_Pos                   (6U)

+#define ETH_MMCRIMR_RXALGNERPIM_Msk                   (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */

+#define ETH_MMCRIMR_RXALGNERPIM                       ETH_MMCRIMR_RXALGNERPIM_Msk  /* MMC Receive Alignment Error Packet Counter Interrupt Mask */

+#define ETH_MMCRIMR_RXCRCERPIM_Pos                    (5U)

+#define ETH_MMCRIMR_RXCRCERPIM_Msk                    (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */

+#define ETH_MMCRIMR_RXCRCERPIM                        ETH_MMCRIMR_RXCRCERPIM_Msk  /* MMC Receive CRC Error Packet Counter Interrupt Mask */

+

+/* Bit definition for Ethernet MMC Tx Interrupt Mask Register */

+#define ETH_MMCTIMR_TXLPITRCIM_Pos                    (27U)

+#define ETH_MMCTIMR_TXLPITRCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */

+#define ETH_MMCTIMR_TXLPITRCIM                        ETH_MMCTIMR_TXLPITRCIM_Msk  /* MMC Transmit LPI transition counter interrupt Mask*/

+#define ETH_MMCTIMR_TXLPIUSCIM_Pos                    (26U)

+#define ETH_MMCTIMR_TXLPIUSCIM_Msk                    (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */

+#define ETH_MMCTIMR_TXLPIUSCIM                        ETH_MMCTIMR_TXLPIUSCIM_Msk  /* MMC Transmit LPI microsecond counter interrupt Mask*/

+#define ETH_MMCTIMR_TXGPKTIM_Pos                      (21U)

+#define ETH_MMCTIMR_TXGPKTIM_Msk                      (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) /*!< 0x00200000 */

+#define ETH_MMCTIMR_TXGPKTIM                          ETH_MMCTIMR_TXGPKTIM_Msk  /* MMC Transmit Good Packet Counter Interrupt Mask*/

+#define ETH_MMCTIMR_TXMCOLGPIM_Pos                    (15U)

+#define ETH_MMCTIMR_TXMCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */

+#define ETH_MMCTIMR_TXMCOLGPIM                        ETH_MMCTIMR_TXMCOLGPIM_Msk  /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */

+#define ETH_MMCTIMR_TXSCOLGPIM_Pos                    (14U)

+#define ETH_MMCTIMR_TXSCOLGPIM_Msk                    (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */

+#define ETH_MMCTIMR_TXSCOLGPIM                        ETH_MMCTIMR_TXSCOLGPIM_Msk  /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */

+

+/* Bit definition for Ethernet MMC Tx Single Collision Good Packets Register */

+#define ETH_MMCTSCGPR_TXSNGLCOLG_Pos                  (0U)

+#define ETH_MMCTSCGPR_TXSNGLCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTSCGPR_TXSNGLCOLG                      ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */

+

+/* Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register */

+#define ETH_MMCTMCGPR_TXMULTCOLG_Pos                  (0U)

+#define ETH_MMCTMCGPR_TXMULTCOLG_msk                  (0xFFFFFFFFUL <<  ETH_MMCTMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTMCGPR_TXMULTCOLG                      ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */

+

+/* Bit definition for Ethernet MMC Tx Packet Count Good Register */

+#define ETH_MMCTPCGR_TXPKTG_Pos                       (0U)

+#define ETH_MMCTPCGR_TXPKTG_msk                       (0xFFFFFFFFUL <<  ETH_MMCTPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTPCGR_TXPKTG                           ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */

+

+/* Bit definition for Ethernet MMC Rx CRC Error Packets Register */

+#define ETH_MMCRCRCEPR_RXCRCERR_Pos                   (0U)

+#define ETH_MMCRCRCEPR_RXCRCERR_msk                   (0xFFFFFFFFUL <<  ETH_MMCRCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRCRCEPR_RXCRCERR                       ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */

+

+/* Bit definition for Ethernet MMC Rx alignment error packets register */

+#define ETH_MMCRAEPR_RXALGNERR_Pos                    (0U)

+#define ETH_MMCRAEPR_RXALGNERR_msk                    (0xFFFFFFFFUL <<  ETH_MMCRAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRAEPR_RXALGNERR                        ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */

+

+/* Bit definition for Ethernet MMC Rx Unicast Packets Good Register */

+#define ETH_MMCRUPGR_RXUCASTG_Pos                     (0U)

+#define ETH_MMCRUPGR_RXUCASTG_msk                     (0xFFFFFFFFUL <<  ETH_MMCRUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRUPGR_RXUCASTG                         ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */

+

+/* Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register */

+#define ETH_MMCTLPIMSTR_TXLPIUSC_Pos                  (0U)

+#define ETH_MMCTLPIMSTR_TXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCTLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTLPIMSTR_TXLPIUSC                      ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */

+

+/* Bit definition for Ethernet MMC Tx LPI Transition Counter Register */

+#define ETH_MMCTLPITCR_TXLPITRC_Pos                   (0U)

+#define ETH_MMCTLPITCR_TXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCTLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCTLPITCR_TXLPITRC                       ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */

+

+/* Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register */

+#define ETH_MMCRLPIMSTR_RXLPIUSC_Pos                  (0U)

+#define ETH_MMCRLPIMSTR_RXLPIUSC_msk                  (0xFFFFFFFFUL <<  ETH_MMCRLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRLPIMSTR_RXLPIUSC                      ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */

+

+/* Bit definition for Ethernet MMC Rx LPI Transition Counter Register */

+#define ETH_MMCRLPITCR_RXLPITRC_Pos                   (0U)

+#define ETH_MMCRLPITCR_RXLPITRC_msk                   (0xFFFFFFFFUL <<  ETH_MMCRLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MMCRLPITCR_RXLPITRC                       ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */

+

+/* Bit definition for Ethernet MAC L3 L4 Control Register */

+#define ETH_MACL3L4CR_L4DPIM_Pos                      (21U)

+#define ETH_MACL3L4CR_L4DPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos) /*!< 0x00200000 */

+#define ETH_MACL3L4CR_L4DPIM                          ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */

+#define ETH_MACL3L4CR_L4DPM_Pos                       (20U)

+#define ETH_MACL3L4CR_L4DPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4DPM_Pos) /*!< 0x00100000 */

+#define ETH_MACL3L4CR_L4DPM                           ETH_MACL3L4CR_L4DPM_Msk  /* Layer 4 Destination Port Match Enable */

+#define ETH_MACL3L4CR_L4SPIM_Pos                      (19U)

+#define ETH_MACL3L4CR_L4SPIM_Msk                      (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos) /*!< 0x00080000 */

+#define ETH_MACL3L4CR_L4SPIM                          ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */

+#define ETH_MACL3L4CR_L4SPM_Pos                       (18U)

+#define ETH_MACL3L4CR_L4SPM_Msk                       (0x1UL << ETH_MACL3L4CR_L4SPM_Pos) /*!< 0x00040000 */

+#define ETH_MACL3L4CR_L4SPM                           ETH_MACL3L4CR_L4SPM_Msk  /* Layer 4 Source Port Match Enable */

+#define ETH_MACL3L4CR_L4PEN_Pos                       (16U)

+#define ETH_MACL3L4CR_L4PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L4PEN_Pos) /*!< 0x00010000 */

+#define ETH_MACL3L4CR_L4PEN                           ETH_MACL3L4CR_L4PEN_Msk  /* Layer 4 Protocol Enable */

+#define ETH_MACL3L4CR_L3HDBM_Pos                      (11U)

+#define ETH_MACL3L4CR_L3HDBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos) /*!< 0x0000F800 */

+#define ETH_MACL3L4CR_L3HDBM                          ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */

+#define ETH_MACL3L4CR_L3HSBM_Pos                      (6U)

+#define ETH_MACL3L4CR_L3HSBM_Msk                      (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos) /*!< 0x000007C0 */

+#define ETH_MACL3L4CR_L3HSBM                          ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */

+#define ETH_MACL3L4CR_L3DAIM_Pos                      (5U)

+#define ETH_MACL3L4CR_L3DAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos) /*!< 0x00000020 */

+#define ETH_MACL3L4CR_L3DAIM                          ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */

+#define ETH_MACL3L4CR_L3DAM_Pos                       (4U)

+#define ETH_MACL3L4CR_L3DAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3DAM_Pos) /*!< 0x00000010 */

+#define ETH_MACL3L4CR_L3DAM                           ETH_MACL3L4CR_L3DAM_Msk  /* Layer 3 IP DA Match Enable */

+#define ETH_MACL3L4CR_L3SAIM_Pos                      (3U)

+#define ETH_MACL3L4CR_L3SAIM_Msk                      (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos) /*!< 0x00000008 */

+#define ETH_MACL3L4CR_L3SAIM                          ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */

+#define ETH_MACL3L4CR_L3SAM_Pos                       (2U)

+#define ETH_MACL3L4CR_L3SAM_Msk                       (0x1UL << ETH_MACL3L4CR_L3SAM_Pos) /*!< 0x00000004 */

+#define ETH_MACL3L4CR_L3SAM                           ETH_MACL3L4CR_L3SAM_Msk  /* Layer 3 IP SA Match Enable*/

+#define ETH_MACL3L4CR_L3PEN_Pos                       (0U)

+#define ETH_MACL3L4CR_L3PEN_Msk                       (0x1UL << ETH_MACL3L4CR_L3PEN_Pos) /*!< 0x00000001 */

+#define ETH_MACL3L4CR_L3PEN                           ETH_MACL3L4CR_L3PEN_Msk  /* Layer 3 Protocol Enable */

+

+/* Bit definition for Ethernet MAC L4 Address Register */

+#define ETH_MACL4AR_L4DP_Pos                          (16U)

+#define ETH_MACL4AR_L4DP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4DP_Pos) /*!< 0xFFFF0000 */

+#define ETH_MACL4AR_L4DP                              ETH_MACL4AR_L4DP_Msk     /* Layer 4 Destination Port Number Field */

+#define ETH_MACL4AR_L4SP_Pos                          (0U)

+#define ETH_MACL4AR_L4SP_Msk                          (0xFFFFUL << ETH_MACL4AR_L4SP_Pos) /*!< 0x0000FFFF */

+#define ETH_MACL4AR_L4SP                              ETH_MACL4AR_L4SP_Msk     /* Layer 4 Source Port Number Field */

+

+/* Bit definition for Ethernet MAC L3 Address0 Register */

+#define ETH_MACL3A0R_L3A0_Pos                         (0U)

+#define ETH_MACL3A0R_L3A0_Msk                         (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A0R_L3A0                             ETH_MACL3A0R_L3A0_Msk    /* Layer 3 Address 0 Field */

+

+/* Bit definition for Ethernet MAC L4 Address1 Register */

+#define ETH_MACL3A1R_L3A1_Pos                         (0U)

+#define ETH_MACL3A1R_L3A1_Msk                         (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A1R_L3A1                             ETH_MACL3A1R_L3A1_Msk    /* Layer 3 Address 1 Field */

+

+/* Bit definition for Ethernet MAC L4 Address2 Register */

+#define ETH_MACL3A2R_L3A2_Pos                         (0U)

+#define ETH_MACL3A2R_L3A2_Msk                         (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A2R_L3A2                             ETH_MACL3A2R_L3A2_Msk    /* Layer 3 Address 2 Field */

+

+/* Bit definition for Ethernet MAC L4 Address3 Register */

+#define ETH_MACL3A3R_L3A3_Pos                         (0U)

+#define ETH_MACL3A3R_L3A3_Msk                         (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACL3A3R_L3A3                             ETH_MACL3A3R_L3A3_Msk    /* Layer 3 Address 3 Field */

+

+/* Bit definition for Ethernet MAC Timestamp Control Register */

+#define ETH_MACTSCR_TXTSSTSM_Pos                      (24U)

+#define ETH_MACTSCR_TXTSSTSM_Msk                      (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */

+#define ETH_MACTSCR_TXTSSTSM                          ETH_MACTSCR_TXTSSTSM_Msk  /* Transmit Timestamp Status Mode */

+#define ETH_MACTSCR_CSC_Pos                           (19U)

+#define ETH_MACTSCR_CSC_Msk                           (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */

+#define ETH_MACTSCR_CSC                               ETH_MACTSCR_CSC_Msk  /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */

+#define ETH_MACTSCR_TSENMACADDR_Pos                   (18U)

+#define ETH_MACTSCR_TSENMACADDR_Msk                   (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */

+#define ETH_MACTSCR_TSENMACADDR                       ETH_MACTSCR_TSENMACADDR_Msk  /* Enable MAC Address for PTP Packet Filtering */

+#define ETH_MACTSCR_SNAPTYPSEL_Pos                    (16U)

+#define ETH_MACTSCR_SNAPTYPSEL_Msk                    (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */

+#define ETH_MACTSCR_SNAPTYPSEL                        ETH_MACTSCR_SNAPTYPSEL_Msk  /* Select PTP packets for Taking Snapshots */

+#define ETH_MACTSCR_TSMSTRENA_Pos                     (15U)

+#define ETH_MACTSCR_TSMSTRENA_Msk                     (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */

+#define ETH_MACTSCR_TSMSTRENA                         ETH_MACTSCR_TSMSTRENA_Msk  /* Enable Snapshot for Messages Relevant to Master */

+#define ETH_MACTSCR_TSEVNTENA_Pos                     (14U)

+#define ETH_MACTSCR_TSEVNTENA_Msk                     (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */

+#define ETH_MACTSCR_TSEVNTENA                         ETH_MACTSCR_TSEVNTENA_Msk  /* Enable Timestamp Snapshot for Event Messages */

+#define ETH_MACTSCR_TSIPV4ENA_Pos                     (13U)

+#define ETH_MACTSCR_TSIPV4ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */

+#define ETH_MACTSCR_TSIPV4ENA                         ETH_MACTSCR_TSIPV4ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv4-UDP */

+#define ETH_MACTSCR_TSIPV6ENA_Pos                     (12U)

+#define ETH_MACTSCR_TSIPV6ENA_Msk                     (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */

+#define ETH_MACTSCR_TSIPV6ENA                         ETH_MACTSCR_TSIPV6ENA_Msk  /* Enable Processing of PTP Packets Sent over IPv6-UDP */

+#define ETH_MACTSCR_TSIPENA_Pos                       (11U)

+#define ETH_MACTSCR_TSIPENA_Msk                       (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */

+#define ETH_MACTSCR_TSIPENA                           ETH_MACTSCR_TSIPENA_Msk  /* Enable Processing of PTP over Ethernet Packets */

+#define ETH_MACTSCR_TSVER2ENA_Pos                     (10U)

+#define ETH_MACTSCR_TSVER2ENA_Msk                     (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */

+#define ETH_MACTSCR_TSVER2ENA                         ETH_MACTSCR_TSVER2ENA_Msk  /* Enable PTP Packet Processing for Version 2 Format */

+#define ETH_MACTSCR_TSCTRLSSR_Pos                     (9U)

+#define ETH_MACTSCR_TSCTRLSSR_Msk                     (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */

+#define ETH_MACTSCR_TSCTRLSSR                         ETH_MACTSCR_TSCTRLSSR_Msk  /* Timestamp Digital or Binary Rollover Control */

+#define ETH_MACTSCR_TSENALL_Pos                       (8U)

+#define ETH_MACTSCR_TSENALL_Msk                       (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */

+#define ETH_MACTSCR_TSENALL                           ETH_MACTSCR_TSENALL_Msk  /* Enable Timestamp for All Packets */

+#define ETH_MACTSCR_TSADDREG_Pos                      (5U)

+#define ETH_MACTSCR_TSADDREG_Msk                      (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */

+#define ETH_MACTSCR_TSADDREG                          ETH_MACTSCR_TSADDREG_Msk  /* Update Addend Register */

+#define ETH_MACTSCR_TSUPDT_Pos                        (3U)

+#define ETH_MACTSCR_TSUPDT_Msk                        (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */

+#define ETH_MACTSCR_TSUPDT                            ETH_MACTSCR_TSUPDT_Msk  /* Update Timestamp */

+#define ETH_MACTSCR_TSINIT_Pos                        (2U)

+#define ETH_MACTSCR_TSINIT_Msk                        (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */

+#define ETH_MACTSCR_TSINIT                             ETH_MACTSCR_TSINIT_Msk  /* Initialize Timestamp */

+#define ETH_MACTSCR_TSCFUPDT_Pos                      (1U)

+#define ETH_MACTSCR_TSCFUPDT_Msk                      (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */

+#define ETH_MACTSCR_TSCFUPDT                          ETH_MACTSCR_TSCFUPDT_Msk  /* Fine or Coarse Timestamp Update*/

+#define ETH_MACTSCR_TSENA_Pos                         (0U)

+#define ETH_MACTSCR_TSENA_Msk                         (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */

+#define ETH_MACTSCR_TSENA                             ETH_MACTSCR_TSENA_Msk  /* Enable Timestamp */

+

+/* Bit definition for Ethernet MAC Sub-second Increment Register */

+#define ETH_MACMACSSIR_SSINC_Pos                      (16U)

+#define ETH_MACMACSSIR_SSINC_Msk                      (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) /*!< 0x0000FF00 */

+#define ETH_MACMACSSIR_SSINC                          ETH_MACMACSSIR_SSINC_Msk  /* Sub-second Increment Value */

+#define ETH_MACMACSSIR_SNSINC_Pos                     (8U)

+#define ETH_MACMACSSIR_SNSINC_Msk                     (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos) /*!< 0x000000FF */

+#define ETH_MACMACSSIR_SNSINC                         ETH_MACMACSSIR_SNSINC_Msk  /* Sub-nanosecond Increment Value */

+

+/* Bit definition for Ethernet MAC System Time Seconds Register */

+#define ETH_MACSTSR_TSS_Pos                           (0U)

+#define ETH_MACSTSR_TSS_Msk                           (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSTSR_TSS                               ETH_MACSTSR_TSS_Msk  /* Timestamp Second */

+

+/* Bit definition for Ethernet MAC System Time Nanoseconds Register */

+#define ETH_MACSTNR_TSSS_Pos                          (0U)

+#define ETH_MACSTNR_TSSS_Msk                          (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACSTNR_TSSS                              ETH_MACSTNR_TSSS_Msk  /* Timestamp Sub-seconds */

+

+/* Bit definition for Ethernet MAC System Time Seconds Update Register */

+#define ETH_MACSTSUR_TSS_Pos                          (0U)

+#define ETH_MACSTSUR_TSS_Msk                          (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSTSUR_TSS                              ETH_MACSTSUR_TSS_Msk  /* Timestamp Seconds */

+

+/* Bit definition for Ethernet MAC System Time Nanoseconds Update Register */

+#define ETH_MACSTNUR_ADDSUB_Pos                       (31U)

+#define ETH_MACSTNUR_ADDSUB_Msk                       (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */

+#define ETH_MACSTNUR_ADDSUB                           ETH_MACSTNUR_ADDSUB_Msk  /* Add or Subtract Time */

+#define ETH_MACSTNUR_TSSS_Pos                         (0U)

+#define ETH_MACSTNUR_TSSS_Msk                         (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACSTNUR_TSSS                             ETH_MACSTNUR_TSSS_Msk  /* Timestamp Sub-seconds */

+

+/* Bit definition for Ethernet MAC Timestamp Addend Register */

+#define ETH_MACTSAR_TSAR_Pos                          (0U)

+#define ETH_MACTSAR_TSAR_Msk                          (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSAR_TSAR                              ETH_MACTSAR_TSAR_Msk  /* Timestamp Addend Register */

+

+/* Bit definition for Ethernet MAC Timestamp Status Register */

+#define ETH_MACTSSR_ATSNS_Pos                         (25U)

+#define ETH_MACTSSR_ATSNS_Msk                         (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */

+#define ETH_MACTSSR_ATSNS                             ETH_MACTSSR_ATSNS_Msk  /* Number of Auxiliary Timestamp Snapshots */

+#define ETH_MACTSSR_ATSSTM_Pos                        (24U)

+#define ETH_MACTSSR_ATSSTM_Msk                        (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */

+#define ETH_MACTSSR_ATSSTM                            ETH_MACTSSR_ATSSTM_Msk  /* Auxiliary Timestamp Snapshot Trigger Missed */

+#define ETH_MACTSSR_ATSSTN_Pos                        (16U)

+#define ETH_MACTSSR_ATSSTN_Msk                        (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */

+#define ETH_MACTSSR_ATSSTN                            ETH_MACTSSR_ATSSTN_Msk  /* Auxiliary Timestamp Snapshot Trigger Identifier */

+#define ETH_MACTSSR_TXTSSIS_Pos                       (15U)

+#define ETH_MACTSSR_TXTSSIS_Msk                       (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */

+#define ETH_MACTSSR_TXTSSIS                           ETH_MACTSSR_TXTSSIS_Msk  /* Tx Timestamp Status Interrupt Status */

+#define ETH_MACTSSR_TSTRGTERR0_Pos                    (3U)

+#define ETH_MACTSSR_TSTRGTERR0_Msk                    (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */

+#define ETH_MACTSSR_TSTRGTERR0                        ETH_MACTSSR_TSTRGTERR0_Msk  /* Timestamp Target Time Error */

+#define ETH_MACTSSR_AUXTSTRIG_Pos                     (2U)

+#define ETH_MACTSSR_AUXTSTRIG_Msk                     (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */

+#define ETH_MACTSSR_AUXTSTRIG                         ETH_MACTSSR_AUXTSTRIG_Msk  /* Auxiliary Timestamp Trigger Snapshot*/

+#define ETH_MACTSSR_TSTARGT0_Pos                      (1U)

+#define ETH_MACTSSR_TSTARGT0_Msk                      (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */

+#define ETH_MACTSSR_TSTARGT0                          ETH_MACTSSR_TSTARGT0_Msk  /* Timestamp Target Time Reached */

+#define ETH_MACTSSR_TSSOVF_Pos                        (0U)

+#define ETH_MACTSSR_TSSOVF_Msk                        (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */

+#define ETH_MACTSSR_TSSOVF                            ETH_MACTSSR_TSSOVF_Msk  /* Timestamp Seconds Overflow */

+

+/* Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register */

+#define ETH_MACTTSSNR_TXTSSMIS_Pos                    (31U)

+#define ETH_MACTTSSNR_TXTSSMIS_Msk                    (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */

+#define ETH_MACTTSSNR_TXTSSMIS                        ETH_MACTTSSNR_TXTSSMIS_Msk  /* Transmit Timestamp Status Missed */

+#define ETH_MACTTSSNR_TXTSSLO_Pos                     (0U)

+#define ETH_MACTTSSNR_TXTSSLO_Msk                     (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACTTSSNR_TXTSSLO                         ETH_MACTTSSNR_TXTSSLO_Msk  /* Transmit Timestamp Status Low */

+

+/* Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register */

+#define ETH_MACTTSSSR_TXTSSHI_Pos                     (0U)

+#define ETH_MACTTSSSR_TXTSSHI_Msk                     (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTTSSSR_TXTSSHI                         ETH_MACTTSSSR_TXTSSHI_Msk  /* Transmit Timestamp Status High */

+

+/* Bit definition for Ethernet MAC Auxiliary Control Register*/

+#define ETH_MACACR_ATSEN3_Pos                         (7U)

+#define ETH_MACACR_ATSEN3_Msk                         (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */

+#define ETH_MACACR_ATSEN3                             ETH_MACACR_ATSEN3_Msk  /* Auxiliary Snapshot 3 Enable */

+#define ETH_MACACR_ATSEN2_Pos                         (6U)

+#define ETH_MACACR_ATSEN2_Msk                         (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */

+#define ETH_MACACR_ATSEN2                             ETH_MACACR_ATSEN2_Msk  /* Auxiliary Snapshot 2 Enable */

+#define ETH_MACACR_ATSEN1_Pos                         (5U)

+#define ETH_MACACR_ATSEN1_Msk                         (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */

+#define ETH_MACACR_ATSEN1                             ETH_MACACR_ATSEN1_Msk  /* Auxiliary Snapshot 1 Enable */

+#define ETH_MACACR_ATSEN0_Pos                         (4U)

+#define ETH_MACACR_ATSEN0_Msk                         (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */

+#define ETH_MACACR_ATSEN0                             ETH_MACACR_ATSEN0_Msk  /* Auxiliary Snapshot 0 Enable */

+#define ETH_MACACR_ATSFC_Pos                          (0U)

+#define ETH_MACACR_ATSFC_Msk                          (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */

+#define ETH_MACACR_ATSFC                              ETH_MACACR_ATSFC_Msk  /* Auxiliary Snapshot FIFO Clear */

+

+/* Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register */

+#define ETH_MACATSNR_AUXTSLO_Pos                      (0U)

+#define ETH_MACATSNR_AUXTSLO_Msk                      (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACATSNR_AUXTSLO                          ETH_MACATSNR_AUXTSLO_Msk  /* Auxiliary Timestamp */

+

+/* Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register */

+#define ETH_MACATSSR_AUXTSHI_Pos                      (0U)

+#define ETH_MACATSSR_AUXTSHI_Msk                      (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACATSSR_AUXTSHI                          ETH_MACATSSR_AUXTSHI_Msk  /* Auxiliary Timestamp */

+

+/* Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register */

+#define ETH_MACTSIACR_OSTIAC_Pos                      (0U)

+#define ETH_MACTSIACR_OSTIAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSIACR_OSTIAC                          ETH_MACTSIACR_OSTIAC_Msk  /* One-Step Timestamp Ingress Asymmetry Correction */

+

+/* Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction Register */

+#define ETH_MACTSEACR_OSTEAC_Pos                      (0U)

+#define ETH_MACTSEACR_OSTEAC_Msk                      (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSEACR_OSTEAC                          ETH_MACTSEACR_OSTEAC_Msk  /* One-Step Timestamp Egress Asymmetry Correction */

+

+/* Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond Register */

+#define ETH_MACTSICNR_TSIC_Pos                        (0U)

+#define ETH_MACTSICNR_TSIC_Msk                        (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSICNR_TSIC                            ETH_MACTSICNR_TSIC_Msk  /* Timestamp Ingress Correction */

+

+/* Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond Register */

+#define ETH_MACTSECNR_TSEC_Pos                        (0U)

+#define ETH_MACTSECNR_TSEC_Msk                        (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACTSECNR_TSEC                            ETH_MACTSECNR_TSEC_Msk  /* Timestamp Egress Correction */

+

+/* Bit definition for Ethernet MAC PPS Control Register */

+#define ETH_MACPPSCR_TRGTMODSEL0_Pos                  (5U)

+#define ETH_MACPPSCR_TRGTMODSEL0_Msk                  (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */

+#define ETH_MACPPSCR_TRGTMODSEL0                      ETH_MACPPSCR_TRGTMODSEL0_Msk  /* Target Time Register Mode for PPS Output */

+#define ETH_MACPPSCR_PPSEN0_Pos                       (4U)

+#define ETH_MACPPSCR_PPSEN0_Msk                       (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */

+#define ETH_MACPPSCR_PPSEN0                           ETH_MACPPSCR_PPSEN0_Msk  /* Flexible PPS Output Mode Enable */

+#define ETH_MACPPSCR_PPSCTRL_Pos                      (0U)

+#define ETH_MACPPSCR_PPSCTRL_Msk                      (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */

+#define ETH_MACPPSCR_PPSCTRL                          ETH_MACPPSCR_PPSCTRL_Msk  /* PPS Output Frequency Control */

+

+/* Bit definition for Ethernet MAC PPS Target Time Seconds Register */

+#define ETH_MACPPSTTSR_TSTRH0_Pos                     (0U)

+#define ETH_MACPPSTTSR_TSTRH0_Msk                     (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACPPSTTSR_TSTRH0                         ETH_MACPPSTTSR_TSTRH0_Msk  /* PPS Target Time Seconds Register */

+

+/* Bit definition for Ethernet MAC PPS Target Time Nanoseconds Register */

+#define ETH_MACPPSTTNR_TRGTBUSY0_Pos                  (31U)

+#define ETH_MACPPSTTNR_TRGTBUSY0_Msk                  (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos) /*!< 0x80000000 */

+#define ETH_MACPPSTTNR_TRGTBUSY0                      ETH_MACPPSTTNR_TRGTBUSY0_Msk  /* PPS Target Time Register Busy */

+#define ETH_MACPPSTTNR_TTSL0_Pos                      (0U)

+#define ETH_MACPPSTTNR_TTSL0_Msk                      (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x7FFFFFFF */

+#define ETH_MACPPSTTNR_TTSL0                          ETH_MACPPSTTNR_TTSL0_Msk  /* Target Time Low for PPS Register */

+

+/* Bit definition for Ethernet MAC PPS Interval Register */

+#define ETH_MACPPSIR_PPSINT0_Pos                      (0U)

+#define ETH_MACPPSIR_PPSINT0_Msk                      (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACPPSIR_PPSINT0                          ETH_MACPPSIR_PPSINT0_Msk  /* PPS Output Signal Interval */

+

+/* Bit definition for Ethernet MAC PPS Width Register */

+#define ETH_MACPPSWR_PPSWIDTH0_Pos                    (0U)

+#define ETH_MACPPSWR_PPSWIDTH0_Msk                    (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACPPSWR_PPSWIDTH0                        ETH_MACPPSWR_PPSWIDTH0_Msk  /* PPS Output Signal Width */

+

+/* Bit definition for Ethernet MAC PTP Offload Control Register */

+#define ETH_MACPOCR_DN_Pos                            (8U)

+#define ETH_MACPOCR_DN_Msk                            (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */

+#define ETH_MACPOCR_DN                                ETH_MACPOCR_DN_Msk  /* Domain Number */

+#define ETH_MACPOCR_DRRDIS_Pos                        (6U)

+#define ETH_MACPOCR_DRRDIS_Msk                        (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */

+#define ETH_MACPOCR_DRRDIS                            ETH_MACPOCR_DRRDIS_Msk  /* Disable PTO Delay Request/Response response generation */

+#define ETH_MACPOCR_APDREQTRIG_Pos                    (5U)

+#define ETH_MACPOCR_APDREQTRIG_Msk                    (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */

+#define ETH_MACPOCR_APDREQTRIG                        ETH_MACPOCR_APDREQTRIG_Msk  /* Automatic PTP Pdelay_Req message Trigger */

+#define ETH_MACPOCR_ASYNCTRIG_Pos                     (4U)

+#define ETH_MACPOCR_ASYNCTRIG_Msk                     (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */

+#define ETH_MACPOCR_ASYNCTRIG                         ETH_MACPOCR_ASYNCTRIG_Msk  /* Automatic PTP SYNC message Trigger */

+#define ETH_MACPOCR_APDREQEN_Pos                      (2U)

+#define ETH_MACPOCR_APDREQEN_Msk                      (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */

+#define ETH_MACPOCR_APDREQEN                          ETH_MACPOCR_APDREQEN_Msk  /* Automatic PTP Pdelay_Req message Enable */

+#define ETH_MACPOCR_ASYNCEN_Pos                       (1U)

+#define ETH_MACPOCR_ASYNCEN_Msk                       (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */

+#define ETH_MACPOCR_ASYNCEN                           ETH_MACPOCR_ASYNCEN_Msk  /* Automatic PTP SYNC message Enable */

+#define ETH_MACPOCR_PTOEN_Pos                         (0U)

+#define ETH_MACPOCR_PTOEN_Msk                         (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */

+#define ETH_MACPOCR_PTOEN                             ETH_MACPOCR_PTOEN_Msk  /* PTP Offload Enable */

+

+/* Bit definition for Ethernet MAC PTP Source Port Identity 0 Register */

+#define ETH_MACSPI0R_SPI0_Pos                         (0U)

+#define ETH_MACSPI0R_SPI0_Msk                         (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSPI0R_SPI0                             ETH_MACSPI0R_SPI0_Msk  /* Source Port Identity 0 */

+

+/* Bit definition for Ethernet MAC PTP Source Port Identity 1 Register */

+#define ETH_MACSPI1R_SPI1_Pos                         (0U)

+#define ETH_MACSPI1R_SPI1_Msk                         (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */

+#define ETH_MACSPI1R_SPI1                             ETH_MACSPI1R_SPI1_Msk  /* Source Port Identity 1 */

+

+/* Bit definition for Ethernet MAC PTP Source Port Identity 2 Register */

+#define ETH_MACSPI2R_SPI2_Pos                         (0U)

+#define ETH_MACSPI2R_SPI2_Msk                         (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */

+#define ETH_MACSPI2R_SPI2                             ETH_MACSPI2R_SPI2_Msk  /* Source Port Identity 2 */

+

+/* Bit definition for Ethernet MAC Log Message Interval Register */

+#define ETH_MACLMIR_LMPDRI_Pos                        (24U)

+#define ETH_MACLMIR_LMPDRI_Msk                        (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */

+#define ETH_MACLMIR_LMPDRI                             ETH_MACLMIR_LMPDRI_Msk  /* Log Min Pdelay_Req Interval */

+#define ETH_MACLMIR_DRSYNCR_Pos                       (8U)

+#define ETH_MACLMIR_DRSYNCR_Msk                       (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */

+#define ETH_MACLMIR_DRSYNCR                           ETH_MACLMIR_DRSYNCR_Msk  /* Delay_Req to SYNC Ratio */

+#define ETH_MACLMIR_LSI_Pos                           (0U)

+#define ETH_MACLMIR_LSI_Msk                           (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */

+#define ETH_MACLMIR_LSI                               ETH_MACLMIR_LSI_Msk  /* Log Sync Interval */

+

+/* Bit definition for Ethernet MTL Operation Mode Register */

+#define ETH_MTLOMR_CNTCLR_Pos                         (9U)

+#define ETH_MTLOMR_CNTCLR_Msk                         (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */

+#define ETH_MTLOMR_CNTCLR                             ETH_MTLOMR_CNTCLR_Msk    /* Counters Reset */

+#define ETH_MTLOMR_CNTPRST_Pos                        (8U)

+#define ETH_MTLOMR_CNTPRST_Msk                        (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */

+#define ETH_MTLOMR_CNTPRST                            ETH_MTLOMR_CNTPRST_Msk   /* Counters Preset */

+#define ETH_MTLOMR_DTXSTS_Pos                         (1U)

+#define ETH_MTLOMR_DTXSTS_Msk                         (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */

+#define ETH_MTLOMR_DTXSTS                             ETH_MTLOMR_DTXSTS_Msk  /* Drop Transmit Status */

+

+/* Bit definition for Ethernet MTL Interrupt Status Register */

+#define ETH_MTLISR_MACIS_Pos                          (16U)

+#define ETH_MTLISR_MACIS_Msk                          (0x1UL << ETH_MTLISR_MACIS_Pos) /*!< 0x00010000 */

+#define ETH_MTLISR_MACIS                              ETH_MTLISR_MACIS_Msk     /* MAC Interrupt Status */

+#define ETH_MTLISR_QIS_Pos                            (0U)

+#define ETH_MTLISR_QIS_Msk                            (0x1UL << ETH_MTLISR_QIS_Pos) /*!< 0x00000001 */

+#define ETH_MTLISR_QIS                                ETH_MTLISR_QIS_Msk       /* Queue Interrupt status */

+

+/* Bit definition for Ethernet MTL Tx Queue Operation Mode Register */

+#define ETH_MTLTQOMR_TTC_Pos                          (4U)

+#define ETH_MTLTQOMR_TTC_Msk                          (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */

+#define ETH_MTLTQOMR_TTC                              ETH_MTLTQOMR_TTC_Msk     /* Transmit Threshold Control */

+#define ETH_MTLTQOMR_TTC_32BITS                       ((uint32_t)0x00000000)   /* 32 bits Threshold */

+#define ETH_MTLTQOMR_TTC_64BITS                       ((uint32_t)0x00000010)   /* 64  bits Threshold */

+#define ETH_MTLTQOMR_TTC_96BITS                       ((uint32_t)0x00000020)   /* 96 bits Threshold */

+#define ETH_MTLTQOMR_TTC_128BITS                      ((uint32_t)0x00000030)   /* 128 bits Threshold */

+#define ETH_MTLTQOMR_TTC_192BITS                      ((uint32_t)0x00000040)   /* 192 bits Threshold */

+#define ETH_MTLTQOMR_TTC_256BITS                      ((uint32_t)0x00000050)   /* 256 bits Threshold */

+#define ETH_MTLTQOMR_TTC_384BITS                      ((uint32_t)0x00000060)   /* 384 bits Threshold */

+#define ETH_MTLTQOMR_TTC_512BITS                      ((uint32_t)0x00000070)   /* 512 bits Threshold */

+#define ETH_MTLTQOMR_TSF_Pos                          (1U)

+#define ETH_MTLTQOMR_TSF_Msk                          (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */

+#define ETH_MTLTQOMR_TSF                              ETH_MTLTQOMR_TSF_Msk     /* Transmit Store and Forward */

+#define ETH_MTLTQOMR_FTQ_Pos                          (0U)

+#define ETH_MTLTQOMR_FTQ_Msk                          (0x1UL << ETH_MTLTQOMR_FTQ_Pos) /*!< 0x00000001 */

+#define ETH_MTLTQOMR_FTQ                              ETH_MTLTQOMR_FTQ_Msk     /* Flush Transmit Queue */

+

+/* Bit definition for Ethernet MTL Tx Queue Underflow Register */

+#define ETH_MTLTQUR_UFCNTOVF_Pos                      (11U)

+#define ETH_MTLTQUR_UFCNTOVF_Msk                      (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos) /*!< 0x00000800 */

+#define ETH_MTLTQUR_UFCNTOVF                          ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */

+#define ETH_MTLTQUR_UFPKTCNT_Pos                      (0U)

+#define ETH_MTLTQUR_UFPKTCNT_Msk                      (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos) /*!< 0x000007FF */

+#define ETH_MTLTQUR_UFPKTCNT                          ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */

+

+/* Bit definition for Ethernet MTL Tx Queue Debug Register */

+#define ETH_MTLTQDR_STXSTSF_Pos                       (20U)

+#define ETH_MTLTQDR_STXSTSF_Msk                       (0x7UL << ETH_MTLTQDR_STXSTSF_Pos) /*!< 0x00700000 */

+#define ETH_MTLTQDR_STXSTSF                           ETH_MTLTQDR_STXSTSF_Msk  /* Number of Status Words in the Tx Status FIFO of Queue */

+#define ETH_MTLTQDR_PTXQ_Pos                          (16U)

+#define ETH_MTLTQDR_PTXQ_Msk                          (0x7UL << ETH_MTLTQDR_PTXQ_Pos) /*!< 0x00070000 */

+#define ETH_MTLTQDR_PTXQ                              ETH_MTLTQDR_PTXQ_Msk     /* Number of Packets in the Transmit Queue */

+#define ETH_MTLTQDR_TXSTSFSTS_Pos                     (5U)

+#define ETH_MTLTQDR_TXSTSFSTS_Msk                     (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos) /*!< 0x00000020 */

+#define ETH_MTLTQDR_TXSTSFSTS                         ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */

+#define ETH_MTLTQDR_TXQSTS_Pos                        (4U)

+#define ETH_MTLTQDR_TXQSTS_Msk                        (0x1UL << ETH_MTLTQDR_TXQSTS_Pos) /*!< 0x00000010 */

+#define ETH_MTLTQDR_TXQSTS                            ETH_MTLTQDR_TXQSTS_Msk   /* MTL Tx Queue Not Empty Status */

+#define ETH_MTLTQDR_TWCSTS_Pos                        (3U)

+#define ETH_MTLTQDR_TWCSTS_Msk                        (0x1UL << ETH_MTLTQDR_TWCSTS_Pos) /*!< 0x00000008 */

+#define ETH_MTLTQDR_TWCSTS                            ETH_MTLTQDR_TWCSTS_Msk   /* MTL Tx Queue Write Controller Status */

+#define ETH_MTLTQDR_TRCSTS_Pos                        (1U)

+#define ETH_MTLTQDR_TRCSTS_Msk                        (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */

+#define ETH_MTLTQDR_TRCSTS                            ETH_MTLTQDR_TRCSTS_Msk  /* MTL Tx Queue Read Controller Status */

+#define ETH_MTLTQDR_TRCSTS_IDLE                       ((uint32_t)0x00000000)  /* Idle state */

+#define ETH_MTLTQDR_TRCSTS_READ                       ((uint32_t)0x00000002)  /* Read state (transferring data to the MAC transmitter) */

+#define ETH_MTLTQDR_TRCSTS_WAITING                    ((uint32_t)0x00000004)  /* Waiting for pending Tx Status from the MAC transmitter */

+#define ETH_MTLTQDR_TRCSTS_FLUSHING                   ((uint32_t)0x00000006)  /* Flushing the Tx queue because of the Packet Abort request from the MAC */

+#define ETH_MTLTQDR_TXQPAUSED_Pos                     (0U)

+#define ETH_MTLTQDR_TXQPAUSED_Msk                     (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */

+#define ETH_MTLTQDR_TXQPAUSED                         ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */

+

+/* Bit definition for Ethernet MTL Queue Interrupt Control Status Register */

+#define ETH_MTLQICSR_RXOIE_Pos                        (24U)

+#define ETH_MTLQICSR_RXOIE_Msk                        (0x1UL << ETH_MTLQICSR_RXOIE_Pos) /*!< 0x01000000 */

+#define ETH_MTLQICSR_RXOIE                            ETH_MTLQICSR_RXOIE_Msk   /* Receive Queue Overflow Interrupt Enable */

+#define ETH_MTLQICSR_RXOVFIS_Pos                      (16U)

+#define ETH_MTLQICSR_RXOVFIS_Msk                      (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos) /*!< 0x00010000 */

+#define ETH_MTLQICSR_RXOVFIS                          ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */

+#define ETH_MTLQICSR_TXUIE_Pos                        (8U)

+#define ETH_MTLQICSR_TXUIE_Msk                        (0x1UL << ETH_MTLQICSR_TXUIE_Pos) /*!< 0x00000100 */

+#define ETH_MTLQICSR_TXUIE                            ETH_MTLQICSR_TXUIE_Msk   /* Transmit Queue Underflow Interrupt Enable */

+#define ETH_MTLQICSR_TXUNFIS_Pos                      (0U)

+#define ETH_MTLQICSR_TXUNFIS_Msk                      (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos) /*!< 0x00000001 */

+#define ETH_MTLQICSR_TXUNFIS                          ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */

+

+/* Bit definition for Ethernet MTL Rx Queue Operation Mode Register */

+#define ETH_MTLRQOMR_RQS_Pos                          (20U)

+#define ETH_MTLRQOMR_RQS_Msk                          (0x7UL << ETH_MTLRQOMR_RQS_Pos) /*!< 0x00700000 */

+#define ETH_MTLRQOMR_RQS                              ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */

+#define ETH_MTLRQOMR_RFD_Pos                          (14U)

+#define ETH_MTLRQOMR_RFD_Msk                          (0x7UL << ETH_MTLRQOMR_RFD_Pos) /*!< 0x0001C000 */

+#define ETH_MTLRQOMR_RFD                              ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */

+#define ETH_MTLRQOMR_RFA_Pos                          (8U)

+#define ETH_MTLRQOMR_RFA_Msk                          (0x7UL << ETH_MTLRQOMR_RFA_Pos) /*!< 0x00000700 */

+#define ETH_MTLRQOMR_RFA                              ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */

+#define ETH_MTLRQOMR_EHFC_Pos                         (7U)

+#define ETH_MTLRQOMR_EHFC_Msk                         (0x1UL << ETH_MTLRQOMR_EHFC_Pos) /*!< 0x00000080 */

+#define ETH_MTLRQOMR_EHFC                             ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */

+#define ETH_MTLRQOMR_DISTCPEF_Pos                     (6U)

+#define ETH_MTLRQOMR_DISTCPEF_Msk                     (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos) /*!< 0x00000040 */

+#define ETH_MTLRQOMR_DISTCPEF                         ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */

+#define ETH_MTLRQOMR_RSF_Pos                          (5U)

+#define ETH_MTLRQOMR_RSF_Msk                          (0x1UL << ETH_MTLRQOMR_RSF_Pos) /*!< 0x00000020 */

+#define ETH_MTLRQOMR_RSF                              ETH_MTLRQOMR_RSF_Msk     /* Receive Queue Store and Forward */

+#define ETH_MTLRQOMR_FEP_Pos                          (4U)

+#define ETH_MTLRQOMR_FEP_Msk                          (0x1UL << ETH_MTLRQOMR_FEP_Pos) /*!< 0x00000010 */

+#define ETH_MTLRQOMR_FEP                              ETH_MTLRQOMR_FEP_Msk     /* Forward Error Packets */

+#define ETH_MTLRQOMR_FUP_Pos                          (3U)

+#define ETH_MTLRQOMR_FUP_Msk                          (0x1UL << ETH_MTLRQOMR_FUP_Pos) /*!< 0x00000008 */

+#define ETH_MTLRQOMR_FUP                              ETH_MTLRQOMR_FUP_Msk     /* Forward Undersized Good Packets */

+#define ETH_MTLRQOMR_RTC_Pos                          (0U)

+#define ETH_MTLRQOMR_RTC_Msk                          (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */

+#define ETH_MTLRQOMR_RTC                              ETH_MTLRQOMR_RTC_Msk     /* Receive Queue Threshold Control */

+#define ETH_MTLRQOMR_RTC_64BITS                       ((uint32_t)0x00000000)   /* 64 bits Threshold */

+#define ETH_MTLRQOMR_RTC_32BITS                       ((uint32_t)0x00000001)   /* 32 bits Threshold */

+#define ETH_MTLRQOMR_RTC_96BITS                       ((uint32_t)0x00000002)   /* 96 bits Threshold */

+#define ETH_MTLRQOMR_RTC_128BITS                      ((uint32_t)0x00000003)   /* 128 bits Threshold */

+

+/* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */

+#define ETH_MTLRQMPOCR_MISCNTOVF_Pos                  (27U)

+#define ETH_MTLRQMPOCR_MISCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */

+#define ETH_MTLRQMPOCR_MISCNTOVF                      ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */

+#define ETH_MTLRQMPOCR_MISPKTCNT_Pos                  (16U)

+#define ETH_MTLRQMPOCR_MISPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */

+#define ETH_MTLRQMPOCR_MISPKTCNT                      ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */

+#define ETH_MTLRQMPOCR_OVFCNTOVF_Pos                  (11U)

+#define ETH_MTLRQMPOCR_OVFCNTOVF_Msk                  (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */

+#define ETH_MTLRQMPOCR_OVFCNTOVF                      ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */

+#define ETH_MTLRQMPOCR_OVFPKTCNT_Pos                  (0U)

+#define ETH_MTLRQMPOCR_OVFPKTCNT_Msk                  (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */

+#define ETH_MTLRQMPOCR_OVFPKTCNT                      ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */

+

+/* Bit definition for Ethernet MTL Rx Queue Debug Register */

+#define ETH_MTLRQDR_PRXQ_Pos                          (16U)

+#define ETH_MTLRQDR_PRXQ_Msk                          (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos) /*!< 0x3FFF0000 */

+#define ETH_MTLRQDR_PRXQ                              ETH_MTLRQDR_PRXQ_Msk     /* Number of Packets in Receive Queue */

+#define ETH_MTLRQDR_RXQSTS_Pos                        (4U)

+#define ETH_MTLRQDR_RXQSTS_Msk                        (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */

+#define ETH_MTLRQDR_RXQSTS                            ETH_MTLRQDR_RXQSTS_Msk   /* MTL Rx Queue Fill-Level Status */

+#define ETH_MTLRQDR_RXQSTS_EMPTY                      ((uint32_t)0x00000000)   /* Rx Queue empty */

+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos         (4U)

+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */

+#define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD             ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */

+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos         (5U)

+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk         (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */

+#define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD             ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */

+#define ETH_MTLRQDR_RXQSTS_FULL_Pos                   (4U)

+#define ETH_MTLRQDR_RXQSTS_FULL_Msk                   (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */

+#define ETH_MTLRQDR_RXQSTS_FULL                       ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */

+#define ETH_MTLRQDR_RRCSTS_Pos                        (1U)

+#define ETH_MTLRQDR_RRCSTS_Msk                        (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */

+#define ETH_MTLRQDR_RRCSTS                            ETH_MTLRQDR_RRCSTS_Msk   /* MTL Rx Queue Read Controller State */

+#define ETH_MTLRQDR_RRCSTS_IDLE                       ((uint32_t)0x00000000)   /* Idle state */

+#define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos            (1U)

+#define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk            (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */

+#define ETH_MTLRQDR_RRCSTS_READINGDATA                ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */

+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos          (2U)

+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk          (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */

+#define ETH_MTLRQDR_RRCSTS_READINGSTATUS              ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */

+#define ETH_MTLRQDR_RRCSTS_FLUSHING_Pos               (1U)

+#define ETH_MTLRQDR_RRCSTS_FLUSHING_Msk               (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */

+#define ETH_MTLRQDR_RRCSTS_FLUSHING                   ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */

+#define ETH_MTLRQDR_RWCSTS_Pos                        (0U)

+#define ETH_MTLRQDR_RWCSTS_Msk                        (0x1UL << ETH_MTLRQDR_RWCSTS_Pos) /*!< 0x00000001 */

+#define ETH_MTLRQDR_RWCSTS                            ETH_MTLRQDR_RWCSTS_Msk   /* MTL Rx Queue Write Controller Active Status */

+

+/* Bit definition for Ethernet MTL Rx Queue Control Register */

+#define ETH_MTLRQCR_RQPA_Pos                          (3U)

+#define ETH_MTLRQCR_RQPA_Msk                          (0x1UL << ETH_MTLRQCR_RQPA_Pos) /*!< 0x00000008 */

+#define ETH_MTLRQCR_RQPA                              ETH_MTLRQCR_RQPA_Msk     /* Receive Queue Packet Arbitration */

+#define ETH_MTLRQCR_RQW_Pos                           (0U)

+#define ETH_MTLRQCR_RQW_Msk                           (0x7UL << ETH_MTLRQCR_RQW_Pos) /*!< 0x00000007 */

+#define ETH_MTLRQCR_RQW                               ETH_MTLRQCR_RQW_Msk      /* Receive Queue Weight */

+

+/* Bit definition for Ethernet DMA Mode Register */

+#define ETH_DMAMR_INTM_Pos                            (16U)

+#define ETH_DMAMR_INTM_Msk                            (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */

+#define ETH_DMAMR_INTM                                ETH_DMAMR_INTM_Msk       /* This field defines the interrupt mode */

+#define ETH_DMAMR_INTM_0                              (0x0UL << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */

+#define ETH_DMAMR_INTM_1                              (0x1UL << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */

+#define ETH_DMAMR_INTM_2                              (0x2UL << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */

+#define ETH_DMAMR_PR_Pos                              (12U)

+#define ETH_DMAMR_PR_Msk                              (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */

+#define ETH_DMAMR_PR                                  ETH_DMAMR_PR_Msk         /* Priority Ratio */

+#define ETH_DMAMR_PR_1_1                              ((uint32_t)0x00000000)   /* The priority ratio is 1:1 */

+#define ETH_DMAMR_PR_2_1                              ((uint32_t)0x00001000)   /* The priority ratio is 2:1 */

+#define ETH_DMAMR_PR_3_1                              ((uint32_t)0x00002000)   /* The priority ratio is 3:1 */

+#define ETH_DMAMR_PR_4_1                              ((uint32_t)0x00003000)   /* The priority ratio is 4:1 */

+#define ETH_DMAMR_PR_5_1                              ((uint32_t)0x00004000)   /* The priority ratio is 5:1 */

+#define ETH_DMAMR_PR_6_1                              ((uint32_t)0x00005000)   /* The priority ratio is 6:1 */

+#define ETH_DMAMR_PR_7_1                              ((uint32_t)0x00006000)   /* The priority ratio is 7:1 */

+#define ETH_DMAMR_PR_8_1                              ((uint32_t)0x00007000)   /* The priority ratio is 8:1 */

+#define ETH_DMAMR_TXPR_Pos                            (11U)

+#define ETH_DMAMR_TXPR_Msk                            (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */

+#define ETH_DMAMR_TXPR                                ETH_DMAMR_TXPR_Msk       /* Transmit Priority */

+#define ETH_DMAMR_DA_Pos                              (1U)

+#define ETH_DMAMR_DA_Msk                              (0x1UL << ETH_DMAMR_DA_Pos) /*!< 0x00000002 */

+#define ETH_DMAMR_DA                                  ETH_DMAMR_DA_Msk         /* DMA Tx or Rx Arbitration Scheme */

+#define ETH_DMAMR_SWR_Pos                             (0U)

+#define ETH_DMAMR_SWR_Msk                             (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */

+#define ETH_DMAMR_SWR                                 ETH_DMAMR_SWR_Msk        /* Software Reset */

+

+/* Bit definition for Ethernet DMA SysBus Mode Register */

+#define ETH_DMASBMR_RB_Pos                            (15U)

+#define ETH_DMASBMR_RB_Msk                            (0x1UL << ETH_DMASBMR_RB_Pos) /*!< 0x00008000 */

+#define ETH_DMASBMR_RB                                ETH_DMASBMR_RB_Msk       /* Rebuild INCRx Burst */

+#define ETH_DMASBMR_MB_Pos                            (14U)

+#define ETH_DMASBMR_MB_Msk                            (0x1UL << ETH_DMASBMR_MB_Pos) /*!< 0x00004000 */

+#define ETH_DMASBMR_MB                                ETH_DMASBMR_MB_Msk       /* Mixed Burst */

+#define ETH_DMASBMR_AAL_Pos                           (12U)

+#define ETH_DMASBMR_AAL_Msk                           (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */

+#define ETH_DMASBMR_AAL                               ETH_DMASBMR_AAL_Msk      /* Address-Aligned Beats */

+#define ETH_DMASBMR_FB_Pos                            (0U)

+#define ETH_DMASBMR_FB_Msk                            (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */

+#define ETH_DMASBMR_FB                                ETH_DMASBMR_FB_Msk       /* Fixed Burst Length */

+

+/* Bit definition for Ethernet DMA Interrupt Status Register */

+#define ETH_DMAISR_MACIS_Pos                          (17U)

+#define ETH_DMAISR_MACIS_Msk                          (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */

+#define ETH_DMAISR_MACIS                              ETH_DMAISR_MACIS_Msk     /* MAC Interrupt Status */

+#define ETH_DMAISR_MTLIS_Pos                          (16U)

+#define ETH_DMAISR_MTLIS_Msk                          (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */

+#define ETH_DMAISR_MTLIS                              ETH_DMAISR_MTLIS_Msk     /* MAC Interrupt Status */

+#define ETH_DMAISR_DMACIS_Pos                         (0U)

+#define ETH_DMAISR_DMACIS_Msk                         (0x1UL << ETH_DMAISR_DMACIS_Pos) /*!< 0x00000001 */

+#define ETH_DMAISR_DMACIS                             ETH_DMAISR_DMACIS_Msk    /* DMA Channel Interrupt Status */

+

+/* Bit definition for Ethernet DMA Debug Status Register */

+#define ETH_DMADSR_TPS_Pos                            (12U)

+#define ETH_DMADSR_TPS_Msk                            (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */

+#define ETH_DMADSR_TPS                                ETH_DMADSR_TPS_Msk       /* DMA Channel Transmit Process State */

+#define ETH_DMADSR_TPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Transmit Command issued) */

+#define ETH_DMADSR_TPS_FETCHING_Pos                   (12U)

+#define ETH_DMADSR_TPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */

+#define ETH_DMADSR_TPS_FETCHING                       ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */

+#define ETH_DMADSR_TPS_WAITING_Pos                    (13U)

+#define ETH_DMADSR_TPS_WAITING_Msk                    (0x1UL << ETH_DMADSR_TPS_WAITING_Pos) /*!< 0x00002000 */

+#define ETH_DMADSR_TPS_WAITING                        ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */

+#define ETH_DMADSR_TPS_READING_Pos                    (12U)

+#define ETH_DMADSR_TPS_READING_Msk                    (0x3UL << ETH_DMADSR_TPS_READING_Pos) /*!< 0x00003000 */

+#define ETH_DMADSR_TPS_READING                        ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */

+#define ETH_DMADSR_TPS_TIMESTAMP_WR_Pos               (14U)

+#define ETH_DMADSR_TPS_TIMESTAMP_WR_Msk               (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos) /*!< 0x00004000 */

+#define ETH_DMADSR_TPS_TIMESTAMP_WR                   ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */

+#define ETH_DMADSR_TPS_SUSPENDED_Pos                  (13U)

+#define ETH_DMADSR_TPS_SUSPENDED_Msk                  (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos) /*!< 0x00006000 */

+#define ETH_DMADSR_TPS_SUSPENDED                      ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */

+#define ETH_DMADSR_TPS_CLOSING_Pos                    (12U)

+#define ETH_DMADSR_TPS_CLOSING_Msk                    (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos) /*!< 0x00007000 */

+#define ETH_DMADSR_TPS_CLOSING                        ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */

+#define ETH_DMADSR_RPS_Pos                            (8U)

+#define ETH_DMADSR_RPS_Msk                            (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */

+#define ETH_DMADSR_RPS                                ETH_DMADSR_RPS_Msk       /* DMA Channel Receive Process State */

+#define ETH_DMADSR_RPS_STOPPED                        ((uint32_t)0x00000000)   /* Stopped (Reset or Stop Receive Command issued) */

+#define ETH_DMADSR_RPS_FETCHING_Pos                   (12U)

+#define ETH_DMADSR_RPS_FETCHING_Msk                   (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */

+#define ETH_DMADSR_RPS_FETCHING                       ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */

+#define ETH_DMADSR_RPS_WAITING_Pos                    (12U)

+#define ETH_DMADSR_RPS_WAITING_Msk                    (0x3UL << ETH_DMADSR_RPS_WAITING_Pos) /*!< 0x00003000 */

+#define ETH_DMADSR_RPS_WAITING                        ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */

+#define ETH_DMADSR_RPS_SUSPENDED_Pos                  (14U)

+#define ETH_DMADSR_RPS_SUSPENDED_Msk                  (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos) /*!< 0x00004000 */

+#define ETH_DMADSR_RPS_SUSPENDED                      ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */

+#define ETH_DMADSR_RPS_CLOSING_Pos                    (12U)

+#define ETH_DMADSR_RPS_CLOSING_Msk                    (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos) /*!< 0x00005000 */

+#define ETH_DMADSR_RPS_CLOSING                        ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */

+#define ETH_DMADSR_RPS_TIMESTAMP_WR_Pos               (13U)

+#define ETH_DMADSR_RPS_TIMESTAMP_WR_Msk               (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos) /*!< 0x00006000 */

+#define ETH_DMADSR_RPS_TIMESTAMP_WR                   ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */

+#define ETH_DMADSR_RPS_TRANSFERRING_Pos               (12U)

+#define ETH_DMADSR_RPS_TRANSFERRING_Msk               (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos) /*!< 0x00007000 */

+#define ETH_DMADSR_RPS_TRANSFERRING                   ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */

+

+/* Bit definition for Ethernet DMA Channel Control Register */

+#define ETH_DMACCR_DSL_Pos                            (18U)

+#define ETH_DMACCR_DSL_Msk                            (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */

+#define ETH_DMACCR_DSL                                ETH_DMACCR_DSL_Msk       /* Descriptor Skip Length */

+#define ETH_DMACCR_DSL_0BIT                           ((uint32_t)0x00000000)

+#define ETH_DMACCR_DSL_32BIT                          ((uint32_t)0x00040000)

+#define ETH_DMACCR_DSL_64BIT                          ((uint32_t)0x00080000)

+#define ETH_DMACCR_DSL_128BIT                         ((uint32_t)0x00100000)

+#define ETH_DMACCR_8PBL                               ((uint32_t)0x00010000)   /* 8xPBL mode */

+#define ETH_DMACCR_MSS_Pos                            (0U)

+#define ETH_DMACCR_MSS_Msk                            (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */

+#define ETH_DMACCR_MSS                                ETH_DMACCR_MSS_Msk       /* Maximum Segment Size */

+

+/* Bit definition for Ethernet DMA Channel Tx Control Register */

+#define ETH_DMACTCR_TPBL_Pos                          (16U)

+#define ETH_DMACTCR_TPBL_Msk                          (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */

+#define ETH_DMACTCR_TPBL                              ETH_DMACTCR_TPBL_Msk     /* Transmit Programmable Burst Length */

+#define ETH_DMACTCR_TPBL_1PBL                         ((uint32_t)0x00010000)   /* Transmit Programmable Burst Length 1 */

+#define ETH_DMACTCR_TPBL_2PBL                         ((uint32_t)0x00020000)   /* Transmit Programmable Burst Length 2 */

+#define ETH_DMACTCR_TPBL_4PBL                         ((uint32_t)0x00040000)   /* Transmit Programmable Burst Length 4 */

+#define ETH_DMACTCR_TPBL_8PBL                         ((uint32_t)0x00080000)   /* Transmit Programmable Burst Length 8 */

+#define ETH_DMACTCR_TPBL_16PBL                        ((uint32_t)0x00100000)   /* Transmit Programmable Burst Length 16 */

+#define ETH_DMACTCR_TPBL_32PBL                        ((uint32_t)0x00200000)   /* Transmit Programmable Burst Length 32 */

+#define ETH_DMACTCR_TSE_Pos                           (12U)

+#define ETH_DMACTCR_TSE_Msk                           (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */

+#define ETH_DMACTCR_TSE                               ETH_DMACTCR_TSE_Msk      /* TCP Segmentation Enabled */

+#define ETH_DMACTCR_OSP_Pos                           (4U)

+#define ETH_DMACTCR_OSP_Msk                           (0x1UL << ETH_DMACTCR_OSP_Pos) /*!< 0x00000010 */

+#define ETH_DMACTCR_OSP                               ETH_DMACTCR_OSP_Msk      /* Operate on Second Packet */

+#define ETH_DMACTCR_ST_Pos                            (0U)

+#define ETH_DMACTCR_ST_Msk                            (0x1UL << ETH_DMACTCR_ST_Pos) /*!< 0x00000001 */

+#define ETH_DMACTCR_ST                                ETH_DMACTCR_ST_Msk       /* Start or Stop Transmission Command */

+

+/* Bit definition for Ethernet DMA Channel Rx Control Register */

+#define ETH_DMACRCR_RPF_Pos                           (31U)

+#define ETH_DMACRCR_RPF_Msk                           (0x1UL << ETH_DMACRCR_RPF_Pos) /*!< 0x80000000 */

+#define ETH_DMACRCR_RPF                               ETH_DMACRCR_RPF_Msk      /* Rx Packet Flush */

+#define ETH_DMACRCR_RPBL_Pos                          (16U)

+#define ETH_DMACRCR_RPBL_Msk                          (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */

+#define ETH_DMACRCR_RPBL                              ETH_DMACRCR_RPBL_Msk     /* Receive Programmable Burst Length */

+#define ETH_DMACRCR_RPBL_1PBL                         ((uint32_t)0x00010000)   /* Receive Programmable Burst Length 1 */

+#define ETH_DMACRCR_RPBL_2PBL                         ((uint32_t)0x00020000)   /* Receive Programmable Burst Length 2 */

+#define ETH_DMACRCR_RPBL_4PBL                         ((uint32_t)0x00040000)   /* Receive Programmable Burst Length 4 */

+#define ETH_DMACRCR_RPBL_8PBL                         ((uint32_t)0x00080000)   /* Receive Programmable Burst Length 8 */

+#define ETH_DMACRCR_RPBL_16PBL                        ((uint32_t)0x00100000)   /* Receive Programmable Burst Length 16 */

+#define ETH_DMACRCR_RPBL_32PBL                        ((uint32_t)0x00200000)   /* Receive Programmable Burst Length 32 */

+#define ETH_DMACRCR_RBSZ_Pos                          (1U)

+#define ETH_DMACRCR_RBSZ_Msk                          (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */

+#define ETH_DMACRCR_RBSZ                              ETH_DMACRCR_RBSZ_Msk     /* Receive Buffer size */

+#define ETH_DMACRCR_SR_Pos                            (0U)

+#define ETH_DMACRCR_SR_Msk                            (0x1UL << ETH_DMACRCR_SR_Pos) /*!< 0x00000001 */

+#define ETH_DMACRCR_SR                                ETH_DMACRCR_SR_Msk       /* Start or Stop Receive */

+

+/* Bit definition for Ethernet DMA CH Tx Desc List Address Register */

+#define ETH_DMACTDLAR_TDESLA_Pos                      (2U)

+#define ETH_DMACTDLAR_TDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACTDLAR_TDESLA                          ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */

+

+/* Bit definition for Ethernet DMA CH Rx Desc List Address Register */

+#define ETH_DMACRDLAR_RDESLA_Pos                      (2U)

+#define ETH_DMACRDLAR_RDESLA_Msk                      (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACRDLAR_RDESLA                          ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */

+

+/* Bit definition for Ethernet DMA CH Tx Desc Tail Pointer Register */

+#define ETH_DMACTDTPR_TDT_Pos                         (2U)

+#define ETH_DMACTDTPR_TDT_Msk                         (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACTDTPR_TDT                             ETH_DMACTDTPR_TDT_Msk    /* Transmit Descriptor Tail Pointer */

+

+/* Bit definition for Ethernet DMA CH Rx Desc Tail Pointer Register */

+#define ETH_DMACRDTPR_RDT_Pos                         (2U)

+#define ETH_DMACRDTPR_RDT_Msk                         (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos) /*!< 0xFFFFFFFC */

+#define ETH_DMACRDTPR_RDT                             ETH_DMACRDTPR_RDT_Msk    /* Receive Descriptor Tail Pointer */

+

+/* Bit definition for Ethernet DMA CH Tx Desc Ring Length Register */

+#define ETH_DMACTDRLR_TDRL_Pos                        (0U)

+#define ETH_DMACTDRLR_TDRL_Msk                        (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos) /*!< 0x000003FF */

+#define ETH_DMACTDRLR_TDRL                            ETH_DMACTDRLR_TDRL_Msk   /* Transmit Descriptor Ring Length */

+

+/* Bit definition for Ethernet DMA CH Rx Desc Ring Length Register */

+#define ETH_DMACRDRLR_RDRL_Pos                        (0U)

+#define ETH_DMACRDRLR_RDRL_Msk                        (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos) /*!< 0x000003FF */

+#define ETH_DMACRDRLR_RDRL                            ETH_DMACRDRLR_RDRL_Msk   /* Receive Descriptor Ring Length */

+

+/* Bit definition for Ethernet DMA Channel Interrupt Enable Register */

+#define ETH_DMACIER_NIE_Pos                           (15U)

+#define ETH_DMACIER_NIE_Msk                           (0x1UL << ETH_DMACIER_NIE_Pos) /*!< 0x00008000 */

+#define ETH_DMACIER_NIE                               ETH_DMACIER_NIE_Msk      /* Normal Interrupt Summary Enable */

+#define ETH_DMACIER_AIE_Pos                           (14U)

+#define ETH_DMACIER_AIE_Msk                           (0x1UL << ETH_DMACIER_AIE_Pos) /*!< 0x00004000 */

+#define ETH_DMACIER_AIE                               ETH_DMACIER_AIE_Msk      /* Abnormal Interrupt Summary Enable */

+#define ETH_DMACIER_CDEE_Pos                          (13U)

+#define ETH_DMACIER_CDEE_Msk                          (0x1UL << ETH_DMACIER_CDEE_Pos) /*!< 0x00002000 */

+#define ETH_DMACIER_CDEE                              ETH_DMACIER_CDEE_Msk     /* Context Descriptor Error Enable */

+#define ETH_DMACIER_FBEE_Pos                          (12U)

+#define ETH_DMACIER_FBEE_Msk                          (0x1UL << ETH_DMACIER_FBEE_Pos) /*!< 0x00001000 */

+#define ETH_DMACIER_FBEE                              ETH_DMACIER_FBEE_Msk     /* Fatal Bus Error Enable */

+#define ETH_DMACIER_ERIE_Pos                          (11U)

+#define ETH_DMACIER_ERIE_Msk                          (0x1UL << ETH_DMACIER_ERIE_Pos) /*!< 0x00000800 */

+#define ETH_DMACIER_ERIE                              ETH_DMACIER_ERIE_Msk     /* Early Receive Interrupt Enable */

+#define ETH_DMACIER_ETIE_Pos                          (10U)

+#define ETH_DMACIER_ETIE_Msk                          (0x1UL << ETH_DMACIER_ETIE_Pos) /*!< 0x00000400 */

+#define ETH_DMACIER_ETIE                              ETH_DMACIER_ETIE_Msk     /* Early Transmit Interrupt Enable */

+#define ETH_DMACIER_RWTE_Pos                          (9U)

+#define ETH_DMACIER_RWTE_Msk                          (0x1UL << ETH_DMACIER_RWTE_Pos) /*!< 0x00000200 */

+#define ETH_DMACIER_RWTE                              ETH_DMACIER_RWTE_Msk     /* Receive Watchdog Timeout Enable */

+#define ETH_DMACIER_RSE_Pos                           (8U)

+#define ETH_DMACIER_RSE_Msk                           (0x1UL << ETH_DMACIER_RSE_Pos) /*!< 0x00000100 */

+#define ETH_DMACIER_RSE                               ETH_DMACIER_RSE_Msk      /* Receive Stopped Enable */

+#define ETH_DMACIER_RBUE_Pos                          (7U)

+#define ETH_DMACIER_RBUE_Msk                          (0x1UL << ETH_DMACIER_RBUE_Pos) /*!< 0x00000080 */

+#define ETH_DMACIER_RBUE                              ETH_DMACIER_RBUE_Msk     /* Receive Buffer Unavailable Enable */

+#define ETH_DMACIER_RIE_Pos                           (6U)

+#define ETH_DMACIER_RIE_Msk                           (0x1UL << ETH_DMACIER_RIE_Pos) /*!< 0x00000040 */

+#define ETH_DMACIER_RIE                               ETH_DMACIER_RIE_Msk      /* Receive Interrupt Enable */

+#define ETH_DMACIER_TBUE_Pos                          (2U)

+#define ETH_DMACIER_TBUE_Msk                          (0x1UL << ETH_DMACIER_TBUE_Pos) /*!< 0x00000004 */

+#define ETH_DMACIER_TBUE                              ETH_DMACIER_TBUE_Msk     /* Transmit Buffer Unavailable Enable */

+#define ETH_DMACIER_TXSE_Pos                          (1U)

+#define ETH_DMACIER_TXSE_Msk                          (0x1UL << ETH_DMACIER_TXSE_Pos) /*!< 0x00000002 */

+#define ETH_DMACIER_TXSE                              ETH_DMACIER_TXSE_Msk     /* Transmit Stopped Enable */

+#define ETH_DMACIER_TIE_Pos                           (0U)

+#define ETH_DMACIER_TIE_Msk                           (0x1UL << ETH_DMACIER_TIE_Pos) /*!< 0x00000001 */

+#define ETH_DMACIER_TIE                               ETH_DMACIER_TIE_Msk      /* Transmit Interrupt Enable */

+

+/* Bit definition for Ethernet DMA Channel Rx Interrupt Watchdog Timer Register */

+#define ETH_DMACRIWTR_RWT_Pos                         (0U)

+#define ETH_DMACRIWTR_RWT_Msk                         (0xFFUL << ETH_DMACRIWTR_RWT_Pos) /*!< 0x000000FF */

+#define ETH_DMACRIWTR_RWT                             ETH_DMACRIWTR_RWT_Msk    /* Receive Interrupt Watchdog Timer Count */

+

+/* Bit definition for Ethernet DMA Channel Current App Tx Desc Register */

+#define ETH_DMACCATDR_CURTDESAPTR_Pos                 (0U)

+#define ETH_DMACCATDR_CURTDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCATDR_CURTDESAPTR                     ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Current App Rx Desc Register */

+#define ETH_DMACCARDR_CURRDESAPTR_Pos                 (0U)

+#define ETH_DMACCARDR_CURRDESAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCARDR_CURRDESAPTR                     ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Current App Tx Buffer Register */

+#define ETH_DMACCATBR_CURTBUFAPTR_Pos                 (0U)

+#define ETH_DMACCATBR_CURTBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCATBR_CURTBUFAPTR                     ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Current App Rx Buffer Register */

+#define ETH_DMACCARBR_CURRBUFAPTR_Pos                 (0U)

+#define ETH_DMACCARBR_CURRBUFAPTR_Msk                 (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */

+#define ETH_DMACCARBR_CURRBUFAPTR                     ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */

+

+/* Bit definition for Ethernet DMA Channel Status Register */

+#define ETH_DMACSR_REB_Pos                            (19U)

+#define ETH_DMACSR_REB_Msk                            (0x7UL << ETH_DMACSR_REB_Pos) /*!< 0x00380000 */

+#define ETH_DMACSR_REB                                ETH_DMACSR_REB_Msk       /* Rx DMA Error Bits */

+#define ETH_DMACSR_TEB_Pos                            (16U)

+#define ETH_DMACSR_TEB_Msk                            (0x7UL << ETH_DMACSR_TEB_Pos) /*!< 0x00070000 */

+#define ETH_DMACSR_TEB                                ETH_DMACSR_TEB_Msk       /* Tx DMA Error Bits */

+#define ETH_DMACSR_NIS_Pos                            (15U)

+#define ETH_DMACSR_NIS_Msk                            (0x1UL << ETH_DMACSR_NIS_Pos) /*!< 0x00008000 */

+#define ETH_DMACSR_NIS                                ETH_DMACSR_NIS_Msk       /* Normal Interrupt Summary */

+#define ETH_DMACSR_AIS_Pos                            (14U)

+#define ETH_DMACSR_AIS_Msk                            (0x1UL << ETH_DMACSR_AIS_Pos) /*!< 0x00004000 */

+#define ETH_DMACSR_AIS                                ETH_DMACSR_AIS_Msk       /* Abnormal Interrupt Summary */

+#define ETH_DMACSR_CDE_Pos                            (13U)

+#define ETH_DMACSR_CDE_Msk                            (0x1UL << ETH_DMACSR_CDE_Pos) /*!< 0x00002000 */

+#define ETH_DMACSR_CDE                                ETH_DMACSR_CDE_Msk       /* Context Descriptor Error */

+#define ETH_DMACSR_FBE_Pos                            (12U)

+#define ETH_DMACSR_FBE_Msk                            (0x1UL << ETH_DMACSR_FBE_Pos) /*!< 0x00001000 */

+#define ETH_DMACSR_FBE                                ETH_DMACSR_FBE_Msk       /* Fatal Bus Error */

+#define ETH_DMACSR_ERI_Pos                            (11U)

+#define ETH_DMACSR_ERI_Msk                            (0x1UL << ETH_DMACSR_ERI_Pos) /*!< 0x00000800 */

+#define ETH_DMACSR_ERI                                ETH_DMACSR_ERI_Msk       /* Early Receive Interrupt */

+#define ETH_DMACSR_ETI_Pos                            (10U)

+#define ETH_DMACSR_ETI_Msk                            (0x1UL << ETH_DMACSR_ETI_Pos) /*!< 0x00000400 */

+#define ETH_DMACSR_ETI                                ETH_DMACSR_ETI_Msk       /* Early Transmit Interrupt */

+#define ETH_DMACSR_RWT_Pos                            (9U)

+#define ETH_DMACSR_RWT_Msk                            (0x1UL << ETH_DMACSR_RWT_Pos) /*!< 0x00000200 */

+#define ETH_DMACSR_RWT                                ETH_DMACSR_RWT_Msk       /* Receive Watchdog Timeout */

+#define ETH_DMACSR_RPS_Pos                            (8U)

+#define ETH_DMACSR_RPS_Msk                            (0x1UL << ETH_DMACSR_RPS_Pos) /*!< 0x00000100 */

+#define ETH_DMACSR_RPS                                ETH_DMACSR_RPS_Msk       /* Receive Process Stopped */

+#define ETH_DMACSR_RBU_Pos                            (7U)

+#define ETH_DMACSR_RBU_Msk                            (0x1UL << ETH_DMACSR_RBU_Pos) /*!< 0x00000080 */

+#define ETH_DMACSR_RBU                                ETH_DMACSR_RBU_Msk       /* Receive Buffer Unavailable */

+#define ETH_DMACSR_RI_Pos                             (6U)

+#define ETH_DMACSR_RI_Msk                             (0x1UL << ETH_DMACSR_RI_Pos) /*!< 0x00000040 */

+#define ETH_DMACSR_RI                                 ETH_DMACSR_RI_Msk        /* Receive Interrupt */

+#define ETH_DMACSR_TBU_Pos                            (2U)

+#define ETH_DMACSR_TBU_Msk                            (0x1UL << ETH_DMACSR_TBU_Pos) /*!< 0x00000004 */

+#define ETH_DMACSR_TBU                                ETH_DMACSR_TBU_Msk       /* Transmit Buffer Unavailable */

+#define ETH_DMACSR_TPS_Pos                            (1U)

+#define ETH_DMACSR_TPS_Msk                            (0x1UL << ETH_DMACSR_TPS_Pos) /*!< 0x00000002 */

+#define ETH_DMACSR_TPS                                ETH_DMACSR_TPS_Msk       /* Transmit Process Stopped */

+#define ETH_DMACSR_TI_Pos                             (0U)

+#define ETH_DMACSR_TI_Msk                             (0x1UL << ETH_DMACSR_TI_Pos) /*!< 0x00000001 */

+#define ETH_DMACSR_TI                                 ETH_DMACSR_TI_Msk        /* Transmit Interrupt */

+

+/* Bit definition for Ethernet DMA Channel missed frame count register */

+#define ETH_DMACMFCR_MFCO_Pos                         (15U)

+#define ETH_DMACMFCR_MFCO_Msk                         (0x1UL << ETH_DMACMFCR_MFCO_Pos) /*!< 0x00008000 */

+#define ETH_DMACMFCR_MFCO                             ETH_DMACMFCR_MFCO_Msk    /* Overflow status of the MFC Counter */

+#define ETH_DMACMFCR_MFC_Pos                          (0U)

+#define ETH_DMACMFCR_MFC_Msk                          (0x7FFUL << ETH_DMACMFCR_MFC_Pos) /*!< 0x000007FF */

+#define ETH_DMACMFCR_MFC                              ETH_DMACMFCR_MFC_Msk     /* The number of packet counters dropped by the DMA */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             DMA Controller                                 */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DMA_SxCR register  *****************/

+#define DMA_SxCR_MBURST_Pos      (23U)

+#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                /*!< 0x01800000 */

+#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk                           /*!< Memory burst transfer configuration */

+#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */

+#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */

+#define DMA_SxCR_PBURST_Pos      (21U)

+#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                /*!< 0x00600000 */

+#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk                           /*!< Peripheral burst transfer configuration */

+#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */

+#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */

+#define DMA_SxCR_TRBUFF_Pos      (20U)

+#define DMA_SxCR_TRBUFF_Msk      (0x1UL << DMA_SxCR_TRBUFF_Pos)                 /*!< 0x00100000 */

+#define DMA_SxCR_TRBUFF          DMA_SxCR_TRBUFF_Msk                            /*!< bufferable transfers enabled/disable */

+#define DMA_SxCR_CT_Pos          (19U)

+#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                    /*!< 0x00080000 */

+#define DMA_SxCR_CT              DMA_SxCR_CT_Msk                               /*!< Current target (only in double buffer mode) */

+#define DMA_SxCR_DBM_Pos         (18U)

+#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                   /*!< 0x00040000 */

+#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk                              /*!< Double buffer mode */

+#define DMA_SxCR_PL_Pos          (16U)

+#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                    /*!< 0x00030000 */

+#define DMA_SxCR_PL              DMA_SxCR_PL_Msk                               /*!< Priority level */

+#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */

+#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */

+#define DMA_SxCR_PINCOS_Pos      (15U)

+#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                /*!< 0x00008000 */

+#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk                           /*!< Peripheral increment offset size */

+#define DMA_SxCR_MSIZE_Pos       (13U)

+#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                 /*!< 0x00006000 */

+#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk                            /*!< Memory data size */

+#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */

+#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */

+#define DMA_SxCR_PSIZE_Pos       (11U)

+#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                 /*!< 0x00001800 */

+#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk                            /*< Peripheral data size */

+#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */

+#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */

+#define DMA_SxCR_MINC_Pos        (10U)

+#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                  /*!< 0x00000400 */

+#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk                             /*!< Memory increment mode */

+#define DMA_SxCR_PINC_Pos        (9U)

+#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                  /*!< 0x00000200 */

+#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk                             /*!< Peripheral increment mode */

+#define DMA_SxCR_CIRC_Pos        (8U)

+#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                  /*!< 0x00000100 */

+#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk                             /*!< Circular mode */

+#define DMA_SxCR_DIR_Pos         (6U)

+#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                   /*!< 0x000000C0 */

+#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk                              /*!< Data transfer direction */

+#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */

+#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */

+#define DMA_SxCR_PFCTRL_Pos      (5U)

+#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                /*!< 0x00000020 */

+#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk                           /*!< Peripheral flow controller */

+#define DMA_SxCR_TCIE_Pos        (4U)

+#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                  /*!< 0x00000010 */

+#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk                             /*!< Transfer complete interrupt enable */

+#define DMA_SxCR_HTIE_Pos        (3U)

+#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                  /*!< 0x00000008 */

+#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk                             /*!< Half transfer interrupt enable */

+#define DMA_SxCR_TEIE_Pos        (2U)

+#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                  /*!< 0x00000004 */

+#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk                             /*!< Transfer error interrupt enable */

+#define DMA_SxCR_DMEIE_Pos       (1U)

+#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                 /*!< 0x00000002 */

+#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk                            /*!< Direct mode error interrupt enable */

+#define DMA_SxCR_EN_Pos          (0U)

+#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                    /*!< 0x00000001 */

+#define DMA_SxCR_EN              DMA_SxCR_EN_Msk                               /*!< Stream enable / flag stream ready when read low */

+

+/********************  Bits definition for DMA_SxCNDTR register  **************/

+#define DMA_SxNDT_Pos            (0U)

+#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                   /*!< 0x0000FFFF */

+#define DMA_SxNDT                DMA_SxNDT_Msk                                 /*!< Number of data items to transfer */

+#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */

+#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */

+#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */

+#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */

+#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */

+#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */

+#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */

+#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */

+#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */

+#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */

+#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */

+#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */

+#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */

+#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */

+#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */

+#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */

+

+/********************  Bits definition for DMA_SxFCR register  ****************/

+#define DMA_SxFCR_FEIE_Pos       (7U)

+#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                 /*!< 0x00000080 */

+#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk                            /*!< FIFO error interrupt enable */

+#define DMA_SxFCR_FS_Pos         (3U)

+#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                   /*!< 0x00000038 */

+#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk                              /*!< FIFO status */

+#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */

+#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */

+#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */

+#define DMA_SxFCR_DMDIS_Pos      (2U)

+#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                /*!< 0x00000004 */

+#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk                           /*!< Direct mode disable */

+#define DMA_SxFCR_FTH_Pos        (0U)

+#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                  /*!< 0x00000003 */

+#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk                             /*!< FIFO threshold selection */

+#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */

+#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */

+

+/********************  Bits definition for DMA_LISR register  *****************/

+#define DMA_LISR_TCIF3_Pos       (27U)

+#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                 /*!< 0x08000000 */

+#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk                            /*!<  Stream 3 transfer complete interrupt flag */

+#define DMA_LISR_HTIF3_Pos       (26U)

+#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                 /*!< 0x04000000 */

+#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk                            /*!<  Stream 3 half transfer interrupt flag */

+#define DMA_LISR_TEIF3_Pos       (25U)

+#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                 /*!< 0x02000000 */

+#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk                            /*!<  Stream 3 transfer error interrupt flag */

+#define DMA_LISR_DMEIF3_Pos      (24U)

+#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                /*!< 0x01000000 */

+#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk                           /*!<  Stream 3 direct mode error interrupt flag */

+#define DMA_LISR_FEIF3_Pos       (22U)

+#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                 /*!< 0x00400000 */

+#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk                            /*!<  Stream 3 FIFO error interrupt flag */

+#define DMA_LISR_TCIF2_Pos       (21U)

+#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                 /*!< 0x00200000 */

+#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk                            /*!<  Stream 2 transfer complete interrupt flag */

+#define DMA_LISR_HTIF2_Pos       (20U)

+#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                 /*!< 0x00100000 */

+#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk                            /*!<  Stream 2 half transfer interrupt flag */

+#define DMA_LISR_TEIF2_Pos       (19U)

+#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                 /*!< 0x00080000 */

+#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk                            /*!<  Stream 2 transfer error interrupt flag */

+#define DMA_LISR_DMEIF2_Pos      (18U)

+#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                /*!< 0x00040000 */

+#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk                           /*!<  Stream 2 direct mode error interrupt flag */

+#define DMA_LISR_FEIF2_Pos       (16U)

+#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                 /*!< 0x00010000 */

+#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk                            /*!<  Stream 2 FIFO error interrupt flag */

+#define DMA_LISR_TCIF1_Pos       (11U)

+#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                 /*!< 0x00000800 */

+#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk                            /*!<  Stream 1 transfer complete interrupt flag */

+#define DMA_LISR_HTIF1_Pos       (10U)

+#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                 /*!< 0x00000400 */

+#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk                            /*!<  Stream 1 half transfer interrupt flag */

+#define DMA_LISR_TEIF1_Pos       (9U)

+#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                 /*!< 0x00000200 */

+#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk                            /*!<  Stream 1 transfer error interrupt flag */

+#define DMA_LISR_DMEIF1_Pos      (8U)

+#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                /*!< 0x00000100 */

+#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk                           /*!<  Stream 1 direct mode error interrupt flag */

+#define DMA_LISR_FEIF1_Pos       (6U)

+#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                 /*!< 0x00000040 */

+#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk                            /*!<  Stream 1 FIFO error interrupt flag */

+#define DMA_LISR_TCIF0_Pos       (5U)

+#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                 /*!< 0x00000020 */

+#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk                            /*!<  Stream 0 transfer complete interrupt flag */

+#define DMA_LISR_HTIF0_Pos       (4U)

+#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                 /*!< 0x00000010 */

+#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk                            /*!<  Stream 0 half transfer interrupt flag */

+#define DMA_LISR_TEIF0_Pos       (3U)

+#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                 /*!< 0x00000008 */

+#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk                            /*!<  Stream 0 transfer error interrupt flag */

+#define DMA_LISR_DMEIF0_Pos      (2U)

+#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                /*!< 0x00000004 */

+#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk                           /*!<  Stream 0 direct mode error interrupt flag */

+#define DMA_LISR_FEIF0_Pos       (0U)

+#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                 /*!< 0x00000001 */

+#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk                            /*!<  Stream 0 FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_HISR register  *****************/

+#define DMA_HISR_TCIF7_Pos       (27U)

+#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                 /*!< 0x08000000 */

+#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk                            /*!<  Stream 7 transfer complete interrupt flag */

+#define DMA_HISR_HTIF7_Pos       (26U)

+#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                 /*!< 0x04000000 */

+#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk                            /*!<  Stream 7 half transfer interrupt flag */

+#define DMA_HISR_TEIF7_Pos       (25U)

+#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                 /*!< 0x02000000 */

+#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk                            /*!<  Stream 7 transfer error interrupt flag */

+#define DMA_HISR_DMEIF7_Pos      (24U)

+#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                /*!< 0x01000000 */

+#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk                           /*!<  Stream 7 direct mode error interrupt flag */

+#define DMA_HISR_FEIF7_Pos       (22U)

+#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                 /*!< 0x00400000 */

+#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk                            /*!<  Stream 7 FIFO error interrupt flag */

+#define DMA_HISR_TCIF6_Pos       (21U)

+#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                 /*!< 0x00200000 */

+#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk                            /*!<  Stream 6 transfer complete interrupt flag */

+#define DMA_HISR_HTIF6_Pos       (20U)

+#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                 /*!< 0x00100000 */

+#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk                            /*!<  Stream 6 half transfer interrupt flag */

+#define DMA_HISR_TEIF6_Pos       (19U)

+#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                 /*!< 0x00080000 */

+#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk                            /*!<  Stream 6 transfer error interrupt flag */

+#define DMA_HISR_DMEIF6_Pos      (18U)

+#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                /*!< 0x00040000 */

+#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk                           /*!<  Stream 6 direct mode error interrupt flag */

+#define DMA_HISR_FEIF6_Pos       (16U)

+#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                 /*!< 0x00010000 */

+#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk                            /*!<  Stream 6 FIFO error interrupt flag */

+#define DMA_HISR_TCIF5_Pos       (11U)

+#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                 /*!< 0x00000800 */

+#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk                            /*!<  Stream 5 transfer complete interrupt flag */

+#define DMA_HISR_HTIF5_Pos       (10U)

+#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                 /*!< 0x00000400 */

+#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk                            /*!<  Stream 5 half transfer interrupt flag */

+#define DMA_HISR_TEIF5_Pos       (9U)

+#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                 /*!< 0x00000200 */

+#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk                            /*!<  Stream 5 transfer error interrupt flag */

+#define DMA_HISR_DMEIF5_Pos      (8U)

+#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                /*!< 0x00000100 */

+#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk                           /*!<  Stream 5 direct mode error interrupt flag */

+#define DMA_HISR_FEIF5_Pos       (6U)

+#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                 /*!< 0x00000040 */

+#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk                            /*!<  Stream 5 FIFO error interrupt flag */

+#define DMA_HISR_TCIF4_Pos       (5U)

+#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                 /*!< 0x00000020 */

+#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk                            /*!<  Stream 4 transfer complete interrupt flag */

+#define DMA_HISR_HTIF4_Pos       (4U)

+#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                 /*!< 0x00000010 */

+#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk                            /*!<  Stream 4 half transfer interrupt flag */

+#define DMA_HISR_TEIF4_Pos       (3U)

+#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                 /*!< 0x00000008 */

+#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk                            /*!<  Stream 4 transfer error interrupt flag */

+#define DMA_HISR_DMEIF4_Pos      (2U)

+#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                /*!< 0x00000004 */

+#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk                           /*!<  Stream 4 direct mode error interrupt flag */

+#define DMA_HISR_FEIF4_Pos       (0U)

+#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                 /*!< 0x00000001 */

+#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk                            /*!<  Stream 4 FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_LIFCR register  ****************/

+#define DMA_LIFCR_CTCIF3_Pos     (27U)

+#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)               /*!< 0x08000000 */

+#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk                          /*!<  Stream 3 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF3_Pos     (26U)

+#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)               /*!< 0x04000000 */

+#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk                          /*!<  Stream 3 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF3_Pos     (25U)

+#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)               /*!< 0x02000000 */

+#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk                          /*!<  Stream 3 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF3_Pos    (24U)

+#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)              /*!< 0x01000000 */

+#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk                         /*!<  Stream 3 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF3_Pos     (22U)

+#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)               /*!< 0x00400000 */

+#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk                          /*!<  Stream 3 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF2_Pos     (21U)

+#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)               /*!< 0x00200000 */

+#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk                          /*!<  Stream 2 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF2_Pos     (20U)

+#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)               /*!< 0x00100000 */

+#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk                          /*!<  Stream 2 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF2_Pos     (19U)

+#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)               /*!< 0x00080000 */

+#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk                          /*!<  Stream 2 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF2_Pos    (18U)

+#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)              /*!< 0x00040000 */

+#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk                         /*!<  Stream 2 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF2_Pos     (16U)

+#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)               /*!< 0x00010000 */

+#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk                          /*!<  Stream 2 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF1_Pos     (11U)

+#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)               /*!< 0x00000800 */

+#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk                          /*!<  Stream 1 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF1_Pos     (10U)

+#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)               /*!< 0x00000400 */

+#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk                          /*!<  Stream 1 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF1_Pos     (9U)

+#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)               /*!< 0x00000200 */

+#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk                          /*!<  Stream 1 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF1_Pos    (8U)

+#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)              /*!< 0x00000100 */

+#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk                         /*!<  Stream 1 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF1_Pos     (6U)

+#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)               /*!< 0x00000040 */

+#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk                          /*!<  Stream 1 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF0_Pos     (5U)

+#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)               /*!< 0x00000020 */

+#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk                          /*!<  Stream 0 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF0_Pos     (4U)

+#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)               /*!< 0x00000010 */

+#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk                          /*!<  Stream 0 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF0_Pos     (3U)

+#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)               /*!< 0x00000008 */

+#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk                          /*!<  Stream 0 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF0_Pos    (2U)

+#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)              /*!< 0x00000004 */

+#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk                         /*!<  Stream 0 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF0_Pos     (0U)

+#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)               /*!< 0x00000001 */

+#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk                          /*!<  Stream 0 clear FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_HIFCR  register  ****************/

+#define DMA_HIFCR_CTCIF7_Pos     (27U)

+#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)               /*!< 0x08000000 */

+#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk                          /*!<  Stream 7 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF7_Pos     (26U)

+#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)               /*!< 0x04000000 */

+#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk                          /*!<  Stream 7 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF7_Pos     (25U)

+#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)               /*!< 0x02000000 */

+#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk                          /*!<  Stream 7 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF7_Pos    (24U)

+#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)              /*!< 0x01000000 */

+#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk                         /*!<  Stream 7 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF7_Pos     (22U)

+#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)               /*!< 0x00400000 */

+#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk                          /*!<  Stream 7 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF6_Pos     (21U)

+#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)               /*!< 0x00200000 */

+#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk                          /*!<  Stream 6 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF6_Pos     (20U)

+#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)               /*!< 0x00100000 */

+#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk                          /*!<  Stream 6 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF6_Pos     (19U)

+#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)               /*!< 0x00080000 */

+#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk                          /*!<  Stream 6 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF6_Pos    (18U)

+#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)              /*!< 0x00040000 */

+#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk                         /*!<  Stream 6 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF6_Pos     (16U)

+#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)               /*!< 0x00010000 */

+#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk                          /*!<  Stream 6 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF5_Pos     (11U)

+#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)               /*!< 0x00000800 */

+#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk                          /*!<  Stream 5 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF5_Pos     (10U)

+#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)               /*!< 0x00000400 */

+#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk                          /*!<  Stream 5 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF5_Pos     (9U)

+#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)               /*!< 0x00000200 */

+#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk                          /*!<  Stream 5 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF5_Pos    (8U)

+#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)              /*!< 0x00000100 */

+#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk                         /*!<  Stream 5 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF5_Pos     (6U)

+#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)               /*!< 0x00000040 */

+#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk                          /*!<  Stream 5 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF4_Pos     (5U)

+#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)               /*!< 0x00000020 */

+#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk                          /*!<  Stream 4 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF4_Pos     (4U)

+#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)               /*!< 0x00000010 */

+#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk                          /*!<  Stream 4 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF4_Pos     (3U)

+#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)               /*!< 0x00000008 */

+#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk                          /*!<  Stream 4 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF4_Pos    (2U)

+#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)              /*!< 0x00000004 */

+#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk                         /*!<  Stream 4 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF4_Pos     (0U)

+#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)               /*!< 0x00000001 */

+#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk                          /*!<  Stream 4 clear FIFO error interrupt flag */

+

+/******************  Bit definition for DMA_SxPAR register  ********************/

+#define DMA_SxPAR_PA_Pos         (0U)

+#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)            /*!< 0xFFFFFFFF */

+#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */

+

+/******************  Bit definition for DMA_SxM0AR register  ********************/

+#define DMA_SxM0AR_M0A_Pos       (0U)

+#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)          /*!< 0xFFFFFFFF */

+#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory 0 Address */

+

+/******************  Bit definition for DMA_SxM1AR register  ********************/

+#define DMA_SxM1AR_M1A_Pos       (0U)

+#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)          /*!< 0xFFFFFFFF */

+#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory 1 Address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             DMAMUX Controller                              */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DMAMUX_CxCR register  **************/

+#define DMAMUX_CxCR_DMAREQ_ID_Pos      (0U)

+#define DMAMUX_CxCR_DMAREQ_ID_Msk      (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)   /*!< 0x000000FF */

+#define DMAMUX_CxCR_DMAREQ_ID          DMAMUX_CxCR_DMAREQ_ID_Msk               /*!<  DMA request identification */

+#define DMAMUX_CxCR_DMAREQ_ID_0        (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000001 */

+#define DMAMUX_CxCR_DMAREQ_ID_1        (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000002 */

+#define DMAMUX_CxCR_DMAREQ_ID_2        (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000004 */

+#define DMAMUX_CxCR_DMAREQ_ID_3        (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000008 */

+#define DMAMUX_CxCR_DMAREQ_ID_4        (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000010 */

+#define DMAMUX_CxCR_DMAREQ_ID_5        (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000020 */

+#define DMAMUX_CxCR_DMAREQ_ID_6        (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000040 */

+#define DMAMUX_CxCR_DMAREQ_ID_7        (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000080 */

+#define DMAMUX_CxCR_SOIE_Pos           (8U)

+#define DMAMUX_CxCR_SOIE_Msk           (0x1UL << DMAMUX_CxCR_SOIE_Pos)         /*!< 0x00000100 */

+#define DMAMUX_CxCR_SOIE               DMAMUX_CxCR_SOIE_Msk                    /*!<  Synchronization overrun interrupt enable */

+#define DMAMUX_CxCR_EGE_Pos            (9U)

+#define DMAMUX_CxCR_EGE_Msk            (0x1UL << DMAMUX_CxCR_EGE_Pos)          /*!< 0x00000200 */

+#define DMAMUX_CxCR_EGE                DMAMUX_CxCR_EGE_Msk                     /*!<  Event generation enable */

+#define DMAMUX_CxCR_SE_Pos             (16U)

+#define DMAMUX_CxCR_SE_Msk             (0x1UL << DMAMUX_CxCR_SE_Pos)           /*!< 0x00010000 */

+#define DMAMUX_CxCR_SE                 DMAMUX_CxCR_SE_Msk                      /*!<  Synchronization enable */

+#define DMAMUX_CxCR_SPOL_Pos           (17U)

+#define DMAMUX_CxCR_SPOL_Msk           (0x3UL << DMAMUX_CxCR_SPOL_Pos)         /*!< 0x00060000 */

+#define DMAMUX_CxCR_SPOL               DMAMUX_CxCR_SPOL_Msk                    /*!<  Synchronization polarity */

+#define DMAMUX_CxCR_SPOL_0             (0x1UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00020000 */

+#define DMAMUX_CxCR_SPOL_1             (0x2UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00040000 */

+#define DMAMUX_CxCR_NBREQ_Pos          (19U)

+#define DMAMUX_CxCR_NBREQ_Msk          (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)       /*!< 0x00F80000 */

+#define DMAMUX_CxCR_NBREQ              DMAMUX_CxCR_NBREQ_Msk                   /*!<  Number of DMA requests minus 1 to forward */

+#define DMAMUX_CxCR_NBREQ_0            (0x01UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00080000 */

+#define DMAMUX_CxCR_NBREQ_1            (0x02UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00100000 */

+#define DMAMUX_CxCR_NBREQ_2            (0x04UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00200000 */

+#define DMAMUX_CxCR_NBREQ_3            (0x08UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00400000 */

+#define DMAMUX_CxCR_NBREQ_4            (0x10UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00800000 */

+#define DMAMUX_CxCR_SYNC_ID_Pos        (24U)

+#define DMAMUX_CxCR_SYNC_ID_Msk        (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)     /*!< 0x1F000000 */

+#define DMAMUX_CxCR_SYNC_ID            DMAMUX_CxCR_SYNC_ID_Msk                 /*!<  Synchronization identification */

+#define DMAMUX_CxCR_SYNC_ID_0          (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x01000000 */

+#define DMAMUX_CxCR_SYNC_ID_1          (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x02000000 */

+#define DMAMUX_CxCR_SYNC_ID_2          (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x04000000 */

+#define DMAMUX_CxCR_SYNC_ID_3          (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x08000000 */

+#define DMAMUX_CxCR_SYNC_ID_4          (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x10000000 */

+

+/********************  Bits definition for DMAMUX_CSR register  **************/

+#define DMAMUX_CSR_SOF0_Pos            (0U)

+#define DMAMUX_CSR_SOF0_Msk            (0x1UL << DMAMUX_CSR_SOF0_Pos)          /*!< 0x00000001 */

+#define DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0_Msk                     /*!< Channel 0 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF1_Pos            (1U)

+#define DMAMUX_CSR_SOF1_Msk            (0x1UL << DMAMUX_CSR_SOF1_Pos)          /*!< 0x00000002 */

+#define DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1_Msk                     /*!< Channel 1 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF2_Pos            (2U)

+#define DMAMUX_CSR_SOF2_Msk            (0x1UL << DMAMUX_CSR_SOF2_Pos)          /*!< 0x00000004 */

+#define DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2_Msk                     /*!< Channel 2 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF3_Pos            (3U)

+#define DMAMUX_CSR_SOF3_Msk            (0x1UL << DMAMUX_CSR_SOF3_Pos)          /*!< 0x00000008 */

+#define DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3_Msk                     /*!< Channel 3 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF4_Pos            (4U)

+#define DMAMUX_CSR_SOF4_Msk            (0x1UL << DMAMUX_CSR_SOF4_Pos)          /*!< 0x00000010 */

+#define DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4_Msk                     /*!< Channel 4 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF5_Pos            (5U)

+#define DMAMUX_CSR_SOF5_Msk            (0x1UL << DMAMUX_CSR_SOF5_Pos)          /*!< 0x00000020 */

+#define DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5_Msk                     /*!< Channel 5 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF6_Pos            (6U)

+#define DMAMUX_CSR_SOF6_Msk            (0x1UL << DMAMUX_CSR_SOF6_Pos)          /*!< 0x00000040 */

+#define DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6_Msk                     /*!< Channel 6 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF7_Pos            (7U)

+#define DMAMUX_CSR_SOF7_Msk            (0x1UL << DMAMUX_CSR_SOF7_Pos)          /*!< 0x00000080 */

+#define DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7_Msk                     /*!< Channel 7 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF8_Pos            (8U)

+#define DMAMUX_CSR_SOF8_Msk            (0x1UL << DMAMUX_CSR_SOF8_Pos)          /*!< 0x00000100 */

+#define DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8_Msk                     /*!< Channel 8 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF9_Pos            (9U)

+#define DMAMUX_CSR_SOF9_Msk            (0x1UL << DMAMUX_CSR_SOF9_Pos)          /*!< 0x00000200 */

+#define DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9_Msk                     /*!< Channel 9 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF10_Pos           (10U)

+#define DMAMUX_CSR_SOF10_Msk           (0x1UL << DMAMUX_CSR_SOF10_Pos)         /*!< 0x00000400 */

+#define DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10_Msk                    /*!< Channel 10 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF11_Pos           (11U)

+#define DMAMUX_CSR_SOF11_Msk           (0x1UL << DMAMUX_CSR_SOF11_Pos)         /*!< 0x00000800 */

+#define DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11_Msk                    /*!< Channel 11 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF12_Pos           (12U)

+#define DMAMUX_CSR_SOF12_Msk           (0x1UL << DMAMUX_CSR_SOF12_Pos)         /*!< 0x00001000 */

+#define DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12_Msk                    /*!< Channel 12 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF13_Pos           (13U)

+#define DMAMUX_CSR_SOF13_Msk           (0x1UL << DMAMUX_CSR_SOF13_Pos)         /*!< 0x00002000 */

+#define DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13_Msk                    /*!< Channel 13 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF14_Pos           (14U)

+#define DMAMUX_CSR_SOF14_Msk           (0x1UL << DMAMUX_CSR_SOF14_Pos)         /*!< 0x00004000 */

+#define DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14_Msk                    /*!< Channel 14 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF15_Pos           (15U)

+#define DMAMUX_CSR_SOF15_Msk           (0x1UL << DMAMUX_CSR_SOF15_Pos)         /*!< 0x00008000 */

+#define DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15_Msk                    /*!< Channel 15 Synchronization overrun event flag */

+

+/********************  Bits definition for DMAMUX_CFR register  **************/

+#define DMAMUX_CFR_CSOF0_Pos           (0U)

+#define DMAMUX_CFR_CSOF0_Msk           (0x1UL << DMAMUX_CFR_CSOF0_Pos)         /*!< 0x00000001 */

+#define DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0_Msk                    /*!< Channel 0 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF1_Pos           (1U)

+#define DMAMUX_CFR_CSOF1_Msk           (0x1UL << DMAMUX_CFR_CSOF1_Pos)         /*!< 0x00000002 */

+#define DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1_Msk                    /*!< Channel 1 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF2_Pos           (2U)

+#define DMAMUX_CFR_CSOF2_Msk           (0x1UL << DMAMUX_CFR_CSOF2_Pos)         /*!< 0x00000004 */

+#define DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2_Msk                    /*!< Channel 2 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF3_Pos           (3U)

+#define DMAMUX_CFR_CSOF3_Msk           (0x1UL << DMAMUX_CFR_CSOF3_Pos)         /*!< 0x00000008 */

+#define DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3_Msk                    /*!< Channel 3 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF4_Pos           (4U)

+#define DMAMUX_CFR_CSOF4_Msk           (0x1UL << DMAMUX_CFR_CSOF4_Pos)         /*!< 0x00000010 */

+#define DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4_Msk                    /*!< Channel 4 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF5_Pos           (5U)

+#define DMAMUX_CFR_CSOF5_Msk           (0x1UL << DMAMUX_CFR_CSOF5_Pos)         /*!< 0x00000020 */

+#define DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5_Msk                    /*!< Channel 5 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF6_Pos           (6U)

+#define DMAMUX_CFR_CSOF6_Msk           (0x1UL << DMAMUX_CFR_CSOF6_Pos)         /*!< 0x00000040 */

+#define DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6_Msk                    /*!< Channel 6 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF7_Pos           (7U)

+#define DMAMUX_CFR_CSOF7_Msk           (0x1UL << DMAMUX_CFR_CSOF7_Pos)         /*!< 0x00000080 */

+#define DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7_Msk                    /*!< Channel 7 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF8_Pos           (8U)

+#define DMAMUX_CFR_CSOF8_Msk           (0x1UL << DMAMUX_CFR_CSOF8_Pos)         /*!< 0x00000100 */

+#define DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8_Msk                    /*!< Channel 8 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF9_Pos           (9U)

+#define DMAMUX_CFR_CSOF9_Msk           (0x1UL << DMAMUX_CFR_CSOF9_Pos)         /*!< 0x00000200 */

+#define DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9_Msk                    /*!< Channel 9 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF10_Pos          (10U)

+#define DMAMUX_CFR_CSOF10_Msk          (0x1UL << DMAMUX_CFR_CSOF10_Pos)        /*!< 0x00000400 */

+#define DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10_Msk                   /*!< Channel 10 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF11_Pos          (11U)

+#define DMAMUX_CFR_CSOF11_Msk          (0x1UL << DMAMUX_CFR_CSOF11_Pos)        /*!< 0x00000800 */

+#define DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11_Msk                   /*!< Channel 11 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF12_Pos          (12U)

+#define DMAMUX_CFR_CSOF12_Msk          (0x1UL << DMAMUX_CFR_CSOF12_Pos)        /*!< 0x00001000 */

+#define DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12_Msk                   /*!< Channel 12 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF13_Pos          (13U)

+#define DMAMUX_CFR_CSOF13_Msk          (0x1UL << DMAMUX_CFR_CSOF13_Pos)        /*!< 0x00002000 */

+#define DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13_Msk                   /*!< Channel 13 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF14_Pos          (14U)

+#define DMAMUX_CFR_CSOF14_Msk          (0x1UL << DMAMUX_CFR_CSOF14_Pos)        /*!< 0x00004000 */

+#define DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14_Msk                   /*!< Channel 14 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF15_Pos          (15U)

+#define DMAMUX_CFR_CSOF15_Msk          (0x1UL << DMAMUX_CFR_CSOF15_Pos)        /*!< 0x00008000 */

+#define DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15_Msk                   /*!< Channel 15 Clear synchronization overrun event flag */

+

+/********************  Bits definition for DMAMUX_RGxCR register  ************/

+#define DMAMUX_RGxCR_SIG_ID_Pos        (0U)

+#define DMAMUX_RGxCR_SIG_ID_Msk        (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)     /*!< 0x0000001F */

+#define DMAMUX_RGxCR_SIG_ID            DMAMUX_RGxCR_SIG_ID_Msk                 /*!< Signal identification */

+#define DMAMUX_RGxCR_SIG_ID_0          (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000001 */

+#define DMAMUX_RGxCR_SIG_ID_1          (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000002 */

+#define DMAMUX_RGxCR_SIG_ID_2          (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000004 */

+#define DMAMUX_RGxCR_SIG_ID_3          (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000008 */

+#define DMAMUX_RGxCR_SIG_ID_4          (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000010 */

+#define DMAMUX_RGxCR_OIE_Pos           (8U)

+#define DMAMUX_RGxCR_OIE_Msk           (0x1UL << DMAMUX_RGxCR_OIE_Pos)         /*!< 0x00000100 */

+#define DMAMUX_RGxCR_OIE               DMAMUX_RGxCR_OIE_Msk                    /*!< Trigger overrun interrupt enable */

+#define DMAMUX_RGxCR_GE_Pos            (16U)

+#define DMAMUX_RGxCR_GE_Msk            (0x1UL << DMAMUX_RGxCR_GE_Pos)          /*!< 0x00010000 */

+#define DMAMUX_RGxCR_GE                DMAMUX_RGxCR_GE_Msk                     /*!< DMA request generator enable */

+#define DMAMUX_RGxCR_GPOL_Pos          (17U)

+#define DMAMUX_RGxCR_GPOL_Msk          (0x3UL << DMAMUX_RGxCR_GPOL_Pos)        /*!< 0x00060000 */

+#define DMAMUX_RGxCR_GPOL              DMAMUX_RGxCR_GPOL_Msk                   /*!< DMA request generator trigger polarity */

+#define DMAMUX_RGxCR_GPOL_0            (0x1UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00020000 */

+#define DMAMUX_RGxCR_GPOL_1            (0x2UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00040000 */

+#define DMAMUX_RGxCR_GNBREQ_Pos        (19U)

+#define DMAMUX_RGxCR_GNBREQ_Msk        (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)     /*!< 0x00F80000 */

+#define DMAMUX_RGxCR_GNBREQ            DMAMUX_RGxCR_GNBREQ_Msk                 /*!< Number of DMA requests to be generated */

+#define DMAMUX_RGxCR_GNBREQ_0          (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00080000 */

+#define DMAMUX_RGxCR_GNBREQ_1          (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00100000 */

+#define DMAMUX_RGxCR_GNBREQ_2          (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00200000 */

+#define DMAMUX_RGxCR_GNBREQ_3          (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00400000 */

+#define DMAMUX_RGxCR_GNBREQ_4          (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00800000 */

+

+/********************  Bits definition for DMAMUX_RGSR register  **************/

+#define DMAMUX_RGSR_OF0_Pos            (0U)

+#define DMAMUX_RGSR_OF0_Msk            (0x1UL << DMAMUX_RGSR_OF0_Pos)          /*!< 0x00000001 */

+#define DMAMUX_RGSR_OF0                DMAMUX_RGSR_OF0_Msk                     /*!< Request generator channel 0 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF1_Pos            (1U)

+#define DMAMUX_RGSR_OF1_Msk            (0x1UL << DMAMUX_RGSR_OF1_Pos)          /*!< 0x00000002 */

+#define DMAMUX_RGSR_OF1                DMAMUX_RGSR_OF1_Msk                     /*!< Request generator channel 1 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF2_Pos            (2U)

+#define DMAMUX_RGSR_OF2_Msk            (0x1UL << DMAMUX_RGSR_OF2_Pos)          /*!< 0x00000004 */

+#define DMAMUX_RGSR_OF2                DMAMUX_RGSR_OF2_Msk                     /*!< Request generator channel 2 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF3_Pos            (3U)

+#define DMAMUX_RGSR_OF3_Msk            (0x1UL << DMAMUX_RGSR_OF3_Pos)          /*!< 0x00000008 */

+#define DMAMUX_RGSR_OF3                DMAMUX_RGSR_OF3_Msk                     /*!< Request generator channel 3 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF4_Pos            (4U)

+#define DMAMUX_RGSR_OF4_Msk            (0x1UL << DMAMUX_RGSR_OF4_Pos)          /*!< 0x00000010 */

+#define DMAMUX_RGSR_OF4                DMAMUX_RGSR_OF4_Msk                     /*!< Request generator channel 4 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF5_Pos            (5U)

+#define DMAMUX_RGSR_OF5_Msk            (0x1UL << DMAMUX_RGSR_OF5_Pos)          /*!< 0x00000020 */

+#define DMAMUX_RGSR_OF5                DMAMUX_RGSR_OF5_Msk                     /*!< Request generator channel 5 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF6_Pos            (6U)

+#define DMAMUX_RGSR_OF6_Msk            (0x1UL << DMAMUX_RGSR_OF6_Pos)          /*!< 0x00000040 */

+#define DMAMUX_RGSR_OF6                DMAMUX_RGSR_OF6_Msk                     /*!< Request generator channel 6 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF7_Pos            (7U)

+#define DMAMUX_RGSR_OF7_Msk            (0x1UL << DMAMUX_RGSR_OF7_Pos)          /*!< 0x00000080 */

+#define DMAMUX_RGSR_OF7                DMAMUX_RGSR_OF7_Msk                     /*!< Request generator channel 7 Trigger overrun event flag */

+

+/********************  Bits definition for DMAMUX_RGCFR register  **************/

+#define DMAMUX_RGCFR_COF0_Pos          (0U)

+#define DMAMUX_RGCFR_COF0_Msk          (0x1UL << DMAMUX_RGCFR_COF0_Pos)        /*!< 0x00000001 */

+#define DMAMUX_RGCFR_COF0              DMAMUX_RGCFR_COF0_Msk                   /*!< Request generator channel 0 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF1_Pos          (1U)

+#define DMAMUX_RGCFR_COF1_Msk          (0x1UL << DMAMUX_RGCFR_COF1_Pos)        /*!< 0x00000002 */

+#define DMAMUX_RGCFR_COF1              DMAMUX_RGCFR_COF1_Msk                   /*!< Request generator channel 1 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF2_Pos          (2U)

+#define DMAMUX_RGCFR_COF2_Msk          (0x1UL << DMAMUX_RGCFR_COF2_Pos)        /*!< 0x00000004 */

+#define DMAMUX_RGCFR_COF2              DMAMUX_RGCFR_COF2_Msk                   /*!< Request generator channel 2 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF3_Pos          (3U)

+#define DMAMUX_RGCFR_COF3_Msk          (0x1UL << DMAMUX_RGCFR_COF3_Pos)        /*!< 0x00000008 */

+#define DMAMUX_RGCFR_COF3              DMAMUX_RGCFR_COF3_Msk                   /*!< Request generator channel 3 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF4_Pos          (4U)

+#define DMAMUX_RGCFR_COF4_Msk          (0x1UL << DMAMUX_RGCFR_COF4_Pos)        /*!< 0x00000010 */

+#define DMAMUX_RGCFR_COF4              DMAMUX_RGCFR_COF4_Msk                   /*!< Request generator channel 4 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF5_Pos          (5U)

+#define DMAMUX_RGCFR_COF5_Msk          (0x1UL << DMAMUX_RGCFR_COF5_Pos)        /*!< 0x00000020 */

+#define DMAMUX_RGCFR_COF5              DMAMUX_RGCFR_COF5_Msk                   /*!< Request generator channel 5 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF6_Pos          (6U)

+#define DMAMUX_RGCFR_COF6_Msk          (0x1UL << DMAMUX_RGCFR_COF6_Pos)        /*!< 0x00000040 */

+#define DMAMUX_RGCFR_COF6              DMAMUX_RGCFR_COF6_Msk                   /*!< Request generator channel 6 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF7_Pos          (7U)

+#define DMAMUX_RGCFR_COF7_Msk          (0x1UL << DMAMUX_RGCFR_COF7_Pos)        /*!< 0x00000080 */

+#define DMAMUX_RGCFR_COF7              DMAMUX_RGCFR_COF7_Msk                   /*!< Request generator channel 7 Clear trigger overrun event flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         AHB Master DMA2D Controller (DMA2D)                */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for DMA2D_CR register  ******************/

+

+#define DMA2D_CR_START_Pos         (0U)

+#define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)               /*!< 0x00000001 */

+#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer                          */

+#define DMA2D_CR_SUSP_Pos          (1U)

+#define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                /*!< 0x00000002 */

+#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer                        */

+#define DMA2D_CR_ABORT_Pos         (2U)

+#define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)               /*!< 0x00000004 */

+#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer                          */

+#define DMA2D_CR_LOM_Pos           (6U)

+#define DMA2D_CR_LOM_Msk           (0x1UL << DMA2D_CR_LOM_Pos)                 /*!< 0x00000040 */

+#define DMA2D_CR_LOM               DMA2D_CR_LOM_Msk                            /*!< Line Offset Mode                         */

+#define DMA2D_CR_TEIE_Pos          (8U)

+#define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                /*!< 0x00000100 */

+#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable         */

+#define DMA2D_CR_TCIE_Pos          (9U)

+#define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                /*!< 0x00000200 */

+#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable      */

+#define DMA2D_CR_TWIE_Pos          (10U)

+#define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                /*!< 0x00000400 */

+#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable     */

+#define DMA2D_CR_CAEIE_Pos         (11U)

+#define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)               /*!< 0x00000800 */

+#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable      */

+#define DMA2D_CR_CTCIE_Pos         (12U)

+#define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)               /*!< 0x00001000 */

+#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */

+#define DMA2D_CR_CEIE_Pos          (13U)

+#define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                /*!< 0x00002000 */

+#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable    */

+#define DMA2D_CR_MODE_Pos          (16U)

+#define DMA2D_CR_MODE_Msk          (0x7UL << DMA2D_CR_MODE_Pos)                /*!< 0x00070000 */

+#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[2:0]                         */

+#define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */

+#define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */

+#define DMA2D_CR_MODE_2            (0x4UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00040000 */

+

+/********************  Bit definition for DMA2D_ISR register  *****************/

+

+#define DMA2D_ISR_TEIF_Pos         (0U)

+#define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)               /*!< 0x00000001 */

+#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag         */

+#define DMA2D_ISR_TCIF_Pos         (1U)

+#define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)               /*!< 0x00000002 */

+#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag      */

+#define DMA2D_ISR_TWIF_Pos         (2U)

+#define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)               /*!< 0x00000004 */

+#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag     */

+#define DMA2D_ISR_CAEIF_Pos        (3U)

+#define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)              /*!< 0x00000008 */

+#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag      */

+#define DMA2D_ISR_CTCIF_Pos        (4U)

+#define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)              /*!< 0x00000010 */

+#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */

+#define DMA2D_ISR_CEIF_Pos         (5U)

+#define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)               /*!< 0x00000020 */

+#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag    */

+

+/********************  Bit definition for DMA2D_IFCR register  ****************/

+

+#define DMA2D_IFCR_CTEIF_Pos       (0U)

+#define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)             /*!< 0x00000001 */

+#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */

+#define DMA2D_IFCR_CTCIF_Pos       (1U)

+#define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)             /*!< 0x00000002 */

+#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */

+#define DMA2D_IFCR_CTWIF_Pos       (2U)

+#define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)             /*!< 0x00000004 */

+#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */

+#define DMA2D_IFCR_CAECIF_Pos      (3U)

+#define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)            /*!< 0x00000008 */

+#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */

+#define DMA2D_IFCR_CCTCIF_Pos      (4U)

+#define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)            /*!< 0x00000010 */

+#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */

+#define DMA2D_IFCR_CCEIF_Pos       (5U)

+#define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)             /*!< 0x00000020 */

+#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */

+

+/********************  Bit definition for DMA2D_FGMAR register  ***************/

+

+#define DMA2D_FGMAR_MA_Pos         (0U)

+#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)        /*!< 0xFFFFFFFF */

+#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Foreground Memory Address */

+

+/********************  Bit definition for DMA2D_FGOR register  ****************/

+

+#define DMA2D_FGOR_LO_Pos          (0U)

+#define DMA2D_FGOR_LO_Msk          (0xFFFFUL << DMA2D_FGOR_LO_Pos)             /*!< 0x0000FFFF */

+#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */

+

+/********************  Bit definition for DMA2D_BGMAR register  ***************/

+

+#define DMA2D_BGMAR_MA_Pos         (0U)

+#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)        /*!< 0xFFFFFFFF */

+#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Background Memory Address */

+

+/********************  Bit definition for DMA2D_BGOR register  ****************/

+

+#define DMA2D_BGOR_LO_Pos          (0U)

+#define DMA2D_BGOR_LO_Msk          (0xFFFFUL << DMA2D_BGOR_LO_Pos)             /*!< 0x0000FFFF */

+#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */

+

+/********************  Bit definition for DMA2D_FGPFCCR register  *************/

+

+#define DMA2D_FGPFCCR_CM_Pos       (0U)

+#define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x0000000F */

+#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */

+#define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */

+#define DMA2D_FGPFCCR_CCM_Pos      (4U)

+#define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)            /*!< 0x00000010 */

+#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */

+#define DMA2D_FGPFCCR_START_Pos    (5U)

+#define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)          /*!< 0x00000020 */

+#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */

+#define DMA2D_FGPFCCR_CS_Pos       (8U)

+#define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)            /*!< 0x0000FF00 */

+#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */

+#define DMA2D_FGPFCCR_AM_Pos       (16U)

+#define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00030000 */

+#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */

+#define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */

+#define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */

+#define DMA2D_FGPFCCR_CSS_Pos      (18U)

+#define DMA2D_FGPFCCR_CSS_Msk      (0x3UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x000C0000 */

+#define DMA2D_FGPFCCR_CSS          DMA2D_FGPFCCR_CSS_Msk                       /* !< Chroma Sub-Sampling */

+#define DMA2D_FGPFCCR_CSS_0        (0x1UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00040000 */

+#define DMA2D_FGPFCCR_CSS_1        (0x2UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00080000 */

+#define DMA2D_FGPFCCR_AI_Pos       (20U)

+#define DMA2D_FGPFCCR_AI_Msk       (0x1UL << DMA2D_FGPFCCR_AI_Pos)             /*!< 0x00100000 */

+#define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Foreground Input Alpha Inverted */

+#define DMA2D_FGPFCCR_RBS_Pos      (21U)

+#define DMA2D_FGPFCCR_RBS_Msk      (0x1UL << DMA2D_FGPFCCR_RBS_Pos)            /*!< 0x00200000 */

+#define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Foreground Input Red Blue Swap */

+#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)

+#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */

+#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */

+

+/********************  Bit definition for DMA2D_FGCOLR register  **************/

+

+#define DMA2D_FGCOLR_BLUE_Pos      (0U)

+#define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)           /*!< 0x000000FF */

+#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Foreground Blue Value */

+#define DMA2D_FGCOLR_GREEN_Pos     (8U)

+#define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */

+#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Foreground Green Value */

+#define DMA2D_FGCOLR_RED_Pos       (16U)

+#define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)            /*!< 0x00FF0000 */

+#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Foreground Red Value */

+

+/********************  Bit definition for DMA2D_BGPFCCR register  *************/

+

+#define DMA2D_BGPFCCR_CM_Pos       (0U)

+#define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x0000000F */

+#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */

+#define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_BGPFCCR_CM_3         (0x8UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000008 */

+#define DMA2D_BGPFCCR_CCM_Pos      (4U)

+#define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)            /*!< 0x00000010 */

+#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */

+#define DMA2D_BGPFCCR_START_Pos    (5U)

+#define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)          /*!< 0x00000020 */

+#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */

+#define DMA2D_BGPFCCR_CS_Pos       (8U)

+#define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)            /*!< 0x0000FF00 */

+#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */

+#define DMA2D_BGPFCCR_AM_Pos       (16U)

+#define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00030000 */

+#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */

+#define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */

+#define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */

+#define DMA2D_BGPFCCR_AI_Pos       (20U)

+#define DMA2D_BGPFCCR_AI_Msk       (0x1UL << DMA2D_BGPFCCR_AI_Pos)             /*!< 0x00100000 */

+#define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< background Input Alpha Inverted */

+#define DMA2D_BGPFCCR_RBS_Pos      (21U)

+#define DMA2D_BGPFCCR_RBS_Msk      (0x1UL << DMA2D_BGPFCCR_RBS_Pos)            /*!< 0x00200000 */

+#define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Background Input Red Blue Swap */

+#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)

+#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */

+#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */

+

+/********************  Bit definition for DMA2D_BGCOLR register  **************/

+

+#define DMA2D_BGCOLR_BLUE_Pos      (0U)

+#define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)           /*!< 0x000000FF */

+#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Background Blue Value */

+#define DMA2D_BGCOLR_GREEN_Pos     (8U)

+#define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */

+#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Background Green Value */

+#define DMA2D_BGCOLR_RED_Pos       (16U)

+#define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)            /*!< 0x00FF0000 */

+#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Background Red Value */

+

+/********************  Bit definition for DMA2D_FGCMAR register  **************/

+

+#define DMA2D_FGCMAR_MA_Pos        (0U)

+#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */

+#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Foreground CLUT Memory Address */

+

+/********************  Bit definition for DMA2D_BGCMAR register  **************/

+

+#define DMA2D_BGCMAR_MA_Pos        (0U)

+#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */

+#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Background CLUT Memory Address */

+

+/********************  Bit definition for DMA2D_OPFCCR register  **************/

+

+#define DMA2D_OPFCCR_CM_Pos        (0U)

+#define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000007 */

+#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Output Color mode CM[2:0] */

+#define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_OPFCCR_SB_Pos        (8U)

+#define DMA2D_OPFCCR_SB_Msk        (0x1UL << DMA2D_OPFCCR_SB_Pos)              /*!< 0x00000100 */

+#define DMA2D_OPFCCR_SB            DMA2D_OPFCCR_SB_Msk                         /*!< Swap Bytes */

+#define DMA2D_OPFCCR_AI_Pos        (20U)

+#define DMA2D_OPFCCR_AI_Msk        (0x1UL << DMA2D_OPFCCR_AI_Pos)              /*!< 0x00100000 */

+#define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Output Alpha Inverted */

+#define DMA2D_OPFCCR_RBS_Pos       (21U)

+#define DMA2D_OPFCCR_RBS_Msk       (0x1UL << DMA2D_OPFCCR_RBS_Pos)             /*!< 0x00200000 */

+#define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Output Red Blue Swap */

+

+/********************  Bit definition for DMA2D_OCOLR register  ***************/

+

+/*!<Mode_ARGB8888/RGB888 */

+

+#define DMA2D_OCOLR_BLUE_1_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_1_Msk     (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos)            /*0x000000FFU*/

+#define DMA2D_OCOLR_BLUE_1         DMA2D_OCOLR_BLUE_1_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_1_Pos    (8U)

+#define DMA2D_OCOLR_GREEN_1_Msk    (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos)            /*0x0000FF00U)*/

+#define DMA2D_OCOLR_GREEN_1        DMA2D_OCOLR_GREEN_1_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_1_Pos      (16U)

+#define DMA2D_OCOLR_RED_1_Msk      (0xFFUL << DMA2D_OCOLR_RED_1_Pos)            /*0x00FF0000U */

+#define DMA2D_OCOLR_RED_1          DMA2D_OCOLR_RED_1_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_1_Pos    (24U)

+#define DMA2D_OCOLR_ALPHA_1_Msk    (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos)          /*0xFF000000U*/

+#define DMA2D_OCOLR_ALPHA_1        DMA2D_OCOLR_ALPHA_1_Msk                     /*!< Output Alpha Channel Value */

+

+/*!<Mode_RGB565 */

+#define DMA2D_OCOLR_BLUE_2_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_2_Msk     (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos)            /*0x0000001FU*/

+#define DMA2D_OCOLR_BLUE_2         DMA2D_OCOLR_BLUE_2_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_2_Pos    (5U)

+#define DMA2D_OCOLR_GREEN_2_Msk    (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos)          /* 0x000007E0U */

+#define DMA2D_OCOLR_GREEN_2        DMA2D_OCOLR_GREEN_2_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_2_Pos      (11U)

+#define DMA2D_OCOLR_RED_2_Msk      (0xF8UL<<DMA2D_OCOLR_RED_2_Pos)              /*0x0000F800U*/

+#define DMA2D_OCOLR_RED_2          DMA2D_OCOLR_RED_2_Msk                       /*!< Output Red Value */

+

+/*!<Mode_ARGB1555 */

+#define DMA2D_OCOLR_BLUE_3_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_3_Msk     (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos)           /*0x0000001FU*/

+#define DMA2D_OCOLR_BLUE_3         DMA2D_OCOLR_BLUE_3_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_3_Pos    (5U)

+#define DMA2D_OCOLR_GREEN_3_Msk    (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos)          /*0x000003E0U*/

+#define DMA2D_OCOLR_GREEN_3        DMA2D_OCOLR_GREEN_3_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_3_Pos      (10U)

+#define DMA2D_OCOLR_RED_3_Msk      (0x7CUL << DMA2D_OCOLR_RED_3_Pos)            /* 0x00007C00U*/

+#define DMA2D_OCOLR_RED_3          DMA2D_OCOLR_RED_3_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_3_Pos    (15U)

+#define DMA2D_OCOLR_ALPHA_3_Msk    (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos)           /*0x00008000U*/

+#define DMA2D_OCOLR_ALPHA_3        DMA2D_OCOLR_ALPHA_3_Msk                     /*!< Output Alpha Channel Value */

+

+/*!<Mode_ARGB4444 */

+#define DMA2D_OCOLR_BLUE_4_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_4_Msk     (0xFUL << DMA2D_OCOLR_BLUE_4_Pos)            /*0x0000000FU*/

+#define DMA2D_OCOLR_BLUE_4         DMA2D_OCOLR_BLUE_4_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_4_Pos    (4U)

+#define DMA2D_OCOLR_GREEN_4_Msk    (0xFUL << DMA2D_OCOLR_GREEN_4_Pos)           /*0x000000F0U*/

+#define DMA2D_OCOLR_GREEN_4        DMA2D_OCOLR_GREEN_4_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_4_Pos      (8U)

+#define DMA2D_OCOLR_RED_4_Msk      (0xFUL << DMA2D_OCOLR_RED_4_Pos)             /*0x00000F00U*/

+#define DMA2D_OCOLR_RED_4          DMA2D_OCOLR_RED_4_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_4_Pos    (12U)

+#define DMA2D_OCOLR_ALPHA_4_Msk    (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos)            /*0x0000F000U*/

+#define DMA2D_OCOLR_ALPHA_4        DMA2D_OCOLR_ALPHA_4_Msk                     /*!< Output Alpha Channel Value */

+

+/********************  Bit definition for DMA2D_OMAR register  ****************/

+

+#define DMA2D_OMAR_MA_Pos          (0U)

+#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)         /*!< 0xFFFFFFFF */

+#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Output Memory Address */

+

+/********************  Bit definition for DMA2D_OOR register  *****************/

+

+#define DMA2D_OOR_LO_Pos           (0U)

+#define DMA2D_OOR_LO_Msk           (0xFFFFUL << DMA2D_OOR_LO_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Output Line Offset */

+

+/********************  Bit definition for DMA2D_NLR register  *****************/

+

+#define DMA2D_NLR_NL_Pos           (0U)

+#define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */

+#define DMA2D_NLR_PL_Pos           (16U)

+#define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)              /*!< 0x3FFF0000 */

+#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */

+

+/********************  Bit definition for DMA2D_LWR register  *****************/

+

+#define DMA2D_LWR_LW_Pos           (0U)

+#define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */

+

+/********************  Bit definition for DMA2D_AMTCR register  ***************/

+

+#define DMA2D_AMTCR_EN_Pos         (0U)

+#define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)               /*!< 0x00000001 */

+#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */

+#define DMA2D_AMTCR_DT_Pos         (8U)

+#define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)              /*!< 0x0000FF00 */

+#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */

+

+

+/********************  Bit definition for DMA2D_FGCLUT register  **************/

+

+/********************  Bit definition for DMA2D_BGCLUT register  **************/

+

+/******************************************************************************/

+/*                                                                            */

+/*                     Display Serial Interface (DSI)                         */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for DSI_VR register  *****************/

+#define DSI_VR_Pos                    (1U)

+#define DSI_VR_Msk                    (0x18999815UL << DSI_VR_Pos)             /*!< 0x3133302A */

+#define DSI_VR                        DSI_VR_Msk                               /*!< DSI Host Version */

+

+/*******************  Bit definition for DSI_CR register  *****************/

+#define DSI_CR_EN_Pos                 (0U)

+#define DSI_CR_EN_Msk                 (0x1UL << DSI_CR_EN_Pos)                 /*!< 0x00000001 */

+#define DSI_CR_EN                     DSI_CR_EN_Msk                            /*!< DSI Host power up and reset */

+

+/*******************  Bit definition for DSI_CCR register  ****************/

+#define DSI_CCR_TXECKDIV_Pos          (0U)

+#define DSI_CCR_TXECKDIV_Msk          (0xFFUL << DSI_CCR_TXECKDIV_Pos)         /*!< 0x000000FF */

+#define DSI_CCR_TXECKDIV              DSI_CCR_TXECKDIV_Msk                     /*!< TX Escape Clock Division */

+#define DSI_CCR_TXECKDIV0_Pos         (0U)

+#define DSI_CCR_TXECKDIV0_Msk         (0x1UL << DSI_CCR_TXECKDIV0_Pos)         /*!< 0x00000001 */

+#define DSI_CCR_TXECKDIV0             DSI_CCR_TXECKDIV0_Msk

+#define DSI_CCR_TXECKDIV1_Pos         (1U)

+#define DSI_CCR_TXECKDIV1_Msk         (0x1UL << DSI_CCR_TXECKDIV1_Pos)         /*!< 0x00000002 */

+#define DSI_CCR_TXECKDIV1             DSI_CCR_TXECKDIV1_Msk

+#define DSI_CCR_TXECKDIV2_Pos         (2U)

+#define DSI_CCR_TXECKDIV2_Msk         (0x1UL << DSI_CCR_TXECKDIV2_Pos)         /*!< 0x00000004 */

+#define DSI_CCR_TXECKDIV2             DSI_CCR_TXECKDIV2_Msk

+#define DSI_CCR_TXECKDIV3_Pos         (3U)

+#define DSI_CCR_TXECKDIV3_Msk         (0x1UL << DSI_CCR_TXECKDIV3_Pos)         /*!< 0x00000008 */

+#define DSI_CCR_TXECKDIV3             DSI_CCR_TXECKDIV3_Msk

+#define DSI_CCR_TXECKDIV4_Pos         (4U)

+#define DSI_CCR_TXECKDIV4_Msk         (0x1UL << DSI_CCR_TXECKDIV4_Pos)         /*!< 0x00000010 */

+#define DSI_CCR_TXECKDIV4             DSI_CCR_TXECKDIV4_Msk

+#define DSI_CCR_TXECKDIV5_Pos         (5U)

+#define DSI_CCR_TXECKDIV5_Msk         (0x1UL << DSI_CCR_TXECKDIV5_Pos)         /*!< 0x00000020 */

+#define DSI_CCR_TXECKDIV5             DSI_CCR_TXECKDIV5_Msk

+#define DSI_CCR_TXECKDIV6_Pos         (6U)

+#define DSI_CCR_TXECKDIV6_Msk         (0x1UL << DSI_CCR_TXECKDIV6_Pos)         /*!< 0x00000040 */

+#define DSI_CCR_TXECKDIV6             DSI_CCR_TXECKDIV6_Msk

+#define DSI_CCR_TXECKDIV7_Pos         (7U)

+#define DSI_CCR_TXECKDIV7_Msk         (0x1UL << DSI_CCR_TXECKDIV7_Pos)         /*!< 0x00000080 */

+#define DSI_CCR_TXECKDIV7             DSI_CCR_TXECKDIV7_Msk

+

+#define DSI_CCR_TOCKDIV_Pos           (8U)

+#define DSI_CCR_TOCKDIV_Msk           (0xFFUL << DSI_CCR_TOCKDIV_Pos)          /*!< 0x0000FF00 */

+#define DSI_CCR_TOCKDIV               DSI_CCR_TOCKDIV_Msk                      /*!< Timeout Clock Division */

+#define DSI_CCR_TOCKDIV0_Pos          (8U)

+#define DSI_CCR_TOCKDIV0_Msk          (0x1UL << DSI_CCR_TOCKDIV0_Pos)          /*!< 0x00000100 */

+#define DSI_CCR_TOCKDIV0              DSI_CCR_TOCKDIV0_Msk

+#define DSI_CCR_TOCKDIV1_Pos          (9U)

+#define DSI_CCR_TOCKDIV1_Msk          (0x1UL << DSI_CCR_TOCKDIV1_Pos)          /*!< 0x00000200 */

+#define DSI_CCR_TOCKDIV1              DSI_CCR_TOCKDIV1_Msk

+#define DSI_CCR_TOCKDIV2_Pos          (10U)

+#define DSI_CCR_TOCKDIV2_Msk          (0x1UL << DSI_CCR_TOCKDIV2_Pos)          /*!< 0x00000400 */

+#define DSI_CCR_TOCKDIV2              DSI_CCR_TOCKDIV2_Msk

+#define DSI_CCR_TOCKDIV3_Pos          (11U)

+#define DSI_CCR_TOCKDIV3_Msk          (0x1UL << DSI_CCR_TOCKDIV3_Pos)          /*!< 0x00000800 */

+#define DSI_CCR_TOCKDIV3              DSI_CCR_TOCKDIV3_Msk

+#define DSI_CCR_TOCKDIV4_Pos          (12U)

+#define DSI_CCR_TOCKDIV4_Msk          (0x1UL << DSI_CCR_TOCKDIV4_Pos)          /*!< 0x00001000 */

+#define DSI_CCR_TOCKDIV4              DSI_CCR_TOCKDIV4_Msk

+#define DSI_CCR_TOCKDIV5_Pos          (13U)

+#define DSI_CCR_TOCKDIV5_Msk          (0x1UL << DSI_CCR_TOCKDIV5_Pos)          /*!< 0x00002000 */

+#define DSI_CCR_TOCKDIV5              DSI_CCR_TOCKDIV5_Msk

+#define DSI_CCR_TOCKDIV6_Pos          (14U)

+#define DSI_CCR_TOCKDIV6_Msk          (0x1UL << DSI_CCR_TOCKDIV6_Pos)          /*!< 0x00004000 */

+#define DSI_CCR_TOCKDIV6              DSI_CCR_TOCKDIV6_Msk

+#define DSI_CCR_TOCKDIV7_Pos          (15U)

+#define DSI_CCR_TOCKDIV7_Msk          (0x1UL << DSI_CCR_TOCKDIV7_Pos)          /*!< 0x00008000 */

+#define DSI_CCR_TOCKDIV7              DSI_CCR_TOCKDIV7_Msk

+

+/*******************  Bit definition for DSI_LVCIDR register  *************/

+#define DSI_LVCIDR_VCID_Pos           (0U)

+#define DSI_LVCIDR_VCID_Msk           (0x3UL << DSI_LVCIDR_VCID_Pos)           /*!< 0x00000003 */

+#define DSI_LVCIDR_VCID               DSI_LVCIDR_VCID_Msk                      /*!< Virtual Channel ID */

+#define DSI_LVCIDR_VCID0_Pos          (0U)

+#define DSI_LVCIDR_VCID0_Msk          (0x1UL << DSI_LVCIDR_VCID0_Pos)          /*!< 0x00000001 */

+#define DSI_LVCIDR_VCID0              DSI_LVCIDR_VCID0_Msk

+#define DSI_LVCIDR_VCID1_Pos          (1U)

+#define DSI_LVCIDR_VCID1_Msk          (0x1UL << DSI_LVCIDR_VCID1_Pos)          /*!< 0x00000002 */

+#define DSI_LVCIDR_VCID1              DSI_LVCIDR_VCID1_Msk

+

+/*******************  Bit definition for DSI_LCOLCR register  *************/

+#define DSI_LCOLCR_COLC_Pos           (0U)

+#define DSI_LCOLCR_COLC_Msk           (0xFUL << DSI_LCOLCR_COLC_Pos)           /*!< 0x0000000F */

+#define DSI_LCOLCR_COLC               DSI_LCOLCR_COLC_Msk                      /*!< Color Coding */

+#define DSI_LCOLCR_COLC0_Pos          (0U)

+#define DSI_LCOLCR_COLC0_Msk          (0x1UL << DSI_LCOLCR_COLC0_Pos)          /*!< 0x00000001 */

+#define DSI_LCOLCR_COLC0              DSI_LCOLCR_COLC0_Msk

+#define DSI_LCOLCR_COLC1_Pos          (5U)

+#define DSI_LCOLCR_COLC1_Msk          (0x1UL << DSI_LCOLCR_COLC1_Pos)          /*!< 0x00000020 */

+#define DSI_LCOLCR_COLC1              DSI_LCOLCR_COLC1_Msk

+#define DSI_LCOLCR_COLC2_Pos          (6U)

+#define DSI_LCOLCR_COLC2_Msk          (0x1UL << DSI_LCOLCR_COLC2_Pos)          /*!< 0x00000040 */

+#define DSI_LCOLCR_COLC2              DSI_LCOLCR_COLC2_Msk

+#define DSI_LCOLCR_COLC3_Pos          (7U)

+#define DSI_LCOLCR_COLC3_Msk          (0x1UL << DSI_LCOLCR_COLC3_Pos)          /*!< 0x00000080 */

+#define DSI_LCOLCR_COLC3              DSI_LCOLCR_COLC3_Msk

+

+#define DSI_LCOLCR_LPE_Pos            (8U)

+#define DSI_LCOLCR_LPE_Msk            (0x1UL << DSI_LCOLCR_LPE_Pos)            /*!< 0x00000100 */

+#define DSI_LCOLCR_LPE                DSI_LCOLCR_LPE_Msk                       /*!< Loosly Packet Enable */

+

+/*******************  Bit definition for DSI_LPCR register  ***************/

+#define DSI_LPCR_DEP_Pos              (0U)

+#define DSI_LPCR_DEP_Msk              (0x1UL << DSI_LPCR_DEP_Pos)              /*!< 0x00000001 */

+#define DSI_LPCR_DEP                  DSI_LPCR_DEP_Msk                         /*!< Data Enable Polarity */

+#define DSI_LPCR_VSP_Pos              (1U)

+#define DSI_LPCR_VSP_Msk              (0x1UL << DSI_LPCR_VSP_Pos)              /*!< 0x00000002 */

+#define DSI_LPCR_VSP                  DSI_LPCR_VSP_Msk                         /*!< VSYNC Polarity */

+#define DSI_LPCR_HSP_Pos              (2U)

+#define DSI_LPCR_HSP_Msk              (0x1UL << DSI_LPCR_HSP_Pos)              /*!< 0x00000004 */

+#define DSI_LPCR_HSP                  DSI_LPCR_HSP_Msk                         /*!< HSYNC Polarity */

+

+/*******************  Bit definition for DSI_LPMCR register  **************/

+#define DSI_LPMCR_VLPSIZE_Pos         (0U)

+#define DSI_LPMCR_VLPSIZE_Msk         (0xFFUL << DSI_LPMCR_VLPSIZE_Pos)        /*!< 0x000000FF */

+#define DSI_LPMCR_VLPSIZE             DSI_LPMCR_VLPSIZE_Msk                    /*!< VACT Largest Packet Size */

+#define DSI_LPMCR_VLPSIZE0_Pos        (0U)

+#define DSI_LPMCR_VLPSIZE0_Msk        (0x1UL << DSI_LPMCR_VLPSIZE0_Pos)        /*!< 0x00000001 */

+#define DSI_LPMCR_VLPSIZE0            DSI_LPMCR_VLPSIZE0_Msk

+#define DSI_LPMCR_VLPSIZE1_Pos        (1U)

+#define DSI_LPMCR_VLPSIZE1_Msk        (0x1UL << DSI_LPMCR_VLPSIZE1_Pos)        /*!< 0x00000002 */

+#define DSI_LPMCR_VLPSIZE1            DSI_LPMCR_VLPSIZE1_Msk

+#define DSI_LPMCR_VLPSIZE2_Pos        (2U)

+#define DSI_LPMCR_VLPSIZE2_Msk        (0x1UL << DSI_LPMCR_VLPSIZE2_Pos)        /*!< 0x00000004 */

+#define DSI_LPMCR_VLPSIZE2            DSI_LPMCR_VLPSIZE2_Msk

+#define DSI_LPMCR_VLPSIZE3_Pos        (3U)

+#define DSI_LPMCR_VLPSIZE3_Msk        (0x1UL << DSI_LPMCR_VLPSIZE3_Pos)        /*!< 0x00000008 */

+#define DSI_LPMCR_VLPSIZE3            DSI_LPMCR_VLPSIZE3_Msk

+#define DSI_LPMCR_VLPSIZE4_Pos        (4U)

+#define DSI_LPMCR_VLPSIZE4_Msk        (0x1UL << DSI_LPMCR_VLPSIZE4_Pos)        /*!< 0x00000010 */

+#define DSI_LPMCR_VLPSIZE4            DSI_LPMCR_VLPSIZE4_Msk

+#define DSI_LPMCR_VLPSIZE5_Pos        (5U)

+#define DSI_LPMCR_VLPSIZE5_Msk        (0x1UL << DSI_LPMCR_VLPSIZE5_Pos)        /*!< 0x00000020 */

+#define DSI_LPMCR_VLPSIZE5            DSI_LPMCR_VLPSIZE5_Msk

+#define DSI_LPMCR_VLPSIZE6_Pos        (6U)

+#define DSI_LPMCR_VLPSIZE6_Msk        (0x1UL << DSI_LPMCR_VLPSIZE6_Pos)        /*!< 0x00000040 */

+#define DSI_LPMCR_VLPSIZE6            DSI_LPMCR_VLPSIZE6_Msk

+#define DSI_LPMCR_VLPSIZE7_Pos        (7U)

+#define DSI_LPMCR_VLPSIZE7_Msk        (0x1UL << DSI_LPMCR_VLPSIZE7_Pos)        /*!< 0x00000080 */

+#define DSI_LPMCR_VLPSIZE7            DSI_LPMCR_VLPSIZE7_Msk

+

+#define DSI_LPMCR_LPSIZE_Pos          (16U)

+#define DSI_LPMCR_LPSIZE_Msk          (0xFFUL << DSI_LPMCR_LPSIZE_Pos)         /*!< 0x00FF0000 */

+#define DSI_LPMCR_LPSIZE              DSI_LPMCR_LPSIZE_Msk                     /*!< Largest Packet Size */

+#define DSI_LPMCR_LPSIZE0_Pos         (16U)

+#define DSI_LPMCR_LPSIZE0_Msk         (0x1UL << DSI_LPMCR_LPSIZE0_Pos)         /*!< 0x00010000 */

+#define DSI_LPMCR_LPSIZE0             DSI_LPMCR_LPSIZE0_Msk

+#define DSI_LPMCR_LPSIZE1_Pos         (17U)

+#define DSI_LPMCR_LPSIZE1_Msk         (0x1UL << DSI_LPMCR_LPSIZE1_Pos)         /*!< 0x00020000 */

+#define DSI_LPMCR_LPSIZE1             DSI_LPMCR_LPSIZE1_Msk

+#define DSI_LPMCR_LPSIZE2_Pos         (18U)

+#define DSI_LPMCR_LPSIZE2_Msk         (0x1UL << DSI_LPMCR_LPSIZE2_Pos)         /*!< 0x00040000 */

+#define DSI_LPMCR_LPSIZE2             DSI_LPMCR_LPSIZE2_Msk

+#define DSI_LPMCR_LPSIZE3_Pos         (19U)

+#define DSI_LPMCR_LPSIZE3_Msk         (0x1UL << DSI_LPMCR_LPSIZE3_Pos)         /*!< 0x00080000 */

+#define DSI_LPMCR_LPSIZE3             DSI_LPMCR_LPSIZE3_Msk

+#define DSI_LPMCR_LPSIZE4_Pos         (20U)

+#define DSI_LPMCR_LPSIZE4_Msk         (0x1UL << DSI_LPMCR_LPSIZE4_Pos)         /*!< 0x00100000 */

+#define DSI_LPMCR_LPSIZE4             DSI_LPMCR_LPSIZE4_Msk

+#define DSI_LPMCR_LPSIZE5_Pos         (21U)

+#define DSI_LPMCR_LPSIZE5_Msk         (0x1UL << DSI_LPMCR_LPSIZE5_Pos)         /*!< 0x00200000 */

+#define DSI_LPMCR_LPSIZE5             DSI_LPMCR_LPSIZE5_Msk

+#define DSI_LPMCR_LPSIZE6_Pos         (22U)

+#define DSI_LPMCR_LPSIZE6_Msk         (0x1UL << DSI_LPMCR_LPSIZE6_Pos)         /*!< 0x00400000 */

+#define DSI_LPMCR_LPSIZE6             DSI_LPMCR_LPSIZE6_Msk

+#define DSI_LPMCR_LPSIZE7_Pos         (23U)

+#define DSI_LPMCR_LPSIZE7_Msk         (0x1UL << DSI_LPMCR_LPSIZE7_Pos)         /*!< 0x00800000 */

+#define DSI_LPMCR_LPSIZE7             DSI_LPMCR_LPSIZE7_Msk

+

+/*******************  Bit definition for DSI_PCR register  ****************/

+#define DSI_PCR_ETTXE_Pos             (0U)

+#define DSI_PCR_ETTXE_Msk             (0x1UL << DSI_PCR_ETTXE_Pos)             /*!< 0x00000001 */

+#define DSI_PCR_ETTXE                 DSI_PCR_ETTXE_Msk                        /*!< EoTp Transmission Enable */

+#define DSI_PCR_ETRXE_Pos             (1U)

+#define DSI_PCR_ETRXE_Msk             (0x1UL << DSI_PCR_ETRXE_Pos)             /*!< 0x00000002 */

+#define DSI_PCR_ETRXE                 DSI_PCR_ETRXE_Msk                        /*!< EoTp Reception Enable */

+#define DSI_PCR_BTAE_Pos              (2U)

+#define DSI_PCR_BTAE_Msk              (0x1UL << DSI_PCR_BTAE_Pos)              /*!< 0x00000004 */

+#define DSI_PCR_BTAE                  DSI_PCR_BTAE_Msk                         /*!< Bus Turn Around Enable */

+#define DSI_PCR_ECCRXE_Pos            (3U)

+#define DSI_PCR_ECCRXE_Msk            (0x1UL << DSI_PCR_ECCRXE_Pos)            /*!< 0x00000008 */

+#define DSI_PCR_ECCRXE                DSI_PCR_ECCRXE_Msk                       /*!< ECC Reception Enable */

+#define DSI_PCR_CRCRXE_Pos            (4U)

+#define DSI_PCR_CRCRXE_Msk            (0x1UL << DSI_PCR_CRCRXE_Pos)            /*!< 0x00000010 */

+#define DSI_PCR_CRCRXE                DSI_PCR_CRCRXE_Msk                       /*!< CRC Reception Enable */

+

+/*******************  Bit definition for DSI_GVCIDR register  *************/

+#define DSI_GVCIDR_VCID_Pos           (0U)

+#define DSI_GVCIDR_VCID_Msk           (0x3UL << DSI_GVCIDR_VCID_Pos)           /*!< 0x00000003 */

+#define DSI_GVCIDR_VCID               DSI_GVCIDR_VCID_Msk                      /*!< Virtual Channel ID */

+#define DSI_GVCIDR_VCID0_Pos          (0U)

+#define DSI_GVCIDR_VCID0_Msk          (0x1UL << DSI_GVCIDR_VCID0_Pos)          /*!< 0x00000001 */

+#define DSI_GVCIDR_VCID0              DSI_GVCIDR_VCID0_Msk

+#define DSI_GVCIDR_VCID1_Pos          (1U)

+#define DSI_GVCIDR_VCID1_Msk          (0x1UL << DSI_GVCIDR_VCID1_Pos)          /*!< 0x00000002 */

+#define DSI_GVCIDR_VCID1              DSI_GVCIDR_VCID1_Msk

+

+/*******************  Bit definition for DSI_MCR register  ****************/

+#define DSI_MCR_CMDM_Pos              (0U)

+#define DSI_MCR_CMDM_Msk              (0x1UL << DSI_MCR_CMDM_Pos)              /*!< 0x00000001 */

+#define DSI_MCR_CMDM                  DSI_MCR_CMDM_Msk                         /*!< Command Mode */

+

+/*******************  Bit definition for DSI_VMCR register  ***************/

+#define DSI_VMCR_VMT_Pos              (0U)

+#define DSI_VMCR_VMT_Msk              (0x3UL << DSI_VMCR_VMT_Pos)              /*!< 0x00000003 */

+#define DSI_VMCR_VMT                  DSI_VMCR_VMT_Msk                         /*!< Video Mode Type */

+#define DSI_VMCR_VMT0_Pos             (0U)

+#define DSI_VMCR_VMT0_Msk             (0x1UL << DSI_VMCR_VMT0_Pos)             /*!< 0x00000001 */

+#define DSI_VMCR_VMT0                 DSI_VMCR_VMT0_Msk

+#define DSI_VMCR_VMT1_Pos             (1U)

+#define DSI_VMCR_VMT1_Msk             (0x1UL << DSI_VMCR_VMT1_Pos)             /*!< 0x00000002 */

+#define DSI_VMCR_VMT1                 DSI_VMCR_VMT1_Msk

+

+#define DSI_VMCR_LPVSAE_Pos           (8U)

+#define DSI_VMCR_LPVSAE_Msk           (0x1UL << DSI_VMCR_LPVSAE_Pos)           /*!< 0x00000100 */

+#define DSI_VMCR_LPVSAE               DSI_VMCR_LPVSAE_Msk                      /*!< Low-Power Vertical Sync Active Enable */

+#define DSI_VMCR_LPVBPE_Pos           (9U)

+#define DSI_VMCR_LPVBPE_Msk           (0x1UL << DSI_VMCR_LPVBPE_Pos)           /*!< 0x00000200 */

+#define DSI_VMCR_LPVBPE               DSI_VMCR_LPVBPE_Msk                      /*!< Low-power Vertical Back-Porch Enable */

+#define DSI_VMCR_LPVFPE_Pos           (10U)

+#define DSI_VMCR_LPVFPE_Msk           (0x1UL << DSI_VMCR_LPVFPE_Pos)           /*!< 0x00000400 */

+#define DSI_VMCR_LPVFPE               DSI_VMCR_LPVFPE_Msk                      /*!< Low-power Vertical Front-porch Enable */

+#define DSI_VMCR_LPVAE_Pos            (11U)

+#define DSI_VMCR_LPVAE_Msk            (0x1UL << DSI_VMCR_LPVAE_Pos)            /*!< 0x00000800 */

+#define DSI_VMCR_LPVAE                DSI_VMCR_LPVAE_Msk                       /*!< Low-Power Vertical Active Enable */

+#define DSI_VMCR_LPHBPE_Pos           (12U)

+#define DSI_VMCR_LPHBPE_Msk           (0x1UL << DSI_VMCR_LPHBPE_Pos)           /*!< 0x00001000 */

+#define DSI_VMCR_LPHBPE               DSI_VMCR_LPHBPE_Msk                      /*!< Low-Power Horizontal Back-Porch Enable */

+#define DSI_VMCR_LPHFPE_Pos           (13U)

+#define DSI_VMCR_LPHFPE_Msk           (0x1UL << DSI_VMCR_LPHFPE_Pos)           /*!< 0x00002000 */

+#define DSI_VMCR_LPHFPE               DSI_VMCR_LPHFPE_Msk                      /*!< Low-Power Horizontal Front-Porch Enable */

+#define DSI_VMCR_FBTAAE_Pos           (14U)

+#define DSI_VMCR_FBTAAE_Msk           (0x1UL << DSI_VMCR_FBTAAE_Pos)           /*!< 0x00004000 */

+#define DSI_VMCR_FBTAAE               DSI_VMCR_FBTAAE_Msk                      /*!< Frame Bus-Turn-Around Acknowledge Enable */

+#define DSI_VMCR_LPCE_Pos             (15U)

+#define DSI_VMCR_LPCE_Msk             (0x1UL << DSI_VMCR_LPCE_Pos)             /*!< 0x00008000 */

+#define DSI_VMCR_LPCE                 DSI_VMCR_LPCE_Msk                        /*!< Low-Power Command Enable */

+#define DSI_VMCR_PGE_Pos              (16U)

+#define DSI_VMCR_PGE_Msk              (0x1UL << DSI_VMCR_PGE_Pos)              /*!< 0x00010000 */

+#define DSI_VMCR_PGE                  DSI_VMCR_PGE_Msk                         /*!< Pattern Generator Enable */

+#define DSI_VMCR_PGM_Pos              (20U)

+#define DSI_VMCR_PGM_Msk              (0x1UL << DSI_VMCR_PGM_Pos)              /*!< 0x00100000 */

+#define DSI_VMCR_PGM                  DSI_VMCR_PGM_Msk                         /*!< Pattern Generator Mode */

+#define DSI_VMCR_PGO_Pos              (24U)

+#define DSI_VMCR_PGO_Msk              (0x1UL << DSI_VMCR_PGO_Pos)              /*!< 0x01000000 */

+#define DSI_VMCR_PGO                  DSI_VMCR_PGO_Msk                         /*!< Pattern Generator Orientation */

+

+/*******************  Bit definition for DSI_VPCR register  ***************/

+#define DSI_VPCR_VPSIZE_Pos           (0U)

+#define DSI_VPCR_VPSIZE_Msk           (0x3FFFUL << DSI_VPCR_VPSIZE_Pos)        /*!< 0x00003FFF */

+#define DSI_VPCR_VPSIZE               DSI_VPCR_VPSIZE_Msk                      /*!< Video Packet Size */

+#define DSI_VPCR_VPSIZE0_Pos          (0U)

+#define DSI_VPCR_VPSIZE0_Msk          (0x1UL << DSI_VPCR_VPSIZE0_Pos)          /*!< 0x00000001 */

+#define DSI_VPCR_VPSIZE0              DSI_VPCR_VPSIZE0_Msk

+#define DSI_VPCR_VPSIZE1_Pos          (1U)

+#define DSI_VPCR_VPSIZE1_Msk          (0x1UL << DSI_VPCR_VPSIZE1_Pos)          /*!< 0x00000002 */

+#define DSI_VPCR_VPSIZE1              DSI_VPCR_VPSIZE1_Msk

+#define DSI_VPCR_VPSIZE2_Pos          (2U)

+#define DSI_VPCR_VPSIZE2_Msk          (0x1UL << DSI_VPCR_VPSIZE2_Pos)          /*!< 0x00000004 */

+#define DSI_VPCR_VPSIZE2              DSI_VPCR_VPSIZE2_Msk

+#define DSI_VPCR_VPSIZE3_Pos          (3U)

+#define DSI_VPCR_VPSIZE3_Msk          (0x1UL << DSI_VPCR_VPSIZE3_Pos)          /*!< 0x00000008 */

+#define DSI_VPCR_VPSIZE3              DSI_VPCR_VPSIZE3_Msk

+#define DSI_VPCR_VPSIZE4_Pos          (4U)

+#define DSI_VPCR_VPSIZE4_Msk          (0x1UL << DSI_VPCR_VPSIZE4_Pos)          /*!< 0x00000010 */

+#define DSI_VPCR_VPSIZE4              DSI_VPCR_VPSIZE4_Msk

+#define DSI_VPCR_VPSIZE5_Pos          (5U)

+#define DSI_VPCR_VPSIZE5_Msk          (0x1UL << DSI_VPCR_VPSIZE5_Pos)          /*!< 0x00000020 */

+#define DSI_VPCR_VPSIZE5              DSI_VPCR_VPSIZE5_Msk

+#define DSI_VPCR_VPSIZE6_Pos          (6U)

+#define DSI_VPCR_VPSIZE6_Msk          (0x1UL << DSI_VPCR_VPSIZE6_Pos)          /*!< 0x00000040 */

+#define DSI_VPCR_VPSIZE6              DSI_VPCR_VPSIZE6_Msk

+#define DSI_VPCR_VPSIZE7_Pos          (7U)

+#define DSI_VPCR_VPSIZE7_Msk          (0x1UL << DSI_VPCR_VPSIZE7_Pos)          /*!< 0x00000080 */

+#define DSI_VPCR_VPSIZE7              DSI_VPCR_VPSIZE7_Msk

+#define DSI_VPCR_VPSIZE8_Pos          (8U)

+#define DSI_VPCR_VPSIZE8_Msk          (0x1UL << DSI_VPCR_VPSIZE8_Pos)          /*!< 0x00000100 */

+#define DSI_VPCR_VPSIZE8              DSI_VPCR_VPSIZE8_Msk

+#define DSI_VPCR_VPSIZE9_Pos          (9U)

+#define DSI_VPCR_VPSIZE9_Msk          (0x1UL << DSI_VPCR_VPSIZE9_Pos)          /*!< 0x00000200 */

+#define DSI_VPCR_VPSIZE9              DSI_VPCR_VPSIZE9_Msk

+#define DSI_VPCR_VPSIZE10_Pos         (10U)

+#define DSI_VPCR_VPSIZE10_Msk         (0x1UL << DSI_VPCR_VPSIZE10_Pos)         /*!< 0x00000400 */

+#define DSI_VPCR_VPSIZE10             DSI_VPCR_VPSIZE10_Msk

+#define DSI_VPCR_VPSIZE11_Pos         (11U)

+#define DSI_VPCR_VPSIZE11_Msk         (0x1UL << DSI_VPCR_VPSIZE11_Pos)         /*!< 0x00000800 */

+#define DSI_VPCR_VPSIZE11             DSI_VPCR_VPSIZE11_Msk

+#define DSI_VPCR_VPSIZE12_Pos         (12U)

+#define DSI_VPCR_VPSIZE12_Msk         (0x1UL << DSI_VPCR_VPSIZE12_Pos)         /*!< 0x00001000 */

+#define DSI_VPCR_VPSIZE12             DSI_VPCR_VPSIZE12_Msk

+#define DSI_VPCR_VPSIZE13_Pos         (13U)

+#define DSI_VPCR_VPSIZE13_Msk         (0x1UL << DSI_VPCR_VPSIZE13_Pos)         /*!< 0x00002000 */

+#define DSI_VPCR_VPSIZE13             DSI_VPCR_VPSIZE13_Msk

+

+/*******************  Bit definition for DSI_VCCR register  ***************/

+#define DSI_VCCR_NUMC_Pos             (0U)

+#define DSI_VCCR_NUMC_Msk             (0x1FFFUL << DSI_VCCR_NUMC_Pos)          /*!< 0x00001FFF */

+#define DSI_VCCR_NUMC                 DSI_VCCR_NUMC_Msk                        /*!< Number of Chunks */

+#define DSI_VCCR_NUMC0_Pos            (0U)

+#define DSI_VCCR_NUMC0_Msk            (0x1UL << DSI_VCCR_NUMC0_Pos)            /*!< 0x00000001 */

+#define DSI_VCCR_NUMC0                DSI_VCCR_NUMC0_Msk

+#define DSI_VCCR_NUMC1_Pos            (1U)

+#define DSI_VCCR_NUMC1_Msk            (0x1UL << DSI_VCCR_NUMC1_Pos)            /*!< 0x00000002 */

+#define DSI_VCCR_NUMC1                DSI_VCCR_NUMC1_Msk

+#define DSI_VCCR_NUMC2_Pos            (2U)

+#define DSI_VCCR_NUMC2_Msk            (0x1UL << DSI_VCCR_NUMC2_Pos)            /*!< 0x00000004 */

+#define DSI_VCCR_NUMC2                DSI_VCCR_NUMC2_Msk

+#define DSI_VCCR_NUMC3_Pos            (3U)

+#define DSI_VCCR_NUMC3_Msk            (0x1UL << DSI_VCCR_NUMC3_Pos)            /*!< 0x00000008 */

+#define DSI_VCCR_NUMC3                DSI_VCCR_NUMC3_Msk

+#define DSI_VCCR_NUMC4_Pos            (4U)

+#define DSI_VCCR_NUMC4_Msk            (0x1UL << DSI_VCCR_NUMC4_Pos)            /*!< 0x00000010 */

+#define DSI_VCCR_NUMC4                DSI_VCCR_NUMC4_Msk

+#define DSI_VCCR_NUMC5_Pos            (5U)

+#define DSI_VCCR_NUMC5_Msk            (0x1UL << DSI_VCCR_NUMC5_Pos)            /*!< 0x00000020 */

+#define DSI_VCCR_NUMC5                DSI_VCCR_NUMC5_Msk

+#define DSI_VCCR_NUMC6_Pos            (6U)

+#define DSI_VCCR_NUMC6_Msk            (0x1UL << DSI_VCCR_NUMC6_Pos)            /*!< 0x00000040 */

+#define DSI_VCCR_NUMC6                DSI_VCCR_NUMC6_Msk

+#define DSI_VCCR_NUMC7_Pos            (7U)

+#define DSI_VCCR_NUMC7_Msk            (0x1UL << DSI_VCCR_NUMC7_Pos)            /*!< 0x00000080 */

+#define DSI_VCCR_NUMC7                DSI_VCCR_NUMC7_Msk

+#define DSI_VCCR_NUMC8_Pos            (8U)

+#define DSI_VCCR_NUMC8_Msk            (0x1UL << DSI_VCCR_NUMC8_Pos)            /*!< 0x00000100 */

+#define DSI_VCCR_NUMC8                DSI_VCCR_NUMC8_Msk

+#define DSI_VCCR_NUMC9_Pos            (9U)

+#define DSI_VCCR_NUMC9_Msk            (0x1UL << DSI_VCCR_NUMC9_Pos)            /*!< 0x00000200 */

+#define DSI_VCCR_NUMC9                DSI_VCCR_NUMC9_Msk

+#define DSI_VCCR_NUMC10_Pos           (10U)

+#define DSI_VCCR_NUMC10_Msk           (0x1UL << DSI_VCCR_NUMC10_Pos)           /*!< 0x00000400 */

+#define DSI_VCCR_NUMC10               DSI_VCCR_NUMC10_Msk

+#define DSI_VCCR_NUMC11_Pos           (11U)

+#define DSI_VCCR_NUMC11_Msk           (0x1UL << DSI_VCCR_NUMC11_Pos)           /*!< 0x00000800 */

+#define DSI_VCCR_NUMC11               DSI_VCCR_NUMC11_Msk

+#define DSI_VCCR_NUMC12_Pos           (12U)

+#define DSI_VCCR_NUMC12_Msk           (0x1UL << DSI_VCCR_NUMC12_Pos)           /*!< 0x00001000 */

+#define DSI_VCCR_NUMC12               DSI_VCCR_NUMC12_Msk

+

+/*******************  Bit definition for DSI_VNPCR register  **************/

+#define DSI_VNPCR_NPSIZE_Pos          (0U)

+#define DSI_VNPCR_NPSIZE_Msk          (0x1FFFUL << DSI_VNPCR_NPSIZE_Pos)       /*!< 0x00001FFF */

+#define DSI_VNPCR_NPSIZE              DSI_VNPCR_NPSIZE_Msk                     /*!< Null Packet Size */

+#define DSI_VNPCR_NPSIZE0_Pos         (0U)

+#define DSI_VNPCR_NPSIZE0_Msk         (0x1UL << DSI_VNPCR_NPSIZE0_Pos)         /*!< 0x00000001 */

+#define DSI_VNPCR_NPSIZE0             DSI_VNPCR_NPSIZE0_Msk

+#define DSI_VNPCR_NPSIZE1_Pos         (1U)

+#define DSI_VNPCR_NPSIZE1_Msk         (0x1UL << DSI_VNPCR_NPSIZE1_Pos)         /*!< 0x00000002 */

+#define DSI_VNPCR_NPSIZE1             DSI_VNPCR_NPSIZE1_Msk

+#define DSI_VNPCR_NPSIZE2_Pos         (2U)

+#define DSI_VNPCR_NPSIZE2_Msk         (0x1UL << DSI_VNPCR_NPSIZE2_Pos)         /*!< 0x00000004 */

+#define DSI_VNPCR_NPSIZE2             DSI_VNPCR_NPSIZE2_Msk

+#define DSI_VNPCR_NPSIZE3_Pos         (3U)

+#define DSI_VNPCR_NPSIZE3_Msk         (0x1UL << DSI_VNPCR_NPSIZE3_Pos)         /*!< 0x00000008 */

+#define DSI_VNPCR_NPSIZE3             DSI_VNPCR_NPSIZE3_Msk

+#define DSI_VNPCR_NPSIZE4_Pos         (4U)

+#define DSI_VNPCR_NPSIZE4_Msk         (0x1UL << DSI_VNPCR_NPSIZE4_Pos)         /*!< 0x00000010 */

+#define DSI_VNPCR_NPSIZE4             DSI_VNPCR_NPSIZE4_Msk

+#define DSI_VNPCR_NPSIZE5_Pos         (5U)

+#define DSI_VNPCR_NPSIZE5_Msk         (0x1UL << DSI_VNPCR_NPSIZE5_Pos)         /*!< 0x00000020 */

+#define DSI_VNPCR_NPSIZE5             DSI_VNPCR_NPSIZE5_Msk

+#define DSI_VNPCR_NPSIZE6_Pos         (6U)

+#define DSI_VNPCR_NPSIZE6_Msk         (0x1UL << DSI_VNPCR_NPSIZE6_Pos)         /*!< 0x00000040 */

+#define DSI_VNPCR_NPSIZE6             DSI_VNPCR_NPSIZE6_Msk

+#define DSI_VNPCR_NPSIZE7_Pos         (7U)

+#define DSI_VNPCR_NPSIZE7_Msk         (0x1UL << DSI_VNPCR_NPSIZE7_Pos)         /*!< 0x00000080 */

+#define DSI_VNPCR_NPSIZE7             DSI_VNPCR_NPSIZE7_Msk

+#define DSI_VNPCR_NPSIZE8_Pos         (8U)

+#define DSI_VNPCR_NPSIZE8_Msk         (0x1UL << DSI_VNPCR_NPSIZE8_Pos)         /*!< 0x00000100 */

+#define DSI_VNPCR_NPSIZE8             DSI_VNPCR_NPSIZE8_Msk

+#define DSI_VNPCR_NPSIZE9_Pos         (9U)

+#define DSI_VNPCR_NPSIZE9_Msk         (0x1UL << DSI_VNPCR_NPSIZE9_Pos)         /*!< 0x00000200 */

+#define DSI_VNPCR_NPSIZE9             DSI_VNPCR_NPSIZE9_Msk

+#define DSI_VNPCR_NPSIZE10_Pos        (10U)

+#define DSI_VNPCR_NPSIZE10_Msk        (0x1UL << DSI_VNPCR_NPSIZE10_Pos)        /*!< 0x00000400 */

+#define DSI_VNPCR_NPSIZE10            DSI_VNPCR_NPSIZE10_Msk

+#define DSI_VNPCR_NPSIZE11_Pos        (11U)

+#define DSI_VNPCR_NPSIZE11_Msk        (0x1UL << DSI_VNPCR_NPSIZE11_Pos)        /*!< 0x00000800 */

+#define DSI_VNPCR_NPSIZE11            DSI_VNPCR_NPSIZE11_Msk

+#define DSI_VNPCR_NPSIZE12_Pos        (12U)

+#define DSI_VNPCR_NPSIZE12_Msk        (0x1UL << DSI_VNPCR_NPSIZE12_Pos)        /*!< 0x00001000 */

+#define DSI_VNPCR_NPSIZE12            DSI_VNPCR_NPSIZE12_Msk

+

+/*******************  Bit definition for DSI_VHSACR register  *************/

+#define DSI_VHSACR_HSA_Pos            (0U)

+#define DSI_VHSACR_HSA_Msk            (0xFFFUL << DSI_VHSACR_HSA_Pos)          /*!< 0x00000FFF */

+#define DSI_VHSACR_HSA                DSI_VHSACR_HSA_Msk                       /*!< Horizontal Synchronism Active duration */

+#define DSI_VHSACR_HSA0_Pos           (0U)

+#define DSI_VHSACR_HSA0_Msk           (0x1UL << DSI_VHSACR_HSA0_Pos)           /*!< 0x00000001 */

+#define DSI_VHSACR_HSA0               DSI_VHSACR_HSA0_Msk

+#define DSI_VHSACR_HSA1_Pos           (1U)

+#define DSI_VHSACR_HSA1_Msk           (0x1UL << DSI_VHSACR_HSA1_Pos)           /*!< 0x00000002 */

+#define DSI_VHSACR_HSA1               DSI_VHSACR_HSA1_Msk

+#define DSI_VHSACR_HSA2_Pos           (2U)

+#define DSI_VHSACR_HSA2_Msk           (0x1UL << DSI_VHSACR_HSA2_Pos)           /*!< 0x00000004 */

+#define DSI_VHSACR_HSA2               DSI_VHSACR_HSA2_Msk

+#define DSI_VHSACR_HSA3_Pos           (3U)

+#define DSI_VHSACR_HSA3_Msk           (0x1UL << DSI_VHSACR_HSA3_Pos)           /*!< 0x00000008 */

+#define DSI_VHSACR_HSA3               DSI_VHSACR_HSA3_Msk

+#define DSI_VHSACR_HSA4_Pos           (4U)

+#define DSI_VHSACR_HSA4_Msk           (0x1UL << DSI_VHSACR_HSA4_Pos)           /*!< 0x00000010 */

+#define DSI_VHSACR_HSA4               DSI_VHSACR_HSA4_Msk

+#define DSI_VHSACR_HSA5_Pos           (5U)

+#define DSI_VHSACR_HSA5_Msk           (0x1UL << DSI_VHSACR_HSA5_Pos)           /*!< 0x00000020 */

+#define DSI_VHSACR_HSA5               DSI_VHSACR_HSA5_Msk

+#define DSI_VHSACR_HSA6_Pos           (6U)

+#define DSI_VHSACR_HSA6_Msk           (0x1UL << DSI_VHSACR_HSA6_Pos)           /*!< 0x00000040 */

+#define DSI_VHSACR_HSA6               DSI_VHSACR_HSA6_Msk

+#define DSI_VHSACR_HSA7_Pos           (7U)

+#define DSI_VHSACR_HSA7_Msk           (0x1UL << DSI_VHSACR_HSA7_Pos)           /*!< 0x00000080 */

+#define DSI_VHSACR_HSA7               DSI_VHSACR_HSA7_Msk

+#define DSI_VHSACR_HSA8_Pos           (8U)

+#define DSI_VHSACR_HSA8_Msk           (0x1UL << DSI_VHSACR_HSA8_Pos)           /*!< 0x00000100 */

+#define DSI_VHSACR_HSA8               DSI_VHSACR_HSA8_Msk

+#define DSI_VHSACR_HSA9_Pos           (9U)

+#define DSI_VHSACR_HSA9_Msk           (0x1UL << DSI_VHSACR_HSA9_Pos)           /*!< 0x00000200 */

+#define DSI_VHSACR_HSA9               DSI_VHSACR_HSA9_Msk

+#define DSI_VHSACR_HSA10_Pos          (10U)

+#define DSI_VHSACR_HSA10_Msk          (0x1UL << DSI_VHSACR_HSA10_Pos)          /*!< 0x00000400 */

+#define DSI_VHSACR_HSA10              DSI_VHSACR_HSA10_Msk

+#define DSI_VHSACR_HSA11_Pos          (11U)

+#define DSI_VHSACR_HSA11_Msk          (0x1UL << DSI_VHSACR_HSA11_Pos)          /*!< 0x00000800 */

+#define DSI_VHSACR_HSA11              DSI_VHSACR_HSA11_Msk

+

+/*******************  Bit definition for DSI_VHBPCR register  *************/

+#define DSI_VHBPCR_HBP_Pos            (0U)

+#define DSI_VHBPCR_HBP_Msk            (0xFFFUL << DSI_VHBPCR_HBP_Pos)          /*!< 0x00000FFF */

+#define DSI_VHBPCR_HBP                DSI_VHBPCR_HBP_Msk                       /*!< Horizontal Back-Porch duration */

+#define DSI_VHBPCR_HBP0_Pos           (0U)

+#define DSI_VHBPCR_HBP0_Msk           (0x1UL << DSI_VHBPCR_HBP0_Pos)           /*!< 0x00000001 */

+#define DSI_VHBPCR_HBP0               DSI_VHBPCR_HBP0_Msk

+#define DSI_VHBPCR_HBP1_Pos           (1U)

+#define DSI_VHBPCR_HBP1_Msk           (0x1UL << DSI_VHBPCR_HBP1_Pos)           /*!< 0x00000002 */

+#define DSI_VHBPCR_HBP1               DSI_VHBPCR_HBP1_Msk

+#define DSI_VHBPCR_HBP2_Pos           (2U)

+#define DSI_VHBPCR_HBP2_Msk           (0x1UL << DSI_VHBPCR_HBP2_Pos)           /*!< 0x00000004 */

+#define DSI_VHBPCR_HBP2               DSI_VHBPCR_HBP2_Msk

+#define DSI_VHBPCR_HBP3_Pos           (3U)

+#define DSI_VHBPCR_HBP3_Msk           (0x1UL << DSI_VHBPCR_HBP3_Pos)           /*!< 0x00000008 */

+#define DSI_VHBPCR_HBP3               DSI_VHBPCR_HBP3_Msk

+#define DSI_VHBPCR_HBP4_Pos           (4U)

+#define DSI_VHBPCR_HBP4_Msk           (0x1UL << DSI_VHBPCR_HBP4_Pos)           /*!< 0x00000010 */

+#define DSI_VHBPCR_HBP4               DSI_VHBPCR_HBP4_Msk

+#define DSI_VHBPCR_HBP5_Pos           (5U)

+#define DSI_VHBPCR_HBP5_Msk           (0x1UL << DSI_VHBPCR_HBP5_Pos)           /*!< 0x00000020 */

+#define DSI_VHBPCR_HBP5               DSI_VHBPCR_HBP5_Msk

+#define DSI_VHBPCR_HBP6_Pos           (6U)

+#define DSI_VHBPCR_HBP6_Msk           (0x1UL << DSI_VHBPCR_HBP6_Pos)           /*!< 0x00000040 */

+#define DSI_VHBPCR_HBP6               DSI_VHBPCR_HBP6_Msk

+#define DSI_VHBPCR_HBP7_Pos           (7U)

+#define DSI_VHBPCR_HBP7_Msk           (0x1UL << DSI_VHBPCR_HBP7_Pos)           /*!< 0x00000080 */

+#define DSI_VHBPCR_HBP7               DSI_VHBPCR_HBP7_Msk

+#define DSI_VHBPCR_HBP8_Pos           (8U)

+#define DSI_VHBPCR_HBP8_Msk           (0x1UL << DSI_VHBPCR_HBP8_Pos)           /*!< 0x00000100 */

+#define DSI_VHBPCR_HBP8               DSI_VHBPCR_HBP8_Msk

+#define DSI_VHBPCR_HBP9_Pos           (9U)

+#define DSI_VHBPCR_HBP9_Msk           (0x1UL << DSI_VHBPCR_HBP9_Pos)           /*!< 0x00000200 */

+#define DSI_VHBPCR_HBP9               DSI_VHBPCR_HBP9_Msk

+#define DSI_VHBPCR_HBP10_Pos          (10U)

+#define DSI_VHBPCR_HBP10_Msk          (0x1UL << DSI_VHBPCR_HBP10_Pos)          /*!< 0x00000400 */

+#define DSI_VHBPCR_HBP10              DSI_VHBPCR_HBP10_Msk

+#define DSI_VHBPCR_HBP11_Pos          (11U)

+#define DSI_VHBPCR_HBP11_Msk          (0x1UL << DSI_VHBPCR_HBP11_Pos)          /*!< 0x00000800 */

+#define DSI_VHBPCR_HBP11              DSI_VHBPCR_HBP11_Msk

+

+/*******************  Bit definition for DSI_VLCR register  ***************/

+#define DSI_VLCR_HLINE_Pos            (0U)

+#define DSI_VLCR_HLINE_Msk            (0x7FFFUL << DSI_VLCR_HLINE_Pos)         /*!< 0x00007FFF */

+#define DSI_VLCR_HLINE                DSI_VLCR_HLINE_Msk                       /*!< Horizontal Line duration */

+#define DSI_VLCR_HLINE0_Pos           (0U)

+#define DSI_VLCR_HLINE0_Msk           (0x1UL << DSI_VLCR_HLINE0_Pos)           /*!< 0x00000001 */

+#define DSI_VLCR_HLINE0               DSI_VLCR_HLINE0_Msk

+#define DSI_VLCR_HLINE1_Pos           (1U)

+#define DSI_VLCR_HLINE1_Msk           (0x1UL << DSI_VLCR_HLINE1_Pos)           /*!< 0x00000002 */

+#define DSI_VLCR_HLINE1               DSI_VLCR_HLINE1_Msk

+#define DSI_VLCR_HLINE2_Pos           (2U)

+#define DSI_VLCR_HLINE2_Msk           (0x1UL << DSI_VLCR_HLINE2_Pos)           /*!< 0x00000004 */

+#define DSI_VLCR_HLINE2               DSI_VLCR_HLINE2_Msk

+#define DSI_VLCR_HLINE3_Pos           (3U)

+#define DSI_VLCR_HLINE3_Msk           (0x1UL << DSI_VLCR_HLINE3_Pos)           /*!< 0x00000008 */

+#define DSI_VLCR_HLINE3               DSI_VLCR_HLINE3_Msk

+#define DSI_VLCR_HLINE4_Pos           (4U)

+#define DSI_VLCR_HLINE4_Msk           (0x1UL << DSI_VLCR_HLINE4_Pos)           /*!< 0x00000010 */

+#define DSI_VLCR_HLINE4               DSI_VLCR_HLINE4_Msk

+#define DSI_VLCR_HLINE5_Pos           (5U)

+#define DSI_VLCR_HLINE5_Msk           (0x1UL << DSI_VLCR_HLINE5_Pos)           /*!< 0x00000020 */

+#define DSI_VLCR_HLINE5               DSI_VLCR_HLINE5_Msk

+#define DSI_VLCR_HLINE6_Pos           (6U)

+#define DSI_VLCR_HLINE6_Msk           (0x1UL << DSI_VLCR_HLINE6_Pos)           /*!< 0x00000040 */

+#define DSI_VLCR_HLINE6               DSI_VLCR_HLINE6_Msk

+#define DSI_VLCR_HLINE7_Pos           (7U)

+#define DSI_VLCR_HLINE7_Msk           (0x1UL << DSI_VLCR_HLINE7_Pos)           /*!< 0x00000080 */

+#define DSI_VLCR_HLINE7               DSI_VLCR_HLINE7_Msk

+#define DSI_VLCR_HLINE8_Pos           (8U)

+#define DSI_VLCR_HLINE8_Msk           (0x1UL << DSI_VLCR_HLINE8_Pos)           /*!< 0x00000100 */

+#define DSI_VLCR_HLINE8               DSI_VLCR_HLINE8_Msk

+#define DSI_VLCR_HLINE9_Pos           (9U)

+#define DSI_VLCR_HLINE9_Msk           (0x1UL << DSI_VLCR_HLINE9_Pos)           /*!< 0x00000200 */

+#define DSI_VLCR_HLINE9               DSI_VLCR_HLINE9_Msk

+#define DSI_VLCR_HLINE10_Pos          (10U)

+#define DSI_VLCR_HLINE10_Msk          (0x1UL << DSI_VLCR_HLINE10_Pos)          /*!< 0x00000400 */

+#define DSI_VLCR_HLINE10              DSI_VLCR_HLINE10_Msk

+#define DSI_VLCR_HLINE11_Pos          (11U)

+#define DSI_VLCR_HLINE11_Msk          (0x1UL << DSI_VLCR_HLINE11_Pos)          /*!< 0x00000800 */

+#define DSI_VLCR_HLINE11              DSI_VLCR_HLINE11_Msk

+#define DSI_VLCR_HLINE12_Pos          (12U)

+#define DSI_VLCR_HLINE12_Msk          (0x1UL << DSI_VLCR_HLINE12_Pos)          /*!< 0x00001000 */

+#define DSI_VLCR_HLINE12              DSI_VLCR_HLINE12_Msk

+#define DSI_VLCR_HLINE13_Pos          (13U)

+#define DSI_VLCR_HLINE13_Msk          (0x1UL << DSI_VLCR_HLINE13_Pos)          /*!< 0x00002000 */

+#define DSI_VLCR_HLINE13              DSI_VLCR_HLINE13_Msk

+#define DSI_VLCR_HLINE14_Pos          (14U)

+#define DSI_VLCR_HLINE14_Msk          (0x1UL << DSI_VLCR_HLINE14_Pos)          /*!< 0x00004000 */

+#define DSI_VLCR_HLINE14              DSI_VLCR_HLINE14_Msk

+

+/*******************  Bit definition for DSI_VVSACR register  *************/

+#define DSI_VVSACR_VSA_Pos            (0U)

+#define DSI_VVSACR_VSA_Msk            (0x3FFUL << DSI_VVSACR_VSA_Pos)          /*!< 0x000003FF */

+#define DSI_VVSACR_VSA                DSI_VVSACR_VSA_Msk                       /*!< Vertical Synchronism Active duration */

+#define DSI_VVSACR_VSA0_Pos           (0U)

+#define DSI_VVSACR_VSA0_Msk           (0x1UL << DSI_VVSACR_VSA0_Pos)           /*!< 0x00000001 */

+#define DSI_VVSACR_VSA0               DSI_VVSACR_VSA0_Msk

+#define DSI_VVSACR_VSA1_Pos           (1U)

+#define DSI_VVSACR_VSA1_Msk           (0x1UL << DSI_VVSACR_VSA1_Pos)           /*!< 0x00000002 */

+#define DSI_VVSACR_VSA1               DSI_VVSACR_VSA1_Msk

+#define DSI_VVSACR_VSA2_Pos           (2U)

+#define DSI_VVSACR_VSA2_Msk           (0x1UL << DSI_VVSACR_VSA2_Pos)           /*!< 0x00000004 */

+#define DSI_VVSACR_VSA2               DSI_VVSACR_VSA2_Msk

+#define DSI_VVSACR_VSA3_Pos           (3U)

+#define DSI_VVSACR_VSA3_Msk           (0x1UL << DSI_VVSACR_VSA3_Pos)           /*!< 0x00000008 */

+#define DSI_VVSACR_VSA3               DSI_VVSACR_VSA3_Msk

+#define DSI_VVSACR_VSA4_Pos           (4U)

+#define DSI_VVSACR_VSA4_Msk           (0x1UL << DSI_VVSACR_VSA4_Pos)           /*!< 0x00000010 */

+#define DSI_VVSACR_VSA4               DSI_VVSACR_VSA4_Msk

+#define DSI_VVSACR_VSA5_Pos           (5U)

+#define DSI_VVSACR_VSA5_Msk           (0x1UL << DSI_VVSACR_VSA5_Pos)           /*!< 0x00000020 */

+#define DSI_VVSACR_VSA5               DSI_VVSACR_VSA5_Msk

+#define DSI_VVSACR_VSA6_Pos           (6U)

+#define DSI_VVSACR_VSA6_Msk           (0x1UL << DSI_VVSACR_VSA6_Pos)           /*!< 0x00000040 */

+#define DSI_VVSACR_VSA6               DSI_VVSACR_VSA6_Msk

+#define DSI_VVSACR_VSA7_Pos           (7U)

+#define DSI_VVSACR_VSA7_Msk           (0x1UL << DSI_VVSACR_VSA7_Pos)           /*!< 0x00000080 */

+#define DSI_VVSACR_VSA7               DSI_VVSACR_VSA7_Msk

+#define DSI_VVSACR_VSA8_Pos           (8U)

+#define DSI_VVSACR_VSA8_Msk           (0x1UL << DSI_VVSACR_VSA8_Pos)           /*!< 0x00000100 */

+#define DSI_VVSACR_VSA8               DSI_VVSACR_VSA8_Msk

+#define DSI_VVSACR_VSA9_Pos           (9U)

+#define DSI_VVSACR_VSA9_Msk           (0x1UL << DSI_VVSACR_VSA9_Pos)           /*!< 0x00000200 */

+#define DSI_VVSACR_VSA9               DSI_VVSACR_VSA9_Msk

+

+/*******************  Bit definition for DSI_VVBPCR register  *************/

+#define DSI_VVBPCR_VBP_Pos            (0U)

+#define DSI_VVBPCR_VBP_Msk            (0x3FFUL << DSI_VVBPCR_VBP_Pos)          /*!< 0x000003FF */

+#define DSI_VVBPCR_VBP                DSI_VVBPCR_VBP_Msk                       /*!< Vertical Back-Porch duration */

+#define DSI_VVBPCR_VBP0_Pos           (0U)

+#define DSI_VVBPCR_VBP0_Msk           (0x1UL << DSI_VVBPCR_VBP0_Pos)           /*!< 0x00000001 */

+#define DSI_VVBPCR_VBP0               DSI_VVBPCR_VBP0_Msk

+#define DSI_VVBPCR_VBP1_Pos           (1U)

+#define DSI_VVBPCR_VBP1_Msk           (0x1UL << DSI_VVBPCR_VBP1_Pos)           /*!< 0x00000002 */

+#define DSI_VVBPCR_VBP1               DSI_VVBPCR_VBP1_Msk

+#define DSI_VVBPCR_VBP2_Pos           (2U)

+#define DSI_VVBPCR_VBP2_Msk           (0x1UL << DSI_VVBPCR_VBP2_Pos)           /*!< 0x00000004 */

+#define DSI_VVBPCR_VBP2               DSI_VVBPCR_VBP2_Msk

+#define DSI_VVBPCR_VBP3_Pos           (3U)

+#define DSI_VVBPCR_VBP3_Msk           (0x1UL << DSI_VVBPCR_VBP3_Pos)           /*!< 0x00000008 */

+#define DSI_VVBPCR_VBP3               DSI_VVBPCR_VBP3_Msk

+#define DSI_VVBPCR_VBP4_Pos           (4U)

+#define DSI_VVBPCR_VBP4_Msk           (0x1UL << DSI_VVBPCR_VBP4_Pos)           /*!< 0x00000010 */

+#define DSI_VVBPCR_VBP4               DSI_VVBPCR_VBP4_Msk

+#define DSI_VVBPCR_VBP5_Pos           (5U)

+#define DSI_VVBPCR_VBP5_Msk           (0x1UL << DSI_VVBPCR_VBP5_Pos)           /*!< 0x00000020 */

+#define DSI_VVBPCR_VBP5               DSI_VVBPCR_VBP5_Msk

+#define DSI_VVBPCR_VBP6_Pos           (6U)

+#define DSI_VVBPCR_VBP6_Msk           (0x1UL << DSI_VVBPCR_VBP6_Pos)           /*!< 0x00000040 */

+#define DSI_VVBPCR_VBP6               DSI_VVBPCR_VBP6_Msk

+#define DSI_VVBPCR_VBP7_Pos           (7U)

+#define DSI_VVBPCR_VBP7_Msk           (0x1UL << DSI_VVBPCR_VBP7_Pos)           /*!< 0x00000080 */

+#define DSI_VVBPCR_VBP7               DSI_VVBPCR_VBP7_Msk

+#define DSI_VVBPCR_VBP8_Pos           (8U)

+#define DSI_VVBPCR_VBP8_Msk           (0x1UL << DSI_VVBPCR_VBP8_Pos)           /*!< 0x00000100 */

+#define DSI_VVBPCR_VBP8               DSI_VVBPCR_VBP8_Msk

+#define DSI_VVBPCR_VBP9_Pos           (9U)

+#define DSI_VVBPCR_VBP9_Msk           (0x1UL << DSI_VVBPCR_VBP9_Pos)           /*!< 0x00000200 */

+#define DSI_VVBPCR_VBP9               DSI_VVBPCR_VBP9_Msk

+

+/*******************  Bit definition for DSI_VVFPCR register  *************/

+#define DSI_VVFPCR_VFP_Pos            (0U)

+#define DSI_VVFPCR_VFP_Msk            (0x3FFUL << DSI_VVFPCR_VFP_Pos)          /*!< 0x000003FF */

+#define DSI_VVFPCR_VFP                DSI_VVFPCR_VFP_Msk                       /*!< Vertical Front-Porch duration */

+#define DSI_VVFPCR_VFP0_Pos           (0U)

+#define DSI_VVFPCR_VFP0_Msk           (0x1UL << DSI_VVFPCR_VFP0_Pos)           /*!< 0x00000001 */

+#define DSI_VVFPCR_VFP0               DSI_VVFPCR_VFP0_Msk

+#define DSI_VVFPCR_VFP1_Pos           (1U)

+#define DSI_VVFPCR_VFP1_Msk           (0x1UL << DSI_VVFPCR_VFP1_Pos)           /*!< 0x00000002 */

+#define DSI_VVFPCR_VFP1               DSI_VVFPCR_VFP1_Msk

+#define DSI_VVFPCR_VFP2_Pos           (2U)

+#define DSI_VVFPCR_VFP2_Msk           (0x1UL << DSI_VVFPCR_VFP2_Pos)           /*!< 0x00000004 */

+#define DSI_VVFPCR_VFP2               DSI_VVFPCR_VFP2_Msk

+#define DSI_VVFPCR_VFP3_Pos           (3U)

+#define DSI_VVFPCR_VFP3_Msk           (0x1UL << DSI_VVFPCR_VFP3_Pos)           /*!< 0x00000008 */

+#define DSI_VVFPCR_VFP3               DSI_VVFPCR_VFP3_Msk

+#define DSI_VVFPCR_VFP4_Pos           (4U)

+#define DSI_VVFPCR_VFP4_Msk           (0x1UL << DSI_VVFPCR_VFP4_Pos)           /*!< 0x00000010 */

+#define DSI_VVFPCR_VFP4               DSI_VVFPCR_VFP4_Msk

+#define DSI_VVFPCR_VFP5_Pos           (5U)

+#define DSI_VVFPCR_VFP5_Msk           (0x1UL << DSI_VVFPCR_VFP5_Pos)           /*!< 0x00000020 */

+#define DSI_VVFPCR_VFP5               DSI_VVFPCR_VFP5_Msk

+#define DSI_VVFPCR_VFP6_Pos           (6U)

+#define DSI_VVFPCR_VFP6_Msk           (0x1UL << DSI_VVFPCR_VFP6_Pos)           /*!< 0x00000040 */

+#define DSI_VVFPCR_VFP6               DSI_VVFPCR_VFP6_Msk

+#define DSI_VVFPCR_VFP7_Pos           (7U)

+#define DSI_VVFPCR_VFP7_Msk           (0x1UL << DSI_VVFPCR_VFP7_Pos)           /*!< 0x00000080 */

+#define DSI_VVFPCR_VFP7               DSI_VVFPCR_VFP7_Msk

+#define DSI_VVFPCR_VFP8_Pos           (8U)

+#define DSI_VVFPCR_VFP8_Msk           (0x1UL << DSI_VVFPCR_VFP8_Pos)           /*!< 0x00000100 */

+#define DSI_VVFPCR_VFP8               DSI_VVFPCR_VFP8_Msk

+#define DSI_VVFPCR_VFP9_Pos           (9U)

+#define DSI_VVFPCR_VFP9_Msk           (0x1UL << DSI_VVFPCR_VFP9_Pos)           /*!< 0x00000200 */

+#define DSI_VVFPCR_VFP9               DSI_VVFPCR_VFP9_Msk

+

+/*******************  Bit definition for DSI_VVACR register  **************/

+#define DSI_VVACR_VA_Pos              (0U)

+#define DSI_VVACR_VA_Msk              (0x3FFFUL << DSI_VVACR_VA_Pos)           /*!< 0x00003FFF */

+#define DSI_VVACR_VA                  DSI_VVACR_VA_Msk                         /*!< Vertical Active duration */

+#define DSI_VVACR_VA0_Pos             (0U)

+#define DSI_VVACR_VA0_Msk             (0x1UL << DSI_VVACR_VA0_Pos)             /*!< 0x00000001 */

+#define DSI_VVACR_VA0                 DSI_VVACR_VA0_Msk

+#define DSI_VVACR_VA1_Pos             (1U)

+#define DSI_VVACR_VA1_Msk             (0x1UL << DSI_VVACR_VA1_Pos)             /*!< 0x00000002 */

+#define DSI_VVACR_VA1                 DSI_VVACR_VA1_Msk

+#define DSI_VVACR_VA2_Pos             (2U)

+#define DSI_VVACR_VA2_Msk             (0x1UL << DSI_VVACR_VA2_Pos)             /*!< 0x00000004 */

+#define DSI_VVACR_VA2                 DSI_VVACR_VA2_Msk

+#define DSI_VVACR_VA3_Pos             (3U)

+#define DSI_VVACR_VA3_Msk             (0x1UL << DSI_VVACR_VA3_Pos)             /*!< 0x00000008 */

+#define DSI_VVACR_VA3                 DSI_VVACR_VA3_Msk

+#define DSI_VVACR_VA4_Pos             (4U)

+#define DSI_VVACR_VA4_Msk             (0x1UL << DSI_VVACR_VA4_Pos)             /*!< 0x00000010 */

+#define DSI_VVACR_VA4                 DSI_VVACR_VA4_Msk

+#define DSI_VVACR_VA5_Pos             (5U)

+#define DSI_VVACR_VA5_Msk             (0x1UL << DSI_VVACR_VA5_Pos)             /*!< 0x00000020 */

+#define DSI_VVACR_VA5                 DSI_VVACR_VA5_Msk

+#define DSI_VVACR_VA6_Pos             (6U)

+#define DSI_VVACR_VA6_Msk             (0x1UL << DSI_VVACR_VA6_Pos)             /*!< 0x00000040 */

+#define DSI_VVACR_VA6                 DSI_VVACR_VA6_Msk

+#define DSI_VVACR_VA7_Pos             (7U)

+#define DSI_VVACR_VA7_Msk             (0x1UL << DSI_VVACR_VA7_Pos)             /*!< 0x00000080 */

+#define DSI_VVACR_VA7                 DSI_VVACR_VA7_Msk

+#define DSI_VVACR_VA8_Pos             (8U)

+#define DSI_VVACR_VA8_Msk             (0x1UL << DSI_VVACR_VA8_Pos)             /*!< 0x00000100 */

+#define DSI_VVACR_VA8                 DSI_VVACR_VA8_Msk

+#define DSI_VVACR_VA9_Pos             (9U)

+#define DSI_VVACR_VA9_Msk             (0x1UL << DSI_VVACR_VA9_Pos)             /*!< 0x00000200 */

+#define DSI_VVACR_VA9                 DSI_VVACR_VA9_Msk

+#define DSI_VVACR_VA10_Pos            (10U)

+#define DSI_VVACR_VA10_Msk            (0x1UL << DSI_VVACR_VA10_Pos)            /*!< 0x00000400 */

+#define DSI_VVACR_VA10                DSI_VVACR_VA10_Msk

+#define DSI_VVACR_VA11_Pos            (11U)

+#define DSI_VVACR_VA11_Msk            (0x1UL << DSI_VVACR_VA11_Pos)            /*!< 0x00000800 */

+#define DSI_VVACR_VA11                DSI_VVACR_VA11_Msk

+#define DSI_VVACR_VA12_Pos            (12U)

+#define DSI_VVACR_VA12_Msk            (0x1UL << DSI_VVACR_VA12_Pos)            /*!< 0x00001000 */

+#define DSI_VVACR_VA12                DSI_VVACR_VA12_Msk

+#define DSI_VVACR_VA13_Pos            (13U)

+#define DSI_VVACR_VA13_Msk            (0x1UL << DSI_VVACR_VA13_Pos)            /*!< 0x00002000 */

+#define DSI_VVACR_VA13                DSI_VVACR_VA13_Msk

+

+/*******************  Bit definition for DSI_LCCR register  ***************/

+#define DSI_LCCR_CMDSIZE_Pos          (0U)

+#define DSI_LCCR_CMDSIZE_Msk          (0xFFFFUL << DSI_LCCR_CMDSIZE_Pos)       /*!< 0x0000FFFF */

+#define DSI_LCCR_CMDSIZE              DSI_LCCR_CMDSIZE_Msk                     /*!< Command Size */

+#define DSI_LCCR_CMDSIZE0_Pos         (0U)

+#define DSI_LCCR_CMDSIZE0_Msk         (0x1UL << DSI_LCCR_CMDSIZE0_Pos)         /*!< 0x00000001 */

+#define DSI_LCCR_CMDSIZE0             DSI_LCCR_CMDSIZE0_Msk

+#define DSI_LCCR_CMDSIZE1_Pos         (1U)

+#define DSI_LCCR_CMDSIZE1_Msk         (0x1UL << DSI_LCCR_CMDSIZE1_Pos)         /*!< 0x00000002 */

+#define DSI_LCCR_CMDSIZE1             DSI_LCCR_CMDSIZE1_Msk

+#define DSI_LCCR_CMDSIZE2_Pos         (2U)

+#define DSI_LCCR_CMDSIZE2_Msk         (0x1UL << DSI_LCCR_CMDSIZE2_Pos)         /*!< 0x00000004 */

+#define DSI_LCCR_CMDSIZE2             DSI_LCCR_CMDSIZE2_Msk

+#define DSI_LCCR_CMDSIZE3_Pos         (3U)

+#define DSI_LCCR_CMDSIZE3_Msk         (0x1UL << DSI_LCCR_CMDSIZE3_Pos)         /*!< 0x00000008 */

+#define DSI_LCCR_CMDSIZE3             DSI_LCCR_CMDSIZE3_Msk

+#define DSI_LCCR_CMDSIZE4_Pos         (4U)

+#define DSI_LCCR_CMDSIZE4_Msk         (0x1UL << DSI_LCCR_CMDSIZE4_Pos)         /*!< 0x00000010 */

+#define DSI_LCCR_CMDSIZE4             DSI_LCCR_CMDSIZE4_Msk

+#define DSI_LCCR_CMDSIZE5_Pos         (5U)

+#define DSI_LCCR_CMDSIZE5_Msk         (0x1UL << DSI_LCCR_CMDSIZE5_Pos)         /*!< 0x00000020 */

+#define DSI_LCCR_CMDSIZE5             DSI_LCCR_CMDSIZE5_Msk

+#define DSI_LCCR_CMDSIZE6_Pos         (6U)

+#define DSI_LCCR_CMDSIZE6_Msk         (0x1UL << DSI_LCCR_CMDSIZE6_Pos)         /*!< 0x00000040 */

+#define DSI_LCCR_CMDSIZE6             DSI_LCCR_CMDSIZE6_Msk

+#define DSI_LCCR_CMDSIZE7_Pos         (7U)

+#define DSI_LCCR_CMDSIZE7_Msk         (0x1UL << DSI_LCCR_CMDSIZE7_Pos)         /*!< 0x00000080 */

+#define DSI_LCCR_CMDSIZE7             DSI_LCCR_CMDSIZE7_Msk

+#define DSI_LCCR_CMDSIZE8_Pos         (8U)

+#define DSI_LCCR_CMDSIZE8_Msk         (0x1UL << DSI_LCCR_CMDSIZE8_Pos)         /*!< 0x00000100 */

+#define DSI_LCCR_CMDSIZE8             DSI_LCCR_CMDSIZE8_Msk

+#define DSI_LCCR_CMDSIZE9_Pos         (9U)

+#define DSI_LCCR_CMDSIZE9_Msk         (0x1UL << DSI_LCCR_CMDSIZE9_Pos)         /*!< 0x00000200 */

+#define DSI_LCCR_CMDSIZE9             DSI_LCCR_CMDSIZE9_Msk

+#define DSI_LCCR_CMDSIZE10_Pos        (10U)

+#define DSI_LCCR_CMDSIZE10_Msk        (0x1UL << DSI_LCCR_CMDSIZE10_Pos)        /*!< 0x00000400 */

+#define DSI_LCCR_CMDSIZE10            DSI_LCCR_CMDSIZE10_Msk

+#define DSI_LCCR_CMDSIZE11_Pos        (11U)

+#define DSI_LCCR_CMDSIZE11_Msk        (0x1UL << DSI_LCCR_CMDSIZE11_Pos)        /*!< 0x00000800 */

+#define DSI_LCCR_CMDSIZE11            DSI_LCCR_CMDSIZE11_Msk

+#define DSI_LCCR_CMDSIZE12_Pos        (12U)

+#define DSI_LCCR_CMDSIZE12_Msk        (0x1UL << DSI_LCCR_CMDSIZE12_Pos)        /*!< 0x00001000 */

+#define DSI_LCCR_CMDSIZE12            DSI_LCCR_CMDSIZE12_Msk

+#define DSI_LCCR_CMDSIZE13_Pos        (13U)

+#define DSI_LCCR_CMDSIZE13_Msk        (0x1UL << DSI_LCCR_CMDSIZE13_Pos)        /*!< 0x00002000 */

+#define DSI_LCCR_CMDSIZE13            DSI_LCCR_CMDSIZE13_Msk

+#define DSI_LCCR_CMDSIZE14_Pos        (14U)

+#define DSI_LCCR_CMDSIZE14_Msk        (0x1UL << DSI_LCCR_CMDSIZE14_Pos)        /*!< 0x00004000 */

+#define DSI_LCCR_CMDSIZE14            DSI_LCCR_CMDSIZE14_Msk

+#define DSI_LCCR_CMDSIZE15_Pos        (15U)

+#define DSI_LCCR_CMDSIZE15_Msk        (0x1UL << DSI_LCCR_CMDSIZE15_Pos)        /*!< 0x00008000 */

+#define DSI_LCCR_CMDSIZE15            DSI_LCCR_CMDSIZE15_Msk

+

+/*******************  Bit definition for DSI_CMCR register  ***************/

+#define DSI_CMCR_TEARE_Pos            (0U)

+#define DSI_CMCR_TEARE_Msk            (0x1UL << DSI_CMCR_TEARE_Pos)            /*!< 0x00000001 */

+#define DSI_CMCR_TEARE                DSI_CMCR_TEARE_Msk                       /*!< Tearing Effect Acknowledge Request Enable */

+#define DSI_CMCR_ARE_Pos              (1U)

+#define DSI_CMCR_ARE_Msk              (0x1UL << DSI_CMCR_ARE_Pos)              /*!< 0x00000002 */

+#define DSI_CMCR_ARE                  DSI_CMCR_ARE_Msk                         /*!< Acknowledge Request Enable */

+#define DSI_CMCR_GSW0TX_Pos           (8U)

+#define DSI_CMCR_GSW0TX_Msk           (0x1UL << DSI_CMCR_GSW0TX_Pos)           /*!< 0x00000100 */

+#define DSI_CMCR_GSW0TX               DSI_CMCR_GSW0TX_Msk                      /*!< Generic Short Write Zero parameters Transmission */

+#define DSI_CMCR_GSW1TX_Pos           (9U)

+#define DSI_CMCR_GSW1TX_Msk           (0x1UL << DSI_CMCR_GSW1TX_Pos)           /*!< 0x00000200 */

+#define DSI_CMCR_GSW1TX               DSI_CMCR_GSW1TX_Msk                      /*!< Generic Short Write One parameters Transmission */

+#define DSI_CMCR_GSW2TX_Pos           (10U)

+#define DSI_CMCR_GSW2TX_Msk           (0x1UL << DSI_CMCR_GSW2TX_Pos)           /*!< 0x00000400 */

+#define DSI_CMCR_GSW2TX               DSI_CMCR_GSW2TX_Msk                      /*!< Generic Short Write Two parameters Transmission */

+#define DSI_CMCR_GSR0TX_Pos           (11U)

+#define DSI_CMCR_GSR0TX_Msk           (0x1UL << DSI_CMCR_GSR0TX_Pos)           /*!< 0x00000800 */

+#define DSI_CMCR_GSR0TX               DSI_CMCR_GSR0TX_Msk                      /*!< Generic Short Read Zero parameters Transmission */

+#define DSI_CMCR_GSR1TX_Pos           (12U)

+#define DSI_CMCR_GSR1TX_Msk           (0x1UL << DSI_CMCR_GSR1TX_Pos)           /*!< 0x00001000 */

+#define DSI_CMCR_GSR1TX               DSI_CMCR_GSR1TX_Msk                      /*!< Generic Short Read One parameters Transmission */

+#define DSI_CMCR_GSR2TX_Pos           (13U)

+#define DSI_CMCR_GSR2TX_Msk           (0x1UL << DSI_CMCR_GSR2TX_Pos)           /*!< 0x00002000 */

+#define DSI_CMCR_GSR2TX               DSI_CMCR_GSR2TX_Msk                      /*!< Generic Short Read Two parameters Transmission */

+#define DSI_CMCR_GLWTX_Pos            (14U)

+#define DSI_CMCR_GLWTX_Msk            (0x1UL << DSI_CMCR_GLWTX_Pos)            /*!< 0x00004000 */

+#define DSI_CMCR_GLWTX                DSI_CMCR_GLWTX_Msk                       /*!< Generic Long Write Transmission */

+#define DSI_CMCR_DSW0TX_Pos           (16U)

+#define DSI_CMCR_DSW0TX_Msk           (0x1UL << DSI_CMCR_DSW0TX_Pos)           /*!< 0x00010000 */

+#define DSI_CMCR_DSW0TX               DSI_CMCR_DSW0TX_Msk                      /*!< DCS Short Write Zero parameter Transmission */

+#define DSI_CMCR_DSW1TX_Pos           (17U)

+#define DSI_CMCR_DSW1TX_Msk           (0x1UL << DSI_CMCR_DSW1TX_Pos)           /*!< 0x00020000 */

+#define DSI_CMCR_DSW1TX               DSI_CMCR_DSW1TX_Msk                      /*!< DCS Short Read One parameter Transmission */

+#define DSI_CMCR_DSR0TX_Pos           (18U)

+#define DSI_CMCR_DSR0TX_Msk           (0x1UL << DSI_CMCR_DSR0TX_Pos)           /*!< 0x00040000 */

+#define DSI_CMCR_DSR0TX               DSI_CMCR_DSR0TX_Msk                      /*!< DCS Short Read Zero parameter Transmission */

+#define DSI_CMCR_DLWTX_Pos            (19U)

+#define DSI_CMCR_DLWTX_Msk            (0x1UL << DSI_CMCR_DLWTX_Pos)            /*!< 0x00080000 */

+#define DSI_CMCR_DLWTX                DSI_CMCR_DLWTX_Msk                       /*!< DCS Long Write Transmission */

+#define DSI_CMCR_MRDPS_Pos            (24U)

+#define DSI_CMCR_MRDPS_Msk            (0x1UL << DSI_CMCR_MRDPS_Pos)            /*!< 0x01000000 */

+#define DSI_CMCR_MRDPS                DSI_CMCR_MRDPS_Msk                       /*!< Maximum Read Packet Size */

+

+/*******************  Bit definition for DSI_GHCR register  ***************/

+#define DSI_GHCR_DT_Pos               (0U)

+#define DSI_GHCR_DT_Msk               (0x3FUL << DSI_GHCR_DT_Pos)              /*!< 0x0000003F */

+#define DSI_GHCR_DT                   DSI_GHCR_DT_Msk                          /*!< Type */

+#define DSI_GHCR_DT0_Pos              (0U)

+#define DSI_GHCR_DT0_Msk              (0x1UL << DSI_GHCR_DT0_Pos)              /*!< 0x00000001 */

+#define DSI_GHCR_DT0                  DSI_GHCR_DT0_Msk

+#define DSI_GHCR_DT1_Pos              (1U)

+#define DSI_GHCR_DT1_Msk              (0x1UL << DSI_GHCR_DT1_Pos)              /*!< 0x00000002 */

+#define DSI_GHCR_DT1                  DSI_GHCR_DT1_Msk

+#define DSI_GHCR_DT2_Pos              (2U)

+#define DSI_GHCR_DT2_Msk              (0x1UL << DSI_GHCR_DT2_Pos)              /*!< 0x00000004 */

+#define DSI_GHCR_DT2                  DSI_GHCR_DT2_Msk

+#define DSI_GHCR_DT3_Pos              (3U)

+#define DSI_GHCR_DT3_Msk              (0x1UL << DSI_GHCR_DT3_Pos)              /*!< 0x00000008 */

+#define DSI_GHCR_DT3                  DSI_GHCR_DT3_Msk

+#define DSI_GHCR_DT4_Pos              (4U)

+#define DSI_GHCR_DT4_Msk              (0x1UL << DSI_GHCR_DT4_Pos)              /*!< 0x00000010 */

+#define DSI_GHCR_DT4                  DSI_GHCR_DT4_Msk

+#define DSI_GHCR_DT5_Pos              (5U)

+#define DSI_GHCR_DT5_Msk              (0x1UL << DSI_GHCR_DT5_Pos)              /*!< 0x00000020 */

+#define DSI_GHCR_DT5                  DSI_GHCR_DT5_Msk

+

+#define DSI_GHCR_VCID_Pos             (6U)

+#define DSI_GHCR_VCID_Msk             (0x3UL << DSI_GHCR_VCID_Pos)             /*!< 0x000000C0 */

+#define DSI_GHCR_VCID                 DSI_GHCR_VCID_Msk                        /*!< Channel */

+#define DSI_GHCR_VCID0_Pos            (6U)

+#define DSI_GHCR_VCID0_Msk            (0x1UL << DSI_GHCR_VCID0_Pos)            /*!< 0x00000040 */

+#define DSI_GHCR_VCID0                DSI_GHCR_VCID0_Msk

+#define DSI_GHCR_VCID1_Pos            (7U)

+#define DSI_GHCR_VCID1_Msk            (0x1UL << DSI_GHCR_VCID1_Pos)            /*!< 0x00000080 */

+#define DSI_GHCR_VCID1                DSI_GHCR_VCID1_Msk

+

+#define DSI_GHCR_WCLSB_Pos            (8U)

+#define DSI_GHCR_WCLSB_Msk            (0xFFUL << DSI_GHCR_WCLSB_Pos)           /*!< 0x0000FF00 */

+#define DSI_GHCR_WCLSB                DSI_GHCR_WCLSB_Msk                       /*!< WordCount LSB */

+#define DSI_GHCR_WCLSB0_Pos           (8U)

+#define DSI_GHCR_WCLSB0_Msk           (0x1UL << DSI_GHCR_WCLSB0_Pos)           /*!< 0x00000100 */

+#define DSI_GHCR_WCLSB0               DSI_GHCR_WCLSB0_Msk

+#define DSI_GHCR_WCLSB1_Pos           (9U)

+#define DSI_GHCR_WCLSB1_Msk           (0x1UL << DSI_GHCR_WCLSB1_Pos)           /*!< 0x00000200 */

+#define DSI_GHCR_WCLSB1               DSI_GHCR_WCLSB1_Msk

+#define DSI_GHCR_WCLSB2_Pos           (10U)

+#define DSI_GHCR_WCLSB2_Msk           (0x1UL << DSI_GHCR_WCLSB2_Pos)           /*!< 0x00000400 */

+#define DSI_GHCR_WCLSB2               DSI_GHCR_WCLSB2_Msk

+#define DSI_GHCR_WCLSB3_Pos           (11U)

+#define DSI_GHCR_WCLSB3_Msk           (0x1UL << DSI_GHCR_WCLSB3_Pos)           /*!< 0x00000800 */

+#define DSI_GHCR_WCLSB3               DSI_GHCR_WCLSB3_Msk

+#define DSI_GHCR_WCLSB4_Pos           (12U)

+#define DSI_GHCR_WCLSB4_Msk           (0x1UL << DSI_GHCR_WCLSB4_Pos)           /*!< 0x00001000 */

+#define DSI_GHCR_WCLSB4               DSI_GHCR_WCLSB4_Msk

+#define DSI_GHCR_WCLSB5_Pos           (13U)

+#define DSI_GHCR_WCLSB5_Msk           (0x1UL << DSI_GHCR_WCLSB5_Pos)           /*!< 0x00002000 */

+#define DSI_GHCR_WCLSB5               DSI_GHCR_WCLSB5_Msk

+#define DSI_GHCR_WCLSB6_Pos           (14U)

+#define DSI_GHCR_WCLSB6_Msk           (0x1UL << DSI_GHCR_WCLSB6_Pos)           /*!< 0x00004000 */

+#define DSI_GHCR_WCLSB6               DSI_GHCR_WCLSB6_Msk

+#define DSI_GHCR_WCLSB7_Pos           (15U)

+#define DSI_GHCR_WCLSB7_Msk           (0x1UL << DSI_GHCR_WCLSB7_Pos)           /*!< 0x00008000 */

+#define DSI_GHCR_WCLSB7               DSI_GHCR_WCLSB7_Msk

+

+#define DSI_GHCR_WCMSB_Pos            (16U)

+#define DSI_GHCR_WCMSB_Msk            (0xFFUL << DSI_GHCR_WCMSB_Pos)           /*!< 0x00FF0000 */

+#define DSI_GHCR_WCMSB                DSI_GHCR_WCMSB_Msk                       /*!< WordCount MSB */

+#define DSI_GHCR_WCMSB0_Pos           (16U)

+#define DSI_GHCR_WCMSB0_Msk           (0x1UL << DSI_GHCR_WCMSB0_Pos)           /*!< 0x00010000 */

+#define DSI_GHCR_WCMSB0               DSI_GHCR_WCMSB0_Msk

+#define DSI_GHCR_WCMSB1_Pos           (17U)

+#define DSI_GHCR_WCMSB1_Msk           (0x1UL << DSI_GHCR_WCMSB1_Pos)           /*!< 0x00020000 */

+#define DSI_GHCR_WCMSB1               DSI_GHCR_WCMSB1_Msk

+#define DSI_GHCR_WCMSB2_Pos           (18U)

+#define DSI_GHCR_WCMSB2_Msk           (0x1UL << DSI_GHCR_WCMSB2_Pos)           /*!< 0x00040000 */

+#define DSI_GHCR_WCMSB2               DSI_GHCR_WCMSB2_Msk

+#define DSI_GHCR_WCMSB3_Pos           (19U)

+#define DSI_GHCR_WCMSB3_Msk           (0x1UL << DSI_GHCR_WCMSB3_Pos)           /*!< 0x00080000 */

+#define DSI_GHCR_WCMSB3               DSI_GHCR_WCMSB3_Msk

+#define DSI_GHCR_WCMSB4_Pos           (20U)

+#define DSI_GHCR_WCMSB4_Msk           (0x1UL << DSI_GHCR_WCMSB4_Pos)           /*!< 0x00100000 */

+#define DSI_GHCR_WCMSB4               DSI_GHCR_WCMSB4_Msk

+#define DSI_GHCR_WCMSB5_Pos           (21U)

+#define DSI_GHCR_WCMSB5_Msk           (0x1UL << DSI_GHCR_WCMSB5_Pos)           /*!< 0x00200000 */

+#define DSI_GHCR_WCMSB5               DSI_GHCR_WCMSB5_Msk

+#define DSI_GHCR_WCMSB6_Pos           (22U)

+#define DSI_GHCR_WCMSB6_Msk           (0x1UL << DSI_GHCR_WCMSB6_Pos)           /*!< 0x00400000 */

+#define DSI_GHCR_WCMSB6               DSI_GHCR_WCMSB6_Msk

+#define DSI_GHCR_WCMSB7_Pos           (23U)

+#define DSI_GHCR_WCMSB7_Msk           (0x1UL << DSI_GHCR_WCMSB7_Pos)           /*!< 0x00800000 */

+#define DSI_GHCR_WCMSB7               DSI_GHCR_WCMSB7_Msk

+

+/*******************  Bit definition for DSI_GPDR register  ***************/

+#define DSI_GPDR_DATA1_Pos            (0U)

+#define DSI_GPDR_DATA1_Msk            (0xFFUL << DSI_GPDR_DATA1_Pos)           /*!< 0x000000FF */

+#define DSI_GPDR_DATA1                DSI_GPDR_DATA1_Msk                       /*!< Payload Byte 1 */

+#define DSI_GPDR_DATA1_0              (0x01UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000001 */

+#define DSI_GPDR_DATA1_1              (0x02UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000002 */

+#define DSI_GPDR_DATA1_2              (0x04UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000004 */

+#define DSI_GPDR_DATA1_3              (0x08UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000008 */

+#define DSI_GPDR_DATA1_4              (0x10UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000010 */

+#define DSI_GPDR_DATA1_5              (0x20UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000020 */

+#define DSI_GPDR_DATA1_6              (0x40UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000040 */

+#define DSI_GPDR_DATA1_7              (0x80UL << DSI_GPDR_DATA1_Pos)            /*!< 0x00000080 */

+

+#define DSI_GPDR_DATA2_Pos            (8U)

+#define DSI_GPDR_DATA2_Msk            (0xFFUL << DSI_GPDR_DATA2_Pos)           /*!< 0x0000FF00 */

+#define DSI_GPDR_DATA2                DSI_GPDR_DATA2_Msk                       /*!< Payload Byte 2 */

+#define DSI_GPDR_DATA2_0              (0x01UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00000100 */

+#define DSI_GPDR_DATA2_1              (0x02UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00000200 */

+#define DSI_GPDR_DATA2_2              (0x04UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00000400 */

+#define DSI_GPDR_DATA2_3              (0x08UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00000800 */

+#define DSI_GPDR_DATA2_4              (0x10UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00001000 */

+#define DSI_GPDR_DATA2_5              (0x20UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00002000 */

+#define DSI_GPDR_DATA2_6              (0x40UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00004000 */

+#define DSI_GPDR_DATA2_7              (0x80UL << DSI_GPDR_DATA2_Pos)            /*!< 0x00008000 */

+

+#define DSI_GPDR_DATA3_Pos            (16U)

+#define DSI_GPDR_DATA3_Msk            (0xFFUL << DSI_GPDR_DATA3_Pos)           /*!< 0x00FF0000 */

+#define DSI_GPDR_DATA3                DSI_GPDR_DATA3_Msk                       /*!< Payload Byte 3 */

+#define DSI_GPDR_DATA3_0              (0x01UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00010000 */

+#define DSI_GPDR_DATA3_1              (0x02UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00020000 */

+#define DSI_GPDR_DATA3_2              (0x04UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00040000 */

+#define DSI_GPDR_DATA3_3              (0x08UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00080000 */

+#define DSI_GPDR_DATA3_4              (0x10UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00100000 */

+#define DSI_GPDR_DATA3_5              (0x20UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00200000 */

+#define DSI_GPDR_DATA3_6              (0x40UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00400000 */

+#define DSI_GPDR_DATA3_7              (0x80UL << DSI_GPDR_DATA3_Pos)            /*!< 0x00800000 */

+

+#define DSI_GPDR_DATA4_Pos            (24U)

+#define DSI_GPDR_DATA4_Msk            (0xFFUL << DSI_GPDR_DATA4_Pos)           /*!< 0xFF000000 */

+#define DSI_GPDR_DATA4                DSI_GPDR_DATA4_Msk                       /*!< Payload Byte 4 */

+#define DSI_GPDR_DATA4_0              (0x01UL << DSI_GPDR_DATA4_Pos)            /*!< 0x01000000 */

+#define DSI_GPDR_DATA4_1              (0x02UL << DSI_GPDR_DATA4_Pos)            /*!< 0x02000000 */

+#define DSI_GPDR_DATA4_2              (0x04UL << DSI_GPDR_DATA4_Pos)            /*!< 0x04000000 */

+#define DSI_GPDR_DATA4_3              (0x08UL << DSI_GPDR_DATA4_Pos)            /*!< 0x08000000 */

+#define DSI_GPDR_DATA4_4              (0x10UL << DSI_GPDR_DATA4_Pos)            /*!< 0x10000000 */

+#define DSI_GPDR_DATA4_5              (0x20UL << DSI_GPDR_DATA4_Pos)            /*!< 0x20000000 */

+#define DSI_GPDR_DATA4_6              (0x40UL << DSI_GPDR_DATA4_Pos)            /*!< 0x40000000 */

+#define DSI_GPDR_DATA4_7              (0x80UL << DSI_GPDR_DATA4_Pos)            /*!< 0x80000000 */

+

+/*******************  Bit definition for DSI_GPSR register  ***************/

+#define DSI_GPSR_CMDFE_Pos            (0U)

+#define DSI_GPSR_CMDFE_Msk            (0x1UL << DSI_GPSR_CMDFE_Pos)            /*!< 0x00000001 */

+#define DSI_GPSR_CMDFE                DSI_GPSR_CMDFE_Msk                       /*!< Command FIFO Empty */

+#define DSI_GPSR_CMDFF_Pos            (1U)

+#define DSI_GPSR_CMDFF_Msk            (0x1UL << DSI_GPSR_CMDFF_Pos)            /*!< 0x00000002 */

+#define DSI_GPSR_CMDFF                DSI_GPSR_CMDFF_Msk                       /*!< Command FIFO Full */

+#define DSI_GPSR_PWRFE_Pos            (2U)

+#define DSI_GPSR_PWRFE_Msk            (0x1UL << DSI_GPSR_PWRFE_Pos)            /*!< 0x00000004 */

+#define DSI_GPSR_PWRFE                DSI_GPSR_PWRFE_Msk                       /*!< Payload Write FIFO Empty */

+#define DSI_GPSR_PWRFF_Pos            (3U)

+#define DSI_GPSR_PWRFF_Msk            (0x1UL << DSI_GPSR_PWRFF_Pos)            /*!< 0x00000008 */

+#define DSI_GPSR_PWRFF                DSI_GPSR_PWRFF_Msk                       /*!< Payload Write FIFO Full */

+#define DSI_GPSR_PRDFE_Pos            (4U)

+#define DSI_GPSR_PRDFE_Msk            (0x1UL << DSI_GPSR_PRDFE_Pos)            /*!< 0x00000010 */

+#define DSI_GPSR_PRDFE                DSI_GPSR_PRDFE_Msk                       /*!< Payload Read FIFO Empty */

+#define DSI_GPSR_PRDFF_Pos            (5U)

+#define DSI_GPSR_PRDFF_Msk            (0x1UL << DSI_GPSR_PRDFF_Pos)            /*!< 0x00000020 */

+#define DSI_GPSR_PRDFF                DSI_GPSR_PRDFF_Msk                       /*!< Payload Read FIFO Full */

+#define DSI_GPSR_RCB_Pos              (6U)

+#define DSI_GPSR_RCB_Msk              (0x1UL << DSI_GPSR_RCB_Pos)              /*!< 0x00000040 */

+#define DSI_GPSR_RCB                  DSI_GPSR_RCB_Msk                         /*!< Read Command Busy */

+

+/*******************  Bit definition for DSI_TCCR0 register  **************/

+#define DSI_TCCR0_LPRX_TOCNT_Pos      (0U)

+#define DSI_TCCR0_LPRX_TOCNT_Msk      (0xFFFFUL << DSI_TCCR0_LPRX_TOCNT_Pos)   /*!< 0x0000FFFF */

+#define DSI_TCCR0_LPRX_TOCNT          DSI_TCCR0_LPRX_TOCNT_Msk                 /*!< Low-power Reception Timeout Counter */

+#define DSI_TCCR0_LPRX_TOCNT0_Pos     (0U)

+#define DSI_TCCR0_LPRX_TOCNT0_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT0_Pos)     /*!< 0x00000001 */

+#define DSI_TCCR0_LPRX_TOCNT0         DSI_TCCR0_LPRX_TOCNT0_Msk

+#define DSI_TCCR0_LPRX_TOCNT1_Pos     (1U)

+#define DSI_TCCR0_LPRX_TOCNT1_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT1_Pos)     /*!< 0x00000002 */

+#define DSI_TCCR0_LPRX_TOCNT1         DSI_TCCR0_LPRX_TOCNT1_Msk

+#define DSI_TCCR0_LPRX_TOCNT2_Pos     (2U)

+#define DSI_TCCR0_LPRX_TOCNT2_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT2_Pos)     /*!< 0x00000004 */

+#define DSI_TCCR0_LPRX_TOCNT2         DSI_TCCR0_LPRX_TOCNT2_Msk

+#define DSI_TCCR0_LPRX_TOCNT3_Pos     (3U)

+#define DSI_TCCR0_LPRX_TOCNT3_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT3_Pos)     /*!< 0x00000008 */

+#define DSI_TCCR0_LPRX_TOCNT3         DSI_TCCR0_LPRX_TOCNT3_Msk

+#define DSI_TCCR0_LPRX_TOCNT4_Pos     (4U)

+#define DSI_TCCR0_LPRX_TOCNT4_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT4_Pos)     /*!< 0x00000010 */

+#define DSI_TCCR0_LPRX_TOCNT4         DSI_TCCR0_LPRX_TOCNT4_Msk

+#define DSI_TCCR0_LPRX_TOCNT5_Pos     (5U)

+#define DSI_TCCR0_LPRX_TOCNT5_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT5_Pos)     /*!< 0x00000020 */

+#define DSI_TCCR0_LPRX_TOCNT5         DSI_TCCR0_LPRX_TOCNT5_Msk

+#define DSI_TCCR0_LPRX_TOCNT6_Pos     (6U)

+#define DSI_TCCR0_LPRX_TOCNT6_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT6_Pos)     /*!< 0x00000040 */

+#define DSI_TCCR0_LPRX_TOCNT6         DSI_TCCR0_LPRX_TOCNT6_Msk

+#define DSI_TCCR0_LPRX_TOCNT7_Pos     (7U)

+#define DSI_TCCR0_LPRX_TOCNT7_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT7_Pos)     /*!< 0x00000080 */

+#define DSI_TCCR0_LPRX_TOCNT7         DSI_TCCR0_LPRX_TOCNT7_Msk

+#define DSI_TCCR0_LPRX_TOCNT8_Pos     (8U)

+#define DSI_TCCR0_LPRX_TOCNT8_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT8_Pos)     /*!< 0x00000100 */

+#define DSI_TCCR0_LPRX_TOCNT8         DSI_TCCR0_LPRX_TOCNT8_Msk

+#define DSI_TCCR0_LPRX_TOCNT9_Pos     (9U)

+#define DSI_TCCR0_LPRX_TOCNT9_Msk     (0x1UL << DSI_TCCR0_LPRX_TOCNT9_Pos)     /*!< 0x00000200 */

+#define DSI_TCCR0_LPRX_TOCNT9         DSI_TCCR0_LPRX_TOCNT9_Msk

+#define DSI_TCCR0_LPRX_TOCNT10_Pos    (10U)

+#define DSI_TCCR0_LPRX_TOCNT10_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT10_Pos)    /*!< 0x00000400 */

+#define DSI_TCCR0_LPRX_TOCNT10        DSI_TCCR0_LPRX_TOCNT10_Msk

+#define DSI_TCCR0_LPRX_TOCNT11_Pos    (11U)

+#define DSI_TCCR0_LPRX_TOCNT11_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT11_Pos)    /*!< 0x00000800 */

+#define DSI_TCCR0_LPRX_TOCNT11        DSI_TCCR0_LPRX_TOCNT11_Msk

+#define DSI_TCCR0_LPRX_TOCNT12_Pos    (12U)

+#define DSI_TCCR0_LPRX_TOCNT12_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT12_Pos)    /*!< 0x00001000 */

+#define DSI_TCCR0_LPRX_TOCNT12        DSI_TCCR0_LPRX_TOCNT12_Msk

+#define DSI_TCCR0_LPRX_TOCNT13_Pos    (13U)

+#define DSI_TCCR0_LPRX_TOCNT13_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT13_Pos)    /*!< 0x00002000 */

+#define DSI_TCCR0_LPRX_TOCNT13        DSI_TCCR0_LPRX_TOCNT13_Msk

+#define DSI_TCCR0_LPRX_TOCNT14_Pos    (14U)

+#define DSI_TCCR0_LPRX_TOCNT14_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT14_Pos)    /*!< 0x00004000 */

+#define DSI_TCCR0_LPRX_TOCNT14        DSI_TCCR0_LPRX_TOCNT14_Msk

+#define DSI_TCCR0_LPRX_TOCNT15_Pos    (15U)

+#define DSI_TCCR0_LPRX_TOCNT15_Msk    (0x1UL << DSI_TCCR0_LPRX_TOCNT15_Pos)    /*!< 0x00008000 */

+#define DSI_TCCR0_LPRX_TOCNT15        DSI_TCCR0_LPRX_TOCNT15_Msk

+

+#define DSI_TCCR0_HSTX_TOCNT_Pos      (16U)

+#define DSI_TCCR0_HSTX_TOCNT_Msk      (0xFFFFUL << DSI_TCCR0_HSTX_TOCNT_Pos)   /*!< 0xFFFF0000 */

+#define DSI_TCCR0_HSTX_TOCNT          DSI_TCCR0_HSTX_TOCNT_Msk                 /*!< High-Speed Transmission Timeout Counter */

+#define DSI_TCCR0_HSTX_TOCNT0_Pos     (16U)

+#define DSI_TCCR0_HSTX_TOCNT0_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT0_Pos)     /*!< 0x00010000 */

+#define DSI_TCCR0_HSTX_TOCNT0         DSI_TCCR0_HSTX_TOCNT0_Msk

+#define DSI_TCCR0_HSTX_TOCNT1_Pos     (17U)

+#define DSI_TCCR0_HSTX_TOCNT1_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT1_Pos)     /*!< 0x00020000 */

+#define DSI_TCCR0_HSTX_TOCNT1         DSI_TCCR0_HSTX_TOCNT1_Msk

+#define DSI_TCCR0_HSTX_TOCNT2_Pos     (18U)

+#define DSI_TCCR0_HSTX_TOCNT2_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT2_Pos)     /*!< 0x00040000 */

+#define DSI_TCCR0_HSTX_TOCNT2         DSI_TCCR0_HSTX_TOCNT2_Msk

+#define DSI_TCCR0_HSTX_TOCNT3_Pos     (19U)

+#define DSI_TCCR0_HSTX_TOCNT3_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT3_Pos)     /*!< 0x00080000 */

+#define DSI_TCCR0_HSTX_TOCNT3         DSI_TCCR0_HSTX_TOCNT3_Msk

+#define DSI_TCCR0_HSTX_TOCNT4_Pos     (20U)

+#define DSI_TCCR0_HSTX_TOCNT4_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT4_Pos)     /*!< 0x00100000 */

+#define DSI_TCCR0_HSTX_TOCNT4         DSI_TCCR0_HSTX_TOCNT4_Msk

+#define DSI_TCCR0_HSTX_TOCNT5_Pos     (21U)

+#define DSI_TCCR0_HSTX_TOCNT5_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT5_Pos)     /*!< 0x00200000 */

+#define DSI_TCCR0_HSTX_TOCNT5         DSI_TCCR0_HSTX_TOCNT5_Msk

+#define DSI_TCCR0_HSTX_TOCNT6_Pos     (22U)

+#define DSI_TCCR0_HSTX_TOCNT6_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT6_Pos)     /*!< 0x00400000 */

+#define DSI_TCCR0_HSTX_TOCNT6         DSI_TCCR0_HSTX_TOCNT6_Msk

+#define DSI_TCCR0_HSTX_TOCNT7_Pos     (23U)

+#define DSI_TCCR0_HSTX_TOCNT7_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT7_Pos)     /*!< 0x00800000 */

+#define DSI_TCCR0_HSTX_TOCNT7         DSI_TCCR0_HSTX_TOCNT7_Msk

+#define DSI_TCCR0_HSTX_TOCNT8_Pos     (24U)

+#define DSI_TCCR0_HSTX_TOCNT8_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT8_Pos)     /*!< 0x01000000 */

+#define DSI_TCCR0_HSTX_TOCNT8         DSI_TCCR0_HSTX_TOCNT8_Msk

+#define DSI_TCCR0_HSTX_TOCNT9_Pos     (25U)

+#define DSI_TCCR0_HSTX_TOCNT9_Msk     (0x1UL << DSI_TCCR0_HSTX_TOCNT9_Pos)     /*!< 0x02000000 */

+#define DSI_TCCR0_HSTX_TOCNT9         DSI_TCCR0_HSTX_TOCNT9_Msk

+#define DSI_TCCR0_HSTX_TOCNT10_Pos    (26U)

+#define DSI_TCCR0_HSTX_TOCNT10_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT10_Pos)    /*!< 0x04000000 */

+#define DSI_TCCR0_HSTX_TOCNT10        DSI_TCCR0_HSTX_TOCNT10_Msk

+#define DSI_TCCR0_HSTX_TOCNT11_Pos    (27U)

+#define DSI_TCCR0_HSTX_TOCNT11_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT11_Pos)    /*!< 0x08000000 */

+#define DSI_TCCR0_HSTX_TOCNT11        DSI_TCCR0_HSTX_TOCNT11_Msk

+#define DSI_TCCR0_HSTX_TOCNT12_Pos    (28U)

+#define DSI_TCCR0_HSTX_TOCNT12_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT12_Pos)    /*!< 0x10000000 */

+#define DSI_TCCR0_HSTX_TOCNT12        DSI_TCCR0_HSTX_TOCNT12_Msk

+#define DSI_TCCR0_HSTX_TOCNT13_Pos    (29U)

+#define DSI_TCCR0_HSTX_TOCNT13_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT13_Pos)    /*!< 0x20000000 */

+#define DSI_TCCR0_HSTX_TOCNT13        DSI_TCCR0_HSTX_TOCNT13_Msk

+#define DSI_TCCR0_HSTX_TOCNT14_Pos    (30U)

+#define DSI_TCCR0_HSTX_TOCNT14_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT14_Pos)    /*!< 0x40000000 */

+#define DSI_TCCR0_HSTX_TOCNT14        DSI_TCCR0_HSTX_TOCNT14_Msk

+#define DSI_TCCR0_HSTX_TOCNT15_Pos    (31U)

+#define DSI_TCCR0_HSTX_TOCNT15_Msk    (0x1UL << DSI_TCCR0_HSTX_TOCNT15_Pos)    /*!< 0x80000000 */

+#define DSI_TCCR0_HSTX_TOCNT15        DSI_TCCR0_HSTX_TOCNT15_Msk

+

+/*******************  Bit definition for DSI_TCCR1 register  **************/

+#define DSI_TCCR1_HSRD_TOCNT_Pos      (0U)

+#define DSI_TCCR1_HSRD_TOCNT_Msk      (0xFFFFUL << DSI_TCCR1_HSRD_TOCNT_Pos)   /*!< 0x0000FFFF */

+#define DSI_TCCR1_HSRD_TOCNT          DSI_TCCR1_HSRD_TOCNT_Msk                 /*!< High-Speed Read Timeout Counter */

+#define DSI_TCCR1_HSRD_TOCNT0_Pos     (0U)

+#define DSI_TCCR1_HSRD_TOCNT0_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT0_Pos)     /*!< 0x00000001 */

+#define DSI_TCCR1_HSRD_TOCNT0         DSI_TCCR1_HSRD_TOCNT0_Msk

+#define DSI_TCCR1_HSRD_TOCNT1_Pos     (1U)

+#define DSI_TCCR1_HSRD_TOCNT1_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT1_Pos)     /*!< 0x00000002 */

+#define DSI_TCCR1_HSRD_TOCNT1         DSI_TCCR1_HSRD_TOCNT1_Msk

+#define DSI_TCCR1_HSRD_TOCNT2_Pos     (2U)

+#define DSI_TCCR1_HSRD_TOCNT2_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT2_Pos)     /*!< 0x00000004 */

+#define DSI_TCCR1_HSRD_TOCNT2         DSI_TCCR1_HSRD_TOCNT2_Msk

+#define DSI_TCCR1_HSRD_TOCNT3_Pos     (3U)

+#define DSI_TCCR1_HSRD_TOCNT3_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT3_Pos)     /*!< 0x00000008 */

+#define DSI_TCCR1_HSRD_TOCNT3         DSI_TCCR1_HSRD_TOCNT3_Msk

+#define DSI_TCCR1_HSRD_TOCNT4_Pos     (4U)

+#define DSI_TCCR1_HSRD_TOCNT4_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT4_Pos)     /*!< 0x00000010 */

+#define DSI_TCCR1_HSRD_TOCNT4         DSI_TCCR1_HSRD_TOCNT4_Msk

+#define DSI_TCCR1_HSRD_TOCNT5_Pos     (5U)

+#define DSI_TCCR1_HSRD_TOCNT5_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT5_Pos)     /*!< 0x00000020 */

+#define DSI_TCCR1_HSRD_TOCNT5         DSI_TCCR1_HSRD_TOCNT5_Msk

+#define DSI_TCCR1_HSRD_TOCNT6_Pos     (6U)

+#define DSI_TCCR1_HSRD_TOCNT6_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT6_Pos)     /*!< 0x00000040 */

+#define DSI_TCCR1_HSRD_TOCNT6         DSI_TCCR1_HSRD_TOCNT6_Msk

+#define DSI_TCCR1_HSRD_TOCNT7_Pos     (7U)

+#define DSI_TCCR1_HSRD_TOCNT7_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT7_Pos)     /*!< 0x00000080 */

+#define DSI_TCCR1_HSRD_TOCNT7         DSI_TCCR1_HSRD_TOCNT7_Msk

+#define DSI_TCCR1_HSRD_TOCNT8_Pos     (8U)

+#define DSI_TCCR1_HSRD_TOCNT8_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT8_Pos)     /*!< 0x00000100 */

+#define DSI_TCCR1_HSRD_TOCNT8         DSI_TCCR1_HSRD_TOCNT8_Msk

+#define DSI_TCCR1_HSRD_TOCNT9_Pos     (9U)

+#define DSI_TCCR1_HSRD_TOCNT9_Msk     (0x1UL << DSI_TCCR1_HSRD_TOCNT9_Pos)     /*!< 0x00000200 */

+#define DSI_TCCR1_HSRD_TOCNT9         DSI_TCCR1_HSRD_TOCNT9_Msk

+#define DSI_TCCR1_HSRD_TOCNT10_Pos    (10U)

+#define DSI_TCCR1_HSRD_TOCNT10_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT10_Pos)    /*!< 0x00000400 */

+#define DSI_TCCR1_HSRD_TOCNT10        DSI_TCCR1_HSRD_TOCNT10_Msk

+#define DSI_TCCR1_HSRD_TOCNT11_Pos    (11U)

+#define DSI_TCCR1_HSRD_TOCNT11_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT11_Pos)    /*!< 0x00000800 */

+#define DSI_TCCR1_HSRD_TOCNT11        DSI_TCCR1_HSRD_TOCNT11_Msk

+#define DSI_TCCR1_HSRD_TOCNT12_Pos    (12U)

+#define DSI_TCCR1_HSRD_TOCNT12_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT12_Pos)    /*!< 0x00001000 */

+#define DSI_TCCR1_HSRD_TOCNT12        DSI_TCCR1_HSRD_TOCNT12_Msk

+#define DSI_TCCR1_HSRD_TOCNT13_Pos    (13U)

+#define DSI_TCCR1_HSRD_TOCNT13_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT13_Pos)    /*!< 0x00002000 */

+#define DSI_TCCR1_HSRD_TOCNT13        DSI_TCCR1_HSRD_TOCNT13_Msk

+#define DSI_TCCR1_HSRD_TOCNT14_Pos    (14U)

+#define DSI_TCCR1_HSRD_TOCNT14_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT14_Pos)    /*!< 0x00004000 */

+#define DSI_TCCR1_HSRD_TOCNT14        DSI_TCCR1_HSRD_TOCNT14_Msk

+#define DSI_TCCR1_HSRD_TOCNT15_Pos    (15U)

+#define DSI_TCCR1_HSRD_TOCNT15_Msk    (0x1UL << DSI_TCCR1_HSRD_TOCNT15_Pos)    /*!< 0x00008000 */

+#define DSI_TCCR1_HSRD_TOCNT15        DSI_TCCR1_HSRD_TOCNT15_Msk

+

+/*******************  Bit definition for DSI_TCCR2 register  **************/

+#define DSI_TCCR2_LPRD_TOCNT_Pos      (0U)

+#define DSI_TCCR2_LPRD_TOCNT_Msk      (0xFFFFUL << DSI_TCCR2_LPRD_TOCNT_Pos)   /*!< 0x0000FFFF */

+#define DSI_TCCR2_LPRD_TOCNT          DSI_TCCR2_LPRD_TOCNT_Msk                 /*!< Low-Power Read Timeout Counter */

+#define DSI_TCCR2_LPRD_TOCNT0_Pos     (0U)

+#define DSI_TCCR2_LPRD_TOCNT0_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT0_Pos)     /*!< 0x00000001 */

+#define DSI_TCCR2_LPRD_TOCNT0         DSI_TCCR2_LPRD_TOCNT0_Msk

+#define DSI_TCCR2_LPRD_TOCNT1_Pos     (1U)

+#define DSI_TCCR2_LPRD_TOCNT1_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT1_Pos)     /*!< 0x00000002 */

+#define DSI_TCCR2_LPRD_TOCNT1         DSI_TCCR2_LPRD_TOCNT1_Msk

+#define DSI_TCCR2_LPRD_TOCNT2_Pos     (2U)

+#define DSI_TCCR2_LPRD_TOCNT2_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT2_Pos)     /*!< 0x00000004 */

+#define DSI_TCCR2_LPRD_TOCNT2         DSI_TCCR2_LPRD_TOCNT2_Msk

+#define DSI_TCCR2_LPRD_TOCNT3_Pos     (3U)

+#define DSI_TCCR2_LPRD_TOCNT3_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT3_Pos)     /*!< 0x00000008 */

+#define DSI_TCCR2_LPRD_TOCNT3         DSI_TCCR2_LPRD_TOCNT3_Msk

+#define DSI_TCCR2_LPRD_TOCNT4_Pos     (4U)

+#define DSI_TCCR2_LPRD_TOCNT4_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT4_Pos)     /*!< 0x00000010 */

+#define DSI_TCCR2_LPRD_TOCNT4         DSI_TCCR2_LPRD_TOCNT4_Msk

+#define DSI_TCCR2_LPRD_TOCNT5_Pos     (5U)

+#define DSI_TCCR2_LPRD_TOCNT5_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT5_Pos)     /*!< 0x00000020 */

+#define DSI_TCCR2_LPRD_TOCNT5         DSI_TCCR2_LPRD_TOCNT5_Msk

+#define DSI_TCCR2_LPRD_TOCNT6_Pos     (6U)

+#define DSI_TCCR2_LPRD_TOCNT6_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT6_Pos)     /*!< 0x00000040 */

+#define DSI_TCCR2_LPRD_TOCNT6         DSI_TCCR2_LPRD_TOCNT6_Msk

+#define DSI_TCCR2_LPRD_TOCNT7_Pos     (7U)

+#define DSI_TCCR2_LPRD_TOCNT7_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT7_Pos)     /*!< 0x00000080 */

+#define DSI_TCCR2_LPRD_TOCNT7         DSI_TCCR2_LPRD_TOCNT7_Msk

+#define DSI_TCCR2_LPRD_TOCNT8_Pos     (8U)

+#define DSI_TCCR2_LPRD_TOCNT8_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT8_Pos)     /*!< 0x00000100 */

+#define DSI_TCCR2_LPRD_TOCNT8         DSI_TCCR2_LPRD_TOCNT8_Msk

+#define DSI_TCCR2_LPRD_TOCNT9_Pos     (9U)

+#define DSI_TCCR2_LPRD_TOCNT9_Msk     (0x1UL << DSI_TCCR2_LPRD_TOCNT9_Pos)     /*!< 0x00000200 */

+#define DSI_TCCR2_LPRD_TOCNT9         DSI_TCCR2_LPRD_TOCNT9_Msk

+#define DSI_TCCR2_LPRD_TOCNT10_Pos    (10U)

+#define DSI_TCCR2_LPRD_TOCNT10_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT10_Pos)    /*!< 0x00000400 */

+#define DSI_TCCR2_LPRD_TOCNT10        DSI_TCCR2_LPRD_TOCNT10_Msk

+#define DSI_TCCR2_LPRD_TOCNT11_Pos    (11U)

+#define DSI_TCCR2_LPRD_TOCNT11_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT11_Pos)    /*!< 0x00000800 */

+#define DSI_TCCR2_LPRD_TOCNT11        DSI_TCCR2_LPRD_TOCNT11_Msk

+#define DSI_TCCR2_LPRD_TOCNT12_Pos    (12U)

+#define DSI_TCCR2_LPRD_TOCNT12_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT12_Pos)    /*!< 0x00001000 */

+#define DSI_TCCR2_LPRD_TOCNT12        DSI_TCCR2_LPRD_TOCNT12_Msk

+#define DSI_TCCR2_LPRD_TOCNT13_Pos    (13U)

+#define DSI_TCCR2_LPRD_TOCNT13_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT13_Pos)    /*!< 0x00002000 */

+#define DSI_TCCR2_LPRD_TOCNT13        DSI_TCCR2_LPRD_TOCNT13_Msk

+#define DSI_TCCR2_LPRD_TOCNT14_Pos    (14U)

+#define DSI_TCCR2_LPRD_TOCNT14_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT14_Pos)    /*!< 0x00004000 */

+#define DSI_TCCR2_LPRD_TOCNT14        DSI_TCCR2_LPRD_TOCNT14_Msk

+#define DSI_TCCR2_LPRD_TOCNT15_Pos    (15U)

+#define DSI_TCCR2_LPRD_TOCNT15_Msk    (0x1UL << DSI_TCCR2_LPRD_TOCNT15_Pos)    /*!< 0x00008000 */

+#define DSI_TCCR2_LPRD_TOCNT15        DSI_TCCR2_LPRD_TOCNT15_Msk

+

+/*******************  Bit definition for DSI_TCCR3 register  **************/

+#define DSI_TCCR3_HSWR_TOCNT_Pos      (0U)

+#define DSI_TCCR3_HSWR_TOCNT_Msk      (0xFFFFUL << DSI_TCCR3_HSWR_TOCNT_Pos)   /*!< 0x0000FFFF */

+#define DSI_TCCR3_HSWR_TOCNT          DSI_TCCR3_HSWR_TOCNT_Msk                 /*!< High-Speed Write Timeout Counter */

+#define DSI_TCCR3_HSWR_TOCNT0_Pos     (0U)

+#define DSI_TCCR3_HSWR_TOCNT0_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT0_Pos)     /*!< 0x00000001 */

+#define DSI_TCCR3_HSWR_TOCNT0         DSI_TCCR3_HSWR_TOCNT0_Msk

+#define DSI_TCCR3_HSWR_TOCNT1_Pos     (1U)

+#define DSI_TCCR3_HSWR_TOCNT1_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT1_Pos)     /*!< 0x00000002 */

+#define DSI_TCCR3_HSWR_TOCNT1         DSI_TCCR3_HSWR_TOCNT1_Msk

+#define DSI_TCCR3_HSWR_TOCNT2_Pos     (2U)

+#define DSI_TCCR3_HSWR_TOCNT2_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT2_Pos)     /*!< 0x00000004 */

+#define DSI_TCCR3_HSWR_TOCNT2         DSI_TCCR3_HSWR_TOCNT2_Msk

+#define DSI_TCCR3_HSWR_TOCNT3_Pos     (3U)

+#define DSI_TCCR3_HSWR_TOCNT3_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT3_Pos)     /*!< 0x00000008 */

+#define DSI_TCCR3_HSWR_TOCNT3         DSI_TCCR3_HSWR_TOCNT3_Msk

+#define DSI_TCCR3_HSWR_TOCNT4_Pos     (4U)

+#define DSI_TCCR3_HSWR_TOCNT4_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT4_Pos)     /*!< 0x00000010 */

+#define DSI_TCCR3_HSWR_TOCNT4         DSI_TCCR3_HSWR_TOCNT4_Msk

+#define DSI_TCCR3_HSWR_TOCNT5_Pos     (5U)

+#define DSI_TCCR3_HSWR_TOCNT5_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT5_Pos)     /*!< 0x00000020 */

+#define DSI_TCCR3_HSWR_TOCNT5         DSI_TCCR3_HSWR_TOCNT5_Msk

+#define DSI_TCCR3_HSWR_TOCNT6_Pos     (6U)

+#define DSI_TCCR3_HSWR_TOCNT6_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT6_Pos)     /*!< 0x00000040 */

+#define DSI_TCCR3_HSWR_TOCNT6         DSI_TCCR3_HSWR_TOCNT6_Msk

+#define DSI_TCCR3_HSWR_TOCNT7_Pos     (7U)

+#define DSI_TCCR3_HSWR_TOCNT7_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT7_Pos)     /*!< 0x00000080 */

+#define DSI_TCCR3_HSWR_TOCNT7         DSI_TCCR3_HSWR_TOCNT7_Msk

+#define DSI_TCCR3_HSWR_TOCNT8_Pos     (8U)

+#define DSI_TCCR3_HSWR_TOCNT8_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT8_Pos)     /*!< 0x00000100 */

+#define DSI_TCCR3_HSWR_TOCNT8         DSI_TCCR3_HSWR_TOCNT8_Msk

+#define DSI_TCCR3_HSWR_TOCNT9_Pos     (9U)

+#define DSI_TCCR3_HSWR_TOCNT9_Msk     (0x1UL << DSI_TCCR3_HSWR_TOCNT9_Pos)     /*!< 0x00000200 */

+#define DSI_TCCR3_HSWR_TOCNT9         DSI_TCCR3_HSWR_TOCNT9_Msk

+#define DSI_TCCR3_HSWR_TOCNT10_Pos    (10U)

+#define DSI_TCCR3_HSWR_TOCNT10_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT10_Pos)    /*!< 0x00000400 */

+#define DSI_TCCR3_HSWR_TOCNT10        DSI_TCCR3_HSWR_TOCNT10_Msk

+#define DSI_TCCR3_HSWR_TOCNT11_Pos    (11U)

+#define DSI_TCCR3_HSWR_TOCNT11_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT11_Pos)    /*!< 0x00000800 */

+#define DSI_TCCR3_HSWR_TOCNT11        DSI_TCCR3_HSWR_TOCNT11_Msk

+#define DSI_TCCR3_HSWR_TOCNT12_Pos    (12U)

+#define DSI_TCCR3_HSWR_TOCNT12_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT12_Pos)    /*!< 0x00001000 */

+#define DSI_TCCR3_HSWR_TOCNT12        DSI_TCCR3_HSWR_TOCNT12_Msk

+#define DSI_TCCR3_HSWR_TOCNT13_Pos    (13U)

+#define DSI_TCCR3_HSWR_TOCNT13_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT13_Pos)    /*!< 0x00002000 */

+#define DSI_TCCR3_HSWR_TOCNT13        DSI_TCCR3_HSWR_TOCNT13_Msk

+#define DSI_TCCR3_HSWR_TOCNT14_Pos    (14U)

+#define DSI_TCCR3_HSWR_TOCNT14_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT14_Pos)    /*!< 0x00004000 */

+#define DSI_TCCR3_HSWR_TOCNT14        DSI_TCCR3_HSWR_TOCNT14_Msk

+#define DSI_TCCR3_HSWR_TOCNT15_Pos    (15U)

+#define DSI_TCCR3_HSWR_TOCNT15_Msk    (0x1UL << DSI_TCCR3_HSWR_TOCNT15_Pos)    /*!< 0x00008000 */

+#define DSI_TCCR3_HSWR_TOCNT15        DSI_TCCR3_HSWR_TOCNT15_Msk

+

+#define DSI_TCCR3_PM_Pos              (24U)

+#define DSI_TCCR3_PM_Msk              (0x1UL << DSI_TCCR3_PM_Pos)              /*!< 0x01000000 */

+#define DSI_TCCR3_PM                  DSI_TCCR3_PM_Msk                         /*!< Presp Mode */

+

+/*******************  Bit definition for DSI_TCCR4 register  **************/

+#define DSI_TCCR4_LPWR_TOCNT_Pos      (0U)

+#define DSI_TCCR4_LPWR_TOCNT_Msk      (0xFFFFUL << DSI_TCCR4_LPWR_TOCNT_Pos)   /*!< 0x0000FFFF */

+#define DSI_TCCR4_LPWR_TOCNT          DSI_TCCR4_LPWR_TOCNT_Msk                 /*!< Low-Power Write Timeout Counter */

+#define DSI_TCCR4_LPWR_TOCNT0_Pos     (0U)

+#define DSI_TCCR4_LPWR_TOCNT0_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT0_Pos)     /*!< 0x00000001 */

+#define DSI_TCCR4_LPWR_TOCNT0         DSI_TCCR4_LPWR_TOCNT0_Msk

+#define DSI_TCCR4_LPWR_TOCNT1_Pos     (1U)

+#define DSI_TCCR4_LPWR_TOCNT1_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT1_Pos)     /*!< 0x00000002 */

+#define DSI_TCCR4_LPWR_TOCNT1         DSI_TCCR4_LPWR_TOCNT1_Msk

+#define DSI_TCCR4_LPWR_TOCNT2_Pos     (2U)

+#define DSI_TCCR4_LPWR_TOCNT2_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT2_Pos)     /*!< 0x00000004 */

+#define DSI_TCCR4_LPWR_TOCNT2         DSI_TCCR4_LPWR_TOCNT2_Msk

+#define DSI_TCCR4_LPWR_TOCNT3_Pos     (3U)

+#define DSI_TCCR4_LPWR_TOCNT3_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT3_Pos)     /*!< 0x00000008 */

+#define DSI_TCCR4_LPWR_TOCNT3         DSI_TCCR4_LPWR_TOCNT3_Msk

+#define DSI_TCCR4_LPWR_TOCNT4_Pos     (4U)

+#define DSI_TCCR4_LPWR_TOCNT4_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT4_Pos)     /*!< 0x00000010 */

+#define DSI_TCCR4_LPWR_TOCNT4         DSI_TCCR4_LPWR_TOCNT4_Msk

+#define DSI_TCCR4_LPWR_TOCNT5_Pos     (5U)

+#define DSI_TCCR4_LPWR_TOCNT5_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT5_Pos)     /*!< 0x00000020 */

+#define DSI_TCCR4_LPWR_TOCNT5         DSI_TCCR4_LPWR_TOCNT5_Msk

+#define DSI_TCCR4_LPWR_TOCNT6_Pos     (6U)

+#define DSI_TCCR4_LPWR_TOCNT6_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT6_Pos)     /*!< 0x00000040 */

+#define DSI_TCCR4_LPWR_TOCNT6         DSI_TCCR4_LPWR_TOCNT6_Msk

+#define DSI_TCCR4_LPWR_TOCNT7_Pos     (7U)

+#define DSI_TCCR4_LPWR_TOCNT7_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT7_Pos)     /*!< 0x00000080 */

+#define DSI_TCCR4_LPWR_TOCNT7         DSI_TCCR4_LPWR_TOCNT7_Msk

+#define DSI_TCCR4_LPWR_TOCNT8_Pos     (8U)

+#define DSI_TCCR4_LPWR_TOCNT8_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT8_Pos)     /*!< 0x00000100 */

+#define DSI_TCCR4_LPWR_TOCNT8         DSI_TCCR4_LPWR_TOCNT8_Msk

+#define DSI_TCCR4_LPWR_TOCNT9_Pos     (9U)

+#define DSI_TCCR4_LPWR_TOCNT9_Msk     (0x1UL << DSI_TCCR4_LPWR_TOCNT9_Pos)     /*!< 0x00000200 */

+#define DSI_TCCR4_LPWR_TOCNT9         DSI_TCCR4_LPWR_TOCNT9_Msk

+#define DSI_TCCR4_LPWR_TOCNT10_Pos    (10U)

+#define DSI_TCCR4_LPWR_TOCNT10_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT10_Pos)    /*!< 0x00000400 */

+#define DSI_TCCR4_LPWR_TOCNT10        DSI_TCCR4_LPWR_TOCNT10_Msk

+#define DSI_TCCR4_LPWR_TOCNT11_Pos    (11U)

+#define DSI_TCCR4_LPWR_TOCNT11_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT11_Pos)    /*!< 0x00000800 */

+#define DSI_TCCR4_LPWR_TOCNT11        DSI_TCCR4_LPWR_TOCNT11_Msk

+#define DSI_TCCR4_LPWR_TOCNT12_Pos    (12U)

+#define DSI_TCCR4_LPWR_TOCNT12_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT12_Pos)    /*!< 0x00001000 */

+#define DSI_TCCR4_LPWR_TOCNT12        DSI_TCCR4_LPWR_TOCNT12_Msk

+#define DSI_TCCR4_LPWR_TOCNT13_Pos    (13U)

+#define DSI_TCCR4_LPWR_TOCNT13_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT13_Pos)    /*!< 0x00002000 */

+#define DSI_TCCR4_LPWR_TOCNT13        DSI_TCCR4_LPWR_TOCNT13_Msk

+#define DSI_TCCR4_LPWR_TOCNT14_Pos    (14U)

+#define DSI_TCCR4_LPWR_TOCNT14_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT14_Pos)    /*!< 0x00004000 */

+#define DSI_TCCR4_LPWR_TOCNT14        DSI_TCCR4_LPWR_TOCNT14_Msk

+#define DSI_TCCR4_LPWR_TOCNT15_Pos    (15U)

+#define DSI_TCCR4_LPWR_TOCNT15_Msk    (0x1UL << DSI_TCCR4_LPWR_TOCNT15_Pos)    /*!< 0x00008000 */

+#define DSI_TCCR4_LPWR_TOCNT15        DSI_TCCR4_LPWR_TOCNT15_Msk

+

+/*******************  Bit definition for DSI_TCCR5 register  **************/

+#define DSI_TCCR5_BTA_TOCNT_Pos       (0U)

+#define DSI_TCCR5_BTA_TOCNT_Msk       (0xFFFFUL << DSI_TCCR5_BTA_TOCNT_Pos)    /*!< 0x0000FFFF */

+#define DSI_TCCR5_BTA_TOCNT           DSI_TCCR5_BTA_TOCNT_Msk                  /*!< Bus-Turn-Around Timeout Counter */

+#define DSI_TCCR5_BTA_TOCNT0_Pos      (0U)

+#define DSI_TCCR5_BTA_TOCNT0_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT0_Pos)      /*!< 0x00000001 */

+#define DSI_TCCR5_BTA_TOCNT0          DSI_TCCR5_BTA_TOCNT0_Msk

+#define DSI_TCCR5_BTA_TOCNT1_Pos      (1U)

+#define DSI_TCCR5_BTA_TOCNT1_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT1_Pos)      /*!< 0x00000002 */

+#define DSI_TCCR5_BTA_TOCNT1          DSI_TCCR5_BTA_TOCNT1_Msk

+#define DSI_TCCR5_BTA_TOCNT2_Pos      (2U)

+#define DSI_TCCR5_BTA_TOCNT2_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT2_Pos)      /*!< 0x00000004 */

+#define DSI_TCCR5_BTA_TOCNT2          DSI_TCCR5_BTA_TOCNT2_Msk

+#define DSI_TCCR5_BTA_TOCNT3_Pos      (3U)

+#define DSI_TCCR5_BTA_TOCNT3_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT3_Pos)      /*!< 0x00000008 */

+#define DSI_TCCR5_BTA_TOCNT3          DSI_TCCR5_BTA_TOCNT3_Msk

+#define DSI_TCCR5_BTA_TOCNT4_Pos      (4U)

+#define DSI_TCCR5_BTA_TOCNT4_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT4_Pos)      /*!< 0x00000010 */

+#define DSI_TCCR5_BTA_TOCNT4          DSI_TCCR5_BTA_TOCNT4_Msk

+#define DSI_TCCR5_BTA_TOCNT5_Pos      (5U)

+#define DSI_TCCR5_BTA_TOCNT5_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT5_Pos)      /*!< 0x00000020 */

+#define DSI_TCCR5_BTA_TOCNT5          DSI_TCCR5_BTA_TOCNT5_Msk

+#define DSI_TCCR5_BTA_TOCNT6_Pos      (6U)

+#define DSI_TCCR5_BTA_TOCNT6_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT6_Pos)      /*!< 0x00000040 */

+#define DSI_TCCR5_BTA_TOCNT6          DSI_TCCR5_BTA_TOCNT6_Msk

+#define DSI_TCCR5_BTA_TOCNT7_Pos      (7U)

+#define DSI_TCCR5_BTA_TOCNT7_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT7_Pos)      /*!< 0x00000080 */

+#define DSI_TCCR5_BTA_TOCNT7          DSI_TCCR5_BTA_TOCNT7_Msk

+#define DSI_TCCR5_BTA_TOCNT8_Pos      (8U)

+#define DSI_TCCR5_BTA_TOCNT8_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT8_Pos)      /*!< 0x00000100 */

+#define DSI_TCCR5_BTA_TOCNT8          DSI_TCCR5_BTA_TOCNT8_Msk

+#define DSI_TCCR5_BTA_TOCNT9_Pos      (9U)

+#define DSI_TCCR5_BTA_TOCNT9_Msk      (0x1UL << DSI_TCCR5_BTA_TOCNT9_Pos)      /*!< 0x00000200 */

+#define DSI_TCCR5_BTA_TOCNT9          DSI_TCCR5_BTA_TOCNT9_Msk

+#define DSI_TCCR5_BTA_TOCNT10_Pos     (10U)

+#define DSI_TCCR5_BTA_TOCNT10_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT10_Pos)     /*!< 0x00000400 */

+#define DSI_TCCR5_BTA_TOCNT10         DSI_TCCR5_BTA_TOCNT10_Msk

+#define DSI_TCCR5_BTA_TOCNT11_Pos     (11U)

+#define DSI_TCCR5_BTA_TOCNT11_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT11_Pos)     /*!< 0x00000800 */

+#define DSI_TCCR5_BTA_TOCNT11         DSI_TCCR5_BTA_TOCNT11_Msk

+#define DSI_TCCR5_BTA_TOCNT12_Pos     (12U)

+#define DSI_TCCR5_BTA_TOCNT12_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT12_Pos)     /*!< 0x00001000 */

+#define DSI_TCCR5_BTA_TOCNT12         DSI_TCCR5_BTA_TOCNT12_Msk

+#define DSI_TCCR5_BTA_TOCNT13_Pos     (13U)

+#define DSI_TCCR5_BTA_TOCNT13_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT13_Pos)     /*!< 0x00002000 */

+#define DSI_TCCR5_BTA_TOCNT13         DSI_TCCR5_BTA_TOCNT13_Msk

+#define DSI_TCCR5_BTA_TOCNT14_Pos     (14U)

+#define DSI_TCCR5_BTA_TOCNT14_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT14_Pos)     /*!< 0x00004000 */

+#define DSI_TCCR5_BTA_TOCNT14         DSI_TCCR5_BTA_TOCNT14_Msk

+#define DSI_TCCR5_BTA_TOCNT15_Pos     (15U)

+#define DSI_TCCR5_BTA_TOCNT15_Msk     (0x1UL << DSI_TCCR5_BTA_TOCNT15_Pos)     /*!< 0x00008000 */

+#define DSI_TCCR5_BTA_TOCNT15         DSI_TCCR5_BTA_TOCNT15_Msk

+

+/*******************  Bit definition for DSI_TDCR register  ***************/

+#define DSI_TDCR_3DM                  ((uint32_t)0x00000003U)                  /*!< 3D Mode */

+#define DSI_TDCR_3DM0                 ((uint32_t)0x00000001U)

+#define DSI_TDCR_3DM1                 ((uint32_t)0x00000002U)

+

+#define DSI_TDCR_3DF                  ((uint32_t)0x0000000CU)                  /*!< 3D Format */

+#define DSI_TDCR_3DF0                 ((uint32_t)0x00000004U)

+#define DSI_TDCR_3DF1                 ((uint32_t)0x00000008U)

+

+#define DSI_TDCR_SVS_Pos              (4U)

+#define DSI_TDCR_SVS_Msk              (0x1UL << DSI_TDCR_SVS_Pos)              /*!< 0x00000010 */

+#define DSI_TDCR_SVS                  DSI_TDCR_SVS_Msk                         /*!< Second VSYNC */

+#define DSI_TDCR_RF_Pos               (5U)

+#define DSI_TDCR_RF_Msk               (0x1UL << DSI_TDCR_RF_Pos)               /*!< 0x00000020 */

+#define DSI_TDCR_RF                   DSI_TDCR_RF_Msk                          /*!< Right First */

+#define DSI_TDCR_S3DC_Pos             (16U)

+#define DSI_TDCR_S3DC_Msk             (0x1UL << DSI_TDCR_S3DC_Pos)             /*!< 0x00010000 */

+#define DSI_TDCR_S3DC                 DSI_TDCR_S3DC_Msk                        /*!< Send 3D Control */

+

+/*******************  Bit definition for DSI_CLCR register  ***************/

+#define DSI_CLCR_DPCC_Pos             (0U)

+#define DSI_CLCR_DPCC_Msk             (0x1UL << DSI_CLCR_DPCC_Pos)             /*!< 0x00000001 */

+#define DSI_CLCR_DPCC                 DSI_CLCR_DPCC_Msk                        /*!< D-PHY Clock Control */

+#define DSI_CLCR_ACR_Pos              (1U)

+#define DSI_CLCR_ACR_Msk              (0x1UL << DSI_CLCR_ACR_Pos)              /*!< 0x00000002 */

+#define DSI_CLCR_ACR                  DSI_CLCR_ACR_Msk                         /*!< Automatic Clocklane Control */

+

+/*******************  Bit definition for DSI_CLTCR register  **************/

+#define DSI_CLTCR_LP2HS_TIME_Pos      (0U)

+#define DSI_CLTCR_LP2HS_TIME_Msk      (0x3FFUL << DSI_CLTCR_LP2HS_TIME_Pos)    /*!< 0x000003FF */

+#define DSI_CLTCR_LP2HS_TIME          DSI_CLTCR_LP2HS_TIME_Msk                 /*!< Low-Power to High-Speed Time */

+#define DSI_CLTCR_LP2HS_TIME0_Pos     (0U)

+#define DSI_CLTCR_LP2HS_TIME0_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME0_Pos)     /*!< 0x00000001 */

+#define DSI_CLTCR_LP2HS_TIME0         DSI_CLTCR_LP2HS_TIME0_Msk

+#define DSI_CLTCR_LP2HS_TIME1_Pos     (1U)

+#define DSI_CLTCR_LP2HS_TIME1_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME1_Pos)     /*!< 0x00000002 */

+#define DSI_CLTCR_LP2HS_TIME1         DSI_CLTCR_LP2HS_TIME1_Msk

+#define DSI_CLTCR_LP2HS_TIME2_Pos     (2U)

+#define DSI_CLTCR_LP2HS_TIME2_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME2_Pos)     /*!< 0x00000004 */

+#define DSI_CLTCR_LP2HS_TIME2         DSI_CLTCR_LP2HS_TIME2_Msk

+#define DSI_CLTCR_LP2HS_TIME3_Pos     (3U)

+#define DSI_CLTCR_LP2HS_TIME3_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME3_Pos)     /*!< 0x00000008 */

+#define DSI_CLTCR_LP2HS_TIME3         DSI_CLTCR_LP2HS_TIME3_Msk

+#define DSI_CLTCR_LP2HS_TIME4_Pos     (4U)

+#define DSI_CLTCR_LP2HS_TIME4_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME4_Pos)     /*!< 0x00000010 */

+#define DSI_CLTCR_LP2HS_TIME4         DSI_CLTCR_LP2HS_TIME4_Msk

+#define DSI_CLTCR_LP2HS_TIME5_Pos     (5U)

+#define DSI_CLTCR_LP2HS_TIME5_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME5_Pos)     /*!< 0x00000020 */

+#define DSI_CLTCR_LP2HS_TIME5         DSI_CLTCR_LP2HS_TIME5_Msk

+#define DSI_CLTCR_LP2HS_TIME6_Pos     (6U)

+#define DSI_CLTCR_LP2HS_TIME6_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME6_Pos)     /*!< 0x00000040 */

+#define DSI_CLTCR_LP2HS_TIME6         DSI_CLTCR_LP2HS_TIME6_Msk

+#define DSI_CLTCR_LP2HS_TIME7_Pos     (7U)

+#define DSI_CLTCR_LP2HS_TIME7_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME7_Pos)     /*!< 0x00000080 */

+#define DSI_CLTCR_LP2HS_TIME7         DSI_CLTCR_LP2HS_TIME7_Msk

+#define DSI_CLTCR_LP2HS_TIME8_Pos     (8U)

+#define DSI_CLTCR_LP2HS_TIME8_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME8_Pos)     /*!< 0x00000100 */

+#define DSI_CLTCR_LP2HS_TIME8         DSI_CLTCR_LP2HS_TIME8_Msk

+#define DSI_CLTCR_LP2HS_TIME9_Pos     (9U)

+#define DSI_CLTCR_LP2HS_TIME9_Msk     (0x1UL << DSI_CLTCR_LP2HS_TIME9_Pos)     /*!< 0x00000200 */

+#define DSI_CLTCR_LP2HS_TIME9         DSI_CLTCR_LP2HS_TIME9_Msk

+

+#define DSI_CLTCR_HS2LP_TIME_Pos      (16U)

+#define DSI_CLTCR_HS2LP_TIME_Msk      (0x3FFUL << DSI_CLTCR_HS2LP_TIME_Pos)    /*!< 0x03FF0000 */

+#define DSI_CLTCR_HS2LP_TIME          DSI_CLTCR_HS2LP_TIME_Msk                 /*!< High-Speed to Low-Power Time */

+#define DSI_CLTCR_HS2LP_TIME0_Pos     (16U)

+#define DSI_CLTCR_HS2LP_TIME0_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME0_Pos)     /*!< 0x00010000 */

+#define DSI_CLTCR_HS2LP_TIME0         DSI_CLTCR_HS2LP_TIME0_Msk

+#define DSI_CLTCR_HS2LP_TIME1_Pos     (17U)

+#define DSI_CLTCR_HS2LP_TIME1_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME1_Pos)     /*!< 0x00020000 */

+#define DSI_CLTCR_HS2LP_TIME1         DSI_CLTCR_HS2LP_TIME1_Msk

+#define DSI_CLTCR_HS2LP_TIME2_Pos     (18U)

+#define DSI_CLTCR_HS2LP_TIME2_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME2_Pos)     /*!< 0x00040000 */

+#define DSI_CLTCR_HS2LP_TIME2         DSI_CLTCR_HS2LP_TIME2_Msk

+#define DSI_CLTCR_HS2LP_TIME3_Pos     (19U)

+#define DSI_CLTCR_HS2LP_TIME3_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME3_Pos)     /*!< 0x00080000 */

+#define DSI_CLTCR_HS2LP_TIME3         DSI_CLTCR_HS2LP_TIME3_Msk

+#define DSI_CLTCR_HS2LP_TIME4_Pos     (20U)

+#define DSI_CLTCR_HS2LP_TIME4_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME4_Pos)     /*!< 0x00100000 */

+#define DSI_CLTCR_HS2LP_TIME4         DSI_CLTCR_HS2LP_TIME4_Msk

+#define DSI_CLTCR_HS2LP_TIME5_Pos     (21U)

+#define DSI_CLTCR_HS2LP_TIME5_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME5_Pos)     /*!< 0x00200000 */

+#define DSI_CLTCR_HS2LP_TIME5         DSI_CLTCR_HS2LP_TIME5_Msk

+#define DSI_CLTCR_HS2LP_TIME6_Pos     (22U)

+#define DSI_CLTCR_HS2LP_TIME6_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME6_Pos)     /*!< 0x00400000 */

+#define DSI_CLTCR_HS2LP_TIME6         DSI_CLTCR_HS2LP_TIME6_Msk

+#define DSI_CLTCR_HS2LP_TIME7_Pos     (23U)

+#define DSI_CLTCR_HS2LP_TIME7_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME7_Pos)     /*!< 0x00800000 */

+#define DSI_CLTCR_HS2LP_TIME7         DSI_CLTCR_HS2LP_TIME7_Msk

+#define DSI_CLTCR_HS2LP_TIME8_Pos     (24U)

+#define DSI_CLTCR_HS2LP_TIME8_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME8_Pos)     /*!< 0x01000000 */

+#define DSI_CLTCR_HS2LP_TIME8         DSI_CLTCR_HS2LP_TIME8_Msk

+#define DSI_CLTCR_HS2LP_TIME9_Pos     (25U)

+#define DSI_CLTCR_HS2LP_TIME9_Msk     (0x1UL << DSI_CLTCR_HS2LP_TIME9_Pos)     /*!< 0x02000000 */

+#define DSI_CLTCR_HS2LP_TIME9         DSI_CLTCR_HS2LP_TIME9_Msk

+

+/*******************  Bit definition for DSI_DLTCR register  **************/

+#define DSI_DLTCR_MRD_TIME_Pos        (0U)

+#define DSI_DLTCR_MRD_TIME_Msk        (0x7FFFUL << DSI_DLTCR_MRD_TIME_Pos)     /*!< 0x00007FFF */

+#define DSI_DLTCR_MRD_TIME            DSI_DLTCR_MRD_TIME_Msk                   /*!< Maximum Read Time */

+#define DSI_DLTCR_MRD_TIME0_Pos       (0U)

+#define DSI_DLTCR_MRD_TIME0_Msk       (0x1UL << DSI_DLTCR_MRD_TIME0_Pos)       /*!< 0x00000001 */

+#define DSI_DLTCR_MRD_TIME0           DSI_DLTCR_MRD_TIME0_Msk

+#define DSI_DLTCR_MRD_TIME1_Pos       (1U)

+#define DSI_DLTCR_MRD_TIME1_Msk       (0x1UL << DSI_DLTCR_MRD_TIME1_Pos)       /*!< 0x00000002 */

+#define DSI_DLTCR_MRD_TIME1           DSI_DLTCR_MRD_TIME1_Msk

+#define DSI_DLTCR_MRD_TIME2_Pos       (2U)

+#define DSI_DLTCR_MRD_TIME2_Msk       (0x1UL << DSI_DLTCR_MRD_TIME2_Pos)       /*!< 0x00000004 */

+#define DSI_DLTCR_MRD_TIME2           DSI_DLTCR_MRD_TIME2_Msk

+#define DSI_DLTCR_MRD_TIME3_Pos       (3U)

+#define DSI_DLTCR_MRD_TIME3_Msk       (0x1UL << DSI_DLTCR_MRD_TIME3_Pos)       /*!< 0x00000008 */

+#define DSI_DLTCR_MRD_TIME3           DSI_DLTCR_MRD_TIME3_Msk

+#define DSI_DLTCR_MRD_TIME4_Pos       (4U)

+#define DSI_DLTCR_MRD_TIME4_Msk       (0x1UL << DSI_DLTCR_MRD_TIME4_Pos)       /*!< 0x00000010 */

+#define DSI_DLTCR_MRD_TIME4           DSI_DLTCR_MRD_TIME4_Msk

+#define DSI_DLTCR_MRD_TIME5_Pos       (5U)

+#define DSI_DLTCR_MRD_TIME5_Msk       (0x1UL << DSI_DLTCR_MRD_TIME5_Pos)       /*!< 0x00000020 */

+#define DSI_DLTCR_MRD_TIME5           DSI_DLTCR_MRD_TIME5_Msk

+#define DSI_DLTCR_MRD_TIME6_Pos       (6U)

+#define DSI_DLTCR_MRD_TIME6_Msk       (0x1UL << DSI_DLTCR_MRD_TIME6_Pos)       /*!< 0x00000040 */

+#define DSI_DLTCR_MRD_TIME6           DSI_DLTCR_MRD_TIME6_Msk

+#define DSI_DLTCR_MRD_TIME7_Pos       (7U)

+#define DSI_DLTCR_MRD_TIME7_Msk       (0x1UL << DSI_DLTCR_MRD_TIME7_Pos)       /*!< 0x00000080 */

+#define DSI_DLTCR_MRD_TIME7           DSI_DLTCR_MRD_TIME7_Msk

+#define DSI_DLTCR_MRD_TIME8_Pos       (8U)

+#define DSI_DLTCR_MRD_TIME8_Msk       (0x1UL << DSI_DLTCR_MRD_TIME8_Pos)       /*!< 0x00000100 */

+#define DSI_DLTCR_MRD_TIME8           DSI_DLTCR_MRD_TIME8_Msk

+#define DSI_DLTCR_MRD_TIME9_Pos       (9U)

+#define DSI_DLTCR_MRD_TIME9_Msk       (0x1UL << DSI_DLTCR_MRD_TIME9_Pos)       /*!< 0x00000200 */

+#define DSI_DLTCR_MRD_TIME9           DSI_DLTCR_MRD_TIME9_Msk

+#define DSI_DLTCR_MRD_TIME10_Pos      (10U)

+#define DSI_DLTCR_MRD_TIME10_Msk      (0x1UL << DSI_DLTCR_MRD_TIME10_Pos)      /*!< 0x00000400 */

+#define DSI_DLTCR_MRD_TIME10          DSI_DLTCR_MRD_TIME10_Msk

+#define DSI_DLTCR_MRD_TIME11_Pos      (11U)

+#define DSI_DLTCR_MRD_TIME11_Msk      (0x1UL << DSI_DLTCR_MRD_TIME11_Pos)      /*!< 0x00000800 */

+#define DSI_DLTCR_MRD_TIME11          DSI_DLTCR_MRD_TIME11_Msk

+#define DSI_DLTCR_MRD_TIME12_Pos      (12U)

+#define DSI_DLTCR_MRD_TIME12_Msk      (0x1UL << DSI_DLTCR_MRD_TIME12_Pos)      /*!< 0x00001000 */

+#define DSI_DLTCR_MRD_TIME12          DSI_DLTCR_MRD_TIME12_Msk

+#define DSI_DLTCR_MRD_TIME13_Pos      (13U)

+#define DSI_DLTCR_MRD_TIME13_Msk      (0x1UL << DSI_DLTCR_MRD_TIME13_Pos)      /*!< 0x00002000 */

+#define DSI_DLTCR_MRD_TIME13          DSI_DLTCR_MRD_TIME13_Msk

+#define DSI_DLTCR_MRD_TIME14_Pos      (14U)

+#define DSI_DLTCR_MRD_TIME14_Msk      (0x1UL << DSI_DLTCR_MRD_TIME14_Pos)      /*!< 0x00004000 */

+#define DSI_DLTCR_MRD_TIME14          DSI_DLTCR_MRD_TIME14_Msk

+

+#define DSI_DLTCR_LP2HS_TIME_Pos      (16U)

+#define DSI_DLTCR_LP2HS_TIME_Msk      (0xFFUL << DSI_DLTCR_LP2HS_TIME_Pos)     /*!< 0x00FF0000 */

+#define DSI_DLTCR_LP2HS_TIME          DSI_DLTCR_LP2HS_TIME_Msk                 /*!< Low-Power To High-Speed Time */

+#define DSI_DLTCR_LP2HS_TIME0_Pos     (16U)

+#define DSI_DLTCR_LP2HS_TIME0_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME0_Pos)     /*!< 0x00010000 */

+#define DSI_DLTCR_LP2HS_TIME0         DSI_DLTCR_LP2HS_TIME0_Msk

+#define DSI_DLTCR_LP2HS_TIME1_Pos     (17U)

+#define DSI_DLTCR_LP2HS_TIME1_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME1_Pos)     /*!< 0x00020000 */

+#define DSI_DLTCR_LP2HS_TIME1         DSI_DLTCR_LP2HS_TIME1_Msk

+#define DSI_DLTCR_LP2HS_TIME2_Pos     (18U)

+#define DSI_DLTCR_LP2HS_TIME2_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME2_Pos)     /*!< 0x00040000 */

+#define DSI_DLTCR_LP2HS_TIME2         DSI_DLTCR_LP2HS_TIME2_Msk

+#define DSI_DLTCR_LP2HS_TIME3_Pos     (19U)

+#define DSI_DLTCR_LP2HS_TIME3_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME3_Pos)     /*!< 0x00080000 */

+#define DSI_DLTCR_LP2HS_TIME3         DSI_DLTCR_LP2HS_TIME3_Msk

+#define DSI_DLTCR_LP2HS_TIME4_Pos     (20U)

+#define DSI_DLTCR_LP2HS_TIME4_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME4_Pos)     /*!< 0x00100000 */

+#define DSI_DLTCR_LP2HS_TIME4         DSI_DLTCR_LP2HS_TIME4_Msk

+#define DSI_DLTCR_LP2HS_TIME5_Pos     (21U)

+#define DSI_DLTCR_LP2HS_TIME5_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME5_Pos)     /*!< 0x00200000 */

+#define DSI_DLTCR_LP2HS_TIME5         DSI_DLTCR_LP2HS_TIME5_Msk

+#define DSI_DLTCR_LP2HS_TIME6_Pos     (22U)

+#define DSI_DLTCR_LP2HS_TIME6_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME6_Pos)     /*!< 0x00400000 */

+#define DSI_DLTCR_LP2HS_TIME6         DSI_DLTCR_LP2HS_TIME6_Msk

+#define DSI_DLTCR_LP2HS_TIME7_Pos     (23U)

+#define DSI_DLTCR_LP2HS_TIME7_Msk     (0x1UL << DSI_DLTCR_LP2HS_TIME7_Pos)     /*!< 0x00800000 */

+#define DSI_DLTCR_LP2HS_TIME7         DSI_DLTCR_LP2HS_TIME7_Msk

+

+#define DSI_DLTCR_HS2LP_TIME_Pos      (24U)

+#define DSI_DLTCR_HS2LP_TIME_Msk      (0xFFUL << DSI_DLTCR_HS2LP_TIME_Pos)     /*!< 0xFF000000 */

+#define DSI_DLTCR_HS2LP_TIME          DSI_DLTCR_HS2LP_TIME_Msk                 /*!< High-Speed To Low-Power Time */

+#define DSI_DLTCR_HS2LP_TIME0_Pos     (24U)

+#define DSI_DLTCR_HS2LP_TIME0_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME0_Pos)     /*!< 0x01000000 */

+#define DSI_DLTCR_HS2LP_TIME0         DSI_DLTCR_HS2LP_TIME0_Msk

+#define DSI_DLTCR_HS2LP_TIME1_Pos     (25U)

+#define DSI_DLTCR_HS2LP_TIME1_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME1_Pos)     /*!< 0x02000000 */

+#define DSI_DLTCR_HS2LP_TIME1         DSI_DLTCR_HS2LP_TIME1_Msk

+#define DSI_DLTCR_HS2LP_TIME2_Pos     (26U)

+#define DSI_DLTCR_HS2LP_TIME2_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME2_Pos)     /*!< 0x04000000 */

+#define DSI_DLTCR_HS2LP_TIME2         DSI_DLTCR_HS2LP_TIME2_Msk

+#define DSI_DLTCR_HS2LP_TIME3_Pos     (27U)

+#define DSI_DLTCR_HS2LP_TIME3_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME3_Pos)     /*!< 0x08000000 */

+#define DSI_DLTCR_HS2LP_TIME3         DSI_DLTCR_HS2LP_TIME3_Msk

+#define DSI_DLTCR_HS2LP_TIME4_Pos     (28U)

+#define DSI_DLTCR_HS2LP_TIME4_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME4_Pos)     /*!< 0x10000000 */

+#define DSI_DLTCR_HS2LP_TIME4         DSI_DLTCR_HS2LP_TIME4_Msk

+#define DSI_DLTCR_HS2LP_TIME5_Pos     (29U)

+#define DSI_DLTCR_HS2LP_TIME5_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME5_Pos)     /*!< 0x20000000 */

+#define DSI_DLTCR_HS2LP_TIME5         DSI_DLTCR_HS2LP_TIME5_Msk

+#define DSI_DLTCR_HS2LP_TIME6_Pos     (30U)

+#define DSI_DLTCR_HS2LP_TIME6_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME6_Pos)     /*!< 0x40000000 */

+#define DSI_DLTCR_HS2LP_TIME6         DSI_DLTCR_HS2LP_TIME6_Msk

+#define DSI_DLTCR_HS2LP_TIME7_Pos     (31U)

+#define DSI_DLTCR_HS2LP_TIME7_Msk     (0x1UL << DSI_DLTCR_HS2LP_TIME7_Pos)     /*!< 0x80000000 */

+#define DSI_DLTCR_HS2LP_TIME7         DSI_DLTCR_HS2LP_TIME7_Msk

+

+/*******************  Bit definition for DSI_PCTLR register  **************/

+#define DSI_PCTLR_DEN_Pos             (1U)

+#define DSI_PCTLR_DEN_Msk             (0x1UL << DSI_PCTLR_DEN_Pos)             /*!< 0x00000002 */

+#define DSI_PCTLR_DEN                 DSI_PCTLR_DEN_Msk                        /*!< Digital Enable */

+#define DSI_PCTLR_CKE_Pos             (2U)

+#define DSI_PCTLR_CKE_Msk             (0x1UL << DSI_PCTLR_CKE_Pos)             /*!< 0x00000004 */

+#define DSI_PCTLR_CKE                 DSI_PCTLR_CKE_Msk                        /*!< Clock Enable */

+

+/*******************  Bit definition for DSI_PCONFR register  *************/

+#define DSI_PCONFR_NL_Pos             (0U)

+#define DSI_PCONFR_NL_Msk             (0x3UL << DSI_PCONFR_NL_Pos)             /*!< 0x00000003 */

+#define DSI_PCONFR_NL                 DSI_PCONFR_NL_Msk                        /*!< Number of Lanes */

+#define DSI_PCONFR_NL0_Pos            (0U)

+#define DSI_PCONFR_NL0_Msk            (0x1UL << DSI_PCONFR_NL0_Pos)            /*!< 0x00000001 */

+#define DSI_PCONFR_NL0                DSI_PCONFR_NL0_Msk

+#define DSI_PCONFR_NL1_Pos            (1U)

+#define DSI_PCONFR_NL1_Msk            (0x1UL << DSI_PCONFR_NL1_Pos)            /*!< 0x00000002 */

+#define DSI_PCONFR_NL1                DSI_PCONFR_NL1_Msk

+

+#define DSI_PCONFR_SW_TIME_Pos        (8U)

+#define DSI_PCONFR_SW_TIME_Msk        (0xFFUL << DSI_PCONFR_SW_TIME_Pos)       /*!< 0x0000FF00 */

+#define DSI_PCONFR_SW_TIME            DSI_PCONFR_SW_TIME_Msk                   /*!< Stop Wait Time */

+#define DSI_PCONFR_SW_TIME0_Pos       (8U)

+#define DSI_PCONFR_SW_TIME0_Msk       (0x1UL << DSI_PCONFR_SW_TIME0_Pos)       /*!< 0x00000100 */

+#define DSI_PCONFR_SW_TIME0           DSI_PCONFR_SW_TIME0_Msk

+#define DSI_PCONFR_SW_TIME1_Pos       (9U)

+#define DSI_PCONFR_SW_TIME1_Msk       (0x1UL << DSI_PCONFR_SW_TIME1_Pos)       /*!< 0x00000200 */

+#define DSI_PCONFR_SW_TIME1           DSI_PCONFR_SW_TIME1_Msk

+#define DSI_PCONFR_SW_TIME2_Pos       (10U)

+#define DSI_PCONFR_SW_TIME2_Msk       (0x1UL << DSI_PCONFR_SW_TIME2_Pos)       /*!< 0x00000400 */

+#define DSI_PCONFR_SW_TIME2           DSI_PCONFR_SW_TIME2_Msk

+#define DSI_PCONFR_SW_TIME3_Pos       (11U)

+#define DSI_PCONFR_SW_TIME3_Msk       (0x1UL << DSI_PCONFR_SW_TIME3_Pos)       /*!< 0x00000800 */

+#define DSI_PCONFR_SW_TIME3           DSI_PCONFR_SW_TIME3_Msk

+#define DSI_PCONFR_SW_TIME4_Pos       (12U)

+#define DSI_PCONFR_SW_TIME4_Msk       (0x1UL << DSI_PCONFR_SW_TIME4_Pos)       /*!< 0x00001000 */

+#define DSI_PCONFR_SW_TIME4           DSI_PCONFR_SW_TIME4_Msk

+#define DSI_PCONFR_SW_TIME5_Pos       (13U)

+#define DSI_PCONFR_SW_TIME5_Msk       (0x1UL << DSI_PCONFR_SW_TIME5_Pos)       /*!< 0x00002000 */

+#define DSI_PCONFR_SW_TIME5           DSI_PCONFR_SW_TIME5_Msk

+#define DSI_PCONFR_SW_TIME6_Pos       (14U)

+#define DSI_PCONFR_SW_TIME6_Msk       (0x1UL << DSI_PCONFR_SW_TIME6_Pos)       /*!< 0x00004000 */

+#define DSI_PCONFR_SW_TIME6           DSI_PCONFR_SW_TIME6_Msk

+#define DSI_PCONFR_SW_TIME7_Pos       (15U)

+#define DSI_PCONFR_SW_TIME7_Msk       (0x1UL << DSI_PCONFR_SW_TIME7_Pos)       /*!< 0x00008000 */

+#define DSI_PCONFR_SW_TIME7           DSI_PCONFR_SW_TIME7_Msk

+

+/*******************  Bit definition for DSI_PUCR register  ***************/

+#define DSI_PUCR_URCL_Pos             (0U)

+#define DSI_PUCR_URCL_Msk             (0x1UL << DSI_PUCR_URCL_Pos)             /*!< 0x00000001 */

+#define DSI_PUCR_URCL                 DSI_PUCR_URCL_Msk                        /*!< ULPS Request on Clock Lane */

+#define DSI_PUCR_UECL_Pos             (1U)

+#define DSI_PUCR_UECL_Msk             (0x1UL << DSI_PUCR_UECL_Pos)             /*!< 0x00000002 */

+#define DSI_PUCR_UECL                 DSI_PUCR_UECL_Msk                        /*!< ULPS Exit on Clock Lane */

+#define DSI_PUCR_URDL_Pos             (2U)

+#define DSI_PUCR_URDL_Msk             (0x1UL << DSI_PUCR_URDL_Pos)             /*!< 0x00000004 */

+#define DSI_PUCR_URDL                 DSI_PUCR_URDL_Msk                        /*!< ULPS Request on Data Lane */

+#define DSI_PUCR_UEDL_Pos             (3U)

+#define DSI_PUCR_UEDL_Msk             (0x1UL << DSI_PUCR_UEDL_Pos)             /*!< 0x00000008 */

+#define DSI_PUCR_UEDL                 DSI_PUCR_UEDL_Msk                        /*!< ULPS Exit on Data Lane */

+

+/*******************  Bit definition for DSI_PTTCR register  **************/

+#define DSI_PTTCR_TX_TRIG_Pos         (0U)

+#define DSI_PTTCR_TX_TRIG_Msk         (0xFUL << DSI_PTTCR_TX_TRIG_Pos)         /*!< 0x0000000F */

+#define DSI_PTTCR_TX_TRIG             DSI_PTTCR_TX_TRIG_Msk                    /*!< Transmission Trigger */

+#define DSI_PTTCR_TX_TRIG0_Pos        (0U)

+#define DSI_PTTCR_TX_TRIG0_Msk        (0x1UL << DSI_PTTCR_TX_TRIG0_Pos)        /*!< 0x00000001 */

+#define DSI_PTTCR_TX_TRIG0            DSI_PTTCR_TX_TRIG0_Msk

+#define DSI_PTTCR_TX_TRIG1_Pos        (1U)

+#define DSI_PTTCR_TX_TRIG1_Msk        (0x1UL << DSI_PTTCR_TX_TRIG1_Pos)        /*!< 0x00000002 */

+#define DSI_PTTCR_TX_TRIG1            DSI_PTTCR_TX_TRIG1_Msk

+#define DSI_PTTCR_TX_TRIG2_Pos        (2U)

+#define DSI_PTTCR_TX_TRIG2_Msk        (0x1UL << DSI_PTTCR_TX_TRIG2_Pos)        /*!< 0x00000004 */

+#define DSI_PTTCR_TX_TRIG2            DSI_PTTCR_TX_TRIG2_Msk

+#define DSI_PTTCR_TX_TRIG3_Pos        (3U)

+#define DSI_PTTCR_TX_TRIG3_Msk        (0x1UL << DSI_PTTCR_TX_TRIG3_Pos)        /*!< 0x00000008 */

+#define DSI_PTTCR_TX_TRIG3            DSI_PTTCR_TX_TRIG3_Msk

+

+/*******************  Bit definition for DSI_PSR register  ****************/

+#define DSI_PSR_PD_Pos                (1U)

+#define DSI_PSR_PD_Msk                (0x1UL << DSI_PSR_PD_Pos)                /*!< 0x00000002 */

+#define DSI_PSR_PD                    DSI_PSR_PD_Msk                           /*!< PHY Direction */

+#define DSI_PSR_PSSC_Pos              (2U)

+#define DSI_PSR_PSSC_Msk              (0x1UL << DSI_PSR_PSSC_Pos)              /*!< 0x00000004 */

+#define DSI_PSR_PSSC                  DSI_PSR_PSSC_Msk                         /*!< PHY Stop State Clock lane */

+#define DSI_PSR_UANC_Pos              (3U)

+#define DSI_PSR_UANC_Msk              (0x1UL << DSI_PSR_UANC_Pos)              /*!< 0x00000008 */

+#define DSI_PSR_UANC                  DSI_PSR_UANC_Msk                         /*!< ULPS Active Not Clock lane */

+#define DSI_PSR_PSS0_Pos              (4U)

+#define DSI_PSR_PSS0_Msk              (0x1UL << DSI_PSR_PSS0_Pos)              /*!< 0x00000010 */

+#define DSI_PSR_PSS0                  DSI_PSR_PSS0_Msk                         /*!< PHY Stop State lane 0 */

+#define DSI_PSR_UAN0_Pos              (5U)

+#define DSI_PSR_UAN0_Msk              (0x1UL << DSI_PSR_UAN0_Pos)              /*!< 0x00000020 */

+#define DSI_PSR_UAN0                  DSI_PSR_UAN0_Msk                         /*!< ULPS Active Not lane 0 */

+#define DSI_PSR_RUE0_Pos              (6U)

+#define DSI_PSR_RUE0_Msk              (0x1UL << DSI_PSR_RUE0_Pos)              /*!< 0x00000040 */

+#define DSI_PSR_RUE0                  DSI_PSR_RUE0_Msk                         /*!< RX ULPS Escape lane 0 */

+#define DSI_PSR_PSS1_Pos              (7U)

+#define DSI_PSR_PSS1_Msk              (0x1UL << DSI_PSR_PSS1_Pos)              /*!< 0x00000080 */

+#define DSI_PSR_PSS1                  DSI_PSR_PSS1_Msk                         /*!< PHY Stop State lane 1 */

+#define DSI_PSR_UAN1_Pos              (8U)

+#define DSI_PSR_UAN1_Msk              (0x1UL << DSI_PSR_UAN1_Pos)              /*!< 0x00000100 */

+#define DSI_PSR_UAN1                  DSI_PSR_UAN1_Msk                         /*!< ULPS Active Not lane 1 */

+

+/*******************  Bit definition for DSI_ISR0 register  ***************/

+#define DSI_ISR0_AE0_Pos              (0U)

+#define DSI_ISR0_AE0_Msk              (0x1UL << DSI_ISR0_AE0_Pos)              /*!< 0x00000001 */

+#define DSI_ISR0_AE0                  DSI_ISR0_AE0_Msk                         /*!< Acknowledge Error 0 */

+#define DSI_ISR0_AE1_Pos              (1U)

+#define DSI_ISR0_AE1_Msk              (0x1UL << DSI_ISR0_AE1_Pos)              /*!< 0x00000002 */

+#define DSI_ISR0_AE1                  DSI_ISR0_AE1_Msk                         /*!< Acknowledge Error 1 */

+#define DSI_ISR0_AE2_Pos              (2U)

+#define DSI_ISR0_AE2_Msk              (0x1UL << DSI_ISR0_AE2_Pos)              /*!< 0x00000004 */

+#define DSI_ISR0_AE2                  DSI_ISR0_AE2_Msk                         /*!< Acknowledge Error 2 */

+#define DSI_ISR0_AE3_Pos              (3U)

+#define DSI_ISR0_AE3_Msk              (0x1UL << DSI_ISR0_AE3_Pos)              /*!< 0x00000008 */

+#define DSI_ISR0_AE3                  DSI_ISR0_AE3_Msk                         /*!< Acknowledge Error 3 */

+#define DSI_ISR0_AE4_Pos              (4U)

+#define DSI_ISR0_AE4_Msk              (0x1UL << DSI_ISR0_AE4_Pos)              /*!< 0x00000010 */

+#define DSI_ISR0_AE4                  DSI_ISR0_AE4_Msk                         /*!< Acknowledge Error 4 */

+#define DSI_ISR0_AE5_Pos              (5U)

+#define DSI_ISR0_AE5_Msk              (0x1UL << DSI_ISR0_AE5_Pos)              /*!< 0x00000020 */

+#define DSI_ISR0_AE5                  DSI_ISR0_AE5_Msk                         /*!< Acknowledge Error 5 */

+#define DSI_ISR0_AE6_Pos              (6U)

+#define DSI_ISR0_AE6_Msk              (0x1UL << DSI_ISR0_AE6_Pos)              /*!< 0x00000040 */

+#define DSI_ISR0_AE6                  DSI_ISR0_AE6_Msk                         /*!< Acknowledge Error 6 */

+#define DSI_ISR0_AE7_Pos              (7U)

+#define DSI_ISR0_AE7_Msk              (0x1UL << DSI_ISR0_AE7_Pos)              /*!< 0x00000080 */

+#define DSI_ISR0_AE7                  DSI_ISR0_AE7_Msk                         /*!< Acknowledge Error 7 */

+#define DSI_ISR0_AE8_Pos              (8U)

+#define DSI_ISR0_AE8_Msk              (0x1UL << DSI_ISR0_AE8_Pos)              /*!< 0x00000100 */

+#define DSI_ISR0_AE8                  DSI_ISR0_AE8_Msk                         /*!< Acknowledge Error 8 */

+#define DSI_ISR0_AE9_Pos              (9U)

+#define DSI_ISR0_AE9_Msk              (0x1UL << DSI_ISR0_AE9_Pos)              /*!< 0x00000200 */

+#define DSI_ISR0_AE9                  DSI_ISR0_AE9_Msk                         /*!< Acknowledge Error 9 */

+#define DSI_ISR0_AE10_Pos             (10U)

+#define DSI_ISR0_AE10_Msk             (0x1UL << DSI_ISR0_AE10_Pos)             /*!< 0x00000400 */

+#define DSI_ISR0_AE10                 DSI_ISR0_AE10_Msk                        /*!< Acknowledge Error 10 */

+#define DSI_ISR0_AE11_Pos             (11U)

+#define DSI_ISR0_AE11_Msk             (0x1UL << DSI_ISR0_AE11_Pos)             /*!< 0x00000800 */

+#define DSI_ISR0_AE11                 DSI_ISR0_AE11_Msk                        /*!< Acknowledge Error 11 */

+#define DSI_ISR0_AE12_Pos             (12U)

+#define DSI_ISR0_AE12_Msk             (0x1UL << DSI_ISR0_AE12_Pos)             /*!< 0x00001000 */

+#define DSI_ISR0_AE12                 DSI_ISR0_AE12_Msk                        /*!< Acknowledge Error 12 */

+#define DSI_ISR0_AE13_Pos             (13U)

+#define DSI_ISR0_AE13_Msk             (0x1UL << DSI_ISR0_AE13_Pos)             /*!< 0x00002000 */

+#define DSI_ISR0_AE13                 DSI_ISR0_AE13_Msk                        /*!< Acknowledge Error 13 */

+#define DSI_ISR0_AE14_Pos             (14U)

+#define DSI_ISR0_AE14_Msk             (0x1UL << DSI_ISR0_AE14_Pos)             /*!< 0x00004000 */

+#define DSI_ISR0_AE14                 DSI_ISR0_AE14_Msk                        /*!< Acknowledge Error 14 */

+#define DSI_ISR0_AE15_Pos             (15U)

+#define DSI_ISR0_AE15_Msk             (0x1UL << DSI_ISR0_AE15_Pos)             /*!< 0x00008000 */

+#define DSI_ISR0_AE15                 DSI_ISR0_AE15_Msk                        /*!< Acknowledge Error 15 */

+#define DSI_ISR0_PE0_Pos              (16U)

+#define DSI_ISR0_PE0_Msk              (0x1UL << DSI_ISR0_PE0_Pos)              /*!< 0x00010000 */

+#define DSI_ISR0_PE0                  DSI_ISR0_PE0_Msk                         /*!< PHY Error 0 */

+#define DSI_ISR0_PE1_Pos              (17U)

+#define DSI_ISR0_PE1_Msk              (0x1UL << DSI_ISR0_PE1_Pos)              /*!< 0x00020000 */

+#define DSI_ISR0_PE1                  DSI_ISR0_PE1_Msk                         /*!< PHY Error 1 */

+#define DSI_ISR0_PE2_Pos              (18U)

+#define DSI_ISR0_PE2_Msk              (0x1UL << DSI_ISR0_PE2_Pos)              /*!< 0x00040000 */

+#define DSI_ISR0_PE2                  DSI_ISR0_PE2_Msk                         /*!< PHY Error 2 */

+#define DSI_ISR0_PE3_Pos              (19U)

+#define DSI_ISR0_PE3_Msk              (0x1UL << DSI_ISR0_PE3_Pos)              /*!< 0x00080000 */

+#define DSI_ISR0_PE3                  DSI_ISR0_PE3_Msk                         /*!< PHY Error 3 */

+#define DSI_ISR0_PE4_Pos              (20U)

+#define DSI_ISR0_PE4_Msk              (0x1UL << DSI_ISR0_PE4_Pos)              /*!< 0x00100000 */

+#define DSI_ISR0_PE4                  DSI_ISR0_PE4_Msk                         /*!< PHY Error 4 */

+

+/*******************  Bit definition for DSI_ISR1 register  ***************/

+#define DSI_ISR1_TOHSTX_Pos           (0U)

+#define DSI_ISR1_TOHSTX_Msk           (0x1UL << DSI_ISR1_TOHSTX_Pos)           /*!< 0x00000001 */

+#define DSI_ISR1_TOHSTX               DSI_ISR1_TOHSTX_Msk                      /*!< Timeout High-Speed Transmission */

+#define DSI_ISR1_TOLPRX_Pos           (1U)

+#define DSI_ISR1_TOLPRX_Msk           (0x1UL << DSI_ISR1_TOLPRX_Pos)           /*!< 0x00000002 */

+#define DSI_ISR1_TOLPRX               DSI_ISR1_TOLPRX_Msk                      /*!< Timeout Low-Power Reception */

+#define DSI_ISR1_ECCSE_Pos            (2U)

+#define DSI_ISR1_ECCSE_Msk            (0x1UL << DSI_ISR1_ECCSE_Pos)            /*!< 0x00000004 */

+#define DSI_ISR1_ECCSE                DSI_ISR1_ECCSE_Msk                       /*!< ECC Single-bit Error */

+#define DSI_ISR1_ECCME_Pos            (3U)

+#define DSI_ISR1_ECCME_Msk            (0x1UL << DSI_ISR1_ECCME_Pos)            /*!< 0x00000008 */

+#define DSI_ISR1_ECCME                DSI_ISR1_ECCME_Msk                       /*!< ECC Multi-bit Error */

+#define DSI_ISR1_CRCE_Pos             (4U)

+#define DSI_ISR1_CRCE_Msk             (0x1UL << DSI_ISR1_CRCE_Pos)             /*!< 0x00000010 */

+#define DSI_ISR1_CRCE                 DSI_ISR1_CRCE_Msk                        /*!< CRC Error */

+#define DSI_ISR1_PSE_Pos              (5U)

+#define DSI_ISR1_PSE_Msk              (0x1UL << DSI_ISR1_PSE_Pos)              /*!< 0x00000020 */

+#define DSI_ISR1_PSE                  DSI_ISR1_PSE_Msk                         /*!< Packet Size Error */

+#define DSI_ISR1_EOTPE_Pos            (6U)

+#define DSI_ISR1_EOTPE_Msk            (0x1UL << DSI_ISR1_EOTPE_Pos)            /*!< 0x00000040 */

+#define DSI_ISR1_EOTPE                DSI_ISR1_EOTPE_Msk                       /*!< EoTp Error */

+#define DSI_ISR1_LPWRE_Pos            (7U)

+#define DSI_ISR1_LPWRE_Msk            (0x1UL << DSI_ISR1_LPWRE_Pos)            /*!< 0x00000080 */

+#define DSI_ISR1_LPWRE                DSI_ISR1_LPWRE_Msk                       /*!< LTDC Payload Write Error */

+#define DSI_ISR1_GCWRE_Pos            (8U)

+#define DSI_ISR1_GCWRE_Msk            (0x1UL << DSI_ISR1_GCWRE_Pos)            /*!< 0x00000100 */

+#define DSI_ISR1_GCWRE                DSI_ISR1_GCWRE_Msk                       /*!< Generic Command Write Error */

+#define DSI_ISR1_GPWRE_Pos            (9U)

+#define DSI_ISR1_GPWRE_Msk            (0x1UL << DSI_ISR1_GPWRE_Pos)            /*!< 0x00000200 */

+#define DSI_ISR1_GPWRE                DSI_ISR1_GPWRE_Msk                       /*!< Generic Payload Write Error */

+#define DSI_ISR1_GPTXE_Pos            (10U)

+#define DSI_ISR1_GPTXE_Msk            (0x1UL << DSI_ISR1_GPTXE_Pos)            /*!< 0x00000400 */

+#define DSI_ISR1_GPTXE                DSI_ISR1_GPTXE_Msk                       /*!< Generic Payload Transmit Error */

+#define DSI_ISR1_GPRDE_Pos            (11U)

+#define DSI_ISR1_GPRDE_Msk            (0x1UL << DSI_ISR1_GPRDE_Pos)            /*!< 0x00000800 */

+#define DSI_ISR1_GPRDE                DSI_ISR1_GPRDE_Msk                       /*!< Generic Payload Read Error */

+#define DSI_ISR1_GPRXE_Pos            (12U)

+#define DSI_ISR1_GPRXE_Msk            (0x1UL << DSI_ISR1_GPRXE_Pos)            /*!< 0x00001000 */

+#define DSI_ISR1_GPRXE                DSI_ISR1_GPRXE_Msk                       /*!< Generic Payload Receive Error */

+

+/*******************  Bit definition for DSI_IER0 register  ***************/

+#define DSI_IER0_AE0IE_Pos            (0U)

+#define DSI_IER0_AE0IE_Msk            (0x1UL << DSI_IER0_AE0IE_Pos)            /*!< 0x00000001 */

+#define DSI_IER0_AE0IE                DSI_IER0_AE0IE_Msk                       /*!< Acknowledge Error 0 Interrupt Enable */

+#define DSI_IER0_AE1IE_Pos            (1U)

+#define DSI_IER0_AE1IE_Msk            (0x1UL << DSI_IER0_AE1IE_Pos)            /*!< 0x00000002 */

+#define DSI_IER0_AE1IE                DSI_IER0_AE1IE_Msk                       /*!< Acknowledge Error 1 Interrupt Enable */

+#define DSI_IER0_AE2IE_Pos            (2U)

+#define DSI_IER0_AE2IE_Msk            (0x1UL << DSI_IER0_AE2IE_Pos)            /*!< 0x00000004 */

+#define DSI_IER0_AE2IE                DSI_IER0_AE2IE_Msk                       /*!< Acknowledge Error 2 Interrupt Enable */

+#define DSI_IER0_AE3IE_Pos            (3U)

+#define DSI_IER0_AE3IE_Msk            (0x1UL << DSI_IER0_AE3IE_Pos)            /*!< 0x00000008 */

+#define DSI_IER0_AE3IE                DSI_IER0_AE3IE_Msk                       /*!< Acknowledge Error 3 Interrupt Enable */

+#define DSI_IER0_AE4IE_Pos            (4U)

+#define DSI_IER0_AE4IE_Msk            (0x1UL << DSI_IER0_AE4IE_Pos)            /*!< 0x00000010 */

+#define DSI_IER0_AE4IE                DSI_IER0_AE4IE_Msk                       /*!< Acknowledge Error 4 Interrupt Enable */

+#define DSI_IER0_AE5IE_Pos            (5U)

+#define DSI_IER0_AE5IE_Msk            (0x1UL << DSI_IER0_AE5IE_Pos)            /*!< 0x00000020 */

+#define DSI_IER0_AE5IE                DSI_IER0_AE5IE_Msk                       /*!< Acknowledge Error 5 Interrupt Enable */

+#define DSI_IER0_AE6IE_Pos            (6U)

+#define DSI_IER0_AE6IE_Msk            (0x1UL << DSI_IER0_AE6IE_Pos)            /*!< 0x00000040 */

+#define DSI_IER0_AE6IE                DSI_IER0_AE6IE_Msk                       /*!< Acknowledge Error 6 Interrupt Enable */

+#define DSI_IER0_AE7IE_Pos            (7U)

+#define DSI_IER0_AE7IE_Msk            (0x1UL << DSI_IER0_AE7IE_Pos)            /*!< 0x00000080 */

+#define DSI_IER0_AE7IE                DSI_IER0_AE7IE_Msk                       /*!< Acknowledge Error 7 Interrupt Enable */

+#define DSI_IER0_AE8IE_Pos            (8U)

+#define DSI_IER0_AE8IE_Msk            (0x1UL << DSI_IER0_AE8IE_Pos)            /*!< 0x00000100 */

+#define DSI_IER0_AE8IE                DSI_IER0_AE8IE_Msk                       /*!< Acknowledge Error 8 Interrupt Enable */

+#define DSI_IER0_AE9IE_Pos            (9U)

+#define DSI_IER0_AE9IE_Msk            (0x1UL << DSI_IER0_AE9IE_Pos)            /*!< 0x00000200 */

+#define DSI_IER0_AE9IE                DSI_IER0_AE9IE_Msk                       /*!< Acknowledge Error 9 Interrupt Enable */

+#define DSI_IER0_AE10IE_Pos           (10U)

+#define DSI_IER0_AE10IE_Msk           (0x1UL << DSI_IER0_AE10IE_Pos)           /*!< 0x00000400 */

+#define DSI_IER0_AE10IE               DSI_IER0_AE10IE_Msk                      /*!< Acknowledge Error 10 Interrupt Enable */

+#define DSI_IER0_AE11IE_Pos           (11U)

+#define DSI_IER0_AE11IE_Msk           (0x1UL << DSI_IER0_AE11IE_Pos)           /*!< 0x00000800 */

+#define DSI_IER0_AE11IE               DSI_IER0_AE11IE_Msk                      /*!< Acknowledge Error 11 Interrupt Enable */

+#define DSI_IER0_AE12IE_Pos           (12U)

+#define DSI_IER0_AE12IE_Msk           (0x1UL << DSI_IER0_AE12IE_Pos)           /*!< 0x00001000 */

+#define DSI_IER0_AE12IE               DSI_IER0_AE12IE_Msk                      /*!< Acknowledge Error 12 Interrupt Enable */

+#define DSI_IER0_AE13IE_Pos           (13U)

+#define DSI_IER0_AE13IE_Msk           (0x1UL << DSI_IER0_AE13IE_Pos)           /*!< 0x00002000 */

+#define DSI_IER0_AE13IE               DSI_IER0_AE13IE_Msk                      /*!< Acknowledge Error 13 Interrupt Enable */

+#define DSI_IER0_AE14IE_Pos           (14U)

+#define DSI_IER0_AE14IE_Msk           (0x1UL << DSI_IER0_AE14IE_Pos)           /*!< 0x00004000 */

+#define DSI_IER0_AE14IE               DSI_IER0_AE14IE_Msk                      /*!< Acknowledge Error 14 Interrupt Enable */

+#define DSI_IER0_AE15IE_Pos           (15U)

+#define DSI_IER0_AE15IE_Msk           (0x1UL << DSI_IER0_AE15IE_Pos)           /*!< 0x00008000 */

+#define DSI_IER0_AE15IE               DSI_IER0_AE15IE_Msk                      /*!< Acknowledge Error 15 Interrupt Enable */

+#define DSI_IER0_PE0IE_Pos            (16U)

+#define DSI_IER0_PE0IE_Msk            (0x1UL << DSI_IER0_PE0IE_Pos)            /*!< 0x00010000 */

+#define DSI_IER0_PE0IE                DSI_IER0_PE0IE_Msk                       /*!< PHY Error 0 Interrupt Enable */

+#define DSI_IER0_PE1IE_Pos            (17U)

+#define DSI_IER0_PE1IE_Msk            (0x1UL << DSI_IER0_PE1IE_Pos)            /*!< 0x00020000 */

+#define DSI_IER0_PE1IE                DSI_IER0_PE1IE_Msk                       /*!< PHY Error 1 Interrupt Enable */

+#define DSI_IER0_PE2IE_Pos            (18U)

+#define DSI_IER0_PE2IE_Msk            (0x1UL << DSI_IER0_PE2IE_Pos)            /*!< 0x00040000 */

+#define DSI_IER0_PE2IE                DSI_IER0_PE2IE_Msk                       /*!< PHY Error 2 Interrupt Enable */

+#define DSI_IER0_PE3IE_Pos            (19U)

+#define DSI_IER0_PE3IE_Msk            (0x1UL << DSI_IER0_PE3IE_Pos)            /*!< 0x00080000 */

+#define DSI_IER0_PE3IE                DSI_IER0_PE3IE_Msk                       /*!< PHY Error 3 Interrupt Enable */

+#define DSI_IER0_PE4IE_Pos            (20U)

+#define DSI_IER0_PE4IE_Msk            (0x1UL << DSI_IER0_PE4IE_Pos)            /*!< 0x00100000 */

+#define DSI_IER0_PE4IE                DSI_IER0_PE4IE_Msk                       /*!< PHY Error 4 Interrupt Enable */

+

+/*******************  Bit definition for DSI_IER1 register  ***************/

+#define DSI_IER1_TOHSTXIE_Pos         (0U)

+#define DSI_IER1_TOHSTXIE_Msk         (0x1UL << DSI_IER1_TOHSTXIE_Pos)         /*!< 0x00000001 */

+#define DSI_IER1_TOHSTXIE             DSI_IER1_TOHSTXIE_Msk                    /*!< Timeout High-Speed Transmission Interrupt Enable */

+#define DSI_IER1_TOLPRXIE_Pos         (1U)

+#define DSI_IER1_TOLPRXIE_Msk         (0x1UL << DSI_IER1_TOLPRXIE_Pos)         /*!< 0x00000002 */

+#define DSI_IER1_TOLPRXIE             DSI_IER1_TOLPRXIE_Msk                    /*!< Timeout Low-Power Reception Interrupt Enable */

+#define DSI_IER1_ECCSEIE_Pos          (2U)

+#define DSI_IER1_ECCSEIE_Msk          (0x1UL << DSI_IER1_ECCSEIE_Pos)          /*!< 0x00000004 */

+#define DSI_IER1_ECCSEIE              DSI_IER1_ECCSEIE_Msk                     /*!< ECC Single-bit Error Interrupt Enable */

+#define DSI_IER1_ECCMEIE_Pos          (3U)

+#define DSI_IER1_ECCMEIE_Msk          (0x1UL << DSI_IER1_ECCMEIE_Pos)          /*!< 0x00000008 */

+#define DSI_IER1_ECCMEIE              DSI_IER1_ECCMEIE_Msk                     /*!< ECC Multi-bit Error Interrupt Enable */

+#define DSI_IER1_CRCEIE_Pos           (4U)

+#define DSI_IER1_CRCEIE_Msk           (0x1UL << DSI_IER1_CRCEIE_Pos)           /*!< 0x00000010 */

+#define DSI_IER1_CRCEIE               DSI_IER1_CRCEIE_Msk                      /*!< CRC Error Interrupt Enable */

+#define DSI_IER1_PSEIE_Pos            (5U)

+#define DSI_IER1_PSEIE_Msk            (0x1UL << DSI_IER1_PSEIE_Pos)            /*!< 0x00000020 */

+#define DSI_IER1_PSEIE                DSI_IER1_PSEIE_Msk                       /*!< Packet Size Error Interrupt Enable */

+#define DSI_IER1_EOTPEIE_Pos          (6U)

+#define DSI_IER1_EOTPEIE_Msk          (0x1UL << DSI_IER1_EOTPEIE_Pos)          /*!< 0x00000040 */

+#define DSI_IER1_EOTPEIE              DSI_IER1_EOTPEIE_Msk                     /*!< EoTp Error Interrupt Enable */

+#define DSI_IER1_LPWREIE_Pos          (7U)

+#define DSI_IER1_LPWREIE_Msk          (0x1UL << DSI_IER1_LPWREIE_Pos)          /*!< 0x00000080 */

+#define DSI_IER1_LPWREIE              DSI_IER1_LPWREIE_Msk                     /*!< LTDC Payload Write Error Interrupt Enable */

+#define DSI_IER1_GCWREIE_Pos          (8U)

+#define DSI_IER1_GCWREIE_Msk          (0x1UL << DSI_IER1_GCWREIE_Pos)          /*!< 0x00000100 */

+#define DSI_IER1_GCWREIE              DSI_IER1_GCWREIE_Msk                     /*!< Generic Command Write Error Interrupt Enable */

+#define DSI_IER1_GPWREIE_Pos          (9U)

+#define DSI_IER1_GPWREIE_Msk          (0x1UL << DSI_IER1_GPWREIE_Pos)          /*!< 0x00000200 */

+#define DSI_IER1_GPWREIE              DSI_IER1_GPWREIE_Msk                     /*!< Generic Payload Write Error Interrupt Enable */

+#define DSI_IER1_GPTXEIE_Pos          (10U)

+#define DSI_IER1_GPTXEIE_Msk          (0x1UL << DSI_IER1_GPTXEIE_Pos)          /*!< 0x00000400 */

+#define DSI_IER1_GPTXEIE              DSI_IER1_GPTXEIE_Msk                     /*!< Generic Payload Transmit Error Interrupt Enable */

+#define DSI_IER1_GPRDEIE_Pos          (11U)

+#define DSI_IER1_GPRDEIE_Msk          (0x1UL << DSI_IER1_GPRDEIE_Pos)          /*!< 0x00000800 */

+#define DSI_IER1_GPRDEIE              DSI_IER1_GPRDEIE_Msk                     /*!< Generic Payload Read Error Interrupt Enable */

+#define DSI_IER1_GPRXEIE_Pos          (12U)

+#define DSI_IER1_GPRXEIE_Msk          (0x1UL << DSI_IER1_GPRXEIE_Pos)          /*!< 0x00001000 */

+#define DSI_IER1_GPRXEIE              DSI_IER1_GPRXEIE_Msk                     /*!< Generic Payload Receive Error Interrupt Enable */

+

+/*******************  Bit definition for DSI_FIR0 register  ***************/

+#define DSI_FIR0_FAE0_Pos             (0U)

+#define DSI_FIR0_FAE0_Msk             (0x1UL << DSI_FIR0_FAE0_Pos)             /*!< 0x00000001 */

+#define DSI_FIR0_FAE0                 DSI_FIR0_FAE0_Msk                        /*!< Force Acknowledge Error 0 */

+#define DSI_FIR0_FAE1_Pos             (1U)

+#define DSI_FIR0_FAE1_Msk             (0x1UL << DSI_FIR0_FAE1_Pos)             /*!< 0x00000002 */

+#define DSI_FIR0_FAE1                 DSI_FIR0_FAE1_Msk                        /*!< Force Acknowledge Error 1 */

+#define DSI_FIR0_FAE2_Pos             (2U)

+#define DSI_FIR0_FAE2_Msk             (0x1UL << DSI_FIR0_FAE2_Pos)             /*!< 0x00000004 */

+#define DSI_FIR0_FAE2                 DSI_FIR0_FAE2_Msk                        /*!< Force Acknowledge Error 2 */

+#define DSI_FIR0_FAE3_Pos             (3U)

+#define DSI_FIR0_FAE3_Msk             (0x1UL << DSI_FIR0_FAE3_Pos)             /*!< 0x00000008 */

+#define DSI_FIR0_FAE3                 DSI_FIR0_FAE3_Msk                        /*!< Force Acknowledge Error 3 */

+#define DSI_FIR0_FAE4_Pos             (4U)

+#define DSI_FIR0_FAE4_Msk             (0x1UL << DSI_FIR0_FAE4_Pos)             /*!< 0x00000010 */

+#define DSI_FIR0_FAE4                 DSI_FIR0_FAE4_Msk                        /*!< Force Acknowledge Error 4 */

+#define DSI_FIR0_FAE5_Pos             (5U)

+#define DSI_FIR0_FAE5_Msk             (0x1UL << DSI_FIR0_FAE5_Pos)             /*!< 0x00000020 */

+#define DSI_FIR0_FAE5                 DSI_FIR0_FAE5_Msk                        /*!< Force Acknowledge Error 5 */

+#define DSI_FIR0_FAE6_Pos             (6U)

+#define DSI_FIR0_FAE6_Msk             (0x1UL << DSI_FIR0_FAE6_Pos)             /*!< 0x00000040 */

+#define DSI_FIR0_FAE6                 DSI_FIR0_FAE6_Msk                        /*!< Force Acknowledge Error 6 */

+#define DSI_FIR0_FAE7_Pos             (7U)

+#define DSI_FIR0_FAE7_Msk             (0x1UL << DSI_FIR0_FAE7_Pos)             /*!< 0x00000080 */

+#define DSI_FIR0_FAE7                 DSI_FIR0_FAE7_Msk                        /*!< Force Acknowledge Error 7 */

+#define DSI_FIR0_FAE8_Pos             (8U)

+#define DSI_FIR0_FAE8_Msk             (0x1UL << DSI_FIR0_FAE8_Pos)             /*!< 0x00000100 */

+#define DSI_FIR0_FAE8                 DSI_FIR0_FAE8_Msk                        /*!< Force Acknowledge Error 8 */

+#define DSI_FIR0_FAE9_Pos             (9U)

+#define DSI_FIR0_FAE9_Msk             (0x1UL << DSI_FIR0_FAE9_Pos)             /*!< 0x00000200 */

+#define DSI_FIR0_FAE9                 DSI_FIR0_FAE9_Msk                        /*!< Force Acknowledge Error 9 */

+#define DSI_FIR0_FAE10_Pos            (10U)

+#define DSI_FIR0_FAE10_Msk            (0x1UL << DSI_FIR0_FAE10_Pos)            /*!< 0x00000400 */

+#define DSI_FIR0_FAE10                DSI_FIR0_FAE10_Msk                       /*!< Force Acknowledge Error 10 */

+#define DSI_FIR0_FAE11_Pos            (11U)

+#define DSI_FIR0_FAE11_Msk            (0x1UL << DSI_FIR0_FAE11_Pos)            /*!< 0x00000800 */

+#define DSI_FIR0_FAE11                DSI_FIR0_FAE11_Msk                       /*!< Force Acknowledge Error 11 */

+#define DSI_FIR0_FAE12_Pos            (12U)

+#define DSI_FIR0_FAE12_Msk            (0x1UL << DSI_FIR0_FAE12_Pos)            /*!< 0x00001000 */

+#define DSI_FIR0_FAE12                DSI_FIR0_FAE12_Msk                       /*!< Force Acknowledge Error 12 */

+#define DSI_FIR0_FAE13_Pos            (13U)

+#define DSI_FIR0_FAE13_Msk            (0x1UL << DSI_FIR0_FAE13_Pos)            /*!< 0x00002000 */

+#define DSI_FIR0_FAE13                DSI_FIR0_FAE13_Msk                       /*!< Force Acknowledge Error 13 */

+#define DSI_FIR0_FAE14_Pos            (14U)

+#define DSI_FIR0_FAE14_Msk            (0x1UL << DSI_FIR0_FAE14_Pos)            /*!< 0x00004000 */

+#define DSI_FIR0_FAE14                DSI_FIR0_FAE14_Msk                       /*!< Force Acknowledge Error 14 */

+#define DSI_FIR0_FAE15_Pos            (15U)

+#define DSI_FIR0_FAE15_Msk            (0x1UL << DSI_FIR0_FAE15_Pos)            /*!< 0x00008000 */

+#define DSI_FIR0_FAE15                DSI_FIR0_FAE15_Msk                       /*!< Force Acknowledge Error 15 */

+#define DSI_FIR0_FPE0_Pos             (16U)

+#define DSI_FIR0_FPE0_Msk             (0x1UL << DSI_FIR0_FPE0_Pos)             /*!< 0x00010000 */

+#define DSI_FIR0_FPE0                 DSI_FIR0_FPE0_Msk                        /*!< Force PHY Error 0 */

+#define DSI_FIR0_FPE1_Pos             (17U)

+#define DSI_FIR0_FPE1_Msk             (0x1UL << DSI_FIR0_FPE1_Pos)             /*!< 0x00020000 */

+#define DSI_FIR0_FPE1                 DSI_FIR0_FPE1_Msk                        /*!< Force PHY Error 1 */

+#define DSI_FIR0_FPE2_Pos             (18U)

+#define DSI_FIR0_FPE2_Msk             (0x1UL << DSI_FIR0_FPE2_Pos)             /*!< 0x00040000 */

+#define DSI_FIR0_FPE2                 DSI_FIR0_FPE2_Msk                        /*!< Force PHY Error 2 */

+#define DSI_FIR0_FPE3_Pos             (19U)

+#define DSI_FIR0_FPE3_Msk             (0x1UL << DSI_FIR0_FPE3_Pos)             /*!< 0x00080000 */

+#define DSI_FIR0_FPE3                 DSI_FIR0_FPE3_Msk                        /*!< Force PHY Error 3 */

+#define DSI_FIR0_FPE4_Pos             (20U)

+#define DSI_FIR0_FPE4_Msk             (0x1UL << DSI_FIR0_FPE4_Pos)             /*!< 0x00100000 */

+#define DSI_FIR0_FPE4                 DSI_FIR0_FPE4_Msk                        /*!< Force PHY Error 4 */

+

+/*******************  Bit definition for DSI_FIR1 register  ***************/

+#define DSI_FIR1_FTOHSTX_Pos          (0U)

+#define DSI_FIR1_FTOHSTX_Msk          (0x1UL << DSI_FIR1_FTOHSTX_Pos)          /*!< 0x00000001 */

+#define DSI_FIR1_FTOHSTX              DSI_FIR1_FTOHSTX_Msk                     /*!< Force Timeout High-Speed Transmission */

+#define DSI_FIR1_FTOLPRX_Pos          (1U)

+#define DSI_FIR1_FTOLPRX_Msk          (0x1UL << DSI_FIR1_FTOLPRX_Pos)          /*!< 0x00000002 */

+#define DSI_FIR1_FTOLPRX              DSI_FIR1_FTOLPRX_Msk                     /*!< Force Timeout Low-Power Reception */

+#define DSI_FIR1_FECCSE_Pos           (2U)

+#define DSI_FIR1_FECCSE_Msk           (0x1UL << DSI_FIR1_FECCSE_Pos)           /*!< 0x00000004 */

+#define DSI_FIR1_FECCSE               DSI_FIR1_FECCSE_Msk                      /*!< Force ECC Single-bit Error */

+#define DSI_FIR1_FECCME_Pos           (3U)

+#define DSI_FIR1_FECCME_Msk           (0x1UL << DSI_FIR1_FECCME_Pos)           /*!< 0x00000008 */

+#define DSI_FIR1_FECCME               DSI_FIR1_FECCME_Msk                      /*!< Force ECC Multi-bit Error */

+#define DSI_FIR1_FCRCE_Pos            (4U)

+#define DSI_FIR1_FCRCE_Msk            (0x1UL << DSI_FIR1_FCRCE_Pos)            /*!< 0x00000010 */

+#define DSI_FIR1_FCRCE                DSI_FIR1_FCRCE_Msk                       /*!< Force CRC Error */

+#define DSI_FIR1_FPSE_Pos             (5U)

+#define DSI_FIR1_FPSE_Msk             (0x1UL << DSI_FIR1_FPSE_Pos)             /*!< 0x00000020 */

+#define DSI_FIR1_FPSE                 DSI_FIR1_FPSE_Msk                        /*!< Force Packet Size Error */

+#define DSI_FIR1_FEOTPE_Pos           (6U)

+#define DSI_FIR1_FEOTPE_Msk           (0x1UL << DSI_FIR1_FEOTPE_Pos)           /*!< 0x00000040 */

+#define DSI_FIR1_FEOTPE               DSI_FIR1_FEOTPE_Msk                      /*!< Force EoTp Error */

+#define DSI_FIR1_FLPWRE_Pos           (7U)

+#define DSI_FIR1_FLPWRE_Msk           (0x1UL << DSI_FIR1_FLPWRE_Pos)           /*!< 0x00000080 */

+#define DSI_FIR1_FLPWRE               DSI_FIR1_FLPWRE_Msk                      /*!< Force LTDC Payload Write Error */

+#define DSI_FIR1_FGCWRE_Pos           (8U)

+#define DSI_FIR1_FGCWRE_Msk           (0x1UL << DSI_FIR1_FGCWRE_Pos)           /*!< 0x00000100 */

+#define DSI_FIR1_FGCWRE               DSI_FIR1_FGCWRE_Msk                      /*!< Force Generic Command Write Error */

+#define DSI_FIR1_FGPWRE_Pos           (9U)

+#define DSI_FIR1_FGPWRE_Msk           (0x1UL << DSI_FIR1_FGPWRE_Pos)           /*!< 0x00000200 */

+#define DSI_FIR1_FGPWRE               DSI_FIR1_FGPWRE_Msk                      /*!< Force Generic Payload Write Error */

+#define DSI_FIR1_FGPTXE_Pos           (10U)

+#define DSI_FIR1_FGPTXE_Msk           (0x1UL << DSI_FIR1_FGPTXE_Pos)           /*!< 0x00000400 */

+#define DSI_FIR1_FGPTXE               DSI_FIR1_FGPTXE_Msk                      /*!< Force Generic Payload Transmit Error */

+#define DSI_FIR1_FGPRDE_Pos           (11U)

+#define DSI_FIR1_FGPRDE_Msk           (0x1UL << DSI_FIR1_FGPRDE_Pos)           /*!< 0x00000800 */

+#define DSI_FIR1_FGPRDE               DSI_FIR1_FGPRDE_Msk                      /*!< Force Generic Payload Read Error */

+#define DSI_FIR1_FGPRXE_Pos           (12U)

+#define DSI_FIR1_FGPRXE_Msk           (0x1UL << DSI_FIR1_FGPRXE_Pos)           /*!< 0x00001000 */

+#define DSI_FIR1_FGPRXE               DSI_FIR1_FGPRXE_Msk                      /*!< Force Generic Payload Receive Error */

+

+/*******************  Bit definition for DSI_VSCR register  ***************/

+#define DSI_VSCR_EN_Pos               (0U)

+#define DSI_VSCR_EN_Msk               (0x1UL << DSI_VSCR_EN_Pos)               /*!< 0x00000001 */

+#define DSI_VSCR_EN                   DSI_VSCR_EN_Msk                          /*!< Enable */

+#define DSI_VSCR_UR_Pos               (8U)

+#define DSI_VSCR_UR_Msk               (0x1UL << DSI_VSCR_UR_Pos)               /*!< 0x00000100 */

+#define DSI_VSCR_UR                   DSI_VSCR_UR_Msk                          /*!< Update Register */

+

+/*******************  Bit definition for DSI_LCVCIDR register  ************/

+#define DSI_LCVCIDR_VCID_Pos          (0U)

+#define DSI_LCVCIDR_VCID_Msk          (0x3UL << DSI_LCVCIDR_VCID_Pos)          /*!< 0x00000003 */

+#define DSI_LCVCIDR_VCID              DSI_LCVCIDR_VCID_Msk                     /*!< Virtual Channel ID */

+#define DSI_LCVCIDR_VCID0_Pos         (0U)

+#define DSI_LCVCIDR_VCID0_Msk         (0x1UL << DSI_LCVCIDR_VCID0_Pos)         /*!< 0x00000001 */

+#define DSI_LCVCIDR_VCID0             DSI_LCVCIDR_VCID0_Msk

+#define DSI_LCVCIDR_VCID1_Pos         (1U)

+#define DSI_LCVCIDR_VCID1_Msk         (0x1UL << DSI_LCVCIDR_VCID1_Pos)         /*!< 0x00000002 */

+#define DSI_LCVCIDR_VCID1             DSI_LCVCIDR_VCID1_Msk

+

+/*******************  Bit definition for DSI_LCCCR register  **************/

+#define DSI_LCCCR_COLC_Pos            (0U)

+#define DSI_LCCCR_COLC_Msk            (0xFUL << DSI_LCCCR_COLC_Pos)            /*!< 0x0000000F */

+#define DSI_LCCCR_COLC                DSI_LCCCR_COLC_Msk                       /*!< Color Coding */

+#define DSI_LCCCR_COLC0_Pos           (0U)

+#define DSI_LCCCR_COLC0_Msk           (0x1UL << DSI_LCCCR_COLC0_Pos)           /*!< 0x00000001 */

+#define DSI_LCCCR_COLC0               DSI_LCCCR_COLC0_Msk

+#define DSI_LCCCR_COLC1_Pos           (1U)

+#define DSI_LCCCR_COLC1_Msk           (0x1UL << DSI_LCCCR_COLC1_Pos)           /*!< 0x00000002 */

+#define DSI_LCCCR_COLC1               DSI_LCCCR_COLC1_Msk

+#define DSI_LCCCR_COLC2_Pos           (2U)

+#define DSI_LCCCR_COLC2_Msk           (0x1UL << DSI_LCCCR_COLC2_Pos)           /*!< 0x00000004 */

+#define DSI_LCCCR_COLC2               DSI_LCCCR_COLC2_Msk

+#define DSI_LCCCR_COLC3_Pos           (3U)

+#define DSI_LCCCR_COLC3_Msk           (0x1UL << DSI_LCCCR_COLC3_Pos)           /*!< 0x00000008 */

+#define DSI_LCCCR_COLC3               DSI_LCCCR_COLC3_Msk

+

+#define DSI_LCCCR_LPE_Pos             (8U)

+#define DSI_LCCCR_LPE_Msk             (0x1UL << DSI_LCCCR_LPE_Pos)             /*!< 0x00000100 */

+#define DSI_LCCCR_LPE                 DSI_LCCCR_LPE_Msk                        /*!< Loosely Packed Enable */

+

+/*******************  Bit definition for DSI_LPMCCR register  *************/

+#define DSI_LPMCCR_VLPSIZE_Pos        (0U)

+#define DSI_LPMCCR_VLPSIZE_Msk        (0xFFUL << DSI_LPMCCR_VLPSIZE_Pos)       /*!< 0x000000FF */

+#define DSI_LPMCCR_VLPSIZE            DSI_LPMCCR_VLPSIZE_Msk                   /*!< VACT Largest Packet Size */

+#define DSI_LPMCCR_VLPSIZE0_Pos       (0U)

+#define DSI_LPMCCR_VLPSIZE0_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE0_Pos)       /*!< 0x00000001 */

+#define DSI_LPMCCR_VLPSIZE0           DSI_LPMCCR_VLPSIZE0_Msk

+#define DSI_LPMCCR_VLPSIZE1_Pos       (1U)

+#define DSI_LPMCCR_VLPSIZE1_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE1_Pos)       /*!< 0x00000002 */

+#define DSI_LPMCCR_VLPSIZE1           DSI_LPMCCR_VLPSIZE1_Msk

+#define DSI_LPMCCR_VLPSIZE2_Pos       (2U)

+#define DSI_LPMCCR_VLPSIZE2_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE2_Pos)       /*!< 0x00000004 */

+#define DSI_LPMCCR_VLPSIZE2           DSI_LPMCCR_VLPSIZE2_Msk

+#define DSI_LPMCCR_VLPSIZE3_Pos       (3U)

+#define DSI_LPMCCR_VLPSIZE3_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE3_Pos)       /*!< 0x00000008 */

+#define DSI_LPMCCR_VLPSIZE3           DSI_LPMCCR_VLPSIZE3_Msk

+#define DSI_LPMCCR_VLPSIZE4_Pos       (4U)

+#define DSI_LPMCCR_VLPSIZE4_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE4_Pos)       /*!< 0x00000010 */

+#define DSI_LPMCCR_VLPSIZE4           DSI_LPMCCR_VLPSIZE4_Msk

+#define DSI_LPMCCR_VLPSIZE5_Pos       (5U)

+#define DSI_LPMCCR_VLPSIZE5_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE5_Pos)       /*!< 0x00000020 */

+#define DSI_LPMCCR_VLPSIZE5           DSI_LPMCCR_VLPSIZE5_Msk

+#define DSI_LPMCCR_VLPSIZE6_Pos       (6U)

+#define DSI_LPMCCR_VLPSIZE6_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE6_Pos)       /*!< 0x00000040 */

+#define DSI_LPMCCR_VLPSIZE6           DSI_LPMCCR_VLPSIZE6_Msk

+#define DSI_LPMCCR_VLPSIZE7_Pos       (7U)

+#define DSI_LPMCCR_VLPSIZE7_Msk       (0x1UL << DSI_LPMCCR_VLPSIZE7_Pos)       /*!< 0x00000080 */

+#define DSI_LPMCCR_VLPSIZE7           DSI_LPMCCR_VLPSIZE7_Msk

+

+#define DSI_LPMCCR_LPSIZE_Pos         (16U)

+#define DSI_LPMCCR_LPSIZE_Msk         (0xFFUL << DSI_LPMCCR_LPSIZE_Pos)        /*!< 0x00FF0000 */

+#define DSI_LPMCCR_LPSIZE             DSI_LPMCCR_LPSIZE_Msk                    /*!< Largest Packet Size */

+#define DSI_LPMCCR_LPSIZE0_Pos        (16U)

+#define DSI_LPMCCR_LPSIZE0_Msk        (0x1UL << DSI_LPMCCR_LPSIZE0_Pos)        /*!< 0x00010000 */

+#define DSI_LPMCCR_LPSIZE0            DSI_LPMCCR_LPSIZE0_Msk

+#define DSI_LPMCCR_LPSIZE1_Pos        (17U)

+#define DSI_LPMCCR_LPSIZE1_Msk        (0x1UL << DSI_LPMCCR_LPSIZE1_Pos)        /*!< 0x00020000 */

+#define DSI_LPMCCR_LPSIZE1            DSI_LPMCCR_LPSIZE1_Msk

+#define DSI_LPMCCR_LPSIZE2_Pos        (18U)

+#define DSI_LPMCCR_LPSIZE2_Msk        (0x1UL << DSI_LPMCCR_LPSIZE2_Pos)        /*!< 0x00040000 */

+#define DSI_LPMCCR_LPSIZE2            DSI_LPMCCR_LPSIZE2_Msk

+#define DSI_LPMCCR_LPSIZE3_Pos        (19U)

+#define DSI_LPMCCR_LPSIZE3_Msk        (0x1UL << DSI_LPMCCR_LPSIZE3_Pos)        /*!< 0x00080000 */

+#define DSI_LPMCCR_LPSIZE3            DSI_LPMCCR_LPSIZE3_Msk

+#define DSI_LPMCCR_LPSIZE4_Pos        (20U)

+#define DSI_LPMCCR_LPSIZE4_Msk        (0x1UL << DSI_LPMCCR_LPSIZE4_Pos)        /*!< 0x00100000 */

+#define DSI_LPMCCR_LPSIZE4            DSI_LPMCCR_LPSIZE4_Msk

+#define DSI_LPMCCR_LPSIZE5_Pos        (21U)

+#define DSI_LPMCCR_LPSIZE5_Msk        (0x1UL << DSI_LPMCCR_LPSIZE5_Pos)        /*!< 0x00200000 */

+#define DSI_LPMCCR_LPSIZE5            DSI_LPMCCR_LPSIZE5_Msk

+#define DSI_LPMCCR_LPSIZE6_Pos        (22U)

+#define DSI_LPMCCR_LPSIZE6_Msk        (0x1UL << DSI_LPMCCR_LPSIZE6_Pos)        /*!< 0x00400000 */

+#define DSI_LPMCCR_LPSIZE6            DSI_LPMCCR_LPSIZE6_Msk

+#define DSI_LPMCCR_LPSIZE7_Pos        (23U)

+#define DSI_LPMCCR_LPSIZE7_Msk        (0x1UL << DSI_LPMCCR_LPSIZE7_Pos)        /*!< 0x00800000 */

+#define DSI_LPMCCR_LPSIZE7            DSI_LPMCCR_LPSIZE7_Msk

+

+/*******************  Bit definition for DSI_VMCCR register  **************/

+#define DSI_VMCCR_VMT_Pos             (0U)

+#define DSI_VMCCR_VMT_Msk             (0x3UL << DSI_VMCCR_VMT_Pos)             /*!< 0x00000003 */

+#define DSI_VMCCR_VMT                 DSI_VMCCR_VMT_Msk                        /*!< Video Mode Type */

+#define DSI_VMCCR_VMT0_Pos            (0U)

+#define DSI_VMCCR_VMT0_Msk            (0x1UL << DSI_VMCCR_VMT0_Pos)            /*!< 0x00000001 */

+#define DSI_VMCCR_VMT0                DSI_VMCCR_VMT0_Msk

+#define DSI_VMCCR_VMT1_Pos            (1U)

+#define DSI_VMCCR_VMT1_Msk            (0x1UL << DSI_VMCCR_VMT1_Pos)            /*!< 0x00000002 */

+#define DSI_VMCCR_VMT1                DSI_VMCCR_VMT1_Msk

+

+#define DSI_VMCCR_LPVSAE_Pos          (8U)

+#define DSI_VMCCR_LPVSAE_Msk          (0x1UL << DSI_VMCCR_LPVSAE_Pos)          /*!< 0x00000100 */

+#define DSI_VMCCR_LPVSAE              DSI_VMCCR_LPVSAE_Msk                     /*!< Low-power Vertical Sync time Enable */

+#define DSI_VMCCR_LPVBPE_Pos          (9U)

+#define DSI_VMCCR_LPVBPE_Msk          (0x1UL << DSI_VMCCR_LPVBPE_Pos)          /*!< 0x00000200 */

+#define DSI_VMCCR_LPVBPE              DSI_VMCCR_LPVBPE_Msk                     /*!< Low-power Vertical Back-porch Enable */

+#define DSI_VMCCR_LPVFPE_Pos          (10U)

+#define DSI_VMCCR_LPVFPE_Msk          (0x1UL << DSI_VMCCR_LPVFPE_Pos)          /*!< 0x00000400 */

+#define DSI_VMCCR_LPVFPE              DSI_VMCCR_LPVFPE_Msk                     /*!< Low-power Vertical Front-porch Enable */

+#define DSI_VMCCR_LPVAE_Pos           (11U)

+#define DSI_VMCCR_LPVAE_Msk           (0x1UL << DSI_VMCCR_LPVAE_Pos)           /*!< 0x00000800 */

+#define DSI_VMCCR_LPVAE               DSI_VMCCR_LPVAE_Msk                      /*!< Low-power Vertical Active Enable */

+#define DSI_VMCCR_LPHBPE_Pos          (12U)

+#define DSI_VMCCR_LPHBPE_Msk          (0x1UL << DSI_VMCCR_LPHBPE_Pos)          /*!< 0x00001000 */

+#define DSI_VMCCR_LPHBPE              DSI_VMCCR_LPHBPE_Msk                     /*!< Low-power Horizontal Back-porch Enable */

+#define DSI_VMCCR_LPHFE_Pos           (13U)

+#define DSI_VMCCR_LPHFE_Msk           (0x1UL << DSI_VMCCR_LPHFE_Pos)           /*!< 0x00002000 */

+#define DSI_VMCCR_LPHFE               DSI_VMCCR_LPHFE_Msk                      /*!< Low-power Horizontal Front-porch Enable */

+#define DSI_VMCCR_FBTAAE_Pos          (14U)

+#define DSI_VMCCR_FBTAAE_Msk          (0x1UL << DSI_VMCCR_FBTAAE_Pos)          /*!< 0x00004000 */

+#define DSI_VMCCR_FBTAAE              DSI_VMCCR_FBTAAE_Msk                     /*!< Frame BTA Acknowledge Enable */

+#define DSI_VMCCR_LPCE_Pos            (15U)

+#define DSI_VMCCR_LPCE_Msk            (0x1UL << DSI_VMCCR_LPCE_Pos)            /*!< 0x00008000 */

+#define DSI_VMCCR_LPCE                DSI_VMCCR_LPCE_Msk                       /*!< Low-power Command Enable */

+

+/*******************  Bit definition for DSI_VPCCR register  **************/

+#define DSI_VPCCR_VPSIZE_Pos          (0U)

+#define DSI_VPCCR_VPSIZE_Msk          (0x3FFFUL << DSI_VPCCR_VPSIZE_Pos)       /*!< 0x00003FFF */

+#define DSI_VPCCR_VPSIZE              DSI_VPCCR_VPSIZE_Msk                     /*!< Video Packet Size */

+#define DSI_VPCCR_VPSIZE0_Pos         (0U)

+#define DSI_VPCCR_VPSIZE0_Msk         (0x1UL << DSI_VPCCR_VPSIZE0_Pos)         /*!< 0x00000001 */

+#define DSI_VPCCR_VPSIZE0             DSI_VPCCR_VPSIZE0_Msk

+#define DSI_VPCCR_VPSIZE1_Pos         (1U)

+#define DSI_VPCCR_VPSIZE1_Msk         (0x1UL << DSI_VPCCR_VPSIZE1_Pos)         /*!< 0x00000002 */

+#define DSI_VPCCR_VPSIZE1             DSI_VPCCR_VPSIZE1_Msk

+#define DSI_VPCCR_VPSIZE2_Pos         (2U)

+#define DSI_VPCCR_VPSIZE2_Msk         (0x1UL << DSI_VPCCR_VPSIZE2_Pos)         /*!< 0x00000004 */

+#define DSI_VPCCR_VPSIZE2             DSI_VPCCR_VPSIZE2_Msk

+#define DSI_VPCCR_VPSIZE3_Pos         (3U)

+#define DSI_VPCCR_VPSIZE3_Msk         (0x1UL << DSI_VPCCR_VPSIZE3_Pos)         /*!< 0x00000008 */

+#define DSI_VPCCR_VPSIZE3             DSI_VPCCR_VPSIZE3_Msk

+#define DSI_VPCCR_VPSIZE4_Pos         (4U)

+#define DSI_VPCCR_VPSIZE4_Msk         (0x1UL << DSI_VPCCR_VPSIZE4_Pos)         /*!< 0x00000010 */

+#define DSI_VPCCR_VPSIZE4             DSI_VPCCR_VPSIZE4_Msk

+#define DSI_VPCCR_VPSIZE5_Pos         (5U)

+#define DSI_VPCCR_VPSIZE5_Msk         (0x1UL << DSI_VPCCR_VPSIZE5_Pos)         /*!< 0x00000020 */

+#define DSI_VPCCR_VPSIZE5             DSI_VPCCR_VPSIZE5_Msk

+#define DSI_VPCCR_VPSIZE6_Pos         (6U)

+#define DSI_VPCCR_VPSIZE6_Msk         (0x1UL << DSI_VPCCR_VPSIZE6_Pos)         /*!< 0x00000040 */

+#define DSI_VPCCR_VPSIZE6             DSI_VPCCR_VPSIZE6_Msk

+#define DSI_VPCCR_VPSIZE7_Pos         (7U)

+#define DSI_VPCCR_VPSIZE7_Msk         (0x1UL << DSI_VPCCR_VPSIZE7_Pos)         /*!< 0x00000080 */

+#define DSI_VPCCR_VPSIZE7             DSI_VPCCR_VPSIZE7_Msk

+#define DSI_VPCCR_VPSIZE8_Pos         (8U)

+#define DSI_VPCCR_VPSIZE8_Msk         (0x1UL << DSI_VPCCR_VPSIZE8_Pos)         /*!< 0x00000100 */

+#define DSI_VPCCR_VPSIZE8             DSI_VPCCR_VPSIZE8_Msk

+#define DSI_VPCCR_VPSIZE9_Pos         (9U)

+#define DSI_VPCCR_VPSIZE9_Msk         (0x1UL << DSI_VPCCR_VPSIZE9_Pos)         /*!< 0x00000200 */

+#define DSI_VPCCR_VPSIZE9             DSI_VPCCR_VPSIZE9_Msk

+#define DSI_VPCCR_VPSIZE10_Pos        (10U)

+#define DSI_VPCCR_VPSIZE10_Msk        (0x1UL << DSI_VPCCR_VPSIZE10_Pos)        /*!< 0x00000400 */

+#define DSI_VPCCR_VPSIZE10            DSI_VPCCR_VPSIZE10_Msk

+#define DSI_VPCCR_VPSIZE11_Pos        (11U)

+#define DSI_VPCCR_VPSIZE11_Msk        (0x1UL << DSI_VPCCR_VPSIZE11_Pos)        /*!< 0x00000800 */

+#define DSI_VPCCR_VPSIZE11            DSI_VPCCR_VPSIZE11_Msk

+#define DSI_VPCCR_VPSIZE12_Pos        (12U)

+#define DSI_VPCCR_VPSIZE12_Msk        (0x1UL << DSI_VPCCR_VPSIZE12_Pos)        /*!< 0x00001000 */

+#define DSI_VPCCR_VPSIZE12            DSI_VPCCR_VPSIZE12_Msk

+#define DSI_VPCCR_VPSIZE13_Pos        (13U)

+#define DSI_VPCCR_VPSIZE13_Msk        (0x1UL << DSI_VPCCR_VPSIZE13_Pos)        /*!< 0x00002000 */

+#define DSI_VPCCR_VPSIZE13            DSI_VPCCR_VPSIZE13_Msk

+

+/*******************  Bit definition for DSI_VCCCR register  **************/

+#define DSI_VCCCR_NUMC_Pos            (0U)

+#define DSI_VCCCR_NUMC_Msk            (0x1FFFUL << DSI_VCCCR_NUMC_Pos)         /*!< 0x00001FFF */

+#define DSI_VCCCR_NUMC                DSI_VCCCR_NUMC_Msk                       /*!< Number of Chunks */

+#define DSI_VCCCR_NUMC0_Pos           (0U)

+#define DSI_VCCCR_NUMC0_Msk           (0x1UL << DSI_VCCCR_NUMC0_Pos)           /*!< 0x00000001 */

+#define DSI_VCCCR_NUMC0               DSI_VCCCR_NUMC0_Msk

+#define DSI_VCCCR_NUMC1_Pos           (1U)

+#define DSI_VCCCR_NUMC1_Msk           (0x1UL << DSI_VCCCR_NUMC1_Pos)           /*!< 0x00000002 */

+#define DSI_VCCCR_NUMC1               DSI_VCCCR_NUMC1_Msk

+#define DSI_VCCCR_NUMC2_Pos           (2U)

+#define DSI_VCCCR_NUMC2_Msk           (0x1UL << DSI_VCCCR_NUMC2_Pos)           /*!< 0x00000004 */

+#define DSI_VCCCR_NUMC2               DSI_VCCCR_NUMC2_Msk

+#define DSI_VCCCR_NUMC3_Pos           (3U)

+#define DSI_VCCCR_NUMC3_Msk           (0x1UL << DSI_VCCCR_NUMC3_Pos)           /*!< 0x00000008 */

+#define DSI_VCCCR_NUMC3               DSI_VCCCR_NUMC3_Msk

+#define DSI_VCCCR_NUMC4_Pos           (4U)

+#define DSI_VCCCR_NUMC4_Msk           (0x1UL << DSI_VCCCR_NUMC4_Pos)           /*!< 0x00000010 */

+#define DSI_VCCCR_NUMC4               DSI_VCCCR_NUMC4_Msk

+#define DSI_VCCCR_NUMC5_Pos           (5U)

+#define DSI_VCCCR_NUMC5_Msk           (0x1UL << DSI_VCCCR_NUMC5_Pos)           /*!< 0x00000020 */

+#define DSI_VCCCR_NUMC5               DSI_VCCCR_NUMC5_Msk

+#define DSI_VCCCR_NUMC6_Pos           (6U)

+#define DSI_VCCCR_NUMC6_Msk           (0x1UL << DSI_VCCCR_NUMC6_Pos)           /*!< 0x00000040 */

+#define DSI_VCCCR_NUMC6               DSI_VCCCR_NUMC6_Msk

+#define DSI_VCCCR_NUMC7_Pos           (7U)

+#define DSI_VCCCR_NUMC7_Msk           (0x1UL << DSI_VCCCR_NUMC7_Pos)           /*!< 0x00000080 */

+#define DSI_VCCCR_NUMC7               DSI_VCCCR_NUMC7_Msk

+#define DSI_VCCCR_NUMC8_Pos           (8U)

+#define DSI_VCCCR_NUMC8_Msk           (0x1UL << DSI_VCCCR_NUMC8_Pos)           /*!< 0x00000100 */

+#define DSI_VCCCR_NUMC8               DSI_VCCCR_NUMC8_Msk

+#define DSI_VCCCR_NUMC9_Pos           (9U)

+#define DSI_VCCCR_NUMC9_Msk           (0x1UL << DSI_VCCCR_NUMC9_Pos)           /*!< 0x00000200 */

+#define DSI_VCCCR_NUMC9               DSI_VCCCR_NUMC9_Msk

+#define DSI_VCCCR_NUMC10_Pos          (10U)

+#define DSI_VCCCR_NUMC10_Msk          (0x1UL << DSI_VCCCR_NUMC10_Pos)          /*!< 0x00000400 */

+#define DSI_VCCCR_NUMC10              DSI_VCCCR_NUMC10_Msk

+#define DSI_VCCCR_NUMC11_Pos          (11U)

+#define DSI_VCCCR_NUMC11_Msk          (0x1UL << DSI_VCCCR_NUMC11_Pos)          /*!< 0x00000800 */

+#define DSI_VCCCR_NUMC11              DSI_VCCCR_NUMC11_Msk

+#define DSI_VCCCR_NUMC12_Pos          (12U)

+#define DSI_VCCCR_NUMC12_Msk          (0x1UL << DSI_VCCCR_NUMC12_Pos)          /*!< 0x00001000 */

+#define DSI_VCCCR_NUMC12              DSI_VCCCR_NUMC12_Msk

+

+/*******************  Bit definition for DSI_VNPCCR register  *************/

+#define DSI_VNPCCR_NPSIZE_Pos         (0U)

+#define DSI_VNPCCR_NPSIZE_Msk         (0x1FFFUL << DSI_VNPCCR_NPSIZE_Pos)      /*!< 0x00001FFF */

+#define DSI_VNPCCR_NPSIZE             DSI_VNPCCR_NPSIZE_Msk                    /*!< Number of Chunks */

+#define DSI_VNPCCR_NPSIZE0_Pos        (0U)

+#define DSI_VNPCCR_NPSIZE0_Msk        (0x1UL << DSI_VNPCCR_NPSIZE0_Pos)        /*!< 0x00000001 */

+#define DSI_VNPCCR_NPSIZE0            DSI_VNPCCR_NPSIZE0_Msk

+#define DSI_VNPCCR_NPSIZE1_Pos        (1U)

+#define DSI_VNPCCR_NPSIZE1_Msk        (0x1UL << DSI_VNPCCR_NPSIZE1_Pos)        /*!< 0x00000002 */

+#define DSI_VNPCCR_NPSIZE1            DSI_VNPCCR_NPSIZE1_Msk

+#define DSI_VNPCCR_NPSIZE2_Pos        (2U)

+#define DSI_VNPCCR_NPSIZE2_Msk        (0x1UL << DSI_VNPCCR_NPSIZE2_Pos)        /*!< 0x00000004 */

+#define DSI_VNPCCR_NPSIZE2            DSI_VNPCCR_NPSIZE2_Msk

+#define DSI_VNPCCR_NPSIZE3_Pos        (3U)

+#define DSI_VNPCCR_NPSIZE3_Msk        (0x1UL << DSI_VNPCCR_NPSIZE3_Pos)        /*!< 0x00000008 */

+#define DSI_VNPCCR_NPSIZE3            DSI_VNPCCR_NPSIZE3_Msk

+#define DSI_VNPCCR_NPSIZE4_Pos        (4U)

+#define DSI_VNPCCR_NPSIZE4_Msk        (0x1UL << DSI_VNPCCR_NPSIZE4_Pos)        /*!< 0x00000010 */

+#define DSI_VNPCCR_NPSIZE4            DSI_VNPCCR_NPSIZE4_Msk

+#define DSI_VNPCCR_NPSIZE5_Pos        (5U)

+#define DSI_VNPCCR_NPSIZE5_Msk        (0x1UL << DSI_VNPCCR_NPSIZE5_Pos)        /*!< 0x00000020 */

+#define DSI_VNPCCR_NPSIZE5            DSI_VNPCCR_NPSIZE5_Msk

+#define DSI_VNPCCR_NPSIZE6_Pos        (6U)

+#define DSI_VNPCCR_NPSIZE6_Msk        (0x1UL << DSI_VNPCCR_NPSIZE6_Pos)        /*!< 0x00000040 */

+#define DSI_VNPCCR_NPSIZE6            DSI_VNPCCR_NPSIZE6_Msk

+#define DSI_VNPCCR_NPSIZE7_Pos        (7U)

+#define DSI_VNPCCR_NPSIZE7_Msk        (0x1UL << DSI_VNPCCR_NPSIZE7_Pos)        /*!< 0x00000080 */

+#define DSI_VNPCCR_NPSIZE7            DSI_VNPCCR_NPSIZE7_Msk

+#define DSI_VNPCCR_NPSIZE8_Pos        (8U)

+#define DSI_VNPCCR_NPSIZE8_Msk        (0x1UL << DSI_VNPCCR_NPSIZE8_Pos)        /*!< 0x00000100 */

+#define DSI_VNPCCR_NPSIZE8            DSI_VNPCCR_NPSIZE8_Msk

+#define DSI_VNPCCR_NPSIZE9_Pos        (9U)

+#define DSI_VNPCCR_NPSIZE9_Msk        (0x1UL << DSI_VNPCCR_NPSIZE9_Pos)        /*!< 0x00000200 */

+#define DSI_VNPCCR_NPSIZE9            DSI_VNPCCR_NPSIZE9_Msk

+#define DSI_VNPCCR_NPSIZE10_Pos       (10U)

+#define DSI_VNPCCR_NPSIZE10_Msk       (0x1UL << DSI_VNPCCR_NPSIZE10_Pos)       /*!< 0x00000400 */

+#define DSI_VNPCCR_NPSIZE10           DSI_VNPCCR_NPSIZE10_Msk

+#define DSI_VNPCCR_NPSIZE11_Pos       (11U)

+#define DSI_VNPCCR_NPSIZE11_Msk       (0x1UL << DSI_VNPCCR_NPSIZE11_Pos)       /*!< 0x00000800 */

+#define DSI_VNPCCR_NPSIZE11           DSI_VNPCCR_NPSIZE11_Msk

+#define DSI_VNPCCR_NPSIZE12_Pos       (12U)

+#define DSI_VNPCCR_NPSIZE12_Msk       (0x1UL << DSI_VNPCCR_NPSIZE12_Pos)       /*!< 0x00001000 */

+#define DSI_VNPCCR_NPSIZE12           DSI_VNPCCR_NPSIZE12_Msk

+

+/*******************  Bit definition for DSI_VHSACCR register  ************/

+#define DSI_VHSACCR_HSA_Pos           (0U)

+#define DSI_VHSACCR_HSA_Msk           (0xFFFUL << DSI_VHSACCR_HSA_Pos)         /*!< 0x00000FFF */

+#define DSI_VHSACCR_HSA               DSI_VHSACCR_HSA_Msk                      /*!< Horizontal Synchronism Active duration */

+#define DSI_VHSACCR_HSA0_Pos          (0U)

+#define DSI_VHSACCR_HSA0_Msk          (0x1UL << DSI_VHSACCR_HSA0_Pos)          /*!< 0x00000001 */

+#define DSI_VHSACCR_HSA0              DSI_VHSACCR_HSA0_Msk

+#define DSI_VHSACCR_HSA1_Pos          (1U)

+#define DSI_VHSACCR_HSA1_Msk          (0x1UL << DSI_VHSACCR_HSA1_Pos)          /*!< 0x00000002 */

+#define DSI_VHSACCR_HSA1              DSI_VHSACCR_HSA1_Msk

+#define DSI_VHSACCR_HSA2_Pos          (2U)

+#define DSI_VHSACCR_HSA2_Msk          (0x1UL << DSI_VHSACCR_HSA2_Pos)          /*!< 0x00000004 */

+#define DSI_VHSACCR_HSA2              DSI_VHSACCR_HSA2_Msk

+#define DSI_VHSACCR_HSA3_Pos          (3U)

+#define DSI_VHSACCR_HSA3_Msk          (0x1UL << DSI_VHSACCR_HSA3_Pos)          /*!< 0x00000008 */

+#define DSI_VHSACCR_HSA3              DSI_VHSACCR_HSA3_Msk

+#define DSI_VHSACCR_HSA4_Pos          (4U)

+#define DSI_VHSACCR_HSA4_Msk          (0x1UL << DSI_VHSACCR_HSA4_Pos)          /*!< 0x00000010 */

+#define DSI_VHSACCR_HSA4              DSI_VHSACCR_HSA4_Msk

+#define DSI_VHSACCR_HSA5_Pos          (5U)

+#define DSI_VHSACCR_HSA5_Msk          (0x1UL << DSI_VHSACCR_HSA5_Pos)          /*!< 0x00000020 */

+#define DSI_VHSACCR_HSA5              DSI_VHSACCR_HSA5_Msk

+#define DSI_VHSACCR_HSA6_Pos          (6U)

+#define DSI_VHSACCR_HSA6_Msk          (0x1UL << DSI_VHSACCR_HSA6_Pos)          /*!< 0x00000040 */

+#define DSI_VHSACCR_HSA6              DSI_VHSACCR_HSA6_Msk

+#define DSI_VHSACCR_HSA7_Pos          (7U)

+#define DSI_VHSACCR_HSA7_Msk          (0x1UL << DSI_VHSACCR_HSA7_Pos)          /*!< 0x00000080 */

+#define DSI_VHSACCR_HSA7              DSI_VHSACCR_HSA7_Msk

+#define DSI_VHSACCR_HSA8_Pos          (8U)

+#define DSI_VHSACCR_HSA8_Msk          (0x1UL << DSI_VHSACCR_HSA8_Pos)          /*!< 0x00000100 */

+#define DSI_VHSACCR_HSA8              DSI_VHSACCR_HSA8_Msk

+#define DSI_VHSACCR_HSA9_Pos          (9U)

+#define DSI_VHSACCR_HSA9_Msk          (0x1UL << DSI_VHSACCR_HSA9_Pos)          /*!< 0x00000200 */

+#define DSI_VHSACCR_HSA9              DSI_VHSACCR_HSA9_Msk

+#define DSI_VHSACCR_HSA10_Pos         (10U)

+#define DSI_VHSACCR_HSA10_Msk         (0x1UL << DSI_VHSACCR_HSA10_Pos)         /*!< 0x00000400 */

+#define DSI_VHSACCR_HSA10             DSI_VHSACCR_HSA10_Msk

+#define DSI_VHSACCR_HSA11_Pos         (11U)

+#define DSI_VHSACCR_HSA11_Msk         (0x1UL << DSI_VHSACCR_HSA11_Pos)         /*!< 0x00000800 */

+#define DSI_VHSACCR_HSA11             DSI_VHSACCR_HSA11_Msk

+

+/*******************  Bit definition for DSI_VHBPCCR register  ************/

+#define DSI_VHBPCCR_HBP_Pos           (0U)

+#define DSI_VHBPCCR_HBP_Msk           (0xFFFUL << DSI_VHBPCCR_HBP_Pos)         /*!< 0x00000FFF */

+#define DSI_VHBPCCR_HBP               DSI_VHBPCCR_HBP_Msk                      /*!< Horizontal Back-Porch duration */

+#define DSI_VHBPCCR_HBP0_Pos          (0U)

+#define DSI_VHBPCCR_HBP0_Msk          (0x1UL << DSI_VHBPCCR_HBP0_Pos)          /*!< 0x00000001 */

+#define DSI_VHBPCCR_HBP0              DSI_VHBPCCR_HBP0_Msk

+#define DSI_VHBPCCR_HBP1_Pos          (1U)

+#define DSI_VHBPCCR_HBP1_Msk          (0x1UL << DSI_VHBPCCR_HBP1_Pos)          /*!< 0x00000002 */

+#define DSI_VHBPCCR_HBP1              DSI_VHBPCCR_HBP1_Msk

+#define DSI_VHBPCCR_HBP2_Pos          (2U)

+#define DSI_VHBPCCR_HBP2_Msk          (0x1UL << DSI_VHBPCCR_HBP2_Pos)          /*!< 0x00000004 */

+#define DSI_VHBPCCR_HBP2              DSI_VHBPCCR_HBP2_Msk

+#define DSI_VHBPCCR_HBP3_Pos          (3U)

+#define DSI_VHBPCCR_HBP3_Msk          (0x1UL << DSI_VHBPCCR_HBP3_Pos)          /*!< 0x00000008 */

+#define DSI_VHBPCCR_HBP3              DSI_VHBPCCR_HBP3_Msk

+#define DSI_VHBPCCR_HBP4_Pos          (4U)

+#define DSI_VHBPCCR_HBP4_Msk          (0x1UL << DSI_VHBPCCR_HBP4_Pos)          /*!< 0x00000010 */

+#define DSI_VHBPCCR_HBP4              DSI_VHBPCCR_HBP4_Msk

+#define DSI_VHBPCCR_HBP5_Pos          (5U)

+#define DSI_VHBPCCR_HBP5_Msk          (0x1UL << DSI_VHBPCCR_HBP5_Pos)          /*!< 0x00000020 */

+#define DSI_VHBPCCR_HBP5              DSI_VHBPCCR_HBP5_Msk

+#define DSI_VHBPCCR_HBP6_Pos          (6U)

+#define DSI_VHBPCCR_HBP6_Msk          (0x1UL << DSI_VHBPCCR_HBP6_Pos)          /*!< 0x00000040 */

+#define DSI_VHBPCCR_HBP6              DSI_VHBPCCR_HBP6_Msk

+#define DSI_VHBPCCR_HBP7_Pos          (7U)

+#define DSI_VHBPCCR_HBP7_Msk          (0x1UL << DSI_VHBPCCR_HBP7_Pos)          /*!< 0x00000080 */

+#define DSI_VHBPCCR_HBP7              DSI_VHBPCCR_HBP7_Msk

+#define DSI_VHBPCCR_HBP8_Pos          (8U)

+#define DSI_VHBPCCR_HBP8_Msk          (0x1UL << DSI_VHBPCCR_HBP8_Pos)          /*!< 0x00000100 */

+#define DSI_VHBPCCR_HBP8              DSI_VHBPCCR_HBP8_Msk

+#define DSI_VHBPCCR_HBP9_Pos          (9U)

+#define DSI_VHBPCCR_HBP9_Msk          (0x1UL << DSI_VHBPCCR_HBP9_Pos)          /*!< 0x00000200 */

+#define DSI_VHBPCCR_HBP9              DSI_VHBPCCR_HBP9_Msk

+#define DSI_VHBPCCR_HBP10_Pos         (10U)

+#define DSI_VHBPCCR_HBP10_Msk         (0x1UL << DSI_VHBPCCR_HBP10_Pos)         /*!< 0x00000400 */

+#define DSI_VHBPCCR_HBP10             DSI_VHBPCCR_HBP10_Msk

+#define DSI_VHBPCCR_HBP11_Pos         (11U)

+#define DSI_VHBPCCR_HBP11_Msk         (0x1UL << DSI_VHBPCCR_HBP11_Pos)         /*!< 0x00000800 */

+#define DSI_VHBPCCR_HBP11             DSI_VHBPCCR_HBP11_Msk

+

+/*******************  Bit definition for DSI_VLCCR register  **************/

+#define DSI_VLCCR_HLINE_Pos           (0U)

+#define DSI_VLCCR_HLINE_Msk           (0x7FFFUL << DSI_VLCCR_HLINE_Pos)        /*!< 0x00007FFF */

+#define DSI_VLCCR_HLINE               DSI_VLCCR_HLINE_Msk                      /*!< Horizontal Line duration */

+#define DSI_VLCCR_HLINE0_Pos          (0U)

+#define DSI_VLCCR_HLINE0_Msk          (0x1UL << DSI_VLCCR_HLINE0_Pos)          /*!< 0x00000001 */

+#define DSI_VLCCR_HLINE0              DSI_VLCCR_HLINE0_Msk

+#define DSI_VLCCR_HLINE1_Pos          (1U)

+#define DSI_VLCCR_HLINE1_Msk          (0x1UL << DSI_VLCCR_HLINE1_Pos)          /*!< 0x00000002 */

+#define DSI_VLCCR_HLINE1              DSI_VLCCR_HLINE1_Msk

+#define DSI_VLCCR_HLINE2_Pos          (2U)

+#define DSI_VLCCR_HLINE2_Msk          (0x1UL << DSI_VLCCR_HLINE2_Pos)          /*!< 0x00000004 */

+#define DSI_VLCCR_HLINE2              DSI_VLCCR_HLINE2_Msk

+#define DSI_VLCCR_HLINE3_Pos          (3U)

+#define DSI_VLCCR_HLINE3_Msk          (0x1UL << DSI_VLCCR_HLINE3_Pos)          /*!< 0x00000008 */

+#define DSI_VLCCR_HLINE3              DSI_VLCCR_HLINE3_Msk

+#define DSI_VLCCR_HLINE4_Pos          (4U)

+#define DSI_VLCCR_HLINE4_Msk          (0x1UL << DSI_VLCCR_HLINE4_Pos)          /*!< 0x00000010 */

+#define DSI_VLCCR_HLINE4              DSI_VLCCR_HLINE4_Msk

+#define DSI_VLCCR_HLINE5_Pos          (5U)

+#define DSI_VLCCR_HLINE5_Msk          (0x1UL << DSI_VLCCR_HLINE5_Pos)          /*!< 0x00000020 */

+#define DSI_VLCCR_HLINE5              DSI_VLCCR_HLINE5_Msk

+#define DSI_VLCCR_HLINE6_Pos          (6U)

+#define DSI_VLCCR_HLINE6_Msk          (0x1UL << DSI_VLCCR_HLINE6_Pos)          /*!< 0x00000040 */

+#define DSI_VLCCR_HLINE6              DSI_VLCCR_HLINE6_Msk

+#define DSI_VLCCR_HLINE7_Pos          (7U)

+#define DSI_VLCCR_HLINE7_Msk          (0x1UL << DSI_VLCCR_HLINE7_Pos)          /*!< 0x00000080 */

+#define DSI_VLCCR_HLINE7              DSI_VLCCR_HLINE7_Msk

+#define DSI_VLCCR_HLINE8_Pos          (8U)

+#define DSI_VLCCR_HLINE8_Msk          (0x1UL << DSI_VLCCR_HLINE8_Pos)          /*!< 0x00000100 */

+#define DSI_VLCCR_HLINE8              DSI_VLCCR_HLINE8_Msk

+#define DSI_VLCCR_HLINE9_Pos          (9U)

+#define DSI_VLCCR_HLINE9_Msk          (0x1UL << DSI_VLCCR_HLINE9_Pos)          /*!< 0x00000200 */

+#define DSI_VLCCR_HLINE9              DSI_VLCCR_HLINE9_Msk

+#define DSI_VLCCR_HLINE10_Pos         (10U)

+#define DSI_VLCCR_HLINE10_Msk         (0x1UL << DSI_VLCCR_HLINE10_Pos)         /*!< 0x00000400 */

+#define DSI_VLCCR_HLINE10             DSI_VLCCR_HLINE10_Msk

+#define DSI_VLCCR_HLINE11_Pos         (11U)

+#define DSI_VLCCR_HLINE11_Msk         (0x1UL << DSI_VLCCR_HLINE11_Pos)         /*!< 0x00000800 */

+#define DSI_VLCCR_HLINE11             DSI_VLCCR_HLINE11_Msk

+#define DSI_VLCCR_HLINE12_Pos         (12U)

+#define DSI_VLCCR_HLINE12_Msk         (0x1UL << DSI_VLCCR_HLINE12_Pos)         /*!< 0x00001000 */

+#define DSI_VLCCR_HLINE12             DSI_VLCCR_HLINE12_Msk

+#define DSI_VLCCR_HLINE13_Pos         (13U)

+#define DSI_VLCCR_HLINE13_Msk         (0x1UL << DSI_VLCCR_HLINE13_Pos)         /*!< 0x00002000 */

+#define DSI_VLCCR_HLINE13             DSI_VLCCR_HLINE13_Msk

+#define DSI_VLCCR_HLINE14_Pos         (14U)

+#define DSI_VLCCR_HLINE14_Msk         (0x1UL << DSI_VLCCR_HLINE14_Pos)         /*!< 0x00004000 */

+#define DSI_VLCCR_HLINE14             DSI_VLCCR_HLINE14_Msk

+

+/*******************  Bit definition for DSI_VVSACCR register  ***************/

+#define DSI_VVSACCR_VSA_Pos           (0U)

+#define DSI_VVSACCR_VSA_Msk           (0x3FFUL << DSI_VVSACCR_VSA_Pos)         /*!< 0x000003FF */

+#define DSI_VVSACCR_VSA               DSI_VVSACCR_VSA_Msk                      /*!< Vertical Synchronism Active duration */

+#define DSI_VVSACCR_VSA0_Pos          (0U)

+#define DSI_VVSACCR_VSA0_Msk          (0x1UL << DSI_VVSACCR_VSA0_Pos)          /*!< 0x00000001 */

+#define DSI_VVSACCR_VSA0              DSI_VVSACCR_VSA0_Msk

+#define DSI_VVSACCR_VSA1_Pos          (1U)

+#define DSI_VVSACCR_VSA1_Msk          (0x1UL << DSI_VVSACCR_VSA1_Pos)          /*!< 0x00000002 */

+#define DSI_VVSACCR_VSA1              DSI_VVSACCR_VSA1_Msk

+#define DSI_VVSACCR_VSA2_Pos          (2U)

+#define DSI_VVSACCR_VSA2_Msk          (0x1UL << DSI_VVSACCR_VSA2_Pos)          /*!< 0x00000004 */

+#define DSI_VVSACCR_VSA2              DSI_VVSACCR_VSA2_Msk

+#define DSI_VVSACCR_VSA3_Pos          (3U)

+#define DSI_VVSACCR_VSA3_Msk          (0x1UL << DSI_VVSACCR_VSA3_Pos)          /*!< 0x00000008 */

+#define DSI_VVSACCR_VSA3              DSI_VVSACCR_VSA3_Msk

+#define DSI_VVSACCR_VSA4_Pos          (4U)

+#define DSI_VVSACCR_VSA4_Msk          (0x1UL << DSI_VVSACCR_VSA4_Pos)          /*!< 0x00000010 */

+#define DSI_VVSACCR_VSA4              DSI_VVSACCR_VSA4_Msk

+#define DSI_VVSACCR_VSA5_Pos          (5U)

+#define DSI_VVSACCR_VSA5_Msk          (0x1UL << DSI_VVSACCR_VSA5_Pos)          /*!< 0x00000020 */

+#define DSI_VVSACCR_VSA5              DSI_VVSACCR_VSA5_Msk

+#define DSI_VVSACCR_VSA6_Pos          (6U)

+#define DSI_VVSACCR_VSA6_Msk          (0x1UL << DSI_VVSACCR_VSA6_Pos)          /*!< 0x00000040 */

+#define DSI_VVSACCR_VSA6              DSI_VVSACCR_VSA6_Msk

+#define DSI_VVSACCR_VSA7_Pos          (7U)

+#define DSI_VVSACCR_VSA7_Msk          (0x1UL << DSI_VVSACCR_VSA7_Pos)          /*!< 0x00000080 */

+#define DSI_VVSACCR_VSA7              DSI_VVSACCR_VSA7_Msk

+#define DSI_VVSACCR_VSA8_Pos          (8U)

+#define DSI_VVSACCR_VSA8_Msk          (0x1UL << DSI_VVSACCR_VSA8_Pos)          /*!< 0x00000100 */

+#define DSI_VVSACCR_VSA8              DSI_VVSACCR_VSA8_Msk

+#define DSI_VVSACCR_VSA9_Pos          (9U)

+#define DSI_VVSACCR_VSA9_Msk          (0x1UL << DSI_VVSACCR_VSA9_Pos)          /*!< 0x00000200 */

+#define DSI_VVSACCR_VSA9              DSI_VVSACCR_VSA9_Msk

+

+/*******************  Bit definition for DSI_VVBPCCR register  ************/

+#define DSI_VVBPCCR_VBP_Pos           (0U)

+#define DSI_VVBPCCR_VBP_Msk           (0x3FFUL << DSI_VVBPCCR_VBP_Pos)         /*!< 0x000003FF */

+#define DSI_VVBPCCR_VBP               DSI_VVBPCCR_VBP_Msk                      /*!< Vertical Back-Porch duration */

+#define DSI_VVBPCCR_VBP0_Pos          (0U)

+#define DSI_VVBPCCR_VBP0_Msk          (0x1UL << DSI_VVBPCCR_VBP0_Pos)          /*!< 0x00000001 */

+#define DSI_VVBPCCR_VBP0              DSI_VVBPCCR_VBP0_Msk

+#define DSI_VVBPCCR_VBP1_Pos          (1U)

+#define DSI_VVBPCCR_VBP1_Msk          (0x1UL << DSI_VVBPCCR_VBP1_Pos)          /*!< 0x00000002 */

+#define DSI_VVBPCCR_VBP1              DSI_VVBPCCR_VBP1_Msk

+#define DSI_VVBPCCR_VBP2_Pos          (2U)

+#define DSI_VVBPCCR_VBP2_Msk          (0x1UL << DSI_VVBPCCR_VBP2_Pos)          /*!< 0x00000004 */

+#define DSI_VVBPCCR_VBP2              DSI_VVBPCCR_VBP2_Msk

+#define DSI_VVBPCCR_VBP3_Pos          (3U)

+#define DSI_VVBPCCR_VBP3_Msk          (0x1UL << DSI_VVBPCCR_VBP3_Pos)          /*!< 0x00000008 */

+#define DSI_VVBPCCR_VBP3              DSI_VVBPCCR_VBP3_Msk

+#define DSI_VVBPCCR_VBP4_Pos          (4U)

+#define DSI_VVBPCCR_VBP4_Msk          (0x1UL << DSI_VVBPCCR_VBP4_Pos)          /*!< 0x00000010 */

+#define DSI_VVBPCCR_VBP4              DSI_VVBPCCR_VBP4_Msk

+#define DSI_VVBPCCR_VBP5_Pos          (5U)

+#define DSI_VVBPCCR_VBP5_Msk          (0x1UL << DSI_VVBPCCR_VBP5_Pos)          /*!< 0x00000020 */

+#define DSI_VVBPCCR_VBP5              DSI_VVBPCCR_VBP5_Msk

+#define DSI_VVBPCCR_VBP6_Pos          (6U)

+#define DSI_VVBPCCR_VBP6_Msk          (0x1UL << DSI_VVBPCCR_VBP6_Pos)          /*!< 0x00000040 */

+#define DSI_VVBPCCR_VBP6              DSI_VVBPCCR_VBP6_Msk

+#define DSI_VVBPCCR_VBP7_Pos          (7U)

+#define DSI_VVBPCCR_VBP7_Msk          (0x1UL << DSI_VVBPCCR_VBP7_Pos)          /*!< 0x00000080 */

+#define DSI_VVBPCCR_VBP7              DSI_VVBPCCR_VBP7_Msk

+#define DSI_VVBPCCR_VBP8_Pos          (8U)

+#define DSI_VVBPCCR_VBP8_Msk          (0x1UL << DSI_VVBPCCR_VBP8_Pos)          /*!< 0x00000100 */

+#define DSI_VVBPCCR_VBP8              DSI_VVBPCCR_VBP8_Msk

+#define DSI_VVBPCCR_VBP9_Pos          (9U)

+#define DSI_VVBPCCR_VBP9_Msk          (0x1UL << DSI_VVBPCCR_VBP9_Pos)          /*!< 0x00000200 */

+#define DSI_VVBPCCR_VBP9              DSI_VVBPCCR_VBP9_Msk

+

+/*******************  Bit definition for DSI_VVFPCCR register  ************/

+#define DSI_VVFPCCR_VFP_Pos           (0U)

+#define DSI_VVFPCCR_VFP_Msk           (0x3FFUL << DSI_VVFPCCR_VFP_Pos)         /*!< 0x000003FF */

+#define DSI_VVFPCCR_VFP               DSI_VVFPCCR_VFP_Msk                      /*!< Vertical Front-Porch duration */

+#define DSI_VVFPCCR_VFP0_Pos          (0U)

+#define DSI_VVFPCCR_VFP0_Msk          (0x1UL << DSI_VVFPCCR_VFP0_Pos)          /*!< 0x00000001 */

+#define DSI_VVFPCCR_VFP0              DSI_VVFPCCR_VFP0_Msk

+#define DSI_VVFPCCR_VFP1_Pos          (1U)

+#define DSI_VVFPCCR_VFP1_Msk          (0x1UL << DSI_VVFPCCR_VFP1_Pos)          /*!< 0x00000002 */

+#define DSI_VVFPCCR_VFP1              DSI_VVFPCCR_VFP1_Msk

+#define DSI_VVFPCCR_VFP2_Pos          (2U)

+#define DSI_VVFPCCR_VFP2_Msk          (0x1UL << DSI_VVFPCCR_VFP2_Pos)          /*!< 0x00000004 */

+#define DSI_VVFPCCR_VFP2              DSI_VVFPCCR_VFP2_Msk

+#define DSI_VVFPCCR_VFP3_Pos          (3U)

+#define DSI_VVFPCCR_VFP3_Msk          (0x1UL << DSI_VVFPCCR_VFP3_Pos)          /*!< 0x00000008 */

+#define DSI_VVFPCCR_VFP3              DSI_VVFPCCR_VFP3_Msk

+#define DSI_VVFPCCR_VFP4_Pos          (4U)

+#define DSI_VVFPCCR_VFP4_Msk          (0x1UL << DSI_VVFPCCR_VFP4_Pos)          /*!< 0x00000010 */

+#define DSI_VVFPCCR_VFP4              DSI_VVFPCCR_VFP4_Msk

+#define DSI_VVFPCCR_VFP5_Pos          (5U)

+#define DSI_VVFPCCR_VFP5_Msk          (0x1UL << DSI_VVFPCCR_VFP5_Pos)          /*!< 0x00000020 */

+#define DSI_VVFPCCR_VFP5              DSI_VVFPCCR_VFP5_Msk

+#define DSI_VVFPCCR_VFP6_Pos          (6U)

+#define DSI_VVFPCCR_VFP6_Msk          (0x1UL << DSI_VVFPCCR_VFP6_Pos)          /*!< 0x00000040 */

+#define DSI_VVFPCCR_VFP6              DSI_VVFPCCR_VFP6_Msk

+#define DSI_VVFPCCR_VFP7_Pos          (7U)

+#define DSI_VVFPCCR_VFP7_Msk          (0x1UL << DSI_VVFPCCR_VFP7_Pos)          /*!< 0x00000080 */

+#define DSI_VVFPCCR_VFP7              DSI_VVFPCCR_VFP7_Msk

+#define DSI_VVFPCCR_VFP8_Pos          (8U)

+#define DSI_VVFPCCR_VFP8_Msk          (0x1UL << DSI_VVFPCCR_VFP8_Pos)          /*!< 0x00000100 */

+#define DSI_VVFPCCR_VFP8              DSI_VVFPCCR_VFP8_Msk

+#define DSI_VVFPCCR_VFP9_Pos          (9U)

+#define DSI_VVFPCCR_VFP9_Msk          (0x1UL << DSI_VVFPCCR_VFP9_Pos)          /*!< 0x00000200 */

+#define DSI_VVFPCCR_VFP9              DSI_VVFPCCR_VFP9_Msk

+

+/*******************  Bit definition for DSI_VVACCR register  *************/

+#define DSI_VVACCR_VA_Pos             (0U)

+#define DSI_VVACCR_VA_Msk             (0x3FFFUL << DSI_VVACCR_VA_Pos)          /*!< 0x00003FFF */

+#define DSI_VVACCR_VA                 DSI_VVACCR_VA_Msk                        /*!< Vertical Active duration */

+#define DSI_VVACCR_VA0_Pos            (0U)

+#define DSI_VVACCR_VA0_Msk            (0x1UL << DSI_VVACCR_VA0_Pos)            /*!< 0x00000001 */

+#define DSI_VVACCR_VA0                DSI_VVACCR_VA0_Msk

+#define DSI_VVACCR_VA1_Pos            (1U)

+#define DSI_VVACCR_VA1_Msk            (0x1UL << DSI_VVACCR_VA1_Pos)            /*!< 0x00000002 */

+#define DSI_VVACCR_VA1                DSI_VVACCR_VA1_Msk

+#define DSI_VVACCR_VA2_Pos            (2U)

+#define DSI_VVACCR_VA2_Msk            (0x1UL << DSI_VVACCR_VA2_Pos)            /*!< 0x00000004 */

+#define DSI_VVACCR_VA2                DSI_VVACCR_VA2_Msk

+#define DSI_VVACCR_VA3_Pos            (3U)

+#define DSI_VVACCR_VA3_Msk            (0x1UL << DSI_VVACCR_VA3_Pos)            /*!< 0x00000008 */

+#define DSI_VVACCR_VA3                DSI_VVACCR_VA3_Msk

+#define DSI_VVACCR_VA4_Pos            (4U)

+#define DSI_VVACCR_VA4_Msk            (0x1UL << DSI_VVACCR_VA4_Pos)            /*!< 0x00000010 */

+#define DSI_VVACCR_VA4                DSI_VVACCR_VA4_Msk

+#define DSI_VVACCR_VA5_Pos            (5U)

+#define DSI_VVACCR_VA5_Msk            (0x1UL << DSI_VVACCR_VA5_Pos)            /*!< 0x00000020 */

+#define DSI_VVACCR_VA5                DSI_VVACCR_VA5_Msk

+#define DSI_VVACCR_VA6_Pos            (6U)

+#define DSI_VVACCR_VA6_Msk            (0x1UL << DSI_VVACCR_VA6_Pos)            /*!< 0x00000040 */

+#define DSI_VVACCR_VA6                DSI_VVACCR_VA6_Msk

+#define DSI_VVACCR_VA7_Pos            (7U)

+#define DSI_VVACCR_VA7_Msk            (0x1UL << DSI_VVACCR_VA7_Pos)            /*!< 0x00000080 */

+#define DSI_VVACCR_VA7                DSI_VVACCR_VA7_Msk

+#define DSI_VVACCR_VA8_Pos            (8U)

+#define DSI_VVACCR_VA8_Msk            (0x1UL << DSI_VVACCR_VA8_Pos)            /*!< 0x00000100 */

+#define DSI_VVACCR_VA8                DSI_VVACCR_VA8_Msk

+#define DSI_VVACCR_VA9_Pos            (9U)

+#define DSI_VVACCR_VA9_Msk            (0x1UL << DSI_VVACCR_VA9_Pos)            /*!< 0x00000200 */

+#define DSI_VVACCR_VA9                DSI_VVACCR_VA9_Msk

+#define DSI_VVACCR_VA10_Pos           (10U)

+#define DSI_VVACCR_VA10_Msk           (0x1UL << DSI_VVACCR_VA10_Pos)           /*!< 0x00000400 */

+#define DSI_VVACCR_VA10               DSI_VVACCR_VA10_Msk

+#define DSI_VVACCR_VA11_Pos           (11U)

+#define DSI_VVACCR_VA11_Msk           (0x1UL << DSI_VVACCR_VA11_Pos)           /*!< 0x00000800 */

+#define DSI_VVACCR_VA11               DSI_VVACCR_VA11_Msk

+#define DSI_VVACCR_VA12_Pos           (12U)

+#define DSI_VVACCR_VA12_Msk           (0x1UL << DSI_VVACCR_VA12_Pos)           /*!< 0x00001000 */

+#define DSI_VVACCR_VA12               DSI_VVACCR_VA12_Msk

+#define DSI_VVACCR_VA13_Pos           (13U)

+#define DSI_VVACCR_VA13_Msk           (0x1UL << DSI_VVACCR_VA13_Pos)           /*!< 0x00002000 */

+#define DSI_VVACCR_VA13               DSI_VVACCR_VA13_Msk

+

+/*******************  Bit definition for DSI_TDCCR register  **************/

+#define DSI_TDCCR_3DM                 ((uint32_t)0x00000003U)                  /*!< 3D Mode */

+#define DSI_TDCCR_3DM0                ((uint32_t)0x00000001U)

+#define DSI_TDCCR_3DM1                ((uint32_t)0x00000002U)

+

+#define DSI_TDCCR_3DF                 ((uint32_t)0x0000000CU)                  /*!< 3D Format */

+#define DSI_TDCCR_3DF0                ((uint32_t)0x00000004U)

+#define DSI_TDCCR_3DF1                ((uint32_t)0x00000008U)

+

+#define DSI_TDCCR_SVS_Pos             (4U)

+#define DSI_TDCCR_SVS_Msk             (0x1UL << DSI_TDCCR_SVS_Pos)             /*!< 0x00000010 */

+#define DSI_TDCCR_SVS                 DSI_TDCCR_SVS_Msk                        /*!< Second VSYNC */

+#define DSI_TDCCR_RF_Pos              (5U)

+#define DSI_TDCCR_RF_Msk              (0x1UL << DSI_TDCCR_RF_Pos)              /*!< 0x00000020 */

+#define DSI_TDCCR_RF                  DSI_TDCCR_RF_Msk                         /*!< Right First */

+#define DSI_TDCCR_S3DC_Pos            (16U)

+#define DSI_TDCCR_S3DC_Msk            (0x1UL << DSI_TDCCR_S3DC_Pos)            /*!< 0x00010000 */

+#define DSI_TDCCR_S3DC                DSI_TDCCR_S3DC_Msk                       /*!< Send 3D Control */

+

+/*******************  Bit definition for DSI_WCFGR register  ***************/

+#define DSI_WCFGR_DSIM_Pos            (0U)

+#define DSI_WCFGR_DSIM_Msk            (0x1UL << DSI_WCFGR_DSIM_Pos)            /*!< 0x00000001 */

+#define DSI_WCFGR_DSIM                DSI_WCFGR_DSIM_Msk                       /*!< DSI Mode */

+#define DSI_WCFGR_COLMUX_Pos          (1U)

+#define DSI_WCFGR_COLMUX_Msk          (0x7UL << DSI_WCFGR_COLMUX_Pos)          /*!< 0x0000000E */

+#define DSI_WCFGR_COLMUX              DSI_WCFGR_COLMUX_Msk                     /*!< Color Multiplexing */

+#define DSI_WCFGR_COLMUX0_Pos         (1U)

+#define DSI_WCFGR_COLMUX0_Msk         (0x1UL << DSI_WCFGR_COLMUX0_Pos)         /*!< 0x00000002 */

+#define DSI_WCFGR_COLMUX0             DSI_WCFGR_COLMUX0_Msk

+#define DSI_WCFGR_COLMUX1_Pos         (2U)

+#define DSI_WCFGR_COLMUX1_Msk         (0x1UL << DSI_WCFGR_COLMUX1_Pos)         /*!< 0x00000004 */

+#define DSI_WCFGR_COLMUX1             DSI_WCFGR_COLMUX1_Msk

+#define DSI_WCFGR_COLMUX2_Pos         (3U)

+#define DSI_WCFGR_COLMUX2_Msk         (0x1UL << DSI_WCFGR_COLMUX2_Pos)         /*!< 0x00000008 */

+#define DSI_WCFGR_COLMUX2             DSI_WCFGR_COLMUX2_Msk

+

+#define DSI_WCFGR_TESRC_Pos           (4U)

+#define DSI_WCFGR_TESRC_Msk           (0x1UL << DSI_WCFGR_TESRC_Pos)           /*!< 0x00000010 */

+#define DSI_WCFGR_TESRC               DSI_WCFGR_TESRC_Msk                      /*!< Tearing Effect Source */

+#define DSI_WCFGR_TEPOL_Pos           (5U)

+#define DSI_WCFGR_TEPOL_Msk           (0x1UL << DSI_WCFGR_TEPOL_Pos)           /*!< 0x00000020 */

+#define DSI_WCFGR_TEPOL               DSI_WCFGR_TEPOL_Msk                      /*!< Tearing Effect Polarity */

+#define DSI_WCFGR_AR_Pos              (6U)

+#define DSI_WCFGR_AR_Msk              (0x1UL << DSI_WCFGR_AR_Pos)              /*!< 0x00000040 */

+#define DSI_WCFGR_AR                  DSI_WCFGR_AR_Msk                         /*!< Automatic Refresh */

+#define DSI_WCFGR_VSPOL_Pos           (7U)

+#define DSI_WCFGR_VSPOL_Msk           (0x1UL << DSI_WCFGR_VSPOL_Pos)           /*!< 0x00000080 */

+#define DSI_WCFGR_VSPOL               DSI_WCFGR_VSPOL_Msk                      /*!< VSync Polarity */

+

+/*******************  Bit definition for DSI_WCR register  *****************/

+#define DSI_WCR_COLM_Pos              (0U)

+#define DSI_WCR_COLM_Msk              (0x1UL << DSI_WCR_COLM_Pos)              /*!< 0x00000001 */

+#define DSI_WCR_COLM                  DSI_WCR_COLM_Msk                         /*!< Color Mode */

+#define DSI_WCR_SHTDN_Pos             (1U)

+#define DSI_WCR_SHTDN_Msk             (0x1UL << DSI_WCR_SHTDN_Pos)             /*!< 0x00000002 */

+#define DSI_WCR_SHTDN                 DSI_WCR_SHTDN_Msk                        /*!< Shutdown */

+#define DSI_WCR_LTDCEN_Pos            (2U)

+#define DSI_WCR_LTDCEN_Msk            (0x1UL << DSI_WCR_LTDCEN_Pos)            /*!< 0x00000004 */

+#define DSI_WCR_LTDCEN                DSI_WCR_LTDCEN_Msk                       /*!< LTDC Enable */

+#define DSI_WCR_DSIEN_Pos             (3U)

+#define DSI_WCR_DSIEN_Msk             (0x1UL << DSI_WCR_DSIEN_Pos)             /*!< 0x00000008 */

+#define DSI_WCR_DSIEN                 DSI_WCR_DSIEN_Msk                        /*!< DSI Enable */

+

+/*******************  Bit definition for DSI_WIER register  ****************/

+#define DSI_WIER_TEIE_Pos             (0U)

+#define DSI_WIER_TEIE_Msk             (0x1UL << DSI_WIER_TEIE_Pos)             /*!< 0x00000001 */

+#define DSI_WIER_TEIE                 DSI_WIER_TEIE_Msk                        /*!< Tearing Effect Interrupt Enable */

+#define DSI_WIER_ERIE_Pos             (1U)

+#define DSI_WIER_ERIE_Msk             (0x1UL << DSI_WIER_ERIE_Pos)             /*!< 0x00000002 */

+#define DSI_WIER_ERIE                 DSI_WIER_ERIE_Msk                        /*!< End of Refresh Interrupt Enable */

+#define DSI_WIER_PLLLIE_Pos           (9U)

+#define DSI_WIER_PLLLIE_Msk           (0x1UL << DSI_WIER_PLLLIE_Pos)           /*!< 0x00000200 */

+#define DSI_WIER_PLLLIE               DSI_WIER_PLLLIE_Msk                      /*!< PLL Lock Interrupt Enable */

+#define DSI_WIER_PLLUIE_Pos           (10U)

+#define DSI_WIER_PLLUIE_Msk           (0x1UL << DSI_WIER_PLLUIE_Pos)           /*!< 0x00000400 */

+#define DSI_WIER_PLLUIE               DSI_WIER_PLLUIE_Msk                      /*!< PLL Unlock Interrupt Enable */

+#define DSI_WIER_RRIE_Pos             (13U)

+#define DSI_WIER_RRIE_Msk             (0x1UL << DSI_WIER_RRIE_Pos)             /*!< 0x00002000 */

+#define DSI_WIER_RRIE                 DSI_WIER_RRIE_Msk                        /*!< Regulator Ready Interrupt Enable */

+

+/*******************  Bit definition for DSI_WISR register  ****************/

+#define DSI_WISR_TEIF_Pos             (0U)

+#define DSI_WISR_TEIF_Msk             (0x1UL << DSI_WISR_TEIF_Pos)             /*!< 0x00000001 */

+#define DSI_WISR_TEIF                 DSI_WISR_TEIF_Msk                        /*!< Tearing Effect Interrupt Flag */

+#define DSI_WISR_ERIF_Pos             (1U)

+#define DSI_WISR_ERIF_Msk             (0x1UL << DSI_WISR_ERIF_Pos)             /*!< 0x00000002 */

+#define DSI_WISR_ERIF                 DSI_WISR_ERIF_Msk                        /*!< End of Refresh Interrupt Flag */

+#define DSI_WISR_BUSY_Pos             (2U)

+#define DSI_WISR_BUSY_Msk             (0x1UL << DSI_WISR_BUSY_Pos)             /*!< 0x00000004 */

+#define DSI_WISR_BUSY                 DSI_WISR_BUSY_Msk                        /*!< Busy Flag */

+#define DSI_WISR_PLLLS_Pos            (8U)

+#define DSI_WISR_PLLLS_Msk            (0x1UL << DSI_WISR_PLLLS_Pos)            /*!< 0x00000100 */

+#define DSI_WISR_PLLLS                DSI_WISR_PLLLS_Msk                       /*!< PLL Lock Status */

+#define DSI_WISR_PLLLIF_Pos           (9U)

+#define DSI_WISR_PLLLIF_Msk           (0x1UL << DSI_WISR_PLLLIF_Pos)           /*!< 0x00000200 */

+#define DSI_WISR_PLLLIF               DSI_WISR_PLLLIF_Msk                      /*!< PLL Lock Interrupt Flag */

+#define DSI_WISR_PLLUIF_Pos           (10U)

+#define DSI_WISR_PLLUIF_Msk           (0x1UL << DSI_WISR_PLLUIF_Pos)           /*!< 0x00000400 */

+#define DSI_WISR_PLLUIF               DSI_WISR_PLLUIF_Msk                      /*!< PLL Unlock Interrupt Flag */

+#define DSI_WISR_RRS_Pos              (12U)

+#define DSI_WISR_RRS_Msk              (0x1UL << DSI_WISR_RRS_Pos)              /*!< 0x00001000 */

+#define DSI_WISR_RRS                  DSI_WISR_RRS_Msk                         /*!< Regulator Ready Flag */

+#define DSI_WISR_RRIF_Pos             (13U)

+#define DSI_WISR_RRIF_Msk             (0x1UL << DSI_WISR_RRIF_Pos)             /*!< 0x00002000 */

+#define DSI_WISR_RRIF                 DSI_WISR_RRIF_Msk                        /*!< Regulator Ready Interrupt Flag */

+

+/*******************  Bit definition for DSI_WIFCR register  ***************/

+#define DSI_WIFCR_CTEIF_Pos           (0U)

+#define DSI_WIFCR_CTEIF_Msk           (0x1UL << DSI_WIFCR_CTEIF_Pos)           /*!< 0x00000001 */

+#define DSI_WIFCR_CTEIF               DSI_WIFCR_CTEIF_Msk                      /*!< Clear Tearing Effect Interrupt Flag */

+#define DSI_WIFCR_CERIF_Pos           (1U)

+#define DSI_WIFCR_CERIF_Msk           (0x1UL << DSI_WIFCR_CERIF_Pos)           /*!< 0x00000002 */

+#define DSI_WIFCR_CERIF               DSI_WIFCR_CERIF_Msk                      /*!< Clear End of Refresh Interrupt Flag */

+#define DSI_WIFCR_CPLLLIF_Pos         (9U)

+#define DSI_WIFCR_CPLLLIF_Msk         (0x1UL << DSI_WIFCR_CPLLLIF_Pos)         /*!< 0x00000200 */

+#define DSI_WIFCR_CPLLLIF             DSI_WIFCR_CPLLLIF_Msk                    /*!< Clear PLL Lock Interrupt Flag */

+#define DSI_WIFCR_CPLLUIF_Pos         (10U)

+#define DSI_WIFCR_CPLLUIF_Msk         (0x1UL << DSI_WIFCR_CPLLUIF_Pos)         /*!< 0x00000400 */

+#define DSI_WIFCR_CPLLUIF             DSI_WIFCR_CPLLUIF_Msk                    /*!< Clear PLL Unlock Interrupt Flag */

+#define DSI_WIFCR_CRRIF_Pos           (13U)

+#define DSI_WIFCR_CRRIF_Msk           (0x1UL << DSI_WIFCR_CRRIF_Pos)           /*!< 0x00002000 */

+#define DSI_WIFCR_CRRIF               DSI_WIFCR_CRRIF_Msk                      /*!< Clear Regulator Ready Interrupt Flag */

+

+/*******************  Bit definition for DSI_WPCR0 register  ***************/

+#define DSI_WPCR0_UIX4_Pos            (0U)

+#define DSI_WPCR0_UIX4_Msk            (0x3FUL << DSI_WPCR0_UIX4_Pos)           /*!< 0x0000003F */

+#define DSI_WPCR0_UIX4                DSI_WPCR0_UIX4_Msk                       /*!< Unit Interval multiplied by 4 */

+#define DSI_WPCR0_UIX4_0              (0x01UL << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000001 */

+#define DSI_WPCR0_UIX4_1              (0x02UL << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000002 */

+#define DSI_WPCR0_UIX4_2              (0x04UL << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000004 */

+#define DSI_WPCR0_UIX4_3              (0x08UL << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000008 */

+#define DSI_WPCR0_UIX4_4              (0x10UL << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000010 */

+#define DSI_WPCR0_UIX4_5              (0x20UL << DSI_WPCR0_UIX4_Pos)            /*!< 0x00000020 */

+

+#define DSI_WPCR0_SWCL_Pos            (6U)

+#define DSI_WPCR0_SWCL_Msk            (0x1UL << DSI_WPCR0_SWCL_Pos)            /*!< 0x00000040 */

+#define DSI_WPCR0_SWCL                DSI_WPCR0_SWCL_Msk                       /*!< Swap pins on clock lane */

+#define DSI_WPCR0_SWDL0_Pos           (7U)

+#define DSI_WPCR0_SWDL0_Msk           (0x1UL << DSI_WPCR0_SWDL0_Pos)           /*!< 0x00000080 */

+#define DSI_WPCR0_SWDL0               DSI_WPCR0_SWDL0_Msk                      /*!< Swap pins on data lane 1 */

+#define DSI_WPCR0_SWDL1_Pos           (8U)

+#define DSI_WPCR0_SWDL1_Msk           (0x1UL << DSI_WPCR0_SWDL1_Pos)           /*!< 0x00000100 */

+#define DSI_WPCR0_SWDL1               DSI_WPCR0_SWDL1_Msk                      /*!< Swap pins on data lane 2 */

+#define DSI_WPCR0_HSICL_Pos           (9U)

+#define DSI_WPCR0_HSICL_Msk           (0x1UL << DSI_WPCR0_HSICL_Pos)           /*!< 0x00000200 */

+#define DSI_WPCR0_HSICL               DSI_WPCR0_HSICL_Msk                      /*!< Invert the high-speed data signal on clock lane */

+#define DSI_WPCR0_HSIDL0_Pos          (10U)

+#define DSI_WPCR0_HSIDL0_Msk          (0x1UL << DSI_WPCR0_HSIDL0_Pos)          /*!< 0x00000400 */

+#define DSI_WPCR0_HSIDL0              DSI_WPCR0_HSIDL0_Msk                     /*!< Invert the high-speed data signal on lane 1 */

+#define DSI_WPCR0_HSIDL1_Pos          (11U)

+#define DSI_WPCR0_HSIDL1_Msk          (0x1UL << DSI_WPCR0_HSIDL1_Pos)          /*!< 0x00000800 */

+#define DSI_WPCR0_HSIDL1              DSI_WPCR0_HSIDL1_Msk                     /*!< Invert the high-speed data signal on lane 2 */

+#define DSI_WPCR0_FTXSMCL_Pos         (12U)

+#define DSI_WPCR0_FTXSMCL_Msk         (0x1UL << DSI_WPCR0_FTXSMCL_Pos)         /*!< 0x00001000 */

+#define DSI_WPCR0_FTXSMCL             DSI_WPCR0_FTXSMCL_Msk                    /*!< Force clock lane in TX stop mode */

+#define DSI_WPCR0_FTXSMDL_Pos         (13U)

+#define DSI_WPCR0_FTXSMDL_Msk         (0x1UL << DSI_WPCR0_FTXSMDL_Pos)         /*!< 0x00002000 */

+#define DSI_WPCR0_FTXSMDL             DSI_WPCR0_FTXSMDL_Msk                    /*!< Force data lanes in TX stop mode */

+#define DSI_WPCR0_CDOFFDL_Pos         (14U)

+#define DSI_WPCR0_CDOFFDL_Msk         (0x1UL << DSI_WPCR0_CDOFFDL_Pos)         /*!< 0x00004000 */

+#define DSI_WPCR0_CDOFFDL             DSI_WPCR0_CDOFFDL_Msk                    /*!< Contention detection OFF */

+#define DSI_WPCR0_TDDL_Pos            (16U)

+#define DSI_WPCR0_TDDL_Msk            (0x1UL << DSI_WPCR0_TDDL_Pos)            /*!< 0x00010000 */

+#define DSI_WPCR0_TDDL                DSI_WPCR0_TDDL_Msk                       /*!< Turn Disable Data Lanes */

+#define DSI_WPCR0_PDEN_Pos            (18U)

+#define DSI_WPCR0_PDEN_Msk            (0x1UL << DSI_WPCR0_PDEN_Pos)            /*!< 0x00040000 */

+#define DSI_WPCR0_PDEN                DSI_WPCR0_PDEN_Msk                       /*!< Pull-Down Enable */

+#define DSI_WPCR0_TCLKPREPEN_Pos      (19U)

+#define DSI_WPCR0_TCLKPREPEN_Msk      (0x1UL << DSI_WPCR0_TCLKPREPEN_Pos)      /*!< 0x00080000 */

+#define DSI_WPCR0_TCLKPREPEN          DSI_WPCR0_TCLKPREPEN_Msk                 /*!< Timer for t-CLKPREP Enable */

+#define DSI_WPCR0_TCLKZEROEN_Pos      (20U)

+#define DSI_WPCR0_TCLKZEROEN_Msk      (0x1UL << DSI_WPCR0_TCLKZEROEN_Pos)      /*!< 0x00100000 */

+#define DSI_WPCR0_TCLKZEROEN          DSI_WPCR0_TCLKZEROEN_Msk                 /*!< Timer for t-CLKZERO Enable */

+#define DSI_WPCR0_THSPREPEN_Pos       (21U)

+#define DSI_WPCR0_THSPREPEN_Msk       (0x1UL << DSI_WPCR0_THSPREPEN_Pos)       /*!< 0x00200000 */

+#define DSI_WPCR0_THSPREPEN           DSI_WPCR0_THSPREPEN_Msk                  /*!< Timer for t-HSPREP Enable */

+#define DSI_WPCR0_THSTRAILEN_Pos      (22U)

+#define DSI_WPCR0_THSTRAILEN_Msk      (0x1UL << DSI_WPCR0_THSTRAILEN_Pos)      /*!< 0x00400000 */

+#define DSI_WPCR0_THSTRAILEN          DSI_WPCR0_THSTRAILEN_Msk                 /*!< Timer for t-HSTRAIL Enable */

+#define DSI_WPCR0_THSZEROEN_Pos       (23U)

+#define DSI_WPCR0_THSZEROEN_Msk       (0x1UL << DSI_WPCR0_THSZEROEN_Pos)       /*!< 0x00800000 */

+#define DSI_WPCR0_THSZEROEN           DSI_WPCR0_THSZEROEN_Msk                  /*!< Timer for t-HSZERO Enable */

+#define DSI_WPCR0_TLPXDEN_Pos         (24U)

+#define DSI_WPCR0_TLPXDEN_Msk         (0x1UL << DSI_WPCR0_TLPXDEN_Pos)         /*!< 0x01000000 */

+#define DSI_WPCR0_TLPXDEN             DSI_WPCR0_TLPXDEN_Msk                    /*!< Timer for t-LPXD Enable */

+#define DSI_WPCR0_THSEXITEN_Pos       (25U)

+#define DSI_WPCR0_THSEXITEN_Msk       (0x1UL << DSI_WPCR0_THSEXITEN_Pos)       /*!< 0x02000000 */

+#define DSI_WPCR0_THSEXITEN           DSI_WPCR0_THSEXITEN_Msk                  /*!< Timer for t-HSEXIT Enable */

+#define DSI_WPCR0_TLPXCEN_Pos         (26U)

+#define DSI_WPCR0_TLPXCEN_Msk         (0x1UL << DSI_WPCR0_TLPXCEN_Pos)         /*!< 0x04000000 */

+#define DSI_WPCR0_TLPXCEN             DSI_WPCR0_TLPXCEN_Msk                    /*!< Timer for t-LPXC Enable */

+#define DSI_WPCR0_TCLKPOSTEN_Pos      (27U)

+#define DSI_WPCR0_TCLKPOSTEN_Msk      (0x1UL << DSI_WPCR0_TCLKPOSTEN_Pos)      /*!< 0x08000000 */

+#define DSI_WPCR0_TCLKPOSTEN          DSI_WPCR0_TCLKPOSTEN_Msk                 /*!< Timer for t-CLKPOST Enable */

+

+/*******************  Bit definition for DSI_WPCR1 register  ***************/

+#define DSI_WPCR1_HSTXDCL_Pos         (0U)

+#define DSI_WPCR1_HSTXDCL_Msk         (0x3UL << DSI_WPCR1_HSTXDCL_Pos)         /*!< 0x00000003 */

+#define DSI_WPCR1_HSTXDCL             DSI_WPCR1_HSTXDCL_Msk                    /*!< High-Speed Transmission Delay on Clock Lane */

+#define DSI_WPCR1_HSTXDCL0_Pos        (0U)

+#define DSI_WPCR1_HSTXDCL0_Msk        (0x1UL << DSI_WPCR1_HSTXDCL0_Pos)        /*!< 0x00000001 */

+#define DSI_WPCR1_HSTXDCL0            DSI_WPCR1_HSTXDCL0_Msk

+#define DSI_WPCR1_HSTXDCL1_Pos        (1U)

+#define DSI_WPCR1_HSTXDCL1_Msk        (0x1UL << DSI_WPCR1_HSTXDCL1_Pos)        /*!< 0x00000002 */

+#define DSI_WPCR1_HSTXDCL1            DSI_WPCR1_HSTXDCL1_Msk

+

+#define DSI_WPCR1_HSTXDDL_Pos         (2U)

+#define DSI_WPCR1_HSTXDDL_Msk         (0x3UL << DSI_WPCR1_HSTXDDL_Pos)         /*!< 0x0000000C */

+#define DSI_WPCR1_HSTXDDL             DSI_WPCR1_HSTXDDL_Msk                    /*!< High-Speed Transmission Delay on Data Lane */

+#define DSI_WPCR1_HSTXDDL0_Pos        (2U)

+#define DSI_WPCR1_HSTXDDL0_Msk        (0x1UL << DSI_WPCR1_HSTXDDL0_Pos)        /*!< 0x00000004 */

+#define DSI_WPCR1_HSTXDDL0            DSI_WPCR1_HSTXDDL0_Msk

+#define DSI_WPCR1_HSTXDDL1_Pos        (3U)

+#define DSI_WPCR1_HSTXDDL1_Msk        (0x1UL << DSI_WPCR1_HSTXDDL1_Pos)        /*!< 0x00000008 */

+#define DSI_WPCR1_HSTXDDL1            DSI_WPCR1_HSTXDDL1_Msk

+

+#define DSI_WPCR1_LPSRCCL_Pos         (6U)

+#define DSI_WPCR1_LPSRCCL_Msk         (0x3UL << DSI_WPCR1_LPSRCCL_Pos)         /*!< 0x000000C0 */

+#define DSI_WPCR1_LPSRCCL             DSI_WPCR1_LPSRCCL_Msk                    /*!< Low-Power transmission Slew Rate Compensation on Clock Lane */

+#define DSI_WPCR1_LPSRCCL0_Pos        (6U)

+#define DSI_WPCR1_LPSRCCL0_Msk        (0x1UL << DSI_WPCR1_LPSRCCL0_Pos)        /*!< 0x00000040 */

+#define DSI_WPCR1_LPSRCCL0            DSI_WPCR1_LPSRCCL0_Msk

+#define DSI_WPCR1_LPSRCCL1_Pos        (7U)

+#define DSI_WPCR1_LPSRCCL1_Msk        (0x1UL << DSI_WPCR1_LPSRCCL1_Pos)        /*!< 0x00000080 */

+#define DSI_WPCR1_LPSRCCL1            DSI_WPCR1_LPSRCCL1_Msk

+

+#define DSI_WPCR1_LPSRCDL_Pos         (8U)

+#define DSI_WPCR1_LPSRCDL_Msk         (0x3UL << DSI_WPCR1_LPSRCDL_Pos)         /*!< 0x00000300 */

+#define DSI_WPCR1_LPSRCDL             DSI_WPCR1_LPSRCDL_Msk                    /*!< Low-Power transmission Slew Rate Compensation on Data Lane */

+#define DSI_WPCR1_LPSRCDL0_Pos        (8U)

+#define DSI_WPCR1_LPSRCDL0_Msk        (0x1UL << DSI_WPCR1_LPSRCDL0_Pos)        /*!< 0x00000100 */

+#define DSI_WPCR1_LPSRCDL0            DSI_WPCR1_LPSRCDL0_Msk

+#define DSI_WPCR1_LPSRCDL1_Pos        (9U)

+#define DSI_WPCR1_LPSRCDL1_Msk        (0x1UL << DSI_WPCR1_LPSRCDL1_Pos)        /*!< 0x00000200 */

+#define DSI_WPCR1_LPSRCDL1            DSI_WPCR1_LPSRCDL1_Msk

+

+#define DSI_WPCR1_SDDC_Pos            (12U)

+#define DSI_WPCR1_SDDC_Msk            (0x1UL << DSI_WPCR1_SDDC_Pos)            /*!< 0x00001000 */

+#define DSI_WPCR1_SDDC                DSI_WPCR1_SDDC_Msk                       /*!< SDD Control */

+

+#define DSI_WPCR1_LPRXVCDL_Pos        (14U)

+#define DSI_WPCR1_LPRXVCDL_Msk        (0x3UL << DSI_WPCR1_LPRXVCDL_Pos)        /*!< 0x0000C000 */

+#define DSI_WPCR1_LPRXVCDL            DSI_WPCR1_LPRXVCDL_Msk                   /*!< Low-Power Reception V-IL Compensation on Data Lanes */

+#define DSI_WPCR1_LPRXVCDL0_Pos       (14U)

+#define DSI_WPCR1_LPRXVCDL0_Msk       (0x1UL << DSI_WPCR1_LPRXVCDL0_Pos)       /*!< 0x00004000 */

+#define DSI_WPCR1_LPRXVCDL0           DSI_WPCR1_LPRXVCDL0_Msk

+#define DSI_WPCR1_LPRXVCDL1_Pos       (15U)

+#define DSI_WPCR1_LPRXVCDL1_Msk       (0x1UL << DSI_WPCR1_LPRXVCDL1_Pos)       /*!< 0x00008000 */

+#define DSI_WPCR1_LPRXVCDL1           DSI_WPCR1_LPRXVCDL1_Msk

+

+#define DSI_WPCR1_HSTXSRCCL_Pos       (16U)

+#define DSI_WPCR1_HSTXSRCCL_Msk       (0x3UL << DSI_WPCR1_HSTXSRCCL_Pos)       /*!< 0x00030000 */

+#define DSI_WPCR1_HSTXSRCCL           DSI_WPCR1_HSTXSRCCL_Msk                  /*!< High-Speed Transmission Delay on Clock Lane */

+#define DSI_WPCR1_HSTXSRCCL0_Pos      (16U)

+#define DSI_WPCR1_HSTXSRCCL0_Msk      (0x1UL << DSI_WPCR1_HSTXSRCCL0_Pos)      /*!< 0x00010000 */

+#define DSI_WPCR1_HSTXSRCCL0          DSI_WPCR1_HSTXSRCCL0_Msk

+#define DSI_WPCR1_HSTXSRCCL1_Pos      (17U)

+#define DSI_WPCR1_HSTXSRCCL1_Msk      (0x1UL << DSI_WPCR1_HSTXSRCCL1_Pos)      /*!< 0x00020000 */

+#define DSI_WPCR1_HSTXSRCCL1          DSI_WPCR1_HSTXSRCCL1_Msk

+

+#define DSI_WPCR1_HSTXSRCDL_Pos       (18U)

+#define DSI_WPCR1_HSTXSRCDL_Msk       (0x3UL << DSI_WPCR1_HSTXSRCDL_Pos)       /*!< 0x000C0000 */

+#define DSI_WPCR1_HSTXSRCDL           DSI_WPCR1_HSTXSRCDL_Msk                  /*!< High-Speed Transmission Delay on Data Lane */

+#define DSI_WPCR1_HSTXSRCDL0_Pos      (18U)

+#define DSI_WPCR1_HSTXSRCDL0_Msk      (0x1UL << DSI_WPCR1_HSTXSRCDL0_Pos)      /*!< 0x00040000 */

+#define DSI_WPCR1_HSTXSRCDL0          DSI_WPCR1_HSTXSRCDL0_Msk

+#define DSI_WPCR1_HSTXSRCDL1_Pos      (19U)

+#define DSI_WPCR1_HSTXSRCDL1_Msk      (0x1UL << DSI_WPCR1_HSTXSRCDL1_Pos)      /*!< 0x00080000 */

+#define DSI_WPCR1_HSTXSRCDL1          DSI_WPCR1_HSTXSRCDL1_Msk

+

+#define DSI_WPCR1_FLPRXLPM_Pos        (22U)

+#define DSI_WPCR1_FLPRXLPM_Msk        (0x1UL << DSI_WPCR1_FLPRXLPM_Pos)        /*!< 0x00400000 */

+#define DSI_WPCR1_FLPRXLPM            DSI_WPCR1_FLPRXLPM_Msk                   /*!< Forces LP Receiver in Low-Power Mode */

+

+#define DSI_WPCR1_LPRXFT_Pos          (25U)

+#define DSI_WPCR1_LPRXFT_Msk          (0x3UL << DSI_WPCR1_LPRXFT_Pos)          /*!< 0x06000000 */

+#define DSI_WPCR1_LPRXFT              DSI_WPCR1_LPRXFT_Msk                     /*!< Low-Power RX low-pass Filtering Tuning */

+#define DSI_WPCR1_LPRXFT0_Pos         (25U)

+#define DSI_WPCR1_LPRXFT0_Msk         (0x1UL << DSI_WPCR1_LPRXFT0_Pos)         /*!< 0x02000000 */

+#define DSI_WPCR1_LPRXFT0             DSI_WPCR1_LPRXFT0_Msk

+#define DSI_WPCR1_LPRXFT1_Pos         (26U)

+#define DSI_WPCR1_LPRXFT1_Msk         (0x1UL << DSI_WPCR1_LPRXFT1_Pos)         /*!< 0x04000000 */

+#define DSI_WPCR1_LPRXFT1             DSI_WPCR1_LPRXFT1_Msk

+

+/*******************  Bit definition for DSI_WPCR2 register  ***************/

+#define DSI_WPCR2_TCLKPREP_Pos        (0U)

+#define DSI_WPCR2_TCLKPREP_Msk        (0xFFUL << DSI_WPCR2_TCLKPREP_Pos)       /*!< 0x000000FF */

+#define DSI_WPCR2_TCLKPREP            DSI_WPCR2_TCLKPREP_Msk                   /*!< t-CLKPREP */

+#define DSI_WPCR2_TCLKPREP0_Pos       (0U)

+#define DSI_WPCR2_TCLKPREP0_Msk       (0x1UL << DSI_WPCR2_TCLKPREP0_Pos)       /*!< 0x00000001 */

+#define DSI_WPCR2_TCLKPREP0           DSI_WPCR2_TCLKPREP0_Msk

+#define DSI_WPCR2_TCLKPREP1_Pos       (1U)

+#define DSI_WPCR2_TCLKPREP1_Msk       (0x1UL << DSI_WPCR2_TCLKPREP1_Pos)       /*!< 0x00000002 */

+#define DSI_WPCR2_TCLKPREP1           DSI_WPCR2_TCLKPREP1_Msk

+#define DSI_WPCR2_TCLKPREP2_Pos       (2U)

+#define DSI_WPCR2_TCLKPREP2_Msk       (0x1UL << DSI_WPCR2_TCLKPREP2_Pos)       /*!< 0x00000004 */

+#define DSI_WPCR2_TCLKPREP2           DSI_WPCR2_TCLKPREP2_Msk

+#define DSI_WPCR2_TCLKPREP3_Pos       (3U)

+#define DSI_WPCR2_TCLKPREP3_Msk       (0x1UL << DSI_WPCR2_TCLKPREP3_Pos)       /*!< 0x00000008 */

+#define DSI_WPCR2_TCLKPREP3           DSI_WPCR2_TCLKPREP3_Msk

+#define DSI_WPCR2_TCLKPREP4_Pos       (4U)

+#define DSI_WPCR2_TCLKPREP4_Msk       (0x1UL << DSI_WPCR2_TCLKPREP4_Pos)       /*!< 0x00000010 */

+#define DSI_WPCR2_TCLKPREP4           DSI_WPCR2_TCLKPREP4_Msk

+#define DSI_WPCR2_TCLKPREP5_Pos       (5U)

+#define DSI_WPCR2_TCLKPREP5_Msk       (0x1UL << DSI_WPCR2_TCLKPREP5_Pos)       /*!< 0x00000020 */

+#define DSI_WPCR2_TCLKPREP5           DSI_WPCR2_TCLKPREP5_Msk

+#define DSI_WPCR2_TCLKPREP6_Pos       (6U)

+#define DSI_WPCR2_TCLKPREP6_Msk       (0x1UL << DSI_WPCR2_TCLKPREP6_Pos)       /*!< 0x00000040 */

+#define DSI_WPCR2_TCLKPREP6           DSI_WPCR2_TCLKPREP6_Msk

+#define DSI_WPCR2_TCLKPREP7_Pos       (7U)

+#define DSI_WPCR2_TCLKPREP7_Msk       (0x1UL << DSI_WPCR2_TCLKPREP7_Pos)       /*!< 0x00000080 */

+#define DSI_WPCR2_TCLKPREP7           DSI_WPCR2_TCLKPREP7_Msk

+

+#define DSI_WPCR2_TCLKZERO_Pos        (8U)

+#define DSI_WPCR2_TCLKZERO_Msk        (0xFFUL << DSI_WPCR2_TCLKZERO_Pos)       /*!< 0x0000FF00 */

+#define DSI_WPCR2_TCLKZERO            DSI_WPCR2_TCLKZERO_Msk                   /*!< t-CLKZERO */

+#define DSI_WPCR2_TCLKZERO0_Pos       (8U)

+#define DSI_WPCR2_TCLKZERO0_Msk       (0x1UL << DSI_WPCR2_TCLKZERO0_Pos)       /*!< 0x00000100 */

+#define DSI_WPCR2_TCLKZERO0           DSI_WPCR2_TCLKZERO0_Msk

+#define DSI_WPCR2_TCLKZERO1_Pos       (9U)

+#define DSI_WPCR2_TCLKZERO1_Msk       (0x1UL << DSI_WPCR2_TCLKZERO1_Pos)       /*!< 0x00000200 */

+#define DSI_WPCR2_TCLKZERO1           DSI_WPCR2_TCLKZERO1_Msk

+#define DSI_WPCR2_TCLKZERO2_Pos       (10U)

+#define DSI_WPCR2_TCLKZERO2_Msk       (0x1UL << DSI_WPCR2_TCLKZERO2_Pos)       /*!< 0x00000400 */

+#define DSI_WPCR2_TCLKZERO2           DSI_WPCR2_TCLKZERO2_Msk

+#define DSI_WPCR2_TCLKZERO3_Pos       (11U)

+#define DSI_WPCR2_TCLKZERO3_Msk       (0x1UL << DSI_WPCR2_TCLKZERO3_Pos)       /*!< 0x00000800 */

+#define DSI_WPCR2_TCLKZERO3           DSI_WPCR2_TCLKZERO3_Msk

+#define DSI_WPCR2_TCLKZERO4_Pos       (12U)

+#define DSI_WPCR2_TCLKZERO4_Msk       (0x1UL << DSI_WPCR2_TCLKZERO4_Pos)       /*!< 0x00001000 */

+#define DSI_WPCR2_TCLKZERO4           DSI_WPCR2_TCLKZERO4_Msk

+#define DSI_WPCR2_TCLKZERO5_Pos       (13U)

+#define DSI_WPCR2_TCLKZERO5_Msk       (0x1UL << DSI_WPCR2_TCLKZERO5_Pos)       /*!< 0x00002000 */

+#define DSI_WPCR2_TCLKZERO5           DSI_WPCR2_TCLKZERO5_Msk

+#define DSI_WPCR2_TCLKZERO6_Pos       (14U)

+#define DSI_WPCR2_TCLKZERO6_Msk       (0x1UL << DSI_WPCR2_TCLKZERO6_Pos)       /*!< 0x00004000 */

+#define DSI_WPCR2_TCLKZERO6           DSI_WPCR2_TCLKZERO6_Msk

+#define DSI_WPCR2_TCLKZERO7_Pos       (15U)

+#define DSI_WPCR2_TCLKZERO7_Msk       (0x1UL << DSI_WPCR2_TCLKZERO7_Pos)       /*!< 0x00008000 */

+#define DSI_WPCR2_TCLKZERO7           DSI_WPCR2_TCLKZERO7_Msk

+

+#define DSI_WPCR2_THSPREP_Pos         (16U)

+#define DSI_WPCR2_THSPREP_Msk         (0xFFUL << DSI_WPCR2_THSPREP_Pos)        /*!< 0x00FF0000 */

+#define DSI_WPCR2_THSPREP             DSI_WPCR2_THSPREP_Msk                    /*!< t-HSPREP */

+#define DSI_WPCR2_THSPREP0_Pos        (16U)

+#define DSI_WPCR2_THSPREP0_Msk        (0x1UL << DSI_WPCR2_THSPREP0_Pos)        /*!< 0x00010000 */

+#define DSI_WPCR2_THSPREP0            DSI_WPCR2_THSPREP0_Msk

+#define DSI_WPCR2_THSPREP1_Pos        (17U)

+#define DSI_WPCR2_THSPREP1_Msk        (0x1UL << DSI_WPCR2_THSPREP1_Pos)        /*!< 0x00020000 */

+#define DSI_WPCR2_THSPREP1            DSI_WPCR2_THSPREP1_Msk

+#define DSI_WPCR2_THSPREP2_Pos        (18U)

+#define DSI_WPCR2_THSPREP2_Msk        (0x1UL << DSI_WPCR2_THSPREP2_Pos)        /*!< 0x00040000 */

+#define DSI_WPCR2_THSPREP2            DSI_WPCR2_THSPREP2_Msk

+#define DSI_WPCR2_THSPREP3_Pos        (19U)

+#define DSI_WPCR2_THSPREP3_Msk        (0x1UL << DSI_WPCR2_THSPREP3_Pos)        /*!< 0x00080000 */

+#define DSI_WPCR2_THSPREP3            DSI_WPCR2_THSPREP3_Msk

+#define DSI_WPCR2_THSPREP4_Pos        (20U)

+#define DSI_WPCR2_THSPREP4_Msk        (0x1UL << DSI_WPCR2_THSPREP4_Pos)        /*!< 0x00100000 */

+#define DSI_WPCR2_THSPREP4            DSI_WPCR2_THSPREP4_Msk

+#define DSI_WPCR2_THSPREP5_Pos        (21U)

+#define DSI_WPCR2_THSPREP5_Msk        (0x1UL << DSI_WPCR2_THSPREP5_Pos)        /*!< 0x00200000 */

+#define DSI_WPCR2_THSPREP5            DSI_WPCR2_THSPREP5_Msk

+#define DSI_WPCR2_THSPREP6_Pos        (22U)

+#define DSI_WPCR2_THSPREP6_Msk        (0x1UL << DSI_WPCR2_THSPREP6_Pos)        /*!< 0x00400000 */

+#define DSI_WPCR2_THSPREP6            DSI_WPCR2_THSPREP6_Msk

+#define DSI_WPCR2_THSPREP7_Pos        (23U)

+#define DSI_WPCR2_THSPREP7_Msk        (0x1UL << DSI_WPCR2_THSPREP7_Pos)        /*!< 0x00800000 */

+#define DSI_WPCR2_THSPREP7            DSI_WPCR2_THSPREP7_Msk

+

+#define DSI_WPCR2_THSTRAIL_Pos        (24U)

+#define DSI_WPCR2_THSTRAIL_Msk        (0xFFUL << DSI_WPCR2_THSTRAIL_Pos)       /*!< 0xFF000000 */

+#define DSI_WPCR2_THSTRAIL            DSI_WPCR2_THSTRAIL_Msk                   /*!< t-HSTRAIL */

+#define DSI_WPCR2_THSTRAIL0_Pos       (24U)

+#define DSI_WPCR2_THSTRAIL0_Msk       (0x1UL << DSI_WPCR2_THSTRAIL0_Pos)       /*!< 0x01000000 */

+#define DSI_WPCR2_THSTRAIL0           DSI_WPCR2_THSTRAIL0_Msk

+#define DSI_WPCR2_THSTRAIL1_Pos       (25U)

+#define DSI_WPCR2_THSTRAIL1_Msk       (0x1UL << DSI_WPCR2_THSTRAIL1_Pos)       /*!< 0x02000000 */

+#define DSI_WPCR2_THSTRAIL1           DSI_WPCR2_THSTRAIL1_Msk

+#define DSI_WPCR2_THSTRAIL2_Pos       (26U)

+#define DSI_WPCR2_THSTRAIL2_Msk       (0x1UL << DSI_WPCR2_THSTRAIL2_Pos)       /*!< 0x04000000 */

+#define DSI_WPCR2_THSTRAIL2           DSI_WPCR2_THSTRAIL2_Msk

+#define DSI_WPCR2_THSTRAIL3_Pos       (27U)

+#define DSI_WPCR2_THSTRAIL3_Msk       (0x1UL << DSI_WPCR2_THSTRAIL3_Pos)       /*!< 0x08000000 */

+#define DSI_WPCR2_THSTRAIL3           DSI_WPCR2_THSTRAIL3_Msk

+#define DSI_WPCR2_THSTRAIL4_Pos       (28U)

+#define DSI_WPCR2_THSTRAIL4_Msk       (0x1UL << DSI_WPCR2_THSTRAIL4_Pos)       /*!< 0x10000000 */

+#define DSI_WPCR2_THSTRAIL4           DSI_WPCR2_THSTRAIL4_Msk

+#define DSI_WPCR2_THSTRAIL5_Pos       (29U)

+#define DSI_WPCR2_THSTRAIL5_Msk       (0x1UL << DSI_WPCR2_THSTRAIL5_Pos)       /*!< 0x20000000 */

+#define DSI_WPCR2_THSTRAIL5           DSI_WPCR2_THSTRAIL5_Msk

+#define DSI_WPCR2_THSTRAIL6_Pos       (30U)

+#define DSI_WPCR2_THSTRAIL6_Msk       (0x1UL << DSI_WPCR2_THSTRAIL6_Pos)       /*!< 0x40000000 */

+#define DSI_WPCR2_THSTRAIL6           DSI_WPCR2_THSTRAIL6_Msk

+#define DSI_WPCR2_THSTRAIL7_Pos       (31U)

+#define DSI_WPCR2_THSTRAIL7_Msk       (0x1UL << DSI_WPCR2_THSTRAIL7_Pos)       /*!< 0x80000000 */

+#define DSI_WPCR2_THSTRAIL7           DSI_WPCR2_THSTRAIL7_Msk

+

+/*******************  Bit definition for DSI_WPCR3 register  ***************/

+#define DSI_WPCR3_THSZERO_Pos         (0U)

+#define DSI_WPCR3_THSZERO_Msk         (0xFFUL << DSI_WPCR3_THSZERO_Pos)        /*!< 0x000000FF */

+#define DSI_WPCR3_THSZERO             DSI_WPCR3_THSZERO_Msk                    /*!< t-HSZERO */

+#define DSI_WPCR3_THSZERO0_Pos        (0U)

+#define DSI_WPCR3_THSZERO0_Msk        (0x1UL << DSI_WPCR3_THSZERO0_Pos)        /*!< 0x00000001 */

+#define DSI_WPCR3_THSZERO0            DSI_WPCR3_THSZERO0_Msk

+#define DSI_WPCR3_THSZERO1_Pos        (1U)

+#define DSI_WPCR3_THSZERO1_Msk        (0x1UL << DSI_WPCR3_THSZERO1_Pos)        /*!< 0x00000002 */

+#define DSI_WPCR3_THSZERO1            DSI_WPCR3_THSZERO1_Msk

+#define DSI_WPCR3_THSZERO2_Pos        (2U)

+#define DSI_WPCR3_THSZERO2_Msk        (0x1UL << DSI_WPCR3_THSZERO2_Pos)        /*!< 0x00000004 */

+#define DSI_WPCR3_THSZERO2            DSI_WPCR3_THSZERO2_Msk

+#define DSI_WPCR3_THSZERO3_Pos        (3U)

+#define DSI_WPCR3_THSZERO3_Msk        (0x1UL << DSI_WPCR3_THSZERO3_Pos)        /*!< 0x00000008 */

+#define DSI_WPCR3_THSZERO3            DSI_WPCR3_THSZERO3_Msk

+#define DSI_WPCR3_THSZERO4_Pos        (4U)

+#define DSI_WPCR3_THSZERO4_Msk        (0x1UL << DSI_WPCR3_THSZERO4_Pos)        /*!< 0x00000010 */

+#define DSI_WPCR3_THSZERO4            DSI_WPCR3_THSZERO4_Msk

+#define DSI_WPCR3_THSZERO5_Pos        (5U)

+#define DSI_WPCR3_THSZERO5_Msk        (0x1UL << DSI_WPCR3_THSZERO5_Pos)        /*!< 0x00000020 */

+#define DSI_WPCR3_THSZERO5            DSI_WPCR3_THSZERO5_Msk

+#define DSI_WPCR3_THSZERO6_Pos        (6U)

+#define DSI_WPCR3_THSZERO6_Msk        (0x1UL << DSI_WPCR3_THSZERO6_Pos)        /*!< 0x00000040 */

+#define DSI_WPCR3_THSZERO6            DSI_WPCR3_THSZERO6_Msk

+#define DSI_WPCR3_THSZERO7_Pos        (7U)

+#define DSI_WPCR3_THSZERO7_Msk        (0x1UL << DSI_WPCR3_THSZERO7_Pos)        /*!< 0x00000080 */

+#define DSI_WPCR3_THSZERO7            DSI_WPCR3_THSZERO7_Msk

+

+#define DSI_WPCR3_TLPXD_Pos           (8U)

+#define DSI_WPCR3_TLPXD_Msk           (0xFFUL << DSI_WPCR3_TLPXD_Pos)          /*!< 0x0000FF00 */

+#define DSI_WPCR3_TLPXD               DSI_WPCR3_TLPXD_Msk                      /*!< t-LPXD */

+#define DSI_WPCR3_TLPXD0_Pos          (8U)

+#define DSI_WPCR3_TLPXD0_Msk          (0x1UL << DSI_WPCR3_TLPXD0_Pos)          /*!< 0x00000100 */

+#define DSI_WPCR3_TLPXD0              DSI_WPCR3_TLPXD0_Msk

+#define DSI_WPCR3_TLPXD1_Pos          (9U)

+#define DSI_WPCR3_TLPXD1_Msk          (0x1UL << DSI_WPCR3_TLPXD1_Pos)          /*!< 0x00000200 */

+#define DSI_WPCR3_TLPXD1              DSI_WPCR3_TLPXD1_Msk

+#define DSI_WPCR3_TLPXD2_Pos          (10U)

+#define DSI_WPCR3_TLPXD2_Msk          (0x1UL << DSI_WPCR3_TLPXD2_Pos)          /*!< 0x00000400 */

+#define DSI_WPCR3_TLPXD2              DSI_WPCR3_TLPXD2_Msk

+#define DSI_WPCR3_TLPXD3_Pos          (11U)

+#define DSI_WPCR3_TLPXD3_Msk          (0x1UL << DSI_WPCR3_TLPXD3_Pos)          /*!< 0x00000800 */

+#define DSI_WPCR3_TLPXD3              DSI_WPCR3_TLPXD3_Msk

+#define DSI_WPCR3_TLPXD4_Pos          (12U)

+#define DSI_WPCR3_TLPXD4_Msk          (0x1UL << DSI_WPCR3_TLPXD4_Pos)          /*!< 0x00001000 */

+#define DSI_WPCR3_TLPXD4              DSI_WPCR3_TLPXD4_Msk

+#define DSI_WPCR3_TLPXD5_Pos          (13U)

+#define DSI_WPCR3_TLPXD5_Msk          (0x1UL << DSI_WPCR3_TLPXD5_Pos)          /*!< 0x00002000 */

+#define DSI_WPCR3_TLPXD5              DSI_WPCR3_TLPXD5_Msk

+#define DSI_WPCR3_TLPXD6_Pos          (14U)

+#define DSI_WPCR3_TLPXD6_Msk          (0x1UL << DSI_WPCR3_TLPXD6_Pos)          /*!< 0x00004000 */

+#define DSI_WPCR3_TLPXD6              DSI_WPCR3_TLPXD6_Msk

+#define DSI_WPCR3_TLPXD7_Pos          (15U)

+#define DSI_WPCR3_TLPXD7_Msk          (0x1UL << DSI_WPCR3_TLPXD7_Pos)          /*!< 0x00008000 */

+#define DSI_WPCR3_TLPXD7              DSI_WPCR3_TLPXD7_Msk

+

+#define DSI_WPCR3_THSEXIT_Pos         (16U)

+#define DSI_WPCR3_THSEXIT_Msk         (0xFFUL << DSI_WPCR3_THSEXIT_Pos)        /*!< 0x00FF0000 */

+#define DSI_WPCR3_THSEXIT             DSI_WPCR3_THSEXIT_Msk                    /*!< t-HSEXIT */

+#define DSI_WPCR3_THSEXIT0_Pos        (16U)

+#define DSI_WPCR3_THSEXIT0_Msk        (0x1UL << DSI_WPCR3_THSEXIT0_Pos)        /*!< 0x00010000 */

+#define DSI_WPCR3_THSEXIT0            DSI_WPCR3_THSEXIT0_Msk

+#define DSI_WPCR3_THSEXIT1_Pos        (17U)

+#define DSI_WPCR3_THSEXIT1_Msk        (0x1UL << DSI_WPCR3_THSEXIT1_Pos)        /*!< 0x00020000 */

+#define DSI_WPCR3_THSEXIT1            DSI_WPCR3_THSEXIT1_Msk

+#define DSI_WPCR3_THSEXIT2_Pos        (18U)

+#define DSI_WPCR3_THSEXIT2_Msk        (0x1UL << DSI_WPCR3_THSEXIT2_Pos)        /*!< 0x00040000 */

+#define DSI_WPCR3_THSEXIT2            DSI_WPCR3_THSEXIT2_Msk

+#define DSI_WPCR3_THSEXIT3_Pos        (19U)

+#define DSI_WPCR3_THSEXIT3_Msk        (0x1UL << DSI_WPCR3_THSEXIT3_Pos)        /*!< 0x00080000 */

+#define DSI_WPCR3_THSEXIT3            DSI_WPCR3_THSEXIT3_Msk

+#define DSI_WPCR3_THSEXIT4_Pos        (20U)

+#define DSI_WPCR3_THSEXIT4_Msk        (0x1UL << DSI_WPCR3_THSEXIT4_Pos)        /*!< 0x00100000 */

+#define DSI_WPCR3_THSEXIT4            DSI_WPCR3_THSEXIT4_Msk

+#define DSI_WPCR3_THSEXIT5_Pos        (21U)

+#define DSI_WPCR3_THSEXIT5_Msk        (0x1UL << DSI_WPCR3_THSEXIT5_Pos)        /*!< 0x00200000 */

+#define DSI_WPCR3_THSEXIT5            DSI_WPCR3_THSEXIT5_Msk

+#define DSI_WPCR3_THSEXIT6_Pos        (22U)

+#define DSI_WPCR3_THSEXIT6_Msk        (0x1UL << DSI_WPCR3_THSEXIT6_Pos)        /*!< 0x00400000 */

+#define DSI_WPCR3_THSEXIT6            DSI_WPCR3_THSEXIT6_Msk

+#define DSI_WPCR3_THSEXIT7_Pos        (23U)

+#define DSI_WPCR3_THSEXIT7_Msk        (0x1UL << DSI_WPCR3_THSEXIT7_Pos)        /*!< 0x00800000 */

+#define DSI_WPCR3_THSEXIT7            DSI_WPCR3_THSEXIT7_Msk

+

+#define DSI_WPCR3_TLPXC_Pos           (24U)

+#define DSI_WPCR3_TLPXC_Msk           (0xFFUL << DSI_WPCR3_TLPXC_Pos)          /*!< 0xFF000000 */

+#define DSI_WPCR3_TLPXC               DSI_WPCR3_TLPXC_Msk                      /*!< t-LPXC */

+#define DSI_WPCR3_TLPXC0_Pos          (24U)

+#define DSI_WPCR3_TLPXC0_Msk          (0x1UL << DSI_WPCR3_TLPXC0_Pos)          /*!< 0x01000000 */

+#define DSI_WPCR3_TLPXC0              DSI_WPCR3_TLPXC0_Msk

+#define DSI_WPCR3_TLPXC1_Pos          (25U)

+#define DSI_WPCR3_TLPXC1_Msk          (0x1UL << DSI_WPCR3_TLPXC1_Pos)          /*!< 0x02000000 */

+#define DSI_WPCR3_TLPXC1              DSI_WPCR3_TLPXC1_Msk

+#define DSI_WPCR3_TLPXC2_Pos          (26U)

+#define DSI_WPCR3_TLPXC2_Msk          (0x1UL << DSI_WPCR3_TLPXC2_Pos)          /*!< 0x04000000 */

+#define DSI_WPCR3_TLPXC2              DSI_WPCR3_TLPXC2_Msk

+#define DSI_WPCR3_TLPXC3_Pos          (27U)

+#define DSI_WPCR3_TLPXC3_Msk          (0x1UL << DSI_WPCR3_TLPXC3_Pos)          /*!< 0x08000000 */

+#define DSI_WPCR3_TLPXC3              DSI_WPCR3_TLPXC3_Msk

+#define DSI_WPCR3_TLPXC4_Pos          (28U)

+#define DSI_WPCR3_TLPXC4_Msk          (0x1UL << DSI_WPCR3_TLPXC4_Pos)          /*!< 0x10000000 */

+#define DSI_WPCR3_TLPXC4              DSI_WPCR3_TLPXC4_Msk

+#define DSI_WPCR3_TLPXC5_Pos          (29U)

+#define DSI_WPCR3_TLPXC5_Msk          (0x1UL << DSI_WPCR3_TLPXC5_Pos)          /*!< 0x20000000 */

+#define DSI_WPCR3_TLPXC5              DSI_WPCR3_TLPXC5_Msk

+#define DSI_WPCR3_TLPXC6_Pos          (30U)

+#define DSI_WPCR3_TLPXC6_Msk          (0x1UL << DSI_WPCR3_TLPXC6_Pos)          /*!< 0x40000000 */

+#define DSI_WPCR3_TLPXC6              DSI_WPCR3_TLPXC6_Msk

+#define DSI_WPCR3_TLPXC7_Pos          (31U)

+#define DSI_WPCR3_TLPXC7_Msk          (0x1UL << DSI_WPCR3_TLPXC7_Pos)          /*!< 0x80000000 */

+#define DSI_WPCR3_TLPXC7              DSI_WPCR3_TLPXC7_Msk

+

+/*******************  Bit definition for DSI_WPCR4 register  ***************/

+#define DSI_WPCR4_TCLKPOST_Pos        (0U)

+#define DSI_WPCR4_TCLKPOST_Msk        (0xFFUL << DSI_WPCR4_TCLKPOST_Pos)       /*!< 0x000000FF */

+#define DSI_WPCR4_TCLKPOST            DSI_WPCR4_TCLKPOST_Msk                   /*!< t-CLKPOST */

+#define DSI_WPCR4_TCLKPOST0_Pos       (0U)

+#define DSI_WPCR4_TCLKPOST0_Msk       (0x1UL << DSI_WPCR4_TCLKPOST0_Pos)       /*!< 0x00000001 */

+#define DSI_WPCR4_TCLKPOST0           DSI_WPCR4_TCLKPOST0_Msk

+#define DSI_WPCR4_TCLKPOST1_Pos       (1U)

+#define DSI_WPCR4_TCLKPOST1_Msk       (0x1UL << DSI_WPCR4_TCLKPOST1_Pos)       /*!< 0x00000002 */

+#define DSI_WPCR4_TCLKPOST1           DSI_WPCR4_TCLKPOST1_Msk

+#define DSI_WPCR4_TCLKPOST2_Pos       (2U)

+#define DSI_WPCR4_TCLKPOST2_Msk       (0x1UL << DSI_WPCR4_TCLKPOST2_Pos)       /*!< 0x00000004 */

+#define DSI_WPCR4_TCLKPOST2           DSI_WPCR4_TCLKPOST2_Msk

+#define DSI_WPCR4_TCLKPOST3_Pos       (3U)

+#define DSI_WPCR4_TCLKPOST3_Msk       (0x1UL << DSI_WPCR4_TCLKPOST3_Pos)       /*!< 0x00000008 */

+#define DSI_WPCR4_TCLKPOST3           DSI_WPCR4_TCLKPOST3_Msk

+#define DSI_WPCR4_TCLKPOST4_Pos       (4U)

+#define DSI_WPCR4_TCLKPOST4_Msk       (0x1UL << DSI_WPCR4_TCLKPOST4_Pos)       /*!< 0x00000010 */

+#define DSI_WPCR4_TCLKPOST4           DSI_WPCR4_TCLKPOST4_Msk

+#define DSI_WPCR4_TCLKPOST5_Pos       (5U)

+#define DSI_WPCR4_TCLKPOST5_Msk       (0x1UL << DSI_WPCR4_TCLKPOST5_Pos)       /*!< 0x00000020 */

+#define DSI_WPCR4_TCLKPOST5           DSI_WPCR4_TCLKPOST5_Msk

+#define DSI_WPCR4_TCLKPOST6_Pos       (6U)

+#define DSI_WPCR4_TCLKPOST6_Msk       (0x1UL << DSI_WPCR4_TCLKPOST6_Pos)       /*!< 0x00000040 */

+#define DSI_WPCR4_TCLKPOST6           DSI_WPCR4_TCLKPOST6_Msk

+#define DSI_WPCR4_TCLKPOST7_Pos       (7U)

+#define DSI_WPCR4_TCLKPOST7_Msk       (0x1UL << DSI_WPCR4_TCLKPOST7_Pos)       /*!< 0x00000080 */

+#define DSI_WPCR4_TCLKPOST7           DSI_WPCR4_TCLKPOST7_Msk

+

+/*******************  Bit definition for DSI_WRPCR register  ***************/

+#define DSI_WRPCR_PLLEN_Pos           (0U)

+#define DSI_WRPCR_PLLEN_Msk           (0x1UL << DSI_WRPCR_PLLEN_Pos)           /*!< 0x00000001 */

+#define DSI_WRPCR_PLLEN               DSI_WRPCR_PLLEN_Msk                      /*!< PLL Enable */

+#define DSI_WRPCR_PLL_NDIV_Pos        (2U)

+#define DSI_WRPCR_PLL_NDIV_Msk        (0x7FUL << DSI_WRPCR_PLL_NDIV_Pos)       /*!< 0x000001FC */

+#define DSI_WRPCR_PLL_NDIV            DSI_WRPCR_PLL_NDIV_Msk                   /*!< PLL Loop Division Factor */

+#define DSI_WRPCR_PLL_NDIV0_Pos       (2U)

+#define DSI_WRPCR_PLL_NDIV0_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV0_Pos)       /*!< 0x00000004 */

+#define DSI_WRPCR_PLL_NDIV0           DSI_WRPCR_PLL_NDIV0_Msk

+#define DSI_WRPCR_PLL_NDIV1_Pos       (3U)

+#define DSI_WRPCR_PLL_NDIV1_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV1_Pos)       /*!< 0x00000008 */

+#define DSI_WRPCR_PLL_NDIV1           DSI_WRPCR_PLL_NDIV1_Msk

+#define DSI_WRPCR_PLL_NDIV2_Pos       (4U)

+#define DSI_WRPCR_PLL_NDIV2_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV2_Pos)       /*!< 0x00000010 */

+#define DSI_WRPCR_PLL_NDIV2           DSI_WRPCR_PLL_NDIV2_Msk

+#define DSI_WRPCR_PLL_NDIV3_Pos       (5U)

+#define DSI_WRPCR_PLL_NDIV3_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV3_Pos)       /*!< 0x00000020 */

+#define DSI_WRPCR_PLL_NDIV3           DSI_WRPCR_PLL_NDIV3_Msk

+#define DSI_WRPCR_PLL_NDIV4_Pos       (6U)

+#define DSI_WRPCR_PLL_NDIV4_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV4_Pos)       /*!< 0x00000040 */

+#define DSI_WRPCR_PLL_NDIV4           DSI_WRPCR_PLL_NDIV4_Msk

+#define DSI_WRPCR_PLL_NDIV5_Pos       (7U)

+#define DSI_WRPCR_PLL_NDIV5_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV5_Pos)       /*!< 0x00000080 */

+#define DSI_WRPCR_PLL_NDIV5           DSI_WRPCR_PLL_NDIV5_Msk

+#define DSI_WRPCR_PLL_NDIV6_Pos       (8U)

+#define DSI_WRPCR_PLL_NDIV6_Msk       (0x1UL << DSI_WRPCR_PLL_NDIV6_Pos)       /*!< 0x00000100 */

+#define DSI_WRPCR_PLL_NDIV6           DSI_WRPCR_PLL_NDIV6_Msk

+

+#define DSI_WRPCR_PLL_IDF_Pos         (11U)

+#define DSI_WRPCR_PLL_IDF_Msk         (0xFUL << DSI_WRPCR_PLL_IDF_Pos)         /*!< 0x00007800 */

+#define DSI_WRPCR_PLL_IDF             DSI_WRPCR_PLL_IDF_Msk                    /*!< PLL Input Division Factor */

+#define DSI_WRPCR_PLL_IDF0_Pos        (11U)

+#define DSI_WRPCR_PLL_IDF0_Msk        (0x1UL << DSI_WRPCR_PLL_IDF0_Pos)        /*!< 0x00000800 */

+#define DSI_WRPCR_PLL_IDF0            DSI_WRPCR_PLL_IDF0_Msk

+#define DSI_WRPCR_PLL_IDF1_Pos        (12U)

+#define DSI_WRPCR_PLL_IDF1_Msk        (0x1UL << DSI_WRPCR_PLL_IDF1_Pos)        /*!< 0x00001000 */

+#define DSI_WRPCR_PLL_IDF1            DSI_WRPCR_PLL_IDF1_Msk

+#define DSI_WRPCR_PLL_IDF2_Pos        (13U)

+#define DSI_WRPCR_PLL_IDF2_Msk        (0x1UL << DSI_WRPCR_PLL_IDF2_Pos)        /*!< 0x00002000 */

+#define DSI_WRPCR_PLL_IDF2            DSI_WRPCR_PLL_IDF2_Msk

+#define DSI_WRPCR_PLL_IDF3_Pos        (14U)

+#define DSI_WRPCR_PLL_IDF3_Msk        (0x1UL << DSI_WRPCR_PLL_IDF3_Pos)        /*!< 0x00004000 */

+#define DSI_WRPCR_PLL_IDF3            DSI_WRPCR_PLL_IDF3_Msk

+

+#define DSI_WRPCR_PLL_ODF_Pos         (16U)

+#define DSI_WRPCR_PLL_ODF_Msk         (0x3UL << DSI_WRPCR_PLL_ODF_Pos)         /*!< 0x00030000 */

+#define DSI_WRPCR_PLL_ODF             DSI_WRPCR_PLL_ODF_Msk                    /*!< PLL Output Division Factor */

+#define DSI_WRPCR_PLL_ODF0_Pos        (16U)

+#define DSI_WRPCR_PLL_ODF0_Msk        (0x1UL << DSI_WRPCR_PLL_ODF0_Pos)        /*!< 0x00010000 */

+#define DSI_WRPCR_PLL_ODF0            DSI_WRPCR_PLL_ODF0_Msk

+#define DSI_WRPCR_PLL_ODF1_Pos        (17U)

+#define DSI_WRPCR_PLL_ODF1_Msk        (0x1UL << DSI_WRPCR_PLL_ODF1_Pos)        /*!< 0x00020000 */

+#define DSI_WRPCR_PLL_ODF1            DSI_WRPCR_PLL_ODF1_Msk

+

+#define DSI_WRPCR_REGEN_Pos           (24U)

+#define DSI_WRPCR_REGEN_Msk           (0x1UL << DSI_WRPCR_REGEN_Pos)           /*!< 0x01000000 */

+#define DSI_WRPCR_REGEN               DSI_WRPCR_REGEN_Msk                      /*!< Regulator Enable */

+

+/******************************************************************************/

+/*                                                                            */

+/*                    External Interrupt/Event Controller                     */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for EXTI_RTSR1 register  *******************/

+#define EXTI_RTSR1_TR_Pos          (0U)

+#define EXTI_RTSR1_TR_Msk          (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)           /*!< 0x003FFFFF */

+#define EXTI_RTSR1_TR              EXTI_RTSR1_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR1_TR0_Pos         (0U)

+#define EXTI_RTSR1_TR0_Msk         (0x1UL << EXTI_RTSR1_TR0_Pos)               /*!< 0x00000001 */

+#define EXTI_RTSR1_TR0             EXTI_RTSR1_TR0_Msk                          /*!< Rising trigger event configuration bit of line 0 */

+#define EXTI_RTSR1_TR1_Pos         (1U)

+#define EXTI_RTSR1_TR1_Msk         (0x1UL << EXTI_RTSR1_TR1_Pos)               /*!< 0x00000002 */

+#define EXTI_RTSR1_TR1             EXTI_RTSR1_TR1_Msk                          /*!< Rising trigger event configuration bit of line 1 */

+#define EXTI_RTSR1_TR2_Pos         (2U)

+#define EXTI_RTSR1_TR2_Msk         (0x1UL << EXTI_RTSR1_TR2_Pos)               /*!< 0x00000004 */

+#define EXTI_RTSR1_TR2             EXTI_RTSR1_TR2_Msk                          /*!< Rising trigger event configuration bit of line 2 */

+#define EXTI_RTSR1_TR3_Pos         (3U)

+#define EXTI_RTSR1_TR3_Msk         (0x1UL << EXTI_RTSR1_TR3_Pos)               /*!< 0x00000008 */

+#define EXTI_RTSR1_TR3             EXTI_RTSR1_TR3_Msk                          /*!< Rising trigger event configuration bit of line 3 */

+#define EXTI_RTSR1_TR4_Pos         (4U)

+#define EXTI_RTSR1_TR4_Msk         (0x1UL << EXTI_RTSR1_TR4_Pos)               /*!< 0x00000010 */

+#define EXTI_RTSR1_TR4             EXTI_RTSR1_TR4_Msk                          /*!< Rising trigger event configuration bit of line 4 */

+#define EXTI_RTSR1_TR5_Pos         (5U)

+#define EXTI_RTSR1_TR5_Msk         (0x1UL << EXTI_RTSR1_TR5_Pos)               /*!< 0x00000020 */

+#define EXTI_RTSR1_TR5             EXTI_RTSR1_TR5_Msk                          /*!< Rising trigger event configuration bit of line 5 */

+#define EXTI_RTSR1_TR6_Pos         (6U)

+#define EXTI_RTSR1_TR6_Msk         (0x1UL << EXTI_RTSR1_TR6_Pos)               /*!< 0x00000040 */

+#define EXTI_RTSR1_TR6             EXTI_RTSR1_TR6_Msk                          /*!< Rising trigger event configuration bit of line 6 */

+#define EXTI_RTSR1_TR7_Pos         (7U)

+#define EXTI_RTSR1_TR7_Msk         (0x1UL << EXTI_RTSR1_TR7_Pos)               /*!< 0x00000080 */

+#define EXTI_RTSR1_TR7             EXTI_RTSR1_TR7_Msk                          /*!< Rising trigger event configuration bit of line 7 */

+#define EXTI_RTSR1_TR8_Pos         (8U)

+#define EXTI_RTSR1_TR8_Msk         (0x1UL << EXTI_RTSR1_TR8_Pos)               /*!< 0x00000100 */

+#define EXTI_RTSR1_TR8             EXTI_RTSR1_TR8_Msk                          /*!< Rising trigger event configuration bit of line 8 */

+#define EXTI_RTSR1_TR9_Pos         (9U)

+#define EXTI_RTSR1_TR9_Msk         (0x1UL << EXTI_RTSR1_TR9_Pos)               /*!< 0x00000200 */

+#define EXTI_RTSR1_TR9             EXTI_RTSR1_TR9_Msk                          /*!< Rising trigger event configuration bit of line 9 */

+#define EXTI_RTSR1_TR10_Pos        (10U)

+#define EXTI_RTSR1_TR10_Msk        (0x1UL << EXTI_RTSR1_TR10_Pos)              /*!< 0x00000400 */

+#define EXTI_RTSR1_TR10            EXTI_RTSR1_TR10_Msk                         /*!< Rising trigger event configuration bit of line 10 */

+#define EXTI_RTSR1_TR11_Pos        (11U)

+#define EXTI_RTSR1_TR11_Msk        (0x1UL << EXTI_RTSR1_TR11_Pos)              /*!< 0x00000800 */

+#define EXTI_RTSR1_TR11            EXTI_RTSR1_TR11_Msk                         /*!< Rising trigger event configuration bit of line 11 */

+#define EXTI_RTSR1_TR12_Pos        (12U)

+#define EXTI_RTSR1_TR12_Msk        (0x1UL << EXTI_RTSR1_TR12_Pos)              /*!< 0x00001000 */

+#define EXTI_RTSR1_TR12            EXTI_RTSR1_TR12_Msk                         /*!< Rising trigger event configuration bit of line 12 */

+#define EXTI_RTSR1_TR13_Pos        (13U)

+#define EXTI_RTSR1_TR13_Msk        (0x1UL << EXTI_RTSR1_TR13_Pos)              /*!< 0x00002000 */

+#define EXTI_RTSR1_TR13            EXTI_RTSR1_TR13_Msk                         /*!< Rising trigger event configuration bit of line 13 */

+#define EXTI_RTSR1_TR14_Pos        (14U)

+#define EXTI_RTSR1_TR14_Msk        (0x1UL << EXTI_RTSR1_TR14_Pos)              /*!< 0x00004000 */

+#define EXTI_RTSR1_TR14            EXTI_RTSR1_TR14_Msk                         /*!< Rising trigger event configuration bit of line 14 */

+#define EXTI_RTSR1_TR15_Pos        (15U)

+#define EXTI_RTSR1_TR15_Msk        (0x1UL << EXTI_RTSR1_TR15_Pos)              /*!< 0x00008000 */

+#define EXTI_RTSR1_TR15            EXTI_RTSR1_TR15_Msk                         /*!< Rising trigger event configuration bit of line 15 */

+#define EXTI_RTSR1_TR16_Pos        (16U)

+#define EXTI_RTSR1_TR16_Msk        (0x1UL << EXTI_RTSR1_TR16_Pos)              /*!< 0x00010000 */

+#define EXTI_RTSR1_TR16            EXTI_RTSR1_TR16_Msk                         /*!< Rising trigger event configuration bit of line 16 */

+#define EXTI_RTSR1_TR17_Pos        (17U)

+#define EXTI_RTSR1_TR17_Msk        (0x1UL << EXTI_RTSR1_TR17_Pos)              /*!< 0x00020000 */

+#define EXTI_RTSR1_TR17            EXTI_RTSR1_TR17_Msk                         /*!< Rising trigger event configuration bit of line 17 */

+#define EXTI_RTSR1_TR18_Pos        (18U)

+#define EXTI_RTSR1_TR18_Msk        (0x1UL << EXTI_RTSR1_TR18_Pos)              /*!< 0x00040000 */

+#define EXTI_RTSR1_TR18            EXTI_RTSR1_TR18_Msk                         /*!< Rising trigger event configuration bit of line 18 */

+#define EXTI_RTSR1_TR19_Pos        (19U)

+#define EXTI_RTSR1_TR19_Msk        (0x1UL << EXTI_RTSR1_TR19_Pos)              /*!< 0x00080000 */

+#define EXTI_RTSR1_TR19            EXTI_RTSR1_TR19_Msk                         /*!< Rising trigger event configuration bit of line 19 */

+#define EXTI_RTSR1_TR20_Pos        (20U)

+#define EXTI_RTSR1_TR20_Msk        (0x1UL << EXTI_RTSR1_TR20_Pos)              /*!< 0x00100000 */

+#define EXTI_RTSR1_TR20            EXTI_RTSR1_TR20_Msk                         /*!< Rising trigger event configuration bit of line 20 */

+#define EXTI_RTSR1_TR21_Pos        (21U)

+#define EXTI_RTSR1_TR21_Msk        (0x1UL << EXTI_RTSR1_TR21_Pos)              /*!< 0x00200000 */

+#define EXTI_RTSR1_TR21            EXTI_RTSR1_TR21_Msk                         /*!< Rising trigger event configuration bit of line 21 */

+

+/******************  Bit definition for EXTI_FTSR1 register  *******************/

+#define EXTI_FTSR1_TR_Pos          (0U)

+#define EXTI_FTSR1_TR_Msk          (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)           /*!< 0x003FFFFF */

+#define EXTI_FTSR1_TR              EXTI_FTSR1_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR1_TR0_Pos         (0U)

+#define EXTI_FTSR1_TR0_Msk         (0x1UL << EXTI_FTSR1_TR0_Pos)               /*!< 0x00000001 */

+#define EXTI_FTSR1_TR0             EXTI_FTSR1_TR0_Msk                          /*!< Falling trigger event configuration bit of line 0 */

+#define EXTI_FTSR1_TR1_Pos         (1U)

+#define EXTI_FTSR1_TR1_Msk         (0x1UL << EXTI_FTSR1_TR1_Pos)               /*!< 0x00000002 */

+#define EXTI_FTSR1_TR1             EXTI_FTSR1_TR1_Msk                          /*!< Falling trigger event configuration bit of line 1 */

+#define EXTI_FTSR1_TR2_Pos         (2U)

+#define EXTI_FTSR1_TR2_Msk         (0x1UL << EXTI_FTSR1_TR2_Pos)               /*!< 0x00000004 */

+#define EXTI_FTSR1_TR2             EXTI_FTSR1_TR2_Msk                          /*!< Falling trigger event configuration bit of line 2 */

+#define EXTI_FTSR1_TR3_Pos         (3U)

+#define EXTI_FTSR1_TR3_Msk         (0x1UL << EXTI_FTSR1_TR3_Pos)               /*!< 0x00000008 */

+#define EXTI_FTSR1_TR3             EXTI_FTSR1_TR3_Msk                          /*!< Falling trigger event configuration bit of line 3 */

+#define EXTI_FTSR1_TR4_Pos         (4U)

+#define EXTI_FTSR1_TR4_Msk         (0x1UL << EXTI_FTSR1_TR4_Pos)               /*!< 0x00000010 */

+#define EXTI_FTSR1_TR4             EXTI_FTSR1_TR4_Msk                          /*!< Falling trigger event configuration bit of line 4 */

+#define EXTI_FTSR1_TR5_Pos         (5U)

+#define EXTI_FTSR1_TR5_Msk         (0x1UL << EXTI_FTSR1_TR5_Pos)               /*!< 0x00000020 */

+#define EXTI_FTSR1_TR5             EXTI_FTSR1_TR5_Msk                          /*!< Falling trigger event configuration bit of line 5 */

+#define EXTI_FTSR1_TR6_Pos         (6U)

+#define EXTI_FTSR1_TR6_Msk         (0x1UL << EXTI_FTSR1_TR6_Pos)               /*!< 0x00000040 */

+#define EXTI_FTSR1_TR6             EXTI_FTSR1_TR6_Msk                          /*!< Falling trigger event configuration bit of line 6 */

+#define EXTI_FTSR1_TR7_Pos         (7U)

+#define EXTI_FTSR1_TR7_Msk         (0x1UL << EXTI_FTSR1_TR7_Pos)               /*!< 0x00000080 */

+#define EXTI_FTSR1_TR7             EXTI_FTSR1_TR7_Msk                          /*!< Falling trigger event configuration bit of line 7 */

+#define EXTI_FTSR1_TR8_Pos         (8U)

+#define EXTI_FTSR1_TR8_Msk         (0x1UL << EXTI_FTSR1_TR8_Pos)               /*!< 0x00000100 */

+#define EXTI_FTSR1_TR8             EXTI_FTSR1_TR8_Msk                          /*!< Falling trigger event configuration bit of line 8 */

+#define EXTI_FTSR1_TR9_Pos         (9U)

+#define EXTI_FTSR1_TR9_Msk         (0x1UL << EXTI_FTSR1_TR9_Pos)               /*!< 0x00000200 */

+#define EXTI_FTSR1_TR9             EXTI_FTSR1_TR9_Msk                          /*!< Falling trigger event configuration bit of line 9 */

+#define EXTI_FTSR1_TR10_Pos        (10U)

+#define EXTI_FTSR1_TR10_Msk        (0x1UL << EXTI_FTSR1_TR10_Pos)              /*!< 0x00000400 */

+#define EXTI_FTSR1_TR10            EXTI_FTSR1_TR10_Msk                         /*!< Falling trigger event configuration bit of line 10 */

+#define EXTI_FTSR1_TR11_Pos        (11U)

+#define EXTI_FTSR1_TR11_Msk        (0x1UL << EXTI_FTSR1_TR11_Pos)              /*!< 0x00000800 */

+#define EXTI_FTSR1_TR11            EXTI_FTSR1_TR11_Msk                         /*!< Falling trigger event configuration bit of line 11 */

+#define EXTI_FTSR1_TR12_Pos        (12U)

+#define EXTI_FTSR1_TR12_Msk        (0x1UL << EXTI_FTSR1_TR12_Pos)              /*!< 0x00001000 */

+#define EXTI_FTSR1_TR12            EXTI_FTSR1_TR12_Msk                         /*!< Falling trigger event configuration bit of line 12 */

+#define EXTI_FTSR1_TR13_Pos        (13U)

+#define EXTI_FTSR1_TR13_Msk        (0x1UL << EXTI_FTSR1_TR13_Pos)              /*!< 0x00002000 */

+#define EXTI_FTSR1_TR13            EXTI_FTSR1_TR13_Msk                         /*!< Falling trigger event configuration bit of line 13 */

+#define EXTI_FTSR1_TR14_Pos        (14U)

+#define EXTI_FTSR1_TR14_Msk        (0x1UL << EXTI_FTSR1_TR14_Pos)              /*!< 0x00004000 */

+#define EXTI_FTSR1_TR14            EXTI_FTSR1_TR14_Msk                         /*!< Falling trigger event configuration bit of line 14 */

+#define EXTI_FTSR1_TR15_Pos        (15U)

+#define EXTI_FTSR1_TR15_Msk        (0x1UL << EXTI_FTSR1_TR15_Pos)              /*!< 0x00008000 */

+#define EXTI_FTSR1_TR15            EXTI_FTSR1_TR15_Msk                         /*!< Falling trigger event configuration bit of line 15 */

+#define EXTI_FTSR1_TR16_Pos        (16U)

+#define EXTI_FTSR1_TR16_Msk        (0x1UL << EXTI_FTSR1_TR16_Pos)              /*!< 0x00010000 */

+#define EXTI_FTSR1_TR16            EXTI_FTSR1_TR16_Msk                         /*!< Falling trigger event configuration bit of line 16 */

+#define EXTI_FTSR1_TR17_Pos        (17U)

+#define EXTI_FTSR1_TR17_Msk        (0x1UL << EXTI_FTSR1_TR17_Pos)              /*!< 0x00020000 */

+#define EXTI_FTSR1_TR17            EXTI_FTSR1_TR17_Msk                         /*!< Falling trigger event configuration bit of line 17 */

+#define EXTI_FTSR1_TR18_Pos        (18U)

+#define EXTI_FTSR1_TR18_Msk        (0x1UL << EXTI_FTSR1_TR18_Pos)              /*!< 0x00040000 */

+#define EXTI_FTSR1_TR18            EXTI_FTSR1_TR18_Msk                         /*!< Falling trigger event configuration bit of line 18 */

+#define EXTI_FTSR1_TR19_Pos        (19U)

+#define EXTI_FTSR1_TR19_Msk        (0x1UL << EXTI_FTSR1_TR19_Pos)              /*!< 0x00080000 */

+#define EXTI_FTSR1_TR19            EXTI_FTSR1_TR19_Msk                         /*!< Falling trigger event configuration bit of line 19 */

+#define EXTI_FTSR1_TR20_Pos        (20U)

+#define EXTI_FTSR1_TR20_Msk        (0x1UL << EXTI_FTSR1_TR20_Pos)              /*!< 0x00100000 */

+#define EXTI_FTSR1_TR20            EXTI_FTSR1_TR20_Msk                         /*!< Falling trigger event configuration bit of line 20 */

+#define EXTI_FTSR1_TR21_Pos        (21U)

+#define EXTI_FTSR1_TR21_Msk        (0x1UL << EXTI_FTSR1_TR21_Pos)              /*!< 0x00200000 */

+#define EXTI_FTSR1_TR21            EXTI_FTSR1_TR21_Msk                         /*!< Falling trigger event configuration bit of line 21 */

+

+/******************  Bit definition for EXTI_SWIER1 register  ******************/

+#define EXTI_SWIER1_SWIER0_Pos     (0U)

+#define EXTI_SWIER1_SWIER0_Msk     (0x1UL << EXTI_SWIER1_SWIER0_Pos)           /*!< 0x00000001 */

+#define EXTI_SWIER1_SWIER0         EXTI_SWIER1_SWIER0_Msk                      /*!< Software Interrupt on line 0 */

+#define EXTI_SWIER1_SWIER1_Pos     (1U)

+#define EXTI_SWIER1_SWIER1_Msk     (0x1UL << EXTI_SWIER1_SWIER1_Pos)           /*!< 0x00000002 */

+#define EXTI_SWIER1_SWIER1         EXTI_SWIER1_SWIER1_Msk                      /*!< Software Interrupt on line 1 */

+#define EXTI_SWIER1_SWIER2_Pos     (2U)

+#define EXTI_SWIER1_SWIER2_Msk     (0x1UL << EXTI_SWIER1_SWIER2_Pos)           /*!< 0x00000004 */

+#define EXTI_SWIER1_SWIER2         EXTI_SWIER1_SWIER2_Msk                      /*!< Software Interrupt on line 2 */

+#define EXTI_SWIER1_SWIER3_Pos     (3U)

+#define EXTI_SWIER1_SWIER3_Msk     (0x1UL << EXTI_SWIER1_SWIER3_Pos)           /*!< 0x00000008 */

+#define EXTI_SWIER1_SWIER3         EXTI_SWIER1_SWIER3_Msk                      /*!< Software Interrupt on line 3 */

+#define EXTI_SWIER1_SWIER4_Pos     (4U)

+#define EXTI_SWIER1_SWIER4_Msk     (0x1UL << EXTI_SWIER1_SWIER4_Pos)           /*!< 0x00000010 */

+#define EXTI_SWIER1_SWIER4         EXTI_SWIER1_SWIER4_Msk                      /*!< Software Interrupt on line 4 */

+#define EXTI_SWIER1_SWIER5_Pos     (5U)

+#define EXTI_SWIER1_SWIER5_Msk     (0x1UL << EXTI_SWIER1_SWIER5_Pos)           /*!< 0x00000020 */

+#define EXTI_SWIER1_SWIER5         EXTI_SWIER1_SWIER5_Msk                      /*!< Software Interrupt on line 5 */

+#define EXTI_SWIER1_SWIER6_Pos     (6U)

+#define EXTI_SWIER1_SWIER6_Msk     (0x1UL << EXTI_SWIER1_SWIER6_Pos)           /*!< 0x00000040 */

+#define EXTI_SWIER1_SWIER6         EXTI_SWIER1_SWIER6_Msk                      /*!< Software Interrupt on line 6 */

+#define EXTI_SWIER1_SWIER7_Pos     (7U)

+#define EXTI_SWIER1_SWIER7_Msk     (0x1UL << EXTI_SWIER1_SWIER7_Pos)           /*!< 0x00000080 */

+#define EXTI_SWIER1_SWIER7         EXTI_SWIER1_SWIER7_Msk                      /*!< Software Interrupt on line 7 */

+#define EXTI_SWIER1_SWIER8_Pos     (8U)

+#define EXTI_SWIER1_SWIER8_Msk     (0x1UL << EXTI_SWIER1_SWIER8_Pos)           /*!< 0x00000100 */

+#define EXTI_SWIER1_SWIER8         EXTI_SWIER1_SWIER8_Msk                      /*!< Software Interrupt on line 8 */

+#define EXTI_SWIER1_SWIER9_Pos     (9U)

+#define EXTI_SWIER1_SWIER9_Msk     (0x1UL << EXTI_SWIER1_SWIER9_Pos)           /*!< 0x00000200 */

+#define EXTI_SWIER1_SWIER9         EXTI_SWIER1_SWIER9_Msk                      /*!< Software Interrupt on line 9 */

+#define EXTI_SWIER1_SWIER10_Pos    (10U)

+#define EXTI_SWIER1_SWIER10_Msk    (0x1UL << EXTI_SWIER1_SWIER10_Pos)          /*!< 0x00000400 */

+#define EXTI_SWIER1_SWIER10        EXTI_SWIER1_SWIER10_Msk                     /*!< Software Interrupt on line 10 */

+#define EXTI_SWIER1_SWIER11_Pos    (11U)

+#define EXTI_SWIER1_SWIER11_Msk    (0x1UL << EXTI_SWIER1_SWIER11_Pos)          /*!< 0x00000800 */

+#define EXTI_SWIER1_SWIER11        EXTI_SWIER1_SWIER11_Msk                     /*!< Software Interrupt on line 11 */

+#define EXTI_SWIER1_SWIER12_Pos    (12U)

+#define EXTI_SWIER1_SWIER12_Msk    (0x1UL << EXTI_SWIER1_SWIER12_Pos)          /*!< 0x00001000 */

+#define EXTI_SWIER1_SWIER12        EXTI_SWIER1_SWIER12_Msk                     /*!< Software Interrupt on line 12 */

+#define EXTI_SWIER1_SWIER13_Pos    (13U)

+#define EXTI_SWIER1_SWIER13_Msk    (0x1UL << EXTI_SWIER1_SWIER13_Pos)          /*!< 0x00002000 */

+#define EXTI_SWIER1_SWIER13        EXTI_SWIER1_SWIER13_Msk                     /*!< Software Interrupt on line 13 */

+#define EXTI_SWIER1_SWIER14_Pos    (14U)

+#define EXTI_SWIER1_SWIER14_Msk    (0x1UL << EXTI_SWIER1_SWIER14_Pos)          /*!< 0x00004000 */

+#define EXTI_SWIER1_SWIER14        EXTI_SWIER1_SWIER14_Msk                     /*!< Software Interrupt on line 14 */

+#define EXTI_SWIER1_SWIER15_Pos    (15U)

+#define EXTI_SWIER1_SWIER15_Msk    (0x1UL << EXTI_SWIER1_SWIER15_Pos)          /*!< 0x00008000 */

+#define EXTI_SWIER1_SWIER15        EXTI_SWIER1_SWIER15_Msk                     /*!< Software Interrupt on line 15 */

+#define EXTI_SWIER1_SWIER16_Pos    (16U)

+#define EXTI_SWIER1_SWIER16_Msk    (0x1UL << EXTI_SWIER1_SWIER16_Pos)          /*!< 0x00010000 */

+#define EXTI_SWIER1_SWIER16        EXTI_SWIER1_SWIER16_Msk                     /*!< Software Interrupt on line 16 */

+#define EXTI_SWIER1_SWIER17_Pos    (17U)

+#define EXTI_SWIER1_SWIER17_Msk    (0x1UL << EXTI_SWIER1_SWIER17_Pos)          /*!< 0x00020000 */

+#define EXTI_SWIER1_SWIER17        EXTI_SWIER1_SWIER17_Msk                     /*!< Software Interrupt on line 17 */

+#define EXTI_SWIER1_SWIER18_Pos    (18U)

+#define EXTI_SWIER1_SWIER18_Msk    (0x1UL << EXTI_SWIER1_SWIER18_Pos)          /*!< 0x00040000 */

+#define EXTI_SWIER1_SWIER18        EXTI_SWIER1_SWIER18_Msk                     /*!< Software Interrupt on line 18 */

+#define EXTI_SWIER1_SWIER19_Pos    (19U)

+#define EXTI_SWIER1_SWIER19_Msk    (0x1UL << EXTI_SWIER1_SWIER19_Pos)          /*!< 0x00080000 */

+#define EXTI_SWIER1_SWIER19        EXTI_SWIER1_SWIER19_Msk                     /*!< Software Interrupt on line 19 */

+#define EXTI_SWIER1_SWIER20_Pos    (20U)

+#define EXTI_SWIER1_SWIER20_Msk    (0x1UL << EXTI_SWIER1_SWIER20_Pos)          /*!< 0x00100000 */

+#define EXTI_SWIER1_SWIER20        EXTI_SWIER1_SWIER20_Msk                     /*!< Software Interrupt on line 20 */

+#define EXTI_SWIER1_SWIER21_Pos    (21U)

+#define EXTI_SWIER1_SWIER21_Msk    (0x1UL << EXTI_SWIER1_SWIER21_Pos)          /*!< 0x00200000 */

+#define EXTI_SWIER1_SWIER21        EXTI_SWIER1_SWIER21_Msk                     /*!< Software Interrupt on line 21 */

+

+/******************  Bit definition for EXTI_D3PMR1 register  ******************/

+#define EXTI_D3PMR1_MR0_Pos        (0U)

+#define EXTI_D3PMR1_MR0_Msk        (0x1UL << EXTI_D3PMR1_MR0_Pos)              /*!< 0x00000001 */

+#define EXTI_D3PMR1_MR0            EXTI_D3PMR1_MR0_Msk                         /*!< Pending Mask Event for line 0  */

+#define EXTI_D3PMR1_MR1_Pos        (1U)

+#define EXTI_D3PMR1_MR1_Msk        (0x1UL << EXTI_D3PMR1_MR1_Pos)              /*!< 0x00000002 */

+#define EXTI_D3PMR1_MR1            EXTI_D3PMR1_MR1_Msk                         /*!< Pending Mask Event for line 1  */

+#define EXTI_D3PMR1_MR2_Pos        (2U)

+#define EXTI_D3PMR1_MR2_Msk        (0x1UL << EXTI_D3PMR1_MR2_Pos)              /*!< 0x00000004 */

+#define EXTI_D3PMR1_MR2            EXTI_D3PMR1_MR2_Msk                         /*!< Pending Mask Event for line 2  */

+#define EXTI_D3PMR1_MR3_Pos        (3U)

+#define EXTI_D3PMR1_MR3_Msk        (0x1UL << EXTI_D3PMR1_MR3_Pos)              /*!< 0x00000008 */

+#define EXTI_D3PMR1_MR3            EXTI_D3PMR1_MR3_Msk                         /*!< Pending Mask Event for line 3  */

+#define EXTI_D3PMR1_MR4_Pos        (4U)

+#define EXTI_D3PMR1_MR4_Msk        (0x1UL << EXTI_D3PMR1_MR4_Pos)              /*!< 0x00000010 */

+#define EXTI_D3PMR1_MR4            EXTI_D3PMR1_MR4_Msk                         /*!< Pending Mask Event for line 4  */

+#define EXTI_D3PMR1_MR5_Pos        (5U)

+#define EXTI_D3PMR1_MR5_Msk        (0x1UL << EXTI_D3PMR1_MR5_Pos)              /*!< 0x00000020 */

+#define EXTI_D3PMR1_MR5            EXTI_D3PMR1_MR5_Msk                         /*!< Pending Mask Event for line 5  */

+#define EXTI_D3PMR1_MR6_Pos        (6U)

+#define EXTI_D3PMR1_MR6_Msk        (0x1UL << EXTI_D3PMR1_MR6_Pos)              /*!< 0x00000040 */

+#define EXTI_D3PMR1_MR6            EXTI_D3PMR1_MR6_Msk                         /*!< Pending Mask Event for line 6  */

+#define EXTI_D3PMR1_MR7_Pos        (7U)

+#define EXTI_D3PMR1_MR7_Msk        (0x1UL << EXTI_D3PMR1_MR7_Pos)              /*!< 0x00000080 */

+#define EXTI_D3PMR1_MR7            EXTI_D3PMR1_MR7_Msk                         /*!< Pending Mask Event for line 7  */

+#define EXTI_D3PMR1_MR8_Pos        (8U)

+#define EXTI_D3PMR1_MR8_Msk        (0x1UL << EXTI_D3PMR1_MR8_Pos)              /*!< 0x00000100 */

+#define EXTI_D3PMR1_MR8            EXTI_D3PMR1_MR8_Msk                         /*!< Pending Mask Event for line 8  */

+#define EXTI_D3PMR1_MR9_Pos        (9U)

+#define EXTI_D3PMR1_MR9_Msk        (0x1UL << EXTI_D3PMR1_MR9_Pos)              /*!< 0x00000200 */

+#define EXTI_D3PMR1_MR9            EXTI_D3PMR1_MR9_Msk                         /*!< Pending Mask Event for line 9  */

+#define EXTI_D3PMR1_MR10_Pos       (10U)

+#define EXTI_D3PMR1_MR10_Msk       (0x1UL << EXTI_D3PMR1_MR10_Pos)             /*!< 0x00000400 */

+#define EXTI_D3PMR1_MR10           EXTI_D3PMR1_MR10_Msk                        /*!< Pending Mask Event for line 10 */

+#define EXTI_D3PMR1_MR11_Pos       (11U)

+#define EXTI_D3PMR1_MR11_Msk       (0x1UL << EXTI_D3PMR1_MR11_Pos)             /*!< 0x00000800 */

+#define EXTI_D3PMR1_MR11           EXTI_D3PMR1_MR11_Msk                        /*!< Pending Mask Event for line 11 */

+#define EXTI_D3PMR1_MR12_Pos       (12U)

+#define EXTI_D3PMR1_MR12_Msk       (0x1UL << EXTI_D3PMR1_MR12_Pos)             /*!< 0x00001000 */

+#define EXTI_D3PMR1_MR12           EXTI_D3PMR1_MR12_Msk                        /*!< Pending Mask Event for line 12 */

+#define EXTI_D3PMR1_MR13_Pos       (13U)

+#define EXTI_D3PMR1_MR13_Msk       (0x1UL << EXTI_D3PMR1_MR13_Pos)             /*!< 0x00002000 */

+#define EXTI_D3PMR1_MR13           EXTI_D3PMR1_MR13_Msk                        /*!< Pending Mask Event for line 13 */

+#define EXTI_D3PMR1_MR14_Pos       (14U)

+#define EXTI_D3PMR1_MR14_Msk       (0x1UL << EXTI_D3PMR1_MR14_Pos)             /*!< 0x00004000 */

+#define EXTI_D3PMR1_MR14           EXTI_D3PMR1_MR14_Msk                        /*!< Pending Mask Event for line 14 */

+#define EXTI_D3PMR1_MR15_Pos       (15U)

+#define EXTI_D3PMR1_MR15_Msk       (0x1UL << EXTI_D3PMR1_MR15_Pos)             /*!< 0x00008000 */

+#define EXTI_D3PMR1_MR15           EXTI_D3PMR1_MR15_Msk                        /*!< Pending Mask Event for line 15 */

+#define EXTI_D3PMR1_MR19_Pos       (19U)

+#define EXTI_D3PMR1_MR19_Msk       (0x1UL << EXTI_D3PMR1_MR19_Pos)             /*!< 0x00080000 */

+#define EXTI_D3PMR1_MR19           EXTI_D3PMR1_MR19_Msk                        /*!< Pending Mask Event for line 19 */

+#define EXTI_D3PMR1_MR20_Pos       (20U)

+#define EXTI_D3PMR1_MR20_Msk       (0x1UL << EXTI_D3PMR1_MR20_Pos)             /*!< 0x00100000 */

+#define EXTI_D3PMR1_MR20           EXTI_D3PMR1_MR20_Msk                        /*!< Pending Mask Event for line 20 */

+#define EXTI_D3PMR1_MR21_Pos       (21U)

+#define EXTI_D3PMR1_MR21_Msk       (0x1UL << EXTI_D3PMR1_MR21_Pos)             /*!< 0x00200000 */

+#define EXTI_D3PMR1_MR21           EXTI_D3PMR1_MR21_Msk                        /*!< Pending Mask Event for line 21 */

+#define EXTI_D3PMR1_MR25_Pos       (24U)

+#define EXTI_D3PMR1_MR25_Msk       (0x1UL << EXTI_D3PMR1_MR25_Pos)             /*!< 0x01000000 */

+#define EXTI_D3PMR1_MR25           EXTI_D3PMR1_MR25_Msk                        /*!< Pending Mask Event for line 25 */

+

+/*******************  Bit definition for EXTI_D3PCR1L register  ****************/

+#define EXTI_D3PCR1L_PCS0_Pos       (0U)

+#define EXTI_D3PCR1L_PCS0_Msk       (0x3UL << EXTI_D3PCR1L_PCS0_Pos)           /*!< 0x00000003 */

+#define EXTI_D3PCR1L_PCS0           EXTI_D3PCR1L_PCS0_Msk                      /*!< D3 Pending request clear input signal selection on line 0 */

+#define EXTI_D3PCR1L_PCS1_Pos       (2U)

+#define EXTI_D3PCR1L_PCS1_Msk       (0x3UL << EXTI_D3PCR1L_PCS1_Pos)           /*!< 0x000000C0 */

+#define EXTI_D3PCR1L_PCS1           EXTI_D3PCR1L_PCS1_Msk                      /*!< D3 Pending request clear input signal selection on line 1 */

+#define EXTI_D3PCR1L_PCS2_Pos       (4U)

+#define EXTI_D3PCR1L_PCS2_Msk       (0x3UL << EXTI_D3PCR1L_PCS2_Pos)           /*!< 0x00000030 */

+#define EXTI_D3PCR1L_PCS2           EXTI_D3PCR1L_PCS2_Msk                      /*!< D3 Pending request clear input signal selection on line 2 */

+#define EXTI_D3PCR1L_PCS3_Pos       (6U)

+#define EXTI_D3PCR1L_PCS3_Msk       (0x3UL << EXTI_D3PCR1L_PCS3_Pos)           /*!< 0x000000C0 */

+#define EXTI_D3PCR1L_PCS3           EXTI_D3PCR1L_PCS3_Msk                      /*!< D3 Pending request clear input signal selection on line 3 */

+#define EXTI_D3PCR1L_PCS4_Pos       (8U)

+#define EXTI_D3PCR1L_PCS4_Msk       (0x3UL << EXTI_D3PCR1L_PCS4_Pos)           /*!< 0x00000300 */

+#define EXTI_D3PCR1L_PCS4           EXTI_D3PCR1L_PCS4_Msk                      /*!< D3 Pending request clear input signal selection on line 4 */

+#define EXTI_D3PCR1L_PCS5_Pos       (10U)

+#define EXTI_D3PCR1L_PCS5_Msk       (0x3UL << EXTI_D3PCR1L_PCS5_Pos)           /*!< 0x00000C00 */

+#define EXTI_D3PCR1L_PCS5           EXTI_D3PCR1L_PCS5_Msk                      /*!< D3 Pending request clear input signal selection on line 5 */

+#define EXTI_D3PCR1L_PCS6_Pos       (12U)

+#define EXTI_D3PCR1L_PCS6_Msk       (0x3UL << EXTI_D3PCR1L_PCS6_Pos)           /*!< 0x00003000 */

+#define EXTI_D3PCR1L_PCS6           EXTI_D3PCR1L_PCS6_Msk                      /*!< D3 Pending request clear input signal selection on line 6 */

+#define EXTI_D3PCR1L_PCS7_Pos       (14U)

+#define EXTI_D3PCR1L_PCS7_Msk       (0x3UL << EXTI_D3PCR1L_PCS7_Pos)           /*!< 0x0000C000 */

+#define EXTI_D3PCR1L_PCS7           EXTI_D3PCR1L_PCS7_Msk                      /*!< D3 Pending request clear input signal selection on line 7 */

+#define EXTI_D3PCR1L_PCS8_Pos       (16U)

+#define EXTI_D3PCR1L_PCS8_Msk       (0x3UL << EXTI_D3PCR1L_PCS8_Pos)           /*!< 0x00030000 */

+#define EXTI_D3PCR1L_PCS8           EXTI_D3PCR1L_PCS8_Msk                      /*!< D3 Pending request clear input signal selection on line 8 */

+#define EXTI_D3PCR1L_PCS9_Pos       (18U)

+#define EXTI_D3PCR1L_PCS9_Msk       (0x3UL << EXTI_D3PCR1L_PCS9_Pos)           /*!< 0x000C0000 */

+#define EXTI_D3PCR1L_PCS9           EXTI_D3PCR1L_PCS9_Msk                      /*!< D3 Pending request clear input signal selection on line 9 */

+#define EXTI_D3PCR1L_PCS10_Pos      (20U)

+#define EXTI_D3PCR1L_PCS10_Msk      (0x3UL << EXTI_D3PCR1L_PCS10_Pos)          /*!< 0x00300000 */

+#define EXTI_D3PCR1L_PCS10          EXTI_D3PCR1L_PCS10_Msk                     /*!< D3 Pending request clear input signal selection on line 10*/

+#define EXTI_D3PCR1L_PCS11_Pos      (22U)

+#define EXTI_D3PCR1L_PCS11_Msk      (0x3UL << EXTI_D3PCR1L_PCS11_Pos)          /*!< 0x00C00000 */

+#define EXTI_D3PCR1L_PCS11          EXTI_D3PCR1L_PCS11_Msk                     /*!< D3 Pending request clear input signal selection on line 11*/

+#define EXTI_D3PCR1L_PCS12_Pos      (24U)

+#define EXTI_D3PCR1L_PCS12_Msk      (0x3UL << EXTI_D3PCR1L_PCS12_Pos)          /*!< 0x03000000 */

+#define EXTI_D3PCR1L_PCS12          EXTI_D3PCR1L_PCS12_Msk                     /*!< D3 Pending request clear input signal selection on line 12*/

+#define EXTI_D3PCR1L_PCS13_Pos      (26U)

+#define EXTI_D3PCR1L_PCS13_Msk      (0x3UL << EXTI_D3PCR1L_PCS13_Pos)          /*!< 0x0C000000 */

+#define EXTI_D3PCR1L_PCS13          EXTI_D3PCR1L_PCS13_Msk                     /*!< D3 Pending request clear input signal selection on line 13*/

+#define EXTI_D3PCR1L_PCS14_Pos      (28U)

+#define EXTI_D3PCR1L_PCS14_Msk      (0x3UL << EXTI_D3PCR1L_PCS14_Pos)          /*!< 0x30000000 */

+#define EXTI_D3PCR1L_PCS14          EXTI_D3PCR1L_PCS14_Msk                     /*!< D3 Pending request clear input signal selection on line 14*/

+#define EXTI_D3PCR1L_PCS15_Pos      (30U)

+#define EXTI_D3PCR1L_PCS15_Msk      (0x3UL << EXTI_D3PCR1L_PCS15_Pos)          /*!< 0xC0000000 */

+#define EXTI_D3PCR1L_PCS15          EXTI_D3PCR1L_PCS15_Msk                     /*!< D3 Pending request clear input signal selection on line 15*/

+

+/*******************  Bit definition for EXTI_D3PCR1H register  ****************/

+#define EXTI_D3PCR1H_PCS19_Pos       (6U)

+#define EXTI_D3PCR1H_PCS19_Msk       (0x3UL << EXTI_D3PCR1H_PCS19_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR1H_PCS19           EXTI_D3PCR1H_PCS19_Msk                    /*!< D3 Pending request clear input signal selection on line 19 */

+#define EXTI_D3PCR1H_PCS20_Pos       (8U)

+#define EXTI_D3PCR1H_PCS20_Msk       (0x3UL << EXTI_D3PCR1H_PCS20_Pos)         /*!< 0x00000300 */

+#define EXTI_D3PCR1H_PCS20           EXTI_D3PCR1H_PCS20_Msk                    /*!< D3 Pending request clear input signal selection on line 20 */

+#define EXTI_D3PCR1H_PCS21_Pos       (10U)

+#define EXTI_D3PCR1H_PCS21_Msk       (0x3UL << EXTI_D3PCR1H_PCS21_Pos)         /*!< 0x00000C00 */

+#define EXTI_D3PCR1H_PCS21           EXTI_D3PCR1H_PCS21_Msk                    /*!< D3 Pending request clear input signal selection on line 21 */

+#define EXTI_D3PCR1H_PCS25_Pos       (18U)

+#define EXTI_D3PCR1H_PCS25_Msk       (0x3UL << EXTI_D3PCR1H_PCS25_Pos)         /*!< 0x000C0000 */

+#define EXTI_D3PCR1H_PCS25           EXTI_D3PCR1H_PCS25_Msk                    /*!< D3 Pending request clear input signal selection on line 25 */

+

+/******************  Bit definition for EXTI_RTSR2 register  *******************/

+#define EXTI_RTSR2_TR_Pos          (17U)

+#define EXTI_RTSR2_TR_Msk          (0x5UL << EXTI_RTSR2_TR_Pos)                /*!< 0x000A0000 */

+#define EXTI_RTSR2_TR              EXTI_RTSR2_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR2_TR49_Pos        (17U)

+#define EXTI_RTSR2_TR49_Msk        (0x1UL << EXTI_RTSR2_TR49_Pos)              /*!< 0x00020000 */

+#define EXTI_RTSR2_TR49            EXTI_RTSR2_TR49_Msk                         /*!< Rising trigger event configuration bit of line 49 */

+#define EXTI_RTSR2_TR51_Pos        (19U)

+#define EXTI_RTSR2_TR51_Msk        (0x1UL << EXTI_RTSR2_TR51_Pos)              /*!< 0x00080000 */

+#define EXTI_RTSR2_TR51            EXTI_RTSR2_TR51_Msk                         /*!< Rising trigger event configuration bit of line 51 */

+

+/******************  Bit definition for EXTI_FTSR2 register  *******************/

+#define EXTI_FTSR2_TR_Pos          (17U)

+#define EXTI_FTSR2_TR_Msk          (0x5UL << EXTI_FTSR2_TR_Pos)                /*!< 0x000A0000 */

+#define EXTI_FTSR2_TR              EXTI_FTSR2_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR2_TR49_Pos        (17U)

+#define EXTI_FTSR2_TR49_Msk        (0x1UL << EXTI_FTSR2_TR49_Pos)              /*!< 0x00020000 */

+#define EXTI_FTSR2_TR49            EXTI_FTSR2_TR49_Msk                         /*!< Falling trigger event configuration bit of line 49 */

+#define EXTI_FTSR2_TR51_Pos        (19U)

+#define EXTI_FTSR2_TR51_Msk        (0x1UL << EXTI_FTSR2_TR51_Pos)              /*!< 0x00080000 */

+#define EXTI_FTSR2_TR51            EXTI_FTSR2_TR51_Msk                         /*!< Falling trigger event configuration bit of line 51 */

+

+/******************  Bit definition for EXTI_SWIER2 register  ******************/

+#define EXTI_SWIER2_SWIER49_Pos    (17U)

+#define EXTI_SWIER2_SWIER49_Msk    (0x1UL << EXTI_SWIER2_SWIER49_Pos)          /*!< 0x00020000 */

+#define EXTI_SWIER2_SWIER49        EXTI_SWIER2_SWIER49_Msk                     /*!< Software Interrupt on line 49 */

+#define EXTI_SWIER2_SWIER51_Pos    (19U)

+#define EXTI_SWIER2_SWIER51_Msk    (0x1UL << EXTI_SWIER2_SWIER51_Pos)          /*!< 0x00080000 */

+#define EXTI_SWIER2_SWIER51        EXTI_SWIER2_SWIER51_Msk                     /*!< Software Interrupt on line 51 */

+

+/******************  Bit definition for EXTI_D3PMR2 register  ******************/

+#define EXTI_D3PMR2_MR34_Pos       (2U)

+#define EXTI_D3PMR2_MR34_Msk       (0x1UL << EXTI_D3PMR2_MR34_Pos)             /*!< 0x00000004 */

+#define EXTI_D3PMR2_MR34           EXTI_D3PMR2_MR34_Msk                        /*!< Pending Mask Event for line 34  */

+#define EXTI_D3PMR2_MR35_Pos       (3U)

+#define EXTI_D3PMR2_MR35_Msk       (0x1UL << EXTI_D3PMR2_MR35_Pos)             /*!< 0x00000008 */

+#define EXTI_D3PMR2_MR35           EXTI_D3PMR2_MR35_Msk                        /*!< Pending Mask Event for line 35  */

+#define EXTI_D3PMR2_MR41_Pos       (9U)

+#define EXTI_D3PMR2_MR41_Msk       (0x1UL << EXTI_D3PMR2_MR41_Pos)             /*!< 0x00000200 */

+#define EXTI_D3PMR2_MR41           EXTI_D3PMR2_MR41_Msk                        /*!< Pending Mask Event for line 41  */

+#define EXTI_D3PMR2_MR48_Pos       (16U)

+#define EXTI_D3PMR2_MR48_Msk       (0x1UL << EXTI_D3PMR2_MR48_Pos)             /*!< 0x00010000 */

+#define EXTI_D3PMR2_MR48           EXTI_D3PMR2_MR48_Msk                        /*!< Pending Mask Event for line 48  */

+#define EXTI_D3PMR2_MR49_Pos       (17U)

+#define EXTI_D3PMR2_MR49_Msk       (0x1UL << EXTI_D3PMR2_MR49_Pos)             /*!< 0x00020000 */

+#define EXTI_D3PMR2_MR49           EXTI_D3PMR2_MR49_Msk                        /*!< Pending Mask Event for line 49  */

+#define EXTI_D3PMR2_MR50_Pos       (18U)

+#define EXTI_D3PMR2_MR50_Msk       (0x1UL << EXTI_D3PMR2_MR50_Pos)             /*!< 0x00040000 */

+#define EXTI_D3PMR2_MR50           EXTI_D3PMR2_MR50_Msk                        /*!< Pending Mask Event for line 50  */

+#define EXTI_D3PMR2_MR51_Pos       (19U)

+#define EXTI_D3PMR2_MR51_Msk       (0x1UL << EXTI_D3PMR2_MR51_Pos)             /*!< 0x00080000 */

+#define EXTI_D3PMR2_MR51           EXTI_D3PMR2_MR51_Msk                        /*!< Pending Mask Event for line 51  */

+#define EXTI_D3PMR2_MR52_Pos       (20U)

+#define EXTI_D3PMR2_MR52_Msk       (0x1UL << EXTI_D3PMR2_MR52_Pos)             /*!< 0x00100000 */

+#define EXTI_D3PMR2_MR52           EXTI_D3PMR2_MR52_Msk                        /*!< Pending Mask Event for line 52  */

+#define EXTI_D3PMR2_MR53_Pos       (21U)

+#define EXTI_D3PMR2_MR53_Msk       (0x1UL << EXTI_D3PMR2_MR53_Pos)             /*!< 0x00200000 */

+#define EXTI_D3PMR2_MR53           EXTI_D3PMR2_MR53_Msk                        /*!< Pending Mask Event for line 53  */

+/*******************  Bit definition for EXTI_D3PCR2L register  ****************/

+#define EXTI_D3PCR2L_PCS34_Pos       (4U)

+#define EXTI_D3PCR2L_PCS34_Msk       (0x3UL << EXTI_D3PCR2L_PCS34_Pos)         /*!< 0x00000030 */

+#define EXTI_D3PCR2L_PCS34           EXTI_D3PCR2L_PCS34_Msk                    /*!< D3 Pending request clear input signal selection on line 34 */

+#define EXTI_D3PCR2L_PCS35_Pos       (6U)

+#define EXTI_D3PCR2L_PCS35_Msk       (0x3UL << EXTI_D3PCR2L_PCS35_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR2L_PCS35           EXTI_D3PCR2L_PCS35_Msk                    /*!< D3 Pending request clear input signal selection on line 35 */

+#define EXTI_D3PCR2L_PCS41_Pos       (18U)

+#define EXTI_D3PCR2L_PCS41_Msk       (0x3UL << EXTI_D3PCR2L_PCS41_Pos)         /*!< 0x000C0000 */

+#define EXTI_D3PCR2L_PCS41           EXTI_D3PCR2L_PCS41_Msk                    /*!< D3 Pending request clear input signal selection on line 41 */

+

+

+/*******************  Bit definition for EXTI_D3PCR2H register  ****************/

+#define EXTI_D3PCR2H_PCS48_Pos       (0U)

+#define EXTI_D3PCR2H_PCS48_Msk       (0x3UL << EXTI_D3PCR2H_PCS48_Pos)         /*!< 0x00000003 */

+#define EXTI_D3PCR2H_PCS48           EXTI_D3PCR2H_PCS48_Msk                    /*!< D3 Pending request clear input signal selection on line 48 */

+#define EXTI_D3PCR2H_PCS49_Pos       (2U)

+#define EXTI_D3PCR2H_PCS49_Msk       (0x3UL << EXTI_D3PCR2H_PCS49_Pos)         /*!< 0x0000000C */

+#define EXTI_D3PCR2H_PCS49           EXTI_D3PCR2H_PCS49_Msk                    /*!< D3 Pending request clear input signal selection on line 49 */

+#define EXTI_D3PCR2H_PCS50_Pos       (4U)

+#define EXTI_D3PCR2H_PCS50_Msk       (0x3UL << EXTI_D3PCR2H_PCS50_Pos)         /*!< 0x00000030 */

+#define EXTI_D3PCR2H_PCS50           EXTI_D3PCR2H_PCS50_Msk                    /*!< D3 Pending request clear input signal selection on line 50 */

+#define EXTI_D3PCR2H_PCS51_Pos       (6U)

+#define EXTI_D3PCR2H_PCS51_Msk       (0x3UL << EXTI_D3PCR2H_PCS51_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR2H_PCS51           EXTI_D3PCR2H_PCS51_Msk                    /*!< D3 Pending request clear input signal selection on line 51 */

+#define EXTI_D3PCR2H_PCS52_Pos       (8U)

+#define EXTI_D3PCR2H_PCS52_Msk       (0x3UL << EXTI_D3PCR2H_PCS52_Pos)         /*!< 0x00000300 */

+#define EXTI_D3PCR2H_PCS52           EXTI_D3PCR2H_PCS52_Msk                    /*!< D3 Pending request clear input signal selection on line 52 */

+#define EXTI_D3PCR2H_PCS53_Pos       (10U)

+#define EXTI_D3PCR2H_PCS53_Msk       (0x3UL << EXTI_D3PCR2H_PCS53_Pos)         /*!< 0x00000C00 */

+#define EXTI_D3PCR2H_PCS53           EXTI_D3PCR2H_PCS53_Msk                    /*!< D3 Pending request clear input signal selection on line 53 */

+/******************  Bit definition for EXTI_RTSR3 register  *******************/

+#define EXTI_RTSR3_TR_Pos          (18U)

+#define EXTI_RTSR3_TR_Msk          (0x1DUL << EXTI_RTSR3_TR_Pos)               /*!< 0x00740000 */

+#define EXTI_RTSR3_TR              EXTI_RTSR3_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR3_TR82_Pos        (18U)

+#define EXTI_RTSR3_TR82_Msk        (0x1UL << EXTI_RTSR3_TR82_Pos)              /*!< 0x00040000 */

+#define EXTI_RTSR3_TR82            EXTI_RTSR3_TR82_Msk                         /*!< Rising trigger event configuration bit of line 82 */

+#define EXTI_RTSR3_TR84_Pos        (20U)

+#define EXTI_RTSR3_TR84_Msk        (0x1UL << EXTI_RTSR3_TR84_Pos)              /*!< 0x00100000 */

+#define EXTI_RTSR3_TR84            EXTI_RTSR3_TR84_Msk                         /*!< Rising trigger event configuration bit of line 84 */

+#define EXTI_RTSR3_TR85_Pos        (21U)

+#define EXTI_RTSR3_TR85_Msk        (0x1UL << EXTI_RTSR3_TR85_Pos)              /*!< 0x00200000 */

+#define EXTI_RTSR3_TR85            EXTI_RTSR3_TR85_Msk                         /*!< Rising trigger event configuration bit of line 85 */

+#define EXTI_RTSR3_TR86_Pos        (22U)

+#define EXTI_RTSR3_TR86_Msk        (0x1UL << EXTI_RTSR3_TR86_Pos)              /*!< 0x00400000 */

+#define EXTI_RTSR3_TR86            EXTI_RTSR3_TR86_Msk                         /*!< Rising trigger event configuration bit of line 86 */

+

+/******************  Bit definition for EXTI_FTSR3 register  *******************/

+#define EXTI_FTSR3_TR_Pos          (18U)

+#define EXTI_FTSR3_TR_Msk          (0x1DUL << EXTI_FTSR3_TR_Pos)               /*!< 0x00740000 */

+#define EXTI_FTSR3_TR              EXTI_FTSR3_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR3_TR82_Pos        (18U)

+#define EXTI_FTSR3_TR82_Msk        (0x1UL << EXTI_FTSR3_TR82_Pos)              /*!< 0x00040000 */

+#define EXTI_FTSR3_TR82            EXTI_FTSR3_TR82_Msk                         /*!< Falling trigger event configuration bit of line 82 */

+#define EXTI_FTSR3_TR84_Pos        (20U)

+#define EXTI_FTSR3_TR84_Msk        (0x1UL << EXTI_FTSR3_TR84_Pos)              /*!< 0x00100000 */

+#define EXTI_FTSR3_TR84            EXTI_FTSR3_TR84_Msk                         /*!< Falling trigger event configuration bit of line 84 */

+#define EXTI_FTSR3_TR85_Pos        (21U)

+#define EXTI_FTSR3_TR85_Msk        (0x1UL << EXTI_FTSR3_TR85_Pos)              /*!< 0x00200000 */

+#define EXTI_FTSR3_TR85            EXTI_FTSR3_TR85_Msk                         /*!< Falling trigger event configuration bit of line 85 */

+#define EXTI_FTSR3_TR86_Pos        (22U)

+#define EXTI_FTSR3_TR86_Msk        (0x1UL << EXTI_FTSR3_TR86_Pos)              /*!< 0x00400000 */

+#define EXTI_FTSR3_TR86            EXTI_FTSR3_TR86_Msk                         /*!< Falling trigger event configuration bit of line 86 */

+

+/******************  Bit definition for EXTI_SWIER3 register  ******************/

+#define EXTI_SWIER3_SWI_Pos        (18U)

+#define EXTI_SWIER3_SWI_Msk        (0x1DUL << EXTI_SWIER3_SWI_Pos)             /*!< 0x00740000 */

+#define EXTI_SWIER3_SWI            EXTI_SWIER3_SWI_Msk                         /*!< Software Interrupt event bit */

+#define EXTI_SWIER3_SWIER82_Pos    (18U)

+#define EXTI_SWIER3_SWIER82_Msk    (0x1UL << EXTI_SWIER3_SWIER82_Pos)          /*!< 0x00040000 */

+#define EXTI_SWIER3_SWIER82        EXTI_SWIER3_SWIER82_Msk                     /*!< Software Interrupt on line 82 */

+#define EXTI_SWIER3_SWIER84_Pos    (20U)

+#define EXTI_SWIER3_SWIER84_Msk    (0x1UL << EXTI_SWIER3_SWIER84_Pos)          /*!< 0x00100000 */

+#define EXTI_SWIER3_SWIER84        EXTI_SWIER3_SWIER84_Msk                     /*!< Software Interrupt on line 84 */

+#define EXTI_SWIER3_SWIER85_Pos    (21U)

+#define EXTI_SWIER3_SWIER85_Msk    (0x1UL << EXTI_SWIER3_SWIER85_Pos)          /*!< 0x00200000 */

+#define EXTI_SWIER3_SWIER85        EXTI_SWIER3_SWIER85_Msk                     /*!< Software Interrupt on line 85 */

+#define EXTI_SWIER3_SWIER86_Pos    (22U)

+#define EXTI_SWIER3_SWIER86_Msk    (0x1UL << EXTI_SWIER3_SWIER86_Pos)          /*!< 0x00400000 */

+#define EXTI_SWIER3_SWIER86        EXTI_SWIER3_SWIER86_Msk                     /*!< Software Interrupt on line 86 */

+

+/*******************  Bit definition for EXTI_IMR1 register  *******************/

+#define EXTI_IMR1_IM_Pos           (0U)

+#define EXTI_IMR1_IM_Msk           (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)          /*!< 0xFFFFFFFF */

+#define EXTI_IMR1_IM               EXTI_IMR1_IM_Msk                            /*!< Interrupt Mask */

+#define EXTI_IMR1_IM0_Pos          (0U)

+#define EXTI_IMR1_IM0_Msk          (0x1UL << EXTI_IMR1_IM0_Pos)                /*!< 0x00000001 */

+#define EXTI_IMR1_IM0              EXTI_IMR1_IM0_Msk                           /*!< Interrupt Mask on line 0 */

+#define EXTI_IMR1_IM1_Pos          (1U)

+#define EXTI_IMR1_IM1_Msk          (0x1UL << EXTI_IMR1_IM1_Pos)                /*!< 0x00000002 */

+#define EXTI_IMR1_IM1              EXTI_IMR1_IM1_Msk                           /*!< Interrupt Mask on line 1 */

+#define EXTI_IMR1_IM2_Pos          (2U)

+#define EXTI_IMR1_IM2_Msk          (0x1UL << EXTI_IMR1_IM2_Pos)                /*!< 0x00000004 */

+#define EXTI_IMR1_IM2              EXTI_IMR1_IM2_Msk                           /*!< Interrupt Mask on line 2 */

+#define EXTI_IMR1_IM3_Pos          (3U)

+#define EXTI_IMR1_IM3_Msk          (0x1UL << EXTI_IMR1_IM3_Pos)                /*!< 0x00000008 */

+#define EXTI_IMR1_IM3              EXTI_IMR1_IM3_Msk                           /*!< Interrupt Mask on line 3 */

+#define EXTI_IMR1_IM4_Pos          (4U)

+#define EXTI_IMR1_IM4_Msk          (0x1UL << EXTI_IMR1_IM4_Pos)                /*!< 0x00000010 */

+#define EXTI_IMR1_IM4              EXTI_IMR1_IM4_Msk                           /*!< Interrupt Mask on line 4 */

+#define EXTI_IMR1_IM5_Pos          (5U)

+#define EXTI_IMR1_IM5_Msk          (0x1UL << EXTI_IMR1_IM5_Pos)                /*!< 0x00000020 */

+#define EXTI_IMR1_IM5              EXTI_IMR1_IM5_Msk                           /*!< Interrupt Mask on line 5 */

+#define EXTI_IMR1_IM6_Pos          (6U)

+#define EXTI_IMR1_IM6_Msk          (0x1UL << EXTI_IMR1_IM6_Pos)                /*!< 0x00000040 */

+#define EXTI_IMR1_IM6              EXTI_IMR1_IM6_Msk                           /*!< Interrupt Mask on line 6 */

+#define EXTI_IMR1_IM7_Pos          (7U)

+#define EXTI_IMR1_IM7_Msk          (0x1UL << EXTI_IMR1_IM7_Pos)                /*!< 0x00000080 */

+#define EXTI_IMR1_IM7              EXTI_IMR1_IM7_Msk                           /*!< Interrupt Mask on line 7 */

+#define EXTI_IMR1_IM8_Pos          (8U)

+#define EXTI_IMR1_IM8_Msk          (0x1UL << EXTI_IMR1_IM8_Pos)                /*!< 0x00000100 */

+#define EXTI_IMR1_IM8              EXTI_IMR1_IM8_Msk                           /*!< Interrupt Mask on line 8 */

+#define EXTI_IMR1_IM9_Pos          (9U)

+#define EXTI_IMR1_IM9_Msk          (0x1UL << EXTI_IMR1_IM9_Pos)                /*!< 0x00000200 */

+#define EXTI_IMR1_IM9              EXTI_IMR1_IM9_Msk                           /*!< Interrupt Mask on line 9 */

+#define EXTI_IMR1_IM10_Pos         (10U)

+#define EXTI_IMR1_IM10_Msk         (0x1UL << EXTI_IMR1_IM10_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR1_IM10             EXTI_IMR1_IM10_Msk                          /*!< Interrupt Mask on line 10 */

+#define EXTI_IMR1_IM11_Pos         (11U)

+#define EXTI_IMR1_IM11_Msk         (0x1UL << EXTI_IMR1_IM11_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR1_IM11             EXTI_IMR1_IM11_Msk                          /*!< Interrupt Mask on line 11 */

+#define EXTI_IMR1_IM12_Pos         (12U)

+#define EXTI_IMR1_IM12_Msk         (0x1UL << EXTI_IMR1_IM12_Pos)               /*!< 0x00001000 */

+#define EXTI_IMR1_IM12             EXTI_IMR1_IM12_Msk                          /*!< Interrupt Mask on line 12 */

+#define EXTI_IMR1_IM13_Pos         (13U)

+#define EXTI_IMR1_IM13_Msk         (0x1UL << EXTI_IMR1_IM13_Pos)               /*!< 0x00002000 */

+#define EXTI_IMR1_IM13             EXTI_IMR1_IM13_Msk                          /*!< Interrupt Mask on line 13 */

+#define EXTI_IMR1_IM14_Pos         (14U)

+#define EXTI_IMR1_IM14_Msk         (0x1UL << EXTI_IMR1_IM14_Pos)               /*!< 0x00004000 */

+#define EXTI_IMR1_IM14             EXTI_IMR1_IM14_Msk                          /*!< Interrupt Mask on line 14 */

+#define EXTI_IMR1_IM15_Pos         (15U)

+#define EXTI_IMR1_IM15_Msk         (0x1UL << EXTI_IMR1_IM15_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR1_IM15             EXTI_IMR1_IM15_Msk                          /*!< Interrupt Mask on line 15 */

+#define EXTI_IMR1_IM16_Pos         (16U)

+#define EXTI_IMR1_IM16_Msk         (0x1UL << EXTI_IMR1_IM16_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR1_IM16             EXTI_IMR1_IM16_Msk                          /*!< Interrupt Mask on line 16 */

+#define EXTI_IMR1_IM17_Pos         (17U)

+#define EXTI_IMR1_IM17_Msk         (0x1UL << EXTI_IMR1_IM17_Pos)               /*!< 0x00020000 */

+#define EXTI_IMR1_IM17             EXTI_IMR1_IM17_Msk                          /*!< Interrupt Mask on line 17 */

+#define EXTI_IMR1_IM18_Pos         (18U)

+#define EXTI_IMR1_IM18_Msk         (0x1UL << EXTI_IMR1_IM18_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR1_IM18             EXTI_IMR1_IM18_Msk                          /*!< Interrupt Mask on line 18 */

+#define EXTI_IMR1_IM19_Pos         (19U)

+#define EXTI_IMR1_IM19_Msk         (0x1UL << EXTI_IMR1_IM19_Pos)               /*!< 0x00080000 */

+#define EXTI_IMR1_IM19             EXTI_IMR1_IM19_Msk                          /*!< Interrupt Mask on line 19 */

+#define EXTI_IMR1_IM20_Pos         (20U)

+#define EXTI_IMR1_IM20_Msk         (0x1UL << EXTI_IMR1_IM20_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR1_IM20             EXTI_IMR1_IM20_Msk                          /*!< Interrupt Mask on line 20 */

+#define EXTI_IMR1_IM21_Pos         (21U)

+#define EXTI_IMR1_IM21_Msk         (0x1UL << EXTI_IMR1_IM21_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR1_IM21             EXTI_IMR1_IM21_Msk                          /*!< Interrupt Mask on line 21 */

+#define EXTI_IMR1_IM22_Pos         (22U)

+#define EXTI_IMR1_IM22_Msk         (0x1UL << EXTI_IMR1_IM22_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR1_IM22             EXTI_IMR1_IM22_Msk                          /*!< Interrupt Mask on line 22 */

+#define EXTI_IMR1_IM23_Pos         (23U)

+#define EXTI_IMR1_IM23_Msk         (0x1UL << EXTI_IMR1_IM23_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR1_IM23             EXTI_IMR1_IM23_Msk                          /*!< Interrupt Mask on line 23 */

+#define EXTI_IMR1_IM24_Pos         (24U)

+#define EXTI_IMR1_IM24_Msk         (0x1UL << EXTI_IMR1_IM24_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR1_IM24             EXTI_IMR1_IM24_Msk                          /*!< Interrupt Mask on line 24 */

+#define EXTI_IMR1_IM25_Pos         (25U)

+#define EXTI_IMR1_IM25_Msk         (0x1UL << EXTI_IMR1_IM25_Pos)               /*!< 0x02000000 */

+#define EXTI_IMR1_IM25             EXTI_IMR1_IM25_Msk                          /*!< Interrupt Mask on line 25 */

+#define EXTI_IMR1_IM26_Pos         (26U)

+#define EXTI_IMR1_IM26_Msk         (0x1UL << EXTI_IMR1_IM26_Pos)               /*!< 0x04000000 */

+#define EXTI_IMR1_IM26             EXTI_IMR1_IM26_Msk                          /*!< Interrupt Mask on line 26 */

+#define EXTI_IMR1_IM27_Pos         (27U)

+#define EXTI_IMR1_IM27_Msk         (0x1UL << EXTI_IMR1_IM27_Pos)               /*!< 0x08000000 */

+#define EXTI_IMR1_IM27             EXTI_IMR1_IM27_Msk                          /*!< Interrupt Mask on line 27 */

+#define EXTI_IMR1_IM28_Pos         (28U)

+#define EXTI_IMR1_IM28_Msk         (0x1UL << EXTI_IMR1_IM28_Pos)               /*!< 0x10000000 */

+#define EXTI_IMR1_IM28             EXTI_IMR1_IM28_Msk                          /*!< Interrupt Mask on line 28 */

+#define EXTI_IMR1_IM29_Pos         (29U)

+#define EXTI_IMR1_IM29_Msk         (0x1UL << EXTI_IMR1_IM29_Pos)               /*!< 0x20000000 */

+#define EXTI_IMR1_IM29             EXTI_IMR1_IM29_Msk                          /*!< Interrupt Mask on line 29 */

+#define EXTI_IMR1_IM30_Pos         (30U)

+#define EXTI_IMR1_IM30_Msk         (0x1UL << EXTI_IMR1_IM30_Pos)               /*!< 0x40000000 */

+#define EXTI_IMR1_IM30             EXTI_IMR1_IM30_Msk                          /*!< Interrupt Mask on line 30 */

+#define EXTI_IMR1_IM31_Pos         (31U)

+#define EXTI_IMR1_IM31_Msk         (0x1UL << EXTI_IMR1_IM31_Pos)               /*!< 0x80000000 */

+#define EXTI_IMR1_IM31             EXTI_IMR1_IM31_Msk                          /*!< Interrupt Mask on line 31 */

+

+/*******************  Bit definition for EXTI_EMR1 register  *******************/

+#define EXTI_EMR1_EM_Pos           (0U)

+#define EXTI_EMR1_EM_Msk           (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)          /*!< 0xFFFFFFFF */

+#define EXTI_EMR1_EM               EXTI_EMR1_EM_Msk                            /*!< Event Mask */

+#define EXTI_EMR1_EM0_Pos          (0U)

+#define EXTI_EMR1_EM0_Msk          (0x1UL << EXTI_EMR1_EM0_Pos)                /*!< 0x00000001 */

+#define EXTI_EMR1_EM0              EXTI_EMR1_EM0_Msk                           /*!< Event Mask on line 0 */

+#define EXTI_EMR1_EM1_Pos          (1U)

+#define EXTI_EMR1_EM1_Msk          (0x1UL << EXTI_EMR1_EM1_Pos)                /*!< 0x00000002 */

+#define EXTI_EMR1_EM1              EXTI_EMR1_EM1_Msk                           /*!< Event Mask on line 1 */

+#define EXTI_EMR1_EM2_Pos          (2U)

+#define EXTI_EMR1_EM2_Msk          (0x1UL << EXTI_EMR1_EM2_Pos)                /*!< 0x00000004 */

+#define EXTI_EMR1_EM2              EXTI_EMR1_EM2_Msk                           /*!< Event Mask on line 2 */

+#define EXTI_EMR1_EM3_Pos          (3U)

+#define EXTI_EMR1_EM3_Msk          (0x1UL << EXTI_EMR1_EM3_Pos)                /*!< 0x00000008 */

+#define EXTI_EMR1_EM3              EXTI_EMR1_EM3_Msk                           /*!< Event Mask on line 3 */

+#define EXTI_EMR1_EM4_Pos          (4U)

+#define EXTI_EMR1_EM4_Msk          (0x1UL << EXTI_EMR1_EM4_Pos)                /*!< 0x00000010 */

+#define EXTI_EMR1_EM4              EXTI_EMR1_EM4_Msk                           /*!< Event Mask on line 4 */

+#define EXTI_EMR1_EM5_Pos          (5U)

+#define EXTI_EMR1_EM5_Msk          (0x1UL << EXTI_EMR1_EM5_Pos)                /*!< 0x00000020 */

+#define EXTI_EMR1_EM5              EXTI_EMR1_EM5_Msk                           /*!< Event Mask on line 5 */

+#define EXTI_EMR1_EM6_Pos          (6U)

+#define EXTI_EMR1_EM6_Msk          (0x1UL << EXTI_EMR1_EM6_Pos)                /*!< 0x00000040 */

+#define EXTI_EMR1_EM6              EXTI_EMR1_EM6_Msk                           /*!< Event Mask on line 6 */

+#define EXTI_EMR1_EM7_Pos          (7U)

+#define EXTI_EMR1_EM7_Msk          (0x1UL << EXTI_EMR1_EM7_Pos)                /*!< 0x00000080 */

+#define EXTI_EMR1_EM7              EXTI_EMR1_EM7_Msk                           /*!< Event Mask on line 7 */

+#define EXTI_EMR1_EM8_Pos          (8U)

+#define EXTI_EMR1_EM8_Msk          (0x1UL << EXTI_EMR1_EM8_Pos)                /*!< 0x00000100 */

+#define EXTI_EMR1_EM8              EXTI_EMR1_EM8_Msk                           /*!< Event Mask on line 8 */

+#define EXTI_EMR1_EM9_Pos          (9U)

+#define EXTI_EMR1_EM9_Msk          (0x1UL << EXTI_EMR1_EM9_Pos)                /*!< 0x00000200 */

+#define EXTI_EMR1_EM9              EXTI_EMR1_EM9_Msk                           /*!< Event Mask on line 9 */

+#define EXTI_EMR1_EM10_Pos         (10U)

+#define EXTI_EMR1_EM10_Msk         (0x1UL << EXTI_EMR1_EM10_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR1_EM10             EXTI_EMR1_EM10_Msk                          /*!< Event Mask on line 10 */

+#define EXTI_EMR1_EM11_Pos         (11U)

+#define EXTI_EMR1_EM11_Msk         (0x1UL << EXTI_EMR1_EM11_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR1_EM11             EXTI_EMR1_EM11_Msk                          /*!< Event Mask on line 11 */

+#define EXTI_EMR1_EM12_Pos         (12U)

+#define EXTI_EMR1_EM12_Msk         (0x1UL << EXTI_EMR1_EM12_Pos)               /*!< 0x00001000 */

+#define EXTI_EMR1_EM12             EXTI_EMR1_EM12_Msk                          /*!< Event Mask on line 12 */

+#define EXTI_EMR1_EM13_Pos         (13U)

+#define EXTI_EMR1_EM13_Msk         (0x1UL << EXTI_EMR1_EM13_Pos)               /*!< 0x00002000 */

+#define EXTI_EMR1_EM13             EXTI_EMR1_EM13_Msk                          /*!< Event Mask on line 13 */

+#define EXTI_EMR1_EM14_Pos         (14U)

+#define EXTI_EMR1_EM14_Msk         (0x1UL << EXTI_EMR1_EM14_Pos)               /*!< 0x00004000 */

+#define EXTI_EMR1_EM14             EXTI_EMR1_EM14_Msk                          /*!< Event Mask on line 14 */

+#define EXTI_EMR1_EM15_Pos         (15U)

+#define EXTI_EMR1_EM15_Msk         (0x1UL << EXTI_EMR1_EM15_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR1_EM15             EXTI_EMR1_EM15_Msk                          /*!< Event Mask on line 15 */

+#define EXTI_EMR1_EM16_Pos         (16U)

+#define EXTI_EMR1_EM16_Msk         (0x1UL << EXTI_EMR1_EM16_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR1_EM16             EXTI_EMR1_EM16_Msk                          /*!< Event Mask on line 16 */

+#define EXTI_EMR1_EM17_Pos         (17U)

+#define EXTI_EMR1_EM17_Msk         (0x1UL << EXTI_EMR1_EM17_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR1_EM17             EXTI_EMR1_EM17_Msk                          /*!< Event Mask on line 17 */

+#define EXTI_EMR1_EM18_Pos         (18U)

+#define EXTI_EMR1_EM18_Msk         (0x1UL << EXTI_EMR1_EM18_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR1_EM18             EXTI_EMR1_EM18_Msk                          /*!< Event Mask on line 18 */

+#define EXTI_EMR1_EM20_Pos         (20U)

+#define EXTI_EMR1_EM20_Msk         (0x1UL << EXTI_EMR1_EM20_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR1_EM20             EXTI_EMR1_EM20_Msk                          /*!< Event Mask on line 20 */

+#define EXTI_EMR1_EM21_Pos         (21U)

+#define EXTI_EMR1_EM21_Msk         (0x1UL << EXTI_EMR1_EM21_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR1_EM21             EXTI_EMR1_EM21_Msk                          /*!< Event Mask on line 21 */

+#define EXTI_EMR1_EM22_Pos         (22U)

+#define EXTI_EMR1_EM22_Msk         (0x1UL << EXTI_EMR1_EM22_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR1_EM22             EXTI_EMR1_EM22_Msk                          /*!< Event Mask on line 22 */

+#define EXTI_EMR1_EM23_Pos         (23U)

+#define EXTI_EMR1_EM23_Msk         (0x1UL << EXTI_EMR1_EM23_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR1_EM23             EXTI_EMR1_EM23_Msk                          /*!< Event Mask on line 23 */

+#define EXTI_EMR1_EM24_Pos         (24U)

+#define EXTI_EMR1_EM24_Msk         (0x1UL << EXTI_EMR1_EM24_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR1_EM24             EXTI_EMR1_EM24_Msk                          /*!< Event Mask on line 24 */

+#define EXTI_EMR1_EM25_Pos         (25U)

+#define EXTI_EMR1_EM25_Msk         (0x1UL << EXTI_EMR1_EM25_Pos)               /*!< 0x02000000 */

+#define EXTI_EMR1_EM25             EXTI_EMR1_EM25_Msk                          /*!< Event Mask on line 25 */

+#define EXTI_EMR1_EM26_Pos         (26U)

+#define EXTI_EMR1_EM26_Msk         (0x1UL << EXTI_EMR1_EM26_Pos)               /*!< 0x04000000 */

+#define EXTI_EMR1_EM26             EXTI_EMR1_EM26_Msk                          /*!< Event Mask on line 26 */

+#define EXTI_EMR1_EM27_Pos         (27U)

+#define EXTI_EMR1_EM27_Msk         (0x1UL << EXTI_EMR1_EM27_Pos)               /*!< 0x08000000 */

+#define EXTI_EMR1_EM27             EXTI_EMR1_EM27_Msk                          /*!< Event Mask on line 27 */

+#define EXTI_EMR1_EM28_Pos         (28U)

+#define EXTI_EMR1_EM28_Msk         (0x1UL << EXTI_EMR1_EM28_Pos)               /*!< 0x10000000 */

+#define EXTI_EMR1_EM28             EXTI_EMR1_EM28_Msk                          /*!< Event Mask on line 28 */

+#define EXTI_EMR1_EM29_Pos         (29U)

+#define EXTI_EMR1_EM29_Msk         (0x1UL << EXTI_EMR1_EM29_Pos)               /*!< 0x20000000 */

+#define EXTI_EMR1_EM29             EXTI_EMR1_EM29_Msk                          /*!< Event Mask on line 29 */

+#define EXTI_EMR1_EM30_Pos         (30U)

+#define EXTI_EMR1_EM30_Msk         (0x1UL << EXTI_EMR1_EM30_Pos)               /*!< 0x40000000 */

+#define EXTI_EMR1_EM30             EXTI_EMR1_EM30_Msk                          /*!< Event Mask on line 30 */

+#define EXTI_EMR1_EM31_Pos         (31U)

+#define EXTI_EMR1_EM31_Msk         (0x1UL << EXTI_EMR1_EM31_Pos)               /*!< 0x80000000 */

+#define EXTI_EMR1_EM31             EXTI_EMR1_EM31_Msk                          /*!< Event Mask on line 31 */

+

+/*******************  Bit definition for EXTI_PR1 register  ********************/

+#define EXTI_PR1_PR_Pos            (0U)

+#define EXTI_PR1_PR_Msk            (0x3FFFFFUL << EXTI_PR1_PR_Pos)             /*!< 0x003FFFFF */

+#define EXTI_PR1_PR                EXTI_PR1_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR1_PR0_Pos           (0U)

+#define EXTI_PR1_PR0_Msk           (0x1UL << EXTI_PR1_PR0_Pos)                 /*!< 0x00000001 */

+#define EXTI_PR1_PR0               EXTI_PR1_PR0_Msk                            /*!< Pending bit for line 0 */

+#define EXTI_PR1_PR1_Pos           (1U)

+#define EXTI_PR1_PR1_Msk           (0x1UL << EXTI_PR1_PR1_Pos)                 /*!< 0x00000002 */

+#define EXTI_PR1_PR1               EXTI_PR1_PR1_Msk                            /*!< Pending bit for line 1 */

+#define EXTI_PR1_PR2_Pos           (2U)

+#define EXTI_PR1_PR2_Msk           (0x1UL << EXTI_PR1_PR2_Pos)                 /*!< 0x00000004 */

+#define EXTI_PR1_PR2               EXTI_PR1_PR2_Msk                            /*!< Pending bit for line 2 */

+#define EXTI_PR1_PR3_Pos           (3U)

+#define EXTI_PR1_PR3_Msk           (0x1UL << EXTI_PR1_PR3_Pos)                 /*!< 0x00000008 */

+#define EXTI_PR1_PR3               EXTI_PR1_PR3_Msk                            /*!< Pending bit for line 3 */

+#define EXTI_PR1_PR4_Pos           (4U)

+#define EXTI_PR1_PR4_Msk           (0x1UL << EXTI_PR1_PR4_Pos)                 /*!< 0x00000010 */

+#define EXTI_PR1_PR4               EXTI_PR1_PR4_Msk                            /*!< Pending bit for line 4 */

+#define EXTI_PR1_PR5_Pos           (5U)

+#define EXTI_PR1_PR5_Msk           (0x1UL << EXTI_PR1_PR5_Pos)                 /*!< 0x00000020 */

+#define EXTI_PR1_PR5               EXTI_PR1_PR5_Msk                            /*!< Pending bit for line 5 */

+#define EXTI_PR1_PR6_Pos           (6U)

+#define EXTI_PR1_PR6_Msk           (0x1UL << EXTI_PR1_PR6_Pos)                 /*!< 0x00000040 */

+#define EXTI_PR1_PR6               EXTI_PR1_PR6_Msk                            /*!< Pending bit for line 6 */

+#define EXTI_PR1_PR7_Pos           (7U)

+#define EXTI_PR1_PR7_Msk           (0x1UL << EXTI_PR1_PR7_Pos)                 /*!< 0x00000080 */

+#define EXTI_PR1_PR7               EXTI_PR1_PR7_Msk                            /*!< Pending bit for line 7 */

+#define EXTI_PR1_PR8_Pos           (8U)

+#define EXTI_PR1_PR8_Msk           (0x1UL << EXTI_PR1_PR8_Pos)                 /*!< 0x00000100 */

+#define EXTI_PR1_PR8               EXTI_PR1_PR8_Msk                            /*!< Pending bit for line 8 */

+#define EXTI_PR1_PR9_Pos           (9U)

+#define EXTI_PR1_PR9_Msk           (0x1UL << EXTI_PR1_PR9_Pos)                 /*!< 0x00000200 */

+#define EXTI_PR1_PR9               EXTI_PR1_PR9_Msk                            /*!< Pending bit for line 9 */

+#define EXTI_PR1_PR10_Pos          (10U)

+#define EXTI_PR1_PR10_Msk          (0x1UL << EXTI_PR1_PR10_Pos)                /*!< 0x00000400 */

+#define EXTI_PR1_PR10              EXTI_PR1_PR10_Msk                           /*!< Pending bit for line 10 */

+#define EXTI_PR1_PR11_Pos          (11U)

+#define EXTI_PR1_PR11_Msk          (0x1UL << EXTI_PR1_PR11_Pos)                /*!< 0x00000800 */

+#define EXTI_PR1_PR11              EXTI_PR1_PR11_Msk                           /*!< Pending bit for line 11 */

+#define EXTI_PR1_PR12_Pos          (12U)

+#define EXTI_PR1_PR12_Msk          (0x1UL << EXTI_PR1_PR12_Pos)                /*!< 0x00001000 */

+#define EXTI_PR1_PR12              EXTI_PR1_PR12_Msk                           /*!< Pending bit for line 12 */

+#define EXTI_PR1_PR13_Pos          (13U)

+#define EXTI_PR1_PR13_Msk          (0x1UL << EXTI_PR1_PR13_Pos)                /*!< 0x00002000 */

+#define EXTI_PR1_PR13              EXTI_PR1_PR13_Msk                           /*!< Pending bit for line 13 */

+#define EXTI_PR1_PR14_Pos          (14U)

+#define EXTI_PR1_PR14_Msk          (0x1UL << EXTI_PR1_PR14_Pos)                /*!< 0x00004000 */

+#define EXTI_PR1_PR14              EXTI_PR1_PR14_Msk                           /*!< Pending bit for line 14 */

+#define EXTI_PR1_PR15_Pos          (15U)

+#define EXTI_PR1_PR15_Msk          (0x1UL << EXTI_PR1_PR15_Pos)                /*!< 0x00008000 */

+#define EXTI_PR1_PR15              EXTI_PR1_PR15_Msk                           /*!< Pending bit for line 15 */

+#define EXTI_PR1_PR16_Pos          (16U)

+#define EXTI_PR1_PR16_Msk          (0x1UL << EXTI_PR1_PR16_Pos)                /*!< 0x00010000 */

+#define EXTI_PR1_PR16              EXTI_PR1_PR16_Msk                           /*!< Pending bit for line 16 */

+#define EXTI_PR1_PR17_Pos          (17U)

+#define EXTI_PR1_PR17_Msk          (0x1UL << EXTI_PR1_PR17_Pos)                /*!< 0x00020000 */

+#define EXTI_PR1_PR17              EXTI_PR1_PR17_Msk                           /*!< Pending bit for line 17 */

+#define EXTI_PR1_PR18_Pos          (18U)

+#define EXTI_PR1_PR18_Msk          (0x1UL << EXTI_PR1_PR18_Pos)                /*!< 0x00040000 */

+#define EXTI_PR1_PR18              EXTI_PR1_PR18_Msk                           /*!< Pending bit for line 18 */

+#define EXTI_PR1_PR19_Pos          (19U)

+#define EXTI_PR1_PR19_Msk          (0x1UL << EXTI_PR1_PR19_Pos)                /*!< 0x00080000 */

+#define EXTI_PR1_PR19              EXTI_PR1_PR19_Msk                           /*!< Pending bit for line 19 */

+#define EXTI_PR1_PR20_Pos          (20U)

+#define EXTI_PR1_PR20_Msk          (0x1UL << EXTI_PR1_PR20_Pos)                /*!< 0x00100000 */

+#define EXTI_PR1_PR20              EXTI_PR1_PR20_Msk                           /*!< Pending bit for line 20 */

+#define EXTI_PR1_PR21_Pos          (21U)

+#define EXTI_PR1_PR21_Msk          (0x1UL << EXTI_PR1_PR21_Pos)                /*!< 0x00200000 */

+#define EXTI_PR1_PR21              EXTI_PR1_PR21_Msk                           /*!< Pending bit for line 21 */

+

+/*******************  Bit definition for EXTI_IMR2 register  *******************/

+#define EXTI_IMR2_IM_Pos           (0U)

+#define EXTI_IMR2_IM_Msk           (0xFFFFDFFFUL << EXTI_IMR2_IM_Pos)          /*!< 0xFFFFDFFF */

+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            /*!< Interrupt Mask */

+#define EXTI_IMR2_IM32_Pos         (0U)

+#define EXTI_IMR2_IM32_Msk         (0x1UL << EXTI_IMR2_IM32_Pos)               /*!< 0x00000001 */

+#define EXTI_IMR2_IM32             EXTI_IMR2_IM32_Msk                          /*!< Interrupt Mask on line 32 */

+#define EXTI_IMR2_IM33_Pos         (1U)

+#define EXTI_IMR2_IM33_Msk         (0x1UL << EXTI_IMR2_IM33_Pos)               /*!< 0x00000002 */

+#define EXTI_IMR2_IM33             EXTI_IMR2_IM33_Msk                          /*!< Interrupt Mask on line 33 */

+#define EXTI_IMR2_IM34_Pos         (2U)

+#define EXTI_IMR2_IM34_Msk         (0x1UL << EXTI_IMR2_IM34_Pos)               /*!< 0x00000004 */

+#define EXTI_IMR2_IM34             EXTI_IMR2_IM34_Msk                          /*!< Interrupt Mask on line 34 */

+#define EXTI_IMR2_IM35_Pos         (3U)

+#define EXTI_IMR2_IM35_Msk         (0x1UL << EXTI_IMR2_IM35_Pos)               /*!< 0x00000008 */

+#define EXTI_IMR2_IM35             EXTI_IMR2_IM35_Msk                          /*!< Interrupt Mask on line 35 */

+#define EXTI_IMR2_IM36_Pos         (4U)

+#define EXTI_IMR2_IM36_Msk         (0x1UL << EXTI_IMR2_IM36_Pos)               /*!< 0x00000010 */

+#define EXTI_IMR2_IM36             EXTI_IMR2_IM36_Msk                          /*!< Interrupt Mask on line 36 */

+#define EXTI_IMR2_IM37_Pos         (5U)

+#define EXTI_IMR2_IM37_Msk         (0x1UL << EXTI_IMR2_IM37_Pos)               /*!< 0x00000020 */

+#define EXTI_IMR2_IM37             EXTI_IMR2_IM37_Msk                          /*!< Interrupt Mask on line 37 */

+#define EXTI_IMR2_IM38_Pos         (6U)

+#define EXTI_IMR2_IM38_Msk         (0x1UL << EXTI_IMR2_IM38_Pos)               /*!< 0x00000040 */

+#define EXTI_IMR2_IM38             EXTI_IMR2_IM38_Msk                          /*!< Interrupt Mask on line 38 */

+#define EXTI_IMR2_IM39_Pos         (7U)

+#define EXTI_IMR2_IM39_Msk         (0x1UL << EXTI_IMR2_IM39_Pos)               /*!< 0x00000080 */

+#define EXTI_IMR2_IM39             EXTI_IMR2_IM39_Msk                          /*!< Interrupt Mask on line 39 */

+#define EXTI_IMR2_IM40_Pos         (8U)

+#define EXTI_IMR2_IM40_Msk         (0x1UL << EXTI_IMR2_IM40_Pos)               /*!< 0x00000100 */

+#define EXTI_IMR2_IM40             EXTI_IMR2_IM40_Msk                          /*!< Interrupt Mask on line 40 */

+#define EXTI_IMR2_IM41_Pos         (9U)

+#define EXTI_IMR2_IM41_Msk         (0x1UL << EXTI_IMR2_IM41_Pos)               /*!< 0x00000200 */

+#define EXTI_IMR2_IM41             EXTI_IMR2_IM41_Msk                          /*!< Interrupt Mask on line 41 */

+#define EXTI_IMR2_IM42_Pos         (10U)

+#define EXTI_IMR2_IM42_Msk         (0x1UL << EXTI_IMR2_IM42_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR2_IM42             EXTI_IMR2_IM42_Msk                          /*!< Interrupt Mask on line 42 */

+#define EXTI_IMR2_IM43_Pos         (11U)

+#define EXTI_IMR2_IM43_Msk         (0x1UL << EXTI_IMR2_IM43_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR2_IM43             EXTI_IMR2_IM43_Msk                          /*!< Interrupt Mask on line 43 */

+#define EXTI_IMR2_IM44_Pos         (12U)

+#define EXTI_IMR2_IM44_Msk         (0x1UL << EXTI_IMR2_IM44_Pos)               /*!< 0x00001000 */

+#define EXTI_IMR2_IM44             EXTI_IMR2_IM44_Msk                          /*!< Interrupt Mask on line 44 */

+#define EXTI_IMR2_IM46_Pos         (14U)

+#define EXTI_IMR2_IM46_Msk         (0x1UL << EXTI_IMR2_IM46_Pos)               /*!< 0x00004000 */

+#define EXTI_IMR2_IM46             EXTI_IMR2_IM46_Msk                          /*!< Interrupt Mask on line 46 */

+#define EXTI_IMR2_IM47_Pos         (15U)

+#define EXTI_IMR2_IM47_Msk         (0x1UL << EXTI_IMR2_IM47_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR2_IM47             EXTI_IMR2_IM47_Msk                          /*!< Interrupt Mask on line 47 */

+#define EXTI_IMR2_IM48_Pos         (16U)

+#define EXTI_IMR2_IM48_Msk         (0x1UL << EXTI_IMR2_IM48_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR2_IM48             EXTI_IMR2_IM48_Msk                          /*!< Interrupt Mask on line 48 */

+#define EXTI_IMR2_IM49_Pos         (17U)

+#define EXTI_IMR2_IM49_Msk         (0x1UL << EXTI_IMR2_IM49_Pos)               /*!< 0x00020000 */

+#define EXTI_IMR2_IM49             EXTI_IMR2_IM49_Msk                          /*!< Interrupt Mask on line 49 */

+#define EXTI_IMR2_IM50_Pos         (18U)

+#define EXTI_IMR2_IM50_Msk         (0x1UL << EXTI_IMR2_IM50_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR2_IM50             EXTI_IMR2_IM50_Msk                          /*!< Interrupt Mask on line 50 */

+#define EXTI_IMR2_IM51_Pos         (19U)

+#define EXTI_IMR2_IM51_Msk         (0x1UL << EXTI_IMR2_IM51_Pos)               /*!< 0x00080000 */

+#define EXTI_IMR2_IM51             EXTI_IMR2_IM51_Msk                          /*!< Interrupt Mask on line 51 */

+#define EXTI_IMR2_IM52_Pos         (20U)

+#define EXTI_IMR2_IM52_Msk         (0x1UL << EXTI_IMR2_IM52_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR2_IM52             EXTI_IMR2_IM52_Msk                          /*!< Interrupt Mask on line 52 */

+#define EXTI_IMR2_IM53_Pos         (21U)

+#define EXTI_IMR2_IM53_Msk         (0x1UL << EXTI_IMR2_IM53_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR2_IM53             EXTI_IMR2_IM53_Msk                          /*!< Interrupt Mask on line 53 */

+#define EXTI_IMR2_IM54_Pos         (22U)

+#define EXTI_IMR2_IM54_Msk         (0x1UL << EXTI_IMR2_IM54_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR2_IM54             EXTI_IMR2_IM54_Msk                          /*!< Interrupt Mask on line 54 */

+#define EXTI_IMR2_IM55_Pos         (23U)

+#define EXTI_IMR2_IM55_Msk         (0x1UL << EXTI_IMR2_IM55_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR2_IM55             EXTI_IMR2_IM55_Msk                          /*!< Interrupt Mask on line 55 */

+#define EXTI_IMR2_IM56_Pos         (24U)

+#define EXTI_IMR2_IM56_Msk         (0x1UL << EXTI_IMR2_IM56_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR2_IM56             EXTI_IMR2_IM56_Msk                          /*!< Interrupt Mask on line 56 */

+#define EXTI_IMR2_IM57_Pos         (25U)

+#define EXTI_IMR2_IM57_Msk         (0x1UL << EXTI_IMR2_IM57_Pos)               /*!< 0x02000000 */

+#define EXTI_IMR2_IM57             EXTI_IMR2_IM57_Msk                          /*!< Interrupt Mask on line 57 */

+#define EXTI_IMR2_IM58_Pos         (26U)

+#define EXTI_IMR2_IM58_Msk         (0x1UL << EXTI_IMR2_IM58_Pos)               /*!< 0x04000000 */

+#define EXTI_IMR2_IM58             EXTI_IMR2_IM58_Msk                          /*!< Interrupt Mask on line 58 */

+#define EXTI_IMR2_IM59_Pos         (27U)

+#define EXTI_IMR2_IM59_Msk         (0x1UL << EXTI_IMR2_IM59_Pos)               /*!< 0x08000000 */

+#define EXTI_IMR2_IM59             EXTI_IMR2_IM59_Msk                          /*!< Interrupt Mask on line 59 */

+#define EXTI_IMR2_IM60_Pos         (28U)

+#define EXTI_IMR2_IM60_Msk         (0x1UL << EXTI_IMR2_IM60_Pos)               /*!< 0x10000000 */

+#define EXTI_IMR2_IM60             EXTI_IMR2_IM60_Msk                          /*!< Interrupt Mask on line 60 */

+#define EXTI_IMR2_IM61_Pos         (29U)

+#define EXTI_IMR2_IM61_Msk         (0x1UL << EXTI_IMR2_IM61_Pos)               /*!< 0x20000000 */

+#define EXTI_IMR2_IM61             EXTI_IMR2_IM61_Msk                          /*!< Interrupt Mask on line 61 */

+#define EXTI_IMR2_IM62_Pos         (30U)

+#define EXTI_IMR2_IM62_Msk         (0x1UL << EXTI_IMR2_IM62_Pos)               /*!< 0x40000000 */

+#define EXTI_IMR2_IM62             EXTI_IMR2_IM62_Msk                          /*!< Interrupt Mask on line 62 */

+#define EXTI_IMR2_IM63_Pos         (31U)

+#define EXTI_IMR2_IM63_Msk         (0x1UL << EXTI_IMR2_IM63_Pos)               /*!< 0x80000000 */

+#define EXTI_IMR2_IM63             EXTI_IMR2_IM63_Msk                          /*!< Interrupt Mask on line 63 */

+

+/*******************  Bit definition for EXTI_EMR2 register  *******************/

+#define EXTI_EMR2_EM_Pos           (0U)

+#define EXTI_EMR2_EM_Msk           (0xFFFFDFFFUL << EXTI_EMR2_EM_Pos)          /*!< 0xFFFFDFFF */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            /*!< Event Mask */

+#define EXTI_EMR2_EM32_Pos         (0U)

+#define EXTI_EMR2_EM32_Msk         (0x1UL << EXTI_EMR2_EM32_Pos)               /*!< 0x00000001 */

+#define EXTI_EMR2_EM32             EXTI_EMR2_EM32_Msk                          /*!< Event Mask on line 32*/

+#define EXTI_EMR2_EM33_Pos         (1U)

+#define EXTI_EMR2_EM33_Msk         (0x1UL << EXTI_EMR2_EM33_Pos)               /*!< 0x00000002 */

+#define EXTI_EMR2_EM33             EXTI_EMR2_EM33_Msk                          /*!< Event Mask on line 33*/

+#define EXTI_EMR2_EM34_Pos         (2U)

+#define EXTI_EMR2_EM34_Msk         (0x1UL << EXTI_EMR2_EM34_Pos)               /*!< 0x00000004 */

+#define EXTI_EMR2_EM34             EXTI_EMR2_EM34_Msk                          /*!< Event Mask on line 34*/

+#define EXTI_EMR2_EM35_Pos         (3U)

+#define EXTI_EMR2_EM35_Msk         (0x1UL << EXTI_EMR2_EM35_Pos)               /*!< 0x00000008 */

+#define EXTI_EMR2_EM35             EXTI_EMR2_EM35_Msk                          /*!< Event Mask on line 35*/

+#define EXTI_EMR2_EM36_Pos         (4U)

+#define EXTI_EMR2_EM36_Msk         (0x1UL << EXTI_EMR2_EM36_Pos)               /*!< 0x00000010 */

+#define EXTI_EMR2_EM36             EXTI_EMR2_EM36_Msk                          /*!< Event Mask on line 36*/

+#define EXTI_EMR2_EM37_Pos         (5U)

+#define EXTI_EMR2_EM37_Msk         (0x1UL << EXTI_EMR2_EM37_Pos)               /*!< 0x00000020 */

+#define EXTI_EMR2_EM37             EXTI_EMR2_EM37_Msk                          /*!< Event Mask on line 37*/

+#define EXTI_EMR2_EM38_Pos         (6U)

+#define EXTI_EMR2_EM38_Msk         (0x1UL << EXTI_EMR2_EM38_Pos)               /*!< 0x00000040 */

+#define EXTI_EMR2_EM38             EXTI_EMR2_EM38_Msk                          /*!< Event Mask on line 38*/

+#define EXTI_EMR2_EM39_Pos         (7U)

+#define EXTI_EMR2_EM39_Msk         (0x1UL << EXTI_EMR2_EM39_Pos)               /*!< 0x00000080 */

+#define EXTI_EMR2_EM39             EXTI_EMR2_EM39_Msk                          /*!< Event Mask on line 39*/

+#define EXTI_EMR2_EM40_Pos         (8U)

+#define EXTI_EMR2_EM40_Msk         (0x1UL << EXTI_EMR2_EM40_Pos)               /*!< 0x00000100 */

+#define EXTI_EMR2_EM40             EXTI_EMR2_EM40_Msk                          /*!< Event Mask on line 40*/

+#define EXTI_EMR2_EM41_Pos         (9U)

+#define EXTI_EMR2_EM41_Msk         (0x1UL << EXTI_EMR2_EM41_Pos)               /*!< 0x00000200 */

+#define EXTI_EMR2_EM41             EXTI_EMR2_EM41_Msk                          /*!< Event Mask on line 41*/

+#define EXTI_EMR2_EM42_Pos         (10U)

+#define EXTI_EMR2_EM42_Msk         (0x1UL << EXTI_EMR2_EM42_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR2_EM42             EXTI_EMR2_EM42_Msk                          /*!< Event Mask on line 42 */

+#define EXTI_EMR2_EM43_Pos         (11U)

+#define EXTI_EMR2_EM43_Msk         (0x1UL << EXTI_EMR2_EM43_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR2_EM43             EXTI_EMR2_EM43_Msk                          /*!< Event Mask on line 43 */

+#define EXTI_EMR2_EM44_Pos         (12U)

+#define EXTI_EMR2_EM44_Msk         (0x1UL << EXTI_EMR2_EM44_Pos)               /*!< 0x00001000 */

+#define EXTI_EMR2_EM44             EXTI_EMR2_EM44_Msk                          /*!< Event Mask on line 44 */

+#define EXTI_EMR2_EM46_Pos         (14U)

+#define EXTI_EMR2_EM46_Msk         (0x1UL << EXTI_EMR2_EM46_Pos)               /*!< 0x00004000 */

+#define EXTI_EMR2_EM46             EXTI_EMR2_EM46_Msk                          /*!< Event Mask on line 46 */

+#define EXTI_EMR2_EM47_Pos         (15U)

+#define EXTI_EMR2_EM47_Msk         (0x1UL << EXTI_EMR2_EM47_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR2_EM47             EXTI_EMR2_EM47_Msk                          /*!< Event Mask on line 47 */

+#define EXTI_EMR2_EM48_Pos         (16U)

+#define EXTI_EMR2_EM48_Msk         (0x1UL << EXTI_EMR2_EM48_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR2_EM48             EXTI_EMR2_EM48_Msk                          /*!< Event Mask on line 48 */

+#define EXTI_EMR2_EM49_Pos         (17U)

+#define EXTI_EMR2_EM49_Msk         (0x1UL << EXTI_EMR2_EM49_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR2_EM49             EXTI_EMR2_EM49_Msk                          /*!< Event Mask on line 49 */

+#define EXTI_EMR2_EM50_Pos         (18U)

+#define EXTI_EMR2_EM50_Msk         (0x1UL << EXTI_EMR2_EM50_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR2_EM50             EXTI_EMR2_EM50_Msk                          /*!< Event Mask on line 50 */

+#define EXTI_EMR2_EM51_Pos         (19U)

+#define EXTI_EMR2_EM51_Msk         (0x1UL << EXTI_EMR2_EM51_Pos)               /*!< 0x00080000 */

+#define EXTI_EMR2_EM51             EXTI_EMR2_EM51_Msk                          /*!< Event Mask on line 51 */

+#define EXTI_EMR2_EM52_Pos         (20U)

+#define EXTI_EMR2_EM52_Msk         (0x1UL << EXTI_EMR2_EM52_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR2_EM52             EXTI_EMR2_EM52_Msk                          /*!< Event Mask on line 52 */

+#define EXTI_EMR2_EM53_Pos         (21U)

+#define EXTI_EMR2_EM53_Msk         (0x1UL << EXTI_EMR2_EM53_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR2_EM53             EXTI_EMR2_EM53_Msk                          /*!< Event Mask on line 53 */

+#define EXTI_EMR2_EM54_Pos         (22U)

+#define EXTI_EMR2_EM54_Msk         (0x1UL << EXTI_EMR2_EM54_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR2_EM54             EXTI_EMR2_EM54_Msk                          /*!< Event Mask on line 54 */

+#define EXTI_EMR2_EM55_Pos         (23U)

+#define EXTI_EMR2_EM55_Msk         (0x1UL << EXTI_EMR2_EM55_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR2_EM55             EXTI_EMR2_EM55_Msk                          /*!< Event Mask on line 55 */

+#define EXTI_EMR2_EM56_Pos         (24U)

+#define EXTI_EMR2_EM56_Msk         (0x1UL << EXTI_EMR2_EM56_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR2_EM56             EXTI_EMR2_EM56_Msk                          /*!< Event Mask on line 56 */

+#define EXTI_EMR2_EM57_Pos         (25U)

+#define EXTI_EMR2_EM57_Msk         (0x1UL << EXTI_EMR2_EM57_Pos)               /*!< 0x02000000 */

+#define EXTI_EMR2_EM57             EXTI_EMR2_EM57_Msk                          /*!< Event Mask on line 57 */

+#define EXTI_EMR2_EM58_Pos         (26U)

+#define EXTI_EMR2_EM58_Msk         (0x1UL << EXTI_EMR2_EM58_Pos)               /*!< 0x04000000 */

+#define EXTI_EMR2_EM58             EXTI_EMR2_EM58_Msk                          /*!< Event Mask on line 58 */

+#define EXTI_EMR2_EM59_Pos         (27U)

+#define EXTI_EMR2_EM59_Msk         (0x1UL << EXTI_EMR2_EM59_Pos)               /*!< 0x08000000 */

+#define EXTI_EMR2_EM59             EXTI_EMR2_EM59_Msk                          /*!< Event Mask on line 59 */

+#define EXTI_EMR2_EM60_Pos         (28U)

+#define EXTI_EMR2_EM60_Msk         (0x1UL << EXTI_EMR2_EM60_Pos)               /*!< 0x10000000 */

+#define EXTI_EMR2_EM60             EXTI_EMR2_EM60_Msk                          /*!< Event Mask on line 60 */

+#define EXTI_EMR2_EM61_Pos         (29U)

+#define EXTI_EMR2_EM61_Msk         (0x1UL << EXTI_EMR2_EM61_Pos)               /*!< 0x20000000 */

+#define EXTI_EMR2_EM61             EXTI_EMR2_EM61_Msk                          /*!< Event Mask on line 61 */

+#define EXTI_EMR2_EM62_Pos         (30U)

+#define EXTI_EMR2_EM62_Msk         (0x1UL << EXTI_EMR2_EM62_Pos)               /*!< 0x40000000 */

+#define EXTI_EMR2_EM62             EXTI_EMR2_EM62_Msk                          /*!< Event Mask on line 62 */

+#define EXTI_EMR2_EM63_Pos         (31U)

+#define EXTI_EMR2_EM63_Msk         (0x1UL << EXTI_EMR2_EM63_Pos)               /*!< 0x80000000 */

+#define EXTI_EMR2_EM63             EXTI_EMR2_EM63_Msk                          /*!< Event Mask on line 63 */

+

+/*******************  Bit definition for EXTI_PR2 register  ********************/

+#define EXTI_PR2_PR_Pos            (17U)

+#define EXTI_PR2_PR_Msk            (0x5UL << EXTI_PR2_PR_Pos)                  /*!< 0x000A0000 */

+#define EXTI_PR2_PR                EXTI_PR2_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR2_PR49_Pos          (17U)

+#define EXTI_PR2_PR49_Msk          (0x1UL << EXTI_PR2_PR49_Pos)                /*!< 0x00020000 */

+#define EXTI_PR2_PR49              EXTI_PR2_PR49_Msk                           /*!< Pending bit for line 49 */

+#define EXTI_PR2_PR51_Pos          (19U)

+#define EXTI_PR2_PR51_Msk          (0x1UL << EXTI_PR2_PR51_Pos)                /*!< 0x00080000 */

+#define EXTI_PR2_PR51              EXTI_PR2_PR51_Msk                           /*!< Pending bit for line 51 */

+

+/*******************  Bit definition for EXTI_IMR3 register  *******************/

+#define EXTI_IMR3_IM_Pos           (0U)

+#define EXTI_IMR3_IM_Msk           (0x00F5FFFFUL << EXTI_IMR3_IM_Pos)          /*!< 0x00F5FFFF */

+#define EXTI_IMR3_IM               EXTI_IMR3_IM_Msk                            /*!< Interrupt Mask */

+#define EXTI_IMR3_IM64_Pos         (0U)

+#define EXTI_IMR3_IM64_Msk         (0x1UL << EXTI_IMR3_IM64_Pos)               /*!< 0x00000001 */

+#define EXTI_IMR3_IM64             EXTI_IMR3_IM64_Msk                          /*!< Interrupt Mask on line 64 */

+#define EXTI_IMR3_IM65_Pos         (1U)

+#define EXTI_IMR3_IM65_Msk         (0x1UL << EXTI_IMR3_IM65_Pos)               /*!< 0x00000002 */

+#define EXTI_IMR3_IM65             EXTI_IMR3_IM65_Msk                          /*!< Interrupt Mask on line 65 */

+#define EXTI_IMR3_IM66_Pos         (2U)

+#define EXTI_IMR3_IM66_Msk         (0x1UL << EXTI_IMR3_IM66_Pos)               /*!< 0x00000004 */

+#define EXTI_IMR3_IM66             EXTI_IMR3_IM66_Msk                          /*!< Interrupt Mask on line 66 */

+#define EXTI_IMR3_IM67_Pos         (3U)

+#define EXTI_IMR3_IM67_Msk         (0x1UL << EXTI_IMR3_IM67_Pos)               /*!< 0x00000008 */

+#define EXTI_IMR3_IM67             EXTI_IMR3_IM67_Msk                          /*!< Interrupt Mask on line 67 */

+#define EXTI_IMR3_IM68_Pos         (4U)

+#define EXTI_IMR3_IM68_Msk         (0x1UL << EXTI_IMR3_IM68_Pos)               /*!< 0x00000010 */

+#define EXTI_IMR3_IM68             EXTI_IMR3_IM68_Msk                          /*!< Interrupt Mask on line 68 */

+#define EXTI_IMR3_IM69_Pos         (5U)

+#define EXTI_IMR3_IM69_Msk         (0x1UL << EXTI_IMR3_IM69_Pos)               /*!< 0x00000020 */

+#define EXTI_IMR3_IM69             EXTI_IMR3_IM69_Msk                          /*!< Interrupt Mask on line 69 */

+#define EXTI_IMR3_IM70_Pos         (6U)

+#define EXTI_IMR3_IM70_Msk         (0x1UL << EXTI_IMR3_IM70_Pos)               /*!< 0x00000040 */

+#define EXTI_IMR3_IM70             EXTI_IMR3_IM70_Msk                          /*!< Interrupt Mask on line 70 */

+#define EXTI_IMR3_IM71_Pos         (7U)

+#define EXTI_IMR3_IM71_Msk         (0x1UL << EXTI_IMR3_IM71_Pos)               /*!< 0x00000080 */

+#define EXTI_IMR3_IM71             EXTI_IMR3_IM71_Msk                          /*!< Interrupt Mask on line 71 */

+#define EXTI_IMR3_IM72_Pos         (8U)

+#define EXTI_IMR3_IM72_Msk         (0x1UL << EXTI_IMR3_IM72_Pos)               /*!< 0x00000100 */

+#define EXTI_IMR3_IM72             EXTI_IMR3_IM72_Msk                          /*!< Interrupt Mask on line 72 */

+#define EXTI_IMR3_IM73_Pos         (9U)

+#define EXTI_IMR3_IM73_Msk         (0x1UL << EXTI_IMR3_IM73_Pos)               /*!< 0x00000200 */

+#define EXTI_IMR3_IM73             EXTI_IMR3_IM73_Msk                          /*!< Interrupt Mask on line 73 */

+#define EXTI_IMR3_IM74_Pos         (10U)

+#define EXTI_IMR3_IM74_Msk         (0x1UL << EXTI_IMR3_IM74_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR3_IM74             EXTI_IMR3_IM74_Msk                          /*!< Interrupt Mask on line 74 */

+#define EXTI_IMR3_IM75_Pos         (11U)

+#define EXTI_IMR3_IM75_Msk         (0x1UL << EXTI_IMR3_IM75_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR3_IM75             EXTI_IMR3_IM75_Msk                          /*!< Interrupt Mask on line 75 */

+#define EXTI_IMR3_IM76_Pos         (12U)

+#define EXTI_IMR3_IM76_Msk         (0x1UL << EXTI_IMR3_IM76_Pos)               /*!< 0x00001000 */

+#define EXTI_IMR3_IM76             EXTI_IMR3_IM76_Msk                          /*!< Interrupt Mask on line 76 */

+#define EXTI_IMR3_IM77_Pos         (13U)

+#define EXTI_IMR3_IM77_Msk         (0x1UL << EXTI_IMR3_IM77_Pos)               /*!< 0x00002000 */

+#define EXTI_IMR3_IM77             EXTI_IMR3_IM77_Msk                          /*!< Interrupt Mask on line 77 */

+#define EXTI_IMR3_IM78_Pos         (14U)

+#define EXTI_IMR3_IM78_Msk         (0x1UL << EXTI_IMR3_IM78_Pos)               /*!< 0x00004000 */

+#define EXTI_IMR3_IM78             EXTI_IMR3_IM78_Msk                          /*!< Interrupt Mask on line 78 */

+#define EXTI_IMR3_IM79_Pos         (15U)

+#define EXTI_IMR3_IM79_Msk         (0x1UL << EXTI_IMR3_IM79_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR3_IM79             EXTI_IMR3_IM79_Msk                          /*!< Interrupt Mask on line 79 */

+#define EXTI_IMR3_IM80_Pos         (16U)

+#define EXTI_IMR3_IM80_Msk         (0x1UL << EXTI_IMR3_IM80_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR3_IM80             EXTI_IMR3_IM80_Msk                          /*!< Interrupt Mask on line 80 */

+#define EXTI_IMR3_IM82_Pos         (18U)

+#define EXTI_IMR3_IM82_Msk         (0x1UL << EXTI_IMR3_IM82_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR3_IM82             EXTI_IMR3_IM82_Msk                          /*!< Interrupt Mask on line 82 */

+#define EXTI_IMR3_IM84_Pos         (20U)

+#define EXTI_IMR3_IM84_Msk         (0x1UL << EXTI_IMR3_IM84_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR3_IM84             EXTI_IMR3_IM84_Msk                          /*!< Interrupt Mask on line 84 */

+#define EXTI_IMR3_IM85_Pos         (21U)

+#define EXTI_IMR3_IM85_Msk         (0x1UL << EXTI_IMR3_IM85_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR3_IM85             EXTI_IMR3_IM85_Msk                          /*!< Interrupt Mask on line 85 */

+#define EXTI_IMR3_IM86_Pos         (22U)

+#define EXTI_IMR3_IM86_Msk         (0x1UL << EXTI_IMR3_IM86_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR3_IM86             EXTI_IMR3_IM86_Msk                          /*!< Interrupt Mask on line 86 */

+#define EXTI_IMR3_IM87_Pos         (23U)

+#define EXTI_IMR3_IM87_Msk         (0x1UL << EXTI_IMR3_IM87_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR3_IM87             EXTI_IMR3_IM87_Msk                          /*!< Interrupt Mask on line 87 */

+

+

+/*******************  Bit definition for EXTI_EMR3 register  *******************/

+#define EXTI_EMR3_EM_Pos           (0U)

+#define EXTI_EMR3_EM_Msk           (0x00F5FFFFUL << EXTI_EMR3_EM_Pos)          /*!< 0x00F5FFFF */

+#define EXTI_EMR3_EM               EXTI_EMR3_EM_Msk                            /*!< Event Mask           */

+#define EXTI_EMR3_EM64_Pos         (0U)

+#define EXTI_EMR3_EM64_Msk         (0x1UL << EXTI_EMR3_EM64_Pos)               /*!< 0x00000001 */

+#define EXTI_EMR3_EM64             EXTI_EMR3_EM64_Msk                          /*!< Event Mask on line 64*/

+#define EXTI_EMR3_EM65_Pos         (1U)

+#define EXTI_EMR3_EM65_Msk         (0x1UL << EXTI_EMR3_EM65_Pos)               /*!< 0x00000002 */

+#define EXTI_EMR3_EM65             EXTI_EMR3_EM65_Msk                          /*!< Event Mask on line 65*/

+#define EXTI_EMR3_EM66_Pos         (2U)

+#define EXTI_EMR3_EM66_Msk         (0x1UL << EXTI_EMR3_EM66_Pos)               /*!< 0x00000004 */

+#define EXTI_EMR3_EM66             EXTI_EMR3_EM66_Msk                          /*!< Event Mask on line 66*/

+#define EXTI_EMR3_EM67_Pos         (3U)

+#define EXTI_EMR3_EM67_Msk         (0x1UL << EXTI_EMR3_EM67_Pos)               /*!< 0x00000008 */

+#define EXTI_EMR3_EM67             EXTI_EMR3_EM67_Msk                          /*!< Event Mask on line 67*/

+#define EXTI_EMR3_EM68_Pos         (4U)

+#define EXTI_EMR3_EM68_Msk         (0x1UL << EXTI_EMR3_EM68_Pos)               /*!< 0x00000010 */

+#define EXTI_EMR3_EM68             EXTI_EMR3_EM68_Msk                          /*!< Event Mask on line 68*/

+#define EXTI_EMR3_EM69_Pos         (5U)

+#define EXTI_EMR3_EM69_Msk         (0x1UL << EXTI_EMR3_EM69_Pos)               /*!< 0x00000020 */

+#define EXTI_EMR3_EM69             EXTI_EMR3_EM69_Msk                          /*!< Event Mask on line 69*/

+#define EXTI_EMR3_EM70_Pos         (6U)

+#define EXTI_EMR3_EM70_Msk         (0x1UL << EXTI_EMR3_EM70_Pos)               /*!< 0x00000040 */

+#define EXTI_EMR3_EM70             EXTI_EMR3_EM70_Msk                          /*!< Event Mask on line 70*/

+#define EXTI_EMR3_EM71_Pos         (7U)

+#define EXTI_EMR3_EM71_Msk         (0x1UL << EXTI_EMR3_EM71_Pos)               /*!< 0x00000080 */

+#define EXTI_EMR3_EM71             EXTI_EMR3_EM71_Msk                          /*!< Event Mask on line 71*/

+#define EXTI_EMR3_EM72_Pos         (8U)

+#define EXTI_EMR3_EM72_Msk         (0x1UL << EXTI_EMR3_EM72_Pos)               /*!< 0x00000100 */

+#define EXTI_EMR3_EM72             EXTI_EMR3_EM72_Msk                          /*!< Event Mask on line 72*/

+#define EXTI_EMR3_EM73_Pos         (9U)

+#define EXTI_EMR3_EM73_Msk         (0x1UL << EXTI_EMR3_EM73_Pos)               /*!< 0x00000200 */

+#define EXTI_EMR3_EM73             EXTI_EMR3_EM73_Msk                          /*!< Event Mask on line 73*/

+#define EXTI_EMR3_EM74_Pos         (10U)

+#define EXTI_EMR3_EM74_Msk         (0x1UL << EXTI_EMR3_EM74_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR3_EM74             EXTI_EMR3_EM74_Msk                          /*!< Event Mask on line 74 */

+#define EXTI_EMR3_EM75_Pos         (11U)

+#define EXTI_EMR3_EM75_Msk         (0x1UL << EXTI_EMR3_EM75_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR3_EM75             EXTI_EMR3_EM75_Msk                          /*!< Event Mask on line 75 */

+#define EXTI_EMR3_EM76_Pos         (12U)

+#define EXTI_EMR3_EM76_Msk         (0x1UL << EXTI_EMR3_EM76_Pos)               /*!< 0x00001000 */

+#define EXTI_EMR3_EM76             EXTI_EMR3_EM76_Msk                          /*!< Event Mask on line 76 */

+#define EXTI_EMR3_EM77_Pos         (13U)

+#define EXTI_EMR3_EM77_Msk         (0x1UL << EXTI_EMR3_EM77_Pos)               /*!< 0x00002000 */

+#define EXTI_EMR3_EM77             EXTI_EMR3_EM77_Msk                          /*!< Event Mask on line 77 */

+#define EXTI_EMR3_EM78_Pos         (14U)

+#define EXTI_EMR3_EM78_Msk         (0x1UL << EXTI_EMR3_EM78_Pos)               /*!< 0x00004000 */

+#define EXTI_EMR3_EM78             EXTI_EMR3_EM78_Msk                          /*!< Event Mask on line 78 */

+#define EXTI_EMR3_EM79_Pos         (15U)

+#define EXTI_EMR3_EM79_Msk         (0x1UL << EXTI_EMR3_EM79_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR3_EM79             EXTI_EMR3_EM79_Msk                          /*!< Event Mask on line 79 */

+#define EXTI_EMR3_EM80_Pos         (16U)

+#define EXTI_EMR3_EM80_Msk         (0x1UL << EXTI_EMR3_EM80_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR3_EM80             EXTI_EMR3_EM80_Msk                          /*!< Event Mask on line 80 */

+#define EXTI_EMR3_EM81_Pos         (17U)

+#define EXTI_EMR3_EM81_Msk         (0x1UL << EXTI_EMR3_EM81_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR3_EM81             EXTI_EMR3_EM81_Msk                          /*!< Event Mask on line 81 */

+#define EXTI_EMR3_EM82_Pos         (18U)

+#define EXTI_EMR3_EM82_Msk         (0x1UL << EXTI_EMR3_EM82_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR3_EM82             EXTI_EMR3_EM82_Msk                          /*!< Event Mask on line 82 */

+#define EXTI_EMR3_EM84_Pos         (20U)

+#define EXTI_EMR3_EM84_Msk         (0x1UL << EXTI_EMR3_EM84_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR3_EM84             EXTI_EMR3_EM84_Msk                          /*!< Event Mask on line 84 */

+#define EXTI_EMR3_EM85_Pos         (21U)

+#define EXTI_EMR3_EM85_Msk         (0x1UL << EXTI_EMR3_EM85_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR3_EM85             EXTI_EMR3_EM85_Msk                          /*!< Event Mask on line 85 */

+#define EXTI_EMR3_EM86_Pos         (22U)

+#define EXTI_EMR3_EM86_Msk         (0x1UL << EXTI_EMR3_EM86_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR3_EM86             EXTI_EMR3_EM86_Msk                          /*!< Event Mask on line 86 */

+#define EXTI_EMR3_EM87_Pos         (23U)

+#define EXTI_EMR3_EM87_Msk         (0x1UL << EXTI_EMR3_EM87_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR3_EM87             EXTI_EMR3_EM87_Msk                          /*!< Event Mask on line 87 */

+

+/*******************  Bit definition for EXTI_PR3 register  ********************/

+#define EXTI_PR3_PR_Pos            (18U)

+#define EXTI_PR3_PR_Msk            (0x1DUL << EXTI_PR3_PR_Pos)                 /*!< 0x00740000 */

+#define EXTI_PR3_PR                EXTI_PR3_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR3_PR82_Pos          (18U)

+#define EXTI_PR3_PR82_Msk          (0x1UL << EXTI_PR3_PR82_Pos)                /*!< 0x00040000 */

+#define EXTI_PR3_PR82              EXTI_PR3_PR82_Msk                           /*!< Pending bit for line 82 */

+#define EXTI_PR3_PR84_Pos          (20U)

+#define EXTI_PR3_PR84_Msk          (0x1UL << EXTI_PR3_PR84_Pos)                /*!< 0x00100000 */

+#define EXTI_PR3_PR84              EXTI_PR3_PR84_Msk                           /*!< Pending bit for line 84 */

+#define EXTI_PR3_PR85_Pos          (21U)

+#define EXTI_PR3_PR85_Msk          (0x1UL << EXTI_PR3_PR85_Pos)                /*!< 0x00200000 */

+#define EXTI_PR3_PR85              EXTI_PR3_PR85_Msk                           /*!< Pending bit for line 85 */

+#define EXTI_PR3_PR86_Pos          (22U)

+#define EXTI_PR3_PR86_Msk          (0x1UL << EXTI_PR3_PR86_Pos)                /*!< 0x00400000 */

+#define EXTI_PR3_PR86              EXTI_PR3_PR86_Msk                           /*!< Pending bit for line 86 */

+/******************************************************************************/

+/*                                                                            */

+/*                                    FLASH                                   */

+/*                                                                            */

+/******************************************************************************/

+/*

+* @brief FLASH Global Defines

+*/

+#define FLASH_SECTOR_TOTAL                   8U                    /* 8 sectors */

+#define FLASH_SIZE                           0x200000UL            /* 2 MB   */

+#define FLASH_BANK_SIZE                      (FLASH_SIZE >> 1)     /* 1 MB   */

+#define FLASH_SECTOR_SIZE                    0x00020000UL          /* 128 KB */

+#define FLASH_LATENCY_DEFAULT                FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */

+#define FLASH_NB_32BITWORD_IN_FLASHWORD      8U                    /* 256 bits */

+#define DUAL_BANK                                                  /* Dual-bank Flash */

+

+/*******************  Bits definition for FLASH_ACR register  **********************/

+#define FLASH_ACR_LATENCY_Pos                (0U)

+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */

+#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */

+#define FLASH_ACR_LATENCY_0WS                (0x00000000UL)

+#define FLASH_ACR_LATENCY_1WS                (0x00000001UL)

+#define FLASH_ACR_LATENCY_2WS                (0x00000002UL)

+#define FLASH_ACR_LATENCY_3WS                (0x00000003UL)

+#define FLASH_ACR_LATENCY_4WS                (0x00000004UL)

+#define FLASH_ACR_LATENCY_5WS                (0x00000005UL)

+#define FLASH_ACR_LATENCY_6WS                (0x00000006UL)

+#define FLASH_ACR_LATENCY_7WS                (0x00000007UL)

+#define FLASH_ACR_LATENCY_8WS                (0x00000008UL)

+#define FLASH_ACR_LATENCY_9WS                (0x00000009UL)

+#define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)

+#define FLASH_ACR_LATENCY_11WS               (0x0000000BUL)

+#define FLASH_ACR_LATENCY_12WS               (0x0000000CUL)

+#define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)

+#define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)

+#define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)

+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)

+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */

+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */

+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */

+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */

+

+/*******************  Bits definition for FLASH_CR register  ***********************/

+#define FLASH_CR_LOCK_Pos                    (0U)

+#define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */

+#define FLASH_CR_LOCK                        FLASH_CR_LOCK_Msk                 /*!< Configuration lock bit */

+#define FLASH_CR_PG_Pos                      (1U)

+#define FLASH_CR_PG_Msk                      (0x1UL << FLASH_CR_PG_Pos)        /*!< 0x00000002 */

+#define FLASH_CR_PG                          FLASH_CR_PG_Msk                   /*!< Internal buffer control bit */

+#define FLASH_CR_SER_Pos                     (2U)

+#define FLASH_CR_SER_Msk                     (0x1UL << FLASH_CR_SER_Pos)       /*!< 0x00000004 */

+#define FLASH_CR_SER                         FLASH_CR_SER_Msk                  /*!< Sector erase request */

+#define FLASH_CR_BER_Pos                     (3U)

+#define FLASH_CR_BER_Msk                     (0x1UL << FLASH_CR_BER_Pos)       /*!< 0x00000008 */

+#define FLASH_CR_BER                         FLASH_CR_BER_Msk                  /*!< Bank erase request */

+#define FLASH_CR_PSIZE_Pos                   (4U)

+#define FLASH_CR_PSIZE_Msk                   (0x3UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000030 */

+#define FLASH_CR_PSIZE                       FLASH_CR_PSIZE_Msk                /*!< Program size */

+#define FLASH_CR_PSIZE_0                     (0x1UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000010 */

+#define FLASH_CR_PSIZE_1                     (0x2UL << FLASH_CR_PSIZE_Pos)     /*!< 0x00000020 */

+#define FLASH_CR_FW_Pos                      (6U)

+#define FLASH_CR_FW_Msk                      (0x1UL << FLASH_CR_FW_Pos)        /*!< 0x00000040 */

+#define FLASH_CR_FW                          FLASH_CR_FW_Msk                   /*!< Write forcing control bit */

+#define FLASH_CR_START_Pos                   (7U)

+#define FLASH_CR_START_Msk                   (0x1UL << FLASH_CR_START_Pos)     /*!< 0x00000080 */

+#define FLASH_CR_START                       FLASH_CR_START_Msk                /*!< Erase start control bit */

+#define FLASH_CR_SNB_Pos                     (8U)

+#define FLASH_CR_SNB_Msk                     (0x7UL << FLASH_CR_SNB_Pos)       /*!< 0x00000700 */

+#define FLASH_CR_SNB                         FLASH_CR_SNB_Msk                  /*!< Sector erase selection number */

+#define FLASH_CR_SNB_0                       (0x1UL << FLASH_CR_SNB_Pos)       /*!< 0x00000100 */

+#define FLASH_CR_SNB_1                       (0x2UL << FLASH_CR_SNB_Pos)       /*!< 0x00000200 */

+#define FLASH_CR_SNB_2                       (0x4UL << FLASH_CR_SNB_Pos)       /*!< 0x00000400 */

+#define FLASH_CR_CRC_EN_Pos                  (15U)

+#define FLASH_CR_CRC_EN_Msk                  (0x1UL << FLASH_CR_CRC_EN_Pos)    /*!< 0x00008000 */

+#define FLASH_CR_CRC_EN                      FLASH_CR_CRC_EN_Msk               /*!< CRC control bit */

+#define FLASH_CR_EOPIE_Pos                   (16U)

+#define FLASH_CR_EOPIE_Msk                   (0x1UL << FLASH_CR_EOPIE_Pos)     /*!< 0x00010000 */

+#define FLASH_CR_EOPIE                       FLASH_CR_EOPIE_Msk                /*!< End-of-program interrupt control bit */

+#define FLASH_CR_WRPERRIE_Pos                (17U)

+#define FLASH_CR_WRPERRIE_Msk                (0x1UL << FLASH_CR_WRPERRIE_Pos)  /*!< 0x00020000 */

+#define FLASH_CR_WRPERRIE                    FLASH_CR_WRPERRIE_Msk             /*!< Write protection error interrupt enable bit */

+#define FLASH_CR_PGSERRIE_Pos                (18U)

+#define FLASH_CR_PGSERRIE_Msk                (0x1UL << FLASH_CR_PGSERRIE_Pos)  /*!< 0x00040000 */

+#define FLASH_CR_PGSERRIE                    FLASH_CR_PGSERRIE_Msk             /*!< Programming sequence error interrupt enable bit */

+#define FLASH_CR_STRBERRIE_Pos               (19U)

+#define FLASH_CR_STRBERRIE_Msk               (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */

+#define FLASH_CR_STRBERRIE                   FLASH_CR_STRBERRIE_Msk            /*!< Strobe error interrupt enable bit */

+#define FLASH_CR_INCERRIE_Pos                (21U)

+#define FLASH_CR_INCERRIE_Msk                (0x1UL << FLASH_CR_INCERRIE_Pos)  /*!< 0x00200000 */

+#define FLASH_CR_INCERRIE                    FLASH_CR_INCERRIE_Msk             /*!< Inconsistency error interrupt enable bit */

+#define FLASH_CR_OPERRIE_Pos                 (22U)

+#define FLASH_CR_OPERRIE_Msk                 (0x1UL << FLASH_CR_OPERRIE_Pos)   /*!< 0x00400000 */

+#define FLASH_CR_OPERRIE                     FLASH_CR_OPERRIE_Msk              /*!< Write/erase error interrupt enable bit */

+#define FLASH_CR_RDPERRIE_Pos                (23U)

+#define FLASH_CR_RDPERRIE_Msk                (0x1UL << FLASH_CR_RDPERRIE_Pos)  /*!< 0x00800000 */

+#define FLASH_CR_RDPERRIE                    FLASH_CR_RDPERRIE_Msk             /*!< Read protection error interrupt enable bit */

+#define FLASH_CR_RDSERRIE_Pos                (24U)

+#define FLASH_CR_RDSERRIE_Msk                (0x1UL << FLASH_CR_RDSERRIE_Pos)  /*!< 0x01000000 */

+#define FLASH_CR_RDSERRIE                    FLASH_CR_RDSERRIE_Msk             /*!< Secure error interrupt enable bit */

+#define FLASH_CR_SNECCERRIE_Pos              (25U)

+#define FLASH_CR_SNECCERRIE_Msk              (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */

+#define FLASH_CR_SNECCERRIE                  FLASH_CR_SNECCERRIE_Msk            /*!< ECC single correction error interrupt enable bit */

+#define FLASH_CR_DBECCERRIE_Pos              (26U)

+#define FLASH_CR_DBECCERRIE_Msk              (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */

+#define FLASH_CR_DBECCERRIE                  FLASH_CR_DBECCERRIE_Msk            /*!< ECC double detection error interrupt enable bit */

+#define FLASH_CR_CRCENDIE_Pos                (27U)

+#define FLASH_CR_CRCENDIE_Msk                (0x1UL << FLASH_CR_CRCENDIE_Pos)  /*!< 0x08000000 */

+#define FLASH_CR_CRCENDIE                    FLASH_CR_CRCENDIE_Msk             /*!< CRC end of calculation interrupt enable bit */

+#define FLASH_CR_CRCRDERRIE_Pos              (28U)

+#define FLASH_CR_CRCRDERRIE_Msk              (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */

+#define FLASH_CR_CRCRDERRIE                  FLASH_CR_CRCRDERRIE_Msk            /*!< CRC read error interrupt enable bit */

+

+/*******************  Bits definition for FLASH_SR register  ***********************/

+#define FLASH_SR_BSY_Pos                     (0U)

+#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)       /*!< 0x00000001 */

+#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy flag */

+#define FLASH_SR_WBNE_Pos                    (1U)

+#define FLASH_SR_WBNE_Msk                    (0x1UL << FLASH_SR_WBNE_Pos)      /*!< 0x00000002 */

+#define FLASH_SR_WBNE                        FLASH_SR_WBNE_Msk                 /*!< Write buffer not empty flag */

+#define FLASH_SR_QW_Pos                      (2U)

+#define FLASH_SR_QW_Msk                      (0x1UL << FLASH_SR_QW_Pos)        /*!< 0x00000004 */

+#define FLASH_SR_QW                          FLASH_SR_QW_Msk                   /*!< Wait queue flag */

+#define FLASH_SR_CRC_BUSY_Pos                (3U)

+#define FLASH_SR_CRC_BUSY_Msk                (0x1UL << FLASH_SR_CRC_BUSY_Pos)  /*!< 0x00000008 */

+#define FLASH_SR_CRC_BUSY                    FLASH_SR_CRC_BUSY_Msk             /*!< CRC busy flag */

+#define FLASH_SR_EOP_Pos                     (16U)

+#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)       /*!< 0x00010000 */

+#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End-of-program flag */

+#define FLASH_SR_WRPERR_Pos                  (17U)

+#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)    /*!< 0x00020000 */

+#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protection error flag */

+#define FLASH_SR_PGSERR_Pos                  (18U)

+#define FLASH_SR_PGSERR_Msk                  (0x1UL << FLASH_SR_PGSERR_Pos)    /*!< 0x00040000 */

+#define FLASH_SR_PGSERR                      FLASH_SR_PGSERR_Msk               /*!< Programming sequence error flag */

+#define FLASH_SR_STRBERR_Pos                 (19U)

+#define FLASH_SR_STRBERR_Msk                 (0x1UL << FLASH_SR_STRBERR_Pos)   /*!< 0x00080000 */

+#define FLASH_SR_STRBERR                     FLASH_SR_STRBERR_Msk              /*!< Strobe error flag */

+#define FLASH_SR_INCERR_Pos                  (21U)

+#define FLASH_SR_INCERR_Msk                  (0x1UL << FLASH_SR_INCERR_Pos)    /*!< 0x00200000 */

+#define FLASH_SR_INCERR                      FLASH_SR_INCERR_Msk               /*!< Inconsistency error flag */

+#define FLASH_SR_OPERR_Pos                   (22U)

+#define FLASH_SR_OPERR_Msk                   (0x1UL << FLASH_SR_OPERR_Pos)     /*!< 0x00400000 */

+#define FLASH_SR_OPERR                       FLASH_SR_OPERR_Msk                /*!< Write/erase error flag */

+#define FLASH_SR_RDPERR_Pos                  (23U)

+#define FLASH_SR_RDPERR_Msk                  (0x1UL << FLASH_SR_RDPERR_Pos)    /*!< 0x00800000 */

+#define FLASH_SR_RDPERR                      FLASH_SR_RDPERR_Msk               /*!< Read protection error flag */

+#define FLASH_SR_RDSERR_Pos                  (24U)

+#define FLASH_SR_RDSERR_Msk                  (0x1UL << FLASH_SR_RDSERR_Pos)    /*!< 0x01000000 */

+#define FLASH_SR_RDSERR                      FLASH_SR_RDSERR_Msk               /*!< Secure error flag */

+#define FLASH_SR_SNECCERR_Pos                (25U)

+#define FLASH_SR_SNECCERR_Msk                (0x1UL << FLASH_SR_SNECCERR_Pos)  /*!< 0x02000000 */

+#define FLASH_SR_SNECCERR                    FLASH_SR_SNECCERR_Msk             /*!< Single correction error flag */

+#define FLASH_SR_DBECCERR_Pos                (26U)

+#define FLASH_SR_DBECCERR_Msk                (0x1UL << FLASH_SR_DBECCERR_Pos)  /*!< 0x04000000 */

+#define FLASH_SR_DBECCERR                    FLASH_SR_DBECCERR_Msk             /*!< ECC double detection error flag */

+#define FLASH_SR_CRCEND_Pos                  (27U)

+#define FLASH_SR_CRCEND_Msk                  (0x1UL << FLASH_SR_CRCEND_Pos)    /*!< 0x08000000 */

+#define FLASH_SR_CRCEND                      FLASH_SR_CRCEND_Msk               /*!< CRC end of calculation flag */

+#define FLASH_SR_CRCRDERR_Pos                (28U)

+#define FLASH_SR_CRCRDERR_Msk                (0x1UL << FLASH_SR_CRCRDERR_Pos)  /*!< 0x10000000 */

+#define FLASH_SR_CRCRDERR                    FLASH_SR_CRCRDERR_Msk             /*!< CRC read error flag */

+

+/*******************  Bits definition for FLASH_CCR register  *******************/

+#define FLASH_CCR_CLR_EOP_Pos                (16U)

+#define FLASH_CCR_CLR_EOP_Msk                (0x1UL << FLASH_CCR_CLR_EOP_Pos)  /*!< 0x00010000 */

+#define FLASH_CCR_CLR_EOP                    FLASH_CCR_CLR_EOP_Msk             /*!< EOP flag clear bit */

+#define FLASH_CCR_CLR_WRPERR_Pos             (17U)

+#define FLASH_CCR_CLR_WRPERR_Msk             (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */

+#define FLASH_CCR_CLR_WRPERR                 FLASH_CCR_CLR_WRPERR_Msk            /*!< WRPERR flag clear bit */

+#define FLASH_CCR_CLR_PGSERR_Pos             (18U)

+#define FLASH_CCR_CLR_PGSERR_Msk             (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */

+#define FLASH_CCR_CLR_PGSERR                 FLASH_CCR_CLR_PGSERR_Msk            /*!< PGSERR flag clear bit */

+#define FLASH_CCR_CLR_STRBERR_Pos            (19U)

+#define FLASH_CCR_CLR_STRBERR_Msk            (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */

+#define FLASH_CCR_CLR_STRBERR                FLASH_CCR_CLR_STRBERR_Msk            /*!< STRBERR flag clear bit */

+#define FLASH_CCR_CLR_INCERR_Pos             (21U)

+#define FLASH_CCR_CLR_INCERR_Msk             (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */

+#define FLASH_CCR_CLR_INCERR                 FLASH_CCR_CLR_INCERR_Msk            /*!< INCERR flag clear bit */

+#define FLASH_CCR_CLR_OPERR_Pos              (22U)

+#define FLASH_CCR_CLR_OPERR_Msk              (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */

+#define FLASH_CCR_CLR_OPERR                  FLASH_CCR_CLR_OPERR_Msk            /*!< OPERR flag clear bit */

+#define FLASH_CCR_CLR_RDPERR_Pos             (23U)

+#define FLASH_CCR_CLR_RDPERR_Msk             (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */

+#define FLASH_CCR_CLR_RDPERR                 FLASH_CCR_CLR_RDPERR_Msk            /*!< RDPERR flag clear bit */

+#define FLASH_CCR_CLR_RDSERR_Pos             (24U)

+#define FLASH_CCR_CLR_RDSERR_Msk             (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */

+#define FLASH_CCR_CLR_RDSERR                 FLASH_CCR_CLR_RDSERR_Msk            /*!< RDSERR flag clear bit */

+#define FLASH_CCR_CLR_SNECCERR_Pos           (25U)

+#define FLASH_CCR_CLR_SNECCERR_Msk           (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */

+#define FLASH_CCR_CLR_SNECCERR               FLASH_CCR_CLR_SNECCERR_Msk            /*!< SNECCERR flag clear bit */

+#define FLASH_CCR_CLR_DBECCERR_Pos           (26U)

+#define FLASH_CCR_CLR_DBECCERR_Msk           (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */

+#define FLASH_CCR_CLR_DBECCERR               FLASH_CCR_CLR_DBECCERR_Msk            /*!< DBECCERR flag clear bit */

+#define FLASH_CCR_CLR_CRCEND_Pos             (27U)

+#define FLASH_CCR_CLR_CRCEND_Msk             (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */

+#define FLASH_CCR_CLR_CRCEND                 FLASH_CCR_CLR_CRCEND_Msk            /*!< CRCEND flag clear bit */

+#define FLASH_CCR_CLR_CRCRDERR_Pos           (28U)

+#define FLASH_CCR_CLR_CRCRDERR_Msk           (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */

+#define FLASH_CCR_CLR_CRCRDERR               FLASH_CCR_CLR_CRCRDERR_Msk            /*!< CRCRDERR flag clear bit */

+

+/*******************  Bits definition for FLASH_OPTCR register  *******************/

+#define FLASH_OPTCR_OPTLOCK_Pos              (0U)

+#define FLASH_OPTCR_OPTLOCK_Msk              (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)  /*!< 0x00000001 */

+#define FLASH_OPTCR_OPTLOCK                  FLASH_OPTCR_OPTLOCK_Msk             /*!< FLASH_OPTCR lock option configuration bit */

+#define FLASH_OPTCR_OPTSTART_Pos             (1U)

+#define FLASH_OPTCR_OPTSTART_Msk             (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */

+#define FLASH_OPTCR_OPTSTART                 FLASH_OPTCR_OPTSTART_Msk            /*!< Option byte start change option configuration bit */

+#define FLASH_OPTCR_MER_Pos                  (4U)

+#define FLASH_OPTCR_MER_Msk                  (0x1UL << FLASH_OPTCR_MER_Pos)      /*!< 0x00000010 */

+#define FLASH_OPTCR_MER                      FLASH_OPTCR_MER_Msk                 /*!< Mass erase request */

+#define FLASH_OPTCR_OPTCHANGEERRIE_Pos       (30U)

+#define FLASH_OPTCR_OPTCHANGEERRIE_Msk       (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */

+#define FLASH_OPTCR_OPTCHANGEERRIE           FLASH_OPTCR_OPTCHANGEERRIE_Msk            /*!< Option byte change error interrupt enable bit */

+#define FLASH_OPTCR_SWAP_BANK_Pos            (31U)

+#define FLASH_OPTCR_SWAP_BANK_Msk            (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */

+#define FLASH_OPTCR_SWAP_BANK                FLASH_OPTCR_SWAP_BANK_Msk            /*!< Bank swapping option configuration bit */

+

+/*******************  Bits definition for FLASH_OPTSR register  ***************/

+#define FLASH_OPTSR_OPT_BUSY_Pos             (0U)

+#define FLASH_OPTSR_OPT_BUSY_Msk             (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */

+#define FLASH_OPTSR_OPT_BUSY                 FLASH_OPTSR_OPT_BUSY_Msk            /*!< Option byte change ongoing flag */

+#define FLASH_OPTSR_BOR_LEV_Pos              (2U)

+#define FLASH_OPTSR_BOR_LEV_Msk              (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */

+#define FLASH_OPTSR_BOR_LEV                  FLASH_OPTSR_BOR_LEV_Msk            /*!< Brownout level option status bit */

+#define FLASH_OPTSR_BOR_LEV_0                (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */

+#define FLASH_OPTSR_BOR_LEV_1                (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */

+#define FLASH_OPTSR_IWDG1_SW_Pos             (4U)

+#define FLASH_OPTSR_IWDG1_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */

+#define FLASH_OPTSR_IWDG1_SW                 FLASH_OPTSR_IWDG1_SW_Msk            /*!< IWDG1 control mode option status bit */

+#define FLASH_OPTSR_IWDG2_SW_Pos             (5U)

+#define FLASH_OPTSR_IWDG2_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG2_SW_Pos) /*!< 0x00000020 */

+#define FLASH_OPTSR_IWDG2_SW                 FLASH_OPTSR_IWDG2_SW_Msk            /*!< IWDG2 control mode option status bit */

+#define FLASH_OPTSR_NRST_STOP_D1_Pos         (6U)

+#define FLASH_OPTSR_NRST_STOP_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */

+#define FLASH_OPTSR_NRST_STOP_D1             FLASH_OPTSR_NRST_STOP_D1_Msk            /*!< D1 domain DStop entry reset option status bit */

+#define FLASH_OPTSR_NRST_STBY_D1_Pos         (7U)

+#define FLASH_OPTSR_NRST_STBY_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */

+#define FLASH_OPTSR_NRST_STBY_D1             FLASH_OPTSR_NRST_STBY_D1_Msk            /*!< D1 domain DStandby entry reset option status bit */

+#define FLASH_OPTSR_RDP_Pos                  (8U)

+#define FLASH_OPTSR_RDP_Msk                  (0xFFUL << FLASH_OPTSR_RDP_Pos)   /*!< 0x0000FF00 */

+#define FLASH_OPTSR_RDP                      FLASH_OPTSR_RDP_Msk               /*!< Readout protection level option status byte */

+#define FLASH_OPTSR_FZ_IWDG_STOP_Pos         (17U)

+#define FLASH_OPTSR_FZ_IWDG_STOP_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */

+#define FLASH_OPTSR_FZ_IWDG_STOP             FLASH_OPTSR_FZ_IWDG_STOP_Msk            /*!< IWDG Stop mode freeze option status bit */

+#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos         (18U)

+#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */

+#define FLASH_OPTSR_FZ_IWDG_SDBY             FLASH_OPTSR_FZ_IWDG_SDBY_Msk            /*!< IWDG Standby mode freeze option status bit */

+#define FLASH_OPTSR_ST_RAM_SIZE_Pos          (19U)

+#define FLASH_OPTSR_ST_RAM_SIZE_Msk          (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */

+#define FLASH_OPTSR_ST_RAM_SIZE              FLASH_OPTSR_ST_RAM_SIZE_Msk            /*!< ST RAM size option status */

+#define FLASH_OPTSR_ST_RAM_SIZE_0            (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */

+#define FLASH_OPTSR_ST_RAM_SIZE_1            (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */

+#define FLASH_OPTSR_SECURITY_Pos             (21U)

+#define FLASH_OPTSR_SECURITY_Msk             (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */

+#define FLASH_OPTSR_SECURITY                 FLASH_OPTSR_SECURITY_Msk            /*!< Security enable option status bit */

+#define FLASH_OPTSR_BCM4_Pos                 (22U)

+#define FLASH_OPTSR_BCM4_Msk                 (0x1UL << FLASH_OPTSR_BCM4_Pos)   /*!< 0x00400000 */

+#define FLASH_OPTSR_BCM4                     FLASH_OPTSR_BCM4_Msk              /*!< Arm Cortex-M4 boot option status bit */

+#define FLASH_OPTSR_BCM7_Pos                 (23U)

+#define FLASH_OPTSR_BCM7_Msk                 (0x1UL << FLASH_OPTSR_BCM7_Pos)   /*!< 0x00800000 */

+#define FLASH_OPTSR_BCM7                     FLASH_OPTSR_BCM7_Msk              /*!< Arm Cortex-M7 boot option status bit */

+#define FLASH_OPTSR_NRST_STOP_D2_Pos         (24U)

+#define FLASH_OPTSR_NRST_STOP_D2_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D2_Pos) /*!< 0x01000000 */

+#define FLASH_OPTSR_NRST_STOP_D2             FLASH_OPTSR_NRST_STOP_D2_Msk            /*!< D2 domain DStop entry reset option status bit */

+#define FLASH_OPTSR_NRST_STBY_D2_Pos         (25U)

+#define FLASH_OPTSR_NRST_STBY_D2_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D2_Pos) /*!< 0x02000000 */

+#define FLASH_OPTSR_NRST_STBY_D2             FLASH_OPTSR_NRST_STBY_D2_Msk            /*!< D2 domain DStandby entry reset option status bit */

+#define FLASH_OPTSR_IO_HSLV_Pos              (29U)

+#define FLASH_OPTSR_IO_HSLV_Msk              (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */

+#define FLASH_OPTSR_IO_HSLV                  FLASH_OPTSR_IO_HSLV_Msk            /*!< I/O high-speed at low-voltage status bit */

+#define FLASH_OPTSR_OPTCHANGEERR_Pos         (30U)

+#define FLASH_OPTSR_OPTCHANGEERR_Msk         (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */

+#define FLASH_OPTSR_OPTCHANGEERR             FLASH_OPTSR_OPTCHANGEERR_Msk            /*!< Option byte change error flag */

+#define FLASH_OPTSR_SWAP_BANK_OPT_Pos        (31U)

+#define FLASH_OPTSR_SWAP_BANK_OPT_Msk        (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */

+#define FLASH_OPTSR_SWAP_BANK_OPT            FLASH_OPTSR_SWAP_BANK_OPT_Msk            /*!< Bank swapping option status bit */

+

+/*******************  Bits definition for FLASH_OPTCCR register  *******************/

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos    (30U)

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk    (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR        FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk            /*!< OPTCHANGEERR reset bit */

+

+/*******************  Bits definition for FLASH_PRAR register  *********************/

+#define FLASH_PRAR_PROT_AREA_START_Pos       (0U)

+#define FLASH_PRAR_PROT_AREA_START_Msk       (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */

+#define FLASH_PRAR_PROT_AREA_START           FLASH_PRAR_PROT_AREA_START_Msk              /*!< PCROP area start status bits */

+#define FLASH_PRAR_PROT_AREA_END_Pos         (16U)

+#define FLASH_PRAR_PROT_AREA_END_Msk         (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */

+#define FLASH_PRAR_PROT_AREA_END             FLASH_PRAR_PROT_AREA_END_Msk              /*!< PCROP area end status bits */

+#define FLASH_PRAR_DMEP_Pos                  (31U)

+#define FLASH_PRAR_DMEP_Msk                  (0x1UL << FLASH_PRAR_DMEP_Pos)    /*!< 0x80000000 */

+#define FLASH_PRAR_DMEP                      FLASH_PRAR_DMEP_Msk               /*!< PCROP protected erase enable option status bit */

+

+/*******************  Bits definition for FLASH_SCAR register  *********************/

+#define FLASH_SCAR_SEC_AREA_START_Pos        (0U)

+#define FLASH_SCAR_SEC_AREA_START_Msk        (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */

+#define FLASH_SCAR_SEC_AREA_START            FLASH_SCAR_SEC_AREA_START_Msk              /*!< Secure-only area start status bits */

+#define FLASH_SCAR_SEC_AREA_END_Pos          (16U)

+#define FLASH_SCAR_SEC_AREA_END_Msk          (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */

+#define FLASH_SCAR_SEC_AREA_END              FLASH_SCAR_SEC_AREA_END_Msk              /*!< Secure-only area end status bits */

+#define FLASH_SCAR_DMES_Pos                  (31U)

+#define FLASH_SCAR_DMES_Msk                  (0x1UL << FLASH_SCAR_DMES_Pos)    /*!< 0x80000000 */

+#define FLASH_SCAR_DMES                      FLASH_SCAR_DMES_Msk               /*!< Secure access protected erase enable option status bit */

+

+/*******************  Bits definition for FLASH_WPSN register  *********************/

+#define FLASH_WPSN_WRPSN_Pos                 (0U)

+#define FLASH_WPSN_WRPSN_Msk                 (0xFFUL << FLASH_WPSN_WRPSN_Pos)  /*!< 0x000000FF */

+#define FLASH_WPSN_WRPSN                     FLASH_WPSN_WRPSN_Msk              /*!< Sector write protection option status byte */

+

+/*******************  Bits definition for FLASH_BOOT7_CUR register  ****************/

+#define FLASH_BOOT7_BCM7_ADD0_Pos            (0U)

+#define FLASH_BOOT7_BCM7_ADD0_Msk            (0xFFFFUL << FLASH_BOOT7_BCM7_ADD0_Pos) /*!< 0x0000FFFF */

+#define FLASH_BOOT7_BCM7_ADD0                FLASH_BOOT7_BCM7_ADD0_Msk               /*!< Arm Cortex-M7 boot address 0 */

+#define FLASH_BOOT7_BCM7_ADD1_Pos            (16U)

+#define FLASH_BOOT7_BCM7_ADD1_Msk            (0xFFFFUL << FLASH_BOOT7_BCM7_ADD1_Pos) /*!< 0xFFFF0000 */

+#define FLASH_BOOT7_BCM7_ADD1                FLASH_BOOT7_BCM7_ADD1_Msk               /*!< Arm Cortex-M7 boot address 1 */

+

+/*******************  Bits definition for FLASH_BOOT4 register  ********************/

+#define FLASH_BOOT4_BCM4_ADD0_Pos            (0U)

+#define FLASH_BOOT4_BCM4_ADD0_Msk            (0xFFFFUL << FLASH_BOOT4_BCM4_ADD0_Pos) /*!< 0x0000FFFF */

+#define FLASH_BOOT4_BCM4_ADD0                FLASH_BOOT4_BCM4_ADD0_Msk               /*!< Arm Cortex-M4 boot address 0 */

+#define FLASH_BOOT4_BCM4_ADD1_Pos            (16U)

+#define FLASH_BOOT4_BCM4_ADD1_Msk            (0xFFFFUL << FLASH_BOOT4_BCM4_ADD1_Pos) /*!< 0xFFFF0000 */

+#define FLASH_BOOT4_BCM4_ADD1                FLASH_BOOT4_BCM4_ADD1_Msk               /*!< Arm Cortex-M4 boot address 1 */

+

+/*******************  Bits definition for FLASH_CRCCR register  ********************/

+#define FLASH_CRCCR_CRC_SECT_Pos             (0U)

+#define FLASH_CRCCR_CRC_SECT_Msk             (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */

+#define FLASH_CRCCR_CRC_SECT                 FLASH_CRCCR_CRC_SECT_Msk            /*!< CRC sector number */

+#define FLASH_CRCCR_CRC_BY_SECT_Pos          (8U)

+#define FLASH_CRCCR_CRC_BY_SECT_Msk          (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */

+#define FLASH_CRCCR_CRC_BY_SECT              FLASH_CRCCR_CRC_BY_SECT_Msk            /*!< CRC sector mode select bit */

+#define FLASH_CRCCR_ADD_SECT_Pos             (9U)

+#define FLASH_CRCCR_ADD_SECT_Msk             (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */

+#define FLASH_CRCCR_ADD_SECT                 FLASH_CRCCR_ADD_SECT_Msk            /*!< CRC sector select bit */

+#define FLASH_CRCCR_CLEAN_SECT_Pos           (10U)

+#define FLASH_CRCCR_CLEAN_SECT_Msk           (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */

+#define FLASH_CRCCR_CLEAN_SECT               FLASH_CRCCR_CLEAN_SECT_Msk            /*!< CRC sector list clear bit */

+#define FLASH_CRCCR_START_CRC_Pos            (16U)

+#define FLASH_CRCCR_START_CRC_Msk            (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */

+#define FLASH_CRCCR_START_CRC                FLASH_CRCCR_START_CRC_Msk            /*!< CRC start bit */

+#define FLASH_CRCCR_CLEAN_CRC_Pos            (17U)

+#define FLASH_CRCCR_CLEAN_CRC_Msk            (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */

+#define FLASH_CRCCR_CLEAN_CRC                FLASH_CRCCR_CLEAN_CRC_Msk            /*!< CRC clear bit */

+#define FLASH_CRCCR_CRC_BURST_Pos            (20U)

+#define FLASH_CRCCR_CRC_BURST_Msk            (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */

+#define FLASH_CRCCR_CRC_BURST                FLASH_CRCCR_CRC_BURST_Msk            /*!< CRC burst size */

+#define FLASH_CRCCR_CRC_BURST_0              (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */

+#define FLASH_CRCCR_CRC_BURST_1              (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */

+#define FLASH_CRCCR_ALL_BANK_Pos             (22U)

+#define FLASH_CRCCR_ALL_BANK_Msk             (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */

+#define FLASH_CRCCR_ALL_BANK                 FLASH_CRCCR_ALL_BANK_Msk            /*!< CRC select bit */

+

+/*******************  Bits definition for FLASH_CRCSADD register  ****************/

+#define FLASH_CRCSADD_CRC_START_ADDR_Pos     (0U)

+#define FLASH_CRCSADD_CRC_START_ADDR_Msk     (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCSADD_CRC_START_ADDR         FLASH_CRCSADD_CRC_START_ADDR_Msk                   /*!< CRC start address */

+

+/*******************  Bits definition for FLASH_CRCEADD register  ****************/

+#define FLASH_CRCEADD_CRC_END_ADDR_Pos       (0U)

+#define FLASH_CRCEADD_CRC_END_ADDR_Msk       (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCEADD_CRC_END_ADDR           FLASH_CRCEADD_CRC_END_ADDR_Msk                   /*!< CRC end address */

+

+/*******************  Bits definition for FLASH_CRCDATA register  ***************/

+#define FLASH_CRCDATA_CRC_DATA_Pos           (0U)

+#define FLASH_CRCDATA_CRC_DATA_Msk           (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCDATA_CRC_DATA               FLASH_CRCDATA_CRC_DATA_Msk                   /*!< CRC result */

+

+/*******************  Bits definition for FLASH_ECC_FA register  *******************/

+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos       (0U)

+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk       (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */

+#define FLASH_ECC_FA_FAIL_ECC_ADDR           FLASH_ECC_FA_FAIL_ECC_ADDR_Msk               /*!< ECC error address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          Flexible Memory Controller                        */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for FMC_BCR1 register  *******************/

+#define FMC_BCR1_CCLKEN_Pos        (20U)

+#define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */

+#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continous clock enable     */

+#define FMC_BCR1_WFDIS_Pos         (21U)

+#define FMC_BCR1_WFDIS_Msk         (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */

+#define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */

+

+#define FMC_BCR1_BMAP_Pos          (24U)

+#define FMC_BCR1_BMAP_Msk          (0x3UL << FMC_BCR1_BMAP_Pos)                /*!< 0x03000000 */

+#define FMC_BCR1_BMAP              FMC_BCR1_BMAP_Msk                           /*!<BMAP[1:0] FMC bank mapping */

+#define FMC_BCR1_BMAP_0            (0x1UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x01000000 */

+#define FMC_BCR1_BMAP_1            (0x2UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x02000000 */

+

+#define FMC_BCR1_FMCEN_Pos         (31U)

+#define FMC_BCR1_FMCEN_Msk         (0x1UL << FMC_BCR1_FMCEN_Pos)               /*!< 0x80000000 */

+#define FMC_BCR1_FMCEN             FMC_BCR1_FMCEN_Msk                          /*!<FMC controller Enable */

+/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/

+#define FMC_BCRx_MBKEN_Pos         (0U)

+#define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */

+#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */

+#define FMC_BCRx_MUXEN_Pos         (1U)

+#define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */

+#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */

+

+#define FMC_BCRx_MTYP_Pos          (2U)

+#define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */

+#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */

+#define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000004 */

+#define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000008 */

+

+#define FMC_BCRx_MWID_Pos          (4U)

+#define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */

+#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */

+#define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000010 */

+#define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000020 */

+

+#define FMC_BCRx_FACCEN_Pos        (6U)

+#define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */

+#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */

+#define FMC_BCRx_BURSTEN_Pos       (8U)

+#define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */

+#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */

+#define FMC_BCRx_WAITPOL_Pos       (9U)

+#define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */

+#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */

+#define FMC_BCRx_WAITCFG_Pos       (11U)

+#define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */

+#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */

+#define FMC_BCRx_WREN_Pos          (12U)

+#define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */

+#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */

+#define FMC_BCRx_WAITEN_Pos        (13U)

+#define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */

+#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */

+#define FMC_BCRx_EXTMOD_Pos        (14U)

+#define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */

+#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */

+#define FMC_BCRx_ASYNCWAIT_Pos     (15U)

+#define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */

+#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */

+

+#define FMC_BCRx_CPSIZE_Pos        (16U)

+#define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */

+#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<PSIZE[2:0] bits CRAM Page Size */

+#define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00010000 */

+#define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00020000 */

+#define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00040000 */

+

+#define FMC_BCRx_CBURSTRW_Pos      (19U)

+#define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */

+#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */

+

+/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/

+#define FMC_BTRx_ADDSET_Pos        (0U)

+#define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */

+#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */

+#define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000001 */

+#define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000002 */

+#define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000004 */

+#define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000008 */

+

+#define FMC_BTRx_ADDHLD_Pos        (4U)

+#define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */

+#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */

+#define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000010 */

+#define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000020 */

+#define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000040 */

+#define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000080 */

+

+#define FMC_BTRx_DATAST_Pos        (8U)

+#define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */

+#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */

+#define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000100 */

+#define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000200 */

+#define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000400 */

+#define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000800 */

+#define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00001000 */

+#define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00002000 */

+#define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00004000 */

+#define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00008000 */

+

+#define FMC_BTRx_BUSTURN_Pos       (16U)

+#define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */

+#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */

+#define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00010000 */

+#define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00020000 */

+#define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00040000 */

+#define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00080000 */

+

+#define FMC_BTRx_CLKDIV_Pos        (20U)

+#define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */

+#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */

+#define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00100000 */

+#define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00200000 */

+#define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00400000 */

+#define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00800000 */

+

+#define FMC_BTRx_DATLAT_Pos        (24U)

+#define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */

+#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */

+#define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x01000000 */

+#define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x02000000 */

+#define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x04000000 */

+#define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x08000000 */

+

+#define FMC_BTRx_ACCMOD_Pos        (28U)

+#define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */

+#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */

+#define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x10000000 */

+#define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x20000000 */

+

+/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/

+#define FMC_BWTRx_ADDSET_Pos       (0U)

+#define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */

+#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */

+#define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000001 */

+#define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000002 */

+#define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000004 */

+#define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000008 */

+

+#define FMC_BWTRx_ADDHLD_Pos       (4U)

+#define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */

+#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */

+#define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000010 */

+#define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000020 */

+#define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000040 */

+#define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000080 */

+

+#define FMC_BWTRx_DATAST_Pos       (8U)

+#define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */

+#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */

+#define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000100 */

+#define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000200 */

+#define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000400 */

+#define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000800 */

+#define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00001000 */

+#define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00002000 */

+#define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00004000 */

+#define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00008000 */

+

+#define FMC_BWTRx_BUSTURN_Pos      (16U)

+#define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */

+#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */

+#define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00010000 */

+#define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00020000 */

+#define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00040000 */

+#define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00080000 */

+

+#define FMC_BWTRx_ACCMOD_Pos       (28U)

+#define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */

+#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */

+#define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x10000000 */

+#define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x20000000 */

+

+/******************  Bit definition for FMC_PCR register  *******************/

+#define FMC_PCR_PWAITEN_Pos        (1U)

+#define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */

+#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */

+#define FMC_PCR_PBKEN_Pos          (2U)

+#define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */

+#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */

+

+#define FMC_PCR_PWID_Pos           (4U)

+#define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */

+#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */

+#define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */

+#define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */

+

+#define FMC_PCR_ECCEN_Pos          (6U)

+#define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */

+#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */

+

+#define FMC_PCR_TCLR_Pos           (9U)

+#define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */

+#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */

+#define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */

+#define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */

+#define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */

+#define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */

+

+#define FMC_PCR_TAR_Pos            (13U)

+#define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */

+#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */

+#define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */

+#define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */

+#define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */

+#define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */

+

+#define FMC_PCR_ECCPS_Pos          (17U)

+#define FMC_PCR_ECCPS_Msk          (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */

+#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */

+#define FMC_PCR_ECCPS_0            (0x1UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */

+#define FMC_PCR_ECCPS_1            (0x2UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */

+#define FMC_PCR_ECCPS_2            (0x4UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */

+

+/*******************  Bit definition for FMC_SR register  *******************/

+#define FMC_SR_IRS_Pos             (0U)

+#define FMC_SR_IRS_Msk             (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */

+#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */

+#define FMC_SR_ILS_Pos             (1U)

+#define FMC_SR_ILS_Msk             (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */

+#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */

+#define FMC_SR_IFS_Pos             (2U)

+#define FMC_SR_IFS_Msk             (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */

+#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */

+#define FMC_SR_IREN_Pos            (3U)

+#define FMC_SR_IREN_Msk            (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */

+#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */

+#define FMC_SR_ILEN_Pos            (4U)

+#define FMC_SR_ILEN_Msk            (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */

+#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */

+#define FMC_SR_IFEN_Pos            (5U)

+#define FMC_SR_IFEN_Msk            (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */

+#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */

+#define FMC_SR_FEMPT_Pos           (6U)

+#define FMC_SR_FEMPT_Msk           (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */

+#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */

+

+/******************  Bit definition for FMC_PMEM register  ******************/

+#define FMC_PMEM_MEMSET_Pos       (0U)

+#define FMC_PMEM_MEMSET_Msk       (0xFFUL << FMC_PMEM_MEMSET_Pos)            /*!< 0x000000FF */

+#define FMC_PMEM_MEMSET           FMC_PMEM_MEMSET_Msk                        /*!<MEMSET[7:0] bits (Common memory setup time) */

+#define FMC_PMEM_MEMSET_0         (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */

+#define FMC_PMEM_MEMSET_1         (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */

+#define FMC_PMEM_MEMSET_2         (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */

+#define FMC_PMEM_MEMSET_3         (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */

+#define FMC_PMEM_MEMSET_4         (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */

+#define FMC_PMEM_MEMSET_5         (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */

+#define FMC_PMEM_MEMSET_6         (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */

+#define FMC_PMEM_MEMSET_7         (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */

+

+#define FMC_PMEM_MEMWAIT_Pos      (8U)

+#define FMC_PMEM_MEMWAIT_Msk      (0xFFUL << FMC_PMEM_MEMWAIT_Pos)           /*!< 0x0000FF00 */

+#define FMC_PMEM_MEMWAIT          FMC_PMEM_MEMWAIT_Msk                       /*!<MEMWAIT[7:0] bits (Common memory wait time) */

+#define FMC_PMEM_MEMWAIT_0        (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */

+#define FMC_PMEM_MEMWAIT_1        (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */

+#define FMC_PMEM_MEMWAIT_2        (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */

+#define FMC_PMEM_MEMWAIT_3        (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */

+#define FMC_PMEM_MEMWAIT_4        (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */

+#define FMC_PMEM_MEMWAIT_5        (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */

+#define FMC_PMEM_MEMWAIT_6        (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */

+#define FMC_PMEM_MEMWAIT_7        (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */

+

+#define FMC_PMEM_MEMHOLD_Pos      (16U)

+#define FMC_PMEM_MEMHOLD_Msk      (0xFFUL << FMC_PMEM_MEMHOLD_Pos)           /*!< 0x00FF0000 */

+#define FMC_PMEM_MEMHOLD          FMC_PMEM_MEMHOLD_Msk                       /*!<MEMHOLD[7:0] bits (Common memory hold time) */

+#define FMC_PMEM_MEMHOLD_0        (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */

+#define FMC_PMEM_MEMHOLD_1        (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */

+#define FMC_PMEM_MEMHOLD_2        (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */

+#define FMC_PMEM_MEMHOLD_3        (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */

+#define FMC_PMEM_MEMHOLD_4        (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */

+#define FMC_PMEM_MEMHOLD_5        (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */

+#define FMC_PMEM_MEMHOLD_6        (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */

+#define FMC_PMEM_MEMHOLD_7        (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */

+

+#define FMC_PMEM_MEMHIZ_Pos       (24U)

+#define FMC_PMEM_MEMHIZ_Msk       (0xFFUL << FMC_PMEM_MEMHIZ_Pos)            /*!< 0xFF000000 */

+#define FMC_PMEM_MEMHIZ           FMC_PMEM_MEMHIZ_Msk                        /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */

+#define FMC_PMEM_MEMHIZ_0         (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */

+#define FMC_PMEM_MEMHIZ_1         (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */

+#define FMC_PMEM_MEMHIZ_2         (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */

+#define FMC_PMEM_MEMHIZ_3         (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */

+#define FMC_PMEM_MEMHIZ_4         (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */

+#define FMC_PMEM_MEMHIZ_5         (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */

+#define FMC_PMEM_MEMHIZ_6         (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */

+#define FMC_PMEM_MEMHIZ_7         (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */

+

+/******************  Bit definition for FMC_PATT register  ******************/

+#define FMC_PATT_ATTSET_Pos       (0U)

+#define FMC_PATT_ATTSET_Msk       (0xFFUL << FMC_PATT_ATTSET_Pos)            /*!< 0x000000FF */

+#define FMC_PATT_ATTSET           FMC_PATT_ATTSET_Msk                        /*!<ATTSET[7:0] bits (Attribute memory setup time) */

+#define FMC_PATT_ATTSET_0         (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */

+#define FMC_PATT_ATTSET_1         (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */

+#define FMC_PATT_ATTSET_2         (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */

+#define FMC_PATT_ATTSET_3         (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */

+#define FMC_PATT_ATTSET_4         (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */

+#define FMC_PATT_ATTSET_5         (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */

+#define FMC_PATT_ATTSET_6         (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */

+#define FMC_PATT_ATTSET_7         (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */

+

+#define FMC_PATT_ATTWAIT_Pos      (8U)

+#define FMC_PATT_ATTWAIT_Msk      (0xFFUL << FMC_PATT_ATTWAIT_Pos)           /*!< 0x0000FF00 */

+#define FMC_PATT_ATTWAIT          FMC_PATT_ATTWAIT_Msk                       /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */

+#define FMC_PATT_ATTWAIT_0        (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */

+#define FMC_PATT_ATTWAIT_1        (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */

+#define FMC_PATT_ATTWAIT_2        (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */

+#define FMC_PATT_ATTWAIT_3        (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */

+#define FMC_PATT_ATTWAIT_4        (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */

+#define FMC_PATT_ATTWAIT_5        (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */

+#define FMC_PATT_ATTWAIT_6        (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */

+#define FMC_PATT_ATTWAIT_7        (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */

+

+#define FMC_PATT_ATTHOLD_Pos      (16U)

+#define FMC_PATT_ATTHOLD_Msk      (0xFFUL << FMC_PATT_ATTHOLD_Pos)           /*!< 0x00FF0000 */

+#define FMC_PATT_ATTHOLD          FMC_PATT_ATTHOLD_Msk                       /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */

+#define FMC_PATT_ATTHOLD_0        (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */

+#define FMC_PATT_ATTHOLD_1        (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */

+#define FMC_PATT_ATTHOLD_2        (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */

+#define FMC_PATT_ATTHOLD_3        (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */

+#define FMC_PATT_ATTHOLD_4        (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */

+#define FMC_PATT_ATTHOLD_5        (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */

+#define FMC_PATT_ATTHOLD_6        (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */

+#define FMC_PATT_ATTHOLD_7        (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */

+

+#define FMC_PATT_ATTHIZ_Pos       (24U)

+#define FMC_PATT_ATTHIZ_Msk       (0xFFUL << FMC_PATT_ATTHIZ_Pos)            /*!< 0xFF000000 */

+#define FMC_PATT_ATTHIZ           FMC_PATT_ATTHIZ_Msk                        /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */

+#define FMC_PATT_ATTHIZ_0         (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */

+#define FMC_PATT_ATTHIZ_1         (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */

+#define FMC_PATT_ATTHIZ_2         (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */

+#define FMC_PATT_ATTHIZ_3         (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */

+#define FMC_PATT_ATTHIZ_4         (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */

+#define FMC_PATT_ATTHIZ_5         (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */

+#define FMC_PATT_ATTHIZ_6         (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */

+#define FMC_PATT_ATTHIZ_7         (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */

+

+/******************  Bit definition for FMC_ECCR3 register  ******************/

+#define FMC_ECCR3_ECC3_Pos         (0U)

+#define FMC_ECCR3_ECC3_Msk         (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)        /*!< 0xFFFFFFFF */

+#define FMC_ECCR3_ECC3             FMC_ECCR3_ECC3_Msk                          /*!<ECC result */

+

+/******************  Bit definition for FMC_SDCRx registers (x=1..4)  *********/

+#define FMC_SDCRx_NC_Pos           (0U)

+#define FMC_SDCRx_NC_Msk           (0x3UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000003 */

+#define FMC_SDCRx_NC               FMC_SDCRx_NC_Msk                            /*!<NC[1:0] bits (Number of column bits) */

+#define FMC_SDCRx_NC_0             (0x1UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000001 */

+#define FMC_SDCRx_NC_1             (0x2UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000002 */

+

+#define FMC_SDCRx_NR_Pos           (2U)

+#define FMC_SDCRx_NR_Msk           (0x3UL << FMC_SDCRx_NR_Pos)                 /*!< 0x0000000C */

+#define FMC_SDCRx_NR               FMC_SDCRx_NR_Msk                            /*!<NR[1:0] bits (Number of row bits) */

+#define FMC_SDCRx_NR_0             (0x1UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000004 */

+#define FMC_SDCRx_NR_1             (0x2UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000008 */

+

+#define FMC_SDCRx_MWID_Pos         (4U)

+#define FMC_SDCRx_MWID_Msk         (0x3UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000030 */

+#define FMC_SDCRx_MWID             FMC_SDCRx_MWID_Msk                          /*!<NR[1:0] bits (Number of row bits) */

+#define FMC_SDCRx_MWID_0           (0x1UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000010 */

+#define FMC_SDCRx_MWID_1           (0x2UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000020 */

+

+#define FMC_SDCRx_NB_Pos           (6U)

+#define FMC_SDCRx_NB_Msk           (0x1UL << FMC_SDCRx_NB_Pos)                 /*!< 0x00000040 */

+#define FMC_SDCRx_NB               FMC_SDCRx_NB_Msk                            /*!<Number of internal bank */

+

+#define FMC_SDCRx_CAS_Pos          (7U)

+#define FMC_SDCRx_CAS_Msk          (0x3UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000180 */

+#define FMC_SDCRx_CAS              FMC_SDCRx_CAS_Msk                           /*!<CAS[1:0] bits (CAS latency) */

+#define FMC_SDCRx_CAS_0            (0x1UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000080 */

+#define FMC_SDCRx_CAS_1            (0x2UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000100 */

+

+#define FMC_SDCRx_WP_Pos           (9U)

+#define FMC_SDCRx_WP_Msk           (0x1UL << FMC_SDCRx_WP_Pos)                 /*!< 0x00000200 */

+#define FMC_SDCRx_WP               FMC_SDCRx_WP_Msk                            /*!<Write protection */

+

+#define FMC_SDCRx_SDCLK_Pos        (10U)

+#define FMC_SDCRx_SDCLK_Msk        (0x3UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000C00 */

+#define FMC_SDCRx_SDCLK            FMC_SDCRx_SDCLK_Msk                         /*!<SDRAM clock configuration */

+#define FMC_SDCRx_SDCLK_0          (0x1UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000400 */

+#define FMC_SDCRx_SDCLK_1          (0x2UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000800 */

+

+#define FMC_SDCRx_RBURST_Pos       (12U)

+#define FMC_SDCRx_RBURST_Msk       (0x1UL << FMC_SDCRx_RBURST_Pos)             /*!< 0x00001000 */

+#define FMC_SDCRx_RBURST           FMC_SDCRx_RBURST_Msk                        /*!<Read burst */

+

+#define FMC_SDCRx_RPIPE_Pos        (13U)

+#define FMC_SDCRx_RPIPE_Msk        (0x3UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00006000 */

+#define FMC_SDCRx_RPIPE            FMC_SDCRx_RPIPE_Msk                         /*!<Write protection */

+#define FMC_SDCRx_RPIPE_0          (0x1UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00002000 */

+#define FMC_SDCRx_RPIPE_1          (0x2UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00004000 */

+

+/******************  Bit definition for FMC_SDTRx(1,2) register  ******************/

+#define FMC_SDTRx_TMRD_Pos         (0U)

+#define FMC_SDTRx_TMRD_Msk         (0xFUL << FMC_SDTRx_TMRD_Pos)               /*!< 0x0000000F */

+#define FMC_SDTRx_TMRD             FMC_SDTRx_TMRD_Msk                          /*!<TMRD[3:0] bits (Load mode register to active) */

+#define FMC_SDTRx_TMRD_0           (0x1UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000001 */

+#define FMC_SDTRx_TMRD_1           (0x2UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000002 */

+#define FMC_SDTRx_TMRD_2           (0x4UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000004 */

+#define FMC_SDTRx_TMRD_3           (0x8UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000008 */

+

+#define FMC_SDTRx_TXSR_Pos         (4U)

+#define FMC_SDTRx_TXSR_Msk         (0xFUL << FMC_SDTRx_TXSR_Pos)               /*!< 0x000000F0 */

+#define FMC_SDTRx_TXSR             FMC_SDTRx_TXSR_Msk                          /*!<TXSR[3:0] bits (Exit self refresh) */

+#define FMC_SDTRx_TXSR_0           (0x1UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000010 */

+#define FMC_SDTRx_TXSR_1           (0x2UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000020 */

+#define FMC_SDTRx_TXSR_2           (0x4UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000040 */

+#define FMC_SDTRx_TXSR_3           (0x8UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000080 */

+

+#define FMC_SDTRx_TRAS_Pos         (8U)

+#define FMC_SDTRx_TRAS_Msk         (0xFUL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000F00 */

+#define FMC_SDTRx_TRAS             FMC_SDTRx_TRAS_Msk                          /*!<TRAS[3:0] bits (Self refresh time) */

+#define FMC_SDTRx_TRAS_0           (0x1UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000100 */

+#define FMC_SDTRx_TRAS_1           (0x2UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000200 */

+#define FMC_SDTRx_TRAS_2           (0x4UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000400 */

+#define FMC_SDTRx_TRAS_3           (0x8UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000800 */

+

+#define FMC_SDTRx_TRC_Pos          (12U)

+#define FMC_SDTRx_TRC_Msk          (0xFUL << FMC_SDTRx_TRC_Pos)                /*!< 0x0000F000 */

+#define FMC_SDTRx_TRC              FMC_SDTRx_TRC_Msk                           /*!<TRC[2:0] bits (Row cycle delay) */

+#define FMC_SDTRx_TRC_0            (0x1UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00001000 */

+#define FMC_SDTRx_TRC_1            (0x2UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00002000 */

+#define FMC_SDTRx_TRC_2            (0x4UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00004000 */

+

+#define FMC_SDTRx_TWR_Pos          (16U)

+#define FMC_SDTRx_TWR_Msk          (0xFUL << FMC_SDTRx_TWR_Pos)                /*!< 0x000F0000 */

+#define FMC_SDTRx_TWR              FMC_SDTRx_TWR_Msk                           /*!<TRC[2:0] bits (Write recovery delay) */

+#define FMC_SDTRx_TWR_0            (0x1UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00010000 */

+#define FMC_SDTRx_TWR_1            (0x2UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00020000 */

+#define FMC_SDTRx_TWR_2            (0x4UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00040000 */

+

+#define FMC_SDTRx_TRP_Pos          (20U)

+#define FMC_SDTRx_TRP_Msk          (0xFUL << FMC_SDTRx_TRP_Pos)                /*!< 0x00F00000 */

+#define FMC_SDTRx_TRP              FMC_SDTRx_TRP_Msk                           /*!<TRP[2:0] bits (Row precharge delay) */

+#define FMC_SDTRx_TRP_0            (0x1UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00100000 */

+#define FMC_SDTRx_TRP_1            (0x2UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00200000 */

+#define FMC_SDTRx_TRP_2            (0x4UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00400000 */

+

+#define FMC_SDTRx_TRCD_Pos         (24U)

+#define FMC_SDTRx_TRCD_Msk         (0xFUL << FMC_SDTRx_TRCD_Pos)               /*!< 0x0F000000 */

+#define FMC_SDTRx_TRCD             FMC_SDTRx_TRCD_Msk                          /*!<TRP[2:0] bits (Row to column delay) */

+#define FMC_SDTRx_TRCD_0           (0x1UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x01000000 */

+#define FMC_SDTRx_TRCD_1           (0x2UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x02000000 */

+#define FMC_SDTRx_TRCD_2           (0x4UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x04000000 */

+

+/******************  Bit definition for FMC_SDCMR register  ******************/

+#define FMC_SDCMR_MODE_Pos         (0U)

+#define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */

+#define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */

+#define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */

+#define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */

+#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */

+

+#define FMC_SDCMR_CTB2_Pos         (3U)

+#define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */

+#define FMC_SDCMR_CTB2             FMC_SDCMR_CTB2_Msk                          /*!<Command target 2 */

+

+#define FMC_SDCMR_CTB1_Pos         (4U)

+#define FMC_SDCMR_CTB1_Msk         (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */

+#define FMC_SDCMR_CTB1             FMC_SDCMR_CTB1_Msk                          /*!<Command target 1 */

+

+#define FMC_SDCMR_NRFS_Pos         (5U)

+#define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */

+#define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!<NRFS[3:0] bits (Number of auto-refresh) */

+#define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000020 */

+#define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000040 */

+#define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000080 */

+#define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000100 */

+

+#define FMC_SDCMR_MRD_Pos          (9U)

+#define FMC_SDCMR_MRD_Msk          (0x1FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */

+#define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!<MRD[12:0] bits (Mode register definition) */

+

+/******************  Bit definition for FMC_SDRTR register  ******************/

+#define FMC_SDRTR_CRE_Pos          (0U)

+#define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */

+#define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!<Clear refresh error flag */

+

+#define FMC_SDRTR_COUNT_Pos        (1U)

+#define FMC_SDRTR_COUNT_Msk        (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */

+#define FMC_SDRTR_COUNT            FMC_SDRTR_COUNT_Msk                         /*!<COUNT[12:0] bits (Refresh timer count) */

+

+#define FMC_SDRTR_REIE_Pos         (14U)

+#define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */

+#define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!<RES interupt enable */

+

+/******************  Bit definition for FMC_SDSR register  ******************/

+#define FMC_SDSR_RE_Pos            (0U)

+#define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */

+#define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!<Refresh error flag */

+

+#define FMC_SDSR_MODES1_Pos        (1U)

+#define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */

+#define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!<MODES1[1:0]bits (Status mode for bank 1) */

+#define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000002 */

+#define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000004 */

+

+#define FMC_SDSR_MODES2_Pos        (3U)

+#define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */

+#define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!<MODES2[1:0]bits (Status mode for bank 2) */

+#define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000008 */

+#define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000010 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            General Purpose I/O                             */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bits definition for GPIO_MODER register  *****************/

+#define GPIO_MODER_MODE0_Pos           (0U)

+#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */

+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk

+#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */

+#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */

+

+#define GPIO_MODER_MODE1_Pos           (2U)

+#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */

+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk

+#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */

+#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */

+

+#define GPIO_MODER_MODE2_Pos           (4U)

+#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */

+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk

+#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */

+#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */

+

+#define GPIO_MODER_MODE3_Pos           (6U)

+#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */

+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk

+#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */

+#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */

+

+#define GPIO_MODER_MODE4_Pos           (8U)

+#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */

+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk

+#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */

+#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */

+

+#define GPIO_MODER_MODE5_Pos           (10U)

+#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */

+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk

+#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */

+#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */

+

+#define GPIO_MODER_MODE6_Pos           (12U)

+#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */

+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk

+#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */

+#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */

+

+#define GPIO_MODER_MODE7_Pos           (14U)

+#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */

+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk

+#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */

+#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */

+

+#define GPIO_MODER_MODE8_Pos           (16U)

+#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */

+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk

+#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */

+#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */

+

+#define GPIO_MODER_MODE9_Pos           (18U)

+#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */

+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk

+#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */

+#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */

+

+#define GPIO_MODER_MODE10_Pos          (20U)

+#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */

+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk

+#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */

+#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */

+

+#define GPIO_MODER_MODE11_Pos          (22U)

+#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */

+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk

+#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */

+#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */

+

+#define GPIO_MODER_MODE12_Pos          (24U)

+#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */

+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk

+#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */

+#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */

+

+#define GPIO_MODER_MODE13_Pos          (26U)

+#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */

+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk

+#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */

+#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */

+

+#define GPIO_MODER_MODE14_Pos          (28U)

+#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */

+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk

+#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */

+#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */

+

+#define GPIO_MODER_MODE15_Pos          (30U)

+#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */

+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk

+#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */

+#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_OTYPER register  ****************/

+#define GPIO_OTYPER_OT0_Pos            (0U)

+#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */

+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk

+#define GPIO_OTYPER_OT1_Pos            (1U)

+#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */

+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk

+#define GPIO_OTYPER_OT2_Pos            (2U)

+#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */

+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk

+#define GPIO_OTYPER_OT3_Pos            (3U)

+#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */

+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk

+#define GPIO_OTYPER_OT4_Pos            (4U)

+#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */

+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk

+#define GPIO_OTYPER_OT5_Pos            (5U)

+#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */

+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk

+#define GPIO_OTYPER_OT6_Pos            (6U)

+#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */

+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk

+#define GPIO_OTYPER_OT7_Pos            (7U)

+#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */

+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk

+#define GPIO_OTYPER_OT8_Pos            (8U)

+#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */

+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk

+#define GPIO_OTYPER_OT9_Pos            (9U)

+#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */

+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk

+#define GPIO_OTYPER_OT10_Pos           (10U)

+#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */

+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk

+#define GPIO_OTYPER_OT11_Pos           (11U)

+#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */

+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk

+#define GPIO_OTYPER_OT12_Pos           (12U)

+#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */

+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk

+#define GPIO_OTYPER_OT13_Pos           (13U)

+#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */

+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk

+#define GPIO_OTYPER_OT14_Pos           (14U)

+#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */

+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk

+#define GPIO_OTYPER_OT15_Pos           (15U)

+#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */

+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk

+

+/******************  Bits definition for GPIO_OSPEEDR register  ***************/

+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)

+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */

+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk

+#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */

+#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */

+

+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)

+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */

+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk

+#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */

+#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */

+

+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)

+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */

+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk

+#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */

+#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */

+

+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)

+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */

+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk

+#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */

+#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */

+

+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)

+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */

+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk

+#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */

+#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */

+

+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)

+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */

+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk

+#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */

+#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */

+

+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)

+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */

+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk

+#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */

+#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */

+

+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)

+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */

+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk

+#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */

+#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */

+

+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)

+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */

+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk

+#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */

+#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */

+

+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)

+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */

+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk

+#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */

+#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */

+

+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)

+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */

+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk

+#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */

+#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */

+

+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)

+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */

+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk

+#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */

+#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */

+

+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)

+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */

+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk

+#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */

+#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */

+

+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)

+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */

+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk

+#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */

+#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */

+

+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)

+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */

+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk

+#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */

+#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */

+

+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)

+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */

+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk

+#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */

+#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_PUPDR register  *****************/

+#define GPIO_PUPDR_PUPD0_Pos           (0U)

+#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */

+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk

+#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */

+#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */

+

+#define GPIO_PUPDR_PUPD1_Pos           (2U)

+#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */

+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk

+#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */

+#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */

+

+#define GPIO_PUPDR_PUPD2_Pos           (4U)

+#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */

+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk

+#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */

+#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */

+

+#define GPIO_PUPDR_PUPD3_Pos           (6U)

+#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */

+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk

+#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */

+#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */

+

+#define GPIO_PUPDR_PUPD4_Pos           (8U)

+#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */

+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk

+#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */

+#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */

+

+#define GPIO_PUPDR_PUPD5_Pos           (10U)

+#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */

+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk

+#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */

+#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */

+

+#define GPIO_PUPDR_PUPD6_Pos           (12U)

+#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */

+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk

+#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */

+#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */

+

+#define GPIO_PUPDR_PUPD7_Pos           (14U)

+#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */

+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk

+#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */

+#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */

+

+#define GPIO_PUPDR_PUPD8_Pos           (16U)

+#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */

+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk

+#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */

+#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */

+

+#define GPIO_PUPDR_PUPD9_Pos           (18U)

+#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */

+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk

+#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */

+#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */

+

+#define GPIO_PUPDR_PUPD10_Pos          (20U)

+#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */

+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk

+#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */

+#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */

+

+#define GPIO_PUPDR_PUPD11_Pos          (22U)

+#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */

+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk

+#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */

+#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */

+

+#define GPIO_PUPDR_PUPD12_Pos          (24U)

+#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */

+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk

+#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */

+#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */

+

+#define GPIO_PUPDR_PUPD13_Pos          (26U)

+#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */

+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk

+#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */

+#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */

+

+#define GPIO_PUPDR_PUPD14_Pos          (28U)

+#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */

+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk

+#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */

+#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */

+

+#define GPIO_PUPDR_PUPD15_Pos          (30U)

+#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */

+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk

+#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */

+#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_IDR register  *******************/

+#define GPIO_IDR_ID0_Pos               (0U)

+#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */

+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk

+#define GPIO_IDR_ID1_Pos               (1U)

+#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */

+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk

+#define GPIO_IDR_ID2_Pos               (2U)

+#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */

+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk

+#define GPIO_IDR_ID3_Pos               (3U)

+#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */

+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk

+#define GPIO_IDR_ID4_Pos               (4U)

+#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */

+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk

+#define GPIO_IDR_ID5_Pos               (5U)

+#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */

+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk

+#define GPIO_IDR_ID6_Pos               (6U)

+#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */

+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk

+#define GPIO_IDR_ID7_Pos               (7U)

+#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */

+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk

+#define GPIO_IDR_ID8_Pos               (8U)

+#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */

+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk

+#define GPIO_IDR_ID9_Pos               (9U)

+#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */

+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk

+#define GPIO_IDR_ID10_Pos              (10U)

+#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */

+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk

+#define GPIO_IDR_ID11_Pos              (11U)

+#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */

+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk

+#define GPIO_IDR_ID12_Pos              (12U)

+#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */

+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk

+#define GPIO_IDR_ID13_Pos              (13U)

+#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */

+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk

+#define GPIO_IDR_ID14_Pos              (14U)

+#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */

+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk

+#define GPIO_IDR_ID15_Pos              (15U)

+#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */

+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk

+

+/******************  Bits definition for GPIO_ODR register  *******************/

+#define GPIO_ODR_OD0_Pos               (0U)

+#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */

+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk

+#define GPIO_ODR_OD1_Pos               (1U)

+#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */

+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk

+#define GPIO_ODR_OD2_Pos               (2U)

+#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */

+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk

+#define GPIO_ODR_OD3_Pos               (3U)

+#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */

+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk

+#define GPIO_ODR_OD4_Pos               (4U)

+#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */

+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk

+#define GPIO_ODR_OD5_Pos               (5U)

+#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */

+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk

+#define GPIO_ODR_OD6_Pos               (6U)

+#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */

+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk

+#define GPIO_ODR_OD7_Pos               (7U)

+#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */

+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk

+#define GPIO_ODR_OD8_Pos               (8U)

+#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */

+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk

+#define GPIO_ODR_OD9_Pos               (9U)

+#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */

+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk

+#define GPIO_ODR_OD10_Pos              (10U)

+#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */

+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk

+#define GPIO_ODR_OD11_Pos              (11U)

+#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */

+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk

+#define GPIO_ODR_OD12_Pos              (12U)

+#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */

+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk

+#define GPIO_ODR_OD13_Pos              (13U)

+#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */

+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk

+#define GPIO_ODR_OD14_Pos              (14U)

+#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */

+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk

+#define GPIO_ODR_OD15_Pos              (15U)

+#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */

+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk

+

+/******************  Bits definition for GPIO_BSRR register  ******************/

+#define GPIO_BSRR_BS0_Pos              (0U)

+#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */

+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk

+#define GPIO_BSRR_BS1_Pos              (1U)

+#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */

+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk

+#define GPIO_BSRR_BS2_Pos              (2U)

+#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */

+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk

+#define GPIO_BSRR_BS3_Pos              (3U)

+#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */

+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk

+#define GPIO_BSRR_BS4_Pos              (4U)

+#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */

+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk

+#define GPIO_BSRR_BS5_Pos              (5U)

+#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */

+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk

+#define GPIO_BSRR_BS6_Pos              (6U)

+#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */

+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk

+#define GPIO_BSRR_BS7_Pos              (7U)

+#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */

+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk

+#define GPIO_BSRR_BS8_Pos              (8U)

+#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */

+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk

+#define GPIO_BSRR_BS9_Pos              (9U)

+#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */

+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk

+#define GPIO_BSRR_BS10_Pos             (10U)

+#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */

+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk

+#define GPIO_BSRR_BS11_Pos             (11U)

+#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */

+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk

+#define GPIO_BSRR_BS12_Pos             (12U)

+#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */

+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk

+#define GPIO_BSRR_BS13_Pos             (13U)

+#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */

+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk

+#define GPIO_BSRR_BS14_Pos             (14U)

+#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */

+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk

+#define GPIO_BSRR_BS15_Pos             (15U)

+#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */

+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk

+#define GPIO_BSRR_BR0_Pos              (16U)

+#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */

+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk

+#define GPIO_BSRR_BR1_Pos              (17U)

+#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */

+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk

+#define GPIO_BSRR_BR2_Pos              (18U)

+#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */

+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk

+#define GPIO_BSRR_BR3_Pos              (19U)

+#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */

+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk

+#define GPIO_BSRR_BR4_Pos              (20U)

+#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */

+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk

+#define GPIO_BSRR_BR5_Pos              (21U)

+#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */

+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk

+#define GPIO_BSRR_BR6_Pos              (22U)

+#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */

+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk

+#define GPIO_BSRR_BR7_Pos              (23U)

+#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */

+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk

+#define GPIO_BSRR_BR8_Pos              (24U)

+#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */

+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk

+#define GPIO_BSRR_BR9_Pos              (25U)

+#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */

+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk

+#define GPIO_BSRR_BR10_Pos             (26U)

+#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */

+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk

+#define GPIO_BSRR_BR11_Pos             (27U)

+#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */

+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk

+#define GPIO_BSRR_BR12_Pos             (28U)

+#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */

+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk

+#define GPIO_BSRR_BR13_Pos             (29U)

+#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */

+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk

+#define GPIO_BSRR_BR14_Pos             (30U)

+#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */

+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk

+#define GPIO_BSRR_BR15_Pos             (31U)

+#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */

+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk

+

+/****************** Bit definition for GPIO_LCKR register *********************/

+#define GPIO_LCKR_LCK0_Pos             (0U)

+#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */

+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk

+#define GPIO_LCKR_LCK1_Pos             (1U)

+#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */

+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk

+#define GPIO_LCKR_LCK2_Pos             (2U)

+#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */

+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk

+#define GPIO_LCKR_LCK3_Pos             (3U)

+#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */

+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk

+#define GPIO_LCKR_LCK4_Pos             (4U)

+#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */

+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk

+#define GPIO_LCKR_LCK5_Pos             (5U)

+#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */

+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk

+#define GPIO_LCKR_LCK6_Pos             (6U)

+#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */

+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk

+#define GPIO_LCKR_LCK7_Pos             (7U)

+#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */

+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk

+#define GPIO_LCKR_LCK8_Pos             (8U)

+#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */

+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk

+#define GPIO_LCKR_LCK9_Pos             (9U)

+#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */

+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk

+#define GPIO_LCKR_LCK10_Pos            (10U)

+#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */

+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk

+#define GPIO_LCKR_LCK11_Pos            (11U)

+#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */

+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk

+#define GPIO_LCKR_LCK12_Pos            (12U)

+#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */

+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk

+#define GPIO_LCKR_LCK13_Pos            (13U)

+#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */

+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk

+#define GPIO_LCKR_LCK14_Pos            (14U)

+#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */

+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk

+#define GPIO_LCKR_LCK15_Pos            (15U)

+#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */

+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk

+#define GPIO_LCKR_LCKK_Pos             (16U)

+#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */

+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk

+

+/****************** Bit definition for GPIO_AFRL register  ********************/

+#define GPIO_AFRL_AFSEL0_Pos           (0U)

+#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */

+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk

+#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */

+#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */

+#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */

+#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */

+#define GPIO_AFRL_AFSEL1_Pos           (4U)

+#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */

+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk

+#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */

+#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */

+#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */

+#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */

+#define GPIO_AFRL_AFSEL2_Pos           (8U)

+#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */

+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk

+#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */

+#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */

+#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */

+#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */

+#define GPIO_AFRL_AFSEL3_Pos           (12U)

+#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */

+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk

+#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */

+#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */

+#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */

+#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */

+#define GPIO_AFRL_AFSEL4_Pos           (16U)

+#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */

+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk

+#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */

+#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */

+#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */

+#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */

+#define GPIO_AFRL_AFSEL5_Pos           (20U)

+#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */

+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk

+#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */

+#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */

+#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */

+#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */

+#define GPIO_AFRL_AFSEL6_Pos           (24U)

+#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */

+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk

+#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */

+#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */

+#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */

+#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */

+#define GPIO_AFRL_AFSEL7_Pos           (28U)

+#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */

+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk

+#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */

+#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */

+#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */

+#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */

+

+/* Legacy defines */

+#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0

+#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1

+#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2

+#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3

+#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4

+#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5

+#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6

+#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7

+

+/****************** Bit definition for GPIO_AFRH register  ********************/

+#define GPIO_AFRH_AFSEL8_Pos           (0U)

+#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */

+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk

+#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */

+#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */

+#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */

+#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */

+#define GPIO_AFRH_AFSEL9_Pos           (4U)

+#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */

+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk

+#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */

+#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */

+#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */

+#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */

+#define GPIO_AFRH_AFSEL10_Pos          (8U)

+#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */

+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk

+#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */

+#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */

+#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */

+#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */

+#define GPIO_AFRH_AFSEL11_Pos          (12U)

+#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */

+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk

+#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */

+#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */

+#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */

+#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */

+#define GPIO_AFRH_AFSEL12_Pos          (16U)

+#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */

+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk

+#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */

+#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */

+#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */

+#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */

+#define GPIO_AFRH_AFSEL13_Pos          (20U)

+#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */

+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk

+#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */

+#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */

+#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */

+#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */

+#define GPIO_AFRH_AFSEL14_Pos          (24U)

+#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */

+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk

+#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */

+#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */

+#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */

+#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */

+#define GPIO_AFRH_AFSEL15_Pos          (28U)

+#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */

+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk

+#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */

+#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */

+#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */

+#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */

+

+/* Legacy defines */

+#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8

+#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9

+#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10

+#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11

+#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12

+#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13

+#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14

+#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15

+

+/******************************************************************************/

+/*                                                                            */

+/*                        HSEM HW Semaphore                                   */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for HSEM_R register  ********************/

+#define HSEM_R_PROCID_Pos         (0U)

+#define HSEM_R_PROCID_Msk         (0xFFUL << HSEM_R_PROCID_Pos)                /*!< 0x000000FF */

+#define HSEM_R_PROCID             HSEM_R_PROCID_Msk                            /*!<Semaphore ProcessID */

+#define HSEM_R_COREID_Pos         (8U)

+#define HSEM_R_COREID_Msk         (0xFFUL << HSEM_R_COREID_Pos)                /*!< 0x0000FF00 */

+#define HSEM_R_COREID             HSEM_R_COREID_Msk                            /*!<Semaphore CoreID.   */

+#define HSEM_R_LOCK_Pos           (31U)

+#define HSEM_R_LOCK_Msk           (0x1UL << HSEM_R_LOCK_Pos)                   /*!< 0x80000000 */

+#define HSEM_R_LOCK               HSEM_R_LOCK_Msk                              /*!<Lock indication.    */

+

+/********************  Bit definition for HSEM_RLR register  ******************/

+#define HSEM_RLR_PROCID_Pos       (0U)

+#define HSEM_RLR_PROCID_Msk       (0xFFUL << HSEM_RLR_PROCID_Pos)              /*!< 0x000000FF */

+#define HSEM_RLR_PROCID           HSEM_RLR_PROCID_Msk                          /*!<Semaphore ProcessID */

+#define HSEM_RLR_COREID_Pos       (8U)

+#define HSEM_RLR_COREID_Msk       (0xFFUL << HSEM_RLR_COREID_Pos)              /*!< 0x0000FF00 */

+#define HSEM_RLR_COREID           HSEM_RLR_COREID_Msk                          /*!<Semaphore CoreID.   */

+#define HSEM_RLR_LOCK_Pos         (31U)

+#define HSEM_RLR_LOCK_Msk         (0x1UL << HSEM_RLR_LOCK_Pos)                 /*!< 0x80000000 */

+#define HSEM_RLR_LOCK             HSEM_RLR_LOCK_Msk                            /*!<Lock indication.    */

+

+/********************  Bit definition for HSEM_C1IER register  *****************/

+#define HSEM_C1IER_ISE0_Pos       (0U)

+#define HSEM_C1IER_ISE0_Msk       (0x1UL << HSEM_C1IER_ISE0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1IER_ISE0           HSEM_C1IER_ISE0_Msk                          /*!<semaphore 0 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE1_Pos       (1U)

+#define HSEM_C1IER_ISE1_Msk       (0x1UL << HSEM_C1IER_ISE1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1IER_ISE1           HSEM_C1IER_ISE1_Msk                          /*!<semaphore 1 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE2_Pos       (2U)

+#define HSEM_C1IER_ISE2_Msk       (0x1UL << HSEM_C1IER_ISE2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1IER_ISE2           HSEM_C1IER_ISE2_Msk                          /*!<semaphore 2 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE3_Pos       (3U)

+#define HSEM_C1IER_ISE3_Msk       (0x1UL << HSEM_C1IER_ISE3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1IER_ISE3           HSEM_C1IER_ISE3_Msk                          /*!<semaphore 3 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE4_Pos       (4U)

+#define HSEM_C1IER_ISE4_Msk       (0x1UL << HSEM_C1IER_ISE4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1IER_ISE4           HSEM_C1IER_ISE4_Msk                          /*!<semaphore 4 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE5_Pos       (5U)

+#define HSEM_C1IER_ISE5_Msk       (0x1UL << HSEM_C1IER_ISE5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1IER_ISE5           HSEM_C1IER_ISE5_Msk                          /*!<semaphore 5 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE6_Pos       (6U)

+#define HSEM_C1IER_ISE6_Msk       (0x1UL << HSEM_C1IER_ISE6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1IER_ISE6           HSEM_C1IER_ISE6_Msk                          /*!<semaphore 6 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE7_Pos       (7U)

+#define HSEM_C1IER_ISE7_Msk       (0x1UL << HSEM_C1IER_ISE7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1IER_ISE7           HSEM_C1IER_ISE7_Msk                          /*!<semaphore 7 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE8_Pos       (8U)

+#define HSEM_C1IER_ISE8_Msk       (0x1UL << HSEM_C1IER_ISE8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1IER_ISE8           HSEM_C1IER_ISE8_Msk                          /*!<semaphore 8 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE9_Pos       (9U)

+#define HSEM_C1IER_ISE9_Msk       (0x1UL << HSEM_C1IER_ISE9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1IER_ISE9           HSEM_C1IER_ISE9_Msk                          /*!<semaphore 9 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE10_Pos      (10U)

+#define HSEM_C1IER_ISE10_Msk      (0x1UL << HSEM_C1IER_ISE10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1IER_ISE10          HSEM_C1IER_ISE10_Msk                         /*!<semaphore 10 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE11_Pos      (11U)

+#define HSEM_C1IER_ISE11_Msk      (0x1UL << HSEM_C1IER_ISE11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1IER_ISE11          HSEM_C1IER_ISE11_Msk                         /*!<semaphore 11 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE12_Pos      (12U)

+#define HSEM_C1IER_ISE12_Msk      (0x1UL << HSEM_C1IER_ISE12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1IER_ISE12          HSEM_C1IER_ISE12_Msk                         /*!<semaphore 12 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE13_Pos      (13U)

+#define HSEM_C1IER_ISE13_Msk      (0x1UL << HSEM_C1IER_ISE13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1IER_ISE13          HSEM_C1IER_ISE13_Msk                         /*!<semaphore 13 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE14_Pos      (14U)

+#define HSEM_C1IER_ISE14_Msk      (0x1UL << HSEM_C1IER_ISE14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1IER_ISE14          HSEM_C1IER_ISE14_Msk                         /*!<semaphore 14 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE15_Pos      (15U)

+#define HSEM_C1IER_ISE15_Msk      (0x1UL << HSEM_C1IER_ISE15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1IER_ISE15          HSEM_C1IER_ISE15_Msk                         /*!<semaphore 15 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE16_Pos      (16U)

+#define HSEM_C1IER_ISE16_Msk      (0x1UL << HSEM_C1IER_ISE16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1IER_ISE16          HSEM_C1IER_ISE16_Msk                         /*!<semaphore 16 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE17_Pos      (17U)

+#define HSEM_C1IER_ISE17_Msk      (0x1UL << HSEM_C1IER_ISE17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1IER_ISE17          HSEM_C1IER_ISE17_Msk                         /*!<semaphore 17 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE18_Pos      (18U)

+#define HSEM_C1IER_ISE18_Msk      (0x1UL << HSEM_C1IER_ISE18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1IER_ISE18          HSEM_C1IER_ISE18_Msk                         /*!<semaphore 18 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE19_Pos      (19U)

+#define HSEM_C1IER_ISE19_Msk      (0x1UL << HSEM_C1IER_ISE19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1IER_ISE19          HSEM_C1IER_ISE19_Msk                         /*!<semaphore 19 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE20_Pos      (20U)

+#define HSEM_C1IER_ISE20_Msk      (0x1UL << HSEM_C1IER_ISE20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1IER_ISE20          HSEM_C1IER_ISE20_Msk                         /*!<semaphore 20 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE21_Pos      (21U)

+#define HSEM_C1IER_ISE21_Msk      (0x1UL << HSEM_C1IER_ISE21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1IER_ISE21          HSEM_C1IER_ISE21_Msk                         /*!<semaphore 21 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE22_Pos      (22U)

+#define HSEM_C1IER_ISE22_Msk      (0x1UL << HSEM_C1IER_ISE22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1IER_ISE22          HSEM_C1IER_ISE22_Msk                         /*!<semaphore 22 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE23_Pos      (23U)

+#define HSEM_C1IER_ISE23_Msk      (0x1UL << HSEM_C1IER_ISE23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1IER_ISE23          HSEM_C1IER_ISE23_Msk                         /*!<semaphore 23 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE24_Pos      (24U)

+#define HSEM_C1IER_ISE24_Msk      (0x1UL << HSEM_C1IER_ISE24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1IER_ISE24          HSEM_C1IER_ISE24_Msk                         /*!<semaphore 24 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE25_Pos      (25U)

+#define HSEM_C1IER_ISE25_Msk      (0x1UL << HSEM_C1IER_ISE25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1IER_ISE25          HSEM_C1IER_ISE25_Msk                         /*!<semaphore 25 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE26_Pos      (26U)

+#define HSEM_C1IER_ISE26_Msk      (0x1UL << HSEM_C1IER_ISE26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1IER_ISE26          HSEM_C1IER_ISE26_Msk                         /*!<semaphore 26 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE27_Pos      (27U)

+#define HSEM_C1IER_ISE27_Msk      (0x1UL << HSEM_C1IER_ISE27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1IER_ISE27          HSEM_C1IER_ISE27_Msk                         /*!<semaphore 27 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE28_Pos      (28U)

+#define HSEM_C1IER_ISE28_Msk      (0x1UL << HSEM_C1IER_ISE28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1IER_ISE28          HSEM_C1IER_ISE28_Msk                         /*!<semaphore 28 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE29_Pos      (29U)

+#define HSEM_C1IER_ISE29_Msk      (0x1UL << HSEM_C1IER_ISE29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1IER_ISE29          HSEM_C1IER_ISE29_Msk                         /*!<semaphore 29 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE30_Pos      (30U)

+#define HSEM_C1IER_ISE30_Msk      (0x1UL << HSEM_C1IER_ISE30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1IER_ISE30          HSEM_C1IER_ISE30_Msk                         /*!<semaphore 30 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE31_Pos      (31U)

+#define HSEM_C1IER_ISE31_Msk      (0x1UL << HSEM_C1IER_ISE31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1IER_ISE31          HSEM_C1IER_ISE31_Msk                         /*!<semaphore 31 interrupt 0 enable bit. */

+

+/********************  Bit definition for HSEM_C1ICR register  *****************/

+#define HSEM_C1ICR_ISC0_Pos       (0U)

+#define HSEM_C1ICR_ISC0_Msk       (0x1UL << HSEM_C1ICR_ISC0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1ICR_ISC0           HSEM_C1ICR_ISC0_Msk                          /*!<semaphore 0 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC1_Pos       (1U)

+#define HSEM_C1ICR_ISC1_Msk       (0x1UL << HSEM_C1ICR_ISC1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1ICR_ISC1           HSEM_C1ICR_ISC1_Msk                          /*!<semaphore 1 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC2_Pos       (2U)

+#define HSEM_C1ICR_ISC2_Msk       (0x1UL << HSEM_C1ICR_ISC2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1ICR_ISC2           HSEM_C1ICR_ISC2_Msk                          /*!<semaphore 2 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC3_Pos       (3U)

+#define HSEM_C1ICR_ISC3_Msk       (0x1UL << HSEM_C1ICR_ISC3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1ICR_ISC3           HSEM_C1ICR_ISC3_Msk                          /*!<semaphore 3 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC4_Pos       (4U)

+#define HSEM_C1ICR_ISC4_Msk       (0x1UL << HSEM_C1ICR_ISC4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1ICR_ISC4           HSEM_C1ICR_ISC4_Msk                          /*!<semaphore 4 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC5_Pos       (5U)

+#define HSEM_C1ICR_ISC5_Msk       (0x1UL << HSEM_C1ICR_ISC5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1ICR_ISC5           HSEM_C1ICR_ISC5_Msk                          /*!<semaphore 5 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC6_Pos       (6U)

+#define HSEM_C1ICR_ISC6_Msk       (0x1UL << HSEM_C1ICR_ISC6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1ICR_ISC6           HSEM_C1ICR_ISC6_Msk                          /*!<semaphore 6 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC7_Pos       (7U)

+#define HSEM_C1ICR_ISC7_Msk       (0x1UL << HSEM_C1ICR_ISC7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1ICR_ISC7           HSEM_C1ICR_ISC7_Msk                          /*!<semaphore 7 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC8_Pos       (8U)

+#define HSEM_C1ICR_ISC8_Msk       (0x1UL << HSEM_C1ICR_ISC8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1ICR_ISC8           HSEM_C1ICR_ISC8_Msk                          /*!<semaphore 8 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC9_Pos       (9U)

+#define HSEM_C1ICR_ISC9_Msk       (0x1UL << HSEM_C1ICR_ISC9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1ICR_ISC9           HSEM_C1ICR_ISC9_Msk                          /*!<semaphore 9 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC10_Pos      (10U)

+#define HSEM_C1ICR_ISC10_Msk      (0x1UL << HSEM_C1ICR_ISC10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1ICR_ISC10          HSEM_C1ICR_ISC10_Msk                         /*!<semaphore 10 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC11_Pos      (11U)

+#define HSEM_C1ICR_ISC11_Msk      (0x1UL << HSEM_C1ICR_ISC11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1ICR_ISC11          HSEM_C1ICR_ISC11_Msk                         /*!<semaphore 11 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC12_Pos      (12U)

+#define HSEM_C1ICR_ISC12_Msk      (0x1UL << HSEM_C1ICR_ISC12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1ICR_ISC12          HSEM_C1ICR_ISC12_Msk                         /*!<semaphore 12 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC13_Pos      (13U)

+#define HSEM_C1ICR_ISC13_Msk      (0x1UL << HSEM_C1ICR_ISC13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1ICR_ISC13          HSEM_C1ICR_ISC13_Msk                         /*!<semaphore 13 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC14_Pos      (14U)

+#define HSEM_C1ICR_ISC14_Msk      (0x1UL << HSEM_C1ICR_ISC14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1ICR_ISC14          HSEM_C1ICR_ISC14_Msk                         /*!<semaphore 14 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC15_Pos      (15U)

+#define HSEM_C1ICR_ISC15_Msk      (0x1UL << HSEM_C1ICR_ISC15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1ICR_ISC15          HSEM_C1ICR_ISC15_Msk                         /*!<semaphore 15 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC16_Pos      (16U)

+#define HSEM_C1ICR_ISC16_Msk      (0x1UL << HSEM_C1ICR_ISC16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1ICR_ISC16          HSEM_C1ICR_ISC16_Msk                         /*!<semaphore 16 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC17_Pos      (17U)

+#define HSEM_C1ICR_ISC17_Msk      (0x1UL << HSEM_C1ICR_ISC17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1ICR_ISC17          HSEM_C1ICR_ISC17_Msk                         /*!<semaphore 17 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC18_Pos      (18U)

+#define HSEM_C1ICR_ISC18_Msk      (0x1UL << HSEM_C1ICR_ISC18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1ICR_ISC18          HSEM_C1ICR_ISC18_Msk                         /*!<semaphore 18 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC19_Pos      (19U)

+#define HSEM_C1ICR_ISC19_Msk      (0x1UL << HSEM_C1ICR_ISC19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1ICR_ISC19          HSEM_C1ICR_ISC19_Msk                         /*!<semaphore 19 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC20_Pos      (20U)

+#define HSEM_C1ICR_ISC20_Msk      (0x1UL << HSEM_C1ICR_ISC20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1ICR_ISC20          HSEM_C1ICR_ISC20_Msk                         /*!<semaphore 20 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC21_Pos      (21U)

+#define HSEM_C1ICR_ISC21_Msk      (0x1UL << HSEM_C1ICR_ISC21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1ICR_ISC21          HSEM_C1ICR_ISC21_Msk                         /*!<semaphore 21 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC22_Pos      (22U)

+#define HSEM_C1ICR_ISC22_Msk      (0x1UL << HSEM_C1ICR_ISC22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1ICR_ISC22          HSEM_C1ICR_ISC22_Msk                         /*!<semaphore 22 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC23_Pos      (23U)

+#define HSEM_C1ICR_ISC23_Msk      (0x1UL << HSEM_C1ICR_ISC23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1ICR_ISC23          HSEM_C1ICR_ISC23_Msk                         /*!<semaphore 23 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC24_Pos      (24U)

+#define HSEM_C1ICR_ISC24_Msk      (0x1UL << HSEM_C1ICR_ISC24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1ICR_ISC24          HSEM_C1ICR_ISC24_Msk                         /*!<semaphore 24 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC25_Pos      (25U)

+#define HSEM_C1ICR_ISC25_Msk      (0x1UL << HSEM_C1ICR_ISC25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1ICR_ISC25          HSEM_C1ICR_ISC25_Msk                         /*!<semaphore 25 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC26_Pos      (26U)

+#define HSEM_C1ICR_ISC26_Msk      (0x1UL << HSEM_C1ICR_ISC26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1ICR_ISC26          HSEM_C1ICR_ISC26_Msk                         /*!<semaphore 26 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC27_Pos      (27U)

+#define HSEM_C1ICR_ISC27_Msk      (0x1UL << HSEM_C1ICR_ISC27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1ICR_ISC27          HSEM_C1ICR_ISC27_Msk                         /*!<semaphore 27 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC28_Pos      (28U)

+#define HSEM_C1ICR_ISC28_Msk      (0x1UL << HSEM_C1ICR_ISC28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1ICR_ISC28          HSEM_C1ICR_ISC28_Msk                         /*!<semaphore 28 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC29_Pos      (29U)

+#define HSEM_C1ICR_ISC29_Msk      (0x1UL << HSEM_C1ICR_ISC29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1ICR_ISC29          HSEM_C1ICR_ISC29_Msk                         /*!<semaphore 29 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC30_Pos      (30U)

+#define HSEM_C1ICR_ISC30_Msk      (0x1UL << HSEM_C1ICR_ISC30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1ICR_ISC30          HSEM_C1ICR_ISC30_Msk                         /*!<semaphore 30 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC31_Pos      (31U)

+#define HSEM_C1ICR_ISC31_Msk      (0x1UL << HSEM_C1ICR_ISC31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1ICR_ISC31          HSEM_C1ICR_ISC31_Msk                         /*!<semaphore 31 interrupt 0 clear bit. */

+

+/********************  Bit definition for HSEM_C1ISR register  *****************/

+#define HSEM_C1ISR_ISF0_Pos       (0U)

+#define HSEM_C1ISR_ISF0_Msk       (0x1UL << HSEM_C1ISR_ISF0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1ISR_ISF0           HSEM_C1ISR_ISF0_Msk                          /*!<semaphore 0 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF1_Pos       (1U)

+#define HSEM_C1ISR_ISF1_Msk       (0x1UL << HSEM_C1ISR_ISF1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1ISR_ISF1           HSEM_C1ISR_ISF1_Msk                          /*!<semaphore 1 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF2_Pos       (2U)

+#define HSEM_C1ISR_ISF2_Msk       (0x1UL << HSEM_C1ISR_ISF2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1ISR_ISF2           HSEM_C1ISR_ISF2_Msk                          /*!<semaphore 2 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF3_Pos       (3U)

+#define HSEM_C1ISR_ISF3_Msk       (0x1UL << HSEM_C1ISR_ISF3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1ISR_ISF3           HSEM_C1ISR_ISF3_Msk                          /*!<semaphore 3 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF4_Pos       (4U)

+#define HSEM_C1ISR_ISF4_Msk       (0x1UL << HSEM_C1ISR_ISF4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1ISR_ISF4           HSEM_C1ISR_ISF4_Msk                          /*!<semaphore 4 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF5_Pos       (5U)

+#define HSEM_C1ISR_ISF5_Msk       (0x1UL << HSEM_C1ISR_ISF5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1ISR_ISF5           HSEM_C1ISR_ISF5_Msk                          /*!<semaphore 5 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF6_Pos       (6U)

+#define HSEM_C1ISR_ISF6_Msk       (0x1UL << HSEM_C1ISR_ISF6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1ISR_ISF6           HSEM_C1ISR_ISF6_Msk                          /*!<semaphore 6 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF7_Pos       (7U)

+#define HSEM_C1ISR_ISF7_Msk       (0x1UL << HSEM_C1ISR_ISF7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1ISR_ISF7           HSEM_C1ISR_ISF7_Msk                          /*!<semaphore 7 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF8_Pos       (8U)

+#define HSEM_C1ISR_ISF8_Msk       (0x1UL << HSEM_C1ISR_ISF8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1ISR_ISF8           HSEM_C1ISR_ISF8_Msk                          /*!<semaphore 8 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF9_Pos       (9U)

+#define HSEM_C1ISR_ISF9_Msk       (0x1UL << HSEM_C1ISR_ISF9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1ISR_ISF9           HSEM_C1ISR_ISF9_Msk                          /*!<semaphore 9 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF10_Pos      (10U)

+#define HSEM_C1ISR_ISF10_Msk      (0x1UL << HSEM_C1ISR_ISF10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1ISR_ISF10          HSEM_C1ISR_ISF10_Msk                         /*!<semaphore 10 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF11_Pos      (11U)

+#define HSEM_C1ISR_ISF11_Msk      (0x1UL << HSEM_C1ISR_ISF11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1ISR_ISF11          HSEM_C1ISR_ISF11_Msk                         /*!<semaphore 11 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF12_Pos      (12U)

+#define HSEM_C1ISR_ISF12_Msk      (0x1UL << HSEM_C1ISR_ISF12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1ISR_ISF12          HSEM_C1ISR_ISF12_Msk                         /*!<semaphore 12 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF13_Pos      (13U)

+#define HSEM_C1ISR_ISF13_Msk      (0x1UL << HSEM_C1ISR_ISF13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1ISR_ISF13          HSEM_C1ISR_ISF13_Msk                         /*!<semaphore 13 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF14_Pos      (14U)

+#define HSEM_C1ISR_ISF14_Msk      (0x1UL << HSEM_C1ISR_ISF14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1ISR_ISF14          HSEM_C1ISR_ISF14_Msk                         /*!<semaphore 14 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF15_Pos      (15U)

+#define HSEM_C1ISR_ISF15_Msk      (0x1UL << HSEM_C1ISR_ISF15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1ISR_ISF15          HSEM_C1ISR_ISF15_Msk                         /*!<semaphore 15 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF16_Pos      (16U)

+#define HSEM_C1ISR_ISF16_Msk      (0x1UL << HSEM_C1ISR_ISF16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1ISR_ISF16          HSEM_C1ISR_ISF16_Msk                         /*!<semaphore 16 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF17_Pos      (17U)

+#define HSEM_C1ISR_ISF17_Msk      (0x1UL << HSEM_C1ISR_ISF17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1ISR_ISF17          HSEM_C1ISR_ISF17_Msk                         /*!<semaphore 17 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF18_Pos      (18U)

+#define HSEM_C1ISR_ISF18_Msk      (0x1UL << HSEM_C1ISR_ISF18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1ISR_ISF18          HSEM_C1ISR_ISF18_Msk                         /*!<semaphore 18 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF19_Pos      (19U)

+#define HSEM_C1ISR_ISF19_Msk      (0x1UL << HSEM_C1ISR_ISF19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1ISR_ISF19          HSEM_C1ISR_ISF19_Msk                         /*!<semaphore 19 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF20_Pos      (20U)

+#define HSEM_C1ISR_ISF20_Msk      (0x1UL << HSEM_C1ISR_ISF20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1ISR_ISF20          HSEM_C1ISR_ISF20_Msk                         /*!<semaphore 20 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF21_Pos      (21U)

+#define HSEM_C1ISR_ISF21_Msk      (0x1UL << HSEM_C1ISR_ISF21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1ISR_ISF21          HSEM_C1ISR_ISF21_Msk                         /*!<semaphore 21 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF22_Pos      (22U)

+#define HSEM_C1ISR_ISF22_Msk      (0x1UL << HSEM_C1ISR_ISF22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1ISR_ISF22          HSEM_C1ISR_ISF22_Msk                         /*!<semaphore 22 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF23_Pos      (23U)

+#define HSEM_C1ISR_ISF23_Msk      (0x1UL << HSEM_C1ISR_ISF23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1ISR_ISF23          HSEM_C1ISR_ISF23_Msk                         /*!<semaphore 23 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF24_Pos      (24U)

+#define HSEM_C1ISR_ISF24_Msk      (0x1UL << HSEM_C1ISR_ISF24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1ISR_ISF24          HSEM_C1ISR_ISF24_Msk                         /*!<semaphore 24 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF25_Pos      (25U)

+#define HSEM_C1ISR_ISF25_Msk      (0x1UL << HSEM_C1ISR_ISF25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1ISR_ISF25          HSEM_C1ISR_ISF25_Msk                         /*!<semaphore 25 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF26_Pos      (26U)

+#define HSEM_C1ISR_ISF26_Msk      (0x1UL << HSEM_C1ISR_ISF26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1ISR_ISF26          HSEM_C1ISR_ISF26_Msk                         /*!<semaphore 26 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF27_Pos      (27U)

+#define HSEM_C1ISR_ISF27_Msk      (0x1UL << HSEM_C1ISR_ISF27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1ISR_ISF27          HSEM_C1ISR_ISF27_Msk                         /*!<semaphore 27 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF28_Pos      (28U)

+#define HSEM_C1ISR_ISF28_Msk      (0x1UL << HSEM_C1ISR_ISF28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1ISR_ISF28          HSEM_C1ISR_ISF28_Msk                         /*!<semaphore 28 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF29_Pos      (29U)

+#define HSEM_C1ISR_ISF29_Msk      (0x1UL << HSEM_C1ISR_ISF29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1ISR_ISF29          HSEM_C1ISR_ISF29_Msk                         /*!<semaphore 29 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF30_Pos      (30U)

+#define HSEM_C1ISR_ISF30_Msk      (0x1UL << HSEM_C1ISR_ISF30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1ISR_ISF30          HSEM_C1ISR_ISF30_Msk                         /*!<semaphore 30 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF31_Pos      (31U)

+#define HSEM_C1ISR_ISF31_Msk      (0x1UL << HSEM_C1ISR_ISF31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1ISR_ISF31          HSEM_C1ISR_ISF31_Msk                         /*!<semaphore 31 interrupt 0 status bit. */

+

+/********************  Bit definition for HSEM_C1MISR register  *****************/

+#define HSEM_C1MISR_MISF0_Pos     (0U)

+#define HSEM_C1MISR_MISF0_Msk     (0x1UL << HSEM_C1MISR_MISF0_Pos)             /*!< 0x00000001 */

+#define HSEM_C1MISR_MISF0         HSEM_C1MISR_MISF0_Msk                        /*!<semaphore 0 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF1_Pos     (1U)

+#define HSEM_C1MISR_MISF1_Msk     (0x1UL << HSEM_C1MISR_MISF1_Pos)             /*!< 0x00000002 */

+#define HSEM_C1MISR_MISF1         HSEM_C1MISR_MISF1_Msk                        /*!<semaphore 1 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF2_Pos     (2U)

+#define HSEM_C1MISR_MISF2_Msk     (0x1UL << HSEM_C1MISR_MISF2_Pos)             /*!< 0x00000004 */

+#define HSEM_C1MISR_MISF2         HSEM_C1MISR_MISF2_Msk                        /*!<semaphore 2 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF3_Pos     (3U)

+#define HSEM_C1MISR_MISF3_Msk     (0x1UL << HSEM_C1MISR_MISF3_Pos)             /*!< 0x00000008 */

+#define HSEM_C1MISR_MISF3         HSEM_C1MISR_MISF3_Msk                        /*!<semaphore 3 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF4_Pos     (4U)

+#define HSEM_C1MISR_MISF4_Msk     (0x1UL << HSEM_C1MISR_MISF4_Pos)             /*!< 0x00000010 */

+#define HSEM_C1MISR_MISF4         HSEM_C1MISR_MISF4_Msk                        /*!<semaphore 4 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF5_Pos     (5U)

+#define HSEM_C1MISR_MISF5_Msk     (0x1UL << HSEM_C1MISR_MISF5_Pos)             /*!< 0x00000020 */

+#define HSEM_C1MISR_MISF5         HSEM_C1MISR_MISF5_Msk                        /*!<semaphore 5 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF6_Pos     (6U)

+#define HSEM_C1MISR_MISF6_Msk     (0x1UL << HSEM_C1MISR_MISF6_Pos)             /*!< 0x00000040 */

+#define HSEM_C1MISR_MISF6         HSEM_C1MISR_MISF6_Msk                        /*!<semaphore 6 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF7_Pos     (7U)

+#define HSEM_C1MISR_MISF7_Msk     (0x1UL << HSEM_C1MISR_MISF7_Pos)             /*!< 0x00000080 */

+#define HSEM_C1MISR_MISF7         HSEM_C1MISR_MISF7_Msk                        /*!<semaphore 7 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF8_Pos     (8U)

+#define HSEM_C1MISR_MISF8_Msk     (0x1UL << HSEM_C1MISR_MISF8_Pos)             /*!< 0x00000100 */

+#define HSEM_C1MISR_MISF8         HSEM_C1MISR_MISF8_Msk                        /*!<semaphore 8 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF9_Pos     (9U)

+#define HSEM_C1MISR_MISF9_Msk     (0x1UL << HSEM_C1MISR_MISF9_Pos)             /*!< 0x00000200 */

+#define HSEM_C1MISR_MISF9         HSEM_C1MISR_MISF9_Msk                        /*!<semaphore 9 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF10_Pos    (10U)

+#define HSEM_C1MISR_MISF10_Msk    (0x1UL << HSEM_C1MISR_MISF10_Pos)            /*!< 0x00000400 */

+#define HSEM_C1MISR_MISF10        HSEM_C1MISR_MISF10_Msk                       /*!<semaphore 10 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF11_Pos    (11U)

+#define HSEM_C1MISR_MISF11_Msk    (0x1UL << HSEM_C1MISR_MISF11_Pos)            /*!< 0x00000800 */

+#define HSEM_C1MISR_MISF11        HSEM_C1MISR_MISF11_Msk                       /*!<semaphore 11 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF12_Pos    (12U)

+#define HSEM_C1MISR_MISF12_Msk    (0x1UL << HSEM_C1MISR_MISF12_Pos)            /*!< 0x00001000 */

+#define HSEM_C1MISR_MISF12        HSEM_C1MISR_MISF12_Msk                       /*!<semaphore 12 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF13_Pos    (13U)

+#define HSEM_C1MISR_MISF13_Msk    (0x1UL << HSEM_C1MISR_MISF13_Pos)            /*!< 0x00002000 */

+#define HSEM_C1MISR_MISF13        HSEM_C1MISR_MISF13_Msk                       /*!<semaphore 13 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF14_Pos    (14U)

+#define HSEM_C1MISR_MISF14_Msk    (0x1UL << HSEM_C1MISR_MISF14_Pos)            /*!< 0x00004000 */

+#define HSEM_C1MISR_MISF14        HSEM_C1MISR_MISF14_Msk                       /*!<semaphore 14 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF15_Pos    (15U)

+#define HSEM_C1MISR_MISF15_Msk    (0x1UL << HSEM_C1MISR_MISF15_Pos)            /*!< 0x00008000 */

+#define HSEM_C1MISR_MISF15        HSEM_C1MISR_MISF15_Msk                       /*!<semaphore 15 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF16_Pos    (16U)

+#define HSEM_C1MISR_MISF16_Msk    (0x1UL << HSEM_C1MISR_MISF16_Pos)            /*!< 0x00010000 */

+#define HSEM_C1MISR_MISF16        HSEM_C1MISR_MISF16_Msk                       /*!<semaphore 16 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF17_Pos    (17U)

+#define HSEM_C1MISR_MISF17_Msk    (0x1UL << HSEM_C1MISR_MISF17_Pos)            /*!< 0x00020000 */

+#define HSEM_C1MISR_MISF17        HSEM_C1MISR_MISF17_Msk                       /*!<semaphore 17 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF18_Pos    (18U)

+#define HSEM_C1MISR_MISF18_Msk    (0x1UL << HSEM_C1MISR_MISF18_Pos)            /*!< 0x00040000 */

+#define HSEM_C1MISR_MISF18        HSEM_C1MISR_MISF18_Msk                       /*!<semaphore 18 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF19_Pos    (19U)

+#define HSEM_C1MISR_MISF19_Msk    (0x1UL << HSEM_C1MISR_MISF19_Pos)            /*!< 0x00080000 */

+#define HSEM_C1MISR_MISF19        HSEM_C1MISR_MISF19_Msk                       /*!<semaphore 19 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF20_Pos    (20U)

+#define HSEM_C1MISR_MISF20_Msk    (0x1UL << HSEM_C1MISR_MISF20_Pos)            /*!< 0x00100000 */

+#define HSEM_C1MISR_MISF20        HSEM_C1MISR_MISF20_Msk                       /*!<semaphore 20 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF21_Pos    (21U)

+#define HSEM_C1MISR_MISF21_Msk    (0x1UL << HSEM_C1MISR_MISF21_Pos)            /*!< 0x00200000 */

+#define HSEM_C1MISR_MISF21        HSEM_C1MISR_MISF21_Msk                       /*!<semaphore 21 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF22_Pos    (22U)

+#define HSEM_C1MISR_MISF22_Msk    (0x1UL << HSEM_C1MISR_MISF22_Pos)            /*!< 0x00400000 */

+#define HSEM_C1MISR_MISF22        HSEM_C1MISR_MISF22_Msk                       /*!<semaphore 22 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF23_Pos    (23U)

+#define HSEM_C1MISR_MISF23_Msk    (0x1UL << HSEM_C1MISR_MISF23_Pos)            /*!< 0x00800000 */

+#define HSEM_C1MISR_MISF23        HSEM_C1MISR_MISF23_Msk                       /*!<semaphore 23 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF24_Pos    (24U)

+#define HSEM_C1MISR_MISF24_Msk    (0x1UL << HSEM_C1MISR_MISF24_Pos)            /*!< 0x01000000 */

+#define HSEM_C1MISR_MISF24        HSEM_C1MISR_MISF24_Msk                       /*!<semaphore 24 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF25_Pos    (25U)

+#define HSEM_C1MISR_MISF25_Msk    (0x1UL << HSEM_C1MISR_MISF25_Pos)            /*!< 0x02000000 */

+#define HSEM_C1MISR_MISF25        HSEM_C1MISR_MISF25_Msk                       /*!<semaphore 25 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF26_Pos    (26U)

+#define HSEM_C1MISR_MISF26_Msk    (0x1UL << HSEM_C1MISR_MISF26_Pos)            /*!< 0x04000000 */

+#define HSEM_C1MISR_MISF26        HSEM_C1MISR_MISF26_Msk                       /*!<semaphore 26 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF27_Pos    (27U)

+#define HSEM_C1MISR_MISF27_Msk    (0x1UL << HSEM_C1MISR_MISF27_Pos)            /*!< 0x08000000 */

+#define HSEM_C1MISR_MISF27        HSEM_C1MISR_MISF27_Msk                       /*!<semaphore 27 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF28_Pos    (28U)

+#define HSEM_C1MISR_MISF28_Msk    (0x1UL << HSEM_C1MISR_MISF28_Pos)            /*!< 0x10000000 */

+#define HSEM_C1MISR_MISF28        HSEM_C1MISR_MISF28_Msk                       /*!<semaphore 28 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF29_Pos    (29U)

+#define HSEM_C1MISR_MISF29_Msk    (0x1UL << HSEM_C1MISR_MISF29_Pos)            /*!< 0x20000000 */

+#define HSEM_C1MISR_MISF29        HSEM_C1MISR_MISF29_Msk                       /*!<semaphore 29 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF30_Pos    (30U)

+#define HSEM_C1MISR_MISF30_Msk    (0x1UL << HSEM_C1MISR_MISF30_Pos)            /*!< 0x40000000 */

+#define HSEM_C1MISR_MISF30        HSEM_C1MISR_MISF30_Msk                       /*!<semaphore 30 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF31_Pos    (31U)

+#define HSEM_C1MISR_MISF31_Msk    (0x1UL << HSEM_C1MISR_MISF31_Pos)            /*!< 0x80000000 */

+#define HSEM_C1MISR_MISF31        HSEM_C1MISR_MISF31_Msk                       /*!<semaphore 31 interrupt 0 masked status bit. */

+

+/********************  Bit definition for HSEM_C2IER register  *****************/

+#define HSEM_C2IER_ISE0_Pos       (0U)

+#define HSEM_C2IER_ISE0_Msk       (0x1UL << HSEM_C2IER_ISE0_Pos)               /*!< 0x00000001 */

+#define HSEM_C2IER_ISE0           HSEM_C2IER_ISE0_Msk                          /*!<semaphore 0 , interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE1_Pos       (1U)

+#define HSEM_C2IER_ISE1_Msk       (0x1UL << HSEM_C2IER_ISE1_Pos)               /*!< 0x00000002 */

+#define HSEM_C2IER_ISE1           HSEM_C2IER_ISE1_Msk                          /*!<semaphore 1 , interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE2_Pos       (2U)

+#define HSEM_C2IER_ISE2_Msk       (0x1UL << HSEM_C2IER_ISE2_Pos)               /*!< 0x00000004 */

+#define HSEM_C2IER_ISE2           HSEM_C2IER_ISE2_Msk                          /*!<semaphore 2 , interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE3_Pos       (3U)

+#define HSEM_C2IER_ISE3_Msk       (0x1UL << HSEM_C2IER_ISE3_Pos)               /*!< 0x00000008 */

+#define HSEM_C2IER_ISE3           HSEM_C2IER_ISE3_Msk                          /*!<semaphore 3 , interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE4_Pos       (4U)

+#define HSEM_C2IER_ISE4_Msk       (0x1UL << HSEM_C2IER_ISE4_Pos)               /*!< 0x00000010 */

+#define HSEM_C2IER_ISE4           HSEM_C2IER_ISE4_Msk                          /*!<semaphore 4 , interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE5_Pos       (5U)

+#define HSEM_C2IER_ISE5_Msk       (0x1UL << HSEM_C2IER_ISE5_Pos)               /*!< 0x00000020 */

+#define HSEM_C2IER_ISE5           HSEM_C2IER_ISE5_Msk                          /*!<semaphore 5 interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE6_Pos       (6U)

+#define HSEM_C2IER_ISE6_Msk       (0x1UL << HSEM_C2IER_ISE6_Pos)               /*!< 0x00000040 */

+#define HSEM_C2IER_ISE6           HSEM_C2IER_ISE6_Msk                          /*!<semaphore 6 interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE7_Pos       (7U)

+#define HSEM_C2IER_ISE7_Msk       (0x1UL << HSEM_C2IER_ISE7_Pos)               /*!< 0x00000080 */

+#define HSEM_C2IER_ISE7           HSEM_C2IER_ISE7_Msk                          /*!<semaphore 7 interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE8_Pos       (8U)

+#define HSEM_C2IER_ISE8_Msk       (0x1UL << HSEM_C2IER_ISE8_Pos)               /*!< 0x00000100 */

+#define HSEM_C2IER_ISE8           HSEM_C2IER_ISE8_Msk                          /*!<semaphore 8 interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE9_Pos       (9U)

+#define HSEM_C2IER_ISE9_Msk       (0x1UL << HSEM_C2IER_ISE9_Pos)               /*!< 0x00000200 */

+#define HSEM_C2IER_ISE9           HSEM_C2IER_ISE9_Msk                          /*!<semaphore 9 interrupt 1 enable bit.  */

+#define HSEM_C2IER_ISE10_Pos      (10U)

+#define HSEM_C2IER_ISE10_Msk      (0x1UL << HSEM_C2IER_ISE10_Pos)              /*!< 0x00000400 */

+#define HSEM_C2IER_ISE10          HSEM_C2IER_ISE10_Msk                         /*!<semaphore 10 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE11_Pos      (11U)

+#define HSEM_C2IER_ISE11_Msk      (0x1UL << HSEM_C2IER_ISE11_Pos)              /*!< 0x00000800 */

+#define HSEM_C2IER_ISE11          HSEM_C2IER_ISE11_Msk                         /*!<semaphore 11 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE12_Pos      (12U)

+#define HSEM_C2IER_ISE12_Msk      (0x1UL << HSEM_C2IER_ISE12_Pos)              /*!< 0x00001000 */

+#define HSEM_C2IER_ISE12          HSEM_C2IER_ISE12_Msk                         /*!<semaphore 12 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE13_Pos      (13U)

+#define HSEM_C2IER_ISE13_Msk      (0x1UL << HSEM_C2IER_ISE13_Pos)              /*!< 0x00002000 */

+#define HSEM_C2IER_ISE13          HSEM_C2IER_ISE13_Msk                         /*!<semaphore 13 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE14_Pos      (14U)

+#define HSEM_C2IER_ISE14_Msk      (0x1UL << HSEM_C2IER_ISE14_Pos)              /*!< 0x00004000 */

+#define HSEM_C2IER_ISE14          HSEM_C2IER_ISE14_Msk                         /*!<semaphore 14 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE15_Pos      (15U)

+#define HSEM_C2IER_ISE15_Msk      (0x1UL << HSEM_C2IER_ISE15_Pos)              /*!< 0x00008000 */

+#define HSEM_C2IER_ISE15          HSEM_C2IER_ISE15_Msk                         /*!<semaphore 15 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE16_Pos      (16U)

+#define HSEM_C2IER_ISE16_Msk      (0x1UL << HSEM_C2IER_ISE16_Pos)              /*!< 0x00010000 */

+#define HSEM_C2IER_ISE16          HSEM_C2IER_ISE16_Msk                         /*!<semaphore 16 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE17_Pos      (17U)

+#define HSEM_C2IER_ISE17_Msk      (0x1UL << HSEM_C2IER_ISE17_Pos)              /*!< 0x00020000 */

+#define HSEM_C2IER_ISE17          HSEM_C2IER_ISE17_Msk                         /*!<semaphore 17 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE18_Pos      (18U)

+#define HSEM_C2IER_ISE18_Msk      (0x1UL << HSEM_C2IER_ISE18_Pos)              /*!< 0x00040000 */

+#define HSEM_C2IER_ISE18          HSEM_C2IER_ISE18_Msk                         /*!<semaphore 18 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE19_Pos      (19U)

+#define HSEM_C2IER_ISE19_Msk      (0x1UL << HSEM_C2IER_ISE19_Pos)              /*!< 0x00080000 */

+#define HSEM_C2IER_ISE19          HSEM_C2IER_ISE19_Msk                         /*!<semaphore 19 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE20_Pos      (20U)

+#define HSEM_C2IER_ISE20_Msk      (0x1UL << HSEM_C2IER_ISE20_Pos)              /*!< 0x00100000 */

+#define HSEM_C2IER_ISE20          HSEM_C2IER_ISE20_Msk                         /*!<semaphore 20 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE21_Pos      (21U)

+#define HSEM_C2IER_ISE21_Msk      (0x1UL << HSEM_C2IER_ISE21_Pos)              /*!< 0x00200000 */

+#define HSEM_C2IER_ISE21          HSEM_C2IER_ISE21_Msk                         /*!<semaphore 21 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE22_Pos      (22U)

+#define HSEM_C2IER_ISE22_Msk      (0x1UL << HSEM_C2IER_ISE22_Pos)              /*!< 0x00400000 */

+#define HSEM_C2IER_ISE22          HSEM_C2IER_ISE22_Msk                         /*!<semaphore 22 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE23_Pos      (23U)

+#define HSEM_C2IER_ISE23_Msk      (0x1UL << HSEM_C2IER_ISE23_Pos)              /*!< 0x00800000 */

+#define HSEM_C2IER_ISE23          HSEM_C2IER_ISE23_Msk                         /*!<semaphore 23 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE24_Pos      (24U)

+#define HSEM_C2IER_ISE24_Msk      (0x1UL << HSEM_C2IER_ISE24_Pos)              /*!< 0x01000000 */

+#define HSEM_C2IER_ISE24          HSEM_C2IER_ISE24_Msk                         /*!<semaphore 24 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE25_Pos      (25U)

+#define HSEM_C2IER_ISE25_Msk      (0x1UL << HSEM_C2IER_ISE25_Pos)              /*!< 0x02000000 */

+#define HSEM_C2IER_ISE25          HSEM_C2IER_ISE25_Msk                         /*!<semaphore 25 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE26_Pos      (26U)

+#define HSEM_C2IER_ISE26_Msk      (0x1UL << HSEM_C2IER_ISE26_Pos)              /*!< 0x04000000 */

+#define HSEM_C2IER_ISE26          HSEM_C2IER_ISE26_Msk                         /*!<semaphore 26 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE27_Pos      (27U)

+#define HSEM_C2IER_ISE27_Msk      (0x1UL << HSEM_C2IER_ISE27_Pos)              /*!< 0x08000000 */

+#define HSEM_C2IER_ISE27          HSEM_C2IER_ISE27_Msk                         /*!<semaphore 27 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE28_Pos      (28U)

+#define HSEM_C2IER_ISE28_Msk      (0x1UL << HSEM_C2IER_ISE28_Pos)              /*!< 0x10000000 */

+#define HSEM_C2IER_ISE28          HSEM_C2IER_ISE28_Msk                         /*!<semaphore 28 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE29_Pos      (29U)

+#define HSEM_C2IER_ISE29_Msk      (0x1UL << HSEM_C2IER_ISE29_Pos)              /*!< 0x20000000 */

+#define HSEM_C2IER_ISE29          HSEM_C2IER_ISE29_Msk                         /*!<semaphore 29 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE30_Pos      (30U)

+#define HSEM_C2IER_ISE30_Msk      (0x1UL << HSEM_C2IER_ISE30_Pos)              /*!< 0x40000000 */

+#define HSEM_C2IER_ISE30          HSEM_C2IER_ISE30_Msk                         /*!<semaphore 30 interrupt 1 enable bit. */

+#define HSEM_C2IER_ISE31_Pos      (31U)

+#define HSEM_C2IER_ISE31_Msk      (0x1UL << HSEM_C2IER_ISE31_Pos)              /*!< 0x80000000 */

+#define HSEM_C2IER_ISE31          HSEM_C2IER_ISE31_Msk                         /*!<semaphore 31 interrupt 1 enable bit. */

+

+/********************  Bit definition for HSEM_C2ICR register  *****************/

+#define HSEM_C2ICR_ISC0_Pos       (0U)

+#define HSEM_C2ICR_ISC0_Msk       (0x1UL << HSEM_C2ICR_ISC0_Pos)               /*!< 0x00000001 */

+#define HSEM_C2ICR_ISC0           HSEM_C2ICR_ISC0_Msk                          /*!<semaphore 0 , interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC1_Pos       (1U)

+#define HSEM_C2ICR_ISC1_Msk       (0x1UL << HSEM_C2ICR_ISC1_Pos)               /*!< 0x00000002 */

+#define HSEM_C2ICR_ISC1           HSEM_C2ICR_ISC1_Msk                          /*!<semaphore 1 , interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC2_Pos       (2U)

+#define HSEM_C2ICR_ISC2_Msk       (0x1UL << HSEM_C2ICR_ISC2_Pos)               /*!< 0x00000004 */

+#define HSEM_C2ICR_ISC2           HSEM_C2ICR_ISC2_Msk                          /*!<semaphore 2 , interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC3_Pos       (3U)

+#define HSEM_C2ICR_ISC3_Msk       (0x1UL << HSEM_C2ICR_ISC3_Pos)               /*!< 0x00000008 */

+#define HSEM_C2ICR_ISC3           HSEM_C2ICR_ISC3_Msk                          /*!<semaphore 3 , interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC4_Pos       (4U)

+#define HSEM_C2ICR_ISC4_Msk       (0x1UL << HSEM_C2ICR_ISC4_Pos)               /*!< 0x00000010 */

+#define HSEM_C2ICR_ISC4           HSEM_C2ICR_ISC4_Msk                          /*!<semaphore 4 , interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC5_Pos       (5U)

+#define HSEM_C2ICR_ISC5_Msk       (0x1UL << HSEM_C2ICR_ISC5_Pos)               /*!< 0x00000020 */

+#define HSEM_C2ICR_ISC5           HSEM_C2ICR_ISC5_Msk                          /*!<semaphore 5 interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC6_Pos       (6U)

+#define HSEM_C2ICR_ISC6_Msk       (0x1UL << HSEM_C2ICR_ISC6_Pos)               /*!< 0x00000040 */

+#define HSEM_C2ICR_ISC6           HSEM_C2ICR_ISC6_Msk                          /*!<semaphore 6 interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC7_Pos       (7U)

+#define HSEM_C2ICR_ISC7_Msk       (0x1UL << HSEM_C2ICR_ISC7_Pos)               /*!< 0x00000080 */

+#define HSEM_C2ICR_ISC7           HSEM_C2ICR_ISC7_Msk                          /*!<semaphore 7 interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC8_Pos       (8U)

+#define HSEM_C2ICR_ISC8_Msk       (0x1UL << HSEM_C2ICR_ISC8_Pos)               /*!< 0x00000100 */

+#define HSEM_C2ICR_ISC8           HSEM_C2ICR_ISC8_Msk                          /*!<semaphore 8 interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC9_Pos       (9U)

+#define HSEM_C2ICR_ISC9_Msk       (0x1UL << HSEM_C2ICR_ISC9_Pos)               /*!< 0x00000200 */

+#define HSEM_C2ICR_ISC9           HSEM_C2ICR_ISC9_Msk                          /*!<semaphore 9 interrupt 1 clear bit.  */

+#define HSEM_C2ICR_ISC10_Pos      (10U)

+#define HSEM_C2ICR_ISC10_Msk      (0x1UL << HSEM_C2ICR_ISC10_Pos)              /*!< 0x00000400 */

+#define HSEM_C2ICR_ISC10          HSEM_C2ICR_ISC10_Msk                         /*!<semaphore 10 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC11_Pos      (11U)

+#define HSEM_C2ICR_ISC11_Msk      (0x1UL << HSEM_C2ICR_ISC11_Pos)              /*!< 0x00000800 */

+#define HSEM_C2ICR_ISC11          HSEM_C2ICR_ISC11_Msk                         /*!<semaphore 11 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC12_Pos      (12U)

+#define HSEM_C2ICR_ISC12_Msk      (0x1UL << HSEM_C2ICR_ISC12_Pos)              /*!< 0x00001000 */

+#define HSEM_C2ICR_ISC12          HSEM_C2ICR_ISC12_Msk                         /*!<semaphore 12 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC13_Pos      (13U)

+#define HSEM_C2ICR_ISC13_Msk      (0x1UL << HSEM_C2ICR_ISC13_Pos)              /*!< 0x00002000 */

+#define HSEM_C2ICR_ISC13          HSEM_C2ICR_ISC13_Msk                         /*!<semaphore 13 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC14_Pos      (14U)

+#define HSEM_C2ICR_ISC14_Msk      (0x1UL << HSEM_C2ICR_ISC14_Pos)              /*!< 0x00004000 */

+#define HSEM_C2ICR_ISC14          HSEM_C2ICR_ISC14_Msk                         /*!<semaphore 14 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC15_Pos      (15U)

+#define HSEM_C2ICR_ISC15_Msk      (0x1UL << HSEM_C2ICR_ISC15_Pos)              /*!< 0x00008000 */

+#define HSEM_C2ICR_ISC15          HSEM_C2ICR_ISC15_Msk                         /*!<semaphore 15 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC16_Pos      (16U)

+#define HSEM_C2ICR_ISC16_Msk      (0x1UL << HSEM_C2ICR_ISC16_Pos)              /*!< 0x00010000 */

+#define HSEM_C2ICR_ISC16          HSEM_C2ICR_ISC16_Msk                         /*!<semaphore 16 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC17_Pos      (17U)

+#define HSEM_C2ICR_ISC17_Msk      (0x1UL << HSEM_C2ICR_ISC17_Pos)              /*!< 0x00020000 */

+#define HSEM_C2ICR_ISC17          HSEM_C2ICR_ISC17_Msk                         /*!<semaphore 17 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC18_Pos      (18U)

+#define HSEM_C2ICR_ISC18_Msk      (0x1UL << HSEM_C2ICR_ISC18_Pos)              /*!< 0x00040000 */

+#define HSEM_C2ICR_ISC18          HSEM_C2ICR_ISC18_Msk                         /*!<semaphore 18 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC19_Pos      (19U)

+#define HSEM_C2ICR_ISC19_Msk      (0x1UL << HSEM_C2ICR_ISC19_Pos)              /*!< 0x00080000 */

+#define HSEM_C2ICR_ISC19          HSEM_C2ICR_ISC19_Msk                         /*!<semaphore 19 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC20_Pos      (20U)

+#define HSEM_C2ICR_ISC20_Msk      (0x1UL << HSEM_C2ICR_ISC20_Pos)              /*!< 0x00100000 */

+#define HSEM_C2ICR_ISC20          HSEM_C2ICR_ISC20_Msk                         /*!<semaphore 20 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC21_Pos      (21U)

+#define HSEM_C2ICR_ISC21_Msk      (0x1UL << HSEM_C2ICR_ISC21_Pos)              /*!< 0x00200000 */

+#define HSEM_C2ICR_ISC21          HSEM_C2ICR_ISC21_Msk                         /*!<semaphore 21 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC22_Pos      (22U)

+#define HSEM_C2ICR_ISC22_Msk      (0x1UL << HSEM_C2ICR_ISC22_Pos)              /*!< 0x00400000 */

+#define HSEM_C2ICR_ISC22          HSEM_C2ICR_ISC22_Msk                         /*!<semaphore 22 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC23_Pos      (23U)

+#define HSEM_C2ICR_ISC23_Msk      (0x1UL << HSEM_C2ICR_ISC23_Pos)              /*!< 0x00800000 */

+#define HSEM_C2ICR_ISC23          HSEM_C2ICR_ISC23_Msk                         /*!<semaphore 23 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC24_Pos      (24U)

+#define HSEM_C2ICR_ISC24_Msk      (0x1UL << HSEM_C2ICR_ISC24_Pos)              /*!< 0x01000000 */

+#define HSEM_C2ICR_ISC24          HSEM_C2ICR_ISC24_Msk                         /*!<semaphore 24 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC25_Pos      (25U)

+#define HSEM_C2ICR_ISC25_Msk      (0x1UL << HSEM_C2ICR_ISC25_Pos)              /*!< 0x02000000 */

+#define HSEM_C2ICR_ISC25          HSEM_C2ICR_ISC25_Msk                         /*!<semaphore 25 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC26_Pos      (26U)

+#define HSEM_C2ICR_ISC26_Msk      (0x1UL << HSEM_C2ICR_ISC26_Pos)              /*!< 0x04000000 */

+#define HSEM_C2ICR_ISC26          HSEM_C2ICR_ISC26_Msk                         /*!<semaphore 26 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC27_Pos      (27U)

+#define HSEM_C2ICR_ISC27_Msk      (0x1UL << HSEM_C2ICR_ISC27_Pos)              /*!< 0x08000000 */

+#define HSEM_C2ICR_ISC27          HSEM_C2ICR_ISC27_Msk                         /*!<semaphore 27 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC28_Pos      (28U)

+#define HSEM_C2ICR_ISC28_Msk      (0x1UL << HSEM_C2ICR_ISC28_Pos)              /*!< 0x10000000 */

+#define HSEM_C2ICR_ISC28          HSEM_C2ICR_ISC28_Msk                         /*!<semaphore 28 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC29_Pos      (29U)

+#define HSEM_C2ICR_ISC29_Msk      (0x1UL << HSEM_C2ICR_ISC29_Pos)              /*!< 0x20000000 */

+#define HSEM_C2ICR_ISC29          HSEM_C2ICR_ISC29_Msk                         /*!<semaphore 29 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC30_Pos      (30U)

+#define HSEM_C2ICR_ISC30_Msk      (0x1UL << HSEM_C2ICR_ISC30_Pos)              /*!< 0x40000000 */

+#define HSEM_C2ICR_ISC30          HSEM_C2ICR_ISC30_Msk                         /*!<semaphore 30 interrupt 1 clear bit. */

+#define HSEM_C2ICR_ISC31_Pos      (31U)

+#define HSEM_C2ICR_ISC31_Msk      (0x1UL << HSEM_C2ICR_ISC31_Pos)              /*!< 0x80000000 */

+#define HSEM_C2ICR_ISC31          HSEM_C2ICR_ISC31_Msk                         /*!<semaphore 31 interrupt 1 clear bit. */

+

+/********************  Bit definition for HSEM_C2ISR register  *****************/

+#define HSEM_C2ISR_ISF0_Pos       (0U)

+#define HSEM_C2ISR_ISF0_Msk       (0x1UL << HSEM_C2ISR_ISF0_Pos)               /*!< 0x00000001 */

+#define HSEM_C2ISR_ISF0           HSEM_C2ISR_ISF0_Msk                          /*!<semaphore 0 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF1_Pos       (1U)

+#define HSEM_C2ISR_ISF1_Msk       (0x1UL << HSEM_C2ISR_ISF1_Pos)               /*!< 0x00000002 */

+#define HSEM_C2ISR_ISF1           HSEM_C2ISR_ISF1_Msk                          /*!<semaphore 1 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF2_Pos       (2U)

+#define HSEM_C2ISR_ISF2_Msk       (0x1UL << HSEM_C2ISR_ISF2_Pos)               /*!< 0x00000004 */

+#define HSEM_C2ISR_ISF2           HSEM_C2ISR_ISF2_Msk                          /*!<semaphore 2 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF3_Pos       (3U)

+#define HSEM_C2ISR_ISF3_Msk       (0x1UL << HSEM_C2ISR_ISF3_Pos)               /*!< 0x00000008 */

+#define HSEM_C2ISR_ISF3           HSEM_C2ISR_ISF3_Msk                          /*!<semaphore 3 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF4_Pos       (4U)

+#define HSEM_C2ISR_ISF4_Msk       (0x1UL << HSEM_C2ISR_ISF4_Pos)               /*!< 0x00000010 */

+#define HSEM_C2ISR_ISF4           HSEM_C2ISR_ISF4_Msk                          /*!<semaphore 4 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF5_Pos       (5U)

+#define HSEM_C2ISR_ISF5_Msk       (0x1UL << HSEM_C2ISR_ISF5_Pos)               /*!< 0x00000020 */

+#define HSEM_C2ISR_ISF5           HSEM_C2ISR_ISF5_Msk                          /*!<semaphore 5 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF6_Pos       (6U)

+#define HSEM_C2ISR_ISF6_Msk       (0x1UL << HSEM_C2ISR_ISF6_Pos)               /*!< 0x00000040 */

+#define HSEM_C2ISR_ISF6           HSEM_C2ISR_ISF6_Msk                          /*!<semaphore 6 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF7_Pos       (7U)

+#define HSEM_C2ISR_ISF7_Msk       (0x1UL << HSEM_C2ISR_ISF7_Pos)               /*!< 0x00000080 */

+#define HSEM_C2ISR_ISF7           HSEM_C2ISR_ISF7_Msk                          /*!<semaphore 7 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF8_Pos       (8U)

+#define HSEM_C2ISR_ISF8_Msk       (0x1UL << HSEM_C2ISR_ISF8_Pos)               /*!< 0x00000100 */

+#define HSEM_C2ISR_ISF8           HSEM_C2ISR_ISF8_Msk                          /*!<semaphore 8 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF9_Pos       (9U)

+#define HSEM_C2ISR_ISF9_Msk       (0x1UL << HSEM_C2ISR_ISF9_Pos)               /*!< 0x00000200 */

+#define HSEM_C2ISR_ISF9           HSEM_C2ISR_ISF9_Msk                          /*!<semaphore 9 interrupt 1 status bit.  */

+#define HSEM_C2ISR_ISF10_Pos      (10U)

+#define HSEM_C2ISR_ISF10_Msk      (0x1UL << HSEM_C2ISR_ISF10_Pos)              /*!< 0x00000400 */

+#define HSEM_C2ISR_ISF10          HSEM_C2ISR_ISF10_Msk                         /*!<semaphore 10 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF11_Pos      (11U)

+#define HSEM_C2ISR_ISF11_Msk      (0x1UL << HSEM_C2ISR_ISF11_Pos)              /*!< 0x00000800 */

+#define HSEM_C2ISR_ISF11          HSEM_C2ISR_ISF11_Msk                         /*!<semaphore 11 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF12_Pos      (12U)

+#define HSEM_C2ISR_ISF12_Msk      (0x1UL << HSEM_C2ISR_ISF12_Pos)              /*!< 0x00001000 */

+#define HSEM_C2ISR_ISF12          HSEM_C2ISR_ISF12_Msk                         /*!<semaphore 12 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF13_Pos      (13U)

+#define HSEM_C2ISR_ISF13_Msk      (0x1UL << HSEM_C2ISR_ISF13_Pos)              /*!< 0x00002000 */

+#define HSEM_C2ISR_ISF13          HSEM_C2ISR_ISF13_Msk                         /*!<semaphore 13 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF14_Pos      (14U)

+#define HSEM_C2ISR_ISF14_Msk      (0x1UL << HSEM_C2ISR_ISF14_Pos)              /*!< 0x00004000 */

+#define HSEM_C2ISR_ISF14          HSEM_C2ISR_ISF14_Msk                         /*!<semaphore 14 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF15_Pos      (15U)

+#define HSEM_C2ISR_ISF15_Msk      (0x1UL << HSEM_C2ISR_ISF15_Pos)              /*!< 0x00008000 */

+#define HSEM_C2ISR_ISF15          HSEM_C2ISR_ISF15_Msk                         /*!<semaphore 15 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF16_Pos      (16U)

+#define HSEM_C2ISR_ISF16_Msk      (0x1UL << HSEM_C2ISR_ISF16_Pos)              /*!< 0x00010000 */

+#define HSEM_C2ISR_ISF16          HSEM_C2ISR_ISF16_Msk                         /*!<semaphore 16 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF17_Pos      (17U)

+#define HSEM_C2ISR_ISF17_Msk      (0x1UL << HSEM_C2ISR_ISF17_Pos)              /*!< 0x00020000 */

+#define HSEM_C2ISR_ISF17          HSEM_C2ISR_ISF17_Msk                         /*!<semaphore 17 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF18_Pos      (18U)

+#define HSEM_C2ISR_ISF18_Msk      (0x1UL << HSEM_C2ISR_ISF18_Pos)              /*!< 0x00040000 */

+#define HSEM_C2ISR_ISF18          HSEM_C2ISR_ISF18_Msk                         /*!<semaphore 18 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF19_Pos      (19U)

+#define HSEM_C2ISR_ISF19_Msk      (0x1UL << HSEM_C2ISR_ISF19_Pos)              /*!< 0x00080000 */

+#define HSEM_C2ISR_ISF19          HSEM_C2ISR_ISF19_Msk                         /*!<semaphore 19 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF20_Pos      (20U)

+#define HSEM_C2ISR_ISF20_Msk      (0x1UL << HSEM_C2ISR_ISF20_Pos)              /*!< 0x00100000 */

+#define HSEM_C2ISR_ISF20          HSEM_C2ISR_ISF20_Msk                         /*!<semaphore 20 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF21_Pos      (21U)

+#define HSEM_C2ISR_ISF21_Msk      (0x1UL << HSEM_C2ISR_ISF21_Pos)              /*!< 0x00200000 */

+#define HSEM_C2ISR_ISF21          HSEM_C2ISR_ISF21_Msk                         /*!<semaphore 21 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF22_Pos      (22U)

+#define HSEM_C2ISR_ISF22_Msk      (0x1UL << HSEM_C2ISR_ISF22_Pos)              /*!< 0x00400000 */

+#define HSEM_C2ISR_ISF22          HSEM_C2ISR_ISF22_Msk                         /*!<semaphore 22 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF23_Pos      (23U)

+#define HSEM_C2ISR_ISF23_Msk      (0x1UL << HSEM_C2ISR_ISF23_Pos)              /*!< 0x00800000 */

+#define HSEM_C2ISR_ISF23          HSEM_C2ISR_ISF23_Msk                         /*!<semaphore 23 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF24_Pos      (24U)

+#define HSEM_C2ISR_ISF24_Msk      (0x1UL << HSEM_C2ISR_ISF24_Pos)              /*!< 0x01000000 */

+#define HSEM_C2ISR_ISF24          HSEM_C2ISR_ISF24_Msk                         /*!<semaphore 24 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF25_Pos      (25U)

+#define HSEM_C2ISR_ISF25_Msk      (0x1UL << HSEM_C2ISR_ISF25_Pos)              /*!< 0x02000000 */

+#define HSEM_C2ISR_ISF25          HSEM_C2ISR_ISF25_Msk                         /*!<semaphore 25 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF26_Pos      (26U)

+#define HSEM_C2ISR_ISF26_Msk      (0x1UL << HSEM_C2ISR_ISF26_Pos)              /*!< 0x04000000 */

+#define HSEM_C2ISR_ISF26          HSEM_C2ISR_ISF26_Msk                         /*!<semaphore 26 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF27_Pos      (27U)

+#define HSEM_C2ISR_ISF27_Msk      (0x1UL << HSEM_C2ISR_ISF27_Pos)              /*!< 0x08000000 */

+#define HSEM_C2ISR_ISF27          HSEM_C2ISR_ISF27_Msk                         /*!<semaphore 27 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF28_Pos      (28U)

+#define HSEM_C2ISR_ISF28_Msk      (0x1UL << HSEM_C2ISR_ISF28_Pos)              /*!< 0x10000000 */

+#define HSEM_C2ISR_ISF28          HSEM_C2ISR_ISF28_Msk                         /*!<semaphore 28 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF29_Pos      (29U)

+#define HSEM_C2ISR_ISF29_Msk      (0x1UL << HSEM_C2ISR_ISF29_Pos)              /*!< 0x20000000 */

+#define HSEM_C2ISR_ISF29          HSEM_C2ISR_ISF29_Msk                         /*!<semaphore 29 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF30_Pos      (30U)

+#define HSEM_C2ISR_ISF30_Msk      (0x1UL << HSEM_C2ISR_ISF30_Pos)              /*!< 0x40000000 */

+#define HSEM_C2ISR_ISF30          HSEM_C2ISR_ISF30_Msk                         /*!<semaphore 30 interrupt 1 status bit. */

+#define HSEM_C2ISR_ISF31_Pos      (31U)

+#define HSEM_C2ISR_ISF31_Msk      (0x1UL << HSEM_C2ISR_ISF31_Pos)              /*!< 0x80000000 */

+#define HSEM_C2ISR_ISF31          HSEM_C2ISR_ISF31_Msk                         /*!<semaphore 31 interrupt 1 status bit. */

+

+/********************  Bit definition for HSEM_C2MISR register  *****************/

+#define HSEM_C2MISR_MISF0_Pos     (0U)

+#define HSEM_C2MISR_MISF0_Msk     (0x1UL << HSEM_C2MISR_MISF0_Pos)             /*!< 0x00000001 */

+#define HSEM_C2MISR_MISF0         HSEM_C2MISR_MISF0_Msk                        /*!<semaphore 0 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF1_Pos     (1U)

+#define HSEM_C2MISR_MISF1_Msk     (0x1UL << HSEM_C2MISR_MISF1_Pos)             /*!< 0x00000002 */

+#define HSEM_C2MISR_MISF1         HSEM_C2MISR_MISF1_Msk                        /*!<semaphore 1 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF2_Pos     (2U)

+#define HSEM_C2MISR_MISF2_Msk     (0x1UL << HSEM_C2MISR_MISF2_Pos)             /*!< 0x00000004 */

+#define HSEM_C2MISR_MISF2         HSEM_C2MISR_MISF2_Msk                        /*!<semaphore 2 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF3_Pos     (3U)

+#define HSEM_C2MISR_MISF3_Msk     (0x1UL << HSEM_C2MISR_MISF3_Pos)             /*!< 0x00000008 */

+#define HSEM_C2MISR_MISF3         HSEM_C2MISR_MISF3_Msk                        /*!<semaphore 3 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF4_Pos     (4U)

+#define HSEM_C2MISR_MISF4_Msk     (0x1UL << HSEM_C2MISR_MISF4_Pos)             /*!< 0x00000010 */

+#define HSEM_C2MISR_MISF4         HSEM_C2MISR_MISF4_Msk                        /*!<semaphore 4 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF5_Pos     (5U)

+#define HSEM_C2MISR_MISF5_Msk     (0x1UL << HSEM_C2MISR_MISF5_Pos)             /*!< 0x00000020 */

+#define HSEM_C2MISR_MISF5         HSEM_C2MISR_MISF5_Msk                        /*!<semaphore 5 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF6_Pos     (6U)

+#define HSEM_C2MISR_MISF6_Msk     (0x1UL << HSEM_C2MISR_MISF6_Pos)             /*!< 0x00000040 */

+#define HSEM_C2MISR_MISF6         HSEM_C2MISR_MISF6_Msk                        /*!<semaphore 6 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF7_Pos     (7U)

+#define HSEM_C2MISR_MISF7_Msk     (0x1UL << HSEM_C2MISR_MISF7_Pos)             /*!< 0x00000080 */

+#define HSEM_C2MISR_MISF7         HSEM_C2MISR_MISF7_Msk                        /*!<semaphore 7 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF8_Pos     (8U)

+#define HSEM_C2MISR_MISF8_Msk     (0x1UL << HSEM_C2MISR_MISF8_Pos)             /*!< 0x00000100 */

+#define HSEM_C2MISR_MISF8         HSEM_C2MISR_MISF8_Msk                        /*!<semaphore 8 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF9_Pos     (9U)

+#define HSEM_C2MISR_MISF9_Msk     (0x1UL << HSEM_C2MISR_MISF9_Pos)             /*!< 0x00000200 */

+#define HSEM_C2MISR_MISF9         HSEM_C2MISR_MISF9_Msk                        /*!<semaphore 9 interrupt 1 masked status bit.  */

+#define HSEM_C2MISR_MISF10_Pos    (10U)

+#define HSEM_C2MISR_MISF10_Msk    (0x1UL << HSEM_C2MISR_MISF10_Pos)            /*!< 0x00000400 */

+#define HSEM_C2MISR_MISF10        HSEM_C2MISR_MISF10_Msk                       /*!<semaphore 10 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF11_Pos    (11U)

+#define HSEM_C2MISR_MISF11_Msk    (0x1UL << HSEM_C2MISR_MISF11_Pos)            /*!< 0x00000800 */

+#define HSEM_C2MISR_MISF11        HSEM_C2MISR_MISF11_Msk                       /*!<semaphore 11 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF12_Pos    (12U)

+#define HSEM_C2MISR_MISF12_Msk    (0x1UL << HSEM_C2MISR_MISF12_Pos)            /*!< 0x00001000 */

+#define HSEM_C2MISR_MISF12        HSEM_C2MISR_MISF12_Msk                       /*!<semaphore 12 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF13_Pos    (13U)

+#define HSEM_C2MISR_MISF13_Msk    (0x1UL << HSEM_C2MISR_MISF13_Pos)            /*!< 0x00002000 */

+#define HSEM_C2MISR_MISF13        HSEM_C2MISR_MISF13_Msk                       /*!<semaphore 13 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF14_Pos    (14U)

+#define HSEM_C2MISR_MISF14_Msk    (0x1UL << HSEM_C2MISR_MISF14_Pos)            /*!< 0x00004000 */

+#define HSEM_C2MISR_MISF14        HSEM_C2MISR_MISF14_Msk                       /*!<semaphore 14 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF15_Pos    (15U)

+#define HSEM_C2MISR_MISF15_Msk    (0x1UL << HSEM_C2MISR_MISF15_Pos)            /*!< 0x00008000 */

+#define HSEM_C2MISR_MISF15        HSEM_C2MISR_MISF15_Msk                       /*!<semaphore 15 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF16_Pos    (16U)

+#define HSEM_C2MISR_MISF16_Msk    (0x1UL << HSEM_C2MISR_MISF16_Pos)            /*!< 0x00010000 */

+#define HSEM_C2MISR_MISF16        HSEM_C2MISR_MISF16_Msk                       /*!<semaphore 16 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF17_Pos    (17U)

+#define HSEM_C2MISR_MISF17_Msk    (0x1UL << HSEM_C2MISR_MISF17_Pos)            /*!< 0x00020000 */

+#define HSEM_C2MISR_MISF17        HSEM_C2MISR_MISF17_Msk                       /*!<semaphore 17 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF18_Pos    (18U)

+#define HSEM_C2MISR_MISF18_Msk    (0x1UL << HSEM_C2MISR_MISF18_Pos)            /*!< 0x00040000 */

+#define HSEM_C2MISR_MISF18        HSEM_C2MISR_MISF18_Msk                       /*!<semaphore 18 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF19_Pos    (19U)

+#define HSEM_C2MISR_MISF19_Msk    (0x1UL << HSEM_C2MISR_MISF19_Pos)            /*!< 0x00080000 */

+#define HSEM_C2MISR_MISF19        HSEM_C2MISR_MISF19_Msk                       /*!<semaphore 19 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF20_Pos    (20U)

+#define HSEM_C2MISR_MISF20_Msk    (0x1UL << HSEM_C2MISR_MISF20_Pos)            /*!< 0x00100000 */

+#define HSEM_C2MISR_MISF20        HSEM_C2MISR_MISF20_Msk                       /*!<semaphore 20 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF21_Pos    (21U)

+#define HSEM_C2MISR_MISF21_Msk    (0x1UL << HSEM_C2MISR_MISF21_Pos)            /*!< 0x00200000 */

+#define HSEM_C2MISR_MISF21        HSEM_C2MISR_MISF21_Msk                       /*!<semaphore 21 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF22_Pos    (22U)

+#define HSEM_C2MISR_MISF22_Msk    (0x1UL << HSEM_C2MISR_MISF22_Pos)            /*!< 0x00400000 */

+#define HSEM_C2MISR_MISF22        HSEM_C2MISR_MISF22_Msk                       /*!<semaphore 22 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF23_Pos    (23U)

+#define HSEM_C2MISR_MISF23_Msk    (0x1UL << HSEM_C2MISR_MISF23_Pos)            /*!< 0x00800000 */

+#define HSEM_C2MISR_MISF23        HSEM_C2MISR_MISF23_Msk                       /*!<semaphore 23 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF24_Pos    (24U)

+#define HSEM_C2MISR_MISF24_Msk    (0x1UL << HSEM_C2MISR_MISF24_Pos)            /*!< 0x01000000 */

+#define HSEM_C2MISR_MISF24        HSEM_C2MISR_MISF24_Msk                       /*!<semaphore 24 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF25_Pos    (25U)

+#define HSEM_C2MISR_MISF25_Msk    (0x1UL << HSEM_C2MISR_MISF25_Pos)            /*!< 0x02000000 */

+#define HSEM_C2MISR_MISF25        HSEM_C2MISR_MISF25_Msk                       /*!<semaphore 25 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF26_Pos    (26U)

+#define HSEM_C2MISR_MISF26_Msk    (0x1UL << HSEM_C2MISR_MISF26_Pos)            /*!< 0x04000000 */

+#define HSEM_C2MISR_MISF26        HSEM_C2MISR_MISF26_Msk                       /*!<semaphore 26 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF27_Pos    (27U)

+#define HSEM_C2MISR_MISF27_Msk    (0x1UL << HSEM_C2MISR_MISF27_Pos)            /*!< 0x08000000 */

+#define HSEM_C2MISR_MISF27        HSEM_C2MISR_MISF27_Msk                       /*!<semaphore 27 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF28_Pos    (28U)

+#define HSEM_C2MISR_MISF28_Msk    (0x1UL << HSEM_C2MISR_MISF28_Pos)            /*!< 0x10000000 */

+#define HSEM_C2MISR_MISF28        HSEM_C2MISR_MISF28_Msk                       /*!<semaphore 28 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF29_Pos    (29U)

+#define HSEM_C2MISR_MISF29_Msk    (0x1UL << HSEM_C2MISR_MISF29_Pos)            /*!< 0x20000000 */

+#define HSEM_C2MISR_MISF29        HSEM_C2MISR_MISF29_Msk                       /*!<semaphore 29 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF30_Pos    (30U)

+#define HSEM_C2MISR_MISF30_Msk    (0x1UL << HSEM_C2MISR_MISF30_Pos)            /*!< 0x40000000 */

+#define HSEM_C2MISR_MISF30        HSEM_C2MISR_MISF30_Msk                       /*!<semaphore 30 interrupt 1 masked status bit. */

+#define HSEM_C2MISR_MISF31_Pos    (31U)

+#define HSEM_C2MISR_MISF31_Msk    (0x1UL << HSEM_C2MISR_MISF31_Pos)            /*!< 0x80000000 */

+#define HSEM_C2MISR_MISF31        HSEM_C2MISR_MISF31_Msk                       /*!<semaphore 31 interrupt 1 masked status bit. */

+/********************  Bit definition for HSEM_CR register  *****************/

+#define HSEM_CR_COREID_Pos        (8U)

+#define HSEM_CR_COREID_Msk        (0xFFUL << HSEM_CR_COREID_Pos)               /*!< 0x0000FF00 */

+#define HSEM_CR_COREID            HSEM_CR_COREID_Msk                           /*!<CoreID of semaphores to be cleared. */

+#define HSEM_CR_KEY_Pos           (16U)

+#define HSEM_CR_KEY_Msk           (0xFFFFUL << HSEM_CR_KEY_Pos)                /*!< 0xFFFF0000 */

+#define HSEM_CR_KEY               HSEM_CR_KEY_Msk                              /*!<semaphores clear key. */

+

+/********************  Bit definition for HSEM_KEYR register  *****************/

+#define HSEM_KEYR_KEY_Pos         (16U)

+#define HSEM_KEYR_KEY_Msk         (0xFFFFUL << HSEM_KEYR_KEY_Pos)              /*!< 0xFFFF0000 */

+#define HSEM_KEYR_KEY             HSEM_KEYR_KEY_Msk                            /*!<semaphores clear key. */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    HASH                                    */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bits definition for HASH_CR register  ********************/

+#define HASH_CR_INIT_Pos          (2U)

+#define HASH_CR_INIT_Msk          (0x1UL << HASH_CR_INIT_Pos)                  /*!< 0x00000004 */

+#define HASH_CR_INIT              HASH_CR_INIT_Msk

+#define HASH_CR_DMAE_Pos          (3U)

+#define HASH_CR_DMAE_Msk          (0x1UL << HASH_CR_DMAE_Pos)                  /*!< 0x00000008 */

+#define HASH_CR_DMAE              HASH_CR_DMAE_Msk

+#define HASH_CR_DATATYPE_Pos      (4U)

+#define HASH_CR_DATATYPE_Msk      (0x3UL << HASH_CR_DATATYPE_Pos)              /*!< 0x00000030 */

+#define HASH_CR_DATATYPE          HASH_CR_DATATYPE_Msk

+#define HASH_CR_DATATYPE_0        (0x1UL << HASH_CR_DATATYPE_Pos)               /*!< 0x00000010 */

+#define HASH_CR_DATATYPE_1        (0x2UL << HASH_CR_DATATYPE_Pos)               /*!< 0x00000020 */

+#define HASH_CR_MODE_Pos          (6U)

+#define HASH_CR_MODE_Msk          (0x1UL << HASH_CR_MODE_Pos)                  /*!< 0x00000040 */

+#define HASH_CR_MODE              HASH_CR_MODE_Msk

+#define HASH_CR_ALGO_Pos          (7U)

+#define HASH_CR_ALGO_Msk          (0x801UL << HASH_CR_ALGO_Pos)                /*!< 0x00040080 */

+#define HASH_CR_ALGO              HASH_CR_ALGO_Msk

+#define HASH_CR_ALGO_0            (0x001UL << HASH_CR_ALGO_Pos)                 /*!< 0x00000080 */

+#define HASH_CR_ALGO_1            (0x800UL << HASH_CR_ALGO_Pos)                 /*!< 0x00040000 */

+#define HASH_CR_NBW_Pos           (8U)

+#define HASH_CR_NBW_Msk           (0xFUL << HASH_CR_NBW_Pos)                   /*!< 0x00000F00 */

+#define HASH_CR_NBW               HASH_CR_NBW_Msk

+#define HASH_CR_NBW_0             (0x1UL << HASH_CR_NBW_Pos)                    /*!< 0x00000100 */

+#define HASH_CR_NBW_1             (0x2UL << HASH_CR_NBW_Pos)                    /*!< 0x00000200 */

+#define HASH_CR_NBW_2             (0x4UL << HASH_CR_NBW_Pos)                    /*!< 0x00000400 */

+#define HASH_CR_NBW_3             (0x8UL << HASH_CR_NBW_Pos)                    /*!< 0x00000800 */

+#define HASH_CR_DINNE_Pos         (12U)

+#define HASH_CR_DINNE_Msk         (0x1UL << HASH_CR_DINNE_Pos)                 /*!< 0x00001000 */

+#define HASH_CR_DINNE             HASH_CR_DINNE_Msk

+#define HASH_CR_MDMAT_Pos         (13U)

+#define HASH_CR_MDMAT_Msk         (0x1UL << HASH_CR_MDMAT_Pos)                 /*!< 0x00002000 */

+#define HASH_CR_MDMAT             HASH_CR_MDMAT_Msk

+#define HASH_CR_LKEY_Pos          (16U)

+#define HASH_CR_LKEY_Msk          (0x1UL << HASH_CR_LKEY_Pos)                  /*!< 0x00010000 */

+#define HASH_CR_LKEY              HASH_CR_LKEY_Msk

+

+/******************  Bits definition for HASH_STR register  *******************/

+#define HASH_STR_NBLW_Pos         (0U)

+#define HASH_STR_NBLW_Msk         (0x1FUL << HASH_STR_NBLW_Pos)                /*!< 0x0000001F */

+#define HASH_STR_NBLW             HASH_STR_NBLW_Msk

+#define HASH_STR_NBLW_0           (0x01UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000001 */

+#define HASH_STR_NBLW_1           (0x02UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000002 */

+#define HASH_STR_NBLW_2           (0x04UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000004 */

+#define HASH_STR_NBLW_3           (0x08UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000008 */

+#define HASH_STR_NBLW_4           (0x10UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000010 */

+#define HASH_STR_DCAL_Pos         (8U)

+#define HASH_STR_DCAL_Msk         (0x1UL << HASH_STR_DCAL_Pos)                 /*!< 0x00000100 */

+#define HASH_STR_DCAL             HASH_STR_DCAL_Msk

+

+/******************  Bits definition for HASH_IMR register  *******************/

+#define HASH_IMR_DINIE_Pos        (0U)

+#define HASH_IMR_DINIE_Msk        (0x1UL << HASH_IMR_DINIE_Pos)                /*!< 0x00000001 */

+#define HASH_IMR_DINIE            HASH_IMR_DINIE_Msk

+#define HASH_IMR_DCIE_Pos         (1U)

+#define HASH_IMR_DCIE_Msk         (0x1UL << HASH_IMR_DCIE_Pos)                 /*!< 0x00000002 */

+#define HASH_IMR_DCIE             HASH_IMR_DCIE_Msk

+

+/******************  Bits definition for HASH_SR register  ********************/

+#define HASH_SR_DINIS_Pos         (0U)

+#define HASH_SR_DINIS_Msk         (0x1UL << HASH_SR_DINIS_Pos)                 /*!< 0x00000001 */

+#define HASH_SR_DINIS             HASH_SR_DINIS_Msk

+#define HASH_SR_DCIS_Pos          (1U)

+#define HASH_SR_DCIS_Msk          (0x1UL << HASH_SR_DCIS_Pos)                  /*!< 0x00000002 */

+#define HASH_SR_DCIS              HASH_SR_DCIS_Msk

+#define HASH_SR_DMAS_Pos          (2U)

+#define HASH_SR_DMAS_Msk          (0x1UL << HASH_SR_DMAS_Pos)                  /*!< 0x00000004 */

+#define HASH_SR_DMAS              HASH_SR_DMAS_Msk

+#define HASH_SR_BUSY_Pos          (3U)

+#define HASH_SR_BUSY_Msk          (0x1UL << HASH_SR_BUSY_Pos)                  /*!< 0x00000008 */

+#define HASH_SR_BUSY              HASH_SR_BUSY_Msk

+/******************************************************************************/

+/*                                                                            */

+/*                      Inter-integrated Circuit Interface (I2C)              */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for I2C_CR1 register  *******************/

+#define I2C_CR1_PE_Pos               (0U)

+#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */

+#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */

+#define I2C_CR1_TXIE_Pos             (1U)

+#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */

+#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */

+#define I2C_CR1_RXIE_Pos             (2U)

+#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */

+#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */

+#define I2C_CR1_ADDRIE_Pos           (3U)

+#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */

+#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */

+#define I2C_CR1_NACKIE_Pos           (4U)

+#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */

+#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */

+#define I2C_CR1_STOPIE_Pos           (5U)

+#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */

+#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */

+#define I2C_CR1_TCIE_Pos             (6U)

+#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */

+#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */

+#define I2C_CR1_ERRIE_Pos            (7U)

+#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */

+#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */

+#define I2C_CR1_DNF_Pos              (8U)

+#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */

+#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */

+#define I2C_CR1_ANFOFF_Pos           (12U)

+#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */

+#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */

+#define I2C_CR1_TXDMAEN_Pos          (14U)

+#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */

+#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */

+#define I2C_CR1_RXDMAEN_Pos          (15U)

+#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */

+#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */

+#define I2C_CR1_SBC_Pos              (16U)

+#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */

+#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */

+#define I2C_CR1_NOSTRETCH_Pos        (17U)

+#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */

+#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */

+#define I2C_CR1_WUPEN_Pos            (18U)

+#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */

+#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */

+#define I2C_CR1_GCEN_Pos             (19U)

+#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */

+#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */

+#define I2C_CR1_SMBHEN_Pos           (20U)

+#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */

+#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */

+#define I2C_CR1_SMBDEN_Pos           (21U)

+#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */

+#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */

+#define I2C_CR1_ALERTEN_Pos          (22U)

+#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */

+#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */

+#define I2C_CR1_PECEN_Pos            (23U)

+#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */

+#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */

+

+/******************  Bit definition for I2C_CR2 register  ********************/

+#define I2C_CR2_SADD_Pos             (0U)

+#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */

+#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */

+#define I2C_CR2_RD_WRN_Pos           (10U)

+#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */

+#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */

+#define I2C_CR2_ADD10_Pos            (11U)

+#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */

+#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */

+#define I2C_CR2_HEAD10R_Pos          (12U)

+#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */

+#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */

+#define I2C_CR2_START_Pos            (13U)

+#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */

+#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */

+#define I2C_CR2_STOP_Pos             (14U)

+#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */

+#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */

+#define I2C_CR2_NACK_Pos             (15U)

+#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */

+#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */

+#define I2C_CR2_NBYTES_Pos           (16U)

+#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */

+#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */

+#define I2C_CR2_RELOAD_Pos           (24U)

+#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */

+#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */

+#define I2C_CR2_AUTOEND_Pos          (25U)

+#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */

+#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */

+#define I2C_CR2_PECBYTE_Pos          (26U)

+#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */

+#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */

+

+/*******************  Bit definition for I2C_OAR1 register  ******************/

+#define I2C_OAR1_OA1_Pos             (0U)

+#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */

+#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */

+#define I2C_OAR1_OA1MODE_Pos         (10U)

+#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */

+#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */

+#define I2C_OAR1_OA1EN_Pos           (15U)

+#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */

+#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */

+

+/*******************  Bit definition for I2C_OAR2 register  ******************/

+#define I2C_OAR2_OA2_Pos             (1U)

+#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */

+#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */

+#define I2C_OAR2_OA2MSK_Pos          (8U)

+#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */

+#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */

+#define I2C_OAR2_OA2NOMASK           0x00000000UL                              /*!< No mask */

+#define I2C_OAR2_OA2MASK01_Pos       (8U)

+#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */

+#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared */

+#define I2C_OAR2_OA2MASK02_Pos       (9U)

+#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */

+#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */

+#define I2C_OAR2_OA2MASK03_Pos       (8U)

+#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */

+#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */

+#define I2C_OAR2_OA2MASK04_Pos       (10U)

+#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */

+#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */

+#define I2C_OAR2_OA2MASK05_Pos       (8U)

+#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */

+#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */

+#define I2C_OAR2_OA2MASK06_Pos       (9U)

+#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */

+#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared */

+#define I2C_OAR2_OA2MASK07_Pos       (8U)

+#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */

+#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done */

+#define I2C_OAR2_OA2EN_Pos           (15U)

+#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */

+#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */

+

+/*******************  Bit definition for I2C_TIMINGR register *******************/

+#define I2C_TIMINGR_SCLL_Pos         (0U)

+#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */

+#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */

+#define I2C_TIMINGR_SCLH_Pos         (8U)

+#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */

+#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */

+#define I2C_TIMINGR_SDADEL_Pos       (16U)

+#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */

+#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */

+#define I2C_TIMINGR_SCLDEL_Pos       (20U)

+#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */

+#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */

+#define I2C_TIMINGR_PRESC_Pos        (28U)

+#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */

+#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */

+

+/******************* Bit definition for I2C_TIMEOUTR register *******************/

+#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)

+#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */

+#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */

+#define I2C_TIMEOUTR_TIDLE_Pos       (12U)

+#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */

+#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */

+#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)

+#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */

+#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */

+#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)

+#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */

+#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/

+#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)

+#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */

+#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */

+

+/******************  Bit definition for I2C_ISR register  *********************/

+#define I2C_ISR_TXE_Pos              (0U)

+#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */

+#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */

+#define I2C_ISR_TXIS_Pos             (1U)

+#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */

+#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */

+#define I2C_ISR_RXNE_Pos             (2U)

+#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */

+#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */

+#define I2C_ISR_ADDR_Pos             (3U)

+#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */

+#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/

+#define I2C_ISR_NACKF_Pos            (4U)

+#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */

+#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */

+#define I2C_ISR_STOPF_Pos            (5U)

+#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */

+#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */

+#define I2C_ISR_TC_Pos               (6U)

+#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */

+#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */

+#define I2C_ISR_TCR_Pos              (7U)

+#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */

+#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */

+#define I2C_ISR_BERR_Pos             (8U)

+#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */

+#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */

+#define I2C_ISR_ARLO_Pos             (9U)

+#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */

+#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */

+#define I2C_ISR_OVR_Pos              (10U)

+#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */

+#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */

+#define I2C_ISR_PECERR_Pos           (11U)

+#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */

+#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */

+#define I2C_ISR_TIMEOUT_Pos          (12U)

+#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */

+#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */

+#define I2C_ISR_ALERT_Pos            (13U)

+#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */

+#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */

+#define I2C_ISR_BUSY_Pos             (15U)

+#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */

+#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */

+#define I2C_ISR_DIR_Pos              (16U)

+#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */

+#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */

+#define I2C_ISR_ADDCODE_Pos          (17U)

+#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */

+#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */

+

+/******************  Bit definition for I2C_ICR register  *********************/

+#define I2C_ICR_ADDRCF_Pos           (3U)

+#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */

+#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */

+#define I2C_ICR_NACKCF_Pos           (4U)

+#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */

+#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */

+#define I2C_ICR_STOPCF_Pos           (5U)

+#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */

+#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */

+#define I2C_ICR_BERRCF_Pos           (8U)

+#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */

+#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */

+#define I2C_ICR_ARLOCF_Pos           (9U)

+#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */

+#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */

+#define I2C_ICR_OVRCF_Pos            (10U)

+#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */

+#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */

+#define I2C_ICR_PECCF_Pos            (11U)

+#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */

+#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */

+#define I2C_ICR_TIMOUTCF_Pos         (12U)

+#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */

+#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */

+#define I2C_ICR_ALERTCF_Pos          (13U)

+#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */

+#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */

+

+/******************  Bit definition for I2C_PECR register  *********************/

+#define I2C_PECR_PEC_Pos             (0U)

+#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */

+#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */

+

+/******************  Bit definition for I2C_RXDR register  *********************/

+#define I2C_RXDR_RXDATA_Pos          (0U)

+#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */

+#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */

+

+/******************  Bit definition for I2C_TXDR register  *********************/

+#define I2C_TXDR_TXDATA_Pos          (0U)

+#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */

+#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           Independent WATCHDOG                             */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for IWDG_KR register  ********************/

+#define IWDG_KR_KEY_Pos      (0U)

+#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */

+#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */

+

+/*******************  Bit definition for IWDG_PR register  ********************/

+#define IWDG_PR_PR_Pos       (0U)

+#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */

+#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */

+#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */

+#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */

+#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */

+

+/*******************  Bit definition for IWDG_RLR register  *******************/

+#define IWDG_RLR_RL_Pos      (0U)

+#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */

+#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */

+

+/*******************  Bit definition for IWDG_SR register  ********************/

+#define IWDG_SR_PVU_Pos      (0U)

+#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */

+#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */

+#define IWDG_SR_RVU_Pos      (1U)

+#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */

+#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */

+#define IWDG_SR_WVU_Pos      (2U)

+#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */

+#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */

+

+/*******************  Bit definition for IWDG_KR register  ********************/

+#define IWDG_WINR_WIN_Pos    (0U)

+#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */

+#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */

+

+/******************************************************************************/

+/*                                                                            */

+/*                        JPEG Encoder/Decoder                                */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for CONFR0 register  ********************/

+#define JPEG_CONFR0_START_Pos           (0U)

+#define JPEG_CONFR0_START_Msk           (0x1UL << JPEG_CONFR0_START_Pos)       /*!< 0x00000001 */

+#define JPEG_CONFR0_START               JPEG_CONFR0_START_Msk                  /*!<Start/Stop bit */

+

+/********************  Bit definition for CONFR1 register  ********************/

+#define JPEG_CONFR1_NF_Pos              (0U)

+#define JPEG_CONFR1_NF_Msk              (0x3UL << JPEG_CONFR1_NF_Pos)          /*!< 0x00000003 */

+#define JPEG_CONFR1_NF                  JPEG_CONFR1_NF_Msk                     /*!<Number of color components */

+#define JPEG_CONFR1_NF_0                (0x1UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000001 */

+#define JPEG_CONFR1_NF_1                (0x2UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000002 */

+#define JPEG_CONFR1_DE_Pos              (3U)

+#define JPEG_CONFR1_DE_Msk              (0x1UL << JPEG_CONFR1_DE_Pos)          /*!< 0x00000008 */

+#define JPEG_CONFR1_DE                  JPEG_CONFR1_DE_Msk                     /*!<Decoding Enable */

+#define JPEG_CONFR1_COLORSPACE_Pos      (4U)

+#define JPEG_CONFR1_COLORSPACE_Msk      (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)  /*!< 0x00000030 */

+#define JPEG_CONFR1_COLORSPACE          JPEG_CONFR1_COLORSPACE_Msk             /*!<Color Space */

+#define JPEG_CONFR1_COLORSPACE_0        (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000010 */

+#define JPEG_CONFR1_COLORSPACE_1        (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000020 */

+#define JPEG_CONFR1_NS_Pos              (6U)

+#define JPEG_CONFR1_NS_Msk              (0x3UL << JPEG_CONFR1_NS_Pos)          /*!< 0x000000C0 */

+#define JPEG_CONFR1_NS                  JPEG_CONFR1_NS_Msk                     /*!<Number of components for Scan */

+#define JPEG_CONFR1_NS_0                (0x1UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR1_NS_1                (0x2UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR1_HDR_Pos             (8U)

+#define JPEG_CONFR1_HDR_Msk             (0x1UL << JPEG_CONFR1_HDR_Pos)         /*!< 0x00000100 */

+#define JPEG_CONFR1_HDR                 JPEG_CONFR1_HDR_Msk                    /*!<Header Processing On/Off */

+#define JPEG_CONFR1_YSIZE_Pos           (16U)

+#define JPEG_CONFR1_YSIZE_Msk           (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)    /*!< 0xFFFF0000 */

+#define JPEG_CONFR1_YSIZE               JPEG_CONFR1_YSIZE_Msk                  /*!<Number of lines in source image */

+

+/********************  Bit definition for CONFR2 register  ********************/

+#define JPEG_CONFR2_NMCU_Pos            (0U)

+#define JPEG_CONFR2_NMCU_Msk            (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)  /*!< 0x03FFFFFF */

+#define JPEG_CONFR2_NMCU                JPEG_CONFR2_NMCU_Msk                   /*!<Number of MCU units minus 1 to encode */

+

+/********************  Bit definition for CONFR3 register  ********************/

+#define JPEG_CONFR3_XSIZE_Pos           (16U)

+#define JPEG_CONFR3_XSIZE_Msk           (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)    /*!< 0xFFFF0000 */

+#define JPEG_CONFR3_XSIZE               JPEG_CONFR3_XSIZE_Msk                  /*!<Number of pixels per line */

+

+/********************  Bit definition for CONFR4 register  ********************/

+#define JPEG_CONFR4_HD_Pos              (0U)

+#define JPEG_CONFR4_HD_Msk              (0x1UL << JPEG_CONFR4_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR4_HD                  JPEG_CONFR4_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR4_HA_Pos              (1U)

+#define JPEG_CONFR4_HA_Msk              (0x1UL << JPEG_CONFR4_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR4_HA                  JPEG_CONFR4_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR4_QT_Pos              (2U)

+#define JPEG_CONFR4_QT_Msk              (0x3UL << JPEG_CONFR4_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR4_QT                  JPEG_CONFR4_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR4_QT_0                (0x1UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR4_QT_1                (0x2UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR4_NB_Pos              (4U)

+#define JPEG_CONFR4_NB_Msk              (0xFUL << JPEG_CONFR4_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR4_NB                  JPEG_CONFR4_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR4_NB_0                (0x1UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR4_NB_1                (0x2UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR4_NB_2                (0x4UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR4_NB_3                (0x8UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR4_VSF_Pos             (8U)

+#define JPEG_CONFR4_VSF_Msk             (0xFUL << JPEG_CONFR4_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR4_VSF                 JPEG_CONFR4_VSF_Msk                    /*!<Vertical sampling factor for component 1 */

+#define JPEG_CONFR4_VSF_0               (0x1UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR4_VSF_1               (0x2UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR4_VSF_2               (0x4UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR4_VSF_3               (0x8UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR4_HSF_Pos             (12U)

+#define JPEG_CONFR4_HSF_Msk             (0xFUL << JPEG_CONFR4_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR4_HSF                 JPEG_CONFR4_HSF_Msk                    /*!<Horizontal sampling factor for component 1 */

+#define JPEG_CONFR4_HSF_0               (0x1UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR4_HSF_1               (0x2UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR4_HSF_2               (0x4UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR4_HSF_3               (0x8UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR5 register  ********************/

+#define JPEG_CONFR5_HD_Pos              (0U)

+#define JPEG_CONFR5_HD_Msk              (0x1UL << JPEG_CONFR5_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR5_HD                  JPEG_CONFR5_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR5_HA_Pos              (1U)

+#define JPEG_CONFR5_HA_Msk              (0x1UL << JPEG_CONFR5_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR5_HA                  JPEG_CONFR5_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR5_QT_Pos              (2U)

+#define JPEG_CONFR5_QT_Msk              (0x3UL << JPEG_CONFR5_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR5_QT                  JPEG_CONFR5_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR5_QT_0                (0x1UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR5_QT_1                (0x2UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR5_NB_Pos              (4U)

+#define JPEG_CONFR5_NB_Msk              (0xFUL << JPEG_CONFR5_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR5_NB                  JPEG_CONFR5_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR5_NB_0                (0x1UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR5_NB_1                (0x2UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR5_NB_2                (0x4UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR5_NB_3                (0x8UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR5_VSF_Pos             (8U)

+#define JPEG_CONFR5_VSF_Msk             (0xFUL << JPEG_CONFR5_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR5_VSF                 JPEG_CONFR5_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR5_VSF_0               (0x1UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR5_VSF_1               (0x2UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR5_VSF_2               (0x4UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR5_VSF_3               (0x8UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR5_HSF_Pos             (12U)

+#define JPEG_CONFR5_HSF_Msk             (0xFUL << JPEG_CONFR5_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR5_HSF                 JPEG_CONFR5_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR5_HSF_0               (0x1UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR5_HSF_1               (0x2UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR5_HSF_2               (0x4UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR5_HSF_3               (0x8UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR6 register  ********************/

+#define JPEG_CONFR6_HD_Pos              (0U)

+#define JPEG_CONFR6_HD_Msk              (0x1UL << JPEG_CONFR6_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR6_HD                  JPEG_CONFR6_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR6_HA_Pos              (1U)

+#define JPEG_CONFR6_HA_Msk              (0x1UL << JPEG_CONFR6_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR6_HA                  JPEG_CONFR6_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR6_QT_Pos              (2U)

+#define JPEG_CONFR6_QT_Msk              (0x3UL << JPEG_CONFR6_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR6_QT                  JPEG_CONFR6_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR6_QT_0                (0x1UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR6_QT_1                (0x2UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR6_NB_Pos              (4U)

+#define JPEG_CONFR6_NB_Msk              (0xFUL << JPEG_CONFR6_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR6_NB                  JPEG_CONFR6_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR6_NB_0                (0x1UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR6_NB_1                (0x2UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR6_NB_2                (0x4UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR6_NB_3                (0x8UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR6_VSF_Pos             (8U)

+#define JPEG_CONFR6_VSF_Msk             (0xFUL << JPEG_CONFR6_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR6_VSF                 JPEG_CONFR6_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR6_VSF_0               (0x1UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR6_VSF_1               (0x2UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR6_VSF_2               (0x4UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR6_VSF_3               (0x8UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR6_HSF_Pos             (12U)

+#define JPEG_CONFR6_HSF_Msk             (0xFUL << JPEG_CONFR6_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR6_HSF                 JPEG_CONFR6_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR6_HSF_0               (0x1UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR6_HSF_1               (0x2UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR6_HSF_2               (0x4UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR6_HSF_3               (0x8UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR7 register  ********************/

+#define JPEG_CONFR7_HD_Pos              (0U)

+#define JPEG_CONFR7_HD_Msk              (0x1UL << JPEG_CONFR7_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR7_HD                  JPEG_CONFR7_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR7_HA_Pos              (1U)

+#define JPEG_CONFR7_HA_Msk              (0x1UL << JPEG_CONFR7_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR7_HA                  JPEG_CONFR7_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR7_QT_Pos              (2U)

+#define JPEG_CONFR7_QT_Msk              (0x3UL << JPEG_CONFR7_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR7_QT                  JPEG_CONFR7_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR7_QT_0                (0x1UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR7_QT_1                (0x2UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR7_NB_Pos              (4U)

+#define JPEG_CONFR7_NB_Msk              (0xFUL << JPEG_CONFR7_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR7_NB                  JPEG_CONFR7_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR7_NB_0                (0x1UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR7_NB_1                (0x2UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR7_NB_2                (0x4UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR7_NB_3                (0x8UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR7_VSF_Pos             (8U)

+#define JPEG_CONFR7_VSF_Msk             (0xFUL << JPEG_CONFR7_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR7_VSF                 JPEG_CONFR7_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR7_VSF_0               (0x1UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR7_VSF_1               (0x2UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR7_VSF_2               (0x4UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR7_VSF_3               (0x8UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR7_HSF_Pos             (12U)

+#define JPEG_CONFR7_HSF_Msk             (0xFUL << JPEG_CONFR7_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR7_HSF                 JPEG_CONFR7_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR7_HSF_0               (0x1UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR7_HSF_1               (0x2UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR7_HSF_2               (0x4UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR7_HSF_3               (0x8UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CR register  ********************/

+#define JPEG_CR_JCEN_Pos                (0U)

+#define JPEG_CR_JCEN_Msk                (0x1UL << JPEG_CR_JCEN_Pos)            /*!< 0x00000001 */

+#define JPEG_CR_JCEN                    JPEG_CR_JCEN_Msk                       /*!<Enable the JPEG Codec Core */

+#define JPEG_CR_IFTIE_Pos               (1U)

+#define JPEG_CR_IFTIE_Msk               (0x1UL << JPEG_CR_IFTIE_Pos)           /*!< 0x00000002 */

+#define JPEG_CR_IFTIE                   JPEG_CR_IFTIE_Msk                      /*!<Input FIFO Threshold Interrupt Enable */

+#define JPEG_CR_IFNFIE_Pos              (2U)

+#define JPEG_CR_IFNFIE_Msk              (0x1UL << JPEG_CR_IFNFIE_Pos)          /*!< 0x00000004 */

+#define JPEG_CR_IFNFIE                  JPEG_CR_IFNFIE_Msk                     /*!<Input FIFO Not Full Interrupt Enable */

+#define JPEG_CR_OFTIE_Pos               (3U)

+#define JPEG_CR_OFTIE_Msk               (0x1UL << JPEG_CR_OFTIE_Pos)           /*!< 0x00000008 */

+#define JPEG_CR_OFTIE                   JPEG_CR_OFTIE_Msk                      /*!<Output FIFO Threshold Interrupt Enable */

+#define JPEG_CR_OFNEIE_Pos              (4U)

+#define JPEG_CR_OFNEIE_Msk              (0x1UL << JPEG_CR_OFNEIE_Pos)          /*!< 0x00000010 */

+#define JPEG_CR_OFNEIE                  JPEG_CR_OFNEIE_Msk                     /*!<Output FIFO Not Empty Interrupt Enable */

+#define JPEG_CR_EOCIE_Pos               (5U)

+#define JPEG_CR_EOCIE_Msk               (0x1UL << JPEG_CR_EOCIE_Pos)           /*!< 0x00000020 */

+#define JPEG_CR_EOCIE                   JPEG_CR_EOCIE_Msk                      /*!<End of Conversion Interrupt Enable */

+#define JPEG_CR_HPDIE_Pos               (6U)

+#define JPEG_CR_HPDIE_Msk               (0x1UL << JPEG_CR_HPDIE_Pos)           /*!< 0x00000040 */

+#define JPEG_CR_HPDIE                   JPEG_CR_HPDIE_Msk                      /*!<Header Parsing Done Interrupt Enable */

+#define JPEG_CR_IFF_Pos                 (13U)

+#define JPEG_CR_IFF_Msk                 (0x1UL << JPEG_CR_IFF_Pos)             /*!< 0x00002000 */

+#define JPEG_CR_IFF                     JPEG_CR_IFF_Msk                        /*!<Flush the input FIFO */

+#define JPEG_CR_OFF_Pos                 (14U)

+#define JPEG_CR_OFF_Msk                 (0x1UL << JPEG_CR_OFF_Pos)             /*!< 0x00004000 */

+#define JPEG_CR_OFF                     JPEG_CR_OFF_Msk                        /*!<Flush the output FIFO */

+

+/********************  Bit definition for SR register  ********************/

+#define JPEG_SR_IFTF_Pos                (1U)

+#define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */

+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is bellow its threshold flag */

+#define JPEG_SR_IFNFF_Pos               (2U)

+#define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */

+#define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */

+#define JPEG_SR_OFTF_Pos                (3U)

+#define JPEG_SR_OFTF_Msk                (0x1UL << JPEG_SR_OFTF_Pos)            /*!< 0x00000008 */

+#define JPEG_SR_OFTF                    JPEG_SR_OFTF_Msk                       /*!<Output FIFO is not empty and has reach its threshold */

+#define JPEG_SR_OFNEF_Pos               (4U)

+#define JPEG_SR_OFNEF_Msk               (0x1UL << JPEG_SR_OFNEF_Pos)           /*!< 0x00000010 */

+#define JPEG_SR_OFNEF                   JPEG_SR_OFNEF_Msk                      /*!<Output FIFO is not empty, a data is available */

+#define JPEG_SR_EOCF_Pos                (5U)

+#define JPEG_SR_EOCF_Msk                (0x1UL << JPEG_SR_EOCF_Pos)            /*!< 0x00000020 */

+#define JPEG_SR_EOCF                    JPEG_SR_EOCF_Msk                       /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */

+#define JPEG_SR_HPDF_Pos                (6U)

+#define JPEG_SR_HPDF_Msk                (0x1UL << JPEG_SR_HPDF_Pos)            /*!< 0x00000040 */

+#define JPEG_SR_HPDF                    JPEG_SR_HPDF_Msk                       /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */

+#define JPEG_SR_COF_Pos                 (7U)

+#define JPEG_SR_COF_Msk                 (0x1UL << JPEG_SR_COF_Pos)             /*!< 0x00000080 */

+#define JPEG_SR_COF                     JPEG_SR_COF_Msk                        /*!<JPEG Codec operation on going flag */

+

+/********************  Bit definition for CFR register  ********************/

+#define JPEG_CFR_CEOCF_Pos              (4U)

+#define JPEG_CFR_CEOCF_Msk              (0x1UL << JPEG_CFR_CEOCF_Pos)          /*!< 0x00000010 */

+#define JPEG_CFR_CEOCF                  JPEG_CFR_CEOCF_Msk                     /*!<Clear End of Conversion Flag */

+#define JPEG_CFR_CHPDF_Pos              (5U)

+#define JPEG_CFR_CHPDF_Msk              (0x1UL << JPEG_CFR_CHPDF_Pos)          /*!< 0x00000020 */

+#define JPEG_CFR_CHPDF                  JPEG_CFR_CHPDF_Msk                     /*!<Clear Header Parsing Done Flag */

+

+/********************  Bit definition for DIR register  ********************/

+#define JPEG_DIR_DATAIN_Pos             (0U)

+#define JPEG_DIR_DATAIN_Msk             (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)  /*!< 0xFFFFFFFF */

+#define JPEG_DIR_DATAIN                 JPEG_DIR_DATAIN_Msk                    /*!<Data Input FIFO */

+

+/********************  Bit definition for DOR register  ********************/

+#define JPEG_DOR_DATAOUT_Pos            (0U)

+#define JPEG_DOR_DATAOUT_Msk            (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */

+#define JPEG_DOR_DATAOUT                JPEG_DOR_DATAOUT_Msk                   /*!<Data Output FIFO */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      LCD-TFT Display Controller (LTDC)                     */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for LTDC_SSCR register  *****************/

+

+#define LTDC_SSCR_VSH_Pos            (0U)

+#define LTDC_SSCR_VSH_Msk            (0x7FFUL << LTDC_SSCR_VSH_Pos)            /*!< 0x000007FF */

+#define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height  */

+#define LTDC_SSCR_HSW_Pos            (16U)

+#define LTDC_SSCR_HSW_Msk            (0xFFFUL << LTDC_SSCR_HSW_Pos)            /*!< 0x0FFF0000 */

+#define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */

+

+/********************  Bit definition for LTDC_BPCR register  *****************/

+

+#define LTDC_BPCR_AVBP_Pos           (0U)

+#define LTDC_BPCR_AVBP_Msk           (0x7FFUL << LTDC_BPCR_AVBP_Pos)           /*!< 0x000007FF */

+#define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch   */

+#define LTDC_BPCR_AHBP_Pos           (16U)

+#define LTDC_BPCR_AHBP_Msk           (0xFFFUL << LTDC_BPCR_AHBP_Pos)           /*!< 0x0FFF0000 */

+#define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */

+

+/********************  Bit definition for LTDC_AWCR register  *****************/

+

+#define LTDC_AWCR_AAH_Pos            (0U)

+#define LTDC_AWCR_AAH_Msk            (0x7FFUL << LTDC_AWCR_AAH_Pos)            /*!< 0x000007FF */

+#define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active heigh */

+#define LTDC_AWCR_AAW_Pos            (16U)

+#define LTDC_AWCR_AAW_Msk            (0xFFFUL << LTDC_AWCR_AAW_Pos)            /*!< 0x0FFF0000 */

+#define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */

+

+/********************  Bit definition for LTDC_TWCR register  *****************/

+

+#define LTDC_TWCR_TOTALH_Pos         (0U)

+#define LTDC_TWCR_TOTALH_Msk         (0x7FFUL << LTDC_TWCR_TOTALH_Pos)         /*!< 0x000007FF */

+#define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total Heigh */

+#define LTDC_TWCR_TOTALW_Pos         (16U)

+#define LTDC_TWCR_TOTALW_Msk         (0xFFFUL << LTDC_TWCR_TOTALW_Pos)         /*!< 0x0FFF0000 */

+#define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */

+

+/********************  Bit definition for LTDC_GCR register  ******************/

+

+#define LTDC_GCR_LTDCEN_Pos          (0U)

+#define LTDC_GCR_LTDCEN_Msk          (0x1UL << LTDC_GCR_LTDCEN_Pos)            /*!< 0x00000001 */

+#define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit       */

+#define LTDC_GCR_DBW_Pos             (4U)

+#define LTDC_GCR_DBW_Msk             (0x7UL << LTDC_GCR_DBW_Pos)               /*!< 0x00000070 */

+#define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width                   */

+#define LTDC_GCR_DGW_Pos             (8U)

+#define LTDC_GCR_DGW_Msk             (0x7UL << LTDC_GCR_DGW_Pos)               /*!< 0x00000700 */

+#define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width                  */

+#define LTDC_GCR_DRW_Pos             (12U)

+#define LTDC_GCR_DRW_Msk             (0x7UL << LTDC_GCR_DRW_Pos)               /*!< 0x00007000 */

+#define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width                    */

+#define LTDC_GCR_DEN_Pos             (16U)

+#define LTDC_GCR_DEN_Msk             (0x1UL << LTDC_GCR_DEN_Pos)               /*!< 0x00010000 */

+#define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable                       */

+#define LTDC_GCR_PCPOL_Pos           (28U)

+#define LTDC_GCR_PCPOL_Msk           (0x1UL << LTDC_GCR_PCPOL_Pos)             /*!< 0x10000000 */

+#define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity                */

+#define LTDC_GCR_DEPOL_Pos           (29U)

+#define LTDC_GCR_DEPOL_Msk           (0x1UL << LTDC_GCR_DEPOL_Pos)             /*!< 0x20000000 */

+#define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity                */

+#define LTDC_GCR_VSPOL_Pos           (30U)

+#define LTDC_GCR_VSPOL_Msk           (0x1UL << LTDC_GCR_VSPOL_Pos)             /*!< 0x40000000 */

+#define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity   */

+#define LTDC_GCR_HSPOL_Pos           (31U)

+#define LTDC_GCR_HSPOL_Msk           (0x1UL << LTDC_GCR_HSPOL_Pos)             /*!< 0x80000000 */

+#define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */

+

+

+/********************  Bit definition for LTDC_SRCR register  *****************/

+

+#define LTDC_SRCR_IMR_Pos            (0U)

+#define LTDC_SRCR_IMR_Msk            (0x1UL << LTDC_SRCR_IMR_Pos)              /*!< 0x00000001 */

+#define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload         */

+#define LTDC_SRCR_VBR_Pos            (1U)

+#define LTDC_SRCR_VBR_Msk            (0x1UL << LTDC_SRCR_VBR_Pos)              /*!< 0x00000002 */

+#define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */

+

+/********************  Bit definition for LTDC_BCCR register  *****************/

+

+#define LTDC_BCCR_BCBLUE_Pos         (0U)

+#define LTDC_BCCR_BCBLUE_Msk         (0xFFUL << LTDC_BCCR_BCBLUE_Pos)          /*!< 0x000000FF */

+#define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value  */

+#define LTDC_BCCR_BCGREEN_Pos        (8U)

+#define LTDC_BCCR_BCGREEN_Msk        (0xFFUL << LTDC_BCCR_BCGREEN_Pos)         /*!< 0x0000FF00 */

+#define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */

+#define LTDC_BCCR_BCRED_Pos          (16U)

+#define LTDC_BCCR_BCRED_Msk          (0xFFUL << LTDC_BCCR_BCRED_Pos)           /*!< 0x00FF0000 */

+#define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value   */

+

+/********************  Bit definition for LTDC_IER register  ******************/

+

+#define LTDC_IER_LIE_Pos             (0U)

+#define LTDC_IER_LIE_Msk             (0x1UL << LTDC_IER_LIE_Pos)               /*!< 0x00000001 */

+#define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable            */

+#define LTDC_IER_FUIE_Pos            (1U)

+#define LTDC_IER_FUIE_Msk            (0x1UL << LTDC_IER_FUIE_Pos)              /*!< 0x00000002 */

+#define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable   */

+#define LTDC_IER_TERRIE_Pos          (2U)

+#define LTDC_IER_TERRIE_Msk          (0x1UL << LTDC_IER_TERRIE_Pos)            /*!< 0x00000004 */

+#define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable  */

+#define LTDC_IER_RRIE_Pos            (3U)

+#define LTDC_IER_RRIE_Msk            (0x1UL << LTDC_IER_RRIE_Pos)              /*!< 0x00000008 */

+#define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */

+

+/********************  Bit definition for LTDC_ISR register  ******************/

+

+#define LTDC_ISR_LIF_Pos             (0U)

+#define LTDC_ISR_LIF_Msk             (0x1UL << LTDC_ISR_LIF_Pos)               /*!< 0x00000001 */

+#define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */

+#define LTDC_ISR_FUIF_Pos            (1U)

+#define LTDC_ISR_FUIF_Msk            (0x1UL << LTDC_ISR_FUIF_Pos)              /*!< 0x00000002 */

+#define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */

+#define LTDC_ISR_TERRIF_Pos          (2U)

+#define LTDC_ISR_TERRIF_Msk          (0x1UL << LTDC_ISR_TERRIF_Pos)            /*!< 0x00000004 */

+#define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */

+#define LTDC_ISR_RRIF_Pos            (3U)

+#define LTDC_ISR_RRIF_Msk            (0x1UL << LTDC_ISR_RRIF_Pos)              /*!< 0x00000008 */

+#define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */

+

+/********************  Bit definition for LTDC_ICR register  ******************/

+

+#define LTDC_ICR_CLIF_Pos            (0U)

+#define LTDC_ICR_CLIF_Msk            (0x1UL << LTDC_ICR_CLIF_Pos)              /*!< 0x00000001 */

+#define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */

+#define LTDC_ICR_CFUIF_Pos           (1U)

+#define LTDC_ICR_CFUIF_Msk           (0x1UL << LTDC_ICR_CFUIF_Pos)             /*!< 0x00000002 */

+#define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */

+#define LTDC_ICR_CTERRIF_Pos         (2U)

+#define LTDC_ICR_CTERRIF_Msk         (0x1UL << LTDC_ICR_CTERRIF_Pos)           /*!< 0x00000004 */

+#define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */

+#define LTDC_ICR_CRRIF_Pos           (3U)

+#define LTDC_ICR_CRRIF_Msk           (0x1UL << LTDC_ICR_CRRIF_Pos)             /*!< 0x00000008 */

+#define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */

+

+/********************  Bit definition for LTDC_LIPCR register  ****************/

+

+#define LTDC_LIPCR_LIPOS_Pos         (0U)

+#define LTDC_LIPCR_LIPOS_Msk         (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)         /*!< 0x000007FF */

+#define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */

+

+/********************  Bit definition for LTDC_CPSR register  *****************/

+

+#define LTDC_CPSR_CYPOS_Pos          (0U)

+#define LTDC_CPSR_CYPOS_Msk          (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)         /*!< 0x0000FFFF */

+#define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */

+#define LTDC_CPSR_CXPOS_Pos          (16U)

+#define LTDC_CPSR_CXPOS_Msk          (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)         /*!< 0xFFFF0000 */

+#define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */

+

+/********************  Bit definition for LTDC_CDSR register  *****************/

+

+#define LTDC_CDSR_VDES_Pos           (0U)

+#define LTDC_CDSR_VDES_Msk           (0x1UL << LTDC_CDSR_VDES_Pos)             /*!< 0x00000001 */

+#define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status       */

+#define LTDC_CDSR_HDES_Pos           (1U)

+#define LTDC_CDSR_HDES_Msk           (0x1UL << LTDC_CDSR_HDES_Pos)             /*!< 0x00000002 */

+#define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status     */

+#define LTDC_CDSR_VSYNCS_Pos         (2U)

+#define LTDC_CDSR_VSYNCS_Msk         (0x1UL << LTDC_CDSR_VSYNCS_Pos)           /*!< 0x00000004 */

+#define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status   */

+#define LTDC_CDSR_HSYNCS_Pos         (3U)

+#define LTDC_CDSR_HSYNCS_Msk         (0x1UL << LTDC_CDSR_HSYNCS_Pos)           /*!< 0x00000008 */

+#define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */

+

+/********************  Bit definition for LTDC_LxCR register  *****************/

+

+#define LTDC_LxCR_LEN_Pos            (0U)

+#define LTDC_LxCR_LEN_Msk            (0x1UL << LTDC_LxCR_LEN_Pos)              /*!< 0x00000001 */

+#define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable              */

+#define LTDC_LxCR_COLKEN_Pos         (1U)

+#define LTDC_LxCR_COLKEN_Msk         (0x1UL << LTDC_LxCR_COLKEN_Pos)           /*!< 0x00000002 */

+#define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable       */

+#define LTDC_LxCR_CLUTEN_Pos         (4U)

+#define LTDC_LxCR_CLUTEN_Msk         (0x1UL << LTDC_LxCR_CLUTEN_Pos)           /*!< 0x00000010 */

+#define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */

+

+/********************  Bit definition for LTDC_LxWHPCR register  **************/

+

+#define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)

+#define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)     /*!< 0x00000FFF */

+#define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */

+#define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)

+#define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)    /*!< 0xFFFF0000 */

+#define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position  */

+

+/********************  Bit definition for LTDC_LxWVPCR register  **************/

+

+#define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)

+#define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)     /*!< 0x00000FFF */

+#define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */

+#define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)

+#define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)    /*!< 0xFFFF0000 */

+#define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position  */

+

+/********************  Bit definition for LTDC_LxCKCR register  ***************/

+

+#define LTDC_LxCKCR_CKBLUE_Pos       (0U)

+#define LTDC_LxCKCR_CKBLUE_Msk       (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value  */

+#define LTDC_LxCKCR_CKGREEN_Pos      (8U)

+#define LTDC_LxCKCR_CKGREEN_Msk      (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */

+#define LTDC_LxCKCR_CKRED_Pos        (16U)

+#define LTDC_LxCKCR_CKRED_Msk        (0xFFUL << LTDC_LxCKCR_CKRED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value   */

+

+/********************  Bit definition for LTDC_LxPFCR register  ***************/

+

+#define LTDC_LxPFCR_PF_Pos           (0U)

+#define LTDC_LxPFCR_PF_Msk           (0x7UL << LTDC_LxPFCR_PF_Pos)             /*!< 0x00000007 */

+#define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */

+

+/********************  Bit definition for LTDC_LxCACR register  ***************/

+

+#define LTDC_LxCACR_CONSTA_Pos       (0U)

+#define LTDC_LxCACR_CONSTA_Msk       (0xFFUL << LTDC_LxCACR_CONSTA_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */

+

+/********************  Bit definition for LTDC_LxDCCR register  ***************/

+

+#define LTDC_LxDCCR_DCBLUE_Pos       (0U)

+#define LTDC_LxDCCR_DCBLUE_Msk       (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue  */

+#define LTDC_LxDCCR_DCGREEN_Pos      (8U)

+#define LTDC_LxDCCR_DCGREEN_Msk      (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */

+#define LTDC_LxDCCR_DCRED_Pos        (16U)

+#define LTDC_LxDCCR_DCRED_Msk        (0xFFUL << LTDC_LxDCCR_DCRED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red   */

+#define LTDC_LxDCCR_DCALPHA_Pos      (24U)

+#define LTDC_LxDCCR_DCALPHA_Msk      (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)       /*!< 0xFF000000 */

+#define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */

+

+/********************  Bit definition for LTDC_LxBFCR register  ***************/

+

+#define LTDC_LxBFCR_BF2_Pos          (0U)

+#define LTDC_LxBFCR_BF2_Msk          (0x7UL << LTDC_LxBFCR_BF2_Pos)            /*!< 0x00000007 */

+#define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */

+#define LTDC_LxBFCR_BF1_Pos          (8U)

+#define LTDC_LxBFCR_BF1_Msk          (0x7UL << LTDC_LxBFCR_BF1_Pos)            /*!< 0x00000700 */

+#define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */

+

+/********************  Bit definition for LTDC_LxCFBAR register  **************/

+

+#define LTDC_LxCFBAR_CFBADD_Pos      (0U)

+#define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */

+#define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */

+

+/********************  Bit definition for LTDC_LxCFBLR register  **************/

+

+#define LTDC_LxCFBLR_CFBLL_Pos       (0U)

+#define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)      /*!< 0x00001FFF */

+#define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length    */

+#define LTDC_LxCFBLR_CFBP_Pos        (16U)

+#define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)       /*!< 0x1FFF0000 */

+#define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */

+

+/********************  Bit definition for LTDC_LxCFBLNR register  *************/

+

+#define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)

+#define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)    /*!< 0x000007FF */

+#define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */

+

+/********************  Bit definition for LTDC_LxCLUTWR register  *************/

+

+#define LTDC_LxCLUTWR_BLUE_Pos       (0U)

+#define LTDC_LxCLUTWR_BLUE_Msk       (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value   */

+#define LTDC_LxCLUTWR_GREEN_Pos      (8U)

+#define LTDC_LxCLUTWR_GREEN_Msk      (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value  */

+#define LTDC_LxCLUTWR_RED_Pos        (16U)

+#define LTDC_LxCLUTWR_RED_Msk        (0xFFUL << LTDC_LxCLUTWR_RED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value    */

+#define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)

+#define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)     /*!< 0xFF000000 */

+#define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                     MDMA                                   */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for MDMA_GISR0 register  ****************/

+#define MDMA_GISR0_GIF0_Pos       (0U)

+#define MDMA_GISR0_GIF0_Msk       (0x1UL << MDMA_GISR0_GIF0_Pos)               /*!< 0x00000001 */

+#define MDMA_GISR0_GIF0           MDMA_GISR0_GIF0_Msk                          /*!< Channel 0 global interrupt flag */

+#define MDMA_GISR0_GIF1_Pos       (1U)

+#define MDMA_GISR0_GIF1_Msk       (0x1UL << MDMA_GISR0_GIF1_Pos)               /*!< 0x00000002 */

+#define MDMA_GISR0_GIF1           MDMA_GISR0_GIF1_Msk                          /*!< Channel 1 global interrupt flag */

+#define MDMA_GISR0_GIF2_Pos       (2U)

+#define MDMA_GISR0_GIF2_Msk       (0x1UL << MDMA_GISR0_GIF2_Pos)               /*!< 0x00000004 */

+#define MDMA_GISR0_GIF2           MDMA_GISR0_GIF2_Msk                          /*!< Channel 2 global interrupt flag */

+#define MDMA_GISR0_GIF3_Pos       (3U)

+#define MDMA_GISR0_GIF3_Msk       (0x1UL << MDMA_GISR0_GIF3_Pos)               /*!< 0x00000008 */

+#define MDMA_GISR0_GIF3           MDMA_GISR0_GIF3_Msk                          /*!< Channel 3 global interrupt flag */

+#define MDMA_GISR0_GIF4_Pos       (4U)

+#define MDMA_GISR0_GIF4_Msk       (0x1UL << MDMA_GISR0_GIF4_Pos)               /*!< 0x00000010 */

+#define MDMA_GISR0_GIF4           MDMA_GISR0_GIF4_Msk                          /*!< Channel 4 global interrupt flag */

+#define MDMA_GISR0_GIF5_Pos       (5U)

+#define MDMA_GISR0_GIF5_Msk       (0x1UL << MDMA_GISR0_GIF5_Pos)               /*!< 0x00000020 */

+#define MDMA_GISR0_GIF5           MDMA_GISR0_GIF5_Msk                          /*!< Channel 5 global interrupt flag */

+#define MDMA_GISR0_GIF6_Pos       (6U)

+#define MDMA_GISR0_GIF6_Msk       (0x1UL << MDMA_GISR0_GIF6_Pos)               /*!< 0x00000040 */

+#define MDMA_GISR0_GIF6           MDMA_GISR0_GIF6_Msk                          /*!< Channel 6 global interrupt flag */

+#define MDMA_GISR0_GIF7_Pos       (7U)

+#define MDMA_GISR0_GIF7_Msk       (0x1UL << MDMA_GISR0_GIF7_Pos)               /*!< 0x00000080 */

+#define MDMA_GISR0_GIF7           MDMA_GISR0_GIF7_Msk                          /*!< Channel 7 global interrupt flag */

+#define MDMA_GISR0_GIF8_Pos       (8U)

+#define MDMA_GISR0_GIF8_Msk       (0x1UL << MDMA_GISR0_GIF8_Pos)               /*!< 0x00000100 */

+#define MDMA_GISR0_GIF8           MDMA_GISR0_GIF8_Msk                          /*!< Channel 8 global interrupt flag */

+#define MDMA_GISR0_GIF9_Pos       (9U)

+#define MDMA_GISR0_GIF9_Msk       (0x1UL << MDMA_GISR0_GIF9_Pos)               /*!< 0x00000200 */

+#define MDMA_GISR0_GIF9           MDMA_GISR0_GIF9_Msk                          /*!< Channel 9 global interrupt flag */

+#define MDMA_GISR0_GIF10_Pos      (10U)

+#define MDMA_GISR0_GIF10_Msk      (0x1UL << MDMA_GISR0_GIF10_Pos)              /*!< 0x00000400 */

+#define MDMA_GISR0_GIF10          MDMA_GISR0_GIF10_Msk                         /*!< Channel 10 global interrupt flag */

+#define MDMA_GISR0_GIF11_Pos      (11U)

+#define MDMA_GISR0_GIF11_Msk      (0x1UL << MDMA_GISR0_GIF11_Pos)              /*!< 0x00000800 */

+#define MDMA_GISR0_GIF11          MDMA_GISR0_GIF11_Msk                         /*!< Channel 11 global interrupt flag */

+#define MDMA_GISR0_GIF12_Pos      (12U)

+#define MDMA_GISR0_GIF12_Msk      (0x1UL << MDMA_GISR0_GIF12_Pos)              /*!< 0x00001000 */

+#define MDMA_GISR0_GIF12          MDMA_GISR0_GIF12_Msk                         /*!< Channel 12 global interrupt flag */

+#define MDMA_GISR0_GIF13_Pos      (13U)

+#define MDMA_GISR0_GIF13_Msk      (0x1UL << MDMA_GISR0_GIF13_Pos)              /*!< 0x00002000 */

+#define MDMA_GISR0_GIF13          MDMA_GISR0_GIF13_Msk                         /*!< Channel 13 global interrupt flag */

+#define MDMA_GISR0_GIF14_Pos      (14U)

+#define MDMA_GISR0_GIF14_Msk      (0x1UL << MDMA_GISR0_GIF14_Pos)              /*!< 0x00004000 */

+#define MDMA_GISR0_GIF14          MDMA_GISR0_GIF14_Msk                         /*!< Channel 14 global interrupt flag */

+#define MDMA_GISR0_GIF15_Pos      (15U)

+#define MDMA_GISR0_GIF15_Msk      (0x1UL << MDMA_GISR0_GIF15_Pos)              /*!< 0x00008000 */

+#define MDMA_GISR0_GIF15          MDMA_GISR0_GIF15_Msk                         /*!< Channel 15 global interrupt flag */

+

+/********************  Bit definition for MDMA_CxISR register  ****************/

+#define MDMA_CISR_TEIF_Pos        (0U)

+#define MDMA_CISR_TEIF_Msk        (0x1UL << MDMA_CISR_TEIF_Pos)                /*!< 0x00000001 */

+#define MDMA_CISR_TEIF            MDMA_CISR_TEIF_Msk                           /*!< Channel x transfer error interrupt flag */

+#define MDMA_CISR_CTCIF_Pos       (1U)

+#define MDMA_CISR_CTCIF_Msk       (0x1UL << MDMA_CISR_CTCIF_Pos)               /*!< 0x00000002 */

+#define MDMA_CISR_CTCIF           MDMA_CISR_CTCIF_Msk                          /*!< Channel x Channel Transfer Complete interrupt flag */

+#define MDMA_CISR_BRTIF_Pos       (2U)

+#define MDMA_CISR_BRTIF_Msk       (0x1UL << MDMA_CISR_BRTIF_Pos)               /*!< 0x00000004 */

+#define MDMA_CISR_BRTIF           MDMA_CISR_BRTIF_Msk                          /*!< Channel x block repeat transfer complete interrupt flag */

+#define MDMA_CISR_BTIF_Pos        (3U)

+#define MDMA_CISR_BTIF_Msk        (0x1UL << MDMA_CISR_BTIF_Pos)                /*!< 0x00000008 */

+#define MDMA_CISR_BTIF            MDMA_CISR_BTIF_Msk                           /*!< Channel x block transfer complete interrupt flag */

+#define MDMA_CISR_TCIF_Pos        (4U)

+#define MDMA_CISR_TCIF_Msk        (0x1UL << MDMA_CISR_TCIF_Pos)                /*!< 0x00000010 */

+#define MDMA_CISR_TCIF            MDMA_CISR_TCIF_Msk                           /*!< Channel x buffer transfer complete interrupt flag */

+#define MDMA_CISR_CRQA_Pos        (16U)

+#define MDMA_CISR_CRQA_Msk        (0x1UL << MDMA_CISR_CRQA_Pos)                /*!< 0x00010000 */

+#define MDMA_CISR_CRQA            MDMA_CISR_CRQA_Msk                           /*!< Channel x ReQest Active flag */

+

+/********************  Bit definition for MDMA_CxIFCR register  ****************/

+#define MDMA_CIFCR_CTEIF_Pos      (0U)

+#define MDMA_CIFCR_CTEIF_Msk      (0x1UL << MDMA_CIFCR_CTEIF_Pos)              /*!< 0x00000001 */

+#define MDMA_CIFCR_CTEIF          MDMA_CIFCR_CTEIF_Msk                         /*!< Channel x clear transfer error interrupt flag */

+#define MDMA_CIFCR_CCTCIF_Pos     (1U)

+#define MDMA_CIFCR_CCTCIF_Msk     (0x1UL << MDMA_CIFCR_CCTCIF_Pos)             /*!< 0x00000002 */

+#define MDMA_CIFCR_CCTCIF         MDMA_CIFCR_CCTCIF_Msk                        /*!< Clear Channel transfer complete interrupt flag for channel x */

+#define MDMA_CIFCR_CBRTIF_Pos     (2U)

+#define MDMA_CIFCR_CBRTIF_Msk     (0x1UL << MDMA_CIFCR_CBRTIF_Pos)             /*!< 0x00000004 */

+#define MDMA_CIFCR_CBRTIF         MDMA_CIFCR_CBRTIF_Msk                        /*!< Channel x clear block repeat transfer complete interrupt flag */

+#define MDMA_CIFCR_CBTIF_Pos      (3U)

+#define MDMA_CIFCR_CBTIF_Msk      (0x1UL << MDMA_CIFCR_CBTIF_Pos)              /*!< 0x00000008 */

+#define MDMA_CIFCR_CBTIF          MDMA_CIFCR_CBTIF_Msk                         /*!< Channel x Clear block transfer complete interrupt flag */

+#define MDMA_CIFCR_CLTCIF_Pos     (4U)

+#define MDMA_CIFCR_CLTCIF_Msk     (0x1UL << MDMA_CIFCR_CLTCIF_Pos)             /*!< 0x00000010 */

+#define MDMA_CIFCR_CLTCIF         MDMA_CIFCR_CLTCIF_Msk                        /*!< CLear Transfer buffer Complete Interrupt Flag for channel */

+

+/********************  Bit definition for MDMA_CxESR register  ****************/

+#define MDMA_CESR_TEA_Pos         (0U)

+#define MDMA_CESR_TEA_Msk         (0x7FUL << MDMA_CESR_TEA_Pos)                /*!< 0x0000007F */

+#define MDMA_CESR_TEA             MDMA_CESR_TEA_Msk                            /*!< Transfer Error Address */

+#define MDMA_CESR_TED_Pos         (7U)

+#define MDMA_CESR_TED_Msk         (0x1UL << MDMA_CESR_TED_Pos)                 /*!< 0x00000080 */

+#define MDMA_CESR_TED             MDMA_CESR_TED_Msk                            /*!< Transfer Error Direction */

+#define MDMA_CESR_TELD_Pos        (8U)

+#define MDMA_CESR_TELD_Msk        (0x1UL << MDMA_CESR_TELD_Pos)                /*!< 0x00000100 */

+#define MDMA_CESR_TELD            MDMA_CESR_TELD_Msk                           /*!< Transfer Error Link Data */

+#define MDMA_CESR_TEMD_Pos        (9U)

+#define MDMA_CESR_TEMD_Msk        (0x1UL << MDMA_CESR_TEMD_Pos)                /*!< 0x00000200 */

+#define MDMA_CESR_TEMD            MDMA_CESR_TEMD_Msk                           /*!< Transfer Error Mask Data */

+#define MDMA_CESR_ASE_Pos         (10U)

+#define MDMA_CESR_ASE_Msk         (0x1UL << MDMA_CESR_ASE_Pos)                 /*!< 0x00000400 */

+#define MDMA_CESR_ASE             MDMA_CESR_ASE_Msk                            /*!< Address/Size Error       */

+#define MDMA_CESR_BSE_Pos         (11U)

+#define MDMA_CESR_BSE_Msk         (0x1UL << MDMA_CESR_BSE_Pos)                 /*!< 0x00000800 */

+#define MDMA_CESR_BSE             MDMA_CESR_BSE_Msk                            /*!< Block Size Error         */

+

+/********************  Bit definition for MDMA_CxCR register  ****************/

+#define MDMA_CCR_EN_Pos           (0U)

+#define MDMA_CCR_EN_Msk           (0x1UL << MDMA_CCR_EN_Pos)                   /*!< 0x00000001 */

+#define MDMA_CCR_EN               MDMA_CCR_EN_Msk                              /*!< Channel enable / flag channel ready when read low */

+#define MDMA_CCR_TEIE_Pos         (1U)

+#define MDMA_CCR_TEIE_Msk         (0x1UL << MDMA_CCR_TEIE_Pos)                 /*!< 0x00000002 */

+#define MDMA_CCR_TEIE             MDMA_CCR_TEIE_Msk                            /*!< Transfer error interrupt enable */

+#define MDMA_CCR_CTCIE_Pos        (2U)

+#define MDMA_CCR_CTCIE_Msk        (0x1UL << MDMA_CCR_CTCIE_Pos)                /*!< 0x00000004 */

+#define MDMA_CCR_CTCIE            MDMA_CCR_CTCIE_Msk                           /*!< Channel Transfer Complete interrupt enable */

+#define MDMA_CCR_BRTIE_Pos        (3U)

+#define MDMA_CCR_BRTIE_Msk        (0x1UL << MDMA_CCR_BRTIE_Pos)                /*!< 0x00000008 */

+#define MDMA_CCR_BRTIE            MDMA_CCR_BRTIE_Msk                           /*!< Block Repeat transfer interrupt enable */

+#define MDMA_CCR_BTIE_Pos         (4U)

+#define MDMA_CCR_BTIE_Msk         (0x1UL << MDMA_CCR_BTIE_Pos)                 /*!< 0x00000010 */

+#define MDMA_CCR_BTIE             MDMA_CCR_BTIE_Msk                            /*!< Block Transfer interrupt enable */

+#define MDMA_CCR_TCIE_Pos         (5U)

+#define MDMA_CCR_TCIE_Msk         (0x1UL << MDMA_CCR_TCIE_Pos)                 /*!< 0x00000020 */

+#define MDMA_CCR_TCIE             MDMA_CCR_TCIE_Msk                            /*!< buffer Transfer Complete interrupt enable */

+#define MDMA_CCR_PL_Pos           (6U)

+#define MDMA_CCR_PL_Msk           (0x3UL << MDMA_CCR_PL_Pos)                   /*!< 0x000000C0 */

+#define MDMA_CCR_PL               MDMA_CCR_PL_Msk                              /*!< Priority level */

+#define MDMA_CCR_PL_0             (0x1UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000040 */

+#define MDMA_CCR_PL_1             (0x2UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000080 */

+#define MDMA_CCR_BEX_Pos          (12U)

+#define MDMA_CCR_BEX_Msk          (0x1UL << MDMA_CCR_BEX_Pos)                  /*!< 0x00001000 */

+#define MDMA_CCR_BEX              MDMA_CCR_BEX_Msk                             /*!< Byte Endianess eXchange */

+#define MDMA_CCR_HEX_Pos          (13U)

+#define MDMA_CCR_HEX_Msk          (0x1UL << MDMA_CCR_HEX_Pos)                  /*!< 0x00002000 */

+#define MDMA_CCR_HEX              MDMA_CCR_HEX_Msk                             /*!< Half word Endianess eXchange */

+#define MDMA_CCR_WEX_Pos          (14U)

+#define MDMA_CCR_WEX_Msk          (0x1UL << MDMA_CCR_WEX_Pos)                  /*!< 0x00004000 */

+#define MDMA_CCR_WEX              MDMA_CCR_WEX_Msk                             /*!< Word Endianess eXchange */

+#define MDMA_CCR_SWRQ_Pos         (16U)

+#define MDMA_CCR_SWRQ_Msk         (0x1UL << MDMA_CCR_SWRQ_Pos)                 /*!< 0x00010000 */

+#define MDMA_CCR_SWRQ             MDMA_CCR_SWRQ_Msk                            /*!< SW ReQuest */

+

+/********************  Bit definition for MDMA_CxTCR register  ****************/

+#define MDMA_CTCR_SINC_Pos        (0U)

+#define MDMA_CTCR_SINC_Msk        (0x3UL << MDMA_CTCR_SINC_Pos)                /*!< 0x00000003 */

+#define MDMA_CTCR_SINC            MDMA_CTCR_SINC_Msk                           /*!< Source increment mode */

+#define MDMA_CTCR_SINC_0          (0x1UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000001 */

+#define MDMA_CTCR_SINC_1          (0x2UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000002 */

+#define MDMA_CTCR_DINC_Pos        (2U)

+#define MDMA_CTCR_DINC_Msk        (0x3UL << MDMA_CTCR_DINC_Pos)                /*!< 0x0000000C */

+#define MDMA_CTCR_DINC            MDMA_CTCR_DINC_Msk                           /*!< Source increment mode */

+#define MDMA_CTCR_DINC_0          (0x1UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000004 */

+#define MDMA_CTCR_DINC_1          (0x2UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000008 */

+#define MDMA_CTCR_SSIZE_Pos       (4U)

+#define MDMA_CTCR_SSIZE_Msk       (0x3UL << MDMA_CTCR_SSIZE_Pos)               /*!< 0x00000030 */

+#define MDMA_CTCR_SSIZE           MDMA_CTCR_SSIZE_Msk                          /*!< Source data size */

+#define MDMA_CTCR_SSIZE_0         (0x1UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000010 */

+#define MDMA_CTCR_SSIZE_1         (0x2UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000020 */

+#define MDMA_CTCR_DSIZE_Pos       (6U)

+#define MDMA_CTCR_DSIZE_Msk       (0x3UL << MDMA_CTCR_DSIZE_Pos)               /*!< 0x000000C0 */

+#define MDMA_CTCR_DSIZE           MDMA_CTCR_DSIZE_Msk                          /*!< Destination data size */

+#define MDMA_CTCR_DSIZE_0         (0x1UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000040 */

+#define MDMA_CTCR_DSIZE_1         (0x2UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000080 */

+#define MDMA_CTCR_SINCOS_Pos      (8U)

+#define MDMA_CTCR_SINCOS_Msk      (0x3UL << MDMA_CTCR_SINCOS_Pos)              /*!< 0x00000300 */

+#define MDMA_CTCR_SINCOS          MDMA_CTCR_SINCOS_Msk                         /*!< Source increment offset size */

+#define MDMA_CTCR_SINCOS_0        (0x1UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000100 */

+#define MDMA_CTCR_SINCOS_1        (0x2UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000200 */

+#define MDMA_CTCR_DINCOS_Pos      (10U)

+#define MDMA_CTCR_DINCOS_Msk      (0x3UL << MDMA_CTCR_DINCOS_Pos)              /*!< 0x00000C00 */

+#define MDMA_CTCR_DINCOS          MDMA_CTCR_DINCOS_Msk                         /*!< Destination increment offset size */

+#define MDMA_CTCR_DINCOS_0        (0x1UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000400 */

+#define MDMA_CTCR_DINCOS_1        (0x2UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000800 */

+#define MDMA_CTCR_SBURST_Pos      (12U)

+#define MDMA_CTCR_SBURST_Msk      (0x7UL << MDMA_CTCR_SBURST_Pos)              /*!< 0x00007000 */

+#define MDMA_CTCR_SBURST          MDMA_CTCR_SBURST_Msk                         /*!< Source burst transfer configuration */

+#define MDMA_CTCR_SBURST_0        (0x1UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00001000 */

+#define MDMA_CTCR_SBURST_1        (0x2UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00002000 */

+#define MDMA_CTCR_SBURST_2        (0x4UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00004000 */

+#define MDMA_CTCR_DBURST_Pos      (15U)

+#define MDMA_CTCR_DBURST_Msk      (0x7UL << MDMA_CTCR_DBURST_Pos)              /*!< 0x00038000 */

+#define MDMA_CTCR_DBURST          MDMA_CTCR_DBURST_Msk                         /*!< Destination burst transfer configuration */

+#define MDMA_CTCR_DBURST_0        (0x1UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00008000 */

+#define MDMA_CTCR_DBURST_1        (0x2UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00010000 */

+#define MDMA_CTCR_DBURST_2        (0x4UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00020000 */

+#define MDMA_CTCR_TLEN_Pos        (18U)

+#define MDMA_CTCR_TLEN_Msk        (0x7FUL << MDMA_CTCR_TLEN_Pos)               /*!< 0x01FC0000 */

+#define MDMA_CTCR_TLEN            MDMA_CTCR_TLEN_Msk                           /*!< buffer Transfer Length (number of bytes - 1) */

+#define MDMA_CTCR_PKE_Pos         (25U)

+#define MDMA_CTCR_PKE_Msk         (0x1UL << MDMA_CTCR_PKE_Pos)                 /*!< 0x02000000 */

+#define MDMA_CTCR_PKE             MDMA_CTCR_PKE_Msk                            /*!< PacK Enable */

+#define MDMA_CTCR_PAM_Pos         (26U)

+#define MDMA_CTCR_PAM_Msk         (0x3UL << MDMA_CTCR_PAM_Pos)                 /*!< 0x0C000000 */

+#define MDMA_CTCR_PAM             MDMA_CTCR_PAM_Msk                            /*!< Padding/Alignement Mode */

+#define MDMA_CTCR_PAM_0           (0x1UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x4000000 */

+#define MDMA_CTCR_PAM_1           (0x2UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x8000000 */

+#define MDMA_CTCR_TRGM_Pos        (28U)

+#define MDMA_CTCR_TRGM_Msk        (0x3UL << MDMA_CTCR_TRGM_Pos)                /*!< 0x30000000 */

+#define MDMA_CTCR_TRGM            MDMA_CTCR_TRGM_Msk                           /*!< Trigger Mode */

+#define MDMA_CTCR_TRGM_0          (0x1UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x10000000 */

+#define MDMA_CTCR_TRGM_1          (0x2UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x20000000 */

+#define MDMA_CTCR_SWRM_Pos        (30U)

+#define MDMA_CTCR_SWRM_Msk        (0x1UL << MDMA_CTCR_SWRM_Pos)                /*!< 0x40000000 */

+#define MDMA_CTCR_SWRM            MDMA_CTCR_SWRM_Msk                           /*!< SW Request Mode */

+#define MDMA_CTCR_BWM_Pos         (31U)

+#define MDMA_CTCR_BWM_Msk         (0x1UL << MDMA_CTCR_BWM_Pos)                 /*!< 0x80000000 */

+#define MDMA_CTCR_BWM             MDMA_CTCR_BWM_Msk                            /*!< Bufferable Write Mode */

+

+/********************  Bit definition for MDMA_CxBNDTR register  ****************/

+#define MDMA_CBNDTR_BNDT_Pos      (0U)

+#define MDMA_CBNDTR_BNDT_Msk      (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos)          /*!< 0x0001FFFF */

+#define MDMA_CBNDTR_BNDT          MDMA_CBNDTR_BNDT_Msk                         /*!< Block Number of data bytes to transfer */

+#define MDMA_CBNDTR_BRSUM_Pos     (18U)

+#define MDMA_CBNDTR_BRSUM_Msk     (0x1UL << MDMA_CBNDTR_BRSUM_Pos)             /*!< 0x00040000 */

+#define MDMA_CBNDTR_BRSUM         MDMA_CBNDTR_BRSUM_Msk                        /*!< Block Repeat Source address Update Mode */

+#define MDMA_CBNDTR_BRDUM_Pos     (19U)

+#define MDMA_CBNDTR_BRDUM_Msk     (0x1UL << MDMA_CBNDTR_BRDUM_Pos)             /*!< 0x00080000 */

+#define MDMA_CBNDTR_BRDUM         MDMA_CBNDTR_BRDUM_Msk                        /*!< Block Repeat Destination address Update Mode */

+#define MDMA_CBNDTR_BRC_Pos       (20U)

+#define MDMA_CBNDTR_BRC_Msk       (0xFFFUL << MDMA_CBNDTR_BRC_Pos)             /*!< 0xFFF00000 */

+#define MDMA_CBNDTR_BRC           MDMA_CBNDTR_BRC_Msk                          /*!< Block Repeat Count */

+

+/********************  Bit definition for MDMA_CxSAR register  ****************/

+#define MDMA_CSAR_SAR_Pos         (0U)

+#define MDMA_CSAR_SAR_Msk         (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CSAR_SAR             MDMA_CSAR_SAR_Msk                            /*!< Source address */

+

+/********************  Bit definition for MDMA_CxDAR register  ****************/

+#define MDMA_CDAR_DAR_Pos         (0U)

+#define MDMA_CDAR_DAR_Msk         (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CDAR_DAR             MDMA_CDAR_DAR_Msk                            /*!< Destination address */

+

+/********************  Bit definition for MDMA_CxBRUR  ************************/

+#define MDMA_CBRUR_SUV_Pos        (0U)

+#define MDMA_CBRUR_SUV_Msk        (0xFFFFUL << MDMA_CBRUR_SUV_Pos)             /*!< 0x0000FFFF */

+#define MDMA_CBRUR_SUV            MDMA_CBRUR_SUV_Msk                           /*!< Source address Update Value */

+#define MDMA_CBRUR_DUV_Pos        (16U)

+#define MDMA_CBRUR_DUV_Msk        (0xFFFFUL << MDMA_CBRUR_DUV_Pos)             /*!< 0xFFFF0000 */

+#define MDMA_CBRUR_DUV            MDMA_CBRUR_DUV_Msk                           /*!< Destination address Update Value */

+

+/********************  Bit definition for MDMA_CxLAR  *************************/

+#define MDMA_CLAR_LAR_Pos         (0U)

+#define MDMA_CLAR_LAR_Msk         (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CLAR_LAR             MDMA_CLAR_LAR_Msk                            /*!< Link Address Register */

+

+/********************  Bit definition for MDMA_CxTBR)  ************************/

+#define MDMA_CTBR_TSEL_Pos        (0U)

+#define MDMA_CTBR_TSEL_Msk        (0xFFUL << MDMA_CTBR_TSEL_Pos)               /*!< 0x000000FF */

+#define MDMA_CTBR_TSEL            MDMA_CTBR_TSEL_Msk                           /*!< Trigger SELection */

+#define MDMA_CTBR_SBUS_Pos        (16U)

+#define MDMA_CTBR_SBUS_Msk        (0x1UL << MDMA_CTBR_SBUS_Pos)                /*!< 0x00010000 */

+#define MDMA_CTBR_SBUS            MDMA_CTBR_SBUS_Msk                           /*!< Source BUS select */

+#define MDMA_CTBR_DBUS_Pos        (17U)

+#define MDMA_CTBR_DBUS_Msk        (0x1UL << MDMA_CTBR_DBUS_Pos)                /*!< 0x00020000 */

+#define MDMA_CTBR_DBUS            MDMA_CTBR_DBUS_Msk                           /*!< Destination BUS select */

+

+/********************  Bit definition for MDMA_CxMAR)  ************************/

+#define MDMA_CMAR_MAR_Pos         (0U)

+#define MDMA_CMAR_MAR_Msk         (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CMAR_MAR             MDMA_CMAR_MAR_Msk                            /*!< Mask address */

+

+/********************  Bit definition for MDMA_CxMDR)  ************************/

+#define MDMA_CMDR_MDR_Pos         (0U)

+#define MDMA_CMDR_MDR_Msk         (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CMDR_MDR             MDMA_CMDR_MDR_Msk                            /*!< Mask Data */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Operational Amplifier (OPAMP)                      */

+/*                                                                            */

+/******************************************************************************/

+/*********************  Bit definition for OPAMPx_CSR register  ***************/

+#define OPAMP_CSR_OPAMPxEN_Pos           (0U)

+#define OPAMP_CSR_OPAMPxEN_Msk           (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)     /*!< 0x00000001 */

+#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */

+#define OPAMP_CSR_FORCEVP_Pos            (1U)

+#define OPAMP_CSR_FORCEVP_Msk            (0x1UL << OPAMP_CSR_FORCEVP_Pos)      /*!< 0x00000002 */

+#define OPAMP_CSR_FORCEVP                OPAMP_CSR_FORCEVP_Msk                 /*!< Force internal reference on VP */

+

+#define OPAMP_CSR_VPSEL_Pos              (2U)

+#define OPAMP_CSR_VPSEL_Msk              (0x3UL << OPAMP_CSR_VPSEL_Pos)        /*!< 0x0000000C */

+#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */

+#define OPAMP_CSR_VPSEL_0                (0x1UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000004 */

+#define OPAMP_CSR_VPSEL_1                (0x2UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000008 */

+

+#define OPAMP_CSR_VMSEL_Pos              (5U)

+#define OPAMP_CSR_VMSEL_Msk              (0x3UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000060 */

+#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */

+#define OPAMP_CSR_VMSEL_0                (0x1UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000020 */

+#define OPAMP_CSR_VMSEL_1                (0x2UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000040 */

+

+#define OPAMP_CSR_OPAHSM_Pos             (8U)

+#define OPAMP_CSR_OPAHSM_Msk             (0x1UL << OPAMP_CSR_OPAHSM_Pos)       /*!< 0x00000100 */

+#define OPAMP_CSR_OPAHSM                 OPAMP_CSR_OPAHSM_Msk                  /*!< Operational amplifier high speed mode */

+#define OPAMP_CSR_CALON_Pos              (11U)

+#define OPAMP_CSR_CALON_Msk              (0x1UL << OPAMP_CSR_CALON_Pos)        /*!< 0x00000800 */

+#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */

+

+#define OPAMP_CSR_CALSEL_Pos             (12U)

+#define OPAMP_CSR_CALSEL_Msk             (0x3UL << OPAMP_CSR_CALSEL_Pos)       /*!< 0x00003000 */

+#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */

+#define OPAMP_CSR_CALSEL_0               (0x1UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00001000 */

+#define OPAMP_CSR_CALSEL_1               (0x2UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */

+

+#define OPAMP_CSR_PGGAIN_Pos             (14U)

+#define OPAMP_CSR_PGGAIN_Msk             (0xFUL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x0003C000 */

+#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */

+#define OPAMP_CSR_PGGAIN_0               (0x1UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00004000 */

+#define OPAMP_CSR_PGGAIN_1               (0x2UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00008000 */

+#define OPAMP_CSR_PGGAIN_2               (0x4UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00010000 */

+#define OPAMP_CSR_PGGAIN_3               (0x8UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00020000 */

+

+#define OPAMP_CSR_USERTRIM_Pos           (18U)

+#define OPAMP_CSR_USERTRIM_Msk           (0x1UL << OPAMP_CSR_USERTRIM_Pos)     /*!< 0x00040000 */

+#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */

+#define OPAMP_CSR_TSTREF_Pos             (29U)

+#define OPAMP_CSR_TSTREF_Msk             (0x1UL << OPAMP_CSR_TSTREF_Pos)       /*!< 0x20000000 */

+#define OPAMP_CSR_TSTREF                 OPAMP_CSR_TSTREF_Msk                  /*!< OpAmp calibration reference voltage output control */

+#define OPAMP_CSR_CALOUT_Pos             (30U)

+#define OPAMP_CSR_CALOUT_Msk             (0x1UL << OPAMP_CSR_CALOUT_Pos)       /*!< 0x40000000 */

+#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier calibration output */

+

+/*********************  Bit definition for OPAMP1_CSR register  ***************/

+#define OPAMP1_CSR_OPAEN_Pos              (0U)

+#define OPAMP1_CSR_OPAEN_Msk              (0x1UL << OPAMP1_CSR_OPAEN_Pos)      /*!< 0x00000001 */

+#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */

+#define OPAMP1_CSR_FORCEVP_Pos            (1U)

+#define OPAMP1_CSR_FORCEVP_Msk            (0x1UL << OPAMP1_CSR_FORCEVP_Pos)    /*!< 0x00000002 */

+#define OPAMP1_CSR_FORCEVP                OPAMP1_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */

+

+#define OPAMP1_CSR_VPSEL_Pos              (2U)

+#define OPAMP1_CSR_VPSEL_Msk              (0x3UL << OPAMP1_CSR_VPSEL_Pos)      /*!< 0x0000000C */

+#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */

+#define OPAMP1_CSR_VPSEL_0                (0x1UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000004 */

+#define OPAMP1_CSR_VPSEL_1                (0x2UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000008 */

+

+#define OPAMP1_CSR_VMSEL_Pos              (5U)

+#define OPAMP1_CSR_VMSEL_Msk              (0x3UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000060 */

+#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */

+#define OPAMP1_CSR_VMSEL_0                (0x1UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000020 */

+#define OPAMP1_CSR_VMSEL_1                (0x2UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000040 */

+

+#define OPAMP1_CSR_OPAHSM_Pos             (8U)

+#define OPAMP1_CSR_OPAHSM_Msk             (0x1UL << OPAMP1_CSR_OPAHSM_Pos)     /*!< 0x00000100 */

+#define OPAMP1_CSR_OPAHSM                 OPAMP1_CSR_OPAHSM_Msk                /*!< Operational amplifier1 high speed mode */

+#define OPAMP1_CSR_CALON_Pos              (11U)

+#define OPAMP1_CSR_CALON_Msk              (0x1UL << OPAMP1_CSR_CALON_Pos)      /*!< 0x00000800 */

+#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */

+

+#define OPAMP1_CSR_CALSEL_Pos             (12U)

+#define OPAMP1_CSR_CALSEL_Msk             (0x3UL << OPAMP1_CSR_CALSEL_Pos)     /*!< 0x00003000 */

+#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */

+#define OPAMP1_CSR_CALSEL_0               (0x1UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00001000 */

+#define OPAMP1_CSR_CALSEL_1               (0x2UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */

+

+#define OPAMP1_CSR_PGGAIN_Pos             (14U)

+#define OPAMP1_CSR_PGGAIN_Msk             (0xFUL << OPAMP1_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */

+#define OPAMP1_CSR_PGGAIN                 OPAMP1_CSR_PGGAIN_Msk                /*!< Operational amplifier1 Programmable amplifier gain value */

+#define OPAMP1_CSR_PGGAIN_0               (0x1UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00004000 */

+#define OPAMP1_CSR_PGGAIN_1               (0x2UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00008000 */

+#define OPAMP1_CSR_PGGAIN_2               (0x4UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00010000 */

+#define OPAMP1_CSR_PGGAIN_3               (0x8UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00020000 */

+

+#define OPAMP1_CSR_USERTRIM_Pos           (18U)

+#define OPAMP1_CSR_USERTRIM_Msk           (0x1UL << OPAMP1_CSR_USERTRIM_Pos)   /*!< 0x00040000 */

+#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */

+#define OPAMP1_CSR_TSTREF_Pos             (29U)

+#define OPAMP1_CSR_TSTREF_Msk             (0x1UL << OPAMP1_CSR_TSTREF_Pos)     /*!< 0x20000000 */

+#define OPAMP1_CSR_TSTREF                 OPAMP1_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */

+#define OPAMP1_CSR_CALOUT_Pos             (30U)

+#define OPAMP1_CSR_CALOUT_Msk             (0x1UL << OPAMP1_CSR_CALOUT_Pos)     /*!< 0x40000000 */

+#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */

+

+/*********************  Bit definition for OPAMP2_CSR register  ***************/

+#define OPAMP2_CSR_OPAEN_Pos              (0U)

+#define OPAMP2_CSR_OPAEN_Msk              (0x1UL << OPAMP2_CSR_OPAEN_Pos)      /*!< 0x00000001 */

+#define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */

+#define OPAMP2_CSR_FORCEVP_Pos            (1U)

+#define OPAMP2_CSR_FORCEVP_Msk            (0x1UL << OPAMP2_CSR_FORCEVP_Pos)    /*!< 0x00000002 */

+#define OPAMP2_CSR_FORCEVP                OPAMP2_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */

+

+#define OPAMP2_CSR_VPSEL_Pos              (2U)

+#define OPAMP2_CSR_VPSEL_Msk              (0x3UL << OPAMP2_CSR_VPSEL_Pos)      /*!< 0x0000000C */

+#define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */

+#define OPAMP2_CSR_VPSEL_0                (0x1UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000004 */

+#define OPAMP2_CSR_VPSEL_1                (0x2UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000008 */

+

+#define OPAMP2_CSR_VMSEL_Pos              (5U)

+#define OPAMP2_CSR_VMSEL_Msk              (0x3UL << OPAMP2_CSR_VMSEL_Pos)      /*!< 0x00000060 */

+#define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */

+#define OPAMP2_CSR_VMSEL_0                (0x1UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000020 */

+#define OPAMP2_CSR_VMSEL_1                (0x2UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000040 */

+

+#define OPAMP2_CSR_OPAHSM_Pos             (8U)

+#define OPAMP2_CSR_OPAHSM_Msk             (0x1UL << OPAMP2_CSR_OPAHSM_Pos)     /*!< 0x00000100 */

+#define OPAMP2_CSR_OPAHSM                 OPAMP2_CSR_OPAHSM_Msk                /*!< Operational amplifier2 high speed mode */

+#define OPAMP2_CSR_CALON_Pos              (11U)

+#define OPAMP2_CSR_CALON_Msk              (0x1UL << OPAMP2_CSR_CALON_Pos)      /*!< 0x00000800 */

+#define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */

+

+#define OPAMP2_CSR_CALSEL_Pos             (12U)

+#define OPAMP2_CSR_CALSEL_Msk             (0x3UL << OPAMP2_CSR_CALSEL_Pos)     /*!< 0x00003000 */

+#define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */

+#define OPAMP2_CSR_CALSEL_0               (0x1UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00001000 */

+#define OPAMP2_CSR_CALSEL_1               (0x2UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */

+

+#define OPAMP2_CSR_PGGAIN_Pos             (14U)

+#define OPAMP2_CSR_PGGAIN_Msk             (0xFUL << OPAMP2_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */

+#define OPAMP2_CSR_PGGAIN                 OPAMP2_CSR_PGGAIN_Msk                /*!< Operational amplifier2 Programmable amplifier gain value */

+#define OPAMP2_CSR_PGGAIN_0               (0x1UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00004000 */

+#define OPAMP2_CSR_PGGAIN_1               (0x2UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00008000 */

+#define OPAMP2_CSR_PGGAIN_2               (0x4UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00010000 */

+#define OPAMP2_CSR_PGGAIN_3               (0x8UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00020000 */

+

+#define OPAMP2_CSR_USERTRIM_Pos           (18U)

+#define OPAMP2_CSR_USERTRIM_Msk           (0x1UL << OPAMP2_CSR_USERTRIM_Pos)   /*!< 0x00040000 */

+#define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */

+#define OPAMP2_CSR_TSTREF_Pos             (29U)

+#define OPAMP2_CSR_TSTREF_Msk             (0x1UL << OPAMP2_CSR_TSTREF_Pos)     /*!< 0x20000000 */

+#define OPAMP2_CSR_TSTREF                 OPAMP2_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */

+#define OPAMP2_CSR_CALOUT_Pos             (30U)

+#define OPAMP2_CSR_CALOUT_Msk             (0x1UL << OPAMP2_CSR_CALOUT_Pos)     /*!< 0x40000000 */

+#define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */

+

+/*******************  Bit definition for OPAMP_OTR register  ******************/

+#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */

+#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP1_OTR register  ******************/

+#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */

+#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP2_OTR register  ******************/

+#define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */

+#define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP_HSOTR register  ****************/

+#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP_HSOTR_TRIMHSOFFSETN        OPAMP_HSOTR_TRIMHSOFFSETN_Msk         /*!< Trim for NMOS differential pairs */

+#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP_HSOTR_TRIMHSOFFSETP        OPAMP_HSOTR_TRIMHSOFFSETP_Msk         /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP1_HSOTR register  ****************/

+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP1_HSOTR_TRIMHSOFFSETN        OPAMP1_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */

+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP1_HSOTR_TRIMHSOFFSETP        OPAMP1_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP2_HSOTR register  ****************/

+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP2_HSOTR_TRIMHSOFFSETN        OPAMP2_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */

+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP2_HSOTR_TRIMHSOFFSETP        OPAMP2_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             Power Control                                  */

+/*                                                                            */

+/******************************************************************************/

+/*************************  NUMBER OF POWER DOMAINS  **************************/

+#define POWER_DOMAINS_NUMBER           3U                                      /*!< 3 Domains */

+

+/********************  Bit definition for PWR_CR1 register  *******************/

+#define PWR_CR1_ALS_Pos                (17U)

+#define PWR_CR1_ALS_Msk                (0x3UL << PWR_CR1_ALS_Pos)              /*!< 0x00060000 */

+#define PWR_CR1_ALS                    PWR_CR1_ALS_Msk                         /*!< Analog Voltage Detector level selection */

+#define PWR_CR1_ALS_0                  (0x1UL << PWR_CR1_ALS_Pos)              /*!< 0x00020000 */

+#define PWR_CR1_ALS_1                  (0x2UL << PWR_CR1_ALS_Pos)              /*!< 0x00040000 */

+#define PWR_CR1_AVDEN_Pos              (16U)

+#define PWR_CR1_AVDEN_Msk              (0x1UL << PWR_CR1_AVDEN_Pos)            /*!< 0x00010000 */

+#define PWR_CR1_AVDEN                  PWR_CR1_AVDEN_Msk                       /*!< Analog Voltage Detector Enable */

+#define PWR_CR1_SVOS_Pos               (14U)

+#define PWR_CR1_SVOS_Msk               (0x3UL << PWR_CR1_SVOS_Pos)             /*!< 0x0000C000 */

+#define PWR_CR1_SVOS                   PWR_CR1_SVOS_Msk                        /*!< System STOP mode Voltage Scaling selection */

+#define PWR_CR1_SVOS_0                 (0x1UL << PWR_CR1_SVOS_Pos)             /*!< 0x00004000 */

+#define PWR_CR1_SVOS_1                 (0x2UL << PWR_CR1_SVOS_Pos)             /*!< 0x00008000 */

+#define PWR_CR1_FLPS_Pos               (9U)

+#define PWR_CR1_FLPS_Msk               (0x1UL << PWR_CR1_FLPS_Pos)             /*!< 0x00000200 */

+#define PWR_CR1_FLPS                   PWR_CR1_FLPS_Msk                        /*!< Flash low power mode in DSTOP */

+#define PWR_CR1_DBP_Pos                (8U)

+#define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */

+#define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable Back-up domain Protection */

+#define PWR_CR1_PLS_Pos                (5U)

+#define PWR_CR1_PLS_Msk                (0x7UL << PWR_CR1_PLS_Pos)              /*!< 0x000000E0 */

+#define PWR_CR1_PLS                    PWR_CR1_PLS_Msk                         /*!< Programmable Voltage Detector level selection */

+#define PWR_CR1_PLS_0                  (0x1UL << PWR_CR1_PLS_Pos)              /*!< 0x00000020 */

+#define PWR_CR1_PLS_1                  (0x2UL << PWR_CR1_PLS_Pos)              /*!< 0x00000040 */

+#define PWR_CR1_PLS_2                  (0x4UL << PWR_CR1_PLS_Pos)              /*!< 0x00000080 */

+#define PWR_CR1_PVDEN_Pos              (4U)

+#define PWR_CR1_PVDEN_Msk              (0x1UL << PWR_CR1_PVDEN_Pos)            /*!< 0x00000010 */

+#define PWR_CR1_PVDEN                  PWR_CR1_PVDEN_Msk                       /*!< Programmable Voltage detector enable */

+#define PWR_CR1_LPDS_Pos               (0U)

+#define PWR_CR1_LPDS_Msk               (0x1UL << PWR_CR1_LPDS_Pos)             /*!< 0x00000001 */

+#define PWR_CR1_LPDS                   PWR_CR1_LPDS_Msk                        /*!< Low Power Deepsleep with SVOS3 */

+

+/*!< PVD level configuration */

+#define PWR_CR1_PLS_LEV0               (0UL)                                   /*!< PVD level 0 */

+#define PWR_CR1_PLS_LEV1_Pos           (5U)

+#define PWR_CR1_PLS_LEV1_Msk           (0x1UL << PWR_CR1_PLS_LEV1_Pos)         /*!< 0x00000020 */

+#define PWR_CR1_PLS_LEV1               PWR_CR1_PLS_LEV1_Msk                    /*!< PVD level 1 */

+#define PWR_CR1_PLS_LEV2_Pos           (6U)

+#define PWR_CR1_PLS_LEV2_Msk           (0x1UL << PWR_CR1_PLS_LEV2_Pos)         /*!< 0x00000040 */

+#define PWR_CR1_PLS_LEV2               PWR_CR1_PLS_LEV2_Msk                    /*!< PVD level 2 */

+#define PWR_CR1_PLS_LEV3_Pos           (5U)

+#define PWR_CR1_PLS_LEV3_Msk           (0x3UL << PWR_CR1_PLS_LEV3_Pos)         /*!< 0x00000060 */

+#define PWR_CR1_PLS_LEV3               PWR_CR1_PLS_LEV3_Msk                    /*!< PVD level 3 */

+#define PWR_CR1_PLS_LEV4_Pos           (7U)

+#define PWR_CR1_PLS_LEV4_Msk           (0x1UL << PWR_CR1_PLS_LEV4_Pos)         /*!< 0x00000080 */

+#define PWR_CR1_PLS_LEV4               PWR_CR1_PLS_LEV4_Msk                    /*!< PVD level 4 */

+#define PWR_CR1_PLS_LEV5_Pos           (5U)

+#define PWR_CR1_PLS_LEV5_Msk           (0x5UL << PWR_CR1_PLS_LEV5_Pos)         /*!< 0x000000A0 */

+#define PWR_CR1_PLS_LEV5               PWR_CR1_PLS_LEV5_Msk                    /*!< PVD level 5 */

+#define PWR_CR1_PLS_LEV6_Pos           (6U)

+#define PWR_CR1_PLS_LEV6_Msk           (0x3UL << PWR_CR1_PLS_LEV6_Pos)         /*!< 0x000000C0 */

+#define PWR_CR1_PLS_LEV6               PWR_CR1_PLS_LEV6_Msk                    /*!< PVD level 6 */

+#define PWR_CR1_PLS_LEV7_Pos           (5U)

+#define PWR_CR1_PLS_LEV7_Msk           (0x7UL << PWR_CR1_PLS_LEV7_Pos)         /*!< 0x000000E0 */

+#define PWR_CR1_PLS_LEV7               PWR_CR1_PLS_LEV7_Msk                    /*!< PVD level 7 */

+

+/*!< AVD level configuration */

+#define PWR_CR1_ALS_LEV0               (0UL)                                   /*!< AVD level 0 */

+#define PWR_CR1_ALS_LEV1_Pos           (17U)

+#define PWR_CR1_ALS_LEV1_Msk           (0x1UL << PWR_CR1_ALS_LEV1_Pos)         /*!< 0x00020000 */

+#define PWR_CR1_ALS_LEV1               PWR_CR1_ALS_LEV1_Msk                    /*!< AVD level 1 */

+#define PWR_CR1_ALS_LEV2_Pos           (18U)

+#define PWR_CR1_ALS_LEV2_Msk           (0x1UL << PWR_CR1_ALS_LEV2_Pos)         /*!< 0x00040000 */

+#define PWR_CR1_ALS_LEV2               PWR_CR1_ALS_LEV2_Msk                    /*!< AVD level 2 */

+#define PWR_CR1_ALS_LEV3_Pos           (17U)

+#define PWR_CR1_ALS_LEV3_Msk           (0x3UL << PWR_CR1_ALS_LEV3_Pos)         /*!< 0x00060000 */

+#define PWR_CR1_ALS_LEV3               PWR_CR1_ALS_LEV3_Msk                    /*!< AVD level 3 */

+

+/********************  Bit definition for PWR_CSR1 register  ******************/

+#define PWR_CSR1_AVDO_Pos              (16U)

+#define PWR_CSR1_AVDO_Msk              (0x1UL << PWR_CSR1_AVDO_Pos)            /*!< 0x00010000 */

+#define PWR_CSR1_AVDO                  PWR_CSR1_AVDO_Msk                       /*!< Analog Voltage Detect Output */

+#define PWR_CSR1_ACTVOS_Pos            (14U)

+#define PWR_CSR1_ACTVOS_Msk            (0x3UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x0000C000 */

+#define PWR_CSR1_ACTVOS                PWR_CSR1_ACTVOS_Msk                     /*!< Current actual used VOS for VDD11 Voltage Scaling */

+#define PWR_CSR1_ACTVOS_0              (0x1UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00004000 */

+#define PWR_CSR1_ACTVOS_1              (0x2UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00008000 */

+#define PWR_CSR1_ACTVOSRDY_Pos         (13U)

+#define PWR_CSR1_ACTVOSRDY_Msk         (0x1UL << PWR_CSR1_ACTVOSRDY_Pos)       /*!< 0x00002000 */

+#define PWR_CSR1_ACTVOSRDY             PWR_CSR1_ACTVOSRDY_Msk                  /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling  */

+#define PWR_CSR1_PVDO_Pos              (4U)

+#define PWR_CSR1_PVDO_Msk              (0x1UL << PWR_CSR1_PVDO_Pos)            /*!< 0x00000010 */

+#define PWR_CSR1_PVDO                  PWR_CSR1_PVDO_Msk                       /*!< Programmable Voltage Detect Output */

+

+/********************  Bit definition for PWR_CR2 register  *******************/

+#define PWR_CR2_TEMPH_Pos              (23U)

+#define PWR_CR2_TEMPH_Msk              (0x1UL << PWR_CR2_TEMPH_Pos)            /*!< 0x00800000 */

+#define PWR_CR2_TEMPH                  PWR_CR2_TEMPH_Msk                       /*!< Monitored temperature level above high threshold */

+#define PWR_CR2_TEMPL_Pos              (22U)

+#define PWR_CR2_TEMPL_Msk              (0x1UL << PWR_CR2_TEMPL_Pos)            /*!< 0x00400000 */

+#define PWR_CR2_TEMPL                  PWR_CR2_TEMPL_Msk                       /*!< Monitored temperature level above low threshold */

+#define PWR_CR2_VBATH_Pos              (21U)

+#define PWR_CR2_VBATH_Msk              (0x1UL << PWR_CR2_VBATH_Pos)            /*!< 0x00200000 */

+#define PWR_CR2_VBATH                  PWR_CR2_VBATH_Msk                       /*!< Monitored VBAT level above high threshold */

+#define PWR_CR2_VBATL_Pos              (20U)

+#define PWR_CR2_VBATL_Msk              (0x1UL << PWR_CR2_VBATL_Pos)            /*!< 0x00100000 */

+#define PWR_CR2_VBATL                  PWR_CR2_VBATL_Msk                       /*!< Monitored VBAT level above low threshold */

+#define PWR_CR2_BRRDY_Pos              (16U)

+#define PWR_CR2_BRRDY_Msk              (0x1UL << PWR_CR2_BRRDY_Pos)            /*!< 0x00010000 */

+#define PWR_CR2_BRRDY                  PWR_CR2_BRRDY_Msk                       /*!< Backup regulator ready */

+#define PWR_CR2_MONEN_Pos              (4U)

+#define PWR_CR2_MONEN_Msk              (0x1UL << PWR_CR2_MONEN_Pos)            /*!< 0x00000010 */

+#define PWR_CR2_MONEN                  PWR_CR2_MONEN_Msk                       /*!< VBAT and temperature monitoring enable */

+#define PWR_CR2_BREN_Pos               (0U)

+#define PWR_CR2_BREN_Msk               (0x1UL << PWR_CR2_BREN_Pos)             /*!< 0x00000001 */

+#define PWR_CR2_BREN                   PWR_CR2_BREN_Msk                        /*!< Backup regulator enable */

+

+/********************  Bit definition for PWR_CR3 register  *******************/

+#define PWR_CR3_USB33RDY_Pos           (26U)

+#define PWR_CR3_USB33RDY_Msk           (0x1UL << PWR_CR3_USB33RDY_Pos)         /*!< 0x04000000 */

+#define PWR_CR3_USB33RDY               PWR_CR3_USB33RDY_Msk                    /*!< USB supply ready */

+#define PWR_CR3_USBREGEN_Pos           (25U)

+#define PWR_CR3_USBREGEN_Msk           (0x1UL << PWR_CR3_USBREGEN_Pos)         /*!< 0x02000000 */

+#define PWR_CR3_USBREGEN               PWR_CR3_USBREGEN_Msk                    /*!< USB regulator enable */

+#define PWR_CR3_USB33DEN_Pos           (24U)

+#define PWR_CR3_USB33DEN_Msk           (0x1UL << PWR_CR3_USB33DEN_Pos)         /*!< 0x01000000 */

+#define PWR_CR3_USB33DEN               PWR_CR3_USB33DEN_Msk                    /*!< VDD33_USB voltage level detector enable */

+#define PWR_CR3_SMPSEXTRDY_Pos         (16U)

+#define PWR_CR3_SMPSEXTRDY_Msk         (0x1UL << PWR_CR3_SMPSEXTRDY_Pos)       /*!< 0x00010000 */

+#define PWR_CR3_SMPSEXTRDY             PWR_CR3_SMPSEXTRDY_Msk                  /*!< SMPS External supply ready */

+#define PWR_CR3_VBRS_Pos               (9U)

+#define PWR_CR3_VBRS_Msk               (0x1UL << PWR_CR3_VBRS_Pos)             /*!< 0x00000200 */

+#define PWR_CR3_VBRS                   PWR_CR3_VBRS_Msk                        /*!< VBAT charging resistor selection */

+#define PWR_CR3_VBE_Pos                (8U)

+#define PWR_CR3_VBE_Msk                (0x1UL << PWR_CR3_VBE_Pos)              /*!< 0x00000100 */

+#define PWR_CR3_VBE                    PWR_CR3_VBE_Msk                         /*!< VBAT charging enable */

+#define PWR_CR3_SMPSLEVEL_Pos          (4U)

+#define PWR_CR3_SMPSLEVEL_Msk          (0x3UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000030 */

+#define PWR_CR3_SMPSLEVEL              PWR_CR3_SMPSLEVEL_Msk                   /*!< SMPS output Voltage */

+#define PWR_CR3_SMPSLEVEL_0            (0x1UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000010 */

+#define PWR_CR3_SMPSLEVEL_1            (0x2UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000020 */

+#define PWR_CR3_SMPSEXTHP_Pos          (3U)

+#define PWR_CR3_SMPSEXTHP_Msk          (0x1UL << PWR_CR3_SMPSEXTHP_Pos)        /*!< 0x00000008 */

+#define PWR_CR3_SMPSEXTHP              PWR_CR3_SMPSEXTHP_Msk                   /*!< SMPS forced ON and in High Power MR mode */

+#define PWR_CR3_SMPSEN_Pos             (2U)

+#define PWR_CR3_SMPSEN_Msk             (0x1UL << PWR_CR3_SMPSEN_Pos)           /*!< 0x00000004 */

+#define PWR_CR3_SMPSEN                 PWR_CR3_SMPSEN_Msk                      /*!< SMPS Enable */

+#define PWR_CR3_LDOEN_Pos              (1U)

+#define PWR_CR3_LDOEN_Msk              (0x1UL << PWR_CR3_LDOEN_Pos)            /*!< 0x00000002 */

+#define PWR_CR3_LDOEN                  PWR_CR3_LDOEN_Msk                       /*!< Low Drop Output regulator enable */

+#define PWR_CR3_BYPASS_Pos             (0U)

+#define PWR_CR3_BYPASS_Msk             (0x1UL << PWR_CR3_BYPASS_Pos)           /*!< 0x00000001 */

+#define PWR_CR3_BYPASS                 PWR_CR3_BYPASS_Msk                      /*!< Power Management Unit bypass */

+

+/********************  Bit definition for PWR_CPUCR register  *****************/

+#define PWR_CPUCR_RUN_D3_Pos           (11U)

+#define PWR_CPUCR_RUN_D3_Msk           (0x1UL << PWR_CPUCR_RUN_D3_Pos)         /*!< 0x00000800 */

+#define PWR_CPUCR_RUN_D3               PWR_CPUCR_RUN_D3_Msk                    /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */

+#define PWR_CPUCR_HOLD2_Pos            (10U)

+#define PWR_CPUCR_HOLD2_Msk            (0x1UL << PWR_CPUCR_HOLD2_Pos)          /*!< 0x00000400 */

+#define PWR_CPUCR_HOLD2                PWR_CPUCR_HOLD2_Msk                     /*!< Hold the CPU2 and allocated peripherals when exiting STOP mode */

+#define PWR_CPUCR_CSSF_Pos             (9U)

+#define PWR_CPUCR_CSSF_Msk             (0x1UL << PWR_CPUCR_CSSF_Pos)           /*!< 0x00000200 */

+#define PWR_CPUCR_CSSF                 PWR_CPUCR_CSSF_Msk                      /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */

+#define PWR_CPUCR_SBF_D2_Pos           (8U)

+#define PWR_CPUCR_SBF_D2_Msk           (0x1UL << PWR_CPUCR_SBF_D2_Pos)         /*!< 0x00000100 */

+#define PWR_CPUCR_SBF_D2               PWR_CPUCR_SBF_D2_Msk                    /*!< D2 domain DSTANDBY Flag */

+#define PWR_CPUCR_SBF_D1_Pos           (7U)

+#define PWR_CPUCR_SBF_D1_Msk           (0x1UL << PWR_CPUCR_SBF_D1_Pos)         /*!< 0x00000080 */

+#define PWR_CPUCR_SBF_D1               PWR_CPUCR_SBF_D1_Msk                    /*!< D1 domain DSTANDBY Flag */

+#define PWR_CPUCR_SBF_Pos              (6U)

+#define PWR_CPUCR_SBF_Msk              (0x1UL << PWR_CPUCR_SBF_Pos)            /*!< 0x00000040 */

+#define PWR_CPUCR_SBF                  PWR_CPUCR_SBF_Msk                       /*!< System STANDBY Flag */

+#define PWR_CPUCR_STOPF_Pos            (5U)

+#define PWR_CPUCR_STOPF_Msk            (0x1UL << PWR_CPUCR_STOPF_Pos)          /*!< 0x00000020 */

+#define PWR_CPUCR_STOPF                PWR_CPUCR_STOPF_Msk                     /*!< STOP Flag */

+#define PWR_CPUCR_HOLD2F_Pos           (4U)

+#define PWR_CPUCR_HOLD2F_Msk           (0x1UL << PWR_CPUCR_HOLD2F_Pos)         /*!< 0x00000010 */

+#define PWR_CPUCR_HOLD2F               PWR_CPUCR_HOLD2F_Msk                    /*!< CPU2 in hold wakeup flag */

+#define PWR_CPUCR_PDDS_D3_Pos          (2U)

+#define PWR_CPUCR_PDDS_D3_Msk          (0x1UL << PWR_CPUCR_PDDS_D3_Pos)        /*!< 0x00000004 */

+#define PWR_CPUCR_PDDS_D3              PWR_CPUCR_PDDS_D3_Msk                   /*!< System D3 domain Power Down Deepsleep */

+#define PWR_CPUCR_PDDS_D2_Pos          (1U)

+#define PWR_CPUCR_PDDS_D2_Msk          (0x1UL << PWR_CPUCR_PDDS_D2_Pos)        /*!< 0x00000002 */

+#define PWR_CPUCR_PDDS_D2              PWR_CPUCR_PDDS_D2_Msk                   /*!< D2 domain Power Down Deepsleep */

+#define PWR_CPUCR_PDDS_D1_Pos          (0U)

+#define PWR_CPUCR_PDDS_D1_Msk          (0x1UL << PWR_CPUCR_PDDS_D1_Pos)        /*!< 0x00000001 */

+#define PWR_CPUCR_PDDS_D1              PWR_CPUCR_PDDS_D1_Msk                   /*!< D1 domain Power Down Deepsleep selection */

+

+/********************  Bit definition for PWR_CPU2CR register  ****************/

+#define PWR_CPU2CR_RUN_D3_Pos          (11U)

+#define PWR_CPU2CR_RUN_D3_Msk          (0x1UL << PWR_CPU2CR_RUN_D3_Pos)        /*!< 0x00000800 */

+#define PWR_CPU2CR_RUN_D3              PWR_CPU2CR_RUN_D3_Msk                   /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */

+#define PWR_CPU2CR_HOLD1_Pos           (10U)

+#define PWR_CPU2CR_HOLD1_Msk           (0x1UL << PWR_CPU2CR_HOLD1_Pos)         /*!< 0x00000400 */

+#define PWR_CPU2CR_HOLD1               PWR_CPU2CR_HOLD1_Msk                    /*!< Hold the CPU1 and allocated peripherals when exiting STOP mode */

+#define PWR_CPU2CR_CSSF_Pos            (9U)

+#define PWR_CPU2CR_CSSF_Msk            (0x1UL << PWR_CPU2CR_CSSF_Pos)          /*!< 0x00000200 */

+#define PWR_CPU2CR_CSSF                PWR_CPU2CR_CSSF_Msk                     /*!< Clear D2 domain CPU2 STANDBY, STOP and HOLD flags */

+#define PWR_CPU2CR_SBF_D2_Pos          (8U)

+#define PWR_CPU2CR_SBF_D2_Msk          (0x1UL << PWR_CPU2CR_SBF_D2_Pos)        /*!< 0x00000100 */

+#define PWR_CPU2CR_SBF_D2              PWR_CPU2CR_SBF_D2_Msk                   /*!< D2 domain DSTANDBY Flag */

+#define PWR_CPU2CR_SBF_D1_Pos          (7U)

+#define PWR_CPU2CR_SBF_D1_Msk          (0x1UL << PWR_CPU2CR_SBF_D1_Pos)        /*!< 0x00000080 */

+#define PWR_CPU2CR_SBF_D1              PWR_CPU2CR_SBF_D1_Msk                   /*!< D1 domain DSTANDBY Flag */

+#define PWR_CPU2CR_SBF_Pos             (6U)

+#define PWR_CPU2CR_SBF_Msk             (0x1UL << PWR_CPU2CR_SBF_Pos)           /*!< 0x00000040 */

+#define PWR_CPU2CR_SBF                 PWR_CPU2CR_SBF_Msk                      /*!< System STANDBY Flag */

+#define PWR_CPU2CR_STOPF_Pos           (5U)

+#define PWR_CPU2CR_STOPF_Msk           (0x1UL << PWR_CPU2CR_STOPF_Pos)         /*!< 0x00000020 */

+#define PWR_CPU2CR_STOPF               PWR_CPU2CR_STOPF_Msk                    /*!< STOP Flag */

+#define PWR_CPU2CR_HOLD1F_Pos          (4U)

+#define PWR_CPU2CR_HOLD1F_Msk          (0x1UL << PWR_CPU2CR_HOLD1F_Pos)        /*!< 0x00000010 */

+#define PWR_CPU2CR_HOLD1F              PWR_CPU2CR_HOLD1F_Msk                   /*!< CPU1 in hold wakeup flag */

+#define PWR_CPU2CR_PDDS_D3_Pos         (2U)

+#define PWR_CPU2CR_PDDS_D3_Msk         (0x1UL << PWR_CPU2CR_PDDS_D3_Pos)       /*!< 0x00000004 */

+#define PWR_CPU2CR_PDDS_D3             PWR_CPU2CR_PDDS_D3_Msk                  /*!< System D3 domain Power Down Deepsleep */

+#define PWR_CPU2CR_PDDS_D2_Pos         (1U)

+#define PWR_CPU2CR_PDDS_D2_Msk         (0x1UL << PWR_CPU2CR_PDDS_D2_Pos)       /*!< 0x00000002 */

+#define PWR_CPU2CR_PDDS_D2             PWR_CPU2CR_PDDS_D2_Msk                  /*!< D2 domain Power Down Deepsleep */

+#define PWR_CPU2CR_PDDS_D1_Pos         (0U)

+#define PWR_CPU2CR_PDDS_D1_Msk         (0x1UL << PWR_CPU2CR_PDDS_D1_Pos)       /*!< 0x00000001 */

+#define PWR_CPU2CR_PDDS_D1             PWR_CPU2CR_PDDS_D1_Msk                  /*!< D1 domain Power Down Deepsleep selection */

+

+

+/********************  Bit definition for PWR_D3CR register  ******************/

+#define PWR_D3CR_VOS_Pos               (14U)

+#define PWR_D3CR_VOS_Msk               (0x3UL << PWR_D3CR_VOS_Pos)             /*!< 0x0000C000 */

+#define PWR_D3CR_VOS                   PWR_D3CR_VOS_Msk                        /*!< Voltage Scaling selection according performance */

+#define PWR_D3CR_VOS_0                 (0x1UL << PWR_D3CR_VOS_Pos)             /*!< 0x00004000 */

+#define PWR_D3CR_VOS_1                 (0x2UL << PWR_D3CR_VOS_Pos)             /*!< 0x00008000 */

+#define PWR_D3CR_VOSRDY_Pos            (13U)

+#define PWR_D3CR_VOSRDY_Msk            (0x1UL << PWR_D3CR_VOSRDY_Pos)          /*!< 0x00002000 */

+#define PWR_D3CR_VOSRDY                PWR_D3CR_VOSRDY_Msk                     /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */

+

+/******************  Bit definition for PWR_WKUPCR register  ******************/

+#define PWR_WKUPCR_WKUPC6_Pos          (5U)

+#define PWR_WKUPCR_WKUPC6_Msk          (0x1UL << PWR_WKUPCR_WKUPC6_Pos)        /*!< 0x00000020 */

+#define PWR_WKUPCR_WKUPC6              PWR_WKUPCR_WKUPC6_Msk                   /*!< Clear Wakeup Pin Flag 6 */

+#define PWR_WKUPCR_WKUPC5_Pos          (4U)

+#define PWR_WKUPCR_WKUPC5_Msk          (0x1UL << PWR_WKUPCR_WKUPC5_Pos)        /*!< 0x00000010 */

+#define PWR_WKUPCR_WKUPC5              PWR_WKUPCR_WKUPC5_Msk                   /*!< Clear Wakeup Pin Flag 5 */

+#define PWR_WKUPCR_WKUPC4_Pos          (3U)

+#define PWR_WKUPCR_WKUPC4_Msk          (0x1UL << PWR_WKUPCR_WKUPC4_Pos)        /*!< 0x00000008 */

+#define PWR_WKUPCR_WKUPC4              PWR_WKUPCR_WKUPC4_Msk                   /*!< Clear Wakeup Pin Flag 4 */

+#define PWR_WKUPCR_WKUPC3_Pos          (2U)

+#define PWR_WKUPCR_WKUPC3_Msk          (0x1UL << PWR_WKUPCR_WKUPC3_Pos)        /*!< 0x00000004 */

+#define PWR_WKUPCR_WKUPC3              PWR_WKUPCR_WKUPC3_Msk                   /*!< Clear Wakeup Pin Flag 3 */

+#define PWR_WKUPCR_WKUPC2_Pos          (1U)

+#define PWR_WKUPCR_WKUPC2_Msk          (0x1UL << PWR_WKUPCR_WKUPC2_Pos)        /*!< 0x00000002 */

+#define PWR_WKUPCR_WKUPC2              PWR_WKUPCR_WKUPC2_Msk                   /*!< Clear Wakeup Pin Flag 2 */

+#define PWR_WKUPCR_WKUPC1_Pos          (0U)

+#define PWR_WKUPCR_WKUPC1_Msk          (0x1UL << PWR_WKUPCR_WKUPC1_Pos)        /*!< 0x00000001 */

+#define PWR_WKUPCR_WKUPC1              PWR_WKUPCR_WKUPC1_Msk                   /*!< Clear Wakeup Pin Flag 1 */

+

+/********************  Bit definition for PWR_WKUPFR register  ****************/

+#define PWR_WKUPFR_WKUPF6_Pos          (5U)

+#define PWR_WKUPFR_WKUPF6_Msk          (0x1UL << PWR_WKUPFR_WKUPF6_Pos)        /*!< 0x00000020 */

+#define PWR_WKUPFR_WKUPF6              PWR_WKUPFR_WKUPF6_Msk                   /*!< Wakeup Pin Flag 6 */

+#define PWR_WKUPFR_WKUPF5_Pos          (4U)

+#define PWR_WKUPFR_WKUPF5_Msk          (0x1UL << PWR_WKUPFR_WKUPF5_Pos)        /*!< 0x00000010 */

+#define PWR_WKUPFR_WKUPF5              PWR_WKUPFR_WKUPF5_Msk                   /*!< Wakeup Pin Flag 5 */

+#define PWR_WKUPFR_WKUPF4_Pos          (3U)

+#define PWR_WKUPFR_WKUPF4_Msk          (0x1UL << PWR_WKUPFR_WKUPF4_Pos)        /*!< 0x00000008 */

+#define PWR_WKUPFR_WKUPF4              PWR_WKUPFR_WKUPF4_Msk                   /*!< Wakeup Pin Flag 4 */

+#define PWR_WKUPFR_WKUPF3_Pos          (2U)

+#define PWR_WKUPFR_WKUPF3_Msk          (0x1UL << PWR_WKUPFR_WKUPF3_Pos)        /*!< 0x00000004 */

+#define PWR_WKUPFR_WKUPF3              PWR_WKUPFR_WKUPF3_Msk                   /*!< Wakeup Pin Flag 3 */

+#define PWR_WKUPFR_WKUPF2_Pos          (1U)

+#define PWR_WKUPFR_WKUPF2_Msk          (0x1UL << PWR_WKUPFR_WKUPF2_Pos)        /*!< 0x00000002 */

+#define PWR_WKUPFR_WKUPF2              PWR_WKUPFR_WKUPF2_Msk                   /*!< Wakeup Pin Flag 2 */

+#define PWR_WKUPFR_WKUPF1_Pos          (0U)

+#define PWR_WKUPFR_WKUPF1_Msk          (0x1UL << PWR_WKUPFR_WKUPF1_Pos)        /*!< 0x00000001 */

+#define PWR_WKUPFR_WKUPF1              PWR_WKUPFR_WKUPF1_Msk                   /*!< Wakeup Pin Flag 1 */

+

+/******************  Bit definition for PWR_WKUPEPR register  *****************/

+#define PWR_WKUPEPR_WKUPPUPD6_Pos      (26U)

+#define PWR_WKUPEPR_WKUPPUPD6_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x0C000000 */

+#define PWR_WKUPEPR_WKUPPUPD6          PWR_WKUPEPR_WKUPPUPD6_Msk               /*!< Wakeup Pin pull configuration for WKUP6 */

+#define PWR_WKUPEPR_WKUPPUPD6_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x04000000 */

+#define PWR_WKUPEPR_WKUPPUPD6_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x08000000 */

+#define PWR_WKUPEPR_WKUPPUPD5_Pos      (24U)

+#define PWR_WKUPEPR_WKUPPUPD5_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x03000000 */

+#define PWR_WKUPEPR_WKUPPUPD5          PWR_WKUPEPR_WKUPPUPD5_Msk               /*!< Wakeup Pin pull configuration for WKUP5 */

+#define PWR_WKUPEPR_WKUPPUPD5_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x01000000 */

+#define PWR_WKUPEPR_WKUPPUPD5_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x02000000 */

+#define PWR_WKUPEPR_WKUPPUPD4_Pos      (22U)

+#define PWR_WKUPEPR_WKUPPUPD4_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00C00000 */

+#define PWR_WKUPEPR_WKUPPUPD4          PWR_WKUPEPR_WKUPPUPD4_Msk               /*!< Wakeup Pin pull configuration for WKUP4 */

+#define PWR_WKUPEPR_WKUPPUPD4_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00400000 */

+#define PWR_WKUPEPR_WKUPPUPD4_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00800000 */

+#define PWR_WKUPEPR_WKUPPUPD3_Pos      (20U)

+#define PWR_WKUPEPR_WKUPPUPD3_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00300000 */

+#define PWR_WKUPEPR_WKUPPUPD3          PWR_WKUPEPR_WKUPPUPD3_Msk               /*!< Wakeup Pin pull configuration for WKUP3 */

+#define PWR_WKUPEPR_WKUPPUPD3_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00100000 */

+#define PWR_WKUPEPR_WKUPPUPD3_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00200000 */

+#define PWR_WKUPEPR_WKUPPUPD2_Pos      (18U)

+#define PWR_WKUPEPR_WKUPPUPD2_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x000C0000 */

+#define PWR_WKUPEPR_WKUPPUPD2          PWR_WKUPEPR_WKUPPUPD2_Msk               /*!< Wakeup Pin pull configuration for WKUP2 */

+#define PWR_WKUPEPR_WKUPPUPD2_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00040000 */

+#define PWR_WKUPEPR_WKUPPUPD2_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00080000 */

+#define PWR_WKUPEPR_WKUPPUPD1_Pos      (16U)

+#define PWR_WKUPEPR_WKUPPUPD1_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00030000 */

+#define PWR_WKUPEPR_WKUPPUPD1          PWR_WKUPEPR_WKUPPUPD1_Msk               /*!< Wakeup Pin pull configuration for WKUP1 */

+#define PWR_WKUPEPR_WKUPPUPD1_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00010000 */

+#define PWR_WKUPEPR_WKUPPUPD1_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00020000 */

+#define PWR_WKUPEPR_WKUPP6_Pos         (13U)

+#define PWR_WKUPEPR_WKUPP6_Msk         (0x1UL << PWR_WKUPEPR_WKUPP6_Pos)       /*!< 0x00002000 */

+#define PWR_WKUPEPR_WKUPP6             PWR_WKUPEPR_WKUPP6_Msk                  /*!< Wakeup Pin Polarity for WKUP6 */

+#define PWR_WKUPEPR_WKUPP5_Pos         (12U)

+#define PWR_WKUPEPR_WKUPP5_Msk         (0x1UL << PWR_WKUPEPR_WKUPP5_Pos)       /*!< 0x00001000 */

+#define PWR_WKUPEPR_WKUPP5             PWR_WKUPEPR_WKUPP5_Msk                  /*!< Wakeup Pin Polarity for WKUP5 */

+#define PWR_WKUPEPR_WKUPP4_Pos         (11U)

+#define PWR_WKUPEPR_WKUPP4_Msk         (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)       /*!< 0x00000800 */

+#define PWR_WKUPEPR_WKUPP4             PWR_WKUPEPR_WKUPP4_Msk                  /*!< Wakeup Pin Polarity for WKUP4 */

+#define PWR_WKUPEPR_WKUPP3_Pos         (10U)

+#define PWR_WKUPEPR_WKUPP3_Msk         (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)       /*!< 0x00000400 */

+#define PWR_WKUPEPR_WKUPP3             PWR_WKUPEPR_WKUPP3_Msk                  /*!< Wakeup Pin Polarity for WKUP3 */

+#define PWR_WKUPEPR_WKUPP2_Pos         (9U)

+#define PWR_WKUPEPR_WKUPP2_Msk         (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)       /*!< 0x00000200 */

+#define PWR_WKUPEPR_WKUPP2             PWR_WKUPEPR_WKUPP2_Msk                  /*!< Wakeup Pin Polarity for WKUP2 */

+#define PWR_WKUPEPR_WKUPP1_Pos         (8U)

+#define PWR_WKUPEPR_WKUPP1_Msk         (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)       /*!< 0x00000100 */

+#define PWR_WKUPEPR_WKUPP1             PWR_WKUPEPR_WKUPP1_Msk                  /*!< Wakeup Pin Polarity for WKUP1 */

+#define PWR_WKUPEPR_WKUPEN6_Pos        (5U)

+#define PWR_WKUPEPR_WKUPEN6_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos)      /*!< 0x00000020 */

+#define PWR_WKUPEPR_WKUPEN6            PWR_WKUPEPR_WKUPEN6_Msk                 /*!< Enable Wakeup Pin WKUP6 */

+#define PWR_WKUPEPR_WKUPEN5_Pos        (4U)

+#define PWR_WKUPEPR_WKUPEN5_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos)      /*!< 0x00000010 */

+#define PWR_WKUPEPR_WKUPEN5            PWR_WKUPEPR_WKUPEN5_Msk                 /*!< Enable Wakeup Pin WKUP5 */

+#define PWR_WKUPEPR_WKUPEN4_Pos        (3U)

+#define PWR_WKUPEPR_WKUPEN4_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)      /*!< 0x00000008 */

+#define PWR_WKUPEPR_WKUPEN4            PWR_WKUPEPR_WKUPEN4_Msk                 /*!< Enable Wakeup Pin WKUP4 */

+#define PWR_WKUPEPR_WKUPEN3_Pos        (2U)

+#define PWR_WKUPEPR_WKUPEN3_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)      /*!< 0x00000004 */

+#define PWR_WKUPEPR_WKUPEN3            PWR_WKUPEPR_WKUPEN3_Msk                 /*!< Enable Wakeup Pin WKUP3 */

+#define PWR_WKUPEPR_WKUPEN2_Pos        (1U)

+#define PWR_WKUPEPR_WKUPEN2_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)      /*!< 0x00000002 */

+#define PWR_WKUPEPR_WKUPEN2            PWR_WKUPEPR_WKUPEN2_Msk                 /*!< Enable Wakeup Pin WKUP2 */

+#define PWR_WKUPEPR_WKUPEN1_Pos        (0U)

+#define PWR_WKUPEPR_WKUPEN1_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)      /*!< 0x00000001 */

+#define PWR_WKUPEPR_WKUPEN1            PWR_WKUPEPR_WKUPEN1_Msk                 /*!< Enable Wakeup Pin WKUP1 */

+#define PWR_WKUPEPR_WKUPEN_Pos         (0U)

+#define PWR_WKUPEPR_WKUPEN_Msk         (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos)      /*!< 0x0000003F */

+#define PWR_WKUPEPR_WKUPEN             PWR_WKUPEPR_WKUPEN_Msk                  /*!< Enable all Wakeup Pin */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Reset and Clock Control                            */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  RCC VERSION  ********************************/

+#define RCC_VER_X

+

+/********************  Bit definition for RCC_CR register  ********************/

+#define RCC_CR_HSION_Pos                       (0U)

+#define RCC_CR_HSION_Msk                       (0x1UL << RCC_CR_HSION_Pos)     /*!< 0x00000001 */

+#define RCC_CR_HSION                           RCC_CR_HSION_Msk                /*!< Internal High Speed clock enable */

+#define RCC_CR_HSIKERON_Pos                    (1U)

+#define RCC_CR_HSIKERON_Msk                    (0x1UL << RCC_CR_HSIKERON_Pos)  /*!< 0x00000002 */

+#define RCC_CR_HSIKERON                        RCC_CR_HSIKERON_Msk             /*!< Internal High Speed clock enable for some IPs Kernel */

+#define RCC_CR_HSIRDY_Pos                      (2U)

+#define RCC_CR_HSIRDY_Msk                      (0x1UL << RCC_CR_HSIRDY_Pos)    /*!< 0x00000004 */

+#define RCC_CR_HSIRDY                          RCC_CR_HSIRDY_Msk               /*!< Internal High Speed clock ready flag */

+#define RCC_CR_HSIDIV_Pos                      (3U)

+#define RCC_CR_HSIDIV_Msk                      (0x3UL << RCC_CR_HSIDIV_Pos)    /*!< 0x00000018 */

+#define RCC_CR_HSIDIV                          RCC_CR_HSIDIV_Msk               /*!< Internal High Speed clock divider selection */

+#define RCC_CR_HSIDIV_1                        (0x0UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000000 */

+#define RCC_CR_HSIDIV_2                        (0x1UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000008 */

+#define RCC_CR_HSIDIV_4                        (0x2UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000010 */

+#define RCC_CR_HSIDIV_8                        (0x3UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000018 */

+

+#define RCC_CR_HSIDIVF_Pos                     (5U)

+#define RCC_CR_HSIDIVF_Msk                     (0x1UL << RCC_CR_HSIDIVF_Pos)   /*!< 0x00000020 */

+#define RCC_CR_HSIDIVF                         RCC_CR_HSIDIVF_Msk              /*!< HSI Divider flag */

+#define RCC_CR_CSION_Pos                       (7U)

+#define RCC_CR_CSION_Msk                       (0x1UL << RCC_CR_CSION_Pos)     /*!< 0x00000080 */

+#define RCC_CR_CSION                           RCC_CR_CSION_Msk                /*!< The Internal RC 4MHz oscillator clock enable */

+#define RCC_CR_CSIRDY_Pos                      (8U)

+#define RCC_CR_CSIRDY_Msk                      (0x1UL << RCC_CR_CSIRDY_Pos)    /*!< 0x00000100 */

+#define RCC_CR_CSIRDY                          RCC_CR_CSIRDY_Msk               /*!< The Internal RC 4MHz oscillator clock ready */

+#define RCC_CR_CSIKERON_Pos                    (9U)

+#define RCC_CR_CSIKERON_Msk                    (0x1UL << RCC_CR_CSIKERON_Pos)  /*!< 0x00000200 */

+#define RCC_CR_CSIKERON                        RCC_CR_CSIKERON_Msk             /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */

+#define RCC_CR_HSI48ON_Pos                     (12U)

+#define RCC_CR_HSI48ON_Msk                     (0x1UL << RCC_CR_HSI48ON_Pos)   /*!< 0x00001000 */

+#define RCC_CR_HSI48ON                         RCC_CR_HSI48ON_Msk              /*!< HSI48 clock enable clock enable  */

+#define RCC_CR_HSI48RDY_Pos                    (13U)

+#define RCC_CR_HSI48RDY_Msk                    (0x1UL << RCC_CR_HSI48RDY_Pos)  /*!< 0x00002000 */

+#define RCC_CR_HSI48RDY                        RCC_CR_HSI48RDY_Msk             /*!< HSI48 clock ready */

+

+#define RCC_CR_D1CKRDY_Pos                     (14U)

+#define RCC_CR_D1CKRDY_Msk                     (0x1UL << RCC_CR_D1CKRDY_Pos)   /*!< 0x00004000 */

+#define RCC_CR_D1CKRDY                         RCC_CR_D1CKRDY_Msk              /*!< D1 domain clocks ready flag  */

+#define RCC_CR_D2CKRDY_Pos                     (15U)

+#define RCC_CR_D2CKRDY_Msk                     (0x1UL << RCC_CR_D2CKRDY_Pos)   /*!< 0x00008000 */

+#define RCC_CR_D2CKRDY                         RCC_CR_D2CKRDY_Msk              /*!< D2 domain clocks ready flag */

+

+#define RCC_CR_HSEON_Pos                       (16U)

+#define RCC_CR_HSEON_Msk                       (0x1UL << RCC_CR_HSEON_Pos)     /*!< 0x00010000 */

+#define RCC_CR_HSEON                           RCC_CR_HSEON_Msk                /*!< External High Speed clock enable */

+#define RCC_CR_HSERDY_Pos                      (17U)

+#define RCC_CR_HSERDY_Msk                      (0x1UL << RCC_CR_HSERDY_Pos)    /*!< 0x00020000 */

+#define RCC_CR_HSERDY                          RCC_CR_HSERDY_Msk               /*!< External High Speed clock ready */

+#define RCC_CR_HSEBYP_Pos                      (18U)

+#define RCC_CR_HSEBYP_Msk                      (0x1UL << RCC_CR_HSEBYP_Pos)    /*!< 0x00040000 */

+#define RCC_CR_HSEBYP                          RCC_CR_HSEBYP_Msk               /*!< External High Speed clock Bypass */

+#define RCC_CR_CSSHSEON_Pos                    (19U)

+#define RCC_CR_CSSHSEON_Msk                    (0x1UL << RCC_CR_CSSHSEON_Pos)  /*!< 0x00080000 */

+#define RCC_CR_CSSHSEON                        RCC_CR_CSSHSEON_Msk             /*!< HSE Clock security System enable */

+

+

+#define RCC_CR_PLL1ON_Pos                      (24U)

+#define RCC_CR_PLL1ON_Msk                      (0x1UL << RCC_CR_PLL1ON_Pos)    /*!< 0x01000000 */

+#define RCC_CR_PLL1ON                          RCC_CR_PLL1ON_Msk               /*!< System PLL1 clock enable */

+#define RCC_CR_PLL1RDY_Pos                     (25U)

+#define RCC_CR_PLL1RDY_Msk                     (0x1UL << RCC_CR_PLL1RDY_Pos)   /*!< 0x02000000 */

+#define RCC_CR_PLL1RDY                         RCC_CR_PLL1RDY_Msk              /*!< System PLL1 clock ready */

+#define RCC_CR_PLL2ON_Pos                      (26U)

+#define RCC_CR_PLL2ON_Msk                      (0x1UL << RCC_CR_PLL2ON_Pos)    /*!< 0x04000000 */

+#define RCC_CR_PLL2ON                          RCC_CR_PLL2ON_Msk               /*!< System PLL2 clock enable */

+#define RCC_CR_PLL2RDY_Pos                     (27U)

+#define RCC_CR_PLL2RDY_Msk                     (0x1UL << RCC_CR_PLL2RDY_Pos)   /*!< 0x08000000 */

+#define RCC_CR_PLL2RDY                         RCC_CR_PLL2RDY_Msk              /*!< System PLL2 clock ready */

+#define RCC_CR_PLL3ON_Pos                      (28U)

+#define RCC_CR_PLL3ON_Msk                      (0x1UL << RCC_CR_PLL3ON_Pos)    /*!< 0x10000000 */

+#define RCC_CR_PLL3ON                          RCC_CR_PLL3ON_Msk               /*!< System PLL3 clock enable */

+#define RCC_CR_PLL3RDY_Pos                     (29U)

+#define RCC_CR_PLL3RDY_Msk                     (0x1UL << RCC_CR_PLL3RDY_Pos)   /*!< 0x20000000 */

+#define RCC_CR_PLL3RDY                         RCC_CR_PLL3RDY_Msk              /*!< System PLL3 clock ready */

+

+/*Legacy */

+#define RCC_CR_PLLON_Pos                       (24U)

+#define RCC_CR_PLLON_Msk                       (0x1UL << RCC_CR_PLLON_Pos)     /*!< 0x01000000 */

+#define RCC_CR_PLLON                           RCC_CR_PLLON_Msk                /*!< System PLL clock enable */

+#define RCC_CR_PLLRDY_Pos                      (25U)

+#define RCC_CR_PLLRDY_Msk                      (0x1UL << RCC_CR_PLLRDY_Pos)    /*!< 0x02000000 */

+#define RCC_CR_PLLRDY                          RCC_CR_PLLRDY_Msk               /*!< System PLL clock ready */

+

+/********************  Bit definition for RCC_HSICFGR register  ***************/

+/*!< HSICAL configuration */

+#define RCC_HSICFGR_HSICAL_Pos                 (0U)

+#define RCC_HSICFGR_HSICAL_Msk                 (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */

+#define RCC_HSICFGR_HSICAL                     RCC_HSICFGR_HSICAL_Msk          /*!< HSICAL[11:0] bits */

+#define RCC_HSICFGR_HSICAL_0                   (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */

+#define RCC_HSICFGR_HSICAL_1                   (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */

+#define RCC_HSICFGR_HSICAL_2                   (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */

+#define RCC_HSICFGR_HSICAL_3                   (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */

+#define RCC_HSICFGR_HSICAL_4                   (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */

+#define RCC_HSICFGR_HSICAL_5                   (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */

+#define RCC_HSICFGR_HSICAL_6                   (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */

+#define RCC_HSICFGR_HSICAL_7                   (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */

+#define RCC_HSICFGR_HSICAL_8                   (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */

+#define RCC_HSICFGR_HSICAL_9                   (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */

+#define RCC_HSICFGR_HSICAL_10                  (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */

+#define RCC_HSICFGR_HSICAL_11                  (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */

+

+/*!< HSITRIM configuration */

+#define RCC_HSICFGR_HSITRIM_Pos                (24U)

+#define RCC_HSICFGR_HSITRIM_Msk                (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */

+#define RCC_HSICFGR_HSITRIM                    RCC_HSICFGR_HSITRIM_Msk         /*!< HSITRIM[6:0] bits */

+#define RCC_HSICFGR_HSITRIM_0                  (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */

+#define RCC_HSICFGR_HSITRIM_1                  (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */

+#define RCC_HSICFGR_HSITRIM_2                  (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */

+#define RCC_HSICFGR_HSITRIM_3                  (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */

+#define RCC_HSICFGR_HSITRIM_4                  (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */

+#define RCC_HSICFGR_HSITRIM_5                  (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */

+#define RCC_HSICFGR_HSITRIM_6                  (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */

+

+

+/********************  Bit definition for RCC_CRRCR register  *****************/

+

+/*!< HSI48CAL configuration */

+#define RCC_CRRCR_HSI48CAL_Pos                 (0U)

+#define RCC_CRRCR_HSI48CAL_Msk                 (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */

+#define RCC_CRRCR_HSI48CAL                     RCC_CRRCR_HSI48CAL_Msk          /*!< HSI48CAL[9:0] bits */

+#define RCC_CRRCR_HSI48CAL_0                   (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */

+#define RCC_CRRCR_HSI48CAL_1                   (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */

+#define RCC_CRRCR_HSI48CAL_2                   (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */

+#define RCC_CRRCR_HSI48CAL_3                   (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */

+#define RCC_CRRCR_HSI48CAL_4                   (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */

+#define RCC_CRRCR_HSI48CAL_5                   (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */

+#define RCC_CRRCR_HSI48CAL_6                   (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */

+#define RCC_CRRCR_HSI48CAL_7                   (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */

+#define RCC_CRRCR_HSI48CAL_8                   (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */

+#define RCC_CRRCR_HSI48CAL_9                   (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */

+

+

+/********************  Bit definition for RCC_CSICFGR register  *****************/

+/*!< CSICAL configuration */

+#define RCC_CSICFGR_CSICAL_Pos                 (0U)

+#define RCC_CSICFGR_CSICAL_Msk                 (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */

+#define RCC_CSICFGR_CSICAL                     RCC_CSICFGR_CSICAL_Msk          /*!< CSICAL[7:0] bits */

+#define RCC_CSICFGR_CSICAL_0                   (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */

+#define RCC_CSICFGR_CSICAL_1                   (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */

+#define RCC_CSICFGR_CSICAL_2                   (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */

+#define RCC_CSICFGR_CSICAL_3                   (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */

+#define RCC_CSICFGR_CSICAL_4                   (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */

+#define RCC_CSICFGR_CSICAL_5                   (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */

+#define RCC_CSICFGR_CSICAL_6                   (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */

+#define RCC_CSICFGR_CSICAL_7                   (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */

+

+/*!< CSITRIM configuration */

+#define RCC_CSICFGR_CSITRIM_Pos                (24U)

+#define RCC_CSICFGR_CSITRIM_Msk                (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */

+#define RCC_CSICFGR_CSITRIM                    RCC_CSICFGR_CSITRIM_Msk         /*!< CSITRIM[5:0] bits */

+#define RCC_CSICFGR_CSITRIM_0                  (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */

+#define RCC_CSICFGR_CSITRIM_1                  (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */

+#define RCC_CSICFGR_CSITRIM_2                  (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */

+#define RCC_CSICFGR_CSITRIM_3                  (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */

+#define RCC_CSICFGR_CSITRIM_4                  (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */

+#define RCC_CSICFGR_CSITRIM_5                  (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */

+

+/********************  Bit definition for RCC_CFGR register  ******************/

+/*!< SW configuration */

+#define RCC_CFGR_SW_Pos                        (0U)

+#define RCC_CFGR_SW_Msk                        (0x7UL << RCC_CFGR_SW_Pos)           /*!< 0x00000007 */

+#define RCC_CFGR_SW                            RCC_CFGR_SW_Msk                     /*!< SW[2:0] bits (System clock Switch) */

+#define RCC_CFGR_SW_0                          (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */

+#define RCC_CFGR_SW_1                          (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */

+#define RCC_CFGR_SW_2                          (0x4UL << RCC_CFGR_SW_Pos)           /*!< 0x00000004 */

+

+#define RCC_CFGR_SW_HSI                        (0x00000000UL)                       /*!< HSI selection as system clock */

+#define RCC_CFGR_SW_CSI                        (0x00000001UL)                       /*!< CSI selection as system clock */

+#define RCC_CFGR_SW_HSE                        (0x00000002UL)                       /*!< HSE selection as system clock */

+#define RCC_CFGR_SW_PLL1                       (0x00000003UL)                       /*!< PLL1 selection as system clock */

+

+/*!< SWS configuration */

+#define RCC_CFGR_SWS_Pos                       (3U)

+#define RCC_CFGR_SWS_Msk                       (0x7UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000038 */

+#define RCC_CFGR_SWS                           RCC_CFGR_SWS_Msk                    /*!< SWS[2:0] bits (System Clock Switch Status) */

+#define RCC_CFGR_SWS_0                         (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */

+#define RCC_CFGR_SWS_1                         (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000010 */

+#define RCC_CFGR_SWS_2                         (0x4UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000020 */

+

+#define RCC_CFGR_SWS_HSI                       (0x00000000UL)                       /*!< HSI used as system clock */

+#define RCC_CFGR_SWS_CSI                       (0x00000008UL)                       /*!< CSI used as system clock */

+#define RCC_CFGR_SWS_HSE                       (0x00000010UL)                       /*!< HSE used as system clock */

+#define RCC_CFGR_SWS_PLL1                      (0x00000018UL)                       /*!< PLL1 used as system clock */

+

+#define RCC_CFGR_STOPWUCK_Pos                  (6U)

+#define RCC_CFGR_STOPWUCK_Msk                  (0x1UL << RCC_CFGR_STOPWUCK_Pos)     /*!< 0x00000040 */

+#define RCC_CFGR_STOPWUCK                      RCC_CFGR_STOPWUCK_Msk                /*!< Wake Up from stop and CSS backup clock selection */

+

+#define RCC_CFGR_STOPKERWUCK_Pos               (7U)

+#define RCC_CFGR_STOPKERWUCK_Msk               (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)  /*!< 0x00000080 */

+#define RCC_CFGR_STOPKERWUCK                   RCC_CFGR_STOPKERWUCK_Msk             /*!< Kernel Clock Selection after a Wake Up from STOP */

+

+/*!< RTCPRE configuration */

+#define RCC_CFGR_RTCPRE_Pos                    (8U)

+#define RCC_CFGR_RTCPRE_Msk                    (0x3FUL << RCC_CFGR_RTCPRE_Pos)

+#define RCC_CFGR_RTCPRE                        RCC_CFGR_RTCPRE_Msk                  /*!< 0x00003F00 */

+#define RCC_CFGR_RTCPRE_0                      (0x1UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000100 */

+#define RCC_CFGR_RTCPRE_1                      (0x2UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000200 */

+#define RCC_CFGR_RTCPRE_2                      (0x4UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000400 */

+#define RCC_CFGR_RTCPRE_3                      (0x8UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000800 */

+#define RCC_CFGR_RTCPRE_4                      (0x10UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00001000 */

+#define RCC_CFGR_RTCPRE_5                      (0x20UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00002000 */

+

+/*!< HRTIMSEL configuration */

+#define RCC_CFGR_HRTIMSEL_Pos                  (14U)

+#define RCC_CFGR_HRTIMSEL_Msk                  (0x1UL << RCC_CFGR_HRTIMSEL_Pos)

+#define RCC_CFGR_HRTIMSEL                      RCC_CFGR_HRTIMSEL_Msk                /*!< 0x00004000 */

+

+/*!< TIMPRE configuration */

+#define RCC_CFGR_TIMPRE_Pos                    (15U)

+#define RCC_CFGR_TIMPRE_Msk                    (0x1UL << RCC_CFGR_TIMPRE_Pos)

+#define RCC_CFGR_TIMPRE                        RCC_CFGR_TIMPRE_Msk                  /*!< 0x00008000 */

+

+/*!< MCO1 configuration */

+#define RCC_CFGR_MCO1_Pos                      (22U)

+#define RCC_CFGR_MCO1_Msk                      (0x7UL << RCC_CFGR_MCO1_Pos)

+#define RCC_CFGR_MCO1                          RCC_CFGR_MCO1_Msk                       /*!< 0x01C00000 */

+#define RCC_CFGR_MCO1_0                        (0x1UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00400000 */

+#define RCC_CFGR_MCO1_1                        (0x2UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00800000 */

+#define RCC_CFGR_MCO1_2                        (0x4UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x01000000 */

+

+#define RCC_CFGR_MCO1PRE_Pos                   (18U)

+#define RCC_CFGR_MCO1PRE_Msk                   (0xFUL << RCC_CFGR_MCO1PRE_Pos)

+#define RCC_CFGR_MCO1PRE                       RCC_CFGR_MCO1PRE_Msk                    /*!< 0x003C0000 */

+#define RCC_CFGR_MCO1PRE_0                     (0x1UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00040000 */

+#define RCC_CFGR_MCO1PRE_1                     (0x2UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00080000 */

+#define RCC_CFGR_MCO1PRE_2                     (0x4UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00100000 */

+#define RCC_CFGR_MCO1PRE_3                     (0x8UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00200000 */

+

+#define RCC_CFGR_MCO2PRE_Pos                   (25U)

+#define RCC_CFGR_MCO2PRE_Msk                   (0xFUL << RCC_CFGR_MCO2PRE_Pos)

+#define RCC_CFGR_MCO2PRE                       RCC_CFGR_MCO2PRE_Msk                    /*!< 0x1E000000 */

+#define RCC_CFGR_MCO2PRE_0                     (0x1UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x02000000 */

+#define RCC_CFGR_MCO2PRE_1                     (0x2UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x04000000 */

+#define RCC_CFGR_MCO2PRE_2                     (0x4UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x08000000 */

+#define RCC_CFGR_MCO2PRE_3                     (0x8UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x10000000 */

+

+#define RCC_CFGR_MCO2_Pos                      (29U)

+#define RCC_CFGR_MCO2_Msk                      (0x7UL << RCC_CFGR_MCO2_Pos)

+#define RCC_CFGR_MCO2                          RCC_CFGR_MCO2_Msk                       /*!< 0xE0000000 */

+#define RCC_CFGR_MCO2_0                        (0x1UL << RCC_CFGR_MCO2_Pos)             /*!< 0x20000000 */

+#define RCC_CFGR_MCO2_1                        (0x2UL << RCC_CFGR_MCO2_Pos)             /*!< 0x40000000 */

+#define RCC_CFGR_MCO2_2                        (0x4UL << RCC_CFGR_MCO2_Pos)             /*!< 0x80000000 */

+

+/********************  Bit definition for RCC_D1CFGR register  ******************/

+/*!< D1HPRE configuration */

+#define RCC_D1CFGR_HPRE_Pos                    (0U)

+#define RCC_D1CFGR_HPRE_Msk                    (0xFUL << RCC_D1CFGR_HPRE_Pos)  /*!< 0x0000000F */

+#define RCC_D1CFGR_HPRE                        RCC_D1CFGR_HPRE_Msk             /*!< HPRE[3:0] bits (AHB3 prescaler) */

+#define RCC_D1CFGR_HPRE_0                      (0x1UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000001 */

+#define RCC_D1CFGR_HPRE_1                      (0x2UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000002 */

+#define RCC_D1CFGR_HPRE_2                      (0x4UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000004 */

+#define RCC_D1CFGR_HPRE_3                      (0x8UL << RCC_D1CFGR_HPRE_Pos)   /*!< 0x00000008 */

+

+

+#define RCC_D1CFGR_HPRE_DIV1                   ((uint32_t)0x00000000)          /*!< AHB3 Clock not divided */

+#define RCC_D1CFGR_HPRE_DIV2_Pos               (3U)

+#define RCC_D1CFGR_HPRE_DIV2_Msk               (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */

+#define RCC_D1CFGR_HPRE_DIV2                   RCC_D1CFGR_HPRE_DIV2_Msk        /*!< AHB3 Clock divided by 2 */

+#define RCC_D1CFGR_HPRE_DIV4_Pos               (0U)

+#define RCC_D1CFGR_HPRE_DIV4_Msk               (0x9UL << RCC_D1CFGR_HPRE_DIV4_Pos) /*!< 0x00000009 */

+#define RCC_D1CFGR_HPRE_DIV4                   RCC_D1CFGR_HPRE_DIV4_Msk        /*!< AHB3 Clock divided by 4 */

+#define RCC_D1CFGR_HPRE_DIV8_Pos               (1U)

+#define RCC_D1CFGR_HPRE_DIV8_Msk               (0x5UL << RCC_D1CFGR_HPRE_DIV8_Pos) /*!< 0x0000000A */

+#define RCC_D1CFGR_HPRE_DIV8                   RCC_D1CFGR_HPRE_DIV8_Msk        /*!< AHB3 Clock divided by 8 */

+#define RCC_D1CFGR_HPRE_DIV16_Pos              (0U)

+#define RCC_D1CFGR_HPRE_DIV16_Msk              (0xBUL << RCC_D1CFGR_HPRE_DIV16_Pos) /*!< 0x0000000B */

+#define RCC_D1CFGR_HPRE_DIV16                  RCC_D1CFGR_HPRE_DIV16_Msk       /*!< AHB3 Clock divided by 16 */

+#define RCC_D1CFGR_HPRE_DIV64_Pos              (2U)

+#define RCC_D1CFGR_HPRE_DIV64_Msk              (0x3UL << RCC_D1CFGR_HPRE_DIV64_Pos) /*!< 0x0000000C */

+#define RCC_D1CFGR_HPRE_DIV64                  RCC_D1CFGR_HPRE_DIV64_Msk       /*!< AHB3 Clock divided by 64 */

+#define RCC_D1CFGR_HPRE_DIV128_Pos             (0U)

+#define RCC_D1CFGR_HPRE_DIV128_Msk             (0xDUL << RCC_D1CFGR_HPRE_DIV128_Pos) /*!< 0x0000000D */

+#define RCC_D1CFGR_HPRE_DIV128                 RCC_D1CFGR_HPRE_DIV128_Msk      /*!< AHB3 Clock divided by 128 */

+#define RCC_D1CFGR_HPRE_DIV256_Pos             (1U)

+#define RCC_D1CFGR_HPRE_DIV256_Msk             (0x7UL << RCC_D1CFGR_HPRE_DIV256_Pos) /*!< 0x0000000E */

+#define RCC_D1CFGR_HPRE_DIV256                 RCC_D1CFGR_HPRE_DIV256_Msk      /*!< AHB3 Clock divided by 256 */

+#define RCC_D1CFGR_HPRE_DIV512_Pos             (0U)

+#define RCC_D1CFGR_HPRE_DIV512_Msk             (0xFUL << RCC_D1CFGR_HPRE_DIV512_Pos) /*!< 0x0000000F */

+#define RCC_D1CFGR_HPRE_DIV512                 RCC_D1CFGR_HPRE_DIV512_Msk      /*!< AHB3 Clock divided by 512 */

+

+/*!< D1PPRE configuration */

+#define RCC_D1CFGR_D1PPRE_Pos                  (4U)

+#define RCC_D1CFGR_D1PPRE_Msk                  (0x7UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000070 */

+#define RCC_D1CFGR_D1PPRE                      RCC_D1CFGR_D1PPRE_Msk           /*!< D1PRE[2:0] bits (APB3 prescaler) */

+#define RCC_D1CFGR_D1PPRE_0                    (0x1UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000010 */

+#define RCC_D1CFGR_D1PPRE_1                    (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */

+#define RCC_D1CFGR_D1PPRE_2                    (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */

+

+#define RCC_D1CFGR_D1PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB3 clock not divided */

+#define RCC_D1CFGR_D1PPRE_DIV2_Pos             (6U)

+#define RCC_D1CFGR_D1PPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_D1CFGR_D1PPRE_DIV2                 RCC_D1CFGR_D1PPRE_DIV2_Msk      /*!< APB3 clock divided by 2 */

+#define RCC_D1CFGR_D1PPRE_DIV4_Pos             (4U)

+#define RCC_D1CFGR_D1PPRE_DIV4_Msk             (0x5UL << RCC_D1CFGR_D1PPRE_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_D1CFGR_D1PPRE_DIV4                 RCC_D1CFGR_D1PPRE_DIV4_Msk      /*!< APB3 clock divided by 4 */

+#define RCC_D1CFGR_D1PPRE_DIV8_Pos             (5U)

+#define RCC_D1CFGR_D1PPRE_DIV8_Msk             (0x3UL << RCC_D1CFGR_D1PPRE_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_D1CFGR_D1PPRE_DIV8                 RCC_D1CFGR_D1PPRE_DIV8_Msk      /*!< APB3 clock divided by 8 */

+#define RCC_D1CFGR_D1PPRE_DIV16_Pos            (4U)

+#define RCC_D1CFGR_D1PPRE_DIV16_Msk            (0x7UL << RCC_D1CFGR_D1PPRE_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_D1CFGR_D1PPRE_DIV16                RCC_D1CFGR_D1PPRE_DIV16_Msk     /*!< APB3 clock divided by 16 */

+

+#define RCC_D1CFGR_D1CPRE_Pos                  (8U)

+#define RCC_D1CFGR_D1CPRE_Msk                  (0xFUL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000F00 */

+#define RCC_D1CFGR_D1CPRE                      RCC_D1CFGR_D1CPRE_Msk           /*!< D1CPRE[2:0] bits (Domain 1 Core prescaler) */

+#define RCC_D1CFGR_D1CPRE_0                    (0x1UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000100 */

+#define RCC_D1CFGR_D1CPRE_1                    (0x2UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000200 */

+#define RCC_D1CFGR_D1CPRE_2                    (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */

+#define RCC_D1CFGR_D1CPRE_3                    (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */

+

+#define RCC_D1CFGR_D1CPRE_DIV1                 ((uint32_t)0x00000000)          /*!< Domain 1 Core clock not divided */

+#define RCC_D1CFGR_D1CPRE_DIV2_Pos             (11U)

+#define RCC_D1CFGR_D1CPRE_DIV2_Msk             (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */

+#define RCC_D1CFGR_D1CPRE_DIV2                 RCC_D1CFGR_D1CPRE_DIV2_Msk      /*!< Domain 1 Core clock divided by 2 */

+#define RCC_D1CFGR_D1CPRE_DIV4_Pos             (8U)

+#define RCC_D1CFGR_D1CPRE_DIV4_Msk             (0x9UL << RCC_D1CFGR_D1CPRE_DIV4_Pos) /*!< 0x00000900 */

+#define RCC_D1CFGR_D1CPRE_DIV4                 RCC_D1CFGR_D1CPRE_DIV4_Msk      /*!< Domain 1 Core clock divided by 4 */

+#define RCC_D1CFGR_D1CPRE_DIV8_Pos             (9U)

+#define RCC_D1CFGR_D1CPRE_DIV8_Msk             (0x5UL << RCC_D1CFGR_D1CPRE_DIV8_Pos) /*!< 0x00000A00 */

+#define RCC_D1CFGR_D1CPRE_DIV8                 RCC_D1CFGR_D1CPRE_DIV8_Msk      /*!< Domain 1 Core clock divided by 8 */

+#define RCC_D1CFGR_D1CPRE_DIV16_Pos            (8U)

+#define RCC_D1CFGR_D1CPRE_DIV16_Msk            (0xBUL << RCC_D1CFGR_D1CPRE_DIV16_Pos) /*!< 0x00000B00 */

+#define RCC_D1CFGR_D1CPRE_DIV16                RCC_D1CFGR_D1CPRE_DIV16_Msk     /*!< Domain 1 Core clock divided by 16 */

+#define RCC_D1CFGR_D1CPRE_DIV64_Pos            (10U)

+#define RCC_D1CFGR_D1CPRE_DIV64_Msk            (0x3UL << RCC_D1CFGR_D1CPRE_DIV64_Pos) /*!< 0x00000C00 */

+#define RCC_D1CFGR_D1CPRE_DIV64                RCC_D1CFGR_D1CPRE_DIV64_Msk     /*!< Domain 1 Core clock divided by 64 */

+#define RCC_D1CFGR_D1CPRE_DIV128_Pos           (8U)

+#define RCC_D1CFGR_D1CPRE_DIV128_Msk           (0xDUL << RCC_D1CFGR_D1CPRE_DIV128_Pos) /*!< 0x00000D00 */

+#define RCC_D1CFGR_D1CPRE_DIV128               RCC_D1CFGR_D1CPRE_DIV128_Msk    /*!< Domain 1 Core clock divided by 128 */

+#define RCC_D1CFGR_D1CPRE_DIV256_Pos           (9U)

+#define RCC_D1CFGR_D1CPRE_DIV256_Msk           (0x7UL << RCC_D1CFGR_D1CPRE_DIV256_Pos) /*!< 0x00000E00 */

+#define RCC_D1CFGR_D1CPRE_DIV256               RCC_D1CFGR_D1CPRE_DIV256_Msk    /*!< Domain 1 Core clock divided by 256 */

+#define RCC_D1CFGR_D1CPRE_DIV512_Pos           (8U)

+#define RCC_D1CFGR_D1CPRE_DIV512_Msk           (0xFUL << RCC_D1CFGR_D1CPRE_DIV512_Pos) /*!< 0x00000F00 */

+#define RCC_D1CFGR_D1CPRE_DIV512               RCC_D1CFGR_D1CPRE_DIV512_Msk    /*!< Domain 1 Core clock divided by 512 */

+

+/********************  Bit definition for RCC_D2CFGR register  ******************/

+/*!< D2PPRE1 configuration */

+#define RCC_D2CFGR_D2PPRE1_Pos                 (4U)

+#define RCC_D2CFGR_D2PPRE1_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000070 */

+#define RCC_D2CFGR_D2PPRE1                     RCC_D2CFGR_D2PPRE1_Msk          /*!< D1PPRE1[2:0] bits (APB1 prescaler) */

+#define RCC_D2CFGR_D2PPRE1_0                   (0x1UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000010 */

+#define RCC_D2CFGR_D2PPRE1_1                   (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */

+#define RCC_D2CFGR_D2PPRE1_2                   (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */

+

+#define RCC_D2CFGR_D2PPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */

+#define RCC_D2CFGR_D2PPRE1_DIV2_Pos            (6U)

+#define RCC_D2CFGR_D2PPRE1_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_D2CFGR_D2PPRE1_DIV2                RCC_D2CFGR_D2PPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */

+#define RCC_D2CFGR_D2PPRE1_DIV4_Pos            (4U)

+#define RCC_D2CFGR_D2PPRE1_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE1_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_D2CFGR_D2PPRE1_DIV4                RCC_D2CFGR_D2PPRE1_DIV4_Msk     /*!< APB1 clock divided by 4 */

+#define RCC_D2CFGR_D2PPRE1_DIV8_Pos            (5U)

+#define RCC_D2CFGR_D2PPRE1_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE1_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_D2CFGR_D2PPRE1_DIV8                RCC_D2CFGR_D2PPRE1_DIV8_Msk     /*!< APB1 clock divided by 8 */

+#define RCC_D2CFGR_D2PPRE1_DIV16_Pos           (4U)

+#define RCC_D2CFGR_D2PPRE1_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE1_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_D2CFGR_D2PPRE1_DIV16               RCC_D2CFGR_D2PPRE1_DIV16_Msk    /*!< APB1 clock divided by 16 */

+

+/*!< D2PPRE2 configuration */

+#define RCC_D2CFGR_D2PPRE2_Pos                 (8U)

+#define RCC_D2CFGR_D2PPRE2_Msk                 (0x7UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000700 */

+#define RCC_D2CFGR_D2PPRE2                     RCC_D2CFGR_D2PPRE2_Msk          /*!< D2PPRE2[2:0] bits (APB2 prescaler) */

+#define RCC_D2CFGR_D2PPRE2_0                   (0x1UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000100 */

+#define RCC_D2CFGR_D2PPRE2_1                   (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */

+#define RCC_D2CFGR_D2PPRE2_2                   (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */

+

+#define RCC_D2CFGR_D2PPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */

+#define RCC_D2CFGR_D2PPRE2_DIV2_Pos            (10U)

+#define RCC_D2CFGR_D2PPRE2_DIV2_Msk            (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */

+#define RCC_D2CFGR_D2PPRE2_DIV2                RCC_D2CFGR_D2PPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */

+#define RCC_D2CFGR_D2PPRE2_DIV4_Pos            (8U)

+#define RCC_D2CFGR_D2PPRE2_DIV4_Msk            (0x5UL << RCC_D2CFGR_D2PPRE2_DIV4_Pos) /*!< 0x00000500 */

+#define RCC_D2CFGR_D2PPRE2_DIV4                RCC_D2CFGR_D2PPRE2_DIV4_Msk     /*!< APB2 clock divided by 4 */

+#define RCC_D2CFGR_D2PPRE2_DIV8_Pos            (9U)

+#define RCC_D2CFGR_D2PPRE2_DIV8_Msk            (0x3UL << RCC_D2CFGR_D2PPRE2_DIV8_Pos) /*!< 0x00000600 */

+#define RCC_D2CFGR_D2PPRE2_DIV8                RCC_D2CFGR_D2PPRE2_DIV8_Msk     /*!< APB2 clock divided by 8 */

+#define RCC_D2CFGR_D2PPRE2_DIV16_Pos           (8U)

+#define RCC_D2CFGR_D2PPRE2_DIV16_Msk           (0x7UL << RCC_D2CFGR_D2PPRE2_DIV16_Pos) /*!< 0x00000700 */

+#define RCC_D2CFGR_D2PPRE2_DIV16               RCC_D2CFGR_D2PPRE2_DIV16_Msk    /*!< APB2 clock divided by 16 */

+

+/********************  Bit definition for RCC_D3CFGR register  ******************/

+/*!< D3PPRE configuration */

+#define RCC_D3CFGR_D3PPRE_Pos                  (4U)

+#define RCC_D3CFGR_D3PPRE_Msk                  (0x7UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000070 */

+#define RCC_D3CFGR_D3PPRE                      RCC_D3CFGR_D3PPRE_Msk           /*!< D3PPRE1[2:0] bits (APB4 prescaler) */

+#define RCC_D3CFGR_D3PPRE_0                    (0x1UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000010 */

+#define RCC_D3CFGR_D3PPRE_1                    (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */

+#define RCC_D3CFGR_D3PPRE_2                    (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */

+

+#define RCC_D3CFGR_D3PPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */

+#define RCC_D3CFGR_D3PPRE_DIV2_Pos             (6U)

+#define RCC_D3CFGR_D3PPRE_DIV2_Msk             (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_D3CFGR_D3PPRE_DIV2                 RCC_D3CFGR_D3PPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */

+#define RCC_D3CFGR_D3PPRE_DIV4_Pos             (4U)

+#define RCC_D3CFGR_D3PPRE_DIV4_Msk             (0x5UL << RCC_D3CFGR_D3PPRE_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_D3CFGR_D3PPRE_DIV4                 RCC_D3CFGR_D3PPRE_DIV4_Msk      /*!< APB4 clock divided by 4 */

+#define RCC_D3CFGR_D3PPRE_DIV8_Pos             (5U)

+#define RCC_D3CFGR_D3PPRE_DIV8_Msk             (0x3UL << RCC_D3CFGR_D3PPRE_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_D3CFGR_D3PPRE_DIV8                 RCC_D3CFGR_D3PPRE_DIV8_Msk      /*!< APB4 clock divided by 8 */

+#define RCC_D3CFGR_D3PPRE_DIV16_Pos            (4U)

+#define RCC_D3CFGR_D3PPRE_DIV16_Msk            (0x7UL << RCC_D3CFGR_D3PPRE_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_D3CFGR_D3PPRE_DIV16                RCC_D3CFGR_D3PPRE_DIV16_Msk     /*!< APB4 clock divided by 16 */

+

+/********************  Bit definition for RCC_PLLCKSELR register  *************/

+

+#define RCC_PLLCKSELR_PLLSRC_Pos               (0U)

+#define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */

+#define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk

+

+#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)

+#define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */

+#define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_HSE_Pos           (1U)

+#define RCC_PLLCKSELR_PLLSRC_HSE_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */

+#define RCC_PLLCKSELR_PLLSRC_HSE               RCC_PLLCKSELR_PLLSRC_HSE_Msk    /*!< HSE source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_NONE_Pos          (0U)

+#define RCC_PLLCKSELR_PLLSRC_NONE_Msk          (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */

+#define RCC_PLLCKSELR_PLLSRC_NONE              RCC_PLLCKSELR_PLLSRC_NONE_Msk   /*!< No source clock selected  */

+

+#define RCC_PLLCKSELR_DIVM1_Pos                (4U)

+#define RCC_PLLCKSELR_DIVM1_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */

+#define RCC_PLLCKSELR_DIVM1                    RCC_PLLCKSELR_DIVM1_Msk

+#define RCC_PLLCKSELR_DIVM1_0                  (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */

+#define RCC_PLLCKSELR_DIVM1_1                  (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */

+#define RCC_PLLCKSELR_DIVM1_2                  (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */

+#define RCC_PLLCKSELR_DIVM1_3                  (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */

+#define RCC_PLLCKSELR_DIVM1_4                  (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */

+#define RCC_PLLCKSELR_DIVM1_5                  (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */

+

+#define RCC_PLLCKSELR_DIVM2_Pos                (12U)

+#define RCC_PLLCKSELR_DIVM2_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */

+#define RCC_PLLCKSELR_DIVM2                    RCC_PLLCKSELR_DIVM2_Msk

+#define RCC_PLLCKSELR_DIVM2_0                  (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */

+#define RCC_PLLCKSELR_DIVM2_1                  (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */

+#define RCC_PLLCKSELR_DIVM2_2                  (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */

+#define RCC_PLLCKSELR_DIVM2_3                  (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */

+#define RCC_PLLCKSELR_DIVM2_4                  (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */

+#define RCC_PLLCKSELR_DIVM2_5                  (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */

+

+#define RCC_PLLCKSELR_DIVM3_Pos                (20U)

+#define RCC_PLLCKSELR_DIVM3_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */

+#define RCC_PLLCKSELR_DIVM3                    RCC_PLLCKSELR_DIVM3_Msk

+#define RCC_PLLCKSELR_DIVM3_0                  (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */

+#define RCC_PLLCKSELR_DIVM3_1                  (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */

+#define RCC_PLLCKSELR_DIVM3_2                  (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */

+#define RCC_PLLCKSELR_DIVM3_3                  (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */

+#define RCC_PLLCKSELR_DIVM3_4                  (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */

+#define RCC_PLLCKSELR_DIVM3_5                  (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */

+

+/********************  Bit definition for RCC_PLLCFGR register  ***************/

+

+#define RCC_PLLCFGR_PLL1FRACEN_Pos             (0U)

+#define RCC_PLLCFGR_PLL1FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */

+#define RCC_PLLCFGR_PLL1FRACEN                 RCC_PLLCFGR_PLL1FRACEN_Msk

+#define RCC_PLLCFGR_PLL1VCOSEL_Pos             (1U)

+#define RCC_PLLCFGR_PLL1VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */

+#define RCC_PLLCFGR_PLL1VCOSEL                 RCC_PLLCFGR_PLL1VCOSEL_Msk

+#define RCC_PLLCFGR_PLL1RGE_Pos                (2U)

+#define RCC_PLLCFGR_PLL1RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */

+#define RCC_PLLCFGR_PLL1RGE                    RCC_PLLCFGR_PLL1RGE_Msk

+#define RCC_PLLCFGR_PLL1RGE_0                  (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL1RGE_1                  (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */

+#define RCC_PLLCFGR_PLL1RGE_2                  (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */

+#define RCC_PLLCFGR_PLL1RGE_3                  (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */

+

+#define RCC_PLLCFGR_PLL2FRACEN_Pos             (4U)

+#define RCC_PLLCFGR_PLL2FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */

+#define RCC_PLLCFGR_PLL2FRACEN                 RCC_PLLCFGR_PLL2FRACEN_Msk

+#define RCC_PLLCFGR_PLL2VCOSEL_Pos             (5U)

+#define RCC_PLLCFGR_PLL2VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */

+#define RCC_PLLCFGR_PLL2VCOSEL                 RCC_PLLCFGR_PLL2VCOSEL_Msk

+#define RCC_PLLCFGR_PLL2RGE_Pos                (6U)

+#define RCC_PLLCFGR_PLL2RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */

+#define RCC_PLLCFGR_PLL2RGE                    RCC_PLLCFGR_PLL2RGE_Msk

+#define RCC_PLLCFGR_PLL2RGE_0                  (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL2RGE_1                  (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */

+#define RCC_PLLCFGR_PLL2RGE_2                  (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */

+#define RCC_PLLCFGR_PLL2RGE_3                  (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */

+

+#define RCC_PLLCFGR_PLL3FRACEN_Pos             (8U)

+#define RCC_PLLCFGR_PLL3FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */

+#define RCC_PLLCFGR_PLL3FRACEN                 RCC_PLLCFGR_PLL3FRACEN_Msk

+#define RCC_PLLCFGR_PLL3VCOSEL_Pos             (9U)

+#define RCC_PLLCFGR_PLL3VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */

+#define RCC_PLLCFGR_PLL3VCOSEL                 RCC_PLLCFGR_PLL3VCOSEL_Msk

+#define RCC_PLLCFGR_PLL3RGE_Pos                (10U)

+#define RCC_PLLCFGR_PLL3RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */

+#define RCC_PLLCFGR_PLL3RGE                    RCC_PLLCFGR_PLL3RGE_Msk

+#define RCC_PLLCFGR_PLL3RGE_0                  (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL3RGE_1                  (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */

+#define RCC_PLLCFGR_PLL3RGE_2                  (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */

+#define RCC_PLLCFGR_PLL3RGE_3                  (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */

+

+#define RCC_PLLCFGR_DIVP1EN_Pos                (16U)

+#define RCC_PLLCFGR_DIVP1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */

+#define RCC_PLLCFGR_DIVP1EN                    RCC_PLLCFGR_DIVP1EN_Msk

+#define RCC_PLLCFGR_DIVQ1EN_Pos                (17U)

+#define RCC_PLLCFGR_DIVQ1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */

+#define RCC_PLLCFGR_DIVQ1EN                    RCC_PLLCFGR_DIVQ1EN_Msk

+#define RCC_PLLCFGR_DIVR1EN_Pos                (18U)

+#define RCC_PLLCFGR_DIVR1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */

+#define RCC_PLLCFGR_DIVR1EN                    RCC_PLLCFGR_DIVR1EN_Msk

+

+#define RCC_PLLCFGR_DIVP2EN_Pos                (19U)

+#define RCC_PLLCFGR_DIVP2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */

+#define RCC_PLLCFGR_DIVP2EN                    RCC_PLLCFGR_DIVP2EN_Msk

+#define RCC_PLLCFGR_DIVQ2EN_Pos                (20U)

+#define RCC_PLLCFGR_DIVQ2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */

+#define RCC_PLLCFGR_DIVQ2EN                    RCC_PLLCFGR_DIVQ2EN_Msk

+#define RCC_PLLCFGR_DIVR2EN_Pos                (21U)

+#define RCC_PLLCFGR_DIVR2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */

+#define RCC_PLLCFGR_DIVR2EN                    RCC_PLLCFGR_DIVR2EN_Msk

+

+#define RCC_PLLCFGR_DIVP3EN_Pos                (22U)

+#define RCC_PLLCFGR_DIVP3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */

+#define RCC_PLLCFGR_DIVP3EN                    RCC_PLLCFGR_DIVP3EN_Msk

+#define RCC_PLLCFGR_DIVQ3EN_Pos                (23U)

+#define RCC_PLLCFGR_DIVQ3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */

+#define RCC_PLLCFGR_DIVQ3EN                    RCC_PLLCFGR_DIVQ3EN_Msk

+#define RCC_PLLCFGR_DIVR3EN_Pos                (24U)

+#define RCC_PLLCFGR_DIVR3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */

+#define RCC_PLLCFGR_DIVR3EN                    RCC_PLLCFGR_DIVR3EN_Msk

+

+

+/********************  Bit definition for RCC_PLL1DIVR register  ***************/

+#define RCC_PLL1DIVR_N1_Pos                    (0U)

+#define RCC_PLL1DIVR_N1_Msk                    (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */

+#define RCC_PLL1DIVR_N1                        RCC_PLL1DIVR_N1_Msk

+#define RCC_PLL1DIVR_P1_Pos                    (9U)

+#define RCC_PLL1DIVR_P1_Msk                    (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL1DIVR_P1                        RCC_PLL1DIVR_P1_Msk

+#define RCC_PLL1DIVR_Q1_Pos                    (16U)

+#define RCC_PLL1DIVR_Q1_Msk                    (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */

+#define RCC_PLL1DIVR_Q1                        RCC_PLL1DIVR_Q1_Msk

+#define RCC_PLL1DIVR_R1_Pos                    (24U)

+#define RCC_PLL1DIVR_R1_Msk                    (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */

+#define RCC_PLL1DIVR_R1                        RCC_PLL1DIVR_R1_Msk

+

+/********************  Bit definition for RCC_PLL1FRACR register  ***************/

+#define RCC_PLL1FRACR_FRACN1_Pos               (3U)

+#define RCC_PLL1FRACR_FRACN1_Msk               (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL1FRACR_FRACN1                   RCC_PLL1FRACR_FRACN1_Msk

+

+/********************  Bit definition for RCC_PLL2DIVR register  ***************/

+#define RCC_PLL2DIVR_N2_Pos                    (0U)

+#define RCC_PLL2DIVR_N2_Msk                    (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */

+#define RCC_PLL2DIVR_N2                        RCC_PLL2DIVR_N2_Msk

+#define RCC_PLL2DIVR_P2_Pos                    (9U)

+#define RCC_PLL2DIVR_P2_Msk                    (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL2DIVR_P2                        RCC_PLL2DIVR_P2_Msk

+#define RCC_PLL2DIVR_Q2_Pos                    (16U)

+#define RCC_PLL2DIVR_Q2_Msk                    (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */

+#define RCC_PLL2DIVR_Q2                        RCC_PLL2DIVR_Q2_Msk

+#define RCC_PLL2DIVR_R2_Pos                    (24U)

+#define RCC_PLL2DIVR_R2_Msk                    (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */

+#define RCC_PLL2DIVR_R2                        RCC_PLL2DIVR_R2_Msk

+

+/********************  Bit definition for RCC_PLL2FRACR register  ***************/

+#define RCC_PLL2FRACR_FRACN2_Pos               (3U)

+#define RCC_PLL2FRACR_FRACN2_Msk               (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL2FRACR_FRACN2                   RCC_PLL2FRACR_FRACN2_Msk

+

+/********************  Bit definition for RCC_PLL3DIVR register  ***************/

+#define RCC_PLL3DIVR_N3_Pos                    (0U)

+#define RCC_PLL3DIVR_N3_Msk                    (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */

+#define RCC_PLL3DIVR_N3                        RCC_PLL3DIVR_N3_Msk

+#define RCC_PLL3DIVR_P3_Pos                    (9U)

+#define RCC_PLL3DIVR_P3_Msk                    (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL3DIVR_P3                        RCC_PLL3DIVR_P3_Msk

+#define RCC_PLL3DIVR_Q3_Pos                    (16U)

+#define RCC_PLL3DIVR_Q3_Msk                    (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */

+#define RCC_PLL3DIVR_Q3                        RCC_PLL3DIVR_Q3_Msk

+#define RCC_PLL3DIVR_R3_Pos                    (24U)

+#define RCC_PLL3DIVR_R3_Msk                    (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */

+#define RCC_PLL3DIVR_R3                        RCC_PLL3DIVR_R3_Msk

+

+/********************  Bit definition for RCC_PLL3FRACR register  ***************/

+#define RCC_PLL3FRACR_FRACN3_Pos               (3U)

+#define RCC_PLL3FRACR_FRACN3_Msk               (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL3FRACR_FRACN3                   RCC_PLL3FRACR_FRACN3_Msk

+

+/********************  Bit definition for RCC_D1CCIPR register  ***************/

+#define RCC_D1CCIPR_FMCSEL_Pos                 (0U)

+#define RCC_D1CCIPR_FMCSEL_Msk                 (0x3UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000003 */

+#define RCC_D1CCIPR_FMCSEL                     RCC_D1CCIPR_FMCSEL_Msk

+#define RCC_D1CCIPR_FMCSEL_0                   (0x1UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000001 */

+#define RCC_D1CCIPR_FMCSEL_1                   (0x2UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000002 */

+#define RCC_D1CCIPR_QSPISEL_Pos                (4U)

+#define RCC_D1CCIPR_QSPISEL_Msk                (0x3UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000030 */

+#define RCC_D1CCIPR_QSPISEL                    RCC_D1CCIPR_QSPISEL_Msk

+#define RCC_D1CCIPR_QSPISEL_0                  (0x1UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000010 */

+#define RCC_D1CCIPR_QSPISEL_1                  (0x2UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000020 */

+#define RCC_D1CCIPR_DSISEL_Pos                 (8U)

+#define RCC_D1CCIPR_DSISEL_Msk                 (0x1UL << RCC_D1CCIPR_DSISEL_Pos) /*!< 0x00000100 */

+#define RCC_D1CCIPR_DSISEL                     RCC_D1CCIPR_DSISEL_Msk

+#define RCC_D1CCIPR_SDMMCSEL_Pos               (16U)

+#define RCC_D1CCIPR_SDMMCSEL_Msk               (0x1UL << RCC_D1CCIPR_SDMMCSEL_Pos) /*!< 0x00010000 */

+#define RCC_D1CCIPR_SDMMCSEL                   RCC_D1CCIPR_SDMMCSEL_Msk

+#define RCC_D1CCIPR_CKPERSEL_Pos               (28U)

+#define RCC_D1CCIPR_CKPERSEL_Msk               (0x3UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x30000000 */

+#define RCC_D1CCIPR_CKPERSEL                   RCC_D1CCIPR_CKPERSEL_Msk

+#define RCC_D1CCIPR_CKPERSEL_0                 (0x1UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x10000000 */

+#define RCC_D1CCIPR_CKPERSEL_1                 (0x2UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x20000000 */

+

+/********************  Bit definition for RCC_D2CCIP1R register  ***************/

+#define RCC_D2CCIP1R_SAI1SEL_Pos               (0U)

+#define RCC_D2CCIP1R_SAI1SEL_Msk               (0x7UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000007 */

+#define RCC_D2CCIP1R_SAI1SEL                   RCC_D2CCIP1R_SAI1SEL_Msk

+#define RCC_D2CCIP1R_SAI1SEL_0                 (0x1UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000001 */

+#define RCC_D2CCIP1R_SAI1SEL_1                 (0x2UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000002 */

+#define RCC_D2CCIP1R_SAI1SEL_2                 (0x4UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000004 */

+

+#define RCC_D2CCIP1R_SAI23SEL_Pos              (6U)

+#define RCC_D2CCIP1R_SAI23SEL_Msk              (0x7UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x000001C0 */

+#define RCC_D2CCIP1R_SAI23SEL                  RCC_D2CCIP1R_SAI23SEL_Msk

+#define RCC_D2CCIP1R_SAI23SEL_0                (0x1UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000040 */

+#define RCC_D2CCIP1R_SAI23SEL_1                (0x2UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000080 */

+#define RCC_D2CCIP1R_SAI23SEL_2                (0x4UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000100 */

+

+#define RCC_D2CCIP1R_SPI123SEL_Pos             (12U)

+#define RCC_D2CCIP1R_SPI123SEL_Msk             (0x7UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */

+#define RCC_D2CCIP1R_SPI123SEL                 RCC_D2CCIP1R_SPI123SEL_Msk

+#define RCC_D2CCIP1R_SPI123SEL_0               (0x1UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */

+#define RCC_D2CCIP1R_SPI123SEL_1               (0x2UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */

+#define RCC_D2CCIP1R_SPI123SEL_2               (0x4UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */

+

+#define RCC_D2CCIP1R_SPI45SEL_Pos              (16U)

+#define RCC_D2CCIP1R_SPI45SEL_Msk              (0x7UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00070000 */

+#define RCC_D2CCIP1R_SPI45SEL                  RCC_D2CCIP1R_SPI45SEL_Msk

+#define RCC_D2CCIP1R_SPI45SEL_0                (0x1UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00010000 */

+#define RCC_D2CCIP1R_SPI45SEL_1                (0x2UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00020000 */

+#define RCC_D2CCIP1R_SPI45SEL_2                (0x4UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00040000 */

+

+#define RCC_D2CCIP1R_SPDIFSEL_Pos              (20U)

+#define RCC_D2CCIP1R_SPDIFSEL_Msk              (0x3UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00300000 */

+#define RCC_D2CCIP1R_SPDIFSEL                  RCC_D2CCIP1R_SPDIFSEL_Msk

+#define RCC_D2CCIP1R_SPDIFSEL_0                (0x1UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00100000 */

+#define RCC_D2CCIP1R_SPDIFSEL_1                (0x2UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00200000 */

+

+#define RCC_D2CCIP1R_DFSDM1SEL_Pos             (24U)

+#define RCC_D2CCIP1R_DFSDM1SEL_Msk             (0x1UL << RCC_D2CCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */

+#define RCC_D2CCIP1R_DFSDM1SEL                 RCC_D2CCIP1R_DFSDM1SEL_Msk

+

+#define RCC_D2CCIP1R_FDCANSEL_Pos              (28U)

+#define RCC_D2CCIP1R_FDCANSEL_Msk              (0x3UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x30000000 */

+#define RCC_D2CCIP1R_FDCANSEL                  RCC_D2CCIP1R_FDCANSEL_Msk

+#define RCC_D2CCIP1R_FDCANSEL_0                (0x1UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x10000000 */

+#define RCC_D2CCIP1R_FDCANSEL_1                (0x2UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x20000000 */

+

+#define RCC_D2CCIP1R_SWPSEL_Pos                (31U)

+#define RCC_D2CCIP1R_SWPSEL_Msk                (0x1UL << RCC_D2CCIP1R_SWPSEL_Pos) /*!< 0x80000000 */

+#define RCC_D2CCIP1R_SWPSEL                    RCC_D2CCIP1R_SWPSEL_Msk

+

+/********************  Bit definition for RCC_D2CCIP2R register  ***************/

+#define RCC_D2CCIP2R_USART16SEL_Pos            (3U)

+#define RCC_D2CCIP2R_USART16SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000038 */

+#define RCC_D2CCIP2R_USART16SEL                RCC_D2CCIP2R_USART16SEL_Msk

+#define RCC_D2CCIP2R_USART16SEL_0              (0x1UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000008 */

+#define RCC_D2CCIP2R_USART16SEL_1              (0x2UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000010 */

+#define RCC_D2CCIP2R_USART16SEL_2              (0x4UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000020 */

+

+#define RCC_D2CCIP2R_USART28SEL_Pos            (0U)

+#define RCC_D2CCIP2R_USART28SEL_Msk            (0x7UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000007 */

+#define RCC_D2CCIP2R_USART28SEL                RCC_D2CCIP2R_USART28SEL_Msk

+#define RCC_D2CCIP2R_USART28SEL_0              (0x1UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000001 */

+#define RCC_D2CCIP2R_USART28SEL_1              (0x2UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000002 */

+#define RCC_D2CCIP2R_USART28SEL_2              (0x4UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000004 */

+

+#define RCC_D2CCIP2R_RNGSEL_Pos                (8U)

+#define RCC_D2CCIP2R_RNGSEL_Msk                (0x3UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000300 */

+#define RCC_D2CCIP2R_RNGSEL                    RCC_D2CCIP2R_RNGSEL_Msk

+#define RCC_D2CCIP2R_RNGSEL_0                  (0x1UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000100 */

+#define RCC_D2CCIP2R_RNGSEL_1                  (0x2UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000200 */

+

+#define RCC_D2CCIP2R_I2C123SEL_Pos             (12U)

+#define RCC_D2CCIP2R_I2C123SEL_Msk             (0x3UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00003000 */

+#define RCC_D2CCIP2R_I2C123SEL                 RCC_D2CCIP2R_I2C123SEL_Msk

+#define RCC_D2CCIP2R_I2C123SEL_0               (0x1UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00001000 */

+#define RCC_D2CCIP2R_I2C123SEL_1               (0x2UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00002000 */

+

+#define RCC_D2CCIP2R_USBSEL_Pos                (20U)

+#define RCC_D2CCIP2R_USBSEL_Msk                (0x3UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00300000 */

+#define RCC_D2CCIP2R_USBSEL                    RCC_D2CCIP2R_USBSEL_Msk

+#define RCC_D2CCIP2R_USBSEL_0                  (0x1UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00100000 */

+#define RCC_D2CCIP2R_USBSEL_1                  (0x2UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00200000 */

+

+#define RCC_D2CCIP2R_CECSEL_Pos                (22U)

+#define RCC_D2CCIP2R_CECSEL_Msk                (0x3UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00C00000 */

+#define RCC_D2CCIP2R_CECSEL                    RCC_D2CCIP2R_CECSEL_Msk

+#define RCC_D2CCIP2R_CECSEL_0                  (0x1UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00400000 */

+#define RCC_D2CCIP2R_CECSEL_1                  (0x2UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00800000 */

+

+#define RCC_D2CCIP2R_LPTIM1SEL_Pos             (28U)

+#define RCC_D2CCIP2R_LPTIM1SEL_Msk             (0x7UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x70000000 */

+#define RCC_D2CCIP2R_LPTIM1SEL                 RCC_D2CCIP2R_LPTIM1SEL_Msk

+#define RCC_D2CCIP2R_LPTIM1SEL_0               (0x1UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x10000000 */

+#define RCC_D2CCIP2R_LPTIM1SEL_1               (0x2UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x20000000 */

+#define RCC_D2CCIP2R_LPTIM1SEL_2               (0x4UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition for RCC_D3CCIPR register  ***************/

+#define RCC_D3CCIPR_LPUART1SEL_Pos             (0U)

+#define RCC_D3CCIPR_LPUART1SEL_Msk             (0x7UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000007 */

+#define RCC_D3CCIPR_LPUART1SEL                 RCC_D3CCIPR_LPUART1SEL_Msk

+#define RCC_D3CCIPR_LPUART1SEL_0               (0x1UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000001 */

+#define RCC_D3CCIPR_LPUART1SEL_1               (0x2UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000002 */

+#define RCC_D3CCIPR_LPUART1SEL_2               (0x4UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000004 */

+

+#define RCC_D3CCIPR_I2C4SEL_Pos                (8U)

+#define RCC_D3CCIPR_I2C4SEL_Msk                (0x3UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000300 */

+#define RCC_D3CCIPR_I2C4SEL                    RCC_D3CCIPR_I2C4SEL_Msk

+#define RCC_D3CCIPR_I2C4SEL_0                  (0x1UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000100 */

+#define RCC_D3CCIPR_I2C4SEL_1                  (0x2UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000200 */

+

+#define RCC_D3CCIPR_LPTIM2SEL_Pos              (10U)

+#define RCC_D3CCIPR_LPTIM2SEL_Msk              (0x7UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001C00 */

+#define RCC_D3CCIPR_LPTIM2SEL                  RCC_D3CCIPR_LPTIM2SEL_Msk

+#define RCC_D3CCIPR_LPTIM2SEL_0                (0x1UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000400 */

+#define RCC_D3CCIPR_LPTIM2SEL_1                (0x2UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000800 */

+#define RCC_D3CCIPR_LPTIM2SEL_2                (0x4UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001000 */

+

+#define RCC_D3CCIPR_LPTIM345SEL_Pos            (13U)

+#define RCC_D3CCIPR_LPTIM345SEL_Msk            (0x7UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x0000E000 */

+#define RCC_D3CCIPR_LPTIM345SEL                RCC_D3CCIPR_LPTIM345SEL_Msk

+#define RCC_D3CCIPR_LPTIM345SEL_0              (0x1UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00002000 */

+#define RCC_D3CCIPR_LPTIM345SEL_1              (0x2UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00004000 */

+#define RCC_D3CCIPR_LPTIM345SEL_2              (0x4UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00008000 */

+

+#define RCC_D3CCIPR_SAI4ASEL_Pos               (21U)

+#define RCC_D3CCIPR_SAI4ASEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00E00000 */

+#define RCC_D3CCIPR_SAI4ASEL                   RCC_D3CCIPR_SAI4ASEL_Msk

+#define RCC_D3CCIPR_SAI4ASEL_0                 (0x1UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00200000 */

+#define RCC_D3CCIPR_SAI4ASEL_1                 (0x2UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00400000 */

+#define RCC_D3CCIPR_SAI4ASEL_2                 (0x4UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00800000 */

+

+#define RCC_D3CCIPR_SAI4BSEL_Pos               (24U)

+#define RCC_D3CCIPR_SAI4BSEL_Msk               (0x7UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x07000000 */

+#define RCC_D3CCIPR_SAI4BSEL                   RCC_D3CCIPR_SAI4BSEL_Msk

+#define RCC_D3CCIPR_SAI4BSEL_0                 (0x1UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x01000000 */

+#define RCC_D3CCIPR_SAI4BSEL_1                 (0x2UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x02000000 */

+#define RCC_D3CCIPR_SAI4BSEL_2                 (0x4UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x04000000 */

+

+#define RCC_D3CCIPR_ADCSEL_Pos                 (16U)

+#define RCC_D3CCIPR_ADCSEL_Msk                 (0x3UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00030000 */

+#define RCC_D3CCIPR_ADCSEL                     RCC_D3CCIPR_ADCSEL_Msk

+#define RCC_D3CCIPR_ADCSEL_0                   (0x1UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00010000 */

+#define RCC_D3CCIPR_ADCSEL_1                   (0x2UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00020000 */

+

+#define RCC_D3CCIPR_SPI6SEL_Pos                (28U)

+#define RCC_D3CCIPR_SPI6SEL_Msk                (0x7UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x70000000 */

+#define RCC_D3CCIPR_SPI6SEL                    RCC_D3CCIPR_SPI6SEL_Msk

+#define RCC_D3CCIPR_SPI6SEL_0                  (0x1UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x10000000 */

+#define RCC_D3CCIPR_SPI6SEL_1                  (0x2UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x20000000 */

+#define RCC_D3CCIPR_SPI6SEL_2                  (0x4UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x40000000 */

+/********************  Bit definition for RCC_CIER register  ******************/

+#define RCC_CIER_LSIRDYIE_Pos                  (0U)

+#define RCC_CIER_LSIRDYIE_Msk                  (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */

+#define RCC_CIER_LSIRDYIE                      RCC_CIER_LSIRDYIE_Msk

+#define RCC_CIER_LSERDYIE_Pos                  (1U)

+#define RCC_CIER_LSERDYIE_Msk                  (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */

+#define RCC_CIER_LSERDYIE                      RCC_CIER_LSERDYIE_Msk

+#define RCC_CIER_HSIRDYIE_Pos                  (2U)

+#define RCC_CIER_HSIRDYIE_Msk                  (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */

+#define RCC_CIER_HSIRDYIE                      RCC_CIER_HSIRDYIE_Msk

+#define RCC_CIER_HSERDYIE_Pos                  (3U)

+#define RCC_CIER_HSERDYIE_Msk                  (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */

+#define RCC_CIER_HSERDYIE                      RCC_CIER_HSERDYIE_Msk

+#define RCC_CIER_CSIRDYIE_Pos                  (4U)

+#define RCC_CIER_CSIRDYIE_Msk                  (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */

+#define RCC_CIER_CSIRDYIE                      RCC_CIER_CSIRDYIE_Msk

+#define RCC_CIER_HSI48RDYIE_Pos                (5U)

+#define RCC_CIER_HSI48RDYIE_Msk                (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */

+#define RCC_CIER_HSI48RDYIE                    RCC_CIER_HSI48RDYIE_Msk

+#define RCC_CIER_PLL1RDYIE_Pos                 (6U)

+#define RCC_CIER_PLL1RDYIE_Msk                 (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */

+#define RCC_CIER_PLL1RDYIE                     RCC_CIER_PLL1RDYIE_Msk

+#define RCC_CIER_PLL2RDYIE_Pos                 (7U)

+#define RCC_CIER_PLL2RDYIE_Msk                 (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */

+#define RCC_CIER_PLL2RDYIE                     RCC_CIER_PLL2RDYIE_Msk

+#define RCC_CIER_PLL3RDYIE_Pos                 (8U)

+#define RCC_CIER_PLL3RDYIE_Msk                 (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */

+#define RCC_CIER_PLL3RDYIE                     RCC_CIER_PLL3RDYIE_Msk

+#define RCC_CIER_LSECSSIE_Pos                  (9U)

+#define RCC_CIER_LSECSSIE_Msk                  (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */

+#define RCC_CIER_LSECSSIE                      RCC_CIER_LSECSSIE_Msk

+

+/********************  Bit definition for RCC_CIFR register  ******************/

+#define RCC_CIFR_LSIRDYF_Pos                   (0U)

+#define RCC_CIFR_LSIRDYF_Msk                   (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */

+#define RCC_CIFR_LSIRDYF                       RCC_CIFR_LSIRDYF_Msk

+#define RCC_CIFR_LSERDYF_Pos                   (1U)

+#define RCC_CIFR_LSERDYF_Msk                   (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */

+#define RCC_CIFR_LSERDYF                       RCC_CIFR_LSERDYF_Msk

+#define RCC_CIFR_HSIRDYF_Pos                   (2U)

+#define RCC_CIFR_HSIRDYF_Msk                   (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */

+#define RCC_CIFR_HSIRDYF                       RCC_CIFR_HSIRDYF_Msk

+#define RCC_CIFR_HSERDYF_Pos                   (3U)

+#define RCC_CIFR_HSERDYF_Msk                   (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */

+#define RCC_CIFR_HSERDYF                       RCC_CIFR_HSERDYF_Msk

+#define RCC_CIFR_CSIRDYF_Pos                   (4U)

+#define RCC_CIFR_CSIRDYF_Msk                   (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */

+#define RCC_CIFR_CSIRDYF                       RCC_CIFR_CSIRDYF_Msk

+#define RCC_CIFR_HSI48RDYF_Pos                 (5U)

+#define RCC_CIFR_HSI48RDYF_Msk                 (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */

+#define RCC_CIFR_HSI48RDYF                     RCC_CIFR_HSI48RDYF_Msk

+#define RCC_CIFR_PLLRDYF_Pos                   (6U)

+#define RCC_CIFR_PLLRDYF_Msk                   (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */

+#define RCC_CIFR_PLLRDYF                       RCC_CIFR_PLLRDYF_Msk

+#define RCC_CIFR_PLL2RDYF_Pos                  (7U)

+#define RCC_CIFR_PLL2RDYF_Msk                  (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */

+#define RCC_CIFR_PLL2RDYF                      RCC_CIFR_PLL2RDYF_Msk

+#define RCC_CIFR_PLL3RDYF_Pos                  (8U)

+#define RCC_CIFR_PLL3RDYF_Msk                  (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */

+#define RCC_CIFR_PLL3RDYF                      RCC_CIFR_PLL3RDYF_Msk

+#define RCC_CIFR_LSECSSF_Pos                   (9U)

+#define RCC_CIFR_LSECSSF_Msk                   (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */

+#define RCC_CIFR_LSECSSF                       RCC_CIFR_LSECSSF_Msk

+#define RCC_CIFR_HSECSSF_Pos                   (10U)

+#define RCC_CIFR_HSECSSF_Msk                   (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */

+#define RCC_CIFR_HSECSSF                       RCC_CIFR_HSECSSF_Msk

+

+/********************  Bit definition for RCC_CICR register  ******************/

+#define RCC_CICR_LSIRDYC_Pos                   (0U)

+#define RCC_CICR_LSIRDYC_Msk                   (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */

+#define RCC_CICR_LSIRDYC                       RCC_CICR_LSIRDYC_Msk

+#define RCC_CICR_LSERDYC_Pos                   (1U)

+#define RCC_CICR_LSERDYC_Msk                   (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */

+#define RCC_CICR_LSERDYC                       RCC_CICR_LSERDYC_Msk

+#define RCC_CICR_HSIRDYC_Pos                   (2U)

+#define RCC_CICR_HSIRDYC_Msk                   (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */

+#define RCC_CICR_HSIRDYC                       RCC_CICR_HSIRDYC_Msk

+#define RCC_CICR_HSERDYC_Pos                   (3U)

+#define RCC_CICR_HSERDYC_Msk                   (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */

+#define RCC_CICR_HSERDYC                       RCC_CICR_HSERDYC_Msk

+#define RCC_CICR_CSIRDYC_Pos                   (4U)

+#define RCC_CICR_CSIRDYC_Msk                   (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */

+#define RCC_CICR_CSIRDYC                       RCC_CICR_CSIRDYC_Msk

+#define RCC_CICR_HSI48RDYC_Pos                 (5U)

+#define RCC_CICR_HSI48RDYC_Msk                 (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */

+#define RCC_CICR_HSI48RDYC                     RCC_CICR_HSI48RDYC_Msk

+#define RCC_CICR_PLLRDYC_Pos                   (6U)

+#define RCC_CICR_PLLRDYC_Msk                   (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */

+#define RCC_CICR_PLLRDYC                       RCC_CICR_PLLRDYC_Msk

+#define RCC_CICR_PLL2RDYC_Pos                  (7U)

+#define RCC_CICR_PLL2RDYC_Msk                  (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */

+#define RCC_CICR_PLL2RDYC                      RCC_CICR_PLL2RDYC_Msk

+#define RCC_CICR_PLL3RDYC_Pos                  (8U)

+#define RCC_CICR_PLL3RDYC_Msk                  (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */

+#define RCC_CICR_PLL3RDYC                      RCC_CICR_PLL3RDYC_Msk

+#define RCC_CICR_LSECSSC_Pos                   (9U)

+#define RCC_CICR_LSECSSC_Msk                   (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */

+#define RCC_CICR_LSECSSC                       RCC_CICR_LSECSSC_Msk

+#define RCC_CICR_HSECSSC_Pos                   (10U)

+#define RCC_CICR_HSECSSC_Msk                   (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */

+#define RCC_CICR_HSECSSC                       RCC_CICR_HSECSSC_Msk

+

+/********************  Bit definition for RCC_BDCR register  ******************/

+#define RCC_BDCR_LSEON_Pos                     (0U)

+#define RCC_BDCR_LSEON_Msk                     (0x1UL << RCC_BDCR_LSEON_Pos)   /*!< 0x00000001 */

+#define RCC_BDCR_LSEON                         RCC_BDCR_LSEON_Msk

+#define RCC_BDCR_LSERDY_Pos                    (1U)

+#define RCC_BDCR_LSERDY_Msk                    (0x1UL << RCC_BDCR_LSERDY_Pos)  /*!< 0x00000002 */

+#define RCC_BDCR_LSERDY                        RCC_BDCR_LSERDY_Msk

+#define RCC_BDCR_LSEBYP_Pos                    (2U)

+#define RCC_BDCR_LSEBYP_Msk                    (0x1UL << RCC_BDCR_LSEBYP_Pos)  /*!< 0x00000004 */

+#define RCC_BDCR_LSEBYP                        RCC_BDCR_LSEBYP_Msk

+

+#define RCC_BDCR_LSEDRV_Pos                    (3U)

+#define RCC_BDCR_LSEDRV_Msk                    (0x3UL << RCC_BDCR_LSEDRV_Pos)  /*!< 0x00000018 */

+#define RCC_BDCR_LSEDRV                        RCC_BDCR_LSEDRV_Msk

+#define RCC_BDCR_LSEDRV_0                      (0x1UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000008 */

+#define RCC_BDCR_LSEDRV_1                      (0x2UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000010 */

+

+#define RCC_BDCR_LSECSSON_Pos                  (5U)

+#define RCC_BDCR_LSECSSON_Msk                  (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */

+#define RCC_BDCR_LSECSSON                      RCC_BDCR_LSECSSON_Msk

+#define RCC_BDCR_LSECSSD_Pos                   (6U)

+#define RCC_BDCR_LSECSSD_Msk                   (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */

+#define RCC_BDCR_LSECSSD                       RCC_BDCR_LSECSSD_Msk

+

+#define RCC_BDCR_RTCSEL_Pos                    (8U)

+#define RCC_BDCR_RTCSEL_Msk                    (0x3UL << RCC_BDCR_RTCSEL_Pos)  /*!< 0x00000300 */

+#define RCC_BDCR_RTCSEL                        RCC_BDCR_RTCSEL_Msk

+#define RCC_BDCR_RTCSEL_0                      (0x1UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000100 */

+#define RCC_BDCR_RTCSEL_1                      (0x2UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000200 */

+

+#define RCC_BDCR_RTCEN_Pos                     (15U)

+#define RCC_BDCR_RTCEN_Msk                     (0x1UL << RCC_BDCR_RTCEN_Pos)   /*!< 0x00008000 */

+#define RCC_BDCR_RTCEN                         RCC_BDCR_RTCEN_Msk

+#define RCC_BDCR_BDRST_Pos                     (16U)

+#define RCC_BDCR_BDRST_Msk                     (0x1UL << RCC_BDCR_BDRST_Pos)   /*!< 0x00010000 */

+#define RCC_BDCR_BDRST                         RCC_BDCR_BDRST_Msk

+/********************  Bit definition for RCC_CSR register  *******************/

+#define RCC_CSR_LSION_Pos                      (0U)

+#define RCC_CSR_LSION_Msk                      (0x1UL << RCC_CSR_LSION_Pos)    /*!< 0x00000001 */

+#define RCC_CSR_LSION                          RCC_CSR_LSION_Msk

+#define RCC_CSR_LSIRDY_Pos                     (1U)

+#define RCC_CSR_LSIRDY_Msk                     (0x1UL << RCC_CSR_LSIRDY_Pos)   /*!< 0x00000002 */

+#define RCC_CSR_LSIRDY                         RCC_CSR_LSIRDY_Msk

+

+

+/********************  Bit definition for RCC_AHB3ENR register  **************/

+#define RCC_AHB3ENR_MDMAEN_Pos                 (0U)

+#define RCC_AHB3ENR_MDMAEN_Msk                 (0x1UL << RCC_AHB3ENR_MDMAEN_Pos)       /*!< 0x00000001 */

+#define RCC_AHB3ENR_MDMAEN                     RCC_AHB3ENR_MDMAEN_Msk

+#define RCC_AHB3ENR_DMA2DEN_Pos                (4U)

+#define RCC_AHB3ENR_DMA2DEN_Msk                (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos)      /*!< 0x00000010 */

+#define RCC_AHB3ENR_DMA2DEN                    RCC_AHB3ENR_DMA2DEN_Msk

+#define RCC_AHB3ENR_JPGDECEN_Pos               (5U)

+#define RCC_AHB3ENR_JPGDECEN_Msk               (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos)     /*!< 0x00000020 */

+#define RCC_AHB3ENR_JPGDECEN                   RCC_AHB3ENR_JPGDECEN_Msk

+#define RCC_AHB3ENR_FMCEN_Pos                  (12U)

+#define RCC_AHB3ENR_FMCEN_Msk                  (0x1UL << RCC_AHB3ENR_FMCEN_Pos)        /*!< 0x00001000 */

+#define RCC_AHB3ENR_FMCEN                      RCC_AHB3ENR_FMCEN_Msk

+#define RCC_AHB3ENR_QSPIEN_Pos                 (14U)

+#define RCC_AHB3ENR_QSPIEN_Msk                 (0x1UL << RCC_AHB3ENR_QSPIEN_Pos)       /*!< 0x00004000 */

+#define RCC_AHB3ENR_QSPIEN                     RCC_AHB3ENR_QSPIEN_Msk

+#define RCC_AHB3ENR_SDMMC1EN_Pos               (16U)

+#define RCC_AHB3ENR_SDMMC1EN_Msk               (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos)     /*!< 0x00010000 */

+#define RCC_AHB3ENR_SDMMC1EN                   RCC_AHB3ENR_SDMMC1EN_Msk

+#define RCC_AHB3ENR_FLASHEN_Pos                (8U)

+#define RCC_AHB3ENR_FLASHEN_Msk                (0x1UL << RCC_AHB3ENR_FLASHEN_Pos)      /*!< 0x00000100 */

+#define RCC_AHB3ENR_FLASHEN                    RCC_AHB3ENR_FLASHEN_Msk

+#define RCC_AHB3ENR_DTCM1EN_Pos                (28U)

+#define RCC_AHB3ENR_DTCM1EN_Msk                (0x1UL << RCC_AHB3ENR_DTCM1EN_Pos)      /*!< 0x10000000 */

+#define RCC_AHB3ENR_DTCM1EN                    RCC_AHB3ENR_DTCM1EN_Msk

+#define RCC_AHB3ENR_DTCM2EN_Pos                (29U)

+#define RCC_AHB3ENR_DTCM2EN_Msk                (0x1UL << RCC_AHB3ENR_DTCM2EN_Pos)      /*!< 0x20000000 */

+#define RCC_AHB3ENR_DTCM2EN                    RCC_AHB3ENR_DTCM2EN_Msk

+#define RCC_AHB3ENR_ITCMEN_Pos                 (30U)

+#define RCC_AHB3ENR_ITCMEN_Msk                 (0x1UL << RCC_AHB3ENR_ITCMEN_Pos)       /*!< 0x40000000 */

+#define RCC_AHB3ENR_ITCMEN                     RCC_AHB3ENR_ITCMEN_Msk

+#define RCC_AHB3ENR_AXISRAMEN_Pos              (31U)

+#define RCC_AHB3ENR_AXISRAMEN_Msk              (0x1UL << RCC_AHB3ENR_AXISRAMEN_Pos)    /*!< 0x80000000 */

+#define RCC_AHB3ENR_AXISRAMEN                  RCC_AHB3ENR_AXISRAMEN_Msk

+

+/* Legacy define */

+#define RCC_AHB3ENR_D1SRAM1EN_Pos              RCC_AHB3ENR_AXISRAMEN_Pos

+#define RCC_AHB3ENR_D1SRAM1EN_Msk              RCC_AHB3ENR_AXISRAMEN_Msk

+#define RCC_AHB3ENR_D1SRAM1EN                  RCC_AHB3ENR_AXISRAMEN

+

+/********************  Bit definition for RCC_AHB1ENR register  ***************/

+#define RCC_AHB1ENR_DMA1EN_Pos                 (0U)

+#define RCC_AHB1ENR_DMA1EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)          /*!< 0x00000001 */

+#define RCC_AHB1ENR_DMA1EN                     RCC_AHB1ENR_DMA1EN_Msk

+#define RCC_AHB1ENR_DMA2EN_Pos                 (1U)

+#define RCC_AHB1ENR_DMA2EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)          /*!< 0x00000002 */

+#define RCC_AHB1ENR_DMA2EN                     RCC_AHB1ENR_DMA2EN_Msk

+#define RCC_AHB1ENR_ADC12EN_Pos                (5U)

+#define RCC_AHB1ENR_ADC12EN_Msk                (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)         /*!< 0x00000020 */

+#define RCC_AHB1ENR_ADC12EN                    RCC_AHB1ENR_ADC12EN_Msk

+#define RCC_AHB1ENR_ARTEN_Pos                  (14U)

+#define RCC_AHB1ENR_ARTEN_Msk                  (0x1UL << RCC_AHB1ENR_ARTEN_Pos)           /*!< 0x00004000 */

+#define RCC_AHB1ENR_ARTEN                      RCC_AHB1ENR_ARTEN_Msk

+#define RCC_AHB1ENR_ETH1MACEN_Pos              (15U)

+#define RCC_AHB1ENR_ETH1MACEN_Msk              (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos)       /*!< 0x00008000 */

+#define RCC_AHB1ENR_ETH1MACEN                  RCC_AHB1ENR_ETH1MACEN_Msk

+#define RCC_AHB1ENR_ETH1TXEN_Pos               (16U)

+#define RCC_AHB1ENR_ETH1TXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos)        /*!< 0x00010000 */

+#define RCC_AHB1ENR_ETH1TXEN                   RCC_AHB1ENR_ETH1TXEN_Msk

+#define RCC_AHB1ENR_ETH1RXEN_Pos               (17U)

+#define RCC_AHB1ENR_ETH1RXEN_Msk               (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos)        /*!< 0x00020000 */

+#define RCC_AHB1ENR_ETH1RXEN                   RCC_AHB1ENR_ETH1RXEN_Msk

+#define RCC_AHB1ENR_USB1OTGHSEN_Pos            (25U)

+#define RCC_AHB1ENR_USB1OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos)     /*!< 0x02000000 */

+#define RCC_AHB1ENR_USB1OTGHSEN                RCC_AHB1ENR_USB1OTGHSEN_Msk

+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos        (26U)

+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */

+#define RCC_AHB1ENR_USB1OTGHSULPIEN            RCC_AHB1ENR_USB1OTGHSULPIEN_Msk

+#define RCC_AHB1ENR_USB2OTGFSEN_Pos            (27U)

+#define RCC_AHB1ENR_USB2OTGFSEN_Msk            (0x1UL << RCC_AHB1ENR_USB2OTGFSEN_Pos)     /*!< 0x08000000 */

+#define RCC_AHB1ENR_USB2OTGFSEN                RCC_AHB1ENR_USB2OTGFSEN_Msk

+#define RCC_AHB1ENR_USB2OTGFSULPIEN_Pos        (28U)

+#define RCC_AHB1ENR_USB2OTGFSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB2OTGFSULPIEN_Pos) /*!< 0x10000000 */

+#define RCC_AHB1ENR_USB2OTGFSULPIEN            RCC_AHB1ENR_USB2OTGFSULPIEN_Msk

+

+/* Legacy define */

+#define RCC_AHB1ENR_USB2OTGHSEN_Pos            RCC_AHB1ENR_USB2OTGFSEN_Pos

+#define RCC_AHB1ENR_USB2OTGHSEN_Msk            RCC_AHB1ENR_USB2OTGFSEN_Msk

+#define RCC_AHB1ENR_USB2OTGHSEN                RCC_AHB1ENR_USB2OTGFSEN

+#define RCC_AHB1ENR_USB2OTGHSULPIEN_Pos        RCC_AHB1ENR_USB2OTGFSULPIEN_Pos

+#define RCC_AHB1ENR_USB2OTGHSULPIEN_Msk        RCC_AHB1ENR_USB2OTGFSULPIEN_Msk

+#define RCC_AHB1ENR_USB2OTGHSULPIEN            RCC_AHB1ENR_USB2OTGFSULPIEN

+

+

+/********************  Bit definition for RCC_AHB2ENR register  ***************/

+#define RCC_AHB2ENR_DCMIEN_Pos                 (0U)

+#define RCC_AHB2ENR_DCMIEN_Msk                 (0x1UL << RCC_AHB2ENR_DCMIEN_Pos)          /*!< 0x00000001 */

+#define RCC_AHB2ENR_DCMIEN                     RCC_AHB2ENR_DCMIEN_Msk

+#define RCC_AHB2ENR_CRYPEN_Pos                 (4U)

+#define RCC_AHB2ENR_CRYPEN_Msk                 (0x1UL << RCC_AHB2ENR_CRYPEN_Pos)          /*!< 0x00000010 */

+#define RCC_AHB2ENR_CRYPEN                     RCC_AHB2ENR_CRYPEN_Msk

+#define RCC_AHB2ENR_HASHEN_Pos                 (5U)

+#define RCC_AHB2ENR_HASHEN_Msk                 (0x1UL << RCC_AHB2ENR_HASHEN_Pos)          /*!< 0x00000020 */

+#define RCC_AHB2ENR_HASHEN                     RCC_AHB2ENR_HASHEN_Msk

+#define RCC_AHB2ENR_RNGEN_Pos                  (6U)

+#define RCC_AHB2ENR_RNGEN_Msk                  (0x1UL << RCC_AHB2ENR_RNGEN_Pos)           /*!< 0x00000040 */

+#define RCC_AHB2ENR_RNGEN                      RCC_AHB2ENR_RNGEN_Msk

+#define RCC_AHB2ENR_SDMMC2EN_Pos               (9U)

+#define RCC_AHB2ENR_SDMMC2EN_Msk               (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)        /*!< 0x00000200 */

+#define RCC_AHB2ENR_SDMMC2EN                   RCC_AHB2ENR_SDMMC2EN_Msk

+#define RCC_AHB2ENR_SRAM1EN_Pos                (29U)

+#define RCC_AHB2ENR_SRAM1EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos)       /*!< 0x20000000 */

+#define RCC_AHB2ENR_SRAM1EN                    RCC_AHB2ENR_SRAM1EN_Msk

+#define RCC_AHB2ENR_SRAM2EN_Pos                (30U)

+#define RCC_AHB2ENR_SRAM2EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos)       /*!< 0x40000000 */

+#define RCC_AHB2ENR_SRAM2EN                    RCC_AHB2ENR_SRAM2EN_Msk

+#define RCC_AHB2ENR_SRAM3EN_Pos                (31U)

+#define RCC_AHB2ENR_SRAM3EN_Msk                (0x1UL << RCC_AHB2ENR_SRAM3EN_Pos)       /*!< 0x80000000 */

+#define RCC_AHB2ENR_SRAM3EN                    RCC_AHB2ENR_SRAM3EN_Msk

+

+/* Legacy define */

+#define RCC_AHB2ENR_D2SRAM1EN_Pos              RCC_AHB2ENR_SRAM1EN_Pos

+#define RCC_AHB2ENR_D2SRAM1EN_Msk              RCC_AHB2ENR_SRAM1EN_Msk

+#define RCC_AHB2ENR_D2SRAM1EN                  RCC_AHB2ENR_SRAM1EN

+#define RCC_AHB2ENR_D2SRAM2EN_Pos              RCC_AHB2ENR_SRAM2EN_Pos

+#define RCC_AHB2ENR_D2SRAM2EN_Msk              RCC_AHB2ENR_SRAM2EN_Msk

+#define RCC_AHB2ENR_D2SRAM2EN                  RCC_AHB2ENR_SRAM2EN

+#define RCC_AHB2ENR_D2SRAM3EN_Pos              RCC_AHB2ENR_SRAM3EN_Pos

+#define RCC_AHB2ENR_D2SRAM3EN_Msk              RCC_AHB2ENR_SRAM3EN_Msk

+#define RCC_AHB2ENR_D2SRAM3EN                  RCC_AHB2ENR_SRAM3EN

+

+/********************  Bit definition for RCC_AHB4ENR register  ******************/

+#define RCC_AHB4ENR_GPIOAEN_Pos                (0U)

+#define RCC_AHB4ENR_GPIOAEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)         /*!< 0x00000001 */

+#define RCC_AHB4ENR_GPIOAEN                    RCC_AHB4ENR_GPIOAEN_Msk

+#define RCC_AHB4ENR_GPIOBEN_Pos                (1U)

+#define RCC_AHB4ENR_GPIOBEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)         /*!< 0x00000002 */

+#define RCC_AHB4ENR_GPIOBEN                    RCC_AHB4ENR_GPIOBEN_Msk

+#define RCC_AHB4ENR_GPIOCEN_Pos                (2U)

+#define RCC_AHB4ENR_GPIOCEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)         /*!< 0x00000004 */

+#define RCC_AHB4ENR_GPIOCEN                    RCC_AHB4ENR_GPIOCEN_Msk

+#define RCC_AHB4ENR_GPIODEN_Pos                (3U)

+#define RCC_AHB4ENR_GPIODEN_Msk                (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)         /*!< 0x00000008 */

+#define RCC_AHB4ENR_GPIODEN                    RCC_AHB4ENR_GPIODEN_Msk

+#define RCC_AHB4ENR_GPIOEEN_Pos                (4U)

+#define RCC_AHB4ENR_GPIOEEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)         /*!< 0x00000010 */

+#define RCC_AHB4ENR_GPIOEEN                    RCC_AHB4ENR_GPIOEEN_Msk

+#define RCC_AHB4ENR_GPIOFEN_Pos                (5U)

+#define RCC_AHB4ENR_GPIOFEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)         /*!< 0x00000020 */

+#define RCC_AHB4ENR_GPIOFEN                    RCC_AHB4ENR_GPIOFEN_Msk

+#define RCC_AHB4ENR_GPIOGEN_Pos                (6U)

+#define RCC_AHB4ENR_GPIOGEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)         /*!< 0x00000040 */

+#define RCC_AHB4ENR_GPIOGEN                    RCC_AHB4ENR_GPIOGEN_Msk

+#define RCC_AHB4ENR_GPIOHEN_Pos                (7U)

+#define RCC_AHB4ENR_GPIOHEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)         /*!< 0x00000080 */

+#define RCC_AHB4ENR_GPIOHEN                    RCC_AHB4ENR_GPIOHEN_Msk

+#define RCC_AHB4ENR_GPIOIEN_Pos                (8U)

+#define RCC_AHB4ENR_GPIOIEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos)         /*!< 0x00000100 */

+#define RCC_AHB4ENR_GPIOIEN                    RCC_AHB4ENR_GPIOIEN_Msk

+#define RCC_AHB4ENR_GPIOJEN_Pos                (9U)

+#define RCC_AHB4ENR_GPIOJEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos)         /*!< 0x00000200 */

+#define RCC_AHB4ENR_GPIOJEN                    RCC_AHB4ENR_GPIOJEN_Msk

+#define RCC_AHB4ENR_GPIOKEN_Pos                (10U)

+#define RCC_AHB4ENR_GPIOKEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos)         /*!< 0x00000400 */

+#define RCC_AHB4ENR_GPIOKEN                    RCC_AHB4ENR_GPIOKEN_Msk

+#define RCC_AHB4ENR_CRCEN_Pos                  (19U)

+#define RCC_AHB4ENR_CRCEN_Msk                  (0x1UL << RCC_AHB4ENR_CRCEN_Pos)           /*!< 0x00080000 */

+#define RCC_AHB4ENR_CRCEN                      RCC_AHB4ENR_CRCEN_Msk

+#define RCC_AHB4ENR_BDMAEN_Pos                 (21U)

+#define RCC_AHB4ENR_BDMAEN_Msk                 (0x1UL << RCC_AHB4ENR_BDMAEN_Pos)          /*!< 0x00200000 */

+#define RCC_AHB4ENR_BDMAEN                     RCC_AHB4ENR_BDMAEN_Msk

+#define RCC_AHB4ENR_ADC3EN_Pos                 (24U)

+#define RCC_AHB4ENR_ADC3EN_Msk                 (0x1UL << RCC_AHB4ENR_ADC3EN_Pos)          /*!< 0x01000000 */

+#define RCC_AHB4ENR_ADC3EN                     RCC_AHB4ENR_ADC3EN_Msk

+#define RCC_AHB4ENR_HSEMEN_Pos                 (25U)

+#define RCC_AHB4ENR_HSEMEN_Msk                 (0x1UL << RCC_AHB4ENR_HSEMEN_Pos)          /*!< 0x02000000 */

+#define RCC_AHB4ENR_HSEMEN                     RCC_AHB4ENR_HSEMEN_Msk

+#define RCC_AHB4ENR_BKPRAMEN_Pos               (28U)

+#define RCC_AHB4ENR_BKPRAMEN_Msk               (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)        /*!< 0x10000000 */

+#define RCC_AHB4ENR_BKPRAMEN                   RCC_AHB4ENR_BKPRAMEN_Msk

+

+/********************  Bit definition for RCC_APB3ENR register  ******************/

+#define RCC_APB3ENR_LTDCEN_Pos                 (3U)

+#define RCC_APB3ENR_LTDCEN_Msk                 (0x1UL << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */

+#define RCC_APB3ENR_LTDCEN                     RCC_APB3ENR_LTDCEN_Msk

+#define RCC_APB3ENR_DSIEN_Pos                  (4U)

+#define RCC_APB3ENR_DSIEN_Msk                  (0x1UL << RCC_APB3ENR_DSIEN_Pos) /*!< 0x00000010 */

+#define RCC_APB3ENR_DSIEN                      RCC_APB3ENR_DSIEN_Msk

+#define RCC_APB3ENR_WWDG1EN_Pos                (6U)

+#define RCC_APB3ENR_WWDG1EN_Msk                (0x1UL << RCC_APB3ENR_WWDG1EN_Pos) /*!< 0x00000040 */

+#define RCC_APB3ENR_WWDG1EN                    RCC_APB3ENR_WWDG1EN_Msk

+

+/********************  Bit definition for RCC_APB1LENR register  ******************/

+

+#define RCC_APB1LENR_TIM2EN_Pos                (0U)

+#define RCC_APB1LENR_TIM2EN_Msk                (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */

+#define RCC_APB1LENR_TIM2EN                    RCC_APB1LENR_TIM2EN_Msk

+#define RCC_APB1LENR_TIM3EN_Pos                (1U)

+#define RCC_APB1LENR_TIM3EN_Msk                (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */

+#define RCC_APB1LENR_TIM3EN                    RCC_APB1LENR_TIM3EN_Msk

+#define RCC_APB1LENR_TIM4EN_Pos                (2U)

+#define RCC_APB1LENR_TIM4EN_Msk                (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */

+#define RCC_APB1LENR_TIM4EN                    RCC_APB1LENR_TIM4EN_Msk

+#define RCC_APB1LENR_TIM5EN_Pos                (3U)

+#define RCC_APB1LENR_TIM5EN_Msk                (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */

+#define RCC_APB1LENR_TIM5EN                    RCC_APB1LENR_TIM5EN_Msk

+#define RCC_APB1LENR_TIM6EN_Pos                (4U)

+#define RCC_APB1LENR_TIM6EN_Msk                (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */

+#define RCC_APB1LENR_TIM6EN                    RCC_APB1LENR_TIM6EN_Msk

+#define RCC_APB1LENR_TIM7EN_Pos                (5U)

+#define RCC_APB1LENR_TIM7EN_Msk                (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */

+#define RCC_APB1LENR_TIM7EN                    RCC_APB1LENR_TIM7EN_Msk

+#define RCC_APB1LENR_TIM12EN_Pos               (6U)

+#define RCC_APB1LENR_TIM12EN_Msk               (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */

+#define RCC_APB1LENR_TIM12EN                   RCC_APB1LENR_TIM12EN_Msk

+#define RCC_APB1LENR_TIM13EN_Pos               (7U)

+#define RCC_APB1LENR_TIM13EN_Msk               (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */

+#define RCC_APB1LENR_TIM13EN                   RCC_APB1LENR_TIM13EN_Msk

+#define RCC_APB1LENR_TIM14EN_Pos               (8U)

+#define RCC_APB1LENR_TIM14EN_Msk               (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */

+#define RCC_APB1LENR_TIM14EN                   RCC_APB1LENR_TIM14EN_Msk

+#define RCC_APB1LENR_LPTIM1EN_Pos              (9U)

+#define RCC_APB1LENR_LPTIM1EN_Msk              (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */

+#define RCC_APB1LENR_LPTIM1EN                  RCC_APB1LENR_LPTIM1EN_Msk

+

+#define RCC_APB1LENR_WWDG2EN_Pos               (11U)

+#define RCC_APB1LENR_WWDG2EN_Msk               (0x1UL << RCC_APB1LENR_WWDG2EN_Pos) /*!< 0x00000800 */

+#define RCC_APB1LENR_WWDG2EN                   RCC_APB1LENR_WWDG2EN_Msk

+

+#define RCC_APB1LENR_SPI2EN_Pos                (14U)

+#define RCC_APB1LENR_SPI2EN_Msk                (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */

+#define RCC_APB1LENR_SPI2EN                    RCC_APB1LENR_SPI2EN_Msk

+#define RCC_APB1LENR_SPI3EN_Pos                (15U)

+#define RCC_APB1LENR_SPI3EN_Msk                (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */

+#define RCC_APB1LENR_SPI3EN                    RCC_APB1LENR_SPI3EN_Msk

+#define RCC_APB1LENR_SPDIFRXEN_Pos             (16U)

+#define RCC_APB1LENR_SPDIFRXEN_Msk             (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */

+#define RCC_APB1LENR_SPDIFRXEN                 RCC_APB1LENR_SPDIFRXEN_Msk

+#define RCC_APB1LENR_USART2EN_Pos              (17U)

+#define RCC_APB1LENR_USART2EN_Msk              (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */

+#define RCC_APB1LENR_USART2EN                  RCC_APB1LENR_USART2EN_Msk

+#define RCC_APB1LENR_USART3EN_Pos              (18U)

+#define RCC_APB1LENR_USART3EN_Msk              (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */

+#define RCC_APB1LENR_USART3EN                  RCC_APB1LENR_USART3EN_Msk

+#define RCC_APB1LENR_UART4EN_Pos               (19U)

+#define RCC_APB1LENR_UART4EN_Msk               (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */

+#define RCC_APB1LENR_UART4EN                   RCC_APB1LENR_UART4EN_Msk

+#define RCC_APB1LENR_UART5EN_Pos               (20U)

+#define RCC_APB1LENR_UART5EN_Msk               (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */

+#define RCC_APB1LENR_UART5EN                   RCC_APB1LENR_UART5EN_Msk

+#define RCC_APB1LENR_I2C1EN_Pos                (21U)

+#define RCC_APB1LENR_I2C1EN_Msk                (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */

+#define RCC_APB1LENR_I2C1EN                    RCC_APB1LENR_I2C1EN_Msk

+#define RCC_APB1LENR_I2C2EN_Pos                (22U)

+#define RCC_APB1LENR_I2C2EN_Msk                (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */

+#define RCC_APB1LENR_I2C2EN                    RCC_APB1LENR_I2C2EN_Msk

+#define RCC_APB1LENR_I2C3EN_Pos                (23U)

+#define RCC_APB1LENR_I2C3EN_Msk                (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */

+#define RCC_APB1LENR_I2C3EN                    RCC_APB1LENR_I2C3EN_Msk

+#define RCC_APB1LENR_CECEN_Pos                 (27U)

+#define RCC_APB1LENR_CECEN_Msk                 (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */

+#define RCC_APB1LENR_CECEN                     RCC_APB1LENR_CECEN_Msk

+#define RCC_APB1LENR_DAC12EN_Pos               (29U)

+#define RCC_APB1LENR_DAC12EN_Msk               (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */

+#define RCC_APB1LENR_DAC12EN                   RCC_APB1LENR_DAC12EN_Msk

+#define RCC_APB1LENR_UART7EN_Pos               (30U)

+#define RCC_APB1LENR_UART7EN_Msk               (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */

+#define RCC_APB1LENR_UART7EN                   RCC_APB1LENR_UART7EN_Msk

+#define RCC_APB1LENR_UART8EN_Pos               (31U)

+#define RCC_APB1LENR_UART8EN_Msk               (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */

+#define RCC_APB1LENR_UART8EN                   RCC_APB1LENR_UART8EN_Msk

+

+/* Legacy define */

+#define RCC_APB1LENR_HDMICECEN_Pos             RCC_APB1LENR_CECEN_Pos

+#define RCC_APB1LENR_HDMICECEN_Msk             RCC_APB1LENR_CECEN_Msk

+#define RCC_APB1LENR_HDMICECEN                 RCC_APB1LENR_CECEN

+/********************  Bit definition for RCC_APB1HENR register  ******************/

+#define RCC_APB1HENR_CRSEN_Pos                 (1U)

+#define RCC_APB1HENR_CRSEN_Msk                 (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1HENR_CRSEN                     RCC_APB1HENR_CRSEN_Msk

+#define RCC_APB1HENR_SWPMIEN_Pos               (2U)

+#define RCC_APB1HENR_SWPMIEN_Msk               (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1HENR_SWPMIEN                   RCC_APB1HENR_SWPMIEN_Msk

+#define RCC_APB1HENR_OPAMPEN_Pos               (4U)

+#define RCC_APB1HENR_OPAMPEN_Msk               (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1HENR_OPAMPEN                   RCC_APB1HENR_OPAMPEN_Msk

+#define RCC_APB1HENR_MDIOSEN_Pos               (5U)

+#define RCC_APB1HENR_MDIOSEN_Msk               (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1HENR_MDIOSEN                   RCC_APB1HENR_MDIOSEN_Msk

+#define RCC_APB1HENR_FDCANEN_Pos               (8U)

+#define RCC_APB1HENR_FDCANEN_Msk               (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1HENR_FDCANEN                   RCC_APB1HENR_FDCANEN_Msk

+

+/********************  Bit definition for RCC_APB2ENR register  ******************/

+#define RCC_APB2ENR_TIM1EN_Pos                 (0U)

+#define RCC_APB2ENR_TIM1EN_Msk                 (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */

+#define RCC_APB2ENR_TIM1EN                     RCC_APB2ENR_TIM1EN_Msk

+#define RCC_APB2ENR_TIM8EN_Pos                 (1U)

+#define RCC_APB2ENR_TIM8EN_Msk                 (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */

+#define RCC_APB2ENR_TIM8EN                     RCC_APB2ENR_TIM8EN_Msk

+#define RCC_APB2ENR_USART1EN_Pos               (4U)

+#define RCC_APB2ENR_USART1EN_Msk               (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */

+#define RCC_APB2ENR_USART1EN                   RCC_APB2ENR_USART1EN_Msk

+#define RCC_APB2ENR_USART6EN_Pos               (5U)

+#define RCC_APB2ENR_USART6EN_Msk               (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */

+#define RCC_APB2ENR_USART6EN                   RCC_APB2ENR_USART6EN_Msk

+#define RCC_APB2ENR_SPI1EN_Pos                 (12U)

+#define RCC_APB2ENR_SPI1EN_Msk                 (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */

+#define RCC_APB2ENR_SPI1EN                     RCC_APB2ENR_SPI1EN_Msk

+#define RCC_APB2ENR_SPI4EN_Pos                 (13U)

+#define RCC_APB2ENR_SPI4EN_Msk                 (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */

+#define RCC_APB2ENR_SPI4EN                     RCC_APB2ENR_SPI4EN_Msk

+#define RCC_APB2ENR_TIM15EN_Pos                (16U)

+#define RCC_APB2ENR_TIM15EN_Msk                (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */

+#define RCC_APB2ENR_TIM15EN                    RCC_APB2ENR_TIM15EN_Msk

+#define RCC_APB2ENR_TIM16EN_Pos                (17U)

+#define RCC_APB2ENR_TIM16EN_Msk                (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */

+#define RCC_APB2ENR_TIM16EN                    RCC_APB2ENR_TIM16EN_Msk

+#define RCC_APB2ENR_TIM17EN_Pos                (18U)

+#define RCC_APB2ENR_TIM17EN_Msk                (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */

+#define RCC_APB2ENR_TIM17EN                    RCC_APB2ENR_TIM17EN_Msk

+#define RCC_APB2ENR_SPI5EN_Pos                 (20U)

+#define RCC_APB2ENR_SPI5EN_Msk                 (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */

+#define RCC_APB2ENR_SPI5EN                     RCC_APB2ENR_SPI5EN_Msk

+#define RCC_APB2ENR_SAI1EN_Pos                 (22U)

+#define RCC_APB2ENR_SAI1EN_Msk                 (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */

+#define RCC_APB2ENR_SAI1EN                     RCC_APB2ENR_SAI1EN_Msk

+#define RCC_APB2ENR_SAI2EN_Pos                 (23U)

+#define RCC_APB2ENR_SAI2EN_Msk                 (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */

+#define RCC_APB2ENR_SAI2EN                     RCC_APB2ENR_SAI2EN_Msk

+#define RCC_APB2ENR_SAI3EN_Pos                 (24U)

+#define RCC_APB2ENR_SAI3EN_Msk                 (0x1UL << RCC_APB2ENR_SAI3EN_Pos) /*!< 0x01000000 */

+#define RCC_APB2ENR_SAI3EN                     RCC_APB2ENR_SAI3EN_Msk

+#define RCC_APB2ENR_DFSDM1EN_Pos               (28U)

+#define RCC_APB2ENR_DFSDM1EN_Msk               (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x10000000 */

+#define RCC_APB2ENR_DFSDM1EN                   RCC_APB2ENR_DFSDM1EN_Msk

+#define RCC_APB2ENR_HRTIMEN_Pos                (29U)

+#define RCC_APB2ENR_HRTIMEN_Msk                (0x1UL << RCC_APB2ENR_HRTIMEN_Pos) /*!< 0x20000000 */

+#define RCC_APB2ENR_HRTIMEN                    RCC_APB2ENR_HRTIMEN_Msk

+

+/********************  Bit definition for RCC_APB4ENR register  ******************/

+#define RCC_APB4ENR_SYSCFGEN_Pos               (1U)

+#define RCC_APB4ENR_SYSCFGEN_Msk               (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */

+#define RCC_APB4ENR_SYSCFGEN                   RCC_APB4ENR_SYSCFGEN_Msk

+#define RCC_APB4ENR_LPUART1EN_Pos              (3U)

+#define RCC_APB4ENR_LPUART1EN_Msk              (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */

+#define RCC_APB4ENR_LPUART1EN                  RCC_APB4ENR_LPUART1EN_Msk

+#define RCC_APB4ENR_SPI6EN_Pos                 (5U)

+#define RCC_APB4ENR_SPI6EN_Msk                 (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */

+#define RCC_APB4ENR_SPI6EN                     RCC_APB4ENR_SPI6EN_Msk

+#define RCC_APB4ENR_I2C4EN_Pos                 (7U)

+#define RCC_APB4ENR_I2C4EN_Msk                 (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */

+#define RCC_APB4ENR_I2C4EN                     RCC_APB4ENR_I2C4EN_Msk

+#define RCC_APB4ENR_LPTIM2EN_Pos               (9U)

+#define RCC_APB4ENR_LPTIM2EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */

+#define RCC_APB4ENR_LPTIM2EN                   RCC_APB4ENR_LPTIM2EN_Msk

+#define RCC_APB4ENR_LPTIM3EN_Pos               (10U)

+#define RCC_APB4ENR_LPTIM3EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */

+#define RCC_APB4ENR_LPTIM3EN                   RCC_APB4ENR_LPTIM3EN_Msk

+#define RCC_APB4ENR_LPTIM4EN_Pos               (11U)

+#define RCC_APB4ENR_LPTIM4EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos) /*!< 0x00000800 */

+#define RCC_APB4ENR_LPTIM4EN                   RCC_APB4ENR_LPTIM4EN_Msk

+#define RCC_APB4ENR_LPTIM5EN_Pos               (12U)

+#define RCC_APB4ENR_LPTIM5EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos) /*!< 0x00001000 */

+#define RCC_APB4ENR_LPTIM5EN                   RCC_APB4ENR_LPTIM5EN_Msk

+#define RCC_APB4ENR_COMP12EN_Pos               (14U)

+#define RCC_APB4ENR_COMP12EN_Msk               (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */

+#define RCC_APB4ENR_COMP12EN                   RCC_APB4ENR_COMP12EN_Msk

+#define RCC_APB4ENR_VREFEN_Pos                 (15U)

+#define RCC_APB4ENR_VREFEN_Msk                 (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */

+#define RCC_APB4ENR_VREFEN                     RCC_APB4ENR_VREFEN_Msk

+#define RCC_APB4ENR_RTCAPBEN_Pos               (16U)

+#define RCC_APB4ENR_RTCAPBEN_Msk               (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */

+#define RCC_APB4ENR_RTCAPBEN                   RCC_APB4ENR_RTCAPBEN_Msk

+#define RCC_APB4ENR_SAI4EN_Pos                 (21U)

+#define RCC_APB4ENR_SAI4EN_Msk                 (0x1UL << RCC_APB4ENR_SAI4EN_Pos) /*!< 0x00200000 */

+#define RCC_APB4ENR_SAI4EN                     RCC_APB4ENR_SAI4EN_Msk

+

+

+/********************  Bit definition for RCC_AHB3RSTR register  ***************/

+#define RCC_AHB3RSTR_MDMARST_Pos               (0U)

+#define RCC_AHB3RSTR_MDMARST_Msk               (0x1UL << RCC_AHB3RSTR_MDMARST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB3RSTR_MDMARST                   RCC_AHB3RSTR_MDMARST_Msk

+#define RCC_AHB3RSTR_DMA2DRST_Pos              (4U)

+#define RCC_AHB3RSTR_DMA2DRST_Msk              (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos)     /*!< 0x00000010 */

+#define RCC_AHB3RSTR_DMA2DRST                  RCC_AHB3RSTR_DMA2DRST_Msk

+#define RCC_AHB3RSTR_JPGDECRST_Pos             (5U)

+#define RCC_AHB3RSTR_JPGDECRST_Msk             (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos)    /*!< 0x00000020 */

+#define RCC_AHB3RSTR_JPGDECRST                 RCC_AHB3RSTR_JPGDECRST_Msk

+#define RCC_AHB3RSTR_FMCRST_Pos                (12U)

+#define RCC_AHB3RSTR_FMCRST_Msk                (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)      /*!< 0x00001000 */

+#define RCC_AHB3RSTR_FMCRST                    RCC_AHB3RSTR_FMCRST_Msk

+#define RCC_AHB3RSTR_QSPIRST_Pos               (14U)

+#define RCC_AHB3RSTR_QSPIRST_Msk               (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos)     /*!< 0x00004000 */

+#define RCC_AHB3RSTR_QSPIRST                   RCC_AHB3RSTR_QSPIRST_Msk

+#define RCC_AHB3RSTR_SDMMC1RST_Pos             (16U)

+#define RCC_AHB3RSTR_SDMMC1RST_Msk             (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos)   /*!< 0x00010000 */

+#define RCC_AHB3RSTR_SDMMC1RST                 RCC_AHB3RSTR_SDMMC1RST_Msk

+

+

+/********************  Bit definition for RCC_AHB1RSTR register  ***************/

+#define RCC_AHB1RSTR_DMA1RST_Pos               (0U)

+#define RCC_AHB1RSTR_DMA1RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB1RSTR_DMA1RST                   RCC_AHB1RSTR_DMA1RST_Msk

+#define RCC_AHB1RSTR_DMA2RST_Pos               (1U)

+#define RCC_AHB1RSTR_DMA2RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)      /*!< 0x00000002 */

+#define RCC_AHB1RSTR_DMA2RST                   RCC_AHB1RSTR_DMA2RST_Msk

+#define RCC_AHB1RSTR_ADC12RST_Pos              (5U)

+#define RCC_AHB1RSTR_ADC12RST_Msk              (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)     /*!< 0x00000020 */

+#define RCC_AHB1RSTR_ADC12RST                  RCC_AHB1RSTR_ADC12RST_Msk

+#define RCC_AHB1RSTR_ARTRST_Pos                (14U)

+#define RCC_AHB1RSTR_ARTRST_Msk                (0x1UL << RCC_AHB1RSTR_ARTRST_Pos)       /*!< 0x00004000 */

+#define RCC_AHB1RSTR_ARTRST                    RCC_AHB1RSTR_ARTRST_Msk

+#define RCC_AHB1RSTR_ETH1MACRST_Pos            (15U)

+#define RCC_AHB1RSTR_ETH1MACRST_Msk            (0x1UL << RCC_AHB1RSTR_ETH1MACRST_Pos)   /*!< 0x00008000 */

+#define RCC_AHB1RSTR_ETH1MACRST                RCC_AHB1RSTR_ETH1MACRST_Msk

+#define RCC_AHB1RSTR_USB1OTGHSRST_Pos          (25U)

+#define RCC_AHB1RSTR_USB1OTGHSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */

+#define RCC_AHB1RSTR_USB1OTGHSRST              RCC_AHB1RSTR_USB1OTGHSRST_Msk

+#define RCC_AHB1RSTR_USB2OTGFSRST_Pos          (27U)

+#define RCC_AHB1RSTR_USB2OTGFSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB2OTGFSRST_Pos) /*!< 0x08000000 */

+#define RCC_AHB1RSTR_USB2OTGFSRST              RCC_AHB1RSTR_USB2OTGFSRST_Msk

+

+/* Legacy define */

+#define RCC_AHB1RSTR_USB2OTGHSRST_Pos          RCC_AHB1RSTR_USB2OTGFSRST_Pos

+#define RCC_AHB1RSTR_USB2OTGHSRST_Msk          RCC_AHB1RSTR_USB2OTGFSRST_Msk

+#define RCC_AHB1RSTR_USB2OTGHSRST              RCC_AHB1RSTR_USB2OTGFSRST

+

+/********************  Bit definition for RCC_AHB2RSTR register  ***************/

+#define RCC_AHB2RSTR_DCMIRST_Pos               (0U)

+#define RCC_AHB2RSTR_DCMIRST_Msk               (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos)       /*!< 0x00000001 */

+#define RCC_AHB2RSTR_DCMIRST                   RCC_AHB2RSTR_DCMIRST_Msk

+#define RCC_AHB2RSTR_CRYPRST_Pos               (4U)

+#define RCC_AHB2RSTR_CRYPRST_Msk               (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos)       /*!< 0x00000010 */

+#define RCC_AHB2RSTR_CRYPRST                   RCC_AHB2RSTR_CRYPRST_Msk

+#define RCC_AHB2RSTR_HASHRST_Pos               (5U)

+#define RCC_AHB2RSTR_HASHRST_Msk               (0x1UL << RCC_AHB2RSTR_HASHRST_Pos)       /*!< 0x00000020 */

+#define RCC_AHB2RSTR_HASHRST                   RCC_AHB2RSTR_HASHRST_Msk

+#define RCC_AHB2RSTR_RNGRST_Pos                (6U)

+#define RCC_AHB2RSTR_RNGRST_Msk                (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)        /*!< 0x00000040 */

+#define RCC_AHB2RSTR_RNGRST                    RCC_AHB2RSTR_RNGRST_Msk

+#define RCC_AHB2RSTR_SDMMC2RST_Pos             (9U)

+#define RCC_AHB2RSTR_SDMMC2RST_Msk             (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)     /*!< 0x00000200 */

+#define RCC_AHB2RSTR_SDMMC2RST                 RCC_AHB2RSTR_SDMMC2RST_Msk

+

+/********************  Bit definition for RCC_AHB4RSTR register  ******************/

+#define RCC_AHB4RSTR_GPIOARST_Pos              (0U)

+#define RCC_AHB4RSTR_GPIOARST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB4RSTR_GPIOARST                  RCC_AHB4RSTR_GPIOARST_Msk

+#define RCC_AHB4RSTR_GPIOBRST_Pos              (1U)

+#define RCC_AHB4RSTR_GPIOBRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)      /*!< 0x00000002 */

+#define RCC_AHB4RSTR_GPIOBRST                  RCC_AHB4RSTR_GPIOBRST_Msk

+#define RCC_AHB4RSTR_GPIOCRST_Pos              (2U)

+#define RCC_AHB4RSTR_GPIOCRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)      /*!< 0x00000004 */

+#define RCC_AHB4RSTR_GPIOCRST                  RCC_AHB4RSTR_GPIOCRST_Msk

+#define RCC_AHB4RSTR_GPIODRST_Pos              (3U)

+#define RCC_AHB4RSTR_GPIODRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)      /*!< 0x00000008 */

+#define RCC_AHB4RSTR_GPIODRST                  RCC_AHB4RSTR_GPIODRST_Msk

+#define RCC_AHB4RSTR_GPIOERST_Pos              (4U)

+#define RCC_AHB4RSTR_GPIOERST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)      /*!< 0x00000010 */

+#define RCC_AHB4RSTR_GPIOERST                  RCC_AHB4RSTR_GPIOERST_Msk

+#define RCC_AHB4RSTR_GPIOFRST_Pos              (5U)

+#define RCC_AHB4RSTR_GPIOFRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)       /*!< 0x00000020 */

+#define RCC_AHB4RSTR_GPIOFRST                  RCC_AHB4RSTR_GPIOFRST_Msk

+#define RCC_AHB4RSTR_GPIOGRST_Pos              (6U)

+#define RCC_AHB4RSTR_GPIOGRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)       /*!< 0x00000040 */

+#define RCC_AHB4RSTR_GPIOGRST                  RCC_AHB4RSTR_GPIOGRST_Msk

+#define RCC_AHB4RSTR_GPIOHRST_Pos              (7U)

+#define RCC_AHB4RSTR_GPIOHRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)       /*!< 0x00000080 */

+#define RCC_AHB4RSTR_GPIOHRST                  RCC_AHB4RSTR_GPIOHRST_Msk

+#define RCC_AHB4RSTR_GPIOIRST_Pos              (8U)

+#define RCC_AHB4RSTR_GPIOIRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos)       /*!< 0x00000100 */

+#define RCC_AHB4RSTR_GPIOIRST                  RCC_AHB4RSTR_GPIOIRST_Msk

+#define RCC_AHB4RSTR_GPIOJRST_Pos              (9U)

+#define RCC_AHB4RSTR_GPIOJRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos)       /*!< 0x00000200 */

+#define RCC_AHB4RSTR_GPIOJRST                  RCC_AHB4RSTR_GPIOJRST_Msk

+#define RCC_AHB4RSTR_GPIOKRST_Pos              (10U)

+#define RCC_AHB4RSTR_GPIOKRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos)       /*!< 0x00000400 */

+#define RCC_AHB4RSTR_GPIOKRST                  RCC_AHB4RSTR_GPIOKRST_Msk

+#define RCC_AHB4RSTR_CRCRST_Pos                (19U)

+#define RCC_AHB4RSTR_CRCRST_Msk                (0x1UL << RCC_AHB4RSTR_CRCRST_Pos)         /*!< 0x00080000 */

+#define RCC_AHB4RSTR_CRCRST                    RCC_AHB4RSTR_CRCRST_Msk

+#define RCC_AHB4RSTR_BDMARST_Pos               (21U)

+#define RCC_AHB4RSTR_BDMARST_Msk               (0x1UL << RCC_AHB4RSTR_BDMARST_Pos)        /*!< 0x00200000 */

+#define RCC_AHB4RSTR_BDMARST                   RCC_AHB4RSTR_BDMARST_Msk

+#define RCC_AHB4RSTR_ADC3RST_Pos               (24U)

+#define RCC_AHB4RSTR_ADC3RST_Msk               (0x1UL << RCC_AHB4RSTR_ADC3RST_Pos)        /*!< 0x01000000 */

+#define RCC_AHB4RSTR_ADC3RST                   RCC_AHB4RSTR_ADC3RST_Msk

+#define RCC_AHB4RSTR_HSEMRST_Pos               (25U)

+#define RCC_AHB4RSTR_HSEMRST_Msk               (0x1UL << RCC_AHB4RSTR_HSEMRST_Pos)        /*!< 0x02000000 */

+#define RCC_AHB4RSTR_HSEMRST                   RCC_AHB4RSTR_HSEMRST_Msk

+

+

+/********************  Bit definition for RCC_APB3RSTR register  ******************/

+#define RCC_APB3RSTR_LTDCRST_Pos               (3U)

+#define RCC_APB3RSTR_LTDCRST_Msk               (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */

+#define RCC_APB3RSTR_LTDCRST                   RCC_APB3RSTR_LTDCRST_Msk

+#define RCC_APB3RSTR_DSIRST_Pos                (4U)

+#define RCC_APB3RSTR_DSIRST_Msk                (0x1UL << RCC_APB3RSTR_DSIRST_Pos) /*!< 0x00000010 */

+#define RCC_APB3RSTR_DSIRST                    RCC_APB3RSTR_DSIRST_Msk

+

+/********************  Bit definition for RCC_APB1LRSTR register  ******************/

+

+#define RCC_APB1LRSTR_TIM2RST_Pos              (0U)

+#define RCC_APB1LRSTR_TIM2RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */

+#define RCC_APB1LRSTR_TIM2RST                  RCC_APB1LRSTR_TIM2RST_Msk

+#define RCC_APB1LRSTR_TIM3RST_Pos              (1U)

+#define RCC_APB1LRSTR_TIM3RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */

+#define RCC_APB1LRSTR_TIM3RST                  RCC_APB1LRSTR_TIM3RST_Msk

+#define RCC_APB1LRSTR_TIM4RST_Pos              (2U)

+#define RCC_APB1LRSTR_TIM4RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */

+#define RCC_APB1LRSTR_TIM4RST                  RCC_APB1LRSTR_TIM4RST_Msk

+#define RCC_APB1LRSTR_TIM5RST_Pos              (3U)

+#define RCC_APB1LRSTR_TIM5RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */

+#define RCC_APB1LRSTR_TIM5RST                  RCC_APB1LRSTR_TIM5RST_Msk

+#define RCC_APB1LRSTR_TIM6RST_Pos              (4U)

+#define RCC_APB1LRSTR_TIM6RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */

+#define RCC_APB1LRSTR_TIM6RST                  RCC_APB1LRSTR_TIM6RST_Msk

+#define RCC_APB1LRSTR_TIM7RST_Pos              (5U)

+#define RCC_APB1LRSTR_TIM7RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */

+#define RCC_APB1LRSTR_TIM7RST                  RCC_APB1LRSTR_TIM7RST_Msk

+#define RCC_APB1LRSTR_TIM12RST_Pos             (6U)

+#define RCC_APB1LRSTR_TIM12RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */

+#define RCC_APB1LRSTR_TIM12RST                 RCC_APB1LRSTR_TIM12RST_Msk

+#define RCC_APB1LRSTR_TIM13RST_Pos             (7U)

+#define RCC_APB1LRSTR_TIM13RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */

+#define RCC_APB1LRSTR_TIM13RST                 RCC_APB1LRSTR_TIM13RST_Msk

+#define RCC_APB1LRSTR_TIM14RST_Pos             (8U)

+#define RCC_APB1LRSTR_TIM14RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */

+#define RCC_APB1LRSTR_TIM14RST                 RCC_APB1LRSTR_TIM14RST_Msk

+#define RCC_APB1LRSTR_LPTIM1RST_Pos            (9U)

+#define RCC_APB1LRSTR_LPTIM1RST_Msk            (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */

+#define RCC_APB1LRSTR_LPTIM1RST                RCC_APB1LRSTR_LPTIM1RST_Msk

+#define RCC_APB1LRSTR_SPI2RST_Pos              (14U)

+#define RCC_APB1LRSTR_SPI2RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */

+#define RCC_APB1LRSTR_SPI2RST                  RCC_APB1LRSTR_SPI2RST_Msk

+#define RCC_APB1LRSTR_SPI3RST_Pos              (15U)

+#define RCC_APB1LRSTR_SPI3RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */

+#define RCC_APB1LRSTR_SPI3RST                  RCC_APB1LRSTR_SPI3RST_Msk

+#define RCC_APB1LRSTR_SPDIFRXRST_Pos           (16U)

+#define RCC_APB1LRSTR_SPDIFRXRST_Msk           (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */

+#define RCC_APB1LRSTR_SPDIFRXRST               RCC_APB1LRSTR_SPDIFRXRST_Msk

+#define RCC_APB1LRSTR_USART2RST_Pos            (17U)

+#define RCC_APB1LRSTR_USART2RST_Msk            (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */

+#define RCC_APB1LRSTR_USART2RST                RCC_APB1LRSTR_USART2RST_Msk

+#define RCC_APB1LRSTR_USART3RST_Pos            (18U)

+#define RCC_APB1LRSTR_USART3RST_Msk            (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */

+#define RCC_APB1LRSTR_USART3RST                RCC_APB1LRSTR_USART3RST_Msk

+#define RCC_APB1LRSTR_UART4RST_Pos             (19U)

+#define RCC_APB1LRSTR_UART4RST_Msk             (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */

+#define RCC_APB1LRSTR_UART4RST                 RCC_APB1LRSTR_UART4RST_Msk

+#define RCC_APB1LRSTR_UART5RST_Pos             (20U)

+#define RCC_APB1LRSTR_UART5RST_Msk             (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */

+#define RCC_APB1LRSTR_UART5RST                 RCC_APB1LRSTR_UART5RST_Msk

+#define RCC_APB1LRSTR_I2C1RST_Pos              (21U)

+#define RCC_APB1LRSTR_I2C1RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */

+#define RCC_APB1LRSTR_I2C1RST                  RCC_APB1LRSTR_I2C1RST_Msk

+#define RCC_APB1LRSTR_I2C2RST_Pos              (22U)

+#define RCC_APB1LRSTR_I2C2RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */

+#define RCC_APB1LRSTR_I2C2RST                  RCC_APB1LRSTR_I2C2RST_Msk

+#define RCC_APB1LRSTR_I2C3RST_Pos              (23U)

+#define RCC_APB1LRSTR_I2C3RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */

+#define RCC_APB1LRSTR_I2C3RST                  RCC_APB1LRSTR_I2C3RST_Msk

+#define RCC_APB1LRSTR_CECRST_Pos               (27U)

+#define RCC_APB1LRSTR_CECRST_Msk               (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */

+#define RCC_APB1LRSTR_CECRST                   RCC_APB1LRSTR_CECRST_Msk

+#define RCC_APB1LRSTR_DAC12RST_Pos             (29U)

+#define RCC_APB1LRSTR_DAC12RST_Msk             (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */

+#define RCC_APB1LRSTR_DAC12RST                 RCC_APB1LRSTR_DAC12RST_Msk

+#define RCC_APB1LRSTR_UART7RST_Pos             (30U)

+#define RCC_APB1LRSTR_UART7RST_Msk             (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */

+#define RCC_APB1LRSTR_UART7RST                 RCC_APB1LRSTR_UART7RST_Msk

+#define RCC_APB1LRSTR_UART8RST_Pos             (31U)

+#define RCC_APB1LRSTR_UART8RST_Msk             (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */

+#define RCC_APB1LRSTR_UART8RST                 RCC_APB1LRSTR_UART8RST_Msk

+

+/* Legacy define */

+#define RCC_APB1LRSTR_HDMICECRST_Pos           RCC_APB1LRSTR_CECRST_Pos

+#define RCC_APB1LRSTR_HDMICECRST_Msk           RCC_APB1LRSTR_CECRST_Msk

+#define RCC_APB1LRSTR_HDMICECRST               RCC_APB1LRSTR_CECRST

+/********************  Bit definition for RCC_APB1HRSTR register  ******************/

+#define RCC_APB1HRSTR_CRSRST_Pos               (1U)

+#define RCC_APB1HRSTR_CRSRST_Msk               (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */

+#define RCC_APB1HRSTR_CRSRST                   RCC_APB1HRSTR_CRSRST_Msk

+#define RCC_APB1HRSTR_SWPMIRST_Pos             (2U)

+#define RCC_APB1HRSTR_SWPMIRST_Msk             (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */

+#define RCC_APB1HRSTR_SWPMIRST                 RCC_APB1HRSTR_SWPMIRST_Msk

+#define RCC_APB1HRSTR_OPAMPRST_Pos             (4U)

+#define RCC_APB1HRSTR_OPAMPRST_Msk             (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */

+#define RCC_APB1HRSTR_OPAMPRST                 RCC_APB1HRSTR_OPAMPRST_Msk

+#define RCC_APB1HRSTR_MDIOSRST_Pos             (5U)

+#define RCC_APB1HRSTR_MDIOSRST_Msk             (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */

+#define RCC_APB1HRSTR_MDIOSRST                 RCC_APB1HRSTR_MDIOSRST_Msk

+#define RCC_APB1HRSTR_FDCANRST_Pos             (8U)

+#define RCC_APB1HRSTR_FDCANRST_Msk             (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */

+#define RCC_APB1HRSTR_FDCANRST                 RCC_APB1HRSTR_FDCANRST_Msk

+

+/********************  Bit definition for RCC_APB2RSTR register  ******************/

+#define RCC_APB2RSTR_TIM1RST_Pos               (0U)

+#define RCC_APB2RSTR_TIM1RST_Msk               (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */

+#define RCC_APB2RSTR_TIM1RST                   RCC_APB2RSTR_TIM1RST_Msk

+#define RCC_APB2RSTR_TIM8RST_Pos               (1U)

+#define RCC_APB2RSTR_TIM8RST_Msk               (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */

+#define RCC_APB2RSTR_TIM8RST                   RCC_APB2RSTR_TIM8RST_Msk

+#define RCC_APB2RSTR_USART1RST_Pos             (4U)

+#define RCC_APB2RSTR_USART1RST_Msk             (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */

+#define RCC_APB2RSTR_USART1RST                 RCC_APB2RSTR_USART1RST_Msk

+#define RCC_APB2RSTR_USART6RST_Pos             (5U)

+#define RCC_APB2RSTR_USART6RST_Msk             (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */

+#define RCC_APB2RSTR_USART6RST                 RCC_APB2RSTR_USART6RST_Msk

+#define RCC_APB2RSTR_SPI1RST_Pos               (12U)

+#define RCC_APB2RSTR_SPI1RST_Msk               (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */

+#define RCC_APB2RSTR_SPI1RST                   RCC_APB2RSTR_SPI1RST_Msk

+#define RCC_APB2RSTR_SPI4RST_Pos               (13U)

+#define RCC_APB2RSTR_SPI4RST_Msk               (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */

+#define RCC_APB2RSTR_SPI4RST                   RCC_APB2RSTR_SPI4RST_Msk

+#define RCC_APB2RSTR_TIM15RST_Pos              (16U)

+#define RCC_APB2RSTR_TIM15RST_Msk              (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */

+#define RCC_APB2RSTR_TIM15RST                  RCC_APB2RSTR_TIM15RST_Msk

+#define RCC_APB2RSTR_TIM16RST_Pos              (17U)

+#define RCC_APB2RSTR_TIM16RST_Msk              (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */

+#define RCC_APB2RSTR_TIM16RST                  RCC_APB2RSTR_TIM16RST_Msk

+#define RCC_APB2RSTR_TIM17RST_Pos              (18U)

+#define RCC_APB2RSTR_TIM17RST_Msk              (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */

+#define RCC_APB2RSTR_TIM17RST                  RCC_APB2RSTR_TIM17RST_Msk

+#define RCC_APB2RSTR_SPI5RST_Pos               (20U)

+#define RCC_APB2RSTR_SPI5RST_Msk               (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */

+#define RCC_APB2RSTR_SPI5RST                   RCC_APB2RSTR_SPI5RST_Msk

+#define RCC_APB2RSTR_SAI1RST_Pos               (22U)

+#define RCC_APB2RSTR_SAI1RST_Msk               (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */

+#define RCC_APB2RSTR_SAI1RST                   RCC_APB2RSTR_SAI1RST_Msk

+#define RCC_APB2RSTR_SAI2RST_Pos               (23U)

+#define RCC_APB2RSTR_SAI2RST_Msk               (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */

+#define RCC_APB2RSTR_SAI2RST                   RCC_APB2RSTR_SAI2RST_Msk

+#define RCC_APB2RSTR_SAI3RST_Pos               (24U)

+#define RCC_APB2RSTR_SAI3RST_Msk               (0x1UL << RCC_APB2RSTR_SAI3RST_Pos) /*!< 0x01000000 */

+#define RCC_APB2RSTR_SAI3RST                   RCC_APB2RSTR_SAI3RST_Msk

+#define RCC_APB2RSTR_DFSDM1RST_Pos             (28U)

+#define RCC_APB2RSTR_DFSDM1RST_Msk             (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */

+#define RCC_APB2RSTR_DFSDM1RST                 RCC_APB2RSTR_DFSDM1RST_Msk

+#define RCC_APB2RSTR_HRTIMRST_Pos              (29U)

+#define RCC_APB2RSTR_HRTIMRST_Msk              (0x1UL << RCC_APB2RSTR_HRTIMRST_Pos) /*!< 0x20000000 */

+#define RCC_APB2RSTR_HRTIMRST                  RCC_APB2RSTR_HRTIMRST_Msk

+

+/********************  Bit definition for RCC_APB4RSTR register  ******************/

+#define RCC_APB4RSTR_SYSCFGRST_Pos             (1U)

+#define RCC_APB4RSTR_SYSCFGRST_Msk             (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */

+#define RCC_APB4RSTR_SYSCFGRST                 RCC_APB4RSTR_SYSCFGRST_Msk

+#define RCC_APB4RSTR_LPUART1RST_Pos            (3U)

+#define RCC_APB4RSTR_LPUART1RST_Msk            (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */

+#define RCC_APB4RSTR_LPUART1RST                RCC_APB4RSTR_LPUART1RST_Msk

+#define RCC_APB4RSTR_SPI6RST_Pos               (5U)

+#define RCC_APB4RSTR_SPI6RST_Msk               (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */

+#define RCC_APB4RSTR_SPI6RST                   RCC_APB4RSTR_SPI6RST_Msk

+#define RCC_APB4RSTR_I2C4RST_Pos               (7U)

+#define RCC_APB4RSTR_I2C4RST_Msk               (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */

+#define RCC_APB4RSTR_I2C4RST                   RCC_APB4RSTR_I2C4RST_Msk

+#define RCC_APB4RSTR_LPTIM2RST_Pos             (9U)

+#define RCC_APB4RSTR_LPTIM2RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */

+#define RCC_APB4RSTR_LPTIM2RST                 RCC_APB4RSTR_LPTIM2RST_Msk

+#define RCC_APB4RSTR_LPTIM3RST_Pos             (10U)

+#define RCC_APB4RSTR_LPTIM3RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */

+#define RCC_APB4RSTR_LPTIM3RST                 RCC_APB4RSTR_LPTIM3RST_Msk

+#define RCC_APB4RSTR_LPTIM4RST_Pos             (11U)

+#define RCC_APB4RSTR_LPTIM4RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos) /*!< 0x00000800 */

+#define RCC_APB4RSTR_LPTIM4RST                 RCC_APB4RSTR_LPTIM4RST_Msk

+#define RCC_APB4RSTR_LPTIM5RST_Pos             (12U)

+#define RCC_APB4RSTR_LPTIM5RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos) /*!< 0x00001000 */

+#define RCC_APB4RSTR_LPTIM5RST                 RCC_APB4RSTR_LPTIM5RST_Msk

+#define RCC_APB4RSTR_COMP12RST_Pos             (14U)

+#define RCC_APB4RSTR_COMP12RST_Msk             (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */

+#define RCC_APB4RSTR_COMP12RST                 RCC_APB4RSTR_COMP12RST_Msk

+#define RCC_APB4RSTR_VREFRST_Pos               (15U)

+#define RCC_APB4RSTR_VREFRST_Msk               (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */

+#define RCC_APB4RSTR_VREFRST                   RCC_APB4RSTR_VREFRST_Msk

+#define RCC_APB4RSTR_SAI4RST_Pos               (21U)

+#define RCC_APB4RSTR_SAI4RST_Msk               (0x1UL << RCC_APB4RSTR_SAI4RST_Pos) /*!< 0x00200000 */

+#define RCC_APB4RSTR_SAI4RST                   RCC_APB4RSTR_SAI4RST_Msk

+

+

+/********************  Bit definition for RCC_GCR register  ********************/

+#define RCC_GCR_WW1RSC_Pos                     (0U)

+#define RCC_GCR_WW1RSC_Msk                     (0x1UL << RCC_GCR_WW1RSC_Pos)   /*!< 0x00000001 */

+#define RCC_GCR_WW1RSC                         RCC_GCR_WW1RSC_Msk

+#define RCC_GCR_WW2RSC_Pos                     (1U)

+#define RCC_GCR_WW2RSC_Msk                     (0x1UL << RCC_GCR_WW2RSC_Pos)   /*!< 0x00000002 */

+#define RCC_GCR_WW2RSC                         RCC_GCR_WW2RSC_Msk

+#define RCC_GCR_BOOT_C1_Pos                    (2U)

+#define RCC_GCR_BOOT_C1_Msk                    (0x1UL << RCC_GCR_BOOT_C1_Pos)  /*!< 0x00000004 */

+#define RCC_GCR_BOOT_C1                        RCC_GCR_BOOT_C1_Msk

+#define RCC_GCR_BOOT_C2_Pos                    (3U)

+#define RCC_GCR_BOOT_C2_Msk                    (0x1UL << RCC_GCR_BOOT_C2_Pos)  /*!< 0x00000008 */

+#define RCC_GCR_BOOT_C2                        RCC_GCR_BOOT_C2_Msk

+

+/********************  Bit definition for RCC_D3AMR register  ********************/

+#define RCC_D3AMR_BDMAAMEN_Pos                 (0U)

+#define RCC_D3AMR_BDMAAMEN_Msk                 (0x1UL << RCC_D3AMR_BDMAAMEN_Pos) /*!< 0x00000001 */

+#define RCC_D3AMR_BDMAAMEN                     RCC_D3AMR_BDMAAMEN_Msk

+#define RCC_D3AMR_LPUART1AMEN_Pos              (3U)

+#define RCC_D3AMR_LPUART1AMEN_Msk              (0x1UL << RCC_D3AMR_LPUART1AMEN_Pos) /*!< 0x00000008 */

+#define RCC_D3AMR_LPUART1AMEN                  RCC_D3AMR_LPUART1AMEN_Msk

+#define RCC_D3AMR_SPI6AMEN_Pos                 (5U)

+#define RCC_D3AMR_SPI6AMEN_Msk                 (0x1UL << RCC_D3AMR_SPI6AMEN_Pos) /*!< 0x00000020 */

+#define RCC_D3AMR_SPI6AMEN                     RCC_D3AMR_SPI6AMEN_Msk

+#define RCC_D3AMR_I2C4AMEN_Pos                 (7U)

+#define RCC_D3AMR_I2C4AMEN_Msk                 (0x1UL << RCC_D3AMR_I2C4AMEN_Pos) /*!< 0x00000080 */

+#define RCC_D3AMR_I2C4AMEN                     RCC_D3AMR_I2C4AMEN_Msk

+#define RCC_D3AMR_LPTIM2AMEN_Pos               (9U)

+#define RCC_D3AMR_LPTIM2AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */

+#define RCC_D3AMR_LPTIM2AMEN                   RCC_D3AMR_LPTIM2AMEN_Msk

+#define RCC_D3AMR_LPTIM3AMEN_Pos               (10U)

+#define RCC_D3AMR_LPTIM3AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */

+#define RCC_D3AMR_LPTIM3AMEN                   RCC_D3AMR_LPTIM3AMEN_Msk

+#define RCC_D3AMR_LPTIM4AMEN_Pos               (11U)

+#define RCC_D3AMR_LPTIM4AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM4AMEN_Pos) /*!< 0x00000800 */

+#define RCC_D3AMR_LPTIM4AMEN                   RCC_D3AMR_LPTIM4AMEN_Msk

+#define RCC_D3AMR_LPTIM5AMEN_Pos               (12U)

+#define RCC_D3AMR_LPTIM5AMEN_Msk               (0x1UL << RCC_D3AMR_LPTIM5AMEN_Pos) /*!< 0x00001000 */

+#define RCC_D3AMR_LPTIM5AMEN                   RCC_D3AMR_LPTIM5AMEN_Msk

+#define RCC_D3AMR_COMP12AMEN_Pos               (14U)

+#define RCC_D3AMR_COMP12AMEN_Msk               (0x1UL << RCC_D3AMR_COMP12AMEN_Pos) /*!< 0x00004000 */

+#define RCC_D3AMR_COMP12AMEN                   RCC_D3AMR_COMP12AMEN_Msk

+#define RCC_D3AMR_VREFAMEN_Pos                 (15U)

+#define RCC_D3AMR_VREFAMEN_Msk                 (0x1UL << RCC_D3AMR_VREFAMEN_Pos) /*!< 0x00008000 */

+#define RCC_D3AMR_VREFAMEN                     RCC_D3AMR_VREFAMEN_Msk

+#define RCC_D3AMR_RTCAMEN_Pos                  (16U)

+#define RCC_D3AMR_RTCAMEN_Msk                  (0x1UL << RCC_D3AMR_RTCAMEN_Pos) /*!< 0x00010000 */

+#define RCC_D3AMR_RTCAMEN                      RCC_D3AMR_RTCAMEN_Msk

+#define RCC_D3AMR_CRCAMEN_Pos                  (19U)

+#define RCC_D3AMR_CRCAMEN_Msk                  (0x1UL << RCC_D3AMR_CRCAMEN_Pos) /*!< 0x00080000 */

+#define RCC_D3AMR_CRCAMEN                      RCC_D3AMR_CRCAMEN_Msk

+#define RCC_D3AMR_SAI4AMEN_Pos                 (21U)

+#define RCC_D3AMR_SAI4AMEN_Msk                 (0x1UL << RCC_D3AMR_SAI4AMEN_Pos) /*!< 0x00200000 */

+#define RCC_D3AMR_SAI4AMEN                     RCC_D3AMR_SAI4AMEN_Msk

+#define RCC_D3AMR_ADC3AMEN_Pos                 (24U)

+#define RCC_D3AMR_ADC3AMEN_Msk                 (0x1UL << RCC_D3AMR_ADC3AMEN_Pos) /*!< 0x01000000 */

+#define RCC_D3AMR_ADC3AMEN                     RCC_D3AMR_ADC3AMEN_Msk

+

+

+#define RCC_D3AMR_BKPRAMAMEN_Pos               (28U)

+#define RCC_D3AMR_BKPRAMAMEN_Msk               (0x1UL << RCC_D3AMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */

+#define RCC_D3AMR_BKPRAMAMEN                   RCC_D3AMR_BKPRAMAMEN_Msk

+#define RCC_D3AMR_SRAM4AMEN_Pos                (29U)

+#define RCC_D3AMR_SRAM4AMEN_Msk                (0x1UL << RCC_D3AMR_SRAM4AMEN_Pos) /*!< 0x20000000 */

+#define RCC_D3AMR_SRAM4AMEN                    RCC_D3AMR_SRAM4AMEN_Msk

+/********************  Bit definition for RCC_AHB3LPENR register  **************/

+#define RCC_AHB3LPENR_MDMALPEN_Pos             (0U)

+#define RCC_AHB3LPENR_MDMALPEN_Msk             (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos)         /*!< 0x00000001 */

+#define RCC_AHB3LPENR_MDMALPEN                 RCC_AHB3LPENR_MDMALPEN_Msk

+#define RCC_AHB3LPENR_DMA2DLPEN_Pos            (4U)

+#define RCC_AHB3LPENR_DMA2DLPEN_Msk            (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos)        /*!< 0x00000010 */

+#define RCC_AHB3LPENR_DMA2DLPEN                RCC_AHB3LPENR_DMA2DLPEN_Msk

+#define RCC_AHB3LPENR_JPGDECLPEN_Pos           (5U)

+#define RCC_AHB3LPENR_JPGDECLPEN_Msk           (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos)       /*!< 0x00000020 */

+#define RCC_AHB3LPENR_JPGDECLPEN               RCC_AHB3LPENR_JPGDECLPEN_Msk

+#define RCC_AHB3LPENR_FLASHLPEN_Pos            (8U)

+#define RCC_AHB3LPENR_FLASHLPEN_Msk            (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos)        /*!< 0x00000100 */

+#define RCC_AHB3LPENR_FLASHLPEN                RCC_AHB3LPENR_FLASHLPEN_Msk

+#define RCC_AHB3LPENR_FMCLPEN_Pos              (12U)

+#define RCC_AHB3LPENR_FMCLPEN_Msk              (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)          /*!< 0x00001000 */

+#define RCC_AHB3LPENR_FMCLPEN                  RCC_AHB3LPENR_FMCLPEN_Msk

+#define RCC_AHB3LPENR_QSPILPEN_Pos             (14U)

+#define RCC_AHB3LPENR_QSPILPEN_Msk             (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos)         /*!< 0x00004000 */

+#define RCC_AHB3LPENR_QSPILPEN                 RCC_AHB3LPENR_QSPILPEN_Msk

+#define RCC_AHB3LPENR_SDMMC1LPEN_Pos           (16U)

+#define RCC_AHB3LPENR_SDMMC1LPEN_Msk           (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos)       /*!< 0x00010000 */

+#define RCC_AHB3LPENR_SDMMC1LPEN               RCC_AHB3LPENR_SDMMC1LPEN_Msk

+#define RCC_AHB3LPENR_DTCM1LPEN_Pos            (28U)

+#define RCC_AHB3LPENR_DTCM1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos)        /*!< 0x10000000 */

+#define RCC_AHB3LPENR_DTCM1LPEN                RCC_AHB3LPENR_DTCM1LPEN_Msk

+#define RCC_AHB3LPENR_DTCM2LPEN_Pos            (29U)

+#define RCC_AHB3LPENR_DTCM2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos)        /*!< 0x20000000 */

+#define RCC_AHB3LPENR_DTCM2LPEN                RCC_AHB3LPENR_DTCM2LPEN_Msk

+#define RCC_AHB3LPENR_ITCMLPEN_Pos             (30U)

+#define RCC_AHB3LPENR_ITCMLPEN_Msk             (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos)         /*!< 0x40000000 */

+#define RCC_AHB3LPENR_ITCMLPEN                 RCC_AHB3LPENR_ITCMLPEN_Msk

+#define RCC_AHB3LPENR_AXISRAMLPEN_Pos          (31U)

+#define RCC_AHB3LPENR_AXISRAMLPEN_Msk          (0x1UL << RCC_AHB3LPENR_AXISRAMLPEN_Pos)      /*!< 0x80000000 */

+#define RCC_AHB3LPENR_AXISRAMLPEN              RCC_AHB3LPENR_AXISRAMLPEN_Msk

+

+

+/********************  Bit definition for RCC_AHB1LPENR register  ***************/

+#define RCC_AHB1LPENR_DMA1LPEN_Pos             (0U)

+#define RCC_AHB1LPENR_DMA1LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB1LPENR_DMA1LPEN                 RCC_AHB1LPENR_DMA1LPEN_Msk

+#define RCC_AHB1LPENR_DMA2LPEN_Pos             (1U)

+#define RCC_AHB1LPENR_DMA2LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */

+#define RCC_AHB1LPENR_DMA2LPEN                 RCC_AHB1LPENR_DMA2LPEN_Msk

+#define RCC_AHB1LPENR_ADC12LPEN_Pos            (5U)

+#define RCC_AHB1LPENR_ADC12LPEN_Msk            (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB1LPENR_ADC12LPEN                RCC_AHB1LPENR_ADC12LPEN_Msk

+#define RCC_AHB1LPENR_ARTLPEN_Pos              (14U)

+#define RCC_AHB1LPENR_ARTLPEN_Msk              (0x1UL << RCC_AHB1LPENR_ARTLPEN_Pos) /*!< 0x00004000 */

+#define RCC_AHB1LPENR_ARTLPEN                  RCC_AHB1LPENR_ARTLPEN_Msk

+#define RCC_AHB1LPENR_ETH1MACLPEN_Pos          (15U)

+#define RCC_AHB1LPENR_ETH1MACLPEN_Msk          (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) /*!< 0x00008000 */

+#define RCC_AHB1LPENR_ETH1MACLPEN              RCC_AHB1LPENR_ETH1MACLPEN_Msk

+#define RCC_AHB1LPENR_ETH1TXLPEN_Pos           (16U)

+#define RCC_AHB1LPENR_ETH1TXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00010000 */

+#define RCC_AHB1LPENR_ETH1TXLPEN               RCC_AHB1LPENR_ETH1TXLPEN_Msk

+#define RCC_AHB1LPENR_ETH1RXLPEN_Pos           (17U)

+#define RCC_AHB1LPENR_ETH1RXLPEN_Msk           (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00020000 */

+#define RCC_AHB1LPENR_ETH1RXLPEN               RCC_AHB1LPENR_ETH1RXLPEN_Msk

+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos        (25U)

+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */

+#define RCC_AHB1LPENR_USB1OTGHSLPEN            RCC_AHB1LPENR_USB1OTGHSLPEN_Msk

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos    (26U)

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN        RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGFSLPEN_Pos        (27U)

+#define RCC_AHB1LPENR_USB2OTGFSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB2OTGFSLPEN_Pos) /*!< 0x08000000 */

+#define RCC_AHB1LPENR_USB2OTGFSLPEN            RCC_AHB1LPENR_USB2OTGFSLPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos    (28U)

+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos) /*!< 0x10000000 */

+#define RCC_AHB1LPENR_USB2OTGFSULPILPEN        RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk

+

+/* Legacy define */

+#define RCC_AHB1LPENR_USB2OTGHSLPEN_Pos        RCC_AHB1LPENR_USB2OTGFSLPEN_Pos

+#define RCC_AHB1LPENR_USB2OTGHSLPEN_Msk        RCC_AHB1LPENR_USB2OTGFSLPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGHSLPEN            RCC_AHB1LPENR_USB2OTGFSLPEN

+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Pos    RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos

+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Msk    RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk

+#define RCC_AHB1LPENR_USB2OTGHSULPILPEN        RCC_AHB1LPENR_USB2OTGFSULPILPEN

+

+/********************  Bit definition for RCC_AHB2LPENR register  ***************/

+#define RCC_AHB2LPENR_DCMILPEN_Pos             (0U)

+#define RCC_AHB2LPENR_DCMILPEN_Msk             (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB2LPENR_DCMILPEN                 RCC_AHB2LPENR_DCMILPEN_Msk

+#define RCC_AHB2LPENR_CRYPLPEN_Pos             (4U)

+#define RCC_AHB2LPENR_CRYPLPEN_Msk             (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */

+#define RCC_AHB2LPENR_CRYPLPEN                 RCC_AHB2LPENR_CRYPLPEN_Msk

+#define RCC_AHB2LPENR_HASHLPEN_Pos             (5U)

+#define RCC_AHB2LPENR_HASHLPEN_Msk             (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB2LPENR_HASHLPEN                 RCC_AHB2LPENR_HASHLPEN_Msk

+#define RCC_AHB2LPENR_RNGLPEN_Pos              (6U)

+#define RCC_AHB2LPENR_RNGLPEN_Msk              (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */

+#define RCC_AHB2LPENR_RNGLPEN                  RCC_AHB2LPENR_RNGLPEN_Msk

+#define RCC_AHB2LPENR_SDMMC2LPEN_Pos           (9U)

+#define RCC_AHB2LPENR_SDMMC2LPEN_Msk           (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */

+#define RCC_AHB2LPENR_SDMMC2LPEN               RCC_AHB2LPENR_SDMMC2LPEN_Msk

+#define RCC_AHB2LPENR_SRAM1LPEN_Pos          (29U)

+#define RCC_AHB2LPENR_SRAM1LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos) /*!< 0x20000000 */

+#define RCC_AHB2LPENR_SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN_Msk

+#define RCC_AHB2LPENR_SRAM2LPEN_Pos          (30U)

+#define RCC_AHB2LPENR_SRAM2LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */

+#define RCC_AHB2LPENR_SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN_Msk

+#define RCC_AHB2LPENR_SRAM3LPEN_Pos          (31U)

+#define RCC_AHB2LPENR_SRAM3LPEN_Msk          (0x1UL << RCC_AHB2LPENR_SRAM3LPEN_Pos) /*!< 0x80000000 */

+#define RCC_AHB2LPENR_SRAM3LPEN              RCC_AHB2LPENR_SRAM3LPEN_Msk

+

+/* Legacy define */

+#define RCC_AHB2LPENR_D2SRAM1LPEN_Pos          RCC_AHB2LPENR_SRAM1LPEN_Pos

+#define RCC_AHB2LPENR_D2SRAM1LPEN_Msk          RCC_AHB2LPENR_SRAM1LPEN_Msk

+#define RCC_AHB2LPENR_D2SRAM1LPEN              RCC_AHB2LPENR_SRAM1LPEN

+#define RCC_AHB2LPENR_D2SRAM2LPEN_Pos          RCC_AHB2LPENR_SRAM2LPEN_Pos

+#define RCC_AHB2LPENR_D2SRAM2LPEN_Msk          RCC_AHB2LPENR_SRAM2LPEN_Msk

+#define RCC_AHB2LPENR_D2SRAM2LPEN              RCC_AHB2LPENR_SRAM2LPEN

+#define RCC_AHB2LPENR_D2SRAM3LPEN_Pos          RCC_AHB2LPENR_SRAM3LPEN_Pos

+#define RCC_AHB2LPENR_D2SRAM3LPEN_Msk          RCC_AHB2LPENR_SRAM3LPEN_Msk

+#define RCC_AHB2LPENR_D2SRAM3LPEN              RCC_AHB2LPENR_SRAM3LPEN

+

+/********************  Bit definition for RCC_AHB4LPENR register  ******************/

+#define RCC_AHB4LPENR_GPIOALPEN_Pos            (0U)

+#define RCC_AHB4LPENR_GPIOALPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB4LPENR_GPIOALPEN                RCC_AHB4LPENR_GPIOALPEN_Msk

+#define RCC_AHB4LPENR_GPIOBLPEN_Pos            (1U)

+#define RCC_AHB4LPENR_GPIOBLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */

+#define RCC_AHB4LPENR_GPIOBLPEN                RCC_AHB4LPENR_GPIOBLPEN_Msk

+#define RCC_AHB4LPENR_GPIOCLPEN_Pos            (2U)

+#define RCC_AHB4LPENR_GPIOCLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */

+#define RCC_AHB4LPENR_GPIOCLPEN                RCC_AHB4LPENR_GPIOCLPEN_Msk

+#define RCC_AHB4LPENR_GPIODLPEN_Pos            (3U)

+#define RCC_AHB4LPENR_GPIODLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */

+#define RCC_AHB4LPENR_GPIODLPEN                RCC_AHB4LPENR_GPIODLPEN_Msk

+#define RCC_AHB4LPENR_GPIOELPEN_Pos            (4U)

+#define RCC_AHB4LPENR_GPIOELPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */

+#define RCC_AHB4LPENR_GPIOELPEN                RCC_AHB4LPENR_GPIOELPEN_Msk

+#define RCC_AHB4LPENR_GPIOFLPEN_Pos            (5U)

+#define RCC_AHB4LPENR_GPIOFLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB4LPENR_GPIOFLPEN                RCC_AHB4LPENR_GPIOFLPEN_Msk

+#define RCC_AHB4LPENR_GPIOGLPEN_Pos            (6U)

+#define RCC_AHB4LPENR_GPIOGLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */

+#define RCC_AHB4LPENR_GPIOGLPEN                RCC_AHB4LPENR_GPIOGLPEN_Msk

+#define RCC_AHB4LPENR_GPIOHLPEN_Pos            (7U)

+#define RCC_AHB4LPENR_GPIOHLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */

+#define RCC_AHB4LPENR_GPIOHLPEN                RCC_AHB4LPENR_GPIOHLPEN_Msk

+#define RCC_AHB4LPENR_GPIOILPEN_Pos            (8U)

+#define RCC_AHB4LPENR_GPIOILPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */

+#define RCC_AHB4LPENR_GPIOILPEN                RCC_AHB4LPENR_GPIOILPEN_Msk

+#define RCC_AHB4LPENR_GPIOJLPEN_Pos            (9U)

+#define RCC_AHB4LPENR_GPIOJLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */

+#define RCC_AHB4LPENR_GPIOJLPEN                RCC_AHB4LPENR_GPIOJLPEN_Msk

+#define RCC_AHB4LPENR_GPIOKLPEN_Pos            (10U)

+#define RCC_AHB4LPENR_GPIOKLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */

+#define RCC_AHB4LPENR_GPIOKLPEN                RCC_AHB4LPENR_GPIOKLPEN_Msk

+#define RCC_AHB4LPENR_CRCLPEN_Pos              (19U)

+#define RCC_AHB4LPENR_CRCLPEN_Msk              (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */

+#define RCC_AHB4LPENR_CRCLPEN                  RCC_AHB4LPENR_CRCLPEN_Msk

+#define RCC_AHB4LPENR_BDMALPEN_Pos             (21U)

+#define RCC_AHB4LPENR_BDMALPEN_Msk             (0x1UL << RCC_AHB4LPENR_BDMALPEN_Pos) /*!< 0x00200000 */

+#define RCC_AHB4LPENR_BDMALPEN                 RCC_AHB4LPENR_BDMALPEN_Msk

+#define RCC_AHB4LPENR_ADC3LPEN_Pos             (24U)

+#define RCC_AHB4LPENR_ADC3LPEN_Msk             (0x1UL << RCC_AHB4LPENR_ADC3LPEN_Pos) /*!< 0x01000000 */

+#define RCC_AHB4LPENR_ADC3LPEN                 RCC_AHB4LPENR_ADC3LPEN_Msk

+#define RCC_AHB4LPENR_BKPRAMLPEN_Pos           (28U)

+#define RCC_AHB4LPENR_BKPRAMLPEN_Msk           (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */

+#define RCC_AHB4LPENR_BKPRAMLPEN               RCC_AHB4LPENR_BKPRAMLPEN_Msk

+#define RCC_AHB4LPENR_SRAM4LPEN_Pos            (29U)

+#define RCC_AHB4LPENR_SRAM4LPEN_Msk            (0x1UL << RCC_AHB4LPENR_SRAM4LPEN_Pos) /*!< 0x20000000 */

+#define RCC_AHB4LPENR_SRAM4LPEN                RCC_AHB4LPENR_SRAM4LPEN_Msk

+

+/* Legacy define */

+#define RCC_AHB4LPENR_D3SRAM1LPEN_Pos          RCC_AHB4LPENR_SRAM4LPEN_Pos

+#define RCC_AHB4LPENR_D3SRAM1LPEN_Msk          RCC_AHB4LPENR_SRAM4LPEN_Msk

+#define RCC_AHB4LPENR_D3SRAM1LPEN              RCC_AHB4LPENR_SRAM4LPEN

+/********************  Bit definition for RCC_APB3LPENR register  ******************/

+#define RCC_APB3LPENR_LTDCLPEN_Pos             (3U)

+#define RCC_APB3LPENR_LTDCLPEN_Msk             (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB3LPENR_LTDCLPEN                 RCC_APB3LPENR_LTDCLPEN_Msk

+#define RCC_APB3LPENR_DSILPEN_Pos              (4U)

+#define RCC_APB3LPENR_DSILPEN_Msk              (0x1UL << RCC_APB3LPENR_DSILPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB3LPENR_DSILPEN                  RCC_APB3LPENR_DSILPEN_Msk

+#define RCC_APB3LPENR_WWDG1LPEN_Pos            (6U)

+#define RCC_APB3LPENR_WWDG1LPEN_Msk            (0x1UL << RCC_APB3LPENR_WWDG1LPEN_Pos) /*!< 0x00000040 */

+#define RCC_APB3LPENR_WWDG1LPEN                RCC_APB3LPENR_WWDG1LPEN_Msk

+

+/********************  Bit definition for RCC_APB1LLPENR register  ******************/

+

+#define RCC_APB1LLPENR_TIM2LPEN_Pos            (0U)

+#define RCC_APB1LLPENR_TIM2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */

+#define RCC_APB1LLPENR_TIM2LPEN                RCC_APB1LLPENR_TIM2LPEN_Msk

+#define RCC_APB1LLPENR_TIM3LPEN_Pos            (1U)

+#define RCC_APB1LLPENR_TIM3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1LLPENR_TIM3LPEN                RCC_APB1LLPENR_TIM3LPEN_Msk

+#define RCC_APB1LLPENR_TIM4LPEN_Pos            (2U)

+#define RCC_APB1LLPENR_TIM4LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1LLPENR_TIM4LPEN                RCC_APB1LLPENR_TIM4LPEN_Msk

+#define RCC_APB1LLPENR_TIM5LPEN_Pos            (3U)

+#define RCC_APB1LLPENR_TIM5LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB1LLPENR_TIM5LPEN                RCC_APB1LLPENR_TIM5LPEN_Msk

+#define RCC_APB1LLPENR_TIM6LPEN_Pos            (4U)

+#define RCC_APB1LLPENR_TIM6LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1LLPENR_TIM6LPEN                RCC_APB1LLPENR_TIM6LPEN_Msk

+#define RCC_APB1LLPENR_TIM7LPEN_Pos            (5U)

+#define RCC_APB1LLPENR_TIM7LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1LLPENR_TIM7LPEN                RCC_APB1LLPENR_TIM7LPEN_Msk

+#define RCC_APB1LLPENR_TIM12LPEN_Pos           (6U)

+#define RCC_APB1LLPENR_TIM12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */

+#define RCC_APB1LLPENR_TIM12LPEN               RCC_APB1LLPENR_TIM12LPEN_Msk

+#define RCC_APB1LLPENR_TIM13LPEN_Pos           (7U)

+#define RCC_APB1LLPENR_TIM13LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB1LLPENR_TIM13LPEN               RCC_APB1LLPENR_TIM13LPEN_Msk

+#define RCC_APB1LLPENR_TIM14LPEN_Pos           (8U)

+#define RCC_APB1LLPENR_TIM14LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1LLPENR_TIM14LPEN               RCC_APB1LLPENR_TIM14LPEN_Msk

+#define RCC_APB1LLPENR_LPTIM1LPEN_Pos          (9U)

+#define RCC_APB1LLPENR_LPTIM1LPEN_Msk          (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */

+#define RCC_APB1LLPENR_LPTIM1LPEN              RCC_APB1LLPENR_LPTIM1LPEN_Msk

+

+#define RCC_APB1LLPENR_WWDG2LPEN_Pos           (11U)

+#define RCC_APB1LLPENR_WWDG2LPEN_Msk           (0x1UL << RCC_APB1LLPENR_WWDG2LPEN_Pos) /*!< 0x00000800 */

+#define RCC_APB1LLPENR_WWDG2LPEN               RCC_APB1LLPENR_WWDG2LPEN_Msk

+

+#define RCC_APB1LLPENR_SPI2LPEN_Pos            (14U)

+#define RCC_APB1LLPENR_SPI2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */

+#define RCC_APB1LLPENR_SPI2LPEN                RCC_APB1LLPENR_SPI2LPEN_Msk

+#define RCC_APB1LLPENR_SPI3LPEN_Pos            (15U)

+#define RCC_APB1LLPENR_SPI3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */

+#define RCC_APB1LLPENR_SPI3LPEN                RCC_APB1LLPENR_SPI3LPEN_Msk

+#define RCC_APB1LLPENR_SPDIFRXLPEN_Pos         (16U)

+#define RCC_APB1LLPENR_SPDIFRXLPEN_Msk         (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB1LLPENR_SPDIFRXLPEN             RCC_APB1LLPENR_SPDIFRXLPEN_Msk

+#define RCC_APB1LLPENR_USART2LPEN_Pos          (17U)

+#define RCC_APB1LLPENR_USART2LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */

+#define RCC_APB1LLPENR_USART2LPEN              RCC_APB1LLPENR_USART2LPEN_Msk

+#define RCC_APB1LLPENR_USART3LPEN_Pos          (18U)

+#define RCC_APB1LLPENR_USART3LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */

+#define RCC_APB1LLPENR_USART3LPEN              RCC_APB1LLPENR_USART3LPEN_Msk

+#define RCC_APB1LLPENR_UART4LPEN_Pos           (19U)

+#define RCC_APB1LLPENR_UART4LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */

+#define RCC_APB1LLPENR_UART4LPEN               RCC_APB1LLPENR_UART4LPEN_Msk

+#define RCC_APB1LLPENR_UART5LPEN_Pos           (20U)

+#define RCC_APB1LLPENR_UART5LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */

+#define RCC_APB1LLPENR_UART5LPEN               RCC_APB1LLPENR_UART5LPEN_Msk

+#define RCC_APB1LLPENR_I2C1LPEN_Pos            (21U)

+#define RCC_APB1LLPENR_I2C1LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */

+#define RCC_APB1LLPENR_I2C1LPEN                RCC_APB1LLPENR_I2C1LPEN_Msk

+#define RCC_APB1LLPENR_I2C2LPEN_Pos            (22U)

+#define RCC_APB1LLPENR_I2C2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */

+#define RCC_APB1LLPENR_I2C2LPEN                RCC_APB1LLPENR_I2C2LPEN_Msk

+#define RCC_APB1LLPENR_I2C3LPEN_Pos            (23U)

+#define RCC_APB1LLPENR_I2C3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */

+#define RCC_APB1LLPENR_I2C3LPEN                RCC_APB1LLPENR_I2C3LPEN_Msk

+#define RCC_APB1LLPENR_CECLPEN_Pos             (27U)

+#define RCC_APB1LLPENR_CECLPEN_Msk             (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */

+#define RCC_APB1LLPENR_CECLPEN                 RCC_APB1LLPENR_CECLPEN_Msk

+#define RCC_APB1LLPENR_DAC12LPEN_Pos           (29U)

+#define RCC_APB1LLPENR_DAC12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */

+#define RCC_APB1LLPENR_DAC12LPEN               RCC_APB1LLPENR_DAC12LPEN_Msk

+#define RCC_APB1LLPENR_UART7LPEN_Pos           (30U)

+#define RCC_APB1LLPENR_UART7LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */

+#define RCC_APB1LLPENR_UART7LPEN               RCC_APB1LLPENR_UART7LPEN_Msk

+#define RCC_APB1LLPENR_UART8LPEN_Pos           (31U)

+#define RCC_APB1LLPENR_UART8LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */

+#define RCC_APB1LLPENR_UART8LPEN               RCC_APB1LLPENR_UART8LPEN_Msk

+

+/* Legacy define */

+#define RCC_APB1LLPENR_HDMICECEN_Pos           RCC_APB1LLPENR_CECLPEN_Pos

+#define RCC_APB1LLPENR_HDMICECEN_Msk           RCC_APB1LLPENR_CECLPEN_Msk

+#define RCC_APB1LLPENR_HDMICECEN               RCC_APB1LLPENR_CECLPEN

+/********************  Bit definition for RCC_APB1HLPENR register  ******************/

+#define RCC_APB1HLPENR_CRSLPEN_Pos             (1U)

+#define RCC_APB1HLPENR_CRSLPEN_Msk             (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1HLPENR_CRSLPEN                 RCC_APB1HLPENR_CRSLPEN_Msk

+#define RCC_APB1HLPENR_SWPMILPEN_Pos           (2U)

+#define RCC_APB1HLPENR_SWPMILPEN_Msk           (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1HLPENR_SWPMILPEN               RCC_APB1HLPENR_SWPMILPEN_Msk

+#define RCC_APB1HLPENR_OPAMPLPEN_Pos           (4U)

+#define RCC_APB1HLPENR_OPAMPLPEN_Msk           (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1HLPENR_OPAMPLPEN               RCC_APB1HLPENR_OPAMPLPEN_Msk

+#define RCC_APB1HLPENR_MDIOSLPEN_Pos           (5U)

+#define RCC_APB1HLPENR_MDIOSLPEN_Msk           (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1HLPENR_MDIOSLPEN               RCC_APB1HLPENR_MDIOSLPEN_Msk

+#define RCC_APB1HLPENR_FDCANLPEN_Pos           (8U)

+#define RCC_APB1HLPENR_FDCANLPEN_Msk           (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1HLPENR_FDCANLPEN               RCC_APB1HLPENR_FDCANLPEN_Msk

+

+/********************  Bit definition for RCC_APB2LPENR register  ******************/

+#define RCC_APB2LPENR_TIM1LPEN_Pos             (0U)

+#define RCC_APB2LPENR_TIM1LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */

+#define RCC_APB2LPENR_TIM1LPEN                 RCC_APB2LPENR_TIM1LPEN_Msk

+#define RCC_APB2LPENR_TIM8LPEN_Pos             (1U)

+#define RCC_APB2LPENR_TIM8LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB2LPENR_TIM8LPEN                 RCC_APB2LPENR_TIM8LPEN_Msk

+#define RCC_APB2LPENR_USART1LPEN_Pos           (4U)

+#define RCC_APB2LPENR_USART1LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB2LPENR_USART1LPEN               RCC_APB2LPENR_USART1LPEN_Msk

+#define RCC_APB2LPENR_USART6LPEN_Pos           (5U)

+#define RCC_APB2LPENR_USART6LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB2LPENR_USART6LPEN               RCC_APB2LPENR_USART6LPEN_Msk

+#define RCC_APB2LPENR_SPI1LPEN_Pos             (12U)

+#define RCC_APB2LPENR_SPI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */

+#define RCC_APB2LPENR_SPI1LPEN                 RCC_APB2LPENR_SPI1LPEN_Msk

+#define RCC_APB2LPENR_SPI4LPEN_Pos             (13U)

+#define RCC_APB2LPENR_SPI4LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */

+#define RCC_APB2LPENR_SPI4LPEN                 RCC_APB2LPENR_SPI4LPEN_Msk

+#define RCC_APB2LPENR_TIM15LPEN_Pos            (16U)

+#define RCC_APB2LPENR_TIM15LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB2LPENR_TIM15LPEN                RCC_APB2LPENR_TIM15LPEN_Msk

+#define RCC_APB2LPENR_TIM16LPEN_Pos            (17U)

+#define RCC_APB2LPENR_TIM16LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */

+#define RCC_APB2LPENR_TIM16LPEN                RCC_APB2LPENR_TIM16LPEN_Msk

+#define RCC_APB2LPENR_TIM17LPEN_Pos            (18U)

+#define RCC_APB2LPENR_TIM17LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */

+#define RCC_APB2LPENR_TIM17LPEN                RCC_APB2LPENR_TIM17LPEN_Msk

+#define RCC_APB2LPENR_SPI5LPEN_Pos             (20U)

+#define RCC_APB2LPENR_SPI5LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */

+#define RCC_APB2LPENR_SPI5LPEN                 RCC_APB2LPENR_SPI5LPEN_Msk

+#define RCC_APB2LPENR_SAI1LPEN_Pos             (22U)

+#define RCC_APB2LPENR_SAI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */

+#define RCC_APB2LPENR_SAI1LPEN                 RCC_APB2LPENR_SAI1LPEN_Msk

+#define RCC_APB2LPENR_SAI2LPEN_Pos             (23U)

+#define RCC_APB2LPENR_SAI2LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */

+#define RCC_APB2LPENR_SAI2LPEN                 RCC_APB2LPENR_SAI2LPEN_Msk

+#define RCC_APB2LPENR_SAI3LPEN_Pos             (24U)

+#define RCC_APB2LPENR_SAI3LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI3LPEN_Pos) /*!< 0x01000000 */

+#define RCC_APB2LPENR_SAI3LPEN                 RCC_APB2LPENR_SAI3LPEN_Msk

+#define RCC_APB2LPENR_DFSDM1LPEN_Pos           (28U)

+#define RCC_APB2LPENR_DFSDM1LPEN_Msk           (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x10000000 */

+#define RCC_APB2LPENR_DFSDM1LPEN               RCC_APB2LPENR_DFSDM1LPEN_Msk

+#define RCC_APB2LPENR_HRTIMLPEN_Pos            (29U)

+#define RCC_APB2LPENR_HRTIMLPEN_Msk            (0x1UL << RCC_APB2LPENR_HRTIMLPEN_Pos) /*!< 0x20000000 */

+#define RCC_APB2LPENR_HRTIMLPEN                RCC_APB2LPENR_HRTIMLPEN_Msk

+

+/********************  Bit definition for RCC_APB4LPENR register  ******************/

+#define RCC_APB4LPENR_SYSCFGLPEN_Pos           (1U)

+#define RCC_APB4LPENR_SYSCFGLPEN_Msk           (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB4LPENR_SYSCFGLPEN               RCC_APB4LPENR_SYSCFGLPEN_Msk

+#define RCC_APB4LPENR_LPUART1LPEN_Pos          (3U)

+#define RCC_APB4LPENR_LPUART1LPEN_Msk          (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB4LPENR_LPUART1LPEN              RCC_APB4LPENR_LPUART1LPEN_Msk

+#define RCC_APB4LPENR_SPI6LPEN_Pos             (5U)

+#define RCC_APB4LPENR_SPI6LPEN_Msk             (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB4LPENR_SPI6LPEN                 RCC_APB4LPENR_SPI6LPEN_Msk

+#define RCC_APB4LPENR_I2C4LPEN_Pos             (7U)

+#define RCC_APB4LPENR_I2C4LPEN_Msk             (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB4LPENR_I2C4LPEN                 RCC_APB4LPENR_I2C4LPEN_Msk

+#define RCC_APB4LPENR_LPTIM2LPEN_Pos           (9U)

+#define RCC_APB4LPENR_LPTIM2LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */

+#define RCC_APB4LPENR_LPTIM2LPEN               RCC_APB4LPENR_LPTIM2LPEN_Msk

+#define RCC_APB4LPENR_LPTIM3LPEN_Pos           (10U)

+#define RCC_APB4LPENR_LPTIM3LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */

+#define RCC_APB4LPENR_LPTIM3LPEN               RCC_APB4LPENR_LPTIM3LPEN_Msk

+#define RCC_APB4LPENR_LPTIM4LPEN_Pos           (11U)

+#define RCC_APB4LPENR_LPTIM4LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) /*!< 0x00000800 */

+#define RCC_APB4LPENR_LPTIM4LPEN               RCC_APB4LPENR_LPTIM4LPEN_Msk

+#define RCC_APB4LPENR_LPTIM5LPEN_Pos           (12U)

+#define RCC_APB4LPENR_LPTIM5LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) /*!< 0x00001000 */

+#define RCC_APB4LPENR_LPTIM5LPEN               RCC_APB4LPENR_LPTIM5LPEN_Msk

+#define RCC_APB4LPENR_COMP12LPEN_Pos           (14U)

+#define RCC_APB4LPENR_COMP12LPEN_Msk           (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */

+#define RCC_APB4LPENR_COMP12LPEN               RCC_APB4LPENR_COMP12LPEN_Msk

+#define RCC_APB4LPENR_VREFLPEN_Pos             (15U)

+#define RCC_APB4LPENR_VREFLPEN_Msk             (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */

+#define RCC_APB4LPENR_VREFLPEN                 RCC_APB4LPENR_VREFLPEN_Msk

+#define RCC_APB4LPENR_RTCAPBLPEN_Pos           (16U)

+#define RCC_APB4LPENR_RTCAPBLPEN_Msk           (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB4LPENR_RTCAPBLPEN               RCC_APB4LPENR_RTCAPBLPEN_Msk

+#define RCC_APB4LPENR_SAI4LPEN_Pos             (21U)

+#define RCC_APB4LPENR_SAI4LPEN_Msk             (0x1UL << RCC_APB4LPENR_SAI4LPEN_Pos) /*!< 0x00200000 */

+#define RCC_APB4LPENR_SAI4LPEN                 RCC_APB4LPENR_SAI4LPEN_Msk

+

+/********************  Bit definition for RCC_D1CCIPR register  ****************/

+#define RCC_D1CCIPR_DSISRC_Pos                 (8U)

+#define RCC_D1CCIPR_DSISRC_Msk                 (0x1UL << RCC_D1CCIPR_DSISRC_Pos) /*!< 0x00000100 */

+#define RCC_D1CCIPR_DSISRC                     RCC_D1CCIPR_DSISRC_Msk

+

+/********************  Bit definition for RCC_RSR register  *******************/

+#define RCC_RSR_RMVF_Pos                       (16U)

+#define RCC_RSR_RMVF_Msk                       (0x1UL << RCC_RSR_RMVF_Pos)     /*!< 0x00010000 */

+#define RCC_RSR_RMVF                           RCC_RSR_RMVF_Msk

+#define RCC_RSR_C1RSTF_Pos                     (17U)

+#define RCC_RSR_C1RSTF_Msk                     (0x1UL << RCC_RSR_C1RSTF_Pos)   /*!< 0x00020000 */

+#define RCC_RSR_C1RSTF                         RCC_RSR_C1RSTF_Msk

+#define RCC_RSR_D1RSTF_Pos                     (19U)

+#define RCC_RSR_D1RSTF_Msk                     (0x1UL << RCC_RSR_D1RSTF_Pos)   /*!< 0x00080000 */

+#define RCC_RSR_D1RSTF                         RCC_RSR_D1RSTF_Msk

+#define RCC_RSR_D2RSTF_Pos                     (20U)

+#define RCC_RSR_D2RSTF_Msk                     (0x1UL << RCC_RSR_D2RSTF_Pos)   /*!< 0x00100000 */

+#define RCC_RSR_D2RSTF                         RCC_RSR_D2RSTF_Msk

+#define RCC_RSR_BORRSTF_Pos                    (21U)

+#define RCC_RSR_BORRSTF_Msk                    (0x1UL << RCC_RSR_BORRSTF_Pos)  /*!< 0x00200000 */

+#define RCC_RSR_BORRSTF                        RCC_RSR_BORRSTF_Msk

+#define RCC_RSR_PINRSTF_Pos                    (22U)

+#define RCC_RSR_PINRSTF_Msk                    (0x1UL << RCC_RSR_PINRSTF_Pos)  /*!< 0x00400000 */

+#define RCC_RSR_PINRSTF                        RCC_RSR_PINRSTF_Msk

+#define RCC_RSR_PORRSTF_Pos                    (23U)

+#define RCC_RSR_PORRSTF_Msk                    (0x1UL << RCC_RSR_PORRSTF_Pos)  /*!< 0x00800000 */

+#define RCC_RSR_PORRSTF                        RCC_RSR_PORRSTF_Msk

+#define RCC_RSR_SFT1RSTF_Pos                   (24U)

+#define RCC_RSR_SFT1RSTF_Msk                   (0x1UL << RCC_RSR_SFT1RSTF_Pos) /*!< 0x01000000 */

+#define RCC_RSR_SFT1RSTF                       RCC_RSR_SFT1RSTF_Msk

+#define RCC_RSR_IWDG1RSTF_Pos                  (26U)

+#define RCC_RSR_IWDG1RSTF_Msk                  (0x1UL << RCC_RSR_IWDG1RSTF_Pos) /*!< 0x04000000 */

+#define RCC_RSR_IWDG1RSTF                      RCC_RSR_IWDG1RSTF_Msk

+#define RCC_RSR_WWDG1RSTF_Pos                  (28U)

+#define RCC_RSR_WWDG1RSTF_Msk                  (0x1UL << RCC_RSR_WWDG1RSTF_Pos) /*!< 0x10000000 */

+#define RCC_RSR_WWDG1RSTF                      RCC_RSR_WWDG1RSTF_Msk

+

+#define RCC_RSR_WWDG2RSTF_Pos                  (29U)

+#define RCC_RSR_WWDG2RSTF_Msk                  (0x1UL << RCC_RSR_WWDG2RSTF_Pos) /*!< 0x20000000 */

+#define RCC_RSR_WWDG2RSTF                      RCC_RSR_WWDG2RSTF_Msk

+#define RCC_RSR_IWDG2RSTF_Pos                  (27U)

+#define RCC_RSR_IWDG2RSTF_Msk                  (0x1UL << RCC_RSR_IWDG2RSTF_Pos) /*!< 0x08000000 */

+#define RCC_RSR_IWDG2RSTF                      RCC_RSR_IWDG2RSTF_Msk

+#define RCC_RSR_SFT2RSTF_Pos                   (25U)

+#define RCC_RSR_SFT2RSTF_Msk                   (0x1UL << RCC_RSR_SFT2RSTF_Pos) /*!< 0x02000000 */

+#define RCC_RSR_SFT2RSTF                       RCC_RSR_SFT2RSTF_Msk

+#define RCC_RSR_C2RSTF_Pos                     (18U)

+#define RCC_RSR_C2RSTF_Msk                     (0x1UL << RCC_RSR_C2RSTF_Pos)   /*!< 0x00040000 */

+#define RCC_RSR_C2RSTF                         RCC_RSR_C2RSTF_Msk

+#define RCC_RSR_LPWR1RSTF_Pos                  (30U)

+#define RCC_RSR_LPWR1RSTF_Msk                  (0x1UL << RCC_RSR_LPWR1RSTF_Pos) /*!< 0x40000000 */

+#define RCC_RSR_LPWR1RSTF                      RCC_RSR_LPWR1RSTF_Msk

+#define RCC_RSR_LPWR2RSTF_Pos                  (31U)

+#define RCC_RSR_LPWR2RSTF_Msk                  (0x1UL << RCC_RSR_LPWR2RSTF_Pos) /*!< 0x80000000 */

+#define RCC_RSR_LPWR2RSTF                      RCC_RSR_LPWR2RSTF_Msk

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    RNG                                     */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for RNG_CR register  *******************/

+#define RNG_CR_RNGEN_Pos    (2U)

+#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */

+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk

+#define RNG_CR_IE_Pos       (3U)

+#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */

+#define RNG_CR_IE           RNG_CR_IE_Msk

+#define RNG_CR_CED_Pos      (5U)

+#define RNG_CR_CED_Msk      (0x1UL << RNG_CR_CED_Pos)                          /*!< 0x00000020 */

+#define RNG_CR_CED          RNG_CR_CED_Msk

+

+/********************  Bits definition for RNG_SR register  *******************/

+#define RNG_SR_DRDY_Pos     (0U)

+#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */

+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk

+#define RNG_SR_CECS_Pos     (1U)

+#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */

+#define RNG_SR_CECS         RNG_SR_CECS_Msk

+#define RNG_SR_SECS_Pos     (2U)

+#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */

+#define RNG_SR_SECS         RNG_SR_SECS_Msk

+#define RNG_SR_CEIS_Pos     (5U)

+#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */

+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk

+#define RNG_SR_SEIS_Pos     (6U)

+#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */

+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                           Real-Time Clock (RTC)                            */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for RTC_TR register  *******************/

+#define RTC_TR_PM_Pos                  (22U)

+#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */

+#define RTC_TR_PM                      RTC_TR_PM_Msk

+#define RTC_TR_HT_Pos                  (20U)

+#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */

+#define RTC_TR_HT                      RTC_TR_HT_Msk

+#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */

+#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */

+#define RTC_TR_HU_Pos                  (16U)

+#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */

+#define RTC_TR_HU                      RTC_TR_HU_Msk

+#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */

+#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */

+#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */

+#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */

+#define RTC_TR_MNT_Pos                 (12U)

+#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */

+#define RTC_TR_MNT                     RTC_TR_MNT_Msk

+#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */

+#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */

+#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */

+#define RTC_TR_MNU_Pos                 (8U)

+#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */

+#define RTC_TR_MNU                     RTC_TR_MNU_Msk

+#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */

+#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */

+#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */

+#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */

+#define RTC_TR_ST_Pos                  (4U)

+#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */

+#define RTC_TR_ST                      RTC_TR_ST_Msk

+#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */

+#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */

+#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */

+#define RTC_TR_SU_Pos                  (0U)

+#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */

+#define RTC_TR_SU                      RTC_TR_SU_Msk

+#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */

+#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */

+#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */

+#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_DR register  *******************/

+#define RTC_DR_YT_Pos                  (20U)

+#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */

+#define RTC_DR_YT                      RTC_DR_YT_Msk

+#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */

+#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */

+#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */

+#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */

+#define RTC_DR_YU_Pos                  (16U)

+#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */

+#define RTC_DR_YU                      RTC_DR_YU_Msk

+#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */

+#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */

+#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */

+#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */

+#define RTC_DR_WDU_Pos                 (13U)

+#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */

+#define RTC_DR_WDU                     RTC_DR_WDU_Msk

+#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */

+#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */

+#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */

+#define RTC_DR_MT_Pos                  (12U)

+#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */

+#define RTC_DR_MT                      RTC_DR_MT_Msk

+#define RTC_DR_MU_Pos                  (8U)

+#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */

+#define RTC_DR_MU                      RTC_DR_MU_Msk

+#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */

+#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */

+#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */

+#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */

+#define RTC_DR_DT_Pos                  (4U)

+#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */

+#define RTC_DR_DT                      RTC_DR_DT_Msk

+#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */

+#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */

+#define RTC_DR_DU_Pos                  (0U)

+#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */

+#define RTC_DR_DU                      RTC_DR_DU_Msk

+#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */

+#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */

+#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */

+#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_CR register  *******************/

+#define RTC_CR_ITSE_Pos                (24U)

+#define RTC_CR_ITSE_Msk                (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */

+#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk

+#define RTC_CR_COE_Pos                 (23U)

+#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */

+#define RTC_CR_COE                     RTC_CR_COE_Msk

+#define RTC_CR_OSEL_Pos                (21U)

+#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */

+#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk

+#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */

+#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */

+#define RTC_CR_POL_Pos                 (20U)

+#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */

+#define RTC_CR_POL                     RTC_CR_POL_Msk

+#define RTC_CR_COSEL_Pos               (19U)

+#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */

+#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk

+#define RTC_CR_BKP_Pos                 (18U)

+#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */

+#define RTC_CR_BKP                     RTC_CR_BKP_Msk

+#define RTC_CR_SUB1H_Pos               (17U)

+#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */

+#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk

+#define RTC_CR_ADD1H_Pos               (16U)

+#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */

+#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk

+#define RTC_CR_TSIE_Pos                (15U)

+#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */

+#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk

+#define RTC_CR_WUTIE_Pos               (14U)

+#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */

+#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk

+#define RTC_CR_ALRBIE_Pos              (13U)

+#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */

+#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk

+#define RTC_CR_ALRAIE_Pos              (12U)

+#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */

+#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk

+#define RTC_CR_TSE_Pos                 (11U)

+#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */

+#define RTC_CR_TSE                     RTC_CR_TSE_Msk

+#define RTC_CR_WUTE_Pos                (10U)

+#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */

+#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk

+#define RTC_CR_ALRBE_Pos               (9U)

+#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */

+#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk

+#define RTC_CR_ALRAE_Pos               (8U)

+#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */

+#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk

+#define RTC_CR_FMT_Pos                 (6U)

+#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */

+#define RTC_CR_FMT                     RTC_CR_FMT_Msk

+#define RTC_CR_BYPSHAD_Pos             (5U)

+#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */

+#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk

+#define RTC_CR_REFCKON_Pos             (4U)

+#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */

+#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk

+#define RTC_CR_TSEDGE_Pos              (3U)

+#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */

+#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk

+#define RTC_CR_WUCKSEL_Pos             (0U)

+#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */

+#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk

+#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */

+#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */

+#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */

+

+/********************  Bits definition for RTC_ISR register  ******************/

+#define RTC_ISR_ITSF_Pos               (17U)

+#define RTC_ISR_ITSF_Msk               (0x1UL << RTC_ISR_ITSF_Pos)             /*!< 0x00020000 */

+#define RTC_ISR_ITSF                   RTC_ISR_ITSF_Msk

+#define RTC_ISR_RECALPF_Pos            (16U)

+#define RTC_ISR_RECALPF_Msk            (0x1UL << RTC_ISR_RECALPF_Pos)          /*!< 0x00010000 */

+#define RTC_ISR_RECALPF                RTC_ISR_RECALPF_Msk

+#define RTC_ISR_TAMP3F_Pos             (15U)

+#define RTC_ISR_TAMP3F_Msk             (0x1UL << RTC_ISR_TAMP3F_Pos)           /*!< 0x00008000 */

+#define RTC_ISR_TAMP3F                 RTC_ISR_TAMP3F_Msk

+#define RTC_ISR_TAMP2F_Pos             (14U)

+#define RTC_ISR_TAMP2F_Msk             (0x1UL << RTC_ISR_TAMP2F_Pos)           /*!< 0x00004000 */

+#define RTC_ISR_TAMP2F                 RTC_ISR_TAMP2F_Msk

+#define RTC_ISR_TAMP1F_Pos             (13U)

+#define RTC_ISR_TAMP1F_Msk             (0x1UL << RTC_ISR_TAMP1F_Pos)           /*!< 0x00002000 */

+#define RTC_ISR_TAMP1F                 RTC_ISR_TAMP1F_Msk

+#define RTC_ISR_TSOVF_Pos              (12U)

+#define RTC_ISR_TSOVF_Msk              (0x1UL << RTC_ISR_TSOVF_Pos)            /*!< 0x00001000 */

+#define RTC_ISR_TSOVF                  RTC_ISR_TSOVF_Msk

+#define RTC_ISR_TSF_Pos                (11U)

+#define RTC_ISR_TSF_Msk                (0x1UL << RTC_ISR_TSF_Pos)              /*!< 0x00000800 */

+#define RTC_ISR_TSF                    RTC_ISR_TSF_Msk

+#define RTC_ISR_WUTF_Pos               (10U)

+#define RTC_ISR_WUTF_Msk               (0x1UL << RTC_ISR_WUTF_Pos)             /*!< 0x00000400 */

+#define RTC_ISR_WUTF                   RTC_ISR_WUTF_Msk

+#define RTC_ISR_ALRBF_Pos              (9U)

+#define RTC_ISR_ALRBF_Msk              (0x1UL << RTC_ISR_ALRBF_Pos)            /*!< 0x00000200 */

+#define RTC_ISR_ALRBF                  RTC_ISR_ALRBF_Msk

+#define RTC_ISR_ALRAF_Pos              (8U)

+#define RTC_ISR_ALRAF_Msk              (0x1UL << RTC_ISR_ALRAF_Pos)            /*!< 0x00000100 */

+#define RTC_ISR_ALRAF                  RTC_ISR_ALRAF_Msk

+#define RTC_ISR_INIT_Pos               (7U)

+#define RTC_ISR_INIT_Msk               (0x1UL << RTC_ISR_INIT_Pos)             /*!< 0x00000080 */

+#define RTC_ISR_INIT                   RTC_ISR_INIT_Msk

+#define RTC_ISR_INITF_Pos              (6U)

+#define RTC_ISR_INITF_Msk              (0x1UL << RTC_ISR_INITF_Pos)            /*!< 0x00000040 */

+#define RTC_ISR_INITF                  RTC_ISR_INITF_Msk

+#define RTC_ISR_RSF_Pos                (5U)

+#define RTC_ISR_RSF_Msk                (0x1UL << RTC_ISR_RSF_Pos)              /*!< 0x00000020 */

+#define RTC_ISR_RSF                    RTC_ISR_RSF_Msk

+#define RTC_ISR_INITS_Pos              (4U)

+#define RTC_ISR_INITS_Msk              (0x1UL << RTC_ISR_INITS_Pos)            /*!< 0x00000010 */

+#define RTC_ISR_INITS                  RTC_ISR_INITS_Msk

+#define RTC_ISR_SHPF_Pos               (3U)

+#define RTC_ISR_SHPF_Msk               (0x1UL << RTC_ISR_SHPF_Pos)             /*!< 0x00000008 */

+#define RTC_ISR_SHPF                   RTC_ISR_SHPF_Msk

+#define RTC_ISR_WUTWF_Pos              (2U)

+#define RTC_ISR_WUTWF_Msk              (0x1UL << RTC_ISR_WUTWF_Pos)            /*!< 0x00000004 */

+#define RTC_ISR_WUTWF                  RTC_ISR_WUTWF_Msk

+#define RTC_ISR_ALRBWF_Pos             (1U)

+#define RTC_ISR_ALRBWF_Msk             (0x1UL << RTC_ISR_ALRBWF_Pos)           /*!< 0x00000002 */

+#define RTC_ISR_ALRBWF                 RTC_ISR_ALRBWF_Msk

+#define RTC_ISR_ALRAWF_Pos             (0U)

+#define RTC_ISR_ALRAWF_Msk             (0x1UL << RTC_ISR_ALRAWF_Pos)           /*!< 0x00000001 */

+#define RTC_ISR_ALRAWF                 RTC_ISR_ALRAWF_Msk

+

+/********************  Bits definition for RTC_PRER register  *****************/

+#define RTC_PRER_PREDIV_A_Pos          (16U)

+#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */

+#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk

+#define RTC_PRER_PREDIV_S_Pos          (0U)

+#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */

+#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk

+

+/********************  Bits definition for RTC_WUTR register  *****************/

+#define RTC_WUTR_WUT_Pos               (0U)

+#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */

+#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk

+

+/********************  Bits definition for RTC_ALRMAR register  ***************/

+#define RTC_ALRMAR_MSK4_Pos            (31U)

+#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */

+#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk

+#define RTC_ALRMAR_WDSEL_Pos           (30U)

+#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */

+#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk

+#define RTC_ALRMAR_DT_Pos              (28U)

+#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */

+#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk

+#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */

+#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */

+#define RTC_ALRMAR_DU_Pos              (24U)

+#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */

+#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk

+#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */

+#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */

+#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */

+#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */

+#define RTC_ALRMAR_MSK3_Pos            (23U)

+#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */

+#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk

+#define RTC_ALRMAR_PM_Pos              (22U)

+#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */

+#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk

+#define RTC_ALRMAR_HT_Pos              (20U)

+#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */

+#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk

+#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */

+#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */

+#define RTC_ALRMAR_HU_Pos              (16U)

+#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */

+#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk

+#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */

+#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */

+#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */

+#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */

+#define RTC_ALRMAR_MSK2_Pos            (15U)

+#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */

+#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk

+#define RTC_ALRMAR_MNT_Pos             (12U)

+#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */

+#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk

+#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */

+#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */

+#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */

+#define RTC_ALRMAR_MNU_Pos             (8U)

+#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */

+#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk

+#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */

+#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */

+#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */

+#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */

+#define RTC_ALRMAR_MSK1_Pos            (7U)

+#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */

+#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk

+#define RTC_ALRMAR_ST_Pos              (4U)

+#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */

+#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk

+#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */

+#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */

+#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */

+#define RTC_ALRMAR_SU_Pos              (0U)

+#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */

+#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk

+#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */

+#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */

+#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */

+#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_ALRMBR register  ***************/

+#define RTC_ALRMBR_MSK4_Pos            (31U)

+#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */

+#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk

+#define RTC_ALRMBR_WDSEL_Pos           (30U)

+#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */

+#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk

+#define RTC_ALRMBR_DT_Pos              (28U)

+#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */

+#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk

+#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */

+#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */

+#define RTC_ALRMBR_DU_Pos              (24U)

+#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */

+#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk

+#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */

+#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */

+#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */

+#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */

+#define RTC_ALRMBR_MSK3_Pos            (23U)

+#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */

+#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk

+#define RTC_ALRMBR_PM_Pos              (22U)

+#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */

+#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk

+#define RTC_ALRMBR_HT_Pos              (20U)

+#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */

+#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk

+#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */

+#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */

+#define RTC_ALRMBR_HU_Pos              (16U)

+#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */

+#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk

+#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */

+#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */

+#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */

+#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */

+#define RTC_ALRMBR_MSK2_Pos            (15U)

+#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */

+#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk

+#define RTC_ALRMBR_MNT_Pos             (12U)

+#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */

+#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk

+#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */

+#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */

+#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */

+#define RTC_ALRMBR_MNU_Pos             (8U)

+#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */

+#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk

+#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */

+#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */

+#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */

+#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */

+#define RTC_ALRMBR_MSK1_Pos            (7U)

+#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */

+#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk

+#define RTC_ALRMBR_ST_Pos              (4U)

+#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */

+#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk

+#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */

+#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */

+#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */

+#define RTC_ALRMBR_SU_Pos              (0U)

+#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */

+#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk

+#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */

+#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */

+#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */

+#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_WPR register  ******************/

+#define RTC_WPR_KEY_Pos                (0U)

+#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */

+#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk

+

+/********************  Bits definition for RTC_SSR register  ******************/

+#define RTC_SSR_SS_Pos                 (0U)

+#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)            /*!< 0x0000FFFF */

+#define RTC_SSR_SS                     RTC_SSR_SS_Msk

+

+/********************  Bits definition for RTC_SHIFTR register  ***************/

+#define RTC_SHIFTR_SUBFS_Pos           (0U)

+#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */

+#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk

+#define RTC_SHIFTR_ADD1S_Pos           (31U)

+#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */

+#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk

+

+/********************  Bits definition for RTC_TSTR register  *****************/

+#define RTC_TSTR_PM_Pos                (22U)

+#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */

+#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk

+#define RTC_TSTR_HT_Pos                (20U)

+#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */

+#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk

+#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */

+#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */

+#define RTC_TSTR_HU_Pos                (16U)

+#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */

+#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk

+#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */

+#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */

+#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */

+#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */

+#define RTC_TSTR_MNT_Pos               (12U)

+#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */

+#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk

+#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */

+#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */

+#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */

+#define RTC_TSTR_MNU_Pos               (8U)

+#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */

+#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk

+#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */

+#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */

+#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */

+#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */

+#define RTC_TSTR_ST_Pos                (4U)

+#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */

+#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk

+#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */

+#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */

+#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */

+#define RTC_TSTR_SU_Pos                (0U)

+#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */

+#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk

+#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */

+#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */

+#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */

+#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_TSDR register  *****************/

+#define RTC_TSDR_WDU_Pos               (13U)

+#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */

+#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk

+#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */

+#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */

+#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */

+#define RTC_TSDR_MT_Pos                (12U)

+#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */

+#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk

+#define RTC_TSDR_MU_Pos                (8U)

+#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */

+#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk

+#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */

+#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */

+#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */

+#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */

+#define RTC_TSDR_DT_Pos                (4U)

+#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */

+#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk

+#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */

+#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */

+#define RTC_TSDR_DU_Pos                (0U)

+#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */

+#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk

+#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */

+#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */

+#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */

+#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_TSSSR register  ****************/

+#define RTC_TSSSR_SS_Pos               (0U)

+#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)          /*!< 0x0000FFFF */

+#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk

+

+/********************  Bits definition for RTC_CALR register  *****************/

+#define RTC_CALR_CALP_Pos              (15U)

+#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */

+#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk

+#define RTC_CALR_CALW8_Pos             (14U)

+#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */

+#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk

+#define RTC_CALR_CALW16_Pos            (13U)

+#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */

+#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk

+#define RTC_CALR_CALM_Pos              (0U)

+#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */

+#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk

+#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */

+#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */

+#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */

+#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */

+#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */

+#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */

+#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */

+#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */

+#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */

+

+/********************  Bits definition for RTC_TAMPCR register  ***************/

+#define RTC_TAMPCR_TAMP3MF_Pos         (24U)

+#define RTC_TAMPCR_TAMP3MF_Msk         (0x1UL << RTC_TAMPCR_TAMP3MF_Pos)       /*!< 0x01000000 */

+#define RTC_TAMPCR_TAMP3MF             RTC_TAMPCR_TAMP3MF_Msk

+#define RTC_TAMPCR_TAMP3NOERASE_Pos    (23U)

+#define RTC_TAMPCR_TAMP3NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos)  /*!< 0x00800000 */

+#define RTC_TAMPCR_TAMP3NOERASE        RTC_TAMPCR_TAMP3NOERASE_Msk

+#define RTC_TAMPCR_TAMP3IE_Pos         (22U)

+#define RTC_TAMPCR_TAMP3IE_Msk         (0x1UL << RTC_TAMPCR_TAMP3IE_Pos)       /*!< 0x00400000 */

+#define RTC_TAMPCR_TAMP3IE             RTC_TAMPCR_TAMP3IE_Msk

+#define RTC_TAMPCR_TAMP2MF_Pos         (21U)

+#define RTC_TAMPCR_TAMP2MF_Msk         (0x1UL << RTC_TAMPCR_TAMP2MF_Pos)       /*!< 0x00200000 */

+#define RTC_TAMPCR_TAMP2MF             RTC_TAMPCR_TAMP2MF_Msk

+#define RTC_TAMPCR_TAMP2NOERASE_Pos    (20U)

+#define RTC_TAMPCR_TAMP2NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos)  /*!< 0x00100000 */

+#define RTC_TAMPCR_TAMP2NOERASE        RTC_TAMPCR_TAMP2NOERASE_Msk

+#define RTC_TAMPCR_TAMP2IE_Pos         (19U)

+#define RTC_TAMPCR_TAMP2IE_Msk         (0x1UL << RTC_TAMPCR_TAMP2IE_Pos)       /*!< 0x00080000 */

+#define RTC_TAMPCR_TAMP2IE             RTC_TAMPCR_TAMP2IE_Msk

+#define RTC_TAMPCR_TAMP1MF_Pos         (18U)

+#define RTC_TAMPCR_TAMP1MF_Msk         (0x1UL << RTC_TAMPCR_TAMP1MF_Pos)       /*!< 0x00040000 */

+#define RTC_TAMPCR_TAMP1MF             RTC_TAMPCR_TAMP1MF_Msk

+#define RTC_TAMPCR_TAMP1NOERASE_Pos    (17U)

+#define RTC_TAMPCR_TAMP1NOERASE_Msk    (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos)  /*!< 0x00020000 */

+#define RTC_TAMPCR_TAMP1NOERASE        RTC_TAMPCR_TAMP1NOERASE_Msk

+#define RTC_TAMPCR_TAMP1IE_Pos         (16U)

+#define RTC_TAMPCR_TAMP1IE_Msk         (0x1UL << RTC_TAMPCR_TAMP1IE_Pos)       /*!< 0x00010000 */

+#define RTC_TAMPCR_TAMP1IE             RTC_TAMPCR_TAMP1IE_Msk

+#define RTC_TAMPCR_TAMPPUDIS_Pos       (15U)

+#define RTC_TAMPCR_TAMPPUDIS_Msk       (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos)     /*!< 0x00008000 */

+#define RTC_TAMPCR_TAMPPUDIS           RTC_TAMPCR_TAMPPUDIS_Msk

+#define RTC_TAMPCR_TAMPPRCH_Pos        (13U)

+#define RTC_TAMPCR_TAMPPRCH_Msk        (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos)      /*!< 0x00006000 */

+#define RTC_TAMPCR_TAMPPRCH            RTC_TAMPCR_TAMPPRCH_Msk

+#define RTC_TAMPCR_TAMPPRCH_0          (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00002000 */

+#define RTC_TAMPCR_TAMPPRCH_1          (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos)       /*!< 0x00004000 */

+#define RTC_TAMPCR_TAMPFLT_Pos         (11U)

+#define RTC_TAMPCR_TAMPFLT_Msk         (0x3UL << RTC_TAMPCR_TAMPFLT_Pos)       /*!< 0x00001800 */

+#define RTC_TAMPCR_TAMPFLT             RTC_TAMPCR_TAMPFLT_Msk

+#define RTC_TAMPCR_TAMPFLT_0           (0x1UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00000800 */

+#define RTC_TAMPCR_TAMPFLT_1           (0x2UL << RTC_TAMPCR_TAMPFLT_Pos)        /*!< 0x00001000 */

+#define RTC_TAMPCR_TAMPFREQ_Pos        (8U)

+#define RTC_TAMPCR_TAMPFREQ_Msk        (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos)      /*!< 0x00000700 */

+#define RTC_TAMPCR_TAMPFREQ            RTC_TAMPCR_TAMPFREQ_Msk

+#define RTC_TAMPCR_TAMPFREQ_0          (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000100 */

+#define RTC_TAMPCR_TAMPFREQ_1          (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000200 */

+#define RTC_TAMPCR_TAMPFREQ_2          (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos)       /*!< 0x00000400 */

+#define RTC_TAMPCR_TAMPTS_Pos          (7U)

+#define RTC_TAMPCR_TAMPTS_Msk          (0x1UL << RTC_TAMPCR_TAMPTS_Pos)        /*!< 0x00000080 */

+#define RTC_TAMPCR_TAMPTS              RTC_TAMPCR_TAMPTS_Msk

+#define RTC_TAMPCR_TAMP3TRG_Pos        (6U)

+#define RTC_TAMPCR_TAMP3TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos)      /*!< 0x00000040 */

+#define RTC_TAMPCR_TAMP3TRG            RTC_TAMPCR_TAMP3TRG_Msk

+#define RTC_TAMPCR_TAMP3E_Pos          (5U)

+#define RTC_TAMPCR_TAMP3E_Msk          (0x1UL << RTC_TAMPCR_TAMP3E_Pos)        /*!< 0x00000020 */

+#define RTC_TAMPCR_TAMP3E              RTC_TAMPCR_TAMP3E_Msk

+#define RTC_TAMPCR_TAMP2TRG_Pos        (4U)

+#define RTC_TAMPCR_TAMP2TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos)      /*!< 0x00000010 */

+#define RTC_TAMPCR_TAMP2TRG            RTC_TAMPCR_TAMP2TRG_Msk

+#define RTC_TAMPCR_TAMP2E_Pos          (3U)

+#define RTC_TAMPCR_TAMP2E_Msk          (0x1UL << RTC_TAMPCR_TAMP2E_Pos)        /*!< 0x00000008 */

+#define RTC_TAMPCR_TAMP2E              RTC_TAMPCR_TAMP2E_Msk

+#define RTC_TAMPCR_TAMPIE_Pos          (2U)

+#define RTC_TAMPCR_TAMPIE_Msk          (0x1UL << RTC_TAMPCR_TAMPIE_Pos)        /*!< 0x00000004 */

+#define RTC_TAMPCR_TAMPIE              RTC_TAMPCR_TAMPIE_Msk

+#define RTC_TAMPCR_TAMP1TRG_Pos        (1U)

+#define RTC_TAMPCR_TAMP1TRG_Msk        (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos)      /*!< 0x00000002 */

+#define RTC_TAMPCR_TAMP1TRG            RTC_TAMPCR_TAMP1TRG_Msk

+#define RTC_TAMPCR_TAMP1E_Pos          (0U)

+#define RTC_TAMPCR_TAMP1E_Msk          (0x1UL << RTC_TAMPCR_TAMP1E_Pos)        /*!< 0x00000001 */

+#define RTC_TAMPCR_TAMP1E              RTC_TAMPCR_TAMP1E_Msk

+

+/********************  Bits definition for RTC_ALRMASSR register  *************/

+#define RTC_ALRMASSR_MASKSS_Pos        (24U)

+#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x0F000000 */

+#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk

+#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */

+#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */

+#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */

+#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */

+#define RTC_ALRMASSR_SS_Pos            (0U)

+#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */

+#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk

+

+/********************  Bits definition for RTC_ALRMBSSR register  *************/

+#define RTC_ALRMBSSR_MASKSS_Pos        (24U)

+#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x0F000000 */

+#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk

+#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */

+#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */

+#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */

+#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */

+#define RTC_ALRMBSSR_SS_Pos            (0U)

+#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */

+#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk

+

+/********************  Bits definition for RTC_OR register  *******************/

+#define RTC_OR_OUT_RMP_Pos             (1U)

+#define RTC_OR_OUT_RMP_Msk             (0x1UL << RTC_OR_OUT_RMP_Pos)           /*!< 0x00000002 */

+#define RTC_OR_OUT_RMP                 RTC_OR_OUT_RMP_Msk

+#define RTC_OR_ALARMOUTTYPE_Pos        (0U)

+#define RTC_OR_ALARMOUTTYPE_Msk        (0x1UL << RTC_OR_ALARMOUTTYPE_Pos)      /*!< 0x00000001 */

+#define RTC_OR_ALARMOUTTYPE            RTC_OR_ALARMOUTTYPE_Msk

+

+/********************  Bits definition for RTC_BKP0R register  ****************/

+#define RTC_BKP0R_Pos                  (0U)

+#define RTC_BKP0R_Msk                  (0xFFFFFFFFUL << RTC_BKP0R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP0R                      RTC_BKP0R_Msk

+

+/********************  Bits definition for RTC_BKP1R register  ****************/

+#define RTC_BKP1R_Pos                  (0U)

+#define RTC_BKP1R_Msk                  (0xFFFFFFFFUL << RTC_BKP1R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP1R                      RTC_BKP1R_Msk

+

+/********************  Bits definition for RTC_BKP2R register  ****************/

+#define RTC_BKP2R_Pos                  (0U)

+#define RTC_BKP2R_Msk                  (0xFFFFFFFFUL << RTC_BKP2R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP2R                      RTC_BKP2R_Msk

+

+/********************  Bits definition for RTC_BKP3R register  ****************/

+#define RTC_BKP3R_Pos                  (0U)

+#define RTC_BKP3R_Msk                  (0xFFFFFFFFUL << RTC_BKP3R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP3R                      RTC_BKP3R_Msk

+

+/********************  Bits definition for RTC_BKP4R register  ****************/

+#define RTC_BKP4R_Pos                  (0U)

+#define RTC_BKP4R_Msk                  (0xFFFFFFFFUL << RTC_BKP4R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP4R                      RTC_BKP4R_Msk

+

+/********************  Bits definition for RTC_BKP5R register  ****************/

+#define RTC_BKP5R_Pos                  (0U)

+#define RTC_BKP5R_Msk                  (0xFFFFFFFFUL << RTC_BKP5R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP5R                      RTC_BKP5R_Msk

+

+/********************  Bits definition for RTC_BKP6R register  ****************/

+#define RTC_BKP6R_Pos                  (0U)

+#define RTC_BKP6R_Msk                  (0xFFFFFFFFUL << RTC_BKP6R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP6R                      RTC_BKP6R_Msk

+

+/********************  Bits definition for RTC_BKP7R register  ****************/

+#define RTC_BKP7R_Pos                  (0U)

+#define RTC_BKP7R_Msk                  (0xFFFFFFFFUL << RTC_BKP7R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP7R                      RTC_BKP7R_Msk

+

+/********************  Bits definition for RTC_BKP8R register  ****************/

+#define RTC_BKP8R_Pos                  (0U)

+#define RTC_BKP8R_Msk                  (0xFFFFFFFFUL << RTC_BKP8R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP8R                      RTC_BKP8R_Msk

+

+/********************  Bits definition for RTC_BKP9R register  ****************/

+#define RTC_BKP9R_Pos                  (0U)

+#define RTC_BKP9R_Msk                  (0xFFFFFFFFUL << RTC_BKP9R_Pos)         /*!< 0xFFFFFFFF */

+#define RTC_BKP9R                      RTC_BKP9R_Msk

+

+/********************  Bits definition for RTC_BKP10R register  ***************/

+#define RTC_BKP10R_Pos                 (0U)

+#define RTC_BKP10R_Msk                 (0xFFFFFFFFUL << RTC_BKP10R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP10R                     RTC_BKP10R_Msk

+

+/********************  Bits definition for RTC_BKP11R register  ***************/

+#define RTC_BKP11R_Pos                 (0U)

+#define RTC_BKP11R_Msk                 (0xFFFFFFFFUL << RTC_BKP11R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP11R                     RTC_BKP11R_Msk

+

+/********************  Bits definition for RTC_BKP12R register  ***************/

+#define RTC_BKP12R_Pos                 (0U)

+#define RTC_BKP12R_Msk                 (0xFFFFFFFFUL << RTC_BKP12R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP12R                     RTC_BKP12R_Msk

+

+/********************  Bits definition for RTC_BKP13R register  ***************/

+#define RTC_BKP13R_Pos                 (0U)

+#define RTC_BKP13R_Msk                 (0xFFFFFFFFUL << RTC_BKP13R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP13R                     RTC_BKP13R_Msk

+

+/********************  Bits definition for RTC_BKP14R register  ***************/

+#define RTC_BKP14R_Pos                 (0U)

+#define RTC_BKP14R_Msk                 (0xFFFFFFFFUL << RTC_BKP14R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP14R                     RTC_BKP14R_Msk

+

+/********************  Bits definition for RTC_BKP15R register  ***************/

+#define RTC_BKP15R_Pos                 (0U)

+#define RTC_BKP15R_Msk                 (0xFFFFFFFFUL << RTC_BKP15R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP15R                     RTC_BKP15R_Msk

+

+/********************  Bits definition for RTC_BKP16R register  ***************/

+#define RTC_BKP16R_Pos                 (0U)

+#define RTC_BKP16R_Msk                 (0xFFFFFFFFUL << RTC_BKP16R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP16R                     RTC_BKP16R_Msk

+

+/********************  Bits definition for RTC_BKP17R register  ***************/

+#define RTC_BKP17R_Pos                 (0U)

+#define RTC_BKP17R_Msk                 (0xFFFFFFFFUL << RTC_BKP17R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP17R                     RTC_BKP17R_Msk

+

+/********************  Bits definition for RTC_BKP18R register  ***************/

+#define RTC_BKP18R_Pos                 (0U)

+#define RTC_BKP18R_Msk                 (0xFFFFFFFFUL << RTC_BKP18R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP18R                     RTC_BKP18R_Msk

+

+/********************  Bits definition for RTC_BKP19R register  ***************/

+#define RTC_BKP19R_Pos                 (0U)

+#define RTC_BKP19R_Msk                 (0xFFFFFFFFUL << RTC_BKP19R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP19R                     RTC_BKP19R_Msk

+

+/********************  Bits definition for RTC_BKP20R register  ***************/

+#define RTC_BKP20R_Pos                 (0U)

+#define RTC_BKP20R_Msk                 (0xFFFFFFFFUL << RTC_BKP20R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP20R                     RTC_BKP20R_Msk

+

+/********************  Bits definition for RTC_BKP21R register  ***************/

+#define RTC_BKP21R_Pos                 (0U)

+#define RTC_BKP21R_Msk                 (0xFFFFFFFFUL << RTC_BKP21R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP21R                     RTC_BKP21R_Msk

+

+/********************  Bits definition for RTC_BKP22R register  ***************/

+#define RTC_BKP22R_Pos                 (0U)

+#define RTC_BKP22R_Msk                 (0xFFFFFFFFUL << RTC_BKP22R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP22R                     RTC_BKP22R_Msk

+

+/********************  Bits definition for RTC_BKP23R register  ***************/

+#define RTC_BKP23R_Pos                 (0U)

+#define RTC_BKP23R_Msk                 (0xFFFFFFFFUL << RTC_BKP23R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP23R                     RTC_BKP23R_Msk

+

+/********************  Bits definition for RTC_BKP24R register  ***************/

+#define RTC_BKP24R_Pos                 (0U)

+#define RTC_BKP24R_Msk                 (0xFFFFFFFFUL << RTC_BKP24R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP24R                     RTC_BKP24R_Msk

+

+/********************  Bits definition for RTC_BKP25R register  ***************/

+#define RTC_BKP25R_Pos                 (0U)

+#define RTC_BKP25R_Msk                 (0xFFFFFFFFUL << RTC_BKP25R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP25R                     RTC_BKP25R_Msk

+

+/********************  Bits definition for RTC_BKP26R register  ***************/

+#define RTC_BKP26R_Pos                 (0U)

+#define RTC_BKP26R_Msk                 (0xFFFFFFFFUL << RTC_BKP26R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP26R                     RTC_BKP26R_Msk

+

+/********************  Bits definition for RTC_BKP27R register  ***************/

+#define RTC_BKP27R_Pos                 (0U)

+#define RTC_BKP27R_Msk                 (0xFFFFFFFFUL << RTC_BKP27R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP27R                     RTC_BKP27R_Msk

+

+/********************  Bits definition for RTC_BKP28R register  ***************/

+#define RTC_BKP28R_Pos                 (0U)

+#define RTC_BKP28R_Msk                 (0xFFFFFFFFUL << RTC_BKP28R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP28R                     RTC_BKP28R_Msk

+

+/********************  Bits definition for RTC_BKP29R register  ***************/

+#define RTC_BKP29R_Pos                 (0U)

+#define RTC_BKP29R_Msk                 (0xFFFFFFFFUL << RTC_BKP29R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP29R                     RTC_BKP29R_Msk

+

+/********************  Bits definition for RTC_BKP30R register  ***************/

+#define RTC_BKP30R_Pos                 (0U)

+#define RTC_BKP30R_Msk                 (0xFFFFFFFFUL << RTC_BKP30R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP30R                     RTC_BKP30R_Msk

+

+/********************  Bits definition for RTC_BKP31R register  ***************/

+#define RTC_BKP31R_Pos                 (0U)

+#define RTC_BKP31R_Msk                 (0xFFFFFFFFUL << RTC_BKP31R_Pos)        /*!< 0xFFFFFFFF */

+#define RTC_BKP31R                     RTC_BKP31R_Msk

+

+/******************** Number of backup registers ******************************/

+#define RTC_BKP_NUMBER_Pos             (5U)

+#define RTC_BKP_NUMBER_Msk             (0x1UL << RTC_BKP_NUMBER_Pos)           /*!< 0x00000020 */

+#define RTC_BKP_NUMBER                 RTC_BKP_NUMBER_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                              SPDIF-RX Interface                            */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for SPDIF_CR register  ******************/

+#define SPDIFRX_CR_SPDIFEN_Pos      (0U)

+#define SPDIFRX_CR_SPDIFEN_Msk      (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)          /*!< 0x00000003 */

+#define SPDIFRX_CR_SPDIFEN          SPDIFRX_CR_SPDIFEN_Msk                     /*!<Peripheral Block Enable                      */

+#define SPDIFRX_CR_RXDMAEN_Pos      (2U)

+#define SPDIFRX_CR_RXDMAEN_Msk      (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)          /*!< 0x00000004 */

+#define SPDIFRX_CR_RXDMAEN          SPDIFRX_CR_RXDMAEN_Msk                     /*!<Receiver DMA Enable for data flow            */

+#define SPDIFRX_CR_RXSTEO_Pos       (3U)

+#define SPDIFRX_CR_RXSTEO_Msk       (0x1UL << SPDIFRX_CR_RXSTEO_Pos)           /*!< 0x00000008 */

+#define SPDIFRX_CR_RXSTEO           SPDIFRX_CR_RXSTEO_Msk                      /*!<Stereo Mode                                  */

+#define SPDIFRX_CR_DRFMT_Pos        (4U)

+#define SPDIFRX_CR_DRFMT_Msk        (0x3UL << SPDIFRX_CR_DRFMT_Pos)            /*!< 0x00000030 */

+#define SPDIFRX_CR_DRFMT            SPDIFRX_CR_DRFMT_Msk                       /*!<RX Data format                               */

+#define SPDIFRX_CR_PMSK_Pos         (6U)

+#define SPDIFRX_CR_PMSK_Msk         (0x1UL << SPDIFRX_CR_PMSK_Pos)             /*!< 0x00000040 */

+#define SPDIFRX_CR_PMSK             SPDIFRX_CR_PMSK_Msk                        /*!<Mask Parity error bit                        */

+#define SPDIFRX_CR_VMSK_Pos         (7U)

+#define SPDIFRX_CR_VMSK_Msk         (0x1UL << SPDIFRX_CR_VMSK_Pos)             /*!< 0x00000080 */

+#define SPDIFRX_CR_VMSK             SPDIFRX_CR_VMSK_Msk                        /*!<Mask of Validity bit                         */

+#define SPDIFRX_CR_CUMSK_Pos        (8U)

+#define SPDIFRX_CR_CUMSK_Msk        (0x1UL << SPDIFRX_CR_CUMSK_Pos)            /*!< 0x00000100 */

+#define SPDIFRX_CR_CUMSK            SPDIFRX_CR_CUMSK_Msk                       /*!<Mask of channel status and user bits         */

+#define SPDIFRX_CR_PTMSK_Pos        (9U)

+#define SPDIFRX_CR_PTMSK_Msk        (0x1UL << SPDIFRX_CR_PTMSK_Pos)            /*!< 0x00000200 */

+#define SPDIFRX_CR_PTMSK            SPDIFRX_CR_PTMSK_Msk                       /*!<Mask of Preamble Type bits                   */

+#define SPDIFRX_CR_CBDMAEN_Pos      (10U)

+#define SPDIFRX_CR_CBDMAEN_Msk      (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)          /*!< 0x00000400 */

+#define SPDIFRX_CR_CBDMAEN          SPDIFRX_CR_CBDMAEN_Msk                     /*!<Control Buffer DMA ENable for control flow   */

+#define SPDIFRX_CR_CHSEL_Pos        (11U)

+#define SPDIFRX_CR_CHSEL_Msk        (0x1UL << SPDIFRX_CR_CHSEL_Pos)            /*!< 0x00000800 */

+#define SPDIFRX_CR_CHSEL            SPDIFRX_CR_CHSEL_Msk                       /*!<Channel Selection                            */

+#define SPDIFRX_CR_NBTR_Pos         (12U)

+#define SPDIFRX_CR_NBTR_Msk         (0x3UL << SPDIFRX_CR_NBTR_Pos)             /*!< 0x00003000 */

+#define SPDIFRX_CR_NBTR             SPDIFRX_CR_NBTR_Msk                        /*!<Maximum allowed re-tries during synchronization phase */

+#define SPDIFRX_CR_WFA_Pos          (14U)

+#define SPDIFRX_CR_WFA_Msk          (0x1UL << SPDIFRX_CR_WFA_Pos)              /*!< 0x00004000 */

+#define SPDIFRX_CR_WFA              SPDIFRX_CR_WFA_Msk                         /*!<Wait For Activity     */

+#define SPDIFRX_CR_INSEL_Pos        (16U)

+#define SPDIFRX_CR_INSEL_Msk        (0x7UL << SPDIFRX_CR_INSEL_Pos)            /*!< 0x00070000 */

+#define SPDIFRX_CR_INSEL            SPDIFRX_CR_INSEL_Msk                       /*!<SPDIF input selection */

+#define SPDIFRX_CR_CKSEN_Pos        (20U)

+#define SPDIFRX_CR_CKSEN_Msk        (0x1UL << SPDIFRX_CR_CKSEN_Pos)            /*!< 0x00100000 */

+#define SPDIFRX_CR_CKSEN            SPDIFRX_CR_CKSEN_Msk                       /*!<Symbol Clock Enable */

+#define SPDIFRX_CR_CKSBKPEN_Pos     (21U)

+#define SPDIFRX_CR_CKSBKPEN_Msk     (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)         /*!< 0x00200000 */

+#define SPDIFRX_CR_CKSBKPEN         SPDIFRX_CR_CKSBKPEN_Msk                    /*!<Backup Symbol Clock Enable */

+

+/*******************  Bit definition for SPDIFRX_IMR register  *******************/

+#define SPDIFRX_IMR_RXNEIE_Pos      (0U)

+#define SPDIFRX_IMR_RXNEIE_Msk      (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)          /*!< 0x00000001 */

+#define SPDIFRX_IMR_RXNEIE          SPDIFRX_IMR_RXNEIE_Msk                     /*!<RXNE interrupt enable                              */

+#define SPDIFRX_IMR_CSRNEIE_Pos     (1U)

+#define SPDIFRX_IMR_CSRNEIE_Msk     (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)         /*!< 0x00000002 */

+#define SPDIFRX_IMR_CSRNEIE         SPDIFRX_IMR_CSRNEIE_Msk                    /*!<Control Buffer Ready Interrupt Enable              */

+#define SPDIFRX_IMR_PERRIE_Pos      (2U)

+#define SPDIFRX_IMR_PERRIE_Msk      (0x1UL << SPDIFRX_IMR_PERRIE_Pos)          /*!< 0x00000004 */

+#define SPDIFRX_IMR_PERRIE          SPDIFRX_IMR_PERRIE_Msk                     /*!<Parity error interrupt enable                      */

+#define SPDIFRX_IMR_OVRIE_Pos       (3U)

+#define SPDIFRX_IMR_OVRIE_Msk       (0x1UL << SPDIFRX_IMR_OVRIE_Pos)           /*!< 0x00000008 */

+#define SPDIFRX_IMR_OVRIE           SPDIFRX_IMR_OVRIE_Msk                      /*!<Overrun error Interrupt Enable                     */

+#define SPDIFRX_IMR_SBLKIE_Pos      (4U)

+#define SPDIFRX_IMR_SBLKIE_Msk      (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)          /*!< 0x00000010 */

+#define SPDIFRX_IMR_SBLKIE          SPDIFRX_IMR_SBLKIE_Msk                     /*!<Synchronization Block Detected Interrupt Enable    */

+#define SPDIFRX_IMR_SYNCDIE_Pos     (5U)

+#define SPDIFRX_IMR_SYNCDIE_Msk     (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)         /*!< 0x00000020 */

+#define SPDIFRX_IMR_SYNCDIE         SPDIFRX_IMR_SYNCDIE_Msk                    /*!<Synchronization Done                               */

+#define SPDIFRX_IMR_IFEIE_Pos       (6U)

+#define SPDIFRX_IMR_IFEIE_Msk       (0x1UL << SPDIFRX_IMR_IFEIE_Pos)           /*!< 0x00000040 */

+#define SPDIFRX_IMR_IFEIE           SPDIFRX_IMR_IFEIE_Msk                      /*!<Serial Interface Error Interrupt Enable            */

+

+/*******************  Bit definition for SPDIFRX_SR register  *******************/

+#define SPDIFRX_SR_RXNE_Pos         (0U)

+#define SPDIFRX_SR_RXNE_Msk         (0x1UL << SPDIFRX_SR_RXNE_Pos)             /*!< 0x00000001 */

+#define SPDIFRX_SR_RXNE             SPDIFRX_SR_RXNE_Msk                        /*!<Read data register not empty                          */

+#define SPDIFRX_SR_CSRNE_Pos        (1U)

+#define SPDIFRX_SR_CSRNE_Msk        (0x1UL << SPDIFRX_SR_CSRNE_Pos)            /*!< 0x00000002 */

+#define SPDIFRX_SR_CSRNE            SPDIFRX_SR_CSRNE_Msk                       /*!<The Control Buffer register is not empty              */

+#define SPDIFRX_SR_PERR_Pos         (2U)

+#define SPDIFRX_SR_PERR_Msk         (0x1UL << SPDIFRX_SR_PERR_Pos)             /*!< 0x00000004 */

+#define SPDIFRX_SR_PERR             SPDIFRX_SR_PERR_Msk                        /*!<Parity error                                          */

+#define SPDIFRX_SR_OVR_Pos          (3U)

+#define SPDIFRX_SR_OVR_Msk          (0x1UL << SPDIFRX_SR_OVR_Pos)              /*!< 0x00000008 */

+#define SPDIFRX_SR_OVR              SPDIFRX_SR_OVR_Msk                         /*!<Overrun error                                         */

+#define SPDIFRX_SR_SBD_Pos          (4U)

+#define SPDIFRX_SR_SBD_Msk          (0x1UL << SPDIFRX_SR_SBD_Pos)              /*!< 0x00000010 */

+#define SPDIFRX_SR_SBD              SPDIFRX_SR_SBD_Msk                         /*!<Synchronization Block Detected                        */

+#define SPDIFRX_SR_SYNCD_Pos        (5U)

+#define SPDIFRX_SR_SYNCD_Msk        (0x1UL << SPDIFRX_SR_SYNCD_Pos)            /*!< 0x00000020 */

+#define SPDIFRX_SR_SYNCD            SPDIFRX_SR_SYNCD_Msk                       /*!<Synchronization Done                                  */

+#define SPDIFRX_SR_FERR_Pos         (6U)

+#define SPDIFRX_SR_FERR_Msk         (0x1UL << SPDIFRX_SR_FERR_Pos)             /*!< 0x00000040 */

+#define SPDIFRX_SR_FERR             SPDIFRX_SR_FERR_Msk                        /*!<Framing error                                         */

+#define SPDIFRX_SR_SERR_Pos         (7U)

+#define SPDIFRX_SR_SERR_Msk         (0x1UL << SPDIFRX_SR_SERR_Pos)             /*!< 0x00000080 */

+#define SPDIFRX_SR_SERR             SPDIFRX_SR_SERR_Msk                        /*!<Synchronization error                                 */

+#define SPDIFRX_SR_TERR_Pos         (8U)

+#define SPDIFRX_SR_TERR_Msk         (0x1UL << SPDIFRX_SR_TERR_Pos)             /*!< 0x00000100 */

+#define SPDIFRX_SR_TERR             SPDIFRX_SR_TERR_Msk                        /*!<Time-out error                                        */

+#define SPDIFRX_SR_WIDTH5_Pos       (16U)

+#define SPDIFRX_SR_WIDTH5_Msk       (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)        /*!< 0x7FFF0000 */

+#define SPDIFRX_SR_WIDTH5           SPDIFRX_SR_WIDTH5_Msk                      /*!<Duration of 5 symbols counted with spdif_clk          */

+

+/*******************  Bit definition for SPDIFRX_IFCR register  *******************/

+#define SPDIFRX_IFCR_PERRCF_Pos     (2U)

+#define SPDIFRX_IFCR_PERRCF_Msk     (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)         /*!< 0x00000004 */

+#define SPDIFRX_IFCR_PERRCF         SPDIFRX_IFCR_PERRCF_Msk                    /*!<Clears the Parity error flag                         */

+#define SPDIFRX_IFCR_OVRCF_Pos      (3U)

+#define SPDIFRX_IFCR_OVRCF_Msk      (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)          /*!< 0x00000008 */

+#define SPDIFRX_IFCR_OVRCF          SPDIFRX_IFCR_OVRCF_Msk                     /*!<Clears the Overrun error flag                        */

+#define SPDIFRX_IFCR_SBDCF_Pos      (4U)

+#define SPDIFRX_IFCR_SBDCF_Msk      (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)          /*!< 0x00000010 */

+#define SPDIFRX_IFCR_SBDCF          SPDIFRX_IFCR_SBDCF_Msk                     /*!<Clears the Synchronization Block Detected flag       */

+#define SPDIFRX_IFCR_SYNCDCF_Pos    (5U)

+#define SPDIFRX_IFCR_SYNCDCF_Msk    (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)        /*!< 0x00000020 */

+#define SPDIFRX_IFCR_SYNCDCF        SPDIFRX_IFCR_SYNCDCF_Msk                   /*!<Clears the Synchronization Done flag                 */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/

+#define SPDIFRX_DR0_DR_Pos          (0U)

+#define SPDIFRX_DR0_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)         /*!< 0x00FFFFFF */

+#define SPDIFRX_DR0_DR              SPDIFRX_DR0_DR_Msk                         /*!<Data value            */

+#define SPDIFRX_DR0_PE_Pos          (24U)

+#define SPDIFRX_DR0_PE_Msk          (0x1UL << SPDIFRX_DR0_PE_Pos)              /*!< 0x01000000 */

+#define SPDIFRX_DR0_PE              SPDIFRX_DR0_PE_Msk                         /*!<Parity Error bit      */

+#define SPDIFRX_DR0_V_Pos           (25U)

+#define SPDIFRX_DR0_V_Msk           (0x1UL << SPDIFRX_DR0_V_Pos)               /*!< 0x02000000 */

+#define SPDIFRX_DR0_V               SPDIFRX_DR0_V_Msk                          /*!<Validity bit          */

+#define SPDIFRX_DR0_U_Pos           (26U)

+#define SPDIFRX_DR0_U_Msk           (0x1UL << SPDIFRX_DR0_U_Pos)               /*!< 0x04000000 */

+#define SPDIFRX_DR0_U               SPDIFRX_DR0_U_Msk                          /*!<User bit              */

+#define SPDIFRX_DR0_C_Pos           (27U)

+#define SPDIFRX_DR0_C_Msk           (0x1UL << SPDIFRX_DR0_C_Pos)               /*!< 0x08000000 */

+#define SPDIFRX_DR0_C               SPDIFRX_DR0_C_Msk                          /*!<Channel Status bit    */

+#define SPDIFRX_DR0_PT_Pos          (28U)

+#define SPDIFRX_DR0_PT_Msk          (0x3UL << SPDIFRX_DR0_PT_Pos)              /*!< 0x30000000 */

+#define SPDIFRX_DR0_PT              SPDIFRX_DR0_PT_Msk                         /*!<Preamble Type         */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/

+#define SPDIFRX_DR1_DR_Pos          (8U)

+#define SPDIFRX_DR1_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)         /*!< 0xFFFFFF00 */

+#define SPDIFRX_DR1_DR              SPDIFRX_DR1_DR_Msk                         /*!<Data value            */

+#define SPDIFRX_DR1_PT_Pos          (4U)

+#define SPDIFRX_DR1_PT_Msk          (0x3UL << SPDIFRX_DR1_PT_Pos)              /*!< 0x00000030 */

+#define SPDIFRX_DR1_PT              SPDIFRX_DR1_PT_Msk                         /*!<Preamble Type         */

+#define SPDIFRX_DR1_C_Pos           (3U)

+#define SPDIFRX_DR1_C_Msk           (0x1UL << SPDIFRX_DR1_C_Pos)               /*!< 0x00000008 */

+#define SPDIFRX_DR1_C               SPDIFRX_DR1_C_Msk                          /*!<Channel Status bit    */

+#define SPDIFRX_DR1_U_Pos           (2U)

+#define SPDIFRX_DR1_U_Msk           (0x1UL << SPDIFRX_DR1_U_Pos)               /*!< 0x00000004 */

+#define SPDIFRX_DR1_U               SPDIFRX_DR1_U_Msk                          /*!<User bit              */

+#define SPDIFRX_DR1_V_Pos           (1U)

+#define SPDIFRX_DR1_V_Msk           (0x1UL << SPDIFRX_DR1_V_Pos)               /*!< 0x00000002 */

+#define SPDIFRX_DR1_V               SPDIFRX_DR1_V_Msk                          /*!<Validity bit          */

+#define SPDIFRX_DR1_PE_Pos          (0U)

+#define SPDIFRX_DR1_PE_Msk          (0x1UL << SPDIFRX_DR1_PE_Pos)              /*!< 0x00000001 */

+#define SPDIFRX_DR1_PE              SPDIFRX_DR1_PE_Msk                         /*!<Parity Error bit      */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/

+#define SPDIFRX_DR1_DRNL1_Pos       (16U)

+#define SPDIFRX_DR1_DRNL1_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)        /*!< 0xFFFF0000 */

+#define SPDIFRX_DR1_DRNL1           SPDIFRX_DR1_DRNL1_Msk                      /*!<Data value Channel B      */

+#define SPDIFRX_DR1_DRNL2_Pos       (0U)

+#define SPDIFRX_DR1_DRNL2_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)        /*!< 0x0000FFFF */

+#define SPDIFRX_DR1_DRNL2           SPDIFRX_DR1_DRNL2_Msk                      /*!<Data value Channel A      */

+

+/*******************  Bit definition for SPDIFRX_CSR register   *******************/

+#define SPDIFRX_CSR_USR_Pos         (0U)

+#define SPDIFRX_CSR_USR_Msk         (0xFFFFUL << SPDIFRX_CSR_USR_Pos)          /*!< 0x0000FFFF */

+#define SPDIFRX_CSR_USR             SPDIFRX_CSR_USR_Msk                        /*!<User data information           */

+#define SPDIFRX_CSR_CS_Pos          (16U)

+#define SPDIFRX_CSR_CS_Msk          (0xFFUL << SPDIFRX_CSR_CS_Pos)             /*!< 0x00FF0000 */

+#define SPDIFRX_CSR_CS              SPDIFRX_CSR_CS_Msk                         /*!<Channel A status information    */

+#define SPDIFRX_CSR_SOB_Pos         (24U)

+#define SPDIFRX_CSR_SOB_Msk         (0x1UL << SPDIFRX_CSR_SOB_Pos)             /*!< 0x01000000 */

+#define SPDIFRX_CSR_SOB             SPDIFRX_CSR_SOB_Msk                        /*!<Start Of Block                  */

+

+/*******************  Bit definition for SPDIFRX_DIR register    *******************/

+#define SPDIFRX_DIR_THI_Pos         (0U)

+#define SPDIFRX_DIR_THI_Msk         (0x1FFFUL << SPDIFRX_DIR_THI_Pos)          /*!< 0x00001FFF */

+#define SPDIFRX_DIR_THI             SPDIFRX_DIR_THI_Msk                        /*!<Threshold LOW      */

+#define SPDIFRX_DIR_TLO_Pos         (16U)

+#define SPDIFRX_DIR_TLO_Msk         (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)          /*!< 0x1FFF0000 */

+#define SPDIFRX_DIR_TLO             SPDIFRX_DIR_TLO_Msk                        /*!<Threshold HIGH     */

+

+/*******************  Bit definition for SPDIFRX_VERR register    *******************/

+#define SPDIFRX_VERR_MINREV_Pos     (0U)

+#define SPDIFRX_VERR_MINREV_Msk     (0xFUL << SPDIFRX_VERR_MINREV_Pos)         /*!< 0x0000000F */

+#define SPDIFRX_VERR_MINREV         SPDIFRX_VERR_MINREV_Msk                    /*!<SPDIFRX Minor revision     */

+#define SPDIFRX_VERR_MAJREV_Pos     (4U)

+#define SPDIFRX_VERR_MAJREV_Msk     (0xFUL << SPDIFRX_VERR_MAJREV_Pos)         /*!< 0x000000F0 */

+#define SPDIFRX_VERR_MAJREV         SPDIFRX_VERR_MAJREV_Msk                    /*!<SPDIFRX Major revision     */

+

+/*******************  Bit definition for SPDIFRX_IDR register    *******************/

+#define SPDIFRX_IDR_ID_Pos          (0U)

+#define SPDIFRX_IDR_ID_Msk          (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos)       /*!< 0xFFFFFFFF */

+#define SPDIFRX_IDR_ID              SPDIFRX_IDR_ID_Msk                         /*!<SPDIFRX identifier     */

+

+/*******************  Bit definition for SPDIFRX_SIDR register    *******************/

+#define SPDIFRX_SIDR_SID_Pos        (0U)

+#define SPDIFRX_SIDR_SID_Msk        (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos)     /*!< 0xFFFFFFFF */

+#define SPDIFRX_SIDR_SID            SPDIFRX_SIDR_SID_Msk                       /*!<Size of the memory region allocated to SPDIFRX registers */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          Serial Audio Interface                            */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  SAI VERSION  ********************************/

+#define SAI_VER_V2_X

+

+/********************  Bit definition for SAI_GCR register  *******************/

+#define SAI_GCR_SYNCIN_Pos         (0U)

+#define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000003 */

+#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */

+#define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */

+#define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */

+

+#define SAI_GCR_SYNCOUT_Pos        (4U)

+#define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000030 */

+#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */

+#define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */

+#define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */

+

+/*******************  Bit definition for SAI_xCR1 register  *******************/

+#define SAI_xCR1_MODE_Pos          (0U)

+#define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */

+#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */

+#define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */

+#define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */

+

+#define SAI_xCR1_PRTCFG_Pos        (2U)

+#define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */

+#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */

+#define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */

+#define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */

+

+#define SAI_xCR1_DS_Pos            (5U)

+#define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */

+#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */

+#define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */

+#define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */

+#define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */

+

+#define SAI_xCR1_LSBFIRST_Pos      (8U)

+#define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */

+#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */

+#define SAI_xCR1_CKSTR_Pos         (9U)

+#define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */

+#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */

+

+#define SAI_xCR1_SYNCEN_Pos        (10U)

+#define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */

+#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */

+#define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */

+#define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */

+

+#define SAI_xCR1_MONO_Pos          (12U)

+#define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */

+#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */

+#define SAI_xCR1_OUTDRIV_Pos       (13U)

+#define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */

+#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */

+#define SAI_xCR1_SAIEN_Pos         (16U)

+#define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */

+#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */

+#define SAI_xCR1_DMAEN_Pos         (17U)

+#define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */

+#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */

+#define SAI_xCR1_NODIV_Pos         (19U)

+#define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */

+#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */

+

+#define SAI_xCR1_MCKDIV_Pos        (20U)

+#define SAI_xCR1_MCKDIV_Msk        (0x3FUL << SAI_xCR1_MCKDIV_Pos)             /*!< 0x03F00000 */

+#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[5:0] (Master ClocK Divider)  */

+#define SAI_xCR1_MCKDIV_0          (0x01UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00100000 */

+#define SAI_xCR1_MCKDIV_1          (0x02UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00200000 */

+#define SAI_xCR1_MCKDIV_2          (0x04UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00400000 */

+#define SAI_xCR1_MCKDIV_3          (0x08UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00800000 */

+#define SAI_xCR1_MCKDIV_4          (0x10UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x01000000 */

+#define SAI_xCR1_MCKDIV_5          (0x20UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x02000000 */

+

+#define SAI_xCR1_MCKEN_Pos         (27U)

+#define SAI_xCR1_MCKEN_Msk         (0x1UL << SAI_xCR1_MCKEN_Pos)               /*!< 0x08000000 */

+#define SAI_xCR1_MCKEN             SAI_xCR1_MCKEN_Msk                          /*!<Master ClocK enable */

+

+#define SAI_xCR1_OSR_Pos           (26U)

+#define SAI_xCR1_OSR_Msk           (0x1UL << SAI_xCR1_OSR_Pos)                 /*!< 0x04000000 */

+#define SAI_xCR1_OSR               SAI_xCR1_OSR_Msk                            /*!<OverSampling Ratio for master clock  */

+

+/* Legacy define */

+#define  SAI_xCR1_NOMCK               SAI_xCR1_NODIV

+

+/*******************  Bit definition for SAI_xCR2 register  *******************/

+#define SAI_xCR2_FTH_Pos           (0U)

+#define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */

+#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */

+#define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */

+#define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */

+#define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */

+

+#define SAI_xCR2_FFLUSH_Pos        (3U)

+#define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */

+#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */

+#define SAI_xCR2_TRIS_Pos          (4U)

+#define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */

+#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */

+#define SAI_xCR2_MUTE_Pos          (5U)

+#define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */

+#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */

+#define SAI_xCR2_MUTEVAL_Pos       (6U)

+#define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */

+#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */

+

+#define SAI_xCR2_MUTECNT_Pos       (7U)

+#define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */

+#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */

+#define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */

+#define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */

+#define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */

+#define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */

+#define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */

+#define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */

+

+#define SAI_xCR2_CPL_Pos           (13U)

+#define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */

+#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */

+

+#define SAI_xCR2_COMP_Pos          (14U)

+#define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */

+#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */

+#define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */

+#define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */

+

+/******************  Bit definition for SAI_xFRCR register  *******************/

+#define SAI_xFRCR_FRL_Pos          (0U)

+#define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */

+#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](FRame Length)  */

+#define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */

+#define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */

+#define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */

+#define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */

+#define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */

+#define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */

+#define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */

+#define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */

+

+#define SAI_xFRCR_FSALL_Pos        (8U)

+#define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */

+#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FSALL[6:0] (Frame Synchronization Active Level Length)  */

+#define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */

+#define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */

+#define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */

+#define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */

+#define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */

+#define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */

+#define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */

+

+#define SAI_xFRCR_FSDEF_Pos        (16U)

+#define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */

+#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!<Frame Synchronization Definition  */

+#define SAI_xFRCR_FSPOL_Pos        (17U)

+#define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */

+#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */

+#define SAI_xFRCR_FSOFF_Pos        (18U)

+#define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */

+#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */

+

+/* Legacy define */

+#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL

+

+/******************  Bit definition for SAI_xSLOTR register  *******************/

+#define SAI_xSLOTR_FBOFF_Pos       (0U)

+#define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */

+#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FBOFF[4:0](First Bit Offset)  */

+#define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */

+#define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */

+#define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */

+#define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */

+#define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */

+

+#define SAI_xSLOTR_SLOTSZ_Pos      (6U)

+#define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */

+#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */

+#define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */

+#define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */

+

+#define SAI_xSLOTR_NBSLOT_Pos      (8U)

+#define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */

+#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */

+#define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */

+#define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */

+#define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */

+#define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */

+

+#define SAI_xSLOTR_SLOTEN_Pos      (16U)

+#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */

+#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */

+

+/*******************  Bit definition for SAI_xIMR register  *******************/

+#define SAI_xIMR_OVRUDRIE_Pos      (0U)

+#define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */

+#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */

+#define SAI_xIMR_MUTEDETIE_Pos     (1U)

+#define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */

+#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */

+#define SAI_xIMR_WCKCFGIE_Pos      (2U)

+#define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */

+#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */

+#define SAI_xIMR_FREQIE_Pos        (3U)

+#define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */

+#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */

+#define SAI_xIMR_CNRDYIE_Pos       (4U)

+#define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */

+#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */

+#define SAI_xIMR_AFSDETIE_Pos      (5U)

+#define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */

+#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */

+#define SAI_xIMR_LFSDETIE_Pos      (6U)

+#define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */

+#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */

+

+/********************  Bit definition for SAI_xSR register  *******************/

+#define SAI_xSR_OVRUDR_Pos         (0U)

+#define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */

+#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */

+#define SAI_xSR_MUTEDET_Pos        (1U)

+#define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */

+#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */

+#define SAI_xSR_WCKCFG_Pos         (2U)

+#define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */

+#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */

+#define SAI_xSR_FREQ_Pos           (3U)

+#define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */

+#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */

+#define SAI_xSR_CNRDY_Pos          (4U)

+#define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */

+#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */

+#define SAI_xSR_AFSDET_Pos         (5U)

+#define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */

+#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */

+#define SAI_xSR_LFSDET_Pos         (6U)

+#define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */

+#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */

+

+#define SAI_xSR_FLVL_Pos           (16U)

+#define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */

+#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */

+#define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */

+#define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */

+#define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */

+

+/******************  Bit definition for SAI_xCLRFR register  ******************/

+#define SAI_xCLRFR_COVRUDR_Pos     (0U)

+#define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */

+#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */

+#define SAI_xCLRFR_CMUTEDET_Pos    (1U)

+#define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */

+#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */

+#define SAI_xCLRFR_CWCKCFG_Pos     (2U)

+#define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */

+#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */

+#define SAI_xCLRFR_CFREQ_Pos       (3U)

+#define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */

+#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */

+#define SAI_xCLRFR_CCNRDY_Pos      (4U)

+#define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */

+#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */

+#define SAI_xCLRFR_CAFSDET_Pos     (5U)

+#define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */

+#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */

+#define SAI_xCLRFR_CLFSDET_Pos     (6U)

+#define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */

+#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */

+

+/******************  Bit definition for SAI_xDR register  *********************/

+#define SAI_xDR_DATA_Pos           (0U)

+#define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */

+#define SAI_xDR_DATA               SAI_xDR_DATA_Msk

+

+/*******************  Bit definition for SAI_PDMCR register  ******************/

+#define SAI_PDMCR_PDMEN_Pos        (0U)

+#define SAI_PDMCR_PDMEN_Msk        (0x1UL << SAI_PDMCR_PDMEN_Pos)              /*!< 0x00000001 */

+#define SAI_PDMCR_PDMEN            SAI_PDMCR_PDMEN_Msk                         /*!<PDM Enable                                          */

+

+#define SAI_PDMCR_MICNBR_Pos       (4U)

+#define SAI_PDMCR_MICNBR_Msk       (0x3UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000030 */

+#define SAI_PDMCR_MICNBR           SAI_PDMCR_MICNBR_Msk                        /*!<Number of microphones                               */

+#define SAI_PDMCR_MICNBR_0         (0x1UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000010 */

+#define SAI_PDMCR_MICNBR_1         (0x2UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000020 */

+

+#define SAI_PDMCR_CKEN1_Pos        (8U)

+#define SAI_PDMCR_CKEN1_Msk        (0x1UL << SAI_PDMCR_CKEN1_Pos)              /*!< 0x00000100 */

+#define SAI_PDMCR_CKEN1            SAI_PDMCR_CKEN1_Msk                         /*!<Clock enable of bitstream clock number 1            */

+#define SAI_PDMCR_CKEN2_Pos        (9U)

+#define SAI_PDMCR_CKEN2_Msk        (0x1UL << SAI_PDMCR_CKEN2_Pos)              /*!< 0x00000200 */

+#define SAI_PDMCR_CKEN2            SAI_PDMCR_CKEN2_Msk                         /*!<Clock enable of bitstream clock number 2            */

+#define SAI_PDMCR_CKEN3_Pos        (10U)

+#define SAI_PDMCR_CKEN3_Msk        (0x1UL << SAI_PDMCR_CKEN3_Pos)              /*!< 0x00000400 */

+#define SAI_PDMCR_CKEN3            SAI_PDMCR_CKEN3_Msk                         /*!<Clock enable of bitstream clock number 3            */

+#define SAI_PDMCR_CKEN4_Pos        (11U)

+#define SAI_PDMCR_CKEN4_Msk        (0x1UL << SAI_PDMCR_CKEN4_Pos)              /*!< 0x00000800 */

+#define SAI_PDMCR_CKEN4            SAI_PDMCR_CKEN4_Msk                         /*!<Clock enable of bitstream clock number 4            */

+

+/******************  Bit definition for SAI_PDMDLY register  ******************/

+#define SAI_PDMDLY_DLYM1L_Pos      (0U)

+#define SAI_PDMDLY_DLYM1L_Msk      (0x7UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000007 */

+#define SAI_PDMDLY_DLYM1L          SAI_PDMDLY_DLYM1L_Msk                       /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */

+#define SAI_PDMDLY_DLYM1L_0        (0x1UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000001 */

+#define SAI_PDMDLY_DLYM1L_1        (0x2UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000002 */

+#define SAI_PDMDLY_DLYM1L_2        (0x4UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000004 */

+

+#define SAI_PDMDLY_DLYM1R_Pos      (4U)

+#define SAI_PDMDLY_DLYM1R_Msk      (0x7UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000070 */

+#define SAI_PDMDLY_DLYM1R          SAI_PDMDLY_DLYM1R_Msk                       /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */

+#define SAI_PDMDLY_DLYM1R_0        (0x1UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000010 */

+#define SAI_PDMDLY_DLYM1R_1        (0x2UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000020 */

+#define SAI_PDMDLY_DLYM1R_2        (0x4UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000040 */

+

+#define SAI_PDMDLY_DLYM2L_Pos      (8U)

+#define SAI_PDMDLY_DLYM2L_Msk      (0x7UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000700 */

+#define SAI_PDMDLY_DLYM2L          SAI_PDMDLY_DLYM2L_Msk                       /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */

+#define SAI_PDMDLY_DLYM2L_0        (0x1UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000100 */

+#define SAI_PDMDLY_DLYM2L_1        (0x2UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000200 */

+#define SAI_PDMDLY_DLYM2L_2        (0x4UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000400 */

+

+#define SAI_PDMDLY_DLYM2R_Pos      (12U)

+#define SAI_PDMDLY_DLYM2R_Msk      (0x7UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00007000 */

+#define SAI_PDMDLY_DLYM2R          SAI_PDMDLY_DLYM2R_Msk                       /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/

+#define SAI_PDMDLY_DLYM2R_0        (0x1UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00001000 */

+#define SAI_PDMDLY_DLYM2R_1        (0x2UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00002000 */

+#define SAI_PDMDLY_DLYM2R_2        (0x4UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00004000 */

+

+#define SAI_PDMDLY_DLYM3L_Pos      (16U)

+#define SAI_PDMDLY_DLYM3L_Msk      (0x7UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00070000 */

+#define SAI_PDMDLY_DLYM3L          SAI_PDMDLY_DLYM3L_Msk                       /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/

+#define SAI_PDMDLY_DLYM3L_0        (0x1UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00010000 */

+#define SAI_PDMDLY_DLYM3L_1        (0x2UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00020000 */

+#define SAI_PDMDLY_DLYM3L_2        (0x4UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00040000 */

+

+#define SAI_PDMDLY_DLYM3R_Pos      (20U)

+#define SAI_PDMDLY_DLYM3R_Msk      (0x7UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00700000 */

+#define SAI_PDMDLY_DLYM3R          SAI_PDMDLY_DLYM3R_Msk                       /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/

+#define SAI_PDMDLY_DLYM3R_0        (0x1UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00100000 */

+#define SAI_PDMDLY_DLYM3R_1        (0x2UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00200000 */

+#define SAI_PDMDLY_DLYM3R_2        (0x4UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00400000 */

+

+#define SAI_PDMDLY_DLYM4L_Pos      (24U)

+#define SAI_PDMDLY_DLYM4L_Msk      (0x7UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x07000000 */

+#define SAI_PDMDLY_DLYM4L          SAI_PDMDLY_DLYM4L_Msk                       /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/

+#define SAI_PDMDLY_DLYM4L_0        (0x1UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x01000000 */

+#define SAI_PDMDLY_DLYM4L_1        (0x2UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x02000000 */

+#define SAI_PDMDLY_DLYM4L_2        (0x4UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x04000000 */

+

+#define SAI_PDMDLY_DLYM4R_Pos      (28U)

+#define SAI_PDMDLY_DLYM4R_Msk      (0x7UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x70000000 */

+#define SAI_PDMDLY_DLYM4R          SAI_PDMDLY_DLYM4R_Msk                       /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/

+#define SAI_PDMDLY_DLYM4R_0        (0x1UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x10000000 */

+#define SAI_PDMDLY_DLYM4R_1        (0x2UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x20000000 */

+#define SAI_PDMDLY_DLYM4R_2        (0x4UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x40000000 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           SDMMC Interface                                  */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for SDMMC_POWER register  ******************/

+#define SDMMC_POWER_PWRCTRL_Pos          (0U)

+#define SDMMC_POWER_PWRCTRL_Msk          (0x3UL << SDMMC_POWER_PWRCTRL_Pos)    /*!< 0x00000003 */

+#define SDMMC_POWER_PWRCTRL              SDMMC_POWER_PWRCTRL_Msk               /*!<PWRCTRL[1:0] bits (Power supply control bits) */

+#define SDMMC_POWER_PWRCTRL_0            (0x1UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000001 */

+#define SDMMC_POWER_PWRCTRL_1            (0x2UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000002 */

+#define SDMMC_POWER_VSWITCH_Pos          (2U)

+#define SDMMC_POWER_VSWITCH_Msk          (0x1UL << SDMMC_POWER_VSWITCH_Pos)    /*!< 0x00000004 */

+#define SDMMC_POWER_VSWITCH              SDMMC_POWER_VSWITCH_Msk               /*!<Voltage switch sequence start */

+#define SDMMC_POWER_VSWITCHEN_Pos        (3U)

+#define SDMMC_POWER_VSWITCHEN_Msk        (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)  /*!< 0x00000008 */

+#define SDMMC_POWER_VSWITCHEN            SDMMC_POWER_VSWITCHEN_Msk             /*!<Voltage switch procedure enable */

+#define SDMMC_POWER_DIRPOL_Pos           (4U)

+#define SDMMC_POWER_DIRPOL_Msk           (0x1UL << SDMMC_POWER_DIRPOL_Pos)     /*!< 0x00000010 */

+#define SDMMC_POWER_DIRPOL               SDMMC_POWER_DIRPOL_Msk                /*!<Data and Command direction signals polarity selection */

+

+/******************  Bit definition for SDMMC_CLKCR register  ******************/

+#define SDMMC_CLKCR_CLKDIV_Pos           (0U)

+#define SDMMC_CLKCR_CLKDIV_Msk           (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)   /*!< 0x000003FF */

+#define SDMMC_CLKCR_CLKDIV               SDMMC_CLKCR_CLKDIV_Msk                /*!<Clock divide factor             */

+#define SDMMC_CLKCR_PWRSAV_Pos           (12U)

+#define SDMMC_CLKCR_PWRSAV_Msk           (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)     /*!< 0x00001000 */

+#define SDMMC_CLKCR_PWRSAV               SDMMC_CLKCR_PWRSAV_Msk                /*!<Power saving configuration bit  */

+

+#define SDMMC_CLKCR_WIDBUS_Pos           (14U)

+#define SDMMC_CLKCR_WIDBUS_Msk           (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)     /*!< 0x0000C000 */

+#define SDMMC_CLKCR_WIDBUS               SDMMC_CLKCR_WIDBUS_Msk                /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */

+#define SDMMC_CLKCR_WIDBUS_0             (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00004000 */

+#define SDMMC_CLKCR_WIDBUS_1             (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00008000 */

+

+#define SDMMC_CLKCR_NEGEDGE_Pos          (16U)

+#define SDMMC_CLKCR_NEGEDGE_Msk          (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)    /*!< 0x00010000 */

+#define SDMMC_CLKCR_NEGEDGE              SDMMC_CLKCR_NEGEDGE_Msk               /*!<SDMMC_CK dephasing selection bit */

+#define SDMMC_CLKCR_HWFC_EN_Pos          (17U)

+#define SDMMC_CLKCR_HWFC_EN_Msk          (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)    /*!< 0x00020000 */

+#define SDMMC_CLKCR_HWFC_EN              SDMMC_CLKCR_HWFC_EN_Msk               /*!<HW Flow Control enable           */

+#define SDMMC_CLKCR_DDR_Pos              (18U)

+#define SDMMC_CLKCR_DDR_Msk              (0x1UL << SDMMC_CLKCR_DDR_Pos)        /*!< 0x00040000 */

+#define SDMMC_CLKCR_DDR                  SDMMC_CLKCR_DDR_Msk                   /*!<Data rate signaling selection    */

+#define SDMMC_CLKCR_BUSSPEED_Pos         (19U)

+#define SDMMC_CLKCR_BUSSPEED_Msk         (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)   /*!< 0x00080000 */

+#define SDMMC_CLKCR_BUSSPEED             SDMMC_CLKCR_BUSSPEED_Msk              /*!<Bus speed mode selection         */

+#define SDMMC_CLKCR_SELCLKRX_Pos         (20U)

+#define SDMMC_CLKCR_SELCLKRX_Msk         (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)   /*!< 0x00300000 */

+#define SDMMC_CLKCR_SELCLKRX             SDMMC_CLKCR_SELCLKRX_Msk              /*!<SELCLKRX[1:0] bits (Receive clock selection) */

+#define SDMMC_CLKCR_SELCLKRX_0           (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00100000 */

+#define SDMMC_CLKCR_SELCLKRX_1           (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00200000 */

+

+/*******************  Bit definition for SDMMC_ARG register  *******************/

+#define SDMMC_ARG_CMDARG_Pos             (0U)

+#define SDMMC_ARG_CMDARG_Msk             (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_ARG_CMDARG                 SDMMC_ARG_CMDARG_Msk                  /*!<Command argument */

+

+/*******************  Bit definition for SDMMC_CMD register  *******************/

+#define SDMMC_CMD_CMDINDEX_Pos           (0U)

+#define SDMMC_CMD_CMDINDEX_Msk           (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)    /*!< 0x0000003F */

+#define SDMMC_CMD_CMDINDEX               SDMMC_CMD_CMDINDEX_Msk                /*!<Command Index                               */

+#define SDMMC_CMD_CMDTRANS_Pos           (6U)

+#define SDMMC_CMD_CMDTRANS_Msk           (0x1UL << SDMMC_CMD_CMDTRANS_Pos)     /*!< 0x00000040 */

+#define SDMMC_CMD_CMDTRANS               SDMMC_CMD_CMDTRANS_Msk                /*!<CPSM Treats command as a Data Transfer      */

+#define SDMMC_CMD_CMDSTOP_Pos            (7U)

+#define SDMMC_CMD_CMDSTOP_Msk            (0x1UL << SDMMC_CMD_CMDSTOP_Pos)      /*!< 0x00000080 */

+#define SDMMC_CMD_CMDSTOP                SDMMC_CMD_CMDSTOP_Msk                 /*!<CPSM Treats command as a Stop               */

+

+#define SDMMC_CMD_WAITRESP_Pos           (8U)

+#define SDMMC_CMD_WAITRESP_Msk           (0x3UL << SDMMC_CMD_WAITRESP_Pos)     /*!< 0x00000300 */

+#define SDMMC_CMD_WAITRESP               SDMMC_CMD_WAITRESP_Msk                /*!<WAITRESP[1:0] bits (Wait for response bits) */

+#define SDMMC_CMD_WAITRESP_0             (0x1UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000100 */

+#define SDMMC_CMD_WAITRESP_1             (0x2UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000200 */

+

+#define SDMMC_CMD_WAITINT_Pos            (10U)

+#define SDMMC_CMD_WAITINT_Msk            (0x1UL << SDMMC_CMD_WAITINT_Pos)      /*!< 0x00000400 */

+#define SDMMC_CMD_WAITINT                SDMMC_CMD_WAITINT_Msk                 /*!<CPSM Waits for Interrupt Request                               */

+#define SDMMC_CMD_WAITPEND_Pos           (11U)

+#define SDMMC_CMD_WAITPEND_Msk           (0x1UL << SDMMC_CMD_WAITPEND_Pos)     /*!< 0x00000800 */

+#define SDMMC_CMD_WAITPEND               SDMMC_CMD_WAITPEND_Msk                /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */

+#define SDMMC_CMD_CPSMEN_Pos             (12U)

+#define SDMMC_CMD_CPSMEN_Msk             (0x1UL << SDMMC_CMD_CPSMEN_Pos)       /*!< 0x00001000 */

+#define SDMMC_CMD_CPSMEN                 SDMMC_CMD_CPSMEN_Msk                  /*!<Command path state machine (CPSM) Enable bit                   */

+#define SDMMC_CMD_DTHOLD_Pos             (13U)

+#define SDMMC_CMD_DTHOLD_Msk             (0x1UL << SDMMC_CMD_DTHOLD_Pos)       /*!< 0x00002000 */

+#define SDMMC_CMD_DTHOLD                 SDMMC_CMD_DTHOLD_Msk                  /*!<Hold new data block transmission and reception in the DPSM     */

+#define SDMMC_CMD_BOOTMODE_Pos           (14U)

+#define SDMMC_CMD_BOOTMODE_Msk           (0x1UL << SDMMC_CMD_BOOTMODE_Pos)     /*!< 0x00004000 */

+#define SDMMC_CMD_BOOTMODE               SDMMC_CMD_BOOTMODE_Msk                /*!<Boot mode                                                      */

+#define SDMMC_CMD_BOOTEN_Pos             (15U)

+#define SDMMC_CMD_BOOTEN_Msk             (0x1UL << SDMMC_CMD_BOOTEN_Pos)       /*!< 0x00008000 */

+#define SDMMC_CMD_BOOTEN                 SDMMC_CMD_BOOTEN_Msk                  /*!<Enable Boot mode procedure                                     */

+#define SDMMC_CMD_CMDSUSPEND_Pos         (16U)

+#define SDMMC_CMD_CMDSUSPEND_Msk         (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)   /*!< 0x00010000 */

+#define SDMMC_CMD_CMDSUSPEND             SDMMC_CMD_CMDSUSPEND_Msk              /*!<CPSM Treats command as a Suspend or Resume command             */

+

+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/

+#define SDMMC_RESPCMD_RESPCMD_Pos        (0U)

+#define SDMMC_RESPCMD_RESPCMD_Msk        (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */

+#define SDMMC_RESPCMD_RESPCMD            SDMMC_RESPCMD_RESPCMD_Msk             /*!<Response command index */

+

+/******************  Bit definition for SDMMC_RESP0 register  ******************/

+#define SDMMC_RESP0_CARDSTATUS0_Pos      (0U)

+#define SDMMC_RESP0_CARDSTATUS0_Msk      (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP0_CARDSTATUS0          SDMMC_RESP0_CARDSTATUS0_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP1 register  ******************/

+#define SDMMC_RESP1_CARDSTATUS1_Pos      (0U)

+#define SDMMC_RESP1_CARDSTATUS1_Msk      (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP1_CARDSTATUS1          SDMMC_RESP1_CARDSTATUS1_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP2 register  ******************/

+#define SDMMC_RESP2_CARDSTATUS2_Pos      (0U)

+#define SDMMC_RESP2_CARDSTATUS2_Msk      (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP2_CARDSTATUS2          SDMMC_RESP2_CARDSTATUS2_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP3 register  ******************/

+#define SDMMC_RESP3_CARDSTATUS3_Pos      (0U)

+#define SDMMC_RESP3_CARDSTATUS3_Msk      (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP3_CARDSTATUS3          SDMMC_RESP3_CARDSTATUS3_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP4 register  ******************/

+#define SDMMC_RESP4_CARDSTATUS4_Pos      (0U)

+#define SDMMC_RESP4_CARDSTATUS4_Msk      (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP4_CARDSTATUS4          SDMMC_RESP4_CARDSTATUS4_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_DTIMER register  *****************/

+#define SDMMC_DTIMER_DATATIME_Pos        (0U)

+#define SDMMC_DTIMER_DATATIME_Msk        (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_DTIMER_DATATIME            SDMMC_DTIMER_DATATIME_Msk             /*!<Data timeout period. */

+

+/******************  Bit definition for SDMMC_DLEN register  *******************/

+#define SDMMC_DLEN_DATALENGTH_Pos        (0U)

+#define SDMMC_DLEN_DATALENGTH_Msk        (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_DLEN_DATALENGTH            SDMMC_DLEN_DATALENGTH_Msk             /*!<Data length value    */

+

+/******************  Bit definition for SDMMC_DCTRL register  ******************/

+#define SDMMC_DCTRL_DTEN_Pos             (0U)

+#define SDMMC_DCTRL_DTEN_Msk             (0x1UL << SDMMC_DCTRL_DTEN_Pos)       /*!< 0x00000001 */

+#define SDMMC_DCTRL_DTEN                 SDMMC_DCTRL_DTEN_Msk                  /*!<Data transfer enabled bit                */

+#define SDMMC_DCTRL_DTDIR_Pos            (1U)

+#define SDMMC_DCTRL_DTDIR_Msk            (0x1UL << SDMMC_DCTRL_DTDIR_Pos)      /*!< 0x00000002 */

+#define SDMMC_DCTRL_DTDIR                SDMMC_DCTRL_DTDIR_Msk                 /*!<Data transfer direction selection        */

+#define SDMMC_DCTRL_DTMODE_Pos           (2U)

+#define SDMMC_DCTRL_DTMODE_Msk           (0x3UL << SDMMC_DCTRL_DTMODE_Pos)     /*!< 0x0000000C */

+#define SDMMC_DCTRL_DTMODE               SDMMC_DCTRL_DTMODE_Msk                /*!<DTMODE[1:0] Data transfer mode selection */

+#define SDMMC_DCTRL_DTMODE_0             (0x1UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000004 */

+#define SDMMC_DCTRL_DTMODE_1             (0x2UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000008 */

+

+#define SDMMC_DCTRL_DBLOCKSIZE_Pos       (4U)

+#define SDMMC_DCTRL_DBLOCKSIZE_Msk       (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */

+#define SDMMC_DCTRL_DBLOCKSIZE           SDMMC_DCTRL_DBLOCKSIZE_Msk            /*!<DBLOCKSIZE[3:0] bits (Data block size) */

+#define SDMMC_DCTRL_DBLOCKSIZE_0         (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000010 */

+#define SDMMC_DCTRL_DBLOCKSIZE_1         (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000020 */

+#define SDMMC_DCTRL_DBLOCKSIZE_2         (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000040 */

+#define SDMMC_DCTRL_DBLOCKSIZE_3         (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000080 */

+

+#define SDMMC_DCTRL_RWSTART_Pos          (8U)

+#define SDMMC_DCTRL_RWSTART_Msk          (0x1UL << SDMMC_DCTRL_RWSTART_Pos)    /*!< 0x00000100 */

+#define SDMMC_DCTRL_RWSTART              SDMMC_DCTRL_RWSTART_Msk               /*!<Read wait start                                 */

+#define SDMMC_DCTRL_RWSTOP_Pos           (9U)

+#define SDMMC_DCTRL_RWSTOP_Msk           (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)     /*!< 0x00000200 */

+#define SDMMC_DCTRL_RWSTOP               SDMMC_DCTRL_RWSTOP_Msk                /*!<Read wait stop                                  */

+#define SDMMC_DCTRL_RWMOD_Pos            (10U)

+#define SDMMC_DCTRL_RWMOD_Msk            (0x1UL << SDMMC_DCTRL_RWMOD_Pos)      /*!< 0x00000400 */

+#define SDMMC_DCTRL_RWMOD                SDMMC_DCTRL_RWMOD_Msk                 /*!<Read wait mode                                  */

+#define SDMMC_DCTRL_SDIOEN_Pos           (11U)

+#define SDMMC_DCTRL_SDIOEN_Msk           (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)     /*!< 0x00000800 */

+#define SDMMC_DCTRL_SDIOEN               SDMMC_DCTRL_SDIOEN_Msk                /*!<SD I/O enable functions                         */

+#define SDMMC_DCTRL_BOOTACKEN_Pos        (12U)

+#define SDMMC_DCTRL_BOOTACKEN_Msk        (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)  /*!< 0x00001000 */

+#define SDMMC_DCTRL_BOOTACKEN            SDMMC_DCTRL_BOOTACKEN_Msk             /*!<Enable the reception of the Boot Acknowledgment */

+#define SDMMC_DCTRL_FIFORST_Pos          (13U)

+#define SDMMC_DCTRL_FIFORST_Msk          (0x1UL << SDMMC_DCTRL_FIFORST_Pos)    /*!< 0x00002000 */

+#define SDMMC_DCTRL_FIFORST              SDMMC_DCTRL_FIFORST_Msk               /*!<FIFO reset                                      */

+

+/******************  Bit definition for SDMMC_DCOUNT register  *****************/

+#define SDMMC_DCOUNT_DATACOUNT_Pos       (0U)

+#define SDMMC_DCOUNT_DATACOUNT_Msk       (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_DCOUNT_DATACOUNT           SDMMC_DCOUNT_DATACOUNT_Msk            /*!<Data count value */

+

+/******************  Bit definition for SDMMC_STA register  ********************/

+#define SDMMC_STA_CCRCFAIL_Pos           (0U)

+#define SDMMC_STA_CCRCFAIL_Msk           (0x1UL << SDMMC_STA_CCRCFAIL_Pos)     /*!< 0x00000001 */

+#define SDMMC_STA_CCRCFAIL               SDMMC_STA_CCRCFAIL_Msk                /*!<Command response received (CRC check failed)  */

+#define SDMMC_STA_DCRCFAIL_Pos           (1U)

+#define SDMMC_STA_DCRCFAIL_Msk           (0x1UL << SDMMC_STA_DCRCFAIL_Pos)     /*!< 0x00000002 */

+#define SDMMC_STA_DCRCFAIL               SDMMC_STA_DCRCFAIL_Msk                /*!<Data block sent/received (CRC check failed)   */

+#define SDMMC_STA_CTIMEOUT_Pos           (2U)

+#define SDMMC_STA_CTIMEOUT_Msk           (0x1UL << SDMMC_STA_CTIMEOUT_Pos)     /*!< 0x00000004 */

+#define SDMMC_STA_CTIMEOUT               SDMMC_STA_CTIMEOUT_Msk                /*!<Command response timeout                      */

+#define SDMMC_STA_DTIMEOUT_Pos           (3U)

+#define SDMMC_STA_DTIMEOUT_Msk           (0x1UL << SDMMC_STA_DTIMEOUT_Pos)     /*!< 0x00000008 */

+#define SDMMC_STA_DTIMEOUT               SDMMC_STA_DTIMEOUT_Msk                /*!<Data timeout                                  */

+#define SDMMC_STA_TXUNDERR_Pos           (4U)

+#define SDMMC_STA_TXUNDERR_Msk           (0x1UL << SDMMC_STA_TXUNDERR_Pos)     /*!< 0x00000010 */

+#define SDMMC_STA_TXUNDERR               SDMMC_STA_TXUNDERR_Msk                /*!<Transmit FIFO underrun error                  */

+#define SDMMC_STA_RXOVERR_Pos            (5U)

+#define SDMMC_STA_RXOVERR_Msk            (0x1UL << SDMMC_STA_RXOVERR_Pos)      /*!< 0x00000020 */

+#define SDMMC_STA_RXOVERR                SDMMC_STA_RXOVERR_Msk                 /*!<Received FIFO overrun error                   */

+#define SDMMC_STA_CMDREND_Pos            (6U)

+#define SDMMC_STA_CMDREND_Msk            (0x1UL << SDMMC_STA_CMDREND_Pos)      /*!< 0x00000040 */

+#define SDMMC_STA_CMDREND                SDMMC_STA_CMDREND_Msk                 /*!<Command response received (CRC check passed)  */

+#define SDMMC_STA_CMDSENT_Pos            (7U)

+#define SDMMC_STA_CMDSENT_Msk            (0x1UL << SDMMC_STA_CMDSENT_Pos)      /*!< 0x00000080 */

+#define SDMMC_STA_CMDSENT                SDMMC_STA_CMDSENT_Msk                 /*!<Command sent (no response required)           */

+#define SDMMC_STA_DATAEND_Pos            (8U)

+#define SDMMC_STA_DATAEND_Msk            (0x1UL << SDMMC_STA_DATAEND_Pos)      /*!< 0x00000100 */

+#define SDMMC_STA_DATAEND                SDMMC_STA_DATAEND_Msk                 /*!<Data end (data counter, SDIDCOUNT, is zero)   */

+#define SDMMC_STA_DHOLD_Pos              (9U)

+#define SDMMC_STA_DHOLD_Msk              (0x1UL << SDMMC_STA_DHOLD_Pos)        /*!< 0x00000200 */

+#define SDMMC_STA_DHOLD                  SDMMC_STA_DHOLD_Msk                   /*!<Data transfer Hold                                                      */

+#define SDMMC_STA_DBCKEND_Pos            (10U)

+#define SDMMC_STA_DBCKEND_Msk            (0x1UL << SDMMC_STA_DBCKEND_Pos)      /*!< 0x00000400 */

+#define SDMMC_STA_DBCKEND                SDMMC_STA_DBCKEND_Msk                 /*!<Data block sent/received (CRC check passed)   */

+#define SDMMC_STA_DABORT_Pos             (11U)

+#define SDMMC_STA_DABORT_Msk             (0x1UL << SDMMC_STA_DABORT_Pos)       /*!< 0x00000800 */

+#define SDMMC_STA_DABORT                 SDMMC_STA_DABORT_Msk                  /*!<Data transfer aborted by CMD12                                          */

+#define SDMMC_STA_DPSMACT_Pos            (12U)

+#define SDMMC_STA_DPSMACT_Msk            (0x1UL << SDMMC_STA_DPSMACT_Pos)      /*!< 0x00001000 */

+#define SDMMC_STA_DPSMACT                SDMMC_STA_DPSMACT_Msk                 /*!<Data path state machine active                                       */

+#define SDMMC_STA_CPSMACT_Pos            (13U)

+#define SDMMC_STA_CPSMACT_Msk            (0x1UL << SDMMC_STA_CPSMACT_Pos)      /*!< 0x00002000 */

+#define SDMMC_STA_CPSMACT                SDMMC_STA_CPSMACT_Msk                 /*!<Command path state machine active                                          */

+#define SDMMC_STA_TXFIFOHE_Pos           (14U)

+#define SDMMC_STA_TXFIFOHE_Msk           (0x1UL << SDMMC_STA_TXFIFOHE_Pos)     /*!< 0x00004000 */

+#define SDMMC_STA_TXFIFOHE               SDMMC_STA_TXFIFOHE_Msk                /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */

+#define SDMMC_STA_RXFIFOHF_Pos           (15U)

+#define SDMMC_STA_RXFIFOHF_Msk           (0x1UL << SDMMC_STA_RXFIFOHF_Pos)     /*!< 0x00008000 */

+#define SDMMC_STA_RXFIFOHF               SDMMC_STA_RXFIFOHF_Msk                /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */

+#define SDMMC_STA_TXFIFOF_Pos            (16U)

+#define SDMMC_STA_TXFIFOF_Msk            (0x1UL << SDMMC_STA_TXFIFOF_Pos)      /*!< 0x00010000 */

+#define SDMMC_STA_TXFIFOF                SDMMC_STA_TXFIFOF_Msk                 /*!<Transmit FIFO full                            */

+#define SDMMC_STA_RXFIFOF_Pos            (17U)

+#define SDMMC_STA_RXFIFOF_Msk            (0x1UL << SDMMC_STA_RXFIFOF_Pos)      /*!< 0x00020000 */

+#define SDMMC_STA_RXFIFOF                SDMMC_STA_RXFIFOF_Msk                 /*!<Receive FIFO full                             */

+#define SDMMC_STA_TXFIFOE_Pos            (18U)

+#define SDMMC_STA_TXFIFOE_Msk            (0x1UL << SDMMC_STA_TXFIFOE_Pos)      /*!< 0x00040000 */

+#define SDMMC_STA_TXFIFOE                SDMMC_STA_TXFIFOE_Msk                 /*!<Transmit FIFO empty                           */

+#define SDMMC_STA_RXFIFOE_Pos            (19U)

+#define SDMMC_STA_RXFIFOE_Msk            (0x1UL << SDMMC_STA_RXFIFOE_Pos)      /*!< 0x00080000 */

+#define SDMMC_STA_RXFIFOE                SDMMC_STA_RXFIFOE_Msk                 /*!<Receive FIFO empty                            */

+#define SDMMC_STA_BUSYD0_Pos             (20U)

+#define SDMMC_STA_BUSYD0_Msk             (0x1UL << SDMMC_STA_BUSYD0_Pos)       /*!< 0x00100000 */

+#define SDMMC_STA_BUSYD0                 SDMMC_STA_BUSYD0_Msk                  /*!<Inverted value of SDMMC_D0 line (Busy)                                  */

+#define SDMMC_STA_BUSYD0END_Pos          (21U)

+#define SDMMC_STA_BUSYD0END_Msk          (0x1UL << SDMMC_STA_BUSYD0END_Pos)    /*!< 0x00200000 */

+#define SDMMC_STA_BUSYD0END              SDMMC_STA_BUSYD0END_Msk               /*!<End of SDMMC_D0 Busy following a CMD response detected                  */

+#define SDMMC_STA_SDIOIT_Pos             (22U)

+#define SDMMC_STA_SDIOIT_Msk             (0x1UL << SDMMC_STA_SDIOIT_Pos)       /*!< 0x00400000 */

+#define SDMMC_STA_SDIOIT                 SDMMC_STA_SDIOIT_Msk                  /*!<SDIO interrupt received                                                 */

+#define SDMMC_STA_ACKFAIL_Pos            (23U)

+#define SDMMC_STA_ACKFAIL_Msk            (0x1UL << SDMMC_STA_ACKFAIL_Pos)      /*!< 0x00800000 */

+#define SDMMC_STA_ACKFAIL                SDMMC_STA_ACKFAIL_Msk                 /*!<Boot Acknowledgment received (BootAck check fail)                       */

+#define SDMMC_STA_ACKTIMEOUT_Pos         (24U)

+#define SDMMC_STA_ACKTIMEOUT_Msk         (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)   /*!< 0x01000000 */

+#define SDMMC_STA_ACKTIMEOUT             SDMMC_STA_ACKTIMEOUT_Msk              /*!<Boot Acknowledgment timeout                                             */

+#define SDMMC_STA_VSWEND_Pos             (25U)

+#define SDMMC_STA_VSWEND_Msk             (0x1UL << SDMMC_STA_VSWEND_Pos)       /*!< 0x02000000 */

+#define SDMMC_STA_VSWEND                 SDMMC_STA_VSWEND_Msk                  /*!<Voltage switch critical timing section completion                       */

+#define SDMMC_STA_CKSTOP_Pos             (26U)

+#define SDMMC_STA_CKSTOP_Msk             (0x1UL << SDMMC_STA_CKSTOP_Pos)       /*!< 0x04000000 */

+#define SDMMC_STA_CKSTOP                 SDMMC_STA_CKSTOP_Msk                  /*!<SDMMC_CK stopped in Voltage switch procedure                            */

+#define SDMMC_STA_IDMATE_Pos             (27U)

+#define SDMMC_STA_IDMATE_Msk             (0x1UL << SDMMC_STA_IDMATE_Pos)       /*!< 0x08000000 */

+#define SDMMC_STA_IDMATE                 SDMMC_STA_IDMATE_Msk                  /*!<IDMA transfer error                                                     */

+#define SDMMC_STA_IDMABTC_Pos            (28U)

+#define SDMMC_STA_IDMABTC_Msk            (0x1UL << SDMMC_STA_IDMABTC_Pos)      /*!< 0x10000000 */

+#define SDMMC_STA_IDMABTC                SDMMC_STA_IDMABTC_Msk                 /*!<IDMA buffer transfer complete                                           */

+

+/*******************  Bit definition for SDMMC_ICR register  *******************/

+#define SDMMC_ICR_CCRCFAILC_Pos          (0U)

+#define SDMMC_ICR_CCRCFAILC_Msk          (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)    /*!< 0x00000001 */

+#define SDMMC_ICR_CCRCFAILC              SDMMC_ICR_CCRCFAILC_Msk               /*!<CCRCFAIL flag clear bit */

+#define SDMMC_ICR_DCRCFAILC_Pos          (1U)

+#define SDMMC_ICR_DCRCFAILC_Msk          (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)    /*!< 0x00000002 */

+#define SDMMC_ICR_DCRCFAILC              SDMMC_ICR_DCRCFAILC_Msk               /*!<DCRCFAIL flag clear bit */

+#define SDMMC_ICR_CTIMEOUTC_Pos          (2U)

+#define SDMMC_ICR_CTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)    /*!< 0x00000004 */

+#define SDMMC_ICR_CTIMEOUTC              SDMMC_ICR_CTIMEOUTC_Msk               /*!<CTIMEOUT flag clear bit */

+#define SDMMC_ICR_DTIMEOUTC_Pos          (3U)

+#define SDMMC_ICR_DTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)    /*!< 0x00000008 */

+#define SDMMC_ICR_DTIMEOUTC              SDMMC_ICR_DTIMEOUTC_Msk               /*!<DTIMEOUT flag clear bit */

+#define SDMMC_ICR_TXUNDERRC_Pos          (4U)

+#define SDMMC_ICR_TXUNDERRC_Msk          (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)    /*!< 0x00000010 */

+#define SDMMC_ICR_TXUNDERRC              SDMMC_ICR_TXUNDERRC_Msk               /*!<TXUNDERR flag clear bit */

+#define SDMMC_ICR_RXOVERRC_Pos           (5U)

+#define SDMMC_ICR_RXOVERRC_Msk           (0x1UL << SDMMC_ICR_RXOVERRC_Pos)     /*!< 0x00000020 */

+#define SDMMC_ICR_RXOVERRC               SDMMC_ICR_RXOVERRC_Msk                /*!<RXOVERR flag clear bit  */

+#define SDMMC_ICR_CMDRENDC_Pos           (6U)

+#define SDMMC_ICR_CMDRENDC_Msk           (0x1UL << SDMMC_ICR_CMDRENDC_Pos)     /*!< 0x00000040 */

+#define SDMMC_ICR_CMDRENDC               SDMMC_ICR_CMDRENDC_Msk                /*!<CMDREND flag clear bit  */

+#define SDMMC_ICR_CMDSENTC_Pos           (7U)

+#define SDMMC_ICR_CMDSENTC_Msk           (0x1UL << SDMMC_ICR_CMDSENTC_Pos)     /*!< 0x00000080 */

+#define SDMMC_ICR_CMDSENTC               SDMMC_ICR_CMDSENTC_Msk                /*!<CMDSENT flag clear bit  */

+#define SDMMC_ICR_DATAENDC_Pos           (8U)

+#define SDMMC_ICR_DATAENDC_Msk           (0x1UL << SDMMC_ICR_DATAENDC_Pos)     /*!< 0x00000100 */

+#define SDMMC_ICR_DATAENDC               SDMMC_ICR_DATAENDC_Msk                /*!<DATAEND flag clear bit  */

+#define SDMMC_ICR_DHOLDC_Pos             (9U)

+#define SDMMC_ICR_DHOLDC_Msk             (0x1UL << SDMMC_ICR_DHOLDC_Pos)       /*!< 0x00000200 */

+#define SDMMC_ICR_DHOLDC                 SDMMC_ICR_DHOLDC_Msk                  /*!<DHOLD flag clear bit       */

+#define SDMMC_ICR_DBCKENDC_Pos           (10U)

+#define SDMMC_ICR_DBCKENDC_Msk           (0x1UL << SDMMC_ICR_DBCKENDC_Pos)     /*!< 0x00000400 */

+#define SDMMC_ICR_DBCKENDC               SDMMC_ICR_DBCKENDC_Msk                /*!<DBCKEND flag clear bit  */

+#define SDMMC_ICR_DABORTC_Pos            (11U)

+#define SDMMC_ICR_DABORTC_Msk            (0x1UL << SDMMC_ICR_DABORTC_Pos)      /*!< 0x00000800 */

+#define SDMMC_ICR_DABORTC                SDMMC_ICR_DABORTC_Msk                 /*!<DABORTC flag clear bit     */

+#define SDMMC_ICR_BUSYD0ENDC_Pos         (21U)

+#define SDMMC_ICR_BUSYD0ENDC_Msk         (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)   /*!< 0x00200000 */

+#define SDMMC_ICR_BUSYD0ENDC             SDMMC_ICR_BUSYD0ENDC_Msk              /*!<BUSYD0ENDC flag clear bit  */

+#define SDMMC_ICR_SDIOITC_Pos            (22U)

+#define SDMMC_ICR_SDIOITC_Msk            (0x1UL << SDMMC_ICR_SDIOITC_Pos)      /*!< 0x00400000 */

+#define SDMMC_ICR_SDIOITC                SDMMC_ICR_SDIOITC_Msk                 /*!<SDIOIT flag clear bit      */

+#define SDMMC_ICR_ACKFAILC_Pos           (23U)

+#define SDMMC_ICR_ACKFAILC_Msk           (0x1UL << SDMMC_ICR_ACKFAILC_Pos)     /*!< 0x00800000 */

+#define SDMMC_ICR_ACKFAILC               SDMMC_ICR_ACKFAILC_Msk                /*!<ACKFAILC flag clear bit    */

+#define SDMMC_ICR_ACKTIMEOUTC_Pos        (24U)

+#define SDMMC_ICR_ACKTIMEOUTC_Msk        (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)  /*!< 0x01000000 */

+#define SDMMC_ICR_ACKTIMEOUTC            SDMMC_ICR_ACKTIMEOUTC_Msk             /*!<ACKTIMEOUTC flag clear bit */

+#define SDMMC_ICR_VSWENDC_Pos            (25U)

+#define SDMMC_ICR_VSWENDC_Msk            (0x1UL << SDMMC_ICR_VSWENDC_Pos)      /*!< 0x02000000 */

+#define SDMMC_ICR_VSWENDC                SDMMC_ICR_VSWENDC_Msk                 /*!<VSWENDC flag clear bit     */

+#define SDMMC_ICR_CKSTOPC_Pos            (26U)

+#define SDMMC_ICR_CKSTOPC_Msk            (0x1UL << SDMMC_ICR_CKSTOPC_Pos)      /*!< 0x04000000 */

+#define SDMMC_ICR_CKSTOPC                SDMMC_ICR_CKSTOPC_Msk                 /*!<CKSTOPC flag clear bit     */

+#define SDMMC_ICR_IDMATEC_Pos            (27U)

+#define SDMMC_ICR_IDMATEC_Msk            (0x1UL << SDMMC_ICR_IDMATEC_Pos)      /*!< 0x08000000 */

+#define SDMMC_ICR_IDMATEC                SDMMC_ICR_IDMATEC_Msk                 /*!<IDMATEC flag clear bit     */

+#define SDMMC_ICR_IDMABTCC_Pos           (28U)

+#define SDMMC_ICR_IDMABTCC_Msk           (0x1UL << SDMMC_ICR_IDMABTCC_Pos)     /*!< 0x10000000 */

+#define SDMMC_ICR_IDMABTCC               SDMMC_ICR_IDMABTCC_Msk                /*!<IDMABTCC flag clear bit    */

+

+/******************  Bit definition for SDMMC_MASK register  *******************/

+#define SDMMC_MASK_CCRCFAILIE_Pos        (0U)

+#define SDMMC_MASK_CCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)  /*!< 0x00000001 */

+#define SDMMC_MASK_CCRCFAILIE            SDMMC_MASK_CCRCFAILIE_Msk             /*!<Command CRC Fail Interrupt Enable          */

+#define SDMMC_MASK_DCRCFAILIE_Pos        (1U)

+#define SDMMC_MASK_DCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)  /*!< 0x00000002 */

+#define SDMMC_MASK_DCRCFAILIE            SDMMC_MASK_DCRCFAILIE_Msk             /*!<Data CRC Fail Interrupt Enable             */

+#define SDMMC_MASK_CTIMEOUTIE_Pos        (2U)

+#define SDMMC_MASK_CTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)  /*!< 0x00000004 */

+#define SDMMC_MASK_CTIMEOUTIE            SDMMC_MASK_CTIMEOUTIE_Msk             /*!<Command TimeOut Interrupt Enable           */

+#define SDMMC_MASK_DTIMEOUTIE_Pos        (3U)

+#define SDMMC_MASK_DTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)  /*!< 0x00000008 */

+#define SDMMC_MASK_DTIMEOUTIE            SDMMC_MASK_DTIMEOUTIE_Msk             /*!<Data TimeOut Interrupt Enable              */

+#define SDMMC_MASK_TXUNDERRIE_Pos        (4U)

+#define SDMMC_MASK_TXUNDERRIE_Msk        (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)  /*!< 0x00000010 */

+#define SDMMC_MASK_TXUNDERRIE            SDMMC_MASK_TXUNDERRIE_Msk             /*!<Tx FIFO UnderRun Error Interrupt Enable    */

+#define SDMMC_MASK_RXOVERRIE_Pos         (5U)

+#define SDMMC_MASK_RXOVERRIE_Msk         (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)   /*!< 0x00000020 */

+#define SDMMC_MASK_RXOVERRIE             SDMMC_MASK_RXOVERRIE_Msk              /*!<Rx FIFO OverRun Error Interrupt Enable     */

+#define SDMMC_MASK_CMDRENDIE_Pos         (6U)

+#define SDMMC_MASK_CMDRENDIE_Msk         (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)   /*!< 0x00000040 */

+#define SDMMC_MASK_CMDRENDIE             SDMMC_MASK_CMDRENDIE_Msk              /*!<Command Response Received Interrupt Enable */

+#define SDMMC_MASK_CMDSENTIE_Pos         (7U)

+#define SDMMC_MASK_CMDSENTIE_Msk         (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)   /*!< 0x00000080 */

+#define SDMMC_MASK_CMDSENTIE             SDMMC_MASK_CMDSENTIE_Msk              /*!<Command Sent Interrupt Enable              */

+#define SDMMC_MASK_DATAENDIE_Pos         (8U)

+#define SDMMC_MASK_DATAENDIE_Msk         (0x1UL << SDMMC_MASK_DATAENDIE_Pos)   /*!< 0x00000100 */

+#define SDMMC_MASK_DATAENDIE             SDMMC_MASK_DATAENDIE_Msk              /*!<Data End Interrupt Enable                  */

+#define SDMMC_MASK_DHOLDIE_Pos           (9U)

+#define SDMMC_MASK_DHOLDIE_Msk           (0x1UL << SDMMC_MASK_DHOLDIE_Pos)     /*!< 0x00000200 */

+#define SDMMC_MASK_DHOLDIE               SDMMC_MASK_DHOLDIE_Msk                /*!<Data Hold Interrupt Enable                 */

+#define SDMMC_MASK_DBCKENDIE_Pos         (10U)

+#define SDMMC_MASK_DBCKENDIE_Msk         (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)   /*!< 0x00000400 */

+#define SDMMC_MASK_DBCKENDIE             SDMMC_MASK_DBCKENDIE_Msk              /*!<Data Block End Interrupt Enable            */

+#define SDMMC_MASK_DABORTIE_Pos          (11U)

+#define SDMMC_MASK_DABORTIE_Msk          (0x1UL << SDMMC_MASK_DABORTIE_Pos)    /*!< 0x00000800 */

+#define SDMMC_MASK_DABORTIE              SDMMC_MASK_DABORTIE_Msk               /*!<Data transfer aborted interrupt enable     */

+

+#define SDMMC_MASK_TXFIFOHEIE_Pos        (14U)

+#define SDMMC_MASK_TXFIFOHEIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)  /*!< 0x00004000 */

+#define SDMMC_MASK_TXFIFOHEIE            SDMMC_MASK_TXFIFOHEIE_Msk             /*!<Tx FIFO Half Empty interrupt Enable        */

+#define SDMMC_MASK_RXFIFOHFIE_Pos        (15U)

+#define SDMMC_MASK_RXFIFOHFIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)  /*!< 0x00008000 */

+#define SDMMC_MASK_RXFIFOHFIE            SDMMC_MASK_RXFIFOHFIE_Msk             /*!<Rx FIFO Half Full interrupt Enable         */

+

+#define SDMMC_MASK_RXFIFOFIE_Pos         (17U)

+#define SDMMC_MASK_RXFIFOFIE_Msk         (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)   /*!< 0x00020000 */

+#define SDMMC_MASK_RXFIFOFIE             SDMMC_MASK_RXFIFOFIE_Msk              /*!<Rx FIFO Full interrupt Enable              */

+#define SDMMC_MASK_TXFIFOEIE_Pos         (18U)

+#define SDMMC_MASK_TXFIFOEIE_Msk         (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)   /*!< 0x00040000 */

+#define SDMMC_MASK_TXFIFOEIE             SDMMC_MASK_TXFIFOEIE_Msk              /*!<Tx FIFO Empty interrupt Enable             */

+

+#define SDMMC_MASK_BUSYD0ENDIE_Pos       (21U)

+#define SDMMC_MASK_BUSYD0ENDIE_Msk       (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */

+#define SDMMC_MASK_BUSYD0ENDIE           SDMMC_MASK_BUSYD0ENDIE_Msk            /*!<BUSYD0ENDIE interrupt Enable */

+#define SDMMC_MASK_SDIOITIE_Pos           (22U)

+#define SDMMC_MASK_SDIOITIE_Msk           (0x1UL << SDMMC_MASK_SDIOITIE_Pos)     /*!< 0x00400000 */

+#define SDMMC_MASK_SDIOITIE               SDMMC_MASK_SDIOITIE_Msk                /*!<SDMMC Mode Interrupt Received interrupt Enable */

+#define SDMMC_MASK_ACKFAILIE_Pos         (23U)

+#define SDMMC_MASK_ACKFAILIE_Msk         (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)   /*!< 0x00800000 */

+#define SDMMC_MASK_ACKFAILIE             SDMMC_MASK_ACKFAILIE_Msk              /*!<Acknowledgment Fail Interrupt Enable */

+#define SDMMC_MASK_ACKTIMEOUTIE_Pos      (24U)

+#define SDMMC_MASK_ACKTIMEOUTIE_Msk      (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */

+#define SDMMC_MASK_ACKTIMEOUTIE          SDMMC_MASK_ACKTIMEOUTIE_Msk           /*!<Acknowledgment timeout Interrupt Enable */

+#define SDMMC_MASK_VSWENDIE_Pos          (25U)

+#define SDMMC_MASK_VSWENDIE_Msk          (0x1UL << SDMMC_MASK_VSWENDIE_Pos)    /*!< 0x02000000 */

+#define SDMMC_MASK_VSWENDIE              SDMMC_MASK_VSWENDIE_Msk               /*!<Voltage switch critical timing section completion Interrupt Enable */

+#define SDMMC_MASK_CKSTOPIE_Pos          (26U)

+#define SDMMC_MASK_CKSTOPIE_Msk          (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)    /*!< 0x04000000 */

+#define SDMMC_MASK_CKSTOPIE              SDMMC_MASK_CKSTOPIE_Msk               /*!<Voltage Switch clock stopped Interrupt Enable */

+#define SDMMC_MASK_IDMABTCIE_Pos         (28U)

+#define SDMMC_MASK_IDMABTCIE_Msk         (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)   /*!< 0x10000000 */

+#define SDMMC_MASK_IDMABTCIE             SDMMC_MASK_IDMABTCIE_Msk              /*!<IDMA buffer transfer complete Interrupt Enable */

+

+/*****************  Bit definition for SDMMC_ACKTIME register  *****************/

+#define SDMMC_ACKTIME_ACKTIME_Pos        (0U)

+#define SDMMC_ACKTIME_ACKTIME_Msk        (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_ACKTIME_ACKTIME            SDMMC_ACKTIME_ACKTIME_Msk             /*!<Boot acknowledgment timeout period */

+

+/******************  Bit definition for SDMMC_FIFO register  *******************/

+#define SDMMC_FIFO_FIFODATA_Pos          (0U)

+#define SDMMC_FIFO_FIFODATA_Msk          (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_FIFO_FIFODATA              SDMMC_FIFO_FIFODATA_Msk               /*!<Receive and transmit FIFO data */

+

+/******************  Bit definition for SDMMC_IDMACTRL register ****************/

+#define SDMMC_IDMA_IDMAEN_Pos            (0U)

+#define SDMMC_IDMA_IDMAEN_Msk            (0x1UL << SDMMC_IDMA_IDMAEN_Pos)      /*!< 0x00000001 */

+#define SDMMC_IDMA_IDMAEN                SDMMC_IDMA_IDMAEN_Msk                 /*!< Enable the internal DMA of the SDMMC peripheral */

+#define SDMMC_IDMA_IDMABMODE_Pos         (1U)

+#define SDMMC_IDMA_IDMABMODE_Msk         (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)   /*!< 0x00000002 */

+#define SDMMC_IDMA_IDMABMODE             SDMMC_IDMA_IDMABMODE_Msk              /*!< Enable double buffer mode for IDMA */

+#define SDMMC_IDMA_IDMABACT_Pos          (2U)

+#define SDMMC_IDMA_IDMABACT_Msk          (0x1UL << SDMMC_IDMA_IDMABACT_Pos)    /*!< 0x00000004 */

+#define SDMMC_IDMA_IDMABACT              SDMMC_IDMA_IDMABACT_Msk               /*!< Uses buffer 1 when double buffer mode is selected */

+

+/*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/

+#define SDMMC_IDMABSIZE_IDMABNDT_Pos     (5U)

+#define SDMMC_IDMABSIZE_IDMABNDT_Msk     (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */

+#define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */

+

+/*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/

+#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */

+

+/*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/

+#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                        Delay Block Interface (DLYB)                        */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for DLYB_CR register  ********************/

+#define DLYB_CR_DEN_Pos         (0U)

+#define DLYB_CR_DEN_Msk         (0x1UL << DLYB_CR_DEN_Pos)                     /*!< 0x00000001 */

+#define DLYB_CR_DEN             DLYB_CR_DEN_Msk                                /*!<Delay Block enable */

+#define DLYB_CR_SEN_Pos         (1U)

+#define DLYB_CR_SEN_Msk         (0x1UL << DLYB_CR_SEN_Pos)                     /*!< 0x00000002 */

+#define DLYB_CR_SEN             DLYB_CR_SEN_Msk                                /*!<Sampler length enable */

+

+

+/*******************  Bit definition for DLYB_CFGR register  ********************/

+#define DLYB_CFGR_SEL_Pos       (0U)

+#define DLYB_CFGR_SEL_Msk       (0xFUL << DLYB_CFGR_SEL_Pos)                   /*!< 0x0000000F */

+#define DLYB_CFGR_SEL           DLYB_CFGR_SEL_Msk                              /*!<Select the phase for the Output clock[3:0] */

+#define DLYB_CFGR_SEL_0         (0x1UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000001 */

+#define DLYB_CFGR_SEL_1         (0x2UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000002 */

+#define DLYB_CFGR_SEL_2         (0x3UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000003 */

+#define DLYB_CFGR_SEL_3         (0x8UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000008 */

+

+#define DLYB_CFGR_UNIT_Pos      (8U)

+#define DLYB_CFGR_UNIT_Msk      (0x7FUL << DLYB_CFGR_UNIT_Pos)                 /*!< 0x00007F00 */

+#define DLYB_CFGR_UNIT          DLYB_CFGR_UNIT_Msk                             /*!<Delay Defines the delay of a Unit delay cell[6:0] */

+#define DLYB_CFGR_UNIT_0        (0x01UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000100 */

+#define DLYB_CFGR_UNIT_1        (0x02UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000200 */

+#define DLYB_CFGR_UNIT_2        (0x04UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000400 */

+#define DLYB_CFGR_UNIT_3        (0x08UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000800 */

+#define DLYB_CFGR_UNIT_4        (0x10UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00001000 */

+#define DLYB_CFGR_UNIT_5        (0x20UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00002000 */

+#define DLYB_CFGR_UNIT_6        (0x40UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00004000 */

+

+#define DLYB_CFGR_LNG_Pos       (16U)

+#define DLYB_CFGR_LNG_Msk       (0xFFFUL << DLYB_CFGR_LNG_Pos)                 /*!< 0x0FFF0000 */

+#define DLYB_CFGR_LNG           DLYB_CFGR_LNG_Msk                              /*!<Delay line length value[11:0] */

+#define DLYB_CFGR_LNG_0         (0x001UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00010000 */

+#define DLYB_CFGR_LNG_1         (0x002UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00020000 */

+#define DLYB_CFGR_LNG_2         (0x004UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00040000 */

+#define DLYB_CFGR_LNG_3         (0x008UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00080000 */

+#define DLYB_CFGR_LNG_4         (0x010UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00100000 */

+#define DLYB_CFGR_LNG_5         (0x020UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00200000 */

+#define DLYB_CFGR_LNG_6         (0x040UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00400000 */

+#define DLYB_CFGR_LNG_7         (0x080UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00800000 */

+#define DLYB_CFGR_LNG_8         (0x100UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x01000000 */

+#define DLYB_CFGR_LNG_9         (0x200UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x02000000 */

+#define DLYB_CFGR_LNG_10        (0x400UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x04000000 */

+#define DLYB_CFGR_LNG_11        (0x800UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x08000000 */

+

+#define DLYB_CFGR_LNGF_Pos      (31U)

+#define DLYB_CFGR_LNGF_Msk      (0x1UL << DLYB_CFGR_LNGF_Pos)                  /*!< 0x80000000 */

+#define DLYB_CFGR_LNGF          DLYB_CFGR_LNGF_Msk                             /*!<Length valid flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                   Serial Peripheral Interface (SPI/I2S)                    */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for SPI_CR1 register  ********************/

+#define SPI_CR1_SPE_Pos             (0U)

+#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000001 */

+#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<Serial Peripheral Enable                         */

+#define SPI_CR1_MASRX_Pos           (8U)

+#define SPI_CR1_MASRX_Msk           (0x1UL << SPI_CR1_MASRX_Pos)               /*!< 0x00000100 */

+#define SPI_CR1_MASRX               SPI_CR1_MASRX_Msk                          /*!<Master automatic SUSP in Receive mode            */

+#define SPI_CR1_CSTART_Pos          (9U)

+#define SPI_CR1_CSTART_Msk          (0x1UL << SPI_CR1_CSTART_Pos)              /*!< 0x00000200 */

+#define SPI_CR1_CSTART              SPI_CR1_CSTART_Msk                         /*!<Master transfer start                            */

+#define SPI_CR1_CSUSP_Pos           (10U)

+#define SPI_CR1_CSUSP_Msk           (0x1UL << SPI_CR1_CSUSP_Pos)               /*!< 0x00000400 */

+#define SPI_CR1_CSUSP               SPI_CR1_CSUSP_Msk                          /*!<Master SUSPend request                           */

+#define SPI_CR1_HDDIR_Pos           (11U)

+#define SPI_CR1_HDDIR_Msk           (0x1UL << SPI_CR1_HDDIR_Pos)               /*!< 0x00000800 */

+#define SPI_CR1_HDDIR               SPI_CR1_HDDIR_Msk                          /*!<Rx/Tx direction at Half-duplex mode              */

+#define SPI_CR1_SSI_Pos             (12U)

+#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00001000 */

+#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal SS signal input level                   */

+#define SPI_CR1_CRC33_17_Pos        (13U)

+#define SPI_CR1_CRC33_17_Msk        (0x1UL << SPI_CR1_CRC33_17_Pos)            /*!< 0x00002000 */

+#define SPI_CR1_CRC33_17             SPI_CR1_CRC33_17_Msk                      /*!<32-bit CRC polynomial configuration              */

+#define SPI_CR1_RCRCINI_Pos         (14U)

+#define SPI_CR1_RCRCINI_Msk         (0x1UL << SPI_CR1_RCRCINI_Pos)             /*!< 0x00004000 */

+#define SPI_CR1_RCRCINI             SPI_CR1_RCRCINI_Msk                        /*!<CRC init pattern control for receiver            */

+#define SPI_CR1_TCRCINI_Pos         (15U)

+#define SPI_CR1_TCRCINI_Msk         (0x1UL << SPI_CR1_TCRCINI_Pos)             /*!< 0x00008000 */

+#define SPI_CR1_TCRCINI             SPI_CR1_TCRCINI_Msk                        /*!<CRC init pattern control for transmitter         */

+#define SPI_CR1_IOLOCK_Pos          (16U)

+#define SPI_CR1_IOLOCK_Msk          (0x1UL << SPI_CR1_IOLOCK_Pos)              /*!< 0x00010000 */

+#define SPI_CR1_IOLOCK              SPI_CR1_IOLOCK_Msk                         /*!<Locking the AF configuration of associated IOs   */

+

+/*******************  Bit definition for SPI_CR2 register  ********************/

+#define SPI_CR2_TSER_Pos            (16U)

+#define SPI_CR2_TSER_Msk            (0xFFFFUL << SPI_CR2_TSER_Pos)             /*!< 0xFFFF0000 */

+#define SPI_CR2_TSER                SPI_CR2_TSER_Msk                           /*!<Number of data transfer extension                */

+#define SPI_CR2_TSIZE_Pos           (0U)

+#define SPI_CR2_TSIZE_Msk           (0xFFFFUL << SPI_CR2_TSIZE_Pos)            /*!< 0x0000FFFF */

+#define SPI_CR2_TSIZE               SPI_CR2_TSIZE_Msk                          /*!<Number of data at current transfer               */

+

+/*******************  Bit definition for SPI_CFG1 register  ********************/

+#define SPI_CFG1_DSIZE_Pos          (0U)

+#define SPI_CFG1_DSIZE_Msk          (0x1FUL << SPI_CFG1_DSIZE_Pos)             /*!< 0x0000001F */

+#define SPI_CFG1_DSIZE              SPI_CFG1_DSIZE_Msk                         /*!<DSIZE[4:0]: Bits number in single SPI data frame */

+#define SPI_CFG1_DSIZE_0            (0x01UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000001 */

+#define SPI_CFG1_DSIZE_1            (0x02UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000002 */

+#define SPI_CFG1_DSIZE_2            (0x04UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000004 */

+#define SPI_CFG1_DSIZE_3            (0x08UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000008 */

+#define SPI_CFG1_DSIZE_4            (0x10UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000010 */

+

+#define SPI_CFG1_FTHLV_Pos          (5U)

+#define SPI_CFG1_FTHLV_Msk          (0xFUL << SPI_CFG1_FTHLV_Pos)              /*!< 0x000001E0 */

+#define SPI_CFG1_FTHLV              SPI_CFG1_FTHLV_Msk                         /*!<FTHVL [3:0]: FIFO threshold level*/

+#define SPI_CFG1_FTHLV_0            (0x1UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000020 */

+#define SPI_CFG1_FTHLV_1            (0x2UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000040 */

+#define SPI_CFG1_FTHLV_2            (0x4UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000080 */

+#define SPI_CFG1_FTHLV_3            (0x8UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000100 */

+

+#define SPI_CFG1_UDRCFG_Pos         (9U)

+#define SPI_CFG1_UDRCFG_Msk         (0x3UL << SPI_CFG1_UDRCFG_Pos)             /*!< 0x00000600 */

+#define SPI_CFG1_UDRCFG             SPI_CFG1_UDRCFG_Msk                        /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */

+#define SPI_CFG1_UDRCFG_0           (0x1UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000200 */

+#define SPI_CFG1_UDRCFG_1           (0x2UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000400 */

+

+

+#define SPI_CFG1_UDRDET_Pos         (11U)

+#define SPI_CFG1_UDRDET_Msk         (0x3UL << SPI_CFG1_UDRDET_Pos)             /*!< 0x00001800 */

+#define SPI_CFG1_UDRDET             SPI_CFG1_UDRDET_Msk                        /*!<UDRDET[1:0]: Detection of underrun condition     */

+#define SPI_CFG1_UDRDET_0           (0x1UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00000800 */

+#define SPI_CFG1_UDRDET_1           (0x2UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00001000 */

+

+#define SPI_CFG1_RXDMAEN_Pos        (14U)

+#define SPI_CFG1_RXDMAEN_Msk        (0x1UL << SPI_CFG1_RXDMAEN_Pos)            /*!< 0x00004000 */

+#define SPI_CFG1_RXDMAEN            SPI_CFG1_RXDMAEN_Msk                       /*!<Rx DMA stream enable                */

+#define SPI_CFG1_TXDMAEN_Pos        (15U)

+#define SPI_CFG1_TXDMAEN_Msk        (0x1UL << SPI_CFG1_TXDMAEN_Pos)            /*!< 0x00008000 */

+#define SPI_CFG1_TXDMAEN            SPI_CFG1_TXDMAEN_Msk                       /*!<Tx DMA stream enable                */

+

+#define SPI_CFG1_CRCSIZE_Pos        (16U)

+#define SPI_CFG1_CRCSIZE_Msk        (0x1FUL << SPI_CFG1_CRCSIZE_Pos)           /*!< 0x001F0000 */

+#define SPI_CFG1_CRCSIZE            SPI_CFG1_CRCSIZE_Msk                       /*!<CRCSIZE [4:0]: Length of CRC frame*/

+#define SPI_CFG1_CRCSIZE_0          (0x01UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00010000 */

+#define SPI_CFG1_CRCSIZE_1          (0x02UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00020000 */

+#define SPI_CFG1_CRCSIZE_2          (0x04UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00040000 */

+#define SPI_CFG1_CRCSIZE_3          (0x08UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00080000 */

+#define SPI_CFG1_CRCSIZE_4          (0x10UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00100000 */

+

+#define SPI_CFG1_CRCEN_Pos          (22U)

+#define SPI_CFG1_CRCEN_Msk          (0x1UL << SPI_CFG1_CRCEN_Pos)              /*!< 0x00400000 */

+#define SPI_CFG1_CRCEN              SPI_CFG1_CRCEN_Msk                         /*!<Hardware CRC computation enable */

+

+#define SPI_CFG1_MBR_Pos            (28U)

+#define SPI_CFG1_MBR_Msk            (0x7UL << SPI_CFG1_MBR_Pos)                /*!< 0x70000000 */

+#define SPI_CFG1_MBR                SPI_CFG1_MBR_Msk                           /*!<Master baud rate                */

+#define SPI_CFG1_MBR_0              (0x1UL << SPI_CFG1_MBR_Pos)                 /*!< 0x10000000 */

+#define SPI_CFG1_MBR_1              (0x2UL << SPI_CFG1_MBR_Pos)                 /*!< 0x20000000 */

+#define SPI_CFG1_MBR_2              (0x4UL << SPI_CFG1_MBR_Pos)                 /*!< 0x40000000 */

+

+/*******************  Bit definition for SPI_CFG2 register  ********************/

+#define SPI_CFG2_MSSI_Pos           (0U)

+#define SPI_CFG2_MSSI_Msk           (0xFUL << SPI_CFG2_MSSI_Pos)               /*!< 0x0000000F */

+#define SPI_CFG2_MSSI               SPI_CFG2_MSSI_Msk                          /*!<Master SS Idleness */

+#define SPI_CFG2_MSSI_0             (0x1UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000001 */

+#define SPI_CFG2_MSSI_1             (0x2UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000002 */

+#define SPI_CFG2_MSSI_2             (0x4UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000004 */

+#define SPI_CFG2_MSSI_3             (0x8UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000008 */

+

+#define SPI_CFG2_MIDI_Pos           (4U)

+#define SPI_CFG2_MIDI_Msk           (0xFUL << SPI_CFG2_MIDI_Pos)               /*!< 0x000000F0 */

+#define SPI_CFG2_MIDI               SPI_CFG2_MIDI_Msk                          /*!<Master Inter-Data Idleness */

+#define SPI_CFG2_MIDI_0             (0x1UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000010 */

+#define SPI_CFG2_MIDI_1             (0x2UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000020 */

+#define SPI_CFG2_MIDI_2             (0x4UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000040 */

+#define SPI_CFG2_MIDI_3             (0x8UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000080 */

+

+#define SPI_CFG2_IOSWP_Pos          (15U)

+#define SPI_CFG2_IOSWP_Msk          (0x1UL << SPI_CFG2_IOSWP_Pos)              /*!< 0x00008000 */

+#define SPI_CFG2_IOSWP              SPI_CFG2_IOSWP_Msk                         /*!<Swap functionality of MISO and MOSI pins */

+

+#define SPI_CFG2_COMM_Pos           (17U)

+#define SPI_CFG2_COMM_Msk           (0x3UL << SPI_CFG2_COMM_Pos)               /*!< 0x00060000 */

+#define SPI_CFG2_COMM               SPI_CFG2_COMM_Msk                          /*!<COMM [1:0]: SPI Communication Mode*/

+#define SPI_CFG2_COMM_0             (0x1UL << SPI_CFG2_COMM_Pos)                /*!< 0x00020000 */

+#define SPI_CFG2_COMM_1             (0x2UL << SPI_CFG2_COMM_Pos)                /*!< 0x00040000 */

+

+#define SPI_CFG2_SP_Pos             (19U)

+#define SPI_CFG2_SP_Msk             (0x7UL << SPI_CFG2_SP_Pos)                 /*!< 0x00380000 */

+#define SPI_CFG2_SP                 SPI_CFG2_SP_Msk                            /*!<SP[2:0]: Serial Protocol */

+#define SPI_CFG2_SP_0               (0x1UL << SPI_CFG2_SP_Pos)                  /*!< 0x00080000 */

+#define SPI_CFG2_SP_1               (0x2UL << SPI_CFG2_SP_Pos)                  /*!< 0x00100000 */

+#define SPI_CFG2_SP_2               (0x4UL << SPI_CFG2_SP_Pos)                  /*!< 0x00200000 */

+

+#define SPI_CFG2_MASTER_Pos         (22U)

+#define SPI_CFG2_MASTER_Msk         (0x1UL << SPI_CFG2_MASTER_Pos)             /*!< 0x00400000 */

+#define SPI_CFG2_MASTER             SPI_CFG2_MASTER_Msk                        /*!<SPI Master           */

+#define SPI_CFG2_LSBFRST_Pos        (23U)

+#define SPI_CFG2_LSBFRST_Msk        (0x1UL << SPI_CFG2_LSBFRST_Pos)            /*!< 0x00800000 */

+#define SPI_CFG2_LSBFRST            SPI_CFG2_LSBFRST_Msk                       /*!<Data frame format               */

+#define SPI_CFG2_CPHA_Pos           (24U)

+#define SPI_CFG2_CPHA_Msk           (0x1UL << SPI_CFG2_CPHA_Pos)               /*!< 0x01000000 */

+#define SPI_CFG2_CPHA               SPI_CFG2_CPHA_Msk                          /*!<Clock Phase      */

+#define SPI_CFG2_CPOL_Pos           (25U)

+#define SPI_CFG2_CPOL_Msk           (0x1UL << SPI_CFG2_CPOL_Pos)               /*!< 0x02000000 */

+#define SPI_CFG2_CPOL               SPI_CFG2_CPOL_Msk                          /*!<Clock Polarity   */

+#define SPI_CFG2_SSM_Pos            (26U)

+#define SPI_CFG2_SSM_Msk            (0x1UL << SPI_CFG2_SSM_Pos)                /*!< 0x04000000 */

+#define SPI_CFG2_SSM                SPI_CFG2_SSM_Msk                           /*!<Software slave management */

+

+#define SPI_CFG2_SSIOP_Pos          (28U)

+#define SPI_CFG2_SSIOP_Msk          (0x1UL << SPI_CFG2_SSIOP_Pos)              /*!< 0x10000000 */

+#define SPI_CFG2_SSIOP              SPI_CFG2_SSIOP_Msk                         /*!<SS input/output polarity */

+#define SPI_CFG2_SSOE_Pos           (29U)

+#define SPI_CFG2_SSOE_Msk           (0x1UL << SPI_CFG2_SSOE_Pos)               /*!< 0x20000000 */

+#define SPI_CFG2_SSOE               SPI_CFG2_SSOE_Msk                          /*!<SS output enable */

+#define SPI_CFG2_SSOM_Pos           (30U)

+#define SPI_CFG2_SSOM_Msk           (0x1UL << SPI_CFG2_SSOM_Pos)               /*!< 0x40000000 */

+#define SPI_CFG2_SSOM               SPI_CFG2_SSOM_Msk                          /*!<SS output management in master mode */

+

+#define SPI_CFG2_AFCNTR_Pos         (31U)

+#define SPI_CFG2_AFCNTR_Msk         (0x1UL << SPI_CFG2_AFCNTR_Pos)             /*!< 0x80000000 */

+#define SPI_CFG2_AFCNTR             SPI_CFG2_AFCNTR_Msk                        /*!<Alternate function GPIOs control */

+

+/*******************  Bit definition for SPI_IER register  ********************/

+#define SPI_IER_RXPIE_Pos           (0U)

+#define SPI_IER_RXPIE_Msk           (0x1UL << SPI_IER_RXPIE_Pos)               /*!< 0x00000001 */

+#define SPI_IER_RXPIE               SPI_IER_RXPIE_Msk                          /*!<RXP Interrupt Enable            */

+#define SPI_IER_TXPIE_Pos           (1U)

+#define SPI_IER_TXPIE_Msk           (0x1UL << SPI_IER_TXPIE_Pos)               /*!< 0x00000002 */

+#define SPI_IER_TXPIE               SPI_IER_TXPIE_Msk                          /*!<TXP interrupt enable            */

+#define SPI_IER_DXPIE_Pos           (2U)

+#define SPI_IER_DXPIE_Msk           (0x1UL << SPI_IER_DXPIE_Pos)               /*!< 0x00000004 */

+#define SPI_IER_DXPIE               SPI_IER_DXPIE_Msk                          /*!<DXP interrupt enable            */

+#define SPI_IER_EOTIE_Pos           (3U)

+#define SPI_IER_EOTIE_Msk           (0x1UL << SPI_IER_EOTIE_Pos)               /*!< 0x00000008 */

+#define SPI_IER_EOTIE               SPI_IER_EOTIE_Msk                          /*!<EOT/SUSP/TXC interrupt enable   */

+#define SPI_IER_TXTFIE_Pos          (4U)

+#define SPI_IER_TXTFIE_Msk          (0x1UL << SPI_IER_TXTFIE_Pos)              /*!< 0x00000010 */

+#define SPI_IER_TXTFIE              SPI_IER_TXTFIE_Msk                         /*!<TXTF interrupt enable           */

+#define SPI_IER_UDRIE_Pos           (5U)

+#define SPI_IER_UDRIE_Msk           (0x1UL << SPI_IER_UDRIE_Pos)               /*!< 0x00000020 */

+#define SPI_IER_UDRIE               SPI_IER_UDRIE_Msk                          /*!<UDR interrupt enable            */

+#define SPI_IER_OVRIE_Pos           (6U)

+#define SPI_IER_OVRIE_Msk           (0x1UL << SPI_IER_OVRIE_Pos)               /*!< 0x00000040 */

+#define SPI_IER_OVRIE               SPI_IER_OVRIE_Msk                          /*!<OVR interrupt enable            */

+#define SPI_IER_CRCEIE_Pos          (7U)

+#define SPI_IER_CRCEIE_Msk          (0x1UL << SPI_IER_CRCEIE_Pos)               /*!< 0x00000080 */

+#define SPI_IER_CRCEIE              SPI_IER_CRCEIE_Msk                          /*!<CRCE interrupt enable           */

+#define SPI_IER_TIFREIE_Pos         (8U)

+#define SPI_IER_TIFREIE_Msk         (0x1UL << SPI_IER_TIFREIE_Pos)             /*!< 0x00000100 */

+#define SPI_IER_TIFREIE             SPI_IER_TIFREIE_Msk                        /*!<TI Frame Error interrupt enable */

+#define SPI_IER_MODFIE_Pos          (9U)

+#define SPI_IER_MODFIE_Msk          (0x1UL << SPI_IER_MODFIE_Pos)              /*!< 0x00000200 */

+#define SPI_IER_MODFIE              SPI_IER_MODFIE_Msk                         /*!<MODF interrupt enable           */

+#define SPI_IER_TSERFIE_Pos         (10U)

+#define SPI_IER_TSERFIE_Msk         (0x1UL << SPI_IER_TSERFIE_Pos)              /*!< 0x00000400 */

+#define SPI_IER_TSERFIE             SPI_IER_TSERFIE_Msk                        /*!<TSERF interrupt enable          */

+

+/*******************  Bit definition for SPI_SR register  ********************/

+#define SPI_SR_RXP_Pos              (0U)

+#define SPI_SR_RXP_Msk              (0x1UL << SPI_SR_RXP_Pos)                  /*!< 0x00000001 */

+#define SPI_SR_RXP                  SPI_SR_RXP_Msk                             /*!<Rx-Packet available             */

+#define SPI_SR_TXP_Pos              (1U)

+#define SPI_SR_TXP_Msk              (0x1UL << SPI_SR_TXP_Pos)                  /*!< 0x00000002 */

+#define SPI_SR_TXP                  SPI_SR_TXP_Msk                             /*!<Tx-Packet space available       */

+#define SPI_SR_DXP_Pos              (2U)

+#define SPI_SR_DXP_Msk              (0x1UL << SPI_SR_DXP_Pos)                  /*!< 0x00000004 */

+#define SPI_SR_DXP                  SPI_SR_DXP_Msk                             /*!<Duplex Packet available         */

+#define SPI_SR_EOT_Pos              (3U)

+#define SPI_SR_EOT_Msk              (0x1UL << SPI_SR_EOT_Pos)                  /*!< 0x00000008 */

+#define SPI_SR_EOT                  SPI_SR_EOT_Msk                             /*!<Duplex Packet available         */

+#define SPI_SR_TXTF_Pos             (4U)

+#define SPI_SR_TXTF_Msk             (0x1UL << SPI_SR_TXTF_Pos)                 /*!< 0x00000010 */

+#define SPI_SR_TXTF                 SPI_SR_TXTF_Msk                            /*!<Transmission Transfer Filled    */

+#define SPI_SR_UDR_Pos              (5U)

+#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000020 */

+#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<UDR at Slave transmission       */

+#define SPI_SR_OVR_Pos              (6U)

+#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */

+#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Rx-Packet available             */

+#define SPI_SR_CRCE_Pos             (7U)

+#define SPI_SR_CRCE_Msk             (0x1UL << SPI_SR_CRCE_Pos)                 /*!< 0x00000080 */

+#define SPI_SR_CRCE                 SPI_SR_CRCE_Msk                            /*!<CRC Error Detected              */

+#define SPI_SR_TIFRE_Pos            (8U)

+#define SPI_SR_TIFRE_Msk            (0x1UL << SPI_SR_TIFRE_Pos)                /*!< 0x00000100 */

+#define SPI_SR_TIFRE                SPI_SR_TIFRE_Msk                           /*!<TI frame format error Detected  */

+#define SPI_SR_MODF_Pos             (9U)

+#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000200 */

+#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode Fault Detected             */

+#define SPI_SR_TSERF_Pos            (10U)

+#define SPI_SR_TSERF_Msk            (0x1UL << SPI_SR_TSERF_Pos)                /*!< 0x00000400 */

+#define SPI_SR_TSERF                SPI_SR_TSERF_Msk                           /*!<Number of SPI data to be transacted reloaded     */

+#define SPI_SR_SUSP_Pos             (11U)

+#define SPI_SR_SUSP_Msk             (0x1UL << SPI_SR_SUSP_Pos)                 /*!< 0x00000800 */

+#define SPI_SR_SUSP                 SPI_SR_SUSP_Msk                            /*!<SUSP is set by hardware  */

+#define SPI_SR_TXC_Pos              (12U)

+#define SPI_SR_TXC_Msk              (0x1UL << SPI_SR_TXC_Pos)                  /*!< 0x00001000 */

+#define SPI_SR_TXC                  SPI_SR_TXC_Msk                             /*!<TxFIFO transmission complete */

+#define SPI_SR_RXPLVL_Pos           (13U)

+#define SPI_SR_RXPLVL_Msk           (0x3UL << SPI_SR_RXPLVL_Pos)               /*!< 0x00006000 */

+#define SPI_SR_RXPLVL               SPI_SR_RXPLVL_Msk                          /*!<RxFIFO Packing Level                             */

+#define SPI_SR_RXPLVL_0             (0x1UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00002000 */

+#define SPI_SR_RXPLVL_1             (0x2UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00004000 */

+#define SPI_SR_RXWNE_Pos            (15U)

+#define SPI_SR_RXWNE_Msk            (0x1UL << SPI_SR_RXWNE_Pos)                /*!< 0x00008000 */

+#define SPI_SR_RXWNE                SPI_SR_RXWNE_Msk                           /*!<Rx FIFO Word Not Empty                           */

+#define SPI_SR_CTSIZE_Pos           (16U)

+#define SPI_SR_CTSIZE_Msk           (0xFFFFUL << SPI_SR_CTSIZE_Pos)            /*!< 0xFFFF0000 */

+#define SPI_SR_CTSIZE               SPI_SR_CTSIZE_Msk                          /*!<Number of data frames remaining in TSIZE         */

+

+/*******************  Bit definition for SPI_IFCR register  ********************/

+#define SPI_IFCR_EOTC_Pos           (3U)

+#define SPI_IFCR_EOTC_Msk           (0x1UL << SPI_IFCR_EOTC_Pos)               /*!< 0x00000008 */

+#define SPI_IFCR_EOTC               SPI_IFCR_EOTC_Msk                          /*!<End Of Transfer flag clear              */

+#define SPI_IFCR_TXTFC_Pos          (4U)

+#define SPI_IFCR_TXTFC_Msk          (0x1UL << SPI_IFCR_TXTFC_Pos)              /*!< 0x00000010 */

+#define SPI_IFCR_TXTFC              SPI_IFCR_TXTFC_Msk                         /*!<Transmission Transfer Filled flag clear */

+#define SPI_IFCR_UDRC_Pos           (5U)

+#define SPI_IFCR_UDRC_Msk           (0x1UL << SPI_IFCR_UDRC_Pos)               /*!< 0x00000020 */

+#define SPI_IFCR_UDRC               SPI_IFCR_UDRC_Msk                          /*!<Underrun flag clear                     */

+#define SPI_IFCR_OVRC_Pos           (6U)

+#define SPI_IFCR_OVRC_Msk           (0x1UL << SPI_IFCR_OVRC_Pos)               /*!< 0x00000040 */

+#define SPI_IFCR_OVRC               SPI_IFCR_OVRC_Msk                          /*!<Overrun flag clear                      */

+#define SPI_IFCR_CRCEC_Pos          (7U)

+#define SPI_IFCR_CRCEC_Msk          (0x1UL << SPI_IFCR_CRCEC_Pos)              /*!< 0x00000080 */

+#define SPI_IFCR_CRCEC              SPI_IFCR_CRCEC_Msk                         /*!<CRC Error flag clear                    */

+#define SPI_IFCR_TIFREC_Pos         (8U)

+#define SPI_IFCR_TIFREC_Msk         (0x1UL << SPI_IFCR_TIFREC_Pos)             /*!< 0x00000100 */

+#define SPI_IFCR_TIFREC             SPI_IFCR_TIFREC_Msk                        /*!<TI frame format error flag clear        */

+#define SPI_IFCR_MODFC_Pos          (9U)

+#define SPI_IFCR_MODFC_Msk          (0x1UL << SPI_IFCR_MODFC_Pos)              /*!< 0x00000200 */

+#define SPI_IFCR_MODFC              SPI_IFCR_MODFC_Msk                         /*!<Mode Fault flag clear                   */

+#define SPI_IFCR_TSERFC_Pos         (10U)

+#define SPI_IFCR_TSERFC_Msk         (0x1UL << SPI_IFCR_TSERFC_Pos)             /*!< 0x00000400 */

+#define SPI_IFCR_TSERFC             SPI_IFCR_TSERFC_Msk                        /*!<TSERFC flag clear                       */

+#define SPI_IFCR_SUSPC_Pos          (11U)

+#define SPI_IFCR_SUSPC_Msk          (0x1UL << SPI_IFCR_SUSPC_Pos)              /*!< 0x00000800 */

+#define SPI_IFCR_SUSPC              SPI_IFCR_SUSPC_Msk                         /*!<SUSPend flag clear                      */

+

+/*******************  Bit definition for SPI_TXDR register  ********************/

+#define SPI_TXDR_TXDR_Pos           (0U)

+#define SPI_TXDR_TXDR_Msk           (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)        /*!< 0xFFFFFFFF */

+#define SPI_TXDR_TXDR               SPI_TXDR_TXDR_Msk                          /* Transmit Data Register */

+

+/*******************  Bit definition for SPI_RXDR register  ********************/

+#define SPI_RXDR_RXDR_Pos           (0U)

+#define SPI_RXDR_RXDR_Msk           (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)        /*!< 0xFFFFFFFF */

+#define SPI_RXDR_RXDR               SPI_RXDR_RXDR_Msk                          /* Receive Data Register  */

+

+/*******************  Bit definition for SPI_CRCPOLY register  ********************/

+#define SPI_CRCPOLY_CRCPOLY_Pos     (0U)

+#define SPI_CRCPOLY_CRCPOLY_Msk     (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)  /*!< 0xFFFFFFFF */

+#define SPI_CRCPOLY_CRCPOLY         SPI_CRCPOLY_CRCPOLY_Msk                    /* CRC Polynomial register  */

+

+/*******************  Bit definition for SPI_TXCRC register  ********************/

+#define SPI_TXCRC_TXCRC_Pos         (0U)

+#define SPI_TXCRC_TXCRC_Msk         (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_TXCRC_TXCRC             SPI_TXCRC_TXCRC_Msk                        /* CRCRegister for transmitter */

+

+/*******************  Bit definition for SPI_RXCRC register  ********************/

+#define SPI_RXCRC_RXCRC_Pos         (0U)

+#define SPI_RXCRC_RXCRC_Msk         (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_RXCRC_RXCRC             SPI_RXCRC_RXCRC_Msk                        /* CRCRegister for receiver */

+

+/*******************  Bit definition for SPI_UDRDR register  ********************/

+#define SPI_UDRDR_UDRDR_Pos         (0U)

+#define SPI_UDRDR_UDRDR_Msk         (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_UDRDR_UDRDR             SPI_UDRDR_UDRDR_Msk                        /* Data at slave underrun condition */

+

+/******************  Bit definition for SPI_I2SCFGR register  *****************/

+#define SPI_I2SCFGR_I2SMOD_Pos      (0U)

+#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000001 */

+#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */

+#define SPI_I2SCFGR_I2SCFG_Pos      (1U)

+#define SPI_I2SCFGR_I2SCFG_Msk      (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x0000000E */

+#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[2:0] I2S configuration mode                */

+#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000002 */

+#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000004 */

+#define SPI_I2SCFGR_I2SCFG_2        (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000008 */

+#define SPI_I2SCFGR_I2SSTD_Pos      (4U)

+#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */

+#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] I2S standard selection                */

+#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */

+#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */

+#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)

+#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */

+#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                         */

+#define SPI_I2SCFGR_DATLEN_Pos      (8U)

+#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000300 */

+#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] Data length to be transferred         */

+#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000100 */

+#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000200 */

+#define SPI_I2SCFGR_CHLEN_Pos       (10U)

+#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000400 */

+#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */

+#define SPI_I2SCFGR_CKPOL_Pos       (11U)

+#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000800 */

+#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<Steady state clock polarity                       */

+#define SPI_I2SCFGR_FIXCH_Pos       (12U)

+#define SPI_I2SCFGR_FIXCH_Msk       (0x1UL << SPI_I2SCFGR_FIXCH_Pos)           /*!< 0x00001000 */

+#define SPI_I2SCFGR_FIXCH           SPI_I2SCFGR_FIXCH_Msk                      /*!<Fixed channel length in SLAVE                     */

+#define SPI_I2SCFGR_WSINV_Pos       (13U)

+#define SPI_I2SCFGR_WSINV_Msk       (0x1UL << SPI_I2SCFGR_WSINV_Pos)           /*!< 0x00002000 */

+#define SPI_I2SCFGR_WSINV           SPI_I2SCFGR_WSINV_Msk                      /*!<Word select inversion                             */

+#define SPI_I2SCFGR_DATFMT_Pos      (14U)

+#define SPI_I2SCFGR_DATFMT_Msk      (0x1UL << SPI_I2SCFGR_DATFMT_Pos)          /*!< 0x00004000 */

+#define SPI_I2SCFGR_DATFMT          SPI_I2SCFGR_DATFMT_Msk                     /*!<Data format                                       */

+#define SPI_I2SCFGR_I2SDIV_Pos      (16U)

+#define SPI_I2SCFGR_I2SDIV_Msk      (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)         /*!< 0x00FF0000 */

+#define SPI_I2SCFGR_I2SDIV          SPI_I2SCFGR_I2SDIV_Msk                     /*!<I2S Linear prescaler */

+#define SPI_I2SCFGR_ODD_Pos         (24U)

+#define SPI_I2SCFGR_ODD_Msk         (0x1UL << SPI_I2SCFGR_ODD_Pos)             /*!< 0x01000000 */

+#define SPI_I2SCFGR_ODD             SPI_I2SCFGR_ODD_Msk                        /*!<Odd factor for the prescaler */

+#define SPI_I2SCFGR_MCKOE_Pos       (25U)

+#define SPI_I2SCFGR_MCKOE_Msk       (0x1UL << SPI_I2SCFGR_MCKOE_Pos)           /*!< 0x02000000 */

+#define SPI_I2SCFGR_MCKOE           SPI_I2SCFGR_MCKOE_Msk                      /*!<Master Clock Output Enable */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    QUADSPI                                 */

+/*                                                                            */

+/******************************************************************************/

+/*****************  Bit definition for QUADSPI_CR register  *******************/

+#define QUADSPI_CR_EN_Pos                (0U)

+#define QUADSPI_CR_EN_Msk                (0x1UL << QUADSPI_CR_EN_Pos)          /*!< 0x00000001 */

+#define QUADSPI_CR_EN                    QUADSPI_CR_EN_Msk                     /*!< Enable */

+#define QUADSPI_CR_ABORT_Pos             (1U)

+#define QUADSPI_CR_ABORT_Msk             (0x1UL << QUADSPI_CR_ABORT_Pos)       /*!< 0x00000002 */

+#define QUADSPI_CR_ABORT                 QUADSPI_CR_ABORT_Msk                  /*!< Abort request */

+#define QUADSPI_CR_DMAEN_Pos             (2U)

+#define QUADSPI_CR_DMAEN_Msk             (0x1UL << QUADSPI_CR_DMAEN_Pos)       /*!< 0x00000004 */

+#define QUADSPI_CR_DMAEN                 QUADSPI_CR_DMAEN_Msk                  /*!< DMA Enable */

+#define QUADSPI_CR_TCEN_Pos              (3U)

+#define QUADSPI_CR_TCEN_Msk              (0x1UL << QUADSPI_CR_TCEN_Pos)        /*!< 0x00000008 */

+#define QUADSPI_CR_TCEN                  QUADSPI_CR_TCEN_Msk                   /*!< Timeout Counter Enable */

+#define QUADSPI_CR_SSHIFT_Pos            (4U)

+#define QUADSPI_CR_SSHIFT_Msk            (0x1UL << QUADSPI_CR_SSHIFT_Pos)      /*!< 0x00000010 */

+#define QUADSPI_CR_SSHIFT                QUADSPI_CR_SSHIFT_Msk                 /*!< SSHIFT Sample Shift */

+#define QUADSPI_CR_DFM_Pos               (6U)

+#define QUADSPI_CR_DFM_Msk               (0x1UL << QUADSPI_CR_DFM_Pos)         /*!< 0x00000040 */

+#define QUADSPI_CR_DFM                   QUADSPI_CR_DFM_Msk                    /*!< Dual Flash Mode */

+#define QUADSPI_CR_FSEL_Pos              (7U)

+#define QUADSPI_CR_FSEL_Msk              (0x1UL << QUADSPI_CR_FSEL_Pos)        /*!< 0x00000080 */

+#define QUADSPI_CR_FSEL                  QUADSPI_CR_FSEL_Msk                   /*!< Flash Select */

+#define QUADSPI_CR_FTHRES_Pos            (8U)

+#define QUADSPI_CR_FTHRES_Msk            (0xFUL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000F00 */

+#define QUADSPI_CR_FTHRES                QUADSPI_CR_FTHRES_Msk                 /*!< FTHRES[3:0] FIFO Level */

+#define QUADSPI_CR_FTHRES_0              (0x1UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000100 */

+#define QUADSPI_CR_FTHRES_1              (0x2UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000200 */

+#define QUADSPI_CR_FTHRES_2              (0x4UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000400 */

+#define QUADSPI_CR_FTHRES_3              (0x8UL << QUADSPI_CR_FTHRES_Pos)      /*!< 0x00000800 */

+#define QUADSPI_CR_TEIE_Pos              (16U)

+#define QUADSPI_CR_TEIE_Msk              (0x1UL << QUADSPI_CR_TEIE_Pos)        /*!< 0x00010000 */

+#define QUADSPI_CR_TEIE                  QUADSPI_CR_TEIE_Msk                   /*!< Transfer Error Interrupt Enable */

+#define QUADSPI_CR_TCIE_Pos              (17U)

+#define QUADSPI_CR_TCIE_Msk              (0x1UL << QUADSPI_CR_TCIE_Pos)        /*!< 0x00020000 */

+#define QUADSPI_CR_TCIE                  QUADSPI_CR_TCIE_Msk                   /*!< Transfer Complete Interrupt Enable */

+#define QUADSPI_CR_FTIE_Pos              (18U)

+#define QUADSPI_CR_FTIE_Msk              (0x1UL << QUADSPI_CR_FTIE_Pos)        /*!< 0x00040000 */

+#define QUADSPI_CR_FTIE                  QUADSPI_CR_FTIE_Msk                   /*!< FIFO Threshold Interrupt Enable */

+#define QUADSPI_CR_SMIE_Pos              (19U)

+#define QUADSPI_CR_SMIE_Msk              (0x1UL << QUADSPI_CR_SMIE_Pos)        /*!< 0x00080000 */

+#define QUADSPI_CR_SMIE                  QUADSPI_CR_SMIE_Msk                   /*!< Status Match Interrupt Enable */

+#define QUADSPI_CR_TOIE_Pos              (20U)

+#define QUADSPI_CR_TOIE_Msk              (0x1UL << QUADSPI_CR_TOIE_Pos)        /*!< 0x00100000 */

+#define QUADSPI_CR_TOIE                  QUADSPI_CR_TOIE_Msk                   /*!< TimeOut Interrupt Enable */

+#define QUADSPI_CR_APMS_Pos              (22U)

+#define QUADSPI_CR_APMS_Msk              (0x1UL << QUADSPI_CR_APMS_Pos)        /*!< 0x00400000 */

+#define QUADSPI_CR_APMS                  QUADSPI_CR_APMS_Msk                   /*!< Bit 1 */

+#define QUADSPI_CR_PMM_Pos               (23U)

+#define QUADSPI_CR_PMM_Msk               (0x1UL << QUADSPI_CR_PMM_Pos)         /*!< 0x00800000 */

+#define QUADSPI_CR_PMM                   QUADSPI_CR_PMM_Msk                    /*!< Polling Match Mode */

+#define QUADSPI_CR_PRESCALER_Pos         (24U)

+#define QUADSPI_CR_PRESCALER_Msk         (0xFFUL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0xFF000000 */

+#define QUADSPI_CR_PRESCALER             QUADSPI_CR_PRESCALER_Msk              /*!< PRESCALER[7:0] Clock prescaler */

+#define QUADSPI_CR_PRESCALER_0           (0x01UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x01000000 */

+#define QUADSPI_CR_PRESCALER_1           (0x02UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x02000000 */

+#define QUADSPI_CR_PRESCALER_2           (0x04UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x04000000 */

+#define QUADSPI_CR_PRESCALER_3           (0x08UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x08000000 */

+#define QUADSPI_CR_PRESCALER_4           (0x10UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x10000000 */

+#define QUADSPI_CR_PRESCALER_5           (0x20UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x20000000 */

+#define QUADSPI_CR_PRESCALER_6           (0x40UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x40000000 */

+#define QUADSPI_CR_PRESCALER_7           (0x80UL << QUADSPI_CR_PRESCALER_Pos)  /*!< 0x80000000 */

+

+/*****************  Bit definition for QUADSPI_DCR register  ******************/

+#define QUADSPI_DCR_CKMODE_Pos           (0U)

+#define QUADSPI_DCR_CKMODE_Msk           (0x1UL << QUADSPI_DCR_CKMODE_Pos)     /*!< 0x00000001 */

+#define QUADSPI_DCR_CKMODE               QUADSPI_DCR_CKMODE_Msk                /*!< Mode 0 / Mode 3 */

+#define QUADSPI_DCR_CSHT_Pos             (8U)

+#define QUADSPI_DCR_CSHT_Msk             (0x7UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000700 */

+#define QUADSPI_DCR_CSHT                 QUADSPI_DCR_CSHT_Msk                  /*!< CSHT[2:0]: ChipSelect High Time */

+#define QUADSPI_DCR_CSHT_0               (0x1UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000100 */

+#define QUADSPI_DCR_CSHT_1               (0x2UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000200 */

+#define QUADSPI_DCR_CSHT_2               (0x4UL << QUADSPI_DCR_CSHT_Pos)       /*!< 0x00000400 */

+#define QUADSPI_DCR_FSIZE_Pos            (16U)

+#define QUADSPI_DCR_FSIZE_Msk            (0x1FUL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x001F0000 */

+#define QUADSPI_DCR_FSIZE                QUADSPI_DCR_FSIZE_Msk                 /*!< FSIZE[4:0]: Flash Size */

+#define QUADSPI_DCR_FSIZE_0              (0x01UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00010000 */

+#define QUADSPI_DCR_FSIZE_1              (0x02UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00020000 */

+#define QUADSPI_DCR_FSIZE_2              (0x04UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00040000 */

+#define QUADSPI_DCR_FSIZE_3              (0x08UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00080000 */

+#define QUADSPI_DCR_FSIZE_4              (0x10UL << QUADSPI_DCR_FSIZE_Pos)     /*!< 0x00100000 */

+

+/******************  Bit definition for QUADSPI_SR register  *******************/

+#define QUADSPI_SR_TEF_Pos               (0U)

+#define QUADSPI_SR_TEF_Msk               (0x1UL << QUADSPI_SR_TEF_Pos)         /*!< 0x00000001 */

+#define QUADSPI_SR_TEF                   QUADSPI_SR_TEF_Msk                    /*!< Transfer Error Flag */

+#define QUADSPI_SR_TCF_Pos               (1U)

+#define QUADSPI_SR_TCF_Msk               (0x1UL << QUADSPI_SR_TCF_Pos)         /*!< 0x00000002 */

+#define QUADSPI_SR_TCF                   QUADSPI_SR_TCF_Msk                    /*!< Transfer Complete Flag */

+#define QUADSPI_SR_FTF_Pos               (2U)

+#define QUADSPI_SR_FTF_Msk               (0x1UL << QUADSPI_SR_FTF_Pos)         /*!< 0x00000004 */

+#define QUADSPI_SR_FTF                   QUADSPI_SR_FTF_Msk                    /*!< FIFO Threshlod Flag */

+#define QUADSPI_SR_SMF_Pos               (3U)

+#define QUADSPI_SR_SMF_Msk               (0x1UL << QUADSPI_SR_SMF_Pos)         /*!< 0x00000008 */

+#define QUADSPI_SR_SMF                   QUADSPI_SR_SMF_Msk                    /*!< Status Match Flag */

+#define QUADSPI_SR_TOF_Pos               (4U)

+#define QUADSPI_SR_TOF_Msk               (0x1UL << QUADSPI_SR_TOF_Pos)         /*!< 0x00000010 */

+#define QUADSPI_SR_TOF                   QUADSPI_SR_TOF_Msk                    /*!< Timeout Flag */

+#define QUADSPI_SR_BUSY_Pos              (5U)

+#define QUADSPI_SR_BUSY_Msk              (0x1UL << QUADSPI_SR_BUSY_Pos)        /*!< 0x00000020 */

+#define QUADSPI_SR_BUSY                  QUADSPI_SR_BUSY_Msk                   /*!< Busy */

+#define QUADSPI_SR_FLEVEL_Pos            (8U)

+#define QUADSPI_SR_FLEVEL_Msk            (0x3FUL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00003F00 */

+#define QUADSPI_SR_FLEVEL                QUADSPI_SR_FLEVEL_Msk                 /*!< FIFO Threshlod Flag */

+#define QUADSPI_SR_FLEVEL_0              (0x01UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000100 */

+#define QUADSPI_SR_FLEVEL_1              (0x02UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000200 */

+#define QUADSPI_SR_FLEVEL_2              (0x04UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000400 */

+#define QUADSPI_SR_FLEVEL_3              (0x08UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00000800 */

+#define QUADSPI_SR_FLEVEL_4              (0x10UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00001000 */

+#define QUADSPI_SR_FLEVEL_5              (0x20UL << QUADSPI_SR_FLEVEL_Pos)     /*!< 0x00002000 */

+

+/******************  Bit definition for QUADSPI_FCR register  ******************/

+#define QUADSPI_FCR_CTEF_Pos             (0U)

+#define QUADSPI_FCR_CTEF_Msk             (0x1UL << QUADSPI_FCR_CTEF_Pos)       /*!< 0x00000001 */

+#define QUADSPI_FCR_CTEF                 QUADSPI_FCR_CTEF_Msk                  /*!< Clear Transfer Error Flag */

+#define QUADSPI_FCR_CTCF_Pos             (1U)

+#define QUADSPI_FCR_CTCF_Msk             (0x1UL << QUADSPI_FCR_CTCF_Pos)       /*!< 0x00000002 */

+#define QUADSPI_FCR_CTCF                 QUADSPI_FCR_CTCF_Msk                  /*!< Clear Transfer Complete Flag */

+#define QUADSPI_FCR_CSMF_Pos             (3U)

+#define QUADSPI_FCR_CSMF_Msk             (0x1UL << QUADSPI_FCR_CSMF_Pos)       /*!< 0x00000008 */

+#define QUADSPI_FCR_CSMF                 QUADSPI_FCR_CSMF_Msk                  /*!< Clear Status Match Flag */

+#define QUADSPI_FCR_CTOF_Pos             (4U)

+#define QUADSPI_FCR_CTOF_Msk             (0x1UL << QUADSPI_FCR_CTOF_Pos)       /*!< 0x00000010 */

+#define QUADSPI_FCR_CTOF                 QUADSPI_FCR_CTOF_Msk                  /*!< Clear Timeout Flag */

+

+/******************  Bit definition for QUADSPI_DLR register  ******************/

+#define QUADSPI_DLR_DL_Pos               (0U)

+#define QUADSPI_DLR_DL_Msk               (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos)  /*!< 0xFFFFFFFF */

+#define QUADSPI_DLR_DL                   QUADSPI_DLR_DL_Msk                    /*!< DL[31:0]: Data Length */

+

+/******************  Bit definition for QUADSPI_CCR register  ******************/

+#define QUADSPI_CCR_INSTRUCTION_Pos      (0U)

+#define QUADSPI_CCR_INSTRUCTION_Msk      (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */

+#define QUADSPI_CCR_INSTRUCTION          QUADSPI_CCR_INSTRUCTION_Msk             /*!< INSTRUCTION[7:0]: Instruction */

+#define QUADSPI_CCR_INSTRUCTION_0        (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */

+#define QUADSPI_CCR_INSTRUCTION_1        (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */

+#define QUADSPI_CCR_INSTRUCTION_2        (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */

+#define QUADSPI_CCR_INSTRUCTION_3        (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */

+#define QUADSPI_CCR_INSTRUCTION_4        (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */

+#define QUADSPI_CCR_INSTRUCTION_5        (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */

+#define QUADSPI_CCR_INSTRUCTION_6        (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */

+#define QUADSPI_CCR_INSTRUCTION_7        (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */

+#define QUADSPI_CCR_IMODE_Pos            (8U)

+#define QUADSPI_CCR_IMODE_Msk            (0x3UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000300 */

+#define QUADSPI_CCR_IMODE                QUADSPI_CCR_IMODE_Msk                   /*!< IMODE[1:0]: Instruction Mode */

+#define QUADSPI_CCR_IMODE_0              (0x1UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000100 */

+#define QUADSPI_CCR_IMODE_1              (0x2UL << QUADSPI_CCR_IMODE_Pos)        /*!< 0x00000200 */

+#define QUADSPI_CCR_ADMODE_Pos           (10U)

+#define QUADSPI_CCR_ADMODE_Msk           (0x3UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000C00 */

+#define QUADSPI_CCR_ADMODE               QUADSPI_CCR_ADMODE_Msk                  /*!< ADMODE[1:0]: Address Mode */

+#define QUADSPI_CCR_ADMODE_0             (0x1UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000400 */

+#define QUADSPI_CCR_ADMODE_1             (0x2UL << QUADSPI_CCR_ADMODE_Pos)       /*!< 0x00000800 */

+#define QUADSPI_CCR_ADSIZE_Pos           (12U)

+#define QUADSPI_CCR_ADSIZE_Msk           (0x3UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00003000 */

+#define QUADSPI_CCR_ADSIZE               QUADSPI_CCR_ADSIZE_Msk                  /*!< ADSIZE[1:0]: Address Size */

+#define QUADSPI_CCR_ADSIZE_0             (0x1UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00001000 */

+#define QUADSPI_CCR_ADSIZE_1             (0x2UL << QUADSPI_CCR_ADSIZE_Pos)       /*!< 0x00002000 */

+#define QUADSPI_CCR_ABMODE_Pos           (14U)

+#define QUADSPI_CCR_ABMODE_Msk           (0x3UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x0000C000 */

+#define QUADSPI_CCR_ABMODE               QUADSPI_CCR_ABMODE_Msk                  /*!< ABMODE[1:0]: Alternate Bytes Mode */

+#define QUADSPI_CCR_ABMODE_0             (0x1UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00004000 */

+#define QUADSPI_CCR_ABMODE_1             (0x2UL << QUADSPI_CCR_ABMODE_Pos)       /*!< 0x00008000 */

+#define QUADSPI_CCR_ABSIZE_Pos           (16U)

+#define QUADSPI_CCR_ABSIZE_Msk           (0x3UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00030000 */

+#define QUADSPI_CCR_ABSIZE               QUADSPI_CCR_ABSIZE_Msk                  /*!< ABSIZE[1:0]: Instruction Mode */

+#define QUADSPI_CCR_ABSIZE_0             (0x1UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00010000 */

+#define QUADSPI_CCR_ABSIZE_1             (0x2UL << QUADSPI_CCR_ABSIZE_Pos)       /*!< 0x00020000 */

+#define QUADSPI_CCR_DCYC_Pos             (18U)

+#define QUADSPI_CCR_DCYC_Msk             (0x1FUL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x007C0000 */

+#define QUADSPI_CCR_DCYC                 QUADSPI_CCR_DCYC_Msk                    /*!< DCYC[4:0]: Dummy Cycles */

+#define QUADSPI_CCR_DCYC_0               (0x01UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00040000 */

+#define QUADSPI_CCR_DCYC_1               (0x02UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00080000 */

+#define QUADSPI_CCR_DCYC_2               (0x04UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00100000 */

+#define QUADSPI_CCR_DCYC_3               (0x08UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00200000 */

+#define QUADSPI_CCR_DCYC_4               (0x10UL << QUADSPI_CCR_DCYC_Pos)        /*!< 0x00400000 */

+#define QUADSPI_CCR_DMODE_Pos            (24U)

+#define QUADSPI_CCR_DMODE_Msk            (0x3UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x03000000 */

+#define QUADSPI_CCR_DMODE                QUADSPI_CCR_DMODE_Msk                   /*!< DMODE[1:0]: Data Mode */

+#define QUADSPI_CCR_DMODE_0              (0x1UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x01000000 */

+#define QUADSPI_CCR_DMODE_1              (0x2UL << QUADSPI_CCR_DMODE_Pos)        /*!< 0x02000000 */

+#define QUADSPI_CCR_FMODE_Pos            (26U)

+#define QUADSPI_CCR_FMODE_Msk            (0x3UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x0C000000 */

+#define QUADSPI_CCR_FMODE                QUADSPI_CCR_FMODE_Msk                   /*!< FMODE[1:0]: Functional Mode */

+#define QUADSPI_CCR_FMODE_0              (0x1UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x04000000 */

+#define QUADSPI_CCR_FMODE_1              (0x2UL << QUADSPI_CCR_FMODE_Pos)        /*!< 0x08000000 */

+#define QUADSPI_CCR_SIOO_Pos             (28U)

+#define QUADSPI_CCR_SIOO_Msk             (0x1UL << QUADSPI_CCR_SIOO_Pos)         /*!< 0x10000000 */

+#define QUADSPI_CCR_SIOO                 QUADSPI_CCR_SIOO_Msk                    /*!< SIOO: Send Instruction Only Once Mode */

+#define QUADSPI_CCR_DHHC_Pos             (30U)

+#define QUADSPI_CCR_DHHC_Msk             (0x1UL << QUADSPI_CCR_DHHC_Pos)         /*!< 0x40000000 */

+#define QUADSPI_CCR_DHHC                 QUADSPI_CCR_DHHC_Msk                    /*!< DHHC: DDR hold half cycle */

+#define QUADSPI_CCR_DDRM_Pos             (31U)

+#define QUADSPI_CCR_DDRM_Msk             (0x1UL << QUADSPI_CCR_DDRM_Pos)         /*!< 0x80000000 */

+#define QUADSPI_CCR_DDRM                 QUADSPI_CCR_DDRM_Msk                    /*!< DDRM: Double Data Rate Mode */

+

+/******************  Bit definition for QUADSPI_AR register  *******************/

+#define QUADSPI_AR_ADDRESS_Pos           (0U)

+#define QUADSPI_AR_ADDRESS_Msk           (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_AR_ADDRESS               QUADSPI_AR_ADDRESS_Msk                /*!< ADDRESS[31:0]: Address */

+

+/******************  Bit definition for QUADSPI_ABR register  ******************/

+#define QUADSPI_ABR_ALTERNATE_Pos        (0U)

+#define QUADSPI_ABR_ALTERNATE_Msk        (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_ABR_ALTERNATE            QUADSPI_ABR_ALTERNATE_Msk             /*!< ALTERNATE[31:0]: Alternate Bytes */

+

+/******************  Bit definition for QUADSPI_DR register  *******************/

+#define QUADSPI_DR_DATA_Pos              (0U)

+#define QUADSPI_DR_DATA_Msk              (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_DR_DATA                  QUADSPI_DR_DATA_Msk                   /*!< DATA[31:0]: Data */

+

+/******************  Bit definition for QUADSPI_PSMKR register  ****************/

+#define QUADSPI_PSMKR_MASK_Pos           (0U)

+#define QUADSPI_PSMKR_MASK_Msk           (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_PSMKR_MASK               QUADSPI_PSMKR_MASK_Msk                /*!< MASK[31:0]: Status Mask */

+

+/******************  Bit definition for QUADSPI_PSMAR register  ****************/

+#define QUADSPI_PSMAR_MATCH_Pos          (0U)

+#define QUADSPI_PSMAR_MATCH_Msk          (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */

+#define QUADSPI_PSMAR_MATCH              QUADSPI_PSMAR_MATCH_Msk               /*!< MATCH[31:0]: Status Match */

+

+/******************  Bit definition for QUADSPI_PIR register  *****************/

+#define QUADSPI_PIR_INTERVAL_Pos         (0U)

+#define QUADSPI_PIR_INTERVAL_Msk         (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */

+#define QUADSPI_PIR_INTERVAL             QUADSPI_PIR_INTERVAL_Msk              /*!< INTERVAL[15:0]: Polling Interval */

+

+/******************  Bit definition for QUADSPI_LPTR register  *****************/

+#define QUADSPI_LPTR_TIMEOUT_Pos         (0U)

+#define QUADSPI_LPTR_TIMEOUT_Msk         (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */

+#define QUADSPI_LPTR_TIMEOUT             QUADSPI_LPTR_TIMEOUT_Msk              /*!< TIMEOUT[15:0]: Timeout period */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                 SYSCFG                                     */

+/*                                                                            */

+/******************************************************************************/

+

+/******************  Bit definition for SYSCFG_PMCR register  ******************/

+#define SYSCFG_PMCR_I2C1_FMP_Pos        (0U)

+#define SYSCFG_PMCR_I2C1_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos)    /*!< 0x00000001 */

+#define SYSCFG_PMCR_I2C1_FMP            SYSCFG_PMCR_I2C1_FMP_Msk               /*!< I2C1 Fast mode plus */

+#define SYSCFG_PMCR_I2C2_FMP_Pos        (1U)

+#define SYSCFG_PMCR_I2C2_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos)    /*!< 0x00000002 */

+#define SYSCFG_PMCR_I2C2_FMP            SYSCFG_PMCR_I2C2_FMP_Msk               /*!< I2C2 Fast mode plus */

+#define SYSCFG_PMCR_I2C3_FMP_Pos        (2U)

+#define SYSCFG_PMCR_I2C3_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos)    /*!< 0x00000004 */

+#define SYSCFG_PMCR_I2C3_FMP            SYSCFG_PMCR_I2C3_FMP_Msk               /*!< I2C3 Fast mode plus */

+#define SYSCFG_PMCR_I2C4_FMP_Pos        (3U)

+#define SYSCFG_PMCR_I2C4_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos)    /*!< 0x00000008 */

+#define SYSCFG_PMCR_I2C4_FMP            SYSCFG_PMCR_I2C4_FMP_Msk               /*!< I2C4 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB6_FMP_Pos     (4U)

+#define SYSCFG_PMCR_I2C_PB6_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */

+#define SYSCFG_PMCR_I2C_PB6_FMP         SYSCFG_PMCR_I2C_PB6_FMP_Msk            /*!< I2C PB6 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB7_FMP_Pos     (5U)

+#define SYSCFG_PMCR_I2C_PB7_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */

+#define SYSCFG_PMCR_I2C_PB7_FMP         SYSCFG_PMCR_I2C_PB7_FMP_Msk            /*!< I2C PB7 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB8_FMP_Pos     (6U)

+#define SYSCFG_PMCR_I2C_PB8_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */

+#define SYSCFG_PMCR_I2C_PB8_FMP         SYSCFG_PMCR_I2C_PB8_FMP_Msk            /*!< I2C PB8 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB9_FMP_Pos     (7U)

+#define SYSCFG_PMCR_I2C_PB9_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */

+#define SYSCFG_PMCR_I2C_PB9_FMP         SYSCFG_PMCR_I2C_PB9_FMP_Msk            /*!< I2C PB9 Fast mode plus */

+#define SYSCFG_PMCR_BOOSTEN_Pos         (8U)

+#define SYSCFG_PMCR_BOOSTEN_Msk         (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos)     /*!< 0x00000100 */

+#define SYSCFG_PMCR_BOOSTEN             SYSCFG_PMCR_BOOSTEN_Msk                /*!< I/O analog switch voltage booster enable */

+

+#define SYSCFG_PMCR_BOOSTVDDSEL_Pos     (9U)

+#define SYSCFG_PMCR_BOOSTVDDSEL_Msk     (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos) /*!< 0x00000200 */

+#define SYSCFG_PMCR_BOOSTVDDSEL         SYSCFG_PMCR_BOOSTVDDSEL_Msk            /*!< Analog switch supply source selection : VDD/VDDA */

+

+#define SYSCFG_PMCR_EPIS_SEL_Pos        (21U)

+#define SYSCFG_PMCR_EPIS_SEL_Msk        (0x7UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00E00000 */

+#define SYSCFG_PMCR_EPIS_SEL            SYSCFG_PMCR_EPIS_SEL_Msk               /*!< Ethernet PHY Interface Selection */

+#define SYSCFG_PMCR_EPIS_SEL_0          (0x1UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00200000 */

+#define SYSCFG_PMCR_EPIS_SEL_1          (0x2UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00400000 */

+#define SYSCFG_PMCR_EPIS_SEL_2          (0x4UL << SYSCFG_PMCR_EPIS_SEL_Pos)    /*!< 0x00800000 */

+#define SYSCFG_PMCR_PA0SO_Pos           (24U)

+#define SYSCFG_PMCR_PA0SO_Msk           (0x1UL << SYSCFG_PMCR_PA0SO_Pos)       /*!< 0x01000000 */

+#define SYSCFG_PMCR_PA0SO               SYSCFG_PMCR_PA0SO_Msk                  /*!< PA0 Switch Open */

+#define SYSCFG_PMCR_PA1SO_Pos           (25U)

+#define SYSCFG_PMCR_PA1SO_Msk           (0x1UL << SYSCFG_PMCR_PA1SO_Pos)       /*!< 0x02000000 */

+#define SYSCFG_PMCR_PA1SO               SYSCFG_PMCR_PA1SO_Msk                  /*!< PA1 Switch Open */

+#define SYSCFG_PMCR_PC2SO_Pos           (26U)

+#define SYSCFG_PMCR_PC2SO_Msk           (0x1UL << SYSCFG_PMCR_PC2SO_Pos)       /*!< 0x04000000 */

+#define SYSCFG_PMCR_PC2SO               SYSCFG_PMCR_PC2SO_Msk                  /*!< PC2 Switch Open */

+#define SYSCFG_PMCR_PC3SO_Pos           (27U)

+#define SYSCFG_PMCR_PC3SO_Msk           (0x1UL << SYSCFG_PMCR_PC3SO_Pos)       /*!< 0x08000000 */

+#define SYSCFG_PMCR_PC3SO               SYSCFG_PMCR_PC3SO_Msk                  /*!< PC3 Switch Open */

+

+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/

+#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)

+#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */

+#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)

+#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */

+#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)

+#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000F00 */

+#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */

+#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)

+#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x0000F000 */

+#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */

+/**

+  * @brief   EXTI0 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */

+

+/**

+  * @brief   EXTI1 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */

+/**

+  * @brief   EXTI2 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */

+

+/**

+  * @brief   EXTI3 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/

+#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)

+#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */

+#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)

+#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */

+#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)

+#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000F00 */

+#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */

+#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)

+#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x0000F000 */

+#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */

+/**

+  * @brief   EXTI4 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */

+/**

+  * @brief   EXTI5 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */

+/**

+  * @brief   EXTI6 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */

+

+/**

+  * @brief   EXTI7 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/

+#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)

+#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */

+#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)

+#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */

+#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)

+#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000F00 */

+#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */

+#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)

+#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x0000F000 */

+#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */

+

+/**

+  * @brief   EXTI8 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */

+

+/**

+  * @brief   EXTI9 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */

+

+/**

+  * @brief   EXTI10 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */

+

+/**

+  * @brief   EXTI11 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/

+#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)

+#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x0000000F */

+#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */

+#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)

+#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x000000F0 */

+#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */

+#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)

+#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000F00 */

+#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */

+#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)

+#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x0000F000 */

+#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */

+/**

+  * @brief   EXTI12 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */

+/**

+  * @brief   EXTI13 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */

+/**

+  * @brief   EXTI14 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */

+/**

+  * @brief   EXTI15 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */

+

+/******************  Bit definition for SYSCFG_CFGR register  ******************/

+#define SYSCFG_CFGR_CM4L_Pos            (0U)

+#define SYSCFG_CFGR_CM4L_Msk            (0x1UL << SYSCFG_CFGR_CM4L_Pos)        /*!< 0x00000001 */

+#define SYSCFG_CFGR_CM4L                SYSCFG_CFGR_CM4L_Msk                   /*!<Cortex-M4 LOCKUP (Hardfault) output enable bit */

+#define SYSCFG_CFGR_PVDL_Pos            (2U)

+#define SYSCFG_CFGR_PVDL_Msk            (0x1UL << SYSCFG_CFGR_PVDL_Pos)        /*!< 0x00000004 */

+#define SYSCFG_CFGR_PVDL                SYSCFG_CFGR_PVDL_Msk                   /*!<PVD lock enable bit */

+#define SYSCFG_CFGR_FLASHL_Pos          (3U)

+#define SYSCFG_CFGR_FLASHL_Msk          (0x1UL << SYSCFG_CFGR_FLASHL_Pos)      /*!< 0x00000008 */

+#define SYSCFG_CFGR_FLASHL              SYSCFG_CFGR_FLASHL_Msk                 /*!<FLASH double ECC error lock bit */

+#define SYSCFG_CFGR_CM7L_Pos            (6U)

+#define SYSCFG_CFGR_CM7L_Msk            (0x1UL << SYSCFG_CFGR_CM7L_Pos)        /*!< 0x00000040 */

+#define SYSCFG_CFGR_CM7L                SYSCFG_CFGR_CM7L_Msk                   /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */

+#define SYSCFG_CFGR_BKRAML_Pos          (7U)

+#define SYSCFG_CFGR_BKRAML_Msk          (0x1UL << SYSCFG_CFGR_BKRAML_Pos)      /*!< 0x00000080 */

+#define SYSCFG_CFGR_BKRAML              SYSCFG_CFGR_BKRAML_Msk                 /*!<Backup SRAM double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM4L_Pos          (9U)

+#define SYSCFG_CFGR_SRAM4L_Msk          (0x1UL << SYSCFG_CFGR_SRAM4L_Pos)      /*!< 0x00000200 */

+#define SYSCFG_CFGR_SRAM4L              SYSCFG_CFGR_SRAM4L_Msk                 /*!<SRAM4 double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM3L_Pos          (10U)

+#define SYSCFG_CFGR_SRAM3L_Msk          (0x1UL << SYSCFG_CFGR_SRAM3L_Pos)      /*!< 0x00000400 */

+#define SYSCFG_CFGR_SRAM3L              SYSCFG_CFGR_SRAM3L_Msk                 /*!<SRAM3 double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM2L_Pos          (11U)

+#define SYSCFG_CFGR_SRAM2L_Msk          (0x1UL << SYSCFG_CFGR_SRAM2L_Pos)      /*!< 0x00000800 */

+#define SYSCFG_CFGR_SRAM2L              SYSCFG_CFGR_SRAM2L_Msk                 /*!<SRAM2 double ECC error lock bit */

+#define SYSCFG_CFGR_SRAM1L_Pos          (12U)

+#define SYSCFG_CFGR_SRAM1L_Msk          (0x1UL << SYSCFG_CFGR_SRAM1L_Pos)      /*!< 0x00001000 */

+#define SYSCFG_CFGR_SRAM1L              SYSCFG_CFGR_SRAM1L_Msk                 /*!<SRAM1 double ECC error lock bit */

+#define SYSCFG_CFGR_DTCML_Pos           (13U)

+#define SYSCFG_CFGR_DTCML_Msk           (0x1UL << SYSCFG_CFGR_DTCML_Pos)       /*!< 0x00002000 */

+#define SYSCFG_CFGR_DTCML               SYSCFG_CFGR_DTCML_Msk                  /*!<DTCM double ECC error lock bit */

+#define SYSCFG_CFGR_ITCML_Pos           (14U)

+#define SYSCFG_CFGR_ITCML_Msk           (0x1UL << SYSCFG_CFGR_ITCML_Pos)       /*!< 0x00004000 */

+#define SYSCFG_CFGR_ITCML               SYSCFG_CFGR_ITCML_Msk                  /*!<ITCM double ECC error lock bit */

+#define SYSCFG_CFGR_AXISRAML_Pos        (15U)

+#define SYSCFG_CFGR_AXISRAML_Msk        (0x1UL << SYSCFG_CFGR_AXISRAML_Pos)    /*!< 0x00008000 */

+#define SYSCFG_CFGR_AXISRAML            SYSCFG_CFGR_AXISRAML_Msk               /*!<AXISRAM double ECC error lock bit */

+

+/******************  Bit definition for SYSCFG_CCCSR register  ******************/

+#define SYSCFG_CCCSR_EN_Pos             (0U)

+#define SYSCFG_CCCSR_EN_Msk             (0x1UL << SYSCFG_CCCSR_EN_Pos)         /*!< 0x00000001 */

+#define SYSCFG_CCCSR_EN                 SYSCFG_CCCSR_EN_Msk                    /*!< I/O compensation cell enable */

+#define SYSCFG_CCCSR_CS_Pos             (1U)

+#define SYSCFG_CCCSR_CS_Msk             (0x1UL << SYSCFG_CCCSR_CS_Pos)         /*!< 0x00000002 */

+#define SYSCFG_CCCSR_CS                 SYSCFG_CCCSR_CS_Msk                    /*!< I/O compensation cell code selection */

+#define SYSCFG_CCCSR_READY_Pos          (8U)

+#define SYSCFG_CCCSR_READY_Msk          (0x1UL << SYSCFG_CCCSR_READY_Pos)      /*!< 0x00000100 */

+#define SYSCFG_CCCSR_READY              SYSCFG_CCCSR_READY_Msk                 /*!< I/O compensation cell ready flag */

+#define SYSCFG_CCCSR_HSLV_Pos           (16U)

+#define SYSCFG_CCCSR_HSLV_Msk           (0x1UL << SYSCFG_CCCSR_HSLV_Pos)       /*!< 0x00010000 */

+#define SYSCFG_CCCSR_HSLV               SYSCFG_CCCSR_HSLV_Msk                  /*!< High-speed at low-voltage */

+

+/******************  Bit definition for SYSCFG_CCVR register  *******************/

+#define SYSCFG_CCVR_NCV_Pos             (0U)

+#define SYSCFG_CCVR_NCV_Msk             (0xFUL << SYSCFG_CCVR_NCV_Pos)         /*!< 0x0000000F */

+#define SYSCFG_CCVR_NCV                 SYSCFG_CCVR_NCV_Msk                    /*!< NMOS compensation value */

+#define SYSCFG_CCVR_PCV_Pos             (4U)

+#define SYSCFG_CCVR_PCV_Msk             (0xFUL << SYSCFG_CCVR_PCV_Pos)         /*!< 0x000000F0 */

+#define SYSCFG_CCVR_PCV                 SYSCFG_CCVR_PCV_Msk                    /*!< PMOS compensation value */

+

+/******************  Bit definition for SYSCFG_CCCR register  *******************/

+#define SYSCFG_CCCR_NCC_Pos             (0U)

+#define SYSCFG_CCCR_NCC_Msk             (0xFUL << SYSCFG_CCCR_NCC_Pos)         /*!< 0x0000000F */

+#define SYSCFG_CCCR_NCC                 SYSCFG_CCCR_NCC_Msk                    /*!< NMOS compensation code */

+#define SYSCFG_CCCR_PCC_Pos             (4U)

+#define SYSCFG_CCCR_PCC_Msk             (0xFUL << SYSCFG_CCCR_PCC_Pos)         /*!< 0x000000F0 */

+#define SYSCFG_CCCR_PCC                 SYSCFG_CCCR_PCC_Msk                    /*!< PMOS compensation code */

+/******************  Bit definition for SYSCFG_PWRCR register  *******************/

+#define SYSCFG_PWRCR_ODEN_Pos           (0U)

+#define SYSCFG_PWRCR_ODEN_Msk           (0x1UL << SYSCFG_PWRCR_ODEN_Pos)         /*!< 0x00000001 */

+#define SYSCFG_PWRCR_ODEN               SYSCFG_PWRCR_ODEN_Msk                    /*!< PWR overdrive enable */

+

+/******************  Bit definition for SYSCFG_PKGR register  *******************/

+#define SYSCFG_PKGR_PKG_Pos             (0U)

+#define SYSCFG_PKGR_PKG_Msk             (0xFUL << SYSCFG_PKGR_PKG_Pos)         /*!< 0x0000000F */

+#define SYSCFG_PKGR_PKG                 SYSCFG_PKGR_PKG_Msk                    /*!< Package type */

+

+/******************  Bit definition for SYSCFG_UR0 register  *******************/

+#define SYSCFG_UR0_BKS_Pos              (0U)

+#define SYSCFG_UR0_BKS_Msk              (0x1UL << SYSCFG_UR0_BKS_Pos)          /*!< 0x00000001 */

+#define SYSCFG_UR0_BKS                  SYSCFG_UR0_BKS_Msk                     /*!< Bank Swap */

+#define SYSCFG_UR0_RDP_Pos              (16U)

+#define SYSCFG_UR0_RDP_Msk              (0xFFUL << SYSCFG_UR0_RDP_Pos)         /*!< 0x00FF0000 */

+#define SYSCFG_UR0_RDP                  SYSCFG_UR0_RDP_Msk                     /*!< Readout protection */

+

+/******************  Bit definition for SYSCFG_UR1 register  *******************/

+#define SYSCFG_UR1_BCM4_Pos             (0U)

+#define SYSCFG_UR1_BCM4_Msk             (0x1UL << SYSCFG_UR1_BCM4_Pos)         /*!< 0x00000001 */

+#define SYSCFG_UR1_BCM4                 SYSCFG_UR1_BCM4_Msk                    /*!< Boot Cortex-M4 */

+#define SYSCFG_UR1_BCM7_Pos             (16U)

+#define SYSCFG_UR1_BCM7_Msk             (0x1UL << SYSCFG_UR1_BCM7_Pos)         /*!< 0x00010000 */

+#define SYSCFG_UR1_BCM7                 SYSCFG_UR1_BCM7_Msk                    /*!< Boot Cortex-M7 */

+/******************  Bit definition for SYSCFG_UR2 register  *******************/

+#define SYSCFG_UR2_BORH_Pos             (0U)

+#define SYSCFG_UR2_BORH_Msk             (0x3UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000003 */

+#define SYSCFG_UR2_BORH                 SYSCFG_UR2_BORH_Msk                    /*!< Brown Out Reset High level */

+#define SYSCFG_UR2_BORH_0               (0x1UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000001 */

+#define SYSCFG_UR2_BORH_1               (0x2UL << SYSCFG_UR2_BORH_Pos)         /*!< 0x00000002 */

+#define SYSCFG_UR2_BCM7_ADD0_Pos        (16U)

+#define SYSCFG_UR2_BCM7_ADD0_Msk        (0xFFFFUL << SYSCFG_UR2_BCM7_ADD0_Pos) /*!< 0xFFFF0000 */

+#define SYSCFG_UR2_BCM7_ADD0            SYSCFG_UR2_BCM7_ADD0_Msk               /*!< Boot Cortex-M7 Address 0 */

+/******************  Bit definition for SYSCFG_UR3 register  *******************/

+#define SYSCFG_UR3_BCM7_ADD1_Pos        (0U)

+#define SYSCFG_UR3_BCM7_ADD1_Msk        (0xFFFFUL << SYSCFG_UR3_BCM7_ADD1_Pos) /*!< 0x0000FFFF */

+#define SYSCFG_UR3_BCM7_ADD1            SYSCFG_UR3_BCM7_ADD1_Msk               /*!< Boot Cortex-M7 Address 1 */

+

+#define SYSCFG_UR3_BCM4_ADD0_Pos        (16U)

+#define SYSCFG_UR3_BCM4_ADD0_Msk        (0xFFFFUL << SYSCFG_UR3_BCM4_ADD0_Pos) /*!< 0xFFFF0000 */

+#define SYSCFG_UR3_BCM4_ADD0            SYSCFG_UR3_BCM4_ADD0_Msk               /*!< Boot Cortex-M4 Address 0 */

+

+/******************  Bit definition for SYSCFG_UR4 register  *******************/

+

+#define SYSCFG_UR4_BCM4_ADD1_Pos        (0U)

+#define SYSCFG_UR4_BCM4_ADD1_Msk        (0xFFFFUL << SYSCFG_UR4_BCM4_ADD1_Pos) /*!< 0x0000FFFF */

+#define SYSCFG_UR4_BCM4_ADD1            SYSCFG_UR4_BCM4_ADD1_Msk               /*!< Boot Cortex-M4 Address 1 */

+

+#define SYSCFG_UR4_MEPAD_BANK1_Pos      (16U)

+#define SYSCFG_UR4_MEPAD_BANK1_Msk      (0x1UL << SYSCFG_UR4_MEPAD_BANK1_Pos)  /*!< 0x00010000 */

+#define SYSCFG_UR4_MEPAD_BANK1          SYSCFG_UR4_MEPAD_BANK1_Msk             /*!< Mass Erase Protected Area Disabled for bank 1 */

+

+/******************  Bit definition for SYSCFG_UR5 register  *******************/

+#define SYSCFG_UR5_MESAD_BANK1_Pos      (0U)

+#define SYSCFG_UR5_MESAD_BANK1_Msk      (0x1UL << SYSCFG_UR5_MESAD_BANK1_Pos)  /*!< 0x00000001 */

+#define SYSCFG_UR5_MESAD_BANK1          SYSCFG_UR5_MESAD_BANK1_Msk             /*!< Mass erase secured area disabled for bank 1 */

+#define SYSCFG_UR5_WRPN_BANK1_Pos       (16U)

+#define SYSCFG_UR5_WRPN_BANK1_Msk       (0xFFUL << SYSCFG_UR5_WRPN_BANK1_Pos)  /*!< 0x00FF0000 */

+#define SYSCFG_UR5_WRPN_BANK1           SYSCFG_UR5_WRPN_BANK1_Msk              /*!< Write protection for flash bank 1 */

+

+/******************  Bit definition for SYSCFG_UR6 register  *******************/

+#define SYSCFG_UR6_PABEG_BANK1_Pos      (0U)

+#define SYSCFG_UR6_PABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PABEG_BANK1_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR6_PABEG_BANK1          SYSCFG_UR6_PABEG_BANK1_Msk             /*!< Protected area start address for bank 1 */

+#define SYSCFG_UR6_PAEND_BANK1_Pos      (16U)

+#define SYSCFG_UR6_PAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR6_PAEND_BANK1_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR6_PAEND_BANK1          SYSCFG_UR6_PAEND_BANK1_Msk             /*!< Protected area end address for bank 1 */

+

+/******************  Bit definition for SYSCFG_UR7 register  *******************/

+#define SYSCFG_UR7_SABEG_BANK1_Pos      (0U)

+#define SYSCFG_UR7_SABEG_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SABEG_BANK1_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR7_SABEG_BANK1          SYSCFG_UR7_SABEG_BANK1_Msk             /*!< Secured area start address for bank 1 */

+#define SYSCFG_UR7_SAEND_BANK1_Pos      (16U)

+#define SYSCFG_UR7_SAEND_BANK1_Msk      (0xFFFUL << SYSCFG_UR7_SAEND_BANK1_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR7_SAEND_BANK1          SYSCFG_UR7_SAEND_BANK1_Msk             /*!< Secured area end address for bank 1 */

+

+/******************  Bit definition for SYSCFG_UR8 register  *******************/

+#define SYSCFG_UR8_MEPAD_BANK2_Pos      (0U)

+#define SYSCFG_UR8_MEPAD_BANK2_Msk      (0x1UL << SYSCFG_UR8_MEPAD_BANK2_Pos)  /*!< 0x00000001 */

+#define SYSCFG_UR8_MEPAD_BANK2          SYSCFG_UR8_MEPAD_BANK2_Msk             /*!< Mass erase Protected area disabled for bank 2 */

+#define SYSCFG_UR8_MESAD_BANK2_Pos      (16U)

+#define SYSCFG_UR8_MESAD_BANK2_Msk      (0x1UL << SYSCFG_UR8_MESAD_BANK2_Pos)  /*!< 0x00010000 */

+#define SYSCFG_UR8_MESAD_BANK2          SYSCFG_UR8_MESAD_BANK2_Msk             /*!< Mass Erase Secured Area Disabled for bank 2 */

+

+/******************  Bit definition for SYSCFG_UR9 register  *******************/

+#define SYSCFG_UR9_WRPN_BANK2_Pos       (0U)

+#define SYSCFG_UR9_WRPN_BANK2_Msk       (0xFFUL << SYSCFG_UR9_WRPN_BANK2_Pos)  /*!< 0x000000FF */

+#define SYSCFG_UR9_WRPN_BANK2           SYSCFG_UR9_WRPN_BANK2_Msk              /*!< Write protection for flash bank 2 */

+#define SYSCFG_UR9_PABEG_BANK2_Pos      (16U)

+#define SYSCFG_UR9_PABEG_BANK2_Msk      (0xFFFUL << SYSCFG_UR9_PABEG_BANK2_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR9_PABEG_BANK2          SYSCFG_UR9_PABEG_BANK2_Msk             /*!< Protected area start address for bank 2 */

+

+/******************  Bit definition for SYSCFG_UR10 register  *******************/

+#define SYSCFG_UR10_PAEND_BANK2_Pos     (0U)

+#define SYSCFG_UR10_PAEND_BANK2_Msk     (0xFFFUL << SYSCFG_UR10_PAEND_BANK2_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR10_PAEND_BANK2         SYSCFG_UR10_PAEND_BANK2_Msk            /*!< Protected area end address for bank 2 */

+#define SYSCFG_UR10_SABEG_BANK2_Pos     (16U)

+#define SYSCFG_UR10_SABEG_BANK2_Msk     (0xFFFUL << SYSCFG_UR10_SABEG_BANK2_Pos) /*!< 0x0FFF0000 */

+#define SYSCFG_UR10_SABEG_BANK2         SYSCFG_UR10_SABEG_BANK2_Msk            /*!< Secured area start address for bank 2 */

+

+/******************  Bit definition for SYSCFG_UR11 register  *******************/

+#define SYSCFG_UR11_SAEND_BANK2_Pos     (0U)

+#define SYSCFG_UR11_SAEND_BANK2_Msk     (0xFFFUL << SYSCFG_UR11_SAEND_BANK2_Pos) /*!< 0x00000FFF */

+#define SYSCFG_UR11_SAEND_BANK2         SYSCFG_UR11_SAEND_BANK2_Msk            /*!< Secured area end address for bank 2 */

+#define SYSCFG_UR11_IWDG1M_Pos          (16U)

+#define SYSCFG_UR11_IWDG1M_Msk          (0x1UL << SYSCFG_UR11_IWDG1M_Pos)      /*!< 0x00010000 */

+#define SYSCFG_UR11_IWDG1M              SYSCFG_UR11_IWDG1M_Msk                 /*!< Independent Watchdog 1 mode (SW or HW) */

+

+/******************  Bit definition for SYSCFG_UR12 register  *******************/

+#define SYSCFG_UR12_IWDG2M_Pos          (0U)

+#define SYSCFG_UR12_IWDG2M_Msk          (0x1UL << SYSCFG_UR12_IWDG2M_Pos)      /*!< 0x00000001 */

+#define SYSCFG_UR12_IWDG2M              SYSCFG_UR12_IWDG2M_Msk                 /*!< Independent Watchdog 2 mode (SW or HW) */

+

+#define SYSCFG_UR12_SECURE_Pos          (16U)

+#define SYSCFG_UR12_SECURE_Msk          (0x1UL << SYSCFG_UR12_SECURE_Pos)      /*!< 0x00010000 */

+#define SYSCFG_UR12_SECURE              SYSCFG_UR12_SECURE_Msk                 /*!< Secure mode status */

+

+/******************  Bit definition for SYSCFG_UR13 register  *******************/

+#define SYSCFG_UR13_SDRS_Pos            (0U)

+#define SYSCFG_UR13_SDRS_Msk            (0x3UL << SYSCFG_UR13_SDRS_Pos)        /*!< 0x00000003 */

+#define SYSCFG_UR13_SDRS                SYSCFG_UR13_SDRS_Msk                   /*!< Secured DTCM RAM Size */

+#define SYSCFG_UR13_D1SBRST_Pos         (16U)

+#define SYSCFG_UR13_D1SBRST_Msk         (0x1UL << SYSCFG_UR13_D1SBRST_Pos)     /*!< 0x00010000 */

+#define SYSCFG_UR13_D1SBRST             SYSCFG_UR13_D1SBRST_Msk                /*!< D1 Standby reset */

+

+/******************  Bit definition for SYSCFG_UR14 register  *******************/

+#define SYSCFG_UR14_D1STPRST_Pos        (0U)

+#define SYSCFG_UR14_D1STPRST_Msk        (0x1UL << SYSCFG_UR14_D1STPRST_Pos)    /*!< 0x00000001 */

+#define SYSCFG_UR14_D1STPRST            SYSCFG_UR14_D1STPRST_Msk               /*!< D1 Stop Reset */

+#define SYSCFG_UR14_D2SBRST_Pos         (16U)

+#define SYSCFG_UR14_D2SBRST_Msk         (0x1UL << SYSCFG_UR14_D2SBRST_Pos)     /*!< 0x00010000 */

+#define SYSCFG_UR14_D2SBRST             SYSCFG_UR14_D2SBRST_Msk                /*!< D2 Standby Reset */

+

+/******************  Bit definition for SYSCFG_UR15 register  *******************/

+#define SYSCFG_UR15_D2STPRST_Pos        (0U)

+#define SYSCFG_UR15_D2STPRST_Msk        (0x1UL << SYSCFG_UR15_D2STPRST_Pos)    /*!< 0x00000001 */

+#define SYSCFG_UR15_D2STPRST            SYSCFG_UR15_D2STPRST_Msk               /*!< D2 Stop Reset */

+#define SYSCFG_UR15_FZIWDGSTB_Pos       (16U)

+#define SYSCFG_UR15_FZIWDGSTB_Msk       (0x1UL << SYSCFG_UR15_FZIWDGSTB_Pos)   /*!< 0x00010000 */

+#define SYSCFG_UR15_FZIWDGSTB           SYSCFG_UR15_FZIWDGSTB_Msk              /*!< Freeze independent watchdogs in Standby mode */

+

+/******************  Bit definition for SYSCFG_UR16 register  *******************/

+#define SYSCFG_UR16_FZIWDGSTP_Pos       (0U)

+#define SYSCFG_UR16_FZIWDGSTP_Msk       (0x1UL << SYSCFG_UR16_FZIWDGSTP_Pos)   /*!< 0x00000001 */

+#define SYSCFG_UR16_FZIWDGSTP           SYSCFG_UR16_FZIWDGSTP_Msk              /*!< Freeze independent watchdogs in Stop mode */

+#define SYSCFG_UR16_PKP_Pos             (16U)

+#define SYSCFG_UR16_PKP_Msk             (0x1UL << SYSCFG_UR16_PKP_Pos)         /*!< 0x00010000 */

+#define SYSCFG_UR16_PKP                 SYSCFG_UR16_PKP_Msk                    /*!< Private key programmed */

+

+/******************  Bit definition for SYSCFG_UR17 register  *******************/

+#define SYSCFG_UR17_IOHSLV_Pos          (0U)

+#define SYSCFG_UR17_IOHSLV_Msk          (0x1UL << SYSCFG_UR17_IOHSLV_Pos)      /*!< 0x00000001 */

+#define SYSCFG_UR17_IOHSLV              SYSCFG_UR17_IOHSLV_Msk                 /*!< I/O high speed / low voltage */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    TIM                                     */

+/*                                                                            */

+/******************************************************************************/

+#define TIM_BREAK_INPUT_SUPPORT             /*!<TIM Break input feature */

+

+/*******************  Bit definition for TIM_CR1 register  ********************/

+#define TIM_CR1_CEN_Pos           (0U)

+#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */

+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */

+#define TIM_CR1_UDIS_Pos          (1U)

+#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */

+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */

+#define TIM_CR1_URS_Pos           (2U)

+#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */

+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */

+#define TIM_CR1_OPM_Pos           (3U)

+#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */

+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */

+#define TIM_CR1_DIR_Pos           (4U)

+#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */

+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */

+

+#define TIM_CR1_CMS_Pos           (5U)

+#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */

+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */

+#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */

+#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */

+

+#define TIM_CR1_ARPE_Pos          (7U)

+#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */

+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */

+

+#define TIM_CR1_CKD_Pos           (8U)

+#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */

+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */

+#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */

+#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */

+

+#define TIM_CR1_UIFREMAP_Pos      (11U)

+#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */

+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */

+

+/*******************  Bit definition for TIM_CR2 register  ********************/

+#define TIM_CR2_CCPC_Pos          (0U)

+#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */

+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */

+#define TIM_CR2_CCUS_Pos          (2U)

+#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */

+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */

+#define TIM_CR2_CCDS_Pos          (3U)

+#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */

+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */

+

+#define TIM_CR2_MMS_Pos           (4U)

+#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */

+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */

+#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */

+#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */

+#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */

+

+#define TIM_CR2_TI1S_Pos          (7U)

+#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */

+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */

+#define TIM_CR2_OIS1_Pos          (8U)

+#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */

+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */

+#define TIM_CR2_OIS1N_Pos         (9U)

+#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */

+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */

+#define TIM_CR2_OIS2_Pos          (10U)

+#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */

+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */

+#define TIM_CR2_OIS2N_Pos         (11U)

+#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */

+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */

+#define TIM_CR2_OIS3_Pos          (12U)

+#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */

+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */

+#define TIM_CR2_OIS3N_Pos         (13U)

+#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */

+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */

+#define TIM_CR2_OIS4_Pos          (14U)

+#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */

+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */

+#define TIM_CR2_OIS5_Pos          (16U)

+#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */

+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */

+#define TIM_CR2_OIS6_Pos          (17U)

+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */

+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */

+

+#define TIM_CR2_MMS2_Pos          (20U)

+#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */

+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */

+#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */

+#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */

+#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */

+#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */

+

+/*******************  Bit definition for TIM_SMCR register  *******************/

+#define TIM_SMCR_SMS_Pos          (0U)

+#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */

+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */

+#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */

+#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */

+#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */

+#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */

+

+#define TIM_SMCR_TS_Pos           (4U)

+#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */

+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[4:0] bits (Trigger selection) */

+#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)                /*!< 0x00000010 */

+#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)                /*!< 0x00000020 */

+#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)                /*!< 0x00000040 */

+#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)                /*!< 0x00100000 */

+#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)                /*!< 0x00200000 */

+

+#define TIM_SMCR_MSM_Pos          (7U)

+#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */

+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */

+

+#define TIM_SMCR_ETF_Pos          (8U)

+#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */

+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */

+#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */

+#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */

+#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */

+#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */

+

+#define TIM_SMCR_ETPS_Pos         (12U)

+#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */

+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */

+#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */

+#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */

+

+#define TIM_SMCR_ECE_Pos          (14U)

+#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */

+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */

+#define TIM_SMCR_ETP_Pos          (15U)

+#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */

+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */

+

+/*******************  Bit definition for TIM_DIER register  *******************/

+#define TIM_DIER_UIE_Pos          (0U)

+#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */

+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */

+#define TIM_DIER_CC1IE_Pos        (1U)

+#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */

+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */

+#define TIM_DIER_CC2IE_Pos        (2U)

+#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */

+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */

+#define TIM_DIER_CC3IE_Pos        (3U)

+#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */

+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */

+#define TIM_DIER_CC4IE_Pos        (4U)

+#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */

+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */

+#define TIM_DIER_COMIE_Pos        (5U)

+#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */

+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */

+#define TIM_DIER_TIE_Pos          (6U)

+#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */

+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */

+#define TIM_DIER_BIE_Pos          (7U)

+#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */

+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */

+#define TIM_DIER_UDE_Pos          (8U)

+#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */

+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */

+#define TIM_DIER_CC1DE_Pos        (9U)

+#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */

+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */

+#define TIM_DIER_CC2DE_Pos        (10U)

+#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */

+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */

+#define TIM_DIER_CC3DE_Pos        (11U)

+#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */

+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */

+#define TIM_DIER_CC4DE_Pos        (12U)

+#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */

+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */

+#define TIM_DIER_COMDE_Pos        (13U)

+#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */

+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */

+#define TIM_DIER_TDE_Pos          (14U)

+#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */

+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */

+

+/********************  Bit definition for TIM_SR register  ********************/

+#define TIM_SR_UIF_Pos            (0U)

+#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */

+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */

+#define TIM_SR_CC1IF_Pos          (1U)

+#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */

+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */

+#define TIM_SR_CC2IF_Pos          (2U)

+#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */

+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */

+#define TIM_SR_CC3IF_Pos          (3U)

+#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */

+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */

+#define TIM_SR_CC4IF_Pos          (4U)

+#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */

+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */

+#define TIM_SR_COMIF_Pos          (5U)

+#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */

+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */

+#define TIM_SR_TIF_Pos            (6U)

+#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */

+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */

+#define TIM_SR_BIF_Pos            (7U)

+#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */

+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */

+#define TIM_SR_B2IF_Pos           (8U)

+#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */

+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break2 interrupt Flag */

+#define TIM_SR_CC1OF_Pos          (9U)

+#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */

+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */

+#define TIM_SR_CC2OF_Pos          (10U)

+#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */

+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */

+#define TIM_SR_CC3OF_Pos          (11U)

+#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */

+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */

+#define TIM_SR_CC4OF_Pos          (12U)

+#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */

+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */

+#define TIM_SR_CC5IF_Pos          (16U)

+#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */

+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */

+#define TIM_SR_CC6IF_Pos          (17U)

+#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */

+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */

+#define TIM_SR_SBIF_Pos           (13U)

+#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */

+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!< System Break Flag */

+

+/*******************  Bit definition for TIM_EGR register  ********************/

+#define TIM_EGR_UG_Pos            (0U)

+#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */

+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */

+#define TIM_EGR_CC1G_Pos          (1U)

+#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */

+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */

+#define TIM_EGR_CC2G_Pos          (2U)

+#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */

+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */

+#define TIM_EGR_CC3G_Pos          (3U)

+#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */

+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */

+#define TIM_EGR_CC4G_Pos          (4U)

+#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */

+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */

+#define TIM_EGR_COMG_Pos          (5U)

+#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */

+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */

+#define TIM_EGR_TG_Pos            (6U)

+#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */

+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */

+#define TIM_EGR_BG_Pos            (7U)

+#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */

+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */

+#define TIM_EGR_B2G_Pos           (8U)

+#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */

+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break Generation */

+

+

+/******************  Bit definition for TIM_CCMR1 register  *******************/

+#define TIM_CCMR1_CC1S_Pos        (0U)

+#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */

+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */

+#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */

+#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */

+

+#define TIM_CCMR1_OC1FE_Pos       (2U)

+#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */

+#define TIM_CCMR1_OC1PE_Pos       (3U)

+#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */

+

+#define TIM_CCMR1_OC1M_Pos        (4U)

+#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */

+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */

+#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */

+#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */

+#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */

+#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR1_OC1CE_Pos       (7U)

+#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */

+

+#define TIM_CCMR1_CC2S_Pos        (8U)

+#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */

+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */

+#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */

+#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */

+

+#define TIM_CCMR1_OC2FE_Pos       (10U)

+#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */

+#define TIM_CCMR1_OC2PE_Pos       (11U)

+#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */

+

+#define TIM_CCMR1_OC2M_Pos        (12U)

+#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */

+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */

+#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */

+#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */

+#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */

+#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */

+

+#define TIM_CCMR1_OC2CE_Pos       (15U)

+#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */

+

+/*----------------------------------------------------------------------------*/

+

+#define TIM_CCMR1_IC1PSC_Pos      (2U)

+#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */

+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */

+#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */

+

+#define TIM_CCMR1_IC1F_Pos        (4U)

+#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */

+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */

+#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */

+

+#define TIM_CCMR1_IC2PSC_Pos      (10U)

+#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */

+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */

+#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */

+

+#define TIM_CCMR1_IC2F_Pos        (12U)

+#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */

+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */

+#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */

+

+/******************  Bit definition for TIM_CCMR2 register  *******************/

+#define TIM_CCMR2_CC3S_Pos        (0U)

+#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */

+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */

+#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */

+#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */

+

+#define TIM_CCMR2_OC3FE_Pos       (2U)

+#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */

+#define TIM_CCMR2_OC3PE_Pos       (3U)

+#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */

+

+#define TIM_CCMR2_OC3M_Pos        (4U)

+#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */

+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */

+#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR2_OC3CE_Pos       (7U)

+#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */

+

+#define TIM_CCMR2_CC4S_Pos        (8U)

+#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */

+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */

+#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */

+#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */

+

+#define TIM_CCMR2_OC4FE_Pos       (10U)

+#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */

+#define TIM_CCMR2_OC4PE_Pos       (11U)

+#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */

+

+#define TIM_CCMR2_OC4M_Pos        (12U)

+#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */

+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */

+#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */

+

+#define TIM_CCMR2_OC4CE_Pos       (15U)

+#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */

+

+/*----------------------------------------------------------------------------*/

+

+#define TIM_CCMR2_IC3PSC_Pos      (2U)

+#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */

+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */

+#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */

+

+#define TIM_CCMR2_IC3F_Pos        (4U)

+#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */

+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */

+#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */

+

+#define TIM_CCMR2_IC4PSC_Pos      (10U)

+#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */

+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */

+#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */

+

+#define TIM_CCMR2_IC4F_Pos        (12U)

+#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */

+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */

+#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */

+

+/*******************  Bit definition for TIM_CCER register  *******************/

+#define TIM_CCER_CC1E_Pos         (0U)

+#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */

+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */

+#define TIM_CCER_CC1P_Pos         (1U)

+#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */

+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */

+#define TIM_CCER_CC1NE_Pos        (2U)

+#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */

+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */

+#define TIM_CCER_CC1NP_Pos        (3U)

+#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */

+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */

+#define TIM_CCER_CC2E_Pos         (4U)

+#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */

+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */

+#define TIM_CCER_CC2P_Pos         (5U)

+#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */

+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */

+#define TIM_CCER_CC2NE_Pos        (6U)

+#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */

+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */

+#define TIM_CCER_CC2NP_Pos        (7U)

+#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */

+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */

+#define TIM_CCER_CC3E_Pos         (8U)

+#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */

+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */

+#define TIM_CCER_CC3P_Pos         (9U)

+#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */

+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */

+#define TIM_CCER_CC3NE_Pos        (10U)

+#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */

+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */

+#define TIM_CCER_CC3NP_Pos        (11U)

+#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */

+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */

+#define TIM_CCER_CC4E_Pos         (12U)

+#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */

+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */

+#define TIM_CCER_CC4P_Pos         (13U)

+#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */

+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */

+#define TIM_CCER_CC4NP_Pos        (15U)

+#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */

+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */

+#define TIM_CCER_CC5E_Pos         (16U)

+#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */

+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */

+#define TIM_CCER_CC5P_Pos         (17U)

+#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */

+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */

+#define TIM_CCER_CC6E_Pos         (20U)

+#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */

+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */

+#define TIM_CCER_CC6P_Pos         (21U)

+#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */

+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */

+/*******************  Bit definition for TIM_CNT register  ********************/

+#define TIM_CNT_CNT_Pos           (0U)

+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */

+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */

+#define TIM_CNT_UIFCPY_Pos        (31U)

+#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */

+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy */

+/*******************  Bit definition for TIM_PSC register  ********************/

+#define TIM_PSC_PSC_Pos           (0U)

+#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */

+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */

+

+/*******************  Bit definition for TIM_ARR register  ********************/

+#define TIM_ARR_ARR_Pos           (0U)

+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */

+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */

+

+/*******************  Bit definition for TIM_RCR register  ********************/

+#define TIM_RCR_REP_Pos           (0U)

+#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                  /*!< 0x000000FF */

+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */

+

+/*******************  Bit definition for TIM_CCR1 register  *******************/

+#define TIM_CCR1_CCR1_Pos         (0U)

+#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */

+

+/*******************  Bit definition for TIM_CCR2 register  *******************/

+#define TIM_CCR2_CCR2_Pos         (0U)

+#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */

+

+/*******************  Bit definition for TIM_CCR3 register  *******************/

+#define TIM_CCR3_CCR3_Pos         (0U)

+#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */

+

+/*******************  Bit definition for TIM_CCR4 register  *******************/

+#define TIM_CCR4_CCR4_Pos         (0U)

+#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */

+

+/*******************  Bit definition for TIM_CCR5 register  *******************/

+#define TIM_CCR5_CCR5_Pos         (0U)

+#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */

+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */

+#define TIM_CCR5_GC5C1_Pos        (29U)

+#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */

+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */

+#define TIM_CCR5_GC5C2_Pos        (30U)

+#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */

+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */

+#define TIM_CCR5_GC5C3_Pos        (31U)

+#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */

+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */

+

+/*******************  Bit definition for TIM_CCR6 register  *******************/

+#define TIM_CCR6_CCR6_Pos         (0U)

+#define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */

+

+/*******************  Bit definition for TIM_BDTR register  *******************/

+#define TIM_BDTR_DTG_Pos          (0U)

+#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */

+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */

+#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */

+#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */

+#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */

+#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */

+#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */

+#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */

+#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */

+#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */

+

+#define TIM_BDTR_LOCK_Pos         (8U)

+#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */

+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */

+#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */

+#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */

+

+#define TIM_BDTR_OSSI_Pos         (10U)

+#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */

+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */

+#define TIM_BDTR_OSSR_Pos         (11U)

+#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */

+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */

+#define TIM_BDTR_BKE_Pos          (12U)

+#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */

+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break1 */

+#define TIM_BDTR_BKP_Pos          (13U)

+#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */

+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break1 */

+#define TIM_BDTR_AOE_Pos          (14U)

+#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */

+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */

+#define TIM_BDTR_MOE_Pos          (15U)

+#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */

+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */

+

+#define TIM_BDTR_BKF_Pos          (16U)

+#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */

+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break1 */

+#define TIM_BDTR_BK2F_Pos         (20U)

+#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */

+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break2 */

+

+#define TIM_BDTR_BK2E_Pos         (24U)

+#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */

+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break2 */

+#define TIM_BDTR_BK2P_Pos         (25U)

+#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */

+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */

+

+/*******************  Bit definition for TIM_DCR register  ********************/

+#define TIM_DCR_DBA_Pos           (0U)

+#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */

+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */

+#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */

+#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */

+#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */

+#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */

+#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */

+

+#define TIM_DCR_DBL_Pos           (8U)

+#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */

+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */

+#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */

+#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */

+#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */

+#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */

+#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */

+

+/*******************  Bit definition for TIM_DMAR register  *******************/

+#define TIM_DMAR_DMAB_Pos         (0U)

+#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */

+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */

+

+/******************  Bit definition for TIM_CCMR3 register  *******************/

+#define TIM_CCMR3_OC5FE_Pos       (2U)

+#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */

+#define TIM_CCMR3_OC5PE_Pos       (3U)

+#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */

+

+#define TIM_CCMR3_OC5M_Pos        (4U)

+#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */

+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */

+#define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR3_OC5CE_Pos       (7U)

+#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */

+

+#define TIM_CCMR3_OC6FE_Pos       (10U)

+#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 4 Fast enable */

+#define TIM_CCMR3_OC6PE_Pos       (11U)

+#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */

+

+#define TIM_CCMR3_OC6M_Pos        (12U)

+#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */

+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */

+#define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */

+

+#define TIM_CCMR3_OC6CE_Pos       (15U)

+#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 4 Clear Enable */

+/*******************  Bit definition for TIM1_AF1 register  *********************/

+#define TIM1_AF1_BKINE_Pos        (0U)

+#define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */

+#define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */

+#define TIM1_AF1_BKCMP1E_Pos      (1U)

+#define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */

+#define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM1_AF1_BKCMP2E_Pos      (2U)

+#define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */

+#define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit */

+#define TIM1_AF1_BKDF1BK0E_Pos    (8U)

+#define TIM1_AF1_BKDF1BK0E_Msk    (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)            /*!< 0x00000100 */

+#define TIM1_AF1_BKDF1BK0E        TIM1_AF1_BKDF1BK0E_Msk                       /*!<BKDF1BK0E Break input DFSDM Break 0 */

+#define TIM1_AF1_BKINP_Pos        (9U)

+#define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */

+#define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */

+#define TIM1_AF1_BKCMP1P_Pos      (10U)

+#define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */

+#define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM1_AF1_BKCMP2P_Pos      (11U)

+#define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */

+#define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */

+

+#define TIM1_AF1_ETRSEL_Pos       (14U)

+#define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */

+#define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */

+#define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00004000 */

+#define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00008000 */

+#define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00010000 */

+#define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM1_AF2 register  *********************/

+#define TIM1_AF2_BK2INE_Pos       (0U)

+#define TIM1_AF2_BK2INE_Msk       (0x1UL << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */

+#define TIM1_AF2_BK2INE           TIM1_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */

+#define TIM1_AF2_BK2CMP1E_Pos     (1U)

+#define TIM1_AF2_BK2CMP1E_Msk     (0x1UL << TIM1_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */

+#define TIM1_AF2_BK2CMP1E         TIM1_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */

+#define TIM1_AF2_BK2CMP2E_Pos     (2U)

+#define TIM1_AF2_BK2CMP2E_Msk     (0x1UL << TIM1_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */

+#define TIM1_AF2_BK2CMP2E         TIM1_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */

+#define TIM1_AF2_BK2DFBK1E_Pos    (8U)

+#define TIM1_AF2_BK2DFBK1E_Msk    (0x1UL << TIM1_AF2_BK2DFBK1E_Pos)            /*!< 0x00000100 */

+#define TIM1_AF2_BK2DFBK1E        TIM1_AF2_BK2DFBK1E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 1 */

+#define TIM1_AF2_BK2INP_Pos       (9U)

+#define TIM1_AF2_BK2INP_Msk       (0x1UL << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */

+#define TIM1_AF2_BK2INP           TIM1_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */

+#define TIM1_AF2_BK2CMP1P_Pos     (10U)

+#define TIM1_AF2_BK2CMP1P_Msk     (0x1UL << TIM1_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */

+#define TIM1_AF2_BK2CMP1P         TIM1_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */

+#define TIM1_AF2_BK2CMP2P_Pos     (11U)

+#define TIM1_AF2_BK2CMP2P_Msk     (0x1UL << TIM1_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */

+#define TIM1_AF2_BK2CMP2P         TIM1_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */

+

+/*******************  Bit definition for TIM_TISEL register  *********************/

+#define TIM_TISEL_TI1SEL_Pos      (0U)

+#define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */

+#define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/

+#define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000001 */

+#define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000002 */

+#define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000004 */

+#define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000008 */

+

+#define TIM_TISEL_TI2SEL_Pos      (8U)

+#define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */

+#define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/

+#define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000100 */

+#define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000200 */

+#define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000400 */

+#define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000800 */

+

+#define TIM_TISEL_TI3SEL_Pos      (16U)

+#define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */

+#define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/

+#define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00010000 */

+#define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00020000 */

+#define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00040000 */

+#define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00080000 */

+

+#define TIM_TISEL_TI4SEL_Pos      (24U)

+#define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */

+#define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/

+#define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x01000000 */

+#define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x02000000 */

+#define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x04000000 */

+#define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x08000000 */

+

+/*******************  Bit definition for TIM8_AF1 register  *********************/

+#define TIM8_AF1_BKINE_Pos        (0U)

+#define TIM8_AF1_BKINE_Msk        (0x1UL << TIM8_AF1_BKINE_Pos)                /*!< 0x00000001 */

+#define TIM8_AF1_BKINE            TIM8_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */

+#define TIM8_AF1_BKCMP1E_Pos      (1U)

+#define TIM8_AF1_BKCMP1E_Msk      (0x1UL << TIM8_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */

+#define TIM8_AF1_BKCMP1E          TIM8_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM8_AF1_BKCMP2E_Pos      (2U)

+#define TIM8_AF1_BKCMP2E_Msk      (0x1UL << TIM8_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */

+#define TIM8_AF1_BKCMP2E          TIM8_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM8_AF1_BKDFBK2E_Pos     (8U)

+#define TIM8_AF1_BKDFBK2E_Msk     (0x1UL << TIM8_AF1_BKDFBK2E_Pos)             /*!< 0x00000100 */

+#define TIM8_AF1_BKDFBK2E         TIM8_AF1_BKDFBK2E_Msk                        /*!<BKDFBK2E Break input DFSDM Break 2 */

+#define TIM8_AF1_BKINP_Pos        (9U)

+#define TIM8_AF1_BKINP_Msk        (0x1UL << TIM8_AF1_BKINP_Pos)                /*!< 0x00000200 */

+#define TIM8_AF1_BKINP            TIM8_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */

+#define TIM8_AF1_BKCMP1P_Pos      (10U)

+#define TIM8_AF1_BKCMP1P_Msk      (0x1UL << TIM8_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */

+#define TIM8_AF1_BKCMP1P          TIM8_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM8_AF1_BKCMP2P_Pos      (11U)

+#define TIM8_AF1_BKCMP2P_Msk      (0x1UL << TIM8_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */

+#define TIM8_AF1_BKCMP2P          TIM8_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */

+

+#define TIM8_AF1_ETRSEL_Pos       (14U)

+#define TIM8_AF1_ETRSEL_Msk       (0xFUL << TIM8_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */

+#define TIM8_AF1_ETRSEL           TIM8_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */

+#define TIM8_AF1_ETRSEL_0         (0x1UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00004000 */

+#define TIM8_AF1_ETRSEL_1         (0x2UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00008000 */

+#define TIM8_AF1_ETRSEL_2         (0x4UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00010000 */

+#define TIM8_AF1_ETRSEL_3         (0x8UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00020000 */

+/*******************  Bit definition for TIM8_AF2 register  *********************/

+#define TIM8_AF2_BK2INE_Pos       (0U)

+#define TIM8_AF2_BK2INE_Msk       (0x1UL << TIM8_AF2_BK2INE_Pos)               /*!< 0x00000001 */

+#define TIM8_AF2_BK2INE           TIM8_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */

+#define TIM8_AF2_BK2CMP1E_Pos     (1U)

+#define TIM8_AF2_BK2CMP1E_Msk     (0x1UL << TIM8_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */

+#define TIM8_AF2_BK2CMP1E         TIM8_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */

+#define TIM8_AF2_BK2CMP2E_Pos     (2U)

+#define TIM8_AF2_BK2CMP2E_Msk     (0x1UL << TIM8_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */

+#define TIM8_AF2_BK2CMP2E         TIM8_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */

+#define TIM8_AF2_BK2DFBK3E_Pos    (8U)

+#define TIM8_AF2_BK2DFBK3E_Msk    (0x1UL << TIM8_AF2_BK2DFBK3E_Pos)            /*!< 0x00000100 */

+#define TIM8_AF2_BK2DFBK3E        TIM8_AF2_BK2DFBK3E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 3 */

+#define TIM8_AF2_BK2INP_Pos       (9U)

+#define TIM8_AF2_BK2INP_Msk       (0x1UL << TIM8_AF2_BK2INP_Pos)               /*!< 0x00000200 */

+#define TIM8_AF2_BK2INP           TIM8_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */

+#define TIM8_AF2_BK2CMP1P_Pos     (10U)

+#define TIM8_AF2_BK2CMP1P_Msk     (0x1UL << TIM8_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */

+#define TIM8_AF2_BK2CMP1P         TIM8_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */

+#define TIM8_AF2_BK2CMP2P_Pos     (11U)

+#define TIM8_AF2_BK2CMP2P_Msk     (0x1UL << TIM8_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */

+#define TIM8_AF2_BK2CMP2P         TIM8_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */

+

+/*******************  Bit definition for TIM2_AF1 register  *********************/

+#define TIM2_AF1_ETRSEL_Pos      (14U)

+#define TIM2_AF1_ETRSEL_Msk      (0xFUL << TIM2_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM2_AF1_ETRSEL          TIM2_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */

+#define TIM2_AF1_ETRSEL_0        (0x1UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM2_AF1_ETRSEL_1        (0x2UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM2_AF1_ETRSEL_2        (0x4UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM2_AF1_ETRSEL_3        (0x8UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM3_AF1 register  *********************/

+#define TIM3_AF1_ETRSEL_Pos      (14U)

+#define TIM3_AF1_ETRSEL_Msk      (0xFUL << TIM3_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM3_AF1_ETRSEL          TIM3_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */

+#define TIM3_AF1_ETRSEL_0        (0x1UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM3_AF1_ETRSEL_1        (0x2UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM3_AF1_ETRSEL_2        (0x4UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM3_AF1_ETRSEL_3        (0x8UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM5_AF1 register  *********************/

+#define TIM5_AF1_ETRSEL_Pos      (14U)

+#define TIM5_AF1_ETRSEL_Msk      (0xFUL << TIM5_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM5_AF1_ETRSEL          TIM5_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */

+#define TIM5_AF1_ETRSEL_0        (0x1UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM5_AF1_ETRSEL_1        (0x2UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM5_AF1_ETRSEL_2        (0x4UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM5_AF1_ETRSEL_3        (0x8UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM15_AF1 register  *********************/

+#define TIM15_AF1_BKINE_Pos        (0U)

+#define TIM15_AF1_BKINE_Msk        (0x1UL << TIM15_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM15_AF1_BKINE            TIM15_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM15_AF1_BKCMP1E_Pos      (1U)

+#define TIM15_AF1_BKCMP1E_Msk      (0x1UL << TIM15_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM15_AF1_BKCMP1E          TIM15_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM15_AF1_BKCMP2E_Pos      (2U)

+#define TIM15_AF1_BKCMP2E_Msk      (0x1UL << TIM15_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM15_AF1_BKCMP2E          TIM15_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM15_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM15_AF1_BKDF1BK2E_Msk    (0x1UL << TIM15_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM15_AF1_BKDF1BK2E        TIM15_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[0] enable */

+#define TIM15_AF1_BKINP_Pos        (9U)

+#define TIM15_AF1_BKINP_Msk        (0x1UL << TIM15_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM15_AF1_BKINP            TIM15_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM15_AF1_BKCMP1P_Pos      (10U)

+#define TIM15_AF1_BKCMP1P_Msk      (0x1UL << TIM15_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM15_AF1_BKCMP1P          TIM15_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM15_AF1_BKCMP2P_Pos      (11U)

+#define TIM15_AF1_BKCMP2P_Msk      (0x1UL << TIM15_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM15_AF1_BKCMP2P          TIM15_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/*******************  Bit definition for TIM16_ register  *********************/

+#define TIM16_AF1_BKINE_Pos        (0U)

+#define TIM16_AF1_BKINE_Msk        (0x1UL << TIM16_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM16_AF1_BKINE            TIM16_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM16_AF1_BKCMP1E_Pos      (1U)

+#define TIM16_AF1_BKCMP1E_Msk      (0x1UL << TIM16_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM16_AF1_BKCMP1E          TIM16_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM16_AF1_BKCMP2E_Pos      (2U)

+#define TIM16_AF1_BKCMP2E_Msk      (0x1UL << TIM16_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM16_AF1_BKCMP2E          TIM16_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM16_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM16_AF1_BKDF1BK2E_Msk    (0x1UL << TIM16_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM16_AF1_BKDF1BK2E        TIM16_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[1] enable */

+#define TIM16_AF1_BKINP_Pos        (9U)

+#define TIM16_AF1_BKINP_Msk        (0x1UL << TIM16_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM16_AF1_BKINP            TIM16_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM16_AF1_BKCMP1P_Pos      (10U)

+#define TIM16_AF1_BKCMP1P_Msk      (0x1UL << TIM16_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM16_AF1_BKCMP1P          TIM16_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM16_AF1_BKCMP2P_Pos      (11U)

+#define TIM16_AF1_BKCMP2P_Msk      (0x1UL << TIM16_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM16_AF1_BKCMP2P          TIM16_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/*******************  Bit definition for TIM17_AF1 register  *********************/

+#define TIM17_AF1_BKINE_Pos        (0U)

+#define TIM17_AF1_BKINE_Msk        (0x1UL << TIM17_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM17_AF1_BKINE            TIM17_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM17_AF1_BKCMP1E_Pos      (1U)

+#define TIM17_AF1_BKCMP1E_Msk      (0x1UL << TIM17_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM17_AF1_BKCMP1E          TIM17_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM17_AF1_BKCMP2E_Pos      (2U)

+#define TIM17_AF1_BKCMP2E_Msk      (0x1UL << TIM17_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM17_AF1_BKCMP2E          TIM17_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM17_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM17_AF1_BKDF1BK2E_Msk    (0x1UL << TIM17_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM17_AF1_BKDF1BK2E        TIM17_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[2] enable */

+#define TIM17_AF1_BKINP_Pos        (9U)

+#define TIM17_AF1_BKINP_Msk        (0x1UL << TIM17_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM17_AF1_BKINP            TIM17_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM17_AF1_BKCMP1P_Pos      (10U)

+#define TIM17_AF1_BKCMP1P_Msk      (0x1UL << TIM17_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM17_AF1_BKCMP1P          TIM17_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM17_AF1_BKCMP2P_Pos      (11U)

+#define TIM17_AF1_BKCMP2P_Msk      (0x1UL << TIM17_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM17_AF1_BKCMP2P          TIM17_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Low Power Timer (LPTTIM)                           */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for LPTIM_ISR register  *******************/

+#define LPTIM_ISR_CMPM_Pos          (0U)

+#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */

+#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */

+#define LPTIM_ISR_ARRM_Pos          (1U)

+#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */

+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */

+#define LPTIM_ISR_EXTTRIG_Pos       (2U)

+#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */

+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */

+#define LPTIM_ISR_CMPOK_Pos         (3U)

+#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */

+#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */

+#define LPTIM_ISR_ARROK_Pos         (4U)

+#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */

+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */

+#define LPTIM_ISR_UP_Pos            (5U)

+#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */

+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */

+#define LPTIM_ISR_DOWN_Pos          (6U)

+#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */

+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */

+

+/******************  Bit definition for LPTIM_ICR register  *******************/

+#define LPTIM_ICR_CMPMCF_Pos        (0U)

+#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */

+#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */

+#define LPTIM_ICR_ARRMCF_Pos        (1U)

+#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */

+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */

+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)

+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */

+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */

+#define LPTIM_ICR_CMPOKCF_Pos       (3U)

+#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */

+#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */

+#define LPTIM_ICR_ARROKCF_Pos       (4U)

+#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */

+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */

+#define LPTIM_ICR_UPCF_Pos          (5U)

+#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */

+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */

+#define LPTIM_ICR_DOWNCF_Pos        (6U)

+#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */

+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */

+

+/******************  Bit definition for LPTIM_IER register ********************/

+#define LPTIM_IER_CMPMIE_Pos        (0U)

+#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */

+#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */

+#define LPTIM_IER_ARRMIE_Pos        (1U)

+#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */

+#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */

+#define LPTIM_IER_EXTTRIGIE_Pos     (2U)

+#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */

+#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */

+#define LPTIM_IER_CMPOKIE_Pos       (3U)

+#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */

+#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */

+#define LPTIM_IER_ARROKIE_Pos       (4U)

+#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */

+#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */

+#define LPTIM_IER_UPIE_Pos          (5U)

+#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */

+#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */

+#define LPTIM_IER_DOWNIE_Pos        (6U)

+#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */

+#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */

+

+/******************  Bit definition for LPTIM_CFGR register *******************/

+#define LPTIM_CFGR_CKSEL_Pos        (0U)

+#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */

+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */

+

+#define LPTIM_CFGR_CKPOL_Pos        (1U)

+#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */

+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */

+#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */

+#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */

+

+#define LPTIM_CFGR_CKFLT_Pos        (3U)

+#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */

+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */

+#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */

+#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */

+

+#define LPTIM_CFGR_TRGFLT_Pos       (6U)

+#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */

+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */

+#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */

+#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */

+

+#define LPTIM_CFGR_PRESC_Pos        (9U)

+#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */

+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */

+#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */

+#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */

+#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */

+

+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)

+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */

+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */

+#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */

+#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */

+#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */

+

+#define LPTIM_CFGR_TRIGEN_Pos       (17U)

+#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */

+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */

+#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */

+#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */

+

+#define LPTIM_CFGR_TIMOUT_Pos       (19U)

+#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */

+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */

+#define LPTIM_CFGR_WAVE_Pos         (20U)

+#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */

+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */

+#define LPTIM_CFGR_WAVPOL_Pos       (21U)

+#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */

+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */

+#define LPTIM_CFGR_PRELOAD_Pos      (22U)

+#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */

+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */

+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)

+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */

+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */

+#define LPTIM_CFGR_ENC_Pos          (24U)

+#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */

+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */

+

+/******************  Bit definition for LPTIM_CR register  ********************/

+#define LPTIM_CR_ENABLE_Pos         (0U)

+#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */

+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */

+#define LPTIM_CR_SNGSTRT_Pos        (1U)

+#define LPTIM_CR_SNGSTRT_Msk        (0x40001UL << LPTIM_CR_SNGSTRT_Pos)        /*!< 0x00080002 */

+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */

+#define LPTIM_CR_CNTSTRT_Pos        (2U)

+#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */

+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */

+#define LPTIM_CR_COUNTRST_Pos       (3U)

+#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */

+#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Timer Counter reset in synchronous mode*/

+#define LPTIM_CR_RSTARE_Pos         (4U)

+#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */

+#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Timer Counter reset after read enable (asynchronously)*/

+

+

+/******************  Bit definition for LPTIM_CMP register  *******************/

+#define LPTIM_CMP_CMP_Pos           (0U)

+#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */

+

+/******************  Bit definition for LPTIM_ARR register  *******************/

+#define LPTIM_ARR_ARR_Pos           (0U)

+#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */

+

+/******************  Bit definition for LPTIM_CNT register  *******************/

+#define LPTIM_CNT_CNT_Pos           (0U)

+#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */

+

+/******************  Bit definition for LPTIM_CFGR2 register  *****************/

+#define LPTIM_CFGR2_IN1SEL_Pos      (0U)

+#define LPTIM_CFGR2_IN1SEL_Msk      (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000003 */

+#define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< IN1SEL[1:0] bits (Remap selection) */

+#define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000001 */

+#define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000002 */

+#define LPTIM_CFGR2_IN2SEL_Pos      (4U)

+#define LPTIM_CFGR2_IN2SEL_Msk      (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000030 */

+#define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< IN2SEL[5:4] bits (Remap selection) */

+#define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000010 */

+#define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000020 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      Analog Comparators (COMP)                             */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for COMP_SR register  ********************/

+#define COMP_SR_C1VAL_Pos            (0U)

+#define COMP_SR_C1VAL_Msk            (0x1UL << COMP_SR_C1VAL_Pos)              /*!< 0x00000001 */

+#define COMP_SR_C1VAL                COMP_SR_C1VAL_Msk

+#define COMP_SR_C2VAL_Pos            (1U)

+#define COMP_SR_C2VAL_Msk            (0x1UL << COMP_SR_C2VAL_Pos)              /*!< 0x00000002 */

+#define COMP_SR_C2VAL                COMP_SR_C2VAL_Msk

+#define COMP_SR_C1IF_Pos             (16U)

+#define COMP_SR_C1IF_Msk             (0x1UL << COMP_SR_C1IF_Pos)               /*!< 0x00010000 */

+#define COMP_SR_C1IF                 COMP_SR_C1IF_Msk

+#define COMP_SR_C2IF_Pos             (17U)

+#define COMP_SR_C2IF_Msk             (0x1UL << COMP_SR_C2IF_Pos)               /*!< 0x00020000 */

+#define COMP_SR_C2IF                 COMP_SR_C2IF_Msk

+/*******************  Bit definition for COMP_ICFR register  ********************/

+#define COMP_ICFR_C1IF_Pos           (16U)

+#define COMP_ICFR_C1IF_Msk           (0x1UL << COMP_ICFR_C1IF_Pos)             /*!< 0x00010000 */

+#define COMP_ICFR_C1IF               COMP_ICFR_C1IF_Msk

+#define COMP_ICFR_C2IF_Pos           (17U)

+#define COMP_ICFR_C2IF_Msk           (0x1UL << COMP_ICFR_C2IF_Pos)             /*!< 0x00020000 */

+#define COMP_ICFR_C2IF               COMP_ICFR_C2IF_Msk

+/*******************  Bit definition for COMP_OR register  ********************/

+#define COMP_OR_AFOPA6_Pos           (0U)

+#define COMP_OR_AFOPA6_Msk           (0x1UL << COMP_OR_AFOPA6_Pos)             /*!< 0x00000001 */

+#define COMP_OR_AFOPA6               COMP_OR_AFOPA6_Msk

+#define COMP_OR_AFOPA8_Pos           (1U)

+#define COMP_OR_AFOPA8_Msk           (0x1UL << COMP_OR_AFOPA8_Pos)             /*!< 0x00000002 */

+#define COMP_OR_AFOPA8               COMP_OR_AFOPA8_Msk

+#define COMP_OR_AFOPB12_Pos          (2U)

+#define COMP_OR_AFOPB12_Msk          (0x1UL << COMP_OR_AFOPB12_Pos)            /*!< 0x00000004 */

+#define COMP_OR_AFOPB12              COMP_OR_AFOPB12_Msk

+#define COMP_OR_AFOPE6_Pos           (3U)

+#define COMP_OR_AFOPE6_Msk           (0x1UL << COMP_OR_AFOPE6_Pos)             /*!< 0x00000008 */

+#define COMP_OR_AFOPE6               COMP_OR_AFOPE6_Msk

+#define COMP_OR_AFOPE15_Pos          (4U)

+#define COMP_OR_AFOPE15_Msk          (0x1UL << COMP_OR_AFOPE15_Pos)            /*!< 0x00000010 */

+#define COMP_OR_AFOPE15              COMP_OR_AFOPE15_Msk

+#define COMP_OR_AFOPG2_Pos           (5U)

+#define COMP_OR_AFOPG2_Msk           (0x1UL << COMP_OR_AFOPG2_Pos)             /*!< 0x00000020 */

+#define COMP_OR_AFOPG2               COMP_OR_AFOPG2_Msk

+#define COMP_OR_AFOPG3_Pos           (6U)

+#define COMP_OR_AFOPG3_Msk           (0x1UL << COMP_OR_AFOPG3_Pos)             /*!< 0x00000040 */

+#define COMP_OR_AFOPG3               COMP_OR_AFOPG3_Msk

+#define COMP_OR_AFOPG4_Pos           (7U)

+#define COMP_OR_AFOPG4_Msk           (0x1UL << COMP_OR_AFOPG4_Pos)             /*!< 0x00000080 */

+#define COMP_OR_AFOPG4               COMP_OR_AFOPG4_Msk

+#define COMP_OR_AFOPI1_Pos           (8U)

+#define COMP_OR_AFOPI1_Msk           (0x1UL << COMP_OR_AFOPI1_Pos)             /*!< 0x00000100 */

+#define COMP_OR_AFOPI1               COMP_OR_AFOPI1_Msk

+#define COMP_OR_AFOPI4_Pos           (9U)

+#define COMP_OR_AFOPI4_Msk           (0x1UL << COMP_OR_AFOPI4_Pos)             /*!< 0x00000200 */

+#define COMP_OR_AFOPI4               COMP_OR_AFOPI4_Msk

+#define COMP_OR_AFOPK2_Pos           (10U)

+#define COMP_OR_AFOPK2_Msk           (0x1UL << COMP_OR_AFOPK2_Pos)             /*!< 0x00000400 */

+#define COMP_OR_AFOPK2               COMP_OR_AFOPK2_Msk

+

+/*!< ******************  Bit definition for COMP_CFGRx register  ********************/

+#define COMP_CFGRx_EN_Pos            (0U)

+#define COMP_CFGRx_EN_Msk            (0x1UL << COMP_CFGRx_EN_Pos)              /*!< 0x00000001 */

+#define COMP_CFGRx_EN                COMP_CFGRx_EN_Msk                         /*!< COMPx enable bit                     */

+#define COMP_CFGRx_BRGEN_Pos         (1U)

+#define COMP_CFGRx_BRGEN_Msk         (0x1UL << COMP_CFGRx_BRGEN_Pos)           /*!< 0x00000002 */

+#define COMP_CFGRx_BRGEN             COMP_CFGRx_BRGEN_Msk                      /*!< COMPx Scaler bridge enable           */

+#define COMP_CFGRx_SCALEN_Pos        (2U)

+#define COMP_CFGRx_SCALEN_Msk        (0x1UL << COMP_CFGRx_SCALEN_Pos)          /*!< 0x00000004 */

+#define COMP_CFGRx_SCALEN            COMP_CFGRx_SCALEN_Msk                     /*!< COMPx Voltage scaler enable bit      */

+#define COMP_CFGRx_POLARITY_Pos      (3U)

+#define COMP_CFGRx_POLARITY_Msk      (0x1UL << COMP_CFGRx_POLARITY_Pos)        /*!< 0x00000008 */

+#define COMP_CFGRx_POLARITY          COMP_CFGRx_POLARITY_Msk                   /*!< COMPx  polarity selection bit        */

+#define COMP_CFGRx_WINMODE_Pos       (4U)

+#define COMP_CFGRx_WINMODE_Msk       (0x1UL << COMP_CFGRx_WINMODE_Pos)         /*!< 0x00000010 */

+#define COMP_CFGRx_WINMODE           COMP_CFGRx_WINMODE_Msk                    /*!< COMPx Windows mode selection bit     */

+#define COMP_CFGRx_ITEN_Pos          (6U)

+#define COMP_CFGRx_ITEN_Msk          (0x1UL << COMP_CFGRx_ITEN_Pos)            /*!< 0x00000040 */

+#define COMP_CFGRx_ITEN              COMP_CFGRx_ITEN_Msk                       /*!< COMPx  interrupt enable              */

+#define COMP_CFGRx_HYST_Pos          (8U)

+#define COMP_CFGRx_HYST_Msk          (0x3UL << COMP_CFGRx_HYST_Pos)            /*!< 0x00000300 */

+#define COMP_CFGRx_HYST              COMP_CFGRx_HYST_Msk                       /*!< COMPx  hysteresis selection bits     */

+#define COMP_CFGRx_HYST_0            (0x1UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000100 */

+#define COMP_CFGRx_HYST_1            (0x2UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000200 */

+#define COMP_CFGRx_PWRMODE_Pos       (12U)

+#define COMP_CFGRx_PWRMODE_Msk       (0x3UL << COMP_CFGRx_PWRMODE_Pos)         /*!< 0x00003000 */

+#define COMP_CFGRx_PWRMODE           COMP_CFGRx_PWRMODE_Msk                    /*!< COMPx Power Mode of the comparator   */

+#define COMP_CFGRx_PWRMODE_0         (0x1UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00001000 */

+#define COMP_CFGRx_PWRMODE_1         (0x2UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00002000 */

+#define COMP_CFGRx_INMSEL_Pos        (16U)

+#define COMP_CFGRx_INMSEL_Msk        (0x7UL << COMP_CFGRx_INMSEL_Pos)          /*!< 0x00070000 */

+#define COMP_CFGRx_INMSEL            COMP_CFGRx_INMSEL_Msk                     /*!< COMPx  input minus selection bit  */

+#define COMP_CFGRx_INMSEL_0          (0x1UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00010000 */

+#define COMP_CFGRx_INMSEL_1          (0x2UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00020000 */

+#define COMP_CFGRx_INMSEL_2          (0x4UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00040000 */

+#define COMP_CFGRx_INPSEL_Pos        (20U)

+#define COMP_CFGRx_INPSEL_Msk        (0x1UL << COMP_CFGRx_INPSEL_Pos)          /*!< 0x00100000 */

+#define COMP_CFGRx_INPSEL            COMP_CFGRx_INPSEL_Msk                     /*!< COMPx  input plus selection bit       */

+#define COMP_CFGRx_BLANKING_Pos      (24U)

+#define COMP_CFGRx_BLANKING_Msk      (0xFUL << COMP_CFGRx_BLANKING_Pos)        /*!< 0x0F000000 */

+#define COMP_CFGRx_BLANKING          COMP_CFGRx_BLANKING_Msk                   /*!< COMPx  blanking source selection bits */

+#define COMP_CFGRx_BLANKING_0        (0x1UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x01000000 */

+#define COMP_CFGRx_BLANKING_1        (0x2UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x02000000 */

+#define COMP_CFGRx_BLANKING_2        (0x4UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x04000000 */

+#define COMP_CFGRx_LOCK_Pos          (31U)

+#define COMP_CFGRx_LOCK_Msk          (0x1UL << COMP_CFGRx_LOCK_Pos)            /*!< 0x80000000 */

+#define COMP_CFGRx_LOCK              COMP_CFGRx_LOCK_Msk                       /*!< COMPx Lock Bit                        */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for USART_CR1 register  *******************/

+#define USART_CR1_UE_Pos                (0U)

+#define USART_CR1_UE_Msk                (0x1UL << USART_CR1_UE_Pos)            /*!< 0x00000001 */

+#define USART_CR1_UE                    USART_CR1_UE_Msk                       /*!< USART Enable */

+#define USART_CR1_UESM_Pos              (1U)

+#define USART_CR1_UESM_Msk              (0x1UL << USART_CR1_UESM_Pos)          /*!< 0x00000002 */

+#define USART_CR1_UESM                  USART_CR1_UESM_Msk                     /*!< USART Enable in STOP Mode */

+#define USART_CR1_RE_Pos                (2U)

+#define USART_CR1_RE_Msk                (0x1UL << USART_CR1_RE_Pos)            /*!< 0x00000004 */

+#define USART_CR1_RE                    USART_CR1_RE_Msk                       /*!< Receiver Enable */

+#define USART_CR1_TE_Pos                (3U)

+#define USART_CR1_TE_Msk                (0x1UL << USART_CR1_TE_Pos)            /*!< 0x00000008 */

+#define USART_CR1_TE                    USART_CR1_TE_Msk                       /*!< Transmitter Enable */

+#define USART_CR1_IDLEIE_Pos            (4U)

+#define USART_CR1_IDLEIE_Msk            (0x1UL << USART_CR1_IDLEIE_Pos)        /*!< 0x00000010 */

+#define USART_CR1_IDLEIE                USART_CR1_IDLEIE_Msk                   /*!< IDLE Interrupt Enable */

+#define USART_CR1_RXNEIE_RXFNEIE_Pos    (5U)

+#define USART_CR1_RXNEIE_RXFNEIE_Msk    (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */

+#define USART_CR1_RXNEIE_RXFNEIE        USART_CR1_RXNEIE_RXFNEIE_Msk           /*!< RXNE and RX FIFO Not Empty Interrupt Enable */

+#define USART_CR1_TCIE_Pos              (6U)

+#define USART_CR1_TCIE_Msk              (0x1UL << USART_CR1_TCIE_Pos)          /*!< 0x00000040 */

+#define USART_CR1_TCIE                  USART_CR1_TCIE_Msk                     /*!< Transmission Complete Interrupt Enable */

+#define USART_CR1_TXEIE_TXFNFIE_Pos     (7U)

+#define USART_CR1_TXEIE_TXFNFIE_Msk     (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */

+#define USART_CR1_TXEIE_TXFNFIE         USART_CR1_TXEIE_TXFNFIE_Msk            /*!< TXE and TX FIFO Not Full Interrupt Enable */

+#define USART_CR1_PEIE_Pos              (8U)

+#define USART_CR1_PEIE_Msk              (0x1UL << USART_CR1_PEIE_Pos)          /*!< 0x00000100 */

+#define USART_CR1_PEIE                  USART_CR1_PEIE_Msk                     /*!< PE Interrupt Enable */

+#define USART_CR1_PS_Pos                (9U)

+#define USART_CR1_PS_Msk                (0x1UL << USART_CR1_PS_Pos)            /*!< 0x00000200 */

+#define USART_CR1_PS                    USART_CR1_PS_Msk                       /*!< Parity Selection */

+#define USART_CR1_PCE_Pos               (10U)

+#define USART_CR1_PCE_Msk               (0x1UL << USART_CR1_PCE_Pos)           /*!< 0x00000400 */

+#define USART_CR1_PCE                   USART_CR1_PCE_Msk                      /*!< Parity Control Enable */

+#define USART_CR1_WAKE_Pos              (11U)

+#define USART_CR1_WAKE_Msk              (0x1UL << USART_CR1_WAKE_Pos)          /*!< 0x00000800 */

+#define USART_CR1_WAKE                  USART_CR1_WAKE_Msk                     /*!< Receiver Wakeup method */

+#define USART_CR1_M_Pos                 (12U)

+#define USART_CR1_M_Msk                 (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */

+#define USART_CR1_M                     USART_CR1_M_Msk                        /*!< Word length */

+#define USART_CR1_M0_Pos                (12U)

+#define USART_CR1_M0_Msk                (0x1UL << USART_CR1_M0_Pos)            /*!< 0x00001000 */

+#define USART_CR1_M0                    USART_CR1_M0_Msk                       /*!< Word length - Bit 0 */

+#define USART_CR1_MME_Pos               (13U)

+#define USART_CR1_MME_Msk               (0x1UL << USART_CR1_MME_Pos)           /*!< 0x00002000 */

+#define USART_CR1_MME                   USART_CR1_MME_Msk                      /*!< Mute Mode Enable */

+#define USART_CR1_CMIE_Pos              (14U)

+#define USART_CR1_CMIE_Msk              (0x1UL << USART_CR1_CMIE_Pos)          /*!< 0x00004000 */

+#define USART_CR1_CMIE                  USART_CR1_CMIE_Msk                     /*!< Character match interrupt enable */

+#define USART_CR1_OVER8_Pos             (15U)

+#define USART_CR1_OVER8_Msk             (0x1UL << USART_CR1_OVER8_Pos)         /*!< 0x00008000 */

+#define USART_CR1_OVER8                 USART_CR1_OVER8_Msk                    /*!< Oversampling by 8-bit or 16-bit mode */

+#define USART_CR1_DEDT_Pos              (16U)

+#define USART_CR1_DEDT_Msk              (0x1FUL << USART_CR1_DEDT_Pos)         /*!< 0x001F0000 */

+#define USART_CR1_DEDT                  USART_CR1_DEDT_Msk                     /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */

+#define USART_CR1_DEDT_0                (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */

+#define USART_CR1_DEDT_1                (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */

+#define USART_CR1_DEDT_2                (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */

+#define USART_CR1_DEDT_3                (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */

+#define USART_CR1_DEDT_4                (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */

+#define USART_CR1_DEAT_Pos              (21U)

+#define USART_CR1_DEAT_Msk              (0x1FUL << USART_CR1_DEAT_Pos)         /*!< 0x03E00000 */

+#define USART_CR1_DEAT                  USART_CR1_DEAT_Msk                     /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */

+#define USART_CR1_DEAT_0                (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */

+#define USART_CR1_DEAT_1                (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */

+#define USART_CR1_DEAT_2                (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */

+#define USART_CR1_DEAT_3                (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */

+#define USART_CR1_DEAT_4                (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */

+#define USART_CR1_RTOIE_Pos             (26U)

+#define USART_CR1_RTOIE_Msk             (0x1UL << USART_CR1_RTOIE_Pos)         /*!< 0x04000000 */

+#define USART_CR1_RTOIE                 USART_CR1_RTOIE_Msk                    /*!< Receive Time Out interrupt enable */

+#define USART_CR1_EOBIE_Pos             (27U)

+#define USART_CR1_EOBIE_Msk             (0x1UL << USART_CR1_EOBIE_Pos)         /*!< 0x08000000 */

+#define USART_CR1_EOBIE                 USART_CR1_EOBIE_Msk                    /*!< End of Block interrupt enable */

+#define USART_CR1_M1_Pos                (28U)

+#define USART_CR1_M1_Msk                (0x1UL << USART_CR1_M1_Pos)            /*!< 0x10000000 */

+#define USART_CR1_M1                    USART_CR1_M1_Msk                       /*!< Word length - Bit 1 */

+#define USART_CR1_FIFOEN_Pos            (29U)

+#define USART_CR1_FIFOEN_Msk            (0x1UL << USART_CR1_FIFOEN_Pos)        /*!< 0x20000000 */

+#define USART_CR1_FIFOEN                USART_CR1_FIFOEN_Msk                   /*!< FIFO mode enable */

+#define USART_CR1_TXFEIE_Pos            (30U)

+#define USART_CR1_TXFEIE_Msk            (0x1UL << USART_CR1_TXFEIE_Pos)        /*!< 0x40000000 */

+#define USART_CR1_TXFEIE                USART_CR1_TXFEIE_Msk                   /*!< TXFIFO empty interrupt enable */

+#define USART_CR1_RXFFIE_Pos            (31U)

+#define USART_CR1_RXFFIE_Msk            (0x1UL << USART_CR1_RXFFIE_Pos)        /*!< 0x80000000 */

+#define USART_CR1_RXFFIE                USART_CR1_RXFFIE_Msk                   /*!< RXFIFO Full interrupt enable */

+

+/* Legacy define */

+#define  USART_CR1_RXNEIE  USART_CR1_RXNEIE_RXFNEIE

+#define  USART_CR1_TXEIE   USART_CR1_TXEIE_TXFNFIE

+

+/******************  Bit definition for USART_CR2 register  *******************/

+#define USART_CR2_SLVEN_Pos             (0U)

+#define USART_CR2_SLVEN_Msk             (0x1UL << USART_CR2_SLVEN_Pos)         /*!< 0x00000001 */

+#define USART_CR2_SLVEN                 USART_CR2_SLVEN_Msk                    /*!< Synchronous Slave mode Enable */

+#define USART_CR2_DIS_NSS_Pos           (3U)

+#define USART_CR2_DIS_NSS_Msk           (0x1UL << USART_CR2_DIS_NSS_Pos)       /*!< 0x00000008 */

+#define USART_CR2_DIS_NSS               USART_CR2_DIS_NSS_Msk                  /*!< Negative Slave Select (NSS) pin management */

+#define USART_CR2_ADDM7_Pos             (4U)

+#define USART_CR2_ADDM7_Msk             (0x1UL << USART_CR2_ADDM7_Pos)         /*!< 0x00000010 */

+#define USART_CR2_ADDM7                 USART_CR2_ADDM7_Msk                    /*!< 7-bit or 4-bit Address Detection */

+#define USART_CR2_LBDL_Pos              (5U)

+#define USART_CR2_LBDL_Msk              (0x1UL << USART_CR2_LBDL_Pos)          /*!< 0x00000020 */

+#define USART_CR2_LBDL                  USART_CR2_LBDL_Msk                     /*!< LIN Break Detection Length */

+#define USART_CR2_LBDIE_Pos             (6U)

+#define USART_CR2_LBDIE_Msk             (0x1UL << USART_CR2_LBDIE_Pos)         /*!< 0x00000040 */

+#define USART_CR2_LBDIE                 USART_CR2_LBDIE_Msk                    /*!< LIN Break Detection Interrupt Enable */

+#define USART_CR2_LBCL_Pos              (8U)

+#define USART_CR2_LBCL_Msk              (0x1UL << USART_CR2_LBCL_Pos)          /*!< 0x00000100 */

+#define USART_CR2_LBCL                  USART_CR2_LBCL_Msk                     /*!< Last Bit Clock pulse */

+#define USART_CR2_CPHA_Pos              (9U)

+#define USART_CR2_CPHA_Msk              (0x1UL << USART_CR2_CPHA_Pos)          /*!< 0x00000200 */

+#define USART_CR2_CPHA                  USART_CR2_CPHA_Msk                     /*!< Clock Phase */

+#define USART_CR2_CPOL_Pos              (10U)

+#define USART_CR2_CPOL_Msk              (0x1UL << USART_CR2_CPOL_Pos)          /*!< 0x00000400 */

+#define USART_CR2_CPOL                  USART_CR2_CPOL_Msk                     /*!< Clock Polarity */

+#define USART_CR2_CLKEN_Pos             (11U)

+#define USART_CR2_CLKEN_Msk             (0x1UL << USART_CR2_CLKEN_Pos)         /*!< 0x00000800 */

+#define USART_CR2_CLKEN                 USART_CR2_CLKEN_Msk                    /*!< Clock Enable */

+#define USART_CR2_STOP_Pos              (12U)

+#define USART_CR2_STOP_Msk              (0x3UL << USART_CR2_STOP_Pos)          /*!< 0x00003000 */

+#define USART_CR2_STOP                  USART_CR2_STOP_Msk                     /*!< STOP[1:0] bits (STOP bits) */

+#define USART_CR2_STOP_0                (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */

+#define USART_CR2_STOP_1                (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */

+#define USART_CR2_LINEN_Pos             (14U)

+#define USART_CR2_LINEN_Msk             (0x1UL << USART_CR2_LINEN_Pos)         /*!< 0x00004000 */

+#define USART_CR2_LINEN                 USART_CR2_LINEN_Msk                    /*!< LIN mode enable */

+#define USART_CR2_SWAP_Pos              (15U)

+#define USART_CR2_SWAP_Msk              (0x1UL << USART_CR2_SWAP_Pos)          /*!< 0x00008000 */

+#define USART_CR2_SWAP                  USART_CR2_SWAP_Msk                     /*!< SWAP TX/RX pins */

+#define USART_CR2_RXINV_Pos             (16U)

+#define USART_CR2_RXINV_Msk             (0x1UL << USART_CR2_RXINV_Pos)         /*!< 0x00010000 */

+#define USART_CR2_RXINV                 USART_CR2_RXINV_Msk                    /*!< RX pin active level inversion */

+#define USART_CR2_TXINV_Pos             (17U)

+#define USART_CR2_TXINV_Msk             (0x1UL << USART_CR2_TXINV_Pos)         /*!< 0x00020000 */

+#define USART_CR2_TXINV                 USART_CR2_TXINV_Msk                    /*!< TX pin active level inversion */

+#define USART_CR2_DATAINV_Pos           (18U)

+#define USART_CR2_DATAINV_Msk           (0x1UL << USART_CR2_DATAINV_Pos)       /*!< 0x00040000 */

+#define USART_CR2_DATAINV               USART_CR2_DATAINV_Msk                  /*!< Binary data inversion */

+#define USART_CR2_MSBFIRST_Pos          (19U)

+#define USART_CR2_MSBFIRST_Msk          (0x1UL << USART_CR2_MSBFIRST_Pos)      /*!< 0x00080000 */

+#define USART_CR2_MSBFIRST              USART_CR2_MSBFIRST_Msk                 /*!< Most Significant Bit First */

+#define USART_CR2_ABREN_Pos             (20U)

+#define USART_CR2_ABREN_Msk             (0x1UL << USART_CR2_ABREN_Pos)         /*!< 0x00100000 */

+#define USART_CR2_ABREN                 USART_CR2_ABREN_Msk                    /*!< Auto Baud-Rate Enable*/

+#define USART_CR2_ABRMODE_Pos           (21U)

+#define USART_CR2_ABRMODE_Msk           (0x3UL << USART_CR2_ABRMODE_Pos)       /*!< 0x00600000 */

+#define USART_CR2_ABRMODE               USART_CR2_ABRMODE_Msk                  /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */

+#define USART_CR2_ABRMODE_0             (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */

+#define USART_CR2_ABRMODE_1             (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */

+#define USART_CR2_RTOEN_Pos             (23U)

+#define USART_CR2_RTOEN_Msk             (0x1UL << USART_CR2_RTOEN_Pos)         /*!< 0x00800000 */

+#define USART_CR2_RTOEN                 USART_CR2_RTOEN_Msk                    /*!< Receiver Time-Out enable */

+#define USART_CR2_ADD_Pos               (24U)

+#define USART_CR2_ADD_Msk               (0xFFUL << USART_CR2_ADD_Pos)          /*!< 0xFF000000 */

+#define USART_CR2_ADD                   USART_CR2_ADD_Msk                      /*!< Address of the USART node */

+

+/******************  Bit definition for USART_CR3 register  *******************/

+#define USART_CR3_EIE_Pos               (0U)

+#define USART_CR3_EIE_Msk               (0x1UL << USART_CR3_EIE_Pos)           /*!< 0x00000001 */

+#define USART_CR3_EIE                   USART_CR3_EIE_Msk                      /*!< Error Interrupt Enable */

+#define USART_CR3_IREN_Pos              (1U)

+#define USART_CR3_IREN_Msk              (0x1UL << USART_CR3_IREN_Pos)          /*!< 0x00000002 */

+#define USART_CR3_IREN                  USART_CR3_IREN_Msk                     /*!< IrDA mode Enable */

+#define USART_CR3_IRLP_Pos              (2U)

+#define USART_CR3_IRLP_Msk              (0x1UL << USART_CR3_IRLP_Pos)          /*!< 0x00000004 */

+#define USART_CR3_IRLP                  USART_CR3_IRLP_Msk                     /*!< IrDA Low-Power */

+#define USART_CR3_HDSEL_Pos             (3U)

+#define USART_CR3_HDSEL_Msk             (0x1UL << USART_CR3_HDSEL_Pos)         /*!< 0x00000008 */

+#define USART_CR3_HDSEL                 USART_CR3_HDSEL_Msk                    /*!< Half-Duplex Selection */

+#define USART_CR3_NACK_Pos              (4U)

+#define USART_CR3_NACK_Msk              (0x1UL << USART_CR3_NACK_Pos)          /*!< 0x00000010 */

+#define USART_CR3_NACK                  USART_CR3_NACK_Msk                     /*!< SmartCard NACK enable */

+#define USART_CR3_SCEN_Pos              (5U)

+#define USART_CR3_SCEN_Msk              (0x1UL << USART_CR3_SCEN_Pos)          /*!< 0x00000020 */

+#define USART_CR3_SCEN                  USART_CR3_SCEN_Msk                     /*!< SmartCard mode enable */

+#define USART_CR3_DMAR_Pos              (6U)

+#define USART_CR3_DMAR_Msk              (0x1UL << USART_CR3_DMAR_Pos)          /*!< 0x00000040 */

+#define USART_CR3_DMAR                  USART_CR3_DMAR_Msk                     /*!< DMA Enable Receiver */

+#define USART_CR3_DMAT_Pos              (7U)

+#define USART_CR3_DMAT_Msk              (0x1UL << USART_CR3_DMAT_Pos)          /*!< 0x00000080 */

+#define USART_CR3_DMAT                  USART_CR3_DMAT_Msk                     /*!< DMA Enable Transmitter */

+#define USART_CR3_RTSE_Pos              (8U)

+#define USART_CR3_RTSE_Msk              (0x1UL << USART_CR3_RTSE_Pos)          /*!< 0x00000100 */

+#define USART_CR3_RTSE                  USART_CR3_RTSE_Msk                     /*!< RTS Enable */

+#define USART_CR3_CTSE_Pos              (9U)

+#define USART_CR3_CTSE_Msk              (0x1UL << USART_CR3_CTSE_Pos)          /*!< 0x00000200 */

+#define USART_CR3_CTSE                  USART_CR3_CTSE_Msk                     /*!< CTS Enable */

+#define USART_CR3_CTSIE_Pos             (10U)

+#define USART_CR3_CTSIE_Msk             (0x1UL << USART_CR3_CTSIE_Pos)         /*!< 0x00000400 */

+#define USART_CR3_CTSIE                 USART_CR3_CTSIE_Msk                    /*!< CTS Interrupt Enable */

+#define USART_CR3_ONEBIT_Pos            (11U)

+#define USART_CR3_ONEBIT_Msk            (0x1UL << USART_CR3_ONEBIT_Pos)        /*!< 0x00000800 */

+#define USART_CR3_ONEBIT                USART_CR3_ONEBIT_Msk                   /*!< One sample bit method enable */

+#define USART_CR3_OVRDIS_Pos            (12U)

+#define USART_CR3_OVRDIS_Msk            (0x1UL << USART_CR3_OVRDIS_Pos)        /*!< 0x00001000 */

+#define USART_CR3_OVRDIS                USART_CR3_OVRDIS_Msk                   /*!< Overrun Disable */

+#define USART_CR3_DDRE_Pos              (13U)

+#define USART_CR3_DDRE_Msk              (0x1UL << USART_CR3_DDRE_Pos)          /*!< 0x00002000 */

+#define USART_CR3_DDRE                  USART_CR3_DDRE_Msk                     /*!< DMA Disable on Reception Error */

+#define USART_CR3_DEM_Pos               (14U)

+#define USART_CR3_DEM_Msk               (0x1UL << USART_CR3_DEM_Pos)           /*!< 0x00004000 */

+#define USART_CR3_DEM                   USART_CR3_DEM_Msk                      /*!< Driver Enable Mode */

+#define USART_CR3_DEP_Pos               (15U)

+#define USART_CR3_DEP_Msk               (0x1UL << USART_CR3_DEP_Pos)           /*!< 0x00008000 */

+#define USART_CR3_DEP                   USART_CR3_DEP_Msk                      /*!< Driver Enable Polarity Selection */

+#define USART_CR3_SCARCNT_Pos           (17U)

+#define USART_CR3_SCARCNT_Msk           (0x7UL << USART_CR3_SCARCNT_Pos)       /*!< 0x000E0000 */

+#define USART_CR3_SCARCNT               USART_CR3_SCARCNT_Msk                  /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */

+#define USART_CR3_SCARCNT_0             (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */

+#define USART_CR3_SCARCNT_1             (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */

+#define USART_CR3_SCARCNT_2             (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */

+#define USART_CR3_WUS_Pos               (20U)

+#define USART_CR3_WUS_Msk               (0x3UL << USART_CR3_WUS_Pos)           /*!< 0x00300000 */

+#define USART_CR3_WUS                   USART_CR3_WUS_Msk                      /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */

+#define USART_CR3_WUS_0                 (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */

+#define USART_CR3_WUS_1                 (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */

+#define USART_CR3_WUFIE_Pos             (22U)

+#define USART_CR3_WUFIE_Msk             (0x1UL << USART_CR3_WUFIE_Pos)         /*!< 0x00400000 */

+#define USART_CR3_WUFIE                 USART_CR3_WUFIE_Msk                    /*!< Wake Up Interrupt Enable */

+#define USART_CR3_TXFTIE_Pos            (23U)

+#define USART_CR3_TXFTIE_Msk            (0x1UL << USART_CR3_TXFTIE_Pos)        /*!< 0x00800000 */

+#define USART_CR3_TXFTIE                USART_CR3_TXFTIE_Msk                   /*!< TXFIFO threshold interrupt enable */

+#define USART_CR3_TCBGTIE_Pos           (24U)

+#define USART_CR3_TCBGTIE_Msk           (0x1UL << USART_CR3_TCBGTIE_Pos)       /*!< 0x01000000 */

+#define USART_CR3_TCBGTIE               USART_CR3_TCBGTIE_Msk                  /*!< Transmission Complete before guard time, interrupt enable */

+#define USART_CR3_RXFTCFG_Pos           (25U)

+#define USART_CR3_RXFTCFG_Msk           (0x7UL << USART_CR3_RXFTCFG_Pos)       /*!< 0x0E000000 */

+#define USART_CR3_RXFTCFG               USART_CR3_RXFTCFG_Msk                  /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */

+#define USART_CR3_RXFTCFG_0             (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */

+#define USART_CR3_RXFTCFG_1             (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */

+#define USART_CR3_RXFTCFG_2             (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */

+#define USART_CR3_RXFTIE_Pos            (28U)

+#define USART_CR3_RXFTIE_Msk            (0x1UL << USART_CR3_RXFTIE_Pos)        /*!< 0x10000000 */

+#define USART_CR3_RXFTIE                USART_CR3_RXFTIE_Msk                   /*!< RXFIFO threshold interrupt enable */

+#define USART_CR3_TXFTCFG_Pos           (29U)

+#define USART_CR3_TXFTCFG_Msk           (0x7UL << USART_CR3_TXFTCFG_Pos)       /*!< 0xE0000000 */

+#define USART_CR3_TXFTCFG               USART_CR3_TXFTCFG_Msk                  /*!< TXFIFO [2:0] threshold configuration */

+#define USART_CR3_TXFTCFG_0             (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */

+#define USART_CR3_TXFTCFG_1             (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */

+#define USART_CR3_TXFTCFG_2             (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */

+

+/******************  Bit definition for USART_BRR register  *******************/

+#define USART_BRR_DIV_FRACTION_Pos      (0U)

+#define USART_BRR_DIV_FRACTION_Msk      (0xFUL << USART_BRR_DIV_FRACTION_Pos)  /*!< 0x0000000F */

+#define USART_BRR_DIV_FRACTION          USART_BRR_DIV_FRACTION_Msk             /*!< Fraction of USARTDIV */

+#define USART_BRR_DIV_MANTISSA_Pos      (4U)

+#define USART_BRR_DIV_MANTISSA_Msk      (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */

+#define USART_BRR_DIV_MANTISSA          USART_BRR_DIV_MANTISSA_Msk             /*!< Mantissa of USARTDIV */

+

+/******************  Bit definition for USART_GTPR register  ******************/

+#define USART_GTPR_PSC_Pos              (0U)

+#define USART_GTPR_PSC_Msk              (0xFFUL << USART_GTPR_PSC_Pos)         /*!< 0x000000FF */

+#define USART_GTPR_PSC                  USART_GTPR_PSC_Msk                     /*!< PSC[7:0] bits (Prescaler value) */

+#define USART_GTPR_GT_Pos               (8U)

+#define USART_GTPR_GT_Msk               (0xFFUL << USART_GTPR_GT_Pos)          /*!< 0x0000FF00 */

+#define USART_GTPR_GT                   USART_GTPR_GT_Msk                      /*!< GT[7:0] bits (Guard time value) */

+

+/*******************  Bit definition for USART_RTOR register  *****************/

+#define USART_RTOR_RTO_Pos              (0U)

+#define USART_RTOR_RTO_Msk              (0xFFFFFFUL << USART_RTOR_RTO_Pos)     /*!< 0x00FFFFFF */

+#define USART_RTOR_RTO                  USART_RTOR_RTO_Msk                     /*!< Receiver Time Out Value */

+#define USART_RTOR_BLEN_Pos             (24U)

+#define USART_RTOR_BLEN_Msk             (0xFFUL << USART_RTOR_BLEN_Pos)        /*!< 0xFF000000 */

+#define USART_RTOR_BLEN                 USART_RTOR_BLEN_Msk                    /*!< Block Length */

+

+/*******************  Bit definition for USART_RQR register  ******************/

+#define USART_RQR_ABRRQ_Pos             (0U)

+#define USART_RQR_ABRRQ_Msk             (0x1UL << USART_RQR_ABRRQ_Pos)         /*!< 0x00000001 */

+#define USART_RQR_ABRRQ                 USART_RQR_ABRRQ_Msk                    /*!< Auto-Baud Rate Request */

+#define USART_RQR_SBKRQ_Pos             (1U)

+#define USART_RQR_SBKRQ_Msk             (0x1UL << USART_RQR_SBKRQ_Pos)         /*!< 0x00000002 */

+#define USART_RQR_SBKRQ                 USART_RQR_SBKRQ_Msk                    /*!< Send Break Request */

+#define USART_RQR_MMRQ_Pos              (2U)

+#define USART_RQR_MMRQ_Msk              (0x1UL << USART_RQR_MMRQ_Pos)          /*!< 0x00000004 */

+#define USART_RQR_MMRQ                  USART_RQR_MMRQ_Msk                     /*!< Mute Mode Request */

+#define USART_RQR_RXFRQ_Pos             (3U)

+#define USART_RQR_RXFRQ_Msk             (0x1UL << USART_RQR_RXFRQ_Pos)         /*!< 0x00000008 */

+#define USART_RQR_RXFRQ                 USART_RQR_RXFRQ_Msk                    /*!< Receive Data flush Request */

+#define USART_RQR_TXFRQ_Pos             (4U)

+#define USART_RQR_TXFRQ_Msk             (0x1UL << USART_RQR_TXFRQ_Pos)         /*!< 0x00000010 */

+#define USART_RQR_TXFRQ                 USART_RQR_TXFRQ_Msk                    /*!< Transmit data flush Request */

+

+/*******************  Bit definition for USART_ISR register  ******************/

+#define USART_ISR_PE_Pos                (0U)

+#define USART_ISR_PE_Msk                (0x1UL << USART_ISR_PE_Pos)            /*!< 0x00000001 */

+#define USART_ISR_PE                    USART_ISR_PE_Msk                       /*!< Parity Error */

+#define USART_ISR_FE_Pos                (1U)

+#define USART_ISR_FE_Msk                (0x1UL << USART_ISR_FE_Pos)            /*!< 0x00000002 */

+#define USART_ISR_FE                    USART_ISR_FE_Msk                       /*!< Framing Error */

+#define USART_ISR_NE_Pos                (2U)

+#define USART_ISR_NE_Msk                (0x1UL << USART_ISR_NE_Pos)            /*!< 0x00000004 */

+#define USART_ISR_NE                    USART_ISR_NE_Msk                       /*!< Noise detected Flag */

+#define USART_ISR_ORE_Pos               (3U)

+#define USART_ISR_ORE_Msk               (0x1UL << USART_ISR_ORE_Pos)           /*!< 0x00000008 */

+#define USART_ISR_ORE                   USART_ISR_ORE_Msk                      /*!< OverRun Error */

+#define USART_ISR_IDLE_Pos              (4U)

+#define USART_ISR_IDLE_Msk              (0x1UL << USART_ISR_IDLE_Pos)          /*!< 0x00000010 */

+#define USART_ISR_IDLE                  USART_ISR_IDLE_Msk                     /*!< IDLE line detected */

+#define USART_ISR_RXNE_RXFNE_Pos        (5U)

+#define USART_ISR_RXNE_RXFNE_Msk        (0x1UL << USART_ISR_RXNE_RXFNE_Pos)    /*!< 0x00000020 */

+#define USART_ISR_RXNE_RXFNE            USART_ISR_RXNE_RXFNE_Msk               /*!< Read Data Register or RX FIFO Not Empty */

+#define USART_ISR_TC_Pos                (6U)

+#define USART_ISR_TC_Msk                (0x1UL << USART_ISR_TC_Pos)            /*!< 0x00000040 */

+#define USART_ISR_TC                    USART_ISR_TC_Msk                       /*!< Transmission Complete */

+#define USART_ISR_TXE_TXFNF_Pos         (7U)

+#define USART_ISR_TXE_TXFNF_Msk         (0x1UL << USART_ISR_TXE_TXFNF_Pos)     /*!< 0x00000080 */

+#define USART_ISR_TXE_TXFNF             USART_ISR_TXE_TXFNF_Msk                /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */

+#define USART_ISR_LBDF_Pos              (8U)

+#define USART_ISR_LBDF_Msk              (0x1UL << USART_ISR_LBDF_Pos)          /*!< 0x00000100 */

+#define USART_ISR_LBDF                  USART_ISR_LBDF_Msk                     /*!< LIN Break Detection Flag */

+#define USART_ISR_CTSIF_Pos             (9U)

+#define USART_ISR_CTSIF_Msk             (0x1UL << USART_ISR_CTSIF_Pos)         /*!< 0x00000200 */

+#define USART_ISR_CTSIF                 USART_ISR_CTSIF_Msk                    /*!< CTS interrupt flag */

+#define USART_ISR_CTS_Pos               (10U)

+#define USART_ISR_CTS_Msk               (0x1UL << USART_ISR_CTS_Pos)           /*!< 0x00000400 */

+#define USART_ISR_CTS                   USART_ISR_CTS_Msk                      /*!< CTS flag */

+#define USART_ISR_RTOF_Pos              (11U)

+#define USART_ISR_RTOF_Msk              (0x1UL << USART_ISR_RTOF_Pos)          /*!< 0x00000800 */

+#define USART_ISR_RTOF                  USART_ISR_RTOF_Msk                     /*!< Receiver Time Out */

+#define USART_ISR_EOBF_Pos              (12U)

+#define USART_ISR_EOBF_Msk              (0x1UL << USART_ISR_EOBF_Pos)          /*!< 0x00001000 */

+#define USART_ISR_EOBF                  USART_ISR_EOBF_Msk                     /*!< End Of Block Flag */

+#define USART_ISR_UDR_Pos               (13U)

+#define USART_ISR_UDR_Msk               (0x1UL << USART_ISR_UDR_Pos)           /*!< 0x00002000 */

+#define USART_ISR_UDR                   USART_ISR_UDR_Msk                      /*!< SPI slave underrun error flag */

+#define USART_ISR_ABRE_Pos              (14U)

+#define USART_ISR_ABRE_Msk              (0x1UL << USART_ISR_ABRE_Pos)          /*!< 0x00004000 */

+#define USART_ISR_ABRE                  USART_ISR_ABRE_Msk                     /*!< Auto-Baud Rate Error */

+#define USART_ISR_ABRF_Pos              (15U)

+#define USART_ISR_ABRF_Msk              (0x1UL << USART_ISR_ABRF_Pos)          /*!< 0x00008000 */

+#define USART_ISR_ABRF                  USART_ISR_ABRF_Msk                     /*!< Auto-Baud Rate Flag */

+#define USART_ISR_BUSY_Pos              (16U)

+#define USART_ISR_BUSY_Msk              (0x1UL << USART_ISR_BUSY_Pos)          /*!< 0x00010000 */

+#define USART_ISR_BUSY                  USART_ISR_BUSY_Msk                     /*!< Busy Flag */

+#define USART_ISR_CMF_Pos               (17U)

+#define USART_ISR_CMF_Msk               (0x1UL << USART_ISR_CMF_Pos)           /*!< 0x00020000 */

+#define USART_ISR_CMF                   USART_ISR_CMF_Msk                      /*!< Character Match Flag */

+#define USART_ISR_SBKF_Pos              (18U)

+#define USART_ISR_SBKF_Msk              (0x1UL << USART_ISR_SBKF_Pos)          /*!< 0x00040000 */

+#define USART_ISR_SBKF                  USART_ISR_SBKF_Msk                     /*!< Send Break Flag */

+#define USART_ISR_RWU_Pos               (19U)

+#define USART_ISR_RWU_Msk               (0x1UL << USART_ISR_RWU_Pos)           /*!< 0x00080000 */

+#define USART_ISR_RWU                   USART_ISR_RWU_Msk                      /*!< Receive Wake Up from mute mode Flag */

+#define USART_ISR_WUF_Pos               (20U)

+#define USART_ISR_WUF_Msk               (0x1UL << USART_ISR_WUF_Pos)           /*!< 0x00100000 */

+#define USART_ISR_WUF                   USART_ISR_WUF_Msk                      /*!< Wake Up from stop mode Flag */

+#define USART_ISR_TEACK_Pos             (21U)

+#define USART_ISR_TEACK_Msk             (0x1UL << USART_ISR_TEACK_Pos)         /*!< 0x00200000 */

+#define USART_ISR_TEACK                 USART_ISR_TEACK_Msk                    /*!< Transmit Enable Acknowledge Flag */

+#define USART_ISR_REACK_Pos             (22U)

+#define USART_ISR_REACK_Msk             (0x1UL << USART_ISR_REACK_Pos)         /*!< 0x00400000 */

+#define USART_ISR_REACK                 USART_ISR_REACK_Msk                    /*!< Receive Enable Acknowledge Flag */

+#define USART_ISR_TXFE_Pos              (23U)

+#define USART_ISR_TXFE_Msk              (0x1UL << USART_ISR_TXFE_Pos)          /*!< 0x00800000 */

+#define USART_ISR_TXFE                  USART_ISR_TXFE_Msk                     /*!< TXFIFO Empty */

+#define USART_ISR_RXFF_Pos              (24U)

+#define USART_ISR_RXFF_Msk              (0x1UL << USART_ISR_RXFF_Pos)          /*!< 0x01000000 */

+#define USART_ISR_RXFF                  USART_ISR_RXFF_Msk                     /*!< RXFIFO Full Flag */

+#define USART_ISR_TCBGT_Pos             (25U)

+#define USART_ISR_TCBGT_Msk             (0x1UL << USART_ISR_TCBGT_Pos)         /*!< 0x02000000 */

+#define USART_ISR_TCBGT                 USART_ISR_TCBGT_Msk                    /*!< Transmission complete before guard time Flag */

+#define USART_ISR_RXFT_Pos              (26U)

+#define USART_ISR_RXFT_Msk              (0x1UL << USART_ISR_RXFT_Pos)          /*!< 0x04000000 */

+#define USART_ISR_RXFT                  USART_ISR_RXFT_Msk                     /*!< RXFIFO threshold Flag */

+#define USART_ISR_TXFT_Pos              (27U)

+#define USART_ISR_TXFT_Msk              (0x1UL << USART_ISR_TXFT_Pos)          /*!< 0x08000000 */

+#define USART_ISR_TXFT                  USART_ISR_TXFT_Msk                     /*!< TXFIFO threshold Flag */

+

+/*******************  Bit definition for USART_ICR register  ******************/

+#define USART_ICR_PECF_Pos              (0U)

+#define USART_ICR_PECF_Msk              (0x1UL << USART_ICR_PECF_Pos)          /*!< 0x00000001 */

+#define USART_ICR_PECF                  USART_ICR_PECF_Msk                     /*!< Parity Error Clear Flag */

+#define USART_ICR_FECF_Pos              (1U)

+#define USART_ICR_FECF_Msk              (0x1UL << USART_ICR_FECF_Pos)          /*!< 0x00000002 */

+#define USART_ICR_FECF                  USART_ICR_FECF_Msk                     /*!< Framing Error Clear Flag */

+#define USART_ICR_NECF_Pos              (2U)

+#define USART_ICR_NECF_Msk              (0x1UL << USART_ICR_NECF_Pos)          /*!< 0x00000004 */

+#define USART_ICR_NECF                  USART_ICR_NECF_Msk                     /*!< Noise detected Clear Flag */

+#define USART_ICR_ORECF_Pos             (3U)

+#define USART_ICR_ORECF_Msk             (0x1UL << USART_ICR_ORECF_Pos)         /*!< 0x00000008 */

+#define USART_ICR_ORECF                 USART_ICR_ORECF_Msk                    /*!< OverRun Error Clear Flag */

+#define USART_ICR_IDLECF_Pos            (4U)

+#define USART_ICR_IDLECF_Msk            (0x1UL << USART_ICR_IDLECF_Pos)        /*!< 0x00000010 */

+#define USART_ICR_IDLECF                USART_ICR_IDLECF_Msk                   /*!< IDLE line detected Clear Flag */

+#define USART_ICR_TXFECF_Pos            (5U)

+#define USART_ICR_TXFECF_Msk            (0x1UL << USART_ICR_TXFECF_Pos)        /*!< 0x00000020 */

+#define USART_ICR_TXFECF                USART_ICR_TXFECF_Msk                   /*!< TXFIFO empty clear flag */

+#define USART_ICR_TCCF_Pos              (6U)

+#define USART_ICR_TCCF_Msk              (0x1UL << USART_ICR_TCCF_Pos)          /*!< 0x00000040 */

+#define USART_ICR_TCCF                  USART_ICR_TCCF_Msk                     /*!< Transmission Complete Clear Flag */

+#define USART_ICR_TCBGTCF_Pos           (7U)

+#define USART_ICR_TCBGTCF_Msk           (0x1UL << USART_ICR_TCBGTCF_Pos)       /*!< 0x00000080 */

+#define USART_ICR_TCBGTCF               USART_ICR_TCBGTCF_Msk                  /*!< Transmission complete before guard time Clear Flag */

+#define USART_ICR_LBDCF_Pos             (8U)

+#define USART_ICR_LBDCF_Msk             (0x1UL << USART_ICR_LBDCF_Pos)         /*!< 0x00000100 */

+#define USART_ICR_LBDCF                 USART_ICR_LBDCF_Msk                    /*!< LIN Break Detection Clear Flag */

+#define USART_ICR_CTSCF_Pos             (9U)

+#define USART_ICR_CTSCF_Msk             (0x1UL << USART_ICR_CTSCF_Pos)         /*!< 0x00000200 */

+#define USART_ICR_CTSCF                 USART_ICR_CTSCF_Msk                    /*!< CTS Interrupt Clear Flag */

+#define USART_ICR_RTOCF_Pos             (11U)

+#define USART_ICR_RTOCF_Msk             (0x1UL << USART_ICR_RTOCF_Pos)         /*!< 0x00000800 */

+#define USART_ICR_RTOCF                 USART_ICR_RTOCF_Msk                    /*!< Receiver Time Out Clear Flag */

+#define USART_ICR_EOBCF_Pos             (12U)

+#define USART_ICR_EOBCF_Msk             (0x1UL << USART_ICR_EOBCF_Pos)         /*!< 0x00001000 */

+#define USART_ICR_EOBCF                 USART_ICR_EOBCF_Msk                    /*!< End Of Block Clear Flag */

+#define USART_ICR_UDRCF_Pos             (13U)

+#define USART_ICR_UDRCF_Msk             (0x1UL << USART_ICR_UDRCF_Pos)         /*!< 0x00002000 */

+#define USART_ICR_UDRCF                 USART_ICR_UDRCF_Msk                    /*!< SPI slave underrun clear flag */

+#define USART_ICR_CMCF_Pos              (17U)

+#define USART_ICR_CMCF_Msk              (0x1UL << USART_ICR_CMCF_Pos)          /*!< 0x00020000 */

+#define USART_ICR_CMCF                  USART_ICR_CMCF_Msk                     /*!< Character Match Clear Flag */

+#define USART_ICR_WUCF_Pos              (20U)

+#define USART_ICR_WUCF_Msk              (0x1UL << USART_ICR_WUCF_Pos)          /*!< 0x00100000 */

+#define USART_ICR_WUCF                  USART_ICR_WUCF_Msk                     /*!< Wake Up from stop mode Clear Flag */

+

+/*******************  Bit definition for USART_RDR register  ******************/

+#define USART_RDR_RDR_Pos               (0U)

+#define USART_RDR_RDR_Msk               (0x1FFUL << USART_RDR_RDR_Pos)         /*!< 0x000001FF */

+#define USART_RDR_RDR                   USART_RDR_RDR_Msk                      /*!< RDR[8:0] bits (Receive Data value) */

+

+/*******************  Bit definition for USART_TDR register  ******************/

+#define USART_TDR_TDR_Pos               (0U)

+#define USART_TDR_TDR_Msk               (0x1FFUL << USART_TDR_TDR_Pos)         /*!< 0x000001FF */

+#define USART_TDR_TDR                   USART_TDR_TDR_Msk                      /*!< TDR[8:0] bits (Transmit Data value) */

+

+/*******************  Bit definition for USART_PRESC register  ******************/

+#define USART_PRESC_PRESCALER_Pos       (0U)

+#define USART_PRESC_PRESCALER_Msk       (0xFUL << USART_PRESC_PRESCALER_Pos)   /*!< 0x0000000F */

+#define USART_PRESC_PRESCALER           USART_PRESC_PRESCALER_Msk              /*!< PRESCALER[3:0] bits (Clock prescaler) */

+#define USART_PRESC_PRESCALER_0         (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */

+#define USART_PRESC_PRESCALER_1         (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */

+#define USART_PRESC_PRESCALER_2         (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */

+#define USART_PRESC_PRESCALER_3         (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */

+

+/******************************************************************************/

+/*                                                                            */

+/*           Single Wire Protocol Master Interface (SWPMI)                    */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for SWPMI_CR register   ********************/

+#define SWPMI_CR_RXDMA_Pos       (0U)

+#define SWPMI_CR_RXDMA_Msk       (0x1UL << SWPMI_CR_RXDMA_Pos)                 /*!< 0x00000001 */

+#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */

+#define SWPMI_CR_TXDMA_Pos       (1U)

+#define SWPMI_CR_TXDMA_Msk       (0x1UL << SWPMI_CR_TXDMA_Pos)                 /*!< 0x00000002 */

+#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */

+#define SWPMI_CR_RXMODE_Pos      (2U)

+#define SWPMI_CR_RXMODE_Msk      (0x1UL << SWPMI_CR_RXMODE_Pos)                /*!< 0x00000004 */

+#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */

+#define SWPMI_CR_TXMODE_Pos      (3U)

+#define SWPMI_CR_TXMODE_Msk      (0x1UL << SWPMI_CR_TXMODE_Pos)                /*!< 0x00000008 */

+#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */

+#define SWPMI_CR_LPBK_Pos        (4U)

+#define SWPMI_CR_LPBK_Msk        (0x1UL << SWPMI_CR_LPBK_Pos)                  /*!< 0x00000010 */

+#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */

+#define SWPMI_CR_SWPACT_Pos      (5U)

+#define SWPMI_CR_SWPACT_Msk      (0x1UL << SWPMI_CR_SWPACT_Pos)                /*!< 0x00000020 */

+#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */

+#define SWPMI_CR_DEACT_Pos       (10U)

+#define SWPMI_CR_DEACT_Msk       (0x1UL << SWPMI_CR_DEACT_Pos)                 /*!< 0x00000400 */

+#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */

+#define SWPMI_CR_SWPEN_Pos       (11U)

+#define SWPMI_CR_SWPEN_Msk       (0x1UL << SWPMI_CR_SWPEN_Pos)                 /*!< 0x00000800 */

+#define SWPMI_CR_SWPEN           SWPMI_CR_SWPEN_Msk                            /*!<Single wire protocol master transceiver enable       */

+

+/*******************  Bit definition for SWPMI_BRR register  ********************/

+#define SWPMI_BRR_BR_Pos         (0U)

+#define SWPMI_BRR_BR_Msk         (0xFFUL << SWPMI_BRR_BR_Pos)                  /*!< 0x000000FF */

+#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[7:0] bits (Bitrate prescaler) */

+

+/*******************  Bit definition for SWPMI_ISR register  ********************/

+#define SWPMI_ISR_RXBFF_Pos      (0U)

+#define SWPMI_ISR_RXBFF_Msk      (0x1UL << SWPMI_ISR_RXBFF_Pos)                /*!< 0x00000001 */

+#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */

+#define SWPMI_ISR_TXBEF_Pos      (1U)

+#define SWPMI_ISR_TXBEF_Msk      (0x1UL << SWPMI_ISR_TXBEF_Pos)                /*!< 0x00000002 */

+#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */

+#define SWPMI_ISR_RXBERF_Pos     (2U)

+#define SWPMI_ISR_RXBERF_Msk     (0x1UL << SWPMI_ISR_RXBERF_Pos)               /*!< 0x00000004 */

+#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */

+#define SWPMI_ISR_RXOVRF_Pos     (3U)

+#define SWPMI_ISR_RXOVRF_Msk     (0x1UL << SWPMI_ISR_RXOVRF_Pos)               /*!< 0x00000008 */

+#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */

+#define SWPMI_ISR_TXUNRF_Pos     (4U)

+#define SWPMI_ISR_TXUNRF_Msk     (0x1UL << SWPMI_ISR_TXUNRF_Pos)               /*!< 0x00000010 */

+#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */

+#define SWPMI_ISR_RXNE_Pos       (5U)

+#define SWPMI_ISR_RXNE_Msk       (0x1UL << SWPMI_ISR_RXNE_Pos)                 /*!< 0x00000020 */

+#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */

+#define SWPMI_ISR_TXE_Pos        (6U)

+#define SWPMI_ISR_TXE_Msk        (0x1UL << SWPMI_ISR_TXE_Pos)                  /*!< 0x00000040 */

+#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */

+#define SWPMI_ISR_TCF_Pos        (7U)

+#define SWPMI_ISR_TCF_Msk        (0x1UL << SWPMI_ISR_TCF_Pos)                  /*!< 0x00000080 */

+#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */

+#define SWPMI_ISR_SRF_Pos        (8U)

+#define SWPMI_ISR_SRF_Msk        (0x1UL << SWPMI_ISR_SRF_Pos)                  /*!< 0x00000100 */

+#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */

+#define SWPMI_ISR_SUSP_Pos       (9U)

+#define SWPMI_ISR_SUSP_Msk       (0x1UL << SWPMI_ISR_SUSP_Pos)                 /*!< 0x00000200 */

+#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */

+#define SWPMI_ISR_DEACTF_Pos     (10U)

+#define SWPMI_ISR_DEACTF_Msk     (0x1UL << SWPMI_ISR_DEACTF_Pos)               /*!< 0x00000400 */

+#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */

+#define SWPMI_ISR_RDYF_Pos       (11U)

+#define SWPMI_ISR_RDYF_Msk       (0x1UL << SWPMI_ISR_RDYF_Pos)                 /*!< 0x00000800 */

+#define SWPMI_ISR_RDYF           SWPMI_ISR_RDYF_Msk                            /*!<Transceiver ready flag          */

+

+/*******************  Bit definition for SWPMI_ICR register  ********************/

+#define SWPMI_ICR_CRXBFF_Pos     (0U)

+#define SWPMI_ICR_CRXBFF_Msk     (0x1UL << SWPMI_ICR_CRXBFF_Pos)               /*!< 0x00000001 */

+#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */

+#define SWPMI_ICR_CTXBEF_Pos     (1U)

+#define SWPMI_ICR_CTXBEF_Msk     (0x1UL << SWPMI_ICR_CTXBEF_Pos)               /*!< 0x00000002 */

+#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */

+#define SWPMI_ICR_CRXBERF_Pos    (2U)

+#define SWPMI_ICR_CRXBERF_Msk    (0x1UL << SWPMI_ICR_CRXBERF_Pos)              /*!< 0x00000004 */

+#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */

+#define SWPMI_ICR_CRXOVRF_Pos    (3U)

+#define SWPMI_ICR_CRXOVRF_Msk    (0x1UL << SWPMI_ICR_CRXOVRF_Pos)              /*!< 0x00000008 */

+#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */

+#define SWPMI_ICR_CTXUNRF_Pos    (4U)

+#define SWPMI_ICR_CTXUNRF_Msk    (0x1UL << SWPMI_ICR_CTXUNRF_Pos)              /*!< 0x00000010 */

+#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */

+#define SWPMI_ICR_CTCF_Pos       (7U)

+#define SWPMI_ICR_CTCF_Msk       (0x1UL << SWPMI_ICR_CTCF_Pos)                 /*!< 0x00000080 */

+#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */

+#define SWPMI_ICR_CSRF_Pos       (8U)

+#define SWPMI_ICR_CSRF_Msk       (0x1UL << SWPMI_ICR_CSRF_Pos)                 /*!< 0x00000100 */

+#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */

+#define SWPMI_ICR_CRDYF_Pos      (11U)

+#define SWPMI_ICR_CRDYF_Msk      (0x1UL << SWPMI_ICR_CRDYF_Pos)                /*!< 0x00000800 */

+#define SWPMI_ICR_CRDYF          SWPMI_ICR_CRDYF_Msk                           /*!<Clear transceiver ready flag         */

+

+/*******************  Bit definition for SWPMI_IER register  ********************/

+#define SWPMI_IER_RXBFIE_Pos     (0U)

+#define SWPMI_IER_RXBFIE_Msk     (0x1UL << SWPMI_IER_RXBFIE_Pos)               /*!< 0x00000001 */

+#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */

+#define SWPMI_IER_TXBEIE_Pos     (1U)

+#define SWPMI_IER_TXBEIE_Msk     (0x1UL << SWPMI_IER_TXBEIE_Pos)               /*!< 0x00000002 */

+#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */

+#define SWPMI_IER_RXBERIE_Pos    (2U)

+#define SWPMI_IER_RXBERIE_Msk    (0x1UL << SWPMI_IER_RXBERIE_Pos)              /*!< 0x00000004 */

+#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */

+#define SWPMI_IER_RXOVRIE_Pos    (3U)

+#define SWPMI_IER_RXOVRIE_Msk    (0x1UL << SWPMI_IER_RXOVRIE_Pos)              /*!< 0x00000008 */

+#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */

+#define SWPMI_IER_TXUNRIE_Pos    (4U)

+#define SWPMI_IER_TXUNRIE_Msk    (0x1UL << SWPMI_IER_TXUNRIE_Pos)              /*!< 0x00000010 */

+#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */

+#define SWPMI_IER_RIE_Pos        (5U)

+#define SWPMI_IER_RIE_Msk        (0x1UL << SWPMI_IER_RIE_Pos)                  /*!< 0x00000020 */

+#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */

+#define SWPMI_IER_TIE_Pos        (6U)

+#define SWPMI_IER_TIE_Msk        (0x1UL << SWPMI_IER_TIE_Pos)                  /*!< 0x00000040 */

+#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */

+#define SWPMI_IER_TCIE_Pos       (7U)

+#define SWPMI_IER_TCIE_Msk       (0x1UL << SWPMI_IER_TCIE_Pos)                 /*!< 0x00000080 */

+#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */

+#define SWPMI_IER_SRIE_Pos       (8U)

+#define SWPMI_IER_SRIE_Msk       (0x1UL << SWPMI_IER_SRIE_Pos)                 /*!< 0x00000100 */

+#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */

+#define SWPMI_IER_RDYIE_Pos      (11U)

+#define SWPMI_IER_RDYIE_Msk      (0x1UL << SWPMI_IER_RDYIE_Pos)                /*!< 0x00000800 */

+#define SWPMI_IER_RDYIE          SWPMI_IER_RDYIE_Msk                           /*!<Transceiver ready interrupt enable          */

+

+/*******************  Bit definition for SWPMI_RFL register  ********************/

+#define SWPMI_RFL_RFL_Pos        (0U)

+#define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */

+#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */

+#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */

+

+/*******************  Bit definition for SWPMI_TDR register  ********************/

+#define SWPMI_TDR_TD_Pos         (0U)

+#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)            /*!< 0xFFFFFFFF */

+#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */

+

+/*******************  Bit definition for SWPMI_RDR register  ********************/

+#define SWPMI_RDR_RD_Pos         (0U)

+#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)            /*!< 0xFFFFFFFF */

+#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Recive Data Register           */

+

+

+/*******************  Bit definition for SWPMI_OR register  ********************/

+#define SWPMI_OR_TBYP_Pos        (0U)

+#define SWPMI_OR_TBYP_Msk        (0x1UL << SWPMI_OR_TBYP_Pos)                  /*!< 0x00000001 */

+#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */

+#define SWPMI_OR_CLASS_Pos       (1U)

+#define SWPMI_OR_CLASS_Msk       (0x1UL << SWPMI_OR_CLASS_Pos)                 /*!< 0x00000002 */

+#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP CLASS selection */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            Window WATCHDOG                                 */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for WWDG_CR register  ********************/

+#define WWDG_CR_T_Pos           (0U)

+#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */

+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */

+#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */

+#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */

+#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */

+#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */

+#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */

+#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */

+#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */

+

+#define WWDG_CR_WDGA_Pos        (7U)

+#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */

+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */

+

+/*******************  Bit definition for WWDG_CFR register  *******************/

+#define WWDG_CFR_W_Pos          (0U)

+#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */

+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */

+#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */

+#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */

+#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */

+#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */

+#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */

+#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */

+#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */

+

+#define WWDG_CFR_EWI_Pos        (9U)

+#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */

+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */

+

+#define WWDG_CFR_WDGTB_Pos      (11U)

+#define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */

+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */

+#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000800 */

+#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00001000 */

+#define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00002000 */

+

+/*******************  Bit definition for WWDG_SR register  ********************/

+#define WWDG_SR_EWIF_Pos        (0U)

+#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */

+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                DBG                                         */

+/*                                                                            */

+/******************************************************************************/

+/*********************************  DEVICE ID  ********************************/

+#define STM32H7_DEV_ID           0x450UL

+

+/********************  Bit definition for DBGMCU_IDCODE register  *************/

+#define DBGMCU_IDCODE_DEV_ID_Pos          (0U)

+#define DBGMCU_IDCODE_DEV_ID_Msk          (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */

+#define DBGMCU_IDCODE_DEV_ID              DBGMCU_IDCODE_DEV_ID_Msk

+#define DBGMCU_IDCODE_REV_ID_Pos          (16U)

+#define DBGMCU_IDCODE_REV_ID_Msk          (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */

+#define DBGMCU_IDCODE_REV_ID              DBGMCU_IDCODE_REV_ID_Msk

+

+/********************  Bit definition for DBGMCU_CR register  *****************/

+#define DBGMCU_CR_DBG_SLEEPD1_Pos         (0U)

+#define DBGMCU_CR_DBG_SLEEPD1_Msk         (0x1UL << DBGMCU_CR_DBG_SLEEPD1_Pos) /*!< 0x00000001 */

+#define DBGMCU_CR_DBG_SLEEPD1             DBGMCU_CR_DBG_SLEEPD1_Msk

+#define DBGMCU_CR_DBG_STOPD1_Pos          (1U)

+#define DBGMCU_CR_DBG_STOPD1_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD1_Pos)  /*!< 0x00000002 */

+#define DBGMCU_CR_DBG_STOPD1              DBGMCU_CR_DBG_STOPD1_Msk

+#define DBGMCU_CR_DBG_STANDBYD1_Pos       (2U)

+#define DBGMCU_CR_DBG_STANDBYD1_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos) /*!< 0x00000004 */

+#define DBGMCU_CR_DBG_STANDBYD1           DBGMCU_CR_DBG_STANDBYD1_Msk

+#define DBGMCU_CR_DBG_SLEEPD2_Pos         (3U)

+#define DBGMCU_CR_DBG_SLEEPD2_Msk         (0x1UL << DBGMCU_CR_DBG_SLEEPD2_Pos) /*!< 0x00000008 */

+#define DBGMCU_CR_DBG_SLEEPD2             DBGMCU_CR_DBG_SLEEPD2_Msk

+#define DBGMCU_CR_DBG_STOPD2_Pos          (4U)

+#define DBGMCU_CR_DBG_STOPD2_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD2_Pos)  /*!< 0x00000010 */

+#define DBGMCU_CR_DBG_STOPD2              DBGMCU_CR_DBG_STOPD2_Msk

+#define DBGMCU_CR_DBG_STANDBYD2_Pos       (5U)

+#define DBGMCU_CR_DBG_STANDBYD2_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD2_Pos) /*!< 0x00000020 */

+#define DBGMCU_CR_DBG_STANDBYD2           DBGMCU_CR_DBG_STANDBYD2_Msk

+#define DBGMCU_CR_DBG_STOPD3_Pos          (7U)

+#define DBGMCU_CR_DBG_STOPD3_Msk          (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos)  /*!< 0x00000080 */

+#define DBGMCU_CR_DBG_STOPD3              DBGMCU_CR_DBG_STOPD3_Msk

+#define DBGMCU_CR_DBG_STANDBYD3_Pos       (8U)

+#define DBGMCU_CR_DBG_STANDBYD3_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos) /*!< 0x00000100 */

+#define DBGMCU_CR_DBG_STANDBYD3           DBGMCU_CR_DBG_STANDBYD3_Msk

+#define DBGMCU_CR_DBG_TRACECKEN_Pos       (20U)

+#define DBGMCU_CR_DBG_TRACECKEN_Msk       (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */

+#define DBGMCU_CR_DBG_TRACECKEN           DBGMCU_CR_DBG_TRACECKEN_Msk

+#define DBGMCU_CR_DBG_CKD1EN_Pos          (21U)

+#define DBGMCU_CR_DBG_CKD1EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD1EN_Pos)  /*!< 0x00200000 */

+#define DBGMCU_CR_DBG_CKD1EN              DBGMCU_CR_DBG_CKD1EN_Msk

+#define DBGMCU_CR_DBG_CKD3EN_Pos          (22U)

+#define DBGMCU_CR_DBG_CKD3EN_Msk          (0x1UL << DBGMCU_CR_DBG_CKD3EN_Pos)  /*!< 0x00400000 */

+#define DBGMCU_CR_DBG_CKD3EN              DBGMCU_CR_DBG_CKD3EN_Msk

+#define DBGMCU_CR_DBG_TRGOEN_Pos          (28U)

+#define DBGMCU_CR_DBG_TRGOEN_Msk          (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)  /*!< 0x10000000 */

+#define DBGMCU_CR_DBG_TRGOEN              DBGMCU_CR_DBG_TRGOEN_Msk

+

+/********************  Bit definition for APB3FZ1 register  ************/

+#define DBGMCU_APB3FZ1_DBG_WWDG1_Pos      (6U)

+#define DBGMCU_APB3FZ1_DBG_WWDG1_Msk      (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB3FZ1_DBG_WWDG1          DBGMCU_APB3FZ1_DBG_WWDG1_Msk

+/********************  Bit definition for APB3FZ2 register  ************/

+#define DBGMCU_APB3FZ2_DBG_WWDG1_Pos      (6U)

+#define DBGMCU_APB3FZ2_DBG_WWDG1_Msk      (0x1UL << DBGMCU_APB3FZ2_DBG_WWDG1_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB3FZ2_DBG_WWDG1          DBGMCU_APB3FZ2_DBG_WWDG1_Msk

+/********************  Bit definition for APB1LFZ1 register  ************/

+#define DBGMCU_APB1LFZ1_DBG_TIM2_Pos      (0U)

+#define DBGMCU_APB1LFZ1_DBG_TIM2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB1LFZ1_DBG_TIM2          DBGMCU_APB1LFZ1_DBG_TIM2_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM3_Pos      (1U)

+#define DBGMCU_APB1LFZ1_DBG_TIM3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB1LFZ1_DBG_TIM3          DBGMCU_APB1LFZ1_DBG_TIM3_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM4_Pos      (2U)

+#define DBGMCU_APB1LFZ1_DBG_TIM4_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */

+#define DBGMCU_APB1LFZ1_DBG_TIM4          DBGMCU_APB1LFZ1_DBG_TIM4_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM5_Pos      (3U)

+#define DBGMCU_APB1LFZ1_DBG_TIM5_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */

+#define DBGMCU_APB1LFZ1_DBG_TIM5          DBGMCU_APB1LFZ1_DBG_TIM5_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM6_Pos      (4U)

+#define DBGMCU_APB1LFZ1_DBG_TIM6_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */

+#define DBGMCU_APB1LFZ1_DBG_TIM6          DBGMCU_APB1LFZ1_DBG_TIM6_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM7_Pos      (5U)

+#define DBGMCU_APB1LFZ1_DBG_TIM7_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */

+#define DBGMCU_APB1LFZ1_DBG_TIM7          DBGMCU_APB1LFZ1_DBG_TIM7_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM12_Pos     (6U)

+#define DBGMCU_APB1LFZ1_DBG_TIM12_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB1LFZ1_DBG_TIM12         DBGMCU_APB1LFZ1_DBG_TIM12_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM13_Pos     (7U)

+#define DBGMCU_APB1LFZ1_DBG_TIM13_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB1LFZ1_DBG_TIM13         DBGMCU_APB1LFZ1_DBG_TIM13_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM14_Pos     (8U)

+#define DBGMCU_APB1LFZ1_DBG_TIM14_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */

+#define DBGMCU_APB1LFZ1_DBG_TIM14         DBGMCU_APB1LFZ1_DBG_TIM14_Msk

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos    (9U)

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1        DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk

+#define DBGMCU_APB1LFZ1_DBG_WWDG2_Pos     (11U)

+#define DBGMCU_APB1LFZ1_DBG_WWDG2_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_WWDG2_Pos) /*!< 0x00000800 */

+#define DBGMCU_APB1LFZ1_DBG_WWDG2         DBGMCU_APB1LFZ1_DBG_WWDG2_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C1_Pos      (21U)

+#define DBGMCU_APB1LFZ1_DBG_I2C1_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C1          DBGMCU_APB1LFZ1_DBG_I2C1_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C2_Pos      (22U)

+#define DBGMCU_APB1LFZ1_DBG_I2C2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C2          DBGMCU_APB1LFZ1_DBG_I2C2_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C3_Pos      (23U)

+#define DBGMCU_APB1LFZ1_DBG_I2C3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C3          DBGMCU_APB1LFZ1_DBG_I2C3_Msk

+

+/********************  Bit definition for APB1LFZ2 register  ************/

+#define DBGMCU_APB1LFZ2_DBG_TIM2_Pos      (0U)

+#define DBGMCU_APB1LFZ2_DBG_TIM2_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM2_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB1LFZ2_DBG_TIM2          DBGMCU_APB1LFZ2_DBG_TIM2_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM3_Pos      (1U)

+#define DBGMCU_APB1LFZ2_DBG_TIM3_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM3_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB1LFZ2_DBG_TIM3          DBGMCU_APB1LFZ2_DBG_TIM3_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM4_Pos      (2U)

+#define DBGMCU_APB1LFZ2_DBG_TIM4_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM4_Pos) /*!< 0x00000004 */

+#define DBGMCU_APB1LFZ2_DBG_TIM4          DBGMCU_APB1LFZ2_DBG_TIM4_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM5_Pos      (3U)

+#define DBGMCU_APB1LFZ2_DBG_TIM5_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM5_Pos) /*!< 0x00000008 */

+#define DBGMCU_APB1LFZ2_DBG_TIM5          DBGMCU_APB1LFZ2_DBG_TIM5_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM6_Pos      (4U)

+#define DBGMCU_APB1LFZ2_DBG_TIM6_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM6_Pos) /*!< 0x00000010 */

+#define DBGMCU_APB1LFZ2_DBG_TIM6          DBGMCU_APB1LFZ2_DBG_TIM6_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM7_Pos      (5U)

+#define DBGMCU_APB1LFZ2_DBG_TIM7_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM7_Pos) /*!< 0x00000020 */

+#define DBGMCU_APB1LFZ2_DBG_TIM7          DBGMCU_APB1LFZ2_DBG_TIM7_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM12_Pos     (6U)

+#define DBGMCU_APB1LFZ2_DBG_TIM12_Msk     (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM12_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB1LFZ2_DBG_TIM12         DBGMCU_APB1LFZ2_DBG_TIM12_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM13_Pos     (7U)

+#define DBGMCU_APB1LFZ2_DBG_TIM13_Msk     (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM13_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB1LFZ2_DBG_TIM13         DBGMCU_APB1LFZ2_DBG_TIM13_Msk

+#define DBGMCU_APB1LFZ2_DBG_TIM14_Pos     (8U)

+#define DBGMCU_APB1LFZ2_DBG_TIM14_Msk     (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM14_Pos) /*!< 0x00000100 */

+#define DBGMCU_APB1LFZ2_DBG_TIM14         DBGMCU_APB1LFZ2_DBG_TIM14_Msk

+#define DBGMCU_APB1LFZ2_DBG_LPTIM1_Pos    (9U)

+#define DBGMCU_APB1LFZ2_DBG_LPTIM1_Msk    (0x1UL << DBGMCU_APB1LFZ2_DBG_LPTIM1_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB1LFZ2_DBG_LPTIM1        DBGMCU_APB1LFZ2_DBG_LPTIM1_Msk

+#define DBGMCU_APB1LFZ2_DBG_WWDG2_Pos     (11U)

+#define DBGMCU_APB1LFZ2_DBG_WWDG2_Msk     (0x1UL << DBGMCU_APB1LFZ2_DBG_WWDG2_Pos) /*!< 0x00000800 */

+#define DBGMCU_APB1LFZ2_DBG_WWDG2         DBGMCU_APB1LFZ2_DBG_WWDG2_Msk

+#define DBGMCU_APB1LFZ2_DBG_I2C1_Pos      (21U)

+#define DBGMCU_APB1LFZ2_DBG_I2C1_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C1_Pos) /*!< 0x00200000 */

+#define DBGMCU_APB1LFZ2_DBG_I2C1          DBGMCU_APB1LFZ2_DBG_I2C1_Msk

+#define DBGMCU_APB1LFZ2_DBG_I2C2_Pos      (22U)

+#define DBGMCU_APB1LFZ2_DBG_I2C2_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C2_Pos) /*!< 0x00400000 */

+#define DBGMCU_APB1LFZ2_DBG_I2C2          DBGMCU_APB1LFZ2_DBG_I2C2_Msk

+#define DBGMCU_APB1LFZ2_DBG_I2C3_Pos      (23U)

+#define DBGMCU_APB1LFZ2_DBG_I2C3_Msk      (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C3_Pos) /*!< 0x00800000 */

+#define DBGMCU_APB1LFZ2_DBG_I2C3          DBGMCU_APB1LFZ2_DBG_I2C3_Msk

+/********************  Bit definition for APB1HFZ1 register  ************/

+#define DBGMCU_APB1HFZ1_DBG_FDCAN_Pos     (8U)

+#define DBGMCU_APB1HFZ1_DBG_FDCAN_Msk     (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_Pos) /*!< 0x00000100 */

+#define DBGMCU_APB1HFZ1_DBG_FDCAN         DBGMCU_APB1HFZ1_DBG_FDCAN_Msk

+/********************  Bit definition for APB1HFZ2 register  ************/

+#define DBGMCU_APB1HFZ2_DBG_FDCAN_Pos     (8U)

+#define DBGMCU_APB1HFZ2_DBG_FDCAN_Msk     (0x1UL << DBGMCU_APB1HFZ2_DBG_FDCAN_Pos) /*!< 0x00000100 */

+#define DBGMCU_APB1HFZ2_DBG_FDCAN         DBGMCU_APB1HFZ2_DBG_FDCAN_Msk

+

+/********************  Bit definition for APB2FZ1 register  ************/

+#define DBGMCU_APB2FZ1_DBG_TIM1_Pos       (0U)

+#define DBGMCU_APB2FZ1_DBG_TIM1_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB2FZ1_DBG_TIM1           DBGMCU_APB2FZ1_DBG_TIM1_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM8_Pos       (1U)

+#define DBGMCU_APB2FZ1_DBG_TIM8_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB2FZ1_DBG_TIM8           DBGMCU_APB2FZ1_DBG_TIM8_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM15_Pos      (16U)

+#define DBGMCU_APB2FZ1_DBG_TIM15_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB2FZ1_DBG_TIM15          DBGMCU_APB2FZ1_DBG_TIM15_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM16_Pos      (17U)

+#define DBGMCU_APB2FZ1_DBG_TIM16_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */

+#define DBGMCU_APB2FZ1_DBG_TIM16          DBGMCU_APB2FZ1_DBG_TIM16_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM17_Pos      (18U)

+#define DBGMCU_APB2FZ1_DBG_TIM17_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB2FZ1_DBG_TIM17          DBGMCU_APB2FZ1_DBG_TIM17_Msk

+#define DBGMCU_APB2FZ1_DBG_HRTIM_Pos      (29U)

+#define DBGMCU_APB2FZ1_DBG_HRTIM_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_HRTIM_Pos) /*!< 0x20000000 */

+#define DBGMCU_APB2FZ1_DBG_HRTIM          DBGMCU_APB2FZ1_DBG_HRTIM_Msk

+

+/********************  Bit definition for APB2FZ2 register  ************/

+#define DBGMCU_APB2FZ2_DBG_TIM1_Pos       (0U)

+#define DBGMCU_APB2FZ2_DBG_TIM1_Msk       (0x1UL << DBGMCU_APB2FZ2_DBG_TIM1_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB2FZ2_DBG_TIM1           DBGMCU_APB2FZ2_DBG_TIM1_Msk

+#define DBGMCU_APB2FZ2_DBG_TIM8_Pos       (1U)

+#define DBGMCU_APB2FZ2_DBG_TIM8_Msk       (0x1UL << DBGMCU_APB2FZ2_DBG_TIM8_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB2FZ2_DBG_TIM8           DBGMCU_APB2FZ2_DBG_TIM8_Msk

+#define DBGMCU_APB2FZ2_DBG_TIM15_Pos      (16U)

+#define DBGMCU_APB2FZ2_DBG_TIM15_Msk      (0x1UL << DBGMCU_APB2FZ2_DBG_TIM15_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB2FZ2_DBG_TIM15          DBGMCU_APB2FZ2_DBG_TIM15_Msk

+#define DBGMCU_APB2FZ2_DBG_TIM16_Pos      (17U)

+#define DBGMCU_APB2FZ2_DBG_TIM16_Msk      (0x1UL << DBGMCU_APB2FZ2_DBG_TIM16_Pos) /*!< 0x00020000 */

+#define DBGMCU_APB2FZ2_DBG_TIM16          DBGMCU_APB2FZ2_DBG_TIM16_Msk

+#define DBGMCU_APB2FZ2_DBG_TIM17_Pos      (18U)

+#define DBGMCU_APB2FZ2_DBG_TIM17_Msk      (0x1UL << DBGMCU_APB2FZ2_DBG_TIM17_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB2FZ2_DBG_TIM17          DBGMCU_APB2FZ2_DBG_TIM17_Msk

+#define DBGMCU_APB2FZ2_DBG_HRTIM_Pos      (29U)

+#define DBGMCU_APB2FZ2_DBG_HRTIM_Msk      (0x1UL << DBGMCU_APB2FZ2_DBG_HRTIM_Pos) /*!< 0x20000000 */

+#define DBGMCU_APB2FZ2_DBG_HRTIM          DBGMCU_APB2FZ2_DBG_HRTIM_Msk

+/********************  Bit definition for APB4FZ1 register  ************/

+#define DBGMCU_APB4FZ1_DBG_I2C4_Pos       (7U)

+#define DBGMCU_APB4FZ1_DBG_I2C4_Msk       (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB4FZ1_DBG_I2C4           DBGMCU_APB4FZ1_DBG_I2C4_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos     (9U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM2         DBGMCU_APB4FZ1_DBG_LPTIM2_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos     (10U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM3         DBGMCU_APB4FZ1_DBG_LPTIM3_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM4_Pos     (11U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM4_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos) /*!< 0x00000800 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM4         DBGMCU_APB4FZ1_DBG_LPTIM4_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM5_Pos     (12U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM5_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos) /*!< 0x00001000 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM5         DBGMCU_APB4FZ1_DBG_LPTIM5_Msk

+#define DBGMCU_APB4FZ1_DBG_RTC_Pos        (16U)

+#define DBGMCU_APB4FZ1_DBG_RTC_Msk        (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB4FZ1_DBG_RTC            DBGMCU_APB4FZ1_DBG_RTC_Msk

+#define DBGMCU_APB4FZ1_DBG_IWDG1_Pos      (18U)

+#define DBGMCU_APB4FZ1_DBG_IWDG1_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB4FZ1_DBG_IWDG1          DBGMCU_APB4FZ1_DBG_IWDG1_Msk

+#define DBGMCU_APB4FZ1_DBG_IWDG2_Pos      (19U)

+#define DBGMCU_APB4FZ1_DBG_IWDG2_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG2_Pos) /*!< 0x00080000 */

+#define DBGMCU_APB4FZ1_DBG_IWDG2          DBGMCU_APB4FZ1_DBG_IWDG2_Msk

+/********************  Bit definition for APB4FZ2 register  ************/

+#define DBGMCU_APB4FZ2_DBG_I2C4_Pos       (7U)

+#define DBGMCU_APB4FZ2_DBG_I2C4_Msk       (0x1UL << DBGMCU_APB4FZ2_DBG_I2C4_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB4FZ2_DBG_I2C4           DBGMCU_APB4FZ2_DBG_I2C4_Msk

+#define DBGMCU_APB4FZ2_DBG_LPTIM2_Pos     (9U)

+#define DBGMCU_APB4FZ2_DBG_LPTIM2_Msk     (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM2_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB4FZ2_DBG_LPTIM2         DBGMCU_APB4FZ2_DBG_LPTIM2_Msk

+#define DBGMCU_APB4FZ2_DBG_LPTIM3_Pos     (10U)

+#define DBGMCU_APB4FZ2_DBG_LPTIM3_Msk     (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM3_Pos) /*!< 0x00000400 */

+#define DBGMCU_APB4FZ2_DBG_LPTIM3         DBGMCU_APB4FZ2_DBG_LPTIM3_Msk

+#define DBGMCU_APB4FZ2_DBG_LPTIM4_Pos     (11U)

+#define DBGMCU_APB4FZ2_DBG_LPTIM4_Msk     (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM4_Pos) /*!< 0x00000800 */

+#define DBGMCU_APB4FZ2_DBG_LPTIM4         DBGMCU_APB4FZ2_DBG_LPTIM4_Msk

+#define DBGMCU_APB4FZ2_DBG_LPTIM5_Pos     (12U)

+#define DBGMCU_APB4FZ2_DBG_LPTIM5_Msk     (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM5_Pos) /*!< 0x00001000 */

+#define DBGMCU_APB4FZ2_DBG_LPTIM5         DBGMCU_APB4FZ2_DBG_LPTIM5_Msk

+#define DBGMCU_APB4FZ2_DBG_RTC_Pos        (16U)

+#define DBGMCU_APB4FZ2_DBG_RTC_Msk        (0x1UL << DBGMCU_APB4FZ2_DBG_RTC_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB4FZ2_DBG_RTC            DBGMCU_APB4FZ2_DBG_RTC_Msk

+#define DBGMCU_APB4FZ2_DBG_IWDG1_Pos      (18U)

+#define DBGMCU_APB4FZ2_DBG_IWDG1_Msk      (0x1UL << DBGMCU_APB4FZ2_DBG_IWDG1_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB4FZ2_DBG_IWDG1          DBGMCU_APB4FZ2_DBG_IWDG1_Msk

+#define DBGMCU_APB4FZ2_DBG_IWDG2_Pos      (19U)

+#define DBGMCU_APB4FZ2_DBG_IWDG2_Msk      (0x1UL << DBGMCU_APB4FZ2_DBG_IWDG2_Pos) /*!< 0x00080000 */

+#define DBGMCU_APB4FZ2_DBG_IWDG2          DBGMCU_APB4FZ2_DBG_IWDG2_Msk

+/******************************************************************************/

+/*                                                                            */

+/*                        High Resolution Timer (HRTIM)                       */

+/*                                                                            */

+/******************************************************************************/

+/******************** Master Timer control register ***************************/

+#define HRTIM_MCR_CK_PSC_Pos          (0U)

+#define HRTIM_MCR_CK_PSC_Msk          (0x7UL << HRTIM_MCR_CK_PSC_Pos)          /*!< 0x00000007 */

+#define HRTIM_MCR_CK_PSC              HRTIM_MCR_CK_PSC_Msk                     /*!< Prescaler mask */

+#define HRTIM_MCR_CK_PSC_0            (0x1UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000001 */

+#define HRTIM_MCR_CK_PSC_1            (0x2UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000002 */

+#define HRTIM_MCR_CK_PSC_2            (0x4UL << HRTIM_MCR_CK_PSC_Pos)           /*!< 0x00000004 */

+

+#define HRTIM_MCR_CONT_Pos            (3U)

+#define HRTIM_MCR_CONT_Msk            (0x1UL << HRTIM_MCR_CONT_Pos)            /*!< 0x00000008 */

+#define HRTIM_MCR_CONT                HRTIM_MCR_CONT_Msk                       /*!< Continuous mode */

+#define HRTIM_MCR_RETRIG_Pos          (4U)

+#define HRTIM_MCR_RETRIG_Msk          (0x1UL << HRTIM_MCR_RETRIG_Pos)          /*!< 0x00000010 */

+#define HRTIM_MCR_RETRIG              HRTIM_MCR_RETRIG_Msk                     /*!< Rettrigreable mode */

+#define HRTIM_MCR_HALF_Pos            (5U)

+#define HRTIM_MCR_HALF_Msk            (0x1UL << HRTIM_MCR_HALF_Pos)            /*!< 0x00000020 */

+#define HRTIM_MCR_HALF                HRTIM_MCR_HALF_Msk                       /*!< Half mode */

+

+#define HRTIM_MCR_SYNC_IN_Pos         (8U)

+#define HRTIM_MCR_SYNC_IN_Msk         (0x3UL << HRTIM_MCR_SYNC_IN_Pos)         /*!< 0x00000300 */

+#define HRTIM_MCR_SYNC_IN             HRTIM_MCR_SYNC_IN_Msk                    /*!< Synchronization input master */

+#define HRTIM_MCR_SYNC_IN_0           (0x1UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000100 */

+#define HRTIM_MCR_SYNC_IN_1           (0x2UL << HRTIM_MCR_SYNC_IN_Pos)          /*!< 0x00000200 */

+#define HRTIM_MCR_SYNCRSTM_Pos        (10U)

+#define HRTIM_MCR_SYNCRSTM_Msk        (0x1UL << HRTIM_MCR_SYNCRSTM_Pos)        /*!< 0x00000400 */

+#define HRTIM_MCR_SYNCRSTM            HRTIM_MCR_SYNCRSTM_Msk                   /*!< Synchronization reset master */

+#define HRTIM_MCR_SYNCSTRTM_Pos       (11U)

+#define HRTIM_MCR_SYNCSTRTM_Msk       (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos)       /*!< 0x00000800 */

+#define HRTIM_MCR_SYNCSTRTM           HRTIM_MCR_SYNCSTRTM_Msk                  /*!< Synchronization start master */

+#define HRTIM_MCR_SYNC_OUT_Pos        (12U)

+#define HRTIM_MCR_SYNC_OUT_Msk        (0x3UL << HRTIM_MCR_SYNC_OUT_Pos)        /*!< 0x00003000 */

+#define HRTIM_MCR_SYNC_OUT            HRTIM_MCR_SYNC_OUT_Msk                   /*!< Synchronization output master */

+#define HRTIM_MCR_SYNC_OUT_0          (0x1UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00001000 */

+#define HRTIM_MCR_SYNC_OUT_1          (0x2UL << HRTIM_MCR_SYNC_OUT_Pos)         /*!< 0x00002000 */

+#define HRTIM_MCR_SYNC_SRC_Pos        (14U)

+#define HRTIM_MCR_SYNC_SRC_Msk        (0x3UL << HRTIM_MCR_SYNC_SRC_Pos)        /*!< 0x0000C000 */

+#define HRTIM_MCR_SYNC_SRC            HRTIM_MCR_SYNC_SRC_Msk                   /*!< Synchronization source */

+#define HRTIM_MCR_SYNC_SRC_0          (0x1UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00004000 */

+#define HRTIM_MCR_SYNC_SRC_1          (0x2UL << HRTIM_MCR_SYNC_SRC_Pos)         /*!< 0x00008000 */

+

+#define HRTIM_MCR_MCEN_Pos            (16U)

+#define HRTIM_MCR_MCEN_Msk            (0x1UL << HRTIM_MCR_MCEN_Pos)            /*!< 0x00010000 */

+#define HRTIM_MCR_MCEN                HRTIM_MCR_MCEN_Msk                       /*!< Master counter enable */

+#define HRTIM_MCR_TACEN_Pos           (17U)

+#define HRTIM_MCR_TACEN_Msk           (0x1UL << HRTIM_MCR_TACEN_Pos)           /*!< 0x00020000 */

+#define HRTIM_MCR_TACEN               HRTIM_MCR_TACEN_Msk                      /*!< Timer A counter enable */

+#define HRTIM_MCR_TBCEN_Pos           (18U)

+#define HRTIM_MCR_TBCEN_Msk           (0x1UL << HRTIM_MCR_TBCEN_Pos)           /*!< 0x00040000 */

+#define HRTIM_MCR_TBCEN               HRTIM_MCR_TBCEN_Msk                      /*!< Timer B counter enable */

+#define HRTIM_MCR_TCCEN_Pos           (19U)

+#define HRTIM_MCR_TCCEN_Msk           (0x1UL << HRTIM_MCR_TCCEN_Pos)           /*!< 0x00080000 */

+#define HRTIM_MCR_TCCEN               HRTIM_MCR_TCCEN_Msk                      /*!< Timer C counter enable */

+#define HRTIM_MCR_TDCEN_Pos           (20U)

+#define HRTIM_MCR_TDCEN_Msk           (0x1UL << HRTIM_MCR_TDCEN_Pos)           /*!< 0x00100000 */

+#define HRTIM_MCR_TDCEN               HRTIM_MCR_TDCEN_Msk                      /*!< Timer D counter enable */

+#define HRTIM_MCR_TECEN_Pos           (21U)

+#define HRTIM_MCR_TECEN_Msk           (0x1UL << HRTIM_MCR_TECEN_Pos)           /*!< 0x00200000 */

+#define HRTIM_MCR_TECEN               HRTIM_MCR_TECEN_Msk                      /*!< Timer E counter enable */

+

+#define HRTIM_MCR_DACSYNC_Pos         (25U)

+#define HRTIM_MCR_DACSYNC_Msk         (0x3UL << HRTIM_MCR_DACSYNC_Pos)         /*!< 0x06000000 */

+#define HRTIM_MCR_DACSYNC             HRTIM_MCR_DACSYNC_Msk                    /*!< DAC sychronization mask */

+#define HRTIM_MCR_DACSYNC_0           (0x1UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x02000000 */

+#define HRTIM_MCR_DACSYNC_1           (0x2UL << HRTIM_MCR_DACSYNC_Pos)          /*!< 0x04000000 */

+

+#define HRTIM_MCR_PREEN_Pos           (27U)

+#define HRTIM_MCR_PREEN_Msk           (0x1UL << HRTIM_MCR_PREEN_Pos)           /*!< 0x08000000 */

+#define HRTIM_MCR_PREEN               HRTIM_MCR_PREEN_Msk                      /*!< Master preload enable */

+#define HRTIM_MCR_MREPU_Pos           (29U)

+#define HRTIM_MCR_MREPU_Msk           (0x1UL << HRTIM_MCR_MREPU_Pos)           /*!< 0x20000000 */

+#define HRTIM_MCR_MREPU               HRTIM_MCR_MREPU_Msk                      /*!< Master repetition update */

+

+#define HRTIM_MCR_BRSTDMA_Pos         (30U)

+#define HRTIM_MCR_BRSTDMA_Msk         (0x3UL << HRTIM_MCR_BRSTDMA_Pos)         /*!< 0xC0000000 */

+#define HRTIM_MCR_BRSTDMA             HRTIM_MCR_BRSTDMA_Msk                    /*!< Burst DMA update */

+#define HRTIM_MCR_BRSTDMA_0           (0x1UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x40000000 */

+#define HRTIM_MCR_BRSTDMA_1           (0x2UL << HRTIM_MCR_BRSTDMA_Pos)          /*!< 0x80000000 */

+

+/******************** Master Timer Interrupt status register ******************/

+#define HRTIM_MISR_MCMP1_Pos          (0U)

+#define HRTIM_MISR_MCMP1_Msk          (0x1UL << HRTIM_MISR_MCMP1_Pos)          /*!< 0x00000001 */

+#define HRTIM_MISR_MCMP1              HRTIM_MISR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag */

+#define HRTIM_MISR_MCMP2_Pos          (1U)

+#define HRTIM_MISR_MCMP2_Msk          (0x1UL << HRTIM_MISR_MCMP2_Pos)          /*!< 0x00000002 */

+#define HRTIM_MISR_MCMP2              HRTIM_MISR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag */

+#define HRTIM_MISR_MCMP3_Pos          (2U)

+#define HRTIM_MISR_MCMP3_Msk          (0x1UL << HRTIM_MISR_MCMP3_Pos)          /*!< 0x00000004 */

+#define HRTIM_MISR_MCMP3              HRTIM_MISR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag */

+#define HRTIM_MISR_MCMP4_Pos          (3U)

+#define HRTIM_MISR_MCMP4_Msk          (0x1UL << HRTIM_MISR_MCMP4_Pos)          /*!< 0x00000008 */

+#define HRTIM_MISR_MCMP4              HRTIM_MISR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag */

+#define HRTIM_MISR_MREP_Pos           (4U)

+#define HRTIM_MISR_MREP_Msk           (0x1UL << HRTIM_MISR_MREP_Pos)           /*!< 0x00000010 */

+#define HRTIM_MISR_MREP               HRTIM_MISR_MREP_Msk                      /*!< Master Repetition interrupt flag */

+#define HRTIM_MISR_SYNC_Pos           (5U)

+#define HRTIM_MISR_SYNC_Msk           (0x1UL << HRTIM_MISR_SYNC_Pos)           /*!< 0x00000020 */

+#define HRTIM_MISR_SYNC               HRTIM_MISR_SYNC_Msk                      /*!< Synchronization input interrupt flag */

+#define HRTIM_MISR_MUPD_Pos           (6U)

+#define HRTIM_MISR_MUPD_Msk           (0x1UL << HRTIM_MISR_MUPD_Pos)           /*!< 0x00000040 */

+#define HRTIM_MISR_MUPD               HRTIM_MISR_MUPD_Msk                      /*!< Master update interrupt flag */

+

+/******************** Master Timer Interrupt clear register *******************/

+#define HRTIM_MICR_MCMP1_Pos          (0U)

+#define HRTIM_MICR_MCMP1_Msk          (0x1UL << HRTIM_MICR_MCMP1_Pos)          /*!< 0x00000001 */

+#define HRTIM_MICR_MCMP1              HRTIM_MICR_MCMP1_Msk                     /*!< Master compare 1 interrupt flag clear */

+#define HRTIM_MICR_MCMP2_Pos          (1U)

+#define HRTIM_MICR_MCMP2_Msk          (0x1UL << HRTIM_MICR_MCMP2_Pos)          /*!< 0x00000002 */

+#define HRTIM_MICR_MCMP2              HRTIM_MICR_MCMP2_Msk                     /*!< Master compare 2 interrupt flag clear */

+#define HRTIM_MICR_MCMP3_Pos          (2U)

+#define HRTIM_MICR_MCMP3_Msk          (0x1UL << HRTIM_MICR_MCMP3_Pos)          /*!< 0x00000004 */

+#define HRTIM_MICR_MCMP3              HRTIM_MICR_MCMP3_Msk                     /*!< Master compare 3 interrupt flag clear */

+#define HRTIM_MICR_MCMP4_Pos          (3U)

+#define HRTIM_MICR_MCMP4_Msk          (0x1UL << HRTIM_MICR_MCMP4_Pos)          /*!< 0x00000008 */

+#define HRTIM_MICR_MCMP4              HRTIM_MICR_MCMP4_Msk                     /*!< Master compare 4 interrupt flag clear */

+#define HRTIM_MICR_MREP_Pos           (4U)

+#define HRTIM_MICR_MREP_Msk           (0x1UL << HRTIM_MICR_MREP_Pos)           /*!< 0x00000010 */

+#define HRTIM_MICR_MREP               HRTIM_MICR_MREP_Msk                      /*!< Master Repetition interrupt flag clear */

+#define HRTIM_MICR_SYNC_Pos           (5U)

+#define HRTIM_MICR_SYNC_Msk           (0x1UL << HRTIM_MICR_SYNC_Pos)           /*!< 0x00000020 */

+#define HRTIM_MICR_SYNC               HRTIM_MICR_SYNC_Msk                      /*!< Synchronization input interrupt flag clear */

+#define HRTIM_MICR_MUPD_Pos           (6U)

+#define HRTIM_MICR_MUPD_Msk           (0x1UL << HRTIM_MICR_MUPD_Pos)           /*!< 0x00000040 */

+#define HRTIM_MICR_MUPD               HRTIM_MICR_MUPD_Msk                      /*!< Master update interrupt flag clear */

+

+/******************** Master Timer DMA/Interrupt enable register **************/

+#define HRTIM_MDIER_MCMP1IE_Pos       (0U)

+#define HRTIM_MDIER_MCMP1IE_Msk       (0x1UL << HRTIM_MDIER_MCMP1IE_Pos)       /*!< 0x00000001 */

+#define HRTIM_MDIER_MCMP1IE           HRTIM_MDIER_MCMP1IE_Msk                  /*!< Master compare 1 interrupt enable */

+#define HRTIM_MDIER_MCMP2IE_Pos       (1U)

+#define HRTIM_MDIER_MCMP2IE_Msk       (0x1UL << HRTIM_MDIER_MCMP2IE_Pos)       /*!< 0x00000002 */

+#define HRTIM_MDIER_MCMP2IE           HRTIM_MDIER_MCMP2IE_Msk                  /*!< Master compare 2 interrupt enable */

+#define HRTIM_MDIER_MCMP3IE_Pos       (2U)

+#define HRTIM_MDIER_MCMP3IE_Msk       (0x1UL << HRTIM_MDIER_MCMP3IE_Pos)       /*!< 0x00000004 */

+#define HRTIM_MDIER_MCMP3IE           HRTIM_MDIER_MCMP3IE_Msk                  /*!< Master compare 3 interrupt enable */

+#define HRTIM_MDIER_MCMP4IE_Pos       (3U)

+#define HRTIM_MDIER_MCMP4IE_Msk       (0x1UL << HRTIM_MDIER_MCMP4IE_Pos)       /*!< 0x00000008 */

+#define HRTIM_MDIER_MCMP4IE           HRTIM_MDIER_MCMP4IE_Msk                  /*!< Master compare 4 interrupt enable */

+#define HRTIM_MDIER_MREPIE_Pos        (4U)

+#define HRTIM_MDIER_MREPIE_Msk        (0x1UL << HRTIM_MDIER_MREPIE_Pos)        /*!< 0x00000010 */

+#define HRTIM_MDIER_MREPIE            HRTIM_MDIER_MREPIE_Msk                   /*!< Master Repetition interrupt enable */

+#define HRTIM_MDIER_SYNCIE_Pos        (5U)

+#define HRTIM_MDIER_SYNCIE_Msk        (0x1UL << HRTIM_MDIER_SYNCIE_Pos)        /*!< 0x00000020 */

+#define HRTIM_MDIER_SYNCIE            HRTIM_MDIER_SYNCIE_Msk                   /*!< Synchronization input interrupt enable */

+#define HRTIM_MDIER_MUPDIE_Pos        (6U)

+#define HRTIM_MDIER_MUPDIE_Msk        (0x1UL << HRTIM_MDIER_MUPDIE_Pos)        /*!< 0x00000040 */

+#define HRTIM_MDIER_MUPDIE            HRTIM_MDIER_MUPDIE_Msk                   /*!< Master update interrupt enable */

+

+#define HRTIM_MDIER_MCMP1DE_Pos       (16U)

+#define HRTIM_MDIER_MCMP1DE_Msk       (0x1UL << HRTIM_MDIER_MCMP1DE_Pos)       /*!< 0x00010000 */

+#define HRTIM_MDIER_MCMP1DE           HRTIM_MDIER_MCMP1DE_Msk                  /*!< Master compare 1 DMA enable */

+#define HRTIM_MDIER_MCMP2DE_Pos       (17U)

+#define HRTIM_MDIER_MCMP2DE_Msk       (0x1UL << HRTIM_MDIER_MCMP2DE_Pos)       /*!< 0x00020000 */

+#define HRTIM_MDIER_MCMP2DE           HRTIM_MDIER_MCMP2DE_Msk                  /*!< Master compare 2 DMA enable */

+#define HRTIM_MDIER_MCMP3DE_Pos       (18U)

+#define HRTIM_MDIER_MCMP3DE_Msk       (0x1UL << HRTIM_MDIER_MCMP3DE_Pos)       /*!< 0x00040000 */

+#define HRTIM_MDIER_MCMP3DE           HRTIM_MDIER_MCMP3DE_Msk                  /*!< Master compare 3 DMA enable */

+#define HRTIM_MDIER_MCMP4DE_Pos       (19U)

+#define HRTIM_MDIER_MCMP4DE_Msk       (0x1UL << HRTIM_MDIER_MCMP4DE_Pos)       /*!< 0x00080000 */

+#define HRTIM_MDIER_MCMP4DE           HRTIM_MDIER_MCMP4DE_Msk                  /*!< Master compare 4 DMA enable */

+#define HRTIM_MDIER_MREPDE_Pos        (20U)

+#define HRTIM_MDIER_MREPDE_Msk        (0x1UL << HRTIM_MDIER_MREPDE_Pos)        /*!< 0x00100000 */

+#define HRTIM_MDIER_MREPDE            HRTIM_MDIER_MREPDE_Msk                   /*!< Master Repetition DMA enable */

+#define HRTIM_MDIER_SYNCDE_Pos        (21U)

+#define HRTIM_MDIER_SYNCDE_Msk        (0x1UL << HRTIM_MDIER_SYNCDE_Pos)        /*!< 0x00200000 */

+#define HRTIM_MDIER_SYNCDE            HRTIM_MDIER_SYNCDE_Msk                   /*!< Synchronization input DMA enable */

+#define HRTIM_MDIER_MUPDDE_Pos        (22U)

+#define HRTIM_MDIER_MUPDDE_Msk        (0x1UL << HRTIM_MDIER_MUPDDE_Pos)        /*!< 0x00400000 */

+#define HRTIM_MDIER_MUPDDE            HRTIM_MDIER_MUPDDE_Msk                   /*!< Master update DMA enable */

+

+/*******************  Bit definition for HRTIM_MCNTR register  ****************/

+#define HRTIM_MCNTR_MCNTR_Pos         (0U)

+#define HRTIM_MCNTR_MCNTR_Msk         (0xFFFFUL << HRTIM_MCNTR_MCNTR_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_MCNTR_MCNTR             HRTIM_MCNTR_MCNTR_Msk                    /*!<Counter Value */

+

+/*******************  Bit definition for HRTIM_MPER register  *****************/

+#define HRTIM_MPER_MPER_Pos           (0U)

+#define HRTIM_MPER_MPER_Msk           (0xFFFFUL << HRTIM_MPER_MPER_Pos)        /*!< 0x0000FFFF */

+#define HRTIM_MPER_MPER               HRTIM_MPER_MPER_Msk                      /*!< Period Value */

+

+/*******************  Bit definition for HRTIM_MREP register  *****************/

+#define HRTIM_MREP_MREP_Pos           (0U)

+#define HRTIM_MREP_MREP_Msk           (0xFFUL << HRTIM_MREP_MREP_Pos)          /*!< 0x000000FF */

+#define HRTIM_MREP_MREP               HRTIM_MREP_MREP_Msk                      /*!<Repetition Value */

+

+/*******************  Bit definition for HRTIM_MCMP1R register  *****************/

+#define HRTIM_MCMP1R_MCMP1R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP1R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP1R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP1R           HRTIM_MCMP1R_MCMP1R_Msk                  /*!<Compare Value */

+

+/*******************  Bit definition for HRTIM_MCMP2R register  *****************/

+#define HRTIM_MCMP1R_MCMP2R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP2R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP2R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP2R           HRTIM_MCMP1R_MCMP2R_Msk                  /*!<Compare Value */

+

+/*******************  Bit definition for HRTIM_MCMP3R register  *****************/

+#define HRTIM_MCMP1R_MCMP3R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP3R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP3R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP3R           HRTIM_MCMP1R_MCMP3R_Msk                  /*!<Compare Value */

+

+/*******************  Bit definition for HRTIM_MCMP4R register  *****************/

+#define HRTIM_MCMP1R_MCMP4R_Pos       (0U)

+#define HRTIM_MCMP1R_MCMP4R_Msk       (0xFFFFUL << HRTIM_MCMP1R_MCMP4R_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_MCMP1R_MCMP4R           HRTIM_MCMP1R_MCMP4R_Msk                  /*!<Compare Value */

+

+/******************** Slave control register **********************************/

+#define HRTIM_TIMCR_CK_PSC_Pos        (0U)

+#define HRTIM_TIMCR_CK_PSC_Msk        (0x7UL << HRTIM_TIMCR_CK_PSC_Pos)        /*!< 0x00000007 */

+#define HRTIM_TIMCR_CK_PSC            HRTIM_TIMCR_CK_PSC_Msk                   /*!< Slave prescaler mask*/

+#define HRTIM_TIMCR_CK_PSC_0          (0x1UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000001 */

+#define HRTIM_TIMCR_CK_PSC_1          (0x2UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000002 */

+#define HRTIM_TIMCR_CK_PSC_2          (0x4UL << HRTIM_TIMCR_CK_PSC_Pos)         /*!< 0x00000004 */

+

+#define HRTIM_TIMCR_CONT_Pos          (3U)

+#define HRTIM_TIMCR_CONT_Msk          (0x1UL << HRTIM_TIMCR_CONT_Pos)          /*!< 0x00000008 */

+#define HRTIM_TIMCR_CONT              HRTIM_TIMCR_CONT_Msk                     /*!< Slave continuous mode */

+#define HRTIM_TIMCR_RETRIG_Pos        (4U)

+#define HRTIM_TIMCR_RETRIG_Msk        (0x1UL << HRTIM_TIMCR_RETRIG_Pos)        /*!< 0x00000010 */

+#define HRTIM_TIMCR_RETRIG            HRTIM_TIMCR_RETRIG_Msk                   /*!< Slave Retrigreable mode */

+#define HRTIM_TIMCR_HALF_Pos          (5U)

+#define HRTIM_TIMCR_HALF_Msk          (0x1UL << HRTIM_TIMCR_HALF_Pos)          /*!< 0x00000020 */

+#define HRTIM_TIMCR_HALF              HRTIM_TIMCR_HALF_Msk                     /*!< Slave Half mode */

+#define HRTIM_TIMCR_PSHPLL_Pos        (6U)

+#define HRTIM_TIMCR_PSHPLL_Msk        (0x1UL << HRTIM_TIMCR_PSHPLL_Pos)        /*!< 0x00000040 */

+#define HRTIM_TIMCR_PSHPLL            HRTIM_TIMCR_PSHPLL_Msk                   /*!< Slave push-pull mode */

+

+#define HRTIM_TIMCR_SYNCRST_Pos       (10U)

+#define HRTIM_TIMCR_SYNCRST_Msk       (0x1UL << HRTIM_TIMCR_SYNCRST_Pos)       /*!< 0x00000400 */

+#define HRTIM_TIMCR_SYNCRST           HRTIM_TIMCR_SYNCRST_Msk                  /*!< Slave synchronization resets */

+#define HRTIM_TIMCR_SYNCSTRT_Pos      (11U)

+#define HRTIM_TIMCR_SYNCSTRT_Msk      (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos)      /*!< 0x00000800 */

+#define HRTIM_TIMCR_SYNCSTRT          HRTIM_TIMCR_SYNCSTRT_Msk                 /*!< Slave synchronization starts */

+

+#define HRTIM_TIMCR_DELCMP2_Pos       (12U)

+#define HRTIM_TIMCR_DELCMP2_Msk       (0x3UL << HRTIM_TIMCR_DELCMP2_Pos)       /*!< 0x00003000 */

+#define HRTIM_TIMCR_DELCMP2           HRTIM_TIMCR_DELCMP2_Msk                  /*!< Slave delayed compartor 2 mode mask */

+#define HRTIM_TIMCR_DELCMP2_0         (0x1UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00001000 */

+#define HRTIM_TIMCR_DELCMP2_1         (0x2UL << HRTIM_TIMCR_DELCMP2_Pos)        /*!< 0x00002000 */

+#define HRTIM_TIMCR_DELCMP4_Pos       (14U)

+#define HRTIM_TIMCR_DELCMP4_Msk       (0x3UL << HRTIM_TIMCR_DELCMP4_Pos)       /*!< 0x0000C000 */

+#define HRTIM_TIMCR_DELCMP4           HRTIM_TIMCR_DELCMP4_Msk                  /*!< Slave delayed compartor 4 mode mask */

+#define HRTIM_TIMCR_DELCMP4_0         (0x1UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00004000 */

+#define HRTIM_TIMCR_DELCMP4_1         (0x2UL << HRTIM_TIMCR_DELCMP4_Pos)        /*!< 0x00008000 */

+

+#define HRTIM_TIMCR_TREPU_Pos         (17U)

+#define HRTIM_TIMCR_TREPU_Msk         (0x1UL << HRTIM_TIMCR_TREPU_Pos)         /*!< 0x00020000 */

+#define HRTIM_TIMCR_TREPU             HRTIM_TIMCR_TREPU_Msk                    /*!< Slave repetition update */

+#define HRTIM_TIMCR_TRSTU_Pos         (18U)

+#define HRTIM_TIMCR_TRSTU_Msk         (0x1UL << HRTIM_TIMCR_TRSTU_Pos)         /*!< 0x00040000 */

+#define HRTIM_TIMCR_TRSTU             HRTIM_TIMCR_TRSTU_Msk                    /*!< Slave reset update */

+#define HRTIM_TIMCR_TAU_Pos           (19U)

+#define HRTIM_TIMCR_TAU_Msk           (0x1UL << HRTIM_TIMCR_TAU_Pos)           /*!< 0x00080000 */

+#define HRTIM_TIMCR_TAU               HRTIM_TIMCR_TAU_Msk                      /*!< Slave Timer A update reserved for TIM A */

+#define HRTIM_TIMCR_TBU_Pos           (20U)

+#define HRTIM_TIMCR_TBU_Msk           (0x1UL << HRTIM_TIMCR_TBU_Pos)           /*!< 0x00100000 */

+#define HRTIM_TIMCR_TBU               HRTIM_TIMCR_TBU_Msk                      /*!< Slave Timer B update reserved for TIM B */

+#define HRTIM_TIMCR_TCU_Pos           (21U)

+#define HRTIM_TIMCR_TCU_Msk           (0x1UL << HRTIM_TIMCR_TCU_Pos)           /*!< 0x00200000 */

+#define HRTIM_TIMCR_TCU               HRTIM_TIMCR_TCU_Msk                      /*!< Slave Timer C update reserved for TIM C */

+#define HRTIM_TIMCR_TDU_Pos           (22U)

+#define HRTIM_TIMCR_TDU_Msk           (0x1UL << HRTIM_TIMCR_TDU_Pos)           /*!< 0x00400000 */

+#define HRTIM_TIMCR_TDU               HRTIM_TIMCR_TDU_Msk                      /*!< Slave Timer D update reserved for TIM D */

+#define HRTIM_TIMCR_TEU_Pos           (23U)

+#define HRTIM_TIMCR_TEU_Msk           (0x1UL << HRTIM_TIMCR_TEU_Pos)           /*!< 0x00800000 */

+#define HRTIM_TIMCR_TEU               HRTIM_TIMCR_TEU_Msk                      /*!< Slave Timer E update reserved for TIM E */

+#define HRTIM_TIMCR_MSTU_Pos          (24U)

+#define HRTIM_TIMCR_MSTU_Msk          (0x1UL << HRTIM_TIMCR_MSTU_Pos)          /*!< 0x01000000 */

+#define HRTIM_TIMCR_MSTU              HRTIM_TIMCR_MSTU_Msk                     /*!< Master Update */

+

+#define HRTIM_TIMCR_DACSYNC_Pos       (25U)

+#define HRTIM_TIMCR_DACSYNC_Msk       (0x3UL << HRTIM_TIMCR_DACSYNC_Pos)       /*!< 0x06000000 */

+#define HRTIM_TIMCR_DACSYNC           HRTIM_TIMCR_DACSYNC_Msk                  /*!< DAC sychronization mask */

+#define HRTIM_TIMCR_DACSYNC_0         (0x1UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x02000000 */

+#define HRTIM_TIMCR_DACSYNC_1         (0x2UL << HRTIM_TIMCR_DACSYNC_Pos)        /*!< 0x04000000 */

+#define HRTIM_TIMCR_PREEN_Pos         (27U)

+#define HRTIM_TIMCR_PREEN_Msk         (0x1UL << HRTIM_TIMCR_PREEN_Pos)         /*!< 0x08000000 */

+#define HRTIM_TIMCR_PREEN             HRTIM_TIMCR_PREEN_Msk                    /*!< Slave preload enable */

+

+#define HRTIM_TIMCR_UPDGAT_Pos        (28U)

+#define HRTIM_TIMCR_UPDGAT_Msk        (0xFUL << HRTIM_TIMCR_UPDGAT_Pos)        /*!< 0xF0000000 */

+#define HRTIM_TIMCR_UPDGAT            HRTIM_TIMCR_UPDGAT_Msk                   /*!< Slave update gating mask */

+#define HRTIM_TIMCR_UPDGAT_0          (0x1UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x10000000 */

+#define HRTIM_TIMCR_UPDGAT_1          (0x2UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x20000000 */

+#define HRTIM_TIMCR_UPDGAT_2          (0x4UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x40000000 */

+#define HRTIM_TIMCR_UPDGAT_3          (0x8UL << HRTIM_TIMCR_UPDGAT_Pos)         /*!< 0x80000000 */

+

+/******************** Slave Interrupt status register **************************/

+#define HRTIM_TIMISR_CMP1_Pos         (0U)

+#define HRTIM_TIMISR_CMP1_Msk         (0x1UL << HRTIM_TIMISR_CMP1_Pos)         /*!< 0x00000001 */

+#define HRTIM_TIMISR_CMP1             HRTIM_TIMISR_CMP1_Msk                    /*!< Slave compare 1 interrupt flag */

+#define HRTIM_TIMISR_CMP2_Pos         (1U)

+#define HRTIM_TIMISR_CMP2_Msk         (0x1UL << HRTIM_TIMISR_CMP2_Pos)         /*!< 0x00000002 */

+#define HRTIM_TIMISR_CMP2             HRTIM_TIMISR_CMP2_Msk                    /*!< Slave compare 2 interrupt flag */

+#define HRTIM_TIMISR_CMP3_Pos         (2U)

+#define HRTIM_TIMISR_CMP3_Msk         (0x1UL << HRTIM_TIMISR_CMP3_Pos)         /*!< 0x00000004 */

+#define HRTIM_TIMISR_CMP3             HRTIM_TIMISR_CMP3_Msk                    /*!< Slave compare 3 interrupt flag */

+#define HRTIM_TIMISR_CMP4_Pos         (3U)

+#define HRTIM_TIMISR_CMP4_Msk         (0x1UL << HRTIM_TIMISR_CMP4_Pos)         /*!< 0x00000008 */

+#define HRTIM_TIMISR_CMP4             HRTIM_TIMISR_CMP4_Msk                    /*!< Slave compare 4 interrupt flag */

+#define HRTIM_TIMISR_REP_Pos          (4U)

+#define HRTIM_TIMISR_REP_Msk          (0x1UL << HRTIM_TIMISR_REP_Pos)          /*!< 0x00000010 */

+#define HRTIM_TIMISR_REP              HRTIM_TIMISR_REP_Msk                     /*!< Slave repetition interrupt flag */

+#define HRTIM_TIMISR_UPD_Pos          (6U)

+#define HRTIM_TIMISR_UPD_Msk          (0x1UL << HRTIM_TIMISR_UPD_Pos)          /*!< 0x00000040 */

+#define HRTIM_TIMISR_UPD              HRTIM_TIMISR_UPD_Msk                     /*!< Slave update interrupt flag */

+#define HRTIM_TIMISR_CPT1_Pos         (7U)

+#define HRTIM_TIMISR_CPT1_Msk         (0x1UL << HRTIM_TIMISR_CPT1_Pos)         /*!< 0x00000080 */

+#define HRTIM_TIMISR_CPT1             HRTIM_TIMISR_CPT1_Msk                    /*!< Slave capture 1 interrupt flag */

+#define HRTIM_TIMISR_CPT2_Pos         (8U)

+#define HRTIM_TIMISR_CPT2_Msk         (0x1UL << HRTIM_TIMISR_CPT2_Pos)         /*!< 0x00000100 */

+#define HRTIM_TIMISR_CPT2             HRTIM_TIMISR_CPT2_Msk                    /*!< Slave capture 2 interrupt flag */

+#define HRTIM_TIMISR_SET1_Pos         (9U)

+#define HRTIM_TIMISR_SET1_Msk         (0x1UL << HRTIM_TIMISR_SET1_Pos)         /*!< 0x00000200 */

+#define HRTIM_TIMISR_SET1             HRTIM_TIMISR_SET1_Msk                    /*!< Slave output 1 set interrupt flag */

+#define HRTIM_TIMISR_RST1_Pos         (10U)

+#define HRTIM_TIMISR_RST1_Msk         (0x1UL << HRTIM_TIMISR_RST1_Pos)         /*!< 0x00000400 */

+#define HRTIM_TIMISR_RST1             HRTIM_TIMISR_RST1_Msk                    /*!< Slave output 1 reset interrupt flag */

+#define HRTIM_TIMISR_SET2_Pos         (11U)

+#define HRTIM_TIMISR_SET2_Msk         (0x1UL << HRTIM_TIMISR_SET2_Pos)         /*!< 0x00000800 */

+#define HRTIM_TIMISR_SET2             HRTIM_TIMISR_SET2_Msk                    /*!< Slave output 2 set interrupt flag */

+#define HRTIM_TIMISR_RST2_Pos         (12U)

+#define HRTIM_TIMISR_RST2_Msk         (0x1UL << HRTIM_TIMISR_RST2_Pos)         /*!< 0x00001000 */

+#define HRTIM_TIMISR_RST2             HRTIM_TIMISR_RST2_Msk                    /*!< Slave output 2 reset interrupt flag */

+#define HRTIM_TIMISR_RST_Pos          (13U)

+#define HRTIM_TIMISR_RST_Msk          (0x1UL << HRTIM_TIMISR_RST_Pos)          /*!< 0x00002000 */

+#define HRTIM_TIMISR_RST              HRTIM_TIMISR_RST_Msk                     /*!< Slave reset interrupt flag */

+#define HRTIM_TIMISR_DLYPRT_Pos       (14U)

+#define HRTIM_TIMISR_DLYPRT_Msk       (0x1UL << HRTIM_TIMISR_DLYPRT_Pos)       /*!< 0x00004000 */

+#define HRTIM_TIMISR_DLYPRT           HRTIM_TIMISR_DLYPRT_Msk                  /*!< Slave output 1 delay protection interrupt flag */

+#define HRTIM_TIMISR_CPPSTAT_Pos      (16U)

+#define HRTIM_TIMISR_CPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos)      /*!< 0x00010000 */

+#define HRTIM_TIMISR_CPPSTAT          HRTIM_TIMISR_CPPSTAT_Msk                 /*!< Slave current push-pull flag */

+#define HRTIM_TIMISR_IPPSTAT_Pos      (17U)

+#define HRTIM_TIMISR_IPPSTAT_Msk      (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos)      /*!< 0x00020000 */

+#define HRTIM_TIMISR_IPPSTAT          HRTIM_TIMISR_IPPSTAT_Msk                 /*!< Slave idle push-pull flag */

+#define HRTIM_TIMISR_O1STAT_Pos       (18U)

+#define HRTIM_TIMISR_O1STAT_Msk       (0x1UL << HRTIM_TIMISR_O1STAT_Pos)       /*!< 0x00040000 */

+#define HRTIM_TIMISR_O1STAT           HRTIM_TIMISR_O1STAT_Msk                  /*!< Slave output 1 state flag */

+#define HRTIM_TIMISR_O2STAT_Pos       (19U)

+#define HRTIM_TIMISR_O2STAT_Msk       (0x1UL << HRTIM_TIMISR_O2STAT_Pos)       /*!< 0x00080000 */

+#define HRTIM_TIMISR_O2STAT           HRTIM_TIMISR_O2STAT_Msk                  /*!< Slave output 2 state flag */

+#define HRTIM_TIMISR_O1CPY_Pos        (20U)

+#define HRTIM_TIMISR_O1CPY_Msk        (0x1UL << HRTIM_TIMISR_O1CPY_Pos)        /*!< 0x00100000 */

+#define HRTIM_TIMISR_O1CPY            HRTIM_TIMISR_O1CPY_Msk                   /*!< Slave output 1 copy flag */

+#define HRTIM_TIMISR_O2CPY_Pos        (21U)

+#define HRTIM_TIMISR_O2CPY_Msk        (0x1UL << HRTIM_TIMISR_O2CPY_Pos)        /*!< 0x00200000 */

+#define HRTIM_TIMISR_O2CPY            HRTIM_TIMISR_O2CPY_Msk                   /*!< Slave output 2 copy flag */

+

+/******************** Slave Interrupt clear register **************************/

+#define HRTIM_TIMICR_CMP1C_Pos        (0U)

+#define HRTIM_TIMICR_CMP1C_Msk        (0x1UL << HRTIM_TIMICR_CMP1C_Pos)        /*!< 0x00000001 */

+#define HRTIM_TIMICR_CMP1C            HRTIM_TIMICR_CMP1C_Msk                   /*!< Slave compare 1 clear flag */

+#define HRTIM_TIMICR_CMP2C_Pos        (1U)

+#define HRTIM_TIMICR_CMP2C_Msk        (0x1UL << HRTIM_TIMICR_CMP2C_Pos)        /*!< 0x00000002 */

+#define HRTIM_TIMICR_CMP2C            HRTIM_TIMICR_CMP2C_Msk                   /*!< Slave compare 2 clear flag */

+#define HRTIM_TIMICR_CMP3C_Pos        (2U)

+#define HRTIM_TIMICR_CMP3C_Msk        (0x1UL << HRTIM_TIMICR_CMP3C_Pos)        /*!< 0x00000004 */

+#define HRTIM_TIMICR_CMP3C            HRTIM_TIMICR_CMP3C_Msk                   /*!< Slave compare 3 clear flag */

+#define HRTIM_TIMICR_CMP4C_Pos        (3U)

+#define HRTIM_TIMICR_CMP4C_Msk        (0x1UL << HRTIM_TIMICR_CMP4C_Pos)        /*!< 0x00000008 */

+#define HRTIM_TIMICR_CMP4C            HRTIM_TIMICR_CMP4C_Msk                   /*!< Slave compare 4 clear flag */

+#define HRTIM_TIMICR_REPC_Pos         (4U)

+#define HRTIM_TIMICR_REPC_Msk         (0x1UL << HRTIM_TIMICR_REPC_Pos)         /*!< 0x00000010 */

+#define HRTIM_TIMICR_REPC             HRTIM_TIMICR_REPC_Msk                    /*!< Slave repetition clear flag */

+#define HRTIM_TIMICR_UPDC_Pos         (6U)

+#define HRTIM_TIMICR_UPDC_Msk         (0x1UL << HRTIM_TIMICR_UPDC_Pos)         /*!< 0x00000040 */

+#define HRTIM_TIMICR_UPDC             HRTIM_TIMICR_UPDC_Msk                    /*!< Slave update clear flag */

+#define HRTIM_TIMICR_CPT1C_Pos        (7U)

+#define HRTIM_TIMICR_CPT1C_Msk        (0x1UL << HRTIM_TIMICR_CPT1C_Pos)        /*!< 0x00000080 */

+#define HRTIM_TIMICR_CPT1C            HRTIM_TIMICR_CPT1C_Msk                   /*!< Slave capture 1 clear flag */

+#define HRTIM_TIMICR_CPT2C_Pos        (8U)

+#define HRTIM_TIMICR_CPT2C_Msk        (0x1UL << HRTIM_TIMICR_CPT2C_Pos)        /*!< 0x00000100 */

+#define HRTIM_TIMICR_CPT2C            HRTIM_TIMICR_CPT2C_Msk                   /*!< Slave capture 2 clear flag */

+#define HRTIM_TIMICR_SET1C_Pos        (9U)

+#define HRTIM_TIMICR_SET1C_Msk        (0x1UL << HRTIM_TIMICR_SET1C_Pos)        /*!< 0x00000200 */

+#define HRTIM_TIMICR_SET1C            HRTIM_TIMICR_SET1C_Msk                   /*!< Slave output 1 set clear flag */

+#define HRTIM_TIMICR_RST1C_Pos        (10U)

+#define HRTIM_TIMICR_RST1C_Msk        (0x1UL << HRTIM_TIMICR_RST1C_Pos)        /*!< 0x00000400 */

+#define HRTIM_TIMICR_RST1C            HRTIM_TIMICR_RST1C_Msk                   /*!< Slave output 1 reset clear flag */

+#define HRTIM_TIMICR_SET2C_Pos        (11U)

+#define HRTIM_TIMICR_SET2C_Msk        (0x1UL << HRTIM_TIMICR_SET2C_Pos)        /*!< 0x00000800 */

+#define HRTIM_TIMICR_SET2C            HRTIM_TIMICR_SET2C_Msk                   /*!< Slave output 2 set clear flag */

+#define HRTIM_TIMICR_RST2C_Pos        (12U)

+#define HRTIM_TIMICR_RST2C_Msk        (0x1UL << HRTIM_TIMICR_RST2C_Pos)        /*!< 0x00001000 */

+#define HRTIM_TIMICR_RST2C            HRTIM_TIMICR_RST2C_Msk                   /*!< Slave output 2 reset clear flag */

+#define HRTIM_TIMICR_RSTC_Pos         (13U)

+#define HRTIM_TIMICR_RSTC_Msk         (0x1UL << HRTIM_TIMICR_RSTC_Pos)         /*!< 0x00002000 */

+#define HRTIM_TIMICR_RSTC             HRTIM_TIMICR_RSTC_Msk                    /*!< Slave reset clear flag */

+#define HRTIM_TIMICR_DLYPRTC_Pos      (14U)

+#define HRTIM_TIMICR_DLYPRTC_Msk      (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos)      /*!< 0x00004000 */

+#define HRTIM_TIMICR_DLYPRTC          HRTIM_TIMICR_DLYPRTC_Msk                 /*!< Slave output 1 delay protection clear flag */

+

+/******************** Slave DMA/Interrupt enable register *********************/

+#define HRTIM_TIMDIER_CMP1IE_Pos      (0U)

+#define HRTIM_TIMDIER_CMP1IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos)      /*!< 0x00000001 */

+#define HRTIM_TIMDIER_CMP1IE          HRTIM_TIMDIER_CMP1IE_Msk                 /*!< Slave compare 1 interrupt enable */

+#define HRTIM_TIMDIER_CMP2IE_Pos      (1U)

+#define HRTIM_TIMDIER_CMP2IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos)      /*!< 0x00000002 */

+#define HRTIM_TIMDIER_CMP2IE          HRTIM_TIMDIER_CMP2IE_Msk                 /*!< Slave compare 2 interrupt enable */

+#define HRTIM_TIMDIER_CMP3IE_Pos      (2U)

+#define HRTIM_TIMDIER_CMP3IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos)      /*!< 0x00000004 */

+#define HRTIM_TIMDIER_CMP3IE          HRTIM_TIMDIER_CMP3IE_Msk                 /*!< Slave compare 3 interrupt enable */

+#define HRTIM_TIMDIER_CMP4IE_Pos      (3U)

+#define HRTIM_TIMDIER_CMP4IE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos)      /*!< 0x00000008 */

+#define HRTIM_TIMDIER_CMP4IE          HRTIM_TIMDIER_CMP4IE_Msk                 /*!< Slave compare 4 interrupt enable */

+#define HRTIM_TIMDIER_REPIE_Pos       (4U)

+#define HRTIM_TIMDIER_REPIE_Msk       (0x1UL << HRTIM_TIMDIER_REPIE_Pos)       /*!< 0x00000010 */

+#define HRTIM_TIMDIER_REPIE           HRTIM_TIMDIER_REPIE_Msk                  /*!< Slave repetition interrupt enable */

+#define HRTIM_TIMDIER_UPDIE_Pos       (6U)

+#define HRTIM_TIMDIER_UPDIE_Msk       (0x1UL << HRTIM_TIMDIER_UPDIE_Pos)       /*!< 0x00000040 */

+#define HRTIM_TIMDIER_UPDIE           HRTIM_TIMDIER_UPDIE_Msk                  /*!< Slave update interrupt enable */

+#define HRTIM_TIMDIER_CPT1IE_Pos      (7U)

+#define HRTIM_TIMDIER_CPT1IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos)      /*!< 0x00000080 */

+#define HRTIM_TIMDIER_CPT1IE          HRTIM_TIMDIER_CPT1IE_Msk                 /*!< Slave capture 1 interrupt enable */

+#define HRTIM_TIMDIER_CPT2IE_Pos      (8U)

+#define HRTIM_TIMDIER_CPT2IE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos)      /*!< 0x00000100 */

+#define HRTIM_TIMDIER_CPT2IE          HRTIM_TIMDIER_CPT2IE_Msk                 /*!< Slave capture 2 interrupt enable */

+#define HRTIM_TIMDIER_SET1IE_Pos      (9U)

+#define HRTIM_TIMDIER_SET1IE_Msk      (0x1UL << HRTIM_TIMDIER_SET1IE_Pos)      /*!< 0x00000200 */

+#define HRTIM_TIMDIER_SET1IE          HRTIM_TIMDIER_SET1IE_Msk                 /*!< Slave output 1 set interrupt enable */

+#define HRTIM_TIMDIER_RST1IE_Pos      (10U)

+#define HRTIM_TIMDIER_RST1IE_Msk      (0x1UL << HRTIM_TIMDIER_RST1IE_Pos)      /*!< 0x00000400 */

+#define HRTIM_TIMDIER_RST1IE          HRTIM_TIMDIER_RST1IE_Msk                 /*!< Slave output 1 reset interrupt enable */

+#define HRTIM_TIMDIER_SET2IE_Pos      (11U)

+#define HRTIM_TIMDIER_SET2IE_Msk      (0x1UL << HRTIM_TIMDIER_SET2IE_Pos)      /*!< 0x00000800 */

+#define HRTIM_TIMDIER_SET2IE          HRTIM_TIMDIER_SET2IE_Msk                 /*!< Slave output 2 set interrupt enable */

+#define HRTIM_TIMDIER_RST2IE_Pos      (12U)

+#define HRTIM_TIMDIER_RST2IE_Msk      (0x1UL << HRTIM_TIMDIER_RST2IE_Pos)      /*!< 0x00001000 */

+#define HRTIM_TIMDIER_RST2IE          HRTIM_TIMDIER_RST2IE_Msk                 /*!< Slave output 2 reset interrupt enable */

+#define HRTIM_TIMDIER_RSTIE_Pos       (13U)

+#define HRTIM_TIMDIER_RSTIE_Msk       (0x1UL << HRTIM_TIMDIER_RSTIE_Pos)       /*!< 0x00002000 */

+#define HRTIM_TIMDIER_RSTIE           HRTIM_TIMDIER_RSTIE_Msk                  /*!< Slave reset interrupt enable */

+#define HRTIM_TIMDIER_DLYPRTIE_Pos    (14U)

+#define HRTIM_TIMDIER_DLYPRTIE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos)    /*!< 0x00004000 */

+#define HRTIM_TIMDIER_DLYPRTIE        HRTIM_TIMDIER_DLYPRTIE_Msk               /*!< Slave delay protection interrupt enable */

+

+#define HRTIM_TIMDIER_CMP1DE_Pos      (16U)

+#define HRTIM_TIMDIER_CMP1DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos)      /*!< 0x00010000 */

+#define HRTIM_TIMDIER_CMP1DE          HRTIM_TIMDIER_CMP1DE_Msk                 /*!< Slave compare 1 request enable */

+#define HRTIM_TIMDIER_CMP2DE_Pos      (17U)

+#define HRTIM_TIMDIER_CMP2DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos)      /*!< 0x00020000 */

+#define HRTIM_TIMDIER_CMP2DE          HRTIM_TIMDIER_CMP2DE_Msk                 /*!< Slave compare 2 request enable */

+#define HRTIM_TIMDIER_CMP3DE_Pos      (18U)

+#define HRTIM_TIMDIER_CMP3DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos)      /*!< 0x00040000 */

+#define HRTIM_TIMDIER_CMP3DE          HRTIM_TIMDIER_CMP3DE_Msk                 /*!< Slave compare 3 request enable */

+#define HRTIM_TIMDIER_CMP4DE_Pos      (19U)

+#define HRTIM_TIMDIER_CMP4DE_Msk      (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos)      /*!< 0x00080000 */

+#define HRTIM_TIMDIER_CMP4DE          HRTIM_TIMDIER_CMP4DE_Msk                 /*!< Slave compare 4 request enable */

+#define HRTIM_TIMDIER_REPDE_Pos       (20U)

+#define HRTIM_TIMDIER_REPDE_Msk       (0x1UL << HRTIM_TIMDIER_REPDE_Pos)       /*!< 0x00100000 */

+#define HRTIM_TIMDIER_REPDE           HRTIM_TIMDIER_REPDE_Msk                  /*!< Slave repetition request enable */

+#define HRTIM_TIMDIER_UPDDE_Pos       (22U)

+#define HRTIM_TIMDIER_UPDDE_Msk       (0x1UL << HRTIM_TIMDIER_UPDDE_Pos)       /*!< 0x00400000 */

+#define HRTIM_TIMDIER_UPDDE           HRTIM_TIMDIER_UPDDE_Msk                  /*!< Slave update request enable */

+#define HRTIM_TIMDIER_CPT1DE_Pos      (23U)

+#define HRTIM_TIMDIER_CPT1DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos)      /*!< 0x00800000 */

+#define HRTIM_TIMDIER_CPT1DE          HRTIM_TIMDIER_CPT1DE_Msk                 /*!< Slave capture 1 request enable */

+#define HRTIM_TIMDIER_CPT2DE_Pos      (24U)

+#define HRTIM_TIMDIER_CPT2DE_Msk      (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos)      /*!< 0x01000000 */

+#define HRTIM_TIMDIER_CPT2DE          HRTIM_TIMDIER_CPT2DE_Msk                 /*!< Slave capture 2 request enable */

+#define HRTIM_TIMDIER_SET1DE_Pos      (25U)

+#define HRTIM_TIMDIER_SET1DE_Msk      (0x1UL << HRTIM_TIMDIER_SET1DE_Pos)      /*!< 0x02000000 */

+#define HRTIM_TIMDIER_SET1DE          HRTIM_TIMDIER_SET1DE_Msk                 /*!< Slave output 1 set request enable */

+#define HRTIM_TIMDIER_RST1DE_Pos      (26U)

+#define HRTIM_TIMDIER_RST1DE_Msk      (0x1UL << HRTIM_TIMDIER_RST1DE_Pos)      /*!< 0x04000000 */

+#define HRTIM_TIMDIER_RST1DE          HRTIM_TIMDIER_RST1DE_Msk                 /*!< Slave output 1 reset request enable */

+#define HRTIM_TIMDIER_SET2DE_Pos      (27U)

+#define HRTIM_TIMDIER_SET2DE_Msk      (0x1UL << HRTIM_TIMDIER_SET2DE_Pos)      /*!< 0x08000000 */

+#define HRTIM_TIMDIER_SET2DE          HRTIM_TIMDIER_SET2DE_Msk                 /*!< Slave output 2 set request enable */

+#define HRTIM_TIMDIER_RST2DE_Pos      (28U)

+#define HRTIM_TIMDIER_RST2DE_Msk      (0x1UL << HRTIM_TIMDIER_RST2DE_Pos)      /*!< 0x10000000 */

+#define HRTIM_TIMDIER_RST2DE          HRTIM_TIMDIER_RST2DE_Msk                 /*!< Slave output 2 reset request enable */

+#define HRTIM_TIMDIER_RSTDE_Pos       (29U)

+#define HRTIM_TIMDIER_RSTDE_Msk       (0x1UL << HRTIM_TIMDIER_RSTDE_Pos)       /*!< 0x20000000 */

+#define HRTIM_TIMDIER_RSTDE           HRTIM_TIMDIER_RSTDE_Msk                  /*!< Slave reset request enable */

+#define HRTIM_TIMDIER_DLYPRTDE_Pos    (30U)

+#define HRTIM_TIMDIER_DLYPRTDE_Msk    (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos)    /*!< 0x40000000 */

+#define HRTIM_TIMDIER_DLYPRTDE        HRTIM_TIMDIER_DLYPRTDE_Msk               /*!< Slavedelay protection request enable */

+

+/******************  Bit definition for HRTIM_CNTR register  ****************/

+#define HRTIM_CNTR_CNTR_Pos           (0U)

+#define HRTIM_CNTR_CNTR_Msk           (0xFFFFUL << HRTIM_CNTR_CNTR_Pos)        /*!< 0x0000FFFF */

+#define HRTIM_CNTR_CNTR               HRTIM_CNTR_CNTR_Msk                      /*!< Counter Value */

+

+/*******************  Bit definition for HRTIM_PER register  *****************/

+#define HRTIM_PER_PER_Pos             (0U)

+#define HRTIM_PER_PER_Msk             (0xFFFFUL << HRTIM_PER_PER_Pos)          /*!< 0x0000FFFF */

+#define HRTIM_PER_PER                 HRTIM_PER_PER_Msk                        /*!< Period Value */

+

+/*******************  Bit definition for HRTIM_REP register  *****************/

+#define HRTIM_REP_REP_Pos             (0U)

+#define HRTIM_REP_REP_Msk             (0xFFUL << HRTIM_REP_REP_Pos)            /*!< 0x000000FF */

+#define HRTIM_REP_REP                 HRTIM_REP_REP_Msk                        /*!< Repetition Value */

+

+/*******************  Bit definition for HRTIM_CMP1R register  *****************/

+#define HRTIM_CMP1R_CMP1R_Pos         (0U)

+#define HRTIM_CMP1R_CMP1R_Msk         (0xFFFFUL << HRTIM_CMP1R_CMP1R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP1R_CMP1R             HRTIM_CMP1R_CMP1R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP1CR register  *****************/

+#define HRTIM_CMP1CR_CMP1CR_Pos       (0U)

+#define HRTIM_CMP1CR_CMP1CR_Msk       (0xFFFFFFFFUL << HRTIM_CMP1CR_CMP1CR_Pos) /*!< 0xFFFFFFFF */

+#define HRTIM_CMP1CR_CMP1CR           HRTIM_CMP1CR_CMP1CR_Msk                  /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP2R register  *****************/

+#define HRTIM_CMP2R_CMP2R_Pos         (0U)

+#define HRTIM_CMP2R_CMP2R_Msk         (0xFFFFUL << HRTIM_CMP2R_CMP2R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP2R_CMP2R             HRTIM_CMP2R_CMP2R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP3R register  *****************/

+#define HRTIM_CMP3R_CMP3R_Pos         (0U)

+#define HRTIM_CMP3R_CMP3R_Msk         (0xFFFFUL << HRTIM_CMP3R_CMP3R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP3R_CMP3R             HRTIM_CMP3R_CMP3R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CMP4R register  *****************/

+#define HRTIM_CMP4R_CMP4R_Pos         (0U)

+#define HRTIM_CMP4R_CMP4R_Msk         (0xFFFFUL << HRTIM_CMP4R_CMP4R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CMP4R_CMP4R             HRTIM_CMP4R_CMP4R_Msk                    /*!< Compare Value */

+

+/*******************  Bit definition for HRTIM_CPT1R register  ****************/

+#define HRTIM_CPT1R_CPT1R_Pos         (0U)

+#define HRTIM_CPT1R_CPT1R_Msk         (0xFFFFUL << HRTIM_CPT1R_CPT1R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CPT1R_CPT1R             HRTIM_CPT1R_CPT1R_Msk                    /*!< Capture Value */

+

+/*******************  Bit definition for HRTIM_CPT2R register  ****************/

+#define HRTIM_CPT2R_CPT2R_Pos         (0U)

+#define HRTIM_CPT2R_CPT2R_Msk         (0xFFFFUL << HRTIM_CPT2R_CPT2R_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_CPT2R_CPT2R             HRTIM_CPT2R_CPT2R_Msk                    /*!< Capture Value */

+

+/******************** Bit definition for Slave Deadtime register **************/

+#define HRTIM_DTR_DTR_Pos             (0U)

+#define HRTIM_DTR_DTR_Msk             (0x1FFUL << HRTIM_DTR_DTR_Pos)           /*!< 0x000001FF */

+#define HRTIM_DTR_DTR                 HRTIM_DTR_DTR_Msk                        /*!< Dead time rising value */

+#define HRTIM_DTR_DTR_0               (0x001UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000001 */

+#define HRTIM_DTR_DTR_1               (0x002UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000002 */

+#define HRTIM_DTR_DTR_2               (0x004UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000004 */

+#define HRTIM_DTR_DTR_3               (0x008UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000008 */

+#define HRTIM_DTR_DTR_4               (0x010UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000010 */

+#define HRTIM_DTR_DTR_5               (0x020UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000020 */

+#define HRTIM_DTR_DTR_6               (0x040UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000040 */

+#define HRTIM_DTR_DTR_7               (0x080UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000080 */

+#define HRTIM_DTR_DTR_8               (0x100UL << HRTIM_DTR_DTR_Pos)            /*!< 0x00000100 */

+#define HRTIM_DTR_SDTR_Pos            (9U)

+#define HRTIM_DTR_SDTR_Msk            (0x1UL << HRTIM_DTR_SDTR_Pos)            /*!< 0x00000200 */

+#define HRTIM_DTR_SDTR                HRTIM_DTR_SDTR_Msk                       /*!< Sign dead time rising value */

+#define HRTIM_DTR_DTPRSC_Pos          (10U)

+#define HRTIM_DTR_DTPRSC_Msk          (0x7UL << HRTIM_DTR_DTPRSC_Pos)          /*!< 0x00001C00 */

+#define HRTIM_DTR_DTPRSC              HRTIM_DTR_DTPRSC_Msk                     /*!< Dead time prescaler */

+#define HRTIM_DTR_DTPRSC_0            (0x1UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000400 */

+#define HRTIM_DTR_DTPRSC_1            (0x2UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00000800 */

+#define HRTIM_DTR_DTPRSC_2            (0x4UL << HRTIM_DTR_DTPRSC_Pos)           /*!< 0x00001000 */

+#define HRTIM_DTR_DTRSLK_Pos          (14U)

+#define HRTIM_DTR_DTRSLK_Msk          (0x1UL << HRTIM_DTR_DTRSLK_Pos)          /*!< 0x00004000 */

+#define HRTIM_DTR_DTRSLK              HRTIM_DTR_DTRSLK_Msk                     /*!< Dead time rising sign lock */

+#define HRTIM_DTR_DTRLK_Pos           (15U)

+#define HRTIM_DTR_DTRLK_Msk           (0x1UL << HRTIM_DTR_DTRLK_Pos)           /*!< 0x00008000 */

+#define HRTIM_DTR_DTRLK               HRTIM_DTR_DTRLK_Msk                      /*!< Dead time rising lock */

+#define HRTIM_DTR_DTF_Pos             (16U)

+#define HRTIM_DTR_DTF_Msk             (0x1FFUL << HRTIM_DTR_DTF_Pos)           /*!< 0x01FF0000 */

+#define HRTIM_DTR_DTF                 HRTIM_DTR_DTF_Msk                        /*!< Dead time falling value */

+#define HRTIM_DTR_DTF_0               (0x001UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00010000 */

+#define HRTIM_DTR_DTF_1               (0x002UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00020000 */

+#define HRTIM_DTR_DTF_2               (0x004UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00040000 */

+#define HRTIM_DTR_DTF_3               (0x008UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00080000 */

+#define HRTIM_DTR_DTF_4               (0x010UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00100000 */

+#define HRTIM_DTR_DTF_5               (0x020UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00200000 */

+#define HRTIM_DTR_DTF_6               (0x040UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00400000 */

+#define HRTIM_DTR_DTF_7               (0x080UL << HRTIM_DTR_DTF_Pos)            /*!< 0x00800000 */

+#define HRTIM_DTR_DTF_8               (0x100UL << HRTIM_DTR_DTF_Pos)            /*!< 0x01000000 */

+#define HRTIM_DTR_SDTF_Pos            (25U)

+#define HRTIM_DTR_SDTF_Msk            (0x1UL << HRTIM_DTR_SDTF_Pos)            /*!< 0x02000000 */

+#define HRTIM_DTR_SDTF                HRTIM_DTR_SDTF_Msk                       /*!< Sign dead time falling value */

+#define HRTIM_DTR_DTFSLK_Pos          (30U)

+#define HRTIM_DTR_DTFSLK_Msk          (0x1UL << HRTIM_DTR_DTFSLK_Pos)          /*!< 0x40000000 */

+#define HRTIM_DTR_DTFSLK              HRTIM_DTR_DTFSLK_Msk                     /*!< Dead time falling sign lock */

+#define HRTIM_DTR_DTFLK_Pos           (31U)

+#define HRTIM_DTR_DTFLK_Msk           (0x1UL << HRTIM_DTR_DTFLK_Pos)           /*!< 0x80000000 */

+#define HRTIM_DTR_DTFLK               HRTIM_DTR_DTFLK_Msk                      /*!< Dead time falling lock */

+

+/**** Bit definition for Slave Output 1 set register **************************/

+#define HRTIM_SET1R_SST_Pos           (0U)

+#define HRTIM_SET1R_SST_Msk           (0x1UL << HRTIM_SET1R_SST_Pos)           /*!< 0x00000001 */

+#define HRTIM_SET1R_SST               HRTIM_SET1R_SST_Msk                      /*!< software set trigger */

+#define HRTIM_SET1R_RESYNC_Pos        (1U)

+#define HRTIM_SET1R_RESYNC_Msk        (0x1UL << HRTIM_SET1R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_SET1R_RESYNC            HRTIM_SET1R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_SET1R_PER_Pos           (2U)

+#define HRTIM_SET1R_PER_Msk           (0x1UL << HRTIM_SET1R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_SET1R_PER               HRTIM_SET1R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_SET1R_CMP1_Pos          (3U)

+#define HRTIM_SET1R_CMP1_Msk          (0x1UL << HRTIM_SET1R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_SET1R_CMP1              HRTIM_SET1R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_SET1R_CMP2_Pos          (4U)

+#define HRTIM_SET1R_CMP2_Msk          (0x1UL << HRTIM_SET1R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_SET1R_CMP2              HRTIM_SET1R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_SET1R_CMP3_Pos          (5U)

+#define HRTIM_SET1R_CMP3_Msk          (0x1UL << HRTIM_SET1R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_SET1R_CMP3              HRTIM_SET1R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_SET1R_CMP4_Pos          (6U)

+#define HRTIM_SET1R_CMP4_Msk          (0x1UL << HRTIM_SET1R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_SET1R_CMP4              HRTIM_SET1R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_SET1R_MSTPER_Pos        (7U)

+#define HRTIM_SET1R_MSTPER_Msk        (0x1UL << HRTIM_SET1R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_SET1R_MSTPER            HRTIM_SET1R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_SET1R_MSTCMP1_Pos       (8U)

+#define HRTIM_SET1R_MSTCMP1_Msk       (0x1UL << HRTIM_SET1R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_SET1R_MSTCMP1           HRTIM_SET1R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_SET1R_MSTCMP2_Pos       (9U)

+#define HRTIM_SET1R_MSTCMP2_Msk       (0x1UL << HRTIM_SET1R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_SET1R_MSTCMP2           HRTIM_SET1R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_SET1R_MSTCMP3_Pos       (10U)

+#define HRTIM_SET1R_MSTCMP3_Msk       (0x1UL << HRTIM_SET1R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_SET1R_MSTCMP3           HRTIM_SET1R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_SET1R_MSTCMP4_Pos       (11U)

+#define HRTIM_SET1R_MSTCMP4_Msk       (0x1UL << HRTIM_SET1R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_SET1R_MSTCMP4           HRTIM_SET1R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_SET1R_TIMEVNT1_Pos      (12U)

+#define HRTIM_SET1R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_SET1R_TIMEVNT1          HRTIM_SET1R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_SET1R_TIMEVNT2_Pos      (13U)

+#define HRTIM_SET1R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_SET1R_TIMEVNT2          HRTIM_SET1R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_SET1R_TIMEVNT3_Pos      (14U)

+#define HRTIM_SET1R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_SET1R_TIMEVNT3          HRTIM_SET1R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_SET1R_TIMEVNT4_Pos      (15U)

+#define HRTIM_SET1R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_SET1R_TIMEVNT4          HRTIM_SET1R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_SET1R_TIMEVNT5_Pos      (16U)

+#define HRTIM_SET1R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_SET1R_TIMEVNT5          HRTIM_SET1R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_SET1R_TIMEVNT6_Pos      (17U)

+#define HRTIM_SET1R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_SET1R_TIMEVNT6          HRTIM_SET1R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_SET1R_TIMEVNT7_Pos      (18U)

+#define HRTIM_SET1R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_SET1R_TIMEVNT7          HRTIM_SET1R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_SET1R_TIMEVNT8_Pos      (19U)

+#define HRTIM_SET1R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_SET1R_TIMEVNT8          HRTIM_SET1R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_SET1R_TIMEVNT9_Pos      (20U)

+#define HRTIM_SET1R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_SET1R_TIMEVNT9          HRTIM_SET1R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_SET1R_EXTVNT1_Pos       (21U)

+#define HRTIM_SET1R_EXTVNT1_Msk       (0x1UL << HRTIM_SET1R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_SET1R_EXTVNT1           HRTIM_SET1R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_SET1R_EXTVNT2_Pos       (22U)

+#define HRTIM_SET1R_EXTVNT2_Msk       (0x1UL << HRTIM_SET1R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_SET1R_EXTVNT2           HRTIM_SET1R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_SET1R_EXTVNT3_Pos       (23U)

+#define HRTIM_SET1R_EXTVNT3_Msk       (0x1UL << HRTIM_SET1R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_SET1R_EXTVNT3           HRTIM_SET1R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_SET1R_EXTVNT4_Pos       (24U)

+#define HRTIM_SET1R_EXTVNT4_Msk       (0x1UL << HRTIM_SET1R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_SET1R_EXTVNT4           HRTIM_SET1R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_SET1R_EXTVNT5_Pos       (25U)

+#define HRTIM_SET1R_EXTVNT5_Msk       (0x1UL << HRTIM_SET1R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_SET1R_EXTVNT5           HRTIM_SET1R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_SET1R_EXTVNT6_Pos       (26U)

+#define HRTIM_SET1R_EXTVNT6_Msk       (0x1UL << HRTIM_SET1R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_SET1R_EXTVNT6           HRTIM_SET1R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_SET1R_EXTVNT7_Pos       (27U)

+#define HRTIM_SET1R_EXTVNT7_Msk       (0x1UL << HRTIM_SET1R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_SET1R_EXTVNT7           HRTIM_SET1R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_SET1R_EXTVNT8_Pos       (28U)

+#define HRTIM_SET1R_EXTVNT8_Msk       (0x1UL << HRTIM_SET1R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_SET1R_EXTVNT8           HRTIM_SET1R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_SET1R_EXTVNT9_Pos       (29U)

+#define HRTIM_SET1R_EXTVNT9_Msk       (0x1UL << HRTIM_SET1R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_SET1R_EXTVNT9           HRTIM_SET1R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_SET1R_EXTVNT10_Pos      (30U)

+#define HRTIM_SET1R_EXTVNT10_Msk      (0x1UL << HRTIM_SET1R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_SET1R_EXTVNT10          HRTIM_SET1R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_SET1R_UPDATE_Pos        (31U)

+#define HRTIM_SET1R_UPDATE_Msk        (0x1UL << HRTIM_SET1R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_SET1R_UPDATE            HRTIM_SET1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+/**** Bit definition for Slave Output 1 reset register ************************/

+#define HRTIM_RST1R_SRT_Pos           (0U)

+#define HRTIM_RST1R_SRT_Msk           (0x1UL << HRTIM_RST1R_SRT_Pos)           /*!< 0x00000001 */

+#define HRTIM_RST1R_SRT               HRTIM_RST1R_SRT_Msk                      /*!< software reset trigger */

+#define HRTIM_RST1R_RESYNC_Pos        (1U)

+#define HRTIM_RST1R_RESYNC_Msk        (0x1UL << HRTIM_RST1R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_RST1R_RESYNC            HRTIM_RST1R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_RST1R_PER_Pos           (2U)

+#define HRTIM_RST1R_PER_Msk           (0x1UL << HRTIM_RST1R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_RST1R_PER               HRTIM_RST1R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_RST1R_CMP1_Pos          (3U)

+#define HRTIM_RST1R_CMP1_Msk          (0x1UL << HRTIM_RST1R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_RST1R_CMP1              HRTIM_RST1R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_RST1R_CMP2_Pos          (4U)

+#define HRTIM_RST1R_CMP2_Msk          (0x1UL << HRTIM_RST1R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_RST1R_CMP2              HRTIM_RST1R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_RST1R_CMP3_Pos          (5U)

+#define HRTIM_RST1R_CMP3_Msk          (0x1UL << HRTIM_RST1R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_RST1R_CMP3              HRTIM_RST1R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_RST1R_CMP4_Pos          (6U)

+#define HRTIM_RST1R_CMP4_Msk          (0x1UL << HRTIM_RST1R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_RST1R_CMP4              HRTIM_RST1R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_RST1R_MSTPER_Pos        (7U)

+#define HRTIM_RST1R_MSTPER_Msk        (0x1UL << HRTIM_RST1R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_RST1R_MSTPER            HRTIM_RST1R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_RST1R_MSTCMP1_Pos       (8U)

+#define HRTIM_RST1R_MSTCMP1_Msk       (0x1UL << HRTIM_RST1R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_RST1R_MSTCMP1           HRTIM_RST1R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_RST1R_MSTCMP2_Pos       (9U)

+#define HRTIM_RST1R_MSTCMP2_Msk       (0x1UL << HRTIM_RST1R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_RST1R_MSTCMP2           HRTIM_RST1R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_RST1R_MSTCMP3_Pos       (10U)

+#define HRTIM_RST1R_MSTCMP3_Msk       (0x1UL << HRTIM_RST1R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_RST1R_MSTCMP3           HRTIM_RST1R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_RST1R_MSTCMP4_Pos       (11U)

+#define HRTIM_RST1R_MSTCMP4_Msk       (0x1UL << HRTIM_RST1R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_RST1R_MSTCMP4           HRTIM_RST1R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_RST1R_TIMEVNT1_Pos      (12U)

+#define HRTIM_RST1R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_RST1R_TIMEVNT1          HRTIM_RST1R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_RST1R_TIMEVNT2_Pos      (13U)

+#define HRTIM_RST1R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_RST1R_TIMEVNT2          HRTIM_RST1R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_RST1R_TIMEVNT3_Pos      (14U)

+#define HRTIM_RST1R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_RST1R_TIMEVNT3          HRTIM_RST1R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_RST1R_TIMEVNT4_Pos      (15U)

+#define HRTIM_RST1R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_RST1R_TIMEVNT4          HRTIM_RST1R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_RST1R_TIMEVNT5_Pos      (16U)

+#define HRTIM_RST1R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_RST1R_TIMEVNT5          HRTIM_RST1R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_RST1R_TIMEVNT6_Pos      (17U)

+#define HRTIM_RST1R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_RST1R_TIMEVNT6          HRTIM_RST1R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_RST1R_TIMEVNT7_Pos      (18U)

+#define HRTIM_RST1R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_RST1R_TIMEVNT7          HRTIM_RST1R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_RST1R_TIMEVNT8_Pos      (19U)

+#define HRTIM_RST1R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_RST1R_TIMEVNT8          HRTIM_RST1R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_RST1R_TIMEVNT9_Pos      (20U)

+#define HRTIM_RST1R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_RST1R_TIMEVNT9          HRTIM_RST1R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_RST1R_EXTVNT1_Pos       (21U)

+#define HRTIM_RST1R_EXTVNT1_Msk       (0x1UL << HRTIM_RST1R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_RST1R_EXTVNT1           HRTIM_RST1R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_RST1R_EXTVNT2_Pos       (22U)

+#define HRTIM_RST1R_EXTVNT2_Msk       (0x1UL << HRTIM_RST1R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_RST1R_EXTVNT2           HRTIM_RST1R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_RST1R_EXTVNT3_Pos       (23U)

+#define HRTIM_RST1R_EXTVNT3_Msk       (0x1UL << HRTIM_RST1R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_RST1R_EXTVNT3           HRTIM_RST1R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_RST1R_EXTVNT4_Pos       (24U)

+#define HRTIM_RST1R_EXTVNT4_Msk       (0x1UL << HRTIM_RST1R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_RST1R_EXTVNT4           HRTIM_RST1R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_RST1R_EXTVNT5_Pos       (25U)

+#define HRTIM_RST1R_EXTVNT5_Msk       (0x1UL << HRTIM_RST1R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_RST1R_EXTVNT5           HRTIM_RST1R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_RST1R_EXTVNT6_Pos       (26U)

+#define HRTIM_RST1R_EXTVNT6_Msk       (0x1UL << HRTIM_RST1R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_RST1R_EXTVNT6           HRTIM_RST1R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_RST1R_EXTVNT7_Pos       (27U)

+#define HRTIM_RST1R_EXTVNT7_Msk       (0x1UL << HRTIM_RST1R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_RST1R_EXTVNT7           HRTIM_RST1R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_RST1R_EXTVNT8_Pos       (28U)

+#define HRTIM_RST1R_EXTVNT8_Msk       (0x1UL << HRTIM_RST1R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_RST1R_EXTVNT8           HRTIM_RST1R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_RST1R_EXTVNT9_Pos       (29U)

+#define HRTIM_RST1R_EXTVNT9_Msk       (0x1UL << HRTIM_RST1R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_RST1R_EXTVNT9           HRTIM_RST1R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_RST1R_EXTVNT10_Pos      (30U)

+#define HRTIM_RST1R_EXTVNT10_Msk      (0x1UL << HRTIM_RST1R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_RST1R_EXTVNT10          HRTIM_RST1R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_RST1R_UPDATE_Pos        (31U)

+#define HRTIM_RST1R_UPDATE_Msk        (0x1UL << HRTIM_RST1R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_RST1R_UPDATE            HRTIM_RST1R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+

+/**** Bit definition for Slave Output 2 set register **************************/

+#define HRTIM_SET2R_SST_Pos           (0U)

+#define HRTIM_SET2R_SST_Msk           (0x1UL << HRTIM_SET2R_SST_Pos)           /*!< 0x00000001 */

+#define HRTIM_SET2R_SST               HRTIM_SET2R_SST_Msk                      /*!< software set trigger */

+#define HRTIM_SET2R_RESYNC_Pos        (1U)

+#define HRTIM_SET2R_RESYNC_Msk        (0x1UL << HRTIM_SET2R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_SET2R_RESYNC            HRTIM_SET2R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_SET2R_PER_Pos           (2U)

+#define HRTIM_SET2R_PER_Msk           (0x1UL << HRTIM_SET2R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_SET2R_PER               HRTIM_SET2R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_SET2R_CMP1_Pos          (3U)

+#define HRTIM_SET2R_CMP1_Msk          (0x1UL << HRTIM_SET2R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_SET2R_CMP1              HRTIM_SET2R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_SET2R_CMP2_Pos          (4U)

+#define HRTIM_SET2R_CMP2_Msk          (0x1UL << HRTIM_SET2R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_SET2R_CMP2              HRTIM_SET2R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_SET2R_CMP3_Pos          (5U)

+#define HRTIM_SET2R_CMP3_Msk          (0x1UL << HRTIM_SET2R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_SET2R_CMP3              HRTIM_SET2R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_SET2R_CMP4_Pos          (6U)

+#define HRTIM_SET2R_CMP4_Msk          (0x1UL << HRTIM_SET2R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_SET2R_CMP4              HRTIM_SET2R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_SET2R_MSTPER_Pos        (7U)

+#define HRTIM_SET2R_MSTPER_Msk        (0x1UL << HRTIM_SET2R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_SET2R_MSTPER            HRTIM_SET2R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_SET2R_MSTCMP1_Pos       (8U)

+#define HRTIM_SET2R_MSTCMP1_Msk       (0x1UL << HRTIM_SET2R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_SET2R_MSTCMP1           HRTIM_SET2R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_SET2R_MSTCMP2_Pos       (9U)

+#define HRTIM_SET2R_MSTCMP2_Msk       (0x1UL << HRTIM_SET2R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_SET2R_MSTCMP2           HRTIM_SET2R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_SET2R_MSTCMP3_Pos       (10U)

+#define HRTIM_SET2R_MSTCMP3_Msk       (0x1UL << HRTIM_SET2R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_SET2R_MSTCMP3           HRTIM_SET2R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_SET2R_MSTCMP4_Pos       (11U)

+#define HRTIM_SET2R_MSTCMP4_Msk       (0x1UL << HRTIM_SET2R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_SET2R_MSTCMP4           HRTIM_SET2R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_SET2R_TIMEVNT1_Pos      (12U)

+#define HRTIM_SET2R_TIMEVNT1_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_SET2R_TIMEVNT1          HRTIM_SET2R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_SET2R_TIMEVNT2_Pos      (13U)

+#define HRTIM_SET2R_TIMEVNT2_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_SET2R_TIMEVNT2          HRTIM_SET2R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_SET2R_TIMEVNT3_Pos      (14U)

+#define HRTIM_SET2R_TIMEVNT3_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_SET2R_TIMEVNT3          HRTIM_SET2R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_SET2R_TIMEVNT4_Pos      (15U)

+#define HRTIM_SET2R_TIMEVNT4_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_SET2R_TIMEVNT4          HRTIM_SET2R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_SET2R_TIMEVNT5_Pos      (16U)

+#define HRTIM_SET2R_TIMEVNT5_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_SET2R_TIMEVNT5          HRTIM_SET2R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_SET2R_TIMEVNT6_Pos      (17U)

+#define HRTIM_SET2R_TIMEVNT6_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_SET2R_TIMEVNT6          HRTIM_SET2R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_SET2R_TIMEVNT7_Pos      (18U)

+#define HRTIM_SET2R_TIMEVNT7_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_SET2R_TIMEVNT7          HRTIM_SET2R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_SET2R_TIMEVNT8_Pos      (19U)

+#define HRTIM_SET2R_TIMEVNT8_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_SET2R_TIMEVNT8          HRTIM_SET2R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_SET2R_TIMEVNT9_Pos      (20U)

+#define HRTIM_SET2R_TIMEVNT9_Msk      (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_SET2R_TIMEVNT9          HRTIM_SET2R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_SET2R_EXTVNT1_Pos       (21U)

+#define HRTIM_SET2R_EXTVNT1_Msk       (0x1UL << HRTIM_SET2R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_SET2R_EXTVNT1           HRTIM_SET2R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_SET2R_EXTVNT2_Pos       (22U)

+#define HRTIM_SET2R_EXTVNT2_Msk       (0x1UL << HRTIM_SET2R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_SET2R_EXTVNT2           HRTIM_SET2R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_SET2R_EXTVNT3_Pos       (23U)

+#define HRTIM_SET2R_EXTVNT3_Msk       (0x1UL << HRTIM_SET2R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_SET2R_EXTVNT3           HRTIM_SET2R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_SET2R_EXTVNT4_Pos       (24U)

+#define HRTIM_SET2R_EXTVNT4_Msk       (0x1UL << HRTIM_SET2R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_SET2R_EXTVNT4           HRTIM_SET2R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_SET2R_EXTVNT5_Pos       (25U)

+#define HRTIM_SET2R_EXTVNT5_Msk       (0x1UL << HRTIM_SET2R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_SET2R_EXTVNT5           HRTIM_SET2R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_SET2R_EXTVNT6_Pos       (26U)

+#define HRTIM_SET2R_EXTVNT6_Msk       (0x1UL << HRTIM_SET2R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_SET2R_EXTVNT6           HRTIM_SET2R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_SET2R_EXTVNT7_Pos       (27U)

+#define HRTIM_SET2R_EXTVNT7_Msk       (0x1UL << HRTIM_SET2R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_SET2R_EXTVNT7           HRTIM_SET2R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_SET2R_EXTVNT8_Pos       (28U)

+#define HRTIM_SET2R_EXTVNT8_Msk       (0x1UL << HRTIM_SET2R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_SET2R_EXTVNT8           HRTIM_SET2R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_SET2R_EXTVNT9_Pos       (29U)

+#define HRTIM_SET2R_EXTVNT9_Msk       (0x1UL << HRTIM_SET2R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_SET2R_EXTVNT9           HRTIM_SET2R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_SET2R_EXTVNT10_Pos      (30U)

+#define HRTIM_SET2R_EXTVNT10_Msk      (0x1UL << HRTIM_SET2R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_SET2R_EXTVNT10          HRTIM_SET2R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_SET2R_UPDATE_Pos        (31U)

+#define HRTIM_SET2R_UPDATE_Msk        (0x1UL << HRTIM_SET2R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_SET2R_UPDATE            HRTIM_SET2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+/**** Bit definition for Slave Output 2 reset register ************************/

+#define HRTIM_RST2R_SRT_Pos           (0U)

+#define HRTIM_RST2R_SRT_Msk           (0x1UL << HRTIM_RST2R_SRT_Pos)           /*!< 0x00000001 */

+#define HRTIM_RST2R_SRT               HRTIM_RST2R_SRT_Msk                      /*!< software reset trigger */

+#define HRTIM_RST2R_RESYNC_Pos        (1U)

+#define HRTIM_RST2R_RESYNC_Msk        (0x1UL << HRTIM_RST2R_RESYNC_Pos)        /*!< 0x00000002 */

+#define HRTIM_RST2R_RESYNC            HRTIM_RST2R_RESYNC_Msk                   /*!< Timer A resynchronization */

+#define HRTIM_RST2R_PER_Pos           (2U)

+#define HRTIM_RST2R_PER_Msk           (0x1UL << HRTIM_RST2R_PER_Pos)           /*!< 0x00000004 */

+#define HRTIM_RST2R_PER               HRTIM_RST2R_PER_Msk                      /*!< Timer A period */

+#define HRTIM_RST2R_CMP1_Pos          (3U)

+#define HRTIM_RST2R_CMP1_Msk          (0x1UL << HRTIM_RST2R_CMP1_Pos)          /*!< 0x00000008 */

+#define HRTIM_RST2R_CMP1              HRTIM_RST2R_CMP1_Msk                     /*!< Timer A compare 1 */

+#define HRTIM_RST2R_CMP2_Pos          (4U)

+#define HRTIM_RST2R_CMP2_Msk          (0x1UL << HRTIM_RST2R_CMP2_Pos)          /*!< 0x00000010 */

+#define HRTIM_RST2R_CMP2              HRTIM_RST2R_CMP2_Msk                     /*!< Timer A compare 2 */

+#define HRTIM_RST2R_CMP3_Pos          (5U)

+#define HRTIM_RST2R_CMP3_Msk          (0x1UL << HRTIM_RST2R_CMP3_Pos)          /*!< 0x00000020 */

+#define HRTIM_RST2R_CMP3              HRTIM_RST2R_CMP3_Msk                     /*!< Timer A compare 3 */

+#define HRTIM_RST2R_CMP4_Pos          (6U)

+#define HRTIM_RST2R_CMP4_Msk          (0x1UL << HRTIM_RST2R_CMP4_Pos)          /*!< 0x00000040 */

+#define HRTIM_RST2R_CMP4              HRTIM_RST2R_CMP4_Msk                     /*!< Timer A compare 4 */

+

+#define HRTIM_RST2R_MSTPER_Pos        (7U)

+#define HRTIM_RST2R_MSTPER_Msk        (0x1UL << HRTIM_RST2R_MSTPER_Pos)        /*!< 0x00000080 */

+#define HRTIM_RST2R_MSTPER            HRTIM_RST2R_MSTPER_Msk                   /*!< Master period */

+#define HRTIM_RST2R_MSTCMP1_Pos       (8U)

+#define HRTIM_RST2R_MSTCMP1_Msk       (0x1UL << HRTIM_RST2R_MSTCMP1_Pos)       /*!< 0x00000100 */

+#define HRTIM_RST2R_MSTCMP1           HRTIM_RST2R_MSTCMP1_Msk                  /*!< Master compare 1 */

+#define HRTIM_RST2R_MSTCMP2_Pos       (9U)

+#define HRTIM_RST2R_MSTCMP2_Msk       (0x1UL << HRTIM_RST2R_MSTCMP2_Pos)       /*!< 0x00000200 */

+#define HRTIM_RST2R_MSTCMP2           HRTIM_RST2R_MSTCMP2_Msk                  /*!< Master compare 2 */

+#define HRTIM_RST2R_MSTCMP3_Pos       (10U)

+#define HRTIM_RST2R_MSTCMP3_Msk       (0x1UL << HRTIM_RST2R_MSTCMP3_Pos)       /*!< 0x00000400 */

+#define HRTIM_RST2R_MSTCMP3           HRTIM_RST2R_MSTCMP3_Msk                  /*!< Master compare 3 */

+#define HRTIM_RST2R_MSTCMP4_Pos       (11U)

+#define HRTIM_RST2R_MSTCMP4_Msk       (0x1UL << HRTIM_RST2R_MSTCMP4_Pos)       /*!< 0x00000800 */

+#define HRTIM_RST2R_MSTCMP4           HRTIM_RST2R_MSTCMP4_Msk                  /*!< Master compare 4 */

+

+#define HRTIM_RST2R_TIMEVNT1_Pos      (12U)

+#define HRTIM_RST2R_TIMEVNT1_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos)      /*!< 0x00001000 */

+#define HRTIM_RST2R_TIMEVNT1          HRTIM_RST2R_TIMEVNT1_Msk                 /*!< Timer event 1 */

+#define HRTIM_RST2R_TIMEVNT2_Pos      (13U)

+#define HRTIM_RST2R_TIMEVNT2_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos)      /*!< 0x00002000 */

+#define HRTIM_RST2R_TIMEVNT2          HRTIM_RST2R_TIMEVNT2_Msk                 /*!< Timer event 2 */

+#define HRTIM_RST2R_TIMEVNT3_Pos      (14U)

+#define HRTIM_RST2R_TIMEVNT3_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos)      /*!< 0x00004000 */

+#define HRTIM_RST2R_TIMEVNT3          HRTIM_RST2R_TIMEVNT3_Msk                 /*!< Timer event 3 */

+#define HRTIM_RST2R_TIMEVNT4_Pos      (15U)

+#define HRTIM_RST2R_TIMEVNT4_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos)      /*!< 0x00008000 */

+#define HRTIM_RST2R_TIMEVNT4          HRTIM_RST2R_TIMEVNT4_Msk                 /*!< Timer event 4 */

+#define HRTIM_RST2R_TIMEVNT5_Pos      (16U)

+#define HRTIM_RST2R_TIMEVNT5_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos)      /*!< 0x00010000 */

+#define HRTIM_RST2R_TIMEVNT5          HRTIM_RST2R_TIMEVNT5_Msk                 /*!< Timer event 5 */

+#define HRTIM_RST2R_TIMEVNT6_Pos      (17U)

+#define HRTIM_RST2R_TIMEVNT6_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos)      /*!< 0x00020000 */

+#define HRTIM_RST2R_TIMEVNT6          HRTIM_RST2R_TIMEVNT6_Msk                 /*!< Timer event 6 */

+#define HRTIM_RST2R_TIMEVNT7_Pos      (18U)

+#define HRTIM_RST2R_TIMEVNT7_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos)      /*!< 0x00040000 */

+#define HRTIM_RST2R_TIMEVNT7          HRTIM_RST2R_TIMEVNT7_Msk                 /*!< Timer event 7 */

+#define HRTIM_RST2R_TIMEVNT8_Pos      (19U)

+#define HRTIM_RST2R_TIMEVNT8_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos)      /*!< 0x00080000 */

+#define HRTIM_RST2R_TIMEVNT8          HRTIM_RST2R_TIMEVNT8_Msk                 /*!< Timer event 8 */

+#define HRTIM_RST2R_TIMEVNT9_Pos      (20U)

+#define HRTIM_RST2R_TIMEVNT9_Msk      (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos)      /*!< 0x00100000 */

+#define HRTIM_RST2R_TIMEVNT9          HRTIM_RST2R_TIMEVNT9_Msk                 /*!< Timer event 9 */

+

+#define HRTIM_RST2R_EXTVNT1_Pos       (21U)

+#define HRTIM_RST2R_EXTVNT1_Msk       (0x1UL << HRTIM_RST2R_EXTVNT1_Pos)       /*!< 0x00200000 */

+#define HRTIM_RST2R_EXTVNT1           HRTIM_RST2R_EXTVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_RST2R_EXTVNT2_Pos       (22U)

+#define HRTIM_RST2R_EXTVNT2_Msk       (0x1UL << HRTIM_RST2R_EXTVNT2_Pos)       /*!< 0x00400000 */

+#define HRTIM_RST2R_EXTVNT2           HRTIM_RST2R_EXTVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_RST2R_EXTVNT3_Pos       (23U)

+#define HRTIM_RST2R_EXTVNT3_Msk       (0x1UL << HRTIM_RST2R_EXTVNT3_Pos)       /*!< 0x00800000 */

+#define HRTIM_RST2R_EXTVNT3           HRTIM_RST2R_EXTVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_RST2R_EXTVNT4_Pos       (24U)

+#define HRTIM_RST2R_EXTVNT4_Msk       (0x1UL << HRTIM_RST2R_EXTVNT4_Pos)       /*!< 0x01000000 */

+#define HRTIM_RST2R_EXTVNT4           HRTIM_RST2R_EXTVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_RST2R_EXTVNT5_Pos       (25U)

+#define HRTIM_RST2R_EXTVNT5_Msk       (0x1UL << HRTIM_RST2R_EXTVNT5_Pos)       /*!< 0x02000000 */

+#define HRTIM_RST2R_EXTVNT5           HRTIM_RST2R_EXTVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_RST2R_EXTVNT6_Pos       (26U)

+#define HRTIM_RST2R_EXTVNT6_Msk       (0x1UL << HRTIM_RST2R_EXTVNT6_Pos)       /*!< 0x04000000 */

+#define HRTIM_RST2R_EXTVNT6           HRTIM_RST2R_EXTVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_RST2R_EXTVNT7_Pos       (27U)

+#define HRTIM_RST2R_EXTVNT7_Msk       (0x1UL << HRTIM_RST2R_EXTVNT7_Pos)       /*!< 0x08000000 */

+#define HRTIM_RST2R_EXTVNT7           HRTIM_RST2R_EXTVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_RST2R_EXTVNT8_Pos       (28U)

+#define HRTIM_RST2R_EXTVNT8_Msk       (0x1UL << HRTIM_RST2R_EXTVNT8_Pos)       /*!< 0x10000000 */

+#define HRTIM_RST2R_EXTVNT8           HRTIM_RST2R_EXTVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_RST2R_EXTVNT9_Pos       (29U)

+#define HRTIM_RST2R_EXTVNT9_Msk       (0x1UL << HRTIM_RST2R_EXTVNT9_Pos)       /*!< 0x20000000 */

+#define HRTIM_RST2R_EXTVNT9           HRTIM_RST2R_EXTVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_RST2R_EXTVNT10_Pos      (30U)

+#define HRTIM_RST2R_EXTVNT10_Msk      (0x1UL << HRTIM_RST2R_EXTVNT10_Pos)      /*!< 0x40000000 */

+#define HRTIM_RST2R_EXTVNT10          HRTIM_RST2R_EXTVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_RST2R_UPDATE_Pos        (31U)

+#define HRTIM_RST2R_UPDATE_Msk        (0x1UL << HRTIM_RST2R_UPDATE_Pos)        /*!< 0x80000000 */

+#define HRTIM_RST2R_UPDATE            HRTIM_RST2R_UPDATE_Msk                   /*!< Register update (transfer preload to active) */

+

+/**** Bit definition for Slave external event filtering  register 1 ***********/

+#define HRTIM_EEFR1_EE1LTCH_Pos       (0U)

+#define HRTIM_EEFR1_EE1LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos)       /*!< 0x00000001 */

+#define HRTIM_EEFR1_EE1LTCH           HRTIM_EEFR1_EE1LTCH_Msk                  /*!< External Event 1 latch */

+#define HRTIM_EEFR1_EE1FLTR_Pos       (1U)

+#define HRTIM_EEFR1_EE1FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos)       /*!< 0x0000001E */

+#define HRTIM_EEFR1_EE1FLTR           HRTIM_EEFR1_EE1FLTR_Msk                  /*!< External Event 1 filter mask */

+#define HRTIM_EEFR1_EE1FLTR_0         (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000002 */

+#define HRTIM_EEFR1_EE1FLTR_1         (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000004 */

+#define HRTIM_EEFR1_EE1FLTR_2         (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000008 */

+#define HRTIM_EEFR1_EE1FLTR_3         (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos)        /*!< 0x00000010 */

+

+#define HRTIM_EEFR1_EE2LTCH_Pos       (6U)

+#define HRTIM_EEFR1_EE2LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos)       /*!< 0x00000040 */

+#define HRTIM_EEFR1_EE2LTCH           HRTIM_EEFR1_EE2LTCH_Msk                  /*!< External Event 2 latch */

+#define HRTIM_EEFR1_EE2FLTR_Pos       (7U)

+#define HRTIM_EEFR1_EE2FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos)       /*!< 0x00000780 */

+#define HRTIM_EEFR1_EE2FLTR           HRTIM_EEFR1_EE2FLTR_Msk                  /*!< External Event 2 filter mask */

+#define HRTIM_EEFR1_EE2FLTR_0         (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000080 */

+#define HRTIM_EEFR1_EE2FLTR_1         (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000100 */

+#define HRTIM_EEFR1_EE2FLTR_2         (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000200 */

+#define HRTIM_EEFR1_EE2FLTR_3         (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos)        /*!< 0x00000400 */

+

+#define HRTIM_EEFR1_EE3LTCH_Pos       (12U)

+#define HRTIM_EEFR1_EE3LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos)       /*!< 0x00001000 */

+#define HRTIM_EEFR1_EE3LTCH           HRTIM_EEFR1_EE3LTCH_Msk                  /*!< External Event 3 latch */

+#define HRTIM_EEFR1_EE3FLTR_Pos       (13U)

+#define HRTIM_EEFR1_EE3FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos)       /*!< 0x0001E000 */

+#define HRTIM_EEFR1_EE3FLTR           HRTIM_EEFR1_EE3FLTR_Msk                  /*!< External Event 3 filter mask */

+#define HRTIM_EEFR1_EE3FLTR_0         (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00002000 */

+#define HRTIM_EEFR1_EE3FLTR_1         (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00004000 */

+#define HRTIM_EEFR1_EE3FLTR_2         (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00008000 */

+#define HRTIM_EEFR1_EE3FLTR_3         (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos)        /*!< 0x00010000 */

+

+#define HRTIM_EEFR1_EE4LTCH_Pos       (18U)

+#define HRTIM_EEFR1_EE4LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos)       /*!< 0x00040000 */

+#define HRTIM_EEFR1_EE4LTCH           HRTIM_EEFR1_EE4LTCH_Msk                  /*!< External Event 4 latch */

+#define HRTIM_EEFR1_EE4FLTR_Pos       (19U)

+#define HRTIM_EEFR1_EE4FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos)       /*!< 0x00780000 */

+#define HRTIM_EEFR1_EE4FLTR           HRTIM_EEFR1_EE4FLTR_Msk                  /*!< External Event 4 filter mask */

+#define HRTIM_EEFR1_EE4FLTR_0         (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00080000 */

+#define HRTIM_EEFR1_EE4FLTR_1         (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00100000 */

+#define HRTIM_EEFR1_EE4FLTR_2         (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00200000 */

+#define HRTIM_EEFR1_EE4FLTR_3         (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos)        /*!< 0x00400000 */

+

+#define HRTIM_EEFR1_EE5LTCH_Pos       (24U)

+#define HRTIM_EEFR1_EE5LTCH_Msk       (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos)       /*!< 0x01000000 */

+#define HRTIM_EEFR1_EE5LTCH           HRTIM_EEFR1_EE5LTCH_Msk                  /*!< External Event 5 latch */

+#define HRTIM_EEFR1_EE5FLTR_Pos       (25U)

+#define HRTIM_EEFR1_EE5FLTR_Msk       (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos)       /*!< 0x1E000000 */

+#define HRTIM_EEFR1_EE5FLTR           HRTIM_EEFR1_EE5FLTR_Msk                  /*!< External Event 5 filter mask */

+#define HRTIM_EEFR1_EE5FLTR_0         (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x02000000 */

+#define HRTIM_EEFR1_EE5FLTR_1         (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x04000000 */

+#define HRTIM_EEFR1_EE5FLTR_2         (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x08000000 */

+#define HRTIM_EEFR1_EE5FLTR_3         (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos)        /*!< 0x10000000 */

+

+/**** Bit definition for Slave external event filtering  register 2 ***********/

+#define HRTIM_EEFR2_EE6LTCH_Pos       (0U)

+#define HRTIM_EEFR2_EE6LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos)       /*!< 0x00000001 */

+#define HRTIM_EEFR2_EE6LTCH           HRTIM_EEFR2_EE6LTCH_Msk                  /*!< External Event 6 latch */

+#define HRTIM_EEFR2_EE6FLTR_Pos       (1U)

+#define HRTIM_EEFR2_EE6FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos)       /*!< 0x0000001E */

+#define HRTIM_EEFR2_EE6FLTR           HRTIM_EEFR2_EE6FLTR_Msk                  /*!< External Event 6 filter mask */

+#define HRTIM_EEFR2_EE6FLTR_0         (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000002 */

+#define HRTIM_EEFR2_EE6FLTR_1         (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000004 */

+#define HRTIM_EEFR2_EE6FLTR_2         (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000008 */

+#define HRTIM_EEFR2_EE6FLTR_3         (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos)        /*!< 0x00000010 */

+

+#define HRTIM_EEFR2_EE7LTCH_Pos       (6U)

+#define HRTIM_EEFR2_EE7LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos)       /*!< 0x00000040 */

+#define HRTIM_EEFR2_EE7LTCH           HRTIM_EEFR2_EE7LTCH_Msk                  /*!< External Event 7 latch */

+#define HRTIM_EEFR2_EE7FLTR_Pos       (7U)

+#define HRTIM_EEFR2_EE7FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos)       /*!< 0x00000780 */

+#define HRTIM_EEFR2_EE7FLTR           HRTIM_EEFR2_EE7FLTR_Msk                  /*!< External Event 7 filter mask */

+#define HRTIM_EEFR2_EE7FLTR_0         (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000080 */

+#define HRTIM_EEFR2_EE7FLTR_1         (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000100 */

+#define HRTIM_EEFR2_EE7FLTR_2         (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000200 */

+#define HRTIM_EEFR2_EE7FLTR_3         (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos)        /*!< 0x00000400 */

+

+#define HRTIM_EEFR2_EE8LTCH_Pos       (12U)

+#define HRTIM_EEFR2_EE8LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos)       /*!< 0x00001000 */

+#define HRTIM_EEFR2_EE8LTCH           HRTIM_EEFR2_EE8LTCH_Msk                  /*!< External Event 8 latch */

+#define HRTIM_EEFR2_EE8FLTR_Pos       (13U)

+#define HRTIM_EEFR2_EE8FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos)       /*!< 0x0001E000 */

+#define HRTIM_EEFR2_EE8FLTR           HRTIM_EEFR2_EE8FLTR_Msk                  /*!< External Event 8 filter mask */

+#define HRTIM_EEFR2_EE8FLTR_0         (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00002000 */

+#define HRTIM_EEFR2_EE8FLTR_1         (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00004000 */

+#define HRTIM_EEFR2_EE8FLTR_2         (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00008000 */

+#define HRTIM_EEFR2_EE8FLTR_3         (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos)        /*!< 0x00010000 */

+

+#define HRTIM_EEFR2_EE9LTCH_Pos       (18U)

+#define HRTIM_EEFR2_EE9LTCH_Msk       (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos)       /*!< 0x00040000 */

+#define HRTIM_EEFR2_EE9LTCH           HRTIM_EEFR2_EE9LTCH_Msk                  /*!< External Event 9 latch */

+#define HRTIM_EEFR2_EE9FLTR_Pos       (19U)

+#define HRTIM_EEFR2_EE9FLTR_Msk       (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos)       /*!< 0x00780000 */

+#define HRTIM_EEFR2_EE9FLTR           HRTIM_EEFR2_EE9FLTR_Msk                  /*!< External Event 9 filter mask */

+#define HRTIM_EEFR2_EE9FLTR_0         (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00080000 */

+#define HRTIM_EEFR2_EE9FLTR_1         (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00100000 */

+#define HRTIM_EEFR2_EE9FLTR_2         (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00200000 */

+#define HRTIM_EEFR2_EE9FLTR_3         (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos)        /*!< 0x00400000 */

+

+#define HRTIM_EEFR2_EE10LTCH_Pos      (24U)

+#define HRTIM_EEFR2_EE10LTCH_Msk      (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos)      /*!< 0x01000000 */

+#define HRTIM_EEFR2_EE10LTCH          HRTIM_EEFR2_EE10LTCH_Msk                 /*!< External Event 10 latch */

+#define HRTIM_EEFR2_EE10FLTR_Pos      (25U)

+#define HRTIM_EEFR2_EE10FLTR_Msk      (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos)      /*!< 0x1E000000 */

+#define HRTIM_EEFR2_EE10FLTR          HRTIM_EEFR2_EE10FLTR_Msk                 /*!< External Event 10 filter mask */

+#define HRTIM_EEFR2_EE10FLTR_0        (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x02000000 */

+#define HRTIM_EEFR2_EE10FLTR_1        (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x04000000 */

+#define HRTIM_EEFR2_EE10FLTR_2        (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x08000000 */

+#define HRTIM_EEFR2_EE10FLTR_3        (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos)       /*!< 0x10000000 */

+

+/**** Bit definition for Slave Timer reset register ***************************/

+#define HRTIM_RSTR_UPDATE_Pos         (1U)

+#define HRTIM_RSTR_UPDATE_Msk         (0x1UL << HRTIM_RSTR_UPDATE_Pos)         /*!< 0x00000002 */

+#define HRTIM_RSTR_UPDATE             HRTIM_RSTR_UPDATE_Msk                    /*!< Timer update */

+#define HRTIM_RSTR_CMP2_Pos           (2U)

+#define HRTIM_RSTR_CMP2_Msk           (0x1UL << HRTIM_RSTR_CMP2_Pos)           /*!< 0x00000004 */

+#define HRTIM_RSTR_CMP2               HRTIM_RSTR_CMP2_Msk                      /*!< Timer compare2 */

+#define HRTIM_RSTR_CMP4_Pos           (3U)

+#define HRTIM_RSTR_CMP4_Msk           (0x1UL << HRTIM_RSTR_CMP4_Pos)           /*!< 0x00000008 */

+#define HRTIM_RSTR_CMP4               HRTIM_RSTR_CMP4_Msk                      /*!< Timer compare4 */

+

+#define HRTIM_RSTR_MSTPER_Pos         (4U)

+#define HRTIM_RSTR_MSTPER_Msk         (0x1UL << HRTIM_RSTR_MSTPER_Pos)         /*!< 0x00000010 */

+#define HRTIM_RSTR_MSTPER             HRTIM_RSTR_MSTPER_Msk                    /*!< Master period */

+#define HRTIM_RSTR_MSTCMP1_Pos        (5U)

+#define HRTIM_RSTR_MSTCMP1_Msk        (0x1UL << HRTIM_RSTR_MSTCMP1_Pos)        /*!< 0x00000020 */

+#define HRTIM_RSTR_MSTCMP1            HRTIM_RSTR_MSTCMP1_Msk                   /*!< Master compare1 */

+#define HRTIM_RSTR_MSTCMP2_Pos        (6U)

+#define HRTIM_RSTR_MSTCMP2_Msk        (0x1UL << HRTIM_RSTR_MSTCMP2_Pos)        /*!< 0x00000040 */

+#define HRTIM_RSTR_MSTCMP2            HRTIM_RSTR_MSTCMP2_Msk                   /*!< Master compare2 */

+#define HRTIM_RSTR_MSTCMP3_Pos        (7U)

+#define HRTIM_RSTR_MSTCMP3_Msk        (0x1UL << HRTIM_RSTR_MSTCMP3_Pos)        /*!< 0x00000080 */

+#define HRTIM_RSTR_MSTCMP3            HRTIM_RSTR_MSTCMP3_Msk                   /*!< Master compare3 */

+#define HRTIM_RSTR_MSTCMP4_Pos        (8U)

+#define HRTIM_RSTR_MSTCMP4_Msk        (0x1UL << HRTIM_RSTR_MSTCMP4_Pos)        /*!< 0x00000100 */

+#define HRTIM_RSTR_MSTCMP4            HRTIM_RSTR_MSTCMP4_Msk                   /*!< Master compare4 */

+

+#define HRTIM_RSTR_EXTEVNT1_Pos       (9U)

+#define HRTIM_RSTR_EXTEVNT1_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos)       /*!< 0x00000200 */

+#define HRTIM_RSTR_EXTEVNT1           HRTIM_RSTR_EXTEVNT1_Msk                  /*!< External event 1 */

+#define HRTIM_RSTR_EXTEVNT2_Pos       (10U)

+#define HRTIM_RSTR_EXTEVNT2_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos)       /*!< 0x00000400 */

+#define HRTIM_RSTR_EXTEVNT2           HRTIM_RSTR_EXTEVNT2_Msk                  /*!< External event 2 */

+#define HRTIM_RSTR_EXTEVNT3_Pos       (11U)

+#define HRTIM_RSTR_EXTEVNT3_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos)       /*!< 0x00000800 */

+#define HRTIM_RSTR_EXTEVNT3           HRTIM_RSTR_EXTEVNT3_Msk                  /*!< External event 3 */

+#define HRTIM_RSTR_EXTEVNT4_Pos       (12U)

+#define HRTIM_RSTR_EXTEVNT4_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos)       /*!< 0x00001000 */

+#define HRTIM_RSTR_EXTEVNT4           HRTIM_RSTR_EXTEVNT4_Msk                  /*!< External event 4 */

+#define HRTIM_RSTR_EXTEVNT5_Pos       (13U)

+#define HRTIM_RSTR_EXTEVNT5_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos)       /*!< 0x00002000 */

+#define HRTIM_RSTR_EXTEVNT5           HRTIM_RSTR_EXTEVNT5_Msk                  /*!< External event 5 */

+#define HRTIM_RSTR_EXTEVNT6_Pos       (14U)

+#define HRTIM_RSTR_EXTEVNT6_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos)       /*!< 0x00004000 */

+#define HRTIM_RSTR_EXTEVNT6           HRTIM_RSTR_EXTEVNT6_Msk                  /*!< External event 6 */

+#define HRTIM_RSTR_EXTEVNT7_Pos       (15U)

+#define HRTIM_RSTR_EXTEVNT7_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos)       /*!< 0x00008000 */

+#define HRTIM_RSTR_EXTEVNT7           HRTIM_RSTR_EXTEVNT7_Msk                  /*!< External event 7 */

+#define HRTIM_RSTR_EXTEVNT8_Pos       (16U)

+#define HRTIM_RSTR_EXTEVNT8_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos)       /*!< 0x00010000 */

+#define HRTIM_RSTR_EXTEVNT8           HRTIM_RSTR_EXTEVNT8_Msk                  /*!< External event 8 */

+#define HRTIM_RSTR_EXTEVNT9_Pos       (17U)

+#define HRTIM_RSTR_EXTEVNT9_Msk       (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos)       /*!< 0x00020000 */

+#define HRTIM_RSTR_EXTEVNT9           HRTIM_RSTR_EXTEVNT9_Msk                  /*!< External event 9 */

+#define HRTIM_RSTR_EXTEVNT10_Pos      (18U)

+#define HRTIM_RSTR_EXTEVNT10_Msk      (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos)      /*!< 0x00040000 */

+#define HRTIM_RSTR_EXTEVNT10          HRTIM_RSTR_EXTEVNT10_Msk                 /*!< External event 10 */

+

+#define HRTIM_RSTR_TIMBCMP1_Pos       (19U)

+#define HRTIM_RSTR_TIMBCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos)       /*!< 0x00080000 */

+#define HRTIM_RSTR_TIMBCMP1           HRTIM_RSTR_TIMBCMP1_Msk                  /*!< Timer B compare 1 */

+#define HRTIM_RSTR_TIMBCMP2_Pos       (20U)

+#define HRTIM_RSTR_TIMBCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos)       /*!< 0x00100000 */

+#define HRTIM_RSTR_TIMBCMP2           HRTIM_RSTR_TIMBCMP2_Msk                  /*!< Timer B compare 2 */

+#define HRTIM_RSTR_TIMBCMP4_Pos       (21U)

+#define HRTIM_RSTR_TIMBCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos)       /*!< 0x00200000 */

+#define HRTIM_RSTR_TIMBCMP4           HRTIM_RSTR_TIMBCMP4_Msk                  /*!< Timer B compare 4 */

+

+#define HRTIM_RSTR_TIMCCMP1_Pos       (22U)

+#define HRTIM_RSTR_TIMCCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos)       /*!< 0x00400000 */

+#define HRTIM_RSTR_TIMCCMP1           HRTIM_RSTR_TIMCCMP1_Msk                  /*!< Timer C compare 1 */

+#define HRTIM_RSTR_TIMCCMP2_Pos       (23U)

+#define HRTIM_RSTR_TIMCCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos)       /*!< 0x00800000 */

+#define HRTIM_RSTR_TIMCCMP2           HRTIM_RSTR_TIMCCMP2_Msk                  /*!< Timer C compare 2 */

+#define HRTIM_RSTR_TIMCCMP4_Pos       (24U)

+#define HRTIM_RSTR_TIMCCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos)       /*!< 0x01000000 */

+#define HRTIM_RSTR_TIMCCMP4           HRTIM_RSTR_TIMCCMP4_Msk                  /*!< Timer C compare 4 */

+

+#define HRTIM_RSTR_TIMDCMP1_Pos       (25U)

+#define HRTIM_RSTR_TIMDCMP1_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos)       /*!< 0x02000000 */

+#define HRTIM_RSTR_TIMDCMP1           HRTIM_RSTR_TIMDCMP1_Msk                  /*!< Timer D compare 1 */

+#define HRTIM_RSTR_TIMDCMP2_Pos       (26U)

+#define HRTIM_RSTR_TIMDCMP2_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos)       /*!< 0x04000000 */

+#define HRTIM_RSTR_TIMDCMP2           HRTIM_RSTR_TIMDCMP2_Msk                  /*!< Timer D compare 2 */

+#define HRTIM_RSTR_TIMDCMP4_Pos       (27U)

+#define HRTIM_RSTR_TIMDCMP4_Msk       (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos)       /*!< 0x08000000 */

+#define HRTIM_RSTR_TIMDCMP4           HRTIM_RSTR_TIMDCMP4_Msk                  /*!< Timer D compare 4 */

+

+#define HRTIM_RSTR_TIMECMP1_Pos       (28U)

+#define HRTIM_RSTR_TIMECMP1_Msk       (0x1UL << HRTIM_RSTR_TIMECMP1_Pos)       /*!< 0x10000000 */

+#define HRTIM_RSTR_TIMECMP1           HRTIM_RSTR_TIMECMP1_Msk                  /*!< Timer E compare 1 */

+#define HRTIM_RSTR_TIMECMP2_Pos       (29U)

+#define HRTIM_RSTR_TIMECMP2_Msk       (0x1UL << HRTIM_RSTR_TIMECMP2_Pos)       /*!< 0x20000000 */

+#define HRTIM_RSTR_TIMECMP2           HRTIM_RSTR_TIMECMP2_Msk                  /*!< Timer E compare 2 */

+#define HRTIM_RSTR_TIMECMP4_Pos       (30U)

+#define HRTIM_RSTR_TIMECMP4_Msk       (0x1UL << HRTIM_RSTR_TIMECMP4_Pos)       /*!< 0x40000000 */

+#define HRTIM_RSTR_TIMECMP4           HRTIM_RSTR_TIMECMP4_Msk                  /*!< Timer E compare 4 */

+

+/**** Bit definition for Slave Timer Chopper register *************************/

+#define HRTIM_CHPR_CARFRQ_Pos         (0U)

+#define HRTIM_CHPR_CARFRQ_Msk         (0xFUL << HRTIM_CHPR_CARFRQ_Pos)         /*!< 0x0000000F */

+#define HRTIM_CHPR_CARFRQ             HRTIM_CHPR_CARFRQ_Msk                    /*!< Timer carrier frequency value */

+#define HRTIM_CHPR_CARFRQ_0           (0x1UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000001 */

+#define HRTIM_CHPR_CARFRQ_1           (0x2UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000002 */

+#define HRTIM_CHPR_CARFRQ_2           (0x4UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000004 */

+#define HRTIM_CHPR_CARFRQ_3           (0x8UL << HRTIM_CHPR_CARFRQ_Pos)          /*!< 0x00000008 */

+

+#define HRTIM_CHPR_CARDTY_Pos         (4U)

+#define HRTIM_CHPR_CARDTY_Msk         (0x7UL << HRTIM_CHPR_CARDTY_Pos)         /*!< 0x00000070 */

+#define HRTIM_CHPR_CARDTY             HRTIM_CHPR_CARDTY_Msk                    /*!< Timer chopper duty cycle value */

+#define HRTIM_CHPR_CARDTY_0           (0x1UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000010 */

+#define HRTIM_CHPR_CARDTY_1           (0x2UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000020 */

+#define HRTIM_CHPR_CARDTY_2           (0x4UL << HRTIM_CHPR_CARDTY_Pos)          /*!< 0x00000040 */

+

+#define HRTIM_CHPR_STRPW_Pos          (7U)

+#define HRTIM_CHPR_STRPW_Msk          (0xFUL << HRTIM_CHPR_STRPW_Pos)          /*!< 0x00000780 */

+#define HRTIM_CHPR_STRPW              HRTIM_CHPR_STRPW_Msk                     /*!< Timer start pulse width value */

+#define HRTIM_CHPR_STRPW_0            (0x1UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000080 */

+#define HRTIM_CHPR_STRPW_1            (0x2UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000100 */

+#define HRTIM_CHPR_STRPW_2            (0x4UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000200 */

+#define HRTIM_CHPR_STRPW_3            (0x8UL << HRTIM_CHPR_STRPW_Pos)           /*!< 0x00000400 */

+

+/**** Bit definition for Slave Timer Capture 1 control register ***************/

+#define HRTIM_CPT1CR_SWCPT_Pos        (0U)

+#define HRTIM_CPT1CR_SWCPT_Msk        (0x1UL << HRTIM_CPT1CR_SWCPT_Pos)        /*!< 0x00000001 */

+#define HRTIM_CPT1CR_SWCPT            HRTIM_CPT1CR_SWCPT_Msk                   /*!< Software capture */

+#define HRTIM_CPT1CR_UPDCPT_Pos       (1U)

+#define HRTIM_CPT1CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos)       /*!< 0x00000002 */

+#define HRTIM_CPT1CR_UPDCPT           HRTIM_CPT1CR_UPDCPT_Msk                  /*!< Update capture */

+#define HRTIM_CPT1CR_EXEV1CPT_Pos     (2U)

+#define HRTIM_CPT1CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos)     /*!< 0x00000004 */

+#define HRTIM_CPT1CR_EXEV1CPT         HRTIM_CPT1CR_EXEV1CPT_Msk                /*!< External event 1 capture */

+#define HRTIM_CPT1CR_EXEV2CPT_Pos     (3U)

+#define HRTIM_CPT1CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos)     /*!< 0x00000008 */

+#define HRTIM_CPT1CR_EXEV2CPT         HRTIM_CPT1CR_EXEV2CPT_Msk                /*!< External event 2 capture */

+#define HRTIM_CPT1CR_EXEV3CPT_Pos     (4U)

+#define HRTIM_CPT1CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos)     /*!< 0x00000010 */

+#define HRTIM_CPT1CR_EXEV3CPT         HRTIM_CPT1CR_EXEV3CPT_Msk                /*!< External event 3 capture */

+#define HRTIM_CPT1CR_EXEV4CPT_Pos     (5U)

+#define HRTIM_CPT1CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos)     /*!< 0x00000020 */

+#define HRTIM_CPT1CR_EXEV4CPT         HRTIM_CPT1CR_EXEV4CPT_Msk                /*!< External event 4 capture */

+#define HRTIM_CPT1CR_EXEV5CPT_Pos     (6U)

+#define HRTIM_CPT1CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos)     /*!< 0x00000040 */

+#define HRTIM_CPT1CR_EXEV5CPT         HRTIM_CPT1CR_EXEV5CPT_Msk                /*!< External event 5 capture */

+#define HRTIM_CPT1CR_EXEV6CPT_Pos     (7U)

+#define HRTIM_CPT1CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos)     /*!< 0x00000080 */

+#define HRTIM_CPT1CR_EXEV6CPT         HRTIM_CPT1CR_EXEV6CPT_Msk                /*!< External event 6 capture */

+#define HRTIM_CPT1CR_EXEV7CPT_Pos     (8U)

+#define HRTIM_CPT1CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos)     /*!< 0x00000100 */

+#define HRTIM_CPT1CR_EXEV7CPT         HRTIM_CPT1CR_EXEV7CPT_Msk                /*!< External event 7 capture */

+#define HRTIM_CPT1CR_EXEV8CPT_Pos     (9U)

+#define HRTIM_CPT1CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos)     /*!< 0x00000200 */

+#define HRTIM_CPT1CR_EXEV8CPT         HRTIM_CPT1CR_EXEV8CPT_Msk                /*!< External event 8 capture */

+#define HRTIM_CPT1CR_EXEV9CPT_Pos     (10U)

+#define HRTIM_CPT1CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos)     /*!< 0x00000400 */

+#define HRTIM_CPT1CR_EXEV9CPT         HRTIM_CPT1CR_EXEV9CPT_Msk                /*!< External event 9 capture */

+#define HRTIM_CPT1CR_EXEV10CPT_Pos    (11U)

+#define HRTIM_CPT1CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos)    /*!< 0x00000800 */

+#define HRTIM_CPT1CR_EXEV10CPT        HRTIM_CPT1CR_EXEV10CPT_Msk               /*!< External event 10 capture */

+

+#define HRTIM_CPT1CR_TA1SET_Pos       (12U)

+#define HRTIM_CPT1CR_TA1SET_Msk       (0x1UL << HRTIM_CPT1CR_TA1SET_Pos)       /*!< 0x00001000 */

+#define HRTIM_CPT1CR_TA1SET           HRTIM_CPT1CR_TA1SET_Msk                  /*!< Timer A output 1 set */

+#define HRTIM_CPT1CR_TA1RST_Pos       (13U)

+#define HRTIM_CPT1CR_TA1RST_Msk       (0x1UL << HRTIM_CPT1CR_TA1RST_Pos)       /*!< 0x00002000 */

+#define HRTIM_CPT1CR_TA1RST           HRTIM_CPT1CR_TA1RST_Msk                  /*!< Timer A output 1 reset */

+#define HRTIM_CPT1CR_TIMACMP1_Pos     (14U)

+#define HRTIM_CPT1CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos)     /*!< 0x00004000 */

+#define HRTIM_CPT1CR_TIMACMP1         HRTIM_CPT1CR_TIMACMP1_Msk                /*!< Timer A compare 1 */

+#define HRTIM_CPT1CR_TIMACMP2_Pos     (15U)

+#define HRTIM_CPT1CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos)     /*!< 0x00008000 */

+#define HRTIM_CPT1CR_TIMACMP2         HRTIM_CPT1CR_TIMACMP2_Msk                /*!< Timer A compare 2 */

+

+#define HRTIM_CPT1CR_TB1SET_Pos       (16U)

+#define HRTIM_CPT1CR_TB1SET_Msk       (0x1UL << HRTIM_CPT1CR_TB1SET_Pos)       /*!< 0x00010000 */

+#define HRTIM_CPT1CR_TB1SET           HRTIM_CPT1CR_TB1SET_Msk                  /*!< Timer B output 1 set */

+#define HRTIM_CPT1CR_TB1RST_Pos       (17U)

+#define HRTIM_CPT1CR_TB1RST_Msk       (0x1UL << HRTIM_CPT1CR_TB1RST_Pos)       /*!< 0x00020000 */

+#define HRTIM_CPT1CR_TB1RST           HRTIM_CPT1CR_TB1RST_Msk                  /*!< Timer B output 1 reset */

+#define HRTIM_CPT1CR_TIMBCMP1_Pos     (18U)

+#define HRTIM_CPT1CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos)     /*!< 0x00040000 */

+#define HRTIM_CPT1CR_TIMBCMP1         HRTIM_CPT1CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */

+#define HRTIM_CPT1CR_TIMBCMP2_Pos     (19U)

+#define HRTIM_CPT1CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos)     /*!< 0x00080000 */

+#define HRTIM_CPT1CR_TIMBCMP2         HRTIM_CPT1CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */

+

+#define HRTIM_CPT1CR_TC1SET_Pos       (20U)

+#define HRTIM_CPT1CR_TC1SET_Msk       (0x1UL << HRTIM_CPT1CR_TC1SET_Pos)       /*!< 0x00100000 */

+#define HRTIM_CPT1CR_TC1SET           HRTIM_CPT1CR_TC1SET_Msk                  /*!< Timer C output 1 set */

+#define HRTIM_CPT1CR_TC1RST_Pos       (21U)

+#define HRTIM_CPT1CR_TC1RST_Msk       (0x1UL << HRTIM_CPT1CR_TC1RST_Pos)       /*!< 0x00200000 */

+#define HRTIM_CPT1CR_TC1RST           HRTIM_CPT1CR_TC1RST_Msk                  /*!< Timer C output 1 reset */

+#define HRTIM_CPT1CR_TIMCCMP1_Pos     (22U)

+#define HRTIM_CPT1CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos)     /*!< 0x00400000 */

+#define HRTIM_CPT1CR_TIMCCMP1         HRTIM_CPT1CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */

+#define HRTIM_CPT1CR_TIMCCMP2_Pos     (23U)

+#define HRTIM_CPT1CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos)     /*!< 0x00800000 */

+#define HRTIM_CPT1CR_TIMCCMP2         HRTIM_CPT1CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */

+

+#define HRTIM_CPT1CR_TD1SET_Pos       (24U)

+#define HRTIM_CPT1CR_TD1SET_Msk       (0x1UL << HRTIM_CPT1CR_TD1SET_Pos)       /*!< 0x01000000 */

+#define HRTIM_CPT1CR_TD1SET           HRTIM_CPT1CR_TD1SET_Msk                  /*!< Timer D output 1 set */

+#define HRTIM_CPT1CR_TD1RST_Pos       (25U)

+#define HRTIM_CPT1CR_TD1RST_Msk       (0x1UL << HRTIM_CPT1CR_TD1RST_Pos)       /*!< 0x02000000 */

+#define HRTIM_CPT1CR_TD1RST           HRTIM_CPT1CR_TD1RST_Msk                  /*!< Timer D output 1 reset */

+#define HRTIM_CPT1CR_TIMDCMP1_Pos     (26U)

+#define HRTIM_CPT1CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos)     /*!< 0x04000000 */

+#define HRTIM_CPT1CR_TIMDCMP1         HRTIM_CPT1CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */

+#define HRTIM_CPT1CR_TIMDCMP2_Pos     (27U)

+#define HRTIM_CPT1CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos)     /*!< 0x08000000 */

+#define HRTIM_CPT1CR_TIMDCMP2         HRTIM_CPT1CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */

+

+#define HRTIM_CPT1CR_TE1SET_Pos       (28U)

+#define HRTIM_CPT1CR_TE1SET_Msk       (0x1UL << HRTIM_CPT1CR_TE1SET_Pos)       /*!< 0x10000000 */

+#define HRTIM_CPT1CR_TE1SET           HRTIM_CPT1CR_TE1SET_Msk                  /*!< Timer E output 1 set */

+#define HRTIM_CPT1CR_TE1RST_Pos       (29U)

+#define HRTIM_CPT1CR_TE1RST_Msk       (0x1UL << HRTIM_CPT1CR_TE1RST_Pos)       /*!< 0x20000000 */

+#define HRTIM_CPT1CR_TE1RST           HRTIM_CPT1CR_TE1RST_Msk                  /*!< Timer E output 1 reset */

+#define HRTIM_CPT1CR_TIMECMP1_Pos     (30U)

+#define HRTIM_CPT1CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos)     /*!< 0x40000000 */

+#define HRTIM_CPT1CR_TIMECMP1         HRTIM_CPT1CR_TIMECMP1_Msk                /*!< Timer E compare 1 */

+#define HRTIM_CPT1CR_TIMECMP2_Pos     (31U)

+#define HRTIM_CPT1CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos)     /*!< 0x80000000 */

+#define HRTIM_CPT1CR_TIMECMP2         HRTIM_CPT1CR_TIMECMP2_Msk                /*!< Timer E compare 2 */

+

+/**** Bit definition for Slave Timer Capture 2 control register ***************/

+#define HRTIM_CPT2CR_SWCPT_Pos        (0U)

+#define HRTIM_CPT2CR_SWCPT_Msk        (0x1UL << HRTIM_CPT2CR_SWCPT_Pos)        /*!< 0x00000001 */

+#define HRTIM_CPT2CR_SWCPT            HRTIM_CPT2CR_SWCPT_Msk                   /*!< Software capture */

+#define HRTIM_CPT2CR_UPDCPT_Pos       (1U)

+#define HRTIM_CPT2CR_UPDCPT_Msk       (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos)       /*!< 0x00000002 */

+#define HRTIM_CPT2CR_UPDCPT           HRTIM_CPT2CR_UPDCPT_Msk                  /*!< Update capture */

+#define HRTIM_CPT2CR_EXEV1CPT_Pos     (2U)

+#define HRTIM_CPT2CR_EXEV1CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos)     /*!< 0x00000004 */

+#define HRTIM_CPT2CR_EXEV1CPT         HRTIM_CPT2CR_EXEV1CPT_Msk                /*!< External event 1 capture */

+#define HRTIM_CPT2CR_EXEV2CPT_Pos     (3U)

+#define HRTIM_CPT2CR_EXEV2CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos)     /*!< 0x00000008 */

+#define HRTIM_CPT2CR_EXEV2CPT         HRTIM_CPT2CR_EXEV2CPT_Msk                /*!< External event 2 capture */

+#define HRTIM_CPT2CR_EXEV3CPT_Pos     (4U)

+#define HRTIM_CPT2CR_EXEV3CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos)     /*!< 0x00000010 */

+#define HRTIM_CPT2CR_EXEV3CPT         HRTIM_CPT2CR_EXEV3CPT_Msk                /*!< External event 3 capture */

+#define HRTIM_CPT2CR_EXEV4CPT_Pos     (5U)

+#define HRTIM_CPT2CR_EXEV4CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos)     /*!< 0x00000020 */

+#define HRTIM_CPT2CR_EXEV4CPT         HRTIM_CPT2CR_EXEV4CPT_Msk                /*!< External event 4 capture */

+#define HRTIM_CPT2CR_EXEV5CPT_Pos     (6U)

+#define HRTIM_CPT2CR_EXEV5CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos)     /*!< 0x00000040 */

+#define HRTIM_CPT2CR_EXEV5CPT         HRTIM_CPT2CR_EXEV5CPT_Msk                /*!< External event 5 capture */

+#define HRTIM_CPT2CR_EXEV6CPT_Pos     (7U)

+#define HRTIM_CPT2CR_EXEV6CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos)     /*!< 0x00000080 */

+#define HRTIM_CPT2CR_EXEV6CPT         HRTIM_CPT2CR_EXEV6CPT_Msk                /*!< External event 6 capture */

+#define HRTIM_CPT2CR_EXEV7CPT_Pos     (8U)

+#define HRTIM_CPT2CR_EXEV7CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos)     /*!< 0x00000100 */

+#define HRTIM_CPT2CR_EXEV7CPT         HRTIM_CPT2CR_EXEV7CPT_Msk                /*!< External event 7 capture */

+#define HRTIM_CPT2CR_EXEV8CPT_Pos     (9U)

+#define HRTIM_CPT2CR_EXEV8CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos)     /*!< 0x00000200 */

+#define HRTIM_CPT2CR_EXEV8CPT         HRTIM_CPT2CR_EXEV8CPT_Msk                /*!< External event 8 capture */

+#define HRTIM_CPT2CR_EXEV9CPT_Pos     (10U)

+#define HRTIM_CPT2CR_EXEV9CPT_Msk     (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos)     /*!< 0x00000400 */

+#define HRTIM_CPT2CR_EXEV9CPT         HRTIM_CPT2CR_EXEV9CPT_Msk                /*!< External event 9 capture */

+#define HRTIM_CPT2CR_EXEV10CPT_Pos    (11U)

+#define HRTIM_CPT2CR_EXEV10CPT_Msk    (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos)    /*!< 0x00000800 */

+#define HRTIM_CPT2CR_EXEV10CPT        HRTIM_CPT2CR_EXEV10CPT_Msk               /*!< External event 10 capture */

+

+#define HRTIM_CPT2CR_TA1SET_Pos       (12U)

+#define HRTIM_CPT2CR_TA1SET_Msk       (0x1UL << HRTIM_CPT2CR_TA1SET_Pos)       /*!< 0x00001000 */

+#define HRTIM_CPT2CR_TA1SET           HRTIM_CPT2CR_TA1SET_Msk                  /*!< Timer A output 1 set */

+#define HRTIM_CPT2CR_TA1RST_Pos       (13U)

+#define HRTIM_CPT2CR_TA1RST_Msk       (0x1UL << HRTIM_CPT2CR_TA1RST_Pos)       /*!< 0x00002000 */

+#define HRTIM_CPT2CR_TA1RST           HRTIM_CPT2CR_TA1RST_Msk                  /*!< Timer A output 1 reset */

+#define HRTIM_CPT2CR_TIMACMP1_Pos     (14U)

+#define HRTIM_CPT2CR_TIMACMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos)     /*!< 0x00004000 */

+#define HRTIM_CPT2CR_TIMACMP1         HRTIM_CPT2CR_TIMACMP1_Msk                /*!< Timer A compare 1 */

+#define HRTIM_CPT2CR_TIMACMP2_Pos     (15U)

+#define HRTIM_CPT2CR_TIMACMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos)     /*!< 0x00008000 */

+#define HRTIM_CPT2CR_TIMACMP2         HRTIM_CPT2CR_TIMACMP2_Msk                /*!< Timer A compare 2 */

+

+#define HRTIM_CPT2CR_TB1SET_Pos       (16U)

+#define HRTIM_CPT2CR_TB1SET_Msk       (0x1UL << HRTIM_CPT2CR_TB1SET_Pos)       /*!< 0x00010000 */

+#define HRTIM_CPT2CR_TB1SET           HRTIM_CPT2CR_TB1SET_Msk                  /*!< Timer B output 1 set */

+#define HRTIM_CPT2CR_TB1RST_Pos       (17U)

+#define HRTIM_CPT2CR_TB1RST_Msk       (0x1UL << HRTIM_CPT2CR_TB1RST_Pos)       /*!< 0x00020000 */

+#define HRTIM_CPT2CR_TB1RST           HRTIM_CPT2CR_TB1RST_Msk                  /*!< Timer B output 1 reset */

+#define HRTIM_CPT2CR_TIMBCMP1_Pos     (18U)

+#define HRTIM_CPT2CR_TIMBCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos)     /*!< 0x00040000 */

+#define HRTIM_CPT2CR_TIMBCMP1         HRTIM_CPT2CR_TIMBCMP1_Msk                /*!< Timer B compare 1 */

+#define HRTIM_CPT2CR_TIMBCMP2_Pos     (19U)

+#define HRTIM_CPT2CR_TIMBCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos)     /*!< 0x00080000 */

+#define HRTIM_CPT2CR_TIMBCMP2         HRTIM_CPT2CR_TIMBCMP2_Msk                /*!< Timer B compare 2 */

+

+#define HRTIM_CPT2CR_TC1SET_Pos       (20U)

+#define HRTIM_CPT2CR_TC1SET_Msk       (0x1UL << HRTIM_CPT2CR_TC1SET_Pos)       /*!< 0x00100000 */

+#define HRTIM_CPT2CR_TC1SET           HRTIM_CPT2CR_TC1SET_Msk                  /*!< Timer C output 1 set */

+#define HRTIM_CPT2CR_TC1RST_Pos       (21U)

+#define HRTIM_CPT2CR_TC1RST_Msk       (0x1UL << HRTIM_CPT2CR_TC1RST_Pos)       /*!< 0x00200000 */

+#define HRTIM_CPT2CR_TC1RST           HRTIM_CPT2CR_TC1RST_Msk                  /*!< Timer C output 1 reset */

+#define HRTIM_CPT2CR_TIMCCMP1_Pos     (22U)

+#define HRTIM_CPT2CR_TIMCCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos)     /*!< 0x00400000 */

+#define HRTIM_CPT2CR_TIMCCMP1         HRTIM_CPT2CR_TIMCCMP1_Msk                /*!< Timer C compare 1 */

+#define HRTIM_CPT2CR_TIMCCMP2_Pos     (23U)

+#define HRTIM_CPT2CR_TIMCCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos)     /*!< 0x00800000 */

+#define HRTIM_CPT2CR_TIMCCMP2         HRTIM_CPT2CR_TIMCCMP2_Msk                /*!< Timer C compare 2 */

+

+#define HRTIM_CPT2CR_TD1SET_Pos       (24U)

+#define HRTIM_CPT2CR_TD1SET_Msk       (0x1UL << HRTIM_CPT2CR_TD1SET_Pos)       /*!< 0x01000000 */

+#define HRTIM_CPT2CR_TD1SET           HRTIM_CPT2CR_TD1SET_Msk                  /*!< Timer D output 1 set */

+#define HRTIM_CPT2CR_TD1RST_Pos       (25U)

+#define HRTIM_CPT2CR_TD1RST_Msk       (0x1UL << HRTIM_CPT2CR_TD1RST_Pos)       /*!< 0x02000000 */

+#define HRTIM_CPT2CR_TD1RST           HRTIM_CPT2CR_TD1RST_Msk                  /*!< Timer D output 1 reset */

+#define HRTIM_CPT2CR_TIMDCMP1_Pos     (26U)

+#define HRTIM_CPT2CR_TIMDCMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos)     /*!< 0x04000000 */

+#define HRTIM_CPT2CR_TIMDCMP1         HRTIM_CPT2CR_TIMDCMP1_Msk                /*!< Timer D compare 1 */

+#define HRTIM_CPT2CR_TIMDCMP2_Pos     (27U)

+#define HRTIM_CPT2CR_TIMDCMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos)     /*!< 0x08000000 */

+#define HRTIM_CPT2CR_TIMDCMP2         HRTIM_CPT2CR_TIMDCMP2_Msk                /*!< Timer D compare 2 */

+

+#define HRTIM_CPT2CR_TE1SET_Pos       (28U)

+#define HRTIM_CPT2CR_TE1SET_Msk       (0x1UL << HRTIM_CPT2CR_TE1SET_Pos)       /*!< 0x10000000 */

+#define HRTIM_CPT2CR_TE1SET           HRTIM_CPT2CR_TE1SET_Msk                  /*!< Timer E output 1 set */

+#define HRTIM_CPT2CR_TE1RST_Pos       (29U)

+#define HRTIM_CPT2CR_TE1RST_Msk       (0x1UL << HRTIM_CPT2CR_TE1RST_Pos)       /*!< 0x20000000 */

+#define HRTIM_CPT2CR_TE1RST           HRTIM_CPT2CR_TE1RST_Msk                  /*!< Timer E output 1 reset */

+#define HRTIM_CPT2CR_TIMECMP1_Pos     (30U)

+#define HRTIM_CPT2CR_TIMECMP1_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos)     /*!< 0x40000000 */

+#define HRTIM_CPT2CR_TIMECMP1         HRTIM_CPT2CR_TIMECMP1_Msk                /*!< Timer E compare 1 */

+#define HRTIM_CPT2CR_TIMECMP2_Pos     (31U)

+#define HRTIM_CPT2CR_TIMECMP2_Msk     (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos)     /*!< 0x80000000 */

+#define HRTIM_CPT2CR_TIMECMP2         HRTIM_CPT2CR_TIMECMP2_Msk                /*!< Timer E compare 2 */

+

+/**** Bit definition for Slave Timer Output register **************************/

+#define HRTIM_OUTR_POL1_Pos           (1U)

+#define HRTIM_OUTR_POL1_Msk           (0x1UL << HRTIM_OUTR_POL1_Pos)           /*!< 0x00000002 */

+#define HRTIM_OUTR_POL1               HRTIM_OUTR_POL1_Msk                      /*!< Slave output 1 polarity */

+#define HRTIM_OUTR_IDLM1_Pos          (2U)

+#define HRTIM_OUTR_IDLM1_Msk          (0x1UL << HRTIM_OUTR_IDLM1_Pos)          /*!< 0x00000004 */

+#define HRTIM_OUTR_IDLM1              HRTIM_OUTR_IDLM1_Msk                     /*!< Slave output 1 idle mode */

+#define HRTIM_OUTR_IDLES1_Pos         (3U)

+#define HRTIM_OUTR_IDLES1_Msk         (0x1UL << HRTIM_OUTR_IDLES1_Pos)         /*!< 0x00000008 */

+#define HRTIM_OUTR_IDLES1             HRTIM_OUTR_IDLES1_Msk                    /*!< Slave output 1 idle state */

+#define HRTIM_OUTR_FAULT1_Pos         (4U)

+#define HRTIM_OUTR_FAULT1_Msk         (0x3UL << HRTIM_OUTR_FAULT1_Pos)         /*!< 0x00000030 */

+#define HRTIM_OUTR_FAULT1             HRTIM_OUTR_FAULT1_Msk                    /*!< Slave output 1 fault state */

+#define HRTIM_OUTR_FAULT1_0           (0x1UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000010 */

+#define HRTIM_OUTR_FAULT1_1           (0x2UL << HRTIM_OUTR_FAULT1_Pos)          /*!< 0x00000020 */

+#define HRTIM_OUTR_CHP1_Pos           (6U)

+#define HRTIM_OUTR_CHP1_Msk           (0x1UL << HRTIM_OUTR_CHP1_Pos)           /*!< 0x00000040 */

+#define HRTIM_OUTR_CHP1               HRTIM_OUTR_CHP1_Msk                      /*!< Slave output 1 chopper enable */

+#define HRTIM_OUTR_DIDL1_Pos          (7U)

+#define HRTIM_OUTR_DIDL1_Msk          (0x1UL << HRTIM_OUTR_DIDL1_Pos)          /*!< 0x00000080 */

+#define HRTIM_OUTR_DIDL1              HRTIM_OUTR_DIDL1_Msk                     /*!< Slave output 1 dead time idle */

+

+#define HRTIM_OUTR_DTEN_Pos           (8U)

+#define HRTIM_OUTR_DTEN_Msk           (0x1UL << HRTIM_OUTR_DTEN_Pos)           /*!< 0x00000100 */

+#define HRTIM_OUTR_DTEN               HRTIM_OUTR_DTEN_Msk                      /*!< Slave output deadtime enable */

+#define HRTIM_OUTR_DLYPRTEN_Pos       (9U)

+#define HRTIM_OUTR_DLYPRTEN_Msk       (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos)       /*!< 0x00000200 */

+#define HRTIM_OUTR_DLYPRTEN           HRTIM_OUTR_DLYPRTEN_Msk                  /*!< Slave output delay protection enable */

+#define HRTIM_OUTR_DLYPRT_Pos         (10U)

+#define HRTIM_OUTR_DLYPRT_Msk         (0x7UL << HRTIM_OUTR_DLYPRT_Pos)         /*!< 0x00001C00 */

+#define HRTIM_OUTR_DLYPRT             HRTIM_OUTR_DLYPRT_Msk                    /*!< Slave output delay protection */

+#define HRTIM_OUTR_DLYPRT_0           (0x1UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000400 */

+#define HRTIM_OUTR_DLYPRT_1           (0x2UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00000800 */

+#define HRTIM_OUTR_DLYPRT_2           (0x4UL << HRTIM_OUTR_DLYPRT_Pos)          /*!< 0x00001000 */

+

+#define HRTIM_OUTR_POL2_Pos           (17U)

+#define HRTIM_OUTR_POL2_Msk           (0x1UL << HRTIM_OUTR_POL2_Pos)           /*!< 0x00020000 */

+#define HRTIM_OUTR_POL2               HRTIM_OUTR_POL2_Msk                      /*!< Slave output 2 polarity */

+#define HRTIM_OUTR_IDLM2_Pos          (18U)

+#define HRTIM_OUTR_IDLM2_Msk          (0x1UL << HRTIM_OUTR_IDLM2_Pos)          /*!< 0x00040000 */

+#define HRTIM_OUTR_IDLM2              HRTIM_OUTR_IDLM2_Msk                     /*!< Slave output 2 idle mode */

+#define HRTIM_OUTR_IDLES2_Pos         (19U)

+#define HRTIM_OUTR_IDLES2_Msk         (0x1UL << HRTIM_OUTR_IDLES2_Pos)         /*!< 0x00080000 */

+#define HRTIM_OUTR_IDLES2             HRTIM_OUTR_IDLES2_Msk                    /*!< Slave output 2 idle state */

+#define HRTIM_OUTR_FAULT2_Pos         (20U)

+#define HRTIM_OUTR_FAULT2_Msk         (0x3UL << HRTIM_OUTR_FAULT2_Pos)         /*!< 0x00300000 */

+#define HRTIM_OUTR_FAULT2             HRTIM_OUTR_FAULT2_Msk                    /*!< Slave output 2 fault state */

+#define HRTIM_OUTR_FAULT2_0           (0x1UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00100000 */

+#define HRTIM_OUTR_FAULT2_1           (0x2UL << HRTIM_OUTR_FAULT2_Pos)          /*!< 0x00200000 */

+#define HRTIM_OUTR_CHP2_Pos           (22U)

+#define HRTIM_OUTR_CHP2_Msk           (0x1UL << HRTIM_OUTR_CHP2_Pos)           /*!< 0x00400000 */

+#define HRTIM_OUTR_CHP2               HRTIM_OUTR_CHP2_Msk                      /*!< Slave output 2 chopper enable */

+#define HRTIM_OUTR_DIDL2_Pos          (23U)

+#define HRTIM_OUTR_DIDL2_Msk          (0x1UL << HRTIM_OUTR_DIDL2_Pos)          /*!< 0x00800000 */

+#define HRTIM_OUTR_DIDL2              HRTIM_OUTR_DIDL2_Msk                     /*!< Slave output 2 dead time idle */

+

+/**** Bit definition for Slave Timer Fault register ***************************/

+#define HRTIM_FLTR_FLT1EN_Pos         (0U)

+#define HRTIM_FLTR_FLT1EN_Msk         (0x1UL << HRTIM_FLTR_FLT1EN_Pos)         /*!< 0x00000001 */

+#define HRTIM_FLTR_FLT1EN             HRTIM_FLTR_FLT1EN_Msk                    /*!< Fault 1 enable */

+#define HRTIM_FLTR_FLT2EN_Pos         (1U)

+#define HRTIM_FLTR_FLT2EN_Msk         (0x1UL << HRTIM_FLTR_FLT2EN_Pos)         /*!< 0x00000002 */

+#define HRTIM_FLTR_FLT2EN             HRTIM_FLTR_FLT2EN_Msk                    /*!< Fault 2 enable */

+#define HRTIM_FLTR_FLT3EN_Pos         (2U)

+#define HRTIM_FLTR_FLT3EN_Msk         (0x1UL << HRTIM_FLTR_FLT3EN_Pos)         /*!< 0x00000004 */

+#define HRTIM_FLTR_FLT3EN             HRTIM_FLTR_FLT3EN_Msk                    /*!< Fault 3 enable */

+#define HRTIM_FLTR_FLT4EN_Pos         (3U)

+#define HRTIM_FLTR_FLT4EN_Msk         (0x1UL << HRTIM_FLTR_FLT4EN_Pos)         /*!< 0x00000008 */

+#define HRTIM_FLTR_FLT4EN             HRTIM_FLTR_FLT4EN_Msk                    /*!< Fault 4 enable */

+#define HRTIM_FLTR_FLT5EN_Pos         (4U)

+#define HRTIM_FLTR_FLT5EN_Msk         (0x1UL << HRTIM_FLTR_FLT5EN_Pos)         /*!< 0x00000010 */

+#define HRTIM_FLTR_FLT5EN             HRTIM_FLTR_FLT5EN_Msk                    /*!< Fault 5 enable */

+#define HRTIM_FLTR_FLTLCK_Pos         (31U)

+#define HRTIM_FLTR_FLTLCK_Msk         (0x1UL << HRTIM_FLTR_FLTLCK_Pos)         /*!< 0x80000000 */

+#define HRTIM_FLTR_FLTLCK             HRTIM_FLTR_FLTLCK_Msk                    /*!< Fault sources lock */

+

+/**** Bit definition for Common HRTIM Timer control register 1 ****************/

+#define HRTIM_CR1_MUDIS_Pos           (0U)

+#define HRTIM_CR1_MUDIS_Msk           (0x1UL << HRTIM_CR1_MUDIS_Pos)           /*!< 0x00000001 */

+#define HRTIM_CR1_MUDIS               HRTIM_CR1_MUDIS_Msk                      /*!< Master update disable*/

+#define HRTIM_CR1_TAUDIS_Pos          (1U)

+#define HRTIM_CR1_TAUDIS_Msk          (0x1UL << HRTIM_CR1_TAUDIS_Pos)          /*!< 0x00000002 */

+#define HRTIM_CR1_TAUDIS              HRTIM_CR1_TAUDIS_Msk                     /*!< Timer A update disable*/

+#define HRTIM_CR1_TBUDIS_Pos          (2U)

+#define HRTIM_CR1_TBUDIS_Msk          (0x1UL << HRTIM_CR1_TBUDIS_Pos)          /*!< 0x00000004 */

+#define HRTIM_CR1_TBUDIS              HRTIM_CR1_TBUDIS_Msk                     /*!< Timer B update disable*/

+#define HRTIM_CR1_TCUDIS_Pos          (3U)

+#define HRTIM_CR1_TCUDIS_Msk          (0x1UL << HRTIM_CR1_TCUDIS_Pos)          /*!< 0x00000008 */

+#define HRTIM_CR1_TCUDIS              HRTIM_CR1_TCUDIS_Msk                     /*!< Timer C update disable*/

+#define HRTIM_CR1_TDUDIS_Pos          (4U)

+#define HRTIM_CR1_TDUDIS_Msk          (0x1UL << HRTIM_CR1_TDUDIS_Pos)          /*!< 0x00000010 */

+#define HRTIM_CR1_TDUDIS              HRTIM_CR1_TDUDIS_Msk                     /*!< Timer D update disable*/

+#define HRTIM_CR1_TEUDIS_Pos          (5U)

+#define HRTIM_CR1_TEUDIS_Msk          (0x1UL << HRTIM_CR1_TEUDIS_Pos)          /*!< 0x00000020 */

+#define HRTIM_CR1_TEUDIS              HRTIM_CR1_TEUDIS_Msk                     /*!< Timer E update disable*/

+#define HRTIM_CR1_ADC1USRC_Pos        (16U)

+#define HRTIM_CR1_ADC1USRC_Msk        (0x7UL << HRTIM_CR1_ADC1USRC_Pos)        /*!< 0x00070000 */

+#define HRTIM_CR1_ADC1USRC            HRTIM_CR1_ADC1USRC_Msk                   /*!< ADC Trigger 1 update source */

+#define HRTIM_CR1_ADC1USRC_0          (0x1UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00010000 */

+#define HRTIM_CR1_ADC1USRC_1          (0x2UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00020000 */

+#define HRTIM_CR1_ADC1USRC_2          (0x4UL << HRTIM_CR1_ADC1USRC_Pos)         /*!< 0x00040000 */

+#define HRTIM_CR1_ADC2USRC_Pos        (19U)

+#define HRTIM_CR1_ADC2USRC_Msk        (0x7UL << HRTIM_CR1_ADC2USRC_Pos)        /*!< 0x00380000 */

+#define HRTIM_CR1_ADC2USRC            HRTIM_CR1_ADC2USRC_Msk                   /*!< ADC Trigger 2 update source */

+#define HRTIM_CR1_ADC2USRC_0          (0x1UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00080000 */

+#define HRTIM_CR1_ADC2USRC_1          (0x2UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00100000 */

+#define HRTIM_CR1_ADC2USRC_2          (0x4UL << HRTIM_CR1_ADC2USRC_Pos)         /*!< 0x00200000 */

+#define HRTIM_CR1_ADC3USRC_Pos        (22U)

+#define HRTIM_CR1_ADC3USRC_Msk        (0x7UL << HRTIM_CR1_ADC3USRC_Pos)        /*!< 0x01C00000 */

+#define HRTIM_CR1_ADC3USRC            HRTIM_CR1_ADC3USRC_Msk                   /*!< ADC Trigger 3 update source */

+#define HRTIM_CR1_ADC3USRC_0          (0x1UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00400000 */

+#define HRTIM_CR1_ADC3USRC_1          (0x2UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x00800000 */

+#define HRTIM_CR1_ADC3USRC_2          (0x4UL << HRTIM_CR1_ADC3USRC_Pos)         /*!< 0x01000000 */

+#define HRTIM_CR1_ADC4USRC_Pos        (25U)

+#define HRTIM_CR1_ADC4USRC_Msk        (0x7UL << HRTIM_CR1_ADC4USRC_Pos)        /*!< 0x0E000000 */

+#define HRTIM_CR1_ADC4USRC            HRTIM_CR1_ADC4USRC_Msk                   /*!< ADC Trigger 4 update source */

+#define HRTIM_CR1_ADC4USRC_0          (0x1UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x02000000 */

+#define HRTIM_CR1_ADC4USRC_1          (0x2UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x04000000 */

+#define HRTIM_CR1_ADC4USRC_2          (0x0UL << HRTIM_CR1_ADC4USRC_Pos)         /*!< 0x0800000 */

+

+/**** Bit definition for Common HRTIM Timer control register 2 ****************/

+#define HRTIM_CR2_MSWU_Pos            (0U)

+#define HRTIM_CR2_MSWU_Msk            (0x1UL << HRTIM_CR2_MSWU_Pos)            /*!< 0x00000001 */

+#define HRTIM_CR2_MSWU                HRTIM_CR2_MSWU_Msk                       /*!< Master software update */

+#define HRTIM_CR2_TASWU_Pos           (1U)

+#define HRTIM_CR2_TASWU_Msk           (0x1UL << HRTIM_CR2_TASWU_Pos)           /*!< 0x00000002 */

+#define HRTIM_CR2_TASWU               HRTIM_CR2_TASWU_Msk                      /*!< Timer A software update */

+#define HRTIM_CR2_TBSWU_Pos           (2U)

+#define HRTIM_CR2_TBSWU_Msk           (0x1UL << HRTIM_CR2_TBSWU_Pos)           /*!< 0x00000004 */

+#define HRTIM_CR2_TBSWU               HRTIM_CR2_TBSWU_Msk                      /*!< Timer B software update */

+#define HRTIM_CR2_TCSWU_Pos           (3U)

+#define HRTIM_CR2_TCSWU_Msk           (0x1UL << HRTIM_CR2_TCSWU_Pos)           /*!< 0x00000008 */

+#define HRTIM_CR2_TCSWU               HRTIM_CR2_TCSWU_Msk                      /*!< Timer C software update */

+#define HRTIM_CR2_TDSWU_Pos           (4U)

+#define HRTIM_CR2_TDSWU_Msk           (0x1UL << HRTIM_CR2_TDSWU_Pos)           /*!< 0x00000010 */

+#define HRTIM_CR2_TDSWU               HRTIM_CR2_TDSWU_Msk                      /*!< Timer D software update */

+#define HRTIM_CR2_TESWU_Pos           (5U)

+#define HRTIM_CR2_TESWU_Msk           (0x1UL << HRTIM_CR2_TESWU_Pos)           /*!< 0x00000020 */

+#define HRTIM_CR2_TESWU               HRTIM_CR2_TESWU_Msk                      /*!< Timer E software update */

+#define HRTIM_CR2_MRST_Pos            (8U)

+#define HRTIM_CR2_MRST_Msk            (0x1UL << HRTIM_CR2_MRST_Pos)            /*!< 0x00000100 */

+#define HRTIM_CR2_MRST                HRTIM_CR2_MRST_Msk                       /*!< Master count software reset */

+#define HRTIM_CR2_TARST_Pos           (9U)

+#define HRTIM_CR2_TARST_Msk           (0x1UL << HRTIM_CR2_TARST_Pos)           /*!< 0x00000200 */

+#define HRTIM_CR2_TARST               HRTIM_CR2_TARST_Msk                      /*!< Timer A count software reset */

+#define HRTIM_CR2_TBRST_Pos           (10U)

+#define HRTIM_CR2_TBRST_Msk           (0x1UL << HRTIM_CR2_TBRST_Pos)           /*!< 0x00000400 */

+#define HRTIM_CR2_TBRST               HRTIM_CR2_TBRST_Msk                      /*!< Timer B count software reset */

+#define HRTIM_CR2_TCRST_Pos           (11U)

+#define HRTIM_CR2_TCRST_Msk           (0x1UL << HRTIM_CR2_TCRST_Pos)           /*!< 0x00000800 */

+#define HRTIM_CR2_TCRST               HRTIM_CR2_TCRST_Msk                      /*!< Timer C count software reset */

+#define HRTIM_CR2_TDRST_Pos           (12U)

+#define HRTIM_CR2_TDRST_Msk           (0x1UL << HRTIM_CR2_TDRST_Pos)           /*!< 0x00001000 */

+#define HRTIM_CR2_TDRST               HRTIM_CR2_TDRST_Msk                      /*!< Timer D count software reset */

+#define HRTIM_CR2_TERST_Pos           (13U)

+#define HRTIM_CR2_TERST_Msk           (0x1UL << HRTIM_CR2_TERST_Pos)           /*!< 0x00002000 */

+#define HRTIM_CR2_TERST               HRTIM_CR2_TERST_Msk                      /*!< Timer E count software reset */

+

+/**** Bit definition for Common HRTIM Timer interrupt status register *********/

+#define HRTIM_ISR_FLT1_Pos            (0U)

+#define HRTIM_ISR_FLT1_Msk            (0x1UL << HRTIM_ISR_FLT1_Pos)            /*!< 0x00000001 */

+#define HRTIM_ISR_FLT1                HRTIM_ISR_FLT1_Msk                       /*!< Fault 1 interrupt flag */

+#define HRTIM_ISR_FLT2_Pos            (1U)

+#define HRTIM_ISR_FLT2_Msk            (0x1UL << HRTIM_ISR_FLT2_Pos)            /*!< 0x00000002 */

+#define HRTIM_ISR_FLT2                HRTIM_ISR_FLT2_Msk                       /*!< Fault 2 interrupt flag */

+#define HRTIM_ISR_FLT3_Pos            (2U)

+#define HRTIM_ISR_FLT3_Msk            (0x1UL << HRTIM_ISR_FLT3_Pos)            /*!< 0x00000004 */

+#define HRTIM_ISR_FLT3                HRTIM_ISR_FLT3_Msk                       /*!< Fault 3 interrupt flag */

+#define HRTIM_ISR_FLT4_Pos            (3U)

+#define HRTIM_ISR_FLT4_Msk            (0x1UL << HRTIM_ISR_FLT4_Pos)            /*!< 0x00000008 */

+#define HRTIM_ISR_FLT4                HRTIM_ISR_FLT4_Msk                       /*!< Fault 4 interrupt flag */

+#define HRTIM_ISR_FLT5_Pos            (4U)

+#define HRTIM_ISR_FLT5_Msk            (0x1UL << HRTIM_ISR_FLT5_Pos)            /*!< 0x00000010 */

+#define HRTIM_ISR_FLT5                HRTIM_ISR_FLT5_Msk                       /*!< Fault 5 interrupt flag */

+#define HRTIM_ISR_SYSFLT_Pos          (5U)

+#define HRTIM_ISR_SYSFLT_Msk          (0x1UL << HRTIM_ISR_SYSFLT_Pos)          /*!< 0x00000020 */

+#define HRTIM_ISR_SYSFLT              HRTIM_ISR_SYSFLT_Msk                     /*!< System Fault interrupt flag */

+#define HRTIM_ISR_BMPER_Pos           (17U)

+#define HRTIM_ISR_BMPER_Msk           (0x1UL << HRTIM_ISR_BMPER_Pos)           /*!< 0x00020000 */

+#define HRTIM_ISR_BMPER               HRTIM_ISR_BMPER_Msk                      /*!<  Burst mode period interrupt flag */

+

+/**** Bit definition for Common HRTIM Timer interrupt clear register **********/

+#define HRTIM_ICR_FLT1C_Pos           (0U)

+#define HRTIM_ICR_FLT1C_Msk           (0x1UL << HRTIM_ICR_FLT1C_Pos)           /*!< 0x00000001 */

+#define HRTIM_ICR_FLT1C               HRTIM_ICR_FLT1C_Msk                      /*!< Fault 1 interrupt flag clear */

+#define HRTIM_ICR_FLT2C_Pos           (1U)

+#define HRTIM_ICR_FLT2C_Msk           (0x1UL << HRTIM_ICR_FLT2C_Pos)           /*!< 0x00000002 */

+#define HRTIM_ICR_FLT2C               HRTIM_ICR_FLT2C_Msk                      /*!< Fault 2 interrupt flag clear */

+#define HRTIM_ICR_FLT3C_Pos           (2U)

+#define HRTIM_ICR_FLT3C_Msk           (0x1UL << HRTIM_ICR_FLT3C_Pos)           /*!< 0x00000004 */

+#define HRTIM_ICR_FLT3C               HRTIM_ICR_FLT3C_Msk                      /*!< Fault 3 interrupt flag clear */

+#define HRTIM_ICR_FLT4C_Pos           (3U)

+#define HRTIM_ICR_FLT4C_Msk           (0x1UL << HRTIM_ICR_FLT4C_Pos)           /*!< 0x00000008 */

+#define HRTIM_ICR_FLT4C               HRTIM_ICR_FLT4C_Msk                      /*!< Fault 4 interrupt flag clear */

+#define HRTIM_ICR_FLT5C_Pos           (4U)

+#define HRTIM_ICR_FLT5C_Msk           (0x1UL << HRTIM_ICR_FLT5C_Pos)           /*!< 0x00000010 */

+#define HRTIM_ICR_FLT5C               HRTIM_ICR_FLT5C_Msk                      /*!< Fault 5 interrupt flag clear */

+#define HRTIM_ICR_SYSFLTC_Pos         (5U)

+#define HRTIM_ICR_SYSFLTC_Msk         (0x1UL << HRTIM_ICR_SYSFLTC_Pos)         /*!< 0x00000020 */

+#define HRTIM_ICR_SYSFLTC             HRTIM_ICR_SYSFLTC_Msk                    /*!< System Fault interrupt flag clear */

+#define HRTIM_ICR_BMPERC_Pos          (17U)

+#define HRTIM_ICR_BMPERC_Msk          (0x1UL << HRTIM_ICR_BMPERC_Pos)          /*!< 0x00020000 */

+#define HRTIM_ICR_BMPERC              HRTIM_ICR_BMPERC_Msk                     /*!<  Burst mode period interrupt flag clear */

+

+/**** Bit definition for Common HRTIM Timer interrupt enable register *********/

+#define HRTIM_IER_FLT1_Pos            (0U)

+#define HRTIM_IER_FLT1_Msk            (0x1UL << HRTIM_IER_FLT1_Pos)            /*!< 0x00000001 */

+#define HRTIM_IER_FLT1                HRTIM_IER_FLT1_Msk                       /*!< Fault 1 interrupt enable */

+#define HRTIM_IER_FLT2_Pos            (1U)

+#define HRTIM_IER_FLT2_Msk            (0x1UL << HRTIM_IER_FLT2_Pos)            /*!< 0x00000002 */

+#define HRTIM_IER_FLT2                HRTIM_IER_FLT2_Msk                       /*!< Fault 2 interrupt enable */

+#define HRTIM_IER_FLT3_Pos            (2U)

+#define HRTIM_IER_FLT3_Msk            (0x1UL << HRTIM_IER_FLT3_Pos)            /*!< 0x00000004 */

+#define HRTIM_IER_FLT3                HRTIM_IER_FLT3_Msk                       /*!< Fault 3 interrupt enable */

+#define HRTIM_IER_FLT4_Pos            (3U)

+#define HRTIM_IER_FLT4_Msk            (0x1UL << HRTIM_IER_FLT4_Pos)            /*!< 0x00000008 */

+#define HRTIM_IER_FLT4                HRTIM_IER_FLT4_Msk                       /*!< Fault 4 interrupt enable */

+#define HRTIM_IER_FLT5_Pos            (4U)

+#define HRTIM_IER_FLT5_Msk            (0x1UL << HRTIM_IER_FLT5_Pos)            /*!< 0x00000010 */

+#define HRTIM_IER_FLT5                HRTIM_IER_FLT5_Msk                       /*!< Fault 5 interrupt enable */

+#define HRTIM_IER_SYSFLT_Pos          (5U)

+#define HRTIM_IER_SYSFLT_Msk          (0x1UL << HRTIM_IER_SYSFLT_Pos)          /*!< 0x00000020 */

+#define HRTIM_IER_SYSFLT              HRTIM_IER_SYSFLT_Msk                     /*!< System Fault interrupt enable */

+#define HRTIM_IER_BMPER_Pos           (17U)

+#define HRTIM_IER_BMPER_Msk           (0x1UL << HRTIM_IER_BMPER_Pos)           /*!< 0x00020000 */

+#define HRTIM_IER_BMPER               HRTIM_IER_BMPER_Msk                      /*!<  Burst mode period interrupt enable */

+

+/**** Bit definition for Common HRTIM Timer output enable register ************/

+#define HRTIM_OENR_TA1OEN_Pos         (0U)

+#define HRTIM_OENR_TA1OEN_Msk         (0x1UL << HRTIM_OENR_TA1OEN_Pos)         /*!< 0x00000001 */

+#define HRTIM_OENR_TA1OEN             HRTIM_OENR_TA1OEN_Msk                    /*!< Timer A Output 1 enable */

+#define HRTIM_OENR_TA2OEN_Pos         (1U)

+#define HRTIM_OENR_TA2OEN_Msk         (0x1UL << HRTIM_OENR_TA2OEN_Pos)         /*!< 0x00000002 */

+#define HRTIM_OENR_TA2OEN             HRTIM_OENR_TA2OEN_Msk                    /*!< Timer A Output 2 enable */

+#define HRTIM_OENR_TB1OEN_Pos         (2U)

+#define HRTIM_OENR_TB1OEN_Msk         (0x1UL << HRTIM_OENR_TB1OEN_Pos)         /*!< 0x00000004 */

+#define HRTIM_OENR_TB1OEN             HRTIM_OENR_TB1OEN_Msk                    /*!< Timer B Output 1 enable */

+#define HRTIM_OENR_TB2OEN_Pos         (3U)

+#define HRTIM_OENR_TB2OEN_Msk         (0x1UL << HRTIM_OENR_TB2OEN_Pos)         /*!< 0x00000008 */

+#define HRTIM_OENR_TB2OEN             HRTIM_OENR_TB2OEN_Msk                    /*!< Timer B Output 2 enable */

+#define HRTIM_OENR_TC1OEN_Pos         (4U)

+#define HRTIM_OENR_TC1OEN_Msk         (0x1UL << HRTIM_OENR_TC1OEN_Pos)         /*!< 0x00000010 */

+#define HRTIM_OENR_TC1OEN             HRTIM_OENR_TC1OEN_Msk                    /*!< Timer C Output 1 enable */

+#define HRTIM_OENR_TC2OEN_Pos         (5U)

+#define HRTIM_OENR_TC2OEN_Msk         (0x1UL << HRTIM_OENR_TC2OEN_Pos)         /*!< 0x00000020 */

+#define HRTIM_OENR_TC2OEN             HRTIM_OENR_TC2OEN_Msk                    /*!< Timer C Output 2 enable */

+#define HRTIM_OENR_TD1OEN_Pos         (6U)

+#define HRTIM_OENR_TD1OEN_Msk         (0x1UL << HRTIM_OENR_TD1OEN_Pos)         /*!< 0x00000040 */

+#define HRTIM_OENR_TD1OEN             HRTIM_OENR_TD1OEN_Msk                    /*!< Timer D Output 1 enable */

+#define HRTIM_OENR_TD2OEN_Pos         (7U)

+#define HRTIM_OENR_TD2OEN_Msk         (0x1UL << HRTIM_OENR_TD2OEN_Pos)         /*!< 0x00000080 */

+#define HRTIM_OENR_TD2OEN             HRTIM_OENR_TD2OEN_Msk                    /*!< Timer D Output 2 enable */

+#define HRTIM_OENR_TE1OEN_Pos         (8U)

+#define HRTIM_OENR_TE1OEN_Msk         (0x1UL << HRTIM_OENR_TE1OEN_Pos)         /*!< 0x00000100 */

+#define HRTIM_OENR_TE1OEN             HRTIM_OENR_TE1OEN_Msk                    /*!< Timer E Output 1 enable */

+#define HRTIM_OENR_TE2OEN_Pos         (9U)

+#define HRTIM_OENR_TE2OEN_Msk         (0x1UL << HRTIM_OENR_TE2OEN_Pos)         /*!< 0x00000200 */

+#define HRTIM_OENR_TE2OEN             HRTIM_OENR_TE2OEN_Msk                    /*!< Timer E Output 2 enable */

+

+/**** Bit definition for Common HRTIM Timer output disable register ***********/

+#define HRTIM_ODISR_TA1ODIS_Pos       (0U)

+#define HRTIM_ODISR_TA1ODIS_Msk       (0x1UL << HRTIM_ODISR_TA1ODIS_Pos)       /*!< 0x00000001 */

+#define HRTIM_ODISR_TA1ODIS           HRTIM_ODISR_TA1ODIS_Msk                  /*!< Timer A Output 1 disable */

+#define HRTIM_ODISR_TA2ODIS_Pos       (1U)

+#define HRTIM_ODISR_TA2ODIS_Msk       (0x1UL << HRTIM_ODISR_TA2ODIS_Pos)       /*!< 0x00000002 */

+#define HRTIM_ODISR_TA2ODIS           HRTIM_ODISR_TA2ODIS_Msk                  /*!< Timer A Output 2 disable */

+#define HRTIM_ODISR_TB1ODIS_Pos       (2U)

+#define HRTIM_ODISR_TB1ODIS_Msk       (0x1UL << HRTIM_ODISR_TB1ODIS_Pos)       /*!< 0x00000004 */

+#define HRTIM_ODISR_TB1ODIS           HRTIM_ODISR_TB1ODIS_Msk                  /*!< Timer B Output 1 disable */

+#define HRTIM_ODISR_TB2ODIS_Pos       (3U)

+#define HRTIM_ODISR_TB2ODIS_Msk       (0x1UL << HRTIM_ODISR_TB2ODIS_Pos)       /*!< 0x00000008 */

+#define HRTIM_ODISR_TB2ODIS           HRTIM_ODISR_TB2ODIS_Msk                  /*!< Timer B Output 2 disable */

+#define HRTIM_ODISR_TC1ODIS_Pos       (4U)

+#define HRTIM_ODISR_TC1ODIS_Msk       (0x1UL << HRTIM_ODISR_TC1ODIS_Pos)       /*!< 0x00000010 */

+#define HRTIM_ODISR_TC1ODIS           HRTIM_ODISR_TC1ODIS_Msk                  /*!< Timer C Output 1 disable */

+#define HRTIM_ODISR_TC2ODIS_Pos       (5U)

+#define HRTIM_ODISR_TC2ODIS_Msk       (0x1UL << HRTIM_ODISR_TC2ODIS_Pos)       /*!< 0x00000020 */

+#define HRTIM_ODISR_TC2ODIS           HRTIM_ODISR_TC2ODIS_Msk                  /*!< Timer C Output 2 disable */

+#define HRTIM_ODISR_TD1ODIS_Pos       (6U)

+#define HRTIM_ODISR_TD1ODIS_Msk       (0x1UL << HRTIM_ODISR_TD1ODIS_Pos)       /*!< 0x00000040 */

+#define HRTIM_ODISR_TD1ODIS           HRTIM_ODISR_TD1ODIS_Msk                  /*!< Timer D Output 1 disable */

+#define HRTIM_ODISR_TD2ODIS_Pos       (7U)

+#define HRTIM_ODISR_TD2ODIS_Msk       (0x1UL << HRTIM_ODISR_TD2ODIS_Pos)       /*!< 0x00000080 */

+#define HRTIM_ODISR_TD2ODIS           HRTIM_ODISR_TD2ODIS_Msk                  /*!< Timer D Output 2 disable */

+#define HRTIM_ODISR_TE1ODIS_Pos       (8U)

+#define HRTIM_ODISR_TE1ODIS_Msk       (0x1UL << HRTIM_ODISR_TE1ODIS_Pos)       /*!< 0x00000100 */

+#define HRTIM_ODISR_TE1ODIS           HRTIM_ODISR_TE1ODIS_Msk                  /*!< Timer E Output 1 disable */

+#define HRTIM_ODISR_TE2ODIS_Pos       (9U)

+#define HRTIM_ODISR_TE2ODIS_Msk       (0x1UL << HRTIM_ODISR_TE2ODIS_Pos)       /*!< 0x00000200 */

+#define HRTIM_ODISR_TE2ODIS           HRTIM_ODISR_TE2ODIS_Msk                  /*!< Timer E Output 2 disable */

+

+/**** Bit definition for Common HRTIM Timer output disable status register *****/

+#define HRTIM_ODSR_TA1ODS_Pos         (0U)

+#define HRTIM_ODSR_TA1ODS_Msk         (0x1UL << HRTIM_ODSR_TA1ODS_Pos)         /*!< 0x00000001 */

+#define HRTIM_ODSR_TA1ODS             HRTIM_ODSR_TA1ODS_Msk                    /*!< Timer A Output 1 disable status */

+#define HRTIM_ODSR_TA2ODS_Pos         (1U)

+#define HRTIM_ODSR_TA2ODS_Msk         (0x1UL << HRTIM_ODSR_TA2ODS_Pos)         /*!< 0x00000002 */

+#define HRTIM_ODSR_TA2ODS             HRTIM_ODSR_TA2ODS_Msk                    /*!< Timer A Output 2 disable status */

+#define HRTIM_ODSR_TB1ODS_Pos         (2U)

+#define HRTIM_ODSR_TB1ODS_Msk         (0x1UL << HRTIM_ODSR_TB1ODS_Pos)         /*!< 0x00000004 */

+#define HRTIM_ODSR_TB1ODS             HRTIM_ODSR_TB1ODS_Msk                    /*!< Timer B Output 1 disable status */

+#define HRTIM_ODSR_TB2ODS_Pos         (3U)

+#define HRTIM_ODSR_TB2ODS_Msk         (0x1UL << HRTIM_ODSR_TB2ODS_Pos)         /*!< 0x00000008 */

+#define HRTIM_ODSR_TB2ODS             HRTIM_ODSR_TB2ODS_Msk                    /*!< Timer B Output 2 disable status */

+#define HRTIM_ODSR_TC1ODS_Pos         (4U)

+#define HRTIM_ODSR_TC1ODS_Msk         (0x1UL << HRTIM_ODSR_TC1ODS_Pos)         /*!< 0x00000010 */

+#define HRTIM_ODSR_TC1ODS             HRTIM_ODSR_TC1ODS_Msk                    /*!< Timer C Output 1 disable status */

+#define HRTIM_ODSR_TC2ODS_Pos         (5U)

+#define HRTIM_ODSR_TC2ODS_Msk         (0x1UL << HRTIM_ODSR_TC2ODS_Pos)         /*!< 0x00000020 */

+#define HRTIM_ODSR_TC2ODS             HRTIM_ODSR_TC2ODS_Msk                    /*!< Timer C Output 2 disable status */

+#define HRTIM_ODSR_TD1ODS_Pos         (6U)

+#define HRTIM_ODSR_TD1ODS_Msk         (0x1UL << HRTIM_ODSR_TD1ODS_Pos)         /*!< 0x00000040 */

+#define HRTIM_ODSR_TD1ODS             HRTIM_ODSR_TD1ODS_Msk                    /*!< Timer D Output 1 disable status */

+#define HRTIM_ODSR_TD2ODS_Pos         (7U)

+#define HRTIM_ODSR_TD2ODS_Msk         (0x1UL << HRTIM_ODSR_TD2ODS_Pos)         /*!< 0x00000080 */

+#define HRTIM_ODSR_TD2ODS             HRTIM_ODSR_TD2ODS_Msk                    /*!< Timer D Output 2 disable status */

+#define HRTIM_ODSR_TE1ODS_Pos         (8U)

+#define HRTIM_ODSR_TE1ODS_Msk         (0x1UL << HRTIM_ODSR_TE1ODS_Pos)         /*!< 0x00000100 */

+#define HRTIM_ODSR_TE1ODS             HRTIM_ODSR_TE1ODS_Msk                    /*!< Timer E Output 1 disable status */

+#define HRTIM_ODSR_TE2ODS_Pos         (9U)

+#define HRTIM_ODSR_TE2ODS_Msk         (0x1UL << HRTIM_ODSR_TE2ODS_Pos)         /*!< 0x00000200 */

+#define HRTIM_ODSR_TE2ODS             HRTIM_ODSR_TE2ODS_Msk                    /*!< Timer E Output 2 disable status */

+

+/**** Bit definition for Common HRTIM Timer Burst mode control register ********/

+#define HRTIM_BMCR_BME_Pos            (0U)

+#define HRTIM_BMCR_BME_Msk            (0x1UL << HRTIM_BMCR_BME_Pos)            /*!< 0x00000001 */

+#define HRTIM_BMCR_BME                HRTIM_BMCR_BME_Msk                       /*!< Burst mode enbale */

+#define HRTIM_BMCR_BMOM_Pos           (1U)

+#define HRTIM_BMCR_BMOM_Msk           (0x1UL << HRTIM_BMCR_BMOM_Pos)           /*!< 0x00000002 */

+#define HRTIM_BMCR_BMOM               HRTIM_BMCR_BMOM_Msk                      /*!< Burst mode operating mode */

+#define HRTIM_BMCR_BMCLK_Pos          (2U)

+#define HRTIM_BMCR_BMCLK_Msk          (0xFUL << HRTIM_BMCR_BMCLK_Pos)          /*!< 0x0000003C */

+#define HRTIM_BMCR_BMCLK              HRTIM_BMCR_BMCLK_Msk                     /*!< Burst mode clock source */

+#define HRTIM_BMCR_BMCLK_0            (0x1UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000004 */

+#define HRTIM_BMCR_BMCLK_1            (0x2UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000008 */

+#define HRTIM_BMCR_BMCLK_2            (0x4UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000010 */

+#define HRTIM_BMCR_BMCLK_3            (0x8UL << HRTIM_BMCR_BMCLK_Pos)           /*!< 0x00000020 */

+#define HRTIM_BMCR_BMPRSC_Pos         (6U)

+#define HRTIM_BMCR_BMPRSC_Msk         (0xFUL << HRTIM_BMCR_BMPRSC_Pos)         /*!< 0x000003C0 */

+#define HRTIM_BMCR_BMPRSC             HRTIM_BMCR_BMPRSC_Msk                    /*!< Burst mode prescaler */

+#define HRTIM_BMCR_BMPRSC_0           (0x1UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000040 */

+#define HRTIM_BMCR_BMPRSC_1           (0x2UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000080 */

+#define HRTIM_BMCR_BMPRSC_2           (0x4UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000100 */

+#define HRTIM_BMCR_BMPRSC_3           (0x8UL << HRTIM_BMCR_BMPRSC_Pos)          /*!< 0x00000200 */

+#define HRTIM_BMCR_BMPREN_Pos         (10U)

+#define HRTIM_BMCR_BMPREN_Msk         (0x1UL << HRTIM_BMCR_BMPREN_Pos)         /*!< 0x00000400 */

+#define HRTIM_BMCR_BMPREN             HRTIM_BMCR_BMPREN_Msk                    /*!< Burst mode Preload bit */

+#define HRTIM_BMCR_MTBM_Pos           (16U)

+#define HRTIM_BMCR_MTBM_Msk           (0x1UL << HRTIM_BMCR_MTBM_Pos)           /*!< 0x00010000 */

+#define HRTIM_BMCR_MTBM               HRTIM_BMCR_MTBM_Msk                      /*!< Master Timer Burst mode */

+#define HRTIM_BMCR_TABM_Pos           (17U)

+#define HRTIM_BMCR_TABM_Msk           (0x1UL << HRTIM_BMCR_TABM_Pos)           /*!< 0x00020000 */

+#define HRTIM_BMCR_TABM               HRTIM_BMCR_TABM_Msk                      /*!< Timer A Burst mode */

+#define HRTIM_BMCR_TBBM_Pos           (18U)

+#define HRTIM_BMCR_TBBM_Msk           (0x1UL << HRTIM_BMCR_TBBM_Pos)           /*!< 0x00040000 */

+#define HRTIM_BMCR_TBBM               HRTIM_BMCR_TBBM_Msk                      /*!< Timer B Burst mode */

+#define HRTIM_BMCR_TCBM_Pos           (19U)

+#define HRTIM_BMCR_TCBM_Msk           (0x1UL << HRTIM_BMCR_TCBM_Pos)           /*!< 0x00080000 */

+#define HRTIM_BMCR_TCBM               HRTIM_BMCR_TCBM_Msk                      /*!< Timer C Burst mode */

+#define HRTIM_BMCR_TDBM_Pos           (20U)

+#define HRTIM_BMCR_TDBM_Msk           (0x1UL << HRTIM_BMCR_TDBM_Pos)           /*!< 0x00100000 */

+#define HRTIM_BMCR_TDBM               HRTIM_BMCR_TDBM_Msk                      /*!< Timer D Burst mode */

+#define HRTIM_BMCR_TEBM_Pos           (21U)

+#define HRTIM_BMCR_TEBM_Msk           (0x1UL << HRTIM_BMCR_TEBM_Pos)           /*!< 0x00200000 */

+#define HRTIM_BMCR_TEBM               HRTIM_BMCR_TEBM_Msk                      /*!< Timer E Burst mode */

+#define HRTIM_BMCR_BMSTAT_Pos         (31U)

+#define HRTIM_BMCR_BMSTAT_Msk         (0x1UL << HRTIM_BMCR_BMSTAT_Pos)         /*!< 0x80000000 */

+#define HRTIM_BMCR_BMSTAT             HRTIM_BMCR_BMSTAT_Msk                    /*!< Burst mode status */

+

+/**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/

+#define HRTIM_BMTRGR_SW_Pos           (0U)

+#define HRTIM_BMTRGR_SW_Msk           (0x1UL << HRTIM_BMTRGR_SW_Pos)           /*!< 0x00000001 */

+#define HRTIM_BMTRGR_SW               HRTIM_BMTRGR_SW_Msk                      /*!< Software start */

+#define HRTIM_BMTRGR_MSTRST_Pos       (1U)

+#define HRTIM_BMTRGR_MSTRST_Msk       (0x1UL << HRTIM_BMTRGR_MSTRST_Pos)       /*!< 0x00000002 */

+#define HRTIM_BMTRGR_MSTRST           HRTIM_BMTRGR_MSTRST_Msk                  /*!<  Master reset */

+#define HRTIM_BMTRGR_MSTREP_Pos       (2U)

+#define HRTIM_BMTRGR_MSTREP_Msk       (0x1UL << HRTIM_BMTRGR_MSTREP_Pos)       /*!< 0x00000004 */

+#define HRTIM_BMTRGR_MSTREP           HRTIM_BMTRGR_MSTREP_Msk                  /*!<  Master repetition */

+#define HRTIM_BMTRGR_MSTCMP1_Pos      (3U)

+#define HRTIM_BMTRGR_MSTCMP1_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos)      /*!< 0x00000008 */

+#define HRTIM_BMTRGR_MSTCMP1          HRTIM_BMTRGR_MSTCMP1_Msk                 /*!<  Master compare 1 */

+#define HRTIM_BMTRGR_MSTCMP2_Pos      (4U)

+#define HRTIM_BMTRGR_MSTCMP2_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos)      /*!< 0x00000010 */

+#define HRTIM_BMTRGR_MSTCMP2          HRTIM_BMTRGR_MSTCMP2_Msk                 /*!< Master compare 2  */

+#define HRTIM_BMTRGR_MSTCMP3_Pos      (5U)

+#define HRTIM_BMTRGR_MSTCMP3_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos)      /*!< 0x00000020 */

+#define HRTIM_BMTRGR_MSTCMP3          HRTIM_BMTRGR_MSTCMP3_Msk                 /*!< Master compare 3 */

+#define HRTIM_BMTRGR_MSTCMP4_Pos      (6U)

+#define HRTIM_BMTRGR_MSTCMP4_Msk      (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos)      /*!< 0x00000040 */

+#define HRTIM_BMTRGR_MSTCMP4          HRTIM_BMTRGR_MSTCMP4_Msk                 /*!< Master compare 4 */

+#define HRTIM_BMTRGR_TARST_Pos        (7U)

+#define HRTIM_BMTRGR_TARST_Msk        (0x1UL << HRTIM_BMTRGR_TARST_Pos)        /*!< 0x00000080 */

+#define HRTIM_BMTRGR_TARST            HRTIM_BMTRGR_TARST_Msk                   /*!< Timer A reset  */

+#define HRTIM_BMTRGR_TAREP_Pos        (8U)

+#define HRTIM_BMTRGR_TAREP_Msk        (0x1UL << HRTIM_BMTRGR_TAREP_Pos)        /*!< 0x00000100 */

+#define HRTIM_BMTRGR_TAREP            HRTIM_BMTRGR_TAREP_Msk                   /*!< Timer A repetition  */

+#define HRTIM_BMTRGR_TACMP1_Pos       (9U)

+#define HRTIM_BMTRGR_TACMP1_Msk       (0x1UL << HRTIM_BMTRGR_TACMP1_Pos)       /*!< 0x00000200 */

+#define HRTIM_BMTRGR_TACMP1           HRTIM_BMTRGR_TACMP1_Msk                  /*!< Timer A compare 1  */

+#define HRTIM_BMTRGR_TACMP2_Pos       (10U)

+#define HRTIM_BMTRGR_TACMP2_Msk       (0x1UL << HRTIM_BMTRGR_TACMP2_Pos)       /*!< 0x00000400 */

+#define HRTIM_BMTRGR_TACMP2           HRTIM_BMTRGR_TACMP2_Msk                  /*!< Timer A compare 2  */

+#define HRTIM_BMTRGR_TBRST_Pos        (11U)

+#define HRTIM_BMTRGR_TBRST_Msk        (0x1UL << HRTIM_BMTRGR_TBRST_Pos)        /*!< 0x00000800 */

+#define HRTIM_BMTRGR_TBRST            HRTIM_BMTRGR_TBRST_Msk                   /*!< Timer B reset  */

+#define HRTIM_BMTRGR_TBREP_Pos        (12U)

+#define HRTIM_BMTRGR_TBREP_Msk        (0x1UL << HRTIM_BMTRGR_TBREP_Pos)        /*!< 0x00001000 */

+#define HRTIM_BMTRGR_TBREP            HRTIM_BMTRGR_TBREP_Msk                   /*!< Timer B repetition  */

+#define HRTIM_BMTRGR_TBCMP1_Pos       (13U)

+#define HRTIM_BMTRGR_TBCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos)       /*!< 0x00002000 */

+#define HRTIM_BMTRGR_TBCMP1           HRTIM_BMTRGR_TBCMP1_Msk                  /*!< Timer B compare 1 */

+#define HRTIM_BMTRGR_TBCMP2_Pos       (14U)

+#define HRTIM_BMTRGR_TBCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos)       /*!< 0x00004000 */

+#define HRTIM_BMTRGR_TBCMP2           HRTIM_BMTRGR_TBCMP2_Msk                  /*!< Timer B compare 2 */

+#define HRTIM_BMTRGR_TCRST_Pos        (15U)

+#define HRTIM_BMTRGR_TCRST_Msk        (0x1UL << HRTIM_BMTRGR_TCRST_Pos)        /*!< 0x00008000 */

+#define HRTIM_BMTRGR_TCRST            HRTIM_BMTRGR_TCRST_Msk                   /*!< Timer C reset  */

+#define HRTIM_BMTRGR_TCREP_Pos        (16U)

+#define HRTIM_BMTRGR_TCREP_Msk        (0x1UL << HRTIM_BMTRGR_TCREP_Pos)        /*!< 0x00010000 */

+#define HRTIM_BMTRGR_TCREP            HRTIM_BMTRGR_TCREP_Msk                   /*!< Timer C repetition */

+#define HRTIM_BMTRGR_TCCMP1_Pos       (17U)

+#define HRTIM_BMTRGR_TCCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos)       /*!< 0x00020000 */

+#define HRTIM_BMTRGR_TCCMP1           HRTIM_BMTRGR_TCCMP1_Msk                  /*!< Timer C compare 1 */

+#define HRTIM_BMTRGR_TCCMP2_Pos       (18U)

+#define HRTIM_BMTRGR_TCCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TCCMP2_Pos)       /*!< 0x00040000 */

+#define HRTIM_BMTRGR_TCCMP2           HRTIM_BMTRGR_TCCMP2_Msk                  /*!< Timer C compare 2 */

+#define HRTIM_BMTRGR_TDRST_Pos        (19U)

+#define HRTIM_BMTRGR_TDRST_Msk        (0x1UL << HRTIM_BMTRGR_TDRST_Pos)        /*!< 0x00080000 */

+#define HRTIM_BMTRGR_TDRST            HRTIM_BMTRGR_TDRST_Msk                   /*!< Timer D reset  */

+#define HRTIM_BMTRGR_TDREP_Pos        (20U)

+#define HRTIM_BMTRGR_TDREP_Msk        (0x1UL << HRTIM_BMTRGR_TDREP_Pos)        /*!< 0x00100000 */

+#define HRTIM_BMTRGR_TDREP            HRTIM_BMTRGR_TDREP_Msk                   /*!< Timer D repetition  */

+#define HRTIM_BMTRGR_TDCMP1_Pos       (21U)

+#define HRTIM_BMTRGR_TDCMP1_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP1_Pos)       /*!< 0x00200000 */

+#define HRTIM_BMTRGR_TDCMP1           HRTIM_BMTRGR_TDCMP1_Msk                  /*!< Timer D compare 1 */

+#define HRTIM_BMTRGR_TDCMP2_Pos       (22U)

+#define HRTIM_BMTRGR_TDCMP2_Msk       (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos)       /*!< 0x00400000 */

+#define HRTIM_BMTRGR_TDCMP2           HRTIM_BMTRGR_TDCMP2_Msk                  /*!< Timer D compare 2 */

+#define HRTIM_BMTRGR_TERST_Pos        (23U)

+#define HRTIM_BMTRGR_TERST_Msk        (0x1UL << HRTIM_BMTRGR_TERST_Pos)        /*!< 0x00800000 */

+#define HRTIM_BMTRGR_TERST            HRTIM_BMTRGR_TERST_Msk                   /*!< Timer E reset  */

+#define HRTIM_BMTRGR_TEREP_Pos        (24U)

+#define HRTIM_BMTRGR_TEREP_Msk        (0x1UL << HRTIM_BMTRGR_TEREP_Pos)        /*!< 0x01000000 */

+#define HRTIM_BMTRGR_TEREP            HRTIM_BMTRGR_TEREP_Msk                   /*!< Timer E repetition  */

+#define HRTIM_BMTRGR_TECMP1_Pos       (25U)

+#define HRTIM_BMTRGR_TECMP1_Msk       (0x1UL << HRTIM_BMTRGR_TECMP1_Pos)       /*!< 0x02000000 */

+#define HRTIM_BMTRGR_TECMP1           HRTIM_BMTRGR_TECMP1_Msk                  /*!< Timer E compare 1 */

+#define HRTIM_BMTRGR_TECMP2_Pos       (26U)

+#define HRTIM_BMTRGR_TECMP2_Msk       (0x1UL << HRTIM_BMTRGR_TECMP2_Pos)       /*!< 0x04000000 */

+#define HRTIM_BMTRGR_TECMP2           HRTIM_BMTRGR_TECMP2_Msk                  /*!< Timer E compare 2 */

+#define HRTIM_BMTRGR_TAEEV7_Pos       (27U)

+#define HRTIM_BMTRGR_TAEEV7_Msk       (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos)       /*!< 0x08000000 */

+#define HRTIM_BMTRGR_TAEEV7           HRTIM_BMTRGR_TAEEV7_Msk                  /*!< Timer A period following External Event7  */

+#define HRTIM_BMTRGR_TDEEV8_Pos       (28U)

+#define HRTIM_BMTRGR_TDEEV8_Msk       (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos)       /*!< 0x10000000 */

+#define HRTIM_BMTRGR_TDEEV8           HRTIM_BMTRGR_TDEEV8_Msk                  /*!< Timer D period following External Event8  */

+#define HRTIM_BMTRGR_EEV7_Pos         (29U)

+#define HRTIM_BMTRGR_EEV7_Msk         (0x1UL << HRTIM_BMTRGR_EEV7_Pos)         /*!< 0x20000000 */

+#define HRTIM_BMTRGR_EEV7             HRTIM_BMTRGR_EEV7_Msk                    /*!< External Event 7 */

+#define HRTIM_BMTRGR_EEV8_Pos         (30U)

+#define HRTIM_BMTRGR_EEV8_Msk         (0x1UL << HRTIM_BMTRGR_EEV8_Pos)         /*!< 0x40000000 */

+#define HRTIM_BMTRGR_EEV8             HRTIM_BMTRGR_EEV8_Msk                    /*!< External Event 8 */

+#define HRTIM_BMTRGR_OCHPEV_Pos       (31U)

+#define HRTIM_BMTRGR_OCHPEV_Msk       (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos)       /*!< 0x80000000 */

+#define HRTIM_BMTRGR_OCHPEV           HRTIM_BMTRGR_OCHPEV_Msk                  /*!< on-chip Event */

+

+/*******************  Bit definition for HRTIM_BMCMPR register  ***************/

+#define HRTIM_BMCMPR_BMCMPR_Pos       (0U)

+#define HRTIM_BMCMPR_BMCMPR_Msk       (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos)    /*!< 0x0000FFFF */

+#define HRTIM_BMCMPR_BMCMPR           HRTIM_BMCMPR_BMCMPR_Msk                  /*!<!<Burst Compare Value */

+

+/*******************  Bit definition for HRTIM_BMPER register  ****************/

+#define HRTIM_BMPER_BMPER_Pos         (0U)

+#define HRTIM_BMPER_BMPER_Msk         (0xFFFFUL << HRTIM_BMPER_BMPER_Pos)      /*!< 0x0000FFFF */

+#define HRTIM_BMPER_BMPER             HRTIM_BMPER_BMPER_Msk                    /*!<!<Burst period Value */

+

+/*******************  Bit definition for HRTIM_EECR1 register  ****************/

+#define HRTIM_EECR1_EE1SRC_Pos        (0U)

+#define HRTIM_EECR1_EE1SRC_Msk        (0x3UL << HRTIM_EECR1_EE1SRC_Pos)        /*!< 0x00000003 */

+#define HRTIM_EECR1_EE1SRC            HRTIM_EECR1_EE1SRC_Msk                   /*!< External event 1 source */

+#define HRTIM_EECR1_EE1SRC_0          (0x1UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000001 */

+#define HRTIM_EECR1_EE1SRC_1          (0x2UL << HRTIM_EECR1_EE1SRC_Pos)         /*!< 0x00000002 */

+#define HRTIM_EECR1_EE1POL_Pos        (2U)

+#define HRTIM_EECR1_EE1POL_Msk        (0x1UL << HRTIM_EECR1_EE1POL_Pos)        /*!< 0x00000004 */

+#define HRTIM_EECR1_EE1POL            HRTIM_EECR1_EE1POL_Msk                   /*!< External event 1 Polarity */

+#define HRTIM_EECR1_EE1SNS_Pos        (3U)

+#define HRTIM_EECR1_EE1SNS_Msk        (0x3UL << HRTIM_EECR1_EE1SNS_Pos)        /*!< 0x00000018 */

+#define HRTIM_EECR1_EE1SNS            HRTIM_EECR1_EE1SNS_Msk                   /*!< External event 1 sensitivity */

+#define HRTIM_EECR1_EE1SNS_0          (0x1UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000008 */

+#define HRTIM_EECR1_EE1SNS_1          (0x2UL << HRTIM_EECR1_EE1SNS_Pos)         /*!< 0x00000010 */

+#define HRTIM_EECR1_EE1FAST_Pos       (5U)

+#define HRTIM_EECR1_EE1FAST_Msk       (0x1UL << HRTIM_EECR1_EE1FAST_Pos)       /*!< 0x00000020 */

+#define HRTIM_EECR1_EE1FAST           HRTIM_EECR1_EE1FAST_Msk                  /*!< External event 1 Fast mode */

+

+#define HRTIM_EECR1_EE2SRC_Pos        (6U)

+#define HRTIM_EECR1_EE2SRC_Msk        (0x3UL << HRTIM_EECR1_EE2SRC_Pos)        /*!< 0x000000C0 */

+#define HRTIM_EECR1_EE2SRC            HRTIM_EECR1_EE2SRC_Msk                   /*!< External event 2 source */

+#define HRTIM_EECR1_EE2SRC_0          (0x1UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000040 */

+#define HRTIM_EECR1_EE2SRC_1          (0x2UL << HRTIM_EECR1_EE2SRC_Pos)         /*!< 0x00000080 */

+#define HRTIM_EECR1_EE2POL_Pos        (8U)

+#define HRTIM_EECR1_EE2POL_Msk        (0x1UL << HRTIM_EECR1_EE2POL_Pos)        /*!< 0x00000100 */

+#define HRTIM_EECR1_EE2POL            HRTIM_EECR1_EE2POL_Msk                   /*!< External event 2 Polarity */

+#define HRTIM_EECR1_EE2SNS_Pos        (9U)

+#define HRTIM_EECR1_EE2SNS_Msk        (0x3UL << HRTIM_EECR1_EE2SNS_Pos)        /*!< 0x00000600 */

+#define HRTIM_EECR1_EE2SNS            HRTIM_EECR1_EE2SNS_Msk                   /*!< External event 2 sensitivity */

+#define HRTIM_EECR1_EE2SNS_0          (0x1UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000200 */

+#define HRTIM_EECR1_EE2SNS_1          (0x2UL << HRTIM_EECR1_EE2SNS_Pos)         /*!< 0x00000400 */

+#define HRTIM_EECR1_EE2FAST_Pos       (11U)

+#define HRTIM_EECR1_EE2FAST_Msk       (0x1UL << HRTIM_EECR1_EE2FAST_Pos)       /*!< 0x00000800 */

+#define HRTIM_EECR1_EE2FAST           HRTIM_EECR1_EE2FAST_Msk                  /*!< External event 2 Fast mode */

+

+#define HRTIM_EECR1_EE3SRC_Pos        (12U)

+#define HRTIM_EECR1_EE3SRC_Msk        (0x3UL << HRTIM_EECR1_EE3SRC_Pos)        /*!< 0x00003000 */

+#define HRTIM_EECR1_EE3SRC            HRTIM_EECR1_EE3SRC_Msk                   /*!< External event 3 source */

+#define HRTIM_EECR1_EE3SRC_0          (0x1UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00001000 */

+#define HRTIM_EECR1_EE3SRC_1          (0x2UL << HRTIM_EECR1_EE3SRC_Pos)         /*!< 0x00002000 */

+#define HRTIM_EECR1_EE3POL_Pos        (14U)

+#define HRTIM_EECR1_EE3POL_Msk        (0x1UL << HRTIM_EECR1_EE3POL_Pos)        /*!< 0x00004000 */

+#define HRTIM_EECR1_EE3POL            HRTIM_EECR1_EE3POL_Msk                   /*!< External event 3 Polarity */

+#define HRTIM_EECR1_EE3SNS_Pos        (15U)

+#define HRTIM_EECR1_EE3SNS_Msk        (0x3UL << HRTIM_EECR1_EE3SNS_Pos)        /*!< 0x00018000 */

+#define HRTIM_EECR1_EE3SNS            HRTIM_EECR1_EE3SNS_Msk                   /*!< External event 3 sensitivity */

+#define HRTIM_EECR1_EE3SNS_0          (0x1UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00008000 */

+#define HRTIM_EECR1_EE3SNS_1          (0x2UL << HRTIM_EECR1_EE3SNS_Pos)         /*!< 0x00010000 */

+#define HRTIM_EECR1_EE3FAST_Pos       (17U)

+#define HRTIM_EECR1_EE3FAST_Msk       (0x1UL << HRTIM_EECR1_EE3FAST_Pos)       /*!< 0x00020000 */

+#define HRTIM_EECR1_EE3FAST           HRTIM_EECR1_EE3FAST_Msk                  /*!< External event 3 Fast mode */

+

+#define HRTIM_EECR1_EE4SRC_Pos        (18U)

+#define HRTIM_EECR1_EE4SRC_Msk        (0x3UL << HRTIM_EECR1_EE4SRC_Pos)        /*!< 0x000C0000 */

+#define HRTIM_EECR1_EE4SRC            HRTIM_EECR1_EE4SRC_Msk                   /*!< External event 4 source */

+#define HRTIM_EECR1_EE4SRC_0          (0x1UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00040000 */

+#define HRTIM_EECR1_EE4SRC_1          (0x2UL << HRTIM_EECR1_EE4SRC_Pos)         /*!< 0x00080000 */

+#define HRTIM_EECR1_EE4POL_Pos        (20U)

+#define HRTIM_EECR1_EE4POL_Msk        (0x1UL << HRTIM_EECR1_EE4POL_Pos)        /*!< 0x00100000 */

+#define HRTIM_EECR1_EE4POL            HRTIM_EECR1_EE4POL_Msk                   /*!< External event 4 Polarity */

+#define HRTIM_EECR1_EE4SNS_Pos        (21U)

+#define HRTIM_EECR1_EE4SNS_Msk        (0x3UL << HRTIM_EECR1_EE4SNS_Pos)        /*!< 0x00600000 */

+#define HRTIM_EECR1_EE4SNS            HRTIM_EECR1_EE4SNS_Msk                   /*!< External event 4 sensitivity */

+#define HRTIM_EECR1_EE4SNS_0          (0x1UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00200000 */

+#define HRTIM_EECR1_EE4SNS_1          (0x2UL << HRTIM_EECR1_EE4SNS_Pos)         /*!< 0x00400000 */

+#define HRTIM_EECR1_EE4FAST_Pos       (23U)

+#define HRTIM_EECR1_EE4FAST_Msk       (0x1UL << HRTIM_EECR1_EE4FAST_Pos)       /*!< 0x00800000 */

+#define HRTIM_EECR1_EE4FAST           HRTIM_EECR1_EE4FAST_Msk                  /*!< External event 4 Fast mode */

+

+#define HRTIM_EECR1_EE5SRC_Pos        (24U)

+#define HRTIM_EECR1_EE5SRC_Msk        (0x3UL << HRTIM_EECR1_EE5SRC_Pos)        /*!< 0x03000000 */

+#define HRTIM_EECR1_EE5SRC            HRTIM_EECR1_EE5SRC_Msk                   /*!< External event 5 source */

+#define HRTIM_EECR1_EE5SRC_0          (0x1UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x01000000 */

+#define HRTIM_EECR1_EE5SRC_1          (0x2UL << HRTIM_EECR1_EE5SRC_Pos)         /*!< 0x02000000 */

+#define HRTIM_EECR1_EE5POL_Pos        (26U)

+#define HRTIM_EECR1_EE5POL_Msk        (0x1UL << HRTIM_EECR1_EE5POL_Pos)        /*!< 0x04000000 */

+#define HRTIM_EECR1_EE5POL            HRTIM_EECR1_EE5POL_Msk                   /*!< External event 5 Polarity */

+#define HRTIM_EECR1_EE5SNS_Pos        (27U)

+#define HRTIM_EECR1_EE5SNS_Msk        (0x3UL << HRTIM_EECR1_EE5SNS_Pos)        /*!< 0x18000000 */

+#define HRTIM_EECR1_EE5SNS            HRTIM_EECR1_EE5SNS_Msk                   /*!< External event 5 sensitivity */

+#define HRTIM_EECR1_EE5SNS_0          (0x1UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x08000000 */

+#define HRTIM_EECR1_EE5SNS_1          (0x2UL << HRTIM_EECR1_EE5SNS_Pos)         /*!< 0x10000000 */

+#define HRTIM_EECR1_EE5FAST_Pos       (29U)

+#define HRTIM_EECR1_EE5FAST_Msk       (0x1UL << HRTIM_EECR1_EE5FAST_Pos)       /*!< 0x20000000 */

+#define HRTIM_EECR1_EE5FAST           HRTIM_EECR1_EE5FAST_Msk                  /*!< External event 5 Fast mode */

+

+/*******************  Bit definition for HRTIM_EECR2 register  ****************/

+#define HRTIM_EECR2_EE6SRC_Pos        (0U)

+#define HRTIM_EECR2_EE6SRC_Msk        (0x3UL << HRTIM_EECR2_EE6SRC_Pos)        /*!< 0x00000003 */

+#define HRTIM_EECR2_EE6SRC            HRTIM_EECR2_EE6SRC_Msk                   /*!< External event 6 source */

+#define HRTIM_EECR2_EE6SRC_0          (0x1UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000001 */

+#define HRTIM_EECR2_EE6SRC_1          (0x2UL << HRTIM_EECR2_EE6SRC_Pos)         /*!< 0x00000002 */

+#define HRTIM_EECR2_EE6POL_Pos        (2U)

+#define HRTIM_EECR2_EE6POL_Msk        (0x1UL << HRTIM_EECR2_EE6POL_Pos)        /*!< 0x00000004 */

+#define HRTIM_EECR2_EE6POL            HRTIM_EECR2_EE6POL_Msk                   /*!< External event 6 Polarity */

+#define HRTIM_EECR2_EE6SNS_Pos        (3U)

+#define HRTIM_EECR2_EE6SNS_Msk        (0x3UL << HRTIM_EECR2_EE6SNS_Pos)        /*!< 0x00000018 */

+#define HRTIM_EECR2_EE6SNS            HRTIM_EECR2_EE6SNS_Msk                   /*!< External event 6 sensitivity */

+#define HRTIM_EECR2_EE6SNS_0          (0x1UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000008 */

+#define HRTIM_EECR2_EE6SNS_1          (0x2UL << HRTIM_EECR2_EE6SNS_Pos)         /*!< 0x00000010 */

+

+#define HRTIM_EECR2_EE7SRC_Pos        (6U)

+#define HRTIM_EECR2_EE7SRC_Msk        (0x3UL << HRTIM_EECR2_EE7SRC_Pos)        /*!< 0x000000C0 */

+#define HRTIM_EECR2_EE7SRC            HRTIM_EECR2_EE7SRC_Msk                   /*!< External event 7 source */

+#define HRTIM_EECR2_EE7SRC_0          (0x1UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000040 */

+#define HRTIM_EECR2_EE7SRC_1          (0x2UL << HRTIM_EECR2_EE7SRC_Pos)         /*!< 0x00000080 */

+#define HRTIM_EECR2_EE7POL_Pos        (8U)

+#define HRTIM_EECR2_EE7POL_Msk        (0x1UL << HRTIM_EECR2_EE7POL_Pos)        /*!< 0x00000100 */

+#define HRTIM_EECR2_EE7POL            HRTIM_EECR2_EE7POL_Msk                   /*!< External event 7 Polarity */

+#define HRTIM_EECR2_EE7SNS_Pos        (9U)

+#define HRTIM_EECR2_EE7SNS_Msk        (0x3UL << HRTIM_EECR2_EE7SNS_Pos)        /*!< 0x00000600 */

+#define HRTIM_EECR2_EE7SNS            HRTIM_EECR2_EE7SNS_Msk                   /*!< External event 7 sensitivity */

+#define HRTIM_EECR2_EE7SNS_0          (0x1UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000200 */

+#define HRTIM_EECR2_EE7SNS_1          (0x2UL << HRTIM_EECR2_EE7SNS_Pos)         /*!< 0x00000400 */

+

+#define HRTIM_EECR2_EE8SRC_Pos        (12U)

+#define HRTIM_EECR2_EE8SRC_Msk        (0x3UL << HRTIM_EECR2_EE8SRC_Pos)        /*!< 0x00003000 */

+#define HRTIM_EECR2_EE8SRC            HRTIM_EECR2_EE8SRC_Msk                   /*!< External event 8 source */

+#define HRTIM_EECR2_EE8SRC_0          (0x1UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00001000 */

+#define HRTIM_EECR2_EE8SRC_1          (0x2UL << HRTIM_EECR2_EE8SRC_Pos)         /*!< 0x00002000 */

+#define HRTIM_EECR2_EE8POL_Pos        (14U)

+#define HRTIM_EECR2_EE8POL_Msk        (0x1UL << HRTIM_EECR2_EE8POL_Pos)        /*!< 0x00004000 */

+#define HRTIM_EECR2_EE8POL            HRTIM_EECR2_EE8POL_Msk                   /*!< External event 8 Polarity */

+#define HRTIM_EECR2_EE8SNS_Pos        (15U)

+#define HRTIM_EECR2_EE8SNS_Msk        (0x3UL << HRTIM_EECR2_EE8SNS_Pos)        /*!< 0x00018000 */

+#define HRTIM_EECR2_EE8SNS            HRTIM_EECR2_EE8SNS_Msk                   /*!< External event 8 sensitivity */

+#define HRTIM_EECR2_EE8SNS_0          (0x1UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00008000 */

+#define HRTIM_EECR2_EE8SNS_1          (0x2UL << HRTIM_EECR2_EE8SNS_Pos)         /*!< 0x00010000 */

+

+#define HRTIM_EECR2_EE9SRC_Pos        (18U)

+#define HRTIM_EECR2_EE9SRC_Msk        (0x3UL << HRTIM_EECR2_EE9SRC_Pos)        /*!< 0x000C0000 */

+#define HRTIM_EECR2_EE9SRC            HRTIM_EECR2_EE9SRC_Msk                   /*!< External event 9 source */

+#define HRTIM_EECR2_EE9SRC_0          (0x1UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00040000 */

+#define HRTIM_EECR2_EE9SRC_1          (0x2UL << HRTIM_EECR2_EE9SRC_Pos)         /*!< 0x00080000 */

+#define HRTIM_EECR2_EE9POL_Pos        (20U)

+#define HRTIM_EECR2_EE9POL_Msk        (0x1UL << HRTIM_EECR2_EE9POL_Pos)        /*!< 0x00100000 */

+#define HRTIM_EECR2_EE9POL            HRTIM_EECR2_EE9POL_Msk                   /*!< External event 9 Polarity */

+#define HRTIM_EECR2_EE9SNS_Pos        (21U)

+#define HRTIM_EECR2_EE9SNS_Msk        (0x3UL << HRTIM_EECR2_EE9SNS_Pos)        /*!< 0x00600000 */

+#define HRTIM_EECR2_EE9SNS            HRTIM_EECR2_EE9SNS_Msk                   /*!< External event 9 sensitivity */

+#define HRTIM_EECR2_EE9SNS_0          (0x1UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00200000 */

+#define HRTIM_EECR2_EE9SNS_1          (0x2UL << HRTIM_EECR2_EE9SNS_Pos)         /*!< 0x00400000 */

+

+#define HRTIM_EECR2_EE10SRC_Pos       (24U)

+#define HRTIM_EECR2_EE10SRC_Msk       (0x3UL << HRTIM_EECR2_EE10SRC_Pos)       /*!< 0x03000000 */

+#define HRTIM_EECR2_EE10SRC           HRTIM_EECR2_EE10SRC_Msk                  /*!< External event 10 source */

+#define HRTIM_EECR2_EE10SRC_0         (0x1UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x01000000 */

+#define HRTIM_EECR2_EE10SRC_1         (0x2UL << HRTIM_EECR2_EE10SRC_Pos)        /*!< 0x02000000 */

+#define HRTIM_EECR2_EE10POL_Pos       (26U)

+#define HRTIM_EECR2_EE10POL_Msk       (0x1UL << HRTIM_EECR2_EE10POL_Pos)       /*!< 0x04000000 */

+#define HRTIM_EECR2_EE10POL           HRTIM_EECR2_EE10POL_Msk                  /*!< External event 10 Polarity */

+#define HRTIM_EECR2_EE10SNS_Pos       (27U)

+#define HRTIM_EECR2_EE10SNS_Msk       (0x3UL << HRTIM_EECR2_EE10SNS_Pos)       /*!< 0x18000000 */

+#define HRTIM_EECR2_EE10SNS           HRTIM_EECR2_EE10SNS_Msk                  /*!< External event 10 sensitivity */

+#define HRTIM_EECR2_EE10SNS_0         (0x1UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x08000000 */

+#define HRTIM_EECR2_EE10SNS_1         (0x2UL << HRTIM_EECR2_EE10SNS_Pos)        /*!< 0x10000000 */

+

+/*******************  Bit definition for HRTIM_EECR3 register  ****************/

+#define HRTIM_EECR3_EE6F_Pos          (0U)

+#define HRTIM_EECR3_EE6F_Msk          (0xFUL << HRTIM_EECR3_EE6F_Pos)          /*!< 0x0000000F */

+#define HRTIM_EECR3_EE6F              HRTIM_EECR3_EE6F_Msk                     /*!< External event 6 filter */

+#define HRTIM_EECR3_EE6F_0            (0x1UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000001 */

+#define HRTIM_EECR3_EE6F_1            (0x2UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000002 */

+#define HRTIM_EECR3_EE6F_2            (0x4UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000004 */

+#define HRTIM_EECR3_EE6F_3            (0x8UL << HRTIM_EECR3_EE6F_Pos)           /*!< 0x00000008 */

+#define HRTIM_EECR3_EE7F_Pos          (6U)

+#define HRTIM_EECR3_EE7F_Msk          (0xFUL << HRTIM_EECR3_EE7F_Pos)          /*!< 0x000003C0 */

+#define HRTIM_EECR3_EE7F              HRTIM_EECR3_EE7F_Msk                     /*!< External event 7 filter */

+#define HRTIM_EECR3_EE7F_0            (0x1UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000040 */

+#define HRTIM_EECR3_EE7F_1            (0x2UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000080 */

+#define HRTIM_EECR3_EE7F_2            (0x4UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000100 */

+#define HRTIM_EECR3_EE7F_3            (0x8UL << HRTIM_EECR3_EE7F_Pos)           /*!< 0x00000200 */

+#define HRTIM_EECR3_EE8F_Pos          (12U)

+#define HRTIM_EECR3_EE8F_Msk          (0xFUL << HRTIM_EECR3_EE8F_Pos)          /*!< 0x0000F000 */

+#define HRTIM_EECR3_EE8F              HRTIM_EECR3_EE8F_Msk                     /*!< External event 8 filter */

+#define HRTIM_EECR3_EE8F_0            (0x1UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00001000 */

+#define HRTIM_EECR3_EE8F_1            (0x2UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00002000 */

+#define HRTIM_EECR3_EE8F_2            (0x4UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00004000 */

+#define HRTIM_EECR3_EE8F_3            (0x8UL << HRTIM_EECR3_EE8F_Pos)           /*!< 0x00008000 */

+#define HRTIM_EECR3_EE9F_Pos          (18U)

+#define HRTIM_EECR3_EE9F_Msk          (0xFUL << HRTIM_EECR3_EE9F_Pos)          /*!< 0x003C0000 */

+#define HRTIM_EECR3_EE9F              HRTIM_EECR3_EE9F_Msk                     /*!< External event 9 filter */

+#define HRTIM_EECR3_EE9F_0            (0x1UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00040000 */

+#define HRTIM_EECR3_EE9F_1            (0x2UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00080000 */

+#define HRTIM_EECR3_EE9F_2            (0x4UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00100000 */

+#define HRTIM_EECR3_EE9F_3            (0x8UL << HRTIM_EECR3_EE9F_Pos)           /*!< 0x00200000 */

+#define HRTIM_EECR3_EE10F_Pos         (24U)

+#define HRTIM_EECR3_EE10F_Msk         (0xFUL << HRTIM_EECR3_EE10F_Pos)         /*!< 0x0F000000 */

+#define HRTIM_EECR3_EE10F             HRTIM_EECR3_EE10F_Msk                    /*!< External event 10 filter */

+#define HRTIM_EECR3_EE10F_0           (0x1UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x01000000 */

+#define HRTIM_EECR3_EE10F_1           (0x2UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x02000000 */

+#define HRTIM_EECR3_EE10F_2           (0x4UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x04000000 */

+#define HRTIM_EECR3_EE10F_3           (0x8UL << HRTIM_EECR3_EE10F_Pos)          /*!< 0x08000000 */

+#define HRTIM_EECR3_EEVSD_Pos         (30U)

+#define HRTIM_EECR3_EEVSD_Msk         (0x3UL << HRTIM_EECR3_EEVSD_Pos)         /*!< 0xC0000000 */

+#define HRTIM_EECR3_EEVSD             HRTIM_EECR3_EEVSD_Msk                    /*!< External event sampling clock division */

+#define HRTIM_EECR3_EEVSD_0           (0x1UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x40000000 */

+#define HRTIM_EECR3_EEVSD_1           (0x2UL << HRTIM_EECR3_EEVSD_Pos)          /*!< 0x80000000 */

+

+/*******************  Bit definition for HRTIM_ADC1R register  ****************/

+#define HRTIM_ADC1R_AD1MC1_Pos        (0U)

+#define HRTIM_ADC1R_AD1MC1_Msk        (0x1UL << HRTIM_ADC1R_AD1MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC1R_AD1MC1            HRTIM_ADC1R_AD1MC1_Msk                   /*!< ADC Trigger 1 on master compare 1 */

+#define HRTIM_ADC1R_AD1MC2_Pos        (1U)

+#define HRTIM_ADC1R_AD1MC2_Msk        (0x1UL << HRTIM_ADC1R_AD1MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC1R_AD1MC2            HRTIM_ADC1R_AD1MC2_Msk                   /*!< ADC Trigger 1 on master compare 2 */

+#define HRTIM_ADC1R_AD1MC3_Pos        (2U)

+#define HRTIM_ADC1R_AD1MC3_Msk        (0x1UL << HRTIM_ADC1R_AD1MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC1R_AD1MC3            HRTIM_ADC1R_AD1MC3_Msk                   /*!< ADC Trigger 1 on master compare 3 */

+#define HRTIM_ADC1R_AD1MC4_Pos        (3U)

+#define HRTIM_ADC1R_AD1MC4_Msk        (0x1UL << HRTIM_ADC1R_AD1MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC1R_AD1MC4            HRTIM_ADC1R_AD1MC4_Msk                   /*!< ADC Trigger 1 on master compare 4 */

+#define HRTIM_ADC1R_AD1MPER_Pos       (4U)

+#define HRTIM_ADC1R_AD1MPER_Msk       (0x1UL << HRTIM_ADC1R_AD1MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC1R_AD1MPER           HRTIM_ADC1R_AD1MPER_Msk                  /*!< ADC Trigger 1 on master period */

+#define HRTIM_ADC1R_AD1EEV1_Pos       (5U)

+#define HRTIM_ADC1R_AD1EEV1_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC1R_AD1EEV1           HRTIM_ADC1R_AD1EEV1_Msk                  /*!< ADC Trigger 1 on external event 1 */

+#define HRTIM_ADC1R_AD1EEV2_Pos       (6U)

+#define HRTIM_ADC1R_AD1EEV2_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC1R_AD1EEV2           HRTIM_ADC1R_AD1EEV2_Msk                  /*!< ADC Trigger 1 on external event 2 */

+#define HRTIM_ADC1R_AD1EEV3_Pos       (7U)

+#define HRTIM_ADC1R_AD1EEV3_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC1R_AD1EEV3           HRTIM_ADC1R_AD1EEV3_Msk                  /*!< ADC Trigger 1 on external event 3 */

+#define HRTIM_ADC1R_AD1EEV4_Pos       (8U)

+#define HRTIM_ADC1R_AD1EEV4_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC1R_AD1EEV4           HRTIM_ADC1R_AD1EEV4_Msk                  /*!< ADC Trigger 1 on external event 4 */

+#define HRTIM_ADC1R_AD1EEV5_Pos       (9U)

+#define HRTIM_ADC1R_AD1EEV5_Msk       (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos)       /*!< 0x00000200 */

+#define HRTIM_ADC1R_AD1EEV5           HRTIM_ADC1R_AD1EEV5_Msk                  /*!< ADC Trigger 1 on external event 5 */

+#define HRTIM_ADC1R_AD1TAC2_Pos       (10U)

+#define HRTIM_ADC1R_AD1TAC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC1R_AD1TAC2           HRTIM_ADC1R_AD1TAC2_Msk                  /*!< ADC Trigger 1 on Timer A compare 2 */

+#define HRTIM_ADC1R_AD1TAC3_Pos       (11U)

+#define HRTIM_ADC1R_AD1TAC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC1R_AD1TAC3           HRTIM_ADC1R_AD1TAC3_Msk                  /*!< ADC Trigger 1 on Timer A compare 3 */

+#define HRTIM_ADC1R_AD1TAC4_Pos       (12U)

+#define HRTIM_ADC1R_AD1TAC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC1R_AD1TAC4           HRTIM_ADC1R_AD1TAC4_Msk                  /*!< ADC Trigger 1 on Timer A compare 4 */

+#define HRTIM_ADC1R_AD1TAPER_Pos      (13U)

+#define HRTIM_ADC1R_AD1TAPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC1R_AD1TAPER          HRTIM_ADC1R_AD1TAPER_Msk                 /*!< ADC Trigger 1 on Timer A period */

+#define HRTIM_ADC1R_AD1TARST_Pos      (14U)

+#define HRTIM_ADC1R_AD1TARST_Msk      (0x1UL << HRTIM_ADC1R_AD1TARST_Pos)      /*!< 0x00004000 */

+#define HRTIM_ADC1R_AD1TARST          HRTIM_ADC1R_AD1TARST_Msk                 /*!< ADC Trigger 1 on Timer A reset */

+#define HRTIM_ADC1R_AD1TBC2_Pos       (15U)

+#define HRTIM_ADC1R_AD1TBC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC2_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC1R_AD1TBC2           HRTIM_ADC1R_AD1TBC2_Msk                  /*!< ADC Trigger 1 on Timer B compare 2 */

+#define HRTIM_ADC1R_AD1TBC3_Pos       (16U)

+#define HRTIM_ADC1R_AD1TBC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC1R_AD1TBC3           HRTIM_ADC1R_AD1TBC3_Msk                  /*!< ADC Trigger 1 on Timer B compare 3 */

+#define HRTIM_ADC1R_AD1TBC4_Pos       (17U)

+#define HRTIM_ADC1R_AD1TBC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos)       /*!< 0x00020000 */

+#define HRTIM_ADC1R_AD1TBC4           HRTIM_ADC1R_AD1TBC4_Msk                  /*!< ADC Trigger 1 on Timer B compare 4 */

+#define HRTIM_ADC1R_AD1TBPER_Pos      (18U)

+#define HRTIM_ADC1R_AD1TBPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos)      /*!< 0x00040000 */

+#define HRTIM_ADC1R_AD1TBPER          HRTIM_ADC1R_AD1TBPER_Msk                 /*!< ADC Trigger 1 on Timer B period */

+#define HRTIM_ADC1R_AD1TBRST_Pos      (19U)

+#define HRTIM_ADC1R_AD1TBRST_Msk      (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos)      /*!< 0x00080000 */

+#define HRTIM_ADC1R_AD1TBRST          HRTIM_ADC1R_AD1TBRST_Msk                 /*!< ADC Trigger 1 on Timer B reset */

+#define HRTIM_ADC1R_AD1TCC2_Pos       (20U)

+#define HRTIM_ADC1R_AD1TCC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC2_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC1R_AD1TCC2           HRTIM_ADC1R_AD1TCC2_Msk                  /*!< ADC Trigger 1 on Timer C compare 2 */

+#define HRTIM_ADC1R_AD1TCC3_Pos       (21U)

+#define HRTIM_ADC1R_AD1TCC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos)       /*!< 0x00200000 */

+#define HRTIM_ADC1R_AD1TCC3           HRTIM_ADC1R_AD1TCC3_Msk                  /*!< ADC Trigger 1 on Timer C compare 3 */

+#define HRTIM_ADC1R_AD1TCC4_Pos       (22U)

+#define HRTIM_ADC1R_AD1TCC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos)       /*!< 0x00400000 */

+#define HRTIM_ADC1R_AD1TCC4           HRTIM_ADC1R_AD1TCC4_Msk                  /*!< ADC Trigger 1 on Timer C compare 4 */

+#define HRTIM_ADC1R_AD1TCPER_Pos      (23U)

+#define HRTIM_ADC1R_AD1TCPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos)      /*!< 0x00800000 */

+#define HRTIM_ADC1R_AD1TCPER          HRTIM_ADC1R_AD1TCPER_Msk                 /*!< ADC Trigger 1 on Timer C period */

+#define HRTIM_ADC1R_AD1TDC2_Pos       (24U)

+#define HRTIM_ADC1R_AD1TDC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC2_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC1R_AD1TDC2           HRTIM_ADC1R_AD1TDC2_Msk                  /*!< ADC Trigger 1 on Timer D compare 2 */

+#define HRTIM_ADC1R_AD1TDC3_Pos       (25U)

+#define HRTIM_ADC1R_AD1TDC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC1R_AD1TDC3           HRTIM_ADC1R_AD1TDC3_Msk                  /*!< ADC Trigger 1 on Timer D compare 3 */

+#define HRTIM_ADC1R_AD1TDC4_Pos       (26U)

+#define HRTIM_ADC1R_AD1TDC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos)       /*!< 0x04000000 */

+#define HRTIM_ADC1R_AD1TDC4           HRTIM_ADC1R_AD1TDC4_Msk                  /*!< ADC Trigger 1 on Timer D compare 4 */

+#define HRTIM_ADC1R_AD1TDPER_Pos      (27U)

+#define HRTIM_ADC1R_AD1TDPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC1R_AD1TDPER          HRTIM_ADC1R_AD1TDPER_Msk                 /*!< ADC Trigger 1 on Timer D period */

+#define HRTIM_ADC1R_AD1TEC2_Pos       (28U)

+#define HRTIM_ADC1R_AD1TEC2_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC1R_AD1TEC2           HRTIM_ADC1R_AD1TEC2_Msk                  /*!< ADC Trigger 1 on Timer E compare 2 */

+#define HRTIM_ADC1R_AD1TEC3_Pos       (29U)

+#define HRTIM_ADC1R_AD1TEC3_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC1R_AD1TEC3           HRTIM_ADC1R_AD1TEC3_Msk                  /*!< ADC Trigger 1 on Timer E compare 3 */

+#define HRTIM_ADC1R_AD1TEC4_Pos       (30U)

+#define HRTIM_ADC1R_AD1TEC4_Msk       (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC1R_AD1TEC4           HRTIM_ADC1R_AD1TEC4_Msk                  /*!< ADC Trigger 1 on Timer E compare 4 */

+#define HRTIM_ADC1R_AD1TEPER_Pos      (31U)

+#define HRTIM_ADC1R_AD1TEPER_Msk      (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC1R_AD1TEPER          HRTIM_ADC1R_AD1TEPER_Msk                 /*!< ADC Trigger 1 on Timer E period */

+

+/*******************  Bit definition for HRTIM_ADC2R register  ****************/

+#define HRTIM_ADC2R_AD2MC1_Pos        (0U)

+#define HRTIM_ADC2R_AD2MC1_Msk        (0x1UL << HRTIM_ADC2R_AD2MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC2R_AD2MC1            HRTIM_ADC2R_AD2MC1_Msk                   /*!< ADC Trigger 2 on master compare 1 */

+#define HRTIM_ADC2R_AD2MC2_Pos        (1U)

+#define HRTIM_ADC2R_AD2MC2_Msk        (0x1UL << HRTIM_ADC2R_AD2MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC2R_AD2MC2            HRTIM_ADC2R_AD2MC2_Msk                   /*!< ADC Trigger 2 on master compare 2 */

+#define HRTIM_ADC2R_AD2MC3_Pos        (2U)

+#define HRTIM_ADC2R_AD2MC3_Msk        (0x1UL << HRTIM_ADC2R_AD2MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC2R_AD2MC3            HRTIM_ADC2R_AD2MC3_Msk                   /*!< ADC Trigger 2 on master compare 3 */

+#define HRTIM_ADC2R_AD2MC4_Pos        (3U)

+#define HRTIM_ADC2R_AD2MC4_Msk        (0x1UL << HRTIM_ADC2R_AD2MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC2R_AD2MC4            HRTIM_ADC2R_AD2MC4_Msk                   /*!< ADC Trigger 2 on master compare 4 */

+#define HRTIM_ADC2R_AD2MPER_Pos       (4U)

+#define HRTIM_ADC2R_AD2MPER_Msk       (0x1UL << HRTIM_ADC2R_AD2MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC2R_AD2MPER           HRTIM_ADC2R_AD2MPER_Msk                  /*!< ADC Trigger 2 on master period */

+#define HRTIM_ADC2R_AD2EEV6_Pos       (5U)

+#define HRTIM_ADC2R_AD2EEV6_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC2R_AD2EEV6           HRTIM_ADC2R_AD2EEV6_Msk                  /*!< ADC Trigger 2 on external event 6 */

+#define HRTIM_ADC2R_AD2EEV7_Pos       (6U)

+#define HRTIM_ADC2R_AD2EEV7_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC2R_AD2EEV7           HRTIM_ADC2R_AD2EEV7_Msk                  /*!< ADC Trigger 2 on external event 7 */

+#define HRTIM_ADC2R_AD2EEV8_Pos       (7U)

+#define HRTIM_ADC2R_AD2EEV8_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC2R_AD2EEV8           HRTIM_ADC2R_AD2EEV8_Msk                  /*!< ADC Trigger 2 on external event 8 */

+#define HRTIM_ADC2R_AD2EEV9_Pos       (8U)

+#define HRTIM_ADC2R_AD2EEV9_Msk       (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC2R_AD2EEV9           HRTIM_ADC2R_AD2EEV9_Msk                  /*!< ADC Trigger 2 on external event 9 */

+#define HRTIM_ADC2R_AD2EEV10_Pos      (9U)

+#define HRTIM_ADC2R_AD2EEV10_Msk      (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos)      /*!< 0x00000200 */

+#define HRTIM_ADC2R_AD2EEV10          HRTIM_ADC2R_AD2EEV10_Msk                 /*!< ADC Trigger 2 on external event 10 */

+#define HRTIM_ADC2R_AD2TAC2_Pos       (10U)

+#define HRTIM_ADC2R_AD2TAC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC2R_AD2TAC2           HRTIM_ADC2R_AD2TAC2_Msk                  /*!< ADC Trigger 2 on Timer A compare 2 */

+#define HRTIM_ADC2R_AD2TAC3_Pos       (11U)

+#define HRTIM_ADC2R_AD2TAC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC2R_AD2TAC3           HRTIM_ADC2R_AD2TAC3_Msk                  /*!< ADC Trigger 2 on Timer A compare 3 */

+#define HRTIM_ADC2R_AD2TAC4_Pos       (12U)

+#define HRTIM_ADC2R_AD2TAC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC2R_AD2TAC4           HRTIM_ADC2R_AD2TAC4_Msk                  /*!< ADC Trigger 2 on Timer A compare 4*/

+#define HRTIM_ADC2R_AD2TAPER_Pos      (13U)

+#define HRTIM_ADC2R_AD2TAPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC2R_AD2TAPER          HRTIM_ADC2R_AD2TAPER_Msk                 /*!< ADC Trigger 2 on Timer A period */

+#define HRTIM_ADC2R_AD2TBC2_Pos       (14U)

+#define HRTIM_ADC2R_AD2TBC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos)       /*!< 0x00004000 */

+#define HRTIM_ADC2R_AD2TBC2           HRTIM_ADC2R_AD2TBC2_Msk                  /*!< ADC Trigger 2 on Timer B compare 2 */

+#define HRTIM_ADC2R_AD2TBC3_Pos       (15U)

+#define HRTIM_ADC2R_AD2TBC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC3_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC2R_AD2TBC3           HRTIM_ADC2R_AD2TBC3_Msk                  /*!< ADC Trigger 2 on Timer B compare 3 */

+#define HRTIM_ADC2R_AD2TBC4_Pos       (16U)

+#define HRTIM_ADC2R_AD2TBC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC2R_AD2TBC4           HRTIM_ADC2R_AD2TBC4_Msk                  /*!< ADC Trigger 2 on Timer B compare 4 */

+#define HRTIM_ADC2R_AD2TBPER_Pos      (17U)

+#define HRTIM_ADC2R_AD2TBPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos)      /*!< 0x00020000 */

+#define HRTIM_ADC2R_AD2TBPER          HRTIM_ADC2R_AD2TBPER_Msk                 /*!< ADC Trigger 2 on Timer B period */

+#define HRTIM_ADC2R_AD2TCC2_Pos       (18U)

+#define HRTIM_ADC2R_AD2TCC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos)       /*!< 0x00040000 */

+#define HRTIM_ADC2R_AD2TCC2           HRTIM_ADC2R_AD2TCC2_Msk                  /*!< ADC Trigger 2 on Timer C compare 2 */

+#define HRTIM_ADC2R_AD2TCC3_Pos       (19U)

+#define HRTIM_ADC2R_AD2TCC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC3_Pos)       /*!< 0x00080000 */

+#define HRTIM_ADC2R_AD2TCC3           HRTIM_ADC2R_AD2TCC3_Msk                  /*!< ADC Trigger 2 on Timer C compare 3 */

+#define HRTIM_ADC2R_AD2TCC4_Pos       (20U)

+#define HRTIM_ADC2R_AD2TCC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC2R_AD2TCC4           HRTIM_ADC2R_AD2TCC4_Msk                  /*!< ADC Trigger 2 on Timer C compare 4 */

+#define HRTIM_ADC2R_AD2TCPER_Pos      (21U)

+#define HRTIM_ADC2R_AD2TCPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos)      /*!< 0x00200000 */

+#define HRTIM_ADC2R_AD2TCPER          HRTIM_ADC2R_AD2TCPER_Msk                 /*!< ADC Trigger 2 on Timer C period */

+#define HRTIM_ADC2R_AD2TCRST_Pos      (22U)

+#define HRTIM_ADC2R_AD2TCRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos)      /*!< 0x00400000 */

+#define HRTIM_ADC2R_AD2TCRST          HRTIM_ADC2R_AD2TCRST_Msk                 /*!< ADC Trigger 2 on Timer C reset */

+#define HRTIM_ADC2R_AD2TDC2_Pos       (23U)

+#define HRTIM_ADC2R_AD2TDC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos)       /*!< 0x00800000 */

+#define HRTIM_ADC2R_AD2TDC2           HRTIM_ADC2R_AD2TDC2_Msk                  /*!< ADC Trigger 2 on Timer D compare 2 */

+#define HRTIM_ADC2R_AD2TDC3_Pos       (24U)

+#define HRTIM_ADC2R_AD2TDC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC3_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC2R_AD2TDC3           HRTIM_ADC2R_AD2TDC3_Msk                  /*!< ADC Trigger 2 on Timer D compare 3 */

+#define HRTIM_ADC2R_AD2TDC4_Pos       (25U)

+#define HRTIM_ADC2R_AD2TDC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC2R_AD2TDC4           HRTIM_ADC2R_AD2TDC4_Msk                  /*!< ADC Trigger 2 on Timer D compare 4*/

+#define HRTIM_ADC2R_AD2TDPER_Pos      (26U)

+#define HRTIM_ADC2R_AD2TDPER_Msk      (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos)      /*!< 0x04000000 */

+#define HRTIM_ADC2R_AD2TDPER          HRTIM_ADC2R_AD2TDPER_Msk                 /*!< ADC Trigger 2 on Timer D period */

+#define HRTIM_ADC2R_AD2TDRST_Pos      (27U)

+#define HRTIM_ADC2R_AD2TDRST_Msk      (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC2R_AD2TDRST          HRTIM_ADC2R_AD2TDRST_Msk                 /*!< ADC Trigger 2 on Timer D reset */

+#define HRTIM_ADC2R_AD2TEC2_Pos       (28U)

+#define HRTIM_ADC2R_AD2TEC2_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC2R_AD2TEC2           HRTIM_ADC2R_AD2TEC2_Msk                  /*!< ADC Trigger 2 on Timer E compare 2 */

+#define HRTIM_ADC2R_AD2TEC3_Pos       (29U)

+#define HRTIM_ADC2R_AD2TEC3_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC2R_AD2TEC3           HRTIM_ADC2R_AD2TEC3_Msk                  /*!< ADC Trigger 2 on Timer E compare 3 */

+#define HRTIM_ADC2R_AD2TEC4_Pos       (30U)

+#define HRTIM_ADC2R_AD2TEC4_Msk       (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC2R_AD2TEC4           HRTIM_ADC2R_AD2TEC4_Msk                  /*!< ADC Trigger 2 on Timer E compare 4 */

+#define HRTIM_ADC2R_AD2TERST_Pos      (31U)

+#define HRTIM_ADC2R_AD2TERST_Msk      (0x1UL << HRTIM_ADC2R_AD2TERST_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC2R_AD2TERST          HRTIM_ADC2R_AD2TERST_Msk                 /*!< ADC Trigger 2 on Timer E reset */

+

+/*******************  Bit definition for HRTIM_ADC3R register  ****************/

+#define HRTIM_ADC3R_AD3MC1_Pos        (0U)

+#define HRTIM_ADC3R_AD3MC1_Msk        (0x1UL << HRTIM_ADC3R_AD3MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC3R_AD3MC1            HRTIM_ADC3R_AD3MC1_Msk                   /*!< ADC Trigger 3 on master compare 1 */

+#define HRTIM_ADC3R_AD3MC2_Pos        (1U)

+#define HRTIM_ADC3R_AD3MC2_Msk        (0x1UL << HRTIM_ADC3R_AD3MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC3R_AD3MC2            HRTIM_ADC3R_AD3MC2_Msk                   /*!< ADC Trigger 3 on master compare 2 */

+#define HRTIM_ADC3R_AD3MC3_Pos        (2U)

+#define HRTIM_ADC3R_AD3MC3_Msk        (0x1UL << HRTIM_ADC3R_AD3MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC3R_AD3MC3            HRTIM_ADC3R_AD3MC3_Msk                   /*!< ADC Trigger 3 on master compare 3 */

+#define HRTIM_ADC3R_AD3MC4_Pos        (3U)

+#define HRTIM_ADC3R_AD3MC4_Msk        (0x1UL << HRTIM_ADC3R_AD3MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC3R_AD3MC4            HRTIM_ADC3R_AD3MC4_Msk                   /*!< ADC Trigger 3 on master compare 4 */

+#define HRTIM_ADC3R_AD3MPER_Pos       (4U)

+#define HRTIM_ADC3R_AD3MPER_Msk       (0x1UL << HRTIM_ADC3R_AD3MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC3R_AD3MPER           HRTIM_ADC3R_AD3MPER_Msk                  /*!< ADC Trigger 3 on master period */

+#define HRTIM_ADC3R_AD3EEV1_Pos       (5U)

+#define HRTIM_ADC3R_AD3EEV1_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC3R_AD3EEV1           HRTIM_ADC3R_AD3EEV1_Msk                  /*!< ADC Trigger 3 on external event 1 */

+#define HRTIM_ADC3R_AD3EEV2_Pos       (6U)

+#define HRTIM_ADC3R_AD3EEV2_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC3R_AD3EEV2           HRTIM_ADC3R_AD3EEV2_Msk                  /*!< ADC Trigger 3 on external event 2 */

+#define HRTIM_ADC3R_AD3EEV3_Pos       (7U)

+#define HRTIM_ADC3R_AD3EEV3_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC3R_AD3EEV3           HRTIM_ADC3R_AD3EEV3_Msk                  /*!< ADC Trigger 3 on external event 3 */

+#define HRTIM_ADC3R_AD3EEV4_Pos       (8U)

+#define HRTIM_ADC3R_AD3EEV4_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC3R_AD3EEV4           HRTIM_ADC3R_AD3EEV4_Msk                  /*!< ADC Trigger 3 on external event 4 */

+#define HRTIM_ADC3R_AD3EEV5_Pos       (9U)

+#define HRTIM_ADC3R_AD3EEV5_Msk       (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos)       /*!< 0x00000200 */

+#define HRTIM_ADC3R_AD3EEV5           HRTIM_ADC3R_AD3EEV5_Msk                  /*!< ADC Trigger 3 on external event 5 */

+#define HRTIM_ADC3R_AD3TAC2_Pos       (10U)

+#define HRTIM_ADC3R_AD3TAC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC3R_AD3TAC2           HRTIM_ADC3R_AD3TAC2_Msk                  /*!< ADC Trigger 3 on Timer A compare 2 */

+#define HRTIM_ADC3R_AD3TAC3_Pos       (11U)

+#define HRTIM_ADC3R_AD3TAC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC3R_AD3TAC3           HRTIM_ADC3R_AD3TAC3_Msk                  /*!< ADC Trigger 3 on Timer A compare 3 */

+#define HRTIM_ADC3R_AD3TAC4_Pos       (12U)

+#define HRTIM_ADC3R_AD3TAC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC3R_AD3TAC4           HRTIM_ADC3R_AD3TAC4_Msk                  /*!< ADC Trigger 3 on Timer A compare 4 */

+#define HRTIM_ADC3R_AD3TAPER_Pos      (13U)

+#define HRTIM_ADC3R_AD3TAPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC3R_AD3TAPER          HRTIM_ADC3R_AD3TAPER_Msk                 /*!< ADC Trigger 3 on Timer A period */

+#define HRTIM_ADC3R_AD3TARST_Pos      (14U)

+#define HRTIM_ADC3R_AD3TARST_Msk      (0x1UL << HRTIM_ADC3R_AD3TARST_Pos)      /*!< 0x00004000 */

+#define HRTIM_ADC3R_AD3TARST          HRTIM_ADC3R_AD3TARST_Msk                 /*!< ADC Trigger 3 on Timer A reset */

+#define HRTIM_ADC3R_AD3TBC2_Pos       (15U)

+#define HRTIM_ADC3R_AD3TBC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC2_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC3R_AD3TBC2           HRTIM_ADC3R_AD3TBC2_Msk                  /*!< ADC Trigger 3 on Timer B compare 2 */

+#define HRTIM_ADC3R_AD3TBC3_Pos       (16U)

+#define HRTIM_ADC3R_AD3TBC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC3R_AD3TBC3           HRTIM_ADC3R_AD3TBC3_Msk                  /*!< ADC Trigger 3 on Timer B compare 3 */

+#define HRTIM_ADC3R_AD3TBC4_Pos       (17U)

+#define HRTIM_ADC3R_AD3TBC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos)       /*!< 0x00020000 */

+#define HRTIM_ADC3R_AD3TBC4           HRTIM_ADC3R_AD3TBC4_Msk                  /*!< ADC Trigger 3 on Timer B compare 4 */

+#define HRTIM_ADC3R_AD3TBPER_Pos      (18U)

+#define HRTIM_ADC3R_AD3TBPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos)      /*!< 0x00040000 */

+#define HRTIM_ADC3R_AD3TBPER          HRTIM_ADC3R_AD3TBPER_Msk                 /*!< ADC Trigger 3 on Timer B period */

+#define HRTIM_ADC3R_AD3TBRST_Pos      (19U)

+#define HRTIM_ADC3R_AD3TBRST_Msk      (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos)      /*!< 0x00080000 */

+#define HRTIM_ADC3R_AD3TBRST          HRTIM_ADC3R_AD3TBRST_Msk                 /*!< ADC Trigger 3 on Timer B reset */

+#define HRTIM_ADC3R_AD3TCC2_Pos       (20U)

+#define HRTIM_ADC3R_AD3TCC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC2_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC3R_AD3TCC2           HRTIM_ADC3R_AD3TCC2_Msk                  /*!< ADC Trigger 3 on Timer C compare 2 */

+#define HRTIM_ADC3R_AD3TCC3_Pos       (21U)

+#define HRTIM_ADC3R_AD3TCC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos)       /*!< 0x00200000 */

+#define HRTIM_ADC3R_AD3TCC3           HRTIM_ADC3R_AD3TCC3_Msk                  /*!< ADC Trigger 3 on Timer C compare 3 */

+#define HRTIM_ADC3R_AD3TCC4_Pos       (22U)

+#define HRTIM_ADC3R_AD3TCC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos)       /*!< 0x00400000 */

+#define HRTIM_ADC3R_AD3TCC4           HRTIM_ADC3R_AD3TCC4_Msk                  /*!< ADC Trigger 3 on Timer C compare 4 */

+#define HRTIM_ADC3R_AD3TCPER_Pos      (23U)

+#define HRTIM_ADC3R_AD3TCPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos)      /*!< 0x00800000 */

+#define HRTIM_ADC3R_AD3TCPER          HRTIM_ADC3R_AD3TCPER_Msk                 /*!< ADC Trigger 3 on Timer C period */

+#define HRTIM_ADC3R_AD3TDC2_Pos       (24U)

+#define HRTIM_ADC3R_AD3TDC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC2_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC3R_AD3TDC2           HRTIM_ADC3R_AD3TDC2_Msk                  /*!< ADC Trigger 3 on Timer D compare 2 */

+#define HRTIM_ADC3R_AD3TDC3_Pos       (25U)

+#define HRTIM_ADC3R_AD3TDC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC3R_AD3TDC3           HRTIM_ADC3R_AD3TDC3_Msk                  /*!< ADC Trigger 3 on Timer D compare 3 */

+#define HRTIM_ADC3R_AD3TDC4_Pos       (26U)

+#define HRTIM_ADC3R_AD3TDC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos)       /*!< 0x04000000 */

+#define HRTIM_ADC3R_AD3TDC4           HRTIM_ADC3R_AD3TDC4_Msk                  /*!< ADC Trigger 3 on Timer D compare 4 */

+#define HRTIM_ADC3R_AD3TDPER_Pos      (27U)

+#define HRTIM_ADC3R_AD3TDPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC3R_AD3TDPER          HRTIM_ADC3R_AD3TDPER_Msk                 /*!< ADC Trigger 3 on Timer D period */

+#define HRTIM_ADC3R_AD3TEC2_Pos       (28U)

+#define HRTIM_ADC3R_AD3TEC2_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC3R_AD3TEC2           HRTIM_ADC3R_AD3TEC2_Msk                  /*!< ADC Trigger 3 on Timer E compare 2 */

+#define HRTIM_ADC3R_AD3TEC3_Pos       (29U)

+#define HRTIM_ADC3R_AD3TEC3_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC3R_AD3TEC3           HRTIM_ADC3R_AD3TEC3_Msk                  /*!< ADC Trigger 3 on Timer E compare 3 */

+#define HRTIM_ADC3R_AD3TEC4_Pos       (30U)

+#define HRTIM_ADC3R_AD3TEC4_Msk       (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC3R_AD3TEC4           HRTIM_ADC3R_AD3TEC4_Msk                  /*!< ADC Trigger 3 on Timer E compare 4 */

+#define HRTIM_ADC3R_AD3TEPER_Pos      (31U)

+#define HRTIM_ADC3R_AD3TEPER_Msk      (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC3R_AD3TEPER          HRTIM_ADC3R_AD3TEPER_Msk                 /*!< ADC Trigger 3 on Timer E period */

+

+/*******************  Bit definition for HRTIM_ADC4R register  ****************/

+#define HRTIM_ADC4R_AD4MC1_Pos        (0U)

+#define HRTIM_ADC4R_AD4MC1_Msk        (0x1UL << HRTIM_ADC4R_AD4MC1_Pos)        /*!< 0x00000001 */

+#define HRTIM_ADC4R_AD4MC1            HRTIM_ADC4R_AD4MC1_Msk                   /*!< ADC Trigger 4 on master compare 1 */

+#define HRTIM_ADC4R_AD4MC2_Pos        (1U)

+#define HRTIM_ADC4R_AD4MC2_Msk        (0x1UL << HRTIM_ADC4R_AD4MC2_Pos)        /*!< 0x00000002 */

+#define HRTIM_ADC4R_AD4MC2            HRTIM_ADC4R_AD4MC2_Msk                   /*!< ADC Trigger 4 on master compare 2 */

+#define HRTIM_ADC4R_AD4MC3_Pos        (2U)

+#define HRTIM_ADC4R_AD4MC3_Msk        (0x1UL << HRTIM_ADC4R_AD4MC3_Pos)        /*!< 0x00000004 */

+#define HRTIM_ADC4R_AD4MC3            HRTIM_ADC4R_AD4MC3_Msk                   /*!< ADC Trigger 4 on master compare 3 */

+#define HRTIM_ADC4R_AD4MC4_Pos        (3U)

+#define HRTIM_ADC4R_AD4MC4_Msk        (0x1UL << HRTIM_ADC4R_AD4MC4_Pos)        /*!< 0x00000008 */

+#define HRTIM_ADC4R_AD4MC4            HRTIM_ADC4R_AD4MC4_Msk                   /*!< ADC Trigger 4 on master compare 4 */

+#define HRTIM_ADC4R_AD4MPER_Pos       (4U)

+#define HRTIM_ADC4R_AD4MPER_Msk       (0x1UL << HRTIM_ADC4R_AD4MPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_ADC4R_AD4MPER           HRTIM_ADC4R_AD4MPER_Msk                  /*!< ADC Trigger 4 on master period */

+#define HRTIM_ADC4R_AD4EEV6_Pos       (5U)

+#define HRTIM_ADC4R_AD4EEV6_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos)       /*!< 0x00000020 */

+#define HRTIM_ADC4R_AD4EEV6           HRTIM_ADC4R_AD4EEV6_Msk                  /*!< ADC Trigger 4 on external event 6 */

+#define HRTIM_ADC4R_AD4EEV7_Pos       (6U)

+#define HRTIM_ADC4R_AD4EEV7_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos)       /*!< 0x00000040 */

+#define HRTIM_ADC4R_AD4EEV7           HRTIM_ADC4R_AD4EEV7_Msk                  /*!< ADC Trigger 4 on external event 7 */

+#define HRTIM_ADC4R_AD4EEV8_Pos       (7U)

+#define HRTIM_ADC4R_AD4EEV8_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos)       /*!< 0x00000080 */

+#define HRTIM_ADC4R_AD4EEV8           HRTIM_ADC4R_AD4EEV8_Msk                  /*!< ADC Trigger 4 on external event 8 */

+#define HRTIM_ADC4R_AD4EEV9_Pos       (8U)

+#define HRTIM_ADC4R_AD4EEV9_Msk       (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos)       /*!< 0x00000100 */

+#define HRTIM_ADC4R_AD4EEV9           HRTIM_ADC4R_AD4EEV9_Msk                  /*!< ADC Trigger 4 on external event 9 */

+#define HRTIM_ADC4R_AD4EEV10_Pos      (9U)

+#define HRTIM_ADC4R_AD4EEV10_Msk      (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos)      /*!< 0x00000200 */

+#define HRTIM_ADC4R_AD4EEV10          HRTIM_ADC4R_AD4EEV10_Msk                 /*!< ADC Trigger 4 on external event 10 */

+#define HRTIM_ADC4R_AD4TAC2_Pos       (10U)

+#define HRTIM_ADC4R_AD4TAC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos)       /*!< 0x00000400 */

+#define HRTIM_ADC4R_AD4TAC2           HRTIM_ADC4R_AD4TAC2_Msk                  /*!< ADC Trigger 4 on Timer A compare 2 */

+#define HRTIM_ADC4R_AD4TAC3_Pos       (11U)

+#define HRTIM_ADC4R_AD4TAC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC3_Pos)       /*!< 0x00000800 */

+#define HRTIM_ADC4R_AD4TAC3           HRTIM_ADC4R_AD4TAC3_Msk                  /*!< ADC Trigger 4 on Timer A compare 3 */

+#define HRTIM_ADC4R_AD4TAC4_Pos       (12U)

+#define HRTIM_ADC4R_AD4TAC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos)       /*!< 0x00001000 */

+#define HRTIM_ADC4R_AD4TAC4           HRTIM_ADC4R_AD4TAC4_Msk                  /*!< ADC Trigger 4 on Timer A compare 4*/

+#define HRTIM_ADC4R_AD4TAPER_Pos      (13U)

+#define HRTIM_ADC4R_AD4TAPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos)      /*!< 0x00002000 */

+#define HRTIM_ADC4R_AD4TAPER          HRTIM_ADC4R_AD4TAPER_Msk                 /*!< ADC Trigger 4 on Timer A period */

+#define HRTIM_ADC4R_AD4TBC2_Pos       (14U)

+#define HRTIM_ADC4R_AD4TBC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos)       /*!< 0x00004000 */

+#define HRTIM_ADC4R_AD4TBC2           HRTIM_ADC4R_AD4TBC2_Msk                  /*!< ADC Trigger 4 on Timer B compare 2 */

+#define HRTIM_ADC4R_AD4TBC3_Pos       (15U)

+#define HRTIM_ADC4R_AD4TBC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC3_Pos)       /*!< 0x00008000 */

+#define HRTIM_ADC4R_AD4TBC3           HRTIM_ADC4R_AD4TBC3_Msk                  /*!< ADC Trigger 4 on Timer B compare 3 */

+#define HRTIM_ADC4R_AD4TBC4_Pos       (16U)

+#define HRTIM_ADC4R_AD4TBC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos)       /*!< 0x00010000 */

+#define HRTIM_ADC4R_AD4TBC4           HRTIM_ADC4R_AD4TBC4_Msk                  /*!< ADC Trigger 4 on Timer B compare 4 */

+#define HRTIM_ADC4R_AD4TBPER_Pos      (17U)

+#define HRTIM_ADC4R_AD4TBPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos)      /*!< 0x00020000 */

+#define HRTIM_ADC4R_AD4TBPER          HRTIM_ADC4R_AD4TBPER_Msk                 /*!< ADC Trigger 4 on Timer B period */

+#define HRTIM_ADC4R_AD4TCC2_Pos       (18U)

+#define HRTIM_ADC4R_AD4TCC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos)       /*!< 0x00040000 */

+#define HRTIM_ADC4R_AD4TCC2           HRTIM_ADC4R_AD4TCC2_Msk                  /*!< ADC Trigger 4 on Timer C compare 2 */

+#define HRTIM_ADC4R_AD4TCC3_Pos       (19U)

+#define HRTIM_ADC4R_AD4TCC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC3_Pos)       /*!< 0x00080000 */

+#define HRTIM_ADC4R_AD4TCC3           HRTIM_ADC4R_AD4TCC3_Msk                  /*!< ADC Trigger 4 on Timer C compare 3 */

+#define HRTIM_ADC4R_AD4TCC4_Pos       (20U)

+#define HRTIM_ADC4R_AD4TCC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos)       /*!< 0x00100000 */

+#define HRTIM_ADC4R_AD4TCC4           HRTIM_ADC4R_AD4TCC4_Msk                  /*!< ADC Trigger 4 on Timer C compare 4 */

+#define HRTIM_ADC4R_AD4TCPER_Pos      (21U)

+#define HRTIM_ADC4R_AD4TCPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos)      /*!< 0x00200000 */

+#define HRTIM_ADC4R_AD4TCPER          HRTIM_ADC4R_AD4TCPER_Msk                 /*!< ADC Trigger 4 on Timer C period */

+#define HRTIM_ADC4R_AD4TCRST_Pos      (22U)

+#define HRTIM_ADC4R_AD4TCRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos)      /*!< 0x00400000 */

+#define HRTIM_ADC4R_AD4TCRST          HRTIM_ADC4R_AD4TCRST_Msk                 /*!< ADC Trigger 4 on Timer C reset */

+#define HRTIM_ADC4R_AD4TDC2_Pos       (23U)

+#define HRTIM_ADC4R_AD4TDC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos)       /*!< 0x00800000 */

+#define HRTIM_ADC4R_AD4TDC2           HRTIM_ADC4R_AD4TDC2_Msk                  /*!< ADC Trigger 4 on Timer D compare 2 */

+#define HRTIM_ADC4R_AD4TDC3_Pos       (24U)

+#define HRTIM_ADC4R_AD4TDC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC3_Pos)       /*!< 0x01000000 */

+#define HRTIM_ADC4R_AD4TDC3           HRTIM_ADC4R_AD4TDC3_Msk                  /*!< ADC Trigger 4 on Timer D compare 3 */

+#define HRTIM_ADC4R_AD4TDC4_Pos       (25U)

+#define HRTIM_ADC4R_AD4TDC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos)       /*!< 0x02000000 */

+#define HRTIM_ADC4R_AD4TDC4           HRTIM_ADC4R_AD4TDC4_Msk                  /*!< ADC Trigger 4 on Timer D compare 4*/

+#define HRTIM_ADC4R_AD4TDPER_Pos      (26U)

+#define HRTIM_ADC4R_AD4TDPER_Msk      (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos)      /*!< 0x04000000 */

+#define HRTIM_ADC4R_AD4TDPER          HRTIM_ADC4R_AD4TDPER_Msk                 /*!< ADC Trigger 4 on Timer D period */

+#define HRTIM_ADC4R_AD4TDRST_Pos      (27U)

+#define HRTIM_ADC4R_AD4TDRST_Msk      (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos)      /*!< 0x08000000 */

+#define HRTIM_ADC4R_AD4TDRST          HRTIM_ADC4R_AD4TDRST_Msk                 /*!< ADC Trigger 4 on Timer D reset */

+#define HRTIM_ADC4R_AD4TEC2_Pos       (28U)

+#define HRTIM_ADC4R_AD4TEC2_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos)       /*!< 0x10000000 */

+#define HRTIM_ADC4R_AD4TEC2           HRTIM_ADC4R_AD4TEC2_Msk                  /*!< ADC Trigger 4 on Timer E compare 2 */

+#define HRTIM_ADC4R_AD4TEC3_Pos       (29U)

+#define HRTIM_ADC4R_AD4TEC3_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos)       /*!< 0x20000000 */

+#define HRTIM_ADC4R_AD4TEC3           HRTIM_ADC4R_AD4TEC3_Msk                  /*!< ADC Trigger 4 on Timer E compare 3 */

+#define HRTIM_ADC4R_AD4TEC4_Pos       (30U)

+#define HRTIM_ADC4R_AD4TEC4_Msk       (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos)       /*!< 0x40000000 */

+#define HRTIM_ADC4R_AD4TEC4           HRTIM_ADC4R_AD4TEC4_Msk                  /*!< ADC Trigger 4 on Timer E compare 4 */

+#define HRTIM_ADC4R_AD4TERST_Pos      (31U)

+#define HRTIM_ADC4R_AD4TERST_Msk      (0x1UL << HRTIM_ADC4R_AD4TERST_Pos)      /*!< 0x80000000 */

+#define HRTIM_ADC4R_AD4TERST          HRTIM_ADC4R_AD4TERST_Msk                 /*!< ADC Trigger 4 on Timer E reset */

+

+/*******************  Bit definition for HRTIM_FLTINR1 register  ***************/

+#define HRTIM_FLTINR1_FLT1E_Pos       (0U)

+#define HRTIM_FLTINR1_FLT1E_Msk       (0x1UL << HRTIM_FLTINR1_FLT1E_Pos)       /*!< 0x00000001 */

+#define HRTIM_FLTINR1_FLT1E           HRTIM_FLTINR1_FLT1E_Msk                  /*!< Fault 1 enable */

+#define HRTIM_FLTINR1_FLT1P_Pos       (1U)

+#define HRTIM_FLTINR1_FLT1P_Msk       (0x1UL << HRTIM_FLTINR1_FLT1P_Pos)       /*!< 0x00000002 */

+#define HRTIM_FLTINR1_FLT1P           HRTIM_FLTINR1_FLT1P_Msk                  /*!< Fault 1 polarity */

+#define HRTIM_FLTINR1_FLT1SRC_Pos     (2U)

+#define HRTIM_FLTINR1_FLT1SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT1SRC_Pos)     /*!< 0x00000004 */

+#define HRTIM_FLTINR1_FLT1SRC         HRTIM_FLTINR1_FLT1SRC_Msk                /*!< Fault 1 source */

+#define HRTIM_FLTINR1_FLT1F_Pos       (3U)

+#define HRTIM_FLTINR1_FLT1F_Msk       (0xFUL << HRTIM_FLTINR1_FLT1F_Pos)       /*!< 0x00000078 */

+#define HRTIM_FLTINR1_FLT1F           HRTIM_FLTINR1_FLT1F_Msk                  /*!< Fault 1 filter */

+#define HRTIM_FLTINR1_FLT1F_0         (0x1UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000008 */

+#define HRTIM_FLTINR1_FLT1F_1         (0x2UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000010 */

+#define HRTIM_FLTINR1_FLT1F_2         (0x4UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000020 */

+#define HRTIM_FLTINR1_FLT1F_3         (0x8UL << HRTIM_FLTINR1_FLT1F_Pos)        /*!< 0x00000040 */

+#define HRTIM_FLTINR1_FLT1LCK_Pos     (7U)

+#define HRTIM_FLTINR1_FLT1LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos)     /*!< 0x00000080 */

+#define HRTIM_FLTINR1_FLT1LCK         HRTIM_FLTINR1_FLT1LCK_Msk                /*!< Fault 1 lock */

+

+#define HRTIM_FLTINR1_FLT2E_Pos       (8U)

+#define HRTIM_FLTINR1_FLT2E_Msk       (0x1UL << HRTIM_FLTINR1_FLT2E_Pos)       /*!< 0x00000100 */

+#define HRTIM_FLTINR1_FLT2E           HRTIM_FLTINR1_FLT2E_Msk                  /*!< Fault 2 enable */

+#define HRTIM_FLTINR1_FLT2P_Pos       (9U)

+#define HRTIM_FLTINR1_FLT2P_Msk       (0x1UL << HRTIM_FLTINR1_FLT2P_Pos)       /*!< 0x00000200 */

+#define HRTIM_FLTINR1_FLT2P           HRTIM_FLTINR1_FLT2P_Msk                  /*!< Fault 2 polarity */

+#define HRTIM_FLTINR1_FLT2SRC_Pos     (10U)

+#define HRTIM_FLTINR1_FLT2SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT2SRC_Pos)     /*!< 0x00000400 */

+#define HRTIM_FLTINR1_FLT2SRC         HRTIM_FLTINR1_FLT2SRC_Msk                /*!< Fault 2 source */

+#define HRTIM_FLTINR1_FLT2F_Pos       (11U)

+#define HRTIM_FLTINR1_FLT2F_Msk       (0xFUL << HRTIM_FLTINR1_FLT2F_Pos)       /*!< 0x00007800 */

+#define HRTIM_FLTINR1_FLT2F           HRTIM_FLTINR1_FLT2F_Msk                  /*!< Fault 2 filter */

+#define HRTIM_FLTINR1_FLT2F_0         (0x1UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00000800 */

+#define HRTIM_FLTINR1_FLT2F_1         (0x2UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00001000 */

+#define HRTIM_FLTINR1_FLT2F_2         (0x4UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00002000 */

+#define HRTIM_FLTINR1_FLT2F_3         (0x8UL << HRTIM_FLTINR1_FLT2F_Pos)        /*!< 0x00004000 */

+#define HRTIM_FLTINR1_FLT2LCK_Pos     (15U)

+#define HRTIM_FLTINR1_FLT2LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos)     /*!< 0x00008000 */

+#define HRTIM_FLTINR1_FLT2LCK         HRTIM_FLTINR1_FLT2LCK_Msk                /*!< Fault 2 lock */

+

+#define HRTIM_FLTINR1_FLT3E_Pos       (16U)

+#define HRTIM_FLTINR1_FLT3E_Msk       (0x1UL << HRTIM_FLTINR1_FLT3E_Pos)       /*!< 0x00010000 */

+#define HRTIM_FLTINR1_FLT3E           HRTIM_FLTINR1_FLT3E_Msk                  /*!< Fault 3 enable */

+#define HRTIM_FLTINR1_FLT3P_Pos       (17U)

+#define HRTIM_FLTINR1_FLT3P_Msk       (0x1UL << HRTIM_FLTINR1_FLT3P_Pos)       /*!< 0x00020000 */

+#define HRTIM_FLTINR1_FLT3P           HRTIM_FLTINR1_FLT3P_Msk                  /*!< Fault 3 polarity */

+#define HRTIM_FLTINR1_FLT3SRC_Pos     (18U)

+#define HRTIM_FLTINR1_FLT3SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT3SRC_Pos)     /*!< 0x00040000 */

+#define HRTIM_FLTINR1_FLT3SRC         HRTIM_FLTINR1_FLT3SRC_Msk                /*!< Fault 3 source */

+#define HRTIM_FLTINR1_FLT3F_Pos       (19U)

+#define HRTIM_FLTINR1_FLT3F_Msk       (0xFUL << HRTIM_FLTINR1_FLT3F_Pos)       /*!< 0x00780000 */

+#define HRTIM_FLTINR1_FLT3F           HRTIM_FLTINR1_FLT3F_Msk                  /*!< Fault 3 filter */

+#define HRTIM_FLTINR1_FLT3F_0         (0x1UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00080000 */

+#define HRTIM_FLTINR1_FLT3F_1         (0x2UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00100000 */

+#define HRTIM_FLTINR1_FLT3F_2         (0x4UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00200000 */

+#define HRTIM_FLTINR1_FLT3F_3         (0x8UL << HRTIM_FLTINR1_FLT3F_Pos)        /*!< 0x00400000 */

+#define HRTIM_FLTINR1_FLT3LCK_Pos     (23U)

+#define HRTIM_FLTINR1_FLT3LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos)     /*!< 0x00800000 */

+#define HRTIM_FLTINR1_FLT3LCK         HRTIM_FLTINR1_FLT3LCK_Msk                /*!< Fault 3 lock */

+

+#define HRTIM_FLTINR1_FLT4E_Pos       (24U)

+#define HRTIM_FLTINR1_FLT4E_Msk       (0x1UL << HRTIM_FLTINR1_FLT4E_Pos)       /*!< 0x01000000 */

+#define HRTIM_FLTINR1_FLT4E           HRTIM_FLTINR1_FLT4E_Msk                  /*!< Fault 4 enable */

+#define HRTIM_FLTINR1_FLT4P_Pos       (25U)

+#define HRTIM_FLTINR1_FLT4P_Msk       (0x1UL << HRTIM_FLTINR1_FLT4P_Pos)       /*!< 0x02000000 */

+#define HRTIM_FLTINR1_FLT4P           HRTIM_FLTINR1_FLT4P_Msk                  /*!< Fault 4 polarity */

+#define HRTIM_FLTINR1_FLT4SRC_Pos     (26U)

+#define HRTIM_FLTINR1_FLT4SRC_Msk     (0x1UL << HRTIM_FLTINR1_FLT4SRC_Pos)     /*!< 0x04000000 */

+#define HRTIM_FLTINR1_FLT4SRC         HRTIM_FLTINR1_FLT4SRC_Msk                /*!< Fault 4 source */

+#define HRTIM_FLTINR1_FLT4F_Pos       (27U)

+#define HRTIM_FLTINR1_FLT4F_Msk       (0xFUL << HRTIM_FLTINR1_FLT4F_Pos)       /*!< 0x78000000 */

+#define HRTIM_FLTINR1_FLT4F           HRTIM_FLTINR1_FLT4F_Msk                  /*!< Fault 4 filter */

+#define HRTIM_FLTINR1_FLT4F_0         (0x1UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x08000000 */

+#define HRTIM_FLTINR1_FLT4F_1         (0x2UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x10000000 */

+#define HRTIM_FLTINR1_FLT4F_2         (0x4UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x20000000 */

+#define HRTIM_FLTINR1_FLT4F_3         (0x8UL << HRTIM_FLTINR1_FLT4F_Pos)        /*!< 0x40000000 */

+#define HRTIM_FLTINR1_FLT4LCK_Pos     (31U)

+#define HRTIM_FLTINR1_FLT4LCK_Msk     (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos)     /*!< 0x80000000 */

+#define HRTIM_FLTINR1_FLT4LCK         HRTIM_FLTINR1_FLT4LCK_Msk                /*!< Fault 4 lock */

+

+/*******************  Bit definition for HRTIM_FLTINR2 register  ***************/

+#define HRTIM_FLTINR2_FLT5E_Pos       (0U)

+#define HRTIM_FLTINR2_FLT5E_Msk       (0x1UL << HRTIM_FLTINR2_FLT5E_Pos)       /*!< 0x00000001 */

+#define HRTIM_FLTINR2_FLT5E           HRTIM_FLTINR2_FLT5E_Msk                  /*!< Fault 5 enable */

+#define HRTIM_FLTINR2_FLT5P_Pos       (1U)

+#define HRTIM_FLTINR2_FLT5P_Msk       (0x1UL << HRTIM_FLTINR2_FLT5P_Pos)       /*!< 0x00000002 */

+#define HRTIM_FLTINR2_FLT5P           HRTIM_FLTINR2_FLT5P_Msk                  /*!< Fault 5 polarity */

+#define HRTIM_FLTINR2_FLT5SRC_Pos     (2U)

+#define HRTIM_FLTINR2_FLT5SRC_Msk     (0x1UL << HRTIM_FLTINR2_FLT5SRC_Pos)     /*!< 0x00000004 */

+#define HRTIM_FLTINR2_FLT5SRC         HRTIM_FLTINR2_FLT5SRC_Msk                /*!< Fault 5 source */

+#define HRTIM_FLTINR2_FLT5F_Pos       (3U)

+#define HRTIM_FLTINR2_FLT5F_Msk       (0xFUL << HRTIM_FLTINR2_FLT5F_Pos)       /*!< 0x00000078 */

+#define HRTIM_FLTINR2_FLT5F           HRTIM_FLTINR2_FLT5F_Msk                  /*!< Fault 5 filter */

+#define HRTIM_FLTINR2_FLT5F_0         (0x1UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000008 */

+#define HRTIM_FLTINR2_FLT5F_1         (0x2UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000010 */

+#define HRTIM_FLTINR2_FLT5F_2         (0x4UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000020 */

+#define HRTIM_FLTINR2_FLT5F_3         (0x8UL << HRTIM_FLTINR2_FLT5F_Pos)        /*!< 0x00000040 */

+#define HRTIM_FLTINR2_FLT5LCK_Pos     (7U)

+#define HRTIM_FLTINR2_FLT5LCK_Msk     (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos)     /*!< 0x00000080 */

+#define HRTIM_FLTINR2_FLT5LCK         HRTIM_FLTINR2_FLT5LCK_Msk                /*!< Fault 5 lock */

+#define HRTIM_FLTINR2_FLTSD_Pos       (24U)

+#define HRTIM_FLTINR2_FLTSD_Msk       (0x3UL << HRTIM_FLTINR2_FLTSD_Pos)       /*!< 0x03000000 */

+#define HRTIM_FLTINR2_FLTSD           HRTIM_FLTINR2_FLTSD_Msk                  /*!< Fault sampling clock division */

+#define HRTIM_FLTINR2_FLTSD_0         (0x1UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x01000000 */

+#define HRTIM_FLTINR2_FLTSD_1         (0x2UL << HRTIM_FLTINR2_FLTSD_Pos)        /*!< 0x02000000 */

+

+/*******************  Bit definition for HRTIM_BDMUPR register  ***************/

+#define HRTIM_BDMUPR_MCR_Pos          (0U)

+#define HRTIM_BDMUPR_MCR_Msk          (0x1UL << HRTIM_BDMUPR_MCR_Pos)          /*!< 0x00000001 */

+#define HRTIM_BDMUPR_MCR              HRTIM_BDMUPR_MCR_Msk                     /*!< MCR register update enable */

+#define HRTIM_BDMUPR_MICR_Pos         (1U)

+#define HRTIM_BDMUPR_MICR_Msk         (0x1UL << HRTIM_BDMUPR_MICR_Pos)         /*!< 0x00000002 */

+#define HRTIM_BDMUPR_MICR             HRTIM_BDMUPR_MICR_Msk                    /*!< MICR register update enable */

+#define HRTIM_BDMUPR_MDIER_Pos        (2U)

+#define HRTIM_BDMUPR_MDIER_Msk        (0x1UL << HRTIM_BDMUPR_MDIER_Pos)        /*!< 0x00000004 */

+#define HRTIM_BDMUPR_MDIER            HRTIM_BDMUPR_MDIER_Msk                   /*!< MDIER register update enable */

+#define HRTIM_BDMUPR_MCNT_Pos         (3U)

+#define HRTIM_BDMUPR_MCNT_Msk         (0x1UL << HRTIM_BDMUPR_MCNT_Pos)         /*!< 0x00000008 */

+#define HRTIM_BDMUPR_MCNT             HRTIM_BDMUPR_MCNT_Msk                    /*!< MCNT register update enable */

+#define HRTIM_BDMUPR_MPER_Pos         (4U)

+#define HRTIM_BDMUPR_MPER_Msk         (0x1UL << HRTIM_BDMUPR_MPER_Pos)         /*!< 0x00000010 */

+#define HRTIM_BDMUPR_MPER             HRTIM_BDMUPR_MPER_Msk                    /*!< MPER register update enable */

+#define HRTIM_BDMUPR_MREP_Pos         (5U)

+#define HRTIM_BDMUPR_MREP_Msk         (0x1UL << HRTIM_BDMUPR_MREP_Pos)         /*!< 0x00000020 */

+#define HRTIM_BDMUPR_MREP             HRTIM_BDMUPR_MREP_Msk                    /*!< MREP register update enable */

+#define HRTIM_BDMUPR_MCMP1_Pos        (6U)

+#define HRTIM_BDMUPR_MCMP1_Msk        (0x1UL << HRTIM_BDMUPR_MCMP1_Pos)        /*!< 0x00000040 */

+#define HRTIM_BDMUPR_MCMP1            HRTIM_BDMUPR_MCMP1_Msk                   /*!< MCMP1 register update enable */

+#define HRTIM_BDMUPR_MCMP2_Pos        (7U)

+#define HRTIM_BDMUPR_MCMP2_Msk        (0x1UL << HRTIM_BDMUPR_MCMP2_Pos)        /*!< 0x00000080 */

+#define HRTIM_BDMUPR_MCMP2            HRTIM_BDMUPR_MCMP2_Msk                   /*!< MCMP2 register update enable */

+#define HRTIM_BDMUPR_MCMP3_Pos        (8U)

+#define HRTIM_BDMUPR_MCMP3_Msk        (0x1UL << HRTIM_BDMUPR_MCMP3_Pos)        /*!< 0x00000100 */

+#define HRTIM_BDMUPR_MCMP3            HRTIM_BDMUPR_MCMP3_Msk                   /*!< MCMP3 register update enable */

+#define HRTIM_BDMUPR_MCMP4_Pos        (9U)

+#define HRTIM_BDMUPR_MCMP4_Msk        (0x1UL << HRTIM_BDMUPR_MCMP4_Pos)        /*!< 0x00000200 */

+#define HRTIM_BDMUPR_MCMP4            HRTIM_BDMUPR_MCMP4_Msk                   /*!< MPCMP4 register update enable */

+

+/*******************  Bit definition for HRTIM_BDTUPR register  ***************/

+#define HRTIM_BDTUPR_TIMCR_Pos        (0U)

+#define HRTIM_BDTUPR_TIMCR_Msk        (0x1UL << HRTIM_BDTUPR_TIMCR_Pos)        /*!< 0x00000001 */

+#define HRTIM_BDTUPR_TIMCR            HRTIM_BDTUPR_TIMCR_Msk                   /*!<  TIMCR register update enable */

+#define HRTIM_BDTUPR_TIMICR_Pos       (1U)

+#define HRTIM_BDTUPR_TIMICR_Msk       (0x1UL << HRTIM_BDTUPR_TIMICR_Pos)       /*!< 0x00000002 */

+#define HRTIM_BDTUPR_TIMICR           HRTIM_BDTUPR_TIMICR_Msk                  /*!<  TIMICR register update enable */

+#define HRTIM_BDTUPR_TIMDIER_Pos      (2U)

+#define HRTIM_BDTUPR_TIMDIER_Msk      (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos)      /*!< 0x00000004 */

+#define HRTIM_BDTUPR_TIMDIER          HRTIM_BDTUPR_TIMDIER_Msk                 /*!<  TIMDIER register update enable */

+#define HRTIM_BDTUPR_TIMCNT_Pos       (3U)

+#define HRTIM_BDTUPR_TIMCNT_Msk       (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos)       /*!< 0x00000008 */

+#define HRTIM_BDTUPR_TIMCNT           HRTIM_BDTUPR_TIMCNT_Msk                  /*!<  TIMCNT register update enable */

+#define HRTIM_BDTUPR_TIMPER_Pos       (4U)

+#define HRTIM_BDTUPR_TIMPER_Msk       (0x1UL << HRTIM_BDTUPR_TIMPER_Pos)       /*!< 0x00000010 */

+#define HRTIM_BDTUPR_TIMPER           HRTIM_BDTUPR_TIMPER_Msk                  /*!<  TIMPER register update enable */

+#define HRTIM_BDTUPR_TIMREP_Pos       (5U)

+#define HRTIM_BDTUPR_TIMREP_Msk       (0x1UL << HRTIM_BDTUPR_TIMREP_Pos)       /*!< 0x00000020 */

+#define HRTIM_BDTUPR_TIMREP           HRTIM_BDTUPR_TIMREP_Msk                  /*!<  TIMREP register update enable */

+#define HRTIM_BDTUPR_TIMCMP1_Pos      (6U)

+#define HRTIM_BDTUPR_TIMCMP1_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos)      /*!< 0x00000040 */

+#define HRTIM_BDTUPR_TIMCMP1          HRTIM_BDTUPR_TIMCMP1_Msk                 /*!<  TIMCMP1 register update enable */

+#define HRTIM_BDTUPR_TIMCMP2_Pos      (7U)

+#define HRTIM_BDTUPR_TIMCMP2_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos)      /*!< 0x00000080 */

+#define HRTIM_BDTUPR_TIMCMP2          HRTIM_BDTUPR_TIMCMP2_Msk                 /*!<  TIMCMP2 register update enable */

+#define HRTIM_BDTUPR_TIMCMP3_Pos      (8U)

+#define HRTIM_BDTUPR_TIMCMP3_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos)      /*!< 0x00000100 */

+#define HRTIM_BDTUPR_TIMCMP3          HRTIM_BDTUPR_TIMCMP3_Msk                 /*!<  TIMCMP3 register update enable */

+#define HRTIM_BDTUPR_TIMCMP4_Pos      (9U)

+#define HRTIM_BDTUPR_TIMCMP4_Msk      (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos)      /*!< 0x00000200 */

+#define HRTIM_BDTUPR_TIMCMP4          HRTIM_BDTUPR_TIMCMP4_Msk                 /*!<  TIMCMP4 register update enable */

+#define HRTIM_BDTUPR_TIMDTR_Pos       (10U)

+#define HRTIM_BDTUPR_TIMDTR_Msk       (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos)       /*!< 0x00000400 */

+#define HRTIM_BDTUPR_TIMDTR           HRTIM_BDTUPR_TIMDTR_Msk                  /*!<  TIMDTR register update enable */

+#define HRTIM_BDTUPR_TIMSET1R_Pos     (11U)

+#define HRTIM_BDTUPR_TIMSET1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos)     /*!< 0x00000800 */

+#define HRTIM_BDTUPR_TIMSET1R         HRTIM_BDTUPR_TIMSET1R_Msk                /*!<  TIMSET1R register update enable */

+#define HRTIM_BDTUPR_TIMRST1R_Pos     (12U)

+#define HRTIM_BDTUPR_TIMRST1R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos)     /*!< 0x00001000 */

+#define HRTIM_BDTUPR_TIMRST1R         HRTIM_BDTUPR_TIMRST1R_Msk                /*!<  TIMRST1R register update enable */

+#define HRTIM_BDTUPR_TIMSET2R_Pos     (13U)

+#define HRTIM_BDTUPR_TIMSET2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos)     /*!< 0x00002000 */

+#define HRTIM_BDTUPR_TIMSET2R         HRTIM_BDTUPR_TIMSET2R_Msk                /*!<  TIMSET2R register update enable */

+#define HRTIM_BDTUPR_TIMRST2R_Pos     (14U)

+#define HRTIM_BDTUPR_TIMRST2R_Msk     (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos)     /*!< 0x00004000 */

+#define HRTIM_BDTUPR_TIMRST2R         HRTIM_BDTUPR_TIMRST2R_Msk                /*!<  TIMRST2R register update enable */

+#define HRTIM_BDTUPR_TIMEEFR1_Pos     (15U)

+#define HRTIM_BDTUPR_TIMEEFR1_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos)     /*!< 0x00008000 */

+#define HRTIM_BDTUPR_TIMEEFR1         HRTIM_BDTUPR_TIMEEFR1_Msk                /*!<  TIMEEFR1 register update enable */

+#define HRTIM_BDTUPR_TIMEEFR2_Pos     (16U)

+#define HRTIM_BDTUPR_TIMEEFR2_Msk     (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos)     /*!< 0x00010000 */

+#define HRTIM_BDTUPR_TIMEEFR2         HRTIM_BDTUPR_TIMEEFR2_Msk                /*!<  TIMEEFR2 register update enable */

+#define HRTIM_BDTUPR_TIMRSTR_Pos      (17U)

+#define HRTIM_BDTUPR_TIMRSTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos)      /*!< 0x00020000 */

+#define HRTIM_BDTUPR_TIMRSTR          HRTIM_BDTUPR_TIMRSTR_Msk                 /*!<  TIMRSTR register update enable */

+#define HRTIM_BDTUPR_TIMCHPR_Pos      (18U)

+#define HRTIM_BDTUPR_TIMCHPR_Msk      (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos)      /*!< 0x00040000 */

+#define HRTIM_BDTUPR_TIMCHPR          HRTIM_BDTUPR_TIMCHPR_Msk                 /*!<  TIMCHPR register update enable */

+#define HRTIM_BDTUPR_TIMOUTR_Pos      (19U)

+#define HRTIM_BDTUPR_TIMOUTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos)      /*!< 0x00080000 */

+#define HRTIM_BDTUPR_TIMOUTR          HRTIM_BDTUPR_TIMOUTR_Msk                 /*!<  TIMOUTR register update enable */

+#define HRTIM_BDTUPR_TIMFLTR_Pos      (20U)

+#define HRTIM_BDTUPR_TIMFLTR_Msk      (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos)      /*!< 0x00100000 */

+#define HRTIM_BDTUPR_TIMFLTR          HRTIM_BDTUPR_TIMFLTR_Msk                 /*!<  TIMFLTR register update enable */

+

+/*******************  Bit definition for HRTIM_BDMADR register  ***************/

+#define HRTIM_BDMADR_BDMADR_Pos       (0U)

+#define HRTIM_BDMADR_BDMADR_Msk       (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos) /*!< 0xFFFFFFFF */

+#define HRTIM_BDMADR_BDMADR           HRTIM_BDMADR_BDMADR_Msk                  /*!<  Burst DMA Data register */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             RAM ECC monitoring                             */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for RAMECC_IER register  ******************/

+#define RAMECC_IER_GECCDEBWIE_Pos         (3U)

+#define RAMECC_IER_GECCDEBWIE_Msk         (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)  /*!< 0x00000008 */

+#define RAMECC_IER_GECCDEBWIE             RAMECC_IER_GECCDEBWIE_Msk             /*!< Global ECC double error on byte write (BW) interrupt enable */

+#define RAMECC_IER_GECCDEIE_Pos           (2U)

+#define RAMECC_IER_GECCDEIE_Msk           (0x1UL << RAMECC_IER_GECCDEIE_Pos)    /*!< 0x00000004 */

+#define RAMECC_IER_GECCDEIE               RAMECC_IER_GECCDEIE_Msk               /*!< Global ECC double error interrupt enable */

+#define RAMECC_IER_GECCSEIE_Pos           (1U)

+#define RAMECC_IER_GECCSEIE_Msk           (0x1UL << RAMECC_IER_GECCSEIE_Pos)    /*!< 0x00000002 */

+#define RAMECC_IER_GECCSEIE               RAMECC_IER_GECCSEIE_Msk               /*!< Global ECC single error interrupt enable */

+#define RAMECC_IER_GIE_Pos                (0U)

+#define RAMECC_IER_GIE_Msk                (0x1UL << RAMECC_IER_GIE_Pos)         /*!< 0x00000001 */

+#define RAMECC_IER_GIE                    RAMECC_IER_GIE_Msk                    /*!< Global interrupt enable */

+

+/*******************  Bit definition for RAMECC_CR register  ******************/

+#define RAMECC_CR_ECCELEN_Pos             (5U)

+#define RAMECC_CR_ECCELEN_Msk             (0x1UL << RAMECC_CR_ECCELEN_Pos)      /*!< 0x00000020 */

+#define RAMECC_CR_ECCELEN                 RAMECC_CR_ECCELEN_Msk                 /*!< ECC error latching enable */

+#define RAMECC_CR_ECCDEBWIE_Pos           (4U)

+#define RAMECC_CR_ECCDEBWIE_Msk           (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)    /*!< 0x00000010 */

+#define RAMECC_CR_ECCDEBWIE               RAMECC_CR_ECCDEBWIE_Msk               /*!< ECC double error on byte write (BW) interrupt enable */

+#define RAMECC_CR_ECCDEIE_Pos             (3U)

+#define RAMECC_CR_ECCDEIE_Msk             (0x1UL << RAMECC_CR_ECCDEIE_Pos)      /*!< 0x00000008 */

+#define RAMECC_CR_ECCDEIE                 RAMECC_CR_ECCDEIE_Msk                 /*!< ECC double error interrupt enable */

+#define RAMECC_CR_ECCSEIE_Pos             (2U)

+#define RAMECC_CR_ECCSEIE_Msk             (0x1UL << RAMECC_CR_ECCSEIE_Pos)      /*!< 0x00000004 */

+#define RAMECC_CR_ECCSEIE                 RAMECC_CR_ECCSEIE_Msk                 /*!< ECC single error interrupt enable */

+

+/*******************  Bit definition for RAMECC_SR register  ******************/

+#define RAMECC_SR_DEBWDF_Pos             (2U)

+#define RAMECC_SR_DEBWDF_Msk             (0x1UL << RAMECC_SR_DEBWDF_Pos)        /*!< 0x00000004 */

+#define RAMECC_SR_DEBWDF                 RAMECC_SR_DEBWDF_Msk                   /*!< ECC double error on byte write (BW) detected flag */

+#define RAMECC_SR_DEDF_Pos               (1U)

+#define RAMECC_SR_DEDF_Msk               (0x1UL << RAMECC_SR_DEDF_Pos)          /*!< 0x00000002 */

+#define RAMECC_SR_DEDF                   RAMECC_SR_DEDF_Msk                     /*!< ECC double error detected flag */

+#define RAMECC_SR_SEDCF_Pos              (0U)

+#define RAMECC_SR_SEDCF_Msk              (0x1UL << RAMECC_SR_SEDCF_Pos)         /*!< 0x00000001 */

+#define RAMECC_SR_SEDCF                  RAMECC_SR_SEDCF_Msk                    /*!< ECC single error detected and corrected flag */

+

+/******************  Bit definition for RAMECC_FAR register  ******************/

+#define RAMECC_FAR_FADD_Pos              (0U)

+#define RAMECC_FAR_FADD_Msk              (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)  /*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FADD                  RAMECC_FAR_FADD_Msk                    /*!< ECC error failing address */

+

+/******************  Bit definition for RAMECC_FDRL register  *****************/

+#define RAMECC_FAR_FDATAL_Pos            (0U)

+#define RAMECC_FAR_FDATAL_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FDATAL                RAMECC_FAR_FDATAL_Msk                  /*!< ECC error failing address */

+

+/******************  Bit definition for RAMECC_FDRH register  *****************/

+#define RAMECC_FAR_FDATAH_Pos            (0U)

+#define RAMECC_FAR_FDATAH_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FDATAH                RAMECC_FAR_FDATAH_Msk                  /* Failing data high (64-bit memory) */

+

+/*****************  Bit definition for RAMECC_FECR register  ******************/

+#define RAMECC_FECR_FEC_Pos              (0U)

+#define RAMECC_FECR_FEC_Msk              (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)  /*!< 0xFFFFFFFF */

+#define RAMECC_FECR_FEC                  RAMECC_FECR_FEC_Msk                    /*!< Failing error code */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                MDIOS                                        */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for MDIOS_CR register  *******************/

+#define MDIOS_CR_EN_Pos                (0U)

+#define MDIOS_CR_EN_Msk                (0x1UL << MDIOS_CR_EN_Pos)              /*!< 0x00000001 */

+#define MDIOS_CR_EN                    MDIOS_CR_EN_Msk                         /*!<  MDIOS slave peripheral enable */

+#define MDIOS_CR_WRIE_Pos              (1U)

+#define MDIOS_CR_WRIE_Msk              (0x1UL << MDIOS_CR_WRIE_Pos)            /*!< 0x00000002 */

+#define MDIOS_CR_WRIE                  MDIOS_CR_WRIE_Msk                       /*!<  MDIOS slave register write interrupt enable. */

+#define MDIOS_CR_RDIE_Pos              (2U)

+#define MDIOS_CR_RDIE_Msk              (0x1UL << MDIOS_CR_RDIE_Pos)            /*!< 0x00000004 */

+#define MDIOS_CR_RDIE                  MDIOS_CR_RDIE_Msk                       /*!<  MDIOS slave register read interrupt enable. */

+#define MDIOS_CR_EIE_Pos               (3U)

+#define MDIOS_CR_EIE_Msk               (0x1UL << MDIOS_CR_EIE_Pos)             /*!< 0x00000008 */

+#define MDIOS_CR_EIE                   MDIOS_CR_EIE_Msk                        /*!<  MDIOS slave register error interrupt enable. */

+#define MDIOS_CR_DPC_Pos               (7U)

+#define MDIOS_CR_DPC_Msk               (0x1UL << MDIOS_CR_DPC_Pos)             /*!< 0x00000080 */

+#define MDIOS_CR_DPC                   MDIOS_CR_DPC_Msk                        /*!<  MDIOS slave disable preamble check. */

+#define MDIOS_CR_PORT_ADDRESS_Pos      (8U)

+#define MDIOS_CR_PORT_ADDRESS_Msk      (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)   /*!< 0x00001F00 */

+#define MDIOS_CR_PORT_ADDRESS          MDIOS_CR_PORT_ADDRESS_Msk               /*!<  MDIOS slave port address mask. */

+#define MDIOS_CR_PORT_ADDRESS_0        (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000100 */

+#define MDIOS_CR_PORT_ADDRESS_1        (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000200 */

+#define MDIOS_CR_PORT_ADDRESS_2        (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000400 */

+#define MDIOS_CR_PORT_ADDRESS_3        (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000800 */

+#define MDIOS_CR_PORT_ADDRESS_4        (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001000 */

+

+/********************  Bit definition for MDIOS_SR register  *******************/

+#define MDIOS_SR_PERF_Pos              (0U)

+#define MDIOS_SR_PERF_Msk              (0x1UL << MDIOS_SR_PERF_Pos)            /*!< 0x00000001 */

+#define MDIOS_SR_PERF                  MDIOS_SR_PERF_Msk                       /*!<  MDIOS slave turnaround error flag*/

+#define MDIOS_SR_SERF_Pos              (1U)

+#define MDIOS_SR_SERF_Msk              (0x1UL << MDIOS_SR_SERF_Pos)            /*!< 0x00000002 */

+#define MDIOS_SR_SERF                  MDIOS_SR_SERF_Msk                       /*!<  MDIOS slave start error flag */

+#define MDIOS_SR_TERF_Pos              (2U)

+#define MDIOS_SR_TERF_Msk              (0x1UL << MDIOS_SR_TERF_Pos)            /*!< 0x00000004 */

+#define MDIOS_SR_TERF                  MDIOS_SR_TERF_Msk                       /*!<  MDIOS slave preamble error flag */

+

+/********************  Bit definition for MDIOS_CLRFR register  *******************/

+#define MDIOS_SR_CPERF_Pos             (0U)

+#define MDIOS_SR_CPERF_Msk             (0x1UL << MDIOS_SR_CPERF_Pos)           /*!< 0x00000001 */

+#define MDIOS_SR_CPERF                 MDIOS_SR_CPERF_Msk                      /*!<  MDIOS slave Clear the turnaround error flag */

+#define MDIOS_SR_CSERF_Pos             (1U)

+#define MDIOS_SR_CSERF_Msk             (0x1UL << MDIOS_SR_CSERF_Pos)           /*!< 0x00000002 */

+#define MDIOS_SR_CSERF                 MDIOS_SR_CSERF_Msk                      /*!<  MDIOS slave Clear the start error flag */

+#define MDIOS_SR_CTERF_Pos             (2U)

+#define MDIOS_SR_CTERF_Msk             (0x1UL << MDIOS_SR_CTERF_Pos)           /*!< 0x00000004 */

+#define MDIOS_SR_CTERF                 MDIOS_SR_CTERF_Msk                      /*!<  MDIOS slave Clear the preamble error flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                       USB_OTG                              */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/

+#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)

+#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */

+#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */

+#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)

+#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */

+#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */

+#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)

+#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */

+#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */

+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)

+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */

+#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */

+#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)

+#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */

+#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */

+#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)

+#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */

+#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */

+#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)

+#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */

+#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */

+#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)

+#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */

+#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */

+#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)

+#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */

+#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */

+#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)

+#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */

+#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */

+#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)

+#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */

+#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */

+#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)

+#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */

+#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */

+#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)

+#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */

+#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */

+#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)

+#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */

+#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */

+#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)

+#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */

+#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */

+#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)

+#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */

+#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */

+#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)

+#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */

+#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */

+#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)

+#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */

+#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */

+

+/********************  Bit definition forUSB_OTG_HCFG register  ********************/

+

+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)

+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */

+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */

+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)

+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */

+

+/********************  Bit definition forUSB_OTG_DCFG register  ********************/

+

+#define USB_OTG_DCFG_DSPD_Pos                    (0U)

+#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */

+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */

+#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */

+#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)

+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */

+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */

+

+#define USB_OTG_DCFG_DAD_Pos                     (4U)

+#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */

+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */

+#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */

+#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */

+#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */

+#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */

+#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */

+#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */

+#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */

+

+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)

+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */

+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */

+#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */

+#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */

+

+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)

+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */

+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */

+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */

+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */

+

+/********************  Bit definition forUSB_OTG_PCGCR register  ********************/

+#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)

+#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */

+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */

+#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)

+#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */

+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */

+#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)

+#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */

+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */

+

+/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/

+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)

+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */

+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */

+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)

+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */

+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */

+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)

+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */

+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */

+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)

+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */

+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */

+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)

+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */

+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */

+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)

+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */

+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */

+

+/********************  Bit definition forUSB_OTG_DCTL register  ********************/

+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)

+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */

+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */

+#define USB_OTG_DCTL_SDIS_Pos                    (1U)

+#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */

+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */

+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)

+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */

+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */

+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)

+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */

+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */

+

+#define USB_OTG_DCTL_TCTL_Pos                    (4U)

+#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */

+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */

+#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */

+#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */

+#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */

+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)

+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */

+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */

+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)

+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */

+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */

+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)

+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */

+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */

+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)

+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */

+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */

+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)

+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */

+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */

+

+/********************  Bit definition forUSB_OTG_HFIR register  ********************/

+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)

+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */

+

+/********************  Bit definition forUSB_OTG_HFNUM register  ********************/

+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)

+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */

+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)

+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */

+

+/********************  Bit definition forUSB_OTG_DSTS register  ********************/

+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)

+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */

+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */

+

+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)

+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */

+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */

+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */

+#define USB_OTG_DSTS_EERR_Pos                    (3U)

+#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */

+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */

+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)

+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */

+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */

+

+/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/

+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)

+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */

+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */

+

+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)

+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */

+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */

+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */

+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */

+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */

+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */

+#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */

+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)

+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */

+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */

+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)

+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */

+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */

+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)

+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */

+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */

+

+/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/

+

+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)

+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */

+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */

+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */

+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */

+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */

+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)

+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */

+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */

+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)

+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */

+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */

+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)

+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */

+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */

+

+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)

+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */

+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */

+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */

+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */

+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */

+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */

+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)

+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */

+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */

+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)

+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */

+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */

+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)

+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */

+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */

+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)

+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */

+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */

+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)

+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */

+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */

+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)

+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */

+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */

+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)

+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */

+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */

+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)

+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */

+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */

+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)

+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */

+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */

+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)

+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */

+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */

+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)

+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */

+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */

+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)

+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */

+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */

+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)

+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */

+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */

+

+/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/

+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)

+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */

+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */

+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)

+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */

+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */

+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)

+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */

+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */

+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)

+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */

+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */

+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)

+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */

+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */

+

+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)

+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */

+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */

+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */

+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */

+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */

+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */

+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */

+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)

+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */

+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */

+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)

+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */

+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */

+

+/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/

+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)

+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */

+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)

+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */

+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)

+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */

+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)

+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */

+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)

+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */

+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)

+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */

+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)

+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */

+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)

+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */

+

+/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/

+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)

+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */

+

+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)

+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */

+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */

+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */

+

+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)

+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */

+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */

+

+/********************  Bit definition forUSB_OTG_HAINT register  ********************/

+#define USB_OTG_HAINT_HAINT_Pos                  (0U)

+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */

+

+/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/

+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)

+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */

+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)

+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */

+#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)

+#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */

+#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask               */

+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)

+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */

+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)

+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */

+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)

+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */

+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)

+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */

+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)

+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */

+#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)

+#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */

+#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)

+#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask               */

+#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)

+#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask               */

+#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)

+#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                */

+

+/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/

+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)

+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */

+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */

+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)

+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */

+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */

+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)

+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */

+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */

+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)

+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */

+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */

+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)

+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */

+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */

+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)

+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */

+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */

+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)

+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */

+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */

+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)

+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */

+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */

+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)

+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */

+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */

+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)

+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */

+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */

+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)

+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */

+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */

+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)

+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */

+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */

+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)

+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */

+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */

+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)

+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */

+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */

+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)

+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */

+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */

+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)

+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */

+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */

+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)

+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */

+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */

+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)

+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */

+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */

+#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)

+#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */

+#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */

+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)

+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */

+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */

+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)

+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */

+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */

+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)

+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */

+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */

+#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)

+#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */

+#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */

+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)

+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */

+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */

+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)

+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */

+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */

+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)

+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */

+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */

+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)

+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */

+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */

+

+/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/

+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)

+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */

+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */

+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)

+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */

+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */

+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)

+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */

+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */

+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)

+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */

+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */

+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)

+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */

+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */

+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)

+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */

+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */

+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)

+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */

+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */

+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)

+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */

+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */

+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)

+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */

+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */

+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)

+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */

+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */

+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)

+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */

+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */

+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)

+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */

+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */

+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)

+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */

+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */

+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)

+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */

+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */

+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)

+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */

+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */

+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)

+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */

+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */

+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)

+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */

+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */

+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)

+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */

+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */

+#define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)

+#define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */

+#define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */

+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)

+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */

+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */

+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)

+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */

+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */

+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)

+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */

+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */

+#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)

+#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */

+#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */

+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)

+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */

+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */

+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)

+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */

+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */

+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)

+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */

+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */

+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)

+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */

+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */

+

+/********************  Bit definition forUSB_OTG_DAINT register  ********************/

+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)

+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */

+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)

+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */

+

+/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/

+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)

+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */

+

+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/

+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)

+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */

+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */

+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)

+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */

+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */

+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)

+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */

+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */

+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)

+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */

+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */

+

+/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/

+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)

+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */

+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)

+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */

+

+/********************  Bit definition for OTG register  ********************/

+

+#define USB_OTG_CHNUM_Pos                        (0U)

+#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)  /*!< 0x0000000F */

+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */

+#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */

+#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */

+#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */

+#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */

+#define USB_OTG_BCNT_Pos                         (4U)

+#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */

+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */

+

+#define USB_OTG_DPID_Pos                         (15U)

+#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)   /*!< 0x00018000 */

+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */

+#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */

+#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */

+

+#define USB_OTG_PKTSTS_Pos                       (17U)

+#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */

+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */

+#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */

+#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */

+#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */

+#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */

+

+#define USB_OTG_EPNUM_Pos                        (0U)

+#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)  /*!< 0x0000000F */

+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */

+#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */

+#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */

+#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */

+#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */

+

+#define USB_OTG_FRMNUM_Pos                       (21U)

+#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */

+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */

+#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */

+#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */

+#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */

+#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */

+

+/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/

+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)

+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/

+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)

+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */

+

+/********************  Bit definition for OTG register  ********************/

+#define USB_OTG_NPTXFSA_Pos                      (0U)

+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */

+#define USB_OTG_NPTXFD_Pos                       (16U)

+#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */

+#define USB_OTG_TX0FSA_Pos                       (0U)

+#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */

+#define USB_OTG_TX0FD_Pos                        (16U)

+#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */

+

+/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/

+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)

+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */

+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */

+

+/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/

+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)

+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */

+

+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)

+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */

+

+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)

+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/

+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)

+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */

+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */

+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)

+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */

+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */

+

+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)

+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */

+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */

+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */

+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)

+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */

+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */

+

+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)

+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */

+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */

+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)

+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */

+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */

+

+/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */

+

+/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/

+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)

+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */

+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */

+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)

+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */

+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */

+

+/********************  Bit definition forUSB_OTG_GCCFG register  ********************/

+#define USB_OTG_GCCFG_DCDET_Pos                  (0U)

+#define USB_OTG_GCCFG_DCDET_Msk                  (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */

+#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */

+#define USB_OTG_GCCFG_PDET_Pos                   (1U)

+#define USB_OTG_GCCFG_PDET_Msk                   (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */

+#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */

+#define USB_OTG_GCCFG_SDET_Pos                   (2U)

+#define USB_OTG_GCCFG_SDET_Msk                   (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */

+#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */

+#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)

+#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */

+#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */

+#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)

+#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */

+#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */

+#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)

+#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */

+#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */

+#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)

+#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */

+#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/

+#define USB_OTG_GCCFG_PDEN_Pos                   (19U)

+#define USB_OTG_GCCFG_PDEN_Msk                   (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */

+#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/

+#define USB_OTG_GCCFG_SDEN_Pos                   (20U)

+#define USB_OTG_GCCFG_SDEN_Msk                   (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */

+#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */

+#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)

+#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */

+#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */

+

+/********************  Bit definition forUSB_OTG_GPWRDN) register  ********************/

+#define USB_OTG_GPWRDN_ADPMEN_Pos                (0U)

+#define USB_OTG_GPWRDN_ADPMEN_Msk                (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */

+#define USB_OTG_GPWRDN_ADPMEN                    USB_OTG_GPWRDN_ADPMEN_Msk     /*!< ADP module enable */

+#define USB_OTG_GPWRDN_ADPIF_Pos                 (23U)

+#define USB_OTG_GPWRDN_ADPIF_Msk                 (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */

+#define USB_OTG_GPWRDN_ADPIF                     USB_OTG_GPWRDN_ADPIF_Msk      /*!< ADP Interrupt flag */

+

+/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/

+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)

+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */

+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)

+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */

+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */

+

+/********************  Bit definition forUSB_OTG_CID register  ********************/

+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)

+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */

+

+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/

+#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)

+#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */

+#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */

+#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)

+#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */

+#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */

+#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)

+#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */

+#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */

+#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)

+#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */

+#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */

+#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)

+#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */

+#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */

+#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)

+#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */

+#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */

+#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)

+#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */

+#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */

+#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)

+#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */

+#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */

+#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)

+#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */

+#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */

+#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)

+#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */

+#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */

+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)

+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */

+#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */

+#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)

+#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */

+#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */

+#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)

+#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */

+#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */

+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)

+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */

+#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */

+#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)

+#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */

+#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */

+

+/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/

+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)

+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */

+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)

+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */

+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)

+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */

+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)

+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */

+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)

+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */

+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)

+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */

+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)

+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */

+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)

+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */

+

+/********************  Bit definition forUSB_OTG_HPRT register  ********************/

+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)

+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */

+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */

+#define USB_OTG_HPRT_PCDET_Pos                   (1U)

+#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */

+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */

+#define USB_OTG_HPRT_PENA_Pos                    (2U)

+#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */

+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */

+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)

+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */

+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */

+#define USB_OTG_HPRT_POCA_Pos                    (4U)

+#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */

+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */

+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)

+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */

+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */

+#define USB_OTG_HPRT_PRES_Pos                    (6U)

+#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */

+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume   */

+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)

+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */

+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend  */

+#define USB_OTG_HPRT_PRST_Pos                    (8U)

+#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */

+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset    */

+

+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)

+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */

+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */

+#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */

+#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */

+#define USB_OTG_HPRT_PPWR_Pos                    (12U)

+#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */

+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */

+

+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)

+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */

+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */

+#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */

+#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */

+#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */

+#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */

+

+#define USB_OTG_HPRT_PSPD_Pos                    (17U)

+#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */

+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */

+#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */

+#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */

+

+/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/

+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)

+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)

+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)

+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */

+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)

+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */

+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)

+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */

+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)

+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */

+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)

+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)

+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)

+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)

+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */

+

+/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/

+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)

+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */

+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)

+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/

+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)

+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */

+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)

+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */

+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */

+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)

+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */

+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */

+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)

+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */

+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */

+

+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)

+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */

+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */

+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)

+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */

+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */

+

+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)

+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */

+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */

+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */

+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */

+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */

+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */

+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)

+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */

+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */

+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)

+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */

+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */

+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)

+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */

+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)

+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */

+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)

+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */

+

+/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/

+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)

+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */

+

+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)

+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */

+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */

+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */

+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */

+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */

+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */

+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)

+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */

+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */

+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)

+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */

+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */

+

+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)

+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */

+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */

+

+#define USB_OTG_HCCHAR_MC_Pos                    (20U)

+#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */

+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */

+#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */

+#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */

+

+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)

+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */

+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */

+#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */

+#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */

+#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */

+#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */

+#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */

+#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */

+#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */

+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)

+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */

+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)

+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */

+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)

+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */

+

+/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/

+

+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)

+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */

+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */

+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */

+

+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)

+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */

+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */

+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */

+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */

+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */

+

+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)

+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */

+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */

+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */

+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */

+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)

+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */

+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */

+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)

+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */

+

+/********************  Bit definition forUSB_OTG_HCINT register  ********************/

+#define USB_OTG_HCINT_XFRC_Pos                   (0U)

+#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */

+#define USB_OTG_HCINT_CHH_Pos                    (1U)

+#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */

+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)

+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */

+#define USB_OTG_HCINT_STALL_Pos                  (3U)

+#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */

+#define USB_OTG_HCINT_NAK_Pos                    (4U)

+#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */

+#define USB_OTG_HCINT_ACK_Pos                    (5U)

+#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */

+#define USB_OTG_HCINT_NYET_Pos                   (6U)

+#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */

+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */

+#define USB_OTG_HCINT_TXERR_Pos                  (7U)

+#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */

+#define USB_OTG_HCINT_BBERR_Pos                  (8U)

+#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */

+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)

+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */

+#define USB_OTG_HCINT_DTERR_Pos                  (10U)

+#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */

+

+/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/

+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)

+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */

+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)

+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */

+#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)

+#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */

+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)

+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */

+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)

+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */

+#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)

+#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */

+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)

+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */

+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)

+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */

+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */

+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)

+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */

+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)

+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */

+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)

+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */

+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */

+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)

+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */

+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */

+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)

+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */

+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */

+

+/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/

+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)

+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */

+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)

+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */

+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)

+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */

+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)

+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */

+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)

+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */

+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)

+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */

+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)

+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */

+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */

+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)

+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */

+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)

+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */

+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)

+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */

+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)

+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */

+

+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/

+

+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)

+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */

+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)

+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */

+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)

+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */

+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */

+/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/

+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)

+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */

+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)

+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */

+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)

+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */

+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)

+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */

+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */

+#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */

+#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/

+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)

+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */

+

+/********************  Bit definition forUSB_OTG_HCDMA register  ********************/

+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)

+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */

+

+/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/

+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)

+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */

+

+/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/

+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)

+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */

+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)

+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/

+

+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)

+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */

+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)

+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */

+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */

+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)

+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */

+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */

+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)

+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */

+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)

+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */

+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */

+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)

+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */

+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */

+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)

+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */

+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */

+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)

+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */

+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */

+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)

+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */

+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */

+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)

+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */

+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)

+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */

+

+/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/

+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)

+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */

+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)

+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */

+#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)

+#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */

+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)

+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */

+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)

+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */

+#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)

+#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< OUT Status Phase Received interrupt */

+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)

+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */

+#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)

+#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */

+#define USB_OTG_DOEPINT_BERR_Pos                 (12U)

+#define USB_OTG_DOEPINT_BERR_Msk                 (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPINT_BERR                      USB_OTG_DOEPINT_BERR_Msk   /*!< Babble error interrupt */

+#define USB_OTG_DOEPINT_NAK_Pos                  (13U)

+#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */

+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)

+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */

+#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)

+#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */

+#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */

+

+/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/

+

+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)

+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */

+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)

+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */

+

+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)

+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */

+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */

+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */

+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition for PCGCCTL register  ********************/

+#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)

+#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */

+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */

+#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)

+#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */

+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */

+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)

+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */

+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/** @addtogroup Exported_macros

+  * @{

+  */

+

+/******************************* ADC Instances ********************************/

+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \

+                                       ((INSTANCE) == ADC2) || \

+                                       ((INSTANCE) == ADC3))

+

+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)

+

+#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) ||\

+                                          ((INSTANCE) == ADC3_COMMON))

+

+/******************************** COMP Instances ******************************/

+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \

+                                       ((INSTANCE) == COMP2))

+

+#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)

+/******************** COMP Instances with window mode capability **************/

+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)

+

+

+/******************************* CRC Instances ********************************/

+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

+

+/******************************* DAC Instances ********************************/

+#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)

+/******************************* DCMI Instances *******************************/

+#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)

+

+/******************************* DELAYBLOCK Instances *******************************/

+#define IS_DLYB_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DLYB_SDMMC1) || \

+                                         ((INSTANCE) == DLYB_SDMMC2) || \

+                                         ((INSTANCE) == DLYB_QUADSPI))

+/****************************** DFSDM Instances *******************************/

+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \

+                                               ((INSTANCE) == DFSDM1_Filter1) || \

+                                               ((INSTANCE) == DFSDM1_Filter2) || \

+                                               ((INSTANCE) == DFSDM1_Filter3))

+

+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \

+                                                 ((INSTANCE) == DFSDM1_Channel1) || \

+                                                 ((INSTANCE) == DFSDM1_Channel2) || \

+                                                 ((INSTANCE) == DFSDM1_Channel3) || \

+                                                 ((INSTANCE) == DFSDM1_Channel4) || \

+                                                 ((INSTANCE) == DFSDM1_Channel5) || \

+                                                 ((INSTANCE) == DFSDM1_Channel6) || \

+                                                 ((INSTANCE) == DFSDM1_Channel7))

+/****************************** RAMECC Instances ******************************/

+#define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC1_Monitor1)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor2)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor3)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor4)   || \

+                                                  ((INSTANCE) == RAMECC1_Monitor5)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor1)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor2)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor3)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor4)   || \

+                                                  ((INSTANCE) == RAMECC2_Monitor5)   || \

+                                                  ((INSTANCE) == RAMECC3_Monitor1)   || \

+                                                  ((INSTANCE) == RAMECC3_Monitor2))

+

+/******************************** DMA Instances *******************************/

+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \

+                                       ((INSTANCE) == DMA1_Stream1)   || \

+                                       ((INSTANCE) == DMA1_Stream2)   || \

+                                       ((INSTANCE) == DMA1_Stream3)   || \

+                                       ((INSTANCE) == DMA1_Stream4)   || \

+                                       ((INSTANCE) == DMA1_Stream5)   || \

+                                       ((INSTANCE) == DMA1_Stream6)   || \

+                                       ((INSTANCE) == DMA1_Stream7)   || \

+                                       ((INSTANCE) == DMA2_Stream0)   || \

+                                       ((INSTANCE) == DMA2_Stream1)   || \

+                                       ((INSTANCE) == DMA2_Stream2)   || \

+                                       ((INSTANCE) == DMA2_Stream3)   || \

+                                       ((INSTANCE) == DMA2_Stream4)   || \

+                                       ((INSTANCE) == DMA2_Stream5)   || \

+                                       ((INSTANCE) == DMA2_Stream6)   || \

+                                       ((INSTANCE) == DMA2_Stream7)   || \

+                                       ((INSTANCE) == BDMA_Channel0) || \

+                                       ((INSTANCE) == BDMA_Channel1) || \

+                                       ((INSTANCE) == BDMA_Channel2) || \

+                                       ((INSTANCE) == BDMA_Channel3) || \

+                                       ((INSTANCE) == BDMA_Channel4) || \

+                                       ((INSTANCE) == BDMA_Channel5) || \

+                                       ((INSTANCE) == BDMA_Channel6) || \

+                                       ((INSTANCE) == BDMA_Channel7))

+

+/****************************** BDMA CHANNEL Instances ***************************/

+#define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \

+                                            ((INSTANCE) == BDMA_Channel1) || \

+                                            ((INSTANCE) == BDMA_Channel2) || \

+                                            ((INSTANCE) == BDMA_Channel3) || \

+                                            ((INSTANCE) == BDMA_Channel4) || \

+                                            ((INSTANCE) == BDMA_Channel5) || \

+                                            ((INSTANCE) == BDMA_Channel6) || \

+                                            ((INSTANCE) == BDMA_Channel7))

+

+/****************************** DMA DMAMUX ALL Instances ***************************/

+#define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)    || \

+                                               ((INSTANCE) == DMA1_Stream1)    || \

+                                               ((INSTANCE) == DMA1_Stream2)    || \

+                                               ((INSTANCE) == DMA1_Stream3)    || \

+                                               ((INSTANCE) == DMA1_Stream4)    || \

+                                               ((INSTANCE) == DMA1_Stream5)    || \

+                                               ((INSTANCE) == DMA1_Stream6)    || \

+                                               ((INSTANCE) == DMA1_Stream7)    || \

+                                               ((INSTANCE) == DMA2_Stream0)    || \

+                                               ((INSTANCE) == DMA2_Stream1)    || \

+                                               ((INSTANCE) == DMA2_Stream2)    || \

+                                               ((INSTANCE) == DMA2_Stream3)    || \

+                                               ((INSTANCE) == DMA2_Stream4)    || \

+                                               ((INSTANCE) == DMA2_Stream5)    || \

+                                               ((INSTANCE) == DMA2_Stream6)    || \

+                                               ((INSTANCE) == DMA2_Stream7)    || \

+                                               ((INSTANCE) == BDMA_Channel0)   || \

+                                               ((INSTANCE) == BDMA_Channel1)   || \

+                                               ((INSTANCE) == BDMA_Channel2)   || \

+                                               ((INSTANCE) == BDMA_Channel3)   || \

+                                               ((INSTANCE) == BDMA_Channel4)   || \

+                                               ((INSTANCE) == BDMA_Channel5)   || \

+                                               ((INSTANCE) == BDMA_Channel6)   || \

+                                               ((INSTANCE) == BDMA_Channel7))

+

+/****************************** BDMA DMAMUX Instances ***************************/

+#define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == BDMA_Channel0) || \

+                                                    ((INSTANCE) == BDMA_Channel1) || \

+                                                    ((INSTANCE) == BDMA_Channel2) || \

+                                                    ((INSTANCE) == BDMA_Channel3) || \

+                                                    ((INSTANCE) == BDMA_Channel4) || \

+                                                    ((INSTANCE) == BDMA_Channel5) || \

+                                                    ((INSTANCE) == BDMA_Channel6) || \

+                                                    ((INSTANCE) == BDMA_Channel7))

+

+/****************************** DMA STREAM Instances ***************************/

+#define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \

+                                          ((INSTANCE) == DMA1_Stream1)   || \

+                                          ((INSTANCE) == DMA1_Stream2)   || \

+                                          ((INSTANCE) == DMA1_Stream3)   || \

+                                          ((INSTANCE) == DMA1_Stream4)   || \

+                                          ((INSTANCE) == DMA1_Stream5)   || \

+                                          ((INSTANCE) == DMA1_Stream6)   || \

+                                          ((INSTANCE) == DMA1_Stream7)   || \

+                                          ((INSTANCE) == DMA2_Stream0)   || \

+                                          ((INSTANCE) == DMA2_Stream1)   || \

+                                          ((INSTANCE) == DMA2_Stream2)   || \

+                                          ((INSTANCE) == DMA2_Stream3)   || \

+                                          ((INSTANCE) == DMA2_Stream4)   || \

+                                          ((INSTANCE) == DMA2_Stream5)   || \

+                                          ((INSTANCE) == DMA2_Stream6)   || \

+                                          ((INSTANCE) == DMA2_Stream7))

+

+/****************************** DMA DMAMUX Instances ***************************/

+#define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)   || \

+                                                  ((INSTANCE) == DMA1_Stream1)   || \

+                                                  ((INSTANCE) == DMA1_Stream2)   || \

+                                                  ((INSTANCE) == DMA1_Stream3)   || \

+                                                  ((INSTANCE) == DMA1_Stream4)   || \

+                                                  ((INSTANCE) == DMA1_Stream5)   || \

+                                                  ((INSTANCE) == DMA1_Stream6)   || \

+                                                  ((INSTANCE) == DMA1_Stream7)   || \

+                                                  ((INSTANCE) == DMA2_Stream0)   || \

+                                                  ((INSTANCE) == DMA2_Stream1)   || \

+                                                  ((INSTANCE) == DMA2_Stream2)   || \

+                                                  ((INSTANCE) == DMA2_Stream3)   || \

+                                                  ((INSTANCE) == DMA2_Stream4)   || \

+                                                  ((INSTANCE) == DMA2_Stream5)   || \

+                                                  ((INSTANCE) == DMA2_Stream6)   || \

+                                                  ((INSTANCE) == DMA2_Stream7))

+

+/******************************** DMA Request Generator Instances **************/

+#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator1) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator2) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator3) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator4) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator5) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator6) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator7) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator0) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator1) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator2) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator3) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator4) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator5) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator6) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator7))

+

+/******************************* DMA2D Instances *******************************/

+#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)

+

+/******************************** MDMA Request Generator Instances **************/

+#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0)  || \

+                                               ((INSTANCE) == MDMA_Channel1)  || \

+                                               ((INSTANCE) == MDMA_Channel2)  || \

+                                               ((INSTANCE) == MDMA_Channel3)  || \

+                                               ((INSTANCE) == MDMA_Channel4)  || \

+                                               ((INSTANCE) == MDMA_Channel5)  || \

+                                               ((INSTANCE) == MDMA_Channel6)  || \

+                                               ((INSTANCE) == MDMA_Channel7)  || \

+                                               ((INSTANCE) == MDMA_Channel8)  || \

+                                               ((INSTANCE) == MDMA_Channel9)  || \

+                                               ((INSTANCE) == MDMA_Channel10) || \

+                                               ((INSTANCE) == MDMA_Channel11) || \

+                                               ((INSTANCE) == MDMA_Channel12) || \

+                                               ((INSTANCE) == MDMA_Channel13) || \

+                                               ((INSTANCE) == MDMA_Channel14) || \

+                                               ((INSTANCE) == MDMA_Channel15))

+

+/******************************* QUADSPI Instances *******************************/

+#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)

+

+/******************************* FDCAN Instances ******************************/

+#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \

+                                             ((__INSTANCE__) == FDCAN2))

+

+#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)

+

+/******************************* GPIO Instances *******************************/

+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \

+                                        ((INSTANCE) == GPIOB) || \

+                                        ((INSTANCE) == GPIOC) || \

+                                        ((INSTANCE) == GPIOD) || \

+                                        ((INSTANCE) == GPIOE) || \

+                                        ((INSTANCE) == GPIOF) || \

+                                        ((INSTANCE) == GPIOG) || \

+                                        ((INSTANCE) == GPIOH) || \

+                                        ((INSTANCE) == GPIOI) || \

+                                        ((INSTANCE) == GPIOJ) || \

+                                        ((INSTANCE) == GPIOK))

+

+/******************************* GPIO AF Instances ****************************/

+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)

+

+/**************************** GPIO Lock Instances *****************************/

+/* On H7, all GPIO Bank support the Lock mechanism */

+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)

+

+/******************************** HSEM Instances *******************************/

+#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)

+/********************  Bit definition for HSEM_CR register  *****************/

+#define HSEM_CPU1_COREID    (0x00000003U) /* Semaphore Core CM7 ID */

+#define HSEM_CPU2_COREID    (0x00000001U) /* Semaphore Core CM4 ID */

+#define HSEM_CR_COREID_CPU1      (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)

+#define HSEM_CR_COREID_CPU2      (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos)

+#if defined(CORE_CM4)

+#define HSEM_CR_COREID_CURRENT   (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos)

+#else  /* CORE_CM7 */

+#define HSEM_CR_COREID_CURRENT   (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)

+#endif /* CORE_CM4 */

+

+#define HSEM_SEMID_MIN     (0U)       /* HSEM ID Min*/

+#define HSEM_SEMID_MAX     (31U)      /* HSEM ID Max */

+

+#define HSEM_PROCESSID_MIN (0U)       /* HSEM Process ID Min */

+#define HSEM_PROCESSID_MAX (255U)     /* HSEM Process ID Max */

+

+#define HSEM_CLEAR_KEY_MIN (0U)       /* HSEM clear Key Min value */

+#define HSEM_CLEAR_KEY_MAX (0xFFFFU)  /* HSEM clear Key Max value */

+

+/******************************** I2C Instances *******************************/

+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

+                                       ((INSTANCE) == I2C2) || \

+                                       ((INSTANCE) == I2C3) || \

+                                       ((INSTANCE) == I2C4))

+/************** I2C Instances : wakeup capability from stop modes *************/

+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)

+

+/****************************** SMBUS Instances *******************************/

+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

+                                         ((INSTANCE) == I2C2) || \

+                                         ((INSTANCE) == I2C3) || \

+                                         ((INSTANCE) == I2C4))

+/******************************** I2S Instances *******************************/

+#define IS_I2S_ALL_INSTANCE(INSTANCE)   (((INSTANCE) == SPI1) || \

+                                         ((INSTANCE) == SPI2) || \

+                                         ((INSTANCE) == SPI3))

+

+/****************************** LTDC Instances ********************************/

+#define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)

+

+/******************************* RNG Instances ********************************/

+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)

+

+/****************************** RTC Instances *********************************/

+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)

+

+/****************************** SDMMC Instances *********************************/

+#define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \

+                                           ((_INSTANCE_) == SDMMC2))

+

+/******************************** SMBUS Instances *****************************/

+#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)

+

+/******************************** SPI Instances *******************************/

+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \

+                                       ((INSTANCE) == SPI2) || \

+                                       ((INSTANCE) == SPI3) || \

+                                       ((INSTANCE) == SPI4) || \

+                                       ((INSTANCE) == SPI5) || \

+                                       ((INSTANCE) == SPI6))

+

+#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \

+                                           ((INSTANCE) == SPI2) || \

+                                           ((INSTANCE) == SPI3))

+

+/******************************** SWPMI Instances *****************************/

+#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)

+

+/****************** LPTIM Instances : All supported instances *****************/

+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \

+                                         ((INSTANCE) == LPTIM2) || \

+                                         ((INSTANCE) == LPTIM3) || \

+                                         ((INSTANCE) == LPTIM4) || \

+                                         ((INSTANCE) == LPTIM5))

+

+/****************** LPTIM Instances : supporting encoder interface **************/

+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \

+                                                           ((INSTANCE) == LPTIM2))

+

+/****************** TIM Instances : All supported instances *******************/

+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM6)   || \

+                                         ((INSTANCE) == TIM7)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM13)  || \

+                                         ((INSTANCE) == TIM14)  || \

+                                         ((INSTANCE) == TIM15)  || \

+                                         ((INSTANCE) == TIM16)  || \

+                                         ((INSTANCE) == TIM17))

+

+/************* TIM Instances : at least 1 capture/compare channel *************/

+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM13)  || \

+                                         ((INSTANCE) == TIM14)  || \

+                                         ((INSTANCE) == TIM15)  || \

+                                         ((INSTANCE) == TIM16)  || \

+                                         ((INSTANCE) == TIM17))

+

+/************ TIM Instances : at least 2 capture/compare channels *************/

+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM15))

+

+/************ TIM Instances : at least 3 capture/compare channels *************/

+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8))

+

+/************ TIM Instances : at least 4 capture/compare channels *************/

+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8))

+

+/************ TIM Instances : at least 5 capture/compare channels *************/

+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM8))

+/************ TIM Instances : at least 6 capture/compare channels *************/

+#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM8))

+

+/******************** TIM Instances : Advanced-control timers *****************/

+#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \

+                                                ((__INSTANCE__) == TIM8))

+

+/******************** TIM Instances : Advanced-control timers *****************/

+

+/******************* TIM Instances : Timer input XOR function *****************/

+#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : DMA requests generation (UDE) *************/

+#define IS_TIM_DMA_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM6)   || \

+                                           ((INSTANCE) == TIM7)   || \

+                                           ((INSTANCE) == TIM8)   || \

+                                           ((INSTANCE) == TIM15)  || \

+                                           ((INSTANCE) == TIM16)  || \

+                                           ((INSTANCE) == TIM17))

+

+/************ TIM Instances : DMA requests generation (CCxDE) *****************/

+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15)  || \

+                                            ((INSTANCE) == TIM16)  || \

+                                            ((INSTANCE) == TIM17))

+

+/************ TIM Instances : DMA requests generation (COMDE) *****************/

+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15))

+

+/******************** TIM Instances : DMA burst feature ***********************/

+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8))

+

+/*************** TIM Instances : external trigger reamp input available *******/

+#define IS_TIM_ETR_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : remapping capability **********************/

+#define IS_TIM_REMAP_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \

+                                          ((INSTANCE) == TIM2)  || \

+                                          ((INSTANCE) == TIM3)  || \

+                                          ((INSTANCE) == TIM5)  || \

+                                          ((INSTANCE) == TIM8)  || \

+                                          ((INSTANCE) == TIM16) || \

+                                          ((INSTANCE) == TIM17))

+

+/*************** TIM Instances : external trigger reamp input available *******/

+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                              ((INSTANCE) == TIM2)   || \

+                                              ((INSTANCE) == TIM3)   || \

+                                              ((INSTANCE) == TIM5)   || \

+                                              ((INSTANCE) == TIM8))

+

+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/

+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM6)   || \

+                                            ((INSTANCE) == TIM7)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15))

+

+/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/

+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM8)   || \

+                                           ((INSTANCE) == TIM12))

+

+/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/

+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM8))

+

+/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/

+#define IS_TIM_TISEL_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)   || \

+                                          ((INSTANCE) == TIM2)   || \

+                                          ((INSTANCE) == TIM3)   || \

+                                          ((INSTANCE) == TIM4)   || \

+                                          ((INSTANCE) == TIM5)   || \

+                                          ((INSTANCE) == TIM8)   || \

+                                          ((INSTANCE) == TIM15)  || \

+                                          ((INSTANCE) == TIM16)  || \

+                                          ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting commutation event *************/

+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \

+                                                     ((INSTANCE) == TIM8)    || \

+                                                     ((INSTANCE) == TIM15)   || \

+                                                     ((INSTANCE) == TIM16)   || \

+                                                     ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting encoder interface **************/

+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1)  || \

+                                                      ((__INSTANCE__) == TIM2)      || \

+                                                      ((__INSTANCE__) == TIM3)      || \

+                                                      ((__INSTANCE__) == TIM4)      || \

+                                                      ((__INSTANCE__) == TIM5)      || \

+                                                      ((__INSTANCE__) == TIM8))

+

+/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/

+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                                       ((INSTANCE) == TIM8))

+/******************* TIM Instances : output(s) available **********************/

+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \

+    ((((INSTANCE) == TIM1) &&                  \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4) ||          \

+      ((CHANNEL) == TIM_CHANNEL_5) ||          \

+      ((CHANNEL) == TIM_CHANNEL_6)))           \

+     ||                                        \

+     (((INSTANCE) == TIM2) &&                  \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM3) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1)||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM4) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM5) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM8) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4) ||          \

+      ((CHANNEL) == TIM_CHANNEL_5) ||          \

+      ((CHANNEL) == TIM_CHANNEL_6)))           \

+  ||                                           \

+     (((INSTANCE) == TIM12) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2)))           \

+  ||                                           \

+     (((INSTANCE) == TIM13) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM14) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM15) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+     ((CHANNEL) == TIM_CHANNEL_2)))            \

+  ||                                           \

+     (((INSTANCE) == TIM16) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM17) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1))))

+

+/****************** TIM Instances : supporting the break function *************/

+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\

+      (((INSTANCE) == TIM1)    || \

+      ((INSTANCE) == TIM8)     || \

+       ((INSTANCE) == TIM15)   || \

+       ((INSTANCE) == TIM16)   || \

+       ((INSTANCE) == TIM17))

+

+/************** TIM Instances : supporting Break source selection *************/

+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \

+                                               ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting complementary output(s) ********/

+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \

+   ((((INSTANCE) == TIM1) &&                    \

+     (((CHANNEL) == TIM_CHANNEL_1) ||           \

+      ((CHANNEL) == TIM_CHANNEL_2) ||           \

+      ((CHANNEL) == TIM_CHANNEL_3)))            \

+ ||                                             \

+      (((INSTANCE) == TIM8) &&                  \

+      (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||           \

+      ((CHANNEL) == TIM_CHANNEL_3)))            \

+    ||                                          \

+    (((INSTANCE) == TIM15) &&                   \

+      ((CHANNEL) == TIM_CHANNEL_1))             \

+    ||                                          \

+    (((INSTANCE) == TIM16) &&                   \

+     ((CHANNEL) == TIM_CHANNEL_1))              \

+    ||                                          \

+    (((INSTANCE) == TIM17) &&                   \

+     ((CHANNEL) == TIM_CHANNEL_1)))

+

+/****************** TIM Instances : supporting counting mode selection ********/

+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting repetition counter *************/

+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15)   || \

+   ((INSTANCE) == TIM16)   || \

+   ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting synchronization ****************/

+#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\

+    (((__INSTANCE__) == TIM1)    || \

+     ((__INSTANCE__) == TIM2)    || \

+     ((__INSTANCE__) == TIM3)    || \

+     ((__INSTANCE__) == TIM4)    || \

+     ((__INSTANCE__) == TIM5)    || \

+     ((__INSTANCE__) == TIM6)    || \

+     ((__INSTANCE__) == TIM8)    || \

+     ((__INSTANCE__) == TIM12)   || \

+     ((__INSTANCE__) == TIM15))

+

+/****************** TIM Instances : supporting clock division *****************/

+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15)   || \

+   ((INSTANCE) == TIM16)   || \

+   ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting external clock mode 1 for ETRF input */

+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting external clock mode 2 **********/

+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\

+ (((INSTANCE) == TIM1)     || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/

+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/

+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : supporting OCxREF clear *******************/

+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3))

+

+/****************** TIM Instances : TIM_32B_COUNTER ***************************/

+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM5))

+

+/****************** TIM Instances : TIM_BKIN2 ***************************/

+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting Hall sensor interface **********/

+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)  || \

+                                                             ((__INSTANCE__) == TIM2)  || \

+                                                             ((__INSTANCE__) == TIM3)  || \

+                                                             ((__INSTANCE__) == TIM4)  || \

+                                                             ((__INSTANCE__) == TIM5)  || \

+                                                             ((__INSTANCE__) == TIM15) || \

+                                                             ((__INSTANCE__) == TIM8))

+

+/****************************** HRTIM Instances *******************************/

+#define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))

+

+/******************** USART Instances : Synchronous mode **********************/

+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                     ((INSTANCE) == USART2) || \

+                                     ((INSTANCE) == USART3) || \

+                                     ((INSTANCE) == USART6))

+

+/******************** USART Instances : SPI slave mode ************************/

+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                              ((INSTANCE) == USART2) || \

+                                              ((INSTANCE) == USART3) || \

+                                              ((INSTANCE) == USART6))

+

+/******************** UART Instances : Asynchronous mode **********************/

+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                    ((INSTANCE) == USART2) || \

+                                    ((INSTANCE) == USART3) || \

+                                    ((INSTANCE) == UART4)  || \

+                                    ((INSTANCE) == UART5)  || \

+                                    ((INSTANCE) == USART6) || \

+                                    ((INSTANCE) == UART7)  || \

+                                    ((INSTANCE) == UART8))

+

+/******************** UART Instances : FIFO mode.******************************/

+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                         ((INSTANCE) == USART2) || \

+                                         ((INSTANCE) == USART3) || \

+                                         ((INSTANCE) == UART4)  || \

+                                         ((INSTANCE) == UART5)  || \

+                                         ((INSTANCE) == USART6) || \

+                                         ((INSTANCE) == UART7)  || \

+                                         ((INSTANCE) == UART8))

+

+/****************** UART Instances : Auto Baud Rate detection *****************/

+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                            ((INSTANCE) == USART2) || \

+                                                            ((INSTANCE) == USART3) || \

+                                                            ((INSTANCE) == UART4)  || \

+                                                            ((INSTANCE) == UART5)  || \

+                                                            ((INSTANCE) == USART6) || \

+                                                            ((INSTANCE) == UART7)  || \

+                                                            ((INSTANCE) == UART8))

+

+/*********************** UART Instances : Driver Enable ***********************/

+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                  ((INSTANCE) == USART2) || \

+                                                  ((INSTANCE) == USART3) || \

+                                                  ((INSTANCE) == UART4)  || \

+                                                  ((INSTANCE) == UART5)  || \

+                                                  ((INSTANCE) == USART6) || \

+                                                  ((INSTANCE) == UART7)  || \

+                                                  ((INSTANCE) == UART8)  || \

+                                                  ((INSTANCE) == LPUART1))

+

+/********************* UART Instances : Half-Duplex mode **********************/

+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                               ((INSTANCE) == USART2) || \

+                                               ((INSTANCE) == USART3) || \

+                                               ((INSTANCE) == UART4)  || \

+                                               ((INSTANCE) == UART5)  || \

+                                               ((INSTANCE) == USART6) || \

+                                               ((INSTANCE) == UART7)  || \

+                                               ((INSTANCE) == UART8)  || \

+                                               ((INSTANCE) == LPUART1))

+

+/******************* UART Instances : Hardware Flow control *******************/

+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                           ((INSTANCE) == USART2) || \

+                                           ((INSTANCE) == USART3) || \

+                                           ((INSTANCE) == UART4)  || \

+                                           ((INSTANCE) == UART5)  || \

+                                           ((INSTANCE) == USART6) || \

+                                           ((INSTANCE) == UART7)  || \

+                                           ((INSTANCE) == UART8)  || \

+                                           ((INSTANCE) == LPUART1))

+

+/************************* UART Instances : LIN mode **************************/

+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                        ((INSTANCE) == USART2) || \

+                                        ((INSTANCE) == USART3) || \

+                                        ((INSTANCE) == UART4)  || \

+                                        ((INSTANCE) == UART5)  || \

+                                        ((INSTANCE) == USART6) || \

+                                        ((INSTANCE) == UART7)  || \

+                                        ((INSTANCE) == UART8))

+

+/****************** UART Instances : Wake-up from Stop mode *******************/

+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                    ((INSTANCE) == USART2) || \

+                                                    ((INSTANCE) == USART3) || \

+                                                    ((INSTANCE) == UART4)  || \

+                                                    ((INSTANCE) == UART5)  || \

+                                                    ((INSTANCE) == USART6) || \

+                                                    ((INSTANCE) == UART7)  || \

+                                                    ((INSTANCE) == UART8)  || \

+                                                    ((INSTANCE) == LPUART1))

+

+/************************* UART Instances : IRDA mode *************************/

+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                    ((INSTANCE) == USART2) || \

+                                    ((INSTANCE) == USART3) || \

+                                    ((INSTANCE) == UART4)  || \

+                                    ((INSTANCE) == UART5)  || \

+                                    ((INSTANCE) == USART6) || \

+                                    ((INSTANCE) == UART7)  || \

+                                    ((INSTANCE) == UART8))

+

+/********************* USART Instances : Smard card mode **********************/

+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                         ((INSTANCE) == USART2) || \

+                                         ((INSTANCE) == USART3) || \

+                                         ((INSTANCE) == USART6))

+

+/****************************** LPUART Instance *******************************/

+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)

+

+/****************************** IWDG Instances ********************************/

+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2))

+/****************************** USB Instances ********************************/

+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)

+

+/****************************** WWDG Instances ********************************/

+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == WWDG1) || \

+                                         ((INSTANCE) == WWDG2))

+/****************************** MDIOS Instances ********************************/

+#define IS_MDIOS_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == MDIOS)

+

+/****************************** CEC Instances *********************************/

+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)

+

+/****************************** SAI Instances ********************************/

+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \

+                    ((INSTANCE) == SAI1_Block_B) || \

+                     ((INSTANCE) == SAI2_Block_A) || \

+                     ((INSTANCE) == SAI2_Block_B) || \

+                     ((INSTANCE) == SAI3_Block_A) || \

+                     ((INSTANCE) == SAI3_Block_B) || \

+                     ((INSTANCE) == SAI4_Block_A) || \

+                     ((INSTANCE) == SAI4_Block_B))

+

+/****************************** SPDIFRX Instances ********************************/

+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)

+

+/****************************** OPAMP Instances *******************************/

+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \

+                                         ((INSTANCE) == OPAMP2))

+

+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)

+

+/*********************** USB OTG PCD Instances ********************************/

+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \

+                                        ((INSTANCE) == USB_OTG_HS))

+

+/*********************** USB OTG HCD Instances ********************************/

+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \

+                                       ((INSTANCE) == USB_OTG_HS))

+

+/******************************************************************************/

+/*  For a painless codes migration between the STM32H7xx device product       */

+/*  lines, or with STM32F7xx devices the aliases defined below are put        */

+/*   in place to overcome the differences in the interrupt handlers and IRQn  */

+/*   definitions. No need to update developed interrupt code when moving      */

+/*  across product lines within the same STM32H7 Family                       */

+/******************************************************************************/

+

+/* Aliases for __IRQn */

+#define  RNG_IRQn                       HASH_RNG_IRQn

+#define  TIM1_BRK_TIM9_IRQn             TIM1_BRK_IRQn

+#define  TIM1_UP_TIM10_IRQn             TIM1_UP_IRQn

+#define  TIM1_TRG_COM_TIM11_IRQn        TIM1_TRG_COM_IRQn

+#define  PVD_IRQn                       PVD_AVD_IRQn

+

+

+

+/* Aliases for __IRQHandler */

+#define   RNG_IRQHandler               HASH_RNG_IRQHandler

+#define TIM1_BRK_TIM9_IRQHandler       TIM1_BRK_IRQHandler

+#define TIM1_UP_TIM9_IRQHandler        TIM1_UP_IRQHandler

+#define TIM1_TRG_COM_TIM11_IRQHandler  TIM1_TRG_COM_IRQHandler

+#define PVD_IRQHandler                 PVD_AVD_IRQHandler

+

+/* Aliases for COMP __IRQHandler */

+#define COMP_IRQHandler                COMP1_IRQHandler

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif /* __cplusplus */

+

+#endif /* STM32H757xx_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7a3xx.h b/bsps/arm/stm32h7/include/stm32h7a3xx.h
new file mode 100644
index 0000000000..b5d73eb8e4
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7a3xx.h
@@ -0,0 +1,22404 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7a3xx.h

+  * @author  MCD Application Team

+  * @brief   CMSIS STM32H7A3xx Device Peripheral Access Layer Header File.

+  *

+  *          This file contains:

+  *           - Data structures and the address mapping for all peripherals

+  *           - Peripheral's registers declarations and bits definition

+  *           - Macros to access peripheral's registers hardware

+  *

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/** @addtogroup CMSIS_Device

+  * @{

+  */

+

+/** @addtogroup stm32h7a3xx

+  * @{

+  */

+

+#ifndef STM32H7A3xx_H

+#define STM32H7A3xx_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif /* __cplusplus */

+

+/** @addtogroup Peripheral_interrupt_number_definition

+  * @{

+  */

+

+/**

+ * @brief STM32H7XX Interrupt Number Definition, according to the selected device

+ *        in @ref Library_configuration_section

+ */

+typedef enum

+{

+/******  Cortex-M Processor Exceptions Numbers *****************************************************************/

+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */

+  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */

+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */

+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */

+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */

+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M SV Call Interrupt                                     */

+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M Debug Monitor Interrupt                               */

+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M Pend SV Interrupt                                     */

+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M System Tick Interrupt                                 */

+/******  STM32 specific Interrupt Numbers **********************************************************************/

+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)                   */

+  PVD_PVM_IRQn                = 1,      /*!< PVD/PVM through EXTI Line detection Interrupt                     */

+  RTC_TAMP_STAMP_CSS_LSE_IRQn = 2,      /*!< Tamper, TimeStamp, CSS and LSE interrupts through the EXTI line   */

+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */

+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */

+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */

+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */

+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */

+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */

+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */

+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */

+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */

+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */

+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */

+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */

+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */

+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */

+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */

+  ADC_IRQn                    = 18,     /*!< ADC1 and  ADC2 global Interrupts                                  */

+  FDCAN1_IT0_IRQn             = 19,     /*!< FDCAN1 Interrupt line 0                                           */

+  FDCAN2_IT0_IRQn             = 20,     /*!< FDCAN2 Interrupt line 0                                           */

+  FDCAN1_IT1_IRQn             = 21,     /*!< FDCAN1 Interrupt line 1                                           */

+  FDCAN2_IT1_IRQn             = 22,     /*!< FDCAN2 Interrupt line 1                                           */

+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */

+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                              */

+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                             */

+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt                            */

+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */

+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */

+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */

+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */

+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */

+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */

+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */

+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */

+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */

+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */

+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */

+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */

+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */

+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */

+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */

+  DFSDM2_IRQn                 = 42,     /*!< DFSDM2 global Interrupt                                           */

+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */

+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */

+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */

+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */

+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */

+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */

+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */

+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */

+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */

+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */

+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */

+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */

+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */

+  DMA2_Stream0_IRQn           = 56,     /*!<   DMA2 Stream 0 global Interrupt                                  */

+  DMA2_Stream1_IRQn           = 57,     /*!<   DMA2 Stream 1 global Interrupt                                  */

+  DMA2_Stream2_IRQn           = 58,     /*!<   DMA2 Stream 2 global Interrupt                                  */

+  DMA2_Stream3_IRQn           = 59,     /*!<   DMA2 Stream 3 global Interrupt                                  */

+  DMA2_Stream4_IRQn           = 60,     /*!<   DMA2 Stream 4 global Interrupt                                  */

+  FDCAN_CAL_IRQn              = 63,     /*!< FDCAN Calibration unit Interrupt                                  */

+  DFSDM1_FLT4_IRQn            = 64,     /*!< DFSDM Filter4 Interrupt                                           */

+  DFSDM1_FLT5_IRQn            = 65,     /*!< DFSDM Filter5 Interrupt                                           */

+  DFSDM1_FLT6_IRQn            = 66,     /*!< DFSDM Filter6 Interrupt                                           */

+  DFSDM1_FLT7_IRQn            = 67,     /*!< DFSDM Filter7 Interrupt                                           */

+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */

+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */

+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */

+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */

+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */

+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */

+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */

+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */

+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */

+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */

+  DCMI_PSSI_IRQn              = 78,     /*!< DCMI and PSSI global interrupt                                    */

+  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */

+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */

+  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */

+  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */

+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */

+  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */

+  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */

+  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */

+  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */

+  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */

+  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */

+  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */

+  OCTOSPI1_IRQn               = 92,     /*!< OCTOSPI1 global interrupt                                         */

+  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */

+  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */

+  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */

+  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */

+  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */

+  DMAMUX1_OVR_IRQn            = 102,    /*!<DMAMUX1 Overrun interrupt                                          */

+  DFSDM1_FLT0_IRQn            = 110,    /*!<DFSDM Filter1 Interrupt                                            */

+  DFSDM1_FLT1_IRQn            = 111,    /*!<DFSDM Filter2 Interrupt                                            */

+  DFSDM1_FLT2_IRQn            = 112,    /*!<DFSDM Filter3 Interrupt                                            */

+  DFSDM1_FLT3_IRQn            = 113,    /*!<DFSDM Filter4 Interrupt                                            */

+  SWPMI1_IRQn                 = 115,    /*!< Serial Wire Interface 1 global interrupt                          */

+  TIM15_IRQn                  = 116,    /*!< TIM15 global Interrupt                                            */

+  TIM16_IRQn                  = 117,    /*!< TIM16 global Interrupt                                            */

+  TIM17_IRQn                  = 118,    /*!< TIM17 global Interrupt                                            */

+  MDIOS_WKUP_IRQn             = 119,    /*!< MDIOS Wakeup  Interrupt                                           */

+  MDIOS_IRQn                  = 120,    /*!< MDIOS global Interrupt                                            */

+  JPEG_IRQn                   = 121,    /*!< JPEG global Interrupt                                             */

+  MDMA_IRQn                   = 122,    /*!< MDMA global Interrupt                                             */

+  SDMMC2_IRQn                 = 124,    /*!< SDMMC2 global Interrupt                                           */

+  HSEM1_IRQn                  = 125,    /*!< HSEM1 global Interrupt                                            */

+  DAC2_IRQn                   = 127,    /*!< DAC2 global Interrupt                                             */

+  DMAMUX2_OVR_IRQn            = 128,    /*!<DMAMUX2 Overrun interrupt                                          */

+  BDMA2_Channel0_IRQn         = 129,    /*!< BDMA2 Channel 0 global Interrupt                                  */

+  BDMA2_Channel1_IRQn         = 130,    /*!< BDMA2 Channel 1 global Interrupt                                  */

+  BDMA2_Channel2_IRQn         = 131,    /*!< BDMA2 Channel 2 global Interrupt                                  */

+  BDMA2_Channel3_IRQn         = 132,    /*!< BDMA2 Channel 3 global Interrupt                                  */

+  BDMA2_Channel4_IRQn         = 133,    /*!< BDMA2 Channel 4 global Interrupt                                  */

+  BDMA2_Channel5_IRQn         = 134,    /*!< BDMA2 Channel 5 global Interrupt                                  */

+  BDMA2_Channel6_IRQn         = 135,    /*!< BDMA2 Channel 6 global Interrupt                                  */

+  BDMA2_Channel7_IRQn         = 136,    /*!< BDMA2 Channel 7 global Interrupt                                  */

+  COMP_IRQn                   = 137 ,   /*!< COMP global Interrupt                                             */

+  LPTIM2_IRQn                 = 138,    /*!< LP TIM2 global interrupt                                          */

+  LPTIM3_IRQn                 = 139,    /*!< LP TIM3 global interrupt                                          */

+  UART9_IRQn                  = 140,    /*!< UART9 global interrupt                                            */

+  USART10_IRQn                = 141,    /*!< USART10 global interrupt                                          */

+  LPUART1_IRQn                = 142,    /*!< LP UART1 interrupt                                                */

+  WWDG_RST_IRQn               = 143,    /*!<Window Watchdog Event interrupt                                    */

+  CRS_IRQn                    = 144,    /*!< Clock Recovery Global Interrupt                                   */

+  ECC_IRQn                    = 145,    /*!< ECC diagnostic Global Interrupt                                   */

+  DTS_IRQn                    = 147,    /*!< Digital Temperature Sensor Global Interrupt                       */

+  WAKEUP_PIN_IRQn             = 149,    /*!< Interrupt for all 6 wake-up pins                                  */

+  OCTOSPI2_IRQn               = 150,    /*!< OctoSPI2 global interrupt                                         */

+  GFXMMU_IRQn                 = 153,    /*!< GFXMMU global interrupt                                           */

+  BDMA1_IRQn                  = 154,    /*!< BDMA1 for DFSM global interrupt                                   */

+} IRQn_Type;

+

+/**

+  * @}

+  */

+

+/** @addtogroup Configuration_section_for_CMSIS

+  * @{

+  */

+

+

+

+

+/**

+  * @brief Configuration of the Cortex-M7 Processor and Core Peripherals

+   */

+#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */

+#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */

+#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */

+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */

+#define __FPU_PRESENT             1       /*!< FPU present                                   */

+#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */

+#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */

+#include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */

+

+/**

+  * @}

+  */

+

+

+

+

+#include "system_stm32h7xx.h"

+#include <stdint.h>

+

+/** @addtogroup Peripheral_registers_structures

+  * @{

+  */

+

+/**

+  * @brief Analog to Digital Converter

+  */

+

+typedef struct

+{

+  __IO uint32_t ISR;              /*!< ADC Interrupt and Status Register,                          Address offset: 0x00 */

+  __IO uint32_t IER;              /*!< ADC Interrupt Enable Register,                              Address offset: 0x04 */

+  __IO uint32_t CR;               /*!< ADC control register,                                       Address offset: 0x08 */

+  __IO uint32_t CFGR;             /*!< ADC Configuration register,                                 Address offset: 0x0C */

+  __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                               Address offset: 0x10 */

+  __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                                 Address offset: 0x14 */

+  __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                                 Address offset: 0x18 */

+  __IO uint32_t PCSEL;            /*!< ADC pre-channel selection,                                  Address offset: 0x1C */

+  __IO uint32_t LTR1;             /*!< ADC watchdog Lower threshold register 1,                    Address offset: 0x20 */

+  __IO uint32_t HTR1;             /*!< ADC watchdog higher threshold register 1,                   Address offset: 0x24 */

+  uint32_t      RESERVED1;        /*!< Reserved, 0x028                                                                  */

+  uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                                  */

+  __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                            Address offset: 0x30 */

+  __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                            Address offset: 0x34 */

+  __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                            Address offset: 0x38 */

+  __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                            Address offset: 0x3C */

+  __IO uint32_t DR;               /*!< ADC regular data register,                                  Address offset: 0x40 */

+  uint32_t      RESERVED3;        /*!< Reserved, 0x044                                                                  */

+  uint32_t      RESERVED4;        /*!< Reserved, 0x048                                                                  */

+  __IO uint32_t JSQR;             /*!< ADC injected sequence register,                             Address offset: 0x4C */

+  uint32_t      RESERVED5[4];     /*!< Reserved, 0x050 - 0x05C                                                          */

+  __IO uint32_t OFR1;             /*!< ADC offset register 1,                                      Address offset: 0x60 */

+  __IO uint32_t OFR2;             /*!< ADC offset register 2,                                      Address offset: 0x64 */

+  __IO uint32_t OFR3;             /*!< ADC offset register 3,                                      Address offset: 0x68 */

+  __IO uint32_t OFR4;             /*!< ADC offset register 4,                                      Address offset: 0x6C */

+  uint32_t      RESERVED6[4];     /*!< Reserved, 0x070 - 0x07C                                                          */

+  __IO uint32_t JDR1;             /*!< ADC injected data register 1,                               Address offset: 0x80 */

+  __IO uint32_t JDR2;             /*!< ADC injected data register 2,                               Address offset: 0x84 */

+  __IO uint32_t JDR3;             /*!< ADC injected data register 3,                               Address offset: 0x88 */

+  __IO uint32_t JDR4;             /*!< ADC injected data register 4,                               Address offset: 0x8C */

+  uint32_t      RESERVED7[4];     /*!< Reserved, 0x090 - 0x09C                                                          */

+  __IO uint32_t AWD2CR;           /*!< ADC  Analog Watchdog 2 Configuration Register,              Address offset: 0xA0 */

+  __IO uint32_t AWD3CR;           /*!< ADC  Analog Watchdog 3 Configuration Register,              Address offset: 0xA4 */

+  uint32_t      RESERVED8;        /*!< Reserved, 0x0A8                                                                  */

+  uint32_t      RESERVED9;        /*!< Reserved, 0x0AC                                                                  */

+  __IO uint32_t LTR2;             /*!< ADC watchdog Lower threshold register 2,                    Address offset: 0xB0 */

+  __IO uint32_t HTR2;             /*!< ADC watchdog Higher threshold register 2,                   Address offset: 0xB4 */

+  __IO uint32_t LTR3;             /*!< ADC watchdog Lower threshold register 3,                    Address offset: 0xB8 */

+  __IO uint32_t HTR3;             /*!< ADC watchdog Higher threshold register 3,                   Address offset: 0xBC */

+  __IO uint32_t DIFSEL;           /*!< ADC  Differential Mode Selection Register,                  Address offset: 0xC0 */

+  __IO uint32_t CALFACT;          /*!< ADC  Calibration Factors,                                   Address offset: 0xC4 */

+  __IO uint32_t CALFACT2;         /*!< ADC  Linearity Calibration Factors,                         Address offset: 0xC8 */

+} ADC_TypeDef;

+

+

+typedef struct

+{

+__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */

+uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */

+__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */

+__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */

+__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */

+

+} ADC_Common_TypeDef;

+

+

+/**

+  * @brief VREFBUF

+  */

+

+typedef struct

+{

+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */

+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */

+} VREFBUF_TypeDef;

+

+

+/**

+  * @brief FD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */

+  __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */

+  __IO uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */

+  __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */

+  __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */

+  __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */

+  __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */

+  __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */

+  __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */

+  __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */

+  __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */

+  __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */

+  __IO uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */

+  __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */

+  __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */

+  __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */

+  __IO uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */

+  __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */

+  __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */

+  __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */

+  __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */

+  __IO uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */

+  __IO uint32_t GFC;          /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */

+  __IO uint32_t SIDFC;        /*!< FDCAN Standard ID Filter Configuration register,                 Address offset: 0x084 */

+  __IO uint32_t XIDFC;        /*!< FDCAN Extended ID Filter Configuration register,                 Address offset: 0x088 */

+  __IO uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */

+  __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x090 */

+  __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x094 */

+  __IO uint32_t NDAT1;        /*!< FDCAN New Data 1 register,                                       Address offset: 0x098 */

+  __IO uint32_t NDAT2;        /*!< FDCAN New Data 2 register,                                       Address offset: 0x09C */

+  __IO uint32_t RXF0C;        /*!< FDCAN Rx FIFO 0 Configuration register,                          Address offset: 0x0A0 */

+  __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x0A4 */

+  __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x0A8 */

+  __IO uint32_t RXBC;         /*!< FDCAN Rx Buffer Configuration register,                          Address offset: 0x0AC */

+  __IO uint32_t RXF1C;        /*!< FDCAN Rx FIFO 1 Configuration register,                          Address offset: 0x0B0 */

+  __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x0B4 */

+  __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x0B8 */

+  __IO uint32_t RXESC;        /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register,        Address offset: 0x0BC */

+  __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */

+  __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */

+  __IO uint32_t TXESC;        /*!< FDCAN Tx Buffer Element Size Configuration register,             Address offset: 0x0C8 */

+  __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0CC */

+  __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0D0 */

+  __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D4 */

+  __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D8 */

+  __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0DC */

+  __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0E0 */

+  __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */

+  __IO uint32_t RESERVED6[2]; /*!< Reserved,                                                                0x0E8 - 0x0EC */

+  __IO uint32_t TXEFC;        /*!< FDCAN Tx Event FIFO Configuration register,                      Address offset: 0x0F0 */

+  __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0F4 */

+  __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0F8 */

+  __IO uint32_t RESERVED7;    /*!< Reserved,                                                                        0x0FC */

+} FDCAN_GlobalTypeDef;

+

+/**

+  * @brief TTFD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t TTTMC;          /*!< TT Trigger Memory Configuration register,    Address offset: 0x100 */

+  __IO uint32_t TTRMC;          /*!< TT Reference Message Configuration register, Address offset: 0x104 */

+  __IO uint32_t TTOCF;          /*!< TT Operation Configuration register,         Address offset: 0x108 */

+  __IO uint32_t TTMLM;          /*!< TT Matrix Limits register,                   Address offset: 0x10C */

+  __IO uint32_t TURCF;          /*!< TUR Configuration register,                  Address offset: 0x110 */

+  __IO uint32_t TTOCN;          /*!< TT Operation Control register,               Address offset: 0x114 */

+  __IO uint32_t TTGTP;          /*!< TT Global Time Preset register,              Address offset: 0x118 */

+  __IO uint32_t TTTMK;          /*!< TT Time Mark register,                       Address offset: 0x11C */

+  __IO uint32_t TTIR;           /*!< TT Interrupt register,                       Address offset: 0x120 */

+  __IO uint32_t TTIE;           /*!< TT Interrupt Enable register,                Address offset: 0x124 */

+  __IO uint32_t TTILS;          /*!< TT Interrupt Line Select register,           Address offset: 0x128 */

+  __IO uint32_t TTOST;          /*!< TT Operation Status register,                Address offset: 0x12C */

+  __IO uint32_t TURNA;          /*!< TT TUR Numerator Actual register,            Address offset: 0x130 */

+  __IO uint32_t TTLGT;          /*!< TT Local and Global Time register,           Address offset: 0x134 */

+  __IO uint32_t TTCTC;          /*!< TT Cycle Time and Count register,            Address offset: 0x138 */

+  __IO uint32_t TTCPT;          /*!< TT Capture Time register,                    Address offset: 0x13C */

+  __IO uint32_t TTCSM;          /*!< TT Cycle Sync Mark register,                 Address offset: 0x140 */

+  __IO uint32_t RESERVED1[111]; /*!< Reserved,                                            0x144 - 0x2FC */

+  __IO uint32_t TTTS;           /*!< TT Trigger Select register,                  Address offset: 0x300 */

+} TTCAN_TypeDef;

+

+/**

+  * @brief FD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t CREL;  /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */

+  __IO uint32_t CCFG;  /*!< Calibration Configuration register,           Address offset: 0x04 */

+  __IO uint32_t CSTAT; /*!< Calibration Status register,                  Address offset: 0x08 */

+  __IO uint32_t CWD;   /*!< Calibration Watchdog register,                Address offset: 0x0C */

+  __IO uint32_t IR;    /*!< CCU Interrupt register,                       Address offset: 0x10 */

+  __IO uint32_t IE;    /*!< CCU Interrupt Enable register,                Address offset: 0x14 */

+} FDCAN_ClockCalibrationUnit_TypeDef;

+

+

+/**

+  * @brief Consumer Electronics Control

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;           /*!< CEC control register,              Address offset:0x00 */

+  __IO uint32_t CFGR;         /*!< CEC configuration register,        Address offset:0x04 */

+  __IO uint32_t TXDR;         /*!< CEC Tx data register ,             Address offset:0x08 */

+  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,              Address offset:0x0C */

+  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register, Address offset:0x10 */

+  __IO uint32_t IER;          /*!< CEC interrupt enable register,     Address offset:0x14 */

+}CEC_TypeDef;

+

+/**

+  * @brief CRC calculation unit

+  */

+

+typedef struct

+{

+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */

+  __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */

+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */

+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */

+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */

+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */

+} CRC_TypeDef;

+

+

+/**

+  * @brief Clock Recovery System

+  */

+typedef struct

+{

+__IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */

+__IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */

+__IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */

+__IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */

+} CRS_TypeDef;

+

+

+/**

+  * @brief Digital to Analog Converter

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */

+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */

+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */

+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */

+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */

+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */

+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */

+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */

+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */

+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */

+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */

+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */

+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */

+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */

+  __IO uint32_t CCR;      /*!< DAC calibration control register,                        Address offset: 0x38 */

+  __IO uint32_t MCR;      /*!< DAC mode control register,                               Address offset: 0x3C */

+  __IO uint32_t SHSR1;    /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */

+  __IO uint32_t SHSR2;    /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */

+  __IO uint32_t SHHR;     /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */

+  __IO uint32_t SHRR;     /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */

+} DAC_TypeDef;

+

+/**

+  * @brief DFSDM module registers

+  */

+typedef struct

+{

+  __IO uint32_t FLTCR1;          /*!< DFSDM control register1,                          Address offset: 0x100 */

+  __IO uint32_t FLTCR2;          /*!< DFSDM control register2,                          Address offset: 0x104 */

+  __IO uint32_t FLTISR;          /*!< DFSDM interrupt and status register,              Address offset: 0x108 */

+  __IO uint32_t FLTICR;          /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */

+  __IO uint32_t FLTJCHGR;        /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */

+  __IO uint32_t FLTFCR;          /*!< DFSDM filter control register,                    Address offset: 0x114 */

+  __IO uint32_t FLTJDATAR;       /*!< DFSDM data register for injected group,           Address offset: 0x118 */

+  __IO uint32_t FLTRDATAR;       /*!< DFSDM data register for regular group,            Address offset: 0x11C */

+  __IO uint32_t FLTAWHTR;        /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */

+  __IO uint32_t FLTAWLTR;        /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */

+  __IO uint32_t FLTAWSR;         /*!< DFSDM analog watchdog status register             Address offset: 0x128 */

+  __IO uint32_t FLTAWCFR;        /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */

+  __IO uint32_t FLTEXMAX;        /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */

+  __IO uint32_t FLTEXMIN;        /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */

+  __IO uint32_t FLTCNVTIMR;      /*!< DFSDM conversion timer,                           Address offset: 0x138 */

+} DFSDM_Filter_TypeDef;

+

+/**

+  * @brief DFSDM channel configuration registers

+  */

+typedef struct

+{

+  __IO uint32_t CHCFGR1;      /*!< DFSDM channel configuration register1,            Address offset: 0x00 */

+  __IO uint32_t CHCFGR2;      /*!< DFSDM channel configuration register2,            Address offset: 0x04 */

+  __IO uint32_t CHAWSCDR;     /*!< DFSDM channel analog watchdog and

+                                   short circuit detector register,                  Address offset: 0x08 */

+  __IO uint32_t CHWDATAR;     /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */

+  __IO uint32_t CHDATINR;     /*!< DFSDM channel data input register,                Address offset: 0x10 */

+  __IO uint32_t CHDLYR;       /*!< DFSDM channel delay register,                     Address offset: 0x14 */

+} DFSDM_Channel_TypeDef;

+

+/**

+  * @brief Debug MCU

+  */

+typedef struct

+{

+  __IO uint32_t IDCODE;        /*!< MCU device ID code,                     Address offset: 0x00 */

+  __IO uint32_t CR;            /*!< Debug MCU configuration register,       Address offset: 0x04 */

+  uint32_t RESERVED4[11];      /*!< Reserved,                             Address offset: 0x08 */

+  __IO uint32_t APB3FZ1;     /*!< Debug MCU APB3FZ1 freeze register,    Address offset: 0x34 */

+  uint32_t RESERVED5;          /*!< Reserved,                             Address offset: 0x38 */

+  __IO uint32_t APB1LFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x3C */

+  uint32_t RESERVED6;          /*!< Reserved,                             Address offset: 0x40 */

+  __IO uint32_t APB1HFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x44 */

+  uint32_t RESERVED7;          /*!< Reserved,                             Address offset: 0x48 */

+  __IO uint32_t APB2FZ1;     /*!< Debug MCU APB2FZ1 freeze register,    Address offset: 0x4C */

+  uint32_t RESERVED8;          /*!< Reserved,                             Address offset: 0x50 */

+  __IO uint32_t APB4FZ1;     /*!< Debug MCU APB4FZ1 freeze register,    Address offset: 0x54 */

+}DBGMCU_TypeDef;

+/**

+  * @brief DCMI

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */

+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */

+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */

+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */

+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */

+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */

+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */

+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */

+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */

+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */

+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */

+} DCMI_TypeDef;

+

+/**

+  * @brief PSSI

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;             /*!< PSSI control register 1,               Address offset: 0x000 */

+  __IO uint32_t SR;             /*!< PSSI status register,                  Address offset: 0x004 */

+  __IO uint32_t RIS;            /*!< PSSI raw interrupt status register,    Address offset: 0x008 */

+  __IO uint32_t IER;            /*!< PSSI interrupt enable register,        Address offset: 0x00C */

+  __IO uint32_t MIS;            /*!< PSSI masked interrupt status register, Address offset: 0x010 */

+  __IO uint32_t ICR;            /*!< PSSI interrupt clear register,         Address offset: 0x014 */

+  __IO uint32_t RESERVED1[4];   /*!< Reserved,                                      0x018 - 0x024 */

+  __IO uint32_t DR;             /*!< PSSI data register,                    Address offset: 0x028 */

+  __IO uint32_t RESERVED2[241]; /*!< Reserved,                                      0x02C - 0x3EC */

+  __IO uint32_t HWCFGR;         /*!< PSSI IP HW configuration register,     Address offset: 0x3F0 */

+  __IO uint32_t VERR;           /*!< PSSI IP version register,              Address offset: 0x3F4 */

+  __IO uint32_t IPIDR;          /*!< PSSI IP ID register,                   Address offset: 0x3F8 */

+  __IO uint32_t SIDR;           /*!< PSSI SIZE ID register,                 Address offset: 0x3FC */

+} PSSI_TypeDef;

+

+/**

+  * @brief DMA Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */

+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */

+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */

+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */

+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */

+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */

+} DMA_Stream_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */

+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */

+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */

+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */

+} DMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CCR;          /*!< DMA channel x configuration register          */

+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register         */

+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register     */

+  __IO uint32_t CM0AR;        /*!< DMA channel x memory 0 address register       */

+  __IO uint32_t CM1AR;        /*!< DMA channel x memory 1 address register       */

+} BDMA_Channel_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */

+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */

+} BDMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CCR;        /*!< DMA Multiplexer Channel x Control Register   */

+}DMAMUX_Channel_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CSR;      /*!< DMA Channel Status Register     */

+  __IO uint32_t  CFR;      /*!< DMA Channel Clear Flag Register */

+}DMAMUX_ChannelStatus_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  RGCR;        /*!< DMA Request Generator x Control Register   */

+}DMAMUX_RequestGen_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  RGSR;        /*!< DMA Request Generator Status Register       */

+  __IO uint32_t  RGCFR;       /*!< DMA Request Generator Clear Flag Register   */

+}DMAMUX_RequestGenStatus_TypeDef;

+

+/**

+  * @brief MDMA Controller

+  */

+typedef struct

+{

+  __IO uint32_t  GISR0;   /*!< MDMA Global Interrupt/Status Register 0,          Address offset: 0x00 */

+}MDMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CISR;      /*!< MDMA channel x interrupt/status register,             Address offset: 0x40 */

+  __IO uint32_t  CIFCR;     /*!< MDMA channel x interrupt flag clear register,         Address offset: 0x44 */

+  __IO uint32_t  CESR;      /*!< MDMA Channel x error status register,                 Address offset: 0x48 */

+  __IO uint32_t  CCR;       /*!< MDMA channel x control register,                      Address offset: 0x4C */

+  __IO uint32_t  CTCR;      /*!< MDMA channel x Transfer Configuration register,       Address offset: 0x50 */

+  __IO uint32_t  CBNDTR;    /*!< MDMA Channel x block number of data register,         Address offset: 0x54 */

+  __IO uint32_t  CSAR;      /*!< MDMA channel x source address register,               Address offset: 0x58 */

+  __IO uint32_t  CDAR;      /*!< MDMA channel x destination address register,          Address offset: 0x5C */

+  __IO uint32_t  CBRUR;     /*!< MDMA channel x Block Repeat address Update register,  Address offset: 0x60 */

+  __IO uint32_t  CLAR;      /*!< MDMA channel x Link Address register,                 Address offset: 0x64 */

+  __IO uint32_t  CTBR;      /*!< MDMA channel x Trigger and Bus selection Register,    Address offset: 0x68 */

+  uint32_t       RESERVED0; /*!< Reserved, 0x68                                                             */

+  __IO uint32_t  CMAR;      /*!< MDMA channel x Mask address register,                 Address offset: 0x70 */

+  __IO uint32_t  CMDR;      /*!< MDMA channel x Mask Data register,                    Address offset: 0x74 */

+}MDMA_Channel_TypeDef;

+

+/**

+  * @brief DMA2D Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */

+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */

+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */

+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */

+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */

+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */

+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */

+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */

+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */

+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */

+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */

+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */

+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */

+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */

+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */

+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */

+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */

+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */

+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */

+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */

+  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */

+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */

+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */

+} DMA2D_TypeDef;

+

+

+/**

+  * @brief External Interrupt/Event Controller

+  */

+

+typedef struct

+{

+__IO uint32_t RTSR1;               /*!< EXTI Rising trigger selection register,          Address offset: 0x00 */

+__IO uint32_t FTSR1;               /*!< EXTI Falling trigger selection register,         Address offset: 0x04 */

+__IO uint32_t SWIER1;              /*!< EXTI Software interrupt event register,          Address offset: 0x08 */

+__IO uint32_t D3PMR1;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */

+__IO uint32_t D3PCR1L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L)     Address offset: 0x10 */

+__IO uint32_t D3PCR1H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H)   Address offset: 0x14 */

+uint32_t      RESERVED1[2];        /*!< Reserved,                                        0x18 to 0x1C         */

+__IO uint32_t RTSR2;               /*!< EXTI Rising trigger selection register,          Address offset: 0x20 */

+__IO uint32_t FTSR2;               /*!< EXTI Falling trigger selection register,         Address offset: 0x24 */

+__IO uint32_t SWIER2;              /*!< EXTI Software interrupt event register,          Address offset: 0x28 */

+__IO uint32_t D3PMR2;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */

+__IO uint32_t D3PCR2L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L)  Address offset: 0x30 */

+__IO uint32_t D3PCR2H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */

+uint32_t      RESERVED2[2];        /*!< Reserved,                                        0x38 to 0x3C         */

+__IO uint32_t RTSR3;               /*!< EXTI Rising trigger selection register,          Address offset: 0x40 */

+__IO uint32_t FTSR3;               /*!< EXTI Falling trigger selection register,         Address offset: 0x44 */

+__IO uint32_t SWIER3;              /*!< EXTI Software interrupt event register,          Address offset: 0x48 */

+__IO uint32_t D3PMR3;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */

+__IO uint32_t D3PCR3L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */

+__IO uint32_t D3PCR3H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */

+uint32_t      RESERVED3[10];       /*!< Reserved,                                        0x58 to 0x7C         */

+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                    Address offset: 0x80 */

+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                        Address offset: 0x84 */

+__IO uint32_t PR1;                 /*!< EXTI Pending register,                           Address offset: 0x88 */

+uint32_t      RESERVED4;           /*!< Reserved,                                        0x8C                 */

+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                    Address offset: 0x90 */

+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                        Address offset: 0x94 */

+__IO uint32_t PR2;                 /*!< EXTI Pending register,                           Address offset: 0x98 */

+uint32_t      RESERVED5;           /*!< Reserved,                                        0x9C                 */

+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                    Address offset: 0xA0 */

+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                        Address offset: 0xA4 */

+__IO uint32_t PR3;                 /*!< EXTI Pending register,                           Address offset: 0xA8 */

+}EXTI_TypeDef;

+

+typedef struct

+{

+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                Address offset: 0x00 */

+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                    Address offset: 0x04 */

+__IO uint32_t PR1;                 /*!< EXTI Pending register,                       Address offset: 0x08 */

+uint32_t      RESERVED1;           /*!< Reserved, 0x0C                                                    */

+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                Address offset: 0x10 */

+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                    Address offset: 0x14 */

+__IO uint32_t PR2;                 /*!< EXTI Pending register,                       Address offset: 0x18 */

+uint32_t      RESERVED2;           /*!< Reserved, 0x1C                                                    */

+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                Address offset: 0x20 */

+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                    Address offset: 0x24 */

+__IO uint32_t PR3;                 /*!< EXTI Pending register,                       Address offset: 0x28 */

+}EXTI_Core_TypeDef;

+

+

+/**

+  * @brief FLASH Registers

+  */

+

+typedef struct

+{

+  __IO uint32_t ACR;             /*!< FLASH access control register,                            Address offset: 0x00  */

+  __IO uint32_t KEYR1;           /*!< Flash Key Register for bank1,                             Address offset: 0x04  */

+  __IO uint32_t OPTKEYR;         /*!< Flash Option Key Register,                                Address offset: 0x08  */

+  __IO uint32_t CR1;             /*!< Flash Control Register for bank1,                         Address offset: 0x0C  */

+  __IO uint32_t SR1;             /*!< Flash Status Register for bank1,                          Address offset: 0x10  */

+  __IO uint32_t CCR1;            /*!< Flash Control Register for bank1,                         Address offset: 0x14  */

+  __IO uint32_t OPTCR;           /*!< Flash Option Control Register,                            Address offset: 0x18  */

+  __IO uint32_t OPTSR_CUR;       /*!< Flash Option Status Current Register,                     Address offset: 0x1C  */

+  __IO uint32_t OPTSR_PRG;       /*!< Flash Option Status to Program Register,                  Address offset: 0x20  */

+  __IO uint32_t OPTCCR;          /*!< Flash Option Clear Control Register,                      Address offset: 0x24  */

+  __IO uint32_t PRAR_CUR1;       /*!< Flash Current Protection Address Register for bank1,      Address offset: 0x28  */

+  __IO uint32_t PRAR_PRG1;       /*!< Flash Protection Address to Program Register for bank1,   Address offset: 0x2C  */

+  __IO uint32_t SCAR_CUR1;       /*!< Flash Current Secure Address Register for bank1,          Address offset: 0x30  */

+  __IO uint32_t SCAR_PRG1;       /*!< Flash Secure Address to Program Register for bank1,       Address offset: 0x34  */

+  __IO uint32_t WPSN_CUR1;       /*!< Flash Current Write Protection Register on bank1,         Address offset: 0x38  */

+  __IO uint32_t WPSN_PRG1;       /*!< Flash Write Protection to Program Register on bank1,      Address offset: 0x3C  */

+  __IO uint32_t BOOT_CUR;        /*!< Flash Current Boot Address for Pelican Core Register,     Address offset: 0x40  */

+  __IO uint32_t BOOT_PRG;        /*!< Flash Boot Address to Program for Pelican Core Register,  Address offset: 0x44  */

+  uint32_t      RESERVED0[2];    /*!< Reserved, 0x48 to 0x4C                                                          */

+  __IO uint32_t CRCCR1;          /*!< Flash CRC Control register For Bank1 Register ,           Address offset: 0x50  */

+  __IO uint32_t CRCSADD1;        /*!< Flash CRC Start Address Register for Bank1 ,              Address offset: 0x54  */

+  __IO uint32_t CRCEADD1;        /*!< Flash CRC End Address Register for Bank1 ,                Address offset: 0x58  */

+  __IO uint32_t CRCDATA;         /*!< Flash CRC Data Register for Bank1 ,                       Address offset: 0x5C  */

+  __IO uint32_t ECC_FA1;         /*!< Flash ECC Fail Address For Bank1 Register ,               Address offset: 0x60  */

+  uint32_t      RESERVED;        /*!< Reserved, 0x64                                                                  */

+  __IO uint32_t OTPBL_CUR;       /*!< Flash Current OTP Block Lock Register,                    Address offset: 0x68  */

+  __IO uint32_t OTPBL_PRG;       /*!< Flash OTP Block Lock to Program Register,                 Address offset: 0x6C  */

+  uint32_t      RESERVED1[37];   /*!< Reserved, 0x70 to 0x100                                                         */

+  __IO uint32_t KEYR2;           /*!< Flash Key Register for bank2,                             Address offset: 0x104 */

+  uint32_t      RESERVED2;       /*!< Reserved, 0x108                                                                 */

+  __IO uint32_t CR2;             /*!< Flash Control Register for bank2,                         Address offset: 0x10C */

+  __IO uint32_t SR2;             /*!< Flash Status Register for bank2,                          Address offset: 0x110 */

+  __IO uint32_t CCR2;            /*!< Flash Status Register for bank2,                          Address offset: 0x114 */

+  uint32_t      RESERVED3[4];    /*!< Reserved, 0x118 to 0x124                                                        */

+  __IO uint32_t PRAR_CUR2;       /*!< Flash Current Protection Address Register for bank2,      Address offset: 0x128 */

+  __IO uint32_t PRAR_PRG2;       /*!< Flash Protection Address to Program Register for bank2,   Address offset: 0x12C */

+  __IO uint32_t SCAR_CUR2;       /*!< Flash Current Secure Address Register for bank2,          Address offset: 0x130 */

+  __IO uint32_t SCAR_PRG2;       /*!< Flash Secure Address Register for bank2,                  Address offset: 0x134 */

+  __IO uint32_t WPSN_CUR2;       /*!< Flash Current Write Protection Register on bank2,         Address offset: 0x138 */

+  __IO uint32_t WPSN_PRG2;       /*!< Flash Write Protection to Program Register on bank2,      Address offset: 0x13C */

+  uint32_t      RESERVED4[4];    /*!< Reserved, 0x140 to 0x14C                                                        */

+  __IO uint32_t CRCCR2;          /*!< Flash CRC Control register For Bank2 Register ,           Address offset: 0x150 */

+  __IO uint32_t CRCSADD2;        /*!< Flash CRC Start Address Register for Bank2 ,              Address offset: 0x154 */

+  __IO uint32_t CRCEADD2;        /*!< Flash CRC End Address Register for Bank2 ,                Address offset: 0x158 */

+  __IO uint32_t CRCDATA2;        /*!< Flash CRC Data Register for Bank2 ,                       Address offset: 0x15C */

+  __IO uint32_t ECC_FA2;         /*!< Flash ECC Fail Address For Bank2 Register ,               Address offset: 0x160 */

+} FLASH_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */

+} FMC_Bank1_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank1E

+  */

+

+typedef struct

+{

+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */

+} FMC_Bank1E_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank2

+  */

+

+typedef struct

+{

+  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */

+  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */

+  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */

+  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */

+  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */

+  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */

+} FMC_Bank2_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank3

+  */

+

+typedef struct

+{

+  __IO uint32_t PCR;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */

+  __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */

+  __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */

+  __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */

+  uint32_t      RESERVED;  /*!< Reserved, 0x90                                                            */

+  __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */

+} FMC_Bank3_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank5 and 6

+  */

+

+

+typedef struct

+{

+  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */

+  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */

+  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */

+  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */

+  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */

+} FMC_Bank5_6_TypeDef;

+

+/**

+  * @brief GFXMMU registers

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;              /*!< GFXMMU configuration register,                     Address offset: 0x00 */

+  __IO uint32_t SR;              /*!< GFXMMU status register,                            Address offset: 0x04 */

+  __IO uint32_t FCR;             /*!< GFXMMU flag clear register,                        Address offset: 0x08 */

+  __IO uint32_t CCR;             /*!< GFXMMU Cache Control Register,                     Address offset: 0x0C */

+  __IO uint32_t DVR;             /*!< GFXMMU default value register,                     Address offset: 0x10 */

+       uint32_t RESERVED1[3];    /*!< Reserved1,                                         Address offset: 0x14 to 0x1C */

+  __IO uint32_t B0CR;            /*!< GFXMMU buffer 0 configuration register,            Address offset: 0x20 */

+  __IO uint32_t B1CR;            /*!< GFXMMU buffer 1 configuration register,            Address offset: 0x24 */

+  __IO uint32_t B2CR;            /*!< GFXMMU buffer 2 configuration register,            Address offset: 0x28 */

+  __IO uint32_t B3CR;            /*!< GFXMMU buffer 3 configuration register,            Address offset: 0x2C */

+       uint32_t RESERVED2[1012]; /*!< Reserved2,                                         Address offset: 0x30 to 0xFFC */

+  __IO uint32_t LUT[2048];       /*!< GFXMMU LUT registers,                              Address offset: 0x1000 to 0x2FFC

+                                      For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */

+} GFXMMU_TypeDef;

+/**

+  * @brief General Purpose I/O

+  */

+

+typedef struct

+{

+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */

+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */

+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */

+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */

+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */

+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */

+  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset,               Address offset: 0x18      */

+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */

+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */

+} GPIO_TypeDef;

+

+/**

+  * @brief Operational Amplifier (OPAMP)

+  */

+

+typedef struct

+{

+  __IO uint32_t CSR;          /*!< OPAMP control/status register,                      Address offset: 0x00 */

+  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,     Address offset: 0x04 */

+  __IO uint32_t HSOTR;        /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */

+} OPAMP_TypeDef;

+

+/**

+  * @brief System configuration controller

+  */

+

+typedef struct

+{

+ uint32_t RESERVED1;           /*!< Reserved,                                           Address offset: 0x00        */

+ __IO uint32_t PMCR;           /*!< SYSCFG peripheral mode configuration register,      Address offset: 0x04        */

+ __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration registers,  Address offset: 0x08-0x14   */

+ __IO uint32_t CFGR;           /*!< SYSCFG configuration registers,                     Address offset: 0x18        */

+ uint32_t RESERVED2;           /*!< Reserved,                                           Address offset: 0x1C        */

+ __IO uint32_t CCCSR;          /*!< SYSCFG compensation cell control/status register,   Address offset: 0x20        */

+ __IO uint32_t CCVR;           /*!< SYSCFG compensation cell value register,            Address offset: 0x24        */

+ __IO uint32_t CCCR;           /*!< SYSCFG compensation cell code register,             Address offset: 0x28        */

+

+} SYSCFG_TypeDef;

+

+/**

+  * @brief Inter-integrated Circuit Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */

+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */

+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */

+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */

+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */

+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */

+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */

+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */

+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */

+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */

+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */

+} I2C_TypeDef;

+

+/**

+  * @brief Independent WATCHDOG

+  */

+

+typedef struct

+{

+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */

+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */

+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */

+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */

+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */

+} IWDG_TypeDef;

+

+

+/**

+  * @brief JPEG Codec

+  */

+typedef struct

+{

+  __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */

+  __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */

+  __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */

+  __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */

+  __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */

+  __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */

+  __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */

+  __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */

+  uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */

+  __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */

+  __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */

+  __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */

+  uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */

+  __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */

+  __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */

+  uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */

+  __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */

+  __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */

+  __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */

+  __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */

+  __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */

+  __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */

+  __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */

+  __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */

+  uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */

+  __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0,                 Address offset: 500h-65Ch */

+  __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1,                 Address offset: 660h-7BCh */

+  __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encodor, DC Huffman table 0,                 Address offset: 7C0h-7DCh */

+  __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encodor, DC Huffman table 1,                 Address offset: 7E0h-7FCh */

+

+} JPEG_TypeDef;

+

+/**

+  * @brief LCD-TFT Display Controller

+  */

+

+typedef struct

+{

+  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04                                                       */

+  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */

+  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */

+  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */

+  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */

+  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */

+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20                                                       */

+  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */

+  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28                                                            */

+  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */

+  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30                                                            */

+  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */

+  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */

+  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */

+  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */

+  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */

+  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */

+} LTDC_TypeDef;

+

+/**

+  * @brief LCD-TFT Display layer x Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */

+  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */

+  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */

+  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */

+  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */

+  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */

+  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */

+  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */

+  uint32_t      RESERVED0[2];  /*!< Reserved */

+  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */

+  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */

+  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */

+  uint32_t      RESERVED1[3];  /*!< Reserved */

+  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */

+

+} LTDC_Layer_TypeDef;

+

+/**

+  * @brief Power Control

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;       /*!< PWR power control register 1,            Address offset: 0x00 */

+  __IO uint32_t CSR1;      /*!< PWR power control status register 1,     Address offset: 0x04 */

+  __IO uint32_t CR2;       /*!< PWR power control register 2,            Address offset: 0x08 */

+  __IO uint32_t CR3;       /*!< PWR power control register 3,            Address offset: 0x0C */

+  __IO uint32_t CPUCR;     /*!< PWR CPU control register,                Address offset: 0x10 */

+       uint32_t RESERVED0; /*!< Reserved,                                Address offset: 0x14 */

+  __IO uint32_t SRDCR;     /*!< PWR SRD domain control register,         Address offset: 0x18 */

+       uint32_t RESERVED1; /*!< Reserved,                                Address offset: 0x1C */

+  __IO uint32_t WKUPCR;    /*!< PWR wakeup clear register,               Address offset: 0x20 */

+  __IO uint32_t WKUPFR;    /*!< PWR wakeup flag register,                Address offset: 0x24 */

+  __IO uint32_t WKUPEPR;   /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */

+} PWR_TypeDef;

+

+/**

+  * @brief Reset and Clock Control

+  */

+

+typedef struct

+{

+ __IO uint32_t CR;             /*!< RCC clock control register,                                              Address offset: 0x00  */

+ __IO uint32_t HSICFGR;        /*!< HSI Clock Calibration Register,                                          Address offset: 0x04  */

+ __IO uint32_t CRRCR;          /*!< Clock Recovery RC  Register,                                             Address offset: 0x08  */

+ __IO uint32_t CSICFGR;        /*!< CSI Clock Calibration Register,                                          Address offset: 0x0C  */

+ __IO uint32_t CFGR;           /*!< RCC clock configuration register,                                        Address offset: 0x10  */

+ uint32_t     RESERVED1;       /*!< Reserved,                                                                Address offset: 0x14  */

+ __IO uint32_t CDCFGR1;         /*!< RCC Domain 1 configuration register,                                    Address offset: 0x18  */

+ __IO uint32_t CDCFGR2;         /*!< RCC Domain 2 configuration register,                                    Address offset: 0x1C  */

+ __IO uint32_t SRDCFGR;         /*!< RCC Domain 3 configuration register,                                    Address offset: 0x20  */

+ uint32_t     RESERVED2;       /*!< Reserved,                                                                Address offset: 0x24  */

+ __IO uint32_t PLLCKSELR;      /*!< RCC PLLs Clock Source Selection Register,                                Address offset: 0x28  */

+ __IO uint32_t PLLCFGR;        /*!< RCC PLLs  Configuration Register,                                        Address offset: 0x2C  */

+ __IO uint32_t PLL1DIVR;       /*!< RCC PLL1 Dividers Configuration Register,                                Address offset: 0x30  */

+ __IO uint32_t PLL1FRACR;      /*!< RCC PLL1 Fractional Divider Configuration Register,                      Address offset: 0x34  */

+ __IO uint32_t PLL2DIVR;       /*!< RCC PLL2 Dividers Configuration Register,                                Address offset: 0x38  */

+ __IO uint32_t PLL2FRACR;      /*!< RCC PLL2 Fractional Divider Configuration Register,                      Address offset: 0x3C  */

+ __IO uint32_t PLL3DIVR;       /*!< RCC PLL3 Dividers Configuration Register,                                Address offset: 0x40  */

+ __IO uint32_t PLL3FRACR;      /*!< RCC PLL3 Fractional Divider Configuration Register,                      Address offset: 0x44  */

+ uint32_t      RESERVED3;      /*!< Reserved,                                                                Address offset: 0x48  */

+ __IO uint32_t  CDCCIPR;       /*!< RCC Domain 1 Kernel Clock Configuration Register                         Address offset: 0x4C  */

+ __IO uint32_t  CDCCIP1R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x50  */

+ __IO uint32_t  CDCCIP2R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x54  */

+ __IO uint32_t  SRDCCIPR;       /*!< RCC Domain 3 Kernel Clock Configuration Register                         Address offset: 0x58  */

+ uint32_t      RESERVED4;      /*!< Reserved,                                                                Address offset: 0x5C  */

+ __IO uint32_t  CIER;          /*!< RCC Clock Source Interrupt Enable Register                               Address offset: 0x60  */

+ __IO uint32_t  CIFR;          /*!< RCC Clock Source Interrupt Flag Register                                 Address offset: 0x64  */

+ __IO uint32_t  CICR;          /*!< RCC Clock Source Interrupt Clear Register                                Address offset: 0x68  */

+ uint32_t     RESERVED5;       /*!< Reserved,                                                                Address offset: 0x6C  */

+ __IO uint32_t  BDCR;          /*!< RCC Vswitch Backup Domain Control Register,                              Address offset: 0x70  */

+ __IO uint32_t  CSR;           /*!< RCC clock control & status register,                                     Address offset: 0x74  */

+ uint32_t     RESERVED6;       /*!< Reserved,                                                                Address offset: 0x78  */

+ __IO uint32_t AHB3RSTR;       /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x7C  */

+ __IO uint32_t AHB1RSTR;       /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x80  */

+ __IO uint32_t AHB2RSTR;       /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x84  */

+ __IO uint32_t AHB4RSTR;       /*!< RCC AHB4 peripheral reset register,                                      Address offset: 0x88  */

+ __IO uint32_t APB3RSTR;       /*!< RCC APB3 peripheral reset register,                                      Address offset: 0x8C  */

+ __IO uint32_t APB1LRSTR;      /*!< RCC APB1 peripheral reset Low Word register,                             Address offset: 0x90  */

+ __IO uint32_t APB1HRSTR;      /*!< RCC APB1 peripheral reset High Word register,                            Address offset: 0x94  */

+ __IO uint32_t APB2RSTR;       /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x98  */

+ __IO uint32_t APB4RSTR;       /*!< RCC APB4 peripheral reset register,                                      Address offset: 0x9C  */

+ uint32_t     RESERVED7;       /*!< Reserved,                                                                Address offset: 0xA0  */

+ uint32_t     RESERVED8;       /*!< Reserved,                                                                Address offset: 0xA4  */

+ __IO uint32_t SRDAMR;         /*!< RCC Domain 3 Autonomous Mode Register,                                   Address offset: 0xA8  */

+  uint32_t     RESERVED9;      /*!< Reserved, 0xAC-0xAF                                                      Address offset: 0xAC  */

+ __IO uint32_t CKGAENR;        /*!< AXI Clocks Gating Enable Register,                                       Address offset: 0xB0  */

+  uint32_t     RESERVED10[31];   /*!< Reserved, 0xAC-0xAF                                                    Address offset: 0xAC  */

+ __IO uint32_t RSR;            /*!< RCC Reset status register,                                               Address offset: 0xD0  */

+ __IO uint32_t AHB3ENR;        /*!< RCC AHB3 peripheral clock  register,                                     Address offset: 0xD4  */

+ __IO uint32_t AHB1ENR;        /*!< RCC AHB1 peripheral clock  register,                                     Address offset: 0xD8  */

+ __IO uint32_t AHB2ENR;        /*!< RCC AHB2 peripheral clock  register,                                     Address offset: 0xDC  */

+ __IO uint32_t AHB4ENR;        /*!< RCC AHB4 peripheral clock  register,                                     Address offset: 0xE0  */

+ __IO uint32_t APB3ENR;        /*!< RCC APB3 peripheral clock  register,                                     Address offset: 0xE4  */

+ __IO uint32_t APB1LENR;       /*!< RCC APB1 peripheral clock  Low Word register,                            Address offset: 0xE8  */

+ __IO uint32_t APB1HENR;       /*!< RCC APB1 peripheral clock  High Word register,                           Address offset: 0xEC  */

+ __IO uint32_t APB2ENR;        /*!< RCC APB2 peripheral clock  register,                                     Address offset: 0xF0  */

+ __IO uint32_t APB4ENR;        /*!< RCC APB4 peripheral clock  register,                                     Address offset: 0xF4  */

+ uint32_t      RESERVED12;      /*!< Reserved,                                                                Address offset: 0xF8  */

+ __IO uint32_t AHB3LPENR;      /*!< RCC AHB3 peripheral sleep clock  register,                               Address offset: 0xFC  */

+ __IO uint32_t AHB1LPENR;      /*!< RCC AHB1 peripheral sleep clock  register,                               Address offset: 0x100 */

+ __IO uint32_t AHB2LPENR;      /*!< RCC AHB2 peripheral sleep clock  register,                               Address offset: 0x104 */

+ __IO uint32_t AHB4LPENR;      /*!< RCC AHB4 peripheral sleep clock  register,                               Address offset: 0x108 */

+ __IO uint32_t APB3LPENR;      /*!< RCC APB3 peripheral sleep clock  register,                               Address offset: 0x10C */

+ __IO uint32_t APB1LLPENR;     /*!< RCC APB1 peripheral sleep clock  Low Word register,                      Address offset: 0x110 */

+ __IO uint32_t APB1HLPENR;     /*!< RCC APB1 peripheral sleep clock  High Word register,                     Address offset: 0x114 */

+ __IO uint32_t APB2LPENR;      /*!< RCC APB2 peripheral sleep clock  register,                               Address offset: 0x118 */

+ __IO uint32_t APB4LPENR;      /*!< RCC APB4 peripheral sleep clock  register,                               Address offset: 0x11C */

+ uint32_t     RESERVED13[4];   /*!< Reserved, 0x120-0x12C                                                    Address offset: 0x120 */

+

+} RCC_TypeDef;

+

+

+/**

+  * @brief Real-Time Clock

+  */

+typedef struct

+{

+  __IO uint32_t TR;             /*!< RTC time register,                              Address offset: 0x00 */

+  __IO uint32_t DR;             /*!< RTC date register,                              Address offset: 0x04 */

+  __IO uint32_t SSR;            /*!< RTC sub second register,                        Address offset: 0x08 */

+  __IO uint32_t ICSR;           /*!< RTC initialization control and status register, Address offset: 0x0C */

+  __IO uint32_t PRER;           /*!< RTC prescaler register,                         Address offset: 0x10 */

+  __IO uint32_t WUTR;           /*!< RTC wakeup timer register,                      Address offset: 0x14 */

+  __IO uint32_t CR;             /*!< RTC control register,                           Address offset: 0x18 */

+       uint32_t RESERVED0;      /*!< Reserved,                                       Address offset: 0x1C */

+       uint32_t RESERVED1;      /*!< Reserved,                                       Address offset: 0x20 */

+  __IO uint32_t WPR;            /*!< RTC write protection register,                  Address offset: 0x24 */

+  __IO uint32_t CALR;           /*!< RTC calibration register,                       Address offset: 0x28 */

+  __IO uint32_t SHIFTR;         /*!< RTC shift control register,                     Address offset: 0x2C */

+  __IO uint32_t TSTR;           /*!< RTC time stamp time register,                   Address offset: 0x30 */

+  __IO uint32_t TSDR;           /*!< RTC time stamp date register,                   Address offset: 0x34 */

+  __IO uint32_t TSSSR;          /*!< RTC time-stamp sub second register,             Address offset: 0x38 */

+       uint32_t RESERVED2;      /*!< Reserved,                                       Address offset: 0x3C */

+  __IO uint32_t ALRMAR;         /*!< RTC alarm A register,                           Address offset: 0x40 */

+  __IO uint32_t ALRMASSR;       /*!< RTC alarm A sub second register,                Address offset: 0x44 */

+  __IO uint32_t ALRMBR;         /*!< RTC alarm B register,                           Address offset: 0x48 */

+  __IO uint32_t ALRMBSSR;       /*!< RTC alarm B sub second register,                Address offset: 0x4C */

+  __IO uint32_t SR;             /*!< RTC Status register,                            Address offset: 0x50 */

+  __IO uint32_t MISR;           /*!< RTC masked interrupt status register,           Address offset: 0x54 */

+       uint32_t RESERVED3;      /*!< Reserved,                                       Address offset: 0x58 */

+  __IO uint32_t SCR;            /*!< RTC status Clear register,                      Address offset: 0x5C */

+  __IO uint32_t CFGR;           /*!< RTC configuration register,                     Address offset: 0x60 */

+} RTC_TypeDef;

+

+/**

+  * @brief Tamper and backup registers

+  */

+typedef struct

+{

+  __IO uint32_t CR1;            /*!< TAMP configuration register 1,            Address offset: 0x00 */

+  __IO uint32_t CR2;            /*!< TAMP configuration register 2,            Address offset: 0x04 */

+       uint32_t RESERVED0;      /*!< Reserved,                                 Address offset: 0x08 */

+  __IO uint32_t FLTCR;          /*!< TAMP filter control register,             Address offset: 0x0C */

+  __IO uint32_t ATCR1;          /*!< TAMP active tamper control register,      Address offset: 0x10 */

+  __IO uint32_t ATSEEDR;        /*!< TAMP active tamper seed register,         Address offset: 0x14 */

+  __IO uint32_t ATOR;           /*!< TAMP active tamper output register,       Address offset: 0x18 */

+       uint32_t RESERVED1[4];   /*!< Reserved,                                 Address offset: 0x1C -- 0x28 */

+  __IO uint32_t IER;            /*!< TAMP interrupt enable register,           Address offset: 0x2C */

+  __IO uint32_t SR;             /*!< TAMP status register,                     Address offset: 0x30 */

+  __IO uint32_t MISR;           /*!< TAMP masked interrupt status register,    Address offset: 0x34 */

+       uint32_t RESERVED2;      /*!< Reserved,                                 Address offset: 0x38 */

+  __IO uint32_t SCR;            /*!< TAMP status clear register,               Address offset: 0x3C */

+  __IO uint32_t COUNTR;         /*!< TAMP monotonic counter register,          Address offset: 0x40 */

+       uint32_t RESERVED3[3];   /*!< Reserved,                                 Address offset: 0x44 -- 0x4C */

+  __IO uint32_t CFGR;           /*!< TAMP configuration register,              Address offset: 0x50 */

+       uint32_t RESERVED4[43];  /*!< Reserved,                                 Address offset: 0x54 -- 0xFC */

+  __IO uint32_t BKP0R;          /*!< TAMP backup register 0,                   Address offset: 0x100 */

+  __IO uint32_t BKP1R;          /*!< TAMP backup register 1,                   Address offset: 0x104 */

+  __IO uint32_t BKP2R;          /*!< TAMP backup register 2,                   Address offset: 0x108 */

+  __IO uint32_t BKP3R;          /*!< TAMP backup register 3,                   Address offset: 0x10C */

+  __IO uint32_t BKP4R;          /*!< TAMP backup register 4,                   Address offset: 0x110 */

+  __IO uint32_t BKP5R;          /*!< TAMP backup register 5,                   Address offset: 0x114 */

+  __IO uint32_t BKP6R;          /*!< TAMP backup register 6,                   Address offset: 0x118 */

+  __IO uint32_t BKP7R;          /*!< TAMP backup register 7,                   Address offset: 0x11C */

+  __IO uint32_t BKP8R;          /*!< TAMP backup register 8,                   Address offset: 0x120 */

+  __IO uint32_t BKP9R;          /*!< TAMP backup register 9,                   Address offset: 0x124 */

+  __IO uint32_t BKP10R;         /*!< TAMP backup register 10,                  Address offset: 0x128 */

+  __IO uint32_t BKP11R;         /*!< TAMP backup register 11,                  Address offset: 0x12C */

+  __IO uint32_t BKP12R;         /*!< TAMP backup register 12,                  Address offset: 0x130 */

+  __IO uint32_t BKP13R;         /*!< TAMP backup register 13,                  Address offset: 0x134 */

+  __IO uint32_t BKP14R;         /*!< TAMP backup register 14,                  Address offset: 0x138 */

+  __IO uint32_t BKP15R;         /*!< TAMP backup register 15,                  Address offset: 0x13C */

+  __IO uint32_t BKP16R;         /*!< TAMP backup register 16,                  Address offset: 0x140 */

+  __IO uint32_t BKP17R;         /*!< TAMP backup register 17,                  Address offset: 0x144 */

+  __IO uint32_t BKP18R;         /*!< TAMP backup register 18,                  Address offset: 0x148 */

+  __IO uint32_t BKP19R;         /*!< TAMP backup register 19,                  Address offset: 0x14C */

+  __IO uint32_t BKP20R;         /*!< TAMP backup register 20,                  Address offset: 0x150 */

+  __IO uint32_t BKP21R;         /*!< TAMP backup register 21,                  Address offset: 0x154 */

+  __IO uint32_t BKP22R;         /*!< TAMP backup register 22,                  Address offset: 0x158 */

+  __IO uint32_t BKP23R;         /*!< TAMP backup register 23,                  Address offset: 0x15C */

+  __IO uint32_t BKP24R;         /*!< TAMP backup register 24,                  Address offset: 0x160 */

+  __IO uint32_t BKP25R;         /*!< TAMP backup register 25,                  Address offset: 0x164 */

+  __IO uint32_t BKP26R;         /*!< TAMP backup register 26,                  Address offset: 0x168 */

+  __IO uint32_t BKP27R;         /*!< TAMP backup register 27,                  Address offset: 0x16C */

+  __IO uint32_t BKP28R;         /*!< TAMP backup register 28,                  Address offset: 0x170 */

+  __IO uint32_t BKP29R;         /*!< TAMP backup register 29,                  Address offset: 0x174 */

+  __IO uint32_t BKP30R;         /*!< TAMP backup register 30,                  Address offset: 0x178 */

+  __IO uint32_t BKP31R;         /*!< TAMP backup register 31,                  Address offset: 0x17C */

+} TAMP_TypeDef;

+

+/**

+  * @brief Serial Audio Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t GCR;           /*!< SAI global configuration register, Address offset: 0x00 */

+  uint32_t      RESERVED0[16]; /*!< Reserved, 0x04 - 0x43                                   */

+  __IO uint32_t PDMCR;         /*!< SAI PDM control register,          Address offset: 0x44 */

+  __IO uint32_t PDMDLY;        /*!< SAI PDM delay register,            Address offset: 0x48 */

+} SAI_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */

+  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */

+  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */

+  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */

+  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */

+  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */

+  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */

+  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */

+} SAI_Block_TypeDef;

+

+/**

+  * @brief SPDIF-RX Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */

+  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */

+  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */

+  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */

+  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */

+  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */

+  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */

+  uint32_t        RESERVED2;    /*!< Reserved,  0x1A                                          */

+} SPDIFRX_TypeDef;

+

+

+/**

+  * @brief Secure digital input/output Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t POWER;          /*!< SDMMC power control register,             Address offset: 0x00  */

+  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,             Address offset: 0x04  */

+  __IO uint32_t ARG;            /*!< SDMMC argument register,                  Address offset: 0x08  */

+  __IO uint32_t CMD;            /*!< SDMMC command register,                   Address offset: 0x0C  */

+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register,          Address offset: 0x10  */

+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                Address offset: 0x14  */

+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                Address offset: 0x18  */

+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                Address offset: 0x1C  */

+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                Address offset: 0x20  */

+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                Address offset: 0x24  */

+  __IO uint32_t DLEN;           /*!< SDMMC data length register,               Address offset: 0x28  */

+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,              Address offset: 0x2C  */

+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,              Address offset: 0x30  */

+  __I uint32_t  STA;            /*!< SDMMC status register,                    Address offset: 0x34  */

+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,           Address offset: 0x38  */

+  __IO uint32_t MASK;           /*!< SDMMC mask register,                      Address offset: 0x3C  */

+  __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,     Address offset: 0x40  */

+  uint32_t      RESERVED0[3];   /*!< Reserved, 0x44 - 0x4C - 0x4C                                    */

+  __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,               Address offset: 0x50  */

+  __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,           Address offset: 0x54  */

+  __IO uint32_t IDMABASE0;      /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58  */

+  __IO uint32_t IDMABASE1;      /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C  */

+  uint32_t      RESERVED1[8];   /*!< Reserved, 0x60-0x7C                                             */

+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,                 Address offset: 0x80  */

+  uint32_t      RESERVED2[222]; /*!< Reserved, 0x84-0x3F8                                            */

+  __IO uint32_t IPVR;           /*!< SDMMC data FIFO register,                 Address offset: 0x3FC */

+} SDMMC_TypeDef;

+

+

+/**

+  * @brief Delay Block DLYB

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;          /*!< DELAY BLOCK control register,  Address offset: 0x00 */

+  __IO uint32_t CFGR;        /*!< DELAY BLOCK configuration register,  Address offset: 0x04 */

+} DLYB_TypeDef;

+

+/**

+  * @brief HW Semaphore HSEM

+  */

+

+typedef struct

+{

+  __IO uint32_t R[32];      /*!< 2-step write lock and read back registers,     Address offset: 00h-7Ch  */

+  __IO uint32_t RLR[32];    /*!< 1-step read lock registers,                    Address offset: 80h-FCh  */

+  __IO uint32_t C1IER;      /*!< HSEM Interrupt enable register ,             Address offset: 100h     */

+  __IO uint32_t C1ICR;      /*!< HSEM Interrupt clear register ,              Address offset: 104h     */

+  __IO uint32_t C1ISR;      /*!< HSEM Interrupt Status register ,             Address offset: 108h     */

+  __IO uint32_t C1MISR;     /*!< HSEM Interrupt Masked Status register ,      Address offset: 10Ch     */

+  uint32_t  Reserved[12];   /* Reserved                                       Address offset: 110h-13Ch  */

+  __IO uint32_t CR;         /*!< HSEM Semaphore clear register ,                Address offset: 140h      */

+  __IO uint32_t KEYR;       /*!< HSEM Semaphore clear key register ,            Address offset: 144h      */

+

+} HSEM_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t IER;        /*!< HSEM interrupt enable register ,                Address offset:   0h     */

+  __IO uint32_t ICR;        /*!< HSEM interrupt clear register ,                 Address offset:   4h     */

+  __IO uint32_t ISR;        /*!< HSEM interrupt status register ,                Address offset:   8h     */

+  __IO uint32_t MISR;       /*!< HSEM masked interrupt status register ,         Address offset:   Ch     */

+} HSEM_Common_TypeDef;

+

+/**

+  * @brief Serial Peripheral Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */

+  __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */

+  __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */

+  __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */

+  __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */

+  __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */

+  __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */

+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */

+  __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */

+  uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */

+  __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */

+  uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */

+  __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */

+  __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */

+  __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */

+  __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */

+  __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */

+

+} SPI_TypeDef;

+

+/**

+  * @brief DTS

+  */

+typedef struct

+{

+  __IO uint32_t CFGR1;         /*!< DTS configuration register,                Address offset: 0x00 */

+  uint32_t RESERVED0;          /*!< Reserved,                                  Address offset: 0x04 */

+  __IO uint32_t T0VALR1;       /*!< DTS T0 Value register,                     Address offset: 0x08 */

+  uint32_t RESERVED1;          /*!< Reserved,                                  Address offset: 0x0C */

+  __IO uint32_t RAMPVALR;      /*!< DTS Ramp value register,                   Address offset: 0x10 */

+  __IO uint32_t ITR1;          /*!< DTS Interrupt threshold register,          Address offset: 0x14 */

+  uint32_t RESERVED2;          /*!< Reserved,                                  Address offset: 0x18 */

+  __IO uint32_t DR;            /*!< DTS data register,                         Address offset: 0x1C */

+  __IO uint32_t SR;            /*!< DTS status register                        Address offset: 0x20 */

+  __IO uint32_t ITENR;         /*!< DTS Interrupt enable register,             Address offset: 0x24 */

+  __IO uint32_t ICIFR;         /*!< DTS Clear Interrupt flag register,         Address offset: 0x28 */

+  __IO uint32_t OR;            /*!< DTS option register 1,                     Address offset: 0x2C */

+}

+DTS_TypeDef;

+

+/**

+  * @brief TIM

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */

+  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */

+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */

+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */

+  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */

+  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */

+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */

+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */

+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */

+  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */

+  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */

+  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */

+  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */

+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */

+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */

+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */

+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */

+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */

+  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */

+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */

+  uint32_t      RESERVED1;   /*!< Reserved, 0x50                                                 */

+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */

+  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */

+  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */

+  __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */

+  __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */

+  __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x68 */

+} TIM_TypeDef;

+

+/**

+  * @brief LPTIMIMER

+  */

+typedef struct

+{

+  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,         Address offset: 0x00 */

+  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,              Address offset: 0x04 */

+  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,             Address offset: 0x08 */

+  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                Address offset: 0x0C */

+  __IO uint32_t CR;       /*!< LPTIM Control register,                      Address offset: 0x10 */

+  __IO uint32_t CMP;      /*!< LPTIM Compare register,                      Address offset: 0x14 */

+  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                   Address offset: 0x18 */

+  __IO uint32_t CNT;      /*!< LPTIM Counter register,                      Address offset: 0x1C */

+  uint32_t  RESERVED1;    /*!< Reserved, 0x20                                                    */

+  __IO uint32_t CFGR2;    /*!< LPTIM Configuration register,                Address offset: 0x24 */

+} LPTIM_TypeDef;

+

+/**

+  * @brief Comparator

+  */

+typedef struct

+{

+  __IO uint32_t SR;        /*!< Comparator status register,                    Address offset: 0x00 */

+  __IO uint32_t ICFR;      /*!< Comparator interrupt clear flag register,       Address offset: 0x04 */

+  __IO uint32_t OR;        /*!< Comparator option register,                  Address offset: 0x08 */

+} COMPOPT_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CFGR;      /*!< Comparator configuration register  ,           Address offset: 0x00 */

+} COMP_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CFGR;       /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */

+} COMP_Common_TypeDef;

+/**

+  * @brief Universal Synchronous Asynchronous Receiver Transmitter

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */

+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */

+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */

+  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */

+  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */

+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */

+  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */

+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */

+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */

+  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */

+  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */

+  __IO uint32_t PRESC;  /*!< USART clock Prescaler register,           Address offset: 0x2C */

+} USART_TypeDef;

+

+/**

+  * @brief Single Wire Protocol Master Interface SPWMI

+  */

+typedef struct

+{

+  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */

+  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */

+    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */

+  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */

+  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */

+  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */

+  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */

+  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */

+  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */

+  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */

+} SWPMI_TypeDef;

+

+/**

+  * @brief Window WATCHDOG

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */

+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */

+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */

+} WWDG_TypeDef;

+

+

+/**

+  * @brief RAM_ECC_Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t CR;           /*!< RAMECC monitor configuration register          */

+  __IO uint32_t SR;           /*!< RAMECC monitor status register                 */

+  __IO uint32_t FAR;          /*!< RAMECC monitor failing address register        */

+  __IO uint32_t FDRL;         /*!< RAMECC monitor failing data low register       */

+  __IO uint32_t FDRH;         /*!< RAMECC monitor failing data high register      */

+  __IO uint32_t FECR;         /*!< RAMECC monitor failing ECC error code register */

+} RAMECC_MonitorTypeDef;

+

+typedef struct

+{

+  __IO uint32_t IER;          /*!< RAMECC interrupt enable register */

+} RAMECC_TypeDef;

+/**

+  * @}

+  */

+

+

+

+/**

+  * @brief RNG

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */

+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */

+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */

+  uint32_t RESERVED;

+  __IO uint32_t HTCR;  /*!< RNG health test configuration register, Address offset: 0x10 */

+} RNG_TypeDef;

+

+/**

+  * @brief MDIOS

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;

+  __IO uint32_t WRFR;

+  __IO uint32_t CWRFR;

+  __IO uint32_t RDFR;

+  __IO uint32_t CRDFR;

+  __IO uint32_t SR;

+  __IO uint32_t CLRFR;

+  uint32_t RESERVED[57];

+  __IO uint32_t DINR0;

+  __IO uint32_t DINR1;

+  __IO uint32_t DINR2;

+  __IO uint32_t DINR3;

+  __IO uint32_t DINR4;

+  __IO uint32_t DINR5;

+  __IO uint32_t DINR6;

+  __IO uint32_t DINR7;

+  __IO uint32_t DINR8;

+  __IO uint32_t DINR9;

+  __IO uint32_t DINR10;

+  __IO uint32_t DINR11;

+  __IO uint32_t DINR12;

+  __IO uint32_t DINR13;

+  __IO uint32_t DINR14;

+  __IO uint32_t DINR15;

+  __IO uint32_t DINR16;

+  __IO uint32_t DINR17;

+  __IO uint32_t DINR18;

+  __IO uint32_t DINR19;

+  __IO uint32_t DINR20;

+  __IO uint32_t DINR21;

+  __IO uint32_t DINR22;

+  __IO uint32_t DINR23;

+  __IO uint32_t DINR24;

+  __IO uint32_t DINR25;

+  __IO uint32_t DINR26;

+  __IO uint32_t DINR27;

+  __IO uint32_t DINR28;

+  __IO uint32_t DINR29;

+  __IO uint32_t DINR30;

+  __IO uint32_t DINR31;

+  __IO uint32_t DOUTR0;

+  __IO uint32_t DOUTR1;

+  __IO uint32_t DOUTR2;

+  __IO uint32_t DOUTR3;

+  __IO uint32_t DOUTR4;

+  __IO uint32_t DOUTR5;

+  __IO uint32_t DOUTR6;

+  __IO uint32_t DOUTR7;

+  __IO uint32_t DOUTR8;

+  __IO uint32_t DOUTR9;

+  __IO uint32_t DOUTR10;

+  __IO uint32_t DOUTR11;

+  __IO uint32_t DOUTR12;

+  __IO uint32_t DOUTR13;

+  __IO uint32_t DOUTR14;

+  __IO uint32_t DOUTR15;

+  __IO uint32_t DOUTR16;

+  __IO uint32_t DOUTR17;

+  __IO uint32_t DOUTR18;

+  __IO uint32_t DOUTR19;

+  __IO uint32_t DOUTR20;

+  __IO uint32_t DOUTR21;

+  __IO uint32_t DOUTR22;

+  __IO uint32_t DOUTR23;

+  __IO uint32_t DOUTR24;

+  __IO uint32_t DOUTR25;

+  __IO uint32_t DOUTR26;

+  __IO uint32_t DOUTR27;

+  __IO uint32_t DOUTR28;

+  __IO uint32_t DOUTR29;

+  __IO uint32_t DOUTR30;

+  __IO uint32_t DOUTR31;

+} MDIOS_TypeDef;

+

+

+/**

+  * @brief USB_OTG_Core_Registers

+  */

+typedef struct

+{

+ __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */

+  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */

+  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */

+  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */

+  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */

+  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */

+  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */

+  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */

+  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */

+  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */

+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */

+  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */

+  uint32_t Reserved30[2];             /*!< Reserved                                     030h */

+  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */

+  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */

+  __IO uint32_t GSNPSID;              /* USB_OTG core ID                                040h*/

+  __IO uint32_t GHWCFG1;              /* User HW config1                                044h*/

+  __IO uint32_t GHWCFG2;              /* User HW config2                                048h*/

+  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */

+  uint32_t  Reserved6;                /*!< Reserved                                     050h */

+  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */

+  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */

+  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */

+   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */

+    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */

+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */

+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */

+} USB_OTG_GlobalTypeDef;

+

+

+/**

+  * @brief USB_OTG_device_Registers

+  */

+typedef struct

+{

+  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */

+  __IO uint32_t DCTL;            /*!< dev Control Register         804h */

+  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */

+  uint32_t Reserved0C;           /*!< Reserved                     80Ch */

+  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */

+  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */

+  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */

+  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */

+  uint32_t  Reserved20;          /*!< Reserved                     820h */

+  uint32_t Reserved9;            /*!< Reserved                     824h */

+  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */

+  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */

+  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */

+  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */

+  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */

+  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */

+  uint32_t Reserved40;           /*!< dedicated EP mask            840h */

+  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */

+  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */

+  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */

+} USB_OTG_DeviceTypeDef;

+

+

+/**

+  * @brief USB_OTG_IN_Endpoint-Specific_Register

+  */

+typedef struct

+{

+  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */

+  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */

+  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */

+  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */

+  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */

+  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */

+  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */

+  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */

+} USB_OTG_INEndpointTypeDef;

+

+

+/**

+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */

+  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */

+  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */

+  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */

+  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */

+  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */

+  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */

+} USB_OTG_OUTEndpointTypeDef;

+

+

+/**

+  * @brief USB_OTG_Host_Mode_Register_Structures

+  */

+typedef struct

+{

+  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */

+  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */

+  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */

+  uint32_t Reserved40C;           /*!< Reserved                             40Ch */

+  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */

+  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */

+  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */

+} USB_OTG_HostTypeDef;

+

+/**

+  * @brief USB_OTG_Host_Channel_Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */

+  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */

+  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */

+  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */

+  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */

+  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */

+  uint32_t Reserved[2];           /*!< Reserved                                      */

+} USB_OTG_HostChannelTypeDef;

+/**

+  * @}

+  */

+

+/**

+  * @brief OCTO Serial Peripheral Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;          /*!< OCTOSPI Control register,                           Address offset: 0x000 */

+  uint32_t RESERVED;         /*!< Reserved,                                           Address offset: 0x004 */

+  __IO uint32_t DCR1;        /*!< OCTOSPI Device Configuration register 1,            Address offset: 0x008 */

+  __IO uint32_t DCR2;        /*!< OCTOSPI Device Configuration register 2,            Address offset: 0x00C */

+  __IO uint32_t DCR3;        /*!< OCTOSPI Device Configuration register 3,            Address offset: 0x010 */

+  __IO uint32_t DCR4;        /*!< OCTOSPI Device Configuration register 4,            Address offset: 0x014 */

+  uint32_t RESERVED1[2];     /*!< Reserved,                                           Address offset: 0x018-0x01C */

+  __IO uint32_t SR;          /*!< OCTOSPI Status register,                            Address offset: 0x020 */

+  __IO uint32_t FCR;         /*!< OCTOSPI Flag Clear register,                        Address offset: 0x024 */

+  uint32_t RESERVED2[6];     /*!< Reserved,                                           Address offset: 0x028-0x03C */

+  __IO uint32_t DLR;         /*!< OCTOSPI Data Length register,                       Address offset: 0x040 */

+  uint32_t RESERVED3;        /*!< Reserved,                                           Address offset: 0x044 */

+  __IO uint32_t AR;          /*!< OCTOSPI Address register,                           Address offset: 0x048 */

+  uint32_t RESERVED4;        /*!< Reserved,                                           Address offset: 0x04C */

+  __IO uint32_t DR;          /*!< OCTOSPI Data register,                              Address offset: 0x050 */

+  uint32_t RESERVED5[11];    /*!< Reserved,                                           Address offset: 0x054-0x07C */

+  __IO uint32_t PSMKR;       /*!< OCTOSPI Polling Status Mask register,               Address offset: 0x080 */

+  uint32_t RESERVED6;        /*!< Reserved,                                           Address offset: 0x084 */

+  __IO uint32_t PSMAR;       /*!< OCTOSPI Polling Status Match register,              Address offset: 0x088 */

+  uint32_t RESERVED7;        /*!< Reserved,                                           Address offset: 0x08C */

+  __IO uint32_t PIR;         /*!< OCTOSPI Polling Interval register,                  Address offset: 0x090 */

+  uint32_t RESERVED8[27];    /*!< Reserved,                                           Address offset: 0x094-0x0FC */

+  __IO uint32_t CCR;         /*!< OCTOSPI Communication Configuration register,       Address offset: 0x100 */

+  uint32_t RESERVED9;        /*!< Reserved,                                           Address offset: 0x104 */

+  __IO uint32_t TCR;         /*!< OCTOSPI Timing Configuration register,              Address offset: 0x108 */

+  uint32_t RESERVED10;       /*!< Reserved,                                           Address offset: 0x10C */

+  __IO uint32_t IR;          /*!< OCTOSPI Instruction register,                       Address offset: 0x110 */

+  uint32_t RESERVED11[3];    /*!< Reserved,                                           Address offset: 0x114-0x11C */

+  __IO uint32_t ABR;         /*!< OCTOSPI Alternate Bytes register,                   Address offset: 0x120 */

+  uint32_t RESERVED12[3];    /*!< Reserved,                                           Address offset: 0x124-0x12C */

+  __IO uint32_t LPTR;        /*!< OCTOSPI Low Power Timeout register,                 Address offset: 0x130 */

+  uint32_t RESERVED13[3];    /*!< Reserved,                                           Address offset: 0x134-0x13C */

+  __IO uint32_t WPCCR;       /*!< OCTOSPI Wrap Communication Configuration register,  Address offset: 0x140 */

+  uint32_t RESERVED14;       /*!< Reserved,                                           Address offset: 0x144 */

+  __IO uint32_t WPTCR;       /*!< OCTOSPI Wrap Timing Configuration register,         Address offset: 0x148 */

+  uint32_t RESERVED15;       /*!< Reserved,                                           Address offset: 0x14C */

+  __IO uint32_t WPIR;        /*!< OCTOSPI Wrap Instruction register,                  Address offset: 0x150 */

+  uint32_t RESERVED16[3];    /*!< Reserved,                                           Address offset: 0x154-0x15C */

+  __IO uint32_t WPABR;       /*!< OCTOSPI Wrap Alternate Bytes register,              Address offset: 0x160 */

+  uint32_t RESERVED17[7];    /*!< Reserved,                                           Address offset: 0x164-0x17C */

+  __IO uint32_t WCCR;        /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */

+  uint32_t RESERVED18;       /*!< Reserved,                                           Address offset: 0x184 */

+  __IO uint32_t WTCR;        /*!< OCTOSPI Write Timing Configuration register,        Address offset: 0x188 */

+  uint32_t RESERVED19;       /*!< Reserved,                                           Address offset: 0x18C */

+  __IO uint32_t WIR;         /*!< OCTOSPI Write Instruction register,                 Address offset: 0x190 */

+  uint32_t RESERVED20[3];    /*!< Reserved,                                           Address offset: 0x194-0x19C */

+  __IO uint32_t WABR;        /*!< OCTOSPI Write Alternate Bytes register,             Address offset: 0x1A0 */

+  uint32_t RESERVED21[23];   /*!< Reserved,                                           Address offset: 0x1A4-0x1FC */

+  __IO uint32_t HLCR;        /*!< OCTOSPI Hyperbus Latency Configuration register,    Address offset: 0x200 */

+  uint32_t RESERVED22[122];  /*!< Reserved,                                           Address offset: 0x204-0x3EC */

+  __IO uint32_t HWCFGR;      /*!< OCTOSPI HW Configuration register,                  Address offset: 0x3F0 */

+  __IO uint32_t VER;         /*!< OCTOSPI Version register,                           Address offset: 0x3F4 */

+  __IO uint32_t ID;          /*!< OCTOSPI Identification register,                    Address offset: 0x3F8 */

+  __IO uint32_t MID;         /*!< OCTOPSI HW Magic ID register,                       Address offset: 0x3FC */

+} OCTOSPI_TypeDef;

+

+/**

+  * @}

+  */

+/**

+  * @brief OCTO Serial Peripheral Interface IO Manager

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;          /*!< OCTOSPI IO Manager Control register,                 Address offset: 0x00 */

+  __IO uint32_t PCR[3];      /*!< OCTOSPI IO Manager Port[1:3] Configuration register, Address offset: 0x04-0x20 */

+} OCTOSPIM_TypeDef;

+

+/**

+  * @}

+  */

+

+/** @addtogroup Peripheral_memory_map

+  * @{

+  */

+#define CD_ITCMRAM_BASE           (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM  */

+#define CD_DTCMRAM_BASE           (0x20000000UL) /*!< Base address of : 128KB (2x64KB) system data RAM accessible over DTCM                   */

+#define CD_AXIFLASH_BASE          (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI                */

+

+#define CD_AXISRAM1_BASE          (0x24000000UL) /*!< Base address of : (up to 256KB) system data RAM1 accessible over over AXI                */

+#define CD_AXISRAM2_BASE          (0x24040000UL) /*!< Base address of : (up to 384KB) system data RAM2 accessible over over AXI                */

+#define CD_AXISRAM3_BASE          (0x240A0000UL) /*!< Base address of : (up to 384KB) system data RAM3 accessible over over AXI                */

+#define CD_AHBSRAM1_BASE          (0x30000000UL) /*!< Base address of : (up to 64KB) system data RAM1 accessible over over AXI->AHB Bridge     */

+#define CD_AHBSRAM2_BASE          (0x30010000UL) /*!< Base address of : (up to 64KB) system data RAM2 accessible over over AXI->AHB Bridge     */

+

+#define SRD_BKPSRAM_BASE           (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge                                */

+#define SRD_SRAM_BASE              (0x38000000UL) /*!< Base address of : Backup SRAM(32 KB) over AXI->AHB Bridge                               */

+

+#define OCTOSPI1_BASE             (0x90000000UL) /*!< Base address of : OCTOSPI1 memories  accessible over AXI                                 */

+#define OCTOSPI2_BASE             (0x70000000UL) /*!< Base address of : OCTOSPI2 memories  accessible over AXI                                 */

+

+#define FLASH_BANK1_BASE          (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI                          */

+#define FLASH_BANK2_BASE          (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI                          */

+#define FLASH_END                 (0x081FFFFFUL) /*!< FLASH end address                                                                       */

+

+/* Legacy define */

+#define FLASH_BASE                FLASH_BANK1_BASE

+#define D1_AXISRAM_BASE           CD_AXISRAM1_BASE

+

+#define FLASH_OTP_BASE            (0x08FFF000UL) /*!< Base address of : (up to 1KB) embedded FLASH Bank1 OTP Area                           */

+#define FLASH_OTP_END             (0x08FFF3FFUL) /*!< End address of : (up to 1KB) embedded FLASH Bank1 OTP Area                            */

+

+

+/*!< Device electronic signature memory map */

+#define UID_BASE                  (0x08FFF800UL)            /*!< Unique device ID register base address */

+#define FLASHSIZE_BASE            (0x08FFF80CUL)            /*!< FLASH Size register base address */

+#define PACKAGE_BASE              (0x08FFF80EUL)            /*!< Package Data register base address */

+

+#define PERIPH_BASE               (0x40000000UL) /*!< Base address of : AHB/ABP Peripherals                                                    */

+/*!< Peripheral memory map */

+#define CD_APB1PERIPH_BASE        PERIPH_BASE                   /*!<  D2_APB1PERIPH_BASE        PERIPH_BASE                                    */

+#define CD_APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)   /*!<  D2_APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)                    */

+#define CD_AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)   /*!<  D2_AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)                    */

+#define CD_AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)   /*!<  D2_AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)                    */

+

+#define CD_APB3PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)   /*!<  D1_APB1PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)                    */

+#define CD_AHB3PERIPH_BASE       (PERIPH_BASE + 0x12000000UL)   /*!<  D1_AHB1PERIPH_BASE       (PERIPH_BASE + 0x12000000UL)                    */

+

+#define SRD_APB4PERIPH_BASE      (PERIPH_BASE + 0x18000000UL)   /*!<  D3_APB1PERIPH_BASE       (PERIPH_BASE + 0x18000000UL)                    */

+#define SRD_AHB4PERIPH_BASE      (PERIPH_BASE + 0x18020000UL)   /*!<  D3_AHB1PERIPH_BASE       (PERIPH_BASE + 0x18020000UL)                    */

+

+/*!< Legacy Peripheral memory map */

+#define APB1PERIPH_BASE        PERIPH_BASE

+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)

+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)

+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)

+

+/*!< CD_AHB3PERIPH peripherals */

+#define MDMA_BASE             (CD_AHB3PERIPH_BASE + 0x0000UL)

+#define DMA2D_BASE            (CD_AHB3PERIPH_BASE + 0x1000UL)

+#define FLASH_R_BASE          (CD_AHB3PERIPH_BASE + 0x2000UL)

+#define JPGDEC_BASE           (CD_AHB3PERIPH_BASE + 0x3000UL)

+#define FMC_R_BASE            (CD_AHB3PERIPH_BASE + 0x4000UL)

+#define OCTOSPI1_R_BASE       (CD_AHB3PERIPH_BASE + 0x5000UL)

+#define DLYB_OCTOSPI1_BASE    (CD_AHB3PERIPH_BASE + 0x6000UL)

+#define SDMMC1_BASE           (CD_AHB3PERIPH_BASE + 0x7000UL)

+#define DLYB_SDMMC1_BASE      (CD_AHB3PERIPH_BASE + 0x8000UL)

+#define RAMECC_BASE           (CD_AHB3PERIPH_BASE + 0x9000UL)

+#define OCTOSPI2_R_BASE       (CD_AHB3PERIPH_BASE + 0xA000UL)

+#define DLYB_OCTOSPI2_BASE    (CD_AHB3PERIPH_BASE + 0xB000UL)

+#define OCTOSPIM_BASE         (CD_AHB3PERIPH_BASE + 0xB400UL)

+

+/*!< CD_AHB1PERIPH peripherals */

+

+#define DMA1_BASE               (CD_AHB1PERIPH_BASE + 0x0000UL)

+#define DMA2_BASE               (CD_AHB1PERIPH_BASE + 0x0400UL)

+#define DMAMUX1_BASE            (CD_AHB1PERIPH_BASE + 0x0800UL)

+#define ADC1_BASE               (CD_AHB1PERIPH_BASE + 0x2000UL)

+#define ADC2_BASE               (CD_AHB1PERIPH_BASE + 0x2100UL)

+#define ADC12_COMMON_BASE       (CD_AHB1PERIPH_BASE + 0x2300UL)

+#define CRC_BASE                (CD_AHB1PERIPH_BASE + 0x3000UL)

+

+/*!< USB registers base address */

+#define USB1_OTG_HS_PERIPH_BASE              (0x40040000UL)

+#define USB_OTG_GLOBAL_BASE                  (0x000UL)

+#define USB_OTG_DEVICE_BASE                  (0x800UL)

+#define USB_OTG_IN_ENDPOINT_BASE             (0x900UL)

+#define USB_OTG_OUT_ENDPOINT_BASE            (0xB00UL)

+#define USB_OTG_EP_REG_SIZE                  (0x20UL)

+#define USB_OTG_HOST_BASE                    (0x400UL)

+#define USB_OTG_HOST_PORT_BASE               (0x440UL)

+#define USB_OTG_HOST_CHANNEL_BASE            (0x500UL)

+#define USB_OTG_HOST_CHANNEL_SIZE            (0x20UL)

+#define USB_OTG_PCGCCTL_BASE                 (0xE00UL)

+#define USB_OTG_FIFO_BASE                    (0x1000UL)

+#define USB_OTG_FIFO_SIZE                    (0x1000UL)

+

+/*!< CD_AHB2PERIPH peripherals */

+

+#define DCMI_BASE              (CD_AHB2PERIPH_BASE + 0x0000UL)

+#define PSSI_BASE              (CD_AHB2PERIPH_BASE + 0x0400UL)

+#define HSEM_BASE              (CD_AHB2PERIPH_BASE + 0x0800UL)

+#define RNG_BASE               (CD_AHB2PERIPH_BASE + 0x1800UL)

+#define SDMMC2_BASE            (CD_AHB2PERIPH_BASE + 0x2400UL)

+#define DLYB_SDMMC2_BASE       (CD_AHB2PERIPH_BASE + 0x2800UL)

+#define BDMA1_BASE             (CD_AHB2PERIPH_BASE + 0x2C00UL)

+

+/*!< SRD_AHB4PERIPH peripherals */

+#define GPIOA_BASE            (SRD_AHB4PERIPH_BASE + 0x0000UL)

+#define GPIOB_BASE            (SRD_AHB4PERIPH_BASE + 0x0400UL)

+#define GPIOC_BASE            (SRD_AHB4PERIPH_BASE + 0x0800UL)

+#define GPIOD_BASE            (SRD_AHB4PERIPH_BASE + 0x0C00UL)

+#define GPIOE_BASE            (SRD_AHB4PERIPH_BASE + 0x1000UL)

+#define GPIOF_BASE            (SRD_AHB4PERIPH_BASE + 0x1400UL)

+#define GPIOG_BASE            (SRD_AHB4PERIPH_BASE + 0x1800UL)

+#define GPIOH_BASE            (SRD_AHB4PERIPH_BASE + 0x1C00UL)

+#define GPIOI_BASE            (SRD_AHB4PERIPH_BASE + 0x2000UL)

+#define GPIOJ_BASE            (SRD_AHB4PERIPH_BASE + 0x2400UL)

+#define GPIOK_BASE            (SRD_AHB4PERIPH_BASE + 0x2800UL)

+#define RCC_BASE              (SRD_AHB4PERIPH_BASE + 0x4400UL)

+#define PWR_BASE              (SRD_AHB4PERIPH_BASE + 0x4800UL)

+#define BDMA2_BASE            (SRD_AHB4PERIPH_BASE + 0x5400UL)

+#define DMAMUX2_BASE          (SRD_AHB4PERIPH_BASE + 0x5800UL)

+

+/*!< CD_APB3PERIPH peripherals */

+#define LTDC_BASE             (CD_APB3PERIPH_BASE + 0x1000UL)

+#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84UL)

+#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104UL)

+#define WWDG1_BASE            (CD_APB3PERIPH_BASE + 0x3000UL)

+

+/*!< CD_APB1PERIPH peripherals */

+#define TIM2_BASE             (CD_APB1PERIPH_BASE + 0x0000UL)

+#define TIM3_BASE             (CD_APB1PERIPH_BASE + 0x0400UL)

+#define TIM4_BASE             (CD_APB1PERIPH_BASE + 0x0800UL)

+#define TIM5_BASE             (CD_APB1PERIPH_BASE + 0x0C00UL)

+#define TIM6_BASE             (CD_APB1PERIPH_BASE + 0x1000UL)

+#define TIM7_BASE             (CD_APB1PERIPH_BASE + 0x1400UL)

+#define TIM12_BASE            (CD_APB1PERIPH_BASE + 0x1800UL)

+#define TIM13_BASE            (CD_APB1PERIPH_BASE + 0x1C00UL)

+#define TIM14_BASE            (CD_APB1PERIPH_BASE + 0x2000UL)

+#define LPTIM1_BASE           (CD_APB1PERIPH_BASE + 0x2400UL)

+

+#define SPI2_BASE             (CD_APB1PERIPH_BASE + 0x3800UL)

+#define SPI3_BASE             (CD_APB1PERIPH_BASE + 0x3C00UL)

+#define SPDIFRX_BASE          (CD_APB1PERIPH_BASE + 0x4000UL)

+#define USART2_BASE           (CD_APB1PERIPH_BASE + 0x4400UL)

+#define USART3_BASE           (CD_APB1PERIPH_BASE + 0x4800UL)

+#define UART4_BASE            (CD_APB1PERIPH_BASE + 0x4C00UL)

+#define UART5_BASE            (CD_APB1PERIPH_BASE + 0x5000UL)

+#define I2C1_BASE             (CD_APB1PERIPH_BASE + 0x5400UL)

+#define I2C2_BASE             (CD_APB1PERIPH_BASE + 0x5800UL)

+#define I2C3_BASE             (CD_APB1PERIPH_BASE + 0x5C00UL)

+#define CEC_BASE              (CD_APB1PERIPH_BASE + 0x6C00UL)

+#define DAC1_BASE             (CD_APB1PERIPH_BASE + 0x7400UL)

+#define UART7_BASE            (CD_APB1PERIPH_BASE + 0x7800UL)

+#define UART8_BASE            (CD_APB1PERIPH_BASE + 0x7C00UL)

+#define CRS_BASE              (CD_APB1PERIPH_BASE + 0x8400UL)

+#define SWPMI1_BASE           (CD_APB1PERIPH_BASE + 0x8800UL)

+#define OPAMP_BASE            (CD_APB1PERIPH_BASE + 0x9000UL)

+#define OPAMP1_BASE           (CD_APB1PERIPH_BASE + 0x9000UL)

+#define OPAMP2_BASE           (CD_APB1PERIPH_BASE + 0x9010UL)

+#define MDIOS_BASE            (CD_APB1PERIPH_BASE + 0x9400UL)

+#define FDCAN1_BASE           (CD_APB1PERIPH_BASE + 0xA000UL)

+#define FDCAN2_BASE           (CD_APB1PERIPH_BASE + 0xA400UL)

+#define FDCAN_CCU_BASE        (CD_APB1PERIPH_BASE + 0xA800UL)

+#define SRAMCAN_BASE          (CD_APB1PERIPH_BASE + 0xAC00UL)

+

+/*!< CD_APB2PERIPH peripherals */

+

+#define TIM1_BASE             (CD_APB2PERIPH_BASE + 0x0000UL)

+#define TIM8_BASE             (CD_APB2PERIPH_BASE + 0x0400UL)

+#define USART1_BASE           (CD_APB2PERIPH_BASE + 0x1000UL)

+#define USART6_BASE           (CD_APB2PERIPH_BASE + 0x1400UL)

+#define UART9_BASE            (CD_APB2PERIPH_BASE + 0x1800UL)

+#define USART10_BASE          (CD_APB2PERIPH_BASE + 0x1C00UL)

+#define SPI1_BASE             (CD_APB2PERIPH_BASE + 0x3000UL)

+#define SPI4_BASE             (CD_APB2PERIPH_BASE + 0x3400UL)

+#define TIM15_BASE            (CD_APB2PERIPH_BASE + 0x4000UL)

+#define TIM16_BASE            (CD_APB2PERIPH_BASE + 0x4400UL)

+#define TIM17_BASE            (CD_APB2PERIPH_BASE + 0x4800UL)

+#define SPI5_BASE             (CD_APB2PERIPH_BASE + 0x5000UL)

+#define SAI1_BASE             (CD_APB2PERIPH_BASE + 0x5800UL)

+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)

+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)

+#define SAI2_BASE             (CD_APB2PERIPH_BASE + 0x5C00UL)

+#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004UL)

+#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024UL)

+#define DFSDM1_BASE           (CD_APB2PERIPH_BASE + 0x7800UL)

+#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00UL)

+#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20UL)

+#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40UL)

+#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60UL)

+#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80UL)

+#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0UL)

+#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0UL)

+#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0UL)

+#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)

+#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)

+#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)

+#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)

+#define DFSDM1_Filter4_BASE   (DFSDM1_BASE + 0x300UL)

+#define DFSDM1_Filter5_BASE   (DFSDM1_BASE + 0x380UL)

+#define DFSDM1_Filter6_BASE   (DFSDM1_BASE + 0x400UL)

+#define DFSDM1_Filter7_BASE   (DFSDM1_BASE + 0x480UL)

+/*!< SRD_APB4PERIPH peripherals */

+#define EXTI_BASE             (SRD_APB4PERIPH_BASE + 0x0000UL)

+#define EXTI_D1_BASE          (EXTI_BASE + 0x0080UL)

+#define SYSCFG_BASE           (SRD_APB4PERIPH_BASE + 0x0400UL)

+#define LPUART1_BASE          (SRD_APB4PERIPH_BASE + 0x0C00UL)

+#define SPI6_BASE             (SRD_APB4PERIPH_BASE + 0x1400UL)

+#define I2C4_BASE             (SRD_APB4PERIPH_BASE + 0x1C00UL)

+#define LPTIM2_BASE           (SRD_APB4PERIPH_BASE + 0x2400UL)

+#define LPTIM3_BASE           (SRD_APB4PERIPH_BASE + 0x2800UL)

+#define DAC2_BASE             (SRD_APB4PERIPH_BASE + 0x3400UL)

+#define COMP12_BASE           (SRD_APB4PERIPH_BASE + 0x3800UL)

+#define COMP1_BASE            (COMP12_BASE + 0x0CUL)

+#define COMP2_BASE            (COMP12_BASE + 0x10UL)

+#define VREFBUF_BASE          (SRD_APB4PERIPH_BASE + 0x3C00UL)

+#define RTC_BASE              (SRD_APB4PERIPH_BASE + 0x4000UL)

+#define TAMP_BASE             (SRD_APB4PERIPH_BASE + 0x4400UL)

+#define IWDG1_BASE            (SRD_APB4PERIPH_BASE + 0x4800UL)

+

+#define DTS_BASE              (SRD_APB4PERIPH_BASE + 0x6800UL)

+

+#define DFSDM2_BASE           (SRD_APB4PERIPH_BASE + 0x6C00UL)

+#define DFSDM2_Channel0_BASE  (DFSDM2_BASE + 0x00UL)

+#define DFSDM2_Channel1_BASE  (DFSDM2_BASE + 0x20UL)

+#define DFSDM2_FLT0_BASE      (DFSDM2_BASE + 0x100UL)

+

+/*!< CD_AHB3PERIPH peripherals */

+#define GFXMMU_BASE           (CD_AHB3PERIPH_BASE + 0xC000UL)

+

+#define BDMA1_Channel0_BASE    (BDMA1_BASE + 0x0008UL)

+#define BDMA1_Channel1_BASE    (BDMA1_BASE + 0x001CUL)

+#define BDMA1_Channel2_BASE    (BDMA1_BASE + 0x0030UL)

+#define BDMA1_Channel3_BASE    (BDMA1_BASE + 0x0044UL)

+#define BDMA1_Channel4_BASE    (BDMA1_BASE + 0x0058UL)

+#define BDMA1_Channel5_BASE    (BDMA1_BASE + 0x006CUL)

+#define BDMA1_Channel6_BASE    (BDMA1_BASE + 0x0080UL)

+#define BDMA1_Channel7_BASE    (BDMA1_BASE + 0x0094UL)

+

+#define BDMA2_Channel0_BASE    (BDMA2_BASE + 0x0008UL)

+#define BDMA2_Channel1_BASE    (BDMA2_BASE + 0x001CUL)

+#define BDMA2_Channel2_BASE    (BDMA2_BASE + 0x0030UL)

+#define BDMA2_Channel3_BASE    (BDMA2_BASE + 0x0044UL)

+#define BDMA2_Channel4_BASE    (BDMA2_BASE + 0x0058UL)

+#define BDMA2_Channel5_BASE    (BDMA2_BASE + 0x006CUL)

+#define BDMA2_Channel6_BASE    (BDMA2_BASE + 0x0080UL)

+#define BDMA2_Channel7_BASE    (BDMA2_BASE + 0x0094UL)

+

+

+#define DMAMUX2_Channel0_BASE    (DMAMUX2_BASE)

+#define DMAMUX2_Channel1_BASE    (DMAMUX2_BASE + 0x0004UL)

+#define DMAMUX2_Channel2_BASE    (DMAMUX2_BASE + 0x0008UL)

+#define DMAMUX2_Channel3_BASE    (DMAMUX2_BASE + 0x000CUL)

+#define DMAMUX2_Channel4_BASE    (DMAMUX2_BASE + 0x0010UL)

+#define DMAMUX2_Channel5_BASE    (DMAMUX2_BASE + 0x0014UL)

+#define DMAMUX2_Channel6_BASE    (DMAMUX2_BASE + 0x0018UL)

+#define DMAMUX2_Channel7_BASE    (DMAMUX2_BASE + 0x001CUL)

+

+#define DMAMUX2_RequestGenerator0_BASE  (DMAMUX2_BASE + 0x0100UL)

+#define DMAMUX2_RequestGenerator1_BASE  (DMAMUX2_BASE + 0x0104UL)

+#define DMAMUX2_RequestGenerator2_BASE  (DMAMUX2_BASE + 0x0108UL)

+#define DMAMUX2_RequestGenerator3_BASE  (DMAMUX2_BASE + 0x010CUL)

+#define DMAMUX2_RequestGenerator4_BASE  (DMAMUX2_BASE + 0x0110UL)

+#define DMAMUX2_RequestGenerator5_BASE  (DMAMUX2_BASE + 0x0114UL)

+#define DMAMUX2_RequestGenerator6_BASE  (DMAMUX2_BASE + 0x0118UL)

+#define DMAMUX2_RequestGenerator7_BASE  (DMAMUX2_BASE + 0x011CUL)

+

+#define DMAMUX2_ChannelStatus_BASE      (DMAMUX2_BASE + 0x0080UL)

+#define DMAMUX2_RequestGenStatus_BASE   (DMAMUX2_BASE + 0x0140UL)

+

+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)

+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)

+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)

+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)

+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)

+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)

+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)

+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)

+

+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)

+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)

+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)

+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)

+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)

+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)

+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)

+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)

+

+

+#define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)

+#define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)

+#define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)

+#define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)

+#define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)

+#define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)

+#define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0018UL)

+#define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x001CUL)

+#define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0020UL)

+#define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x0024UL)

+#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)

+#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)

+#define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)

+#define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)

+#define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)

+#define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)

+

+#define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)

+#define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)

+#define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)

+#define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)

+#define DMAMUX1_RequestGenerator4_BASE  (DMAMUX1_BASE + 0x0110UL)

+#define DMAMUX1_RequestGenerator5_BASE  (DMAMUX1_BASE + 0x0114UL)

+#define DMAMUX1_RequestGenerator6_BASE  (DMAMUX1_BASE + 0x0118UL)

+#define DMAMUX1_RequestGenerator7_BASE  (DMAMUX1_BASE + 0x011CUL)

+

+#define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)

+#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)

+

+/*!< FMC Banks registers base  address */

+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)

+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)

+#define FMC_Bank2_R_BASE      (FMC_R_BASE + 0x0060UL)

+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)

+#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)

+

+/* Debug MCU registers base address */

+#define DBGMCU_BASE           (0x5C001000UL)

+

+#define MDMA_Channel0_BASE    (MDMA_BASE + 0x00000040UL)

+#define MDMA_Channel1_BASE    (MDMA_BASE + 0x00000080UL)

+#define MDMA_Channel2_BASE    (MDMA_BASE + 0x000000C0UL)

+#define MDMA_Channel3_BASE    (MDMA_BASE + 0x00000100UL)

+#define MDMA_Channel4_BASE    (MDMA_BASE + 0x00000140UL)

+#define MDMA_Channel5_BASE    (MDMA_BASE + 0x00000180UL)

+#define MDMA_Channel6_BASE    (MDMA_BASE + 0x000001C0UL)

+#define MDMA_Channel7_BASE    (MDMA_BASE + 0x00000200UL)

+#define MDMA_Channel8_BASE    (MDMA_BASE + 0x00000240UL)

+#define MDMA_Channel9_BASE    (MDMA_BASE + 0x00000280UL)

+#define MDMA_Channel10_BASE   (MDMA_BASE + 0x000002C0UL)

+#define MDMA_Channel11_BASE   (MDMA_BASE + 0x00000300UL)

+#define MDMA_Channel12_BASE   (MDMA_BASE + 0x00000340UL)

+#define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)

+#define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)

+#define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)

+#define MDMA_Channel16_BASE   (MDMA_BASE + 0x00000440UL)

+

+/* GFXMMU virtual buffers base address */

+#define GFXMMU_VIRTUAL_BUFFERS_BASE  (0x25000000UL)

+#define GFXMMU_VIRTUAL_BUFFER0_BASE  (GFXMMU_VIRTUAL_BUFFERS_BASE)

+#define GFXMMU_VIRTUAL_BUFFER1_BASE  (GFXMMU_VIRTUAL_BUFFERS_BASE + 0x400000UL)

+#define GFXMMU_VIRTUAL_BUFFER2_BASE  (GFXMMU_VIRTUAL_BUFFERS_BASE + 0x800000UL)

+#define GFXMMU_VIRTUAL_BUFFER3_BASE  (GFXMMU_VIRTUAL_BUFFERS_BASE + 0xC00000UL)

+

+#define RAMECC_Monitor1_BASE (RAMECC_BASE + 0x20UL)

+#define RAMECC_Monitor2_BASE (RAMECC_BASE + 0x40UL)

+#define RAMECC_Monitor3_BASE (RAMECC_BASE + 0x60UL)

+

+/**

+  * @}

+  */

+

+/** @addtogroup Peripheral_declaration

+  * @{

+  */

+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)

+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)

+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)

+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)

+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)

+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)

+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)

+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)

+#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)

+#define RTC                 ((RTC_TypeDef *) RTC_BASE)

+#define TAMP                ((TAMP_TypeDef *) TAMP_BASE)

+#define WWDG1               ((WWDG_TypeDef *) WWDG1_BASE)

+

+

+#define IWDG1               ((IWDG_TypeDef *) IWDG1_BASE)

+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)

+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)

+#define SPI4                ((SPI_TypeDef *) SPI4_BASE)

+#define SPI5                ((SPI_TypeDef *) SPI5_BASE)

+#define SPI6                ((SPI_TypeDef *) SPI6_BASE)

+#define USART2              ((USART_TypeDef *) USART2_BASE)

+#define USART3              ((USART_TypeDef *) USART3_BASE)

+#define USART6              ((USART_TypeDef *) USART6_BASE)

+#define USART10             ((USART_TypeDef *) USART10_BASE)

+#define UART7               ((USART_TypeDef *) UART7_BASE)

+#define UART8               ((USART_TypeDef *) UART8_BASE)

+#define UART9               ((USART_TypeDef *) UART9_BASE)

+#define CRS                 ((CRS_TypeDef *) CRS_BASE)

+#define UART4               ((USART_TypeDef *) UART4_BASE)

+#define UART5               ((USART_TypeDef *) UART5_BASE)

+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)

+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)

+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)

+#define I2C4                ((I2C_TypeDef *) I2C4_BASE)

+#define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

+#define FDCAN2              ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

+#define FDCAN_CCU           ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

+#define CEC                 ((CEC_TypeDef *) CEC_BASE)

+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)

+#define PWR                 ((PWR_TypeDef *) PWR_BASE)

+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)

+#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)

+#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)

+#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)

+#define LPTIM3              ((LPTIM_TypeDef *) LPTIM3_BASE)

+#define DTS                 ((DTS_TypeDef *) DTS_BASE)

+

+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)

+#define COMP12              ((COMPOPT_TypeDef *) COMP12_BASE)

+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)

+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)

+#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)

+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)

+#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)

+#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)

+

+

+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)

+#define EXTI_D1             ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)

+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)

+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)

+#define USART1              ((USART_TypeDef *) USART1_BASE)

+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)

+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)

+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)

+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)

+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)

+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

+#define SAI2                ((SAI_TypeDef *) SAI2_BASE)

+#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)

+#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)

+

+#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

+#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

+#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

+#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

+#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

+#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

+#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

+#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

+#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

+#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

+#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

+#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

+#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

+#define DFSDM1_Filter4      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter4_BASE)

+#define DFSDM1_Filter5      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter5_BASE)

+#define DFSDM1_Filter6      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter6_BASE)

+#define DFSDM1_Filter7      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter7_BASE)

+#define DFSDM2_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel0_BASE)

+#define DFSDM2_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel1_BASE)

+#define DFSDM2_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM2_FLT0_BASE)

+#define DMA2D               ((DMA2D_TypeDef *) DMA2D_BASE)

+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)

+#define PSSI                ((PSSI_TypeDef *) PSSI_BASE)

+#define RCC                 ((RCC_TypeDef *) RCC_BASE)

+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)

+#define CRC                 ((CRC_TypeDef *) CRC_BASE)

+

+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)

+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)

+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)

+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)

+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)

+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)

+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)

+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)

+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)

+#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)

+#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)

+

+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)

+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)

+#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

+

+#define RNG                 ((RNG_TypeDef *) RNG_BASE)

+#define SDMMC2              ((SDMMC_TypeDef *) SDMMC2_BASE)

+#define DLYB_SDMMC2         ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

+

+#define BDMA1                ((BDMA_TypeDef *) BDMA1_BASE)

+#define BDMA1_Channel0       ((BDMA_Channel_TypeDef *) BDMA1_Channel0_BASE)

+#define BDMA1_Channel1       ((BDMA_Channel_TypeDef *) BDMA1_Channel1_BASE)

+#define BDMA1_Channel2       ((BDMA_Channel_TypeDef *) BDMA1_Channel2_BASE)

+#define BDMA1_Channel3       ((BDMA_Channel_TypeDef *) BDMA1_Channel3_BASE)

+#define BDMA1_Channel4       ((BDMA_Channel_TypeDef *) BDMA1_Channel4_BASE)

+#define BDMA1_Channel5       ((BDMA_Channel_TypeDef *) BDMA1_Channel5_BASE)

+#define BDMA1_Channel6       ((BDMA_Channel_TypeDef *) BDMA1_Channel6_BASE)

+#define BDMA1_Channel7       ((BDMA_Channel_TypeDef *) BDMA1_Channel7_BASE)

+

+#define BDMA2                ((BDMA_TypeDef *) BDMA2_BASE)

+#define BDMA2_Channel0       ((BDMA_Channel_TypeDef *) BDMA2_Channel0_BASE)

+#define BDMA2_Channel1       ((BDMA_Channel_TypeDef *) BDMA2_Channel1_BASE)

+#define BDMA2_Channel2       ((BDMA_Channel_TypeDef *) BDMA2_Channel2_BASE)

+#define BDMA2_Channel3       ((BDMA_Channel_TypeDef *) BDMA2_Channel3_BASE)

+#define BDMA2_Channel4       ((BDMA_Channel_TypeDef *) BDMA2_Channel4_BASE)

+#define BDMA2_Channel5       ((BDMA_Channel_TypeDef *) BDMA2_Channel5_BASE)

+#define BDMA2_Channel6       ((BDMA_Channel_TypeDef *) BDMA2_Channel6_BASE)

+#define BDMA2_Channel7       ((BDMA_Channel_TypeDef *) BDMA2_Channel7_BASE)

+

+#define RAMECC               ((RAMECC_TypeDef *)RAMECC_BASE)

+#define RAMECC_Monitor1      ((RAMECC_MonitorTypeDef *)RAMECC_Monitor1_BASE)

+#define RAMECC_Monitor2      ((RAMECC_MonitorTypeDef *)RAMECC_Monitor2_BASE)

+#define RAMECC_Monitor3      ((RAMECC_MonitorTypeDef *)RAMECC_Monitor3_BASE)

+

+#define DMAMUX2                ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

+#define DMAMUX2_Channel0       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

+#define DMAMUX2_Channel1       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

+#define DMAMUX2_Channel2       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

+#define DMAMUX2_Channel3       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

+#define DMAMUX2_Channel4       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

+#define DMAMUX2_Channel5       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

+#define DMAMUX2_Channel6       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

+#define DMAMUX2_Channel7       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

+

+

+#define DMAMUX2_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

+#define DMAMUX2_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

+#define DMAMUX2_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

+#define DMAMUX2_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

+#define DMAMUX2_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

+#define DMAMUX2_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

+#define DMAMUX2_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

+#define DMAMUX2_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

+

+#define DMAMUX2_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

+#define DMAMUX2_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

+

+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)

+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

+

+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)

+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

+

+

+#define DMAMUX1              ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

+#define DMAMUX1_Channel0     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

+#define DMAMUX1_Channel1     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

+#define DMAMUX1_Channel2     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

+#define DMAMUX1_Channel3     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

+#define DMAMUX1_Channel4     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

+#define DMAMUX1_Channel5     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

+#define DMAMUX1_Channel6     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

+#define DMAMUX1_Channel7     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

+#define DMAMUX1_Channel8     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

+#define DMAMUX1_Channel9     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

+#define DMAMUX1_Channel10    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

+#define DMAMUX1_Channel11    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

+#define DMAMUX1_Channel12    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

+#define DMAMUX1_Channel13    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

+#define DMAMUX1_Channel14    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

+#define DMAMUX1_Channel15    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

+

+#define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

+#define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

+#define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

+#define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

+#define DMAMUX1_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

+#define DMAMUX1_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

+#define DMAMUX1_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

+#define DMAMUX1_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

+

+#define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *)    DMAMUX1_ChannelStatus_BASE)

+#define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

+

+

+#define FMC_Bank1_R           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

+#define FMC_Bank1E_R          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

+#define FMC_Bank2_R           ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

+#define FMC_Bank3_R           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

+#define FMC_Bank5_6_R         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

+

+#define DAC2                ((DAC_TypeDef *) DAC2_BASE)

+#define OCTOSPI1            ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)

+#define DLYB_OCTOSPI1       ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE)

+#define OCTOSPI2            ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)

+#define DLYB_OCTOSPI2       ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE)

+#define OCTOSPIM            ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)

+#define GFXMMU              ((GFXMMU_TypeDef *) GFXMMU_BASE)

+

+#define SDMMC1                ((SDMMC_TypeDef *) SDMMC1_BASE)

+#define DLYB_SDMMC1           ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

+

+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)

+

+#define JPEG                ((JPEG_TypeDef *) JPGDEC_BASE)

+#define HSEM                ((HSEM_TypeDef *) HSEM_BASE)

+#define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

+

+#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)

+#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

+#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

+

+#define MDIOS               ((MDIOS_TypeDef *) MDIOS_BASE)

+

+#define MDMA                ((MDMA_TypeDef *)MDMA_BASE)

+#define MDMA_Channel0       ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

+#define MDMA_Channel1       ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

+#define MDMA_Channel2       ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

+#define MDMA_Channel3       ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

+#define MDMA_Channel4       ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

+#define MDMA_Channel5       ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

+#define MDMA_Channel6       ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

+#define MDMA_Channel7       ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

+#define MDMA_Channel8       ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

+#define MDMA_Channel9       ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

+#define MDMA_Channel10      ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

+#define MDMA_Channel11      ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

+#define MDMA_Channel12      ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

+#define MDMA_Channel13      ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

+#define MDMA_Channel14      ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

+#define MDMA_Channel15      ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

+

+

+#define USB1_OTG_HS         ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

+

+/* Legacy defines */

+#define USB_OTG_HS                   USB1_OTG_HS

+#define USB_OTG_HS_PERIPH_BASE       USB1_OTG_HS_PERIPH_BASE

+

+/**

+  * @}

+  */

+

+/** @addtogroup Exported_constants

+  * @{

+  */

+

+  /** @addtogroup Peripheral_Registers_Bits_Definition

+  * @{

+  */

+

+/******************************************************************************/

+/*                         Peripheral Registers_Bits_Definition               */

+/******************************************************************************/

+

+/******************************************************************************/

+/*                                                                            */

+/*                        Analog to Digital Converter                         */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  ADC VERSION  ********************************/

+#define ADC_VER_V5_3

+/********************  Bit definition for ADC_ISR register  ********************/

+#define ADC_ISR_ADRDY_Pos                 (0U)

+#define ADC_ISR_ADRDY_Msk                 (0x1UL << ADC_ISR_ADRDY_Pos)         /*!< 0x00000001 */

+#define ADC_ISR_ADRDY                     ADC_ISR_ADRDY_Msk                    /*!< ADC Ready (ADRDY) flag  */

+#define ADC_ISR_EOSMP_Pos                 (1U)

+#define ADC_ISR_EOSMP_Msk                 (0x1UL << ADC_ISR_EOSMP_Pos)         /*!< 0x00000002 */

+#define ADC_ISR_EOSMP                     ADC_ISR_EOSMP_Msk                    /*!< ADC End of Sampling flag */

+#define ADC_ISR_EOC_Pos                   (2U)

+#define ADC_ISR_EOC_Msk                   (0x1UL << ADC_ISR_EOC_Pos)           /*!< 0x00000004 */

+#define ADC_ISR_EOC                       ADC_ISR_EOC_Msk                      /*!< ADC End of Regular Conversion flag */

+#define ADC_ISR_EOS_Pos                   (3U)

+#define ADC_ISR_EOS_Msk                   (0x1UL << ADC_ISR_EOS_Pos)           /*!< 0x00000008 */

+#define ADC_ISR_EOS                       ADC_ISR_EOS_Msk                      /*!< ADC End of Regular sequence of Conversions flag */

+#define ADC_ISR_OVR_Pos                   (4U)

+#define ADC_ISR_OVR_Msk                   (0x1UL << ADC_ISR_OVR_Pos)           /*!< 0x00000010 */

+#define ADC_ISR_OVR                       ADC_ISR_OVR_Msk                      /*!< ADC overrun flag */

+#define ADC_ISR_JEOC_Pos                  (5U)

+#define ADC_ISR_JEOC_Msk                  (0x1UL << ADC_ISR_JEOC_Pos)          /*!< 0x00000020 */

+#define ADC_ISR_JEOC                      ADC_ISR_JEOC_Msk                     /*!< ADC End of Injected Conversion flag */

+#define ADC_ISR_JEOS_Pos                  (6U)

+#define ADC_ISR_JEOS_Msk                  (0x1UL << ADC_ISR_JEOS_Pos)          /*!< 0x00000040 */

+#define ADC_ISR_JEOS                      ADC_ISR_JEOS_Msk                     /*!< ADC End of Injected sequence of Conversions flag */

+#define ADC_ISR_AWD1_Pos                  (7U)

+#define ADC_ISR_AWD1_Msk                  (0x1UL << ADC_ISR_AWD1_Pos)          /*!< 0x00000080 */

+#define ADC_ISR_AWD1                      ADC_ISR_AWD1_Msk                     /*!< ADC Analog watchdog 1 flag */

+#define ADC_ISR_AWD2_Pos                  (8U)

+#define ADC_ISR_AWD2_Msk                  (0x1UL << ADC_ISR_AWD2_Pos)          /*!< 0x00000100 */

+#define ADC_ISR_AWD2                      ADC_ISR_AWD2_Msk                     /*!< ADC Analog watchdog 2 flag */

+#define ADC_ISR_AWD3_Pos                  (9U)

+#define ADC_ISR_AWD3_Msk                  (0x1UL << ADC_ISR_AWD3_Pos)          /*!< 0x00000200 */

+#define ADC_ISR_AWD3                      ADC_ISR_AWD3_Msk                     /*!< ADC Analog watchdog 3 flag */

+#define ADC_ISR_JQOVF_Pos                 (10U)

+#define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */

+#define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */

+

+/********************  Bit definition for ADC_IER register  ********************/

+#define ADC_IER_ADRDYIE_Pos               (0U)

+#define ADC_IER_ADRDYIE_Msk               (0x1UL << ADC_IER_ADRDYIE_Pos)       /*!< 0x00000001 */

+#define ADC_IER_ADRDYIE                   ADC_IER_ADRDYIE_Msk                  /*!< ADC Ready (ADRDY) interrupt source */

+#define ADC_IER_EOSMPIE_Pos               (1U)

+#define ADC_IER_EOSMPIE_Msk               (0x1UL << ADC_IER_EOSMPIE_Pos)       /*!< 0x00000002 */

+#define ADC_IER_EOSMPIE                   ADC_IER_EOSMPIE_Msk                  /*!< ADC End of Sampling interrupt source */

+#define ADC_IER_EOCIE_Pos                 (2U)

+#define ADC_IER_EOCIE_Msk                 (0x1UL << ADC_IER_EOCIE_Pos)         /*!< 0x00000004 */

+#define ADC_IER_EOCIE                     ADC_IER_EOCIE_Msk                    /*!< ADC End of Regular Conversion interrupt source */

+#define ADC_IER_EOSIE_Pos                 (3U)

+#define ADC_IER_EOSIE_Msk                 (0x1UL << ADC_IER_EOSIE_Pos)         /*!< 0x00000008 */

+#define ADC_IER_EOSIE                     ADC_IER_EOSIE_Msk                    /*!< ADC End of Regular sequence of Conversions interrupt source */

+#define ADC_IER_OVRIE_Pos                 (4U)

+#define ADC_IER_OVRIE_Msk                 (0x1UL << ADC_IER_OVRIE_Pos)         /*!< 0x00000010 */

+#define ADC_IER_OVRIE                     ADC_IER_OVRIE_Msk                    /*!< ADC overrun interrupt source */

+#define ADC_IER_JEOCIE_Pos                (5U)

+#define ADC_IER_JEOCIE_Msk                (0x1UL << ADC_IER_JEOCIE_Pos)        /*!< 0x00000020 */

+#define ADC_IER_JEOCIE                    ADC_IER_JEOCIE_Msk                   /*!< ADC End of Injected Conversion interrupt source */

+#define ADC_IER_JEOSIE_Pos                (6U)

+#define ADC_IER_JEOSIE_Msk                (0x1UL << ADC_IER_JEOSIE_Pos)        /*!< 0x00000040 */

+#define ADC_IER_JEOSIE                    ADC_IER_JEOSIE_Msk                   /*!< ADC End of Injected sequence of Conversions interrupt source */

+#define ADC_IER_AWD1IE_Pos                (7U)

+#define ADC_IER_AWD1IE_Msk                (0x1UL << ADC_IER_AWD1IE_Pos)        /*!< 0x00000080 */

+#define ADC_IER_AWD1IE                    ADC_IER_AWD1IE_Msk                   /*!< ADC Analog watchdog 1 interrupt source */

+#define ADC_IER_AWD2IE_Pos                (8U)

+#define ADC_IER_AWD2IE_Msk                (0x1UL << ADC_IER_AWD2IE_Pos)        /*!< 0x00000100 */

+#define ADC_IER_AWD2IE                    ADC_IER_AWD2IE_Msk                   /*!< ADC Analog watchdog 2 interrupt source */

+#define ADC_IER_AWD3IE_Pos                (9U)

+#define ADC_IER_AWD3IE_Msk                (0x1UL << ADC_IER_AWD3IE_Pos)        /*!< 0x00000200 */

+#define ADC_IER_AWD3IE                    ADC_IER_AWD3IE_Msk                   /*!< ADC Analog watchdog 3 interrupt source */

+#define ADC_IER_JQOVFIE_Pos               (10U)

+#define ADC_IER_JQOVFIE_Msk               (0x1UL << ADC_IER_JQOVFIE_Pos)       /*!< 0x00000400 */

+#define ADC_IER_JQOVFIE                   ADC_IER_JQOVFIE_Msk                  /*!< ADC Injected Context Queue Overflow interrupt source */

+

+/********************  Bit definition for ADC_CR register  ********************/

+#define ADC_CR_ADEN_Pos                   (0U)

+#define ADC_CR_ADEN_Msk                   (0x1UL << ADC_CR_ADEN_Pos)           /*!< 0x00000001 */

+#define ADC_CR_ADEN                       ADC_CR_ADEN_Msk                      /*!< ADC Enable control */

+#define ADC_CR_ADDIS_Pos                  (1U)

+#define ADC_CR_ADDIS_Msk                  (0x1UL << ADC_CR_ADDIS_Pos)          /*!< 0x00000002 */

+#define ADC_CR_ADDIS                      ADC_CR_ADDIS_Msk                     /*!< ADC Disable command */

+#define ADC_CR_ADSTART_Pos                (2U)

+#define ADC_CR_ADSTART_Msk                (0x1UL << ADC_CR_ADSTART_Pos)        /*!< 0x00000004 */

+#define ADC_CR_ADSTART                    ADC_CR_ADSTART_Msk                   /*!< ADC Start of Regular conversion */

+#define ADC_CR_JADSTART_Pos               (3U)

+#define ADC_CR_JADSTART_Msk               (0x1UL << ADC_CR_JADSTART_Pos)       /*!< 0x00000008 */

+#define ADC_CR_JADSTART                   ADC_CR_JADSTART_Msk                  /*!< ADC Start of injected conversion */

+#define ADC_CR_ADSTP_Pos                  (4U)

+#define ADC_CR_ADSTP_Msk                  (0x1UL << ADC_CR_ADSTP_Pos)          /*!< 0x00000010 */

+#define ADC_CR_ADSTP                      ADC_CR_ADSTP_Msk                     /*!< ADC Stop of Regular conversion */

+#define ADC_CR_JADSTP_Pos                 (5U)

+#define ADC_CR_JADSTP_Msk                 (0x1UL << ADC_CR_JADSTP_Pos)         /*!< 0x00000020 */

+#define ADC_CR_JADSTP                     ADC_CR_JADSTP_Msk                    /*!< ADC Stop of injected conversion */

+#define ADC_CR_BOOST_Pos                  (8U)

+#define ADC_CR_BOOST_Msk                  (0x3UL << ADC_CR_BOOST_Pos)          /*!< 0x00000300 */

+#define ADC_CR_BOOST                      ADC_CR_BOOST_Msk                     /*!< ADC Boost Mode configuration */

+#define ADC_CR_BOOST_0                    (0x1UL << ADC_CR_BOOST_Pos)           /*!< 0x00000100 */

+#define ADC_CR_BOOST_1                    (0x2UL << ADC_CR_BOOST_Pos)           /*!< 0x00000200 */

+#define ADC_CR_ADCALLIN_Pos               (16U)

+#define ADC_CR_ADCALLIN_Msk               (0x1UL << ADC_CR_ADCALLIN_Pos)       /*!< 0x00010000 */

+#define ADC_CR_ADCALLIN                   ADC_CR_ADCALLIN_Msk                  /*!< ADC Linearity calibration */

+#define ADC_CR_LINCALRDYW1_Pos            (22U)

+#define ADC_CR_LINCALRDYW1_Msk            (0x1UL << ADC_CR_LINCALRDYW1_Pos)    /*!< 0x00400000 */

+#define ADC_CR_LINCALRDYW1                ADC_CR_LINCALRDYW1_Msk               /*!< ADC Linearity calibration ready Word 1 */

+#define ADC_CR_LINCALRDYW2_Pos            (23U)

+#define ADC_CR_LINCALRDYW2_Msk            (0x1UL << ADC_CR_LINCALRDYW2_Pos)    /*!< 0x00800000 */

+#define ADC_CR_LINCALRDYW2                ADC_CR_LINCALRDYW2_Msk               /*!< ADC Linearity calibration ready Word 2 */

+#define ADC_CR_LINCALRDYW3_Pos            (24U)

+#define ADC_CR_LINCALRDYW3_Msk            (0x1UL << ADC_CR_LINCALRDYW3_Pos)    /*!< 0x01000000 */

+#define ADC_CR_LINCALRDYW3                ADC_CR_LINCALRDYW3_Msk               /*!< ADC Linearity calibration ready Word 3 */

+#define ADC_CR_LINCALRDYW4_Pos            (25U)

+#define ADC_CR_LINCALRDYW4_Msk            (0x1UL << ADC_CR_LINCALRDYW4_Pos)    /*!< 0x02000000 */

+#define ADC_CR_LINCALRDYW4                ADC_CR_LINCALRDYW4_Msk               /*!< ADC Linearity calibration ready Word 4 */

+#define ADC_CR_LINCALRDYW5_Pos            (26U)

+#define ADC_CR_LINCALRDYW5_Msk            (0x1UL << ADC_CR_LINCALRDYW5_Pos)    /*!< 0x04000000 */

+#define ADC_CR_LINCALRDYW5                ADC_CR_LINCALRDYW5_Msk               /*!< ADC Linearity calibration ready Word 5 */

+#define ADC_CR_LINCALRDYW6_Pos            (27U)

+#define ADC_CR_LINCALRDYW6_Msk            (0x1UL << ADC_CR_LINCALRDYW6_Pos)    /*!< 0x08000000 */

+#define ADC_CR_LINCALRDYW6                ADC_CR_LINCALRDYW6_Msk               /*!< ADC Linearity calibration ready Word 6 */

+#define ADC_CR_ADVREGEN_Pos               (28U)

+#define ADC_CR_ADVREGEN_Msk               (0x1UL << ADC_CR_ADVREGEN_Pos)       /*!< 0x10000000 */

+#define ADC_CR_ADVREGEN                   ADC_CR_ADVREGEN_Msk                  /*!< ADC Voltage regulator Enable */

+#define ADC_CR_DEEPPWD_Pos                (29U)

+#define ADC_CR_DEEPPWD_Msk                (0x1UL << ADC_CR_DEEPPWD_Pos)        /*!< 0x20000000 */

+#define ADC_CR_DEEPPWD                    ADC_CR_DEEPPWD_Msk                   /*!< ADC Deep power down Enable */

+#define ADC_CR_ADCALDIF_Pos               (30U)

+#define ADC_CR_ADCALDIF_Msk               (0x1UL << ADC_CR_ADCALDIF_Pos)       /*!< 0x40000000 */

+#define ADC_CR_ADCALDIF                   ADC_CR_ADCALDIF_Msk                  /*!< ADC Differential Mode for calibration */

+#define ADC_CR_ADCAL_Pos                  (31U)

+#define ADC_CR_ADCAL_Msk                  (0x1UL << ADC_CR_ADCAL_Pos)          /*!< 0x80000000 */

+#define ADC_CR_ADCAL                      ADC_CR_ADCAL_Msk                     /*!< ADC Calibration */

+

+/********************  Bit definition for ADC_CFGR register  ********************/

+#define ADC_CFGR_DMNGT_Pos                (0U)

+#define ADC_CFGR_DMNGT_Msk                (0x3UL << ADC_CFGR_DMNGT_Pos)        /*!< 0x00000003 */

+#define ADC_CFGR_DMNGT                    ADC_CFGR_DMNGT_Msk                   /*!< ADC Data Management configuration */

+#define ADC_CFGR_DMNGT_0                  (0x1UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000001 */

+#define ADC_CFGR_DMNGT_1                  (0x2UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000002 */

+

+#define ADC_CFGR_RES_Pos                  (2U)

+#define ADC_CFGR_RES_Msk                  (0x7UL << ADC_CFGR_RES_Pos)          /*!< 0x0000001C */

+#define ADC_CFGR_RES                      ADC_CFGR_RES_Msk                     /*!< ADC Data resolution */

+#define ADC_CFGR_RES_0                    (0x1UL << ADC_CFGR_RES_Pos)           /*!< 0x00000004 */

+#define ADC_CFGR_RES_1                    (0x2UL << ADC_CFGR_RES_Pos)           /*!< 0x00000008 */

+#define ADC_CFGR_RES_2                    (0x4UL << ADC_CFGR_RES_Pos)           /*!< 0x00000010 */

+

+#define ADC_CFGR_EXTSEL_Pos               (5U)

+#define ADC_CFGR_EXTSEL_Msk               (0x1FUL << ADC_CFGR_EXTSEL_Pos)      /*!< 0x000003E0 */

+#define ADC_CFGR_EXTSEL                   ADC_CFGR_EXTSEL_Msk                  /*!< ADC External trigger selection for regular group */

+#define ADC_CFGR_EXTSEL_0                 (0x01UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000020 */

+#define ADC_CFGR_EXTSEL_1                 (0x02UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000040 */

+#define ADC_CFGR_EXTSEL_2                 (0x04UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000080 */

+#define ADC_CFGR_EXTSEL_3                 (0x08UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000100 */

+#define ADC_CFGR_EXTSEL_4                 (0x10UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000200 */

+

+#define ADC_CFGR_EXTEN_Pos                (10U)

+#define ADC_CFGR_EXTEN_Msk                (0x3UL << ADC_CFGR_EXTEN_Pos)        /*!< 0x00000C00 */

+#define ADC_CFGR_EXTEN                    ADC_CFGR_EXTEN_Msk                   /*!< ADC External trigger enable and polarity selection for regular channels */

+#define ADC_CFGR_EXTEN_0                  (0x1UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000400 */

+#define ADC_CFGR_EXTEN_1                  (0x2UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000800 */

+

+#define ADC_CFGR_OVRMOD_Pos               (12U)

+#define ADC_CFGR_OVRMOD_Msk               (0x1UL << ADC_CFGR_OVRMOD_Pos)       /*!< 0x00001000 */

+#define ADC_CFGR_OVRMOD                   ADC_CFGR_OVRMOD_Msk                  /*!< ADC overrun mode */

+#define ADC_CFGR_CONT_Pos                 (13U)

+#define ADC_CFGR_CONT_Msk                 (0x1UL << ADC_CFGR_CONT_Pos)         /*!< 0x00002000 */

+#define ADC_CFGR_CONT                     ADC_CFGR_CONT_Msk                    /*!< ADC Single/continuous conversion mode for regular conversion */

+#define ADC_CFGR_AUTDLY_Pos               (14U)

+#define ADC_CFGR_AUTDLY_Msk               (0x1UL << ADC_CFGR_AUTDLY_Pos)       /*!< 0x00004000 */

+#define ADC_CFGR_AUTDLY                   ADC_CFGR_AUTDLY_Msk                  /*!< ADC Delayed conversion mode */

+

+#define ADC_CFGR_DISCEN_Pos               (16U)

+#define ADC_CFGR_DISCEN_Msk               (0x1UL << ADC_CFGR_DISCEN_Pos)       /*!< 0x00010000 */

+#define ADC_CFGR_DISCEN                   ADC_CFGR_DISCEN_Msk                  /*!< ADC Discontinuous mode for regular channels */

+

+#define ADC_CFGR_DISCNUM_Pos              (17U)

+#define ADC_CFGR_DISCNUM_Msk              (0x7UL << ADC_CFGR_DISCNUM_Pos)      /*!< 0x000E0000 */

+#define ADC_CFGR_DISCNUM                  ADC_CFGR_DISCNUM_Msk                 /*!< ADC Discontinuous mode channel count */

+#define ADC_CFGR_DISCNUM_0                (0x1UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00020000 */

+#define ADC_CFGR_DISCNUM_1                (0x2UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00040000 */

+#define ADC_CFGR_DISCNUM_2                (0x4UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00080000 */

+

+#define ADC_CFGR_JDISCEN_Pos              (20U)

+#define ADC_CFGR_JDISCEN_Msk              (0x1UL << ADC_CFGR_JDISCEN_Pos)      /*!< 0x00100000 */

+#define ADC_CFGR_JDISCEN                  ADC_CFGR_JDISCEN_Msk                 /*!< ADC Discontinuous mode on injected channels */

+#define ADC_CFGR_JQM_Pos                  (21U)

+#define ADC_CFGR_JQM_Msk                  (0x1UL << ADC_CFGR_JQM_Pos)          /*!< 0x00200000 */

+#define ADC_CFGR_JQM                      ADC_CFGR_JQM_Msk                     /*!< ADC JSQR Queue mode */

+#define ADC_CFGR_AWD1SGL_Pos              (22U)

+#define ADC_CFGR_AWD1SGL_Msk              (0x1UL << ADC_CFGR_AWD1SGL_Pos)      /*!< 0x00400000 */

+#define ADC_CFGR_AWD1SGL                  ADC_CFGR_AWD1SGL_Msk                 /*!< Enable the watchdog 1 on a single channel or on all channels */

+#define ADC_CFGR_AWD1EN_Pos               (23U)

+#define ADC_CFGR_AWD1EN_Msk               (0x1UL << ADC_CFGR_AWD1EN_Pos)       /*!< 0x00800000 */

+#define ADC_CFGR_AWD1EN                   ADC_CFGR_AWD1EN_Msk                  /*!< ADC Analog watchdog 1 enable on regular Channels */

+#define ADC_CFGR_JAWD1EN_Pos              (24U)

+#define ADC_CFGR_JAWD1EN_Msk              (0x1UL << ADC_CFGR_JAWD1EN_Pos)      /*!< 0x01000000 */

+#define ADC_CFGR_JAWD1EN                  ADC_CFGR_JAWD1EN_Msk                 /*!< ADC Analog watchdog 1 enable on injected Channels */

+#define ADC_CFGR_JAUTO_Pos                (25U)

+#define ADC_CFGR_JAUTO_Msk                (0x1UL << ADC_CFGR_JAUTO_Pos)        /*!< 0x02000000 */

+#define ADC_CFGR_JAUTO                    ADC_CFGR_JAUTO_Msk                   /*!< ADC Automatic injected group conversion */

+

+#define ADC_CFGR_AWD1CH_Pos               (26U)

+#define ADC_CFGR_AWD1CH_Msk               (0x1FUL << ADC_CFGR_AWD1CH_Pos)      /*!< 0x7C000000 */

+#define ADC_CFGR_AWD1CH                   ADC_CFGR_AWD1CH_Msk                  /*!< ADC Analog watchdog 1 Channel selection */

+#define ADC_CFGR_AWD1CH_0                 (0x01UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x04000000 */

+#define ADC_CFGR_AWD1CH_1                 (0x02UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x08000000 */

+#define ADC_CFGR_AWD1CH_2                 (0x04UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x10000000 */

+#define ADC_CFGR_AWD1CH_3                 (0x08UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x20000000 */

+#define ADC_CFGR_AWD1CH_4                 (0x10UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x40000000 */

+

+#define ADC_CFGR_JQDIS_Pos                (31U)

+#define ADC_CFGR_JQDIS_Msk                (0x1UL << ADC_CFGR_JQDIS_Pos)        /*!< 0x80000000 */

+#define ADC_CFGR_JQDIS                    ADC_CFGR_JQDIS_Msk                   /*!< ADC Injected queue disable */

+

+/********************  Bit definition for ADC_CFGR2 register  ********************/

+#define ADC_CFGR2_ROVSE_Pos               (0U)

+#define ADC_CFGR2_ROVSE_Msk               (0x1UL << ADC_CFGR2_ROVSE_Pos)       /*!< 0x00000001 */

+#define ADC_CFGR2_ROVSE                   ADC_CFGR2_ROVSE_Msk                  /*!< ADC Regular group oversampler enable */

+#define ADC_CFGR2_JOVSE_Pos               (1U)

+#define ADC_CFGR2_JOVSE_Msk               (0x1UL << ADC_CFGR2_JOVSE_Pos)       /*!< 0x00000002 */

+#define ADC_CFGR2_JOVSE                   ADC_CFGR2_JOVSE_Msk                  /*!< ADC Injected group oversampler enable */

+

+#define ADC_CFGR2_OVSS_Pos                (5U)

+#define ADC_CFGR2_OVSS_Msk                (0xFUL << ADC_CFGR2_OVSS_Pos)        /*!< 0x000001E0 */

+#define ADC_CFGR2_OVSS                    ADC_CFGR2_OVSS_Msk                   /*!< ADC Regular Oversampling shift */

+#define ADC_CFGR2_OVSS_0                  (0x1UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000020 */

+#define ADC_CFGR2_OVSS_1                  (0x2UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000040 */

+#define ADC_CFGR2_OVSS_2                  (0x4UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000080 */

+#define ADC_CFGR2_OVSS_3                  (0x8UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000100 */

+

+#define ADC_CFGR2_TROVS_Pos               (9U)

+#define ADC_CFGR2_TROVS_Msk               (0x1UL << ADC_CFGR2_TROVS_Pos)       /*!< 0x00000200 */

+#define ADC_CFGR2_TROVS                   ADC_CFGR2_TROVS_Msk                  /*!< ADC Triggered regular Oversampling */

+#define ADC_CFGR2_ROVSM_Pos               (10U)

+#define ADC_CFGR2_ROVSM_Msk               (0x1UL << ADC_CFGR2_ROVSM_Pos)       /*!< 0x00000400 */

+#define ADC_CFGR2_ROVSM                   ADC_CFGR2_ROVSM_Msk                  /*!< ADC Regular oversampling mode */

+

+#define ADC_CFGR2_RSHIFT1_Pos             (11U)

+#define ADC_CFGR2_RSHIFT1_Msk             (0x1UL << ADC_CFGR2_RSHIFT1_Pos)     /*!< 0x00000800 */

+#define ADC_CFGR2_RSHIFT1                 ADC_CFGR2_RSHIFT1_Msk                /*!< ADC Right-shift data after Offset 1 correction */

+#define ADC_CFGR2_RSHIFT2_Pos             (12U)

+#define ADC_CFGR2_RSHIFT2_Msk             (0x1UL << ADC_CFGR2_RSHIFT2_Pos)     /*!< 0x00001000 */

+#define ADC_CFGR2_RSHIFT2                 ADC_CFGR2_RSHIFT2_Msk                /*!< ADC Right-shift data after Offset 2 correction */

+#define ADC_CFGR2_RSHIFT3_Pos             (13U)

+#define ADC_CFGR2_RSHIFT3_Msk             (0x1UL << ADC_CFGR2_RSHIFT3_Pos)     /*!< 0x00002000 */

+#define ADC_CFGR2_RSHIFT3                 ADC_CFGR2_RSHIFT3_Msk                /*!< ADC Right-shift data after Offset 3 correction */

+#define ADC_CFGR2_RSHIFT4_Pos             (14U)

+#define ADC_CFGR2_RSHIFT4_Msk             (0x1UL << ADC_CFGR2_RSHIFT4_Pos)     /*!< 0x00004000 */

+#define ADC_CFGR2_RSHIFT4                 ADC_CFGR2_RSHIFT4_Msk                /*!< ADC Right-shift data after Offset 4 correction */

+

+#define ADC_CFGR2_OVSR_Pos                (16U)

+#define ADC_CFGR2_OVSR_Msk                (0x3FFUL << ADC_CFGR2_OVSR_Pos)      /*!< 0x03FF0000 */

+#define ADC_CFGR2_OVSR                    ADC_CFGR2_OVSR_Msk                   /*!< ADC oversampling Ratio */

+#define ADC_CFGR2_OVSR_0                  (0x001UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00010000 */

+#define ADC_CFGR2_OVSR_1                  (0x002UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00020000 */

+#define ADC_CFGR2_OVSR_2                  (0x004UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00040000 */

+#define ADC_CFGR2_OVSR_3                  (0x008UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00080000 */

+#define ADC_CFGR2_OVSR_4                  (0x010UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00100000 */

+#define ADC_CFGR2_OVSR_5                  (0x020UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00200000 */

+#define ADC_CFGR2_OVSR_6                  (0x040UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00400000 */

+#define ADC_CFGR2_OVSR_7                  (0x080UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00800000 */

+#define ADC_CFGR2_OVSR_8                  (0x100UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x01000000 */

+#define ADC_CFGR2_OVSR_9                  (0x200UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x02000000 */

+

+#define ADC_CFGR2_LSHIFT_Pos              (28U)

+#define ADC_CFGR2_LSHIFT_Msk              (0xFUL << ADC_CFGR2_LSHIFT_Pos)      /*!< 0xF0000000 */

+#define ADC_CFGR2_LSHIFT                  ADC_CFGR2_LSHIFT_Msk                 /*!< ADC Left shift factor */

+#define ADC_CFGR2_LSHIFT_0                (0x1UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x10000000 */

+#define ADC_CFGR2_LSHIFT_1                (0x2UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x20000000 */

+#define ADC_CFGR2_LSHIFT_2                (0x4UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x40000000 */

+#define ADC_CFGR2_LSHIFT_3                (0x8UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_SMPR1 register  ********************/

+#define ADC_SMPR1_SMP0_Pos                (0U)

+#define ADC_SMPR1_SMP0_Msk                (0x7UL << ADC_SMPR1_SMP0_Pos)        /*!< 0x00000007 */

+#define ADC_SMPR1_SMP0                    ADC_SMPR1_SMP0_Msk                   /*!< ADC Channel 0 Sampling time selection  */

+#define ADC_SMPR1_SMP0_0                  (0x1UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000001 */

+#define ADC_SMPR1_SMP0_1                  (0x2UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000002 */

+#define ADC_SMPR1_SMP0_2                  (0x4UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000004 */

+

+#define ADC_SMPR1_SMP1_Pos                (3U)

+#define ADC_SMPR1_SMP1_Msk                (0x7UL << ADC_SMPR1_SMP1_Pos)        /*!< 0x00000038 */

+#define ADC_SMPR1_SMP1                    ADC_SMPR1_SMP1_Msk                   /*!< ADC Channel 1 Sampling time selection  */

+#define ADC_SMPR1_SMP1_0                  (0x1UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000008 */

+#define ADC_SMPR1_SMP1_1                  (0x2UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000010 */

+#define ADC_SMPR1_SMP1_2                  (0x4UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000020 */

+

+#define ADC_SMPR1_SMP2_Pos                (6U)

+#define ADC_SMPR1_SMP2_Msk                (0x7UL << ADC_SMPR1_SMP2_Pos)        /*!< 0x000001C0 */

+#define ADC_SMPR1_SMP2                    ADC_SMPR1_SMP2_Msk                   /*!< ADC Channel 2 Sampling time selection  */

+#define ADC_SMPR1_SMP2_0                  (0x1UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000040 */

+#define ADC_SMPR1_SMP2_1                  (0x2UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000080 */

+#define ADC_SMPR1_SMP2_2                  (0x4UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000100 */

+

+#define ADC_SMPR1_SMP3_Pos                (9U)

+#define ADC_SMPR1_SMP3_Msk                (0x7UL << ADC_SMPR1_SMP3_Pos)        /*!< 0x00000E00 */

+#define ADC_SMPR1_SMP3                    ADC_SMPR1_SMP3_Msk                   /*!< ADC Channel 3 Sampling time selection  */

+#define ADC_SMPR1_SMP3_0                  (0x1UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000200 */

+#define ADC_SMPR1_SMP3_1                  (0x2UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000400 */

+#define ADC_SMPR1_SMP3_2                  (0x4UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000800 */

+

+#define ADC_SMPR1_SMP4_Pos                (12U)

+#define ADC_SMPR1_SMP4_Msk                (0x7UL << ADC_SMPR1_SMP4_Pos)        /*!< 0x00007000 */

+#define ADC_SMPR1_SMP4                    ADC_SMPR1_SMP4_Msk                   /*!< ADC Channel 4 Sampling time selection  */

+#define ADC_SMPR1_SMP4_0                  (0x1UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00001000 */

+#define ADC_SMPR1_SMP4_1                  (0x2UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00002000 */

+#define ADC_SMPR1_SMP4_2                  (0x4UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00004000 */

+

+#define ADC_SMPR1_SMP5_Pos                (15U)

+#define ADC_SMPR1_SMP5_Msk                (0x7UL << ADC_SMPR1_SMP5_Pos)        /*!< 0x00038000 */

+#define ADC_SMPR1_SMP5                    ADC_SMPR1_SMP5_Msk                   /*!< ADC Channel 5 Sampling time selection  */

+#define ADC_SMPR1_SMP5_0                  (0x1UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00008000 */

+#define ADC_SMPR1_SMP5_1                  (0x2UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00010000 */

+#define ADC_SMPR1_SMP5_2                  (0x4UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00020000 */

+

+#define ADC_SMPR1_SMP6_Pos                (18U)

+#define ADC_SMPR1_SMP6_Msk                (0x7UL << ADC_SMPR1_SMP6_Pos)        /*!< 0x001C0000 */

+#define ADC_SMPR1_SMP6                    ADC_SMPR1_SMP6_Msk                   /*!< ADC Channel 6 Sampling time selection  */

+#define ADC_SMPR1_SMP6_0                  (0x1UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00040000 */

+#define ADC_SMPR1_SMP6_1                  (0x2UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00080000 */

+#define ADC_SMPR1_SMP6_2                  (0x4UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00100000 */

+

+#define ADC_SMPR1_SMP7_Pos                (21U)

+#define ADC_SMPR1_SMP7_Msk                (0x7UL << ADC_SMPR1_SMP7_Pos)        /*!< 0x00E00000 */

+#define ADC_SMPR1_SMP7                    ADC_SMPR1_SMP7_Msk                   /*!< ADC Channel 7 Sampling time selection  */

+#define ADC_SMPR1_SMP7_0                  (0x1UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00200000 */

+#define ADC_SMPR1_SMP7_1                  (0x2UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00400000 */

+#define ADC_SMPR1_SMP7_2                  (0x4UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00800000 */

+

+#define ADC_SMPR1_SMP8_Pos                (24U)

+#define ADC_SMPR1_SMP8_Msk                (0x7UL << ADC_SMPR1_SMP8_Pos)        /*!< 0x07000000 */

+#define ADC_SMPR1_SMP8                    ADC_SMPR1_SMP8_Msk                   /*!< ADC Channel 8 Sampling time selection  */

+#define ADC_SMPR1_SMP8_0                  (0x1UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x01000000 */

+#define ADC_SMPR1_SMP8_1                  (0x2UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x02000000 */

+#define ADC_SMPR1_SMP8_2                  (0x4UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x04000000 */

+

+#define ADC_SMPR1_SMP9_Pos                (27U)

+#define ADC_SMPR1_SMP9_Msk                (0x7UL << ADC_SMPR1_SMP9_Pos)        /*!< 0x38000000 */

+#define ADC_SMPR1_SMP9                    ADC_SMPR1_SMP9_Msk                   /*!< ADC Channel 9 Sampling time selection  */

+#define ADC_SMPR1_SMP9_0                  (0x1UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x08000000 */

+#define ADC_SMPR1_SMP9_1                  (0x2UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x10000000 */

+#define ADC_SMPR1_SMP9_2                  (0x4UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x20000000 */

+

+/********************  Bit definition for ADC_SMPR2 register  ********************/

+#define ADC_SMPR2_SMP10_Pos               (0U)

+#define ADC_SMPR2_SMP10_Msk               (0x7UL << ADC_SMPR2_SMP10_Pos)       /*!< 0x00000007 */

+#define ADC_SMPR2_SMP10                   ADC_SMPR2_SMP10_Msk                  /*!< ADC Channel 10 Sampling time selection  */

+#define ADC_SMPR2_SMP10_0                 (0x1UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000001 */

+#define ADC_SMPR2_SMP10_1                 (0x2UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000002 */

+#define ADC_SMPR2_SMP10_2                 (0x4UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000004 */

+

+#define ADC_SMPR2_SMP11_Pos               (3U)

+#define ADC_SMPR2_SMP11_Msk               (0x7UL << ADC_SMPR2_SMP11_Pos)       /*!< 0x00000038 */

+#define ADC_SMPR2_SMP11                   ADC_SMPR2_SMP11_Msk                  /*!< ADC Channel 11 Sampling time selection  */

+#define ADC_SMPR2_SMP11_0                 (0x1UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000008 */

+#define ADC_SMPR2_SMP11_1                 (0x2UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000010 */

+#define ADC_SMPR2_SMP11_2                 (0x4UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000020 */

+

+#define ADC_SMPR2_SMP12_Pos               (6U)

+#define ADC_SMPR2_SMP12_Msk               (0x7UL << ADC_SMPR2_SMP12_Pos)       /*!< 0x000001C0 */

+#define ADC_SMPR2_SMP12                   ADC_SMPR2_SMP12_Msk                  /*!< ADC Channel 12 Sampling time selection  */

+#define ADC_SMPR2_SMP12_0                 (0x1UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000040 */

+#define ADC_SMPR2_SMP12_1                 (0x2UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000080 */

+#define ADC_SMPR2_SMP12_2                 (0x4UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000100 */

+

+#define ADC_SMPR2_SMP13_Pos               (9U)

+#define ADC_SMPR2_SMP13_Msk               (0x7UL << ADC_SMPR2_SMP13_Pos)       /*!< 0x00000E00 */

+#define ADC_SMPR2_SMP13                   ADC_SMPR2_SMP13_Msk                  /*!< ADC Channel 13 Sampling time selection  */

+#define ADC_SMPR2_SMP13_0                 (0x1UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000200 */

+#define ADC_SMPR2_SMP13_1                 (0x2UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000400 */

+#define ADC_SMPR2_SMP13_2                 (0x4UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000800 */

+

+#define ADC_SMPR2_SMP14_Pos               (12U)

+#define ADC_SMPR2_SMP14_Msk               (0x7UL << ADC_SMPR2_SMP14_Pos)       /*!< 0x00007000 */

+#define ADC_SMPR2_SMP14                   ADC_SMPR2_SMP14_Msk                  /*!< ADC Channel 14 Sampling time selection  */

+#define ADC_SMPR2_SMP14_0                 (0x1UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00001000 */

+#define ADC_SMPR2_SMP14_1                 (0x2UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00002000 */

+#define ADC_SMPR2_SMP14_2                 (0x4UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00004000 */

+

+#define ADC_SMPR2_SMP15_Pos               (15U)

+#define ADC_SMPR2_SMP15_Msk               (0x7UL << ADC_SMPR2_SMP15_Pos)       /*!< 0x00038000 */

+#define ADC_SMPR2_SMP15                   ADC_SMPR2_SMP15_Msk                  /*!< ADC Channel 15 Sampling time selection  */

+#define ADC_SMPR2_SMP15_0                 (0x1UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00008000 */

+#define ADC_SMPR2_SMP15_1                 (0x2UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00010000 */

+#define ADC_SMPR2_SMP15_2                 (0x4UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00020000 */

+

+#define ADC_SMPR2_SMP16_Pos               (18U)

+#define ADC_SMPR2_SMP16_Msk               (0x7UL << ADC_SMPR2_SMP16_Pos)       /*!< 0x001C0000 */

+#define ADC_SMPR2_SMP16                   ADC_SMPR2_SMP16_Msk                  /*!< ADC Channel 16 Sampling time selection  */

+#define ADC_SMPR2_SMP16_0                 (0x1UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00040000 */

+#define ADC_SMPR2_SMP16_1                 (0x2UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00080000 */

+#define ADC_SMPR2_SMP16_2                 (0x4UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00100000 */

+

+#define ADC_SMPR2_SMP17_Pos               (21U)

+#define ADC_SMPR2_SMP17_Msk               (0x7UL << ADC_SMPR2_SMP17_Pos)       /*!< 0x00E00000 */

+#define ADC_SMPR2_SMP17                   ADC_SMPR2_SMP17_Msk                  /*!< ADC Channel 17 Sampling time selection  */

+#define ADC_SMPR2_SMP17_0                 (0x1UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00200000 */

+#define ADC_SMPR2_SMP17_1                 (0x2UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00400000 */

+#define ADC_SMPR2_SMP17_2                 (0x4UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00800000 */

+

+#define ADC_SMPR2_SMP18_Pos               (24U)

+#define ADC_SMPR2_SMP18_Msk               (0x7UL << ADC_SMPR2_SMP18_Pos)       /*!< 0x07000000 */

+#define ADC_SMPR2_SMP18                   ADC_SMPR2_SMP18_Msk                  /*!< ADC Channel 18 Sampling time selection  */

+#define ADC_SMPR2_SMP18_0                 (0x1UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x01000000 */

+#define ADC_SMPR2_SMP18_1                 (0x2UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x02000000 */

+#define ADC_SMPR2_SMP18_2                 (0x4UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x04000000 */

+

+#define ADC_SMPR2_SMP19_Pos               (27U)

+#define ADC_SMPR2_SMP19_Msk               (0x7UL << ADC_SMPR2_SMP19_Pos)       /*!< 0x38000000 */

+#define ADC_SMPR2_SMP19                   ADC_SMPR2_SMP19_Msk                  /*!< ADC Channel 19 Sampling time selection  */

+#define ADC_SMPR2_SMP19_0                 (0x1UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x08000000 */

+#define ADC_SMPR2_SMP19_1                 (0x2UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x10000000 */

+#define ADC_SMPR2_SMP19_2                 (0x4UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x20000000 */

+

+/********************  Bit definition for ADC_PCSEL register  ********************/

+#define ADC_PCSEL_PCSEL_Pos               (0U)

+#define ADC_PCSEL_PCSEL_Msk               (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)   /*!< 0x000FFFFF */

+#define ADC_PCSEL_PCSEL                   ADC_PCSEL_PCSEL_Msk                  /*!< ADC pre channel selection */

+#define ADC_PCSEL_PCSEL_0                 (0x00001UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */

+#define ADC_PCSEL_PCSEL_1                 (0x00002UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */

+#define ADC_PCSEL_PCSEL_2                 (0x00004UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */

+#define ADC_PCSEL_PCSEL_3                 (0x00008UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */

+#define ADC_PCSEL_PCSEL_4                 (0x00010UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */

+#define ADC_PCSEL_PCSEL_5                 (0x00020UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */

+#define ADC_PCSEL_PCSEL_6                 (0x00040UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */

+#define ADC_PCSEL_PCSEL_7                 (0x00080UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */

+#define ADC_PCSEL_PCSEL_8                 (0x00100UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */

+#define ADC_PCSEL_PCSEL_9                 (0x00200UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */

+#define ADC_PCSEL_PCSEL_10                (0x00400UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */

+#define ADC_PCSEL_PCSEL_11                (0x00800UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */

+#define ADC_PCSEL_PCSEL_12                (0x01000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */

+#define ADC_PCSEL_PCSEL_13                (0x02000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */

+#define ADC_PCSEL_PCSEL_14                (0x04000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */

+#define ADC_PCSEL_PCSEL_15                (0x08000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */

+#define ADC_PCSEL_PCSEL_16                (0x10000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */

+#define ADC_PCSEL_PCSEL_17                (0x20000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */

+#define ADC_PCSEL_PCSEL_18                (0x40000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */

+#define ADC_PCSEL_PCSEL_19                (0x80000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00080000 */

+

+/*****************  Bit definition for ADC_LTR1, 2, 3 registers *****************/

+#define ADC_LTR_LT_Pos                    (0U)

+#define ADC_LTR_LT_Msk                    (0x3FFFFFFUL << ADC_LTR_LT_Pos)      /*!< 0x03FFFFFF */

+#define ADC_LTR_LT                        ADC_LTR_LT_Msk                       /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */

+

+/*****************  Bit definition for ADC_HTR1, 2, 3 registers  ****************/

+#define ADC_HTR_HT_Pos                    (0U)

+#define ADC_HTR_HT_Msk                    (0x3FFFFFFUL << ADC_HTR_HT_Pos)      /*!< 0x03FFFFFF */

+#define ADC_HTR_HT                        ADC_HTR_HT_Msk                       /*!< ADC Analog watchdog 1,2 and 3 higher threshold */

+

+

+/********************  Bit definition for ADC_SQR1 register  ********************/

+#define ADC_SQR1_L_Pos                    (0U)

+#define ADC_SQR1_L_Msk                    (0xFUL << ADC_SQR1_L_Pos)            /*!< 0x0000000F */

+#define ADC_SQR1_L                        ADC_SQR1_L_Msk                       /*!< ADC regular channel sequence lenght */

+#define ADC_SQR1_L_0                      (0x1UL << ADC_SQR1_L_Pos)             /*!< 0x00000001 */

+#define ADC_SQR1_L_1                      (0x2UL << ADC_SQR1_L_Pos)             /*!< 0x00000002 */

+#define ADC_SQR1_L_2                      (0x4UL << ADC_SQR1_L_Pos)             /*!< 0x00000004 */

+#define ADC_SQR1_L_3                      (0x8UL << ADC_SQR1_L_Pos)             /*!< 0x00000008 */

+

+#define ADC_SQR1_SQ1_Pos                  (6U)

+#define ADC_SQR1_SQ1_Msk                  (0x1FUL << ADC_SQR1_SQ1_Pos)         /*!< 0x000007C0 */

+#define ADC_SQR1_SQ1                      ADC_SQR1_SQ1_Msk                     /*!< ADC 1st conversion in regular sequence */

+#define ADC_SQR1_SQ1_0                    (0x01UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000040 */

+#define ADC_SQR1_SQ1_1                    (0x02UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000080 */

+#define ADC_SQR1_SQ1_2                    (0x04UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000100 */

+#define ADC_SQR1_SQ1_3                    (0x08UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000200 */

+#define ADC_SQR1_SQ1_4                    (0x10UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000400 */

+

+#define ADC_SQR1_SQ2_Pos                  (12U)

+#define ADC_SQR1_SQ2_Msk                  (0x1FUL << ADC_SQR1_SQ2_Pos)         /*!< 0x0001F000 */

+#define ADC_SQR1_SQ2                      ADC_SQR1_SQ2_Msk                     /*!< ADC 2nd conversion in regular sequence */

+#define ADC_SQR1_SQ2_0                    (0x01UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00001000 */

+#define ADC_SQR1_SQ2_1                    (0x02UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00002000 */

+#define ADC_SQR1_SQ2_2                    (0x04UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00004000 */

+#define ADC_SQR1_SQ2_3                    (0x08UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00008000 */

+#define ADC_SQR1_SQ2_4                    (0x10UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00010000 */

+

+#define ADC_SQR1_SQ3_Pos                  (18U)

+#define ADC_SQR1_SQ3_Msk                  (0x1FUL << ADC_SQR1_SQ3_Pos)         /*!< 0x007C0000 */

+#define ADC_SQR1_SQ3                      ADC_SQR1_SQ3_Msk                     /*!< ADC 3rd conversion in regular sequence */

+#define ADC_SQR1_SQ3_0                    (0x01UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00040000 */

+#define ADC_SQR1_SQ3_1                    (0x02UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00080000 */

+#define ADC_SQR1_SQ3_2                    (0x04UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00100000 */

+#define ADC_SQR1_SQ3_3                    (0x08UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00200000 */

+#define ADC_SQR1_SQ3_4                    (0x10UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00400000 */

+

+#define ADC_SQR1_SQ4_Pos                  (24U)

+#define ADC_SQR1_SQ4_Msk                  (0x1FUL << ADC_SQR1_SQ4_Pos)         /*!< 0x1F000000 */

+#define ADC_SQR1_SQ4                      ADC_SQR1_SQ4_Msk                     /*!< ADC 4th conversion in regular sequence */

+#define ADC_SQR1_SQ4_0                    (0x01UL << ADC_SQR1_SQ4_Pos)          /*!< 0x01000000 */

+#define ADC_SQR1_SQ4_1                    (0x02UL << ADC_SQR1_SQ4_Pos)          /*!< 0x02000000 */

+#define ADC_SQR1_SQ4_2                    (0x04UL << ADC_SQR1_SQ4_Pos)          /*!< 0x04000000 */

+#define ADC_SQR1_SQ4_3                    (0x08UL << ADC_SQR1_SQ4_Pos)          /*!< 0x08000000 */

+#define ADC_SQR1_SQ4_4                    (0x10UL << ADC_SQR1_SQ4_Pos)          /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR2 register  ********************/

+#define ADC_SQR2_SQ5_Pos                  (0U)

+#define ADC_SQR2_SQ5_Msk                  (0x1FUL << ADC_SQR2_SQ5_Pos)         /*!< 0x0000001F */

+#define ADC_SQR2_SQ5                      ADC_SQR2_SQ5_Msk                     /*!< ADC 5th conversion in regular sequence */

+#define ADC_SQR2_SQ5_0                    (0x01UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000001 */

+#define ADC_SQR2_SQ5_1                    (0x02UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000002 */

+#define ADC_SQR2_SQ5_2                    (0x04UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000004 */

+#define ADC_SQR2_SQ5_3                    (0x08UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000008 */

+#define ADC_SQR2_SQ5_4                    (0x10UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000010 */

+

+#define ADC_SQR2_SQ6_Pos                  (6U)

+#define ADC_SQR2_SQ6_Msk                  (0x1FUL << ADC_SQR2_SQ6_Pos)         /*!< 0x000007C0 */

+#define ADC_SQR2_SQ6                      ADC_SQR2_SQ6_Msk                     /*!< ADC 6th conversion in regular sequence */

+#define ADC_SQR2_SQ6_0                    (0x01UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000040 */

+#define ADC_SQR2_SQ6_1                    (0x02UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000080 */

+#define ADC_SQR2_SQ6_2                    (0x04UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000100 */

+#define ADC_SQR2_SQ6_3                    (0x08UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000200 */

+#define ADC_SQR2_SQ6_4                    (0x10UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000400 */

+

+#define ADC_SQR2_SQ7_Pos                  (12U)

+#define ADC_SQR2_SQ7_Msk                  (0x1FUL << ADC_SQR2_SQ7_Pos)         /*!< 0x0001F000 */

+#define ADC_SQR2_SQ7                      ADC_SQR2_SQ7_Msk                     /*!< ADC 7th conversion in regular sequence */

+#define ADC_SQR2_SQ7_0                    (0x01UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00001000 */

+#define ADC_SQR2_SQ7_1                    (0x02UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00002000 */

+#define ADC_SQR2_SQ7_2                    (0x04UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00004000 */

+#define ADC_SQR2_SQ7_3                    (0x08UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00008000 */

+#define ADC_SQR2_SQ7_4                    (0x10UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00010000 */

+

+#define ADC_SQR2_SQ8_Pos                  (18U)

+#define ADC_SQR2_SQ8_Msk                  (0x1FUL << ADC_SQR2_SQ8_Pos)         /*!< 0x007C0000 */

+#define ADC_SQR2_SQ8                      ADC_SQR2_SQ8_Msk                     /*!< ADC 8th conversion in regular sequence */

+#define ADC_SQR2_SQ8_0                    (0x01UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00040000 */

+#define ADC_SQR2_SQ8_1                    (0x02UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00080000 */

+#define ADC_SQR2_SQ8_2                    (0x04UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00100000 */

+#define ADC_SQR2_SQ8_3                    (0x08UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00200000 */

+#define ADC_SQR2_SQ8_4                    (0x10UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00400000 */

+

+#define ADC_SQR2_SQ9_Pos                  (24U)

+#define ADC_SQR2_SQ9_Msk                  (0x1FUL << ADC_SQR2_SQ9_Pos)         /*!< 0x1F000000 */

+#define ADC_SQR2_SQ9                      ADC_SQR2_SQ9_Msk                     /*!< ADC 9th conversion in regular sequence */

+#define ADC_SQR2_SQ9_0                    (0x01UL << ADC_SQR2_SQ9_Pos)          /*!< 0x01000000 */

+#define ADC_SQR2_SQ9_1                    (0x02UL << ADC_SQR2_SQ9_Pos)          /*!< 0x02000000 */

+#define ADC_SQR2_SQ9_2                    (0x04UL << ADC_SQR2_SQ9_Pos)          /*!< 0x04000000 */

+#define ADC_SQR2_SQ9_3                    (0x08UL << ADC_SQR2_SQ9_Pos)          /*!< 0x08000000 */

+#define ADC_SQR2_SQ9_4                    (0x10UL << ADC_SQR2_SQ9_Pos)          /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR3 register  ********************/

+#define ADC_SQR3_SQ10_Pos                 (0U)

+#define ADC_SQR3_SQ10_Msk                 (0x1FUL << ADC_SQR3_SQ10_Pos)        /*!< 0x0000001F */

+#define ADC_SQR3_SQ10                     ADC_SQR3_SQ10_Msk                    /*!< ADC 10th conversion in regular sequence */

+#define ADC_SQR3_SQ10_0                   (0x01UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000001 */

+#define ADC_SQR3_SQ10_1                   (0x02UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000002 */

+#define ADC_SQR3_SQ10_2                   (0x04UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000004 */

+#define ADC_SQR3_SQ10_3                   (0x08UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000008 */

+#define ADC_SQR3_SQ10_4                   (0x10UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000010 */

+

+#define ADC_SQR3_SQ11_Pos                 (6U)

+#define ADC_SQR3_SQ11_Msk                 (0x1FUL << ADC_SQR3_SQ11_Pos)        /*!< 0x000007C0 */

+#define ADC_SQR3_SQ11                     ADC_SQR3_SQ11_Msk                    /*!< ADC 11th conversion in regular sequence */

+#define ADC_SQR3_SQ11_0                   (0x01UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000040 */

+#define ADC_SQR3_SQ11_1                   (0x02UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000080 */

+#define ADC_SQR3_SQ11_2                   (0x04UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000100 */

+#define ADC_SQR3_SQ11_3                   (0x08UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000200 */

+#define ADC_SQR3_SQ11_4                   (0x10UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000400 */

+

+#define ADC_SQR3_SQ12_Pos                 (12U)

+#define ADC_SQR3_SQ12_Msk                 (0x1FUL << ADC_SQR3_SQ12_Pos)        /*!< 0x0001F000 */

+#define ADC_SQR3_SQ12                     ADC_SQR3_SQ12_Msk                    /*!< ADC 12th conversion in regular sequence */

+#define ADC_SQR3_SQ12_0                   (0x01UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00001000 */

+#define ADC_SQR3_SQ12_1                   (0x02UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00002000 */

+#define ADC_SQR3_SQ12_2                   (0x04UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00004000 */

+#define ADC_SQR3_SQ12_3                   (0x08UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00008000 */

+#define ADC_SQR3_SQ12_4                   (0x10UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00010000 */

+

+#define ADC_SQR3_SQ13_Pos                 (18U)

+#define ADC_SQR3_SQ13_Msk                 (0x1FUL << ADC_SQR3_SQ13_Pos)        /*!< 0x007C0000 */

+#define ADC_SQR3_SQ13                     ADC_SQR3_SQ13_Msk                    /*!< ADC 13th conversion in regular sequence */

+#define ADC_SQR3_SQ13_0                   (0x01UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00040000 */

+#define ADC_SQR3_SQ13_1                   (0x02UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00080000 */

+#define ADC_SQR3_SQ13_2                   (0x04UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00100000 */

+#define ADC_SQR3_SQ13_3                   (0x08UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00200000 */

+#define ADC_SQR3_SQ13_4                   (0x10UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00400000 */

+

+#define ADC_SQR3_SQ14_Pos                 (24U)

+#define ADC_SQR3_SQ14_Msk                 (0x1FUL << ADC_SQR3_SQ14_Pos)        /*!< 0x1F000000 */

+#define ADC_SQR3_SQ14                     ADC_SQR3_SQ14_Msk                    /*!< ADC 14th conversion in regular sequence */

+#define ADC_SQR3_SQ14_0                   (0x01UL << ADC_SQR3_SQ14_Pos)         /*!< 0x01000000 */

+#define ADC_SQR3_SQ14_1                   (0x02UL << ADC_SQR3_SQ14_Pos)         /*!< 0x02000000 */

+#define ADC_SQR3_SQ14_2                   (0x04UL << ADC_SQR3_SQ14_Pos)         /*!< 0x04000000 */

+#define ADC_SQR3_SQ14_3                   (0x08UL << ADC_SQR3_SQ14_Pos)         /*!< 0x08000000 */

+#define ADC_SQR3_SQ14_4                   (0x10UL << ADC_SQR3_SQ14_Pos)         /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR4 register  ********************/

+#define ADC_SQR4_SQ15_Pos                 (0U)

+#define ADC_SQR4_SQ15_Msk                 (0x1FUL << ADC_SQR4_SQ15_Pos)        /*!< 0x0000001F */

+#define ADC_SQR4_SQ15                     ADC_SQR4_SQ15_Msk                    /*!< ADC 15th conversion in regular sequence */

+#define ADC_SQR4_SQ15_0                   (0x01UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000001 */

+#define ADC_SQR4_SQ15_1                   (0x02UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000002 */

+#define ADC_SQR4_SQ15_2                   (0x04UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000004 */

+#define ADC_SQR4_SQ15_3                   (0x08UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000008 */

+#define ADC_SQR4_SQ15_4                   (0x10UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000010 */

+

+#define ADC_SQR4_SQ16_Pos                 (6U)

+#define ADC_SQR4_SQ16_Msk                 (0x1FUL << ADC_SQR4_SQ16_Pos)        /*!< 0x000007C0 */

+#define ADC_SQR4_SQ16                     ADC_SQR4_SQ16_Msk                    /*!< ADC 16th conversion in regular sequence */

+#define ADC_SQR4_SQ16_0                   (0x01UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000040 */

+#define ADC_SQR4_SQ16_1                   (0x02UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000080 */

+#define ADC_SQR4_SQ16_2                   (0x04UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000100 */

+#define ADC_SQR4_SQ16_3                   (0x08UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000200 */

+#define ADC_SQR4_SQ16_4                   (0x10UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000400 */

+/********************  Bit definition for ADC_DR register  ********************/

+#define ADC_DR_RDATA_Pos                  (0U)

+#define ADC_DR_RDATA_Msk                  (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)   /*!< 0xFFFFFFFF */

+#define ADC_DR_RDATA                      ADC_DR_RDATA_Msk                     /*!< ADC regular Data converted */

+

+/********************  Bit definition for ADC_JSQR register  ********************/

+#define ADC_JSQR_JL_Pos                   (0U)

+#define ADC_JSQR_JL_Msk                   (0x3UL << ADC_JSQR_JL_Pos)           /*!< 0x00000003 */

+#define ADC_JSQR_JL                       ADC_JSQR_JL_Msk                      /*!< ADC injected channel sequence length */

+#define ADC_JSQR_JL_0                     (0x1UL << ADC_JSQR_JL_Pos)           /*!< 0x00000001 */

+#define ADC_JSQR_JL_1                     (0x2UL << ADC_JSQR_JL_Pos)           /*!< 0x00000002 */

+

+#define ADC_JSQR_JEXTSEL_Pos              (2U)

+#define ADC_JSQR_JEXTSEL_Msk              (0x1FUL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x0000007C */

+#define ADC_JSQR_JEXTSEL                  ADC_JSQR_JEXTSEL_Msk                 /*!< ADC external trigger selection for injected group */

+#define ADC_JSQR_JEXTSEL_0                (0x01UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000004 */

+#define ADC_JSQR_JEXTSEL_1                (0x02UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000008 */

+#define ADC_JSQR_JEXTSEL_2                (0x04UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000010 */

+#define ADC_JSQR_JEXTSEL_3                (0x08UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000020 */

+#define ADC_JSQR_JEXTSEL_4                (0x10UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000040 */

+

+#define ADC_JSQR_JEXTEN_Pos               (7U)

+#define ADC_JSQR_JEXTEN_Msk               (0x3UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000180 */

+#define ADC_JSQR_JEXTEN                   ADC_JSQR_JEXTEN_Msk                  /*!< ADC external trigger enable and polarity selection for injected channels */

+#define ADC_JSQR_JEXTEN_0                 (0x1UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000080 */

+#define ADC_JSQR_JEXTEN_1                 (0x2UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000100 */

+

+#define ADC_JSQR_JSQ1_Pos                 (9U)

+#define ADC_JSQR_JSQ1_Msk                 (0x1FUL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00003E00 */

+#define ADC_JSQR_JSQ1                     ADC_JSQR_JSQ1_Msk                    /*!< ADC 1st conversion in injected sequence */

+#define ADC_JSQR_JSQ1_0                   (0x01UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000200 */

+#define ADC_JSQR_JSQ1_1                   (0x02UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000400 */

+#define ADC_JSQR_JSQ1_2                   (0x04UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000800 */

+#define ADC_JSQR_JSQ1_3                   (0x08UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00001000 */

+#define ADC_JSQR_JSQ1_4                   (0x10UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00002000 */

+

+#define ADC_JSQR_JSQ2_Pos                 (15U)

+#define ADC_JSQR_JSQ2_Msk                 (0x1FUL << ADC_JSQR_JSQ2_Pos)        /*!< 0x000F8000 */

+#define ADC_JSQR_JSQ2                     ADC_JSQR_JSQ2_Msk                    /*!< ADC 2nd conversion in injected sequence */

+#define ADC_JSQR_JSQ2_0                   (0x01UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00008000 */

+#define ADC_JSQR_JSQ2_1                   (0x02UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00010000 */

+#define ADC_JSQR_JSQ2_2                   (0x04UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00020000 */

+#define ADC_JSQR_JSQ2_3                   (0x08UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00040000 */

+#define ADC_JSQR_JSQ2_4                   (0x10UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00080000 */

+

+#define ADC_JSQR_JSQ3_Pos                 (21U)

+#define ADC_JSQR_JSQ3_Msk                 (0x1FUL << ADC_JSQR_JSQ3_Pos)        /*!< 0x03E00000 */

+#define ADC_JSQR_JSQ3                     ADC_JSQR_JSQ3_Msk                    /*!< ADC 3rd conversion in injected sequence */

+#define ADC_JSQR_JSQ3_0                   (0x01UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00200000 */

+#define ADC_JSQR_JSQ3_1                   (0x02UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00400000 */

+#define ADC_JSQR_JSQ3_2                   (0x04UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00800000 */

+#define ADC_JSQR_JSQ3_3                   (0x08UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x01000000 */

+#define ADC_JSQR_JSQ3_4                   (0x10UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x02000000 */

+

+#define ADC_JSQR_JSQ4_Pos                 (27U)

+#define ADC_JSQR_JSQ4_Msk                 (0x1FUL << ADC_JSQR_JSQ4_Pos)        /*!< 0xF8000000 */

+#define ADC_JSQR_JSQ4                     ADC_JSQR_JSQ4_Msk                    /*!< ADC 4th conversion in injected sequence */

+#define ADC_JSQR_JSQ4_0                   (0x01UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x08000000 */

+#define ADC_JSQR_JSQ4_1                   (0x02UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x10000000 */

+#define ADC_JSQR_JSQ4_2                   (0x04UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x20000000 */

+#define ADC_JSQR_JSQ4_3                   (0x08UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x40000000 */

+#define ADC_JSQR_JSQ4_4                   (0x10UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_OFR1 register  ********************/

+#define ADC_OFR1_OFFSET1_Pos              (0U)

+#define ADC_OFR1_OFFSET1_Msk              (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR1_OFFSET1                  ADC_OFR1_OFFSET1_Msk                  /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */

+#define ADC_OFR1_OFFSET1_0                (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */

+#define ADC_OFR1_OFFSET1_1                (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */

+#define ADC_OFR1_OFFSET1_2                (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */

+#define ADC_OFR1_OFFSET1_3                (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */

+#define ADC_OFR1_OFFSET1_4                (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */

+#define ADC_OFR1_OFFSET1_5                (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */

+#define ADC_OFR1_OFFSET1_6                (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */

+#define ADC_OFR1_OFFSET1_7                (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */

+#define ADC_OFR1_OFFSET1_8                (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */

+#define ADC_OFR1_OFFSET1_9                (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */

+#define ADC_OFR1_OFFSET1_10               (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */

+#define ADC_OFR1_OFFSET1_11               (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */

+#define ADC_OFR1_OFFSET1_12               (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */

+#define ADC_OFR1_OFFSET1_13               (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */

+#define ADC_OFR1_OFFSET1_14               (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */

+#define ADC_OFR1_OFFSET1_15               (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */

+#define ADC_OFR1_OFFSET1_16               (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */

+#define ADC_OFR1_OFFSET1_17               (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */

+#define ADC_OFR1_OFFSET1_18               (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */

+#define ADC_OFR1_OFFSET1_19               (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */

+#define ADC_OFR1_OFFSET1_20               (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */

+#define ADC_OFR1_OFFSET1_21               (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */

+#define ADC_OFR1_OFFSET1_22               (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */

+#define ADC_OFR1_OFFSET1_23               (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */

+#define ADC_OFR1_OFFSET1_24               (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */

+#define ADC_OFR1_OFFSET1_25               (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR1_OFFSET1_CH_Pos           (26U)

+#define ADC_OFR1_OFFSET1_CH_Msk           (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR1_OFFSET1_CH               ADC_OFR1_OFFSET1_CH_Msk               /*!< ADC Channel selection for the data offset 1 */

+#define ADC_OFR1_OFFSET1_CH_0             (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR1_OFFSET1_CH_1             (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR1_OFFSET1_CH_2             (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR1_OFFSET1_CH_3             (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR1_OFFSET1_CH_4             (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR1_SSATE_Pos                (31U)

+#define ADC_OFR1_SSATE_Msk                (0x1UL << ADC_OFR1_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR1_SSATE                    ADC_OFR1_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR2 register  ********************/

+#define ADC_OFR2_OFFSET2_Pos              (0U)

+#define ADC_OFR2_OFFSET2_Msk              (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR2_OFFSET2                  ADC_OFR2_OFFSET2_Msk                  /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */

+#define ADC_OFR2_OFFSET2_0                (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */

+#define ADC_OFR2_OFFSET2_1                (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */

+#define ADC_OFR2_OFFSET2_2                (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */

+#define ADC_OFR2_OFFSET2_3                (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */

+#define ADC_OFR2_OFFSET2_4                (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */

+#define ADC_OFR2_OFFSET2_5                (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */

+#define ADC_OFR2_OFFSET2_6                (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */

+#define ADC_OFR2_OFFSET2_7                (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */

+#define ADC_OFR2_OFFSET2_8                (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */

+#define ADC_OFR2_OFFSET2_9                (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */

+#define ADC_OFR2_OFFSET2_10               (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */

+#define ADC_OFR2_OFFSET2_11               (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */

+#define ADC_OFR2_OFFSET2_12               (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */

+#define ADC_OFR2_OFFSET2_13               (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */

+#define ADC_OFR2_OFFSET2_14               (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */

+#define ADC_OFR2_OFFSET2_15               (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */

+#define ADC_OFR2_OFFSET2_16               (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */

+#define ADC_OFR2_OFFSET2_17               (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */

+#define ADC_OFR2_OFFSET2_18               (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */

+#define ADC_OFR2_OFFSET2_19               (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */

+#define ADC_OFR2_OFFSET2_20               (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */

+#define ADC_OFR2_OFFSET2_21               (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */

+#define ADC_OFR2_OFFSET2_22               (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */

+#define ADC_OFR2_OFFSET2_23               (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */

+#define ADC_OFR2_OFFSET2_24               (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */

+#define ADC_OFR2_OFFSET2_25               (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR2_OFFSET2_CH_Pos           (26U)

+#define ADC_OFR2_OFFSET2_CH_Msk           (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR2_OFFSET2_CH               ADC_OFR2_OFFSET2_CH_Msk               /*!< ADC Channel selection for the data offset 2 */

+#define ADC_OFR2_OFFSET2_CH_0             (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR2_OFFSET2_CH_1             (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR2_OFFSET2_CH_2             (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR2_OFFSET2_CH_3             (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR2_OFFSET2_CH_4             (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR2_SSATE_Pos                (31U)

+#define ADC_OFR2_SSATE_Msk                (0x1UL << ADC_OFR2_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR2_SSATE                    ADC_OFR2_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR3 register  ********************/

+#define ADC_OFR3_OFFSET3_Pos              (0U)

+#define ADC_OFR3_OFFSET3_Msk              (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR3_OFFSET3                  ADC_OFR3_OFFSET3_Msk                  /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */

+#define ADC_OFR3_OFFSET3_0                (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */

+#define ADC_OFR3_OFFSET3_1                (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */

+#define ADC_OFR3_OFFSET3_2                (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */

+#define ADC_OFR3_OFFSET3_3                (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */

+#define ADC_OFR3_OFFSET3_4                (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */

+#define ADC_OFR3_OFFSET3_5                (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */

+#define ADC_OFR3_OFFSET3_6                (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */

+#define ADC_OFR3_OFFSET3_7                (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */

+#define ADC_OFR3_OFFSET3_8                (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */

+#define ADC_OFR3_OFFSET3_9                (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */

+#define ADC_OFR3_OFFSET3_10               (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */

+#define ADC_OFR3_OFFSET3_11               (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */

+#define ADC_OFR3_OFFSET3_12               (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */

+#define ADC_OFR3_OFFSET3_13               (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */

+#define ADC_OFR3_OFFSET3_14               (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */

+#define ADC_OFR3_OFFSET3_15               (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */

+#define ADC_OFR3_OFFSET3_16               (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */

+#define ADC_OFR3_OFFSET3_17               (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */

+#define ADC_OFR3_OFFSET3_18               (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */

+#define ADC_OFR3_OFFSET3_19               (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */

+#define ADC_OFR3_OFFSET3_20               (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */

+#define ADC_OFR3_OFFSET3_21               (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */

+#define ADC_OFR3_OFFSET3_22               (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */

+#define ADC_OFR3_OFFSET3_23               (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */

+#define ADC_OFR3_OFFSET3_24               (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */

+#define ADC_OFR3_OFFSET3_25               (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR3_OFFSET3_CH_Pos           (26U)

+#define ADC_OFR3_OFFSET3_CH_Msk           (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR3_OFFSET3_CH               ADC_OFR3_OFFSET3_CH_Msk               /*!< ADC Channel selection for the data offset 3 */

+#define ADC_OFR3_OFFSET3_CH_0             (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR3_OFFSET3_CH_1             (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR3_OFFSET3_CH_2             (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR3_OFFSET3_CH_3             (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR3_OFFSET3_CH_4             (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR3_SSATE_Pos                (31U)

+#define ADC_OFR3_SSATE_Msk                (0x1UL << ADC_OFR3_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR3_SSATE                    ADC_OFR3_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR4 register  ********************/

+#define ADC_OFR4_OFFSET4_Pos              (0U)

+#define ADC_OFR4_OFFSET4_Msk              (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR4_OFFSET4                  ADC_OFR4_OFFSET4_Msk                  /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */

+#define ADC_OFR4_OFFSET4_0                (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */

+#define ADC_OFR4_OFFSET4_1                (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */

+#define ADC_OFR4_OFFSET4_2                (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */

+#define ADC_OFR4_OFFSET4_3                (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */

+#define ADC_OFR4_OFFSET4_4                (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */

+#define ADC_OFR4_OFFSET4_5                (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */

+#define ADC_OFR4_OFFSET4_6                (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */

+#define ADC_OFR4_OFFSET4_7                (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */

+#define ADC_OFR4_OFFSET4_8                (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */

+#define ADC_OFR4_OFFSET4_9                (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */

+#define ADC_OFR4_OFFSET4_10               (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */

+#define ADC_OFR4_OFFSET4_11               (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */

+#define ADC_OFR4_OFFSET4_12               (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */

+#define ADC_OFR4_OFFSET4_13               (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */

+#define ADC_OFR4_OFFSET4_14               (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */

+#define ADC_OFR4_OFFSET4_15               (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */

+#define ADC_OFR4_OFFSET4_16               (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */

+#define ADC_OFR4_OFFSET4_17               (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */

+#define ADC_OFR4_OFFSET4_18               (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */

+#define ADC_OFR4_OFFSET4_19               (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */

+#define ADC_OFR4_OFFSET4_20               (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */

+#define ADC_OFR4_OFFSET4_21               (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */

+#define ADC_OFR4_OFFSET4_22               (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */

+#define ADC_OFR4_OFFSET4_23               (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */

+#define ADC_OFR4_OFFSET4_24               (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */

+#define ADC_OFR4_OFFSET4_25               (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR4_OFFSET4_CH_Pos           (26U)

+#define ADC_OFR4_OFFSET4_CH_Msk           (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR4_OFFSET4_CH               ADC_OFR4_OFFSET4_CH_Msk               /*!< ADC Channel selection for the data offset 4 */

+#define ADC_OFR4_OFFSET4_CH_0             (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR4_OFFSET4_CH_1             (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR4_OFFSET4_CH_2             (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR4_OFFSET4_CH_3             (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR4_OFFSET4_CH_4             (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR4_SSATE_Pos                (31U)

+#define ADC_OFR4_SSATE_Msk                (0x1UL << ADC_OFR4_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR4_SSATE                    ADC_OFR4_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_JDR1 register  ********************/

+#define ADC_JDR1_JDATA_Pos                (0U)

+#define ADC_JDR1_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR1_JDATA                    ADC_JDR1_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR1_JDATA_0                  (0x00000001UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR1_JDATA_1                  (0x00000002UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR1_JDATA_2                  (0x00000004UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR1_JDATA_3                  (0x00000008UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR1_JDATA_4                  (0x00000010UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR1_JDATA_5                  (0x00000020UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR1_JDATA_6                  (0x00000040UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR1_JDATA_7                  (0x00000080UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR1_JDATA_8                  (0x00000100UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR1_JDATA_9                  (0x00000200UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR1_JDATA_10                 (0x00000400UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR1_JDATA_11                 (0x00000800UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR1_JDATA_12                 (0x00001000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR1_JDATA_13                 (0x00002000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR1_JDATA_14                 (0x00004000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR1_JDATA_15                 (0x00008000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR1_JDATA_16                 (0x00010000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR1_JDATA_17                 (0x00020000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR1_JDATA_18                 (0x00040000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR1_JDATA_19                 (0x00080000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR1_JDATA_20                 (0x00100000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR1_JDATA_21                 (0x00200000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR1_JDATA_22                 (0x00400000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR1_JDATA_23                 (0x00800000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR1_JDATA_24                 (0x01000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR1_JDATA_25                 (0x02000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR1_JDATA_26                 (0x04000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR1_JDATA_27                 (0x08000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR1_JDATA_28                 (0x10000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR1_JDATA_29                 (0x20000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR1_JDATA_30                 (0x40000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR1_JDATA_31                 (0x80000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR2 register  ********************/

+#define ADC_JDR2_JDATA_Pos                (0U)

+#define ADC_JDR2_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR2_JDATA                    ADC_JDR2_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR2_JDATA_0                  (0x00000001UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR2_JDATA_1                  (0x00000002UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR2_JDATA_2                  (0x00000004UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR2_JDATA_3                  (0x00000008UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR2_JDATA_4                  (0x00000010UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR2_JDATA_5                  (0x00000020UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR2_JDATA_6                  (0x00000040UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR2_JDATA_7                  (0x00000080UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR2_JDATA_8                  (0x00000100UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR2_JDATA_9                  (0x00000200UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR2_JDATA_10                 (0x00000400UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR2_JDATA_11                 (0x00000800UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR2_JDATA_12                 (0x00001000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR2_JDATA_13                 (0x00002000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR2_JDATA_14                 (0x00004000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR2_JDATA_15                 (0x00008000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR2_JDATA_16                 (0x00010000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR2_JDATA_17                 (0x00020000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR2_JDATA_18                 (0x00040000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR2_JDATA_19                 (0x00080000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR2_JDATA_20                 (0x00100000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR2_JDATA_21                 (0x00200000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR2_JDATA_22                 (0x00400000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR2_JDATA_23                 (0x00800000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR2_JDATA_24                 (0x01000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR2_JDATA_25                 (0x02000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR2_JDATA_26                 (0x04000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR2_JDATA_27                 (0x08000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR2_JDATA_28                 (0x10000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR2_JDATA_29                 (0x20000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR2_JDATA_30                 (0x40000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR2_JDATA_31                 (0x80000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR3 register  ********************/

+#define ADC_JDR3_JDATA_Pos                (0U)

+#define ADC_JDR3_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR3_JDATA                    ADC_JDR3_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR3_JDATA_0                  (0x00000001UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR3_JDATA_1                  (0x00000002UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR3_JDATA_2                  (0x00000004UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR3_JDATA_3                  (0x00000008UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR3_JDATA_4                  (0x00000010UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR3_JDATA_5                  (0x00000020UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR3_JDATA_6                  (0x00000040UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR3_JDATA_7                  (0x00000080UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR3_JDATA_8                  (0x00000100UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR3_JDATA_9                  (0x00000200UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR3_JDATA_10                 (0x00000400UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR3_JDATA_11                 (0x00000800UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR3_JDATA_12                 (0x00001000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR3_JDATA_13                 (0x00002000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR3_JDATA_14                 (0x00004000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR3_JDATA_15                 (0x00008000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR3_JDATA_16                 (0x00010000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR3_JDATA_17                 (0x00020000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR3_JDATA_18                 (0x00040000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR3_JDATA_19                 (0x00080000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR3_JDATA_20                 (0x00100000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR3_JDATA_21                 (0x00200000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR3_JDATA_22                 (0x00400000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR3_JDATA_23                 (0x00800000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR3_JDATA_24                 (0x01000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR3_JDATA_25                 (0x02000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR3_JDATA_26                 (0x04000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR3_JDATA_27                 (0x08000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR3_JDATA_28                 (0x10000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR3_JDATA_29                 (0x20000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR3_JDATA_30                 (0x40000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR3_JDATA_31                 (0x80000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR4 register  ********************/

+#define ADC_JDR4_JDATA_Pos                (0U)

+#define ADC_JDR4_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR4_JDATA                    ADC_JDR4_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR4_JDATA_0                  (0x00000001UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR4_JDATA_1                  (0x00000002UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR4_JDATA_2                  (0x00000004UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR4_JDATA_3                  (0x00000008UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR4_JDATA_4                  (0x00000010UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR4_JDATA_5                  (0x00000020UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR4_JDATA_6                  (0x00000040UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR4_JDATA_7                  (0x00000080UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR4_JDATA_8                  (0x00000100UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR4_JDATA_9                  (0x00000200UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR4_JDATA_10                 (0x00000400UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR4_JDATA_11                 (0x00000800UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR4_JDATA_12                 (0x00001000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR4_JDATA_13                 (0x00002000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR4_JDATA_14                 (0x00004000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR4_JDATA_15                 (0x00008000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR4_JDATA_16                 (0x00010000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR4_JDATA_17                 (0x00020000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR4_JDATA_18                 (0x00040000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR4_JDATA_19                 (0x00080000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR4_JDATA_20                 (0x00100000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR4_JDATA_21                 (0x00200000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR4_JDATA_22                 (0x00400000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR4_JDATA_23                 (0x00800000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR4_JDATA_24                 (0x01000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR4_JDATA_25                 (0x02000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR4_JDATA_26                 (0x04000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR4_JDATA_27                 (0x08000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR4_JDATA_28                 (0x10000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR4_JDATA_29                 (0x20000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR4_JDATA_30                 (0x40000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR4_JDATA_31                 (0x80000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_AWD2CR register  ********************/

+#define ADC_AWD2CR_AWD2CH_Pos             (0U)

+#define ADC_AWD2CR_AWD2CH_Msk             (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x000FFFFF */

+#define ADC_AWD2CR_AWD2CH                 ADC_AWD2CR_AWD2CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */

+#define ADC_AWD2CR_AWD2CH_0               (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000001 */

+#define ADC_AWD2CR_AWD2CH_1               (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000002 */

+#define ADC_AWD2CR_AWD2CH_2               (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000004 */

+#define ADC_AWD2CR_AWD2CH_3               (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000008 */

+#define ADC_AWD2CR_AWD2CH_4               (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000010 */

+#define ADC_AWD2CR_AWD2CH_5               (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000020 */

+#define ADC_AWD2CR_AWD2CH_6               (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000040 */

+#define ADC_AWD2CR_AWD2CH_7               (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000080 */

+#define ADC_AWD2CR_AWD2CH_8               (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000100 */

+#define ADC_AWD2CR_AWD2CH_9               (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000200 */

+#define ADC_AWD2CR_AWD2CH_10              (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000400 */

+#define ADC_AWD2CR_AWD2CH_11              (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000800 */

+#define ADC_AWD2CR_AWD2CH_12              (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00001000 */

+#define ADC_AWD2CR_AWD2CH_13              (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00002000 */

+#define ADC_AWD2CR_AWD2CH_14              (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00004000 */

+#define ADC_AWD2CR_AWD2CH_15              (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00008000 */

+#define ADC_AWD2CR_AWD2CH_16              (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00010000 */

+#define ADC_AWD2CR_AWD2CH_17              (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00020000 */

+#define ADC_AWD2CR_AWD2CH_18              (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */

+#define ADC_AWD2CR_AWD2CH_19              (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_AWD3CR register  ********************/

+#define ADC_AWD3CR_AWD3CH_Pos             (0U)

+#define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x000FFFFF */

+#define ADC_AWD3CR_AWD3CH                 ADC_AWD3CR_AWD3CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */

+#define ADC_AWD3CR_AWD3CH_0               (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000001 */

+#define ADC_AWD3CR_AWD3CH_1               (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000002 */

+#define ADC_AWD3CR_AWD3CH_2               (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000004 */

+#define ADC_AWD3CR_AWD3CH_3               (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000008 */

+#define ADC_AWD3CR_AWD3CH_4               (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000010 */

+#define ADC_AWD3CR_AWD3CH_5               (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000020 */

+#define ADC_AWD3CR_AWD3CH_6               (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000040 */

+#define ADC_AWD3CR_AWD3CH_7               (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000080 */

+#define ADC_AWD3CR_AWD3CH_8               (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000100 */

+#define ADC_AWD3CR_AWD3CH_9               (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000200 */

+#define ADC_AWD3CR_AWD3CH_10              (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000400 */

+#define ADC_AWD3CR_AWD3CH_11              (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000800 */

+#define ADC_AWD3CR_AWD3CH_12              (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00001000 */

+#define ADC_AWD3CR_AWD3CH_13              (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00002000 */

+#define ADC_AWD3CR_AWD3CH_14              (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00004000 */

+#define ADC_AWD3CR_AWD3CH_15              (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00008000 */

+#define ADC_AWD3CR_AWD3CH_16              (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00010000 */

+#define ADC_AWD3CR_AWD3CH_17              (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00020000 */

+#define ADC_AWD3CR_AWD3CH_18              (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */

+#define ADC_AWD3CR_AWD3CH_19              (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_DIFSEL register  ********************/

+#define ADC_DIFSEL_DIFSEL_Pos             (0U)

+#define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */

+#define ADC_DIFSEL_DIFSEL                 ADC_DIFSEL_DIFSEL_Msk                 /*!< ADC differential modes for channels 1 to 18 */

+#define ADC_DIFSEL_DIFSEL_0               (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000001 */

+#define ADC_DIFSEL_DIFSEL_1               (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000002 */

+#define ADC_DIFSEL_DIFSEL_2               (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000004 */

+#define ADC_DIFSEL_DIFSEL_3               (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000008 */

+#define ADC_DIFSEL_DIFSEL_4               (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000010 */

+#define ADC_DIFSEL_DIFSEL_5               (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000020 */

+#define ADC_DIFSEL_DIFSEL_6               (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000040 */

+#define ADC_DIFSEL_DIFSEL_7               (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000080 */

+#define ADC_DIFSEL_DIFSEL_8               (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000100 */

+#define ADC_DIFSEL_DIFSEL_9               (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000200 */

+#define ADC_DIFSEL_DIFSEL_10              (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000400 */

+#define ADC_DIFSEL_DIFSEL_11              (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000800 */

+#define ADC_DIFSEL_DIFSEL_12              (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00001000 */

+#define ADC_DIFSEL_DIFSEL_13              (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00002000 */

+#define ADC_DIFSEL_DIFSEL_14              (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00004000 */

+#define ADC_DIFSEL_DIFSEL_15              (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00008000 */

+#define ADC_DIFSEL_DIFSEL_16              (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00010000 */

+#define ADC_DIFSEL_DIFSEL_17              (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00020000 */

+#define ADC_DIFSEL_DIFSEL_18              (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00040000 */

+#define ADC_DIFSEL_DIFSEL_19              (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_CALFACT register  ********************/

+#define ADC_CALFACT_CALFACT_S_Pos         (0U)

+#define ADC_CALFACT_CALFACT_S_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */

+#define ADC_CALFACT_CALFACT_S             ADC_CALFACT_CALFACT_S_Msk              /*!< ADC calibration factors in single-ended mode */

+#define ADC_CALFACT_CALFACT_S_0           (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */

+#define ADC_CALFACT_CALFACT_S_1           (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */

+#define ADC_CALFACT_CALFACT_S_2           (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */

+#define ADC_CALFACT_CALFACT_S_3           (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */

+#define ADC_CALFACT_CALFACT_S_4           (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */

+#define ADC_CALFACT_CALFACT_S_5           (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */

+#define ADC_CALFACT_CALFACT_S_6           (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */

+#define ADC_CALFACT_CALFACT_S_7           (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */

+#define ADC_CALFACT_CALFACT_S_8           (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */

+#define ADC_CALFACT_CALFACT_S_9           (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */

+#define ADC_CALFACT_CALFACT_S_10          (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */

+#define ADC_CALFACT_CALFACT_D_Pos         (16U)

+#define ADC_CALFACT_CALFACT_D_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */

+#define ADC_CALFACT_CALFACT_D             ADC_CALFACT_CALFACT_D_Msk              /*!< ADC calibration factors in differential mode */

+#define ADC_CALFACT_CALFACT_D_0           (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */

+#define ADC_CALFACT_CALFACT_D_1           (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */

+#define ADC_CALFACT_CALFACT_D_2           (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */

+#define ADC_CALFACT_CALFACT_D_3           (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */

+#define ADC_CALFACT_CALFACT_D_4           (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */

+#define ADC_CALFACT_CALFACT_D_5           (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */

+#define ADC_CALFACT_CALFACT_D_6           (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */

+#define ADC_CALFACT_CALFACT_D_7           (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */

+#define ADC_CALFACT_CALFACT_D_8           (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */

+#define ADC_CALFACT_CALFACT_D_9           (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */

+#define ADC_CALFACT_CALFACT_D_10          (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */

+

+/********************  Bit definition for ADC_CALFACT2 register  ********************/

+#define ADC_CALFACT2_LINCALFACT_Pos       (0U)

+#define ADC_CALFACT2_LINCALFACT_Msk       (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */

+#define ADC_CALFACT2_LINCALFACT           ADC_CALFACT2_LINCALFACT_Msk                   /*!< ADC Linearity calibration factors */

+#define ADC_CALFACT2_LINCALFACT_0         (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */

+#define ADC_CALFACT2_LINCALFACT_1         (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */

+#define ADC_CALFACT2_LINCALFACT_2         (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */

+#define ADC_CALFACT2_LINCALFACT_3         (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */

+#define ADC_CALFACT2_LINCALFACT_4         (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */

+#define ADC_CALFACT2_LINCALFACT_5         (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */

+#define ADC_CALFACT2_LINCALFACT_6         (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */

+#define ADC_CALFACT2_LINCALFACT_7         (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */

+#define ADC_CALFACT2_LINCALFACT_8         (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */

+#define ADC_CALFACT2_LINCALFACT_9         (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */

+#define ADC_CALFACT2_LINCALFACT_10        (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */

+#define ADC_CALFACT2_LINCALFACT_11        (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */

+#define ADC_CALFACT2_LINCALFACT_12        (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */

+#define ADC_CALFACT2_LINCALFACT_13        (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */

+#define ADC_CALFACT2_LINCALFACT_14        (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */

+#define ADC_CALFACT2_LINCALFACT_15        (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */

+#define ADC_CALFACT2_LINCALFACT_16        (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */

+#define ADC_CALFACT2_LINCALFACT_17        (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */

+#define ADC_CALFACT2_LINCALFACT_18        (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */

+#define ADC_CALFACT2_LINCALFACT_19        (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */

+#define ADC_CALFACT2_LINCALFACT_20        (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */

+#define ADC_CALFACT2_LINCALFACT_21        (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */

+#define ADC_CALFACT2_LINCALFACT_22        (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */

+#define ADC_CALFACT2_LINCALFACT_23        (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */

+#define ADC_CALFACT2_LINCALFACT_24        (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */

+#define ADC_CALFACT2_LINCALFACT_25        (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */

+#define ADC_CALFACT2_LINCALFACT_26        (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */

+#define ADC_CALFACT2_LINCALFACT_27        (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */

+#define ADC_CALFACT2_LINCALFACT_28        (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */

+#define ADC_CALFACT2_LINCALFACT_29        (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */

+

+/*************************  ADC Common registers  *****************************/

+/********************  Bit definition for ADC_CSR register  ********************/

+#define ADC_CSR_ADRDY_MST_Pos             (0U)

+#define ADC_CSR_ADRDY_MST_Msk             (0x1UL << ADC_CSR_ADRDY_MST_Pos)     /*!< 0x00000001 */

+#define ADC_CSR_ADRDY_MST                 ADC_CSR_ADRDY_MST_Msk                /*!< Master ADC ready */

+#define ADC_CSR_EOSMP_MST_Pos             (1U)

+#define ADC_CSR_EOSMP_MST_Msk             (0x1UL << ADC_CSR_EOSMP_MST_Pos)     /*!< 0x00000002 */

+#define ADC_CSR_EOSMP_MST                 ADC_CSR_EOSMP_MST_Msk                /*!< End of sampling phase flag of the master ADC */

+#define ADC_CSR_EOC_MST_Pos               (2U)

+#define ADC_CSR_EOC_MST_Msk               (0x1UL << ADC_CSR_EOC_MST_Pos)       /*!< 0x00000004 */

+#define ADC_CSR_EOC_MST                   ADC_CSR_EOC_MST_Msk                  /*!< End of regular conversion of the master ADC */

+#define ADC_CSR_EOS_MST_Pos               (3U)

+#define ADC_CSR_EOS_MST_Msk               (0x1UL << ADC_CSR_EOS_MST_Pos)       /*!< 0x00000008 */

+#define ADC_CSR_EOS_MST                   ADC_CSR_EOS_MST_Msk                  /*!< End of regular sequence flag of the master ADC */

+#define ADC_CSR_OVR_MST_Pos               (4U)

+#define ADC_CSR_OVR_MST_Msk               (0x1UL << ADC_CSR_OVR_MST_Pos)       /*!< 0x00000010 */

+#define ADC_CSR_OVR_MST                   ADC_CSR_OVR_MST_Msk                  /*!< Overrun flag of the master ADC */

+#define ADC_CSR_JEOC_MST_Pos              (5U)

+#define ADC_CSR_JEOC_MST_Msk              (0x1UL << ADC_CSR_JEOC_MST_Pos)      /*!< 0x00000020 */

+#define ADC_CSR_JEOC_MST                  ADC_CSR_JEOC_MST_Msk                 /*!< End of injected conversion of the master ADC */

+#define ADC_CSR_JEOS_MST_Pos              (6U)

+#define ADC_CSR_JEOS_MST_Msk              (0x1UL << ADC_CSR_JEOS_MST_Pos)      /*!< 0x00000040 */

+#define ADC_CSR_JEOS_MST                  ADC_CSR_JEOS_MST_Msk                 /*!< End of injected sequence flag of the master ADC */

+#define ADC_CSR_AWD1_MST_Pos              (7U)

+#define ADC_CSR_AWD1_MST_Msk              (0x1UL << ADC_CSR_AWD1_MST_Pos)      /*!< 0x00000080 */

+#define ADC_CSR_AWD1_MST                  ADC_CSR_AWD1_MST_Msk                 /*!< Analog watchdog 1 flag of the master ADC */

+#define ADC_CSR_AWD2_MST_Pos              (8U)

+#define ADC_CSR_AWD2_MST_Msk              (0x1UL << ADC_CSR_AWD2_MST_Pos)      /*!< 0x00000100 */

+#define ADC_CSR_AWD2_MST                  ADC_CSR_AWD2_MST_Msk                 /*!< Analog watchdog 2 flag of the master ADC */

+#define ADC_CSR_AWD3_MST_Pos              (9U)

+#define ADC_CSR_AWD3_MST_Msk              (0x1UL << ADC_CSR_AWD3_MST_Pos)      /*!< 0x00000200 */

+#define ADC_CSR_AWD3_MST                  ADC_CSR_AWD3_MST_Msk                 /*!< Analog watchdog 3 flag of the master ADC */

+#define ADC_CSR_JQOVF_MST_Pos             (10U)

+#define ADC_CSR_JQOVF_MST_Msk             (0x1UL << ADC_CSR_JQOVF_MST_Pos)     /*!< 0x00000400 */

+#define ADC_CSR_JQOVF_MST                 ADC_CSR_JQOVF_MST_Msk                /*!< Injected context queue overflow flag of the master ADC */

+#define ADC_CSR_ADRDY_SLV_Pos             (16U)

+#define ADC_CSR_ADRDY_SLV_Msk             (0x1UL << ADC_CSR_ADRDY_SLV_Pos)     /*!< 0x00010000 */

+#define ADC_CSR_ADRDY_SLV                 ADC_CSR_ADRDY_SLV_Msk                /*!< Slave ADC ready */

+#define ADC_CSR_EOSMP_SLV_Pos             (17U)

+#define ADC_CSR_EOSMP_SLV_Msk             (0x1UL << ADC_CSR_EOSMP_SLV_Pos)     /*!< 0x00020000 */

+#define ADC_CSR_EOSMP_SLV                 ADC_CSR_EOSMP_SLV_Msk                /*!< End of sampling phase flag of the slave ADC */

+#define ADC_CSR_EOC_SLV_Pos               (18U)

+#define ADC_CSR_EOC_SLV_Msk               (0x1UL << ADC_CSR_EOC_SLV_Pos)       /*!< 0x00040000 */

+#define ADC_CSR_EOC_SLV                   ADC_CSR_EOC_SLV_Msk                  /*!< End of regular conversion of the slave ADC */

+#define ADC_CSR_EOS_SLV_Pos               (19U)

+#define ADC_CSR_EOS_SLV_Msk               (0x1UL << ADC_CSR_EOS_SLV_Pos)       /*!< 0x00080000 */

+#define ADC_CSR_EOS_SLV                   ADC_CSR_EOS_SLV_Msk                  /*!< End of regular sequence flag of the slave ADC */

+#define ADC_CSR_OVR_SLV_Pos               (20U)

+#define ADC_CSR_OVR_SLV_Msk               (0x1UL << ADC_CSR_OVR_SLV_Pos)       /*!< 0x00100000 */

+#define ADC_CSR_OVR_SLV                   ADC_CSR_OVR_SLV_Msk                  /*!< Overrun flag of the slave ADC */

+#define ADC_CSR_JEOC_SLV_Pos              (21U)

+#define ADC_CSR_JEOC_SLV_Msk              (0x1UL << ADC_CSR_JEOC_SLV_Pos)      /*!< 0x00200000 */

+#define ADC_CSR_JEOC_SLV                  ADC_CSR_JEOC_SLV_Msk                 /*!< End of injected conversion of the slave ADC */

+#define ADC_CSR_JEOS_SLV_Pos              (22U)

+#define ADC_CSR_JEOS_SLV_Msk              (0x1UL << ADC_CSR_JEOS_SLV_Pos)      /*!< 0x00400000 */

+#define ADC_CSR_JEOS_SLV                  ADC_CSR_JEOS_SLV_Msk                 /*!< End of injected sequence flag of the slave ADC */

+#define ADC_CSR_AWD1_SLV_Pos              (23U)

+#define ADC_CSR_AWD1_SLV_Msk              (0x1UL << ADC_CSR_AWD1_SLV_Pos)      /*!< 0x00800000 */

+#define ADC_CSR_AWD1_SLV                  ADC_CSR_AWD1_SLV_Msk                 /*!< Analog watchdog 1 flag of the slave ADC */

+#define ADC_CSR_AWD2_SLV_Pos              (24U)

+#define ADC_CSR_AWD2_SLV_Msk              (0x1UL << ADC_CSR_AWD2_SLV_Pos)      /*!< 0x01000000 */

+#define ADC_CSR_AWD2_SLV                  ADC_CSR_AWD2_SLV_Msk                 /*!< Analog watchdog 2 flag of the slave ADC */

+#define ADC_CSR_AWD3_SLV_Pos              (25U)

+#define ADC_CSR_AWD3_SLV_Msk              (0x1UL << ADC_CSR_AWD3_SLV_Pos)      /*!< 0x02000000 */

+#define ADC_CSR_AWD3_SLV                  ADC_CSR_AWD3_SLV_Msk                 /*!< Analog watchdog 3 flag of the slave ADC */

+#define ADC_CSR_JQOVF_SLV_Pos             (26U)

+#define ADC_CSR_JQOVF_SLV_Msk             (0x1UL << ADC_CSR_JQOVF_SLV_Pos)     /*!< 0x04000000 */

+#define ADC_CSR_JQOVF_SLV                 ADC_CSR_JQOVF_SLV_Msk                /*!< Injected context queue overflow flag of the slave ADC */

+

+/********************  Bit definition for ADC_CCR register  ********************/

+#define ADC_CCR_DUAL_Pos                  (0U)

+#define ADC_CCR_DUAL_Msk                  (0x1FUL << ADC_CCR_DUAL_Pos)          /*!< 0x0000001F */

+#define ADC_CCR_DUAL                      ADC_CCR_DUAL_Msk                      /*!< Dual ADC mode selection */

+#define ADC_CCR_DUAL_0                    (0x01UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000001 */

+#define ADC_CCR_DUAL_1                    (0x02UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000002 */

+#define ADC_CCR_DUAL_2                    (0x04UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000004 */

+#define ADC_CCR_DUAL_3                    (0x08UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000008 */

+#define ADC_CCR_DUAL_4                    (0x10UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000010 */

+

+#define ADC_CCR_DELAY_Pos                 (8U)

+#define ADC_CCR_DELAY_Msk                 (0xFUL << ADC_CCR_DELAY_Pos)          /*!< 0x00000F00 */

+#define ADC_CCR_DELAY                     ADC_CCR_DELAY_Msk                     /*!< Delay between 2 sampling phases */

+#define ADC_CCR_DELAY_0                   (0x1UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000100 */

+#define ADC_CCR_DELAY_1                   (0x2UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000200 */

+#define ADC_CCR_DELAY_2                   (0x4UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000400 */

+#define ADC_CCR_DELAY_3                   (0x8UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000800 */

+

+

+#define ADC_CCR_DAMDF_Pos                 (14U)

+#define ADC_CCR_DAMDF_Msk                 (0x3UL << ADC_CCR_DAMDF_Pos)          /*!< 0x0000C000 */

+#define ADC_CCR_DAMDF                     ADC_CCR_DAMDF_Msk                     /*!< Dual ADC mode Data format */

+#define ADC_CCR_DAMDF_0                   (0x1UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00004000 */

+#define ADC_CCR_DAMDF_1                   (0x2UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00008000 */

+

+#define ADC_CCR_CKMODE_Pos                (16U)

+#define ADC_CCR_CKMODE_Msk                (0x3UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00030000 */

+#define ADC_CCR_CKMODE                    ADC_CCR_CKMODE_Msk                    /*!< ADC clock mode */

+#define ADC_CCR_CKMODE_0                  (0x1UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00010000 */

+#define ADC_CCR_CKMODE_1                  (0x2UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00020000 */

+

+#define ADC_CCR_PRESC_Pos                 (18U)

+#define ADC_CCR_PRESC_Msk                 (0xFUL << ADC_CCR_PRESC_Pos)          /*!< 0x003C0000 */

+#define ADC_CCR_PRESC                     ADC_CCR_PRESC_Msk                     /*!< ADC prescaler */

+#define ADC_CCR_PRESC_0                   (0x1UL << ADC_CCR_PRESC_Pos)          /*!< 0x00040000 */

+#define ADC_CCR_PRESC_1                   (0x2UL << ADC_CCR_PRESC_Pos)          /*!< 0x00080000 */

+#define ADC_CCR_PRESC_2                   (0x4UL << ADC_CCR_PRESC_Pos)          /*!< 0x00100000 */

+#define ADC_CCR_PRESC_3                   (0x8UL << ADC_CCR_PRESC_Pos)          /*!< 0x00200000 */

+

+#define ADC_CCR_VREFEN_Pos                (22U)

+#define ADC_CCR_VREFEN_Msk                (0x1UL << ADC_CCR_VREFEN_Pos)         /*!< 0x00400000 */

+#define ADC_CCR_VREFEN                    ADC_CCR_VREFEN_Msk                    /*!< VREFINT enable */

+#define ADC_CCR_TSEN_Pos                  (23U)

+#define ADC_CCR_TSEN_Msk                  (0x1UL << ADC_CCR_TSEN_Pos)           /*!< 0x00800000 */

+#define ADC_CCR_TSEN                      ADC_CCR_TSEN_Msk                      /*!< Temperature sensor enable */

+#define ADC_CCR_VBATEN_Pos                (24U)

+#define ADC_CCR_VBATEN_Msk                (0x1UL << ADC_CCR_VBATEN_Pos)         /*!< 0x01000000 */

+#define ADC_CCR_VBATEN                    ADC_CCR_VBATEN_Msk                    /*!< VBAT enable */

+

+/********************  Bit definition for ADC_CDR register  *******************/

+#define ADC_CDR_RDATA_MST_Pos             (0U)

+#define ADC_CDR_RDATA_MST_Msk             (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)   /*!< 0x0000FFFF */

+#define ADC_CDR_RDATA_MST                 ADC_CDR_RDATA_MST_Msk                 /*!< ADC multimode master group regular conversion data */

+

+#define ADC_CDR_RDATA_SLV_Pos             (16U)

+#define ADC_CDR_RDATA_SLV_Msk             (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)   /*!< 0xFFFF0000 */

+#define ADC_CDR_RDATA_SLV                 ADC_CDR_RDATA_SLV_Msk                 /*!< ADC multimode slave group regular conversion data */

+

+/********************  Bit definition for ADC_CDR2 register  ******************/

+#define ADC_CDR2_RDATA_ALT_Pos            (0U)

+#define ADC_CDR2_RDATA_ALT_Msk            (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */

+#define ADC_CDR2_RDATA_ALT                ADC_CDR2_RDATA_ALT_Msk                   /*!< Regular data of the master/slave alternated ADCs */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                   VREFBUF                                  */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for VREFBUF_CSR register  ****************/

+#define VREFBUF_CSR_ENVR_Pos        (0U)

+#define VREFBUF_CSR_ENVR_Msk        (0x1UL << VREFBUF_CSR_ENVR_Pos)            /*!< 0x00000001 */

+#define VREFBUF_CSR_ENVR            VREFBUF_CSR_ENVR_Msk                       /*!<Voltage reference buffer enable */

+#define VREFBUF_CSR_HIZ_Pos         (1U)

+#define VREFBUF_CSR_HIZ_Msk         (0x1UL << VREFBUF_CSR_HIZ_Pos)             /*!< 0x00000002 */

+#define VREFBUF_CSR_HIZ             VREFBUF_CSR_HIZ_Msk                        /*!<High impedance mode             */

+#define VREFBUF_CSR_VRR_Pos         (3U)

+#define VREFBUF_CSR_VRR_Msk         (0x1UL << VREFBUF_CSR_VRR_Pos)             /*!< 0x00000008 */

+#define VREFBUF_CSR_VRR             VREFBUF_CSR_VRR_Msk                        /*!<Voltage reference buffer ready  */

+#define VREFBUF_CSR_VRS_Pos         (4U)

+#define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */

+#define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */

+

+#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */

+#define VREFBUF_CSR_VRS_OUT2_Pos    (4U)

+#define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */

+#define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */

+#define VREFBUF_CSR_VRS_OUT3_Pos    (5U)

+#define VREFBUF_CSR_VRS_OUT3_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)        /*!< 0x00000020 */

+#define VREFBUF_CSR_VRS_OUT3        VREFBUF_CSR_VRS_OUT3_Msk                   /*!<Voltage reference VREF_OUT3     */

+#define VREFBUF_CSR_VRS_OUT4_Pos    (4U)

+#define VREFBUF_CSR_VRS_OUT4_Msk    (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)        /*!< 0x00000030 */

+#define VREFBUF_CSR_VRS_OUT4        VREFBUF_CSR_VRS_OUT4_Msk                   /*!<Voltage reference VREF_OUT4     */

+

+/*******************  Bit definition for VREFBUF_CCR register  ****************/

+#define VREFBUF_CCR_TRIM_Pos        (0U)

+#define VREFBUF_CCR_TRIM_Msk        (0x3FUL << VREFBUF_CCR_TRIM_Pos)           /*!< 0x0000003F */

+#define VREFBUF_CCR_TRIM            VREFBUF_CCR_TRIM_Msk                       /*!<TRIM[5:0] bits (Trimming code)  */

+

+/******************************************************************************/

+/*                                                                            */

+/*                 Flexible Datarate Controller Area Network                  */

+/*                                                                            */

+/******************************************************************************/

+/*!<FDCAN control and status registers */

+/*****************  Bit definition for FDCAN_CREL register  *******************/

+#define FDCAN_CREL_DAY_Pos        (0U)

+#define FDCAN_CREL_DAY_Msk        (0xFFUL << FDCAN_CREL_DAY_Pos)               /*!< 0x000000FF */

+#define FDCAN_CREL_DAY            FDCAN_CREL_DAY_Msk                           /*!<Timestamp Day                           */

+#define FDCAN_CREL_MON_Pos        (8U)

+#define FDCAN_CREL_MON_Msk        (0xFFUL << FDCAN_CREL_MON_Pos)               /*!< 0x0000FF00 */

+#define FDCAN_CREL_MON            FDCAN_CREL_MON_Msk                           /*!<Timestamp Month                         */

+#define FDCAN_CREL_YEAR_Pos       (16U)

+#define FDCAN_CREL_YEAR_Msk       (0xFUL << FDCAN_CREL_YEAR_Pos)               /*!< 0x000F0000 */

+#define FDCAN_CREL_YEAR           FDCAN_CREL_YEAR_Msk                          /*!<Timestamp Year                          */

+#define FDCAN_CREL_SUBSTEP_Pos    (20U)

+#define FDCAN_CREL_SUBSTEP_Msk    (0xFUL << FDCAN_CREL_SUBSTEP_Pos)            /*!< 0x00F00000 */

+#define FDCAN_CREL_SUBSTEP        FDCAN_CREL_SUBSTEP_Msk                       /*!<Sub-step of Core release                */

+#define FDCAN_CREL_STEP_Pos       (24U)

+#define FDCAN_CREL_STEP_Msk       (0xFUL << FDCAN_CREL_STEP_Pos)               /*!< 0x0F000000 */

+#define FDCAN_CREL_STEP           FDCAN_CREL_STEP_Msk                          /*!<Step of Core release                    */

+#define FDCAN_CREL_REL_Pos        (28U)

+#define FDCAN_CREL_REL_Msk        (0xFUL << FDCAN_CREL_REL_Pos)                /*!< 0xF0000000 */

+#define FDCAN_CREL_REL            FDCAN_CREL_REL_Msk                           /*!<Core release                            */

+

+/*****************  Bit definition for FDCAN_ENDN register  *******************/

+#define FDCAN_ENDN_ETV_Pos        (0U)

+#define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endiannes Test Value                    */

+

+/*****************  Bit definition for FDCAN_DBTP register  *******************/

+#define FDCAN_DBTP_DSJW_Pos       (0U)

+#define FDCAN_DBTP_DSJW_Msk       (0xFUL << FDCAN_DBTP_DSJW_Pos)               /*!< 0x0000000F */

+#define FDCAN_DBTP_DSJW           FDCAN_DBTP_DSJW_Msk                          /*!<Synchronization Jump Width              */

+#define FDCAN_DBTP_DTSEG2_Pos     (4U)

+#define FDCAN_DBTP_DTSEG2_Msk     (0xFUL << FDCAN_DBTP_DTSEG2_Pos)             /*!< 0x000000F0 */

+#define FDCAN_DBTP_DTSEG2         FDCAN_DBTP_DTSEG2_Msk                        /*!<Data time segment after sample point    */

+#define FDCAN_DBTP_DTSEG1_Pos     (8U)

+#define FDCAN_DBTP_DTSEG1_Msk     (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)            /*!< 0x00001F00 */

+#define FDCAN_DBTP_DTSEG1         FDCAN_DBTP_DTSEG1_Msk                        /*!<Data time segment before sample point   */

+#define FDCAN_DBTP_DBRP_Pos       (16U)

+#define FDCAN_DBTP_DBRP_Msk       (0x1FUL << FDCAN_DBTP_DBRP_Pos)              /*!< 0x001F0000 */

+#define FDCAN_DBTP_DBRP           FDCAN_DBTP_DBRP_Msk                          /*!<Data BIt Rate Prescaler                 */

+#define FDCAN_DBTP_TDC_Pos        (23U)

+#define FDCAN_DBTP_TDC_Msk        (0x1UL << FDCAN_DBTP_TDC_Pos)                /*!< 0x00800000 */

+#define FDCAN_DBTP_TDC            FDCAN_DBTP_TDC_Msk                           /*!<Transceiver Delay Compensation          */

+

+/*****************  Bit definition for FDCAN_TEST register  *******************/

+#define FDCAN_TEST_LBCK_Pos       (4U)

+#define FDCAN_TEST_LBCK_Msk       (0x1UL << FDCAN_TEST_LBCK_Pos)               /*!< 0x00000010 */

+#define FDCAN_TEST_LBCK           FDCAN_TEST_LBCK_Msk                          /*!<Loop Back mode                           */

+#define FDCAN_TEST_TX_Pos         (5U)

+#define FDCAN_TEST_TX_Msk         (0x3UL << FDCAN_TEST_TX_Pos)                 /*!< 0x00000060 */

+#define FDCAN_TEST_TX             FDCAN_TEST_TX_Msk                            /*!<Control of Transmit Pin                  */

+#define FDCAN_TEST_RX_Pos         (7U)

+#define FDCAN_TEST_RX_Msk         (0x1UL << FDCAN_TEST_RX_Pos)                 /*!< 0x00000080 */

+#define FDCAN_TEST_RX             FDCAN_TEST_RX_Msk                            /*!<Receive Pin                              */

+

+/*****************  Bit definition for FDCAN_RWD register  ********************/

+#define FDCAN_RWD_WDC_Pos         (0U)

+#define FDCAN_RWD_WDC_Msk         (0xFFUL << FDCAN_RWD_WDC_Pos)                /*!< 0x000000FF */

+#define FDCAN_RWD_WDC             FDCAN_RWD_WDC_Msk                            /*!<Watchdog configuration                   */

+#define FDCAN_RWD_WDV_Pos         (8U)

+#define FDCAN_RWD_WDV_Msk         (0xFFUL << FDCAN_RWD_WDV_Pos)                /*!< 0x0000FF00 */

+#define FDCAN_RWD_WDV             FDCAN_RWD_WDV_Msk                            /*!<Watchdog value                           */

+

+/*****************  Bit definition for FDCAN_CCCR register  ********************/

+#define FDCAN_CCCR_INIT_Pos       (0U)

+#define FDCAN_CCCR_INIT_Msk       (0x1UL << FDCAN_CCCR_INIT_Pos)               /*!< 0x00000001 */

+#define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!<Initialization                           */

+#define FDCAN_CCCR_CCE_Pos        (1U)

+#define FDCAN_CCCR_CCE_Msk        (0x1UL << FDCAN_CCCR_CCE_Pos)                /*!< 0x00000002 */

+#define FDCAN_CCCR_CCE            FDCAN_CCCR_CCE_Msk                           /*!<Configuration Change Enable              */

+#define FDCAN_CCCR_ASM_Pos        (2U)

+#define FDCAN_CCCR_ASM_Msk        (0x1UL << FDCAN_CCCR_ASM_Pos)                /*!< 0x00000004 */

+#define FDCAN_CCCR_ASM            FDCAN_CCCR_ASM_Msk                           /*!<ASM Restricted Operation Mode            */

+#define FDCAN_CCCR_CSA_Pos        (3U)

+#define FDCAN_CCCR_CSA_Msk        (0x1UL << FDCAN_CCCR_CSA_Pos)                /*!< 0x00000008 */

+#define FDCAN_CCCR_CSA            FDCAN_CCCR_CSA_Msk                           /*!<Clock Stop Acknowledge                   */

+#define FDCAN_CCCR_CSR_Pos        (4U)

+#define FDCAN_CCCR_CSR_Msk        (0x1UL << FDCAN_CCCR_CSR_Pos)                /*!< 0x00000010 */

+#define FDCAN_CCCR_CSR            FDCAN_CCCR_CSR_Msk                           /*!<Clock Stop Request                       */

+#define FDCAN_CCCR_MON_Pos        (5U)

+#define FDCAN_CCCR_MON_Msk        (0x1UL << FDCAN_CCCR_MON_Pos)                /*!< 0x00000020 */

+#define FDCAN_CCCR_MON            FDCAN_CCCR_MON_Msk                           /*!<Bus Monitoring Mode                      */

+#define FDCAN_CCCR_DAR_Pos        (6U)

+#define FDCAN_CCCR_DAR_Msk        (0x1UL << FDCAN_CCCR_DAR_Pos)                /*!< 0x00000040 */

+#define FDCAN_CCCR_DAR            FDCAN_CCCR_DAR_Msk                           /*!<Disable Automatic Retransmission         */

+#define FDCAN_CCCR_TEST_Pos       (7U)

+#define FDCAN_CCCR_TEST_Msk       (0x1UL << FDCAN_CCCR_TEST_Pos)               /*!< 0x00000080 */

+#define FDCAN_CCCR_TEST           FDCAN_CCCR_TEST_Msk                          /*!<Test Mode Enable                         */

+#define FDCAN_CCCR_FDOE_Pos       (8U)

+#define FDCAN_CCCR_FDOE_Msk       (0x1UL << FDCAN_CCCR_FDOE_Pos)               /*!< 0x00000100 */

+#define FDCAN_CCCR_FDOE           FDCAN_CCCR_FDOE_Msk                          /*!<FD Operation Enable                      */

+#define FDCAN_CCCR_BRSE_Pos       (9U)

+#define FDCAN_CCCR_BRSE_Msk       (0x1UL << FDCAN_CCCR_BRSE_Pos)               /*!< 0x00000200 */

+#define FDCAN_CCCR_BRSE           FDCAN_CCCR_BRSE_Msk                          /*!<FDCAN Bit Rate Switching                 */

+#define FDCAN_CCCR_PXHD_Pos       (12U)

+#define FDCAN_CCCR_PXHD_Msk       (0x1UL << FDCAN_CCCR_PXHD_Pos)               /*!< 0x00001000 */

+#define FDCAN_CCCR_PXHD           FDCAN_CCCR_PXHD_Msk                          /*!<Protocol Exception Handling Disable      */

+#define FDCAN_CCCR_EFBI_Pos       (13U)

+#define FDCAN_CCCR_EFBI_Msk       (0x1UL << FDCAN_CCCR_EFBI_Pos)               /*!< 0x00002000 */

+#define FDCAN_CCCR_EFBI           FDCAN_CCCR_EFBI_Msk                          /*!<Edge Filtering during Bus Integration    */

+#define FDCAN_CCCR_TXP_Pos        (14U)

+#define FDCAN_CCCR_TXP_Msk        (0x1UL << FDCAN_CCCR_TXP_Pos)                /*!< 0x00004000 */

+#define FDCAN_CCCR_TXP            FDCAN_CCCR_TXP_Msk                           /*!<Two CAN bit times Pause                  */

+#define FDCAN_CCCR_NISO_Pos       (15U)

+#define FDCAN_CCCR_NISO_Msk       (0x1UL << FDCAN_CCCR_NISO_Pos)               /*!< 0x00008000 */

+#define FDCAN_CCCR_NISO           FDCAN_CCCR_NISO_Msk                          /*!<Non ISO Operation                        */

+

+/*****************  Bit definition for FDCAN_NBTP register  ********************/

+#define FDCAN_NBTP_NTSEG2_Pos     (0U)

+#define FDCAN_NBTP_NTSEG2_Msk     (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)            /*!< 0x0000007F */

+#define FDCAN_NBTP_NTSEG2         FDCAN_NBTP_NTSEG2_Msk                        /*!<Nominal Time segment after sample point  */

+#define FDCAN_NBTP_NTSEG1_Pos     (8U)

+#define FDCAN_NBTP_NTSEG1_Msk     (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)            /*!< 0x0000FF00 */

+#define FDCAN_NBTP_NTSEG1         FDCAN_NBTP_NTSEG1_Msk                        /*!<Nominal Time segment before sample point */

+#define FDCAN_NBTP_NBRP_Pos       (16U)

+#define FDCAN_NBTP_NBRP_Msk       (0x1FFUL << FDCAN_NBTP_NBRP_Pos)             /*!< 0x01FF0000 */

+#define FDCAN_NBTP_NBRP           FDCAN_NBTP_NBRP_Msk                          /*!<Bit Rate Prescaler                       */

+#define FDCAN_NBTP_NSJW_Pos       (25U)

+#define FDCAN_NBTP_NSJW_Msk       (0x7FUL << FDCAN_NBTP_NSJW_Pos)              /*!< 0xFE000000 */

+#define FDCAN_NBTP_NSJW           FDCAN_NBTP_NSJW_Msk                          /*!<Nominal (Re)Synchronization Jump Width   */

+

+/*****************  Bit definition for FDCAN_TSCC register  ********************/

+#define FDCAN_TSCC_TSS_Pos        (0U)

+#define FDCAN_TSCC_TSS_Msk        (0x3UL << FDCAN_TSCC_TSS_Pos)                /*!< 0x00000003 */

+#define FDCAN_TSCC_TSS            FDCAN_TSCC_TSS_Msk                           /*!<Timestamp Select                         */

+#define FDCAN_TSCC_TCP_Pos        (16U)

+#define FDCAN_TSCC_TCP_Msk        (0xFUL << FDCAN_TSCC_TCP_Pos)                /*!< 0x000F0000 */

+#define FDCAN_TSCC_TCP            FDCAN_TSCC_TCP_Msk                           /*!<Timestamp Counter Prescaler              */

+

+/*****************  Bit definition for FDCAN_TSCV register  ********************/

+#define FDCAN_TSCV_TSC_Pos        (0U)

+#define FDCAN_TSCV_TSC_Msk        (0xFFFFUL << FDCAN_TSCV_TSC_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TSCV_TSC            FDCAN_TSCV_TSC_Msk                           /*!<Timestamp Counter                        */

+

+/*****************  Bit definition for FDCAN_TOCC register  ********************/

+#define FDCAN_TOCC_ETOC_Pos       (0U)

+#define FDCAN_TOCC_ETOC_Msk       (0x1UL << FDCAN_TOCC_ETOC_Pos)               /*!< 0x00000001 */

+#define FDCAN_TOCC_ETOC           FDCAN_TOCC_ETOC_Msk                          /*!<Enable Timeout Counter                   */

+#define FDCAN_TOCC_TOS_Pos        (1U)

+#define FDCAN_TOCC_TOS_Msk        (0x3UL << FDCAN_TOCC_TOS_Pos)                /*!< 0x00000006 */

+#define FDCAN_TOCC_TOS            FDCAN_TOCC_TOS_Msk                           /*!<Timeout Select                           */

+#define FDCAN_TOCC_TOP_Pos        (16U)

+#define FDCAN_TOCC_TOP_Msk        (0xFFFFUL << FDCAN_TOCC_TOP_Pos)             /*!< 0xFFFF0000 */

+#define FDCAN_TOCC_TOP            FDCAN_TOCC_TOP_Msk                           /*!<Timeout Period                           */

+

+/*****************  Bit definition for FDCAN_TOCV register  ********************/

+#define FDCAN_TOCV_TOC_Pos        (0U)

+#define FDCAN_TOCV_TOC_Msk        (0xFFFFUL << FDCAN_TOCV_TOC_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TOCV_TOC            FDCAN_TOCV_TOC_Msk                           /*!<Timeout Counter                          */

+

+/*****************  Bit definition for FDCAN_ECR register  *********************/

+#define FDCAN_ECR_TEC_Pos         (0U)

+#define FDCAN_ECR_TEC_Msk         (0xFUL << FDCAN_ECR_TEC_Pos)                 /*!< 0x0000000F */

+#define FDCAN_ECR_TEC             FDCAN_ECR_TEC_Msk                            /*!<Transmit Error Counter                   */

+#define FDCAN_ECR_REC_Pos         (8U)

+#define FDCAN_ECR_REC_Msk         (0x7FUL << FDCAN_ECR_REC_Pos)                /*!< 0x00007F00 */

+#define FDCAN_ECR_REC             FDCAN_ECR_REC_Msk                            /*!<Receive Error Counter                    */

+#define FDCAN_ECR_RP_Pos          (15U)

+#define FDCAN_ECR_RP_Msk          (0x1UL << FDCAN_ECR_RP_Pos)                  /*!< 0x00008000 */

+#define FDCAN_ECR_RP              FDCAN_ECR_RP_Msk                             /*!<Receive Error Passive                    */

+#define FDCAN_ECR_CEL_Pos         (16U)

+#define FDCAN_ECR_CEL_Msk         (0xFFUL << FDCAN_ECR_CEL_Pos)                /*!< 0x00FF0000 */

+#define FDCAN_ECR_CEL             FDCAN_ECR_CEL_Msk                            /*!<CAN Error Logging                        */

+

+/*****************  Bit definition for FDCAN_PSR register  *********************/

+#define FDCAN_PSR_LEC_Pos         (0U)

+#define FDCAN_PSR_LEC_Msk         (0x7UL << FDCAN_PSR_LEC_Pos)                 /*!< 0x00000007 */

+#define FDCAN_PSR_LEC             FDCAN_PSR_LEC_Msk                            /*!<Last Error Code                          */

+#define FDCAN_PSR_ACT_Pos         (3U)

+#define FDCAN_PSR_ACT_Msk         (0x3UL << FDCAN_PSR_ACT_Pos)                 /*!< 0x00000018 */

+#define FDCAN_PSR_ACT             FDCAN_PSR_ACT_Msk                            /*!<Activity                                 */

+#define FDCAN_PSR_EP_Pos          (5U)

+#define FDCAN_PSR_EP_Msk          (0x1UL << FDCAN_PSR_EP_Pos)                  /*!< 0x00000020 */

+#define FDCAN_PSR_EP              FDCAN_PSR_EP_Msk                             /*!<Error Passive                            */

+#define FDCAN_PSR_EW_Pos          (6U)

+#define FDCAN_PSR_EW_Msk          (0x1UL << FDCAN_PSR_EW_Pos)                  /*!< 0x00000040 */

+#define FDCAN_PSR_EW              FDCAN_PSR_EW_Msk                             /*!<Warning Status                           */

+#define FDCAN_PSR_BO_Pos          (7U)

+#define FDCAN_PSR_BO_Msk          (0x1UL << FDCAN_PSR_BO_Pos)                  /*!< 0x00000080 */

+#define FDCAN_PSR_BO              FDCAN_PSR_BO_Msk                             /*!<Bus_Off Status                           */

+#define FDCAN_PSR_DLEC_Pos        (8U)

+#define FDCAN_PSR_DLEC_Msk        (0x7UL << FDCAN_PSR_DLEC_Pos)                /*!< 0x00000700 */

+#define FDCAN_PSR_DLEC            FDCAN_PSR_DLEC_Msk                           /*!<Data Last Error Code                     */

+#define FDCAN_PSR_RESI_Pos        (11U)

+#define FDCAN_PSR_RESI_Msk        (0x1UL << FDCAN_PSR_RESI_Pos)                /*!< 0x00000800 */

+#define FDCAN_PSR_RESI            FDCAN_PSR_RESI_Msk                           /*!<ESI flag of last received FDCAN Message  */

+#define FDCAN_PSR_RBRS_Pos        (12U)

+#define FDCAN_PSR_RBRS_Msk        (0x1UL << FDCAN_PSR_RBRS_Pos)                /*!< 0x00001000 */

+#define FDCAN_PSR_RBRS            FDCAN_PSR_RBRS_Msk                           /*!<BRS flag of last received FDCAN Message  */

+#define FDCAN_PSR_REDL_Pos        (13U)

+#define FDCAN_PSR_REDL_Msk        (0x1UL << FDCAN_PSR_REDL_Pos)                /*!< 0x00002000 */

+#define FDCAN_PSR_REDL            FDCAN_PSR_REDL_Msk                           /*!<Received FDCAN Message                   */

+#define FDCAN_PSR_PXE_Pos         (14U)

+#define FDCAN_PSR_PXE_Msk         (0x1UL << FDCAN_PSR_PXE_Pos)                 /*!< 0x00004000 */

+#define FDCAN_PSR_PXE             FDCAN_PSR_PXE_Msk                            /*!<Protocol Exception Event                 */

+#define FDCAN_PSR_TDCV_Pos        (16U)

+#define FDCAN_PSR_TDCV_Msk        (0x7FUL << FDCAN_PSR_TDCV_Pos)               /*!< 0x007F0000 */

+#define FDCAN_PSR_TDCV            FDCAN_PSR_TDCV_Msk                           /*!<Transmitter Delay Compensation Value     */

+

+/*****************  Bit definition for FDCAN_TDCR register  ********************/

+#define FDCAN_TDCR_TDCF_Pos       (0U)

+#define FDCAN_TDCR_TDCF_Msk       (0x7FUL << FDCAN_TDCR_TDCF_Pos)              /*!< 0x0000007F */

+#define FDCAN_TDCR_TDCF           FDCAN_TDCR_TDCF_Msk                          /*!<Transmitter Delay Compensation Filter    */

+#define FDCAN_TDCR_TDCO_Pos       (8U)

+#define FDCAN_TDCR_TDCO_Msk       (0x7FUL << FDCAN_TDCR_TDCO_Pos)              /*!< 0x00007F00 */

+#define FDCAN_TDCR_TDCO           FDCAN_TDCR_TDCO_Msk                          /*!<Transmitter Delay Compensation Offset    */

+

+/*****************  Bit definition for FDCAN_IR register  **********************/

+#define FDCAN_IR_RF0N_Pos         (0U)

+#define FDCAN_IR_RF0N_Msk         (0x1UL << FDCAN_IR_RF0N_Pos)                 /*!< 0x00000001 */

+#define FDCAN_IR_RF0N             FDCAN_IR_RF0N_Msk                            /*!<Rx FIFO 0 New Message                    */

+#define FDCAN_IR_RF0W_Pos         (1U)

+#define FDCAN_IR_RF0W_Msk         (0x1UL << FDCAN_IR_RF0W_Pos)                 /*!< 0x00000002 */

+#define FDCAN_IR_RF0W             FDCAN_IR_RF0W_Msk                            /*!<Rx FIFO 0 Watermark Reached              */

+#define FDCAN_IR_RF0F_Pos         (2U)

+#define FDCAN_IR_RF0F_Msk         (0x1UL << FDCAN_IR_RF0F_Pos)                 /*!< 0x00000004 */

+#define FDCAN_IR_RF0F             FDCAN_IR_RF0F_Msk                            /*!<Rx FIFO 0 Full                           */

+#define FDCAN_IR_RF0L_Pos         (3U)

+#define FDCAN_IR_RF0L_Msk         (0x1UL << FDCAN_IR_RF0L_Pos)                 /*!< 0x00000008 */

+#define FDCAN_IR_RF0L             FDCAN_IR_RF0L_Msk                            /*!<Rx FIFO 0 Message Lost                   */

+#define FDCAN_IR_RF1N_Pos         (4U)

+#define FDCAN_IR_RF1N_Msk         (0x1UL << FDCAN_IR_RF1N_Pos)                 /*!< 0x00000010 */

+#define FDCAN_IR_RF1N             FDCAN_IR_RF1N_Msk                            /*!<Rx FIFO 1 New Message                    */

+#define FDCAN_IR_RF1W_Pos         (5U)

+#define FDCAN_IR_RF1W_Msk         (0x1UL << FDCAN_IR_RF1W_Pos)                 /*!< 0x00000020 */

+#define FDCAN_IR_RF1W             FDCAN_IR_RF1W_Msk                            /*!<Rx FIFO 1 Watermark Reached              */

+#define FDCAN_IR_RF1F_Pos         (6U)

+#define FDCAN_IR_RF1F_Msk         (0x1UL << FDCAN_IR_RF1F_Pos)                 /*!< 0x00000040 */

+#define FDCAN_IR_RF1F             FDCAN_IR_RF1F_Msk                            /*!<Rx FIFO 1 Full                           */

+#define FDCAN_IR_RF1L_Pos         (7U)

+#define FDCAN_IR_RF1L_Msk         (0x1UL << FDCAN_IR_RF1L_Pos)                 /*!< 0x00000080 */

+#define FDCAN_IR_RF1L             FDCAN_IR_RF1L_Msk                            /*!<Rx FIFO 1 Message Lost                   */

+#define FDCAN_IR_HPM_Pos          (8U)

+#define FDCAN_IR_HPM_Msk          (0x1UL << FDCAN_IR_HPM_Pos)                  /*!< 0x00000100 */

+#define FDCAN_IR_HPM              FDCAN_IR_HPM_Msk                             /*!<High Priority Message                    */

+#define FDCAN_IR_TC_Pos           (9U)

+#define FDCAN_IR_TC_Msk           (0x1UL << FDCAN_IR_TC_Pos)                   /*!< 0x00000200 */

+#define FDCAN_IR_TC               FDCAN_IR_TC_Msk                              /*!<Transmission Completed                   */

+#define FDCAN_IR_TCF_Pos          (10U)

+#define FDCAN_IR_TCF_Msk          (0x1UL << FDCAN_IR_TCF_Pos)                  /*!< 0x00000400 */

+#define FDCAN_IR_TCF              FDCAN_IR_TCF_Msk                             /*!<Transmission Cancellation Finished       */

+#define FDCAN_IR_TFE_Pos          (11U)

+#define FDCAN_IR_TFE_Msk          (0x1UL << FDCAN_IR_TFE_Pos)                  /*!< 0x00000800 */

+#define FDCAN_IR_TFE              FDCAN_IR_TFE_Msk                             /*!<Tx FIFO Empty                            */

+#define FDCAN_IR_TEFN_Pos         (12U)

+#define FDCAN_IR_TEFN_Msk         (0x1UL << FDCAN_IR_TEFN_Pos)                 /*!< 0x00001000 */

+#define FDCAN_IR_TEFN             FDCAN_IR_TEFN_Msk                            /*!<Tx Event FIFO New Entry                  */

+#define FDCAN_IR_TEFW_Pos         (13U)

+#define FDCAN_IR_TEFW_Msk         (0x1UL << FDCAN_IR_TEFW_Pos)                 /*!< 0x00002000 */

+#define FDCAN_IR_TEFW             FDCAN_IR_TEFW_Msk                            /*!<Tx Event FIFO Watermark Reached          */

+#define FDCAN_IR_TEFF_Pos         (14U)

+#define FDCAN_IR_TEFF_Msk         (0x1UL << FDCAN_IR_TEFF_Pos)                 /*!< 0x00004000 */

+#define FDCAN_IR_TEFF             FDCAN_IR_TEFF_Msk                            /*!<Tx Event FIFO Full                       */

+#define FDCAN_IR_TEFL_Pos         (15U)

+#define FDCAN_IR_TEFL_Msk         (0x1UL << FDCAN_IR_TEFL_Pos)                 /*!< 0x00008000 */

+#define FDCAN_IR_TEFL             FDCAN_IR_TEFL_Msk                            /*!<Tx Event FIFO Element Lost               */

+#define FDCAN_IR_TSW_Pos          (16U)

+#define FDCAN_IR_TSW_Msk          (0x1UL << FDCAN_IR_TSW_Pos)                  /*!< 0x00010000 */

+#define FDCAN_IR_TSW              FDCAN_IR_TSW_Msk                             /*!<Timestamp Wraparound                     */

+#define FDCAN_IR_MRAF_Pos         (17U)

+#define FDCAN_IR_MRAF_Msk         (0x1UL << FDCAN_IR_MRAF_Pos)                 /*!< 0x00020000 */

+#define FDCAN_IR_MRAF             FDCAN_IR_MRAF_Msk                            /*!<Message RAM Access Failure               */

+#define FDCAN_IR_TOO_Pos          (18U)

+#define FDCAN_IR_TOO_Msk          (0x1UL << FDCAN_IR_TOO_Pos)                  /*!< 0x00040000 */

+#define FDCAN_IR_TOO              FDCAN_IR_TOO_Msk                             /*!<Timeout Occurred                         */

+#define FDCAN_IR_DRX_Pos          (19U)

+#define FDCAN_IR_DRX_Msk          (0x1UL << FDCAN_IR_DRX_Pos)                  /*!< 0x00080000 */

+#define FDCAN_IR_DRX              FDCAN_IR_DRX_Msk                             /*!<Message stored to Dedicated Rx Buffer    */

+#define FDCAN_IR_ELO_Pos          (22U)

+#define FDCAN_IR_ELO_Msk          (0x1UL << FDCAN_IR_ELO_Pos)                  /*!< 0x00400000 */

+#define FDCAN_IR_ELO              FDCAN_IR_ELO_Msk                             /*!<Error Logging Overflow                   */

+#define FDCAN_IR_EP_Pos           (23U)

+#define FDCAN_IR_EP_Msk           (0x1UL << FDCAN_IR_EP_Pos)                   /*!< 0x00800000 */

+#define FDCAN_IR_EP               FDCAN_IR_EP_Msk                              /*!<Error Passive                            */

+#define FDCAN_IR_EW_Pos           (24U)

+#define FDCAN_IR_EW_Msk           (0x1UL << FDCAN_IR_EW_Pos)                   /*!< 0x01000000 */

+#define FDCAN_IR_EW               FDCAN_IR_EW_Msk                              /*!<Warning Status                           */

+#define FDCAN_IR_BO_Pos           (25U)

+#define FDCAN_IR_BO_Msk           (0x1UL << FDCAN_IR_BO_Pos)                   /*!< 0x02000000 */

+#define FDCAN_IR_BO               FDCAN_IR_BO_Msk                              /*!<Bus_Off Status                           */

+#define FDCAN_IR_WDI_Pos          (26U)

+#define FDCAN_IR_WDI_Msk          (0x1UL << FDCAN_IR_WDI_Pos)                  /*!< 0x04000000 */

+#define FDCAN_IR_WDI              FDCAN_IR_WDI_Msk                             /*!<Watchdog Interrupt                       */

+#define FDCAN_IR_PEA_Pos          (27U)

+#define FDCAN_IR_PEA_Msk          (0x1UL << FDCAN_IR_PEA_Pos)                  /*!< 0x08000000 */

+#define FDCAN_IR_PEA              FDCAN_IR_PEA_Msk                             /*!<Protocol Error in Arbitration Phase      */

+#define FDCAN_IR_PED_Pos          (28U)

+#define FDCAN_IR_PED_Msk          (0x1UL << FDCAN_IR_PED_Pos)                  /*!< 0x10000000 */

+#define FDCAN_IR_PED              FDCAN_IR_PED_Msk                             /*!<Protocol Error in Data Phase             */

+#define FDCAN_IR_ARA_Pos          (29U)

+#define FDCAN_IR_ARA_Msk          (0x1UL << FDCAN_IR_ARA_Pos)                  /*!< 0x20000000 */

+#define FDCAN_IR_ARA              FDCAN_IR_ARA_Msk                             /*!<Access to Reserved Address               */

+

+/*****************  Bit definition for FDCAN_IE register  **********************/

+#define FDCAN_IE_RF0NE_Pos        (0U)

+#define FDCAN_IE_RF0NE_Msk        (0x1UL << FDCAN_IE_RF0NE_Pos)                /*!< 0x00000001 */

+#define FDCAN_IE_RF0NE            FDCAN_IE_RF0NE_Msk                           /*!<Rx FIFO 0 New Message Enable                 */

+#define FDCAN_IE_RF0WE_Pos        (1U)

+#define FDCAN_IE_RF0WE_Msk        (0x1UL << FDCAN_IE_RF0WE_Pos)                /*!< 0x00000002 */

+#define FDCAN_IE_RF0WE            FDCAN_IE_RF0WE_Msk                           /*!<Rx FIFO 0 Watermark Reached Enable           */

+#define FDCAN_IE_RF0FE_Pos        (2U)

+#define FDCAN_IE_RF0FE_Msk        (0x1UL << FDCAN_IE_RF0FE_Pos)                /*!< 0x00000004 */

+#define FDCAN_IE_RF0FE            FDCAN_IE_RF0FE_Msk                           /*!<Rx FIFO 0 Full Enable                        */

+#define FDCAN_IE_RF0LE_Pos        (3U)

+#define FDCAN_IE_RF0LE_Msk        (0x1UL << FDCAN_IE_RF0LE_Pos)                /*!< 0x00000008 */

+#define FDCAN_IE_RF0LE            FDCAN_IE_RF0LE_Msk                           /*!<Rx FIFO 0 Message Lost Enable                */

+#define FDCAN_IE_RF1NE_Pos        (4U)

+#define FDCAN_IE_RF1NE_Msk        (0x1UL << FDCAN_IE_RF1NE_Pos)                /*!< 0x00000010 */

+#define FDCAN_IE_RF1NE            FDCAN_IE_RF1NE_Msk                           /*!<Rx FIFO 1 New Message Enable                 */

+#define FDCAN_IE_RF1WE_Pos        (5U)

+#define FDCAN_IE_RF1WE_Msk        (0x1UL << FDCAN_IE_RF1WE_Pos)                /*!< 0x00000020 */

+#define FDCAN_IE_RF1WE            FDCAN_IE_RF1WE_Msk                           /*!<Rx FIFO 1 Watermark Reached Enable           */

+#define FDCAN_IE_RF1FE_Pos        (6U)

+#define FDCAN_IE_RF1FE_Msk        (0x1UL << FDCAN_IE_RF1FE_Pos)                /*!< 0x00000040 */

+#define FDCAN_IE_RF1FE            FDCAN_IE_RF1FE_Msk                           /*!<Rx FIFO 1 Full Enable                        */

+#define FDCAN_IE_RF1LE_Pos        (7U)

+#define FDCAN_IE_RF1LE_Msk        (0x1UL << FDCAN_IE_RF1LE_Pos)                /*!< 0x00000080 */

+#define FDCAN_IE_RF1LE            FDCAN_IE_RF1LE_Msk                           /*!<Rx FIFO 1 Message Lost Enable                */

+#define FDCAN_IE_HPME_Pos         (8U)

+#define FDCAN_IE_HPME_Msk         (0x1UL << FDCAN_IE_HPME_Pos)                 /*!< 0x00000100 */

+#define FDCAN_IE_HPME             FDCAN_IE_HPME_Msk                            /*!<High Priority Message Enable                 */

+#define FDCAN_IE_TCE_Pos          (9U)

+#define FDCAN_IE_TCE_Msk          (0x1UL << FDCAN_IE_TCE_Pos)                  /*!< 0x00000200 */

+#define FDCAN_IE_TCE              FDCAN_IE_TCE_Msk                             /*!<Transmission Completed Enable                */

+#define FDCAN_IE_TCFE_Pos         (10U)

+#define FDCAN_IE_TCFE_Msk         (0x1UL << FDCAN_IE_TCFE_Pos)                 /*!< 0x00000400 */

+#define FDCAN_IE_TCFE             FDCAN_IE_TCFE_Msk                            /*!<Transmission Cancellation Finished Enable    */

+#define FDCAN_IE_TFEE_Pos         (11U)

+#define FDCAN_IE_TFEE_Msk         (0x1UL << FDCAN_IE_TFEE_Pos)                 /*!< 0x00000800 */

+#define FDCAN_IE_TFEE             FDCAN_IE_TFEE_Msk                            /*!<Tx FIFO Empty Enable                         */

+#define FDCAN_IE_TEFNE_Pos        (12U)

+#define FDCAN_IE_TEFNE_Msk        (0x1UL << FDCAN_IE_TEFNE_Pos)                /*!< 0x00001000 */

+#define FDCAN_IE_TEFNE            FDCAN_IE_TEFNE_Msk                           /*!<Tx Event FIFO New Entry Enable               */

+#define FDCAN_IE_TEFWE_Pos        (13U)

+#define FDCAN_IE_TEFWE_Msk        (0x1UL << FDCAN_IE_TEFWE_Pos)                /*!< 0x00002000 */

+#define FDCAN_IE_TEFWE            FDCAN_IE_TEFWE_Msk                           /*!<Tx Event FIFO Watermark Reached Enable       */

+#define FDCAN_IE_TEFFE_Pos        (14U)

+#define FDCAN_IE_TEFFE_Msk        (0x1UL << FDCAN_IE_TEFFE_Pos)                /*!< 0x00004000 */

+#define FDCAN_IE_TEFFE            FDCAN_IE_TEFFE_Msk                           /*!<Tx Event FIFO Full Enable                    */

+#define FDCAN_IE_TEFLE_Pos        (15U)

+#define FDCAN_IE_TEFLE_Msk        (0x1UL << FDCAN_IE_TEFLE_Pos)                /*!< 0x00008000 */

+#define FDCAN_IE_TEFLE            FDCAN_IE_TEFLE_Msk                           /*!<Tx Event FIFO Element Lost Enable            */

+#define FDCAN_IE_TSWE_Pos         (16U)

+#define FDCAN_IE_TSWE_Msk         (0x1UL << FDCAN_IE_TSWE_Pos)                 /*!< 0x00010000 */

+#define FDCAN_IE_TSWE             FDCAN_IE_TSWE_Msk                            /*!<Timestamp Wraparound Enable                  */

+#define FDCAN_IE_MRAFE_Pos        (17U)

+#define FDCAN_IE_MRAFE_Msk        (0x1UL << FDCAN_IE_MRAFE_Pos)                /*!< 0x00020000 */

+#define FDCAN_IE_MRAFE            FDCAN_IE_MRAFE_Msk                           /*!<Message RAM Access Failure Enable            */

+#define FDCAN_IE_TOOE_Pos         (18U)

+#define FDCAN_IE_TOOE_Msk         (0x1UL << FDCAN_IE_TOOE_Pos)                 /*!< 0x00040000 */

+#define FDCAN_IE_TOOE             FDCAN_IE_TOOE_Msk                            /*!<Timeout Occurred Enable                      */

+#define FDCAN_IE_DRXE_Pos         (19U)

+#define FDCAN_IE_DRXE_Msk         (0x1UL << FDCAN_IE_DRXE_Pos)                 /*!< 0x00080000 */

+#define FDCAN_IE_DRXE             FDCAN_IE_DRXE_Msk                            /*!<Message stored to Dedicated Rx Buffer Enable */

+#define FDCAN_IE_BECE_Pos         (20U)

+#define FDCAN_IE_BECE_Msk         (0x1UL << FDCAN_IE_BECE_Pos)                 /*!< 0x00100000 */

+#define FDCAN_IE_BECE             FDCAN_IE_BECE_Msk                            /*!<Bit Error Corrected Interrupt Enable         */

+#define FDCAN_IE_BEUE_Pos         (21U)

+#define FDCAN_IE_BEUE_Msk         (0x1UL << FDCAN_IE_BEUE_Pos)                 /*!< 0x00200000 */

+#define FDCAN_IE_BEUE             FDCAN_IE_BEUE_Msk                            /*!<Bit Error Uncorrected Interrupt Enable       */

+#define FDCAN_IE_ELOE_Pos         (22U)

+#define FDCAN_IE_ELOE_Msk         (0x1UL << FDCAN_IE_ELOE_Pos)                 /*!< 0x00400000 */

+#define FDCAN_IE_ELOE             FDCAN_IE_ELOE_Msk                            /*!<Error Logging Overflow Enable                */

+#define FDCAN_IE_EPE_Pos          (23U)

+#define FDCAN_IE_EPE_Msk          (0x1UL << FDCAN_IE_EPE_Pos)                  /*!< 0x00800000 */

+#define FDCAN_IE_EPE              FDCAN_IE_EPE_Msk                             /*!<Error Passive Enable                         */

+#define FDCAN_IE_EWE_Pos          (24U)

+#define FDCAN_IE_EWE_Msk          (0x1UL << FDCAN_IE_EWE_Pos)                  /*!< 0x01000000 */

+#define FDCAN_IE_EWE              FDCAN_IE_EWE_Msk                             /*!<Warning Status Enable                        */

+#define FDCAN_IE_BOE_Pos          (25U)

+#define FDCAN_IE_BOE_Msk          (0x1UL << FDCAN_IE_BOE_Pos)                  /*!< 0x02000000 */

+#define FDCAN_IE_BOE              FDCAN_IE_BOE_Msk                             /*!<Bus_Off Status Enable                        */

+#define FDCAN_IE_WDIE_Pos         (26U)

+#define FDCAN_IE_WDIE_Msk         (0x1UL << FDCAN_IE_WDIE_Pos)                 /*!< 0x04000000 */

+#define FDCAN_IE_WDIE             FDCAN_IE_WDIE_Msk                            /*!<Watchdog Interrupt Enable                    */

+#define FDCAN_IE_PEAE_Pos         (27U)

+#define FDCAN_IE_PEAE_Msk         (0x1UL << FDCAN_IE_PEAE_Pos)                 /*!< 0x08000000 */

+#define FDCAN_IE_PEAE             FDCAN_IE_PEAE_Msk                            /*!<Protocol Error in Arbitration Phase Enable   */

+#define FDCAN_IE_PEDE_Pos         (28U)

+#define FDCAN_IE_PEDE_Msk         (0x1UL << FDCAN_IE_PEDE_Pos)                 /*!< 0x10000000 */

+#define FDCAN_IE_PEDE             FDCAN_IE_PEDE_Msk                            /*!<Protocol Error in Data Phase Enable          */

+#define FDCAN_IE_ARAE_Pos         (29U)

+#define FDCAN_IE_ARAE_Msk         (0x1UL << FDCAN_IE_ARAE_Pos)                 /*!< 0x20000000 */

+#define FDCAN_IE_ARAE             FDCAN_IE_ARAE_Msk                            /*!<Access to Reserved Address Enable            */

+

+/*****************  Bit definition for FDCAN_ILS register  **********************/

+#define FDCAN_ILS_RF0NL_Pos       (0U)

+#define FDCAN_ILS_RF0NL_Msk       (0x1UL << FDCAN_ILS_RF0NL_Pos)               /*!< 0x00000001 */

+#define FDCAN_ILS_RF0NL           FDCAN_ILS_RF0NL_Msk                          /*!<Rx FIFO 0 New Message Line                  */

+#define FDCAN_ILS_RF0WL_Pos       (1U)

+#define FDCAN_ILS_RF0WL_Msk       (0x1UL << FDCAN_ILS_RF0WL_Pos)               /*!< 0x00000002 */

+#define FDCAN_ILS_RF0WL           FDCAN_ILS_RF0WL_Msk                          /*!<Rx FIFO 0 Watermark Reached Line            */

+#define FDCAN_ILS_RF0FL_Pos       (2U)

+#define FDCAN_ILS_RF0FL_Msk       (0x1UL << FDCAN_ILS_RF0FL_Pos)               /*!< 0x00000004 */

+#define FDCAN_ILS_RF0FL           FDCAN_ILS_RF0FL_Msk                          /*!<Rx FIFO 0 Full Line                         */

+#define FDCAN_ILS_RF0LL_Pos       (3U)

+#define FDCAN_ILS_RF0LL_Msk       (0x1UL << FDCAN_ILS_RF0LL_Pos)               /*!< 0x00000008 */

+#define FDCAN_ILS_RF0LL           FDCAN_ILS_RF0LL_Msk                          /*!<Rx FIFO 0 Message Lost Line                 */

+#define FDCAN_ILS_RF1NL_Pos       (4U)

+#define FDCAN_ILS_RF1NL_Msk       (0x1UL << FDCAN_ILS_RF1NL_Pos)               /*!< 0x00000010 */

+#define FDCAN_ILS_RF1NL           FDCAN_ILS_RF1NL_Msk                          /*!<Rx FIFO 1 New Message Line                  */

+#define FDCAN_ILS_RF1WL_Pos       (5U)

+#define FDCAN_ILS_RF1WL_Msk       (0x1UL << FDCAN_ILS_RF1WL_Pos)               /*!< 0x00000020 */

+#define FDCAN_ILS_RF1WL           FDCAN_ILS_RF1WL_Msk                          /*!<Rx FIFO 1 Watermark Reached Line            */

+#define FDCAN_ILS_RF1FL_Pos       (6U)

+#define FDCAN_ILS_RF1FL_Msk       (0x1UL << FDCAN_ILS_RF1FL_Pos)               /*!< 0x00000040 */

+#define FDCAN_ILS_RF1FL           FDCAN_ILS_RF1FL_Msk                          /*!<Rx FIFO 1 Full Line                         */

+#define FDCAN_ILS_RF1LL_Pos       (7U)

+#define FDCAN_ILS_RF1LL_Msk       (0x1UL << FDCAN_ILS_RF1LL_Pos)               /*!< 0x00000080 */

+#define FDCAN_ILS_RF1LL           FDCAN_ILS_RF1LL_Msk                          /*!<Rx FIFO 1 Message Lost Line                 */

+#define FDCAN_ILS_HPML_Pos        (8U)

+#define FDCAN_ILS_HPML_Msk        (0x1UL << FDCAN_ILS_HPML_Pos)                /*!< 0x00000100 */

+#define FDCAN_ILS_HPML            FDCAN_ILS_HPML_Msk                           /*!<High Priority Message Line                  */

+#define FDCAN_ILS_TCL_Pos         (9U)

+#define FDCAN_ILS_TCL_Msk         (0x1UL << FDCAN_ILS_TCL_Pos)                 /*!< 0x00000200 */

+#define FDCAN_ILS_TCL             FDCAN_ILS_TCL_Msk                            /*!<Transmission Completed Line                 */

+#define FDCAN_ILS_TCFL_Pos        (10U)

+#define FDCAN_ILS_TCFL_Msk        (0x1UL << FDCAN_ILS_TCFL_Pos)                /*!< 0x00000400 */

+#define FDCAN_ILS_TCFL            FDCAN_ILS_TCFL_Msk                           /*!<Transmission Cancellation Finished Line     */

+#define FDCAN_ILS_TFEL_Pos        (11U)

+#define FDCAN_ILS_TFEL_Msk        (0x1UL << FDCAN_ILS_TFEL_Pos)                /*!< 0x00000800 */

+#define FDCAN_ILS_TFEL            FDCAN_ILS_TFEL_Msk                           /*!<Tx FIFO Empty Line                          */

+#define FDCAN_ILS_TEFNL_Pos       (12U)

+#define FDCAN_ILS_TEFNL_Msk       (0x1UL << FDCAN_ILS_TEFNL_Pos)               /*!< 0x00001000 */

+#define FDCAN_ILS_TEFNL           FDCAN_ILS_TEFNL_Msk                          /*!<Tx Event FIFO New Entry Line                */

+#define FDCAN_ILS_TEFWL_Pos       (13U)

+#define FDCAN_ILS_TEFWL_Msk       (0x1UL << FDCAN_ILS_TEFWL_Pos)               /*!< 0x00002000 */

+#define FDCAN_ILS_TEFWL           FDCAN_ILS_TEFWL_Msk                          /*!<Tx Event FIFO Watermark Reached Line        */

+#define FDCAN_ILS_TEFFL_Pos       (14U)

+#define FDCAN_ILS_TEFFL_Msk       (0x1UL << FDCAN_ILS_TEFFL_Pos)               /*!< 0x00004000 */

+#define FDCAN_ILS_TEFFL           FDCAN_ILS_TEFFL_Msk                          /*!<Tx Event FIFO Full Line                     */

+#define FDCAN_ILS_TEFLL_Pos       (15U)

+#define FDCAN_ILS_TEFLL_Msk       (0x1UL << FDCAN_ILS_TEFLL_Pos)               /*!< 0x00008000 */

+#define FDCAN_ILS_TEFLL           FDCAN_ILS_TEFLL_Msk                          /*!<Tx Event FIFO Element Lost Line             */

+#define FDCAN_ILS_TSWL_Pos        (16U)

+#define FDCAN_ILS_TSWL_Msk        (0x1UL << FDCAN_ILS_TSWL_Pos)                /*!< 0x00010000 */

+#define FDCAN_ILS_TSWL            FDCAN_ILS_TSWL_Msk                           /*!<Timestamp Wraparound Line                   */

+#define FDCAN_ILS_MRAFE_Pos       (17U)

+#define FDCAN_ILS_MRAFE_Msk       (0x1UL << FDCAN_ILS_MRAFE_Pos)               /*!< 0x00020000 */

+#define FDCAN_ILS_MRAFE           FDCAN_ILS_MRAFE_Msk                          /*!<Message RAM Access Failure Line             */

+#define FDCAN_ILS_TOOE_Pos        (18U)

+#define FDCAN_ILS_TOOE_Msk        (0x1UL << FDCAN_ILS_TOOE_Pos)                /*!< 0x00040000 */

+#define FDCAN_ILS_TOOE            FDCAN_ILS_TOOE_Msk                           /*!<Timeout Occurred Line                       */

+#define FDCAN_ILS_DRXE_Pos        (19U)

+#define FDCAN_ILS_DRXE_Msk        (0x1UL << FDCAN_ILS_DRXE_Pos)                /*!< 0x00080000 */

+#define FDCAN_ILS_DRXE            FDCAN_ILS_DRXE_Msk                           /*!<Message stored to Dedicated Rx Buffer Line  */

+#define FDCAN_ILS_BECE_Pos        (20U)

+#define FDCAN_ILS_BECE_Msk        (0x1UL << FDCAN_ILS_BECE_Pos)                /*!< 0x00100000 */

+#define FDCAN_ILS_BECE            FDCAN_ILS_BECE_Msk                           /*!<Bit Error Corrected Interrupt Line          */

+#define FDCAN_ILS_BEUE_Pos        (21U)

+#define FDCAN_ILS_BEUE_Msk        (0x1UL << FDCAN_ILS_BEUE_Pos)                /*!< 0x00200000 */

+#define FDCAN_ILS_BEUE            FDCAN_ILS_BEUE_Msk                           /*!<Bit Error Uncorrected Interrupt Line        */

+#define FDCAN_ILS_ELOE_Pos        (22U)

+#define FDCAN_ILS_ELOE_Msk        (0x1UL << FDCAN_ILS_ELOE_Pos)                /*!< 0x00400000 */

+#define FDCAN_ILS_ELOE            FDCAN_ILS_ELOE_Msk                           /*!<Error Logging Overflow Line                 */

+#define FDCAN_ILS_EPE_Pos         (23U)

+#define FDCAN_ILS_EPE_Msk         (0x1UL << FDCAN_ILS_EPE_Pos)                 /*!< 0x00800000 */

+#define FDCAN_ILS_EPE             FDCAN_ILS_EPE_Msk                            /*!<Error Passive Line                          */

+#define FDCAN_ILS_EWE_Pos         (24U)

+#define FDCAN_ILS_EWE_Msk         (0x1UL << FDCAN_ILS_EWE_Pos)                 /*!< 0x01000000 */

+#define FDCAN_ILS_EWE             FDCAN_ILS_EWE_Msk                            /*!<Warning Status Line                         */

+#define FDCAN_ILS_BOE_Pos         (25U)

+#define FDCAN_ILS_BOE_Msk         (0x1UL << FDCAN_ILS_BOE_Pos)                 /*!< 0x02000000 */

+#define FDCAN_ILS_BOE             FDCAN_ILS_BOE_Msk                            /*!<Bus_Off Status Line                         */

+#define FDCAN_ILS_WDIE_Pos        (26U)

+#define FDCAN_ILS_WDIE_Msk        (0x1UL << FDCAN_ILS_WDIE_Pos)                /*!< 0x04000000 */

+#define FDCAN_ILS_WDIE            FDCAN_ILS_WDIE_Msk                           /*!<Watchdog Interrupt Line                     */

+#define FDCAN_ILS_PEAE_Pos        (27U)

+#define FDCAN_ILS_PEAE_Msk        (0x1UL << FDCAN_ILS_PEAE_Pos)                /*!< 0x08000000 */

+#define FDCAN_ILS_PEAE            FDCAN_ILS_PEAE_Msk                           /*!<Protocol Error in Arbitration Phase Line    */

+#define FDCAN_ILS_PEDE_Pos        (28U)

+#define FDCAN_ILS_PEDE_Msk        (0x1UL << FDCAN_ILS_PEDE_Pos)                /*!< 0x10000000 */

+#define FDCAN_ILS_PEDE            FDCAN_ILS_PEDE_Msk                           /*!<Protocol Error in Data Phase Line           */

+#define FDCAN_ILS_ARAE_Pos        (29U)

+#define FDCAN_ILS_ARAE_Msk        (0x1UL << FDCAN_ILS_ARAE_Pos)                /*!< 0x20000000 */

+#define FDCAN_ILS_ARAE            FDCAN_ILS_ARAE_Msk                           /*!<Access to Reserved Address Line             */

+

+/*****************  Bit definition for FDCAN_ILE register  **********************/

+#define FDCAN_ILE_EINT0_Pos       (0U)

+#define FDCAN_ILE_EINT0_Msk       (0x1UL << FDCAN_ILE_EINT0_Pos)               /*!< 0x00000001 */

+#define FDCAN_ILE_EINT0           FDCAN_ILE_EINT0_Msk                          /*!<Enable Interrupt Line 0                   */

+#define FDCAN_ILE_EINT1_Pos       (1U)

+#define FDCAN_ILE_EINT1_Msk       (0x1UL << FDCAN_ILE_EINT1_Pos)               /*!< 0x00000002 */

+#define FDCAN_ILE_EINT1           FDCAN_ILE_EINT1_Msk                          /*!<Enable Interrupt Line 1                   */

+

+/*****************  Bit definition for FDCAN_GFC register  **********************/

+#define FDCAN_GFC_RRFE_Pos        (0U)

+#define FDCAN_GFC_RRFE_Msk        (0x1UL << FDCAN_GFC_RRFE_Pos)                /*!< 0x00000001 */

+#define FDCAN_GFC_RRFE            FDCAN_GFC_RRFE_Msk                           /*!<Reject Remote Frames Extended             */

+#define FDCAN_GFC_RRFS_Pos        (1U)

+#define FDCAN_GFC_RRFS_Msk        (0x1UL << FDCAN_GFC_RRFS_Pos)                /*!< 0x00000002 */

+#define FDCAN_GFC_RRFS            FDCAN_GFC_RRFS_Msk                           /*!<Reject Remote Frames Standard             */

+#define FDCAN_GFC_ANFE_Pos        (2U)

+#define FDCAN_GFC_ANFE_Msk        (0x3UL << FDCAN_GFC_ANFE_Pos)                /*!< 0x0000000C */

+#define FDCAN_GFC_ANFE            FDCAN_GFC_ANFE_Msk                           /*!<Accept Non-matching Frames Extended       */

+#define FDCAN_GFC_ANFS_Pos        (4U)

+#define FDCAN_GFC_ANFS_Msk        (0x3UL << FDCAN_GFC_ANFS_Pos)                /*!< 0x00000030 */

+#define FDCAN_GFC_ANFS            FDCAN_GFC_ANFS_Msk                           /*!<Accept Non-matching Frames Standard       */

+

+/*****************  Bit definition for FDCAN_SIDFC register  ********************/

+#define FDCAN_SIDFC_FLSSA_Pos     (2U)

+#define FDCAN_SIDFC_FLSSA_Msk     (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)          /*!< 0x0000FFFC */

+#define FDCAN_SIDFC_FLSSA         FDCAN_SIDFC_FLSSA_Msk                        /*!<Filter List Standard Start Address        */

+#define FDCAN_SIDFC_LSS_Pos       (16U)

+#define FDCAN_SIDFC_LSS_Msk       (0xFFUL << FDCAN_SIDFC_LSS_Pos)              /*!< 0x00FF0000 */

+#define FDCAN_SIDFC_LSS           FDCAN_SIDFC_LSS_Msk                          /*!<List Size Standard                        */

+

+/*****************  Bit definition for FDCAN_XIDFC register  ********************/

+#define FDCAN_XIDFC_FLESA_Pos     (2U)

+#define FDCAN_XIDFC_FLESA_Msk     (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)          /*!< 0x0000FFFC */

+#define FDCAN_XIDFC_FLESA         FDCAN_XIDFC_FLESA_Msk                        /*!<Filter List Standard Start Address        */

+#define FDCAN_XIDFC_LSE_Pos       (16U)

+#define FDCAN_XIDFC_LSE_Msk       (0x7FUL << FDCAN_XIDFC_LSE_Pos)              /*!< 0x007F0000 */

+#define FDCAN_XIDFC_LSE           FDCAN_XIDFC_LSE_Msk                          /*!<List Size Extended                        */

+

+/*****************  Bit definition for FDCAN_XIDAM register  ********************/

+#define FDCAN_XIDAM_EIDM_Pos      (0U)

+#define FDCAN_XIDAM_EIDM_Msk      (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)       /*!< 0x1FFFFFFF */

+#define FDCAN_XIDAM_EIDM          FDCAN_XIDAM_EIDM_Msk                         /*!<Extended ID Mask                          */

+

+/*****************  Bit definition for FDCAN_HPMS register  *********************/

+#define FDCAN_HPMS_BIDX_Pos       (0U)

+#define FDCAN_HPMS_BIDX_Msk       (0x3FUL << FDCAN_HPMS_BIDX_Pos)              /*!< 0x0000003F */

+#define FDCAN_HPMS_BIDX           FDCAN_HPMS_BIDX_Msk                          /*!<Buffer Index                              */

+#define FDCAN_HPMS_MSI_Pos        (6U)

+#define FDCAN_HPMS_MSI_Msk        (0x3UL << FDCAN_HPMS_MSI_Pos)                /*!< 0x000000C0 */

+#define FDCAN_HPMS_MSI            FDCAN_HPMS_MSI_Msk                           /*!<Message Storage Indicator                 */

+#define FDCAN_HPMS_FIDX_Pos       (8U)

+#define FDCAN_HPMS_FIDX_Msk       (0x7FUL << FDCAN_HPMS_FIDX_Pos)              /*!< 0x00007F00 */

+#define FDCAN_HPMS_FIDX           FDCAN_HPMS_FIDX_Msk                          /*!<Filter Index                              */

+#define FDCAN_HPMS_FLST_Pos       (15U)

+#define FDCAN_HPMS_FLST_Msk       (0x1UL << FDCAN_HPMS_FLST_Pos)               /*!< 0x00008000 */

+#define FDCAN_HPMS_FLST           FDCAN_HPMS_FLST_Msk                          /*!<Filter List                               */

+

+/*****************  Bit definition for FDCAN_NDAT1 register  ********************/

+#define FDCAN_NDAT1_ND0_Pos       (0U)

+#define FDCAN_NDAT1_ND0_Msk       (0x1UL << FDCAN_NDAT1_ND0_Pos)               /*!< 0x00000001 */

+#define FDCAN_NDAT1_ND0           FDCAN_NDAT1_ND0_Msk                          /*!<New Data flag of Rx Buffer 0              */

+#define FDCAN_NDAT1_ND1_Pos       (1U)

+#define FDCAN_NDAT1_ND1_Msk       (0x1UL << FDCAN_NDAT1_ND1_Pos)               /*!< 0x00000002 */

+#define FDCAN_NDAT1_ND1           FDCAN_NDAT1_ND1_Msk                          /*!<New Data flag of Rx Buffer 1              */

+#define FDCAN_NDAT1_ND2_Pos       (2U)

+#define FDCAN_NDAT1_ND2_Msk       (0x1UL << FDCAN_NDAT1_ND2_Pos)               /*!< 0x00000004 */

+#define FDCAN_NDAT1_ND2           FDCAN_NDAT1_ND2_Msk                          /*!<New Data flag of Rx Buffer 2              */

+#define FDCAN_NDAT1_ND3_Pos       (3U)

+#define FDCAN_NDAT1_ND3_Msk       (0x1UL << FDCAN_NDAT1_ND3_Pos)               /*!< 0x00000008 */

+#define FDCAN_NDAT1_ND3           FDCAN_NDAT1_ND3_Msk                          /*!<New Data flag of Rx Buffer 3              */

+#define FDCAN_NDAT1_ND4_Pos       (4U)

+#define FDCAN_NDAT1_ND4_Msk       (0x1UL << FDCAN_NDAT1_ND4_Pos)               /*!< 0x00000010 */

+#define FDCAN_NDAT1_ND4           FDCAN_NDAT1_ND4_Msk                          /*!<New Data flag of Rx Buffer 4              */

+#define FDCAN_NDAT1_ND5_Pos       (5U)

+#define FDCAN_NDAT1_ND5_Msk       (0x1UL << FDCAN_NDAT1_ND5_Pos)               /*!< 0x00000020 */

+#define FDCAN_NDAT1_ND5           FDCAN_NDAT1_ND5_Msk                          /*!<New Data flag of Rx Buffer 5              */

+#define FDCAN_NDAT1_ND6_Pos       (6U)

+#define FDCAN_NDAT1_ND6_Msk       (0x1UL << FDCAN_NDAT1_ND6_Pos)               /*!< 0x00000040 */

+#define FDCAN_NDAT1_ND6           FDCAN_NDAT1_ND6_Msk                          /*!<New Data flag of Rx Buffer 6              */

+#define FDCAN_NDAT1_ND7_Pos       (7U)

+#define FDCAN_NDAT1_ND7_Msk       (0x1UL << FDCAN_NDAT1_ND7_Pos)               /*!< 0x00000080 */

+#define FDCAN_NDAT1_ND7           FDCAN_NDAT1_ND7_Msk                          /*!<New Data flag of Rx Buffer 7              */

+#define FDCAN_NDAT1_ND8_Pos       (8U)

+#define FDCAN_NDAT1_ND8_Msk       (0x1UL << FDCAN_NDAT1_ND8_Pos)               /*!< 0x00000100 */

+#define FDCAN_NDAT1_ND8           FDCAN_NDAT1_ND8_Msk                          /*!<New Data flag of Rx Buffer 8              */

+#define FDCAN_NDAT1_ND9_Pos       (9U)

+#define FDCAN_NDAT1_ND9_Msk       (0x1UL << FDCAN_NDAT1_ND9_Pos)               /*!< 0x00000200 */

+#define FDCAN_NDAT1_ND9           FDCAN_NDAT1_ND9_Msk                          /*!<New Data flag of Rx Buffer 9              */

+#define FDCAN_NDAT1_ND10_Pos      (10U)

+#define FDCAN_NDAT1_ND10_Msk      (0x1UL << FDCAN_NDAT1_ND10_Pos)              /*!< 0x00000400 */

+#define FDCAN_NDAT1_ND10          FDCAN_NDAT1_ND10_Msk                         /*!<New Data flag of Rx Buffer 10             */

+#define FDCAN_NDAT1_ND11_Pos      (11U)

+#define FDCAN_NDAT1_ND11_Msk      (0x1UL << FDCAN_NDAT1_ND11_Pos)              /*!< 0x00000800 */

+#define FDCAN_NDAT1_ND11          FDCAN_NDAT1_ND11_Msk                         /*!<New Data flag of Rx Buffer 11             */

+#define FDCAN_NDAT1_ND12_Pos      (12U)

+#define FDCAN_NDAT1_ND12_Msk      (0x1UL << FDCAN_NDAT1_ND12_Pos)              /*!< 0x00001000 */

+#define FDCAN_NDAT1_ND12          FDCAN_NDAT1_ND12_Msk                         /*!<New Data flag of Rx Buffer 12             */

+#define FDCAN_NDAT1_ND13_Pos      (13U)

+#define FDCAN_NDAT1_ND13_Msk      (0x1UL << FDCAN_NDAT1_ND13_Pos)              /*!< 0x00002000 */

+#define FDCAN_NDAT1_ND13          FDCAN_NDAT1_ND13_Msk                         /*!<New Data flag of Rx Buffer 13             */

+#define FDCAN_NDAT1_ND14_Pos      (14U)

+#define FDCAN_NDAT1_ND14_Msk      (0x1UL << FDCAN_NDAT1_ND14_Pos)              /*!< 0x00004000 */

+#define FDCAN_NDAT1_ND14          FDCAN_NDAT1_ND14_Msk                         /*!<New Data flag of Rx Buffer 14             */

+#define FDCAN_NDAT1_ND15_Pos      (15U)

+#define FDCAN_NDAT1_ND15_Msk      (0x1UL << FDCAN_NDAT1_ND15_Pos)              /*!< 0x00008000 */

+#define FDCAN_NDAT1_ND15          FDCAN_NDAT1_ND15_Msk                         /*!<New Data flag of Rx Buffer 15             */

+#define FDCAN_NDAT1_ND16_Pos      (16U)

+#define FDCAN_NDAT1_ND16_Msk      (0x1UL << FDCAN_NDAT1_ND16_Pos)              /*!< 0x00010000 */

+#define FDCAN_NDAT1_ND16          FDCAN_NDAT1_ND16_Msk                         /*!<New Data flag of Rx Buffer 16             */

+#define FDCAN_NDAT1_ND17_Pos      (17U)

+#define FDCAN_NDAT1_ND17_Msk      (0x1UL << FDCAN_NDAT1_ND17_Pos)              /*!< 0x00020000 */

+#define FDCAN_NDAT1_ND17          FDCAN_NDAT1_ND17_Msk                         /*!<New Data flag of Rx Buffer 17             */

+#define FDCAN_NDAT1_ND18_Pos      (18U)

+#define FDCAN_NDAT1_ND18_Msk      (0x1UL << FDCAN_NDAT1_ND18_Pos)              /*!< 0x00040000 */

+#define FDCAN_NDAT1_ND18          FDCAN_NDAT1_ND18_Msk                         /*!<New Data flag of Rx Buffer 18             */

+#define FDCAN_NDAT1_ND19_Pos      (19U)

+#define FDCAN_NDAT1_ND19_Msk      (0x1UL << FDCAN_NDAT1_ND19_Pos)              /*!< 0x00080000 */

+#define FDCAN_NDAT1_ND19          FDCAN_NDAT1_ND19_Msk                         /*!<New Data flag of Rx Buffer 19             */

+#define FDCAN_NDAT1_ND20_Pos      (20U)

+#define FDCAN_NDAT1_ND20_Msk      (0x1UL << FDCAN_NDAT1_ND20_Pos)              /*!< 0x00100000 */

+#define FDCAN_NDAT1_ND20          FDCAN_NDAT1_ND20_Msk                         /*!<New Data flag of Rx Buffer 20             */

+#define FDCAN_NDAT1_ND21_Pos      (21U)

+#define FDCAN_NDAT1_ND21_Msk      (0x1UL << FDCAN_NDAT1_ND21_Pos)              /*!< 0x00200000 */

+#define FDCAN_NDAT1_ND21          FDCAN_NDAT1_ND21_Msk                         /*!<New Data flag of Rx Buffer 21             */

+#define FDCAN_NDAT1_ND22_Pos      (22U)

+#define FDCAN_NDAT1_ND22_Msk      (0x1UL << FDCAN_NDAT1_ND22_Pos)              /*!< 0x00400000 */

+#define FDCAN_NDAT1_ND22          FDCAN_NDAT1_ND22_Msk                         /*!<New Data flag of Rx Buffer 22             */

+#define FDCAN_NDAT1_ND23_Pos      (23U)

+#define FDCAN_NDAT1_ND23_Msk      (0x1UL << FDCAN_NDAT1_ND23_Pos)              /*!< 0x00800000 */

+#define FDCAN_NDAT1_ND23          FDCAN_NDAT1_ND23_Msk                         /*!<New Data flag of Rx Buffer 23             */

+#define FDCAN_NDAT1_ND24_Pos      (24U)

+#define FDCAN_NDAT1_ND24_Msk      (0x1UL << FDCAN_NDAT1_ND24_Pos)              /*!< 0x01000000 */

+#define FDCAN_NDAT1_ND24          FDCAN_NDAT1_ND24_Msk                         /*!<New Data flag of Rx Buffer 24             */

+#define FDCAN_NDAT1_ND25_Pos      (25U)

+#define FDCAN_NDAT1_ND25_Msk      (0x1UL << FDCAN_NDAT1_ND25_Pos)              /*!< 0x02000000 */

+#define FDCAN_NDAT1_ND25          FDCAN_NDAT1_ND25_Msk                         /*!<New Data flag of Rx Buffer 25             */

+#define FDCAN_NDAT1_ND26_Pos      (26U)

+#define FDCAN_NDAT1_ND26_Msk      (0x1UL << FDCAN_NDAT1_ND26_Pos)              /*!< 0x04000000 */

+#define FDCAN_NDAT1_ND26          FDCAN_NDAT1_ND26_Msk                         /*!<New Data flag of Rx Buffer 26             */

+#define FDCAN_NDAT1_ND27_Pos      (27U)

+#define FDCAN_NDAT1_ND27_Msk      (0x1UL << FDCAN_NDAT1_ND27_Pos)              /*!< 0x08000000 */

+#define FDCAN_NDAT1_ND27          FDCAN_NDAT1_ND27_Msk                         /*!<New Data flag of Rx Buffer 27             */

+#define FDCAN_NDAT1_ND28_Pos      (28U)

+#define FDCAN_NDAT1_ND28_Msk      (0x1UL << FDCAN_NDAT1_ND28_Pos)              /*!< 0x10000000 */

+#define FDCAN_NDAT1_ND28          FDCAN_NDAT1_ND28_Msk                         /*!<New Data flag of Rx Buffer 28             */

+#define FDCAN_NDAT1_ND29_Pos      (29U)

+#define FDCAN_NDAT1_ND29_Msk      (0x1UL << FDCAN_NDAT1_ND29_Pos)              /*!< 0x20000000 */

+#define FDCAN_NDAT1_ND29          FDCAN_NDAT1_ND29_Msk                         /*!<New Data flag of Rx Buffer 29             */

+#define FDCAN_NDAT1_ND30_Pos      (30U)

+#define FDCAN_NDAT1_ND30_Msk      (0x1UL << FDCAN_NDAT1_ND30_Pos)              /*!< 0x40000000 */

+#define FDCAN_NDAT1_ND30          FDCAN_NDAT1_ND30_Msk                         /*!<New Data flag of Rx Buffer 30             */

+#define FDCAN_NDAT1_ND31_Pos      (31U)

+#define FDCAN_NDAT1_ND31_Msk      (0x1UL << FDCAN_NDAT1_ND31_Pos)              /*!< 0x80000000 */

+#define FDCAN_NDAT1_ND31          FDCAN_NDAT1_ND31_Msk                         /*!<New Data flag of Rx Buffer 31             */

+

+/*****************  Bit definition for FDCAN_NDAT2 register  ********************/

+#define FDCAN_NDAT2_ND32_Pos      (0U)

+#define FDCAN_NDAT2_ND32_Msk      (0x1UL << FDCAN_NDAT2_ND32_Pos)              /*!< 0x00000001 */

+#define FDCAN_NDAT2_ND32          FDCAN_NDAT2_ND32_Msk                         /*!<New Data flag of Rx Buffer 32             */

+#define FDCAN_NDAT2_ND33_Pos      (1U)

+#define FDCAN_NDAT2_ND33_Msk      (0x1UL << FDCAN_NDAT2_ND33_Pos)              /*!< 0x00000002 */

+#define FDCAN_NDAT2_ND33          FDCAN_NDAT2_ND33_Msk                         /*!<New Data flag of Rx Buffer 33             */

+#define FDCAN_NDAT2_ND34_Pos      (2U)

+#define FDCAN_NDAT2_ND34_Msk      (0x1UL << FDCAN_NDAT2_ND34_Pos)              /*!< 0x00000004 */

+#define FDCAN_NDAT2_ND34          FDCAN_NDAT2_ND34_Msk                         /*!<New Data flag of Rx Buffer 34             */

+#define FDCAN_NDAT2_ND35_Pos      (3U)

+#define FDCAN_NDAT2_ND35_Msk      (0x1UL << FDCAN_NDAT2_ND35_Pos)              /*!< 0x00000008 */

+#define FDCAN_NDAT2_ND35          FDCAN_NDAT2_ND35_Msk                         /*!<New Data flag of Rx Buffer 35             */

+#define FDCAN_NDAT2_ND36_Pos      (4U)

+#define FDCAN_NDAT2_ND36_Msk      (0x1UL << FDCAN_NDAT2_ND36_Pos)              /*!< 0x00000010 */

+#define FDCAN_NDAT2_ND36          FDCAN_NDAT2_ND36_Msk                         /*!<New Data flag of Rx Buffer 36             */

+#define FDCAN_NDAT2_ND37_Pos      (5U)

+#define FDCAN_NDAT2_ND37_Msk      (0x1UL << FDCAN_NDAT2_ND37_Pos)              /*!< 0x00000020 */

+#define FDCAN_NDAT2_ND37          FDCAN_NDAT2_ND37_Msk                         /*!<New Data flag of Rx Buffer 37             */

+#define FDCAN_NDAT2_ND38_Pos      (6U)

+#define FDCAN_NDAT2_ND38_Msk      (0x1UL << FDCAN_NDAT2_ND38_Pos)              /*!< 0x00000040 */

+#define FDCAN_NDAT2_ND38          FDCAN_NDAT2_ND38_Msk                         /*!<New Data flag of Rx Buffer 38             */

+#define FDCAN_NDAT2_ND39_Pos      (7U)

+#define FDCAN_NDAT2_ND39_Msk      (0x1UL << FDCAN_NDAT2_ND39_Pos)              /*!< 0x00000080 */

+#define FDCAN_NDAT2_ND39          FDCAN_NDAT2_ND39_Msk                         /*!<New Data flag of Rx Buffer 39             */

+#define FDCAN_NDAT2_ND40_Pos      (8U)

+#define FDCAN_NDAT2_ND40_Msk      (0x1UL << FDCAN_NDAT2_ND40_Pos)              /*!< 0x00000100 */

+#define FDCAN_NDAT2_ND40          FDCAN_NDAT2_ND40_Msk                         /*!<New Data flag of Rx Buffer 40             */

+#define FDCAN_NDAT2_ND41_Pos      (9U)

+#define FDCAN_NDAT2_ND41_Msk      (0x1UL << FDCAN_NDAT2_ND41_Pos)              /*!< 0x00000200 */

+#define FDCAN_NDAT2_ND41          FDCAN_NDAT2_ND41_Msk                         /*!<New Data flag of Rx Buffer 41             */

+#define FDCAN_NDAT2_ND42_Pos      (10U)

+#define FDCAN_NDAT2_ND42_Msk      (0x1UL << FDCAN_NDAT2_ND42_Pos)              /*!< 0x00000400 */

+#define FDCAN_NDAT2_ND42          FDCAN_NDAT2_ND42_Msk                         /*!<New Data flag of Rx Buffer 42             */

+#define FDCAN_NDAT2_ND43_Pos      (11U)

+#define FDCAN_NDAT2_ND43_Msk      (0x1UL << FDCAN_NDAT2_ND43_Pos)              /*!< 0x00000800 */

+#define FDCAN_NDAT2_ND43          FDCAN_NDAT2_ND43_Msk                         /*!<New Data flag of Rx Buffer 43             */

+#define FDCAN_NDAT2_ND44_Pos      (12U)

+#define FDCAN_NDAT2_ND44_Msk      (0x1UL << FDCAN_NDAT2_ND44_Pos)              /*!< 0x00001000 */

+#define FDCAN_NDAT2_ND44          FDCAN_NDAT2_ND44_Msk                         /*!<New Data flag of Rx Buffer 44             */

+#define FDCAN_NDAT2_ND45_Pos      (13U)

+#define FDCAN_NDAT2_ND45_Msk      (0x1UL << FDCAN_NDAT2_ND45_Pos)              /*!< 0x00002000 */

+#define FDCAN_NDAT2_ND45          FDCAN_NDAT2_ND45_Msk                         /*!<New Data flag of Rx Buffer 45             */

+#define FDCAN_NDAT2_ND46_Pos      (14U)

+#define FDCAN_NDAT2_ND46_Msk      (0x1UL << FDCAN_NDAT2_ND46_Pos)              /*!< 0x00004000 */

+#define FDCAN_NDAT2_ND46          FDCAN_NDAT2_ND46_Msk                         /*!<New Data flag of Rx Buffer 46             */

+#define FDCAN_NDAT2_ND47_Pos      (15U)

+#define FDCAN_NDAT2_ND47_Msk      (0x1UL << FDCAN_NDAT2_ND47_Pos)              /*!< 0x00008000 */

+#define FDCAN_NDAT2_ND47          FDCAN_NDAT2_ND47_Msk                         /*!<New Data flag of Rx Buffer 47             */

+#define FDCAN_NDAT2_ND48_Pos      (16U)

+#define FDCAN_NDAT2_ND48_Msk      (0x1UL << FDCAN_NDAT2_ND48_Pos)              /*!< 0x00010000 */

+#define FDCAN_NDAT2_ND48          FDCAN_NDAT2_ND48_Msk                         /*!<New Data flag of Rx Buffer 48             */

+#define FDCAN_NDAT2_ND49_Pos      (17U)

+#define FDCAN_NDAT2_ND49_Msk      (0x1UL << FDCAN_NDAT2_ND49_Pos)              /*!< 0x00020000 */

+#define FDCAN_NDAT2_ND49          FDCAN_NDAT2_ND49_Msk                         /*!<New Data flag of Rx Buffer 49             */

+#define FDCAN_NDAT2_ND50_Pos      (18U)

+#define FDCAN_NDAT2_ND50_Msk      (0x1UL << FDCAN_NDAT2_ND50_Pos)              /*!< 0x00040000 */

+#define FDCAN_NDAT2_ND50          FDCAN_NDAT2_ND50_Msk                         /*!<New Data flag of Rx Buffer 50             */

+#define FDCAN_NDAT2_ND51_Pos      (19U)

+#define FDCAN_NDAT2_ND51_Msk      (0x1UL << FDCAN_NDAT2_ND51_Pos)              /*!< 0x00080000 */

+#define FDCAN_NDAT2_ND51          FDCAN_NDAT2_ND51_Msk                         /*!<New Data flag of Rx Buffer 51             */

+#define FDCAN_NDAT2_ND52_Pos      (20U)

+#define FDCAN_NDAT2_ND52_Msk      (0x1UL << FDCAN_NDAT2_ND52_Pos)              /*!< 0x00100000 */

+#define FDCAN_NDAT2_ND52          FDCAN_NDAT2_ND52_Msk                         /*!<New Data flag of Rx Buffer 52             */

+#define FDCAN_NDAT2_ND53_Pos      (21U)

+#define FDCAN_NDAT2_ND53_Msk      (0x1UL << FDCAN_NDAT2_ND53_Pos)              /*!< 0x00200000 */

+#define FDCAN_NDAT2_ND53          FDCAN_NDAT2_ND53_Msk                         /*!<New Data flag of Rx Buffer 53             */

+#define FDCAN_NDAT2_ND54_Pos      (22U)

+#define FDCAN_NDAT2_ND54_Msk      (0x1UL << FDCAN_NDAT2_ND54_Pos)              /*!< 0x00400000 */

+#define FDCAN_NDAT2_ND54          FDCAN_NDAT2_ND54_Msk                         /*!<New Data flag of Rx Buffer 54             */

+#define FDCAN_NDAT2_ND55_Pos      (23U)

+#define FDCAN_NDAT2_ND55_Msk      (0x1UL << FDCAN_NDAT2_ND55_Pos)              /*!< 0x00800000 */

+#define FDCAN_NDAT2_ND55          FDCAN_NDAT2_ND55_Msk                         /*!<New Data flag of Rx Buffer 55             */

+#define FDCAN_NDAT2_ND56_Pos      (24U)

+#define FDCAN_NDAT2_ND56_Msk      (0x1UL << FDCAN_NDAT2_ND56_Pos)              /*!< 0x01000000 */

+#define FDCAN_NDAT2_ND56          FDCAN_NDAT2_ND56_Msk                         /*!<New Data flag of Rx Buffer 56             */

+#define FDCAN_NDAT2_ND57_Pos      (25U)

+#define FDCAN_NDAT2_ND57_Msk      (0x1UL << FDCAN_NDAT2_ND57_Pos)              /*!< 0x02000000 */

+#define FDCAN_NDAT2_ND57          FDCAN_NDAT2_ND57_Msk                         /*!<New Data flag of Rx Buffer 57             */

+#define FDCAN_NDAT2_ND58_Pos      (26U)

+#define FDCAN_NDAT2_ND58_Msk      (0x1UL << FDCAN_NDAT2_ND58_Pos)              /*!< 0x04000000 */

+#define FDCAN_NDAT2_ND58          FDCAN_NDAT2_ND58_Msk                         /*!<New Data flag of Rx Buffer 58             */

+#define FDCAN_NDAT2_ND59_Pos      (27U)

+#define FDCAN_NDAT2_ND59_Msk      (0x1UL << FDCAN_NDAT2_ND59_Pos)              /*!< 0x08000000 */

+#define FDCAN_NDAT2_ND59          FDCAN_NDAT2_ND59_Msk                         /*!<New Data flag of Rx Buffer 59             */

+#define FDCAN_NDAT2_ND60_Pos      (28U)

+#define FDCAN_NDAT2_ND60_Msk      (0x1UL << FDCAN_NDAT2_ND60_Pos)              /*!< 0x10000000 */

+#define FDCAN_NDAT2_ND60          FDCAN_NDAT2_ND60_Msk                         /*!<New Data flag of Rx Buffer 60             */

+#define FDCAN_NDAT2_ND61_Pos      (29U)

+#define FDCAN_NDAT2_ND61_Msk      (0x1UL << FDCAN_NDAT2_ND61_Pos)              /*!< 0x20000000 */

+#define FDCAN_NDAT2_ND61          FDCAN_NDAT2_ND61_Msk                         /*!<New Data flag of Rx Buffer 61             */

+#define FDCAN_NDAT2_ND62_Pos      (30U)

+#define FDCAN_NDAT2_ND62_Msk      (0x1UL << FDCAN_NDAT2_ND62_Pos)              /*!< 0x40000000 */

+#define FDCAN_NDAT2_ND62          FDCAN_NDAT2_ND62_Msk                         /*!<New Data flag of Rx Buffer 62             */

+#define FDCAN_NDAT2_ND63_Pos      (31U)

+#define FDCAN_NDAT2_ND63_Msk      (0x1UL << FDCAN_NDAT2_ND63_Pos)              /*!< 0x80000000 */

+#define FDCAN_NDAT2_ND63          FDCAN_NDAT2_ND63_Msk                         /*!<New Data flag of Rx Buffer 63             */

+

+/*****************  Bit definition for FDCAN_RXF0C register  ********************/

+#define FDCAN_RXF0C_F0SA_Pos      (2U)

+#define FDCAN_RXF0C_F0SA_Msk      (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_RXF0C_F0SA          FDCAN_RXF0C_F0SA_Msk                         /*!<Rx FIFO 0 Start Address                   */

+#define FDCAN_RXF0C_F0S_Pos       (16U)

+#define FDCAN_RXF0C_F0S_Msk       (0x7FUL << FDCAN_RXF0C_F0S_Pos)              /*!< 0x007F0000 */

+#define FDCAN_RXF0C_F0S           FDCAN_RXF0C_F0S_Msk                          /*!<Number of Rx FIFO 0 elements              */

+#define FDCAN_RXF0C_F0WM_Pos      (24U)

+#define FDCAN_RXF0C_F0WM_Msk      (0x7FUL << FDCAN_RXF0C_F0WM_Pos)             /*!< 0x7F000000 */

+#define FDCAN_RXF0C_F0WM          FDCAN_RXF0C_F0WM_Msk                         /*!<FIFO 0 Watermark                          */

+#define FDCAN_RXF0C_F0OM_Pos      (31U)

+#define FDCAN_RXF0C_F0OM_Msk      (0x1UL << FDCAN_RXF0C_F0OM_Pos)              /*!< 0x80000000 */

+#define FDCAN_RXF0C_F0OM          FDCAN_RXF0C_F0OM_Msk                         /*!<FIFO 0 Operation Mode                     */

+

+/*****************  Bit definition for FDCAN_RXF0S register  ********************/

+#define FDCAN_RXF0S_F0FL_Pos      (0U)

+#define FDCAN_RXF0S_F0FL_Msk      (0x7FUL << FDCAN_RXF0S_F0FL_Pos)             /*!< 0x0000007F */

+#define FDCAN_RXF0S_F0FL          FDCAN_RXF0S_F0FL_Msk                         /*!<Rx FIFO 0 Fill Level                      */

+#define FDCAN_RXF0S_F0GI_Pos      (8U)

+#define FDCAN_RXF0S_F0GI_Msk      (0x3FUL << FDCAN_RXF0S_F0GI_Pos)             /*!< 0x00003F00 */

+#define FDCAN_RXF0S_F0GI          FDCAN_RXF0S_F0GI_Msk                         /*!<Rx FIFO 0 Get Index                       */

+#define FDCAN_RXF0S_F0PI_Pos      (16U)

+#define FDCAN_RXF0S_F0PI_Msk      (0x3FUL << FDCAN_RXF0S_F0PI_Pos)             /*!< 0x003F0000 */

+#define FDCAN_RXF0S_F0PI          FDCAN_RXF0S_F0PI_Msk                         /*!<Rx FIFO 0 Put Index                       */

+#define FDCAN_RXF0S_F0F_Pos       (24U)

+#define FDCAN_RXF0S_F0F_Msk       (0x1UL << FDCAN_RXF0S_F0F_Pos)               /*!< 0x01000000 */

+#define FDCAN_RXF0S_F0F           FDCAN_RXF0S_F0F_Msk                          /*!<Rx FIFO 0 Full                            */

+#define FDCAN_RXF0S_RF0L_Pos      (25U)

+#define FDCAN_RXF0S_RF0L_Msk      (0x1UL << FDCAN_RXF0S_RF0L_Pos)              /*!< 0x02000000 */

+#define FDCAN_RXF0S_RF0L          FDCAN_RXF0S_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                    */

+

+/*****************  Bit definition for FDCAN_RXF0A register  ********************/

+#define FDCAN_RXF0A_F0AI_Pos      (0U)

+#define FDCAN_RXF0A_F0AI_Msk      (0x3FUL << FDCAN_RXF0A_F0AI_Pos)             /*!< 0x0000003F */

+#define FDCAN_RXF0A_F0AI          FDCAN_RXF0A_F0AI_Msk                         /*!<Rx FIFO 0 Acknowledge Index               */

+

+/*****************  Bit definition for FDCAN_RXBC register  ********************/

+#define FDCAN_RXBC_RBSA_Pos       (2U)

+#define FDCAN_RXBC_RBSA_Msk       (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)            /*!< 0x0000FFFC */

+#define FDCAN_RXBC_RBSA           FDCAN_RXBC_RBSA_Msk                          /*!<Rx Buffer Start Address                   */

+

+/*****************  Bit definition for FDCAN_RXF1C register  ********************/

+#define FDCAN_RXF1C_F1SA_Pos      (2U)

+#define FDCAN_RXF1C_F1SA_Msk      (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_RXF1C_F1SA          FDCAN_RXF1C_F1SA_Msk                         /*!<Rx FIFO 1 Start Address                   */

+#define FDCAN_RXF1C_F1S_Pos       (16U)

+#define FDCAN_RXF1C_F1S_Msk       (0x7FUL << FDCAN_RXF1C_F1S_Pos)              /*!< 0x007F0000 */

+#define FDCAN_RXF1C_F1S           FDCAN_RXF1C_F1S_Msk                          /*!<Number of Rx FIFO 1 elements              */

+#define FDCAN_RXF1C_F1WM_Pos      (24U)

+#define FDCAN_RXF1C_F1WM_Msk      (0x7FUL << FDCAN_RXF1C_F1WM_Pos)             /*!< 0x7F000000 */

+#define FDCAN_RXF1C_F1WM          FDCAN_RXF1C_F1WM_Msk                         /*!<Rx FIFO 1 Watermark                       */

+#define FDCAN_RXF1C_F1OM_Pos      (31U)

+#define FDCAN_RXF1C_F1OM_Msk      (0x1UL << FDCAN_RXF1C_F1OM_Pos)              /*!< 0x80000000 */

+#define FDCAN_RXF1C_F1OM          FDCAN_RXF1C_F1OM_Msk                         /*!<FIFO 1 Operation Mode                     */

+

+/*****************  Bit definition for FDCAN_RXF1S register  ********************/

+#define FDCAN_RXF1S_F1FL_Pos      (0U)

+#define FDCAN_RXF1S_F1FL_Msk      (0x7FUL << FDCAN_RXF1S_F1FL_Pos)             /*!< 0x0000007F */

+#define FDCAN_RXF1S_F1FL          FDCAN_RXF1S_F1FL_Msk                         /*!<Rx FIFO 1 Fill Level                      */

+#define FDCAN_RXF1S_F1GI_Pos      (8U)

+#define FDCAN_RXF1S_F1GI_Msk      (0x3FUL << FDCAN_RXF1S_F1GI_Pos)             /*!< 0x00003F00 */

+#define FDCAN_RXF1S_F1GI          FDCAN_RXF1S_F1GI_Msk                         /*!<Rx FIFO 1 Get Index                       */

+#define FDCAN_RXF1S_F1PI_Pos      (16U)

+#define FDCAN_RXF1S_F1PI_Msk      (0x3FUL << FDCAN_RXF1S_F1PI_Pos)             /*!< 0x003F0000 */

+#define FDCAN_RXF1S_F1PI          FDCAN_RXF1S_F1PI_Msk                         /*!<Rx FIFO 1 Put Index                       */

+#define FDCAN_RXF1S_F1F_Pos       (24U)

+#define FDCAN_RXF1S_F1F_Msk       (0x1UL << FDCAN_RXF1S_F1F_Pos)               /*!< 0x01000000 */

+#define FDCAN_RXF1S_F1F           FDCAN_RXF1S_F1F_Msk                          /*!<Rx FIFO 1 Full                            */

+#define FDCAN_RXF1S_RF1L_Pos      (25U)

+#define FDCAN_RXF1S_RF1L_Msk      (0x1UL << FDCAN_RXF1S_RF1L_Pos)              /*!< 0x02000000 */

+#define FDCAN_RXF1S_RF1L          FDCAN_RXF1S_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                    */

+

+/*****************  Bit definition for FDCAN_RXF1A register  ********************/

+#define FDCAN_RXF1A_F1AI_Pos      (0U)

+#define FDCAN_RXF1A_F1AI_Msk      (0x3FUL << FDCAN_RXF1A_F1AI_Pos)             /*!< 0x0000003F */

+#define FDCAN_RXF1A_F1AI          FDCAN_RXF1A_F1AI_Msk                         /*!<Rx FIFO 1 Acknowledge Index               */

+

+/*****************  Bit definition for FDCAN_RXESC register  ********************/

+#define FDCAN_RXESC_F0DS_Pos      (0U)

+#define FDCAN_RXESC_F0DS_Msk      (0x7UL << FDCAN_RXESC_F0DS_Pos)              /*!< 0x00000007 */

+#define FDCAN_RXESC_F0DS          FDCAN_RXESC_F0DS_Msk                         /*!<Rx FIFO 1 Data Field Size                 */

+#define FDCAN_RXESC_F1DS_Pos      (4U)

+#define FDCAN_RXESC_F1DS_Msk      (0x7UL << FDCAN_RXESC_F1DS_Pos)              /*!< 0x00000070 */

+#define FDCAN_RXESC_F1DS          FDCAN_RXESC_F1DS_Msk                         /*!<Rx FIFO 0 Data Field Size                 */

+#define FDCAN_RXESC_RBDS_Pos      (8U)

+#define FDCAN_RXESC_RBDS_Msk      (0x7UL << FDCAN_RXESC_RBDS_Pos)              /*!< 0x00000700 */

+#define FDCAN_RXESC_RBDS          FDCAN_RXESC_RBDS_Msk                         /*!<Rx Buffer Data Field Size                 */

+

+/*****************  Bit definition for FDCAN_TXBC register  *********************/

+#define FDCAN_TXBC_TBSA_Pos       (2U)

+#define FDCAN_TXBC_TBSA_Msk       (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)            /*!< 0x0000FFFC */

+#define FDCAN_TXBC_TBSA           FDCAN_TXBC_TBSA_Msk                          /*!<Tx Buffers Start Address                  */

+#define FDCAN_TXBC_NDTB_Pos       (16U)

+#define FDCAN_TXBC_NDTB_Msk       (0x3FUL << FDCAN_TXBC_NDTB_Pos)              /*!< 0x003F0000 */

+#define FDCAN_TXBC_NDTB           FDCAN_TXBC_NDTB_Msk                          /*!<Number of Dedicated Transmit Buffers      */

+#define FDCAN_TXBC_TFQS_Pos       (24U)

+#define FDCAN_TXBC_TFQS_Msk       (0x3FUL << FDCAN_TXBC_TFQS_Pos)              /*!< 0x3F000000 */

+#define FDCAN_TXBC_TFQS           FDCAN_TXBC_TFQS_Msk                          /*!<Transmit FIFO/Queue Size                  */

+#define FDCAN_TXBC_TFQM_Pos       (30U)

+#define FDCAN_TXBC_TFQM_Msk       (0x1UL << FDCAN_TXBC_TFQM_Pos)               /*!< 0x40000000 */

+#define FDCAN_TXBC_TFQM           FDCAN_TXBC_TFQM_Msk                          /*!<Tx FIFO/Queue Mode                        */

+

+/*****************  Bit definition for FDCAN_TXFQS register  *********************/

+#define FDCAN_TXFQS_TFFL_Pos      (0U)

+#define FDCAN_TXFQS_TFFL_Msk      (0x3FUL << FDCAN_TXFQS_TFFL_Pos)             /*!< 0x0000003F */

+#define FDCAN_TXFQS_TFFL          FDCAN_TXFQS_TFFL_Msk                         /*!<Tx FIFO Free Level                        */

+#define FDCAN_TXFQS_TFGI_Pos      (8U)

+#define FDCAN_TXFQS_TFGI_Msk      (0x1FUL << FDCAN_TXFQS_TFGI_Pos)             /*!< 0x00001F00 */

+#define FDCAN_TXFQS_TFGI          FDCAN_TXFQS_TFGI_Msk                         /*!<Tx FIFO Get Index                         */

+#define FDCAN_TXFQS_TFQPI_Pos     (16U)

+#define FDCAN_TXFQS_TFQPI_Msk     (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)            /*!< 0x001F0000 */

+#define FDCAN_TXFQS_TFQPI         FDCAN_TXFQS_TFQPI_Msk                        /*!<Tx FIFO/Queue Put Index                   */

+#define FDCAN_TXFQS_TFQF_Pos      (21U)

+#define FDCAN_TXFQS_TFQF_Msk      (0x1UL << FDCAN_TXFQS_TFQF_Pos)              /*!< 0x00200000 */

+#define FDCAN_TXFQS_TFQF          FDCAN_TXFQS_TFQF_Msk                         /*!<Tx FIFO/Queue Full                        */

+

+/*****************  Bit definition for FDCAN_TXESC register  *********************/

+#define FDCAN_TXESC_TBDS_Pos      (0U)

+#define FDCAN_TXESC_TBDS_Msk      (0x7UL << FDCAN_TXESC_TBDS_Pos)              /*!< 0x00000007 */

+#define FDCAN_TXESC_TBDS          FDCAN_TXESC_TBDS_Msk                         /*!<Tx Buffer Data Field Size                 */

+

+/*****************  Bit definition for FDCAN_TXBRP register  *********************/

+#define FDCAN_TXBRP_TRP_Pos       (0U)

+#define FDCAN_TXBRP_TRP_Msk       (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)        /*!< 0xFFFFFFFF */

+#define FDCAN_TXBRP_TRP           FDCAN_TXBRP_TRP_Msk                          /*!<Transmission Request Pending              */

+

+/*****************  Bit definition for FDCAN_TXBAR register  *********************/

+#define FDCAN_TXBAR_AR_Pos        (0U)

+#define FDCAN_TXBAR_AR_Msk        (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBAR_AR            FDCAN_TXBAR_AR_Msk                           /*!<Add Request                               */

+

+/*****************  Bit definition for FDCAN_TXBCR register  *********************/

+#define FDCAN_TXBCR_CR_Pos        (0U)

+#define FDCAN_TXBCR_CR_Msk        (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCR_CR            FDCAN_TXBCR_CR_Msk                           /*!<Cancellation Request                      */

+

+/*****************  Bit definition for FDCAN_TXBTO register  *********************/

+#define FDCAN_TXBTO_TO_Pos        (0U)

+#define FDCAN_TXBTO_TO_Msk        (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBTO_TO            FDCAN_TXBTO_TO_Msk                           /*!<Transmission Occurred                     */

+

+/*****************  Bit definition for FDCAN_TXBCF register  *********************/

+#define FDCAN_TXBCF_CF_Pos        (0U)

+#define FDCAN_TXBCF_CF_Msk        (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCF_CF            FDCAN_TXBCF_CF_Msk                           /*!<Cancellation Finished                     */

+

+/*****************  Bit definition for FDCAN_TXBTIE register  ********************/

+#define FDCAN_TXBTIE_TIE_Pos      (0U)

+#define FDCAN_TXBTIE_TIE_Msk      (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)       /*!< 0xFFFFFFFF */

+#define FDCAN_TXBTIE_TIE          FDCAN_TXBTIE_TIE_Msk                         /*!<Transmission Interrupt Enable             */

+

+/*****************  Bit definition for FDCAN_ TXBCIE register  *******************/

+#define FDCAN_TXBCIE_CFIE_Pos     (0U)

+#define FDCAN_TXBCIE_CFIE_Msk     (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)      /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCIE_CFIE         FDCAN_TXBCIE_CFIE_Msk                        /*!<Cancellation Finished Interrupt Enable    */

+

+/*****************  Bit definition for FDCAN_TXEFC register  *********************/

+#define FDCAN_TXEFC_EFSA_Pos      (2U)

+#define FDCAN_TXEFC_EFSA_Msk      (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_TXEFC_EFSA          FDCAN_TXEFC_EFSA_Msk                         /*!<Event FIFO Start Address                  */

+#define FDCAN_TXEFC_EFS_Pos       (16U)

+#define FDCAN_TXEFC_EFS_Msk       (0x3FUL << FDCAN_TXEFC_EFS_Pos)              /*!< 0x003F0000 */

+#define FDCAN_TXEFC_EFS           FDCAN_TXEFC_EFS_Msk                          /*!<Event FIFO Size                           */

+#define FDCAN_TXEFC_EFWM_Pos      (24U)

+#define FDCAN_TXEFC_EFWM_Msk      (0x3FUL << FDCAN_TXEFC_EFWM_Pos)             /*!< 0x3F000000 */

+#define FDCAN_TXEFC_EFWM          FDCAN_TXEFC_EFWM_Msk                         /*!<Event FIFO Watermark                      */

+

+/*****************  Bit definition for FDCAN_TXEFS register  *********************/

+#define FDCAN_TXEFS_EFFL_Pos      (0U)

+#define FDCAN_TXEFS_EFFL_Msk      (0x3FUL << FDCAN_TXEFS_EFFL_Pos)             /*!< 0x0000003F */

+#define FDCAN_TXEFS_EFFL          FDCAN_TXEFS_EFFL_Msk                         /*!<Event FIFO Fill Level                     */

+#define FDCAN_TXEFS_EFGI_Pos      (8U)

+#define FDCAN_TXEFS_EFGI_Msk      (0x1FUL << FDCAN_TXEFS_EFGI_Pos)             /*!< 0x00001F00 */

+#define FDCAN_TXEFS_EFGI          FDCAN_TXEFS_EFGI_Msk                         /*!<Event FIFO Get Index                      */

+#define FDCAN_TXEFS_EFPI_Pos      (16U)

+#define FDCAN_TXEFS_EFPI_Msk      (0x1FUL << FDCAN_TXEFS_EFPI_Pos)             /*!< 0x001F0000 */

+#define FDCAN_TXEFS_EFPI          FDCAN_TXEFS_EFPI_Msk                         /*!<Event FIFO Put Index                      */

+#define FDCAN_TXEFS_EFF_Pos       (24U)

+#define FDCAN_TXEFS_EFF_Msk       (0x1UL << FDCAN_TXEFS_EFF_Pos)               /*!< 0x01000000 */

+#define FDCAN_TXEFS_EFF           FDCAN_TXEFS_EFF_Msk                          /*!<Event FIFO Full                           */

+#define FDCAN_TXEFS_TEFL_Pos      (25U)

+#define FDCAN_TXEFS_TEFL_Msk      (0x1UL << FDCAN_TXEFS_TEFL_Pos)              /*!< 0x02000000 */

+#define FDCAN_TXEFS_TEFL          FDCAN_TXEFS_TEFL_Msk                         /*!<Tx Event FIFO Element Lost                */

+

+/*****************  Bit definition for FDCAN_TXEFA register  *********************/

+#define FDCAN_TXEFA_EFAI_Pos      (0U)

+#define FDCAN_TXEFA_EFAI_Msk      (0x1FUL << FDCAN_TXEFA_EFAI_Pos)             /*!< 0x0000001F */

+#define FDCAN_TXEFA_EFAI          FDCAN_TXEFA_EFAI_Msk                         /*!<Event FIFO Acknowledge Index              */

+

+/*****************  Bit definition for FDCAN_TTTMC register  *********************/

+#define FDCAN_TTTMC_TMSA_Pos      (2U)

+#define FDCAN_TTTMC_TMSA_Msk      (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_TTTMC_TMSA          FDCAN_TTTMC_TMSA_Msk                         /*!<Trigger Memory Start Address              */

+#define FDCAN_TTTMC_TME_Pos       (16U)

+#define FDCAN_TTTMC_TME_Msk       (0x7FUL << FDCAN_TTTMC_TME_Pos)              /*!< 0x007F0000 */

+#define FDCAN_TTTMC_TME           FDCAN_TTTMC_TME_Msk                          /*!<Trigger Memory Elements                   */

+

+/*****************  Bit definition for FDCAN_TTRMC register  *********************/

+#define FDCAN_TTRMC_RID_Pos       (0U)

+#define FDCAN_TTRMC_RID_Msk       (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)        /*!< 0x1FFFFFFF */

+#define FDCAN_TTRMC_RID           FDCAN_TTRMC_RID_Msk                          /*!<Reference Identifier                      */

+#define FDCAN_TTRMC_XTD_Pos       (30U)

+#define FDCAN_TTRMC_XTD_Msk       (0x1UL << FDCAN_TTRMC_XTD_Pos)               /*!< 0x40000000 */

+#define FDCAN_TTRMC_XTD           FDCAN_TTRMC_XTD_Msk                          /*!< Extended Identifier                      */

+#define FDCAN_TTRMC_RMPS_Pos      (31U)

+#define FDCAN_TTRMC_RMPS_Msk      (0x1UL << FDCAN_TTRMC_RMPS_Pos)              /*!< 0x80000000 */

+#define FDCAN_TTRMC_RMPS          FDCAN_TTRMC_RMPS_Msk                         /*!<Reference Message Payload Select          */

+

+/*****************  Bit definition for FDCAN_TTOCF register  *********************/

+#define FDCAN_TTOCF_OM_Pos        (0U)

+#define FDCAN_TTOCF_OM_Msk        (0x3UL << FDCAN_TTOCF_OM_Pos)                /*!< 0x00000003 */

+#define FDCAN_TTOCF_OM            FDCAN_TTOCF_OM_Msk                           /*!<Operation Mode                            */

+#define FDCAN_TTOCF_GEN_Pos       (3U)

+#define FDCAN_TTOCF_GEN_Msk       (0x1UL << FDCAN_TTOCF_GEN_Pos)               /*!< 0x00000008 */

+#define FDCAN_TTOCF_GEN           FDCAN_TTOCF_GEN_Msk                          /*!<Gap Enable                                */

+#define FDCAN_TTOCF_TM_Pos        (4U)

+#define FDCAN_TTOCF_TM_Msk        (0x1UL << FDCAN_TTOCF_TM_Pos)                /*!< 0x00000010 */

+#define FDCAN_TTOCF_TM            FDCAN_TTOCF_TM_Msk                           /*!<Time Master                               */

+#define FDCAN_TTOCF_LDSDL_Pos     (5U)

+#define FDCAN_TTOCF_LDSDL_Msk     (0x7UL << FDCAN_TTOCF_LDSDL_Pos)             /*!< 0x000000E0 */

+#define FDCAN_TTOCF_LDSDL         FDCAN_TTOCF_LDSDL_Msk                        /*!<LD of Synchronization Deviation Limit     */

+#define FDCAN_TTOCF_IRTO_Pos      (8U)

+#define FDCAN_TTOCF_IRTO_Msk      (0x7FUL << FDCAN_TTOCF_IRTO_Pos)             /*!< 0x00007F00 */

+#define FDCAN_TTOCF_IRTO          FDCAN_TTOCF_IRTO_Msk                         /*!<Initial Reference Trigger Offset          */

+#define FDCAN_TTOCF_EECS_Pos      (15U)

+#define FDCAN_TTOCF_EECS_Msk      (0x1UL << FDCAN_TTOCF_EECS_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTOCF_EECS          FDCAN_TTOCF_EECS_Msk                         /*!<Enable External Clock Synchronization     */

+#define FDCAN_TTOCF_AWL_Pos       (16U)

+#define FDCAN_TTOCF_AWL_Msk       (0xFFUL << FDCAN_TTOCF_AWL_Pos)              /*!< 0x00FF0000 */

+#define FDCAN_TTOCF_AWL           FDCAN_TTOCF_AWL_Msk                          /*!<Application Watchdog Limit                */

+#define FDCAN_TTOCF_EGTF_Pos      (24U)

+#define FDCAN_TTOCF_EGTF_Msk      (0x1UL << FDCAN_TTOCF_EGTF_Pos)              /*!< 0x01000000 */

+#define FDCAN_TTOCF_EGTF          FDCAN_TTOCF_EGTF_Msk                         /*!<Enable Global Time Filtering              */

+#define FDCAN_TTOCF_ECC_Pos       (25U)

+#define FDCAN_TTOCF_ECC_Msk       (0x1UL << FDCAN_TTOCF_ECC_Pos)               /*!< 0x02000000 */

+#define FDCAN_TTOCF_ECC           FDCAN_TTOCF_ECC_Msk                          /*!<Enable Clock Calibration                  */

+#define FDCAN_TTOCF_EVTP_Pos      (26U)

+#define FDCAN_TTOCF_EVTP_Msk      (0x1UL << FDCAN_TTOCF_EVTP_Pos)              /*!< 0x04000000 */

+#define FDCAN_TTOCF_EVTP          FDCAN_TTOCF_EVTP_Msk                         /*!<Event Trigger Polarity                    */

+

+/*****************  Bit definition for FDCAN_TTMLM register  *********************/

+#define FDCAN_TTMLM_CCM_Pos       (0U)

+#define FDCAN_TTMLM_CCM_Msk       (0x3FUL << FDCAN_TTMLM_CCM_Pos)              /*!< 0x0000003F */

+#define FDCAN_TTMLM_CCM           FDCAN_TTMLM_CCM_Msk                          /*!<Cycle Count Max                           */

+#define FDCAN_TTMLM_CSS_Pos       (6U)

+#define FDCAN_TTMLM_CSS_Msk       (0x3UL << FDCAN_TTMLM_CSS_Pos)               /*!< 0x000000C0 */

+#define FDCAN_TTMLM_CSS           FDCAN_TTMLM_CSS_Msk                          /*!<Cycle Start Synchronization               */

+#define FDCAN_TTMLM_TXEW_Pos      (8U)

+#define FDCAN_TTMLM_TXEW_Msk      (0xFUL << FDCAN_TTMLM_TXEW_Pos)              /*!< 0x00000F00 */

+#define FDCAN_TTMLM_TXEW          FDCAN_TTMLM_TXEW_Msk                         /*!<Tx Enable Window                          */

+#define FDCAN_TTMLM_ENTT_Pos      (16U)

+#define FDCAN_TTMLM_ENTT_Msk      (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)            /*!< 0x0FFF0000 */

+#define FDCAN_TTMLM_ENTT          FDCAN_TTMLM_ENTT_Msk                         /*!<Expected Number of Tx Triggers            */

+

+/*****************  Bit definition for FDCAN_TURCF register  *********************/

+#define FDCAN_TURCF_NCL_Pos       (0U)

+#define FDCAN_TURCF_NCL_Msk       (0xFFFFUL << FDCAN_TURCF_NCL_Pos)            /*!< 0x0000FFFF */

+#define FDCAN_TURCF_NCL           FDCAN_TURCF_NCL_Msk                          /*!<Numerator Configuration Low               */

+#define FDCAN_TURCF_DC_Pos        (16U)

+#define FDCAN_TURCF_DC_Msk        (0x3FFFUL << FDCAN_TURCF_DC_Pos)             /*!< 0x3FFF0000 */

+#define FDCAN_TURCF_DC            FDCAN_TURCF_DC_Msk                           /*!<Denominator Configuration                 */

+#define FDCAN_TURCF_ELT_Pos       (31U)

+#define FDCAN_TURCF_ELT_Msk       (0x1UL << FDCAN_TURCF_ELT_Pos)               /*!< 0x80000000 */

+#define FDCAN_TURCF_ELT           FDCAN_TURCF_ELT_Msk                          /*!<Enable Local Time                         */

+

+/*****************  Bit definition for FDCAN_TTOCN register  ********************/

+#define FDCAN_TTOCN_SGT_Pos       (0U)

+#define FDCAN_TTOCN_SGT_Msk       (0x1UL << FDCAN_TTOCN_SGT_Pos)               /*!< 0x00000001 */

+#define FDCAN_TTOCN_SGT           FDCAN_TTOCN_SGT_Msk                          /*!<Set Global time                           */

+#define FDCAN_TTOCN_ECS_Pos       (1U)

+#define FDCAN_TTOCN_ECS_Msk       (0x1UL << FDCAN_TTOCN_ECS_Pos)               /*!< 0x00000002 */

+#define FDCAN_TTOCN_ECS           FDCAN_TTOCN_ECS_Msk                          /*!<External Clock Synchronization            */

+#define FDCAN_TTOCN_SWP_Pos       (2U)

+#define FDCAN_TTOCN_SWP_Msk       (0x1UL << FDCAN_TTOCN_SWP_Pos)               /*!< 0x00000004 */

+#define FDCAN_TTOCN_SWP           FDCAN_TTOCN_SWP_Msk                          /*!<Stop Watch Polarity                       */

+#define FDCAN_TTOCN_SWS_Pos       (3U)

+#define FDCAN_TTOCN_SWS_Msk       (0x3UL << FDCAN_TTOCN_SWS_Pos)               /*!< 0x00000018 */

+#define FDCAN_TTOCN_SWS           FDCAN_TTOCN_SWS_Msk                          /*!<Stop Watch Source                         */

+#define FDCAN_TTOCN_RTIE_Pos      (5U)

+#define FDCAN_TTOCN_RTIE_Msk      (0x1UL << FDCAN_TTOCN_RTIE_Pos)              /*!< 0x00000020 */

+#define FDCAN_TTOCN_RTIE          FDCAN_TTOCN_RTIE_Msk                         /*!<Register Time Mark Interrupt Pulse Enable */

+#define FDCAN_TTOCN_TMC_Pos       (6U)

+#define FDCAN_TTOCN_TMC_Msk       (0x3UL << FDCAN_TTOCN_TMC_Pos)               /*!< 0x000000C0 */

+#define FDCAN_TTOCN_TMC           FDCAN_TTOCN_TMC_Msk                          /*!<Register Time Mark Compare                */

+#define FDCAN_TTOCN_TTIE_Pos      (8U)

+#define FDCAN_TTOCN_TTIE_Msk      (0x1UL << FDCAN_TTOCN_TTIE_Pos)              /*!< 0x00000100 */

+#define FDCAN_TTOCN_TTIE          FDCAN_TTOCN_TTIE_Msk                         /*!<Trigger Time Mark Interrupt Pulse Enable  */

+#define FDCAN_TTOCN_GCS_Pos       (9U)

+#define FDCAN_TTOCN_GCS_Msk       (0x1UL << FDCAN_TTOCN_GCS_Pos)               /*!< 0x00000200 */

+#define FDCAN_TTOCN_GCS           FDCAN_TTOCN_GCS_Msk                          /*!<Gap Control Select                        */

+#define FDCAN_TTOCN_FGP_Pos       (10U)

+#define FDCAN_TTOCN_FGP_Msk       (0x1UL << FDCAN_TTOCN_FGP_Pos)               /*!< 0x00000400 */

+#define FDCAN_TTOCN_FGP           FDCAN_TTOCN_FGP_Msk                          /*!<Finish Gap                                */

+#define FDCAN_TTOCN_TMG_Pos       (11U)

+#define FDCAN_TTOCN_TMG_Msk       (0x1UL << FDCAN_TTOCN_TMG_Pos)               /*!< 0x00000800 */

+#define FDCAN_TTOCN_TMG           FDCAN_TTOCN_TMG_Msk                          /*!<Time Mark Gap                             */

+#define FDCAN_TTOCN_NIG_Pos       (12U)

+#define FDCAN_TTOCN_NIG_Msk       (0x1UL << FDCAN_TTOCN_NIG_Pos)               /*!< 0x00001000 */

+#define FDCAN_TTOCN_NIG           FDCAN_TTOCN_NIG_Msk                          /*!<Next is Gap                               */

+#define FDCAN_TTOCN_ESCN_Pos      (13U)

+#define FDCAN_TTOCN_ESCN_Msk      (0x1UL << FDCAN_TTOCN_ESCN_Pos)              /*!< 0x00002000 */

+#define FDCAN_TTOCN_ESCN          FDCAN_TTOCN_ESCN_Msk                         /*!<External Synchronization Control          */

+#define FDCAN_TTOCN_LCKC_Pos      (15U)

+#define FDCAN_TTOCN_LCKC_Msk      (0x1UL << FDCAN_TTOCN_LCKC_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTOCN_LCKC          FDCAN_TTOCN_LCKC_Msk                         /*!<TT Operation Control Register Locked      */

+

+/*****************  Bit definition for FDCAN_TTGTP register  ********************/

+#define FDCAN_TTGTP_TP_Pos        (0U)

+#define FDCAN_TTGTP_TP_Msk        (0xFFFFUL << FDCAN_TTGTP_TP_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTGTP_TP            FDCAN_TTGTP_TP_Msk                           /*!<Time Preset                               */

+#define FDCAN_TTGTP_CTP_Pos       (16U)

+#define FDCAN_TTGTP_CTP_Msk       (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)            /*!< 0xFFFF0000 */

+#define FDCAN_TTGTP_CTP           FDCAN_TTGTP_CTP_Msk                          /*!<Cycle Time Target Phase                   */

+

+/*****************  Bit definition for FDCAN_TTTMK register  ********************/

+#define FDCAN_TTTMK_TM_Pos        (0U)

+#define FDCAN_TTTMK_TM_Msk        (0xFFFFUL << FDCAN_TTTMK_TM_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTTMK_TM            FDCAN_TTTMK_TM_Msk                           /*!<Time Mark                                 */

+#define FDCAN_TTTMK_TICC_Pos      (16U)

+#define FDCAN_TTTMK_TICC_Msk      (0x7FUL << FDCAN_TTTMK_TICC_Pos)             /*!< 0x007F0000 */

+#define FDCAN_TTTMK_TICC          FDCAN_TTTMK_TICC_Msk                         /*!<Time Mark Cycle Code                      */

+#define FDCAN_TTTMK_LCKM_Pos      (31U)

+#define FDCAN_TTTMK_LCKM_Msk      (0x1UL << FDCAN_TTTMK_LCKM_Pos)              /*!< 0x80000000 */

+#define FDCAN_TTTMK_LCKM          FDCAN_TTTMK_LCKM_Msk                         /*!<TT Time Mark Register Locked              */

+

+/*****************  Bit definition for FDCAN_TTIR register  ********************/

+#define FDCAN_TTIR_SBC_Pos        (0U)

+#define FDCAN_TTIR_SBC_Msk        (0x1UL << FDCAN_TTIR_SBC_Pos)                /*!< 0x00000001 */

+#define FDCAN_TTIR_SBC            FDCAN_TTIR_SBC_Msk                           /*!<Start of Basic Cycle                      */

+#define FDCAN_TTIR_SMC_Pos        (1U)

+#define FDCAN_TTIR_SMC_Msk        (0x1UL << FDCAN_TTIR_SMC_Pos)                /*!< 0x00000002 */

+#define FDCAN_TTIR_SMC            FDCAN_TTIR_SMC_Msk                           /*!<Start of Matrix Cycle                     */

+#define FDCAN_TTIR_CSM_Pos        (2U)

+#define FDCAN_TTIR_CSM_Msk        (0x1UL << FDCAN_TTIR_CSM_Pos)                /*!< 0x00000004 */

+#define FDCAN_TTIR_CSM            FDCAN_TTIR_CSM_Msk                           /*!<Change of Synchronization Mode            */

+#define FDCAN_TTIR_SOG_Pos        (3U)

+#define FDCAN_TTIR_SOG_Msk        (0x1UL << FDCAN_TTIR_SOG_Pos)                /*!< 0x00000008 */

+#define FDCAN_TTIR_SOG            FDCAN_TTIR_SOG_Msk                           /*!<Start of Gap                              */

+#define FDCAN_TTIR_RTMI_Pos       (4U)

+#define FDCAN_TTIR_RTMI_Msk       (0x1UL << FDCAN_TTIR_RTMI_Pos)               /*!< 0x00000010 */

+#define FDCAN_TTIR_RTMI           FDCAN_TTIR_RTMI_Msk                          /*!<Register Time Mark Interrupt              */

+#define FDCAN_TTIR_TTMI_Pos       (5U)

+#define FDCAN_TTIR_TTMI_Msk       (0x1UL << FDCAN_TTIR_TTMI_Pos)               /*!< 0x00000020 */

+#define FDCAN_TTIR_TTMI           FDCAN_TTIR_TTMI_Msk                          /*!<Trigger Time Mark Event Internal          */

+#define FDCAN_TTIR_SWE_Pos        (6U)

+#define FDCAN_TTIR_SWE_Msk        (0x1UL << FDCAN_TTIR_SWE_Pos)                /*!< 0x00000040 */

+#define FDCAN_TTIR_SWE            FDCAN_TTIR_SWE_Msk                           /*!<Stop Watch Event                          */

+#define FDCAN_TTIR_GTW_Pos        (7U)

+#define FDCAN_TTIR_GTW_Msk        (0x1UL << FDCAN_TTIR_GTW_Pos)                /*!< 0x00000080 */

+#define FDCAN_TTIR_GTW            FDCAN_TTIR_GTW_Msk                           /*!<Global Time Wrap                          */

+#define FDCAN_TTIR_GTD_Pos        (8U)

+#define FDCAN_TTIR_GTD_Msk        (0x1UL << FDCAN_TTIR_GTD_Pos)                /*!< 0x00000100 */

+#define FDCAN_TTIR_GTD            FDCAN_TTIR_GTD_Msk                           /*!<Global Time Discontinuity                 */

+#define FDCAN_TTIR_GTE_Pos        (9U)

+#define FDCAN_TTIR_GTE_Msk        (0x1UL << FDCAN_TTIR_GTE_Pos)                /*!< 0x00000200 */

+#define FDCAN_TTIR_GTE            FDCAN_TTIR_GTE_Msk                           /*!<Global Time Error                         */

+#define FDCAN_TTIR_TXU_Pos        (10U)

+#define FDCAN_TTIR_TXU_Msk        (0x1UL << FDCAN_TTIR_TXU_Pos)                /*!< 0x00000400 */

+#define FDCAN_TTIR_TXU            FDCAN_TTIR_TXU_Msk                           /*!<Tx Count Underflow                        */

+#define FDCAN_TTIR_TXO_Pos        (11U)

+#define FDCAN_TTIR_TXO_Msk        (0x1UL << FDCAN_TTIR_TXO_Pos)                /*!< 0x00000800 */

+#define FDCAN_TTIR_TXO            FDCAN_TTIR_TXO_Msk                           /*!<Tx Count Overflow                         */

+#define FDCAN_TTIR_SE1_Pos        (12U)

+#define FDCAN_TTIR_SE1_Msk        (0x1UL << FDCAN_TTIR_SE1_Pos)                /*!< 0x00001000 */

+#define FDCAN_TTIR_SE1            FDCAN_TTIR_SE1_Msk                           /*!<Scheduling Error 1                        */

+#define FDCAN_TTIR_SE2_Pos        (13U)

+#define FDCAN_TTIR_SE2_Msk        (0x1UL << FDCAN_TTIR_SE2_Pos)                /*!< 0x00002000 */

+#define FDCAN_TTIR_SE2            FDCAN_TTIR_SE2_Msk                           /*!<Scheduling Error 2                        */

+#define FDCAN_TTIR_ELC_Pos        (14U)

+#define FDCAN_TTIR_ELC_Msk        (0x1UL << FDCAN_TTIR_ELC_Pos)                /*!< 0x00004000 */

+#define FDCAN_TTIR_ELC            FDCAN_TTIR_ELC_Msk                           /*!<Error Level Changed                       */

+#define FDCAN_TTIR_IWT_Pos        (15U)

+#define FDCAN_TTIR_IWT_Msk        (0x1UL << FDCAN_TTIR_IWT_Pos)                /*!< 0x00008000 */

+#define FDCAN_TTIR_IWT            FDCAN_TTIR_IWT_Msk                           /*!<Initialization Watch Trigger              */

+#define FDCAN_TTIR_WT_Pos         (16U)

+#define FDCAN_TTIR_WT_Msk         (0x1UL << FDCAN_TTIR_WT_Pos)                 /*!< 0x00010000 */

+#define FDCAN_TTIR_WT             FDCAN_TTIR_WT_Msk                            /*!<Watch Trigger                             */

+#define FDCAN_TTIR_AW_Pos         (17U)

+#define FDCAN_TTIR_AW_Msk         (0x1UL << FDCAN_TTIR_AW_Pos)                 /*!< 0x00020000 */

+#define FDCAN_TTIR_AW             FDCAN_TTIR_AW_Msk                            /*!<Application Watchdog                      */

+#define FDCAN_TTIR_CER_Pos        (18U)

+#define FDCAN_TTIR_CER_Msk        (0x1UL << FDCAN_TTIR_CER_Pos)                /*!< 0x00040000 */

+#define FDCAN_TTIR_CER            FDCAN_TTIR_CER_Msk                           /*!<Configuration Error                       */

+

+/*****************  Bit definition for FDCAN_TTIE register  ********************/

+#define FDCAN_TTIE_SBCE_Pos       (0U)

+#define FDCAN_TTIE_SBCE_Msk       (0x1UL << FDCAN_TTIE_SBCE_Pos)               /*!< 0x00000001 */

+#define FDCAN_TTIE_SBCE           FDCAN_TTIE_SBCE_Msk                          /*!<Start of Basic Cycle Interrupt Enable             */

+#define FDCAN_TTIE_SMCE_Pos       (1U)

+#define FDCAN_TTIE_SMCE_Msk       (0x1UL << FDCAN_TTIE_SMCE_Pos)               /*!< 0x00000002 */

+#define FDCAN_TTIE_SMCE           FDCAN_TTIE_SMCE_Msk                          /*!<Start of Matrix Cycle Interrupt Enable            */

+#define FDCAN_TTIE_CSME_Pos       (2U)

+#define FDCAN_TTIE_CSME_Msk       (0x1UL << FDCAN_TTIE_CSME_Pos)               /*!< 0x00000004 */

+#define FDCAN_TTIE_CSME           FDCAN_TTIE_CSME_Msk                          /*!<Change of Synchronization Mode Interrupt Enable   */

+#define FDCAN_TTIE_SOGE_Pos       (3U)

+#define FDCAN_TTIE_SOGE_Msk       (0x1UL << FDCAN_TTIE_SOGE_Pos)               /*!< 0x00000008 */

+#define FDCAN_TTIE_SOGE           FDCAN_TTIE_SOGE_Msk                          /*!<Start of Gap Interrupt Enable                     */

+#define FDCAN_TTIE_RTMIE_Pos      (4U)

+#define FDCAN_TTIE_RTMIE_Msk      (0x1UL << FDCAN_TTIE_RTMIE_Pos)              /*!< 0x00000010 */

+#define FDCAN_TTIE_RTMIE          FDCAN_TTIE_RTMIE_Msk                         /*!<Register Time Mark Interrupt Interrupt Enable     */

+#define FDCAN_TTIE_TTMIE_Pos      (5U)

+#define FDCAN_TTIE_TTMIE_Msk      (0x1UL << FDCAN_TTIE_TTMIE_Pos)              /*!< 0x00000020 */

+#define FDCAN_TTIE_TTMIE          FDCAN_TTIE_TTMIE_Msk                         /*!<Trigger Time Mark Event Internal Interrupt Enable */

+#define FDCAN_TTIE_SWEE_Pos       (6U)

+#define FDCAN_TTIE_SWEE_Msk       (0x1UL << FDCAN_TTIE_SWEE_Pos)               /*!< 0x00000040 */

+#define FDCAN_TTIE_SWEE           FDCAN_TTIE_SWEE_Msk                          /*!<Stop Watch Event Interrupt Enable                 */

+#define FDCAN_TTIE_GTWE_Pos       (7U)

+#define FDCAN_TTIE_GTWE_Msk       (0x1UL << FDCAN_TTIE_GTWE_Pos)               /*!< 0x00000080 */

+#define FDCAN_TTIE_GTWE           FDCAN_TTIE_GTWE_Msk                          /*!<Global Time Wrap Interrupt Enable                 */

+#define FDCAN_TTIE_GTDE_Pos       (8U)

+#define FDCAN_TTIE_GTDE_Msk       (0x1UL << FDCAN_TTIE_GTDE_Pos)               /*!< 0x00000100 */

+#define FDCAN_TTIE_GTDE           FDCAN_TTIE_GTDE_Msk                          /*!<Global Time Discontinuity Interrupt Enable        */

+#define FDCAN_TTIE_GTEE_Pos       (9U)

+#define FDCAN_TTIE_GTEE_Msk       (0x1UL << FDCAN_TTIE_GTEE_Pos)               /*!< 0x00000200 */

+#define FDCAN_TTIE_GTEE           FDCAN_TTIE_GTEE_Msk                          /*!<Global Time Error Interrupt Enable                */

+#define FDCAN_TTIE_TXUE_Pos       (10U)

+#define FDCAN_TTIE_TXUE_Msk       (0x1UL << FDCAN_TTIE_TXUE_Pos)               /*!< 0x00000400 */

+#define FDCAN_TTIE_TXUE           FDCAN_TTIE_TXUE_Msk                          /*!<Tx Count Underflow Interrupt Enable               */

+#define FDCAN_TTIE_TXOE_Pos       (11U)

+#define FDCAN_TTIE_TXOE_Msk       (0x1UL << FDCAN_TTIE_TXOE_Pos)               /*!< 0x00000800 */

+#define FDCAN_TTIE_TXOE           FDCAN_TTIE_TXOE_Msk                          /*!<Tx Count Overflow Interrupt Enable                */

+#define FDCAN_TTIE_SE1E_Pos       (12U)

+#define FDCAN_TTIE_SE1E_Msk       (0x1UL << FDCAN_TTIE_SE1E_Pos)               /*!< 0x00001000 */

+#define FDCAN_TTIE_SE1E           FDCAN_TTIE_SE1E_Msk                          /*!<Scheduling Error 1 Interrupt Enable               */

+#define FDCAN_TTIE_SE2E_Pos       (13U)

+#define FDCAN_TTIE_SE2E_Msk       (0x1UL << FDCAN_TTIE_SE2E_Pos)               /*!< 0x00002000 */

+#define FDCAN_TTIE_SE2E           FDCAN_TTIE_SE2E_Msk                          /*!<Scheduling Error 2 Interrupt Enable               */

+#define FDCAN_TTIE_ELCE_Pos       (14U)

+#define FDCAN_TTIE_ELCE_Msk       (0x1UL << FDCAN_TTIE_ELCE_Pos)               /*!< 0x00004000 */

+#define FDCAN_TTIE_ELCE           FDCAN_TTIE_ELCE_Msk                          /*!<Error Level Changed Interrupt Enable              */

+#define FDCAN_TTIE_IWTE_Pos       (15U)

+#define FDCAN_TTIE_IWTE_Msk       (0x1UL << FDCAN_TTIE_IWTE_Pos)               /*!< 0x00008000 */

+#define FDCAN_TTIE_IWTE           FDCAN_TTIE_IWTE_Msk                          /*!<Initialization Watch Trigger Interrupt Enable     */

+#define FDCAN_TTIE_WTE_Pos        (16U)

+#define FDCAN_TTIE_WTE_Msk        (0x1UL << FDCAN_TTIE_WTE_Pos)                /*!< 0x00010000 */

+#define FDCAN_TTIE_WTE            FDCAN_TTIE_WTE_Msk                           /*!<Watch Trigger Interrupt Enable                    */

+#define FDCAN_TTIE_AWE_Pos        (17U)

+#define FDCAN_TTIE_AWE_Msk        (0x1UL << FDCAN_TTIE_AWE_Pos)                /*!< 0x00020000 */

+#define FDCAN_TTIE_AWE            FDCAN_TTIE_AWE_Msk                           /*!<Application Watchdog Interrupt Enable             */

+#define FDCAN_TTIE_CERE_Pos       (18U)

+#define FDCAN_TTIE_CERE_Msk       (0x1UL << FDCAN_TTIE_CERE_Pos)               /*!< 0x00040000 */

+#define FDCAN_TTIE_CERE           FDCAN_TTIE_CERE_Msk                          /*!<Configuration Error Interrupt Enable              */

+

+/*****************  Bit definition for FDCAN_TTILS register  ********************/

+#define FDCAN_TTILS_SBCS_Pos      (0U)

+#define FDCAN_TTILS_SBCS_Msk      (0x1UL << FDCAN_TTILS_SBCS_Pos)              /*!< 0x00000001 */

+#define FDCAN_TTILS_SBCS          FDCAN_TTILS_SBCS_Msk                         /*!<Start of Basic Cycle Interrupt Line               */

+#define FDCAN_TTILS_SMCS_Pos      (1U)

+#define FDCAN_TTILS_SMCS_Msk      (0x1UL << FDCAN_TTILS_SMCS_Pos)              /*!< 0x00000002 */

+#define FDCAN_TTILS_SMCS          FDCAN_TTILS_SMCS_Msk                         /*!<Start of Matrix Cycle Interrupt Line              */

+#define FDCAN_TTILS_CSMS_Pos      (2U)

+#define FDCAN_TTILS_CSMS_Msk      (0x1UL << FDCAN_TTILS_CSMS_Pos)              /*!< 0x00000004 */

+#define FDCAN_TTILS_CSMS          FDCAN_TTILS_CSMS_Msk                         /*!<Change of Synchronization Mode Interrupt Line     */

+#define FDCAN_TTILS_SOGS_Pos      (3U)

+#define FDCAN_TTILS_SOGS_Msk      (0x1UL << FDCAN_TTILS_SOGS_Pos)              /*!< 0x00000008 */

+#define FDCAN_TTILS_SOGS          FDCAN_TTILS_SOGS_Msk                         /*!<Start of Gap Interrupt Line                       */

+#define FDCAN_TTILS_RTMIS_Pos     (4U)

+#define FDCAN_TTILS_RTMIS_Msk     (0x1UL << FDCAN_TTILS_RTMIS_Pos)             /*!< 0x00000010 */

+#define FDCAN_TTILS_RTMIS         FDCAN_TTILS_RTMIS_Msk                        /*!<Register Time Mark Interrupt Interrupt Line       */

+#define FDCAN_TTILS_TTMIS_Pos     (5U)

+#define FDCAN_TTILS_TTMIS_Msk     (0x1UL << FDCAN_TTILS_TTMIS_Pos)             /*!< 0x00000020 */

+#define FDCAN_TTILS_TTMIS         FDCAN_TTILS_TTMIS_Msk                        /*!<Trigger Time Mark Event Internal Interrupt Line   */

+#define FDCAN_TTILS_SWES_Pos      (6U)

+#define FDCAN_TTILS_SWES_Msk      (0x1UL << FDCAN_TTILS_SWES_Pos)              /*!< 0x00000040 */

+#define FDCAN_TTILS_SWES          FDCAN_TTILS_SWES_Msk                         /*!<Stop Watch Event Interrupt Line                   */

+#define FDCAN_TTILS_GTWS_Pos      (7U)

+#define FDCAN_TTILS_GTWS_Msk      (0x1UL << FDCAN_TTILS_GTWS_Pos)              /*!< 0x00000080 */

+#define FDCAN_TTILS_GTWS          FDCAN_TTILS_GTWS_Msk                         /*!<Global Time Wrap Interrupt Line                   */

+#define FDCAN_TTILS_GTDS_Pos      (8U)

+#define FDCAN_TTILS_GTDS_Msk      (0x1UL << FDCAN_TTILS_GTDS_Pos)              /*!< 0x00000100 */

+#define FDCAN_TTILS_GTDS          FDCAN_TTILS_GTDS_Msk                         /*!<Global Time Discontinuity Interrupt Line          */

+#define FDCAN_TTILS_GTES_Pos      (9U)

+#define FDCAN_TTILS_GTES_Msk      (0x1UL << FDCAN_TTILS_GTES_Pos)              /*!< 0x00000200 */

+#define FDCAN_TTILS_GTES          FDCAN_TTILS_GTES_Msk                         /*!<Global Time Error Interrupt Line                  */

+#define FDCAN_TTILS_TXUS_Pos      (10U)

+#define FDCAN_TTILS_TXUS_Msk      (0x1UL << FDCAN_TTILS_TXUS_Pos)              /*!< 0x00000400 */

+#define FDCAN_TTILS_TXUS          FDCAN_TTILS_TXUS_Msk                         /*!<Tx Count Underflow Interrupt Line                 */

+#define FDCAN_TTILS_TXOS_Pos      (11U)

+#define FDCAN_TTILS_TXOS_Msk      (0x1UL << FDCAN_TTILS_TXOS_Pos)              /*!< 0x00000800 */

+#define FDCAN_TTILS_TXOS          FDCAN_TTILS_TXOS_Msk                         /*!<Tx Count Overflow Interrupt Line                  */

+#define FDCAN_TTILS_SE1S_Pos      (12U)

+#define FDCAN_TTILS_SE1S_Msk      (0x1UL << FDCAN_TTILS_SE1S_Pos)              /*!< 0x00001000 */

+#define FDCAN_TTILS_SE1S          FDCAN_TTILS_SE1S_Msk                         /*!<Scheduling Error 1 Interrupt Line                 */

+#define FDCAN_TTILS_SE2S_Pos      (13U)

+#define FDCAN_TTILS_SE2S_Msk      (0x1UL << FDCAN_TTILS_SE2S_Pos)              /*!< 0x00002000 */

+#define FDCAN_TTILS_SE2S          FDCAN_TTILS_SE2S_Msk                         /*!<Scheduling Error 2 Interrupt Line                 */

+#define FDCAN_TTILS_ELCS_Pos      (14U)

+#define FDCAN_TTILS_ELCS_Msk      (0x1UL << FDCAN_TTILS_ELCS_Pos)              /*!< 0x00004000 */

+#define FDCAN_TTILS_ELCS          FDCAN_TTILS_ELCS_Msk                         /*!<Error Level Changed Interrupt Line                */

+#define FDCAN_TTILS_IWTS_Pos      (15U)

+#define FDCAN_TTILS_IWTS_Msk      (0x1UL << FDCAN_TTILS_IWTS_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTILS_IWTS          FDCAN_TTILS_IWTS_Msk                         /*!<Initialization Watch Trigger Interrupt Line       */

+#define FDCAN_TTILS_WTS_Pos       (16U)

+#define FDCAN_TTILS_WTS_Msk       (0x1UL << FDCAN_TTILS_WTS_Pos)               /*!< 0x00010000 */

+#define FDCAN_TTILS_WTS           FDCAN_TTILS_WTS_Msk                          /*!<Watch Trigger Interrupt Line                      */

+#define FDCAN_TTILS_AWS_Pos       (17U)

+#define FDCAN_TTILS_AWS_Msk       (0x1UL << FDCAN_TTILS_AWS_Pos)               /*!< 0x00020000 */

+#define FDCAN_TTILS_AWS           FDCAN_TTILS_AWS_Msk                          /*!<Application Watchdog Interrupt Line               */

+#define FDCAN_TTILS_CERS_Pos      (18U)

+#define FDCAN_TTILS_CERS_Msk      (0x1UL << FDCAN_TTILS_CERS_Pos)              /*!< 0x00040000 */

+#define FDCAN_TTILS_CERS          FDCAN_TTILS_CERS_Msk                         /*!<Configuration Error Interrupt Line                */

+

+/*****************  Bit definition for FDCAN_TTOST register  ********************/

+#define FDCAN_TTOST_EL_Pos        (0U)

+#define FDCAN_TTOST_EL_Msk        (0x3UL << FDCAN_TTOST_EL_Pos)                /*!< 0x00000003 */

+#define FDCAN_TTOST_EL            FDCAN_TTOST_EL_Msk                           /*!<Error Level                              */

+#define FDCAN_TTOST_MS_Pos        (2U)

+#define FDCAN_TTOST_MS_Msk        (0x3UL << FDCAN_TTOST_MS_Pos)                /*!< 0x0000000C */

+#define FDCAN_TTOST_MS            FDCAN_TTOST_MS_Msk                           /*!<Master State                             */

+#define FDCAN_TTOST_SYS_Pos       (4U)

+#define FDCAN_TTOST_SYS_Msk       (0x3UL << FDCAN_TTOST_SYS_Pos)               /*!< 0x00000030 */

+#define FDCAN_TTOST_SYS           FDCAN_TTOST_SYS_Msk                          /*!<Synchronization State                    */

+#define FDCAN_TTOST_QGTP_Pos      (6U)

+#define FDCAN_TTOST_QGTP_Msk      (0x1UL << FDCAN_TTOST_QGTP_Pos)              /*!< 0x00000040 */

+#define FDCAN_TTOST_QGTP          FDCAN_TTOST_QGTP_Msk                         /*!<Quality of Global Time Phase             */

+#define FDCAN_TTOST_QCS_Pos       (7U)

+#define FDCAN_TTOST_QCS_Msk       (0x1UL << FDCAN_TTOST_QCS_Pos)               /*!< 0x00000080 */

+#define FDCAN_TTOST_QCS           FDCAN_TTOST_QCS_Msk                          /*!<Quality of Clock Speed                   */

+#define FDCAN_TTOST_RTO_Pos       (8U)

+#define FDCAN_TTOST_RTO_Msk       (0xFFUL << FDCAN_TTOST_RTO_Pos)              /*!< 0x0000FF00 */

+#define FDCAN_TTOST_RTO           FDCAN_TTOST_RTO_Msk                          /*!<Reference Trigger Offset                 */

+#define FDCAN_TTOST_WGTD_Pos      (22U)

+#define FDCAN_TTOST_WGTD_Msk      (0x1UL << FDCAN_TTOST_WGTD_Pos)              /*!< 0x00400000 */

+#define FDCAN_TTOST_WGTD          FDCAN_TTOST_WGTD_Msk                         /*!<Wait for Global Time Discontinuity       */

+#define FDCAN_TTOST_GFI_Pos       (23U)

+#define FDCAN_TTOST_GFI_Msk       (0x1UL << FDCAN_TTOST_GFI_Pos)               /*!< 0x00800000 */

+#define FDCAN_TTOST_GFI           FDCAN_TTOST_GFI_Msk                          /*!<Gap Finished Indicator                   */

+#define FDCAN_TTOST_TMP_Pos       (24U)

+#define FDCAN_TTOST_TMP_Msk       (0x7UL << FDCAN_TTOST_TMP_Pos)               /*!< 0x07000000 */

+#define FDCAN_TTOST_TMP           FDCAN_TTOST_TMP_Msk                          /*!<Time Master Priority                     */

+#define FDCAN_TTOST_GSI_Pos       (27U)

+#define FDCAN_TTOST_GSI_Msk       (0x1UL << FDCAN_TTOST_GSI_Pos)               /*!< 0x08000000 */

+#define FDCAN_TTOST_GSI           FDCAN_TTOST_GSI_Msk                          /*!<Gap Started Indicator                    */

+#define FDCAN_TTOST_WFE_Pos       (28U)

+#define FDCAN_TTOST_WFE_Msk       (0x1UL << FDCAN_TTOST_WFE_Pos)               /*!< 0x10000000 */

+#define FDCAN_TTOST_WFE           FDCAN_TTOST_WFE_Msk                          /*!<Wait for Event                           */

+#define FDCAN_TTOST_AWE_Pos       (29U)

+#define FDCAN_TTOST_AWE_Msk       (0x1UL << FDCAN_TTOST_AWE_Pos)               /*!< 0x20000000 */

+#define FDCAN_TTOST_AWE           FDCAN_TTOST_AWE_Msk                          /*!<Application Watchdog Event               */

+#define FDCAN_TTOST_WECS_Pos      (30U)

+#define FDCAN_TTOST_WECS_Msk      (0x1UL << FDCAN_TTOST_WECS_Pos)              /*!< 0x40000000 */

+#define FDCAN_TTOST_WECS          FDCAN_TTOST_WECS_Msk                         /*!<Wait for External Clock Synchronization  */

+#define FDCAN_TTOST_SPL_Pos       (31U)

+#define FDCAN_TTOST_SPL_Msk       (0x1UL << FDCAN_TTOST_SPL_Pos)               /*!< 0x80000000 */

+#define FDCAN_TTOST_SPL           FDCAN_TTOST_SPL_Msk                          /*!<Schedule Phase Lock                      */

+

+/*****************  Bit definition for FDCAN_TURNA register  ********************/

+#define FDCAN_TURNA_NAV_Pos       (0U)

+#define FDCAN_TURNA_NAV_Msk       (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)           /*!< 0x0003FFFF */

+#define FDCAN_TURNA_NAV           FDCAN_TURNA_NAV_Msk                          /*!<Numerator Actual Value                   */

+

+/*****************  Bit definition for FDCAN_TTLGT register  ********************/

+#define FDCAN_TTLGT_LT_Pos        (0U)

+#define FDCAN_TTLGT_LT_Msk        (0xFFFFUL << FDCAN_TTLGT_LT_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTLGT_LT            FDCAN_TTLGT_LT_Msk                           /*!<Local Time                               */

+#define FDCAN_TTLGT_GT_Pos        (16U)

+#define FDCAN_TTLGT_GT_Msk        (0xFFFFUL << FDCAN_TTLGT_GT_Pos)             /*!< 0xFFFF0000 */

+#define FDCAN_TTLGT_GT            FDCAN_TTLGT_GT_Msk                           /*!<Global Time                              */

+

+/*****************  Bit definition for FDCAN_TTCTC register  ********************/

+#define FDCAN_TTCTC_CT_Pos        (0U)

+#define FDCAN_TTCTC_CT_Msk        (0xFFFFUL << FDCAN_TTCTC_CT_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTCTC_CT            FDCAN_TTCTC_CT_Msk                           /*!<Cycle Time                               */

+#define FDCAN_TTCTC_CC_Pos        (16U)

+#define FDCAN_TTCTC_CC_Msk        (0x3FUL << FDCAN_TTCTC_CC_Pos)               /*!< 0x003F0000 */

+#define FDCAN_TTCTC_CC            FDCAN_TTCTC_CC_Msk                           /*!<Cycle Count                              */

+

+/*****************  Bit definition for FDCAN_TTCPT register  ********************/

+#define FDCAN_TTCPT_CCV_Pos       (0U)

+#define FDCAN_TTCPT_CCV_Msk       (0x3FUL << FDCAN_TTCPT_CCV_Pos)              /*!< 0x0000003F */

+#define FDCAN_TTCPT_CCV           FDCAN_TTCPT_CCV_Msk                          /*!<Cycle Count Value                        */

+#define FDCAN_TTCPT_SWV_Pos       (16U)

+#define FDCAN_TTCPT_SWV_Msk       (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)            /*!< 0xFFFF0000 */

+#define FDCAN_TTCPT_SWV           FDCAN_TTCPT_SWV_Msk                          /*!<Stop Watch Value                         */

+

+/*****************  Bit definition for FDCAN_TTCSM register  ********************/

+#define FDCAN_TTCSM_CSM_Pos       (0U)

+#define FDCAN_TTCSM_CSM_Msk       (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)            /*!< 0x0000FFFF */

+#define FDCAN_TTCSM_CSM           FDCAN_TTCSM_CSM_Msk                          /*!<Cycle Sync Mark                          */

+

+/*****************  Bit definition for FDCAN_TTTS register  *********************/

+#define FDCAN_TTTS_SWTSEL_Pos     (0U)

+#define FDCAN_TTTS_SWTSEL_Msk     (0x3UL << FDCAN_TTTS_SWTSEL_Pos)             /*!< 0x00000003 */

+#define FDCAN_TTTS_SWTSEL         FDCAN_TTTS_SWTSEL_Msk                        /*!<Stop watch trigger input selection       */

+#define FDCAN_TTTS_EVTSEL_Pos     (4U)

+#define FDCAN_TTTS_EVTSEL_Msk     (0x3UL << FDCAN_TTTS_EVTSEL_Pos)             /*!< 0x00000030 */

+#define FDCAN_TTTS_EVTSEL         FDCAN_TTTS_EVTSEL_Msk                        /*!<Event trigger input selection            */

+

+/********************************************************************************/

+/*                                                                              */

+/*                      FDCANCCU (Clock Calibration unit)                       */

+/*                                                                              */

+/********************************************************************************/

+

+/*****************  Bit definition for FDCANCCU_CREL register  ******************/

+#define FDCANCCU_CREL_DAY_Pos        (0U)

+#define FDCANCCU_CREL_DAY_Msk        (0xFFUL << FDCANCCU_CREL_DAY_Pos)         /*!< 0x000000FF */

+#define FDCANCCU_CREL_DAY            FDCANCCU_CREL_DAY_Msk                     /*!<Timestamp Day                           */

+#define FDCANCCU_CREL_MON_Pos        (8U)

+#define FDCANCCU_CREL_MON_Msk        (0xFFUL << FDCANCCU_CREL_MON_Pos)         /*!< 0x0000FF00 */

+#define FDCANCCU_CREL_MON            FDCANCCU_CREL_MON_Msk                     /*!<Timestamp Month                         */

+#define FDCANCCU_CREL_YEAR_Pos       (16U)

+#define FDCANCCU_CREL_YEAR_Msk       (0xFUL << FDCANCCU_CREL_YEAR_Pos)         /*!< 0x000F0000 */

+#define FDCANCCU_CREL_YEAR           FDCANCCU_CREL_YEAR_Msk                    /*!<Timestamp Year                          */

+#define FDCANCCU_CREL_SUBSTEP_Pos    (20U)

+#define FDCANCCU_CREL_SUBSTEP_Msk    (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)      /*!< 0x00F00000 */

+#define FDCANCCU_CREL_SUBSTEP        FDCANCCU_CREL_SUBSTEP_Msk                 /*!<Sub-step of Core release                */

+#define FDCANCCU_CREL_STEP_Pos       (24U)

+#define FDCANCCU_CREL_STEP_Msk       (0xFUL << FDCANCCU_CREL_STEP_Pos)         /*!< 0x0F000000 */

+#define FDCANCCU_CREL_STEP           FDCANCCU_CREL_STEP_Msk                    /*!<Step of Core release                    */

+#define FDCANCCU_CREL_REL_Pos        (28U)

+#define FDCANCCU_CREL_REL_Msk        (0xFUL << FDCANCCU_CREL_REL_Pos)          /*!< 0xF0000000 */

+#define FDCANCCU_CREL_REL            FDCANCCU_CREL_REL_Msk                     /*!<Core release                            */

+

+/*****************  Bit definition for FDCANCCU_CCFG register  ******************/

+#define FDCANCCU_CCFG_TQBT_Pos       (0U)

+#define FDCANCCU_CCFG_TQBT_Msk       (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)        /*!< 0x0000001F */

+#define FDCANCCU_CCFG_TQBT           FDCANCCU_CCFG_TQBT_Msk                    /*!<Time Quanta per Bit Time                */

+#define FDCANCCU_CCFG_BCC_Pos        (6U)

+#define FDCANCCU_CCFG_BCC_Msk        (0x1UL << FDCANCCU_CCFG_BCC_Pos)          /*!< 0x00000040 */

+#define FDCANCCU_CCFG_BCC            FDCANCCU_CCFG_BCC_Msk                     /*!<Bypass Clock Calibration                */

+#define FDCANCCU_CCFG_CFL_Pos        (7U)

+#define FDCANCCU_CCFG_CFL_Msk        (0x1UL << FDCANCCU_CCFG_CFL_Pos)          /*!< 0x00000080 */

+#define FDCANCCU_CCFG_CFL            FDCANCCU_CCFG_CFL_Msk                     /*!<Calibration Field Length                */

+#define FDCANCCU_CCFG_OCPM_Pos       (8U)

+#define FDCANCCU_CCFG_OCPM_Msk       (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)        /*!< 0x0000FF00 */

+#define FDCANCCU_CCFG_OCPM           FDCANCCU_CCFG_OCPM_Msk                    /*!<Oscillator Clock Periods Minimum        */

+#define FDCANCCU_CCFG_CDIV_Pos       (16U)

+#define FDCANCCU_CCFG_CDIV_Msk       (0xFUL << FDCANCCU_CCFG_CDIV_Pos)         /*!< 0x000F0000 */

+#define FDCANCCU_CCFG_CDIV           FDCANCCU_CCFG_CDIV_Msk                    /*!<Clock Divider                           */

+#define FDCANCCU_CCFG_SWR_Pos        (31U)

+#define FDCANCCU_CCFG_SWR_Msk        (0x1UL << FDCANCCU_CCFG_SWR_Pos)          /*!< 0x80000000 */

+#define FDCANCCU_CCFG_SWR            FDCANCCU_CCFG_SWR_Msk                     /*!<Software Reset                          */

+

+/*****************  Bit definition for FDCANCCU_CSTAT register  *****************/

+#define FDCANCCU_CSTAT_OCPC_Pos      (0U)

+#define FDCANCCU_CSTAT_OCPC_Msk      (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)    /*!< 0x0003FFFF */

+#define FDCANCCU_CSTAT_OCPC          FDCANCCU_CSTAT_OCPC_Msk                   /*!<Oscillator Clock Period Counter        */

+#define FDCANCCU_CSTAT_TQC_Pos       (18U)

+#define FDCANCCU_CSTAT_TQC_Msk       (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)       /*!< 0x1FFC0000 */

+#define FDCANCCU_CSTAT_TQC           FDCANCCU_CSTAT_TQC_Msk                    /*!<Time Quanta Counter                    */

+#define FDCANCCU_CSTAT_CALS_Pos      (30U)

+#define FDCANCCU_CSTAT_CALS_Msk      (0x3UL << FDCANCCU_CSTAT_CALS_Pos)        /*!< 0xC0000000 */

+#define FDCANCCU_CSTAT_CALS          FDCANCCU_CSTAT_CALS_Msk                   /*!<Calibration State                      */

+

+/******************  Bit definition for FDCANCCU_CWD register  ******************/

+#define FDCANCCU_CWD_WDC_Pos         (0U)

+#define FDCANCCU_CWD_WDC_Msk         (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)        /*!< 0x0000FFFF */

+#define FDCANCCU_CWD_WDC             FDCANCCU_CWD_WDC_Msk                      /*!<Watchdog Configuration                 */

+#define FDCANCCU_CWD_WDV_Pos         (16U)

+#define FDCANCCU_CWD_WDV_Msk         (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)        /*!< 0xFFFF0000 */

+#define FDCANCCU_CWD_WDV             FDCANCCU_CWD_WDV_Msk                      /*!<Watchdog Value                         */

+

+/******************  Bit definition for FDCANCCU_IR register  *******************/

+#define FDCANCCU_IR_CWE_Pos          (0U)

+#define FDCANCCU_IR_CWE_Msk          (0x1UL << FDCANCCU_IR_CWE_Pos)            /*!< 0x00000001 */

+#define FDCANCCU_IR_CWE              FDCANCCU_IR_CWE_Msk                       /*!<Calibration Watchdog Event             */

+#define FDCANCCU_IR_CSC_Pos          (1U)

+#define FDCANCCU_IR_CSC_Msk          (0x1UL << FDCANCCU_IR_CSC_Pos)            /*!< 0x00000002 */

+#define FDCANCCU_IR_CSC              FDCANCCU_IR_CSC_Msk                       /*!<Calibration State Changed              */

+

+/******************  Bit definition for FDCANCCU_IE register  *******************/

+#define FDCANCCU_IE_CWEE_Pos         (0U)

+#define FDCANCCU_IE_CWEE_Msk         (0x1UL << FDCANCCU_IE_CWEE_Pos)           /*!< 0x00000001 */

+#define FDCANCCU_IE_CWEE             FDCANCCU_IE_CWEE_Msk                      /*!<Calibration Watchdog Event Enable      */

+#define FDCANCCU_IE_CSCE_Pos         (1U)

+#define FDCANCCU_IE_CSCE_Msk         (0x1UL << FDCANCCU_IE_CSCE_Pos)           /*!< 0x00000002 */

+#define FDCANCCU_IE_CSCE             FDCANCCU_IE_CSCE_Msk                      /*!<Calibration State Changed Enable       */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          HDMI-CEC (CEC)                                    */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for CEC_CR register  *********************/

+#define CEC_CR_CECEN_Pos         (0U)

+#define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                   /*!< 0x00000001 */

+#define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                                */

+#define CEC_CR_TXSOM_Pos         (1U)

+#define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                   /*!< 0x00000002 */

+#define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message                   */

+#define CEC_CR_TXEOM_Pos         (2U)

+#define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                   /*!< 0x00000004 */

+#define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message                     */

+

+/*******************  Bit definition for CEC_CFGR register  *******************/

+#define CEC_CFGR_SFT_Pos         (0U)

+#define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                   /*!< 0x00000007 */

+#define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time                      */

+#define CEC_CFGR_RXTOL_Pos       (3U)

+#define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                 /*!< 0x00000008 */

+#define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                             */

+#define CEC_CFGR_BRESTP_Pos      (4U)

+#define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                /*!< 0x00000010 */

+#define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                               */

+#define CEC_CFGR_BREGEN_Pos      (5U)

+#define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                /*!< 0x00000020 */

+#define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation           */

+#define CEC_CFGR_LBPEGEN_Pos     (6U)

+#define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)               /*!< 0x00000040 */

+#define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error generation      */

+#define CEC_CFGR_SFTOPT_Pos      (8U)

+#define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                /*!< 0x00000100 */

+#define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional             */

+#define CEC_CFGR_BRDNOGEN_Pos    (7U)

+#define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)              /*!< 0x00000080 */

+#define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No error generation         */

+#define CEC_CFGR_OAR_Pos         (16U)

+#define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                /*!< 0x7FFF0000 */

+#define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                           */

+#define CEC_CFGR_LSTN_Pos        (31U)

+#define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                  /*!< 0x80000000 */

+#define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                           */

+

+/*******************  Bit definition for CEC_TXDR register  *******************/

+#define CEC_TXDR_TXD_Pos         (0U)

+#define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                  /*!< 0x000000FF */

+#define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                               */

+

+/*******************  Bit definition for CEC_RXDR register  *******************/

+#define CEC_RXDR_RXD_Pos         (0U)

+#define CEC_RXDR_RXD_Msk         (0xFFUL << CEC_RXDR_RXD_Pos)                  /*!< 0x000000FF */

+#define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                              /*!< CEC Rx Data                               */

+

+/*******************  Bit definition for CEC_ISR register  ********************/

+#define CEC_ISR_RXBR_Pos         (0U)

+#define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                   /*!< 0x00000001 */

+#define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                      */

+#define CEC_ISR_RXEND_Pos        (1U)

+#define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                  /*!< 0x00000002 */

+#define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                      */

+#define CEC_ISR_RXOVR_Pos        (2U)

+#define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                  /*!< 0x00000004 */

+#define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                            */

+#define CEC_ISR_BRE_Pos          (3U)

+#define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                    /*!< 0x00000008 */

+#define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                   */

+#define CEC_ISR_SBPE_Pos         (4U)

+#define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                   /*!< 0x00000010 */

+#define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error             */

+#define CEC_ISR_LBPE_Pos         (5U)

+#define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                   /*!< 0x00000020 */

+#define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error              */

+#define CEC_ISR_RXACKE_Pos       (6U)

+#define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                 /*!< 0x00000040 */

+#define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge                */

+#define CEC_ISR_ARBLST_Pos       (7U)

+#define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                 /*!< 0x00000080 */

+#define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                      */

+#define CEC_ISR_TXBR_Pos         (8U)

+#define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                   /*!< 0x00000100 */

+#define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                       */

+#define CEC_ISR_TXEND_Pos        (9U)

+#define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                  /*!< 0x00000200 */

+#define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                   */

+#define CEC_ISR_TXUDR_Pos        (10U)

+#define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                  /*!< 0x00000400 */

+#define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                    */

+#define CEC_ISR_TXERR_Pos        (11U)

+#define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                  /*!< 0x00000800 */

+#define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                              */

+#define CEC_ISR_TXACKE_Pos       (12U)

+#define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                 /*!< 0x00001000 */

+#define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge                */

+

+/*******************  Bit definition for CEC_IER register  ********************/

+#define CEC_IER_RXBRIE_Pos       (0U)

+#define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                 /*!< 0x00000001 */

+#define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable            */

+#define CEC_IER_RXENDIE_Pos      (1U)

+#define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                /*!< 0x00000002 */

+#define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable            */

+#define CEC_IER_RXOVRIE_Pos      (2U)

+#define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                /*!< 0x00000004 */

+#define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable                  */

+#define CEC_IER_BREIE_Pos        (3U)

+#define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                  /*!< 0x00000008 */

+#define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable         */

+#define CEC_IER_SBPEIE_Pos       (4U)

+#define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                 /*!< 0x00000010 */

+#define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable   */

+#define CEC_IER_LBPEIE_Pos       (5U)

+#define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                 /*!< 0x00000020 */

+#define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable    */

+#define CEC_IER_RXACKEIE_Pos     (6U)

+#define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)               /*!< 0x00000040 */

+#define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable      */

+#define CEC_IER_ARBLSTIE_Pos     (7U)

+#define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)               /*!< 0x00000080 */

+#define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable            */

+#define CEC_IER_TXBRIE_Pos       (8U)

+#define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                 /*!< 0x00000100 */

+#define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable            */

+#define CEC_IER_TXENDIE_Pos      (9U)

+#define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                /*!< 0x00000200 */

+#define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable         */

+#define CEC_IER_TXUDRIE_Pos      (10U)

+#define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                /*!< 0x00000400 */

+#define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable          */

+#define CEC_IER_TXERRIE_Pos      (11U)

+#define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                /*!< 0x00000800 */

+#define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                    */

+#define CEC_IER_TXACKEIE_Pos     (12U)

+#define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)               /*!< 0x00001000 */

+#define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable      */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          CRC calculation unit                              */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for CRC_DR register  *********************/

+#define CRC_DR_DR_Pos            (0U)

+#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */

+#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */

+

+/*******************  Bit definition for CRC_IDR register  ********************/

+#define CRC_IDR_IDR_Pos          (0U)

+#define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */

+#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */

+

+/********************  Bit definition for CRC_CR register  ********************/

+#define CRC_CR_RESET_Pos         (0U)

+#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */

+#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */

+#define CRC_CR_POLYSIZE_Pos      (3U)

+#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */

+#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */

+#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */

+#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */

+#define CRC_CR_REV_IN_Pos        (5U)

+#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */

+#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */

+#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */

+#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */

+#define CRC_CR_REV_OUT_Pos       (7U)

+#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */

+#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */

+

+/*******************  Bit definition for CRC_INIT register  *******************/

+#define CRC_INIT_INIT_Pos        (0U)

+#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */

+#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */

+

+/*******************  Bit definition for CRC_POL register  ********************/

+#define CRC_POL_POL_Pos          (0U)

+#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */

+#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          CRS Clock Recovery System                         */

+/******************************************************************************/

+

+/*******************  Bit definition for CRS_CR register  *********************/

+#define CRS_CR_SYNCOKIE_Pos       (0U)

+#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */

+#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */

+#define CRS_CR_SYNCWARNIE_Pos     (1U)

+#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */

+#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */

+#define CRS_CR_ERRIE_Pos          (2U)

+#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */

+#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */

+#define CRS_CR_ESYNCIE_Pos        (3U)

+#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */

+#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */

+#define CRS_CR_CEN_Pos            (5U)

+#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */

+#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */

+#define CRS_CR_AUTOTRIMEN_Pos     (6U)

+#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */

+#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */

+#define CRS_CR_SWSYNC_Pos         (7U)

+#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */

+#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */

+#define CRS_CR_TRIM_Pos           (8U)

+#define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00003F00 */

+#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */

+

+/*******************  Bit definition for CRS_CFGR register  *********************/

+#define CRS_CFGR_RELOAD_Pos       (0U)

+#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */

+#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */

+#define CRS_CFGR_FELIM_Pos        (16U)

+#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */

+#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */

+

+#define CRS_CFGR_SYNCDIV_Pos      (24U)

+#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */

+#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */

+#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */

+#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */

+#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */

+

+#define CRS_CFGR_SYNCSRC_Pos      (28U)

+#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */

+#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */

+#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */

+#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */

+

+#define CRS_CFGR_SYNCPOL_Pos      (31U)

+#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */

+#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */

+

+/*******************  Bit definition for CRS_ISR register  *********************/

+#define CRS_ISR_SYNCOKF_Pos       (0U)

+#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */

+#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */

+#define CRS_ISR_SYNCWARNF_Pos     (1U)

+#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */

+#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */

+#define CRS_ISR_ERRF_Pos          (2U)

+#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */

+#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */

+#define CRS_ISR_ESYNCF_Pos        (3U)

+#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */

+#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */

+#define CRS_ISR_SYNCERR_Pos       (8U)

+#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */

+#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */

+#define CRS_ISR_SYNCMISS_Pos      (9U)

+#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */

+#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */

+#define CRS_ISR_TRIMOVF_Pos       (10U)

+#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */

+#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */

+#define CRS_ISR_FEDIR_Pos         (15U)

+#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */

+#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */

+#define CRS_ISR_FECAP_Pos         (16U)

+#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */

+#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */

+

+/*******************  Bit definition for CRS_ICR register  *********************/

+#define CRS_ICR_SYNCOKC_Pos       (0U)

+#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */

+#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */

+#define CRS_ICR_SYNCWARNC_Pos     (1U)

+#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */

+#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */

+#define CRS_ICR_ERRC_Pos          (2U)

+#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */

+#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */

+#define CRS_ICR_ESYNCC_Pos        (3U)

+#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */

+#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      Digital to Analog Converter                           */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for DAC_CR register  ********************/

+#define DAC_CR_EN1_Pos              (0U)

+#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */

+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */

+#define DAC_CR_TEN1_Pos             (1U)

+#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */

+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */

+

+#define DAC_CR_TSEL1_Pos            (2U)

+#define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */

+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */

+#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000004 */

+#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */

+#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */

+#define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */

+

+

+#define DAC_CR_WAVE1_Pos            (6U)

+#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */

+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */

+#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */

+#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */

+

+#define DAC_CR_MAMP1_Pos            (8U)

+#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */

+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */

+#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */

+#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */

+#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */

+#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */

+

+#define DAC_CR_DMAEN1_Pos           (12U)

+#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */

+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */

+#define DAC_CR_DMAUDRIE1_Pos        (13U)

+#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */

+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/

+#define DAC_CR_CEN1_Pos             (14U)

+#define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */

+#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/

+

+#define DAC_CR_EN2_Pos              (16U)

+#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */

+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */

+#define DAC_CR_TEN2_Pos             (17U)

+#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */

+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */

+

+#define DAC_CR_TSEL2_Pos            (18U)

+#define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */

+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */

+#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00040000 */

+#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */

+#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */

+#define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */

+

+

+#define DAC_CR_WAVE2_Pos            (22U)

+#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */

+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */

+#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */

+#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */

+

+#define DAC_CR_MAMP2_Pos            (24U)

+#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */

+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */

+#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */

+#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */

+#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */

+#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */

+

+#define DAC_CR_DMAEN2_Pos           (28U)

+#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */

+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */

+#define DAC_CR_DMAUDRIE2_Pos        (29U)

+#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */

+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/

+#define DAC_CR_CEN2_Pos             (30U)

+#define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */

+#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/

+

+/*****************  Bit definition for DAC_SWTRIGR register  ******************/

+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)

+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */

+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */

+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)

+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */

+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */

+

+/*****************  Bit definition for DAC_DHR12R1 register  ******************/

+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)

+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12L1 register  ******************/

+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)

+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8R1 register  ******************/

+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)

+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12R2 register  ******************/

+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)

+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12L2 register  ******************/

+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)

+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8R2 register  ******************/

+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)

+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12RD register  ******************/

+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)

+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */

+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)

+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */

+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12LD register  ******************/

+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)

+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */

+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)

+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */

+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8RD register  ******************/

+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)

+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */

+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)

+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */

+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */

+

+/*******************  Bit definition for DAC_DOR1 register  *******************/

+#define DAC_DOR1_DACC1DOR_Pos       (0U)

+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */

+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */

+

+/*******************  Bit definition for DAC_DOR2 register  *******************/

+#define DAC_DOR2_DACC2DOR_Pos       (0U)

+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */

+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */

+

+/********************  Bit definition for DAC_SR register  ********************/

+#define DAC_SR_DMAUDR1_Pos          (13U)

+#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */

+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */

+#define DAC_SR_CAL_FLAG1_Pos        (14U)

+#define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */

+#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */

+#define DAC_SR_BWST1_Pos            (15U)

+#define DAC_SR_BWST1_Msk            (0x4001UL << DAC_SR_BWST1_Pos)             /*!< 0x20008000 */

+#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */

+

+#define DAC_SR_DMAUDR2_Pos          (29U)

+#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */

+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */

+#define DAC_SR_CAL_FLAG2_Pos        (30U)

+#define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */

+#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */

+#define DAC_SR_BWST2_Pos            (31U)

+#define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */

+#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */

+

+/*******************  Bit definition for DAC_CCR register  ********************/

+#define DAC_CCR_OTRIM1_Pos          (0U)

+#define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */

+#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */

+#define DAC_CCR_OTRIM2_Pos          (16U)

+#define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */

+#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */

+

+/*******************  Bit definition for DAC_MCR register  *******************/

+#define DAC_MCR_MODE1_Pos           (0U)

+#define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */

+#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */

+#define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */

+#define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */

+#define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */

+

+#define DAC_MCR_MODE2_Pos           (16U)

+#define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */

+#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */

+#define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */

+#define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */

+#define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */

+

+/******************  Bit definition for DAC_SHSR1 register  ******************/

+#define DAC_SHSR1_TSAMPLE1_Pos      (0U)

+#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */

+#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */

+

+/******************  Bit definition for DAC_SHSR2 register  ******************/

+#define DAC_SHSR2_TSAMPLE2_Pos      (0U)

+#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */

+#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */

+

+/******************  Bit definition for DAC_SHHR register  ******************/

+#define DAC_SHHR_THOLD1_Pos         (0U)

+#define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */

+#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */

+#define DAC_SHHR_THOLD2_Pos         (16U)

+#define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */

+#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */

+

+/******************  Bit definition for DAC_SHRR register  ******************/

+#define DAC_SHRR_TREFRESH1_Pos      (0U)

+#define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */

+#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */

+#define DAC_SHRR_TREFRESH2_Pos      (16U)

+#define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */

+#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    DCMI                                    */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DCMI_CR register  ******************/

+#define DCMI_CR_CAPTURE_Pos        (0U)

+#define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)              /*!< 0x00000001 */

+#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk

+#define DCMI_CR_CM_Pos             (1U)

+#define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                   /*!< 0x00000002 */

+#define DCMI_CR_CM                 DCMI_CR_CM_Msk

+#define DCMI_CR_CROP_Pos           (2U)

+#define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                 /*!< 0x00000004 */

+#define DCMI_CR_CROP               DCMI_CR_CROP_Msk

+#define DCMI_CR_JPEG_Pos           (3U)

+#define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                 /*!< 0x00000008 */

+#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk

+#define DCMI_CR_ESS_Pos            (4U)

+#define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                  /*!< 0x00000010 */

+#define DCMI_CR_ESS                DCMI_CR_ESS_Msk

+#define DCMI_CR_PCKPOL_Pos         (5U)

+#define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)               /*!< 0x00000020 */

+#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk

+#define DCMI_CR_HSPOL_Pos          (6U)

+#define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                /*!< 0x00000040 */

+#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk

+#define DCMI_CR_VSPOL_Pos          (7U)

+#define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */

+#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk

+#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)

+#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)

+#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)

+#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)

+#define DCMI_CR_CRE_Pos            (12U)

+#define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */

+#define DCMI_CR_CRE                DCMI_CR_CRE_Msk

+#define DCMI_CR_ENABLE_Pos         (14U)

+#define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)               /*!< 0x00004000 */

+#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk

+#define DCMI_CR_BSM_Pos            (16U)

+#define DCMI_CR_BSM_Msk            (0x3UL << DCMI_CR_BSM_Pos)                  /*!< 0x00030000 */

+#define DCMI_CR_BSM                DCMI_CR_BSM_Msk

+#define DCMI_CR_BSM_0              (0x1UL << DCMI_CR_BSM_Pos)                   /*!< 0x00010000 */

+#define DCMI_CR_BSM_1              (0x2UL << DCMI_CR_BSM_Pos)                   /*!< 0x00020000 */

+#define DCMI_CR_OEBS_Pos           (18U)

+#define DCMI_CR_OEBS_Msk           (0x1UL << DCMI_CR_OEBS_Pos)                 /*!< 0x00040000 */

+#define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk

+#define DCMI_CR_LSM_Pos            (19U)

+#define DCMI_CR_LSM_Msk            (0x1UL << DCMI_CR_LSM_Pos)                  /*!< 0x00080000 */

+#define DCMI_CR_LSM                DCMI_CR_LSM_Msk

+#define DCMI_CR_OELS_Pos           (20U)

+#define DCMI_CR_OELS_Msk           (0x1UL << DCMI_CR_OELS_Pos)                 /*!< 0x00100000 */

+#define DCMI_CR_OELS               DCMI_CR_OELS_Msk

+

+/********************  Bits definition for DCMI_SR register  ******************/

+#define DCMI_SR_HSYNC_Pos          (0U)

+#define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                /*!< 0x00000001 */

+#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk

+#define DCMI_SR_VSYNC_Pos          (1U)

+#define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                /*!< 0x00000002 */

+#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk

+#define DCMI_SR_FNE_Pos            (2U)

+#define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                  /*!< 0x00000004 */

+#define DCMI_SR_FNE                DCMI_SR_FNE_Msk

+

+/********************  Bits definition for DCMI_RIS register   ****************/

+#define DCMI_RIS_FRAME_RIS_Pos     (0U)

+#define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)           /*!< 0x00000001 */

+#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk

+#define DCMI_RIS_OVR_RIS_Pos       (1U)

+#define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)             /*!< 0x00000002 */

+#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk

+#define DCMI_RIS_ERR_RIS_Pos       (2U)

+#define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)             /*!< 0x00000004 */

+#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk

+#define DCMI_RIS_VSYNC_RIS_Pos     (3U)

+#define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)           /*!< 0x00000008 */

+#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk

+#define DCMI_RIS_LINE_RIS_Pos      (4U)

+#define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)            /*!< 0x00000010 */

+#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk

+

+/********************  Bits definition for DCMI_IER register  *****************/

+#define DCMI_IER_FRAME_IE_Pos      (0U)

+#define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)            /*!< 0x00000001 */

+#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk

+#define DCMI_IER_OVR_IE_Pos        (1U)

+#define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)              /*!< 0x00000002 */

+#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk

+#define DCMI_IER_ERR_IE_Pos        (2U)

+#define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)              /*!< 0x00000004 */

+#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk

+#define DCMI_IER_VSYNC_IE_Pos      (3U)

+#define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)            /*!< 0x00000008 */

+#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk

+#define DCMI_IER_LINE_IE_Pos       (4U)

+#define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)             /*!< 0x00000010 */

+#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk

+

+

+/********************  Bits definition for DCMI_MIS register  *****************/

+#define DCMI_MIS_FRAME_MIS_Pos     (0U)

+#define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)           /*!< 0x00000001 */

+#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk

+#define DCMI_MIS_OVR_MIS_Pos       (1U)

+#define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)             /*!< 0x00000002 */

+#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk

+#define DCMI_MIS_ERR_MIS_Pos       (2U)

+#define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)             /*!< 0x00000004 */

+#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk

+#define DCMI_MIS_VSYNC_MIS_Pos     (3U)

+#define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)           /*!< 0x00000008 */

+#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk

+#define DCMI_MIS_LINE_MIS_Pos      (4U)

+#define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)            /*!< 0x00000010 */

+#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk

+

+

+/********************  Bits definition for DCMI_ICR register  *****************/

+#define DCMI_ICR_FRAME_ISC_Pos     (0U)

+#define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)           /*!< 0x00000001 */

+#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk

+#define DCMI_ICR_OVR_ISC_Pos       (1U)

+#define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)             /*!< 0x00000002 */

+#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk

+#define DCMI_ICR_ERR_ISC_Pos       (2U)

+#define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)             /*!< 0x00000004 */

+#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk

+#define DCMI_ICR_VSYNC_ISC_Pos     (3U)

+#define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)           /*!< 0x00000008 */

+#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk

+#define DCMI_ICR_LINE_ISC_Pos      (4U)

+#define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)            /*!< 0x00000010 */

+#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk

+

+

+/********************  Bits definition for DCMI_ESCR register  ******************/

+#define DCMI_ESCR_FSC_Pos          (0U)

+#define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)               /*!< 0x000000FF */

+#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk

+#define DCMI_ESCR_LSC_Pos          (8U)

+#define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)               /*!< 0x0000FF00 */

+#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk

+#define DCMI_ESCR_LEC_Pos          (16U)

+#define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)               /*!< 0x00FF0000 */

+#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk

+#define DCMI_ESCR_FEC_Pos          (24U)

+#define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)               /*!< 0xFF000000 */

+#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk

+

+/********************  Bits definition for DCMI_ESUR register  ******************/

+#define DCMI_ESUR_FSU_Pos          (0U)

+#define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)               /*!< 0x000000FF */

+#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk

+#define DCMI_ESUR_LSU_Pos          (8U)

+#define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)               /*!< 0x0000FF00 */

+#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk

+#define DCMI_ESUR_LEU_Pos          (16U)

+#define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)               /*!< 0x00FF0000 */

+#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk

+#define DCMI_ESUR_FEU_Pos          (24U)

+#define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)               /*!< 0xFF000000 */

+#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk

+

+/********************  Bits definition for DCMI_CWSTRT register  ******************/

+#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)

+#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)       /*!< 0x00003FFF */

+#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk

+#define DCMI_CWSTRT_VST_Pos        (16U)

+#define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)           /*!< 0x1FFF0000 */

+#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk

+

+/********************  Bits definition for DCMI_CWSIZE register  ******************/

+#define DCMI_CWSIZE_CAPCNT_Pos     (0U)

+#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)        /*!< 0x00003FFF */

+#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk

+#define DCMI_CWSIZE_VLINE_Pos      (16U)

+#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)         /*!< 0x3FFF0000 */

+#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk

+

+/********************  Bits definition for DCMI_DR register  ******************/

+#define DCMI_DR_BYTE0_Pos          (0U)

+#define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)               /*!< 0x000000FF */

+#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk

+#define DCMI_DR_BYTE1_Pos          (8U)

+#define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)               /*!< 0x0000FF00 */

+#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk

+#define DCMI_DR_BYTE2_Pos          (16U)

+#define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)               /*!< 0x00FF0000 */

+#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk

+#define DCMI_DR_BYTE3_Pos          (24U)

+#define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)               /*!< 0xFF000000 */

+#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                 Digital Filter for Sigma Delta Modulators                  */

+/*                                                                            */

+/******************************************************************************/

+

+/****************   DFSDM channel configuration registers  ********************/

+

+/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/

+#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)

+#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)   /*!< 0x80000000 */

+#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */

+#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)

+#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)  /*!< 0x40000000 */

+#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */

+#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)

+#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */

+#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */

+#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)

+#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x0000C000 */

+#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */

+#define DFSDM_CHCFGR1_DATPACK_1         (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */

+#define DFSDM_CHCFGR1_DATPACK_0         (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */

+#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)

+#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00003000 */

+#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */

+#define DFSDM_CHCFGR1_DATMPX_1          (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */

+#define DFSDM_CHCFGR1_DATMPX_0          (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */

+#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)

+#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)   /*!< 0x00000100 */

+#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */

+#define DFSDM_CHCFGR1_CHEN_Pos          (7U)

+#define DFSDM_CHCFGR1_CHEN_Msk          (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)      /*!< 0x00000080 */

+#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */

+#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)

+#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)    /*!< 0x00000040 */

+#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */

+#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)

+#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)     /*!< 0x00000020 */

+#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */

+#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)

+#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x0000000C */

+#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */

+#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */

+#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */

+#define DFSDM_CHCFGR1_SITP_Pos          (0U)

+#define DFSDM_CHCFGR1_SITP_Msk          (0x3UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000003 */

+#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */

+#define DFSDM_CHCFGR1_SITP_1            (0x2UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */

+#define DFSDM_CHCFGR1_SITP_0            (0x1UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */

+

+/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/

+#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)

+#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */

+#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)

+#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)    /*!< 0x000000F8 */

+#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */

+

+/******************  Bit definition for DFSDM_CHAWSCDR register *****************/

+#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)

+#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00C00000 */

+#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */

+#define DFSDM_CHAWSCDR_AWFORD_1         (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */

+#define DFSDM_CHAWSCDR_AWFORD_0         (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */

+#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)

+#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)  /*!< 0x001F0000 */

+#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */

+#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)

+#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)    /*!< 0x0000F000 */

+#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */

+#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)

+#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)    /*!< 0x000000FF */

+#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */

+

+/****************  Bit definition for DFSDM_CHWDATR register *******************/

+#define DFSDM_CHWDATR_WDATA_Pos         (0U)

+#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)  /*!< 0x0000FFFF */

+#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */

+

+/****************  Bit definition for DFSDM_CHDATINR register *****************/

+#define DFSDM_CHDATINR_INDAT0_Pos       (0U)

+#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */

+#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */

+#define DFSDM_CHDATINR_INDAT1_Pos       (16U)

+#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */

+#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */

+

+/****************  Bit definition for DFSDM_CHDLYR register *****************/

+#define DFSDM_CHDLYR_PLSSKP_Pos         (0U)

+#define DFSDM_CHDLYR_PLSSKP_Msk         (0x3FUL << DFSDM_CHDLYR_PLSSKP_Pos)    /*!< 0x0000003F*/

+#define DFSDM_CHDLYR_PLSSKP             DFSDM_CHDLYR_PLSSKP_Msk

+/************************   DFSDM module registers  ****************************/

+

+/********************  Bit definition for DFSDM_FLTCR1 register *******************/

+#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)

+#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)     /*!< 0x40000000 */

+#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */

+#define DFSDM_FLTCR1_FAST_Pos           (29U)

+#define DFSDM_FLTCR1_FAST_Msk           (0x1UL << DFSDM_FLTCR1_FAST_Pos)       /*!< 0x20000000 */

+#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */

+#define DFSDM_FLTCR1_RCH_Pos            (24U)

+#define DFSDM_FLTCR1_RCH_Msk            (0x7UL << DFSDM_FLTCR1_RCH_Pos)        /*!< 0x07000000 */

+#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */

+#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)

+#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)     /*!< 0x00200000 */

+#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */

+#define DFSDM_FLTCR1_RSYNC_Pos          (19U)

+#define DFSDM_FLTCR1_RSYNC_Msk          (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)      /*!< 0x00080000 */

+#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */

+#define DFSDM_FLTCR1_RCONT_Pos          (18U)

+#define DFSDM_FLTCR1_RCONT_Msk          (0x1UL << DFSDM_FLTCR1_RCONT_Pos)      /*!< 0x00040000 */

+#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */

+#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)

+#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)   /*!< 0x00020000 */

+#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */

+#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)

+#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00006000 */

+#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */

+#define DFSDM_FLTCR1_JEXTEN_1           (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */

+#define DFSDM_FLTCR1_JEXTEN_0           (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */

+#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)

+#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)   /*!< 0x00001F00 */

+#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */

+#define DFSDM_FLTCR1_JEXTSEL_0          (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000100 */

+#define DFSDM_FLTCR1_JEXTSEL_1          (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000200 */

+#define DFSDM_FLTCR1_JEXTSEL_2          (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000400 */

+#define DFSDM_FLTCR1_JEXTSEL_3          (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000800 */

+#define DFSDM_FLTCR1_JEXTSEL_4          (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00001000 */

+

+#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)

+#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)     /*!< 0x00000020 */

+#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */

+#define DFSDM_FLTCR1_JSCAN_Pos          (4U)

+#define DFSDM_FLTCR1_JSCAN_Msk          (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)      /*!< 0x00000010 */

+#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */

+#define DFSDM_FLTCR1_JSYNC_Pos          (3U)

+#define DFSDM_FLTCR1_JSYNC_Msk          (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)      /*!< 0x00000008 */

+#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */

+#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)

+#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)   /*!< 0x00000002 */

+#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */

+#define DFSDM_FLTCR1_DFEN_Pos           (0U)

+#define DFSDM_FLTCR1_DFEN_Msk           (0x1UL << DFSDM_FLTCR1_DFEN_Pos)       /*!< 0x00000001 */

+#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */

+

+/********************  Bit definition for DFSDM_FLTCR2 register *******************/

+#define DFSDM_FLTCR2_AWDCH_Pos          (16U)

+#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)     /*!< 0x00FF0000 */

+#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */

+#define DFSDM_FLTCR2_EXCH_Pos           (8U)

+#define DFSDM_FLTCR2_EXCH_Msk           (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)      /*!< 0x0000FF00 */

+#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */

+#define DFSDM_FLTCR2_CKABIE_Pos         (6U)

+#define DFSDM_FLTCR2_CKABIE_Msk         (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)     /*!< 0x00000040 */

+#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */

+#define DFSDM_FLTCR2_SCDIE_Pos          (5U)

+#define DFSDM_FLTCR2_SCDIE_Msk          (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)      /*!< 0x00000020 */

+#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */

+#define DFSDM_FLTCR2_AWDIE_Pos          (4U)

+#define DFSDM_FLTCR2_AWDIE_Msk          (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)      /*!< 0x00000010 */

+#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */

+#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)

+#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)     /*!< 0x00000008 */

+#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */

+#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)

+#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)     /*!< 0x00000004 */

+#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */

+#define DFSDM_FLTCR2_REOCIE_Pos         (1U)

+#define DFSDM_FLTCR2_REOCIE_Msk         (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)     /*!< 0x00000002 */

+#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */

+#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)

+#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)     /*!< 0x00000001 */

+#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */

+

+/********************  Bit definition for DFSDM_FLTISR register *******************/

+#define DFSDM_FLTISR_SCDF_Pos           (24U)

+#define DFSDM_FLTISR_SCDF_Msk           (0xFFUL << DFSDM_FLTISR_SCDF_Pos)      /*!< 0xFF000000 */

+#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */

+#define DFSDM_FLTISR_CKABF_Pos          (16U)

+#define DFSDM_FLTISR_CKABF_Msk          (0xFFUL << DFSDM_FLTISR_CKABF_Pos)     /*!< 0x00FF0000 */

+#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */

+#define DFSDM_FLTISR_RCIP_Pos           (14U)

+#define DFSDM_FLTISR_RCIP_Msk           (0x1UL << DFSDM_FLTISR_RCIP_Pos)       /*!< 0x00004000 */

+#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */

+#define DFSDM_FLTISR_JCIP_Pos           (13U)

+#define DFSDM_FLTISR_JCIP_Msk           (0x1UL << DFSDM_FLTISR_JCIP_Pos)       /*!< 0x00002000 */

+#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */

+#define DFSDM_FLTISR_AWDF_Pos           (4U)

+#define DFSDM_FLTISR_AWDF_Msk           (0x1UL << DFSDM_FLTISR_AWDF_Pos)       /*!< 0x00000010 */

+#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */

+#define DFSDM_FLTISR_ROVRF_Pos          (3U)

+#define DFSDM_FLTISR_ROVRF_Msk          (0x1UL << DFSDM_FLTISR_ROVRF_Pos)      /*!< 0x00000008 */

+#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */

+#define DFSDM_FLTISR_JOVRF_Pos          (2U)

+#define DFSDM_FLTISR_JOVRF_Msk          (0x1UL << DFSDM_FLTISR_JOVRF_Pos)      /*!< 0x00000004 */

+#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */

+#define DFSDM_FLTISR_REOCF_Pos          (1U)

+#define DFSDM_FLTISR_REOCF_Msk          (0x1UL << DFSDM_FLTISR_REOCF_Pos)      /*!< 0x00000002 */

+#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */

+#define DFSDM_FLTISR_JEOCF_Pos          (0U)

+#define DFSDM_FLTISR_JEOCF_Msk          (0x1UL << DFSDM_FLTISR_JEOCF_Pos)      /*!< 0x00000001 */

+#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */

+

+/********************  Bit definition for DFSDM_FLTICR register *******************/

+#define DFSDM_FLTICR_CLRSCDF_Pos        (24U)

+#define DFSDM_FLTICR_CLRSCDF_Msk        (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)   /*!< 0xFF000000 */

+#define DFSDM_FLTICR_CLRSCDF            DFSDM_FLTICR_CLRSCDF_Msk               /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */

+#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)

+#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)  /*!< 0x00FF0000 */

+#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */

+#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)

+#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)   /*!< 0x00000008 */

+#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */

+#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)

+#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)   /*!< 0x00000004 */

+#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */

+

+/*******************  Bit definition for DFSDM_FLTJCHGR register ******************/

+#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)

+#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)    /*!< 0x000000FF */

+#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */

+

+/********************  Bit definition for DFSDM_FLTFCR register *******************/

+#define DFSDM_FLTFCR_FORD_Pos           (29U)

+#define DFSDM_FLTFCR_FORD_Msk           (0x7UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0xE0000000 */

+#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */

+#define DFSDM_FLTFCR_FORD_2             (0x4UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */

+#define DFSDM_FLTFCR_FORD_1             (0x2UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */

+#define DFSDM_FLTFCR_FORD_0             (0x1UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */

+#define DFSDM_FLTFCR_FOSR_Pos           (16U)

+#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)     /*!< 0x03FF0000 */

+#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */

+#define DFSDM_FLTFCR_IOSR_Pos           (0U)

+#define DFSDM_FLTFCR_IOSR_Msk           (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)      /*!< 0x000000FF */

+#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */

+

+/******************  Bit definition for DFSDM_FLTJDATAR register *****************/

+#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)

+#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */

+#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)

+#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */

+#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */

+

+/******************  Bit definition for DFSDM_FLTRDATAR register *****************/

+#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)

+#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */

+#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)

+#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)   /*!< 0x00000010 */

+#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */

+#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)

+#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */

+#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */

+

+/******************  Bit definition for DFSDM_FLTAWHTR register ******************/

+#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)

+#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */

+#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)

+#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)    /*!< 0x0000000F */

+#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */

+

+/******************  Bit definition for DFSDM_FLTAWLTR register ******************/

+#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)

+#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWHT[23:0] Analog watchdog low threshold */

+#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)

+#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)    /*!< 0x0000000F */

+#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */

+

+/******************  Bit definition for DFSDM_FLTAWSR register ******************/

+#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)

+#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)    /*!< 0x0000FF00 */

+#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */

+#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)

+#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)    /*!< 0x000000FF */

+#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */

+

+/******************  Bit definition for DFSDM_FLTAWCFR) register *****************/

+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)

+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */

+#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */

+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)

+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */

+#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */

+

+/******************  Bit definition for DFSDM_FLTEXMAX register ******************/

+#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)

+#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */

+#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)

+#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)  /*!< 0x00000007 */

+#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */

+

+/******************  Bit definition for DFSDM_FLTEXMIN register ******************/

+#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)

+#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */

+#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)

+#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)  /*!< 0x00000007 */

+#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */

+

+/******************  Bit definition for DFSDM_FLTCNVTIMR register ******************/

+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)

+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */

+#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           BDMA Controller                                  */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for BDMA_ISR register  ********************/

+#define BDMA_ISR_GIF0_Pos       (0U)

+#define BDMA_ISR_GIF0_Msk       (0x1UL << BDMA_ISR_GIF0_Pos)                   /*!< 0x00000001 */

+#define BDMA_ISR_GIF0           BDMA_ISR_GIF0_Msk                              /*!< Channel 0 Global interrupt flag */

+#define BDMA_ISR_TCIF0_Pos      (1U)

+#define BDMA_ISR_TCIF0_Msk      (0x1UL << BDMA_ISR_TCIF0_Pos)                  /*!< 0x00000002 */

+#define BDMA_ISR_TCIF0          BDMA_ISR_TCIF0_Msk                             /*!< Channel 0 Transfer Complete flag */

+#define BDMA_ISR_HTIF0_Pos      (2U)

+#define BDMA_ISR_HTIF0_Msk      (0x1UL << BDMA_ISR_HTIF0_Pos)                  /*!< 0x00000004 */

+#define BDMA_ISR_HTIF0          BDMA_ISR_HTIF0_Msk                             /*!< Channel 0 Half Transfer flag */

+#define BDMA_ISR_TEIF0_Pos      (3U)

+#define BDMA_ISR_TEIF0_Msk      (0x1UL << BDMA_ISR_TEIF0_Pos)                  /*!< 0x00000008 */

+#define BDMA_ISR_TEIF0          BDMA_ISR_TEIF0_Msk                             /*!< Channel 0 Transfer Error flag */

+#define BDMA_ISR_GIF1_Pos       (4U)

+#define BDMA_ISR_GIF1_Msk       (0x1UL << BDMA_ISR_GIF1_Pos)                   /*!< 0x00000010 */

+#define BDMA_ISR_GIF1           BDMA_ISR_GIF1_Msk                              /*!< Channel 1 Global interrupt flag */

+#define BDMA_ISR_TCIF1_Pos      (5U)

+#define BDMA_ISR_TCIF1_Msk      (0x1UL << BDMA_ISR_TCIF1_Pos)                  /*!< 0x00000020 */

+#define BDMA_ISR_TCIF1          BDMA_ISR_TCIF1_Msk                             /*!< Channel 1 Transfer Complete flag */

+#define BDMA_ISR_HTIF1_Pos      (6U)

+#define BDMA_ISR_HTIF1_Msk      (0x1UL << BDMA_ISR_HTIF1_Pos)                  /*!< 0x00000040 */

+#define BDMA_ISR_HTIF1          BDMA_ISR_HTIF1_Msk                             /*!< Channel 1 Half Transfer flag */

+#define BDMA_ISR_TEIF1_Pos      (7U)

+#define BDMA_ISR_TEIF1_Msk      (0x1UL << BDMA_ISR_TEIF1_Pos)                  /*!< 0x00000080 */

+#define BDMA_ISR_TEIF1          BDMA_ISR_TEIF1_Msk                             /*!< Channel 1 Transfer Error flag */

+#define BDMA_ISR_GIF2_Pos       (8U)

+#define BDMA_ISR_GIF2_Msk       (0x1UL << BDMA_ISR_GIF2_Pos)                   /*!< 0x00000100 */

+#define BDMA_ISR_GIF2           BDMA_ISR_GIF2_Msk                              /*!< Channel 2 Global interrupt flag */

+#define BDMA_ISR_TCIF2_Pos      (9U)

+#define BDMA_ISR_TCIF2_Msk      (0x1UL << BDMA_ISR_TCIF2_Pos)                  /*!< 0x00000200 */

+#define BDMA_ISR_TCIF2          BDMA_ISR_TCIF2_Msk                             /*!< Channel 2 Transfer Complete flag */

+#define BDMA_ISR_HTIF2_Pos      (10U)

+#define BDMA_ISR_HTIF2_Msk      (0x1UL << BDMA_ISR_HTIF2_Pos)                  /*!< 0x00000400 */

+#define BDMA_ISR_HTIF2          BDMA_ISR_HTIF2_Msk                             /*!< Channel 2 Half Transfer flag */

+#define BDMA_ISR_TEIF2_Pos      (11U)

+#define BDMA_ISR_TEIF2_Msk      (0x1UL << BDMA_ISR_TEIF2_Pos)                  /*!< 0x00000800 */

+#define BDMA_ISR_TEIF2          BDMA_ISR_TEIF2_Msk                             /*!< Channel 2 Transfer Error flag */

+#define BDMA_ISR_GIF3_Pos       (12U)

+#define BDMA_ISR_GIF3_Msk       (0x1UL << BDMA_ISR_GIF3_Pos)                   /*!< 0x00001000 */

+#define BDMA_ISR_GIF3           BDMA_ISR_GIF3_Msk                              /*!< Channel 3 Global interrupt flag */

+#define BDMA_ISR_TCIF3_Pos      (13U)

+#define BDMA_ISR_TCIF3_Msk      (0x1UL << BDMA_ISR_TCIF3_Pos)                  /*!< 0x00002000 */

+#define BDMA_ISR_TCIF3          BDMA_ISR_TCIF3_Msk                             /*!< Channel 3 Transfer Complete flag */

+#define BDMA_ISR_HTIF3_Pos      (14U)

+#define BDMA_ISR_HTIF3_Msk      (0x1UL << BDMA_ISR_HTIF3_Pos)                  /*!< 0x00004000 */

+#define BDMA_ISR_HTIF3          BDMA_ISR_HTIF3_Msk                             /*!< Channel 3 Half Transfer flag */

+#define BDMA_ISR_TEIF3_Pos      (15U)

+#define BDMA_ISR_TEIF3_Msk      (0x1UL << BDMA_ISR_TEIF3_Pos)                  /*!< 0x00008000 */

+#define BDMA_ISR_TEIF3          BDMA_ISR_TEIF3_Msk                             /*!< Channel 3 Transfer Error flag */

+#define BDMA_ISR_GIF4_Pos       (16U)

+#define BDMA_ISR_GIF4_Msk       (0x1UL << BDMA_ISR_GIF4_Pos)                   /*!< 0x00010000 */

+#define BDMA_ISR_GIF4           BDMA_ISR_GIF4_Msk                              /*!< Channel 4 Global interrupt flag */

+#define BDMA_ISR_TCIF4_Pos      (17U)

+#define BDMA_ISR_TCIF4_Msk      (0x1UL << BDMA_ISR_TCIF4_Pos)                  /*!< 0x00020000 */

+#define BDMA_ISR_TCIF4          BDMA_ISR_TCIF4_Msk                             /*!< Channel 4 Transfer Complete flag */

+#define BDMA_ISR_HTIF4_Pos      (18U)

+#define BDMA_ISR_HTIF4_Msk      (0x1UL << BDMA_ISR_HTIF4_Pos)                  /*!< 0x00040000 */

+#define BDMA_ISR_HTIF4          BDMA_ISR_HTIF4_Msk                             /*!< Channel 4 Half Transfer flag */

+#define BDMA_ISR_TEIF4_Pos      (19U)

+#define BDMA_ISR_TEIF4_Msk      (0x1UL << BDMA_ISR_TEIF4_Pos)                  /*!< 0x00080000 */

+#define BDMA_ISR_TEIF4          BDMA_ISR_TEIF4_Msk                             /*!< Channel 4 Transfer Error flag */

+#define BDMA_ISR_GIF5_Pos       (20U)

+#define BDMA_ISR_GIF5_Msk       (0x1UL << BDMA_ISR_GIF5_Pos)                   /*!< 0x00100000 */

+#define BDMA_ISR_GIF5           BDMA_ISR_GIF5_Msk                              /*!< Channel 5 Global interrupt flag */

+#define BDMA_ISR_TCIF5_Pos      (21U)

+#define BDMA_ISR_TCIF5_Msk      (0x1UL << BDMA_ISR_TCIF5_Pos)                  /*!< 0x00200000 */

+#define BDMA_ISR_TCIF5          BDMA_ISR_TCIF5_Msk                             /*!< Channel 5 Transfer Complete flag */

+#define BDMA_ISR_HTIF5_Pos      (22U)

+#define BDMA_ISR_HTIF5_Msk      (0x1UL << BDMA_ISR_HTIF5_Pos)                  /*!< 0x00400000 */

+#define BDMA_ISR_HTIF5          BDMA_ISR_HTIF5_Msk                             /*!< Channel 5 Half Transfer flag */

+#define BDMA_ISR_TEIF5_Pos      (23U)

+#define BDMA_ISR_TEIF5_Msk      (0x1UL << BDMA_ISR_TEIF5_Pos)                  /*!< 0x00800000 */

+#define BDMA_ISR_TEIF5          BDMA_ISR_TEIF5_Msk                             /*!< Channel 5 Transfer Error flag */

+#define BDMA_ISR_GIF6_Pos       (24U)

+#define BDMA_ISR_GIF6_Msk       (0x1UL << BDMA_ISR_GIF6_Pos)                   /*!< 0x01000000 */

+#define BDMA_ISR_GIF6           BDMA_ISR_GIF6_Msk                              /*!< Channel 6 Global interrupt flag */

+#define BDMA_ISR_TCIF6_Pos      (25U)

+#define BDMA_ISR_TCIF6_Msk      (0x1UL << BDMA_ISR_TCIF6_Pos)                  /*!< 0x02000000 */

+#define BDMA_ISR_TCIF6          BDMA_ISR_TCIF6_Msk                             /*!< Channel 6 Transfer Complete flag */

+#define BDMA_ISR_HTIF6_Pos      (26U)

+#define BDMA_ISR_HTIF6_Msk      (0x1UL << BDMA_ISR_HTIF6_Pos)                  /*!< 0x04000000 */

+#define BDMA_ISR_HTIF6          BDMA_ISR_HTIF6_Msk                             /*!< Channel 6 Half Transfer flag */

+#define BDMA_ISR_TEIF6_Pos      (27U)

+#define BDMA_ISR_TEIF6_Msk      (0x1UL << BDMA_ISR_TEIF6_Pos)                  /*!< 0x08000000 */

+#define BDMA_ISR_TEIF6          BDMA_ISR_TEIF6_Msk                             /*!< Channel 6 Transfer Error flag */

+#define BDMA_ISR_GIF7_Pos       (28U)

+#define BDMA_ISR_GIF7_Msk       (0x1UL << BDMA_ISR_GIF7_Pos)                   /*!< 0x10000000 */

+#define BDMA_ISR_GIF7           BDMA_ISR_GIF7_Msk                              /*!< Channel 7 Global interrupt flag */

+#define BDMA_ISR_TCIF7_Pos      (29U)

+#define BDMA_ISR_TCIF7_Msk      (0x1UL << BDMA_ISR_TCIF7_Pos)                  /*!< 0x20000000 */

+#define BDMA_ISR_TCIF7          BDMA_ISR_TCIF7_Msk                             /*!< Channel 7 Transfer Complete flag */

+#define BDMA_ISR_HTIF7_Pos      (30U)

+#define BDMA_ISR_HTIF7_Msk      (0x1UL << BDMA_ISR_HTIF7_Pos)                  /*!< 0x40000000 */

+#define BDMA_ISR_HTIF7          BDMA_ISR_HTIF7_Msk                             /*!< Channel 7 Half Transfer flag */

+#define BDMA_ISR_TEIF7_Pos      (31U)

+#define BDMA_ISR_TEIF7_Msk      (0x1UL << BDMA_ISR_TEIF7_Pos)                  /*!< 0x80000000 */

+#define BDMA_ISR_TEIF7          BDMA_ISR_TEIF7_Msk                             /*!< Channel 7 Transfer Error flag */

+

+/*******************  Bit definition for BDMA_IFCR register  *******************/

+#define BDMA_IFCR_CGIF0_Pos     (0U)

+#define BDMA_IFCR_CGIF0_Msk     (0x1UL << BDMA_IFCR_CGIF0_Pos)                 /*!< 0x00000001 */

+#define BDMA_IFCR_CGIF0         BDMA_IFCR_CGIF0_Msk                            /*!< Channel 0 Global interrupt clearr */

+#define BDMA_IFCR_CTCIF0_Pos    (1U)

+#define BDMA_IFCR_CTCIF0_Msk    (0x1UL << BDMA_IFCR_CTCIF0_Pos)                /*!< 0x00000002 */

+#define BDMA_IFCR_CTCIF0        BDMA_IFCR_CTCIF0_Msk                           /*!< Channel 0 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF0_Pos    (2U)

+#define BDMA_IFCR_CHTIF0_Msk    (0x1UL << BDMA_IFCR_CHTIF0_Pos)                /*!< 0x00000004 */

+#define BDMA_IFCR_CHTIF0        BDMA_IFCR_CHTIF0_Msk                           /*!< Channel 0 Half Transfer clear */

+#define BDMA_IFCR_CTEIF0_Pos    (3U)

+#define BDMA_IFCR_CTEIF0_Msk    (0x1UL << BDMA_IFCR_CTEIF0_Pos)                /*!< 0x00000008 */

+#define BDMA_IFCR_CTEIF0        BDMA_IFCR_CTEIF0_Msk                           /*!< Channel 0 Transfer Error clear */

+#define BDMA_IFCR_CGIF1_Pos     (4U)

+#define BDMA_IFCR_CGIF1_Msk     (0x1UL << BDMA_IFCR_CGIF1_Pos)                 /*!< 0x00000010 */

+#define BDMA_IFCR_CGIF1         BDMA_IFCR_CGIF1_Msk                            /*!< Channel 1 Global interrupt clear */

+#define BDMA_IFCR_CTCIF1_Pos    (5U)

+#define BDMA_IFCR_CTCIF1_Msk    (0x1UL << BDMA_IFCR_CTCIF1_Pos)                /*!< 0x00000020 */

+#define BDMA_IFCR_CTCIF1        BDMA_IFCR_CTCIF1_Msk                           /*!< Channel 1 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF1_Pos    (6U)

+#define BDMA_IFCR_CHTIF1_Msk    (0x1UL << BDMA_IFCR_CHTIF1_Pos)                /*!< 0x00000040 */

+#define BDMA_IFCR_CHTIF1        BDMA_IFCR_CHTIF1_Msk                           /*!< Channel 1 Half Transfer clear */

+#define BDMA_IFCR_CTEIF1_Pos    (7U)

+#define BDMA_IFCR_CTEIF1_Msk    (0x1UL << BDMA_IFCR_CTEIF1_Pos)                /*!< 0x00000080 */

+#define BDMA_IFCR_CTEIF1        BDMA_IFCR_CTEIF1_Msk                           /*!< Channel 1 Transfer Error clear */

+#define BDMA_IFCR_CGIF2_Pos     (8U)

+#define BDMA_IFCR_CGIF2_Msk     (0x1UL << BDMA_IFCR_CGIF2_Pos)                 /*!< 0x00000100 */

+#define BDMA_IFCR_CGIF2         BDMA_IFCR_CGIF2_Msk                            /*!< Channel 2 Global interrupt clear */

+#define BDMA_IFCR_CTCIF2_Pos    (9U)

+#define BDMA_IFCR_CTCIF2_Msk    (0x1UL << BDMA_IFCR_CTCIF2_Pos)                /*!< 0x00000200 */

+#define BDMA_IFCR_CTCIF2        BDMA_IFCR_CTCIF2_Msk                           /*!< Channel 2 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF2_Pos    (10U)

+#define BDMA_IFCR_CHTIF2_Msk    (0x1UL << BDMA_IFCR_CHTIF2_Pos)                /*!< 0x00000400 */

+#define BDMA_IFCR_CHTIF2        BDMA_IFCR_CHTIF2_Msk                           /*!< Channel 2 Half Transfer clear */

+#define BDMA_IFCR_CTEIF2_Pos    (11U)

+#define BDMA_IFCR_CTEIF2_Msk    (0x1UL << BDMA_IFCR_CTEIF2_Pos)                /*!< 0x00000800 */

+#define BDMA_IFCR_CTEIF2        BDMA_IFCR_CTEIF2_Msk                           /*!< Channel 2 Transfer Error clear */

+#define BDMA_IFCR_CGIF3_Pos     (12U)

+#define BDMA_IFCR_CGIF3_Msk     (0x1UL << BDMA_IFCR_CGIF3_Pos)                 /*!< 0x00001000 */

+#define BDMA_IFCR_CGIF3         BDMA_IFCR_CGIF3_Msk                            /*!< Channel 3 Global interrupt clear */

+#define BDMA_IFCR_CTCIF3_Pos    (13U)

+#define BDMA_IFCR_CTCIF3_Msk    (0x1UL << BDMA_IFCR_CTCIF3_Pos)                /*!< 0x00002000 */

+#define BDMA_IFCR_CTCIF3        BDMA_IFCR_CTCIF3_Msk                           /*!< Channel 3 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF3_Pos    (14U)

+#define BDMA_IFCR_CHTIF3_Msk    (0x1UL << BDMA_IFCR_CHTIF3_Pos)                /*!< 0x00004000 */

+#define BDMA_IFCR_CHTIF3        BDMA_IFCR_CHTIF3_Msk                           /*!< Channel 3 Half Transfer clear */

+#define BDMA_IFCR_CTEIF3_Pos    (15U)

+#define BDMA_IFCR_CTEIF3_Msk    (0x1UL << BDMA_IFCR_CTEIF3_Pos)                /*!< 0x00008000 */

+#define BDMA_IFCR_CTEIF3        BDMA_IFCR_CTEIF3_Msk                           /*!< Channel 3 Transfer Error clear */

+#define BDMA_IFCR_CGIF4_Pos     (16U)

+#define BDMA_IFCR_CGIF4_Msk     (0x1UL << BDMA_IFCR_CGIF4_Pos)                 /*!< 0x00010000 */

+#define BDMA_IFCR_CGIF4         BDMA_IFCR_CGIF4_Msk                            /*!< Channel 4 Global interrupt clear */

+#define BDMA_IFCR_CTCIF4_Pos    (17U)

+#define BDMA_IFCR_CTCIF4_Msk    (0x1UL << BDMA_IFCR_CTCIF4_Pos)                /*!< 0x00020000 */

+#define BDMA_IFCR_CTCIF4        BDMA_IFCR_CTCIF4_Msk                           /*!< Channel 4 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF4_Pos    (18U)

+#define BDMA_IFCR_CHTIF4_Msk    (0x1UL << BDMA_IFCR_CHTIF4_Pos)                /*!< 0x00040000 */

+#define BDMA_IFCR_CHTIF4        BDMA_IFCR_CHTIF4_Msk                           /*!< Channel 4 Half Transfer clear */

+#define BDMA_IFCR_CTEIF4_Pos    (19U)

+#define BDMA_IFCR_CTEIF4_Msk    (0x1UL << BDMA_IFCR_CTEIF4_Pos)                /*!< 0x00080000 */

+#define BDMA_IFCR_CTEIF4        BDMA_IFCR_CTEIF4_Msk                           /*!< Channel 4 Transfer Error clear */

+#define BDMA_IFCR_CGIF5_Pos     (20U)

+#define BDMA_IFCR_CGIF5_Msk     (0x1UL << BDMA_IFCR_CGIF5_Pos)                 /*!< 0x00100000 */

+#define BDMA_IFCR_CGIF5         BDMA_IFCR_CGIF5_Msk                            /*!< Channel 5 Global interrupt clear */

+#define BDMA_IFCR_CTCIF5_Pos    (21U)

+#define BDMA_IFCR_CTCIF5_Msk    (0x1UL << BDMA_IFCR_CTCIF5_Pos)                /*!< 0x00200000 */

+#define BDMA_IFCR_CTCIF5        BDMA_IFCR_CTCIF5_Msk                           /*!< Channel 5 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF5_Pos    (22U)

+#define BDMA_IFCR_CHTIF5_Msk    (0x1UL << BDMA_IFCR_CHTIF5_Pos)                /*!< 0x00400000 */

+#define BDMA_IFCR_CHTIF5        BDMA_IFCR_CHTIF5_Msk                           /*!< Channel 5 Half Transfer clear */

+#define BDMA_IFCR_CTEIF5_Pos    (23U)

+#define BDMA_IFCR_CTEIF5_Msk    (0x1UL << BDMA_IFCR_CTEIF5_Pos)                /*!< 0x00800000 */

+#define BDMA_IFCR_CTEIF5        BDMA_IFCR_CTEIF5_Msk                           /*!< Channel 5 Transfer Error clear */

+#define BDMA_IFCR_CGIF6_Pos     (24U)

+#define BDMA_IFCR_CGIF6_Msk     (0x1UL << BDMA_IFCR_CGIF6_Pos)                 /*!< 0x01000000 */

+#define BDMA_IFCR_CGIF6         BDMA_IFCR_CGIF6_Msk                            /*!< Channel 6 Global interrupt clear */

+#define BDMA_IFCR_CTCIF6_Pos    (25U)

+#define BDMA_IFCR_CTCIF6_Msk    (0x1UL << BDMA_IFCR_CTCIF6_Pos)                /*!< 0x02000000 */

+#define BDMA_IFCR_CTCIF6        BDMA_IFCR_CTCIF6_Msk                           /*!< Channel 6 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF6_Pos    (26U)

+#define BDMA_IFCR_CHTIF6_Msk    (0x1UL << BDMA_IFCR_CHTIF6_Pos)                /*!< 0x04000000 */

+#define BDMA_IFCR_CHTIF6        BDMA_IFCR_CHTIF6_Msk                           /*!< Channel 6 Half Transfer clear */

+#define BDMA_IFCR_CTEIF6_Pos    (27U)

+#define BDMA_IFCR_CTEIF6_Msk    (0x1UL << BDMA_IFCR_CTEIF6_Pos)                /*!< 0x08000000 */

+#define BDMA_IFCR_CTEIF6        BDMA_IFCR_CTEIF6_Msk                           /*!< Channel 6 Transfer Error clear */

+#define BDMA_IFCR_CGIF7_Pos     (28U)

+#define BDMA_IFCR_CGIF7_Msk     (0x1UL << BDMA_IFCR_CGIF7_Pos)                 /*!< 0x10000000 */

+#define BDMA_IFCR_CGIF7         BDMA_IFCR_CGIF7_Msk                            /*!< Channel 7 Global interrupt clear */

+#define BDMA_IFCR_CTCIF7_Pos    (29U)

+#define BDMA_IFCR_CTCIF7_Msk    (0x1UL << BDMA_IFCR_CTCIF7_Pos)                /*!< 0x20000000 */

+#define BDMA_IFCR_CTCIF7        BDMA_IFCR_CTCIF7_Msk                           /*!< Channel 7 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF7_Pos    (30U)

+#define BDMA_IFCR_CHTIF7_Msk    (0x1UL << BDMA_IFCR_CHTIF7_Pos)                /*!< 0x40000000 */

+#define BDMA_IFCR_CHTIF7        BDMA_IFCR_CHTIF7_Msk                           /*!< Channel 7 Half Transfer clear */

+#define BDMA_IFCR_CTEIF7_Pos    (31U)

+#define BDMA_IFCR_CTEIF7_Msk    (0x1UL << BDMA_IFCR_CTEIF7_Pos)                /*!< 0x80000000 */

+#define BDMA_IFCR_CTEIF7        BDMA_IFCR_CTEIF7_Msk                           /*!< Channel 7 Transfer Error clear */

+

+/*******************  Bit definition for BDMA_CCR register  ********************/

+#define BDMA_CCR_EN_Pos         (0U)

+#define BDMA_CCR_EN_Msk         (0x1UL << BDMA_CCR_EN_Pos)                     /*!< 0x00000001 */

+#define BDMA_CCR_EN             BDMA_CCR_EN_Msk                                /*!< Channel enable                      */

+#define BDMA_CCR_TCIE_Pos       (1U)

+#define BDMA_CCR_TCIE_Msk       (0x1UL << BDMA_CCR_TCIE_Pos)                   /*!< 0x00000002 */

+#define BDMA_CCR_TCIE           BDMA_CCR_TCIE_Msk                              /*!< Transfer complete interrupt enable  */

+#define BDMA_CCR_HTIE_Pos       (2U)

+#define BDMA_CCR_HTIE_Msk       (0x1UL << BDMA_CCR_HTIE_Pos)                   /*!< 0x00000004 */

+#define BDMA_CCR_HTIE           BDMA_CCR_HTIE_Msk                              /*!< Half Transfer interrupt enable      */

+#define BDMA_CCR_TEIE_Pos       (3U)

+#define BDMA_CCR_TEIE_Msk       (0x1UL << BDMA_CCR_TEIE_Pos)                   /*!< 0x00000008 */

+#define BDMA_CCR_TEIE           BDMA_CCR_TEIE_Msk                              /*!< Transfer error interrupt enable     */

+#define BDMA_CCR_DIR_Pos        (4U)

+#define BDMA_CCR_DIR_Msk        (0x1UL << BDMA_CCR_DIR_Pos)                    /*!< 0x00000010 */

+#define BDMA_CCR_DIR            BDMA_CCR_DIR_Msk                               /*!< Data transfer direction             */

+#define BDMA_CCR_CIRC_Pos       (5U)

+#define BDMA_CCR_CIRC_Msk       (0x1UL << BDMA_CCR_CIRC_Pos)                   /*!< 0x00000020 */

+#define BDMA_CCR_CIRC           BDMA_CCR_CIRC_Msk                              /*!< Circular mode                       */

+#define BDMA_CCR_PINC_Pos       (6U)

+#define BDMA_CCR_PINC_Msk       (0x1UL << BDMA_CCR_PINC_Pos)                   /*!< 0x00000040 */

+#define BDMA_CCR_PINC           BDMA_CCR_PINC_Msk                              /*!< Peripheral increment mode           */

+#define BDMA_CCR_MINC_Pos       (7U)

+#define BDMA_CCR_MINC_Msk       (0x1UL << BDMA_CCR_MINC_Pos)                   /*!< 0x00000080 */

+#define BDMA_CCR_MINC           BDMA_CCR_MINC_Msk                              /*!< Memory increment mode               */

+

+#define BDMA_CCR_PSIZE_Pos      (8U)

+#define BDMA_CCR_PSIZE_Msk      (0x3UL << BDMA_CCR_PSIZE_Pos)                  /*!< 0x00000300 */

+#define BDMA_CCR_PSIZE          BDMA_CCR_PSIZE_Msk                             /*!< PSIZE[1:0] bits (Peripheral size)   */

+#define BDMA_CCR_PSIZE_0        (0x1UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000100 */

+#define BDMA_CCR_PSIZE_1        (0x2UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000200 */

+

+#define BDMA_CCR_MSIZE_Pos      (10U)

+#define BDMA_CCR_MSIZE_Msk      (0x3UL << BDMA_CCR_MSIZE_Pos)                  /*!< 0x00000C00 */

+#define BDMA_CCR_MSIZE          BDMA_CCR_MSIZE_Msk                             /*!< MSIZE[1:0] bits (Memory size)       */

+#define BDMA_CCR_MSIZE_0        (0x1UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000400 */

+#define BDMA_CCR_MSIZE_1        (0x2UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000800 */

+

+#define BDMA_CCR_PL_Pos         (12U)

+#define BDMA_CCR_PL_Msk         (0x3UL << BDMA_CCR_PL_Pos)                     /*!< 0x00003000 */

+#define BDMA_CCR_PL             BDMA_CCR_PL_Msk                                /*!< PL[1:0] bits(Channel Priority level)*/

+#define BDMA_CCR_PL_0           (0x1UL << BDMA_CCR_PL_Pos)                      /*!< 0x00001000 */

+#define BDMA_CCR_PL_1           (0x2UL << BDMA_CCR_PL_Pos)                      /*!< 0x00002000 */

+

+#define BDMA_CCR_MEM2MEM_Pos    (14U)

+#define BDMA_CCR_MEM2MEM_Msk    (0x1UL << BDMA_CCR_MEM2MEM_Pos)                /*!< 0x00004000 */

+#define BDMA_CCR_MEM2MEM        BDMA_CCR_MEM2MEM_Msk                           /*!< Memory to memory mode               */

+#define BDMA_CCR_DBM_Pos        (15U)

+#define BDMA_CCR_DBM_Msk        (0x1UL << BDMA_CCR_DBM_Pos)                    /*!< 0x0000A000 */

+#define BDMA_CCR_DBM            BDMA_CCR_DBM_Msk                               /*!< Memory to memory mode               */

+#define BDMA_CCR_CT_Pos         (16U)

+#define BDMA_CCR_CT_Msk         (0x1UL << BDMA_CCR_CT_Pos)                     /*!< 0x00010000 */

+#define BDMA_CCR_CT             BDMA_CCR_CT_Msk                                /*!< Memory to memory mode               */

+

+/******************  Bit definition for BDMA_CNDTR register  *******************/

+#define BDMA_CNDTR_NDT_Pos      (0U)

+#define BDMA_CNDTR_NDT_Msk      (0xFFFFUL << BDMA_CNDTR_NDT_Pos)               /*!< 0x0000FFFF */

+#define BDMA_CNDTR_NDT          BDMA_CNDTR_NDT_Msk                             /*!< Number of data to Transfer          */

+

+/******************  Bit definition for BDMA_CPAR register  ********************/

+#define BDMA_CPAR_PA_Pos        (0U)

+#define BDMA_CPAR_PA_Msk        (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CPAR_PA            BDMA_CPAR_PA_Msk                               /*!< Peripheral Address                  */

+

+/******************  Bit definition for BDMA_CM0AR register  ********************/

+#define BDMA_CM0AR_MA_Pos        (0U)

+#define BDMA_CM0AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CM0AR_MA            BDMA_CM0AR_MA_Msk                               /*!< Memory Address                      */

+

+/******************  Bit definition for BDMA_CM1AR register  ********************/

+#define BDMA_CM1AR_MA_Pos        (0U)

+#define BDMA_CM1AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CM1AR_MA            BDMA_CM1AR_MA_Msk                               /*!< Memory Address                      */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             DMA Controller                                 */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DMA_SxCR register  *****************/

+#define DMA_SxCR_MBURST_Pos      (23U)

+#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                /*!< 0x01800000 */

+#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk                           /*!< Memory burst transfer configuration */

+#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */

+#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */

+#define DMA_SxCR_PBURST_Pos      (21U)

+#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                /*!< 0x00600000 */

+#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk                           /*!< Peripheral burst transfer configuration */

+#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */

+#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */

+#define DMA_SxCR_TRBUFF_Pos      (20U)

+#define DMA_SxCR_TRBUFF_Msk      (0x1UL << DMA_SxCR_TRBUFF_Pos)                 /*!< 0x00100000 */

+#define DMA_SxCR_TRBUFF          DMA_SxCR_TRBUFF_Msk                            /*!< bufferable transfers enabled/disable */

+#define DMA_SxCR_CT_Pos          (19U)

+#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                    /*!< 0x00080000 */

+#define DMA_SxCR_CT              DMA_SxCR_CT_Msk                               /*!< Current target (only in double buffer mode) */

+#define DMA_SxCR_DBM_Pos         (18U)

+#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                   /*!< 0x00040000 */

+#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk                              /*!< Double buffer mode */

+#define DMA_SxCR_PL_Pos          (16U)

+#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                    /*!< 0x00030000 */

+#define DMA_SxCR_PL              DMA_SxCR_PL_Msk                               /*!< Priority level */

+#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */

+#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */

+#define DMA_SxCR_PINCOS_Pos      (15U)

+#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                /*!< 0x00008000 */

+#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk                           /*!< Peripheral increment offset size */

+#define DMA_SxCR_MSIZE_Pos       (13U)

+#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                 /*!< 0x00006000 */

+#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk                            /*!< Memory data size */

+#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */

+#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */

+#define DMA_SxCR_PSIZE_Pos       (11U)

+#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                 /*!< 0x00001800 */

+#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk                            /*< Peripheral data size */

+#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */

+#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */

+#define DMA_SxCR_MINC_Pos        (10U)

+#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                  /*!< 0x00000400 */

+#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk                             /*!< Memory increment mode */

+#define DMA_SxCR_PINC_Pos        (9U)

+#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                  /*!< 0x00000200 */

+#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk                             /*!< Peripheral increment mode */

+#define DMA_SxCR_CIRC_Pos        (8U)

+#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                  /*!< 0x00000100 */

+#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk                             /*!< Circular mode */

+#define DMA_SxCR_DIR_Pos         (6U)

+#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                   /*!< 0x000000C0 */

+#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk                              /*!< Data transfer direction */

+#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */

+#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */

+#define DMA_SxCR_PFCTRL_Pos      (5U)

+#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                /*!< 0x00000020 */

+#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk                           /*!< Peripheral flow controller */

+#define DMA_SxCR_TCIE_Pos        (4U)

+#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                  /*!< 0x00000010 */

+#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk                             /*!< Transfer complete interrupt enable */

+#define DMA_SxCR_HTIE_Pos        (3U)

+#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                  /*!< 0x00000008 */

+#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk                             /*!< Half transfer interrupt enable */

+#define DMA_SxCR_TEIE_Pos        (2U)

+#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                  /*!< 0x00000004 */

+#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk                             /*!< Transfer error interrupt enable */

+#define DMA_SxCR_DMEIE_Pos       (1U)

+#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                 /*!< 0x00000002 */

+#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk                            /*!< Direct mode error interrupt enable */

+#define DMA_SxCR_EN_Pos          (0U)

+#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                    /*!< 0x00000001 */

+#define DMA_SxCR_EN              DMA_SxCR_EN_Msk                               /*!< Stream enable / flag stream ready when read low */

+

+/********************  Bits definition for DMA_SxCNDTR register  **************/

+#define DMA_SxNDT_Pos            (0U)

+#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                   /*!< 0x0000FFFF */

+#define DMA_SxNDT                DMA_SxNDT_Msk                                 /*!< Number of data items to transfer */

+#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */

+#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */

+#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */

+#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */

+#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */

+#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */

+#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */

+#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */

+#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */

+#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */

+#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */

+#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */

+#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */

+#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */

+#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */

+#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */

+

+/********************  Bits definition for DMA_SxFCR register  ****************/

+#define DMA_SxFCR_FEIE_Pos       (7U)

+#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                 /*!< 0x00000080 */

+#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk                            /*!< FIFO error interrupt enable */

+#define DMA_SxFCR_FS_Pos         (3U)

+#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                   /*!< 0x00000038 */

+#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk                              /*!< FIFO status */

+#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */

+#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */

+#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */

+#define DMA_SxFCR_DMDIS_Pos      (2U)

+#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                /*!< 0x00000004 */

+#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk                           /*!< Direct mode disable */

+#define DMA_SxFCR_FTH_Pos        (0U)

+#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                  /*!< 0x00000003 */

+#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk                             /*!< FIFO threshold selection */

+#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */

+#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */

+

+/********************  Bits definition for DMA_LISR register  *****************/

+#define DMA_LISR_TCIF3_Pos       (27U)

+#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                 /*!< 0x08000000 */

+#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk                            /*!<  Stream 3 transfer complete interrupt flag */

+#define DMA_LISR_HTIF3_Pos       (26U)

+#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                 /*!< 0x04000000 */

+#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk                            /*!<  Stream 3 half transfer interrupt flag */

+#define DMA_LISR_TEIF3_Pos       (25U)

+#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                 /*!< 0x02000000 */

+#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk                            /*!<  Stream 3 transfer error interrupt flag */

+#define DMA_LISR_DMEIF3_Pos      (24U)

+#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                /*!< 0x01000000 */

+#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk                           /*!<  Stream 3 direct mode error interrupt flag */

+#define DMA_LISR_FEIF3_Pos       (22U)

+#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                 /*!< 0x00400000 */

+#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk                            /*!<  Stream 3 FIFO error interrupt flag */

+#define DMA_LISR_TCIF2_Pos       (21U)

+#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                 /*!< 0x00200000 */

+#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk                            /*!<  Stream 2 transfer complete interrupt flag */

+#define DMA_LISR_HTIF2_Pos       (20U)

+#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                 /*!< 0x00100000 */

+#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk                            /*!<  Stream 2 half transfer interrupt flag */

+#define DMA_LISR_TEIF2_Pos       (19U)

+#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                 /*!< 0x00080000 */

+#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk                            /*!<  Stream 2 transfer error interrupt flag */

+#define DMA_LISR_DMEIF2_Pos      (18U)

+#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                /*!< 0x00040000 */

+#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk                           /*!<  Stream 2 direct mode error interrupt flag */

+#define DMA_LISR_FEIF2_Pos       (16U)

+#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                 /*!< 0x00010000 */

+#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk                            /*!<  Stream 2 FIFO error interrupt flag */

+#define DMA_LISR_TCIF1_Pos       (11U)

+#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                 /*!< 0x00000800 */

+#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk                            /*!<  Stream 1 transfer complete interrupt flag */

+#define DMA_LISR_HTIF1_Pos       (10U)

+#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                 /*!< 0x00000400 */

+#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk                            /*!<  Stream 1 half transfer interrupt flag */

+#define DMA_LISR_TEIF1_Pos       (9U)

+#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                 /*!< 0x00000200 */

+#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk                            /*!<  Stream 1 transfer error interrupt flag */

+#define DMA_LISR_DMEIF1_Pos      (8U)

+#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                /*!< 0x00000100 */

+#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk                           /*!<  Stream 1 direct mode error interrupt flag */

+#define DMA_LISR_FEIF1_Pos       (6U)

+#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                 /*!< 0x00000040 */

+#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk                            /*!<  Stream 1 FIFO error interrupt flag */

+#define DMA_LISR_TCIF0_Pos       (5U)

+#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                 /*!< 0x00000020 */

+#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk                            /*!<  Stream 0 transfer complete interrupt flag */

+#define DMA_LISR_HTIF0_Pos       (4U)

+#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                 /*!< 0x00000010 */

+#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk                            /*!<  Stream 0 half transfer interrupt flag */

+#define DMA_LISR_TEIF0_Pos       (3U)

+#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                 /*!< 0x00000008 */

+#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk                            /*!<  Stream 0 transfer error interrupt flag */

+#define DMA_LISR_DMEIF0_Pos      (2U)

+#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                /*!< 0x00000004 */

+#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk                           /*!<  Stream 0 direct mode error interrupt flag */

+#define DMA_LISR_FEIF0_Pos       (0U)

+#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                 /*!< 0x00000001 */

+#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk                            /*!<  Stream 0 FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_HISR register  *****************/

+#define DMA_HISR_TCIF7_Pos       (27U)

+#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                 /*!< 0x08000000 */

+#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk                            /*!<  Stream 7 transfer complete interrupt flag */

+#define DMA_HISR_HTIF7_Pos       (26U)

+#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                 /*!< 0x04000000 */

+#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk                            /*!<  Stream 7 half transfer interrupt flag */

+#define DMA_HISR_TEIF7_Pos       (25U)

+#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                 /*!< 0x02000000 */

+#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk                            /*!<  Stream 7 transfer error interrupt flag */

+#define DMA_HISR_DMEIF7_Pos      (24U)

+#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                /*!< 0x01000000 */

+#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk                           /*!<  Stream 7 direct mode error interrupt flag */

+#define DMA_HISR_FEIF7_Pos       (22U)

+#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                 /*!< 0x00400000 */

+#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk                            /*!<  Stream 7 FIFO error interrupt flag */

+#define DMA_HISR_TCIF6_Pos       (21U)

+#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                 /*!< 0x00200000 */

+#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk                            /*!<  Stream 6 transfer complete interrupt flag */

+#define DMA_HISR_HTIF6_Pos       (20U)

+#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                 /*!< 0x00100000 */

+#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk                            /*!<  Stream 6 half transfer interrupt flag */

+#define DMA_HISR_TEIF6_Pos       (19U)

+#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                 /*!< 0x00080000 */

+#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk                            /*!<  Stream 6 transfer error interrupt flag */

+#define DMA_HISR_DMEIF6_Pos      (18U)

+#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                /*!< 0x00040000 */

+#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk                           /*!<  Stream 6 direct mode error interrupt flag */

+#define DMA_HISR_FEIF6_Pos       (16U)

+#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                 /*!< 0x00010000 */

+#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk                            /*!<  Stream 6 FIFO error interrupt flag */

+#define DMA_HISR_TCIF5_Pos       (11U)

+#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                 /*!< 0x00000800 */

+#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk                            /*!<  Stream 5 transfer complete interrupt flag */

+#define DMA_HISR_HTIF5_Pos       (10U)

+#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                 /*!< 0x00000400 */

+#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk                            /*!<  Stream 5 half transfer interrupt flag */

+#define DMA_HISR_TEIF5_Pos       (9U)

+#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                 /*!< 0x00000200 */

+#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk                            /*!<  Stream 5 transfer error interrupt flag */

+#define DMA_HISR_DMEIF5_Pos      (8U)

+#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                /*!< 0x00000100 */

+#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk                           /*!<  Stream 5 direct mode error interrupt flag */

+#define DMA_HISR_FEIF5_Pos       (6U)

+#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                 /*!< 0x00000040 */

+#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk                            /*!<  Stream 5 FIFO error interrupt flag */

+#define DMA_HISR_TCIF4_Pos       (5U)

+#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                 /*!< 0x00000020 */

+#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk                            /*!<  Stream 4 transfer complete interrupt flag */

+#define DMA_HISR_HTIF4_Pos       (4U)

+#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                 /*!< 0x00000010 */

+#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk                            /*!<  Stream 4 half transfer interrupt flag */

+#define DMA_HISR_TEIF4_Pos       (3U)

+#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                 /*!< 0x00000008 */

+#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk                            /*!<  Stream 4 transfer error interrupt flag */

+#define DMA_HISR_DMEIF4_Pos      (2U)

+#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                /*!< 0x00000004 */

+#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk                           /*!<  Stream 4 direct mode error interrupt flag */

+#define DMA_HISR_FEIF4_Pos       (0U)

+#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                 /*!< 0x00000001 */

+#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk                            /*!<  Stream 4 FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_LIFCR register  ****************/

+#define DMA_LIFCR_CTCIF3_Pos     (27U)

+#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)               /*!< 0x08000000 */

+#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk                          /*!<  Stream 3 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF3_Pos     (26U)

+#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)               /*!< 0x04000000 */

+#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk                          /*!<  Stream 3 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF3_Pos     (25U)

+#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)               /*!< 0x02000000 */

+#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk                          /*!<  Stream 3 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF3_Pos    (24U)

+#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)              /*!< 0x01000000 */

+#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk                         /*!<  Stream 3 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF3_Pos     (22U)

+#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)               /*!< 0x00400000 */

+#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk                          /*!<  Stream 3 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF2_Pos     (21U)

+#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)               /*!< 0x00200000 */

+#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk                          /*!<  Stream 2 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF2_Pos     (20U)

+#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)               /*!< 0x00100000 */

+#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk                          /*!<  Stream 2 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF2_Pos     (19U)

+#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)               /*!< 0x00080000 */

+#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk                          /*!<  Stream 2 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF2_Pos    (18U)

+#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)              /*!< 0x00040000 */

+#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk                         /*!<  Stream 2 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF2_Pos     (16U)

+#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)               /*!< 0x00010000 */

+#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk                          /*!<  Stream 2 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF1_Pos     (11U)

+#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)               /*!< 0x00000800 */

+#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk                          /*!<  Stream 1 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF1_Pos     (10U)

+#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)               /*!< 0x00000400 */

+#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk                          /*!<  Stream 1 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF1_Pos     (9U)

+#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)               /*!< 0x00000200 */

+#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk                          /*!<  Stream 1 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF1_Pos    (8U)

+#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)              /*!< 0x00000100 */

+#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk                         /*!<  Stream 1 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF1_Pos     (6U)

+#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)               /*!< 0x00000040 */

+#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk                          /*!<  Stream 1 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF0_Pos     (5U)

+#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)               /*!< 0x00000020 */

+#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk                          /*!<  Stream 0 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF0_Pos     (4U)

+#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)               /*!< 0x00000010 */

+#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk                          /*!<  Stream 0 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF0_Pos     (3U)

+#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)               /*!< 0x00000008 */

+#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk                          /*!<  Stream 0 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF0_Pos    (2U)

+#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)              /*!< 0x00000004 */

+#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk                         /*!<  Stream 0 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF0_Pos     (0U)

+#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)               /*!< 0x00000001 */

+#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk                          /*!<  Stream 0 clear FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_HIFCR  register  ****************/

+#define DMA_HIFCR_CTCIF7_Pos     (27U)

+#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)               /*!< 0x08000000 */

+#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk                          /*!<  Stream 7 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF7_Pos     (26U)

+#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)               /*!< 0x04000000 */

+#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk                          /*!<  Stream 7 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF7_Pos     (25U)

+#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)               /*!< 0x02000000 */

+#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk                          /*!<  Stream 7 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF7_Pos    (24U)

+#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)              /*!< 0x01000000 */

+#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk                         /*!<  Stream 7 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF7_Pos     (22U)

+#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)               /*!< 0x00400000 */

+#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk                          /*!<  Stream 7 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF6_Pos     (21U)

+#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)               /*!< 0x00200000 */

+#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk                          /*!<  Stream 6 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF6_Pos     (20U)

+#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)               /*!< 0x00100000 */

+#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk                          /*!<  Stream 6 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF6_Pos     (19U)

+#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)               /*!< 0x00080000 */

+#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk                          /*!<  Stream 6 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF6_Pos    (18U)

+#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)              /*!< 0x00040000 */

+#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk                         /*!<  Stream 6 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF6_Pos     (16U)

+#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)               /*!< 0x00010000 */

+#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk                          /*!<  Stream 6 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF5_Pos     (11U)

+#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)               /*!< 0x00000800 */

+#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk                          /*!<  Stream 5 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF5_Pos     (10U)

+#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)               /*!< 0x00000400 */

+#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk                          /*!<  Stream 5 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF5_Pos     (9U)

+#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)               /*!< 0x00000200 */

+#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk                          /*!<  Stream 5 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF5_Pos    (8U)

+#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)              /*!< 0x00000100 */

+#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk                         /*!<  Stream 5 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF5_Pos     (6U)

+#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)               /*!< 0x00000040 */

+#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk                          /*!<  Stream 5 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF4_Pos     (5U)

+#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)               /*!< 0x00000020 */

+#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk                          /*!<  Stream 4 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF4_Pos     (4U)

+#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)               /*!< 0x00000010 */

+#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk                          /*!<  Stream 4 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF4_Pos     (3U)

+#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)               /*!< 0x00000008 */

+#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk                          /*!<  Stream 4 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF4_Pos    (2U)

+#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)              /*!< 0x00000004 */

+#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk                         /*!<  Stream 4 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF4_Pos     (0U)

+#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)               /*!< 0x00000001 */

+#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk                          /*!<  Stream 4 clear FIFO error interrupt flag */

+

+/******************  Bit definition for DMA_SxPAR register  ********************/

+#define DMA_SxPAR_PA_Pos         (0U)

+#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)            /*!< 0xFFFFFFFF */

+#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */

+

+/******************  Bit definition for DMA_SxM0AR register  ********************/

+#define DMA_SxM0AR_M0A_Pos       (0U)

+#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)          /*!< 0xFFFFFFFF */

+#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory 0 Address */

+

+/******************  Bit definition for DMA_SxM1AR register  ********************/

+#define DMA_SxM1AR_M1A_Pos       (0U)

+#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)          /*!< 0xFFFFFFFF */

+#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory 1 Address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             DMAMUX Controller                              */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DMAMUX_CxCR register  **************/

+#define DMAMUX_CxCR_DMAREQ_ID_Pos      (0U)

+#define DMAMUX_CxCR_DMAREQ_ID_Msk      (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)   /*!< 0x000000FF */

+#define DMAMUX_CxCR_DMAREQ_ID          DMAMUX_CxCR_DMAREQ_ID_Msk               /*!<  DMA request identification */

+#define DMAMUX_CxCR_DMAREQ_ID_0        (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000001 */

+#define DMAMUX_CxCR_DMAREQ_ID_1        (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000002 */

+#define DMAMUX_CxCR_DMAREQ_ID_2        (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000004 */

+#define DMAMUX_CxCR_DMAREQ_ID_3        (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000008 */

+#define DMAMUX_CxCR_DMAREQ_ID_4        (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000010 */

+#define DMAMUX_CxCR_DMAREQ_ID_5        (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000020 */

+#define DMAMUX_CxCR_DMAREQ_ID_6        (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000040 */

+#define DMAMUX_CxCR_DMAREQ_ID_7        (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000080 */

+#define DMAMUX_CxCR_SOIE_Pos           (8U)

+#define DMAMUX_CxCR_SOIE_Msk           (0x1UL << DMAMUX_CxCR_SOIE_Pos)         /*!< 0x00000100 */

+#define DMAMUX_CxCR_SOIE               DMAMUX_CxCR_SOIE_Msk                    /*!<  Synchronization overrun interrupt enable */

+#define DMAMUX_CxCR_EGE_Pos            (9U)

+#define DMAMUX_CxCR_EGE_Msk            (0x1UL << DMAMUX_CxCR_EGE_Pos)          /*!< 0x00000200 */

+#define DMAMUX_CxCR_EGE                DMAMUX_CxCR_EGE_Msk                     /*!<  Event generation enable */

+#define DMAMUX_CxCR_SE_Pos             (16U)

+#define DMAMUX_CxCR_SE_Msk             (0x1UL << DMAMUX_CxCR_SE_Pos)           /*!< 0x00010000 */

+#define DMAMUX_CxCR_SE                 DMAMUX_CxCR_SE_Msk                      /*!<  Synchronization enable */

+#define DMAMUX_CxCR_SPOL_Pos           (17U)

+#define DMAMUX_CxCR_SPOL_Msk           (0x3UL << DMAMUX_CxCR_SPOL_Pos)         /*!< 0x00060000 */

+#define DMAMUX_CxCR_SPOL               DMAMUX_CxCR_SPOL_Msk                    /*!<  Synchronization polarity */

+#define DMAMUX_CxCR_SPOL_0             (0x1UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00020000 */

+#define DMAMUX_CxCR_SPOL_1             (0x2UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00040000 */

+#define DMAMUX_CxCR_NBREQ_Pos          (19U)

+#define DMAMUX_CxCR_NBREQ_Msk          (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)       /*!< 0x00F80000 */

+#define DMAMUX_CxCR_NBREQ              DMAMUX_CxCR_NBREQ_Msk                   /*!<  Number of DMA requests minus 1 to forward */

+#define DMAMUX_CxCR_NBREQ_0            (0x01UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00080000 */

+#define DMAMUX_CxCR_NBREQ_1            (0x02UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00100000 */

+#define DMAMUX_CxCR_NBREQ_2            (0x04UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00200000 */

+#define DMAMUX_CxCR_NBREQ_3            (0x08UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00400000 */

+#define DMAMUX_CxCR_NBREQ_4            (0x10UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00800000 */

+#define DMAMUX_CxCR_SYNC_ID_Pos        (24U)

+#define DMAMUX_CxCR_SYNC_ID_Msk        (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)     /*!< 0x1F000000 */

+#define DMAMUX_CxCR_SYNC_ID            DMAMUX_CxCR_SYNC_ID_Msk                 /*!<  Synchronization identification */

+#define DMAMUX_CxCR_SYNC_ID_0          (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x01000000 */

+#define DMAMUX_CxCR_SYNC_ID_1          (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x02000000 */

+#define DMAMUX_CxCR_SYNC_ID_2          (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x04000000 */

+#define DMAMUX_CxCR_SYNC_ID_3          (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x08000000 */

+#define DMAMUX_CxCR_SYNC_ID_4          (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x10000000 */

+

+/********************  Bits definition for DMAMUX_CSR register  **************/

+#define DMAMUX_CSR_SOF0_Pos            (0U)

+#define DMAMUX_CSR_SOF0_Msk            (0x1UL << DMAMUX_CSR_SOF0_Pos)          /*!< 0x00000001 */

+#define DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0_Msk                     /*!< Channel 0 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF1_Pos            (1U)

+#define DMAMUX_CSR_SOF1_Msk            (0x1UL << DMAMUX_CSR_SOF1_Pos)          /*!< 0x00000002 */

+#define DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1_Msk                     /*!< Channel 1 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF2_Pos            (2U)

+#define DMAMUX_CSR_SOF2_Msk            (0x1UL << DMAMUX_CSR_SOF2_Pos)          /*!< 0x00000004 */

+#define DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2_Msk                     /*!< Channel 2 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF3_Pos            (3U)

+#define DMAMUX_CSR_SOF3_Msk            (0x1UL << DMAMUX_CSR_SOF3_Pos)          /*!< 0x00000008 */

+#define DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3_Msk                     /*!< Channel 3 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF4_Pos            (4U)

+#define DMAMUX_CSR_SOF4_Msk            (0x1UL << DMAMUX_CSR_SOF4_Pos)          /*!< 0x00000010 */

+#define DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4_Msk                     /*!< Channel 4 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF5_Pos            (5U)

+#define DMAMUX_CSR_SOF5_Msk            (0x1UL << DMAMUX_CSR_SOF5_Pos)          /*!< 0x00000020 */

+#define DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5_Msk                     /*!< Channel 5 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF6_Pos            (6U)

+#define DMAMUX_CSR_SOF6_Msk            (0x1UL << DMAMUX_CSR_SOF6_Pos)          /*!< 0x00000040 */

+#define DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6_Msk                     /*!< Channel 6 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF7_Pos            (7U)

+#define DMAMUX_CSR_SOF7_Msk            (0x1UL << DMAMUX_CSR_SOF7_Pos)          /*!< 0x00000080 */

+#define DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7_Msk                     /*!< Channel 7 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF8_Pos            (8U)

+#define DMAMUX_CSR_SOF8_Msk            (0x1UL << DMAMUX_CSR_SOF8_Pos)          /*!< 0x00000100 */

+#define DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8_Msk                     /*!< Channel 8 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF9_Pos            (9U)

+#define DMAMUX_CSR_SOF9_Msk            (0x1UL << DMAMUX_CSR_SOF9_Pos)          /*!< 0x00000200 */

+#define DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9_Msk                     /*!< Channel 9 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF10_Pos           (10U)

+#define DMAMUX_CSR_SOF10_Msk           (0x1UL << DMAMUX_CSR_SOF10_Pos)         /*!< 0x00000400 */

+#define DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10_Msk                    /*!< Channel 10 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF11_Pos           (11U)

+#define DMAMUX_CSR_SOF11_Msk           (0x1UL << DMAMUX_CSR_SOF11_Pos)         /*!< 0x00000800 */

+#define DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11_Msk                    /*!< Channel 11 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF12_Pos           (12U)

+#define DMAMUX_CSR_SOF12_Msk           (0x1UL << DMAMUX_CSR_SOF12_Pos)         /*!< 0x00001000 */

+#define DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12_Msk                    /*!< Channel 12 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF13_Pos           (13U)

+#define DMAMUX_CSR_SOF13_Msk           (0x1UL << DMAMUX_CSR_SOF13_Pos)         /*!< 0x00002000 */

+#define DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13_Msk                    /*!< Channel 13 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF14_Pos           (14U)

+#define DMAMUX_CSR_SOF14_Msk           (0x1UL << DMAMUX_CSR_SOF14_Pos)         /*!< 0x00004000 */

+#define DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14_Msk                    /*!< Channel 14 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF15_Pos           (15U)

+#define DMAMUX_CSR_SOF15_Msk           (0x1UL << DMAMUX_CSR_SOF15_Pos)         /*!< 0x00008000 */

+#define DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15_Msk                    /*!< Channel 15 Synchronization overrun event flag */

+

+/********************  Bits definition for DMAMUX_CFR register  **************/

+#define DMAMUX_CFR_CSOF0_Pos           (0U)

+#define DMAMUX_CFR_CSOF0_Msk           (0x1UL << DMAMUX_CFR_CSOF0_Pos)         /*!< 0x00000001 */

+#define DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0_Msk                    /*!< Channel 0 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF1_Pos           (1U)

+#define DMAMUX_CFR_CSOF1_Msk           (0x1UL << DMAMUX_CFR_CSOF1_Pos)         /*!< 0x00000002 */

+#define DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1_Msk                    /*!< Channel 1 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF2_Pos           (2U)

+#define DMAMUX_CFR_CSOF2_Msk           (0x1UL << DMAMUX_CFR_CSOF2_Pos)         /*!< 0x00000004 */

+#define DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2_Msk                    /*!< Channel 2 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF3_Pos           (3U)

+#define DMAMUX_CFR_CSOF3_Msk           (0x1UL << DMAMUX_CFR_CSOF3_Pos)         /*!< 0x00000008 */

+#define DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3_Msk                    /*!< Channel 3 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF4_Pos           (4U)

+#define DMAMUX_CFR_CSOF4_Msk           (0x1UL << DMAMUX_CFR_CSOF4_Pos)         /*!< 0x00000010 */

+#define DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4_Msk                    /*!< Channel 4 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF5_Pos           (5U)

+#define DMAMUX_CFR_CSOF5_Msk           (0x1UL << DMAMUX_CFR_CSOF5_Pos)         /*!< 0x00000020 */

+#define DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5_Msk                    /*!< Channel 5 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF6_Pos           (6U)

+#define DMAMUX_CFR_CSOF6_Msk           (0x1UL << DMAMUX_CFR_CSOF6_Pos)         /*!< 0x00000040 */

+#define DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6_Msk                    /*!< Channel 6 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF7_Pos           (7U)

+#define DMAMUX_CFR_CSOF7_Msk           (0x1UL << DMAMUX_CFR_CSOF7_Pos)         /*!< 0x00000080 */

+#define DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7_Msk                    /*!< Channel 7 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF8_Pos           (8U)

+#define DMAMUX_CFR_CSOF8_Msk           (0x1UL << DMAMUX_CFR_CSOF8_Pos)         /*!< 0x00000100 */

+#define DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8_Msk                    /*!< Channel 8 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF9_Pos           (9U)

+#define DMAMUX_CFR_CSOF9_Msk           (0x1UL << DMAMUX_CFR_CSOF9_Pos)         /*!< 0x00000200 */

+#define DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9_Msk                    /*!< Channel 9 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF10_Pos          (10U)

+#define DMAMUX_CFR_CSOF10_Msk          (0x1UL << DMAMUX_CFR_CSOF10_Pos)        /*!< 0x00000400 */

+#define DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10_Msk                   /*!< Channel 10 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF11_Pos          (11U)

+#define DMAMUX_CFR_CSOF11_Msk          (0x1UL << DMAMUX_CFR_CSOF11_Pos)        /*!< 0x00000800 */

+#define DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11_Msk                   /*!< Channel 11 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF12_Pos          (12U)

+#define DMAMUX_CFR_CSOF12_Msk          (0x1UL << DMAMUX_CFR_CSOF12_Pos)        /*!< 0x00001000 */

+#define DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12_Msk                   /*!< Channel 12 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF13_Pos          (13U)

+#define DMAMUX_CFR_CSOF13_Msk          (0x1UL << DMAMUX_CFR_CSOF13_Pos)        /*!< 0x00002000 */

+#define DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13_Msk                   /*!< Channel 13 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF14_Pos          (14U)

+#define DMAMUX_CFR_CSOF14_Msk          (0x1UL << DMAMUX_CFR_CSOF14_Pos)        /*!< 0x00004000 */

+#define DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14_Msk                   /*!< Channel 14 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF15_Pos          (15U)

+#define DMAMUX_CFR_CSOF15_Msk          (0x1UL << DMAMUX_CFR_CSOF15_Pos)        /*!< 0x00008000 */

+#define DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15_Msk                   /*!< Channel 15 Clear synchronization overrun event flag */

+

+/********************  Bits definition for DMAMUX_RGxCR register  ************/

+#define DMAMUX_RGxCR_SIG_ID_Pos        (0U)

+#define DMAMUX_RGxCR_SIG_ID_Msk        (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)     /*!< 0x0000001F */

+#define DMAMUX_RGxCR_SIG_ID            DMAMUX_RGxCR_SIG_ID_Msk                 /*!< Signal identification */

+#define DMAMUX_RGxCR_SIG_ID_0          (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000001 */

+#define DMAMUX_RGxCR_SIG_ID_1          (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000002 */

+#define DMAMUX_RGxCR_SIG_ID_2          (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000004 */

+#define DMAMUX_RGxCR_SIG_ID_3          (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000008 */

+#define DMAMUX_RGxCR_SIG_ID_4          (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000010 */

+#define DMAMUX_RGxCR_OIE_Pos           (8U)

+#define DMAMUX_RGxCR_OIE_Msk           (0x1UL << DMAMUX_RGxCR_OIE_Pos)         /*!< 0x00000100 */

+#define DMAMUX_RGxCR_OIE               DMAMUX_RGxCR_OIE_Msk                    /*!< Trigger overrun interrupt enable */

+#define DMAMUX_RGxCR_GE_Pos            (16U)

+#define DMAMUX_RGxCR_GE_Msk            (0x1UL << DMAMUX_RGxCR_GE_Pos)          /*!< 0x00010000 */

+#define DMAMUX_RGxCR_GE                DMAMUX_RGxCR_GE_Msk                     /*!< DMA request generator enable */

+#define DMAMUX_RGxCR_GPOL_Pos          (17U)

+#define DMAMUX_RGxCR_GPOL_Msk          (0x3UL << DMAMUX_RGxCR_GPOL_Pos)        /*!< 0x00060000 */

+#define DMAMUX_RGxCR_GPOL              DMAMUX_RGxCR_GPOL_Msk                   /*!< DMA request generator trigger polarity */

+#define DMAMUX_RGxCR_GPOL_0            (0x1UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00020000 */

+#define DMAMUX_RGxCR_GPOL_1            (0x2UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00040000 */

+#define DMAMUX_RGxCR_GNBREQ_Pos        (19U)

+#define DMAMUX_RGxCR_GNBREQ_Msk        (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)     /*!< 0x00F80000 */

+#define DMAMUX_RGxCR_GNBREQ            DMAMUX_RGxCR_GNBREQ_Msk                 /*!< Number of DMA requests to be generated */

+#define DMAMUX_RGxCR_GNBREQ_0          (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00080000 */

+#define DMAMUX_RGxCR_GNBREQ_1          (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00100000 */

+#define DMAMUX_RGxCR_GNBREQ_2          (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00200000 */

+#define DMAMUX_RGxCR_GNBREQ_3          (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00400000 */

+#define DMAMUX_RGxCR_GNBREQ_4          (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00800000 */

+

+/********************  Bits definition for DMAMUX_RGSR register  **************/

+#define DMAMUX_RGSR_OF0_Pos            (0U)

+#define DMAMUX_RGSR_OF0_Msk            (0x1UL << DMAMUX_RGSR_OF0_Pos)          /*!< 0x00000001 */

+#define DMAMUX_RGSR_OF0                DMAMUX_RGSR_OF0_Msk                     /*!< Request generator channel 0 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF1_Pos            (1U)

+#define DMAMUX_RGSR_OF1_Msk            (0x1UL << DMAMUX_RGSR_OF1_Pos)          /*!< 0x00000002 */

+#define DMAMUX_RGSR_OF1                DMAMUX_RGSR_OF1_Msk                     /*!< Request generator channel 1 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF2_Pos            (2U)

+#define DMAMUX_RGSR_OF2_Msk            (0x1UL << DMAMUX_RGSR_OF2_Pos)          /*!< 0x00000004 */

+#define DMAMUX_RGSR_OF2                DMAMUX_RGSR_OF2_Msk                     /*!< Request generator channel 2 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF3_Pos            (3U)

+#define DMAMUX_RGSR_OF3_Msk            (0x1UL << DMAMUX_RGSR_OF3_Pos)          /*!< 0x00000008 */

+#define DMAMUX_RGSR_OF3                DMAMUX_RGSR_OF3_Msk                     /*!< Request generator channel 3 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF4_Pos            (4U)

+#define DMAMUX_RGSR_OF4_Msk            (0x1UL << DMAMUX_RGSR_OF4_Pos)          /*!< 0x00000010 */

+#define DMAMUX_RGSR_OF4                DMAMUX_RGSR_OF4_Msk                     /*!< Request generator channel 4 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF5_Pos            (5U)

+#define DMAMUX_RGSR_OF5_Msk            (0x1UL << DMAMUX_RGSR_OF5_Pos)          /*!< 0x00000020 */

+#define DMAMUX_RGSR_OF5                DMAMUX_RGSR_OF5_Msk                     /*!< Request generator channel 5 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF6_Pos            (6U)

+#define DMAMUX_RGSR_OF6_Msk            (0x1UL << DMAMUX_RGSR_OF6_Pos)          /*!< 0x00000040 */

+#define DMAMUX_RGSR_OF6                DMAMUX_RGSR_OF6_Msk                     /*!< Request generator channel 6 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF7_Pos            (7U)

+#define DMAMUX_RGSR_OF7_Msk            (0x1UL << DMAMUX_RGSR_OF7_Pos)          /*!< 0x00000080 */

+#define DMAMUX_RGSR_OF7                DMAMUX_RGSR_OF7_Msk                     /*!< Request generator channel 7 Trigger overrun event flag */

+

+/********************  Bits definition for DMAMUX_RGCFR register  **************/

+#define DMAMUX_RGCFR_COF0_Pos          (0U)

+#define DMAMUX_RGCFR_COF0_Msk          (0x1UL << DMAMUX_RGCFR_COF0_Pos)        /*!< 0x00000001 */

+#define DMAMUX_RGCFR_COF0              DMAMUX_RGCFR_COF0_Msk                   /*!< Request generator channel 0 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF1_Pos          (1U)

+#define DMAMUX_RGCFR_COF1_Msk          (0x1UL << DMAMUX_RGCFR_COF1_Pos)        /*!< 0x00000002 */

+#define DMAMUX_RGCFR_COF1              DMAMUX_RGCFR_COF1_Msk                   /*!< Request generator channel 1 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF2_Pos          (2U)

+#define DMAMUX_RGCFR_COF2_Msk          (0x1UL << DMAMUX_RGCFR_COF2_Pos)        /*!< 0x00000004 */

+#define DMAMUX_RGCFR_COF2              DMAMUX_RGCFR_COF2_Msk                   /*!< Request generator channel 2 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF3_Pos          (3U)

+#define DMAMUX_RGCFR_COF3_Msk          (0x1UL << DMAMUX_RGCFR_COF3_Pos)        /*!< 0x00000008 */

+#define DMAMUX_RGCFR_COF3              DMAMUX_RGCFR_COF3_Msk                   /*!< Request generator channel 3 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF4_Pos          (4U)

+#define DMAMUX_RGCFR_COF4_Msk          (0x1UL << DMAMUX_RGCFR_COF4_Pos)        /*!< 0x00000010 */

+#define DMAMUX_RGCFR_COF4              DMAMUX_RGCFR_COF4_Msk                   /*!< Request generator channel 4 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF5_Pos          (5U)

+#define DMAMUX_RGCFR_COF5_Msk          (0x1UL << DMAMUX_RGCFR_COF5_Pos)        /*!< 0x00000020 */

+#define DMAMUX_RGCFR_COF5              DMAMUX_RGCFR_COF5_Msk                   /*!< Request generator channel 5 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF6_Pos          (6U)

+#define DMAMUX_RGCFR_COF6_Msk          (0x1UL << DMAMUX_RGCFR_COF6_Pos)        /*!< 0x00000040 */

+#define DMAMUX_RGCFR_COF6              DMAMUX_RGCFR_COF6_Msk                   /*!< Request generator channel 6 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF7_Pos          (7U)

+#define DMAMUX_RGCFR_COF7_Msk          (0x1UL << DMAMUX_RGCFR_COF7_Pos)        /*!< 0x00000080 */

+#define DMAMUX_RGCFR_COF7              DMAMUX_RGCFR_COF7_Msk                   /*!< Request generator channel 7 Clear trigger overrun event flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         AHB Master DMA2D Controller (DMA2D)                */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for DMA2D_CR register  ******************/

+

+#define DMA2D_CR_START_Pos         (0U)

+#define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)               /*!< 0x00000001 */

+#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer                          */

+#define DMA2D_CR_SUSP_Pos          (1U)

+#define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                /*!< 0x00000002 */

+#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer                        */

+#define DMA2D_CR_ABORT_Pos         (2U)

+#define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)               /*!< 0x00000004 */

+#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer                          */

+#define DMA2D_CR_LOM_Pos           (6U)

+#define DMA2D_CR_LOM_Msk           (0x1UL << DMA2D_CR_LOM_Pos)                 /*!< 0x00000040 */

+#define DMA2D_CR_LOM               DMA2D_CR_LOM_Msk                            /*!< Line Offset Mode                         */

+#define DMA2D_CR_TEIE_Pos          (8U)

+#define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                /*!< 0x00000100 */

+#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable         */

+#define DMA2D_CR_TCIE_Pos          (9U)

+#define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                /*!< 0x00000200 */

+#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable      */

+#define DMA2D_CR_TWIE_Pos          (10U)

+#define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                /*!< 0x00000400 */

+#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable     */

+#define DMA2D_CR_CAEIE_Pos         (11U)

+#define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)               /*!< 0x00000800 */

+#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable      */

+#define DMA2D_CR_CTCIE_Pos         (12U)

+#define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)               /*!< 0x00001000 */

+#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */

+#define DMA2D_CR_CEIE_Pos          (13U)

+#define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                /*!< 0x00002000 */

+#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable    */

+#define DMA2D_CR_MODE_Pos          (16U)

+#define DMA2D_CR_MODE_Msk          (0x7UL << DMA2D_CR_MODE_Pos)                /*!< 0x00070000 */

+#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[2:0]                         */

+#define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */

+#define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */

+#define DMA2D_CR_MODE_2            (0x4UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00040000 */

+

+/********************  Bit definition for DMA2D_ISR register  *****************/

+

+#define DMA2D_ISR_TEIF_Pos         (0U)

+#define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)               /*!< 0x00000001 */

+#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag         */

+#define DMA2D_ISR_TCIF_Pos         (1U)

+#define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)               /*!< 0x00000002 */

+#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag      */

+#define DMA2D_ISR_TWIF_Pos         (2U)

+#define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)               /*!< 0x00000004 */

+#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag     */

+#define DMA2D_ISR_CAEIF_Pos        (3U)

+#define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)              /*!< 0x00000008 */

+#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag      */

+#define DMA2D_ISR_CTCIF_Pos        (4U)

+#define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)              /*!< 0x00000010 */

+#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */

+#define DMA2D_ISR_CEIF_Pos         (5U)

+#define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)               /*!< 0x00000020 */

+#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag    */

+

+/********************  Bit definition for DMA2D_IFCR register  ****************/

+

+#define DMA2D_IFCR_CTEIF_Pos       (0U)

+#define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)             /*!< 0x00000001 */

+#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */

+#define DMA2D_IFCR_CTCIF_Pos       (1U)

+#define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)             /*!< 0x00000002 */

+#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */

+#define DMA2D_IFCR_CTWIF_Pos       (2U)

+#define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)             /*!< 0x00000004 */

+#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */

+#define DMA2D_IFCR_CAECIF_Pos      (3U)

+#define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)            /*!< 0x00000008 */

+#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */

+#define DMA2D_IFCR_CCTCIF_Pos      (4U)

+#define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)            /*!< 0x00000010 */

+#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */

+#define DMA2D_IFCR_CCEIF_Pos       (5U)

+#define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)             /*!< 0x00000020 */

+#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */

+

+/********************  Bit definition for DMA2D_FGMAR register  ***************/

+

+#define DMA2D_FGMAR_MA_Pos         (0U)

+#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)        /*!< 0xFFFFFFFF */

+#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Foreground Memory Address */

+

+/********************  Bit definition for DMA2D_FGOR register  ****************/

+

+#define DMA2D_FGOR_LO_Pos          (0U)

+#define DMA2D_FGOR_LO_Msk          (0xFFFFUL << DMA2D_FGOR_LO_Pos)             /*!< 0x0000FFFF */

+#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */

+

+/********************  Bit definition for DMA2D_BGMAR register  ***************/

+

+#define DMA2D_BGMAR_MA_Pos         (0U)

+#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)        /*!< 0xFFFFFFFF */

+#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Background Memory Address */

+

+/********************  Bit definition for DMA2D_BGOR register  ****************/

+

+#define DMA2D_BGOR_LO_Pos          (0U)

+#define DMA2D_BGOR_LO_Msk          (0xFFFFUL << DMA2D_BGOR_LO_Pos)             /*!< 0x0000FFFF */

+#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */

+

+/********************  Bit definition for DMA2D_FGPFCCR register  *************/

+

+#define DMA2D_FGPFCCR_CM_Pos       (0U)

+#define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x0000000F */

+#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */

+#define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */

+#define DMA2D_FGPFCCR_CCM_Pos      (4U)

+#define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)            /*!< 0x00000010 */

+#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */

+#define DMA2D_FGPFCCR_START_Pos    (5U)

+#define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)          /*!< 0x00000020 */

+#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */

+#define DMA2D_FGPFCCR_CS_Pos       (8U)

+#define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)            /*!< 0x0000FF00 */

+#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */

+#define DMA2D_FGPFCCR_AM_Pos       (16U)

+#define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00030000 */

+#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */

+#define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */

+#define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */

+#define DMA2D_FGPFCCR_CSS_Pos      (18U)

+#define DMA2D_FGPFCCR_CSS_Msk      (0x3UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x000C0000 */

+#define DMA2D_FGPFCCR_CSS          DMA2D_FGPFCCR_CSS_Msk                       /* !< Chroma Sub-Sampling */

+#define DMA2D_FGPFCCR_CSS_0        (0x1UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00040000 */

+#define DMA2D_FGPFCCR_CSS_1        (0x2UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00080000 */

+#define DMA2D_FGPFCCR_AI_Pos       (20U)

+#define DMA2D_FGPFCCR_AI_Msk       (0x1UL << DMA2D_FGPFCCR_AI_Pos)             /*!< 0x00100000 */

+#define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Foreground Input Alpha Inverted */

+#define DMA2D_FGPFCCR_RBS_Pos      (21U)

+#define DMA2D_FGPFCCR_RBS_Msk      (0x1UL << DMA2D_FGPFCCR_RBS_Pos)            /*!< 0x00200000 */

+#define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Foreground Input Red Blue Swap */

+#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)

+#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */

+#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */

+

+/********************  Bit definition for DMA2D_FGCOLR register  **************/

+

+#define DMA2D_FGCOLR_BLUE_Pos      (0U)

+#define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)           /*!< 0x000000FF */

+#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Foreground Blue Value */

+#define DMA2D_FGCOLR_GREEN_Pos     (8U)

+#define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */

+#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Foreground Green Value */

+#define DMA2D_FGCOLR_RED_Pos       (16U)

+#define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)            /*!< 0x00FF0000 */

+#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Foreground Red Value */

+

+/********************  Bit definition for DMA2D_BGPFCCR register  *************/

+

+#define DMA2D_BGPFCCR_CM_Pos       (0U)

+#define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x0000000F */

+#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */

+#define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_BGPFCCR_CM_3         (0x8UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000008 */

+#define DMA2D_BGPFCCR_CCM_Pos      (4U)

+#define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)            /*!< 0x00000010 */

+#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */

+#define DMA2D_BGPFCCR_START_Pos    (5U)

+#define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)          /*!< 0x00000020 */

+#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */

+#define DMA2D_BGPFCCR_CS_Pos       (8U)

+#define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)            /*!< 0x0000FF00 */

+#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */

+#define DMA2D_BGPFCCR_AM_Pos       (16U)

+#define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00030000 */

+#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */

+#define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */

+#define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */

+#define DMA2D_BGPFCCR_AI_Pos       (20U)

+#define DMA2D_BGPFCCR_AI_Msk       (0x1UL << DMA2D_BGPFCCR_AI_Pos)             /*!< 0x00100000 */

+#define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< background Input Alpha Inverted */

+#define DMA2D_BGPFCCR_RBS_Pos      (21U)

+#define DMA2D_BGPFCCR_RBS_Msk      (0x1UL << DMA2D_BGPFCCR_RBS_Pos)            /*!< 0x00200000 */

+#define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Background Input Red Blue Swap */

+#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)

+#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */

+#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */

+

+/********************  Bit definition for DMA2D_BGCOLR register  **************/

+

+#define DMA2D_BGCOLR_BLUE_Pos      (0U)

+#define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)           /*!< 0x000000FF */

+#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Background Blue Value */

+#define DMA2D_BGCOLR_GREEN_Pos     (8U)

+#define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */

+#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Background Green Value */

+#define DMA2D_BGCOLR_RED_Pos       (16U)

+#define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)            /*!< 0x00FF0000 */

+#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Background Red Value */

+

+/********************  Bit definition for DMA2D_FGCMAR register  **************/

+

+#define DMA2D_FGCMAR_MA_Pos        (0U)

+#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */

+#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Foreground CLUT Memory Address */

+

+/********************  Bit definition for DMA2D_BGCMAR register  **************/

+

+#define DMA2D_BGCMAR_MA_Pos        (0U)

+#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */

+#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Background CLUT Memory Address */

+

+/********************  Bit definition for DMA2D_OPFCCR register  **************/

+

+#define DMA2D_OPFCCR_CM_Pos        (0U)

+#define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000007 */

+#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Output Color mode CM[2:0] */

+#define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_OPFCCR_SB_Pos        (8U)

+#define DMA2D_OPFCCR_SB_Msk        (0x1UL << DMA2D_OPFCCR_SB_Pos)              /*!< 0x00000100 */

+#define DMA2D_OPFCCR_SB            DMA2D_OPFCCR_SB_Msk                         /*!< Swap Bytes */

+#define DMA2D_OPFCCR_AI_Pos        (20U)

+#define DMA2D_OPFCCR_AI_Msk        (0x1UL << DMA2D_OPFCCR_AI_Pos)              /*!< 0x00100000 */

+#define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Output Alpha Inverted */

+#define DMA2D_OPFCCR_RBS_Pos       (21U)

+#define DMA2D_OPFCCR_RBS_Msk       (0x1UL << DMA2D_OPFCCR_RBS_Pos)             /*!< 0x00200000 */

+#define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Output Red Blue Swap */

+

+/********************  Bit definition for DMA2D_OCOLR register  ***************/

+

+/*!<Mode_ARGB8888/RGB888 */

+

+#define DMA2D_OCOLR_BLUE_1_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_1_Msk     (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos)            /*0x000000FFU*/

+#define DMA2D_OCOLR_BLUE_1         DMA2D_OCOLR_BLUE_1_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_1_Pos    (8U)

+#define DMA2D_OCOLR_GREEN_1_Msk    (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos)            /*0x0000FF00U)*/

+#define DMA2D_OCOLR_GREEN_1        DMA2D_OCOLR_GREEN_1_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_1_Pos      (16U)

+#define DMA2D_OCOLR_RED_1_Msk      (0xFFUL << DMA2D_OCOLR_RED_1_Pos)            /*0x00FF0000U */

+#define DMA2D_OCOLR_RED_1          DMA2D_OCOLR_RED_1_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_1_Pos    (24U)

+#define DMA2D_OCOLR_ALPHA_1_Msk    (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos)          /*0xFF000000U*/

+#define DMA2D_OCOLR_ALPHA_1        DMA2D_OCOLR_ALPHA_1_Msk                     /*!< Output Alpha Channel Value */

+

+/*!<Mode_RGB565 */

+#define DMA2D_OCOLR_BLUE_2_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_2_Msk     (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos)            /*0x0000001FU*/

+#define DMA2D_OCOLR_BLUE_2         DMA2D_OCOLR_BLUE_2_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_2_Pos    (5U)

+#define DMA2D_OCOLR_GREEN_2_Msk    (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos)          /* 0x000007E0U */

+#define DMA2D_OCOLR_GREEN_2        DMA2D_OCOLR_GREEN_2_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_2_Pos      (11U)

+#define DMA2D_OCOLR_RED_2_Msk      (0xF8UL<<DMA2D_OCOLR_RED_2_Pos)              /*0x0000F800U*/

+#define DMA2D_OCOLR_RED_2          DMA2D_OCOLR_RED_2_Msk                       /*!< Output Red Value */

+

+/*!<Mode_ARGB1555 */

+#define DMA2D_OCOLR_BLUE_3_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_3_Msk     (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos)           /*0x0000001FU*/

+#define DMA2D_OCOLR_BLUE_3         DMA2D_OCOLR_BLUE_3_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_3_Pos    (5U)

+#define DMA2D_OCOLR_GREEN_3_Msk    (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos)          /*0x000003E0U*/

+#define DMA2D_OCOLR_GREEN_3        DMA2D_OCOLR_GREEN_3_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_3_Pos      (10U)

+#define DMA2D_OCOLR_RED_3_Msk      (0x7CUL << DMA2D_OCOLR_RED_3_Pos)            /* 0x00007C00U*/

+#define DMA2D_OCOLR_RED_3          DMA2D_OCOLR_RED_3_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_3_Pos    (15U)

+#define DMA2D_OCOLR_ALPHA_3_Msk    (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos)           /*0x00008000U*/

+#define DMA2D_OCOLR_ALPHA_3        DMA2D_OCOLR_ALPHA_3_Msk                     /*!< Output Alpha Channel Value */

+

+/*!<Mode_ARGB4444 */

+#define DMA2D_OCOLR_BLUE_4_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_4_Msk     (0xFUL << DMA2D_OCOLR_BLUE_4_Pos)            /*0x0000000FU*/

+#define DMA2D_OCOLR_BLUE_4         DMA2D_OCOLR_BLUE_4_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_4_Pos    (4U)

+#define DMA2D_OCOLR_GREEN_4_Msk    (0xFUL << DMA2D_OCOLR_GREEN_4_Pos)           /*0x000000F0U*/

+#define DMA2D_OCOLR_GREEN_4        DMA2D_OCOLR_GREEN_4_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_4_Pos      (8U)

+#define DMA2D_OCOLR_RED_4_Msk      (0xFUL << DMA2D_OCOLR_RED_4_Pos)             /*0x00000F00U*/

+#define DMA2D_OCOLR_RED_4          DMA2D_OCOLR_RED_4_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_4_Pos    (12U)

+#define DMA2D_OCOLR_ALPHA_4_Msk    (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos)            /*0x0000F000U*/

+#define DMA2D_OCOLR_ALPHA_4        DMA2D_OCOLR_ALPHA_4_Msk                     /*!< Output Alpha Channel Value */

+

+/********************  Bit definition for DMA2D_OMAR register  ****************/

+

+#define DMA2D_OMAR_MA_Pos          (0U)

+#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)         /*!< 0xFFFFFFFF */

+#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Output Memory Address */

+

+/********************  Bit definition for DMA2D_OOR register  *****************/

+

+#define DMA2D_OOR_LO_Pos           (0U)

+#define DMA2D_OOR_LO_Msk           (0xFFFFUL << DMA2D_OOR_LO_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Output Line Offset */

+

+/********************  Bit definition for DMA2D_NLR register  *****************/

+

+#define DMA2D_NLR_NL_Pos           (0U)

+#define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */

+#define DMA2D_NLR_PL_Pos           (16U)

+#define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)              /*!< 0x3FFF0000 */

+#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */

+

+/********************  Bit definition for DMA2D_LWR register  *****************/

+

+#define DMA2D_LWR_LW_Pos           (0U)

+#define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */

+

+/********************  Bit definition for DMA2D_AMTCR register  ***************/

+

+#define DMA2D_AMTCR_EN_Pos         (0U)

+#define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)               /*!< 0x00000001 */

+#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */

+#define DMA2D_AMTCR_DT_Pos         (8U)

+#define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)              /*!< 0x0000FF00 */

+#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */

+

+

+/********************  Bit definition for DMA2D_FGCLUT register  **************/

+

+/********************  Bit definition for DMA2D_BGCLUT register  **************/

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                    External Interrupt/Event Controller                     */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for EXTI_RTSR1 register  *******************/

+#define EXTI_RTSR1_TR_Pos          (0U)

+#define EXTI_RTSR1_TR_Msk          (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)           /*!< 0x003FFFFF */

+#define EXTI_RTSR1_TR              EXTI_RTSR1_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR1_TR0_Pos         (0U)

+#define EXTI_RTSR1_TR0_Msk         (0x1UL << EXTI_RTSR1_TR0_Pos)               /*!< 0x00000001 */

+#define EXTI_RTSR1_TR0             EXTI_RTSR1_TR0_Msk                          /*!< Rising trigger event configuration bit of line 0 */

+#define EXTI_RTSR1_TR1_Pos         (1U)

+#define EXTI_RTSR1_TR1_Msk         (0x1UL << EXTI_RTSR1_TR1_Pos)               /*!< 0x00000002 */

+#define EXTI_RTSR1_TR1             EXTI_RTSR1_TR1_Msk                          /*!< Rising trigger event configuration bit of line 1 */

+#define EXTI_RTSR1_TR2_Pos         (2U)

+#define EXTI_RTSR1_TR2_Msk         (0x1UL << EXTI_RTSR1_TR2_Pos)               /*!< 0x00000004 */

+#define EXTI_RTSR1_TR2             EXTI_RTSR1_TR2_Msk                          /*!< Rising trigger event configuration bit of line 2 */

+#define EXTI_RTSR1_TR3_Pos         (3U)

+#define EXTI_RTSR1_TR3_Msk         (0x1UL << EXTI_RTSR1_TR3_Pos)               /*!< 0x00000008 */

+#define EXTI_RTSR1_TR3             EXTI_RTSR1_TR3_Msk                          /*!< Rising trigger event configuration bit of line 3 */

+#define EXTI_RTSR1_TR4_Pos         (4U)

+#define EXTI_RTSR1_TR4_Msk         (0x1UL << EXTI_RTSR1_TR4_Pos)               /*!< 0x00000010 */

+#define EXTI_RTSR1_TR4             EXTI_RTSR1_TR4_Msk                          /*!< Rising trigger event configuration bit of line 4 */

+#define EXTI_RTSR1_TR5_Pos         (5U)

+#define EXTI_RTSR1_TR5_Msk         (0x1UL << EXTI_RTSR1_TR5_Pos)               /*!< 0x00000020 */

+#define EXTI_RTSR1_TR5             EXTI_RTSR1_TR5_Msk                          /*!< Rising trigger event configuration bit of line 5 */

+#define EXTI_RTSR1_TR6_Pos         (6U)

+#define EXTI_RTSR1_TR6_Msk         (0x1UL << EXTI_RTSR1_TR6_Pos)               /*!< 0x00000040 */

+#define EXTI_RTSR1_TR6             EXTI_RTSR1_TR6_Msk                          /*!< Rising trigger event configuration bit of line 6 */

+#define EXTI_RTSR1_TR7_Pos         (7U)

+#define EXTI_RTSR1_TR7_Msk         (0x1UL << EXTI_RTSR1_TR7_Pos)               /*!< 0x00000080 */

+#define EXTI_RTSR1_TR7             EXTI_RTSR1_TR7_Msk                          /*!< Rising trigger event configuration bit of line 7 */

+#define EXTI_RTSR1_TR8_Pos         (8U)

+#define EXTI_RTSR1_TR8_Msk         (0x1UL << EXTI_RTSR1_TR8_Pos)               /*!< 0x00000100 */

+#define EXTI_RTSR1_TR8             EXTI_RTSR1_TR8_Msk                          /*!< Rising trigger event configuration bit of line 8 */

+#define EXTI_RTSR1_TR9_Pos         (9U)

+#define EXTI_RTSR1_TR9_Msk         (0x1UL << EXTI_RTSR1_TR9_Pos)               /*!< 0x00000200 */

+#define EXTI_RTSR1_TR9             EXTI_RTSR1_TR9_Msk                          /*!< Rising trigger event configuration bit of line 9 */

+#define EXTI_RTSR1_TR10_Pos        (10U)

+#define EXTI_RTSR1_TR10_Msk        (0x1UL << EXTI_RTSR1_TR10_Pos)              /*!< 0x00000400 */

+#define EXTI_RTSR1_TR10            EXTI_RTSR1_TR10_Msk                         /*!< Rising trigger event configuration bit of line 10 */

+#define EXTI_RTSR1_TR11_Pos        (11U)

+#define EXTI_RTSR1_TR11_Msk        (0x1UL << EXTI_RTSR1_TR11_Pos)              /*!< 0x00000800 */

+#define EXTI_RTSR1_TR11            EXTI_RTSR1_TR11_Msk                         /*!< Rising trigger event configuration bit of line 11 */

+#define EXTI_RTSR1_TR12_Pos        (12U)

+#define EXTI_RTSR1_TR12_Msk        (0x1UL << EXTI_RTSR1_TR12_Pos)              /*!< 0x00001000 */

+#define EXTI_RTSR1_TR12            EXTI_RTSR1_TR12_Msk                         /*!< Rising trigger event configuration bit of line 12 */

+#define EXTI_RTSR1_TR13_Pos        (13U)

+#define EXTI_RTSR1_TR13_Msk        (0x1UL << EXTI_RTSR1_TR13_Pos)              /*!< 0x00002000 */

+#define EXTI_RTSR1_TR13            EXTI_RTSR1_TR13_Msk                         /*!< Rising trigger event configuration bit of line 13 */

+#define EXTI_RTSR1_TR14_Pos        (14U)

+#define EXTI_RTSR1_TR14_Msk        (0x1UL << EXTI_RTSR1_TR14_Pos)              /*!< 0x00004000 */

+#define EXTI_RTSR1_TR14            EXTI_RTSR1_TR14_Msk                         /*!< Rising trigger event configuration bit of line 14 */

+#define EXTI_RTSR1_TR15_Pos        (15U)

+#define EXTI_RTSR1_TR15_Msk        (0x1UL << EXTI_RTSR1_TR15_Pos)              /*!< 0x00008000 */

+#define EXTI_RTSR1_TR15            EXTI_RTSR1_TR15_Msk                         /*!< Rising trigger event configuration bit of line 15 */

+#define EXTI_RTSR1_TR16_Pos        (16U)

+#define EXTI_RTSR1_TR16_Msk        (0x1UL << EXTI_RTSR1_TR16_Pos)              /*!< 0x00010000 */

+#define EXTI_RTSR1_TR16            EXTI_RTSR1_TR16_Msk                         /*!< Rising trigger event configuration bit of line 16 */

+#define EXTI_RTSR1_TR17_Pos        (17U)

+#define EXTI_RTSR1_TR17_Msk        (0x1UL << EXTI_RTSR1_TR17_Pos)              /*!< 0x00020000 */

+#define EXTI_RTSR1_TR17            EXTI_RTSR1_TR17_Msk                         /*!< Rising trigger event configuration bit of line 17 */

+#define EXTI_RTSR1_TR18_Pos        (18U)

+#define EXTI_RTSR1_TR18_Msk        (0x1UL << EXTI_RTSR1_TR18_Pos)              /*!< 0x00040000 */

+#define EXTI_RTSR1_TR18            EXTI_RTSR1_TR18_Msk                         /*!< Rising trigger event configuration bit of line 18 */

+#define EXTI_RTSR1_TR19_Pos        (19U)

+#define EXTI_RTSR1_TR19_Msk        (0x1UL << EXTI_RTSR1_TR19_Pos)              /*!< 0x00080000 */

+#define EXTI_RTSR1_TR19            EXTI_RTSR1_TR19_Msk                         /*!< Rising trigger event configuration bit of line 19 */

+#define EXTI_RTSR1_TR20_Pos        (20U)

+#define EXTI_RTSR1_TR20_Msk        (0x1UL << EXTI_RTSR1_TR20_Pos)              /*!< 0x00100000 */

+#define EXTI_RTSR1_TR20            EXTI_RTSR1_TR20_Msk                         /*!< Rising trigger event configuration bit of line 20 */

+#define EXTI_RTSR1_TR21_Pos        (21U)

+#define EXTI_RTSR1_TR21_Msk        (0x1UL << EXTI_RTSR1_TR21_Pos)              /*!< 0x00200000 */

+#define EXTI_RTSR1_TR21            EXTI_RTSR1_TR21_Msk                         /*!< Rising trigger event configuration bit of line 21 */

+

+/******************  Bit definition for EXTI_FTSR1 register  *******************/

+#define EXTI_FTSR1_TR_Pos          (0U)

+#define EXTI_FTSR1_TR_Msk          (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)           /*!< 0x003FFFFF */

+#define EXTI_FTSR1_TR              EXTI_FTSR1_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR1_TR0_Pos         (0U)

+#define EXTI_FTSR1_TR0_Msk         (0x1UL << EXTI_FTSR1_TR0_Pos)               /*!< 0x00000001 */

+#define EXTI_FTSR1_TR0             EXTI_FTSR1_TR0_Msk                          /*!< Falling trigger event configuration bit of line 0 */

+#define EXTI_FTSR1_TR1_Pos         (1U)

+#define EXTI_FTSR1_TR1_Msk         (0x1UL << EXTI_FTSR1_TR1_Pos)               /*!< 0x00000002 */

+#define EXTI_FTSR1_TR1             EXTI_FTSR1_TR1_Msk                          /*!< Falling trigger event configuration bit of line 1 */

+#define EXTI_FTSR1_TR2_Pos         (2U)

+#define EXTI_FTSR1_TR2_Msk         (0x1UL << EXTI_FTSR1_TR2_Pos)               /*!< 0x00000004 */

+#define EXTI_FTSR1_TR2             EXTI_FTSR1_TR2_Msk                          /*!< Falling trigger event configuration bit of line 2 */

+#define EXTI_FTSR1_TR3_Pos         (3U)

+#define EXTI_FTSR1_TR3_Msk         (0x1UL << EXTI_FTSR1_TR3_Pos)               /*!< 0x00000008 */

+#define EXTI_FTSR1_TR3             EXTI_FTSR1_TR3_Msk                          /*!< Falling trigger event configuration bit of line 3 */

+#define EXTI_FTSR1_TR4_Pos         (4U)

+#define EXTI_FTSR1_TR4_Msk         (0x1UL << EXTI_FTSR1_TR4_Pos)               /*!< 0x00000010 */

+#define EXTI_FTSR1_TR4             EXTI_FTSR1_TR4_Msk                          /*!< Falling trigger event configuration bit of line 4 */

+#define EXTI_FTSR1_TR5_Pos         (5U)

+#define EXTI_FTSR1_TR5_Msk         (0x1UL << EXTI_FTSR1_TR5_Pos)               /*!< 0x00000020 */

+#define EXTI_FTSR1_TR5             EXTI_FTSR1_TR5_Msk                          /*!< Falling trigger event configuration bit of line 5 */

+#define EXTI_FTSR1_TR6_Pos         (6U)

+#define EXTI_FTSR1_TR6_Msk         (0x1UL << EXTI_FTSR1_TR6_Pos)               /*!< 0x00000040 */

+#define EXTI_FTSR1_TR6             EXTI_FTSR1_TR6_Msk                          /*!< Falling trigger event configuration bit of line 6 */

+#define EXTI_FTSR1_TR7_Pos         (7U)

+#define EXTI_FTSR1_TR7_Msk         (0x1UL << EXTI_FTSR1_TR7_Pos)               /*!< 0x00000080 */

+#define EXTI_FTSR1_TR7             EXTI_FTSR1_TR7_Msk                          /*!< Falling trigger event configuration bit of line 7 */

+#define EXTI_FTSR1_TR8_Pos         (8U)

+#define EXTI_FTSR1_TR8_Msk         (0x1UL << EXTI_FTSR1_TR8_Pos)               /*!< 0x00000100 */

+#define EXTI_FTSR1_TR8             EXTI_FTSR1_TR8_Msk                          /*!< Falling trigger event configuration bit of line 8 */

+#define EXTI_FTSR1_TR9_Pos         (9U)

+#define EXTI_FTSR1_TR9_Msk         (0x1UL << EXTI_FTSR1_TR9_Pos)               /*!< 0x00000200 */

+#define EXTI_FTSR1_TR9             EXTI_FTSR1_TR9_Msk                          /*!< Falling trigger event configuration bit of line 9 */

+#define EXTI_FTSR1_TR10_Pos        (10U)

+#define EXTI_FTSR1_TR10_Msk        (0x1UL << EXTI_FTSR1_TR10_Pos)              /*!< 0x00000400 */

+#define EXTI_FTSR1_TR10            EXTI_FTSR1_TR10_Msk                         /*!< Falling trigger event configuration bit of line 10 */

+#define EXTI_FTSR1_TR11_Pos        (11U)

+#define EXTI_FTSR1_TR11_Msk        (0x1UL << EXTI_FTSR1_TR11_Pos)              /*!< 0x00000800 */

+#define EXTI_FTSR1_TR11            EXTI_FTSR1_TR11_Msk                         /*!< Falling trigger event configuration bit of line 11 */

+#define EXTI_FTSR1_TR12_Pos        (12U)

+#define EXTI_FTSR1_TR12_Msk        (0x1UL << EXTI_FTSR1_TR12_Pos)              /*!< 0x00001000 */

+#define EXTI_FTSR1_TR12            EXTI_FTSR1_TR12_Msk                         /*!< Falling trigger event configuration bit of line 12 */

+#define EXTI_FTSR1_TR13_Pos        (13U)

+#define EXTI_FTSR1_TR13_Msk        (0x1UL << EXTI_FTSR1_TR13_Pos)              /*!< 0x00002000 */

+#define EXTI_FTSR1_TR13            EXTI_FTSR1_TR13_Msk                         /*!< Falling trigger event configuration bit of line 13 */

+#define EXTI_FTSR1_TR14_Pos        (14U)

+#define EXTI_FTSR1_TR14_Msk        (0x1UL << EXTI_FTSR1_TR14_Pos)              /*!< 0x00004000 */

+#define EXTI_FTSR1_TR14            EXTI_FTSR1_TR14_Msk                         /*!< Falling trigger event configuration bit of line 14 */

+#define EXTI_FTSR1_TR15_Pos        (15U)

+#define EXTI_FTSR1_TR15_Msk        (0x1UL << EXTI_FTSR1_TR15_Pos)              /*!< 0x00008000 */

+#define EXTI_FTSR1_TR15            EXTI_FTSR1_TR15_Msk                         /*!< Falling trigger event configuration bit of line 15 */

+#define EXTI_FTSR1_TR16_Pos        (16U)

+#define EXTI_FTSR1_TR16_Msk        (0x1UL << EXTI_FTSR1_TR16_Pos)              /*!< 0x00010000 */

+#define EXTI_FTSR1_TR16            EXTI_FTSR1_TR16_Msk                         /*!< Falling trigger event configuration bit of line 16 */

+#define EXTI_FTSR1_TR17_Pos        (17U)

+#define EXTI_FTSR1_TR17_Msk        (0x1UL << EXTI_FTSR1_TR17_Pos)              /*!< 0x00020000 */

+#define EXTI_FTSR1_TR17            EXTI_FTSR1_TR17_Msk                         /*!< Falling trigger event configuration bit of line 17 */

+#define EXTI_FTSR1_TR18_Pos        (18U)

+#define EXTI_FTSR1_TR18_Msk        (0x1UL << EXTI_FTSR1_TR18_Pos)              /*!< 0x00040000 */

+#define EXTI_FTSR1_TR18            EXTI_FTSR1_TR18_Msk                         /*!< Falling trigger event configuration bit of line 18 */

+#define EXTI_FTSR1_TR19_Pos        (19U)

+#define EXTI_FTSR1_TR19_Msk        (0x1UL << EXTI_FTSR1_TR19_Pos)              /*!< 0x00080000 */

+#define EXTI_FTSR1_TR19            EXTI_FTSR1_TR19_Msk                         /*!< Falling trigger event configuration bit of line 19 */

+#define EXTI_FTSR1_TR20_Pos        (20U)

+#define EXTI_FTSR1_TR20_Msk        (0x1UL << EXTI_FTSR1_TR20_Pos)              /*!< 0x00100000 */

+#define EXTI_FTSR1_TR20            EXTI_FTSR1_TR20_Msk                         /*!< Falling trigger event configuration bit of line 20 */

+#define EXTI_FTSR1_TR21_Pos        (21U)

+#define EXTI_FTSR1_TR21_Msk        (0x1UL << EXTI_FTSR1_TR21_Pos)              /*!< 0x00200000 */

+#define EXTI_FTSR1_TR21            EXTI_FTSR1_TR21_Msk                         /*!< Falling trigger event configuration bit of line 21 */

+

+/******************  Bit definition for EXTI_SWIER1 register  ******************/

+#define EXTI_SWIER1_SWIER0_Pos     (0U)

+#define EXTI_SWIER1_SWIER0_Msk     (0x1UL << EXTI_SWIER1_SWIER0_Pos)           /*!< 0x00000001 */

+#define EXTI_SWIER1_SWIER0         EXTI_SWIER1_SWIER0_Msk                      /*!< Software Interrupt on line 0 */

+#define EXTI_SWIER1_SWIER1_Pos     (1U)

+#define EXTI_SWIER1_SWIER1_Msk     (0x1UL << EXTI_SWIER1_SWIER1_Pos)           /*!< 0x00000002 */

+#define EXTI_SWIER1_SWIER1         EXTI_SWIER1_SWIER1_Msk                      /*!< Software Interrupt on line 1 */

+#define EXTI_SWIER1_SWIER2_Pos     (2U)

+#define EXTI_SWIER1_SWIER2_Msk     (0x1UL << EXTI_SWIER1_SWIER2_Pos)           /*!< 0x00000004 */

+#define EXTI_SWIER1_SWIER2         EXTI_SWIER1_SWIER2_Msk                      /*!< Software Interrupt on line 2 */

+#define EXTI_SWIER1_SWIER3_Pos     (3U)

+#define EXTI_SWIER1_SWIER3_Msk     (0x1UL << EXTI_SWIER1_SWIER3_Pos)           /*!< 0x00000008 */

+#define EXTI_SWIER1_SWIER3         EXTI_SWIER1_SWIER3_Msk                      /*!< Software Interrupt on line 3 */

+#define EXTI_SWIER1_SWIER4_Pos     (4U)

+#define EXTI_SWIER1_SWIER4_Msk     (0x1UL << EXTI_SWIER1_SWIER4_Pos)           /*!< 0x00000010 */

+#define EXTI_SWIER1_SWIER4         EXTI_SWIER1_SWIER4_Msk                      /*!< Software Interrupt on line 4 */

+#define EXTI_SWIER1_SWIER5_Pos     (5U)

+#define EXTI_SWIER1_SWIER5_Msk     (0x1UL << EXTI_SWIER1_SWIER5_Pos)           /*!< 0x00000020 */

+#define EXTI_SWIER1_SWIER5         EXTI_SWIER1_SWIER5_Msk                      /*!< Software Interrupt on line 5 */

+#define EXTI_SWIER1_SWIER6_Pos     (6U)

+#define EXTI_SWIER1_SWIER6_Msk     (0x1UL << EXTI_SWIER1_SWIER6_Pos)           /*!< 0x00000040 */

+#define EXTI_SWIER1_SWIER6         EXTI_SWIER1_SWIER6_Msk                      /*!< Software Interrupt on line 6 */

+#define EXTI_SWIER1_SWIER7_Pos     (7U)

+#define EXTI_SWIER1_SWIER7_Msk     (0x1UL << EXTI_SWIER1_SWIER7_Pos)           /*!< 0x00000080 */

+#define EXTI_SWIER1_SWIER7         EXTI_SWIER1_SWIER7_Msk                      /*!< Software Interrupt on line 7 */

+#define EXTI_SWIER1_SWIER8_Pos     (8U)

+#define EXTI_SWIER1_SWIER8_Msk     (0x1UL << EXTI_SWIER1_SWIER8_Pos)           /*!< 0x00000100 */

+#define EXTI_SWIER1_SWIER8         EXTI_SWIER1_SWIER8_Msk                      /*!< Software Interrupt on line 8 */

+#define EXTI_SWIER1_SWIER9_Pos     (9U)

+#define EXTI_SWIER1_SWIER9_Msk     (0x1UL << EXTI_SWIER1_SWIER9_Pos)           /*!< 0x00000200 */

+#define EXTI_SWIER1_SWIER9         EXTI_SWIER1_SWIER9_Msk                      /*!< Software Interrupt on line 9 */

+#define EXTI_SWIER1_SWIER10_Pos    (10U)

+#define EXTI_SWIER1_SWIER10_Msk    (0x1UL << EXTI_SWIER1_SWIER10_Pos)          /*!< 0x00000400 */

+#define EXTI_SWIER1_SWIER10        EXTI_SWIER1_SWIER10_Msk                     /*!< Software Interrupt on line 10 */

+#define EXTI_SWIER1_SWIER11_Pos    (11U)

+#define EXTI_SWIER1_SWIER11_Msk    (0x1UL << EXTI_SWIER1_SWIER11_Pos)          /*!< 0x00000800 */

+#define EXTI_SWIER1_SWIER11        EXTI_SWIER1_SWIER11_Msk                     /*!< Software Interrupt on line 11 */

+#define EXTI_SWIER1_SWIER12_Pos    (12U)

+#define EXTI_SWIER1_SWIER12_Msk    (0x1UL << EXTI_SWIER1_SWIER12_Pos)          /*!< 0x00001000 */

+#define EXTI_SWIER1_SWIER12        EXTI_SWIER1_SWIER12_Msk                     /*!< Software Interrupt on line 12 */

+#define EXTI_SWIER1_SWIER13_Pos    (13U)

+#define EXTI_SWIER1_SWIER13_Msk    (0x1UL << EXTI_SWIER1_SWIER13_Pos)          /*!< 0x00002000 */

+#define EXTI_SWIER1_SWIER13        EXTI_SWIER1_SWIER13_Msk                     /*!< Software Interrupt on line 13 */

+#define EXTI_SWIER1_SWIER14_Pos    (14U)

+#define EXTI_SWIER1_SWIER14_Msk    (0x1UL << EXTI_SWIER1_SWIER14_Pos)          /*!< 0x00004000 */

+#define EXTI_SWIER1_SWIER14        EXTI_SWIER1_SWIER14_Msk                     /*!< Software Interrupt on line 14 */

+#define EXTI_SWIER1_SWIER15_Pos    (15U)

+#define EXTI_SWIER1_SWIER15_Msk    (0x1UL << EXTI_SWIER1_SWIER15_Pos)          /*!< 0x00008000 */

+#define EXTI_SWIER1_SWIER15        EXTI_SWIER1_SWIER15_Msk                     /*!< Software Interrupt on line 15 */

+#define EXTI_SWIER1_SWIER16_Pos    (16U)

+#define EXTI_SWIER1_SWIER16_Msk    (0x1UL << EXTI_SWIER1_SWIER16_Pos)          /*!< 0x00010000 */

+#define EXTI_SWIER1_SWIER16        EXTI_SWIER1_SWIER16_Msk                     /*!< Software Interrupt on line 16 */

+#define EXTI_SWIER1_SWIER17_Pos    (17U)

+#define EXTI_SWIER1_SWIER17_Msk    (0x1UL << EXTI_SWIER1_SWIER17_Pos)          /*!< 0x00020000 */

+#define EXTI_SWIER1_SWIER17        EXTI_SWIER1_SWIER17_Msk                     /*!< Software Interrupt on line 17 */

+#define EXTI_SWIER1_SWIER18_Pos    (18U)

+#define EXTI_SWIER1_SWIER18_Msk    (0x1UL << EXTI_SWIER1_SWIER18_Pos)          /*!< 0x00040000 */

+#define EXTI_SWIER1_SWIER18        EXTI_SWIER1_SWIER18_Msk                     /*!< Software Interrupt on line 18 */

+#define EXTI_SWIER1_SWIER19_Pos    (19U)

+#define EXTI_SWIER1_SWIER19_Msk    (0x1UL << EXTI_SWIER1_SWIER19_Pos)          /*!< 0x00080000 */

+#define EXTI_SWIER1_SWIER19        EXTI_SWIER1_SWIER19_Msk                     /*!< Software Interrupt on line 19 */

+#define EXTI_SWIER1_SWIER20_Pos    (20U)

+#define EXTI_SWIER1_SWIER20_Msk    (0x1UL << EXTI_SWIER1_SWIER20_Pos)          /*!< 0x00100000 */

+#define EXTI_SWIER1_SWIER20        EXTI_SWIER1_SWIER20_Msk                     /*!< Software Interrupt on line 20 */

+#define EXTI_SWIER1_SWIER21_Pos    (21U)

+#define EXTI_SWIER1_SWIER21_Msk    (0x1UL << EXTI_SWIER1_SWIER21_Pos)          /*!< 0x00200000 */

+#define EXTI_SWIER1_SWIER21        EXTI_SWIER1_SWIER21_Msk                     /*!< Software Interrupt on line 21 */

+

+/******************  Bit definition for EXTI_D3PMR1 register  ******************/

+#define EXTI_D3PMR1_MR0_Pos        (0U)

+#define EXTI_D3PMR1_MR0_Msk        (0x1UL << EXTI_D3PMR1_MR0_Pos)              /*!< 0x00000001 */

+#define EXTI_D3PMR1_MR0            EXTI_D3PMR1_MR0_Msk                         /*!< Pending Mask Event for line 0  */

+#define EXTI_D3PMR1_MR1_Pos        (1U)

+#define EXTI_D3PMR1_MR1_Msk        (0x1UL << EXTI_D3PMR1_MR1_Pos)              /*!< 0x00000002 */

+#define EXTI_D3PMR1_MR1            EXTI_D3PMR1_MR1_Msk                         /*!< Pending Mask Event for line 1  */

+#define EXTI_D3PMR1_MR2_Pos        (2U)

+#define EXTI_D3PMR1_MR2_Msk        (0x1UL << EXTI_D3PMR1_MR2_Pos)              /*!< 0x00000004 */

+#define EXTI_D3PMR1_MR2            EXTI_D3PMR1_MR2_Msk                         /*!< Pending Mask Event for line 2  */

+#define EXTI_D3PMR1_MR3_Pos        (3U)

+#define EXTI_D3PMR1_MR3_Msk        (0x1UL << EXTI_D3PMR1_MR3_Pos)              /*!< 0x00000008 */

+#define EXTI_D3PMR1_MR3            EXTI_D3PMR1_MR3_Msk                         /*!< Pending Mask Event for line 3  */

+#define EXTI_D3PMR1_MR4_Pos        (4U)

+#define EXTI_D3PMR1_MR4_Msk        (0x1UL << EXTI_D3PMR1_MR4_Pos)              /*!< 0x00000010 */

+#define EXTI_D3PMR1_MR4            EXTI_D3PMR1_MR4_Msk                         /*!< Pending Mask Event for line 4  */

+#define EXTI_D3PMR1_MR5_Pos        (5U)

+#define EXTI_D3PMR1_MR5_Msk        (0x1UL << EXTI_D3PMR1_MR5_Pos)              /*!< 0x00000020 */

+#define EXTI_D3PMR1_MR5            EXTI_D3PMR1_MR5_Msk                         /*!< Pending Mask Event for line 5  */

+#define EXTI_D3PMR1_MR6_Pos        (6U)

+#define EXTI_D3PMR1_MR6_Msk        (0x1UL << EXTI_D3PMR1_MR6_Pos)              /*!< 0x00000040 */

+#define EXTI_D3PMR1_MR6            EXTI_D3PMR1_MR6_Msk                         /*!< Pending Mask Event for line 6  */

+#define EXTI_D3PMR1_MR7_Pos        (7U)

+#define EXTI_D3PMR1_MR7_Msk        (0x1UL << EXTI_D3PMR1_MR7_Pos)              /*!< 0x00000080 */

+#define EXTI_D3PMR1_MR7            EXTI_D3PMR1_MR7_Msk                         /*!< Pending Mask Event for line 7  */

+#define EXTI_D3PMR1_MR8_Pos        (8U)

+#define EXTI_D3PMR1_MR8_Msk        (0x1UL << EXTI_D3PMR1_MR8_Pos)              /*!< 0x00000100 */

+#define EXTI_D3PMR1_MR8            EXTI_D3PMR1_MR8_Msk                         /*!< Pending Mask Event for line 8  */

+#define EXTI_D3PMR1_MR9_Pos        (9U)

+#define EXTI_D3PMR1_MR9_Msk        (0x1UL << EXTI_D3PMR1_MR9_Pos)              /*!< 0x00000200 */

+#define EXTI_D3PMR1_MR9            EXTI_D3PMR1_MR9_Msk                         /*!< Pending Mask Event for line 9  */

+#define EXTI_D3PMR1_MR10_Pos       (10U)

+#define EXTI_D3PMR1_MR10_Msk       (0x1UL << EXTI_D3PMR1_MR10_Pos)             /*!< 0x00000400 */

+#define EXTI_D3PMR1_MR10           EXTI_D3PMR1_MR10_Msk                        /*!< Pending Mask Event for line 10 */

+#define EXTI_D3PMR1_MR11_Pos       (11U)

+#define EXTI_D3PMR1_MR11_Msk       (0x1UL << EXTI_D3PMR1_MR11_Pos)             /*!< 0x00000800 */

+#define EXTI_D3PMR1_MR11           EXTI_D3PMR1_MR11_Msk                        /*!< Pending Mask Event for line 11 */

+#define EXTI_D3PMR1_MR12_Pos       (12U)

+#define EXTI_D3PMR1_MR12_Msk       (0x1UL << EXTI_D3PMR1_MR12_Pos)             /*!< 0x00001000 */

+#define EXTI_D3PMR1_MR12           EXTI_D3PMR1_MR12_Msk                        /*!< Pending Mask Event for line 12 */

+#define EXTI_D3PMR1_MR13_Pos       (13U)

+#define EXTI_D3PMR1_MR13_Msk       (0x1UL << EXTI_D3PMR1_MR13_Pos)             /*!< 0x00002000 */

+#define EXTI_D3PMR1_MR13           EXTI_D3PMR1_MR13_Msk                        /*!< Pending Mask Event for line 13 */

+#define EXTI_D3PMR1_MR14_Pos       (14U)

+#define EXTI_D3PMR1_MR14_Msk       (0x1UL << EXTI_D3PMR1_MR14_Pos)             /*!< 0x00004000 */

+#define EXTI_D3PMR1_MR14           EXTI_D3PMR1_MR14_Msk                        /*!< Pending Mask Event for line 14 */

+#define EXTI_D3PMR1_MR15_Pos       (15U)

+#define EXTI_D3PMR1_MR15_Msk       (0x1UL << EXTI_D3PMR1_MR15_Pos)             /*!< 0x00008000 */

+#define EXTI_D3PMR1_MR15           EXTI_D3PMR1_MR15_Msk                        /*!< Pending Mask Event for line 15 */

+#define EXTI_D3PMR1_MR19_Pos       (19U)

+#define EXTI_D3PMR1_MR19_Msk       (0x1UL << EXTI_D3PMR1_MR19_Pos)             /*!< 0x00080000 */

+#define EXTI_D3PMR1_MR19           EXTI_D3PMR1_MR19_Msk                        /*!< Pending Mask Event for line 19 */

+#define EXTI_D3PMR1_MR20_Pos       (20U)

+#define EXTI_D3PMR1_MR20_Msk       (0x1UL << EXTI_D3PMR1_MR20_Pos)             /*!< 0x00100000 */

+#define EXTI_D3PMR1_MR20           EXTI_D3PMR1_MR20_Msk                        /*!< Pending Mask Event for line 20 */

+#define EXTI_D3PMR1_MR21_Pos       (21U)

+#define EXTI_D3PMR1_MR21_Msk       (0x1UL << EXTI_D3PMR1_MR21_Pos)             /*!< 0x00200000 */

+#define EXTI_D3PMR1_MR21           EXTI_D3PMR1_MR21_Msk                        /*!< Pending Mask Event for line 21 */

+#define EXTI_D3PMR1_MR25_Pos       (24U)

+#define EXTI_D3PMR1_MR25_Msk       (0x1UL << EXTI_D3PMR1_MR25_Pos)             /*!< 0x01000000 */

+#define EXTI_D3PMR1_MR25           EXTI_D3PMR1_MR25_Msk                        /*!< Pending Mask Event for line 25 */

+

+/*******************  Bit definition for EXTI_D3PCR1L register  ****************/

+#define EXTI_D3PCR1L_PCS0_Pos       (0U)

+#define EXTI_D3PCR1L_PCS0_Msk       (0x3UL << EXTI_D3PCR1L_PCS0_Pos)           /*!< 0x00000003 */

+#define EXTI_D3PCR1L_PCS0           EXTI_D3PCR1L_PCS0_Msk                      /*!< D3 Pending request clear input signal selection on line 0 */

+#define EXTI_D3PCR1L_PCS1_Pos       (2U)

+#define EXTI_D3PCR1L_PCS1_Msk       (0x3UL << EXTI_D3PCR1L_PCS1_Pos)           /*!< 0x000000C0 */

+#define EXTI_D3PCR1L_PCS1           EXTI_D3PCR1L_PCS1_Msk                      /*!< D3 Pending request clear input signal selection on line 1 */

+#define EXTI_D3PCR1L_PCS2_Pos       (4U)

+#define EXTI_D3PCR1L_PCS2_Msk       (0x3UL << EXTI_D3PCR1L_PCS2_Pos)           /*!< 0x00000030 */

+#define EXTI_D3PCR1L_PCS2           EXTI_D3PCR1L_PCS2_Msk                      /*!< D3 Pending request clear input signal selection on line 2 */

+#define EXTI_D3PCR1L_PCS3_Pos       (6U)

+#define EXTI_D3PCR1L_PCS3_Msk       (0x3UL << EXTI_D3PCR1L_PCS3_Pos)           /*!< 0x000000C0 */

+#define EXTI_D3PCR1L_PCS3           EXTI_D3PCR1L_PCS3_Msk                      /*!< D3 Pending request clear input signal selection on line 3 */

+#define EXTI_D3PCR1L_PCS4_Pos       (8U)

+#define EXTI_D3PCR1L_PCS4_Msk       (0x3UL << EXTI_D3PCR1L_PCS4_Pos)           /*!< 0x00000300 */

+#define EXTI_D3PCR1L_PCS4           EXTI_D3PCR1L_PCS4_Msk                      /*!< D3 Pending request clear input signal selection on line 4 */

+#define EXTI_D3PCR1L_PCS5_Pos       (10U)

+#define EXTI_D3PCR1L_PCS5_Msk       (0x3UL << EXTI_D3PCR1L_PCS5_Pos)           /*!< 0x00000C00 */

+#define EXTI_D3PCR1L_PCS5           EXTI_D3PCR1L_PCS5_Msk                      /*!< D3 Pending request clear input signal selection on line 5 */

+#define EXTI_D3PCR1L_PCS6_Pos       (12U)

+#define EXTI_D3PCR1L_PCS6_Msk       (0x3UL << EXTI_D3PCR1L_PCS6_Pos)           /*!< 0x00003000 */

+#define EXTI_D3PCR1L_PCS6           EXTI_D3PCR1L_PCS6_Msk                      /*!< D3 Pending request clear input signal selection on line 6 */

+#define EXTI_D3PCR1L_PCS7_Pos       (14U)

+#define EXTI_D3PCR1L_PCS7_Msk       (0x3UL << EXTI_D3PCR1L_PCS7_Pos)           /*!< 0x0000C000 */

+#define EXTI_D3PCR1L_PCS7           EXTI_D3PCR1L_PCS7_Msk                      /*!< D3 Pending request clear input signal selection on line 7 */

+#define EXTI_D3PCR1L_PCS8_Pos       (16U)

+#define EXTI_D3PCR1L_PCS8_Msk       (0x3UL << EXTI_D3PCR1L_PCS8_Pos)           /*!< 0x00030000 */

+#define EXTI_D3PCR1L_PCS8           EXTI_D3PCR1L_PCS8_Msk                      /*!< D3 Pending request clear input signal selection on line 8 */

+#define EXTI_D3PCR1L_PCS9_Pos       (18U)

+#define EXTI_D3PCR1L_PCS9_Msk       (0x3UL << EXTI_D3PCR1L_PCS9_Pos)           /*!< 0x000C0000 */

+#define EXTI_D3PCR1L_PCS9           EXTI_D3PCR1L_PCS9_Msk                      /*!< D3 Pending request clear input signal selection on line 9 */

+#define EXTI_D3PCR1L_PCS10_Pos      (20U)

+#define EXTI_D3PCR1L_PCS10_Msk      (0x3UL << EXTI_D3PCR1L_PCS10_Pos)          /*!< 0x00300000 */

+#define EXTI_D3PCR1L_PCS10          EXTI_D3PCR1L_PCS10_Msk                     /*!< D3 Pending request clear input signal selection on line 10*/

+#define EXTI_D3PCR1L_PCS11_Pos      (22U)

+#define EXTI_D3PCR1L_PCS11_Msk      (0x3UL << EXTI_D3PCR1L_PCS11_Pos)          /*!< 0x00C00000 */

+#define EXTI_D3PCR1L_PCS11          EXTI_D3PCR1L_PCS11_Msk                     /*!< D3 Pending request clear input signal selection on line 11*/

+#define EXTI_D3PCR1L_PCS12_Pos      (24U)

+#define EXTI_D3PCR1L_PCS12_Msk      (0x3UL << EXTI_D3PCR1L_PCS12_Pos)          /*!< 0x03000000 */

+#define EXTI_D3PCR1L_PCS12          EXTI_D3PCR1L_PCS12_Msk                     /*!< D3 Pending request clear input signal selection on line 12*/

+#define EXTI_D3PCR1L_PCS13_Pos      (26U)

+#define EXTI_D3PCR1L_PCS13_Msk      (0x3UL << EXTI_D3PCR1L_PCS13_Pos)          /*!< 0x0C000000 */

+#define EXTI_D3PCR1L_PCS13          EXTI_D3PCR1L_PCS13_Msk                     /*!< D3 Pending request clear input signal selection on line 13*/

+#define EXTI_D3PCR1L_PCS14_Pos      (28U)

+#define EXTI_D3PCR1L_PCS14_Msk      (0x3UL << EXTI_D3PCR1L_PCS14_Pos)          /*!< 0x30000000 */

+#define EXTI_D3PCR1L_PCS14          EXTI_D3PCR1L_PCS14_Msk                     /*!< D3 Pending request clear input signal selection on line 14*/

+#define EXTI_D3PCR1L_PCS15_Pos      (30U)

+#define EXTI_D3PCR1L_PCS15_Msk      (0x3UL << EXTI_D3PCR1L_PCS15_Pos)          /*!< 0xC0000000 */

+#define EXTI_D3PCR1L_PCS15          EXTI_D3PCR1L_PCS15_Msk                     /*!< D3 Pending request clear input signal selection on line 15*/

+

+/*******************  Bit definition for EXTI_D3PCR1H register  ****************/

+#define EXTI_D3PCR1H_PCS19_Pos       (6U)

+#define EXTI_D3PCR1H_PCS19_Msk       (0x3UL << EXTI_D3PCR1H_PCS19_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR1H_PCS19           EXTI_D3PCR1H_PCS19_Msk                    /*!< D3 Pending request clear input signal selection on line 19 */

+#define EXTI_D3PCR1H_PCS20_Pos       (8U)

+#define EXTI_D3PCR1H_PCS20_Msk       (0x3UL << EXTI_D3PCR1H_PCS20_Pos)         /*!< 0x00000300 */

+#define EXTI_D3PCR1H_PCS20           EXTI_D3PCR1H_PCS20_Msk                    /*!< D3 Pending request clear input signal selection on line 20 */

+#define EXTI_D3PCR1H_PCS21_Pos       (10U)

+#define EXTI_D3PCR1H_PCS21_Msk       (0x3UL << EXTI_D3PCR1H_PCS21_Pos)         /*!< 0x00000C00 */

+#define EXTI_D3PCR1H_PCS21           EXTI_D3PCR1H_PCS21_Msk                    /*!< D3 Pending request clear input signal selection on line 21 */

+#define EXTI_D3PCR1H_PCS25_Pos       (18U)

+#define EXTI_D3PCR1H_PCS25_Msk       (0x3UL << EXTI_D3PCR1H_PCS25_Pos)         /*!< 0x000C0000 */

+#define EXTI_D3PCR1H_PCS25           EXTI_D3PCR1H_PCS25_Msk                    /*!< D3 Pending request clear input signal selection on line 25 */

+

+/******************  Bit definition for EXTI_RTSR2 register  *******************/

+#define EXTI_RTSR2_TR_Pos          (17U)

+#define EXTI_RTSR2_TR_Msk          (0x5UL << EXTI_RTSR2_TR_Pos)                /*!< 0x000A0000 */

+#define EXTI_RTSR2_TR              EXTI_RTSR2_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR2_TR49_Pos        (17U)

+#define EXTI_RTSR2_TR49_Msk        (0x1UL << EXTI_RTSR2_TR49_Pos)              /*!< 0x00020000 */

+#define EXTI_RTSR2_TR49            EXTI_RTSR2_TR49_Msk                         /*!< Rising trigger event configuration bit of line 49 */

+#define EXTI_RTSR2_TR51_Pos        (19U)

+#define EXTI_RTSR2_TR51_Msk        (0x1UL << EXTI_RTSR2_TR51_Pos)              /*!< 0x00080000 */

+#define EXTI_RTSR2_TR51            EXTI_RTSR2_TR51_Msk                         /*!< Rising trigger event configuration bit of line 51 */

+

+/******************  Bit definition for EXTI_FTSR2 register  *******************/

+#define EXTI_FTSR2_TR_Pos          (17U)

+#define EXTI_FTSR2_TR_Msk          (0x5UL << EXTI_FTSR2_TR_Pos)                /*!< 0x000A0000 */

+#define EXTI_FTSR2_TR              EXTI_FTSR2_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR2_TR49_Pos        (17U)

+#define EXTI_FTSR2_TR49_Msk        (0x1UL << EXTI_FTSR2_TR49_Pos)              /*!< 0x00020000 */

+#define EXTI_FTSR2_TR49            EXTI_FTSR2_TR49_Msk                         /*!< Falling trigger event configuration bit of line 49 */

+#define EXTI_FTSR2_TR51_Pos        (19U)

+#define EXTI_FTSR2_TR51_Msk        (0x1UL << EXTI_FTSR2_TR51_Pos)              /*!< 0x00080000 */

+#define EXTI_FTSR2_TR51            EXTI_FTSR2_TR51_Msk                         /*!< Falling trigger event configuration bit of line 51 */

+

+/******************  Bit definition for EXTI_SWIER2 register  ******************/

+#define EXTI_SWIER2_SWIER49_Pos    (17U)

+#define EXTI_SWIER2_SWIER49_Msk    (0x1UL << EXTI_SWIER2_SWIER49_Pos)          /*!< 0x00020000 */

+#define EXTI_SWIER2_SWIER49        EXTI_SWIER2_SWIER49_Msk                     /*!< Software Interrupt on line 49 */

+#define EXTI_SWIER2_SWIER51_Pos    (19U)

+#define EXTI_SWIER2_SWIER51_Msk    (0x1UL << EXTI_SWIER2_SWIER51_Pos)          /*!< 0x00080000 */

+#define EXTI_SWIER2_SWIER51        EXTI_SWIER2_SWIER51_Msk                     /*!< Software Interrupt on line 51 */

+

+/******************  Bit definition for EXTI_D3PMR2 register  ******************/

+#define EXTI_D3PMR2_MR34_Pos       (2U)

+#define EXTI_D3PMR2_MR34_Msk       (0x1UL << EXTI_D3PMR2_MR34_Pos)             /*!< 0x00000004 */

+#define EXTI_D3PMR2_MR34           EXTI_D3PMR2_MR34_Msk                        /*!< Pending Mask Event for line 34  */

+#define EXTI_D3PMR2_MR35_Pos       (3U)

+#define EXTI_D3PMR2_MR35_Msk       (0x1UL << EXTI_D3PMR2_MR35_Pos)             /*!< 0x00000008 */

+#define EXTI_D3PMR2_MR35           EXTI_D3PMR2_MR35_Msk                        /*!< Pending Mask Event for line 35  */

+#define EXTI_D3PMR2_MR41_Pos       (9U)

+#define EXTI_D3PMR2_MR41_Msk       (0x1UL << EXTI_D3PMR2_MR41_Pos)             /*!< 0x00000200 */

+#define EXTI_D3PMR2_MR41           EXTI_D3PMR2_MR41_Msk                        /*!< Pending Mask Event for line 41  */

+#define EXTI_D3PMR2_MR48_Pos       (16U)

+#define EXTI_D3PMR2_MR48_Msk       (0x1UL << EXTI_D3PMR2_MR48_Pos)             /*!< 0x00010000 */

+#define EXTI_D3PMR2_MR48           EXTI_D3PMR2_MR48_Msk                        /*!< Pending Mask Event for line 48  */

+#define EXTI_D3PMR2_MR49_Pos       (17U)

+#define EXTI_D3PMR2_MR49_Msk       (0x1UL << EXTI_D3PMR2_MR49_Pos)             /*!< 0x00020000 */

+#define EXTI_D3PMR2_MR49           EXTI_D3PMR2_MR49_Msk                        /*!< Pending Mask Event for line 49  */

+#define EXTI_D3PMR2_MR50_Pos       (18U)

+#define EXTI_D3PMR2_MR50_Msk       (0x1UL << EXTI_D3PMR2_MR50_Pos)             /*!< 0x00040000 */

+#define EXTI_D3PMR2_MR50           EXTI_D3PMR2_MR50_Msk                        /*!< Pending Mask Event for line 50  */

+#define EXTI_D3PMR2_MR51_Pos       (19U)

+#define EXTI_D3PMR2_MR51_Msk       (0x1UL << EXTI_D3PMR2_MR51_Pos)             /*!< 0x00080000 */

+#define EXTI_D3PMR2_MR51           EXTI_D3PMR2_MR51_Msk                        /*!< Pending Mask Event for line 51  */

+/*******************  Bit definition for EXTI_D3PCR2L register  ****************/

+#define EXTI_D3PCR2L_PCS34_Pos       (4U)

+#define EXTI_D3PCR2L_PCS34_Msk       (0x3UL << EXTI_D3PCR2L_PCS34_Pos)         /*!< 0x00000030 */

+#define EXTI_D3PCR2L_PCS34           EXTI_D3PCR2L_PCS34_Msk                    /*!< D3 Pending request clear input signal selection on line 34 */

+#define EXTI_D3PCR2L_PCS35_Pos       (6U)

+#define EXTI_D3PCR2L_PCS35_Msk       (0x3UL << EXTI_D3PCR2L_PCS35_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR2L_PCS35           EXTI_D3PCR2L_PCS35_Msk                    /*!< D3 Pending request clear input signal selection on line 35 */

+#define EXTI_D3PCR2L_PCS41_Pos       (18U)

+#define EXTI_D3PCR2L_PCS41_Msk       (0x3UL << EXTI_D3PCR2L_PCS41_Pos)         /*!< 0x000C0000 */

+#define EXTI_D3PCR2L_PCS41           EXTI_D3PCR2L_PCS41_Msk                    /*!< D3 Pending request clear input signal selection on line 41 */

+

+

+/*******************  Bit definition for EXTI_D3PCR2H register  ****************/

+#define EXTI_D3PCR2H_PCS48_Pos       (0U)

+#define EXTI_D3PCR2H_PCS48_Msk       (0x3UL << EXTI_D3PCR2H_PCS48_Pos)         /*!< 0x00000003 */

+#define EXTI_D3PCR2H_PCS48           EXTI_D3PCR2H_PCS48_Msk                    /*!< D3 Pending request clear input signal selection on line 48 */

+#define EXTI_D3PCR2H_PCS49_Pos       (2U)

+#define EXTI_D3PCR2H_PCS49_Msk       (0x3UL << EXTI_D3PCR2H_PCS49_Pos)         /*!< 0x0000000C */

+#define EXTI_D3PCR2H_PCS49           EXTI_D3PCR2H_PCS49_Msk                    /*!< D3 Pending request clear input signal selection on line 49 */

+#define EXTI_D3PCR2H_PCS50_Pos       (4U)

+#define EXTI_D3PCR2H_PCS50_Msk       (0x3UL << EXTI_D3PCR2H_PCS50_Pos)         /*!< 0x00000030 */

+#define EXTI_D3PCR2H_PCS50           EXTI_D3PCR2H_PCS50_Msk                    /*!< D3 Pending request clear input signal selection on line 50 */

+#define EXTI_D3PCR2H_PCS51_Pos       (6U)

+#define EXTI_D3PCR2H_PCS51_Msk       (0x3UL << EXTI_D3PCR2H_PCS51_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR2H_PCS51           EXTI_D3PCR2H_PCS51_Msk                    /*!< D3 Pending request clear input signal selection on line 51 */

+/******************  Bit definition for EXTI_RTSR3 register  *******************/

+#define EXTI_RTSR3_TR_Pos          (18U)

+#define EXTI_RTSR3_TR_Msk          (0x9UL << EXTI_RTSR3_TR_Pos)                /*!< 0x00240000 */

+#define EXTI_RTSR3_TR              EXTI_RTSR3_TR_Msk                           /*!< Rising trigger event configuration bit            */

+#define EXTI_RTSR3_TR82_Pos        (18U)

+#define EXTI_RTSR3_TR82_Msk        (0x1UL << EXTI_RTSR3_TR82_Pos)              /*!< 0x00040000 */

+#define EXTI_RTSR3_TR82            EXTI_RTSR3_TR82_Msk                         /*!< Rising trigger event configuration bit of line 82 */

+#define EXTI_RTSR3_TR85_Pos        (21U)

+#define EXTI_RTSR3_TR85_Msk        (0x1UL << EXTI_RTSR3_TR85_Pos)              /*!< 0x00200000 */

+#define EXTI_RTSR3_TR85            EXTI_RTSR3_TR85_Msk                         /*!< Rising trigger event configuration bit of line 85 */

+

+/******************  Bit definition for EXTI_FTSR3 register  *******************/

+#define EXTI_FTSR3_TR_Pos          (18U)

+#define EXTI_FTSR3_TR_Msk          (0x9UL << EXTI_FTSR3_TR_Pos)                /*!< 0x00240000 */

+#define EXTI_FTSR3_TR              EXTI_FTSR3_TR_Msk                           /*!< Falling trigger event configuration bit            */

+#define EXTI_FTSR3_TR82_Pos        (18U)

+#define EXTI_FTSR3_TR82_Msk        (0x1UL << EXTI_FTSR3_TR82_Pos)              /*!< 0x00040000 */

+#define EXTI_FTSR3_TR82            EXTI_FTSR3_TR82_Msk                         /*!< Falling trigger event configuration bit of line 82 */

+#define EXTI_FTSR3_TR85_Pos        (21U)

+#define EXTI_FTSR3_TR85_Msk        (0x1UL << EXTI_FTSR3_TR85_Pos)              /*!< 0x00200000 */

+#define EXTI_FTSR3_TR85            EXTI_FTSR3_TR85_Msk                         /*!< Falling trigger event configuration bit of line 85 */

+

+/******************  Bit definition for EXTI_SWIER3 register  ******************/

+#define EXTI_SWIER3_SWI_Pos        (18U)

+#define EXTI_SWIER3_SWI_Msk        (0x9UL << EXTI_SWIER3_SWI_Pos)              /*!< 0x00240000 */

+#define EXTI_SWIER3_SWI            EXTI_SWIER3_SWI_Msk                         /*!< Software Interrupt event bit */

+#define EXTI_SWIER3_SWIER82_Pos    (18U)

+#define EXTI_SWIER3_SWIER82_Msk    (0x1UL << EXTI_SWIER3_SWIER82_Pos)          /*!< 0x00040000 */

+#define EXTI_SWIER3_SWIER82        EXTI_SWIER3_SWIER82_Msk                     /*!< Software Interrupt on line 82 */

+#define EXTI_SWIER3_SWIER85_Pos    (21U)

+#define EXTI_SWIER3_SWIER85_Msk    (0x1UL << EXTI_SWIER3_SWIER85_Pos)          /*!< 0x00200000 */

+#define EXTI_SWIER3_SWIER85        EXTI_SWIER3_SWIER85_Msk                     /*!< Software Interrupt on line 85 */

+

+/******************  Bit definition for EXTI_D3PMR3 register  ******************/

+#define EXTI_D3PMR3_MR88_Pos       (24U)

+#define EXTI_D3PMR3_MR88_Msk       (0x1UL << EXTI_D3PMR3_MR88_Pos)             /*!< 0x01000000 */

+#define EXTI_D3PMR3_MR88           EXTI_D3PMR3_MR88_Msk                        /*!< Pending Mask Event for line 88  */

+

+/*******************  Bit definition for EXTI_D3PCR3H register  ****************/

+#define EXTI_D3PCR3H_PCS88_Pos       (16U)

+#define EXTI_D3PCR3H_PCS88_Msk       (0x3UL << EXTI_D3PCR3H_PCS88_Pos)         /*!< 0x00030000 */

+#define EXTI_D3PCR3H_PCS88           EXTI_D3PCR3H_PCS88_Msk                    /*!< D3 Pending request clear input signal selection on line 88 */

+

+/*******************  Bit definition for EXTI_IMR1 register  *******************/

+#define EXTI_IMR1_IM_Pos           (0U)

+#define EXTI_IMR1_IM_Msk           (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)          /*!< 0xFFFFFFFF */

+#define EXTI_IMR1_IM               EXTI_IMR1_IM_Msk                            /*!< Interrupt Mask */

+#define EXTI_IMR1_IM0_Pos          (0U)

+#define EXTI_IMR1_IM0_Msk          (0x1UL << EXTI_IMR1_IM0_Pos)                /*!< 0x00000001 */

+#define EXTI_IMR1_IM0              EXTI_IMR1_IM0_Msk                           /*!< Interrupt Mask on line 0 */

+#define EXTI_IMR1_IM1_Pos          (1U)

+#define EXTI_IMR1_IM1_Msk          (0x1UL << EXTI_IMR1_IM1_Pos)                /*!< 0x00000002 */

+#define EXTI_IMR1_IM1              EXTI_IMR1_IM1_Msk                           /*!< Interrupt Mask on line 1 */

+#define EXTI_IMR1_IM2_Pos          (2U)

+#define EXTI_IMR1_IM2_Msk          (0x1UL << EXTI_IMR1_IM2_Pos)                /*!< 0x00000004 */

+#define EXTI_IMR1_IM2              EXTI_IMR1_IM2_Msk                           /*!< Interrupt Mask on line 2 */

+#define EXTI_IMR1_IM3_Pos          (3U)

+#define EXTI_IMR1_IM3_Msk          (0x1UL << EXTI_IMR1_IM3_Pos)                /*!< 0x00000008 */

+#define EXTI_IMR1_IM3              EXTI_IMR1_IM3_Msk                           /*!< Interrupt Mask on line 3 */

+#define EXTI_IMR1_IM4_Pos          (4U)

+#define EXTI_IMR1_IM4_Msk          (0x1UL << EXTI_IMR1_IM4_Pos)                /*!< 0x00000010 */

+#define EXTI_IMR1_IM4              EXTI_IMR1_IM4_Msk                           /*!< Interrupt Mask on line 4 */

+#define EXTI_IMR1_IM5_Pos          (5U)

+#define EXTI_IMR1_IM5_Msk          (0x1UL << EXTI_IMR1_IM5_Pos)                /*!< 0x00000020 */

+#define EXTI_IMR1_IM5              EXTI_IMR1_IM5_Msk                           /*!< Interrupt Mask on line 5 */

+#define EXTI_IMR1_IM6_Pos          (6U)

+#define EXTI_IMR1_IM6_Msk          (0x1UL << EXTI_IMR1_IM6_Pos)                /*!< 0x00000040 */

+#define EXTI_IMR1_IM6              EXTI_IMR1_IM6_Msk                           /*!< Interrupt Mask on line 6 */

+#define EXTI_IMR1_IM7_Pos          (7U)

+#define EXTI_IMR1_IM7_Msk          (0x1UL << EXTI_IMR1_IM7_Pos)                /*!< 0x00000080 */

+#define EXTI_IMR1_IM7              EXTI_IMR1_IM7_Msk                           /*!< Interrupt Mask on line 7 */

+#define EXTI_IMR1_IM8_Pos          (8U)

+#define EXTI_IMR1_IM8_Msk          (0x1UL << EXTI_IMR1_IM8_Pos)                /*!< 0x00000100 */

+#define EXTI_IMR1_IM8              EXTI_IMR1_IM8_Msk                           /*!< Interrupt Mask on line 8 */

+#define EXTI_IMR1_IM9_Pos          (9U)

+#define EXTI_IMR1_IM9_Msk          (0x1UL << EXTI_IMR1_IM9_Pos)                /*!< 0x00000200 */

+#define EXTI_IMR1_IM9              EXTI_IMR1_IM9_Msk                           /*!< Interrupt Mask on line 9 */

+#define EXTI_IMR1_IM10_Pos         (10U)

+#define EXTI_IMR1_IM10_Msk         (0x1UL << EXTI_IMR1_IM10_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR1_IM10             EXTI_IMR1_IM10_Msk                          /*!< Interrupt Mask on line 10 */

+#define EXTI_IMR1_IM11_Pos         (11U)

+#define EXTI_IMR1_IM11_Msk         (0x1UL << EXTI_IMR1_IM11_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR1_IM11             EXTI_IMR1_IM11_Msk                          /*!< Interrupt Mask on line 11 */

+#define EXTI_IMR1_IM12_Pos         (12U)

+#define EXTI_IMR1_IM12_Msk         (0x1UL << EXTI_IMR1_IM12_Pos)               /*!< 0x00001000 */

+#define EXTI_IMR1_IM12             EXTI_IMR1_IM12_Msk                          /*!< Interrupt Mask on line 12 */

+#define EXTI_IMR1_IM13_Pos         (13U)

+#define EXTI_IMR1_IM13_Msk         (0x1UL << EXTI_IMR1_IM13_Pos)               /*!< 0x00002000 */

+#define EXTI_IMR1_IM13             EXTI_IMR1_IM13_Msk                          /*!< Interrupt Mask on line 13 */

+#define EXTI_IMR1_IM14_Pos         (14U)

+#define EXTI_IMR1_IM14_Msk         (0x1UL << EXTI_IMR1_IM14_Pos)               /*!< 0x00004000 */

+#define EXTI_IMR1_IM14             EXTI_IMR1_IM14_Msk                          /*!< Interrupt Mask on line 14 */

+#define EXTI_IMR1_IM15_Pos         (15U)

+#define EXTI_IMR1_IM15_Msk         (0x1UL << EXTI_IMR1_IM15_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR1_IM15             EXTI_IMR1_IM15_Msk                          /*!< Interrupt Mask on line 15 */

+#define EXTI_IMR1_IM16_Pos         (16U)

+#define EXTI_IMR1_IM16_Msk         (0x1UL << EXTI_IMR1_IM16_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR1_IM16             EXTI_IMR1_IM16_Msk                          /*!< Interrupt Mask on line 16 */

+#define EXTI_IMR1_IM17_Pos         (17U)

+#define EXTI_IMR1_IM17_Msk         (0x1UL << EXTI_IMR1_IM17_Pos)               /*!< 0x00020000 */

+#define EXTI_IMR1_IM17             EXTI_IMR1_IM17_Msk                          /*!< Interrupt Mask on line 17 */

+#define EXTI_IMR1_IM18_Pos         (18U)

+#define EXTI_IMR1_IM18_Msk         (0x1UL << EXTI_IMR1_IM18_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR1_IM18             EXTI_IMR1_IM18_Msk                          /*!< Interrupt Mask on line 18 */

+#define EXTI_IMR1_IM19_Pos         (19U)

+#define EXTI_IMR1_IM19_Msk         (0x1UL << EXTI_IMR1_IM19_Pos)               /*!< 0x00080000 */

+#define EXTI_IMR1_IM19             EXTI_IMR1_IM19_Msk                          /*!< Interrupt Mask on line 19 */

+#define EXTI_IMR1_IM20_Pos         (20U)

+#define EXTI_IMR1_IM20_Msk         (0x1UL << EXTI_IMR1_IM20_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR1_IM20             EXTI_IMR1_IM20_Msk                          /*!< Interrupt Mask on line 20 */

+#define EXTI_IMR1_IM21_Pos         (21U)

+#define EXTI_IMR1_IM21_Msk         (0x1UL << EXTI_IMR1_IM21_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR1_IM21             EXTI_IMR1_IM21_Msk                          /*!< Interrupt Mask on line 21 */

+#define EXTI_IMR1_IM22_Pos         (22U)

+#define EXTI_IMR1_IM22_Msk         (0x1UL << EXTI_IMR1_IM22_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR1_IM22             EXTI_IMR1_IM22_Msk                          /*!< Interrupt Mask on line 22 */

+#define EXTI_IMR1_IM23_Pos         (23U)

+#define EXTI_IMR1_IM23_Msk         (0x1UL << EXTI_IMR1_IM23_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR1_IM23             EXTI_IMR1_IM23_Msk                          /*!< Interrupt Mask on line 23 */

+#define EXTI_IMR1_IM24_Pos         (24U)

+#define EXTI_IMR1_IM24_Msk         (0x1UL << EXTI_IMR1_IM24_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR1_IM24             EXTI_IMR1_IM24_Msk                          /*!< Interrupt Mask on line 24 */

+#define EXTI_IMR1_IM25_Pos         (25U)

+#define EXTI_IMR1_IM25_Msk         (0x1UL << EXTI_IMR1_IM25_Pos)               /*!< 0x02000000 */

+#define EXTI_IMR1_IM25             EXTI_IMR1_IM25_Msk                          /*!< Interrupt Mask on line 25 */

+#define EXTI_IMR1_IM26_Pos         (26U)

+#define EXTI_IMR1_IM26_Msk         (0x1UL << EXTI_IMR1_IM26_Pos)               /*!< 0x04000000 */

+#define EXTI_IMR1_IM26             EXTI_IMR1_IM26_Msk                          /*!< Interrupt Mask on line 26 */

+#define EXTI_IMR1_IM27_Pos         (27U)

+#define EXTI_IMR1_IM27_Msk         (0x1UL << EXTI_IMR1_IM27_Pos)               /*!< 0x08000000 */

+#define EXTI_IMR1_IM27             EXTI_IMR1_IM27_Msk                          /*!< Interrupt Mask on line 27 */

+#define EXTI_IMR1_IM28_Pos         (28U)

+#define EXTI_IMR1_IM28_Msk         (0x1UL << EXTI_IMR1_IM28_Pos)               /*!< 0x10000000 */

+#define EXTI_IMR1_IM28             EXTI_IMR1_IM28_Msk                          /*!< Interrupt Mask on line 28 */

+#define EXTI_IMR1_IM29_Pos         (29U)

+#define EXTI_IMR1_IM29_Msk         (0x1UL << EXTI_IMR1_IM29_Pos)               /*!< 0x20000000 */

+#define EXTI_IMR1_IM29             EXTI_IMR1_IM29_Msk                          /*!< Interrupt Mask on line 29 */

+#define EXTI_IMR1_IM30_Pos         (30U)

+#define EXTI_IMR1_IM30_Msk         (0x1UL << EXTI_IMR1_IM30_Pos)               /*!< 0x40000000 */

+#define EXTI_IMR1_IM30             EXTI_IMR1_IM30_Msk                          /*!< Interrupt Mask on line 30 */

+#define EXTI_IMR1_IM31_Pos         (31U)

+#define EXTI_IMR1_IM31_Msk         (0x1UL << EXTI_IMR1_IM31_Pos)               /*!< 0x80000000 */

+#define EXTI_IMR1_IM31             EXTI_IMR1_IM31_Msk                          /*!< Interrupt Mask on line 31 */

+

+/*******************  Bit definition for EXTI_EMR1 register  *******************/

+#define EXTI_EMR1_EM_Pos           (0U)

+#define EXTI_EMR1_EM_Msk           (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)          /*!< 0xFFFFFFFF */

+#define EXTI_EMR1_EM               EXTI_EMR1_EM_Msk                            /*!< Event Mask */

+#define EXTI_EMR1_EM0_Pos          (0U)

+#define EXTI_EMR1_EM0_Msk          (0x1UL << EXTI_EMR1_EM0_Pos)                /*!< 0x00000001 */

+#define EXTI_EMR1_EM0              EXTI_EMR1_EM0_Msk                           /*!< Event Mask on line 0 */

+#define EXTI_EMR1_EM1_Pos          (1U)

+#define EXTI_EMR1_EM1_Msk          (0x1UL << EXTI_EMR1_EM1_Pos)                /*!< 0x00000002 */

+#define EXTI_EMR1_EM1              EXTI_EMR1_EM1_Msk                           /*!< Event Mask on line 1 */

+#define EXTI_EMR1_EM2_Pos          (2U)

+#define EXTI_EMR1_EM2_Msk          (0x1UL << EXTI_EMR1_EM2_Pos)                /*!< 0x00000004 */

+#define EXTI_EMR1_EM2              EXTI_EMR1_EM2_Msk                           /*!< Event Mask on line 2 */

+#define EXTI_EMR1_EM3_Pos          (3U)

+#define EXTI_EMR1_EM3_Msk          (0x1UL << EXTI_EMR1_EM3_Pos)                /*!< 0x00000008 */

+#define EXTI_EMR1_EM3              EXTI_EMR1_EM3_Msk                           /*!< Event Mask on line 3 */

+#define EXTI_EMR1_EM4_Pos          (4U)

+#define EXTI_EMR1_EM4_Msk          (0x1UL << EXTI_EMR1_EM4_Pos)                /*!< 0x00000010 */

+#define EXTI_EMR1_EM4              EXTI_EMR1_EM4_Msk                           /*!< Event Mask on line 4 */

+#define EXTI_EMR1_EM5_Pos          (5U)

+#define EXTI_EMR1_EM5_Msk          (0x1UL << EXTI_EMR1_EM5_Pos)                /*!< 0x00000020 */

+#define EXTI_EMR1_EM5              EXTI_EMR1_EM5_Msk                           /*!< Event Mask on line 5 */

+#define EXTI_EMR1_EM6_Pos          (6U)

+#define EXTI_EMR1_EM6_Msk          (0x1UL << EXTI_EMR1_EM6_Pos)                /*!< 0x00000040 */

+#define EXTI_EMR1_EM6              EXTI_EMR1_EM6_Msk                           /*!< Event Mask on line 6 */

+#define EXTI_EMR1_EM7_Pos          (7U)

+#define EXTI_EMR1_EM7_Msk          (0x1UL << EXTI_EMR1_EM7_Pos)                /*!< 0x00000080 */

+#define EXTI_EMR1_EM7              EXTI_EMR1_EM7_Msk                           /*!< Event Mask on line 7 */

+#define EXTI_EMR1_EM8_Pos          (8U)

+#define EXTI_EMR1_EM8_Msk          (0x1UL << EXTI_EMR1_EM8_Pos)                /*!< 0x00000100 */

+#define EXTI_EMR1_EM8              EXTI_EMR1_EM8_Msk                           /*!< Event Mask on line 8 */

+#define EXTI_EMR1_EM9_Pos          (9U)

+#define EXTI_EMR1_EM9_Msk          (0x1UL << EXTI_EMR1_EM9_Pos)                /*!< 0x00000200 */

+#define EXTI_EMR1_EM9              EXTI_EMR1_EM9_Msk                           /*!< Event Mask on line 9 */

+#define EXTI_EMR1_EM10_Pos         (10U)

+#define EXTI_EMR1_EM10_Msk         (0x1UL << EXTI_EMR1_EM10_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR1_EM10             EXTI_EMR1_EM10_Msk                          /*!< Event Mask on line 10 */

+#define EXTI_EMR1_EM11_Pos         (11U)

+#define EXTI_EMR1_EM11_Msk         (0x1UL << EXTI_EMR1_EM11_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR1_EM11             EXTI_EMR1_EM11_Msk                          /*!< Event Mask on line 11 */

+#define EXTI_EMR1_EM12_Pos         (12U)

+#define EXTI_EMR1_EM12_Msk         (0x1UL << EXTI_EMR1_EM12_Pos)               /*!< 0x00001000 */

+#define EXTI_EMR1_EM12             EXTI_EMR1_EM12_Msk                          /*!< Event Mask on line 12 */

+#define EXTI_EMR1_EM13_Pos         (13U)

+#define EXTI_EMR1_EM13_Msk         (0x1UL << EXTI_EMR1_EM13_Pos)               /*!< 0x00002000 */

+#define EXTI_EMR1_EM13             EXTI_EMR1_EM13_Msk                          /*!< Event Mask on line 13 */

+#define EXTI_EMR1_EM14_Pos         (14U)

+#define EXTI_EMR1_EM14_Msk         (0x1UL << EXTI_EMR1_EM14_Pos)               /*!< 0x00004000 */

+#define EXTI_EMR1_EM14             EXTI_EMR1_EM14_Msk                          /*!< Event Mask on line 14 */

+#define EXTI_EMR1_EM15_Pos         (15U)

+#define EXTI_EMR1_EM15_Msk         (0x1UL << EXTI_EMR1_EM15_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR1_EM15             EXTI_EMR1_EM15_Msk                          /*!< Event Mask on line 15 */

+#define EXTI_EMR1_EM16_Pos         (16U)

+#define EXTI_EMR1_EM16_Msk         (0x1UL << EXTI_EMR1_EM16_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR1_EM16             EXTI_EMR1_EM16_Msk                          /*!< Event Mask on line 16 */

+#define EXTI_EMR1_EM17_Pos         (17U)

+#define EXTI_EMR1_EM17_Msk         (0x1UL << EXTI_EMR1_EM17_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR1_EM17             EXTI_EMR1_EM17_Msk                          /*!< Event Mask on line 17 */

+#define EXTI_EMR1_EM18_Pos         (18U)

+#define EXTI_EMR1_EM18_Msk         (0x1UL << EXTI_EMR1_EM18_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR1_EM18             EXTI_EMR1_EM18_Msk                          /*!< Event Mask on line 18 */

+#define EXTI_EMR1_EM20_Pos         (20U)

+#define EXTI_EMR1_EM20_Msk         (0x1UL << EXTI_EMR1_EM20_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR1_EM20             EXTI_EMR1_EM20_Msk                          /*!< Event Mask on line 20 */

+#define EXTI_EMR1_EM21_Pos         (21U)

+#define EXTI_EMR1_EM21_Msk         (0x1UL << EXTI_EMR1_EM21_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR1_EM21             EXTI_EMR1_EM21_Msk                          /*!< Event Mask on line 21 */

+#define EXTI_EMR1_EM22_Pos         (22U)

+#define EXTI_EMR1_EM22_Msk         (0x1UL << EXTI_EMR1_EM22_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR1_EM22             EXTI_EMR1_EM22_Msk                          /*!< Event Mask on line 22 */

+#define EXTI_EMR1_EM23_Pos         (23U)

+#define EXTI_EMR1_EM23_Msk         (0x1UL << EXTI_EMR1_EM23_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR1_EM23             EXTI_EMR1_EM23_Msk                          /*!< Event Mask on line 23 */

+#define EXTI_EMR1_EM24_Pos         (24U)

+#define EXTI_EMR1_EM24_Msk         (0x1UL << EXTI_EMR1_EM24_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR1_EM24             EXTI_EMR1_EM24_Msk                          /*!< Event Mask on line 24 */

+#define EXTI_EMR1_EM25_Pos         (25U)

+#define EXTI_EMR1_EM25_Msk         (0x1UL << EXTI_EMR1_EM25_Pos)               /*!< 0x02000000 */

+#define EXTI_EMR1_EM25             EXTI_EMR1_EM25_Msk                          /*!< Event Mask on line 25 */

+#define EXTI_EMR1_EM26_Pos         (26U)

+#define EXTI_EMR1_EM26_Msk         (0x1UL << EXTI_EMR1_EM26_Pos)               /*!< 0x04000000 */

+#define EXTI_EMR1_EM26             EXTI_EMR1_EM26_Msk                          /*!< Event Mask on line 26 */

+#define EXTI_EMR1_EM27_Pos         (27U)

+#define EXTI_EMR1_EM27_Msk         (0x1UL << EXTI_EMR1_EM27_Pos)               /*!< 0x08000000 */

+#define EXTI_EMR1_EM27             EXTI_EMR1_EM27_Msk                          /*!< Event Mask on line 27 */

+#define EXTI_EMR1_EM28_Pos         (28U)

+#define EXTI_EMR1_EM28_Msk         (0x1UL << EXTI_EMR1_EM28_Pos)               /*!< 0x10000000 */

+#define EXTI_EMR1_EM28             EXTI_EMR1_EM28_Msk                          /*!< Event Mask on line 28 */

+#define EXTI_EMR1_EM29_Pos         (29U)

+#define EXTI_EMR1_EM29_Msk         (0x1UL << EXTI_EMR1_EM29_Pos)               /*!< 0x20000000 */

+#define EXTI_EMR1_EM29             EXTI_EMR1_EM29_Msk                          /*!< Event Mask on line 29 */

+#define EXTI_EMR1_EM30_Pos         (30U)

+#define EXTI_EMR1_EM30_Msk         (0x1UL << EXTI_EMR1_EM30_Pos)               /*!< 0x40000000 */

+#define EXTI_EMR1_EM30             EXTI_EMR1_EM30_Msk                          /*!< Event Mask on line 30 */

+#define EXTI_EMR1_EM31_Pos         (31U)

+#define EXTI_EMR1_EM31_Msk         (0x1UL << EXTI_EMR1_EM31_Pos)               /*!< 0x80000000 */

+#define EXTI_EMR1_EM31             EXTI_EMR1_EM31_Msk                          /*!< Event Mask on line 31 */

+

+/*******************  Bit definition for EXTI_PR1 register  ********************/

+#define EXTI_PR1_PR_Pos            (0U)

+#define EXTI_PR1_PR_Msk            (0x3FFFFFUL << EXTI_PR1_PR_Pos)             /*!< 0x003FFFFF */

+#define EXTI_PR1_PR                EXTI_PR1_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR1_PR0_Pos           (0U)

+#define EXTI_PR1_PR0_Msk           (0x1UL << EXTI_PR1_PR0_Pos)                 /*!< 0x00000001 */

+#define EXTI_PR1_PR0               EXTI_PR1_PR0_Msk                            /*!< Pending bit for line 0 */

+#define EXTI_PR1_PR1_Pos           (1U)

+#define EXTI_PR1_PR1_Msk           (0x1UL << EXTI_PR1_PR1_Pos)                 /*!< 0x00000002 */

+#define EXTI_PR1_PR1               EXTI_PR1_PR1_Msk                            /*!< Pending bit for line 1 */

+#define EXTI_PR1_PR2_Pos           (2U)

+#define EXTI_PR1_PR2_Msk           (0x1UL << EXTI_PR1_PR2_Pos)                 /*!< 0x00000004 */

+#define EXTI_PR1_PR2               EXTI_PR1_PR2_Msk                            /*!< Pending bit for line 2 */

+#define EXTI_PR1_PR3_Pos           (3U)

+#define EXTI_PR1_PR3_Msk           (0x1UL << EXTI_PR1_PR3_Pos)                 /*!< 0x00000008 */

+#define EXTI_PR1_PR3               EXTI_PR1_PR3_Msk                            /*!< Pending bit for line 3 */

+#define EXTI_PR1_PR4_Pos           (4U)

+#define EXTI_PR1_PR4_Msk           (0x1UL << EXTI_PR1_PR4_Pos)                 /*!< 0x00000010 */

+#define EXTI_PR1_PR4               EXTI_PR1_PR4_Msk                            /*!< Pending bit for line 4 */

+#define EXTI_PR1_PR5_Pos           (5U)

+#define EXTI_PR1_PR5_Msk           (0x1UL << EXTI_PR1_PR5_Pos)                 /*!< 0x00000020 */

+#define EXTI_PR1_PR5               EXTI_PR1_PR5_Msk                            /*!< Pending bit for line 5 */

+#define EXTI_PR1_PR6_Pos           (6U)

+#define EXTI_PR1_PR6_Msk           (0x1UL << EXTI_PR1_PR6_Pos)                 /*!< 0x00000040 */

+#define EXTI_PR1_PR6               EXTI_PR1_PR6_Msk                            /*!< Pending bit for line 6 */

+#define EXTI_PR1_PR7_Pos           (7U)

+#define EXTI_PR1_PR7_Msk           (0x1UL << EXTI_PR1_PR7_Pos)                 /*!< 0x00000080 */

+#define EXTI_PR1_PR7               EXTI_PR1_PR7_Msk                            /*!< Pending bit for line 7 */

+#define EXTI_PR1_PR8_Pos           (8U)

+#define EXTI_PR1_PR8_Msk           (0x1UL << EXTI_PR1_PR8_Pos)                 /*!< 0x00000100 */

+#define EXTI_PR1_PR8               EXTI_PR1_PR8_Msk                            /*!< Pending bit for line 8 */

+#define EXTI_PR1_PR9_Pos           (9U)

+#define EXTI_PR1_PR9_Msk           (0x1UL << EXTI_PR1_PR9_Pos)                 /*!< 0x00000200 */

+#define EXTI_PR1_PR9               EXTI_PR1_PR9_Msk                            /*!< Pending bit for line 9 */

+#define EXTI_PR1_PR10_Pos          (10U)

+#define EXTI_PR1_PR10_Msk          (0x1UL << EXTI_PR1_PR10_Pos)                /*!< 0x00000400 */

+#define EXTI_PR1_PR10              EXTI_PR1_PR10_Msk                           /*!< Pending bit for line 10 */

+#define EXTI_PR1_PR11_Pos          (11U)

+#define EXTI_PR1_PR11_Msk          (0x1UL << EXTI_PR1_PR11_Pos)                /*!< 0x00000800 */

+#define EXTI_PR1_PR11              EXTI_PR1_PR11_Msk                           /*!< Pending bit for line 11 */

+#define EXTI_PR1_PR12_Pos          (12U)

+#define EXTI_PR1_PR12_Msk          (0x1UL << EXTI_PR1_PR12_Pos)                /*!< 0x00001000 */

+#define EXTI_PR1_PR12              EXTI_PR1_PR12_Msk                           /*!< Pending bit for line 12 */

+#define EXTI_PR1_PR13_Pos          (13U)

+#define EXTI_PR1_PR13_Msk          (0x1UL << EXTI_PR1_PR13_Pos)                /*!< 0x00002000 */

+#define EXTI_PR1_PR13              EXTI_PR1_PR13_Msk                           /*!< Pending bit for line 13 */

+#define EXTI_PR1_PR14_Pos          (14U)

+#define EXTI_PR1_PR14_Msk          (0x1UL << EXTI_PR1_PR14_Pos)                /*!< 0x00004000 */

+#define EXTI_PR1_PR14              EXTI_PR1_PR14_Msk                           /*!< Pending bit for line 14 */

+#define EXTI_PR1_PR15_Pos          (15U)

+#define EXTI_PR1_PR15_Msk          (0x1UL << EXTI_PR1_PR15_Pos)                /*!< 0x00008000 */

+#define EXTI_PR1_PR15              EXTI_PR1_PR15_Msk                           /*!< Pending bit for line 15 */

+#define EXTI_PR1_PR16_Pos          (16U)

+#define EXTI_PR1_PR16_Msk          (0x1UL << EXTI_PR1_PR16_Pos)                /*!< 0x00010000 */

+#define EXTI_PR1_PR16              EXTI_PR1_PR16_Msk                           /*!< Pending bit for line 16 */

+#define EXTI_PR1_PR17_Pos          (17U)

+#define EXTI_PR1_PR17_Msk          (0x1UL << EXTI_PR1_PR17_Pos)                /*!< 0x00020000 */

+#define EXTI_PR1_PR17              EXTI_PR1_PR17_Msk                           /*!< Pending bit for line 17 */

+#define EXTI_PR1_PR18_Pos          (18U)

+#define EXTI_PR1_PR18_Msk          (0x1UL << EXTI_PR1_PR18_Pos)                /*!< 0x00040000 */

+#define EXTI_PR1_PR18              EXTI_PR1_PR18_Msk                           /*!< Pending bit for line 18 */

+#define EXTI_PR1_PR19_Pos          (19U)

+#define EXTI_PR1_PR19_Msk          (0x1UL << EXTI_PR1_PR19_Pos)                /*!< 0x00080000 */

+#define EXTI_PR1_PR19              EXTI_PR1_PR19_Msk                           /*!< Pending bit for line 19 */

+#define EXTI_PR1_PR20_Pos          (20U)

+#define EXTI_PR1_PR20_Msk          (0x1UL << EXTI_PR1_PR20_Pos)                /*!< 0x00100000 */

+#define EXTI_PR1_PR20              EXTI_PR1_PR20_Msk                           /*!< Pending bit for line 20 */

+#define EXTI_PR1_PR21_Pos          (21U)

+#define EXTI_PR1_PR21_Msk          (0x1UL << EXTI_PR1_PR21_Pos)                /*!< 0x00200000 */

+#define EXTI_PR1_PR21              EXTI_PR1_PR21_Msk                           /*!< Pending bit for line 21 */

+

+/*******************  Bit definition for EXTI_IMR2 register  *******************/

+#define EXTI_IMR2_IM_Pos           (0U)

+#define EXTI_IMR2_IM_Msk           (0xFFFF8FFFUL << EXTI_IMR2_IM_Pos)          /*!< 0xFFFF8FFF */

+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            /*!< Interrupt Mask            */

+#define EXTI_IMR2_IM32_Pos         (0U)

+#define EXTI_IMR2_IM32_Msk         (0x1UL << EXTI_IMR2_IM32_Pos)               /*!< 0x00000001 */

+#define EXTI_IMR2_IM32             EXTI_IMR2_IM32_Msk                          /*!< Interrupt Mask on line 32 */

+#define EXTI_IMR2_IM33_Pos         (1U)

+#define EXTI_IMR2_IM33_Msk         (0x1UL << EXTI_IMR2_IM33_Pos)               /*!< 0x00000002 */

+#define EXTI_IMR2_IM33             EXTI_IMR2_IM33_Msk                          /*!< Interrupt Mask on line 33 */

+#define EXTI_IMR2_IM34_Pos         (2U)

+#define EXTI_IMR2_IM34_Msk         (0x1UL << EXTI_IMR2_IM34_Pos)               /*!< 0x00000004 */

+#define EXTI_IMR2_IM34             EXTI_IMR2_IM34_Msk                          /*!< Interrupt Mask on line 34 */

+#define EXTI_IMR2_IM35_Pos         (3U)

+#define EXTI_IMR2_IM35_Msk         (0x1UL << EXTI_IMR2_IM35_Pos)               /*!< 0x00000008 */

+#define EXTI_IMR2_IM35             EXTI_IMR2_IM35_Msk                          /*!< Interrupt Mask on line 35 */

+#define EXTI_IMR2_IM36_Pos         (4U)

+#define EXTI_IMR2_IM36_Msk         (0x1UL << EXTI_IMR2_IM36_Pos)               /*!< 0x00000010 */

+#define EXTI_IMR2_IM36             EXTI_IMR2_IM36_Msk                          /*!< Interrupt Mask on line 36 */

+#define EXTI_IMR2_IM37_Pos         (5U)

+#define EXTI_IMR2_IM37_Msk         (0x1UL << EXTI_IMR2_IM37_Pos)               /*!< 0x00000020 */

+#define EXTI_IMR2_IM37             EXTI_IMR2_IM37_Msk                          /*!< Interrupt Mask on line 37 */

+#define EXTI_IMR2_IM38_Pos         (6U)

+#define EXTI_IMR2_IM38_Msk         (0x1UL << EXTI_IMR2_IM38_Pos)               /*!< 0x00000040 */

+#define EXTI_IMR2_IM38             EXTI_IMR2_IM38_Msk                          /*!< Interrupt Mask on line 38 */

+#define EXTI_IMR2_IM39_Pos         (7U)

+#define EXTI_IMR2_IM39_Msk         (0x1UL << EXTI_IMR2_IM39_Pos)               /*!< 0x00000080 */

+#define EXTI_IMR2_IM39             EXTI_IMR2_IM39_Msk                          /*!< Interrupt Mask on line 39 */

+#define EXTI_IMR2_IM40_Pos         (8U)

+#define EXTI_IMR2_IM40_Msk         (0x1UL << EXTI_IMR2_IM40_Pos)               /*!< 0x00000100 */

+#define EXTI_IMR2_IM40             EXTI_IMR2_IM40_Msk                          /*!< Interrupt Mask on line 40 */

+#define EXTI_IMR2_IM41_Pos         (9U)

+#define EXTI_IMR2_IM41_Msk         (0x1UL << EXTI_IMR2_IM41_Pos)               /*!< 0x00000200 */

+#define EXTI_IMR2_IM41             EXTI_IMR2_IM41_Msk                          /*!< Interrupt Mask on line 41 */

+#define EXTI_IMR2_IM42_Pos         (10U)

+#define EXTI_IMR2_IM42_Msk         (0x1UL << EXTI_IMR2_IM42_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR2_IM42             EXTI_IMR2_IM42_Msk                          /*!< Interrupt Mask on line 42 */

+#define EXTI_IMR2_IM43_Pos         (11U)

+#define EXTI_IMR2_IM43_Msk         (0x1UL << EXTI_IMR2_IM43_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR2_IM43             EXTI_IMR2_IM43_Msk                          /*!< Interrupt Mask on line 43 */

+#define EXTI_IMR2_IM47_Pos         (15U)

+#define EXTI_IMR2_IM47_Msk         (0x1UL << EXTI_IMR2_IM47_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR2_IM47             EXTI_IMR2_IM47_Msk                          /*!< Interrupt Mask on line 47 */

+#define EXTI_IMR2_IM48_Pos         (16U)

+#define EXTI_IMR2_IM48_Msk         (0x1UL << EXTI_IMR2_IM48_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR2_IM48             EXTI_IMR2_IM48_Msk                          /*!< Interrupt Mask on line 48 */

+#define EXTI_IMR2_IM49_Pos         (17U)

+#define EXTI_IMR2_IM49_Msk         (0x1UL << EXTI_IMR2_IM49_Pos)               /*!< 0x00020000 */

+#define EXTI_IMR2_IM49             EXTI_IMR2_IM49_Msk                          /*!< Interrupt Mask on line 49 */

+#define EXTI_IMR2_IM50_Pos         (18U)

+#define EXTI_IMR2_IM50_Msk         (0x1UL << EXTI_IMR2_IM50_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR2_IM50             EXTI_IMR2_IM50_Msk                          /*!< Interrupt Mask on line 50 */

+#define EXTI_IMR2_IM51_Pos         (19U)

+#define EXTI_IMR2_IM51_Msk         (0x1UL << EXTI_IMR2_IM51_Pos)               /*!< 0x00080000 */

+#define EXTI_IMR2_IM51             EXTI_IMR2_IM51_Msk                          /*!< Interrupt Mask on line 51 */

+#define EXTI_IMR2_IM52_Pos         (20U)

+#define EXTI_IMR2_IM52_Msk         (0x1UL << EXTI_IMR2_IM52_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR2_IM52             EXTI_IMR2_IM52_Msk                          /*!< Interrupt Mask on line 52 */

+#define EXTI_IMR2_IM53_Pos         (21U)

+#define EXTI_IMR2_IM53_Msk         (0x1UL << EXTI_IMR2_IM53_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR2_IM53             EXTI_IMR2_IM53_Msk                          /*!< Interrupt Mask on line 53 */

+#define EXTI_IMR2_IM54_Pos         (22U)

+#define EXTI_IMR2_IM54_Msk         (0x1UL << EXTI_IMR2_IM54_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR2_IM54             EXTI_IMR2_IM54_Msk                          /*!< Interrupt Mask on line 54 */

+#define EXTI_IMR2_IM55_Pos         (23U)

+#define EXTI_IMR2_IM55_Msk         (0x1UL << EXTI_IMR2_IM55_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR2_IM55             EXTI_IMR2_IM55_Msk                          /*!< Interrupt Mask on line 55 */

+#define EXTI_IMR2_IM56_Pos         (24U)

+#define EXTI_IMR2_IM56_Msk         (0x1UL << EXTI_IMR2_IM56_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR2_IM56             EXTI_IMR2_IM56_Msk                          /*!< Interrupt Mask on line 56 */

+#define EXTI_IMR2_IM57_Pos         (25U)

+#define EXTI_IMR2_IM57_Msk         (0x1UL << EXTI_IMR2_IM57_Pos)               /*!< 0x02000000 */

+#define EXTI_IMR2_IM57             EXTI_IMR2_IM57_Msk                          /*!< Interrupt Mask on line 57 */

+#define EXTI_IMR2_IM58_Pos         (26U)

+#define EXTI_IMR2_IM58_Msk         (0x1UL << EXTI_IMR2_IM58_Pos)               /*!< 0x04000000 */

+#define EXTI_IMR2_IM58             EXTI_IMR2_IM58_Msk                          /*!< Interrupt Mask on line 58 */

+#define EXTI_IMR2_IM59_Pos         (27U)

+#define EXTI_IMR2_IM59_Msk         (0x1UL << EXTI_IMR2_IM59_Pos)               /*!< 0x08000000 */

+#define EXTI_IMR2_IM59             EXTI_IMR2_IM59_Msk                          /*!< Interrupt Mask on line 59 */

+#define EXTI_IMR2_IM60_Pos         (28U)

+#define EXTI_IMR2_IM60_Msk         (0x1UL << EXTI_IMR2_IM60_Pos)               /*!< 0x10000000 */

+#define EXTI_IMR2_IM60             EXTI_IMR2_IM60_Msk                          /*!< Interrupt Mask on line 60 */

+#define EXTI_IMR2_IM61_Pos         (29U)

+#define EXTI_IMR2_IM61_Msk         (0x1UL << EXTI_IMR2_IM61_Pos)               /*!< 0x20000000 */

+#define EXTI_IMR2_IM61             EXTI_IMR2_IM61_Msk                          /*!< Interrupt Mask on line 61 */

+#define EXTI_IMR2_IM62_Pos         (30U)

+#define EXTI_IMR2_IM62_Msk         (0x1UL << EXTI_IMR2_IM62_Pos)               /*!< 0x40000000 */

+#define EXTI_IMR2_IM62             EXTI_IMR2_IM62_Msk                          /*!< Interrupt Mask on line 62 */

+#define EXTI_IMR2_IM63_Pos         (31U)

+#define EXTI_IMR2_IM63_Msk         (0x1UL << EXTI_IMR2_IM63_Pos)               /*!< 0x80000000 */

+#define EXTI_IMR2_IM63             EXTI_IMR2_IM63_Msk                          /*!< Interrupt Mask on line 63 */

+

+/*******************  Bit definition for EXTI_EMR2 register  *******************/

+#define EXTI_EMR2_EM_Pos           (0U)

+#define EXTI_EMR2_EM_Msk           (0xFFFF8FFFUL << EXTI_EMR2_EM_Pos)          /*!< 0xFFFF8FFF */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            /*!< Event Mask           */

+#define EXTI_EMR2_EM32_Pos         (0U)

+#define EXTI_EMR2_EM32_Msk         (0x1UL << EXTI_EMR2_EM32_Pos)               /*!< 0x00000001 */

+#define EXTI_EMR2_EM32             EXTI_EMR2_EM32_Msk                          /*!< Event Mask on line 32*/

+#define EXTI_EMR2_EM33_Pos         (1U)

+#define EXTI_EMR2_EM33_Msk         (0x1UL << EXTI_EMR2_EM33_Pos)               /*!< 0x00000002 */

+#define EXTI_EMR2_EM33             EXTI_EMR2_EM33_Msk                          /*!< Event Mask on line 33*/

+#define EXTI_EMR2_EM34_Pos         (2U)

+#define EXTI_EMR2_EM34_Msk         (0x1UL << EXTI_EMR2_EM34_Pos)               /*!< 0x00000004 */

+#define EXTI_EMR2_EM34             EXTI_EMR2_EM34_Msk                          /*!< Event Mask on line 34*/

+#define EXTI_EMR2_EM35_Pos         (3U)

+#define EXTI_EMR2_EM35_Msk         (0x1UL << EXTI_EMR2_EM35_Pos)               /*!< 0x00000008 */

+#define EXTI_EMR2_EM35             EXTI_EMR2_EM35_Msk                          /*!< Event Mask on line 35*/

+#define EXTI_EMR2_EM36_Pos         (4U)

+#define EXTI_EMR2_EM36_Msk         (0x1UL << EXTI_EMR2_EM36_Pos)               /*!< 0x00000010 */

+#define EXTI_EMR2_EM36             EXTI_EMR2_EM36_Msk                          /*!< Event Mask on line 36*/

+#define EXTI_EMR2_EM37_Pos         (5U)

+#define EXTI_EMR2_EM37_Msk         (0x1UL << EXTI_EMR2_EM37_Pos)               /*!< 0x00000020 */

+#define EXTI_EMR2_EM37             EXTI_EMR2_EM37_Msk                          /*!< Event Mask on line 37*/

+#define EXTI_EMR2_EM38_Pos         (6U)

+#define EXTI_EMR2_EM38_Msk         (0x1UL << EXTI_EMR2_EM38_Pos)               /*!< 0x00000040 */

+#define EXTI_EMR2_EM38             EXTI_EMR2_EM38_Msk                          /*!< Event Mask on line 38*/

+#define EXTI_EMR2_EM39_Pos         (7U)

+#define EXTI_EMR2_EM39_Msk         (0x1UL << EXTI_EMR2_EM39_Pos)               /*!< 0x00000080 */

+#define EXTI_EMR2_EM39             EXTI_EMR2_EM39_Msk                          /*!< Event Mask on line 39*/

+#define EXTI_EMR2_EM40_Pos         (8U)

+#define EXTI_EMR2_EM40_Msk         (0x1UL << EXTI_EMR2_EM40_Pos)               /*!< 0x00000100 */

+#define EXTI_EMR2_EM40             EXTI_EMR2_EM40_Msk                          /*!< Event Mask on line 40*/

+#define EXTI_EMR2_EM41_Pos         (9U)

+#define EXTI_EMR2_EM41_Msk         (0x1UL << EXTI_EMR2_EM41_Pos)               /*!< 0x00000200 */

+#define EXTI_EMR2_EM41             EXTI_EMR2_EM41_Msk                          /*!< Event Mask on line 41*/

+#define EXTI_EMR2_EM42_Pos         (10U)

+#define EXTI_EMR2_EM42_Msk         (0x1UL << EXTI_EMR2_EM42_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR2_EM42             EXTI_EMR2_EM42_Msk                          /*!< Event Mask on line 42 */

+#define EXTI_EMR2_EM43_Pos         (11U)

+#define EXTI_EMR2_EM43_Msk         (0x1UL << EXTI_EMR2_EM43_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR2_EM43             EXTI_EMR2_EM43_Msk                          /*!< Event Mask on line 43 */

+#define EXTI_EMR2_EM47_Pos         (15U)

+#define EXTI_EMR2_EM47_Msk         (0x1UL << EXTI_EMR2_EM47_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR2_EM47             EXTI_EMR2_EM47_Msk                          /*!< Event Mask on line 47 */

+#define EXTI_EMR2_EM48_Pos         (16U)

+#define EXTI_EMR2_EM48_Msk         (0x1UL << EXTI_EMR2_EM48_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR2_EM48             EXTI_EMR2_EM48_Msk                          /*!< Event Mask on line 48 */

+#define EXTI_EMR2_EM49_Pos         (17U)

+#define EXTI_EMR2_EM49_Msk         (0x1UL << EXTI_EMR2_EM49_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR2_EM49             EXTI_EMR2_EM49_Msk                          /*!< Event Mask on line 49 */

+#define EXTI_EMR2_EM50_Pos         (18U)

+#define EXTI_EMR2_EM50_Msk         (0x1UL << EXTI_EMR2_EM50_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR2_EM50             EXTI_EMR2_EM50_Msk                          /*!< Event Mask on line 50 */

+#define EXTI_EMR2_EM51_Pos         (19U)

+#define EXTI_EMR2_EM51_Msk         (0x1UL << EXTI_EMR2_EM51_Pos)               /*!< 0x00080000 */

+#define EXTI_EMR2_EM51             EXTI_EMR2_EM51_Msk                          /*!< Event Mask on line 51 */

+#define EXTI_EMR2_EM52_Pos         (20U)

+#define EXTI_EMR2_EM52_Msk         (0x1UL << EXTI_EMR2_EM52_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR2_EM52             EXTI_EMR2_EM52_Msk                          /*!< Event Mask on line 52 */

+#define EXTI_EMR2_EM53_Pos         (21U)

+#define EXTI_EMR2_EM53_Msk         (0x1UL << EXTI_EMR2_EM53_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR2_EM53             EXTI_EMR2_EM53_Msk                          /*!< Event Mask on line 53 */

+#define EXTI_EMR2_EM54_Pos         (22U)

+#define EXTI_EMR2_EM54_Msk         (0x1UL << EXTI_EMR2_EM54_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR2_EM54             EXTI_EMR2_EM54_Msk                          /*!< Event Mask on line 54 */

+#define EXTI_EMR2_EM55_Pos         (23U)

+#define EXTI_EMR2_EM55_Msk         (0x1UL << EXTI_EMR2_EM55_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR2_EM55             EXTI_EMR2_EM55_Msk                          /*!< Event Mask on line 55 */

+#define EXTI_EMR2_EM56_Pos         (24U)

+#define EXTI_EMR2_EM56_Msk         (0x1UL << EXTI_EMR2_EM56_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR2_EM56             EXTI_EMR2_EM56_Msk                          /*!< Event Mask on line 56 */

+#define EXTI_EMR2_EM57_Pos         (25U)

+#define EXTI_EMR2_EM57_Msk         (0x1UL << EXTI_EMR2_EM57_Pos)               /*!< 0x02000000 */

+#define EXTI_EMR2_EM57             EXTI_EMR2_EM57_Msk                          /*!< Event Mask on line 57 */

+#define EXTI_EMR2_EM58_Pos         (26U)

+#define EXTI_EMR2_EM58_Msk         (0x1UL << EXTI_EMR2_EM58_Pos)               /*!< 0x04000000 */

+#define EXTI_EMR2_EM58             EXTI_EMR2_EM58_Msk                          /*!< Event Mask on line 58 */

+#define EXTI_EMR2_EM59_Pos         (27U)

+#define EXTI_EMR2_EM59_Msk         (0x1UL << EXTI_EMR2_EM59_Pos)               /*!< 0x08000000 */

+#define EXTI_EMR2_EM59             EXTI_EMR2_EM59_Msk                          /*!< Event Mask on line 59 */

+#define EXTI_EMR2_EM60_Pos         (28U)

+#define EXTI_EMR2_EM60_Msk         (0x1UL << EXTI_EMR2_EM60_Pos)               /*!< 0x10000000 */

+#define EXTI_EMR2_EM60             EXTI_EMR2_EM60_Msk                          /*!< Event Mask on line 60 */

+#define EXTI_EMR2_EM61_Pos         (29U)

+#define EXTI_EMR2_EM61_Msk         (0x1UL << EXTI_EMR2_EM61_Pos)               /*!< 0x20000000 */

+#define EXTI_EMR2_EM61             EXTI_EMR2_EM61_Msk                          /*!< Event Mask on line 61 */

+#define EXTI_EMR2_EM62_Pos         (30U)

+#define EXTI_EMR2_EM62_Msk         (0x1UL << EXTI_EMR2_EM62_Pos)               /*!< 0x40000000 */

+#define EXTI_EMR2_EM62             EXTI_EMR2_EM62_Msk                          /*!< Event Mask on line 62 */

+#define EXTI_EMR2_EM63_Pos         (31U)

+#define EXTI_EMR2_EM63_Msk         (0x1UL << EXTI_EMR2_EM63_Pos)               /*!< 0x80000000 */

+#define EXTI_EMR2_EM63             EXTI_EMR2_EM63_Msk                          /*!< Event Mask on line 63 */

+

+/*******************  Bit definition for EXTI_PR2 register  ********************/

+#define EXTI_PR2_PR_Pos            (17U)

+#define EXTI_PR2_PR_Msk            (0x5UL << EXTI_PR2_PR_Pos)                  /*!< 0x000A0000 */

+#define EXTI_PR2_PR                EXTI_PR2_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR2_PR49_Pos          (17U)

+#define EXTI_PR2_PR49_Msk          (0x1UL << EXTI_PR2_PR49_Pos)                /*!< 0x00020000 */

+#define EXTI_PR2_PR49              EXTI_PR2_PR49_Msk                           /*!< Pending bit for line 49 */

+#define EXTI_PR2_PR51_Pos          (19U)

+#define EXTI_PR2_PR51_Msk          (0x1UL << EXTI_PR2_PR51_Pos)                /*!< 0x00080000 */

+#define EXTI_PR2_PR51              EXTI_PR2_PR51_Msk                           /*!< Pending bit for line 51 */

+

+/*******************  Bit definition for EXTI_IMR3 register  *******************/

+#define EXTI_IMR3_IM_Pos           (0U)

+#define EXTI_IMR3_IM_Msk           (0x001A527FFUL << EXTI_IMR3_IM_Pos)         /*!< 0x001A527FF */

+#define EXTI_IMR3_IM               EXTI_IMR3_IM_Msk                            /*!< Interrupt Mask            */

+#define EXTI_IMR3_IM64_Pos         (0U)

+#define EXTI_IMR3_IM64_Msk         (0x1UL << EXTI_IMR3_IM64_Pos)               /*!< 0x00000001 */

+#define EXTI_IMR3_IM64             EXTI_IMR3_IM64_Msk                          /*!< Interrupt Mask on line 64 */

+#define EXTI_IMR3_IM65_Pos         (1U)

+#define EXTI_IMR3_IM65_Msk         (0x1UL << EXTI_IMR3_IM65_Pos)               /*!< 0x00000002 */

+#define EXTI_IMR3_IM65             EXTI_IMR3_IM65_Msk                          /*!< Interrupt Mask on line 65 */

+#define EXTI_IMR3_IM66_Pos         (2U)

+#define EXTI_IMR3_IM66_Msk         (0x1UL << EXTI_IMR3_IM66_Pos)               /*!< 0x00000004 */

+#define EXTI_IMR3_IM66             EXTI_IMR3_IM66_Msk                          /*!< Interrupt Mask on line 66 */

+#define EXTI_IMR3_IM67_Pos         (3U)

+#define EXTI_IMR3_IM67_Msk         (0x1UL << EXTI_IMR3_IM67_Pos)               /*!< 0x00000008 */

+#define EXTI_IMR3_IM67             EXTI_IMR3_IM67_Msk                          /*!< Interrupt Mask on line 67 */

+#define EXTI_IMR3_IM68_Pos         (4U)

+#define EXTI_IMR3_IM68_Msk         (0x1UL << EXTI_IMR3_IM68_Pos)               /*!< 0x00000010 */

+#define EXTI_IMR3_IM68             EXTI_IMR3_IM68_Msk                          /*!< Interrupt Mask on line 68 */

+#define EXTI_IMR3_IM69_Pos         (5U)

+#define EXTI_IMR3_IM69_Msk         (0x1UL << EXTI_IMR3_IM69_Pos)               /*!< 0x00000020 */

+#define EXTI_IMR3_IM69             EXTI_IMR3_IM69_Msk                          /*!< Interrupt Mask on line 69 */

+#define EXTI_IMR3_IM70_Pos         (6U)

+#define EXTI_IMR3_IM70_Msk         (0x1UL << EXTI_IMR3_IM70_Pos)               /*!< 0x00000040 */

+#define EXTI_IMR3_IM70             EXTI_IMR3_IM70_Msk                          /*!< Interrupt Mask on line 70 */

+#define EXTI_IMR3_IM71_Pos         (7U)

+#define EXTI_IMR3_IM71_Msk         (0x1UL << EXTI_IMR3_IM71_Pos)               /*!< 0x00000080 */

+#define EXTI_IMR3_IM71             EXTI_IMR3_IM71_Msk                          /*!< Interrupt Mask on line 71 */

+#define EXTI_IMR3_IM72_Pos         (8U)

+#define EXTI_IMR3_IM72_Msk         (0x1UL << EXTI_IMR3_IM72_Pos)               /*!< 0x00000100 */

+#define EXTI_IMR3_IM72             EXTI_IMR3_IM72_Msk                          /*!< Interrupt Mask on line 72 */

+#define EXTI_IMR3_IM73_Pos         (9U)

+#define EXTI_IMR3_IM73_Msk         (0x1UL << EXTI_IMR3_IM73_Pos)               /*!< 0x00000200 */

+#define EXTI_IMR3_IM73             EXTI_IMR3_IM73_Msk                          /*!< Interrupt Mask on line 73 */

+#define EXTI_IMR3_IM74_Pos         (10U)

+#define EXTI_IMR3_IM74_Msk         (0x1UL << EXTI_IMR3_IM74_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR3_IM74             EXTI_IMR3_IM74_Msk                          /*!< Interrupt Mask on line 74 */

+#define EXTI_IMR3_IM77_Pos         (13U)

+#define EXTI_IMR3_IM77_Msk         (0x1UL << EXTI_IMR3_IM77_Pos)               /*!< 0x00002000 */

+#define EXTI_IMR3_IM77             EXTI_IMR3_IM77_Msk                          /*!< Interrupt Mask on line 77 */

+#define EXTI_IMR3_IM80_Pos         (16U)

+#define EXTI_IMR3_IM80_Msk         (0x1UL << EXTI_IMR3_IM80_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR3_IM80             EXTI_IMR3_IM80_Msk                          /*!< Interrupt Mask on line 80 */

+#define EXTI_IMR3_IM82_Pos         (18U)

+#define EXTI_IMR3_IM82_Msk         (0x1UL << EXTI_IMR3_IM82_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR3_IM82             EXTI_IMR3_IM82_Msk                          /*!< Interrupt Mask on line 82 */

+#define EXTI_IMR3_IM85_Pos         (21U)

+#define EXTI_IMR3_IM85_Msk         (0x1UL << EXTI_IMR3_IM85_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR3_IM85             EXTI_IMR3_IM85_Msk                          /*!< Interrupt Mask on line 85 */

+#define EXTI_IMR3_IM87_Pos         (23U)

+#define EXTI_IMR3_IM87_Msk         (0x1UL << EXTI_IMR3_IM87_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR3_IM87             EXTI_IMR3_IM87_Msk                          /*!< Interrupt Mask on line 87 */

+

+

+#define EXTI_IMR3_IM88_Pos         (24U)

+#define EXTI_IMR3_IM88_Msk         (0x1UL << EXTI_IMR3_IM88_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR3_IM88             EXTI_IMR3_IM88_Msk                          /*!< Interrupt Mask on line 88 */

+

+/*******************  Bit definition for EXTI_EMR3 register  *******************/

+#define EXTI_EMR3_EM_Pos           (0U)

+#define EXTI_EMR3_EM_Msk           (0x01A527FFUL << EXTI_EMR3_EM_Pos)          /*!< 0x01A527FF */

+#define EXTI_EMR3_EM               EXTI_EMR3_EM_Msk                            /*!< Event Mask           */

+#define EXTI_EMR3_EM64_Pos         (0U)

+#define EXTI_EMR3_EM64_Msk         (0x1UL << EXTI_EMR3_EM64_Pos)               /*!< 0x00000001 */

+#define EXTI_EMR3_EM64             EXTI_EMR3_EM64_Msk                          /*!< Event Mask on line 64*/

+#define EXTI_EMR3_EM65_Pos         (1U)

+#define EXTI_EMR3_EM65_Msk         (0x1UL << EXTI_EMR3_EM65_Pos)               /*!< 0x00000002 */

+#define EXTI_EMR3_EM65             EXTI_EMR3_EM65_Msk                          /*!< Event Mask on line 65*/

+#define EXTI_EMR3_EM66_Pos         (2U)

+#define EXTI_EMR3_EM66_Msk         (0x1UL << EXTI_EMR3_EM66_Pos)               /*!< 0x00000004 */

+#define EXTI_EMR3_EM66             EXTI_EMR3_EM66_Msk                          /*!< Event Mask on line 66*/

+#define EXTI_EMR3_EM67_Pos         (3U)

+#define EXTI_EMR3_EM67_Msk         (0x1UL << EXTI_EMR3_EM67_Pos)               /*!< 0x00000008 */

+#define EXTI_EMR3_EM67             EXTI_EMR3_EM67_Msk                          /*!< Event Mask on line 67*/

+#define EXTI_EMR3_EM68_Pos         (4U)

+#define EXTI_EMR3_EM68_Msk         (0x1UL << EXTI_EMR3_EM68_Pos)               /*!< 0x00000010 */

+#define EXTI_EMR3_EM68             EXTI_EMR3_EM68_Msk                          /*!< Event Mask on line 68*/

+#define EXTI_EMR3_EM69_Pos         (5U)

+#define EXTI_EMR3_EM69_Msk         (0x1UL << EXTI_EMR3_EM69_Pos)               /*!< 0x00000020 */

+#define EXTI_EMR3_EM69             EXTI_EMR3_EM69_Msk                          /*!< Event Mask on line 69*/

+#define EXTI_EMR3_EM70_Pos         (6U)

+#define EXTI_EMR3_EM70_Msk         (0x1UL << EXTI_EMR3_EM70_Pos)               /*!< 0x00000040 */

+#define EXTI_EMR3_EM70             EXTI_EMR3_EM70_Msk                          /*!< Event Mask on line 70*/

+#define EXTI_EMR3_EM71_Pos         (7U)

+#define EXTI_EMR3_EM71_Msk         (0x1UL << EXTI_EMR3_EM71_Pos)               /*!< 0x00000080 */

+#define EXTI_EMR3_EM71             EXTI_EMR3_EM71_Msk                          /*!< Event Mask on line 71*/

+#define EXTI_EMR3_EM72_Pos         (8U)

+#define EXTI_EMR3_EM72_Msk         (0x1UL << EXTI_EMR3_EM72_Pos)               /*!< 0x00000100 */

+#define EXTI_EMR3_EM72             EXTI_EMR3_EM72_Msk                          /*!< Event Mask on line 72*/

+#define EXTI_EMR3_EM73_Pos         (9U)

+#define EXTI_EMR3_EM73_Msk         (0x1UL << EXTI_EMR3_EM73_Pos)               /*!< 0x00000200 */

+#define EXTI_EMR3_EM73             EXTI_EMR3_EM73_Msk                          /*!< Event Mask on line 73*/

+#define EXTI_EMR3_EM74_Pos         (10U)

+#define EXTI_EMR3_EM74_Msk         (0x1UL << EXTI_EMR3_EM74_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR3_EM74             EXTI_EMR3_EM74_Msk                          /*!< Event Mask on line 74 */

+#define EXTI_EMR3_EM77_Pos         (13U)

+#define EXTI_EMR3_EM77_Msk         (0x1UL << EXTI_EMR3_EM77_Pos)               /*!< 0x00002000 */

+#define EXTI_EMR3_EM77             EXTI_EMR3_EM77_Msk                          /*!< Event Mask on line 77 */

+#define EXTI_EMR3_EM80_Pos         (16U)

+#define EXTI_EMR3_EM80_Msk         (0x1UL << EXTI_EMR3_EM80_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR3_EM80             EXTI_EMR3_EM80_Msk                          /*!< Event Mask on line 80 */

+#define EXTI_EMR3_EM81_Pos         (17U)

+#define EXTI_EMR3_EM81_Msk         (0x1UL << EXTI_EMR3_EM81_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR3_EM81             EXTI_EMR3_EM81_Msk                          /*!< Event Mask on line 81 */

+#define EXTI_EMR3_EM82_Pos         (18U)

+#define EXTI_EMR3_EM82_Msk         (0x1UL << EXTI_EMR3_EM82_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR3_EM82             EXTI_EMR3_EM82_Msk                          /*!< Event Mask on line 82 */

+#define EXTI_EMR3_EM85_Pos         (21U)

+#define EXTI_EMR3_EM85_Msk         (0x1UL << EXTI_EMR3_EM85_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR3_EM85             EXTI_EMR3_EM85_Msk                          /*!< Event Mask on line 85 */

+#define EXTI_EMR3_EM87_Pos         (23U)

+#define EXTI_EMR3_EM87_Msk         (0x1UL << EXTI_EMR3_EM87_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR3_EM87             EXTI_EMR3_EM87_Msk                          /*!< Event Mask on line 87 */

+

+#define EXTI_EMR3_EM88_Pos         (24U)

+#define EXTI_EMR3_EM88_Msk         (0x1UL << EXTI_EMR3_EM88_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR3_EM88             EXTI_EMR3_EM88_Msk                          /*!< Event Mask on line 88 */

+

+/*******************  Bit definition for EXTI_PR3 register  ********************/

+#define EXTI_PR3_PR_Pos            (18U)

+#define EXTI_PR3_PR_Msk            (0x9UL << EXTI_PR3_PR_Pos)                  /*!< 0x00240000 */

+#define EXTI_PR3_PR                EXTI_PR3_PR_Msk                             /*!< Pending bit             */

+#define EXTI_PR3_PR82_Pos          (18U)

+#define EXTI_PR3_PR82_Msk          (0x1UL << EXTI_PR3_PR82_Pos)                /*!< 0x00040000 */

+#define EXTI_PR3_PR82              EXTI_PR3_PR82_Msk                           /*!< Pending bit for line 82 */

+#define EXTI_PR3_PR85_Pos          (21U)

+#define EXTI_PR3_PR85_Msk          (0x1UL << EXTI_PR3_PR85_Pos)                /*!< 0x00200000 */

+#define EXTI_PR3_PR85              EXTI_PR3_PR85_Msk                           /*!< Pending bit for line 85 */

+/******************************************************************************/

+/*                                                                            */

+/*                                    FLASH                                   */

+/*                                                                            */

+/******************************************************************************/

+/*

+* @brief FLASH Global Defines

+*/

+#define FLASH_SECTOR_TOTAL                   128U                  /* 128 sectors */

+#define FLASH_SIZE                           0x200000UL            /* 2 MB   */

+#define FLASH_BANK_SIZE                      (FLASH_SIZE >> 1)     /* 1 MB   */

+#define FLASH_SECTOR_SIZE                    0x00002000UL          /* 8 KB   */

+#define FLASH_LATENCY_DEFAULT                FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycles */

+#define FLASH_NB_32BITWORD_IN_FLASHWORD      4U                    /* 128 bits */

+#define DUAL_BANK                                                  /* Dual-bank Flash */

+

+/*******************  Bits definition for FLASH_ACR register  **********************/

+#define FLASH_ACR_LATENCY_Pos                (0U)

+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */

+#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */

+#define FLASH_ACR_LATENCY_0WS                (0x00000000UL)

+#define FLASH_ACR_LATENCY_1WS                (0x00000001UL)

+#define FLASH_ACR_LATENCY_2WS                (0x00000002UL)

+#define FLASH_ACR_LATENCY_3WS                (0x00000003UL)

+#define FLASH_ACR_LATENCY_4WS                (0x00000004UL)

+#define FLASH_ACR_LATENCY_5WS                (0x00000005UL)

+#define FLASH_ACR_LATENCY_6WS                (0x00000006UL)

+#define FLASH_ACR_LATENCY_7WS                (0x00000007UL)

+#define FLASH_ACR_LATENCY_8WS                (0x00000008UL)

+#define FLASH_ACR_LATENCY_9WS                (0x00000009UL)

+#define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)

+#define FLASH_ACR_LATENCY_11WS               (0x0000000BUL)

+#define FLASH_ACR_LATENCY_12WS               (0x0000000CUL)

+#define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)

+#define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)

+#define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)

+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)

+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */

+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */

+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */

+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */

+

+/*******************  Bits definition for FLASH_CR register  ***********************/

+#define FLASH_CR_LOCK_Pos                    (0U)

+#define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */

+#define FLASH_CR_LOCK                        FLASH_CR_LOCK_Msk                 /*!< Configuration lock bit */

+#define FLASH_CR_PG_Pos                      (1U)

+#define FLASH_CR_PG_Msk                      (0x1UL << FLASH_CR_PG_Pos)        /*!< 0x00000002 */

+#define FLASH_CR_PG                          FLASH_CR_PG_Msk                   /*!< Internal buffer control bit */

+#define FLASH_CR_SER_Pos                     (2U)

+#define FLASH_CR_SER_Msk                     (0x1UL << FLASH_CR_SER_Pos)       /*!< 0x00000004 */

+#define FLASH_CR_SER                         FLASH_CR_SER_Msk                  /*!< Sector erase request */

+#define FLASH_CR_BER_Pos                     (3U)

+#define FLASH_CR_BER_Msk                     (0x1UL << FLASH_CR_BER_Pos)       /*!< 0x00000008 */

+#define FLASH_CR_BER                         FLASH_CR_BER_Msk                  /*!< Bank erase request */

+#define FLASH_CR_FW_Pos                      (4U)

+#define FLASH_CR_FW_Msk                      (0x1UL << FLASH_CR_FW_Pos)        /*!< 0x00000010 */

+#define FLASH_CR_FW                          FLASH_CR_FW_Msk                   /*!< Write forcing control bit */

+#define FLASH_CR_START_Pos                   (5U)

+#define FLASH_CR_START_Msk                   (0x1UL << FLASH_CR_START_Pos)     /*!< 0x00000020 */

+#define FLASH_CR_START                       FLASH_CR_START_Msk                /*!< Erase start control bit */

+#define FLASH_CR_SNB_Pos                     (6U)

+#define FLASH_CR_SNB_Msk                     (0x7FUL << FLASH_CR_SNB_Pos)      /*!< 0x00001FC0 */

+#define FLASH_CR_SNB                         FLASH_CR_SNB_Msk                  /*!< Sector erase selection number */

+#define FLASH_CR_SNB_0                       (0x01UL << FLASH_CR_SNB_Pos)      /*!< 0x00000040 */

+#define FLASH_CR_SNB_1                       (0x02UL << FLASH_CR_SNB_Pos)      /*!< 0x00000080 */

+#define FLASH_CR_SNB_2                       (0x04UL << FLASH_CR_SNB_Pos)      /*!< 0x00000100 */

+#define FLASH_CR_SNB_3                       (0x08UL << FLASH_CR_SNB_Pos)      /*!< 0x00000200 */

+#define FLASH_CR_SNB_4                       (0x10UL << FLASH_CR_SNB_Pos)      /*!< 0x00000400 */

+#define FLASH_CR_SNB_5                       (0x20UL << FLASH_CR_SNB_Pos)      /*!< 0x00000800 */

+#define FLASH_CR_SNB_6                       (0x40UL << FLASH_CR_SNB_Pos)      /*!< 0x00001000 */

+#define FLASH_CR_CRC_EN_Pos                  (15U)

+#define FLASH_CR_CRC_EN_Msk                  (0x1UL << FLASH_CR_CRC_EN_Pos)    /*!< 0x00008000 */

+#define FLASH_CR_CRC_EN                      FLASH_CR_CRC_EN_Msk               /*!< CRC control bit */

+#define FLASH_CR_EOPIE_Pos                   (16U)

+#define FLASH_CR_EOPIE_Msk                   (0x1UL << FLASH_CR_EOPIE_Pos)     /*!< 0x00010000 */

+#define FLASH_CR_EOPIE                       FLASH_CR_EOPIE_Msk                /*!< End-of-program interrupt control bit */

+#define FLASH_CR_WRPERRIE_Pos                (17U)

+#define FLASH_CR_WRPERRIE_Msk                (0x1UL << FLASH_CR_WRPERRIE_Pos)  /*!< 0x00020000 */

+#define FLASH_CR_WRPERRIE                    FLASH_CR_WRPERRIE_Msk             /*!< Write protection error interrupt enable bit */

+#define FLASH_CR_PGSERRIE_Pos                (18U)

+#define FLASH_CR_PGSERRIE_Msk                (0x1UL << FLASH_CR_PGSERRIE_Pos)  /*!< 0x00040000 */

+#define FLASH_CR_PGSERRIE                    FLASH_CR_PGSERRIE_Msk             /*!< Programming sequence error interrupt enable bit */

+#define FLASH_CR_STRBERRIE_Pos               (19U)

+#define FLASH_CR_STRBERRIE_Msk               (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */

+#define FLASH_CR_STRBERRIE                   FLASH_CR_STRBERRIE_Msk            /*!< Strobe error interrupt enable bit */

+#define FLASH_CR_INCERRIE_Pos                (21U)

+#define FLASH_CR_INCERRIE_Msk                (0x1UL << FLASH_CR_INCERRIE_Pos)  /*!< 0x00200000 */

+#define FLASH_CR_INCERRIE                    FLASH_CR_INCERRIE_Msk             /*!< Inconsistency error interrupt enable bit */

+#define FLASH_CR_RDPERRIE_Pos                (23U)

+#define FLASH_CR_RDPERRIE_Msk                (0x1UL << FLASH_CR_RDPERRIE_Pos)  /*!< 0x00800000 */

+#define FLASH_CR_RDPERRIE                    FLASH_CR_RDPERRIE_Msk             /*!< Read protection error interrupt enable bit */

+#define FLASH_CR_RDSERRIE_Pos                (24U)

+#define FLASH_CR_RDSERRIE_Msk                (0x1UL << FLASH_CR_RDSERRIE_Pos)  /*!< 0x01000000 */

+#define FLASH_CR_RDSERRIE                    FLASH_CR_RDSERRIE_Msk             /*!< Secure error interrupt enable bit */

+#define FLASH_CR_SNECCERRIE_Pos              (25U)

+#define FLASH_CR_SNECCERRIE_Msk              (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */

+#define FLASH_CR_SNECCERRIE                  FLASH_CR_SNECCERRIE_Msk            /*!< ECC single correction error interrupt enable bit */

+#define FLASH_CR_DBECCERRIE_Pos              (26U)

+#define FLASH_CR_DBECCERRIE_Msk              (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */

+#define FLASH_CR_DBECCERRIE                  FLASH_CR_DBECCERRIE_Msk            /*!< ECC double detection error interrupt enable bit */

+#define FLASH_CR_CRCENDIE_Pos                (27U)

+#define FLASH_CR_CRCENDIE_Msk                (0x1UL << FLASH_CR_CRCENDIE_Pos)  /*!< 0x08000000 */

+#define FLASH_CR_CRCENDIE                    FLASH_CR_CRCENDIE_Msk             /*!< CRC end of calculation interrupt enable bit */

+#define FLASH_CR_CRCRDERRIE_Pos              (28U)

+#define FLASH_CR_CRCRDERRIE_Msk              (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */

+#define FLASH_CR_CRCRDERRIE                  FLASH_CR_CRCRDERRIE_Msk            /*!< CRC read error interrupt enable bit */

+

+/*******************  Bits definition for FLASH_SR register  ***********************/

+#define FLASH_SR_BSY_Pos                     (0U)

+#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)       /*!< 0x00000001 */

+#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy flag */

+#define FLASH_SR_WBNE_Pos                    (1U)

+#define FLASH_SR_WBNE_Msk                    (0x1UL << FLASH_SR_WBNE_Pos)      /*!< 0x00000002 */

+#define FLASH_SR_WBNE                        FLASH_SR_WBNE_Msk                 /*!< Write buffer not empty flag */

+#define FLASH_SR_QW_Pos                      (2U)

+#define FLASH_SR_QW_Msk                      (0x1UL << FLASH_SR_QW_Pos)        /*!< 0x00000004 */

+#define FLASH_SR_QW                          FLASH_SR_QW_Msk                   /*!< Wait queue flag */

+#define FLASH_SR_CRC_BUSY_Pos                (3U)

+#define FLASH_SR_CRC_BUSY_Msk                (0x1UL << FLASH_SR_CRC_BUSY_Pos)  /*!< 0x00000008 */

+#define FLASH_SR_CRC_BUSY                    FLASH_SR_CRC_BUSY_Msk             /*!< CRC busy flag */

+#define FLASH_SR_EOP_Pos                     (16U)

+#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)       /*!< 0x00010000 */

+#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End-of-program flag */

+#define FLASH_SR_WRPERR_Pos                  (17U)

+#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)    /*!< 0x00020000 */

+#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protection error flag */

+#define FLASH_SR_PGSERR_Pos                  (18U)

+#define FLASH_SR_PGSERR_Msk                  (0x1UL << FLASH_SR_PGSERR_Pos)    /*!< 0x00040000 */

+#define FLASH_SR_PGSERR                      FLASH_SR_PGSERR_Msk               /*!< Programming sequence error flag */

+#define FLASH_SR_STRBERR_Pos                 (19U)

+#define FLASH_SR_STRBERR_Msk                 (0x1UL << FLASH_SR_STRBERR_Pos)   /*!< 0x00080000 */

+#define FLASH_SR_STRBERR                     FLASH_SR_STRBERR_Msk              /*!< Strobe error flag */

+#define FLASH_SR_INCERR_Pos                  (21U)

+#define FLASH_SR_INCERR_Msk                  (0x1UL << FLASH_SR_INCERR_Pos)    /*!< 0x00200000 */

+#define FLASH_SR_INCERR                      FLASH_SR_INCERR_Msk               /*!< Inconsistency error flag */

+#define FLASH_SR_RDPERR_Pos                  (23U)

+#define FLASH_SR_RDPERR_Msk                  (0x1UL << FLASH_SR_RDPERR_Pos)    /*!< 0x00800000 */

+#define FLASH_SR_RDPERR                      FLASH_SR_RDPERR_Msk               /*!< Read protection error flag */

+#define FLASH_SR_RDSERR_Pos                  (24U)

+#define FLASH_SR_RDSERR_Msk                  (0x1UL << FLASH_SR_RDSERR_Pos)    /*!< 0x01000000 */

+#define FLASH_SR_RDSERR                      FLASH_SR_RDSERR_Msk               /*!< Secure error flag */

+#define FLASH_SR_SNECCERR_Pos                (25U)

+#define FLASH_SR_SNECCERR_Msk                (0x1UL << FLASH_SR_SNECCERR_Pos)  /*!< 0x02000000 */

+#define FLASH_SR_SNECCERR                    FLASH_SR_SNECCERR_Msk             /*!< Single correction error flag */

+#define FLASH_SR_DBECCERR_Pos                (26U)

+#define FLASH_SR_DBECCERR_Msk                (0x1UL << FLASH_SR_DBECCERR_Pos)  /*!< 0x04000000 */

+#define FLASH_SR_DBECCERR                    FLASH_SR_DBECCERR_Msk             /*!< ECC double detection error flag */

+#define FLASH_SR_CRCEND_Pos                  (27U)

+#define FLASH_SR_CRCEND_Msk                  (0x1UL << FLASH_SR_CRCEND_Pos)    /*!< 0x08000000 */

+#define FLASH_SR_CRCEND                      FLASH_SR_CRCEND_Msk               /*!< CRC end of calculation flag */

+#define FLASH_SR_CRCRDERR_Pos                (28U)

+#define FLASH_SR_CRCRDERR_Msk                (0x1UL << FLASH_SR_CRCRDERR_Pos)  /*!< 0x10000000 */

+#define FLASH_SR_CRCRDERR                    FLASH_SR_CRCRDERR_Msk             /*!< CRC read error flag */

+

+/*******************  Bits definition for FLASH_CCR register  *******************/

+#define FLASH_CCR_CLR_EOP_Pos                (16U)

+#define FLASH_CCR_CLR_EOP_Msk                (0x1UL << FLASH_CCR_CLR_EOP_Pos)  /*!< 0x00010000 */

+#define FLASH_CCR_CLR_EOP                    FLASH_CCR_CLR_EOP_Msk             /*!< EOP flag clear bit */

+#define FLASH_CCR_CLR_WRPERR_Pos             (17U)

+#define FLASH_CCR_CLR_WRPERR_Msk             (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */

+#define FLASH_CCR_CLR_WRPERR                 FLASH_CCR_CLR_WRPERR_Msk            /*!< WRPERR flag clear bit */

+#define FLASH_CCR_CLR_PGSERR_Pos             (18U)

+#define FLASH_CCR_CLR_PGSERR_Msk             (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */

+#define FLASH_CCR_CLR_PGSERR                 FLASH_CCR_CLR_PGSERR_Msk            /*!< PGSERR flag clear bit */

+#define FLASH_CCR_CLR_STRBERR_Pos            (19U)

+#define FLASH_CCR_CLR_STRBERR_Msk            (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */

+#define FLASH_CCR_CLR_STRBERR                FLASH_CCR_CLR_STRBERR_Msk            /*!< STRBERR flag clear bit */

+#define FLASH_CCR_CLR_INCERR_Pos             (21U)

+#define FLASH_CCR_CLR_INCERR_Msk             (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */

+#define FLASH_CCR_CLR_INCERR                 FLASH_CCR_CLR_INCERR_Msk            /*!< INCERR flag clear bit */

+#define FLASH_CCR_CLR_RDPERR_Pos             (23U)

+#define FLASH_CCR_CLR_RDPERR_Msk             (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */

+#define FLASH_CCR_CLR_RDPERR                 FLASH_CCR_CLR_RDPERR_Msk            /*!< RDPERR flag clear bit */

+#define FLASH_CCR_CLR_RDSERR_Pos             (24U)

+#define FLASH_CCR_CLR_RDSERR_Msk             (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */

+#define FLASH_CCR_CLR_RDSERR                 FLASH_CCR_CLR_RDSERR_Msk            /*!< RDSERR flag clear bit */

+#define FLASH_CCR_CLR_SNECCERR_Pos           (25U)

+#define FLASH_CCR_CLR_SNECCERR_Msk           (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */

+#define FLASH_CCR_CLR_SNECCERR               FLASH_CCR_CLR_SNECCERR_Msk            /*!< SNECCERR flag clear bit */

+#define FLASH_CCR_CLR_DBECCERR_Pos           (26U)

+#define FLASH_CCR_CLR_DBECCERR_Msk           (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */

+#define FLASH_CCR_CLR_DBECCERR               FLASH_CCR_CLR_DBECCERR_Msk            /*!< DBECCERR flag clear bit */

+#define FLASH_CCR_CLR_CRCEND_Pos             (27U)

+#define FLASH_CCR_CLR_CRCEND_Msk             (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */

+#define FLASH_CCR_CLR_CRCEND                 FLASH_CCR_CLR_CRCEND_Msk            /*!< CRCEND flag clear bit */

+#define FLASH_CCR_CLR_CRCRDERR_Pos           (28U)

+#define FLASH_CCR_CLR_CRCRDERR_Msk           (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */

+#define FLASH_CCR_CLR_CRCRDERR               FLASH_CCR_CLR_CRCRDERR_Msk            /*!< CRCRDERR flag clear bit */

+

+/*******************  Bits definition for FLASH_OPTCR register  *******************/

+#define FLASH_OPTCR_OPTLOCK_Pos              (0U)

+#define FLASH_OPTCR_OPTLOCK_Msk              (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)  /*!< 0x00000001 */

+#define FLASH_OPTCR_OPTLOCK                  FLASH_OPTCR_OPTLOCK_Msk             /*!< FLASH_OPTCR lock option configuration bit */

+#define FLASH_OPTCR_OPTSTART_Pos             (1U)

+#define FLASH_OPTCR_OPTSTART_Msk             (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */

+#define FLASH_OPTCR_OPTSTART                 FLASH_OPTCR_OPTSTART_Msk            /*!< Option byte start change option configuration bit */

+#define FLASH_OPTCR_MER_Pos                  (4U)

+#define FLASH_OPTCR_MER_Msk                  (0x1UL << FLASH_OPTCR_MER_Pos)      /*!< 0x00000010 */

+#define FLASH_OPTCR_MER                      FLASH_OPTCR_MER_Msk                 /*!< Mass erase request */

+#define FLASH_OPTCR_PG_OTP_Pos               (5U)

+#define FLASH_OPTCR_PG_OTP_Msk               (0x1UL << FLASH_OPTCR_PG_OTP_Pos)   /*!< 0x00000020 */

+#define FLASH_OPTCR_PG_OTP                   FLASH_OPTCR_PG_OTP_Msk              /*!< OTP program control bit */

+#define FLASH_OPTCR_OPTCHANGEERRIE_Pos       (30U)

+#define FLASH_OPTCR_OPTCHANGEERRIE_Msk       (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */

+#define FLASH_OPTCR_OPTCHANGEERRIE           FLASH_OPTCR_OPTCHANGEERRIE_Msk            /*!< Option byte change error interrupt enable bit */

+#define FLASH_OPTCR_SWAP_BANK_Pos            (31U)

+#define FLASH_OPTCR_SWAP_BANK_Msk            (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */

+#define FLASH_OPTCR_SWAP_BANK                FLASH_OPTCR_SWAP_BANK_Msk            /*!< Bank swapping option configuration bit */

+

+/*******************  Bits definition for FLASH_OPTSR register  ***************/

+#define FLASH_OPTSR_OPT_BUSY_Pos             (0U)

+#define FLASH_OPTSR_OPT_BUSY_Msk             (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */

+#define FLASH_OPTSR_OPT_BUSY                 FLASH_OPTSR_OPT_BUSY_Msk            /*!< Option byte change ongoing flag */

+#define FLASH_OPTSR_BOR_LEV_Pos              (2U)

+#define FLASH_OPTSR_BOR_LEV_Msk              (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */

+#define FLASH_OPTSR_BOR_LEV                  FLASH_OPTSR_BOR_LEV_Msk            /*!< Brownout level option status bit */

+#define FLASH_OPTSR_BOR_LEV_0                (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */

+#define FLASH_OPTSR_BOR_LEV_1                (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */

+#define FLASH_OPTSR_IWDG1_SW_Pos             (4U)

+#define FLASH_OPTSR_IWDG1_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */

+#define FLASH_OPTSR_IWDG1_SW                 FLASH_OPTSR_IWDG1_SW_Msk            /*!< IWDG1 control mode option status bit */

+#define FLASH_OPTSR_NRST_STOP_D1_Pos         (6U)

+#define FLASH_OPTSR_NRST_STOP_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */

+#define FLASH_OPTSR_NRST_STOP_D1             FLASH_OPTSR_NRST_STOP_D1_Msk            /*!< D1 domain DStop entry reset option status bit */

+#define FLASH_OPTSR_NRST_STBY_D1_Pos         (7U)

+#define FLASH_OPTSR_NRST_STBY_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */

+#define FLASH_OPTSR_NRST_STBY_D1             FLASH_OPTSR_NRST_STBY_D1_Msk            /*!< D1 domain DStandby entry reset option status bit */

+#define FLASH_OPTSR_RDP_Pos                  (8U)

+#define FLASH_OPTSR_RDP_Msk                  (0xFFUL << FLASH_OPTSR_RDP_Pos)   /*!< 0x0000FF00 */

+#define FLASH_OPTSR_RDP                      FLASH_OPTSR_RDP_Msk               /*!< Readout protection level option status byte */

+#define FLASH_OPTSR_VDDMMC_HSLV_Pos          (16U)

+#define FLASH_OPTSR_VDDMMC_HSLV_Msk          (0x1UL << FLASH_OPTSR_VDDMMC_HSLV_Pos) /*!< 0x00010000 */

+#define FLASH_OPTSR_VDDMMC_HSLV              FLASH_OPTSR_VDDMMC_HSLV_Msk            /*!< VDDMMC I/O high-speed at low-voltage status bit (below 2.5V) */

+#define FLASH_OPTSR_FZ_IWDG_STOP_Pos         (17U)

+#define FLASH_OPTSR_FZ_IWDG_STOP_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */

+#define FLASH_OPTSR_FZ_IWDG_STOP             FLASH_OPTSR_FZ_IWDG_STOP_Msk            /*!< IWDG Stop mode freeze option status bit */

+#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos         (18U)

+#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */

+#define FLASH_OPTSR_FZ_IWDG_SDBY             FLASH_OPTSR_FZ_IWDG_SDBY_Msk            /*!< IWDG Standby mode freeze option status bit */

+#define FLASH_OPTSR_ST_RAM_SIZE_Pos          (19U)

+#define FLASH_OPTSR_ST_RAM_SIZE_Msk          (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */

+#define FLASH_OPTSR_ST_RAM_SIZE              FLASH_OPTSR_ST_RAM_SIZE_Msk            /*!< ST RAM size option status */

+#define FLASH_OPTSR_ST_RAM_SIZE_0            (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */

+#define FLASH_OPTSR_ST_RAM_SIZE_1            (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */

+#define FLASH_OPTSR_SECURITY_Pos             (21U)

+#define FLASH_OPTSR_SECURITY_Msk             (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */

+#define FLASH_OPTSR_SECURITY                 FLASH_OPTSR_SECURITY_Msk            /*!< Security enable option status bit */

+#define FLASH_OPTSR_IO_HSLV_Pos              (29U)

+#define FLASH_OPTSR_IO_HSLV_Msk              (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */

+#define FLASH_OPTSR_IO_HSLV                  FLASH_OPTSR_IO_HSLV_Msk            /*!< I/O high-speed at low-voltage status bit */

+#define FLASH_OPTSR_OPTCHANGEERR_Pos         (30U)

+#define FLASH_OPTSR_OPTCHANGEERR_Msk         (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */

+#define FLASH_OPTSR_OPTCHANGEERR             FLASH_OPTSR_OPTCHANGEERR_Msk            /*!< Option byte change error flag */

+#define FLASH_OPTSR_SWAP_BANK_OPT_Pos        (31U)

+#define FLASH_OPTSR_SWAP_BANK_OPT_Msk        (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */

+#define FLASH_OPTSR_SWAP_BANK_OPT            FLASH_OPTSR_SWAP_BANK_OPT_Msk            /*!< Bank swapping option status bit */

+

+/*******************  Bits definition for FLASH_OPTCCR register  *******************/

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos    (30U)

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk    (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR        FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk            /*!< OPTCHANGEERR reset bit */

+

+/*******************  Bits definition for FLASH_PRAR register  *********************/

+#define FLASH_PRAR_PROT_AREA_START_Pos       (0U)

+#define FLASH_PRAR_PROT_AREA_START_Msk       (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */

+#define FLASH_PRAR_PROT_AREA_START           FLASH_PRAR_PROT_AREA_START_Msk              /*!< PCROP area start status bits */

+#define FLASH_PRAR_PROT_AREA_END_Pos         (16U)

+#define FLASH_PRAR_PROT_AREA_END_Msk         (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */

+#define FLASH_PRAR_PROT_AREA_END             FLASH_PRAR_PROT_AREA_END_Msk              /*!< PCROP area end status bits */

+#define FLASH_PRAR_DMEP_Pos                  (31U)

+#define FLASH_PRAR_DMEP_Msk                  (0x1UL << FLASH_PRAR_DMEP_Pos)    /*!< 0x80000000 */

+#define FLASH_PRAR_DMEP                      FLASH_PRAR_DMEP_Msk               /*!< PCROP protected erase enable option status bit */

+

+/*******************  Bits definition for FLASH_SCAR register  *********************/

+#define FLASH_SCAR_SEC_AREA_START_Pos        (0U)

+#define FLASH_SCAR_SEC_AREA_START_Msk        (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */

+#define FLASH_SCAR_SEC_AREA_START            FLASH_SCAR_SEC_AREA_START_Msk              /*!< Secure-only area start status bits */

+#define FLASH_SCAR_SEC_AREA_END_Pos          (16U)

+#define FLASH_SCAR_SEC_AREA_END_Msk          (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */

+#define FLASH_SCAR_SEC_AREA_END              FLASH_SCAR_SEC_AREA_END_Msk              /*!< Secure-only area end status bits */

+#define FLASH_SCAR_DMES_Pos                  (31U)

+#define FLASH_SCAR_DMES_Msk                  (0x1UL << FLASH_SCAR_DMES_Pos)    /*!< 0x80000000 */

+#define FLASH_SCAR_DMES                      FLASH_SCAR_DMES_Msk               /*!< Secure access protected erase enable option status bit */

+

+/*******************  Bits definition for FLASH_WPSN register  *********************/

+#define FLASH_WPSN_WRPSN_Pos                 (0U)

+#define FLASH_WPSN_WRPSN_Msk                 (0xFFFFFFFFUL << FLASH_WPSN_WRPSN_Pos)  /*!< 0xFFFFFFFF */

+#define FLASH_WPSN_WRPSN                     FLASH_WPSN_WRPSN_Msk              /*!< Sector write protection option status byte */

+

+/*******************  Bits definition for FLASH_BOOT_CUR register  ****************/

+#define FLASH_BOOT_ADD0_Pos                  (0U)

+#define FLASH_BOOT_ADD0_Msk                  (0xFFFFUL << FLASH_BOOT_ADD0_Pos) /*!< 0x0000FFFF */

+#define FLASH_BOOT_ADD0                      FLASH_BOOT_ADD0_Msk               /*!< Arm Cortex-M7 boot address 0 */

+#define FLASH_BOOT_ADD1_Pos                  (16U)

+#define FLASH_BOOT_ADD1_Msk                  (0xFFFFUL << FLASH_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */

+#define FLASH_BOOT_ADD1                      FLASH_BOOT_ADD1_Msk               /*!< Arm Cortex-M7 boot address 1 */

+

+

+/*******************  Bits definition for FLASH_CRCCR register  ********************/

+#define FLASH_CRCCR_CRC_SECT_Pos             (0U)

+#define FLASH_CRCCR_CRC_SECT_Msk             (0x3FUL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x0000003F */

+#define FLASH_CRCCR_CRC_SECT                 FLASH_CRCCR_CRC_SECT_Msk             /*!< CRC sector number */

+#define FLASH_CRCCR_CRC_BY_SECT_Pos          (8U)

+#define FLASH_CRCCR_CRC_BY_SECT_Msk          (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */

+#define FLASH_CRCCR_CRC_BY_SECT              FLASH_CRCCR_CRC_BY_SECT_Msk            /*!< CRC sector mode select bit */

+#define FLASH_CRCCR_ADD_SECT_Pos             (9U)

+#define FLASH_CRCCR_ADD_SECT_Msk             (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */

+#define FLASH_CRCCR_ADD_SECT                 FLASH_CRCCR_ADD_SECT_Msk            /*!< CRC sector select bit */

+#define FLASH_CRCCR_CLEAN_SECT_Pos           (10U)

+#define FLASH_CRCCR_CLEAN_SECT_Msk           (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */

+#define FLASH_CRCCR_CLEAN_SECT               FLASH_CRCCR_CLEAN_SECT_Msk            /*!< CRC sector list clear bit */

+#define FLASH_CRCCR_START_CRC_Pos            (16U)

+#define FLASH_CRCCR_START_CRC_Msk            (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */

+#define FLASH_CRCCR_START_CRC                FLASH_CRCCR_START_CRC_Msk            /*!< CRC start bit */

+#define FLASH_CRCCR_CLEAN_CRC_Pos            (17U)

+#define FLASH_CRCCR_CLEAN_CRC_Msk            (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */

+#define FLASH_CRCCR_CLEAN_CRC                FLASH_CRCCR_CLEAN_CRC_Msk            /*!< CRC clear bit */

+#define FLASH_CRCCR_CRC_BURST_Pos            (20U)

+#define FLASH_CRCCR_CRC_BURST_Msk            (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */

+#define FLASH_CRCCR_CRC_BURST                FLASH_CRCCR_CRC_BURST_Msk            /*!< CRC burst size */

+#define FLASH_CRCCR_CRC_BURST_0              (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */

+#define FLASH_CRCCR_CRC_BURST_1              (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */

+#define FLASH_CRCCR_ALL_BANK_Pos             (22U)

+#define FLASH_CRCCR_ALL_BANK_Msk             (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */

+#define FLASH_CRCCR_ALL_BANK                 FLASH_CRCCR_ALL_BANK_Msk            /*!< CRC select bit */

+

+/*******************  Bits definition for FLASH_CRCSADD register  ****************/

+#define FLASH_CRCSADD_CRC_START_ADDR_Pos     (0U)

+#define FLASH_CRCSADD_CRC_START_ADDR_Msk     (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCSADD_CRC_START_ADDR         FLASH_CRCSADD_CRC_START_ADDR_Msk                   /*!< CRC start address */

+

+/*******************  Bits definition for FLASH_CRCEADD register  ****************/

+#define FLASH_CRCEADD_CRC_END_ADDR_Pos       (0U)

+#define FLASH_CRCEADD_CRC_END_ADDR_Msk       (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCEADD_CRC_END_ADDR           FLASH_CRCEADD_CRC_END_ADDR_Msk                   /*!< CRC end address */

+

+/*******************  Bits definition for FLASH_CRCDATA register  ***************/

+#define FLASH_CRCDATA_CRC_DATA_Pos           (0U)

+#define FLASH_CRCDATA_CRC_DATA_Msk           (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCDATA_CRC_DATA               FLASH_CRCDATA_CRC_DATA_Msk                   /*!< CRC result */

+

+/*******************  Bits definition for FLASH_ECC_FA register  *******************/

+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos       (0U)

+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk       (0xFFFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x0000FFFF */

+#define FLASH_ECC_FA_FAIL_ECC_ADDR           FLASH_ECC_FA_FAIL_ECC_ADDR_Msk               /*!< ECC error address */

+#define FLASH_ECC_FA_OTP_FAIL_ECC_Pos        (31U)

+#define FLASH_ECC_FA_OTP_FAIL_ECC_Msk        (0x1UL << FLASH_ECC_FA_OTP_FAIL_ECC_Pos) /*!< 0x80000000 */

+#define FLASH_ECC_FA_OTP_FAIL_ECC            FLASH_ECC_FA_OTP_FAIL_ECC_Msk            /*!< OTP ECC error bit */

+

+/*******************  Bits definition for FLASH_OTPBL register  *******************/

+#define FLASH_OTPBL_LOCKBL_Pos               (0U)

+#define FLASH_OTPBL_LOCKBL_Msk               (0xFFFFUL << FLASH_OTPBL_LOCKBL_Pos) /*!< 0x0000FFFF */

+#define FLASH_OTPBL_LOCKBL                   FLASH_OTPBL_LOCKBL_Msk               /*!< OTP Block Lock */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          Flexible Memory Controller                        */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for FMC_BCR1 register  *******************/

+#define FMC_BCR1_CCLKEN_Pos        (20U)

+#define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */

+#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continous clock enable     */

+#define FMC_BCR1_WFDIS_Pos         (21U)

+#define FMC_BCR1_WFDIS_Msk         (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */

+#define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */

+

+#define FMC_BCR1_BMAP_Pos          (24U)

+#define FMC_BCR1_BMAP_Msk          (0x3UL << FMC_BCR1_BMAP_Pos)                /*!< 0x03000000 */

+#define FMC_BCR1_BMAP              FMC_BCR1_BMAP_Msk                           /*!<BMAP[1:0] FMC bank mapping */

+#define FMC_BCR1_BMAP_0            (0x1UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x01000000 */

+#define FMC_BCR1_BMAP_1            (0x2UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x02000000 */

+

+#define FMC_BCR1_FMCEN_Pos         (31U)

+#define FMC_BCR1_FMCEN_Msk         (0x1UL << FMC_BCR1_FMCEN_Pos)               /*!< 0x80000000 */

+#define FMC_BCR1_FMCEN             FMC_BCR1_FMCEN_Msk                          /*!<FMC controller Enable */

+/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/

+#define FMC_BCRx_MBKEN_Pos         (0U)

+#define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */

+#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */

+#define FMC_BCRx_MUXEN_Pos         (1U)

+#define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */

+#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */

+

+#define FMC_BCRx_MTYP_Pos          (2U)

+#define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */

+#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */

+#define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000004 */

+#define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000008 */

+

+#define FMC_BCRx_MWID_Pos          (4U)

+#define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */

+#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */

+#define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000010 */

+#define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000020 */

+

+#define FMC_BCRx_FACCEN_Pos        (6U)

+#define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */

+#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */

+#define FMC_BCRx_BURSTEN_Pos       (8U)

+#define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */

+#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */

+#define FMC_BCRx_WAITPOL_Pos       (9U)

+#define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */

+#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */

+#define FMC_BCRx_WAITCFG_Pos       (11U)

+#define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */

+#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */

+#define FMC_BCRx_WREN_Pos          (12U)

+#define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */

+#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */

+#define FMC_BCRx_WAITEN_Pos        (13U)

+#define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */

+#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */

+#define FMC_BCRx_EXTMOD_Pos        (14U)

+#define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */

+#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */

+#define FMC_BCRx_ASYNCWAIT_Pos     (15U)

+#define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */

+#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */

+

+#define FMC_BCRx_CPSIZE_Pos        (16U)

+#define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */

+#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<PSIZE[2:0] bits CRAM Page Size */

+#define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00010000 */

+#define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00020000 */

+#define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00040000 */

+

+#define FMC_BCRx_CBURSTRW_Pos      (19U)

+#define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */

+#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */

+

+/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/

+#define FMC_BTRx_ADDSET_Pos        (0U)

+#define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */

+#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */

+#define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000001 */

+#define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000002 */

+#define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000004 */

+#define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000008 */

+

+#define FMC_BTRx_ADDHLD_Pos        (4U)

+#define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */

+#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */

+#define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000010 */

+#define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000020 */

+#define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000040 */

+#define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000080 */

+

+#define FMC_BTRx_DATAST_Pos        (8U)

+#define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */

+#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */

+#define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000100 */

+#define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000200 */

+#define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000400 */

+#define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000800 */

+#define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00001000 */

+#define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00002000 */

+#define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00004000 */

+#define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00008000 */

+

+#define FMC_BTRx_BUSTURN_Pos       (16U)

+#define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */

+#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */

+#define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00010000 */

+#define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00020000 */

+#define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00040000 */

+#define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00080000 */

+

+#define FMC_BTRx_CLKDIV_Pos        (20U)

+#define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */

+#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */

+#define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00100000 */

+#define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00200000 */

+#define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00400000 */

+#define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00800000 */

+

+#define FMC_BTRx_DATLAT_Pos        (24U)

+#define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */

+#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */

+#define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x01000000 */

+#define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x02000000 */

+#define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x04000000 */

+#define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x08000000 */

+

+#define FMC_BTRx_ACCMOD_Pos        (28U)

+#define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */

+#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */

+#define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x10000000 */

+#define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x20000000 */

+

+/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/

+#define FMC_BWTRx_ADDSET_Pos       (0U)

+#define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */

+#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */

+#define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000001 */

+#define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000002 */

+#define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000004 */

+#define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000008 */

+

+#define FMC_BWTRx_ADDHLD_Pos       (4U)

+#define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */

+#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */

+#define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000010 */

+#define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000020 */

+#define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000040 */

+#define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000080 */

+

+#define FMC_BWTRx_DATAST_Pos       (8U)

+#define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */

+#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */

+#define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000100 */

+#define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000200 */

+#define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000400 */

+#define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000800 */

+#define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00001000 */

+#define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00002000 */

+#define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00004000 */

+#define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00008000 */

+

+#define FMC_BWTRx_BUSTURN_Pos      (16U)

+#define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */

+#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */

+#define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00010000 */

+#define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00020000 */

+#define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00040000 */

+#define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00080000 */

+

+#define FMC_BWTRx_ACCMOD_Pos       (28U)

+#define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */

+#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */

+#define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x10000000 */

+#define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x20000000 */

+

+/******************  Bit definition for FMC_PCR register  *******************/

+#define FMC_PCR_PWAITEN_Pos        (1U)

+#define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */

+#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */

+#define FMC_PCR_PBKEN_Pos          (2U)

+#define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */

+#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */

+

+#define FMC_PCR_PWID_Pos           (4U)

+#define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */

+#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */

+#define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */

+#define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */

+

+#define FMC_PCR_ECCEN_Pos          (6U)

+#define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */

+#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */

+

+#define FMC_PCR_TCLR_Pos           (9U)

+#define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */

+#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */

+#define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */

+#define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */

+#define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */

+#define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */

+

+#define FMC_PCR_TAR_Pos            (13U)

+#define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */

+#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */

+#define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */

+#define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */

+#define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */

+#define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */

+

+#define FMC_PCR_ECCPS_Pos          (17U)

+#define FMC_PCR_ECCPS_Msk          (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */

+#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */

+#define FMC_PCR_ECCPS_0            (0x1UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */

+#define FMC_PCR_ECCPS_1            (0x2UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */

+#define FMC_PCR_ECCPS_2            (0x4UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */

+

+/*******************  Bit definition for FMC_SR register  *******************/

+#define FMC_SR_IRS_Pos             (0U)

+#define FMC_SR_IRS_Msk             (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */

+#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */

+#define FMC_SR_ILS_Pos             (1U)

+#define FMC_SR_ILS_Msk             (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */

+#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */

+#define FMC_SR_IFS_Pos             (2U)

+#define FMC_SR_IFS_Msk             (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */

+#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */

+#define FMC_SR_IREN_Pos            (3U)

+#define FMC_SR_IREN_Msk            (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */

+#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */

+#define FMC_SR_ILEN_Pos            (4U)

+#define FMC_SR_ILEN_Msk            (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */

+#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */

+#define FMC_SR_IFEN_Pos            (5U)

+#define FMC_SR_IFEN_Msk            (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */

+#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */

+#define FMC_SR_FEMPT_Pos           (6U)

+#define FMC_SR_FEMPT_Msk           (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */

+#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */

+

+/******************  Bit definition for FMC_PMEM register  ******************/

+#define FMC_PMEM_MEMSET_Pos       (0U)

+#define FMC_PMEM_MEMSET_Msk       (0xFFUL << FMC_PMEM_MEMSET_Pos)            /*!< 0x000000FF */

+#define FMC_PMEM_MEMSET           FMC_PMEM_MEMSET_Msk                        /*!<MEMSET[7:0] bits (Common memory setup time) */

+#define FMC_PMEM_MEMSET_0         (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */

+#define FMC_PMEM_MEMSET_1         (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */

+#define FMC_PMEM_MEMSET_2         (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */

+#define FMC_PMEM_MEMSET_3         (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */

+#define FMC_PMEM_MEMSET_4         (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */

+#define FMC_PMEM_MEMSET_5         (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */

+#define FMC_PMEM_MEMSET_6         (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */

+#define FMC_PMEM_MEMSET_7         (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */

+

+#define FMC_PMEM_MEMWAIT_Pos      (8U)

+#define FMC_PMEM_MEMWAIT_Msk      (0xFFUL << FMC_PMEM_MEMWAIT_Pos)           /*!< 0x0000FF00 */

+#define FMC_PMEM_MEMWAIT          FMC_PMEM_MEMWAIT_Msk                       /*!<MEMWAIT[7:0] bits (Common memory wait time) */

+#define FMC_PMEM_MEMWAIT_0        (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */

+#define FMC_PMEM_MEMWAIT_1        (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */

+#define FMC_PMEM_MEMWAIT_2        (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */

+#define FMC_PMEM_MEMWAIT_3        (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */

+#define FMC_PMEM_MEMWAIT_4        (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */

+#define FMC_PMEM_MEMWAIT_5        (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */

+#define FMC_PMEM_MEMWAIT_6        (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */

+#define FMC_PMEM_MEMWAIT_7        (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */

+

+#define FMC_PMEM_MEMHOLD_Pos      (16U)

+#define FMC_PMEM_MEMHOLD_Msk      (0xFFUL << FMC_PMEM_MEMHOLD_Pos)           /*!< 0x00FF0000 */

+#define FMC_PMEM_MEMHOLD          FMC_PMEM_MEMHOLD_Msk                       /*!<MEMHOLD[7:0] bits (Common memory hold time) */

+#define FMC_PMEM_MEMHOLD_0        (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */

+#define FMC_PMEM_MEMHOLD_1        (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */

+#define FMC_PMEM_MEMHOLD_2        (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */

+#define FMC_PMEM_MEMHOLD_3        (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */

+#define FMC_PMEM_MEMHOLD_4        (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */

+#define FMC_PMEM_MEMHOLD_5        (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */

+#define FMC_PMEM_MEMHOLD_6        (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */

+#define FMC_PMEM_MEMHOLD_7        (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */

+

+#define FMC_PMEM_MEMHIZ_Pos       (24U)

+#define FMC_PMEM_MEMHIZ_Msk       (0xFFUL << FMC_PMEM_MEMHIZ_Pos)            /*!< 0xFF000000 */

+#define FMC_PMEM_MEMHIZ           FMC_PMEM_MEMHIZ_Msk                        /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */

+#define FMC_PMEM_MEMHIZ_0         (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */

+#define FMC_PMEM_MEMHIZ_1         (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */

+#define FMC_PMEM_MEMHIZ_2         (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */

+#define FMC_PMEM_MEMHIZ_3         (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */

+#define FMC_PMEM_MEMHIZ_4         (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */

+#define FMC_PMEM_MEMHIZ_5         (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */

+#define FMC_PMEM_MEMHIZ_6         (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */

+#define FMC_PMEM_MEMHIZ_7         (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */

+

+/******************  Bit definition for FMC_PATT register  ******************/

+#define FMC_PATT_ATTSET_Pos       (0U)

+#define FMC_PATT_ATTSET_Msk       (0xFFUL << FMC_PATT_ATTSET_Pos)            /*!< 0x000000FF */

+#define FMC_PATT_ATTSET           FMC_PATT_ATTSET_Msk                        /*!<ATTSET[7:0] bits (Attribute memory setup time) */

+#define FMC_PATT_ATTSET_0         (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */

+#define FMC_PATT_ATTSET_1         (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */

+#define FMC_PATT_ATTSET_2         (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */

+#define FMC_PATT_ATTSET_3         (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */

+#define FMC_PATT_ATTSET_4         (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */

+#define FMC_PATT_ATTSET_5         (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */

+#define FMC_PATT_ATTSET_6         (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */

+#define FMC_PATT_ATTSET_7         (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */

+

+#define FMC_PATT_ATTWAIT_Pos      (8U)

+#define FMC_PATT_ATTWAIT_Msk      (0xFFUL << FMC_PATT_ATTWAIT_Pos)           /*!< 0x0000FF00 */

+#define FMC_PATT_ATTWAIT          FMC_PATT_ATTWAIT_Msk                       /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */

+#define FMC_PATT_ATTWAIT_0        (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */

+#define FMC_PATT_ATTWAIT_1        (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */

+#define FMC_PATT_ATTWAIT_2        (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */

+#define FMC_PATT_ATTWAIT_3        (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */

+#define FMC_PATT_ATTWAIT_4        (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */

+#define FMC_PATT_ATTWAIT_5        (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */

+#define FMC_PATT_ATTWAIT_6        (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */

+#define FMC_PATT_ATTWAIT_7        (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */

+

+#define FMC_PATT_ATTHOLD_Pos      (16U)

+#define FMC_PATT_ATTHOLD_Msk      (0xFFUL << FMC_PATT_ATTHOLD_Pos)           /*!< 0x00FF0000 */

+#define FMC_PATT_ATTHOLD          FMC_PATT_ATTHOLD_Msk                       /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */

+#define FMC_PATT_ATTHOLD_0        (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */

+#define FMC_PATT_ATTHOLD_1        (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */

+#define FMC_PATT_ATTHOLD_2        (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */

+#define FMC_PATT_ATTHOLD_3        (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */

+#define FMC_PATT_ATTHOLD_4        (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */

+#define FMC_PATT_ATTHOLD_5        (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */

+#define FMC_PATT_ATTHOLD_6        (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */

+#define FMC_PATT_ATTHOLD_7        (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */

+

+#define FMC_PATT_ATTHIZ_Pos       (24U)

+#define FMC_PATT_ATTHIZ_Msk       (0xFFUL << FMC_PATT_ATTHIZ_Pos)            /*!< 0xFF000000 */

+#define FMC_PATT_ATTHIZ           FMC_PATT_ATTHIZ_Msk                        /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */

+#define FMC_PATT_ATTHIZ_0         (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */

+#define FMC_PATT_ATTHIZ_1         (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */

+#define FMC_PATT_ATTHIZ_2         (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */

+#define FMC_PATT_ATTHIZ_3         (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */

+#define FMC_PATT_ATTHIZ_4         (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */

+#define FMC_PATT_ATTHIZ_5         (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */

+#define FMC_PATT_ATTHIZ_6         (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */

+#define FMC_PATT_ATTHIZ_7         (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */

+

+/******************  Bit definition for FMC_ECCR3 register  ******************/

+#define FMC_ECCR3_ECC3_Pos         (0U)

+#define FMC_ECCR3_ECC3_Msk         (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)        /*!< 0xFFFFFFFF */

+#define FMC_ECCR3_ECC3             FMC_ECCR3_ECC3_Msk                          /*!<ECC result */

+

+/******************  Bit definition for FMC_SDCRx registers (x=1..4)  *********/

+#define FMC_SDCRx_NC_Pos           (0U)

+#define FMC_SDCRx_NC_Msk           (0x3UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000003 */

+#define FMC_SDCRx_NC               FMC_SDCRx_NC_Msk                            /*!<NC[1:0] bits (Number of column bits) */

+#define FMC_SDCRx_NC_0             (0x1UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000001 */

+#define FMC_SDCRx_NC_1             (0x2UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000002 */

+

+#define FMC_SDCRx_NR_Pos           (2U)

+#define FMC_SDCRx_NR_Msk           (0x3UL << FMC_SDCRx_NR_Pos)                 /*!< 0x0000000C */

+#define FMC_SDCRx_NR               FMC_SDCRx_NR_Msk                            /*!<NR[1:0] bits (Number of row bits) */

+#define FMC_SDCRx_NR_0             (0x1UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000004 */

+#define FMC_SDCRx_NR_1             (0x2UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000008 */

+

+#define FMC_SDCRx_MWID_Pos         (4U)

+#define FMC_SDCRx_MWID_Msk         (0x3UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000030 */

+#define FMC_SDCRx_MWID             FMC_SDCRx_MWID_Msk                          /*!<NR[1:0] bits (Number of row bits) */

+#define FMC_SDCRx_MWID_0           (0x1UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000010 */

+#define FMC_SDCRx_MWID_1           (0x2UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000020 */

+

+#define FMC_SDCRx_NB_Pos           (6U)

+#define FMC_SDCRx_NB_Msk           (0x1UL << FMC_SDCRx_NB_Pos)                 /*!< 0x00000040 */

+#define FMC_SDCRx_NB               FMC_SDCRx_NB_Msk                            /*!<Number of internal bank */

+

+#define FMC_SDCRx_CAS_Pos          (7U)

+#define FMC_SDCRx_CAS_Msk          (0x3UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000180 */

+#define FMC_SDCRx_CAS              FMC_SDCRx_CAS_Msk                           /*!<CAS[1:0] bits (CAS latency) */

+#define FMC_SDCRx_CAS_0            (0x1UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000080 */

+#define FMC_SDCRx_CAS_1            (0x2UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000100 */

+

+#define FMC_SDCRx_WP_Pos           (9U)

+#define FMC_SDCRx_WP_Msk           (0x1UL << FMC_SDCRx_WP_Pos)                 /*!< 0x00000200 */

+#define FMC_SDCRx_WP               FMC_SDCRx_WP_Msk                            /*!<Write protection */

+

+#define FMC_SDCRx_SDCLK_Pos        (10U)

+#define FMC_SDCRx_SDCLK_Msk        (0x3UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000C00 */

+#define FMC_SDCRx_SDCLK            FMC_SDCRx_SDCLK_Msk                         /*!<SDRAM clock configuration */

+#define FMC_SDCRx_SDCLK_0          (0x1UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000400 */

+#define FMC_SDCRx_SDCLK_1          (0x2UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000800 */

+

+#define FMC_SDCRx_RBURST_Pos       (12U)

+#define FMC_SDCRx_RBURST_Msk       (0x1UL << FMC_SDCRx_RBURST_Pos)             /*!< 0x00001000 */

+#define FMC_SDCRx_RBURST           FMC_SDCRx_RBURST_Msk                        /*!<Read burst */

+

+#define FMC_SDCRx_RPIPE_Pos        (13U)

+#define FMC_SDCRx_RPIPE_Msk        (0x3UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00006000 */

+#define FMC_SDCRx_RPIPE            FMC_SDCRx_RPIPE_Msk                         /*!<Write protection */

+#define FMC_SDCRx_RPIPE_0          (0x1UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00002000 */

+#define FMC_SDCRx_RPIPE_1          (0x2UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00004000 */

+

+/******************  Bit definition for FMC_SDTRx(1,2) register  ******************/

+#define FMC_SDTRx_TMRD_Pos         (0U)

+#define FMC_SDTRx_TMRD_Msk         (0xFUL << FMC_SDTRx_TMRD_Pos)               /*!< 0x0000000F */

+#define FMC_SDTRx_TMRD             FMC_SDTRx_TMRD_Msk                          /*!<TMRD[3:0] bits (Load mode register to active) */

+#define FMC_SDTRx_TMRD_0           (0x1UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000001 */

+#define FMC_SDTRx_TMRD_1           (0x2UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000002 */

+#define FMC_SDTRx_TMRD_2           (0x4UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000004 */

+#define FMC_SDTRx_TMRD_3           (0x8UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000008 */

+

+#define FMC_SDTRx_TXSR_Pos         (4U)

+#define FMC_SDTRx_TXSR_Msk         (0xFUL << FMC_SDTRx_TXSR_Pos)               /*!< 0x000000F0 */

+#define FMC_SDTRx_TXSR             FMC_SDTRx_TXSR_Msk                          /*!<TXSR[3:0] bits (Exit self refresh) */

+#define FMC_SDTRx_TXSR_0           (0x1UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000010 */

+#define FMC_SDTRx_TXSR_1           (0x2UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000020 */

+#define FMC_SDTRx_TXSR_2           (0x4UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000040 */

+#define FMC_SDTRx_TXSR_3           (0x8UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000080 */

+

+#define FMC_SDTRx_TRAS_Pos         (8U)

+#define FMC_SDTRx_TRAS_Msk         (0xFUL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000F00 */

+#define FMC_SDTRx_TRAS             FMC_SDTRx_TRAS_Msk                          /*!<TRAS[3:0] bits (Self refresh time) */

+#define FMC_SDTRx_TRAS_0           (0x1UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000100 */

+#define FMC_SDTRx_TRAS_1           (0x2UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000200 */

+#define FMC_SDTRx_TRAS_2           (0x4UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000400 */

+#define FMC_SDTRx_TRAS_3           (0x8UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000800 */

+

+#define FMC_SDTRx_TRC_Pos          (12U)

+#define FMC_SDTRx_TRC_Msk          (0xFUL << FMC_SDTRx_TRC_Pos)                /*!< 0x0000F000 */

+#define FMC_SDTRx_TRC              FMC_SDTRx_TRC_Msk                           /*!<TRC[2:0] bits (Row cycle delay) */

+#define FMC_SDTRx_TRC_0            (0x1UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00001000 */

+#define FMC_SDTRx_TRC_1            (0x2UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00002000 */

+#define FMC_SDTRx_TRC_2            (0x4UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00004000 */

+

+#define FMC_SDTRx_TWR_Pos          (16U)

+#define FMC_SDTRx_TWR_Msk          (0xFUL << FMC_SDTRx_TWR_Pos)                /*!< 0x000F0000 */

+#define FMC_SDTRx_TWR              FMC_SDTRx_TWR_Msk                           /*!<TRC[2:0] bits (Write recovery delay) */

+#define FMC_SDTRx_TWR_0            (0x1UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00010000 */

+#define FMC_SDTRx_TWR_1            (0x2UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00020000 */

+#define FMC_SDTRx_TWR_2            (0x4UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00040000 */

+

+#define FMC_SDTRx_TRP_Pos          (20U)

+#define FMC_SDTRx_TRP_Msk          (0xFUL << FMC_SDTRx_TRP_Pos)                /*!< 0x00F00000 */

+#define FMC_SDTRx_TRP              FMC_SDTRx_TRP_Msk                           /*!<TRP[2:0] bits (Row precharge delay) */

+#define FMC_SDTRx_TRP_0            (0x1UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00100000 */

+#define FMC_SDTRx_TRP_1            (0x2UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00200000 */

+#define FMC_SDTRx_TRP_2            (0x4UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00400000 */

+

+#define FMC_SDTRx_TRCD_Pos         (24U)

+#define FMC_SDTRx_TRCD_Msk         (0xFUL << FMC_SDTRx_TRCD_Pos)               /*!< 0x0F000000 */

+#define FMC_SDTRx_TRCD             FMC_SDTRx_TRCD_Msk                          /*!<TRP[2:0] bits (Row to column delay) */

+#define FMC_SDTRx_TRCD_0           (0x1UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x01000000 */

+#define FMC_SDTRx_TRCD_1           (0x2UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x02000000 */

+#define FMC_SDTRx_TRCD_2           (0x4UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x04000000 */

+

+/******************  Bit definition for FMC_SDCMR register  ******************/

+#define FMC_SDCMR_MODE_Pos         (0U)

+#define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */

+#define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */

+#define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */

+#define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */

+#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */

+

+#define FMC_SDCMR_CTB2_Pos         (3U)

+#define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */

+#define FMC_SDCMR_CTB2             FMC_SDCMR_CTB2_Msk                          /*!<Command target 2 */

+

+#define FMC_SDCMR_CTB1_Pos         (4U)

+#define FMC_SDCMR_CTB1_Msk         (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */

+#define FMC_SDCMR_CTB1             FMC_SDCMR_CTB1_Msk                          /*!<Command target 1 */

+

+#define FMC_SDCMR_NRFS_Pos         (5U)

+#define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */

+#define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!<NRFS[3:0] bits (Number of auto-refresh) */

+#define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000020 */

+#define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000040 */

+#define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000080 */

+#define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000100 */

+

+#define FMC_SDCMR_MRD_Pos          (9U)

+#define FMC_SDCMR_MRD_Msk          (0x1FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */

+#define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!<MRD[12:0] bits (Mode register definition) */

+

+/******************  Bit definition for FMC_SDRTR register  ******************/

+#define FMC_SDRTR_CRE_Pos          (0U)

+#define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */

+#define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!<Clear refresh error flag */

+

+#define FMC_SDRTR_COUNT_Pos        (1U)

+#define FMC_SDRTR_COUNT_Msk        (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */

+#define FMC_SDRTR_COUNT            FMC_SDRTR_COUNT_Msk                         /*!<COUNT[12:0] bits (Refresh timer count) */

+

+#define FMC_SDRTR_REIE_Pos         (14U)

+#define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */

+#define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!<RES interupt enable */

+

+/******************  Bit definition for FMC_SDSR register  ******************/

+#define FMC_SDSR_RE_Pos            (0U)

+#define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */

+#define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!<Refresh error flag */

+

+#define FMC_SDSR_MODES1_Pos        (1U)

+#define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */

+#define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!<MODES1[1:0]bits (Status mode for bank 1) */

+#define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000002 */

+#define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000004 */

+

+#define FMC_SDSR_MODES2_Pos        (3U)

+#define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */

+#define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!<MODES2[1:0]bits (Status mode for bank 2) */

+#define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000008 */

+#define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000010 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                       Graphic MMU (GFXMMU)                                 */

+/*                                                                            */

+/******************************************************************************/

+/****************** Bits definition for GFXMMU_CR register ********************/

+#define GFXMMU_CR_B0OIE_Pos                (0U)

+#define GFXMMU_CR_B0OIE_Msk                (0x1UL << GFXMMU_CR_B0OIE_Pos)       /*!< 0x00000001 */

+#define GFXMMU_CR_B0OIE                    GFXMMU_CR_B0OIE_Msk                 /*!< Buffer 0 overflow interrupt enable */

+#define GFXMMU_CR_B1OIE_Pos                (1U)

+#define GFXMMU_CR_B1OIE_Msk                (0x1UL << GFXMMU_CR_B1OIE_Pos)       /*!< 0x00000002 */

+#define GFXMMU_CR_B1OIE                    GFXMMU_CR_B1OIE_Msk                 /*!< Buffer 1 overflow interrupt enable */

+#define GFXMMU_CR_B2OIE_Pos                (2U)

+#define GFXMMU_CR_B2OIE_Msk                (0x1UL << GFXMMU_CR_B2OIE_Pos)       /*!< 0x00000004 */

+#define GFXMMU_CR_B2OIE                    GFXMMU_CR_B2OIE_Msk                 /*!< Buffer 2 overflow interrupt enable */

+#define GFXMMU_CR_B3OIE_Pos                (3U)

+#define GFXMMU_CR_B3OIE_Msk                (0x1UL << GFXMMU_CR_B3OIE_Pos)       /*!< 0x00000008 */

+#define GFXMMU_CR_B3OIE                    GFXMMU_CR_B3OIE_Msk                 /*!< Buffer 3 overflow interrupt enable */

+#define GFXMMU_CR_AMEIE_Pos                (4U)

+#define GFXMMU_CR_AMEIE_Msk                (0x1UL << GFXMMU_CR_AMEIE_Pos)       /*!< 0x00000010 */

+#define GFXMMU_CR_AMEIE                    GFXMMU_CR_AMEIE_Msk                 /*!< AHB master error interrupt enable */

+#define GFXMMU_CR_192BM_Pos                (6U)

+#define GFXMMU_CR_192BM_Msk                (0x1UL << GFXMMU_CR_192BM_Pos)       /*!< 0x00000040 */

+#define GFXMMU_CR_192BM                    GFXMMU_CR_192BM_Msk                 /*!< 192 block mode */

+#define GFXMMU_CR_CE_Pos                   (7U)

+#define GFXMMU_CR_CE_Msk                   (0x1UL << GFXMMU_CR_CE_Pos)          /*!< 0x00000080 */

+#define GFXMMU_CR_CE                       GFXMMU_CR_CE_Msk                    /*!< Cache Enable */

+#define GFXMMU_CR_CL_Pos                   (8U)

+#define GFXMMU_CR_CL_Msk                   (0x1UL << GFXMMU_CR_CL_Pos)          /*!< 0x00000100 */

+#define GFXMMU_CR_CL                       GFXMMU_CR_CL_Msk                    /*!< Cache Lock */

+#define GFXMMU_CR_CLB_Pos                  (9U)

+#define GFXMMU_CR_CLB_Msk                  (0x3UL << GFXMMU_CR_CLB_Pos)         /*!< 0x00000600 */

+#define GFXMMU_CR_CLB                      GFXMMU_CR_CLB_Msk                   /*!< CLB[1:0]: Cache Lock Buffer */

+#define GFXMMU_CR_CLB_0                    (0x1UL << GFXMMU_CR_CLB_Pos)         /*!< Cache locked on buffer 1 */

+#define GFXMMU_CR_CLB_1                    (0x2UL << GFXMMU_CR_CLB_Pos)         /*!< Cache locked on buffer 2 */

+#define GFXMMU_CR_FC_Pos                   (11U)

+#define GFXMMU_CR_FC_Msk                   (0x1UL << GFXMMU_CR_FC_Pos)          /*!< 0x00000800 */

+#define GFXMMU_CR_FC                       GFXMMU_CR_FC_Msk                    /*!< Force Caching */

+#define GFXMMU_CR_PD_Pos                   (12U)

+#define GFXMMU_CR_PD_Msk                   (0x1UL << GFXMMU_CR_PD_Pos)          /*!< 0x00001000 */

+#define GFXMMU_CR_PD                       GFXMMU_CR_PD_Msk                    /*!< Prefetch Disable */

+#define GFXMMU_CR_OC_Pos                   (16U)

+#define GFXMMU_CR_OC_Msk                   (0x1UL << GFXMMU_CR_OC_Pos)          /*!< 0x00002000 */

+#define GFXMMU_CR_OC                       GFXMMU_CR_OC_Msk                    /*!< Outter Cachability */

+#define GFXMMU_CR_OB_Pos                   (17U)

+#define GFXMMU_CR_OB_Msk                   (0x1UL << GFXMMU_CR_OB_Pos)          /*!< 0x00002000 */

+#define GFXMMU_CR_OB                       GFXMMU_CR_OB_Msk                    /*!< Outter Bufferability */

+

+/****************** Bits definition for GFXMMU_SR register ********************/

+#define GFXMMU_SR_B0OF_Pos                 (0U)

+#define GFXMMU_SR_B0OF_Msk                 (0x1UL << GFXMMU_SR_B0OF_Pos)        /*!< 0x00000001 */

+#define GFXMMU_SR_B0OF                     GFXMMU_SR_B0OF_Msk                  /*!< Buffer 0 overflow flag */

+#define GFXMMU_SR_B1OF_Pos                 (1U)

+#define GFXMMU_SR_B1OF_Msk                 (0x1UL << GFXMMU_SR_B1OF_Pos)        /*!< 0x00000002 */

+#define GFXMMU_SR_B1OF                     GFXMMU_SR_B1OF_Msk                  /*!< Buffer 1 overflow flag */

+#define GFXMMU_SR_B2OF_Pos                 (2U)

+#define GFXMMU_SR_B2OF_Msk                 (0x1UL << GFXMMU_SR_B2OF_Pos)        /*!< 0x00000004 */

+#define GFXMMU_SR_B2OF                     GFXMMU_SR_B2OF_Msk                  /*!< Buffer 2 overflow flag */

+#define GFXMMU_SR_B3OF_Pos                 (3U)

+#define GFXMMU_SR_B3OF_Msk                 (0x1UL << GFXMMU_SR_B3OF_Pos)        /*!< 0x00000008 */

+#define GFXMMU_SR_B3OF                     GFXMMU_SR_B3OF_Msk                  /*!< Buffer 3 overflow flag */

+#define GFXMMU_SR_AMEF_Pos                 (4U)

+#define GFXMMU_SR_AMEF_Msk                 (0x1UL << GFXMMU_SR_AMEF_Pos)        /*!< 0x00000010 */

+#define GFXMMU_SR_AMEF                     GFXMMU_SR_AMEF_Msk                  /*!< AHB master error flag */

+

+/****************** Bits definition for GFXMMU_FCR register *******************/

+#define GFXMMU_FCR_CB0OF_Pos               (0U)

+#define GFXMMU_FCR_CB0OF_Msk               (0x1UL << GFXMMU_FCR_CB0OF_Pos)      /*!< 0x00000001 */

+#define GFXMMU_FCR_CB0OF                   GFXMMU_FCR_CB0OF_Msk                /*!< Clear buffer 0 overflow flag */

+#define GFXMMU_FCR_CB1OF_Pos               (1U)

+#define GFXMMU_FCR_CB1OF_Msk               (0x1UL << GFXMMU_FCR_CB1OF_Pos)      /*!< 0x00000002 */

+#define GFXMMU_FCR_CB1OF                   GFXMMU_FCR_CB1OF_Msk                /*!< Clear buffer 1 overflow flag */

+#define GFXMMU_FCR_CB2OF_Pos               (2U)

+#define GFXMMU_FCR_CB2OF_Msk               (0x1UL << GFXMMU_FCR_CB2OF_Pos)      /*!< 0x00000004 */

+#define GFXMMU_FCR_CB2OF                   GFXMMU_FCR_CB2OF_Msk                /*!< Clear buffer 2 overflow flag */

+#define GFXMMU_FCR_CB3OF_Pos               (3U)

+#define GFXMMU_FCR_CB3OF_Msk               (0x1UL << GFXMMU_FCR_CB3OF_Pos)      /*!< 0x00000008 */

+#define GFXMMU_FCR_CB3OF                   GFXMMU_FCR_CB3OF_Msk                /*!< Clear buffer 3 overflow flag */

+#define GFXMMU_FCR_CAMEF_Pos               (4U)

+#define GFXMMU_FCR_CAMEF_Msk               (0x1UL << GFXMMU_FCR_CAMEF_Pos)      /*!< 0x00000010 */

+#define GFXMMU_FCR_CAMEF                   GFXMMU_FCR_CAMEF_Msk                /*!< Clear AHB master error flag */

+

+/****************** Bits definition for GFXMMU_CCR register *******************/

+#define GFXMMU_CCR_FF_Pos                  (0U)

+#define GFXMMU_CCR_FF_Msk                  (0x1UL << GFXMMU_CCR_FF_Pos)         /*!< 0x00000001 */

+#define GFXMMU_CCR_FF                      GFXMMU_CCR_FF_Msk                   /*!< Clear buffer 0 overflow flag */

+#define GFXMMU_CCR_FI_Pos                  (1U)

+#define GFXMMU_CCR_FI_Msk                  (0x1UL << GFXMMU_CCR_FI_Pos)         /*!< 0x00000002 */

+#define GFXMMU_CCR_FI                      GFXMMU_CCR_FI_Msk                   /*!< Clear buffer 1 overflow flag */

+

+/****************** Bits definition for GFXMMU_DVR register *******************/

+#define GFXMMU_DVR_DV_Pos                  (0U)

+#define GFXMMU_DVR_DV_Msk                  (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos)  /*!< 0xFFFFFFFF */

+#define GFXMMU_DVR_DV                      GFXMMU_DVR_DV_Msk                   /*!< DV[31:0] bits (Default value) */

+

+/****************** Bits definition for GFXMMU_B0CR register ******************/

+#define GFXMMU_B0CR_PBO_Pos                (4U)

+#define GFXMMU_B0CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B0CR_PBO_Pos)   /*!< 0x007FFFF0 */

+#define GFXMMU_B0CR_PBO                    GFXMMU_B0CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */

+#define GFXMMU_B0CR_PBBA_Pos               (23U)

+#define GFXMMU_B0CR_PBBA_Msk               (0x1FFUL << GFXMMU_B0CR_PBBA_Pos)    /*!< 0xFF800000 */

+#define GFXMMU_B0CR_PBBA                   GFXMMU_B0CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */

+

+/****************** Bits definition for GFXMMU_B1CR register ******************/

+#define GFXMMU_B1CR_PBO_Pos                (4U)

+#define GFXMMU_B1CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos)   /*!< 0x007FFFF0 */

+#define GFXMMU_B1CR_PBO                    GFXMMU_B1CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */

+#define GFXMMU_B1CR_PBBA_Pos               (23U)

+#define GFXMMU_B1CR_PBBA_Msk               (0x1FFUL << GFXMMU_B1CR_PBBA_Pos)    /*!< 0xFF800000 */

+#define GFXMMU_B1CR_PBBA                   GFXMMU_B1CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */

+

+/****************** Bits definition for GFXMMU_B2CR register ******************/

+#define GFXMMU_B2CR_PBO_Pos                (4U)

+#define GFXMMU_B2CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B2CR_PBO_Pos)   /*!< 0x007FFFF0 */

+#define GFXMMU_B2CR_PBO                    GFXMMU_B2CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */

+#define GFXMMU_B2CR_PBBA_Pos               (23U)

+#define GFXMMU_B2CR_PBBA_Msk               (0x1FFUL << GFXMMU_B2CR_PBBA_Pos)    /*!< 0xFF800000 */

+#define GFXMMU_B2CR_PBBA                   GFXMMU_B2CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */

+

+/****************** Bits definition for GFXMMU_B3CR register ******************/

+#define GFXMMU_B3CR_PBO_Pos                (4U)

+#define GFXMMU_B3CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B3CR_PBO_Pos)   /*!< 0x007FFFF0 */

+#define GFXMMU_B3CR_PBO                    GFXMMU_B3CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */

+#define GFXMMU_B3CR_PBBA_Pos               (23U)

+#define GFXMMU_B3CR_PBBA_Msk               (0x1FFUL << GFXMMU_B3CR_PBBA_Pos)    /*!< 0xFF800000 */

+#define GFXMMU_B3CR_PBBA                   GFXMMU_B3CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */

+

+/****************** Bits definition for GFXMMU_LUTxL register *****************/

+#define GFXMMU_LUTxL_EN_Pos                (0U)

+#define GFXMMU_LUTxL_EN_Msk                (0x1UL << GFXMMU_LUTxL_EN_Pos)       /*!< 0x00000001 */

+#define GFXMMU_LUTxL_EN                    GFXMMU_LUTxL_EN_Msk                 /*!< Enable */

+#define GFXMMU_LUTxL_FVB_Pos               (8U)

+#define GFXMMU_LUTxL_FVB_Msk               (0xFFUL << GFXMMU_LUTxL_FVB_Pos)     /*!< 0x0000FF00 */

+#define GFXMMU_LUTxL_FVB                   GFXMMU_LUTxL_FVB_Msk                /*!< FVB[7:0] bits (First visible block) */

+#define GFXMMU_LUTxL_LVB_Pos               (16U)

+#define GFXMMU_LUTxL_LVB_Msk               (0xFFUL << GFXMMU_LUTxL_LVB_Pos)     /*!< 0x00FF0000 */

+#define GFXMMU_LUTxL_LVB                   GFXMMU_LUTxL_LVB_Msk                /*!< LVB[7:0] bits (Last visible block) */

+

+/****************** Bits definition for GFXMMU_LUTxH register *****************/

+#define GFXMMU_LUTxH_LO_Pos                (4U)

+#define GFXMMU_LUTxH_LO_Msk                (0x3FFFFUL << GFXMMU_LUTxH_LO_Pos)   /*!< 0x003FFFF0 */

+#define GFXMMU_LUTxH_LO                    GFXMMU_LUTxH_LO_Msk                 /*!< LO[21:4] bits (Line offset) */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            General Purpose I/O                             */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bits definition for GPIO_MODER register  *****************/

+#define GPIO_MODER_MODE0_Pos           (0U)

+#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */

+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk

+#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */

+#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */

+

+#define GPIO_MODER_MODE1_Pos           (2U)

+#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */

+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk

+#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */

+#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */

+

+#define GPIO_MODER_MODE2_Pos           (4U)

+#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */

+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk

+#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */

+#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */

+

+#define GPIO_MODER_MODE3_Pos           (6U)

+#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */

+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk

+#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */

+#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */

+

+#define GPIO_MODER_MODE4_Pos           (8U)

+#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */

+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk

+#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */

+#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */

+

+#define GPIO_MODER_MODE5_Pos           (10U)

+#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */

+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk

+#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */

+#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */

+

+#define GPIO_MODER_MODE6_Pos           (12U)

+#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */

+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk

+#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */

+#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */

+

+#define GPIO_MODER_MODE7_Pos           (14U)

+#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */

+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk

+#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */

+#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */

+

+#define GPIO_MODER_MODE8_Pos           (16U)

+#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */

+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk

+#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */

+#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */

+

+#define GPIO_MODER_MODE9_Pos           (18U)

+#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */

+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk

+#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */

+#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */

+

+#define GPIO_MODER_MODE10_Pos          (20U)

+#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */

+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk

+#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */

+#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */

+

+#define GPIO_MODER_MODE11_Pos          (22U)

+#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */

+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk

+#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */

+#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */

+

+#define GPIO_MODER_MODE12_Pos          (24U)

+#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */

+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk

+#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */

+#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */

+

+#define GPIO_MODER_MODE13_Pos          (26U)

+#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */

+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk

+#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */

+#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */

+

+#define GPIO_MODER_MODE14_Pos          (28U)

+#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */

+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk

+#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */

+#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */

+

+#define GPIO_MODER_MODE15_Pos          (30U)

+#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */

+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk

+#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */

+#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_OTYPER register  ****************/

+#define GPIO_OTYPER_OT0_Pos            (0U)

+#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */

+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk

+#define GPIO_OTYPER_OT1_Pos            (1U)

+#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */

+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk

+#define GPIO_OTYPER_OT2_Pos            (2U)

+#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */

+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk

+#define GPIO_OTYPER_OT3_Pos            (3U)

+#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */

+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk

+#define GPIO_OTYPER_OT4_Pos            (4U)

+#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */

+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk

+#define GPIO_OTYPER_OT5_Pos            (5U)

+#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */

+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk

+#define GPIO_OTYPER_OT6_Pos            (6U)

+#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */

+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk

+#define GPIO_OTYPER_OT7_Pos            (7U)

+#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */

+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk

+#define GPIO_OTYPER_OT8_Pos            (8U)

+#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */

+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk

+#define GPIO_OTYPER_OT9_Pos            (9U)

+#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */

+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk

+#define GPIO_OTYPER_OT10_Pos           (10U)

+#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */

+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk

+#define GPIO_OTYPER_OT11_Pos           (11U)

+#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */

+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk

+#define GPIO_OTYPER_OT12_Pos           (12U)

+#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */

+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk

+#define GPIO_OTYPER_OT13_Pos           (13U)

+#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */

+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk

+#define GPIO_OTYPER_OT14_Pos           (14U)

+#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */

+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk

+#define GPIO_OTYPER_OT15_Pos           (15U)

+#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */

+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk

+

+/******************  Bits definition for GPIO_OSPEEDR register  ***************/

+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)

+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */

+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk

+#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */

+#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */

+

+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)

+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */

+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk

+#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */

+#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */

+

+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)

+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */

+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk

+#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */

+#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */

+

+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)

+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */

+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk

+#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */

+#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */

+

+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)

+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */

+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk

+#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */

+#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */

+

+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)

+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */

+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk

+#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */

+#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */

+

+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)

+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */

+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk

+#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */

+#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */

+

+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)

+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */

+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk

+#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */

+#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */

+

+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)

+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */

+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk

+#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */

+#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */

+

+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)

+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */

+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk

+#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */

+#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */

+

+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)

+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */

+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk

+#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */

+#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */

+

+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)

+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */

+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk

+#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */

+#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */

+

+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)

+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */

+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk

+#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */

+#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */

+

+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)

+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */

+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk

+#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */

+#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */

+

+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)

+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */

+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk

+#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */

+#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */

+

+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)

+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */

+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk

+#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */

+#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_PUPDR register  *****************/

+#define GPIO_PUPDR_PUPD0_Pos           (0U)

+#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */

+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk

+#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */

+#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */

+

+#define GPIO_PUPDR_PUPD1_Pos           (2U)

+#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */

+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk

+#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */

+#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */

+

+#define GPIO_PUPDR_PUPD2_Pos           (4U)

+#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */

+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk

+#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */

+#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */

+

+#define GPIO_PUPDR_PUPD3_Pos           (6U)

+#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */

+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk

+#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */

+#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */

+

+#define GPIO_PUPDR_PUPD4_Pos           (8U)

+#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */

+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk

+#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */

+#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */

+

+#define GPIO_PUPDR_PUPD5_Pos           (10U)

+#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */

+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk

+#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */

+#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */

+

+#define GPIO_PUPDR_PUPD6_Pos           (12U)

+#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */

+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk

+#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */

+#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */

+

+#define GPIO_PUPDR_PUPD7_Pos           (14U)

+#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */

+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk

+#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */

+#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */

+

+#define GPIO_PUPDR_PUPD8_Pos           (16U)

+#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */

+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk

+#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */

+#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */

+

+#define GPIO_PUPDR_PUPD9_Pos           (18U)

+#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */

+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk

+#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */

+#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */

+

+#define GPIO_PUPDR_PUPD10_Pos          (20U)

+#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */

+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk

+#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */

+#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */

+

+#define GPIO_PUPDR_PUPD11_Pos          (22U)

+#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */

+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk

+#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */

+#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */

+

+#define GPIO_PUPDR_PUPD12_Pos          (24U)

+#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */

+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk

+#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */

+#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */

+

+#define GPIO_PUPDR_PUPD13_Pos          (26U)

+#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */

+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk

+#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */

+#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */

+

+#define GPIO_PUPDR_PUPD14_Pos          (28U)

+#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */

+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk

+#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */

+#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */

+

+#define GPIO_PUPDR_PUPD15_Pos          (30U)

+#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */

+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk

+#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */

+#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_IDR register  *******************/

+#define GPIO_IDR_ID0_Pos               (0U)

+#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */

+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk

+#define GPIO_IDR_ID1_Pos               (1U)

+#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */

+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk

+#define GPIO_IDR_ID2_Pos               (2U)

+#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */

+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk

+#define GPIO_IDR_ID3_Pos               (3U)

+#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */

+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk

+#define GPIO_IDR_ID4_Pos               (4U)

+#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */

+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk

+#define GPIO_IDR_ID5_Pos               (5U)

+#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */

+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk

+#define GPIO_IDR_ID6_Pos               (6U)

+#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */

+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk

+#define GPIO_IDR_ID7_Pos               (7U)

+#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */

+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk

+#define GPIO_IDR_ID8_Pos               (8U)

+#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */

+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk

+#define GPIO_IDR_ID9_Pos               (9U)

+#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */

+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk

+#define GPIO_IDR_ID10_Pos              (10U)

+#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */

+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk

+#define GPIO_IDR_ID11_Pos              (11U)

+#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */

+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk

+#define GPIO_IDR_ID12_Pos              (12U)

+#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */

+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk

+#define GPIO_IDR_ID13_Pos              (13U)

+#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */

+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk

+#define GPIO_IDR_ID14_Pos              (14U)

+#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */

+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk

+#define GPIO_IDR_ID15_Pos              (15U)

+#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */

+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk

+

+/******************  Bits definition for GPIO_ODR register  *******************/

+#define GPIO_ODR_OD0_Pos               (0U)

+#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */

+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk

+#define GPIO_ODR_OD1_Pos               (1U)

+#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */

+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk

+#define GPIO_ODR_OD2_Pos               (2U)

+#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */

+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk

+#define GPIO_ODR_OD3_Pos               (3U)

+#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */

+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk

+#define GPIO_ODR_OD4_Pos               (4U)

+#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */

+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk

+#define GPIO_ODR_OD5_Pos               (5U)

+#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */

+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk

+#define GPIO_ODR_OD6_Pos               (6U)

+#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */

+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk

+#define GPIO_ODR_OD7_Pos               (7U)

+#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */

+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk

+#define GPIO_ODR_OD8_Pos               (8U)

+#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */

+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk

+#define GPIO_ODR_OD9_Pos               (9U)

+#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */

+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk

+#define GPIO_ODR_OD10_Pos              (10U)

+#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */

+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk

+#define GPIO_ODR_OD11_Pos              (11U)

+#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */

+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk

+#define GPIO_ODR_OD12_Pos              (12U)

+#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */

+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk

+#define GPIO_ODR_OD13_Pos              (13U)

+#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */

+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk

+#define GPIO_ODR_OD14_Pos              (14U)

+#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */

+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk

+#define GPIO_ODR_OD15_Pos              (15U)

+#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */

+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk

+

+/******************  Bits definition for GPIO_BSRR register  ******************/

+#define GPIO_BSRR_BS0_Pos              (0U)

+#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */

+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk

+#define GPIO_BSRR_BS1_Pos              (1U)

+#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */

+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk

+#define GPIO_BSRR_BS2_Pos              (2U)

+#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */

+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk

+#define GPIO_BSRR_BS3_Pos              (3U)

+#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */

+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk

+#define GPIO_BSRR_BS4_Pos              (4U)

+#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */

+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk

+#define GPIO_BSRR_BS5_Pos              (5U)

+#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */

+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk

+#define GPIO_BSRR_BS6_Pos              (6U)

+#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */

+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk

+#define GPIO_BSRR_BS7_Pos              (7U)

+#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */

+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk

+#define GPIO_BSRR_BS8_Pos              (8U)

+#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */

+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk

+#define GPIO_BSRR_BS9_Pos              (9U)

+#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */

+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk

+#define GPIO_BSRR_BS10_Pos             (10U)

+#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */

+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk

+#define GPIO_BSRR_BS11_Pos             (11U)

+#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */

+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk

+#define GPIO_BSRR_BS12_Pos             (12U)

+#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */

+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk

+#define GPIO_BSRR_BS13_Pos             (13U)

+#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */

+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk

+#define GPIO_BSRR_BS14_Pos             (14U)

+#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */

+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk

+#define GPIO_BSRR_BS15_Pos             (15U)

+#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */

+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk

+#define GPIO_BSRR_BR0_Pos              (16U)

+#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */

+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk

+#define GPIO_BSRR_BR1_Pos              (17U)

+#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */

+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk

+#define GPIO_BSRR_BR2_Pos              (18U)

+#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */

+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk

+#define GPIO_BSRR_BR3_Pos              (19U)

+#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */

+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk

+#define GPIO_BSRR_BR4_Pos              (20U)

+#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */

+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk

+#define GPIO_BSRR_BR5_Pos              (21U)

+#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */

+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk

+#define GPIO_BSRR_BR6_Pos              (22U)

+#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */

+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk

+#define GPIO_BSRR_BR7_Pos              (23U)

+#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */

+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk

+#define GPIO_BSRR_BR8_Pos              (24U)

+#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */

+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk

+#define GPIO_BSRR_BR9_Pos              (25U)

+#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */

+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk

+#define GPIO_BSRR_BR10_Pos             (26U)

+#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */

+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk

+#define GPIO_BSRR_BR11_Pos             (27U)

+#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */

+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk

+#define GPIO_BSRR_BR12_Pos             (28U)

+#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */

+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk

+#define GPIO_BSRR_BR13_Pos             (29U)

+#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */

+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk

+#define GPIO_BSRR_BR14_Pos             (30U)

+#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */

+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk

+#define GPIO_BSRR_BR15_Pos             (31U)

+#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */

+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk

+

+/****************** Bit definition for GPIO_LCKR register *********************/

+#define GPIO_LCKR_LCK0_Pos             (0U)

+#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */

+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk

+#define GPIO_LCKR_LCK1_Pos             (1U)

+#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */

+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk

+#define GPIO_LCKR_LCK2_Pos             (2U)

+#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */

+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk

+#define GPIO_LCKR_LCK3_Pos             (3U)

+#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */

+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk

+#define GPIO_LCKR_LCK4_Pos             (4U)

+#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */

+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk

+#define GPIO_LCKR_LCK5_Pos             (5U)

+#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */

+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk

+#define GPIO_LCKR_LCK6_Pos             (6U)

+#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */

+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk

+#define GPIO_LCKR_LCK7_Pos             (7U)

+#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */

+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk

+#define GPIO_LCKR_LCK8_Pos             (8U)

+#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */

+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk

+#define GPIO_LCKR_LCK9_Pos             (9U)

+#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */

+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk

+#define GPIO_LCKR_LCK10_Pos            (10U)

+#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */

+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk

+#define GPIO_LCKR_LCK11_Pos            (11U)

+#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */

+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk

+#define GPIO_LCKR_LCK12_Pos            (12U)

+#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */

+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk

+#define GPIO_LCKR_LCK13_Pos            (13U)

+#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */

+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk

+#define GPIO_LCKR_LCK14_Pos            (14U)

+#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */

+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk

+#define GPIO_LCKR_LCK15_Pos            (15U)

+#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */

+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk

+#define GPIO_LCKR_LCKK_Pos             (16U)

+#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */

+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk

+

+/****************** Bit definition for GPIO_AFRL register  ********************/

+#define GPIO_AFRL_AFSEL0_Pos           (0U)

+#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */

+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk

+#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */

+#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */

+#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */

+#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */

+#define GPIO_AFRL_AFSEL1_Pos           (4U)

+#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */

+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk

+#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */

+#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */

+#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */

+#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */

+#define GPIO_AFRL_AFSEL2_Pos           (8U)

+#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */

+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk

+#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */

+#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */

+#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */

+#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */

+#define GPIO_AFRL_AFSEL3_Pos           (12U)

+#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */

+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk

+#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */

+#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */

+#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */

+#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */

+#define GPIO_AFRL_AFSEL4_Pos           (16U)

+#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */

+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk

+#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */

+#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */

+#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */

+#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */

+#define GPIO_AFRL_AFSEL5_Pos           (20U)

+#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */

+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk

+#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */

+#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */

+#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */

+#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */

+#define GPIO_AFRL_AFSEL6_Pos           (24U)

+#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */

+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk

+#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */

+#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */

+#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */

+#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */

+#define GPIO_AFRL_AFSEL7_Pos           (28U)

+#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */

+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk

+#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */

+#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */

+#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */

+#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */

+

+/* Legacy defines */

+#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0

+#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1

+#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2

+#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3

+#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4

+#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5

+#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6

+#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7

+

+/****************** Bit definition for GPIO_AFRH register  ********************/

+#define GPIO_AFRH_AFSEL8_Pos           (0U)

+#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */

+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk

+#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */

+#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */

+#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */

+#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */

+#define GPIO_AFRH_AFSEL9_Pos           (4U)

+#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */

+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk

+#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */

+#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */

+#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */

+#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */

+#define GPIO_AFRH_AFSEL10_Pos          (8U)

+#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */

+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk

+#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */

+#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */

+#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */

+#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */

+#define GPIO_AFRH_AFSEL11_Pos          (12U)

+#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */

+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk

+#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */

+#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */

+#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */

+#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */

+#define GPIO_AFRH_AFSEL12_Pos          (16U)

+#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */

+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk

+#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */

+#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */

+#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */

+#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */

+#define GPIO_AFRH_AFSEL13_Pos          (20U)

+#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */

+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk

+#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */

+#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */

+#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */

+#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */

+#define GPIO_AFRH_AFSEL14_Pos          (24U)

+#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */

+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk

+#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */

+#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */

+#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */

+#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */

+#define GPIO_AFRH_AFSEL15_Pos          (28U)

+#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */

+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk

+#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */

+#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */

+#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */

+#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */

+

+/* Legacy defines */

+#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8

+#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9

+#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10

+#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11

+#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12

+#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13

+#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14

+#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15

+

+/******************************************************************************/

+/*                                                                            */

+/*                        HSEM HW Semaphore                                   */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for HSEM_R register  ********************/

+#define HSEM_R_PROCID_Pos         (0U)

+#define HSEM_R_PROCID_Msk         (0xFFUL << HSEM_R_PROCID_Pos)                /*!< 0x000000FF */

+#define HSEM_R_PROCID             HSEM_R_PROCID_Msk                            /*!<Semaphore ProcessID */

+#define HSEM_R_COREID_Pos         (8U)

+#define HSEM_R_COREID_Msk         (0xFFUL << HSEM_R_COREID_Pos)                /*!< 0x0000FF00 */

+#define HSEM_R_COREID             HSEM_R_COREID_Msk                            /*!<Semaphore CoreID.   */

+#define HSEM_R_LOCK_Pos           (31U)

+#define HSEM_R_LOCK_Msk           (0x1UL << HSEM_R_LOCK_Pos)                   /*!< 0x80000000 */

+#define HSEM_R_LOCK               HSEM_R_LOCK_Msk                              /*!<Lock indication.    */

+

+/********************  Bit definition for HSEM_RLR register  ******************/

+#define HSEM_RLR_PROCID_Pos       (0U)

+#define HSEM_RLR_PROCID_Msk       (0xFFUL << HSEM_RLR_PROCID_Pos)              /*!< 0x000000FF */

+#define HSEM_RLR_PROCID           HSEM_RLR_PROCID_Msk                          /*!<Semaphore ProcessID */

+#define HSEM_RLR_COREID_Pos       (8U)

+#define HSEM_RLR_COREID_Msk       (0xFFUL << HSEM_RLR_COREID_Pos)              /*!< 0x0000FF00 */

+#define HSEM_RLR_COREID           HSEM_RLR_COREID_Msk                          /*!<Semaphore CoreID.   */

+#define HSEM_RLR_LOCK_Pos         (31U)

+#define HSEM_RLR_LOCK_Msk         (0x1UL << HSEM_RLR_LOCK_Pos)                 /*!< 0x80000000 */

+#define HSEM_RLR_LOCK             HSEM_RLR_LOCK_Msk                            /*!<Lock indication.    */

+

+/********************  Bit definition for HSEM_C1IER register  *****************/

+#define HSEM_C1IER_ISE0_Pos       (0U)

+#define HSEM_C1IER_ISE0_Msk       (0x1UL << HSEM_C1IER_ISE0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1IER_ISE0           HSEM_C1IER_ISE0_Msk                          /*!<semaphore 0 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE1_Pos       (1U)

+#define HSEM_C1IER_ISE1_Msk       (0x1UL << HSEM_C1IER_ISE1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1IER_ISE1           HSEM_C1IER_ISE1_Msk                          /*!<semaphore 1 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE2_Pos       (2U)

+#define HSEM_C1IER_ISE2_Msk       (0x1UL << HSEM_C1IER_ISE2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1IER_ISE2           HSEM_C1IER_ISE2_Msk                          /*!<semaphore 2 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE3_Pos       (3U)

+#define HSEM_C1IER_ISE3_Msk       (0x1UL << HSEM_C1IER_ISE3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1IER_ISE3           HSEM_C1IER_ISE3_Msk                          /*!<semaphore 3 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE4_Pos       (4U)

+#define HSEM_C1IER_ISE4_Msk       (0x1UL << HSEM_C1IER_ISE4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1IER_ISE4           HSEM_C1IER_ISE4_Msk                          /*!<semaphore 4 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE5_Pos       (5U)

+#define HSEM_C1IER_ISE5_Msk       (0x1UL << HSEM_C1IER_ISE5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1IER_ISE5           HSEM_C1IER_ISE5_Msk                          /*!<semaphore 5 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE6_Pos       (6U)

+#define HSEM_C1IER_ISE6_Msk       (0x1UL << HSEM_C1IER_ISE6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1IER_ISE6           HSEM_C1IER_ISE6_Msk                          /*!<semaphore 6 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE7_Pos       (7U)

+#define HSEM_C1IER_ISE7_Msk       (0x1UL << HSEM_C1IER_ISE7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1IER_ISE7           HSEM_C1IER_ISE7_Msk                          /*!<semaphore 7 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE8_Pos       (8U)

+#define HSEM_C1IER_ISE8_Msk       (0x1UL << HSEM_C1IER_ISE8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1IER_ISE8           HSEM_C1IER_ISE8_Msk                          /*!<semaphore 8 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE9_Pos       (9U)

+#define HSEM_C1IER_ISE9_Msk       (0x1UL << HSEM_C1IER_ISE9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1IER_ISE9           HSEM_C1IER_ISE9_Msk                          /*!<semaphore 9 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE10_Pos      (10U)

+#define HSEM_C1IER_ISE10_Msk      (0x1UL << HSEM_C1IER_ISE10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1IER_ISE10          HSEM_C1IER_ISE10_Msk                         /*!<semaphore 10 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE11_Pos      (11U)

+#define HSEM_C1IER_ISE11_Msk      (0x1UL << HSEM_C1IER_ISE11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1IER_ISE11          HSEM_C1IER_ISE11_Msk                         /*!<semaphore 11 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE12_Pos      (12U)

+#define HSEM_C1IER_ISE12_Msk      (0x1UL << HSEM_C1IER_ISE12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1IER_ISE12          HSEM_C1IER_ISE12_Msk                         /*!<semaphore 12 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE13_Pos      (13U)

+#define HSEM_C1IER_ISE13_Msk      (0x1UL << HSEM_C1IER_ISE13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1IER_ISE13          HSEM_C1IER_ISE13_Msk                         /*!<semaphore 13 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE14_Pos      (14U)

+#define HSEM_C1IER_ISE14_Msk      (0x1UL << HSEM_C1IER_ISE14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1IER_ISE14          HSEM_C1IER_ISE14_Msk                         /*!<semaphore 14 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE15_Pos      (15U)

+#define HSEM_C1IER_ISE15_Msk      (0x1UL << HSEM_C1IER_ISE15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1IER_ISE15          HSEM_C1IER_ISE15_Msk                         /*!<semaphore 15 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE16_Pos      (16U)

+#define HSEM_C1IER_ISE16_Msk      (0x1UL << HSEM_C1IER_ISE16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1IER_ISE16          HSEM_C1IER_ISE16_Msk                         /*!<semaphore 16 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE17_Pos      (17U)

+#define HSEM_C1IER_ISE17_Msk      (0x1UL << HSEM_C1IER_ISE17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1IER_ISE17          HSEM_C1IER_ISE17_Msk                         /*!<semaphore 17 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE18_Pos      (18U)

+#define HSEM_C1IER_ISE18_Msk      (0x1UL << HSEM_C1IER_ISE18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1IER_ISE18          HSEM_C1IER_ISE18_Msk                         /*!<semaphore 18 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE19_Pos      (19U)

+#define HSEM_C1IER_ISE19_Msk      (0x1UL << HSEM_C1IER_ISE19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1IER_ISE19          HSEM_C1IER_ISE19_Msk                         /*!<semaphore 19 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE20_Pos      (20U)

+#define HSEM_C1IER_ISE20_Msk      (0x1UL << HSEM_C1IER_ISE20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1IER_ISE20          HSEM_C1IER_ISE20_Msk                         /*!<semaphore 20 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE21_Pos      (21U)

+#define HSEM_C1IER_ISE21_Msk      (0x1UL << HSEM_C1IER_ISE21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1IER_ISE21          HSEM_C1IER_ISE21_Msk                         /*!<semaphore 21 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE22_Pos      (22U)

+#define HSEM_C1IER_ISE22_Msk      (0x1UL << HSEM_C1IER_ISE22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1IER_ISE22          HSEM_C1IER_ISE22_Msk                         /*!<semaphore 22 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE23_Pos      (23U)

+#define HSEM_C1IER_ISE23_Msk      (0x1UL << HSEM_C1IER_ISE23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1IER_ISE23          HSEM_C1IER_ISE23_Msk                         /*!<semaphore 23 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE24_Pos      (24U)

+#define HSEM_C1IER_ISE24_Msk      (0x1UL << HSEM_C1IER_ISE24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1IER_ISE24          HSEM_C1IER_ISE24_Msk                         /*!<semaphore 24 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE25_Pos      (25U)

+#define HSEM_C1IER_ISE25_Msk      (0x1UL << HSEM_C1IER_ISE25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1IER_ISE25          HSEM_C1IER_ISE25_Msk                         /*!<semaphore 25 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE26_Pos      (26U)

+#define HSEM_C1IER_ISE26_Msk      (0x1UL << HSEM_C1IER_ISE26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1IER_ISE26          HSEM_C1IER_ISE26_Msk                         /*!<semaphore 26 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE27_Pos      (27U)

+#define HSEM_C1IER_ISE27_Msk      (0x1UL << HSEM_C1IER_ISE27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1IER_ISE27          HSEM_C1IER_ISE27_Msk                         /*!<semaphore 27 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE28_Pos      (28U)

+#define HSEM_C1IER_ISE28_Msk      (0x1UL << HSEM_C1IER_ISE28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1IER_ISE28          HSEM_C1IER_ISE28_Msk                         /*!<semaphore 28 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE29_Pos      (29U)

+#define HSEM_C1IER_ISE29_Msk      (0x1UL << HSEM_C1IER_ISE29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1IER_ISE29          HSEM_C1IER_ISE29_Msk                         /*!<semaphore 29 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE30_Pos      (30U)

+#define HSEM_C1IER_ISE30_Msk      (0x1UL << HSEM_C1IER_ISE30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1IER_ISE30          HSEM_C1IER_ISE30_Msk                         /*!<semaphore 30 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE31_Pos      (31U)

+#define HSEM_C1IER_ISE31_Msk      (0x1UL << HSEM_C1IER_ISE31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1IER_ISE31          HSEM_C1IER_ISE31_Msk                         /*!<semaphore 31 interrupt 0 enable bit. */

+

+/********************  Bit definition for HSEM_C1ICR register  *****************/

+#define HSEM_C1ICR_ISC0_Pos       (0U)

+#define HSEM_C1ICR_ISC0_Msk       (0x1UL << HSEM_C1ICR_ISC0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1ICR_ISC0           HSEM_C1ICR_ISC0_Msk                          /*!<semaphore 0 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC1_Pos       (1U)

+#define HSEM_C1ICR_ISC1_Msk       (0x1UL << HSEM_C1ICR_ISC1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1ICR_ISC1           HSEM_C1ICR_ISC1_Msk                          /*!<semaphore 1 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC2_Pos       (2U)

+#define HSEM_C1ICR_ISC2_Msk       (0x1UL << HSEM_C1ICR_ISC2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1ICR_ISC2           HSEM_C1ICR_ISC2_Msk                          /*!<semaphore 2 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC3_Pos       (3U)

+#define HSEM_C1ICR_ISC3_Msk       (0x1UL << HSEM_C1ICR_ISC3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1ICR_ISC3           HSEM_C1ICR_ISC3_Msk                          /*!<semaphore 3 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC4_Pos       (4U)

+#define HSEM_C1ICR_ISC4_Msk       (0x1UL << HSEM_C1ICR_ISC4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1ICR_ISC4           HSEM_C1ICR_ISC4_Msk                          /*!<semaphore 4 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC5_Pos       (5U)

+#define HSEM_C1ICR_ISC5_Msk       (0x1UL << HSEM_C1ICR_ISC5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1ICR_ISC5           HSEM_C1ICR_ISC5_Msk                          /*!<semaphore 5 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC6_Pos       (6U)

+#define HSEM_C1ICR_ISC6_Msk       (0x1UL << HSEM_C1ICR_ISC6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1ICR_ISC6           HSEM_C1ICR_ISC6_Msk                          /*!<semaphore 6 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC7_Pos       (7U)

+#define HSEM_C1ICR_ISC7_Msk       (0x1UL << HSEM_C1ICR_ISC7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1ICR_ISC7           HSEM_C1ICR_ISC7_Msk                          /*!<semaphore 7 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC8_Pos       (8U)

+#define HSEM_C1ICR_ISC8_Msk       (0x1UL << HSEM_C1ICR_ISC8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1ICR_ISC8           HSEM_C1ICR_ISC8_Msk                          /*!<semaphore 8 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC9_Pos       (9U)

+#define HSEM_C1ICR_ISC9_Msk       (0x1UL << HSEM_C1ICR_ISC9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1ICR_ISC9           HSEM_C1ICR_ISC9_Msk                          /*!<semaphore 9 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC10_Pos      (10U)

+#define HSEM_C1ICR_ISC10_Msk      (0x1UL << HSEM_C1ICR_ISC10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1ICR_ISC10          HSEM_C1ICR_ISC10_Msk                         /*!<semaphore 10 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC11_Pos      (11U)

+#define HSEM_C1ICR_ISC11_Msk      (0x1UL << HSEM_C1ICR_ISC11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1ICR_ISC11          HSEM_C1ICR_ISC11_Msk                         /*!<semaphore 11 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC12_Pos      (12U)

+#define HSEM_C1ICR_ISC12_Msk      (0x1UL << HSEM_C1ICR_ISC12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1ICR_ISC12          HSEM_C1ICR_ISC12_Msk                         /*!<semaphore 12 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC13_Pos      (13U)

+#define HSEM_C1ICR_ISC13_Msk      (0x1UL << HSEM_C1ICR_ISC13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1ICR_ISC13          HSEM_C1ICR_ISC13_Msk                         /*!<semaphore 13 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC14_Pos      (14U)

+#define HSEM_C1ICR_ISC14_Msk      (0x1UL << HSEM_C1ICR_ISC14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1ICR_ISC14          HSEM_C1ICR_ISC14_Msk                         /*!<semaphore 14 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC15_Pos      (15U)

+#define HSEM_C1ICR_ISC15_Msk      (0x1UL << HSEM_C1ICR_ISC15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1ICR_ISC15          HSEM_C1ICR_ISC15_Msk                         /*!<semaphore 15 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC16_Pos      (16U)

+#define HSEM_C1ICR_ISC16_Msk      (0x1UL << HSEM_C1ICR_ISC16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1ICR_ISC16          HSEM_C1ICR_ISC16_Msk                         /*!<semaphore 16 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC17_Pos      (17U)

+#define HSEM_C1ICR_ISC17_Msk      (0x1UL << HSEM_C1ICR_ISC17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1ICR_ISC17          HSEM_C1ICR_ISC17_Msk                         /*!<semaphore 17 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC18_Pos      (18U)

+#define HSEM_C1ICR_ISC18_Msk      (0x1UL << HSEM_C1ICR_ISC18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1ICR_ISC18          HSEM_C1ICR_ISC18_Msk                         /*!<semaphore 18 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC19_Pos      (19U)

+#define HSEM_C1ICR_ISC19_Msk      (0x1UL << HSEM_C1ICR_ISC19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1ICR_ISC19          HSEM_C1ICR_ISC19_Msk                         /*!<semaphore 19 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC20_Pos      (20U)

+#define HSEM_C1ICR_ISC20_Msk      (0x1UL << HSEM_C1ICR_ISC20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1ICR_ISC20          HSEM_C1ICR_ISC20_Msk                         /*!<semaphore 20 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC21_Pos      (21U)

+#define HSEM_C1ICR_ISC21_Msk      (0x1UL << HSEM_C1ICR_ISC21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1ICR_ISC21          HSEM_C1ICR_ISC21_Msk                         /*!<semaphore 21 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC22_Pos      (22U)

+#define HSEM_C1ICR_ISC22_Msk      (0x1UL << HSEM_C1ICR_ISC22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1ICR_ISC22          HSEM_C1ICR_ISC22_Msk                         /*!<semaphore 22 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC23_Pos      (23U)

+#define HSEM_C1ICR_ISC23_Msk      (0x1UL << HSEM_C1ICR_ISC23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1ICR_ISC23          HSEM_C1ICR_ISC23_Msk                         /*!<semaphore 23 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC24_Pos      (24U)

+#define HSEM_C1ICR_ISC24_Msk      (0x1UL << HSEM_C1ICR_ISC24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1ICR_ISC24          HSEM_C1ICR_ISC24_Msk                         /*!<semaphore 24 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC25_Pos      (25U)

+#define HSEM_C1ICR_ISC25_Msk      (0x1UL << HSEM_C1ICR_ISC25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1ICR_ISC25          HSEM_C1ICR_ISC25_Msk                         /*!<semaphore 25 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC26_Pos      (26U)

+#define HSEM_C1ICR_ISC26_Msk      (0x1UL << HSEM_C1ICR_ISC26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1ICR_ISC26          HSEM_C1ICR_ISC26_Msk                         /*!<semaphore 26 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC27_Pos      (27U)

+#define HSEM_C1ICR_ISC27_Msk      (0x1UL << HSEM_C1ICR_ISC27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1ICR_ISC27          HSEM_C1ICR_ISC27_Msk                         /*!<semaphore 27 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC28_Pos      (28U)

+#define HSEM_C1ICR_ISC28_Msk      (0x1UL << HSEM_C1ICR_ISC28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1ICR_ISC28          HSEM_C1ICR_ISC28_Msk                         /*!<semaphore 28 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC29_Pos      (29U)

+#define HSEM_C1ICR_ISC29_Msk      (0x1UL << HSEM_C1ICR_ISC29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1ICR_ISC29          HSEM_C1ICR_ISC29_Msk                         /*!<semaphore 29 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC30_Pos      (30U)

+#define HSEM_C1ICR_ISC30_Msk      (0x1UL << HSEM_C1ICR_ISC30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1ICR_ISC30          HSEM_C1ICR_ISC30_Msk                         /*!<semaphore 30 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC31_Pos      (31U)

+#define HSEM_C1ICR_ISC31_Msk      (0x1UL << HSEM_C1ICR_ISC31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1ICR_ISC31          HSEM_C1ICR_ISC31_Msk                         /*!<semaphore 31 interrupt 0 clear bit. */

+

+/********************  Bit definition for HSEM_C1ISR register  *****************/

+#define HSEM_C1ISR_ISF0_Pos       (0U)

+#define HSEM_C1ISR_ISF0_Msk       (0x1UL << HSEM_C1ISR_ISF0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1ISR_ISF0           HSEM_C1ISR_ISF0_Msk                          /*!<semaphore 0 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF1_Pos       (1U)

+#define HSEM_C1ISR_ISF1_Msk       (0x1UL << HSEM_C1ISR_ISF1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1ISR_ISF1           HSEM_C1ISR_ISF1_Msk                          /*!<semaphore 1 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF2_Pos       (2U)

+#define HSEM_C1ISR_ISF2_Msk       (0x1UL << HSEM_C1ISR_ISF2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1ISR_ISF2           HSEM_C1ISR_ISF2_Msk                          /*!<semaphore 2 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF3_Pos       (3U)

+#define HSEM_C1ISR_ISF3_Msk       (0x1UL << HSEM_C1ISR_ISF3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1ISR_ISF3           HSEM_C1ISR_ISF3_Msk                          /*!<semaphore 3 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF4_Pos       (4U)

+#define HSEM_C1ISR_ISF4_Msk       (0x1UL << HSEM_C1ISR_ISF4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1ISR_ISF4           HSEM_C1ISR_ISF4_Msk                          /*!<semaphore 4 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF5_Pos       (5U)

+#define HSEM_C1ISR_ISF5_Msk       (0x1UL << HSEM_C1ISR_ISF5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1ISR_ISF5           HSEM_C1ISR_ISF5_Msk                          /*!<semaphore 5 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF6_Pos       (6U)

+#define HSEM_C1ISR_ISF6_Msk       (0x1UL << HSEM_C1ISR_ISF6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1ISR_ISF6           HSEM_C1ISR_ISF6_Msk                          /*!<semaphore 6 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF7_Pos       (7U)

+#define HSEM_C1ISR_ISF7_Msk       (0x1UL << HSEM_C1ISR_ISF7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1ISR_ISF7           HSEM_C1ISR_ISF7_Msk                          /*!<semaphore 7 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF8_Pos       (8U)

+#define HSEM_C1ISR_ISF8_Msk       (0x1UL << HSEM_C1ISR_ISF8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1ISR_ISF8           HSEM_C1ISR_ISF8_Msk                          /*!<semaphore 8 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF9_Pos       (9U)

+#define HSEM_C1ISR_ISF9_Msk       (0x1UL << HSEM_C1ISR_ISF9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1ISR_ISF9           HSEM_C1ISR_ISF9_Msk                          /*!<semaphore 9 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF10_Pos      (10U)

+#define HSEM_C1ISR_ISF10_Msk      (0x1UL << HSEM_C1ISR_ISF10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1ISR_ISF10          HSEM_C1ISR_ISF10_Msk                         /*!<semaphore 10 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF11_Pos      (11U)

+#define HSEM_C1ISR_ISF11_Msk      (0x1UL << HSEM_C1ISR_ISF11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1ISR_ISF11          HSEM_C1ISR_ISF11_Msk                         /*!<semaphore 11 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF12_Pos      (12U)

+#define HSEM_C1ISR_ISF12_Msk      (0x1UL << HSEM_C1ISR_ISF12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1ISR_ISF12          HSEM_C1ISR_ISF12_Msk                         /*!<semaphore 12 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF13_Pos      (13U)

+#define HSEM_C1ISR_ISF13_Msk      (0x1UL << HSEM_C1ISR_ISF13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1ISR_ISF13          HSEM_C1ISR_ISF13_Msk                         /*!<semaphore 13 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF14_Pos      (14U)

+#define HSEM_C1ISR_ISF14_Msk      (0x1UL << HSEM_C1ISR_ISF14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1ISR_ISF14          HSEM_C1ISR_ISF14_Msk                         /*!<semaphore 14 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF15_Pos      (15U)

+#define HSEM_C1ISR_ISF15_Msk      (0x1UL << HSEM_C1ISR_ISF15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1ISR_ISF15          HSEM_C1ISR_ISF15_Msk                         /*!<semaphore 15 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF16_Pos      (16U)

+#define HSEM_C1ISR_ISF16_Msk      (0x1UL << HSEM_C1ISR_ISF16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1ISR_ISF16          HSEM_C1ISR_ISF16_Msk                         /*!<semaphore 16 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF17_Pos      (17U)

+#define HSEM_C1ISR_ISF17_Msk      (0x1UL << HSEM_C1ISR_ISF17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1ISR_ISF17          HSEM_C1ISR_ISF17_Msk                         /*!<semaphore 17 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF18_Pos      (18U)

+#define HSEM_C1ISR_ISF18_Msk      (0x1UL << HSEM_C1ISR_ISF18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1ISR_ISF18          HSEM_C1ISR_ISF18_Msk                         /*!<semaphore 18 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF19_Pos      (19U)

+#define HSEM_C1ISR_ISF19_Msk      (0x1UL << HSEM_C1ISR_ISF19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1ISR_ISF19          HSEM_C1ISR_ISF19_Msk                         /*!<semaphore 19 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF20_Pos      (20U)

+#define HSEM_C1ISR_ISF20_Msk      (0x1UL << HSEM_C1ISR_ISF20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1ISR_ISF20          HSEM_C1ISR_ISF20_Msk                         /*!<semaphore 20 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF21_Pos      (21U)

+#define HSEM_C1ISR_ISF21_Msk      (0x1UL << HSEM_C1ISR_ISF21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1ISR_ISF21          HSEM_C1ISR_ISF21_Msk                         /*!<semaphore 21 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF22_Pos      (22U)

+#define HSEM_C1ISR_ISF22_Msk      (0x1UL << HSEM_C1ISR_ISF22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1ISR_ISF22          HSEM_C1ISR_ISF22_Msk                         /*!<semaphore 22 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF23_Pos      (23U)

+#define HSEM_C1ISR_ISF23_Msk      (0x1UL << HSEM_C1ISR_ISF23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1ISR_ISF23          HSEM_C1ISR_ISF23_Msk                         /*!<semaphore 23 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF24_Pos      (24U)

+#define HSEM_C1ISR_ISF24_Msk      (0x1UL << HSEM_C1ISR_ISF24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1ISR_ISF24          HSEM_C1ISR_ISF24_Msk                         /*!<semaphore 24 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF25_Pos      (25U)

+#define HSEM_C1ISR_ISF25_Msk      (0x1UL << HSEM_C1ISR_ISF25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1ISR_ISF25          HSEM_C1ISR_ISF25_Msk                         /*!<semaphore 25 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF26_Pos      (26U)

+#define HSEM_C1ISR_ISF26_Msk      (0x1UL << HSEM_C1ISR_ISF26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1ISR_ISF26          HSEM_C1ISR_ISF26_Msk                         /*!<semaphore 26 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF27_Pos      (27U)

+#define HSEM_C1ISR_ISF27_Msk      (0x1UL << HSEM_C1ISR_ISF27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1ISR_ISF27          HSEM_C1ISR_ISF27_Msk                         /*!<semaphore 27 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF28_Pos      (28U)

+#define HSEM_C1ISR_ISF28_Msk      (0x1UL << HSEM_C1ISR_ISF28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1ISR_ISF28          HSEM_C1ISR_ISF28_Msk                         /*!<semaphore 28 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF29_Pos      (29U)

+#define HSEM_C1ISR_ISF29_Msk      (0x1UL << HSEM_C1ISR_ISF29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1ISR_ISF29          HSEM_C1ISR_ISF29_Msk                         /*!<semaphore 29 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF30_Pos      (30U)

+#define HSEM_C1ISR_ISF30_Msk      (0x1UL << HSEM_C1ISR_ISF30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1ISR_ISF30          HSEM_C1ISR_ISF30_Msk                         /*!<semaphore 30 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF31_Pos      (31U)

+#define HSEM_C1ISR_ISF31_Msk      (0x1UL << HSEM_C1ISR_ISF31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1ISR_ISF31          HSEM_C1ISR_ISF31_Msk                         /*!<semaphore 31 interrupt 0 status bit. */

+

+/********************  Bit definition for HSEM_C1MISR register  *****************/

+#define HSEM_C1MISR_MISF0_Pos     (0U)

+#define HSEM_C1MISR_MISF0_Msk     (0x1UL << HSEM_C1MISR_MISF0_Pos)             /*!< 0x00000001 */

+#define HSEM_C1MISR_MISF0         HSEM_C1MISR_MISF0_Msk                        /*!<semaphore 0 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF1_Pos     (1U)

+#define HSEM_C1MISR_MISF1_Msk     (0x1UL << HSEM_C1MISR_MISF1_Pos)             /*!< 0x00000002 */

+#define HSEM_C1MISR_MISF1         HSEM_C1MISR_MISF1_Msk                        /*!<semaphore 1 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF2_Pos     (2U)

+#define HSEM_C1MISR_MISF2_Msk     (0x1UL << HSEM_C1MISR_MISF2_Pos)             /*!< 0x00000004 */

+#define HSEM_C1MISR_MISF2         HSEM_C1MISR_MISF2_Msk                        /*!<semaphore 2 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF3_Pos     (3U)

+#define HSEM_C1MISR_MISF3_Msk     (0x1UL << HSEM_C1MISR_MISF3_Pos)             /*!< 0x00000008 */

+#define HSEM_C1MISR_MISF3         HSEM_C1MISR_MISF3_Msk                        /*!<semaphore 3 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF4_Pos     (4U)

+#define HSEM_C1MISR_MISF4_Msk     (0x1UL << HSEM_C1MISR_MISF4_Pos)             /*!< 0x00000010 */

+#define HSEM_C1MISR_MISF4         HSEM_C1MISR_MISF4_Msk                        /*!<semaphore 4 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF5_Pos     (5U)

+#define HSEM_C1MISR_MISF5_Msk     (0x1UL << HSEM_C1MISR_MISF5_Pos)             /*!< 0x00000020 */

+#define HSEM_C1MISR_MISF5         HSEM_C1MISR_MISF5_Msk                        /*!<semaphore 5 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF6_Pos     (6U)

+#define HSEM_C1MISR_MISF6_Msk     (0x1UL << HSEM_C1MISR_MISF6_Pos)             /*!< 0x00000040 */

+#define HSEM_C1MISR_MISF6         HSEM_C1MISR_MISF6_Msk                        /*!<semaphore 6 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF7_Pos     (7U)

+#define HSEM_C1MISR_MISF7_Msk     (0x1UL << HSEM_C1MISR_MISF7_Pos)             /*!< 0x00000080 */

+#define HSEM_C1MISR_MISF7         HSEM_C1MISR_MISF7_Msk                        /*!<semaphore 7 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF8_Pos     (8U)

+#define HSEM_C1MISR_MISF8_Msk     (0x1UL << HSEM_C1MISR_MISF8_Pos)             /*!< 0x00000100 */

+#define HSEM_C1MISR_MISF8         HSEM_C1MISR_MISF8_Msk                        /*!<semaphore 8 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF9_Pos     (9U)

+#define HSEM_C1MISR_MISF9_Msk     (0x1UL << HSEM_C1MISR_MISF9_Pos)             /*!< 0x00000200 */

+#define HSEM_C1MISR_MISF9         HSEM_C1MISR_MISF9_Msk                        /*!<semaphore 9 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF10_Pos    (10U)

+#define HSEM_C1MISR_MISF10_Msk    (0x1UL << HSEM_C1MISR_MISF10_Pos)            /*!< 0x00000400 */

+#define HSEM_C1MISR_MISF10        HSEM_C1MISR_MISF10_Msk                       /*!<semaphore 10 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF11_Pos    (11U)

+#define HSEM_C1MISR_MISF11_Msk    (0x1UL << HSEM_C1MISR_MISF11_Pos)            /*!< 0x00000800 */

+#define HSEM_C1MISR_MISF11        HSEM_C1MISR_MISF11_Msk                       /*!<semaphore 11 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF12_Pos    (12U)

+#define HSEM_C1MISR_MISF12_Msk    (0x1UL << HSEM_C1MISR_MISF12_Pos)            /*!< 0x00001000 */

+#define HSEM_C1MISR_MISF12        HSEM_C1MISR_MISF12_Msk                       /*!<semaphore 12 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF13_Pos    (13U)

+#define HSEM_C1MISR_MISF13_Msk    (0x1UL << HSEM_C1MISR_MISF13_Pos)            /*!< 0x00002000 */

+#define HSEM_C1MISR_MISF13        HSEM_C1MISR_MISF13_Msk                       /*!<semaphore 13 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF14_Pos    (14U)

+#define HSEM_C1MISR_MISF14_Msk    (0x1UL << HSEM_C1MISR_MISF14_Pos)            /*!< 0x00004000 */

+#define HSEM_C1MISR_MISF14        HSEM_C1MISR_MISF14_Msk                       /*!<semaphore 14 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF15_Pos    (15U)

+#define HSEM_C1MISR_MISF15_Msk    (0x1UL << HSEM_C1MISR_MISF15_Pos)            /*!< 0x00008000 */

+#define HSEM_C1MISR_MISF15        HSEM_C1MISR_MISF15_Msk                       /*!<semaphore 15 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF16_Pos    (16U)

+#define HSEM_C1MISR_MISF16_Msk    (0x1UL << HSEM_C1MISR_MISF16_Pos)            /*!< 0x00010000 */

+#define HSEM_C1MISR_MISF16        HSEM_C1MISR_MISF16_Msk                       /*!<semaphore 16 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF17_Pos    (17U)

+#define HSEM_C1MISR_MISF17_Msk    (0x1UL << HSEM_C1MISR_MISF17_Pos)            /*!< 0x00020000 */

+#define HSEM_C1MISR_MISF17        HSEM_C1MISR_MISF17_Msk                       /*!<semaphore 17 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF18_Pos    (18U)

+#define HSEM_C1MISR_MISF18_Msk    (0x1UL << HSEM_C1MISR_MISF18_Pos)            /*!< 0x00040000 */

+#define HSEM_C1MISR_MISF18        HSEM_C1MISR_MISF18_Msk                       /*!<semaphore 18 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF19_Pos    (19U)

+#define HSEM_C1MISR_MISF19_Msk    (0x1UL << HSEM_C1MISR_MISF19_Pos)            /*!< 0x00080000 */

+#define HSEM_C1MISR_MISF19        HSEM_C1MISR_MISF19_Msk                       /*!<semaphore 19 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF20_Pos    (20U)

+#define HSEM_C1MISR_MISF20_Msk    (0x1UL << HSEM_C1MISR_MISF20_Pos)            /*!< 0x00100000 */

+#define HSEM_C1MISR_MISF20        HSEM_C1MISR_MISF20_Msk                       /*!<semaphore 20 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF21_Pos    (21U)

+#define HSEM_C1MISR_MISF21_Msk    (0x1UL << HSEM_C1MISR_MISF21_Pos)            /*!< 0x00200000 */

+#define HSEM_C1MISR_MISF21        HSEM_C1MISR_MISF21_Msk                       /*!<semaphore 21 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF22_Pos    (22U)

+#define HSEM_C1MISR_MISF22_Msk    (0x1UL << HSEM_C1MISR_MISF22_Pos)            /*!< 0x00400000 */

+#define HSEM_C1MISR_MISF22        HSEM_C1MISR_MISF22_Msk                       /*!<semaphore 22 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF23_Pos    (23U)

+#define HSEM_C1MISR_MISF23_Msk    (0x1UL << HSEM_C1MISR_MISF23_Pos)            /*!< 0x00800000 */

+#define HSEM_C1MISR_MISF23        HSEM_C1MISR_MISF23_Msk                       /*!<semaphore 23 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF24_Pos    (24U)

+#define HSEM_C1MISR_MISF24_Msk    (0x1UL << HSEM_C1MISR_MISF24_Pos)            /*!< 0x01000000 */

+#define HSEM_C1MISR_MISF24        HSEM_C1MISR_MISF24_Msk                       /*!<semaphore 24 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF25_Pos    (25U)

+#define HSEM_C1MISR_MISF25_Msk    (0x1UL << HSEM_C1MISR_MISF25_Pos)            /*!< 0x02000000 */

+#define HSEM_C1MISR_MISF25        HSEM_C1MISR_MISF25_Msk                       /*!<semaphore 25 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF26_Pos    (26U)

+#define HSEM_C1MISR_MISF26_Msk    (0x1UL << HSEM_C1MISR_MISF26_Pos)            /*!< 0x04000000 */

+#define HSEM_C1MISR_MISF26        HSEM_C1MISR_MISF26_Msk                       /*!<semaphore 26 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF27_Pos    (27U)

+#define HSEM_C1MISR_MISF27_Msk    (0x1UL << HSEM_C1MISR_MISF27_Pos)            /*!< 0x08000000 */

+#define HSEM_C1MISR_MISF27        HSEM_C1MISR_MISF27_Msk                       /*!<semaphore 27 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF28_Pos    (28U)

+#define HSEM_C1MISR_MISF28_Msk    (0x1UL << HSEM_C1MISR_MISF28_Pos)            /*!< 0x10000000 */

+#define HSEM_C1MISR_MISF28        HSEM_C1MISR_MISF28_Msk                       /*!<semaphore 28 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF29_Pos    (29U)

+#define HSEM_C1MISR_MISF29_Msk    (0x1UL << HSEM_C1MISR_MISF29_Pos)            /*!< 0x20000000 */

+#define HSEM_C1MISR_MISF29        HSEM_C1MISR_MISF29_Msk                       /*!<semaphore 29 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF30_Pos    (30U)

+#define HSEM_C1MISR_MISF30_Msk    (0x1UL << HSEM_C1MISR_MISF30_Pos)            /*!< 0x40000000 */

+#define HSEM_C1MISR_MISF30        HSEM_C1MISR_MISF30_Msk                       /*!<semaphore 30 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF31_Pos    (31U)

+#define HSEM_C1MISR_MISF31_Msk    (0x1UL << HSEM_C1MISR_MISF31_Pos)            /*!< 0x80000000 */

+#define HSEM_C1MISR_MISF31        HSEM_C1MISR_MISF31_Msk                       /*!<semaphore 31 interrupt 0 masked status bit. */

+

+/********************  Bit definition for HSEM_CR register  *****************/

+#define HSEM_CR_COREID_Pos        (8U)

+#define HSEM_CR_COREID_Msk        (0xFFUL << HSEM_CR_COREID_Pos)               /*!< 0x0000FF00 */

+#define HSEM_CR_COREID            HSEM_CR_COREID_Msk                           /*!<CoreID of semaphores to be cleared. */

+#define HSEM_CR_KEY_Pos           (16U)

+#define HSEM_CR_KEY_Msk           (0xFFFFUL << HSEM_CR_KEY_Pos)                /*!< 0xFFFF0000 */

+#define HSEM_CR_KEY               HSEM_CR_KEY_Msk                              /*!<semaphores clear key. */

+

+/********************  Bit definition for HSEM_KEYR register  *****************/

+#define HSEM_KEYR_KEY_Pos         (16U)

+#define HSEM_KEYR_KEY_Msk         (0xFFFFUL << HSEM_KEYR_KEY_Pos)              /*!< 0xFFFF0000 */

+#define HSEM_KEYR_KEY             HSEM_KEYR_KEY_Msk                            /*!<semaphores clear key. */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      Inter-integrated Circuit Interface (I2C)              */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for I2C_CR1 register  *******************/

+#define I2C_CR1_PE_Pos               (0U)

+#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */

+#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */

+#define I2C_CR1_TXIE_Pos             (1U)

+#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */

+#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */

+#define I2C_CR1_RXIE_Pos             (2U)

+#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */

+#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */

+#define I2C_CR1_ADDRIE_Pos           (3U)

+#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */

+#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */

+#define I2C_CR1_NACKIE_Pos           (4U)

+#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */

+#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */

+#define I2C_CR1_STOPIE_Pos           (5U)

+#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */

+#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */

+#define I2C_CR1_TCIE_Pos             (6U)

+#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */

+#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */

+#define I2C_CR1_ERRIE_Pos            (7U)

+#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */

+#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */

+#define I2C_CR1_DNF_Pos              (8U)

+#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */

+#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */

+#define I2C_CR1_ANFOFF_Pos           (12U)

+#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */

+#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */

+#define I2C_CR1_TXDMAEN_Pos          (14U)

+#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */

+#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */

+#define I2C_CR1_RXDMAEN_Pos          (15U)

+#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */

+#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */

+#define I2C_CR1_SBC_Pos              (16U)

+#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */

+#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */

+#define I2C_CR1_NOSTRETCH_Pos        (17U)

+#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */

+#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */

+#define I2C_CR1_WUPEN_Pos            (18U)

+#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */

+#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */

+#define I2C_CR1_GCEN_Pos             (19U)

+#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */

+#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */

+#define I2C_CR1_SMBHEN_Pos           (20U)

+#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */

+#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */

+#define I2C_CR1_SMBDEN_Pos           (21U)

+#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */

+#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */

+#define I2C_CR1_ALERTEN_Pos          (22U)

+#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */

+#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */

+#define I2C_CR1_PECEN_Pos            (23U)

+#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */

+#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */

+

+/******************  Bit definition for I2C_CR2 register  ********************/

+#define I2C_CR2_SADD_Pos             (0U)

+#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */

+#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */

+#define I2C_CR2_RD_WRN_Pos           (10U)

+#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */

+#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */

+#define I2C_CR2_ADD10_Pos            (11U)

+#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */

+#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */

+#define I2C_CR2_HEAD10R_Pos          (12U)

+#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */

+#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */

+#define I2C_CR2_START_Pos            (13U)

+#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */

+#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */

+#define I2C_CR2_STOP_Pos             (14U)

+#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */

+#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */

+#define I2C_CR2_NACK_Pos             (15U)

+#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */

+#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */

+#define I2C_CR2_NBYTES_Pos           (16U)

+#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */

+#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */

+#define I2C_CR2_RELOAD_Pos           (24U)

+#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */

+#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */

+#define I2C_CR2_AUTOEND_Pos          (25U)

+#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */

+#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */

+#define I2C_CR2_PECBYTE_Pos          (26U)

+#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */

+#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */

+

+/*******************  Bit definition for I2C_OAR1 register  ******************/

+#define I2C_OAR1_OA1_Pos             (0U)

+#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */

+#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */

+#define I2C_OAR1_OA1MODE_Pos         (10U)

+#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */

+#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */

+#define I2C_OAR1_OA1EN_Pos           (15U)

+#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */

+#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */

+

+/*******************  Bit definition for I2C_OAR2 register  ******************/

+#define I2C_OAR2_OA2_Pos             (1U)

+#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */

+#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */

+#define I2C_OAR2_OA2MSK_Pos          (8U)

+#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */

+#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */

+#define I2C_OAR2_OA2NOMASK           0x00000000UL                              /*!< No mask */

+#define I2C_OAR2_OA2MASK01_Pos       (8U)

+#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */

+#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared */

+#define I2C_OAR2_OA2MASK02_Pos       (9U)

+#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */

+#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */

+#define I2C_OAR2_OA2MASK03_Pos       (8U)

+#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */

+#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */

+#define I2C_OAR2_OA2MASK04_Pos       (10U)

+#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */

+#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */

+#define I2C_OAR2_OA2MASK05_Pos       (8U)

+#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */

+#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */

+#define I2C_OAR2_OA2MASK06_Pos       (9U)

+#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */

+#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared */

+#define I2C_OAR2_OA2MASK07_Pos       (8U)

+#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */

+#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done */

+#define I2C_OAR2_OA2EN_Pos           (15U)

+#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */

+#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */

+

+/*******************  Bit definition for I2C_TIMINGR register *******************/

+#define I2C_TIMINGR_SCLL_Pos         (0U)

+#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */

+#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */

+#define I2C_TIMINGR_SCLH_Pos         (8U)

+#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */

+#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */

+#define I2C_TIMINGR_SDADEL_Pos       (16U)

+#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */

+#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */

+#define I2C_TIMINGR_SCLDEL_Pos       (20U)

+#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */

+#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */

+#define I2C_TIMINGR_PRESC_Pos        (28U)

+#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */

+#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */

+

+/******************* Bit definition for I2C_TIMEOUTR register *******************/

+#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)

+#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */

+#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */

+#define I2C_TIMEOUTR_TIDLE_Pos       (12U)

+#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */

+#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */

+#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)

+#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */

+#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */

+#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)

+#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */

+#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/

+#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)

+#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */

+#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */

+

+/******************  Bit definition for I2C_ISR register  *********************/

+#define I2C_ISR_TXE_Pos              (0U)

+#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */

+#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */

+#define I2C_ISR_TXIS_Pos             (1U)

+#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */

+#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */

+#define I2C_ISR_RXNE_Pos             (2U)

+#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */

+#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */

+#define I2C_ISR_ADDR_Pos             (3U)

+#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */

+#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/

+#define I2C_ISR_NACKF_Pos            (4U)

+#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */

+#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */

+#define I2C_ISR_STOPF_Pos            (5U)

+#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */

+#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */

+#define I2C_ISR_TC_Pos               (6U)

+#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */

+#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */

+#define I2C_ISR_TCR_Pos              (7U)

+#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */

+#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */

+#define I2C_ISR_BERR_Pos             (8U)

+#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */

+#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */

+#define I2C_ISR_ARLO_Pos             (9U)

+#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */

+#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */

+#define I2C_ISR_OVR_Pos              (10U)

+#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */

+#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */

+#define I2C_ISR_PECERR_Pos           (11U)

+#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */

+#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */

+#define I2C_ISR_TIMEOUT_Pos          (12U)

+#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */

+#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */

+#define I2C_ISR_ALERT_Pos            (13U)

+#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */

+#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */

+#define I2C_ISR_BUSY_Pos             (15U)

+#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */

+#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */

+#define I2C_ISR_DIR_Pos              (16U)

+#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */

+#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */

+#define I2C_ISR_ADDCODE_Pos          (17U)

+#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */

+#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */

+

+/******************  Bit definition for I2C_ICR register  *********************/

+#define I2C_ICR_ADDRCF_Pos           (3U)

+#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */

+#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */

+#define I2C_ICR_NACKCF_Pos           (4U)

+#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */

+#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */

+#define I2C_ICR_STOPCF_Pos           (5U)

+#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */

+#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */

+#define I2C_ICR_BERRCF_Pos           (8U)

+#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */

+#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */

+#define I2C_ICR_ARLOCF_Pos           (9U)

+#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */

+#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */

+#define I2C_ICR_OVRCF_Pos            (10U)

+#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */

+#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */

+#define I2C_ICR_PECCF_Pos            (11U)

+#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */

+#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */

+#define I2C_ICR_TIMOUTCF_Pos         (12U)

+#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */

+#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */

+#define I2C_ICR_ALERTCF_Pos          (13U)

+#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */

+#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */

+

+/******************  Bit definition for I2C_PECR register  *********************/

+#define I2C_PECR_PEC_Pos             (0U)

+#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */

+#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */

+

+/******************  Bit definition for I2C_RXDR register  *********************/

+#define I2C_RXDR_RXDATA_Pos          (0U)

+#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */

+#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */

+

+/******************  Bit definition for I2C_TXDR register  *********************/

+#define I2C_TXDR_TXDATA_Pos          (0U)

+#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */

+#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           Independent WATCHDOG                             */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for IWDG_KR register  ********************/

+#define IWDG_KR_KEY_Pos      (0U)

+#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */

+#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */

+

+/*******************  Bit definition for IWDG_PR register  ********************/

+#define IWDG_PR_PR_Pos       (0U)

+#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */

+#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */

+#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */

+#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */

+#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */

+

+/*******************  Bit definition for IWDG_RLR register  *******************/

+#define IWDG_RLR_RL_Pos      (0U)

+#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */

+#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */

+

+/*******************  Bit definition for IWDG_SR register  ********************/

+#define IWDG_SR_PVU_Pos      (0U)

+#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */

+#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */

+#define IWDG_SR_RVU_Pos      (1U)

+#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */

+#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */

+#define IWDG_SR_WVU_Pos      (2U)

+#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */

+#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */

+

+/*******************  Bit definition for IWDG_KR register  ********************/

+#define IWDG_WINR_WIN_Pos    (0U)

+#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */

+#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */

+

+/******************************************************************************/

+/*                                                                            */

+/*                        JPEG Encoder/Decoder                                */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for CONFR0 register  ********************/

+#define JPEG_CONFR0_START_Pos           (0U)

+#define JPEG_CONFR0_START_Msk           (0x1UL << JPEG_CONFR0_START_Pos)       /*!< 0x00000001 */

+#define JPEG_CONFR0_START               JPEG_CONFR0_START_Msk                  /*!<Start/Stop bit */

+

+/********************  Bit definition for CONFR1 register  ********************/

+#define JPEG_CONFR1_NF_Pos              (0U)

+#define JPEG_CONFR1_NF_Msk              (0x3UL << JPEG_CONFR1_NF_Pos)          /*!< 0x00000003 */

+#define JPEG_CONFR1_NF                  JPEG_CONFR1_NF_Msk                     /*!<Number of color components */

+#define JPEG_CONFR1_NF_0                (0x1UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000001 */

+#define JPEG_CONFR1_NF_1                (0x2UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000002 */

+#define JPEG_CONFR1_DE_Pos              (3U)

+#define JPEG_CONFR1_DE_Msk              (0x1UL << JPEG_CONFR1_DE_Pos)          /*!< 0x00000008 */

+#define JPEG_CONFR1_DE                  JPEG_CONFR1_DE_Msk                     /*!<Decoding Enable */

+#define JPEG_CONFR1_COLORSPACE_Pos      (4U)

+#define JPEG_CONFR1_COLORSPACE_Msk      (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)  /*!< 0x00000030 */

+#define JPEG_CONFR1_COLORSPACE          JPEG_CONFR1_COLORSPACE_Msk             /*!<Color Space */

+#define JPEG_CONFR1_COLORSPACE_0        (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000010 */

+#define JPEG_CONFR1_COLORSPACE_1        (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000020 */

+#define JPEG_CONFR1_NS_Pos              (6U)

+#define JPEG_CONFR1_NS_Msk              (0x3UL << JPEG_CONFR1_NS_Pos)          /*!< 0x000000C0 */

+#define JPEG_CONFR1_NS                  JPEG_CONFR1_NS_Msk                     /*!<Number of components for Scan */

+#define JPEG_CONFR1_NS_0                (0x1UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR1_NS_1                (0x2UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR1_HDR_Pos             (8U)

+#define JPEG_CONFR1_HDR_Msk             (0x1UL << JPEG_CONFR1_HDR_Pos)         /*!< 0x00000100 */

+#define JPEG_CONFR1_HDR                 JPEG_CONFR1_HDR_Msk                    /*!<Header Processing On/Off */

+#define JPEG_CONFR1_YSIZE_Pos           (16U)

+#define JPEG_CONFR1_YSIZE_Msk           (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)    /*!< 0xFFFF0000 */

+#define JPEG_CONFR1_YSIZE               JPEG_CONFR1_YSIZE_Msk                  /*!<Number of lines in source image */

+

+/********************  Bit definition for CONFR2 register  ********************/

+#define JPEG_CONFR2_NMCU_Pos            (0U)

+#define JPEG_CONFR2_NMCU_Msk            (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)  /*!< 0x03FFFFFF */

+#define JPEG_CONFR2_NMCU                JPEG_CONFR2_NMCU_Msk                   /*!<Number of MCU units minus 1 to encode */

+

+/********************  Bit definition for CONFR3 register  ********************/

+#define JPEG_CONFR3_XSIZE_Pos           (16U)

+#define JPEG_CONFR3_XSIZE_Msk           (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)    /*!< 0xFFFF0000 */

+#define JPEG_CONFR3_XSIZE               JPEG_CONFR3_XSIZE_Msk                  /*!<Number of pixels per line */

+

+/********************  Bit definition for CONFR4 register  ********************/

+#define JPEG_CONFR4_HD_Pos              (0U)

+#define JPEG_CONFR4_HD_Msk              (0x1UL << JPEG_CONFR4_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR4_HD                  JPEG_CONFR4_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR4_HA_Pos              (1U)

+#define JPEG_CONFR4_HA_Msk              (0x1UL << JPEG_CONFR4_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR4_HA                  JPEG_CONFR4_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR4_QT_Pos              (2U)

+#define JPEG_CONFR4_QT_Msk              (0x3UL << JPEG_CONFR4_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR4_QT                  JPEG_CONFR4_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR4_QT_0                (0x1UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR4_QT_1                (0x2UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR4_NB_Pos              (4U)

+#define JPEG_CONFR4_NB_Msk              (0xFUL << JPEG_CONFR4_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR4_NB                  JPEG_CONFR4_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR4_NB_0                (0x1UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR4_NB_1                (0x2UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR4_NB_2                (0x4UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR4_NB_3                (0x8UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR4_VSF_Pos             (8U)

+#define JPEG_CONFR4_VSF_Msk             (0xFUL << JPEG_CONFR4_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR4_VSF                 JPEG_CONFR4_VSF_Msk                    /*!<Vertical sampling factor for component 1 */

+#define JPEG_CONFR4_VSF_0               (0x1UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR4_VSF_1               (0x2UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR4_VSF_2               (0x4UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR4_VSF_3               (0x8UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR4_HSF_Pos             (12U)

+#define JPEG_CONFR4_HSF_Msk             (0xFUL << JPEG_CONFR4_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR4_HSF                 JPEG_CONFR4_HSF_Msk                    /*!<Horizontal sampling factor for component 1 */

+#define JPEG_CONFR4_HSF_0               (0x1UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR4_HSF_1               (0x2UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR4_HSF_2               (0x4UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR4_HSF_3               (0x8UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR5 register  ********************/

+#define JPEG_CONFR5_HD_Pos              (0U)

+#define JPEG_CONFR5_HD_Msk              (0x1UL << JPEG_CONFR5_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR5_HD                  JPEG_CONFR5_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR5_HA_Pos              (1U)

+#define JPEG_CONFR5_HA_Msk              (0x1UL << JPEG_CONFR5_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR5_HA                  JPEG_CONFR5_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR5_QT_Pos              (2U)

+#define JPEG_CONFR5_QT_Msk              (0x3UL << JPEG_CONFR5_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR5_QT                  JPEG_CONFR5_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR5_QT_0                (0x1UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR5_QT_1                (0x2UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR5_NB_Pos              (4U)

+#define JPEG_CONFR5_NB_Msk              (0xFUL << JPEG_CONFR5_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR5_NB                  JPEG_CONFR5_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR5_NB_0                (0x1UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR5_NB_1                (0x2UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR5_NB_2                (0x4UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR5_NB_3                (0x8UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR5_VSF_Pos             (8U)

+#define JPEG_CONFR5_VSF_Msk             (0xFUL << JPEG_CONFR5_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR5_VSF                 JPEG_CONFR5_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR5_VSF_0               (0x1UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR5_VSF_1               (0x2UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR5_VSF_2               (0x4UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR5_VSF_3               (0x8UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR5_HSF_Pos             (12U)

+#define JPEG_CONFR5_HSF_Msk             (0xFUL << JPEG_CONFR5_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR5_HSF                 JPEG_CONFR5_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR5_HSF_0               (0x1UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR5_HSF_1               (0x2UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR5_HSF_2               (0x4UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR5_HSF_3               (0x8UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR6 register  ********************/

+#define JPEG_CONFR6_HD_Pos              (0U)

+#define JPEG_CONFR6_HD_Msk              (0x1UL << JPEG_CONFR6_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR6_HD                  JPEG_CONFR6_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR6_HA_Pos              (1U)

+#define JPEG_CONFR6_HA_Msk              (0x1UL << JPEG_CONFR6_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR6_HA                  JPEG_CONFR6_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR6_QT_Pos              (2U)

+#define JPEG_CONFR6_QT_Msk              (0x3UL << JPEG_CONFR6_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR6_QT                  JPEG_CONFR6_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR6_QT_0                (0x1UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR6_QT_1                (0x2UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR6_NB_Pos              (4U)

+#define JPEG_CONFR6_NB_Msk              (0xFUL << JPEG_CONFR6_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR6_NB                  JPEG_CONFR6_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR6_NB_0                (0x1UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR6_NB_1                (0x2UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR6_NB_2                (0x4UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR6_NB_3                (0x8UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR6_VSF_Pos             (8U)

+#define JPEG_CONFR6_VSF_Msk             (0xFUL << JPEG_CONFR6_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR6_VSF                 JPEG_CONFR6_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR6_VSF_0               (0x1UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR6_VSF_1               (0x2UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR6_VSF_2               (0x4UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR6_VSF_3               (0x8UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR6_HSF_Pos             (12U)

+#define JPEG_CONFR6_HSF_Msk             (0xFUL << JPEG_CONFR6_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR6_HSF                 JPEG_CONFR6_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR6_HSF_0               (0x1UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR6_HSF_1               (0x2UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR6_HSF_2               (0x4UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR6_HSF_3               (0x8UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR7 register  ********************/

+#define JPEG_CONFR7_HD_Pos              (0U)

+#define JPEG_CONFR7_HD_Msk              (0x1UL << JPEG_CONFR7_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR7_HD                  JPEG_CONFR7_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR7_HA_Pos              (1U)

+#define JPEG_CONFR7_HA_Msk              (0x1UL << JPEG_CONFR7_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR7_HA                  JPEG_CONFR7_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR7_QT_Pos              (2U)

+#define JPEG_CONFR7_QT_Msk              (0x3UL << JPEG_CONFR7_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR7_QT                  JPEG_CONFR7_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR7_QT_0                (0x1UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR7_QT_1                (0x2UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR7_NB_Pos              (4U)

+#define JPEG_CONFR7_NB_Msk              (0xFUL << JPEG_CONFR7_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR7_NB                  JPEG_CONFR7_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR7_NB_0                (0x1UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR7_NB_1                (0x2UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR7_NB_2                (0x4UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR7_NB_3                (0x8UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR7_VSF_Pos             (8U)

+#define JPEG_CONFR7_VSF_Msk             (0xFUL << JPEG_CONFR7_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR7_VSF                 JPEG_CONFR7_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR7_VSF_0               (0x1UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR7_VSF_1               (0x2UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR7_VSF_2               (0x4UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR7_VSF_3               (0x8UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR7_HSF_Pos             (12U)

+#define JPEG_CONFR7_HSF_Msk             (0xFUL << JPEG_CONFR7_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR7_HSF                 JPEG_CONFR7_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR7_HSF_0               (0x1UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR7_HSF_1               (0x2UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR7_HSF_2               (0x4UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR7_HSF_3               (0x8UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CR register  ********************/

+#define JPEG_CR_JCEN_Pos                (0U)

+#define JPEG_CR_JCEN_Msk                (0x1UL << JPEG_CR_JCEN_Pos)            /*!< 0x00000001 */

+#define JPEG_CR_JCEN                    JPEG_CR_JCEN_Msk                       /*!<Enable the JPEG Codec Core */

+#define JPEG_CR_IFTIE_Pos               (1U)

+#define JPEG_CR_IFTIE_Msk               (0x1UL << JPEG_CR_IFTIE_Pos)           /*!< 0x00000002 */

+#define JPEG_CR_IFTIE                   JPEG_CR_IFTIE_Msk                      /*!<Input FIFO Threshold Interrupt Enable */

+#define JPEG_CR_IFNFIE_Pos              (2U)

+#define JPEG_CR_IFNFIE_Msk              (0x1UL << JPEG_CR_IFNFIE_Pos)          /*!< 0x00000004 */

+#define JPEG_CR_IFNFIE                  JPEG_CR_IFNFIE_Msk                     /*!<Input FIFO Not Full Interrupt Enable */

+#define JPEG_CR_OFTIE_Pos               (3U)

+#define JPEG_CR_OFTIE_Msk               (0x1UL << JPEG_CR_OFTIE_Pos)           /*!< 0x00000008 */

+#define JPEG_CR_OFTIE                   JPEG_CR_OFTIE_Msk                      /*!<Output FIFO Threshold Interrupt Enable */

+#define JPEG_CR_OFNEIE_Pos              (4U)

+#define JPEG_CR_OFNEIE_Msk              (0x1UL << JPEG_CR_OFNEIE_Pos)          /*!< 0x00000010 */

+#define JPEG_CR_OFNEIE                  JPEG_CR_OFNEIE_Msk                     /*!<Output FIFO Not Empty Interrupt Enable */

+#define JPEG_CR_EOCIE_Pos               (5U)

+#define JPEG_CR_EOCIE_Msk               (0x1UL << JPEG_CR_EOCIE_Pos)           /*!< 0x00000020 */

+#define JPEG_CR_EOCIE                   JPEG_CR_EOCIE_Msk                      /*!<End of Conversion Interrupt Enable */

+#define JPEG_CR_HPDIE_Pos               (6U)

+#define JPEG_CR_HPDIE_Msk               (0x1UL << JPEG_CR_HPDIE_Pos)           /*!< 0x00000040 */

+#define JPEG_CR_HPDIE                   JPEG_CR_HPDIE_Msk                      /*!<Header Parsing Done Interrupt Enable */

+#define JPEG_CR_IFF_Pos                 (13U)

+#define JPEG_CR_IFF_Msk                 (0x1UL << JPEG_CR_IFF_Pos)             /*!< 0x00002000 */

+#define JPEG_CR_IFF                     JPEG_CR_IFF_Msk                        /*!<Flush the input FIFO */

+#define JPEG_CR_OFF_Pos                 (14U)

+#define JPEG_CR_OFF_Msk                 (0x1UL << JPEG_CR_OFF_Pos)             /*!< 0x00004000 */

+#define JPEG_CR_OFF                     JPEG_CR_OFF_Msk                        /*!<Flush the output FIFO */

+

+/********************  Bit definition for SR register  ********************/

+#define JPEG_SR_IFTF_Pos                (1U)

+#define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */

+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is bellow its threshold flag */

+#define JPEG_SR_IFNFF_Pos               (2U)

+#define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */

+#define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */

+#define JPEG_SR_OFTF_Pos                (3U)

+#define JPEG_SR_OFTF_Msk                (0x1UL << JPEG_SR_OFTF_Pos)            /*!< 0x00000008 */

+#define JPEG_SR_OFTF                    JPEG_SR_OFTF_Msk                       /*!<Output FIFO is not empty and has reach its threshold */

+#define JPEG_SR_OFNEF_Pos               (4U)

+#define JPEG_SR_OFNEF_Msk               (0x1UL << JPEG_SR_OFNEF_Pos)           /*!< 0x00000010 */

+#define JPEG_SR_OFNEF                   JPEG_SR_OFNEF_Msk                      /*!<Output FIFO is not empty, a data is available */

+#define JPEG_SR_EOCF_Pos                (5U)

+#define JPEG_SR_EOCF_Msk                (0x1UL << JPEG_SR_EOCF_Pos)            /*!< 0x00000020 */

+#define JPEG_SR_EOCF                    JPEG_SR_EOCF_Msk                       /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */

+#define JPEG_SR_HPDF_Pos                (6U)

+#define JPEG_SR_HPDF_Msk                (0x1UL << JPEG_SR_HPDF_Pos)            /*!< 0x00000040 */

+#define JPEG_SR_HPDF                    JPEG_SR_HPDF_Msk                       /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */

+#define JPEG_SR_COF_Pos                 (7U)

+#define JPEG_SR_COF_Msk                 (0x1UL << JPEG_SR_COF_Pos)             /*!< 0x00000080 */

+#define JPEG_SR_COF                     JPEG_SR_COF_Msk                        /*!<JPEG Codec operation on going flag */

+

+/********************  Bit definition for CFR register  ********************/

+#define JPEG_CFR_CEOCF_Pos              (4U)

+#define JPEG_CFR_CEOCF_Msk              (0x1UL << JPEG_CFR_CEOCF_Pos)          /*!< 0x00000010 */

+#define JPEG_CFR_CEOCF                  JPEG_CFR_CEOCF_Msk                     /*!<Clear End of Conversion Flag */

+#define JPEG_CFR_CHPDF_Pos              (5U)

+#define JPEG_CFR_CHPDF_Msk              (0x1UL << JPEG_CFR_CHPDF_Pos)          /*!< 0x00000020 */

+#define JPEG_CFR_CHPDF                  JPEG_CFR_CHPDF_Msk                     /*!<Clear Header Parsing Done Flag */

+

+/********************  Bit definition for DIR register  ********************/

+#define JPEG_DIR_DATAIN_Pos             (0U)

+#define JPEG_DIR_DATAIN_Msk             (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)  /*!< 0xFFFFFFFF */

+#define JPEG_DIR_DATAIN                 JPEG_DIR_DATAIN_Msk                    /*!<Data Input FIFO */

+

+/********************  Bit definition for DOR register  ********************/

+#define JPEG_DOR_DATAOUT_Pos            (0U)

+#define JPEG_DOR_DATAOUT_Msk            (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */

+#define JPEG_DOR_DATAOUT                JPEG_DOR_DATAOUT_Msk                   /*!<Data Output FIFO */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      LCD-TFT Display Controller (LTDC)                     */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for LTDC_SSCR register  *****************/

+

+#define LTDC_SSCR_VSH_Pos            (0U)

+#define LTDC_SSCR_VSH_Msk            (0x7FFUL << LTDC_SSCR_VSH_Pos)            /*!< 0x000007FF */

+#define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height  */

+#define LTDC_SSCR_HSW_Pos            (16U)

+#define LTDC_SSCR_HSW_Msk            (0xFFFUL << LTDC_SSCR_HSW_Pos)            /*!< 0x0FFF0000 */

+#define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */

+

+/********************  Bit definition for LTDC_BPCR register  *****************/

+

+#define LTDC_BPCR_AVBP_Pos           (0U)

+#define LTDC_BPCR_AVBP_Msk           (0x7FFUL << LTDC_BPCR_AVBP_Pos)           /*!< 0x000007FF */

+#define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch   */

+#define LTDC_BPCR_AHBP_Pos           (16U)

+#define LTDC_BPCR_AHBP_Msk           (0xFFFUL << LTDC_BPCR_AHBP_Pos)           /*!< 0x0FFF0000 */

+#define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */

+

+/********************  Bit definition for LTDC_AWCR register  *****************/

+

+#define LTDC_AWCR_AAH_Pos            (0U)

+#define LTDC_AWCR_AAH_Msk            (0x7FFUL << LTDC_AWCR_AAH_Pos)            /*!< 0x000007FF */

+#define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active heigh */

+#define LTDC_AWCR_AAW_Pos            (16U)

+#define LTDC_AWCR_AAW_Msk            (0xFFFUL << LTDC_AWCR_AAW_Pos)            /*!< 0x0FFF0000 */

+#define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */

+

+/********************  Bit definition for LTDC_TWCR register  *****************/

+

+#define LTDC_TWCR_TOTALH_Pos         (0U)

+#define LTDC_TWCR_TOTALH_Msk         (0x7FFUL << LTDC_TWCR_TOTALH_Pos)         /*!< 0x000007FF */

+#define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total Heigh */

+#define LTDC_TWCR_TOTALW_Pos         (16U)

+#define LTDC_TWCR_TOTALW_Msk         (0xFFFUL << LTDC_TWCR_TOTALW_Pos)         /*!< 0x0FFF0000 */

+#define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */

+

+/********************  Bit definition for LTDC_GCR register  ******************/

+

+#define LTDC_GCR_LTDCEN_Pos          (0U)

+#define LTDC_GCR_LTDCEN_Msk          (0x1UL << LTDC_GCR_LTDCEN_Pos)            /*!< 0x00000001 */

+#define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit       */

+#define LTDC_GCR_DBW_Pos             (4U)

+#define LTDC_GCR_DBW_Msk             (0x7UL << LTDC_GCR_DBW_Pos)               /*!< 0x00000070 */

+#define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width                   */

+#define LTDC_GCR_DGW_Pos             (8U)

+#define LTDC_GCR_DGW_Msk             (0x7UL << LTDC_GCR_DGW_Pos)               /*!< 0x00000700 */

+#define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width                  */

+#define LTDC_GCR_DRW_Pos             (12U)

+#define LTDC_GCR_DRW_Msk             (0x7UL << LTDC_GCR_DRW_Pos)               /*!< 0x00007000 */

+#define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width                    */

+#define LTDC_GCR_DEN_Pos             (16U)

+#define LTDC_GCR_DEN_Msk             (0x1UL << LTDC_GCR_DEN_Pos)               /*!< 0x00010000 */

+#define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable                       */

+#define LTDC_GCR_PCPOL_Pos           (28U)

+#define LTDC_GCR_PCPOL_Msk           (0x1UL << LTDC_GCR_PCPOL_Pos)             /*!< 0x10000000 */

+#define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity                */

+#define LTDC_GCR_DEPOL_Pos           (29U)

+#define LTDC_GCR_DEPOL_Msk           (0x1UL << LTDC_GCR_DEPOL_Pos)             /*!< 0x20000000 */

+#define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity                */

+#define LTDC_GCR_VSPOL_Pos           (30U)

+#define LTDC_GCR_VSPOL_Msk           (0x1UL << LTDC_GCR_VSPOL_Pos)             /*!< 0x40000000 */

+#define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity   */

+#define LTDC_GCR_HSPOL_Pos           (31U)

+#define LTDC_GCR_HSPOL_Msk           (0x1UL << LTDC_GCR_HSPOL_Pos)             /*!< 0x80000000 */

+#define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */

+

+

+/********************  Bit definition for LTDC_SRCR register  *****************/

+

+#define LTDC_SRCR_IMR_Pos            (0U)

+#define LTDC_SRCR_IMR_Msk            (0x1UL << LTDC_SRCR_IMR_Pos)              /*!< 0x00000001 */

+#define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload         */

+#define LTDC_SRCR_VBR_Pos            (1U)

+#define LTDC_SRCR_VBR_Msk            (0x1UL << LTDC_SRCR_VBR_Pos)              /*!< 0x00000002 */

+#define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */

+

+/********************  Bit definition for LTDC_BCCR register  *****************/

+

+#define LTDC_BCCR_BCBLUE_Pos         (0U)

+#define LTDC_BCCR_BCBLUE_Msk         (0xFFUL << LTDC_BCCR_BCBLUE_Pos)          /*!< 0x000000FF */

+#define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value  */

+#define LTDC_BCCR_BCGREEN_Pos        (8U)

+#define LTDC_BCCR_BCGREEN_Msk        (0xFFUL << LTDC_BCCR_BCGREEN_Pos)         /*!< 0x0000FF00 */

+#define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */

+#define LTDC_BCCR_BCRED_Pos          (16U)

+#define LTDC_BCCR_BCRED_Msk          (0xFFUL << LTDC_BCCR_BCRED_Pos)           /*!< 0x00FF0000 */

+#define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value   */

+

+/********************  Bit definition for LTDC_IER register  ******************/

+

+#define LTDC_IER_LIE_Pos             (0U)

+#define LTDC_IER_LIE_Msk             (0x1UL << LTDC_IER_LIE_Pos)               /*!< 0x00000001 */

+#define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable            */

+#define LTDC_IER_FUIE_Pos            (1U)

+#define LTDC_IER_FUIE_Msk            (0x1UL << LTDC_IER_FUIE_Pos)              /*!< 0x00000002 */

+#define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable   */

+#define LTDC_IER_TERRIE_Pos          (2U)

+#define LTDC_IER_TERRIE_Msk          (0x1UL << LTDC_IER_TERRIE_Pos)            /*!< 0x00000004 */

+#define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable  */

+#define LTDC_IER_RRIE_Pos            (3U)

+#define LTDC_IER_RRIE_Msk            (0x1UL << LTDC_IER_RRIE_Pos)              /*!< 0x00000008 */

+#define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */

+

+/********************  Bit definition for LTDC_ISR register  ******************/

+

+#define LTDC_ISR_LIF_Pos             (0U)

+#define LTDC_ISR_LIF_Msk             (0x1UL << LTDC_ISR_LIF_Pos)               /*!< 0x00000001 */

+#define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */

+#define LTDC_ISR_FUIF_Pos            (1U)

+#define LTDC_ISR_FUIF_Msk            (0x1UL << LTDC_ISR_FUIF_Pos)              /*!< 0x00000002 */

+#define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */

+#define LTDC_ISR_TERRIF_Pos          (2U)

+#define LTDC_ISR_TERRIF_Msk          (0x1UL << LTDC_ISR_TERRIF_Pos)            /*!< 0x00000004 */

+#define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */

+#define LTDC_ISR_RRIF_Pos            (3U)

+#define LTDC_ISR_RRIF_Msk            (0x1UL << LTDC_ISR_RRIF_Pos)              /*!< 0x00000008 */

+#define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */

+

+/********************  Bit definition for LTDC_ICR register  ******************/

+

+#define LTDC_ICR_CLIF_Pos            (0U)

+#define LTDC_ICR_CLIF_Msk            (0x1UL << LTDC_ICR_CLIF_Pos)              /*!< 0x00000001 */

+#define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */

+#define LTDC_ICR_CFUIF_Pos           (1U)

+#define LTDC_ICR_CFUIF_Msk           (0x1UL << LTDC_ICR_CFUIF_Pos)             /*!< 0x00000002 */

+#define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */

+#define LTDC_ICR_CTERRIF_Pos         (2U)

+#define LTDC_ICR_CTERRIF_Msk         (0x1UL << LTDC_ICR_CTERRIF_Pos)           /*!< 0x00000004 */

+#define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */

+#define LTDC_ICR_CRRIF_Pos           (3U)

+#define LTDC_ICR_CRRIF_Msk           (0x1UL << LTDC_ICR_CRRIF_Pos)             /*!< 0x00000008 */

+#define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */

+

+/********************  Bit definition for LTDC_LIPCR register  ****************/

+

+#define LTDC_LIPCR_LIPOS_Pos         (0U)

+#define LTDC_LIPCR_LIPOS_Msk         (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)         /*!< 0x000007FF */

+#define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */

+

+/********************  Bit definition for LTDC_CPSR register  *****************/

+

+#define LTDC_CPSR_CYPOS_Pos          (0U)

+#define LTDC_CPSR_CYPOS_Msk          (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)         /*!< 0x0000FFFF */

+#define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */

+#define LTDC_CPSR_CXPOS_Pos          (16U)

+#define LTDC_CPSR_CXPOS_Msk          (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)         /*!< 0xFFFF0000 */

+#define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */

+

+/********************  Bit definition for LTDC_CDSR register  *****************/

+

+#define LTDC_CDSR_VDES_Pos           (0U)

+#define LTDC_CDSR_VDES_Msk           (0x1UL << LTDC_CDSR_VDES_Pos)             /*!< 0x00000001 */

+#define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status       */

+#define LTDC_CDSR_HDES_Pos           (1U)

+#define LTDC_CDSR_HDES_Msk           (0x1UL << LTDC_CDSR_HDES_Pos)             /*!< 0x00000002 */

+#define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status     */

+#define LTDC_CDSR_VSYNCS_Pos         (2U)

+#define LTDC_CDSR_VSYNCS_Msk         (0x1UL << LTDC_CDSR_VSYNCS_Pos)           /*!< 0x00000004 */

+#define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status   */

+#define LTDC_CDSR_HSYNCS_Pos         (3U)

+#define LTDC_CDSR_HSYNCS_Msk         (0x1UL << LTDC_CDSR_HSYNCS_Pos)           /*!< 0x00000008 */

+#define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */

+

+/********************  Bit definition for LTDC_LxCR register  *****************/

+

+#define LTDC_LxCR_LEN_Pos            (0U)

+#define LTDC_LxCR_LEN_Msk            (0x1UL << LTDC_LxCR_LEN_Pos)              /*!< 0x00000001 */

+#define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable              */

+#define LTDC_LxCR_COLKEN_Pos         (1U)

+#define LTDC_LxCR_COLKEN_Msk         (0x1UL << LTDC_LxCR_COLKEN_Pos)           /*!< 0x00000002 */

+#define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable       */

+#define LTDC_LxCR_CLUTEN_Pos         (4U)

+#define LTDC_LxCR_CLUTEN_Msk         (0x1UL << LTDC_LxCR_CLUTEN_Pos)           /*!< 0x00000010 */

+#define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */

+

+/********************  Bit definition for LTDC_LxWHPCR register  **************/

+

+#define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)

+#define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)     /*!< 0x00000FFF */

+#define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */

+#define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)

+#define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)    /*!< 0xFFFF0000 */

+#define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position  */

+

+/********************  Bit definition for LTDC_LxWVPCR register  **************/

+

+#define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)

+#define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)     /*!< 0x00000FFF */

+#define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */

+#define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)

+#define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)    /*!< 0xFFFF0000 */

+#define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position  */

+

+/********************  Bit definition for LTDC_LxCKCR register  ***************/

+

+#define LTDC_LxCKCR_CKBLUE_Pos       (0U)

+#define LTDC_LxCKCR_CKBLUE_Msk       (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value  */

+#define LTDC_LxCKCR_CKGREEN_Pos      (8U)

+#define LTDC_LxCKCR_CKGREEN_Msk      (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */

+#define LTDC_LxCKCR_CKRED_Pos        (16U)

+#define LTDC_LxCKCR_CKRED_Msk        (0xFFUL << LTDC_LxCKCR_CKRED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value   */

+

+/********************  Bit definition for LTDC_LxPFCR register  ***************/

+

+#define LTDC_LxPFCR_PF_Pos           (0U)

+#define LTDC_LxPFCR_PF_Msk           (0x7UL << LTDC_LxPFCR_PF_Pos)             /*!< 0x00000007 */

+#define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */

+

+/********************  Bit definition for LTDC_LxCACR register  ***************/

+

+#define LTDC_LxCACR_CONSTA_Pos       (0U)

+#define LTDC_LxCACR_CONSTA_Msk       (0xFFUL << LTDC_LxCACR_CONSTA_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */

+

+/********************  Bit definition for LTDC_LxDCCR register  ***************/

+

+#define LTDC_LxDCCR_DCBLUE_Pos       (0U)

+#define LTDC_LxDCCR_DCBLUE_Msk       (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue  */

+#define LTDC_LxDCCR_DCGREEN_Pos      (8U)

+#define LTDC_LxDCCR_DCGREEN_Msk      (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */

+#define LTDC_LxDCCR_DCRED_Pos        (16U)

+#define LTDC_LxDCCR_DCRED_Msk        (0xFFUL << LTDC_LxDCCR_DCRED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red   */

+#define LTDC_LxDCCR_DCALPHA_Pos      (24U)

+#define LTDC_LxDCCR_DCALPHA_Msk      (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)       /*!< 0xFF000000 */

+#define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */

+

+/********************  Bit definition for LTDC_LxBFCR register  ***************/

+

+#define LTDC_LxBFCR_BF2_Pos          (0U)

+#define LTDC_LxBFCR_BF2_Msk          (0x7UL << LTDC_LxBFCR_BF2_Pos)            /*!< 0x00000007 */

+#define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */

+#define LTDC_LxBFCR_BF1_Pos          (8U)

+#define LTDC_LxBFCR_BF1_Msk          (0x7UL << LTDC_LxBFCR_BF1_Pos)            /*!< 0x00000700 */

+#define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */

+

+/********************  Bit definition for LTDC_LxCFBAR register  **************/

+

+#define LTDC_LxCFBAR_CFBADD_Pos      (0U)

+#define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */

+#define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */

+

+/********************  Bit definition for LTDC_LxCFBLR register  **************/

+

+#define LTDC_LxCFBLR_CFBLL_Pos       (0U)

+#define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)      /*!< 0x00001FFF */

+#define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length    */

+#define LTDC_LxCFBLR_CFBP_Pos        (16U)

+#define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)       /*!< 0x1FFF0000 */

+#define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */

+

+/********************  Bit definition for LTDC_LxCFBLNR register  *************/

+

+#define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)

+#define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)    /*!< 0x000007FF */

+#define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */

+

+/********************  Bit definition for LTDC_LxCLUTWR register  *************/

+

+#define LTDC_LxCLUTWR_BLUE_Pos       (0U)

+#define LTDC_LxCLUTWR_BLUE_Msk       (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value   */

+#define LTDC_LxCLUTWR_GREEN_Pos      (8U)

+#define LTDC_LxCLUTWR_GREEN_Msk      (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value  */

+#define LTDC_LxCLUTWR_RED_Pos        (16U)

+#define LTDC_LxCLUTWR_RED_Msk        (0xFFUL << LTDC_LxCLUTWR_RED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value    */

+#define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)

+#define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)     /*!< 0xFF000000 */

+#define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                     MDMA                                   */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for MDMA_GISR0 register  ****************/

+#define MDMA_GISR0_GIF0_Pos       (0U)

+#define MDMA_GISR0_GIF0_Msk       (0x1UL << MDMA_GISR0_GIF0_Pos)               /*!< 0x00000001 */

+#define MDMA_GISR0_GIF0           MDMA_GISR0_GIF0_Msk                          /*!< Channel 0 global interrupt flag */

+#define MDMA_GISR0_GIF1_Pos       (1U)

+#define MDMA_GISR0_GIF1_Msk       (0x1UL << MDMA_GISR0_GIF1_Pos)               /*!< 0x00000002 */

+#define MDMA_GISR0_GIF1           MDMA_GISR0_GIF1_Msk                          /*!< Channel 1 global interrupt flag */

+#define MDMA_GISR0_GIF2_Pos       (2U)

+#define MDMA_GISR0_GIF2_Msk       (0x1UL << MDMA_GISR0_GIF2_Pos)               /*!< 0x00000004 */

+#define MDMA_GISR0_GIF2           MDMA_GISR0_GIF2_Msk                          /*!< Channel 2 global interrupt flag */

+#define MDMA_GISR0_GIF3_Pos       (3U)

+#define MDMA_GISR0_GIF3_Msk       (0x1UL << MDMA_GISR0_GIF3_Pos)               /*!< 0x00000008 */

+#define MDMA_GISR0_GIF3           MDMA_GISR0_GIF3_Msk                          /*!< Channel 3 global interrupt flag */

+#define MDMA_GISR0_GIF4_Pos       (4U)

+#define MDMA_GISR0_GIF4_Msk       (0x1UL << MDMA_GISR0_GIF4_Pos)               /*!< 0x00000010 */

+#define MDMA_GISR0_GIF4           MDMA_GISR0_GIF4_Msk                          /*!< Channel 4 global interrupt flag */

+#define MDMA_GISR0_GIF5_Pos       (5U)

+#define MDMA_GISR0_GIF5_Msk       (0x1UL << MDMA_GISR0_GIF5_Pos)               /*!< 0x00000020 */

+#define MDMA_GISR0_GIF5           MDMA_GISR0_GIF5_Msk                          /*!< Channel 5 global interrupt flag */

+#define MDMA_GISR0_GIF6_Pos       (6U)

+#define MDMA_GISR0_GIF6_Msk       (0x1UL << MDMA_GISR0_GIF6_Pos)               /*!< 0x00000040 */

+#define MDMA_GISR0_GIF6           MDMA_GISR0_GIF6_Msk                          /*!< Channel 6 global interrupt flag */

+#define MDMA_GISR0_GIF7_Pos       (7U)

+#define MDMA_GISR0_GIF7_Msk       (0x1UL << MDMA_GISR0_GIF7_Pos)               /*!< 0x00000080 */

+#define MDMA_GISR0_GIF7           MDMA_GISR0_GIF7_Msk                          /*!< Channel 7 global interrupt flag */

+#define MDMA_GISR0_GIF8_Pos       (8U)

+#define MDMA_GISR0_GIF8_Msk       (0x1UL << MDMA_GISR0_GIF8_Pos)               /*!< 0x00000100 */

+#define MDMA_GISR0_GIF8           MDMA_GISR0_GIF8_Msk                          /*!< Channel 8 global interrupt flag */

+#define MDMA_GISR0_GIF9_Pos       (9U)

+#define MDMA_GISR0_GIF9_Msk       (0x1UL << MDMA_GISR0_GIF9_Pos)               /*!< 0x00000200 */

+#define MDMA_GISR0_GIF9           MDMA_GISR0_GIF9_Msk                          /*!< Channel 9 global interrupt flag */

+#define MDMA_GISR0_GIF10_Pos      (10U)

+#define MDMA_GISR0_GIF10_Msk      (0x1UL << MDMA_GISR0_GIF10_Pos)              /*!< 0x00000400 */

+#define MDMA_GISR0_GIF10          MDMA_GISR0_GIF10_Msk                         /*!< Channel 10 global interrupt flag */

+#define MDMA_GISR0_GIF11_Pos      (11U)

+#define MDMA_GISR0_GIF11_Msk      (0x1UL << MDMA_GISR0_GIF11_Pos)              /*!< 0x00000800 */

+#define MDMA_GISR0_GIF11          MDMA_GISR0_GIF11_Msk                         /*!< Channel 11 global interrupt flag */

+#define MDMA_GISR0_GIF12_Pos      (12U)

+#define MDMA_GISR0_GIF12_Msk      (0x1UL << MDMA_GISR0_GIF12_Pos)              /*!< 0x00001000 */

+#define MDMA_GISR0_GIF12          MDMA_GISR0_GIF12_Msk                         /*!< Channel 12 global interrupt flag */

+#define MDMA_GISR0_GIF13_Pos      (13U)

+#define MDMA_GISR0_GIF13_Msk      (0x1UL << MDMA_GISR0_GIF13_Pos)              /*!< 0x00002000 */

+#define MDMA_GISR0_GIF13          MDMA_GISR0_GIF13_Msk                         /*!< Channel 13 global interrupt flag */

+#define MDMA_GISR0_GIF14_Pos      (14U)

+#define MDMA_GISR0_GIF14_Msk      (0x1UL << MDMA_GISR0_GIF14_Pos)              /*!< 0x00004000 */

+#define MDMA_GISR0_GIF14          MDMA_GISR0_GIF14_Msk                         /*!< Channel 14 global interrupt flag */

+#define MDMA_GISR0_GIF15_Pos      (15U)

+#define MDMA_GISR0_GIF15_Msk      (0x1UL << MDMA_GISR0_GIF15_Pos)              /*!< 0x00008000 */

+#define MDMA_GISR0_GIF15          MDMA_GISR0_GIF15_Msk                         /*!< Channel 15 global interrupt flag */

+

+/********************  Bit definition for MDMA_CxISR register  ****************/

+#define MDMA_CISR_TEIF_Pos        (0U)

+#define MDMA_CISR_TEIF_Msk        (0x1UL << MDMA_CISR_TEIF_Pos)                /*!< 0x00000001 */

+#define MDMA_CISR_TEIF            MDMA_CISR_TEIF_Msk                           /*!< Channel x transfer error interrupt flag */

+#define MDMA_CISR_CTCIF_Pos       (1U)

+#define MDMA_CISR_CTCIF_Msk       (0x1UL << MDMA_CISR_CTCIF_Pos)               /*!< 0x00000002 */

+#define MDMA_CISR_CTCIF           MDMA_CISR_CTCIF_Msk                          /*!< Channel x Channel Transfer Complete interrupt flag */

+#define MDMA_CISR_BRTIF_Pos       (2U)

+#define MDMA_CISR_BRTIF_Msk       (0x1UL << MDMA_CISR_BRTIF_Pos)               /*!< 0x00000004 */

+#define MDMA_CISR_BRTIF           MDMA_CISR_BRTIF_Msk                          /*!< Channel x block repeat transfer complete interrupt flag */

+#define MDMA_CISR_BTIF_Pos        (3U)

+#define MDMA_CISR_BTIF_Msk        (0x1UL << MDMA_CISR_BTIF_Pos)                /*!< 0x00000008 */

+#define MDMA_CISR_BTIF            MDMA_CISR_BTIF_Msk                           /*!< Channel x block transfer complete interrupt flag */

+#define MDMA_CISR_TCIF_Pos        (4U)

+#define MDMA_CISR_TCIF_Msk        (0x1UL << MDMA_CISR_TCIF_Pos)                /*!< 0x00000010 */

+#define MDMA_CISR_TCIF            MDMA_CISR_TCIF_Msk                           /*!< Channel x buffer transfer complete interrupt flag */

+#define MDMA_CISR_CRQA_Pos        (16U)

+#define MDMA_CISR_CRQA_Msk        (0x1UL << MDMA_CISR_CRQA_Pos)                /*!< 0x00010000 */

+#define MDMA_CISR_CRQA            MDMA_CISR_CRQA_Msk                           /*!< Channel x ReQest Active flag */

+

+/********************  Bit definition for MDMA_CxIFCR register  ****************/

+#define MDMA_CIFCR_CTEIF_Pos      (0U)

+#define MDMA_CIFCR_CTEIF_Msk      (0x1UL << MDMA_CIFCR_CTEIF_Pos)              /*!< 0x00000001 */

+#define MDMA_CIFCR_CTEIF          MDMA_CIFCR_CTEIF_Msk                         /*!< Channel x clear transfer error interrupt flag */

+#define MDMA_CIFCR_CCTCIF_Pos     (1U)

+#define MDMA_CIFCR_CCTCIF_Msk     (0x1UL << MDMA_CIFCR_CCTCIF_Pos)             /*!< 0x00000002 */

+#define MDMA_CIFCR_CCTCIF         MDMA_CIFCR_CCTCIF_Msk                        /*!< Clear Channel transfer complete interrupt flag for channel x */

+#define MDMA_CIFCR_CBRTIF_Pos     (2U)

+#define MDMA_CIFCR_CBRTIF_Msk     (0x1UL << MDMA_CIFCR_CBRTIF_Pos)             /*!< 0x00000004 */

+#define MDMA_CIFCR_CBRTIF         MDMA_CIFCR_CBRTIF_Msk                        /*!< Channel x clear block repeat transfer complete interrupt flag */

+#define MDMA_CIFCR_CBTIF_Pos      (3U)

+#define MDMA_CIFCR_CBTIF_Msk      (0x1UL << MDMA_CIFCR_CBTIF_Pos)              /*!< 0x00000008 */

+#define MDMA_CIFCR_CBTIF          MDMA_CIFCR_CBTIF_Msk                         /*!< Channel x Clear block transfer complete interrupt flag */

+#define MDMA_CIFCR_CLTCIF_Pos     (4U)

+#define MDMA_CIFCR_CLTCIF_Msk     (0x1UL << MDMA_CIFCR_CLTCIF_Pos)             /*!< 0x00000010 */

+#define MDMA_CIFCR_CLTCIF         MDMA_CIFCR_CLTCIF_Msk                        /*!< CLear Transfer buffer Complete Interrupt Flag for channel */

+

+/********************  Bit definition for MDMA_CxESR register  ****************/

+#define MDMA_CESR_TEA_Pos         (0U)

+#define MDMA_CESR_TEA_Msk         (0x7FUL << MDMA_CESR_TEA_Pos)                /*!< 0x0000007F */

+#define MDMA_CESR_TEA             MDMA_CESR_TEA_Msk                            /*!< Transfer Error Address */

+#define MDMA_CESR_TED_Pos         (7U)

+#define MDMA_CESR_TED_Msk         (0x1UL << MDMA_CESR_TED_Pos)                 /*!< 0x00000080 */

+#define MDMA_CESR_TED             MDMA_CESR_TED_Msk                            /*!< Transfer Error Direction */

+#define MDMA_CESR_TELD_Pos        (8U)

+#define MDMA_CESR_TELD_Msk        (0x1UL << MDMA_CESR_TELD_Pos)                /*!< 0x00000100 */

+#define MDMA_CESR_TELD            MDMA_CESR_TELD_Msk                           /*!< Transfer Error Link Data */

+#define MDMA_CESR_TEMD_Pos        (9U)

+#define MDMA_CESR_TEMD_Msk        (0x1UL << MDMA_CESR_TEMD_Pos)                /*!< 0x00000200 */

+#define MDMA_CESR_TEMD            MDMA_CESR_TEMD_Msk                           /*!< Transfer Error Mask Data */

+#define MDMA_CESR_ASE_Pos         (10U)

+#define MDMA_CESR_ASE_Msk         (0x1UL << MDMA_CESR_ASE_Pos)                 /*!< 0x00000400 */

+#define MDMA_CESR_ASE             MDMA_CESR_ASE_Msk                            /*!< Address/Size Error       */

+#define MDMA_CESR_BSE_Pos         (11U)

+#define MDMA_CESR_BSE_Msk         (0x1UL << MDMA_CESR_BSE_Pos)                 /*!< 0x00000800 */

+#define MDMA_CESR_BSE             MDMA_CESR_BSE_Msk                            /*!< Block Size Error         */

+

+/********************  Bit definition for MDMA_CxCR register  ****************/

+#define MDMA_CCR_EN_Pos           (0U)

+#define MDMA_CCR_EN_Msk           (0x1UL << MDMA_CCR_EN_Pos)                   /*!< 0x00000001 */

+#define MDMA_CCR_EN               MDMA_CCR_EN_Msk                              /*!< Channel enable / flag channel ready when read low */

+#define MDMA_CCR_TEIE_Pos         (1U)

+#define MDMA_CCR_TEIE_Msk         (0x1UL << MDMA_CCR_TEIE_Pos)                 /*!< 0x00000002 */

+#define MDMA_CCR_TEIE             MDMA_CCR_TEIE_Msk                            /*!< Transfer error interrupt enable */

+#define MDMA_CCR_CTCIE_Pos        (2U)

+#define MDMA_CCR_CTCIE_Msk        (0x1UL << MDMA_CCR_CTCIE_Pos)                /*!< 0x00000004 */

+#define MDMA_CCR_CTCIE            MDMA_CCR_CTCIE_Msk                           /*!< Channel Transfer Complete interrupt enable */

+#define MDMA_CCR_BRTIE_Pos        (3U)

+#define MDMA_CCR_BRTIE_Msk        (0x1UL << MDMA_CCR_BRTIE_Pos)                /*!< 0x00000008 */

+#define MDMA_CCR_BRTIE            MDMA_CCR_BRTIE_Msk                           /*!< Block Repeat transfer interrupt enable */

+#define MDMA_CCR_BTIE_Pos         (4U)

+#define MDMA_CCR_BTIE_Msk         (0x1UL << MDMA_CCR_BTIE_Pos)                 /*!< 0x00000010 */

+#define MDMA_CCR_BTIE             MDMA_CCR_BTIE_Msk                            /*!< Block Transfer interrupt enable */

+#define MDMA_CCR_TCIE_Pos         (5U)

+#define MDMA_CCR_TCIE_Msk         (0x1UL << MDMA_CCR_TCIE_Pos)                 /*!< 0x00000020 */

+#define MDMA_CCR_TCIE             MDMA_CCR_TCIE_Msk                            /*!< buffer Transfer Complete interrupt enable */

+#define MDMA_CCR_PL_Pos           (6U)

+#define MDMA_CCR_PL_Msk           (0x3UL << MDMA_CCR_PL_Pos)                   /*!< 0x000000C0 */

+#define MDMA_CCR_PL               MDMA_CCR_PL_Msk                              /*!< Priority level */

+#define MDMA_CCR_PL_0             (0x1UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000040 */

+#define MDMA_CCR_PL_1             (0x2UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000080 */

+#define MDMA_CCR_BEX_Pos          (12U)

+#define MDMA_CCR_BEX_Msk          (0x1UL << MDMA_CCR_BEX_Pos)                  /*!< 0x00001000 */

+#define MDMA_CCR_BEX              MDMA_CCR_BEX_Msk                             /*!< Byte Endianess eXchange */

+#define MDMA_CCR_HEX_Pos          (13U)

+#define MDMA_CCR_HEX_Msk          (0x1UL << MDMA_CCR_HEX_Pos)                  /*!< 0x00002000 */

+#define MDMA_CCR_HEX              MDMA_CCR_HEX_Msk                             /*!< Half word Endianess eXchange */

+#define MDMA_CCR_WEX_Pos          (14U)

+#define MDMA_CCR_WEX_Msk          (0x1UL << MDMA_CCR_WEX_Pos)                  /*!< 0x00004000 */

+#define MDMA_CCR_WEX              MDMA_CCR_WEX_Msk                             /*!< Word Endianess eXchange */

+#define MDMA_CCR_SWRQ_Pos         (16U)

+#define MDMA_CCR_SWRQ_Msk         (0x1UL << MDMA_CCR_SWRQ_Pos)                 /*!< 0x00010000 */

+#define MDMA_CCR_SWRQ             MDMA_CCR_SWRQ_Msk                            /*!< SW ReQuest */

+

+/********************  Bit definition for MDMA_CxTCR register  ****************/

+#define MDMA_CTCR_SINC_Pos        (0U)

+#define MDMA_CTCR_SINC_Msk        (0x3UL << MDMA_CTCR_SINC_Pos)                /*!< 0x00000003 */

+#define MDMA_CTCR_SINC            MDMA_CTCR_SINC_Msk                           /*!< Source increment mode */

+#define MDMA_CTCR_SINC_0          (0x1UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000001 */

+#define MDMA_CTCR_SINC_1          (0x2UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000002 */

+#define MDMA_CTCR_DINC_Pos        (2U)

+#define MDMA_CTCR_DINC_Msk        (0x3UL << MDMA_CTCR_DINC_Pos)                /*!< 0x0000000C */

+#define MDMA_CTCR_DINC            MDMA_CTCR_DINC_Msk                           /*!< Source increment mode */

+#define MDMA_CTCR_DINC_0          (0x1UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000004 */

+#define MDMA_CTCR_DINC_1          (0x2UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000008 */

+#define MDMA_CTCR_SSIZE_Pos       (4U)

+#define MDMA_CTCR_SSIZE_Msk       (0x3UL << MDMA_CTCR_SSIZE_Pos)               /*!< 0x00000030 */

+#define MDMA_CTCR_SSIZE           MDMA_CTCR_SSIZE_Msk                          /*!< Source data size */

+#define MDMA_CTCR_SSIZE_0         (0x1UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000010 */

+#define MDMA_CTCR_SSIZE_1         (0x2UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000020 */

+#define MDMA_CTCR_DSIZE_Pos       (6U)

+#define MDMA_CTCR_DSIZE_Msk       (0x3UL << MDMA_CTCR_DSIZE_Pos)               /*!< 0x000000C0 */

+#define MDMA_CTCR_DSIZE           MDMA_CTCR_DSIZE_Msk                          /*!< Destination data size */

+#define MDMA_CTCR_DSIZE_0         (0x1UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000040 */

+#define MDMA_CTCR_DSIZE_1         (0x2UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000080 */

+#define MDMA_CTCR_SINCOS_Pos      (8U)

+#define MDMA_CTCR_SINCOS_Msk      (0x3UL << MDMA_CTCR_SINCOS_Pos)              /*!< 0x00000300 */

+#define MDMA_CTCR_SINCOS          MDMA_CTCR_SINCOS_Msk                         /*!< Source increment offset size */

+#define MDMA_CTCR_SINCOS_0        (0x1UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000100 */

+#define MDMA_CTCR_SINCOS_1        (0x2UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000200 */

+#define MDMA_CTCR_DINCOS_Pos      (10U)

+#define MDMA_CTCR_DINCOS_Msk      (0x3UL << MDMA_CTCR_DINCOS_Pos)              /*!< 0x00000C00 */

+#define MDMA_CTCR_DINCOS          MDMA_CTCR_DINCOS_Msk                         /*!< Destination increment offset size */

+#define MDMA_CTCR_DINCOS_0        (0x1UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000400 */

+#define MDMA_CTCR_DINCOS_1        (0x2UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000800 */

+#define MDMA_CTCR_SBURST_Pos      (12U)

+#define MDMA_CTCR_SBURST_Msk      (0x7UL << MDMA_CTCR_SBURST_Pos)              /*!< 0x00007000 */

+#define MDMA_CTCR_SBURST          MDMA_CTCR_SBURST_Msk                         /*!< Source burst transfer configuration */

+#define MDMA_CTCR_SBURST_0        (0x1UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00001000 */

+#define MDMA_CTCR_SBURST_1        (0x2UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00002000 */

+#define MDMA_CTCR_SBURST_2        (0x4UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00004000 */

+#define MDMA_CTCR_DBURST_Pos      (15U)

+#define MDMA_CTCR_DBURST_Msk      (0x7UL << MDMA_CTCR_DBURST_Pos)              /*!< 0x00038000 */

+#define MDMA_CTCR_DBURST          MDMA_CTCR_DBURST_Msk                         /*!< Destination burst transfer configuration */

+#define MDMA_CTCR_DBURST_0        (0x1UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00008000 */

+#define MDMA_CTCR_DBURST_1        (0x2UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00010000 */

+#define MDMA_CTCR_DBURST_2        (0x4UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00020000 */

+#define MDMA_CTCR_TLEN_Pos        (18U)

+#define MDMA_CTCR_TLEN_Msk        (0x7FUL << MDMA_CTCR_TLEN_Pos)               /*!< 0x01FC0000 */

+#define MDMA_CTCR_TLEN            MDMA_CTCR_TLEN_Msk                           /*!< buffer Transfer Length (number of bytes - 1) */

+#define MDMA_CTCR_PKE_Pos         (25U)

+#define MDMA_CTCR_PKE_Msk         (0x1UL << MDMA_CTCR_PKE_Pos)                 /*!< 0x02000000 */

+#define MDMA_CTCR_PKE             MDMA_CTCR_PKE_Msk                            /*!< PacK Enable */

+#define MDMA_CTCR_PAM_Pos         (26U)

+#define MDMA_CTCR_PAM_Msk         (0x3UL << MDMA_CTCR_PAM_Pos)                 /*!< 0x0C000000 */

+#define MDMA_CTCR_PAM             MDMA_CTCR_PAM_Msk                            /*!< Padding/Alignement Mode */

+#define MDMA_CTCR_PAM_0           (0x1UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x4000000 */

+#define MDMA_CTCR_PAM_1           (0x2UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x8000000 */

+#define MDMA_CTCR_TRGM_Pos        (28U)

+#define MDMA_CTCR_TRGM_Msk        (0x3UL << MDMA_CTCR_TRGM_Pos)                /*!< 0x30000000 */

+#define MDMA_CTCR_TRGM            MDMA_CTCR_TRGM_Msk                           /*!< Trigger Mode */

+#define MDMA_CTCR_TRGM_0          (0x1UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x10000000 */

+#define MDMA_CTCR_TRGM_1          (0x2UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x20000000 */

+#define MDMA_CTCR_SWRM_Pos        (30U)

+#define MDMA_CTCR_SWRM_Msk        (0x1UL << MDMA_CTCR_SWRM_Pos)                /*!< 0x40000000 */

+#define MDMA_CTCR_SWRM            MDMA_CTCR_SWRM_Msk                           /*!< SW Request Mode */

+#define MDMA_CTCR_BWM_Pos         (31U)

+#define MDMA_CTCR_BWM_Msk         (0x1UL << MDMA_CTCR_BWM_Pos)                 /*!< 0x80000000 */

+#define MDMA_CTCR_BWM             MDMA_CTCR_BWM_Msk                            /*!< Bufferable Write Mode */

+

+/********************  Bit definition for MDMA_CxBNDTR register  ****************/

+#define MDMA_CBNDTR_BNDT_Pos      (0U)

+#define MDMA_CBNDTR_BNDT_Msk      (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos)          /*!< 0x0001FFFF */

+#define MDMA_CBNDTR_BNDT          MDMA_CBNDTR_BNDT_Msk                         /*!< Block Number of data bytes to transfer */

+#define MDMA_CBNDTR_BRSUM_Pos     (18U)

+#define MDMA_CBNDTR_BRSUM_Msk     (0x1UL << MDMA_CBNDTR_BRSUM_Pos)             /*!< 0x00040000 */

+#define MDMA_CBNDTR_BRSUM         MDMA_CBNDTR_BRSUM_Msk                        /*!< Block Repeat Source address Update Mode */

+#define MDMA_CBNDTR_BRDUM_Pos     (19U)

+#define MDMA_CBNDTR_BRDUM_Msk     (0x1UL << MDMA_CBNDTR_BRDUM_Pos)             /*!< 0x00080000 */

+#define MDMA_CBNDTR_BRDUM         MDMA_CBNDTR_BRDUM_Msk                        /*!< Block Repeat Destination address Update Mode */

+#define MDMA_CBNDTR_BRC_Pos       (20U)

+#define MDMA_CBNDTR_BRC_Msk       (0xFFFUL << MDMA_CBNDTR_BRC_Pos)             /*!< 0xFFF00000 */

+#define MDMA_CBNDTR_BRC           MDMA_CBNDTR_BRC_Msk                          /*!< Block Repeat Count */

+

+/********************  Bit definition for MDMA_CxSAR register  ****************/

+#define MDMA_CSAR_SAR_Pos         (0U)

+#define MDMA_CSAR_SAR_Msk         (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CSAR_SAR             MDMA_CSAR_SAR_Msk                            /*!< Source address */

+

+/********************  Bit definition for MDMA_CxDAR register  ****************/

+#define MDMA_CDAR_DAR_Pos         (0U)

+#define MDMA_CDAR_DAR_Msk         (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CDAR_DAR             MDMA_CDAR_DAR_Msk                            /*!< Destination address */

+

+/********************  Bit definition for MDMA_CxBRUR  ************************/

+#define MDMA_CBRUR_SUV_Pos        (0U)

+#define MDMA_CBRUR_SUV_Msk        (0xFFFFUL << MDMA_CBRUR_SUV_Pos)             /*!< 0x0000FFFF */

+#define MDMA_CBRUR_SUV            MDMA_CBRUR_SUV_Msk                           /*!< Source address Update Value */

+#define MDMA_CBRUR_DUV_Pos        (16U)

+#define MDMA_CBRUR_DUV_Msk        (0xFFFFUL << MDMA_CBRUR_DUV_Pos)             /*!< 0xFFFF0000 */

+#define MDMA_CBRUR_DUV            MDMA_CBRUR_DUV_Msk                           /*!< Destination address Update Value */

+

+/********************  Bit definition for MDMA_CxLAR  *************************/

+#define MDMA_CLAR_LAR_Pos         (0U)

+#define MDMA_CLAR_LAR_Msk         (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CLAR_LAR             MDMA_CLAR_LAR_Msk                            /*!< Link Address Register */

+

+/********************  Bit definition for MDMA_CxTBR)  ************************/

+#define MDMA_CTBR_TSEL_Pos        (0U)

+#define MDMA_CTBR_TSEL_Msk        (0xFFUL << MDMA_CTBR_TSEL_Pos)               /*!< 0x000000FF */

+#define MDMA_CTBR_TSEL            MDMA_CTBR_TSEL_Msk                           /*!< Trigger SELection */

+#define MDMA_CTBR_SBUS_Pos        (16U)

+#define MDMA_CTBR_SBUS_Msk        (0x1UL << MDMA_CTBR_SBUS_Pos)                /*!< 0x00010000 */

+#define MDMA_CTBR_SBUS            MDMA_CTBR_SBUS_Msk                           /*!< Source BUS select */

+#define MDMA_CTBR_DBUS_Pos        (17U)

+#define MDMA_CTBR_DBUS_Msk        (0x1UL << MDMA_CTBR_DBUS_Pos)                /*!< 0x00020000 */

+#define MDMA_CTBR_DBUS            MDMA_CTBR_DBUS_Msk                           /*!< Destination BUS select */

+

+/********************  Bit definition for MDMA_CxMAR)  ************************/

+#define MDMA_CMAR_MAR_Pos         (0U)

+#define MDMA_CMAR_MAR_Msk         (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CMAR_MAR             MDMA_CMAR_MAR_Msk                            /*!< Mask address */

+

+/********************  Bit definition for MDMA_CxMDR)  ************************/

+#define MDMA_CMDR_MDR_Pos         (0U)

+#define MDMA_CMDR_MDR_Msk         (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CMDR_MDR             MDMA_CMDR_MDR_Msk                            /*!< Mask Data */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Operational Amplifier (OPAMP)                      */

+/*                                                                            */

+/******************************************************************************/

+/*********************  Bit definition for OPAMPx_CSR register  ***************/

+#define OPAMP_CSR_OPAMPxEN_Pos           (0U)

+#define OPAMP_CSR_OPAMPxEN_Msk           (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)     /*!< 0x00000001 */

+#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */

+#define OPAMP_CSR_FORCEVP_Pos            (1U)

+#define OPAMP_CSR_FORCEVP_Msk            (0x1UL << OPAMP_CSR_FORCEVP_Pos)      /*!< 0x00000002 */

+#define OPAMP_CSR_FORCEVP                OPAMP_CSR_FORCEVP_Msk                 /*!< Force internal reference on VP */

+

+#define OPAMP_CSR_VPSEL_Pos              (2U)

+#define OPAMP_CSR_VPSEL_Msk              (0x3UL << OPAMP_CSR_VPSEL_Pos)        /*!< 0x0000000C */

+#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */

+#define OPAMP_CSR_VPSEL_0                (0x1UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000004 */

+#define OPAMP_CSR_VPSEL_1                (0x2UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000008 */

+

+#define OPAMP_CSR_VMSEL_Pos              (5U)

+#define OPAMP_CSR_VMSEL_Msk              (0x3UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000060 */

+#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */

+#define OPAMP_CSR_VMSEL_0                (0x1UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000020 */

+#define OPAMP_CSR_VMSEL_1                (0x2UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000040 */

+

+#define OPAMP_CSR_OPAHSM_Pos             (8U)

+#define OPAMP_CSR_OPAHSM_Msk             (0x1UL << OPAMP_CSR_OPAHSM_Pos)       /*!< 0x00000100 */

+#define OPAMP_CSR_OPAHSM                 OPAMP_CSR_OPAHSM_Msk                  /*!< Operational amplifier high speed mode */

+#define OPAMP_CSR_CALON_Pos              (11U)

+#define OPAMP_CSR_CALON_Msk              (0x1UL << OPAMP_CSR_CALON_Pos)        /*!< 0x00000800 */

+#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */

+

+#define OPAMP_CSR_CALSEL_Pos             (12U)

+#define OPAMP_CSR_CALSEL_Msk             (0x3UL << OPAMP_CSR_CALSEL_Pos)       /*!< 0x00003000 */

+#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */

+#define OPAMP_CSR_CALSEL_0               (0x1UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00001000 */

+#define OPAMP_CSR_CALSEL_1               (0x2UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */

+

+#define OPAMP_CSR_PGGAIN_Pos             (14U)

+#define OPAMP_CSR_PGGAIN_Msk             (0xFUL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x0003C000 */

+#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */

+#define OPAMP_CSR_PGGAIN_0               (0x1UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00004000 */

+#define OPAMP_CSR_PGGAIN_1               (0x2UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00008000 */

+#define OPAMP_CSR_PGGAIN_2               (0x4UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00010000 */

+#define OPAMP_CSR_PGGAIN_3               (0x8UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00020000 */

+

+#define OPAMP_CSR_USERTRIM_Pos           (18U)

+#define OPAMP_CSR_USERTRIM_Msk           (0x1UL << OPAMP_CSR_USERTRIM_Pos)     /*!< 0x00040000 */

+#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */

+#define OPAMP_CSR_TSTREF_Pos             (29U)

+#define OPAMP_CSR_TSTREF_Msk             (0x1UL << OPAMP_CSR_TSTREF_Pos)       /*!< 0x20000000 */

+#define OPAMP_CSR_TSTREF                 OPAMP_CSR_TSTREF_Msk                  /*!< OpAmp calibration reference voltage output control */

+#define OPAMP_CSR_CALOUT_Pos             (30U)

+#define OPAMP_CSR_CALOUT_Msk             (0x1UL << OPAMP_CSR_CALOUT_Pos)       /*!< 0x40000000 */

+#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier calibration output */

+

+/*********************  Bit definition for OPAMP1_CSR register  ***************/

+#define OPAMP1_CSR_OPAEN_Pos              (0U)

+#define OPAMP1_CSR_OPAEN_Msk              (0x1UL << OPAMP1_CSR_OPAEN_Pos)      /*!< 0x00000001 */

+#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */

+#define OPAMP1_CSR_FORCEVP_Pos            (1U)

+#define OPAMP1_CSR_FORCEVP_Msk            (0x1UL << OPAMP1_CSR_FORCEVP_Pos)    /*!< 0x00000002 */

+#define OPAMP1_CSR_FORCEVP                OPAMP1_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */

+

+#define OPAMP1_CSR_VPSEL_Pos              (2U)

+#define OPAMP1_CSR_VPSEL_Msk              (0x3UL << OPAMP1_CSR_VPSEL_Pos)      /*!< 0x0000000C */

+#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */

+#define OPAMP1_CSR_VPSEL_0                (0x1UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000004 */

+#define OPAMP1_CSR_VPSEL_1                (0x2UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000008 */

+

+#define OPAMP1_CSR_VMSEL_Pos              (5U)

+#define OPAMP1_CSR_VMSEL_Msk              (0x3UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000060 */

+#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */

+#define OPAMP1_CSR_VMSEL_0                (0x1UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000020 */

+#define OPAMP1_CSR_VMSEL_1                (0x2UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000040 */

+

+#define OPAMP1_CSR_OPAHSM_Pos             (8U)

+#define OPAMP1_CSR_OPAHSM_Msk             (0x1UL << OPAMP1_CSR_OPAHSM_Pos)     /*!< 0x00000100 */

+#define OPAMP1_CSR_OPAHSM                 OPAMP1_CSR_OPAHSM_Msk                /*!< Operational amplifier1 high speed mode */

+#define OPAMP1_CSR_CALON_Pos              (11U)

+#define OPAMP1_CSR_CALON_Msk              (0x1UL << OPAMP1_CSR_CALON_Pos)      /*!< 0x00000800 */

+#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */

+

+#define OPAMP1_CSR_CALSEL_Pos             (12U)

+#define OPAMP1_CSR_CALSEL_Msk             (0x3UL << OPAMP1_CSR_CALSEL_Pos)     /*!< 0x00003000 */

+#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */

+#define OPAMP1_CSR_CALSEL_0               (0x1UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00001000 */

+#define OPAMP1_CSR_CALSEL_1               (0x2UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */

+

+#define OPAMP1_CSR_PGGAIN_Pos             (14U)

+#define OPAMP1_CSR_PGGAIN_Msk             (0xFUL << OPAMP1_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */

+#define OPAMP1_CSR_PGGAIN                 OPAMP1_CSR_PGGAIN_Msk                /*!< Operational amplifier1 Programmable amplifier gain value */

+#define OPAMP1_CSR_PGGAIN_0               (0x1UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00004000 */

+#define OPAMP1_CSR_PGGAIN_1               (0x2UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00008000 */

+#define OPAMP1_CSR_PGGAIN_2               (0x4UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00010000 */

+#define OPAMP1_CSR_PGGAIN_3               (0x8UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00020000 */

+

+#define OPAMP1_CSR_USERTRIM_Pos           (18U)

+#define OPAMP1_CSR_USERTRIM_Msk           (0x1UL << OPAMP1_CSR_USERTRIM_Pos)   /*!< 0x00040000 */

+#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */

+#define OPAMP1_CSR_TSTREF_Pos             (29U)

+#define OPAMP1_CSR_TSTREF_Msk             (0x1UL << OPAMP1_CSR_TSTREF_Pos)     /*!< 0x20000000 */

+#define OPAMP1_CSR_TSTREF                 OPAMP1_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */

+#define OPAMP1_CSR_CALOUT_Pos             (30U)

+#define OPAMP1_CSR_CALOUT_Msk             (0x1UL << OPAMP1_CSR_CALOUT_Pos)     /*!< 0x40000000 */

+#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */

+

+/*********************  Bit definition for OPAMP2_CSR register  ***************/

+#define OPAMP2_CSR_OPAEN_Pos              (0U)

+#define OPAMP2_CSR_OPAEN_Msk              (0x1UL << OPAMP2_CSR_OPAEN_Pos)      /*!< 0x00000001 */

+#define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */

+#define OPAMP2_CSR_FORCEVP_Pos            (1U)

+#define OPAMP2_CSR_FORCEVP_Msk            (0x1UL << OPAMP2_CSR_FORCEVP_Pos)    /*!< 0x00000002 */

+#define OPAMP2_CSR_FORCEVP                OPAMP2_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */

+

+#define OPAMP2_CSR_VPSEL_Pos              (2U)

+#define OPAMP2_CSR_VPSEL_Msk              (0x3UL << OPAMP2_CSR_VPSEL_Pos)      /*!< 0x0000000C */

+#define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */

+#define OPAMP2_CSR_VPSEL_0                (0x1UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000004 */

+#define OPAMP2_CSR_VPSEL_1                (0x2UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000008 */

+

+#define OPAMP2_CSR_VMSEL_Pos              (5U)

+#define OPAMP2_CSR_VMSEL_Msk              (0x3UL << OPAMP2_CSR_VMSEL_Pos)      /*!< 0x00000060 */

+#define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */

+#define OPAMP2_CSR_VMSEL_0                (0x1UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000020 */

+#define OPAMP2_CSR_VMSEL_1                (0x2UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000040 */

+

+#define OPAMP2_CSR_OPAHSM_Pos             (8U)

+#define OPAMP2_CSR_OPAHSM_Msk             (0x1UL << OPAMP2_CSR_OPAHSM_Pos)     /*!< 0x00000100 */

+#define OPAMP2_CSR_OPAHSM                 OPAMP2_CSR_OPAHSM_Msk                /*!< Operational amplifier2 high speed mode */

+#define OPAMP2_CSR_CALON_Pos              (11U)

+#define OPAMP2_CSR_CALON_Msk              (0x1UL << OPAMP2_CSR_CALON_Pos)      /*!< 0x00000800 */

+#define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */

+

+#define OPAMP2_CSR_CALSEL_Pos             (12U)

+#define OPAMP2_CSR_CALSEL_Msk             (0x3UL << OPAMP2_CSR_CALSEL_Pos)     /*!< 0x00003000 */

+#define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */

+#define OPAMP2_CSR_CALSEL_0               (0x1UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00001000 */

+#define OPAMP2_CSR_CALSEL_1               (0x2UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */

+

+#define OPAMP2_CSR_PGGAIN_Pos             (14U)

+#define OPAMP2_CSR_PGGAIN_Msk             (0xFUL << OPAMP2_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */

+#define OPAMP2_CSR_PGGAIN                 OPAMP2_CSR_PGGAIN_Msk                /*!< Operational amplifier2 Programmable amplifier gain value */

+#define OPAMP2_CSR_PGGAIN_0               (0x1UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00004000 */

+#define OPAMP2_CSR_PGGAIN_1               (0x2UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00008000 */

+#define OPAMP2_CSR_PGGAIN_2               (0x4UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00010000 */

+#define OPAMP2_CSR_PGGAIN_3               (0x8UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00020000 */

+

+#define OPAMP2_CSR_USERTRIM_Pos           (18U)

+#define OPAMP2_CSR_USERTRIM_Msk           (0x1UL << OPAMP2_CSR_USERTRIM_Pos)   /*!< 0x00040000 */

+#define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */

+#define OPAMP2_CSR_TSTREF_Pos             (29U)

+#define OPAMP2_CSR_TSTREF_Msk             (0x1UL << OPAMP2_CSR_TSTREF_Pos)     /*!< 0x20000000 */

+#define OPAMP2_CSR_TSTREF                 OPAMP2_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */

+#define OPAMP2_CSR_CALOUT_Pos             (30U)

+#define OPAMP2_CSR_CALOUT_Msk             (0x1UL << OPAMP2_CSR_CALOUT_Pos)     /*!< 0x40000000 */

+#define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */

+

+/*******************  Bit definition for OPAMP_OTR register  ******************/

+#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */

+#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP1_OTR register  ******************/

+#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */

+#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP2_OTR register  ******************/

+#define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */

+#define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP_HSOTR register  ****************/

+#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP_HSOTR_TRIMHSOFFSETN        OPAMP_HSOTR_TRIMHSOFFSETN_Msk         /*!< Trim for NMOS differential pairs */

+#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP_HSOTR_TRIMHSOFFSETP        OPAMP_HSOTR_TRIMHSOFFSETP_Msk         /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP1_HSOTR register  ****************/

+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP1_HSOTR_TRIMHSOFFSETN        OPAMP1_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */

+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP1_HSOTR_TRIMHSOFFSETP        OPAMP1_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP2_HSOTR register  ****************/

+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP2_HSOTR_TRIMHSOFFSETN        OPAMP2_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */

+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP2_HSOTR_TRIMHSOFFSETP        OPAMP2_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */

+

+/******************************************************************************/

+/*                                                                            */

+/*                Parallel Synchronous Slave Interface (PSSI )                */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for PSSI_CR register  *******************/

+#define PSSI_CR_OUTEN_Pos               (31U)

+#define PSSI_CR_OUTEN_Msk               (0x1UL << PSSI_CR_OUTEN_Pos)           /*!< 0x80000000 */

+#define PSSI_CR_OUTEN                   PSSI_CR_OUTEN_Msk                      /*!< Data direction selection */

+#define PSSI_CR_DMAEN_Pos               (30U)

+#define PSSI_CR_DMAEN_Msk               (0x1UL << PSSI_CR_DMAEN_Pos)           /*!< 0x40000000 */

+#define PSSI_CR_DMAEN                   PSSI_CR_DMAEN_Msk                      /*!< DMA enable */

+#define PSSI_CR_DERDYCFG_Pos            (18U)

+#define PSSI_CR_DERDYCFG_Msk            (0x7UL << PSSI_CR_DERDYCFG_Pos)        /*!< 0x001C0000 */

+#define PSSI_CR_DERDYCFG                PSSI_CR_DERDYCFG_Msk                   /*!< Data enable and ready configuration */

+#define PSSI_CR_ENABLE_Pos              (14U)

+#define PSSI_CR_ENABLE_Msk              (0x1UL << PSSI_CR_ENABLE_Pos)          /*!< 0x00004000 */

+#define PSSI_CR_ENABLE                  PSSI_CR_ENABLE_Msk                     /*!< PSSI enable */

+#define PSSI_CR_EDM_Pos                 (10U)

+#define PSSI_CR_EDM_Msk                 (0x3UL << PSSI_CR_EDM_Pos)             /*!< 0x00000C00 */

+#define PSSI_CR_EDM                     PSSI_CR_EDM_Msk                        /*!< Extended data mode */

+#define PSSI_CR_RDYPOL_Pos              (8U)

+#define PSSI_CR_RDYPOL_Msk              (0x1UL << PSSI_CR_RDYPOL_Pos)          /*!< 0x00000C00 */

+#define PSSI_CR_RDYPOL                  PSSI_CR_RDYPOL_Msk                     /*!< Ready polarity */

+#define PSSI_CR_DEPOL_Pos               (6U)

+#define PSSI_CR_DEPOL_Msk               (0x1UL << PSSI_CR_DEPOL_Pos)           /*!< 0x00000C00 */

+#define PSSI_CR_DEPOL                   PSSI_CR_DEPOL_Msk                      /*!<  Data enable polarity */

+#define PSSI_CR_CKPOL_Pos               (5U)

+#define PSSI_CR_CKPOL_Msk               (0x1UL << PSSI_CR_CKPOL_Pos)           /*!< 0x00000C00 */

+#define PSSI_CR_CKPOL                   PSSI_CR_CKPOL_Msk                      /*!< Parallel data clock polarity */

+/********************  Bit definition for PSSI_SR register  *******************/

+#define PSSI_SR_RTT1B_Pos               (3U)

+#define PSSI_SR_RTT1B_Msk               (0x1UL << PSSI_SR_RTT1B_Pos)           /*!< 0x00000008 */

+#define PSSI_SR_RTT1B                   PSSI_SR_RTT1B_Msk                      /*!< Ready to transfer one byte */

+#define PSSI_SR_RTT4B_Pos               (2U)

+#define PSSI_SR_RTT4B_Msk               (0x1UL << PSSI_SR_RTT4B_Pos)           /*!< 0x00000004 */

+#define PSSI_SR_RTT4B                   PSSI_SR_RTT4B_Msk                      /*!< Ready to transfer four bytes */

+/********************  Bit definition for PSSI_RIS register  *******************/

+#define PSSI_RIS_OVR_RIS_Pos            (1U)

+#define PSSI_RIS_OVR_RIS_Msk            (0x1UL << PSSI_RIS_OVR_RIS_Pos)        /*!< 0x00000002 */

+#define PSSI_RIS_OVR_RIS                PSSI_RIS_OVR_RIS_Msk                   /*!< Data buffer overrun/underrun raw interrupt status */

+/********************  Bit definition for PSSI_IER register  *******************/

+#define PSSI_IER_OVR_IE_Pos             (1U)

+#define PSSI_IER_OVR_IE_Msk             (0x1UL << PSSI_IER_OVR_IE_Pos)         /*!< 0x00000002 */

+#define PSSI_IER_OVR_IE                 PSSI_IER_OVR_IE_Msk                    /*!< Data buffer overrun/underrun interrupt enable */

+/********************  Bit definition for PSSI_MIS register  *******************/

+#define PSSI_MIS_OVR_MIS_Pos            (1U)

+#define PSSI_MIS_OVR_MIS_Msk            (0x1UL << PSSI_MIS_OVR_MIS_Pos)        /*!< 0x00000002 */

+#define PSSI_MIS_OVR_MIS                PSSI_MIS_OVR_MIS_Msk                   /*!< Data buffer overrun/underrun masked interrupt status */

+/********************  Bit definition for PSSI_ICR register  *******************/

+#define PSSI_ICR_OVR_ISC_Pos            (1U)

+#define PSSI_ICR_OVR_ISC_Msk            (0x1UL << PSSI_ICR_OVR_ISC_Pos)        /*!< 0x00000002 */

+#define PSSI_ICR_OVR_ISC                PSSI_ICR_OVR_ISC_Msk                   /*!< Data buffer overrun/underrun interrupt status clear */

+/********************  Bit definition for PSSI_DR register  *******************/

+#define PSSI_DR_DR_Pos                  (0U)

+#define PSSI_DR_DR_Msk                  (0xFFFFFFFFUL << PSSI_DR_DR_Pos)       /*!< 0xFFFFFFF */

+#define PSSI_DR_DR                      PSSI_DR_DR_Msk                         /*!< Data register  */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             Power Control                                  */

+/*                                                                            */

+/******************************************************************************/

+/*************************  NUMBER OF POWER DOMAINS  **************************/

+#define POWER_DOMAINS_NUMBER           2U                                      /*!< 2 Domains */

+

+/********************  Bit definition for PWR_CR1 register  *******************/

+#define PWR_CR1_SRDRAMSO_Pos           (27U)

+#define PWR_CR1_SRDRAMSO_Msk           (0x1UL << PWR_CR1_SRDRAMSO_Pos)         /*!< 0x08000000 */

+#define PWR_CR1_SRDRAMSO               PWR_CR1_SRDRAMSO_Msk                    /*!< SmartRun Domain AHB Memory Shut-Off in DStop/DStop2 Low-Power Mode */

+#define PWR_CR1_HSITFSO_Pos            (26U)

+#define PWR_CR1_HSITFSO_Msk            (0x1UL << PWR_CR1_HSITFSO_Pos)          /*!< 0x04000000 */

+#define PWR_CR1_HSITFSO                PWR_CR1_HSITFSO_Msk                     /*!< High-Speed Interfaces USB and FDCAN Memories Shut-off in DStop/DStop2 Mode */

+#define PWR_CR1_GFXSO_Pos              (25U)

+#define PWR_CR1_GFXSO_Msk              (0x1UL << PWR_CR1_GFXSO_Pos)            /*!< 0x02000000 */

+#define PWR_CR1_GFXSO                  PWR_CR1_GFXSO_Msk                       /*!< GFXMMU and JPEG Memories Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_ITCMSO_Pos             (24U)

+#define PWR_CR1_ITCMSO_Msk             (0x1UL << PWR_CR1_ITCMSO_Pos)           /*!< 0x01000000 */

+#define PWR_CR1_ITCMSO                 PWR_CR1_ITCMSO_Msk                      /*!< Instruction TCM and ETM Memories Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_AHBRAM2SO_Pos          (23U)

+#define PWR_CR1_AHBRAM2SO_Msk          (0x1UL << PWR_CR1_AHBRAM2SO_Pos)        /*!< 0x00800000 */

+#define PWR_CR1_AHBRAM2SO              PWR_CR1_AHBRAM2SO_Msk                   /*!< AHB RAM2 Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_AHBRAM1SO_Pos          (22U)

+#define PWR_CR1_AHBRAM1SO_Msk          (0x1UL << PWR_CR1_AHBRAM1SO_Pos)        /*!< 0x00400000 */

+#define PWR_CR1_AHBRAM1SO              PWR_CR1_AHBRAM1SO_Msk                   /*!< AHB RAM1 Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_AXIRAM3SO_Pos          (21U)

+#define PWR_CR1_AXIRAM3SO_Msk          (0x1UL << PWR_CR1_AXIRAM3SO_Pos)        /*!< 0x00200000 */

+#define PWR_CR1_AXIRAM3SO              PWR_CR1_AXIRAM3SO_Msk                   /*!< AXI RAM3 Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_AXIRAM2SO_Pos          (20U)

+#define PWR_CR1_AXIRAM2SO_Msk          (0x1UL << PWR_CR1_AXIRAM2SO_Pos)        /*!< 0x00100000 */

+#define PWR_CR1_AXIRAM2SO              PWR_CR1_AXIRAM2SO_Msk                   /*!< AXI RAM2 Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_AXIRAM1SO_Pos          (19U)

+#define PWR_CR1_AXIRAM1SO_Msk          (0x1UL << PWR_CR1_AXIRAM1SO_Pos)        /*!< 0x00080000 */

+#define PWR_CR1_AXIRAM1SO              PWR_CR1_AXIRAM1SO_Msk                   /*!< AXI RAM1 Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_ALS_Pos                (17U)

+#define PWR_CR1_ALS_Msk                (0x3UL << PWR_CR1_ALS_Pos)              /*!< 0x00060000 */

+#define PWR_CR1_ALS                    PWR_CR1_ALS_Msk                         /*!< Analog Voltage Detector level selection */

+#define PWR_CR1_ALS_0                  (0x1UL << PWR_CR1_ALS_Pos)              /*!< 0x00020000 */

+#define PWR_CR1_ALS_1                  (0x2UL << PWR_CR1_ALS_Pos)              /*!< 0x00040000 */

+#define PWR_CR1_AVDEN_Pos              (16U)

+#define PWR_CR1_AVDEN_Msk              (0x1UL << PWR_CR1_AVDEN_Pos)            /*!< 0x00010000 */

+#define PWR_CR1_AVDEN                  PWR_CR1_AVDEN_Msk                       /*!< Analog Voltage Detector Enable */

+#define PWR_CR1_SVOS_Pos               (14U)

+#define PWR_CR1_SVOS_Msk               (0x3UL << PWR_CR1_SVOS_Pos)             /*!< 0x0000C000 */

+#define PWR_CR1_SVOS                   PWR_CR1_SVOS_Msk                        /*!< System STOP mode Voltage Scaling selection */

+#define PWR_CR1_SVOS_0                 (0x1UL << PWR_CR1_SVOS_Pos)             /*!< 0x00004000 */

+#define PWR_CR1_SVOS_1                 (0x2UL << PWR_CR1_SVOS_Pos)             /*!< 0x00008000 */

+#define PWR_CR1_AVD_READY_Pos          (13U)

+#define PWR_CR1_AVD_READY_Msk          (0x1UL << PWR_CR1_AVD_READY_Pos)        /*!< 0x00002000 */

+#define PWR_CR1_AVD_READY              PWR_CR1_AVD_READY_Msk                   /*!< Analog Voltage Ready. */

+#define PWR_CR1_BOOSTE_Pos             (12U)

+#define PWR_CR1_BOOSTE_Msk             (0x1UL << PWR_CR1_BOOSTE_Pos)           /*!< 0x00001000 */

+#define PWR_CR1_BOOSTE                 PWR_CR1_BOOSTE_Msk                      /*!< Analog Switch VBoost control */

+#define PWR_CR1_FLPS_Pos               (9U)

+#define PWR_CR1_FLPS_Msk               (0x1UL << PWR_CR1_FLPS_Pos)             /*!< 0x00000200 */

+#define PWR_CR1_FLPS                   PWR_CR1_FLPS_Msk                        /*!< Flash low power mode in DSTOP */

+#define PWR_CR1_DBP_Pos                (8U)

+#define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */

+#define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable Back-up domain Protection */

+#define PWR_CR1_PLS_Pos                (5U)

+#define PWR_CR1_PLS_Msk                (0x7UL << PWR_CR1_PLS_Pos)              /*!< 0x000000E0 */

+#define PWR_CR1_PLS                    PWR_CR1_PLS_Msk                         /*!< Programmable Voltage Detector level selection */

+#define PWR_CR1_PLS_0                  (0x1UL << PWR_CR1_PLS_Pos)              /*!< 0x00000020 */

+#define PWR_CR1_PLS_1                  (0x2UL << PWR_CR1_PLS_Pos)              /*!< 0x00000040 */

+#define PWR_CR1_PLS_2                  (0x4UL << PWR_CR1_PLS_Pos)              /*!< 0x00000080 */

+#define PWR_CR1_PVDEN_Pos              (4U)

+#define PWR_CR1_PVDEN_Msk              (0x1UL << PWR_CR1_PVDEN_Pos)            /*!< 0x00000010 */

+#define PWR_CR1_PVDEN                  PWR_CR1_PVDEN_Msk                       /*!< Programmable Voltage detector enable */

+#define PWR_CR1_LPDS_Pos               (0U)

+#define PWR_CR1_LPDS_Msk               (0x1UL << PWR_CR1_LPDS_Pos)             /*!< 0x00000001 */

+#define PWR_CR1_LPDS                   PWR_CR1_LPDS_Msk                        /*!< Low Power Deepsleep with SVOS3 */

+

+/*!< PVD level configuration */

+#define PWR_CR1_PLS_LEV0               (0UL)                                   /*!< PVD level 0 */

+#define PWR_CR1_PLS_LEV1_Pos           (5U)

+#define PWR_CR1_PLS_LEV1_Msk           (0x1UL << PWR_CR1_PLS_LEV1_Pos)         /*!< 0x00000020 */

+#define PWR_CR1_PLS_LEV1               PWR_CR1_PLS_LEV1_Msk                    /*!< PVD level 1 */

+#define PWR_CR1_PLS_LEV2_Pos           (6U)

+#define PWR_CR1_PLS_LEV2_Msk           (0x1UL << PWR_CR1_PLS_LEV2_Pos)         /*!< 0x00000040 */

+#define PWR_CR1_PLS_LEV2               PWR_CR1_PLS_LEV2_Msk                    /*!< PVD level 2 */

+#define PWR_CR1_PLS_LEV3_Pos           (5U)

+#define PWR_CR1_PLS_LEV3_Msk           (0x3UL << PWR_CR1_PLS_LEV3_Pos)         /*!< 0x00000060 */

+#define PWR_CR1_PLS_LEV3               PWR_CR1_PLS_LEV3_Msk                    /*!< PVD level 3 */

+#define PWR_CR1_PLS_LEV4_Pos           (7U)

+#define PWR_CR1_PLS_LEV4_Msk           (0x1UL << PWR_CR1_PLS_LEV4_Pos)         /*!< 0x00000080 */

+#define PWR_CR1_PLS_LEV4               PWR_CR1_PLS_LEV4_Msk                    /*!< PVD level 4 */

+#define PWR_CR1_PLS_LEV5_Pos           (5U)

+#define PWR_CR1_PLS_LEV5_Msk           (0x5UL << PWR_CR1_PLS_LEV5_Pos)         /*!< 0x000000A0 */

+#define PWR_CR1_PLS_LEV5               PWR_CR1_PLS_LEV5_Msk                    /*!< PVD level 5 */

+#define PWR_CR1_PLS_LEV6_Pos           (6U)

+#define PWR_CR1_PLS_LEV6_Msk           (0x3UL << PWR_CR1_PLS_LEV6_Pos)         /*!< 0x000000C0 */

+#define PWR_CR1_PLS_LEV6               PWR_CR1_PLS_LEV6_Msk                    /*!< PVD level 6 */

+#define PWR_CR1_PLS_LEV7_Pos           (5U)

+#define PWR_CR1_PLS_LEV7_Msk           (0x7UL << PWR_CR1_PLS_LEV7_Pos)         /*!< 0x000000E0 */

+#define PWR_CR1_PLS_LEV7               PWR_CR1_PLS_LEV7_Msk                    /*!< PVD level 7 */

+

+/*!< AVD level configuration */

+#define PWR_CR1_ALS_LEV0               (0UL)                                   /*!< AVD level 0 */

+#define PWR_CR1_ALS_LEV1_Pos           (17U)

+#define PWR_CR1_ALS_LEV1_Msk           (0x1UL << PWR_CR1_ALS_LEV1_Pos)         /*!< 0x00020000 */

+#define PWR_CR1_ALS_LEV1               PWR_CR1_ALS_LEV1_Msk                    /*!< AVD level 1 */

+#define PWR_CR1_ALS_LEV2_Pos           (18U)

+#define PWR_CR1_ALS_LEV2_Msk           (0x1UL << PWR_CR1_ALS_LEV2_Pos)         /*!< 0x00040000 */

+#define PWR_CR1_ALS_LEV2               PWR_CR1_ALS_LEV2_Msk                    /*!< AVD level 2 */

+#define PWR_CR1_ALS_LEV3_Pos           (17U)

+#define PWR_CR1_ALS_LEV3_Msk           (0x3UL << PWR_CR1_ALS_LEV3_Pos)         /*!< 0x00060000 */

+#define PWR_CR1_ALS_LEV3               PWR_CR1_ALS_LEV3_Msk                    /*!< AVD level 3 */

+

+/********************  Bit definition for PWR_CSR1 register  ******************/

+#define PWR_CSR1_MMCVDO_Pos            (17U)

+#define PWR_CSR1_MMCVDO_Msk            (0x1UL << PWR_CSR1_MMCVDO_Pos)          /*!< 0x00020000                        */

+#define PWR_CSR1_MMCVDO                PWR_CSR1_MMCVDO_Msk                     /*!< voltage detector output on VDDMMC */

+#define PWR_CSR1_AVDO_Pos              (16U)

+#define PWR_CSR1_AVDO_Msk              (0x1UL << PWR_CSR1_AVDO_Pos)            /*!< 0x00010000 */

+#define PWR_CSR1_AVDO                  PWR_CSR1_AVDO_Msk                       /*!< Analog Voltage Detect Output */

+#define PWR_CSR1_ACTVOS_Pos            (14U)

+#define PWR_CSR1_ACTVOS_Msk            (0x3UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x0000C000 */

+#define PWR_CSR1_ACTVOS                PWR_CSR1_ACTVOS_Msk                     /*!< Current actual used VOS for VDD11 Voltage Scaling */

+#define PWR_CSR1_ACTVOS_0              (0x1UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00004000 */

+#define PWR_CSR1_ACTVOS_1              (0x2UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00008000 */

+#define PWR_CSR1_ACTVOSRDY_Pos         (13U)

+#define PWR_CSR1_ACTVOSRDY_Msk         (0x1UL << PWR_CSR1_ACTVOSRDY_Pos)       /*!< 0x00002000 */

+#define PWR_CSR1_ACTVOSRDY             PWR_CSR1_ACTVOSRDY_Msk                  /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling  */

+#define PWR_CSR1_PVDO_Pos              (4U)

+#define PWR_CSR1_PVDO_Msk              (0x1UL << PWR_CSR1_PVDO_Pos)            /*!< 0x00000010 */

+#define PWR_CSR1_PVDO                  PWR_CSR1_PVDO_Msk                       /*!< Programmable Voltage Detect Output */

+

+/********************  Bit definition for PWR_CR2 register  *******************/

+#define PWR_CR2_TEMPH_Pos              (23U)

+#define PWR_CR2_TEMPH_Msk              (0x1UL << PWR_CR2_TEMPH_Pos)            /*!< 0x00800000 */

+#define PWR_CR2_TEMPH                  PWR_CR2_TEMPH_Msk                       /*!< Monitored temperature level above high threshold */

+#define PWR_CR2_TEMPL_Pos              (22U)

+#define PWR_CR2_TEMPL_Msk              (0x1UL << PWR_CR2_TEMPL_Pos)            /*!< 0x00400000 */

+#define PWR_CR2_TEMPL                  PWR_CR2_TEMPL_Msk                       /*!< Monitored temperature level above low threshold */

+#define PWR_CR2_VBATH_Pos              (21U)

+#define PWR_CR2_VBATH_Msk              (0x1UL << PWR_CR2_VBATH_Pos)            /*!< 0x00200000 */

+#define PWR_CR2_VBATH                  PWR_CR2_VBATH_Msk                       /*!< Monitored VBAT level above high threshold */

+#define PWR_CR2_VBATL_Pos              (20U)

+#define PWR_CR2_VBATL_Msk              (0x1UL << PWR_CR2_VBATL_Pos)            /*!< 0x00100000 */

+#define PWR_CR2_VBATL                  PWR_CR2_VBATL_Msk                       /*!< Monitored VBAT level above low threshold */

+#define PWR_CR2_BRRDY_Pos              (16U)

+#define PWR_CR2_BRRDY_Msk              (0x1UL << PWR_CR2_BRRDY_Pos)            /*!< 0x00010000 */

+#define PWR_CR2_BRRDY                  PWR_CR2_BRRDY_Msk                       /*!< Backup regulator ready */

+#define PWR_CR2_MONEN_Pos              (4U)

+#define PWR_CR2_MONEN_Msk              (0x1UL << PWR_CR2_MONEN_Pos)            /*!< 0x00000010 */

+#define PWR_CR2_MONEN                  PWR_CR2_MONEN_Msk                       /*!< VBAT and temperature monitoring enable */

+#define PWR_CR2_BREN_Pos               (0U)

+#define PWR_CR2_BREN_Msk               (0x1UL << PWR_CR2_BREN_Pos)             /*!< 0x00000001 */

+#define PWR_CR2_BREN                   PWR_CR2_BREN_Msk                        /*!< Backup regulator enable */

+

+/********************  Bit definition for PWR_CR3 register  *******************/

+#define PWR_CR3_USB33RDY_Pos           (26U)

+#define PWR_CR3_USB33RDY_Msk           (0x1UL << PWR_CR3_USB33RDY_Pos)         /*!< 0x04000000 */

+#define PWR_CR3_USB33RDY               PWR_CR3_USB33RDY_Msk                    /*!< USB supply ready */

+#define PWR_CR3_USBREGEN_Pos           (25U)

+#define PWR_CR3_USBREGEN_Msk           (0x1UL << PWR_CR3_USBREGEN_Pos)         /*!< 0x02000000 */

+#define PWR_CR3_USBREGEN               PWR_CR3_USBREGEN_Msk                    /*!< USB regulator enable */

+#define PWR_CR3_USB33DEN_Pos           (24U)

+#define PWR_CR3_USB33DEN_Msk           (0x1UL << PWR_CR3_USB33DEN_Pos)         /*!< 0x01000000 */

+#define PWR_CR3_USB33DEN               PWR_CR3_USB33DEN_Msk                    /*!< VDD33_USB voltage level detector enable */

+#define PWR_CR3_VBRS_Pos               (9U)

+#define PWR_CR3_VBRS_Msk               (0x1UL << PWR_CR3_VBRS_Pos)             /*!< 0x00000200 */

+#define PWR_CR3_VBRS                   PWR_CR3_VBRS_Msk                        /*!< VBAT charging resistor selection */

+#define PWR_CR3_VBE_Pos                (8U)

+#define PWR_CR3_VBE_Msk                (0x1UL << PWR_CR3_VBE_Pos)              /*!< 0x00000100 */

+#define PWR_CR3_VBE                    PWR_CR3_VBE_Msk                         /*!< VBAT charging enable */

+#define PWR_CR3_SCUEN_Pos              (2U)

+#define PWR_CR3_SCUEN_Msk              (0x1UL << PWR_CR3_SCUEN_Pos)            /*!< 0x00000004 */

+#define PWR_CR3_SCUEN                  PWR_CR3_SCUEN_Msk                       /*!< Supply configuration update enable */

+#define PWR_CR3_LDOEN_Pos              (1U)

+#define PWR_CR3_LDOEN_Msk              (0x1UL << PWR_CR3_LDOEN_Pos)            /*!< 0x00000002 */

+#define PWR_CR3_LDOEN                  PWR_CR3_LDOEN_Msk                       /*!< Low Drop Output regulator enable */

+#define PWR_CR3_BYPASS_Pos             (0U)

+#define PWR_CR3_BYPASS_Msk             (0x1UL << PWR_CR3_BYPASS_Pos)           /*!< 0x00000001 */

+#define PWR_CR3_BYPASS                 PWR_CR3_BYPASS_Msk                      /*!< Power Management Unit bypass */

+

+/********************  Bit definition for PWR_CPUCR register  *****************/

+#define PWR_CPUCR_RUN_SRD_Pos          (11U)

+#define PWR_CPUCR_RUN_SRD_Msk          (0x1UL << PWR_CPUCR_RUN_SRD_Pos)        /*!< 0x00000800 */

+#define PWR_CPUCR_RUN_SRD              PWR_CPUCR_RUN_SRD_Msk                   /*!< Keep system SRD domain in RUN mode regardless of the CPU sub-systems modes */

+#define PWR_CPUCR_CSSF_Pos             (9U)

+#define PWR_CPUCR_CSSF_Msk             (0x1UL << PWR_CPUCR_CSSF_Pos)           /*!< 0x00000200 */

+#define PWR_CPUCR_CSSF                 PWR_CPUCR_CSSF_Msk                      /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */

+#define PWR_CPUCR_SBF_Pos              (6U)

+#define PWR_CPUCR_SBF_Msk              (0x1UL << PWR_CPUCR_SBF_Pos)            /*!< 0x00000040 */

+#define PWR_CPUCR_SBF                  PWR_CPUCR_SBF_Msk                       /*!< System STANDBY Flag */

+#define PWR_CPUCR_STOPF_Pos            (5U)

+#define PWR_CPUCR_STOPF_Msk            (0x1UL << PWR_CPUCR_STOPF_Pos)          /*!< 0x00000020 */

+#define PWR_CPUCR_STOPF                PWR_CPUCR_STOPF_Msk                     /*!< STOP Flag */

+#define PWR_CPUCR_PDDS_SRD_Pos         (2U)

+#define PWR_CPUCR_PDDS_SRD_Msk         (0x1UL << PWR_CPUCR_PDDS_SRD_Pos)       /*!< 0x00000004 */

+#define PWR_CPUCR_PDDS_SRD             PWR_CPUCR_PDDS_SRD_Msk                  /*!< System SRD domain Power Down Deepsleep */

+#define PWR_CPUCR_RETDS_CD_Pos         (0U)

+#define PWR_CPUCR_RETDS_CD_Msk         (0x1UL << PWR_CPUCR_RETDS_CD_Pos)       /*!< 0x00000001 */

+#define PWR_CPUCR_RETDS_CD             PWR_CPUCR_RETDS_CD_Msk                  /*!< CD domain Power Down Deepsleep selection */

+/********************  Bit definition for PWR_SRDCR register  *****************/

+#define PWR_SRDCR_VOS_Pos              (14U)

+#define PWR_SRDCR_VOS_Msk              (0x3UL << PWR_SRDCR_VOS_Pos)             /*!< 0x0000C000 */

+#define PWR_SRDCR_VOS                  PWR_SRDCR_VOS_Msk                        /*!< Voltage Scaling selection according performance */

+#define PWR_SRDCR_VOS_0                (0x1UL << PWR_SRDCR_VOS_Pos)             /*!< 0x00004000 */

+#define PWR_SRDCR_VOS_1                (0x2UL << PWR_SRDCR_VOS_Pos)             /*!< 0x00008000 */

+#define PWR_SRDCR_VOSRDY_Pos           (13U)

+#define PWR_SRDCR_VOSRDY_Msk           (0x1UL << PWR_SRDCR_VOSRDY_Pos)          /*!< 0x00002000 */

+#define PWR_SRDCR_VOSRDY               PWR_SRDCR_VOSRDY_Msk                     /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */

+/******************  Bit definition for PWR_WKUPCR register  ******************/

+#define PWR_WKUPCR_WKUPC6_Pos          (5U)

+#define PWR_WKUPCR_WKUPC6_Msk          (0x1UL << PWR_WKUPCR_WKUPC6_Pos)        /*!< 0x00000020 */

+#define PWR_WKUPCR_WKUPC6              PWR_WKUPCR_WKUPC6_Msk                   /*!< Clear Wakeup Pin Flag 6 */

+#define PWR_WKUPCR_WKUPC5_Pos          (4U)

+#define PWR_WKUPCR_WKUPC5_Msk          (0x1UL << PWR_WKUPCR_WKUPC5_Pos)        /*!< 0x00000010 */

+#define PWR_WKUPCR_WKUPC5              PWR_WKUPCR_WKUPC5_Msk                   /*!< Clear Wakeup Pin Flag 5 */

+#define PWR_WKUPCR_WKUPC4_Pos          (3U)

+#define PWR_WKUPCR_WKUPC4_Msk          (0x1UL << PWR_WKUPCR_WKUPC4_Pos)        /*!< 0x00000008 */

+#define PWR_WKUPCR_WKUPC4              PWR_WKUPCR_WKUPC4_Msk                   /*!< Clear Wakeup Pin Flag 4 */

+#define PWR_WKUPCR_WKUPC3_Pos          (2U)

+#define PWR_WKUPCR_WKUPC3_Msk          (0x1UL << PWR_WKUPCR_WKUPC3_Pos)        /*!< 0x00000004 */

+#define PWR_WKUPCR_WKUPC3              PWR_WKUPCR_WKUPC3_Msk                   /*!< Clear Wakeup Pin Flag 3 */

+#define PWR_WKUPCR_WKUPC2_Pos          (1U)

+#define PWR_WKUPCR_WKUPC2_Msk          (0x1UL << PWR_WKUPCR_WKUPC2_Pos)        /*!< 0x00000002 */

+#define PWR_WKUPCR_WKUPC2              PWR_WKUPCR_WKUPC2_Msk                   /*!< Clear Wakeup Pin Flag 2 */

+#define PWR_WKUPCR_WKUPC1_Pos          (0U)

+#define PWR_WKUPCR_WKUPC1_Msk          (0x1UL << PWR_WKUPCR_WKUPC1_Pos)        /*!< 0x00000001 */

+#define PWR_WKUPCR_WKUPC1              PWR_WKUPCR_WKUPC1_Msk                   /*!< Clear Wakeup Pin Flag 1 */

+

+/********************  Bit definition for PWR_WKUPFR register  ****************/

+#define PWR_WKUPFR_WKUPF6_Pos          (5U)

+#define PWR_WKUPFR_WKUPF6_Msk          (0x1UL << PWR_WKUPFR_WKUPF6_Pos)        /*!< 0x00000020 */

+#define PWR_WKUPFR_WKUPF6              PWR_WKUPFR_WKUPF6_Msk                   /*!< Wakeup Pin Flag 6 */

+#define PWR_WKUPFR_WKUPF5_Pos          (4U)

+#define PWR_WKUPFR_WKUPF5_Msk          (0x1UL << PWR_WKUPFR_WKUPF5_Pos)        /*!< 0x00000010 */

+#define PWR_WKUPFR_WKUPF5              PWR_WKUPFR_WKUPF5_Msk                   /*!< Wakeup Pin Flag 5 */

+#define PWR_WKUPFR_WKUPF4_Pos          (3U)

+#define PWR_WKUPFR_WKUPF4_Msk          (0x1UL << PWR_WKUPFR_WKUPF4_Pos)        /*!< 0x00000008 */

+#define PWR_WKUPFR_WKUPF4              PWR_WKUPFR_WKUPF4_Msk                   /*!< Wakeup Pin Flag 4 */

+#define PWR_WKUPFR_WKUPF3_Pos          (2U)

+#define PWR_WKUPFR_WKUPF3_Msk          (0x1UL << PWR_WKUPFR_WKUPF3_Pos)        /*!< 0x00000004 */

+#define PWR_WKUPFR_WKUPF3              PWR_WKUPFR_WKUPF3_Msk                   /*!< Wakeup Pin Flag 3 */

+#define PWR_WKUPFR_WKUPF2_Pos          (1U)

+#define PWR_WKUPFR_WKUPF2_Msk          (0x1UL << PWR_WKUPFR_WKUPF2_Pos)        /*!< 0x00000002 */

+#define PWR_WKUPFR_WKUPF2              PWR_WKUPFR_WKUPF2_Msk                   /*!< Wakeup Pin Flag 2 */

+#define PWR_WKUPFR_WKUPF1_Pos          (0U)

+#define PWR_WKUPFR_WKUPF1_Msk          (0x1UL << PWR_WKUPFR_WKUPF1_Pos)        /*!< 0x00000001 */

+#define PWR_WKUPFR_WKUPF1              PWR_WKUPFR_WKUPF1_Msk                   /*!< Wakeup Pin Flag 1 */

+

+/******************  Bit definition for PWR_WKUPEPR register  *****************/

+#define PWR_WKUPEPR_WKUPPUPD6_Pos      (26U)

+#define PWR_WKUPEPR_WKUPPUPD6_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x0C000000 */

+#define PWR_WKUPEPR_WKUPPUPD6          PWR_WKUPEPR_WKUPPUPD6_Msk               /*!< Wakeup Pin pull configuration for WKUP6 */

+#define PWR_WKUPEPR_WKUPPUPD6_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x04000000 */

+#define PWR_WKUPEPR_WKUPPUPD6_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x08000000 */

+#define PWR_WKUPEPR_WKUPPUPD5_Pos      (24U)

+#define PWR_WKUPEPR_WKUPPUPD5_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x03000000 */

+#define PWR_WKUPEPR_WKUPPUPD5          PWR_WKUPEPR_WKUPPUPD5_Msk               /*!< Wakeup Pin pull configuration for WKUP5 */

+#define PWR_WKUPEPR_WKUPPUPD5_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x01000000 */

+#define PWR_WKUPEPR_WKUPPUPD5_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x02000000 */

+#define PWR_WKUPEPR_WKUPPUPD4_Pos      (22U)

+#define PWR_WKUPEPR_WKUPPUPD4_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00C00000 */

+#define PWR_WKUPEPR_WKUPPUPD4          PWR_WKUPEPR_WKUPPUPD4_Msk               /*!< Wakeup Pin pull configuration for WKUP4 */

+#define PWR_WKUPEPR_WKUPPUPD4_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00400000 */

+#define PWR_WKUPEPR_WKUPPUPD4_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00800000 */

+#define PWR_WKUPEPR_WKUPPUPD3_Pos      (20U)

+#define PWR_WKUPEPR_WKUPPUPD3_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00300000 */

+#define PWR_WKUPEPR_WKUPPUPD3          PWR_WKUPEPR_WKUPPUPD3_Msk               /*!< Wakeup Pin pull configuration for WKUP3 */

+#define PWR_WKUPEPR_WKUPPUPD3_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00100000 */

+#define PWR_WKUPEPR_WKUPPUPD3_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00200000 */

+#define PWR_WKUPEPR_WKUPPUPD2_Pos      (18U)

+#define PWR_WKUPEPR_WKUPPUPD2_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x000C0000 */

+#define PWR_WKUPEPR_WKUPPUPD2          PWR_WKUPEPR_WKUPPUPD2_Msk               /*!< Wakeup Pin pull configuration for WKUP2 */

+#define PWR_WKUPEPR_WKUPPUPD2_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00040000 */

+#define PWR_WKUPEPR_WKUPPUPD2_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00080000 */

+#define PWR_WKUPEPR_WKUPPUPD1_Pos      (16U)

+#define PWR_WKUPEPR_WKUPPUPD1_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00030000 */

+#define PWR_WKUPEPR_WKUPPUPD1          PWR_WKUPEPR_WKUPPUPD1_Msk               /*!< Wakeup Pin pull configuration for WKUP1 */

+#define PWR_WKUPEPR_WKUPPUPD1_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00010000 */

+#define PWR_WKUPEPR_WKUPPUPD1_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00020000 */

+#define PWR_WKUPEPR_WKUPP6_Pos         (13U)

+#define PWR_WKUPEPR_WKUPP6_Msk         (0x1UL << PWR_WKUPEPR_WKUPP6_Pos)       /*!< 0x00002000 */

+#define PWR_WKUPEPR_WKUPP6             PWR_WKUPEPR_WKUPP6_Msk                  /*!< Wakeup Pin Polarity for WKUP6 */

+#define PWR_WKUPEPR_WKUPP5_Pos         (12U)

+#define PWR_WKUPEPR_WKUPP5_Msk         (0x1UL << PWR_WKUPEPR_WKUPP5_Pos)       /*!< 0x00001000 */

+#define PWR_WKUPEPR_WKUPP5             PWR_WKUPEPR_WKUPP5_Msk                  /*!< Wakeup Pin Polarity for WKUP5 */

+#define PWR_WKUPEPR_WKUPP4_Pos         (11U)

+#define PWR_WKUPEPR_WKUPP4_Msk         (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)       /*!< 0x00000800 */

+#define PWR_WKUPEPR_WKUPP4             PWR_WKUPEPR_WKUPP4_Msk                  /*!< Wakeup Pin Polarity for WKUP4 */

+#define PWR_WKUPEPR_WKUPP3_Pos         (10U)

+#define PWR_WKUPEPR_WKUPP3_Msk         (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)       /*!< 0x00000400 */

+#define PWR_WKUPEPR_WKUPP3             PWR_WKUPEPR_WKUPP3_Msk                  /*!< Wakeup Pin Polarity for WKUP3 */

+#define PWR_WKUPEPR_WKUPP2_Pos         (9U)

+#define PWR_WKUPEPR_WKUPP2_Msk         (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)       /*!< 0x00000200 */

+#define PWR_WKUPEPR_WKUPP2             PWR_WKUPEPR_WKUPP2_Msk                  /*!< Wakeup Pin Polarity for WKUP2 */

+#define PWR_WKUPEPR_WKUPP1_Pos         (8U)

+#define PWR_WKUPEPR_WKUPP1_Msk         (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)       /*!< 0x00000100 */

+#define PWR_WKUPEPR_WKUPP1             PWR_WKUPEPR_WKUPP1_Msk                  /*!< Wakeup Pin Polarity for WKUP1 */

+#define PWR_WKUPEPR_WKUPEN6_Pos        (5U)

+#define PWR_WKUPEPR_WKUPEN6_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos)      /*!< 0x00000020 */

+#define PWR_WKUPEPR_WKUPEN6            PWR_WKUPEPR_WKUPEN6_Msk                 /*!< Enable Wakeup Pin WKUP6 */

+#define PWR_WKUPEPR_WKUPEN5_Pos        (4U)

+#define PWR_WKUPEPR_WKUPEN5_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos)      /*!< 0x00000010 */

+#define PWR_WKUPEPR_WKUPEN5            PWR_WKUPEPR_WKUPEN5_Msk                 /*!< Enable Wakeup Pin WKUP5 */

+#define PWR_WKUPEPR_WKUPEN4_Pos        (3U)

+#define PWR_WKUPEPR_WKUPEN4_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)      /*!< 0x00000008 */

+#define PWR_WKUPEPR_WKUPEN4            PWR_WKUPEPR_WKUPEN4_Msk                 /*!< Enable Wakeup Pin WKUP4 */

+#define PWR_WKUPEPR_WKUPEN3_Pos        (2U)

+#define PWR_WKUPEPR_WKUPEN3_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)      /*!< 0x00000004 */

+#define PWR_WKUPEPR_WKUPEN3            PWR_WKUPEPR_WKUPEN3_Msk                 /*!< Enable Wakeup Pin WKUP3 */

+#define PWR_WKUPEPR_WKUPEN2_Pos        (1U)

+#define PWR_WKUPEPR_WKUPEN2_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)      /*!< 0x00000002 */

+#define PWR_WKUPEPR_WKUPEN2            PWR_WKUPEPR_WKUPEN2_Msk                 /*!< Enable Wakeup Pin WKUP2 */

+#define PWR_WKUPEPR_WKUPEN1_Pos        (0U)

+#define PWR_WKUPEPR_WKUPEN1_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)      /*!< 0x00000001 */

+#define PWR_WKUPEPR_WKUPEN1            PWR_WKUPEPR_WKUPEN1_Msk                 /*!< Enable Wakeup Pin WKUP1 */

+#define PWR_WKUPEPR_WKUPEN_Pos         (0U)

+#define PWR_WKUPEPR_WKUPEN_Msk         (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos)      /*!< 0x0000003F */

+#define PWR_WKUPEPR_WKUPEN             PWR_WKUPEPR_WKUPEN_Msk                  /*!< Enable all Wakeup Pin */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Reset and Clock Control                            */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  RCC VERSION  ********************************/

+#define RCC_VER_2_0

+

+/********************  Bit definition for RCC_CR register  ********************/

+#define RCC_CR_HSION_Pos                       (0U)

+#define RCC_CR_HSION_Msk                       (0x1UL << RCC_CR_HSION_Pos)     /*!< 0x00000001 */

+#define RCC_CR_HSION                           RCC_CR_HSION_Msk                /*!< Internal High Speed clock enable */

+#define RCC_CR_HSIKERON_Pos                    (1U)

+#define RCC_CR_HSIKERON_Msk                    (0x1UL << RCC_CR_HSIKERON_Pos)  /*!< 0x00000002 */

+#define RCC_CR_HSIKERON                        RCC_CR_HSIKERON_Msk             /*!< Internal High Speed clock enable for some IPs Kernel */

+#define RCC_CR_HSIRDY_Pos                      (2U)

+#define RCC_CR_HSIRDY_Msk                      (0x1UL << RCC_CR_HSIRDY_Pos)    /*!< 0x00000004 */

+#define RCC_CR_HSIRDY                          RCC_CR_HSIRDY_Msk               /*!< Internal High Speed clock ready flag */

+#define RCC_CR_HSIDIV_Pos                      (3U)

+#define RCC_CR_HSIDIV_Msk                      (0x3UL << RCC_CR_HSIDIV_Pos)    /*!< 0x00000018 */

+#define RCC_CR_HSIDIV                          RCC_CR_HSIDIV_Msk               /*!< Internal High Speed clock divider selection */

+#define RCC_CR_HSIDIV_1                        (0x0UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000000 */

+#define RCC_CR_HSIDIV_2                        (0x1UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000008 */

+#define RCC_CR_HSIDIV_4                        (0x2UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000010 */

+#define RCC_CR_HSIDIV_8                        (0x3UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000018 */

+

+#define RCC_CR_HSIDIVF_Pos                     (5U)

+#define RCC_CR_HSIDIVF_Msk                     (0x1UL << RCC_CR_HSIDIVF_Pos)   /*!< 0x00000020 */

+#define RCC_CR_HSIDIVF                         RCC_CR_HSIDIVF_Msk              /*!< HSI Divider flag */

+#define RCC_CR_CSION_Pos                       (7U)

+#define RCC_CR_CSION_Msk                       (0x1UL << RCC_CR_CSION_Pos)     /*!< 0x00000080 */

+#define RCC_CR_CSION                           RCC_CR_CSION_Msk                /*!< The Internal RC 4MHz oscillator clock enable */

+#define RCC_CR_CSIRDY_Pos                      (8U)

+#define RCC_CR_CSIRDY_Msk                      (0x1UL << RCC_CR_CSIRDY_Pos)    /*!< 0x00000100 */

+#define RCC_CR_CSIRDY                          RCC_CR_CSIRDY_Msk               /*!< The Internal RC 4MHz oscillator clock ready */

+#define RCC_CR_CSIKERON_Pos                    (9U)

+#define RCC_CR_CSIKERON_Msk                    (0x1UL << RCC_CR_CSIKERON_Pos)  /*!< 0x00000200 */

+#define RCC_CR_CSIKERON                        RCC_CR_CSIKERON_Msk             /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */

+#define RCC_CR_HSI48ON_Pos                     (12U)

+#define RCC_CR_HSI48ON_Msk                     (0x1UL << RCC_CR_HSI48ON_Pos)   /*!< 0x00001000 */

+#define RCC_CR_HSI48ON                         RCC_CR_HSI48ON_Msk              /*!< HSI48 clock enable clock enable  */

+#define RCC_CR_HSI48RDY_Pos                    (13U)

+#define RCC_CR_HSI48RDY_Msk                    (0x1UL << RCC_CR_HSI48RDY_Pos)  /*!< 0x00002000 */

+#define RCC_CR_HSI48RDY                        RCC_CR_HSI48RDY_Msk             /*!< HSI48 clock ready */

+

+#define RCC_CR_CPUCKRDY_Pos                     (14U)

+#define RCC_CR_CPUCKRDY_Msk                     (0x1UL << RCC_CR_CPUCKRDY_Pos)   /*!< 0x00004000 */

+#define RCC_CR_CPUCKRDY                         RCC_CR_CPUCKRDY_Msk              /*!< CPU domain clocks ready flag  */

+#define RCC_CR_CDCKRDY_Pos                     (15U)

+#define RCC_CR_CDCKRDY_Msk                     (0x1UL << RCC_CR_CDCKRDY_Pos)   /*!< 0x00008000 */

+#define RCC_CR_CDCKRDY                         RCC_CR_CDCKRDY_Msk              /*!< CD domain clocks ready flag */

+

+#define RCC_CR_HSEON_Pos                       (16U)

+#define RCC_CR_HSEON_Msk                       (0x1UL << RCC_CR_HSEON_Pos)     /*!< 0x00010000 */

+#define RCC_CR_HSEON                           RCC_CR_HSEON_Msk                /*!< External High Speed clock enable */

+#define RCC_CR_HSERDY_Pos                      (17U)

+#define RCC_CR_HSERDY_Msk                      (0x1UL << RCC_CR_HSERDY_Pos)    /*!< 0x00020000 */

+#define RCC_CR_HSERDY                          RCC_CR_HSERDY_Msk               /*!< External High Speed clock ready */

+#define RCC_CR_HSEBYP_Pos                      (18U)

+#define RCC_CR_HSEBYP_Msk                      (0x1UL << RCC_CR_HSEBYP_Pos)    /*!< 0x00040000 */

+#define RCC_CR_HSEBYP                          RCC_CR_HSEBYP_Msk               /*!< External High Speed clock Bypass */

+#define RCC_CR_CSSHSEON_Pos                    (19U)

+#define RCC_CR_CSSHSEON_Msk                    (0x1UL << RCC_CR_CSSHSEON_Pos)  /*!< 0x00080000 */

+#define RCC_CR_CSSHSEON                        RCC_CR_CSSHSEON_Msk             /*!< HSE Clock security System enable */

+

+#define RCC_CR_HSEEXT_Pos                    (20U)

+#define RCC_CR_HSEEXT_Msk                    (0x1UL << RCC_CR_HSEEXT_Pos)  /*!< 0x00080000 */

+#define RCC_CR_HSEEXT                        RCC_CR_HSEEXT_Msk             /*!< HSE Clock security System enable */

+

+#define RCC_CR_PLL1ON_Pos                      (24U)

+#define RCC_CR_PLL1ON_Msk                      (0x1UL << RCC_CR_PLL1ON_Pos)    /*!< 0x01000000 */

+#define RCC_CR_PLL1ON                          RCC_CR_PLL1ON_Msk               /*!< System PLL1 clock enable */

+#define RCC_CR_PLL1RDY_Pos                     (25U)

+#define RCC_CR_PLL1RDY_Msk                     (0x1UL << RCC_CR_PLL1RDY_Pos)   /*!< 0x02000000 */

+#define RCC_CR_PLL1RDY                         RCC_CR_PLL1RDY_Msk              /*!< System PLL1 clock ready */

+#define RCC_CR_PLL2ON_Pos                      (26U)

+#define RCC_CR_PLL2ON_Msk                      (0x1UL << RCC_CR_PLL2ON_Pos)    /*!< 0x04000000 */

+#define RCC_CR_PLL2ON                          RCC_CR_PLL2ON_Msk               /*!< System PLL2 clock enable */

+#define RCC_CR_PLL2RDY_Pos                     (27U)

+#define RCC_CR_PLL2RDY_Msk                     (0x1UL << RCC_CR_PLL2RDY_Pos)   /*!< 0x08000000 */

+#define RCC_CR_PLL2RDY                         RCC_CR_PLL2RDY_Msk              /*!< System PLL2 clock ready */

+#define RCC_CR_PLL3ON_Pos                      (28U)

+#define RCC_CR_PLL3ON_Msk                      (0x1UL << RCC_CR_PLL3ON_Pos)    /*!< 0x10000000 */

+#define RCC_CR_PLL3ON                          RCC_CR_PLL3ON_Msk               /*!< System PLL3 clock enable */

+#define RCC_CR_PLL3RDY_Pos                     (29U)

+#define RCC_CR_PLL3RDY_Msk                     (0x1UL << RCC_CR_PLL3RDY_Pos)   /*!< 0x20000000 */

+#define RCC_CR_PLL3RDY                         RCC_CR_PLL3RDY_Msk              /*!< System PLL3 clock ready */

+

+/*Legacy */

+#define RCC_CR_PLLON_Pos                       (24U)

+#define RCC_CR_PLLON_Msk                       (0x1UL << RCC_CR_PLLON_Pos)     /*!< 0x01000000 */

+#define RCC_CR_PLLON                           RCC_CR_PLLON_Msk                /*!< System PLL clock enable */

+#define RCC_CR_PLLRDY_Pos                      (25U)

+#define RCC_CR_PLLRDY_Msk                      (0x1UL << RCC_CR_PLLRDY_Pos)    /*!< 0x02000000 */

+#define RCC_CR_PLLRDY                          RCC_CR_PLLRDY_Msk               /*!< System PLL clock ready */

+

+/********************  Bit definition for RCC_HSICFGR register  ***************/

+/*!< HSICAL configuration */

+#define RCC_HSICFGR_HSICAL_Pos                 (0U)

+#define RCC_HSICFGR_HSICAL_Msk                 (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */

+#define RCC_HSICFGR_HSICAL                     RCC_HSICFGR_HSICAL_Msk          /*!< HSICAL[11:0] bits */

+#define RCC_HSICFGR_HSICAL_0                   (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */

+#define RCC_HSICFGR_HSICAL_1                   (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */

+#define RCC_HSICFGR_HSICAL_2                   (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */

+#define RCC_HSICFGR_HSICAL_3                   (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */

+#define RCC_HSICFGR_HSICAL_4                   (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */

+#define RCC_HSICFGR_HSICAL_5                   (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */

+#define RCC_HSICFGR_HSICAL_6                   (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */

+#define RCC_HSICFGR_HSICAL_7                   (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */

+#define RCC_HSICFGR_HSICAL_8                   (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */

+#define RCC_HSICFGR_HSICAL_9                   (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */

+#define RCC_HSICFGR_HSICAL_10                  (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */

+#define RCC_HSICFGR_HSICAL_11                  (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */

+

+/*!< HSITRIM configuration */

+#define RCC_HSICFGR_HSITRIM_Pos                (24U)

+#define RCC_HSICFGR_HSITRIM_Msk                (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */

+#define RCC_HSICFGR_HSITRIM                    RCC_HSICFGR_HSITRIM_Msk         /*!< HSITRIM[6:0] bits */

+#define RCC_HSICFGR_HSITRIM_0                  (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */

+#define RCC_HSICFGR_HSITRIM_1                  (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */

+#define RCC_HSICFGR_HSITRIM_2                  (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */

+#define RCC_HSICFGR_HSITRIM_3                  (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */

+#define RCC_HSICFGR_HSITRIM_4                  (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */

+#define RCC_HSICFGR_HSITRIM_5                  (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */

+#define RCC_HSICFGR_HSITRIM_6                  (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */

+

+

+/********************  Bit definition for RCC_CRRCR register  *****************/

+

+/*!< HSI48CAL configuration */

+#define RCC_CRRCR_HSI48CAL_Pos                 (0U)

+#define RCC_CRRCR_HSI48CAL_Msk                 (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */

+#define RCC_CRRCR_HSI48CAL                     RCC_CRRCR_HSI48CAL_Msk          /*!< HSI48CAL[9:0] bits */

+#define RCC_CRRCR_HSI48CAL_0                   (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */

+#define RCC_CRRCR_HSI48CAL_1                   (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */

+#define RCC_CRRCR_HSI48CAL_2                   (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */

+#define RCC_CRRCR_HSI48CAL_3                   (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */

+#define RCC_CRRCR_HSI48CAL_4                   (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */

+#define RCC_CRRCR_HSI48CAL_5                   (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */

+#define RCC_CRRCR_HSI48CAL_6                   (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */

+#define RCC_CRRCR_HSI48CAL_7                   (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */

+#define RCC_CRRCR_HSI48CAL_8                   (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */

+#define RCC_CRRCR_HSI48CAL_9                   (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */

+

+

+/********************  Bit definition for RCC_CSICFGR register  *****************/

+/*!< CSICAL configuration */

+#define RCC_CSICFGR_CSICAL_Pos                 (0U)

+#define RCC_CSICFGR_CSICAL_Msk                 (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */

+#define RCC_CSICFGR_CSICAL                     RCC_CSICFGR_CSICAL_Msk          /*!< CSICAL[7:0] bits */

+#define RCC_CSICFGR_CSICAL_0                   (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */

+#define RCC_CSICFGR_CSICAL_1                   (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */

+#define RCC_CSICFGR_CSICAL_2                   (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */

+#define RCC_CSICFGR_CSICAL_3                   (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */

+#define RCC_CSICFGR_CSICAL_4                   (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */

+#define RCC_CSICFGR_CSICAL_5                   (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */

+#define RCC_CSICFGR_CSICAL_6                   (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */

+#define RCC_CSICFGR_CSICAL_7                   (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */

+

+/*!< CSITRIM configuration */

+#define RCC_CSICFGR_CSITRIM_Pos                (24U)

+#define RCC_CSICFGR_CSITRIM_Msk                (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */

+#define RCC_CSICFGR_CSITRIM                    RCC_CSICFGR_CSITRIM_Msk         /*!< CSITRIM[5:0] bits */

+#define RCC_CSICFGR_CSITRIM_0                  (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */

+#define RCC_CSICFGR_CSITRIM_1                  (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */

+#define RCC_CSICFGR_CSITRIM_2                  (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */

+#define RCC_CSICFGR_CSITRIM_3                  (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */

+#define RCC_CSICFGR_CSITRIM_4                  (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */

+#define RCC_CSICFGR_CSITRIM_5                  (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */

+

+/********************  Bit definition for RCC_CFGR register  ******************/

+/*!< SW configuration */

+#define RCC_CFGR_SW_Pos                        (0U)

+#define RCC_CFGR_SW_Msk                        (0x7UL << RCC_CFGR_SW_Pos)           /*!< 0x00000007 */

+#define RCC_CFGR_SW                            RCC_CFGR_SW_Msk                     /*!< SW[2:0] bits (System clock Switch) */

+#define RCC_CFGR_SW_0                          (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */

+#define RCC_CFGR_SW_1                          (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */

+#define RCC_CFGR_SW_2                          (0x4UL << RCC_CFGR_SW_Pos)           /*!< 0x00000004 */

+

+#define RCC_CFGR_SW_HSI                        (0x00000000UL)                       /*!< HSI selection as system clock */

+#define RCC_CFGR_SW_CSI                        (0x00000001UL)                       /*!< CSI selection as system clock */

+#define RCC_CFGR_SW_HSE                        (0x00000002UL)                       /*!< HSE selection as system clock */

+#define RCC_CFGR_SW_PLL1                       (0x00000003UL)                       /*!< PLL1 selection as system clock */

+

+/*!< SWS configuration */

+#define RCC_CFGR_SWS_Pos                       (3U)

+#define RCC_CFGR_SWS_Msk                       (0x7UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000038 */

+#define RCC_CFGR_SWS                           RCC_CFGR_SWS_Msk                    /*!< SWS[2:0] bits (System Clock Switch Status) */

+#define RCC_CFGR_SWS_0                         (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */

+#define RCC_CFGR_SWS_1                         (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000010 */

+#define RCC_CFGR_SWS_2                         (0x4UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000020 */

+

+#define RCC_CFGR_SWS_HSI                       (0x00000000UL)                       /*!< HSI used as system clock */

+#define RCC_CFGR_SWS_CSI                       (0x00000008UL)                       /*!< CSI used as system clock */

+#define RCC_CFGR_SWS_HSE                       (0x00000010UL)                       /*!< HSE used as system clock */

+#define RCC_CFGR_SWS_PLL1                      (0x00000018UL)                       /*!< PLL1 used as system clock */

+

+#define RCC_CFGR_STOPWUCK_Pos                  (6U)

+#define RCC_CFGR_STOPWUCK_Msk                  (0x1UL << RCC_CFGR_STOPWUCK_Pos)     /*!< 0x00000040 */

+#define RCC_CFGR_STOPWUCK                      RCC_CFGR_STOPWUCK_Msk                /*!< Wake Up from stop and CSS backup clock selection */

+

+#define RCC_CFGR_STOPKERWUCK_Pos               (7U)

+#define RCC_CFGR_STOPKERWUCK_Msk               (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)  /*!< 0x00000080 */

+#define RCC_CFGR_STOPKERWUCK                   RCC_CFGR_STOPKERWUCK_Msk             /*!< Kernel Clock Selection after a Wake Up from STOP */

+

+/*!< RTCPRE configuration */

+#define RCC_CFGR_RTCPRE_Pos                    (8U)

+#define RCC_CFGR_RTCPRE_Msk                    (0x3FUL << RCC_CFGR_RTCPRE_Pos)

+#define RCC_CFGR_RTCPRE                        RCC_CFGR_RTCPRE_Msk                  /*!< 0x00003F00 */

+#define RCC_CFGR_RTCPRE_0                      (0x1UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000100 */

+#define RCC_CFGR_RTCPRE_1                      (0x2UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000200 */

+#define RCC_CFGR_RTCPRE_2                      (0x4UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000400 */

+#define RCC_CFGR_RTCPRE_3                      (0x8UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000800 */

+#define RCC_CFGR_RTCPRE_4                      (0x10UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00001000 */

+#define RCC_CFGR_RTCPRE_5                      (0x20UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00002000 */

+

+

+/*!< TIMPRE configuration */

+#define RCC_CFGR_TIMPRE_Pos                    (15U)

+#define RCC_CFGR_TIMPRE_Msk                    (0x1UL << RCC_CFGR_TIMPRE_Pos)

+#define RCC_CFGR_TIMPRE                        RCC_CFGR_TIMPRE_Msk                  /*!< 0x00008000 */

+

+/*!< MCO1 configuration */

+#define RCC_CFGR_MCO1_Pos                      (22U)

+#define RCC_CFGR_MCO1_Msk                      (0x7UL << RCC_CFGR_MCO1_Pos)

+#define RCC_CFGR_MCO1                          RCC_CFGR_MCO1_Msk                       /*!< 0x01C00000 */

+#define RCC_CFGR_MCO1_0                        (0x1UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00400000 */

+#define RCC_CFGR_MCO1_1                        (0x2UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00800000 */

+#define RCC_CFGR_MCO1_2                        (0x4UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x01000000 */

+

+#define RCC_CFGR_MCO1PRE_Pos                   (18U)

+#define RCC_CFGR_MCO1PRE_Msk                   (0xFUL << RCC_CFGR_MCO1PRE_Pos)

+#define RCC_CFGR_MCO1PRE                       RCC_CFGR_MCO1PRE_Msk                    /*!< 0x003C0000 */

+#define RCC_CFGR_MCO1PRE_0                     (0x1UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00040000 */

+#define RCC_CFGR_MCO1PRE_1                     (0x2UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00080000 */

+#define RCC_CFGR_MCO1PRE_2                     (0x4UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00100000 */

+#define RCC_CFGR_MCO1PRE_3                     (0x8UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00200000 */

+

+#define RCC_CFGR_MCO2PRE_Pos                   (25U)

+#define RCC_CFGR_MCO2PRE_Msk                   (0xFUL << RCC_CFGR_MCO2PRE_Pos)

+#define RCC_CFGR_MCO2PRE                       RCC_CFGR_MCO2PRE_Msk                    /*!< 0x1E000000 */

+#define RCC_CFGR_MCO2PRE_0                     (0x1UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x02000000 */

+#define RCC_CFGR_MCO2PRE_1                     (0x2UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x04000000 */

+#define RCC_CFGR_MCO2PRE_2                     (0x4UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x08000000 */

+#define RCC_CFGR_MCO2PRE_3                     (0x8UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x10000000 */

+

+#define RCC_CFGR_MCO2_Pos                      (29U)

+#define RCC_CFGR_MCO2_Msk                      (0x7UL << RCC_CFGR_MCO2_Pos)

+#define RCC_CFGR_MCO2                          RCC_CFGR_MCO2_Msk                       /*!< 0xE0000000 */

+#define RCC_CFGR_MCO2_0                        (0x1UL << RCC_CFGR_MCO2_Pos)             /*!< 0x20000000 */

+#define RCC_CFGR_MCO2_1                        (0x2UL << RCC_CFGR_MCO2_Pos)             /*!< 0x40000000 */

+#define RCC_CFGR_MCO2_2                        (0x4UL << RCC_CFGR_MCO2_Pos)             /*!< 0x80000000 */

+

+/********************  Bit definition for RCC_D1CFGR register  ******************/

+/*!< D1HPRE configuration */

+#define RCC_CDCFGR1_HPRE_Pos                    (0U)

+#define RCC_CDCFGR1_HPRE_Msk                    (0xFUL << RCC_CDCFGR1_HPRE_Pos)  /*!< 0x0000000F */

+#define RCC_CDCFGR1_HPRE                        RCC_CDCFGR1_HPRE_Msk             /*!< HPRE[3:0] bits (AHB3 prescaler) */

+#define RCC_CDCFGR1_HPRE_0                      (0x1UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000001 */

+#define RCC_CDCFGR1_HPRE_1                      (0x2UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000002 */

+#define RCC_CDCFGR1_HPRE_2                      (0x4UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000004 */

+#define RCC_CDCFGR1_HPRE_3                      (0x8UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000008 */

+

+#define RCC_CDCFGR1_HPRE_DIV1                   ((uint32_t)0x00000000)                 /*!< AHB3 Clock not divided */

+#define RCC_CDCFGR1_HPRE_DIV2_Pos               (3U)

+#define RCC_CDCFGR1_HPRE_DIV2_Msk               (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos)   /*!< 0x00000008 */

+#define RCC_CDCFGR1_HPRE_DIV2                   RCC_CDCFGR1_HPRE_DIV2_Msk              /*!< AHB3 Clock divided by 2 */

+#define RCC_CDCFGR1_HPRE_DIV4_Pos               (0U)

+#define RCC_CDCFGR1_HPRE_DIV4_Msk               (0x9UL << RCC_CDCFGR1_HPRE_DIV4_Pos)   /*!< 0x00000009 */

+#define RCC_CDCFGR1_HPRE_DIV4                   RCC_CDCFGR1_HPRE_DIV4_Msk              /*!< AHB3 Clock divided by 4 */

+#define RCC_CDCFGR1_HPRE_DIV8_Pos               (1U)

+#define RCC_CDCFGR1_HPRE_DIV8_Msk               (0x5UL << RCC_CDCFGR1_HPRE_DIV8_Pos)   /*!< 0x0000000A */

+#define RCC_CDCFGR1_HPRE_DIV8                   RCC_CDCFGR1_HPRE_DIV8_Msk              /*!< AHB3 Clock divided by 8 */

+#define RCC_CDCFGR1_HPRE_DIV16_Pos              (0U)

+#define RCC_CDCFGR1_HPRE_DIV16_Msk              (0xBUL << RCC_CDCFGR1_HPRE_DIV16_Pos)  /*!< 0x0000000B */

+#define RCC_CDCFGR1_HPRE_DIV16                  RCC_CDCFGR1_HPRE_DIV16_Msk             /*!< AHB3 Clock divided by 16 */

+#define RCC_CDCFGR1_HPRE_DIV64_Pos              (2U)

+#define RCC_CDCFGR1_HPRE_DIV64_Msk              (0x3UL << RCC_CDCFGR1_HPRE_DIV64_Pos)  /*!< 0x0000000C */

+#define RCC_CDCFGR1_HPRE_DIV64                  RCC_CDCFGR1_HPRE_DIV64_Msk             /*!< AHB3 Clock divided by 64 */

+#define RCC_CDCFGR1_HPRE_DIV128_Pos             (0U)

+#define RCC_CDCFGR1_HPRE_DIV128_Msk             (0xDUL << RCC_CDCFGR1_HPRE_DIV128_Pos) /*!< 0x0000000D */

+#define RCC_CDCFGR1_HPRE_DIV128                 RCC_CDCFGR1_HPRE_DIV128_Msk            /*!< AHB3 Clock divided by 128 */

+#define RCC_CDCFGR1_HPRE_DIV256_Pos             (1U)

+#define RCC_CDCFGR1_HPRE_DIV256_Msk             (0x7UL << RCC_CDCFGR1_HPRE_DIV256_Pos) /*!< 0x0000000E */

+#define RCC_CDCFGR1_HPRE_DIV256                 RCC_CDCFGR1_HPRE_DIV256_Msk            /*!< AHB3 Clock divided by 256 */

+#define RCC_CDCFGR1_HPRE_DIV512_Pos             (0U)

+#define RCC_CDCFGR1_HPRE_DIV512_Msk             (0xFUL << RCC_CDCFGR1_HPRE_DIV512_Pos) /*!< 0x0000000F */

+#define RCC_CDCFGR1_HPRE_DIV512                 RCC_CDCFGR1_HPRE_DIV512_Msk            /*!< AHB3 Clock divided by 512 */

+

+/*!< D1PPRE configuration */

+#define RCC_CDCFGR1_CDPPRE_Pos                  (4U)

+#define RCC_CDCFGR1_CDPPRE_Msk                  (0x7UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000070 */

+#define RCC_CDCFGR1_CDPPRE                      RCC_CDCFGR1_CDPPRE_Msk                 /*!< CDPRE[2:0] bits (APB3 prescaler) */

+#define RCC_CDCFGR1_CDPPRE_0                    (0x1UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000010 */

+#define RCC_CDCFGR1_CDPPRE_1                    (0x2UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000020 */

+#define RCC_CDCFGR1_CDPPRE_2                    (0x4UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000040 */

+

+#define RCC_CDCFGR1_CDPPRE_DIV1                 ((uint32_t)0x00000000)                 /*!< APB3 clock not divided */

+#define RCC_CDCFGR1_CDPPRE_DIV2_Pos             (6U)

+#define RCC_CDCFGR1_CDPPRE_DIV2_Msk             (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_CDCFGR1_CDPPRE_DIV2                 RCC_CDCFGR1_CDPPRE_DIV2_Msk            /*!< APB3 clock divided by 2 */

+#define RCC_CDCFGR1_CDPPRE_DIV4_Pos             (4U)

+#define RCC_CDCFGR1_CDPPRE_DIV4_Msk             (0x5UL << RCC_CDCFGR1_CDPPRE_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_CDCFGR1_CDPPRE_DIV4                 RCC_CDCFGR1_CDPPRE_DIV4_Msk            /*!< APB3 clock divided by 4 */

+#define RCC_CDCFGR1_CDPPRE_DIV8_Pos             (5U)

+#define RCC_CDCFGR1_CDPPRE_DIV8_Msk             (0x3UL << RCC_CDCFGR1_CDPPRE_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_CDCFGR1_CDPPRE_DIV8                 RCC_CDCFGR1_CDPPRE_DIV8_Msk            /*!< APB3 clock divided by 8 */

+#define RCC_CDCFGR1_CDPPRE_DIV16_Pos            (4U)

+#define RCC_CDCFGR1_CDPPRE_DIV16_Msk            (0x7UL << RCC_CDCFGR1_CDPPRE_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_CDCFGR1_CDPPRE_DIV16                RCC_CDCFGR1_CDPPRE_DIV16_Msk            /*!< APB3 clock divided by 16 */

+

+#define RCC_CDCFGR1_CDCPRE_Pos                  (8U)

+#define RCC_CDCFGR1_CDCPRE_Msk                  (0xFUL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000F00 */

+#define RCC_CDCFGR1_CDCPRE                      RCC_CDCFGR1_CDCPRE_Msk                  /*!< CDCPRE[2:0] bits (Domain 1 Core prescaler) */

+#define RCC_CDCFGR1_CDCPRE_0                    (0x1UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000100 */

+#define RCC_CDCFGR1_CDCPRE_1                    (0x2UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000200 */

+#define RCC_CDCFGR1_CDCPRE_2                    (0x4UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000400 */

+#define RCC_CDCFGR1_CDCPRE_3                    (0x8UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000800 */

+

+#define RCC_CDCFGR1_CDCPRE_DIV1                 ((uint32_t)0x00000000)                  /*!< Domain 1 Core clock not divided */

+#define RCC_CDCFGR1_CDCPRE_DIV2_Pos             (11U)

+#define RCC_CDCFGR1_CDCPRE_DIV2_Msk             (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos)  /*!< 0x00000800 */

+#define RCC_CDCFGR1_CDCPRE_DIV2                 RCC_CDCFGR1_CDCPRE_DIV2_Msk             /*!< Domain 1 Core clock divided by 2 */

+#define RCC_CDCFGR1_CDCPRE_DIV4_Pos             (8U)

+#define RCC_CDCFGR1_CDCPRE_DIV4_Msk             (0x9UL << RCC_CDCFGR1_CDCPRE_DIV4_Pos)  /*!< 0x00000900 */

+#define RCC_CDCFGR1_CDCPRE_DIV4                 RCC_CDCFGR1_CDCPRE_DIV4_Msk             /*!< Domain 1 Core clock divided by 4 */

+#define RCC_CDCFGR1_CDCPRE_DIV8_Pos             (9U)

+#define RCC_CDCFGR1_CDCPRE_DIV8_Msk             (0x5UL << RCC_CDCFGR1_CDCPRE_DIV8_Pos)  /*!< 0x00000A00 */

+#define RCC_CDCFGR1_CDCPRE_DIV8                 RCC_CDCFGR1_CDCPRE_DIV8_Msk             /*!< Domain 1 Core clock divided by 8 */

+#define RCC_CDCFGR1_CDCPRE_DIV16_Pos            (8U)

+#define RCC_CDCFGR1_CDCPRE_DIV16_Msk            (0xBUL << RCC_CDCFGR1_CDCPRE_DIV16_Pos) /*!< 0x00000B00 */

+#define RCC_CDCFGR1_CDCPRE_DIV16                RCC_CDCFGR1_CDCPRE_DIV16_Msk            /*!< Domain 1 Core clock divided by 16 */

+#define RCC_CDCFGR1_CDCPRE_DIV64_Pos            (10U)

+#define RCC_CDCFGR1_CDCPRE_DIV64_Msk            (0x3UL << RCC_CDCFGR1_CDCPRE_DIV64_Pos) /*!< 0x00000C00 */

+#define RCC_CDCFGR1_CDCPRE_DIV64                RCC_CDCFGR1_CDCPRE_DIV64_Msk            /*!< Domain 1 Core clock divided by 64 */

+#define RCC_CDCFGR1_CDCPRE_DIV128_Pos           (8U)

+#define RCC_CDCFGR1_CDCPRE_DIV128_Msk           (0xDUL << RCC_CDCFGR1_CDCPRE_DIV128_Pos)/*!< 0x00000D00 */

+#define RCC_CDCFGR1_CDCPRE_DIV128               RCC_CDCFGR1_CDCPRE_DIV128_Msk           /*!< Domain 1 Core clock divided by 128 */

+#define RCC_CDCFGR1_CDCPRE_DIV256_Pos           (9U)

+#define RCC_CDCFGR1_CDCPRE_DIV256_Msk           (0x7UL << RCC_CDCFGR1_CDCPRE_DIV256_Pos)/*!< 0x00000E00 */

+#define RCC_CDCFGR1_CDCPRE_DIV256               RCC_CDCFGR1_CDCPRE_DIV256_Msk           /*!< Domain 1 Core clock divided by 256 */

+#define RCC_CDCFGR1_CDCPRE_DIV512_Pos           (8U)

+#define RCC_CDCFGR1_CDCPRE_DIV512_Msk           (0xFUL << RCC_CDCFGR1_CDCPRE_DIV512_Pos)/*!< 0x00000F00 */

+#define RCC_CDCFGR1_CDCPRE_DIV512               RCC_CDCFGR1_CDCPRE_DIV512_Msk           /*!< Domain 1 Core clock divided by 512 */

+

+/********************  Bit definition for RCC_CDCFGR2 register  ******************/

+/*!< CDPPRE1 configuration */

+#define RCC_CDCFGR2_CDPPRE1_Pos                 (4U)

+#define RCC_CDCFGR2_CDPPRE1_Msk                 (0x7UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000070 */

+#define RCC_CDCFGR2_CDPPRE1                     RCC_CDCFGR2_CDPPRE1_Msk          /*!< D1PPRE1[2:0] bits (APB1 prescaler) */

+#define RCC_CDCFGR2_CDPPRE1_0                   (0x1UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000010 */

+#define RCC_CDCFGR2_CDPPRE1_1                   (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */

+#define RCC_CDCFGR2_CDPPRE1_2                   (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */

+

+#define RCC_CDCFGR2_CDPPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */

+#define RCC_CDCFGR2_CDPPRE1_DIV2_Pos            (6U)

+#define RCC_CDCFGR2_CDPPRE1_DIV2_Msk            (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_CDCFGR2_CDPPRE1_DIV2                RCC_CDCFGR2_CDPPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */

+#define RCC_CDCFGR2_CDPPRE1_DIV4_Pos            (4U)

+#define RCC_CDCFGR2_CDPPRE1_DIV4_Msk            (0x5UL << RCC_CDCFGR2_CDPPRE1_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_CDCFGR2_CDPPRE1_DIV4                RCC_CDCFGR2_CDPPRE1_DIV4_Msk     /*!< APB1 clock divided by 4 */

+#define RCC_CDCFGR2_CDPPRE1_DIV8_Pos            (5U)

+#define RCC_CDCFGR2_CDPPRE1_DIV8_Msk            (0x3UL << RCC_CDCFGR2_CDPPRE1_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_CDCFGR2_CDPPRE1_DIV8                RCC_CDCFGR2_CDPPRE1_DIV8_Msk     /*!< APB1 clock divided by 8 */

+#define RCC_CDCFGR2_CDPPRE1_DIV16_Pos           (4U)

+#define RCC_CDCFGR2_CDPPRE1_DIV16_Msk           (0x7UL << RCC_CDCFGR2_CDPPRE1_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_CDCFGR2_CDPPRE1_DIV16               RCC_CDCFGR2_CDPPRE1_DIV16_Msk    /*!< APB1 clock divided by 16 */

+

+/*!< CDPPRE2 configuration */

+#define RCC_CDCFGR2_CDPPRE2_Pos                 (8U)

+#define RCC_CDCFGR2_CDPPRE2_Msk                 (0x7UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000700 */

+#define RCC_CDCFGR2_CDPPRE2                     RCC_CDCFGR2_CDPPRE2_Msk          /*!< CDPPRE2[2:0] bits (APB2 prescaler) */

+#define RCC_CDCFGR2_CDPPRE2_0                   (0x1UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000100 */

+#define RCC_CDCFGR2_CDPPRE2_1                   (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */

+#define RCC_CDCFGR2_CDPPRE2_2                   (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */

+

+#define RCC_CDCFGR2_CDPPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */

+#define RCC_CDCFGR2_CDPPRE2_DIV2_Pos            (10U)

+#define RCC_CDCFGR2_CDPPRE2_DIV2_Msk            (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */

+#define RCC_CDCFGR2_CDPPRE2_DIV2                RCC_CDCFGR2_CDPPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */

+#define RCC_CDCFGR2_CDPPRE2_DIV4_Pos            (8U)

+#define RCC_CDCFGR2_CDPPRE2_DIV4_Msk            (0x5UL << RCC_CDCFGR2_CDPPRE2_DIV4_Pos) /*!< 0x00000500 */

+#define RCC_CDCFGR2_CDPPRE2_DIV4                RCC_CDCFGR2_CDPPRE2_DIV4_Msk     /*!< APB2 clock divided by 4 */

+#define RCC_CDCFGR2_CDPPRE2_DIV8_Pos            (9U)

+#define RCC_CDCFGR2_CDPPRE2_DIV8_Msk            (0x3UL << RCC_CDCFGR2_CDPPRE2_DIV8_Pos) /*!< 0x00000600 */

+#define RCC_CDCFGR2_CDPPRE2_DIV8                RCC_CDCFGR2_CDPPRE2_DIV8_Msk     /*!< APB2 clock divided by 8 */

+#define RCC_CDCFGR2_CDPPRE2_DIV16_Pos           (8U)

+#define RCC_CDCFGR2_CDPPRE2_DIV16_Msk           (0x7UL << RCC_CDCFGR2_CDPPRE2_DIV16_Pos) /*!< 0x00000700 */

+#define RCC_CDCFGR2_CDPPRE2_DIV16               RCC_CDCFGR2_CDPPRE2_DIV16_Msk    /*!< APB2 clock divided by 16 */

+

+/********************  Bit definition for RCC_SRDCFGR register  ******************/

+/*!< SRDPPRE configuration */

+#define RCC_SRDCFGR_SRDPPRE_Pos                  (4U)

+#define RCC_SRDCFGR_SRDPPRE_Msk                  (0x7UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000070 */

+#define RCC_SRDCFGR_SRDPPRE                      RCC_SRDCFGR_SRDPPRE_Msk           /*!< SRDPPRE1[2:0] bits (APB4 prescaler) */

+#define RCC_SRDCFGR_SRDPPRE_0                    (0x1UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000010 */

+#define RCC_SRDCFGR_SRDPPRE_1                    (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */

+#define RCC_SRDCFGR_SRDPPRE_2                    (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */

+

+#define RCC_SRDCFGR_SRDPPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */

+#define RCC_SRDCFGR_SRDPPRE_DIV2_Pos             (6U)

+#define RCC_SRDCFGR_SRDPPRE_DIV2_Msk             (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_SRDCFGR_SRDPPRE_DIV2                 RCC_SRDCFGR_SRDPPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */

+#define RCC_SRDCFGR_SRDPPRE_DIV4_Pos             (4U)

+#define RCC_SRDCFGR_SRDPPRE_DIV4_Msk             (0x5UL << RCC_SRDCFGR_SRDPPRE_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_SRDCFGR_SRDPPRE_DIV4                 RCC_SRDCFGR_SRDPPRE_DIV4_Msk      /*!< APB4 clock divided by 4 */

+#define RCC_SRDCFGR_SRDPPRE_DIV8_Pos             (5U)

+#define RCC_SRDCFGR_SRDPPRE_DIV8_Msk             (0x3UL << RCC_SRDCFGR_SRDPPRE_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_SRDCFGR_SRDPPRE_DIV8                 RCC_SRDCFGR_SRDPPRE_DIV8_Msk      /*!< APB4 clock divided by 8 */

+#define RCC_SRDCFGR_SRDPPRE_DIV16_Pos            (4U)

+#define RCC_SRDCFGR_SRDPPRE_DIV16_Msk            (0x7UL << RCC_SRDCFGR_SRDPPRE_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_SRDCFGR_SRDPPRE_DIV16                RCC_SRDCFGR_SRDPPRE_DIV16_Msk     /*!< APB4 clock divided by 16 */

+

+/********************  Bit definition for RCC_PLLCKSELR register  *************/

+

+#define RCC_PLLCKSELR_PLLSRC_Pos               (0U)

+#define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */

+#define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk

+

+#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)

+#define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */

+#define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_HSE_Pos           (1U)

+#define RCC_PLLCKSELR_PLLSRC_HSE_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */

+#define RCC_PLLCKSELR_PLLSRC_HSE               RCC_PLLCKSELR_PLLSRC_HSE_Msk    /*!< HSE source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_NONE_Pos          (0U)

+#define RCC_PLLCKSELR_PLLSRC_NONE_Msk          (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */

+#define RCC_PLLCKSELR_PLLSRC_NONE              RCC_PLLCKSELR_PLLSRC_NONE_Msk   /*!< No source clock selected  */

+

+#define RCC_PLLCKSELR_DIVM1_Pos                (4U)

+#define RCC_PLLCKSELR_DIVM1_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */

+#define RCC_PLLCKSELR_DIVM1                    RCC_PLLCKSELR_DIVM1_Msk

+#define RCC_PLLCKSELR_DIVM1_0                  (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */

+#define RCC_PLLCKSELR_DIVM1_1                  (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */

+#define RCC_PLLCKSELR_DIVM1_2                  (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */

+#define RCC_PLLCKSELR_DIVM1_3                  (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */

+#define RCC_PLLCKSELR_DIVM1_4                  (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */

+#define RCC_PLLCKSELR_DIVM1_5                  (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */

+

+#define RCC_PLLCKSELR_DIVM2_Pos                (12U)

+#define RCC_PLLCKSELR_DIVM2_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */

+#define RCC_PLLCKSELR_DIVM2                    RCC_PLLCKSELR_DIVM2_Msk

+#define RCC_PLLCKSELR_DIVM2_0                  (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */

+#define RCC_PLLCKSELR_DIVM2_1                  (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */

+#define RCC_PLLCKSELR_DIVM2_2                  (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */

+#define RCC_PLLCKSELR_DIVM2_3                  (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */

+#define RCC_PLLCKSELR_DIVM2_4                  (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */

+#define RCC_PLLCKSELR_DIVM2_5                  (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */

+

+#define RCC_PLLCKSELR_DIVM3_Pos                (20U)

+#define RCC_PLLCKSELR_DIVM3_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */

+#define RCC_PLLCKSELR_DIVM3                    RCC_PLLCKSELR_DIVM3_Msk

+#define RCC_PLLCKSELR_DIVM3_0                  (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */

+#define RCC_PLLCKSELR_DIVM3_1                  (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */

+#define RCC_PLLCKSELR_DIVM3_2                  (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */

+#define RCC_PLLCKSELR_DIVM3_3                  (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */

+#define RCC_PLLCKSELR_DIVM3_4                  (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */

+#define RCC_PLLCKSELR_DIVM3_5                  (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */

+

+/********************  Bit definition for RCC_PLLCFGR register  ***************/

+

+#define RCC_PLLCFGR_PLL1FRACEN_Pos             (0U)

+#define RCC_PLLCFGR_PLL1FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */

+#define RCC_PLLCFGR_PLL1FRACEN                 RCC_PLLCFGR_PLL1FRACEN_Msk

+#define RCC_PLLCFGR_PLL1VCOSEL_Pos             (1U)

+#define RCC_PLLCFGR_PLL1VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */

+#define RCC_PLLCFGR_PLL1VCOSEL                 RCC_PLLCFGR_PLL1VCOSEL_Msk

+#define RCC_PLLCFGR_PLL1RGE_Pos                (2U)

+#define RCC_PLLCFGR_PLL1RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */

+#define RCC_PLLCFGR_PLL1RGE                    RCC_PLLCFGR_PLL1RGE_Msk

+#define RCC_PLLCFGR_PLL1RGE_0                  (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL1RGE_1                  (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */

+#define RCC_PLLCFGR_PLL1RGE_2                  (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */

+#define RCC_PLLCFGR_PLL1RGE_3                  (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */

+

+#define RCC_PLLCFGR_PLL2FRACEN_Pos             (4U)

+#define RCC_PLLCFGR_PLL2FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */

+#define RCC_PLLCFGR_PLL2FRACEN                 RCC_PLLCFGR_PLL2FRACEN_Msk

+#define RCC_PLLCFGR_PLL2VCOSEL_Pos             (5U)

+#define RCC_PLLCFGR_PLL2VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */

+#define RCC_PLLCFGR_PLL2VCOSEL                 RCC_PLLCFGR_PLL2VCOSEL_Msk

+#define RCC_PLLCFGR_PLL2RGE_Pos                (6U)

+#define RCC_PLLCFGR_PLL2RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */

+#define RCC_PLLCFGR_PLL2RGE                    RCC_PLLCFGR_PLL2RGE_Msk

+#define RCC_PLLCFGR_PLL2RGE_0                  (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL2RGE_1                  (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */

+#define RCC_PLLCFGR_PLL2RGE_2                  (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */

+#define RCC_PLLCFGR_PLL2RGE_3                  (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */

+

+#define RCC_PLLCFGR_PLL3FRACEN_Pos             (8U)

+#define RCC_PLLCFGR_PLL3FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */

+#define RCC_PLLCFGR_PLL3FRACEN                 RCC_PLLCFGR_PLL3FRACEN_Msk

+#define RCC_PLLCFGR_PLL3VCOSEL_Pos             (9U)

+#define RCC_PLLCFGR_PLL3VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */

+#define RCC_PLLCFGR_PLL3VCOSEL                 RCC_PLLCFGR_PLL3VCOSEL_Msk

+#define RCC_PLLCFGR_PLL3RGE_Pos                (10U)

+#define RCC_PLLCFGR_PLL3RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */

+#define RCC_PLLCFGR_PLL3RGE                    RCC_PLLCFGR_PLL3RGE_Msk

+#define RCC_PLLCFGR_PLL3RGE_0                  (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL3RGE_1                  (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */

+#define RCC_PLLCFGR_PLL3RGE_2                  (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */

+#define RCC_PLLCFGR_PLL3RGE_3                  (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */

+

+#define RCC_PLLCFGR_DIVP1EN_Pos                (16U)

+#define RCC_PLLCFGR_DIVP1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */

+#define RCC_PLLCFGR_DIVP1EN                    RCC_PLLCFGR_DIVP1EN_Msk

+#define RCC_PLLCFGR_DIVQ1EN_Pos                (17U)

+#define RCC_PLLCFGR_DIVQ1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */

+#define RCC_PLLCFGR_DIVQ1EN                    RCC_PLLCFGR_DIVQ1EN_Msk

+#define RCC_PLLCFGR_DIVR1EN_Pos                (18U)

+#define RCC_PLLCFGR_DIVR1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */

+#define RCC_PLLCFGR_DIVR1EN                    RCC_PLLCFGR_DIVR1EN_Msk

+

+#define RCC_PLLCFGR_DIVP2EN_Pos                (19U)

+#define RCC_PLLCFGR_DIVP2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */

+#define RCC_PLLCFGR_DIVP2EN                    RCC_PLLCFGR_DIVP2EN_Msk

+#define RCC_PLLCFGR_DIVQ2EN_Pos                (20U)

+#define RCC_PLLCFGR_DIVQ2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */

+#define RCC_PLLCFGR_DIVQ2EN                    RCC_PLLCFGR_DIVQ2EN_Msk

+#define RCC_PLLCFGR_DIVR2EN_Pos                (21U)

+#define RCC_PLLCFGR_DIVR2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */

+#define RCC_PLLCFGR_DIVR2EN                    RCC_PLLCFGR_DIVR2EN_Msk

+

+#define RCC_PLLCFGR_DIVP3EN_Pos                (22U)

+#define RCC_PLLCFGR_DIVP3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */

+#define RCC_PLLCFGR_DIVP3EN                    RCC_PLLCFGR_DIVP3EN_Msk

+#define RCC_PLLCFGR_DIVQ3EN_Pos                (23U)

+#define RCC_PLLCFGR_DIVQ3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */

+#define RCC_PLLCFGR_DIVQ3EN                    RCC_PLLCFGR_DIVQ3EN_Msk

+#define RCC_PLLCFGR_DIVR3EN_Pos                (24U)

+#define RCC_PLLCFGR_DIVR3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */

+#define RCC_PLLCFGR_DIVR3EN                    RCC_PLLCFGR_DIVR3EN_Msk

+

+

+/********************  Bit definition for RCC_PLL1DIVR register  ***************/

+#define RCC_PLL1DIVR_N1_Pos                    (0U)

+#define RCC_PLL1DIVR_N1_Msk                    (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */

+#define RCC_PLL1DIVR_N1                        RCC_PLL1DIVR_N1_Msk

+#define RCC_PLL1DIVR_P1_Pos                    (9U)

+#define RCC_PLL1DIVR_P1_Msk                    (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL1DIVR_P1                        RCC_PLL1DIVR_P1_Msk

+#define RCC_PLL1DIVR_Q1_Pos                    (16U)

+#define RCC_PLL1DIVR_Q1_Msk                    (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */

+#define RCC_PLL1DIVR_Q1                        RCC_PLL1DIVR_Q1_Msk

+#define RCC_PLL1DIVR_R1_Pos                    (24U)

+#define RCC_PLL1DIVR_R1_Msk                    (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */

+#define RCC_PLL1DIVR_R1                        RCC_PLL1DIVR_R1_Msk

+

+/********************  Bit definition for RCC_PLL1FRACR register  ***************/

+#define RCC_PLL1FRACR_FRACN1_Pos               (3U)

+#define RCC_PLL1FRACR_FRACN1_Msk               (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL1FRACR_FRACN1                   RCC_PLL1FRACR_FRACN1_Msk

+

+/********************  Bit definition for RCC_PLL2DIVR register  ***************/

+#define RCC_PLL2DIVR_N2_Pos                    (0U)

+#define RCC_PLL2DIVR_N2_Msk                    (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */

+#define RCC_PLL2DIVR_N2                        RCC_PLL2DIVR_N2_Msk

+#define RCC_PLL2DIVR_P2_Pos                    (9U)

+#define RCC_PLL2DIVR_P2_Msk                    (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL2DIVR_P2                        RCC_PLL2DIVR_P2_Msk

+#define RCC_PLL2DIVR_Q2_Pos                    (16U)

+#define RCC_PLL2DIVR_Q2_Msk                    (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */

+#define RCC_PLL2DIVR_Q2                        RCC_PLL2DIVR_Q2_Msk

+#define RCC_PLL2DIVR_R2_Pos                    (24U)

+#define RCC_PLL2DIVR_R2_Msk                    (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */

+#define RCC_PLL2DIVR_R2                        RCC_PLL2DIVR_R2_Msk

+

+/********************  Bit definition for RCC_PLL2FRACR register  ***************/

+#define RCC_PLL2FRACR_FRACN2_Pos               (3U)

+#define RCC_PLL2FRACR_FRACN2_Msk               (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL2FRACR_FRACN2                   RCC_PLL2FRACR_FRACN2_Msk

+

+/********************  Bit definition for RCC_PLL3DIVR register  ***************/

+#define RCC_PLL3DIVR_N3_Pos                    (0U)

+#define RCC_PLL3DIVR_N3_Msk                    (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */

+#define RCC_PLL3DIVR_N3                        RCC_PLL3DIVR_N3_Msk

+#define RCC_PLL3DIVR_P3_Pos                    (9U)

+#define RCC_PLL3DIVR_P3_Msk                    (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL3DIVR_P3                        RCC_PLL3DIVR_P3_Msk

+#define RCC_PLL3DIVR_Q3_Pos                    (16U)

+#define RCC_PLL3DIVR_Q3_Msk                    (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */

+#define RCC_PLL3DIVR_Q3                        RCC_PLL3DIVR_Q3_Msk

+#define RCC_PLL3DIVR_R3_Pos                    (24U)

+#define RCC_PLL3DIVR_R3_Msk                    (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */

+#define RCC_PLL3DIVR_R3                        RCC_PLL3DIVR_R3_Msk

+

+/********************  Bit definition for RCC_PLL3FRACR register  ***************/

+#define RCC_PLL3FRACR_FRACN3_Pos               (3U)

+#define RCC_PLL3FRACR_FRACN3_Msk               (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL3FRACR_FRACN3                   RCC_PLL3FRACR_FRACN3_Msk

+

+/********************  Bit definition for RCC_CDCCIPR register  ***************/

+#define RCC_CDCCIPR_FMCSEL_Pos                 (0U)

+#define RCC_CDCCIPR_FMCSEL_Msk                 (0x3UL << RCC_CDCCIPR_FMCSEL_Pos)     /*!< 0x00000003 */

+#define RCC_CDCCIPR_FMCSEL                     RCC_CDCCIPR_FMCSEL_Msk

+#define RCC_CDCCIPR_FMCSEL_0                   (0x1UL << RCC_CDCCIPR_FMCSEL_Pos)     /*!< 0x00000001 */

+#define RCC_CDCCIPR_FMCSEL_1                   (0x2UL << RCC_CDCCIPR_FMCSEL_Pos)     /*!< 0x00000002 */

+#define RCC_CDCCIPR_OCTOSPISEL_Pos             (4U)

+#define RCC_CDCCIPR_OCTOSPISEL_Msk             (0x3UL << RCC_CDCCIPR_OCTOSPISEL_Pos) /*!< 0x00000030 */

+#define RCC_CDCCIPR_OCTOSPISEL                 RCC_CDCCIPR_OCTOSPISEL_Msk

+#define RCC_CDCCIPR_OCTOSPISEL_0               (0x1UL << RCC_CDCCIPR_OCTOSPISEL_Pos) /*!< 0x00000010 */

+#define RCC_CDCCIPR_OCTOSPISEL_1               (0x2UL << RCC_CDCCIPR_OCTOSPISEL_Pos) /*!< 0x00000020 */

+#define RCC_CDCCIPR_SDMMCSEL_Pos               (16U)

+#define RCC_CDCCIPR_SDMMCSEL_Msk               (0x1UL << RCC_CDCCIPR_SDMMCSEL_Pos)   /*!< 0x00010000 */

+#define RCC_CDCCIPR_SDMMCSEL                   RCC_CDCCIPR_SDMMCSEL_Msk

+#define RCC_CDCCIPR_CKPERSEL_Pos               (28U)

+#define RCC_CDCCIPR_CKPERSEL_Msk               (0x3UL << RCC_CDCCIPR_CKPERSEL_Pos)   /*!< 0x30000000 */

+#define RCC_CDCCIPR_CKPERSEL                   RCC_CDCCIPR_CKPERSEL_Msk

+#define RCC_CDCCIPR_CKPERSEL_0                 (0x1UL << RCC_CDCCIPR_CKPERSEL_Pos)   /*!< 0x10000000 */

+#define RCC_CDCCIPR_CKPERSEL_1                 (0x2UL << RCC_CDCCIPR_CKPERSEL_Pos)   /*!< 0x20000000 */

+

+/********************  Bit definition for RCC_CDCCIP1R register  ***************/

+#define RCC_CDCCIP1R_SAI1SEL_Pos               (0U)

+#define RCC_CDCCIP1R_SAI1SEL_Msk               (0x7UL << RCC_CDCCIP1R_SAI1SEL_Pos)   /*!< 0x00000007 */

+#define RCC_CDCCIP1R_SAI1SEL                   RCC_CDCCIP1R_SAI1SEL_Msk

+#define RCC_CDCCIP1R_SAI1SEL_0                 (0x1UL << RCC_CDCCIP1R_SAI1SEL_Pos)   /*!< 0x00000001 */

+#define RCC_CDCCIP1R_SAI1SEL_1                 (0x2UL << RCC_CDCCIP1R_SAI1SEL_Pos)   /*!< 0x00000002 */

+#define RCC_CDCCIP1R_SAI1SEL_2                 (0x4UL << RCC_CDCCIP1R_SAI1SEL_Pos)   /*!< 0x00000004 */

+

+#define RCC_CDCCIP1R_SAI2ASEL_Pos              (6U)

+#define RCC_CDCCIP1R_SAI2ASEL_Msk              (0x7UL << RCC_CDCCIP1R_SAI2ASEL_Pos)  /*!< 0x000001C0 */

+#define RCC_CDCCIP1R_SAI2ASEL                  RCC_CDCCIP1R_SAI2ASEL_Msk

+#define RCC_CDCCIP1R_SAI2ASEL_0                (0x1UL << RCC_CDCCIP1R_SAI2ASEL_Pos)  /*!< 0x00000040 */

+#define RCC_CDCCIP1R_SAI2ASEL_1                (0x2UL << RCC_CDCCIP1R_SAI2ASEL_Pos)  /*!< 0x00000080 */

+#define RCC_CDCCIP1R_SAI2ASEL_2                (0x4UL << RCC_CDCCIP1R_SAI2ASEL_Pos)  /*!< 0x00000100 */

+

+#define RCC_CDCCIP1R_SAI2BSEL_Pos              (9U)

+#define RCC_CDCCIP1R_SAI2BSEL_Msk              (0x7UL << RCC_CDCCIP1R_SAI2BSEL_Pos)  /*!< 0x00000E00 */

+#define RCC_CDCCIP1R_SAI2BSEL                  RCC_CDCCIP1R_SAI2BSEL_Msk

+#define RCC_CDCCIP1R_SAI2BSEL_0                (0x1UL << RCC_CDCCIP1R_SAI2BSEL_Pos)  /*!< 0x00000200 */

+#define RCC_CDCCIP1R_SAI2BSEL_1                (0x2UL << RCC_CDCCIP1R_SAI2BSEL_Pos)  /*!< 0x00000400 */

+#define RCC_CDCCIP1R_SAI2BSEL_2                (0x4UL << RCC_CDCCIP1R_SAI2BSEL_Pos)  /*!< 0x00000800 */

+

+#define RCC_CDCCIP1R_SPI123SEL_Pos             (12U)

+#define RCC_CDCCIP1R_SPI123SEL_Msk             (0x7UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */

+#define RCC_CDCCIP1R_SPI123SEL                 RCC_CDCCIP1R_SPI123SEL_Msk

+#define RCC_CDCCIP1R_SPI123SEL_0               (0x1UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */

+#define RCC_CDCCIP1R_SPI123SEL_1               (0x2UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */

+#define RCC_CDCCIP1R_SPI123SEL_2               (0x4UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */

+

+#define RCC_CDCCIP1R_SPI45SEL_Pos              (16U)

+#define RCC_CDCCIP1R_SPI45SEL_Msk              (0x7UL << RCC_CDCCIP1R_SPI45SEL_Pos)  /*!< 0x00070000 */

+#define RCC_CDCCIP1R_SPI45SEL                  RCC_CDCCIP1R_SPI45SEL_Msk

+#define RCC_CDCCIP1R_SPI45SEL_0                (0x1UL << RCC_CDCCIP1R_SPI45SEL_Pos)  /*!< 0x00010000 */

+#define RCC_CDCCIP1R_SPI45SEL_1                (0x2UL << RCC_CDCCIP1R_SPI45SEL_Pos)  /*!< 0x00020000 */

+#define RCC_CDCCIP1R_SPI45SEL_2                (0x4UL << RCC_CDCCIP1R_SPI45SEL_Pos)  /*!< 0x00040000 */

+

+#define RCC_CDCCIP1R_SPDIFSEL_Pos              (20U)

+#define RCC_CDCCIP1R_SPDIFSEL_Msk              (0x3UL << RCC_CDCCIP1R_SPDIFSEL_Pos)  /*!< 0x00300000 */

+#define RCC_CDCCIP1R_SPDIFSEL                  RCC_CDCCIP1R_SPDIFSEL_Msk

+#define RCC_CDCCIP1R_SPDIFSEL_0                (0x1UL << RCC_CDCCIP1R_SPDIFSEL_Pos)  /*!< 0x00100000 */

+#define RCC_CDCCIP1R_SPDIFSEL_1                (0x2UL << RCC_CDCCIP1R_SPDIFSEL_Pos)  /*!< 0x00200000 */

+

+#define RCC_CDCCIP1R_DFSDM1SEL_Pos             (24U)

+#define RCC_CDCCIP1R_DFSDM1SEL_Msk             (0x1UL << RCC_CDCCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */

+#define RCC_CDCCIP1R_DFSDM1SEL                 RCC_CDCCIP1R_DFSDM1SEL_Msk

+

+#define RCC_CDCCIP1R_FDCANSEL_Pos              (28U)

+#define RCC_CDCCIP1R_FDCANSEL_Msk              (0x3UL << RCC_CDCCIP1R_FDCANSEL_Pos)  /*!< 0x30000000 */

+#define RCC_CDCCIP1R_FDCANSEL                  RCC_CDCCIP1R_FDCANSEL_Msk

+#define RCC_CDCCIP1R_FDCANSEL_0                (0x1UL << RCC_CDCCIP1R_FDCANSEL_Pos)  /*!< 0x10000000 */

+#define RCC_CDCCIP1R_FDCANSEL_1                (0x2UL << RCC_CDCCIP1R_FDCANSEL_Pos)  /*!< 0x20000000 */

+

+#define RCC_CDCCIP1R_SWPSEL_Pos                (31U)

+#define RCC_CDCCIP1R_SWPSEL_Msk                (0x1UL << RCC_CDCCIP1R_SWPSEL_Pos)    /*!< 0x80000000 */

+#define RCC_CDCCIP1R_SWPSEL                    RCC_CDCCIP1R_SWPSEL_Msk

+

+/********************  Bit definition for RCC_CDCCIP2R register  ***************/

+#define RCC_CDCCIP2R_USART234578SEL_Pos        (0U)

+#define RCC_CDCCIP2R_USART234578SEL_Msk        (0x7UL << RCC_CDCCIP2R_USART234578SEL_Pos)   /*!< 0x00000007 */

+#define RCC_CDCCIP2R_USART234578SEL            RCC_CDCCIP2R_USART234578SEL_Msk

+#define RCC_CDCCIP2R_USART234578SEL_0          (0x1UL << RCC_CDCCIP2R_USART234578SEL_Pos)   /*!< 0x00000001 */

+#define RCC_CDCCIP2R_USART234578SEL_1          (0x2UL << RCC_CDCCIP2R_USART234578SEL_Pos)   /*!< 0x00000002 */

+#define RCC_CDCCIP2R_USART234578SEL_2          (0x4UL << RCC_CDCCIP2R_USART234578SEL_Pos)   /*!< 0x00000004 */

+

+#define RCC_CDCCIP2R_USART16910SEL_Pos         (3U)

+#define RCC_CDCCIP2R_USART16910SEL_Msk         (0x7UL << RCC_CDCCIP2R_USART16910SEL_Pos)    /*!< 0x00000038 */

+#define RCC_CDCCIP2R_USART16910SEL             RCC_CDCCIP2R_USART16910SEL_Msk

+#define RCC_CDCCIP2R_USART16910SEL_0           (0x1UL << RCC_CDCCIP2R_USART16910SEL_Pos)    /*!< 0x00000008 */

+#define RCC_CDCCIP2R_USART16910SEL_1           (0x2UL << RCC_CDCCIP2R_USART16910SEL_Pos)    /*!< 0x00000010 */

+#define RCC_CDCCIP2R_USART16910SEL_2           (0x4UL << RCC_CDCCIP2R_USART16910SEL_Pos)    /*!< 0x00000020 */

+

+#define RCC_CDCCIP2R_RNGSEL_Pos                (8U)

+#define RCC_CDCCIP2R_RNGSEL_Msk                (0x3UL << RCC_CDCCIP2R_RNGSEL_Pos)           /*!< 0x00000300 */

+#define RCC_CDCCIP2R_RNGSEL                    RCC_CDCCIP2R_RNGSEL_Msk

+#define RCC_CDCCIP2R_RNGSEL_0                  (0x1UL << RCC_CDCCIP2R_RNGSEL_Pos)           /*!< 0x00000100 */

+#define RCC_CDCCIP2R_RNGSEL_1                  (0x2UL << RCC_CDCCIP2R_RNGSEL_Pos)           /*!< 0x00000200 */

+

+#define RCC_CDCCIP2R_I2C123SEL_Pos             (12U)

+#define RCC_CDCCIP2R_I2C123SEL_Msk             (0x3UL << RCC_CDCCIP2R_I2C123SEL_Pos)        /*!< 0x00003000 */

+#define RCC_CDCCIP2R_I2C123SEL                 RCC_CDCCIP2R_I2C123SEL_Msk

+#define RCC_CDCCIP2R_I2C123SEL_0               (0x1UL << RCC_CDCCIP2R_I2C123SEL_Pos)        /*!< 0x00001000 */

+#define RCC_CDCCIP2R_I2C123SEL_1               (0x2UL << RCC_CDCCIP2R_I2C123SEL_Pos)        /*!< 0x00002000 */

+

+#define RCC_CDCCIP2R_USBSEL_Pos                (20U)

+#define RCC_CDCCIP2R_USBSEL_Msk                (0x3UL << RCC_CDCCIP2R_USBSEL_Pos)           /*!< 0x00300000 */

+#define RCC_CDCCIP2R_USBSEL                    RCC_CDCCIP2R_USBSEL_Msk

+#define RCC_CDCCIP2R_USBSEL_0                  (0x1UL << RCC_CDCCIP2R_USBSEL_Pos)           /*!< 0x00100000 */

+#define RCC_CDCCIP2R_USBSEL_1                  (0x2UL << RCC_CDCCIP2R_USBSEL_Pos)           /*!< 0x00200000 */

+

+#define RCC_CDCCIP2R_CECSEL_Pos                (22U)

+#define RCC_CDCCIP2R_CECSEL_Msk                (0x3UL << RCC_CDCCIP2R_CECSEL_Pos)           /*!< 0x00C00000 */

+#define RCC_CDCCIP2R_CECSEL                    RCC_CDCCIP2R_CECSEL_Msk

+#define RCC_CDCCIP2R_CECSEL_0                  (0x1UL << RCC_CDCCIP2R_CECSEL_Pos)           /*!< 0x00400000 */

+#define RCC_CDCCIP2R_CECSEL_1                  (0x2UL << RCC_CDCCIP2R_CECSEL_Pos)           /*!< 0x00800000 */

+

+#define RCC_CDCCIP2R_LPTIM1SEL_Pos             (28U)

+#define RCC_CDCCIP2R_LPTIM1SEL_Msk             (0x7UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)        /*!< 0x70000000 */

+#define RCC_CDCCIP2R_LPTIM1SEL                 RCC_CDCCIP2R_LPTIM1SEL_Msk

+#define RCC_CDCCIP2R_LPTIM1SEL_0               (0x1UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)        /*!< 0x10000000 */

+#define RCC_CDCCIP2R_LPTIM1SEL_1               (0x2UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)        /*!< 0x20000000 */

+#define RCC_CDCCIP2R_LPTIM1SEL_2               (0x4UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)        /*!< 0x40000000 */

+

+/********************  Bit definition for RCC_SRDCCIPR register  ***************/

+#define RCC_SRDCCIPR_LPUART1SEL_Pos             (0U)

+#define RCC_SRDCCIPR_LPUART1SEL_Msk             (0x7UL << RCC_SRDCCIPR_LPUART1SEL_Pos)      /*!< 0x00000007 */

+#define RCC_SRDCCIPR_LPUART1SEL                 RCC_SRDCCIPR_LPUART1SEL_Msk

+#define RCC_SRDCCIPR_LPUART1SEL_0               (0x1UL << RCC_SRDCCIPR_LPUART1SEL_Pos)      /*!< 0x00000001 */

+#define RCC_SRDCCIPR_LPUART1SEL_1               (0x2UL << RCC_SRDCCIPR_LPUART1SEL_Pos)      /*!< 0x00000002 */

+#define RCC_SRDCCIPR_LPUART1SEL_2               (0x4UL << RCC_SRDCCIPR_LPUART1SEL_Pos)      /*!< 0x00000004 */

+

+#define RCC_SRDCCIPR_I2C4SEL_Pos                (8U)

+#define RCC_SRDCCIPR_I2C4SEL_Msk                (0x3UL << RCC_SRDCCIPR_I2C4SEL_Pos)         /*!< 0x00000300 */

+#define RCC_SRDCCIPR_I2C4SEL                    RCC_SRDCCIPR_I2C4SEL_Msk

+#define RCC_SRDCCIPR_I2C4SEL_0                  (0x1UL << RCC_SRDCCIPR_I2C4SEL_Pos)         /*!< 0x00000100 */

+#define RCC_SRDCCIPR_I2C4SEL_1                  (0x2UL << RCC_SRDCCIPR_I2C4SEL_Pos)         /*!< 0x00000200 */

+

+#define RCC_SRDCCIPR_LPTIM2SEL_Pos              (10U)

+#define RCC_SRDCCIPR_LPTIM2SEL_Msk              (0x7UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)       /*!< 0x00001C00 */

+#define RCC_SRDCCIPR_LPTIM2SEL                  RCC_SRDCCIPR_LPTIM2SEL_Msk

+#define RCC_SRDCCIPR_LPTIM2SEL_0                (0x1UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)       /*!< 0x00000400 */

+#define RCC_SRDCCIPR_LPTIM2SEL_1                (0x2UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)       /*!< 0x00000800 */

+#define RCC_SRDCCIPR_LPTIM2SEL_2                (0x4UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)       /*!< 0x00001000 */

+

+#define RCC_SRDCCIPR_LPTIM3SEL_Pos            (13U)

+#define RCC_SRDCCIPR_LPTIM3SEL_Msk            (0x7UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)         /*!< 0x0000E000 */

+#define RCC_SRDCCIPR_LPTIM3SEL                RCC_SRDCCIPR_LPTIM3SEL_Msk

+#define RCC_SRDCCIPR_LPTIM3SEL_0              (0x1UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)         /*!< 0x00002000 */

+#define RCC_SRDCCIPR_LPTIM3SEL_1              (0x2UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)         /*!< 0x00004000 */

+#define RCC_SRDCCIPR_LPTIM3SEL_2              (0x4UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)         /*!< 0x00008000 */

+

+#define RCC_SRDCCIPR_ADCSEL_Pos                 (16U)

+#define RCC_SRDCCIPR_ADCSEL_Msk                 (0x3UL << RCC_SRDCCIPR_ADCSEL_Pos)          /*!< 0x00030000 */

+#define RCC_SRDCCIPR_ADCSEL                     RCC_SRDCCIPR_ADCSEL_Msk

+#define RCC_SRDCCIPR_ADCSEL_0                   (0x1UL << RCC_SRDCCIPR_ADCSEL_Pos)          /*!< 0x00010000 */

+#define RCC_SRDCCIPR_ADCSEL_1                   (0x2UL << RCC_SRDCCIPR_ADCSEL_Pos)          /*!< 0x00020000 */

+

+#define RCC_SRDCCIPR_DFSDM2SEL_Pos              (27U)

+#define RCC_SRDCCIPR_DFSDM2SEL_Msk              (0x1UL << RCC_SRDCCIPR_DFSDM2SEL_Pos)       /*!< 0x08000000 */

+#define RCC_SRDCCIPR_DFSDM2SEL                   RCC_SRDCCIPR_DFSDM2SEL_Msk

+

+#define RCC_SRDCCIPR_SPI6SEL_Pos                (28U)

+#define RCC_SRDCCIPR_SPI6SEL_Msk                (0x7UL << RCC_SRDCCIPR_SPI6SEL_Pos)         /*!< 0x70000000 */

+#define RCC_SRDCCIPR_SPI6SEL                    RCC_SRDCCIPR_SPI6SEL_Msk

+#define RCC_SRDCCIPR_SPI6SEL_0                  (0x1UL << RCC_SRDCCIPR_SPI6SEL_Pos)         /*!< 0x10000000 */

+#define RCC_SRDCCIPR_SPI6SEL_1                  (0x2UL << RCC_SRDCCIPR_SPI6SEL_Pos)         /*!< 0x20000000 */

+#define RCC_SRDCCIPR_SPI6SEL_2                  (0x4UL << RCC_SRDCCIPR_SPI6SEL_Pos)         /*!< 0x40000000 */

+

+/********************  Bit definition for RCC_CIER register  ******************/

+#define RCC_CIER_LSIRDYIE_Pos                  (0U)

+#define RCC_CIER_LSIRDYIE_Msk                  (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */

+#define RCC_CIER_LSIRDYIE                      RCC_CIER_LSIRDYIE_Msk

+#define RCC_CIER_LSERDYIE_Pos                  (1U)

+#define RCC_CIER_LSERDYIE_Msk                  (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */

+#define RCC_CIER_LSERDYIE                      RCC_CIER_LSERDYIE_Msk

+#define RCC_CIER_HSIRDYIE_Pos                  (2U)

+#define RCC_CIER_HSIRDYIE_Msk                  (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */

+#define RCC_CIER_HSIRDYIE                      RCC_CIER_HSIRDYIE_Msk

+#define RCC_CIER_HSERDYIE_Pos                  (3U)

+#define RCC_CIER_HSERDYIE_Msk                  (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */

+#define RCC_CIER_HSERDYIE                      RCC_CIER_HSERDYIE_Msk

+#define RCC_CIER_CSIRDYIE_Pos                  (4U)

+#define RCC_CIER_CSIRDYIE_Msk                  (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */

+#define RCC_CIER_CSIRDYIE                      RCC_CIER_CSIRDYIE_Msk

+#define RCC_CIER_HSI48RDYIE_Pos                (5U)

+#define RCC_CIER_HSI48RDYIE_Msk                (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */

+#define RCC_CIER_HSI48RDYIE                    RCC_CIER_HSI48RDYIE_Msk

+#define RCC_CIER_PLL1RDYIE_Pos                 (6U)

+#define RCC_CIER_PLL1RDYIE_Msk                 (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */

+#define RCC_CIER_PLL1RDYIE                     RCC_CIER_PLL1RDYIE_Msk

+#define RCC_CIER_PLL2RDYIE_Pos                 (7U)

+#define RCC_CIER_PLL2RDYIE_Msk                 (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */

+#define RCC_CIER_PLL2RDYIE                     RCC_CIER_PLL2RDYIE_Msk

+#define RCC_CIER_PLL3RDYIE_Pos                 (8U)

+#define RCC_CIER_PLL3RDYIE_Msk                 (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */

+#define RCC_CIER_PLL3RDYIE                     RCC_CIER_PLL3RDYIE_Msk

+#define RCC_CIER_LSECSSIE_Pos                  (9U)

+#define RCC_CIER_LSECSSIE_Msk                  (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */

+#define RCC_CIER_LSECSSIE                      RCC_CIER_LSECSSIE_Msk

+

+/********************  Bit definition for RCC_CIFR register  ******************/

+#define RCC_CIFR_LSIRDYF_Pos                   (0U)

+#define RCC_CIFR_LSIRDYF_Msk                   (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */

+#define RCC_CIFR_LSIRDYF                       RCC_CIFR_LSIRDYF_Msk

+#define RCC_CIFR_LSERDYF_Pos                   (1U)

+#define RCC_CIFR_LSERDYF_Msk                   (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */

+#define RCC_CIFR_LSERDYF                       RCC_CIFR_LSERDYF_Msk

+#define RCC_CIFR_HSIRDYF_Pos                   (2U)

+#define RCC_CIFR_HSIRDYF_Msk                   (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */

+#define RCC_CIFR_HSIRDYF                       RCC_CIFR_HSIRDYF_Msk

+#define RCC_CIFR_HSERDYF_Pos                   (3U)

+#define RCC_CIFR_HSERDYF_Msk                   (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */

+#define RCC_CIFR_HSERDYF                       RCC_CIFR_HSERDYF_Msk

+#define RCC_CIFR_CSIRDYF_Pos                   (4U)

+#define RCC_CIFR_CSIRDYF_Msk                   (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */

+#define RCC_CIFR_CSIRDYF                       RCC_CIFR_CSIRDYF_Msk

+#define RCC_CIFR_HSI48RDYF_Pos                 (5U)

+#define RCC_CIFR_HSI48RDYF_Msk                 (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */

+#define RCC_CIFR_HSI48RDYF                     RCC_CIFR_HSI48RDYF_Msk

+#define RCC_CIFR_PLLRDYF_Pos                   (6U)

+#define RCC_CIFR_PLLRDYF_Msk                   (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */

+#define RCC_CIFR_PLLRDYF                       RCC_CIFR_PLLRDYF_Msk

+#define RCC_CIFR_PLL2RDYF_Pos                  (7U)

+#define RCC_CIFR_PLL2RDYF_Msk                  (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */

+#define RCC_CIFR_PLL2RDYF                      RCC_CIFR_PLL2RDYF_Msk

+#define RCC_CIFR_PLL3RDYF_Pos                  (8U)

+#define RCC_CIFR_PLL3RDYF_Msk                  (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */

+#define RCC_CIFR_PLL3RDYF                      RCC_CIFR_PLL3RDYF_Msk

+#define RCC_CIFR_LSECSSF_Pos                   (9U)

+#define RCC_CIFR_LSECSSF_Msk                   (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */

+#define RCC_CIFR_LSECSSF                       RCC_CIFR_LSECSSF_Msk

+#define RCC_CIFR_HSECSSF_Pos                   (10U)

+#define RCC_CIFR_HSECSSF_Msk                   (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */

+#define RCC_CIFR_HSECSSF                       RCC_CIFR_HSECSSF_Msk

+

+/********************  Bit definition for RCC_CICR register  ******************/

+#define RCC_CICR_LSIRDYC_Pos                   (0U)

+#define RCC_CICR_LSIRDYC_Msk                   (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */

+#define RCC_CICR_LSIRDYC                       RCC_CICR_LSIRDYC_Msk

+#define RCC_CICR_LSERDYC_Pos                   (1U)

+#define RCC_CICR_LSERDYC_Msk                   (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */

+#define RCC_CICR_LSERDYC                       RCC_CICR_LSERDYC_Msk

+#define RCC_CICR_HSIRDYC_Pos                   (2U)

+#define RCC_CICR_HSIRDYC_Msk                   (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */

+#define RCC_CICR_HSIRDYC                       RCC_CICR_HSIRDYC_Msk

+#define RCC_CICR_HSERDYC_Pos                   (3U)

+#define RCC_CICR_HSERDYC_Msk                   (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */

+#define RCC_CICR_HSERDYC                       RCC_CICR_HSERDYC_Msk

+#define RCC_CICR_CSIRDYC_Pos                   (4U)

+#define RCC_CICR_CSIRDYC_Msk                   (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */

+#define RCC_CICR_CSIRDYC                       RCC_CICR_CSIRDYC_Msk

+#define RCC_CICR_HSI48RDYC_Pos                 (5U)

+#define RCC_CICR_HSI48RDYC_Msk                 (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */

+#define RCC_CICR_HSI48RDYC                     RCC_CICR_HSI48RDYC_Msk

+#define RCC_CICR_PLLRDYC_Pos                   (6U)

+#define RCC_CICR_PLLRDYC_Msk                   (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */

+#define RCC_CICR_PLLRDYC                       RCC_CICR_PLLRDYC_Msk

+#define RCC_CICR_PLL2RDYC_Pos                  (7U)

+#define RCC_CICR_PLL2RDYC_Msk                  (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */

+#define RCC_CICR_PLL2RDYC                      RCC_CICR_PLL2RDYC_Msk

+#define RCC_CICR_PLL3RDYC_Pos                  (8U)

+#define RCC_CICR_PLL3RDYC_Msk                  (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */

+#define RCC_CICR_PLL3RDYC                      RCC_CICR_PLL3RDYC_Msk

+#define RCC_CICR_LSECSSC_Pos                   (9U)

+#define RCC_CICR_LSECSSC_Msk                   (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */

+#define RCC_CICR_LSECSSC                       RCC_CICR_LSECSSC_Msk

+#define RCC_CICR_HSECSSC_Pos                   (10U)

+#define RCC_CICR_HSECSSC_Msk                   (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */

+#define RCC_CICR_HSECSSC                       RCC_CICR_HSECSSC_Msk

+

+/********************  Bit definition for RCC_BDCR register  ******************/

+#define RCC_BDCR_LSEON_Pos                     (0U)

+#define RCC_BDCR_LSEON_Msk                     (0x1UL << RCC_BDCR_LSEON_Pos)   /*!< 0x00000001 */

+#define RCC_BDCR_LSEON                         RCC_BDCR_LSEON_Msk

+#define RCC_BDCR_LSERDY_Pos                    (1U)

+#define RCC_BDCR_LSERDY_Msk                    (0x1UL << RCC_BDCR_LSERDY_Pos)  /*!< 0x00000002 */

+#define RCC_BDCR_LSERDY                        RCC_BDCR_LSERDY_Msk

+#define RCC_BDCR_LSEBYP_Pos                    (2U)

+#define RCC_BDCR_LSEBYP_Msk                    (0x1UL << RCC_BDCR_LSEBYP_Pos)  /*!< 0x00000004 */

+#define RCC_BDCR_LSEBYP                        RCC_BDCR_LSEBYP_Msk

+

+#define RCC_BDCR_LSEDRV_Pos                    (3U)

+#define RCC_BDCR_LSEDRV_Msk                    (0x3UL << RCC_BDCR_LSEDRV_Pos)  /*!< 0x00000018 */

+#define RCC_BDCR_LSEDRV                        RCC_BDCR_LSEDRV_Msk

+#define RCC_BDCR_LSEDRV_0                      (0x1UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000008 */

+#define RCC_BDCR_LSEDRV_1                      (0x2UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000010 */

+

+#define RCC_BDCR_LSECSSON_Pos                  (5U)

+#define RCC_BDCR_LSECSSON_Msk                  (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */

+#define RCC_BDCR_LSECSSON                      RCC_BDCR_LSECSSON_Msk

+#define RCC_BDCR_LSECSSD_Pos                   (6U)

+#define RCC_BDCR_LSECSSD_Msk                   (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */

+#define RCC_BDCR_LSECSSD                       RCC_BDCR_LSECSSD_Msk

+#define RCC_BDCR_LSEEXT_Pos                    (7U)

+#define RCC_BDCR_LSEEXT_Msk                    (0x1UL << RCC_BDCR_LSEEXT_Pos)  /*!< 0x00000080 */

+#define RCC_BDCR_LSEEXT                        RCC_BDCR_LSEEXT_Msk

+

+#define RCC_BDCR_RTCSEL_Pos                    (8U)

+#define RCC_BDCR_RTCSEL_Msk                    (0x3UL << RCC_BDCR_RTCSEL_Pos)  /*!< 0x00000300 */

+#define RCC_BDCR_RTCSEL                        RCC_BDCR_RTCSEL_Msk

+#define RCC_BDCR_RTCSEL_0                      (0x1UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000100 */

+#define RCC_BDCR_RTCSEL_1                      (0x2UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000200 */

+

+#define RCC_BDCR_RTCEN_Pos                     (15U)

+#define RCC_BDCR_RTCEN_Msk                     (0x1UL << RCC_BDCR_RTCEN_Pos)   /*!< 0x00008000 */

+#define RCC_BDCR_RTCEN                         RCC_BDCR_RTCEN_Msk

+#define RCC_BDCR_VSWRST_Pos                    (16U)

+#define RCC_BDCR_VSWRST_Msk                    (0x1UL << RCC_BDCR_VSWRST_Pos)   /*!< 0x00010000 */

+#define RCC_BDCR_VSWRST                        RCC_BDCR_VSWRST_Msk

+/* Legacy define */

+#define RCC_BDCR_BDRST_Pos                     RCC_BDCR_VSWRST_Pos

+#define RCC_BDCR_BDRST_Msk                     RCC_BDCR_VSWRST_Msk

+#define RCC_BDCR_BDRST                         RCC_BDCR_VSWRST

+/********************  Bit definition for RCC_CSR register  *******************/

+#define RCC_CSR_LSION_Pos                      (0U)

+#define RCC_CSR_LSION_Msk                      (0x1UL << RCC_CSR_LSION_Pos)    /*!< 0x00000001 */

+#define RCC_CSR_LSION                          RCC_CSR_LSION_Msk

+#define RCC_CSR_LSIRDY_Pos                     (1U)

+#define RCC_CSR_LSIRDY_Msk                     (0x1UL << RCC_CSR_LSIRDY_Pos)   /*!< 0x00000002 */

+#define RCC_CSR_LSIRDY                         RCC_CSR_LSIRDY_Msk

+

+

+/********************  Bit definition for RCC_AHB3ENR register  **************/

+#define RCC_AHB3ENR_MDMAEN_Pos                 (0U)

+#define RCC_AHB3ENR_MDMAEN_Msk                 (0x1UL << RCC_AHB3ENR_MDMAEN_Pos)       /*!< 0x00000001 */

+#define RCC_AHB3ENR_MDMAEN                     RCC_AHB3ENR_MDMAEN_Msk

+#define RCC_AHB3ENR_DMA2DEN_Pos                (4U)

+#define RCC_AHB3ENR_DMA2DEN_Msk                (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos)      /*!< 0x00000010 */

+#define RCC_AHB3ENR_DMA2DEN                    RCC_AHB3ENR_DMA2DEN_Msk

+#define RCC_AHB3ENR_JPGDECEN_Pos               (5U)

+#define RCC_AHB3ENR_JPGDECEN_Msk               (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos)     /*!< 0x00000020 */

+#define RCC_AHB3ENR_JPGDECEN                   RCC_AHB3ENR_JPGDECEN_Msk

+#define RCC_AHB3ENR_FMCEN_Pos                  (12U)

+#define RCC_AHB3ENR_FMCEN_Msk                  (0x1UL << RCC_AHB3ENR_FMCEN_Pos)        /*!< 0x00001000 */

+#define RCC_AHB3ENR_FMCEN                      RCC_AHB3ENR_FMCEN_Msk

+#define RCC_AHB3ENR_OSPI1EN_Pos                (14U)

+#define RCC_AHB3ENR_OSPI1EN_Msk                (0x1UL << RCC_AHB3ENR_OSPI1EN_Pos)      /*!< 0x00004000 */

+#define RCC_AHB3ENR_OSPI1EN                    RCC_AHB3ENR_OSPI1EN_Msk

+#define RCC_AHB3ENR_SDMMC1EN_Pos               (16U)

+#define RCC_AHB3ENR_SDMMC1EN_Msk               (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos)     /*!< 0x00010000 */

+#define RCC_AHB3ENR_SDMMC1EN                   RCC_AHB3ENR_SDMMC1EN_Msk

+#define RCC_AHB3ENR_OSPI2EN_Pos                (19U)

+#define RCC_AHB3ENR_OSPI2EN_Msk                (0x1UL << RCC_AHB3ENR_OSPI2EN_Pos)      /*!< 0x00040000 */

+#define RCC_AHB3ENR_OSPI2EN                    RCC_AHB3ENR_OSPI2EN_Msk

+#define RCC_AHB3ENR_IOMNGREN_Pos               (21U)

+#define RCC_AHB3ENR_IOMNGREN_Msk               (0x1UL << RCC_AHB3ENR_IOMNGREN_Pos)     /*!< 0x00100000 */

+#define RCC_AHB3ENR_IOMNGREN                   RCC_AHB3ENR_IOMNGREN_Msk

+#define RCC_AHB3ENR_GFXMMUEN_Pos               (24U)

+#define RCC_AHB3ENR_GFXMMUEN_Msk               (0x1UL << RCC_AHB3ENR_GFXMMUEN_Pos)     /*!< 0x00800000 */

+#define RCC_AHB3ENR_GFXMMUEN                   RCC_AHB3ENR_GFXMMUEN_Msk

+

+/********************  Bit definition for RCC_AHB1ENR register  ***************/

+#define RCC_AHB1ENR_DMA1EN_Pos                 (0U)

+#define RCC_AHB1ENR_DMA1EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)          /*!< 0x00000001 */

+#define RCC_AHB1ENR_DMA1EN                     RCC_AHB1ENR_DMA1EN_Msk

+#define RCC_AHB1ENR_DMA2EN_Pos                 (1U)

+#define RCC_AHB1ENR_DMA2EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)          /*!< 0x00000002 */

+#define RCC_AHB1ENR_DMA2EN                     RCC_AHB1ENR_DMA2EN_Msk

+#define RCC_AHB1ENR_ADC12EN_Pos                (5U)

+#define RCC_AHB1ENR_ADC12EN_Msk                (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)         /*!< 0x00000020 */

+#define RCC_AHB1ENR_ADC12EN                    RCC_AHB1ENR_ADC12EN_Msk

+#define RCC_AHB1ENR_CRCEN_Pos                  (9U)

+#define RCC_AHB1ENR_CRCEN_Msk                  (0x1UL << RCC_AHB1ENR_CRCEN_Pos)           /*!< 0x00000200 */

+#define RCC_AHB1ENR_CRCEN                      RCC_AHB1ENR_CRCEN_Msk

+#define RCC_AHB1ENR_USB1OTGHSEN_Pos            (25U)

+#define RCC_AHB1ENR_USB1OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos)     /*!< 0x02000000 */

+#define RCC_AHB1ENR_USB1OTGHSEN                RCC_AHB1ENR_USB1OTGHSEN_Msk

+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos        (26U)

+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */

+#define RCC_AHB1ENR_USB1OTGHSULPIEN            RCC_AHB1ENR_USB1OTGHSULPIEN_Msk

+

+/********************  Bit definition for RCC_AHB2ENR register  ***************/

+#define RCC_AHB2ENR_DCMI_PSSIEN_Pos            (0U)

+#define RCC_AHB2ENR_DCMI_PSSIEN_Msk            (0x1UL << RCC_AHB2ENR_DCMI_PSSIEN_Pos)     /*!< 0x00000001 */

+#define RCC_AHB2ENR_DCMI_PSSIEN                RCC_AHB2ENR_DCMI_PSSIEN_Msk

+#define RCC_AHB2ENR_HSEMEN_Pos                 (2U)

+#define RCC_AHB2ENR_HSEMEN_Msk                 (0x1UL << RCC_AHB2ENR_HSEMEN_Pos)          /*!< 0x00000004 */

+#define RCC_AHB2ENR_HSEMEN                     RCC_AHB2ENR_HSEMEN_Msk

+#define RCC_AHB2ENR_RNGEN_Pos                  (6U)

+#define RCC_AHB2ENR_RNGEN_Msk                  (0x1UL << RCC_AHB2ENR_RNGEN_Pos)           /*!< 0x00000040 */

+#define RCC_AHB2ENR_RNGEN                      RCC_AHB2ENR_RNGEN_Msk

+#define RCC_AHB2ENR_SDMMC2EN_Pos               (9U)

+#define RCC_AHB2ENR_SDMMC2EN_Msk               (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)        /*!< 0x00000200 */

+#define RCC_AHB2ENR_SDMMC2EN                   RCC_AHB2ENR_SDMMC2EN_Msk

+#define RCC_AHB2ENR_BDMA1EN_Pos                (11U)

+#define RCC_AHB2ENR_BDMA1EN_Msk                (0x1UL << RCC_AHB2ENR_BDMA1EN_Pos)         /*!< 0x00000800 */

+#define RCC_AHB2ENR_BDMA1EN                    RCC_AHB2ENR_BDMA1EN_Msk

+#define RCC_AHB2ENR_AHBSRAM1EN_Pos             (29U)

+#define RCC_AHB2ENR_AHBSRAM1EN_Msk             (0x1UL << RCC_AHB2ENR_AHBSRAM1EN_Pos)       /*!< 0x20000000 */

+#define RCC_AHB2ENR_AHBSRAM1EN                 RCC_AHB2ENR_AHBSRAM1EN_Msk

+#define RCC_AHB2ENR_AHBSRAM2EN_Pos             (30U)

+#define RCC_AHB2ENR_AHBSRAM2EN_Msk             (0x1UL << RCC_AHB2ENR_AHBSRAM2EN_Pos)       /*!< 0x40000000 */

+#define RCC_AHB2ENR_AHBSRAM2EN                 RCC_AHB2ENR_AHBSRAM2EN_Msk

+

+/* Legacy define */

+#define RCC_AHB2ENR_DCMIEN_Pos                 RCC_AHB2ENR_DCMI_PSSIEN_Pos

+#define RCC_AHB2ENR_DCMIEN_Msk                 RCC_AHB2ENR_DCMI_PSSIEN_Msk

+#define RCC_AHB2ENR_DCMIEN                     RCC_AHB2ENR_DCMI_PSSIEN

+

+/********************  Bit definition for RCC_AHB4ENR register  ******************/

+#define RCC_AHB4ENR_GPIOAEN_Pos                (0U)

+#define RCC_AHB4ENR_GPIOAEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)         /*!< 0x00000001 */

+#define RCC_AHB4ENR_GPIOAEN                    RCC_AHB4ENR_GPIOAEN_Msk

+#define RCC_AHB4ENR_GPIOBEN_Pos                (1U)

+#define RCC_AHB4ENR_GPIOBEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)         /*!< 0x00000002 */

+#define RCC_AHB4ENR_GPIOBEN                    RCC_AHB4ENR_GPIOBEN_Msk

+#define RCC_AHB4ENR_GPIOCEN_Pos                (2U)

+#define RCC_AHB4ENR_GPIOCEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)         /*!< 0x00000004 */

+#define RCC_AHB4ENR_GPIOCEN                    RCC_AHB4ENR_GPIOCEN_Msk

+#define RCC_AHB4ENR_GPIODEN_Pos                (3U)

+#define RCC_AHB4ENR_GPIODEN_Msk                (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)         /*!< 0x00000008 */

+#define RCC_AHB4ENR_GPIODEN                    RCC_AHB4ENR_GPIODEN_Msk

+#define RCC_AHB4ENR_GPIOEEN_Pos                (4U)

+#define RCC_AHB4ENR_GPIOEEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)         /*!< 0x00000010 */

+#define RCC_AHB4ENR_GPIOEEN                    RCC_AHB4ENR_GPIOEEN_Msk

+#define RCC_AHB4ENR_GPIOFEN_Pos                (5U)

+#define RCC_AHB4ENR_GPIOFEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)         /*!< 0x00000020 */

+#define RCC_AHB4ENR_GPIOFEN                    RCC_AHB4ENR_GPIOFEN_Msk

+#define RCC_AHB4ENR_GPIOGEN_Pos                (6U)

+#define RCC_AHB4ENR_GPIOGEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)         /*!< 0x00000040 */

+#define RCC_AHB4ENR_GPIOGEN                    RCC_AHB4ENR_GPIOGEN_Msk

+#define RCC_AHB4ENR_GPIOHEN_Pos                (7U)

+#define RCC_AHB4ENR_GPIOHEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)         /*!< 0x00000080 */

+#define RCC_AHB4ENR_GPIOHEN                    RCC_AHB4ENR_GPIOHEN_Msk

+#define RCC_AHB4ENR_GPIOIEN_Pos                (8U)

+#define RCC_AHB4ENR_GPIOIEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos)         /*!< 0x00000100 */

+#define RCC_AHB4ENR_GPIOIEN                    RCC_AHB4ENR_GPIOIEN_Msk

+#define RCC_AHB4ENR_GPIOJEN_Pos                (9U)

+#define RCC_AHB4ENR_GPIOJEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos)         /*!< 0x00000200 */

+#define RCC_AHB4ENR_GPIOJEN                    RCC_AHB4ENR_GPIOJEN_Msk

+#define RCC_AHB4ENR_GPIOKEN_Pos                (10U)

+#define RCC_AHB4ENR_GPIOKEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos)         /*!< 0x00000400 */

+#define RCC_AHB4ENR_GPIOKEN                    RCC_AHB4ENR_GPIOKEN_Msk

+#define RCC_AHB4ENR_BDMA2EN_Pos                (21U)

+#define RCC_AHB4ENR_BDMA2EN_Msk                (0x1UL << RCC_AHB4ENR_BDMA2EN_Pos)         /*!< 0x00080000 */

+#define RCC_AHB4ENR_BDMA2EN                    RCC_AHB4ENR_BDMA2EN_Msk

+#define RCC_AHB4ENR_BKPRAMEN_Pos               (28U)

+#define RCC_AHB4ENR_BKPRAMEN_Msk               (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)        /*!< 0x10000000 */

+#define RCC_AHB4ENR_BKPRAMEN                   RCC_AHB4ENR_BKPRAMEN_Msk

+#define RCC_AHB4ENR_SRDSRAMEN_Pos              (29U)

+#define RCC_AHB4ENR_SRDSRAMEN_Msk              (0x1UL << RCC_AHB4ENR_SRDSRAMEN_Pos)       /*!< 0x20000000 */

+#define RCC_AHB4ENR_SRDSRAMEN                  RCC_AHB4ENR_SRDSRAMEN_Msk

+

+/********************  Bit definition for RCC_APB3ENR register  ******************/

+#define RCC_APB3ENR_LTDCEN_Pos                 (3U)

+#define RCC_APB3ENR_LTDCEN_Msk                 (0x1UL << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */

+#define RCC_APB3ENR_LTDCEN                     RCC_APB3ENR_LTDCEN_Msk

+#define RCC_APB3ENR_WWDGEN_Pos                 (6U)

+#define RCC_APB3ENR_WWDGEN_Msk                 (0x1UL << RCC_APB3ENR_WWDGEN_Pos) /*!< 0x00000040 */

+#define RCC_APB3ENR_WWDGEN                     RCC_APB3ENR_WWDGEN_Msk

+

+/* Legacy define */

+#define RCC_APB3ENR_WWDG1EN_Pos                 RCC_APB3ENR_WWDGEN_Pos

+#define RCC_APB3ENR_WWDG1EN_Msk                 RCC_APB3ENR_WWDGEN_Msk

+#define RCC_APB3ENR_WWDG1EN                     RCC_APB3ENR_WWDGEN

+/********************  Bit definition for RCC_APB1LENR register  ******************/

+

+#define RCC_APB1LENR_TIM2EN_Pos                (0U)

+#define RCC_APB1LENR_TIM2EN_Msk                (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */

+#define RCC_APB1LENR_TIM2EN                    RCC_APB1LENR_TIM2EN_Msk

+#define RCC_APB1LENR_TIM3EN_Pos                (1U)

+#define RCC_APB1LENR_TIM3EN_Msk                (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */

+#define RCC_APB1LENR_TIM3EN                    RCC_APB1LENR_TIM3EN_Msk

+#define RCC_APB1LENR_TIM4EN_Pos                (2U)

+#define RCC_APB1LENR_TIM4EN_Msk                (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */

+#define RCC_APB1LENR_TIM4EN                    RCC_APB1LENR_TIM4EN_Msk

+#define RCC_APB1LENR_TIM5EN_Pos                (3U)

+#define RCC_APB1LENR_TIM5EN_Msk                (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */

+#define RCC_APB1LENR_TIM5EN                    RCC_APB1LENR_TIM5EN_Msk

+#define RCC_APB1LENR_TIM6EN_Pos                (4U)

+#define RCC_APB1LENR_TIM6EN_Msk                (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */

+#define RCC_APB1LENR_TIM6EN                    RCC_APB1LENR_TIM6EN_Msk

+#define RCC_APB1LENR_TIM7EN_Pos                (5U)

+#define RCC_APB1LENR_TIM7EN_Msk                (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */

+#define RCC_APB1LENR_TIM7EN                    RCC_APB1LENR_TIM7EN_Msk

+#define RCC_APB1LENR_TIM12EN_Pos               (6U)

+#define RCC_APB1LENR_TIM12EN_Msk               (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */

+#define RCC_APB1LENR_TIM12EN                   RCC_APB1LENR_TIM12EN_Msk

+#define RCC_APB1LENR_TIM13EN_Pos               (7U)

+#define RCC_APB1LENR_TIM13EN_Msk               (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */

+#define RCC_APB1LENR_TIM13EN                   RCC_APB1LENR_TIM13EN_Msk

+#define RCC_APB1LENR_TIM14EN_Pos               (8U)

+#define RCC_APB1LENR_TIM14EN_Msk               (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */

+#define RCC_APB1LENR_TIM14EN                   RCC_APB1LENR_TIM14EN_Msk

+#define RCC_APB1LENR_LPTIM1EN_Pos              (9U)

+#define RCC_APB1LENR_LPTIM1EN_Msk              (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */

+#define RCC_APB1LENR_LPTIM1EN                  RCC_APB1LENR_LPTIM1EN_Msk

+

+

+#define RCC_APB1LENR_SPI2EN_Pos                (14U)

+#define RCC_APB1LENR_SPI2EN_Msk                (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */

+#define RCC_APB1LENR_SPI2EN                    RCC_APB1LENR_SPI2EN_Msk

+#define RCC_APB1LENR_SPI3EN_Pos                (15U)

+#define RCC_APB1LENR_SPI3EN_Msk                (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */

+#define RCC_APB1LENR_SPI3EN                    RCC_APB1LENR_SPI3EN_Msk

+#define RCC_APB1LENR_SPDIFRXEN_Pos             (16U)

+#define RCC_APB1LENR_SPDIFRXEN_Msk             (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */

+#define RCC_APB1LENR_SPDIFRXEN                 RCC_APB1LENR_SPDIFRXEN_Msk

+#define RCC_APB1LENR_USART2EN_Pos              (17U)

+#define RCC_APB1LENR_USART2EN_Msk              (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */

+#define RCC_APB1LENR_USART2EN                  RCC_APB1LENR_USART2EN_Msk

+#define RCC_APB1LENR_USART3EN_Pos              (18U)

+#define RCC_APB1LENR_USART3EN_Msk              (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */

+#define RCC_APB1LENR_USART3EN                  RCC_APB1LENR_USART3EN_Msk

+#define RCC_APB1LENR_UART4EN_Pos               (19U)

+#define RCC_APB1LENR_UART4EN_Msk               (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */

+#define RCC_APB1LENR_UART4EN                   RCC_APB1LENR_UART4EN_Msk

+#define RCC_APB1LENR_UART5EN_Pos               (20U)

+#define RCC_APB1LENR_UART5EN_Msk               (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */

+#define RCC_APB1LENR_UART5EN                   RCC_APB1LENR_UART5EN_Msk

+#define RCC_APB1LENR_I2C1EN_Pos                (21U)

+#define RCC_APB1LENR_I2C1EN_Msk                (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */

+#define RCC_APB1LENR_I2C1EN                    RCC_APB1LENR_I2C1EN_Msk

+#define RCC_APB1LENR_I2C2EN_Pos                (22U)

+#define RCC_APB1LENR_I2C2EN_Msk                (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */

+#define RCC_APB1LENR_I2C2EN                    RCC_APB1LENR_I2C2EN_Msk

+#define RCC_APB1LENR_I2C3EN_Pos                (23U)

+#define RCC_APB1LENR_I2C3EN_Msk                (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */

+#define RCC_APB1LENR_I2C3EN                    RCC_APB1LENR_I2C3EN_Msk

+#define RCC_APB1LENR_CECEN_Pos                 (27U)

+#define RCC_APB1LENR_CECEN_Msk                 (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */

+#define RCC_APB1LENR_CECEN                     RCC_APB1LENR_CECEN_Msk

+#define RCC_APB1LENR_DAC12EN_Pos               (29U)

+#define RCC_APB1LENR_DAC12EN_Msk               (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */

+#define RCC_APB1LENR_DAC12EN                   RCC_APB1LENR_DAC12EN_Msk

+#define RCC_APB1LENR_UART7EN_Pos               (30U)

+#define RCC_APB1LENR_UART7EN_Msk               (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */

+#define RCC_APB1LENR_UART7EN                   RCC_APB1LENR_UART7EN_Msk

+#define RCC_APB1LENR_UART8EN_Pos               (31U)

+#define RCC_APB1LENR_UART8EN_Msk               (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */

+#define RCC_APB1LENR_UART8EN                   RCC_APB1LENR_UART8EN_Msk

+

+/* Legacy define */

+#define RCC_APB1LENR_HDMICECEN_Pos             RCC_APB1LENR_CECEN_Pos

+#define RCC_APB1LENR_HDMICECEN_Msk             RCC_APB1LENR_CECEN_Msk

+#define RCC_APB1LENR_HDMICECEN                 RCC_APB1LENR_CECEN

+/********************  Bit definition for RCC_APB1HENR register  ******************/

+#define RCC_APB1HENR_CRSEN_Pos                 (1U)

+#define RCC_APB1HENR_CRSEN_Msk                 (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1HENR_CRSEN                     RCC_APB1HENR_CRSEN_Msk

+#define RCC_APB1HENR_SWPMIEN_Pos               (2U)

+#define RCC_APB1HENR_SWPMIEN_Msk               (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1HENR_SWPMIEN                   RCC_APB1HENR_SWPMIEN_Msk

+#define RCC_APB1HENR_OPAMPEN_Pos               (4U)

+#define RCC_APB1HENR_OPAMPEN_Msk               (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1HENR_OPAMPEN                   RCC_APB1HENR_OPAMPEN_Msk

+#define RCC_APB1HENR_MDIOSEN_Pos               (5U)

+#define RCC_APB1HENR_MDIOSEN_Msk               (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1HENR_MDIOSEN                   RCC_APB1HENR_MDIOSEN_Msk

+#define RCC_APB1HENR_FDCANEN_Pos               (8U)

+#define RCC_APB1HENR_FDCANEN_Msk               (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1HENR_FDCANEN                   RCC_APB1HENR_FDCANEN_Msk

+

+/********************  Bit definition for RCC_APB2ENR register  ******************/

+#define RCC_APB2ENR_TIM1EN_Pos                 (0U)

+#define RCC_APB2ENR_TIM1EN_Msk                 (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */

+#define RCC_APB2ENR_TIM1EN                     RCC_APB2ENR_TIM1EN_Msk

+#define RCC_APB2ENR_TIM8EN_Pos                 (1U)

+#define RCC_APB2ENR_TIM8EN_Msk                 (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */

+#define RCC_APB2ENR_TIM8EN                     RCC_APB2ENR_TIM8EN_Msk

+#define RCC_APB2ENR_USART1EN_Pos               (4U)

+#define RCC_APB2ENR_USART1EN_Msk               (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */

+#define RCC_APB2ENR_USART1EN                   RCC_APB2ENR_USART1EN_Msk

+#define RCC_APB2ENR_USART6EN_Pos               (5U)

+#define RCC_APB2ENR_USART6EN_Msk               (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */

+#define RCC_APB2ENR_USART6EN                   RCC_APB2ENR_USART6EN_Msk

+#define RCC_APB2ENR_UART9EN_Pos                (6U)

+#define RCC_APB2ENR_UART9EN_Msk                (0x1UL << RCC_APB2ENR_UART9EN_Pos) /*!< 0x00000040 */

+#define RCC_APB2ENR_UART9EN                    RCC_APB2ENR_UART9EN_Msk

+#define RCC_APB2ENR_USART10EN_Pos              (7U)

+#define RCC_APB2ENR_USART10EN_Msk              (0x1UL << RCC_APB2ENR_USART10EN_Pos) /*!< 0x00000080 */

+#define RCC_APB2ENR_USART10EN                   RCC_APB2ENR_USART10EN_Msk

+#define RCC_APB2ENR_SPI1EN_Pos                 (12U)

+#define RCC_APB2ENR_SPI1EN_Msk                 (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */

+#define RCC_APB2ENR_SPI1EN                     RCC_APB2ENR_SPI1EN_Msk

+#define RCC_APB2ENR_SPI4EN_Pos                 (13U)

+#define RCC_APB2ENR_SPI4EN_Msk                 (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */

+#define RCC_APB2ENR_SPI4EN                     RCC_APB2ENR_SPI4EN_Msk

+#define RCC_APB2ENR_TIM15EN_Pos                (16U)

+#define RCC_APB2ENR_TIM15EN_Msk                (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */

+#define RCC_APB2ENR_TIM15EN                    RCC_APB2ENR_TIM15EN_Msk

+#define RCC_APB2ENR_TIM16EN_Pos                (17U)

+#define RCC_APB2ENR_TIM16EN_Msk                (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */

+#define RCC_APB2ENR_TIM16EN                    RCC_APB2ENR_TIM16EN_Msk

+#define RCC_APB2ENR_TIM17EN_Pos                (18U)

+#define RCC_APB2ENR_TIM17EN_Msk                (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */

+#define RCC_APB2ENR_TIM17EN                    RCC_APB2ENR_TIM17EN_Msk

+#define RCC_APB2ENR_SPI5EN_Pos                 (20U)

+#define RCC_APB2ENR_SPI5EN_Msk                 (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */

+#define RCC_APB2ENR_SPI5EN                     RCC_APB2ENR_SPI5EN_Msk

+#define RCC_APB2ENR_SAI1EN_Pos                 (22U)

+#define RCC_APB2ENR_SAI1EN_Msk                 (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */

+#define RCC_APB2ENR_SAI1EN                     RCC_APB2ENR_SAI1EN_Msk

+#define RCC_APB2ENR_SAI2EN_Pos                 (23U)

+#define RCC_APB2ENR_SAI2EN_Msk                 (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */

+#define RCC_APB2ENR_SAI2EN                     RCC_APB2ENR_SAI2EN_Msk

+#define RCC_APB2ENR_DFSDM1EN_Pos               (30U)

+#define RCC_APB2ENR_DFSDM1EN_Msk               (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x40000000 */

+#define RCC_APB2ENR_DFSDM1EN                   RCC_APB2ENR_DFSDM1EN_Msk

+

+/********************  Bit definition for RCC_APB4ENR register  ******************/

+#define RCC_APB4ENR_SYSCFGEN_Pos               (1U)

+#define RCC_APB4ENR_SYSCFGEN_Msk               (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */

+#define RCC_APB4ENR_SYSCFGEN                   RCC_APB4ENR_SYSCFGEN_Msk

+#define RCC_APB4ENR_LPUART1EN_Pos              (3U)

+#define RCC_APB4ENR_LPUART1EN_Msk              (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */

+#define RCC_APB4ENR_LPUART1EN                  RCC_APB4ENR_LPUART1EN_Msk

+#define RCC_APB4ENR_SPI6EN_Pos                 (5U)

+#define RCC_APB4ENR_SPI6EN_Msk                 (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */

+#define RCC_APB4ENR_SPI6EN                     RCC_APB4ENR_SPI6EN_Msk

+#define RCC_APB4ENR_I2C4EN_Pos                 (7U)

+#define RCC_APB4ENR_I2C4EN_Msk                 (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */

+#define RCC_APB4ENR_I2C4EN                     RCC_APB4ENR_I2C4EN_Msk

+#define RCC_APB4ENR_LPTIM2EN_Pos               (9U)

+#define RCC_APB4ENR_LPTIM2EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */

+#define RCC_APB4ENR_LPTIM2EN                   RCC_APB4ENR_LPTIM2EN_Msk

+#define RCC_APB4ENR_LPTIM3EN_Pos               (10U)

+#define RCC_APB4ENR_LPTIM3EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */

+#define RCC_APB4ENR_LPTIM3EN                   RCC_APB4ENR_LPTIM3EN_Msk

+#define RCC_APB4ENR_DAC2EN_Pos                 (13U)

+#define RCC_APB4ENR_DAC2EN_Msk                 (0x1UL << RCC_APB4ENR_DAC2EN_Pos) /*!< 0x00002000 */

+#define RCC_APB4ENR_DAC2EN                     RCC_APB4ENR_DAC2EN_Msk

+#define RCC_APB4ENR_COMP12EN_Pos               (14U)

+#define RCC_APB4ENR_COMP12EN_Msk               (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */

+#define RCC_APB4ENR_COMP12EN                   RCC_APB4ENR_COMP12EN_Msk

+#define RCC_APB4ENR_VREFEN_Pos                 (15U)

+#define RCC_APB4ENR_VREFEN_Msk                 (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */

+#define RCC_APB4ENR_VREFEN                     RCC_APB4ENR_VREFEN_Msk

+#define RCC_APB4ENR_RTCAPBEN_Pos               (16U)

+#define RCC_APB4ENR_RTCAPBEN_Msk               (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */

+#define RCC_APB4ENR_RTCAPBEN                   RCC_APB4ENR_RTCAPBEN_Msk

+

+#define RCC_APB4ENR_DTSEN_Pos                  (26U)

+#define RCC_APB4ENR_DTSEN_Msk                  (0x1UL << RCC_APB4ENR_DTSEN_Pos) /*!< 0x04000000 */

+#define RCC_APB4ENR_DTSEN                      RCC_APB4ENR_DTSEN_Msk

+#define RCC_APB4ENR_DFSDM2EN_Pos               (27U)

+#define RCC_APB4ENR_DFSDM2EN_Msk               (0x1UL << RCC_APB4ENR_DFSDM2EN_Pos) /*!< 0x08000000 */

+#define RCC_APB4ENR_DFSDM2EN                   RCC_APB4ENR_DFSDM2EN_Msk

+

+/********************  Bit definition for RCC_AHB3RSTR register  ***************/

+#define RCC_AHB3RSTR_MDMARST_Pos               (0U)

+#define RCC_AHB3RSTR_MDMARST_Msk               (0x1UL << RCC_AHB3RSTR_MDMARST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB3RSTR_MDMARST                   RCC_AHB3RSTR_MDMARST_Msk

+#define RCC_AHB3RSTR_DMA2DRST_Pos              (4U)

+#define RCC_AHB3RSTR_DMA2DRST_Msk              (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos)     /*!< 0x00000010 */

+#define RCC_AHB3RSTR_DMA2DRST                  RCC_AHB3RSTR_DMA2DRST_Msk

+#define RCC_AHB3RSTR_JPGDECRST_Pos             (5U)

+#define RCC_AHB3RSTR_JPGDECRST_Msk             (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos)    /*!< 0x00000020 */

+#define RCC_AHB3RSTR_JPGDECRST                 RCC_AHB3RSTR_JPGDECRST_Msk

+#define RCC_AHB3RSTR_FMCRST_Pos                (12U)

+#define RCC_AHB3RSTR_FMCRST_Msk                (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)      /*!< 0x00001000 */

+#define RCC_AHB3RSTR_FMCRST                    RCC_AHB3RSTR_FMCRST_Msk

+#define RCC_AHB3RSTR_OSPI1RST_Pos              (14U)

+#define RCC_AHB3RSTR_OSPI1RST_Msk              (0x1UL << RCC_AHB3RSTR_OSPI1RST_Pos)    /*!< 0x00004000 */

+#define RCC_AHB3RSTR_OSPI1RST                   RCC_AHB3RSTR_OSPI1RST_Msk

+#define RCC_AHB3RSTR_SDMMC1RST_Pos             (16U)

+#define RCC_AHB3RSTR_SDMMC1RST_Msk             (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos)   /*!< 0x00010000 */

+#define RCC_AHB3RSTR_SDMMC1RST                 RCC_AHB3RSTR_SDMMC1RST_Msk

+#define RCC_AHB3RSTR_OSPI2RST_Pos              (19U)

+#define RCC_AHB3RSTR_OSPI2RST_Msk              (0x1UL << RCC_AHB3RSTR_OSPI2RST_Pos)    /*!< 0x00008000 */

+#define RCC_AHB3RSTR_OSPI2RST                  RCC_AHB3RSTR_OSPI2RST_Msk

+#define RCC_AHB3RSTR_IOMNGRRST_Pos             (21U)

+#define RCC_AHB3RSTR_IOMNGRRST_Msk             (0x1UL << RCC_AHB3RSTR_IOMNGRRST_Pos)   /*!< 0x00020000 */

+#define RCC_AHB3RSTR_IOMNGRRST                 RCC_AHB3RSTR_IOMNGRRST_Msk

+#define RCC_AHB3RSTR_GFXMMURST_Pos             (24U)

+#define RCC_AHB3RSTR_GFXMMURST_Msk             (0x1UL << RCC_AHB3RSTR_GFXMMURST_Pos)   /*!< 0x00100000 */

+#define RCC_AHB3RSTR_GFXMMURST                 RCC_AHB3RSTR_GFXMMURST_Msk

+

+

+/********************  Bit definition for RCC_AHB1RSTR register  ***************/

+#define RCC_AHB1RSTR_DMA1RST_Pos               (0U)

+#define RCC_AHB1RSTR_DMA1RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB1RSTR_DMA1RST                   RCC_AHB1RSTR_DMA1RST_Msk

+#define RCC_AHB1RSTR_DMA2RST_Pos               (1U)

+#define RCC_AHB1RSTR_DMA2RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)      /*!< 0x00000002 */

+#define RCC_AHB1RSTR_DMA2RST                   RCC_AHB1RSTR_DMA2RST_Msk

+#define RCC_AHB1RSTR_ADC12RST_Pos              (5U)

+#define RCC_AHB1RSTR_ADC12RST_Msk              (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)     /*!< 0x00000020 */

+#define RCC_AHB1RSTR_ADC12RST                  RCC_AHB1RSTR_ADC12RST_Msk

+#define RCC_AHB1RSTR_CRCRST_Pos                (9U)

+#define RCC_AHB1RSTR_CRCRST_Msk                (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)       /*!< 0x00000200 */

+#define RCC_AHB1RSTR_CRCRST                    RCC_AHB1RSTR_CRCRST_Msk

+#define RCC_AHB1RSTR_USB1OTGHSRST_Pos          (25U)

+#define RCC_AHB1RSTR_USB1OTGHSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */

+#define RCC_AHB1RSTR_USB1OTGHSRST              RCC_AHB1RSTR_USB1OTGHSRST_Msk

+

+/********************  Bit definition for RCC_AHB2RSTR register  ***************/

+#define RCC_AHB2RSTR_DCMI_PSSIRST_Pos          (0U)

+#define RCC_AHB2RSTR_DCMI_PSSIRST_Msk          (0x1UL << RCC_AHB2RSTR_DCMI_PSSIRST_Pos)  /*!< 0x00000001 */

+#define RCC_AHB2RSTR_DCMI_PSSIRST              RCC_AHB2RSTR_DCMI_PSSIRST_Msk

+#define RCC_AHB2RSTR_HSEMRST_Pos               (2U)

+#define RCC_AHB2RSTR_HSEMRST_Msk               (0x1UL << RCC_AHB2RSTR_HSEMRST_Pos)       /*!< 0x00000004 */

+#define RCC_AHB2RSTR_HSEMRST                   RCC_AHB2RSTR_HSEMRST_Msk

+#define RCC_AHB2RSTR_RNGRST_Pos                (6U)

+#define RCC_AHB2RSTR_RNGRST_Msk                (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)        /*!< 0x00000040 */

+#define RCC_AHB2RSTR_RNGRST                    RCC_AHB2RSTR_RNGRST_Msk

+#define RCC_AHB2RSTR_SDMMC2RST_Pos             (9U)

+#define RCC_AHB2RSTR_SDMMC2RST_Msk             (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)     /*!< 0x00000200 */

+#define RCC_AHB2RSTR_SDMMC2RST                 RCC_AHB2RSTR_SDMMC2RST_Msk

+#define RCC_AHB2RSTR_BDMA1RST_Pos              (11U)

+#define RCC_AHB2RSTR_BDMA1RST_Msk              (0x1UL << RCC_AHB2RSTR_BDMA1RST_Pos)      /*!< 0x00000200 */

+#define RCC_AHB2RSTR_BDMA1RST                  RCC_AHB2RSTR_BDMA1RST_Msk

+

+/* Legacy define */

+#define RCC_AHB2RSTR_DCMIRST_Pos               RCC_AHB2RSTR_DCMI_PSSIRST_Pos

+#define RCC_AHB2RSTR_DCMIRST_Msk               RCC_AHB2RSTR_DCMI_PSSIRST_Msk

+#define RCC_AHB2RSTR_DCMIRST                   RCC_AHB2RSTR_DCMI_PSSIRST

+/********************  Bit definition for RCC_AHB4RSTR register  ******************/

+#define RCC_AHB4RSTR_GPIOARST_Pos              (0U)

+#define RCC_AHB4RSTR_GPIOARST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB4RSTR_GPIOARST                  RCC_AHB4RSTR_GPIOARST_Msk

+#define RCC_AHB4RSTR_GPIOBRST_Pos              (1U)

+#define RCC_AHB4RSTR_GPIOBRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)      /*!< 0x00000002 */

+#define RCC_AHB4RSTR_GPIOBRST                  RCC_AHB4RSTR_GPIOBRST_Msk

+#define RCC_AHB4RSTR_GPIOCRST_Pos              (2U)

+#define RCC_AHB4RSTR_GPIOCRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)      /*!< 0x00000004 */

+#define RCC_AHB4RSTR_GPIOCRST                  RCC_AHB4RSTR_GPIOCRST_Msk

+#define RCC_AHB4RSTR_GPIODRST_Pos              (3U)

+#define RCC_AHB4RSTR_GPIODRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)      /*!< 0x00000008 */

+#define RCC_AHB4RSTR_GPIODRST                  RCC_AHB4RSTR_GPIODRST_Msk

+#define RCC_AHB4RSTR_GPIOERST_Pos              (4U)

+#define RCC_AHB4RSTR_GPIOERST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)      /*!< 0x00000010 */

+#define RCC_AHB4RSTR_GPIOERST                  RCC_AHB4RSTR_GPIOERST_Msk

+#define RCC_AHB4RSTR_GPIOFRST_Pos              (5U)

+#define RCC_AHB4RSTR_GPIOFRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)       /*!< 0x00000020 */

+#define RCC_AHB4RSTR_GPIOFRST                  RCC_AHB4RSTR_GPIOFRST_Msk

+#define RCC_AHB4RSTR_GPIOGRST_Pos              (6U)

+#define RCC_AHB4RSTR_GPIOGRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)       /*!< 0x00000040 */

+#define RCC_AHB4RSTR_GPIOGRST                  RCC_AHB4RSTR_GPIOGRST_Msk

+#define RCC_AHB4RSTR_GPIOHRST_Pos              (7U)

+#define RCC_AHB4RSTR_GPIOHRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)       /*!< 0x00000080 */

+#define RCC_AHB4RSTR_GPIOHRST                  RCC_AHB4RSTR_GPIOHRST_Msk

+#define RCC_AHB4RSTR_GPIOIRST_Pos              (8U)

+#define RCC_AHB4RSTR_GPIOIRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos)       /*!< 0x00000100 */

+#define RCC_AHB4RSTR_GPIOIRST                  RCC_AHB4RSTR_GPIOIRST_Msk

+#define RCC_AHB4RSTR_GPIOJRST_Pos              (9U)

+#define RCC_AHB4RSTR_GPIOJRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos)       /*!< 0x00000200 */

+#define RCC_AHB4RSTR_GPIOJRST                  RCC_AHB4RSTR_GPIOJRST_Msk

+#define RCC_AHB4RSTR_GPIOKRST_Pos              (10U)

+#define RCC_AHB4RSTR_GPIOKRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos)       /*!< 0x00000400 */

+#define RCC_AHB4RSTR_GPIOKRST                  RCC_AHB4RSTR_GPIOKRST_Msk

+#define RCC_AHB4RSTR_BDMA2RST_Pos              (21U)

+#define RCC_AHB4RSTR_BDMA2RST_Msk              (0x1UL << RCC_AHB4RSTR_BDMA2RST_Pos)       /*!< 0x00200000 */

+#define RCC_AHB4RSTR_BDMA2RST                   RCC_AHB4RSTR_BDMA2RST_Msk

+

+

+/********************  Bit definition for RCC_APB3RSTR register  ******************/

+#define RCC_APB3RSTR_LTDCRST_Pos               (3U)

+#define RCC_APB3RSTR_LTDCRST_Msk               (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */

+#define RCC_APB3RSTR_LTDCRST                   RCC_APB3RSTR_LTDCRST_Msk

+

+/********************  Bit definition for RCC_APB1LRSTR register  ******************/

+

+#define RCC_APB1LRSTR_TIM2RST_Pos              (0U)

+#define RCC_APB1LRSTR_TIM2RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */

+#define RCC_APB1LRSTR_TIM2RST                  RCC_APB1LRSTR_TIM2RST_Msk

+#define RCC_APB1LRSTR_TIM3RST_Pos              (1U)

+#define RCC_APB1LRSTR_TIM3RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */

+#define RCC_APB1LRSTR_TIM3RST                  RCC_APB1LRSTR_TIM3RST_Msk

+#define RCC_APB1LRSTR_TIM4RST_Pos              (2U)

+#define RCC_APB1LRSTR_TIM4RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */

+#define RCC_APB1LRSTR_TIM4RST                  RCC_APB1LRSTR_TIM4RST_Msk

+#define RCC_APB1LRSTR_TIM5RST_Pos              (3U)

+#define RCC_APB1LRSTR_TIM5RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */

+#define RCC_APB1LRSTR_TIM5RST                  RCC_APB1LRSTR_TIM5RST_Msk

+#define RCC_APB1LRSTR_TIM6RST_Pos              (4U)

+#define RCC_APB1LRSTR_TIM6RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */

+#define RCC_APB1LRSTR_TIM6RST                  RCC_APB1LRSTR_TIM6RST_Msk

+#define RCC_APB1LRSTR_TIM7RST_Pos              (5U)

+#define RCC_APB1LRSTR_TIM7RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */

+#define RCC_APB1LRSTR_TIM7RST                  RCC_APB1LRSTR_TIM7RST_Msk

+#define RCC_APB1LRSTR_TIM12RST_Pos             (6U)

+#define RCC_APB1LRSTR_TIM12RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */

+#define RCC_APB1LRSTR_TIM12RST                 RCC_APB1LRSTR_TIM12RST_Msk

+#define RCC_APB1LRSTR_TIM13RST_Pos             (7U)

+#define RCC_APB1LRSTR_TIM13RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */

+#define RCC_APB1LRSTR_TIM13RST                 RCC_APB1LRSTR_TIM13RST_Msk

+#define RCC_APB1LRSTR_TIM14RST_Pos             (8U)

+#define RCC_APB1LRSTR_TIM14RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */

+#define RCC_APB1LRSTR_TIM14RST                 RCC_APB1LRSTR_TIM14RST_Msk

+#define RCC_APB1LRSTR_LPTIM1RST_Pos            (9U)

+#define RCC_APB1LRSTR_LPTIM1RST_Msk            (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */

+#define RCC_APB1LRSTR_LPTIM1RST                RCC_APB1LRSTR_LPTIM1RST_Msk

+#define RCC_APB1LRSTR_SPI2RST_Pos              (14U)

+#define RCC_APB1LRSTR_SPI2RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */

+#define RCC_APB1LRSTR_SPI2RST                  RCC_APB1LRSTR_SPI2RST_Msk

+#define RCC_APB1LRSTR_SPI3RST_Pos              (15U)

+#define RCC_APB1LRSTR_SPI3RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */

+#define RCC_APB1LRSTR_SPI3RST                  RCC_APB1LRSTR_SPI3RST_Msk

+#define RCC_APB1LRSTR_SPDIFRXRST_Pos           (16U)

+#define RCC_APB1LRSTR_SPDIFRXRST_Msk           (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */

+#define RCC_APB1LRSTR_SPDIFRXRST               RCC_APB1LRSTR_SPDIFRXRST_Msk

+#define RCC_APB1LRSTR_USART2RST_Pos            (17U)

+#define RCC_APB1LRSTR_USART2RST_Msk            (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */

+#define RCC_APB1LRSTR_USART2RST                RCC_APB1LRSTR_USART2RST_Msk

+#define RCC_APB1LRSTR_USART3RST_Pos            (18U)

+#define RCC_APB1LRSTR_USART3RST_Msk            (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */

+#define RCC_APB1LRSTR_USART3RST                RCC_APB1LRSTR_USART3RST_Msk

+#define RCC_APB1LRSTR_UART4RST_Pos             (19U)

+#define RCC_APB1LRSTR_UART4RST_Msk             (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */

+#define RCC_APB1LRSTR_UART4RST                 RCC_APB1LRSTR_UART4RST_Msk

+#define RCC_APB1LRSTR_UART5RST_Pos             (20U)

+#define RCC_APB1LRSTR_UART5RST_Msk             (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */

+#define RCC_APB1LRSTR_UART5RST                 RCC_APB1LRSTR_UART5RST_Msk

+#define RCC_APB1LRSTR_I2C1RST_Pos              (21U)

+#define RCC_APB1LRSTR_I2C1RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */

+#define RCC_APB1LRSTR_I2C1RST                  RCC_APB1LRSTR_I2C1RST_Msk

+#define RCC_APB1LRSTR_I2C2RST_Pos              (22U)

+#define RCC_APB1LRSTR_I2C2RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */

+#define RCC_APB1LRSTR_I2C2RST                  RCC_APB1LRSTR_I2C2RST_Msk

+#define RCC_APB1LRSTR_I2C3RST_Pos              (23U)

+#define RCC_APB1LRSTR_I2C3RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */

+#define RCC_APB1LRSTR_I2C3RST                  RCC_APB1LRSTR_I2C3RST_Msk

+#define RCC_APB1LRSTR_CECRST_Pos               (27U)

+#define RCC_APB1LRSTR_CECRST_Msk               (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */

+#define RCC_APB1LRSTR_CECRST                   RCC_APB1LRSTR_CECRST_Msk

+#define RCC_APB1LRSTR_DAC12RST_Pos             (29U)

+#define RCC_APB1LRSTR_DAC12RST_Msk             (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */

+#define RCC_APB1LRSTR_DAC12RST                 RCC_APB1LRSTR_DAC12RST_Msk

+#define RCC_APB1LRSTR_UART7RST_Pos             (30U)

+#define RCC_APB1LRSTR_UART7RST_Msk             (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */

+#define RCC_APB1LRSTR_UART7RST                 RCC_APB1LRSTR_UART7RST_Msk

+#define RCC_APB1LRSTR_UART8RST_Pos             (31U)

+#define RCC_APB1LRSTR_UART8RST_Msk             (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */

+#define RCC_APB1LRSTR_UART8RST                 RCC_APB1LRSTR_UART8RST_Msk

+

+/* Legacy define */

+#define RCC_APB1LRSTR_HDMICECRST_Pos           RCC_APB1LRSTR_CECRST_Pos

+#define RCC_APB1LRSTR_HDMICECRST_Msk           RCC_APB1LRSTR_CECRST_Msk

+#define RCC_APB1LRSTR_HDMICECRST               RCC_APB1LRSTR_CECRST

+/********************  Bit definition for RCC_APB1HRSTR register  ******************/

+#define RCC_APB1HRSTR_CRSRST_Pos               (1U)

+#define RCC_APB1HRSTR_CRSRST_Msk               (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */

+#define RCC_APB1HRSTR_CRSRST                   RCC_APB1HRSTR_CRSRST_Msk

+#define RCC_APB1HRSTR_SWPMIRST_Pos             (2U)

+#define RCC_APB1HRSTR_SWPMIRST_Msk             (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */

+#define RCC_APB1HRSTR_SWPMIRST                 RCC_APB1HRSTR_SWPMIRST_Msk

+#define RCC_APB1HRSTR_OPAMPRST_Pos             (4U)

+#define RCC_APB1HRSTR_OPAMPRST_Msk             (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */

+#define RCC_APB1HRSTR_OPAMPRST                 RCC_APB1HRSTR_OPAMPRST_Msk

+#define RCC_APB1HRSTR_MDIOSRST_Pos             (5U)

+#define RCC_APB1HRSTR_MDIOSRST_Msk             (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */

+#define RCC_APB1HRSTR_MDIOSRST                 RCC_APB1HRSTR_MDIOSRST_Msk

+#define RCC_APB1HRSTR_FDCANRST_Pos             (8U)

+#define RCC_APB1HRSTR_FDCANRST_Msk             (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */

+#define RCC_APB1HRSTR_FDCANRST                 RCC_APB1HRSTR_FDCANRST_Msk

+

+/********************  Bit definition for RCC_APB2RSTR register  ******************/

+#define RCC_APB2RSTR_TIM1RST_Pos               (0U)

+#define RCC_APB2RSTR_TIM1RST_Msk               (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */

+#define RCC_APB2RSTR_TIM1RST                   RCC_APB2RSTR_TIM1RST_Msk

+#define RCC_APB2RSTR_TIM8RST_Pos               (1U)

+#define RCC_APB2RSTR_TIM8RST_Msk               (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */

+#define RCC_APB2RSTR_TIM8RST                   RCC_APB2RSTR_TIM8RST_Msk

+#define RCC_APB2RSTR_USART1RST_Pos             (4U)

+#define RCC_APB2RSTR_USART1RST_Msk             (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */

+#define RCC_APB2RSTR_USART1RST                 RCC_APB2RSTR_USART1RST_Msk

+#define RCC_APB2RSTR_USART6RST_Pos             (5U)

+#define RCC_APB2RSTR_USART6RST_Msk             (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */

+#define RCC_APB2RSTR_USART6RST                 RCC_APB2RSTR_USART6RST_Msk

+#define RCC_APB2RSTR_UART9RST_Pos              (6U)

+#define RCC_APB2RSTR_UART9RST_Msk              (0x1UL << RCC_APB2RSTR_UART9RST_Pos) /*!< 0x00000040 */

+#define RCC_APB2RSTR_UART9RST                  RCC_APB2RSTR_UART9RST_Msk

+#define RCC_APB2RSTR_USART10RST_Pos            (7U)

+#define RCC_APB2RSTR_USART10RST_Msk            (0x1UL << RCC_APB2RSTR_USART10RST_Pos) /*!< 0x00000080 */

+#define RCC_APB2RSTR_USART10RST                RCC_APB2RSTR_USART10RST_Msk

+#define RCC_APB2RSTR_SPI1RST_Pos               (12U)

+#define RCC_APB2RSTR_SPI1RST_Msk               (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */

+#define RCC_APB2RSTR_SPI1RST                   RCC_APB2RSTR_SPI1RST_Msk

+#define RCC_APB2RSTR_SPI4RST_Pos               (13U)

+#define RCC_APB2RSTR_SPI4RST_Msk               (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */

+#define RCC_APB2RSTR_SPI4RST                   RCC_APB2RSTR_SPI4RST_Msk

+#define RCC_APB2RSTR_TIM15RST_Pos              (16U)

+#define RCC_APB2RSTR_TIM15RST_Msk              (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */

+#define RCC_APB2RSTR_TIM15RST                  RCC_APB2RSTR_TIM15RST_Msk

+#define RCC_APB2RSTR_TIM16RST_Pos              (17U)

+#define RCC_APB2RSTR_TIM16RST_Msk              (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */

+#define RCC_APB2RSTR_TIM16RST                  RCC_APB2RSTR_TIM16RST_Msk

+#define RCC_APB2RSTR_TIM17RST_Pos              (18U)

+#define RCC_APB2RSTR_TIM17RST_Msk              (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */

+#define RCC_APB2RSTR_TIM17RST                  RCC_APB2RSTR_TIM17RST_Msk

+#define RCC_APB2RSTR_SPI5RST_Pos               (20U)

+#define RCC_APB2RSTR_SPI5RST_Msk               (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */

+#define RCC_APB2RSTR_SPI5RST                   RCC_APB2RSTR_SPI5RST_Msk

+#define RCC_APB2RSTR_SAI1RST_Pos               (22U)

+#define RCC_APB2RSTR_SAI1RST_Msk               (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */

+#define RCC_APB2RSTR_SAI1RST                   RCC_APB2RSTR_SAI1RST_Msk

+#define RCC_APB2RSTR_SAI2RST_Pos               (23U)

+#define RCC_APB2RSTR_SAI2RST_Msk               (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */

+#define RCC_APB2RSTR_SAI2RST                   RCC_APB2RSTR_SAI2RST_Msk

+#define RCC_APB2RSTR_DFSDM1RST_Pos             (30U)

+#define RCC_APB2RSTR_DFSDM1RST_Msk             (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */

+#define RCC_APB2RSTR_DFSDM1RST                 RCC_APB2RSTR_DFSDM1RST_Msk

+

+/********************  Bit definition for RCC_APB4RSTR register  ******************/

+#define RCC_APB4RSTR_SYSCFGRST_Pos             (1U)

+#define RCC_APB4RSTR_SYSCFGRST_Msk             (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */

+#define RCC_APB4RSTR_SYSCFGRST                 RCC_APB4RSTR_SYSCFGRST_Msk

+#define RCC_APB4RSTR_LPUART1RST_Pos            (3U)

+#define RCC_APB4RSTR_LPUART1RST_Msk            (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */

+#define RCC_APB4RSTR_LPUART1RST                RCC_APB4RSTR_LPUART1RST_Msk

+#define RCC_APB4RSTR_SPI6RST_Pos               (5U)

+#define RCC_APB4RSTR_SPI6RST_Msk               (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */

+#define RCC_APB4RSTR_SPI6RST                   RCC_APB4RSTR_SPI6RST_Msk

+#define RCC_APB4RSTR_I2C4RST_Pos               (7U)

+#define RCC_APB4RSTR_I2C4RST_Msk               (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */

+#define RCC_APB4RSTR_I2C4RST                   RCC_APB4RSTR_I2C4RST_Msk

+#define RCC_APB4RSTR_LPTIM2RST_Pos             (9U)

+#define RCC_APB4RSTR_LPTIM2RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */

+#define RCC_APB4RSTR_LPTIM2RST                 RCC_APB4RSTR_LPTIM2RST_Msk

+#define RCC_APB4RSTR_LPTIM3RST_Pos             (10U)

+#define RCC_APB4RSTR_LPTIM3RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */

+#define RCC_APB4RSTR_LPTIM3RST                 RCC_APB4RSTR_LPTIM3RST_Msk

+#define RCC_APB4RSTR_DAC2RST_Pos               (13U)

+#define RCC_APB4RSTR_DAC2RST_Msk               (0x1UL << RCC_APB4RSTR_DAC2RST_Pos) /*!< 0x00001000 */

+#define RCC_APB4RSTR_DAC2RST                    RCC_APB4RSTR_DAC2RST_Msk

+#define RCC_APB4RSTR_COMP12RST_Pos             (14U)

+#define RCC_APB4RSTR_COMP12RST_Msk             (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */

+#define RCC_APB4RSTR_COMP12RST                 RCC_APB4RSTR_COMP12RST_Msk

+#define RCC_APB4RSTR_VREFRST_Pos               (15U)

+#define RCC_APB4RSTR_VREFRST_Msk               (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */

+#define RCC_APB4RSTR_VREFRST                   RCC_APB4RSTR_VREFRST_Msk

+

+#define RCC_APB4RSTR_DTSRST_Pos                (26U)

+#define RCC_APB4RSTR_DTSRST_Msk                (0x1UL << RCC_APB4RSTR_DTSRST_Pos) /*!< 0x04000000 */

+#define RCC_APB4RSTR_DTSRST                    RCC_APB4RSTR_DTSRST_Msk

+#define RCC_APB4RSTR_DFSDM2RST_Pos             (27U)

+#define RCC_APB4RSTR_DFSDM2RST_Msk             (0x1UL << RCC_APB4RSTR_DFSDM2RST_Pos) /*!< 0x08000000 */

+#define RCC_APB4RSTR_DFSDM2RST                 RCC_APB4RSTR_DFSDM2RST_Msk

+

+

+/********************  Bit definition for RCC_SRDAMR register  ********************/

+#define RCC_SRDAMR_BDMA2AMEN_Pos               (0U)

+#define RCC_SRDAMR_BDMA2AMEN_Msk               (0x1UL << RCC_SRDAMR_BDMA2AMEN_Pos) /*!< 0x00000001 */

+#define RCC_SRDAMR_BDMA2AMEN                   RCC_SRDAMR_BDMA2AMEN_Msk

+#define RCC_SRDAMR_GPIOAMEN_Pos                (1U)

+#define RCC_SRDAMR_GPIOAMEN_Msk                (0x1UL << RCC_SRDAMR_GPIOAMEN_Pos) /*!< 0x00000001 */

+#define RCC_SRDAMR_GPIOAMEN                    RCC_SRDAMR_GPIOAMEN_Msk

+#define RCC_SRDAMR_LPUART1AMEN_Pos             (3U)

+#define RCC_SRDAMR_LPUART1AMEN_Msk             (0x1UL << RCC_SRDAMR_LPUART1AMEN_Pos) /*!< 0x00000008 */

+#define RCC_SRDAMR_LPUART1AMEN                 RCC_SRDAMR_LPUART1AMEN_Msk

+#define RCC_SRDAMR_SPI6AMEN_Pos                (5U)

+#define RCC_SRDAMR_SPI6AMEN_Msk                (0x1UL << RCC_SRDAMR_SPI6AMEN_Pos) /*!< 0x00000020 */

+#define RCC_SRDAMR_SPI6AMEN                    RCC_SRDAMR_SPI6AMEN_Msk

+#define RCC_SRDAMR_I2C4AMEN_Pos                (7U)

+#define RCC_SRDAMR_I2C4AMEN_Msk                (0x1UL << RCC_SRDAMR_I2C4AMEN_Pos) /*!< 0x00000080 */

+#define RCC_SRDAMR_I2C4AMEN                    RCC_SRDAMR_I2C4AMEN_Msk

+#define RCC_SRDAMR_LPTIM2AMEN_Pos              (9U)

+#define RCC_SRDAMR_LPTIM2AMEN_Msk              (0x1UL << RCC_SRDAMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */

+#define RCC_SRDAMR_LPTIM2AMEN                  RCC_SRDAMR_LPTIM2AMEN_Msk

+#define RCC_SRDAMR_LPTIM3AMEN_Pos              (10U)

+#define RCC_SRDAMR_LPTIM3AMEN_Msk              (0x1UL << RCC_SRDAMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */

+#define RCC_SRDAMR_LPTIM3AMEN                  RCC_SRDAMR_LPTIM3AMEN_Msk

+#define RCC_SRDAMR_DAC2AMEN_Pos                (13U)

+#define RCC_SRDAMR_DAC2AMEN_Msk                (0x1UL << RCC_SRDAMR_DAC2AMEN_Pos) /*!< 0x00004000 */

+#define RCC_SRDAMR_DAC2AMEN                    RCC_SRDAMR_DAC2AMEN_Msk

+#define RCC_SRDAMR_COMP12AMEN_Pos              (14U)

+#define RCC_SRDAMR_COMP12AMEN_Msk              (0x1UL << RCC_SRDAMR_COMP12AMEN_Pos) /*!< 0x00004000 */

+#define RCC_SRDAMR_COMP12AMEN                  RCC_SRDAMR_COMP12AMEN_Msk

+#define RCC_SRDAMR_VREFAMEN_Pos                (15U)

+#define RCC_SRDAMR_VREFAMEN_Msk                (0x1UL << RCC_SRDAMR_VREFAMEN_Pos) /*!< 0x00008000 */

+#define RCC_SRDAMR_VREFAMEN                     RCC_SRDAMR_VREFAMEN_Msk

+#define RCC_SRDAMR_RTCAMEN_Pos                 (16U)

+#define RCC_SRDAMR_RTCAMEN_Msk                 (0x1UL << RCC_SRDAMR_RTCAMEN_Pos) /*!< 0x00010000 */

+#define RCC_SRDAMR_RTCAMEN                     RCC_SRDAMR_RTCAMEN_Msk

+#define RCC_SRDAMR_DTSAMEN_Pos                 (26U)

+#define RCC_SRDAMR_DTSAMEN_Msk                 (0x1UL << RCC_SRDAMR_DTSAMEN_Pos) /*!< 0x04000000 */

+#define RCC_SRDAMR_DTSAMEN                     RCC_SRDAMR_DTSAMEN_Msk

+#define RCC_SRDAMR_DFSDM2AMEN_Pos              (27U)

+#define RCC_SRDAMR_DFSDM2AMEN_Msk              (0x1UL << RCC_SRDAMR_DFSDM2AMEN_Pos) /*!< 0x20000000 */

+#define RCC_SRDAMR_DFSDM2AMEN                   RCC_SRDAMR_DFSDM2AMEN_Msk

+#define RCC_SRDAMR_BKPRAMAMEN_Pos              (28U)

+#define RCC_SRDAMR_BKPRAMAMEN_Msk              (0x1UL << RCC_SRDAMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */

+#define RCC_SRDAMR_BKPRAMAMEN                  RCC_SRDAMR_BKPRAMAMEN_Msk

+#define RCC_SRDAMR_SRDSRAMAMEN_Pos             (29U)

+#define RCC_SRDAMR_SRDSRAMAMEN_Msk             (0x1UL << RCC_SRDAMR_SRDSRAMAMEN_Pos) /*!< 0x20000000 */

+#define RCC_SRDAMR_SRDSRAMAMEN                  RCC_SRDAMR_SRDSRAMAMEN_Msk

+/********************  Bit definition for RCC_CKGAENR register  ********************/

+#define RCC_CKGAENR_AXICKG_Pos                 (0U)

+#define RCC_CKGAENR_AXICKG_Msk                 (0x1UL << RCC_CKGAENR_AXICKG_Pos) /*!< 0x00000001 */

+#define RCC_CKGAENR_AXICKG                      RCC_CKGAENR_AXICKG_Msk

+#define RCC_CKGAENR_AHBCKG_Pos                 (1U)

+#define RCC_CKGAENR_AHBCKG_Msk                 (0x1UL << RCC_CKGAENR_AHBCKG_Pos) /*!< 0x00000002 */

+#define RCC_CKGAENR_AHBCKG                     RCC_CKGAENR_AHBCKG_Msk

+#define RCC_CKGAENR_CPUCKG_Pos                 (2U)

+#define RCC_CKGAENR_CPUCKG_Msk                 (0x1UL << RCC_CKGAENR_CPUCKG_Pos) /*!< 0x00000004 */

+#define RCC_CKGAENR_CPUCKG                     RCC_CKGAENR_CPUCKG_Msk

+#define RCC_CKGAENR_SDMMCCKG_Pos               (3U)

+#define RCC_CKGAENR_SDMMCCKG_Msk               (0x1UL << RCC_CKGAENR_SDMMCCKG_Pos) /*!< 0x00000008 */

+#define RCC_CKGAENR_SDMMCCKG                    RCC_CKGAENR_SDMMCCKG_Msk

+#define RCC_CKGAENR_MDMACKG_Pos                (4U)

+#define RCC_CKGAENR_MDMACKG_Msk                (0x1UL << RCC_CKGAENR_MDMACKG_Pos) /*!< 0x00000010 */

+#define RCC_CKGAENR_MDMACKG                    RCC_CKGAENR_MDMACKG_Msk

+#define RCC_CKGAENR_DMA2DCKG_Pos               (5U)

+#define RCC_CKGAENR_DMA2DCKG_Msk               (0x1UL << RCC_CKGAENR_DMA2DCKG_Pos) /*!< 0x00000020 */

+#define RCC_CKGAENR_DMA2DCKG                    RCC_CKGAENR_DMA2DCKG_Msk

+#define RCC_CKGAENR_LTDCCKG_Pos                (6U)

+#define RCC_CKGAENR_LTDCCKG_Msk                (0x1UL << RCC_CKGAENR_LTDCCKG_Pos) /*!< 0x00000040 */

+#define RCC_CKGAENR_LTDCCKG                    RCC_CKGAENR_LTDCCKG_Msk

+#define RCC_CKGAENR_GFXMMUMCKG_Pos             (7U)

+#define RCC_CKGAENR_GFXMMUMCKG_Msk             (0x1UL << RCC_CKGAENR_GFXMMUMCKG_Pos) /*!< 0x00000080 */

+#define RCC_CKGAENR_GFXMMUMCKG                 RCC_CKGAENR_GFXMMUMCKG_Msk

+#define RCC_CKGAENR_AHB12CKG_Pos               (8U)

+#define RCC_CKGAENR_AHB12CKG_Msk               (0x1UL << RCC_CKGAENR_AHB12CKG_Pos) /*!< 0x00000100 */

+#define RCC_CKGAENR_AHB12CKG                   RCC_CKGAENR_AHB12CKG_Msk

+#define RCC_CKGAENR_AHB34CKG_Pos               (9U)

+#define RCC_CKGAENR_AHB34CKG_Msk               (0x1UL << RCC_CKGAENR_AHB34CKG_Pos) /*!< 0x00000200 */

+#define RCC_CKGAENR_AHB34CKG                   RCC_CKGAENR_AHB34CKG_Msk

+#define RCC_CKGAENR_FLIFTCKG_Pos               (10U)

+#define RCC_CKGAENR_FLIFTCKG_Msk               (0x1UL << RCC_CKGAENR_FLIFTCKG_Pos) /*!< 0x00000400 */

+#define RCC_CKGAENR_FLIFTCKG                   RCC_CKGAENR_FLIFTCKG_Msk

+#define RCC_CKGAENR_OCTOSPI2CKG_Pos            (11U)

+#define RCC_CKGAENR_OCTOSPI2CKG_Msk            (0x1UL << RCC_CKGAENR_OCTOSPI2CKG_Pos) /*!< 0x00000800 */

+#define RCC_CKGAENR_OCTOSPI2CKG                RCC_CKGAENR_OCTOSPI2CKG_Msk

+#define RCC_CKGAENR_FMCCKG_Pos                 (12U)

+#define RCC_CKGAENR_FMCCKG_Msk                 (0x1UL << RCC_CKGAENR_FMCCKG_Pos) /*!< 0x00001000 */

+#define RCC_CKGAENR_FMCCKG                     RCC_CKGAENR_FMCCKG_Msk

+#define RCC_CKGAENR_OCTOSPI1CKG_Pos            (13U)

+#define RCC_CKGAENR_OCTOSPI1CKG_Msk            (0x1UL << RCC_CKGAENR_OCTOSPI1CKG_Pos) /*!< 0x00002000 */

+#define RCC_CKGAENR_OCTOSPI1CKG                RCC_CKGAENR_OCTOSPI1CKG_Msk

+#define RCC_CKGAENR_AXIRAM1CKG_Pos             (14U)

+#define RCC_CKGAENR_AXIRAM1CKG_Msk             (0x1UL << RCC_CKGAENR_AXIRAM1CKG_Pos) /*!< 0x00004000 */

+#define RCC_CKGAENR_AXIRAM1CKG                 RCC_CKGAENR_AXIRAM1CKG_Msk

+#define RCC_CKGAENR_AXIRAM2CKG_Pos             (15U)

+#define RCC_CKGAENR_AXIRAM2CKG_Msk             (0x1UL << RCC_CKGAENR_AXIRAM2CKG_Pos) /*!< 0x00008000 */

+#define RCC_CKGAENR_AXIRAM2CKG                 RCC_CKGAENR_AXIRAM2CKG_Msk

+#define RCC_CKGAENR_AXIRAM3CKG_Pos             (16U)

+#define RCC_CKGAENR_AXIRAM3CKG_Msk             (0x1UL << RCC_CKGAENR_AXIRAM3CKG_Pos) /*!< 0x00010000 */

+#define RCC_CKGAENR_AXIRAM3CKG                 RCC_CKGAENR_AXIRAM3CKG_Msk

+#define RCC_CKGAENR_GFXMMUSCKG_Pos             (17U)

+#define RCC_CKGAENR_GFXMMUSCKG_Msk             (0x1UL << RCC_CKGAENR_GFXMMUSCKG_Pos) /*!< 0x00020000 */

+#define RCC_CKGAENR_GFXMMUSCKG                 RCC_CKGAENR_GFXMMUSCKG_Msk

+#define RCC_CKGAENR_ECCRAMCKG_Pos              (29U)

+#define RCC_CKGAENR_ECCRAMCKG_Msk              (0x1UL << RCC_CKGAENR_ECCRAMCKG_Pos) /*!< 0x20000000 */

+#define RCC_CKGAENR_ECCRAMCKG                  RCC_CKGAENR_ECCRAMCKG_Msk

+#define RCC_CKGAENR_EXTICKG_Pos                (30U)

+#define RCC_CKGAENR_EXTICKG_Msk                (0x1UL << RCC_CKGAENR_EXTICKG_Pos) /*!< 0x40000000 */

+#define RCC_CKGAENR_EXTICKG                    RCC_CKGAENR_EXTICKG_Msk

+#define RCC_CKGAENR_JTAGCKG_Pos                (31U)

+#define RCC_CKGAENR_JTAGCKG_Msk                (0x1UL << RCC_CKGAENR_JTAGCKG_Pos) /*!< 0x80000008 */

+#define RCC_CKGAENR_JTAGCKG                    RCC_CKGAENR_JTAGCKG_Msk

+/********************  Bit definition for RCC_AHB3LPENR register  **************/

+#define RCC_AHB3LPENR_MDMALPEN_Pos             (0U)

+#define RCC_AHB3LPENR_MDMALPEN_Msk             (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos)         /*!< 0x00000001 */

+#define RCC_AHB3LPENR_MDMALPEN                 RCC_AHB3LPENR_MDMALPEN_Msk

+#define RCC_AHB3LPENR_DMA2DLPEN_Pos            (4U)

+#define RCC_AHB3LPENR_DMA2DLPEN_Msk            (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos)        /*!< 0x00000010 */

+#define RCC_AHB3LPENR_DMA2DLPEN                RCC_AHB3LPENR_DMA2DLPEN_Msk

+#define RCC_AHB3LPENR_JPGDECLPEN_Pos           (5U)

+#define RCC_AHB3LPENR_JPGDECLPEN_Msk           (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos)       /*!< 0x00000020 */

+#define RCC_AHB3LPENR_JPGDECLPEN               RCC_AHB3LPENR_JPGDECLPEN_Msk

+#define RCC_AHB3LPENR_FLASHLPEN_Pos            (8U)

+#define RCC_AHB3LPENR_FLASHLPEN_Msk            (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos)        /*!< 0x00000100 */

+#define RCC_AHB3LPENR_FLASHLPEN                RCC_AHB3LPENR_FLASHLPEN_Msk

+#define RCC_AHB3LPENR_FMCLPEN_Pos              (12U)

+#define RCC_AHB3LPENR_FMCLPEN_Msk              (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)          /*!< 0x00001000 */

+#define RCC_AHB3LPENR_FMCLPEN                  RCC_AHB3LPENR_FMCLPEN_Msk

+#define RCC_AHB3LPENR_OSPI1LPEN_Pos            (14U)

+#define RCC_AHB3LPENR_OSPI1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_OSPI1LPEN_Pos)        /*!< 0x00004000 */

+#define RCC_AHB3LPENR_OSPI1LPEN                RCC_AHB3LPENR_OSPI1LPEN_Msk

+#define RCC_AHB3LPENR_SDMMC1LPEN_Pos           (16U)

+#define RCC_AHB3LPENR_SDMMC1LPEN_Msk           (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos)       /*!< 0x00010000 */

+#define RCC_AHB3LPENR_SDMMC1LPEN               RCC_AHB3LPENR_SDMMC1LPEN_Msk

+#define RCC_AHB3LPENR_OSPI2LPEN_Pos            (19U)

+#define RCC_AHB3LPENR_OSPI2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_OSPI2LPEN_Pos)        /*!< 0x00080000 */

+#define RCC_AHB3LPENR_OSPI2LPEN                RCC_AHB3LPENR_OSPI2LPEN_Msk

+#define RCC_AHB3LPENR_IOMNGRLPEN_Pos           (21U)

+#define RCC_AHB3LPENR_IOMNGRLPEN_Msk           (0x1UL << RCC_AHB3LPENR_IOMNGRLPEN_Pos)       /*!< 0x00200000 */

+#define RCC_AHB3LPENR_IOMNGRLPEN               RCC_AHB3LPENR_IOMNGRLPEN_Msk

+#define RCC_AHB3LPENR_GFXMMULPEN_Pos           (24U)

+#define RCC_AHB3LPENR_GFXMMULPEN_Msk           (0x1UL << RCC_AHB3LPENR_GFXMMULPEN_Pos)       /*!< 0x01000000 */

+#define RCC_AHB3LPENR_GFXMMULPEN               RCC_AHB3LPENR_GFXMMULPEN_Msk

+#define RCC_AHB3LPENR_AXISRAM2LPEN_Pos         (26U)

+#define RCC_AHB3LPENR_AXISRAM2LPEN_Msk         (0x1UL << RCC_AHB3LPENR_AXISRAM2LPEN_Pos)     /*!< 0x02000000 */

+#define RCC_AHB3LPENR_AXISRAM2LPEN             RCC_AHB3LPENR_AXISRAM2LPEN_Msk

+#define RCC_AHB3LPENR_AXISRAM3LPEN_Pos         (27U)

+#define RCC_AHB3LPENR_AXISRAM3LPEN_Msk         (0x1UL << RCC_AHB3LPENR_AXISRAM3LPEN_Pos)     /*!< 0x04000000 */

+#define RCC_AHB3LPENR_AXISRAM3LPEN             RCC_AHB3LPENR_AXISRAM3LPEN_Msk

+#define RCC_AHB3LPENR_DTCM1LPEN_Pos            (28U)

+#define RCC_AHB3LPENR_DTCM1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos)        /*!< 0x10000000 */

+#define RCC_AHB3LPENR_DTCM1LPEN                RCC_AHB3LPENR_DTCM1LPEN_Msk

+#define RCC_AHB3LPENR_DTCM2LPEN_Pos            (29U)

+#define RCC_AHB3LPENR_DTCM2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos)        /*!< 0x20000000 */

+#define RCC_AHB3LPENR_DTCM2LPEN                RCC_AHB3LPENR_DTCM2LPEN_Msk

+#define RCC_AHB3LPENR_ITCMLPEN_Pos             (30U)

+#define RCC_AHB3LPENR_ITCMLPEN_Msk             (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos)         /*!< 0x40000000 */

+#define RCC_AHB3LPENR_ITCMLPEN                 RCC_AHB3LPENR_ITCMLPEN_Msk

+#define RCC_AHB3LPENR_AXISRAM1LPEN_Pos         (31U)

+#define RCC_AHB3LPENR_AXISRAM1LPEN_Msk         (0x1UL << RCC_AHB3LPENR_AXISRAM1LPEN_Pos)      /*!< 0x80000000 */

+#define RCC_AHB3LPENR_AXISRAM1LPEN             RCC_AHB3LPENR_AXISRAM1LPEN_Msk

+

+

+/* Legacy define */

+#define RCC_AHB3LPENR_AXISRAMLPEN_Pos          RCC_AHB3LPENR_AXISRAM1LPEN_Pos

+#define RCC_AHB3LPENR_AXISRAMLPEN_Msk          RCC_AHB3LPENR_AXISRAM1LPEN_Msk

+#define RCC_AHB3LPENR_AXISRAMLPEN              RCC_AHB3LPENR_AXISRAM1LPEN

+/********************  Bit definition for RCC_AHB1LPENR register  ***************/

+#define RCC_AHB1LPENR_DMA1LPEN_Pos             (0U)

+#define RCC_AHB1LPENR_DMA1LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB1LPENR_DMA1LPEN                 RCC_AHB1LPENR_DMA1LPEN_Msk

+#define RCC_AHB1LPENR_DMA2LPEN_Pos             (1U)

+#define RCC_AHB1LPENR_DMA2LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */

+#define RCC_AHB1LPENR_DMA2LPEN                 RCC_AHB1LPENR_DMA2LPEN_Msk

+#define RCC_AHB1LPENR_ADC12LPEN_Pos            (5U)

+#define RCC_AHB1LPENR_ADC12LPEN_Msk            (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB1LPENR_ADC12LPEN                RCC_AHB1LPENR_ADC12LPEN_Msk

+#define RCC_AHB1LPENR_CRCLPEN_Pos              (9U)

+#define RCC_AHB1LPENR_CRCLPEN_Msk              (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00008000 */

+#define RCC_AHB1LPENR_CRCLPEN                   RCC_AHB1LPENR_CRCLPEN_Msk

+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos        (25U)

+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */

+#define RCC_AHB1LPENR_USB1OTGHSLPEN            RCC_AHB1LPENR_USB1OTGHSLPEN_Msk

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos    (26U)

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN        RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk

+

+/********************  Bit definition for RCC_AHB2LPENR register  ***************/

+#define RCC_AHB2LPENR_DCMI_PSSILPEN_Pos        (0U)

+#define RCC_AHB2LPENR_DCMI_PSSILPEN_Msk        (0x1UL << RCC_AHB2LPENR_DCMI_PSSILPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB2LPENR_DCMI_PSSILPEN            RCC_AHB2LPENR_DCMI_PSSILPEN_Msk

+#define RCC_AHB2LPENR_RNGLPEN_Pos              (6U)

+#define RCC_AHB2LPENR_RNGLPEN_Msk              (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */

+#define RCC_AHB2LPENR_RNGLPEN                  RCC_AHB2LPENR_RNGLPEN_Msk

+#define RCC_AHB2LPENR_SDMMC2LPEN_Pos           (9U)

+#define RCC_AHB2LPENR_SDMMC2LPEN_Msk           (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */

+#define RCC_AHB2LPENR_SDMMC2LPEN               RCC_AHB2LPENR_SDMMC2LPEN_Msk

+#define RCC_AHB2LPENR_BDMA1LPEN_Pos            (11U)

+#define RCC_AHB2LPENR_BDMA1LPEN_Msk            (0x1UL << RCC_AHB2LPENR_BDMA1LPEN_Pos)   /*!< 0x00000800 */

+#define RCC_AHB2LPENR_BDMA1LPEN                RCC_AHB2LPENR_BDMA1LPEN_Msk

+#define RCC_AHB2LPENR_AHBSRAM1LPEN_Pos         (29U)

+#define RCC_AHB2LPENR_AHBSRAM1LPEN_Msk         (0x1UL << RCC_AHB2LPENR_AHBSRAM1LPEN_Pos) /*!< 0x20000000 */

+#define RCC_AHB2LPENR_AHBSRAM1LPEN             RCC_AHB2LPENR_AHBSRAM1LPEN_Msk

+#define RCC_AHB2LPENR_AHBSRAM2LPEN_Pos         (30U)

+#define RCC_AHB2LPENR_AHBSRAM2LPEN_Msk         (0x1UL << RCC_AHB2LPENR_AHBSRAM2LPEN_Pos) /*!< 0x40000000 */

+#define RCC_AHB2LPENR_AHBSRAM2LPEN             RCC_AHB2LPENR_AHBSRAM2LPEN_Msk

+

+/* Legacy define */

+#define RCC_AHB2LPENR_DFSDMDMALPEN_Pos         RCC_AHB2LPENR_BDMA1LPEN_Pos

+#define RCC_AHB2LPENR_DFSDMDMALPEN_Msk         RCC_AHB2LPENR_BDMA1LPEN_Msk

+#define RCC_AHB2LPENR_DFSDMDMALPEN             RCC_AHB2LPENR_BDMA1LPEN

+#define RCC_AHB2LPENR_DCMILPEN_Pos             RCC_AHB2LPENR_DCMI_PSSILPEN_Pos

+#define RCC_AHB2LPENR_DCMILPEN_Msk             RCC_AHB2LPENR_DCMI_PSSILPEN_Msk

+#define RCC_AHB2LPENR_DCMILPEN                 RCC_AHB2LPENR_DCMI_PSSILPEN

+

+/********************  Bit definition for RCC_AHB4LPENR register  ******************/

+#define RCC_AHB4LPENR_GPIOALPEN_Pos            (0U)

+#define RCC_AHB4LPENR_GPIOALPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB4LPENR_GPIOALPEN                RCC_AHB4LPENR_GPIOALPEN_Msk

+#define RCC_AHB4LPENR_GPIOBLPEN_Pos            (1U)

+#define RCC_AHB4LPENR_GPIOBLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */

+#define RCC_AHB4LPENR_GPIOBLPEN                RCC_AHB4LPENR_GPIOBLPEN_Msk

+#define RCC_AHB4LPENR_GPIOCLPEN_Pos            (2U)

+#define RCC_AHB4LPENR_GPIOCLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */

+#define RCC_AHB4LPENR_GPIOCLPEN                RCC_AHB4LPENR_GPIOCLPEN_Msk

+#define RCC_AHB4LPENR_GPIODLPEN_Pos            (3U)

+#define RCC_AHB4LPENR_GPIODLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */

+#define RCC_AHB4LPENR_GPIODLPEN                RCC_AHB4LPENR_GPIODLPEN_Msk

+#define RCC_AHB4LPENR_GPIOELPEN_Pos            (4U)

+#define RCC_AHB4LPENR_GPIOELPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */

+#define RCC_AHB4LPENR_GPIOELPEN                RCC_AHB4LPENR_GPIOELPEN_Msk

+#define RCC_AHB4LPENR_GPIOFLPEN_Pos            (5U)

+#define RCC_AHB4LPENR_GPIOFLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB4LPENR_GPIOFLPEN                RCC_AHB4LPENR_GPIOFLPEN_Msk

+#define RCC_AHB4LPENR_GPIOGLPEN_Pos            (6U)

+#define RCC_AHB4LPENR_GPIOGLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */

+#define RCC_AHB4LPENR_GPIOGLPEN                RCC_AHB4LPENR_GPIOGLPEN_Msk

+#define RCC_AHB4LPENR_GPIOHLPEN_Pos            (7U)

+#define RCC_AHB4LPENR_GPIOHLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */

+#define RCC_AHB4LPENR_GPIOHLPEN                RCC_AHB4LPENR_GPIOHLPEN_Msk

+#define RCC_AHB4LPENR_GPIOILPEN_Pos            (8U)

+#define RCC_AHB4LPENR_GPIOILPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */

+#define RCC_AHB4LPENR_GPIOILPEN                RCC_AHB4LPENR_GPIOILPEN_Msk

+#define RCC_AHB4LPENR_GPIOJLPEN_Pos            (9U)

+#define RCC_AHB4LPENR_GPIOJLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */

+#define RCC_AHB4LPENR_GPIOJLPEN                RCC_AHB4LPENR_GPIOJLPEN_Msk

+#define RCC_AHB4LPENR_GPIOKLPEN_Pos            (10U)

+#define RCC_AHB4LPENR_GPIOKLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */

+#define RCC_AHB4LPENR_GPIOKLPEN                RCC_AHB4LPENR_GPIOKLPEN_Msk

+#define RCC_AHB4LPENR_BDMA2LPEN_Pos             (21U)

+#define RCC_AHB4LPENR_BDMA2LPEN_Msk             (0x1UL << RCC_AHB4LPENR_BDMA2LPEN_Pos) /*!< 0x00200000 */

+#define RCC_AHB4LPENR_BDMA2LPEN                 RCC_AHB4LPENR_BDMA2LPEN_Msk

+#define RCC_AHB4LPENR_BKPRAMLPEN_Pos           (28U)

+#define RCC_AHB4LPENR_BKPRAMLPEN_Msk           (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */

+#define RCC_AHB4LPENR_BKPRAMLPEN               RCC_AHB4LPENR_BKPRAMLPEN_Msk

+#define RCC_AHB4LPENR_SRDSRAMLPEN_Pos          (29U)

+#define RCC_AHB4LPENR_SRDSRAMLPEN_Msk          (0x1UL << RCC_AHB4LPENR_SRDSRAMLPEN_Pos) /*!< 0x20000000 */

+#define RCC_AHB4LPENR_SRDSRAMLPEN              RCC_AHB4LPENR_SRDSRAMLPEN_Msk

+

+/********************  Bit definition for RCC_APB3LPENR register  ******************/

+#define RCC_APB3LPENR_LTDCLPEN_Pos             (3U)

+#define RCC_APB3LPENR_LTDCLPEN_Msk             (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB3LPENR_LTDCLPEN                 RCC_APB3LPENR_LTDCLPEN_Msk

+#define RCC_APB3LPENR_WWDGLPEN_Pos             (6U)

+#define RCC_APB3LPENR_WWDGLPEN_Msk             (0x1UL << RCC_APB3LPENR_WWDGLPEN_Pos)  /*!< 0x00000040 */

+#define RCC_APB3LPENR_WWDGLPEN                 RCC_APB3LPENR_WWDGLPEN_Msk

+

+/* Legacy define */

+#define RCC_APB3LPENR_WWDG1LPEN_Pos            RCC_APB3LPENR_WWDGLPEN_Pos

+#define RCC_APB3LPENR_WWDG1LPEN_Msk            RCC_APB3LPENR_WWDGLPEN_Msk

+#define RCC_APB3LPENR_WWDG1LPEN                RCC_APB3LPENR_WWDGLPEN

+/********************  Bit definition for RCC_APB1LLPENR register  ******************/

+

+#define RCC_APB1LLPENR_TIM2LPEN_Pos            (0U)

+#define RCC_APB1LLPENR_TIM2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */

+#define RCC_APB1LLPENR_TIM2LPEN                RCC_APB1LLPENR_TIM2LPEN_Msk

+#define RCC_APB1LLPENR_TIM3LPEN_Pos            (1U)

+#define RCC_APB1LLPENR_TIM3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1LLPENR_TIM3LPEN                RCC_APB1LLPENR_TIM3LPEN_Msk

+#define RCC_APB1LLPENR_TIM4LPEN_Pos            (2U)

+#define RCC_APB1LLPENR_TIM4LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1LLPENR_TIM4LPEN                RCC_APB1LLPENR_TIM4LPEN_Msk

+#define RCC_APB1LLPENR_TIM5LPEN_Pos            (3U)

+#define RCC_APB1LLPENR_TIM5LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB1LLPENR_TIM5LPEN                RCC_APB1LLPENR_TIM5LPEN_Msk

+#define RCC_APB1LLPENR_TIM6LPEN_Pos            (4U)

+#define RCC_APB1LLPENR_TIM6LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1LLPENR_TIM6LPEN                RCC_APB1LLPENR_TIM6LPEN_Msk

+#define RCC_APB1LLPENR_TIM7LPEN_Pos            (5U)

+#define RCC_APB1LLPENR_TIM7LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1LLPENR_TIM7LPEN                RCC_APB1LLPENR_TIM7LPEN_Msk

+#define RCC_APB1LLPENR_TIM12LPEN_Pos           (6U)

+#define RCC_APB1LLPENR_TIM12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */

+#define RCC_APB1LLPENR_TIM12LPEN               RCC_APB1LLPENR_TIM12LPEN_Msk

+#define RCC_APB1LLPENR_TIM13LPEN_Pos           (7U)

+#define RCC_APB1LLPENR_TIM13LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB1LLPENR_TIM13LPEN               RCC_APB1LLPENR_TIM13LPEN_Msk

+#define RCC_APB1LLPENR_TIM14LPEN_Pos           (8U)

+#define RCC_APB1LLPENR_TIM14LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1LLPENR_TIM14LPEN               RCC_APB1LLPENR_TIM14LPEN_Msk

+#define RCC_APB1LLPENR_LPTIM1LPEN_Pos          (9U)

+#define RCC_APB1LLPENR_LPTIM1LPEN_Msk          (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */

+#define RCC_APB1LLPENR_LPTIM1LPEN              RCC_APB1LLPENR_LPTIM1LPEN_Msk

+

+

+#define RCC_APB1LLPENR_SPI2LPEN_Pos            (14U)

+#define RCC_APB1LLPENR_SPI2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */

+#define RCC_APB1LLPENR_SPI2LPEN                RCC_APB1LLPENR_SPI2LPEN_Msk

+#define RCC_APB1LLPENR_SPI3LPEN_Pos            (15U)

+#define RCC_APB1LLPENR_SPI3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */

+#define RCC_APB1LLPENR_SPI3LPEN                RCC_APB1LLPENR_SPI3LPEN_Msk

+#define RCC_APB1LLPENR_SPDIFRXLPEN_Pos         (16U)

+#define RCC_APB1LLPENR_SPDIFRXLPEN_Msk         (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB1LLPENR_SPDIFRXLPEN             RCC_APB1LLPENR_SPDIFRXLPEN_Msk

+#define RCC_APB1LLPENR_USART2LPEN_Pos          (17U)

+#define RCC_APB1LLPENR_USART2LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */

+#define RCC_APB1LLPENR_USART2LPEN              RCC_APB1LLPENR_USART2LPEN_Msk

+#define RCC_APB1LLPENR_USART3LPEN_Pos          (18U)

+#define RCC_APB1LLPENR_USART3LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */

+#define RCC_APB1LLPENR_USART3LPEN              RCC_APB1LLPENR_USART3LPEN_Msk

+#define RCC_APB1LLPENR_UART4LPEN_Pos           (19U)

+#define RCC_APB1LLPENR_UART4LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */

+#define RCC_APB1LLPENR_UART4LPEN               RCC_APB1LLPENR_UART4LPEN_Msk

+#define RCC_APB1LLPENR_UART5LPEN_Pos           (20U)

+#define RCC_APB1LLPENR_UART5LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */

+#define RCC_APB1LLPENR_UART5LPEN               RCC_APB1LLPENR_UART5LPEN_Msk

+#define RCC_APB1LLPENR_I2C1LPEN_Pos            (21U)

+#define RCC_APB1LLPENR_I2C1LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */

+#define RCC_APB1LLPENR_I2C1LPEN                RCC_APB1LLPENR_I2C1LPEN_Msk

+#define RCC_APB1LLPENR_I2C2LPEN_Pos            (22U)

+#define RCC_APB1LLPENR_I2C2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */

+#define RCC_APB1LLPENR_I2C2LPEN                RCC_APB1LLPENR_I2C2LPEN_Msk

+#define RCC_APB1LLPENR_I2C3LPEN_Pos            (23U)

+#define RCC_APB1LLPENR_I2C3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */

+#define RCC_APB1LLPENR_I2C3LPEN                RCC_APB1LLPENR_I2C3LPEN_Msk

+#define RCC_APB1LLPENR_CECLPEN_Pos             (27U)

+#define RCC_APB1LLPENR_CECLPEN_Msk             (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */

+#define RCC_APB1LLPENR_CECLPEN                 RCC_APB1LLPENR_CECLPEN_Msk

+#define RCC_APB1LLPENR_DAC12LPEN_Pos           (29U)

+#define RCC_APB1LLPENR_DAC12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */

+#define RCC_APB1LLPENR_DAC12LPEN               RCC_APB1LLPENR_DAC12LPEN_Msk

+#define RCC_APB1LLPENR_UART7LPEN_Pos           (30U)

+#define RCC_APB1LLPENR_UART7LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */

+#define RCC_APB1LLPENR_UART7LPEN               RCC_APB1LLPENR_UART7LPEN_Msk

+#define RCC_APB1LLPENR_UART8LPEN_Pos           (31U)

+#define RCC_APB1LLPENR_UART8LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */

+#define RCC_APB1LLPENR_UART8LPEN               RCC_APB1LLPENR_UART8LPEN_Msk

+

+/* Legacy define */

+#define RCC_APB1LLPENR_HDMICECEN_Pos           RCC_APB1LLPENR_CECLPEN_Pos

+#define RCC_APB1LLPENR_HDMICECEN_Msk           RCC_APB1LLPENR_CECLPEN_Msk

+#define RCC_APB1LLPENR_HDMICECEN               RCC_APB1LLPENR_CECLPEN

+/********************  Bit definition for RCC_APB1HLPENR register  ******************/

+#define RCC_APB1HLPENR_CRSLPEN_Pos             (1U)

+#define RCC_APB1HLPENR_CRSLPEN_Msk             (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1HLPENR_CRSLPEN                 RCC_APB1HLPENR_CRSLPEN_Msk

+#define RCC_APB1HLPENR_SWPMILPEN_Pos           (2U)

+#define RCC_APB1HLPENR_SWPMILPEN_Msk           (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1HLPENR_SWPMILPEN               RCC_APB1HLPENR_SWPMILPEN_Msk

+#define RCC_APB1HLPENR_OPAMPLPEN_Pos           (4U)

+#define RCC_APB1HLPENR_OPAMPLPEN_Msk           (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1HLPENR_OPAMPLPEN               RCC_APB1HLPENR_OPAMPLPEN_Msk

+#define RCC_APB1HLPENR_MDIOSLPEN_Pos           (5U)

+#define RCC_APB1HLPENR_MDIOSLPEN_Msk           (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1HLPENR_MDIOSLPEN               RCC_APB1HLPENR_MDIOSLPEN_Msk

+#define RCC_APB1HLPENR_FDCANLPEN_Pos           (8U)

+#define RCC_APB1HLPENR_FDCANLPEN_Msk           (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1HLPENR_FDCANLPEN               RCC_APB1HLPENR_FDCANLPEN_Msk

+

+/********************  Bit definition for RCC_APB2LPENR register  ******************/

+#define RCC_APB2LPENR_TIM1LPEN_Pos             (0U)

+#define RCC_APB2LPENR_TIM1LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */

+#define RCC_APB2LPENR_TIM1LPEN                 RCC_APB2LPENR_TIM1LPEN_Msk

+#define RCC_APB2LPENR_TIM8LPEN_Pos             (1U)

+#define RCC_APB2LPENR_TIM8LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB2LPENR_TIM8LPEN                 RCC_APB2LPENR_TIM8LPEN_Msk

+#define RCC_APB2LPENR_USART1LPEN_Pos           (4U)

+#define RCC_APB2LPENR_USART1LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB2LPENR_USART1LPEN               RCC_APB2LPENR_USART1LPEN_Msk

+#define RCC_APB2LPENR_USART6LPEN_Pos           (5U)

+#define RCC_APB2LPENR_USART6LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB2LPENR_USART6LPEN               RCC_APB2LPENR_USART6LPEN_Msk

+#define RCC_APB2LPENR_UART9LPEN_Pos            (6U)

+#define RCC_APB2LPENR_UART9LPEN_Msk            (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos) /*!< 0x00000040 */

+#define RCC_APB2LPENR_UART9LPEN                 RCC_APB2LPENR_UART9LPEN_Msk

+#define RCC_APB2LPENR_USART10LPEN_Pos          (7U)

+#define RCC_APB2LPENR_USART10LPEN_Msk          (0x1UL << RCC_APB2LPENR_USART10LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB2LPENR_USART10LPEN               RCC_APB2LPENR_USART10LPEN_Msk

+#define RCC_APB2LPENR_SPI1LPEN_Pos             (12U)

+#define RCC_APB2LPENR_SPI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */

+#define RCC_APB2LPENR_SPI1LPEN                 RCC_APB2LPENR_SPI1LPEN_Msk

+#define RCC_APB2LPENR_SPI4LPEN_Pos             (13U)

+#define RCC_APB2LPENR_SPI4LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */

+#define RCC_APB2LPENR_SPI4LPEN                 RCC_APB2LPENR_SPI4LPEN_Msk

+#define RCC_APB2LPENR_TIM15LPEN_Pos            (16U)

+#define RCC_APB2LPENR_TIM15LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB2LPENR_TIM15LPEN                RCC_APB2LPENR_TIM15LPEN_Msk

+#define RCC_APB2LPENR_TIM16LPEN_Pos            (17U)

+#define RCC_APB2LPENR_TIM16LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */

+#define RCC_APB2LPENR_TIM16LPEN                RCC_APB2LPENR_TIM16LPEN_Msk

+#define RCC_APB2LPENR_TIM17LPEN_Pos            (18U)

+#define RCC_APB2LPENR_TIM17LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */

+#define RCC_APB2LPENR_TIM17LPEN                RCC_APB2LPENR_TIM17LPEN_Msk

+#define RCC_APB2LPENR_SPI5LPEN_Pos             (20U)

+#define RCC_APB2LPENR_SPI5LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */

+#define RCC_APB2LPENR_SPI5LPEN                 RCC_APB2LPENR_SPI5LPEN_Msk

+#define RCC_APB2LPENR_SAI1LPEN_Pos             (22U)

+#define RCC_APB2LPENR_SAI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */

+#define RCC_APB2LPENR_SAI1LPEN                 RCC_APB2LPENR_SAI1LPEN_Msk

+#define RCC_APB2LPENR_SAI2LPEN_Pos             (23U)

+#define RCC_APB2LPENR_SAI2LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */

+#define RCC_APB2LPENR_SAI2LPEN                 RCC_APB2LPENR_SAI2LPEN_Msk

+#define RCC_APB2LPENR_DFSDM1LPEN_Pos           (30U)

+#define RCC_APB2LPENR_DFSDM1LPEN_Msk           (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x40000000 */

+#define RCC_APB2LPENR_DFSDM1LPEN               RCC_APB2LPENR_DFSDM1LPEN_Msk

+

+/********************  Bit definition for RCC_APB4LPENR register  ******************/

+#define RCC_APB4LPENR_SYSCFGLPEN_Pos           (1U)

+#define RCC_APB4LPENR_SYSCFGLPEN_Msk           (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB4LPENR_SYSCFGLPEN               RCC_APB4LPENR_SYSCFGLPEN_Msk

+#define RCC_APB4LPENR_LPUART1LPEN_Pos          (3U)

+#define RCC_APB4LPENR_LPUART1LPEN_Msk          (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB4LPENR_LPUART1LPEN              RCC_APB4LPENR_LPUART1LPEN_Msk

+#define RCC_APB4LPENR_SPI6LPEN_Pos             (5U)

+#define RCC_APB4LPENR_SPI6LPEN_Msk             (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB4LPENR_SPI6LPEN                 RCC_APB4LPENR_SPI6LPEN_Msk

+#define RCC_APB4LPENR_I2C4LPEN_Pos             (7U)

+#define RCC_APB4LPENR_I2C4LPEN_Msk             (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB4LPENR_I2C4LPEN                 RCC_APB4LPENR_I2C4LPEN_Msk

+#define RCC_APB4LPENR_LPTIM2LPEN_Pos           (9U)

+#define RCC_APB4LPENR_LPTIM2LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */

+#define RCC_APB4LPENR_LPTIM2LPEN               RCC_APB4LPENR_LPTIM2LPEN_Msk

+#define RCC_APB4LPENR_LPTIM3LPEN_Pos           (10U)

+#define RCC_APB4LPENR_LPTIM3LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */

+#define RCC_APB4LPENR_LPTIM3LPEN               RCC_APB4LPENR_LPTIM3LPEN_Msk

+#define RCC_APB4LPENR_DAC2LPEN_Pos             (13U)

+#define RCC_APB4LPENR_DAC2LPEN_Msk             (0x1UL << RCC_APB4LPENR_DAC2LPEN_Pos) /*!< 0x00002000 */

+#define RCC_APB4LPENR_DAC2LPEN                 RCC_APB4LPENR_DAC2LPEN_Msk

+#define RCC_APB4LPENR_COMP12LPEN_Pos           (14U)

+#define RCC_APB4LPENR_COMP12LPEN_Msk           (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */

+#define RCC_APB4LPENR_COMP12LPEN               RCC_APB4LPENR_COMP12LPEN_Msk

+#define RCC_APB4LPENR_VREFLPEN_Pos             (15U)

+#define RCC_APB4LPENR_VREFLPEN_Msk             (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */

+#define RCC_APB4LPENR_VREFLPEN                 RCC_APB4LPENR_VREFLPEN_Msk

+#define RCC_APB4LPENR_RTCAPBLPEN_Pos           (16U)

+#define RCC_APB4LPENR_RTCAPBLPEN_Msk           (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB4LPENR_RTCAPBLPEN               RCC_APB4LPENR_RTCAPBLPEN_Msk

+

+#define RCC_APB4LPENR_DTSLPEN_Pos              (26U)

+#define RCC_APB4LPENR_DTSLPEN_Msk              (0x1UL << RCC_APB4LPENR_DTSLPEN_Pos) /*!< 0x04000000 */

+#define RCC_APB4LPENR_DTSLPEN                  RCC_APB4LPENR_DTSLPEN_Msk

+#define RCC_APB4LPENR_DFSDM2LPEN_Pos           (27U)

+#define RCC_APB4LPENR_DFSDM2LPEN_Msk           (0x1UL << RCC_APB4LPENR_DFSDM2LPEN_Pos) /*!< 0x08000000 */

+#define RCC_APB4LPENR_DFSDM2LPEN                RCC_APB4LPENR_DFSDM2LPEN_Msk

+

+/********************  Bit definition for RCC_RSR register  *******************/

+#define RCC_RSR_RMVF_Pos                       (16U)

+#define RCC_RSR_RMVF_Msk                       (0x1UL << RCC_RSR_RMVF_Pos)     /*!< 0x00010000 */

+#define RCC_RSR_RMVF                           RCC_RSR_RMVF_Msk

+#define RCC_RSR_CDRSTF_Pos                     (19U)

+#define RCC_RSR_CDRSTF_Msk                     (0x1UL << RCC_RSR_CDRSTF_Pos)   /*!< 0x00080000 */

+#define RCC_RSR_CDRSTF                         RCC_RSR_CDRSTF_Msk

+#define RCC_RSR_BORRSTF_Pos                    (21U)

+#define RCC_RSR_BORRSTF_Msk                    (0x1UL << RCC_RSR_BORRSTF_Pos)  /*!< 0x00200000 */

+#define RCC_RSR_BORRSTF                        RCC_RSR_BORRSTF_Msk

+#define RCC_RSR_PINRSTF_Pos                    (22U)

+#define RCC_RSR_PINRSTF_Msk                    (0x1UL << RCC_RSR_PINRSTF_Pos)  /*!< 0x00400000 */

+#define RCC_RSR_PINRSTF                        RCC_RSR_PINRSTF_Msk

+#define RCC_RSR_PORRSTF_Pos                    (23U)

+#define RCC_RSR_PORRSTF_Msk                    (0x1UL << RCC_RSR_PORRSTF_Pos)  /*!< 0x00800000 */

+#define RCC_RSR_PORRSTF                        RCC_RSR_PORRSTF_Msk

+#define RCC_RSR_SFTRSTF_Pos                    (24U)

+#define RCC_RSR_SFTRSTF_Msk                    (0x1UL << RCC_RSR_SFTRSTF_Pos)  /*!< 0x01000000 */

+#define RCC_RSR_SFTRSTF                        RCC_RSR_SFTRSTF_Msk

+#define RCC_RSR_IWDGRSTF_Pos                   (26U)

+#define RCC_RSR_IWDGRSTF_Msk                   (0x1UL << RCC_RSR_IWDGRSTF_Pos) /*!< 0x04000000 */

+#define RCC_RSR_IWDGRSTF                       RCC_RSR_IWDGRSTF_Msk

+#define RCC_RSR_WWDGRSTF_Pos                   (28U)

+#define RCC_RSR_WWDGRSTF_Msk                   (0x1UL << RCC_RSR_WWDGRSTF_Pos) /*!< 0x10000000 */

+#define RCC_RSR_WWDGRSTF                       RCC_RSR_WWDGRSTF_Msk

+

+#define RCC_RSR_LPWRRSTF_Pos                   (30U)

+#define RCC_RSR_LPWRRSTF_Msk                   (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */

+#define RCC_RSR_LPWRRSTF                       RCC_RSR_LPWRRSTF_Msk

+

+

+/* Legacy define */

+#define RCC_RSR_IWDG1RSTF_Pos                  RCC_RSR_IWDGRSTF_Pos

+#define RCC_RSR_IWDG1RSTF_Msk                  RCC_RSR_IWDGRSTF_Msk

+#define RCC_RSR_IWDG1RSTF                      RCC_RSR_IWDGRSTF

+#define RCC_RSR_WWDG1RSTF_Pos                  RCC_RSR_WWDGRSTF_Pos

+#define RCC_RSR_WWDG1RSTF_Msk                  RCC_RSR_WWDGRSTF_Msk

+#define RCC_RSR_WWDG1RSTF                      RCC_RSR_WWDGRSTF

+/******************************************************************************/

+/*                                                                            */

+/*                                    RNG                                     */

+/*                                                                            */

+/******************************************************************************/

+/***************************    RNG VER  **************************************/

+#define RNG_VER_3_1

+/********************  Bits definition for RNG_CR register  *******************/

+#define RNG_CR_RNGEN_Pos    (2U)

+#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */

+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk

+#define RNG_CR_IE_Pos       (3U)

+#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */

+#define RNG_CR_IE           RNG_CR_IE_Msk

+#define RNG_CR_CED_Pos      (5U)

+#define RNG_CR_CED_Msk      (0x1UL << RNG_CR_CED_Pos)                          /*!< 0x00000020 */

+#define RNG_CR_CED          RNG_CR_CED_Msk

+#define RNG_CR_RNG_CONFIG3_Pos      (8U)

+#define RNG_CR_RNG_CONFIG3_Msk      (0xFUL << RNG_CR_RNG_CONFIG3_Pos)          /*!< 0x00000F00 */

+#define RNG_CR_RNG_CONFIG3          RNG_CR_RNG_CONFIG3_Msk

+#define RNG_CR_NISTC_Pos            (12U)

+#define RNG_CR_NISTC_Msk            (0x1UL << RNG_CR_NISTC_Pos)                /*!< 0x00001000 */

+#define RNG_CR_NISTC                RNG_CR_NISTC_Msk

+#define RNG_CR_RNG_CONFIG2_Pos      (13U)

+#define RNG_CR_RNG_CONFIG2_Msk      (0x7UL << RNG_CR_RNG_CONFIG2_Pos)          /*!< 0x0000E000 */

+#define RNG_CR_RNG_CONFIG2          RNG_CR_RNG_CONFIG2_Msk

+#define RNG_CR_CLKDIV_Pos           (16U)

+#define RNG_CR_CLKDIV_Msk           (0xFUL << RNG_CR_CLKDIV_Pos)               /*!< 0x000F0000 */

+#define RNG_CR_CLKDIV               RNG_CR_CLKDIV_Msk

+#define RNG_CR_CLKDIV_0             (0x1U << RNG_CR_CLKDIV_Pos)                /*!< 0x00010000 */

+#define RNG_CR_CLKDIV_1             (0x2U << RNG_CR_CLKDIV_Pos)                /*!< 0x00020000 */

+#define RNG_CR_CLKDIV_2             (0x4U << RNG_CR_CLKDIV_Pos)                /*!< 0x00040000 */

+#define RNG_CR_CLKDIV_3             (0x8U << RNG_CR_CLKDIV_Pos)                /*!< 0x00080000 */

+#define RNG_CR_RNG_CONFIG1_Pos      (20U)

+#define RNG_CR_RNG_CONFIG1_Msk      (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)         /*!< 0x03F00000 */

+#define RNG_CR_RNG_CONFIG1          RNG_CR_RNG_CONFIG1_Msk

+#define RNG_CR_CONDRST_Pos         (30U)

+#define RNG_CR_CONDRST_Msk         (0x1UL << RNG_CR_CONDRST_Pos)                  /*!< 0x40000000 */

+#define RNG_CR_CONDRST             RNG_CR_CONDRST_Msk

+#define RNG_CR_CONFIGLOCK_Pos      (31U)

+#define RNG_CR_CONFIGLOCK_Msk      (0x1UL << RNG_CR_CONFIGLOCK_Pos)            /*!< 0x80000000 */

+#define RNG_CR_CONFIGLOCK          RNG_CR_CONFIGLOCK_Msk

+

+/********************  Bits definition for RNG_SR register  *******************/

+#define RNG_SR_DRDY_Pos     (0U)

+#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */

+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk

+#define RNG_SR_CECS_Pos     (1U)

+#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */

+#define RNG_SR_CECS         RNG_SR_CECS_Msk

+#define RNG_SR_SECS_Pos     (2U)

+#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */

+#define RNG_SR_SECS         RNG_SR_SECS_Msk

+#define RNG_SR_CEIS_Pos     (5U)

+#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */

+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk

+#define RNG_SR_SEIS_Pos     (6U)

+#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */

+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                           Real-Time Clock (RTC)                            */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for RTC_TR register  *******************/

+#define RTC_TR_PM_Pos                  (22U)

+#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */

+#define RTC_TR_PM                      RTC_TR_PM_Msk

+#define RTC_TR_HT_Pos                  (20U)

+#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */

+#define RTC_TR_HT                      RTC_TR_HT_Msk

+#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */

+#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */

+#define RTC_TR_HU_Pos                  (16U)

+#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */

+#define RTC_TR_HU                      RTC_TR_HU_Msk

+#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */

+#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */

+#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */

+#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */

+#define RTC_TR_MNT_Pos                 (12U)

+#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */

+#define RTC_TR_MNT                     RTC_TR_MNT_Msk

+#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */

+#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */

+#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */

+#define RTC_TR_MNU_Pos                 (8U)

+#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */

+#define RTC_TR_MNU                     RTC_TR_MNU_Msk

+#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */

+#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */

+#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */

+#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */

+#define RTC_TR_ST_Pos                  (4U)

+#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */

+#define RTC_TR_ST                      RTC_TR_ST_Msk

+#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */

+#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */

+#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */

+#define RTC_TR_SU_Pos                  (0U)

+#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */

+#define RTC_TR_SU                      RTC_TR_SU_Msk

+#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */

+#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */

+#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */

+#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_DR register  *******************/

+#define RTC_DR_YT_Pos                  (20U)

+#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */

+#define RTC_DR_YT                      RTC_DR_YT_Msk

+#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */

+#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */

+#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */

+#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */

+#define RTC_DR_YU_Pos                  (16U)

+#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */

+#define RTC_DR_YU                      RTC_DR_YU_Msk

+#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */

+#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */

+#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */

+#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */

+#define RTC_DR_WDU_Pos                 (13U)

+#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */

+#define RTC_DR_WDU                     RTC_DR_WDU_Msk

+#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */

+#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */

+#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */

+#define RTC_DR_MT_Pos                  (12U)

+#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */

+#define RTC_DR_MT                      RTC_DR_MT_Msk

+#define RTC_DR_MU_Pos                  (8U)

+#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */

+#define RTC_DR_MU                      RTC_DR_MU_Msk

+#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */

+#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */

+#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */

+#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */

+#define RTC_DR_DT_Pos                  (4U)

+#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */

+#define RTC_DR_DT                      RTC_DR_DT_Msk

+#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */

+#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */

+#define RTC_DR_DU_Pos                  (0U)

+#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */

+#define RTC_DR_DU                      RTC_DR_DU_Msk

+#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */

+#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */

+#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */

+#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_CR register  *******************/

+#define RTC_CR_OUT2EN_Pos            (31U)

+#define RTC_CR_OUT2EN_Msk            (0x1UL << RTC_CR_OUT2EN_Pos)              /*!< 0x80000000 */

+#define RTC_CR_OUT2EN                RTC_CR_OUT2EN_Msk                         /*!<RTC_OUT2 output enable */

+#define RTC_CR_TAMPALRM_TYPE_Pos     (30U)

+#define RTC_CR_TAMPALRM_TYPE_Msk     (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)       /*!< 0x40000000 */

+#define RTC_CR_TAMPALRM_TYPE         RTC_CR_TAMPALRM_TYPE_Msk                  /*!<TAMPALARM output type  */

+#define RTC_CR_TAMPALRM_PU_Pos       (29U)

+#define RTC_CR_TAMPALRM_PU_Msk       (0x1UL << RTC_CR_TAMPALRM_PU_Pos)         /*!< 0x20000000 */

+#define RTC_CR_TAMPALRM_PU           RTC_CR_TAMPALRM_PU_Msk                    /*!<TAMPALARM output pull-up config */

+#define RTC_CR_TAMPOE_Pos            (26U)

+#define RTC_CR_TAMPOE_Msk            (0x1UL << RTC_CR_TAMPOE_Pos)              /*!< 0x04000000 */

+#define RTC_CR_TAMPOE                RTC_CR_TAMPOE_Msk                         /*!<Tamper detection output enable on TAMPALARM  */

+#define RTC_CR_TAMPTS_Pos            (25U)

+#define RTC_CR_TAMPTS_Msk            (0x1UL << RTC_CR_TAMPTS_Pos)              /*!< 0x02000000 */

+#define RTC_CR_TAMPTS                RTC_CR_TAMPTS_Msk                         /*!<Activate timestamp on tamper detection event  */

+#define RTC_CR_ITSE_Pos                (24U)

+#define RTC_CR_ITSE_Msk                (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */

+#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk

+#define RTC_CR_COE_Pos                 (23U)

+#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */

+#define RTC_CR_COE                     RTC_CR_COE_Msk

+#define RTC_CR_OSEL_Pos                (21U)

+#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */

+#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk

+#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */

+#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */

+#define RTC_CR_POL_Pos                 (20U)

+#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */

+#define RTC_CR_POL                     RTC_CR_POL_Msk

+#define RTC_CR_COSEL_Pos               (19U)

+#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */

+#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk

+#define RTC_CR_BKP_Pos                 (18U)

+#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */

+#define RTC_CR_BKP                     RTC_CR_BKP_Msk

+#define RTC_CR_SUB1H_Pos               (17U)

+#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */

+#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk

+#define RTC_CR_ADD1H_Pos               (16U)

+#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */

+#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk

+#define RTC_CR_TSIE_Pos                (15U)

+#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */

+#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk

+#define RTC_CR_WUTIE_Pos               (14U)

+#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */

+#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk

+#define RTC_CR_ALRBIE_Pos              (13U)

+#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */

+#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk

+#define RTC_CR_ALRAIE_Pos              (12U)

+#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */

+#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk

+#define RTC_CR_TSE_Pos                 (11U)

+#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */

+#define RTC_CR_TSE                     RTC_CR_TSE_Msk

+#define RTC_CR_WUTE_Pos                (10U)

+#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */

+#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk

+#define RTC_CR_ALRBE_Pos               (9U)

+#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */

+#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk

+#define RTC_CR_ALRAE_Pos               (8U)

+#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */

+#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk

+#define RTC_CR_FMT_Pos                 (6U)

+#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */

+#define RTC_CR_FMT                     RTC_CR_FMT_Msk

+#define RTC_CR_BYPSHAD_Pos             (5U)

+#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */

+#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk

+#define RTC_CR_REFCKON_Pos             (4U)

+#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */

+#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk

+#define RTC_CR_TSEDGE_Pos              (3U)

+#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */

+#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk

+#define RTC_CR_WUCKSEL_Pos             (0U)

+#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */

+#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk

+#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */

+#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */

+#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */

+

+/********************  Bits definition for RTC_ICSR register  ******************/

+#define RTC_ICSR_RECALPF_Pos         (16U)

+#define RTC_ICSR_RECALPF_Msk         (0x1UL << RTC_ICSR_RECALPF_Pos)           /*!< 0x00010000 */

+#define RTC_ICSR_RECALPF             RTC_ICSR_RECALPF_Msk

+#define RTC_ICSR_INIT_Pos            (7U)

+#define RTC_ICSR_INIT_Msk            (0x1UL << RTC_ICSR_INIT_Pos)              /*!< 0x00000080 */

+#define RTC_ICSR_INIT                RTC_ICSR_INIT_Msk

+#define RTC_ICSR_INITF_Pos           (6U)

+#define RTC_ICSR_INITF_Msk           (0x1UL << RTC_ICSR_INITF_Pos)             /*!< 0x00000040 */

+#define RTC_ICSR_INITF               RTC_ICSR_INITF_Msk

+#define RTC_ICSR_RSF_Pos             (5U)

+#define RTC_ICSR_RSF_Msk             (0x1UL << RTC_ICSR_RSF_Pos)               /*!< 0x00000020 */

+#define RTC_ICSR_RSF                 RTC_ICSR_RSF_Msk

+#define RTC_ICSR_INITS_Pos           (4U)

+#define RTC_ICSR_INITS_Msk           (0x1UL << RTC_ICSR_INITS_Pos)             /*!< 0x00000010 */

+#define RTC_ICSR_INITS               RTC_ICSR_INITS_Msk

+#define RTC_ICSR_SHPF_Pos            (3U)

+#define RTC_ICSR_SHPF_Msk            (0x1UL << RTC_ICSR_SHPF_Pos)              /*!< 0x00000008 */

+#define RTC_ICSR_SHPF                RTC_ICSR_SHPF_Msk

+#define RTC_ICSR_WUTWF_Pos           (2U)

+#define RTC_ICSR_WUTWF_Msk           (0x1UL << RTC_ICSR_WUTWF_Pos)             /*!< 0x00000004 */

+#define RTC_ICSR_WUTWF               RTC_ICSR_WUTWF_Msk

+#define RTC_ICSR_ALRBWF_Pos          (1U)

+#define RTC_ICSR_ALRBWF_Msk          (0x1UL << RTC_ICSR_ALRBWF_Pos)            /*!< 0x00000002 */

+#define RTC_ICSR_ALRBWF              RTC_ICSR_ALRBWF_Msk

+#define RTC_ICSR_ALRAWF_Pos          (0U)

+#define RTC_ICSR_ALRAWF_Msk          (0x1UL << RTC_ICSR_ALRAWF_Pos)            /*!< 0x00000001 */

+#define RTC_ICSR_ALRAWF              RTC_ICSR_ALRAWF_Msk

+

+/********************  Bits definition for RTC_PRER register  *****************/

+#define RTC_PRER_PREDIV_A_Pos          (16U)

+#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */

+#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk

+#define RTC_PRER_PREDIV_S_Pos          (0U)

+#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */

+#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk

+

+/********************  Bits definition for RTC_WUTR register  *****************/

+#define RTC_WUTR_WUT_Pos               (0U)

+#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */

+#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk

+

+/********************  Bits definition for RTC_ALRMAR register  ***************/

+#define RTC_ALRMAR_MSK4_Pos            (31U)

+#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */

+#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk

+#define RTC_ALRMAR_WDSEL_Pos           (30U)

+#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */

+#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk

+#define RTC_ALRMAR_DT_Pos              (28U)

+#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */

+#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk

+#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */

+#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */

+#define RTC_ALRMAR_DU_Pos              (24U)

+#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */

+#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk

+#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */

+#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */

+#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */

+#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */

+#define RTC_ALRMAR_MSK3_Pos            (23U)

+#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */

+#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk

+#define RTC_ALRMAR_PM_Pos              (22U)

+#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */

+#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk

+#define RTC_ALRMAR_HT_Pos              (20U)

+#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */

+#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk

+#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */

+#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */

+#define RTC_ALRMAR_HU_Pos              (16U)

+#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */

+#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk

+#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */

+#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */

+#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */

+#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */

+#define RTC_ALRMAR_MSK2_Pos            (15U)

+#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */

+#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk

+#define RTC_ALRMAR_MNT_Pos             (12U)

+#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */

+#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk

+#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */

+#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */

+#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */

+#define RTC_ALRMAR_MNU_Pos             (8U)

+#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */

+#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk

+#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */

+#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */

+#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */

+#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */

+#define RTC_ALRMAR_MSK1_Pos            (7U)

+#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */

+#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk

+#define RTC_ALRMAR_ST_Pos              (4U)

+#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */

+#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk

+#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */

+#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */

+#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */

+#define RTC_ALRMAR_SU_Pos              (0U)

+#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */

+#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk

+#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */

+#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */

+#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */

+#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_ALRMBR register  ***************/

+#define RTC_ALRMBR_MSK4_Pos            (31U)

+#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */

+#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk

+#define RTC_ALRMBR_WDSEL_Pos           (30U)

+#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */

+#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk

+#define RTC_ALRMBR_DT_Pos              (28U)

+#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */

+#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk

+#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */

+#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */

+#define RTC_ALRMBR_DU_Pos              (24U)

+#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */

+#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk

+#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */

+#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */

+#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */

+#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */

+#define RTC_ALRMBR_MSK3_Pos            (23U)

+#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */

+#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk

+#define RTC_ALRMBR_PM_Pos              (22U)

+#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */

+#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk

+#define RTC_ALRMBR_HT_Pos              (20U)

+#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */

+#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk

+#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */

+#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */

+#define RTC_ALRMBR_HU_Pos              (16U)

+#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */

+#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk

+#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */

+#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */

+#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */

+#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */

+#define RTC_ALRMBR_MSK2_Pos            (15U)

+#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */

+#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk

+#define RTC_ALRMBR_MNT_Pos             (12U)

+#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */

+#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk

+#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */

+#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */

+#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */

+#define RTC_ALRMBR_MNU_Pos             (8U)

+#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */

+#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk

+#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */

+#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */

+#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */

+#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */

+#define RTC_ALRMBR_MSK1_Pos            (7U)

+#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */

+#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk

+#define RTC_ALRMBR_ST_Pos              (4U)

+#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */

+#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk

+#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */

+#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */

+#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */

+#define RTC_ALRMBR_SU_Pos              (0U)

+#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */

+#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk

+#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */

+#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */

+#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */

+#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_WPR register  ******************/

+#define RTC_WPR_KEY_Pos                (0U)

+#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */

+#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk

+

+/********************  Bits definition for RTC_SSR register  ******************/

+#define RTC_SSR_SS_Pos                 (0U)

+#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)            /*!< 0x0000FFFF */

+#define RTC_SSR_SS                     RTC_SSR_SS_Msk

+

+/********************  Bits definition for RTC_SHIFTR register  ***************/

+#define RTC_SHIFTR_SUBFS_Pos           (0U)

+#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */

+#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk

+#define RTC_SHIFTR_ADD1S_Pos           (31U)

+#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */

+#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk

+

+/********************  Bits definition for RTC_TSTR register  *****************/

+#define RTC_TSTR_PM_Pos                (22U)

+#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */

+#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk

+#define RTC_TSTR_HT_Pos                (20U)

+#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */

+#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk

+#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */

+#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */

+#define RTC_TSTR_HU_Pos                (16U)

+#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */

+#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk

+#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */

+#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */

+#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */

+#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */

+#define RTC_TSTR_MNT_Pos               (12U)

+#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */

+#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk

+#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */

+#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */

+#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */

+#define RTC_TSTR_MNU_Pos               (8U)

+#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */

+#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk

+#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */

+#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */

+#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */

+#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */

+#define RTC_TSTR_ST_Pos                (4U)

+#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */

+#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk

+#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */

+#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */

+#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */

+#define RTC_TSTR_SU_Pos                (0U)

+#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */

+#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk

+#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */

+#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */

+#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */

+#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_TSDR register  *****************/

+#define RTC_TSDR_WDU_Pos               (13U)

+#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */

+#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk

+#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */

+#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */

+#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */

+#define RTC_TSDR_MT_Pos                (12U)

+#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */

+#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk

+#define RTC_TSDR_MU_Pos                (8U)

+#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */

+#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk

+#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */

+#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */

+#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */

+#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */

+#define RTC_TSDR_DT_Pos                (4U)

+#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */

+#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk

+#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */

+#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */

+#define RTC_TSDR_DU_Pos                (0U)

+#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */

+#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk

+#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */

+#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */

+#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */

+#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_TSSSR register  ****************/

+#define RTC_TSSSR_SS_Pos               (0U)

+#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)          /*!< 0x0000FFFF */

+#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk

+

+/********************  Bits definition for RTC_CALR register  *****************/

+#define RTC_CALR_CALP_Pos              (15U)

+#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */

+#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk

+#define RTC_CALR_CALW8_Pos             (14U)

+#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */

+#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk

+#define RTC_CALR_CALW16_Pos            (13U)

+#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */

+#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk

+#define RTC_CALR_CALM_Pos              (0U)

+#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */

+#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk

+#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */

+#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */

+#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */

+#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */

+#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */

+#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */

+#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */

+#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */

+#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */

+

+

+/********************  Bits definition for RTC_ALRMASSR register  *************/

+#define RTC_ALRMASSR_MASKSS_Pos        (24U)

+#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x0F000000 */

+#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk

+#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */

+#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */

+#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */

+#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */

+#define RTC_ALRMASSR_SS_Pos            (0U)

+#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */

+#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk

+

+/********************  Bits definition for RTC_ALRMBSSR register  *************/

+#define RTC_ALRMBSSR_MASKSS_Pos        (24U)

+#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x0F000000 */

+#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk

+#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */

+#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */

+#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */

+#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */

+#define RTC_ALRMBSSR_SS_Pos            (0U)

+#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */

+#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk

+

+

+/********************  Bits definition for RTC_SR register  *******************/

+#define RTC_SR_ITSF_Pos              (5U)

+#define RTC_SR_ITSF_Msk              (0x1UL << RTC_SR_ITSF_Pos)                 /*!< 0x00000020 */

+#define RTC_SR_ITSF                  RTC_SR_ITSF_Msk

+#define RTC_SR_TSOVF_Pos             (4U)

+#define RTC_SR_TSOVF_Msk             (0x1UL << RTC_SR_TSOVF_Pos)                /*!< 0x00000010 */

+#define RTC_SR_TSOVF                 RTC_SR_TSOVF_Msk

+#define RTC_SR_TSF_Pos               (3U)

+#define RTC_SR_TSF_Msk               (0x1UL << RTC_SR_TSF_Pos)                  /*!< 0x00000008 */

+#define RTC_SR_TSF                   RTC_SR_TSF_Msk

+#define RTC_SR_WUTF_Pos              (2U)

+#define RTC_SR_WUTF_Msk              (0x1UL << RTC_SR_WUTF_Pos)                 /*!< 0x00000004 */

+#define RTC_SR_WUTF                  RTC_SR_WUTF_Msk

+#define RTC_SR_ALRBF_Pos             (1U)

+#define RTC_SR_ALRBF_Msk             (0x1UL << RTC_SR_ALRBF_Pos)                /*!< 0x00000002 */

+#define RTC_SR_ALRBF                 RTC_SR_ALRBF_Msk

+#define RTC_SR_ALRAF_Pos             (0U)

+#define RTC_SR_ALRAF_Msk             (0x1UL << RTC_SR_ALRAF_Pos)                /*!< 0x00000001 */

+#define RTC_SR_ALRAF                 RTC_SR_ALRAF_Msk

+

+/********************  Bits definition for RTC_MISR register  *****************/

+#define RTC_MISR_ITSMF_Pos           (5U)

+#define RTC_MISR_ITSMF_Msk           (0x1UL << RTC_MISR_ITSMF_Pos)              /*!< 0x00000020 */

+#define RTC_MISR_ITSMF               RTC_MISR_ITSMF_Msk

+#define RTC_MISR_TSOVMF_Pos          (4U)

+#define RTC_MISR_TSOVMF_Msk          (0x1UL << RTC_MISR_TSOVMF_Pos)             /*!< 0x00000010 */

+#define RTC_MISR_TSOVMF              RTC_MISR_TSOVMF_Msk

+#define RTC_MISR_TSMF_Pos            (3U)

+#define RTC_MISR_TSMF_Msk            (0x1UL << RTC_MISR_TSMF_Pos)               /*!< 0x00000008 */

+#define RTC_MISR_TSMF                RTC_MISR_TSMF_Msk

+#define RTC_MISR_WUTMF_Pos           (2U)

+#define RTC_MISR_WUTMF_Msk           (0x1UL << RTC_MISR_WUTMF_Pos)              /*!< 0x00000004 */

+#define RTC_MISR_WUTMF               RTC_MISR_WUTMF_Msk

+#define RTC_MISR_ALRBMF_Pos          (1U)

+#define RTC_MISR_ALRBMF_Msk          (0x1UL << RTC_MISR_ALRBMF_Pos)             /*!< 0x00000002 */

+#define RTC_MISR_ALRBMF              RTC_MISR_ALRBMF_Msk

+#define RTC_MISR_ALRAMF_Pos          (0U)

+#define RTC_MISR_ALRAMF_Msk          (0x1UL << RTC_MISR_ALRAMF_Pos)             /*!< 0x00000001 */

+#define RTC_MISR_ALRAMF              RTC_MISR_ALRAMF_Msk

+

+/********************  Bits definition for RTC_SCR register  ******************/

+#define RTC_SCR_CITSF_Pos            (5U)

+#define RTC_SCR_CITSF_Msk            (0x1UL << RTC_SCR_CITSF_Pos)               /*!< 0x00000020 */

+#define RTC_SCR_CITSF                RTC_SCR_CITSF_Msk

+#define RTC_SCR_CTSOVF_Pos           (4U)

+#define RTC_SCR_CTSOVF_Msk           (0x1UL << RTC_SCR_CTSOVF_Pos)              /*!< 0x00000010 */

+#define RTC_SCR_CTSOVF               RTC_SCR_CTSOVF_Msk

+#define RTC_SCR_CTSF_Pos             (3U)

+#define RTC_SCR_CTSF_Msk             (0x1UL << RTC_SCR_CTSF_Pos)                /*!< 0x00000008 */

+#define RTC_SCR_CTSF                 RTC_SCR_CTSF_Msk

+#define RTC_SCR_CWUTF_Pos            (2U)

+#define RTC_SCR_CWUTF_Msk            (0x1UL << RTC_SCR_CWUTF_Pos)               /*!< 0x00000004 */

+#define RTC_SCR_CWUTF                RTC_SCR_CWUTF_Msk

+#define RTC_SCR_CALRBF_Pos           (1U)

+#define RTC_SCR_CALRBF_Msk           (0x1UL << RTC_SCR_CALRBF_Pos)              /*!< 0x00000002 */

+#define RTC_SCR_CALRBF               RTC_SCR_CALRBF_Msk

+#define RTC_SCR_CALRAF_Pos           (0U)

+#define RTC_SCR_CALRAF_Msk           (0x1UL << RTC_SCR_CALRAF_Pos)              /*!< 0x00000001 */

+#define RTC_SCR_CALRAF               RTC_SCR_CALRAF_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                     Tamper and backup register (TAMP)                      */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for TAMP_CR1 register  *****************/

+#define TAMP_CR1_TAMP1E_Pos          (0U)

+#define TAMP_CR1_TAMP1E_Msk          (0x1UL << TAMP_CR1_TAMP1E_Pos)            /*!< 0x00000001 */

+#define TAMP_CR1_TAMP1E              TAMP_CR1_TAMP1E_Msk

+#define TAMP_CR1_TAMP2E_Pos          (1U)

+#define TAMP_CR1_TAMP2E_Msk          (0x1UL << TAMP_CR1_TAMP2E_Pos)            /*!< 0x00000002 */

+#define TAMP_CR1_TAMP2E              TAMP_CR1_TAMP2E_Msk

+#define TAMP_CR1_TAMP3E_Pos          (2U)

+#define TAMP_CR1_TAMP3E_Msk          (0x1UL << TAMP_CR1_TAMP3E_Pos)            /*!< 0x00000004 */

+#define TAMP_CR1_TAMP3E              TAMP_CR1_TAMP3E_Msk

+#define TAMP_CR1_ITAMP1E_Pos         (16U)

+#define TAMP_CR1_ITAMP1E_Msk         (0x1UL << TAMP_CR1_ITAMP1E_Pos)           /*!< 0x00010000 */

+#define TAMP_CR1_ITAMP1E             TAMP_CR1_ITAMP1E_Msk

+#define TAMP_CR1_ITAMP2E_Pos         (17U)

+#define TAMP_CR1_ITAMP2E_Msk         (0x1UL << TAMP_CR1_ITAMP2E_Pos)           /*!< 0x00020000 */

+#define TAMP_CR1_ITAMP2E             TAMP_CR1_ITAMP2E_Msk

+#define TAMP_CR1_ITAMP3E_Pos         (18U)

+#define TAMP_CR1_ITAMP3E_Msk         (0x1UL << TAMP_CR1_ITAMP3E_Pos)           /*!< 0x00040000 */

+#define TAMP_CR1_ITAMP3E             TAMP_CR1_ITAMP3E_Msk

+#define TAMP_CR1_ITAMP4E_Pos         (19U)

+#define TAMP_CR1_ITAMP4E_Msk         (0x1UL << TAMP_CR1_ITAMP4E_Pos)           /*!< 0x00080000 */

+#define TAMP_CR1_ITAMP4E             TAMP_CR1_ITAMP4E_Msk

+#define TAMP_CR1_ITAMP5E_Pos         (20U)

+#define TAMP_CR1_ITAMP5E_Msk         (0x1UL << TAMP_CR1_ITAMP5E_Pos)           /*!< 0x00100000 */

+#define TAMP_CR1_ITAMP5E             TAMP_CR1_ITAMP5E_Msk

+#define TAMP_CR1_ITAMP6E_Pos         (21U)

+#define TAMP_CR1_ITAMP6E_Msk         (0x1UL << TAMP_CR1_ITAMP6E_Pos)           /*!< 0x00200000 */

+#define TAMP_CR1_ITAMP6E             TAMP_CR1_ITAMP6E_Msk

+#define TAMP_CR1_ITAMP8E_Pos         (23U)

+#define TAMP_CR1_ITAMP8E_Msk         (0x1UL << TAMP_CR1_ITAMP8E_Pos)           /*!< 0x00800000 */

+#define TAMP_CR1_ITAMP8E             TAMP_CR1_ITAMP8E_Msk

+

+/********************  Bits definition for TAMP_CR2 register  *****************/

+#define TAMP_CR2_TAMP1NOERASE_Pos    (0U)

+#define TAMP_CR2_TAMP1NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)      /*!< 0x00000001 */

+#define TAMP_CR2_TAMP1NOERASE        TAMP_CR2_TAMP1NOERASE_Msk

+#define TAMP_CR2_TAMP2NOERASE_Pos    (1U)

+#define TAMP_CR2_TAMP2NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)      /*!< 0x00000002 */

+#define TAMP_CR2_TAMP2NOERASE        TAMP_CR2_TAMP2NOERASE_Msk

+#define TAMP_CR2_TAMP3NOERASE_Pos    (2U)

+#define TAMP_CR2_TAMP3NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos)      /*!< 0x00000004 */

+#define TAMP_CR2_TAMP3NOERASE        TAMP_CR2_TAMP3NOERASE_Msk

+#define TAMP_CR2_TAMP1MSK_Pos        (16U)

+#define TAMP_CR2_TAMP1MSK_Msk        (0x1UL << TAMP_CR2_TAMP1MSK_Pos)          /*!< 0x00010000 */

+#define TAMP_CR2_TAMP1MSK            TAMP_CR2_TAMP1MSK_Msk

+#define TAMP_CR2_TAMP2MSK_Pos        (17U)

+#define TAMP_CR2_TAMP2MSK_Msk        (0x1UL << TAMP_CR2_TAMP2MSK_Pos)          /*!< 0x00020000 */

+#define TAMP_CR2_TAMP2MSK            TAMP_CR2_TAMP2MSK_Msk

+#define TAMP_CR2_TAMP3MSK_Pos        (18U)

+#define TAMP_CR2_TAMP3MSK_Msk        (0x1UL << TAMP_CR2_TAMP3MSK_Pos)          /*!< 0x00040000 */

+#define TAMP_CR2_TAMP3MSK            TAMP_CR2_TAMP3MSK_Msk

+#define TAMP_CR2_TAMP1TRG_Pos        (24U)

+#define TAMP_CR2_TAMP1TRG_Msk        (0x1UL << TAMP_CR2_TAMP1TRG_Pos)          /*!< 0x01000000 */

+#define TAMP_CR2_TAMP1TRG            TAMP_CR2_TAMP1TRG_Msk

+#define TAMP_CR2_TAMP2TRG_Pos        (25U)

+#define TAMP_CR2_TAMP2TRG_Msk        (0x1UL << TAMP_CR2_TAMP2TRG_Pos)          /*!< 0x02000000 */

+#define TAMP_CR2_TAMP2TRG            TAMP_CR2_TAMP2TRG_Msk

+#define TAMP_CR2_TAMP3TRG_Pos        (26U)

+#define TAMP_CR2_TAMP3TRG_Msk        (0x1UL << TAMP_CR2_TAMP3TRG_Pos)          /*!< 0x04000000 */

+#define TAMP_CR2_TAMP3TRG            TAMP_CR2_TAMP3TRG_Msk

+

+/********************  Bits definition for TAMP_FLTCR register  ***************/

+#define TAMP_FLTCR_TAMPFREQ_Pos      (0U)

+#define TAMP_FLTCR_TAMPFREQ_Msk      (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000007 */

+#define TAMP_FLTCR_TAMPFREQ          TAMP_FLTCR_TAMPFREQ_Msk

+#define TAMP_FLTCR_TAMPFREQ_0        (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000001 */

+#define TAMP_FLTCR_TAMPFREQ_1        (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000002 */

+#define TAMP_FLTCR_TAMPFREQ_2        (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000004 */

+#define TAMP_FLTCR_TAMPFLT_Pos       (3U)

+#define TAMP_FLTCR_TAMPFLT_Msk       (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000018 */

+#define TAMP_FLTCR_TAMPFLT           TAMP_FLTCR_TAMPFLT_Msk

+#define TAMP_FLTCR_TAMPFLT_0         (0x1UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000008 */

+#define TAMP_FLTCR_TAMPFLT_1         (0x2UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000010 */

+#define TAMP_FLTCR_TAMPPRCH_Pos      (5U)

+#define TAMP_FLTCR_TAMPPRCH_Msk      (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000060 */

+#define TAMP_FLTCR_TAMPPRCH          TAMP_FLTCR_TAMPPRCH_Msk

+#define TAMP_FLTCR_TAMPPRCH_0        (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000020 */

+#define TAMP_FLTCR_TAMPPRCH_1        (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000040 */

+#define TAMP_FLTCR_TAMPPUDIS_Pos     (7U)

+#define TAMP_FLTCR_TAMPPUDIS_Msk     (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)        /*!< 0x00000080 */

+#define TAMP_FLTCR_TAMPPUDIS         TAMP_FLTCR_TAMPPUDIS_Msk

+

+/*******************  Bits definition for TAMP_ATCR1 register  ****************/

+#define TAMP_ATCR1_TAMP1AM_Pos       (0U)

+#define TAMP_ATCR1_TAMP1AM_Msk       (0x1UL << TAMP_ATCR1_TAMP1AM_Pos)         /*!< 0x00000001 */

+#define TAMP_ATCR1_TAMP1AM           TAMP_ATCR1_TAMP1AM_Msk

+#define TAMP_ATCR1_TAMP2AM_Pos       (1U)

+#define TAMP_ATCR1_TAMP2AM_Msk       (0x1UL << TAMP_ATCR1_TAMP2AM_Pos)         /*!< 0x00000002 */

+#define TAMP_ATCR1_TAMP2AM           TAMP_ATCR1_TAMP2AM_Msk

+#define TAMP_ATCR1_TAMP3AM_Pos       (2U)

+#define TAMP_ATCR1_TAMP3AM_Msk       (0x1UL << TAMP_ATCR1_TAMP3AM_Pos)         /*!< 0x00000004 */

+#define TAMP_ATCR1_TAMP3AM           TAMP_ATCR1_TAMP3AM_Msk

+#define TAMP_ATCR1_ATOSEL1_Pos       (8U)

+#define TAMP_ATCR1_ATOSEL1_Msk       (0x3UL << TAMP_ATCR1_ATOSEL1_Pos)          /*!< 0x00000300 */

+#define TAMP_ATCR1_ATOSEL1            TAMP_ATCR1_ATOSEL1_Msk

+#define TAMP_ATCR1_ATOSEL1_0         (0x1UL << TAMP_ATCR1_ATOSEL1_Pos)         /*!< 0x00000100 */

+#define TAMP_ATCR1_ATOSEL1_1         (0x2UL << TAMP_ATCR1_ATOSEL1_Pos)         /*!< 0x00000200 */

+#define TAMP_ATCR1_ATOSEL2_Pos       (10U)

+#define TAMP_ATCR1_ATOSEL2_Msk       (0x3UL << TAMP_ATCR1_ATOSEL2_Pos)          /*!< 0x00000C00 */

+#define TAMP_ATCR1_ATOSEL2            TAMP_ATCR1_ATOSEL2_Msk

+#define TAMP_ATCR1_ATOSEL2_0         (0x1UL << TAMP_ATCR1_ATOSEL2_Pos)         /*!< 0x00000400 */

+#define TAMP_ATCR1_ATOSEL2_1         (0x2UL << TAMP_ATCR1_ATOSEL2_Pos)         /*!< 0x00000800 */

+#define TAMP_ATCR1_ATOSEL3_Pos       (12U)

+#define TAMP_ATCR1_ATOSEL3_Msk       (0x3UL << TAMP_ATCR1_ATOSEL3_Pos)          /*!< 0x00003000 */

+#define TAMP_ATCR1_ATOSEL3            TAMP_ATCR1_ATOSEL3_Msk

+#define TAMP_ATCR1_ATOSEL3_0         (0x1UL << TAMP_ATCR1_ATOSEL3_Pos)         /*!< 0x00001000 */

+#define TAMP_ATCR1_ATOSEL3_1         (0x2UL << TAMP_ATCR1_ATOSEL3_Pos)         /*!< 0x00002000 */

+#define TAMP_ATCR1_ATOSEL4_Pos       (14U)

+#define TAMP_ATCR1_ATOSEL4_Msk       (0x3UL << TAMP_ATCR1_ATOSEL4_Pos)          /*!< 0x0000C000 */

+#define TAMP_ATCR1_ATOSEL4            TAMP_ATCR1_ATOSEL4_Msk

+#define TAMP_ATCR1_ATOSEL4_0         (0x1UL << TAMP_ATCR1_ATOSEL4_Pos)         /*!< 0x00004000 */

+#define TAMP_ATCR1_ATOSEL4_1         (0x2UL << TAMP_ATCR1_ATOSEL4_Pos)         /*!< 0x00008000 */

+#define TAMP_ATCR1_ATCKSEL_Pos       (16U)

+#define TAMP_ATCR1_ATCKSEL_Msk       (0x7UL << TAMP_ATCR1_ATCKSEL_Pos)          /*!< 0x00070000 */

+#define TAMP_ATCR1_ATCKSEL            TAMP_ATCR1_ATCKSEL_Msk

+#define TAMP_ATCR1_ATCKSEL_0         (0x1UL << TAMP_ATCR1_ATCKSEL_Pos)         /*!< 0x00010000 */

+#define TAMP_ATCR1_ATCKSEL_1         (0x2UL << TAMP_ATCR1_ATCKSEL_Pos)         /*!< 0x00020000 */

+#define TAMP_ATCR1_ATCKSEL_2         (0x4UL << TAMP_ATCR1_ATCKSEL_Pos)         /*!< 0x00040000 */

+#define TAMP_ATCR1_ATPER_Pos         (24U)

+#define TAMP_ATCR1_ATPER_Msk         (0x7UL << TAMP_ATCR1_ATPER_Pos)           /*!< 0x07000000 */

+#define TAMP_ATCR1_ATPER             TAMP_ATCR1_ATPER_Msk

+#define TAMP_ATCR1_ATOSHARE_Pos      (30U)

+#define TAMP_ATCR1_ATOSHARE_Msk      (0x1UL << TAMP_ATCR1_ATOSHARE_Pos)        /*!< 0x40000000 */

+#define TAMP_ATCR1_ATOSHARE          TAMP_ATCR1_ATOSHARE_Msk

+#define TAMP_ATCR1_FLTEN_Pos         (31U)

+#define TAMP_ATCR1_FLTEN_Msk         (0x1UL << TAMP_ATCR1_FLTEN_Pos)           /*!< 0x80000000 */

+#define TAMP_ATCR1_FLTEN             TAMP_ATCR1_FLTEN_Msk

+

+/********************  Bits definition for TAMP_ATSEEDR register  *************/

+#define TAMP_ATSEEDR_SEED_Pos        (0U)

+#define TAMP_ATSEEDR_SEED_Msk        (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos)   /*!< 0xFFFFFFFF */

+#define TAMP_ATSEEDR_SEED            TAMP_ATSEEDR_SEED_Msk

+

+/********************  Bits definition for TAMP_ATOR register  ****************/

+#define TAMP_ATOR_PRNG_Pos           (0U)

+#define TAMP_ATOR_PRNG_Msk           (0x000000FFUL << TAMP_ATOR_PRNG_Pos)      /*!< 0x000000FF */

+#define TAMP_ATOR_PRNG               TAMP_ATOR_PRNG_Msk

+#define TAMP_ATOR_SEEDF_Pos          (14U)

+#define TAMP_ATOR_SEEDF_Msk          (0x01UL << TAMP_ATOR_SEEDF_Pos)           /*!< 0x00004000 */

+#define TAMP_ATOR_SEEDF              TAMP_ATOR_SEEDF_Msk

+#define TAMP_ATOR_INITS_Pos          (15U)

+#define TAMP_ATOR_INITS_Msk          (0x01UL << TAMP_ATOR_INITS_Pos)           /*!< 0x00008000 */

+#define TAMP_ATOR_INITS              TAMP_ATOR_INITS_Msk

+

+/********************  Bits definition for TAMP_IER register  *****************/

+#define TAMP_IER_TAMP1IE_Pos         (0U)

+#define TAMP_IER_TAMP1IE_Msk         (0x1UL << TAMP_IER_TAMP1IE_Pos)           /*!< 0x00000001 */

+#define TAMP_IER_TAMP1IE             TAMP_IER_TAMP1IE_Msk

+#define TAMP_IER_TAMP2IE_Pos         (1U)

+#define TAMP_IER_TAMP2IE_Msk         (0x1UL << TAMP_IER_TAMP2IE_Pos)           /*!< 0x00000002 */

+#define TAMP_IER_TAMP2IE             TAMP_IER_TAMP2IE_Msk

+#define TAMP_IER_TAMP3IE_Pos         (2U)

+#define TAMP_IER_TAMP3IE_Msk         (0x1UL << TAMP_IER_TAMP3IE_Pos)           /*!< 0x00000004 */

+#define TAMP_IER_TAMP3IE             TAMP_IER_TAMP3IE_Msk

+#define TAMP_IER_ITAMP1IE_Pos        (16U)

+#define TAMP_IER_ITAMP1IE_Msk        (0x1UL << TAMP_IER_ITAMP1IE_Pos)          /*!< 0x00010000 */

+#define TAMP_IER_ITAMP1IE            TAMP_IER_ITAMP1IE_Msk

+#define TAMP_IER_ITAMP2IE_Pos        (17U)

+#define TAMP_IER_ITAMP2IE_Msk        (0x1UL << TAMP_IER_ITAMP2IE_Pos)          /*!< 0x00020000 */

+#define TAMP_IER_ITAMP2IE            TAMP_IER_ITAMP2IE_Msk

+#define TAMP_IER_ITAMP3IE_Pos        (18U)

+#define TAMP_IER_ITAMP3IE_Msk        (0x1UL << TAMP_IER_ITAMP3IE_Pos)          /*!< 0x00040000 */

+#define TAMP_IER_ITAMP3IE            TAMP_IER_ITAMP3IE_Msk

+#define TAMP_IER_ITAMP4IE_Pos        (19U)

+#define TAMP_IER_ITAMP4IE_Msk        (0x1UL << TAMP_IER_ITAMP4IE_Pos)          /*!< 0x00080000 */

+#define TAMP_IER_ITAMP4IE            TAMP_IER_ITAMP4IE_Msk

+#define TAMP_IER_ITAMP5IE_Pos        (20U)

+#define TAMP_IER_ITAMP5IE_Msk        (0x1UL << TAMP_IER_ITAMP5IE_Pos)          /*!< 0x00100000 */

+#define TAMP_IER_ITAMP5IE            TAMP_IER_ITAMP5IE_Msk

+#define TAMP_IER_ITAMP6IE_Pos        (21U)

+#define TAMP_IER_ITAMP6IE_Msk        (0x1UL << TAMP_IER_ITAMP6IE_Pos)          /*!< 0x00200000 */

+#define TAMP_IER_ITAMP6IE            TAMP_IER_ITAMP6IE_Msk

+#define TAMP_IER_ITAMP8IE_Pos        (23U)

+#define TAMP_IER_ITAMP8IE_Msk        (0x1UL << TAMP_IER_ITAMP8IE_Pos)          /*!< 0x00800000 */

+#define TAMP_IER_ITAMP8IE            TAMP_IER_ITAMP8IE_Msk

+

+/********************  Bits definition for TAMP_SR register  *****************/

+#define TAMP_SR_TAMP1F_Pos           (0U)

+#define TAMP_SR_TAMP1F_Msk           (0x1UL << TAMP_SR_TAMP1F_Pos)             /*!< 0x00000001 */

+#define TAMP_SR_TAMP1F               TAMP_SR_TAMP1F_Msk

+#define TAMP_SR_TAMP2F_Pos           (1U)

+#define TAMP_SR_TAMP2F_Msk           (0x1UL << TAMP_SR_TAMP2F_Pos)             /*!< 0x00000002 */

+#define TAMP_SR_TAMP2F               TAMP_SR_TAMP2F_Msk

+#define TAMP_SR_TAMP3F_Pos           (2U)

+#define TAMP_SR_TAMP3F_Msk           (0x1UL << TAMP_SR_TAMP3F_Pos)             /*!< 0x00000004 */

+#define TAMP_SR_TAMP3F               TAMP_SR_TAMP3F_Msk

+#define TAMP_SR_ITAMP1F_Pos          (16U)

+#define TAMP_SR_ITAMP1F_Msk          (0x1UL << TAMP_SR_ITAMP1F_Pos)            /*!< 0x00010000 */

+#define TAMP_SR_ITAMP1F              TAMP_SR_ITAMP1F_Msk

+#define TAMP_SR_ITAMP2F_Pos          (17U)

+#define TAMP_SR_ITAMP2F_Msk          (0x1UL << TAMP_SR_ITAMP2F_Pos)            /*!< 0x00020000 */

+#define TAMP_SR_ITAMP2F              TAMP_SR_ITAMP2F_Msk

+#define TAMP_SR_ITAMP3F_Pos          (18U)

+#define TAMP_SR_ITAMP3F_Msk          (0x1UL << TAMP_SR_ITAMP3F_Pos)            /*!< 0x00040000 */

+#define TAMP_SR_ITAMP3F              TAMP_SR_ITAMP3F_Msk

+#define TAMP_SR_ITAMP4F_Pos          (19U)

+#define TAMP_SR_ITAMP4F_Msk          (0x1UL << TAMP_SR_ITAMP4F_Pos)            /*!< 0x00080000 */

+#define TAMP_SR_ITAMP4F              TAMP_SR_ITAMP4F_Msk

+#define TAMP_SR_ITAMP5F_Pos          (20U)

+#define TAMP_SR_ITAMP5F_Msk          (0x1UL << TAMP_SR_ITAMP5F_Pos)            /*!< 0x00100000 */

+#define TAMP_SR_ITAMP5F              TAMP_SR_ITAMP5F_Msk

+#define TAMP_SR_ITAMP6F_Pos          (21U)

+#define TAMP_SR_ITAMP6F_Msk          (0x1UL << TAMP_SR_ITAMP6F_Pos)            /*!< 0x00200000 */

+#define TAMP_SR_ITAMP6F              TAMP_SR_ITAMP6F_Msk

+#define TAMP_SR_ITAMP8F_Pos          (23U)

+#define TAMP_SR_ITAMP8F_Msk          (0x1UL << TAMP_SR_ITAMP8F_Pos)            /*!< 0x00800000 */

+#define TAMP_SR_ITAMP8F              TAMP_SR_ITAMP8F_Msk

+

+/********************  Bits definition for TAMP_MISR register  ************ *****/

+#define TAMP_MISR_TAMP1MF_Pos        (0U)

+#define TAMP_MISR_TAMP1MF_Msk        (0x1UL << TAMP_MISR_TAMP1MF_Pos)           /*!< 0x00000001 */

+#define TAMP_MISR_TAMP1MF            TAMP_MISR_TAMP1MF_Msk

+#define TAMP_MISR_TAMP2MF_Pos        (1U)

+#define TAMP_MISR_TAMP2MF_Msk        (0x1UL << TAMP_MISR_TAMP2MF_Pos)           /*!< 0x00000002 */

+#define TAMP_MISR_TAMP2MF            TAMP_MISR_TAMP2MF_Msk

+#define TAMP_MISR_TAMP3MF_Pos        (2U)

+#define TAMP_MISR_TAMP3MF_Msk        (0x1UL << TAMP_MISR_TAMP3MF_Pos)          /*!< 0x00000004 */

+#define TAMP_MISR_TAMP3MF            TAMP_MISR_TAMP3MF_Msk

+#define TAMP_MISR_ITAMP1MF_Pos       (16U)

+#define TAMP_MISR_ITAMP1MF_Msk       (0x1UL << TAMP_MISR_ITAMP1MF_Pos)         /*!< 0x00010000 */

+#define TAMP_MISR_ITAMP1MF           TAMP_MISR_ITAMP1MF_Msk

+#define TAMP_MISR_ITAMP2MF_Pos       (17U)

+#define TAMP_MISR_ITAMP2MF_Msk       (0x1UL << TAMP_MISR_ITAMP2MF_Pos)         /*!< 0x00020000 */

+#define TAMP_MISR_ITAMP2MF           TAMP_MISR_ITAMP2MF_Msk

+#define TAMP_MISR_ITAMP3MF_Pos       (18U)

+#define TAMP_MISR_ITAMP3MF_Msk       (0x1UL << TAMP_MISR_ITAMP3MF_Pos)         /*!< 0x00040000 */

+#define TAMP_MISR_ITAMP3MF           TAMP_MISR_ITAMP3MF_Msk

+#define TAMP_MISR_ITAMP4MF_Pos       (19U)

+#define TAMP_MISR_ITAMP4MF_Msk       (0x1UL << TAMP_MISR_ITAMP4MF_Pos)         /*!< 0x00080000 */

+#define TAMP_MISR_ITAMP4MF           TAMP_MISR_ITAMP4MF_Msk

+#define TAMP_MISR_ITAMP5MF_Pos       (20U)

+#define TAMP_MISR_ITAMP5MF_Msk       (0x1UL << TAMP_MISR_ITAMP5MF_Pos)         /*!< 0x00100000 */

+#define TAMP_MISR_ITAMP5MF           TAMP_MISR_ITAMP5MF_Msk

+#define TAMP_MISR_ITAMP6MF_Pos       (21U)

+#define TAMP_MISR_ITAMP6MF_Msk       (0x1UL << TAMP_MISR_ITAMP6MF_Pos)         /*!< 0x00200000 */

+#define TAMP_MISR_ITAMP6MF           TAMP_MISR_ITAMP6MF_Msk

+#define TAMP_MISR_ITAMP8MF_Pos       (23U)

+#define TAMP_MISR_ITAMP8MF_Msk       (0x1UL << TAMP_MISR_ITAMP8MF_Pos)         /*!< 0x00800000 */

+#define TAMP_MISR_ITAMP8MF           TAMP_MISR_ITAMP8MF_Msk

+

+/********************  Bits definition for TAMP_SCR register  *****************/

+#define TAMP_SCR_CTAMP1F_Pos         (0U)

+#define TAMP_SCR_CTAMP1F_Msk         (0x1UL << TAMP_SCR_CTAMP1F_Pos)            /*!< 0x00000001 */

+#define TAMP_SCR_CTAMP1F             TAMP_SCR_CTAMP1F_Msk

+#define TAMP_SCR_CTAMP2F_Pos         (1U)

+#define TAMP_SCR_CTAMP2F_Msk         (0x1UL << TAMP_SCR_CTAMP2F_Pos)            /*!< 0x00000002 */

+#define TAMP_SCR_CTAMP2F             TAMP_SCR_CTAMP2F_Msk

+#define TAMP_SCR_CTAMP3F_Pos         (2U)

+#define TAMP_SCR_CTAMP3F_Msk         (0x1UL << TAMP_SCR_CTAMP3F_Pos)           /*!< 0x00000004 */

+#define TAMP_SCR_CTAMP3F             TAMP_SCR_CTAMP3F_Msk

+#define TAMP_SCR_CITAMP1F_Pos        (16U)

+#define TAMP_SCR_CITAMP1F_Msk        (0x1UL << TAMP_SCR_CITAMP1F_Pos)          /*!< 0x00010000 */

+#define TAMP_SCR_CITAMP1F            TAMP_SCR_CITAMP1F_Msk

+#define TAMP_SCR_CITAMP2F_Pos        (17U)

+#define TAMP_SCR_CITAMP2F_Msk        (0x1UL << TAMP_SCR_CITAMP2F_Pos)          /*!< 0x00020000 */

+#define TAMP_SCR_CITAMP2F            TAMP_SCR_CITAMP2F_Msk

+#define TAMP_SCR_CITAMP3F_Pos        (18U)

+#define TAMP_SCR_CITAMP3F_Msk        (0x1UL << TAMP_SCR_CITAMP3F_Pos)          /*!< 0x00040000 */

+#define TAMP_SCR_CITAMP3F            TAMP_SCR_CITAMP3F_Msk

+#define TAMP_SCR_CITAMP4F_Pos        (19U)

+#define TAMP_SCR_CITAMP4F_Msk        (0x1UL << TAMP_SCR_CITAMP4F_Pos)          /*!< 0x00080000 */

+#define TAMP_SCR_CITAMP4F            TAMP_SCR_CITAMP4F_Msk

+#define TAMP_SCR_CITAMP5F_Pos        (20U)

+#define TAMP_SCR_CITAMP5F_Msk        (0x1UL << TAMP_SCR_CITAMP5F_Pos)          /*!< 0x00100000 */

+#define TAMP_SCR_CITAMP5F            TAMP_SCR_CITAMP5F_Msk

+#define TAMP_SCR_CITAMP6F_Pos        (21U)

+#define TAMP_SCR_CITAMP6F_Msk        (0x1UL << TAMP_SCR_CITAMP6F_Pos)          /*!< 0x00200000 */

+#define TAMP_SCR_CITAMP6F            TAMP_SCR_CITAMP6F_Msk

+#define TAMP_SCR_CITAMP8F_Pos        (23U)

+#define TAMP_SCR_CITAMP8F_Msk        (0x1UL << TAMP_SCR_CITAMP8F_Pos)          /*!< 0x00800000 */

+#define TAMP_SCR_CITAMP8F            TAMP_SCR_CITAMP8F_Msk

+

+/********************  Bits definition for TAMP_COUNTR register  **************/

+#define TAMP_COUNTR_Pos              (16U)

+#define TAMP_COUNTR_Msk              (0xFFFFUL << TAMP_COUNTR_Pos)             /*!< 0xFFFF0000 */

+#define TAMP_COUNTR                  TAMP_COUNTR_Msk

+

+/********************  Bits definition for TAMP_OR register  ******************/

+#define TAMP_OR_OUT3_RMP_Pos         (0U)

+#define TAMP_OR_OUT3_RMP_Msk         (0x1UL << TAMP_OR_OUT3_RMP_Pos)           /*!< 0x00000001 */

+#define TAMP_OR_OUT3_RMP             TAMP_OR_OUT3_RMP_Msk

+

+/********************  Bits definition for TAMP_BKP0R register  ***************/

+#define TAMP_BKP0R_Pos               (0U)

+#define TAMP_BKP0R_Msk               (0xFFFFFFFFUL << TAMP_BKP0R_Pos)           /*!< 0xFFFFFFFF */

+#define TAMP_BKP0R                   TAMP_BKP0R_Msk

+

+/********************  Bits definition for TAMP_BKP1R register  ****************/

+#define TAMP_BKP1R_Pos               (0U)

+#define TAMP_BKP1R_Msk               (0xFFFFFFFFUL << TAMP_BKP1R_Pos)           /*!< 0xFFFFFFFF */

+#define TAMP_BKP1R                   TAMP_BKP1R_Msk

+

+/********************  Bits definition for TAMP_BKP2R register  ****************/

+#define TAMP_BKP2R_Pos               (0U)

+#define TAMP_BKP2R_Msk               (0xFFFFFFFFUL << TAMP_BKP2R_Pos)           /*!< 0xFFFFFFFF */

+#define TAMP_BKP2R                   TAMP_BKP2R_Msk

+

+/********************  Bits definition for TAMP_BKP3R register  ****************/

+#define TAMP_BKP3R_Pos               (0U)

+#define TAMP_BKP3R_Msk               (0xFFFFFFFFUL << TAMP_BKP3R_Pos)           /*!< 0xFFFFFFFF */

+#define TAMP_BKP3R                   TAMP_BKP3R_Msk

+

+/********************  Bits definition for TAMP_BKP4R register  ****************/

+#define TAMP_BKP4R_Pos               (0U)

+#define TAMP_BKP4R_Msk               (0xFFFFFFFFUL << TAMP_BKP4R_Pos)           /*!< 0xFFFFFFFF */

+#define TAMP_BKP4R                   TAMP_BKP4R_Msk

+

+/********************  Bits definition for TAMP_BKP5R register  ****************/

+#define TAMP_BKP5R_Pos               (0U)

+#define TAMP_BKP5R_Msk               (0xFFFFFFFFUL << TAMP_BKP5R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP5R                   TAMP_BKP5R_Msk

+

+/********************  Bits definition for TAMP_BKP6R register  ****************/

+#define TAMP_BKP6R_Pos               (0U)

+#define TAMP_BKP6R_Msk               (0xFFFFFFFFUL << TAMP_BKP6R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP6R                   TAMP_BKP6R_Msk

+

+/********************  Bits definition for TAMP_BKP7R register  ****************/

+#define TAMP_BKP7R_Pos               (0U)

+#define TAMP_BKP7R_Msk               (0xFFFFFFFFUL << TAMP_BKP7R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP7R                   TAMP_BKP7R_Msk

+

+/********************  Bits definition for TAMP_BKP8R register  ****************/

+#define TAMP_BKP8R_Pos               (0U)

+#define TAMP_BKP8R_Msk               (0xFFFFFFFFUL << TAMP_BKP8R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP8R                   TAMP_BKP8R_Msk

+

+/********************  Bits definition for TAMP_BKP9R register  ****************/

+#define TAMP_BKP9R_Pos               (0U)

+#define TAMP_BKP9R_Msk               (0xFFFFFFFFUL << TAMP_BKP9R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP9R                   TAMP_BKP9R_Msk

+

+/********************  Bits definition for TAMP_BKP10R register  ***************/

+#define TAMP_BKP10R_Pos              (0U)

+#define TAMP_BKP10R_Msk              (0xFFFFFFFFUL << TAMP_BKP10R_Pos)         /*!< 0xFFFFFFFF */

+#define TAMP_BKP10R                  TAMP_BKP10R_Msk

+

+/********************  Bits definition for TAMP_BKP11R register  ***************/

+#define TAMP_BKP11R_Pos              (0U)

+#define TAMP_BKP11R_Msk              (0xFFFFFFFFUL << TAMP_BKP11R_Pos)         /*!< 0xFFFFFFFF */

+#define TAMP_BKP11R                  TAMP_BKP11R_Msk

+

+/********************  Bits definition for TAMP_BKP12R register  ***************/

+#define TAMP_BKP12R_Pos              (0U)

+#define TAMP_BKP12R_Msk              (0xFFFFFFFFUL << TAMP_BKP12R_Pos)         /*!< 0xFFFFFFFF */

+#define TAMP_BKP12R                  TAMP_BKP12R_Msk

+

+/********************  Bits definition for TAMP_BKP13R register  ***************/

+#define TAMP_BKP13R_Pos              (0U)

+#define TAMP_BKP13R_Msk              (0xFFFFFFFFUL << TAMP_BKP13R_Pos)         /*!< 0xFFFFFFFF */

+#define TAMP_BKP13R                  TAMP_BKP13R_Msk

+

+/********************  Bits definition for TAMP_BKP14R register  ***************/

+#define TAMP_BKP14R_Pos              (0U)

+#define TAMP_BKP14R_Msk              (0xFFFFFFFFUL << TAMP_BKP14R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP14R                  TAMP_BKP14R_Msk

+

+/********************  Bits definition for TAMP_BKP15R register  ***************/

+#define TAMP_BKP15R_Pos              (0U)

+#define TAMP_BKP15R_Msk              (0xFFFFFFFFUL << TAMP_BKP15R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP15R                  TAMP_BKP15R_Msk

+

+/********************  Bits definition for TAMP_BKP16R register  ***************/

+#define TAMP_BKP16R_Pos              (0U)

+#define TAMP_BKP16R_Msk              (0xFFFFFFFFUL << TAMP_BKP16R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP16R                  TAMP_BKP16R_Msk

+

+/********************  Bits definition for TAMP_BKP17R register  ***************/

+#define TAMP_BKP17R_Pos              (0U)

+#define TAMP_BKP17R_Msk              (0xFFFFFFFFUL << TAMP_BKP17R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP17R                  TAMP_BKP17R_Msk

+

+/********************  Bits definition for TAMP_BKP18R register  ***************/

+#define TAMP_BKP18R_Pos              (0U)

+#define TAMP_BKP18R_Msk              (0xFFFFFFFFUL << TAMP_BKP18R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP18R                  TAMP_BKP18R_Msk

+

+/********************  Bits definition for TAMP_BKP19R register  ***************/

+#define TAMP_BKP19R_Pos              (0U)

+#define TAMP_BKP19R_Msk              (0xFFFFFFFFUL << TAMP_BKP19R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP19R                  TAMP_BKP19R_Msk

+

+/********************  Bits definition for TAMP_BKP20R register  ***************/

+#define TAMP_BKP20R_Pos              (0U)

+#define TAMP_BKP20R_Msk              (0xFFFFFFFFUL << TAMP_BKP20R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP20R                  TAMP_BKP20R_Msk

+

+/********************  Bits definition for TAMP_BKP21R register  ***************/

+#define TAMP_BKP21R_Pos              (0U)

+#define TAMP_BKP21R_Msk              (0xFFFFFFFFUL << TAMP_BKP21R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP21R                  TAMP_BKP21R_Msk

+

+/********************  Bits definition for TAMP_BKP22R register  ***************/

+#define TAMP_BKP22R_Pos              (0U)

+#define TAMP_BKP22R_Msk              (0xFFFFFFFFUL << TAMP_BKP22R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP22R                  TAMP_BKP22R_Msk

+

+/********************  Bits definition for TAMP_BKP23R register  ***************/

+#define TAMP_BKP23R_Pos              (0U)

+#define TAMP_BKP23R_Msk              (0xFFFFFFFFUL << TAMP_BKP23R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP23R                  TAMP_BKP23R_Msk

+

+/********************  Bits definition for TAMP_BKP24R register  ***************/

+#define TAMP_BKP24R_Pos              (0U)

+#define TAMP_BKP24R_Msk              (0xFFFFFFFFUL << TAMP_BKP24R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP24R                  TAMP_BKP24R_Msk

+

+/********************  Bits definition for TAMP_BKP25R register  ***************/

+#define TAMP_BKP25R_Pos              (0U)

+#define TAMP_BKP25R_Msk              (0xFFFFFFFFUL << TAMP_BKP25R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP25R                  TAMP_BKP25R_Msk

+

+/********************  Bits definition for TAMP_BKP26R register  ***************/

+#define TAMP_BKP26R_Pos              (0U)

+#define TAMP_BKP26R_Msk              (0xFFFFFFFFUL << TAMP_BKP26R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP26R                  TAMP_BKP26R_Msk

+

+/********************  Bits definition for TAMP_BKP27R register  ***************/

+#define TAMP_BKP27R_Pos              (0U)

+#define TAMP_BKP27R_Msk              (0xFFFFFFFFUL << TAMP_BKP27R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP27R                  TAMP_BKP27R_Msk

+

+/********************  Bits definition for TAMP_BKP28R register  ***************/

+#define TAMP_BKP28R_Pos              (0U)

+#define TAMP_BKP28R_Msk              (0xFFFFFFFFUL << TAMP_BKP28R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP28R                  TAMP_BKP28R_Msk

+

+/********************  Bits definition for TAMP_BKP29R register  ***************/

+#define TAMP_BKP29R_Pos              (0U)

+#define TAMP_BKP29R_Msk              (0xFFFFFFFFUL << TAMP_BKP29R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP29R                  TAMP_BKP29R_Msk

+

+/********************  Bits definition for TAMP_BKP30R register  ***************/

+#define TAMP_BKP30R_Pos              (0U)

+#define TAMP_BKP30R_Msk              (0xFFFFFFFFUL << TAMP_BKP30R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP30R                  TAMP_BKP30R_Msk

+

+/********************  Bits definition for TAMP_BKP31R register  ***************/

+#define TAMP_BKP31R_Pos              (0U)

+#define TAMP_BKP31R_Msk              (0xFFFFFFFFUL << TAMP_BKP31R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP31R                  TAMP_BKP31R_Msk

+

+/******************** Number of backup registers ******************************/

+#define TAMP_BKP_NUMBER_Pos             (5U)

+#define TAMP_BKP_NUMBER_Msk             (0x1UL << TAMP_BKP_NUMBER_Pos)         /*!< 0x00000080 */

+#define TAMP_BKP_NUMBER                 TAMP_BKP_NUMBER_Msk                    /*!< 32 BKPREG  */

+

+/******************************************************************************/

+/*                                                                            */

+/*                              SPDIF-RX Interface                            */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for SPDIF_CR register  ******************/

+#define SPDIFRX_CR_SPDIFEN_Pos      (0U)

+#define SPDIFRX_CR_SPDIFEN_Msk      (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)          /*!< 0x00000003 */

+#define SPDIFRX_CR_SPDIFEN          SPDIFRX_CR_SPDIFEN_Msk                     /*!<Peripheral Block Enable                      */

+#define SPDIFRX_CR_RXDMAEN_Pos      (2U)

+#define SPDIFRX_CR_RXDMAEN_Msk      (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)          /*!< 0x00000004 */

+#define SPDIFRX_CR_RXDMAEN          SPDIFRX_CR_RXDMAEN_Msk                     /*!<Receiver DMA Enable for data flow            */

+#define SPDIFRX_CR_RXSTEO_Pos       (3U)

+#define SPDIFRX_CR_RXSTEO_Msk       (0x1UL << SPDIFRX_CR_RXSTEO_Pos)           /*!< 0x00000008 */

+#define SPDIFRX_CR_RXSTEO           SPDIFRX_CR_RXSTEO_Msk                      /*!<Stereo Mode                                  */

+#define SPDIFRX_CR_DRFMT_Pos        (4U)

+#define SPDIFRX_CR_DRFMT_Msk        (0x3UL << SPDIFRX_CR_DRFMT_Pos)            /*!< 0x00000030 */

+#define SPDIFRX_CR_DRFMT            SPDIFRX_CR_DRFMT_Msk                       /*!<RX Data format                               */

+#define SPDIFRX_CR_PMSK_Pos         (6U)

+#define SPDIFRX_CR_PMSK_Msk         (0x1UL << SPDIFRX_CR_PMSK_Pos)             /*!< 0x00000040 */

+#define SPDIFRX_CR_PMSK             SPDIFRX_CR_PMSK_Msk                        /*!<Mask Parity error bit                        */

+#define SPDIFRX_CR_VMSK_Pos         (7U)

+#define SPDIFRX_CR_VMSK_Msk         (0x1UL << SPDIFRX_CR_VMSK_Pos)             /*!< 0x00000080 */

+#define SPDIFRX_CR_VMSK             SPDIFRX_CR_VMSK_Msk                        /*!<Mask of Validity bit                         */

+#define SPDIFRX_CR_CUMSK_Pos        (8U)

+#define SPDIFRX_CR_CUMSK_Msk        (0x1UL << SPDIFRX_CR_CUMSK_Pos)            /*!< 0x00000100 */

+#define SPDIFRX_CR_CUMSK            SPDIFRX_CR_CUMSK_Msk                       /*!<Mask of channel status and user bits         */

+#define SPDIFRX_CR_PTMSK_Pos        (9U)

+#define SPDIFRX_CR_PTMSK_Msk        (0x1UL << SPDIFRX_CR_PTMSK_Pos)            /*!< 0x00000200 */

+#define SPDIFRX_CR_PTMSK            SPDIFRX_CR_PTMSK_Msk                       /*!<Mask of Preamble Type bits                   */

+#define SPDIFRX_CR_CBDMAEN_Pos      (10U)

+#define SPDIFRX_CR_CBDMAEN_Msk      (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)          /*!< 0x00000400 */

+#define SPDIFRX_CR_CBDMAEN          SPDIFRX_CR_CBDMAEN_Msk                     /*!<Control Buffer DMA ENable for control flow   */

+#define SPDIFRX_CR_CHSEL_Pos        (11U)

+#define SPDIFRX_CR_CHSEL_Msk        (0x1UL << SPDIFRX_CR_CHSEL_Pos)            /*!< 0x00000800 */

+#define SPDIFRX_CR_CHSEL            SPDIFRX_CR_CHSEL_Msk                       /*!<Channel Selection                            */

+#define SPDIFRX_CR_NBTR_Pos         (12U)

+#define SPDIFRX_CR_NBTR_Msk         (0x3UL << SPDIFRX_CR_NBTR_Pos)             /*!< 0x00003000 */

+#define SPDIFRX_CR_NBTR             SPDIFRX_CR_NBTR_Msk                        /*!<Maximum allowed re-tries during synchronization phase */

+#define SPDIFRX_CR_WFA_Pos          (14U)

+#define SPDIFRX_CR_WFA_Msk          (0x1UL << SPDIFRX_CR_WFA_Pos)              /*!< 0x00004000 */

+#define SPDIFRX_CR_WFA              SPDIFRX_CR_WFA_Msk                         /*!<Wait For Activity     */

+#define SPDIFRX_CR_INSEL_Pos        (16U)

+#define SPDIFRX_CR_INSEL_Msk        (0x7UL << SPDIFRX_CR_INSEL_Pos)            /*!< 0x00070000 */

+#define SPDIFRX_CR_INSEL            SPDIFRX_CR_INSEL_Msk                       /*!<SPDIF input selection */

+#define SPDIFRX_CR_CKSEN_Pos        (20U)

+#define SPDIFRX_CR_CKSEN_Msk        (0x1UL << SPDIFRX_CR_CKSEN_Pos)            /*!< 0x00100000 */

+#define SPDIFRX_CR_CKSEN            SPDIFRX_CR_CKSEN_Msk                       /*!<Symbol Clock Enable */

+#define SPDIFRX_CR_CKSBKPEN_Pos     (21U)

+#define SPDIFRX_CR_CKSBKPEN_Msk     (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)         /*!< 0x00200000 */

+#define SPDIFRX_CR_CKSBKPEN         SPDIFRX_CR_CKSBKPEN_Msk                    /*!<Backup Symbol Clock Enable */

+

+/*******************  Bit definition for SPDIFRX_IMR register  *******************/

+#define SPDIFRX_IMR_RXNEIE_Pos      (0U)

+#define SPDIFRX_IMR_RXNEIE_Msk      (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)          /*!< 0x00000001 */

+#define SPDIFRX_IMR_RXNEIE          SPDIFRX_IMR_RXNEIE_Msk                     /*!<RXNE interrupt enable                              */

+#define SPDIFRX_IMR_CSRNEIE_Pos     (1U)

+#define SPDIFRX_IMR_CSRNEIE_Msk     (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)         /*!< 0x00000002 */

+#define SPDIFRX_IMR_CSRNEIE         SPDIFRX_IMR_CSRNEIE_Msk                    /*!<Control Buffer Ready Interrupt Enable              */

+#define SPDIFRX_IMR_PERRIE_Pos      (2U)

+#define SPDIFRX_IMR_PERRIE_Msk      (0x1UL << SPDIFRX_IMR_PERRIE_Pos)          /*!< 0x00000004 */

+#define SPDIFRX_IMR_PERRIE          SPDIFRX_IMR_PERRIE_Msk                     /*!<Parity error interrupt enable                      */

+#define SPDIFRX_IMR_OVRIE_Pos       (3U)

+#define SPDIFRX_IMR_OVRIE_Msk       (0x1UL << SPDIFRX_IMR_OVRIE_Pos)           /*!< 0x00000008 */

+#define SPDIFRX_IMR_OVRIE           SPDIFRX_IMR_OVRIE_Msk                      /*!<Overrun error Interrupt Enable                     */

+#define SPDIFRX_IMR_SBLKIE_Pos      (4U)

+#define SPDIFRX_IMR_SBLKIE_Msk      (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)          /*!< 0x00000010 */

+#define SPDIFRX_IMR_SBLKIE          SPDIFRX_IMR_SBLKIE_Msk                     /*!<Synchronization Block Detected Interrupt Enable    */

+#define SPDIFRX_IMR_SYNCDIE_Pos     (5U)

+#define SPDIFRX_IMR_SYNCDIE_Msk     (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)         /*!< 0x00000020 */

+#define SPDIFRX_IMR_SYNCDIE         SPDIFRX_IMR_SYNCDIE_Msk                    /*!<Synchronization Done                               */

+#define SPDIFRX_IMR_IFEIE_Pos       (6U)

+#define SPDIFRX_IMR_IFEIE_Msk       (0x1UL << SPDIFRX_IMR_IFEIE_Pos)           /*!< 0x00000040 */

+#define SPDIFRX_IMR_IFEIE           SPDIFRX_IMR_IFEIE_Msk                      /*!<Serial Interface Error Interrupt Enable            */

+

+/*******************  Bit definition for SPDIFRX_SR register  *******************/

+#define SPDIFRX_SR_RXNE_Pos         (0U)

+#define SPDIFRX_SR_RXNE_Msk         (0x1UL << SPDIFRX_SR_RXNE_Pos)             /*!< 0x00000001 */

+#define SPDIFRX_SR_RXNE             SPDIFRX_SR_RXNE_Msk                        /*!<Read data register not empty                          */

+#define SPDIFRX_SR_CSRNE_Pos        (1U)

+#define SPDIFRX_SR_CSRNE_Msk        (0x1UL << SPDIFRX_SR_CSRNE_Pos)            /*!< 0x00000002 */

+#define SPDIFRX_SR_CSRNE            SPDIFRX_SR_CSRNE_Msk                       /*!<The Control Buffer register is not empty              */

+#define SPDIFRX_SR_PERR_Pos         (2U)

+#define SPDIFRX_SR_PERR_Msk         (0x1UL << SPDIFRX_SR_PERR_Pos)             /*!< 0x00000004 */

+#define SPDIFRX_SR_PERR             SPDIFRX_SR_PERR_Msk                        /*!<Parity error                                          */

+#define SPDIFRX_SR_OVR_Pos          (3U)

+#define SPDIFRX_SR_OVR_Msk          (0x1UL << SPDIFRX_SR_OVR_Pos)              /*!< 0x00000008 */

+#define SPDIFRX_SR_OVR              SPDIFRX_SR_OVR_Msk                         /*!<Overrun error                                         */

+#define SPDIFRX_SR_SBD_Pos          (4U)

+#define SPDIFRX_SR_SBD_Msk          (0x1UL << SPDIFRX_SR_SBD_Pos)              /*!< 0x00000010 */

+#define SPDIFRX_SR_SBD              SPDIFRX_SR_SBD_Msk                         /*!<Synchronization Block Detected                        */

+#define SPDIFRX_SR_SYNCD_Pos        (5U)

+#define SPDIFRX_SR_SYNCD_Msk        (0x1UL << SPDIFRX_SR_SYNCD_Pos)            /*!< 0x00000020 */

+#define SPDIFRX_SR_SYNCD            SPDIFRX_SR_SYNCD_Msk                       /*!<Synchronization Done                                  */

+#define SPDIFRX_SR_FERR_Pos         (6U)

+#define SPDIFRX_SR_FERR_Msk         (0x1UL << SPDIFRX_SR_FERR_Pos)             /*!< 0x00000040 */

+#define SPDIFRX_SR_FERR             SPDIFRX_SR_FERR_Msk                        /*!<Framing error                                         */

+#define SPDIFRX_SR_SERR_Pos         (7U)

+#define SPDIFRX_SR_SERR_Msk         (0x1UL << SPDIFRX_SR_SERR_Pos)             /*!< 0x00000080 */

+#define SPDIFRX_SR_SERR             SPDIFRX_SR_SERR_Msk                        /*!<Synchronization error                                 */

+#define SPDIFRX_SR_TERR_Pos         (8U)

+#define SPDIFRX_SR_TERR_Msk         (0x1UL << SPDIFRX_SR_TERR_Pos)             /*!< 0x00000100 */

+#define SPDIFRX_SR_TERR             SPDIFRX_SR_TERR_Msk                        /*!<Time-out error                                        */

+#define SPDIFRX_SR_WIDTH5_Pos       (16U)

+#define SPDIFRX_SR_WIDTH5_Msk       (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)        /*!< 0x7FFF0000 */

+#define SPDIFRX_SR_WIDTH5           SPDIFRX_SR_WIDTH5_Msk                      /*!<Duration of 5 symbols counted with spdif_clk          */

+

+/*******************  Bit definition for SPDIFRX_IFCR register  *******************/

+#define SPDIFRX_IFCR_PERRCF_Pos     (2U)

+#define SPDIFRX_IFCR_PERRCF_Msk     (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)         /*!< 0x00000004 */

+#define SPDIFRX_IFCR_PERRCF         SPDIFRX_IFCR_PERRCF_Msk                    /*!<Clears the Parity error flag                         */

+#define SPDIFRX_IFCR_OVRCF_Pos      (3U)

+#define SPDIFRX_IFCR_OVRCF_Msk      (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)          /*!< 0x00000008 */

+#define SPDIFRX_IFCR_OVRCF          SPDIFRX_IFCR_OVRCF_Msk                     /*!<Clears the Overrun error flag                        */

+#define SPDIFRX_IFCR_SBDCF_Pos      (4U)

+#define SPDIFRX_IFCR_SBDCF_Msk      (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)          /*!< 0x00000010 */

+#define SPDIFRX_IFCR_SBDCF          SPDIFRX_IFCR_SBDCF_Msk                     /*!<Clears the Synchronization Block Detected flag       */

+#define SPDIFRX_IFCR_SYNCDCF_Pos    (5U)

+#define SPDIFRX_IFCR_SYNCDCF_Msk    (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)        /*!< 0x00000020 */

+#define SPDIFRX_IFCR_SYNCDCF        SPDIFRX_IFCR_SYNCDCF_Msk                   /*!<Clears the Synchronization Done flag                 */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/

+#define SPDIFRX_DR0_DR_Pos          (0U)

+#define SPDIFRX_DR0_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)         /*!< 0x00FFFFFF */

+#define SPDIFRX_DR0_DR              SPDIFRX_DR0_DR_Msk                         /*!<Data value            */

+#define SPDIFRX_DR0_PE_Pos          (24U)

+#define SPDIFRX_DR0_PE_Msk          (0x1UL << SPDIFRX_DR0_PE_Pos)              /*!< 0x01000000 */

+#define SPDIFRX_DR0_PE              SPDIFRX_DR0_PE_Msk                         /*!<Parity Error bit      */

+#define SPDIFRX_DR0_V_Pos           (25U)

+#define SPDIFRX_DR0_V_Msk           (0x1UL << SPDIFRX_DR0_V_Pos)               /*!< 0x02000000 */

+#define SPDIFRX_DR0_V               SPDIFRX_DR0_V_Msk                          /*!<Validity bit          */

+#define SPDIFRX_DR0_U_Pos           (26U)

+#define SPDIFRX_DR0_U_Msk           (0x1UL << SPDIFRX_DR0_U_Pos)               /*!< 0x04000000 */

+#define SPDIFRX_DR0_U               SPDIFRX_DR0_U_Msk                          /*!<User bit              */

+#define SPDIFRX_DR0_C_Pos           (27U)

+#define SPDIFRX_DR0_C_Msk           (0x1UL << SPDIFRX_DR0_C_Pos)               /*!< 0x08000000 */

+#define SPDIFRX_DR0_C               SPDIFRX_DR0_C_Msk                          /*!<Channel Status bit    */

+#define SPDIFRX_DR0_PT_Pos          (28U)

+#define SPDIFRX_DR0_PT_Msk          (0x3UL << SPDIFRX_DR0_PT_Pos)              /*!< 0x30000000 */

+#define SPDIFRX_DR0_PT              SPDIFRX_DR0_PT_Msk                         /*!<Preamble Type         */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/

+#define SPDIFRX_DR1_DR_Pos          (8U)

+#define SPDIFRX_DR1_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)         /*!< 0xFFFFFF00 */

+#define SPDIFRX_DR1_DR              SPDIFRX_DR1_DR_Msk                         /*!<Data value            */

+#define SPDIFRX_DR1_PT_Pos          (4U)

+#define SPDIFRX_DR1_PT_Msk          (0x3UL << SPDIFRX_DR1_PT_Pos)              /*!< 0x00000030 */

+#define SPDIFRX_DR1_PT              SPDIFRX_DR1_PT_Msk                         /*!<Preamble Type         */

+#define SPDIFRX_DR1_C_Pos           (3U)

+#define SPDIFRX_DR1_C_Msk           (0x1UL << SPDIFRX_DR1_C_Pos)               /*!< 0x00000008 */

+#define SPDIFRX_DR1_C               SPDIFRX_DR1_C_Msk                          /*!<Channel Status bit    */

+#define SPDIFRX_DR1_U_Pos           (2U)

+#define SPDIFRX_DR1_U_Msk           (0x1UL << SPDIFRX_DR1_U_Pos)               /*!< 0x00000004 */

+#define SPDIFRX_DR1_U               SPDIFRX_DR1_U_Msk                          /*!<User bit              */

+#define SPDIFRX_DR1_V_Pos           (1U)

+#define SPDIFRX_DR1_V_Msk           (0x1UL << SPDIFRX_DR1_V_Pos)               /*!< 0x00000002 */

+#define SPDIFRX_DR1_V               SPDIFRX_DR1_V_Msk                          /*!<Validity bit          */

+#define SPDIFRX_DR1_PE_Pos          (0U)

+#define SPDIFRX_DR1_PE_Msk          (0x1UL << SPDIFRX_DR1_PE_Pos)              /*!< 0x00000001 */

+#define SPDIFRX_DR1_PE              SPDIFRX_DR1_PE_Msk                         /*!<Parity Error bit      */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/

+#define SPDIFRX_DR1_DRNL1_Pos       (16U)

+#define SPDIFRX_DR1_DRNL1_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)        /*!< 0xFFFF0000 */

+#define SPDIFRX_DR1_DRNL1           SPDIFRX_DR1_DRNL1_Msk                      /*!<Data value Channel B      */

+#define SPDIFRX_DR1_DRNL2_Pos       (0U)

+#define SPDIFRX_DR1_DRNL2_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)        /*!< 0x0000FFFF */

+#define SPDIFRX_DR1_DRNL2           SPDIFRX_DR1_DRNL2_Msk                      /*!<Data value Channel A      */

+

+/*******************  Bit definition for SPDIFRX_CSR register   *******************/

+#define SPDIFRX_CSR_USR_Pos         (0U)

+#define SPDIFRX_CSR_USR_Msk         (0xFFFFUL << SPDIFRX_CSR_USR_Pos)          /*!< 0x0000FFFF */

+#define SPDIFRX_CSR_USR             SPDIFRX_CSR_USR_Msk                        /*!<User data information           */

+#define SPDIFRX_CSR_CS_Pos          (16U)

+#define SPDIFRX_CSR_CS_Msk          (0xFFUL << SPDIFRX_CSR_CS_Pos)             /*!< 0x00FF0000 */

+#define SPDIFRX_CSR_CS              SPDIFRX_CSR_CS_Msk                         /*!<Channel A status information    */

+#define SPDIFRX_CSR_SOB_Pos         (24U)

+#define SPDIFRX_CSR_SOB_Msk         (0x1UL << SPDIFRX_CSR_SOB_Pos)             /*!< 0x01000000 */

+#define SPDIFRX_CSR_SOB             SPDIFRX_CSR_SOB_Msk                        /*!<Start Of Block                  */

+

+/*******************  Bit definition for SPDIFRX_DIR register    *******************/

+#define SPDIFRX_DIR_THI_Pos         (0U)

+#define SPDIFRX_DIR_THI_Msk         (0x1FFFUL << SPDIFRX_DIR_THI_Pos)          /*!< 0x00001FFF */

+#define SPDIFRX_DIR_THI             SPDIFRX_DIR_THI_Msk                        /*!<Threshold LOW      */

+#define SPDIFRX_DIR_TLO_Pos         (16U)

+#define SPDIFRX_DIR_TLO_Msk         (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)          /*!< 0x1FFF0000 */

+#define SPDIFRX_DIR_TLO             SPDIFRX_DIR_TLO_Msk                        /*!<Threshold HIGH     */

+

+/*******************  Bit definition for SPDIFRX_VERR register    *******************/

+#define SPDIFRX_VERR_MINREV_Pos     (0U)

+#define SPDIFRX_VERR_MINREV_Msk     (0xFUL << SPDIFRX_VERR_MINREV_Pos)         /*!< 0x0000000F */

+#define SPDIFRX_VERR_MINREV         SPDIFRX_VERR_MINREV_Msk                    /*!<SPDIFRX Minor revision     */

+#define SPDIFRX_VERR_MAJREV_Pos     (4U)

+#define SPDIFRX_VERR_MAJREV_Msk     (0xFUL << SPDIFRX_VERR_MAJREV_Pos)         /*!< 0x000000F0 */

+#define SPDIFRX_VERR_MAJREV         SPDIFRX_VERR_MAJREV_Msk                    /*!<SPDIFRX Major revision     */

+

+/*******************  Bit definition for SPDIFRX_IDR register    *******************/

+#define SPDIFRX_IDR_ID_Pos          (0U)

+#define SPDIFRX_IDR_ID_Msk          (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos)       /*!< 0xFFFFFFFF */

+#define SPDIFRX_IDR_ID              SPDIFRX_IDR_ID_Msk                         /*!<SPDIFRX identifier     */

+

+/*******************  Bit definition for SPDIFRX_SIDR register    *******************/

+#define SPDIFRX_SIDR_SID_Pos        (0U)

+#define SPDIFRX_SIDR_SID_Msk        (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos)     /*!< 0xFFFFFFFF */

+#define SPDIFRX_SIDR_SID            SPDIFRX_SIDR_SID_Msk                       /*!<Size of the memory region allocated to SPDIFRX registers */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          Serial Audio Interface                            */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  SAI VERSION  ********************************/

+#define SAI_VER_V2_1

+

+/********************  Bit definition for SAI_GCR register  *******************/

+#define SAI_GCR_SYNCIN_Pos         (0U)

+#define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000003 */

+#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */

+#define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */

+#define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */

+

+#define SAI_GCR_SYNCOUT_Pos        (4U)

+#define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000030 */

+#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */

+#define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */

+#define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */

+

+/*******************  Bit definition for SAI_xCR1 register  *******************/

+#define SAI_xCR1_MODE_Pos          (0U)

+#define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */

+#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */

+#define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */

+#define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */

+

+#define SAI_xCR1_PRTCFG_Pos        (2U)

+#define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */

+#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */

+#define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */

+#define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */

+

+#define SAI_xCR1_DS_Pos            (5U)

+#define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */

+#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */

+#define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */

+#define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */

+#define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */

+

+#define SAI_xCR1_LSBFIRST_Pos      (8U)

+#define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */

+#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */

+#define SAI_xCR1_CKSTR_Pos         (9U)

+#define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */

+#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */

+

+#define SAI_xCR1_SYNCEN_Pos        (10U)

+#define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */

+#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */

+#define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */

+#define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */

+

+#define SAI_xCR1_MONO_Pos          (12U)

+#define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */

+#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */

+#define SAI_xCR1_OUTDRIV_Pos       (13U)

+#define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */

+#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */

+#define SAI_xCR1_SAIEN_Pos         (16U)

+#define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */

+#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */

+#define SAI_xCR1_DMAEN_Pos         (17U)

+#define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */

+#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */

+#define SAI_xCR1_NODIV_Pos         (19U)

+#define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */

+#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */

+

+#define SAI_xCR1_MCKDIV_Pos        (20U)

+#define SAI_xCR1_MCKDIV_Msk        (0x3FUL << SAI_xCR1_MCKDIV_Pos)             /*!< 0x03F00000 */

+#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[5:0] (Master ClocK Divider)  */

+#define SAI_xCR1_MCKDIV_0          (0x01UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00100000 */

+#define SAI_xCR1_MCKDIV_1          (0x02UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00200000 */

+#define SAI_xCR1_MCKDIV_2          (0x04UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00400000 */

+#define SAI_xCR1_MCKDIV_3          (0x08UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00800000 */

+#define SAI_xCR1_MCKDIV_4          (0x10UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x01000000 */

+#define SAI_xCR1_MCKDIV_5          (0x20UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x02000000 */

+

+#define SAI_xCR1_MCKEN_Pos         (27U)

+#define SAI_xCR1_MCKEN_Msk         (0x1UL << SAI_xCR1_MCKEN_Pos)               /*!< 0x08000000 */

+#define SAI_xCR1_MCKEN             SAI_xCR1_MCKEN_Msk                          /*!<Master ClocK enable */

+

+#define SAI_xCR1_OSR_Pos           (26U)

+#define SAI_xCR1_OSR_Msk           (0x1UL << SAI_xCR1_OSR_Pos)                 /*!< 0x04000000 */

+#define SAI_xCR1_OSR               SAI_xCR1_OSR_Msk                            /*!<OverSampling Ratio for master clock  */

+

+/* Legacy define */

+#define  SAI_xCR1_NOMCK               SAI_xCR1_NODIV

+

+/*******************  Bit definition for SAI_xCR2 register  *******************/

+#define SAI_xCR2_FTH_Pos           (0U)

+#define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */

+#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */

+#define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */

+#define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */

+#define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */

+

+#define SAI_xCR2_FFLUSH_Pos        (3U)

+#define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */

+#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */

+#define SAI_xCR2_TRIS_Pos          (4U)

+#define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */

+#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */

+#define SAI_xCR2_MUTE_Pos          (5U)

+#define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */

+#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */

+#define SAI_xCR2_MUTEVAL_Pos       (6U)

+#define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */

+#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */

+

+#define SAI_xCR2_MUTECNT_Pos       (7U)

+#define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */

+#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */

+#define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */

+#define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */

+#define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */

+#define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */

+#define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */

+#define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */

+

+#define SAI_xCR2_CPL_Pos           (13U)

+#define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */

+#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */

+

+#define SAI_xCR2_COMP_Pos          (14U)

+#define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */

+#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */

+#define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */

+#define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */

+

+/******************  Bit definition for SAI_xFRCR register  *******************/

+#define SAI_xFRCR_FRL_Pos          (0U)

+#define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */

+#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](FRame Length)  */

+#define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */

+#define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */

+#define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */

+#define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */

+#define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */

+#define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */

+#define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */

+#define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */

+

+#define SAI_xFRCR_FSALL_Pos        (8U)

+#define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */

+#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FSALL[6:0] (Frame Synchronization Active Level Length)  */

+#define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */

+#define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */

+#define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */

+#define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */

+#define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */

+#define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */

+#define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */

+

+#define SAI_xFRCR_FSDEF_Pos        (16U)

+#define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */

+#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!<Frame Synchronization Definition  */

+#define SAI_xFRCR_FSPOL_Pos        (17U)

+#define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */

+#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */

+#define SAI_xFRCR_FSOFF_Pos        (18U)

+#define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */

+#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */

+

+/* Legacy define */

+#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL

+

+/******************  Bit definition for SAI_xSLOTR register  *******************/

+#define SAI_xSLOTR_FBOFF_Pos       (0U)

+#define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */

+#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FBOFF[4:0](First Bit Offset)  */

+#define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */

+#define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */

+#define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */

+#define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */

+#define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */

+

+#define SAI_xSLOTR_SLOTSZ_Pos      (6U)

+#define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */

+#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */

+#define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */

+#define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */

+

+#define SAI_xSLOTR_NBSLOT_Pos      (8U)

+#define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */

+#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */

+#define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */

+#define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */

+#define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */

+#define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */

+

+#define SAI_xSLOTR_SLOTEN_Pos      (16U)

+#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */

+#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */

+

+/*******************  Bit definition for SAI_xIMR register  *******************/

+#define SAI_xIMR_OVRUDRIE_Pos      (0U)

+#define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */

+#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */

+#define SAI_xIMR_MUTEDETIE_Pos     (1U)

+#define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */

+#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */

+#define SAI_xIMR_WCKCFGIE_Pos      (2U)

+#define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */

+#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */

+#define SAI_xIMR_FREQIE_Pos        (3U)

+#define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */

+#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */

+#define SAI_xIMR_CNRDYIE_Pos       (4U)

+#define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */

+#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */

+#define SAI_xIMR_AFSDETIE_Pos      (5U)

+#define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */

+#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */

+#define SAI_xIMR_LFSDETIE_Pos      (6U)

+#define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */

+#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */

+

+/********************  Bit definition for SAI_xSR register  *******************/

+#define SAI_xSR_OVRUDR_Pos         (0U)

+#define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */

+#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */

+#define SAI_xSR_MUTEDET_Pos        (1U)

+#define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */

+#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */

+#define SAI_xSR_WCKCFG_Pos         (2U)

+#define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */

+#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */

+#define SAI_xSR_FREQ_Pos           (3U)

+#define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */

+#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */

+#define SAI_xSR_CNRDY_Pos          (4U)

+#define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */

+#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */

+#define SAI_xSR_AFSDET_Pos         (5U)

+#define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */

+#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */

+#define SAI_xSR_LFSDET_Pos         (6U)

+#define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */

+#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */

+

+#define SAI_xSR_FLVL_Pos           (16U)

+#define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */

+#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */

+#define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */

+#define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */

+#define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */

+

+/******************  Bit definition for SAI_xCLRFR register  ******************/

+#define SAI_xCLRFR_COVRUDR_Pos     (0U)

+#define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */

+#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */

+#define SAI_xCLRFR_CMUTEDET_Pos    (1U)

+#define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */

+#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */

+#define SAI_xCLRFR_CWCKCFG_Pos     (2U)

+#define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */

+#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */

+#define SAI_xCLRFR_CFREQ_Pos       (3U)

+#define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */

+#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */

+#define SAI_xCLRFR_CCNRDY_Pos      (4U)

+#define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */

+#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */

+#define SAI_xCLRFR_CAFSDET_Pos     (5U)

+#define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */

+#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */

+#define SAI_xCLRFR_CLFSDET_Pos     (6U)

+#define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */

+#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */

+

+/******************  Bit definition for SAI_xDR register  *********************/

+#define SAI_xDR_DATA_Pos           (0U)

+#define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */

+#define SAI_xDR_DATA               SAI_xDR_DATA_Msk

+

+/*******************  Bit definition for SAI_PDMCR register  ******************/

+#define SAI_PDMCR_PDMEN_Pos        (0U)

+#define SAI_PDMCR_PDMEN_Msk        (0x1UL << SAI_PDMCR_PDMEN_Pos)              /*!< 0x00000001 */

+#define SAI_PDMCR_PDMEN            SAI_PDMCR_PDMEN_Msk                         /*!<PDM Enable                                          */

+

+#define SAI_PDMCR_MICNBR_Pos       (4U)

+#define SAI_PDMCR_MICNBR_Msk       (0x3UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000030 */

+#define SAI_PDMCR_MICNBR           SAI_PDMCR_MICNBR_Msk                        /*!<Number of microphones                               */

+#define SAI_PDMCR_MICNBR_0         (0x1UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000010 */

+#define SAI_PDMCR_MICNBR_1         (0x2UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000020 */

+

+#define SAI_PDMCR_CKEN1_Pos        (8U)

+#define SAI_PDMCR_CKEN1_Msk        (0x1UL << SAI_PDMCR_CKEN1_Pos)              /*!< 0x00000100 */

+#define SAI_PDMCR_CKEN1            SAI_PDMCR_CKEN1_Msk                         /*!<Clock enable of bitstream clock number 1            */

+#define SAI_PDMCR_CKEN2_Pos        (9U)

+#define SAI_PDMCR_CKEN2_Msk        (0x1UL << SAI_PDMCR_CKEN2_Pos)              /*!< 0x00000200 */

+#define SAI_PDMCR_CKEN2            SAI_PDMCR_CKEN2_Msk                         /*!<Clock enable of bitstream clock number 2            */

+#define SAI_PDMCR_CKEN3_Pos        (10U)

+#define SAI_PDMCR_CKEN3_Msk        (0x1UL << SAI_PDMCR_CKEN3_Pos)              /*!< 0x00000400 */

+#define SAI_PDMCR_CKEN3            SAI_PDMCR_CKEN3_Msk                         /*!<Clock enable of bitstream clock number 3            */

+#define SAI_PDMCR_CKEN4_Pos        (11U)

+#define SAI_PDMCR_CKEN4_Msk        (0x1UL << SAI_PDMCR_CKEN4_Pos)              /*!< 0x00000800 */

+#define SAI_PDMCR_CKEN4            SAI_PDMCR_CKEN4_Msk                         /*!<Clock enable of bitstream clock number 4            */

+

+/******************  Bit definition for SAI_PDMDLY register  ******************/

+#define SAI_PDMDLY_DLYM1L_Pos      (0U)

+#define SAI_PDMDLY_DLYM1L_Msk      (0x7UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000007 */

+#define SAI_PDMDLY_DLYM1L          SAI_PDMDLY_DLYM1L_Msk                       /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */

+#define SAI_PDMDLY_DLYM1L_0        (0x1UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000001 */

+#define SAI_PDMDLY_DLYM1L_1        (0x2UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000002 */

+#define SAI_PDMDLY_DLYM1L_2        (0x4UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000004 */

+

+#define SAI_PDMDLY_DLYM1R_Pos      (4U)

+#define SAI_PDMDLY_DLYM1R_Msk      (0x7UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000070 */

+#define SAI_PDMDLY_DLYM1R          SAI_PDMDLY_DLYM1R_Msk                       /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */

+#define SAI_PDMDLY_DLYM1R_0        (0x1UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000010 */

+#define SAI_PDMDLY_DLYM1R_1        (0x2UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000020 */

+#define SAI_PDMDLY_DLYM1R_2        (0x4UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000040 */

+

+#define SAI_PDMDLY_DLYM2L_Pos      (8U)

+#define SAI_PDMDLY_DLYM2L_Msk      (0x7UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000700 */

+#define SAI_PDMDLY_DLYM2L          SAI_PDMDLY_DLYM2L_Msk                       /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */

+#define SAI_PDMDLY_DLYM2L_0        (0x1UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000100 */

+#define SAI_PDMDLY_DLYM2L_1        (0x2UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000200 */

+#define SAI_PDMDLY_DLYM2L_2        (0x4UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000400 */

+

+#define SAI_PDMDLY_DLYM2R_Pos      (12U)

+#define SAI_PDMDLY_DLYM2R_Msk      (0x7UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00007000 */

+#define SAI_PDMDLY_DLYM2R          SAI_PDMDLY_DLYM2R_Msk                       /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/

+#define SAI_PDMDLY_DLYM2R_0        (0x1UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00001000 */

+#define SAI_PDMDLY_DLYM2R_1        (0x2UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00002000 */

+#define SAI_PDMDLY_DLYM2R_2        (0x4UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00004000 */

+

+#define SAI_PDMDLY_DLYM3L_Pos      (16U)

+#define SAI_PDMDLY_DLYM3L_Msk      (0x7UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00070000 */

+#define SAI_PDMDLY_DLYM3L          SAI_PDMDLY_DLYM3L_Msk                       /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/

+#define SAI_PDMDLY_DLYM3L_0        (0x1UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00010000 */

+#define SAI_PDMDLY_DLYM3L_1        (0x2UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00020000 */

+#define SAI_PDMDLY_DLYM3L_2        (0x4UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00040000 */

+

+#define SAI_PDMDLY_DLYM3R_Pos      (20U)

+#define SAI_PDMDLY_DLYM3R_Msk      (0x7UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00700000 */

+#define SAI_PDMDLY_DLYM3R          SAI_PDMDLY_DLYM3R_Msk                       /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/

+#define SAI_PDMDLY_DLYM3R_0        (0x1UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00100000 */

+#define SAI_PDMDLY_DLYM3R_1        (0x2UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00200000 */

+#define SAI_PDMDLY_DLYM3R_2        (0x4UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00400000 */

+

+#define SAI_PDMDLY_DLYM4L_Pos      (24U)

+#define SAI_PDMDLY_DLYM4L_Msk      (0x7UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x07000000 */

+#define SAI_PDMDLY_DLYM4L          SAI_PDMDLY_DLYM4L_Msk                       /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/

+#define SAI_PDMDLY_DLYM4L_0        (0x1UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x01000000 */

+#define SAI_PDMDLY_DLYM4L_1        (0x2UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x02000000 */

+#define SAI_PDMDLY_DLYM4L_2        (0x4UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x04000000 */

+

+#define SAI_PDMDLY_DLYM4R_Pos      (28U)

+#define SAI_PDMDLY_DLYM4R_Msk      (0x7UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x70000000 */

+#define SAI_PDMDLY_DLYM4R          SAI_PDMDLY_DLYM4R_Msk                       /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/

+#define SAI_PDMDLY_DLYM4R_0        (0x1UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x10000000 */

+#define SAI_PDMDLY_DLYM4R_1        (0x2UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x20000000 */

+#define SAI_PDMDLY_DLYM4R_2        (0x4UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x40000000 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           SDMMC Interface                                  */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for SDMMC_POWER register  ******************/

+#define SDMMC_POWER_PWRCTRL_Pos          (0U)

+#define SDMMC_POWER_PWRCTRL_Msk          (0x3UL << SDMMC_POWER_PWRCTRL_Pos)    /*!< 0x00000003 */

+#define SDMMC_POWER_PWRCTRL              SDMMC_POWER_PWRCTRL_Msk               /*!<PWRCTRL[1:0] bits (Power supply control bits) */

+#define SDMMC_POWER_PWRCTRL_0            (0x1UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000001 */

+#define SDMMC_POWER_PWRCTRL_1            (0x2UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000002 */

+#define SDMMC_POWER_VSWITCH_Pos          (2U)

+#define SDMMC_POWER_VSWITCH_Msk          (0x1UL << SDMMC_POWER_VSWITCH_Pos)    /*!< 0x00000004 */

+#define SDMMC_POWER_VSWITCH              SDMMC_POWER_VSWITCH_Msk               /*!<Voltage switch sequence start */

+#define SDMMC_POWER_VSWITCHEN_Pos        (3U)

+#define SDMMC_POWER_VSWITCHEN_Msk        (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)  /*!< 0x00000008 */

+#define SDMMC_POWER_VSWITCHEN            SDMMC_POWER_VSWITCHEN_Msk             /*!<Voltage switch procedure enable */

+#define SDMMC_POWER_DIRPOL_Pos           (4U)

+#define SDMMC_POWER_DIRPOL_Msk           (0x1UL << SDMMC_POWER_DIRPOL_Pos)     /*!< 0x00000010 */

+#define SDMMC_POWER_DIRPOL               SDMMC_POWER_DIRPOL_Msk                /*!<Data and Command direction signals polarity selection */

+

+/******************  Bit definition for SDMMC_CLKCR register  ******************/

+#define SDMMC_CLKCR_CLKDIV_Pos           (0U)

+#define SDMMC_CLKCR_CLKDIV_Msk           (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)   /*!< 0x000003FF */

+#define SDMMC_CLKCR_CLKDIV               SDMMC_CLKCR_CLKDIV_Msk                /*!<Clock divide factor             */

+#define SDMMC_CLKCR_PWRSAV_Pos           (12U)

+#define SDMMC_CLKCR_PWRSAV_Msk           (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)     /*!< 0x00001000 */

+#define SDMMC_CLKCR_PWRSAV               SDMMC_CLKCR_PWRSAV_Msk                /*!<Power saving configuration bit  */

+

+#define SDMMC_CLKCR_WIDBUS_Pos           (14U)

+#define SDMMC_CLKCR_WIDBUS_Msk           (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)     /*!< 0x0000C000 */

+#define SDMMC_CLKCR_WIDBUS               SDMMC_CLKCR_WIDBUS_Msk                /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */

+#define SDMMC_CLKCR_WIDBUS_0             (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00004000 */

+#define SDMMC_CLKCR_WIDBUS_1             (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00008000 */

+

+#define SDMMC_CLKCR_NEGEDGE_Pos          (16U)

+#define SDMMC_CLKCR_NEGEDGE_Msk          (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)    /*!< 0x00010000 */

+#define SDMMC_CLKCR_NEGEDGE              SDMMC_CLKCR_NEGEDGE_Msk               /*!<SDMMC_CK dephasing selection bit */

+#define SDMMC_CLKCR_HWFC_EN_Pos          (17U)

+#define SDMMC_CLKCR_HWFC_EN_Msk          (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)    /*!< 0x00020000 */

+#define SDMMC_CLKCR_HWFC_EN              SDMMC_CLKCR_HWFC_EN_Msk               /*!<HW Flow Control enable           */

+#define SDMMC_CLKCR_DDR_Pos              (18U)

+#define SDMMC_CLKCR_DDR_Msk              (0x1UL << SDMMC_CLKCR_DDR_Pos)        /*!< 0x00040000 */

+#define SDMMC_CLKCR_DDR                  SDMMC_CLKCR_DDR_Msk                   /*!<Data rate signaling selection    */

+#define SDMMC_CLKCR_BUSSPEED_Pos         (19U)

+#define SDMMC_CLKCR_BUSSPEED_Msk         (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)   /*!< 0x00080000 */

+#define SDMMC_CLKCR_BUSSPEED             SDMMC_CLKCR_BUSSPEED_Msk              /*!<Bus speed mode selection         */

+#define SDMMC_CLKCR_SELCLKRX_Pos         (20U)

+#define SDMMC_CLKCR_SELCLKRX_Msk         (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)   /*!< 0x00300000 */

+#define SDMMC_CLKCR_SELCLKRX             SDMMC_CLKCR_SELCLKRX_Msk              /*!<SELCLKRX[1:0] bits (Receive clock selection) */

+#define SDMMC_CLKCR_SELCLKRX_0           (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00100000 */

+#define SDMMC_CLKCR_SELCLKRX_1           (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00200000 */

+

+/*******************  Bit definition for SDMMC_ARG register  *******************/

+#define SDMMC_ARG_CMDARG_Pos             (0U)

+#define SDMMC_ARG_CMDARG_Msk             (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_ARG_CMDARG                 SDMMC_ARG_CMDARG_Msk                  /*!<Command argument */

+

+/*******************  Bit definition for SDMMC_CMD register  *******************/

+#define SDMMC_CMD_CMDINDEX_Pos           (0U)

+#define SDMMC_CMD_CMDINDEX_Msk           (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)    /*!< 0x0000003F */

+#define SDMMC_CMD_CMDINDEX               SDMMC_CMD_CMDINDEX_Msk                /*!<Command Index                               */

+#define SDMMC_CMD_CMDTRANS_Pos           (6U)

+#define SDMMC_CMD_CMDTRANS_Msk           (0x1UL << SDMMC_CMD_CMDTRANS_Pos)     /*!< 0x00000040 */

+#define SDMMC_CMD_CMDTRANS               SDMMC_CMD_CMDTRANS_Msk                /*!<CPSM Treats command as a Data Transfer      */

+#define SDMMC_CMD_CMDSTOP_Pos            (7U)

+#define SDMMC_CMD_CMDSTOP_Msk            (0x1UL << SDMMC_CMD_CMDSTOP_Pos)      /*!< 0x00000080 */

+#define SDMMC_CMD_CMDSTOP                SDMMC_CMD_CMDSTOP_Msk                 /*!<CPSM Treats command as a Stop               */

+

+#define SDMMC_CMD_WAITRESP_Pos           (8U)

+#define SDMMC_CMD_WAITRESP_Msk           (0x3UL << SDMMC_CMD_WAITRESP_Pos)     /*!< 0x00000300 */

+#define SDMMC_CMD_WAITRESP               SDMMC_CMD_WAITRESP_Msk                /*!<WAITRESP[1:0] bits (Wait for response bits) */

+#define SDMMC_CMD_WAITRESP_0             (0x1UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000100 */

+#define SDMMC_CMD_WAITRESP_1             (0x2UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000200 */

+

+#define SDMMC_CMD_WAITINT_Pos            (10U)

+#define SDMMC_CMD_WAITINT_Msk            (0x1UL << SDMMC_CMD_WAITINT_Pos)      /*!< 0x00000400 */

+#define SDMMC_CMD_WAITINT                SDMMC_CMD_WAITINT_Msk                 /*!<CPSM Waits for Interrupt Request                               */

+#define SDMMC_CMD_WAITPEND_Pos           (11U)

+#define SDMMC_CMD_WAITPEND_Msk           (0x1UL << SDMMC_CMD_WAITPEND_Pos)     /*!< 0x00000800 */

+#define SDMMC_CMD_WAITPEND               SDMMC_CMD_WAITPEND_Msk                /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */

+#define SDMMC_CMD_CPSMEN_Pos             (12U)

+#define SDMMC_CMD_CPSMEN_Msk             (0x1UL << SDMMC_CMD_CPSMEN_Pos)       /*!< 0x00001000 */

+#define SDMMC_CMD_CPSMEN                 SDMMC_CMD_CPSMEN_Msk                  /*!<Command path state machine (CPSM) Enable bit                   */

+#define SDMMC_CMD_DTHOLD_Pos             (13U)

+#define SDMMC_CMD_DTHOLD_Msk             (0x1UL << SDMMC_CMD_DTHOLD_Pos)       /*!< 0x00002000 */

+#define SDMMC_CMD_DTHOLD                 SDMMC_CMD_DTHOLD_Msk                  /*!<Hold new data block transmission and reception in the DPSM     */

+#define SDMMC_CMD_BOOTMODE_Pos           (14U)

+#define SDMMC_CMD_BOOTMODE_Msk           (0x1UL << SDMMC_CMD_BOOTMODE_Pos)     /*!< 0x00004000 */

+#define SDMMC_CMD_BOOTMODE               SDMMC_CMD_BOOTMODE_Msk                /*!<Boot mode                                                      */

+#define SDMMC_CMD_BOOTEN_Pos             (15U)

+#define SDMMC_CMD_BOOTEN_Msk             (0x1UL << SDMMC_CMD_BOOTEN_Pos)       /*!< 0x00008000 */

+#define SDMMC_CMD_BOOTEN                 SDMMC_CMD_BOOTEN_Msk                  /*!<Enable Boot mode procedure                                     */

+#define SDMMC_CMD_CMDSUSPEND_Pos         (16U)

+#define SDMMC_CMD_CMDSUSPEND_Msk         (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)   /*!< 0x00010000 */

+#define SDMMC_CMD_CMDSUSPEND             SDMMC_CMD_CMDSUSPEND_Msk              /*!<CPSM Treats command as a Suspend or Resume command             */

+

+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/

+#define SDMMC_RESPCMD_RESPCMD_Pos        (0U)

+#define SDMMC_RESPCMD_RESPCMD_Msk        (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */

+#define SDMMC_RESPCMD_RESPCMD            SDMMC_RESPCMD_RESPCMD_Msk             /*!<Response command index */

+

+/******************  Bit definition for SDMMC_RESP0 register  ******************/

+#define SDMMC_RESP0_CARDSTATUS0_Pos      (0U)

+#define SDMMC_RESP0_CARDSTATUS0_Msk      (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP0_CARDSTATUS0          SDMMC_RESP0_CARDSTATUS0_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP1 register  ******************/

+#define SDMMC_RESP1_CARDSTATUS1_Pos      (0U)

+#define SDMMC_RESP1_CARDSTATUS1_Msk      (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP1_CARDSTATUS1          SDMMC_RESP1_CARDSTATUS1_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP2 register  ******************/

+#define SDMMC_RESP2_CARDSTATUS2_Pos      (0U)

+#define SDMMC_RESP2_CARDSTATUS2_Msk      (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP2_CARDSTATUS2          SDMMC_RESP2_CARDSTATUS2_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP3 register  ******************/

+#define SDMMC_RESP3_CARDSTATUS3_Pos      (0U)

+#define SDMMC_RESP3_CARDSTATUS3_Msk      (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP3_CARDSTATUS3          SDMMC_RESP3_CARDSTATUS3_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP4 register  ******************/

+#define SDMMC_RESP4_CARDSTATUS4_Pos      (0U)

+#define SDMMC_RESP4_CARDSTATUS4_Msk      (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP4_CARDSTATUS4          SDMMC_RESP4_CARDSTATUS4_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_DTIMER register  *****************/

+#define SDMMC_DTIMER_DATATIME_Pos        (0U)

+#define SDMMC_DTIMER_DATATIME_Msk        (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_DTIMER_DATATIME            SDMMC_DTIMER_DATATIME_Msk             /*!<Data timeout period. */

+

+/******************  Bit definition for SDMMC_DLEN register  *******************/

+#define SDMMC_DLEN_DATALENGTH_Pos        (0U)

+#define SDMMC_DLEN_DATALENGTH_Msk        (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_DLEN_DATALENGTH            SDMMC_DLEN_DATALENGTH_Msk             /*!<Data length value    */

+

+/******************  Bit definition for SDMMC_DCTRL register  ******************/

+#define SDMMC_DCTRL_DTEN_Pos             (0U)

+#define SDMMC_DCTRL_DTEN_Msk             (0x1UL << SDMMC_DCTRL_DTEN_Pos)       /*!< 0x00000001 */

+#define SDMMC_DCTRL_DTEN                 SDMMC_DCTRL_DTEN_Msk                  /*!<Data transfer enabled bit                */

+#define SDMMC_DCTRL_DTDIR_Pos            (1U)

+#define SDMMC_DCTRL_DTDIR_Msk            (0x1UL << SDMMC_DCTRL_DTDIR_Pos)      /*!< 0x00000002 */

+#define SDMMC_DCTRL_DTDIR                SDMMC_DCTRL_DTDIR_Msk                 /*!<Data transfer direction selection        */

+#define SDMMC_DCTRL_DTMODE_Pos           (2U)

+#define SDMMC_DCTRL_DTMODE_Msk           (0x3UL << SDMMC_DCTRL_DTMODE_Pos)     /*!< 0x0000000C */

+#define SDMMC_DCTRL_DTMODE               SDMMC_DCTRL_DTMODE_Msk                /*!<DTMODE[1:0] Data transfer mode selection */

+#define SDMMC_DCTRL_DTMODE_0             (0x1UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000004 */

+#define SDMMC_DCTRL_DTMODE_1             (0x2UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000008 */

+

+#define SDMMC_DCTRL_DBLOCKSIZE_Pos       (4U)

+#define SDMMC_DCTRL_DBLOCKSIZE_Msk       (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */

+#define SDMMC_DCTRL_DBLOCKSIZE           SDMMC_DCTRL_DBLOCKSIZE_Msk            /*!<DBLOCKSIZE[3:0] bits (Data block size) */

+#define SDMMC_DCTRL_DBLOCKSIZE_0         (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000010 */

+#define SDMMC_DCTRL_DBLOCKSIZE_1         (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000020 */

+#define SDMMC_DCTRL_DBLOCKSIZE_2         (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000040 */

+#define SDMMC_DCTRL_DBLOCKSIZE_3         (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000080 */

+

+#define SDMMC_DCTRL_RWSTART_Pos          (8U)

+#define SDMMC_DCTRL_RWSTART_Msk          (0x1UL << SDMMC_DCTRL_RWSTART_Pos)    /*!< 0x00000100 */

+#define SDMMC_DCTRL_RWSTART              SDMMC_DCTRL_RWSTART_Msk               /*!<Read wait start                                 */

+#define SDMMC_DCTRL_RWSTOP_Pos           (9U)

+#define SDMMC_DCTRL_RWSTOP_Msk           (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)     /*!< 0x00000200 */

+#define SDMMC_DCTRL_RWSTOP               SDMMC_DCTRL_RWSTOP_Msk                /*!<Read wait stop                                  */

+#define SDMMC_DCTRL_RWMOD_Pos            (10U)

+#define SDMMC_DCTRL_RWMOD_Msk            (0x1UL << SDMMC_DCTRL_RWMOD_Pos)      /*!< 0x00000400 */

+#define SDMMC_DCTRL_RWMOD                SDMMC_DCTRL_RWMOD_Msk                 /*!<Read wait mode                                  */

+#define SDMMC_DCTRL_SDIOEN_Pos           (11U)

+#define SDMMC_DCTRL_SDIOEN_Msk           (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)     /*!< 0x00000800 */

+#define SDMMC_DCTRL_SDIOEN               SDMMC_DCTRL_SDIOEN_Msk                /*!<SD I/O enable functions                         */

+#define SDMMC_DCTRL_BOOTACKEN_Pos        (12U)

+#define SDMMC_DCTRL_BOOTACKEN_Msk        (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)  /*!< 0x00001000 */

+#define SDMMC_DCTRL_BOOTACKEN            SDMMC_DCTRL_BOOTACKEN_Msk             /*!<Enable the reception of the Boot Acknowledgment */

+#define SDMMC_DCTRL_FIFORST_Pos          (13U)

+#define SDMMC_DCTRL_FIFORST_Msk          (0x1UL << SDMMC_DCTRL_FIFORST_Pos)    /*!< 0x00002000 */

+#define SDMMC_DCTRL_FIFORST              SDMMC_DCTRL_FIFORST_Msk               /*!<FIFO reset                                      */

+

+/******************  Bit definition for SDMMC_DCOUNT register  *****************/

+#define SDMMC_DCOUNT_DATACOUNT_Pos       (0U)

+#define SDMMC_DCOUNT_DATACOUNT_Msk       (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_DCOUNT_DATACOUNT           SDMMC_DCOUNT_DATACOUNT_Msk            /*!<Data count value */

+

+/******************  Bit definition for SDMMC_STA register  ********************/

+#define SDMMC_STA_CCRCFAIL_Pos           (0U)

+#define SDMMC_STA_CCRCFAIL_Msk           (0x1UL << SDMMC_STA_CCRCFAIL_Pos)     /*!< 0x00000001 */

+#define SDMMC_STA_CCRCFAIL               SDMMC_STA_CCRCFAIL_Msk                /*!<Command response received (CRC check failed)  */

+#define SDMMC_STA_DCRCFAIL_Pos           (1U)

+#define SDMMC_STA_DCRCFAIL_Msk           (0x1UL << SDMMC_STA_DCRCFAIL_Pos)     /*!< 0x00000002 */

+#define SDMMC_STA_DCRCFAIL               SDMMC_STA_DCRCFAIL_Msk                /*!<Data block sent/received (CRC check failed)   */

+#define SDMMC_STA_CTIMEOUT_Pos           (2U)

+#define SDMMC_STA_CTIMEOUT_Msk           (0x1UL << SDMMC_STA_CTIMEOUT_Pos)     /*!< 0x00000004 */

+#define SDMMC_STA_CTIMEOUT               SDMMC_STA_CTIMEOUT_Msk                /*!<Command response timeout                      */

+#define SDMMC_STA_DTIMEOUT_Pos           (3U)

+#define SDMMC_STA_DTIMEOUT_Msk           (0x1UL << SDMMC_STA_DTIMEOUT_Pos)     /*!< 0x00000008 */

+#define SDMMC_STA_DTIMEOUT               SDMMC_STA_DTIMEOUT_Msk                /*!<Data timeout                                  */

+#define SDMMC_STA_TXUNDERR_Pos           (4U)

+#define SDMMC_STA_TXUNDERR_Msk           (0x1UL << SDMMC_STA_TXUNDERR_Pos)     /*!< 0x00000010 */

+#define SDMMC_STA_TXUNDERR               SDMMC_STA_TXUNDERR_Msk                /*!<Transmit FIFO underrun error                  */

+#define SDMMC_STA_RXOVERR_Pos            (5U)

+#define SDMMC_STA_RXOVERR_Msk            (0x1UL << SDMMC_STA_RXOVERR_Pos)      /*!< 0x00000020 */

+#define SDMMC_STA_RXOVERR                SDMMC_STA_RXOVERR_Msk                 /*!<Received FIFO overrun error                   */

+#define SDMMC_STA_CMDREND_Pos            (6U)

+#define SDMMC_STA_CMDREND_Msk            (0x1UL << SDMMC_STA_CMDREND_Pos)      /*!< 0x00000040 */

+#define SDMMC_STA_CMDREND                SDMMC_STA_CMDREND_Msk                 /*!<Command response received (CRC check passed)  */

+#define SDMMC_STA_CMDSENT_Pos            (7U)

+#define SDMMC_STA_CMDSENT_Msk            (0x1UL << SDMMC_STA_CMDSENT_Pos)      /*!< 0x00000080 */

+#define SDMMC_STA_CMDSENT                SDMMC_STA_CMDSENT_Msk                 /*!<Command sent (no response required)           */

+#define SDMMC_STA_DATAEND_Pos            (8U)

+#define SDMMC_STA_DATAEND_Msk            (0x1UL << SDMMC_STA_DATAEND_Pos)      /*!< 0x00000100 */

+#define SDMMC_STA_DATAEND                SDMMC_STA_DATAEND_Msk                 /*!<Data end (data counter, SDIDCOUNT, is zero)   */

+#define SDMMC_STA_DHOLD_Pos              (9U)

+#define SDMMC_STA_DHOLD_Msk              (0x1UL << SDMMC_STA_DHOLD_Pos)        /*!< 0x00000200 */

+#define SDMMC_STA_DHOLD                  SDMMC_STA_DHOLD_Msk                   /*!<Data transfer Hold                                                      */

+#define SDMMC_STA_DBCKEND_Pos            (10U)

+#define SDMMC_STA_DBCKEND_Msk            (0x1UL << SDMMC_STA_DBCKEND_Pos)      /*!< 0x00000400 */

+#define SDMMC_STA_DBCKEND                SDMMC_STA_DBCKEND_Msk                 /*!<Data block sent/received (CRC check passed)   */

+#define SDMMC_STA_DABORT_Pos             (11U)

+#define SDMMC_STA_DABORT_Msk             (0x1UL << SDMMC_STA_DABORT_Pos)       /*!< 0x00000800 */

+#define SDMMC_STA_DABORT                 SDMMC_STA_DABORT_Msk                  /*!<Data transfer aborted by CMD12                                          */

+#define SDMMC_STA_DPSMACT_Pos            (12U)

+#define SDMMC_STA_DPSMACT_Msk            (0x1UL << SDMMC_STA_DPSMACT_Pos)      /*!< 0x00001000 */

+#define SDMMC_STA_DPSMACT                SDMMC_STA_DPSMACT_Msk                 /*!<Data path state machine active                                       */

+#define SDMMC_STA_CPSMACT_Pos            (13U)

+#define SDMMC_STA_CPSMACT_Msk            (0x1UL << SDMMC_STA_CPSMACT_Pos)      /*!< 0x00002000 */

+#define SDMMC_STA_CPSMACT                SDMMC_STA_CPSMACT_Msk                 /*!<Command path state machine active                                          */

+#define SDMMC_STA_TXFIFOHE_Pos           (14U)

+#define SDMMC_STA_TXFIFOHE_Msk           (0x1UL << SDMMC_STA_TXFIFOHE_Pos)     /*!< 0x00004000 */

+#define SDMMC_STA_TXFIFOHE               SDMMC_STA_TXFIFOHE_Msk                /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */

+#define SDMMC_STA_RXFIFOHF_Pos           (15U)

+#define SDMMC_STA_RXFIFOHF_Msk           (0x1UL << SDMMC_STA_RXFIFOHF_Pos)     /*!< 0x00008000 */

+#define SDMMC_STA_RXFIFOHF               SDMMC_STA_RXFIFOHF_Msk                /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */

+#define SDMMC_STA_TXFIFOF_Pos            (16U)

+#define SDMMC_STA_TXFIFOF_Msk            (0x1UL << SDMMC_STA_TXFIFOF_Pos)      /*!< 0x00010000 */

+#define SDMMC_STA_TXFIFOF                SDMMC_STA_TXFIFOF_Msk                 /*!<Transmit FIFO full                            */

+#define SDMMC_STA_RXFIFOF_Pos            (17U)

+#define SDMMC_STA_RXFIFOF_Msk            (0x1UL << SDMMC_STA_RXFIFOF_Pos)      /*!< 0x00020000 */

+#define SDMMC_STA_RXFIFOF                SDMMC_STA_RXFIFOF_Msk                 /*!<Receive FIFO full                             */

+#define SDMMC_STA_TXFIFOE_Pos            (18U)

+#define SDMMC_STA_TXFIFOE_Msk            (0x1UL << SDMMC_STA_TXFIFOE_Pos)      /*!< 0x00040000 */

+#define SDMMC_STA_TXFIFOE                SDMMC_STA_TXFIFOE_Msk                 /*!<Transmit FIFO empty                           */

+#define SDMMC_STA_RXFIFOE_Pos            (19U)

+#define SDMMC_STA_RXFIFOE_Msk            (0x1UL << SDMMC_STA_RXFIFOE_Pos)      /*!< 0x00080000 */

+#define SDMMC_STA_RXFIFOE                SDMMC_STA_RXFIFOE_Msk                 /*!<Receive FIFO empty                            */

+#define SDMMC_STA_BUSYD0_Pos             (20U)

+#define SDMMC_STA_BUSYD0_Msk             (0x1UL << SDMMC_STA_BUSYD0_Pos)       /*!< 0x00100000 */

+#define SDMMC_STA_BUSYD0                 SDMMC_STA_BUSYD0_Msk                  /*!<Inverted value of SDMMC_D0 line (Busy)                                  */

+#define SDMMC_STA_BUSYD0END_Pos          (21U)

+#define SDMMC_STA_BUSYD0END_Msk          (0x1UL << SDMMC_STA_BUSYD0END_Pos)    /*!< 0x00200000 */

+#define SDMMC_STA_BUSYD0END              SDMMC_STA_BUSYD0END_Msk               /*!<End of SDMMC_D0 Busy following a CMD response detected                  */

+#define SDMMC_STA_SDIOIT_Pos             (22U)

+#define SDMMC_STA_SDIOIT_Msk             (0x1UL << SDMMC_STA_SDIOIT_Pos)       /*!< 0x00400000 */

+#define SDMMC_STA_SDIOIT                 SDMMC_STA_SDIOIT_Msk                  /*!<SDIO interrupt received                                                 */

+#define SDMMC_STA_ACKFAIL_Pos            (23U)

+#define SDMMC_STA_ACKFAIL_Msk            (0x1UL << SDMMC_STA_ACKFAIL_Pos)      /*!< 0x00800000 */

+#define SDMMC_STA_ACKFAIL                SDMMC_STA_ACKFAIL_Msk                 /*!<Boot Acknowledgment received (BootAck check fail)                       */

+#define SDMMC_STA_ACKTIMEOUT_Pos         (24U)

+#define SDMMC_STA_ACKTIMEOUT_Msk         (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)   /*!< 0x01000000 */

+#define SDMMC_STA_ACKTIMEOUT             SDMMC_STA_ACKTIMEOUT_Msk              /*!<Boot Acknowledgment timeout                                             */

+#define SDMMC_STA_VSWEND_Pos             (25U)

+#define SDMMC_STA_VSWEND_Msk             (0x1UL << SDMMC_STA_VSWEND_Pos)       /*!< 0x02000000 */

+#define SDMMC_STA_VSWEND                 SDMMC_STA_VSWEND_Msk                  /*!<Voltage switch critical timing section completion                       */

+#define SDMMC_STA_CKSTOP_Pos             (26U)

+#define SDMMC_STA_CKSTOP_Msk             (0x1UL << SDMMC_STA_CKSTOP_Pos)       /*!< 0x04000000 */

+#define SDMMC_STA_CKSTOP                 SDMMC_STA_CKSTOP_Msk                  /*!<SDMMC_CK stopped in Voltage switch procedure                            */

+#define SDMMC_STA_IDMATE_Pos             (27U)

+#define SDMMC_STA_IDMATE_Msk             (0x1UL << SDMMC_STA_IDMATE_Pos)       /*!< 0x08000000 */

+#define SDMMC_STA_IDMATE                 SDMMC_STA_IDMATE_Msk                  /*!<IDMA transfer error                                                     */

+#define SDMMC_STA_IDMABTC_Pos            (28U)

+#define SDMMC_STA_IDMABTC_Msk            (0x1UL << SDMMC_STA_IDMABTC_Pos)      /*!< 0x10000000 */

+#define SDMMC_STA_IDMABTC                SDMMC_STA_IDMABTC_Msk                 /*!<IDMA buffer transfer complete                                           */

+

+/*******************  Bit definition for SDMMC_ICR register  *******************/

+#define SDMMC_ICR_CCRCFAILC_Pos          (0U)

+#define SDMMC_ICR_CCRCFAILC_Msk          (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)    /*!< 0x00000001 */

+#define SDMMC_ICR_CCRCFAILC              SDMMC_ICR_CCRCFAILC_Msk               /*!<CCRCFAIL flag clear bit */

+#define SDMMC_ICR_DCRCFAILC_Pos          (1U)

+#define SDMMC_ICR_DCRCFAILC_Msk          (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)    /*!< 0x00000002 */

+#define SDMMC_ICR_DCRCFAILC              SDMMC_ICR_DCRCFAILC_Msk               /*!<DCRCFAIL flag clear bit */

+#define SDMMC_ICR_CTIMEOUTC_Pos          (2U)

+#define SDMMC_ICR_CTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)    /*!< 0x00000004 */

+#define SDMMC_ICR_CTIMEOUTC              SDMMC_ICR_CTIMEOUTC_Msk               /*!<CTIMEOUT flag clear bit */

+#define SDMMC_ICR_DTIMEOUTC_Pos          (3U)

+#define SDMMC_ICR_DTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)    /*!< 0x00000008 */

+#define SDMMC_ICR_DTIMEOUTC              SDMMC_ICR_DTIMEOUTC_Msk               /*!<DTIMEOUT flag clear bit */

+#define SDMMC_ICR_TXUNDERRC_Pos          (4U)

+#define SDMMC_ICR_TXUNDERRC_Msk          (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)    /*!< 0x00000010 */

+#define SDMMC_ICR_TXUNDERRC              SDMMC_ICR_TXUNDERRC_Msk               /*!<TXUNDERR flag clear bit */

+#define SDMMC_ICR_RXOVERRC_Pos           (5U)

+#define SDMMC_ICR_RXOVERRC_Msk           (0x1UL << SDMMC_ICR_RXOVERRC_Pos)     /*!< 0x00000020 */

+#define SDMMC_ICR_RXOVERRC               SDMMC_ICR_RXOVERRC_Msk                /*!<RXOVERR flag clear bit  */

+#define SDMMC_ICR_CMDRENDC_Pos           (6U)

+#define SDMMC_ICR_CMDRENDC_Msk           (0x1UL << SDMMC_ICR_CMDRENDC_Pos)     /*!< 0x00000040 */

+#define SDMMC_ICR_CMDRENDC               SDMMC_ICR_CMDRENDC_Msk                /*!<CMDREND flag clear bit  */

+#define SDMMC_ICR_CMDSENTC_Pos           (7U)

+#define SDMMC_ICR_CMDSENTC_Msk           (0x1UL << SDMMC_ICR_CMDSENTC_Pos)     /*!< 0x00000080 */

+#define SDMMC_ICR_CMDSENTC               SDMMC_ICR_CMDSENTC_Msk                /*!<CMDSENT flag clear bit  */

+#define SDMMC_ICR_DATAENDC_Pos           (8U)

+#define SDMMC_ICR_DATAENDC_Msk           (0x1UL << SDMMC_ICR_DATAENDC_Pos)     /*!< 0x00000100 */

+#define SDMMC_ICR_DATAENDC               SDMMC_ICR_DATAENDC_Msk                /*!<DATAEND flag clear bit  */

+#define SDMMC_ICR_DHOLDC_Pos             (9U)

+#define SDMMC_ICR_DHOLDC_Msk             (0x1UL << SDMMC_ICR_DHOLDC_Pos)       /*!< 0x00000200 */

+#define SDMMC_ICR_DHOLDC                 SDMMC_ICR_DHOLDC_Msk                  /*!<DHOLD flag clear bit       */

+#define SDMMC_ICR_DBCKENDC_Pos           (10U)

+#define SDMMC_ICR_DBCKENDC_Msk           (0x1UL << SDMMC_ICR_DBCKENDC_Pos)     /*!< 0x00000400 */

+#define SDMMC_ICR_DBCKENDC               SDMMC_ICR_DBCKENDC_Msk                /*!<DBCKEND flag clear bit  */

+#define SDMMC_ICR_DABORTC_Pos            (11U)

+#define SDMMC_ICR_DABORTC_Msk            (0x1UL << SDMMC_ICR_DABORTC_Pos)      /*!< 0x00000800 */

+#define SDMMC_ICR_DABORTC                SDMMC_ICR_DABORTC_Msk                 /*!<DABORTC flag clear bit     */

+#define SDMMC_ICR_BUSYD0ENDC_Pos         (21U)

+#define SDMMC_ICR_BUSYD0ENDC_Msk         (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)   /*!< 0x00200000 */

+#define SDMMC_ICR_BUSYD0ENDC             SDMMC_ICR_BUSYD0ENDC_Msk              /*!<BUSYD0ENDC flag clear bit  */

+#define SDMMC_ICR_SDIOITC_Pos            (22U)

+#define SDMMC_ICR_SDIOITC_Msk            (0x1UL << SDMMC_ICR_SDIOITC_Pos)      /*!< 0x00400000 */

+#define SDMMC_ICR_SDIOITC                SDMMC_ICR_SDIOITC_Msk                 /*!<SDIOIT flag clear bit      */

+#define SDMMC_ICR_ACKFAILC_Pos           (23U)

+#define SDMMC_ICR_ACKFAILC_Msk           (0x1UL << SDMMC_ICR_ACKFAILC_Pos)     /*!< 0x00800000 */

+#define SDMMC_ICR_ACKFAILC               SDMMC_ICR_ACKFAILC_Msk                /*!<ACKFAILC flag clear bit    */

+#define SDMMC_ICR_ACKTIMEOUTC_Pos        (24U)

+#define SDMMC_ICR_ACKTIMEOUTC_Msk        (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)  /*!< 0x01000000 */

+#define SDMMC_ICR_ACKTIMEOUTC            SDMMC_ICR_ACKTIMEOUTC_Msk             /*!<ACKTIMEOUTC flag clear bit */

+#define SDMMC_ICR_VSWENDC_Pos            (25U)

+#define SDMMC_ICR_VSWENDC_Msk            (0x1UL << SDMMC_ICR_VSWENDC_Pos)      /*!< 0x02000000 */

+#define SDMMC_ICR_VSWENDC                SDMMC_ICR_VSWENDC_Msk                 /*!<VSWENDC flag clear bit     */

+#define SDMMC_ICR_CKSTOPC_Pos            (26U)

+#define SDMMC_ICR_CKSTOPC_Msk            (0x1UL << SDMMC_ICR_CKSTOPC_Pos)      /*!< 0x04000000 */

+#define SDMMC_ICR_CKSTOPC                SDMMC_ICR_CKSTOPC_Msk                 /*!<CKSTOPC flag clear bit     */

+#define SDMMC_ICR_IDMATEC_Pos            (27U)

+#define SDMMC_ICR_IDMATEC_Msk            (0x1UL << SDMMC_ICR_IDMATEC_Pos)      /*!< 0x08000000 */

+#define SDMMC_ICR_IDMATEC                SDMMC_ICR_IDMATEC_Msk                 /*!<IDMATEC flag clear bit     */

+#define SDMMC_ICR_IDMABTCC_Pos           (28U)

+#define SDMMC_ICR_IDMABTCC_Msk           (0x1UL << SDMMC_ICR_IDMABTCC_Pos)     /*!< 0x10000000 */

+#define SDMMC_ICR_IDMABTCC               SDMMC_ICR_IDMABTCC_Msk                /*!<IDMABTCC flag clear bit    */

+

+/******************  Bit definition for SDMMC_MASK register  *******************/

+#define SDMMC_MASK_CCRCFAILIE_Pos        (0U)

+#define SDMMC_MASK_CCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)  /*!< 0x00000001 */

+#define SDMMC_MASK_CCRCFAILIE            SDMMC_MASK_CCRCFAILIE_Msk             /*!<Command CRC Fail Interrupt Enable          */

+#define SDMMC_MASK_DCRCFAILIE_Pos        (1U)

+#define SDMMC_MASK_DCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)  /*!< 0x00000002 */

+#define SDMMC_MASK_DCRCFAILIE            SDMMC_MASK_DCRCFAILIE_Msk             /*!<Data CRC Fail Interrupt Enable             */

+#define SDMMC_MASK_CTIMEOUTIE_Pos        (2U)

+#define SDMMC_MASK_CTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)  /*!< 0x00000004 */

+#define SDMMC_MASK_CTIMEOUTIE            SDMMC_MASK_CTIMEOUTIE_Msk             /*!<Command TimeOut Interrupt Enable           */

+#define SDMMC_MASK_DTIMEOUTIE_Pos        (3U)

+#define SDMMC_MASK_DTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)  /*!< 0x00000008 */

+#define SDMMC_MASK_DTIMEOUTIE            SDMMC_MASK_DTIMEOUTIE_Msk             /*!<Data TimeOut Interrupt Enable              */

+#define SDMMC_MASK_TXUNDERRIE_Pos        (4U)

+#define SDMMC_MASK_TXUNDERRIE_Msk        (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)  /*!< 0x00000010 */

+#define SDMMC_MASK_TXUNDERRIE            SDMMC_MASK_TXUNDERRIE_Msk             /*!<Tx FIFO UnderRun Error Interrupt Enable    */

+#define SDMMC_MASK_RXOVERRIE_Pos         (5U)

+#define SDMMC_MASK_RXOVERRIE_Msk         (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)   /*!< 0x00000020 */

+#define SDMMC_MASK_RXOVERRIE             SDMMC_MASK_RXOVERRIE_Msk              /*!<Rx FIFO OverRun Error Interrupt Enable     */

+#define SDMMC_MASK_CMDRENDIE_Pos         (6U)

+#define SDMMC_MASK_CMDRENDIE_Msk         (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)   /*!< 0x00000040 */

+#define SDMMC_MASK_CMDRENDIE             SDMMC_MASK_CMDRENDIE_Msk              /*!<Command Response Received Interrupt Enable */

+#define SDMMC_MASK_CMDSENTIE_Pos         (7U)

+#define SDMMC_MASK_CMDSENTIE_Msk         (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)   /*!< 0x00000080 */

+#define SDMMC_MASK_CMDSENTIE             SDMMC_MASK_CMDSENTIE_Msk              /*!<Command Sent Interrupt Enable              */

+#define SDMMC_MASK_DATAENDIE_Pos         (8U)

+#define SDMMC_MASK_DATAENDIE_Msk         (0x1UL << SDMMC_MASK_DATAENDIE_Pos)   /*!< 0x00000100 */

+#define SDMMC_MASK_DATAENDIE             SDMMC_MASK_DATAENDIE_Msk              /*!<Data End Interrupt Enable                  */

+#define SDMMC_MASK_DHOLDIE_Pos           (9U)

+#define SDMMC_MASK_DHOLDIE_Msk           (0x1UL << SDMMC_MASK_DHOLDIE_Pos)     /*!< 0x00000200 */

+#define SDMMC_MASK_DHOLDIE               SDMMC_MASK_DHOLDIE_Msk                /*!<Data Hold Interrupt Enable                 */

+#define SDMMC_MASK_DBCKENDIE_Pos         (10U)

+#define SDMMC_MASK_DBCKENDIE_Msk         (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)   /*!< 0x00000400 */

+#define SDMMC_MASK_DBCKENDIE             SDMMC_MASK_DBCKENDIE_Msk              /*!<Data Block End Interrupt Enable            */

+#define SDMMC_MASK_DABORTIE_Pos          (11U)

+#define SDMMC_MASK_DABORTIE_Msk          (0x1UL << SDMMC_MASK_DABORTIE_Pos)    /*!< 0x00000800 */

+#define SDMMC_MASK_DABORTIE              SDMMC_MASK_DABORTIE_Msk               /*!<Data transfer aborted interrupt enable     */

+

+#define SDMMC_MASK_TXFIFOHEIE_Pos        (14U)

+#define SDMMC_MASK_TXFIFOHEIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)  /*!< 0x00004000 */

+#define SDMMC_MASK_TXFIFOHEIE            SDMMC_MASK_TXFIFOHEIE_Msk             /*!<Tx FIFO Half Empty interrupt Enable        */

+#define SDMMC_MASK_RXFIFOHFIE_Pos        (15U)

+#define SDMMC_MASK_RXFIFOHFIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)  /*!< 0x00008000 */

+#define SDMMC_MASK_RXFIFOHFIE            SDMMC_MASK_RXFIFOHFIE_Msk             /*!<Rx FIFO Half Full interrupt Enable         */

+

+#define SDMMC_MASK_RXFIFOFIE_Pos         (17U)

+#define SDMMC_MASK_RXFIFOFIE_Msk         (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)   /*!< 0x00020000 */

+#define SDMMC_MASK_RXFIFOFIE             SDMMC_MASK_RXFIFOFIE_Msk              /*!<Rx FIFO Full interrupt Enable              */

+#define SDMMC_MASK_TXFIFOEIE_Pos         (18U)

+#define SDMMC_MASK_TXFIFOEIE_Msk         (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)   /*!< 0x00040000 */

+#define SDMMC_MASK_TXFIFOEIE             SDMMC_MASK_TXFIFOEIE_Msk              /*!<Tx FIFO Empty interrupt Enable             */

+

+#define SDMMC_MASK_BUSYD0ENDIE_Pos       (21U)

+#define SDMMC_MASK_BUSYD0ENDIE_Msk       (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */

+#define SDMMC_MASK_BUSYD0ENDIE           SDMMC_MASK_BUSYD0ENDIE_Msk            /*!<BUSYD0ENDIE interrupt Enable */

+#define SDMMC_MASK_SDIOITIE_Pos           (22U)

+#define SDMMC_MASK_SDIOITIE_Msk           (0x1UL << SDMMC_MASK_SDIOITIE_Pos)     /*!< 0x00400000 */

+#define SDMMC_MASK_SDIOITIE               SDMMC_MASK_SDIOITIE_Msk                /*!<SDMMC Mode Interrupt Received interrupt Enable */

+#define SDMMC_MASK_ACKFAILIE_Pos         (23U)

+#define SDMMC_MASK_ACKFAILIE_Msk         (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)   /*!< 0x00800000 */

+#define SDMMC_MASK_ACKFAILIE             SDMMC_MASK_ACKFAILIE_Msk              /*!<Acknowledgment Fail Interrupt Enable */

+#define SDMMC_MASK_ACKTIMEOUTIE_Pos      (24U)

+#define SDMMC_MASK_ACKTIMEOUTIE_Msk      (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */

+#define SDMMC_MASK_ACKTIMEOUTIE          SDMMC_MASK_ACKTIMEOUTIE_Msk           /*!<Acknowledgment timeout Interrupt Enable */

+#define SDMMC_MASK_VSWENDIE_Pos          (25U)

+#define SDMMC_MASK_VSWENDIE_Msk          (0x1UL << SDMMC_MASK_VSWENDIE_Pos)    /*!< 0x02000000 */

+#define SDMMC_MASK_VSWENDIE              SDMMC_MASK_VSWENDIE_Msk               /*!<Voltage switch critical timing section completion Interrupt Enable */

+#define SDMMC_MASK_CKSTOPIE_Pos          (26U)

+#define SDMMC_MASK_CKSTOPIE_Msk          (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)    /*!< 0x04000000 */

+#define SDMMC_MASK_CKSTOPIE              SDMMC_MASK_CKSTOPIE_Msk               /*!<Voltage Switch clock stopped Interrupt Enable */

+#define SDMMC_MASK_IDMABTCIE_Pos         (28U)

+#define SDMMC_MASK_IDMABTCIE_Msk         (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)   /*!< 0x10000000 */

+#define SDMMC_MASK_IDMABTCIE             SDMMC_MASK_IDMABTCIE_Msk              /*!<IDMA buffer transfer complete Interrupt Enable */

+

+/*****************  Bit definition for SDMMC_ACKTIME register  *****************/

+#define SDMMC_ACKTIME_ACKTIME_Pos        (0U)

+#define SDMMC_ACKTIME_ACKTIME_Msk        (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_ACKTIME_ACKTIME            SDMMC_ACKTIME_ACKTIME_Msk             /*!<Boot acknowledgment timeout period */

+

+/******************  Bit definition for SDMMC_FIFO register  *******************/

+#define SDMMC_FIFO_FIFODATA_Pos          (0U)

+#define SDMMC_FIFO_FIFODATA_Msk          (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_FIFO_FIFODATA              SDMMC_FIFO_FIFODATA_Msk               /*!<Receive and transmit FIFO data */

+

+/******************  Bit definition for SDMMC_IDMACTRL register ****************/

+#define SDMMC_IDMA_IDMAEN_Pos            (0U)

+#define SDMMC_IDMA_IDMAEN_Msk            (0x1UL << SDMMC_IDMA_IDMAEN_Pos)      /*!< 0x00000001 */

+#define SDMMC_IDMA_IDMAEN                SDMMC_IDMA_IDMAEN_Msk                 /*!< Enable the internal DMA of the SDMMC peripheral */

+#define SDMMC_IDMA_IDMABMODE_Pos         (1U)

+#define SDMMC_IDMA_IDMABMODE_Msk         (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)   /*!< 0x00000002 */

+#define SDMMC_IDMA_IDMABMODE             SDMMC_IDMA_IDMABMODE_Msk              /*!< Enable double buffer mode for IDMA */

+#define SDMMC_IDMA_IDMABACT_Pos          (2U)

+#define SDMMC_IDMA_IDMABACT_Msk          (0x1UL << SDMMC_IDMA_IDMABACT_Pos)    /*!< 0x00000004 */

+#define SDMMC_IDMA_IDMABACT              SDMMC_IDMA_IDMABACT_Msk               /*!< Uses buffer 1 when double buffer mode is selected */

+

+/*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/

+#define SDMMC_IDMABSIZE_IDMABNDT_Pos     (5U)

+#define SDMMC_IDMABSIZE_IDMABNDT_Msk     (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */

+#define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */

+

+/*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/

+#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */

+

+/*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/

+#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                        Delay Block Interface (DLYB)                        */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for DLYB_CR register  ********************/

+#define DLYB_CR_DEN_Pos         (0U)

+#define DLYB_CR_DEN_Msk         (0x1UL << DLYB_CR_DEN_Pos)                     /*!< 0x00000001 */

+#define DLYB_CR_DEN             DLYB_CR_DEN_Msk                                /*!<Delay Block enable */

+#define DLYB_CR_SEN_Pos         (1U)

+#define DLYB_CR_SEN_Msk         (0x1UL << DLYB_CR_SEN_Pos)                     /*!< 0x00000002 */

+#define DLYB_CR_SEN             DLYB_CR_SEN_Msk                                /*!<Sampler length enable */

+

+

+/*******************  Bit definition for DLYB_CFGR register  ********************/

+#define DLYB_CFGR_SEL_Pos       (0U)

+#define DLYB_CFGR_SEL_Msk       (0xFUL << DLYB_CFGR_SEL_Pos)                   /*!< 0x0000000F */

+#define DLYB_CFGR_SEL           DLYB_CFGR_SEL_Msk                              /*!<Select the phase for the Output clock[3:0] */

+#define DLYB_CFGR_SEL_0         (0x1UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000001 */

+#define DLYB_CFGR_SEL_1         (0x2UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000002 */

+#define DLYB_CFGR_SEL_2         (0x3UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000003 */

+#define DLYB_CFGR_SEL_3         (0x8UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000008 */

+

+#define DLYB_CFGR_UNIT_Pos      (8U)

+#define DLYB_CFGR_UNIT_Msk      (0x7FUL << DLYB_CFGR_UNIT_Pos)                 /*!< 0x00007F00 */

+#define DLYB_CFGR_UNIT          DLYB_CFGR_UNIT_Msk                             /*!<Delay Defines the delay of a Unit delay cell[6:0] */

+#define DLYB_CFGR_UNIT_0        (0x01UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000100 */

+#define DLYB_CFGR_UNIT_1        (0x02UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000200 */

+#define DLYB_CFGR_UNIT_2        (0x04UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000400 */

+#define DLYB_CFGR_UNIT_3        (0x08UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000800 */

+#define DLYB_CFGR_UNIT_4        (0x10UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00001000 */

+#define DLYB_CFGR_UNIT_5        (0x20UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00002000 */

+#define DLYB_CFGR_UNIT_6        (0x40UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00004000 */

+

+#define DLYB_CFGR_LNG_Pos       (16U)

+#define DLYB_CFGR_LNG_Msk       (0xFFFUL << DLYB_CFGR_LNG_Pos)                 /*!< 0x0FFF0000 */

+#define DLYB_CFGR_LNG           DLYB_CFGR_LNG_Msk                              /*!<Delay line length value[11:0] */

+#define DLYB_CFGR_LNG_0         (0x001UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00010000 */

+#define DLYB_CFGR_LNG_1         (0x002UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00020000 */

+#define DLYB_CFGR_LNG_2         (0x004UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00040000 */

+#define DLYB_CFGR_LNG_3         (0x008UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00080000 */

+#define DLYB_CFGR_LNG_4         (0x010UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00100000 */

+#define DLYB_CFGR_LNG_5         (0x020UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00200000 */

+#define DLYB_CFGR_LNG_6         (0x040UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00400000 */

+#define DLYB_CFGR_LNG_7         (0x080UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00800000 */

+#define DLYB_CFGR_LNG_8         (0x100UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x01000000 */

+#define DLYB_CFGR_LNG_9         (0x200UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x02000000 */

+#define DLYB_CFGR_LNG_10        (0x400UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x04000000 */

+#define DLYB_CFGR_LNG_11        (0x800UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x08000000 */

+

+#define DLYB_CFGR_LNGF_Pos      (31U)

+#define DLYB_CFGR_LNGF_Msk      (0x1UL << DLYB_CFGR_LNGF_Pos)                  /*!< 0x80000000 */

+#define DLYB_CFGR_LNGF          DLYB_CFGR_LNGF_Msk                             /*!<Length valid flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                   Serial Peripheral Interface (SPI/I2S)                    */

+/*                                                                            */

+/******************************************************************************/

+#define SPI_SPI6I2S_SUPPORT       /*!<SPI6 I2S support feature */

+/*******************  Bit definition for SPI_CR1 register  ********************/

+#define SPI_CR1_SPE_Pos             (0U)

+#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000001 */

+#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<Serial Peripheral Enable                         */

+#define SPI_CR1_MASRX_Pos           (8U)

+#define SPI_CR1_MASRX_Msk           (0x1UL << SPI_CR1_MASRX_Pos)               /*!< 0x00000100 */

+#define SPI_CR1_MASRX               SPI_CR1_MASRX_Msk                          /*!<Master automatic SUSP in Receive mode            */

+#define SPI_CR1_CSTART_Pos          (9U)

+#define SPI_CR1_CSTART_Msk          (0x1UL << SPI_CR1_CSTART_Pos)              /*!< 0x00000200 */

+#define SPI_CR1_CSTART              SPI_CR1_CSTART_Msk                         /*!<Master transfer start                            */

+#define SPI_CR1_CSUSP_Pos           (10U)

+#define SPI_CR1_CSUSP_Msk           (0x1UL << SPI_CR1_CSUSP_Pos)               /*!< 0x00000400 */

+#define SPI_CR1_CSUSP               SPI_CR1_CSUSP_Msk                          /*!<Master SUSPend request                           */

+#define SPI_CR1_HDDIR_Pos           (11U)

+#define SPI_CR1_HDDIR_Msk           (0x1UL << SPI_CR1_HDDIR_Pos)               /*!< 0x00000800 */

+#define SPI_CR1_HDDIR               SPI_CR1_HDDIR_Msk                          /*!<Rx/Tx direction at Half-duplex mode              */

+#define SPI_CR1_SSI_Pos             (12U)

+#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00001000 */

+#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal SS signal input level                   */

+#define SPI_CR1_CRC33_17_Pos        (13U)

+#define SPI_CR1_CRC33_17_Msk        (0x1UL << SPI_CR1_CRC33_17_Pos)            /*!< 0x00002000 */

+#define SPI_CR1_CRC33_17             SPI_CR1_CRC33_17_Msk                      /*!<32-bit CRC polynomial configuration              */

+#define SPI_CR1_RCRCINI_Pos         (14U)

+#define SPI_CR1_RCRCINI_Msk         (0x1UL << SPI_CR1_RCRCINI_Pos)             /*!< 0x00004000 */

+#define SPI_CR1_RCRCINI             SPI_CR1_RCRCINI_Msk                        /*!<CRC init pattern control for receiver            */

+#define SPI_CR1_TCRCINI_Pos         (15U)

+#define SPI_CR1_TCRCINI_Msk         (0x1UL << SPI_CR1_TCRCINI_Pos)             /*!< 0x00008000 */

+#define SPI_CR1_TCRCINI             SPI_CR1_TCRCINI_Msk                        /*!<CRC init pattern control for transmitter         */

+#define SPI_CR1_IOLOCK_Pos          (16U)

+#define SPI_CR1_IOLOCK_Msk          (0x1UL << SPI_CR1_IOLOCK_Pos)              /*!< 0x00010000 */

+#define SPI_CR1_IOLOCK              SPI_CR1_IOLOCK_Msk                         /*!<Locking the AF configuration of associated IOs   */

+

+/*******************  Bit definition for SPI_CR2 register  ********************/

+#define SPI_CR2_TSER_Pos            (16U)

+#define SPI_CR2_TSER_Msk            (0xFFFFUL << SPI_CR2_TSER_Pos)             /*!< 0xFFFF0000 */

+#define SPI_CR2_TSER                SPI_CR2_TSER_Msk                           /*!<Number of data transfer extension                */

+#define SPI_CR2_TSIZE_Pos           (0U)

+#define SPI_CR2_TSIZE_Msk           (0xFFFFUL << SPI_CR2_TSIZE_Pos)            /*!< 0x0000FFFF */

+#define SPI_CR2_TSIZE               SPI_CR2_TSIZE_Msk                          /*!<Number of data at current transfer               */

+

+/*******************  Bit definition for SPI_CFG1 register  ********************/

+#define SPI_CFG1_DSIZE_Pos          (0U)

+#define SPI_CFG1_DSIZE_Msk          (0x1FUL << SPI_CFG1_DSIZE_Pos)             /*!< 0x0000001F */

+#define SPI_CFG1_DSIZE              SPI_CFG1_DSIZE_Msk                         /*!<DSIZE[4:0]: Bits number in single SPI data frame */

+#define SPI_CFG1_DSIZE_0            (0x01UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000001 */

+#define SPI_CFG1_DSIZE_1            (0x02UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000002 */

+#define SPI_CFG1_DSIZE_2            (0x04UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000004 */

+#define SPI_CFG1_DSIZE_3            (0x08UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000008 */

+#define SPI_CFG1_DSIZE_4            (0x10UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000010 */

+

+#define SPI_CFG1_FTHLV_Pos          (5U)

+#define SPI_CFG1_FTHLV_Msk          (0xFUL << SPI_CFG1_FTHLV_Pos)              /*!< 0x000001E0 */

+#define SPI_CFG1_FTHLV              SPI_CFG1_FTHLV_Msk                         /*!<FTHVL [3:0]: FIFO threshold level*/

+#define SPI_CFG1_FTHLV_0            (0x1UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000020 */

+#define SPI_CFG1_FTHLV_1            (0x2UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000040 */

+#define SPI_CFG1_FTHLV_2            (0x4UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000080 */

+#define SPI_CFG1_FTHLV_3            (0x8UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000100 */

+

+#define SPI_CFG1_UDRCFG_Pos         (9U)

+#define SPI_CFG1_UDRCFG_Msk         (0x3UL << SPI_CFG1_UDRCFG_Pos)             /*!< 0x00000600 */

+#define SPI_CFG1_UDRCFG             SPI_CFG1_UDRCFG_Msk                        /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */

+#define SPI_CFG1_UDRCFG_0           (0x1UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000200 */

+#define SPI_CFG1_UDRCFG_1           (0x2UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000400 */

+

+

+#define SPI_CFG1_UDRDET_Pos         (11U)

+#define SPI_CFG1_UDRDET_Msk         (0x3UL << SPI_CFG1_UDRDET_Pos)             /*!< 0x00001800 */

+#define SPI_CFG1_UDRDET             SPI_CFG1_UDRDET_Msk                        /*!<UDRDET[1:0]: Detection of underrun condition     */

+#define SPI_CFG1_UDRDET_0           (0x1UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00000800 */

+#define SPI_CFG1_UDRDET_1           (0x2UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00001000 */

+

+#define SPI_CFG1_RXDMAEN_Pos        (14U)

+#define SPI_CFG1_RXDMAEN_Msk        (0x1UL << SPI_CFG1_RXDMAEN_Pos)            /*!< 0x00004000 */

+#define SPI_CFG1_RXDMAEN            SPI_CFG1_RXDMAEN_Msk                       /*!<Rx DMA stream enable                */

+#define SPI_CFG1_TXDMAEN_Pos        (15U)

+#define SPI_CFG1_TXDMAEN_Msk        (0x1UL << SPI_CFG1_TXDMAEN_Pos)            /*!< 0x00008000 */

+#define SPI_CFG1_TXDMAEN            SPI_CFG1_TXDMAEN_Msk                       /*!<Tx DMA stream enable                */

+

+#define SPI_CFG1_CRCSIZE_Pos        (16U)

+#define SPI_CFG1_CRCSIZE_Msk        (0x1FUL << SPI_CFG1_CRCSIZE_Pos)           /*!< 0x001F0000 */

+#define SPI_CFG1_CRCSIZE            SPI_CFG1_CRCSIZE_Msk                       /*!<CRCSIZE [4:0]: Length of CRC frame*/

+#define SPI_CFG1_CRCSIZE_0          (0x01UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00010000 */

+#define SPI_CFG1_CRCSIZE_1          (0x02UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00020000 */

+#define SPI_CFG1_CRCSIZE_2          (0x04UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00040000 */

+#define SPI_CFG1_CRCSIZE_3          (0x08UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00080000 */

+#define SPI_CFG1_CRCSIZE_4          (0x10UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00100000 */

+

+#define SPI_CFG1_CRCEN_Pos          (22U)

+#define SPI_CFG1_CRCEN_Msk          (0x1UL << SPI_CFG1_CRCEN_Pos)              /*!< 0x00400000 */

+#define SPI_CFG1_CRCEN              SPI_CFG1_CRCEN_Msk                         /*!<Hardware CRC computation enable */

+

+#define SPI_CFG1_MBR_Pos            (28U)

+#define SPI_CFG1_MBR_Msk            (0x7UL << SPI_CFG1_MBR_Pos)                /*!< 0x70000000 */

+#define SPI_CFG1_MBR                SPI_CFG1_MBR_Msk                           /*!<Master baud rate                */

+#define SPI_CFG1_MBR_0              (0x1UL << SPI_CFG1_MBR_Pos)                 /*!< 0x10000000 */

+#define SPI_CFG1_MBR_1              (0x2UL << SPI_CFG1_MBR_Pos)                 /*!< 0x20000000 */

+#define SPI_CFG1_MBR_2              (0x4UL << SPI_CFG1_MBR_Pos)                 /*!< 0x40000000 */

+

+/*******************  Bit definition for SPI_CFG2 register  ********************/

+#define SPI_CFG2_MSSI_Pos           (0U)

+#define SPI_CFG2_MSSI_Msk           (0xFUL << SPI_CFG2_MSSI_Pos)               /*!< 0x0000000F */

+#define SPI_CFG2_MSSI               SPI_CFG2_MSSI_Msk                          /*!<Master SS Idleness */

+#define SPI_CFG2_MSSI_0             (0x1UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000001 */

+#define SPI_CFG2_MSSI_1             (0x2UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000002 */

+#define SPI_CFG2_MSSI_2             (0x4UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000004 */

+#define SPI_CFG2_MSSI_3             (0x8UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000008 */

+

+#define SPI_CFG2_MIDI_Pos           (4U)

+#define SPI_CFG2_MIDI_Msk           (0xFUL << SPI_CFG2_MIDI_Pos)               /*!< 0x000000F0 */

+#define SPI_CFG2_MIDI               SPI_CFG2_MIDI_Msk                          /*!<Master Inter-Data Idleness */

+#define SPI_CFG2_MIDI_0             (0x1UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000010 */

+#define SPI_CFG2_MIDI_1             (0x2UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000020 */

+#define SPI_CFG2_MIDI_2             (0x4UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000040 */

+#define SPI_CFG2_MIDI_3             (0x8UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000080 */

+

+#define SPI_CFG2_IOSWP_Pos          (15U)

+#define SPI_CFG2_IOSWP_Msk          (0x1UL << SPI_CFG2_IOSWP_Pos)              /*!< 0x00008000 */

+#define SPI_CFG2_IOSWP              SPI_CFG2_IOSWP_Msk                         /*!<Swap functionality of MISO and MOSI pins */

+

+#define SPI_CFG2_COMM_Pos           (17U)

+#define SPI_CFG2_COMM_Msk           (0x3UL << SPI_CFG2_COMM_Pos)               /*!< 0x00060000 */

+#define SPI_CFG2_COMM               SPI_CFG2_COMM_Msk                          /*!<COMM [1:0]: SPI Communication Mode*/

+#define SPI_CFG2_COMM_0             (0x1UL << SPI_CFG2_COMM_Pos)                /*!< 0x00020000 */

+#define SPI_CFG2_COMM_1             (0x2UL << SPI_CFG2_COMM_Pos)                /*!< 0x00040000 */

+

+#define SPI_CFG2_SP_Pos             (19U)

+#define SPI_CFG2_SP_Msk             (0x7UL << SPI_CFG2_SP_Pos)                 /*!< 0x00380000 */

+#define SPI_CFG2_SP                 SPI_CFG2_SP_Msk                            /*!<SP[2:0]: Serial Protocol */

+#define SPI_CFG2_SP_0               (0x1UL << SPI_CFG2_SP_Pos)                  /*!< 0x00080000 */

+#define SPI_CFG2_SP_1               (0x2UL << SPI_CFG2_SP_Pos)                  /*!< 0x00100000 */

+#define SPI_CFG2_SP_2               (0x4UL << SPI_CFG2_SP_Pos)                  /*!< 0x00200000 */

+

+#define SPI_CFG2_MASTER_Pos         (22U)

+#define SPI_CFG2_MASTER_Msk         (0x1UL << SPI_CFG2_MASTER_Pos)             /*!< 0x00400000 */

+#define SPI_CFG2_MASTER             SPI_CFG2_MASTER_Msk                        /*!<SPI Master           */

+#define SPI_CFG2_LSBFRST_Pos        (23U)

+#define SPI_CFG2_LSBFRST_Msk        (0x1UL << SPI_CFG2_LSBFRST_Pos)            /*!< 0x00800000 */

+#define SPI_CFG2_LSBFRST            SPI_CFG2_LSBFRST_Msk                       /*!<Data frame format               */

+#define SPI_CFG2_CPHA_Pos           (24U)

+#define SPI_CFG2_CPHA_Msk           (0x1UL << SPI_CFG2_CPHA_Pos)               /*!< 0x01000000 */

+#define SPI_CFG2_CPHA               SPI_CFG2_CPHA_Msk                          /*!<Clock Phase      */

+#define SPI_CFG2_CPOL_Pos           (25U)

+#define SPI_CFG2_CPOL_Msk           (0x1UL << SPI_CFG2_CPOL_Pos)               /*!< 0x02000000 */

+#define SPI_CFG2_CPOL               SPI_CFG2_CPOL_Msk                          /*!<Clock Polarity   */

+#define SPI_CFG2_SSM_Pos            (26U)

+#define SPI_CFG2_SSM_Msk            (0x1UL << SPI_CFG2_SSM_Pos)                /*!< 0x04000000 */

+#define SPI_CFG2_SSM                SPI_CFG2_SSM_Msk                           /*!<Software slave management */

+

+#define SPI_CFG2_SSIOP_Pos          (28U)

+#define SPI_CFG2_SSIOP_Msk          (0x1UL << SPI_CFG2_SSIOP_Pos)              /*!< 0x10000000 */

+#define SPI_CFG2_SSIOP              SPI_CFG2_SSIOP_Msk                         /*!<SS input/output polarity */

+#define SPI_CFG2_SSOE_Pos           (29U)

+#define SPI_CFG2_SSOE_Msk           (0x1UL << SPI_CFG2_SSOE_Pos)               /*!< 0x20000000 */

+#define SPI_CFG2_SSOE               SPI_CFG2_SSOE_Msk                          /*!<SS output enable */

+#define SPI_CFG2_SSOM_Pos           (30U)

+#define SPI_CFG2_SSOM_Msk           (0x1UL << SPI_CFG2_SSOM_Pos)               /*!< 0x40000000 */

+#define SPI_CFG2_SSOM               SPI_CFG2_SSOM_Msk                          /*!<SS output management in master mode */

+

+#define SPI_CFG2_AFCNTR_Pos         (31U)

+#define SPI_CFG2_AFCNTR_Msk         (0x1UL << SPI_CFG2_AFCNTR_Pos)             /*!< 0x80000000 */

+#define SPI_CFG2_AFCNTR             SPI_CFG2_AFCNTR_Msk                        /*!<Alternate function GPIOs control */

+

+/*******************  Bit definition for SPI_IER register  ********************/

+#define SPI_IER_RXPIE_Pos           (0U)

+#define SPI_IER_RXPIE_Msk           (0x1UL << SPI_IER_RXPIE_Pos)               /*!< 0x00000001 */

+#define SPI_IER_RXPIE               SPI_IER_RXPIE_Msk                          /*!<RXP Interrupt Enable            */

+#define SPI_IER_TXPIE_Pos           (1U)

+#define SPI_IER_TXPIE_Msk           (0x1UL << SPI_IER_TXPIE_Pos)               /*!< 0x00000002 */

+#define SPI_IER_TXPIE               SPI_IER_TXPIE_Msk                          /*!<TXP interrupt enable            */

+#define SPI_IER_DXPIE_Pos           (2U)

+#define SPI_IER_DXPIE_Msk           (0x1UL << SPI_IER_DXPIE_Pos)               /*!< 0x00000004 */

+#define SPI_IER_DXPIE               SPI_IER_DXPIE_Msk                          /*!<DXP interrupt enable            */

+#define SPI_IER_EOTIE_Pos           (3U)

+#define SPI_IER_EOTIE_Msk           (0x1UL << SPI_IER_EOTIE_Pos)               /*!< 0x00000008 */

+#define SPI_IER_EOTIE               SPI_IER_EOTIE_Msk                          /*!<EOT/SUSP/TXC interrupt enable   */

+#define SPI_IER_TXTFIE_Pos          (4U)

+#define SPI_IER_TXTFIE_Msk          (0x1UL << SPI_IER_TXTFIE_Pos)              /*!< 0x00000010 */

+#define SPI_IER_TXTFIE              SPI_IER_TXTFIE_Msk                         /*!<TXTF interrupt enable           */

+#define SPI_IER_UDRIE_Pos           (5U)

+#define SPI_IER_UDRIE_Msk           (0x1UL << SPI_IER_UDRIE_Pos)               /*!< 0x00000020 */

+#define SPI_IER_UDRIE               SPI_IER_UDRIE_Msk                          /*!<UDR interrupt enable            */

+#define SPI_IER_OVRIE_Pos           (6U)

+#define SPI_IER_OVRIE_Msk           (0x1UL << SPI_IER_OVRIE_Pos)               /*!< 0x00000040 */

+#define SPI_IER_OVRIE               SPI_IER_OVRIE_Msk                          /*!<OVR interrupt enable            */

+#define SPI_IER_CRCEIE_Pos          (7U)

+#define SPI_IER_CRCEIE_Msk          (0x1UL << SPI_IER_CRCEIE_Pos)               /*!< 0x00000080 */

+#define SPI_IER_CRCEIE              SPI_IER_CRCEIE_Msk                          /*!<CRCE interrupt enable           */

+#define SPI_IER_TIFREIE_Pos         (8U)

+#define SPI_IER_TIFREIE_Msk         (0x1UL << SPI_IER_TIFREIE_Pos)             /*!< 0x00000100 */

+#define SPI_IER_TIFREIE             SPI_IER_TIFREIE_Msk                        /*!<TI Frame Error interrupt enable */

+#define SPI_IER_MODFIE_Pos          (9U)

+#define SPI_IER_MODFIE_Msk          (0x1UL << SPI_IER_MODFIE_Pos)              /*!< 0x00000200 */

+#define SPI_IER_MODFIE              SPI_IER_MODFIE_Msk                         /*!<MODF interrupt enable           */

+#define SPI_IER_TSERFIE_Pos         (10U)

+#define SPI_IER_TSERFIE_Msk         (0x1UL << SPI_IER_TSERFIE_Pos)              /*!< 0x00000400 */

+#define SPI_IER_TSERFIE             SPI_IER_TSERFIE_Msk                        /*!<TSERF interrupt enable          */

+

+/*******************  Bit definition for SPI_SR register  ********************/

+#define SPI_SR_RXP_Pos              (0U)

+#define SPI_SR_RXP_Msk              (0x1UL << SPI_SR_RXP_Pos)                  /*!< 0x00000001 */

+#define SPI_SR_RXP                  SPI_SR_RXP_Msk                             /*!<Rx-Packet available             */

+#define SPI_SR_TXP_Pos              (1U)

+#define SPI_SR_TXP_Msk              (0x1UL << SPI_SR_TXP_Pos)                  /*!< 0x00000002 */

+#define SPI_SR_TXP                  SPI_SR_TXP_Msk                             /*!<Tx-Packet space available       */

+#define SPI_SR_DXP_Pos              (2U)

+#define SPI_SR_DXP_Msk              (0x1UL << SPI_SR_DXP_Pos)                  /*!< 0x00000004 */

+#define SPI_SR_DXP                  SPI_SR_DXP_Msk                             /*!<Duplex Packet available         */

+#define SPI_SR_EOT_Pos              (3U)

+#define SPI_SR_EOT_Msk              (0x1UL << SPI_SR_EOT_Pos)                  /*!< 0x00000008 */

+#define SPI_SR_EOT                  SPI_SR_EOT_Msk                             /*!<Duplex Packet available         */

+#define SPI_SR_TXTF_Pos             (4U)

+#define SPI_SR_TXTF_Msk             (0x1UL << SPI_SR_TXTF_Pos)                 /*!< 0x00000010 */

+#define SPI_SR_TXTF                 SPI_SR_TXTF_Msk                            /*!<Transmission Transfer Filled    */

+#define SPI_SR_UDR_Pos              (5U)

+#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000020 */

+#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<UDR at Slave transmission       */

+#define SPI_SR_OVR_Pos              (6U)

+#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */

+#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Rx-Packet available             */

+#define SPI_SR_CRCE_Pos             (7U)

+#define SPI_SR_CRCE_Msk             (0x1UL << SPI_SR_CRCE_Pos)                 /*!< 0x00000080 */

+#define SPI_SR_CRCE                 SPI_SR_CRCE_Msk                            /*!<CRC Error Detected              */

+#define SPI_SR_TIFRE_Pos            (8U)

+#define SPI_SR_TIFRE_Msk            (0x1UL << SPI_SR_TIFRE_Pos)                /*!< 0x00000100 */

+#define SPI_SR_TIFRE                SPI_SR_TIFRE_Msk                           /*!<TI frame format error Detected  */

+#define SPI_SR_MODF_Pos             (9U)

+#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000200 */

+#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode Fault Detected             */

+#define SPI_SR_TSERF_Pos            (10U)

+#define SPI_SR_TSERF_Msk            (0x1UL << SPI_SR_TSERF_Pos)                /*!< 0x00000400 */

+#define SPI_SR_TSERF                SPI_SR_TSERF_Msk                           /*!<Number of SPI data to be transacted reloaded     */

+#define SPI_SR_SUSP_Pos             (11U)

+#define SPI_SR_SUSP_Msk             (0x1UL << SPI_SR_SUSP_Pos)                 /*!< 0x00000800 */

+#define SPI_SR_SUSP                 SPI_SR_SUSP_Msk                            /*!<SUSP is set by hardware  */

+#define SPI_SR_TXC_Pos              (12U)

+#define SPI_SR_TXC_Msk              (0x1UL << SPI_SR_TXC_Pos)                  /*!< 0x00001000 */

+#define SPI_SR_TXC                  SPI_SR_TXC_Msk                             /*!<TxFIFO transmission complete */

+#define SPI_SR_RXPLVL_Pos           (13U)

+#define SPI_SR_RXPLVL_Msk           (0x3UL << SPI_SR_RXPLVL_Pos)               /*!< 0x00006000 */

+#define SPI_SR_RXPLVL               SPI_SR_RXPLVL_Msk                          /*!<RxFIFO Packing Level                             */

+#define SPI_SR_RXPLVL_0             (0x1UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00002000 */

+#define SPI_SR_RXPLVL_1             (0x2UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00004000 */

+#define SPI_SR_RXWNE_Pos            (15U)

+#define SPI_SR_RXWNE_Msk            (0x1UL << SPI_SR_RXWNE_Pos)                /*!< 0x00008000 */

+#define SPI_SR_RXWNE                SPI_SR_RXWNE_Msk                           /*!<Rx FIFO Word Not Empty                           */

+#define SPI_SR_CTSIZE_Pos           (16U)

+#define SPI_SR_CTSIZE_Msk           (0xFFFFUL << SPI_SR_CTSIZE_Pos)            /*!< 0xFFFF0000 */

+#define SPI_SR_CTSIZE               SPI_SR_CTSIZE_Msk                          /*!<Number of data frames remaining in TSIZE         */

+

+/*******************  Bit definition for SPI_IFCR register  ********************/

+#define SPI_IFCR_EOTC_Pos           (3U)

+#define SPI_IFCR_EOTC_Msk           (0x1UL << SPI_IFCR_EOTC_Pos)               /*!< 0x00000008 */

+#define SPI_IFCR_EOTC               SPI_IFCR_EOTC_Msk                          /*!<End Of Transfer flag clear              */

+#define SPI_IFCR_TXTFC_Pos          (4U)

+#define SPI_IFCR_TXTFC_Msk          (0x1UL << SPI_IFCR_TXTFC_Pos)              /*!< 0x00000010 */

+#define SPI_IFCR_TXTFC              SPI_IFCR_TXTFC_Msk                         /*!<Transmission Transfer Filled flag clear */

+#define SPI_IFCR_UDRC_Pos           (5U)

+#define SPI_IFCR_UDRC_Msk           (0x1UL << SPI_IFCR_UDRC_Pos)               /*!< 0x00000020 */

+#define SPI_IFCR_UDRC               SPI_IFCR_UDRC_Msk                          /*!<Underrun flag clear                     */

+#define SPI_IFCR_OVRC_Pos           (6U)

+#define SPI_IFCR_OVRC_Msk           (0x1UL << SPI_IFCR_OVRC_Pos)               /*!< 0x00000040 */

+#define SPI_IFCR_OVRC               SPI_IFCR_OVRC_Msk                          /*!<Overrun flag clear                      */

+#define SPI_IFCR_CRCEC_Pos          (7U)

+#define SPI_IFCR_CRCEC_Msk          (0x1UL << SPI_IFCR_CRCEC_Pos)              /*!< 0x00000080 */

+#define SPI_IFCR_CRCEC              SPI_IFCR_CRCEC_Msk                         /*!<CRC Error flag clear                    */

+#define SPI_IFCR_TIFREC_Pos         (8U)

+#define SPI_IFCR_TIFREC_Msk         (0x1UL << SPI_IFCR_TIFREC_Pos)             /*!< 0x00000100 */

+#define SPI_IFCR_TIFREC             SPI_IFCR_TIFREC_Msk                        /*!<TI frame format error flag clear        */

+#define SPI_IFCR_MODFC_Pos          (9U)

+#define SPI_IFCR_MODFC_Msk          (0x1UL << SPI_IFCR_MODFC_Pos)              /*!< 0x00000200 */

+#define SPI_IFCR_MODFC              SPI_IFCR_MODFC_Msk                         /*!<Mode Fault flag clear                   */

+#define SPI_IFCR_TSERFC_Pos         (10U)

+#define SPI_IFCR_TSERFC_Msk         (0x1UL << SPI_IFCR_TSERFC_Pos)             /*!< 0x00000400 */

+#define SPI_IFCR_TSERFC             SPI_IFCR_TSERFC_Msk                        /*!<TSERFC flag clear                       */

+#define SPI_IFCR_SUSPC_Pos          (11U)

+#define SPI_IFCR_SUSPC_Msk          (0x1UL << SPI_IFCR_SUSPC_Pos)              /*!< 0x00000800 */

+#define SPI_IFCR_SUSPC              SPI_IFCR_SUSPC_Msk                         /*!<SUSPend flag clear                      */

+

+/*******************  Bit definition for SPI_TXDR register  ********************/

+#define SPI_TXDR_TXDR_Pos           (0U)

+#define SPI_TXDR_TXDR_Msk           (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)        /*!< 0xFFFFFFFF */

+#define SPI_TXDR_TXDR               SPI_TXDR_TXDR_Msk                          /* Transmit Data Register */

+

+/*******************  Bit definition for SPI_RXDR register  ********************/

+#define SPI_RXDR_RXDR_Pos           (0U)

+#define SPI_RXDR_RXDR_Msk           (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)        /*!< 0xFFFFFFFF */

+#define SPI_RXDR_RXDR               SPI_RXDR_RXDR_Msk                          /* Receive Data Register  */

+

+/*******************  Bit definition for SPI_CRCPOLY register  ********************/

+#define SPI_CRCPOLY_CRCPOLY_Pos     (0U)

+#define SPI_CRCPOLY_CRCPOLY_Msk     (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)  /*!< 0xFFFFFFFF */

+#define SPI_CRCPOLY_CRCPOLY         SPI_CRCPOLY_CRCPOLY_Msk                    /* CRC Polynomial register  */

+

+/*******************  Bit definition for SPI_TXCRC register  ********************/

+#define SPI_TXCRC_TXCRC_Pos         (0U)

+#define SPI_TXCRC_TXCRC_Msk         (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_TXCRC_TXCRC             SPI_TXCRC_TXCRC_Msk                        /* CRCRegister for transmitter */

+

+/*******************  Bit definition for SPI_RXCRC register  ********************/

+#define SPI_RXCRC_RXCRC_Pos         (0U)

+#define SPI_RXCRC_RXCRC_Msk         (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_RXCRC_RXCRC             SPI_RXCRC_RXCRC_Msk                        /* CRCRegister for receiver */

+

+/*******************  Bit definition for SPI_UDRDR register  ********************/

+#define SPI_UDRDR_UDRDR_Pos         (0U)

+#define SPI_UDRDR_UDRDR_Msk         (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_UDRDR_UDRDR             SPI_UDRDR_UDRDR_Msk                        /* Data at slave underrun condition */

+

+/******************  Bit definition for SPI_I2SCFGR register  *****************/

+#define SPI_I2SCFGR_I2SMOD_Pos      (0U)

+#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000001 */

+#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */

+#define SPI_I2SCFGR_I2SCFG_Pos      (1U)

+#define SPI_I2SCFGR_I2SCFG_Msk      (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x0000000E */

+#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[2:0] I2S configuration mode                */

+#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000002 */

+#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000004 */

+#define SPI_I2SCFGR_I2SCFG_2        (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000008 */

+#define SPI_I2SCFGR_I2SSTD_Pos      (4U)

+#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */

+#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] I2S standard selection                */

+#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */

+#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */

+#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)

+#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */

+#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                         */

+#define SPI_I2SCFGR_DATLEN_Pos      (8U)

+#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000300 */

+#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] Data length to be transferred         */

+#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000100 */

+#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000200 */

+#define SPI_I2SCFGR_CHLEN_Pos       (10U)

+#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000400 */

+#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */

+#define SPI_I2SCFGR_CKPOL_Pos       (11U)

+#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000800 */

+#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<Steady state clock polarity                       */

+#define SPI_I2SCFGR_FIXCH_Pos       (12U)

+#define SPI_I2SCFGR_FIXCH_Msk       (0x1UL << SPI_I2SCFGR_FIXCH_Pos)           /*!< 0x00001000 */

+#define SPI_I2SCFGR_FIXCH           SPI_I2SCFGR_FIXCH_Msk                      /*!<Fixed channel length in SLAVE                     */

+#define SPI_I2SCFGR_WSINV_Pos       (13U)

+#define SPI_I2SCFGR_WSINV_Msk       (0x1UL << SPI_I2SCFGR_WSINV_Pos)           /*!< 0x00002000 */

+#define SPI_I2SCFGR_WSINV           SPI_I2SCFGR_WSINV_Msk                      /*!<Word select inversion                             */

+#define SPI_I2SCFGR_DATFMT_Pos      (14U)

+#define SPI_I2SCFGR_DATFMT_Msk      (0x1UL << SPI_I2SCFGR_DATFMT_Pos)          /*!< 0x00004000 */

+#define SPI_I2SCFGR_DATFMT          SPI_I2SCFGR_DATFMT_Msk                     /*!<Data format                                       */

+#define SPI_I2SCFGR_I2SDIV_Pos      (16U)

+#define SPI_I2SCFGR_I2SDIV_Msk      (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)         /*!< 0x00FF0000 */

+#define SPI_I2SCFGR_I2SDIV          SPI_I2SCFGR_I2SDIV_Msk                     /*!<I2S Linear prescaler */

+#define SPI_I2SCFGR_ODD_Pos         (24U)

+#define SPI_I2SCFGR_ODD_Msk         (0x1UL << SPI_I2SCFGR_ODD_Pos)             /*!< 0x01000000 */

+#define SPI_I2SCFGR_ODD             SPI_I2SCFGR_ODD_Msk                        /*!<Odd factor for the prescaler */

+#define SPI_I2SCFGR_MCKOE_Pos       (25U)

+#define SPI_I2SCFGR_MCKOE_Msk       (0x1UL << SPI_I2SCFGR_MCKOE_Pos)           /*!< 0x02000000 */

+#define SPI_I2SCFGR_MCKOE           SPI_I2SCFGR_MCKOE_Msk                      /*!<Master Clock Output Enable */

+

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                 SYSCFG                                     */

+/*                                                                            */

+/******************************************************************************/

+

+/******************  Bit definition for SYSCFG_PMCR register  ******************/

+#define SYSCFG_PMCR_I2C1_FMP_Pos        (0U)

+#define SYSCFG_PMCR_I2C1_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos)    /*!< 0x00000001 */

+#define SYSCFG_PMCR_I2C1_FMP            SYSCFG_PMCR_I2C1_FMP_Msk               /*!< I2C1 Fast mode plus */

+#define SYSCFG_PMCR_I2C2_FMP_Pos        (1U)

+#define SYSCFG_PMCR_I2C2_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos)    /*!< 0x00000002 */

+#define SYSCFG_PMCR_I2C2_FMP            SYSCFG_PMCR_I2C2_FMP_Msk               /*!< I2C2 Fast mode plus */

+#define SYSCFG_PMCR_I2C3_FMP_Pos        (2U)

+#define SYSCFG_PMCR_I2C3_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos)    /*!< 0x00000004 */

+#define SYSCFG_PMCR_I2C3_FMP            SYSCFG_PMCR_I2C3_FMP_Msk               /*!< I2C3 Fast mode plus */

+#define SYSCFG_PMCR_I2C4_FMP_Pos        (3U)

+#define SYSCFG_PMCR_I2C4_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos)    /*!< 0x00000008 */

+#define SYSCFG_PMCR_I2C4_FMP            SYSCFG_PMCR_I2C4_FMP_Msk               /*!< I2C4 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB6_FMP_Pos     (4U)

+#define SYSCFG_PMCR_I2C_PB6_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */

+#define SYSCFG_PMCR_I2C_PB6_FMP         SYSCFG_PMCR_I2C_PB6_FMP_Msk            /*!< I2C PB6 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB7_FMP_Pos     (5U)

+#define SYSCFG_PMCR_I2C_PB7_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */

+#define SYSCFG_PMCR_I2C_PB7_FMP         SYSCFG_PMCR_I2C_PB7_FMP_Msk            /*!< I2C PB7 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB8_FMP_Pos     (6U)

+#define SYSCFG_PMCR_I2C_PB8_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */

+#define SYSCFG_PMCR_I2C_PB8_FMP         SYSCFG_PMCR_I2C_PB8_FMP_Msk            /*!< I2C PB8 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB9_FMP_Pos     (7U)

+#define SYSCFG_PMCR_I2C_PB9_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */

+#define SYSCFG_PMCR_I2C_PB9_FMP         SYSCFG_PMCR_I2C_PB9_FMP_Msk            /*!< I2C PB9 Fast mode plus */

+#define SYSCFG_PMCR_PA0SO_Pos           (24U)

+#define SYSCFG_PMCR_PA0SO_Msk           (0x1UL << SYSCFG_PMCR_PA0SO_Pos)       /*!< 0x01000000 */

+#define SYSCFG_PMCR_PA0SO               SYSCFG_PMCR_PA0SO_Msk                  /*!< PA0 Switch Open */

+#define SYSCFG_PMCR_PA1SO_Pos           (25U)

+#define SYSCFG_PMCR_PA1SO_Msk           (0x1UL << SYSCFG_PMCR_PA1SO_Pos)       /*!< 0x02000000 */

+#define SYSCFG_PMCR_PA1SO               SYSCFG_PMCR_PA1SO_Msk                  /*!< PA1 Switch Open */

+#define SYSCFG_PMCR_PC2SO_Pos           (26U)

+#define SYSCFG_PMCR_PC2SO_Msk           (0x1UL << SYSCFG_PMCR_PC2SO_Pos)       /*!< 0x04000000 */

+#define SYSCFG_PMCR_PC2SO               SYSCFG_PMCR_PC2SO_Msk                  /*!< PC2 Switch Open */

+#define SYSCFG_PMCR_PC3SO_Pos           (27U)

+#define SYSCFG_PMCR_PC3SO_Msk           (0x1UL << SYSCFG_PMCR_PC3SO_Pos)       /*!< 0x08000000 */

+#define SYSCFG_PMCR_PC3SO               SYSCFG_PMCR_PC3SO_Msk                  /*!< PC3 Switch Open */

+

+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/

+#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)

+#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */

+#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)

+#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */

+#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)

+#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000F00 */

+#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */

+#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)

+#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x0000F000 */

+#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */

+/**

+  * @brief   EXTI0 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */

+

+/**

+  * @brief   EXTI1 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */

+/**

+  * @brief   EXTI2 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */

+

+/**

+  * @brief   EXTI3 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/

+#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)

+#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */

+#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)

+#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */

+#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)

+#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000F00 */

+#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */

+#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)

+#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x0000F000 */

+#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */

+/**

+  * @brief   EXTI4 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */

+/**

+  * @brief   EXTI5 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */

+/**

+  * @brief   EXTI6 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */

+

+/**

+  * @brief   EXTI7 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/

+#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)

+#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */

+#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)

+#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */

+#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)

+#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000F00 */

+#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */

+#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)

+#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x0000F000 */

+#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */

+

+/**

+  * @brief   EXTI8 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */

+

+/**

+  * @brief   EXTI9 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */

+

+/**

+  * @brief   EXTI10 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */

+

+/**

+  * @brief   EXTI11 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/

+#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)

+#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x0000000F */

+#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */

+#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)

+#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x000000F0 */

+#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */

+#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)

+#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000F00 */

+#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */

+#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)

+#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x0000F000 */

+#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */

+/**

+  * @brief   EXTI12 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */

+/**

+  * @brief   EXTI13 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */

+/**

+  * @brief   EXTI14 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */

+/**

+  * @brief   EXTI15 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */

+

+/******************  Bit definition for SYSCFG_CFGR register  ******************/

+#define SYSCFG_CFGR_PVDL_Pos            (2U)

+#define SYSCFG_CFGR_PVDL_Msk            (0x1UL << SYSCFG_CFGR_PVDL_Pos)        /*!< 0x00000004 */

+#define SYSCFG_CFGR_PVDL                SYSCFG_CFGR_PVDL_Msk                   /*!<PVD lock enable bit */

+#define SYSCFG_CFGR_FLASHL_Pos          (3U)

+#define SYSCFG_CFGR_FLASHL_Msk          (0x1UL << SYSCFG_CFGR_FLASHL_Pos)      /*!< 0x00000008 */

+#define SYSCFG_CFGR_FLASHL              SYSCFG_CFGR_FLASHL_Msk                 /*!<FLASH double ECC error lock bit */

+#define SYSCFG_CFGR_CM7L_Pos            (6U)

+#define SYSCFG_CFGR_CM7L_Msk            (0x1UL << SYSCFG_CFGR_CM7L_Pos)        /*!< 0x00000040 */

+#define SYSCFG_CFGR_CM7L                SYSCFG_CFGR_CM7L_Msk                   /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */

+#define SYSCFG_CFGR_DTCML_Pos           (13U)

+#define SYSCFG_CFGR_DTCML_Msk           (0x1UL << SYSCFG_CFGR_DTCML_Pos)       /*!< 0x00002000 */

+#define SYSCFG_CFGR_DTCML               SYSCFG_CFGR_DTCML_Msk                  /*!<DTCM double ECC error lock bit */

+#define SYSCFG_CFGR_ITCML_Pos           (14U)

+#define SYSCFG_CFGR_ITCML_Msk           (0x1UL << SYSCFG_CFGR_ITCML_Pos)       /*!< 0x00004000 */

+#define SYSCFG_CFGR_ITCML               SYSCFG_CFGR_ITCML_Msk                  /*!<ITCM double ECC error lock bit */

+/******************  Bit definition for SYSCFG_CCCSR register  ******************/

+#define SYSCFG_CCCSR_EN_Pos             (0U)

+#define SYSCFG_CCCSR_EN_Msk             (0x1UL << SYSCFG_CCCSR_EN_Pos)         /*!< 0x00000001 */

+#define SYSCFG_CCCSR_EN                 SYSCFG_CCCSR_EN_Msk                    /*!< I/O compensation cell enable */

+#define SYSCFG_CCCSR_CS_Pos             (1U)

+#define SYSCFG_CCCSR_CS_Msk             (0x1UL << SYSCFG_CCCSR_CS_Pos)         /*!< 0x00000002 */

+#define SYSCFG_CCCSR_CS                 SYSCFG_CCCSR_CS_Msk                    /*!< I/O compensation cell code selection */

+#define SYSCFG_CCCSR_CS_MMC_Pos         (3U)

+#define SYSCFG_CCCSR_CS_MMC_Msk         (0x1UL << SYSCFG_CCCSR_CS_MMC_Pos)         /*!< 0x00000004 */

+#define SYSCFG_CCCSR_CS_MMC             SYSCFG_CCCSR_CS_MMC_Msk                    /*!< I/O compensation cell code selection */

+#define SYSCFG_CCCSR_READY_Pos          (8U)

+#define SYSCFG_CCCSR_READY_Msk          (0x1UL << SYSCFG_CCCSR_READY_Pos)      /*!< 0x00000100 */

+#define SYSCFG_CCCSR_READY              SYSCFG_CCCSR_READY_Msk                 /*!< I/O compensation cell ready flag */

+#define SYSCFG_CCCSR_HSLV0_Pos           (16U)

+#define SYSCFG_CCCSR_HSLV0_Msk           (0x1UL << SYSCFG_CCCSR_HSLV0_Pos)       /*!< 0x00010000 */

+#define SYSCFG_CCCSR_HSLV0               SYSCFG_CCCSR_HSLV0_Msk                  /*!< High-speed at low-voltage */

+#define SYSCFG_CCCSR_HSLV1_Pos           (17U)

+#define SYSCFG_CCCSR_HSLV1_Msk           (0x1UL << SYSCFG_CCCSR_HSLV1_Pos)       /*!< 0x00020000 */

+#define SYSCFG_CCCSR_HSLV1               SYSCFG_CCCSR_HSLV1_Msk                  /*!< High-speed at low-voltage */

+#define SYSCFG_CCCSR_HSLV2_Pos           (18U)

+#define SYSCFG_CCCSR_HSLV2_Msk           (0x1UL << SYSCFG_CCCSR_HSLV2_Pos)       /*!< 0x00040000 */

+#define SYSCFG_CCCSR_HSLV2               SYSCFG_CCCSR_HSLV2_Msk                  /*!< High-speed at low-voltage */

+#define SYSCFG_CCCSR_HSLV3_Pos           (19U)

+#define SYSCFG_CCCSR_HSLV3_Msk           (0x1UL << SYSCFG_CCCSR_HSLV3_Pos)       /*!< 0x00080000 */

+#define SYSCFG_CCCSR_HSLV3               SYSCFG_CCCSR_HSLV3_Msk                  /*!< High-speed at low-voltage */

+/******************  Bit definition for SYSCFG_CCVR register  *******************/

+#define SYSCFG_CCVR_NCV_Pos             (0U)

+#define SYSCFG_CCVR_NCV_Msk             (0xFUL << SYSCFG_CCVR_NCV_Pos)         /*!< 0x0000000F */

+#define SYSCFG_CCVR_NCV                 SYSCFG_CCVR_NCV_Msk                    /*!< NMOS compensation value */

+#define SYSCFG_CCVR_PCV_Pos             (4U)

+#define SYSCFG_CCVR_PCV_Msk             (0xFUL << SYSCFG_CCVR_PCV_Pos)         /*!< 0x000000F0 */

+#define SYSCFG_CCVR_PCV                 SYSCFG_CCVR_PCV_Msk                    /*!< PMOS compensation value */

+

+/******************  Bit definition for SYSCFG_CCCR register  *******************/

+#define SYSCFG_CCCR_NCC_Pos             (0U)

+#define SYSCFG_CCCR_NCC_Msk             (0xFUL << SYSCFG_CCCR_NCC_Pos)         /*!< 0x0000000F */

+#define SYSCFG_CCCR_NCC                 SYSCFG_CCCR_NCC_Msk                    /*!< NMOS compensation code */

+#define SYSCFG_CCCR_PCC_Pos             (4U)

+#define SYSCFG_CCCR_PCC_Msk             (0xFUL << SYSCFG_CCCR_PCC_Pos)         /*!< 0x000000F0 */

+#define SYSCFG_CCCR_PCC                 SYSCFG_CCCR_PCC_Msk                    /*!< PMOS compensation code */

+#define SYSCFG_CCCR_NCC_MMC_Pos         (8U)

+#define SYSCFG_CCCR_NCC_MMC_Msk         (0xFUL << SYSCFG_CCCR_NCC_MMC_Pos)     /*!< 0x00000F00 */

+#define SYSCFG_CCCR_NCC_MMC             SYSCFG_CCCR_NCC_MMC_Msk                /*!< NMOS compensation code */

+#define SYSCFG_CCCR_PCC_MMC_Pos         (12U)

+#define SYSCFG_CCCR_PCC_MMC_Msk         (0xFUL << SYSCFG_CCCR_PCC_MMC_Pos)     /*!< 0x0000F000 */

+#define SYSCFG_CCCR_PCC_MMC             SYSCFG_CCCR_PCC_MMC_Msk                /*!< PMOS compensation code */

+/******************************************************************************/

+/*                                                                            */

+/*                    Digital Temperature Sensor (DTS)                        */

+/*                                                                            */

+/******************************************************************************/

+

+/******************  Bit definition for DTS_CFGR1 register  ******************/

+#define DTS_CFGR1_TS1_EN_Pos               (0U)

+#define DTS_CFGR1_TS1_EN_Msk               (0x1UL << DTS_CFGR1_TS1_EN_Pos) /*!< 0x00000001 */

+#define DTS_CFGR1_TS1_EN                   DTS_CFGR1_TS1_EN_Msk        /*!< DTS Enable */

+#define DTS_CFGR1_TS1_START_Pos            (4U)

+#define DTS_CFGR1_TS1_START_Msk            (0x1UL << DTS_CFGR1_TS1_START_Pos) /*!< 0x00000010 */

+#define DTS_CFGR1_TS1_START                DTS_CFGR1_TS1_START_Msk     /*!< Proceed to a frequency measurement on DTS */

+#define DTS_CFGR1_TS1_INTRIG_SEL_Pos       (8U)

+#define DTS_CFGR1_TS1_INTRIG_SEL_Msk       (0xFUL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000F00 */

+#define DTS_CFGR1_TS1_INTRIG_SEL           DTS_CFGR1_TS1_INTRIG_SEL_Msk /*!< Input triggers selection bits [3:0] for DTS */

+#define DTS_CFGR1_TS1_INTRIG_SEL_0         (0x1UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000100 */

+#define DTS_CFGR1_TS1_INTRIG_SEL_1         (0x2UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000200 */

+#define DTS_CFGR1_TS1_INTRIG_SEL_2         (0x4UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000400 */

+#define DTS_CFGR1_TS1_INTRIG_SEL_3         (0x8UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000800 */

+#define DTS_CFGR1_TS1_SMP_TIME_Pos         (16U)

+#define DTS_CFGR1_TS1_SMP_TIME_Msk         (0xFUL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x000F0000 */

+#define DTS_CFGR1_TS1_SMP_TIME             DTS_CFGR1_TS1_SMP_TIME_Msk  /*!< Sample time [3:0] for DTS */

+#define DTS_CFGR1_TS1_SMP_TIME_0           (0x1UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00010000 */

+#define DTS_CFGR1_TS1_SMP_TIME_1           (0x2UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00020000 */

+#define DTS_CFGR1_TS1_SMP_TIME_2           (0x4UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00040000 */

+#define DTS_CFGR1_TS1_SMP_TIME_3           (0x8UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00080000 */

+#define DTS_CFGR1_REFCLK_SEL_Pos           (20U)

+#define DTS_CFGR1_REFCLK_SEL_Msk           (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */

+#define DTS_CFGR1_REFCLK_SEL               DTS_CFGR1_REFCLK_SEL_Msk    /*!< Reference Clock Selection */

+#define DTS_CFGR1_Q_MEAS_OPT_Pos           (21U)

+#define DTS_CFGR1_Q_MEAS_OPT_Msk           (0x1UL << DTS_CFGR1_Q_MEAS_OPT_Pos) /*!< 0x00200000 */

+#define DTS_CFGR1_Q_MEAS_OPT               DTS_CFGR1_Q_MEAS_OPT_Msk    /*!< Quick measure option bit  */

+#define DTS_CFGR1_HSREF_CLK_DIV_Pos        (24U)

+#define DTS_CFGR1_HSREF_CLK_DIV_Msk        (0x7FUL << DTS_CFGR1_HSREF_CLK_DIV_Pos) /*!< 0x7F000000 */

+#define DTS_CFGR1_HSREF_CLK_DIV            DTS_CFGR1_HSREF_CLK_DIV_Msk /*!< High Speed Clock Divider Ratio [6:0]*/

+

+/******************  Bit definition for DTS_T0VALR1 register  ******************/

+#define DTS_T0VALR1_TS1_FMT0_Pos           (0U)

+#define DTS_T0VALR1_TS1_FMT0_Msk           (0xFFFFUL << DTS_T0VALR1_TS1_FMT0_Pos) /*!< 0x0000FFFF */

+#define DTS_T0VALR1_TS1_FMT0               DTS_T0VALR1_TS1_FMT0_Msk    /*!< Engineering value of the measured frequency at T0 for DTS */

+#define DTS_T0VALR1_TS1_T0_Pos             (16U)

+#define DTS_T0VALR1_TS1_T0_Msk             (0x3UL << DTS_T0VALR1_TS1_T0_Pos) /*!< 0x00030000 */

+#define DTS_T0VALR1_TS1_T0                 DTS_T0VALR1_TS1_T0_Msk      /*!< Engineering value of the DTSerature T0 for DTS */

+

+/******************  Bit definition for DTS_RAMPVALR register  ******************/

+#define DTS_RAMPVALR_TS1_RAMP_COEFF_Pos    (0U)

+#define DTS_RAMPVALR_TS1_RAMP_COEFF_Msk    (0xFFFFUL << DTS_RAMPVALR_TS1_RAMP_COEFF_Pos) /*!< 0x0000FFFF */

+#define DTS_RAMPVALR_TS1_RAMP_COEFF        DTS_RAMPVALR_TS1_RAMP_COEFF_Msk /*!< Engineering value of the ramp coefficient for DTS */

+

+/******************  Bit definition for DTS_ITR1 register      ******************/

+#define DTS_ITR1_TS1_LITTHD_Pos            (0U)

+#define DTS_ITR1_TS1_LITTHD_Msk            (0xFFFFUL << DTS_ITR1_TS1_LITTHD_Pos) /*!< 0x0000FFFF */

+#define DTS_ITR1_TS1_LITTHD                DTS_ITR1_TS1_LITTHD_Msk     /*!< Low interrupt threshold[15:0] for DTS */

+#define DTS_ITR1_TS1_HITTHD_Pos            (16U)

+#define DTS_ITR1_TS1_HITTHD_Msk            (0xFFFFUL << DTS_ITR1_TS1_HITTHD_Pos) /*!< 0xFFFF0000 */

+#define DTS_ITR1_TS1_HITTHD                DTS_ITR1_TS1_HITTHD_Msk     /*!< High interrupt threshold[15:0] for DTS */

+

+/******************  Bit definition for DTS_DR register        ******************/

+#define DTS_DR_TS1_MFREQ_Pos               (0U)

+#define DTS_DR_TS1_MFREQ_Msk               (0xFFFFUL << DTS_DR_TS1_MFREQ_Pos) /*!< 0x0000FFFF */

+#define DTS_DR_TS1_MFREQ                   DTS_DR_TS1_MFREQ_Msk        /*!< Measured Frequency[15:0] for DTS */

+

+/******************  Bit definition for DTS_SR register        ******************/

+#define DTS_SR_TS1_ITEF_Pos                (0U)

+#define DTS_SR_TS1_ITEF_Msk                (0x1UL << DTS_SR_TS1_ITEF_Pos) /*!< 0x00000001 */

+#define DTS_SR_TS1_ITEF                    DTS_SR_TS1_ITEF_Msk         /*!< Interrupt flag for end of measure for DTS */

+#define DTS_SR_TS1_ITLF_Pos                (1U)

+#define DTS_SR_TS1_ITLF_Msk                (0x1UL << DTS_SR_TS1_ITLF_Pos) /*!< 0x00000002 */

+#define DTS_SR_TS1_ITLF                    DTS_SR_TS1_ITLF_Msk         /*!< Interrupt flag for low threshold for DTS  */

+#define DTS_SR_TS1_ITHF_Pos                (2U)

+#define DTS_SR_TS1_ITHF_Msk                (0x1UL << DTS_SR_TS1_ITHF_Pos) /*!< 0x00000004 */

+#define DTS_SR_TS1_ITHF                    DTS_SR_TS1_ITHF_Msk         /*!< Interrupt flag for high threshold for DTS */

+#define DTS_SR_TS1_AITEF_Pos               (4U)

+#define DTS_SR_TS1_AITEF_Msk               (0x1UL << DTS_SR_TS1_AITEF_Pos) /*!< 0x00000010 */

+#define DTS_SR_TS1_AITEF                   DTS_SR_TS1_AITEF_Msk        /*!< Asynchronous interrupt flag for end of measure for DTS */

+#define DTS_SR_TS1_AITLF_Pos               (5U)

+#define DTS_SR_TS1_AITLF_Msk               (0x1UL << DTS_SR_TS1_AITLF_Pos) /*!< 0x00000020 */

+#define DTS_SR_TS1_AITLF                   DTS_SR_TS1_AITLF_Msk        /*!< Asynchronous interrupt flag for low threshold for DTS  */

+#define DTS_SR_TS1_AITHF_Pos               (6U)

+#define DTS_SR_TS1_AITHF_Msk               (0x1UL << DTS_SR_TS1_AITHF_Pos) /*!< 0x00000040 */

+#define DTS_SR_TS1_AITHF                   DTS_SR_TS1_AITHF_Msk        /*!< Asynchronous interrupt flag for high threshold for DTS */

+#define DTS_SR_TS1_RDY_Pos                 (15U)

+#define DTS_SR_TS1_RDY_Msk                 (0x1UL << DTS_SR_TS1_RDY_Pos) /*!< 0x00008000 */

+#define DTS_SR_TS1_RDY                     DTS_SR_TS1_RDY_Msk          /*!< DTS ready flag */

+

+/******************  Bit definition for DTS_ITENR register      ******************/

+#define DTS_ITENR_TS1_ITEEN_Pos            (0U)

+#define DTS_ITENR_TS1_ITEEN_Msk            (0x1UL << DTS_ITENR_TS1_ITEEN_Pos) /*!< 0x00000001 */

+#define DTS_ITENR_TS1_ITEEN                DTS_ITENR_TS1_ITEEN_Msk     /*!< Enable interrupt flag for end of measure for DTS */

+#define DTS_ITENR_TS1_ITLEN_Pos            (1U)

+#define DTS_ITENR_TS1_ITLEN_Msk            (0x1UL << DTS_ITENR_TS1_ITLEN_Pos) /*!< 0x00000002 */

+#define DTS_ITENR_TS1_ITLEN                DTS_ITENR_TS1_ITLEN_Msk     /*!< Enable interrupt flag for low threshold for DTS  */

+#define DTS_ITENR_TS1_ITHEN_Pos            (2U)

+#define DTS_ITENR_TS1_ITHEN_Msk            (0x1UL << DTS_ITENR_TS1_ITHEN_Pos) /*!< 0x00000004 */

+#define DTS_ITENR_TS1_ITHEN                DTS_ITENR_TS1_ITHEN_Msk     /*!< Enable interrupt flag for high threshold for DTS */

+#define DTS_ITENR_TS1_AITEEN_Pos           (4U)

+#define DTS_ITENR_TS1_AITEEN_Msk           (0x1UL << DTS_ITENR_TS1_AITEEN_Pos) /*!< 0x00000010 */

+#define DTS_ITENR_TS1_AITEEN               DTS_ITENR_TS1_AITEEN_Msk    /*!< Enable asynchronous interrupt flag for end of measure for DTS */

+#define DTS_ITENR_TS1_AITLEN_Pos           (5U)

+#define DTS_ITENR_TS1_AITLEN_Msk           (0x1UL << DTS_ITENR_TS1_AITLEN_Pos) /*!< 0x00000020 */

+#define DTS_ITENR_TS1_AITLEN               DTS_ITENR_TS1_AITLEN_Msk    /*!< Enable Asynchronous interrupt flag for low threshold for DTS  */

+#define DTS_ITENR_TS1_AITHEN_Pos           (6U)

+#define DTS_ITENR_TS1_AITHEN_Msk           (0x1UL << DTS_ITENR_TS1_AITHEN_Pos) /*!< 0x00000040 */

+#define DTS_ITENR_TS1_AITHEN               DTS_ITENR_TS1_AITHEN_Msk    /*!< Enable asynchronous interrupt flag for high threshold for DTS */

+

+/******************  Bit definition for DTS_ICIFR register      ******************/

+#define DTS_ICIFR_TS1_CITEF_Pos            (0U)

+#define DTS_ICIFR_TS1_CITEF_Msk            (0x1UL << DTS_ICIFR_TS1_CITEF_Pos) /*!< 0x00000001 */

+#define DTS_ICIFR_TS1_CITEF                DTS_ICIFR_TS1_CITEF_Msk     /*!< Clear the IT flag for End Of Measure for DTS */

+#define DTS_ICIFR_TS1_CITLF_Pos            (1U)

+#define DTS_ICIFR_TS1_CITLF_Msk            (0x1UL << DTS_ICIFR_TS1_CITLF_Pos) /*!< 0x00000002 */

+#define DTS_ICIFR_TS1_CITLF                DTS_ICIFR_TS1_CITLF_Msk     /*!< Clear the IT flag for low threshold for DTS  */

+#define DTS_ICIFR_TS1_CITHF_Pos            (2U)

+#define DTS_ICIFR_TS1_CITHF_Msk            (0x1UL << DTS_ICIFR_TS1_CITHF_Pos) /*!< 0x00000004 */

+#define DTS_ICIFR_TS1_CITHF                DTS_ICIFR_TS1_CITHF_Msk     /*!< Clear the IT flag for high threshold on DTS  */

+#define DTS_ICIFR_TS1_CAITEF_Pos           (4U)

+#define DTS_ICIFR_TS1_CAITEF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITEF_Pos) /*!< 0x00000010 */

+#define DTS_ICIFR_TS1_CAITEF               DTS_ICIFR_TS1_CAITEF_Msk    /*!< Clear the asynchronous IT flag for End Of Measure for DTS */

+#define DTS_ICIFR_TS1_CAITLF_Pos           (5U)

+#define DTS_ICIFR_TS1_CAITLF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITLF_Pos) /*!< 0x00000020 */

+#define DTS_ICIFR_TS1_CAITLF               DTS_ICIFR_TS1_CAITLF_Msk    /*!< Clear the asynchronous IT flag for low threshold for DTS  */

+#define DTS_ICIFR_TS1_CAITHF_Pos           (6U)

+#define DTS_ICIFR_TS1_CAITHF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITHF_Pos) /*!< 0x00000040 */

+#define DTS_ICIFR_TS1_CAITHF               DTS_ICIFR_TS1_CAITHF_Msk    /*!< Clear the asynchronous IT flag for high threshold on DTS  */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    TIM                                     */

+/*                                                                            */

+/******************************************************************************/

+#define TIM_BREAK_INPUT_SUPPORT             /*!<TIM Break input feature */

+

+/*******************  Bit definition for TIM_CR1 register  ********************/

+#define TIM_CR1_CEN_Pos           (0U)

+#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */

+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */

+#define TIM_CR1_UDIS_Pos          (1U)

+#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */

+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */

+#define TIM_CR1_URS_Pos           (2U)

+#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */

+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */

+#define TIM_CR1_OPM_Pos           (3U)

+#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */

+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */

+#define TIM_CR1_DIR_Pos           (4U)

+#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */

+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */

+

+#define TIM_CR1_CMS_Pos           (5U)

+#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */

+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */

+#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */

+#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */

+

+#define TIM_CR1_ARPE_Pos          (7U)

+#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */

+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */

+

+#define TIM_CR1_CKD_Pos           (8U)

+#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */

+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */

+#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */

+#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */

+

+#define TIM_CR1_UIFREMAP_Pos      (11U)

+#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */

+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */

+

+/*******************  Bit definition for TIM_CR2 register  ********************/

+#define TIM_CR2_CCPC_Pos          (0U)

+#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */

+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */

+#define TIM_CR2_CCUS_Pos          (2U)

+#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */

+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */

+#define TIM_CR2_CCDS_Pos          (3U)

+#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */

+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */

+

+#define TIM_CR2_MMS_Pos           (4U)

+#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */

+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */

+#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */

+#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */

+#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */

+

+#define TIM_CR2_TI1S_Pos          (7U)

+#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */

+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */

+#define TIM_CR2_OIS1_Pos          (8U)

+#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */

+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */

+#define TIM_CR2_OIS1N_Pos         (9U)

+#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */

+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */

+#define TIM_CR2_OIS2_Pos          (10U)

+#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */

+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */

+#define TIM_CR2_OIS2N_Pos         (11U)

+#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */

+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */

+#define TIM_CR2_OIS3_Pos          (12U)

+#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */

+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */

+#define TIM_CR2_OIS3N_Pos         (13U)

+#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */

+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */

+#define TIM_CR2_OIS4_Pos          (14U)

+#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */

+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */

+#define TIM_CR2_OIS5_Pos          (16U)

+#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */

+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */

+#define TIM_CR2_OIS6_Pos          (17U)

+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */

+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */

+

+#define TIM_CR2_MMS2_Pos          (20U)

+#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */

+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */

+#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */

+#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */

+#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */

+#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */

+

+/*******************  Bit definition for TIM_SMCR register  *******************/

+#define TIM_SMCR_SMS_Pos          (0U)

+#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */

+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */

+#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */

+#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */

+#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */

+#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */

+

+#define TIM_SMCR_TS_Pos           (4U)

+#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */

+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[4:0] bits (Trigger selection) */

+#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)                /*!< 0x00000010 */

+#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)                /*!< 0x00000020 */

+#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)                /*!< 0x00000040 */

+#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)                /*!< 0x00100000 */

+#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)                /*!< 0x00200000 */

+

+#define TIM_SMCR_MSM_Pos          (7U)

+#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */

+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */

+

+#define TIM_SMCR_ETF_Pos          (8U)

+#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */

+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */

+#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */

+#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */

+#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */

+#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */

+

+#define TIM_SMCR_ETPS_Pos         (12U)

+#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */

+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */

+#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */

+#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */

+

+#define TIM_SMCR_ECE_Pos          (14U)

+#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */

+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */

+#define TIM_SMCR_ETP_Pos          (15U)

+#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */

+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */

+

+/*******************  Bit definition for TIM_DIER register  *******************/

+#define TIM_DIER_UIE_Pos          (0U)

+#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */

+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */

+#define TIM_DIER_CC1IE_Pos        (1U)

+#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */

+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */

+#define TIM_DIER_CC2IE_Pos        (2U)

+#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */

+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */

+#define TIM_DIER_CC3IE_Pos        (3U)

+#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */

+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */

+#define TIM_DIER_CC4IE_Pos        (4U)

+#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */

+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */

+#define TIM_DIER_COMIE_Pos        (5U)

+#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */

+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */

+#define TIM_DIER_TIE_Pos          (6U)

+#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */

+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */

+#define TIM_DIER_BIE_Pos          (7U)

+#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */

+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */

+#define TIM_DIER_UDE_Pos          (8U)

+#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */

+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */

+#define TIM_DIER_CC1DE_Pos        (9U)

+#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */

+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */

+#define TIM_DIER_CC2DE_Pos        (10U)

+#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */

+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */

+#define TIM_DIER_CC3DE_Pos        (11U)

+#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */

+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */

+#define TIM_DIER_CC4DE_Pos        (12U)

+#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */

+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */

+#define TIM_DIER_COMDE_Pos        (13U)

+#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */

+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */

+#define TIM_DIER_TDE_Pos          (14U)

+#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */

+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */

+

+/********************  Bit definition for TIM_SR register  ********************/

+#define TIM_SR_UIF_Pos            (0U)

+#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */

+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */

+#define TIM_SR_CC1IF_Pos          (1U)

+#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */

+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */

+#define TIM_SR_CC2IF_Pos          (2U)

+#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */

+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */

+#define TIM_SR_CC3IF_Pos          (3U)

+#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */

+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */

+#define TIM_SR_CC4IF_Pos          (4U)

+#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */

+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */

+#define TIM_SR_COMIF_Pos          (5U)

+#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */

+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */

+#define TIM_SR_TIF_Pos            (6U)

+#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */

+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */

+#define TIM_SR_BIF_Pos            (7U)

+#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */

+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */

+#define TIM_SR_B2IF_Pos           (8U)

+#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */

+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break2 interrupt Flag */

+#define TIM_SR_CC1OF_Pos          (9U)

+#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */

+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */

+#define TIM_SR_CC2OF_Pos          (10U)

+#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */

+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */

+#define TIM_SR_CC3OF_Pos          (11U)

+#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */

+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */

+#define TIM_SR_CC4OF_Pos          (12U)

+#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */

+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */

+#define TIM_SR_CC5IF_Pos          (16U)

+#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */

+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */

+#define TIM_SR_CC6IF_Pos          (17U)

+#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */

+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */

+#define TIM_SR_SBIF_Pos           (13U)

+#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */

+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!< System Break Flag */

+

+/*******************  Bit definition for TIM_EGR register  ********************/

+#define TIM_EGR_UG_Pos            (0U)

+#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */

+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */

+#define TIM_EGR_CC1G_Pos          (1U)

+#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */

+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */

+#define TIM_EGR_CC2G_Pos          (2U)

+#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */

+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */

+#define TIM_EGR_CC3G_Pos          (3U)

+#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */

+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */

+#define TIM_EGR_CC4G_Pos          (4U)

+#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */

+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */

+#define TIM_EGR_COMG_Pos          (5U)

+#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */

+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */

+#define TIM_EGR_TG_Pos            (6U)

+#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */

+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */

+#define TIM_EGR_BG_Pos            (7U)

+#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */

+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */

+#define TIM_EGR_B2G_Pos           (8U)

+#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */

+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break Generation */

+

+

+/******************  Bit definition for TIM_CCMR1 register  *******************/

+#define TIM_CCMR1_CC1S_Pos        (0U)

+#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */

+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */

+#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */

+#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */

+

+#define TIM_CCMR1_OC1FE_Pos       (2U)

+#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */

+#define TIM_CCMR1_OC1PE_Pos       (3U)

+#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */

+

+#define TIM_CCMR1_OC1M_Pos        (4U)

+#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */

+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */

+#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */

+#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */

+#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */

+#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR1_OC1CE_Pos       (7U)

+#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */

+

+#define TIM_CCMR1_CC2S_Pos        (8U)

+#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */

+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */

+#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */

+#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */

+

+#define TIM_CCMR1_OC2FE_Pos       (10U)

+#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */

+#define TIM_CCMR1_OC2PE_Pos       (11U)

+#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */

+

+#define TIM_CCMR1_OC2M_Pos        (12U)

+#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */

+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */

+#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */

+#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */

+#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */

+#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */

+

+#define TIM_CCMR1_OC2CE_Pos       (15U)

+#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */

+

+/*----------------------------------------------------------------------------*/

+

+#define TIM_CCMR1_IC1PSC_Pos      (2U)

+#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */

+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */

+#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */

+

+#define TIM_CCMR1_IC1F_Pos        (4U)

+#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */

+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */

+#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */

+

+#define TIM_CCMR1_IC2PSC_Pos      (10U)

+#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */

+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */

+#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */

+

+#define TIM_CCMR1_IC2F_Pos        (12U)

+#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */

+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */

+#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */

+

+/******************  Bit definition for TIM_CCMR2 register  *******************/

+#define TIM_CCMR2_CC3S_Pos        (0U)

+#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */

+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */

+#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */

+#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */

+

+#define TIM_CCMR2_OC3FE_Pos       (2U)

+#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */

+#define TIM_CCMR2_OC3PE_Pos       (3U)

+#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */

+

+#define TIM_CCMR2_OC3M_Pos        (4U)

+#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */

+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */

+#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR2_OC3CE_Pos       (7U)

+#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */

+

+#define TIM_CCMR2_CC4S_Pos        (8U)

+#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */

+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */

+#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */

+#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */

+

+#define TIM_CCMR2_OC4FE_Pos       (10U)

+#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */

+#define TIM_CCMR2_OC4PE_Pos       (11U)

+#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */

+

+#define TIM_CCMR2_OC4M_Pos        (12U)

+#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */

+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */

+#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */

+

+#define TIM_CCMR2_OC4CE_Pos       (15U)

+#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */

+

+/*----------------------------------------------------------------------------*/

+

+#define TIM_CCMR2_IC3PSC_Pos      (2U)

+#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */

+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */

+#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */

+

+#define TIM_CCMR2_IC3F_Pos        (4U)

+#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */

+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */

+#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */

+

+#define TIM_CCMR2_IC4PSC_Pos      (10U)

+#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */

+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */

+#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */

+

+#define TIM_CCMR2_IC4F_Pos        (12U)

+#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */

+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */

+#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */

+

+/*******************  Bit definition for TIM_CCER register  *******************/

+#define TIM_CCER_CC1E_Pos         (0U)

+#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */

+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */

+#define TIM_CCER_CC1P_Pos         (1U)

+#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */

+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */

+#define TIM_CCER_CC1NE_Pos        (2U)

+#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */

+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */

+#define TIM_CCER_CC1NP_Pos        (3U)

+#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */

+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */

+#define TIM_CCER_CC2E_Pos         (4U)

+#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */

+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */

+#define TIM_CCER_CC2P_Pos         (5U)

+#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */

+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */

+#define TIM_CCER_CC2NE_Pos        (6U)

+#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */

+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */

+#define TIM_CCER_CC2NP_Pos        (7U)

+#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */

+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */

+#define TIM_CCER_CC3E_Pos         (8U)

+#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */

+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */

+#define TIM_CCER_CC3P_Pos         (9U)

+#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */

+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */

+#define TIM_CCER_CC3NE_Pos        (10U)

+#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */

+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */

+#define TIM_CCER_CC3NP_Pos        (11U)

+#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */

+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */

+#define TIM_CCER_CC4E_Pos         (12U)

+#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */

+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */

+#define TIM_CCER_CC4P_Pos         (13U)

+#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */

+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */

+#define TIM_CCER_CC4NP_Pos        (15U)

+#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */

+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */

+#define TIM_CCER_CC5E_Pos         (16U)

+#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */

+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */

+#define TIM_CCER_CC5P_Pos         (17U)

+#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */

+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */

+#define TIM_CCER_CC6E_Pos         (20U)

+#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */

+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */

+#define TIM_CCER_CC6P_Pos         (21U)

+#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */

+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */

+/*******************  Bit definition for TIM_CNT register  ********************/

+#define TIM_CNT_CNT_Pos           (0U)

+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */

+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */

+#define TIM_CNT_UIFCPY_Pos        (31U)

+#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */

+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy */

+/*******************  Bit definition for TIM_PSC register  ********************/

+#define TIM_PSC_PSC_Pos           (0U)

+#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */

+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */

+

+/*******************  Bit definition for TIM_ARR register  ********************/

+#define TIM_ARR_ARR_Pos           (0U)

+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */

+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */

+

+/*******************  Bit definition for TIM_RCR register  ********************/

+#define TIM_RCR_REP_Pos           (0U)

+#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                  /*!< 0x000000FF */

+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */

+

+/*******************  Bit definition for TIM_CCR1 register  *******************/

+#define TIM_CCR1_CCR1_Pos         (0U)

+#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */

+

+/*******************  Bit definition for TIM_CCR2 register  *******************/

+#define TIM_CCR2_CCR2_Pos         (0U)

+#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */

+

+/*******************  Bit definition for TIM_CCR3 register  *******************/

+#define TIM_CCR3_CCR3_Pos         (0U)

+#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */

+

+/*******************  Bit definition for TIM_CCR4 register  *******************/

+#define TIM_CCR4_CCR4_Pos         (0U)

+#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */

+

+/*******************  Bit definition for TIM_CCR5 register  *******************/

+#define TIM_CCR5_CCR5_Pos         (0U)

+#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */

+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */

+#define TIM_CCR5_GC5C1_Pos        (29U)

+#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */

+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */

+#define TIM_CCR5_GC5C2_Pos        (30U)

+#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */

+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */

+#define TIM_CCR5_GC5C3_Pos        (31U)

+#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */

+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */

+

+/*******************  Bit definition for TIM_CCR6 register  *******************/

+#define TIM_CCR6_CCR6_Pos         (0U)

+#define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */

+

+/*******************  Bit definition for TIM_BDTR register  *******************/

+#define TIM_BDTR_DTG_Pos          (0U)

+#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */

+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */

+#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */

+#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */

+#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */

+#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */

+#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */

+#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */

+#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */

+#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */

+

+#define TIM_BDTR_LOCK_Pos         (8U)

+#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */

+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */

+#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */

+#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */

+

+#define TIM_BDTR_OSSI_Pos         (10U)

+#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */

+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */

+#define TIM_BDTR_OSSR_Pos         (11U)

+#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */

+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */

+#define TIM_BDTR_BKE_Pos          (12U)

+#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */

+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break1 */

+#define TIM_BDTR_BKP_Pos          (13U)

+#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */

+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break1 */

+#define TIM_BDTR_AOE_Pos          (14U)

+#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */

+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */

+#define TIM_BDTR_MOE_Pos          (15U)

+#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */

+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */

+

+#define TIM_BDTR_BKF_Pos          (16U)

+#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */

+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break1 */

+#define TIM_BDTR_BK2F_Pos         (20U)

+#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */

+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break2 */

+

+#define TIM_BDTR_BK2E_Pos         (24U)

+#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */

+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break2 */

+#define TIM_BDTR_BK2P_Pos         (25U)

+#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */

+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */

+

+/*******************  Bit definition for TIM_DCR register  ********************/

+#define TIM_DCR_DBA_Pos           (0U)

+#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */

+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */

+#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */

+#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */

+#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */

+#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */

+#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */

+

+#define TIM_DCR_DBL_Pos           (8U)

+#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */

+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */

+#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */

+#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */

+#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */

+#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */

+#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */

+

+/*******************  Bit definition for TIM_DMAR register  *******************/

+#define TIM_DMAR_DMAB_Pos         (0U)

+#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */

+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */

+

+/******************  Bit definition for TIM_CCMR3 register  *******************/

+#define TIM_CCMR3_OC5FE_Pos       (2U)

+#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */

+#define TIM_CCMR3_OC5PE_Pos       (3U)

+#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */

+

+#define TIM_CCMR3_OC5M_Pos        (4U)

+#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */

+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */

+#define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR3_OC5CE_Pos       (7U)

+#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */

+

+#define TIM_CCMR3_OC6FE_Pos       (10U)

+#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 4 Fast enable */

+#define TIM_CCMR3_OC6PE_Pos       (11U)

+#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */

+

+#define TIM_CCMR3_OC6M_Pos        (12U)

+#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */

+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */

+#define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */

+

+#define TIM_CCMR3_OC6CE_Pos       (15U)

+#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 4 Clear Enable */

+/*******************  Bit definition for TIM1_AF1 register  *********************/

+#define TIM1_AF1_BKINE_Pos        (0U)

+#define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */

+#define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */

+#define TIM1_AF1_BKCMP1E_Pos      (1U)

+#define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */

+#define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM1_AF1_BKCMP2E_Pos      (2U)

+#define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */

+#define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit */

+#define TIM1_AF1_BKDF1BK0E_Pos    (8U)

+#define TIM1_AF1_BKDF1BK0E_Msk    (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)            /*!< 0x00000100 */

+#define TIM1_AF1_BKDF1BK0E        TIM1_AF1_BKDF1BK0E_Msk                       /*!<BKDF1BK0E Break input DFSDM Break 0 */

+#define TIM1_AF1_BKINP_Pos        (9U)

+#define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */

+#define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */

+#define TIM1_AF1_BKCMP1P_Pos      (10U)

+#define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */

+#define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM1_AF1_BKCMP2P_Pos      (11U)

+#define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */

+#define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */

+

+#define TIM1_AF1_ETRSEL_Pos       (14U)

+#define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */

+#define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */

+#define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00004000 */

+#define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00008000 */

+#define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00010000 */

+#define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM1_AF2 register  *********************/

+#define TIM1_AF2_BK2INE_Pos       (0U)

+#define TIM1_AF2_BK2INE_Msk       (0x1UL << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */

+#define TIM1_AF2_BK2INE           TIM1_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */

+#define TIM1_AF2_BK2CMP1E_Pos     (1U)

+#define TIM1_AF2_BK2CMP1E_Msk     (0x1UL << TIM1_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */

+#define TIM1_AF2_BK2CMP1E         TIM1_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */

+#define TIM1_AF2_BK2CMP2E_Pos     (2U)

+#define TIM1_AF2_BK2CMP2E_Msk     (0x1UL << TIM1_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */

+#define TIM1_AF2_BK2CMP2E         TIM1_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */

+#define TIM1_AF2_BK2DFBK1E_Pos    (8U)

+#define TIM1_AF2_BK2DFBK1E_Msk    (0x1UL << TIM1_AF2_BK2DFBK1E_Pos)            /*!< 0x00000100 */

+#define TIM1_AF2_BK2DFBK1E        TIM1_AF2_BK2DFBK1E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 1 */

+#define TIM1_AF2_BK2INP_Pos       (9U)

+#define TIM1_AF2_BK2INP_Msk       (0x1UL << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */

+#define TIM1_AF2_BK2INP           TIM1_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */

+#define TIM1_AF2_BK2CMP1P_Pos     (10U)

+#define TIM1_AF2_BK2CMP1P_Msk     (0x1UL << TIM1_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */

+#define TIM1_AF2_BK2CMP1P         TIM1_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */

+#define TIM1_AF2_BK2CMP2P_Pos     (11U)

+#define TIM1_AF2_BK2CMP2P_Msk     (0x1UL << TIM1_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */

+#define TIM1_AF2_BK2CMP2P         TIM1_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */

+

+/*******************  Bit definition for TIM_TISEL register  *********************/

+#define TIM_TISEL_TI1SEL_Pos      (0U)

+#define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */

+#define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/

+#define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000001 */

+#define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000002 */

+#define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000004 */

+#define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000008 */

+

+#define TIM_TISEL_TI2SEL_Pos      (8U)

+#define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */

+#define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/

+#define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000100 */

+#define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000200 */

+#define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000400 */

+#define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000800 */

+

+#define TIM_TISEL_TI3SEL_Pos      (16U)

+#define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */

+#define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/

+#define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00010000 */

+#define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00020000 */

+#define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00040000 */

+#define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00080000 */

+

+#define TIM_TISEL_TI4SEL_Pos      (24U)

+#define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */

+#define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/

+#define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x01000000 */

+#define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x02000000 */

+#define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x04000000 */

+#define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x08000000 */

+

+/*******************  Bit definition for TIM8_AF1 register  *********************/

+#define TIM8_AF1_BKINE_Pos        (0U)

+#define TIM8_AF1_BKINE_Msk        (0x1UL << TIM8_AF1_BKINE_Pos)                /*!< 0x00000001 */

+#define TIM8_AF1_BKINE            TIM8_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */

+#define TIM8_AF1_BKCMP1E_Pos      (1U)

+#define TIM8_AF1_BKCMP1E_Msk      (0x1UL << TIM8_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */

+#define TIM8_AF1_BKCMP1E          TIM8_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM8_AF1_BKCMP2E_Pos      (2U)

+#define TIM8_AF1_BKCMP2E_Msk      (0x1UL << TIM8_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */

+#define TIM8_AF1_BKCMP2E          TIM8_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM8_AF1_BKDFBK2E_Pos     (8U)

+#define TIM8_AF1_BKDFBK2E_Msk     (0x1UL << TIM8_AF1_BKDFBK2E_Pos)             /*!< 0x00000100 */

+#define TIM8_AF1_BKDFBK2E         TIM8_AF1_BKDFBK2E_Msk                        /*!<BKDFBK2E Break input DFSDM Break 2 */

+#define TIM8_AF1_BKINP_Pos        (9U)

+#define TIM8_AF1_BKINP_Msk        (0x1UL << TIM8_AF1_BKINP_Pos)                /*!< 0x00000200 */

+#define TIM8_AF1_BKINP            TIM8_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */

+#define TIM8_AF1_BKCMP1P_Pos      (10U)

+#define TIM8_AF1_BKCMP1P_Msk      (0x1UL << TIM8_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */

+#define TIM8_AF1_BKCMP1P          TIM8_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM8_AF1_BKCMP2P_Pos      (11U)

+#define TIM8_AF1_BKCMP2P_Msk      (0x1UL << TIM8_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */

+#define TIM8_AF1_BKCMP2P          TIM8_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */

+

+#define TIM8_AF1_ETRSEL_Pos       (14U)

+#define TIM8_AF1_ETRSEL_Msk       (0xFUL << TIM8_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */

+#define TIM8_AF1_ETRSEL           TIM8_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */

+#define TIM8_AF1_ETRSEL_0         (0x1UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00004000 */

+#define TIM8_AF1_ETRSEL_1         (0x2UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00008000 */

+#define TIM8_AF1_ETRSEL_2         (0x4UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00010000 */

+#define TIM8_AF1_ETRSEL_3         (0x8UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00020000 */

+/*******************  Bit definition for TIM8_AF2 register  *********************/

+#define TIM8_AF2_BK2INE_Pos       (0U)

+#define TIM8_AF2_BK2INE_Msk       (0x1UL << TIM8_AF2_BK2INE_Pos)               /*!< 0x00000001 */

+#define TIM8_AF2_BK2INE           TIM8_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */

+#define TIM8_AF2_BK2CMP1E_Pos     (1U)

+#define TIM8_AF2_BK2CMP1E_Msk     (0x1UL << TIM8_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */

+#define TIM8_AF2_BK2CMP1E         TIM8_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */

+#define TIM8_AF2_BK2CMP2E_Pos     (2U)

+#define TIM8_AF2_BK2CMP2E_Msk     (0x1UL << TIM8_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */

+#define TIM8_AF2_BK2CMP2E         TIM8_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */

+#define TIM8_AF2_BK2DFBK3E_Pos    (8U)

+#define TIM8_AF2_BK2DFBK3E_Msk    (0x1UL << TIM8_AF2_BK2DFBK3E_Pos)            /*!< 0x00000100 */

+#define TIM8_AF2_BK2DFBK3E        TIM8_AF2_BK2DFBK3E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 3 */

+#define TIM8_AF2_BK2INP_Pos       (9U)

+#define TIM8_AF2_BK2INP_Msk       (0x1UL << TIM8_AF2_BK2INP_Pos)               /*!< 0x00000200 */

+#define TIM8_AF2_BK2INP           TIM8_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */

+#define TIM8_AF2_BK2CMP1P_Pos     (10U)

+#define TIM8_AF2_BK2CMP1P_Msk     (0x1UL << TIM8_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */

+#define TIM8_AF2_BK2CMP1P         TIM8_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */

+#define TIM8_AF2_BK2CMP2P_Pos     (11U)

+#define TIM8_AF2_BK2CMP2P_Msk     (0x1UL << TIM8_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */

+#define TIM8_AF2_BK2CMP2P         TIM8_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */

+

+/*******************  Bit definition for TIM2_AF1 register  *********************/

+#define TIM2_AF1_ETRSEL_Pos      (14U)

+#define TIM2_AF1_ETRSEL_Msk      (0xFUL << TIM2_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM2_AF1_ETRSEL          TIM2_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */

+#define TIM2_AF1_ETRSEL_0        (0x1UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM2_AF1_ETRSEL_1        (0x2UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM2_AF1_ETRSEL_2        (0x4UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM2_AF1_ETRSEL_3        (0x8UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM3_AF1 register  *********************/

+#define TIM3_AF1_ETRSEL_Pos      (14U)

+#define TIM3_AF1_ETRSEL_Msk      (0xFUL << TIM3_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM3_AF1_ETRSEL          TIM3_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */

+#define TIM3_AF1_ETRSEL_0        (0x1UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM3_AF1_ETRSEL_1        (0x2UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM3_AF1_ETRSEL_2        (0x4UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM3_AF1_ETRSEL_3        (0x8UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM5_AF1 register  *********************/

+#define TIM5_AF1_ETRSEL_Pos      (14U)

+#define TIM5_AF1_ETRSEL_Msk      (0xFUL << TIM5_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM5_AF1_ETRSEL          TIM5_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */

+#define TIM5_AF1_ETRSEL_0        (0x1UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM5_AF1_ETRSEL_1        (0x2UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM5_AF1_ETRSEL_2        (0x4UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM5_AF1_ETRSEL_3        (0x8UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM15_AF1 register  *********************/

+#define TIM15_AF1_BKINE_Pos        (0U)

+#define TIM15_AF1_BKINE_Msk        (0x1UL << TIM15_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM15_AF1_BKINE            TIM15_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM15_AF1_BKCMP1E_Pos      (1U)

+#define TIM15_AF1_BKCMP1E_Msk      (0x1UL << TIM15_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM15_AF1_BKCMP1E          TIM15_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM15_AF1_BKCMP2E_Pos      (2U)

+#define TIM15_AF1_BKCMP2E_Msk      (0x1UL << TIM15_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM15_AF1_BKCMP2E          TIM15_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM15_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM15_AF1_BKDF1BK2E_Msk    (0x1UL << TIM15_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM15_AF1_BKDF1BK2E        TIM15_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[0] enable */

+#define TIM15_AF1_BKINP_Pos        (9U)

+#define TIM15_AF1_BKINP_Msk        (0x1UL << TIM15_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM15_AF1_BKINP            TIM15_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM15_AF1_BKCMP1P_Pos      (10U)

+#define TIM15_AF1_BKCMP1P_Msk      (0x1UL << TIM15_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM15_AF1_BKCMP1P          TIM15_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM15_AF1_BKCMP2P_Pos      (11U)

+#define TIM15_AF1_BKCMP2P_Msk      (0x1UL << TIM15_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM15_AF1_BKCMP2P          TIM15_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/*******************  Bit definition for TIM16_ register  *********************/

+#define TIM16_AF1_BKINE_Pos        (0U)

+#define TIM16_AF1_BKINE_Msk        (0x1UL << TIM16_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM16_AF1_BKINE            TIM16_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM16_AF1_BKCMP1E_Pos      (1U)

+#define TIM16_AF1_BKCMP1E_Msk      (0x1UL << TIM16_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM16_AF1_BKCMP1E          TIM16_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM16_AF1_BKCMP2E_Pos      (2U)

+#define TIM16_AF1_BKCMP2E_Msk      (0x1UL << TIM16_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM16_AF1_BKCMP2E          TIM16_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM16_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM16_AF1_BKDF1BK2E_Msk    (0x1UL << TIM16_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM16_AF1_BKDF1BK2E        TIM16_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[1] enable */

+#define TIM16_AF1_BKINP_Pos        (9U)

+#define TIM16_AF1_BKINP_Msk        (0x1UL << TIM16_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM16_AF1_BKINP            TIM16_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM16_AF1_BKCMP1P_Pos      (10U)

+#define TIM16_AF1_BKCMP1P_Msk      (0x1UL << TIM16_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM16_AF1_BKCMP1P          TIM16_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM16_AF1_BKCMP2P_Pos      (11U)

+#define TIM16_AF1_BKCMP2P_Msk      (0x1UL << TIM16_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM16_AF1_BKCMP2P          TIM16_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/*******************  Bit definition for TIM17_AF1 register  *********************/

+#define TIM17_AF1_BKINE_Pos        (0U)

+#define TIM17_AF1_BKINE_Msk        (0x1UL << TIM17_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM17_AF1_BKINE            TIM17_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM17_AF1_BKCMP1E_Pos      (1U)

+#define TIM17_AF1_BKCMP1E_Msk      (0x1UL << TIM17_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM17_AF1_BKCMP1E          TIM17_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM17_AF1_BKCMP2E_Pos      (2U)

+#define TIM17_AF1_BKCMP2E_Msk      (0x1UL << TIM17_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM17_AF1_BKCMP2E          TIM17_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM17_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM17_AF1_BKDF1BK2E_Msk    (0x1UL << TIM17_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM17_AF1_BKDF1BK2E        TIM17_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[2] enable */

+#define TIM17_AF1_BKINP_Pos        (9U)

+#define TIM17_AF1_BKINP_Msk        (0x1UL << TIM17_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM17_AF1_BKINP            TIM17_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM17_AF1_BKCMP1P_Pos      (10U)

+#define TIM17_AF1_BKCMP1P_Msk      (0x1UL << TIM17_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM17_AF1_BKCMP1P          TIM17_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM17_AF1_BKCMP2P_Pos      (11U)

+#define TIM17_AF1_BKCMP2P_Msk      (0x1UL << TIM17_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM17_AF1_BKCMP2P          TIM17_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Low Power Timer (LPTTIM)                           */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for LPTIM_ISR register  *******************/

+#define LPTIM_ISR_CMPM_Pos          (0U)

+#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */

+#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */

+#define LPTIM_ISR_ARRM_Pos          (1U)

+#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */

+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */

+#define LPTIM_ISR_EXTTRIG_Pos       (2U)

+#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */

+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */

+#define LPTIM_ISR_CMPOK_Pos         (3U)

+#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */

+#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */

+#define LPTIM_ISR_ARROK_Pos         (4U)

+#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */

+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */

+#define LPTIM_ISR_UP_Pos            (5U)

+#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */

+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */

+#define LPTIM_ISR_DOWN_Pos          (6U)

+#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */

+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */

+

+/******************  Bit definition for LPTIM_ICR register  *******************/

+#define LPTIM_ICR_CMPMCF_Pos        (0U)

+#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */

+#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */

+#define LPTIM_ICR_ARRMCF_Pos        (1U)

+#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */

+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */

+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)

+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */

+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */

+#define LPTIM_ICR_CMPOKCF_Pos       (3U)

+#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */

+#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */

+#define LPTIM_ICR_ARROKCF_Pos       (4U)

+#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */

+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */

+#define LPTIM_ICR_UPCF_Pos          (5U)

+#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */

+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */

+#define LPTIM_ICR_DOWNCF_Pos        (6U)

+#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */

+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */

+

+/******************  Bit definition for LPTIM_IER register ********************/

+#define LPTIM_IER_CMPMIE_Pos        (0U)

+#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */

+#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */

+#define LPTIM_IER_ARRMIE_Pos        (1U)

+#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */

+#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */

+#define LPTIM_IER_EXTTRIGIE_Pos     (2U)

+#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */

+#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */

+#define LPTIM_IER_CMPOKIE_Pos       (3U)

+#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */

+#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */

+#define LPTIM_IER_ARROKIE_Pos       (4U)

+#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */

+#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */

+#define LPTIM_IER_UPIE_Pos          (5U)

+#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */

+#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */

+#define LPTIM_IER_DOWNIE_Pos        (6U)

+#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */

+#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */

+

+/******************  Bit definition for LPTIM_CFGR register *******************/

+#define LPTIM_CFGR_CKSEL_Pos        (0U)

+#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */

+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */

+

+#define LPTIM_CFGR_CKPOL_Pos        (1U)

+#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */

+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */

+#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */

+#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */

+

+#define LPTIM_CFGR_CKFLT_Pos        (3U)

+#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */

+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */

+#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */

+#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */

+

+#define LPTIM_CFGR_TRGFLT_Pos       (6U)

+#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */

+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */

+#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */

+#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */

+

+#define LPTIM_CFGR_PRESC_Pos        (9U)

+#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */

+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */

+#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */

+#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */

+#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */

+

+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)

+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */

+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */

+#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */

+#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */

+#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */

+

+#define LPTIM_CFGR_TRIGEN_Pos       (17U)

+#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */

+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */

+#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */

+#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */

+

+#define LPTIM_CFGR_TIMOUT_Pos       (19U)

+#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */

+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */

+#define LPTIM_CFGR_WAVE_Pos         (20U)

+#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */

+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */

+#define LPTIM_CFGR_WAVPOL_Pos       (21U)

+#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */

+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */

+#define LPTIM_CFGR_PRELOAD_Pos      (22U)

+#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */

+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */

+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)

+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */

+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */

+#define LPTIM_CFGR_ENC_Pos          (24U)

+#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */

+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */

+

+/******************  Bit definition for LPTIM_CR register  ********************/

+#define LPTIM_CR_ENABLE_Pos         (0U)

+#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */

+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */

+#define LPTIM_CR_SNGSTRT_Pos        (1U)

+#define LPTIM_CR_SNGSTRT_Msk        (0x40001UL << LPTIM_CR_SNGSTRT_Pos)        /*!< 0x00080002 */

+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */

+#define LPTIM_CR_CNTSTRT_Pos        (2U)

+#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */

+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */

+#define LPTIM_CR_COUNTRST_Pos       (3U)

+#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */

+#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Timer Counter reset in synchronous mode*/

+#define LPTIM_CR_RSTARE_Pos         (4U)

+#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */

+#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Timer Counter reset after read enable (asynchronously)*/

+

+

+/******************  Bit definition for LPTIM_CMP register  *******************/

+#define LPTIM_CMP_CMP_Pos           (0U)

+#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */

+

+/******************  Bit definition for LPTIM_ARR register  *******************/

+#define LPTIM_ARR_ARR_Pos           (0U)

+#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */

+

+/******************  Bit definition for LPTIM_CNT register  *******************/

+#define LPTIM_CNT_CNT_Pos           (0U)

+#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */

+

+/******************  Bit definition for LPTIM_CFGR2 register  *****************/

+#define LPTIM_CFGR2_IN1SEL_Pos      (0U)

+#define LPTIM_CFGR2_IN1SEL_Msk      (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000003 */

+#define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< IN1SEL[1:0] bits (Remap selection) */

+#define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000001 */

+#define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000002 */

+#define LPTIM_CFGR2_IN2SEL_Pos      (4U)

+#define LPTIM_CFGR2_IN2SEL_Msk      (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000030 */

+#define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< IN2SEL[5:4] bits (Remap selection) */

+#define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000010 */

+#define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000020 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    OCTOSPI                                 */

+/*                                                                            */

+/******************************************************************************/

+/*****************  Bit definition for OCTOSPI_CR register  *******************/

+#define OCTOSPI_CR_EN_Pos              (0U)

+#define OCTOSPI_CR_EN_Msk              (0x1UL << OCTOSPI_CR_EN_Pos)             /*!< 0x00000001 */

+#define OCTOSPI_CR_EN                  OCTOSPI_CR_EN_Msk                       /*!< Enable */

+#define OCTOSPI_CR_ABORT_Pos           (1U)

+#define OCTOSPI_CR_ABORT_Msk           (0x1UL << OCTOSPI_CR_ABORT_Pos)          /*!< 0x00000002 */

+#define OCTOSPI_CR_ABORT               OCTOSPI_CR_ABORT_Msk                    /*!< Abort request */

+#define OCTOSPI_CR_DMAEN_Pos           (2U)

+#define OCTOSPI_CR_DMAEN_Msk           (0x1UL << OCTOSPI_CR_DMAEN_Pos)          /*!< 0x00000004 */

+#define OCTOSPI_CR_DMAEN               OCTOSPI_CR_DMAEN_Msk                    /*!< DMA Enable */

+#define OCTOSPI_CR_TCEN_Pos            (3U)

+#define OCTOSPI_CR_TCEN_Msk            (0x1UL << OCTOSPI_CR_TCEN_Pos)           /*!< 0x00000008 */

+#define OCTOSPI_CR_TCEN                OCTOSPI_CR_TCEN_Msk                     /*!< Timeout Counter Enable */

+#define OCTOSPI_CR_DQM_Pos             (6U)

+#define OCTOSPI_CR_DQM_Msk             (0x1UL << OCTOSPI_CR_DQM_Pos)            /*!< 0x00000040 */

+#define OCTOSPI_CR_DQM                 OCTOSPI_CR_DQM_Msk                      /*!< Dual-Quad Mode */

+#define OCTOSPI_CR_FSEL_Pos            (7U)

+#define OCTOSPI_CR_FSEL_Msk            (0x1UL << OCTOSPI_CR_FSEL_Pos)           /*!< 0x00000080 */

+#define OCTOSPI_CR_FSEL                OCTOSPI_CR_FSEL_Msk                     /*!< Flash Select */

+#define OCTOSPI_CR_FTHRES_Pos          (8U)

+#define OCTOSPI_CR_FTHRES_Msk          (0x1FUL << OCTOSPI_CR_FTHRES_Pos)        /*!< 0x00001F00 */

+#define OCTOSPI_CR_FTHRES              OCTOSPI_CR_FTHRES_Msk                   /*!< FIFO Threshold Level */

+#define OCTOSPI_CR_TEIE_Pos            (16U)

+#define OCTOSPI_CR_TEIE_Msk            (0x1UL << OCTOSPI_CR_TEIE_Pos)           /*!< 0x00010000 */

+#define OCTOSPI_CR_TEIE                OCTOSPI_CR_TEIE_Msk                     /*!< Transfer Error Interrupt Enable */

+#define OCTOSPI_CR_TCIE_Pos            (17U)

+#define OCTOSPI_CR_TCIE_Msk            (0x1UL << OCTOSPI_CR_TCIE_Pos)           /*!< 0x00020000 */

+#define OCTOSPI_CR_TCIE                OCTOSPI_CR_TCIE_Msk                     /*!< Transfer Complete Interrupt Enable */

+#define OCTOSPI_CR_FTIE_Pos            (18U)

+#define OCTOSPI_CR_FTIE_Msk            (0x1UL << OCTOSPI_CR_FTIE_Pos)           /*!< 0x00040000 */

+#define OCTOSPI_CR_FTIE                OCTOSPI_CR_FTIE_Msk                     /*!< FIFO Threshold Interrupt Enable */

+#define OCTOSPI_CR_SMIE_Pos            (19U)

+#define OCTOSPI_CR_SMIE_Msk            (0x1UL << OCTOSPI_CR_SMIE_Pos)           /*!< 0x00080000 */

+#define OCTOSPI_CR_SMIE                OCTOSPI_CR_SMIE_Msk                     /*!< Status Match Interrupt Enable */

+#define OCTOSPI_CR_TOIE_Pos            (20U)

+#define OCTOSPI_CR_TOIE_Msk            (0x1UL << OCTOSPI_CR_TOIE_Pos)           /*!< 0x00100000 */

+#define OCTOSPI_CR_TOIE                OCTOSPI_CR_TOIE_Msk                     /*!< TimeOut Interrupt Enable */

+#define OCTOSPI_CR_APMS_Pos            (22U)

+#define OCTOSPI_CR_APMS_Msk            (0x1UL << OCTOSPI_CR_APMS_Pos)           /*!< 0x00400000 */

+#define OCTOSPI_CR_APMS                OCTOSPI_CR_APMS_Msk                     /*!< Automatic Poll Mode Stop */

+#define OCTOSPI_CR_PMM_Pos             (23U)

+#define OCTOSPI_CR_PMM_Msk             (0x1UL << OCTOSPI_CR_PMM_Pos)            /*!< 0x00800000 */

+#define OCTOSPI_CR_PMM                 OCTOSPI_CR_PMM_Msk                      /*!< Polling Match Mode */

+#define OCTOSPI_CR_FMODE_Pos           (28U)

+#define OCTOSPI_CR_FMODE_Msk           (0x3UL << OCTOSPI_CR_FMODE_Pos)          /*!< 0x30000000 */

+#define OCTOSPI_CR_FMODE               OCTOSPI_CR_FMODE_Msk                    /*!< Functional Mode */

+#define OCTOSPI_CR_FMODE_0             (0x1UL << OCTOSPI_CR_FMODE_Pos)          /*!< 0x10000000 */

+#define OCTOSPI_CR_FMODE_1             (0x2UL << OCTOSPI_CR_FMODE_Pos)          /*!< 0x20000000 */

+

+/****************  Bit definition for OCTOSPI_DCR1 register  ******************/

+#define OCTOSPI_DCR1_CKMODE_Pos        (0U)

+#define OCTOSPI_DCR1_CKMODE_Msk        (0x1UL << OCTOSPI_DCR1_CKMODE_Pos)       /*!< 0x00000001 */

+#define OCTOSPI_DCR1_CKMODE            OCTOSPI_DCR1_CKMODE_Msk                 /*!< Mode 0 / Mode 3 */

+#define OCTOSPI_DCR1_FRCK_Pos          (1U)

+#define OCTOSPI_DCR1_FRCK_Msk          (0x1UL << OCTOSPI_DCR1_FRCK_Pos)         /*!< 0x00000002 */

+#define OCTOSPI_DCR1_FRCK              OCTOSPI_DCR1_FRCK_Msk                   /*!< Free Running Clock */

+#define OCTOSPI_DCR1_DLYBYP_Pos        (3U)

+#define OCTOSPI_DCR1_DLYBYP_Msk        (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos)       /*!< 0x00000008 */

+#define OCTOSPI_DCR1_DLYBYP            OCTOSPI_DCR1_DLYBYP_Msk                 /*!< Delay Block */

+#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)

+#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */

+#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */

+#define OCTOSPI_DCR1_CSHT_Pos          (8U)

+#define OCTOSPI_DCR1_CSHT_Msk          (0x7UL << OCTOSPI_DCR1_CSHT_Pos)         /*!< 0x00000700 */

+#define OCTOSPI_DCR1_CSHT              OCTOSPI_DCR1_CSHT_Msk                   /*!< Chip Select High Time */

+#define OCTOSPI_DCR1_DEVSIZE_Pos       (16U)

+#define OCTOSPI_DCR1_DEVSIZE_Msk       (0x1FUL << OCTOSPI_DCR1_DEVSIZE_Pos)     /*!< 0x001F0000 */

+#define OCTOSPI_DCR1_DEVSIZE           OCTOSPI_DCR1_DEVSIZE_Msk                /*!< Device Size */

+#define OCTOSPI_DCR1_MTYP_Pos          (24U)

+#define OCTOSPI_DCR1_MTYP_Msk          (0x7UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x07000000 */

+#define OCTOSPI_DCR1_MTYP              OCTOSPI_DCR1_MTYP_Msk                   /*!< Memory Type */

+#define OCTOSPI_DCR1_MTYP_0            (0x1UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x01000000 */

+#define OCTOSPI_DCR1_MTYP_1            (0x2UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x02000000 */

+#define OCTOSPI_DCR1_MTYP_2            (0x4UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x04000000 */

+

+/****************  Bit definition for OCTOSPI_DCR2 register  ******************/

+#define OCTOSPI_DCR2_PRESCALER_Pos     (0U)

+#define OCTOSPI_DCR2_PRESCALER_Msk     (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos)   /*!< 0x000000FF */

+#define OCTOSPI_DCR2_PRESCALER         OCTOSPI_DCR2_PRESCALER_Msk              /*!< Clock prescaler */

+#define OCTOSPI_DCR2_WRAPSIZE_Pos      (16U)

+#define OCTOSPI_DCR2_WRAPSIZE_Msk      (0x7UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00070000 */

+#define OCTOSPI_DCR2_WRAPSIZE          OCTOSPI_DCR2_WRAPSIZE_Msk               /*!< Wrap Size */

+#define OCTOSPI_DCR2_WRAPSIZE_0        (0x1UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00010000 */

+#define OCTOSPI_DCR2_WRAPSIZE_1        (0x2UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00020000 */

+#define OCTOSPI_DCR2_WRAPSIZE_2        (0x4UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00040000 */

+

+/****************  Bit definition for OCTOSPI_DCR3 register  ******************/

+#define OCTOSPI_DCR3_MAXTRAN_Pos       (0U)

+#define OCTOSPI_DCR3_MAXTRAN_Msk       (0xFFUL << OCTOSPI_DCR3_MAXTRAN_Pos)     /*!< 0x000000FF */

+#define OCTOSPI_DCR3_MAXTRAN           OCTOSPI_DCR3_MAXTRAN_Msk                /*!< Maximum Transfer */

+#define OCTOSPI_DCR3_CSBOUND_Pos       (16U)

+#define OCTOSPI_DCR3_CSBOUND_Msk       (0x1FUL << OCTOSPI_DCR3_CSBOUND_Pos)     /*!< 0x001F0000 */

+#define OCTOSPI_DCR3_CSBOUND           OCTOSPI_DCR3_CSBOUND_Msk                /*!< CS Boundary */

+

+/****************  Bit definition for OCTOSPI_DCR4 register  ******************/

+#define OCTOSPI_DCR4_REFRESH_Pos       (0U)

+#define OCTOSPI_DCR4_REFRESH_Msk       (0xFFFFFFFFUL << OCTOSPI_DCR4_REFRESH_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_DCR4_REFRESH           OCTOSPI_DCR4_REFRESH_Msk                /*!< Refresh rate */

+

+/*****************  Bit definition for OCTOSPI_SR register  *******************/

+#define OCTOSPI_SR_TEF_Pos             (0U)

+#define OCTOSPI_SR_TEF_Msk             (0x1UL << OCTOSPI_SR_TEF_Pos)            /*!< 0x00000001 */

+#define OCTOSPI_SR_TEF                 OCTOSPI_SR_TEF_Msk                      /*!< Transfer Error Flag */

+#define OCTOSPI_SR_TCF_Pos             (1U)

+#define OCTOSPI_SR_TCF_Msk             (0x1UL << OCTOSPI_SR_TCF_Pos)            /*!< 0x00000002 */

+#define OCTOSPI_SR_TCF                 OCTOSPI_SR_TCF_Msk                      /*!< Transfer Complete Flag */

+#define OCTOSPI_SR_FTF_Pos             (2U)

+#define OCTOSPI_SR_FTF_Msk             (0x1UL << OCTOSPI_SR_FTF_Pos)            /*!< 0x00000004 */

+#define OCTOSPI_SR_FTF                 OCTOSPI_SR_FTF_Msk                      /*!< FIFO Threshold Flag */

+#define OCTOSPI_SR_SMF_Pos             (3U)

+#define OCTOSPI_SR_SMF_Msk             (0x1UL << OCTOSPI_SR_SMF_Pos)            /*!< 0x00000008 */

+#define OCTOSPI_SR_SMF                 OCTOSPI_SR_SMF_Msk                      /*!< Status Match Flag */

+#define OCTOSPI_SR_TOF_Pos             (4U)

+#define OCTOSPI_SR_TOF_Msk             (0x1UL << OCTOSPI_SR_TOF_Pos)            /*!< 0x00000010 */

+#define OCTOSPI_SR_TOF                 OCTOSPI_SR_TOF_Msk                      /*!< Timeout Flag */

+#define OCTOSPI_SR_BUSY_Pos            (5U)

+#define OCTOSPI_SR_BUSY_Msk            (0x1UL << OCTOSPI_SR_BUSY_Pos)           /*!< 0x00000020 */

+#define OCTOSPI_SR_BUSY                OCTOSPI_SR_BUSY_Msk                     /*!< Busy */

+#define OCTOSPI_SR_FLEVEL_Pos          (8U)

+#define OCTOSPI_SR_FLEVEL_Msk          (0x3FUL << OCTOSPI_SR_FLEVEL_Pos)        /*!< 0x00003F00 */

+#define OCTOSPI_SR_FLEVEL              OCTOSPI_SR_FLEVEL_Msk                   /*!< FIFO Level */

+

+/****************  Bit definition for OCTOSPI_FCR register  *******************/

+#define OCTOSPI_FCR_CTEF_Pos           (0U)

+#define OCTOSPI_FCR_CTEF_Msk           (0x1UL << OCTOSPI_FCR_CTEF_Pos)          /*!< 0x00000001 */

+#define OCTOSPI_FCR_CTEF               OCTOSPI_FCR_CTEF_Msk                    /*!< Clear Transfer Error Flag */

+#define OCTOSPI_FCR_CTCF_Pos           (1U)

+#define OCTOSPI_FCR_CTCF_Msk           (0x1UL << OCTOSPI_FCR_CTCF_Pos)          /*!< 0x00000002 */

+#define OCTOSPI_FCR_CTCF               OCTOSPI_FCR_CTCF_Msk                    /*!< Clear Transfer Complete Flag */

+#define OCTOSPI_FCR_CSMF_Pos           (3U)

+#define OCTOSPI_FCR_CSMF_Msk           (0x1UL << OCTOSPI_FCR_CSMF_Pos)          /*!< 0x00000008 */

+#define OCTOSPI_FCR_CSMF               OCTOSPI_FCR_CSMF_Msk                    /*!< Clear Status Match Flag */

+#define OCTOSPI_FCR_CTOF_Pos           (4U)

+#define OCTOSPI_FCR_CTOF_Msk           (0x1UL << OCTOSPI_FCR_CTOF_Pos)          /*!< 0x00000010 */

+#define OCTOSPI_FCR_CTOF               OCTOSPI_FCR_CTOF_Msk                    /*!< Clear Timeout Flag */

+

+/****************  Bit definition for OCTOSPI_DLR register  *******************/

+#define OCTOSPI_DLR_DL_Pos             (0U)

+#define OCTOSPI_DLR_DL_Msk             (0xFFFFFFFFUL << OCTOSPI_DLR_DL_Pos)     /*!< 0xFFFFFFFF */

+#define OCTOSPI_DLR_DL                 OCTOSPI_DLR_DL_Msk                      /*!< Data Length */

+

+/*****************  Bit definition for OCTOSPI_AR register  *******************/

+#define OCTOSPI_AR_ADDRESS_Pos         (0U)

+#define OCTOSPI_AR_ADDRESS_Msk         (0xFFFFFFFFUL << OCTOSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_AR_ADDRESS             OCTOSPI_AR_ADDRESS_Msk                  /*!< Address */

+

+/*****************  Bit definition for OCTOSPI_DR register  *******************/

+#define OCTOSPI_DR_DATA_Pos            (0U)

+#define OCTOSPI_DR_DATA_Msk            (0xFFFFFFFFUL << OCTOSPI_DR_DATA_Pos)    /*!< 0xFFFFFFFF */

+#define OCTOSPI_DR_DATA                OCTOSPI_DR_DATA_Msk                     /*!< Data */

+

+/***************  Bit definition for OCTOSPI_PSMKR register  ******************/

+#define OCTOSPI_PSMKR_MASK_Pos         (0U)

+#define OCTOSPI_PSMKR_MASK_Msk         (0xFFFFFFFFUL << OCTOSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_PSMKR_MASK             OCTOSPI_PSMKR_MASK_Msk                  /*!< Status mask */

+

+/***************  Bit definition for OCTOSPI_PSMAR register  ******************/

+#define OCTOSPI_PSMAR_MATCH_Pos        (0U)

+#define OCTOSPI_PSMAR_MATCH_Msk        (0xFFFFFFFFUL << OCTOSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_PSMAR_MATCH            OCTOSPI_PSMAR_MATCH_Msk                 /*!< Status match */

+

+/****************  Bit definition for OCTOSPI_PIR register  *******************/

+#define OCTOSPI_PIR_INTERVAL_Pos       (0U)

+#define OCTOSPI_PIR_INTERVAL_Msk       (0xFFFFUL << OCTOSPI_PIR_INTERVAL_Pos)   /*!< 0x0000FFFF */

+#define OCTOSPI_PIR_INTERVAL           OCTOSPI_PIR_INTERVAL_Msk                /*!< Polling Interval */

+

+/****************  Bit definition for OCTOSPI_CCR register  *******************/

+#define OCTOSPI_CCR_IMODE_Pos          (0U)

+#define OCTOSPI_CCR_IMODE_Msk          (0x7UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000007 */

+#define OCTOSPI_CCR_IMODE              OCTOSPI_CCR_IMODE_Msk                   /*!< Instruction Mode */

+#define OCTOSPI_CCR_IMODE_0            (0x1UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000001 */

+#define OCTOSPI_CCR_IMODE_1            (0x2UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000002 */

+#define OCTOSPI_CCR_IMODE_2            (0x4UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000004 */

+#define OCTOSPI_CCR_IDTR_Pos           (3U)

+#define OCTOSPI_CCR_IDTR_Msk           (0x1UL << OCTOSPI_CCR_IDTR_Pos)          /*!< 0x00000008 */

+#define OCTOSPI_CCR_IDTR               OCTOSPI_CCR_IDTR_Msk                    /*!< Instruction Double Transfer Rate */

+#define OCTOSPI_CCR_ISIZE_Pos          (4U)

+#define OCTOSPI_CCR_ISIZE_Msk          (0x3UL << OCTOSPI_CCR_ISIZE_Pos)         /*!< 0x00000030 */

+#define OCTOSPI_CCR_ISIZE              OCTOSPI_CCR_ISIZE_Msk                   /*!< Instruction Size */

+#define OCTOSPI_CCR_ISIZE_0            (0x1UL << OCTOSPI_CCR_ISIZE_Pos)         /*!< 0x00000010 */

+#define OCTOSPI_CCR_ISIZE_1            (0x2UL << OCTOSPI_CCR_ISIZE_Pos)         /*!< 0x00000020 */

+#define OCTOSPI_CCR_ADMODE_Pos         (8U)

+#define OCTOSPI_CCR_ADMODE_Msk         (0x7UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000700 */

+#define OCTOSPI_CCR_ADMODE             OCTOSPI_CCR_ADMODE_Msk                  /*!< Address Mode */

+#define OCTOSPI_CCR_ADMODE_0           (0x1UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000100 */

+#define OCTOSPI_CCR_ADMODE_1           (0x2UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000200 */

+#define OCTOSPI_CCR_ADMODE_2           (0x4UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000400 */

+#define OCTOSPI_CCR_ADDTR_Pos          (11U)

+#define OCTOSPI_CCR_ADDTR_Msk          (0x1UL << OCTOSPI_CCR_ADDTR_Pos)         /*!< 0x00000800 */

+#define OCTOSPI_CCR_ADDTR              OCTOSPI_CCR_ADDTR_Msk                   /*!< Address Double Transfer Rate */

+#define OCTOSPI_CCR_ADSIZE_Pos         (12U)

+#define OCTOSPI_CCR_ADSIZE_Msk         (0x3UL << OCTOSPI_CCR_ADSIZE_Pos)        /*!< 0x00003000 */

+#define OCTOSPI_CCR_ADSIZE             OCTOSPI_CCR_ADSIZE_Msk                  /*!< Address Size */

+#define OCTOSPI_CCR_ADSIZE_0           (0x1UL << OCTOSPI_CCR_ADSIZE_Pos)        /*!< 0x00001000 */

+#define OCTOSPI_CCR_ADSIZE_1           (0x2UL << OCTOSPI_CCR_ADSIZE_Pos)        /*!< 0x00002000 */

+#define OCTOSPI_CCR_ABMODE_Pos         (16U)

+#define OCTOSPI_CCR_ABMODE_Msk         (0x7UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00070000 */

+#define OCTOSPI_CCR_ABMODE             OCTOSPI_CCR_ABMODE_Msk                  /*!< Alternate Bytes Mode */

+#define OCTOSPI_CCR_ABMODE_0           (0x1UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00010000 */

+#define OCTOSPI_CCR_ABMODE_1           (0x2UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00020000 */

+#define OCTOSPI_CCR_ABMODE_2           (0x4UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00040000 */

+#define OCTOSPI_CCR_ABDTR_Pos          (19U)

+#define OCTOSPI_CCR_ABDTR_Msk          (0x1UL << OCTOSPI_CCR_ABDTR_Pos)         /*!< 0x00080000 */

+#define OCTOSPI_CCR_ABDTR              OCTOSPI_CCR_ABDTR_Msk                   /*!< Alternate Bytes Double Transfer Rate */

+#define OCTOSPI_CCR_ABSIZE_Pos         (20U)

+#define OCTOSPI_CCR_ABSIZE_Msk         (0x3UL << OCTOSPI_CCR_ABSIZE_Pos)        /*!< 0x00300000 */

+#define OCTOSPI_CCR_ABSIZE             OCTOSPI_CCR_ABSIZE_Msk                  /*!< Alternate Bytes Size */

+#define OCTOSPI_CCR_ABSIZE_0           (0x1UL << OCTOSPI_CCR_ABSIZE_Pos)        /*!< 0x00100000 */

+#define OCTOSPI_CCR_ABSIZE_1           (0x2UL << OCTOSPI_CCR_ABSIZE_Pos)        /*!< 0x00200000 */

+#define OCTOSPI_CCR_DMODE_Pos          (24U)

+#define OCTOSPI_CCR_DMODE_Msk          (0x7UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x07000000 */

+#define OCTOSPI_CCR_DMODE              OCTOSPI_CCR_DMODE_Msk                   /*!< Data Mode */

+#define OCTOSPI_CCR_DMODE_0            (0x1UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x01000000 */

+#define OCTOSPI_CCR_DMODE_1            (0x2UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x02000000 */

+#define OCTOSPI_CCR_DMODE_2            (0x4UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x04000000 */

+#define OCTOSPI_CCR_DDTR_Pos           (27U)

+#define OCTOSPI_CCR_DDTR_Msk           (0x1UL << OCTOSPI_CCR_DDTR_Pos)          /*!< 0x08000000 */

+#define OCTOSPI_CCR_DDTR               OCTOSPI_CCR_DDTR_Msk                    /*!< Data Double Transfer Rate */

+#define OCTOSPI_CCR_DQSE_Pos           (29U)

+#define OCTOSPI_CCR_DQSE_Msk           (0x1UL << OCTOSPI_CCR_DQSE_Pos)          /*!< 0x20000000 */

+#define OCTOSPI_CCR_DQSE               OCTOSPI_CCR_DQSE_Msk                    /*!< DQS Enable */

+#define OCTOSPI_CCR_SIOO_Pos           (31U)

+#define OCTOSPI_CCR_SIOO_Msk           (0x1UL << OCTOSPI_CCR_SIOO_Pos)          /*!< 0x80000000 */

+#define OCTOSPI_CCR_SIOO               OCTOSPI_CCR_SIOO_Msk                    /*!< Send Instruction Only Once Mode */

+

+/****************  Bit definition for OCTOSPI_TCR register  *******************/

+#define OCTOSPI_TCR_DCYC_Pos           (0U)

+#define OCTOSPI_TCR_DCYC_Msk           (0x1FUL << OCTOSPI_TCR_DCYC_Pos)         /*!< 0x0000001F */

+#define OCTOSPI_TCR_DCYC               OCTOSPI_TCR_DCYC_Msk                    /*!< Number of Dummy Cycles */

+#define OCTOSPI_TCR_DHQC_Pos           (28U)

+#define OCTOSPI_TCR_DHQC_Msk           (0x1UL << OCTOSPI_TCR_DHQC_Pos)          /*!< 0x10000000 */

+#define OCTOSPI_TCR_DHQC               OCTOSPI_TCR_DHQC_Msk                    /*!< Delay Hold Quarter Cycle */

+#define OCTOSPI_TCR_SSHIFT_Pos         (30U)

+#define OCTOSPI_TCR_SSHIFT_Msk         (0x1UL << OCTOSPI_TCR_SSHIFT_Pos)        /*!< 0x40000000 */

+#define OCTOSPI_TCR_SSHIFT             OCTOSPI_TCR_SSHIFT_Msk                  /*!< Sample Shift */

+

+/*****************  Bit definition for OCTOSPI_IR register  *******************/

+#define OCTOSPI_IR_INSTRUCTION_Pos     (0U)

+#define OCTOSPI_IR_INSTRUCTION_Msk     (0xFFFFFFFFUL << OCTOSPI_IR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_IR_INSTRUCTION         OCTOSPI_IR_INSTRUCTION_Msk              /*!< Instruction */

+

+/****************  Bit definition for OCTOSPI_ABR register  *******************/

+#define OCTOSPI_ABR_ALTERNATE_Pos      (0U)

+#define OCTOSPI_ABR_ALTERNATE_Msk      (0xFFFFFFFFUL << OCTOSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_ABR_ALTERNATE          OCTOSPI_ABR_ALTERNATE_Msk               /*!< Alternate Bytes */

+

+/****************  Bit definition for OCTOSPI_LPTR register  ******************/

+#define OCTOSPI_LPTR_TIMEOUT_Pos       (0U)

+#define OCTOSPI_LPTR_TIMEOUT_Msk       (0xFFFFUL << OCTOSPI_LPTR_TIMEOUT_Pos)   /*!< 0x0000FFFF */

+#define OCTOSPI_LPTR_TIMEOUT           OCTOSPI_LPTR_TIMEOUT_Msk                /*!< Timeout period */

+

+/****************  Bit definition for OCTOSPI_WPCCR register  *******************/

+#define OCTOSPI_WPCCR_IMODE_Pos        (0U)

+#define OCTOSPI_WPCCR_IMODE_Msk        (0x7UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000007 */

+#define OCTOSPI_WPCCR_IMODE            OCTOSPI_WPCCR_IMODE_Msk                 /*!< Instruction Mode */

+#define OCTOSPI_WPCCR_IMODE_0          (0x1UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000001 */

+#define OCTOSPI_WPCCR_IMODE_1          (0x2UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000002 */

+#define OCTOSPI_WPCCR_IMODE_2          (0x4UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000004 */

+#define OCTOSPI_WPCCR_IDTR_Pos         (3U)

+#define OCTOSPI_WPCCR_IDTR_Msk         (0x1UL << OCTOSPI_WPCCR_IDTR_Pos)        /*!< 0x00000008 */

+#define OCTOSPI_WPCCR_IDTR             OCTOSPI_WPCCR_IDTR_Msk                  /*!< Instruction Double Transfer Rate */

+#define OCTOSPI_WPCCR_ISIZE_Pos        (4U)

+#define OCTOSPI_WPCCR_ISIZE_Msk        (0x3UL << OCTOSPI_WPCCR_ISIZE_Pos)       /*!< 0x00000030 */

+#define OCTOSPI_WPCCR_ISIZE            OCTOSPI_WPCCR_ISIZE_Msk                 /*!< Instruction Size */

+#define OCTOSPI_WPCCR_ISIZE_0          (0x1UL << OCTOSPI_WPCCR_ISIZE_Pos)       /*!< 0x00000010 */

+#define OCTOSPI_WPCCR_ISIZE_1          (0x2UL << OCTOSPI_WPCCR_ISIZE_Pos)       /*!< 0x00000020 */

+#define OCTOSPI_WPCCR_ADMODE_Pos       (8U)

+#define OCTOSPI_WPCCR_ADMODE_Msk       (0x7UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000700 */

+#define OCTOSPI_WPCCR_ADMODE           OCTOSPI_WPCCR_ADMODE_Msk                /*!< Address Mode */

+#define OCTOSPI_WPCCR_ADMODE_0         (0x1UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000100 */

+#define OCTOSPI_WPCCR_ADMODE_1         (0x2UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000200 */

+#define OCTOSPI_WPCCR_ADMODE_2         (0x4UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000400 */

+#define OCTOSPI_WPCCR_ADDTR_Pos        (11U)

+#define OCTOSPI_WPCCR_ADDTR_Msk        (0x1UL << OCTOSPI_WPCCR_ADDTR_Pos)       /*!< 0x00000800 */

+#define OCTOSPI_WPCCR_ADDTR            OCTOSPI_WPCCR_ADDTR_Msk                 /*!< Address Double Transfer Rate */

+#define OCTOSPI_WPCCR_ADSIZE_Pos       (12U)

+#define OCTOSPI_WPCCR_ADSIZE_Msk       (0x3UL << OCTOSPI_WPCCR_ADSIZE_Pos)      /*!< 0x00003000 */

+#define OCTOSPI_WPCCR_ADSIZE           OCTOSPI_WPCCR_ADSIZE_Msk                /*!< Address Size */

+#define OCTOSPI_WPCCR_ADSIZE_0         (0x1UL << OCTOSPI_WPCCR_ADSIZE_Pos)      /*!< 0x00001000 */

+#define OCTOSPI_WPCCR_ADSIZE_1         (0x2UL << OCTOSPI_WPCCR_ADSIZE_Pos)      /*!< 0x00002000 */

+#define OCTOSPI_WPCCR_ABMODE_Pos       (16U)

+#define OCTOSPI_WPCCR_ABMODE_Msk       (0x7UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00070000 */

+#define OCTOSPI_WPCCR_ABMODE           OCTOSPI_WPCCR_ABMODE_Msk                /*!< Alternate Bytes Mode */

+#define OCTOSPI_WPCCR_ABMODE_0         (0x1UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00010000 */

+#define OCTOSPI_WPCCR_ABMODE_1         (0x2UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00020000 */

+#define OCTOSPI_WPCCR_ABMODE_2         (0x4UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00040000 */

+#define OCTOSPI_WPCCR_ABDTR_Pos        (19U)

+#define OCTOSPI_WPCCR_ABDTR_Msk        (0x1UL << OCTOSPI_WPCCR_ABDTR_Pos)       /*!< 0x00080000 */

+#define OCTOSPI_WPCCR_ABDTR            OCTOSPI_WPCCR_ABDTR_Msk                 /*!< Alternate Bytes Double Transfer Rate */

+#define OCTOSPI_WPCCR_ABSIZE_Pos       (20U)

+#define OCTOSPI_WPCCR_ABSIZE_Msk       (0x3UL << OCTOSPI_WPCCR_ABSIZE_Pos)      /*!< 0x00300000 */

+#define OCTOSPI_WPCCR_ABSIZE           OCTOSPI_WPCCR_ABSIZE_Msk                /*!< Alternate Bytes Size */

+#define OCTOSPI_WPCCR_ABSIZE_0         (0x1UL << OCTOSPI_WPCCR_ABSIZE_Pos)      /*!< 0x00100000 */

+#define OCTOSPI_WPCCR_ABSIZE_1         (0x2UL << OCTOSPI_WPCCR_ABSIZE_Pos)      /*!< 0x00200000 */

+#define OCTOSPI_WPCCR_DMODE_Pos        (24U)

+#define OCTOSPI_WPCCR_DMODE_Msk        (0x7UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x07000000 */

+#define OCTOSPI_WPCCR_DMODE            OCTOSPI_WPCCR_DMODE_Msk                 /*!< Data Mode */

+#define OCTOSPI_WPCCR_DMODE_0          (0x1UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x01000000 */

+#define OCTOSPI_WPCCR_DMODE_1          (0x2UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x02000000 */

+#define OCTOSPI_WPCCR_DMODE_2          (0x4UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x04000000 */

+#define OCTOSPI_WPCCR_DDTR_Pos         (27U)

+#define OCTOSPI_WPCCR_DDTR_Msk         (0x1UL << OCTOSPI_WPCCR_DDTR_Pos)        /*!< 0x08000000 */

+#define OCTOSPI_WPCCR_DDTR             OCTOSPI_WPCCR_DDTR_Msk                  /*!< Data Double Transfer Rate */

+#define OCTOSPI_WPCCR_DQSE_Pos         (29U)

+#define OCTOSPI_WPCCR_DQSE_Msk         (0x1UL << OCTOSPI_WPCCR_DQSE_Pos)        /*!< 0x20000000 */

+#define OCTOSPI_WPCCR_DQSE             OCTOSPI_WPCCR_DQSE_Msk                  /*!< DQS Enable */

+#define OCTOSPI_WPCCR_SIOO_Pos         (31U)

+#define OCTOSPI_WPCCR_SIOO_Msk         (0x1UL << OCTOSPI_WPCCR_SIOO_Pos)        /*!< 0x80000000 */

+#define OCTOSPI_WPCCR_SIOO             OCTOSPI_WPCCR_SIOO_Msk                  /*!< Send Instruction Only Once Mode */

+

+/****************  Bit definition for OCTOSPI_WPTCR register  *******************/

+#define OCTOSPI_WPTCR_DCYC_Pos         (0U)

+#define OCTOSPI_WPTCR_DCYC_Msk         (0x1FUL << OCTOSPI_WPTCR_DCYC_Pos)       /*!< 0x0000001F */

+#define OCTOSPI_WPTCR_DCYC             OCTOSPI_WPTCR_DCYC_Msk                  /*!< Number of Dummy Cycles */

+#define OCTOSPI_WPTCR_DHQC_Pos         (28U)

+#define OCTOSPI_WPTCR_DHQC_Msk         (0x1UL << OCTOSPI_WPTCR_DHQC_Pos)        /*!< 0x10000000 */

+#define OCTOSPI_WPTCR_DHQC             OCTOSPI_WPTCR_DHQC_Msk                  /*!< Delay Hold Quarter Cycle */

+#define OCTOSPI_WPTCR_SSHIFT_Pos       (30U)

+#define OCTOSPI_WPTCR_SSHIFT_Msk       (0x1UL << OCTOSPI_WPTCR_SSHIFT_Pos)      /*!< 0x40000000 */

+#define OCTOSPI_WPTCR_SSHIFT           OCTOSPI_WPTCR_SSHIFT_Msk                /*!< Sample Shift */

+

+/*****************  Bit definition for OCTOSPI_WPIR register  *******************/

+#define OCTOSPI_WPIR_INSTRUCTION_Pos   (0U)

+#define OCTOSPI_WPIR_INSTRUCTION_Msk   (0xFFFFFFFFUL << OCTOSPI_WPIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_WPIR_INSTRUCTION       OCTOSPI_WPIR_INSTRUCTION_Msk            /*!< Instruction */

+

+/****************  Bit definition for OCTOSPI_WPABR register  *******************/

+#define OCTOSPI_WPABR_ALTERNATE_Pos    (0U)

+#define OCTOSPI_WPABR_ALTERNATE_Msk    (0xFFFFFFFFUL << OCTOSPI_WPABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_WPABR_ALTERNATE        OCTOSPI_WPABR_ALTERNATE_Msk             /*!< Alternate Bytes */

+

+/****************  Bit definition for OCTOSPI_WCCR register  ******************/

+#define OCTOSPI_WCCR_IMODE_Pos         (0U)

+#define OCTOSPI_WCCR_IMODE_Msk         (0x7UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000007 */

+#define OCTOSPI_WCCR_IMODE             OCTOSPI_WCCR_IMODE_Msk                  /*!< Instruction Mode */

+#define OCTOSPI_WCCR_IMODE_0           (0x1UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000001 */

+#define OCTOSPI_WCCR_IMODE_1           (0x2UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000002 */

+#define OCTOSPI_WCCR_IMODE_2           (0x4UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000004 */

+#define OCTOSPI_WCCR_IDTR_Pos          (3U)

+#define OCTOSPI_WCCR_IDTR_Msk          (0x1UL << OCTOSPI_WCCR_IDTR_Pos)         /*!< 0x00000008 */

+#define OCTOSPI_WCCR_IDTR              OCTOSPI_WCCR_IDTR_Msk                   /*!< Instruction Double Transfer Rate */

+#define OCTOSPI_WCCR_ISIZE_Pos         (4U)

+#define OCTOSPI_WCCR_ISIZE_Msk         (0x3UL << OCTOSPI_WCCR_ISIZE_Pos)        /*!< 0x00000030 */

+#define OCTOSPI_WCCR_ISIZE             OCTOSPI_WCCR_ISIZE_Msk                  /*!< Instruction Size */

+#define OCTOSPI_WCCR_ISIZE_0           (0x1UL << OCTOSPI_WCCR_ISIZE_Pos)        /*!< 0x00000010 */

+#define OCTOSPI_WCCR_ISIZE_1           (0x2UL << OCTOSPI_WCCR_ISIZE_Pos)        /*!< 0x00000020 */

+#define OCTOSPI_WCCR_ADMODE_Pos        (8U)

+#define OCTOSPI_WCCR_ADMODE_Msk        (0x7UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000700 */

+#define OCTOSPI_WCCR_ADMODE            OCTOSPI_WCCR_ADMODE_Msk                 /*!< Address Mode */

+#define OCTOSPI_WCCR_ADMODE_0          (0x1UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000100 */

+#define OCTOSPI_WCCR_ADMODE_1          (0x2UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000200 */

+#define OCTOSPI_WCCR_ADMODE_2          (0x4UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000400 */

+#define OCTOSPI_WCCR_ADDTR_Pos         (11U)

+#define OCTOSPI_WCCR_ADDTR_Msk         (0x1UL << OCTOSPI_WCCR_ADDTR_Pos)        /*!< 0x00000800 */

+#define OCTOSPI_WCCR_ADDTR             OCTOSPI_WCCR_ADDTR_Msk                  /*!< Address Double Transfer Rate */

+#define OCTOSPI_WCCR_ADSIZE_Pos        (12U)

+#define OCTOSPI_WCCR_ADSIZE_Msk        (0x3UL << OCTOSPI_WCCR_ADSIZE_Pos)       /*!< 0x00003000 */

+#define OCTOSPI_WCCR_ADSIZE            OCTOSPI_WCCR_ADSIZE_Msk                 /*!< Address Size */

+#define OCTOSPI_WCCR_ADSIZE_0          (0x1UL << OCTOSPI_WCCR_ADSIZE_Pos)       /*!< 0x00001000 */

+#define OCTOSPI_WCCR_ADSIZE_1          (0x2UL << OCTOSPI_WCCR_ADSIZE_Pos)       /*!< 0x00002000 */

+#define OCTOSPI_WCCR_ABMODE_Pos        (16U)

+#define OCTOSPI_WCCR_ABMODE_Msk        (0x7UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00070000 */

+#define OCTOSPI_WCCR_ABMODE            OCTOSPI_WCCR_ABMODE_Msk                 /*!< Alternate Bytes Mode */

+#define OCTOSPI_WCCR_ABMODE_0          (0x1UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00010000 */

+#define OCTOSPI_WCCR_ABMODE_1          (0x2UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00020000 */

+#define OCTOSPI_WCCR_ABMODE_2          (0x4UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00040000 */

+#define OCTOSPI_WCCR_ABDTR_Pos         (19U)

+#define OCTOSPI_WCCR_ABDTR_Msk         (0x1UL << OCTOSPI_WCCR_ABDTR_Pos)        /*!< 0x00080000 */

+#define OCTOSPI_WCCR_ABDTR             OCTOSPI_WCCR_ABDTR_Msk                  /*!< Alternate Bytes Double Transfer Rate */

+#define OCTOSPI_WCCR_ABSIZE_Pos        (20U)

+#define OCTOSPI_WCCR_ABSIZE_Msk        (0x3UL << OCTOSPI_WCCR_ABSIZE_Pos)       /*!< 0x00300000 */

+#define OCTOSPI_WCCR_ABSIZE            OCTOSPI_WCCR_ABSIZE_Msk                 /*!< Alternate Bytes Size */

+#define OCTOSPI_WCCR_ABSIZE_0          (0x1UL << OCTOSPI_WCCR_ABSIZE_Pos)       /*!< 0x00100000 */

+#define OCTOSPI_WCCR_ABSIZE_1          (0x2UL << OCTOSPI_WCCR_ABSIZE_Pos)       /*!< 0x00200000 */

+#define OCTOSPI_WCCR_DMODE_Pos         (24U)

+#define OCTOSPI_WCCR_DMODE_Msk         (0x7UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x07000000 */

+#define OCTOSPI_WCCR_DMODE             OCTOSPI_WCCR_DMODE_Msk                  /*!< Data Mode */

+#define OCTOSPI_WCCR_DMODE_0           (0x1UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x01000000 */

+#define OCTOSPI_WCCR_DMODE_1           (0x2UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x02000000 */

+#define OCTOSPI_WCCR_DMODE_2           (0x4UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x04000000 */

+#define OCTOSPI_WCCR_DDTR_Pos          (27U)

+#define OCTOSPI_WCCR_DDTR_Msk          (0x1UL << OCTOSPI_WCCR_DDTR_Pos)         /*!< 0x08000000 */

+#define OCTOSPI_WCCR_DDTR              OCTOSPI_WCCR_DDTR_Msk                   /*!< Data Double Transfer Rate */

+#define OCTOSPI_WCCR_DQSE_Pos          (29U)

+#define OCTOSPI_WCCR_DQSE_Msk          (0x1UL << OCTOSPI_WCCR_DQSE_Pos)         /*!< 0x20000000 */

+#define OCTOSPI_WCCR_DQSE              OCTOSPI_WCCR_DQSE_Msk                   /*!< DQS Enable */

+#define OCTOSPI_WCCR_SIOO_Pos          (31U)

+#define OCTOSPI_WCCR_SIOO_Msk          (0x1UL << OCTOSPI_WCCR_SIOO_Pos)         /*!< 0x80000000 */

+#define OCTOSPI_WCCR_SIOO              OCTOSPI_WCCR_SIOO_Msk                   /*!< Send Instruction Only Once Mode */

+

+/****************  Bit definition for OCTOSPI_WTCR register  ******************/

+#define OCTOSPI_WTCR_DCYC_Pos          (0U)

+#define OCTOSPI_WTCR_DCYC_Msk          (0x1FUL << OCTOSPI_WTCR_DCYC_Pos)        /*!< 0x0000001F */

+#define OCTOSPI_WTCR_DCYC              OCTOSPI_WTCR_DCYC_Msk                   /*!< Number of Dummy Cycles */

+

+/****************  Bit definition for OCTOSPI_WIR register  *******************/

+#define OCTOSPI_WIR_INSTRUCTION_Pos    (0U)

+#define OCTOSPI_WIR_INSTRUCTION_Msk    (0xFFFFFFFFUL << OCTOSPI_WIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_WIR_INSTRUCTION        OCTOSPI_WIR_INSTRUCTION_Msk             /*!< Instruction */

+

+/****************  Bit definition for OCTOSPI_WABR register  ******************/

+#define OCTOSPI_WABR_ALTERNATE_Pos     (0U)

+#define OCTOSPI_WABR_ALTERNATE_Msk     (0xFFFFFFFFUL << OCTOSPI_WABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_WABR_ALTERNATE         OCTOSPI_WABR_ALTERNATE_Msk              /*!< Alternate Bytes */

+

+/****************  Bit definition for OCTOSPI_HLCR register  ******************/

+#define OCTOSPI_HLCR_LM_Pos            (0U)

+#define OCTOSPI_HLCR_LM_Msk            (0x1UL << OCTOSPI_HLCR_LM_Pos)           /*!< 0x00000001 */

+#define OCTOSPI_HLCR_LM                OCTOSPI_HLCR_LM_Msk                     /*!< Latency Mode */

+#define OCTOSPI_HLCR_WZL_Pos           (1U)

+#define OCTOSPI_HLCR_WZL_Msk           (0x1UL << OCTOSPI_HLCR_WZL_Pos)          /*!< 0x00000002 */

+#define OCTOSPI_HLCR_WZL               OCTOSPI_HLCR_WZL_Msk                    /*!< Write Zero Latency */

+#define OCTOSPI_HLCR_TACC_Pos          (8U)

+#define OCTOSPI_HLCR_TACC_Msk          (0xFFUL << OCTOSPI_HLCR_TACC_Pos)        /*!< 0x0000FF00 */

+#define OCTOSPI_HLCR_TACC              OCTOSPI_HLCR_TACC_Msk                   /*!< Access Time */

+#define OCTOSPI_HLCR_TRWR_Pos          (16U)

+#define OCTOSPI_HLCR_TRWR_Msk          (0xFFUL << OCTOSPI_HLCR_TRWR_Pos)        /*!< 0x00FF0000 */

+#define OCTOSPI_HLCR_TRWR              OCTOSPI_HLCR_TRWR_Msk                   /*!< Read Write Recovery Time */

+

+/****************  Bit definition for OCTOSPI_VER register  *******************/

+#define OCTOSPI_VER_VER_Pos            (0U)

+#define OCTOSPI_VER_VER_Msk            (0xFFUL << OCTOSPI_VER_VER_Pos)          /*!< 0x000000FF */

+#define OCTOSPI_VER_VER                OCTOSPI_VER_VER_Msk                     /*!< Version */

+

+/*****************  Bit definition for OCTOSPI_ID register  *******************/

+#define OCTOSPI_ID_ID_Pos              (0U)

+#define OCTOSPI_ID_ID_Msk              (0xFFFFFFFFUL << OCTOSPI_ID_ID_Pos)      /*!< 0xFFFFFFFF */

+#define OCTOSPI_ID_ID                  OCTOSPI_ID_ID_Msk                       /*!< Identification */

+

+/****************  Bit definition for OCTOSPI_MID register  *******************/

+#define OCTOSPI_MID_MID_Pos            (0U)

+#define OCTOSPI_MID_MID_Msk            (0xFFFFFFFFUL << OCTOSPI_MID_MID_Pos)    /*!< 0xFFFFFFFF */

+#define OCTOSPI_MID_MID                OCTOSPI_MID_MID_Msk                     /*!< Magic ID */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                  OCTOSPIM                                  */

+/*                                                                            */

+/******************************************************************************/

+

+/***************  Bit definition for OCTOSPIM_CR register  ********************/

+#define OCTOSPIM_CR_MUXEN_Pos          (0U)

+#define OCTOSPIM_CR_MUXEN_Msk          (0x1UL << OCTOSPIM_CR_MUXEN_Pos)        /*!< 0x00000001 */

+#define OCTOSPIM_CR_MUXEN              OCTOSPIM_CR_MUXEN_Msk                   /*!< Multiplexed mode enable */

+#define OCTOSPIM_CR_REQ2ACK_TIME_Pos   (16U)

+#define OCTOSPIM_CR_REQ2ACK_TIME_Msk   (0xFFUL << OCTOSPIM_CR_REQ2ACK_TIME_Pos)/*!< 0x00FF0000 */

+#define OCTOSPIM_CR_REQ2ACK_TIME       OCTOSPIM_CR_REQ2ACK_TIME_Msk            /*!< REQ to ACK time */

+

+/***************  Bit definition for OCTOSPIM_PCR register  *******************/

+#define OCTOSPIM_PCR_CLKEN_Pos         (0U)

+#define OCTOSPIM_PCR_CLKEN_Msk         (0x1UL << OCTOSPIM_PCR_CLKEN_Pos)        /*!< 0x00000001 */

+#define OCTOSPIM_PCR_CLKEN             OCTOSPIM_PCR_CLKEN_Msk                   /*!< CLK/CLKn Enable for Port n */

+#define OCTOSPIM_PCR_CLKSRC_Pos        (1U)

+#define OCTOSPIM_PCR_CLKSRC_Msk        (0x1UL << OCTOSPIM_PCR_CLKSRC_Pos)       /*!< 0x00000002 */

+#define OCTOSPIM_PCR_CLKSRC            OCTOSPIM_PCR_CLKSRC_Msk                  /*!< CLK/CLKn Source for Port n */

+#define OCTOSPIM_PCR_DQSEN_Pos         (4U)

+#define OCTOSPIM_PCR_DQSEN_Msk         (0x1UL << OCTOSPIM_PCR_DQSEN_Pos)        /*!< 0x00000010 */

+#define OCTOSPIM_PCR_DQSEN             OCTOSPIM_PCR_DQSEN_Msk                   /*!< DQS Enable for Port n */

+#define OCTOSPIM_PCR_DQSSRC_Pos        (5U)

+#define OCTOSPIM_PCR_DQSSRC_Msk        (0x1UL << OCTOSPIM_PCR_DQSSRC_Pos)       /*!< 0x00000020 */

+#define OCTOSPIM_PCR_DQSSRC            OCTOSPIM_PCR_DQSSRC_Msk                  /*!< DQS Source for Port n */

+#define OCTOSPIM_PCR_NCSEN_Pos         (8U)

+#define OCTOSPIM_PCR_NCSEN_Msk         (0x1UL << OCTOSPIM_PCR_NCSEN_Pos)        /*!< 0x00000100 */

+#define OCTOSPIM_PCR_NCSEN             OCTOSPIM_PCR_NCSEN_Msk                   /*!< nCS Enable for Port n */

+#define OCTOSPIM_PCR_NCSSRC_Pos        (9U)

+#define OCTOSPIM_PCR_NCSSRC_Msk        (0x1UL << OCTOSPIM_PCR_NCSSRC_Pos)       /*!< 0x00000200 */

+#define OCTOSPIM_PCR_NCSSRC            OCTOSPIM_PCR_NCSSRC_Msk                  /*!< nCS Source for Port n */

+#define OCTOSPIM_PCR_IOLEN_Pos         (16U)

+#define OCTOSPIM_PCR_IOLEN_Msk         (0x1UL << OCTOSPIM_PCR_IOLEN_Pos)        /*!< 0x00010000 */

+#define OCTOSPIM_PCR_IOLEN             OCTOSPIM_PCR_IOLEN_Msk                   /*!< IO[3:0] Enable for Port n */

+#define OCTOSPIM_PCR_IOLSRC_Pos        (17U)

+#define OCTOSPIM_PCR_IOLSRC_Msk        (0x3UL << OCTOSPIM_PCR_IOLSRC_Pos)       /*!< 0x00060000 */

+#define OCTOSPIM_PCR_IOLSRC            OCTOSPIM_PCR_IOLSRC_Msk                  /*!< IO[3:0] Source for Port n */

+#define OCTOSPIM_PCR_IOLSRC_0          (0x1UL << OCTOSPIM_PCR_IOLSRC_Pos)       /*!< 0x00020000 */

+#define OCTOSPIM_PCR_IOLSRC_1          (0x2UL << OCTOSPIM_PCR_IOLSRC_Pos)       /*!< 0x00040000 */

+#define OCTOSPIM_PCR_IOHEN_Pos         (24U)

+#define OCTOSPIM_PCR_IOHEN_Msk         (0x1UL << OCTOSPIM_PCR_IOHEN_Pos)        /*!< 0x01000000 */

+#define OCTOSPIM_PCR_IOHEN             OCTOSPIM_PCR_IOHEN_Msk                   /*!< IO[7:4] Enable for Port n */

+#define OCTOSPIM_PCR_IOHSRC_Pos        (25U)

+#define OCTOSPIM_PCR_IOHSRC_Msk        (0x3UL << OCTOSPIM_PCR_IOHSRC_Pos)       /*!< 0x06000000 */

+#define OCTOSPIM_PCR_IOHSRC            OCTOSPIM_PCR_IOHSRC_Msk                  /*!< IO[7:4] Source for Port n */

+#define OCTOSPIM_PCR_IOHSRC_0          (0x1UL << OCTOSPIM_PCR_IOHSRC_Pos)       /*!< 0x02000000 */

+#define OCTOSPIM_PCR_IOHSRC_1          (0x2UL << OCTOSPIM_PCR_IOHSRC_Pos)       /*!< 0x04000000 */

+/******************************************************************************/

+/*                                                                            */

+/*                      Analog Comparators (COMP)                             */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for COMP_SR register  ********************/

+#define COMP_SR_C1VAL_Pos            (0U)

+#define COMP_SR_C1VAL_Msk            (0x1UL << COMP_SR_C1VAL_Pos)              /*!< 0x00000001 */

+#define COMP_SR_C1VAL                COMP_SR_C1VAL_Msk

+#define COMP_SR_C2VAL_Pos            (1U)

+#define COMP_SR_C2VAL_Msk            (0x1UL << COMP_SR_C2VAL_Pos)              /*!< 0x00000002 */

+#define COMP_SR_C2VAL                COMP_SR_C2VAL_Msk

+#define COMP_SR_C1IF_Pos             (16U)

+#define COMP_SR_C1IF_Msk             (0x1UL << COMP_SR_C1IF_Pos)               /*!< 0x00010000 */

+#define COMP_SR_C1IF                 COMP_SR_C1IF_Msk

+#define COMP_SR_C2IF_Pos             (17U)

+#define COMP_SR_C2IF_Msk             (0x1UL << COMP_SR_C2IF_Pos)               /*!< 0x00020000 */

+#define COMP_SR_C2IF                 COMP_SR_C2IF_Msk

+/*******************  Bit definition for COMP_ICFR register  ********************/

+#define COMP_ICFR_C1IF_Pos           (16U)

+#define COMP_ICFR_C1IF_Msk           (0x1UL << COMP_ICFR_C1IF_Pos)             /*!< 0x00010000 */

+#define COMP_ICFR_C1IF               COMP_ICFR_C1IF_Msk

+#define COMP_ICFR_C2IF_Pos           (17U)

+#define COMP_ICFR_C2IF_Msk           (0x1UL << COMP_ICFR_C2IF_Pos)             /*!< 0x00020000 */

+#define COMP_ICFR_C2IF               COMP_ICFR_C2IF_Msk

+/*******************  Bit definition for COMP_OR register  ********************/

+#define COMP_OR_AFOPA6_Pos           (0U)

+#define COMP_OR_AFOPA6_Msk           (0x1UL << COMP_OR_AFOPA6_Pos)             /*!< 0x00000001 */

+#define COMP_OR_AFOPA6               COMP_OR_AFOPA6_Msk

+#define COMP_OR_AFOPA8_Pos           (1U)

+#define COMP_OR_AFOPA8_Msk           (0x1UL << COMP_OR_AFOPA8_Pos)             /*!< 0x00000002 */

+#define COMP_OR_AFOPA8               COMP_OR_AFOPA8_Msk

+#define COMP_OR_AFOPB12_Pos          (2U)

+#define COMP_OR_AFOPB12_Msk          (0x1UL << COMP_OR_AFOPB12_Pos)            /*!< 0x00000004 */

+#define COMP_OR_AFOPB12              COMP_OR_AFOPB12_Msk

+#define COMP_OR_AFOPE6_Pos           (3U)

+#define COMP_OR_AFOPE6_Msk           (0x1UL << COMP_OR_AFOPE6_Pos)             /*!< 0x00000008 */

+#define COMP_OR_AFOPE6               COMP_OR_AFOPE6_Msk

+#define COMP_OR_AFOPE15_Pos          (4U)

+#define COMP_OR_AFOPE15_Msk          (0x1UL << COMP_OR_AFOPE15_Pos)            /*!< 0x00000010 */

+#define COMP_OR_AFOPE15              COMP_OR_AFOPE15_Msk

+#define COMP_OR_AFOPG2_Pos           (5U)

+#define COMP_OR_AFOPG2_Msk           (0x1UL << COMP_OR_AFOPG2_Pos)             /*!< 0x00000020 */

+#define COMP_OR_AFOPG2               COMP_OR_AFOPG2_Msk

+#define COMP_OR_AFOPG3_Pos           (6U)

+#define COMP_OR_AFOPG3_Msk           (0x1UL << COMP_OR_AFOPG3_Pos)             /*!< 0x00000040 */

+#define COMP_OR_AFOPG3               COMP_OR_AFOPG3_Msk

+#define COMP_OR_AFOPG4_Pos           (7U)

+#define COMP_OR_AFOPG4_Msk           (0x1UL << COMP_OR_AFOPG4_Pos)             /*!< 0x00000080 */

+#define COMP_OR_AFOPG4               COMP_OR_AFOPG4_Msk

+#define COMP_OR_AFOPI1_Pos           (8U)

+#define COMP_OR_AFOPI1_Msk           (0x1UL << COMP_OR_AFOPI1_Pos)             /*!< 0x00000100 */

+#define COMP_OR_AFOPI1               COMP_OR_AFOPI1_Msk

+#define COMP_OR_AFOPI4_Pos           (9U)

+#define COMP_OR_AFOPI4_Msk           (0x1UL << COMP_OR_AFOPI4_Pos)             /*!< 0x00000200 */

+#define COMP_OR_AFOPI4               COMP_OR_AFOPI4_Msk

+#define COMP_OR_AFOPK2_Pos           (10U)

+#define COMP_OR_AFOPK2_Msk           (0x1UL << COMP_OR_AFOPK2_Pos)             /*!< 0x00000400 */

+#define COMP_OR_AFOPK2               COMP_OR_AFOPK2_Msk

+

+/*!< ******************  Bit definition for COMP_CFGRx register  ********************/

+#define COMP_CFGRx_EN_Pos            (0U)

+#define COMP_CFGRx_EN_Msk            (0x1UL << COMP_CFGRx_EN_Pos)              /*!< 0x00000001 */

+#define COMP_CFGRx_EN                COMP_CFGRx_EN_Msk                         /*!< COMPx enable bit                     */

+#define COMP_CFGRx_BRGEN_Pos         (1U)

+#define COMP_CFGRx_BRGEN_Msk         (0x1UL << COMP_CFGRx_BRGEN_Pos)           /*!< 0x00000002 */

+#define COMP_CFGRx_BRGEN             COMP_CFGRx_BRGEN_Msk                      /*!< COMPx Scaler bridge enable           */

+#define COMP_CFGRx_SCALEN_Pos        (2U)

+#define COMP_CFGRx_SCALEN_Msk        (0x1UL << COMP_CFGRx_SCALEN_Pos)          /*!< 0x00000004 */

+#define COMP_CFGRx_SCALEN            COMP_CFGRx_SCALEN_Msk                     /*!< COMPx Voltage scaler enable bit      */

+#define COMP_CFGRx_POLARITY_Pos      (3U)

+#define COMP_CFGRx_POLARITY_Msk      (0x1UL << COMP_CFGRx_POLARITY_Pos)        /*!< 0x00000008 */

+#define COMP_CFGRx_POLARITY          COMP_CFGRx_POLARITY_Msk                   /*!< COMPx  polarity selection bit        */

+#define COMP_CFGRx_WINMODE_Pos       (4U)

+#define COMP_CFGRx_WINMODE_Msk       (0x1UL << COMP_CFGRx_WINMODE_Pos)         /*!< 0x00000010 */

+#define COMP_CFGRx_WINMODE           COMP_CFGRx_WINMODE_Msk                    /*!< COMPx Windows mode selection bit     */

+#define COMP_CFGRx_ITEN_Pos          (6U)

+#define COMP_CFGRx_ITEN_Msk          (0x1UL << COMP_CFGRx_ITEN_Pos)            /*!< 0x00000040 */

+#define COMP_CFGRx_ITEN              COMP_CFGRx_ITEN_Msk                       /*!< COMPx  interrupt enable              */

+#define COMP_CFGRx_HYST_Pos          (8U)

+#define COMP_CFGRx_HYST_Msk          (0x3UL << COMP_CFGRx_HYST_Pos)            /*!< 0x00000300 */

+#define COMP_CFGRx_HYST              COMP_CFGRx_HYST_Msk                       /*!< COMPx  hysteresis selection bits     */

+#define COMP_CFGRx_HYST_0            (0x1UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000100 */

+#define COMP_CFGRx_HYST_1            (0x2UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000200 */

+#define COMP_CFGRx_PWRMODE_Pos       (12U)

+#define COMP_CFGRx_PWRMODE_Msk       (0x3UL << COMP_CFGRx_PWRMODE_Pos)         /*!< 0x00003000 */

+#define COMP_CFGRx_PWRMODE           COMP_CFGRx_PWRMODE_Msk                    /*!< COMPx Power Mode of the comparator   */

+#define COMP_CFGRx_PWRMODE_0         (0x1UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00001000 */

+#define COMP_CFGRx_PWRMODE_1         (0x2UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00002000 */

+#define COMP_CFGRx_INMSEL_Pos        (16U)

+#define COMP_CFGRx_INMSEL_Msk        (0xFUL << COMP_CFGRx_INMSEL_Pos)          /*!< 0x000F0000 */

+#define COMP_CFGRx_INMSEL            COMP_CFGRx_INMSEL_Msk                     /*!< COMPx  input minus selection bit  */

+#define COMP_CFGRx_INMSEL_0          (0x1UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00010000 */

+#define COMP_CFGRx_INMSEL_1          (0x2UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00020000 */

+#define COMP_CFGRx_INMSEL_2          (0x4UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00040000 */

+#define COMP_CFGRx_INMSEL_3          (0x8UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00080000 */

+#define COMP_CFGRx_INPSEL_Pos        (20U)

+#define COMP_CFGRx_INPSEL_Msk        (0x1UL << COMP_CFGRx_INPSEL_Pos)          /*!< 0x00100000 */

+#define COMP_CFGRx_INPSEL            COMP_CFGRx_INPSEL_Msk                     /*!< COMPx  input plus selection bit       */

+#define COMP_CFGRx_INP2SEL_Pos        (22U)

+#define COMP_CFGRx_INP2SEL_Msk        (0x1UL << COMP_CFGRx_INP2SEL_Pos)        /*!< 0x00400000 */

+#define COMP_CFGRx_INP2SEL            COMP_CFGRx_INP2SEL_Msk                   /*!< COMPx  input plus 2 selection bit     */

+#define COMP_CFGRx_BLANKING_Pos      (24U)

+#define COMP_CFGRx_BLANKING_Msk      (0xFUL << COMP_CFGRx_BLANKING_Pos)        /*!< 0x0F000000 */

+#define COMP_CFGRx_BLANKING          COMP_CFGRx_BLANKING_Msk                   /*!< COMPx  blanking source selection bits */

+#define COMP_CFGRx_BLANKING_0        (0x1UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x01000000 */

+#define COMP_CFGRx_BLANKING_1        (0x2UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x02000000 */

+#define COMP_CFGRx_BLANKING_2        (0x4UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x04000000 */

+#define COMP_CFGRx_LOCK_Pos          (31U)

+#define COMP_CFGRx_LOCK_Msk          (0x1UL << COMP_CFGRx_LOCK_Pos)            /*!< 0x80000000 */

+#define COMP_CFGRx_LOCK              COMP_CFGRx_LOCK_Msk                       /*!< COMPx Lock Bit                        */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for USART_CR1 register  *******************/

+#define USART_CR1_UE_Pos                (0U)

+#define USART_CR1_UE_Msk                (0x1UL << USART_CR1_UE_Pos)            /*!< 0x00000001 */

+#define USART_CR1_UE                    USART_CR1_UE_Msk                       /*!< USART Enable */

+#define USART_CR1_UESM_Pos              (1U)

+#define USART_CR1_UESM_Msk              (0x1UL << USART_CR1_UESM_Pos)          /*!< 0x00000002 */

+#define USART_CR1_UESM                  USART_CR1_UESM_Msk                     /*!< USART Enable in STOP Mode */

+#define USART_CR1_RE_Pos                (2U)

+#define USART_CR1_RE_Msk                (0x1UL << USART_CR1_RE_Pos)            /*!< 0x00000004 */

+#define USART_CR1_RE                    USART_CR1_RE_Msk                       /*!< Receiver Enable */

+#define USART_CR1_TE_Pos                (3U)

+#define USART_CR1_TE_Msk                (0x1UL << USART_CR1_TE_Pos)            /*!< 0x00000008 */

+#define USART_CR1_TE                    USART_CR1_TE_Msk                       /*!< Transmitter Enable */

+#define USART_CR1_IDLEIE_Pos            (4U)

+#define USART_CR1_IDLEIE_Msk            (0x1UL << USART_CR1_IDLEIE_Pos)        /*!< 0x00000010 */

+#define USART_CR1_IDLEIE                USART_CR1_IDLEIE_Msk                   /*!< IDLE Interrupt Enable */

+#define USART_CR1_RXNEIE_RXFNEIE_Pos    (5U)

+#define USART_CR1_RXNEIE_RXFNEIE_Msk    (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */

+#define USART_CR1_RXNEIE_RXFNEIE        USART_CR1_RXNEIE_RXFNEIE_Msk           /*!< RXNE and RX FIFO Not Empty Interrupt Enable */

+#define USART_CR1_TCIE_Pos              (6U)

+#define USART_CR1_TCIE_Msk              (0x1UL << USART_CR1_TCIE_Pos)          /*!< 0x00000040 */

+#define USART_CR1_TCIE                  USART_CR1_TCIE_Msk                     /*!< Transmission Complete Interrupt Enable */

+#define USART_CR1_TXEIE_TXFNFIE_Pos     (7U)

+#define USART_CR1_TXEIE_TXFNFIE_Msk     (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */

+#define USART_CR1_TXEIE_TXFNFIE         USART_CR1_TXEIE_TXFNFIE_Msk            /*!< TXE and TX FIFO Not Full Interrupt Enable */

+#define USART_CR1_PEIE_Pos              (8U)

+#define USART_CR1_PEIE_Msk              (0x1UL << USART_CR1_PEIE_Pos)          /*!< 0x00000100 */

+#define USART_CR1_PEIE                  USART_CR1_PEIE_Msk                     /*!< PE Interrupt Enable */

+#define USART_CR1_PS_Pos                (9U)

+#define USART_CR1_PS_Msk                (0x1UL << USART_CR1_PS_Pos)            /*!< 0x00000200 */

+#define USART_CR1_PS                    USART_CR1_PS_Msk                       /*!< Parity Selection */

+#define USART_CR1_PCE_Pos               (10U)

+#define USART_CR1_PCE_Msk               (0x1UL << USART_CR1_PCE_Pos)           /*!< 0x00000400 */

+#define USART_CR1_PCE                   USART_CR1_PCE_Msk                      /*!< Parity Control Enable */

+#define USART_CR1_WAKE_Pos              (11U)

+#define USART_CR1_WAKE_Msk              (0x1UL << USART_CR1_WAKE_Pos)          /*!< 0x00000800 */

+#define USART_CR1_WAKE                  USART_CR1_WAKE_Msk                     /*!< Receiver Wakeup method */

+#define USART_CR1_M_Pos                 (12U)

+#define USART_CR1_M_Msk                 (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */

+#define USART_CR1_M                     USART_CR1_M_Msk                        /*!< Word length */

+#define USART_CR1_M0_Pos                (12U)

+#define USART_CR1_M0_Msk                (0x1UL << USART_CR1_M0_Pos)            /*!< 0x00001000 */

+#define USART_CR1_M0                    USART_CR1_M0_Msk                       /*!< Word length - Bit 0 */

+#define USART_CR1_MME_Pos               (13U)

+#define USART_CR1_MME_Msk               (0x1UL << USART_CR1_MME_Pos)           /*!< 0x00002000 */

+#define USART_CR1_MME                   USART_CR1_MME_Msk                      /*!< Mute Mode Enable */

+#define USART_CR1_CMIE_Pos              (14U)

+#define USART_CR1_CMIE_Msk              (0x1UL << USART_CR1_CMIE_Pos)          /*!< 0x00004000 */

+#define USART_CR1_CMIE                  USART_CR1_CMIE_Msk                     /*!< Character match interrupt enable */

+#define USART_CR1_OVER8_Pos             (15U)

+#define USART_CR1_OVER8_Msk             (0x1UL << USART_CR1_OVER8_Pos)         /*!< 0x00008000 */

+#define USART_CR1_OVER8                 USART_CR1_OVER8_Msk                    /*!< Oversampling by 8-bit or 16-bit mode */

+#define USART_CR1_DEDT_Pos              (16U)

+#define USART_CR1_DEDT_Msk              (0x1FUL << USART_CR1_DEDT_Pos)         /*!< 0x001F0000 */

+#define USART_CR1_DEDT                  USART_CR1_DEDT_Msk                     /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */

+#define USART_CR1_DEDT_0                (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */

+#define USART_CR1_DEDT_1                (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */

+#define USART_CR1_DEDT_2                (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */

+#define USART_CR1_DEDT_3                (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */

+#define USART_CR1_DEDT_4                (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */

+#define USART_CR1_DEAT_Pos              (21U)

+#define USART_CR1_DEAT_Msk              (0x1FUL << USART_CR1_DEAT_Pos)         /*!< 0x03E00000 */

+#define USART_CR1_DEAT                  USART_CR1_DEAT_Msk                     /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */

+#define USART_CR1_DEAT_0                (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */

+#define USART_CR1_DEAT_1                (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */

+#define USART_CR1_DEAT_2                (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */

+#define USART_CR1_DEAT_3                (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */

+#define USART_CR1_DEAT_4                (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */

+#define USART_CR1_RTOIE_Pos             (26U)

+#define USART_CR1_RTOIE_Msk             (0x1UL << USART_CR1_RTOIE_Pos)         /*!< 0x04000000 */

+#define USART_CR1_RTOIE                 USART_CR1_RTOIE_Msk                    /*!< Receive Time Out interrupt enable */

+#define USART_CR1_EOBIE_Pos             (27U)

+#define USART_CR1_EOBIE_Msk             (0x1UL << USART_CR1_EOBIE_Pos)         /*!< 0x08000000 */

+#define USART_CR1_EOBIE                 USART_CR1_EOBIE_Msk                    /*!< End of Block interrupt enable */

+#define USART_CR1_M1_Pos                (28U)

+#define USART_CR1_M1_Msk                (0x1UL << USART_CR1_M1_Pos)            /*!< 0x10000000 */

+#define USART_CR1_M1                    USART_CR1_M1_Msk                       /*!< Word length - Bit 1 */

+#define USART_CR1_FIFOEN_Pos            (29U)

+#define USART_CR1_FIFOEN_Msk            (0x1UL << USART_CR1_FIFOEN_Pos)        /*!< 0x20000000 */

+#define USART_CR1_FIFOEN                USART_CR1_FIFOEN_Msk                   /*!< FIFO mode enable */

+#define USART_CR1_TXFEIE_Pos            (30U)

+#define USART_CR1_TXFEIE_Msk            (0x1UL << USART_CR1_TXFEIE_Pos)        /*!< 0x40000000 */

+#define USART_CR1_TXFEIE                USART_CR1_TXFEIE_Msk                   /*!< TXFIFO empty interrupt enable */

+#define USART_CR1_RXFFIE_Pos            (31U)

+#define USART_CR1_RXFFIE_Msk            (0x1UL << USART_CR1_RXFFIE_Pos)        /*!< 0x80000000 */

+#define USART_CR1_RXFFIE                USART_CR1_RXFFIE_Msk                   /*!< RXFIFO Full interrupt enable */

+

+/* Legacy define */

+#define  USART_CR1_RXNEIE  USART_CR1_RXNEIE_RXFNEIE

+#define  USART_CR1_TXEIE   USART_CR1_TXEIE_TXFNFIE

+

+/******************  Bit definition for USART_CR2 register  *******************/

+#define USART_CR2_SLVEN_Pos             (0U)

+#define USART_CR2_SLVEN_Msk             (0x1UL << USART_CR2_SLVEN_Pos)         /*!< 0x00000001 */

+#define USART_CR2_SLVEN                 USART_CR2_SLVEN_Msk                    /*!< Synchronous Slave mode Enable */

+#define USART_CR2_DIS_NSS_Pos           (3U)

+#define USART_CR2_DIS_NSS_Msk           (0x1UL << USART_CR2_DIS_NSS_Pos)       /*!< 0x00000008 */

+#define USART_CR2_DIS_NSS               USART_CR2_DIS_NSS_Msk                  /*!< Negative Slave Select (NSS) pin management */

+#define USART_CR2_ADDM7_Pos             (4U)

+#define USART_CR2_ADDM7_Msk             (0x1UL << USART_CR2_ADDM7_Pos)         /*!< 0x00000010 */

+#define USART_CR2_ADDM7                 USART_CR2_ADDM7_Msk                    /*!< 7-bit or 4-bit Address Detection */

+#define USART_CR2_LBDL_Pos              (5U)

+#define USART_CR2_LBDL_Msk              (0x1UL << USART_CR2_LBDL_Pos)          /*!< 0x00000020 */

+#define USART_CR2_LBDL                  USART_CR2_LBDL_Msk                     /*!< LIN Break Detection Length */

+#define USART_CR2_LBDIE_Pos             (6U)

+#define USART_CR2_LBDIE_Msk             (0x1UL << USART_CR2_LBDIE_Pos)         /*!< 0x00000040 */

+#define USART_CR2_LBDIE                 USART_CR2_LBDIE_Msk                    /*!< LIN Break Detection Interrupt Enable */

+#define USART_CR2_LBCL_Pos              (8U)

+#define USART_CR2_LBCL_Msk              (0x1UL << USART_CR2_LBCL_Pos)          /*!< 0x00000100 */

+#define USART_CR2_LBCL                  USART_CR2_LBCL_Msk                     /*!< Last Bit Clock pulse */

+#define USART_CR2_CPHA_Pos              (9U)

+#define USART_CR2_CPHA_Msk              (0x1UL << USART_CR2_CPHA_Pos)          /*!< 0x00000200 */

+#define USART_CR2_CPHA                  USART_CR2_CPHA_Msk                     /*!< Clock Phase */

+#define USART_CR2_CPOL_Pos              (10U)

+#define USART_CR2_CPOL_Msk              (0x1UL << USART_CR2_CPOL_Pos)          /*!< 0x00000400 */

+#define USART_CR2_CPOL                  USART_CR2_CPOL_Msk                     /*!< Clock Polarity */

+#define USART_CR2_CLKEN_Pos             (11U)

+#define USART_CR2_CLKEN_Msk             (0x1UL << USART_CR2_CLKEN_Pos)         /*!< 0x00000800 */

+#define USART_CR2_CLKEN                 USART_CR2_CLKEN_Msk                    /*!< Clock Enable */

+#define USART_CR2_STOP_Pos              (12U)

+#define USART_CR2_STOP_Msk              (0x3UL << USART_CR2_STOP_Pos)          /*!< 0x00003000 */

+#define USART_CR2_STOP                  USART_CR2_STOP_Msk                     /*!< STOP[1:0] bits (STOP bits) */

+#define USART_CR2_STOP_0                (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */

+#define USART_CR2_STOP_1                (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */

+#define USART_CR2_LINEN_Pos             (14U)

+#define USART_CR2_LINEN_Msk             (0x1UL << USART_CR2_LINEN_Pos)         /*!< 0x00004000 */

+#define USART_CR2_LINEN                 USART_CR2_LINEN_Msk                    /*!< LIN mode enable */

+#define USART_CR2_SWAP_Pos              (15U)

+#define USART_CR2_SWAP_Msk              (0x1UL << USART_CR2_SWAP_Pos)          /*!< 0x00008000 */

+#define USART_CR2_SWAP                  USART_CR2_SWAP_Msk                     /*!< SWAP TX/RX pins */

+#define USART_CR2_RXINV_Pos             (16U)

+#define USART_CR2_RXINV_Msk             (0x1UL << USART_CR2_RXINV_Pos)         /*!< 0x00010000 */

+#define USART_CR2_RXINV                 USART_CR2_RXINV_Msk                    /*!< RX pin active level inversion */

+#define USART_CR2_TXINV_Pos             (17U)

+#define USART_CR2_TXINV_Msk             (0x1UL << USART_CR2_TXINV_Pos)         /*!< 0x00020000 */

+#define USART_CR2_TXINV                 USART_CR2_TXINV_Msk                    /*!< TX pin active level inversion */

+#define USART_CR2_DATAINV_Pos           (18U)

+#define USART_CR2_DATAINV_Msk           (0x1UL << USART_CR2_DATAINV_Pos)       /*!< 0x00040000 */

+#define USART_CR2_DATAINV               USART_CR2_DATAINV_Msk                  /*!< Binary data inversion */

+#define USART_CR2_MSBFIRST_Pos          (19U)

+#define USART_CR2_MSBFIRST_Msk          (0x1UL << USART_CR2_MSBFIRST_Pos)      /*!< 0x00080000 */

+#define USART_CR2_MSBFIRST              USART_CR2_MSBFIRST_Msk                 /*!< Most Significant Bit First */

+#define USART_CR2_ABREN_Pos             (20U)

+#define USART_CR2_ABREN_Msk             (0x1UL << USART_CR2_ABREN_Pos)         /*!< 0x00100000 */

+#define USART_CR2_ABREN                 USART_CR2_ABREN_Msk                    /*!< Auto Baud-Rate Enable*/

+#define USART_CR2_ABRMODE_Pos           (21U)

+#define USART_CR2_ABRMODE_Msk           (0x3UL << USART_CR2_ABRMODE_Pos)       /*!< 0x00600000 */

+#define USART_CR2_ABRMODE               USART_CR2_ABRMODE_Msk                  /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */

+#define USART_CR2_ABRMODE_0             (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */

+#define USART_CR2_ABRMODE_1             (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */

+#define USART_CR2_RTOEN_Pos             (23U)

+#define USART_CR2_RTOEN_Msk             (0x1UL << USART_CR2_RTOEN_Pos)         /*!< 0x00800000 */

+#define USART_CR2_RTOEN                 USART_CR2_RTOEN_Msk                    /*!< Receiver Time-Out enable */

+#define USART_CR2_ADD_Pos               (24U)

+#define USART_CR2_ADD_Msk               (0xFFUL << USART_CR2_ADD_Pos)          /*!< 0xFF000000 */

+#define USART_CR2_ADD                   USART_CR2_ADD_Msk                      /*!< Address of the USART node */

+

+/******************  Bit definition for USART_CR3 register  *******************/

+#define USART_CR3_EIE_Pos               (0U)

+#define USART_CR3_EIE_Msk               (0x1UL << USART_CR3_EIE_Pos)           /*!< 0x00000001 */

+#define USART_CR3_EIE                   USART_CR3_EIE_Msk                      /*!< Error Interrupt Enable */

+#define USART_CR3_IREN_Pos              (1U)

+#define USART_CR3_IREN_Msk              (0x1UL << USART_CR3_IREN_Pos)          /*!< 0x00000002 */

+#define USART_CR3_IREN                  USART_CR3_IREN_Msk                     /*!< IrDA mode Enable */

+#define USART_CR3_IRLP_Pos              (2U)

+#define USART_CR3_IRLP_Msk              (0x1UL << USART_CR3_IRLP_Pos)          /*!< 0x00000004 */

+#define USART_CR3_IRLP                  USART_CR3_IRLP_Msk                     /*!< IrDA Low-Power */

+#define USART_CR3_HDSEL_Pos             (3U)

+#define USART_CR3_HDSEL_Msk             (0x1UL << USART_CR3_HDSEL_Pos)         /*!< 0x00000008 */

+#define USART_CR3_HDSEL                 USART_CR3_HDSEL_Msk                    /*!< Half-Duplex Selection */

+#define USART_CR3_NACK_Pos              (4U)

+#define USART_CR3_NACK_Msk              (0x1UL << USART_CR3_NACK_Pos)          /*!< 0x00000010 */

+#define USART_CR3_NACK                  USART_CR3_NACK_Msk                     /*!< SmartCard NACK enable */

+#define USART_CR3_SCEN_Pos              (5U)

+#define USART_CR3_SCEN_Msk              (0x1UL << USART_CR3_SCEN_Pos)          /*!< 0x00000020 */

+#define USART_CR3_SCEN                  USART_CR3_SCEN_Msk                     /*!< SmartCard mode enable */

+#define USART_CR3_DMAR_Pos              (6U)

+#define USART_CR3_DMAR_Msk              (0x1UL << USART_CR3_DMAR_Pos)          /*!< 0x00000040 */

+#define USART_CR3_DMAR                  USART_CR3_DMAR_Msk                     /*!< DMA Enable Receiver */

+#define USART_CR3_DMAT_Pos              (7U)

+#define USART_CR3_DMAT_Msk              (0x1UL << USART_CR3_DMAT_Pos)          /*!< 0x00000080 */

+#define USART_CR3_DMAT                  USART_CR3_DMAT_Msk                     /*!< DMA Enable Transmitter */

+#define USART_CR3_RTSE_Pos              (8U)

+#define USART_CR3_RTSE_Msk              (0x1UL << USART_CR3_RTSE_Pos)          /*!< 0x00000100 */

+#define USART_CR3_RTSE                  USART_CR3_RTSE_Msk                     /*!< RTS Enable */

+#define USART_CR3_CTSE_Pos              (9U)

+#define USART_CR3_CTSE_Msk              (0x1UL << USART_CR3_CTSE_Pos)          /*!< 0x00000200 */

+#define USART_CR3_CTSE                  USART_CR3_CTSE_Msk                     /*!< CTS Enable */

+#define USART_CR3_CTSIE_Pos             (10U)

+#define USART_CR3_CTSIE_Msk             (0x1UL << USART_CR3_CTSIE_Pos)         /*!< 0x00000400 */

+#define USART_CR3_CTSIE                 USART_CR3_CTSIE_Msk                    /*!< CTS Interrupt Enable */

+#define USART_CR3_ONEBIT_Pos            (11U)

+#define USART_CR3_ONEBIT_Msk            (0x1UL << USART_CR3_ONEBIT_Pos)        /*!< 0x00000800 */

+#define USART_CR3_ONEBIT                USART_CR3_ONEBIT_Msk                   /*!< One sample bit method enable */

+#define USART_CR3_OVRDIS_Pos            (12U)

+#define USART_CR3_OVRDIS_Msk            (0x1UL << USART_CR3_OVRDIS_Pos)        /*!< 0x00001000 */

+#define USART_CR3_OVRDIS                USART_CR3_OVRDIS_Msk                   /*!< Overrun Disable */

+#define USART_CR3_DDRE_Pos              (13U)

+#define USART_CR3_DDRE_Msk              (0x1UL << USART_CR3_DDRE_Pos)          /*!< 0x00002000 */

+#define USART_CR3_DDRE                  USART_CR3_DDRE_Msk                     /*!< DMA Disable on Reception Error */

+#define USART_CR3_DEM_Pos               (14U)

+#define USART_CR3_DEM_Msk               (0x1UL << USART_CR3_DEM_Pos)           /*!< 0x00004000 */

+#define USART_CR3_DEM                   USART_CR3_DEM_Msk                      /*!< Driver Enable Mode */

+#define USART_CR3_DEP_Pos               (15U)

+#define USART_CR3_DEP_Msk               (0x1UL << USART_CR3_DEP_Pos)           /*!< 0x00008000 */

+#define USART_CR3_DEP                   USART_CR3_DEP_Msk                      /*!< Driver Enable Polarity Selection */

+#define USART_CR3_SCARCNT_Pos           (17U)

+#define USART_CR3_SCARCNT_Msk           (0x7UL << USART_CR3_SCARCNT_Pos)       /*!< 0x000E0000 */

+#define USART_CR3_SCARCNT               USART_CR3_SCARCNT_Msk                  /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */

+#define USART_CR3_SCARCNT_0             (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */

+#define USART_CR3_SCARCNT_1             (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */

+#define USART_CR3_SCARCNT_2             (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */

+#define USART_CR3_WUS_Pos               (20U)

+#define USART_CR3_WUS_Msk               (0x3UL << USART_CR3_WUS_Pos)           /*!< 0x00300000 */

+#define USART_CR3_WUS                   USART_CR3_WUS_Msk                      /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */

+#define USART_CR3_WUS_0                 (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */

+#define USART_CR3_WUS_1                 (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */

+#define USART_CR3_WUFIE_Pos             (22U)

+#define USART_CR3_WUFIE_Msk             (0x1UL << USART_CR3_WUFIE_Pos)         /*!< 0x00400000 */

+#define USART_CR3_WUFIE                 USART_CR3_WUFIE_Msk                    /*!< Wake Up Interrupt Enable */

+#define USART_CR3_TXFTIE_Pos            (23U)

+#define USART_CR3_TXFTIE_Msk            (0x1UL << USART_CR3_TXFTIE_Pos)        /*!< 0x00800000 */

+#define USART_CR3_TXFTIE                USART_CR3_TXFTIE_Msk                   /*!< TXFIFO threshold interrupt enable */

+#define USART_CR3_TCBGTIE_Pos           (24U)

+#define USART_CR3_TCBGTIE_Msk           (0x1UL << USART_CR3_TCBGTIE_Pos)       /*!< 0x01000000 */

+#define USART_CR3_TCBGTIE               USART_CR3_TCBGTIE_Msk                  /*!< Transmission Complete before guard time, interrupt enable */

+#define USART_CR3_RXFTCFG_Pos           (25U)

+#define USART_CR3_RXFTCFG_Msk           (0x7UL << USART_CR3_RXFTCFG_Pos)       /*!< 0x0E000000 */

+#define USART_CR3_RXFTCFG               USART_CR3_RXFTCFG_Msk                  /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */

+#define USART_CR3_RXFTCFG_0             (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */

+#define USART_CR3_RXFTCFG_1             (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */

+#define USART_CR3_RXFTCFG_2             (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */

+#define USART_CR3_RXFTIE_Pos            (28U)

+#define USART_CR3_RXFTIE_Msk            (0x1UL << USART_CR3_RXFTIE_Pos)        /*!< 0x10000000 */

+#define USART_CR3_RXFTIE                USART_CR3_RXFTIE_Msk                   /*!< RXFIFO threshold interrupt enable */

+#define USART_CR3_TXFTCFG_Pos           (29U)

+#define USART_CR3_TXFTCFG_Msk           (0x7UL << USART_CR3_TXFTCFG_Pos)       /*!< 0xE0000000 */

+#define USART_CR3_TXFTCFG               USART_CR3_TXFTCFG_Msk                  /*!< TXFIFO [2:0] threshold configuration */

+#define USART_CR3_TXFTCFG_0             (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */

+#define USART_CR3_TXFTCFG_1             (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */

+#define USART_CR3_TXFTCFG_2             (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */

+

+/******************  Bit definition for USART_BRR register  *******************/

+#define USART_BRR_DIV_FRACTION_Pos      (0U)

+#define USART_BRR_DIV_FRACTION_Msk      (0xFUL << USART_BRR_DIV_FRACTION_Pos)  /*!< 0x0000000F */

+#define USART_BRR_DIV_FRACTION          USART_BRR_DIV_FRACTION_Msk             /*!< Fraction of USARTDIV */

+#define USART_BRR_DIV_MANTISSA_Pos      (4U)

+#define USART_BRR_DIV_MANTISSA_Msk      (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */

+#define USART_BRR_DIV_MANTISSA          USART_BRR_DIV_MANTISSA_Msk             /*!< Mantissa of USARTDIV */

+

+/******************  Bit definition for USART_GTPR register  ******************/

+#define USART_GTPR_PSC_Pos              (0U)

+#define USART_GTPR_PSC_Msk              (0xFFUL << USART_GTPR_PSC_Pos)         /*!< 0x000000FF */

+#define USART_GTPR_PSC                  USART_GTPR_PSC_Msk                     /*!< PSC[7:0] bits (Prescaler value) */

+#define USART_GTPR_GT_Pos               (8U)

+#define USART_GTPR_GT_Msk               (0xFFUL << USART_GTPR_GT_Pos)          /*!< 0x0000FF00 */

+#define USART_GTPR_GT                   USART_GTPR_GT_Msk                      /*!< GT[7:0] bits (Guard time value) */

+

+/*******************  Bit definition for USART_RTOR register  *****************/

+#define USART_RTOR_RTO_Pos              (0U)

+#define USART_RTOR_RTO_Msk              (0xFFFFFFUL << USART_RTOR_RTO_Pos)     /*!< 0x00FFFFFF */

+#define USART_RTOR_RTO                  USART_RTOR_RTO_Msk                     /*!< Receiver Time Out Value */

+#define USART_RTOR_BLEN_Pos             (24U)

+#define USART_RTOR_BLEN_Msk             (0xFFUL << USART_RTOR_BLEN_Pos)        /*!< 0xFF000000 */

+#define USART_RTOR_BLEN                 USART_RTOR_BLEN_Msk                    /*!< Block Length */

+

+/*******************  Bit definition for USART_RQR register  ******************/

+#define USART_RQR_ABRRQ_Pos             (0U)

+#define USART_RQR_ABRRQ_Msk             (0x1UL << USART_RQR_ABRRQ_Pos)         /*!< 0x00000001 */

+#define USART_RQR_ABRRQ                 USART_RQR_ABRRQ_Msk                    /*!< Auto-Baud Rate Request */

+#define USART_RQR_SBKRQ_Pos             (1U)

+#define USART_RQR_SBKRQ_Msk             (0x1UL << USART_RQR_SBKRQ_Pos)         /*!< 0x00000002 */

+#define USART_RQR_SBKRQ                 USART_RQR_SBKRQ_Msk                    /*!< Send Break Request */

+#define USART_RQR_MMRQ_Pos              (2U)

+#define USART_RQR_MMRQ_Msk              (0x1UL << USART_RQR_MMRQ_Pos)          /*!< 0x00000004 */

+#define USART_RQR_MMRQ                  USART_RQR_MMRQ_Msk                     /*!< Mute Mode Request */

+#define USART_RQR_RXFRQ_Pos             (3U)

+#define USART_RQR_RXFRQ_Msk             (0x1UL << USART_RQR_RXFRQ_Pos)         /*!< 0x00000008 */

+#define USART_RQR_RXFRQ                 USART_RQR_RXFRQ_Msk                    /*!< Receive Data flush Request */

+#define USART_RQR_TXFRQ_Pos             (4U)

+#define USART_RQR_TXFRQ_Msk             (0x1UL << USART_RQR_TXFRQ_Pos)         /*!< 0x00000010 */

+#define USART_RQR_TXFRQ                 USART_RQR_TXFRQ_Msk                    /*!< Transmit data flush Request */

+

+/*******************  Bit definition for USART_ISR register  ******************/

+#define USART_ISR_PE_Pos                (0U)

+#define USART_ISR_PE_Msk                (0x1UL << USART_ISR_PE_Pos)            /*!< 0x00000001 */

+#define USART_ISR_PE                    USART_ISR_PE_Msk                       /*!< Parity Error */

+#define USART_ISR_FE_Pos                (1U)

+#define USART_ISR_FE_Msk                (0x1UL << USART_ISR_FE_Pos)            /*!< 0x00000002 */

+#define USART_ISR_FE                    USART_ISR_FE_Msk                       /*!< Framing Error */

+#define USART_ISR_NE_Pos                (2U)

+#define USART_ISR_NE_Msk                (0x1UL << USART_ISR_NE_Pos)            /*!< 0x00000004 */

+#define USART_ISR_NE                    USART_ISR_NE_Msk                       /*!< Noise detected Flag */

+#define USART_ISR_ORE_Pos               (3U)

+#define USART_ISR_ORE_Msk               (0x1UL << USART_ISR_ORE_Pos)           /*!< 0x00000008 */

+#define USART_ISR_ORE                   USART_ISR_ORE_Msk                      /*!< OverRun Error */

+#define USART_ISR_IDLE_Pos              (4U)

+#define USART_ISR_IDLE_Msk              (0x1UL << USART_ISR_IDLE_Pos)          /*!< 0x00000010 */

+#define USART_ISR_IDLE                  USART_ISR_IDLE_Msk                     /*!< IDLE line detected */

+#define USART_ISR_RXNE_RXFNE_Pos        (5U)

+#define USART_ISR_RXNE_RXFNE_Msk        (0x1UL << USART_ISR_RXNE_RXFNE_Pos)    /*!< 0x00000020 */

+#define USART_ISR_RXNE_RXFNE            USART_ISR_RXNE_RXFNE_Msk               /*!< Read Data Register or RX FIFO Not Empty */

+#define USART_ISR_TC_Pos                (6U)

+#define USART_ISR_TC_Msk                (0x1UL << USART_ISR_TC_Pos)            /*!< 0x00000040 */

+#define USART_ISR_TC                    USART_ISR_TC_Msk                       /*!< Transmission Complete */

+#define USART_ISR_TXE_TXFNF_Pos         (7U)

+#define USART_ISR_TXE_TXFNF_Msk         (0x1UL << USART_ISR_TXE_TXFNF_Pos)     /*!< 0x00000080 */

+#define USART_ISR_TXE_TXFNF             USART_ISR_TXE_TXFNF_Msk                /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */

+#define USART_ISR_LBDF_Pos              (8U)

+#define USART_ISR_LBDF_Msk              (0x1UL << USART_ISR_LBDF_Pos)          /*!< 0x00000100 */

+#define USART_ISR_LBDF                  USART_ISR_LBDF_Msk                     /*!< LIN Break Detection Flag */

+#define USART_ISR_CTSIF_Pos             (9U)

+#define USART_ISR_CTSIF_Msk             (0x1UL << USART_ISR_CTSIF_Pos)         /*!< 0x00000200 */

+#define USART_ISR_CTSIF                 USART_ISR_CTSIF_Msk                    /*!< CTS interrupt flag */

+#define USART_ISR_CTS_Pos               (10U)

+#define USART_ISR_CTS_Msk               (0x1UL << USART_ISR_CTS_Pos)           /*!< 0x00000400 */

+#define USART_ISR_CTS                   USART_ISR_CTS_Msk                      /*!< CTS flag */

+#define USART_ISR_RTOF_Pos              (11U)

+#define USART_ISR_RTOF_Msk              (0x1UL << USART_ISR_RTOF_Pos)          /*!< 0x00000800 */

+#define USART_ISR_RTOF                  USART_ISR_RTOF_Msk                     /*!< Receiver Time Out */

+#define USART_ISR_EOBF_Pos              (12U)

+#define USART_ISR_EOBF_Msk              (0x1UL << USART_ISR_EOBF_Pos)          /*!< 0x00001000 */

+#define USART_ISR_EOBF                  USART_ISR_EOBF_Msk                     /*!< End Of Block Flag */

+#define USART_ISR_UDR_Pos               (13U)

+#define USART_ISR_UDR_Msk               (0x1UL << USART_ISR_UDR_Pos)           /*!< 0x00002000 */

+#define USART_ISR_UDR                   USART_ISR_UDR_Msk                      /*!< SPI slave underrun error flag */

+#define USART_ISR_ABRE_Pos              (14U)

+#define USART_ISR_ABRE_Msk              (0x1UL << USART_ISR_ABRE_Pos)          /*!< 0x00004000 */

+#define USART_ISR_ABRE                  USART_ISR_ABRE_Msk                     /*!< Auto-Baud Rate Error */

+#define USART_ISR_ABRF_Pos              (15U)

+#define USART_ISR_ABRF_Msk              (0x1UL << USART_ISR_ABRF_Pos)          /*!< 0x00008000 */

+#define USART_ISR_ABRF                  USART_ISR_ABRF_Msk                     /*!< Auto-Baud Rate Flag */

+#define USART_ISR_BUSY_Pos              (16U)

+#define USART_ISR_BUSY_Msk              (0x1UL << USART_ISR_BUSY_Pos)          /*!< 0x00010000 */

+#define USART_ISR_BUSY                  USART_ISR_BUSY_Msk                     /*!< Busy Flag */

+#define USART_ISR_CMF_Pos               (17U)

+#define USART_ISR_CMF_Msk               (0x1UL << USART_ISR_CMF_Pos)           /*!< 0x00020000 */

+#define USART_ISR_CMF                   USART_ISR_CMF_Msk                      /*!< Character Match Flag */

+#define USART_ISR_SBKF_Pos              (18U)

+#define USART_ISR_SBKF_Msk              (0x1UL << USART_ISR_SBKF_Pos)          /*!< 0x00040000 */

+#define USART_ISR_SBKF                  USART_ISR_SBKF_Msk                     /*!< Send Break Flag */

+#define USART_ISR_RWU_Pos               (19U)

+#define USART_ISR_RWU_Msk               (0x1UL << USART_ISR_RWU_Pos)           /*!< 0x00080000 */

+#define USART_ISR_RWU                   USART_ISR_RWU_Msk                      /*!< Receive Wake Up from mute mode Flag */

+#define USART_ISR_WUF_Pos               (20U)

+#define USART_ISR_WUF_Msk               (0x1UL << USART_ISR_WUF_Pos)           /*!< 0x00100000 */

+#define USART_ISR_WUF                   USART_ISR_WUF_Msk                      /*!< Wake Up from stop mode Flag */

+#define USART_ISR_TEACK_Pos             (21U)

+#define USART_ISR_TEACK_Msk             (0x1UL << USART_ISR_TEACK_Pos)         /*!< 0x00200000 */

+#define USART_ISR_TEACK                 USART_ISR_TEACK_Msk                    /*!< Transmit Enable Acknowledge Flag */

+#define USART_ISR_REACK_Pos             (22U)

+#define USART_ISR_REACK_Msk             (0x1UL << USART_ISR_REACK_Pos)         /*!< 0x00400000 */

+#define USART_ISR_REACK                 USART_ISR_REACK_Msk                    /*!< Receive Enable Acknowledge Flag */

+#define USART_ISR_TXFE_Pos              (23U)

+#define USART_ISR_TXFE_Msk              (0x1UL << USART_ISR_TXFE_Pos)          /*!< 0x00800000 */

+#define USART_ISR_TXFE                  USART_ISR_TXFE_Msk                     /*!< TXFIFO Empty */

+#define USART_ISR_RXFF_Pos              (24U)

+#define USART_ISR_RXFF_Msk              (0x1UL << USART_ISR_RXFF_Pos)          /*!< 0x01000000 */

+#define USART_ISR_RXFF                  USART_ISR_RXFF_Msk                     /*!< RXFIFO Full Flag */

+#define USART_ISR_TCBGT_Pos             (25U)

+#define USART_ISR_TCBGT_Msk             (0x1UL << USART_ISR_TCBGT_Pos)         /*!< 0x02000000 */

+#define USART_ISR_TCBGT                 USART_ISR_TCBGT_Msk                    /*!< Transmission complete before guard time Flag */

+#define USART_ISR_RXFT_Pos              (26U)

+#define USART_ISR_RXFT_Msk              (0x1UL << USART_ISR_RXFT_Pos)          /*!< 0x04000000 */

+#define USART_ISR_RXFT                  USART_ISR_RXFT_Msk                     /*!< RXFIFO threshold Flag */

+#define USART_ISR_TXFT_Pos              (27U)

+#define USART_ISR_TXFT_Msk              (0x1UL << USART_ISR_TXFT_Pos)          /*!< 0x08000000 */

+#define USART_ISR_TXFT                  USART_ISR_TXFT_Msk                     /*!< TXFIFO threshold Flag */

+

+/*******************  Bit definition for USART_ICR register  ******************/

+#define USART_ICR_PECF_Pos              (0U)

+#define USART_ICR_PECF_Msk              (0x1UL << USART_ICR_PECF_Pos)          /*!< 0x00000001 */

+#define USART_ICR_PECF                  USART_ICR_PECF_Msk                     /*!< Parity Error Clear Flag */

+#define USART_ICR_FECF_Pos              (1U)

+#define USART_ICR_FECF_Msk              (0x1UL << USART_ICR_FECF_Pos)          /*!< 0x00000002 */

+#define USART_ICR_FECF                  USART_ICR_FECF_Msk                     /*!< Framing Error Clear Flag */

+#define USART_ICR_NECF_Pos              (2U)

+#define USART_ICR_NECF_Msk              (0x1UL << USART_ICR_NECF_Pos)          /*!< 0x00000004 */

+#define USART_ICR_NECF                  USART_ICR_NECF_Msk                     /*!< Noise detected Clear Flag */

+#define USART_ICR_ORECF_Pos             (3U)

+#define USART_ICR_ORECF_Msk             (0x1UL << USART_ICR_ORECF_Pos)         /*!< 0x00000008 */

+#define USART_ICR_ORECF                 USART_ICR_ORECF_Msk                    /*!< OverRun Error Clear Flag */

+#define USART_ICR_IDLECF_Pos            (4U)

+#define USART_ICR_IDLECF_Msk            (0x1UL << USART_ICR_IDLECF_Pos)        /*!< 0x00000010 */

+#define USART_ICR_IDLECF                USART_ICR_IDLECF_Msk                   /*!< IDLE line detected Clear Flag */

+#define USART_ICR_TXFECF_Pos            (5U)

+#define USART_ICR_TXFECF_Msk            (0x1UL << USART_ICR_TXFECF_Pos)        /*!< 0x00000020 */

+#define USART_ICR_TXFECF                USART_ICR_TXFECF_Msk                   /*!< TXFIFO empty clear flag */

+#define USART_ICR_TCCF_Pos              (6U)

+#define USART_ICR_TCCF_Msk              (0x1UL << USART_ICR_TCCF_Pos)          /*!< 0x00000040 */

+#define USART_ICR_TCCF                  USART_ICR_TCCF_Msk                     /*!< Transmission Complete Clear Flag */

+#define USART_ICR_TCBGTCF_Pos           (7U)

+#define USART_ICR_TCBGTCF_Msk           (0x1UL << USART_ICR_TCBGTCF_Pos)       /*!< 0x00000080 */

+#define USART_ICR_TCBGTCF               USART_ICR_TCBGTCF_Msk                  /*!< Transmission complete before guard time Clear Flag */

+#define USART_ICR_LBDCF_Pos             (8U)

+#define USART_ICR_LBDCF_Msk             (0x1UL << USART_ICR_LBDCF_Pos)         /*!< 0x00000100 */

+#define USART_ICR_LBDCF                 USART_ICR_LBDCF_Msk                    /*!< LIN Break Detection Clear Flag */

+#define USART_ICR_CTSCF_Pos             (9U)

+#define USART_ICR_CTSCF_Msk             (0x1UL << USART_ICR_CTSCF_Pos)         /*!< 0x00000200 */

+#define USART_ICR_CTSCF                 USART_ICR_CTSCF_Msk                    /*!< CTS Interrupt Clear Flag */

+#define USART_ICR_RTOCF_Pos             (11U)

+#define USART_ICR_RTOCF_Msk             (0x1UL << USART_ICR_RTOCF_Pos)         /*!< 0x00000800 */

+#define USART_ICR_RTOCF                 USART_ICR_RTOCF_Msk                    /*!< Receiver Time Out Clear Flag */

+#define USART_ICR_EOBCF_Pos             (12U)

+#define USART_ICR_EOBCF_Msk             (0x1UL << USART_ICR_EOBCF_Pos)         /*!< 0x00001000 */

+#define USART_ICR_EOBCF                 USART_ICR_EOBCF_Msk                    /*!< End Of Block Clear Flag */

+#define USART_ICR_UDRCF_Pos             (13U)

+#define USART_ICR_UDRCF_Msk             (0x1UL << USART_ICR_UDRCF_Pos)         /*!< 0x00002000 */

+#define USART_ICR_UDRCF                 USART_ICR_UDRCF_Msk                    /*!< SPI slave underrun clear flag */

+#define USART_ICR_CMCF_Pos              (17U)

+#define USART_ICR_CMCF_Msk              (0x1UL << USART_ICR_CMCF_Pos)          /*!< 0x00020000 */

+#define USART_ICR_CMCF                  USART_ICR_CMCF_Msk                     /*!< Character Match Clear Flag */

+#define USART_ICR_WUCF_Pos              (20U)

+#define USART_ICR_WUCF_Msk              (0x1UL << USART_ICR_WUCF_Pos)          /*!< 0x00100000 */

+#define USART_ICR_WUCF                  USART_ICR_WUCF_Msk                     /*!< Wake Up from stop mode Clear Flag */

+

+/*******************  Bit definition for USART_RDR register  ******************/

+#define USART_RDR_RDR_Pos               (0U)

+#define USART_RDR_RDR_Msk               (0x1FFUL << USART_RDR_RDR_Pos)         /*!< 0x000001FF */

+#define USART_RDR_RDR                   USART_RDR_RDR_Msk                      /*!< RDR[8:0] bits (Receive Data value) */

+

+/*******************  Bit definition for USART_TDR register  ******************/

+#define USART_TDR_TDR_Pos               (0U)

+#define USART_TDR_TDR_Msk               (0x1FFUL << USART_TDR_TDR_Pos)         /*!< 0x000001FF */

+#define USART_TDR_TDR                   USART_TDR_TDR_Msk                      /*!< TDR[8:0] bits (Transmit Data value) */

+

+/*******************  Bit definition for USART_PRESC register  ******************/

+#define USART_PRESC_PRESCALER_Pos       (0U)

+#define USART_PRESC_PRESCALER_Msk       (0xFUL << USART_PRESC_PRESCALER_Pos)   /*!< 0x0000000F */

+#define USART_PRESC_PRESCALER           USART_PRESC_PRESCALER_Msk              /*!< PRESCALER[3:0] bits (Clock prescaler) */

+#define USART_PRESC_PRESCALER_0         (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */

+#define USART_PRESC_PRESCALER_1         (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */

+#define USART_PRESC_PRESCALER_2         (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */

+#define USART_PRESC_PRESCALER_3         (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */

+

+/******************************************************************************/

+/*                                                                            */

+/*           Single Wire Protocol Master Interface (SWPMI)                    */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for SWPMI_CR register   ********************/

+#define SWPMI_CR_RXDMA_Pos       (0U)

+#define SWPMI_CR_RXDMA_Msk       (0x1UL << SWPMI_CR_RXDMA_Pos)                 /*!< 0x00000001 */

+#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */

+#define SWPMI_CR_TXDMA_Pos       (1U)

+#define SWPMI_CR_TXDMA_Msk       (0x1UL << SWPMI_CR_TXDMA_Pos)                 /*!< 0x00000002 */

+#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */

+#define SWPMI_CR_RXMODE_Pos      (2U)

+#define SWPMI_CR_RXMODE_Msk      (0x1UL << SWPMI_CR_RXMODE_Pos)                /*!< 0x00000004 */

+#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */

+#define SWPMI_CR_TXMODE_Pos      (3U)

+#define SWPMI_CR_TXMODE_Msk      (0x1UL << SWPMI_CR_TXMODE_Pos)                /*!< 0x00000008 */

+#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */

+#define SWPMI_CR_LPBK_Pos        (4U)

+#define SWPMI_CR_LPBK_Msk        (0x1UL << SWPMI_CR_LPBK_Pos)                  /*!< 0x00000010 */

+#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */

+#define SWPMI_CR_SWPACT_Pos      (5U)

+#define SWPMI_CR_SWPACT_Msk      (0x1UL << SWPMI_CR_SWPACT_Pos)                /*!< 0x00000020 */

+#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */

+#define SWPMI_CR_DEACT_Pos       (10U)

+#define SWPMI_CR_DEACT_Msk       (0x1UL << SWPMI_CR_DEACT_Pos)                 /*!< 0x00000400 */

+#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */

+#define SWPMI_CR_SWPEN_Pos       (11U)

+#define SWPMI_CR_SWPEN_Msk       (0x1UL << SWPMI_CR_SWPEN_Pos)                 /*!< 0x00000800 */

+#define SWPMI_CR_SWPEN           SWPMI_CR_SWPEN_Msk                            /*!<Single wire protocol master transceiver enable       */

+

+/*******************  Bit definition for SWPMI_BRR register  ********************/

+#define SWPMI_BRR_BR_Pos         (0U)

+#define SWPMI_BRR_BR_Msk         (0xFFUL << SWPMI_BRR_BR_Pos)                  /*!< 0x000000FF */

+#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[7:0] bits (Bitrate prescaler) */

+

+/*******************  Bit definition for SWPMI_ISR register  ********************/

+#define SWPMI_ISR_RXBFF_Pos      (0U)

+#define SWPMI_ISR_RXBFF_Msk      (0x1UL << SWPMI_ISR_RXBFF_Pos)                /*!< 0x00000001 */

+#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */

+#define SWPMI_ISR_TXBEF_Pos      (1U)

+#define SWPMI_ISR_TXBEF_Msk      (0x1UL << SWPMI_ISR_TXBEF_Pos)                /*!< 0x00000002 */

+#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */

+#define SWPMI_ISR_RXBERF_Pos     (2U)

+#define SWPMI_ISR_RXBERF_Msk     (0x1UL << SWPMI_ISR_RXBERF_Pos)               /*!< 0x00000004 */

+#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */

+#define SWPMI_ISR_RXOVRF_Pos     (3U)

+#define SWPMI_ISR_RXOVRF_Msk     (0x1UL << SWPMI_ISR_RXOVRF_Pos)               /*!< 0x00000008 */

+#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */

+#define SWPMI_ISR_TXUNRF_Pos     (4U)

+#define SWPMI_ISR_TXUNRF_Msk     (0x1UL << SWPMI_ISR_TXUNRF_Pos)               /*!< 0x00000010 */

+#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */

+#define SWPMI_ISR_RXNE_Pos       (5U)

+#define SWPMI_ISR_RXNE_Msk       (0x1UL << SWPMI_ISR_RXNE_Pos)                 /*!< 0x00000020 */

+#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */

+#define SWPMI_ISR_TXE_Pos        (6U)

+#define SWPMI_ISR_TXE_Msk        (0x1UL << SWPMI_ISR_TXE_Pos)                  /*!< 0x00000040 */

+#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */

+#define SWPMI_ISR_TCF_Pos        (7U)

+#define SWPMI_ISR_TCF_Msk        (0x1UL << SWPMI_ISR_TCF_Pos)                  /*!< 0x00000080 */

+#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */

+#define SWPMI_ISR_SRF_Pos        (8U)

+#define SWPMI_ISR_SRF_Msk        (0x1UL << SWPMI_ISR_SRF_Pos)                  /*!< 0x00000100 */

+#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */

+#define SWPMI_ISR_SUSP_Pos       (9U)

+#define SWPMI_ISR_SUSP_Msk       (0x1UL << SWPMI_ISR_SUSP_Pos)                 /*!< 0x00000200 */

+#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */

+#define SWPMI_ISR_DEACTF_Pos     (10U)

+#define SWPMI_ISR_DEACTF_Msk     (0x1UL << SWPMI_ISR_DEACTF_Pos)               /*!< 0x00000400 */

+#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */

+#define SWPMI_ISR_RDYF_Pos       (11U)

+#define SWPMI_ISR_RDYF_Msk       (0x1UL << SWPMI_ISR_RDYF_Pos)                 /*!< 0x00000800 */

+#define SWPMI_ISR_RDYF           SWPMI_ISR_RDYF_Msk                            /*!<Transceiver ready flag          */

+

+/*******************  Bit definition for SWPMI_ICR register  ********************/

+#define SWPMI_ICR_CRXBFF_Pos     (0U)

+#define SWPMI_ICR_CRXBFF_Msk     (0x1UL << SWPMI_ICR_CRXBFF_Pos)               /*!< 0x00000001 */

+#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */

+#define SWPMI_ICR_CTXBEF_Pos     (1U)

+#define SWPMI_ICR_CTXBEF_Msk     (0x1UL << SWPMI_ICR_CTXBEF_Pos)               /*!< 0x00000002 */

+#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */

+#define SWPMI_ICR_CRXBERF_Pos    (2U)

+#define SWPMI_ICR_CRXBERF_Msk    (0x1UL << SWPMI_ICR_CRXBERF_Pos)              /*!< 0x00000004 */

+#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */

+#define SWPMI_ICR_CRXOVRF_Pos    (3U)

+#define SWPMI_ICR_CRXOVRF_Msk    (0x1UL << SWPMI_ICR_CRXOVRF_Pos)              /*!< 0x00000008 */

+#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */

+#define SWPMI_ICR_CTXUNRF_Pos    (4U)

+#define SWPMI_ICR_CTXUNRF_Msk    (0x1UL << SWPMI_ICR_CTXUNRF_Pos)              /*!< 0x00000010 */

+#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */

+#define SWPMI_ICR_CTCF_Pos       (7U)

+#define SWPMI_ICR_CTCF_Msk       (0x1UL << SWPMI_ICR_CTCF_Pos)                 /*!< 0x00000080 */

+#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */

+#define SWPMI_ICR_CSRF_Pos       (8U)

+#define SWPMI_ICR_CSRF_Msk       (0x1UL << SWPMI_ICR_CSRF_Pos)                 /*!< 0x00000100 */

+#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */

+#define SWPMI_ICR_CRDYF_Pos      (11U)

+#define SWPMI_ICR_CRDYF_Msk      (0x1UL << SWPMI_ICR_CRDYF_Pos)                /*!< 0x00000800 */

+#define SWPMI_ICR_CRDYF          SWPMI_ICR_CRDYF_Msk                           /*!<Clear transceiver ready flag         */

+

+/*******************  Bit definition for SWPMI_IER register  ********************/

+#define SWPMI_IER_RXBFIE_Pos     (0U)

+#define SWPMI_IER_RXBFIE_Msk     (0x1UL << SWPMI_IER_RXBFIE_Pos)               /*!< 0x00000001 */

+#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */

+#define SWPMI_IER_TXBEIE_Pos     (1U)

+#define SWPMI_IER_TXBEIE_Msk     (0x1UL << SWPMI_IER_TXBEIE_Pos)               /*!< 0x00000002 */

+#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */

+#define SWPMI_IER_RXBERIE_Pos    (2U)

+#define SWPMI_IER_RXBERIE_Msk    (0x1UL << SWPMI_IER_RXBERIE_Pos)              /*!< 0x00000004 */

+#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */

+#define SWPMI_IER_RXOVRIE_Pos    (3U)

+#define SWPMI_IER_RXOVRIE_Msk    (0x1UL << SWPMI_IER_RXOVRIE_Pos)              /*!< 0x00000008 */

+#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */

+#define SWPMI_IER_TXUNRIE_Pos    (4U)

+#define SWPMI_IER_TXUNRIE_Msk    (0x1UL << SWPMI_IER_TXUNRIE_Pos)              /*!< 0x00000010 */

+#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */

+#define SWPMI_IER_RIE_Pos        (5U)

+#define SWPMI_IER_RIE_Msk        (0x1UL << SWPMI_IER_RIE_Pos)                  /*!< 0x00000020 */

+#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */

+#define SWPMI_IER_TIE_Pos        (6U)

+#define SWPMI_IER_TIE_Msk        (0x1UL << SWPMI_IER_TIE_Pos)                  /*!< 0x00000040 */

+#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */

+#define SWPMI_IER_TCIE_Pos       (7U)

+#define SWPMI_IER_TCIE_Msk       (0x1UL << SWPMI_IER_TCIE_Pos)                 /*!< 0x00000080 */

+#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */

+#define SWPMI_IER_SRIE_Pos       (8U)

+#define SWPMI_IER_SRIE_Msk       (0x1UL << SWPMI_IER_SRIE_Pos)                 /*!< 0x00000100 */

+#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */

+#define SWPMI_IER_RDYIE_Pos      (11U)

+#define SWPMI_IER_RDYIE_Msk      (0x1UL << SWPMI_IER_RDYIE_Pos)                /*!< 0x00000800 */

+#define SWPMI_IER_RDYIE          SWPMI_IER_RDYIE_Msk                           /*!<Transceiver ready interrupt enable          */

+

+/*******************  Bit definition for SWPMI_RFL register  ********************/

+#define SWPMI_RFL_RFL_Pos        (0U)

+#define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */

+#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */

+#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */

+

+/*******************  Bit definition for SWPMI_TDR register  ********************/

+#define SWPMI_TDR_TD_Pos         (0U)

+#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)            /*!< 0xFFFFFFFF */

+#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */

+

+/*******************  Bit definition for SWPMI_RDR register  ********************/

+#define SWPMI_RDR_RD_Pos         (0U)

+#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)            /*!< 0xFFFFFFFF */

+#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Recive Data Register           */

+

+

+/*******************  Bit definition for SWPMI_OR register  ********************/

+#define SWPMI_OR_TBYP_Pos        (0U)

+#define SWPMI_OR_TBYP_Msk        (0x1UL << SWPMI_OR_TBYP_Pos)                  /*!< 0x00000001 */

+#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */

+#define SWPMI_OR_CLASS_Pos       (1U)

+#define SWPMI_OR_CLASS_Msk       (0x1UL << SWPMI_OR_CLASS_Pos)                 /*!< 0x00000002 */

+#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP CLASS selection */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            Window WATCHDOG                                 */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for WWDG_CR register  ********************/

+#define WWDG_CR_T_Pos           (0U)

+#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */

+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */

+#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */

+#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */

+#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */

+#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */

+#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */

+#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */

+#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */

+

+#define WWDG_CR_WDGA_Pos        (7U)

+#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */

+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */

+

+/*******************  Bit definition for WWDG_CFR register  *******************/

+#define WWDG_CFR_W_Pos          (0U)

+#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */

+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */

+#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */

+#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */

+#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */

+#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */

+#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */

+#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */

+#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */

+

+#define WWDG_CFR_EWI_Pos        (9U)

+#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */

+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */

+

+#define WWDG_CFR_WDGTB_Pos      (11U)

+#define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */

+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */

+#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000800 */

+#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00001000 */

+#define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00002000 */

+

+/*******************  Bit definition for WWDG_SR register  ********************/

+#define WWDG_SR_EWIF_Pos        (0U)

+#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */

+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                DBG                                         */

+/*                                                                            */

+/******************************************************************************/

+/*********************************  DEVICE ID  ********************************/

+#define STM32H7_DEV_ID           0x480UL

+

+/********************  Bit definition for DBGMCU_IDCODE register  *************/

+#define DBGMCU_IDCODE_DEV_ID_Pos          (0U)

+#define DBGMCU_IDCODE_DEV_ID_Msk          (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */

+#define DBGMCU_IDCODE_DEV_ID              DBGMCU_IDCODE_DEV_ID_Msk

+#define DBGMCU_IDCODE_REV_ID_Pos          (16U)

+#define DBGMCU_IDCODE_REV_ID_Msk          (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */

+#define DBGMCU_IDCODE_REV_ID              DBGMCU_IDCODE_REV_ID_Msk

+

+/********************  Bit definition for DBGMCU_CR register  *****************/

+#define DBGMCU_CR_DBG_SLEEPCD_Pos         (0U)

+#define DBGMCU_CR_DBG_SLEEPCD_Msk         (0x1UL << DBGMCU_CR_DBG_SLEEPCD_Pos) /*!< 0x00000001 */

+#define DBGMCU_CR_DBG_SLEEPCD             DBGMCU_CR_DBG_SLEEPCD_Msk

+#define DBGMCU_CR_DBG_STOPCD_Pos          (1U)

+#define DBGMCU_CR_DBG_STOPCD_Msk          (0x1UL << DBGMCU_CR_DBG_STOPCD_Pos)  /*!< 0x00000002 */

+#define DBGMCU_CR_DBG_STOPCD              DBGMCU_CR_DBG_STOPCD_Msk

+#define DBGMCU_CR_DBG_STANDBYCD_Pos       (2U)

+#define DBGMCU_CR_DBG_STANDBYCD_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYCD_Pos) /*!< 0x00000004 */

+#define DBGMCU_CR_DBG_STANDBYCD           DBGMCU_CR_DBG_STANDBYCD_Msk

+

+/* Legacy defines */

+#define DBGMCU_CR_DBG_SLEEPD1_Pos         DBGMCU_CR_DBG_SLEEPCD_Pos

+#define DBGMCU_CR_DBG_SLEEPD1_Msk         DBGMCU_CR_DBG_SLEEPCD_Msk

+#define DBGMCU_CR_DBG_SLEEPD1             DBGMCU_CR_DBG_SLEEPCD

+#define DBGMCU_CR_DBG_STOPD1_Pos          DBGMCU_CR_DBG_STOPCD_Pos

+#define DBGMCU_CR_DBG_STOPD1_Msk          DBGMCU_CR_DBG_STOPCD_Msk

+#define DBGMCU_CR_DBG_STOPD1              DBGMCU_CR_DBG_STOPCD

+#define DBGMCU_CR_DBG_STANDBYD1_Pos       DBGMCU_CR_DBG_STANDBYCD_Pos

+#define DBGMCU_CR_DBG_STANDBYD1_Msk       DBGMCU_CR_DBG_STANDBYCD_Msk

+#define DBGMCU_CR_DBG_STANDBYD1           DBGMCU_CR_DBG_STANDBYCD

+#define DBGMCU_CR_DBG_STOPSRD_Pos          (7U)

+#define DBGMCU_CR_DBG_STOPSRD_Msk          (0x1UL << DBGMCU_CR_DBG_STOPSRD_Pos)  /*!< 0x00000080 */

+#define DBGMCU_CR_DBG_STOPSRD              DBGMCU_CR_DBG_STOPSRD_Msk

+#define DBGMCU_CR_DBG_STANDBYSRD_Pos       (8U)

+#define DBGMCU_CR_DBG_STANDBYSRD_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYSRD_Pos) /*!< 0x00000100 */

+#define DBGMCU_CR_DBG_STANDBYSRD           DBGMCU_CR_DBG_STANDBYSRD_Msk

+

+/* Legacy defines */

+#define DBGMCU_CR_DBG_STOPD3_Pos          DBGMCU_CR_DBG_STOPSRD_Pos

+#define DBGMCU_CR_DBG_STOPD3_Msk          DBGMCU_CR_DBG_STOPSRD_Msk

+#define DBGMCU_CR_DBG_STOPD3              DBGMCU_CR_DBG_STOPSRD

+#define DBGMCU_CR_DBG_STANDBYD3_Pos       DBGMCU_CR_DBG_STANDBYSRD_Pos

+#define DBGMCU_CR_DBG_STANDBYD3_Msk       DBGMCU_CR_DBG_STANDBYSRD_Msk

+#define DBGMCU_CR_DBG_STANDBYD3           DBGMCU_CR_DBG_STANDBYSRD

+

+#define DBGMCU_CR_DBG_TRACECKEN_Pos       (20U)

+#define DBGMCU_CR_DBG_TRACECKEN_Msk       (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */

+#define DBGMCU_CR_DBG_TRACECKEN           DBGMCU_CR_DBG_TRACECKEN_Msk

+#define DBGMCU_CR_DBG_CKCDEN_Pos          (21U)

+#define DBGMCU_CR_DBG_CKCDEN_Msk          (0x1UL << DBGMCU_CR_DBG_CKCDEN_Pos)  /*!< 0x00200000 */

+#define DBGMCU_CR_DBG_CKCDEN              DBGMCU_CR_DBG_CKCDEN_Msk

+#define DBGMCU_CR_DBG_CKSRDEN_Pos          (22U)

+#define DBGMCU_CR_DBG_CKSRDEN_Msk          (0x1UL << DBGMCU_CR_DBG_CKSRDEN_Pos)  /*!< 0x00400000 */

+#define DBGMCU_CR_DBG_CKSRDEN              DBGMCU_CR_DBG_CKSRDEN_Msk

+

+/* Legacy defines */

+#define DBGMCU_CR_DBG_CKD1EN_Pos          DBGMCU_CR_DBG_CKCDEN_Pos

+#define DBGMCU_CR_DBG_CKD1EN_Msk          DBGMCU_CR_DBG_CKCDEN_Msk

+#define DBGMCU_CR_DBG_CKD1EN              DBGMCU_CR_DBG_CKCDEN

+#define DBGMCU_CR_DBG_CKD3EN_Pos          DBGMCU_CR_DBG_CKSRDEN_Pos

+#define DBGMCU_CR_DBG_CKD3EN_Msk          DBGMCU_CR_DBG_CKSRDEN_Msk

+#define DBGMCU_CR_DBG_CKD3EN              DBGMCU_CR_DBG_CKSRDEN

+

+#define DBGMCU_CR_DBG_TRGOEN_Pos          (28U)

+#define DBGMCU_CR_DBG_TRGOEN_Msk          (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)  /*!< 0x10000000 */

+#define DBGMCU_CR_DBG_TRGOEN              DBGMCU_CR_DBG_TRGOEN_Msk

+

+/********************  Bit definition for APB3FZ1 register  ************/

+#define DBGMCU_APB3FZ1_DBG_WWDG1_Pos      (6U)

+#define DBGMCU_APB3FZ1_DBG_WWDG1_Msk      (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB3FZ1_DBG_WWDG1          DBGMCU_APB3FZ1_DBG_WWDG1_Msk

+/********************  Bit definition for APB1LFZ1 register  ************/

+#define DBGMCU_APB1LFZ1_DBG_TIM2_Pos      (0U)

+#define DBGMCU_APB1LFZ1_DBG_TIM2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB1LFZ1_DBG_TIM2          DBGMCU_APB1LFZ1_DBG_TIM2_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM3_Pos      (1U)

+#define DBGMCU_APB1LFZ1_DBG_TIM3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB1LFZ1_DBG_TIM3          DBGMCU_APB1LFZ1_DBG_TIM3_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM4_Pos      (2U)

+#define DBGMCU_APB1LFZ1_DBG_TIM4_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */

+#define DBGMCU_APB1LFZ1_DBG_TIM4          DBGMCU_APB1LFZ1_DBG_TIM4_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM5_Pos      (3U)

+#define DBGMCU_APB1LFZ1_DBG_TIM5_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */

+#define DBGMCU_APB1LFZ1_DBG_TIM5          DBGMCU_APB1LFZ1_DBG_TIM5_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM6_Pos      (4U)

+#define DBGMCU_APB1LFZ1_DBG_TIM6_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */

+#define DBGMCU_APB1LFZ1_DBG_TIM6          DBGMCU_APB1LFZ1_DBG_TIM6_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM7_Pos      (5U)

+#define DBGMCU_APB1LFZ1_DBG_TIM7_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */

+#define DBGMCU_APB1LFZ1_DBG_TIM7          DBGMCU_APB1LFZ1_DBG_TIM7_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM12_Pos     (6U)

+#define DBGMCU_APB1LFZ1_DBG_TIM12_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB1LFZ1_DBG_TIM12         DBGMCU_APB1LFZ1_DBG_TIM12_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM13_Pos     (7U)

+#define DBGMCU_APB1LFZ1_DBG_TIM13_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB1LFZ1_DBG_TIM13         DBGMCU_APB1LFZ1_DBG_TIM13_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM14_Pos     (8U)

+#define DBGMCU_APB1LFZ1_DBG_TIM14_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */

+#define DBGMCU_APB1LFZ1_DBG_TIM14         DBGMCU_APB1LFZ1_DBG_TIM14_Msk

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos    (9U)

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1        DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C1_Pos      (21U)

+#define DBGMCU_APB1LFZ1_DBG_I2C1_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C1          DBGMCU_APB1LFZ1_DBG_I2C1_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C2_Pos      (22U)

+#define DBGMCU_APB1LFZ1_DBG_I2C2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C2          DBGMCU_APB1LFZ1_DBG_I2C2_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C3_Pos      (23U)

+#define DBGMCU_APB1LFZ1_DBG_I2C3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C3          DBGMCU_APB1LFZ1_DBG_I2C3_Msk

+

+/********************  Bit definition for APB2FZ1 register  ************/

+#define DBGMCU_APB2FZ1_DBG_TIM1_Pos       (0U)

+#define DBGMCU_APB2FZ1_DBG_TIM1_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB2FZ1_DBG_TIM1           DBGMCU_APB2FZ1_DBG_TIM1_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM8_Pos       (1U)

+#define DBGMCU_APB2FZ1_DBG_TIM8_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB2FZ1_DBG_TIM8           DBGMCU_APB2FZ1_DBG_TIM8_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM15_Pos      (16U)

+#define DBGMCU_APB2FZ1_DBG_TIM15_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB2FZ1_DBG_TIM15          DBGMCU_APB2FZ1_DBG_TIM15_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM16_Pos      (17U)

+#define DBGMCU_APB2FZ1_DBG_TIM16_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */

+#define DBGMCU_APB2FZ1_DBG_TIM16          DBGMCU_APB2FZ1_DBG_TIM16_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM17_Pos      (18U)

+#define DBGMCU_APB2FZ1_DBG_TIM17_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB2FZ1_DBG_TIM17          DBGMCU_APB2FZ1_DBG_TIM17_Msk

+/********************  Bit definition for APB4FZ1 register  ************/

+#define DBGMCU_APB4FZ1_DBG_I2C4_Pos       (7U)

+#define DBGMCU_APB4FZ1_DBG_I2C4_Msk       (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB4FZ1_DBG_I2C4           DBGMCU_APB4FZ1_DBG_I2C4_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos     (9U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM2         DBGMCU_APB4FZ1_DBG_LPTIM2_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos     (10U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM3         DBGMCU_APB4FZ1_DBG_LPTIM3_Msk

+#define DBGMCU_APB4FZ1_DBG_RTC_Pos        (16U)

+#define DBGMCU_APB4FZ1_DBG_RTC_Msk        (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB4FZ1_DBG_RTC            DBGMCU_APB4FZ1_DBG_RTC_Msk

+#define DBGMCU_APB4FZ1_DBG_IWDG1_Pos      (18U)

+#define DBGMCU_APB4FZ1_DBG_IWDG1_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB4FZ1_DBG_IWDG1          DBGMCU_APB4FZ1_DBG_IWDG1_Msk

+/******************************************************************************/

+/*                                                                            */

+/*                             RAM ECC monitoring                             */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for RAMECC_IER register  ******************/

+#define RAMECC_IER_GECCDEBWIE_Pos         (3U)

+#define RAMECC_IER_GECCDEBWIE_Msk         (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)  /*!< 0x00000008 */

+#define RAMECC_IER_GECCDEBWIE             RAMECC_IER_GECCDEBWIE_Msk             /*!< Global ECC double error on byte write (BW) interrupt enable */

+#define RAMECC_IER_GECCDEIE_Pos           (2U)

+#define RAMECC_IER_GECCDEIE_Msk           (0x1UL << RAMECC_IER_GECCDEIE_Pos)    /*!< 0x00000004 */

+#define RAMECC_IER_GECCDEIE               RAMECC_IER_GECCDEIE_Msk               /*!< Global ECC double error interrupt enable */

+#define RAMECC_IER_GECCSEIE_Pos           (1U)

+#define RAMECC_IER_GECCSEIE_Msk           (0x1UL << RAMECC_IER_GECCSEIE_Pos)    /*!< 0x00000002 */

+#define RAMECC_IER_GECCSEIE               RAMECC_IER_GECCSEIE_Msk               /*!< Global ECC single error interrupt enable */

+#define RAMECC_IER_GIE_Pos                (0U)

+#define RAMECC_IER_GIE_Msk                (0x1UL << RAMECC_IER_GIE_Pos)         /*!< 0x00000001 */

+#define RAMECC_IER_GIE                    RAMECC_IER_GIE_Msk                    /*!< Global interrupt enable */

+

+/*******************  Bit definition for RAMECC_CR register  ******************/

+#define RAMECC_CR_ECCELEN_Pos             (5U)

+#define RAMECC_CR_ECCELEN_Msk             (0x1UL << RAMECC_CR_ECCELEN_Pos)      /*!< 0x00000020 */

+#define RAMECC_CR_ECCELEN                 RAMECC_CR_ECCELEN_Msk                 /*!< ECC error latching enable */

+#define RAMECC_CR_ECCDEBWIE_Pos           (4U)

+#define RAMECC_CR_ECCDEBWIE_Msk           (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)    /*!< 0x00000010 */

+#define RAMECC_CR_ECCDEBWIE               RAMECC_CR_ECCDEBWIE_Msk               /*!< ECC double error on byte write (BW) interrupt enable */

+#define RAMECC_CR_ECCDEIE_Pos             (3U)

+#define RAMECC_CR_ECCDEIE_Msk             (0x1UL << RAMECC_CR_ECCDEIE_Pos)      /*!< 0x00000008 */

+#define RAMECC_CR_ECCDEIE                 RAMECC_CR_ECCDEIE_Msk                 /*!< ECC double error interrupt enable */

+#define RAMECC_CR_ECCSEIE_Pos             (2U)

+#define RAMECC_CR_ECCSEIE_Msk             (0x1UL << RAMECC_CR_ECCSEIE_Pos)      /*!< 0x00000004 */

+#define RAMECC_CR_ECCSEIE                 RAMECC_CR_ECCSEIE_Msk                 /*!< ECC single error interrupt enable */

+

+/*******************  Bit definition for RAMECC_SR register  ******************/

+#define RAMECC_SR_DEBWDF_Pos             (2U)

+#define RAMECC_SR_DEBWDF_Msk             (0x1UL << RAMECC_SR_DEBWDF_Pos)        /*!< 0x00000004 */

+#define RAMECC_SR_DEBWDF                 RAMECC_SR_DEBWDF_Msk                   /*!< ECC double error on byte write (BW) detected flag */

+#define RAMECC_SR_DEDF_Pos               (1U)

+#define RAMECC_SR_DEDF_Msk               (0x1UL << RAMECC_SR_DEDF_Pos)          /*!< 0x00000002 */

+#define RAMECC_SR_DEDF                   RAMECC_SR_DEDF_Msk                     /*!< ECC double error detected flag */

+#define RAMECC_SR_SEDCF_Pos              (0U)

+#define RAMECC_SR_SEDCF_Msk              (0x1UL << RAMECC_SR_SEDCF_Pos)         /*!< 0x00000001 */

+#define RAMECC_SR_SEDCF                  RAMECC_SR_SEDCF_Msk                    /*!< ECC single error detected and corrected flag */

+

+/******************  Bit definition for RAMECC_FAR register  ******************/

+#define RAMECC_FAR_FADD_Pos              (0U)

+#define RAMECC_FAR_FADD_Msk              (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)  /*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FADD                  RAMECC_FAR_FADD_Msk                    /*!< ECC error failing address */

+

+/******************  Bit definition for RAMECC_FDRL register  *****************/

+#define RAMECC_FAR_FDATAL_Pos            (0U)

+#define RAMECC_FAR_FDATAL_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FDATAL                RAMECC_FAR_FDATAL_Msk                  /*!< ECC error failing address */

+

+/******************  Bit definition for RAMECC_FDRH register  *****************/

+#define RAMECC_FAR_FDATAH_Pos            (0U)

+#define RAMECC_FAR_FDATAH_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FDATAH                RAMECC_FAR_FDATAH_Msk                  /* Failing data high (64-bit memory) */

+

+/*****************  Bit definition for RAMECC_FECR register  ******************/

+#define RAMECC_FECR_FEC_Pos              (0U)

+#define RAMECC_FECR_FEC_Msk              (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)  /*!< 0xFFFFFFFF */

+#define RAMECC_FECR_FEC                  RAMECC_FECR_FEC_Msk                    /*!< Failing error code */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                MDIOS                                        */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for MDIOS_CR register  *******************/

+#define MDIOS_CR_EN_Pos                (0U)

+#define MDIOS_CR_EN_Msk                (0x1UL << MDIOS_CR_EN_Pos)              /*!< 0x00000001 */

+#define MDIOS_CR_EN                    MDIOS_CR_EN_Msk                         /*!<  MDIOS slave peripheral enable */

+#define MDIOS_CR_WRIE_Pos              (1U)

+#define MDIOS_CR_WRIE_Msk              (0x1UL << MDIOS_CR_WRIE_Pos)            /*!< 0x00000002 */

+#define MDIOS_CR_WRIE                  MDIOS_CR_WRIE_Msk                       /*!<  MDIOS slave register write interrupt enable. */

+#define MDIOS_CR_RDIE_Pos              (2U)

+#define MDIOS_CR_RDIE_Msk              (0x1UL << MDIOS_CR_RDIE_Pos)            /*!< 0x00000004 */

+#define MDIOS_CR_RDIE                  MDIOS_CR_RDIE_Msk                       /*!<  MDIOS slave register read interrupt enable. */

+#define MDIOS_CR_EIE_Pos               (3U)

+#define MDIOS_CR_EIE_Msk               (0x1UL << MDIOS_CR_EIE_Pos)             /*!< 0x00000008 */

+#define MDIOS_CR_EIE                   MDIOS_CR_EIE_Msk                        /*!<  MDIOS slave register error interrupt enable. */

+#define MDIOS_CR_DPC_Pos               (7U)

+#define MDIOS_CR_DPC_Msk               (0x1UL << MDIOS_CR_DPC_Pos)             /*!< 0x00000080 */

+#define MDIOS_CR_DPC                   MDIOS_CR_DPC_Msk                        /*!<  MDIOS slave disable preamble check. */

+#define MDIOS_CR_PORT_ADDRESS_Pos      (8U)

+#define MDIOS_CR_PORT_ADDRESS_Msk      (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)   /*!< 0x00001F00 */

+#define MDIOS_CR_PORT_ADDRESS          MDIOS_CR_PORT_ADDRESS_Msk               /*!<  MDIOS slave port address mask. */

+#define MDIOS_CR_PORT_ADDRESS_0        (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000100 */

+#define MDIOS_CR_PORT_ADDRESS_1        (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000200 */

+#define MDIOS_CR_PORT_ADDRESS_2        (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000400 */

+#define MDIOS_CR_PORT_ADDRESS_3        (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000800 */

+#define MDIOS_CR_PORT_ADDRESS_4        (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001000 */

+

+/********************  Bit definition for MDIOS_SR register  *******************/

+#define MDIOS_SR_PERF_Pos              (0U)

+#define MDIOS_SR_PERF_Msk              (0x1UL << MDIOS_SR_PERF_Pos)            /*!< 0x00000001 */

+#define MDIOS_SR_PERF                  MDIOS_SR_PERF_Msk                       /*!<  MDIOS slave turnaround error flag*/

+#define MDIOS_SR_SERF_Pos              (1U)

+#define MDIOS_SR_SERF_Msk              (0x1UL << MDIOS_SR_SERF_Pos)            /*!< 0x00000002 */

+#define MDIOS_SR_SERF                  MDIOS_SR_SERF_Msk                       /*!<  MDIOS slave start error flag */

+#define MDIOS_SR_TERF_Pos              (2U)

+#define MDIOS_SR_TERF_Msk              (0x1UL << MDIOS_SR_TERF_Pos)            /*!< 0x00000004 */

+#define MDIOS_SR_TERF                  MDIOS_SR_TERF_Msk                       /*!<  MDIOS slave preamble error flag */

+

+/********************  Bit definition for MDIOS_CLRFR register  *******************/

+#define MDIOS_SR_CPERF_Pos             (0U)

+#define MDIOS_SR_CPERF_Msk             (0x1UL << MDIOS_SR_CPERF_Pos)           /*!< 0x00000001 */

+#define MDIOS_SR_CPERF                 MDIOS_SR_CPERF_Msk                      /*!<  MDIOS slave Clear the turnaround error flag */

+#define MDIOS_SR_CSERF_Pos             (1U)

+#define MDIOS_SR_CSERF_Msk             (0x1UL << MDIOS_SR_CSERF_Pos)           /*!< 0x00000002 */

+#define MDIOS_SR_CSERF                 MDIOS_SR_CSERF_Msk                      /*!<  MDIOS slave Clear the start error flag */

+#define MDIOS_SR_CTERF_Pos             (2U)

+#define MDIOS_SR_CTERF_Msk             (0x1UL << MDIOS_SR_CTERF_Pos)           /*!< 0x00000004 */

+#define MDIOS_SR_CTERF                 MDIOS_SR_CTERF_Msk                      /*!<  MDIOS slave Clear the preamble error flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                       USB_OTG                              */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/

+#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)

+#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */

+#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */

+#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)

+#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */

+#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */

+#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)

+#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */

+#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */

+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)

+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */

+#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */

+#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)

+#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */

+#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */

+#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)

+#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */

+#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */

+#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)

+#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */

+#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */

+#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)

+#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */

+#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */

+#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)

+#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */

+#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */

+#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)

+#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */

+#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */

+#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)

+#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */

+#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */

+#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)

+#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */

+#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */

+#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)

+#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */

+#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */

+#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)

+#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */

+#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */

+#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)

+#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */

+#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */

+#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)

+#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */

+#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */

+#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)

+#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */

+#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */

+#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)

+#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */

+#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */

+

+/********************  Bit definition forUSB_OTG_HCFG register  ********************/

+

+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)

+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */

+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */

+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)

+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */

+

+/********************  Bit definition forUSB_OTG_DCFG register  ********************/

+

+#define USB_OTG_DCFG_DSPD_Pos                    (0U)

+#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */

+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */

+#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */

+#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)

+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */

+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */

+

+#define USB_OTG_DCFG_DAD_Pos                     (4U)

+#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */

+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */

+#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */

+#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */

+#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */

+#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */

+#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */

+#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */

+#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */

+

+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)

+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */

+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */

+#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */

+#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */

+

+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)

+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */

+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */

+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */

+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */

+

+/********************  Bit definition forUSB_OTG_PCGCR register  ********************/

+#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)

+#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */

+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */

+#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)

+#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */

+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */

+#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)

+#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */

+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */

+

+/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/

+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)

+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */

+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */

+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)

+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */

+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */

+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)

+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */

+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */

+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)

+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */

+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */

+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)

+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */

+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */

+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)

+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */

+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */

+

+/********************  Bit definition forUSB_OTG_DCTL register  ********************/

+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)

+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */

+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */

+#define USB_OTG_DCTL_SDIS_Pos                    (1U)

+#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */

+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */

+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)

+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */

+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */

+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)

+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */

+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */

+

+#define USB_OTG_DCTL_TCTL_Pos                    (4U)

+#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */

+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */

+#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */

+#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */

+#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */

+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)

+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */

+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */

+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)

+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */

+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */

+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)

+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */

+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */

+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)

+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */

+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */

+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)

+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */

+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */

+

+/********************  Bit definition forUSB_OTG_HFIR register  ********************/

+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)

+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */

+

+/********************  Bit definition forUSB_OTG_HFNUM register  ********************/

+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)

+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */

+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)

+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */

+

+/********************  Bit definition forUSB_OTG_DSTS register  ********************/

+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)

+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */

+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */

+

+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)

+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */

+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */

+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */

+#define USB_OTG_DSTS_EERR_Pos                    (3U)

+#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */

+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */

+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)

+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */

+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */

+

+/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/

+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)

+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */

+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */

+

+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)

+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */

+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */

+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */

+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */

+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */

+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */

+#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */

+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)

+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */

+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */

+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)

+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */

+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */

+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)

+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */

+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */

+

+/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/

+

+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)

+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */

+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */

+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */

+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */

+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */

+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)

+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */

+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */

+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)

+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */

+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */

+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)

+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */

+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */

+

+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)

+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */

+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */

+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */

+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */

+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */

+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */

+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)

+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */

+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */

+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)

+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */

+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */

+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)

+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */

+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */

+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)

+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */

+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */

+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)

+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */

+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */

+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)

+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */

+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */

+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)

+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */

+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */

+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)

+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */

+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */

+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)

+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */

+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */

+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)

+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */

+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */

+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)

+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */

+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */

+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)

+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */

+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */

+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)

+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */

+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */

+

+/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/

+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)

+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */

+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */

+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)

+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */

+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */

+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)

+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */

+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */

+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)

+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */

+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */

+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)

+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */

+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */

+

+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)

+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */

+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */

+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */

+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */

+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */

+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */

+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */

+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)

+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */

+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */

+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)

+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */

+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */

+

+/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/

+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)

+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */

+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)

+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */

+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)

+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */

+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)

+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */

+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)

+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */

+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)

+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */

+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)

+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */

+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)

+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */

+

+/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/

+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)

+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */

+

+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)

+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */

+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */

+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */

+

+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)

+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */

+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */

+

+/********************  Bit definition forUSB_OTG_HAINT register  ********************/

+#define USB_OTG_HAINT_HAINT_Pos                  (0U)

+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */

+

+/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/

+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)

+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */

+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)

+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */

+#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)

+#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */

+#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask               */

+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)

+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */

+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)

+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */

+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)

+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */

+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)

+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */

+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)

+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */

+#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)

+#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */

+#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)

+#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask               */

+#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)

+#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask               */

+#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)

+#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                */

+

+/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/

+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)

+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */

+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */

+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)

+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */

+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */

+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)

+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */

+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */

+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)

+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */

+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */

+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)

+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */

+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */

+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)

+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */

+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */

+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)

+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */

+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */

+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)

+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */

+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */

+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)

+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */

+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */

+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)

+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */

+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */

+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)

+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */

+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */

+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)

+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */

+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */

+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)

+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */

+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */

+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)

+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */

+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */

+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)

+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */

+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */

+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)

+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */

+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */

+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)

+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */

+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */

+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)

+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */

+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */

+#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)

+#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */

+#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */

+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)

+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */

+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */

+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)

+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */

+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */

+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)

+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */

+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */

+#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)

+#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */

+#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */

+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)

+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */

+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */

+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)

+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */

+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */

+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)

+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */

+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */

+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)

+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */

+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */

+

+/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/

+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)

+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */

+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */

+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)

+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */

+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */

+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)

+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */

+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */

+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)

+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */

+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */

+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)

+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */

+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */

+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)

+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */

+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */

+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)

+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */

+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */

+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)

+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */

+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */

+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)

+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */

+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */

+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)

+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */

+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */

+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)

+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */

+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */

+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)

+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */

+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */

+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)

+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */

+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */

+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)

+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */

+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */

+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)

+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */

+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */

+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)

+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */

+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */

+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)

+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */

+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */

+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)

+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */

+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */

+#define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)

+#define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */

+#define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */

+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)

+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */

+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */

+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)

+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */

+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */

+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)

+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */

+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */

+#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)

+#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */

+#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */

+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)

+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */

+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */

+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)

+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */

+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */

+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)

+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */

+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */

+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)

+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */

+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */

+

+/********************  Bit definition forUSB_OTG_DAINT register  ********************/

+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)

+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */

+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)

+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */

+

+/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/

+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)

+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */

+

+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/

+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)

+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */

+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */

+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)

+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */

+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */

+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)

+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */

+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */

+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)

+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */

+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */

+

+/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/

+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)

+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */

+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)

+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */

+

+/********************  Bit definition for OTG register  ********************/

+

+#define USB_OTG_CHNUM_Pos                        (0U)

+#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)  /*!< 0x0000000F */

+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */

+#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */

+#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */

+#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */

+#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */

+#define USB_OTG_BCNT_Pos                         (4U)

+#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */

+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */

+

+#define USB_OTG_DPID_Pos                         (15U)

+#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)   /*!< 0x00018000 */

+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */

+#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */

+#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */

+

+#define USB_OTG_PKTSTS_Pos                       (17U)

+#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */

+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */

+#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */

+#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */

+#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */

+#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */

+

+#define USB_OTG_EPNUM_Pos                        (0U)

+#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)  /*!< 0x0000000F */

+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */

+#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */

+#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */

+#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */

+#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */

+

+#define USB_OTG_FRMNUM_Pos                       (21U)

+#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */

+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */

+#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */

+#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */

+#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */

+#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */

+

+/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/

+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)

+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/

+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)

+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */

+

+/********************  Bit definition for OTG register  ********************/

+#define USB_OTG_NPTXFSA_Pos                      (0U)

+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */

+#define USB_OTG_NPTXFD_Pos                       (16U)

+#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */

+#define USB_OTG_TX0FSA_Pos                       (0U)

+#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */

+#define USB_OTG_TX0FD_Pos                        (16U)

+#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */

+

+/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/

+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)

+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */

+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */

+

+/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/

+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)

+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */

+

+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)

+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */

+

+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)

+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/

+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)

+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */

+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */

+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)

+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */

+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */

+

+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)

+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */

+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */

+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */

+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)

+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */

+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */

+

+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)

+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */

+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */

+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)

+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */

+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */

+

+/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */

+

+/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/

+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)

+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */

+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */

+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)

+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */

+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */

+

+/********************  Bit definition forUSB_OTG_GCCFG register  ********************/

+#define USB_OTG_GCCFG_DCDET_Pos                  (0U)

+#define USB_OTG_GCCFG_DCDET_Msk                  (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */

+#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */

+#define USB_OTG_GCCFG_PDET_Pos                   (1U)

+#define USB_OTG_GCCFG_PDET_Msk                   (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */

+#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */

+#define USB_OTG_GCCFG_SDET_Pos                   (2U)

+#define USB_OTG_GCCFG_SDET_Msk                   (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */

+#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */

+#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)

+#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */

+#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */

+#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)

+#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */

+#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */

+#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)

+#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */

+#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */

+#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)

+#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */

+#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/

+#define USB_OTG_GCCFG_PDEN_Pos                   (19U)

+#define USB_OTG_GCCFG_PDEN_Msk                   (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */

+#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/

+#define USB_OTG_GCCFG_SDEN_Pos                   (20U)

+#define USB_OTG_GCCFG_SDEN_Msk                   (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */

+#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */

+#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)

+#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */

+#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */

+

+/********************  Bit definition forUSB_OTG_GPWRDN) register  ********************/

+#define USB_OTG_GPWRDN_ADPMEN_Pos                (0U)

+#define USB_OTG_GPWRDN_ADPMEN_Msk                (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */

+#define USB_OTG_GPWRDN_ADPMEN                    USB_OTG_GPWRDN_ADPMEN_Msk     /*!< ADP module enable */

+#define USB_OTG_GPWRDN_ADPIF_Pos                 (23U)

+#define USB_OTG_GPWRDN_ADPIF_Msk                 (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */

+#define USB_OTG_GPWRDN_ADPIF                     USB_OTG_GPWRDN_ADPIF_Msk      /*!< ADP Interrupt flag */

+

+/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/

+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)

+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */

+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)

+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */

+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */

+

+/********************  Bit definition forUSB_OTG_CID register  ********************/

+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)

+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */

+

+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/

+#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)

+#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */

+#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */

+#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)

+#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */

+#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */

+#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)

+#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */

+#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */

+#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)

+#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */

+#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */

+#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)

+#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */

+#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */

+#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)

+#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */

+#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */

+#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)

+#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */

+#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */

+#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)

+#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */

+#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */

+#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)

+#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */

+#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */

+#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)

+#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */

+#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */

+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)

+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */

+#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */

+#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)

+#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */

+#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */

+#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)

+#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */

+#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */

+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)

+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */

+#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */

+#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)

+#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */

+#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */

+

+/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/

+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)

+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */

+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)

+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */

+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)

+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */

+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)

+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */

+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)

+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */

+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)

+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */

+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)

+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */

+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)

+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */

+

+/********************  Bit definition forUSB_OTG_HPRT register  ********************/

+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)

+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */

+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */

+#define USB_OTG_HPRT_PCDET_Pos                   (1U)

+#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */

+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */

+#define USB_OTG_HPRT_PENA_Pos                    (2U)

+#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */

+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */

+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)

+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */

+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */

+#define USB_OTG_HPRT_POCA_Pos                    (4U)

+#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */

+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */

+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)

+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */

+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */

+#define USB_OTG_HPRT_PRES_Pos                    (6U)

+#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */

+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume   */

+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)

+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */

+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend  */

+#define USB_OTG_HPRT_PRST_Pos                    (8U)

+#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */

+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset    */

+

+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)

+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */

+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */

+#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */

+#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */

+#define USB_OTG_HPRT_PPWR_Pos                    (12U)

+#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */

+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */

+

+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)

+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */

+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */

+#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */

+#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */

+#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */

+#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */

+

+#define USB_OTG_HPRT_PSPD_Pos                    (17U)

+#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */

+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */

+#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */

+#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */

+

+/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/

+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)

+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)

+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)

+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */

+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)

+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */

+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)

+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */

+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)

+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */

+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)

+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)

+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)

+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)

+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */

+

+/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/

+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)

+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */

+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)

+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/

+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)

+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */

+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)

+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */

+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */

+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)

+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */

+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */

+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)

+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */

+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */

+

+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)

+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */

+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */

+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)

+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */

+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */

+

+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)

+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */

+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */

+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */

+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */

+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */

+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */

+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)

+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */

+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */

+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)

+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */

+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */

+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)

+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */

+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)

+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */

+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)

+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */

+

+/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/

+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)

+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */

+

+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)

+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */

+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */

+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */

+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */

+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */

+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */

+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)

+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */

+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */

+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)

+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */

+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */

+

+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)

+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */

+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */

+

+#define USB_OTG_HCCHAR_MC_Pos                    (20U)

+#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */

+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */

+#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */

+#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */

+

+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)

+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */

+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */

+#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */

+#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */

+#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */

+#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */

+#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */

+#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */

+#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */

+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)

+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */

+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)

+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */

+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)

+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */

+

+/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/

+

+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)

+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */

+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */

+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */

+

+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)

+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */

+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */

+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */

+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */

+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */

+

+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)

+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */

+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */

+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */

+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */

+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)

+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */

+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */

+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)

+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */

+

+/********************  Bit definition forUSB_OTG_HCINT register  ********************/

+#define USB_OTG_HCINT_XFRC_Pos                   (0U)

+#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */

+#define USB_OTG_HCINT_CHH_Pos                    (1U)

+#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */

+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)

+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */

+#define USB_OTG_HCINT_STALL_Pos                  (3U)

+#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */

+#define USB_OTG_HCINT_NAK_Pos                    (4U)

+#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */

+#define USB_OTG_HCINT_ACK_Pos                    (5U)

+#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */

+#define USB_OTG_HCINT_NYET_Pos                   (6U)

+#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */

+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */

+#define USB_OTG_HCINT_TXERR_Pos                  (7U)

+#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */

+#define USB_OTG_HCINT_BBERR_Pos                  (8U)

+#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */

+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)

+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */

+#define USB_OTG_HCINT_DTERR_Pos                  (10U)

+#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */

+

+/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/

+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)

+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */

+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)

+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */

+#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)

+#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */

+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)

+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */

+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)

+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */

+#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)

+#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */

+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)

+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */

+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)

+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */

+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */

+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)

+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */

+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)

+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */

+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)

+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */

+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */

+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)

+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */

+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */

+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)

+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */

+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */

+

+/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/

+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)

+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */

+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)

+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */

+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)

+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */

+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)

+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */

+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)

+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */

+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)

+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */

+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)

+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */

+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */

+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)

+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */

+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)

+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */

+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)

+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */

+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)

+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */

+

+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/

+

+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)

+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */

+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)

+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */

+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)

+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */

+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */

+/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/

+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)

+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */

+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)

+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */

+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)

+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */

+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)

+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */

+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */

+#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */

+#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/

+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)

+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */

+

+/********************  Bit definition forUSB_OTG_HCDMA register  ********************/

+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)

+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */

+

+/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/

+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)

+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */

+

+/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/

+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)

+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */

+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)

+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/

+

+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)

+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */

+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)

+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */

+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */

+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)

+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */

+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */

+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)

+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */

+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)

+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */

+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */

+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)

+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */

+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */

+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)

+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */

+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */

+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)

+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */

+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */

+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)

+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */

+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */

+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)

+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */

+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)

+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */

+

+/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/

+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)

+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */

+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)

+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */

+#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)

+#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */

+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)

+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */

+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)

+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */

+#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)

+#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< OUT Status Phase Received interrupt */

+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)

+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */

+#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)

+#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */

+#define USB_OTG_DOEPINT_BNA_Pos                  (9U)

+#define USB_OTG_DOEPINT_BNA_Msk                  (0x1UL << USB_OTG_DOEPINT_BNA_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPINT_BNA                      USB_OTG_DOEPINT_BNA_Msk   /*!< Buffer not available interrupt */

+#define USB_OTG_DOEPINT_BERR_Pos                 (12U)

+#define USB_OTG_DOEPINT_BERR_Msk                 (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPINT_BERR                      USB_OTG_DOEPINT_BERR_Msk   /*!< Babble error interrupt */

+#define USB_OTG_DOEPINT_NAK_Pos                  (13U)

+#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */

+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)

+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */

+#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)

+#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */

+#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */

+

+/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/

+

+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)

+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */

+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)

+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */

+

+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)

+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */

+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */

+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */

+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition for PCGCCTL register  ********************/

+#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)

+#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */

+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */

+#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)

+#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */

+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */

+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)

+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */

+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/** @addtogroup Exported_macros

+  * @{

+  */

+

+/******************************* ADC Instances ********************************/

+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \

+                                       ((INSTANCE) == ADC2))

+

+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)

+

+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)

+

+/******************************** COMP Instances ******************************/

+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \

+                                       ((INSTANCE) == COMP2))

+

+#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)

+/******************** COMP Instances with window mode capability **************/

+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)

+

+/******************************** DTS Instances ******************************/

+#define IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS)

+

+/******************************* CRC Instances ********************************/

+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

+

+/******************************* DAC Instances ********************************/

+#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1)|| \

+                                       ((INSTANCE) == DAC2))

+/******************************* DCMI Instances *******************************/

+#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)

+

+/******************************* DELAYBLOCK Instances *******************************/

+#define IS_DLYB_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DLYB_SDMMC1) || \

+                                         ((INSTANCE) == DLYB_SDMMC2) || \

+                                         ((INSTANCE) == DLYB_OCTOSPI1) || \

+                                         ((INSTANCE) == DLYB_OCTOSPI2) )

+/****************************** DFSDM Instances *******************************/

+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \

+                                         ((INSTANCE) == DFSDM1_Filter1) || \

+                                         ((INSTANCE) == DFSDM1_Filter2) || \

+                                         ((INSTANCE) == DFSDM1_Filter3) || \

+                                         ((INSTANCE) == DFSDM1_Filter4) || \

+                                         ((INSTANCE) == DFSDM1_Filter5) || \

+                                         ((INSTANCE) == DFSDM1_Filter6) || \

+                                         ((INSTANCE) == DFSDM1_Filter7) || \

+                                         ((INSTANCE) == DFSDM2_Filter0))

+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \

+                                                 ((INSTANCE) == DFSDM1_Channel1) || \

+                                                 ((INSTANCE) == DFSDM1_Channel2) || \

+                                                 ((INSTANCE) == DFSDM1_Channel3) || \

+                                                 ((INSTANCE) == DFSDM1_Channel4) || \

+                                                 ((INSTANCE) == DFSDM1_Channel5) || \

+                                                 ((INSTANCE) == DFSDM1_Channel6) || \

+                                                 ((INSTANCE) == DFSDM1_Channel7) || \

+                                                 ((INSTANCE) == DFSDM2_Channel0) || \

+                                                 ((INSTANCE) == DFSDM2_Channel1))

+/****************************** RAMECC Instances ******************************/

+#define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC_Monitor1)   || \

+                                                  ((INSTANCE) == RAMECC_Monitor2)   || \

+                                                  ((INSTANCE) == RAMECC_Monitor3))

+

+/******************************** DMA Instances *******************************/

+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \

+                                       ((INSTANCE) == DMA1_Stream1)   || \

+                                       ((INSTANCE) == DMA1_Stream2)   || \

+                                       ((INSTANCE) == DMA1_Stream3)   || \

+                                       ((INSTANCE) == DMA1_Stream4)   || \

+                                       ((INSTANCE) == DMA1_Stream5)   || \

+                                       ((INSTANCE) == DMA1_Stream6)   || \

+                                       ((INSTANCE) == DMA1_Stream7)   || \

+                                       ((INSTANCE) == DMA2_Stream0)   || \

+                                       ((INSTANCE) == DMA2_Stream1)   || \

+                                       ((INSTANCE) == DMA2_Stream2)   || \

+                                       ((INSTANCE) == DMA2_Stream3)   || \

+                                       ((INSTANCE) == DMA2_Stream4)   || \

+                                       ((INSTANCE) == DMA2_Stream5)   || \

+                                       ((INSTANCE) == DMA2_Stream6)   || \

+                                       ((INSTANCE) == DMA2_Stream7)   || \

+                                       ((INSTANCE) == BDMA1_Channel0) || \

+                                       ((INSTANCE) == BDMA1_Channel1) || \

+                                       ((INSTANCE) == BDMA1_Channel2) || \

+                                       ((INSTANCE) == BDMA1_Channel3) || \

+                                       ((INSTANCE) == BDMA1_Channel4) || \

+                                       ((INSTANCE) == BDMA1_Channel5) || \

+                                       ((INSTANCE) == BDMA1_Channel6) || \

+                                       ((INSTANCE) == BDMA1_Channel7) || \

+                                       ((INSTANCE) == BDMA2_Channel0) || \

+                                       ((INSTANCE) == BDMA2_Channel1) || \

+                                       ((INSTANCE) == BDMA2_Channel2) || \

+                                       ((INSTANCE) == BDMA2_Channel3) || \

+                                       ((INSTANCE) == BDMA2_Channel4) || \

+                                       ((INSTANCE) == BDMA2_Channel5) || \

+                                       ((INSTANCE) == BDMA2_Channel6) || \

+                                       ((INSTANCE) == BDMA2_Channel7))

+

+/****************************** BDMA CHANNEL Instances ***************************/

+#define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA1_Channel0) || \

+                                            ((INSTANCE) == BDMA1_Channel1) || \

+                                            ((INSTANCE) == BDMA1_Channel2) || \

+                                            ((INSTANCE) == BDMA1_Channel3) || \

+                                            ((INSTANCE) == BDMA1_Channel4) || \

+                                            ((INSTANCE) == BDMA1_Channel5) || \

+                                            ((INSTANCE) == BDMA1_Channel6) || \

+                                            ((INSTANCE) == BDMA1_Channel7) || \

+                                            ((INSTANCE) == BDMA2_Channel0) || \

+                                            ((INSTANCE) == BDMA2_Channel1) || \

+                                            ((INSTANCE) == BDMA2_Channel2) || \

+                                            ((INSTANCE) == BDMA2_Channel3) || \

+                                            ((INSTANCE) == BDMA2_Channel4) || \

+                                            ((INSTANCE) == BDMA2_Channel5) || \

+                                            ((INSTANCE) == BDMA2_Channel6) || \

+                                            ((INSTANCE) == BDMA2_Channel7))

+

+/****************************** DMA DMAMUX ALL Instances ***************************/

+#define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)    || \

+                                               ((INSTANCE) == DMA1_Stream1)    || \

+                                               ((INSTANCE) == DMA1_Stream2)    || \

+                                               ((INSTANCE) == DMA1_Stream3)    || \

+                                               ((INSTANCE) == DMA1_Stream4)    || \

+                                               ((INSTANCE) == DMA1_Stream5)    || \

+                                               ((INSTANCE) == DMA1_Stream6)    || \

+                                               ((INSTANCE) == DMA1_Stream7)    || \

+                                               ((INSTANCE) == DMA2_Stream0)    || \

+                                               ((INSTANCE) == DMA2_Stream1)    || \

+                                               ((INSTANCE) == DMA2_Stream2)    || \

+                                               ((INSTANCE) == DMA2_Stream3)    || \

+                                               ((INSTANCE) == DMA2_Stream4)    || \

+                                               ((INSTANCE) == DMA2_Stream5)    || \

+                                               ((INSTANCE) == DMA2_Stream6)    || \

+                                               ((INSTANCE) == DMA2_Stream7)    || \

+                                               ((INSTANCE) == BDMA2_Channel0)  || \

+                                               ((INSTANCE) == BDMA2_Channel1)  || \

+                                               ((INSTANCE) == BDMA2_Channel2)  || \

+                                               ((INSTANCE) == BDMA2_Channel3)  || \

+                                               ((INSTANCE) == BDMA2_Channel4)  || \

+                                               ((INSTANCE) == BDMA2_Channel5)  || \

+                                               ((INSTANCE) == BDMA2_Channel6)  || \

+                                               ((INSTANCE) == BDMA2_Channel7))

+

+/****************************** BDMA DMAMUX Instances ***************************/

+#define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == BDMA2_Channel0) || \

+                                                    ((INSTANCE) == BDMA2_Channel1) || \

+                                                    ((INSTANCE) == BDMA2_Channel2) || \

+                                                    ((INSTANCE) == BDMA2_Channel3) || \

+                                                    ((INSTANCE) == BDMA2_Channel4) || \

+                                                    ((INSTANCE) == BDMA2_Channel5) || \

+                                                    ((INSTANCE) == BDMA2_Channel6) || \

+                                                    ((INSTANCE) == BDMA2_Channel7))

+

+/****************************** DMA STREAM Instances ***************************/

+#define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \

+                                          ((INSTANCE) == DMA1_Stream1)   || \

+                                          ((INSTANCE) == DMA1_Stream2)   || \

+                                          ((INSTANCE) == DMA1_Stream3)   || \

+                                          ((INSTANCE) == DMA1_Stream4)   || \

+                                          ((INSTANCE) == DMA1_Stream5)   || \

+                                          ((INSTANCE) == DMA1_Stream6)   || \

+                                          ((INSTANCE) == DMA1_Stream7)   || \

+                                          ((INSTANCE) == DMA2_Stream0)   || \

+                                          ((INSTANCE) == DMA2_Stream1)   || \

+                                          ((INSTANCE) == DMA2_Stream2)   || \

+                                          ((INSTANCE) == DMA2_Stream3)   || \

+                                          ((INSTANCE) == DMA2_Stream4)   || \

+                                          ((INSTANCE) == DMA2_Stream5)   || \

+                                          ((INSTANCE) == DMA2_Stream6)   || \

+                                          ((INSTANCE) == DMA2_Stream7))

+

+/****************************** DMA DMAMUX Instances ***************************/

+#define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)   || \

+                                                  ((INSTANCE) == DMA1_Stream1)   || \

+                                                  ((INSTANCE) == DMA1_Stream2)   || \

+                                                  ((INSTANCE) == DMA1_Stream3)   || \

+                                                  ((INSTANCE) == DMA1_Stream4)   || \

+                                                  ((INSTANCE) == DMA1_Stream5)   || \

+                                                  ((INSTANCE) == DMA1_Stream6)   || \

+                                                  ((INSTANCE) == DMA1_Stream7)   || \

+                                                  ((INSTANCE) == DMA2_Stream0)   || \

+                                                  ((INSTANCE) == DMA2_Stream1)   || \

+                                                  ((INSTANCE) == DMA2_Stream2)   || \

+                                                  ((INSTANCE) == DMA2_Stream3)   || \

+                                                  ((INSTANCE) == DMA2_Stream4)   || \

+                                                  ((INSTANCE) == DMA2_Stream5)   || \

+                                                  ((INSTANCE) == DMA2_Stream6)   || \

+                                                  ((INSTANCE) == DMA2_Stream7))

+

+/******************************** DMA Request Generator Instances **************/

+#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator1) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator2) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator3) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator4) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator5) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator6) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator7) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator0) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator1) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator2) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator3) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator4) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator5) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator6) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator7))

+

+/******************************* DMA2D Instances *******************************/

+#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)

+

+/****************************** PSSI Instance *********************************/

+#define IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI)

+

+/******************************** MDMA Request Generator Instances **************/

+#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0)  || \

+                                               ((INSTANCE) == MDMA_Channel1)  || \

+                                               ((INSTANCE) == MDMA_Channel2)  || \

+                                               ((INSTANCE) == MDMA_Channel3)  || \

+                                               ((INSTANCE) == MDMA_Channel4)  || \

+                                               ((INSTANCE) == MDMA_Channel5)  || \

+                                               ((INSTANCE) == MDMA_Channel6)  || \

+                                               ((INSTANCE) == MDMA_Channel7)  || \

+                                               ((INSTANCE) == MDMA_Channel8)  || \

+                                               ((INSTANCE) == MDMA_Channel9)  || \

+                                               ((INSTANCE) == MDMA_Channel10) || \

+                                               ((INSTANCE) == MDMA_Channel11) || \

+                                               ((INSTANCE) == MDMA_Channel12) || \

+                                               ((INSTANCE) == MDMA_Channel13) || \

+                                               ((INSTANCE) == MDMA_Channel14) || \

+                                               ((INSTANCE) == MDMA_Channel15))

+

+

+/******************************* FDCAN Instances ******************************/

+#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \

+                                             ((__INSTANCE__) == FDCAN2))

+

+#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)

+

+/******************************* GFXMMU Instances *******************************/

+#define IS_GFXMMU_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GFXMMU)

+

+/******************************* GPIO Instances *******************************/

+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \

+                                        ((INSTANCE) == GPIOB) || \

+                                        ((INSTANCE) == GPIOC) || \

+                                        ((INSTANCE) == GPIOD) || \

+                                        ((INSTANCE) == GPIOE) || \

+                                        ((INSTANCE) == GPIOF) || \

+                                        ((INSTANCE) == GPIOG) || \

+                                        ((INSTANCE) == GPIOH) || \

+                                        ((INSTANCE) == GPIOI) || \

+                                        ((INSTANCE) == GPIOJ) || \

+                                        ((INSTANCE) == GPIOK))

+

+/******************************* GPIO AF Instances ****************************/

+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)

+

+/**************************** GPIO Lock Instances *****************************/

+/* On H7, all GPIO Bank support the Lock mechanism */

+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)

+

+/******************************** HSEM Instances *******************************/

+#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)

+#define HSEM_CPU1_COREID         (0x00000001U) /* Semaphore Core CM7 ID */

+#define HSEM_CR_COREID_CPU1      (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)

+#define HSEM_CR_COREID_CURRENT   (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)

+

+#define HSEM_SEMID_MIN     (0U)       /* HSEM ID Min*/

+#define HSEM_SEMID_MAX     (15U)      /* HSEM ID Max */

+

+#define HSEM_PROCESSID_MIN (0U)       /* HSEM Process ID Min */

+#define HSEM_PROCESSID_MAX (255U)     /* HSEM Process ID Max */

+

+#define HSEM_CLEAR_KEY_MIN (0U)       /* HSEM clear Key Min value */

+#define HSEM_CLEAR_KEY_MAX (0xFFFFU)  /* HSEM clear Key Max value */

+

+/******************************** I2C Instances *******************************/

+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

+                                       ((INSTANCE) == I2C2) || \

+                                       ((INSTANCE) == I2C3) || \

+                                       ((INSTANCE) == I2C4))

+/************** I2C Instances : wakeup capability from stop modes *************/

+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)

+

+/****************************** SMBUS Instances *******************************/

+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

+                                         ((INSTANCE) == I2C2) || \

+                                         ((INSTANCE) == I2C3) || \

+                                         ((INSTANCE) == I2C4))

+/******************************** I2S Instances *******************************/

+#define IS_I2S_ALL_INSTANCE(INSTANCE)   (((INSTANCE) == SPI1) || \

+                                         ((INSTANCE) == SPI2) || \

+                                         ((INSTANCE) == SPI3) || \

+                                         ((INSTANCE) == SPI6))

+

+/****************************** LTDC Instances ********************************/

+#define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)

+

+/******************************* RNG Instances ********************************/

+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)

+

+/****************************** RTC Instances *********************************/

+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)

+

+/****************************** SDMMC Instances *********************************/

+#define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \

+                                           ((_INSTANCE_) == SDMMC2))

+

+/******************************** SMBUS Instances *****************************/

+#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)

+

+/******************************** SPI Instances *******************************/

+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \

+                                       ((INSTANCE) == SPI2) || \

+                                       ((INSTANCE) == SPI3) || \

+                                       ((INSTANCE) == SPI4) || \

+                                       ((INSTANCE) == SPI5) || \

+                                       ((INSTANCE) == SPI6))

+

+#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \

+                                           ((INSTANCE) == SPI2) || \

+                                           ((INSTANCE) == SPI3))

+

+/******************************** SWPMI Instances *****************************/

+#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)

+

+/****************** LPTIM Instances : All supported instances *****************/

+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \

+                                         ((INSTANCE) == LPTIM2) || \

+                                         ((INSTANCE) == LPTIM3))

+

+/****************** LPTIM Instances : supporting encoder interface **************/

+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \

+                                                           ((INSTANCE) == LPTIM2))

+

+/****************** TIM Instances : All supported instances *******************/

+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM6)   || \

+                                         ((INSTANCE) == TIM7)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM13)  || \

+                                         ((INSTANCE) == TIM14)  || \

+                                         ((INSTANCE) == TIM15)  || \

+                                         ((INSTANCE) == TIM16)  || \

+                                         ((INSTANCE) == TIM17))

+

+/************* TIM Instances : at least 1 capture/compare channel *************/

+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM13)  || \

+                                         ((INSTANCE) == TIM14)  || \

+                                         ((INSTANCE) == TIM15)  || \

+                                         ((INSTANCE) == TIM16)  || \

+                                         ((INSTANCE) == TIM17))

+

+/************ TIM Instances : at least 2 capture/compare channels *************/

+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM15))

+

+/************ TIM Instances : at least 3 capture/compare channels *************/

+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8))

+

+/************ TIM Instances : at least 4 capture/compare channels *************/

+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8))

+

+/************ TIM Instances : at least 5 capture/compare channels *************/

+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM8))

+/************ TIM Instances : at least 6 capture/compare channels *************/

+#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM8))

+

+/******************** TIM Instances : Advanced-control timers *****************/

+#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \

+                                                ((__INSTANCE__) == TIM8))

+

+/******************** TIM Instances : Advanced-control timers *****************/

+

+/******************* TIM Instances : Timer input XOR function *****************/

+#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : DMA requests generation (UDE) *************/

+#define IS_TIM_DMA_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM6)   || \

+                                           ((INSTANCE) == TIM7)   || \

+                                           ((INSTANCE) == TIM8)   || \

+                                           ((INSTANCE) == TIM15)  || \

+                                           ((INSTANCE) == TIM16)  || \

+                                           ((INSTANCE) == TIM17))

+

+/************ TIM Instances : DMA requests generation (CCxDE) *****************/

+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15)  || \

+                                            ((INSTANCE) == TIM16)  || \

+                                            ((INSTANCE) == TIM17))

+

+/************ TIM Instances : DMA requests generation (COMDE) *****************/

+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15))

+

+/******************** TIM Instances : DMA burst feature ***********************/

+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8))

+

+/*************** TIM Instances : external trigger reamp input available *******/

+#define IS_TIM_ETR_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : remapping capability **********************/

+#define IS_TIM_REMAP_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \

+                                          ((INSTANCE) == TIM2)  || \

+                                          ((INSTANCE) == TIM3)  || \

+                                          ((INSTANCE) == TIM5)  || \

+                                          ((INSTANCE) == TIM8)  || \

+                                          ((INSTANCE) == TIM16) || \

+                                          ((INSTANCE) == TIM17))

+

+/*************** TIM Instances : external trigger reamp input available *******/

+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                              ((INSTANCE) == TIM2)   || \

+                                              ((INSTANCE) == TIM3)   || \

+                                              ((INSTANCE) == TIM5)   || \

+                                              ((INSTANCE) == TIM8))

+

+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/

+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM6)   || \

+                                            ((INSTANCE) == TIM7)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15))

+

+/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/

+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM8)   || \

+                                           ((INSTANCE) == TIM12))

+

+/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/

+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM8))

+

+/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/

+#define IS_TIM_TISEL_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)   || \

+                                          ((INSTANCE) == TIM2)   || \

+                                          ((INSTANCE) == TIM3)   || \

+                                          ((INSTANCE) == TIM4)   || \

+                                          ((INSTANCE) == TIM5)   || \

+                                          ((INSTANCE) == TIM8)   || \

+                                          ((INSTANCE) == TIM15)  || \

+                                          ((INSTANCE) == TIM16)  || \

+                                          ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting commutation event *************/

+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \

+                                                     ((INSTANCE) == TIM8)    || \

+                                                     ((INSTANCE) == TIM15)   || \

+                                                     ((INSTANCE) == TIM16)   || \

+                                                     ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting encoder interface **************/

+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1)  || \

+                                                      ((__INSTANCE__) == TIM2)      || \

+                                                      ((__INSTANCE__) == TIM3)      || \

+                                                      ((__INSTANCE__) == TIM4)      || \

+                                                      ((__INSTANCE__) == TIM5)      || \

+                                                      ((__INSTANCE__) == TIM8))

+

+/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/

+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                                       ((INSTANCE) == TIM8))

+/******************* TIM Instances : output(s) available **********************/

+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \

+    ((((INSTANCE) == TIM1) &&                  \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4) ||          \

+      ((CHANNEL) == TIM_CHANNEL_5) ||          \

+      ((CHANNEL) == TIM_CHANNEL_6)))           \

+     ||                                        \

+     (((INSTANCE) == TIM2) &&                  \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM3) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1)||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM4) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM5) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM8) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4) ||          \

+      ((CHANNEL) == TIM_CHANNEL_5) ||          \

+      ((CHANNEL) == TIM_CHANNEL_6)))           \

+  ||                                           \

+     (((INSTANCE) == TIM12) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2)))           \

+  ||                                           \

+     (((INSTANCE) == TIM13) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM14) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM15) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+     ((CHANNEL) == TIM_CHANNEL_2)))            \

+  ||                                           \

+     (((INSTANCE) == TIM16) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM17) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1))))

+

+/****************** TIM Instances : supporting the break function *************/

+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\

+      (((INSTANCE) == TIM1)    || \

+      ((INSTANCE) == TIM8)     || \

+       ((INSTANCE) == TIM15)   || \

+       ((INSTANCE) == TIM16)   || \

+       ((INSTANCE) == TIM17))

+

+/************** TIM Instances : supporting Break source selection *************/

+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \

+                                               ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting complementary output(s) ********/

+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \

+   ((((INSTANCE) == TIM1) &&                    \

+     (((CHANNEL) == TIM_CHANNEL_1) ||           \

+      ((CHANNEL) == TIM_CHANNEL_2) ||           \

+      ((CHANNEL) == TIM_CHANNEL_3)))            \

+ ||                                             \

+      (((INSTANCE) == TIM8) &&                  \

+      (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||           \

+      ((CHANNEL) == TIM_CHANNEL_3)))            \

+    ||                                          \

+    (((INSTANCE) == TIM15) &&                   \

+      ((CHANNEL) == TIM_CHANNEL_1))             \

+    ||                                          \

+    (((INSTANCE) == TIM16) &&                   \

+     ((CHANNEL) == TIM_CHANNEL_1))              \

+    ||                                          \

+    (((INSTANCE) == TIM17) &&                   \

+     ((CHANNEL) == TIM_CHANNEL_1)))

+

+/****************** TIM Instances : supporting counting mode selection ********/

+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting repetition counter *************/

+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15)   || \

+   ((INSTANCE) == TIM16)   || \

+   ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting synchronization ****************/

+#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\

+    (((__INSTANCE__) == TIM1)    || \

+     ((__INSTANCE__) == TIM2)    || \

+     ((__INSTANCE__) == TIM3)    || \

+     ((__INSTANCE__) == TIM4)    || \

+     ((__INSTANCE__) == TIM5)    || \

+     ((__INSTANCE__) == TIM6)    || \

+     ((__INSTANCE__) == TIM8)    || \

+     ((__INSTANCE__) == TIM12)   || \

+     ((__INSTANCE__) == TIM15))

+

+/****************** TIM Instances : supporting clock division *****************/

+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15)   || \

+   ((INSTANCE) == TIM16)   || \

+   ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting external clock mode 1 for ETRF input */

+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting external clock mode 2 **********/

+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\

+ (((INSTANCE) == TIM1)     || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/

+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/

+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : supporting OCxREF clear *******************/

+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3))

+

+/****************** TIM Instances : TIM_32B_COUNTER ***************************/

+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM5))

+

+/****************** TIM Instances : TIM_BKIN2 ***************************/

+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting Hall sensor interface **********/

+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)  || \

+                                                             ((__INSTANCE__) == TIM2)  || \

+                                                             ((__INSTANCE__) == TIM3)  || \

+                                                             ((__INSTANCE__) == TIM4)  || \

+                                                             ((__INSTANCE__) == TIM5)  || \

+                                                             ((__INSTANCE__) == TIM15) || \

+                                                             ((__INSTANCE__) == TIM8))

+

+/******************** USART Instances : Synchronous mode **********************/

+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                     ((INSTANCE) == USART2) || \

+                                     ((INSTANCE) == USART3) || \

+                                     ((INSTANCE) == USART6) || \

+                                     ((INSTANCE) == USART10))

+

+/******************** USART Instances : SPI slave mode ************************/

+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                              ((INSTANCE) == USART2) || \

+                                              ((INSTANCE) == USART3) || \

+                                              ((INSTANCE) == USART6) || \

+                                              ((INSTANCE) == USART10))

+

+/******************** UART Instances : Asynchronous mode **********************/

+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                    ((INSTANCE) == USART2) || \

+                                    ((INSTANCE) == USART3) || \

+                                    ((INSTANCE) == UART4)  || \

+                                    ((INSTANCE) == UART5)  || \

+                                    ((INSTANCE) == USART6) || \

+                                    ((INSTANCE) == UART7)  || \

+                                    ((INSTANCE) == UART8)  || \

+                                    ((INSTANCE) == UART9)  || \

+                                    ((INSTANCE) == USART10))

+

+/******************** UART Instances : FIFO mode.******************************/

+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                         ((INSTANCE) == USART2) || \

+                                         ((INSTANCE) == USART3) || \

+                                         ((INSTANCE) == UART4)  || \

+                                         ((INSTANCE) == UART5)  || \

+                                         ((INSTANCE) == USART6) || \

+                                         ((INSTANCE) == UART7)  || \

+                                         ((INSTANCE) == UART8)  || \

+                                         ((INSTANCE) == UART9)  || \

+                                         ((INSTANCE) == USART10)|| \

+                                         ((INSTANCE) == LPUART1))

+

+/****************** UART Instances : Auto Baud Rate detection *****************/

+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                            ((INSTANCE) == USART2) || \

+                                                            ((INSTANCE) == USART3) || \

+                                                            ((INSTANCE) == UART4)  || \

+                                                            ((INSTANCE) == UART5)  || \

+                                                            ((INSTANCE) == USART6) || \

+                                                            ((INSTANCE) == UART7)  || \

+                                                            ((INSTANCE) == UART8)  || \

+                                                            ((INSTANCE) == UART9)  || \

+                                                            ((INSTANCE) == USART10))

+

+/*********************** UART Instances : Driver Enable ***********************/

+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                  ((INSTANCE) == USART2) || \

+                                                  ((INSTANCE) == USART3) || \

+                                                  ((INSTANCE) == UART4)  || \

+                                                  ((INSTANCE) == UART5)  || \

+                                                  ((INSTANCE) == USART6) || \

+                                                  ((INSTANCE) == UART7)  || \

+                                                  ((INSTANCE) == UART8)  || \

+                                                  ((INSTANCE) == UART9)  || \

+                                                  ((INSTANCE) == USART10)|| \

+                                                  ((INSTANCE) == LPUART1))

+

+/********************* UART Instances : Half-Duplex mode **********************/

+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                               ((INSTANCE) == USART2) || \

+                                               ((INSTANCE) == USART3) || \

+                                               ((INSTANCE) == UART4)  || \

+                                               ((INSTANCE) == UART5)  || \

+                                               ((INSTANCE) == USART6) || \

+                                               ((INSTANCE) == UART7)  || \

+                                               ((INSTANCE) == UART8)  || \

+                                               ((INSTANCE) == UART9)  || \

+                                               ((INSTANCE) == USART10)|| \

+                                               ((INSTANCE) == LPUART1))

+

+/******************* UART Instances : Hardware Flow control *******************/

+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                           ((INSTANCE) == USART2) || \

+                                           ((INSTANCE) == USART3) || \

+                                           ((INSTANCE) == UART4)  || \

+                                           ((INSTANCE) == UART5)  || \

+                                           ((INSTANCE) == USART6) || \

+                                           ((INSTANCE) == UART7)  || \

+                                           ((INSTANCE) == UART8)  || \

+                                           ((INSTANCE) == UART9)  || \

+                                           ((INSTANCE) == USART10)|| \

+                                           ((INSTANCE) == LPUART1))

+

+/************************* UART Instances : LIN mode **************************/

+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                        ((INSTANCE) == USART2) || \

+                                        ((INSTANCE) == USART3) || \

+                                        ((INSTANCE) == UART4)  || \

+                                        ((INSTANCE) == UART5)  || \

+                                        ((INSTANCE) == USART6) || \

+                                        ((INSTANCE) == UART7)  || \

+                                        ((INSTANCE) == UART8)  || \

+                                        ((INSTANCE) == UART9)  || \

+                                        ((INSTANCE) == USART10))

+

+/****************** UART Instances : Wake-up from Stop mode *******************/

+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                    ((INSTANCE) == USART2) || \

+                                                    ((INSTANCE) == USART3) || \

+                                                    ((INSTANCE) == UART4)  || \

+                                                    ((INSTANCE) == UART5)  || \

+                                                    ((INSTANCE) == USART6) || \

+                                                    ((INSTANCE) == UART7)  || \

+                                                    ((INSTANCE) == UART8)  || \

+                                                    ((INSTANCE) == UART9)  || \

+                                                    ((INSTANCE) == USART10)|| \

+                                                    ((INSTANCE) == LPUART1))

+

+/************************* UART Instances : IRDA mode *************************/

+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                    ((INSTANCE) == USART2) || \

+                                    ((INSTANCE) == USART3) || \

+                                    ((INSTANCE) == UART4)  || \

+                                    ((INSTANCE) == UART5)  || \

+                                    ((INSTANCE) == USART6) || \

+                                    ((INSTANCE) == UART7)  || \

+                                    ((INSTANCE) == UART8)  || \

+                                    ((INSTANCE) == UART9)  || \

+                                    ((INSTANCE) == USART10))

+

+/********************* USART Instances : Smard card mode **********************/

+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                         ((INSTANCE) == USART2) || \

+                                         ((INSTANCE) == USART3) || \

+                                         ((INSTANCE) == USART6) ||\

+                                         ((INSTANCE) == USART10))

+

+/****************************** LPUART Instance *******************************/

+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)

+

+/****************************** IWDG Instances ********************************/

+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG1)

+/****************************** USB Instances ********************************/

+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)

+

+/****************************** WWDG Instances ********************************/

+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG1)

+/****************************** MDIOS Instances ********************************/

+#define IS_MDIOS_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == MDIOS)

+

+/****************************** CEC Instances *********************************/

+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)

+

+/****************************** SAI Instances ********************************/

+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \

+                                       ((INSTANCE) == SAI1_Block_B) || \

+                                       ((INSTANCE) == SAI2_Block_A) || \

+                                       ((INSTANCE) == SAI2_Block_B))

+

+/****************************** SPDIFRX Instances ********************************/

+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)

+

+/****************************** OPAMP Instances *******************************/

+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \

+                                         ((INSTANCE) == OPAMP2))

+

+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)

+

+/*********************** USB OTG PCD Instances ********************************/

+#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS)

+

+/*********************** USB OTG HCD Instances ********************************/

+#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS)

+

+/******************************************************************************/

+/*  For a painless codes migration between the STM32H7xx device product       */

+/*  lines, or with STM32F7xx devices the aliases defined below are put        */

+/*   in place to overcome the differences in the interrupt handlers and IRQn  */

+/*   definitions. No need to update developed interrupt code when moving      */

+/*  across product lines within the same STM32H7 Family                       */

+/******************************************************************************/

+

+/* Aliases for __IRQn */

+#define  HASH_RNG_IRQn                  RNG_IRQn

+#define  TIM1_BRK_TIM9_IRQn             TIM1_BRK_IRQn

+#define  TIM1_UP_TIM10_IRQn             TIM1_UP_IRQn

+#define  TIM1_TRG_COM_TIM11_IRQn        TIM1_TRG_COM_IRQn

+#define  PVD_IRQn                       PVD_AVD_IRQn

+

+/* Aliases for BDMA __IRQn */

+#define  BDMA_Channel0_IRQn             BDMA2_Channel0_IRQn

+#define  BDMA_Channel1_IRQn             BDMA2_Channel1_IRQn

+#define  BDMA_Channel2_IRQn             BDMA2_Channel2_IRQn

+#define  BDMA_Channel3_IRQn             BDMA2_Channel3_IRQn

+#define  BDMA_Channel4_IRQn             BDMA2_Channel4_IRQn

+#define  BDMA_Channel5_IRQn             BDMA2_Channel5_IRQn

+#define  BDMA_Channel6_IRQn             BDMA2_Channel6_IRQn

+#define  BDMA_Channel7_IRQn             BDMA2_Channel7_IRQn

+

+/* Aliases for PWR __IRQn */

+#define  PVD_AVD_IRQn                   PVD_PVM_IRQn

+

+/* Aliases for DCMI/PSSI __IRQn */

+#define  DCMI_IRQn                      DCMI_PSSI_IRQn

+

+/* Aliases for __IRQHandler */

+#define  HASH_RNG_IRQHandler           RNG_IRQHandler

+#define TIM1_BRK_TIM9_IRQHandler       TIM1_BRK_IRQHandler

+#define TIM1_UP_TIM9_IRQHandler        TIM1_UP_IRQHandler

+#define TIM1_TRG_COM_TIM11_IRQHandler  TIM1_TRG_COM_IRQHandler

+#define PVD_IRQHandler                 PVD_AVD_IRQHandler

+

+

+/* Aliases for BDMA __IRQHandler */

+#define  BDMA_Channel0_IRQHandler      BDMA2_Channel0_IRQHandler

+#define  BDMA_Channel1_IRQHandler      BDMA2_Channel1_IRQHandler

+#define  BDMA_Channel2_IRQHandler      BDMA2_Channel2_IRQHandler

+#define  BDMA_Channel3_IRQHandler      BDMA2_Channel3_IRQHandler

+#define  BDMA_Channel4_IRQHandler      BDMA2_Channel4_IRQHandler

+#define  BDMA_Channel5_IRQHandler      BDMA2_Channel5_IRQHandler

+#define  BDMA_Channel6_IRQHandler      BDMA2_Channel6_IRQHandler

+#define  BDMA_Channel7_IRQHandler      BDMA2_Channel7_IRQHandler

+

+/* Aliases for PWR __IRQHandler */

+#define  PVD_AVD_IRQHandler            PVD_PVM_IRQHandler

+

+/* Aliases for DCMI/PSSI __IRQHandler */

+#define  DCMI_IRQHandler               DCMI_PSSI_IRQHandler

+

+/* Alias for BDMA defines */

+#define BDMA_BASE              BDMA2_BASE

+#define BDMA_Channel0_BASE     BDMA2_Channel0_BASE

+#define BDMA_Channel1_BASE     BDMA2_Channel1_BASE

+#define BDMA_Channel2_BASE     BDMA2_Channel2_BASE

+#define BDMA_Channel3_BASE     BDMA2_Channel3_BASE

+#define BDMA_Channel4_BASE     BDMA2_Channel4_BASE

+#define BDMA_Channel5_BASE     BDMA2_Channel5_BASE

+#define BDMA_Channel6_BASE     BDMA2_Channel6_BASE

+#define BDMA_Channel7_BASE     BDMA2_Channel7_BASE

+

+#define BDMA                   BDMA2

+#define BDMA_Channel0          BDMA2_Channel0

+#define BDMA_Channel1          BDMA2_Channel1

+#define BDMA_Channel2          BDMA2_Channel2

+#define BDMA_Channel3          BDMA2_Channel3

+#define BDMA_Channel4          BDMA2_Channel4

+#define BDMA_Channel5          BDMA2_Channel5

+#define BDMA_Channel6          BDMA2_Channel6

+#define BDMA_Channel7          BDMA2_Channel7

+

+/* Alias for PWR defines */

+#define PWR_CPUCR_RUN_D3       PWR_CPUCR_RUN_SRD

+#define PWR_CPUCR_PDDS_D3      PWR_CPUCR_PDDS_SRD

+#define PWR_CPUCR_PDDS_D1      PWR_CPUCR_RETDS_CD

+

+#define PWR_D3CR_VOS           PWR_SRDCR_VOS

+

+#define PWR_D3CR_VOS_0         PWR_SRDCR_VOS_0

+#define PWR_D3CR_VOS_1         PWR_SRDCR_VOS_1

+#define PWR_D3CR_VOSRDY        PWR_SRDCR_VOSRDY

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif /* __cplusplus */

+

+#endif /* STM32H7A3xx_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7a3xxq.h b/bsps/arm/stm32h7/include/stm32h7a3xxq.h
new file mode 100644
index 0000000000..b694f215c1
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7a3xxq.h
@@ -0,0 +1,22416 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7a3xxq.h

+  * @author  MCD Application Team

+  * @brief   CMSIS STM32H7A3xxQ Device Peripheral Access Layer Header File.

+  *

+  *          This file contains:

+  *           - Data structures and the address mapping for all peripherals

+  *           - Peripheral's registers declarations and bits definition

+  *           - Macros to access peripheral's registers hardware

+  *

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/** @addtogroup CMSIS_Device

+  * @{

+  */

+

+/** @addtogroup stm32h7a3xxq

+  * @{

+  */

+

+#ifndef STM32H7A3xxQ_H

+#define STM32H7A3xxQ_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif /* __cplusplus */

+

+/** @addtogroup Peripheral_interrupt_number_definition

+  * @{

+  */

+

+/**

+ * @brief STM32H7XX Interrupt Number Definition, according to the selected device

+ *        in @ref Library_configuration_section

+ */

+typedef enum

+{

+/******  Cortex-M Processor Exceptions Numbers *****************************************************************/

+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */

+  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */

+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */

+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */

+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */

+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M SV Call Interrupt                                     */

+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M Debug Monitor Interrupt                               */

+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M Pend SV Interrupt                                     */

+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M System Tick Interrupt                                 */

+/******  STM32 specific Interrupt Numbers **********************************************************************/

+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)                   */

+  PVD_PVM_IRQn                = 1,      /*!< PVD/PVM through EXTI Line detection Interrupt                     */

+  RTC_TAMP_STAMP_CSS_LSE_IRQn = 2,      /*!< Tamper, TimeStamp, CSS and LSE interrupts through the EXTI line   */

+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */

+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */

+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */

+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */

+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */

+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */

+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */

+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */

+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */

+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */

+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */

+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */

+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */

+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */

+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */

+  ADC_IRQn                    = 18,     /*!< ADC1 and  ADC2 global Interrupts                                  */

+  FDCAN1_IT0_IRQn             = 19,     /*!< FDCAN1 Interrupt line 0                                           */

+  FDCAN2_IT0_IRQn             = 20,     /*!< FDCAN2 Interrupt line 0                                           */

+  FDCAN1_IT1_IRQn             = 21,     /*!< FDCAN1 Interrupt line 1                                           */

+  FDCAN2_IT1_IRQn             = 22,     /*!< FDCAN2 Interrupt line 1                                           */

+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */

+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                              */

+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                             */

+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt                            */

+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */

+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */

+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */

+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */

+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */

+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */

+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */

+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */

+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */

+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */

+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */

+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */

+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */

+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */

+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */

+  DFSDM2_IRQn                 = 42,     /*!< DFSDM2 global Interrupt                                           */

+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */

+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */

+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */

+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */

+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */

+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */

+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */

+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */

+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */

+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */

+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */

+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */

+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */

+  DMA2_Stream0_IRQn           = 56,     /*!<   DMA2 Stream 0 global Interrupt                                  */

+  DMA2_Stream1_IRQn           = 57,     /*!<   DMA2 Stream 1 global Interrupt                                  */

+  DMA2_Stream2_IRQn           = 58,     /*!<   DMA2 Stream 2 global Interrupt                                  */

+  DMA2_Stream3_IRQn           = 59,     /*!<   DMA2 Stream 3 global Interrupt                                  */

+  DMA2_Stream4_IRQn           = 60,     /*!<   DMA2 Stream 4 global Interrupt                                  */

+  FDCAN_CAL_IRQn              = 63,     /*!< FDCAN Calibration unit Interrupt                                  */

+  DFSDM1_FLT4_IRQn            = 64,     /*!< DFSDM Filter4 Interrupt                                           */

+  DFSDM1_FLT5_IRQn            = 65,     /*!< DFSDM Filter5 Interrupt                                           */

+  DFSDM1_FLT6_IRQn            = 66,     /*!< DFSDM Filter6 Interrupt                                           */

+  DFSDM1_FLT7_IRQn            = 67,     /*!< DFSDM Filter7 Interrupt                                           */

+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */

+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */

+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */

+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */

+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */

+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */

+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */

+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */

+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */

+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */

+  DCMI_PSSI_IRQn              = 78,     /*!< DCMI and PSSI global interrupt                                    */

+  RNG_IRQn                    = 80,     /*!< RNG global interrupt                                              */

+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */

+  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */

+  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */

+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */

+  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */

+  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */

+  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */

+  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */

+  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */

+  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */

+  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */

+  OCTOSPI1_IRQn               = 92,     /*!< OCTOSPI1 global interrupt                                         */

+  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */

+  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */

+  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */

+  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */

+  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */

+  DMAMUX1_OVR_IRQn            = 102,    /*!<DMAMUX1 Overrun interrupt                                          */

+  DFSDM1_FLT0_IRQn            = 110,    /*!<DFSDM Filter1 Interrupt                                            */

+  DFSDM1_FLT1_IRQn            = 111,    /*!<DFSDM Filter2 Interrupt                                            */

+  DFSDM1_FLT2_IRQn            = 112,    /*!<DFSDM Filter3 Interrupt                                            */

+  DFSDM1_FLT3_IRQn            = 113,    /*!<DFSDM Filter4 Interrupt                                            */

+  SWPMI1_IRQn                 = 115,    /*!< Serial Wire Interface 1 global interrupt                          */

+  TIM15_IRQn                  = 116,    /*!< TIM15 global Interrupt                                            */

+  TIM16_IRQn                  = 117,    /*!< TIM16 global Interrupt                                            */

+  TIM17_IRQn                  = 118,    /*!< TIM17 global Interrupt                                            */

+  MDIOS_WKUP_IRQn             = 119,    /*!< MDIOS Wakeup  Interrupt                                           */

+  MDIOS_IRQn                  = 120,    /*!< MDIOS global Interrupt                                            */

+  JPEG_IRQn                   = 121,    /*!< JPEG global Interrupt                                             */

+  MDMA_IRQn                   = 122,    /*!< MDMA global Interrupt                                             */

+  SDMMC2_IRQn                 = 124,    /*!< SDMMC2 global Interrupt                                           */

+  HSEM1_IRQn                  = 125,    /*!< HSEM1 global Interrupt                                            */

+  DAC2_IRQn                   = 127,    /*!< DAC2 global Interrupt                                             */

+  DMAMUX2_OVR_IRQn            = 128,    /*!<DMAMUX2 Overrun interrupt                                          */

+  BDMA2_Channel0_IRQn         = 129,    /*!< BDMA2 Channel 0 global Interrupt                                  */

+  BDMA2_Channel1_IRQn         = 130,    /*!< BDMA2 Channel 1 global Interrupt                                  */

+  BDMA2_Channel2_IRQn         = 131,    /*!< BDMA2 Channel 2 global Interrupt                                  */

+  BDMA2_Channel3_IRQn         = 132,    /*!< BDMA2 Channel 3 global Interrupt                                  */

+  BDMA2_Channel4_IRQn         = 133,    /*!< BDMA2 Channel 4 global Interrupt                                  */

+  BDMA2_Channel5_IRQn         = 134,    /*!< BDMA2 Channel 5 global Interrupt                                  */

+  BDMA2_Channel6_IRQn         = 135,    /*!< BDMA2 Channel 6 global Interrupt                                  */

+  BDMA2_Channel7_IRQn         = 136,    /*!< BDMA2 Channel 7 global Interrupt                                  */

+  COMP_IRQn                   = 137 ,   /*!< COMP global Interrupt                                             */

+  LPTIM2_IRQn                 = 138,    /*!< LP TIM2 global interrupt                                          */

+  LPTIM3_IRQn                 = 139,    /*!< LP TIM3 global interrupt                                          */

+  UART9_IRQn                  = 140,    /*!< UART9 global interrupt                                            */

+  USART10_IRQn                = 141,    /*!< USART10 global interrupt                                          */

+  LPUART1_IRQn                = 142,    /*!< LP UART1 interrupt                                                */

+  WWDG_RST_IRQn               = 143,    /*!<Window Watchdog Event interrupt                                    */

+  CRS_IRQn                    = 144,    /*!< Clock Recovery Global Interrupt                                   */

+  ECC_IRQn                    = 145,    /*!< ECC diagnostic Global Interrupt                                   */

+  DTS_IRQn                    = 147,    /*!< Digital Temperature Sensor Global Interrupt                       */

+  WAKEUP_PIN_IRQn             = 149,    /*!< Interrupt for all 6 wake-up pins                                  */

+  OCTOSPI2_IRQn               = 150,    /*!< OctoSPI2 global interrupt                                         */

+  GFXMMU_IRQn                 = 153,    /*!< GFXMMU global interrupt                                           */

+  BDMA1_IRQn                  = 154,    /*!< BDMA1 for DFSM global interrupt                                   */

+} IRQn_Type;

+

+/**

+  * @}

+  */

+

+/** @addtogroup Configuration_section_for_CMSIS

+  * @{

+  */

+

+#define SMPS       /*!< Switched mode power supply feature */

+

+

+

+/**

+  * @brief Configuration of the Cortex-M7 Processor and Core Peripherals

+   */

+#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */

+#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */

+#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */

+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */

+#define __FPU_PRESENT             1       /*!< FPU present                                   */

+#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */

+#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */

+#include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */

+

+/**

+  * @}

+  */

+

+

+

+

+#include "system_stm32h7xx.h"

+#include <stdint.h>

+

+/** @addtogroup Peripheral_registers_structures

+  * @{

+  */

+

+/**

+  * @brief Analog to Digital Converter

+  */

+

+typedef struct

+{

+  __IO uint32_t ISR;              /*!< ADC Interrupt and Status Register,                          Address offset: 0x00 */

+  __IO uint32_t IER;              /*!< ADC Interrupt Enable Register,                              Address offset: 0x04 */

+  __IO uint32_t CR;               /*!< ADC control register,                                       Address offset: 0x08 */

+  __IO uint32_t CFGR;             /*!< ADC Configuration register,                                 Address offset: 0x0C */

+  __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                               Address offset: 0x10 */

+  __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                                 Address offset: 0x14 */

+  __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                                 Address offset: 0x18 */

+  __IO uint32_t PCSEL;            /*!< ADC pre-channel selection,                                  Address offset: 0x1C */

+  __IO uint32_t LTR1;             /*!< ADC watchdog Lower threshold register 1,                    Address offset: 0x20 */

+  __IO uint32_t HTR1;             /*!< ADC watchdog higher threshold register 1,                   Address offset: 0x24 */

+  uint32_t      RESERVED1;        /*!< Reserved, 0x028                                                                  */

+  uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                                  */

+  __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                            Address offset: 0x30 */

+  __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                            Address offset: 0x34 */

+  __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                            Address offset: 0x38 */

+  __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                            Address offset: 0x3C */

+  __IO uint32_t DR;               /*!< ADC regular data register,                                  Address offset: 0x40 */

+  uint32_t      RESERVED3;        /*!< Reserved, 0x044                                                                  */

+  uint32_t      RESERVED4;        /*!< Reserved, 0x048                                                                  */

+  __IO uint32_t JSQR;             /*!< ADC injected sequence register,                             Address offset: 0x4C */

+  uint32_t      RESERVED5[4];     /*!< Reserved, 0x050 - 0x05C                                                          */

+  __IO uint32_t OFR1;             /*!< ADC offset register 1,                                      Address offset: 0x60 */

+  __IO uint32_t OFR2;             /*!< ADC offset register 2,                                      Address offset: 0x64 */

+  __IO uint32_t OFR3;             /*!< ADC offset register 3,                                      Address offset: 0x68 */

+  __IO uint32_t OFR4;             /*!< ADC offset register 4,                                      Address offset: 0x6C */

+  uint32_t      RESERVED6[4];     /*!< Reserved, 0x070 - 0x07C                                                          */

+  __IO uint32_t JDR1;             /*!< ADC injected data register 1,                               Address offset: 0x80 */

+  __IO uint32_t JDR2;             /*!< ADC injected data register 2,                               Address offset: 0x84 */

+  __IO uint32_t JDR3;             /*!< ADC injected data register 3,                               Address offset: 0x88 */

+  __IO uint32_t JDR4;             /*!< ADC injected data register 4,                               Address offset: 0x8C */

+  uint32_t      RESERVED7[4];     /*!< Reserved, 0x090 - 0x09C                                                          */

+  __IO uint32_t AWD2CR;           /*!< ADC  Analog Watchdog 2 Configuration Register,              Address offset: 0xA0 */

+  __IO uint32_t AWD3CR;           /*!< ADC  Analog Watchdog 3 Configuration Register,              Address offset: 0xA4 */

+  uint32_t      RESERVED8;        /*!< Reserved, 0x0A8                                                                  */

+  uint32_t      RESERVED9;        /*!< Reserved, 0x0AC                                                                  */

+  __IO uint32_t LTR2;             /*!< ADC watchdog Lower threshold register 2,                    Address offset: 0xB0 */

+  __IO uint32_t HTR2;             /*!< ADC watchdog Higher threshold register 2,                   Address offset: 0xB4 */

+  __IO uint32_t LTR3;             /*!< ADC watchdog Lower threshold register 3,                    Address offset: 0xB8 */

+  __IO uint32_t HTR3;             /*!< ADC watchdog Higher threshold register 3,                   Address offset: 0xBC */

+  __IO uint32_t DIFSEL;           /*!< ADC  Differential Mode Selection Register,                  Address offset: 0xC0 */

+  __IO uint32_t CALFACT;          /*!< ADC  Calibration Factors,                                   Address offset: 0xC4 */

+  __IO uint32_t CALFACT2;         /*!< ADC  Linearity Calibration Factors,                         Address offset: 0xC8 */

+} ADC_TypeDef;

+

+

+typedef struct

+{

+__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */

+uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */

+__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */

+__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */

+__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */

+

+} ADC_Common_TypeDef;

+

+

+/**

+  * @brief VREFBUF

+  */

+

+typedef struct

+{

+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */

+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */

+} VREFBUF_TypeDef;

+

+

+/**

+  * @brief FD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */

+  __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */

+  __IO uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */

+  __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */

+  __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */

+  __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */

+  __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */

+  __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */

+  __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */

+  __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */

+  __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */

+  __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */

+  __IO uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */

+  __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */

+  __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */

+  __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */

+  __IO uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */

+  __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */

+  __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */

+  __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */

+  __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */

+  __IO uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */

+  __IO uint32_t GFC;          /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */

+  __IO uint32_t SIDFC;        /*!< FDCAN Standard ID Filter Configuration register,                 Address offset: 0x084 */

+  __IO uint32_t XIDFC;        /*!< FDCAN Extended ID Filter Configuration register,                 Address offset: 0x088 */

+  __IO uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */

+  __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x090 */

+  __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x094 */

+  __IO uint32_t NDAT1;        /*!< FDCAN New Data 1 register,                                       Address offset: 0x098 */

+  __IO uint32_t NDAT2;        /*!< FDCAN New Data 2 register,                                       Address offset: 0x09C */

+  __IO uint32_t RXF0C;        /*!< FDCAN Rx FIFO 0 Configuration register,                          Address offset: 0x0A0 */

+  __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x0A4 */

+  __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x0A8 */

+  __IO uint32_t RXBC;         /*!< FDCAN Rx Buffer Configuration register,                          Address offset: 0x0AC */

+  __IO uint32_t RXF1C;        /*!< FDCAN Rx FIFO 1 Configuration register,                          Address offset: 0x0B0 */

+  __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x0B4 */

+  __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x0B8 */

+  __IO uint32_t RXESC;        /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register,        Address offset: 0x0BC */

+  __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */

+  __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */

+  __IO uint32_t TXESC;        /*!< FDCAN Tx Buffer Element Size Configuration register,             Address offset: 0x0C8 */

+  __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0CC */

+  __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0D0 */

+  __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D4 */

+  __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D8 */

+  __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0DC */

+  __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0E0 */

+  __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */

+  __IO uint32_t RESERVED6[2]; /*!< Reserved,                                                                0x0E8 - 0x0EC */

+  __IO uint32_t TXEFC;        /*!< FDCAN Tx Event FIFO Configuration register,                      Address offset: 0x0F0 */

+  __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0F4 */

+  __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0F8 */

+  __IO uint32_t RESERVED7;    /*!< Reserved,                                                                        0x0FC */

+} FDCAN_GlobalTypeDef;

+

+/**

+  * @brief TTFD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t TTTMC;          /*!< TT Trigger Memory Configuration register,    Address offset: 0x100 */

+  __IO uint32_t TTRMC;          /*!< TT Reference Message Configuration register, Address offset: 0x104 */

+  __IO uint32_t TTOCF;          /*!< TT Operation Configuration register,         Address offset: 0x108 */

+  __IO uint32_t TTMLM;          /*!< TT Matrix Limits register,                   Address offset: 0x10C */

+  __IO uint32_t TURCF;          /*!< TUR Configuration register,                  Address offset: 0x110 */

+  __IO uint32_t TTOCN;          /*!< TT Operation Control register,               Address offset: 0x114 */

+  __IO uint32_t TTGTP;          /*!< TT Global Time Preset register,              Address offset: 0x118 */

+  __IO uint32_t TTTMK;          /*!< TT Time Mark register,                       Address offset: 0x11C */

+  __IO uint32_t TTIR;           /*!< TT Interrupt register,                       Address offset: 0x120 */

+  __IO uint32_t TTIE;           /*!< TT Interrupt Enable register,                Address offset: 0x124 */

+  __IO uint32_t TTILS;          /*!< TT Interrupt Line Select register,           Address offset: 0x128 */

+  __IO uint32_t TTOST;          /*!< TT Operation Status register,                Address offset: 0x12C */

+  __IO uint32_t TURNA;          /*!< TT TUR Numerator Actual register,            Address offset: 0x130 */

+  __IO uint32_t TTLGT;          /*!< TT Local and Global Time register,           Address offset: 0x134 */

+  __IO uint32_t TTCTC;          /*!< TT Cycle Time and Count register,            Address offset: 0x138 */

+  __IO uint32_t TTCPT;          /*!< TT Capture Time register,                    Address offset: 0x13C */

+  __IO uint32_t TTCSM;          /*!< TT Cycle Sync Mark register,                 Address offset: 0x140 */

+  __IO uint32_t RESERVED1[111]; /*!< Reserved,                                            0x144 - 0x2FC */

+  __IO uint32_t TTTS;           /*!< TT Trigger Select register,                  Address offset: 0x300 */

+} TTCAN_TypeDef;

+

+/**

+  * @brief FD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t CREL;  /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */

+  __IO uint32_t CCFG;  /*!< Calibration Configuration register,           Address offset: 0x04 */

+  __IO uint32_t CSTAT; /*!< Calibration Status register,                  Address offset: 0x08 */

+  __IO uint32_t CWD;   /*!< Calibration Watchdog register,                Address offset: 0x0C */

+  __IO uint32_t IR;    /*!< CCU Interrupt register,                       Address offset: 0x10 */

+  __IO uint32_t IE;    /*!< CCU Interrupt Enable register,                Address offset: 0x14 */

+} FDCAN_ClockCalibrationUnit_TypeDef;

+

+

+/**

+  * @brief Consumer Electronics Control

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;           /*!< CEC control register,              Address offset:0x00 */

+  __IO uint32_t CFGR;         /*!< CEC configuration register,        Address offset:0x04 */

+  __IO uint32_t TXDR;         /*!< CEC Tx data register ,             Address offset:0x08 */

+  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,              Address offset:0x0C */

+  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register, Address offset:0x10 */

+  __IO uint32_t IER;          /*!< CEC interrupt enable register,     Address offset:0x14 */

+}CEC_TypeDef;

+

+/**

+  * @brief CRC calculation unit

+  */

+

+typedef struct

+{

+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */

+  __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */

+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */

+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */

+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */

+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */

+} CRC_TypeDef;

+

+

+/**

+  * @brief Clock Recovery System

+  */

+typedef struct

+{

+__IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */

+__IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */

+__IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */

+__IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */

+} CRS_TypeDef;

+

+

+/**

+  * @brief Digital to Analog Converter

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */

+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */

+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */

+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */

+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */

+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */

+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */

+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */

+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */

+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */

+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */

+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */

+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */

+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */

+  __IO uint32_t CCR;      /*!< DAC calibration control register,                        Address offset: 0x38 */

+  __IO uint32_t MCR;      /*!< DAC mode control register,                               Address offset: 0x3C */

+  __IO uint32_t SHSR1;    /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */

+  __IO uint32_t SHSR2;    /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */

+  __IO uint32_t SHHR;     /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */

+  __IO uint32_t SHRR;     /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */

+} DAC_TypeDef;

+

+/**

+  * @brief DFSDM module registers

+  */

+typedef struct

+{

+  __IO uint32_t FLTCR1;          /*!< DFSDM control register1,                          Address offset: 0x100 */

+  __IO uint32_t FLTCR2;          /*!< DFSDM control register2,                          Address offset: 0x104 */

+  __IO uint32_t FLTISR;          /*!< DFSDM interrupt and status register,              Address offset: 0x108 */

+  __IO uint32_t FLTICR;          /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */

+  __IO uint32_t FLTJCHGR;        /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */

+  __IO uint32_t FLTFCR;          /*!< DFSDM filter control register,                    Address offset: 0x114 */

+  __IO uint32_t FLTJDATAR;       /*!< DFSDM data register for injected group,           Address offset: 0x118 */

+  __IO uint32_t FLTRDATAR;       /*!< DFSDM data register for regular group,            Address offset: 0x11C */

+  __IO uint32_t FLTAWHTR;        /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */

+  __IO uint32_t FLTAWLTR;        /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */

+  __IO uint32_t FLTAWSR;         /*!< DFSDM analog watchdog status register             Address offset: 0x128 */

+  __IO uint32_t FLTAWCFR;        /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */

+  __IO uint32_t FLTEXMAX;        /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */

+  __IO uint32_t FLTEXMIN;        /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */

+  __IO uint32_t FLTCNVTIMR;      /*!< DFSDM conversion timer,                           Address offset: 0x138 */

+} DFSDM_Filter_TypeDef;

+

+/**

+  * @brief DFSDM channel configuration registers

+  */

+typedef struct

+{

+  __IO uint32_t CHCFGR1;      /*!< DFSDM channel configuration register1,            Address offset: 0x00 */

+  __IO uint32_t CHCFGR2;      /*!< DFSDM channel configuration register2,            Address offset: 0x04 */

+  __IO uint32_t CHAWSCDR;     /*!< DFSDM channel analog watchdog and

+                                   short circuit detector register,                  Address offset: 0x08 */

+  __IO uint32_t CHWDATAR;     /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */

+  __IO uint32_t CHDATINR;     /*!< DFSDM channel data input register,                Address offset: 0x10 */

+  __IO uint32_t CHDLYR;       /*!< DFSDM channel delay register,                     Address offset: 0x14 */

+} DFSDM_Channel_TypeDef;

+

+/**

+  * @brief Debug MCU

+  */

+typedef struct

+{

+  __IO uint32_t IDCODE;        /*!< MCU device ID code,                     Address offset: 0x00 */

+  __IO uint32_t CR;            /*!< Debug MCU configuration register,       Address offset: 0x04 */

+  uint32_t RESERVED4[11];      /*!< Reserved,                             Address offset: 0x08 */

+  __IO uint32_t APB3FZ1;     /*!< Debug MCU APB3FZ1 freeze register,    Address offset: 0x34 */

+  uint32_t RESERVED5;          /*!< Reserved,                             Address offset: 0x38 */

+  __IO uint32_t APB1LFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x3C */

+  uint32_t RESERVED6;          /*!< Reserved,                             Address offset: 0x40 */

+  __IO uint32_t APB1HFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x44 */

+  uint32_t RESERVED7;          /*!< Reserved,                             Address offset: 0x48 */

+  __IO uint32_t APB2FZ1;     /*!< Debug MCU APB2FZ1 freeze register,    Address offset: 0x4C */

+  uint32_t RESERVED8;          /*!< Reserved,                             Address offset: 0x50 */

+  __IO uint32_t APB4FZ1;     /*!< Debug MCU APB4FZ1 freeze register,    Address offset: 0x54 */

+}DBGMCU_TypeDef;

+/**

+  * @brief DCMI

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */

+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */

+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */

+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */

+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */

+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */

+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */

+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */

+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */

+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */

+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */

+} DCMI_TypeDef;

+

+/**

+  * @brief PSSI

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;             /*!< PSSI control register 1,               Address offset: 0x000 */

+  __IO uint32_t SR;             /*!< PSSI status register,                  Address offset: 0x004 */

+  __IO uint32_t RIS;            /*!< PSSI raw interrupt status register,    Address offset: 0x008 */

+  __IO uint32_t IER;            /*!< PSSI interrupt enable register,        Address offset: 0x00C */

+  __IO uint32_t MIS;            /*!< PSSI masked interrupt status register, Address offset: 0x010 */

+  __IO uint32_t ICR;            /*!< PSSI interrupt clear register,         Address offset: 0x014 */

+  __IO uint32_t RESERVED1[4];   /*!< Reserved,                                      0x018 - 0x024 */

+  __IO uint32_t DR;             /*!< PSSI data register,                    Address offset: 0x028 */

+  __IO uint32_t RESERVED2[241]; /*!< Reserved,                                      0x02C - 0x3EC */

+  __IO uint32_t HWCFGR;         /*!< PSSI IP HW configuration register,     Address offset: 0x3F0 */

+  __IO uint32_t VERR;           /*!< PSSI IP version register,              Address offset: 0x3F4 */

+  __IO uint32_t IPIDR;          /*!< PSSI IP ID register,                   Address offset: 0x3F8 */

+  __IO uint32_t SIDR;           /*!< PSSI SIZE ID register,                 Address offset: 0x3FC */

+} PSSI_TypeDef;

+

+/**

+  * @brief DMA Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */

+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */

+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */

+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */

+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */

+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */

+} DMA_Stream_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */

+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */

+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */

+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */

+} DMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CCR;          /*!< DMA channel x configuration register          */

+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register         */

+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register     */

+  __IO uint32_t CM0AR;        /*!< DMA channel x memory 0 address register       */

+  __IO uint32_t CM1AR;        /*!< DMA channel x memory 1 address register       */

+} BDMA_Channel_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */

+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */

+} BDMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CCR;        /*!< DMA Multiplexer Channel x Control Register   */

+}DMAMUX_Channel_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CSR;      /*!< DMA Channel Status Register     */

+  __IO uint32_t  CFR;      /*!< DMA Channel Clear Flag Register */

+}DMAMUX_ChannelStatus_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  RGCR;        /*!< DMA Request Generator x Control Register   */

+}DMAMUX_RequestGen_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  RGSR;        /*!< DMA Request Generator Status Register       */

+  __IO uint32_t  RGCFR;       /*!< DMA Request Generator Clear Flag Register   */

+}DMAMUX_RequestGenStatus_TypeDef;

+

+/**

+  * @brief MDMA Controller

+  */

+typedef struct

+{

+  __IO uint32_t  GISR0;   /*!< MDMA Global Interrupt/Status Register 0,          Address offset: 0x00 */

+}MDMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CISR;      /*!< MDMA channel x interrupt/status register,             Address offset: 0x40 */

+  __IO uint32_t  CIFCR;     /*!< MDMA channel x interrupt flag clear register,         Address offset: 0x44 */

+  __IO uint32_t  CESR;      /*!< MDMA Channel x error status register,                 Address offset: 0x48 */

+  __IO uint32_t  CCR;       /*!< MDMA channel x control register,                      Address offset: 0x4C */

+  __IO uint32_t  CTCR;      /*!< MDMA channel x Transfer Configuration register,       Address offset: 0x50 */

+  __IO uint32_t  CBNDTR;    /*!< MDMA Channel x block number of data register,         Address offset: 0x54 */

+  __IO uint32_t  CSAR;      /*!< MDMA channel x source address register,               Address offset: 0x58 */

+  __IO uint32_t  CDAR;      /*!< MDMA channel x destination address register,          Address offset: 0x5C */

+  __IO uint32_t  CBRUR;     /*!< MDMA channel x Block Repeat address Update register,  Address offset: 0x60 */

+  __IO uint32_t  CLAR;      /*!< MDMA channel x Link Address register,                 Address offset: 0x64 */

+  __IO uint32_t  CTBR;      /*!< MDMA channel x Trigger and Bus selection Register,    Address offset: 0x68 */

+  uint32_t       RESERVED0; /*!< Reserved, 0x68                                                             */

+  __IO uint32_t  CMAR;      /*!< MDMA channel x Mask address register,                 Address offset: 0x70 */

+  __IO uint32_t  CMDR;      /*!< MDMA channel x Mask Data register,                    Address offset: 0x74 */

+}MDMA_Channel_TypeDef;

+

+/**

+  * @brief DMA2D Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */

+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */

+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */

+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */

+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */

+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */

+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */

+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */

+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */

+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */

+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */

+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */

+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */

+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */

+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */

+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */

+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */

+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */

+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */

+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */

+  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */

+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */

+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */

+} DMA2D_TypeDef;

+

+

+/**

+  * @brief External Interrupt/Event Controller

+  */

+

+typedef struct

+{

+__IO uint32_t RTSR1;               /*!< EXTI Rising trigger selection register,          Address offset: 0x00 */

+__IO uint32_t FTSR1;               /*!< EXTI Falling trigger selection register,         Address offset: 0x04 */

+__IO uint32_t SWIER1;              /*!< EXTI Software interrupt event register,          Address offset: 0x08 */

+__IO uint32_t D3PMR1;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */

+__IO uint32_t D3PCR1L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L)     Address offset: 0x10 */

+__IO uint32_t D3PCR1H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H)   Address offset: 0x14 */

+uint32_t      RESERVED1[2];        /*!< Reserved,                                        0x18 to 0x1C         */

+__IO uint32_t RTSR2;               /*!< EXTI Rising trigger selection register,          Address offset: 0x20 */

+__IO uint32_t FTSR2;               /*!< EXTI Falling trigger selection register,         Address offset: 0x24 */

+__IO uint32_t SWIER2;              /*!< EXTI Software interrupt event register,          Address offset: 0x28 */

+__IO uint32_t D3PMR2;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */

+__IO uint32_t D3PCR2L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L)  Address offset: 0x30 */

+__IO uint32_t D3PCR2H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */

+uint32_t      RESERVED2[2];        /*!< Reserved,                                        0x38 to 0x3C         */

+__IO uint32_t RTSR3;               /*!< EXTI Rising trigger selection register,          Address offset: 0x40 */

+__IO uint32_t FTSR3;               /*!< EXTI Falling trigger selection register,         Address offset: 0x44 */

+__IO uint32_t SWIER3;              /*!< EXTI Software interrupt event register,          Address offset: 0x48 */

+__IO uint32_t D3PMR3;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */

+__IO uint32_t D3PCR3L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */

+__IO uint32_t D3PCR3H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */

+uint32_t      RESERVED3[10];       /*!< Reserved,                                        0x58 to 0x7C         */

+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                    Address offset: 0x80 */

+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                        Address offset: 0x84 */

+__IO uint32_t PR1;                 /*!< EXTI Pending register,                           Address offset: 0x88 */

+uint32_t      RESERVED4;           /*!< Reserved,                                        0x8C                 */

+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                    Address offset: 0x90 */

+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                        Address offset: 0x94 */

+__IO uint32_t PR2;                 /*!< EXTI Pending register,                           Address offset: 0x98 */

+uint32_t      RESERVED5;           /*!< Reserved,                                        0x9C                 */

+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                    Address offset: 0xA0 */

+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                        Address offset: 0xA4 */

+__IO uint32_t PR3;                 /*!< EXTI Pending register,                           Address offset: 0xA8 */

+}EXTI_TypeDef;

+

+typedef struct

+{

+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                Address offset: 0x00 */

+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                    Address offset: 0x04 */

+__IO uint32_t PR1;                 /*!< EXTI Pending register,                       Address offset: 0x08 */

+uint32_t      RESERVED1;           /*!< Reserved, 0x0C                                                    */

+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                Address offset: 0x10 */

+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                    Address offset: 0x14 */

+__IO uint32_t PR2;                 /*!< EXTI Pending register,                       Address offset: 0x18 */

+uint32_t      RESERVED2;           /*!< Reserved, 0x1C                                                    */

+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                Address offset: 0x20 */

+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                    Address offset: 0x24 */

+__IO uint32_t PR3;                 /*!< EXTI Pending register,                       Address offset: 0x28 */

+}EXTI_Core_TypeDef;

+

+

+/**

+  * @brief FLASH Registers

+  */

+

+typedef struct

+{

+  __IO uint32_t ACR;             /*!< FLASH access control register,                            Address offset: 0x00  */

+  __IO uint32_t KEYR1;           /*!< Flash Key Register for bank1,                             Address offset: 0x04  */

+  __IO uint32_t OPTKEYR;         /*!< Flash Option Key Register,                                Address offset: 0x08  */

+  __IO uint32_t CR1;             /*!< Flash Control Register for bank1,                         Address offset: 0x0C  */

+  __IO uint32_t SR1;             /*!< Flash Status Register for bank1,                          Address offset: 0x10  */

+  __IO uint32_t CCR1;            /*!< Flash Control Register for bank1,                         Address offset: 0x14  */

+  __IO uint32_t OPTCR;           /*!< Flash Option Control Register,                            Address offset: 0x18  */

+  __IO uint32_t OPTSR_CUR;       /*!< Flash Option Status Current Register,                     Address offset: 0x1C  */

+  __IO uint32_t OPTSR_PRG;       /*!< Flash Option Status to Program Register,                  Address offset: 0x20  */

+  __IO uint32_t OPTCCR;          /*!< Flash Option Clear Control Register,                      Address offset: 0x24  */

+  __IO uint32_t PRAR_CUR1;       /*!< Flash Current Protection Address Register for bank1,      Address offset: 0x28  */

+  __IO uint32_t PRAR_PRG1;       /*!< Flash Protection Address to Program Register for bank1,   Address offset: 0x2C  */

+  __IO uint32_t SCAR_CUR1;       /*!< Flash Current Secure Address Register for bank1,          Address offset: 0x30  */

+  __IO uint32_t SCAR_PRG1;       /*!< Flash Secure Address to Program Register for bank1,       Address offset: 0x34  */

+  __IO uint32_t WPSN_CUR1;       /*!< Flash Current Write Protection Register on bank1,         Address offset: 0x38  */

+  __IO uint32_t WPSN_PRG1;       /*!< Flash Write Protection to Program Register on bank1,      Address offset: 0x3C  */

+  __IO uint32_t BOOT_CUR;        /*!< Flash Current Boot Address for Pelican Core Register,     Address offset: 0x40  */

+  __IO uint32_t BOOT_PRG;        /*!< Flash Boot Address to Program for Pelican Core Register,  Address offset: 0x44  */

+  uint32_t      RESERVED0[2];    /*!< Reserved, 0x48 to 0x4C                                                          */

+  __IO uint32_t CRCCR1;          /*!< Flash CRC Control register For Bank1 Register ,           Address offset: 0x50  */

+  __IO uint32_t CRCSADD1;        /*!< Flash CRC Start Address Register for Bank1 ,              Address offset: 0x54  */

+  __IO uint32_t CRCEADD1;        /*!< Flash CRC End Address Register for Bank1 ,                Address offset: 0x58  */

+  __IO uint32_t CRCDATA;         /*!< Flash CRC Data Register for Bank1 ,                       Address offset: 0x5C  */

+  __IO uint32_t ECC_FA1;         /*!< Flash ECC Fail Address For Bank1 Register ,               Address offset: 0x60  */

+  uint32_t      RESERVED;        /*!< Reserved, 0x64                                                                  */

+  __IO uint32_t OTPBL_CUR;       /*!< Flash Current OTP Block Lock Register,                    Address offset: 0x68  */

+  __IO uint32_t OTPBL_PRG;       /*!< Flash OTP Block Lock to Program Register,                 Address offset: 0x6C  */

+  uint32_t      RESERVED1[37];   /*!< Reserved, 0x70 to 0x100                                                         */

+  __IO uint32_t KEYR2;           /*!< Flash Key Register for bank2,                             Address offset: 0x104 */

+  uint32_t      RESERVED2;       /*!< Reserved, 0x108                                                                 */

+  __IO uint32_t CR2;             /*!< Flash Control Register for bank2,                         Address offset: 0x10C */

+  __IO uint32_t SR2;             /*!< Flash Status Register for bank2,                          Address offset: 0x110 */

+  __IO uint32_t CCR2;            /*!< Flash Status Register for bank2,                          Address offset: 0x114 */

+  uint32_t      RESERVED3[4];    /*!< Reserved, 0x118 to 0x124                                                        */

+  __IO uint32_t PRAR_CUR2;       /*!< Flash Current Protection Address Register for bank2,      Address offset: 0x128 */

+  __IO uint32_t PRAR_PRG2;       /*!< Flash Protection Address to Program Register for bank2,   Address offset: 0x12C */

+  __IO uint32_t SCAR_CUR2;       /*!< Flash Current Secure Address Register for bank2,          Address offset: 0x130 */

+  __IO uint32_t SCAR_PRG2;       /*!< Flash Secure Address Register for bank2,                  Address offset: 0x134 */

+  __IO uint32_t WPSN_CUR2;       /*!< Flash Current Write Protection Register on bank2,         Address offset: 0x138 */

+  __IO uint32_t WPSN_PRG2;       /*!< Flash Write Protection to Program Register on bank2,      Address offset: 0x13C */

+  uint32_t      RESERVED4[4];    /*!< Reserved, 0x140 to 0x14C                                                        */

+  __IO uint32_t CRCCR2;          /*!< Flash CRC Control register For Bank2 Register ,           Address offset: 0x150 */

+  __IO uint32_t CRCSADD2;        /*!< Flash CRC Start Address Register for Bank2 ,              Address offset: 0x154 */

+  __IO uint32_t CRCEADD2;        /*!< Flash CRC End Address Register for Bank2 ,                Address offset: 0x158 */

+  __IO uint32_t CRCDATA2;        /*!< Flash CRC Data Register for Bank2 ,                       Address offset: 0x15C */

+  __IO uint32_t ECC_FA2;         /*!< Flash ECC Fail Address For Bank2 Register ,               Address offset: 0x160 */

+} FLASH_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */

+} FMC_Bank1_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank1E

+  */

+

+typedef struct

+{

+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */

+} FMC_Bank1E_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank2

+  */

+

+typedef struct

+{

+  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */

+  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */

+  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */

+  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */

+  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */

+  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */

+} FMC_Bank2_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank3

+  */

+

+typedef struct

+{

+  __IO uint32_t PCR;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */

+  __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */

+  __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */

+  __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */

+  uint32_t      RESERVED;  /*!< Reserved, 0x90                                                            */

+  __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */

+} FMC_Bank3_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank5 and 6

+  */

+

+

+typedef struct

+{

+  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */

+  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */

+  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */

+  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */

+  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */

+} FMC_Bank5_6_TypeDef;

+

+/**

+  * @brief GFXMMU registers

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;              /*!< GFXMMU configuration register,                     Address offset: 0x00 */

+  __IO uint32_t SR;              /*!< GFXMMU status register,                            Address offset: 0x04 */

+  __IO uint32_t FCR;             /*!< GFXMMU flag clear register,                        Address offset: 0x08 */

+  __IO uint32_t CCR;             /*!< GFXMMU Cache Control Register,                     Address offset: 0x0C */

+  __IO uint32_t DVR;             /*!< GFXMMU default value register,                     Address offset: 0x10 */

+       uint32_t RESERVED1[3];    /*!< Reserved1,                                         Address offset: 0x14 to 0x1C */

+  __IO uint32_t B0CR;            /*!< GFXMMU buffer 0 configuration register,            Address offset: 0x20 */

+  __IO uint32_t B1CR;            /*!< GFXMMU buffer 1 configuration register,            Address offset: 0x24 */

+  __IO uint32_t B2CR;            /*!< GFXMMU buffer 2 configuration register,            Address offset: 0x28 */

+  __IO uint32_t B3CR;            /*!< GFXMMU buffer 3 configuration register,            Address offset: 0x2C */

+       uint32_t RESERVED2[1012]; /*!< Reserved2,                                         Address offset: 0x30 to 0xFFC */

+  __IO uint32_t LUT[2048];       /*!< GFXMMU LUT registers,                              Address offset: 0x1000 to 0x2FFC

+                                      For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */

+} GFXMMU_TypeDef;

+/**

+  * @brief General Purpose I/O

+  */

+

+typedef struct

+{

+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */

+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */

+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */

+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */

+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */

+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */

+  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset,               Address offset: 0x18      */

+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */

+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */

+} GPIO_TypeDef;

+

+/**

+  * @brief Operational Amplifier (OPAMP)

+  */

+

+typedef struct

+{

+  __IO uint32_t CSR;          /*!< OPAMP control/status register,                      Address offset: 0x00 */

+  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,     Address offset: 0x04 */

+  __IO uint32_t HSOTR;        /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */

+} OPAMP_TypeDef;

+

+/**

+  * @brief System configuration controller

+  */

+

+typedef struct

+{

+ uint32_t RESERVED1;           /*!< Reserved,                                           Address offset: 0x00        */

+ __IO uint32_t PMCR;           /*!< SYSCFG peripheral mode configuration register,      Address offset: 0x04        */

+ __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration registers,  Address offset: 0x08-0x14   */

+ __IO uint32_t CFGR;           /*!< SYSCFG configuration registers,                     Address offset: 0x18        */

+ uint32_t RESERVED2;           /*!< Reserved,                                           Address offset: 0x1C        */

+ __IO uint32_t CCCSR;          /*!< SYSCFG compensation cell control/status register,   Address offset: 0x20        */

+ __IO uint32_t CCVR;           /*!< SYSCFG compensation cell value register,            Address offset: 0x24        */

+ __IO uint32_t CCCR;           /*!< SYSCFG compensation cell code register,             Address offset: 0x28        */

+

+} SYSCFG_TypeDef;

+

+/**

+  * @brief Inter-integrated Circuit Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */

+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */

+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */

+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */

+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */

+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */

+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */

+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */

+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */

+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */

+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */

+} I2C_TypeDef;

+

+/**

+  * @brief Independent WATCHDOG

+  */

+

+typedef struct

+{

+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */

+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */

+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */

+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */

+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */

+} IWDG_TypeDef;

+

+

+/**

+  * @brief JPEG Codec

+  */

+typedef struct

+{

+  __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */

+  __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */

+  __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */

+  __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */

+  __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */

+  __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */

+  __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */

+  __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */

+  uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */

+  __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */

+  __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */

+  __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */

+  uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */

+  __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */

+  __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */

+  uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */

+  __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */

+  __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */

+  __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */

+  __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */

+  __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */

+  __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */

+  __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */

+  __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */

+  uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */

+  __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0,                 Address offset: 500h-65Ch */

+  __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1,                 Address offset: 660h-7BCh */

+  __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encodor, DC Huffman table 0,                 Address offset: 7C0h-7DCh */

+  __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encodor, DC Huffman table 1,                 Address offset: 7E0h-7FCh */

+

+} JPEG_TypeDef;

+

+/**

+  * @brief LCD-TFT Display Controller

+  */

+

+typedef struct

+{

+  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04                                                       */

+  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */

+  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */

+  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */

+  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */

+  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */

+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20                                                       */

+  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */

+  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28                                                            */

+  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */

+  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30                                                            */

+  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */

+  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */

+  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */

+  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */

+  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */

+  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */

+} LTDC_TypeDef;

+

+/**

+  * @brief LCD-TFT Display layer x Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */

+  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */

+  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */

+  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */

+  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */

+  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */

+  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */

+  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */

+  uint32_t      RESERVED0[2];  /*!< Reserved */

+  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */

+  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */

+  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */

+  uint32_t      RESERVED1[3];  /*!< Reserved */

+  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */

+

+} LTDC_Layer_TypeDef;

+

+/**

+  * @brief Power Control

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;       /*!< PWR power control register 1,            Address offset: 0x00 */

+  __IO uint32_t CSR1;      /*!< PWR power control status register 1,     Address offset: 0x04 */

+  __IO uint32_t CR2;       /*!< PWR power control register 2,            Address offset: 0x08 */

+  __IO uint32_t CR3;       /*!< PWR power control register 3,            Address offset: 0x0C */

+  __IO uint32_t CPUCR;     /*!< PWR CPU control register,                Address offset: 0x10 */

+       uint32_t RESERVED0; /*!< Reserved,                                Address offset: 0x14 */

+  __IO uint32_t SRDCR;     /*!< PWR SRD domain control register,         Address offset: 0x18 */

+       uint32_t RESERVED1; /*!< Reserved,                                Address offset: 0x1C */

+  __IO uint32_t WKUPCR;    /*!< PWR wakeup clear register,               Address offset: 0x20 */

+  __IO uint32_t WKUPFR;    /*!< PWR wakeup flag register,                Address offset: 0x24 */

+  __IO uint32_t WKUPEPR;   /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */

+} PWR_TypeDef;

+

+/**

+  * @brief Reset and Clock Control

+  */

+

+typedef struct

+{

+ __IO uint32_t CR;             /*!< RCC clock control register,                                              Address offset: 0x00  */

+ __IO uint32_t HSICFGR;        /*!< HSI Clock Calibration Register,                                          Address offset: 0x04  */

+ __IO uint32_t CRRCR;          /*!< Clock Recovery RC  Register,                                             Address offset: 0x08  */

+ __IO uint32_t CSICFGR;        /*!< CSI Clock Calibration Register,                                          Address offset: 0x0C  */

+ __IO uint32_t CFGR;           /*!< RCC clock configuration register,                                        Address offset: 0x10  */

+ uint32_t     RESERVED1;       /*!< Reserved,                                                                Address offset: 0x14  */

+ __IO uint32_t CDCFGR1;         /*!< RCC Domain 1 configuration register,                                    Address offset: 0x18  */

+ __IO uint32_t CDCFGR2;         /*!< RCC Domain 2 configuration register,                                    Address offset: 0x1C  */

+ __IO uint32_t SRDCFGR;         /*!< RCC Domain 3 configuration register,                                    Address offset: 0x20  */

+ uint32_t     RESERVED2;       /*!< Reserved,                                                                Address offset: 0x24  */

+ __IO uint32_t PLLCKSELR;      /*!< RCC PLLs Clock Source Selection Register,                                Address offset: 0x28  */

+ __IO uint32_t PLLCFGR;        /*!< RCC PLLs  Configuration Register,                                        Address offset: 0x2C  */

+ __IO uint32_t PLL1DIVR;       /*!< RCC PLL1 Dividers Configuration Register,                                Address offset: 0x30  */

+ __IO uint32_t PLL1FRACR;      /*!< RCC PLL1 Fractional Divider Configuration Register,                      Address offset: 0x34  */

+ __IO uint32_t PLL2DIVR;       /*!< RCC PLL2 Dividers Configuration Register,                                Address offset: 0x38  */

+ __IO uint32_t PLL2FRACR;      /*!< RCC PLL2 Fractional Divider Configuration Register,                      Address offset: 0x3C  */

+ __IO uint32_t PLL3DIVR;       /*!< RCC PLL3 Dividers Configuration Register,                                Address offset: 0x40  */

+ __IO uint32_t PLL3FRACR;      /*!< RCC PLL3 Fractional Divider Configuration Register,                      Address offset: 0x44  */

+ uint32_t      RESERVED3;      /*!< Reserved,                                                                Address offset: 0x48  */

+ __IO uint32_t  CDCCIPR;       /*!< RCC Domain 1 Kernel Clock Configuration Register                         Address offset: 0x4C  */

+ __IO uint32_t  CDCCIP1R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x50  */

+ __IO uint32_t  CDCCIP2R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x54  */

+ __IO uint32_t  SRDCCIPR;       /*!< RCC Domain 3 Kernel Clock Configuration Register                         Address offset: 0x58  */

+ uint32_t      RESERVED4;      /*!< Reserved,                                                                Address offset: 0x5C  */

+ __IO uint32_t  CIER;          /*!< RCC Clock Source Interrupt Enable Register                               Address offset: 0x60  */

+ __IO uint32_t  CIFR;          /*!< RCC Clock Source Interrupt Flag Register                                 Address offset: 0x64  */

+ __IO uint32_t  CICR;          /*!< RCC Clock Source Interrupt Clear Register                                Address offset: 0x68  */

+ uint32_t     RESERVED5;       /*!< Reserved,                                                                Address offset: 0x6C  */

+ __IO uint32_t  BDCR;          /*!< RCC Vswitch Backup Domain Control Register,                              Address offset: 0x70  */

+ __IO uint32_t  CSR;           /*!< RCC clock control & status register,                                     Address offset: 0x74  */

+ uint32_t     RESERVED6;       /*!< Reserved,                                                                Address offset: 0x78  */

+ __IO uint32_t AHB3RSTR;       /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x7C  */

+ __IO uint32_t AHB1RSTR;       /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x80  */

+ __IO uint32_t AHB2RSTR;       /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x84  */

+ __IO uint32_t AHB4RSTR;       /*!< RCC AHB4 peripheral reset register,                                      Address offset: 0x88  */

+ __IO uint32_t APB3RSTR;       /*!< RCC APB3 peripheral reset register,                                      Address offset: 0x8C  */

+ __IO uint32_t APB1LRSTR;      /*!< RCC APB1 peripheral reset Low Word register,                             Address offset: 0x90  */

+ __IO uint32_t APB1HRSTR;      /*!< RCC APB1 peripheral reset High Word register,                            Address offset: 0x94  */

+ __IO uint32_t APB2RSTR;       /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x98  */

+ __IO uint32_t APB4RSTR;       /*!< RCC APB4 peripheral reset register,                                      Address offset: 0x9C  */

+ uint32_t     RESERVED7;       /*!< Reserved,                                                                Address offset: 0xA0  */

+ uint32_t     RESERVED8;       /*!< Reserved,                                                                Address offset: 0xA4  */

+ __IO uint32_t SRDAMR;         /*!< RCC Domain 3 Autonomous Mode Register,                                   Address offset: 0xA8  */

+  uint32_t     RESERVED9;      /*!< Reserved, 0xAC-0xAF                                                      Address offset: 0xAC  */

+ __IO uint32_t CKGAENR;        /*!< AXI Clocks Gating Enable Register,                                       Address offset: 0xB0  */

+  uint32_t     RESERVED10[31];   /*!< Reserved, 0xAC-0xAF                                                    Address offset: 0xAC  */

+ __IO uint32_t RSR;            /*!< RCC Reset status register,                                               Address offset: 0xD0  */

+ __IO uint32_t AHB3ENR;        /*!< RCC AHB3 peripheral clock  register,                                     Address offset: 0xD4  */

+ __IO uint32_t AHB1ENR;        /*!< RCC AHB1 peripheral clock  register,                                     Address offset: 0xD8  */

+ __IO uint32_t AHB2ENR;        /*!< RCC AHB2 peripheral clock  register,                                     Address offset: 0xDC  */

+ __IO uint32_t AHB4ENR;        /*!< RCC AHB4 peripheral clock  register,                                     Address offset: 0xE0  */

+ __IO uint32_t APB3ENR;        /*!< RCC APB3 peripheral clock  register,                                     Address offset: 0xE4  */

+ __IO uint32_t APB1LENR;       /*!< RCC APB1 peripheral clock  Low Word register,                            Address offset: 0xE8  */

+ __IO uint32_t APB1HENR;       /*!< RCC APB1 peripheral clock  High Word register,                           Address offset: 0xEC  */

+ __IO uint32_t APB2ENR;        /*!< RCC APB2 peripheral clock  register,                                     Address offset: 0xF0  */

+ __IO uint32_t APB4ENR;        /*!< RCC APB4 peripheral clock  register,                                     Address offset: 0xF4  */

+ uint32_t      RESERVED12;      /*!< Reserved,                                                                Address offset: 0xF8  */

+ __IO uint32_t AHB3LPENR;      /*!< RCC AHB3 peripheral sleep clock  register,                               Address offset: 0xFC  */

+ __IO uint32_t AHB1LPENR;      /*!< RCC AHB1 peripheral sleep clock  register,                               Address offset: 0x100 */

+ __IO uint32_t AHB2LPENR;      /*!< RCC AHB2 peripheral sleep clock  register,                               Address offset: 0x104 */

+ __IO uint32_t AHB4LPENR;      /*!< RCC AHB4 peripheral sleep clock  register,                               Address offset: 0x108 */

+ __IO uint32_t APB3LPENR;      /*!< RCC APB3 peripheral sleep clock  register,                               Address offset: 0x10C */

+ __IO uint32_t APB1LLPENR;     /*!< RCC APB1 peripheral sleep clock  Low Word register,                      Address offset: 0x110 */

+ __IO uint32_t APB1HLPENR;     /*!< RCC APB1 peripheral sleep clock  High Word register,                     Address offset: 0x114 */

+ __IO uint32_t APB2LPENR;      /*!< RCC APB2 peripheral sleep clock  register,                               Address offset: 0x118 */

+ __IO uint32_t APB4LPENR;      /*!< RCC APB4 peripheral sleep clock  register,                               Address offset: 0x11C */

+ uint32_t     RESERVED13[4];   /*!< Reserved, 0x120-0x12C                                                    Address offset: 0x120 */

+

+} RCC_TypeDef;

+

+

+/**

+  * @brief Real-Time Clock

+  */

+typedef struct

+{

+  __IO uint32_t TR;             /*!< RTC time register,                              Address offset: 0x00 */

+  __IO uint32_t DR;             /*!< RTC date register,                              Address offset: 0x04 */

+  __IO uint32_t SSR;            /*!< RTC sub second register,                        Address offset: 0x08 */

+  __IO uint32_t ICSR;           /*!< RTC initialization control and status register, Address offset: 0x0C */

+  __IO uint32_t PRER;           /*!< RTC prescaler register,                         Address offset: 0x10 */

+  __IO uint32_t WUTR;           /*!< RTC wakeup timer register,                      Address offset: 0x14 */

+  __IO uint32_t CR;             /*!< RTC control register,                           Address offset: 0x18 */

+       uint32_t RESERVED0;      /*!< Reserved,                                       Address offset: 0x1C */

+       uint32_t RESERVED1;      /*!< Reserved,                                       Address offset: 0x20 */

+  __IO uint32_t WPR;            /*!< RTC write protection register,                  Address offset: 0x24 */

+  __IO uint32_t CALR;           /*!< RTC calibration register,                       Address offset: 0x28 */

+  __IO uint32_t SHIFTR;         /*!< RTC shift control register,                     Address offset: 0x2C */

+  __IO uint32_t TSTR;           /*!< RTC time stamp time register,                   Address offset: 0x30 */

+  __IO uint32_t TSDR;           /*!< RTC time stamp date register,                   Address offset: 0x34 */

+  __IO uint32_t TSSSR;          /*!< RTC time-stamp sub second register,             Address offset: 0x38 */

+       uint32_t RESERVED2;      /*!< Reserved,                                       Address offset: 0x3C */

+  __IO uint32_t ALRMAR;         /*!< RTC alarm A register,                           Address offset: 0x40 */

+  __IO uint32_t ALRMASSR;       /*!< RTC alarm A sub second register,                Address offset: 0x44 */

+  __IO uint32_t ALRMBR;         /*!< RTC alarm B register,                           Address offset: 0x48 */

+  __IO uint32_t ALRMBSSR;       /*!< RTC alarm B sub second register,                Address offset: 0x4C */

+  __IO uint32_t SR;             /*!< RTC Status register,                            Address offset: 0x50 */

+  __IO uint32_t MISR;           /*!< RTC masked interrupt status register,           Address offset: 0x54 */

+       uint32_t RESERVED3;      /*!< Reserved,                                       Address offset: 0x58 */

+  __IO uint32_t SCR;            /*!< RTC status Clear register,                      Address offset: 0x5C */

+  __IO uint32_t CFGR;           /*!< RTC configuration register,                     Address offset: 0x60 */

+} RTC_TypeDef;

+

+/**

+  * @brief Tamper and backup registers

+  */

+typedef struct

+{

+  __IO uint32_t CR1;            /*!< TAMP configuration register 1,            Address offset: 0x00 */

+  __IO uint32_t CR2;            /*!< TAMP configuration register 2,            Address offset: 0x04 */

+       uint32_t RESERVED0;      /*!< Reserved,                                 Address offset: 0x08 */

+  __IO uint32_t FLTCR;          /*!< TAMP filter control register,             Address offset: 0x0C */

+  __IO uint32_t ATCR1;          /*!< TAMP active tamper control register,      Address offset: 0x10 */

+  __IO uint32_t ATSEEDR;        /*!< TAMP active tamper seed register,         Address offset: 0x14 */

+  __IO uint32_t ATOR;           /*!< TAMP active tamper output register,       Address offset: 0x18 */

+       uint32_t RESERVED1[4];   /*!< Reserved,                                 Address offset: 0x1C -- 0x28 */

+  __IO uint32_t IER;            /*!< TAMP interrupt enable register,           Address offset: 0x2C */

+  __IO uint32_t SR;             /*!< TAMP status register,                     Address offset: 0x30 */

+  __IO uint32_t MISR;           /*!< TAMP masked interrupt status register,    Address offset: 0x34 */

+       uint32_t RESERVED2;      /*!< Reserved,                                 Address offset: 0x38 */

+  __IO uint32_t SCR;            /*!< TAMP status clear register,               Address offset: 0x3C */

+  __IO uint32_t COUNTR;         /*!< TAMP monotonic counter register,          Address offset: 0x40 */

+       uint32_t RESERVED3[3];   /*!< Reserved,                                 Address offset: 0x44 -- 0x4C */

+  __IO uint32_t CFGR;           /*!< TAMP configuration register,              Address offset: 0x50 */

+       uint32_t RESERVED4[43];  /*!< Reserved,                                 Address offset: 0x54 -- 0xFC */

+  __IO uint32_t BKP0R;          /*!< TAMP backup register 0,                   Address offset: 0x100 */

+  __IO uint32_t BKP1R;          /*!< TAMP backup register 1,                   Address offset: 0x104 */

+  __IO uint32_t BKP2R;          /*!< TAMP backup register 2,                   Address offset: 0x108 */

+  __IO uint32_t BKP3R;          /*!< TAMP backup register 3,                   Address offset: 0x10C */

+  __IO uint32_t BKP4R;          /*!< TAMP backup register 4,                   Address offset: 0x110 */

+  __IO uint32_t BKP5R;          /*!< TAMP backup register 5,                   Address offset: 0x114 */

+  __IO uint32_t BKP6R;          /*!< TAMP backup register 6,                   Address offset: 0x118 */

+  __IO uint32_t BKP7R;          /*!< TAMP backup register 7,                   Address offset: 0x11C */

+  __IO uint32_t BKP8R;          /*!< TAMP backup register 8,                   Address offset: 0x120 */

+  __IO uint32_t BKP9R;          /*!< TAMP backup register 9,                   Address offset: 0x124 */

+  __IO uint32_t BKP10R;         /*!< TAMP backup register 10,                  Address offset: 0x128 */

+  __IO uint32_t BKP11R;         /*!< TAMP backup register 11,                  Address offset: 0x12C */

+  __IO uint32_t BKP12R;         /*!< TAMP backup register 12,                  Address offset: 0x130 */

+  __IO uint32_t BKP13R;         /*!< TAMP backup register 13,                  Address offset: 0x134 */

+  __IO uint32_t BKP14R;         /*!< TAMP backup register 14,                  Address offset: 0x138 */

+  __IO uint32_t BKP15R;         /*!< TAMP backup register 15,                  Address offset: 0x13C */

+  __IO uint32_t BKP16R;         /*!< TAMP backup register 16,                  Address offset: 0x140 */

+  __IO uint32_t BKP17R;         /*!< TAMP backup register 17,                  Address offset: 0x144 */

+  __IO uint32_t BKP18R;         /*!< TAMP backup register 18,                  Address offset: 0x148 */

+  __IO uint32_t BKP19R;         /*!< TAMP backup register 19,                  Address offset: 0x14C */

+  __IO uint32_t BKP20R;         /*!< TAMP backup register 20,                  Address offset: 0x150 */

+  __IO uint32_t BKP21R;         /*!< TAMP backup register 21,                  Address offset: 0x154 */

+  __IO uint32_t BKP22R;         /*!< TAMP backup register 22,                  Address offset: 0x158 */

+  __IO uint32_t BKP23R;         /*!< TAMP backup register 23,                  Address offset: 0x15C */

+  __IO uint32_t BKP24R;         /*!< TAMP backup register 24,                  Address offset: 0x160 */

+  __IO uint32_t BKP25R;         /*!< TAMP backup register 25,                  Address offset: 0x164 */

+  __IO uint32_t BKP26R;         /*!< TAMP backup register 26,                  Address offset: 0x168 */

+  __IO uint32_t BKP27R;         /*!< TAMP backup register 27,                  Address offset: 0x16C */

+  __IO uint32_t BKP28R;         /*!< TAMP backup register 28,                  Address offset: 0x170 */

+  __IO uint32_t BKP29R;         /*!< TAMP backup register 29,                  Address offset: 0x174 */

+  __IO uint32_t BKP30R;         /*!< TAMP backup register 30,                  Address offset: 0x178 */

+  __IO uint32_t BKP31R;         /*!< TAMP backup register 31,                  Address offset: 0x17C */

+} TAMP_TypeDef;

+

+/**

+  * @brief Serial Audio Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t GCR;           /*!< SAI global configuration register, Address offset: 0x00 */

+  uint32_t      RESERVED0[16]; /*!< Reserved, 0x04 - 0x43                                   */

+  __IO uint32_t PDMCR;         /*!< SAI PDM control register,          Address offset: 0x44 */

+  __IO uint32_t PDMDLY;        /*!< SAI PDM delay register,            Address offset: 0x48 */

+} SAI_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */

+  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */

+  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */

+  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */

+  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */

+  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */

+  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */

+  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */

+} SAI_Block_TypeDef;

+

+/**

+  * @brief SPDIF-RX Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */

+  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */

+  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */

+  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */

+  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */

+  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */

+  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */

+  uint32_t        RESERVED2;    /*!< Reserved,  0x1A                                          */

+} SPDIFRX_TypeDef;

+

+

+/**

+  * @brief Secure digital input/output Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t POWER;          /*!< SDMMC power control register,             Address offset: 0x00  */

+  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,             Address offset: 0x04  */

+  __IO uint32_t ARG;            /*!< SDMMC argument register,                  Address offset: 0x08  */

+  __IO uint32_t CMD;            /*!< SDMMC command register,                   Address offset: 0x0C  */

+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register,          Address offset: 0x10  */

+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                Address offset: 0x14  */

+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                Address offset: 0x18  */

+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                Address offset: 0x1C  */

+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                Address offset: 0x20  */

+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                Address offset: 0x24  */

+  __IO uint32_t DLEN;           /*!< SDMMC data length register,               Address offset: 0x28  */

+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,              Address offset: 0x2C  */

+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,              Address offset: 0x30  */

+  __I uint32_t  STA;            /*!< SDMMC status register,                    Address offset: 0x34  */

+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,           Address offset: 0x38  */

+  __IO uint32_t MASK;           /*!< SDMMC mask register,                      Address offset: 0x3C  */

+  __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,     Address offset: 0x40  */

+  uint32_t      RESERVED0[3];   /*!< Reserved, 0x44 - 0x4C - 0x4C                                    */

+  __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,               Address offset: 0x50  */

+  __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,           Address offset: 0x54  */

+  __IO uint32_t IDMABASE0;      /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58  */

+  __IO uint32_t IDMABASE1;      /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C  */

+  uint32_t      RESERVED1[8];   /*!< Reserved, 0x60-0x7C                                             */

+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,                 Address offset: 0x80  */

+  uint32_t      RESERVED2[222]; /*!< Reserved, 0x84-0x3F8                                            */

+  __IO uint32_t IPVR;           /*!< SDMMC data FIFO register,                 Address offset: 0x3FC */

+} SDMMC_TypeDef;

+

+

+/**

+  * @brief Delay Block DLYB

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;          /*!< DELAY BLOCK control register,  Address offset: 0x00 */

+  __IO uint32_t CFGR;        /*!< DELAY BLOCK configuration register,  Address offset: 0x04 */

+} DLYB_TypeDef;

+

+/**

+  * @brief HW Semaphore HSEM

+  */

+

+typedef struct

+{

+  __IO uint32_t R[32];      /*!< 2-step write lock and read back registers,     Address offset: 00h-7Ch  */

+  __IO uint32_t RLR[32];    /*!< 1-step read lock registers,                    Address offset: 80h-FCh  */

+  __IO uint32_t C1IER;      /*!< HSEM Interrupt enable register ,             Address offset: 100h     */

+  __IO uint32_t C1ICR;      /*!< HSEM Interrupt clear register ,              Address offset: 104h     */

+  __IO uint32_t C1ISR;      /*!< HSEM Interrupt Status register ,             Address offset: 108h     */

+  __IO uint32_t C1MISR;     /*!< HSEM Interrupt Masked Status register ,      Address offset: 10Ch     */

+  uint32_t  Reserved[12];   /* Reserved                                       Address offset: 110h-13Ch  */

+  __IO uint32_t CR;         /*!< HSEM Semaphore clear register ,                Address offset: 140h      */

+  __IO uint32_t KEYR;       /*!< HSEM Semaphore clear key register ,            Address offset: 144h      */

+

+} HSEM_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t IER;        /*!< HSEM interrupt enable register ,                Address offset:   0h     */

+  __IO uint32_t ICR;        /*!< HSEM interrupt clear register ,                 Address offset:   4h     */

+  __IO uint32_t ISR;        /*!< HSEM interrupt status register ,                Address offset:   8h     */

+  __IO uint32_t MISR;       /*!< HSEM masked interrupt status register ,         Address offset:   Ch     */

+} HSEM_Common_TypeDef;

+

+/**

+  * @brief Serial Peripheral Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */

+  __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */

+  __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */

+  __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */

+  __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */

+  __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */

+  __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */

+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */

+  __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */

+  uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */

+  __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */

+  uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */

+  __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */

+  __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */

+  __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */

+  __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */

+  __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */

+

+} SPI_TypeDef;

+

+/**

+  * @brief DTS

+  */

+typedef struct

+{

+  __IO uint32_t CFGR1;         /*!< DTS configuration register,                Address offset: 0x00 */

+  uint32_t RESERVED0;          /*!< Reserved,                                  Address offset: 0x04 */

+  __IO uint32_t T0VALR1;       /*!< DTS T0 Value register,                     Address offset: 0x08 */

+  uint32_t RESERVED1;          /*!< Reserved,                                  Address offset: 0x0C */

+  __IO uint32_t RAMPVALR;      /*!< DTS Ramp value register,                   Address offset: 0x10 */

+  __IO uint32_t ITR1;          /*!< DTS Interrupt threshold register,          Address offset: 0x14 */

+  uint32_t RESERVED2;          /*!< Reserved,                                  Address offset: 0x18 */

+  __IO uint32_t DR;            /*!< DTS data register,                         Address offset: 0x1C */

+  __IO uint32_t SR;            /*!< DTS status register                        Address offset: 0x20 */

+  __IO uint32_t ITENR;         /*!< DTS Interrupt enable register,             Address offset: 0x24 */

+  __IO uint32_t ICIFR;         /*!< DTS Clear Interrupt flag register,         Address offset: 0x28 */

+  __IO uint32_t OR;            /*!< DTS option register 1,                     Address offset: 0x2C */

+}

+DTS_TypeDef;

+

+/**

+  * @brief TIM

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */

+  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */

+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */

+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */

+  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */

+  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */

+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */

+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */

+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */

+  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */

+  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */

+  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */

+  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */

+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */

+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */

+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */

+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */

+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */

+  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */

+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */

+  uint32_t      RESERVED1;   /*!< Reserved, 0x50                                                 */

+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */

+  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */

+  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */

+  __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */

+  __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */

+  __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x68 */

+} TIM_TypeDef;

+

+/**

+  * @brief LPTIMIMER

+  */

+typedef struct

+{

+  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,         Address offset: 0x00 */

+  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,              Address offset: 0x04 */

+  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,             Address offset: 0x08 */

+  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                Address offset: 0x0C */

+  __IO uint32_t CR;       /*!< LPTIM Control register,                      Address offset: 0x10 */

+  __IO uint32_t CMP;      /*!< LPTIM Compare register,                      Address offset: 0x14 */

+  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                   Address offset: 0x18 */

+  __IO uint32_t CNT;      /*!< LPTIM Counter register,                      Address offset: 0x1C */

+  uint32_t  RESERVED1;    /*!< Reserved, 0x20                                                    */

+  __IO uint32_t CFGR2;    /*!< LPTIM Configuration register,                Address offset: 0x24 */

+} LPTIM_TypeDef;

+

+/**

+  * @brief Comparator

+  */

+typedef struct

+{

+  __IO uint32_t SR;        /*!< Comparator status register,                    Address offset: 0x00 */

+  __IO uint32_t ICFR;      /*!< Comparator interrupt clear flag register,       Address offset: 0x04 */

+  __IO uint32_t OR;        /*!< Comparator option register,                  Address offset: 0x08 */

+} COMPOPT_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CFGR;      /*!< Comparator configuration register  ,           Address offset: 0x00 */

+} COMP_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CFGR;       /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */

+} COMP_Common_TypeDef;

+/**

+  * @brief Universal Synchronous Asynchronous Receiver Transmitter

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */

+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */

+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */

+  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */

+  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */

+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */

+  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */

+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */

+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */

+  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */

+  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */

+  __IO uint32_t PRESC;  /*!< USART clock Prescaler register,           Address offset: 0x2C */

+} USART_TypeDef;

+

+/**

+  * @brief Single Wire Protocol Master Interface SPWMI

+  */

+typedef struct

+{

+  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */

+  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */

+    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */

+  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */

+  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */

+  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */

+  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */

+  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */

+  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */

+  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */

+} SWPMI_TypeDef;

+

+/**

+  * @brief Window WATCHDOG

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */

+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */

+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */

+} WWDG_TypeDef;

+

+

+/**

+  * @brief RAM_ECC_Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t CR;           /*!< RAMECC monitor configuration register          */

+  __IO uint32_t SR;           /*!< RAMECC monitor status register                 */

+  __IO uint32_t FAR;          /*!< RAMECC monitor failing address register        */

+  __IO uint32_t FDRL;         /*!< RAMECC monitor failing data low register       */

+  __IO uint32_t FDRH;         /*!< RAMECC monitor failing data high register      */

+  __IO uint32_t FECR;         /*!< RAMECC monitor failing ECC error code register */

+} RAMECC_MonitorTypeDef;

+

+typedef struct

+{

+  __IO uint32_t IER;          /*!< RAMECC interrupt enable register */

+} RAMECC_TypeDef;

+/**

+  * @}

+  */

+

+

+

+/**

+  * @brief RNG

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */

+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */

+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */

+  uint32_t RESERVED;

+  __IO uint32_t HTCR;  /*!< RNG health test configuration register, Address offset: 0x10 */

+} RNG_TypeDef;

+

+/**

+  * @brief MDIOS

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;

+  __IO uint32_t WRFR;

+  __IO uint32_t CWRFR;

+  __IO uint32_t RDFR;

+  __IO uint32_t CRDFR;

+  __IO uint32_t SR;

+  __IO uint32_t CLRFR;

+  uint32_t RESERVED[57];

+  __IO uint32_t DINR0;

+  __IO uint32_t DINR1;

+  __IO uint32_t DINR2;

+  __IO uint32_t DINR3;

+  __IO uint32_t DINR4;

+  __IO uint32_t DINR5;

+  __IO uint32_t DINR6;

+  __IO uint32_t DINR7;

+  __IO uint32_t DINR8;

+  __IO uint32_t DINR9;

+  __IO uint32_t DINR10;

+  __IO uint32_t DINR11;

+  __IO uint32_t DINR12;

+  __IO uint32_t DINR13;

+  __IO uint32_t DINR14;

+  __IO uint32_t DINR15;

+  __IO uint32_t DINR16;

+  __IO uint32_t DINR17;

+  __IO uint32_t DINR18;

+  __IO uint32_t DINR19;

+  __IO uint32_t DINR20;

+  __IO uint32_t DINR21;

+  __IO uint32_t DINR22;

+  __IO uint32_t DINR23;

+  __IO uint32_t DINR24;

+  __IO uint32_t DINR25;

+  __IO uint32_t DINR26;

+  __IO uint32_t DINR27;

+  __IO uint32_t DINR28;

+  __IO uint32_t DINR29;

+  __IO uint32_t DINR30;

+  __IO uint32_t DINR31;

+  __IO uint32_t DOUTR0;

+  __IO uint32_t DOUTR1;

+  __IO uint32_t DOUTR2;

+  __IO uint32_t DOUTR3;

+  __IO uint32_t DOUTR4;

+  __IO uint32_t DOUTR5;

+  __IO uint32_t DOUTR6;

+  __IO uint32_t DOUTR7;

+  __IO uint32_t DOUTR8;

+  __IO uint32_t DOUTR9;

+  __IO uint32_t DOUTR10;

+  __IO uint32_t DOUTR11;

+  __IO uint32_t DOUTR12;

+  __IO uint32_t DOUTR13;

+  __IO uint32_t DOUTR14;

+  __IO uint32_t DOUTR15;

+  __IO uint32_t DOUTR16;

+  __IO uint32_t DOUTR17;

+  __IO uint32_t DOUTR18;

+  __IO uint32_t DOUTR19;

+  __IO uint32_t DOUTR20;

+  __IO uint32_t DOUTR21;

+  __IO uint32_t DOUTR22;

+  __IO uint32_t DOUTR23;

+  __IO uint32_t DOUTR24;

+  __IO uint32_t DOUTR25;

+  __IO uint32_t DOUTR26;

+  __IO uint32_t DOUTR27;

+  __IO uint32_t DOUTR28;

+  __IO uint32_t DOUTR29;

+  __IO uint32_t DOUTR30;

+  __IO uint32_t DOUTR31;

+} MDIOS_TypeDef;

+

+

+/**

+  * @brief USB_OTG_Core_Registers

+  */

+typedef struct

+{

+ __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */

+  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */

+  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */

+  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */

+  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */

+  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */

+  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */

+  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */

+  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */

+  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */

+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */

+  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */

+  uint32_t Reserved30[2];             /*!< Reserved                                     030h */

+  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */

+  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */

+  __IO uint32_t GSNPSID;              /* USB_OTG core ID                                040h*/

+  __IO uint32_t GHWCFG1;              /* User HW config1                                044h*/

+  __IO uint32_t GHWCFG2;              /* User HW config2                                048h*/

+  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */

+  uint32_t  Reserved6;                /*!< Reserved                                     050h */

+  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */

+  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */

+  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */

+   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */

+    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */

+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */

+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */

+} USB_OTG_GlobalTypeDef;

+

+

+/**

+  * @brief USB_OTG_device_Registers

+  */

+typedef struct

+{

+  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */

+  __IO uint32_t DCTL;            /*!< dev Control Register         804h */

+  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */

+  uint32_t Reserved0C;           /*!< Reserved                     80Ch */

+  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */

+  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */

+  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */

+  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */

+  uint32_t  Reserved20;          /*!< Reserved                     820h */

+  uint32_t Reserved9;            /*!< Reserved                     824h */

+  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */

+  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */

+  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */

+  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */

+  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */

+  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */

+  uint32_t Reserved40;           /*!< dedicated EP mask            840h */

+  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */

+  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */

+  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */

+} USB_OTG_DeviceTypeDef;

+

+

+/**

+  * @brief USB_OTG_IN_Endpoint-Specific_Register

+  */

+typedef struct

+{

+  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */

+  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */

+  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */

+  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */

+  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */

+  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */

+  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */

+  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */

+} USB_OTG_INEndpointTypeDef;

+

+

+/**

+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */

+  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */

+  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */

+  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */

+  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */

+  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */

+  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */

+} USB_OTG_OUTEndpointTypeDef;

+

+

+/**

+  * @brief USB_OTG_Host_Mode_Register_Structures

+  */

+typedef struct

+{

+  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */

+  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */

+  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */

+  uint32_t Reserved40C;           /*!< Reserved                             40Ch */

+  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */

+  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */

+  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */

+} USB_OTG_HostTypeDef;

+

+/**

+  * @brief USB_OTG_Host_Channel_Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */

+  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */

+  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */

+  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */

+  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */

+  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */

+  uint32_t Reserved[2];           /*!< Reserved                                      */

+} USB_OTG_HostChannelTypeDef;

+/**

+  * @}

+  */

+

+/**

+  * @brief OCTO Serial Peripheral Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;          /*!< OCTOSPI Control register,                           Address offset: 0x000 */

+  uint32_t RESERVED;         /*!< Reserved,                                           Address offset: 0x004 */

+  __IO uint32_t DCR1;        /*!< OCTOSPI Device Configuration register 1,            Address offset: 0x008 */

+  __IO uint32_t DCR2;        /*!< OCTOSPI Device Configuration register 2,            Address offset: 0x00C */

+  __IO uint32_t DCR3;        /*!< OCTOSPI Device Configuration register 3,            Address offset: 0x010 */

+  __IO uint32_t DCR4;        /*!< OCTOSPI Device Configuration register 4,            Address offset: 0x014 */

+  uint32_t RESERVED1[2];     /*!< Reserved,                                           Address offset: 0x018-0x01C */

+  __IO uint32_t SR;          /*!< OCTOSPI Status register,                            Address offset: 0x020 */

+  __IO uint32_t FCR;         /*!< OCTOSPI Flag Clear register,                        Address offset: 0x024 */

+  uint32_t RESERVED2[6];     /*!< Reserved,                                           Address offset: 0x028-0x03C */

+  __IO uint32_t DLR;         /*!< OCTOSPI Data Length register,                       Address offset: 0x040 */

+  uint32_t RESERVED3;        /*!< Reserved,                                           Address offset: 0x044 */

+  __IO uint32_t AR;          /*!< OCTOSPI Address register,                           Address offset: 0x048 */

+  uint32_t RESERVED4;        /*!< Reserved,                                           Address offset: 0x04C */

+  __IO uint32_t DR;          /*!< OCTOSPI Data register,                              Address offset: 0x050 */

+  uint32_t RESERVED5[11];    /*!< Reserved,                                           Address offset: 0x054-0x07C */

+  __IO uint32_t PSMKR;       /*!< OCTOSPI Polling Status Mask register,               Address offset: 0x080 */

+  uint32_t RESERVED6;        /*!< Reserved,                                           Address offset: 0x084 */

+  __IO uint32_t PSMAR;       /*!< OCTOSPI Polling Status Match register,              Address offset: 0x088 */

+  uint32_t RESERVED7;        /*!< Reserved,                                           Address offset: 0x08C */

+  __IO uint32_t PIR;         /*!< OCTOSPI Polling Interval register,                  Address offset: 0x090 */

+  uint32_t RESERVED8[27];    /*!< Reserved,                                           Address offset: 0x094-0x0FC */

+  __IO uint32_t CCR;         /*!< OCTOSPI Communication Configuration register,       Address offset: 0x100 */

+  uint32_t RESERVED9;        /*!< Reserved,                                           Address offset: 0x104 */

+  __IO uint32_t TCR;         /*!< OCTOSPI Timing Configuration register,              Address offset: 0x108 */

+  uint32_t RESERVED10;       /*!< Reserved,                                           Address offset: 0x10C */

+  __IO uint32_t IR;          /*!< OCTOSPI Instruction register,                       Address offset: 0x110 */

+  uint32_t RESERVED11[3];    /*!< Reserved,                                           Address offset: 0x114-0x11C */

+  __IO uint32_t ABR;         /*!< OCTOSPI Alternate Bytes register,                   Address offset: 0x120 */

+  uint32_t RESERVED12[3];    /*!< Reserved,                                           Address offset: 0x124-0x12C */

+  __IO uint32_t LPTR;        /*!< OCTOSPI Low Power Timeout register,                 Address offset: 0x130 */

+  uint32_t RESERVED13[3];    /*!< Reserved,                                           Address offset: 0x134-0x13C */

+  __IO uint32_t WPCCR;       /*!< OCTOSPI Wrap Communication Configuration register,  Address offset: 0x140 */

+  uint32_t RESERVED14;       /*!< Reserved,                                           Address offset: 0x144 */

+  __IO uint32_t WPTCR;       /*!< OCTOSPI Wrap Timing Configuration register,         Address offset: 0x148 */

+  uint32_t RESERVED15;       /*!< Reserved,                                           Address offset: 0x14C */

+  __IO uint32_t WPIR;        /*!< OCTOSPI Wrap Instruction register,                  Address offset: 0x150 */

+  uint32_t RESERVED16[3];    /*!< Reserved,                                           Address offset: 0x154-0x15C */

+  __IO uint32_t WPABR;       /*!< OCTOSPI Wrap Alternate Bytes register,              Address offset: 0x160 */

+  uint32_t RESERVED17[7];    /*!< Reserved,                                           Address offset: 0x164-0x17C */

+  __IO uint32_t WCCR;        /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */

+  uint32_t RESERVED18;       /*!< Reserved,                                           Address offset: 0x184 */

+  __IO uint32_t WTCR;        /*!< OCTOSPI Write Timing Configuration register,        Address offset: 0x188 */

+  uint32_t RESERVED19;       /*!< Reserved,                                           Address offset: 0x18C */

+  __IO uint32_t WIR;         /*!< OCTOSPI Write Instruction register,                 Address offset: 0x190 */

+  uint32_t RESERVED20[3];    /*!< Reserved,                                           Address offset: 0x194-0x19C */

+  __IO uint32_t WABR;        /*!< OCTOSPI Write Alternate Bytes register,             Address offset: 0x1A0 */

+  uint32_t RESERVED21[23];   /*!< Reserved,                                           Address offset: 0x1A4-0x1FC */

+  __IO uint32_t HLCR;        /*!< OCTOSPI Hyperbus Latency Configuration register,    Address offset: 0x200 */

+  uint32_t RESERVED22[122];  /*!< Reserved,                                           Address offset: 0x204-0x3EC */

+  __IO uint32_t HWCFGR;      /*!< OCTOSPI HW Configuration register,                  Address offset: 0x3F0 */

+  __IO uint32_t VER;         /*!< OCTOSPI Version register,                           Address offset: 0x3F4 */

+  __IO uint32_t ID;          /*!< OCTOSPI Identification register,                    Address offset: 0x3F8 */

+  __IO uint32_t MID;         /*!< OCTOPSI HW Magic ID register,                       Address offset: 0x3FC */

+} OCTOSPI_TypeDef;

+

+/**

+  * @}

+  */

+/**

+  * @brief OCTO Serial Peripheral Interface IO Manager

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;          /*!< OCTOSPI IO Manager Control register,                 Address offset: 0x00 */

+  __IO uint32_t PCR[3];      /*!< OCTOSPI IO Manager Port[1:3] Configuration register, Address offset: 0x04-0x20 */

+} OCTOSPIM_TypeDef;

+

+/**

+  * @}

+  */

+

+/** @addtogroup Peripheral_memory_map

+  * @{

+  */

+#define CD_ITCMRAM_BASE           (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM  */

+#define CD_DTCMRAM_BASE           (0x20000000UL) /*!< Base address of : 128KB (2x64KB) system data RAM accessible over DTCM                   */

+#define CD_AXIFLASH_BASE          (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI                */

+

+#define CD_AXISRAM1_BASE          (0x24000000UL) /*!< Base address of : (up to 256KB) system data RAM1 accessible over over AXI                */

+#define CD_AXISRAM2_BASE          (0x24040000UL) /*!< Base address of : (up to 384KB) system data RAM2 accessible over over AXI                */

+#define CD_AXISRAM3_BASE          (0x240A0000UL) /*!< Base address of : (up to 384KB) system data RAM3 accessible over over AXI                */

+#define CD_AHBSRAM1_BASE          (0x30000000UL) /*!< Base address of : (up to 64KB) system data RAM1 accessible over over AXI->AHB Bridge     */

+#define CD_AHBSRAM2_BASE          (0x30010000UL) /*!< Base address of : (up to 64KB) system data RAM2 accessible over over AXI->AHB Bridge     */

+

+#define SRD_BKPSRAM_BASE           (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge                                */

+#define SRD_SRAM_BASE              (0x38000000UL) /*!< Base address of : Backup SRAM(32 KB) over AXI->AHB Bridge                               */

+

+#define OCTOSPI1_BASE             (0x90000000UL) /*!< Base address of : OCTOSPI1 memories  accessible over AXI                                 */

+#define OCTOSPI2_BASE             (0x70000000UL) /*!< Base address of : OCTOSPI2 memories  accessible over AXI                                 */

+

+#define FLASH_BANK1_BASE          (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI                          */

+#define FLASH_BANK2_BASE          (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI                          */

+#define FLASH_END                 (0x081FFFFFUL) /*!< FLASH end address                                                                       */

+

+/* Legacy define */

+#define FLASH_BASE                FLASH_BANK1_BASE

+#define D1_AXISRAM_BASE           CD_AXISRAM1_BASE

+

+#define FLASH_OTP_BASE            (0x08FFF000UL) /*!< Base address of : (up to 1KB) embedded FLASH Bank1 OTP Area                           */

+#define FLASH_OTP_END             (0x08FFF3FFUL) /*!< End address of : (up to 1KB) embedded FLASH Bank1 OTP Area                            */

+

+

+/*!< Device electronic signature memory map */

+#define UID_BASE                  (0x08FFF800UL)            /*!< Unique device ID register base address */

+#define FLASHSIZE_BASE            (0x08FFF80CUL)            /*!< FLASH Size register base address */

+#define PACKAGE_BASE              (0x08FFF80EUL)            /*!< Package Data register base address */

+

+#define PERIPH_BASE               (0x40000000UL) /*!< Base address of : AHB/ABP Peripherals                                                    */

+/*!< Peripheral memory map */

+#define CD_APB1PERIPH_BASE        PERIPH_BASE                   /*!<  D2_APB1PERIPH_BASE        PERIPH_BASE                                    */

+#define CD_APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)   /*!<  D2_APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)                    */

+#define CD_AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)   /*!<  D2_AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)                    */

+#define CD_AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)   /*!<  D2_AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)                    */

+

+#define CD_APB3PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)   /*!<  D1_APB1PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)                    */

+#define CD_AHB3PERIPH_BASE       (PERIPH_BASE + 0x12000000UL)   /*!<  D1_AHB1PERIPH_BASE       (PERIPH_BASE + 0x12000000UL)                    */

+

+#define SRD_APB4PERIPH_BASE      (PERIPH_BASE + 0x18000000UL)   /*!<  D3_APB1PERIPH_BASE       (PERIPH_BASE + 0x18000000UL)                    */

+#define SRD_AHB4PERIPH_BASE      (PERIPH_BASE + 0x18020000UL)   /*!<  D3_AHB1PERIPH_BASE       (PERIPH_BASE + 0x18020000UL)                    */

+

+/*!< Legacy Peripheral memory map */

+#define APB1PERIPH_BASE        PERIPH_BASE

+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)

+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)

+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)

+

+/*!< CD_AHB3PERIPH peripherals */

+#define MDMA_BASE             (CD_AHB3PERIPH_BASE + 0x0000UL)

+#define DMA2D_BASE            (CD_AHB3PERIPH_BASE + 0x1000UL)

+#define FLASH_R_BASE          (CD_AHB3PERIPH_BASE + 0x2000UL)

+#define JPGDEC_BASE           (CD_AHB3PERIPH_BASE + 0x3000UL)

+#define FMC_R_BASE            (CD_AHB3PERIPH_BASE + 0x4000UL)

+#define OCTOSPI1_R_BASE       (CD_AHB3PERIPH_BASE + 0x5000UL)

+#define DLYB_OCTOSPI1_BASE    (CD_AHB3PERIPH_BASE + 0x6000UL)

+#define SDMMC1_BASE           (CD_AHB3PERIPH_BASE + 0x7000UL)

+#define DLYB_SDMMC1_BASE      (CD_AHB3PERIPH_BASE + 0x8000UL)

+#define RAMECC_BASE           (CD_AHB3PERIPH_BASE + 0x9000UL)

+#define OCTOSPI2_R_BASE       (CD_AHB3PERIPH_BASE + 0xA000UL)

+#define DLYB_OCTOSPI2_BASE    (CD_AHB3PERIPH_BASE + 0xB000UL)

+#define OCTOSPIM_BASE         (CD_AHB3PERIPH_BASE + 0xB400UL)

+

+/*!< CD_AHB1PERIPH peripherals */

+

+#define DMA1_BASE               (CD_AHB1PERIPH_BASE + 0x0000UL)

+#define DMA2_BASE               (CD_AHB1PERIPH_BASE + 0x0400UL)

+#define DMAMUX1_BASE            (CD_AHB1PERIPH_BASE + 0x0800UL)

+#define ADC1_BASE               (CD_AHB1PERIPH_BASE + 0x2000UL)

+#define ADC2_BASE               (CD_AHB1PERIPH_BASE + 0x2100UL)

+#define ADC12_COMMON_BASE       (CD_AHB1PERIPH_BASE + 0x2300UL)

+#define CRC_BASE                (CD_AHB1PERIPH_BASE + 0x3000UL)

+

+/*!< USB registers base address */

+#define USB1_OTG_HS_PERIPH_BASE              (0x40040000UL)

+#define USB_OTG_GLOBAL_BASE                  (0x000UL)

+#define USB_OTG_DEVICE_BASE                  (0x800UL)

+#define USB_OTG_IN_ENDPOINT_BASE             (0x900UL)

+#define USB_OTG_OUT_ENDPOINT_BASE            (0xB00UL)

+#define USB_OTG_EP_REG_SIZE                  (0x20UL)

+#define USB_OTG_HOST_BASE                    (0x400UL)

+#define USB_OTG_HOST_PORT_BASE               (0x440UL)

+#define USB_OTG_HOST_CHANNEL_BASE            (0x500UL)

+#define USB_OTG_HOST_CHANNEL_SIZE            (0x20UL)

+#define USB_OTG_PCGCCTL_BASE                 (0xE00UL)

+#define USB_OTG_FIFO_BASE                    (0x1000UL)

+#define USB_OTG_FIFO_SIZE                    (0x1000UL)

+

+/*!< CD_AHB2PERIPH peripherals */

+

+#define DCMI_BASE              (CD_AHB2PERIPH_BASE + 0x0000UL)

+#define PSSI_BASE              (CD_AHB2PERIPH_BASE + 0x0400UL)

+#define HSEM_BASE              (CD_AHB2PERIPH_BASE + 0x0800UL)

+#define RNG_BASE               (CD_AHB2PERIPH_BASE + 0x1800UL)

+#define SDMMC2_BASE            (CD_AHB2PERIPH_BASE + 0x2400UL)

+#define DLYB_SDMMC2_BASE       (CD_AHB2PERIPH_BASE + 0x2800UL)

+#define BDMA1_BASE             (CD_AHB2PERIPH_BASE + 0x2C00UL)

+

+/*!< SRD_AHB4PERIPH peripherals */

+#define GPIOA_BASE            (SRD_AHB4PERIPH_BASE + 0x0000UL)

+#define GPIOB_BASE            (SRD_AHB4PERIPH_BASE + 0x0400UL)

+#define GPIOC_BASE            (SRD_AHB4PERIPH_BASE + 0x0800UL)

+#define GPIOD_BASE            (SRD_AHB4PERIPH_BASE + 0x0C00UL)

+#define GPIOE_BASE            (SRD_AHB4PERIPH_BASE + 0x1000UL)

+#define GPIOF_BASE            (SRD_AHB4PERIPH_BASE + 0x1400UL)

+#define GPIOG_BASE            (SRD_AHB4PERIPH_BASE + 0x1800UL)

+#define GPIOH_BASE            (SRD_AHB4PERIPH_BASE + 0x1C00UL)

+#define GPIOI_BASE            (SRD_AHB4PERIPH_BASE + 0x2000UL)

+#define GPIOJ_BASE            (SRD_AHB4PERIPH_BASE + 0x2400UL)

+#define GPIOK_BASE            (SRD_AHB4PERIPH_BASE + 0x2800UL)

+#define RCC_BASE              (SRD_AHB4PERIPH_BASE + 0x4400UL)

+#define PWR_BASE              (SRD_AHB4PERIPH_BASE + 0x4800UL)

+#define BDMA2_BASE            (SRD_AHB4PERIPH_BASE + 0x5400UL)

+#define DMAMUX2_BASE          (SRD_AHB4PERIPH_BASE + 0x5800UL)

+

+/*!< CD_APB3PERIPH peripherals */

+#define LTDC_BASE             (CD_APB3PERIPH_BASE + 0x1000UL)

+#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84UL)

+#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104UL)

+#define WWDG1_BASE            (CD_APB3PERIPH_BASE + 0x3000UL)

+

+/*!< CD_APB1PERIPH peripherals */

+#define TIM2_BASE             (CD_APB1PERIPH_BASE + 0x0000UL)

+#define TIM3_BASE             (CD_APB1PERIPH_BASE + 0x0400UL)

+#define TIM4_BASE             (CD_APB1PERIPH_BASE + 0x0800UL)

+#define TIM5_BASE             (CD_APB1PERIPH_BASE + 0x0C00UL)

+#define TIM6_BASE             (CD_APB1PERIPH_BASE + 0x1000UL)

+#define TIM7_BASE             (CD_APB1PERIPH_BASE + 0x1400UL)

+#define TIM12_BASE            (CD_APB1PERIPH_BASE + 0x1800UL)

+#define TIM13_BASE            (CD_APB1PERIPH_BASE + 0x1C00UL)

+#define TIM14_BASE            (CD_APB1PERIPH_BASE + 0x2000UL)

+#define LPTIM1_BASE           (CD_APB1PERIPH_BASE + 0x2400UL)

+

+#define SPI2_BASE             (CD_APB1PERIPH_BASE + 0x3800UL)

+#define SPI3_BASE             (CD_APB1PERIPH_BASE + 0x3C00UL)

+#define SPDIFRX_BASE          (CD_APB1PERIPH_BASE + 0x4000UL)

+#define USART2_BASE           (CD_APB1PERIPH_BASE + 0x4400UL)

+#define USART3_BASE           (CD_APB1PERIPH_BASE + 0x4800UL)

+#define UART4_BASE            (CD_APB1PERIPH_BASE + 0x4C00UL)

+#define UART5_BASE            (CD_APB1PERIPH_BASE + 0x5000UL)

+#define I2C1_BASE             (CD_APB1PERIPH_BASE + 0x5400UL)

+#define I2C2_BASE             (CD_APB1PERIPH_BASE + 0x5800UL)

+#define I2C3_BASE             (CD_APB1PERIPH_BASE + 0x5C00UL)

+#define CEC_BASE              (CD_APB1PERIPH_BASE + 0x6C00UL)

+#define DAC1_BASE             (CD_APB1PERIPH_BASE + 0x7400UL)

+#define UART7_BASE            (CD_APB1PERIPH_BASE + 0x7800UL)

+#define UART8_BASE            (CD_APB1PERIPH_BASE + 0x7C00UL)

+#define CRS_BASE              (CD_APB1PERIPH_BASE + 0x8400UL)

+#define SWPMI1_BASE           (CD_APB1PERIPH_BASE + 0x8800UL)

+#define OPAMP_BASE            (CD_APB1PERIPH_BASE + 0x9000UL)

+#define OPAMP1_BASE           (CD_APB1PERIPH_BASE + 0x9000UL)

+#define OPAMP2_BASE           (CD_APB1PERIPH_BASE + 0x9010UL)

+#define MDIOS_BASE            (CD_APB1PERIPH_BASE + 0x9400UL)

+#define FDCAN1_BASE           (CD_APB1PERIPH_BASE + 0xA000UL)

+#define FDCAN2_BASE           (CD_APB1PERIPH_BASE + 0xA400UL)

+#define FDCAN_CCU_BASE        (CD_APB1PERIPH_BASE + 0xA800UL)

+#define SRAMCAN_BASE          (CD_APB1PERIPH_BASE + 0xAC00UL)

+

+/*!< CD_APB2PERIPH peripherals */

+

+#define TIM1_BASE             (CD_APB2PERIPH_BASE + 0x0000UL)

+#define TIM8_BASE             (CD_APB2PERIPH_BASE + 0x0400UL)

+#define USART1_BASE           (CD_APB2PERIPH_BASE + 0x1000UL)

+#define USART6_BASE           (CD_APB2PERIPH_BASE + 0x1400UL)

+#define UART9_BASE            (CD_APB2PERIPH_BASE + 0x1800UL)

+#define USART10_BASE          (CD_APB2PERIPH_BASE + 0x1C00UL)

+#define SPI1_BASE             (CD_APB2PERIPH_BASE + 0x3000UL)

+#define SPI4_BASE             (CD_APB2PERIPH_BASE + 0x3400UL)

+#define TIM15_BASE            (CD_APB2PERIPH_BASE + 0x4000UL)

+#define TIM16_BASE            (CD_APB2PERIPH_BASE + 0x4400UL)

+#define TIM17_BASE            (CD_APB2PERIPH_BASE + 0x4800UL)

+#define SPI5_BASE             (CD_APB2PERIPH_BASE + 0x5000UL)

+#define SAI1_BASE             (CD_APB2PERIPH_BASE + 0x5800UL)

+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)

+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)

+#define SAI2_BASE             (CD_APB2PERIPH_BASE + 0x5C00UL)

+#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004UL)

+#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024UL)

+#define DFSDM1_BASE           (CD_APB2PERIPH_BASE + 0x7800UL)

+#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00UL)

+#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20UL)

+#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40UL)

+#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60UL)

+#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80UL)

+#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0UL)

+#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0UL)

+#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0UL)

+#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)

+#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)

+#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)

+#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)

+#define DFSDM1_Filter4_BASE   (DFSDM1_BASE + 0x300UL)

+#define DFSDM1_Filter5_BASE   (DFSDM1_BASE + 0x380UL)

+#define DFSDM1_Filter6_BASE   (DFSDM1_BASE + 0x400UL)

+#define DFSDM1_Filter7_BASE   (DFSDM1_BASE + 0x480UL)

+/*!< SRD_APB4PERIPH peripherals */

+#define EXTI_BASE             (SRD_APB4PERIPH_BASE + 0x0000UL)

+#define EXTI_D1_BASE          (EXTI_BASE + 0x0080UL)

+#define SYSCFG_BASE           (SRD_APB4PERIPH_BASE + 0x0400UL)

+#define LPUART1_BASE          (SRD_APB4PERIPH_BASE + 0x0C00UL)

+#define SPI6_BASE             (SRD_APB4PERIPH_BASE + 0x1400UL)

+#define I2C4_BASE             (SRD_APB4PERIPH_BASE + 0x1C00UL)

+#define LPTIM2_BASE           (SRD_APB4PERIPH_BASE + 0x2400UL)

+#define LPTIM3_BASE           (SRD_APB4PERIPH_BASE + 0x2800UL)

+#define DAC2_BASE             (SRD_APB4PERIPH_BASE + 0x3400UL)

+#define COMP12_BASE           (SRD_APB4PERIPH_BASE + 0x3800UL)

+#define COMP1_BASE            (COMP12_BASE + 0x0CUL)

+#define COMP2_BASE            (COMP12_BASE + 0x10UL)

+#define VREFBUF_BASE          (SRD_APB4PERIPH_BASE + 0x3C00UL)

+#define RTC_BASE              (SRD_APB4PERIPH_BASE + 0x4000UL)

+#define TAMP_BASE             (SRD_APB4PERIPH_BASE + 0x4400UL)

+#define IWDG1_BASE            (SRD_APB4PERIPH_BASE + 0x4800UL)

+

+#define DTS_BASE              (SRD_APB4PERIPH_BASE + 0x6800UL)

+

+#define DFSDM2_BASE           (SRD_APB4PERIPH_BASE + 0x6C00UL)

+#define DFSDM2_Channel0_BASE  (DFSDM2_BASE + 0x00UL)

+#define DFSDM2_Channel1_BASE  (DFSDM2_BASE + 0x20UL)

+#define DFSDM2_FLT0_BASE      (DFSDM2_BASE + 0x100UL)

+

+/*!< CD_AHB3PERIPH peripherals */

+#define GFXMMU_BASE           (CD_AHB3PERIPH_BASE + 0xC000UL)

+

+#define BDMA1_Channel0_BASE    (BDMA1_BASE + 0x0008UL)

+#define BDMA1_Channel1_BASE    (BDMA1_BASE + 0x001CUL)

+#define BDMA1_Channel2_BASE    (BDMA1_BASE + 0x0030UL)

+#define BDMA1_Channel3_BASE    (BDMA1_BASE + 0x0044UL)

+#define BDMA1_Channel4_BASE    (BDMA1_BASE + 0x0058UL)

+#define BDMA1_Channel5_BASE    (BDMA1_BASE + 0x006CUL)

+#define BDMA1_Channel6_BASE    (BDMA1_BASE + 0x0080UL)

+#define BDMA1_Channel7_BASE    (BDMA1_BASE + 0x0094UL)

+

+#define BDMA2_Channel0_BASE    (BDMA2_BASE + 0x0008UL)

+#define BDMA2_Channel1_BASE    (BDMA2_BASE + 0x001CUL)

+#define BDMA2_Channel2_BASE    (BDMA2_BASE + 0x0030UL)

+#define BDMA2_Channel3_BASE    (BDMA2_BASE + 0x0044UL)

+#define BDMA2_Channel4_BASE    (BDMA2_BASE + 0x0058UL)

+#define BDMA2_Channel5_BASE    (BDMA2_BASE + 0x006CUL)

+#define BDMA2_Channel6_BASE    (BDMA2_BASE + 0x0080UL)

+#define BDMA2_Channel7_BASE    (BDMA2_BASE + 0x0094UL)

+

+

+#define DMAMUX2_Channel0_BASE    (DMAMUX2_BASE)

+#define DMAMUX2_Channel1_BASE    (DMAMUX2_BASE + 0x0004UL)

+#define DMAMUX2_Channel2_BASE    (DMAMUX2_BASE + 0x0008UL)

+#define DMAMUX2_Channel3_BASE    (DMAMUX2_BASE + 0x000CUL)

+#define DMAMUX2_Channel4_BASE    (DMAMUX2_BASE + 0x0010UL)

+#define DMAMUX2_Channel5_BASE    (DMAMUX2_BASE + 0x0014UL)

+#define DMAMUX2_Channel6_BASE    (DMAMUX2_BASE + 0x0018UL)

+#define DMAMUX2_Channel7_BASE    (DMAMUX2_BASE + 0x001CUL)

+

+#define DMAMUX2_RequestGenerator0_BASE  (DMAMUX2_BASE + 0x0100UL)

+#define DMAMUX2_RequestGenerator1_BASE  (DMAMUX2_BASE + 0x0104UL)

+#define DMAMUX2_RequestGenerator2_BASE  (DMAMUX2_BASE + 0x0108UL)

+#define DMAMUX2_RequestGenerator3_BASE  (DMAMUX2_BASE + 0x010CUL)

+#define DMAMUX2_RequestGenerator4_BASE  (DMAMUX2_BASE + 0x0110UL)

+#define DMAMUX2_RequestGenerator5_BASE  (DMAMUX2_BASE + 0x0114UL)

+#define DMAMUX2_RequestGenerator6_BASE  (DMAMUX2_BASE + 0x0118UL)

+#define DMAMUX2_RequestGenerator7_BASE  (DMAMUX2_BASE + 0x011CUL)

+

+#define DMAMUX2_ChannelStatus_BASE      (DMAMUX2_BASE + 0x0080UL)

+#define DMAMUX2_RequestGenStatus_BASE   (DMAMUX2_BASE + 0x0140UL)

+

+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)

+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)

+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)

+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)

+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)

+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)

+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)

+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)

+

+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)

+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)

+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)

+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)

+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)

+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)

+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)

+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)

+

+

+#define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)

+#define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)

+#define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)

+#define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)

+#define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)

+#define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)

+#define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0018UL)

+#define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x001CUL)

+#define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0020UL)

+#define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x0024UL)

+#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)

+#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)

+#define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)

+#define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)

+#define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)

+#define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)

+

+#define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)

+#define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)

+#define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)

+#define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)

+#define DMAMUX1_RequestGenerator4_BASE  (DMAMUX1_BASE + 0x0110UL)

+#define DMAMUX1_RequestGenerator5_BASE  (DMAMUX1_BASE + 0x0114UL)

+#define DMAMUX1_RequestGenerator6_BASE  (DMAMUX1_BASE + 0x0118UL)

+#define DMAMUX1_RequestGenerator7_BASE  (DMAMUX1_BASE + 0x011CUL)

+

+#define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)

+#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)

+

+/*!< FMC Banks registers base  address */

+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)

+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)

+#define FMC_Bank2_R_BASE      (FMC_R_BASE + 0x0060UL)

+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)

+#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)

+

+/* Debug MCU registers base address */

+#define DBGMCU_BASE           (0x5C001000UL)

+

+#define MDMA_Channel0_BASE    (MDMA_BASE + 0x00000040UL)

+#define MDMA_Channel1_BASE    (MDMA_BASE + 0x00000080UL)

+#define MDMA_Channel2_BASE    (MDMA_BASE + 0x000000C0UL)

+#define MDMA_Channel3_BASE    (MDMA_BASE + 0x00000100UL)

+#define MDMA_Channel4_BASE    (MDMA_BASE + 0x00000140UL)

+#define MDMA_Channel5_BASE    (MDMA_BASE + 0x00000180UL)

+#define MDMA_Channel6_BASE    (MDMA_BASE + 0x000001C0UL)

+#define MDMA_Channel7_BASE    (MDMA_BASE + 0x00000200UL)

+#define MDMA_Channel8_BASE    (MDMA_BASE + 0x00000240UL)

+#define MDMA_Channel9_BASE    (MDMA_BASE + 0x00000280UL)

+#define MDMA_Channel10_BASE   (MDMA_BASE + 0x000002C0UL)

+#define MDMA_Channel11_BASE   (MDMA_BASE + 0x00000300UL)

+#define MDMA_Channel12_BASE   (MDMA_BASE + 0x00000340UL)

+#define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)

+#define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)

+#define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)

+#define MDMA_Channel16_BASE   (MDMA_BASE + 0x00000440UL)

+

+/* GFXMMU virtual buffers base address */

+#define GFXMMU_VIRTUAL_BUFFERS_BASE  (0x25000000UL)

+#define GFXMMU_VIRTUAL_BUFFER0_BASE  (GFXMMU_VIRTUAL_BUFFERS_BASE)

+#define GFXMMU_VIRTUAL_BUFFER1_BASE  (GFXMMU_VIRTUAL_BUFFERS_BASE + 0x400000UL)

+#define GFXMMU_VIRTUAL_BUFFER2_BASE  (GFXMMU_VIRTUAL_BUFFERS_BASE + 0x800000UL)

+#define GFXMMU_VIRTUAL_BUFFER3_BASE  (GFXMMU_VIRTUAL_BUFFERS_BASE + 0xC00000UL)

+

+#define RAMECC_Monitor1_BASE (RAMECC_BASE + 0x20UL)

+#define RAMECC_Monitor2_BASE (RAMECC_BASE + 0x40UL)

+#define RAMECC_Monitor3_BASE (RAMECC_BASE + 0x60UL)

+

+/**

+  * @}

+  */

+

+/** @addtogroup Peripheral_declaration

+  * @{

+  */

+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)

+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)

+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)

+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)

+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)

+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)

+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)

+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)

+#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)

+#define RTC                 ((RTC_TypeDef *) RTC_BASE)

+#define TAMP                ((TAMP_TypeDef *) TAMP_BASE)

+#define WWDG1               ((WWDG_TypeDef *) WWDG1_BASE)

+

+

+#define IWDG1               ((IWDG_TypeDef *) IWDG1_BASE)

+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)

+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)

+#define SPI4                ((SPI_TypeDef *) SPI4_BASE)

+#define SPI5                ((SPI_TypeDef *) SPI5_BASE)

+#define SPI6                ((SPI_TypeDef *) SPI6_BASE)

+#define USART2              ((USART_TypeDef *) USART2_BASE)

+#define USART3              ((USART_TypeDef *) USART3_BASE)

+#define USART6              ((USART_TypeDef *) USART6_BASE)

+#define USART10             ((USART_TypeDef *) USART10_BASE)

+#define UART7               ((USART_TypeDef *) UART7_BASE)

+#define UART8               ((USART_TypeDef *) UART8_BASE)

+#define UART9               ((USART_TypeDef *) UART9_BASE)

+#define CRS                 ((CRS_TypeDef *) CRS_BASE)

+#define UART4               ((USART_TypeDef *) UART4_BASE)

+#define UART5               ((USART_TypeDef *) UART5_BASE)

+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)

+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)

+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)

+#define I2C4                ((I2C_TypeDef *) I2C4_BASE)

+#define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

+#define FDCAN2              ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

+#define FDCAN_CCU           ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

+#define CEC                 ((CEC_TypeDef *) CEC_BASE)

+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)

+#define PWR                 ((PWR_TypeDef *) PWR_BASE)

+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)

+#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)

+#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)

+#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)

+#define LPTIM3              ((LPTIM_TypeDef *) LPTIM3_BASE)

+#define DTS                 ((DTS_TypeDef *) DTS_BASE)

+

+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)

+#define COMP12              ((COMPOPT_TypeDef *) COMP12_BASE)

+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)

+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)

+#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)

+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)

+#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)

+#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)

+

+

+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)

+#define EXTI_D1             ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)

+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)

+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)

+#define USART1              ((USART_TypeDef *) USART1_BASE)

+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)

+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)

+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)

+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)

+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)

+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

+#define SAI2                ((SAI_TypeDef *) SAI2_BASE)

+#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)

+#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)

+

+#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

+#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

+#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

+#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

+#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

+#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

+#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

+#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

+#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

+#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

+#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

+#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

+#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

+#define DFSDM1_Filter4      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter4_BASE)

+#define DFSDM1_Filter5      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter5_BASE)

+#define DFSDM1_Filter6      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter6_BASE)

+#define DFSDM1_Filter7      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter7_BASE)

+#define DFSDM2_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel0_BASE)

+#define DFSDM2_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel1_BASE)

+#define DFSDM2_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM2_FLT0_BASE)

+#define DMA2D               ((DMA2D_TypeDef *) DMA2D_BASE)

+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)

+#define PSSI                ((PSSI_TypeDef *) PSSI_BASE)

+#define RCC                 ((RCC_TypeDef *) RCC_BASE)

+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)

+#define CRC                 ((CRC_TypeDef *) CRC_BASE)

+

+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)

+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)

+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)

+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)

+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)

+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)

+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)

+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)

+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)

+#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)

+#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)

+

+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)

+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)

+#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

+

+#define RNG                 ((RNG_TypeDef *) RNG_BASE)

+#define SDMMC2              ((SDMMC_TypeDef *) SDMMC2_BASE)

+#define DLYB_SDMMC2         ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

+

+#define BDMA1                ((BDMA_TypeDef *) BDMA1_BASE)

+#define BDMA1_Channel0       ((BDMA_Channel_TypeDef *) BDMA1_Channel0_BASE)

+#define BDMA1_Channel1       ((BDMA_Channel_TypeDef *) BDMA1_Channel1_BASE)

+#define BDMA1_Channel2       ((BDMA_Channel_TypeDef *) BDMA1_Channel2_BASE)

+#define BDMA1_Channel3       ((BDMA_Channel_TypeDef *) BDMA1_Channel3_BASE)

+#define BDMA1_Channel4       ((BDMA_Channel_TypeDef *) BDMA1_Channel4_BASE)

+#define BDMA1_Channel5       ((BDMA_Channel_TypeDef *) BDMA1_Channel5_BASE)

+#define BDMA1_Channel6       ((BDMA_Channel_TypeDef *) BDMA1_Channel6_BASE)

+#define BDMA1_Channel7       ((BDMA_Channel_TypeDef *) BDMA1_Channel7_BASE)

+

+#define BDMA2                ((BDMA_TypeDef *) BDMA2_BASE)

+#define BDMA2_Channel0       ((BDMA_Channel_TypeDef *) BDMA2_Channel0_BASE)

+#define BDMA2_Channel1       ((BDMA_Channel_TypeDef *) BDMA2_Channel1_BASE)

+#define BDMA2_Channel2       ((BDMA_Channel_TypeDef *) BDMA2_Channel2_BASE)

+#define BDMA2_Channel3       ((BDMA_Channel_TypeDef *) BDMA2_Channel3_BASE)

+#define BDMA2_Channel4       ((BDMA_Channel_TypeDef *) BDMA2_Channel4_BASE)

+#define BDMA2_Channel5       ((BDMA_Channel_TypeDef *) BDMA2_Channel5_BASE)

+#define BDMA2_Channel6       ((BDMA_Channel_TypeDef *) BDMA2_Channel6_BASE)

+#define BDMA2_Channel7       ((BDMA_Channel_TypeDef *) BDMA2_Channel7_BASE)

+

+#define RAMECC               ((RAMECC_TypeDef *)RAMECC_BASE)

+#define RAMECC_Monitor1      ((RAMECC_MonitorTypeDef *)RAMECC_Monitor1_BASE)

+#define RAMECC_Monitor2      ((RAMECC_MonitorTypeDef *)RAMECC_Monitor2_BASE)

+#define RAMECC_Monitor3      ((RAMECC_MonitorTypeDef *)RAMECC_Monitor3_BASE)

+

+#define DMAMUX2                ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

+#define DMAMUX2_Channel0       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

+#define DMAMUX2_Channel1       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

+#define DMAMUX2_Channel2       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

+#define DMAMUX2_Channel3       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

+#define DMAMUX2_Channel4       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

+#define DMAMUX2_Channel5       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

+#define DMAMUX2_Channel6       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

+#define DMAMUX2_Channel7       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

+

+

+#define DMAMUX2_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

+#define DMAMUX2_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

+#define DMAMUX2_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

+#define DMAMUX2_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

+#define DMAMUX2_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

+#define DMAMUX2_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

+#define DMAMUX2_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

+#define DMAMUX2_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

+

+#define DMAMUX2_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

+#define DMAMUX2_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

+

+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)

+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

+

+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)

+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

+

+

+#define DMAMUX1              ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

+#define DMAMUX1_Channel0     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

+#define DMAMUX1_Channel1     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

+#define DMAMUX1_Channel2     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

+#define DMAMUX1_Channel3     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

+#define DMAMUX1_Channel4     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

+#define DMAMUX1_Channel5     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

+#define DMAMUX1_Channel6     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

+#define DMAMUX1_Channel7     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

+#define DMAMUX1_Channel8     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

+#define DMAMUX1_Channel9     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

+#define DMAMUX1_Channel10    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

+#define DMAMUX1_Channel11    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

+#define DMAMUX1_Channel12    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

+#define DMAMUX1_Channel13    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

+#define DMAMUX1_Channel14    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

+#define DMAMUX1_Channel15    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

+

+#define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

+#define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

+#define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

+#define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

+#define DMAMUX1_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

+#define DMAMUX1_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

+#define DMAMUX1_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

+#define DMAMUX1_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

+

+#define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *)    DMAMUX1_ChannelStatus_BASE)

+#define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

+

+

+#define FMC_Bank1_R           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

+#define FMC_Bank1E_R          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

+#define FMC_Bank2_R           ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

+#define FMC_Bank3_R           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

+#define FMC_Bank5_6_R         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

+

+#define DAC2                ((DAC_TypeDef *) DAC2_BASE)

+#define OCTOSPI1            ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)

+#define DLYB_OCTOSPI1       ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE)

+#define OCTOSPI2            ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)

+#define DLYB_OCTOSPI2       ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE)

+#define OCTOSPIM            ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)

+#define GFXMMU              ((GFXMMU_TypeDef *) GFXMMU_BASE)

+

+#define SDMMC1                ((SDMMC_TypeDef *) SDMMC1_BASE)

+#define DLYB_SDMMC1           ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

+

+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)

+

+#define JPEG                ((JPEG_TypeDef *) JPGDEC_BASE)

+#define HSEM                ((HSEM_TypeDef *) HSEM_BASE)

+#define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

+

+#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)

+#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

+#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

+

+#define MDIOS               ((MDIOS_TypeDef *) MDIOS_BASE)

+

+#define MDMA                ((MDMA_TypeDef *)MDMA_BASE)

+#define MDMA_Channel0       ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

+#define MDMA_Channel1       ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

+#define MDMA_Channel2       ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

+#define MDMA_Channel3       ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

+#define MDMA_Channel4       ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

+#define MDMA_Channel5       ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

+#define MDMA_Channel6       ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

+#define MDMA_Channel7       ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

+#define MDMA_Channel8       ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

+#define MDMA_Channel9       ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

+#define MDMA_Channel10      ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

+#define MDMA_Channel11      ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

+#define MDMA_Channel12      ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

+#define MDMA_Channel13      ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

+#define MDMA_Channel14      ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

+#define MDMA_Channel15      ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

+

+

+#define USB1_OTG_HS         ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

+

+/* Legacy defines */

+#define USB_OTG_HS                   USB1_OTG_HS

+#define USB_OTG_HS_PERIPH_BASE       USB1_OTG_HS_PERIPH_BASE

+

+/**

+  * @}

+  */

+

+/** @addtogroup Exported_constants

+  * @{

+  */

+

+  /** @addtogroup Peripheral_Registers_Bits_Definition

+  * @{

+  */

+

+/******************************************************************************/

+/*                         Peripheral Registers_Bits_Definition               */

+/******************************************************************************/

+

+/******************************************************************************/

+/*                                                                            */

+/*                        Analog to Digital Converter                         */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  ADC VERSION  ********************************/

+#define ADC_VER_V5_3

+/********************  Bit definition for ADC_ISR register  ********************/

+#define ADC_ISR_ADRDY_Pos                 (0U)

+#define ADC_ISR_ADRDY_Msk                 (0x1UL << ADC_ISR_ADRDY_Pos)         /*!< 0x00000001 */

+#define ADC_ISR_ADRDY                     ADC_ISR_ADRDY_Msk                    /*!< ADC Ready (ADRDY) flag  */

+#define ADC_ISR_EOSMP_Pos                 (1U)

+#define ADC_ISR_EOSMP_Msk                 (0x1UL << ADC_ISR_EOSMP_Pos)         /*!< 0x00000002 */

+#define ADC_ISR_EOSMP                     ADC_ISR_EOSMP_Msk                    /*!< ADC End of Sampling flag */

+#define ADC_ISR_EOC_Pos                   (2U)

+#define ADC_ISR_EOC_Msk                   (0x1UL << ADC_ISR_EOC_Pos)           /*!< 0x00000004 */

+#define ADC_ISR_EOC                       ADC_ISR_EOC_Msk                      /*!< ADC End of Regular Conversion flag */

+#define ADC_ISR_EOS_Pos                   (3U)

+#define ADC_ISR_EOS_Msk                   (0x1UL << ADC_ISR_EOS_Pos)           /*!< 0x00000008 */

+#define ADC_ISR_EOS                       ADC_ISR_EOS_Msk                      /*!< ADC End of Regular sequence of Conversions flag */

+#define ADC_ISR_OVR_Pos                   (4U)

+#define ADC_ISR_OVR_Msk                   (0x1UL << ADC_ISR_OVR_Pos)           /*!< 0x00000010 */

+#define ADC_ISR_OVR                       ADC_ISR_OVR_Msk                      /*!< ADC overrun flag */

+#define ADC_ISR_JEOC_Pos                  (5U)

+#define ADC_ISR_JEOC_Msk                  (0x1UL << ADC_ISR_JEOC_Pos)          /*!< 0x00000020 */

+#define ADC_ISR_JEOC                      ADC_ISR_JEOC_Msk                     /*!< ADC End of Injected Conversion flag */

+#define ADC_ISR_JEOS_Pos                  (6U)

+#define ADC_ISR_JEOS_Msk                  (0x1UL << ADC_ISR_JEOS_Pos)          /*!< 0x00000040 */

+#define ADC_ISR_JEOS                      ADC_ISR_JEOS_Msk                     /*!< ADC End of Injected sequence of Conversions flag */

+#define ADC_ISR_AWD1_Pos                  (7U)

+#define ADC_ISR_AWD1_Msk                  (0x1UL << ADC_ISR_AWD1_Pos)          /*!< 0x00000080 */

+#define ADC_ISR_AWD1                      ADC_ISR_AWD1_Msk                     /*!< ADC Analog watchdog 1 flag */

+#define ADC_ISR_AWD2_Pos                  (8U)

+#define ADC_ISR_AWD2_Msk                  (0x1UL << ADC_ISR_AWD2_Pos)          /*!< 0x00000100 */

+#define ADC_ISR_AWD2                      ADC_ISR_AWD2_Msk                     /*!< ADC Analog watchdog 2 flag */

+#define ADC_ISR_AWD3_Pos                  (9U)

+#define ADC_ISR_AWD3_Msk                  (0x1UL << ADC_ISR_AWD3_Pos)          /*!< 0x00000200 */

+#define ADC_ISR_AWD3                      ADC_ISR_AWD3_Msk                     /*!< ADC Analog watchdog 3 flag */

+#define ADC_ISR_JQOVF_Pos                 (10U)

+#define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */

+#define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */

+

+/********************  Bit definition for ADC_IER register  ********************/

+#define ADC_IER_ADRDYIE_Pos               (0U)

+#define ADC_IER_ADRDYIE_Msk               (0x1UL << ADC_IER_ADRDYIE_Pos)       /*!< 0x00000001 */

+#define ADC_IER_ADRDYIE                   ADC_IER_ADRDYIE_Msk                  /*!< ADC Ready (ADRDY) interrupt source */

+#define ADC_IER_EOSMPIE_Pos               (1U)

+#define ADC_IER_EOSMPIE_Msk               (0x1UL << ADC_IER_EOSMPIE_Pos)       /*!< 0x00000002 */

+#define ADC_IER_EOSMPIE                   ADC_IER_EOSMPIE_Msk                  /*!< ADC End of Sampling interrupt source */

+#define ADC_IER_EOCIE_Pos                 (2U)

+#define ADC_IER_EOCIE_Msk                 (0x1UL << ADC_IER_EOCIE_Pos)         /*!< 0x00000004 */

+#define ADC_IER_EOCIE                     ADC_IER_EOCIE_Msk                    /*!< ADC End of Regular Conversion interrupt source */

+#define ADC_IER_EOSIE_Pos                 (3U)

+#define ADC_IER_EOSIE_Msk                 (0x1UL << ADC_IER_EOSIE_Pos)         /*!< 0x00000008 */

+#define ADC_IER_EOSIE                     ADC_IER_EOSIE_Msk                    /*!< ADC End of Regular sequence of Conversions interrupt source */

+#define ADC_IER_OVRIE_Pos                 (4U)

+#define ADC_IER_OVRIE_Msk                 (0x1UL << ADC_IER_OVRIE_Pos)         /*!< 0x00000010 */

+#define ADC_IER_OVRIE                     ADC_IER_OVRIE_Msk                    /*!< ADC overrun interrupt source */

+#define ADC_IER_JEOCIE_Pos                (5U)

+#define ADC_IER_JEOCIE_Msk                (0x1UL << ADC_IER_JEOCIE_Pos)        /*!< 0x00000020 */

+#define ADC_IER_JEOCIE                    ADC_IER_JEOCIE_Msk                   /*!< ADC End of Injected Conversion interrupt source */

+#define ADC_IER_JEOSIE_Pos                (6U)

+#define ADC_IER_JEOSIE_Msk                (0x1UL << ADC_IER_JEOSIE_Pos)        /*!< 0x00000040 */

+#define ADC_IER_JEOSIE                    ADC_IER_JEOSIE_Msk                   /*!< ADC End of Injected sequence of Conversions interrupt source */

+#define ADC_IER_AWD1IE_Pos                (7U)

+#define ADC_IER_AWD1IE_Msk                (0x1UL << ADC_IER_AWD1IE_Pos)        /*!< 0x00000080 */

+#define ADC_IER_AWD1IE                    ADC_IER_AWD1IE_Msk                   /*!< ADC Analog watchdog 1 interrupt source */

+#define ADC_IER_AWD2IE_Pos                (8U)

+#define ADC_IER_AWD2IE_Msk                (0x1UL << ADC_IER_AWD2IE_Pos)        /*!< 0x00000100 */

+#define ADC_IER_AWD2IE                    ADC_IER_AWD2IE_Msk                   /*!< ADC Analog watchdog 2 interrupt source */

+#define ADC_IER_AWD3IE_Pos                (9U)

+#define ADC_IER_AWD3IE_Msk                (0x1UL << ADC_IER_AWD3IE_Pos)        /*!< 0x00000200 */

+#define ADC_IER_AWD3IE                    ADC_IER_AWD3IE_Msk                   /*!< ADC Analog watchdog 3 interrupt source */

+#define ADC_IER_JQOVFIE_Pos               (10U)

+#define ADC_IER_JQOVFIE_Msk               (0x1UL << ADC_IER_JQOVFIE_Pos)       /*!< 0x00000400 */

+#define ADC_IER_JQOVFIE                   ADC_IER_JQOVFIE_Msk                  /*!< ADC Injected Context Queue Overflow interrupt source */

+

+/********************  Bit definition for ADC_CR register  ********************/

+#define ADC_CR_ADEN_Pos                   (0U)

+#define ADC_CR_ADEN_Msk                   (0x1UL << ADC_CR_ADEN_Pos)           /*!< 0x00000001 */

+#define ADC_CR_ADEN                       ADC_CR_ADEN_Msk                      /*!< ADC Enable control */

+#define ADC_CR_ADDIS_Pos                  (1U)

+#define ADC_CR_ADDIS_Msk                  (0x1UL << ADC_CR_ADDIS_Pos)          /*!< 0x00000002 */

+#define ADC_CR_ADDIS                      ADC_CR_ADDIS_Msk                     /*!< ADC Disable command */

+#define ADC_CR_ADSTART_Pos                (2U)

+#define ADC_CR_ADSTART_Msk                (0x1UL << ADC_CR_ADSTART_Pos)        /*!< 0x00000004 */

+#define ADC_CR_ADSTART                    ADC_CR_ADSTART_Msk                   /*!< ADC Start of Regular conversion */

+#define ADC_CR_JADSTART_Pos               (3U)

+#define ADC_CR_JADSTART_Msk               (0x1UL << ADC_CR_JADSTART_Pos)       /*!< 0x00000008 */

+#define ADC_CR_JADSTART                   ADC_CR_JADSTART_Msk                  /*!< ADC Start of injected conversion */

+#define ADC_CR_ADSTP_Pos                  (4U)

+#define ADC_CR_ADSTP_Msk                  (0x1UL << ADC_CR_ADSTP_Pos)          /*!< 0x00000010 */

+#define ADC_CR_ADSTP                      ADC_CR_ADSTP_Msk                     /*!< ADC Stop of Regular conversion */

+#define ADC_CR_JADSTP_Pos                 (5U)

+#define ADC_CR_JADSTP_Msk                 (0x1UL << ADC_CR_JADSTP_Pos)         /*!< 0x00000020 */

+#define ADC_CR_JADSTP                     ADC_CR_JADSTP_Msk                    /*!< ADC Stop of injected conversion */

+#define ADC_CR_BOOST_Pos                  (8U)

+#define ADC_CR_BOOST_Msk                  (0x3UL << ADC_CR_BOOST_Pos)          /*!< 0x00000300 */

+#define ADC_CR_BOOST                      ADC_CR_BOOST_Msk                     /*!< ADC Boost Mode configuration */

+#define ADC_CR_BOOST_0                    (0x1UL << ADC_CR_BOOST_Pos)           /*!< 0x00000100 */

+#define ADC_CR_BOOST_1                    (0x2UL << ADC_CR_BOOST_Pos)           /*!< 0x00000200 */

+#define ADC_CR_ADCALLIN_Pos               (16U)

+#define ADC_CR_ADCALLIN_Msk               (0x1UL << ADC_CR_ADCALLIN_Pos)       /*!< 0x00010000 */

+#define ADC_CR_ADCALLIN                   ADC_CR_ADCALLIN_Msk                  /*!< ADC Linearity calibration */

+#define ADC_CR_LINCALRDYW1_Pos            (22U)

+#define ADC_CR_LINCALRDYW1_Msk            (0x1UL << ADC_CR_LINCALRDYW1_Pos)    /*!< 0x00400000 */

+#define ADC_CR_LINCALRDYW1                ADC_CR_LINCALRDYW1_Msk               /*!< ADC Linearity calibration ready Word 1 */

+#define ADC_CR_LINCALRDYW2_Pos            (23U)

+#define ADC_CR_LINCALRDYW2_Msk            (0x1UL << ADC_CR_LINCALRDYW2_Pos)    /*!< 0x00800000 */

+#define ADC_CR_LINCALRDYW2                ADC_CR_LINCALRDYW2_Msk               /*!< ADC Linearity calibration ready Word 2 */

+#define ADC_CR_LINCALRDYW3_Pos            (24U)

+#define ADC_CR_LINCALRDYW3_Msk            (0x1UL << ADC_CR_LINCALRDYW3_Pos)    /*!< 0x01000000 */

+#define ADC_CR_LINCALRDYW3                ADC_CR_LINCALRDYW3_Msk               /*!< ADC Linearity calibration ready Word 3 */

+#define ADC_CR_LINCALRDYW4_Pos            (25U)

+#define ADC_CR_LINCALRDYW4_Msk            (0x1UL << ADC_CR_LINCALRDYW4_Pos)    /*!< 0x02000000 */

+#define ADC_CR_LINCALRDYW4                ADC_CR_LINCALRDYW4_Msk               /*!< ADC Linearity calibration ready Word 4 */

+#define ADC_CR_LINCALRDYW5_Pos            (26U)

+#define ADC_CR_LINCALRDYW5_Msk            (0x1UL << ADC_CR_LINCALRDYW5_Pos)    /*!< 0x04000000 */

+#define ADC_CR_LINCALRDYW5                ADC_CR_LINCALRDYW5_Msk               /*!< ADC Linearity calibration ready Word 5 */

+#define ADC_CR_LINCALRDYW6_Pos            (27U)

+#define ADC_CR_LINCALRDYW6_Msk            (0x1UL << ADC_CR_LINCALRDYW6_Pos)    /*!< 0x08000000 */

+#define ADC_CR_LINCALRDYW6                ADC_CR_LINCALRDYW6_Msk               /*!< ADC Linearity calibration ready Word 6 */

+#define ADC_CR_ADVREGEN_Pos               (28U)

+#define ADC_CR_ADVREGEN_Msk               (0x1UL << ADC_CR_ADVREGEN_Pos)       /*!< 0x10000000 */

+#define ADC_CR_ADVREGEN                   ADC_CR_ADVREGEN_Msk                  /*!< ADC Voltage regulator Enable */

+#define ADC_CR_DEEPPWD_Pos                (29U)

+#define ADC_CR_DEEPPWD_Msk                (0x1UL << ADC_CR_DEEPPWD_Pos)        /*!< 0x20000000 */

+#define ADC_CR_DEEPPWD                    ADC_CR_DEEPPWD_Msk                   /*!< ADC Deep power down Enable */

+#define ADC_CR_ADCALDIF_Pos               (30U)

+#define ADC_CR_ADCALDIF_Msk               (0x1UL << ADC_CR_ADCALDIF_Pos)       /*!< 0x40000000 */

+#define ADC_CR_ADCALDIF                   ADC_CR_ADCALDIF_Msk                  /*!< ADC Differential Mode for calibration */

+#define ADC_CR_ADCAL_Pos                  (31U)

+#define ADC_CR_ADCAL_Msk                  (0x1UL << ADC_CR_ADCAL_Pos)          /*!< 0x80000000 */

+#define ADC_CR_ADCAL                      ADC_CR_ADCAL_Msk                     /*!< ADC Calibration */

+

+/********************  Bit definition for ADC_CFGR register  ********************/

+#define ADC_CFGR_DMNGT_Pos                (0U)

+#define ADC_CFGR_DMNGT_Msk                (0x3UL << ADC_CFGR_DMNGT_Pos)        /*!< 0x00000003 */

+#define ADC_CFGR_DMNGT                    ADC_CFGR_DMNGT_Msk                   /*!< ADC Data Management configuration */

+#define ADC_CFGR_DMNGT_0                  (0x1UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000001 */

+#define ADC_CFGR_DMNGT_1                  (0x2UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000002 */

+

+#define ADC_CFGR_RES_Pos                  (2U)

+#define ADC_CFGR_RES_Msk                  (0x7UL << ADC_CFGR_RES_Pos)          /*!< 0x0000001C */

+#define ADC_CFGR_RES                      ADC_CFGR_RES_Msk                     /*!< ADC Data resolution */

+#define ADC_CFGR_RES_0                    (0x1UL << ADC_CFGR_RES_Pos)           /*!< 0x00000004 */

+#define ADC_CFGR_RES_1                    (0x2UL << ADC_CFGR_RES_Pos)           /*!< 0x00000008 */

+#define ADC_CFGR_RES_2                    (0x4UL << ADC_CFGR_RES_Pos)           /*!< 0x00000010 */

+

+#define ADC_CFGR_EXTSEL_Pos               (5U)

+#define ADC_CFGR_EXTSEL_Msk               (0x1FUL << ADC_CFGR_EXTSEL_Pos)      /*!< 0x000003E0 */

+#define ADC_CFGR_EXTSEL                   ADC_CFGR_EXTSEL_Msk                  /*!< ADC External trigger selection for regular group */

+#define ADC_CFGR_EXTSEL_0                 (0x01UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000020 */

+#define ADC_CFGR_EXTSEL_1                 (0x02UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000040 */

+#define ADC_CFGR_EXTSEL_2                 (0x04UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000080 */

+#define ADC_CFGR_EXTSEL_3                 (0x08UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000100 */

+#define ADC_CFGR_EXTSEL_4                 (0x10UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000200 */

+

+#define ADC_CFGR_EXTEN_Pos                (10U)

+#define ADC_CFGR_EXTEN_Msk                (0x3UL << ADC_CFGR_EXTEN_Pos)        /*!< 0x00000C00 */

+#define ADC_CFGR_EXTEN                    ADC_CFGR_EXTEN_Msk                   /*!< ADC External trigger enable and polarity selection for regular channels */

+#define ADC_CFGR_EXTEN_0                  (0x1UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000400 */

+#define ADC_CFGR_EXTEN_1                  (0x2UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000800 */

+

+#define ADC_CFGR_OVRMOD_Pos               (12U)

+#define ADC_CFGR_OVRMOD_Msk               (0x1UL << ADC_CFGR_OVRMOD_Pos)       /*!< 0x00001000 */

+#define ADC_CFGR_OVRMOD                   ADC_CFGR_OVRMOD_Msk                  /*!< ADC overrun mode */

+#define ADC_CFGR_CONT_Pos                 (13U)

+#define ADC_CFGR_CONT_Msk                 (0x1UL << ADC_CFGR_CONT_Pos)         /*!< 0x00002000 */

+#define ADC_CFGR_CONT                     ADC_CFGR_CONT_Msk                    /*!< ADC Single/continuous conversion mode for regular conversion */

+#define ADC_CFGR_AUTDLY_Pos               (14U)

+#define ADC_CFGR_AUTDLY_Msk               (0x1UL << ADC_CFGR_AUTDLY_Pos)       /*!< 0x00004000 */

+#define ADC_CFGR_AUTDLY                   ADC_CFGR_AUTDLY_Msk                  /*!< ADC Delayed conversion mode */

+

+#define ADC_CFGR_DISCEN_Pos               (16U)

+#define ADC_CFGR_DISCEN_Msk               (0x1UL << ADC_CFGR_DISCEN_Pos)       /*!< 0x00010000 */

+#define ADC_CFGR_DISCEN                   ADC_CFGR_DISCEN_Msk                  /*!< ADC Discontinuous mode for regular channels */

+

+#define ADC_CFGR_DISCNUM_Pos              (17U)

+#define ADC_CFGR_DISCNUM_Msk              (0x7UL << ADC_CFGR_DISCNUM_Pos)      /*!< 0x000E0000 */

+#define ADC_CFGR_DISCNUM                  ADC_CFGR_DISCNUM_Msk                 /*!< ADC Discontinuous mode channel count */

+#define ADC_CFGR_DISCNUM_0                (0x1UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00020000 */

+#define ADC_CFGR_DISCNUM_1                (0x2UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00040000 */

+#define ADC_CFGR_DISCNUM_2                (0x4UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00080000 */

+

+#define ADC_CFGR_JDISCEN_Pos              (20U)

+#define ADC_CFGR_JDISCEN_Msk              (0x1UL << ADC_CFGR_JDISCEN_Pos)      /*!< 0x00100000 */

+#define ADC_CFGR_JDISCEN                  ADC_CFGR_JDISCEN_Msk                 /*!< ADC Discontinuous mode on injected channels */

+#define ADC_CFGR_JQM_Pos                  (21U)

+#define ADC_CFGR_JQM_Msk                  (0x1UL << ADC_CFGR_JQM_Pos)          /*!< 0x00200000 */

+#define ADC_CFGR_JQM                      ADC_CFGR_JQM_Msk                     /*!< ADC JSQR Queue mode */

+#define ADC_CFGR_AWD1SGL_Pos              (22U)

+#define ADC_CFGR_AWD1SGL_Msk              (0x1UL << ADC_CFGR_AWD1SGL_Pos)      /*!< 0x00400000 */

+#define ADC_CFGR_AWD1SGL                  ADC_CFGR_AWD1SGL_Msk                 /*!< Enable the watchdog 1 on a single channel or on all channels */

+#define ADC_CFGR_AWD1EN_Pos               (23U)

+#define ADC_CFGR_AWD1EN_Msk               (0x1UL << ADC_CFGR_AWD1EN_Pos)       /*!< 0x00800000 */

+#define ADC_CFGR_AWD1EN                   ADC_CFGR_AWD1EN_Msk                  /*!< ADC Analog watchdog 1 enable on regular Channels */

+#define ADC_CFGR_JAWD1EN_Pos              (24U)

+#define ADC_CFGR_JAWD1EN_Msk              (0x1UL << ADC_CFGR_JAWD1EN_Pos)      /*!< 0x01000000 */

+#define ADC_CFGR_JAWD1EN                  ADC_CFGR_JAWD1EN_Msk                 /*!< ADC Analog watchdog 1 enable on injected Channels */

+#define ADC_CFGR_JAUTO_Pos                (25U)

+#define ADC_CFGR_JAUTO_Msk                (0x1UL << ADC_CFGR_JAUTO_Pos)        /*!< 0x02000000 */

+#define ADC_CFGR_JAUTO                    ADC_CFGR_JAUTO_Msk                   /*!< ADC Automatic injected group conversion */

+

+#define ADC_CFGR_AWD1CH_Pos               (26U)

+#define ADC_CFGR_AWD1CH_Msk               (0x1FUL << ADC_CFGR_AWD1CH_Pos)      /*!< 0x7C000000 */

+#define ADC_CFGR_AWD1CH                   ADC_CFGR_AWD1CH_Msk                  /*!< ADC Analog watchdog 1 Channel selection */

+#define ADC_CFGR_AWD1CH_0                 (0x01UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x04000000 */

+#define ADC_CFGR_AWD1CH_1                 (0x02UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x08000000 */

+#define ADC_CFGR_AWD1CH_2                 (0x04UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x10000000 */

+#define ADC_CFGR_AWD1CH_3                 (0x08UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x20000000 */

+#define ADC_CFGR_AWD1CH_4                 (0x10UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x40000000 */

+

+#define ADC_CFGR_JQDIS_Pos                (31U)

+#define ADC_CFGR_JQDIS_Msk                (0x1UL << ADC_CFGR_JQDIS_Pos)        /*!< 0x80000000 */

+#define ADC_CFGR_JQDIS                    ADC_CFGR_JQDIS_Msk                   /*!< ADC Injected queue disable */

+

+/********************  Bit definition for ADC_CFGR2 register  ********************/

+#define ADC_CFGR2_ROVSE_Pos               (0U)

+#define ADC_CFGR2_ROVSE_Msk               (0x1UL << ADC_CFGR2_ROVSE_Pos)       /*!< 0x00000001 */

+#define ADC_CFGR2_ROVSE                   ADC_CFGR2_ROVSE_Msk                  /*!< ADC Regular group oversampler enable */

+#define ADC_CFGR2_JOVSE_Pos               (1U)

+#define ADC_CFGR2_JOVSE_Msk               (0x1UL << ADC_CFGR2_JOVSE_Pos)       /*!< 0x00000002 */

+#define ADC_CFGR2_JOVSE                   ADC_CFGR2_JOVSE_Msk                  /*!< ADC Injected group oversampler enable */

+

+#define ADC_CFGR2_OVSS_Pos                (5U)

+#define ADC_CFGR2_OVSS_Msk                (0xFUL << ADC_CFGR2_OVSS_Pos)        /*!< 0x000001E0 */

+#define ADC_CFGR2_OVSS                    ADC_CFGR2_OVSS_Msk                   /*!< ADC Regular Oversampling shift */

+#define ADC_CFGR2_OVSS_0                  (0x1UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000020 */

+#define ADC_CFGR2_OVSS_1                  (0x2UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000040 */

+#define ADC_CFGR2_OVSS_2                  (0x4UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000080 */

+#define ADC_CFGR2_OVSS_3                  (0x8UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000100 */

+

+#define ADC_CFGR2_TROVS_Pos               (9U)

+#define ADC_CFGR2_TROVS_Msk               (0x1UL << ADC_CFGR2_TROVS_Pos)       /*!< 0x00000200 */

+#define ADC_CFGR2_TROVS                   ADC_CFGR2_TROVS_Msk                  /*!< ADC Triggered regular Oversampling */

+#define ADC_CFGR2_ROVSM_Pos               (10U)

+#define ADC_CFGR2_ROVSM_Msk               (0x1UL << ADC_CFGR2_ROVSM_Pos)       /*!< 0x00000400 */

+#define ADC_CFGR2_ROVSM                   ADC_CFGR2_ROVSM_Msk                  /*!< ADC Regular oversampling mode */

+

+#define ADC_CFGR2_RSHIFT1_Pos             (11U)

+#define ADC_CFGR2_RSHIFT1_Msk             (0x1UL << ADC_CFGR2_RSHIFT1_Pos)     /*!< 0x00000800 */

+#define ADC_CFGR2_RSHIFT1                 ADC_CFGR2_RSHIFT1_Msk                /*!< ADC Right-shift data after Offset 1 correction */

+#define ADC_CFGR2_RSHIFT2_Pos             (12U)

+#define ADC_CFGR2_RSHIFT2_Msk             (0x1UL << ADC_CFGR2_RSHIFT2_Pos)     /*!< 0x00001000 */

+#define ADC_CFGR2_RSHIFT2                 ADC_CFGR2_RSHIFT2_Msk                /*!< ADC Right-shift data after Offset 2 correction */

+#define ADC_CFGR2_RSHIFT3_Pos             (13U)

+#define ADC_CFGR2_RSHIFT3_Msk             (0x1UL << ADC_CFGR2_RSHIFT3_Pos)     /*!< 0x00002000 */

+#define ADC_CFGR2_RSHIFT3                 ADC_CFGR2_RSHIFT3_Msk                /*!< ADC Right-shift data after Offset 3 correction */

+#define ADC_CFGR2_RSHIFT4_Pos             (14U)

+#define ADC_CFGR2_RSHIFT4_Msk             (0x1UL << ADC_CFGR2_RSHIFT4_Pos)     /*!< 0x00004000 */

+#define ADC_CFGR2_RSHIFT4                 ADC_CFGR2_RSHIFT4_Msk                /*!< ADC Right-shift data after Offset 4 correction */

+

+#define ADC_CFGR2_OVSR_Pos                (16U)

+#define ADC_CFGR2_OVSR_Msk                (0x3FFUL << ADC_CFGR2_OVSR_Pos)      /*!< 0x03FF0000 */

+#define ADC_CFGR2_OVSR                    ADC_CFGR2_OVSR_Msk                   /*!< ADC oversampling Ratio */

+#define ADC_CFGR2_OVSR_0                  (0x001UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00010000 */

+#define ADC_CFGR2_OVSR_1                  (0x002UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00020000 */

+#define ADC_CFGR2_OVSR_2                  (0x004UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00040000 */

+#define ADC_CFGR2_OVSR_3                  (0x008UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00080000 */

+#define ADC_CFGR2_OVSR_4                  (0x010UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00100000 */

+#define ADC_CFGR2_OVSR_5                  (0x020UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00200000 */

+#define ADC_CFGR2_OVSR_6                  (0x040UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00400000 */

+#define ADC_CFGR2_OVSR_7                  (0x080UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00800000 */

+#define ADC_CFGR2_OVSR_8                  (0x100UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x01000000 */

+#define ADC_CFGR2_OVSR_9                  (0x200UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x02000000 */

+

+#define ADC_CFGR2_LSHIFT_Pos              (28U)

+#define ADC_CFGR2_LSHIFT_Msk              (0xFUL << ADC_CFGR2_LSHIFT_Pos)      /*!< 0xF0000000 */

+#define ADC_CFGR2_LSHIFT                  ADC_CFGR2_LSHIFT_Msk                 /*!< ADC Left shift factor */

+#define ADC_CFGR2_LSHIFT_0                (0x1UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x10000000 */

+#define ADC_CFGR2_LSHIFT_1                (0x2UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x20000000 */

+#define ADC_CFGR2_LSHIFT_2                (0x4UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x40000000 */

+#define ADC_CFGR2_LSHIFT_3                (0x8UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_SMPR1 register  ********************/

+#define ADC_SMPR1_SMP0_Pos                (0U)

+#define ADC_SMPR1_SMP0_Msk                (0x7UL << ADC_SMPR1_SMP0_Pos)        /*!< 0x00000007 */

+#define ADC_SMPR1_SMP0                    ADC_SMPR1_SMP0_Msk                   /*!< ADC Channel 0 Sampling time selection  */

+#define ADC_SMPR1_SMP0_0                  (0x1UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000001 */

+#define ADC_SMPR1_SMP0_1                  (0x2UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000002 */

+#define ADC_SMPR1_SMP0_2                  (0x4UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000004 */

+

+#define ADC_SMPR1_SMP1_Pos                (3U)

+#define ADC_SMPR1_SMP1_Msk                (0x7UL << ADC_SMPR1_SMP1_Pos)        /*!< 0x00000038 */

+#define ADC_SMPR1_SMP1                    ADC_SMPR1_SMP1_Msk                   /*!< ADC Channel 1 Sampling time selection  */

+#define ADC_SMPR1_SMP1_0                  (0x1UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000008 */

+#define ADC_SMPR1_SMP1_1                  (0x2UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000010 */

+#define ADC_SMPR1_SMP1_2                  (0x4UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000020 */

+

+#define ADC_SMPR1_SMP2_Pos                (6U)

+#define ADC_SMPR1_SMP2_Msk                (0x7UL << ADC_SMPR1_SMP2_Pos)        /*!< 0x000001C0 */

+#define ADC_SMPR1_SMP2                    ADC_SMPR1_SMP2_Msk                   /*!< ADC Channel 2 Sampling time selection  */

+#define ADC_SMPR1_SMP2_0                  (0x1UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000040 */

+#define ADC_SMPR1_SMP2_1                  (0x2UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000080 */

+#define ADC_SMPR1_SMP2_2                  (0x4UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000100 */

+

+#define ADC_SMPR1_SMP3_Pos                (9U)

+#define ADC_SMPR1_SMP3_Msk                (0x7UL << ADC_SMPR1_SMP3_Pos)        /*!< 0x00000E00 */

+#define ADC_SMPR1_SMP3                    ADC_SMPR1_SMP3_Msk                   /*!< ADC Channel 3 Sampling time selection  */

+#define ADC_SMPR1_SMP3_0                  (0x1UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000200 */

+#define ADC_SMPR1_SMP3_1                  (0x2UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000400 */

+#define ADC_SMPR1_SMP3_2                  (0x4UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000800 */

+

+#define ADC_SMPR1_SMP4_Pos                (12U)

+#define ADC_SMPR1_SMP4_Msk                (0x7UL << ADC_SMPR1_SMP4_Pos)        /*!< 0x00007000 */

+#define ADC_SMPR1_SMP4                    ADC_SMPR1_SMP4_Msk                   /*!< ADC Channel 4 Sampling time selection  */

+#define ADC_SMPR1_SMP4_0                  (0x1UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00001000 */

+#define ADC_SMPR1_SMP4_1                  (0x2UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00002000 */

+#define ADC_SMPR1_SMP4_2                  (0x4UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00004000 */

+

+#define ADC_SMPR1_SMP5_Pos                (15U)

+#define ADC_SMPR1_SMP5_Msk                (0x7UL << ADC_SMPR1_SMP5_Pos)        /*!< 0x00038000 */

+#define ADC_SMPR1_SMP5                    ADC_SMPR1_SMP5_Msk                   /*!< ADC Channel 5 Sampling time selection  */

+#define ADC_SMPR1_SMP5_0                  (0x1UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00008000 */

+#define ADC_SMPR1_SMP5_1                  (0x2UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00010000 */

+#define ADC_SMPR1_SMP5_2                  (0x4UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00020000 */

+

+#define ADC_SMPR1_SMP6_Pos                (18U)

+#define ADC_SMPR1_SMP6_Msk                (0x7UL << ADC_SMPR1_SMP6_Pos)        /*!< 0x001C0000 */

+#define ADC_SMPR1_SMP6                    ADC_SMPR1_SMP6_Msk                   /*!< ADC Channel 6 Sampling time selection  */

+#define ADC_SMPR1_SMP6_0                  (0x1UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00040000 */

+#define ADC_SMPR1_SMP6_1                  (0x2UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00080000 */

+#define ADC_SMPR1_SMP6_2                  (0x4UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00100000 */

+

+#define ADC_SMPR1_SMP7_Pos                (21U)

+#define ADC_SMPR1_SMP7_Msk                (0x7UL << ADC_SMPR1_SMP7_Pos)        /*!< 0x00E00000 */

+#define ADC_SMPR1_SMP7                    ADC_SMPR1_SMP7_Msk                   /*!< ADC Channel 7 Sampling time selection  */

+#define ADC_SMPR1_SMP7_0                  (0x1UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00200000 */

+#define ADC_SMPR1_SMP7_1                  (0x2UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00400000 */

+#define ADC_SMPR1_SMP7_2                  (0x4UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00800000 */

+

+#define ADC_SMPR1_SMP8_Pos                (24U)

+#define ADC_SMPR1_SMP8_Msk                (0x7UL << ADC_SMPR1_SMP8_Pos)        /*!< 0x07000000 */

+#define ADC_SMPR1_SMP8                    ADC_SMPR1_SMP8_Msk                   /*!< ADC Channel 8 Sampling time selection  */

+#define ADC_SMPR1_SMP8_0                  (0x1UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x01000000 */

+#define ADC_SMPR1_SMP8_1                  (0x2UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x02000000 */

+#define ADC_SMPR1_SMP8_2                  (0x4UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x04000000 */

+

+#define ADC_SMPR1_SMP9_Pos                (27U)

+#define ADC_SMPR1_SMP9_Msk                (0x7UL << ADC_SMPR1_SMP9_Pos)        /*!< 0x38000000 */

+#define ADC_SMPR1_SMP9                    ADC_SMPR1_SMP9_Msk                   /*!< ADC Channel 9 Sampling time selection  */

+#define ADC_SMPR1_SMP9_0                  (0x1UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x08000000 */

+#define ADC_SMPR1_SMP9_1                  (0x2UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x10000000 */

+#define ADC_SMPR1_SMP9_2                  (0x4UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x20000000 */

+

+/********************  Bit definition for ADC_SMPR2 register  ********************/

+#define ADC_SMPR2_SMP10_Pos               (0U)

+#define ADC_SMPR2_SMP10_Msk               (0x7UL << ADC_SMPR2_SMP10_Pos)       /*!< 0x00000007 */

+#define ADC_SMPR2_SMP10                   ADC_SMPR2_SMP10_Msk                  /*!< ADC Channel 10 Sampling time selection  */

+#define ADC_SMPR2_SMP10_0                 (0x1UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000001 */

+#define ADC_SMPR2_SMP10_1                 (0x2UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000002 */

+#define ADC_SMPR2_SMP10_2                 (0x4UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000004 */

+

+#define ADC_SMPR2_SMP11_Pos               (3U)

+#define ADC_SMPR2_SMP11_Msk               (0x7UL << ADC_SMPR2_SMP11_Pos)       /*!< 0x00000038 */

+#define ADC_SMPR2_SMP11                   ADC_SMPR2_SMP11_Msk                  /*!< ADC Channel 11 Sampling time selection  */

+#define ADC_SMPR2_SMP11_0                 (0x1UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000008 */

+#define ADC_SMPR2_SMP11_1                 (0x2UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000010 */

+#define ADC_SMPR2_SMP11_2                 (0x4UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000020 */

+

+#define ADC_SMPR2_SMP12_Pos               (6U)

+#define ADC_SMPR2_SMP12_Msk               (0x7UL << ADC_SMPR2_SMP12_Pos)       /*!< 0x000001C0 */

+#define ADC_SMPR2_SMP12                   ADC_SMPR2_SMP12_Msk                  /*!< ADC Channel 12 Sampling time selection  */

+#define ADC_SMPR2_SMP12_0                 (0x1UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000040 */

+#define ADC_SMPR2_SMP12_1                 (0x2UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000080 */

+#define ADC_SMPR2_SMP12_2                 (0x4UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000100 */

+

+#define ADC_SMPR2_SMP13_Pos               (9U)

+#define ADC_SMPR2_SMP13_Msk               (0x7UL << ADC_SMPR2_SMP13_Pos)       /*!< 0x00000E00 */

+#define ADC_SMPR2_SMP13                   ADC_SMPR2_SMP13_Msk                  /*!< ADC Channel 13 Sampling time selection  */

+#define ADC_SMPR2_SMP13_0                 (0x1UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000200 */

+#define ADC_SMPR2_SMP13_1                 (0x2UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000400 */

+#define ADC_SMPR2_SMP13_2                 (0x4UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000800 */

+

+#define ADC_SMPR2_SMP14_Pos               (12U)

+#define ADC_SMPR2_SMP14_Msk               (0x7UL << ADC_SMPR2_SMP14_Pos)       /*!< 0x00007000 */

+#define ADC_SMPR2_SMP14                   ADC_SMPR2_SMP14_Msk                  /*!< ADC Channel 14 Sampling time selection  */

+#define ADC_SMPR2_SMP14_0                 (0x1UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00001000 */

+#define ADC_SMPR2_SMP14_1                 (0x2UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00002000 */

+#define ADC_SMPR2_SMP14_2                 (0x4UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00004000 */

+

+#define ADC_SMPR2_SMP15_Pos               (15U)

+#define ADC_SMPR2_SMP15_Msk               (0x7UL << ADC_SMPR2_SMP15_Pos)       /*!< 0x00038000 */

+#define ADC_SMPR2_SMP15                   ADC_SMPR2_SMP15_Msk                  /*!< ADC Channel 15 Sampling time selection  */

+#define ADC_SMPR2_SMP15_0                 (0x1UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00008000 */

+#define ADC_SMPR2_SMP15_1                 (0x2UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00010000 */

+#define ADC_SMPR2_SMP15_2                 (0x4UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00020000 */

+

+#define ADC_SMPR2_SMP16_Pos               (18U)

+#define ADC_SMPR2_SMP16_Msk               (0x7UL << ADC_SMPR2_SMP16_Pos)       /*!< 0x001C0000 */

+#define ADC_SMPR2_SMP16                   ADC_SMPR2_SMP16_Msk                  /*!< ADC Channel 16 Sampling time selection  */

+#define ADC_SMPR2_SMP16_0                 (0x1UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00040000 */

+#define ADC_SMPR2_SMP16_1                 (0x2UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00080000 */

+#define ADC_SMPR2_SMP16_2                 (0x4UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00100000 */

+

+#define ADC_SMPR2_SMP17_Pos               (21U)

+#define ADC_SMPR2_SMP17_Msk               (0x7UL << ADC_SMPR2_SMP17_Pos)       /*!< 0x00E00000 */

+#define ADC_SMPR2_SMP17                   ADC_SMPR2_SMP17_Msk                  /*!< ADC Channel 17 Sampling time selection  */

+#define ADC_SMPR2_SMP17_0                 (0x1UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00200000 */

+#define ADC_SMPR2_SMP17_1                 (0x2UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00400000 */

+#define ADC_SMPR2_SMP17_2                 (0x4UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00800000 */

+

+#define ADC_SMPR2_SMP18_Pos               (24U)

+#define ADC_SMPR2_SMP18_Msk               (0x7UL << ADC_SMPR2_SMP18_Pos)       /*!< 0x07000000 */

+#define ADC_SMPR2_SMP18                   ADC_SMPR2_SMP18_Msk                  /*!< ADC Channel 18 Sampling time selection  */

+#define ADC_SMPR2_SMP18_0                 (0x1UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x01000000 */

+#define ADC_SMPR2_SMP18_1                 (0x2UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x02000000 */

+#define ADC_SMPR2_SMP18_2                 (0x4UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x04000000 */

+

+#define ADC_SMPR2_SMP19_Pos               (27U)

+#define ADC_SMPR2_SMP19_Msk               (0x7UL << ADC_SMPR2_SMP19_Pos)       /*!< 0x38000000 */

+#define ADC_SMPR2_SMP19                   ADC_SMPR2_SMP19_Msk                  /*!< ADC Channel 19 Sampling time selection  */

+#define ADC_SMPR2_SMP19_0                 (0x1UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x08000000 */

+#define ADC_SMPR2_SMP19_1                 (0x2UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x10000000 */

+#define ADC_SMPR2_SMP19_2                 (0x4UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x20000000 */

+

+/********************  Bit definition for ADC_PCSEL register  ********************/

+#define ADC_PCSEL_PCSEL_Pos               (0U)

+#define ADC_PCSEL_PCSEL_Msk               (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)   /*!< 0x000FFFFF */

+#define ADC_PCSEL_PCSEL                   ADC_PCSEL_PCSEL_Msk                  /*!< ADC pre channel selection */

+#define ADC_PCSEL_PCSEL_0                 (0x00001UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */

+#define ADC_PCSEL_PCSEL_1                 (0x00002UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */

+#define ADC_PCSEL_PCSEL_2                 (0x00004UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */

+#define ADC_PCSEL_PCSEL_3                 (0x00008UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */

+#define ADC_PCSEL_PCSEL_4                 (0x00010UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */

+#define ADC_PCSEL_PCSEL_5                 (0x00020UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */

+#define ADC_PCSEL_PCSEL_6                 (0x00040UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */

+#define ADC_PCSEL_PCSEL_7                 (0x00080UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */

+#define ADC_PCSEL_PCSEL_8                 (0x00100UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */

+#define ADC_PCSEL_PCSEL_9                 (0x00200UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */

+#define ADC_PCSEL_PCSEL_10                (0x00400UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */

+#define ADC_PCSEL_PCSEL_11                (0x00800UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */

+#define ADC_PCSEL_PCSEL_12                (0x01000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */

+#define ADC_PCSEL_PCSEL_13                (0x02000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */

+#define ADC_PCSEL_PCSEL_14                (0x04000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */

+#define ADC_PCSEL_PCSEL_15                (0x08000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */

+#define ADC_PCSEL_PCSEL_16                (0x10000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */

+#define ADC_PCSEL_PCSEL_17                (0x20000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */

+#define ADC_PCSEL_PCSEL_18                (0x40000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */

+#define ADC_PCSEL_PCSEL_19                (0x80000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00080000 */

+

+/*****************  Bit definition for ADC_LTR1, 2, 3 registers *****************/

+#define ADC_LTR_LT_Pos                    (0U)

+#define ADC_LTR_LT_Msk                    (0x3FFFFFFUL << ADC_LTR_LT_Pos)      /*!< 0x03FFFFFF */

+#define ADC_LTR_LT                        ADC_LTR_LT_Msk                       /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */

+

+/*****************  Bit definition for ADC_HTR1, 2, 3 registers  ****************/

+#define ADC_HTR_HT_Pos                    (0U)

+#define ADC_HTR_HT_Msk                    (0x3FFFFFFUL << ADC_HTR_HT_Pos)      /*!< 0x03FFFFFF */

+#define ADC_HTR_HT                        ADC_HTR_HT_Msk                       /*!< ADC Analog watchdog 1,2 and 3 higher threshold */

+

+

+/********************  Bit definition for ADC_SQR1 register  ********************/

+#define ADC_SQR1_L_Pos                    (0U)

+#define ADC_SQR1_L_Msk                    (0xFUL << ADC_SQR1_L_Pos)            /*!< 0x0000000F */

+#define ADC_SQR1_L                        ADC_SQR1_L_Msk                       /*!< ADC regular channel sequence lenght */

+#define ADC_SQR1_L_0                      (0x1UL << ADC_SQR1_L_Pos)             /*!< 0x00000001 */

+#define ADC_SQR1_L_1                      (0x2UL << ADC_SQR1_L_Pos)             /*!< 0x00000002 */

+#define ADC_SQR1_L_2                      (0x4UL << ADC_SQR1_L_Pos)             /*!< 0x00000004 */

+#define ADC_SQR1_L_3                      (0x8UL << ADC_SQR1_L_Pos)             /*!< 0x00000008 */

+

+#define ADC_SQR1_SQ1_Pos                  (6U)

+#define ADC_SQR1_SQ1_Msk                  (0x1FUL << ADC_SQR1_SQ1_Pos)         /*!< 0x000007C0 */

+#define ADC_SQR1_SQ1                      ADC_SQR1_SQ1_Msk                     /*!< ADC 1st conversion in regular sequence */

+#define ADC_SQR1_SQ1_0                    (0x01UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000040 */

+#define ADC_SQR1_SQ1_1                    (0x02UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000080 */

+#define ADC_SQR1_SQ1_2                    (0x04UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000100 */

+#define ADC_SQR1_SQ1_3                    (0x08UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000200 */

+#define ADC_SQR1_SQ1_4                    (0x10UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000400 */

+

+#define ADC_SQR1_SQ2_Pos                  (12U)

+#define ADC_SQR1_SQ2_Msk                  (0x1FUL << ADC_SQR1_SQ2_Pos)         /*!< 0x0001F000 */

+#define ADC_SQR1_SQ2                      ADC_SQR1_SQ2_Msk                     /*!< ADC 2nd conversion in regular sequence */

+#define ADC_SQR1_SQ2_0                    (0x01UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00001000 */

+#define ADC_SQR1_SQ2_1                    (0x02UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00002000 */

+#define ADC_SQR1_SQ2_2                    (0x04UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00004000 */

+#define ADC_SQR1_SQ2_3                    (0x08UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00008000 */

+#define ADC_SQR1_SQ2_4                    (0x10UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00010000 */

+

+#define ADC_SQR1_SQ3_Pos                  (18U)

+#define ADC_SQR1_SQ3_Msk                  (0x1FUL << ADC_SQR1_SQ3_Pos)         /*!< 0x007C0000 */

+#define ADC_SQR1_SQ3                      ADC_SQR1_SQ3_Msk                     /*!< ADC 3rd conversion in regular sequence */

+#define ADC_SQR1_SQ3_0                    (0x01UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00040000 */

+#define ADC_SQR1_SQ3_1                    (0x02UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00080000 */

+#define ADC_SQR1_SQ3_2                    (0x04UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00100000 */

+#define ADC_SQR1_SQ3_3                    (0x08UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00200000 */

+#define ADC_SQR1_SQ3_4                    (0x10UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00400000 */

+

+#define ADC_SQR1_SQ4_Pos                  (24U)

+#define ADC_SQR1_SQ4_Msk                  (0x1FUL << ADC_SQR1_SQ4_Pos)         /*!< 0x1F000000 */

+#define ADC_SQR1_SQ4                      ADC_SQR1_SQ4_Msk                     /*!< ADC 4th conversion in regular sequence */

+#define ADC_SQR1_SQ4_0                    (0x01UL << ADC_SQR1_SQ4_Pos)          /*!< 0x01000000 */

+#define ADC_SQR1_SQ4_1                    (0x02UL << ADC_SQR1_SQ4_Pos)          /*!< 0x02000000 */

+#define ADC_SQR1_SQ4_2                    (0x04UL << ADC_SQR1_SQ4_Pos)          /*!< 0x04000000 */

+#define ADC_SQR1_SQ4_3                    (0x08UL << ADC_SQR1_SQ4_Pos)          /*!< 0x08000000 */

+#define ADC_SQR1_SQ4_4                    (0x10UL << ADC_SQR1_SQ4_Pos)          /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR2 register  ********************/

+#define ADC_SQR2_SQ5_Pos                  (0U)

+#define ADC_SQR2_SQ5_Msk                  (0x1FUL << ADC_SQR2_SQ5_Pos)         /*!< 0x0000001F */

+#define ADC_SQR2_SQ5                      ADC_SQR2_SQ5_Msk                     /*!< ADC 5th conversion in regular sequence */

+#define ADC_SQR2_SQ5_0                    (0x01UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000001 */

+#define ADC_SQR2_SQ5_1                    (0x02UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000002 */

+#define ADC_SQR2_SQ5_2                    (0x04UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000004 */

+#define ADC_SQR2_SQ5_3                    (0x08UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000008 */

+#define ADC_SQR2_SQ5_4                    (0x10UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000010 */

+

+#define ADC_SQR2_SQ6_Pos                  (6U)

+#define ADC_SQR2_SQ6_Msk                  (0x1FUL << ADC_SQR2_SQ6_Pos)         /*!< 0x000007C0 */

+#define ADC_SQR2_SQ6                      ADC_SQR2_SQ6_Msk                     /*!< ADC 6th conversion in regular sequence */

+#define ADC_SQR2_SQ6_0                    (0x01UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000040 */

+#define ADC_SQR2_SQ6_1                    (0x02UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000080 */

+#define ADC_SQR2_SQ6_2                    (0x04UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000100 */

+#define ADC_SQR2_SQ6_3                    (0x08UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000200 */

+#define ADC_SQR2_SQ6_4                    (0x10UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000400 */

+

+#define ADC_SQR2_SQ7_Pos                  (12U)

+#define ADC_SQR2_SQ7_Msk                  (0x1FUL << ADC_SQR2_SQ7_Pos)         /*!< 0x0001F000 */

+#define ADC_SQR2_SQ7                      ADC_SQR2_SQ7_Msk                     /*!< ADC 7th conversion in regular sequence */

+#define ADC_SQR2_SQ7_0                    (0x01UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00001000 */

+#define ADC_SQR2_SQ7_1                    (0x02UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00002000 */

+#define ADC_SQR2_SQ7_2                    (0x04UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00004000 */

+#define ADC_SQR2_SQ7_3                    (0x08UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00008000 */

+#define ADC_SQR2_SQ7_4                    (0x10UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00010000 */

+

+#define ADC_SQR2_SQ8_Pos                  (18U)

+#define ADC_SQR2_SQ8_Msk                  (0x1FUL << ADC_SQR2_SQ8_Pos)         /*!< 0x007C0000 */

+#define ADC_SQR2_SQ8                      ADC_SQR2_SQ8_Msk                     /*!< ADC 8th conversion in regular sequence */

+#define ADC_SQR2_SQ8_0                    (0x01UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00040000 */

+#define ADC_SQR2_SQ8_1                    (0x02UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00080000 */

+#define ADC_SQR2_SQ8_2                    (0x04UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00100000 */

+#define ADC_SQR2_SQ8_3                    (0x08UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00200000 */

+#define ADC_SQR2_SQ8_4                    (0x10UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00400000 */

+

+#define ADC_SQR2_SQ9_Pos                  (24U)

+#define ADC_SQR2_SQ9_Msk                  (0x1FUL << ADC_SQR2_SQ9_Pos)         /*!< 0x1F000000 */

+#define ADC_SQR2_SQ9                      ADC_SQR2_SQ9_Msk                     /*!< ADC 9th conversion in regular sequence */

+#define ADC_SQR2_SQ9_0                    (0x01UL << ADC_SQR2_SQ9_Pos)          /*!< 0x01000000 */

+#define ADC_SQR2_SQ9_1                    (0x02UL << ADC_SQR2_SQ9_Pos)          /*!< 0x02000000 */

+#define ADC_SQR2_SQ9_2                    (0x04UL << ADC_SQR2_SQ9_Pos)          /*!< 0x04000000 */

+#define ADC_SQR2_SQ9_3                    (0x08UL << ADC_SQR2_SQ9_Pos)          /*!< 0x08000000 */

+#define ADC_SQR2_SQ9_4                    (0x10UL << ADC_SQR2_SQ9_Pos)          /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR3 register  ********************/

+#define ADC_SQR3_SQ10_Pos                 (0U)

+#define ADC_SQR3_SQ10_Msk                 (0x1FUL << ADC_SQR3_SQ10_Pos)        /*!< 0x0000001F */

+#define ADC_SQR3_SQ10                     ADC_SQR3_SQ10_Msk                    /*!< ADC 10th conversion in regular sequence */

+#define ADC_SQR3_SQ10_0                   (0x01UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000001 */

+#define ADC_SQR3_SQ10_1                   (0x02UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000002 */

+#define ADC_SQR3_SQ10_2                   (0x04UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000004 */

+#define ADC_SQR3_SQ10_3                   (0x08UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000008 */

+#define ADC_SQR3_SQ10_4                   (0x10UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000010 */

+

+#define ADC_SQR3_SQ11_Pos                 (6U)

+#define ADC_SQR3_SQ11_Msk                 (0x1FUL << ADC_SQR3_SQ11_Pos)        /*!< 0x000007C0 */

+#define ADC_SQR3_SQ11                     ADC_SQR3_SQ11_Msk                    /*!< ADC 11th conversion in regular sequence */

+#define ADC_SQR3_SQ11_0                   (0x01UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000040 */

+#define ADC_SQR3_SQ11_1                   (0x02UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000080 */

+#define ADC_SQR3_SQ11_2                   (0x04UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000100 */

+#define ADC_SQR3_SQ11_3                   (0x08UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000200 */

+#define ADC_SQR3_SQ11_4                   (0x10UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000400 */

+

+#define ADC_SQR3_SQ12_Pos                 (12U)

+#define ADC_SQR3_SQ12_Msk                 (0x1FUL << ADC_SQR3_SQ12_Pos)        /*!< 0x0001F000 */

+#define ADC_SQR3_SQ12                     ADC_SQR3_SQ12_Msk                    /*!< ADC 12th conversion in regular sequence */

+#define ADC_SQR3_SQ12_0                   (0x01UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00001000 */

+#define ADC_SQR3_SQ12_1                   (0x02UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00002000 */

+#define ADC_SQR3_SQ12_2                   (0x04UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00004000 */

+#define ADC_SQR3_SQ12_3                   (0x08UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00008000 */

+#define ADC_SQR3_SQ12_4                   (0x10UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00010000 */

+

+#define ADC_SQR3_SQ13_Pos                 (18U)

+#define ADC_SQR3_SQ13_Msk                 (0x1FUL << ADC_SQR3_SQ13_Pos)        /*!< 0x007C0000 */

+#define ADC_SQR3_SQ13                     ADC_SQR3_SQ13_Msk                    /*!< ADC 13th conversion in regular sequence */

+#define ADC_SQR3_SQ13_0                   (0x01UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00040000 */

+#define ADC_SQR3_SQ13_1                   (0x02UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00080000 */

+#define ADC_SQR3_SQ13_2                   (0x04UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00100000 */

+#define ADC_SQR3_SQ13_3                   (0x08UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00200000 */

+#define ADC_SQR3_SQ13_4                   (0x10UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00400000 */

+

+#define ADC_SQR3_SQ14_Pos                 (24U)

+#define ADC_SQR3_SQ14_Msk                 (0x1FUL << ADC_SQR3_SQ14_Pos)        /*!< 0x1F000000 */

+#define ADC_SQR3_SQ14                     ADC_SQR3_SQ14_Msk                    /*!< ADC 14th conversion in regular sequence */

+#define ADC_SQR3_SQ14_0                   (0x01UL << ADC_SQR3_SQ14_Pos)         /*!< 0x01000000 */

+#define ADC_SQR3_SQ14_1                   (0x02UL << ADC_SQR3_SQ14_Pos)         /*!< 0x02000000 */

+#define ADC_SQR3_SQ14_2                   (0x04UL << ADC_SQR3_SQ14_Pos)         /*!< 0x04000000 */

+#define ADC_SQR3_SQ14_3                   (0x08UL << ADC_SQR3_SQ14_Pos)         /*!< 0x08000000 */

+#define ADC_SQR3_SQ14_4                   (0x10UL << ADC_SQR3_SQ14_Pos)         /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR4 register  ********************/

+#define ADC_SQR4_SQ15_Pos                 (0U)

+#define ADC_SQR4_SQ15_Msk                 (0x1FUL << ADC_SQR4_SQ15_Pos)        /*!< 0x0000001F */

+#define ADC_SQR4_SQ15                     ADC_SQR4_SQ15_Msk                    /*!< ADC 15th conversion in regular sequence */

+#define ADC_SQR4_SQ15_0                   (0x01UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000001 */

+#define ADC_SQR4_SQ15_1                   (0x02UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000002 */

+#define ADC_SQR4_SQ15_2                   (0x04UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000004 */

+#define ADC_SQR4_SQ15_3                   (0x08UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000008 */

+#define ADC_SQR4_SQ15_4                   (0x10UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000010 */

+

+#define ADC_SQR4_SQ16_Pos                 (6U)

+#define ADC_SQR4_SQ16_Msk                 (0x1FUL << ADC_SQR4_SQ16_Pos)        /*!< 0x000007C0 */

+#define ADC_SQR4_SQ16                     ADC_SQR4_SQ16_Msk                    /*!< ADC 16th conversion in regular sequence */

+#define ADC_SQR4_SQ16_0                   (0x01UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000040 */

+#define ADC_SQR4_SQ16_1                   (0x02UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000080 */

+#define ADC_SQR4_SQ16_2                   (0x04UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000100 */

+#define ADC_SQR4_SQ16_3                   (0x08UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000200 */

+#define ADC_SQR4_SQ16_4                   (0x10UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000400 */

+/********************  Bit definition for ADC_DR register  ********************/

+#define ADC_DR_RDATA_Pos                  (0U)

+#define ADC_DR_RDATA_Msk                  (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)   /*!< 0xFFFFFFFF */

+#define ADC_DR_RDATA                      ADC_DR_RDATA_Msk                     /*!< ADC regular Data converted */

+

+/********************  Bit definition for ADC_JSQR register  ********************/

+#define ADC_JSQR_JL_Pos                   (0U)

+#define ADC_JSQR_JL_Msk                   (0x3UL << ADC_JSQR_JL_Pos)           /*!< 0x00000003 */

+#define ADC_JSQR_JL                       ADC_JSQR_JL_Msk                      /*!< ADC injected channel sequence length */

+#define ADC_JSQR_JL_0                     (0x1UL << ADC_JSQR_JL_Pos)           /*!< 0x00000001 */

+#define ADC_JSQR_JL_1                     (0x2UL << ADC_JSQR_JL_Pos)           /*!< 0x00000002 */

+

+#define ADC_JSQR_JEXTSEL_Pos              (2U)

+#define ADC_JSQR_JEXTSEL_Msk              (0x1FUL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x0000007C */

+#define ADC_JSQR_JEXTSEL                  ADC_JSQR_JEXTSEL_Msk                 /*!< ADC external trigger selection for injected group */

+#define ADC_JSQR_JEXTSEL_0                (0x01UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000004 */

+#define ADC_JSQR_JEXTSEL_1                (0x02UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000008 */

+#define ADC_JSQR_JEXTSEL_2                (0x04UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000010 */

+#define ADC_JSQR_JEXTSEL_3                (0x08UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000020 */

+#define ADC_JSQR_JEXTSEL_4                (0x10UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000040 */

+

+#define ADC_JSQR_JEXTEN_Pos               (7U)

+#define ADC_JSQR_JEXTEN_Msk               (0x3UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000180 */

+#define ADC_JSQR_JEXTEN                   ADC_JSQR_JEXTEN_Msk                  /*!< ADC external trigger enable and polarity selection for injected channels */

+#define ADC_JSQR_JEXTEN_0                 (0x1UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000080 */

+#define ADC_JSQR_JEXTEN_1                 (0x2UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000100 */

+

+#define ADC_JSQR_JSQ1_Pos                 (9U)

+#define ADC_JSQR_JSQ1_Msk                 (0x1FUL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00003E00 */

+#define ADC_JSQR_JSQ1                     ADC_JSQR_JSQ1_Msk                    /*!< ADC 1st conversion in injected sequence */

+#define ADC_JSQR_JSQ1_0                   (0x01UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000200 */

+#define ADC_JSQR_JSQ1_1                   (0x02UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000400 */

+#define ADC_JSQR_JSQ1_2                   (0x04UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000800 */

+#define ADC_JSQR_JSQ1_3                   (0x08UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00001000 */

+#define ADC_JSQR_JSQ1_4                   (0x10UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00002000 */

+

+#define ADC_JSQR_JSQ2_Pos                 (15U)

+#define ADC_JSQR_JSQ2_Msk                 (0x1FUL << ADC_JSQR_JSQ2_Pos)        /*!< 0x000F8000 */

+#define ADC_JSQR_JSQ2                     ADC_JSQR_JSQ2_Msk                    /*!< ADC 2nd conversion in injected sequence */

+#define ADC_JSQR_JSQ2_0                   (0x01UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00008000 */

+#define ADC_JSQR_JSQ2_1                   (0x02UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00010000 */

+#define ADC_JSQR_JSQ2_2                   (0x04UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00020000 */

+#define ADC_JSQR_JSQ2_3                   (0x08UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00040000 */

+#define ADC_JSQR_JSQ2_4                   (0x10UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00080000 */

+

+#define ADC_JSQR_JSQ3_Pos                 (21U)

+#define ADC_JSQR_JSQ3_Msk                 (0x1FUL << ADC_JSQR_JSQ3_Pos)        /*!< 0x03E00000 */

+#define ADC_JSQR_JSQ3                     ADC_JSQR_JSQ3_Msk                    /*!< ADC 3rd conversion in injected sequence */

+#define ADC_JSQR_JSQ3_0                   (0x01UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00200000 */

+#define ADC_JSQR_JSQ3_1                   (0x02UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00400000 */

+#define ADC_JSQR_JSQ3_2                   (0x04UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00800000 */

+#define ADC_JSQR_JSQ3_3                   (0x08UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x01000000 */

+#define ADC_JSQR_JSQ3_4                   (0x10UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x02000000 */

+

+#define ADC_JSQR_JSQ4_Pos                 (27U)

+#define ADC_JSQR_JSQ4_Msk                 (0x1FUL << ADC_JSQR_JSQ4_Pos)        /*!< 0xF8000000 */

+#define ADC_JSQR_JSQ4                     ADC_JSQR_JSQ4_Msk                    /*!< ADC 4th conversion in injected sequence */

+#define ADC_JSQR_JSQ4_0                   (0x01UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x08000000 */

+#define ADC_JSQR_JSQ4_1                   (0x02UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x10000000 */

+#define ADC_JSQR_JSQ4_2                   (0x04UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x20000000 */

+#define ADC_JSQR_JSQ4_3                   (0x08UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x40000000 */

+#define ADC_JSQR_JSQ4_4                   (0x10UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_OFR1 register  ********************/

+#define ADC_OFR1_OFFSET1_Pos              (0U)

+#define ADC_OFR1_OFFSET1_Msk              (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR1_OFFSET1                  ADC_OFR1_OFFSET1_Msk                  /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */

+#define ADC_OFR1_OFFSET1_0                (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */

+#define ADC_OFR1_OFFSET1_1                (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */

+#define ADC_OFR1_OFFSET1_2                (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */

+#define ADC_OFR1_OFFSET1_3                (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */

+#define ADC_OFR1_OFFSET1_4                (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */

+#define ADC_OFR1_OFFSET1_5                (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */

+#define ADC_OFR1_OFFSET1_6                (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */

+#define ADC_OFR1_OFFSET1_7                (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */

+#define ADC_OFR1_OFFSET1_8                (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */

+#define ADC_OFR1_OFFSET1_9                (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */

+#define ADC_OFR1_OFFSET1_10               (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */

+#define ADC_OFR1_OFFSET1_11               (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */

+#define ADC_OFR1_OFFSET1_12               (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */

+#define ADC_OFR1_OFFSET1_13               (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */

+#define ADC_OFR1_OFFSET1_14               (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */

+#define ADC_OFR1_OFFSET1_15               (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */

+#define ADC_OFR1_OFFSET1_16               (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */

+#define ADC_OFR1_OFFSET1_17               (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */

+#define ADC_OFR1_OFFSET1_18               (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */

+#define ADC_OFR1_OFFSET1_19               (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */

+#define ADC_OFR1_OFFSET1_20               (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */

+#define ADC_OFR1_OFFSET1_21               (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */

+#define ADC_OFR1_OFFSET1_22               (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */

+#define ADC_OFR1_OFFSET1_23               (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */

+#define ADC_OFR1_OFFSET1_24               (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */

+#define ADC_OFR1_OFFSET1_25               (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR1_OFFSET1_CH_Pos           (26U)

+#define ADC_OFR1_OFFSET1_CH_Msk           (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR1_OFFSET1_CH               ADC_OFR1_OFFSET1_CH_Msk               /*!< ADC Channel selection for the data offset 1 */

+#define ADC_OFR1_OFFSET1_CH_0             (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR1_OFFSET1_CH_1             (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR1_OFFSET1_CH_2             (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR1_OFFSET1_CH_3             (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR1_OFFSET1_CH_4             (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR1_SSATE_Pos                (31U)

+#define ADC_OFR1_SSATE_Msk                (0x1UL << ADC_OFR1_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR1_SSATE                    ADC_OFR1_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR2 register  ********************/

+#define ADC_OFR2_OFFSET2_Pos              (0U)

+#define ADC_OFR2_OFFSET2_Msk              (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR2_OFFSET2                  ADC_OFR2_OFFSET2_Msk                  /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */

+#define ADC_OFR2_OFFSET2_0                (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */

+#define ADC_OFR2_OFFSET2_1                (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */

+#define ADC_OFR2_OFFSET2_2                (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */

+#define ADC_OFR2_OFFSET2_3                (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */

+#define ADC_OFR2_OFFSET2_4                (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */

+#define ADC_OFR2_OFFSET2_5                (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */

+#define ADC_OFR2_OFFSET2_6                (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */

+#define ADC_OFR2_OFFSET2_7                (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */

+#define ADC_OFR2_OFFSET2_8                (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */

+#define ADC_OFR2_OFFSET2_9                (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */

+#define ADC_OFR2_OFFSET2_10               (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */

+#define ADC_OFR2_OFFSET2_11               (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */

+#define ADC_OFR2_OFFSET2_12               (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */

+#define ADC_OFR2_OFFSET2_13               (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */

+#define ADC_OFR2_OFFSET2_14               (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */

+#define ADC_OFR2_OFFSET2_15               (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */

+#define ADC_OFR2_OFFSET2_16               (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */

+#define ADC_OFR2_OFFSET2_17               (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */

+#define ADC_OFR2_OFFSET2_18               (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */

+#define ADC_OFR2_OFFSET2_19               (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */

+#define ADC_OFR2_OFFSET2_20               (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */

+#define ADC_OFR2_OFFSET2_21               (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */

+#define ADC_OFR2_OFFSET2_22               (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */

+#define ADC_OFR2_OFFSET2_23               (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */

+#define ADC_OFR2_OFFSET2_24               (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */

+#define ADC_OFR2_OFFSET2_25               (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR2_OFFSET2_CH_Pos           (26U)

+#define ADC_OFR2_OFFSET2_CH_Msk           (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR2_OFFSET2_CH               ADC_OFR2_OFFSET2_CH_Msk               /*!< ADC Channel selection for the data offset 2 */

+#define ADC_OFR2_OFFSET2_CH_0             (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR2_OFFSET2_CH_1             (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR2_OFFSET2_CH_2             (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR2_OFFSET2_CH_3             (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR2_OFFSET2_CH_4             (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR2_SSATE_Pos                (31U)

+#define ADC_OFR2_SSATE_Msk                (0x1UL << ADC_OFR2_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR2_SSATE                    ADC_OFR2_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR3 register  ********************/

+#define ADC_OFR3_OFFSET3_Pos              (0U)

+#define ADC_OFR3_OFFSET3_Msk              (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR3_OFFSET3                  ADC_OFR3_OFFSET3_Msk                  /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */

+#define ADC_OFR3_OFFSET3_0                (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */

+#define ADC_OFR3_OFFSET3_1                (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */

+#define ADC_OFR3_OFFSET3_2                (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */

+#define ADC_OFR3_OFFSET3_3                (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */

+#define ADC_OFR3_OFFSET3_4                (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */

+#define ADC_OFR3_OFFSET3_5                (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */

+#define ADC_OFR3_OFFSET3_6                (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */

+#define ADC_OFR3_OFFSET3_7                (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */

+#define ADC_OFR3_OFFSET3_8                (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */

+#define ADC_OFR3_OFFSET3_9                (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */

+#define ADC_OFR3_OFFSET3_10               (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */

+#define ADC_OFR3_OFFSET3_11               (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */

+#define ADC_OFR3_OFFSET3_12               (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */

+#define ADC_OFR3_OFFSET3_13               (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */

+#define ADC_OFR3_OFFSET3_14               (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */

+#define ADC_OFR3_OFFSET3_15               (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */

+#define ADC_OFR3_OFFSET3_16               (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */

+#define ADC_OFR3_OFFSET3_17               (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */

+#define ADC_OFR3_OFFSET3_18               (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */

+#define ADC_OFR3_OFFSET3_19               (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */

+#define ADC_OFR3_OFFSET3_20               (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */

+#define ADC_OFR3_OFFSET3_21               (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */

+#define ADC_OFR3_OFFSET3_22               (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */

+#define ADC_OFR3_OFFSET3_23               (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */

+#define ADC_OFR3_OFFSET3_24               (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */

+#define ADC_OFR3_OFFSET3_25               (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR3_OFFSET3_CH_Pos           (26U)

+#define ADC_OFR3_OFFSET3_CH_Msk           (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR3_OFFSET3_CH               ADC_OFR3_OFFSET3_CH_Msk               /*!< ADC Channel selection for the data offset 3 */

+#define ADC_OFR3_OFFSET3_CH_0             (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR3_OFFSET3_CH_1             (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR3_OFFSET3_CH_2             (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR3_OFFSET3_CH_3             (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR3_OFFSET3_CH_4             (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR3_SSATE_Pos                (31U)

+#define ADC_OFR3_SSATE_Msk                (0x1UL << ADC_OFR3_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR3_SSATE                    ADC_OFR3_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR4 register  ********************/

+#define ADC_OFR4_OFFSET4_Pos              (0U)

+#define ADC_OFR4_OFFSET4_Msk              (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR4_OFFSET4                  ADC_OFR4_OFFSET4_Msk                  /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */

+#define ADC_OFR4_OFFSET4_0                (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */

+#define ADC_OFR4_OFFSET4_1                (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */

+#define ADC_OFR4_OFFSET4_2                (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */

+#define ADC_OFR4_OFFSET4_3                (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */

+#define ADC_OFR4_OFFSET4_4                (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */

+#define ADC_OFR4_OFFSET4_5                (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */

+#define ADC_OFR4_OFFSET4_6                (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */

+#define ADC_OFR4_OFFSET4_7                (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */

+#define ADC_OFR4_OFFSET4_8                (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */

+#define ADC_OFR4_OFFSET4_9                (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */

+#define ADC_OFR4_OFFSET4_10               (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */

+#define ADC_OFR4_OFFSET4_11               (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */

+#define ADC_OFR4_OFFSET4_12               (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */

+#define ADC_OFR4_OFFSET4_13               (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */

+#define ADC_OFR4_OFFSET4_14               (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */

+#define ADC_OFR4_OFFSET4_15               (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */

+#define ADC_OFR4_OFFSET4_16               (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */

+#define ADC_OFR4_OFFSET4_17               (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */

+#define ADC_OFR4_OFFSET4_18               (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */

+#define ADC_OFR4_OFFSET4_19               (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */

+#define ADC_OFR4_OFFSET4_20               (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */

+#define ADC_OFR4_OFFSET4_21               (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */

+#define ADC_OFR4_OFFSET4_22               (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */

+#define ADC_OFR4_OFFSET4_23               (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */

+#define ADC_OFR4_OFFSET4_24               (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */

+#define ADC_OFR4_OFFSET4_25               (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR4_OFFSET4_CH_Pos           (26U)

+#define ADC_OFR4_OFFSET4_CH_Msk           (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR4_OFFSET4_CH               ADC_OFR4_OFFSET4_CH_Msk               /*!< ADC Channel selection for the data offset 4 */

+#define ADC_OFR4_OFFSET4_CH_0             (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR4_OFFSET4_CH_1             (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR4_OFFSET4_CH_2             (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR4_OFFSET4_CH_3             (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR4_OFFSET4_CH_4             (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR4_SSATE_Pos                (31U)

+#define ADC_OFR4_SSATE_Msk                (0x1UL << ADC_OFR4_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR4_SSATE                    ADC_OFR4_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_JDR1 register  ********************/

+#define ADC_JDR1_JDATA_Pos                (0U)

+#define ADC_JDR1_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR1_JDATA                    ADC_JDR1_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR1_JDATA_0                  (0x00000001UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR1_JDATA_1                  (0x00000002UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR1_JDATA_2                  (0x00000004UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR1_JDATA_3                  (0x00000008UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR1_JDATA_4                  (0x00000010UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR1_JDATA_5                  (0x00000020UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR1_JDATA_6                  (0x00000040UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR1_JDATA_7                  (0x00000080UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR1_JDATA_8                  (0x00000100UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR1_JDATA_9                  (0x00000200UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR1_JDATA_10                 (0x00000400UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR1_JDATA_11                 (0x00000800UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR1_JDATA_12                 (0x00001000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR1_JDATA_13                 (0x00002000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR1_JDATA_14                 (0x00004000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR1_JDATA_15                 (0x00008000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR1_JDATA_16                 (0x00010000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR1_JDATA_17                 (0x00020000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR1_JDATA_18                 (0x00040000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR1_JDATA_19                 (0x00080000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR1_JDATA_20                 (0x00100000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR1_JDATA_21                 (0x00200000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR1_JDATA_22                 (0x00400000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR1_JDATA_23                 (0x00800000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR1_JDATA_24                 (0x01000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR1_JDATA_25                 (0x02000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR1_JDATA_26                 (0x04000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR1_JDATA_27                 (0x08000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR1_JDATA_28                 (0x10000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR1_JDATA_29                 (0x20000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR1_JDATA_30                 (0x40000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR1_JDATA_31                 (0x80000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR2 register  ********************/

+#define ADC_JDR2_JDATA_Pos                (0U)

+#define ADC_JDR2_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR2_JDATA                    ADC_JDR2_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR2_JDATA_0                  (0x00000001UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR2_JDATA_1                  (0x00000002UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR2_JDATA_2                  (0x00000004UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR2_JDATA_3                  (0x00000008UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR2_JDATA_4                  (0x00000010UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR2_JDATA_5                  (0x00000020UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR2_JDATA_6                  (0x00000040UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR2_JDATA_7                  (0x00000080UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR2_JDATA_8                  (0x00000100UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR2_JDATA_9                  (0x00000200UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR2_JDATA_10                 (0x00000400UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR2_JDATA_11                 (0x00000800UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR2_JDATA_12                 (0x00001000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR2_JDATA_13                 (0x00002000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR2_JDATA_14                 (0x00004000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR2_JDATA_15                 (0x00008000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR2_JDATA_16                 (0x00010000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR2_JDATA_17                 (0x00020000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR2_JDATA_18                 (0x00040000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR2_JDATA_19                 (0x00080000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR2_JDATA_20                 (0x00100000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR2_JDATA_21                 (0x00200000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR2_JDATA_22                 (0x00400000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR2_JDATA_23                 (0x00800000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR2_JDATA_24                 (0x01000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR2_JDATA_25                 (0x02000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR2_JDATA_26                 (0x04000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR2_JDATA_27                 (0x08000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR2_JDATA_28                 (0x10000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR2_JDATA_29                 (0x20000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR2_JDATA_30                 (0x40000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR2_JDATA_31                 (0x80000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR3 register  ********************/

+#define ADC_JDR3_JDATA_Pos                (0U)

+#define ADC_JDR3_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR3_JDATA                    ADC_JDR3_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR3_JDATA_0                  (0x00000001UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR3_JDATA_1                  (0x00000002UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR3_JDATA_2                  (0x00000004UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR3_JDATA_3                  (0x00000008UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR3_JDATA_4                  (0x00000010UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR3_JDATA_5                  (0x00000020UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR3_JDATA_6                  (0x00000040UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR3_JDATA_7                  (0x00000080UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR3_JDATA_8                  (0x00000100UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR3_JDATA_9                  (0x00000200UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR3_JDATA_10                 (0x00000400UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR3_JDATA_11                 (0x00000800UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR3_JDATA_12                 (0x00001000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR3_JDATA_13                 (0x00002000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR3_JDATA_14                 (0x00004000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR3_JDATA_15                 (0x00008000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR3_JDATA_16                 (0x00010000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR3_JDATA_17                 (0x00020000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR3_JDATA_18                 (0x00040000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR3_JDATA_19                 (0x00080000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR3_JDATA_20                 (0x00100000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR3_JDATA_21                 (0x00200000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR3_JDATA_22                 (0x00400000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR3_JDATA_23                 (0x00800000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR3_JDATA_24                 (0x01000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR3_JDATA_25                 (0x02000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR3_JDATA_26                 (0x04000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR3_JDATA_27                 (0x08000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR3_JDATA_28                 (0x10000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR3_JDATA_29                 (0x20000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR3_JDATA_30                 (0x40000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR3_JDATA_31                 (0x80000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR4 register  ********************/

+#define ADC_JDR4_JDATA_Pos                (0U)

+#define ADC_JDR4_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR4_JDATA                    ADC_JDR4_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR4_JDATA_0                  (0x00000001UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR4_JDATA_1                  (0x00000002UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR4_JDATA_2                  (0x00000004UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR4_JDATA_3                  (0x00000008UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR4_JDATA_4                  (0x00000010UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR4_JDATA_5                  (0x00000020UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR4_JDATA_6                  (0x00000040UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR4_JDATA_7                  (0x00000080UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR4_JDATA_8                  (0x00000100UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR4_JDATA_9                  (0x00000200UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR4_JDATA_10                 (0x00000400UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR4_JDATA_11                 (0x00000800UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR4_JDATA_12                 (0x00001000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR4_JDATA_13                 (0x00002000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR4_JDATA_14                 (0x00004000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR4_JDATA_15                 (0x00008000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR4_JDATA_16                 (0x00010000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR4_JDATA_17                 (0x00020000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR4_JDATA_18                 (0x00040000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR4_JDATA_19                 (0x00080000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR4_JDATA_20                 (0x00100000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR4_JDATA_21                 (0x00200000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR4_JDATA_22                 (0x00400000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR4_JDATA_23                 (0x00800000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR4_JDATA_24                 (0x01000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR4_JDATA_25                 (0x02000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR4_JDATA_26                 (0x04000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR4_JDATA_27                 (0x08000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR4_JDATA_28                 (0x10000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR4_JDATA_29                 (0x20000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR4_JDATA_30                 (0x40000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR4_JDATA_31                 (0x80000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_AWD2CR register  ********************/

+#define ADC_AWD2CR_AWD2CH_Pos             (0U)

+#define ADC_AWD2CR_AWD2CH_Msk             (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x000FFFFF */

+#define ADC_AWD2CR_AWD2CH                 ADC_AWD2CR_AWD2CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */

+#define ADC_AWD2CR_AWD2CH_0               (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000001 */

+#define ADC_AWD2CR_AWD2CH_1               (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000002 */

+#define ADC_AWD2CR_AWD2CH_2               (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000004 */

+#define ADC_AWD2CR_AWD2CH_3               (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000008 */

+#define ADC_AWD2CR_AWD2CH_4               (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000010 */

+#define ADC_AWD2CR_AWD2CH_5               (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000020 */

+#define ADC_AWD2CR_AWD2CH_6               (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000040 */

+#define ADC_AWD2CR_AWD2CH_7               (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000080 */

+#define ADC_AWD2CR_AWD2CH_8               (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000100 */

+#define ADC_AWD2CR_AWD2CH_9               (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000200 */

+#define ADC_AWD2CR_AWD2CH_10              (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000400 */

+#define ADC_AWD2CR_AWD2CH_11              (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000800 */

+#define ADC_AWD2CR_AWD2CH_12              (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00001000 */

+#define ADC_AWD2CR_AWD2CH_13              (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00002000 */

+#define ADC_AWD2CR_AWD2CH_14              (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00004000 */

+#define ADC_AWD2CR_AWD2CH_15              (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00008000 */

+#define ADC_AWD2CR_AWD2CH_16              (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00010000 */

+#define ADC_AWD2CR_AWD2CH_17              (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00020000 */

+#define ADC_AWD2CR_AWD2CH_18              (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */

+#define ADC_AWD2CR_AWD2CH_19              (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_AWD3CR register  ********************/

+#define ADC_AWD3CR_AWD3CH_Pos             (0U)

+#define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x000FFFFF */

+#define ADC_AWD3CR_AWD3CH                 ADC_AWD3CR_AWD3CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */

+#define ADC_AWD3CR_AWD3CH_0               (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000001 */

+#define ADC_AWD3CR_AWD3CH_1               (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000002 */

+#define ADC_AWD3CR_AWD3CH_2               (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000004 */

+#define ADC_AWD3CR_AWD3CH_3               (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000008 */

+#define ADC_AWD3CR_AWD3CH_4               (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000010 */

+#define ADC_AWD3CR_AWD3CH_5               (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000020 */

+#define ADC_AWD3CR_AWD3CH_6               (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000040 */

+#define ADC_AWD3CR_AWD3CH_7               (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000080 */

+#define ADC_AWD3CR_AWD3CH_8               (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000100 */

+#define ADC_AWD3CR_AWD3CH_9               (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000200 */

+#define ADC_AWD3CR_AWD3CH_10              (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000400 */

+#define ADC_AWD3CR_AWD3CH_11              (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000800 */

+#define ADC_AWD3CR_AWD3CH_12              (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00001000 */

+#define ADC_AWD3CR_AWD3CH_13              (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00002000 */

+#define ADC_AWD3CR_AWD3CH_14              (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00004000 */

+#define ADC_AWD3CR_AWD3CH_15              (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00008000 */

+#define ADC_AWD3CR_AWD3CH_16              (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00010000 */

+#define ADC_AWD3CR_AWD3CH_17              (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00020000 */

+#define ADC_AWD3CR_AWD3CH_18              (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */

+#define ADC_AWD3CR_AWD3CH_19              (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_DIFSEL register  ********************/

+#define ADC_DIFSEL_DIFSEL_Pos             (0U)

+#define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */

+#define ADC_DIFSEL_DIFSEL                 ADC_DIFSEL_DIFSEL_Msk                 /*!< ADC differential modes for channels 1 to 18 */

+#define ADC_DIFSEL_DIFSEL_0               (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000001 */

+#define ADC_DIFSEL_DIFSEL_1               (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000002 */

+#define ADC_DIFSEL_DIFSEL_2               (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000004 */

+#define ADC_DIFSEL_DIFSEL_3               (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000008 */

+#define ADC_DIFSEL_DIFSEL_4               (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000010 */

+#define ADC_DIFSEL_DIFSEL_5               (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000020 */

+#define ADC_DIFSEL_DIFSEL_6               (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000040 */

+#define ADC_DIFSEL_DIFSEL_7               (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000080 */

+#define ADC_DIFSEL_DIFSEL_8               (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000100 */

+#define ADC_DIFSEL_DIFSEL_9               (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000200 */

+#define ADC_DIFSEL_DIFSEL_10              (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000400 */

+#define ADC_DIFSEL_DIFSEL_11              (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000800 */

+#define ADC_DIFSEL_DIFSEL_12              (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00001000 */

+#define ADC_DIFSEL_DIFSEL_13              (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00002000 */

+#define ADC_DIFSEL_DIFSEL_14              (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00004000 */

+#define ADC_DIFSEL_DIFSEL_15              (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00008000 */

+#define ADC_DIFSEL_DIFSEL_16              (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00010000 */

+#define ADC_DIFSEL_DIFSEL_17              (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00020000 */

+#define ADC_DIFSEL_DIFSEL_18              (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00040000 */

+#define ADC_DIFSEL_DIFSEL_19              (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_CALFACT register  ********************/

+#define ADC_CALFACT_CALFACT_S_Pos         (0U)

+#define ADC_CALFACT_CALFACT_S_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */

+#define ADC_CALFACT_CALFACT_S             ADC_CALFACT_CALFACT_S_Msk              /*!< ADC calibration factors in single-ended mode */

+#define ADC_CALFACT_CALFACT_S_0           (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */

+#define ADC_CALFACT_CALFACT_S_1           (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */

+#define ADC_CALFACT_CALFACT_S_2           (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */

+#define ADC_CALFACT_CALFACT_S_3           (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */

+#define ADC_CALFACT_CALFACT_S_4           (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */

+#define ADC_CALFACT_CALFACT_S_5           (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */

+#define ADC_CALFACT_CALFACT_S_6           (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */

+#define ADC_CALFACT_CALFACT_S_7           (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */

+#define ADC_CALFACT_CALFACT_S_8           (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */

+#define ADC_CALFACT_CALFACT_S_9           (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */

+#define ADC_CALFACT_CALFACT_S_10          (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */

+#define ADC_CALFACT_CALFACT_D_Pos         (16U)

+#define ADC_CALFACT_CALFACT_D_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */

+#define ADC_CALFACT_CALFACT_D             ADC_CALFACT_CALFACT_D_Msk              /*!< ADC calibration factors in differential mode */

+#define ADC_CALFACT_CALFACT_D_0           (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */

+#define ADC_CALFACT_CALFACT_D_1           (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */

+#define ADC_CALFACT_CALFACT_D_2           (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */

+#define ADC_CALFACT_CALFACT_D_3           (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */

+#define ADC_CALFACT_CALFACT_D_4           (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */

+#define ADC_CALFACT_CALFACT_D_5           (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */

+#define ADC_CALFACT_CALFACT_D_6           (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */

+#define ADC_CALFACT_CALFACT_D_7           (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */

+#define ADC_CALFACT_CALFACT_D_8           (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */

+#define ADC_CALFACT_CALFACT_D_9           (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */

+#define ADC_CALFACT_CALFACT_D_10          (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */

+

+/********************  Bit definition for ADC_CALFACT2 register  ********************/

+#define ADC_CALFACT2_LINCALFACT_Pos       (0U)

+#define ADC_CALFACT2_LINCALFACT_Msk       (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */

+#define ADC_CALFACT2_LINCALFACT           ADC_CALFACT2_LINCALFACT_Msk                   /*!< ADC Linearity calibration factors */

+#define ADC_CALFACT2_LINCALFACT_0         (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */

+#define ADC_CALFACT2_LINCALFACT_1         (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */

+#define ADC_CALFACT2_LINCALFACT_2         (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */

+#define ADC_CALFACT2_LINCALFACT_3         (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */

+#define ADC_CALFACT2_LINCALFACT_4         (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */

+#define ADC_CALFACT2_LINCALFACT_5         (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */

+#define ADC_CALFACT2_LINCALFACT_6         (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */

+#define ADC_CALFACT2_LINCALFACT_7         (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */

+#define ADC_CALFACT2_LINCALFACT_8         (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */

+#define ADC_CALFACT2_LINCALFACT_9         (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */

+#define ADC_CALFACT2_LINCALFACT_10        (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */

+#define ADC_CALFACT2_LINCALFACT_11        (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */

+#define ADC_CALFACT2_LINCALFACT_12        (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */

+#define ADC_CALFACT2_LINCALFACT_13        (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */

+#define ADC_CALFACT2_LINCALFACT_14        (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */

+#define ADC_CALFACT2_LINCALFACT_15        (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */

+#define ADC_CALFACT2_LINCALFACT_16        (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */

+#define ADC_CALFACT2_LINCALFACT_17        (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */

+#define ADC_CALFACT2_LINCALFACT_18        (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */

+#define ADC_CALFACT2_LINCALFACT_19        (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */

+#define ADC_CALFACT2_LINCALFACT_20        (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */

+#define ADC_CALFACT2_LINCALFACT_21        (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */

+#define ADC_CALFACT2_LINCALFACT_22        (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */

+#define ADC_CALFACT2_LINCALFACT_23        (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */

+#define ADC_CALFACT2_LINCALFACT_24        (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */

+#define ADC_CALFACT2_LINCALFACT_25        (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */

+#define ADC_CALFACT2_LINCALFACT_26        (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */

+#define ADC_CALFACT2_LINCALFACT_27        (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */

+#define ADC_CALFACT2_LINCALFACT_28        (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */

+#define ADC_CALFACT2_LINCALFACT_29        (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */

+

+/*************************  ADC Common registers  *****************************/

+/********************  Bit definition for ADC_CSR register  ********************/

+#define ADC_CSR_ADRDY_MST_Pos             (0U)

+#define ADC_CSR_ADRDY_MST_Msk             (0x1UL << ADC_CSR_ADRDY_MST_Pos)     /*!< 0x00000001 */

+#define ADC_CSR_ADRDY_MST                 ADC_CSR_ADRDY_MST_Msk                /*!< Master ADC ready */

+#define ADC_CSR_EOSMP_MST_Pos             (1U)

+#define ADC_CSR_EOSMP_MST_Msk             (0x1UL << ADC_CSR_EOSMP_MST_Pos)     /*!< 0x00000002 */

+#define ADC_CSR_EOSMP_MST                 ADC_CSR_EOSMP_MST_Msk                /*!< End of sampling phase flag of the master ADC */

+#define ADC_CSR_EOC_MST_Pos               (2U)

+#define ADC_CSR_EOC_MST_Msk               (0x1UL << ADC_CSR_EOC_MST_Pos)       /*!< 0x00000004 */

+#define ADC_CSR_EOC_MST                   ADC_CSR_EOC_MST_Msk                  /*!< End of regular conversion of the master ADC */

+#define ADC_CSR_EOS_MST_Pos               (3U)

+#define ADC_CSR_EOS_MST_Msk               (0x1UL << ADC_CSR_EOS_MST_Pos)       /*!< 0x00000008 */

+#define ADC_CSR_EOS_MST                   ADC_CSR_EOS_MST_Msk                  /*!< End of regular sequence flag of the master ADC */

+#define ADC_CSR_OVR_MST_Pos               (4U)

+#define ADC_CSR_OVR_MST_Msk               (0x1UL << ADC_CSR_OVR_MST_Pos)       /*!< 0x00000010 */

+#define ADC_CSR_OVR_MST                   ADC_CSR_OVR_MST_Msk                  /*!< Overrun flag of the master ADC */

+#define ADC_CSR_JEOC_MST_Pos              (5U)

+#define ADC_CSR_JEOC_MST_Msk              (0x1UL << ADC_CSR_JEOC_MST_Pos)      /*!< 0x00000020 */

+#define ADC_CSR_JEOC_MST                  ADC_CSR_JEOC_MST_Msk                 /*!< End of injected conversion of the master ADC */

+#define ADC_CSR_JEOS_MST_Pos              (6U)

+#define ADC_CSR_JEOS_MST_Msk              (0x1UL << ADC_CSR_JEOS_MST_Pos)      /*!< 0x00000040 */

+#define ADC_CSR_JEOS_MST                  ADC_CSR_JEOS_MST_Msk                 /*!< End of injected sequence flag of the master ADC */

+#define ADC_CSR_AWD1_MST_Pos              (7U)

+#define ADC_CSR_AWD1_MST_Msk              (0x1UL << ADC_CSR_AWD1_MST_Pos)      /*!< 0x00000080 */

+#define ADC_CSR_AWD1_MST                  ADC_CSR_AWD1_MST_Msk                 /*!< Analog watchdog 1 flag of the master ADC */

+#define ADC_CSR_AWD2_MST_Pos              (8U)

+#define ADC_CSR_AWD2_MST_Msk              (0x1UL << ADC_CSR_AWD2_MST_Pos)      /*!< 0x00000100 */

+#define ADC_CSR_AWD2_MST                  ADC_CSR_AWD2_MST_Msk                 /*!< Analog watchdog 2 flag of the master ADC */

+#define ADC_CSR_AWD3_MST_Pos              (9U)

+#define ADC_CSR_AWD3_MST_Msk              (0x1UL << ADC_CSR_AWD3_MST_Pos)      /*!< 0x00000200 */

+#define ADC_CSR_AWD3_MST                  ADC_CSR_AWD3_MST_Msk                 /*!< Analog watchdog 3 flag of the master ADC */

+#define ADC_CSR_JQOVF_MST_Pos             (10U)

+#define ADC_CSR_JQOVF_MST_Msk             (0x1UL << ADC_CSR_JQOVF_MST_Pos)     /*!< 0x00000400 */

+#define ADC_CSR_JQOVF_MST                 ADC_CSR_JQOVF_MST_Msk                /*!< Injected context queue overflow flag of the master ADC */

+#define ADC_CSR_ADRDY_SLV_Pos             (16U)

+#define ADC_CSR_ADRDY_SLV_Msk             (0x1UL << ADC_CSR_ADRDY_SLV_Pos)     /*!< 0x00010000 */

+#define ADC_CSR_ADRDY_SLV                 ADC_CSR_ADRDY_SLV_Msk                /*!< Slave ADC ready */

+#define ADC_CSR_EOSMP_SLV_Pos             (17U)

+#define ADC_CSR_EOSMP_SLV_Msk             (0x1UL << ADC_CSR_EOSMP_SLV_Pos)     /*!< 0x00020000 */

+#define ADC_CSR_EOSMP_SLV                 ADC_CSR_EOSMP_SLV_Msk                /*!< End of sampling phase flag of the slave ADC */

+#define ADC_CSR_EOC_SLV_Pos               (18U)

+#define ADC_CSR_EOC_SLV_Msk               (0x1UL << ADC_CSR_EOC_SLV_Pos)       /*!< 0x00040000 */

+#define ADC_CSR_EOC_SLV                   ADC_CSR_EOC_SLV_Msk                  /*!< End of regular conversion of the slave ADC */

+#define ADC_CSR_EOS_SLV_Pos               (19U)

+#define ADC_CSR_EOS_SLV_Msk               (0x1UL << ADC_CSR_EOS_SLV_Pos)       /*!< 0x00080000 */

+#define ADC_CSR_EOS_SLV                   ADC_CSR_EOS_SLV_Msk                  /*!< End of regular sequence flag of the slave ADC */

+#define ADC_CSR_OVR_SLV_Pos               (20U)

+#define ADC_CSR_OVR_SLV_Msk               (0x1UL << ADC_CSR_OVR_SLV_Pos)       /*!< 0x00100000 */

+#define ADC_CSR_OVR_SLV                   ADC_CSR_OVR_SLV_Msk                  /*!< Overrun flag of the slave ADC */

+#define ADC_CSR_JEOC_SLV_Pos              (21U)

+#define ADC_CSR_JEOC_SLV_Msk              (0x1UL << ADC_CSR_JEOC_SLV_Pos)      /*!< 0x00200000 */

+#define ADC_CSR_JEOC_SLV                  ADC_CSR_JEOC_SLV_Msk                 /*!< End of injected conversion of the slave ADC */

+#define ADC_CSR_JEOS_SLV_Pos              (22U)

+#define ADC_CSR_JEOS_SLV_Msk              (0x1UL << ADC_CSR_JEOS_SLV_Pos)      /*!< 0x00400000 */

+#define ADC_CSR_JEOS_SLV                  ADC_CSR_JEOS_SLV_Msk                 /*!< End of injected sequence flag of the slave ADC */

+#define ADC_CSR_AWD1_SLV_Pos              (23U)

+#define ADC_CSR_AWD1_SLV_Msk              (0x1UL << ADC_CSR_AWD1_SLV_Pos)      /*!< 0x00800000 */

+#define ADC_CSR_AWD1_SLV                  ADC_CSR_AWD1_SLV_Msk                 /*!< Analog watchdog 1 flag of the slave ADC */

+#define ADC_CSR_AWD2_SLV_Pos              (24U)

+#define ADC_CSR_AWD2_SLV_Msk              (0x1UL << ADC_CSR_AWD2_SLV_Pos)      /*!< 0x01000000 */

+#define ADC_CSR_AWD2_SLV                  ADC_CSR_AWD2_SLV_Msk                 /*!< Analog watchdog 2 flag of the slave ADC */

+#define ADC_CSR_AWD3_SLV_Pos              (25U)

+#define ADC_CSR_AWD3_SLV_Msk              (0x1UL << ADC_CSR_AWD3_SLV_Pos)      /*!< 0x02000000 */

+#define ADC_CSR_AWD3_SLV                  ADC_CSR_AWD3_SLV_Msk                 /*!< Analog watchdog 3 flag of the slave ADC */

+#define ADC_CSR_JQOVF_SLV_Pos             (26U)

+#define ADC_CSR_JQOVF_SLV_Msk             (0x1UL << ADC_CSR_JQOVF_SLV_Pos)     /*!< 0x04000000 */

+#define ADC_CSR_JQOVF_SLV                 ADC_CSR_JQOVF_SLV_Msk                /*!< Injected context queue overflow flag of the slave ADC */

+

+/********************  Bit definition for ADC_CCR register  ********************/

+#define ADC_CCR_DUAL_Pos                  (0U)

+#define ADC_CCR_DUAL_Msk                  (0x1FUL << ADC_CCR_DUAL_Pos)          /*!< 0x0000001F */

+#define ADC_CCR_DUAL                      ADC_CCR_DUAL_Msk                      /*!< Dual ADC mode selection */

+#define ADC_CCR_DUAL_0                    (0x01UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000001 */

+#define ADC_CCR_DUAL_1                    (0x02UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000002 */

+#define ADC_CCR_DUAL_2                    (0x04UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000004 */

+#define ADC_CCR_DUAL_3                    (0x08UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000008 */

+#define ADC_CCR_DUAL_4                    (0x10UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000010 */

+

+#define ADC_CCR_DELAY_Pos                 (8U)

+#define ADC_CCR_DELAY_Msk                 (0xFUL << ADC_CCR_DELAY_Pos)          /*!< 0x00000F00 */

+#define ADC_CCR_DELAY                     ADC_CCR_DELAY_Msk                     /*!< Delay between 2 sampling phases */

+#define ADC_CCR_DELAY_0                   (0x1UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000100 */

+#define ADC_CCR_DELAY_1                   (0x2UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000200 */

+#define ADC_CCR_DELAY_2                   (0x4UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000400 */

+#define ADC_CCR_DELAY_3                   (0x8UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000800 */

+

+

+#define ADC_CCR_DAMDF_Pos                 (14U)

+#define ADC_CCR_DAMDF_Msk                 (0x3UL << ADC_CCR_DAMDF_Pos)          /*!< 0x0000C000 */

+#define ADC_CCR_DAMDF                     ADC_CCR_DAMDF_Msk                     /*!< Dual ADC mode Data format */

+#define ADC_CCR_DAMDF_0                   (0x1UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00004000 */

+#define ADC_CCR_DAMDF_1                   (0x2UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00008000 */

+

+#define ADC_CCR_CKMODE_Pos                (16U)

+#define ADC_CCR_CKMODE_Msk                (0x3UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00030000 */

+#define ADC_CCR_CKMODE                    ADC_CCR_CKMODE_Msk                    /*!< ADC clock mode */

+#define ADC_CCR_CKMODE_0                  (0x1UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00010000 */

+#define ADC_CCR_CKMODE_1                  (0x2UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00020000 */

+

+#define ADC_CCR_PRESC_Pos                 (18U)

+#define ADC_CCR_PRESC_Msk                 (0xFUL << ADC_CCR_PRESC_Pos)          /*!< 0x003C0000 */

+#define ADC_CCR_PRESC                     ADC_CCR_PRESC_Msk                     /*!< ADC prescaler */

+#define ADC_CCR_PRESC_0                   (0x1UL << ADC_CCR_PRESC_Pos)          /*!< 0x00040000 */

+#define ADC_CCR_PRESC_1                   (0x2UL << ADC_CCR_PRESC_Pos)          /*!< 0x00080000 */

+#define ADC_CCR_PRESC_2                   (0x4UL << ADC_CCR_PRESC_Pos)          /*!< 0x00100000 */

+#define ADC_CCR_PRESC_3                   (0x8UL << ADC_CCR_PRESC_Pos)          /*!< 0x00200000 */

+

+#define ADC_CCR_VREFEN_Pos                (22U)

+#define ADC_CCR_VREFEN_Msk                (0x1UL << ADC_CCR_VREFEN_Pos)         /*!< 0x00400000 */

+#define ADC_CCR_VREFEN                    ADC_CCR_VREFEN_Msk                    /*!< VREFINT enable */

+#define ADC_CCR_TSEN_Pos                  (23U)

+#define ADC_CCR_TSEN_Msk                  (0x1UL << ADC_CCR_TSEN_Pos)           /*!< 0x00800000 */

+#define ADC_CCR_TSEN                      ADC_CCR_TSEN_Msk                      /*!< Temperature sensor enable */

+#define ADC_CCR_VBATEN_Pos                (24U)

+#define ADC_CCR_VBATEN_Msk                (0x1UL << ADC_CCR_VBATEN_Pos)         /*!< 0x01000000 */

+#define ADC_CCR_VBATEN                    ADC_CCR_VBATEN_Msk                    /*!< VBAT enable */

+

+/********************  Bit definition for ADC_CDR register  *******************/

+#define ADC_CDR_RDATA_MST_Pos             (0U)

+#define ADC_CDR_RDATA_MST_Msk             (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)   /*!< 0x0000FFFF */

+#define ADC_CDR_RDATA_MST                 ADC_CDR_RDATA_MST_Msk                 /*!< ADC multimode master group regular conversion data */

+

+#define ADC_CDR_RDATA_SLV_Pos             (16U)

+#define ADC_CDR_RDATA_SLV_Msk             (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)   /*!< 0xFFFF0000 */

+#define ADC_CDR_RDATA_SLV                 ADC_CDR_RDATA_SLV_Msk                 /*!< ADC multimode slave group regular conversion data */

+

+/********************  Bit definition for ADC_CDR2 register  ******************/

+#define ADC_CDR2_RDATA_ALT_Pos            (0U)

+#define ADC_CDR2_RDATA_ALT_Msk            (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */

+#define ADC_CDR2_RDATA_ALT                ADC_CDR2_RDATA_ALT_Msk                   /*!< Regular data of the master/slave alternated ADCs */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                   VREFBUF                                  */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for VREFBUF_CSR register  ****************/

+#define VREFBUF_CSR_ENVR_Pos        (0U)

+#define VREFBUF_CSR_ENVR_Msk        (0x1UL << VREFBUF_CSR_ENVR_Pos)            /*!< 0x00000001 */

+#define VREFBUF_CSR_ENVR            VREFBUF_CSR_ENVR_Msk                       /*!<Voltage reference buffer enable */

+#define VREFBUF_CSR_HIZ_Pos         (1U)

+#define VREFBUF_CSR_HIZ_Msk         (0x1UL << VREFBUF_CSR_HIZ_Pos)             /*!< 0x00000002 */

+#define VREFBUF_CSR_HIZ             VREFBUF_CSR_HIZ_Msk                        /*!<High impedance mode             */

+#define VREFBUF_CSR_VRR_Pos         (3U)

+#define VREFBUF_CSR_VRR_Msk         (0x1UL << VREFBUF_CSR_VRR_Pos)             /*!< 0x00000008 */

+#define VREFBUF_CSR_VRR             VREFBUF_CSR_VRR_Msk                        /*!<Voltage reference buffer ready  */

+#define VREFBUF_CSR_VRS_Pos         (4U)

+#define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */

+#define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */

+

+#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */

+#define VREFBUF_CSR_VRS_OUT2_Pos    (4U)

+#define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */

+#define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */

+#define VREFBUF_CSR_VRS_OUT3_Pos    (5U)

+#define VREFBUF_CSR_VRS_OUT3_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)        /*!< 0x00000020 */

+#define VREFBUF_CSR_VRS_OUT3        VREFBUF_CSR_VRS_OUT3_Msk                   /*!<Voltage reference VREF_OUT3     */

+#define VREFBUF_CSR_VRS_OUT4_Pos    (4U)

+#define VREFBUF_CSR_VRS_OUT4_Msk    (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)        /*!< 0x00000030 */

+#define VREFBUF_CSR_VRS_OUT4        VREFBUF_CSR_VRS_OUT4_Msk                   /*!<Voltage reference VREF_OUT4     */

+

+/*******************  Bit definition for VREFBUF_CCR register  ****************/

+#define VREFBUF_CCR_TRIM_Pos        (0U)

+#define VREFBUF_CCR_TRIM_Msk        (0x3FUL << VREFBUF_CCR_TRIM_Pos)           /*!< 0x0000003F */

+#define VREFBUF_CCR_TRIM            VREFBUF_CCR_TRIM_Msk                       /*!<TRIM[5:0] bits (Trimming code)  */

+

+/******************************************************************************/

+/*                                                                            */

+/*                 Flexible Datarate Controller Area Network                  */

+/*                                                                            */

+/******************************************************************************/

+/*!<FDCAN control and status registers */

+/*****************  Bit definition for FDCAN_CREL register  *******************/

+#define FDCAN_CREL_DAY_Pos        (0U)

+#define FDCAN_CREL_DAY_Msk        (0xFFUL << FDCAN_CREL_DAY_Pos)               /*!< 0x000000FF */

+#define FDCAN_CREL_DAY            FDCAN_CREL_DAY_Msk                           /*!<Timestamp Day                           */

+#define FDCAN_CREL_MON_Pos        (8U)

+#define FDCAN_CREL_MON_Msk        (0xFFUL << FDCAN_CREL_MON_Pos)               /*!< 0x0000FF00 */

+#define FDCAN_CREL_MON            FDCAN_CREL_MON_Msk                           /*!<Timestamp Month                         */

+#define FDCAN_CREL_YEAR_Pos       (16U)

+#define FDCAN_CREL_YEAR_Msk       (0xFUL << FDCAN_CREL_YEAR_Pos)               /*!< 0x000F0000 */

+#define FDCAN_CREL_YEAR           FDCAN_CREL_YEAR_Msk                          /*!<Timestamp Year                          */

+#define FDCAN_CREL_SUBSTEP_Pos    (20U)

+#define FDCAN_CREL_SUBSTEP_Msk    (0xFUL << FDCAN_CREL_SUBSTEP_Pos)            /*!< 0x00F00000 */

+#define FDCAN_CREL_SUBSTEP        FDCAN_CREL_SUBSTEP_Msk                       /*!<Sub-step of Core release                */

+#define FDCAN_CREL_STEP_Pos       (24U)

+#define FDCAN_CREL_STEP_Msk       (0xFUL << FDCAN_CREL_STEP_Pos)               /*!< 0x0F000000 */

+#define FDCAN_CREL_STEP           FDCAN_CREL_STEP_Msk                          /*!<Step of Core release                    */

+#define FDCAN_CREL_REL_Pos        (28U)

+#define FDCAN_CREL_REL_Msk        (0xFUL << FDCAN_CREL_REL_Pos)                /*!< 0xF0000000 */

+#define FDCAN_CREL_REL            FDCAN_CREL_REL_Msk                           /*!<Core release                            */

+

+/*****************  Bit definition for FDCAN_ENDN register  *******************/

+#define FDCAN_ENDN_ETV_Pos        (0U)

+#define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endiannes Test Value                    */

+

+/*****************  Bit definition for FDCAN_DBTP register  *******************/

+#define FDCAN_DBTP_DSJW_Pos       (0U)

+#define FDCAN_DBTP_DSJW_Msk       (0xFUL << FDCAN_DBTP_DSJW_Pos)               /*!< 0x0000000F */

+#define FDCAN_DBTP_DSJW           FDCAN_DBTP_DSJW_Msk                          /*!<Synchronization Jump Width              */

+#define FDCAN_DBTP_DTSEG2_Pos     (4U)

+#define FDCAN_DBTP_DTSEG2_Msk     (0xFUL << FDCAN_DBTP_DTSEG2_Pos)             /*!< 0x000000F0 */

+#define FDCAN_DBTP_DTSEG2         FDCAN_DBTP_DTSEG2_Msk                        /*!<Data time segment after sample point    */

+#define FDCAN_DBTP_DTSEG1_Pos     (8U)

+#define FDCAN_DBTP_DTSEG1_Msk     (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)            /*!< 0x00001F00 */

+#define FDCAN_DBTP_DTSEG1         FDCAN_DBTP_DTSEG1_Msk                        /*!<Data time segment before sample point   */

+#define FDCAN_DBTP_DBRP_Pos       (16U)

+#define FDCAN_DBTP_DBRP_Msk       (0x1FUL << FDCAN_DBTP_DBRP_Pos)              /*!< 0x001F0000 */

+#define FDCAN_DBTP_DBRP           FDCAN_DBTP_DBRP_Msk                          /*!<Data BIt Rate Prescaler                 */

+#define FDCAN_DBTP_TDC_Pos        (23U)

+#define FDCAN_DBTP_TDC_Msk        (0x1UL << FDCAN_DBTP_TDC_Pos)                /*!< 0x00800000 */

+#define FDCAN_DBTP_TDC            FDCAN_DBTP_TDC_Msk                           /*!<Transceiver Delay Compensation          */

+

+/*****************  Bit definition for FDCAN_TEST register  *******************/

+#define FDCAN_TEST_LBCK_Pos       (4U)

+#define FDCAN_TEST_LBCK_Msk       (0x1UL << FDCAN_TEST_LBCK_Pos)               /*!< 0x00000010 */

+#define FDCAN_TEST_LBCK           FDCAN_TEST_LBCK_Msk                          /*!<Loop Back mode                           */

+#define FDCAN_TEST_TX_Pos         (5U)

+#define FDCAN_TEST_TX_Msk         (0x3UL << FDCAN_TEST_TX_Pos)                 /*!< 0x00000060 */

+#define FDCAN_TEST_TX             FDCAN_TEST_TX_Msk                            /*!<Control of Transmit Pin                  */

+#define FDCAN_TEST_RX_Pos         (7U)

+#define FDCAN_TEST_RX_Msk         (0x1UL << FDCAN_TEST_RX_Pos)                 /*!< 0x00000080 */

+#define FDCAN_TEST_RX             FDCAN_TEST_RX_Msk                            /*!<Receive Pin                              */

+

+/*****************  Bit definition for FDCAN_RWD register  ********************/

+#define FDCAN_RWD_WDC_Pos         (0U)

+#define FDCAN_RWD_WDC_Msk         (0xFFUL << FDCAN_RWD_WDC_Pos)                /*!< 0x000000FF */

+#define FDCAN_RWD_WDC             FDCAN_RWD_WDC_Msk                            /*!<Watchdog configuration                   */

+#define FDCAN_RWD_WDV_Pos         (8U)

+#define FDCAN_RWD_WDV_Msk         (0xFFUL << FDCAN_RWD_WDV_Pos)                /*!< 0x0000FF00 */

+#define FDCAN_RWD_WDV             FDCAN_RWD_WDV_Msk                            /*!<Watchdog value                           */

+

+/*****************  Bit definition for FDCAN_CCCR register  ********************/

+#define FDCAN_CCCR_INIT_Pos       (0U)

+#define FDCAN_CCCR_INIT_Msk       (0x1UL << FDCAN_CCCR_INIT_Pos)               /*!< 0x00000001 */

+#define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!<Initialization                           */

+#define FDCAN_CCCR_CCE_Pos        (1U)

+#define FDCAN_CCCR_CCE_Msk        (0x1UL << FDCAN_CCCR_CCE_Pos)                /*!< 0x00000002 */

+#define FDCAN_CCCR_CCE            FDCAN_CCCR_CCE_Msk                           /*!<Configuration Change Enable              */

+#define FDCAN_CCCR_ASM_Pos        (2U)

+#define FDCAN_CCCR_ASM_Msk        (0x1UL << FDCAN_CCCR_ASM_Pos)                /*!< 0x00000004 */

+#define FDCAN_CCCR_ASM            FDCAN_CCCR_ASM_Msk                           /*!<ASM Restricted Operation Mode            */

+#define FDCAN_CCCR_CSA_Pos        (3U)

+#define FDCAN_CCCR_CSA_Msk        (0x1UL << FDCAN_CCCR_CSA_Pos)                /*!< 0x00000008 */

+#define FDCAN_CCCR_CSA            FDCAN_CCCR_CSA_Msk                           /*!<Clock Stop Acknowledge                   */

+#define FDCAN_CCCR_CSR_Pos        (4U)

+#define FDCAN_CCCR_CSR_Msk        (0x1UL << FDCAN_CCCR_CSR_Pos)                /*!< 0x00000010 */

+#define FDCAN_CCCR_CSR            FDCAN_CCCR_CSR_Msk                           /*!<Clock Stop Request                       */

+#define FDCAN_CCCR_MON_Pos        (5U)

+#define FDCAN_CCCR_MON_Msk        (0x1UL << FDCAN_CCCR_MON_Pos)                /*!< 0x00000020 */

+#define FDCAN_CCCR_MON            FDCAN_CCCR_MON_Msk                           /*!<Bus Monitoring Mode                      */

+#define FDCAN_CCCR_DAR_Pos        (6U)

+#define FDCAN_CCCR_DAR_Msk        (0x1UL << FDCAN_CCCR_DAR_Pos)                /*!< 0x00000040 */

+#define FDCAN_CCCR_DAR            FDCAN_CCCR_DAR_Msk                           /*!<Disable Automatic Retransmission         */

+#define FDCAN_CCCR_TEST_Pos       (7U)

+#define FDCAN_CCCR_TEST_Msk       (0x1UL << FDCAN_CCCR_TEST_Pos)               /*!< 0x00000080 */

+#define FDCAN_CCCR_TEST           FDCAN_CCCR_TEST_Msk                          /*!<Test Mode Enable                         */

+#define FDCAN_CCCR_FDOE_Pos       (8U)

+#define FDCAN_CCCR_FDOE_Msk       (0x1UL << FDCAN_CCCR_FDOE_Pos)               /*!< 0x00000100 */

+#define FDCAN_CCCR_FDOE           FDCAN_CCCR_FDOE_Msk                          /*!<FD Operation Enable                      */

+#define FDCAN_CCCR_BRSE_Pos       (9U)

+#define FDCAN_CCCR_BRSE_Msk       (0x1UL << FDCAN_CCCR_BRSE_Pos)               /*!< 0x00000200 */

+#define FDCAN_CCCR_BRSE           FDCAN_CCCR_BRSE_Msk                          /*!<FDCAN Bit Rate Switching                 */

+#define FDCAN_CCCR_PXHD_Pos       (12U)

+#define FDCAN_CCCR_PXHD_Msk       (0x1UL << FDCAN_CCCR_PXHD_Pos)               /*!< 0x00001000 */

+#define FDCAN_CCCR_PXHD           FDCAN_CCCR_PXHD_Msk                          /*!<Protocol Exception Handling Disable      */

+#define FDCAN_CCCR_EFBI_Pos       (13U)

+#define FDCAN_CCCR_EFBI_Msk       (0x1UL << FDCAN_CCCR_EFBI_Pos)               /*!< 0x00002000 */

+#define FDCAN_CCCR_EFBI           FDCAN_CCCR_EFBI_Msk                          /*!<Edge Filtering during Bus Integration    */

+#define FDCAN_CCCR_TXP_Pos        (14U)

+#define FDCAN_CCCR_TXP_Msk        (0x1UL << FDCAN_CCCR_TXP_Pos)                /*!< 0x00004000 */

+#define FDCAN_CCCR_TXP            FDCAN_CCCR_TXP_Msk                           /*!<Two CAN bit times Pause                  */

+#define FDCAN_CCCR_NISO_Pos       (15U)

+#define FDCAN_CCCR_NISO_Msk       (0x1UL << FDCAN_CCCR_NISO_Pos)               /*!< 0x00008000 */

+#define FDCAN_CCCR_NISO           FDCAN_CCCR_NISO_Msk                          /*!<Non ISO Operation                        */

+

+/*****************  Bit definition for FDCAN_NBTP register  ********************/

+#define FDCAN_NBTP_NTSEG2_Pos     (0U)

+#define FDCAN_NBTP_NTSEG2_Msk     (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)            /*!< 0x0000007F */

+#define FDCAN_NBTP_NTSEG2         FDCAN_NBTP_NTSEG2_Msk                        /*!<Nominal Time segment after sample point  */

+#define FDCAN_NBTP_NTSEG1_Pos     (8U)

+#define FDCAN_NBTP_NTSEG1_Msk     (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)            /*!< 0x0000FF00 */

+#define FDCAN_NBTP_NTSEG1         FDCAN_NBTP_NTSEG1_Msk                        /*!<Nominal Time segment before sample point */

+#define FDCAN_NBTP_NBRP_Pos       (16U)

+#define FDCAN_NBTP_NBRP_Msk       (0x1FFUL << FDCAN_NBTP_NBRP_Pos)             /*!< 0x01FF0000 */

+#define FDCAN_NBTP_NBRP           FDCAN_NBTP_NBRP_Msk                          /*!<Bit Rate Prescaler                       */

+#define FDCAN_NBTP_NSJW_Pos       (25U)

+#define FDCAN_NBTP_NSJW_Msk       (0x7FUL << FDCAN_NBTP_NSJW_Pos)              /*!< 0xFE000000 */

+#define FDCAN_NBTP_NSJW           FDCAN_NBTP_NSJW_Msk                          /*!<Nominal (Re)Synchronization Jump Width   */

+

+/*****************  Bit definition for FDCAN_TSCC register  ********************/

+#define FDCAN_TSCC_TSS_Pos        (0U)

+#define FDCAN_TSCC_TSS_Msk        (0x3UL << FDCAN_TSCC_TSS_Pos)                /*!< 0x00000003 */

+#define FDCAN_TSCC_TSS            FDCAN_TSCC_TSS_Msk                           /*!<Timestamp Select                         */

+#define FDCAN_TSCC_TCP_Pos        (16U)

+#define FDCAN_TSCC_TCP_Msk        (0xFUL << FDCAN_TSCC_TCP_Pos)                /*!< 0x000F0000 */

+#define FDCAN_TSCC_TCP            FDCAN_TSCC_TCP_Msk                           /*!<Timestamp Counter Prescaler              */

+

+/*****************  Bit definition for FDCAN_TSCV register  ********************/

+#define FDCAN_TSCV_TSC_Pos        (0U)

+#define FDCAN_TSCV_TSC_Msk        (0xFFFFUL << FDCAN_TSCV_TSC_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TSCV_TSC            FDCAN_TSCV_TSC_Msk                           /*!<Timestamp Counter                        */

+

+/*****************  Bit definition for FDCAN_TOCC register  ********************/

+#define FDCAN_TOCC_ETOC_Pos       (0U)

+#define FDCAN_TOCC_ETOC_Msk       (0x1UL << FDCAN_TOCC_ETOC_Pos)               /*!< 0x00000001 */

+#define FDCAN_TOCC_ETOC           FDCAN_TOCC_ETOC_Msk                          /*!<Enable Timeout Counter                   */

+#define FDCAN_TOCC_TOS_Pos        (1U)

+#define FDCAN_TOCC_TOS_Msk        (0x3UL << FDCAN_TOCC_TOS_Pos)                /*!< 0x00000006 */

+#define FDCAN_TOCC_TOS            FDCAN_TOCC_TOS_Msk                           /*!<Timeout Select                           */

+#define FDCAN_TOCC_TOP_Pos        (16U)

+#define FDCAN_TOCC_TOP_Msk        (0xFFFFUL << FDCAN_TOCC_TOP_Pos)             /*!< 0xFFFF0000 */

+#define FDCAN_TOCC_TOP            FDCAN_TOCC_TOP_Msk                           /*!<Timeout Period                           */

+

+/*****************  Bit definition for FDCAN_TOCV register  ********************/

+#define FDCAN_TOCV_TOC_Pos        (0U)

+#define FDCAN_TOCV_TOC_Msk        (0xFFFFUL << FDCAN_TOCV_TOC_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TOCV_TOC            FDCAN_TOCV_TOC_Msk                           /*!<Timeout Counter                          */

+

+/*****************  Bit definition for FDCAN_ECR register  *********************/

+#define FDCAN_ECR_TEC_Pos         (0U)

+#define FDCAN_ECR_TEC_Msk         (0xFUL << FDCAN_ECR_TEC_Pos)                 /*!< 0x0000000F */

+#define FDCAN_ECR_TEC             FDCAN_ECR_TEC_Msk                            /*!<Transmit Error Counter                   */

+#define FDCAN_ECR_REC_Pos         (8U)

+#define FDCAN_ECR_REC_Msk         (0x7FUL << FDCAN_ECR_REC_Pos)                /*!< 0x00007F00 */

+#define FDCAN_ECR_REC             FDCAN_ECR_REC_Msk                            /*!<Receive Error Counter                    */

+#define FDCAN_ECR_RP_Pos          (15U)

+#define FDCAN_ECR_RP_Msk          (0x1UL << FDCAN_ECR_RP_Pos)                  /*!< 0x00008000 */

+#define FDCAN_ECR_RP              FDCAN_ECR_RP_Msk                             /*!<Receive Error Passive                    */

+#define FDCAN_ECR_CEL_Pos         (16U)

+#define FDCAN_ECR_CEL_Msk         (0xFFUL << FDCAN_ECR_CEL_Pos)                /*!< 0x00FF0000 */

+#define FDCAN_ECR_CEL             FDCAN_ECR_CEL_Msk                            /*!<CAN Error Logging                        */

+

+/*****************  Bit definition for FDCAN_PSR register  *********************/

+#define FDCAN_PSR_LEC_Pos         (0U)

+#define FDCAN_PSR_LEC_Msk         (0x7UL << FDCAN_PSR_LEC_Pos)                 /*!< 0x00000007 */

+#define FDCAN_PSR_LEC             FDCAN_PSR_LEC_Msk                            /*!<Last Error Code                          */

+#define FDCAN_PSR_ACT_Pos         (3U)

+#define FDCAN_PSR_ACT_Msk         (0x3UL << FDCAN_PSR_ACT_Pos)                 /*!< 0x00000018 */

+#define FDCAN_PSR_ACT             FDCAN_PSR_ACT_Msk                            /*!<Activity                                 */

+#define FDCAN_PSR_EP_Pos          (5U)

+#define FDCAN_PSR_EP_Msk          (0x1UL << FDCAN_PSR_EP_Pos)                  /*!< 0x00000020 */

+#define FDCAN_PSR_EP              FDCAN_PSR_EP_Msk                             /*!<Error Passive                            */

+#define FDCAN_PSR_EW_Pos          (6U)

+#define FDCAN_PSR_EW_Msk          (0x1UL << FDCAN_PSR_EW_Pos)                  /*!< 0x00000040 */

+#define FDCAN_PSR_EW              FDCAN_PSR_EW_Msk                             /*!<Warning Status                           */

+#define FDCAN_PSR_BO_Pos          (7U)

+#define FDCAN_PSR_BO_Msk          (0x1UL << FDCAN_PSR_BO_Pos)                  /*!< 0x00000080 */

+#define FDCAN_PSR_BO              FDCAN_PSR_BO_Msk                             /*!<Bus_Off Status                           */

+#define FDCAN_PSR_DLEC_Pos        (8U)

+#define FDCAN_PSR_DLEC_Msk        (0x7UL << FDCAN_PSR_DLEC_Pos)                /*!< 0x00000700 */

+#define FDCAN_PSR_DLEC            FDCAN_PSR_DLEC_Msk                           /*!<Data Last Error Code                     */

+#define FDCAN_PSR_RESI_Pos        (11U)

+#define FDCAN_PSR_RESI_Msk        (0x1UL << FDCAN_PSR_RESI_Pos)                /*!< 0x00000800 */

+#define FDCAN_PSR_RESI            FDCAN_PSR_RESI_Msk                           /*!<ESI flag of last received FDCAN Message  */

+#define FDCAN_PSR_RBRS_Pos        (12U)

+#define FDCAN_PSR_RBRS_Msk        (0x1UL << FDCAN_PSR_RBRS_Pos)                /*!< 0x00001000 */

+#define FDCAN_PSR_RBRS            FDCAN_PSR_RBRS_Msk                           /*!<BRS flag of last received FDCAN Message  */

+#define FDCAN_PSR_REDL_Pos        (13U)

+#define FDCAN_PSR_REDL_Msk        (0x1UL << FDCAN_PSR_REDL_Pos)                /*!< 0x00002000 */

+#define FDCAN_PSR_REDL            FDCAN_PSR_REDL_Msk                           /*!<Received FDCAN Message                   */

+#define FDCAN_PSR_PXE_Pos         (14U)

+#define FDCAN_PSR_PXE_Msk         (0x1UL << FDCAN_PSR_PXE_Pos)                 /*!< 0x00004000 */

+#define FDCAN_PSR_PXE             FDCAN_PSR_PXE_Msk                            /*!<Protocol Exception Event                 */

+#define FDCAN_PSR_TDCV_Pos        (16U)

+#define FDCAN_PSR_TDCV_Msk        (0x7FUL << FDCAN_PSR_TDCV_Pos)               /*!< 0x007F0000 */

+#define FDCAN_PSR_TDCV            FDCAN_PSR_TDCV_Msk                           /*!<Transmitter Delay Compensation Value     */

+

+/*****************  Bit definition for FDCAN_TDCR register  ********************/

+#define FDCAN_TDCR_TDCF_Pos       (0U)

+#define FDCAN_TDCR_TDCF_Msk       (0x7FUL << FDCAN_TDCR_TDCF_Pos)              /*!< 0x0000007F */

+#define FDCAN_TDCR_TDCF           FDCAN_TDCR_TDCF_Msk                          /*!<Transmitter Delay Compensation Filter    */

+#define FDCAN_TDCR_TDCO_Pos       (8U)

+#define FDCAN_TDCR_TDCO_Msk       (0x7FUL << FDCAN_TDCR_TDCO_Pos)              /*!< 0x00007F00 */

+#define FDCAN_TDCR_TDCO           FDCAN_TDCR_TDCO_Msk                          /*!<Transmitter Delay Compensation Offset    */

+

+/*****************  Bit definition for FDCAN_IR register  **********************/

+#define FDCAN_IR_RF0N_Pos         (0U)

+#define FDCAN_IR_RF0N_Msk         (0x1UL << FDCAN_IR_RF0N_Pos)                 /*!< 0x00000001 */

+#define FDCAN_IR_RF0N             FDCAN_IR_RF0N_Msk                            /*!<Rx FIFO 0 New Message                    */

+#define FDCAN_IR_RF0W_Pos         (1U)

+#define FDCAN_IR_RF0W_Msk         (0x1UL << FDCAN_IR_RF0W_Pos)                 /*!< 0x00000002 */

+#define FDCAN_IR_RF0W             FDCAN_IR_RF0W_Msk                            /*!<Rx FIFO 0 Watermark Reached              */

+#define FDCAN_IR_RF0F_Pos         (2U)

+#define FDCAN_IR_RF0F_Msk         (0x1UL << FDCAN_IR_RF0F_Pos)                 /*!< 0x00000004 */

+#define FDCAN_IR_RF0F             FDCAN_IR_RF0F_Msk                            /*!<Rx FIFO 0 Full                           */

+#define FDCAN_IR_RF0L_Pos         (3U)

+#define FDCAN_IR_RF0L_Msk         (0x1UL << FDCAN_IR_RF0L_Pos)                 /*!< 0x00000008 */

+#define FDCAN_IR_RF0L             FDCAN_IR_RF0L_Msk                            /*!<Rx FIFO 0 Message Lost                   */

+#define FDCAN_IR_RF1N_Pos         (4U)

+#define FDCAN_IR_RF1N_Msk         (0x1UL << FDCAN_IR_RF1N_Pos)                 /*!< 0x00000010 */

+#define FDCAN_IR_RF1N             FDCAN_IR_RF1N_Msk                            /*!<Rx FIFO 1 New Message                    */

+#define FDCAN_IR_RF1W_Pos         (5U)

+#define FDCAN_IR_RF1W_Msk         (0x1UL << FDCAN_IR_RF1W_Pos)                 /*!< 0x00000020 */

+#define FDCAN_IR_RF1W             FDCAN_IR_RF1W_Msk                            /*!<Rx FIFO 1 Watermark Reached              */

+#define FDCAN_IR_RF1F_Pos         (6U)

+#define FDCAN_IR_RF1F_Msk         (0x1UL << FDCAN_IR_RF1F_Pos)                 /*!< 0x00000040 */

+#define FDCAN_IR_RF1F             FDCAN_IR_RF1F_Msk                            /*!<Rx FIFO 1 Full                           */

+#define FDCAN_IR_RF1L_Pos         (7U)

+#define FDCAN_IR_RF1L_Msk         (0x1UL << FDCAN_IR_RF1L_Pos)                 /*!< 0x00000080 */

+#define FDCAN_IR_RF1L             FDCAN_IR_RF1L_Msk                            /*!<Rx FIFO 1 Message Lost                   */

+#define FDCAN_IR_HPM_Pos          (8U)

+#define FDCAN_IR_HPM_Msk          (0x1UL << FDCAN_IR_HPM_Pos)                  /*!< 0x00000100 */

+#define FDCAN_IR_HPM              FDCAN_IR_HPM_Msk                             /*!<High Priority Message                    */

+#define FDCAN_IR_TC_Pos           (9U)

+#define FDCAN_IR_TC_Msk           (0x1UL << FDCAN_IR_TC_Pos)                   /*!< 0x00000200 */

+#define FDCAN_IR_TC               FDCAN_IR_TC_Msk                              /*!<Transmission Completed                   */

+#define FDCAN_IR_TCF_Pos          (10U)

+#define FDCAN_IR_TCF_Msk          (0x1UL << FDCAN_IR_TCF_Pos)                  /*!< 0x00000400 */

+#define FDCAN_IR_TCF              FDCAN_IR_TCF_Msk                             /*!<Transmission Cancellation Finished       */

+#define FDCAN_IR_TFE_Pos          (11U)

+#define FDCAN_IR_TFE_Msk          (0x1UL << FDCAN_IR_TFE_Pos)                  /*!< 0x00000800 */

+#define FDCAN_IR_TFE              FDCAN_IR_TFE_Msk                             /*!<Tx FIFO Empty                            */

+#define FDCAN_IR_TEFN_Pos         (12U)

+#define FDCAN_IR_TEFN_Msk         (0x1UL << FDCAN_IR_TEFN_Pos)                 /*!< 0x00001000 */

+#define FDCAN_IR_TEFN             FDCAN_IR_TEFN_Msk                            /*!<Tx Event FIFO New Entry                  */

+#define FDCAN_IR_TEFW_Pos         (13U)

+#define FDCAN_IR_TEFW_Msk         (0x1UL << FDCAN_IR_TEFW_Pos)                 /*!< 0x00002000 */

+#define FDCAN_IR_TEFW             FDCAN_IR_TEFW_Msk                            /*!<Tx Event FIFO Watermark Reached          */

+#define FDCAN_IR_TEFF_Pos         (14U)

+#define FDCAN_IR_TEFF_Msk         (0x1UL << FDCAN_IR_TEFF_Pos)                 /*!< 0x00004000 */

+#define FDCAN_IR_TEFF             FDCAN_IR_TEFF_Msk                            /*!<Tx Event FIFO Full                       */

+#define FDCAN_IR_TEFL_Pos         (15U)

+#define FDCAN_IR_TEFL_Msk         (0x1UL << FDCAN_IR_TEFL_Pos)                 /*!< 0x00008000 */

+#define FDCAN_IR_TEFL             FDCAN_IR_TEFL_Msk                            /*!<Tx Event FIFO Element Lost               */

+#define FDCAN_IR_TSW_Pos          (16U)

+#define FDCAN_IR_TSW_Msk          (0x1UL << FDCAN_IR_TSW_Pos)                  /*!< 0x00010000 */

+#define FDCAN_IR_TSW              FDCAN_IR_TSW_Msk                             /*!<Timestamp Wraparound                     */

+#define FDCAN_IR_MRAF_Pos         (17U)

+#define FDCAN_IR_MRAF_Msk         (0x1UL << FDCAN_IR_MRAF_Pos)                 /*!< 0x00020000 */

+#define FDCAN_IR_MRAF             FDCAN_IR_MRAF_Msk                            /*!<Message RAM Access Failure               */

+#define FDCAN_IR_TOO_Pos          (18U)

+#define FDCAN_IR_TOO_Msk          (0x1UL << FDCAN_IR_TOO_Pos)                  /*!< 0x00040000 */

+#define FDCAN_IR_TOO              FDCAN_IR_TOO_Msk                             /*!<Timeout Occurred                         */

+#define FDCAN_IR_DRX_Pos          (19U)

+#define FDCAN_IR_DRX_Msk          (0x1UL << FDCAN_IR_DRX_Pos)                  /*!< 0x00080000 */

+#define FDCAN_IR_DRX              FDCAN_IR_DRX_Msk                             /*!<Message stored to Dedicated Rx Buffer    */

+#define FDCAN_IR_ELO_Pos          (22U)

+#define FDCAN_IR_ELO_Msk          (0x1UL << FDCAN_IR_ELO_Pos)                  /*!< 0x00400000 */

+#define FDCAN_IR_ELO              FDCAN_IR_ELO_Msk                             /*!<Error Logging Overflow                   */

+#define FDCAN_IR_EP_Pos           (23U)

+#define FDCAN_IR_EP_Msk           (0x1UL << FDCAN_IR_EP_Pos)                   /*!< 0x00800000 */

+#define FDCAN_IR_EP               FDCAN_IR_EP_Msk                              /*!<Error Passive                            */

+#define FDCAN_IR_EW_Pos           (24U)

+#define FDCAN_IR_EW_Msk           (0x1UL << FDCAN_IR_EW_Pos)                   /*!< 0x01000000 */

+#define FDCAN_IR_EW               FDCAN_IR_EW_Msk                              /*!<Warning Status                           */

+#define FDCAN_IR_BO_Pos           (25U)

+#define FDCAN_IR_BO_Msk           (0x1UL << FDCAN_IR_BO_Pos)                   /*!< 0x02000000 */

+#define FDCAN_IR_BO               FDCAN_IR_BO_Msk                              /*!<Bus_Off Status                           */

+#define FDCAN_IR_WDI_Pos          (26U)

+#define FDCAN_IR_WDI_Msk          (0x1UL << FDCAN_IR_WDI_Pos)                  /*!< 0x04000000 */

+#define FDCAN_IR_WDI              FDCAN_IR_WDI_Msk                             /*!<Watchdog Interrupt                       */

+#define FDCAN_IR_PEA_Pos          (27U)

+#define FDCAN_IR_PEA_Msk          (0x1UL << FDCAN_IR_PEA_Pos)                  /*!< 0x08000000 */

+#define FDCAN_IR_PEA              FDCAN_IR_PEA_Msk                             /*!<Protocol Error in Arbitration Phase      */

+#define FDCAN_IR_PED_Pos          (28U)

+#define FDCAN_IR_PED_Msk          (0x1UL << FDCAN_IR_PED_Pos)                  /*!< 0x10000000 */

+#define FDCAN_IR_PED              FDCAN_IR_PED_Msk                             /*!<Protocol Error in Data Phase             */

+#define FDCAN_IR_ARA_Pos          (29U)

+#define FDCAN_IR_ARA_Msk          (0x1UL << FDCAN_IR_ARA_Pos)                  /*!< 0x20000000 */

+#define FDCAN_IR_ARA              FDCAN_IR_ARA_Msk                             /*!<Access to Reserved Address               */

+

+/*****************  Bit definition for FDCAN_IE register  **********************/

+#define FDCAN_IE_RF0NE_Pos        (0U)

+#define FDCAN_IE_RF0NE_Msk        (0x1UL << FDCAN_IE_RF0NE_Pos)                /*!< 0x00000001 */

+#define FDCAN_IE_RF0NE            FDCAN_IE_RF0NE_Msk                           /*!<Rx FIFO 0 New Message Enable                 */

+#define FDCAN_IE_RF0WE_Pos        (1U)

+#define FDCAN_IE_RF0WE_Msk        (0x1UL << FDCAN_IE_RF0WE_Pos)                /*!< 0x00000002 */

+#define FDCAN_IE_RF0WE            FDCAN_IE_RF0WE_Msk                           /*!<Rx FIFO 0 Watermark Reached Enable           */

+#define FDCAN_IE_RF0FE_Pos        (2U)

+#define FDCAN_IE_RF0FE_Msk        (0x1UL << FDCAN_IE_RF0FE_Pos)                /*!< 0x00000004 */

+#define FDCAN_IE_RF0FE            FDCAN_IE_RF0FE_Msk                           /*!<Rx FIFO 0 Full Enable                        */

+#define FDCAN_IE_RF0LE_Pos        (3U)

+#define FDCAN_IE_RF0LE_Msk        (0x1UL << FDCAN_IE_RF0LE_Pos)                /*!< 0x00000008 */

+#define FDCAN_IE_RF0LE            FDCAN_IE_RF0LE_Msk                           /*!<Rx FIFO 0 Message Lost Enable                */

+#define FDCAN_IE_RF1NE_Pos        (4U)

+#define FDCAN_IE_RF1NE_Msk        (0x1UL << FDCAN_IE_RF1NE_Pos)                /*!< 0x00000010 */

+#define FDCAN_IE_RF1NE            FDCAN_IE_RF1NE_Msk                           /*!<Rx FIFO 1 New Message Enable                 */

+#define FDCAN_IE_RF1WE_Pos        (5U)

+#define FDCAN_IE_RF1WE_Msk        (0x1UL << FDCAN_IE_RF1WE_Pos)                /*!< 0x00000020 */

+#define FDCAN_IE_RF1WE            FDCAN_IE_RF1WE_Msk                           /*!<Rx FIFO 1 Watermark Reached Enable           */

+#define FDCAN_IE_RF1FE_Pos        (6U)

+#define FDCAN_IE_RF1FE_Msk        (0x1UL << FDCAN_IE_RF1FE_Pos)                /*!< 0x00000040 */

+#define FDCAN_IE_RF1FE            FDCAN_IE_RF1FE_Msk                           /*!<Rx FIFO 1 Full Enable                        */

+#define FDCAN_IE_RF1LE_Pos        (7U)

+#define FDCAN_IE_RF1LE_Msk        (0x1UL << FDCAN_IE_RF1LE_Pos)                /*!< 0x00000080 */

+#define FDCAN_IE_RF1LE            FDCAN_IE_RF1LE_Msk                           /*!<Rx FIFO 1 Message Lost Enable                */

+#define FDCAN_IE_HPME_Pos         (8U)

+#define FDCAN_IE_HPME_Msk         (0x1UL << FDCAN_IE_HPME_Pos)                 /*!< 0x00000100 */

+#define FDCAN_IE_HPME             FDCAN_IE_HPME_Msk                            /*!<High Priority Message Enable                 */

+#define FDCAN_IE_TCE_Pos          (9U)

+#define FDCAN_IE_TCE_Msk          (0x1UL << FDCAN_IE_TCE_Pos)                  /*!< 0x00000200 */

+#define FDCAN_IE_TCE              FDCAN_IE_TCE_Msk                             /*!<Transmission Completed Enable                */

+#define FDCAN_IE_TCFE_Pos         (10U)

+#define FDCAN_IE_TCFE_Msk         (0x1UL << FDCAN_IE_TCFE_Pos)                 /*!< 0x00000400 */

+#define FDCAN_IE_TCFE             FDCAN_IE_TCFE_Msk                            /*!<Transmission Cancellation Finished Enable    */

+#define FDCAN_IE_TFEE_Pos         (11U)

+#define FDCAN_IE_TFEE_Msk         (0x1UL << FDCAN_IE_TFEE_Pos)                 /*!< 0x00000800 */

+#define FDCAN_IE_TFEE             FDCAN_IE_TFEE_Msk                            /*!<Tx FIFO Empty Enable                         */

+#define FDCAN_IE_TEFNE_Pos        (12U)

+#define FDCAN_IE_TEFNE_Msk        (0x1UL << FDCAN_IE_TEFNE_Pos)                /*!< 0x00001000 */

+#define FDCAN_IE_TEFNE            FDCAN_IE_TEFNE_Msk                           /*!<Tx Event FIFO New Entry Enable               */

+#define FDCAN_IE_TEFWE_Pos        (13U)

+#define FDCAN_IE_TEFWE_Msk        (0x1UL << FDCAN_IE_TEFWE_Pos)                /*!< 0x00002000 */

+#define FDCAN_IE_TEFWE            FDCAN_IE_TEFWE_Msk                           /*!<Tx Event FIFO Watermark Reached Enable       */

+#define FDCAN_IE_TEFFE_Pos        (14U)

+#define FDCAN_IE_TEFFE_Msk        (0x1UL << FDCAN_IE_TEFFE_Pos)                /*!< 0x00004000 */

+#define FDCAN_IE_TEFFE            FDCAN_IE_TEFFE_Msk                           /*!<Tx Event FIFO Full Enable                    */

+#define FDCAN_IE_TEFLE_Pos        (15U)

+#define FDCAN_IE_TEFLE_Msk        (0x1UL << FDCAN_IE_TEFLE_Pos)                /*!< 0x00008000 */

+#define FDCAN_IE_TEFLE            FDCAN_IE_TEFLE_Msk                           /*!<Tx Event FIFO Element Lost Enable            */

+#define FDCAN_IE_TSWE_Pos         (16U)

+#define FDCAN_IE_TSWE_Msk         (0x1UL << FDCAN_IE_TSWE_Pos)                 /*!< 0x00010000 */

+#define FDCAN_IE_TSWE             FDCAN_IE_TSWE_Msk                            /*!<Timestamp Wraparound Enable                  */

+#define FDCAN_IE_MRAFE_Pos        (17U)

+#define FDCAN_IE_MRAFE_Msk        (0x1UL << FDCAN_IE_MRAFE_Pos)                /*!< 0x00020000 */

+#define FDCAN_IE_MRAFE            FDCAN_IE_MRAFE_Msk                           /*!<Message RAM Access Failure Enable            */

+#define FDCAN_IE_TOOE_Pos         (18U)

+#define FDCAN_IE_TOOE_Msk         (0x1UL << FDCAN_IE_TOOE_Pos)                 /*!< 0x00040000 */

+#define FDCAN_IE_TOOE             FDCAN_IE_TOOE_Msk                            /*!<Timeout Occurred Enable                      */

+#define FDCAN_IE_DRXE_Pos         (19U)

+#define FDCAN_IE_DRXE_Msk         (0x1UL << FDCAN_IE_DRXE_Pos)                 /*!< 0x00080000 */

+#define FDCAN_IE_DRXE             FDCAN_IE_DRXE_Msk                            /*!<Message stored to Dedicated Rx Buffer Enable */

+#define FDCAN_IE_BECE_Pos         (20U)

+#define FDCAN_IE_BECE_Msk         (0x1UL << FDCAN_IE_BECE_Pos)                 /*!< 0x00100000 */

+#define FDCAN_IE_BECE             FDCAN_IE_BECE_Msk                            /*!<Bit Error Corrected Interrupt Enable         */

+#define FDCAN_IE_BEUE_Pos         (21U)

+#define FDCAN_IE_BEUE_Msk         (0x1UL << FDCAN_IE_BEUE_Pos)                 /*!< 0x00200000 */

+#define FDCAN_IE_BEUE             FDCAN_IE_BEUE_Msk                            /*!<Bit Error Uncorrected Interrupt Enable       */

+#define FDCAN_IE_ELOE_Pos         (22U)

+#define FDCAN_IE_ELOE_Msk         (0x1UL << FDCAN_IE_ELOE_Pos)                 /*!< 0x00400000 */

+#define FDCAN_IE_ELOE             FDCAN_IE_ELOE_Msk                            /*!<Error Logging Overflow Enable                */

+#define FDCAN_IE_EPE_Pos          (23U)

+#define FDCAN_IE_EPE_Msk          (0x1UL << FDCAN_IE_EPE_Pos)                  /*!< 0x00800000 */

+#define FDCAN_IE_EPE              FDCAN_IE_EPE_Msk                             /*!<Error Passive Enable                         */

+#define FDCAN_IE_EWE_Pos          (24U)

+#define FDCAN_IE_EWE_Msk          (0x1UL << FDCAN_IE_EWE_Pos)                  /*!< 0x01000000 */

+#define FDCAN_IE_EWE              FDCAN_IE_EWE_Msk                             /*!<Warning Status Enable                        */

+#define FDCAN_IE_BOE_Pos          (25U)

+#define FDCAN_IE_BOE_Msk          (0x1UL << FDCAN_IE_BOE_Pos)                  /*!< 0x02000000 */

+#define FDCAN_IE_BOE              FDCAN_IE_BOE_Msk                             /*!<Bus_Off Status Enable                        */

+#define FDCAN_IE_WDIE_Pos         (26U)

+#define FDCAN_IE_WDIE_Msk         (0x1UL << FDCAN_IE_WDIE_Pos)                 /*!< 0x04000000 */

+#define FDCAN_IE_WDIE             FDCAN_IE_WDIE_Msk                            /*!<Watchdog Interrupt Enable                    */

+#define FDCAN_IE_PEAE_Pos         (27U)

+#define FDCAN_IE_PEAE_Msk         (0x1UL << FDCAN_IE_PEAE_Pos)                 /*!< 0x08000000 */

+#define FDCAN_IE_PEAE             FDCAN_IE_PEAE_Msk                            /*!<Protocol Error in Arbitration Phase Enable   */

+#define FDCAN_IE_PEDE_Pos         (28U)

+#define FDCAN_IE_PEDE_Msk         (0x1UL << FDCAN_IE_PEDE_Pos)                 /*!< 0x10000000 */

+#define FDCAN_IE_PEDE             FDCAN_IE_PEDE_Msk                            /*!<Protocol Error in Data Phase Enable          */

+#define FDCAN_IE_ARAE_Pos         (29U)

+#define FDCAN_IE_ARAE_Msk         (0x1UL << FDCAN_IE_ARAE_Pos)                 /*!< 0x20000000 */

+#define FDCAN_IE_ARAE             FDCAN_IE_ARAE_Msk                            /*!<Access to Reserved Address Enable            */

+

+/*****************  Bit definition for FDCAN_ILS register  **********************/

+#define FDCAN_ILS_RF0NL_Pos       (0U)

+#define FDCAN_ILS_RF0NL_Msk       (0x1UL << FDCAN_ILS_RF0NL_Pos)               /*!< 0x00000001 */

+#define FDCAN_ILS_RF0NL           FDCAN_ILS_RF0NL_Msk                          /*!<Rx FIFO 0 New Message Line                  */

+#define FDCAN_ILS_RF0WL_Pos       (1U)

+#define FDCAN_ILS_RF0WL_Msk       (0x1UL << FDCAN_ILS_RF0WL_Pos)               /*!< 0x00000002 */

+#define FDCAN_ILS_RF0WL           FDCAN_ILS_RF0WL_Msk                          /*!<Rx FIFO 0 Watermark Reached Line            */

+#define FDCAN_ILS_RF0FL_Pos       (2U)

+#define FDCAN_ILS_RF0FL_Msk       (0x1UL << FDCAN_ILS_RF0FL_Pos)               /*!< 0x00000004 */

+#define FDCAN_ILS_RF0FL           FDCAN_ILS_RF0FL_Msk                          /*!<Rx FIFO 0 Full Line                         */

+#define FDCAN_ILS_RF0LL_Pos       (3U)

+#define FDCAN_ILS_RF0LL_Msk       (0x1UL << FDCAN_ILS_RF0LL_Pos)               /*!< 0x00000008 */

+#define FDCAN_ILS_RF0LL           FDCAN_ILS_RF0LL_Msk                          /*!<Rx FIFO 0 Message Lost Line                 */

+#define FDCAN_ILS_RF1NL_Pos       (4U)

+#define FDCAN_ILS_RF1NL_Msk       (0x1UL << FDCAN_ILS_RF1NL_Pos)               /*!< 0x00000010 */

+#define FDCAN_ILS_RF1NL           FDCAN_ILS_RF1NL_Msk                          /*!<Rx FIFO 1 New Message Line                  */

+#define FDCAN_ILS_RF1WL_Pos       (5U)

+#define FDCAN_ILS_RF1WL_Msk       (0x1UL << FDCAN_ILS_RF1WL_Pos)               /*!< 0x00000020 */

+#define FDCAN_ILS_RF1WL           FDCAN_ILS_RF1WL_Msk                          /*!<Rx FIFO 1 Watermark Reached Line            */

+#define FDCAN_ILS_RF1FL_Pos       (6U)

+#define FDCAN_ILS_RF1FL_Msk       (0x1UL << FDCAN_ILS_RF1FL_Pos)               /*!< 0x00000040 */

+#define FDCAN_ILS_RF1FL           FDCAN_ILS_RF1FL_Msk                          /*!<Rx FIFO 1 Full Line                         */

+#define FDCAN_ILS_RF1LL_Pos       (7U)

+#define FDCAN_ILS_RF1LL_Msk       (0x1UL << FDCAN_ILS_RF1LL_Pos)               /*!< 0x00000080 */

+#define FDCAN_ILS_RF1LL           FDCAN_ILS_RF1LL_Msk                          /*!<Rx FIFO 1 Message Lost Line                 */

+#define FDCAN_ILS_HPML_Pos        (8U)

+#define FDCAN_ILS_HPML_Msk        (0x1UL << FDCAN_ILS_HPML_Pos)                /*!< 0x00000100 */

+#define FDCAN_ILS_HPML            FDCAN_ILS_HPML_Msk                           /*!<High Priority Message Line                  */

+#define FDCAN_ILS_TCL_Pos         (9U)

+#define FDCAN_ILS_TCL_Msk         (0x1UL << FDCAN_ILS_TCL_Pos)                 /*!< 0x00000200 */

+#define FDCAN_ILS_TCL             FDCAN_ILS_TCL_Msk                            /*!<Transmission Completed Line                 */

+#define FDCAN_ILS_TCFL_Pos        (10U)

+#define FDCAN_ILS_TCFL_Msk        (0x1UL << FDCAN_ILS_TCFL_Pos)                /*!< 0x00000400 */

+#define FDCAN_ILS_TCFL            FDCAN_ILS_TCFL_Msk                           /*!<Transmission Cancellation Finished Line     */

+#define FDCAN_ILS_TFEL_Pos        (11U)

+#define FDCAN_ILS_TFEL_Msk        (0x1UL << FDCAN_ILS_TFEL_Pos)                /*!< 0x00000800 */

+#define FDCAN_ILS_TFEL            FDCAN_ILS_TFEL_Msk                           /*!<Tx FIFO Empty Line                          */

+#define FDCAN_ILS_TEFNL_Pos       (12U)

+#define FDCAN_ILS_TEFNL_Msk       (0x1UL << FDCAN_ILS_TEFNL_Pos)               /*!< 0x00001000 */

+#define FDCAN_ILS_TEFNL           FDCAN_ILS_TEFNL_Msk                          /*!<Tx Event FIFO New Entry Line                */

+#define FDCAN_ILS_TEFWL_Pos       (13U)

+#define FDCAN_ILS_TEFWL_Msk       (0x1UL << FDCAN_ILS_TEFWL_Pos)               /*!< 0x00002000 */

+#define FDCAN_ILS_TEFWL           FDCAN_ILS_TEFWL_Msk                          /*!<Tx Event FIFO Watermark Reached Line        */

+#define FDCAN_ILS_TEFFL_Pos       (14U)

+#define FDCAN_ILS_TEFFL_Msk       (0x1UL << FDCAN_ILS_TEFFL_Pos)               /*!< 0x00004000 */

+#define FDCAN_ILS_TEFFL           FDCAN_ILS_TEFFL_Msk                          /*!<Tx Event FIFO Full Line                     */

+#define FDCAN_ILS_TEFLL_Pos       (15U)

+#define FDCAN_ILS_TEFLL_Msk       (0x1UL << FDCAN_ILS_TEFLL_Pos)               /*!< 0x00008000 */

+#define FDCAN_ILS_TEFLL           FDCAN_ILS_TEFLL_Msk                          /*!<Tx Event FIFO Element Lost Line             */

+#define FDCAN_ILS_TSWL_Pos        (16U)

+#define FDCAN_ILS_TSWL_Msk        (0x1UL << FDCAN_ILS_TSWL_Pos)                /*!< 0x00010000 */

+#define FDCAN_ILS_TSWL            FDCAN_ILS_TSWL_Msk                           /*!<Timestamp Wraparound Line                   */

+#define FDCAN_ILS_MRAFE_Pos       (17U)

+#define FDCAN_ILS_MRAFE_Msk       (0x1UL << FDCAN_ILS_MRAFE_Pos)               /*!< 0x00020000 */

+#define FDCAN_ILS_MRAFE           FDCAN_ILS_MRAFE_Msk                          /*!<Message RAM Access Failure Line             */

+#define FDCAN_ILS_TOOE_Pos        (18U)

+#define FDCAN_ILS_TOOE_Msk        (0x1UL << FDCAN_ILS_TOOE_Pos)                /*!< 0x00040000 */

+#define FDCAN_ILS_TOOE            FDCAN_ILS_TOOE_Msk                           /*!<Timeout Occurred Line                       */

+#define FDCAN_ILS_DRXE_Pos        (19U)

+#define FDCAN_ILS_DRXE_Msk        (0x1UL << FDCAN_ILS_DRXE_Pos)                /*!< 0x00080000 */

+#define FDCAN_ILS_DRXE            FDCAN_ILS_DRXE_Msk                           /*!<Message stored to Dedicated Rx Buffer Line  */

+#define FDCAN_ILS_BECE_Pos        (20U)

+#define FDCAN_ILS_BECE_Msk        (0x1UL << FDCAN_ILS_BECE_Pos)                /*!< 0x00100000 */

+#define FDCAN_ILS_BECE            FDCAN_ILS_BECE_Msk                           /*!<Bit Error Corrected Interrupt Line          */

+#define FDCAN_ILS_BEUE_Pos        (21U)

+#define FDCAN_ILS_BEUE_Msk        (0x1UL << FDCAN_ILS_BEUE_Pos)                /*!< 0x00200000 */

+#define FDCAN_ILS_BEUE            FDCAN_ILS_BEUE_Msk                           /*!<Bit Error Uncorrected Interrupt Line        */

+#define FDCAN_ILS_ELOE_Pos        (22U)

+#define FDCAN_ILS_ELOE_Msk        (0x1UL << FDCAN_ILS_ELOE_Pos)                /*!< 0x00400000 */

+#define FDCAN_ILS_ELOE            FDCAN_ILS_ELOE_Msk                           /*!<Error Logging Overflow Line                 */

+#define FDCAN_ILS_EPE_Pos         (23U)

+#define FDCAN_ILS_EPE_Msk         (0x1UL << FDCAN_ILS_EPE_Pos)                 /*!< 0x00800000 */

+#define FDCAN_ILS_EPE             FDCAN_ILS_EPE_Msk                            /*!<Error Passive Line                          */

+#define FDCAN_ILS_EWE_Pos         (24U)

+#define FDCAN_ILS_EWE_Msk         (0x1UL << FDCAN_ILS_EWE_Pos)                 /*!< 0x01000000 */

+#define FDCAN_ILS_EWE             FDCAN_ILS_EWE_Msk                            /*!<Warning Status Line                         */

+#define FDCAN_ILS_BOE_Pos         (25U)

+#define FDCAN_ILS_BOE_Msk         (0x1UL << FDCAN_ILS_BOE_Pos)                 /*!< 0x02000000 */

+#define FDCAN_ILS_BOE             FDCAN_ILS_BOE_Msk                            /*!<Bus_Off Status Line                         */

+#define FDCAN_ILS_WDIE_Pos        (26U)

+#define FDCAN_ILS_WDIE_Msk        (0x1UL << FDCAN_ILS_WDIE_Pos)                /*!< 0x04000000 */

+#define FDCAN_ILS_WDIE            FDCAN_ILS_WDIE_Msk                           /*!<Watchdog Interrupt Line                     */

+#define FDCAN_ILS_PEAE_Pos        (27U)

+#define FDCAN_ILS_PEAE_Msk        (0x1UL << FDCAN_ILS_PEAE_Pos)                /*!< 0x08000000 */

+#define FDCAN_ILS_PEAE            FDCAN_ILS_PEAE_Msk                           /*!<Protocol Error in Arbitration Phase Line    */

+#define FDCAN_ILS_PEDE_Pos        (28U)

+#define FDCAN_ILS_PEDE_Msk        (0x1UL << FDCAN_ILS_PEDE_Pos)                /*!< 0x10000000 */

+#define FDCAN_ILS_PEDE            FDCAN_ILS_PEDE_Msk                           /*!<Protocol Error in Data Phase Line           */

+#define FDCAN_ILS_ARAE_Pos        (29U)

+#define FDCAN_ILS_ARAE_Msk        (0x1UL << FDCAN_ILS_ARAE_Pos)                /*!< 0x20000000 */

+#define FDCAN_ILS_ARAE            FDCAN_ILS_ARAE_Msk                           /*!<Access to Reserved Address Line             */

+

+/*****************  Bit definition for FDCAN_ILE register  **********************/

+#define FDCAN_ILE_EINT0_Pos       (0U)

+#define FDCAN_ILE_EINT0_Msk       (0x1UL << FDCAN_ILE_EINT0_Pos)               /*!< 0x00000001 */

+#define FDCAN_ILE_EINT0           FDCAN_ILE_EINT0_Msk                          /*!<Enable Interrupt Line 0                   */

+#define FDCAN_ILE_EINT1_Pos       (1U)

+#define FDCAN_ILE_EINT1_Msk       (0x1UL << FDCAN_ILE_EINT1_Pos)               /*!< 0x00000002 */

+#define FDCAN_ILE_EINT1           FDCAN_ILE_EINT1_Msk                          /*!<Enable Interrupt Line 1                   */

+

+/*****************  Bit definition for FDCAN_GFC register  **********************/

+#define FDCAN_GFC_RRFE_Pos        (0U)

+#define FDCAN_GFC_RRFE_Msk        (0x1UL << FDCAN_GFC_RRFE_Pos)                /*!< 0x00000001 */

+#define FDCAN_GFC_RRFE            FDCAN_GFC_RRFE_Msk                           /*!<Reject Remote Frames Extended             */

+#define FDCAN_GFC_RRFS_Pos        (1U)

+#define FDCAN_GFC_RRFS_Msk        (0x1UL << FDCAN_GFC_RRFS_Pos)                /*!< 0x00000002 */

+#define FDCAN_GFC_RRFS            FDCAN_GFC_RRFS_Msk                           /*!<Reject Remote Frames Standard             */

+#define FDCAN_GFC_ANFE_Pos        (2U)

+#define FDCAN_GFC_ANFE_Msk        (0x3UL << FDCAN_GFC_ANFE_Pos)                /*!< 0x0000000C */

+#define FDCAN_GFC_ANFE            FDCAN_GFC_ANFE_Msk                           /*!<Accept Non-matching Frames Extended       */

+#define FDCAN_GFC_ANFS_Pos        (4U)

+#define FDCAN_GFC_ANFS_Msk        (0x3UL << FDCAN_GFC_ANFS_Pos)                /*!< 0x00000030 */

+#define FDCAN_GFC_ANFS            FDCAN_GFC_ANFS_Msk                           /*!<Accept Non-matching Frames Standard       */

+

+/*****************  Bit definition for FDCAN_SIDFC register  ********************/

+#define FDCAN_SIDFC_FLSSA_Pos     (2U)

+#define FDCAN_SIDFC_FLSSA_Msk     (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)          /*!< 0x0000FFFC */

+#define FDCAN_SIDFC_FLSSA         FDCAN_SIDFC_FLSSA_Msk                        /*!<Filter List Standard Start Address        */

+#define FDCAN_SIDFC_LSS_Pos       (16U)

+#define FDCAN_SIDFC_LSS_Msk       (0xFFUL << FDCAN_SIDFC_LSS_Pos)              /*!< 0x00FF0000 */

+#define FDCAN_SIDFC_LSS           FDCAN_SIDFC_LSS_Msk                          /*!<List Size Standard                        */

+

+/*****************  Bit definition for FDCAN_XIDFC register  ********************/

+#define FDCAN_XIDFC_FLESA_Pos     (2U)

+#define FDCAN_XIDFC_FLESA_Msk     (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)          /*!< 0x0000FFFC */

+#define FDCAN_XIDFC_FLESA         FDCAN_XIDFC_FLESA_Msk                        /*!<Filter List Standard Start Address        */

+#define FDCAN_XIDFC_LSE_Pos       (16U)

+#define FDCAN_XIDFC_LSE_Msk       (0x7FUL << FDCAN_XIDFC_LSE_Pos)              /*!< 0x007F0000 */

+#define FDCAN_XIDFC_LSE           FDCAN_XIDFC_LSE_Msk                          /*!<List Size Extended                        */

+

+/*****************  Bit definition for FDCAN_XIDAM register  ********************/

+#define FDCAN_XIDAM_EIDM_Pos      (0U)

+#define FDCAN_XIDAM_EIDM_Msk      (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)       /*!< 0x1FFFFFFF */

+#define FDCAN_XIDAM_EIDM          FDCAN_XIDAM_EIDM_Msk                         /*!<Extended ID Mask                          */

+

+/*****************  Bit definition for FDCAN_HPMS register  *********************/

+#define FDCAN_HPMS_BIDX_Pos       (0U)

+#define FDCAN_HPMS_BIDX_Msk       (0x3FUL << FDCAN_HPMS_BIDX_Pos)              /*!< 0x0000003F */

+#define FDCAN_HPMS_BIDX           FDCAN_HPMS_BIDX_Msk                          /*!<Buffer Index                              */

+#define FDCAN_HPMS_MSI_Pos        (6U)

+#define FDCAN_HPMS_MSI_Msk        (0x3UL << FDCAN_HPMS_MSI_Pos)                /*!< 0x000000C0 */

+#define FDCAN_HPMS_MSI            FDCAN_HPMS_MSI_Msk                           /*!<Message Storage Indicator                 */

+#define FDCAN_HPMS_FIDX_Pos       (8U)

+#define FDCAN_HPMS_FIDX_Msk       (0x7FUL << FDCAN_HPMS_FIDX_Pos)              /*!< 0x00007F00 */

+#define FDCAN_HPMS_FIDX           FDCAN_HPMS_FIDX_Msk                          /*!<Filter Index                              */

+#define FDCAN_HPMS_FLST_Pos       (15U)

+#define FDCAN_HPMS_FLST_Msk       (0x1UL << FDCAN_HPMS_FLST_Pos)               /*!< 0x00008000 */

+#define FDCAN_HPMS_FLST           FDCAN_HPMS_FLST_Msk                          /*!<Filter List                               */

+

+/*****************  Bit definition for FDCAN_NDAT1 register  ********************/

+#define FDCAN_NDAT1_ND0_Pos       (0U)

+#define FDCAN_NDAT1_ND0_Msk       (0x1UL << FDCAN_NDAT1_ND0_Pos)               /*!< 0x00000001 */

+#define FDCAN_NDAT1_ND0           FDCAN_NDAT1_ND0_Msk                          /*!<New Data flag of Rx Buffer 0              */

+#define FDCAN_NDAT1_ND1_Pos       (1U)

+#define FDCAN_NDAT1_ND1_Msk       (0x1UL << FDCAN_NDAT1_ND1_Pos)               /*!< 0x00000002 */

+#define FDCAN_NDAT1_ND1           FDCAN_NDAT1_ND1_Msk                          /*!<New Data flag of Rx Buffer 1              */

+#define FDCAN_NDAT1_ND2_Pos       (2U)

+#define FDCAN_NDAT1_ND2_Msk       (0x1UL << FDCAN_NDAT1_ND2_Pos)               /*!< 0x00000004 */

+#define FDCAN_NDAT1_ND2           FDCAN_NDAT1_ND2_Msk                          /*!<New Data flag of Rx Buffer 2              */

+#define FDCAN_NDAT1_ND3_Pos       (3U)

+#define FDCAN_NDAT1_ND3_Msk       (0x1UL << FDCAN_NDAT1_ND3_Pos)               /*!< 0x00000008 */

+#define FDCAN_NDAT1_ND3           FDCAN_NDAT1_ND3_Msk                          /*!<New Data flag of Rx Buffer 3              */

+#define FDCAN_NDAT1_ND4_Pos       (4U)

+#define FDCAN_NDAT1_ND4_Msk       (0x1UL << FDCAN_NDAT1_ND4_Pos)               /*!< 0x00000010 */

+#define FDCAN_NDAT1_ND4           FDCAN_NDAT1_ND4_Msk                          /*!<New Data flag of Rx Buffer 4              */

+#define FDCAN_NDAT1_ND5_Pos       (5U)

+#define FDCAN_NDAT1_ND5_Msk       (0x1UL << FDCAN_NDAT1_ND5_Pos)               /*!< 0x00000020 */

+#define FDCAN_NDAT1_ND5           FDCAN_NDAT1_ND5_Msk                          /*!<New Data flag of Rx Buffer 5              */

+#define FDCAN_NDAT1_ND6_Pos       (6U)

+#define FDCAN_NDAT1_ND6_Msk       (0x1UL << FDCAN_NDAT1_ND6_Pos)               /*!< 0x00000040 */

+#define FDCAN_NDAT1_ND6           FDCAN_NDAT1_ND6_Msk                          /*!<New Data flag of Rx Buffer 6              */

+#define FDCAN_NDAT1_ND7_Pos       (7U)

+#define FDCAN_NDAT1_ND7_Msk       (0x1UL << FDCAN_NDAT1_ND7_Pos)               /*!< 0x00000080 */

+#define FDCAN_NDAT1_ND7           FDCAN_NDAT1_ND7_Msk                          /*!<New Data flag of Rx Buffer 7              */

+#define FDCAN_NDAT1_ND8_Pos       (8U)

+#define FDCAN_NDAT1_ND8_Msk       (0x1UL << FDCAN_NDAT1_ND8_Pos)               /*!< 0x00000100 */

+#define FDCAN_NDAT1_ND8           FDCAN_NDAT1_ND8_Msk                          /*!<New Data flag of Rx Buffer 8              */

+#define FDCAN_NDAT1_ND9_Pos       (9U)

+#define FDCAN_NDAT1_ND9_Msk       (0x1UL << FDCAN_NDAT1_ND9_Pos)               /*!< 0x00000200 */

+#define FDCAN_NDAT1_ND9           FDCAN_NDAT1_ND9_Msk                          /*!<New Data flag of Rx Buffer 9              */

+#define FDCAN_NDAT1_ND10_Pos      (10U)

+#define FDCAN_NDAT1_ND10_Msk      (0x1UL << FDCAN_NDAT1_ND10_Pos)              /*!< 0x00000400 */

+#define FDCAN_NDAT1_ND10          FDCAN_NDAT1_ND10_Msk                         /*!<New Data flag of Rx Buffer 10             */

+#define FDCAN_NDAT1_ND11_Pos      (11U)

+#define FDCAN_NDAT1_ND11_Msk      (0x1UL << FDCAN_NDAT1_ND11_Pos)              /*!< 0x00000800 */

+#define FDCAN_NDAT1_ND11          FDCAN_NDAT1_ND11_Msk                         /*!<New Data flag of Rx Buffer 11             */

+#define FDCAN_NDAT1_ND12_Pos      (12U)

+#define FDCAN_NDAT1_ND12_Msk      (0x1UL << FDCAN_NDAT1_ND12_Pos)              /*!< 0x00001000 */

+#define FDCAN_NDAT1_ND12          FDCAN_NDAT1_ND12_Msk                         /*!<New Data flag of Rx Buffer 12             */

+#define FDCAN_NDAT1_ND13_Pos      (13U)

+#define FDCAN_NDAT1_ND13_Msk      (0x1UL << FDCAN_NDAT1_ND13_Pos)              /*!< 0x00002000 */

+#define FDCAN_NDAT1_ND13          FDCAN_NDAT1_ND13_Msk                         /*!<New Data flag of Rx Buffer 13             */

+#define FDCAN_NDAT1_ND14_Pos      (14U)

+#define FDCAN_NDAT1_ND14_Msk      (0x1UL << FDCAN_NDAT1_ND14_Pos)              /*!< 0x00004000 */

+#define FDCAN_NDAT1_ND14          FDCAN_NDAT1_ND14_Msk                         /*!<New Data flag of Rx Buffer 14             */

+#define FDCAN_NDAT1_ND15_Pos      (15U)

+#define FDCAN_NDAT1_ND15_Msk      (0x1UL << FDCAN_NDAT1_ND15_Pos)              /*!< 0x00008000 */

+#define FDCAN_NDAT1_ND15          FDCAN_NDAT1_ND15_Msk                         /*!<New Data flag of Rx Buffer 15             */

+#define FDCAN_NDAT1_ND16_Pos      (16U)

+#define FDCAN_NDAT1_ND16_Msk      (0x1UL << FDCAN_NDAT1_ND16_Pos)              /*!< 0x00010000 */

+#define FDCAN_NDAT1_ND16          FDCAN_NDAT1_ND16_Msk                         /*!<New Data flag of Rx Buffer 16             */

+#define FDCAN_NDAT1_ND17_Pos      (17U)

+#define FDCAN_NDAT1_ND17_Msk      (0x1UL << FDCAN_NDAT1_ND17_Pos)              /*!< 0x00020000 */

+#define FDCAN_NDAT1_ND17          FDCAN_NDAT1_ND17_Msk                         /*!<New Data flag of Rx Buffer 17             */

+#define FDCAN_NDAT1_ND18_Pos      (18U)

+#define FDCAN_NDAT1_ND18_Msk      (0x1UL << FDCAN_NDAT1_ND18_Pos)              /*!< 0x00040000 */

+#define FDCAN_NDAT1_ND18          FDCAN_NDAT1_ND18_Msk                         /*!<New Data flag of Rx Buffer 18             */

+#define FDCAN_NDAT1_ND19_Pos      (19U)

+#define FDCAN_NDAT1_ND19_Msk      (0x1UL << FDCAN_NDAT1_ND19_Pos)              /*!< 0x00080000 */

+#define FDCAN_NDAT1_ND19          FDCAN_NDAT1_ND19_Msk                         /*!<New Data flag of Rx Buffer 19             */

+#define FDCAN_NDAT1_ND20_Pos      (20U)

+#define FDCAN_NDAT1_ND20_Msk      (0x1UL << FDCAN_NDAT1_ND20_Pos)              /*!< 0x00100000 */

+#define FDCAN_NDAT1_ND20          FDCAN_NDAT1_ND20_Msk                         /*!<New Data flag of Rx Buffer 20             */

+#define FDCAN_NDAT1_ND21_Pos      (21U)

+#define FDCAN_NDAT1_ND21_Msk      (0x1UL << FDCAN_NDAT1_ND21_Pos)              /*!< 0x00200000 */

+#define FDCAN_NDAT1_ND21          FDCAN_NDAT1_ND21_Msk                         /*!<New Data flag of Rx Buffer 21             */

+#define FDCAN_NDAT1_ND22_Pos      (22U)

+#define FDCAN_NDAT1_ND22_Msk      (0x1UL << FDCAN_NDAT1_ND22_Pos)              /*!< 0x00400000 */

+#define FDCAN_NDAT1_ND22          FDCAN_NDAT1_ND22_Msk                         /*!<New Data flag of Rx Buffer 22             */

+#define FDCAN_NDAT1_ND23_Pos      (23U)

+#define FDCAN_NDAT1_ND23_Msk      (0x1UL << FDCAN_NDAT1_ND23_Pos)              /*!< 0x00800000 */

+#define FDCAN_NDAT1_ND23          FDCAN_NDAT1_ND23_Msk                         /*!<New Data flag of Rx Buffer 23             */

+#define FDCAN_NDAT1_ND24_Pos      (24U)

+#define FDCAN_NDAT1_ND24_Msk      (0x1UL << FDCAN_NDAT1_ND24_Pos)              /*!< 0x01000000 */

+#define FDCAN_NDAT1_ND24          FDCAN_NDAT1_ND24_Msk                         /*!<New Data flag of Rx Buffer 24             */

+#define FDCAN_NDAT1_ND25_Pos      (25U)

+#define FDCAN_NDAT1_ND25_Msk      (0x1UL << FDCAN_NDAT1_ND25_Pos)              /*!< 0x02000000 */

+#define FDCAN_NDAT1_ND25          FDCAN_NDAT1_ND25_Msk                         /*!<New Data flag of Rx Buffer 25             */

+#define FDCAN_NDAT1_ND26_Pos      (26U)

+#define FDCAN_NDAT1_ND26_Msk      (0x1UL << FDCAN_NDAT1_ND26_Pos)              /*!< 0x04000000 */

+#define FDCAN_NDAT1_ND26          FDCAN_NDAT1_ND26_Msk                         /*!<New Data flag of Rx Buffer 26             */

+#define FDCAN_NDAT1_ND27_Pos      (27U)

+#define FDCAN_NDAT1_ND27_Msk      (0x1UL << FDCAN_NDAT1_ND27_Pos)              /*!< 0x08000000 */

+#define FDCAN_NDAT1_ND27          FDCAN_NDAT1_ND27_Msk                         /*!<New Data flag of Rx Buffer 27             */

+#define FDCAN_NDAT1_ND28_Pos      (28U)

+#define FDCAN_NDAT1_ND28_Msk      (0x1UL << FDCAN_NDAT1_ND28_Pos)              /*!< 0x10000000 */

+#define FDCAN_NDAT1_ND28          FDCAN_NDAT1_ND28_Msk                         /*!<New Data flag of Rx Buffer 28             */

+#define FDCAN_NDAT1_ND29_Pos      (29U)

+#define FDCAN_NDAT1_ND29_Msk      (0x1UL << FDCAN_NDAT1_ND29_Pos)              /*!< 0x20000000 */

+#define FDCAN_NDAT1_ND29          FDCAN_NDAT1_ND29_Msk                         /*!<New Data flag of Rx Buffer 29             */

+#define FDCAN_NDAT1_ND30_Pos      (30U)

+#define FDCAN_NDAT1_ND30_Msk      (0x1UL << FDCAN_NDAT1_ND30_Pos)              /*!< 0x40000000 */

+#define FDCAN_NDAT1_ND30          FDCAN_NDAT1_ND30_Msk                         /*!<New Data flag of Rx Buffer 30             */

+#define FDCAN_NDAT1_ND31_Pos      (31U)

+#define FDCAN_NDAT1_ND31_Msk      (0x1UL << FDCAN_NDAT1_ND31_Pos)              /*!< 0x80000000 */

+#define FDCAN_NDAT1_ND31          FDCAN_NDAT1_ND31_Msk                         /*!<New Data flag of Rx Buffer 31             */

+

+/*****************  Bit definition for FDCAN_NDAT2 register  ********************/

+#define FDCAN_NDAT2_ND32_Pos      (0U)

+#define FDCAN_NDAT2_ND32_Msk      (0x1UL << FDCAN_NDAT2_ND32_Pos)              /*!< 0x00000001 */

+#define FDCAN_NDAT2_ND32          FDCAN_NDAT2_ND32_Msk                         /*!<New Data flag of Rx Buffer 32             */

+#define FDCAN_NDAT2_ND33_Pos      (1U)

+#define FDCAN_NDAT2_ND33_Msk      (0x1UL << FDCAN_NDAT2_ND33_Pos)              /*!< 0x00000002 */

+#define FDCAN_NDAT2_ND33          FDCAN_NDAT2_ND33_Msk                         /*!<New Data flag of Rx Buffer 33             */

+#define FDCAN_NDAT2_ND34_Pos      (2U)

+#define FDCAN_NDAT2_ND34_Msk      (0x1UL << FDCAN_NDAT2_ND34_Pos)              /*!< 0x00000004 */

+#define FDCAN_NDAT2_ND34          FDCAN_NDAT2_ND34_Msk                         /*!<New Data flag of Rx Buffer 34             */

+#define FDCAN_NDAT2_ND35_Pos      (3U)

+#define FDCAN_NDAT2_ND35_Msk      (0x1UL << FDCAN_NDAT2_ND35_Pos)              /*!< 0x00000008 */

+#define FDCAN_NDAT2_ND35          FDCAN_NDAT2_ND35_Msk                         /*!<New Data flag of Rx Buffer 35             */

+#define FDCAN_NDAT2_ND36_Pos      (4U)

+#define FDCAN_NDAT2_ND36_Msk      (0x1UL << FDCAN_NDAT2_ND36_Pos)              /*!< 0x00000010 */

+#define FDCAN_NDAT2_ND36          FDCAN_NDAT2_ND36_Msk                         /*!<New Data flag of Rx Buffer 36             */

+#define FDCAN_NDAT2_ND37_Pos      (5U)

+#define FDCAN_NDAT2_ND37_Msk      (0x1UL << FDCAN_NDAT2_ND37_Pos)              /*!< 0x00000020 */

+#define FDCAN_NDAT2_ND37          FDCAN_NDAT2_ND37_Msk                         /*!<New Data flag of Rx Buffer 37             */

+#define FDCAN_NDAT2_ND38_Pos      (6U)

+#define FDCAN_NDAT2_ND38_Msk      (0x1UL << FDCAN_NDAT2_ND38_Pos)              /*!< 0x00000040 */

+#define FDCAN_NDAT2_ND38          FDCAN_NDAT2_ND38_Msk                         /*!<New Data flag of Rx Buffer 38             */

+#define FDCAN_NDAT2_ND39_Pos      (7U)

+#define FDCAN_NDAT2_ND39_Msk      (0x1UL << FDCAN_NDAT2_ND39_Pos)              /*!< 0x00000080 */

+#define FDCAN_NDAT2_ND39          FDCAN_NDAT2_ND39_Msk                         /*!<New Data flag of Rx Buffer 39             */

+#define FDCAN_NDAT2_ND40_Pos      (8U)

+#define FDCAN_NDAT2_ND40_Msk      (0x1UL << FDCAN_NDAT2_ND40_Pos)              /*!< 0x00000100 */

+#define FDCAN_NDAT2_ND40          FDCAN_NDAT2_ND40_Msk                         /*!<New Data flag of Rx Buffer 40             */

+#define FDCAN_NDAT2_ND41_Pos      (9U)

+#define FDCAN_NDAT2_ND41_Msk      (0x1UL << FDCAN_NDAT2_ND41_Pos)              /*!< 0x00000200 */

+#define FDCAN_NDAT2_ND41          FDCAN_NDAT2_ND41_Msk                         /*!<New Data flag of Rx Buffer 41             */

+#define FDCAN_NDAT2_ND42_Pos      (10U)

+#define FDCAN_NDAT2_ND42_Msk      (0x1UL << FDCAN_NDAT2_ND42_Pos)              /*!< 0x00000400 */

+#define FDCAN_NDAT2_ND42          FDCAN_NDAT2_ND42_Msk                         /*!<New Data flag of Rx Buffer 42             */

+#define FDCAN_NDAT2_ND43_Pos      (11U)

+#define FDCAN_NDAT2_ND43_Msk      (0x1UL << FDCAN_NDAT2_ND43_Pos)              /*!< 0x00000800 */

+#define FDCAN_NDAT2_ND43          FDCAN_NDAT2_ND43_Msk                         /*!<New Data flag of Rx Buffer 43             */

+#define FDCAN_NDAT2_ND44_Pos      (12U)

+#define FDCAN_NDAT2_ND44_Msk      (0x1UL << FDCAN_NDAT2_ND44_Pos)              /*!< 0x00001000 */

+#define FDCAN_NDAT2_ND44          FDCAN_NDAT2_ND44_Msk                         /*!<New Data flag of Rx Buffer 44             */

+#define FDCAN_NDAT2_ND45_Pos      (13U)

+#define FDCAN_NDAT2_ND45_Msk      (0x1UL << FDCAN_NDAT2_ND45_Pos)              /*!< 0x00002000 */

+#define FDCAN_NDAT2_ND45          FDCAN_NDAT2_ND45_Msk                         /*!<New Data flag of Rx Buffer 45             */

+#define FDCAN_NDAT2_ND46_Pos      (14U)

+#define FDCAN_NDAT2_ND46_Msk      (0x1UL << FDCAN_NDAT2_ND46_Pos)              /*!< 0x00004000 */

+#define FDCAN_NDAT2_ND46          FDCAN_NDAT2_ND46_Msk                         /*!<New Data flag of Rx Buffer 46             */

+#define FDCAN_NDAT2_ND47_Pos      (15U)

+#define FDCAN_NDAT2_ND47_Msk      (0x1UL << FDCAN_NDAT2_ND47_Pos)              /*!< 0x00008000 */

+#define FDCAN_NDAT2_ND47          FDCAN_NDAT2_ND47_Msk                         /*!<New Data flag of Rx Buffer 47             */

+#define FDCAN_NDAT2_ND48_Pos      (16U)

+#define FDCAN_NDAT2_ND48_Msk      (0x1UL << FDCAN_NDAT2_ND48_Pos)              /*!< 0x00010000 */

+#define FDCAN_NDAT2_ND48          FDCAN_NDAT2_ND48_Msk                         /*!<New Data flag of Rx Buffer 48             */

+#define FDCAN_NDAT2_ND49_Pos      (17U)

+#define FDCAN_NDAT2_ND49_Msk      (0x1UL << FDCAN_NDAT2_ND49_Pos)              /*!< 0x00020000 */

+#define FDCAN_NDAT2_ND49          FDCAN_NDAT2_ND49_Msk                         /*!<New Data flag of Rx Buffer 49             */

+#define FDCAN_NDAT2_ND50_Pos      (18U)

+#define FDCAN_NDAT2_ND50_Msk      (0x1UL << FDCAN_NDAT2_ND50_Pos)              /*!< 0x00040000 */

+#define FDCAN_NDAT2_ND50          FDCAN_NDAT2_ND50_Msk                         /*!<New Data flag of Rx Buffer 50             */

+#define FDCAN_NDAT2_ND51_Pos      (19U)

+#define FDCAN_NDAT2_ND51_Msk      (0x1UL << FDCAN_NDAT2_ND51_Pos)              /*!< 0x00080000 */

+#define FDCAN_NDAT2_ND51          FDCAN_NDAT2_ND51_Msk                         /*!<New Data flag of Rx Buffer 51             */

+#define FDCAN_NDAT2_ND52_Pos      (20U)

+#define FDCAN_NDAT2_ND52_Msk      (0x1UL << FDCAN_NDAT2_ND52_Pos)              /*!< 0x00100000 */

+#define FDCAN_NDAT2_ND52          FDCAN_NDAT2_ND52_Msk                         /*!<New Data flag of Rx Buffer 52             */

+#define FDCAN_NDAT2_ND53_Pos      (21U)

+#define FDCAN_NDAT2_ND53_Msk      (0x1UL << FDCAN_NDAT2_ND53_Pos)              /*!< 0x00200000 */

+#define FDCAN_NDAT2_ND53          FDCAN_NDAT2_ND53_Msk                         /*!<New Data flag of Rx Buffer 53             */

+#define FDCAN_NDAT2_ND54_Pos      (22U)

+#define FDCAN_NDAT2_ND54_Msk      (0x1UL << FDCAN_NDAT2_ND54_Pos)              /*!< 0x00400000 */

+#define FDCAN_NDAT2_ND54          FDCAN_NDAT2_ND54_Msk                         /*!<New Data flag of Rx Buffer 54             */

+#define FDCAN_NDAT2_ND55_Pos      (23U)

+#define FDCAN_NDAT2_ND55_Msk      (0x1UL << FDCAN_NDAT2_ND55_Pos)              /*!< 0x00800000 */

+#define FDCAN_NDAT2_ND55          FDCAN_NDAT2_ND55_Msk                         /*!<New Data flag of Rx Buffer 55             */

+#define FDCAN_NDAT2_ND56_Pos      (24U)

+#define FDCAN_NDAT2_ND56_Msk      (0x1UL << FDCAN_NDAT2_ND56_Pos)              /*!< 0x01000000 */

+#define FDCAN_NDAT2_ND56          FDCAN_NDAT2_ND56_Msk                         /*!<New Data flag of Rx Buffer 56             */

+#define FDCAN_NDAT2_ND57_Pos      (25U)

+#define FDCAN_NDAT2_ND57_Msk      (0x1UL << FDCAN_NDAT2_ND57_Pos)              /*!< 0x02000000 */

+#define FDCAN_NDAT2_ND57          FDCAN_NDAT2_ND57_Msk                         /*!<New Data flag of Rx Buffer 57             */

+#define FDCAN_NDAT2_ND58_Pos      (26U)

+#define FDCAN_NDAT2_ND58_Msk      (0x1UL << FDCAN_NDAT2_ND58_Pos)              /*!< 0x04000000 */

+#define FDCAN_NDAT2_ND58          FDCAN_NDAT2_ND58_Msk                         /*!<New Data flag of Rx Buffer 58             */

+#define FDCAN_NDAT2_ND59_Pos      (27U)

+#define FDCAN_NDAT2_ND59_Msk      (0x1UL << FDCAN_NDAT2_ND59_Pos)              /*!< 0x08000000 */

+#define FDCAN_NDAT2_ND59          FDCAN_NDAT2_ND59_Msk                         /*!<New Data flag of Rx Buffer 59             */

+#define FDCAN_NDAT2_ND60_Pos      (28U)

+#define FDCAN_NDAT2_ND60_Msk      (0x1UL << FDCAN_NDAT2_ND60_Pos)              /*!< 0x10000000 */

+#define FDCAN_NDAT2_ND60          FDCAN_NDAT2_ND60_Msk                         /*!<New Data flag of Rx Buffer 60             */

+#define FDCAN_NDAT2_ND61_Pos      (29U)

+#define FDCAN_NDAT2_ND61_Msk      (0x1UL << FDCAN_NDAT2_ND61_Pos)              /*!< 0x20000000 */

+#define FDCAN_NDAT2_ND61          FDCAN_NDAT2_ND61_Msk                         /*!<New Data flag of Rx Buffer 61             */

+#define FDCAN_NDAT2_ND62_Pos      (30U)

+#define FDCAN_NDAT2_ND62_Msk      (0x1UL << FDCAN_NDAT2_ND62_Pos)              /*!< 0x40000000 */

+#define FDCAN_NDAT2_ND62          FDCAN_NDAT2_ND62_Msk                         /*!<New Data flag of Rx Buffer 62             */

+#define FDCAN_NDAT2_ND63_Pos      (31U)

+#define FDCAN_NDAT2_ND63_Msk      (0x1UL << FDCAN_NDAT2_ND63_Pos)              /*!< 0x80000000 */

+#define FDCAN_NDAT2_ND63          FDCAN_NDAT2_ND63_Msk                         /*!<New Data flag of Rx Buffer 63             */

+

+/*****************  Bit definition for FDCAN_RXF0C register  ********************/

+#define FDCAN_RXF0C_F0SA_Pos      (2U)

+#define FDCAN_RXF0C_F0SA_Msk      (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_RXF0C_F0SA          FDCAN_RXF0C_F0SA_Msk                         /*!<Rx FIFO 0 Start Address                   */

+#define FDCAN_RXF0C_F0S_Pos       (16U)

+#define FDCAN_RXF0C_F0S_Msk       (0x7FUL << FDCAN_RXF0C_F0S_Pos)              /*!< 0x007F0000 */

+#define FDCAN_RXF0C_F0S           FDCAN_RXF0C_F0S_Msk                          /*!<Number of Rx FIFO 0 elements              */

+#define FDCAN_RXF0C_F0WM_Pos      (24U)

+#define FDCAN_RXF0C_F0WM_Msk      (0x7FUL << FDCAN_RXF0C_F0WM_Pos)             /*!< 0x7F000000 */

+#define FDCAN_RXF0C_F0WM          FDCAN_RXF0C_F0WM_Msk                         /*!<FIFO 0 Watermark                          */

+#define FDCAN_RXF0C_F0OM_Pos      (31U)

+#define FDCAN_RXF0C_F0OM_Msk      (0x1UL << FDCAN_RXF0C_F0OM_Pos)              /*!< 0x80000000 */

+#define FDCAN_RXF0C_F0OM          FDCAN_RXF0C_F0OM_Msk                         /*!<FIFO 0 Operation Mode                     */

+

+/*****************  Bit definition for FDCAN_RXF0S register  ********************/

+#define FDCAN_RXF0S_F0FL_Pos      (0U)

+#define FDCAN_RXF0S_F0FL_Msk      (0x7FUL << FDCAN_RXF0S_F0FL_Pos)             /*!< 0x0000007F */

+#define FDCAN_RXF0S_F0FL          FDCAN_RXF0S_F0FL_Msk                         /*!<Rx FIFO 0 Fill Level                      */

+#define FDCAN_RXF0S_F0GI_Pos      (8U)

+#define FDCAN_RXF0S_F0GI_Msk      (0x3FUL << FDCAN_RXF0S_F0GI_Pos)             /*!< 0x00003F00 */

+#define FDCAN_RXF0S_F0GI          FDCAN_RXF0S_F0GI_Msk                         /*!<Rx FIFO 0 Get Index                       */

+#define FDCAN_RXF0S_F0PI_Pos      (16U)

+#define FDCAN_RXF0S_F0PI_Msk      (0x3FUL << FDCAN_RXF0S_F0PI_Pos)             /*!< 0x003F0000 */

+#define FDCAN_RXF0S_F0PI          FDCAN_RXF0S_F0PI_Msk                         /*!<Rx FIFO 0 Put Index                       */

+#define FDCAN_RXF0S_F0F_Pos       (24U)

+#define FDCAN_RXF0S_F0F_Msk       (0x1UL << FDCAN_RXF0S_F0F_Pos)               /*!< 0x01000000 */

+#define FDCAN_RXF0S_F0F           FDCAN_RXF0S_F0F_Msk                          /*!<Rx FIFO 0 Full                            */

+#define FDCAN_RXF0S_RF0L_Pos      (25U)

+#define FDCAN_RXF0S_RF0L_Msk      (0x1UL << FDCAN_RXF0S_RF0L_Pos)              /*!< 0x02000000 */

+#define FDCAN_RXF0S_RF0L          FDCAN_RXF0S_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                    */

+

+/*****************  Bit definition for FDCAN_RXF0A register  ********************/

+#define FDCAN_RXF0A_F0AI_Pos      (0U)

+#define FDCAN_RXF0A_F0AI_Msk      (0x3FUL << FDCAN_RXF0A_F0AI_Pos)             /*!< 0x0000003F */

+#define FDCAN_RXF0A_F0AI          FDCAN_RXF0A_F0AI_Msk                         /*!<Rx FIFO 0 Acknowledge Index               */

+

+/*****************  Bit definition for FDCAN_RXBC register  ********************/

+#define FDCAN_RXBC_RBSA_Pos       (2U)

+#define FDCAN_RXBC_RBSA_Msk       (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)            /*!< 0x0000FFFC */

+#define FDCAN_RXBC_RBSA           FDCAN_RXBC_RBSA_Msk                          /*!<Rx Buffer Start Address                   */

+

+/*****************  Bit definition for FDCAN_RXF1C register  ********************/

+#define FDCAN_RXF1C_F1SA_Pos      (2U)

+#define FDCAN_RXF1C_F1SA_Msk      (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_RXF1C_F1SA          FDCAN_RXF1C_F1SA_Msk                         /*!<Rx FIFO 1 Start Address                   */

+#define FDCAN_RXF1C_F1S_Pos       (16U)

+#define FDCAN_RXF1C_F1S_Msk       (0x7FUL << FDCAN_RXF1C_F1S_Pos)              /*!< 0x007F0000 */

+#define FDCAN_RXF1C_F1S           FDCAN_RXF1C_F1S_Msk                          /*!<Number of Rx FIFO 1 elements              */

+#define FDCAN_RXF1C_F1WM_Pos      (24U)

+#define FDCAN_RXF1C_F1WM_Msk      (0x7FUL << FDCAN_RXF1C_F1WM_Pos)             /*!< 0x7F000000 */

+#define FDCAN_RXF1C_F1WM          FDCAN_RXF1C_F1WM_Msk                         /*!<Rx FIFO 1 Watermark                       */

+#define FDCAN_RXF1C_F1OM_Pos      (31U)

+#define FDCAN_RXF1C_F1OM_Msk      (0x1UL << FDCAN_RXF1C_F1OM_Pos)              /*!< 0x80000000 */

+#define FDCAN_RXF1C_F1OM          FDCAN_RXF1C_F1OM_Msk                         /*!<FIFO 1 Operation Mode                     */

+

+/*****************  Bit definition for FDCAN_RXF1S register  ********************/

+#define FDCAN_RXF1S_F1FL_Pos      (0U)

+#define FDCAN_RXF1S_F1FL_Msk      (0x7FUL << FDCAN_RXF1S_F1FL_Pos)             /*!< 0x0000007F */

+#define FDCAN_RXF1S_F1FL          FDCAN_RXF1S_F1FL_Msk                         /*!<Rx FIFO 1 Fill Level                      */

+#define FDCAN_RXF1S_F1GI_Pos      (8U)

+#define FDCAN_RXF1S_F1GI_Msk      (0x3FUL << FDCAN_RXF1S_F1GI_Pos)             /*!< 0x00003F00 */

+#define FDCAN_RXF1S_F1GI          FDCAN_RXF1S_F1GI_Msk                         /*!<Rx FIFO 1 Get Index                       */

+#define FDCAN_RXF1S_F1PI_Pos      (16U)

+#define FDCAN_RXF1S_F1PI_Msk      (0x3FUL << FDCAN_RXF1S_F1PI_Pos)             /*!< 0x003F0000 */

+#define FDCAN_RXF1S_F1PI          FDCAN_RXF1S_F1PI_Msk                         /*!<Rx FIFO 1 Put Index                       */

+#define FDCAN_RXF1S_F1F_Pos       (24U)

+#define FDCAN_RXF1S_F1F_Msk       (0x1UL << FDCAN_RXF1S_F1F_Pos)               /*!< 0x01000000 */

+#define FDCAN_RXF1S_F1F           FDCAN_RXF1S_F1F_Msk                          /*!<Rx FIFO 1 Full                            */

+#define FDCAN_RXF1S_RF1L_Pos      (25U)

+#define FDCAN_RXF1S_RF1L_Msk      (0x1UL << FDCAN_RXF1S_RF1L_Pos)              /*!< 0x02000000 */

+#define FDCAN_RXF1S_RF1L          FDCAN_RXF1S_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                    */

+

+/*****************  Bit definition for FDCAN_RXF1A register  ********************/

+#define FDCAN_RXF1A_F1AI_Pos      (0U)

+#define FDCAN_RXF1A_F1AI_Msk      (0x3FUL << FDCAN_RXF1A_F1AI_Pos)             /*!< 0x0000003F */

+#define FDCAN_RXF1A_F1AI          FDCAN_RXF1A_F1AI_Msk                         /*!<Rx FIFO 1 Acknowledge Index               */

+

+/*****************  Bit definition for FDCAN_RXESC register  ********************/

+#define FDCAN_RXESC_F0DS_Pos      (0U)

+#define FDCAN_RXESC_F0DS_Msk      (0x7UL << FDCAN_RXESC_F0DS_Pos)              /*!< 0x00000007 */

+#define FDCAN_RXESC_F0DS          FDCAN_RXESC_F0DS_Msk                         /*!<Rx FIFO 1 Data Field Size                 */

+#define FDCAN_RXESC_F1DS_Pos      (4U)

+#define FDCAN_RXESC_F1DS_Msk      (0x7UL << FDCAN_RXESC_F1DS_Pos)              /*!< 0x00000070 */

+#define FDCAN_RXESC_F1DS          FDCAN_RXESC_F1DS_Msk                         /*!<Rx FIFO 0 Data Field Size                 */

+#define FDCAN_RXESC_RBDS_Pos      (8U)

+#define FDCAN_RXESC_RBDS_Msk      (0x7UL << FDCAN_RXESC_RBDS_Pos)              /*!< 0x00000700 */

+#define FDCAN_RXESC_RBDS          FDCAN_RXESC_RBDS_Msk                         /*!<Rx Buffer Data Field Size                 */

+

+/*****************  Bit definition for FDCAN_TXBC register  *********************/

+#define FDCAN_TXBC_TBSA_Pos       (2U)

+#define FDCAN_TXBC_TBSA_Msk       (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)            /*!< 0x0000FFFC */

+#define FDCAN_TXBC_TBSA           FDCAN_TXBC_TBSA_Msk                          /*!<Tx Buffers Start Address                  */

+#define FDCAN_TXBC_NDTB_Pos       (16U)

+#define FDCAN_TXBC_NDTB_Msk       (0x3FUL << FDCAN_TXBC_NDTB_Pos)              /*!< 0x003F0000 */

+#define FDCAN_TXBC_NDTB           FDCAN_TXBC_NDTB_Msk                          /*!<Number of Dedicated Transmit Buffers      */

+#define FDCAN_TXBC_TFQS_Pos       (24U)

+#define FDCAN_TXBC_TFQS_Msk       (0x3FUL << FDCAN_TXBC_TFQS_Pos)              /*!< 0x3F000000 */

+#define FDCAN_TXBC_TFQS           FDCAN_TXBC_TFQS_Msk                          /*!<Transmit FIFO/Queue Size                  */

+#define FDCAN_TXBC_TFQM_Pos       (30U)

+#define FDCAN_TXBC_TFQM_Msk       (0x1UL << FDCAN_TXBC_TFQM_Pos)               /*!< 0x40000000 */

+#define FDCAN_TXBC_TFQM           FDCAN_TXBC_TFQM_Msk                          /*!<Tx FIFO/Queue Mode                        */

+

+/*****************  Bit definition for FDCAN_TXFQS register  *********************/

+#define FDCAN_TXFQS_TFFL_Pos      (0U)

+#define FDCAN_TXFQS_TFFL_Msk      (0x3FUL << FDCAN_TXFQS_TFFL_Pos)             /*!< 0x0000003F */

+#define FDCAN_TXFQS_TFFL          FDCAN_TXFQS_TFFL_Msk                         /*!<Tx FIFO Free Level                        */

+#define FDCAN_TXFQS_TFGI_Pos      (8U)

+#define FDCAN_TXFQS_TFGI_Msk      (0x1FUL << FDCAN_TXFQS_TFGI_Pos)             /*!< 0x00001F00 */

+#define FDCAN_TXFQS_TFGI          FDCAN_TXFQS_TFGI_Msk                         /*!<Tx FIFO Get Index                         */

+#define FDCAN_TXFQS_TFQPI_Pos     (16U)

+#define FDCAN_TXFQS_TFQPI_Msk     (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)            /*!< 0x001F0000 */

+#define FDCAN_TXFQS_TFQPI         FDCAN_TXFQS_TFQPI_Msk                        /*!<Tx FIFO/Queue Put Index                   */

+#define FDCAN_TXFQS_TFQF_Pos      (21U)

+#define FDCAN_TXFQS_TFQF_Msk      (0x1UL << FDCAN_TXFQS_TFQF_Pos)              /*!< 0x00200000 */

+#define FDCAN_TXFQS_TFQF          FDCAN_TXFQS_TFQF_Msk                         /*!<Tx FIFO/Queue Full                        */

+

+/*****************  Bit definition for FDCAN_TXESC register  *********************/

+#define FDCAN_TXESC_TBDS_Pos      (0U)

+#define FDCAN_TXESC_TBDS_Msk      (0x7UL << FDCAN_TXESC_TBDS_Pos)              /*!< 0x00000007 */

+#define FDCAN_TXESC_TBDS          FDCAN_TXESC_TBDS_Msk                         /*!<Tx Buffer Data Field Size                 */

+

+/*****************  Bit definition for FDCAN_TXBRP register  *********************/

+#define FDCAN_TXBRP_TRP_Pos       (0U)

+#define FDCAN_TXBRP_TRP_Msk       (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)        /*!< 0xFFFFFFFF */

+#define FDCAN_TXBRP_TRP           FDCAN_TXBRP_TRP_Msk                          /*!<Transmission Request Pending              */

+

+/*****************  Bit definition for FDCAN_TXBAR register  *********************/

+#define FDCAN_TXBAR_AR_Pos        (0U)

+#define FDCAN_TXBAR_AR_Msk        (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBAR_AR            FDCAN_TXBAR_AR_Msk                           /*!<Add Request                               */

+

+/*****************  Bit definition for FDCAN_TXBCR register  *********************/

+#define FDCAN_TXBCR_CR_Pos        (0U)

+#define FDCAN_TXBCR_CR_Msk        (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCR_CR            FDCAN_TXBCR_CR_Msk                           /*!<Cancellation Request                      */

+

+/*****************  Bit definition for FDCAN_TXBTO register  *********************/

+#define FDCAN_TXBTO_TO_Pos        (0U)

+#define FDCAN_TXBTO_TO_Msk        (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBTO_TO            FDCAN_TXBTO_TO_Msk                           /*!<Transmission Occurred                     */

+

+/*****************  Bit definition for FDCAN_TXBCF register  *********************/

+#define FDCAN_TXBCF_CF_Pos        (0U)

+#define FDCAN_TXBCF_CF_Msk        (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCF_CF            FDCAN_TXBCF_CF_Msk                           /*!<Cancellation Finished                     */

+

+/*****************  Bit definition for FDCAN_TXBTIE register  ********************/

+#define FDCAN_TXBTIE_TIE_Pos      (0U)

+#define FDCAN_TXBTIE_TIE_Msk      (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)       /*!< 0xFFFFFFFF */

+#define FDCAN_TXBTIE_TIE          FDCAN_TXBTIE_TIE_Msk                         /*!<Transmission Interrupt Enable             */

+

+/*****************  Bit definition for FDCAN_ TXBCIE register  *******************/

+#define FDCAN_TXBCIE_CFIE_Pos     (0U)

+#define FDCAN_TXBCIE_CFIE_Msk     (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)      /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCIE_CFIE         FDCAN_TXBCIE_CFIE_Msk                        /*!<Cancellation Finished Interrupt Enable    */

+

+/*****************  Bit definition for FDCAN_TXEFC register  *********************/

+#define FDCAN_TXEFC_EFSA_Pos      (2U)

+#define FDCAN_TXEFC_EFSA_Msk      (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_TXEFC_EFSA          FDCAN_TXEFC_EFSA_Msk                         /*!<Event FIFO Start Address                  */

+#define FDCAN_TXEFC_EFS_Pos       (16U)

+#define FDCAN_TXEFC_EFS_Msk       (0x3FUL << FDCAN_TXEFC_EFS_Pos)              /*!< 0x003F0000 */

+#define FDCAN_TXEFC_EFS           FDCAN_TXEFC_EFS_Msk                          /*!<Event FIFO Size                           */

+#define FDCAN_TXEFC_EFWM_Pos      (24U)

+#define FDCAN_TXEFC_EFWM_Msk      (0x3FUL << FDCAN_TXEFC_EFWM_Pos)             /*!< 0x3F000000 */

+#define FDCAN_TXEFC_EFWM          FDCAN_TXEFC_EFWM_Msk                         /*!<Event FIFO Watermark                      */

+

+/*****************  Bit definition for FDCAN_TXEFS register  *********************/

+#define FDCAN_TXEFS_EFFL_Pos      (0U)

+#define FDCAN_TXEFS_EFFL_Msk      (0x3FUL << FDCAN_TXEFS_EFFL_Pos)             /*!< 0x0000003F */

+#define FDCAN_TXEFS_EFFL          FDCAN_TXEFS_EFFL_Msk                         /*!<Event FIFO Fill Level                     */

+#define FDCAN_TXEFS_EFGI_Pos      (8U)

+#define FDCAN_TXEFS_EFGI_Msk      (0x1FUL << FDCAN_TXEFS_EFGI_Pos)             /*!< 0x00001F00 */

+#define FDCAN_TXEFS_EFGI          FDCAN_TXEFS_EFGI_Msk                         /*!<Event FIFO Get Index                      */

+#define FDCAN_TXEFS_EFPI_Pos      (16U)

+#define FDCAN_TXEFS_EFPI_Msk      (0x1FUL << FDCAN_TXEFS_EFPI_Pos)             /*!< 0x001F0000 */

+#define FDCAN_TXEFS_EFPI          FDCAN_TXEFS_EFPI_Msk                         /*!<Event FIFO Put Index                      */

+#define FDCAN_TXEFS_EFF_Pos       (24U)

+#define FDCAN_TXEFS_EFF_Msk       (0x1UL << FDCAN_TXEFS_EFF_Pos)               /*!< 0x01000000 */

+#define FDCAN_TXEFS_EFF           FDCAN_TXEFS_EFF_Msk                          /*!<Event FIFO Full                           */

+#define FDCAN_TXEFS_TEFL_Pos      (25U)

+#define FDCAN_TXEFS_TEFL_Msk      (0x1UL << FDCAN_TXEFS_TEFL_Pos)              /*!< 0x02000000 */

+#define FDCAN_TXEFS_TEFL          FDCAN_TXEFS_TEFL_Msk                         /*!<Tx Event FIFO Element Lost                */

+

+/*****************  Bit definition for FDCAN_TXEFA register  *********************/

+#define FDCAN_TXEFA_EFAI_Pos      (0U)

+#define FDCAN_TXEFA_EFAI_Msk      (0x1FUL << FDCAN_TXEFA_EFAI_Pos)             /*!< 0x0000001F */

+#define FDCAN_TXEFA_EFAI          FDCAN_TXEFA_EFAI_Msk                         /*!<Event FIFO Acknowledge Index              */

+

+/*****************  Bit definition for FDCAN_TTTMC register  *********************/

+#define FDCAN_TTTMC_TMSA_Pos      (2U)

+#define FDCAN_TTTMC_TMSA_Msk      (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_TTTMC_TMSA          FDCAN_TTTMC_TMSA_Msk                         /*!<Trigger Memory Start Address              */

+#define FDCAN_TTTMC_TME_Pos       (16U)

+#define FDCAN_TTTMC_TME_Msk       (0x7FUL << FDCAN_TTTMC_TME_Pos)              /*!< 0x007F0000 */

+#define FDCAN_TTTMC_TME           FDCAN_TTTMC_TME_Msk                          /*!<Trigger Memory Elements                   */

+

+/*****************  Bit definition for FDCAN_TTRMC register  *********************/

+#define FDCAN_TTRMC_RID_Pos       (0U)

+#define FDCAN_TTRMC_RID_Msk       (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)        /*!< 0x1FFFFFFF */

+#define FDCAN_TTRMC_RID           FDCAN_TTRMC_RID_Msk                          /*!<Reference Identifier                      */

+#define FDCAN_TTRMC_XTD_Pos       (30U)

+#define FDCAN_TTRMC_XTD_Msk       (0x1UL << FDCAN_TTRMC_XTD_Pos)               /*!< 0x40000000 */

+#define FDCAN_TTRMC_XTD           FDCAN_TTRMC_XTD_Msk                          /*!< Extended Identifier                      */

+#define FDCAN_TTRMC_RMPS_Pos      (31U)

+#define FDCAN_TTRMC_RMPS_Msk      (0x1UL << FDCAN_TTRMC_RMPS_Pos)              /*!< 0x80000000 */

+#define FDCAN_TTRMC_RMPS          FDCAN_TTRMC_RMPS_Msk                         /*!<Reference Message Payload Select          */

+

+/*****************  Bit definition for FDCAN_TTOCF register  *********************/

+#define FDCAN_TTOCF_OM_Pos        (0U)

+#define FDCAN_TTOCF_OM_Msk        (0x3UL << FDCAN_TTOCF_OM_Pos)                /*!< 0x00000003 */

+#define FDCAN_TTOCF_OM            FDCAN_TTOCF_OM_Msk                           /*!<Operation Mode                            */

+#define FDCAN_TTOCF_GEN_Pos       (3U)

+#define FDCAN_TTOCF_GEN_Msk       (0x1UL << FDCAN_TTOCF_GEN_Pos)               /*!< 0x00000008 */

+#define FDCAN_TTOCF_GEN           FDCAN_TTOCF_GEN_Msk                          /*!<Gap Enable                                */

+#define FDCAN_TTOCF_TM_Pos        (4U)

+#define FDCAN_TTOCF_TM_Msk        (0x1UL << FDCAN_TTOCF_TM_Pos)                /*!< 0x00000010 */

+#define FDCAN_TTOCF_TM            FDCAN_TTOCF_TM_Msk                           /*!<Time Master                               */

+#define FDCAN_TTOCF_LDSDL_Pos     (5U)

+#define FDCAN_TTOCF_LDSDL_Msk     (0x7UL << FDCAN_TTOCF_LDSDL_Pos)             /*!< 0x000000E0 */

+#define FDCAN_TTOCF_LDSDL         FDCAN_TTOCF_LDSDL_Msk                        /*!<LD of Synchronization Deviation Limit     */

+#define FDCAN_TTOCF_IRTO_Pos      (8U)

+#define FDCAN_TTOCF_IRTO_Msk      (0x7FUL << FDCAN_TTOCF_IRTO_Pos)             /*!< 0x00007F00 */

+#define FDCAN_TTOCF_IRTO          FDCAN_TTOCF_IRTO_Msk                         /*!<Initial Reference Trigger Offset          */

+#define FDCAN_TTOCF_EECS_Pos      (15U)

+#define FDCAN_TTOCF_EECS_Msk      (0x1UL << FDCAN_TTOCF_EECS_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTOCF_EECS          FDCAN_TTOCF_EECS_Msk                         /*!<Enable External Clock Synchronization     */

+#define FDCAN_TTOCF_AWL_Pos       (16U)

+#define FDCAN_TTOCF_AWL_Msk       (0xFFUL << FDCAN_TTOCF_AWL_Pos)              /*!< 0x00FF0000 */

+#define FDCAN_TTOCF_AWL           FDCAN_TTOCF_AWL_Msk                          /*!<Application Watchdog Limit                */

+#define FDCAN_TTOCF_EGTF_Pos      (24U)

+#define FDCAN_TTOCF_EGTF_Msk      (0x1UL << FDCAN_TTOCF_EGTF_Pos)              /*!< 0x01000000 */

+#define FDCAN_TTOCF_EGTF          FDCAN_TTOCF_EGTF_Msk                         /*!<Enable Global Time Filtering              */

+#define FDCAN_TTOCF_ECC_Pos       (25U)

+#define FDCAN_TTOCF_ECC_Msk       (0x1UL << FDCAN_TTOCF_ECC_Pos)               /*!< 0x02000000 */

+#define FDCAN_TTOCF_ECC           FDCAN_TTOCF_ECC_Msk                          /*!<Enable Clock Calibration                  */

+#define FDCAN_TTOCF_EVTP_Pos      (26U)

+#define FDCAN_TTOCF_EVTP_Msk      (0x1UL << FDCAN_TTOCF_EVTP_Pos)              /*!< 0x04000000 */

+#define FDCAN_TTOCF_EVTP          FDCAN_TTOCF_EVTP_Msk                         /*!<Event Trigger Polarity                    */

+

+/*****************  Bit definition for FDCAN_TTMLM register  *********************/

+#define FDCAN_TTMLM_CCM_Pos       (0U)

+#define FDCAN_TTMLM_CCM_Msk       (0x3FUL << FDCAN_TTMLM_CCM_Pos)              /*!< 0x0000003F */

+#define FDCAN_TTMLM_CCM           FDCAN_TTMLM_CCM_Msk                          /*!<Cycle Count Max                           */

+#define FDCAN_TTMLM_CSS_Pos       (6U)

+#define FDCAN_TTMLM_CSS_Msk       (0x3UL << FDCAN_TTMLM_CSS_Pos)               /*!< 0x000000C0 */

+#define FDCAN_TTMLM_CSS           FDCAN_TTMLM_CSS_Msk                          /*!<Cycle Start Synchronization               */

+#define FDCAN_TTMLM_TXEW_Pos      (8U)

+#define FDCAN_TTMLM_TXEW_Msk      (0xFUL << FDCAN_TTMLM_TXEW_Pos)              /*!< 0x00000F00 */

+#define FDCAN_TTMLM_TXEW          FDCAN_TTMLM_TXEW_Msk                         /*!<Tx Enable Window                          */

+#define FDCAN_TTMLM_ENTT_Pos      (16U)

+#define FDCAN_TTMLM_ENTT_Msk      (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)            /*!< 0x0FFF0000 */

+#define FDCAN_TTMLM_ENTT          FDCAN_TTMLM_ENTT_Msk                         /*!<Expected Number of Tx Triggers            */

+

+/*****************  Bit definition for FDCAN_TURCF register  *********************/

+#define FDCAN_TURCF_NCL_Pos       (0U)

+#define FDCAN_TURCF_NCL_Msk       (0xFFFFUL << FDCAN_TURCF_NCL_Pos)            /*!< 0x0000FFFF */

+#define FDCAN_TURCF_NCL           FDCAN_TURCF_NCL_Msk                          /*!<Numerator Configuration Low               */

+#define FDCAN_TURCF_DC_Pos        (16U)

+#define FDCAN_TURCF_DC_Msk        (0x3FFFUL << FDCAN_TURCF_DC_Pos)             /*!< 0x3FFF0000 */

+#define FDCAN_TURCF_DC            FDCAN_TURCF_DC_Msk                           /*!<Denominator Configuration                 */

+#define FDCAN_TURCF_ELT_Pos       (31U)

+#define FDCAN_TURCF_ELT_Msk       (0x1UL << FDCAN_TURCF_ELT_Pos)               /*!< 0x80000000 */

+#define FDCAN_TURCF_ELT           FDCAN_TURCF_ELT_Msk                          /*!<Enable Local Time                         */

+

+/*****************  Bit definition for FDCAN_TTOCN register  ********************/

+#define FDCAN_TTOCN_SGT_Pos       (0U)

+#define FDCAN_TTOCN_SGT_Msk       (0x1UL << FDCAN_TTOCN_SGT_Pos)               /*!< 0x00000001 */

+#define FDCAN_TTOCN_SGT           FDCAN_TTOCN_SGT_Msk                          /*!<Set Global time                           */

+#define FDCAN_TTOCN_ECS_Pos       (1U)

+#define FDCAN_TTOCN_ECS_Msk       (0x1UL << FDCAN_TTOCN_ECS_Pos)               /*!< 0x00000002 */

+#define FDCAN_TTOCN_ECS           FDCAN_TTOCN_ECS_Msk                          /*!<External Clock Synchronization            */

+#define FDCAN_TTOCN_SWP_Pos       (2U)

+#define FDCAN_TTOCN_SWP_Msk       (0x1UL << FDCAN_TTOCN_SWP_Pos)               /*!< 0x00000004 */

+#define FDCAN_TTOCN_SWP           FDCAN_TTOCN_SWP_Msk                          /*!<Stop Watch Polarity                       */

+#define FDCAN_TTOCN_SWS_Pos       (3U)

+#define FDCAN_TTOCN_SWS_Msk       (0x3UL << FDCAN_TTOCN_SWS_Pos)               /*!< 0x00000018 */

+#define FDCAN_TTOCN_SWS           FDCAN_TTOCN_SWS_Msk                          /*!<Stop Watch Source                         */

+#define FDCAN_TTOCN_RTIE_Pos      (5U)

+#define FDCAN_TTOCN_RTIE_Msk      (0x1UL << FDCAN_TTOCN_RTIE_Pos)              /*!< 0x00000020 */

+#define FDCAN_TTOCN_RTIE          FDCAN_TTOCN_RTIE_Msk                         /*!<Register Time Mark Interrupt Pulse Enable */

+#define FDCAN_TTOCN_TMC_Pos       (6U)

+#define FDCAN_TTOCN_TMC_Msk       (0x3UL << FDCAN_TTOCN_TMC_Pos)               /*!< 0x000000C0 */

+#define FDCAN_TTOCN_TMC           FDCAN_TTOCN_TMC_Msk                          /*!<Register Time Mark Compare                */

+#define FDCAN_TTOCN_TTIE_Pos      (8U)

+#define FDCAN_TTOCN_TTIE_Msk      (0x1UL << FDCAN_TTOCN_TTIE_Pos)              /*!< 0x00000100 */

+#define FDCAN_TTOCN_TTIE          FDCAN_TTOCN_TTIE_Msk                         /*!<Trigger Time Mark Interrupt Pulse Enable  */

+#define FDCAN_TTOCN_GCS_Pos       (9U)

+#define FDCAN_TTOCN_GCS_Msk       (0x1UL << FDCAN_TTOCN_GCS_Pos)               /*!< 0x00000200 */

+#define FDCAN_TTOCN_GCS           FDCAN_TTOCN_GCS_Msk                          /*!<Gap Control Select                        */

+#define FDCAN_TTOCN_FGP_Pos       (10U)

+#define FDCAN_TTOCN_FGP_Msk       (0x1UL << FDCAN_TTOCN_FGP_Pos)               /*!< 0x00000400 */

+#define FDCAN_TTOCN_FGP           FDCAN_TTOCN_FGP_Msk                          /*!<Finish Gap                                */

+#define FDCAN_TTOCN_TMG_Pos       (11U)

+#define FDCAN_TTOCN_TMG_Msk       (0x1UL << FDCAN_TTOCN_TMG_Pos)               /*!< 0x00000800 */

+#define FDCAN_TTOCN_TMG           FDCAN_TTOCN_TMG_Msk                          /*!<Time Mark Gap                             */

+#define FDCAN_TTOCN_NIG_Pos       (12U)

+#define FDCAN_TTOCN_NIG_Msk       (0x1UL << FDCAN_TTOCN_NIG_Pos)               /*!< 0x00001000 */

+#define FDCAN_TTOCN_NIG           FDCAN_TTOCN_NIG_Msk                          /*!<Next is Gap                               */

+#define FDCAN_TTOCN_ESCN_Pos      (13U)

+#define FDCAN_TTOCN_ESCN_Msk      (0x1UL << FDCAN_TTOCN_ESCN_Pos)              /*!< 0x00002000 */

+#define FDCAN_TTOCN_ESCN          FDCAN_TTOCN_ESCN_Msk                         /*!<External Synchronization Control          */

+#define FDCAN_TTOCN_LCKC_Pos      (15U)

+#define FDCAN_TTOCN_LCKC_Msk      (0x1UL << FDCAN_TTOCN_LCKC_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTOCN_LCKC          FDCAN_TTOCN_LCKC_Msk                         /*!<TT Operation Control Register Locked      */

+

+/*****************  Bit definition for FDCAN_TTGTP register  ********************/

+#define FDCAN_TTGTP_TP_Pos        (0U)

+#define FDCAN_TTGTP_TP_Msk        (0xFFFFUL << FDCAN_TTGTP_TP_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTGTP_TP            FDCAN_TTGTP_TP_Msk                           /*!<Time Preset                               */

+#define FDCAN_TTGTP_CTP_Pos       (16U)

+#define FDCAN_TTGTP_CTP_Msk       (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)            /*!< 0xFFFF0000 */

+#define FDCAN_TTGTP_CTP           FDCAN_TTGTP_CTP_Msk                          /*!<Cycle Time Target Phase                   */

+

+/*****************  Bit definition for FDCAN_TTTMK register  ********************/

+#define FDCAN_TTTMK_TM_Pos        (0U)

+#define FDCAN_TTTMK_TM_Msk        (0xFFFFUL << FDCAN_TTTMK_TM_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTTMK_TM            FDCAN_TTTMK_TM_Msk                           /*!<Time Mark                                 */

+#define FDCAN_TTTMK_TICC_Pos      (16U)

+#define FDCAN_TTTMK_TICC_Msk      (0x7FUL << FDCAN_TTTMK_TICC_Pos)             /*!< 0x007F0000 */

+#define FDCAN_TTTMK_TICC          FDCAN_TTTMK_TICC_Msk                         /*!<Time Mark Cycle Code                      */

+#define FDCAN_TTTMK_LCKM_Pos      (31U)

+#define FDCAN_TTTMK_LCKM_Msk      (0x1UL << FDCAN_TTTMK_LCKM_Pos)              /*!< 0x80000000 */

+#define FDCAN_TTTMK_LCKM          FDCAN_TTTMK_LCKM_Msk                         /*!<TT Time Mark Register Locked              */

+

+/*****************  Bit definition for FDCAN_TTIR register  ********************/

+#define FDCAN_TTIR_SBC_Pos        (0U)

+#define FDCAN_TTIR_SBC_Msk        (0x1UL << FDCAN_TTIR_SBC_Pos)                /*!< 0x00000001 */

+#define FDCAN_TTIR_SBC            FDCAN_TTIR_SBC_Msk                           /*!<Start of Basic Cycle                      */

+#define FDCAN_TTIR_SMC_Pos        (1U)

+#define FDCAN_TTIR_SMC_Msk        (0x1UL << FDCAN_TTIR_SMC_Pos)                /*!< 0x00000002 */

+#define FDCAN_TTIR_SMC            FDCAN_TTIR_SMC_Msk                           /*!<Start of Matrix Cycle                     */

+#define FDCAN_TTIR_CSM_Pos        (2U)

+#define FDCAN_TTIR_CSM_Msk        (0x1UL << FDCAN_TTIR_CSM_Pos)                /*!< 0x00000004 */

+#define FDCAN_TTIR_CSM            FDCAN_TTIR_CSM_Msk                           /*!<Change of Synchronization Mode            */

+#define FDCAN_TTIR_SOG_Pos        (3U)

+#define FDCAN_TTIR_SOG_Msk        (0x1UL << FDCAN_TTIR_SOG_Pos)                /*!< 0x00000008 */

+#define FDCAN_TTIR_SOG            FDCAN_TTIR_SOG_Msk                           /*!<Start of Gap                              */

+#define FDCAN_TTIR_RTMI_Pos       (4U)

+#define FDCAN_TTIR_RTMI_Msk       (0x1UL << FDCAN_TTIR_RTMI_Pos)               /*!< 0x00000010 */

+#define FDCAN_TTIR_RTMI           FDCAN_TTIR_RTMI_Msk                          /*!<Register Time Mark Interrupt              */

+#define FDCAN_TTIR_TTMI_Pos       (5U)

+#define FDCAN_TTIR_TTMI_Msk       (0x1UL << FDCAN_TTIR_TTMI_Pos)               /*!< 0x00000020 */

+#define FDCAN_TTIR_TTMI           FDCAN_TTIR_TTMI_Msk                          /*!<Trigger Time Mark Event Internal          */

+#define FDCAN_TTIR_SWE_Pos        (6U)

+#define FDCAN_TTIR_SWE_Msk        (0x1UL << FDCAN_TTIR_SWE_Pos)                /*!< 0x00000040 */

+#define FDCAN_TTIR_SWE            FDCAN_TTIR_SWE_Msk                           /*!<Stop Watch Event                          */

+#define FDCAN_TTIR_GTW_Pos        (7U)

+#define FDCAN_TTIR_GTW_Msk        (0x1UL << FDCAN_TTIR_GTW_Pos)                /*!< 0x00000080 */

+#define FDCAN_TTIR_GTW            FDCAN_TTIR_GTW_Msk                           /*!<Global Time Wrap                          */

+#define FDCAN_TTIR_GTD_Pos        (8U)

+#define FDCAN_TTIR_GTD_Msk        (0x1UL << FDCAN_TTIR_GTD_Pos)                /*!< 0x00000100 */

+#define FDCAN_TTIR_GTD            FDCAN_TTIR_GTD_Msk                           /*!<Global Time Discontinuity                 */

+#define FDCAN_TTIR_GTE_Pos        (9U)

+#define FDCAN_TTIR_GTE_Msk        (0x1UL << FDCAN_TTIR_GTE_Pos)                /*!< 0x00000200 */

+#define FDCAN_TTIR_GTE            FDCAN_TTIR_GTE_Msk                           /*!<Global Time Error                         */

+#define FDCAN_TTIR_TXU_Pos        (10U)

+#define FDCAN_TTIR_TXU_Msk        (0x1UL << FDCAN_TTIR_TXU_Pos)                /*!< 0x00000400 */

+#define FDCAN_TTIR_TXU            FDCAN_TTIR_TXU_Msk                           /*!<Tx Count Underflow                        */

+#define FDCAN_TTIR_TXO_Pos        (11U)

+#define FDCAN_TTIR_TXO_Msk        (0x1UL << FDCAN_TTIR_TXO_Pos)                /*!< 0x00000800 */

+#define FDCAN_TTIR_TXO            FDCAN_TTIR_TXO_Msk                           /*!<Tx Count Overflow                         */

+#define FDCAN_TTIR_SE1_Pos        (12U)

+#define FDCAN_TTIR_SE1_Msk        (0x1UL << FDCAN_TTIR_SE1_Pos)                /*!< 0x00001000 */

+#define FDCAN_TTIR_SE1            FDCAN_TTIR_SE1_Msk                           /*!<Scheduling Error 1                        */

+#define FDCAN_TTIR_SE2_Pos        (13U)

+#define FDCAN_TTIR_SE2_Msk        (0x1UL << FDCAN_TTIR_SE2_Pos)                /*!< 0x00002000 */

+#define FDCAN_TTIR_SE2            FDCAN_TTIR_SE2_Msk                           /*!<Scheduling Error 2                        */

+#define FDCAN_TTIR_ELC_Pos        (14U)

+#define FDCAN_TTIR_ELC_Msk        (0x1UL << FDCAN_TTIR_ELC_Pos)                /*!< 0x00004000 */

+#define FDCAN_TTIR_ELC            FDCAN_TTIR_ELC_Msk                           /*!<Error Level Changed                       */

+#define FDCAN_TTIR_IWT_Pos        (15U)

+#define FDCAN_TTIR_IWT_Msk        (0x1UL << FDCAN_TTIR_IWT_Pos)                /*!< 0x00008000 */

+#define FDCAN_TTIR_IWT            FDCAN_TTIR_IWT_Msk                           /*!<Initialization Watch Trigger              */

+#define FDCAN_TTIR_WT_Pos         (16U)

+#define FDCAN_TTIR_WT_Msk         (0x1UL << FDCAN_TTIR_WT_Pos)                 /*!< 0x00010000 */

+#define FDCAN_TTIR_WT             FDCAN_TTIR_WT_Msk                            /*!<Watch Trigger                             */

+#define FDCAN_TTIR_AW_Pos         (17U)

+#define FDCAN_TTIR_AW_Msk         (0x1UL << FDCAN_TTIR_AW_Pos)                 /*!< 0x00020000 */

+#define FDCAN_TTIR_AW             FDCAN_TTIR_AW_Msk                            /*!<Application Watchdog                      */

+#define FDCAN_TTIR_CER_Pos        (18U)

+#define FDCAN_TTIR_CER_Msk        (0x1UL << FDCAN_TTIR_CER_Pos)                /*!< 0x00040000 */

+#define FDCAN_TTIR_CER            FDCAN_TTIR_CER_Msk                           /*!<Configuration Error                       */

+

+/*****************  Bit definition for FDCAN_TTIE register  ********************/

+#define FDCAN_TTIE_SBCE_Pos       (0U)

+#define FDCAN_TTIE_SBCE_Msk       (0x1UL << FDCAN_TTIE_SBCE_Pos)               /*!< 0x00000001 */

+#define FDCAN_TTIE_SBCE           FDCAN_TTIE_SBCE_Msk                          /*!<Start of Basic Cycle Interrupt Enable             */

+#define FDCAN_TTIE_SMCE_Pos       (1U)

+#define FDCAN_TTIE_SMCE_Msk       (0x1UL << FDCAN_TTIE_SMCE_Pos)               /*!< 0x00000002 */

+#define FDCAN_TTIE_SMCE           FDCAN_TTIE_SMCE_Msk                          /*!<Start of Matrix Cycle Interrupt Enable            */

+#define FDCAN_TTIE_CSME_Pos       (2U)

+#define FDCAN_TTIE_CSME_Msk       (0x1UL << FDCAN_TTIE_CSME_Pos)               /*!< 0x00000004 */

+#define FDCAN_TTIE_CSME           FDCAN_TTIE_CSME_Msk                          /*!<Change of Synchronization Mode Interrupt Enable   */

+#define FDCAN_TTIE_SOGE_Pos       (3U)

+#define FDCAN_TTIE_SOGE_Msk       (0x1UL << FDCAN_TTIE_SOGE_Pos)               /*!< 0x00000008 */

+#define FDCAN_TTIE_SOGE           FDCAN_TTIE_SOGE_Msk                          /*!<Start of Gap Interrupt Enable                     */

+#define FDCAN_TTIE_RTMIE_Pos      (4U)

+#define FDCAN_TTIE_RTMIE_Msk      (0x1UL << FDCAN_TTIE_RTMIE_Pos)              /*!< 0x00000010 */

+#define FDCAN_TTIE_RTMIE          FDCAN_TTIE_RTMIE_Msk                         /*!<Register Time Mark Interrupt Interrupt Enable     */

+#define FDCAN_TTIE_TTMIE_Pos      (5U)

+#define FDCAN_TTIE_TTMIE_Msk      (0x1UL << FDCAN_TTIE_TTMIE_Pos)              /*!< 0x00000020 */

+#define FDCAN_TTIE_TTMIE          FDCAN_TTIE_TTMIE_Msk                         /*!<Trigger Time Mark Event Internal Interrupt Enable */

+#define FDCAN_TTIE_SWEE_Pos       (6U)

+#define FDCAN_TTIE_SWEE_Msk       (0x1UL << FDCAN_TTIE_SWEE_Pos)               /*!< 0x00000040 */

+#define FDCAN_TTIE_SWEE           FDCAN_TTIE_SWEE_Msk                          /*!<Stop Watch Event Interrupt Enable                 */

+#define FDCAN_TTIE_GTWE_Pos       (7U)

+#define FDCAN_TTIE_GTWE_Msk       (0x1UL << FDCAN_TTIE_GTWE_Pos)               /*!< 0x00000080 */

+#define FDCAN_TTIE_GTWE           FDCAN_TTIE_GTWE_Msk                          /*!<Global Time Wrap Interrupt Enable                 */

+#define FDCAN_TTIE_GTDE_Pos       (8U)

+#define FDCAN_TTIE_GTDE_Msk       (0x1UL << FDCAN_TTIE_GTDE_Pos)               /*!< 0x00000100 */

+#define FDCAN_TTIE_GTDE           FDCAN_TTIE_GTDE_Msk                          /*!<Global Time Discontinuity Interrupt Enable        */

+#define FDCAN_TTIE_GTEE_Pos       (9U)

+#define FDCAN_TTIE_GTEE_Msk       (0x1UL << FDCAN_TTIE_GTEE_Pos)               /*!< 0x00000200 */

+#define FDCAN_TTIE_GTEE           FDCAN_TTIE_GTEE_Msk                          /*!<Global Time Error Interrupt Enable                */

+#define FDCAN_TTIE_TXUE_Pos       (10U)

+#define FDCAN_TTIE_TXUE_Msk       (0x1UL << FDCAN_TTIE_TXUE_Pos)               /*!< 0x00000400 */

+#define FDCAN_TTIE_TXUE           FDCAN_TTIE_TXUE_Msk                          /*!<Tx Count Underflow Interrupt Enable               */

+#define FDCAN_TTIE_TXOE_Pos       (11U)

+#define FDCAN_TTIE_TXOE_Msk       (0x1UL << FDCAN_TTIE_TXOE_Pos)               /*!< 0x00000800 */

+#define FDCAN_TTIE_TXOE           FDCAN_TTIE_TXOE_Msk                          /*!<Tx Count Overflow Interrupt Enable                */

+#define FDCAN_TTIE_SE1E_Pos       (12U)

+#define FDCAN_TTIE_SE1E_Msk       (0x1UL << FDCAN_TTIE_SE1E_Pos)               /*!< 0x00001000 */

+#define FDCAN_TTIE_SE1E           FDCAN_TTIE_SE1E_Msk                          /*!<Scheduling Error 1 Interrupt Enable               */

+#define FDCAN_TTIE_SE2E_Pos       (13U)

+#define FDCAN_TTIE_SE2E_Msk       (0x1UL << FDCAN_TTIE_SE2E_Pos)               /*!< 0x00002000 */

+#define FDCAN_TTIE_SE2E           FDCAN_TTIE_SE2E_Msk                          /*!<Scheduling Error 2 Interrupt Enable               */

+#define FDCAN_TTIE_ELCE_Pos       (14U)

+#define FDCAN_TTIE_ELCE_Msk       (0x1UL << FDCAN_TTIE_ELCE_Pos)               /*!< 0x00004000 */

+#define FDCAN_TTIE_ELCE           FDCAN_TTIE_ELCE_Msk                          /*!<Error Level Changed Interrupt Enable              */

+#define FDCAN_TTIE_IWTE_Pos       (15U)

+#define FDCAN_TTIE_IWTE_Msk       (0x1UL << FDCAN_TTIE_IWTE_Pos)               /*!< 0x00008000 */

+#define FDCAN_TTIE_IWTE           FDCAN_TTIE_IWTE_Msk                          /*!<Initialization Watch Trigger Interrupt Enable     */

+#define FDCAN_TTIE_WTE_Pos        (16U)

+#define FDCAN_TTIE_WTE_Msk        (0x1UL << FDCAN_TTIE_WTE_Pos)                /*!< 0x00010000 */

+#define FDCAN_TTIE_WTE            FDCAN_TTIE_WTE_Msk                           /*!<Watch Trigger Interrupt Enable                    */

+#define FDCAN_TTIE_AWE_Pos        (17U)

+#define FDCAN_TTIE_AWE_Msk        (0x1UL << FDCAN_TTIE_AWE_Pos)                /*!< 0x00020000 */

+#define FDCAN_TTIE_AWE            FDCAN_TTIE_AWE_Msk                           /*!<Application Watchdog Interrupt Enable             */

+#define FDCAN_TTIE_CERE_Pos       (18U)

+#define FDCAN_TTIE_CERE_Msk       (0x1UL << FDCAN_TTIE_CERE_Pos)               /*!< 0x00040000 */

+#define FDCAN_TTIE_CERE           FDCAN_TTIE_CERE_Msk                          /*!<Configuration Error Interrupt Enable              */

+

+/*****************  Bit definition for FDCAN_TTILS register  ********************/

+#define FDCAN_TTILS_SBCS_Pos      (0U)

+#define FDCAN_TTILS_SBCS_Msk      (0x1UL << FDCAN_TTILS_SBCS_Pos)              /*!< 0x00000001 */

+#define FDCAN_TTILS_SBCS          FDCAN_TTILS_SBCS_Msk                         /*!<Start of Basic Cycle Interrupt Line               */

+#define FDCAN_TTILS_SMCS_Pos      (1U)

+#define FDCAN_TTILS_SMCS_Msk      (0x1UL << FDCAN_TTILS_SMCS_Pos)              /*!< 0x00000002 */

+#define FDCAN_TTILS_SMCS          FDCAN_TTILS_SMCS_Msk                         /*!<Start of Matrix Cycle Interrupt Line              */

+#define FDCAN_TTILS_CSMS_Pos      (2U)

+#define FDCAN_TTILS_CSMS_Msk      (0x1UL << FDCAN_TTILS_CSMS_Pos)              /*!< 0x00000004 */

+#define FDCAN_TTILS_CSMS          FDCAN_TTILS_CSMS_Msk                         /*!<Change of Synchronization Mode Interrupt Line     */

+#define FDCAN_TTILS_SOGS_Pos      (3U)

+#define FDCAN_TTILS_SOGS_Msk      (0x1UL << FDCAN_TTILS_SOGS_Pos)              /*!< 0x00000008 */

+#define FDCAN_TTILS_SOGS          FDCAN_TTILS_SOGS_Msk                         /*!<Start of Gap Interrupt Line                       */

+#define FDCAN_TTILS_RTMIS_Pos     (4U)

+#define FDCAN_TTILS_RTMIS_Msk     (0x1UL << FDCAN_TTILS_RTMIS_Pos)             /*!< 0x00000010 */

+#define FDCAN_TTILS_RTMIS         FDCAN_TTILS_RTMIS_Msk                        /*!<Register Time Mark Interrupt Interrupt Line       */

+#define FDCAN_TTILS_TTMIS_Pos     (5U)

+#define FDCAN_TTILS_TTMIS_Msk     (0x1UL << FDCAN_TTILS_TTMIS_Pos)             /*!< 0x00000020 */

+#define FDCAN_TTILS_TTMIS         FDCAN_TTILS_TTMIS_Msk                        /*!<Trigger Time Mark Event Internal Interrupt Line   */

+#define FDCAN_TTILS_SWES_Pos      (6U)

+#define FDCAN_TTILS_SWES_Msk      (0x1UL << FDCAN_TTILS_SWES_Pos)              /*!< 0x00000040 */

+#define FDCAN_TTILS_SWES          FDCAN_TTILS_SWES_Msk                         /*!<Stop Watch Event Interrupt Line                   */

+#define FDCAN_TTILS_GTWS_Pos      (7U)

+#define FDCAN_TTILS_GTWS_Msk      (0x1UL << FDCAN_TTILS_GTWS_Pos)              /*!< 0x00000080 */

+#define FDCAN_TTILS_GTWS          FDCAN_TTILS_GTWS_Msk                         /*!<Global Time Wrap Interrupt Line                   */

+#define FDCAN_TTILS_GTDS_Pos      (8U)

+#define FDCAN_TTILS_GTDS_Msk      (0x1UL << FDCAN_TTILS_GTDS_Pos)              /*!< 0x00000100 */

+#define FDCAN_TTILS_GTDS          FDCAN_TTILS_GTDS_Msk                         /*!<Global Time Discontinuity Interrupt Line          */

+#define FDCAN_TTILS_GTES_Pos      (9U)

+#define FDCAN_TTILS_GTES_Msk      (0x1UL << FDCAN_TTILS_GTES_Pos)              /*!< 0x00000200 */

+#define FDCAN_TTILS_GTES          FDCAN_TTILS_GTES_Msk                         /*!<Global Time Error Interrupt Line                  */

+#define FDCAN_TTILS_TXUS_Pos      (10U)

+#define FDCAN_TTILS_TXUS_Msk      (0x1UL << FDCAN_TTILS_TXUS_Pos)              /*!< 0x00000400 */

+#define FDCAN_TTILS_TXUS          FDCAN_TTILS_TXUS_Msk                         /*!<Tx Count Underflow Interrupt Line                 */

+#define FDCAN_TTILS_TXOS_Pos      (11U)

+#define FDCAN_TTILS_TXOS_Msk      (0x1UL << FDCAN_TTILS_TXOS_Pos)              /*!< 0x00000800 */

+#define FDCAN_TTILS_TXOS          FDCAN_TTILS_TXOS_Msk                         /*!<Tx Count Overflow Interrupt Line                  */

+#define FDCAN_TTILS_SE1S_Pos      (12U)

+#define FDCAN_TTILS_SE1S_Msk      (0x1UL << FDCAN_TTILS_SE1S_Pos)              /*!< 0x00001000 */

+#define FDCAN_TTILS_SE1S          FDCAN_TTILS_SE1S_Msk                         /*!<Scheduling Error 1 Interrupt Line                 */

+#define FDCAN_TTILS_SE2S_Pos      (13U)

+#define FDCAN_TTILS_SE2S_Msk      (0x1UL << FDCAN_TTILS_SE2S_Pos)              /*!< 0x00002000 */

+#define FDCAN_TTILS_SE2S          FDCAN_TTILS_SE2S_Msk                         /*!<Scheduling Error 2 Interrupt Line                 */

+#define FDCAN_TTILS_ELCS_Pos      (14U)

+#define FDCAN_TTILS_ELCS_Msk      (0x1UL << FDCAN_TTILS_ELCS_Pos)              /*!< 0x00004000 */

+#define FDCAN_TTILS_ELCS          FDCAN_TTILS_ELCS_Msk                         /*!<Error Level Changed Interrupt Line                */

+#define FDCAN_TTILS_IWTS_Pos      (15U)

+#define FDCAN_TTILS_IWTS_Msk      (0x1UL << FDCAN_TTILS_IWTS_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTILS_IWTS          FDCAN_TTILS_IWTS_Msk                         /*!<Initialization Watch Trigger Interrupt Line       */

+#define FDCAN_TTILS_WTS_Pos       (16U)

+#define FDCAN_TTILS_WTS_Msk       (0x1UL << FDCAN_TTILS_WTS_Pos)               /*!< 0x00010000 */

+#define FDCAN_TTILS_WTS           FDCAN_TTILS_WTS_Msk                          /*!<Watch Trigger Interrupt Line                      */

+#define FDCAN_TTILS_AWS_Pos       (17U)

+#define FDCAN_TTILS_AWS_Msk       (0x1UL << FDCAN_TTILS_AWS_Pos)               /*!< 0x00020000 */

+#define FDCAN_TTILS_AWS           FDCAN_TTILS_AWS_Msk                          /*!<Application Watchdog Interrupt Line               */

+#define FDCAN_TTILS_CERS_Pos      (18U)

+#define FDCAN_TTILS_CERS_Msk      (0x1UL << FDCAN_TTILS_CERS_Pos)              /*!< 0x00040000 */

+#define FDCAN_TTILS_CERS          FDCAN_TTILS_CERS_Msk                         /*!<Configuration Error Interrupt Line                */

+

+/*****************  Bit definition for FDCAN_TTOST register  ********************/

+#define FDCAN_TTOST_EL_Pos        (0U)

+#define FDCAN_TTOST_EL_Msk        (0x3UL << FDCAN_TTOST_EL_Pos)                /*!< 0x00000003 */

+#define FDCAN_TTOST_EL            FDCAN_TTOST_EL_Msk                           /*!<Error Level                              */

+#define FDCAN_TTOST_MS_Pos        (2U)

+#define FDCAN_TTOST_MS_Msk        (0x3UL << FDCAN_TTOST_MS_Pos)                /*!< 0x0000000C */

+#define FDCAN_TTOST_MS            FDCAN_TTOST_MS_Msk                           /*!<Master State                             */

+#define FDCAN_TTOST_SYS_Pos       (4U)

+#define FDCAN_TTOST_SYS_Msk       (0x3UL << FDCAN_TTOST_SYS_Pos)               /*!< 0x00000030 */

+#define FDCAN_TTOST_SYS           FDCAN_TTOST_SYS_Msk                          /*!<Synchronization State                    */

+#define FDCAN_TTOST_QGTP_Pos      (6U)

+#define FDCAN_TTOST_QGTP_Msk      (0x1UL << FDCAN_TTOST_QGTP_Pos)              /*!< 0x00000040 */

+#define FDCAN_TTOST_QGTP          FDCAN_TTOST_QGTP_Msk                         /*!<Quality of Global Time Phase             */

+#define FDCAN_TTOST_QCS_Pos       (7U)

+#define FDCAN_TTOST_QCS_Msk       (0x1UL << FDCAN_TTOST_QCS_Pos)               /*!< 0x00000080 */

+#define FDCAN_TTOST_QCS           FDCAN_TTOST_QCS_Msk                          /*!<Quality of Clock Speed                   */

+#define FDCAN_TTOST_RTO_Pos       (8U)

+#define FDCAN_TTOST_RTO_Msk       (0xFFUL << FDCAN_TTOST_RTO_Pos)              /*!< 0x0000FF00 */

+#define FDCAN_TTOST_RTO           FDCAN_TTOST_RTO_Msk                          /*!<Reference Trigger Offset                 */

+#define FDCAN_TTOST_WGTD_Pos      (22U)

+#define FDCAN_TTOST_WGTD_Msk      (0x1UL << FDCAN_TTOST_WGTD_Pos)              /*!< 0x00400000 */

+#define FDCAN_TTOST_WGTD          FDCAN_TTOST_WGTD_Msk                         /*!<Wait for Global Time Discontinuity       */

+#define FDCAN_TTOST_GFI_Pos       (23U)

+#define FDCAN_TTOST_GFI_Msk       (0x1UL << FDCAN_TTOST_GFI_Pos)               /*!< 0x00800000 */

+#define FDCAN_TTOST_GFI           FDCAN_TTOST_GFI_Msk                          /*!<Gap Finished Indicator                   */

+#define FDCAN_TTOST_TMP_Pos       (24U)

+#define FDCAN_TTOST_TMP_Msk       (0x7UL << FDCAN_TTOST_TMP_Pos)               /*!< 0x07000000 */

+#define FDCAN_TTOST_TMP           FDCAN_TTOST_TMP_Msk                          /*!<Time Master Priority                     */

+#define FDCAN_TTOST_GSI_Pos       (27U)

+#define FDCAN_TTOST_GSI_Msk       (0x1UL << FDCAN_TTOST_GSI_Pos)               /*!< 0x08000000 */

+#define FDCAN_TTOST_GSI           FDCAN_TTOST_GSI_Msk                          /*!<Gap Started Indicator                    */

+#define FDCAN_TTOST_WFE_Pos       (28U)

+#define FDCAN_TTOST_WFE_Msk       (0x1UL << FDCAN_TTOST_WFE_Pos)               /*!< 0x10000000 */

+#define FDCAN_TTOST_WFE           FDCAN_TTOST_WFE_Msk                          /*!<Wait for Event                           */

+#define FDCAN_TTOST_AWE_Pos       (29U)

+#define FDCAN_TTOST_AWE_Msk       (0x1UL << FDCAN_TTOST_AWE_Pos)               /*!< 0x20000000 */

+#define FDCAN_TTOST_AWE           FDCAN_TTOST_AWE_Msk                          /*!<Application Watchdog Event               */

+#define FDCAN_TTOST_WECS_Pos      (30U)

+#define FDCAN_TTOST_WECS_Msk      (0x1UL << FDCAN_TTOST_WECS_Pos)              /*!< 0x40000000 */

+#define FDCAN_TTOST_WECS          FDCAN_TTOST_WECS_Msk                         /*!<Wait for External Clock Synchronization  */

+#define FDCAN_TTOST_SPL_Pos       (31U)

+#define FDCAN_TTOST_SPL_Msk       (0x1UL << FDCAN_TTOST_SPL_Pos)               /*!< 0x80000000 */

+#define FDCAN_TTOST_SPL           FDCAN_TTOST_SPL_Msk                          /*!<Schedule Phase Lock                      */

+

+/*****************  Bit definition for FDCAN_TURNA register  ********************/

+#define FDCAN_TURNA_NAV_Pos       (0U)

+#define FDCAN_TURNA_NAV_Msk       (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)           /*!< 0x0003FFFF */

+#define FDCAN_TURNA_NAV           FDCAN_TURNA_NAV_Msk                          /*!<Numerator Actual Value                   */

+

+/*****************  Bit definition for FDCAN_TTLGT register  ********************/

+#define FDCAN_TTLGT_LT_Pos        (0U)

+#define FDCAN_TTLGT_LT_Msk        (0xFFFFUL << FDCAN_TTLGT_LT_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTLGT_LT            FDCAN_TTLGT_LT_Msk                           /*!<Local Time                               */

+#define FDCAN_TTLGT_GT_Pos        (16U)

+#define FDCAN_TTLGT_GT_Msk        (0xFFFFUL << FDCAN_TTLGT_GT_Pos)             /*!< 0xFFFF0000 */

+#define FDCAN_TTLGT_GT            FDCAN_TTLGT_GT_Msk                           /*!<Global Time                              */

+

+/*****************  Bit definition for FDCAN_TTCTC register  ********************/

+#define FDCAN_TTCTC_CT_Pos        (0U)

+#define FDCAN_TTCTC_CT_Msk        (0xFFFFUL << FDCAN_TTCTC_CT_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTCTC_CT            FDCAN_TTCTC_CT_Msk                           /*!<Cycle Time                               */

+#define FDCAN_TTCTC_CC_Pos        (16U)

+#define FDCAN_TTCTC_CC_Msk        (0x3FUL << FDCAN_TTCTC_CC_Pos)               /*!< 0x003F0000 */

+#define FDCAN_TTCTC_CC            FDCAN_TTCTC_CC_Msk                           /*!<Cycle Count                              */

+

+/*****************  Bit definition for FDCAN_TTCPT register  ********************/

+#define FDCAN_TTCPT_CCV_Pos       (0U)

+#define FDCAN_TTCPT_CCV_Msk       (0x3FUL << FDCAN_TTCPT_CCV_Pos)              /*!< 0x0000003F */

+#define FDCAN_TTCPT_CCV           FDCAN_TTCPT_CCV_Msk                          /*!<Cycle Count Value                        */

+#define FDCAN_TTCPT_SWV_Pos       (16U)

+#define FDCAN_TTCPT_SWV_Msk       (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)            /*!< 0xFFFF0000 */

+#define FDCAN_TTCPT_SWV           FDCAN_TTCPT_SWV_Msk                          /*!<Stop Watch Value                         */

+

+/*****************  Bit definition for FDCAN_TTCSM register  ********************/

+#define FDCAN_TTCSM_CSM_Pos       (0U)

+#define FDCAN_TTCSM_CSM_Msk       (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)            /*!< 0x0000FFFF */

+#define FDCAN_TTCSM_CSM           FDCAN_TTCSM_CSM_Msk                          /*!<Cycle Sync Mark                          */

+

+/*****************  Bit definition for FDCAN_TTTS register  *********************/

+#define FDCAN_TTTS_SWTSEL_Pos     (0U)

+#define FDCAN_TTTS_SWTSEL_Msk     (0x3UL << FDCAN_TTTS_SWTSEL_Pos)             /*!< 0x00000003 */

+#define FDCAN_TTTS_SWTSEL         FDCAN_TTTS_SWTSEL_Msk                        /*!<Stop watch trigger input selection       */

+#define FDCAN_TTTS_EVTSEL_Pos     (4U)

+#define FDCAN_TTTS_EVTSEL_Msk     (0x3UL << FDCAN_TTTS_EVTSEL_Pos)             /*!< 0x00000030 */

+#define FDCAN_TTTS_EVTSEL         FDCAN_TTTS_EVTSEL_Msk                        /*!<Event trigger input selection            */

+

+/********************************************************************************/

+/*                                                                              */

+/*                      FDCANCCU (Clock Calibration unit)                       */

+/*                                                                              */

+/********************************************************************************/

+

+/*****************  Bit definition for FDCANCCU_CREL register  ******************/

+#define FDCANCCU_CREL_DAY_Pos        (0U)

+#define FDCANCCU_CREL_DAY_Msk        (0xFFUL << FDCANCCU_CREL_DAY_Pos)         /*!< 0x000000FF */

+#define FDCANCCU_CREL_DAY            FDCANCCU_CREL_DAY_Msk                     /*!<Timestamp Day                           */

+#define FDCANCCU_CREL_MON_Pos        (8U)

+#define FDCANCCU_CREL_MON_Msk        (0xFFUL << FDCANCCU_CREL_MON_Pos)         /*!< 0x0000FF00 */

+#define FDCANCCU_CREL_MON            FDCANCCU_CREL_MON_Msk                     /*!<Timestamp Month                         */

+#define FDCANCCU_CREL_YEAR_Pos       (16U)

+#define FDCANCCU_CREL_YEAR_Msk       (0xFUL << FDCANCCU_CREL_YEAR_Pos)         /*!< 0x000F0000 */

+#define FDCANCCU_CREL_YEAR           FDCANCCU_CREL_YEAR_Msk                    /*!<Timestamp Year                          */

+#define FDCANCCU_CREL_SUBSTEP_Pos    (20U)

+#define FDCANCCU_CREL_SUBSTEP_Msk    (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)      /*!< 0x00F00000 */

+#define FDCANCCU_CREL_SUBSTEP        FDCANCCU_CREL_SUBSTEP_Msk                 /*!<Sub-step of Core release                */

+#define FDCANCCU_CREL_STEP_Pos       (24U)

+#define FDCANCCU_CREL_STEP_Msk       (0xFUL << FDCANCCU_CREL_STEP_Pos)         /*!< 0x0F000000 */

+#define FDCANCCU_CREL_STEP           FDCANCCU_CREL_STEP_Msk                    /*!<Step of Core release                    */

+#define FDCANCCU_CREL_REL_Pos        (28U)

+#define FDCANCCU_CREL_REL_Msk        (0xFUL << FDCANCCU_CREL_REL_Pos)          /*!< 0xF0000000 */

+#define FDCANCCU_CREL_REL            FDCANCCU_CREL_REL_Msk                     /*!<Core release                            */

+

+/*****************  Bit definition for FDCANCCU_CCFG register  ******************/

+#define FDCANCCU_CCFG_TQBT_Pos       (0U)

+#define FDCANCCU_CCFG_TQBT_Msk       (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)        /*!< 0x0000001F */

+#define FDCANCCU_CCFG_TQBT           FDCANCCU_CCFG_TQBT_Msk                    /*!<Time Quanta per Bit Time                */

+#define FDCANCCU_CCFG_BCC_Pos        (6U)

+#define FDCANCCU_CCFG_BCC_Msk        (0x1UL << FDCANCCU_CCFG_BCC_Pos)          /*!< 0x00000040 */

+#define FDCANCCU_CCFG_BCC            FDCANCCU_CCFG_BCC_Msk                     /*!<Bypass Clock Calibration                */

+#define FDCANCCU_CCFG_CFL_Pos        (7U)

+#define FDCANCCU_CCFG_CFL_Msk        (0x1UL << FDCANCCU_CCFG_CFL_Pos)          /*!< 0x00000080 */

+#define FDCANCCU_CCFG_CFL            FDCANCCU_CCFG_CFL_Msk                     /*!<Calibration Field Length                */

+#define FDCANCCU_CCFG_OCPM_Pos       (8U)

+#define FDCANCCU_CCFG_OCPM_Msk       (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)        /*!< 0x0000FF00 */

+#define FDCANCCU_CCFG_OCPM           FDCANCCU_CCFG_OCPM_Msk                    /*!<Oscillator Clock Periods Minimum        */

+#define FDCANCCU_CCFG_CDIV_Pos       (16U)

+#define FDCANCCU_CCFG_CDIV_Msk       (0xFUL << FDCANCCU_CCFG_CDIV_Pos)         /*!< 0x000F0000 */

+#define FDCANCCU_CCFG_CDIV           FDCANCCU_CCFG_CDIV_Msk                    /*!<Clock Divider                           */

+#define FDCANCCU_CCFG_SWR_Pos        (31U)

+#define FDCANCCU_CCFG_SWR_Msk        (0x1UL << FDCANCCU_CCFG_SWR_Pos)          /*!< 0x80000000 */

+#define FDCANCCU_CCFG_SWR            FDCANCCU_CCFG_SWR_Msk                     /*!<Software Reset                          */

+

+/*****************  Bit definition for FDCANCCU_CSTAT register  *****************/

+#define FDCANCCU_CSTAT_OCPC_Pos      (0U)

+#define FDCANCCU_CSTAT_OCPC_Msk      (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)    /*!< 0x0003FFFF */

+#define FDCANCCU_CSTAT_OCPC          FDCANCCU_CSTAT_OCPC_Msk                   /*!<Oscillator Clock Period Counter        */

+#define FDCANCCU_CSTAT_TQC_Pos       (18U)

+#define FDCANCCU_CSTAT_TQC_Msk       (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)       /*!< 0x1FFC0000 */

+#define FDCANCCU_CSTAT_TQC           FDCANCCU_CSTAT_TQC_Msk                    /*!<Time Quanta Counter                    */

+#define FDCANCCU_CSTAT_CALS_Pos      (30U)

+#define FDCANCCU_CSTAT_CALS_Msk      (0x3UL << FDCANCCU_CSTAT_CALS_Pos)        /*!< 0xC0000000 */

+#define FDCANCCU_CSTAT_CALS          FDCANCCU_CSTAT_CALS_Msk                   /*!<Calibration State                      */

+

+/******************  Bit definition for FDCANCCU_CWD register  ******************/

+#define FDCANCCU_CWD_WDC_Pos         (0U)

+#define FDCANCCU_CWD_WDC_Msk         (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)        /*!< 0x0000FFFF */

+#define FDCANCCU_CWD_WDC             FDCANCCU_CWD_WDC_Msk                      /*!<Watchdog Configuration                 */

+#define FDCANCCU_CWD_WDV_Pos         (16U)

+#define FDCANCCU_CWD_WDV_Msk         (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)        /*!< 0xFFFF0000 */

+#define FDCANCCU_CWD_WDV             FDCANCCU_CWD_WDV_Msk                      /*!<Watchdog Value                         */

+

+/******************  Bit definition for FDCANCCU_IR register  *******************/

+#define FDCANCCU_IR_CWE_Pos          (0U)

+#define FDCANCCU_IR_CWE_Msk          (0x1UL << FDCANCCU_IR_CWE_Pos)            /*!< 0x00000001 */

+#define FDCANCCU_IR_CWE              FDCANCCU_IR_CWE_Msk                       /*!<Calibration Watchdog Event             */

+#define FDCANCCU_IR_CSC_Pos          (1U)

+#define FDCANCCU_IR_CSC_Msk          (0x1UL << FDCANCCU_IR_CSC_Pos)            /*!< 0x00000002 */

+#define FDCANCCU_IR_CSC              FDCANCCU_IR_CSC_Msk                       /*!<Calibration State Changed              */

+

+/******************  Bit definition for FDCANCCU_IE register  *******************/

+#define FDCANCCU_IE_CWEE_Pos         (0U)

+#define FDCANCCU_IE_CWEE_Msk         (0x1UL << FDCANCCU_IE_CWEE_Pos)           /*!< 0x00000001 */

+#define FDCANCCU_IE_CWEE             FDCANCCU_IE_CWEE_Msk                      /*!<Calibration Watchdog Event Enable      */

+#define FDCANCCU_IE_CSCE_Pos         (1U)

+#define FDCANCCU_IE_CSCE_Msk         (0x1UL << FDCANCCU_IE_CSCE_Pos)           /*!< 0x00000002 */

+#define FDCANCCU_IE_CSCE             FDCANCCU_IE_CSCE_Msk                      /*!<Calibration State Changed Enable       */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          HDMI-CEC (CEC)                                    */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for CEC_CR register  *********************/

+#define CEC_CR_CECEN_Pos         (0U)

+#define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                   /*!< 0x00000001 */

+#define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                                */

+#define CEC_CR_TXSOM_Pos         (1U)

+#define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                   /*!< 0x00000002 */

+#define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message                   */

+#define CEC_CR_TXEOM_Pos         (2U)

+#define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                   /*!< 0x00000004 */

+#define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message                     */

+

+/*******************  Bit definition for CEC_CFGR register  *******************/

+#define CEC_CFGR_SFT_Pos         (0U)

+#define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                   /*!< 0x00000007 */

+#define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time                      */

+#define CEC_CFGR_RXTOL_Pos       (3U)

+#define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                 /*!< 0x00000008 */

+#define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                             */

+#define CEC_CFGR_BRESTP_Pos      (4U)

+#define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                /*!< 0x00000010 */

+#define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                               */

+#define CEC_CFGR_BREGEN_Pos      (5U)

+#define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                /*!< 0x00000020 */

+#define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation           */

+#define CEC_CFGR_LBPEGEN_Pos     (6U)

+#define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)               /*!< 0x00000040 */

+#define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error generation      */

+#define CEC_CFGR_SFTOPT_Pos      (8U)

+#define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                /*!< 0x00000100 */

+#define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional             */

+#define CEC_CFGR_BRDNOGEN_Pos    (7U)

+#define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)              /*!< 0x00000080 */

+#define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No error generation         */

+#define CEC_CFGR_OAR_Pos         (16U)

+#define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                /*!< 0x7FFF0000 */

+#define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                           */

+#define CEC_CFGR_LSTN_Pos        (31U)

+#define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                  /*!< 0x80000000 */

+#define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                           */

+

+/*******************  Bit definition for CEC_TXDR register  *******************/

+#define CEC_TXDR_TXD_Pos         (0U)

+#define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                  /*!< 0x000000FF */

+#define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                               */

+

+/*******************  Bit definition for CEC_RXDR register  *******************/

+#define CEC_RXDR_RXD_Pos         (0U)

+#define CEC_RXDR_RXD_Msk         (0xFFUL << CEC_RXDR_RXD_Pos)                  /*!< 0x000000FF */

+#define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                              /*!< CEC Rx Data                               */

+

+/*******************  Bit definition for CEC_ISR register  ********************/

+#define CEC_ISR_RXBR_Pos         (0U)

+#define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                   /*!< 0x00000001 */

+#define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                      */

+#define CEC_ISR_RXEND_Pos        (1U)

+#define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                  /*!< 0x00000002 */

+#define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                      */

+#define CEC_ISR_RXOVR_Pos        (2U)

+#define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                  /*!< 0x00000004 */

+#define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                            */

+#define CEC_ISR_BRE_Pos          (3U)

+#define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                    /*!< 0x00000008 */

+#define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                   */

+#define CEC_ISR_SBPE_Pos         (4U)

+#define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                   /*!< 0x00000010 */

+#define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error             */

+#define CEC_ISR_LBPE_Pos         (5U)

+#define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                   /*!< 0x00000020 */

+#define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error              */

+#define CEC_ISR_RXACKE_Pos       (6U)

+#define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                 /*!< 0x00000040 */

+#define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge                */

+#define CEC_ISR_ARBLST_Pos       (7U)

+#define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                 /*!< 0x00000080 */

+#define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                      */

+#define CEC_ISR_TXBR_Pos         (8U)

+#define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                   /*!< 0x00000100 */

+#define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                       */

+#define CEC_ISR_TXEND_Pos        (9U)

+#define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                  /*!< 0x00000200 */

+#define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                   */

+#define CEC_ISR_TXUDR_Pos        (10U)

+#define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                  /*!< 0x00000400 */

+#define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                    */

+#define CEC_ISR_TXERR_Pos        (11U)

+#define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                  /*!< 0x00000800 */

+#define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                              */

+#define CEC_ISR_TXACKE_Pos       (12U)

+#define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                 /*!< 0x00001000 */

+#define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge                */

+

+/*******************  Bit definition for CEC_IER register  ********************/

+#define CEC_IER_RXBRIE_Pos       (0U)

+#define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                 /*!< 0x00000001 */

+#define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable            */

+#define CEC_IER_RXENDIE_Pos      (1U)

+#define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                /*!< 0x00000002 */

+#define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable            */

+#define CEC_IER_RXOVRIE_Pos      (2U)

+#define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                /*!< 0x00000004 */

+#define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable                  */

+#define CEC_IER_BREIE_Pos        (3U)

+#define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                  /*!< 0x00000008 */

+#define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable         */

+#define CEC_IER_SBPEIE_Pos       (4U)

+#define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                 /*!< 0x00000010 */

+#define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable   */

+#define CEC_IER_LBPEIE_Pos       (5U)

+#define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                 /*!< 0x00000020 */

+#define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable    */

+#define CEC_IER_RXACKEIE_Pos     (6U)

+#define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)               /*!< 0x00000040 */

+#define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable      */

+#define CEC_IER_ARBLSTIE_Pos     (7U)

+#define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)               /*!< 0x00000080 */

+#define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable            */

+#define CEC_IER_TXBRIE_Pos       (8U)

+#define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                 /*!< 0x00000100 */

+#define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable            */

+#define CEC_IER_TXENDIE_Pos      (9U)

+#define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                /*!< 0x00000200 */

+#define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable         */

+#define CEC_IER_TXUDRIE_Pos      (10U)

+#define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                /*!< 0x00000400 */

+#define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable          */

+#define CEC_IER_TXERRIE_Pos      (11U)

+#define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                /*!< 0x00000800 */

+#define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                    */

+#define CEC_IER_TXACKEIE_Pos     (12U)

+#define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)               /*!< 0x00001000 */

+#define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable      */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          CRC calculation unit                              */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for CRC_DR register  *********************/

+#define CRC_DR_DR_Pos            (0U)

+#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */

+#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */

+

+/*******************  Bit definition for CRC_IDR register  ********************/

+#define CRC_IDR_IDR_Pos          (0U)

+#define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */

+#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */

+

+/********************  Bit definition for CRC_CR register  ********************/

+#define CRC_CR_RESET_Pos         (0U)

+#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */

+#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */

+#define CRC_CR_POLYSIZE_Pos      (3U)

+#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */

+#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */

+#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */

+#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */

+#define CRC_CR_REV_IN_Pos        (5U)

+#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */

+#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */

+#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */

+#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */

+#define CRC_CR_REV_OUT_Pos       (7U)

+#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */

+#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */

+

+/*******************  Bit definition for CRC_INIT register  *******************/

+#define CRC_INIT_INIT_Pos        (0U)

+#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */

+#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */

+

+/*******************  Bit definition for CRC_POL register  ********************/

+#define CRC_POL_POL_Pos          (0U)

+#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */

+#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          CRS Clock Recovery System                         */

+/******************************************************************************/

+

+/*******************  Bit definition for CRS_CR register  *********************/

+#define CRS_CR_SYNCOKIE_Pos       (0U)

+#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */

+#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */

+#define CRS_CR_SYNCWARNIE_Pos     (1U)

+#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */

+#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */

+#define CRS_CR_ERRIE_Pos          (2U)

+#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */

+#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */

+#define CRS_CR_ESYNCIE_Pos        (3U)

+#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */

+#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */

+#define CRS_CR_CEN_Pos            (5U)

+#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */

+#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */

+#define CRS_CR_AUTOTRIMEN_Pos     (6U)

+#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */

+#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */

+#define CRS_CR_SWSYNC_Pos         (7U)

+#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */

+#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */

+#define CRS_CR_TRIM_Pos           (8U)

+#define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00003F00 */

+#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */

+

+/*******************  Bit definition for CRS_CFGR register  *********************/

+#define CRS_CFGR_RELOAD_Pos       (0U)

+#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */

+#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */

+#define CRS_CFGR_FELIM_Pos        (16U)

+#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */

+#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */

+

+#define CRS_CFGR_SYNCDIV_Pos      (24U)

+#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */

+#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */

+#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */

+#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */

+#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */

+

+#define CRS_CFGR_SYNCSRC_Pos      (28U)

+#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */

+#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */

+#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */

+#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */

+

+#define CRS_CFGR_SYNCPOL_Pos      (31U)

+#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */

+#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */

+

+/*******************  Bit definition for CRS_ISR register  *********************/

+#define CRS_ISR_SYNCOKF_Pos       (0U)

+#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */

+#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */

+#define CRS_ISR_SYNCWARNF_Pos     (1U)

+#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */

+#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */

+#define CRS_ISR_ERRF_Pos          (2U)

+#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */

+#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */

+#define CRS_ISR_ESYNCF_Pos        (3U)

+#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */

+#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */

+#define CRS_ISR_SYNCERR_Pos       (8U)

+#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */

+#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */

+#define CRS_ISR_SYNCMISS_Pos      (9U)

+#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */

+#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */

+#define CRS_ISR_TRIMOVF_Pos       (10U)

+#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */

+#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */

+#define CRS_ISR_FEDIR_Pos         (15U)

+#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */

+#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */

+#define CRS_ISR_FECAP_Pos         (16U)

+#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */

+#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */

+

+/*******************  Bit definition for CRS_ICR register  *********************/

+#define CRS_ICR_SYNCOKC_Pos       (0U)

+#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */

+#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */

+#define CRS_ICR_SYNCWARNC_Pos     (1U)

+#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */

+#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */

+#define CRS_ICR_ERRC_Pos          (2U)

+#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */

+#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */

+#define CRS_ICR_ESYNCC_Pos        (3U)

+#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */

+#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      Digital to Analog Converter                           */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for DAC_CR register  ********************/

+#define DAC_CR_EN1_Pos              (0U)

+#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */

+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */

+#define DAC_CR_TEN1_Pos             (1U)

+#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */

+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */

+

+#define DAC_CR_TSEL1_Pos            (2U)

+#define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */

+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */

+#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000004 */

+#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */

+#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */

+#define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */

+

+

+#define DAC_CR_WAVE1_Pos            (6U)

+#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */

+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */

+#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */

+#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */

+

+#define DAC_CR_MAMP1_Pos            (8U)

+#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */

+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */

+#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */

+#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */

+#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */

+#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */

+

+#define DAC_CR_DMAEN1_Pos           (12U)

+#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */

+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */

+#define DAC_CR_DMAUDRIE1_Pos        (13U)

+#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */

+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/

+#define DAC_CR_CEN1_Pos             (14U)

+#define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */

+#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/

+

+#define DAC_CR_EN2_Pos              (16U)

+#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */

+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */

+#define DAC_CR_TEN2_Pos             (17U)

+#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */

+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */

+

+#define DAC_CR_TSEL2_Pos            (18U)

+#define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */

+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */

+#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00040000 */

+#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */

+#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */

+#define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */

+

+

+#define DAC_CR_WAVE2_Pos            (22U)

+#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */

+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */

+#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */

+#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */

+

+#define DAC_CR_MAMP2_Pos            (24U)

+#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */

+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */

+#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */

+#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */

+#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */

+#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */

+

+#define DAC_CR_DMAEN2_Pos           (28U)

+#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */

+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */

+#define DAC_CR_DMAUDRIE2_Pos        (29U)

+#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */

+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/

+#define DAC_CR_CEN2_Pos             (30U)

+#define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */

+#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/

+

+/*****************  Bit definition for DAC_SWTRIGR register  ******************/

+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)

+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */

+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */

+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)

+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */

+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */

+

+/*****************  Bit definition for DAC_DHR12R1 register  ******************/

+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)

+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12L1 register  ******************/

+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)

+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8R1 register  ******************/

+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)

+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12R2 register  ******************/

+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)

+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12L2 register  ******************/

+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)

+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8R2 register  ******************/

+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)

+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12RD register  ******************/

+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)

+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */

+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)

+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */

+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12LD register  ******************/

+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)

+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */

+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)

+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */

+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8RD register  ******************/

+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)

+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */

+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)

+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */

+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */

+

+/*******************  Bit definition for DAC_DOR1 register  *******************/

+#define DAC_DOR1_DACC1DOR_Pos       (0U)

+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */

+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */

+

+/*******************  Bit definition for DAC_DOR2 register  *******************/

+#define DAC_DOR2_DACC2DOR_Pos       (0U)

+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */

+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */

+

+/********************  Bit definition for DAC_SR register  ********************/

+#define DAC_SR_DMAUDR1_Pos          (13U)

+#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */

+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */

+#define DAC_SR_CAL_FLAG1_Pos        (14U)

+#define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */

+#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */

+#define DAC_SR_BWST1_Pos            (15U)

+#define DAC_SR_BWST1_Msk            (0x4001UL << DAC_SR_BWST1_Pos)             /*!< 0x20008000 */

+#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */

+

+#define DAC_SR_DMAUDR2_Pos          (29U)

+#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */

+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */

+#define DAC_SR_CAL_FLAG2_Pos        (30U)

+#define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */

+#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */

+#define DAC_SR_BWST2_Pos            (31U)

+#define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */

+#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */

+

+/*******************  Bit definition for DAC_CCR register  ********************/

+#define DAC_CCR_OTRIM1_Pos          (0U)

+#define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */

+#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */

+#define DAC_CCR_OTRIM2_Pos          (16U)

+#define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */

+#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */

+

+/*******************  Bit definition for DAC_MCR register  *******************/

+#define DAC_MCR_MODE1_Pos           (0U)

+#define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */

+#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */

+#define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */

+#define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */

+#define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */

+

+#define DAC_MCR_MODE2_Pos           (16U)

+#define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */

+#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */

+#define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */

+#define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */

+#define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */

+

+/******************  Bit definition for DAC_SHSR1 register  ******************/

+#define DAC_SHSR1_TSAMPLE1_Pos      (0U)

+#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */

+#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */

+

+/******************  Bit definition for DAC_SHSR2 register  ******************/

+#define DAC_SHSR2_TSAMPLE2_Pos      (0U)

+#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */

+#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */

+

+/******************  Bit definition for DAC_SHHR register  ******************/

+#define DAC_SHHR_THOLD1_Pos         (0U)

+#define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */

+#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */

+#define DAC_SHHR_THOLD2_Pos         (16U)

+#define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */

+#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */

+

+/******************  Bit definition for DAC_SHRR register  ******************/

+#define DAC_SHRR_TREFRESH1_Pos      (0U)

+#define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */

+#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */

+#define DAC_SHRR_TREFRESH2_Pos      (16U)

+#define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */

+#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    DCMI                                    */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DCMI_CR register  ******************/

+#define DCMI_CR_CAPTURE_Pos        (0U)

+#define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)              /*!< 0x00000001 */

+#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk

+#define DCMI_CR_CM_Pos             (1U)

+#define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                   /*!< 0x00000002 */

+#define DCMI_CR_CM                 DCMI_CR_CM_Msk

+#define DCMI_CR_CROP_Pos           (2U)

+#define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                 /*!< 0x00000004 */

+#define DCMI_CR_CROP               DCMI_CR_CROP_Msk

+#define DCMI_CR_JPEG_Pos           (3U)

+#define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                 /*!< 0x00000008 */

+#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk

+#define DCMI_CR_ESS_Pos            (4U)

+#define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                  /*!< 0x00000010 */

+#define DCMI_CR_ESS                DCMI_CR_ESS_Msk

+#define DCMI_CR_PCKPOL_Pos         (5U)

+#define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)               /*!< 0x00000020 */

+#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk

+#define DCMI_CR_HSPOL_Pos          (6U)

+#define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                /*!< 0x00000040 */

+#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk

+#define DCMI_CR_VSPOL_Pos          (7U)

+#define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */

+#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk

+#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)

+#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)

+#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)

+#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)

+#define DCMI_CR_CRE_Pos            (12U)

+#define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */

+#define DCMI_CR_CRE                DCMI_CR_CRE_Msk

+#define DCMI_CR_ENABLE_Pos         (14U)

+#define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)               /*!< 0x00004000 */

+#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk

+#define DCMI_CR_BSM_Pos            (16U)

+#define DCMI_CR_BSM_Msk            (0x3UL << DCMI_CR_BSM_Pos)                  /*!< 0x00030000 */

+#define DCMI_CR_BSM                DCMI_CR_BSM_Msk

+#define DCMI_CR_BSM_0              (0x1UL << DCMI_CR_BSM_Pos)                   /*!< 0x00010000 */

+#define DCMI_CR_BSM_1              (0x2UL << DCMI_CR_BSM_Pos)                   /*!< 0x00020000 */

+#define DCMI_CR_OEBS_Pos           (18U)

+#define DCMI_CR_OEBS_Msk           (0x1UL << DCMI_CR_OEBS_Pos)                 /*!< 0x00040000 */

+#define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk

+#define DCMI_CR_LSM_Pos            (19U)

+#define DCMI_CR_LSM_Msk            (0x1UL << DCMI_CR_LSM_Pos)                  /*!< 0x00080000 */

+#define DCMI_CR_LSM                DCMI_CR_LSM_Msk

+#define DCMI_CR_OELS_Pos           (20U)

+#define DCMI_CR_OELS_Msk           (0x1UL << DCMI_CR_OELS_Pos)                 /*!< 0x00100000 */

+#define DCMI_CR_OELS               DCMI_CR_OELS_Msk

+

+/********************  Bits definition for DCMI_SR register  ******************/

+#define DCMI_SR_HSYNC_Pos          (0U)

+#define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                /*!< 0x00000001 */

+#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk

+#define DCMI_SR_VSYNC_Pos          (1U)

+#define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                /*!< 0x00000002 */

+#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk

+#define DCMI_SR_FNE_Pos            (2U)

+#define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                  /*!< 0x00000004 */

+#define DCMI_SR_FNE                DCMI_SR_FNE_Msk

+

+/********************  Bits definition for DCMI_RIS register   ****************/

+#define DCMI_RIS_FRAME_RIS_Pos     (0U)

+#define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)           /*!< 0x00000001 */

+#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk

+#define DCMI_RIS_OVR_RIS_Pos       (1U)

+#define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)             /*!< 0x00000002 */

+#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk

+#define DCMI_RIS_ERR_RIS_Pos       (2U)

+#define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)             /*!< 0x00000004 */

+#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk

+#define DCMI_RIS_VSYNC_RIS_Pos     (3U)

+#define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)           /*!< 0x00000008 */

+#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk

+#define DCMI_RIS_LINE_RIS_Pos      (4U)

+#define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)            /*!< 0x00000010 */

+#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk

+

+/********************  Bits definition for DCMI_IER register  *****************/

+#define DCMI_IER_FRAME_IE_Pos      (0U)

+#define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)            /*!< 0x00000001 */

+#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk

+#define DCMI_IER_OVR_IE_Pos        (1U)

+#define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)              /*!< 0x00000002 */

+#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk

+#define DCMI_IER_ERR_IE_Pos        (2U)

+#define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)              /*!< 0x00000004 */

+#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk

+#define DCMI_IER_VSYNC_IE_Pos      (3U)

+#define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)            /*!< 0x00000008 */

+#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk

+#define DCMI_IER_LINE_IE_Pos       (4U)

+#define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)             /*!< 0x00000010 */

+#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk

+

+

+/********************  Bits definition for DCMI_MIS register  *****************/

+#define DCMI_MIS_FRAME_MIS_Pos     (0U)

+#define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)           /*!< 0x00000001 */

+#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk

+#define DCMI_MIS_OVR_MIS_Pos       (1U)

+#define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)             /*!< 0x00000002 */

+#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk

+#define DCMI_MIS_ERR_MIS_Pos       (2U)

+#define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)             /*!< 0x00000004 */

+#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk

+#define DCMI_MIS_VSYNC_MIS_Pos     (3U)

+#define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)           /*!< 0x00000008 */

+#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk

+#define DCMI_MIS_LINE_MIS_Pos      (4U)

+#define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)            /*!< 0x00000010 */

+#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk

+

+

+/********************  Bits definition for DCMI_ICR register  *****************/

+#define DCMI_ICR_FRAME_ISC_Pos     (0U)

+#define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)           /*!< 0x00000001 */

+#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk

+#define DCMI_ICR_OVR_ISC_Pos       (1U)

+#define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)             /*!< 0x00000002 */

+#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk

+#define DCMI_ICR_ERR_ISC_Pos       (2U)

+#define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)             /*!< 0x00000004 */

+#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk

+#define DCMI_ICR_VSYNC_ISC_Pos     (3U)

+#define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)           /*!< 0x00000008 */

+#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk

+#define DCMI_ICR_LINE_ISC_Pos      (4U)

+#define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)            /*!< 0x00000010 */

+#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk

+

+

+/********************  Bits definition for DCMI_ESCR register  ******************/

+#define DCMI_ESCR_FSC_Pos          (0U)

+#define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)               /*!< 0x000000FF */

+#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk

+#define DCMI_ESCR_LSC_Pos          (8U)

+#define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)               /*!< 0x0000FF00 */

+#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk

+#define DCMI_ESCR_LEC_Pos          (16U)

+#define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)               /*!< 0x00FF0000 */

+#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk

+#define DCMI_ESCR_FEC_Pos          (24U)

+#define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)               /*!< 0xFF000000 */

+#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk

+

+/********************  Bits definition for DCMI_ESUR register  ******************/

+#define DCMI_ESUR_FSU_Pos          (0U)

+#define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)               /*!< 0x000000FF */

+#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk

+#define DCMI_ESUR_LSU_Pos          (8U)

+#define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)               /*!< 0x0000FF00 */

+#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk

+#define DCMI_ESUR_LEU_Pos          (16U)

+#define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)               /*!< 0x00FF0000 */

+#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk

+#define DCMI_ESUR_FEU_Pos          (24U)

+#define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)               /*!< 0xFF000000 */

+#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk

+

+/********************  Bits definition for DCMI_CWSTRT register  ******************/

+#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)

+#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)       /*!< 0x00003FFF */

+#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk

+#define DCMI_CWSTRT_VST_Pos        (16U)

+#define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)           /*!< 0x1FFF0000 */

+#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk

+

+/********************  Bits definition for DCMI_CWSIZE register  ******************/

+#define DCMI_CWSIZE_CAPCNT_Pos     (0U)

+#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)        /*!< 0x00003FFF */

+#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk

+#define DCMI_CWSIZE_VLINE_Pos      (16U)

+#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)         /*!< 0x3FFF0000 */

+#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk

+

+/********************  Bits definition for DCMI_DR register  ******************/

+#define DCMI_DR_BYTE0_Pos          (0U)

+#define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)               /*!< 0x000000FF */

+#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk

+#define DCMI_DR_BYTE1_Pos          (8U)

+#define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)               /*!< 0x0000FF00 */

+#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk

+#define DCMI_DR_BYTE2_Pos          (16U)

+#define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)               /*!< 0x00FF0000 */

+#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk

+#define DCMI_DR_BYTE3_Pos          (24U)

+#define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)               /*!< 0xFF000000 */

+#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                 Digital Filter for Sigma Delta Modulators                  */

+/*                                                                            */

+/******************************************************************************/

+

+/****************   DFSDM channel configuration registers  ********************/

+

+/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/

+#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)

+#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)   /*!< 0x80000000 */

+#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */

+#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)

+#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)  /*!< 0x40000000 */

+#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */

+#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)

+#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */

+#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */

+#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)

+#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x0000C000 */

+#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */

+#define DFSDM_CHCFGR1_DATPACK_1         (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */

+#define DFSDM_CHCFGR1_DATPACK_0         (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */

+#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)

+#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00003000 */

+#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */

+#define DFSDM_CHCFGR1_DATMPX_1          (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */

+#define DFSDM_CHCFGR1_DATMPX_0          (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */

+#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)

+#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)   /*!< 0x00000100 */

+#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */

+#define DFSDM_CHCFGR1_CHEN_Pos          (7U)

+#define DFSDM_CHCFGR1_CHEN_Msk          (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)      /*!< 0x00000080 */

+#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */

+#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)

+#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)    /*!< 0x00000040 */

+#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */

+#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)

+#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)     /*!< 0x00000020 */

+#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */

+#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)

+#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x0000000C */

+#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */

+#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */

+#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */

+#define DFSDM_CHCFGR1_SITP_Pos          (0U)

+#define DFSDM_CHCFGR1_SITP_Msk          (0x3UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000003 */

+#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */

+#define DFSDM_CHCFGR1_SITP_1            (0x2UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */

+#define DFSDM_CHCFGR1_SITP_0            (0x1UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */

+

+/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/

+#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)

+#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */

+#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)

+#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)    /*!< 0x000000F8 */

+#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */

+

+/******************  Bit definition for DFSDM_CHAWSCDR register *****************/

+#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)

+#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00C00000 */

+#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */

+#define DFSDM_CHAWSCDR_AWFORD_1         (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */

+#define DFSDM_CHAWSCDR_AWFORD_0         (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */

+#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)

+#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)  /*!< 0x001F0000 */

+#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */

+#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)

+#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)    /*!< 0x0000F000 */

+#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */

+#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)

+#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)    /*!< 0x000000FF */

+#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */

+

+/****************  Bit definition for DFSDM_CHWDATR register *******************/

+#define DFSDM_CHWDATR_WDATA_Pos         (0U)

+#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)  /*!< 0x0000FFFF */

+#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */

+

+/****************  Bit definition for DFSDM_CHDATINR register *****************/

+#define DFSDM_CHDATINR_INDAT0_Pos       (0U)

+#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */

+#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */

+#define DFSDM_CHDATINR_INDAT1_Pos       (16U)

+#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */

+#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */

+

+/****************  Bit definition for DFSDM_CHDLYR register *****************/

+#define DFSDM_CHDLYR_PLSSKP_Pos         (0U)

+#define DFSDM_CHDLYR_PLSSKP_Msk         (0x3FUL << DFSDM_CHDLYR_PLSSKP_Pos)    /*!< 0x0000003F*/

+#define DFSDM_CHDLYR_PLSSKP             DFSDM_CHDLYR_PLSSKP_Msk

+/************************   DFSDM module registers  ****************************/

+

+/********************  Bit definition for DFSDM_FLTCR1 register *******************/

+#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)

+#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)     /*!< 0x40000000 */

+#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */

+#define DFSDM_FLTCR1_FAST_Pos           (29U)

+#define DFSDM_FLTCR1_FAST_Msk           (0x1UL << DFSDM_FLTCR1_FAST_Pos)       /*!< 0x20000000 */

+#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */

+#define DFSDM_FLTCR1_RCH_Pos            (24U)

+#define DFSDM_FLTCR1_RCH_Msk            (0x7UL << DFSDM_FLTCR1_RCH_Pos)        /*!< 0x07000000 */

+#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */

+#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)

+#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)     /*!< 0x00200000 */

+#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */

+#define DFSDM_FLTCR1_RSYNC_Pos          (19U)

+#define DFSDM_FLTCR1_RSYNC_Msk          (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)      /*!< 0x00080000 */

+#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */

+#define DFSDM_FLTCR1_RCONT_Pos          (18U)

+#define DFSDM_FLTCR1_RCONT_Msk          (0x1UL << DFSDM_FLTCR1_RCONT_Pos)      /*!< 0x00040000 */

+#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */

+#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)

+#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)   /*!< 0x00020000 */

+#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */

+#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)

+#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00006000 */

+#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */

+#define DFSDM_FLTCR1_JEXTEN_1           (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */

+#define DFSDM_FLTCR1_JEXTEN_0           (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */

+#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)

+#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)   /*!< 0x00001F00 */

+#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */

+#define DFSDM_FLTCR1_JEXTSEL_0          (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000100 */

+#define DFSDM_FLTCR1_JEXTSEL_1          (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000200 */

+#define DFSDM_FLTCR1_JEXTSEL_2          (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000400 */

+#define DFSDM_FLTCR1_JEXTSEL_3          (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000800 */

+#define DFSDM_FLTCR1_JEXTSEL_4          (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00001000 */

+

+#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)

+#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)     /*!< 0x00000020 */

+#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */

+#define DFSDM_FLTCR1_JSCAN_Pos          (4U)

+#define DFSDM_FLTCR1_JSCAN_Msk          (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)      /*!< 0x00000010 */

+#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */

+#define DFSDM_FLTCR1_JSYNC_Pos          (3U)

+#define DFSDM_FLTCR1_JSYNC_Msk          (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)      /*!< 0x00000008 */

+#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */

+#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)

+#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)   /*!< 0x00000002 */

+#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */

+#define DFSDM_FLTCR1_DFEN_Pos           (0U)

+#define DFSDM_FLTCR1_DFEN_Msk           (0x1UL << DFSDM_FLTCR1_DFEN_Pos)       /*!< 0x00000001 */

+#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */

+

+/********************  Bit definition for DFSDM_FLTCR2 register *******************/

+#define DFSDM_FLTCR2_AWDCH_Pos          (16U)

+#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)     /*!< 0x00FF0000 */

+#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */

+#define DFSDM_FLTCR2_EXCH_Pos           (8U)

+#define DFSDM_FLTCR2_EXCH_Msk           (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)      /*!< 0x0000FF00 */

+#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */

+#define DFSDM_FLTCR2_CKABIE_Pos         (6U)

+#define DFSDM_FLTCR2_CKABIE_Msk         (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)     /*!< 0x00000040 */

+#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */

+#define DFSDM_FLTCR2_SCDIE_Pos          (5U)

+#define DFSDM_FLTCR2_SCDIE_Msk          (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)      /*!< 0x00000020 */

+#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */

+#define DFSDM_FLTCR2_AWDIE_Pos          (4U)

+#define DFSDM_FLTCR2_AWDIE_Msk          (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)      /*!< 0x00000010 */

+#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */

+#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)

+#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)     /*!< 0x00000008 */

+#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */

+#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)

+#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)     /*!< 0x00000004 */

+#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */

+#define DFSDM_FLTCR2_REOCIE_Pos         (1U)

+#define DFSDM_FLTCR2_REOCIE_Msk         (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)     /*!< 0x00000002 */

+#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */

+#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)

+#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)     /*!< 0x00000001 */

+#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */

+

+/********************  Bit definition for DFSDM_FLTISR register *******************/

+#define DFSDM_FLTISR_SCDF_Pos           (24U)

+#define DFSDM_FLTISR_SCDF_Msk           (0xFFUL << DFSDM_FLTISR_SCDF_Pos)      /*!< 0xFF000000 */

+#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */

+#define DFSDM_FLTISR_CKABF_Pos          (16U)

+#define DFSDM_FLTISR_CKABF_Msk          (0xFFUL << DFSDM_FLTISR_CKABF_Pos)     /*!< 0x00FF0000 */

+#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */

+#define DFSDM_FLTISR_RCIP_Pos           (14U)

+#define DFSDM_FLTISR_RCIP_Msk           (0x1UL << DFSDM_FLTISR_RCIP_Pos)       /*!< 0x00004000 */

+#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */

+#define DFSDM_FLTISR_JCIP_Pos           (13U)

+#define DFSDM_FLTISR_JCIP_Msk           (0x1UL << DFSDM_FLTISR_JCIP_Pos)       /*!< 0x00002000 */

+#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */

+#define DFSDM_FLTISR_AWDF_Pos           (4U)

+#define DFSDM_FLTISR_AWDF_Msk           (0x1UL << DFSDM_FLTISR_AWDF_Pos)       /*!< 0x00000010 */

+#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */

+#define DFSDM_FLTISR_ROVRF_Pos          (3U)

+#define DFSDM_FLTISR_ROVRF_Msk          (0x1UL << DFSDM_FLTISR_ROVRF_Pos)      /*!< 0x00000008 */

+#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */

+#define DFSDM_FLTISR_JOVRF_Pos          (2U)

+#define DFSDM_FLTISR_JOVRF_Msk          (0x1UL << DFSDM_FLTISR_JOVRF_Pos)      /*!< 0x00000004 */

+#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */

+#define DFSDM_FLTISR_REOCF_Pos          (1U)

+#define DFSDM_FLTISR_REOCF_Msk          (0x1UL << DFSDM_FLTISR_REOCF_Pos)      /*!< 0x00000002 */

+#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */

+#define DFSDM_FLTISR_JEOCF_Pos          (0U)

+#define DFSDM_FLTISR_JEOCF_Msk          (0x1UL << DFSDM_FLTISR_JEOCF_Pos)      /*!< 0x00000001 */

+#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */

+

+/********************  Bit definition for DFSDM_FLTICR register *******************/

+#define DFSDM_FLTICR_CLRSCDF_Pos        (24U)

+#define DFSDM_FLTICR_CLRSCDF_Msk        (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)   /*!< 0xFF000000 */

+#define DFSDM_FLTICR_CLRSCDF            DFSDM_FLTICR_CLRSCDF_Msk               /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */

+#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)

+#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)  /*!< 0x00FF0000 */

+#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */

+#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)

+#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)   /*!< 0x00000008 */

+#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */

+#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)

+#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)   /*!< 0x00000004 */

+#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */

+

+/*******************  Bit definition for DFSDM_FLTJCHGR register ******************/

+#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)

+#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)    /*!< 0x000000FF */

+#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */

+

+/********************  Bit definition for DFSDM_FLTFCR register *******************/

+#define DFSDM_FLTFCR_FORD_Pos           (29U)

+#define DFSDM_FLTFCR_FORD_Msk           (0x7UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0xE0000000 */

+#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */

+#define DFSDM_FLTFCR_FORD_2             (0x4UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */

+#define DFSDM_FLTFCR_FORD_1             (0x2UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */

+#define DFSDM_FLTFCR_FORD_0             (0x1UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */

+#define DFSDM_FLTFCR_FOSR_Pos           (16U)

+#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)     /*!< 0x03FF0000 */

+#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */

+#define DFSDM_FLTFCR_IOSR_Pos           (0U)

+#define DFSDM_FLTFCR_IOSR_Msk           (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)      /*!< 0x000000FF */

+#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */

+

+/******************  Bit definition for DFSDM_FLTJDATAR register *****************/

+#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)

+#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */

+#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)

+#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */

+#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */

+

+/******************  Bit definition for DFSDM_FLTRDATAR register *****************/

+#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)

+#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */

+#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)

+#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)   /*!< 0x00000010 */

+#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */

+#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)

+#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */

+#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */

+

+/******************  Bit definition for DFSDM_FLTAWHTR register ******************/

+#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)

+#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */

+#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)

+#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)    /*!< 0x0000000F */

+#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */

+

+/******************  Bit definition for DFSDM_FLTAWLTR register ******************/

+#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)

+#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWHT[23:0] Analog watchdog low threshold */

+#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)

+#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)    /*!< 0x0000000F */

+#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */

+

+/******************  Bit definition for DFSDM_FLTAWSR register ******************/

+#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)

+#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)    /*!< 0x0000FF00 */

+#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */

+#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)

+#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)    /*!< 0x000000FF */

+#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */

+

+/******************  Bit definition for DFSDM_FLTAWCFR) register *****************/

+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)

+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */

+#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */

+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)

+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */

+#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */

+

+/******************  Bit definition for DFSDM_FLTEXMAX register ******************/

+#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)

+#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */

+#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)

+#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)  /*!< 0x00000007 */

+#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */

+

+/******************  Bit definition for DFSDM_FLTEXMIN register ******************/

+#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)

+#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */

+#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)

+#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)  /*!< 0x00000007 */

+#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */

+

+/******************  Bit definition for DFSDM_FLTCNVTIMR register ******************/

+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)

+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */

+#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           BDMA Controller                                  */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for BDMA_ISR register  ********************/

+#define BDMA_ISR_GIF0_Pos       (0U)

+#define BDMA_ISR_GIF0_Msk       (0x1UL << BDMA_ISR_GIF0_Pos)                   /*!< 0x00000001 */

+#define BDMA_ISR_GIF0           BDMA_ISR_GIF0_Msk                              /*!< Channel 0 Global interrupt flag */

+#define BDMA_ISR_TCIF0_Pos      (1U)

+#define BDMA_ISR_TCIF0_Msk      (0x1UL << BDMA_ISR_TCIF0_Pos)                  /*!< 0x00000002 */

+#define BDMA_ISR_TCIF0          BDMA_ISR_TCIF0_Msk                             /*!< Channel 0 Transfer Complete flag */

+#define BDMA_ISR_HTIF0_Pos      (2U)

+#define BDMA_ISR_HTIF0_Msk      (0x1UL << BDMA_ISR_HTIF0_Pos)                  /*!< 0x00000004 */

+#define BDMA_ISR_HTIF0          BDMA_ISR_HTIF0_Msk                             /*!< Channel 0 Half Transfer flag */

+#define BDMA_ISR_TEIF0_Pos      (3U)

+#define BDMA_ISR_TEIF0_Msk      (0x1UL << BDMA_ISR_TEIF0_Pos)                  /*!< 0x00000008 */

+#define BDMA_ISR_TEIF0          BDMA_ISR_TEIF0_Msk                             /*!< Channel 0 Transfer Error flag */

+#define BDMA_ISR_GIF1_Pos       (4U)

+#define BDMA_ISR_GIF1_Msk       (0x1UL << BDMA_ISR_GIF1_Pos)                   /*!< 0x00000010 */

+#define BDMA_ISR_GIF1           BDMA_ISR_GIF1_Msk                              /*!< Channel 1 Global interrupt flag */

+#define BDMA_ISR_TCIF1_Pos      (5U)

+#define BDMA_ISR_TCIF1_Msk      (0x1UL << BDMA_ISR_TCIF1_Pos)                  /*!< 0x00000020 */

+#define BDMA_ISR_TCIF1          BDMA_ISR_TCIF1_Msk                             /*!< Channel 1 Transfer Complete flag */

+#define BDMA_ISR_HTIF1_Pos      (6U)

+#define BDMA_ISR_HTIF1_Msk      (0x1UL << BDMA_ISR_HTIF1_Pos)                  /*!< 0x00000040 */

+#define BDMA_ISR_HTIF1          BDMA_ISR_HTIF1_Msk                             /*!< Channel 1 Half Transfer flag */

+#define BDMA_ISR_TEIF1_Pos      (7U)

+#define BDMA_ISR_TEIF1_Msk      (0x1UL << BDMA_ISR_TEIF1_Pos)                  /*!< 0x00000080 */

+#define BDMA_ISR_TEIF1          BDMA_ISR_TEIF1_Msk                             /*!< Channel 1 Transfer Error flag */

+#define BDMA_ISR_GIF2_Pos       (8U)

+#define BDMA_ISR_GIF2_Msk       (0x1UL << BDMA_ISR_GIF2_Pos)                   /*!< 0x00000100 */

+#define BDMA_ISR_GIF2           BDMA_ISR_GIF2_Msk                              /*!< Channel 2 Global interrupt flag */

+#define BDMA_ISR_TCIF2_Pos      (9U)

+#define BDMA_ISR_TCIF2_Msk      (0x1UL << BDMA_ISR_TCIF2_Pos)                  /*!< 0x00000200 */

+#define BDMA_ISR_TCIF2          BDMA_ISR_TCIF2_Msk                             /*!< Channel 2 Transfer Complete flag */

+#define BDMA_ISR_HTIF2_Pos      (10U)

+#define BDMA_ISR_HTIF2_Msk      (0x1UL << BDMA_ISR_HTIF2_Pos)                  /*!< 0x00000400 */

+#define BDMA_ISR_HTIF2          BDMA_ISR_HTIF2_Msk                             /*!< Channel 2 Half Transfer flag */

+#define BDMA_ISR_TEIF2_Pos      (11U)

+#define BDMA_ISR_TEIF2_Msk      (0x1UL << BDMA_ISR_TEIF2_Pos)                  /*!< 0x00000800 */

+#define BDMA_ISR_TEIF2          BDMA_ISR_TEIF2_Msk                             /*!< Channel 2 Transfer Error flag */

+#define BDMA_ISR_GIF3_Pos       (12U)

+#define BDMA_ISR_GIF3_Msk       (0x1UL << BDMA_ISR_GIF3_Pos)                   /*!< 0x00001000 */

+#define BDMA_ISR_GIF3           BDMA_ISR_GIF3_Msk                              /*!< Channel 3 Global interrupt flag */

+#define BDMA_ISR_TCIF3_Pos      (13U)

+#define BDMA_ISR_TCIF3_Msk      (0x1UL << BDMA_ISR_TCIF3_Pos)                  /*!< 0x00002000 */

+#define BDMA_ISR_TCIF3          BDMA_ISR_TCIF3_Msk                             /*!< Channel 3 Transfer Complete flag */

+#define BDMA_ISR_HTIF3_Pos      (14U)

+#define BDMA_ISR_HTIF3_Msk      (0x1UL << BDMA_ISR_HTIF3_Pos)                  /*!< 0x00004000 */

+#define BDMA_ISR_HTIF3          BDMA_ISR_HTIF3_Msk                             /*!< Channel 3 Half Transfer flag */

+#define BDMA_ISR_TEIF3_Pos      (15U)

+#define BDMA_ISR_TEIF3_Msk      (0x1UL << BDMA_ISR_TEIF3_Pos)                  /*!< 0x00008000 */

+#define BDMA_ISR_TEIF3          BDMA_ISR_TEIF3_Msk                             /*!< Channel 3 Transfer Error flag */

+#define BDMA_ISR_GIF4_Pos       (16U)

+#define BDMA_ISR_GIF4_Msk       (0x1UL << BDMA_ISR_GIF4_Pos)                   /*!< 0x00010000 */

+#define BDMA_ISR_GIF4           BDMA_ISR_GIF4_Msk                              /*!< Channel 4 Global interrupt flag */

+#define BDMA_ISR_TCIF4_Pos      (17U)

+#define BDMA_ISR_TCIF4_Msk      (0x1UL << BDMA_ISR_TCIF4_Pos)                  /*!< 0x00020000 */

+#define BDMA_ISR_TCIF4          BDMA_ISR_TCIF4_Msk                             /*!< Channel 4 Transfer Complete flag */

+#define BDMA_ISR_HTIF4_Pos      (18U)

+#define BDMA_ISR_HTIF4_Msk      (0x1UL << BDMA_ISR_HTIF4_Pos)                  /*!< 0x00040000 */

+#define BDMA_ISR_HTIF4          BDMA_ISR_HTIF4_Msk                             /*!< Channel 4 Half Transfer flag */

+#define BDMA_ISR_TEIF4_Pos      (19U)

+#define BDMA_ISR_TEIF4_Msk      (0x1UL << BDMA_ISR_TEIF4_Pos)                  /*!< 0x00080000 */

+#define BDMA_ISR_TEIF4          BDMA_ISR_TEIF4_Msk                             /*!< Channel 4 Transfer Error flag */

+#define BDMA_ISR_GIF5_Pos       (20U)

+#define BDMA_ISR_GIF5_Msk       (0x1UL << BDMA_ISR_GIF5_Pos)                   /*!< 0x00100000 */

+#define BDMA_ISR_GIF5           BDMA_ISR_GIF5_Msk                              /*!< Channel 5 Global interrupt flag */

+#define BDMA_ISR_TCIF5_Pos      (21U)

+#define BDMA_ISR_TCIF5_Msk      (0x1UL << BDMA_ISR_TCIF5_Pos)                  /*!< 0x00200000 */

+#define BDMA_ISR_TCIF5          BDMA_ISR_TCIF5_Msk                             /*!< Channel 5 Transfer Complete flag */

+#define BDMA_ISR_HTIF5_Pos      (22U)

+#define BDMA_ISR_HTIF5_Msk      (0x1UL << BDMA_ISR_HTIF5_Pos)                  /*!< 0x00400000 */

+#define BDMA_ISR_HTIF5          BDMA_ISR_HTIF5_Msk                             /*!< Channel 5 Half Transfer flag */

+#define BDMA_ISR_TEIF5_Pos      (23U)

+#define BDMA_ISR_TEIF5_Msk      (0x1UL << BDMA_ISR_TEIF5_Pos)                  /*!< 0x00800000 */

+#define BDMA_ISR_TEIF5          BDMA_ISR_TEIF5_Msk                             /*!< Channel 5 Transfer Error flag */

+#define BDMA_ISR_GIF6_Pos       (24U)

+#define BDMA_ISR_GIF6_Msk       (0x1UL << BDMA_ISR_GIF6_Pos)                   /*!< 0x01000000 */

+#define BDMA_ISR_GIF6           BDMA_ISR_GIF6_Msk                              /*!< Channel 6 Global interrupt flag */

+#define BDMA_ISR_TCIF6_Pos      (25U)

+#define BDMA_ISR_TCIF6_Msk      (0x1UL << BDMA_ISR_TCIF6_Pos)                  /*!< 0x02000000 */

+#define BDMA_ISR_TCIF6          BDMA_ISR_TCIF6_Msk                             /*!< Channel 6 Transfer Complete flag */

+#define BDMA_ISR_HTIF6_Pos      (26U)

+#define BDMA_ISR_HTIF6_Msk      (0x1UL << BDMA_ISR_HTIF6_Pos)                  /*!< 0x04000000 */

+#define BDMA_ISR_HTIF6          BDMA_ISR_HTIF6_Msk                             /*!< Channel 6 Half Transfer flag */

+#define BDMA_ISR_TEIF6_Pos      (27U)

+#define BDMA_ISR_TEIF6_Msk      (0x1UL << BDMA_ISR_TEIF6_Pos)                  /*!< 0x08000000 */

+#define BDMA_ISR_TEIF6          BDMA_ISR_TEIF6_Msk                             /*!< Channel 6 Transfer Error flag */

+#define BDMA_ISR_GIF7_Pos       (28U)

+#define BDMA_ISR_GIF7_Msk       (0x1UL << BDMA_ISR_GIF7_Pos)                   /*!< 0x10000000 */

+#define BDMA_ISR_GIF7           BDMA_ISR_GIF7_Msk                              /*!< Channel 7 Global interrupt flag */

+#define BDMA_ISR_TCIF7_Pos      (29U)

+#define BDMA_ISR_TCIF7_Msk      (0x1UL << BDMA_ISR_TCIF7_Pos)                  /*!< 0x20000000 */

+#define BDMA_ISR_TCIF7          BDMA_ISR_TCIF7_Msk                             /*!< Channel 7 Transfer Complete flag */

+#define BDMA_ISR_HTIF7_Pos      (30U)

+#define BDMA_ISR_HTIF7_Msk      (0x1UL << BDMA_ISR_HTIF7_Pos)                  /*!< 0x40000000 */

+#define BDMA_ISR_HTIF7          BDMA_ISR_HTIF7_Msk                             /*!< Channel 7 Half Transfer flag */

+#define BDMA_ISR_TEIF7_Pos      (31U)

+#define BDMA_ISR_TEIF7_Msk      (0x1UL << BDMA_ISR_TEIF7_Pos)                  /*!< 0x80000000 */

+#define BDMA_ISR_TEIF7          BDMA_ISR_TEIF7_Msk                             /*!< Channel 7 Transfer Error flag */

+

+/*******************  Bit definition for BDMA_IFCR register  *******************/

+#define BDMA_IFCR_CGIF0_Pos     (0U)

+#define BDMA_IFCR_CGIF0_Msk     (0x1UL << BDMA_IFCR_CGIF0_Pos)                 /*!< 0x00000001 */

+#define BDMA_IFCR_CGIF0         BDMA_IFCR_CGIF0_Msk                            /*!< Channel 0 Global interrupt clearr */

+#define BDMA_IFCR_CTCIF0_Pos    (1U)

+#define BDMA_IFCR_CTCIF0_Msk    (0x1UL << BDMA_IFCR_CTCIF0_Pos)                /*!< 0x00000002 */

+#define BDMA_IFCR_CTCIF0        BDMA_IFCR_CTCIF0_Msk                           /*!< Channel 0 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF0_Pos    (2U)

+#define BDMA_IFCR_CHTIF0_Msk    (0x1UL << BDMA_IFCR_CHTIF0_Pos)                /*!< 0x00000004 */

+#define BDMA_IFCR_CHTIF0        BDMA_IFCR_CHTIF0_Msk                           /*!< Channel 0 Half Transfer clear */

+#define BDMA_IFCR_CTEIF0_Pos    (3U)

+#define BDMA_IFCR_CTEIF0_Msk    (0x1UL << BDMA_IFCR_CTEIF0_Pos)                /*!< 0x00000008 */

+#define BDMA_IFCR_CTEIF0        BDMA_IFCR_CTEIF0_Msk                           /*!< Channel 0 Transfer Error clear */

+#define BDMA_IFCR_CGIF1_Pos     (4U)

+#define BDMA_IFCR_CGIF1_Msk     (0x1UL << BDMA_IFCR_CGIF1_Pos)                 /*!< 0x00000010 */

+#define BDMA_IFCR_CGIF1         BDMA_IFCR_CGIF1_Msk                            /*!< Channel 1 Global interrupt clear */

+#define BDMA_IFCR_CTCIF1_Pos    (5U)

+#define BDMA_IFCR_CTCIF1_Msk    (0x1UL << BDMA_IFCR_CTCIF1_Pos)                /*!< 0x00000020 */

+#define BDMA_IFCR_CTCIF1        BDMA_IFCR_CTCIF1_Msk                           /*!< Channel 1 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF1_Pos    (6U)

+#define BDMA_IFCR_CHTIF1_Msk    (0x1UL << BDMA_IFCR_CHTIF1_Pos)                /*!< 0x00000040 */

+#define BDMA_IFCR_CHTIF1        BDMA_IFCR_CHTIF1_Msk                           /*!< Channel 1 Half Transfer clear */

+#define BDMA_IFCR_CTEIF1_Pos    (7U)

+#define BDMA_IFCR_CTEIF1_Msk    (0x1UL << BDMA_IFCR_CTEIF1_Pos)                /*!< 0x00000080 */

+#define BDMA_IFCR_CTEIF1        BDMA_IFCR_CTEIF1_Msk                           /*!< Channel 1 Transfer Error clear */

+#define BDMA_IFCR_CGIF2_Pos     (8U)

+#define BDMA_IFCR_CGIF2_Msk     (0x1UL << BDMA_IFCR_CGIF2_Pos)                 /*!< 0x00000100 */

+#define BDMA_IFCR_CGIF2         BDMA_IFCR_CGIF2_Msk                            /*!< Channel 2 Global interrupt clear */

+#define BDMA_IFCR_CTCIF2_Pos    (9U)

+#define BDMA_IFCR_CTCIF2_Msk    (0x1UL << BDMA_IFCR_CTCIF2_Pos)                /*!< 0x00000200 */

+#define BDMA_IFCR_CTCIF2        BDMA_IFCR_CTCIF2_Msk                           /*!< Channel 2 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF2_Pos    (10U)

+#define BDMA_IFCR_CHTIF2_Msk    (0x1UL << BDMA_IFCR_CHTIF2_Pos)                /*!< 0x00000400 */

+#define BDMA_IFCR_CHTIF2        BDMA_IFCR_CHTIF2_Msk                           /*!< Channel 2 Half Transfer clear */

+#define BDMA_IFCR_CTEIF2_Pos    (11U)

+#define BDMA_IFCR_CTEIF2_Msk    (0x1UL << BDMA_IFCR_CTEIF2_Pos)                /*!< 0x00000800 */

+#define BDMA_IFCR_CTEIF2        BDMA_IFCR_CTEIF2_Msk                           /*!< Channel 2 Transfer Error clear */

+#define BDMA_IFCR_CGIF3_Pos     (12U)

+#define BDMA_IFCR_CGIF3_Msk     (0x1UL << BDMA_IFCR_CGIF3_Pos)                 /*!< 0x00001000 */

+#define BDMA_IFCR_CGIF3         BDMA_IFCR_CGIF3_Msk                            /*!< Channel 3 Global interrupt clear */

+#define BDMA_IFCR_CTCIF3_Pos    (13U)

+#define BDMA_IFCR_CTCIF3_Msk    (0x1UL << BDMA_IFCR_CTCIF3_Pos)                /*!< 0x00002000 */

+#define BDMA_IFCR_CTCIF3        BDMA_IFCR_CTCIF3_Msk                           /*!< Channel 3 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF3_Pos    (14U)

+#define BDMA_IFCR_CHTIF3_Msk    (0x1UL << BDMA_IFCR_CHTIF3_Pos)                /*!< 0x00004000 */

+#define BDMA_IFCR_CHTIF3        BDMA_IFCR_CHTIF3_Msk                           /*!< Channel 3 Half Transfer clear */

+#define BDMA_IFCR_CTEIF3_Pos    (15U)

+#define BDMA_IFCR_CTEIF3_Msk    (0x1UL << BDMA_IFCR_CTEIF3_Pos)                /*!< 0x00008000 */

+#define BDMA_IFCR_CTEIF3        BDMA_IFCR_CTEIF3_Msk                           /*!< Channel 3 Transfer Error clear */

+#define BDMA_IFCR_CGIF4_Pos     (16U)

+#define BDMA_IFCR_CGIF4_Msk     (0x1UL << BDMA_IFCR_CGIF4_Pos)                 /*!< 0x00010000 */

+#define BDMA_IFCR_CGIF4         BDMA_IFCR_CGIF4_Msk                            /*!< Channel 4 Global interrupt clear */

+#define BDMA_IFCR_CTCIF4_Pos    (17U)

+#define BDMA_IFCR_CTCIF4_Msk    (0x1UL << BDMA_IFCR_CTCIF4_Pos)                /*!< 0x00020000 */

+#define BDMA_IFCR_CTCIF4        BDMA_IFCR_CTCIF4_Msk                           /*!< Channel 4 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF4_Pos    (18U)

+#define BDMA_IFCR_CHTIF4_Msk    (0x1UL << BDMA_IFCR_CHTIF4_Pos)                /*!< 0x00040000 */

+#define BDMA_IFCR_CHTIF4        BDMA_IFCR_CHTIF4_Msk                           /*!< Channel 4 Half Transfer clear */

+#define BDMA_IFCR_CTEIF4_Pos    (19U)

+#define BDMA_IFCR_CTEIF4_Msk    (0x1UL << BDMA_IFCR_CTEIF4_Pos)                /*!< 0x00080000 */

+#define BDMA_IFCR_CTEIF4        BDMA_IFCR_CTEIF4_Msk                           /*!< Channel 4 Transfer Error clear */

+#define BDMA_IFCR_CGIF5_Pos     (20U)

+#define BDMA_IFCR_CGIF5_Msk     (0x1UL << BDMA_IFCR_CGIF5_Pos)                 /*!< 0x00100000 */

+#define BDMA_IFCR_CGIF5         BDMA_IFCR_CGIF5_Msk                            /*!< Channel 5 Global interrupt clear */

+#define BDMA_IFCR_CTCIF5_Pos    (21U)

+#define BDMA_IFCR_CTCIF5_Msk    (0x1UL << BDMA_IFCR_CTCIF5_Pos)                /*!< 0x00200000 */

+#define BDMA_IFCR_CTCIF5        BDMA_IFCR_CTCIF5_Msk                           /*!< Channel 5 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF5_Pos    (22U)

+#define BDMA_IFCR_CHTIF5_Msk    (0x1UL << BDMA_IFCR_CHTIF5_Pos)                /*!< 0x00400000 */

+#define BDMA_IFCR_CHTIF5        BDMA_IFCR_CHTIF5_Msk                           /*!< Channel 5 Half Transfer clear */

+#define BDMA_IFCR_CTEIF5_Pos    (23U)

+#define BDMA_IFCR_CTEIF5_Msk    (0x1UL << BDMA_IFCR_CTEIF5_Pos)                /*!< 0x00800000 */

+#define BDMA_IFCR_CTEIF5        BDMA_IFCR_CTEIF5_Msk                           /*!< Channel 5 Transfer Error clear */

+#define BDMA_IFCR_CGIF6_Pos     (24U)

+#define BDMA_IFCR_CGIF6_Msk     (0x1UL << BDMA_IFCR_CGIF6_Pos)                 /*!< 0x01000000 */

+#define BDMA_IFCR_CGIF6         BDMA_IFCR_CGIF6_Msk                            /*!< Channel 6 Global interrupt clear */

+#define BDMA_IFCR_CTCIF6_Pos    (25U)

+#define BDMA_IFCR_CTCIF6_Msk    (0x1UL << BDMA_IFCR_CTCIF6_Pos)                /*!< 0x02000000 */

+#define BDMA_IFCR_CTCIF6        BDMA_IFCR_CTCIF6_Msk                           /*!< Channel 6 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF6_Pos    (26U)

+#define BDMA_IFCR_CHTIF6_Msk    (0x1UL << BDMA_IFCR_CHTIF6_Pos)                /*!< 0x04000000 */

+#define BDMA_IFCR_CHTIF6        BDMA_IFCR_CHTIF6_Msk                           /*!< Channel 6 Half Transfer clear */

+#define BDMA_IFCR_CTEIF6_Pos    (27U)

+#define BDMA_IFCR_CTEIF6_Msk    (0x1UL << BDMA_IFCR_CTEIF6_Pos)                /*!< 0x08000000 */

+#define BDMA_IFCR_CTEIF6        BDMA_IFCR_CTEIF6_Msk                           /*!< Channel 6 Transfer Error clear */

+#define BDMA_IFCR_CGIF7_Pos     (28U)

+#define BDMA_IFCR_CGIF7_Msk     (0x1UL << BDMA_IFCR_CGIF7_Pos)                 /*!< 0x10000000 */

+#define BDMA_IFCR_CGIF7         BDMA_IFCR_CGIF7_Msk                            /*!< Channel 7 Global interrupt clear */

+#define BDMA_IFCR_CTCIF7_Pos    (29U)

+#define BDMA_IFCR_CTCIF7_Msk    (0x1UL << BDMA_IFCR_CTCIF7_Pos)                /*!< 0x20000000 */

+#define BDMA_IFCR_CTCIF7        BDMA_IFCR_CTCIF7_Msk                           /*!< Channel 7 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF7_Pos    (30U)

+#define BDMA_IFCR_CHTIF7_Msk    (0x1UL << BDMA_IFCR_CHTIF7_Pos)                /*!< 0x40000000 */

+#define BDMA_IFCR_CHTIF7        BDMA_IFCR_CHTIF7_Msk                           /*!< Channel 7 Half Transfer clear */

+#define BDMA_IFCR_CTEIF7_Pos    (31U)

+#define BDMA_IFCR_CTEIF7_Msk    (0x1UL << BDMA_IFCR_CTEIF7_Pos)                /*!< 0x80000000 */

+#define BDMA_IFCR_CTEIF7        BDMA_IFCR_CTEIF7_Msk                           /*!< Channel 7 Transfer Error clear */

+

+/*******************  Bit definition for BDMA_CCR register  ********************/

+#define BDMA_CCR_EN_Pos         (0U)

+#define BDMA_CCR_EN_Msk         (0x1UL << BDMA_CCR_EN_Pos)                     /*!< 0x00000001 */

+#define BDMA_CCR_EN             BDMA_CCR_EN_Msk                                /*!< Channel enable                      */

+#define BDMA_CCR_TCIE_Pos       (1U)

+#define BDMA_CCR_TCIE_Msk       (0x1UL << BDMA_CCR_TCIE_Pos)                   /*!< 0x00000002 */

+#define BDMA_CCR_TCIE           BDMA_CCR_TCIE_Msk                              /*!< Transfer complete interrupt enable  */

+#define BDMA_CCR_HTIE_Pos       (2U)

+#define BDMA_CCR_HTIE_Msk       (0x1UL << BDMA_CCR_HTIE_Pos)                   /*!< 0x00000004 */

+#define BDMA_CCR_HTIE           BDMA_CCR_HTIE_Msk                              /*!< Half Transfer interrupt enable      */

+#define BDMA_CCR_TEIE_Pos       (3U)

+#define BDMA_CCR_TEIE_Msk       (0x1UL << BDMA_CCR_TEIE_Pos)                   /*!< 0x00000008 */

+#define BDMA_CCR_TEIE           BDMA_CCR_TEIE_Msk                              /*!< Transfer error interrupt enable     */

+#define BDMA_CCR_DIR_Pos        (4U)

+#define BDMA_CCR_DIR_Msk        (0x1UL << BDMA_CCR_DIR_Pos)                    /*!< 0x00000010 */

+#define BDMA_CCR_DIR            BDMA_CCR_DIR_Msk                               /*!< Data transfer direction             */

+#define BDMA_CCR_CIRC_Pos       (5U)

+#define BDMA_CCR_CIRC_Msk       (0x1UL << BDMA_CCR_CIRC_Pos)                   /*!< 0x00000020 */

+#define BDMA_CCR_CIRC           BDMA_CCR_CIRC_Msk                              /*!< Circular mode                       */

+#define BDMA_CCR_PINC_Pos       (6U)

+#define BDMA_CCR_PINC_Msk       (0x1UL << BDMA_CCR_PINC_Pos)                   /*!< 0x00000040 */

+#define BDMA_CCR_PINC           BDMA_CCR_PINC_Msk                              /*!< Peripheral increment mode           */

+#define BDMA_CCR_MINC_Pos       (7U)

+#define BDMA_CCR_MINC_Msk       (0x1UL << BDMA_CCR_MINC_Pos)                   /*!< 0x00000080 */

+#define BDMA_CCR_MINC           BDMA_CCR_MINC_Msk                              /*!< Memory increment mode               */

+

+#define BDMA_CCR_PSIZE_Pos      (8U)

+#define BDMA_CCR_PSIZE_Msk      (0x3UL << BDMA_CCR_PSIZE_Pos)                  /*!< 0x00000300 */

+#define BDMA_CCR_PSIZE          BDMA_CCR_PSIZE_Msk                             /*!< PSIZE[1:0] bits (Peripheral size)   */

+#define BDMA_CCR_PSIZE_0        (0x1UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000100 */

+#define BDMA_CCR_PSIZE_1        (0x2UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000200 */

+

+#define BDMA_CCR_MSIZE_Pos      (10U)

+#define BDMA_CCR_MSIZE_Msk      (0x3UL << BDMA_CCR_MSIZE_Pos)                  /*!< 0x00000C00 */

+#define BDMA_CCR_MSIZE          BDMA_CCR_MSIZE_Msk                             /*!< MSIZE[1:0] bits (Memory size)       */

+#define BDMA_CCR_MSIZE_0        (0x1UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000400 */

+#define BDMA_CCR_MSIZE_1        (0x2UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000800 */

+

+#define BDMA_CCR_PL_Pos         (12U)

+#define BDMA_CCR_PL_Msk         (0x3UL << BDMA_CCR_PL_Pos)                     /*!< 0x00003000 */

+#define BDMA_CCR_PL             BDMA_CCR_PL_Msk                                /*!< PL[1:0] bits(Channel Priority level)*/

+#define BDMA_CCR_PL_0           (0x1UL << BDMA_CCR_PL_Pos)                      /*!< 0x00001000 */

+#define BDMA_CCR_PL_1           (0x2UL << BDMA_CCR_PL_Pos)                      /*!< 0x00002000 */

+

+#define BDMA_CCR_MEM2MEM_Pos    (14U)

+#define BDMA_CCR_MEM2MEM_Msk    (0x1UL << BDMA_CCR_MEM2MEM_Pos)                /*!< 0x00004000 */

+#define BDMA_CCR_MEM2MEM        BDMA_CCR_MEM2MEM_Msk                           /*!< Memory to memory mode               */

+#define BDMA_CCR_DBM_Pos        (15U)

+#define BDMA_CCR_DBM_Msk        (0x1UL << BDMA_CCR_DBM_Pos)                    /*!< 0x0000A000 */

+#define BDMA_CCR_DBM            BDMA_CCR_DBM_Msk                               /*!< Memory to memory mode               */

+#define BDMA_CCR_CT_Pos         (16U)

+#define BDMA_CCR_CT_Msk         (0x1UL << BDMA_CCR_CT_Pos)                     /*!< 0x00010000 */

+#define BDMA_CCR_CT             BDMA_CCR_CT_Msk                                /*!< Memory to memory mode               */

+

+/******************  Bit definition for BDMA_CNDTR register  *******************/

+#define BDMA_CNDTR_NDT_Pos      (0U)

+#define BDMA_CNDTR_NDT_Msk      (0xFFFFUL << BDMA_CNDTR_NDT_Pos)               /*!< 0x0000FFFF */

+#define BDMA_CNDTR_NDT          BDMA_CNDTR_NDT_Msk                             /*!< Number of data to Transfer          */

+

+/******************  Bit definition for BDMA_CPAR register  ********************/

+#define BDMA_CPAR_PA_Pos        (0U)

+#define BDMA_CPAR_PA_Msk        (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CPAR_PA            BDMA_CPAR_PA_Msk                               /*!< Peripheral Address                  */

+

+/******************  Bit definition for BDMA_CM0AR register  ********************/

+#define BDMA_CM0AR_MA_Pos        (0U)

+#define BDMA_CM0AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CM0AR_MA            BDMA_CM0AR_MA_Msk                               /*!< Memory Address                      */

+

+/******************  Bit definition for BDMA_CM1AR register  ********************/

+#define BDMA_CM1AR_MA_Pos        (0U)

+#define BDMA_CM1AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CM1AR_MA            BDMA_CM1AR_MA_Msk                               /*!< Memory Address                      */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             DMA Controller                                 */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DMA_SxCR register  *****************/

+#define DMA_SxCR_MBURST_Pos      (23U)

+#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                /*!< 0x01800000 */

+#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk                           /*!< Memory burst transfer configuration */

+#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */

+#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */

+#define DMA_SxCR_PBURST_Pos      (21U)

+#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                /*!< 0x00600000 */

+#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk                           /*!< Peripheral burst transfer configuration */

+#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */

+#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */

+#define DMA_SxCR_TRBUFF_Pos      (20U)

+#define DMA_SxCR_TRBUFF_Msk      (0x1UL << DMA_SxCR_TRBUFF_Pos)                 /*!< 0x00100000 */

+#define DMA_SxCR_TRBUFF          DMA_SxCR_TRBUFF_Msk                            /*!< bufferable transfers enabled/disable */

+#define DMA_SxCR_CT_Pos          (19U)

+#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                    /*!< 0x00080000 */

+#define DMA_SxCR_CT              DMA_SxCR_CT_Msk                               /*!< Current target (only in double buffer mode) */

+#define DMA_SxCR_DBM_Pos         (18U)

+#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                   /*!< 0x00040000 */

+#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk                              /*!< Double buffer mode */

+#define DMA_SxCR_PL_Pos          (16U)

+#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                    /*!< 0x00030000 */

+#define DMA_SxCR_PL              DMA_SxCR_PL_Msk                               /*!< Priority level */

+#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */

+#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */

+#define DMA_SxCR_PINCOS_Pos      (15U)

+#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                /*!< 0x00008000 */

+#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk                           /*!< Peripheral increment offset size */

+#define DMA_SxCR_MSIZE_Pos       (13U)

+#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                 /*!< 0x00006000 */

+#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk                            /*!< Memory data size */

+#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */

+#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */

+#define DMA_SxCR_PSIZE_Pos       (11U)

+#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                 /*!< 0x00001800 */

+#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk                            /*< Peripheral data size */

+#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */

+#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */

+#define DMA_SxCR_MINC_Pos        (10U)

+#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                  /*!< 0x00000400 */

+#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk                             /*!< Memory increment mode */

+#define DMA_SxCR_PINC_Pos        (9U)

+#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                  /*!< 0x00000200 */

+#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk                             /*!< Peripheral increment mode */

+#define DMA_SxCR_CIRC_Pos        (8U)

+#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                  /*!< 0x00000100 */

+#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk                             /*!< Circular mode */

+#define DMA_SxCR_DIR_Pos         (6U)

+#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                   /*!< 0x000000C0 */

+#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk                              /*!< Data transfer direction */

+#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */

+#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */

+#define DMA_SxCR_PFCTRL_Pos      (5U)

+#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                /*!< 0x00000020 */

+#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk                           /*!< Peripheral flow controller */

+#define DMA_SxCR_TCIE_Pos        (4U)

+#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                  /*!< 0x00000010 */

+#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk                             /*!< Transfer complete interrupt enable */

+#define DMA_SxCR_HTIE_Pos        (3U)

+#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                  /*!< 0x00000008 */

+#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk                             /*!< Half transfer interrupt enable */

+#define DMA_SxCR_TEIE_Pos        (2U)

+#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                  /*!< 0x00000004 */

+#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk                             /*!< Transfer error interrupt enable */

+#define DMA_SxCR_DMEIE_Pos       (1U)

+#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                 /*!< 0x00000002 */

+#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk                            /*!< Direct mode error interrupt enable */

+#define DMA_SxCR_EN_Pos          (0U)

+#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                    /*!< 0x00000001 */

+#define DMA_SxCR_EN              DMA_SxCR_EN_Msk                               /*!< Stream enable / flag stream ready when read low */

+

+/********************  Bits definition for DMA_SxCNDTR register  **************/

+#define DMA_SxNDT_Pos            (0U)

+#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                   /*!< 0x0000FFFF */

+#define DMA_SxNDT                DMA_SxNDT_Msk                                 /*!< Number of data items to transfer */

+#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */

+#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */

+#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */

+#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */

+#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */

+#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */

+#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */

+#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */

+#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */

+#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */

+#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */

+#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */

+#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */

+#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */

+#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */

+#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */

+

+/********************  Bits definition for DMA_SxFCR register  ****************/

+#define DMA_SxFCR_FEIE_Pos       (7U)

+#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                 /*!< 0x00000080 */

+#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk                            /*!< FIFO error interrupt enable */

+#define DMA_SxFCR_FS_Pos         (3U)

+#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                   /*!< 0x00000038 */

+#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk                              /*!< FIFO status */

+#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */

+#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */

+#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */

+#define DMA_SxFCR_DMDIS_Pos      (2U)

+#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                /*!< 0x00000004 */

+#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk                           /*!< Direct mode disable */

+#define DMA_SxFCR_FTH_Pos        (0U)

+#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                  /*!< 0x00000003 */

+#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk                             /*!< FIFO threshold selection */

+#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */

+#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */

+

+/********************  Bits definition for DMA_LISR register  *****************/

+#define DMA_LISR_TCIF3_Pos       (27U)

+#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                 /*!< 0x08000000 */

+#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk                            /*!<  Stream 3 transfer complete interrupt flag */

+#define DMA_LISR_HTIF3_Pos       (26U)

+#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                 /*!< 0x04000000 */

+#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk                            /*!<  Stream 3 half transfer interrupt flag */

+#define DMA_LISR_TEIF3_Pos       (25U)

+#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                 /*!< 0x02000000 */

+#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk                            /*!<  Stream 3 transfer error interrupt flag */

+#define DMA_LISR_DMEIF3_Pos      (24U)

+#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                /*!< 0x01000000 */

+#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk                           /*!<  Stream 3 direct mode error interrupt flag */

+#define DMA_LISR_FEIF3_Pos       (22U)

+#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                 /*!< 0x00400000 */

+#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk                            /*!<  Stream 3 FIFO error interrupt flag */

+#define DMA_LISR_TCIF2_Pos       (21U)

+#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                 /*!< 0x00200000 */

+#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk                            /*!<  Stream 2 transfer complete interrupt flag */

+#define DMA_LISR_HTIF2_Pos       (20U)

+#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                 /*!< 0x00100000 */

+#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk                            /*!<  Stream 2 half transfer interrupt flag */

+#define DMA_LISR_TEIF2_Pos       (19U)

+#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                 /*!< 0x00080000 */

+#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk                            /*!<  Stream 2 transfer error interrupt flag */

+#define DMA_LISR_DMEIF2_Pos      (18U)

+#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                /*!< 0x00040000 */

+#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk                           /*!<  Stream 2 direct mode error interrupt flag */

+#define DMA_LISR_FEIF2_Pos       (16U)

+#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                 /*!< 0x00010000 */

+#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk                            /*!<  Stream 2 FIFO error interrupt flag */

+#define DMA_LISR_TCIF1_Pos       (11U)

+#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                 /*!< 0x00000800 */

+#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk                            /*!<  Stream 1 transfer complete interrupt flag */

+#define DMA_LISR_HTIF1_Pos       (10U)

+#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                 /*!< 0x00000400 */

+#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk                            /*!<  Stream 1 half transfer interrupt flag */

+#define DMA_LISR_TEIF1_Pos       (9U)

+#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                 /*!< 0x00000200 */

+#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk                            /*!<  Stream 1 transfer error interrupt flag */

+#define DMA_LISR_DMEIF1_Pos      (8U)

+#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                /*!< 0x00000100 */

+#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk                           /*!<  Stream 1 direct mode error interrupt flag */

+#define DMA_LISR_FEIF1_Pos       (6U)

+#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                 /*!< 0x00000040 */

+#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk                            /*!<  Stream 1 FIFO error interrupt flag */

+#define DMA_LISR_TCIF0_Pos       (5U)

+#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                 /*!< 0x00000020 */

+#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk                            /*!<  Stream 0 transfer complete interrupt flag */

+#define DMA_LISR_HTIF0_Pos       (4U)

+#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                 /*!< 0x00000010 */

+#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk                            /*!<  Stream 0 half transfer interrupt flag */

+#define DMA_LISR_TEIF0_Pos       (3U)

+#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                 /*!< 0x00000008 */

+#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk                            /*!<  Stream 0 transfer error interrupt flag */

+#define DMA_LISR_DMEIF0_Pos      (2U)

+#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                /*!< 0x00000004 */

+#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk                           /*!<  Stream 0 direct mode error interrupt flag */

+#define DMA_LISR_FEIF0_Pos       (0U)

+#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                 /*!< 0x00000001 */

+#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk                            /*!<  Stream 0 FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_HISR register  *****************/

+#define DMA_HISR_TCIF7_Pos       (27U)

+#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                 /*!< 0x08000000 */

+#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk                            /*!<  Stream 7 transfer complete interrupt flag */

+#define DMA_HISR_HTIF7_Pos       (26U)

+#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                 /*!< 0x04000000 */

+#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk                            /*!<  Stream 7 half transfer interrupt flag */

+#define DMA_HISR_TEIF7_Pos       (25U)

+#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                 /*!< 0x02000000 */

+#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk                            /*!<  Stream 7 transfer error interrupt flag */

+#define DMA_HISR_DMEIF7_Pos      (24U)

+#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                /*!< 0x01000000 */

+#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk                           /*!<  Stream 7 direct mode error interrupt flag */

+#define DMA_HISR_FEIF7_Pos       (22U)

+#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                 /*!< 0x00400000 */

+#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk                            /*!<  Stream 7 FIFO error interrupt flag */

+#define DMA_HISR_TCIF6_Pos       (21U)

+#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                 /*!< 0x00200000 */

+#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk                            /*!<  Stream 6 transfer complete interrupt flag */

+#define DMA_HISR_HTIF6_Pos       (20U)

+#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                 /*!< 0x00100000 */

+#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk                            /*!<  Stream 6 half transfer interrupt flag */

+#define DMA_HISR_TEIF6_Pos       (19U)

+#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                 /*!< 0x00080000 */

+#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk                            /*!<  Stream 6 transfer error interrupt flag */

+#define DMA_HISR_DMEIF6_Pos      (18U)

+#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                /*!< 0x00040000 */

+#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk                           /*!<  Stream 6 direct mode error interrupt flag */

+#define DMA_HISR_FEIF6_Pos       (16U)

+#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                 /*!< 0x00010000 */

+#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk                            /*!<  Stream 6 FIFO error interrupt flag */

+#define DMA_HISR_TCIF5_Pos       (11U)

+#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                 /*!< 0x00000800 */

+#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk                            /*!<  Stream 5 transfer complete interrupt flag */

+#define DMA_HISR_HTIF5_Pos       (10U)

+#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                 /*!< 0x00000400 */

+#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk                            /*!<  Stream 5 half transfer interrupt flag */

+#define DMA_HISR_TEIF5_Pos       (9U)

+#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                 /*!< 0x00000200 */

+#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk                            /*!<  Stream 5 transfer error interrupt flag */

+#define DMA_HISR_DMEIF5_Pos      (8U)

+#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                /*!< 0x00000100 */

+#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk                           /*!<  Stream 5 direct mode error interrupt flag */

+#define DMA_HISR_FEIF5_Pos       (6U)

+#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                 /*!< 0x00000040 */

+#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk                            /*!<  Stream 5 FIFO error interrupt flag */

+#define DMA_HISR_TCIF4_Pos       (5U)

+#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                 /*!< 0x00000020 */

+#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk                            /*!<  Stream 4 transfer complete interrupt flag */

+#define DMA_HISR_HTIF4_Pos       (4U)

+#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                 /*!< 0x00000010 */

+#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk                            /*!<  Stream 4 half transfer interrupt flag */

+#define DMA_HISR_TEIF4_Pos       (3U)

+#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                 /*!< 0x00000008 */

+#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk                            /*!<  Stream 4 transfer error interrupt flag */

+#define DMA_HISR_DMEIF4_Pos      (2U)

+#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                /*!< 0x00000004 */

+#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk                           /*!<  Stream 4 direct mode error interrupt flag */

+#define DMA_HISR_FEIF4_Pos       (0U)

+#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                 /*!< 0x00000001 */

+#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk                            /*!<  Stream 4 FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_LIFCR register  ****************/

+#define DMA_LIFCR_CTCIF3_Pos     (27U)

+#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)               /*!< 0x08000000 */

+#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk                          /*!<  Stream 3 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF3_Pos     (26U)

+#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)               /*!< 0x04000000 */

+#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk                          /*!<  Stream 3 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF3_Pos     (25U)

+#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)               /*!< 0x02000000 */

+#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk                          /*!<  Stream 3 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF3_Pos    (24U)

+#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)              /*!< 0x01000000 */

+#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk                         /*!<  Stream 3 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF3_Pos     (22U)

+#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)               /*!< 0x00400000 */

+#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk                          /*!<  Stream 3 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF2_Pos     (21U)

+#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)               /*!< 0x00200000 */

+#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk                          /*!<  Stream 2 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF2_Pos     (20U)

+#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)               /*!< 0x00100000 */

+#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk                          /*!<  Stream 2 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF2_Pos     (19U)

+#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)               /*!< 0x00080000 */

+#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk                          /*!<  Stream 2 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF2_Pos    (18U)

+#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)              /*!< 0x00040000 */

+#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk                         /*!<  Stream 2 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF2_Pos     (16U)

+#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)               /*!< 0x00010000 */

+#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk                          /*!<  Stream 2 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF1_Pos     (11U)

+#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)               /*!< 0x00000800 */

+#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk                          /*!<  Stream 1 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF1_Pos     (10U)

+#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)               /*!< 0x00000400 */

+#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk                          /*!<  Stream 1 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF1_Pos     (9U)

+#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)               /*!< 0x00000200 */

+#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk                          /*!<  Stream 1 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF1_Pos    (8U)

+#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)              /*!< 0x00000100 */

+#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk                         /*!<  Stream 1 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF1_Pos     (6U)

+#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)               /*!< 0x00000040 */

+#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk                          /*!<  Stream 1 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF0_Pos     (5U)

+#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)               /*!< 0x00000020 */

+#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk                          /*!<  Stream 0 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF0_Pos     (4U)

+#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)               /*!< 0x00000010 */

+#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk                          /*!<  Stream 0 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF0_Pos     (3U)

+#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)               /*!< 0x00000008 */

+#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk                          /*!<  Stream 0 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF0_Pos    (2U)

+#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)              /*!< 0x00000004 */

+#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk                         /*!<  Stream 0 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF0_Pos     (0U)

+#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)               /*!< 0x00000001 */

+#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk                          /*!<  Stream 0 clear FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_HIFCR  register  ****************/

+#define DMA_HIFCR_CTCIF7_Pos     (27U)

+#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)               /*!< 0x08000000 */

+#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk                          /*!<  Stream 7 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF7_Pos     (26U)

+#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)               /*!< 0x04000000 */

+#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk                          /*!<  Stream 7 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF7_Pos     (25U)

+#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)               /*!< 0x02000000 */

+#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk                          /*!<  Stream 7 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF7_Pos    (24U)

+#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)              /*!< 0x01000000 */

+#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk                         /*!<  Stream 7 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF7_Pos     (22U)

+#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)               /*!< 0x00400000 */

+#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk                          /*!<  Stream 7 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF6_Pos     (21U)

+#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)               /*!< 0x00200000 */

+#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk                          /*!<  Stream 6 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF6_Pos     (20U)

+#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)               /*!< 0x00100000 */

+#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk                          /*!<  Stream 6 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF6_Pos     (19U)

+#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)               /*!< 0x00080000 */

+#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk                          /*!<  Stream 6 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF6_Pos    (18U)

+#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)              /*!< 0x00040000 */

+#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk                         /*!<  Stream 6 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF6_Pos     (16U)

+#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)               /*!< 0x00010000 */

+#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk                          /*!<  Stream 6 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF5_Pos     (11U)

+#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)               /*!< 0x00000800 */

+#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk                          /*!<  Stream 5 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF5_Pos     (10U)

+#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)               /*!< 0x00000400 */

+#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk                          /*!<  Stream 5 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF5_Pos     (9U)

+#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)               /*!< 0x00000200 */

+#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk                          /*!<  Stream 5 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF5_Pos    (8U)

+#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)              /*!< 0x00000100 */

+#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk                         /*!<  Stream 5 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF5_Pos     (6U)

+#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)               /*!< 0x00000040 */

+#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk                          /*!<  Stream 5 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF4_Pos     (5U)

+#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)               /*!< 0x00000020 */

+#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk                          /*!<  Stream 4 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF4_Pos     (4U)

+#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)               /*!< 0x00000010 */

+#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk                          /*!<  Stream 4 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF4_Pos     (3U)

+#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)               /*!< 0x00000008 */

+#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk                          /*!<  Stream 4 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF4_Pos    (2U)

+#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)              /*!< 0x00000004 */

+#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk                         /*!<  Stream 4 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF4_Pos     (0U)

+#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)               /*!< 0x00000001 */

+#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk                          /*!<  Stream 4 clear FIFO error interrupt flag */

+

+/******************  Bit definition for DMA_SxPAR register  ********************/

+#define DMA_SxPAR_PA_Pos         (0U)

+#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)            /*!< 0xFFFFFFFF */

+#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */

+

+/******************  Bit definition for DMA_SxM0AR register  ********************/

+#define DMA_SxM0AR_M0A_Pos       (0U)

+#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)          /*!< 0xFFFFFFFF */

+#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory 0 Address */

+

+/******************  Bit definition for DMA_SxM1AR register  ********************/

+#define DMA_SxM1AR_M1A_Pos       (0U)

+#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)          /*!< 0xFFFFFFFF */

+#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory 1 Address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             DMAMUX Controller                              */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DMAMUX_CxCR register  **************/

+#define DMAMUX_CxCR_DMAREQ_ID_Pos      (0U)

+#define DMAMUX_CxCR_DMAREQ_ID_Msk      (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)   /*!< 0x000000FF */

+#define DMAMUX_CxCR_DMAREQ_ID          DMAMUX_CxCR_DMAREQ_ID_Msk               /*!<  DMA request identification */

+#define DMAMUX_CxCR_DMAREQ_ID_0        (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000001 */

+#define DMAMUX_CxCR_DMAREQ_ID_1        (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000002 */

+#define DMAMUX_CxCR_DMAREQ_ID_2        (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000004 */

+#define DMAMUX_CxCR_DMAREQ_ID_3        (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000008 */

+#define DMAMUX_CxCR_DMAREQ_ID_4        (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000010 */

+#define DMAMUX_CxCR_DMAREQ_ID_5        (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000020 */

+#define DMAMUX_CxCR_DMAREQ_ID_6        (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000040 */

+#define DMAMUX_CxCR_DMAREQ_ID_7        (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000080 */

+#define DMAMUX_CxCR_SOIE_Pos           (8U)

+#define DMAMUX_CxCR_SOIE_Msk           (0x1UL << DMAMUX_CxCR_SOIE_Pos)         /*!< 0x00000100 */

+#define DMAMUX_CxCR_SOIE               DMAMUX_CxCR_SOIE_Msk                    /*!<  Synchronization overrun interrupt enable */

+#define DMAMUX_CxCR_EGE_Pos            (9U)

+#define DMAMUX_CxCR_EGE_Msk            (0x1UL << DMAMUX_CxCR_EGE_Pos)          /*!< 0x00000200 */

+#define DMAMUX_CxCR_EGE                DMAMUX_CxCR_EGE_Msk                     /*!<  Event generation enable */

+#define DMAMUX_CxCR_SE_Pos             (16U)

+#define DMAMUX_CxCR_SE_Msk             (0x1UL << DMAMUX_CxCR_SE_Pos)           /*!< 0x00010000 */

+#define DMAMUX_CxCR_SE                 DMAMUX_CxCR_SE_Msk                      /*!<  Synchronization enable */

+#define DMAMUX_CxCR_SPOL_Pos           (17U)

+#define DMAMUX_CxCR_SPOL_Msk           (0x3UL << DMAMUX_CxCR_SPOL_Pos)         /*!< 0x00060000 */

+#define DMAMUX_CxCR_SPOL               DMAMUX_CxCR_SPOL_Msk                    /*!<  Synchronization polarity */

+#define DMAMUX_CxCR_SPOL_0             (0x1UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00020000 */

+#define DMAMUX_CxCR_SPOL_1             (0x2UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00040000 */

+#define DMAMUX_CxCR_NBREQ_Pos          (19U)

+#define DMAMUX_CxCR_NBREQ_Msk          (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)       /*!< 0x00F80000 */

+#define DMAMUX_CxCR_NBREQ              DMAMUX_CxCR_NBREQ_Msk                   /*!<  Number of DMA requests minus 1 to forward */

+#define DMAMUX_CxCR_NBREQ_0            (0x01UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00080000 */

+#define DMAMUX_CxCR_NBREQ_1            (0x02UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00100000 */

+#define DMAMUX_CxCR_NBREQ_2            (0x04UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00200000 */

+#define DMAMUX_CxCR_NBREQ_3            (0x08UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00400000 */

+#define DMAMUX_CxCR_NBREQ_4            (0x10UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00800000 */

+#define DMAMUX_CxCR_SYNC_ID_Pos        (24U)

+#define DMAMUX_CxCR_SYNC_ID_Msk        (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)     /*!< 0x1F000000 */

+#define DMAMUX_CxCR_SYNC_ID            DMAMUX_CxCR_SYNC_ID_Msk                 /*!<  Synchronization identification */

+#define DMAMUX_CxCR_SYNC_ID_0          (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x01000000 */

+#define DMAMUX_CxCR_SYNC_ID_1          (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x02000000 */

+#define DMAMUX_CxCR_SYNC_ID_2          (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x04000000 */

+#define DMAMUX_CxCR_SYNC_ID_3          (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x08000000 */

+#define DMAMUX_CxCR_SYNC_ID_4          (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x10000000 */

+

+/********************  Bits definition for DMAMUX_CSR register  **************/

+#define DMAMUX_CSR_SOF0_Pos            (0U)

+#define DMAMUX_CSR_SOF0_Msk            (0x1UL << DMAMUX_CSR_SOF0_Pos)          /*!< 0x00000001 */

+#define DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0_Msk                     /*!< Channel 0 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF1_Pos            (1U)

+#define DMAMUX_CSR_SOF1_Msk            (0x1UL << DMAMUX_CSR_SOF1_Pos)          /*!< 0x00000002 */

+#define DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1_Msk                     /*!< Channel 1 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF2_Pos            (2U)

+#define DMAMUX_CSR_SOF2_Msk            (0x1UL << DMAMUX_CSR_SOF2_Pos)          /*!< 0x00000004 */

+#define DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2_Msk                     /*!< Channel 2 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF3_Pos            (3U)

+#define DMAMUX_CSR_SOF3_Msk            (0x1UL << DMAMUX_CSR_SOF3_Pos)          /*!< 0x00000008 */

+#define DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3_Msk                     /*!< Channel 3 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF4_Pos            (4U)

+#define DMAMUX_CSR_SOF4_Msk            (0x1UL << DMAMUX_CSR_SOF4_Pos)          /*!< 0x00000010 */

+#define DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4_Msk                     /*!< Channel 4 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF5_Pos            (5U)

+#define DMAMUX_CSR_SOF5_Msk            (0x1UL << DMAMUX_CSR_SOF5_Pos)          /*!< 0x00000020 */

+#define DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5_Msk                     /*!< Channel 5 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF6_Pos            (6U)

+#define DMAMUX_CSR_SOF6_Msk            (0x1UL << DMAMUX_CSR_SOF6_Pos)          /*!< 0x00000040 */

+#define DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6_Msk                     /*!< Channel 6 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF7_Pos            (7U)

+#define DMAMUX_CSR_SOF7_Msk            (0x1UL << DMAMUX_CSR_SOF7_Pos)          /*!< 0x00000080 */

+#define DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7_Msk                     /*!< Channel 7 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF8_Pos            (8U)

+#define DMAMUX_CSR_SOF8_Msk            (0x1UL << DMAMUX_CSR_SOF8_Pos)          /*!< 0x00000100 */

+#define DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8_Msk                     /*!< Channel 8 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF9_Pos            (9U)

+#define DMAMUX_CSR_SOF9_Msk            (0x1UL << DMAMUX_CSR_SOF9_Pos)          /*!< 0x00000200 */

+#define DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9_Msk                     /*!< Channel 9 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF10_Pos           (10U)

+#define DMAMUX_CSR_SOF10_Msk           (0x1UL << DMAMUX_CSR_SOF10_Pos)         /*!< 0x00000400 */

+#define DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10_Msk                    /*!< Channel 10 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF11_Pos           (11U)

+#define DMAMUX_CSR_SOF11_Msk           (0x1UL << DMAMUX_CSR_SOF11_Pos)         /*!< 0x00000800 */

+#define DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11_Msk                    /*!< Channel 11 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF12_Pos           (12U)

+#define DMAMUX_CSR_SOF12_Msk           (0x1UL << DMAMUX_CSR_SOF12_Pos)         /*!< 0x00001000 */

+#define DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12_Msk                    /*!< Channel 12 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF13_Pos           (13U)

+#define DMAMUX_CSR_SOF13_Msk           (0x1UL << DMAMUX_CSR_SOF13_Pos)         /*!< 0x00002000 */

+#define DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13_Msk                    /*!< Channel 13 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF14_Pos           (14U)

+#define DMAMUX_CSR_SOF14_Msk           (0x1UL << DMAMUX_CSR_SOF14_Pos)         /*!< 0x00004000 */

+#define DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14_Msk                    /*!< Channel 14 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF15_Pos           (15U)

+#define DMAMUX_CSR_SOF15_Msk           (0x1UL << DMAMUX_CSR_SOF15_Pos)         /*!< 0x00008000 */

+#define DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15_Msk                    /*!< Channel 15 Synchronization overrun event flag */

+

+/********************  Bits definition for DMAMUX_CFR register  **************/

+#define DMAMUX_CFR_CSOF0_Pos           (0U)

+#define DMAMUX_CFR_CSOF0_Msk           (0x1UL << DMAMUX_CFR_CSOF0_Pos)         /*!< 0x00000001 */

+#define DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0_Msk                    /*!< Channel 0 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF1_Pos           (1U)

+#define DMAMUX_CFR_CSOF1_Msk           (0x1UL << DMAMUX_CFR_CSOF1_Pos)         /*!< 0x00000002 */

+#define DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1_Msk                    /*!< Channel 1 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF2_Pos           (2U)

+#define DMAMUX_CFR_CSOF2_Msk           (0x1UL << DMAMUX_CFR_CSOF2_Pos)         /*!< 0x00000004 */

+#define DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2_Msk                    /*!< Channel 2 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF3_Pos           (3U)

+#define DMAMUX_CFR_CSOF3_Msk           (0x1UL << DMAMUX_CFR_CSOF3_Pos)         /*!< 0x00000008 */

+#define DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3_Msk                    /*!< Channel 3 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF4_Pos           (4U)

+#define DMAMUX_CFR_CSOF4_Msk           (0x1UL << DMAMUX_CFR_CSOF4_Pos)         /*!< 0x00000010 */

+#define DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4_Msk                    /*!< Channel 4 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF5_Pos           (5U)

+#define DMAMUX_CFR_CSOF5_Msk           (0x1UL << DMAMUX_CFR_CSOF5_Pos)         /*!< 0x00000020 */

+#define DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5_Msk                    /*!< Channel 5 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF6_Pos           (6U)

+#define DMAMUX_CFR_CSOF6_Msk           (0x1UL << DMAMUX_CFR_CSOF6_Pos)         /*!< 0x00000040 */

+#define DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6_Msk                    /*!< Channel 6 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF7_Pos           (7U)

+#define DMAMUX_CFR_CSOF7_Msk           (0x1UL << DMAMUX_CFR_CSOF7_Pos)         /*!< 0x00000080 */

+#define DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7_Msk                    /*!< Channel 7 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF8_Pos           (8U)

+#define DMAMUX_CFR_CSOF8_Msk           (0x1UL << DMAMUX_CFR_CSOF8_Pos)         /*!< 0x00000100 */

+#define DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8_Msk                    /*!< Channel 8 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF9_Pos           (9U)

+#define DMAMUX_CFR_CSOF9_Msk           (0x1UL << DMAMUX_CFR_CSOF9_Pos)         /*!< 0x00000200 */

+#define DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9_Msk                    /*!< Channel 9 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF10_Pos          (10U)

+#define DMAMUX_CFR_CSOF10_Msk          (0x1UL << DMAMUX_CFR_CSOF10_Pos)        /*!< 0x00000400 */

+#define DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10_Msk                   /*!< Channel 10 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF11_Pos          (11U)

+#define DMAMUX_CFR_CSOF11_Msk          (0x1UL << DMAMUX_CFR_CSOF11_Pos)        /*!< 0x00000800 */

+#define DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11_Msk                   /*!< Channel 11 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF12_Pos          (12U)

+#define DMAMUX_CFR_CSOF12_Msk          (0x1UL << DMAMUX_CFR_CSOF12_Pos)        /*!< 0x00001000 */

+#define DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12_Msk                   /*!< Channel 12 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF13_Pos          (13U)

+#define DMAMUX_CFR_CSOF13_Msk          (0x1UL << DMAMUX_CFR_CSOF13_Pos)        /*!< 0x00002000 */

+#define DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13_Msk                   /*!< Channel 13 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF14_Pos          (14U)

+#define DMAMUX_CFR_CSOF14_Msk          (0x1UL << DMAMUX_CFR_CSOF14_Pos)        /*!< 0x00004000 */

+#define DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14_Msk                   /*!< Channel 14 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF15_Pos          (15U)

+#define DMAMUX_CFR_CSOF15_Msk          (0x1UL << DMAMUX_CFR_CSOF15_Pos)        /*!< 0x00008000 */

+#define DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15_Msk                   /*!< Channel 15 Clear synchronization overrun event flag */

+

+/********************  Bits definition for DMAMUX_RGxCR register  ************/

+#define DMAMUX_RGxCR_SIG_ID_Pos        (0U)

+#define DMAMUX_RGxCR_SIG_ID_Msk        (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)     /*!< 0x0000001F */

+#define DMAMUX_RGxCR_SIG_ID            DMAMUX_RGxCR_SIG_ID_Msk                 /*!< Signal identification */

+#define DMAMUX_RGxCR_SIG_ID_0          (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000001 */

+#define DMAMUX_RGxCR_SIG_ID_1          (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000002 */

+#define DMAMUX_RGxCR_SIG_ID_2          (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000004 */

+#define DMAMUX_RGxCR_SIG_ID_3          (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000008 */

+#define DMAMUX_RGxCR_SIG_ID_4          (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000010 */

+#define DMAMUX_RGxCR_OIE_Pos           (8U)

+#define DMAMUX_RGxCR_OIE_Msk           (0x1UL << DMAMUX_RGxCR_OIE_Pos)         /*!< 0x00000100 */

+#define DMAMUX_RGxCR_OIE               DMAMUX_RGxCR_OIE_Msk                    /*!< Trigger overrun interrupt enable */

+#define DMAMUX_RGxCR_GE_Pos            (16U)

+#define DMAMUX_RGxCR_GE_Msk            (0x1UL << DMAMUX_RGxCR_GE_Pos)          /*!< 0x00010000 */

+#define DMAMUX_RGxCR_GE                DMAMUX_RGxCR_GE_Msk                     /*!< DMA request generator enable */

+#define DMAMUX_RGxCR_GPOL_Pos          (17U)

+#define DMAMUX_RGxCR_GPOL_Msk          (0x3UL << DMAMUX_RGxCR_GPOL_Pos)        /*!< 0x00060000 */

+#define DMAMUX_RGxCR_GPOL              DMAMUX_RGxCR_GPOL_Msk                   /*!< DMA request generator trigger polarity */

+#define DMAMUX_RGxCR_GPOL_0            (0x1UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00020000 */

+#define DMAMUX_RGxCR_GPOL_1            (0x2UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00040000 */

+#define DMAMUX_RGxCR_GNBREQ_Pos        (19U)

+#define DMAMUX_RGxCR_GNBREQ_Msk        (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)     /*!< 0x00F80000 */

+#define DMAMUX_RGxCR_GNBREQ            DMAMUX_RGxCR_GNBREQ_Msk                 /*!< Number of DMA requests to be generated */

+#define DMAMUX_RGxCR_GNBREQ_0          (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00080000 */

+#define DMAMUX_RGxCR_GNBREQ_1          (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00100000 */

+#define DMAMUX_RGxCR_GNBREQ_2          (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00200000 */

+#define DMAMUX_RGxCR_GNBREQ_3          (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00400000 */

+#define DMAMUX_RGxCR_GNBREQ_4          (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00800000 */

+

+/********************  Bits definition for DMAMUX_RGSR register  **************/

+#define DMAMUX_RGSR_OF0_Pos            (0U)

+#define DMAMUX_RGSR_OF0_Msk            (0x1UL << DMAMUX_RGSR_OF0_Pos)          /*!< 0x00000001 */

+#define DMAMUX_RGSR_OF0                DMAMUX_RGSR_OF0_Msk                     /*!< Request generator channel 0 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF1_Pos            (1U)

+#define DMAMUX_RGSR_OF1_Msk            (0x1UL << DMAMUX_RGSR_OF1_Pos)          /*!< 0x00000002 */

+#define DMAMUX_RGSR_OF1                DMAMUX_RGSR_OF1_Msk                     /*!< Request generator channel 1 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF2_Pos            (2U)

+#define DMAMUX_RGSR_OF2_Msk            (0x1UL << DMAMUX_RGSR_OF2_Pos)          /*!< 0x00000004 */

+#define DMAMUX_RGSR_OF2                DMAMUX_RGSR_OF2_Msk                     /*!< Request generator channel 2 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF3_Pos            (3U)

+#define DMAMUX_RGSR_OF3_Msk            (0x1UL << DMAMUX_RGSR_OF3_Pos)          /*!< 0x00000008 */

+#define DMAMUX_RGSR_OF3                DMAMUX_RGSR_OF3_Msk                     /*!< Request generator channel 3 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF4_Pos            (4U)

+#define DMAMUX_RGSR_OF4_Msk            (0x1UL << DMAMUX_RGSR_OF4_Pos)          /*!< 0x00000010 */

+#define DMAMUX_RGSR_OF4                DMAMUX_RGSR_OF4_Msk                     /*!< Request generator channel 4 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF5_Pos            (5U)

+#define DMAMUX_RGSR_OF5_Msk            (0x1UL << DMAMUX_RGSR_OF5_Pos)          /*!< 0x00000020 */

+#define DMAMUX_RGSR_OF5                DMAMUX_RGSR_OF5_Msk                     /*!< Request generator channel 5 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF6_Pos            (6U)

+#define DMAMUX_RGSR_OF6_Msk            (0x1UL << DMAMUX_RGSR_OF6_Pos)          /*!< 0x00000040 */

+#define DMAMUX_RGSR_OF6                DMAMUX_RGSR_OF6_Msk                     /*!< Request generator channel 6 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF7_Pos            (7U)

+#define DMAMUX_RGSR_OF7_Msk            (0x1UL << DMAMUX_RGSR_OF7_Pos)          /*!< 0x00000080 */

+#define DMAMUX_RGSR_OF7                DMAMUX_RGSR_OF7_Msk                     /*!< Request generator channel 7 Trigger overrun event flag */

+

+/********************  Bits definition for DMAMUX_RGCFR register  **************/

+#define DMAMUX_RGCFR_COF0_Pos          (0U)

+#define DMAMUX_RGCFR_COF0_Msk          (0x1UL << DMAMUX_RGCFR_COF0_Pos)        /*!< 0x00000001 */

+#define DMAMUX_RGCFR_COF0              DMAMUX_RGCFR_COF0_Msk                   /*!< Request generator channel 0 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF1_Pos          (1U)

+#define DMAMUX_RGCFR_COF1_Msk          (0x1UL << DMAMUX_RGCFR_COF1_Pos)        /*!< 0x00000002 */

+#define DMAMUX_RGCFR_COF1              DMAMUX_RGCFR_COF1_Msk                   /*!< Request generator channel 1 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF2_Pos          (2U)

+#define DMAMUX_RGCFR_COF2_Msk          (0x1UL << DMAMUX_RGCFR_COF2_Pos)        /*!< 0x00000004 */

+#define DMAMUX_RGCFR_COF2              DMAMUX_RGCFR_COF2_Msk                   /*!< Request generator channel 2 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF3_Pos          (3U)

+#define DMAMUX_RGCFR_COF3_Msk          (0x1UL << DMAMUX_RGCFR_COF3_Pos)        /*!< 0x00000008 */

+#define DMAMUX_RGCFR_COF3              DMAMUX_RGCFR_COF3_Msk                   /*!< Request generator channel 3 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF4_Pos          (4U)

+#define DMAMUX_RGCFR_COF4_Msk          (0x1UL << DMAMUX_RGCFR_COF4_Pos)        /*!< 0x00000010 */

+#define DMAMUX_RGCFR_COF4              DMAMUX_RGCFR_COF4_Msk                   /*!< Request generator channel 4 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF5_Pos          (5U)

+#define DMAMUX_RGCFR_COF5_Msk          (0x1UL << DMAMUX_RGCFR_COF5_Pos)        /*!< 0x00000020 */

+#define DMAMUX_RGCFR_COF5              DMAMUX_RGCFR_COF5_Msk                   /*!< Request generator channel 5 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF6_Pos          (6U)

+#define DMAMUX_RGCFR_COF6_Msk          (0x1UL << DMAMUX_RGCFR_COF6_Pos)        /*!< 0x00000040 */

+#define DMAMUX_RGCFR_COF6              DMAMUX_RGCFR_COF6_Msk                   /*!< Request generator channel 6 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF7_Pos          (7U)

+#define DMAMUX_RGCFR_COF7_Msk          (0x1UL << DMAMUX_RGCFR_COF7_Pos)        /*!< 0x00000080 */

+#define DMAMUX_RGCFR_COF7              DMAMUX_RGCFR_COF7_Msk                   /*!< Request generator channel 7 Clear trigger overrun event flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         AHB Master DMA2D Controller (DMA2D)                */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for DMA2D_CR register  ******************/

+

+#define DMA2D_CR_START_Pos         (0U)

+#define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)               /*!< 0x00000001 */

+#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer                          */

+#define DMA2D_CR_SUSP_Pos          (1U)

+#define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                /*!< 0x00000002 */

+#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer                        */

+#define DMA2D_CR_ABORT_Pos         (2U)

+#define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)               /*!< 0x00000004 */

+#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer                          */

+#define DMA2D_CR_LOM_Pos           (6U)

+#define DMA2D_CR_LOM_Msk           (0x1UL << DMA2D_CR_LOM_Pos)                 /*!< 0x00000040 */

+#define DMA2D_CR_LOM               DMA2D_CR_LOM_Msk                            /*!< Line Offset Mode                         */

+#define DMA2D_CR_TEIE_Pos          (8U)

+#define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                /*!< 0x00000100 */

+#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable         */

+#define DMA2D_CR_TCIE_Pos          (9U)

+#define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                /*!< 0x00000200 */

+#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable      */

+#define DMA2D_CR_TWIE_Pos          (10U)

+#define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                /*!< 0x00000400 */

+#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable     */

+#define DMA2D_CR_CAEIE_Pos         (11U)

+#define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)               /*!< 0x00000800 */

+#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable      */

+#define DMA2D_CR_CTCIE_Pos         (12U)

+#define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)               /*!< 0x00001000 */

+#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */

+#define DMA2D_CR_CEIE_Pos          (13U)

+#define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                /*!< 0x00002000 */

+#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable    */

+#define DMA2D_CR_MODE_Pos          (16U)

+#define DMA2D_CR_MODE_Msk          (0x7UL << DMA2D_CR_MODE_Pos)                /*!< 0x00070000 */

+#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[2:0]                         */

+#define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */

+#define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */

+#define DMA2D_CR_MODE_2            (0x4UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00040000 */

+

+/********************  Bit definition for DMA2D_ISR register  *****************/

+

+#define DMA2D_ISR_TEIF_Pos         (0U)

+#define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)               /*!< 0x00000001 */

+#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag         */

+#define DMA2D_ISR_TCIF_Pos         (1U)

+#define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)               /*!< 0x00000002 */

+#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag      */

+#define DMA2D_ISR_TWIF_Pos         (2U)

+#define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)               /*!< 0x00000004 */

+#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag     */

+#define DMA2D_ISR_CAEIF_Pos        (3U)

+#define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)              /*!< 0x00000008 */

+#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag      */

+#define DMA2D_ISR_CTCIF_Pos        (4U)

+#define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)              /*!< 0x00000010 */

+#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */

+#define DMA2D_ISR_CEIF_Pos         (5U)

+#define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)               /*!< 0x00000020 */

+#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag    */

+

+/********************  Bit definition for DMA2D_IFCR register  ****************/

+

+#define DMA2D_IFCR_CTEIF_Pos       (0U)

+#define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)             /*!< 0x00000001 */

+#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */

+#define DMA2D_IFCR_CTCIF_Pos       (1U)

+#define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)             /*!< 0x00000002 */

+#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */

+#define DMA2D_IFCR_CTWIF_Pos       (2U)

+#define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)             /*!< 0x00000004 */

+#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */

+#define DMA2D_IFCR_CAECIF_Pos      (3U)

+#define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)            /*!< 0x00000008 */

+#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */

+#define DMA2D_IFCR_CCTCIF_Pos      (4U)

+#define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)            /*!< 0x00000010 */

+#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */

+#define DMA2D_IFCR_CCEIF_Pos       (5U)

+#define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)             /*!< 0x00000020 */

+#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */

+

+/********************  Bit definition for DMA2D_FGMAR register  ***************/

+

+#define DMA2D_FGMAR_MA_Pos         (0U)

+#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)        /*!< 0xFFFFFFFF */

+#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Foreground Memory Address */

+

+/********************  Bit definition for DMA2D_FGOR register  ****************/

+

+#define DMA2D_FGOR_LO_Pos          (0U)

+#define DMA2D_FGOR_LO_Msk          (0xFFFFUL << DMA2D_FGOR_LO_Pos)             /*!< 0x0000FFFF */

+#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */

+

+/********************  Bit definition for DMA2D_BGMAR register  ***************/

+

+#define DMA2D_BGMAR_MA_Pos         (0U)

+#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)        /*!< 0xFFFFFFFF */

+#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Background Memory Address */

+

+/********************  Bit definition for DMA2D_BGOR register  ****************/

+

+#define DMA2D_BGOR_LO_Pos          (0U)

+#define DMA2D_BGOR_LO_Msk          (0xFFFFUL << DMA2D_BGOR_LO_Pos)             /*!< 0x0000FFFF */

+#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */

+

+/********************  Bit definition for DMA2D_FGPFCCR register  *************/

+

+#define DMA2D_FGPFCCR_CM_Pos       (0U)

+#define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x0000000F */

+#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */

+#define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */

+#define DMA2D_FGPFCCR_CCM_Pos      (4U)

+#define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)            /*!< 0x00000010 */

+#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */

+#define DMA2D_FGPFCCR_START_Pos    (5U)

+#define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)          /*!< 0x00000020 */

+#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */

+#define DMA2D_FGPFCCR_CS_Pos       (8U)

+#define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)            /*!< 0x0000FF00 */

+#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */

+#define DMA2D_FGPFCCR_AM_Pos       (16U)

+#define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00030000 */

+#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */

+#define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */

+#define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */

+#define DMA2D_FGPFCCR_CSS_Pos      (18U)

+#define DMA2D_FGPFCCR_CSS_Msk      (0x3UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x000C0000 */

+#define DMA2D_FGPFCCR_CSS          DMA2D_FGPFCCR_CSS_Msk                       /* !< Chroma Sub-Sampling */

+#define DMA2D_FGPFCCR_CSS_0        (0x1UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00040000 */

+#define DMA2D_FGPFCCR_CSS_1        (0x2UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00080000 */

+#define DMA2D_FGPFCCR_AI_Pos       (20U)

+#define DMA2D_FGPFCCR_AI_Msk       (0x1UL << DMA2D_FGPFCCR_AI_Pos)             /*!< 0x00100000 */

+#define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Foreground Input Alpha Inverted */

+#define DMA2D_FGPFCCR_RBS_Pos      (21U)

+#define DMA2D_FGPFCCR_RBS_Msk      (0x1UL << DMA2D_FGPFCCR_RBS_Pos)            /*!< 0x00200000 */

+#define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Foreground Input Red Blue Swap */

+#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)

+#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */

+#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */

+

+/********************  Bit definition for DMA2D_FGCOLR register  **************/

+

+#define DMA2D_FGCOLR_BLUE_Pos      (0U)

+#define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)           /*!< 0x000000FF */

+#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Foreground Blue Value */

+#define DMA2D_FGCOLR_GREEN_Pos     (8U)

+#define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */

+#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Foreground Green Value */

+#define DMA2D_FGCOLR_RED_Pos       (16U)

+#define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)            /*!< 0x00FF0000 */

+#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Foreground Red Value */

+

+/********************  Bit definition for DMA2D_BGPFCCR register  *************/

+

+#define DMA2D_BGPFCCR_CM_Pos       (0U)

+#define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x0000000F */

+#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */

+#define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_BGPFCCR_CM_3         (0x8UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000008 */

+#define DMA2D_BGPFCCR_CCM_Pos      (4U)

+#define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)            /*!< 0x00000010 */

+#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */

+#define DMA2D_BGPFCCR_START_Pos    (5U)

+#define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)          /*!< 0x00000020 */

+#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */

+#define DMA2D_BGPFCCR_CS_Pos       (8U)

+#define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)            /*!< 0x0000FF00 */

+#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */

+#define DMA2D_BGPFCCR_AM_Pos       (16U)

+#define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00030000 */

+#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */

+#define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */

+#define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */

+#define DMA2D_BGPFCCR_AI_Pos       (20U)

+#define DMA2D_BGPFCCR_AI_Msk       (0x1UL << DMA2D_BGPFCCR_AI_Pos)             /*!< 0x00100000 */

+#define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< background Input Alpha Inverted */

+#define DMA2D_BGPFCCR_RBS_Pos      (21U)

+#define DMA2D_BGPFCCR_RBS_Msk      (0x1UL << DMA2D_BGPFCCR_RBS_Pos)            /*!< 0x00200000 */

+#define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Background Input Red Blue Swap */

+#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)

+#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */

+#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */

+

+/********************  Bit definition for DMA2D_BGCOLR register  **************/

+

+#define DMA2D_BGCOLR_BLUE_Pos      (0U)

+#define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)           /*!< 0x000000FF */

+#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Background Blue Value */

+#define DMA2D_BGCOLR_GREEN_Pos     (8U)

+#define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */

+#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Background Green Value */

+#define DMA2D_BGCOLR_RED_Pos       (16U)

+#define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)            /*!< 0x00FF0000 */

+#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Background Red Value */

+

+/********************  Bit definition for DMA2D_FGCMAR register  **************/

+

+#define DMA2D_FGCMAR_MA_Pos        (0U)

+#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */

+#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Foreground CLUT Memory Address */

+

+/********************  Bit definition for DMA2D_BGCMAR register  **************/

+

+#define DMA2D_BGCMAR_MA_Pos        (0U)

+#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */

+#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Background CLUT Memory Address */

+

+/********************  Bit definition for DMA2D_OPFCCR register  **************/

+

+#define DMA2D_OPFCCR_CM_Pos        (0U)

+#define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000007 */

+#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Output Color mode CM[2:0] */

+#define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_OPFCCR_SB_Pos        (8U)

+#define DMA2D_OPFCCR_SB_Msk        (0x1UL << DMA2D_OPFCCR_SB_Pos)              /*!< 0x00000100 */

+#define DMA2D_OPFCCR_SB            DMA2D_OPFCCR_SB_Msk                         /*!< Swap Bytes */

+#define DMA2D_OPFCCR_AI_Pos        (20U)

+#define DMA2D_OPFCCR_AI_Msk        (0x1UL << DMA2D_OPFCCR_AI_Pos)              /*!< 0x00100000 */

+#define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Output Alpha Inverted */

+#define DMA2D_OPFCCR_RBS_Pos       (21U)

+#define DMA2D_OPFCCR_RBS_Msk       (0x1UL << DMA2D_OPFCCR_RBS_Pos)             /*!< 0x00200000 */

+#define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Output Red Blue Swap */

+

+/********************  Bit definition for DMA2D_OCOLR register  ***************/

+

+/*!<Mode_ARGB8888/RGB888 */

+

+#define DMA2D_OCOLR_BLUE_1_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_1_Msk     (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos)            /*0x000000FFU*/

+#define DMA2D_OCOLR_BLUE_1         DMA2D_OCOLR_BLUE_1_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_1_Pos    (8U)

+#define DMA2D_OCOLR_GREEN_1_Msk    (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos)            /*0x0000FF00U)*/

+#define DMA2D_OCOLR_GREEN_1        DMA2D_OCOLR_GREEN_1_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_1_Pos      (16U)

+#define DMA2D_OCOLR_RED_1_Msk      (0xFFUL << DMA2D_OCOLR_RED_1_Pos)            /*0x00FF0000U */

+#define DMA2D_OCOLR_RED_1          DMA2D_OCOLR_RED_1_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_1_Pos    (24U)

+#define DMA2D_OCOLR_ALPHA_1_Msk    (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos)          /*0xFF000000U*/

+#define DMA2D_OCOLR_ALPHA_1        DMA2D_OCOLR_ALPHA_1_Msk                     /*!< Output Alpha Channel Value */

+

+/*!<Mode_RGB565 */

+#define DMA2D_OCOLR_BLUE_2_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_2_Msk     (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos)            /*0x0000001FU*/

+#define DMA2D_OCOLR_BLUE_2         DMA2D_OCOLR_BLUE_2_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_2_Pos    (5U)

+#define DMA2D_OCOLR_GREEN_2_Msk    (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos)          /* 0x000007E0U */

+#define DMA2D_OCOLR_GREEN_2        DMA2D_OCOLR_GREEN_2_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_2_Pos      (11U)

+#define DMA2D_OCOLR_RED_2_Msk      (0xF8UL<<DMA2D_OCOLR_RED_2_Pos)              /*0x0000F800U*/

+#define DMA2D_OCOLR_RED_2          DMA2D_OCOLR_RED_2_Msk                       /*!< Output Red Value */

+

+/*!<Mode_ARGB1555 */

+#define DMA2D_OCOLR_BLUE_3_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_3_Msk     (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos)           /*0x0000001FU*/

+#define DMA2D_OCOLR_BLUE_3         DMA2D_OCOLR_BLUE_3_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_3_Pos    (5U)

+#define DMA2D_OCOLR_GREEN_3_Msk    (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos)          /*0x000003E0U*/

+#define DMA2D_OCOLR_GREEN_3        DMA2D_OCOLR_GREEN_3_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_3_Pos      (10U)

+#define DMA2D_OCOLR_RED_3_Msk      (0x7CUL << DMA2D_OCOLR_RED_3_Pos)            /* 0x00007C00U*/

+#define DMA2D_OCOLR_RED_3          DMA2D_OCOLR_RED_3_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_3_Pos    (15U)

+#define DMA2D_OCOLR_ALPHA_3_Msk    (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos)           /*0x00008000U*/

+#define DMA2D_OCOLR_ALPHA_3        DMA2D_OCOLR_ALPHA_3_Msk                     /*!< Output Alpha Channel Value */

+

+/*!<Mode_ARGB4444 */

+#define DMA2D_OCOLR_BLUE_4_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_4_Msk     (0xFUL << DMA2D_OCOLR_BLUE_4_Pos)            /*0x0000000FU*/

+#define DMA2D_OCOLR_BLUE_4         DMA2D_OCOLR_BLUE_4_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_4_Pos    (4U)

+#define DMA2D_OCOLR_GREEN_4_Msk    (0xFUL << DMA2D_OCOLR_GREEN_4_Pos)           /*0x000000F0U*/

+#define DMA2D_OCOLR_GREEN_4        DMA2D_OCOLR_GREEN_4_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_4_Pos      (8U)

+#define DMA2D_OCOLR_RED_4_Msk      (0xFUL << DMA2D_OCOLR_RED_4_Pos)             /*0x00000F00U*/

+#define DMA2D_OCOLR_RED_4          DMA2D_OCOLR_RED_4_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_4_Pos    (12U)

+#define DMA2D_OCOLR_ALPHA_4_Msk    (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos)            /*0x0000F000U*/

+#define DMA2D_OCOLR_ALPHA_4        DMA2D_OCOLR_ALPHA_4_Msk                     /*!< Output Alpha Channel Value */

+

+/********************  Bit definition for DMA2D_OMAR register  ****************/

+

+#define DMA2D_OMAR_MA_Pos          (0U)

+#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)         /*!< 0xFFFFFFFF */

+#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Output Memory Address */

+

+/********************  Bit definition for DMA2D_OOR register  *****************/

+

+#define DMA2D_OOR_LO_Pos           (0U)

+#define DMA2D_OOR_LO_Msk           (0xFFFFUL << DMA2D_OOR_LO_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Output Line Offset */

+

+/********************  Bit definition for DMA2D_NLR register  *****************/

+

+#define DMA2D_NLR_NL_Pos           (0U)

+#define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */

+#define DMA2D_NLR_PL_Pos           (16U)

+#define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)              /*!< 0x3FFF0000 */

+#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */

+

+/********************  Bit definition for DMA2D_LWR register  *****************/

+

+#define DMA2D_LWR_LW_Pos           (0U)

+#define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */

+

+/********************  Bit definition for DMA2D_AMTCR register  ***************/

+

+#define DMA2D_AMTCR_EN_Pos         (0U)

+#define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)               /*!< 0x00000001 */

+#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */

+#define DMA2D_AMTCR_DT_Pos         (8U)

+#define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)              /*!< 0x0000FF00 */

+#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */

+

+

+/********************  Bit definition for DMA2D_FGCLUT register  **************/

+

+/********************  Bit definition for DMA2D_BGCLUT register  **************/

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                    External Interrupt/Event Controller                     */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for EXTI_RTSR1 register  *******************/

+#define EXTI_RTSR1_TR_Pos          (0U)

+#define EXTI_RTSR1_TR_Msk          (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)           /*!< 0x003FFFFF */

+#define EXTI_RTSR1_TR              EXTI_RTSR1_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR1_TR0_Pos         (0U)

+#define EXTI_RTSR1_TR0_Msk         (0x1UL << EXTI_RTSR1_TR0_Pos)               /*!< 0x00000001 */

+#define EXTI_RTSR1_TR0             EXTI_RTSR1_TR0_Msk                          /*!< Rising trigger event configuration bit of line 0 */

+#define EXTI_RTSR1_TR1_Pos         (1U)

+#define EXTI_RTSR1_TR1_Msk         (0x1UL << EXTI_RTSR1_TR1_Pos)               /*!< 0x00000002 */

+#define EXTI_RTSR1_TR1             EXTI_RTSR1_TR1_Msk                          /*!< Rising trigger event configuration bit of line 1 */

+#define EXTI_RTSR1_TR2_Pos         (2U)

+#define EXTI_RTSR1_TR2_Msk         (0x1UL << EXTI_RTSR1_TR2_Pos)               /*!< 0x00000004 */

+#define EXTI_RTSR1_TR2             EXTI_RTSR1_TR2_Msk                          /*!< Rising trigger event configuration bit of line 2 */

+#define EXTI_RTSR1_TR3_Pos         (3U)

+#define EXTI_RTSR1_TR3_Msk         (0x1UL << EXTI_RTSR1_TR3_Pos)               /*!< 0x00000008 */

+#define EXTI_RTSR1_TR3             EXTI_RTSR1_TR3_Msk                          /*!< Rising trigger event configuration bit of line 3 */

+#define EXTI_RTSR1_TR4_Pos         (4U)

+#define EXTI_RTSR1_TR4_Msk         (0x1UL << EXTI_RTSR1_TR4_Pos)               /*!< 0x00000010 */

+#define EXTI_RTSR1_TR4             EXTI_RTSR1_TR4_Msk                          /*!< Rising trigger event configuration bit of line 4 */

+#define EXTI_RTSR1_TR5_Pos         (5U)

+#define EXTI_RTSR1_TR5_Msk         (0x1UL << EXTI_RTSR1_TR5_Pos)               /*!< 0x00000020 */

+#define EXTI_RTSR1_TR5             EXTI_RTSR1_TR5_Msk                          /*!< Rising trigger event configuration bit of line 5 */

+#define EXTI_RTSR1_TR6_Pos         (6U)

+#define EXTI_RTSR1_TR6_Msk         (0x1UL << EXTI_RTSR1_TR6_Pos)               /*!< 0x00000040 */

+#define EXTI_RTSR1_TR6             EXTI_RTSR1_TR6_Msk                          /*!< Rising trigger event configuration bit of line 6 */

+#define EXTI_RTSR1_TR7_Pos         (7U)

+#define EXTI_RTSR1_TR7_Msk         (0x1UL << EXTI_RTSR1_TR7_Pos)               /*!< 0x00000080 */

+#define EXTI_RTSR1_TR7             EXTI_RTSR1_TR7_Msk                          /*!< Rising trigger event configuration bit of line 7 */

+#define EXTI_RTSR1_TR8_Pos         (8U)

+#define EXTI_RTSR1_TR8_Msk         (0x1UL << EXTI_RTSR1_TR8_Pos)               /*!< 0x00000100 */

+#define EXTI_RTSR1_TR8             EXTI_RTSR1_TR8_Msk                          /*!< Rising trigger event configuration bit of line 8 */

+#define EXTI_RTSR1_TR9_Pos         (9U)

+#define EXTI_RTSR1_TR9_Msk         (0x1UL << EXTI_RTSR1_TR9_Pos)               /*!< 0x00000200 */

+#define EXTI_RTSR1_TR9             EXTI_RTSR1_TR9_Msk                          /*!< Rising trigger event configuration bit of line 9 */

+#define EXTI_RTSR1_TR10_Pos        (10U)

+#define EXTI_RTSR1_TR10_Msk        (0x1UL << EXTI_RTSR1_TR10_Pos)              /*!< 0x00000400 */

+#define EXTI_RTSR1_TR10            EXTI_RTSR1_TR10_Msk                         /*!< Rising trigger event configuration bit of line 10 */

+#define EXTI_RTSR1_TR11_Pos        (11U)

+#define EXTI_RTSR1_TR11_Msk        (0x1UL << EXTI_RTSR1_TR11_Pos)              /*!< 0x00000800 */

+#define EXTI_RTSR1_TR11            EXTI_RTSR1_TR11_Msk                         /*!< Rising trigger event configuration bit of line 11 */

+#define EXTI_RTSR1_TR12_Pos        (12U)

+#define EXTI_RTSR1_TR12_Msk        (0x1UL << EXTI_RTSR1_TR12_Pos)              /*!< 0x00001000 */

+#define EXTI_RTSR1_TR12            EXTI_RTSR1_TR12_Msk                         /*!< Rising trigger event configuration bit of line 12 */

+#define EXTI_RTSR1_TR13_Pos        (13U)

+#define EXTI_RTSR1_TR13_Msk        (0x1UL << EXTI_RTSR1_TR13_Pos)              /*!< 0x00002000 */

+#define EXTI_RTSR1_TR13            EXTI_RTSR1_TR13_Msk                         /*!< Rising trigger event configuration bit of line 13 */

+#define EXTI_RTSR1_TR14_Pos        (14U)

+#define EXTI_RTSR1_TR14_Msk        (0x1UL << EXTI_RTSR1_TR14_Pos)              /*!< 0x00004000 */

+#define EXTI_RTSR1_TR14            EXTI_RTSR1_TR14_Msk                         /*!< Rising trigger event configuration bit of line 14 */

+#define EXTI_RTSR1_TR15_Pos        (15U)

+#define EXTI_RTSR1_TR15_Msk        (0x1UL << EXTI_RTSR1_TR15_Pos)              /*!< 0x00008000 */

+#define EXTI_RTSR1_TR15            EXTI_RTSR1_TR15_Msk                         /*!< Rising trigger event configuration bit of line 15 */

+#define EXTI_RTSR1_TR16_Pos        (16U)

+#define EXTI_RTSR1_TR16_Msk        (0x1UL << EXTI_RTSR1_TR16_Pos)              /*!< 0x00010000 */

+#define EXTI_RTSR1_TR16            EXTI_RTSR1_TR16_Msk                         /*!< Rising trigger event configuration bit of line 16 */

+#define EXTI_RTSR1_TR17_Pos        (17U)

+#define EXTI_RTSR1_TR17_Msk        (0x1UL << EXTI_RTSR1_TR17_Pos)              /*!< 0x00020000 */

+#define EXTI_RTSR1_TR17            EXTI_RTSR1_TR17_Msk                         /*!< Rising trigger event configuration bit of line 17 */

+#define EXTI_RTSR1_TR18_Pos        (18U)

+#define EXTI_RTSR1_TR18_Msk        (0x1UL << EXTI_RTSR1_TR18_Pos)              /*!< 0x00040000 */

+#define EXTI_RTSR1_TR18            EXTI_RTSR1_TR18_Msk                         /*!< Rising trigger event configuration bit of line 18 */

+#define EXTI_RTSR1_TR19_Pos        (19U)

+#define EXTI_RTSR1_TR19_Msk        (0x1UL << EXTI_RTSR1_TR19_Pos)              /*!< 0x00080000 */

+#define EXTI_RTSR1_TR19            EXTI_RTSR1_TR19_Msk                         /*!< Rising trigger event configuration bit of line 19 */

+#define EXTI_RTSR1_TR20_Pos        (20U)

+#define EXTI_RTSR1_TR20_Msk        (0x1UL << EXTI_RTSR1_TR20_Pos)              /*!< 0x00100000 */

+#define EXTI_RTSR1_TR20            EXTI_RTSR1_TR20_Msk                         /*!< Rising trigger event configuration bit of line 20 */

+#define EXTI_RTSR1_TR21_Pos        (21U)

+#define EXTI_RTSR1_TR21_Msk        (0x1UL << EXTI_RTSR1_TR21_Pos)              /*!< 0x00200000 */

+#define EXTI_RTSR1_TR21            EXTI_RTSR1_TR21_Msk                         /*!< Rising trigger event configuration bit of line 21 */

+

+/******************  Bit definition for EXTI_FTSR1 register  *******************/

+#define EXTI_FTSR1_TR_Pos          (0U)

+#define EXTI_FTSR1_TR_Msk          (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)           /*!< 0x003FFFFF */

+#define EXTI_FTSR1_TR              EXTI_FTSR1_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR1_TR0_Pos         (0U)

+#define EXTI_FTSR1_TR0_Msk         (0x1UL << EXTI_FTSR1_TR0_Pos)               /*!< 0x00000001 */

+#define EXTI_FTSR1_TR0             EXTI_FTSR1_TR0_Msk                          /*!< Falling trigger event configuration bit of line 0 */

+#define EXTI_FTSR1_TR1_Pos         (1U)

+#define EXTI_FTSR1_TR1_Msk         (0x1UL << EXTI_FTSR1_TR1_Pos)               /*!< 0x00000002 */

+#define EXTI_FTSR1_TR1             EXTI_FTSR1_TR1_Msk                          /*!< Falling trigger event configuration bit of line 1 */

+#define EXTI_FTSR1_TR2_Pos         (2U)

+#define EXTI_FTSR1_TR2_Msk         (0x1UL << EXTI_FTSR1_TR2_Pos)               /*!< 0x00000004 */

+#define EXTI_FTSR1_TR2             EXTI_FTSR1_TR2_Msk                          /*!< Falling trigger event configuration bit of line 2 */

+#define EXTI_FTSR1_TR3_Pos         (3U)

+#define EXTI_FTSR1_TR3_Msk         (0x1UL << EXTI_FTSR1_TR3_Pos)               /*!< 0x00000008 */

+#define EXTI_FTSR1_TR3             EXTI_FTSR1_TR3_Msk                          /*!< Falling trigger event configuration bit of line 3 */

+#define EXTI_FTSR1_TR4_Pos         (4U)

+#define EXTI_FTSR1_TR4_Msk         (0x1UL << EXTI_FTSR1_TR4_Pos)               /*!< 0x00000010 */

+#define EXTI_FTSR1_TR4             EXTI_FTSR1_TR4_Msk                          /*!< Falling trigger event configuration bit of line 4 */

+#define EXTI_FTSR1_TR5_Pos         (5U)

+#define EXTI_FTSR1_TR5_Msk         (0x1UL << EXTI_FTSR1_TR5_Pos)               /*!< 0x00000020 */

+#define EXTI_FTSR1_TR5             EXTI_FTSR1_TR5_Msk                          /*!< Falling trigger event configuration bit of line 5 */

+#define EXTI_FTSR1_TR6_Pos         (6U)

+#define EXTI_FTSR1_TR6_Msk         (0x1UL << EXTI_FTSR1_TR6_Pos)               /*!< 0x00000040 */

+#define EXTI_FTSR1_TR6             EXTI_FTSR1_TR6_Msk                          /*!< Falling trigger event configuration bit of line 6 */

+#define EXTI_FTSR1_TR7_Pos         (7U)

+#define EXTI_FTSR1_TR7_Msk         (0x1UL << EXTI_FTSR1_TR7_Pos)               /*!< 0x00000080 */

+#define EXTI_FTSR1_TR7             EXTI_FTSR1_TR7_Msk                          /*!< Falling trigger event configuration bit of line 7 */

+#define EXTI_FTSR1_TR8_Pos         (8U)

+#define EXTI_FTSR1_TR8_Msk         (0x1UL << EXTI_FTSR1_TR8_Pos)               /*!< 0x00000100 */

+#define EXTI_FTSR1_TR8             EXTI_FTSR1_TR8_Msk                          /*!< Falling trigger event configuration bit of line 8 */

+#define EXTI_FTSR1_TR9_Pos         (9U)

+#define EXTI_FTSR1_TR9_Msk         (0x1UL << EXTI_FTSR1_TR9_Pos)               /*!< 0x00000200 */

+#define EXTI_FTSR1_TR9             EXTI_FTSR1_TR9_Msk                          /*!< Falling trigger event configuration bit of line 9 */

+#define EXTI_FTSR1_TR10_Pos        (10U)

+#define EXTI_FTSR1_TR10_Msk        (0x1UL << EXTI_FTSR1_TR10_Pos)              /*!< 0x00000400 */

+#define EXTI_FTSR1_TR10            EXTI_FTSR1_TR10_Msk                         /*!< Falling trigger event configuration bit of line 10 */

+#define EXTI_FTSR1_TR11_Pos        (11U)

+#define EXTI_FTSR1_TR11_Msk        (0x1UL << EXTI_FTSR1_TR11_Pos)              /*!< 0x00000800 */

+#define EXTI_FTSR1_TR11            EXTI_FTSR1_TR11_Msk                         /*!< Falling trigger event configuration bit of line 11 */

+#define EXTI_FTSR1_TR12_Pos        (12U)

+#define EXTI_FTSR1_TR12_Msk        (0x1UL << EXTI_FTSR1_TR12_Pos)              /*!< 0x00001000 */

+#define EXTI_FTSR1_TR12            EXTI_FTSR1_TR12_Msk                         /*!< Falling trigger event configuration bit of line 12 */

+#define EXTI_FTSR1_TR13_Pos        (13U)

+#define EXTI_FTSR1_TR13_Msk        (0x1UL << EXTI_FTSR1_TR13_Pos)              /*!< 0x00002000 */

+#define EXTI_FTSR1_TR13            EXTI_FTSR1_TR13_Msk                         /*!< Falling trigger event configuration bit of line 13 */

+#define EXTI_FTSR1_TR14_Pos        (14U)

+#define EXTI_FTSR1_TR14_Msk        (0x1UL << EXTI_FTSR1_TR14_Pos)              /*!< 0x00004000 */

+#define EXTI_FTSR1_TR14            EXTI_FTSR1_TR14_Msk                         /*!< Falling trigger event configuration bit of line 14 */

+#define EXTI_FTSR1_TR15_Pos        (15U)

+#define EXTI_FTSR1_TR15_Msk        (0x1UL << EXTI_FTSR1_TR15_Pos)              /*!< 0x00008000 */

+#define EXTI_FTSR1_TR15            EXTI_FTSR1_TR15_Msk                         /*!< Falling trigger event configuration bit of line 15 */

+#define EXTI_FTSR1_TR16_Pos        (16U)

+#define EXTI_FTSR1_TR16_Msk        (0x1UL << EXTI_FTSR1_TR16_Pos)              /*!< 0x00010000 */

+#define EXTI_FTSR1_TR16            EXTI_FTSR1_TR16_Msk                         /*!< Falling trigger event configuration bit of line 16 */

+#define EXTI_FTSR1_TR17_Pos        (17U)

+#define EXTI_FTSR1_TR17_Msk        (0x1UL << EXTI_FTSR1_TR17_Pos)              /*!< 0x00020000 */

+#define EXTI_FTSR1_TR17            EXTI_FTSR1_TR17_Msk                         /*!< Falling trigger event configuration bit of line 17 */

+#define EXTI_FTSR1_TR18_Pos        (18U)

+#define EXTI_FTSR1_TR18_Msk        (0x1UL << EXTI_FTSR1_TR18_Pos)              /*!< 0x00040000 */

+#define EXTI_FTSR1_TR18            EXTI_FTSR1_TR18_Msk                         /*!< Falling trigger event configuration bit of line 18 */

+#define EXTI_FTSR1_TR19_Pos        (19U)

+#define EXTI_FTSR1_TR19_Msk        (0x1UL << EXTI_FTSR1_TR19_Pos)              /*!< 0x00080000 */

+#define EXTI_FTSR1_TR19            EXTI_FTSR1_TR19_Msk                         /*!< Falling trigger event configuration bit of line 19 */

+#define EXTI_FTSR1_TR20_Pos        (20U)

+#define EXTI_FTSR1_TR20_Msk        (0x1UL << EXTI_FTSR1_TR20_Pos)              /*!< 0x00100000 */

+#define EXTI_FTSR1_TR20            EXTI_FTSR1_TR20_Msk                         /*!< Falling trigger event configuration bit of line 20 */

+#define EXTI_FTSR1_TR21_Pos        (21U)

+#define EXTI_FTSR1_TR21_Msk        (0x1UL << EXTI_FTSR1_TR21_Pos)              /*!< 0x00200000 */

+#define EXTI_FTSR1_TR21            EXTI_FTSR1_TR21_Msk                         /*!< Falling trigger event configuration bit of line 21 */

+

+/******************  Bit definition for EXTI_SWIER1 register  ******************/

+#define EXTI_SWIER1_SWIER0_Pos     (0U)

+#define EXTI_SWIER1_SWIER0_Msk     (0x1UL << EXTI_SWIER1_SWIER0_Pos)           /*!< 0x00000001 */

+#define EXTI_SWIER1_SWIER0         EXTI_SWIER1_SWIER0_Msk                      /*!< Software Interrupt on line 0 */

+#define EXTI_SWIER1_SWIER1_Pos     (1U)

+#define EXTI_SWIER1_SWIER1_Msk     (0x1UL << EXTI_SWIER1_SWIER1_Pos)           /*!< 0x00000002 */

+#define EXTI_SWIER1_SWIER1         EXTI_SWIER1_SWIER1_Msk                      /*!< Software Interrupt on line 1 */

+#define EXTI_SWIER1_SWIER2_Pos     (2U)

+#define EXTI_SWIER1_SWIER2_Msk     (0x1UL << EXTI_SWIER1_SWIER2_Pos)           /*!< 0x00000004 */

+#define EXTI_SWIER1_SWIER2         EXTI_SWIER1_SWIER2_Msk                      /*!< Software Interrupt on line 2 */

+#define EXTI_SWIER1_SWIER3_Pos     (3U)

+#define EXTI_SWIER1_SWIER3_Msk     (0x1UL << EXTI_SWIER1_SWIER3_Pos)           /*!< 0x00000008 */

+#define EXTI_SWIER1_SWIER3         EXTI_SWIER1_SWIER3_Msk                      /*!< Software Interrupt on line 3 */

+#define EXTI_SWIER1_SWIER4_Pos     (4U)

+#define EXTI_SWIER1_SWIER4_Msk     (0x1UL << EXTI_SWIER1_SWIER4_Pos)           /*!< 0x00000010 */

+#define EXTI_SWIER1_SWIER4         EXTI_SWIER1_SWIER4_Msk                      /*!< Software Interrupt on line 4 */

+#define EXTI_SWIER1_SWIER5_Pos     (5U)

+#define EXTI_SWIER1_SWIER5_Msk     (0x1UL << EXTI_SWIER1_SWIER5_Pos)           /*!< 0x00000020 */

+#define EXTI_SWIER1_SWIER5         EXTI_SWIER1_SWIER5_Msk                      /*!< Software Interrupt on line 5 */

+#define EXTI_SWIER1_SWIER6_Pos     (6U)

+#define EXTI_SWIER1_SWIER6_Msk     (0x1UL << EXTI_SWIER1_SWIER6_Pos)           /*!< 0x00000040 */

+#define EXTI_SWIER1_SWIER6         EXTI_SWIER1_SWIER6_Msk                      /*!< Software Interrupt on line 6 */

+#define EXTI_SWIER1_SWIER7_Pos     (7U)

+#define EXTI_SWIER1_SWIER7_Msk     (0x1UL << EXTI_SWIER1_SWIER7_Pos)           /*!< 0x00000080 */

+#define EXTI_SWIER1_SWIER7         EXTI_SWIER1_SWIER7_Msk                      /*!< Software Interrupt on line 7 */

+#define EXTI_SWIER1_SWIER8_Pos     (8U)

+#define EXTI_SWIER1_SWIER8_Msk     (0x1UL << EXTI_SWIER1_SWIER8_Pos)           /*!< 0x00000100 */

+#define EXTI_SWIER1_SWIER8         EXTI_SWIER1_SWIER8_Msk                      /*!< Software Interrupt on line 8 */

+#define EXTI_SWIER1_SWIER9_Pos     (9U)

+#define EXTI_SWIER1_SWIER9_Msk     (0x1UL << EXTI_SWIER1_SWIER9_Pos)           /*!< 0x00000200 */

+#define EXTI_SWIER1_SWIER9         EXTI_SWIER1_SWIER9_Msk                      /*!< Software Interrupt on line 9 */

+#define EXTI_SWIER1_SWIER10_Pos    (10U)

+#define EXTI_SWIER1_SWIER10_Msk    (0x1UL << EXTI_SWIER1_SWIER10_Pos)          /*!< 0x00000400 */

+#define EXTI_SWIER1_SWIER10        EXTI_SWIER1_SWIER10_Msk                     /*!< Software Interrupt on line 10 */

+#define EXTI_SWIER1_SWIER11_Pos    (11U)

+#define EXTI_SWIER1_SWIER11_Msk    (0x1UL << EXTI_SWIER1_SWIER11_Pos)          /*!< 0x00000800 */

+#define EXTI_SWIER1_SWIER11        EXTI_SWIER1_SWIER11_Msk                     /*!< Software Interrupt on line 11 */

+#define EXTI_SWIER1_SWIER12_Pos    (12U)

+#define EXTI_SWIER1_SWIER12_Msk    (0x1UL << EXTI_SWIER1_SWIER12_Pos)          /*!< 0x00001000 */

+#define EXTI_SWIER1_SWIER12        EXTI_SWIER1_SWIER12_Msk                     /*!< Software Interrupt on line 12 */

+#define EXTI_SWIER1_SWIER13_Pos    (13U)

+#define EXTI_SWIER1_SWIER13_Msk    (0x1UL << EXTI_SWIER1_SWIER13_Pos)          /*!< 0x00002000 */

+#define EXTI_SWIER1_SWIER13        EXTI_SWIER1_SWIER13_Msk                     /*!< Software Interrupt on line 13 */

+#define EXTI_SWIER1_SWIER14_Pos    (14U)

+#define EXTI_SWIER1_SWIER14_Msk    (0x1UL << EXTI_SWIER1_SWIER14_Pos)          /*!< 0x00004000 */

+#define EXTI_SWIER1_SWIER14        EXTI_SWIER1_SWIER14_Msk                     /*!< Software Interrupt on line 14 */

+#define EXTI_SWIER1_SWIER15_Pos    (15U)

+#define EXTI_SWIER1_SWIER15_Msk    (0x1UL << EXTI_SWIER1_SWIER15_Pos)          /*!< 0x00008000 */

+#define EXTI_SWIER1_SWIER15        EXTI_SWIER1_SWIER15_Msk                     /*!< Software Interrupt on line 15 */

+#define EXTI_SWIER1_SWIER16_Pos    (16U)

+#define EXTI_SWIER1_SWIER16_Msk    (0x1UL << EXTI_SWIER1_SWIER16_Pos)          /*!< 0x00010000 */

+#define EXTI_SWIER1_SWIER16        EXTI_SWIER1_SWIER16_Msk                     /*!< Software Interrupt on line 16 */

+#define EXTI_SWIER1_SWIER17_Pos    (17U)

+#define EXTI_SWIER1_SWIER17_Msk    (0x1UL << EXTI_SWIER1_SWIER17_Pos)          /*!< 0x00020000 */

+#define EXTI_SWIER1_SWIER17        EXTI_SWIER1_SWIER17_Msk                     /*!< Software Interrupt on line 17 */

+#define EXTI_SWIER1_SWIER18_Pos    (18U)

+#define EXTI_SWIER1_SWIER18_Msk    (0x1UL << EXTI_SWIER1_SWIER18_Pos)          /*!< 0x00040000 */

+#define EXTI_SWIER1_SWIER18        EXTI_SWIER1_SWIER18_Msk                     /*!< Software Interrupt on line 18 */

+#define EXTI_SWIER1_SWIER19_Pos    (19U)

+#define EXTI_SWIER1_SWIER19_Msk    (0x1UL << EXTI_SWIER1_SWIER19_Pos)          /*!< 0x00080000 */

+#define EXTI_SWIER1_SWIER19        EXTI_SWIER1_SWIER19_Msk                     /*!< Software Interrupt on line 19 */

+#define EXTI_SWIER1_SWIER20_Pos    (20U)

+#define EXTI_SWIER1_SWIER20_Msk    (0x1UL << EXTI_SWIER1_SWIER20_Pos)          /*!< 0x00100000 */

+#define EXTI_SWIER1_SWIER20        EXTI_SWIER1_SWIER20_Msk                     /*!< Software Interrupt on line 20 */

+#define EXTI_SWIER1_SWIER21_Pos    (21U)

+#define EXTI_SWIER1_SWIER21_Msk    (0x1UL << EXTI_SWIER1_SWIER21_Pos)          /*!< 0x00200000 */

+#define EXTI_SWIER1_SWIER21        EXTI_SWIER1_SWIER21_Msk                     /*!< Software Interrupt on line 21 */

+

+/******************  Bit definition for EXTI_D3PMR1 register  ******************/

+#define EXTI_D3PMR1_MR0_Pos        (0U)

+#define EXTI_D3PMR1_MR0_Msk        (0x1UL << EXTI_D3PMR1_MR0_Pos)              /*!< 0x00000001 */

+#define EXTI_D3PMR1_MR0            EXTI_D3PMR1_MR0_Msk                         /*!< Pending Mask Event for line 0  */

+#define EXTI_D3PMR1_MR1_Pos        (1U)

+#define EXTI_D3PMR1_MR1_Msk        (0x1UL << EXTI_D3PMR1_MR1_Pos)              /*!< 0x00000002 */

+#define EXTI_D3PMR1_MR1            EXTI_D3PMR1_MR1_Msk                         /*!< Pending Mask Event for line 1  */

+#define EXTI_D3PMR1_MR2_Pos        (2U)

+#define EXTI_D3PMR1_MR2_Msk        (0x1UL << EXTI_D3PMR1_MR2_Pos)              /*!< 0x00000004 */

+#define EXTI_D3PMR1_MR2            EXTI_D3PMR1_MR2_Msk                         /*!< Pending Mask Event for line 2  */

+#define EXTI_D3PMR1_MR3_Pos        (3U)

+#define EXTI_D3PMR1_MR3_Msk        (0x1UL << EXTI_D3PMR1_MR3_Pos)              /*!< 0x00000008 */

+#define EXTI_D3PMR1_MR3            EXTI_D3PMR1_MR3_Msk                         /*!< Pending Mask Event for line 3  */

+#define EXTI_D3PMR1_MR4_Pos        (4U)

+#define EXTI_D3PMR1_MR4_Msk        (0x1UL << EXTI_D3PMR1_MR4_Pos)              /*!< 0x00000010 */

+#define EXTI_D3PMR1_MR4            EXTI_D3PMR1_MR4_Msk                         /*!< Pending Mask Event for line 4  */

+#define EXTI_D3PMR1_MR5_Pos        (5U)

+#define EXTI_D3PMR1_MR5_Msk        (0x1UL << EXTI_D3PMR1_MR5_Pos)              /*!< 0x00000020 */

+#define EXTI_D3PMR1_MR5            EXTI_D3PMR1_MR5_Msk                         /*!< Pending Mask Event for line 5  */

+#define EXTI_D3PMR1_MR6_Pos        (6U)

+#define EXTI_D3PMR1_MR6_Msk        (0x1UL << EXTI_D3PMR1_MR6_Pos)              /*!< 0x00000040 */

+#define EXTI_D3PMR1_MR6            EXTI_D3PMR1_MR6_Msk                         /*!< Pending Mask Event for line 6  */

+#define EXTI_D3PMR1_MR7_Pos        (7U)

+#define EXTI_D3PMR1_MR7_Msk        (0x1UL << EXTI_D3PMR1_MR7_Pos)              /*!< 0x00000080 */

+#define EXTI_D3PMR1_MR7            EXTI_D3PMR1_MR7_Msk                         /*!< Pending Mask Event for line 7  */

+#define EXTI_D3PMR1_MR8_Pos        (8U)

+#define EXTI_D3PMR1_MR8_Msk        (0x1UL << EXTI_D3PMR1_MR8_Pos)              /*!< 0x00000100 */

+#define EXTI_D3PMR1_MR8            EXTI_D3PMR1_MR8_Msk                         /*!< Pending Mask Event for line 8  */

+#define EXTI_D3PMR1_MR9_Pos        (9U)

+#define EXTI_D3PMR1_MR9_Msk        (0x1UL << EXTI_D3PMR1_MR9_Pos)              /*!< 0x00000200 */

+#define EXTI_D3PMR1_MR9            EXTI_D3PMR1_MR9_Msk                         /*!< Pending Mask Event for line 9  */

+#define EXTI_D3PMR1_MR10_Pos       (10U)

+#define EXTI_D3PMR1_MR10_Msk       (0x1UL << EXTI_D3PMR1_MR10_Pos)             /*!< 0x00000400 */

+#define EXTI_D3PMR1_MR10           EXTI_D3PMR1_MR10_Msk                        /*!< Pending Mask Event for line 10 */

+#define EXTI_D3PMR1_MR11_Pos       (11U)

+#define EXTI_D3PMR1_MR11_Msk       (0x1UL << EXTI_D3PMR1_MR11_Pos)             /*!< 0x00000800 */

+#define EXTI_D3PMR1_MR11           EXTI_D3PMR1_MR11_Msk                        /*!< Pending Mask Event for line 11 */

+#define EXTI_D3PMR1_MR12_Pos       (12U)

+#define EXTI_D3PMR1_MR12_Msk       (0x1UL << EXTI_D3PMR1_MR12_Pos)             /*!< 0x00001000 */

+#define EXTI_D3PMR1_MR12           EXTI_D3PMR1_MR12_Msk                        /*!< Pending Mask Event for line 12 */

+#define EXTI_D3PMR1_MR13_Pos       (13U)

+#define EXTI_D3PMR1_MR13_Msk       (0x1UL << EXTI_D3PMR1_MR13_Pos)             /*!< 0x00002000 */

+#define EXTI_D3PMR1_MR13           EXTI_D3PMR1_MR13_Msk                        /*!< Pending Mask Event for line 13 */

+#define EXTI_D3PMR1_MR14_Pos       (14U)

+#define EXTI_D3PMR1_MR14_Msk       (0x1UL << EXTI_D3PMR1_MR14_Pos)             /*!< 0x00004000 */

+#define EXTI_D3PMR1_MR14           EXTI_D3PMR1_MR14_Msk                        /*!< Pending Mask Event for line 14 */

+#define EXTI_D3PMR1_MR15_Pos       (15U)

+#define EXTI_D3PMR1_MR15_Msk       (0x1UL << EXTI_D3PMR1_MR15_Pos)             /*!< 0x00008000 */

+#define EXTI_D3PMR1_MR15           EXTI_D3PMR1_MR15_Msk                        /*!< Pending Mask Event for line 15 */

+#define EXTI_D3PMR1_MR19_Pos       (19U)

+#define EXTI_D3PMR1_MR19_Msk       (0x1UL << EXTI_D3PMR1_MR19_Pos)             /*!< 0x00080000 */

+#define EXTI_D3PMR1_MR19           EXTI_D3PMR1_MR19_Msk                        /*!< Pending Mask Event for line 19 */

+#define EXTI_D3PMR1_MR20_Pos       (20U)

+#define EXTI_D3PMR1_MR20_Msk       (0x1UL << EXTI_D3PMR1_MR20_Pos)             /*!< 0x00100000 */

+#define EXTI_D3PMR1_MR20           EXTI_D3PMR1_MR20_Msk                        /*!< Pending Mask Event for line 20 */

+#define EXTI_D3PMR1_MR21_Pos       (21U)

+#define EXTI_D3PMR1_MR21_Msk       (0x1UL << EXTI_D3PMR1_MR21_Pos)             /*!< 0x00200000 */

+#define EXTI_D3PMR1_MR21           EXTI_D3PMR1_MR21_Msk                        /*!< Pending Mask Event for line 21 */

+#define EXTI_D3PMR1_MR25_Pos       (24U)

+#define EXTI_D3PMR1_MR25_Msk       (0x1UL << EXTI_D3PMR1_MR25_Pos)             /*!< 0x01000000 */

+#define EXTI_D3PMR1_MR25           EXTI_D3PMR1_MR25_Msk                        /*!< Pending Mask Event for line 25 */

+

+/*******************  Bit definition for EXTI_D3PCR1L register  ****************/

+#define EXTI_D3PCR1L_PCS0_Pos       (0U)

+#define EXTI_D3PCR1L_PCS0_Msk       (0x3UL << EXTI_D3PCR1L_PCS0_Pos)           /*!< 0x00000003 */

+#define EXTI_D3PCR1L_PCS0           EXTI_D3PCR1L_PCS0_Msk                      /*!< D3 Pending request clear input signal selection on line 0 */

+#define EXTI_D3PCR1L_PCS1_Pos       (2U)

+#define EXTI_D3PCR1L_PCS1_Msk       (0x3UL << EXTI_D3PCR1L_PCS1_Pos)           /*!< 0x000000C0 */

+#define EXTI_D3PCR1L_PCS1           EXTI_D3PCR1L_PCS1_Msk                      /*!< D3 Pending request clear input signal selection on line 1 */

+#define EXTI_D3PCR1L_PCS2_Pos       (4U)

+#define EXTI_D3PCR1L_PCS2_Msk       (0x3UL << EXTI_D3PCR1L_PCS2_Pos)           /*!< 0x00000030 */

+#define EXTI_D3PCR1L_PCS2           EXTI_D3PCR1L_PCS2_Msk                      /*!< D3 Pending request clear input signal selection on line 2 */

+#define EXTI_D3PCR1L_PCS3_Pos       (6U)

+#define EXTI_D3PCR1L_PCS3_Msk       (0x3UL << EXTI_D3PCR1L_PCS3_Pos)           /*!< 0x000000C0 */

+#define EXTI_D3PCR1L_PCS3           EXTI_D3PCR1L_PCS3_Msk                      /*!< D3 Pending request clear input signal selection on line 3 */

+#define EXTI_D3PCR1L_PCS4_Pos       (8U)

+#define EXTI_D3PCR1L_PCS4_Msk       (0x3UL << EXTI_D3PCR1L_PCS4_Pos)           /*!< 0x00000300 */

+#define EXTI_D3PCR1L_PCS4           EXTI_D3PCR1L_PCS4_Msk                      /*!< D3 Pending request clear input signal selection on line 4 */

+#define EXTI_D3PCR1L_PCS5_Pos       (10U)

+#define EXTI_D3PCR1L_PCS5_Msk       (0x3UL << EXTI_D3PCR1L_PCS5_Pos)           /*!< 0x00000C00 */

+#define EXTI_D3PCR1L_PCS5           EXTI_D3PCR1L_PCS5_Msk                      /*!< D3 Pending request clear input signal selection on line 5 */

+#define EXTI_D3PCR1L_PCS6_Pos       (12U)

+#define EXTI_D3PCR1L_PCS6_Msk       (0x3UL << EXTI_D3PCR1L_PCS6_Pos)           /*!< 0x00003000 */

+#define EXTI_D3PCR1L_PCS6           EXTI_D3PCR1L_PCS6_Msk                      /*!< D3 Pending request clear input signal selection on line 6 */

+#define EXTI_D3PCR1L_PCS7_Pos       (14U)

+#define EXTI_D3PCR1L_PCS7_Msk       (0x3UL << EXTI_D3PCR1L_PCS7_Pos)           /*!< 0x0000C000 */

+#define EXTI_D3PCR1L_PCS7           EXTI_D3PCR1L_PCS7_Msk                      /*!< D3 Pending request clear input signal selection on line 7 */

+#define EXTI_D3PCR1L_PCS8_Pos       (16U)

+#define EXTI_D3PCR1L_PCS8_Msk       (0x3UL << EXTI_D3PCR1L_PCS8_Pos)           /*!< 0x00030000 */

+#define EXTI_D3PCR1L_PCS8           EXTI_D3PCR1L_PCS8_Msk                      /*!< D3 Pending request clear input signal selection on line 8 */

+#define EXTI_D3PCR1L_PCS9_Pos       (18U)

+#define EXTI_D3PCR1L_PCS9_Msk       (0x3UL << EXTI_D3PCR1L_PCS9_Pos)           /*!< 0x000C0000 */

+#define EXTI_D3PCR1L_PCS9           EXTI_D3PCR1L_PCS9_Msk                      /*!< D3 Pending request clear input signal selection on line 9 */

+#define EXTI_D3PCR1L_PCS10_Pos      (20U)

+#define EXTI_D3PCR1L_PCS10_Msk      (0x3UL << EXTI_D3PCR1L_PCS10_Pos)          /*!< 0x00300000 */

+#define EXTI_D3PCR1L_PCS10          EXTI_D3PCR1L_PCS10_Msk                     /*!< D3 Pending request clear input signal selection on line 10*/

+#define EXTI_D3PCR1L_PCS11_Pos      (22U)

+#define EXTI_D3PCR1L_PCS11_Msk      (0x3UL << EXTI_D3PCR1L_PCS11_Pos)          /*!< 0x00C00000 */

+#define EXTI_D3PCR1L_PCS11          EXTI_D3PCR1L_PCS11_Msk                     /*!< D3 Pending request clear input signal selection on line 11*/

+#define EXTI_D3PCR1L_PCS12_Pos      (24U)

+#define EXTI_D3PCR1L_PCS12_Msk      (0x3UL << EXTI_D3PCR1L_PCS12_Pos)          /*!< 0x03000000 */

+#define EXTI_D3PCR1L_PCS12          EXTI_D3PCR1L_PCS12_Msk                     /*!< D3 Pending request clear input signal selection on line 12*/

+#define EXTI_D3PCR1L_PCS13_Pos      (26U)

+#define EXTI_D3PCR1L_PCS13_Msk      (0x3UL << EXTI_D3PCR1L_PCS13_Pos)          /*!< 0x0C000000 */

+#define EXTI_D3PCR1L_PCS13          EXTI_D3PCR1L_PCS13_Msk                     /*!< D3 Pending request clear input signal selection on line 13*/

+#define EXTI_D3PCR1L_PCS14_Pos      (28U)

+#define EXTI_D3PCR1L_PCS14_Msk      (0x3UL << EXTI_D3PCR1L_PCS14_Pos)          /*!< 0x30000000 */

+#define EXTI_D3PCR1L_PCS14          EXTI_D3PCR1L_PCS14_Msk                     /*!< D3 Pending request clear input signal selection on line 14*/

+#define EXTI_D3PCR1L_PCS15_Pos      (30U)

+#define EXTI_D3PCR1L_PCS15_Msk      (0x3UL << EXTI_D3PCR1L_PCS15_Pos)          /*!< 0xC0000000 */

+#define EXTI_D3PCR1L_PCS15          EXTI_D3PCR1L_PCS15_Msk                     /*!< D3 Pending request clear input signal selection on line 15*/

+

+/*******************  Bit definition for EXTI_D3PCR1H register  ****************/

+#define EXTI_D3PCR1H_PCS19_Pos       (6U)

+#define EXTI_D3PCR1H_PCS19_Msk       (0x3UL << EXTI_D3PCR1H_PCS19_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR1H_PCS19           EXTI_D3PCR1H_PCS19_Msk                    /*!< D3 Pending request clear input signal selection on line 19 */

+#define EXTI_D3PCR1H_PCS20_Pos       (8U)

+#define EXTI_D3PCR1H_PCS20_Msk       (0x3UL << EXTI_D3PCR1H_PCS20_Pos)         /*!< 0x00000300 */

+#define EXTI_D3PCR1H_PCS20           EXTI_D3PCR1H_PCS20_Msk                    /*!< D3 Pending request clear input signal selection on line 20 */

+#define EXTI_D3PCR1H_PCS21_Pos       (10U)

+#define EXTI_D3PCR1H_PCS21_Msk       (0x3UL << EXTI_D3PCR1H_PCS21_Pos)         /*!< 0x00000C00 */

+#define EXTI_D3PCR1H_PCS21           EXTI_D3PCR1H_PCS21_Msk                    /*!< D3 Pending request clear input signal selection on line 21 */

+#define EXTI_D3PCR1H_PCS25_Pos       (18U)

+#define EXTI_D3PCR1H_PCS25_Msk       (0x3UL << EXTI_D3PCR1H_PCS25_Pos)         /*!< 0x000C0000 */

+#define EXTI_D3PCR1H_PCS25           EXTI_D3PCR1H_PCS25_Msk                    /*!< D3 Pending request clear input signal selection on line 25 */

+

+/******************  Bit definition for EXTI_RTSR2 register  *******************/

+#define EXTI_RTSR2_TR_Pos          (17U)

+#define EXTI_RTSR2_TR_Msk          (0x5UL << EXTI_RTSR2_TR_Pos)                /*!< 0x000A0000 */

+#define EXTI_RTSR2_TR              EXTI_RTSR2_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR2_TR49_Pos        (17U)

+#define EXTI_RTSR2_TR49_Msk        (0x1UL << EXTI_RTSR2_TR49_Pos)              /*!< 0x00020000 */

+#define EXTI_RTSR2_TR49            EXTI_RTSR2_TR49_Msk                         /*!< Rising trigger event configuration bit of line 49 */

+#define EXTI_RTSR2_TR51_Pos        (19U)

+#define EXTI_RTSR2_TR51_Msk        (0x1UL << EXTI_RTSR2_TR51_Pos)              /*!< 0x00080000 */

+#define EXTI_RTSR2_TR51            EXTI_RTSR2_TR51_Msk                         /*!< Rising trigger event configuration bit of line 51 */

+

+/******************  Bit definition for EXTI_FTSR2 register  *******************/

+#define EXTI_FTSR2_TR_Pos          (17U)

+#define EXTI_FTSR2_TR_Msk          (0x5UL << EXTI_FTSR2_TR_Pos)                /*!< 0x000A0000 */

+#define EXTI_FTSR2_TR              EXTI_FTSR2_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR2_TR49_Pos        (17U)

+#define EXTI_FTSR2_TR49_Msk        (0x1UL << EXTI_FTSR2_TR49_Pos)              /*!< 0x00020000 */

+#define EXTI_FTSR2_TR49            EXTI_FTSR2_TR49_Msk                         /*!< Falling trigger event configuration bit of line 49 */

+#define EXTI_FTSR2_TR51_Pos        (19U)

+#define EXTI_FTSR2_TR51_Msk        (0x1UL << EXTI_FTSR2_TR51_Pos)              /*!< 0x00080000 */

+#define EXTI_FTSR2_TR51            EXTI_FTSR2_TR51_Msk                         /*!< Falling trigger event configuration bit of line 51 */

+

+/******************  Bit definition for EXTI_SWIER2 register  ******************/

+#define EXTI_SWIER2_SWIER49_Pos    (17U)

+#define EXTI_SWIER2_SWIER49_Msk    (0x1UL << EXTI_SWIER2_SWIER49_Pos)          /*!< 0x00020000 */

+#define EXTI_SWIER2_SWIER49        EXTI_SWIER2_SWIER49_Msk                     /*!< Software Interrupt on line 49 */

+#define EXTI_SWIER2_SWIER51_Pos    (19U)

+#define EXTI_SWIER2_SWIER51_Msk    (0x1UL << EXTI_SWIER2_SWIER51_Pos)          /*!< 0x00080000 */

+#define EXTI_SWIER2_SWIER51        EXTI_SWIER2_SWIER51_Msk                     /*!< Software Interrupt on line 51 */

+

+/******************  Bit definition for EXTI_D3PMR2 register  ******************/

+#define EXTI_D3PMR2_MR34_Pos       (2U)

+#define EXTI_D3PMR2_MR34_Msk       (0x1UL << EXTI_D3PMR2_MR34_Pos)             /*!< 0x00000004 */

+#define EXTI_D3PMR2_MR34           EXTI_D3PMR2_MR34_Msk                        /*!< Pending Mask Event for line 34  */

+#define EXTI_D3PMR2_MR35_Pos       (3U)

+#define EXTI_D3PMR2_MR35_Msk       (0x1UL << EXTI_D3PMR2_MR35_Pos)             /*!< 0x00000008 */

+#define EXTI_D3PMR2_MR35           EXTI_D3PMR2_MR35_Msk                        /*!< Pending Mask Event for line 35  */

+#define EXTI_D3PMR2_MR41_Pos       (9U)

+#define EXTI_D3PMR2_MR41_Msk       (0x1UL << EXTI_D3PMR2_MR41_Pos)             /*!< 0x00000200 */

+#define EXTI_D3PMR2_MR41           EXTI_D3PMR2_MR41_Msk                        /*!< Pending Mask Event for line 41  */

+#define EXTI_D3PMR2_MR48_Pos       (16U)

+#define EXTI_D3PMR2_MR48_Msk       (0x1UL << EXTI_D3PMR2_MR48_Pos)             /*!< 0x00010000 */

+#define EXTI_D3PMR2_MR48           EXTI_D3PMR2_MR48_Msk                        /*!< Pending Mask Event for line 48  */

+#define EXTI_D3PMR2_MR49_Pos       (17U)

+#define EXTI_D3PMR2_MR49_Msk       (0x1UL << EXTI_D3PMR2_MR49_Pos)             /*!< 0x00020000 */

+#define EXTI_D3PMR2_MR49           EXTI_D3PMR2_MR49_Msk                        /*!< Pending Mask Event for line 49  */

+#define EXTI_D3PMR2_MR50_Pos       (18U)

+#define EXTI_D3PMR2_MR50_Msk       (0x1UL << EXTI_D3PMR2_MR50_Pos)             /*!< 0x00040000 */

+#define EXTI_D3PMR2_MR50           EXTI_D3PMR2_MR50_Msk                        /*!< Pending Mask Event for line 50  */

+#define EXTI_D3PMR2_MR51_Pos       (19U)

+#define EXTI_D3PMR2_MR51_Msk       (0x1UL << EXTI_D3PMR2_MR51_Pos)             /*!< 0x00080000 */

+#define EXTI_D3PMR2_MR51           EXTI_D3PMR2_MR51_Msk                        /*!< Pending Mask Event for line 51  */

+/*******************  Bit definition for EXTI_D3PCR2L register  ****************/

+#define EXTI_D3PCR2L_PCS34_Pos       (4U)

+#define EXTI_D3PCR2L_PCS34_Msk       (0x3UL << EXTI_D3PCR2L_PCS34_Pos)         /*!< 0x00000030 */

+#define EXTI_D3PCR2L_PCS34           EXTI_D3PCR2L_PCS34_Msk                    /*!< D3 Pending request clear input signal selection on line 34 */

+#define EXTI_D3PCR2L_PCS35_Pos       (6U)

+#define EXTI_D3PCR2L_PCS35_Msk       (0x3UL << EXTI_D3PCR2L_PCS35_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR2L_PCS35           EXTI_D3PCR2L_PCS35_Msk                    /*!< D3 Pending request clear input signal selection on line 35 */

+#define EXTI_D3PCR2L_PCS41_Pos       (18U)

+#define EXTI_D3PCR2L_PCS41_Msk       (0x3UL << EXTI_D3PCR2L_PCS41_Pos)         /*!< 0x000C0000 */

+#define EXTI_D3PCR2L_PCS41           EXTI_D3PCR2L_PCS41_Msk                    /*!< D3 Pending request clear input signal selection on line 41 */

+

+

+/*******************  Bit definition for EXTI_D3PCR2H register  ****************/

+#define EXTI_D3PCR2H_PCS48_Pos       (0U)

+#define EXTI_D3PCR2H_PCS48_Msk       (0x3UL << EXTI_D3PCR2H_PCS48_Pos)         /*!< 0x00000003 */

+#define EXTI_D3PCR2H_PCS48           EXTI_D3PCR2H_PCS48_Msk                    /*!< D3 Pending request clear input signal selection on line 48 */

+#define EXTI_D3PCR2H_PCS49_Pos       (2U)

+#define EXTI_D3PCR2H_PCS49_Msk       (0x3UL << EXTI_D3PCR2H_PCS49_Pos)         /*!< 0x0000000C */

+#define EXTI_D3PCR2H_PCS49           EXTI_D3PCR2H_PCS49_Msk                    /*!< D3 Pending request clear input signal selection on line 49 */

+#define EXTI_D3PCR2H_PCS50_Pos       (4U)

+#define EXTI_D3PCR2H_PCS50_Msk       (0x3UL << EXTI_D3PCR2H_PCS50_Pos)         /*!< 0x00000030 */

+#define EXTI_D3PCR2H_PCS50           EXTI_D3PCR2H_PCS50_Msk                    /*!< D3 Pending request clear input signal selection on line 50 */

+#define EXTI_D3PCR2H_PCS51_Pos       (6U)

+#define EXTI_D3PCR2H_PCS51_Msk       (0x3UL << EXTI_D3PCR2H_PCS51_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR2H_PCS51           EXTI_D3PCR2H_PCS51_Msk                    /*!< D3 Pending request clear input signal selection on line 51 */

+/******************  Bit definition for EXTI_RTSR3 register  *******************/

+#define EXTI_RTSR3_TR_Pos          (18U)

+#define EXTI_RTSR3_TR_Msk          (0x9UL << EXTI_RTSR3_TR_Pos)                /*!< 0x00240000 */

+#define EXTI_RTSR3_TR              EXTI_RTSR3_TR_Msk                           /*!< Rising trigger event configuration bit            */

+#define EXTI_RTSR3_TR82_Pos        (18U)

+#define EXTI_RTSR3_TR82_Msk        (0x1UL << EXTI_RTSR3_TR82_Pos)              /*!< 0x00040000 */

+#define EXTI_RTSR3_TR82            EXTI_RTSR3_TR82_Msk                         /*!< Rising trigger event configuration bit of line 82 */

+#define EXTI_RTSR3_TR85_Pos        (21U)

+#define EXTI_RTSR3_TR85_Msk        (0x1UL << EXTI_RTSR3_TR85_Pos)              /*!< 0x00200000 */

+#define EXTI_RTSR3_TR85            EXTI_RTSR3_TR85_Msk                         /*!< Rising trigger event configuration bit of line 85 */

+

+/******************  Bit definition for EXTI_FTSR3 register  *******************/

+#define EXTI_FTSR3_TR_Pos          (18U)

+#define EXTI_FTSR3_TR_Msk          (0x9UL << EXTI_FTSR3_TR_Pos)                /*!< 0x00240000 */

+#define EXTI_FTSR3_TR              EXTI_FTSR3_TR_Msk                           /*!< Falling trigger event configuration bit            */

+#define EXTI_FTSR3_TR82_Pos        (18U)

+#define EXTI_FTSR3_TR82_Msk        (0x1UL << EXTI_FTSR3_TR82_Pos)              /*!< 0x00040000 */

+#define EXTI_FTSR3_TR82            EXTI_FTSR3_TR82_Msk                         /*!< Falling trigger event configuration bit of line 82 */

+#define EXTI_FTSR3_TR85_Pos        (21U)

+#define EXTI_FTSR3_TR85_Msk        (0x1UL << EXTI_FTSR3_TR85_Pos)              /*!< 0x00200000 */

+#define EXTI_FTSR3_TR85            EXTI_FTSR3_TR85_Msk                         /*!< Falling trigger event configuration bit of line 85 */

+

+/******************  Bit definition for EXTI_SWIER3 register  ******************/

+#define EXTI_SWIER3_SWI_Pos        (18U)

+#define EXTI_SWIER3_SWI_Msk        (0x9UL << EXTI_SWIER3_SWI_Pos)              /*!< 0x00240000 */

+#define EXTI_SWIER3_SWI            EXTI_SWIER3_SWI_Msk                         /*!< Software Interrupt event bit */

+#define EXTI_SWIER3_SWIER82_Pos    (18U)

+#define EXTI_SWIER3_SWIER82_Msk    (0x1UL << EXTI_SWIER3_SWIER82_Pos)          /*!< 0x00040000 */

+#define EXTI_SWIER3_SWIER82        EXTI_SWIER3_SWIER82_Msk                     /*!< Software Interrupt on line 82 */

+#define EXTI_SWIER3_SWIER85_Pos    (21U)

+#define EXTI_SWIER3_SWIER85_Msk    (0x1UL << EXTI_SWIER3_SWIER85_Pos)          /*!< 0x00200000 */

+#define EXTI_SWIER3_SWIER85        EXTI_SWIER3_SWIER85_Msk                     /*!< Software Interrupt on line 85 */

+

+/******************  Bit definition for EXTI_D3PMR3 register  ******************/

+#define EXTI_D3PMR3_MR88_Pos       (24U)

+#define EXTI_D3PMR3_MR88_Msk       (0x1UL << EXTI_D3PMR3_MR88_Pos)             /*!< 0x01000000 */

+#define EXTI_D3PMR3_MR88           EXTI_D3PMR3_MR88_Msk                        /*!< Pending Mask Event for line 88  */

+

+/*******************  Bit definition for EXTI_D3PCR3H register  ****************/

+#define EXTI_D3PCR3H_PCS88_Pos       (16U)

+#define EXTI_D3PCR3H_PCS88_Msk       (0x3UL << EXTI_D3PCR3H_PCS88_Pos)         /*!< 0x00030000 */

+#define EXTI_D3PCR3H_PCS88           EXTI_D3PCR3H_PCS88_Msk                    /*!< D3 Pending request clear input signal selection on line 88 */

+

+/*******************  Bit definition for EXTI_IMR1 register  *******************/

+#define EXTI_IMR1_IM_Pos           (0U)

+#define EXTI_IMR1_IM_Msk           (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)          /*!< 0xFFFFFFFF */

+#define EXTI_IMR1_IM               EXTI_IMR1_IM_Msk                            /*!< Interrupt Mask */

+#define EXTI_IMR1_IM0_Pos          (0U)

+#define EXTI_IMR1_IM0_Msk          (0x1UL << EXTI_IMR1_IM0_Pos)                /*!< 0x00000001 */

+#define EXTI_IMR1_IM0              EXTI_IMR1_IM0_Msk                           /*!< Interrupt Mask on line 0 */

+#define EXTI_IMR1_IM1_Pos          (1U)

+#define EXTI_IMR1_IM1_Msk          (0x1UL << EXTI_IMR1_IM1_Pos)                /*!< 0x00000002 */

+#define EXTI_IMR1_IM1              EXTI_IMR1_IM1_Msk                           /*!< Interrupt Mask on line 1 */

+#define EXTI_IMR1_IM2_Pos          (2U)

+#define EXTI_IMR1_IM2_Msk          (0x1UL << EXTI_IMR1_IM2_Pos)                /*!< 0x00000004 */

+#define EXTI_IMR1_IM2              EXTI_IMR1_IM2_Msk                           /*!< Interrupt Mask on line 2 */

+#define EXTI_IMR1_IM3_Pos          (3U)

+#define EXTI_IMR1_IM3_Msk          (0x1UL << EXTI_IMR1_IM3_Pos)                /*!< 0x00000008 */

+#define EXTI_IMR1_IM3              EXTI_IMR1_IM3_Msk                           /*!< Interrupt Mask on line 3 */

+#define EXTI_IMR1_IM4_Pos          (4U)

+#define EXTI_IMR1_IM4_Msk          (0x1UL << EXTI_IMR1_IM4_Pos)                /*!< 0x00000010 */

+#define EXTI_IMR1_IM4              EXTI_IMR1_IM4_Msk                           /*!< Interrupt Mask on line 4 */

+#define EXTI_IMR1_IM5_Pos          (5U)

+#define EXTI_IMR1_IM5_Msk          (0x1UL << EXTI_IMR1_IM5_Pos)                /*!< 0x00000020 */

+#define EXTI_IMR1_IM5              EXTI_IMR1_IM5_Msk                           /*!< Interrupt Mask on line 5 */

+#define EXTI_IMR1_IM6_Pos          (6U)

+#define EXTI_IMR1_IM6_Msk          (0x1UL << EXTI_IMR1_IM6_Pos)                /*!< 0x00000040 */

+#define EXTI_IMR1_IM6              EXTI_IMR1_IM6_Msk                           /*!< Interrupt Mask on line 6 */

+#define EXTI_IMR1_IM7_Pos          (7U)

+#define EXTI_IMR1_IM7_Msk          (0x1UL << EXTI_IMR1_IM7_Pos)                /*!< 0x00000080 */

+#define EXTI_IMR1_IM7              EXTI_IMR1_IM7_Msk                           /*!< Interrupt Mask on line 7 */

+#define EXTI_IMR1_IM8_Pos          (8U)

+#define EXTI_IMR1_IM8_Msk          (0x1UL << EXTI_IMR1_IM8_Pos)                /*!< 0x00000100 */

+#define EXTI_IMR1_IM8              EXTI_IMR1_IM8_Msk                           /*!< Interrupt Mask on line 8 */

+#define EXTI_IMR1_IM9_Pos          (9U)

+#define EXTI_IMR1_IM9_Msk          (0x1UL << EXTI_IMR1_IM9_Pos)                /*!< 0x00000200 */

+#define EXTI_IMR1_IM9              EXTI_IMR1_IM9_Msk                           /*!< Interrupt Mask on line 9 */

+#define EXTI_IMR1_IM10_Pos         (10U)

+#define EXTI_IMR1_IM10_Msk         (0x1UL << EXTI_IMR1_IM10_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR1_IM10             EXTI_IMR1_IM10_Msk                          /*!< Interrupt Mask on line 10 */

+#define EXTI_IMR1_IM11_Pos         (11U)

+#define EXTI_IMR1_IM11_Msk         (0x1UL << EXTI_IMR1_IM11_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR1_IM11             EXTI_IMR1_IM11_Msk                          /*!< Interrupt Mask on line 11 */

+#define EXTI_IMR1_IM12_Pos         (12U)

+#define EXTI_IMR1_IM12_Msk         (0x1UL << EXTI_IMR1_IM12_Pos)               /*!< 0x00001000 */

+#define EXTI_IMR1_IM12             EXTI_IMR1_IM12_Msk                          /*!< Interrupt Mask on line 12 */

+#define EXTI_IMR1_IM13_Pos         (13U)

+#define EXTI_IMR1_IM13_Msk         (0x1UL << EXTI_IMR1_IM13_Pos)               /*!< 0x00002000 */

+#define EXTI_IMR1_IM13             EXTI_IMR1_IM13_Msk                          /*!< Interrupt Mask on line 13 */

+#define EXTI_IMR1_IM14_Pos         (14U)

+#define EXTI_IMR1_IM14_Msk         (0x1UL << EXTI_IMR1_IM14_Pos)               /*!< 0x00004000 */

+#define EXTI_IMR1_IM14             EXTI_IMR1_IM14_Msk                          /*!< Interrupt Mask on line 14 */

+#define EXTI_IMR1_IM15_Pos         (15U)

+#define EXTI_IMR1_IM15_Msk         (0x1UL << EXTI_IMR1_IM15_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR1_IM15             EXTI_IMR1_IM15_Msk                          /*!< Interrupt Mask on line 15 */

+#define EXTI_IMR1_IM16_Pos         (16U)

+#define EXTI_IMR1_IM16_Msk         (0x1UL << EXTI_IMR1_IM16_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR1_IM16             EXTI_IMR1_IM16_Msk                          /*!< Interrupt Mask on line 16 */

+#define EXTI_IMR1_IM17_Pos         (17U)

+#define EXTI_IMR1_IM17_Msk         (0x1UL << EXTI_IMR1_IM17_Pos)               /*!< 0x00020000 */

+#define EXTI_IMR1_IM17             EXTI_IMR1_IM17_Msk                          /*!< Interrupt Mask on line 17 */

+#define EXTI_IMR1_IM18_Pos         (18U)

+#define EXTI_IMR1_IM18_Msk         (0x1UL << EXTI_IMR1_IM18_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR1_IM18             EXTI_IMR1_IM18_Msk                          /*!< Interrupt Mask on line 18 */

+#define EXTI_IMR1_IM19_Pos         (19U)

+#define EXTI_IMR1_IM19_Msk         (0x1UL << EXTI_IMR1_IM19_Pos)               /*!< 0x00080000 */

+#define EXTI_IMR1_IM19             EXTI_IMR1_IM19_Msk                          /*!< Interrupt Mask on line 19 */

+#define EXTI_IMR1_IM20_Pos         (20U)

+#define EXTI_IMR1_IM20_Msk         (0x1UL << EXTI_IMR1_IM20_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR1_IM20             EXTI_IMR1_IM20_Msk                          /*!< Interrupt Mask on line 20 */

+#define EXTI_IMR1_IM21_Pos         (21U)

+#define EXTI_IMR1_IM21_Msk         (0x1UL << EXTI_IMR1_IM21_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR1_IM21             EXTI_IMR1_IM21_Msk                          /*!< Interrupt Mask on line 21 */

+#define EXTI_IMR1_IM22_Pos         (22U)

+#define EXTI_IMR1_IM22_Msk         (0x1UL << EXTI_IMR1_IM22_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR1_IM22             EXTI_IMR1_IM22_Msk                          /*!< Interrupt Mask on line 22 */

+#define EXTI_IMR1_IM23_Pos         (23U)

+#define EXTI_IMR1_IM23_Msk         (0x1UL << EXTI_IMR1_IM23_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR1_IM23             EXTI_IMR1_IM23_Msk                          /*!< Interrupt Mask on line 23 */

+#define EXTI_IMR1_IM24_Pos         (24U)

+#define EXTI_IMR1_IM24_Msk         (0x1UL << EXTI_IMR1_IM24_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR1_IM24             EXTI_IMR1_IM24_Msk                          /*!< Interrupt Mask on line 24 */

+#define EXTI_IMR1_IM25_Pos         (25U)

+#define EXTI_IMR1_IM25_Msk         (0x1UL << EXTI_IMR1_IM25_Pos)               /*!< 0x02000000 */

+#define EXTI_IMR1_IM25             EXTI_IMR1_IM25_Msk                          /*!< Interrupt Mask on line 25 */

+#define EXTI_IMR1_IM26_Pos         (26U)

+#define EXTI_IMR1_IM26_Msk         (0x1UL << EXTI_IMR1_IM26_Pos)               /*!< 0x04000000 */

+#define EXTI_IMR1_IM26             EXTI_IMR1_IM26_Msk                          /*!< Interrupt Mask on line 26 */

+#define EXTI_IMR1_IM27_Pos         (27U)

+#define EXTI_IMR1_IM27_Msk         (0x1UL << EXTI_IMR1_IM27_Pos)               /*!< 0x08000000 */

+#define EXTI_IMR1_IM27             EXTI_IMR1_IM27_Msk                          /*!< Interrupt Mask on line 27 */

+#define EXTI_IMR1_IM28_Pos         (28U)

+#define EXTI_IMR1_IM28_Msk         (0x1UL << EXTI_IMR1_IM28_Pos)               /*!< 0x10000000 */

+#define EXTI_IMR1_IM28             EXTI_IMR1_IM28_Msk                          /*!< Interrupt Mask on line 28 */

+#define EXTI_IMR1_IM29_Pos         (29U)

+#define EXTI_IMR1_IM29_Msk         (0x1UL << EXTI_IMR1_IM29_Pos)               /*!< 0x20000000 */

+#define EXTI_IMR1_IM29             EXTI_IMR1_IM29_Msk                          /*!< Interrupt Mask on line 29 */

+#define EXTI_IMR1_IM30_Pos         (30U)

+#define EXTI_IMR1_IM30_Msk         (0x1UL << EXTI_IMR1_IM30_Pos)               /*!< 0x40000000 */

+#define EXTI_IMR1_IM30             EXTI_IMR1_IM30_Msk                          /*!< Interrupt Mask on line 30 */

+#define EXTI_IMR1_IM31_Pos         (31U)

+#define EXTI_IMR1_IM31_Msk         (0x1UL << EXTI_IMR1_IM31_Pos)               /*!< 0x80000000 */

+#define EXTI_IMR1_IM31             EXTI_IMR1_IM31_Msk                          /*!< Interrupt Mask on line 31 */

+

+/*******************  Bit definition for EXTI_EMR1 register  *******************/

+#define EXTI_EMR1_EM_Pos           (0U)

+#define EXTI_EMR1_EM_Msk           (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)          /*!< 0xFFFFFFFF */

+#define EXTI_EMR1_EM               EXTI_EMR1_EM_Msk                            /*!< Event Mask */

+#define EXTI_EMR1_EM0_Pos          (0U)

+#define EXTI_EMR1_EM0_Msk          (0x1UL << EXTI_EMR1_EM0_Pos)                /*!< 0x00000001 */

+#define EXTI_EMR1_EM0              EXTI_EMR1_EM0_Msk                           /*!< Event Mask on line 0 */

+#define EXTI_EMR1_EM1_Pos          (1U)

+#define EXTI_EMR1_EM1_Msk          (0x1UL << EXTI_EMR1_EM1_Pos)                /*!< 0x00000002 */

+#define EXTI_EMR1_EM1              EXTI_EMR1_EM1_Msk                           /*!< Event Mask on line 1 */

+#define EXTI_EMR1_EM2_Pos          (2U)

+#define EXTI_EMR1_EM2_Msk          (0x1UL << EXTI_EMR1_EM2_Pos)                /*!< 0x00000004 */

+#define EXTI_EMR1_EM2              EXTI_EMR1_EM2_Msk                           /*!< Event Mask on line 2 */

+#define EXTI_EMR1_EM3_Pos          (3U)

+#define EXTI_EMR1_EM3_Msk          (0x1UL << EXTI_EMR1_EM3_Pos)                /*!< 0x00000008 */

+#define EXTI_EMR1_EM3              EXTI_EMR1_EM3_Msk                           /*!< Event Mask on line 3 */

+#define EXTI_EMR1_EM4_Pos          (4U)

+#define EXTI_EMR1_EM4_Msk          (0x1UL << EXTI_EMR1_EM4_Pos)                /*!< 0x00000010 */

+#define EXTI_EMR1_EM4              EXTI_EMR1_EM4_Msk                           /*!< Event Mask on line 4 */

+#define EXTI_EMR1_EM5_Pos          (5U)

+#define EXTI_EMR1_EM5_Msk          (0x1UL << EXTI_EMR1_EM5_Pos)                /*!< 0x00000020 */

+#define EXTI_EMR1_EM5              EXTI_EMR1_EM5_Msk                           /*!< Event Mask on line 5 */

+#define EXTI_EMR1_EM6_Pos          (6U)

+#define EXTI_EMR1_EM6_Msk          (0x1UL << EXTI_EMR1_EM6_Pos)                /*!< 0x00000040 */

+#define EXTI_EMR1_EM6              EXTI_EMR1_EM6_Msk                           /*!< Event Mask on line 6 */

+#define EXTI_EMR1_EM7_Pos          (7U)

+#define EXTI_EMR1_EM7_Msk          (0x1UL << EXTI_EMR1_EM7_Pos)                /*!< 0x00000080 */

+#define EXTI_EMR1_EM7              EXTI_EMR1_EM7_Msk                           /*!< Event Mask on line 7 */

+#define EXTI_EMR1_EM8_Pos          (8U)

+#define EXTI_EMR1_EM8_Msk          (0x1UL << EXTI_EMR1_EM8_Pos)                /*!< 0x00000100 */

+#define EXTI_EMR1_EM8              EXTI_EMR1_EM8_Msk                           /*!< Event Mask on line 8 */

+#define EXTI_EMR1_EM9_Pos          (9U)

+#define EXTI_EMR1_EM9_Msk          (0x1UL << EXTI_EMR1_EM9_Pos)                /*!< 0x00000200 */

+#define EXTI_EMR1_EM9              EXTI_EMR1_EM9_Msk                           /*!< Event Mask on line 9 */

+#define EXTI_EMR1_EM10_Pos         (10U)

+#define EXTI_EMR1_EM10_Msk         (0x1UL << EXTI_EMR1_EM10_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR1_EM10             EXTI_EMR1_EM10_Msk                          /*!< Event Mask on line 10 */

+#define EXTI_EMR1_EM11_Pos         (11U)

+#define EXTI_EMR1_EM11_Msk         (0x1UL << EXTI_EMR1_EM11_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR1_EM11             EXTI_EMR1_EM11_Msk                          /*!< Event Mask on line 11 */

+#define EXTI_EMR1_EM12_Pos         (12U)

+#define EXTI_EMR1_EM12_Msk         (0x1UL << EXTI_EMR1_EM12_Pos)               /*!< 0x00001000 */

+#define EXTI_EMR1_EM12             EXTI_EMR1_EM12_Msk                          /*!< Event Mask on line 12 */

+#define EXTI_EMR1_EM13_Pos         (13U)

+#define EXTI_EMR1_EM13_Msk         (0x1UL << EXTI_EMR1_EM13_Pos)               /*!< 0x00002000 */

+#define EXTI_EMR1_EM13             EXTI_EMR1_EM13_Msk                          /*!< Event Mask on line 13 */

+#define EXTI_EMR1_EM14_Pos         (14U)

+#define EXTI_EMR1_EM14_Msk         (0x1UL << EXTI_EMR1_EM14_Pos)               /*!< 0x00004000 */

+#define EXTI_EMR1_EM14             EXTI_EMR1_EM14_Msk                          /*!< Event Mask on line 14 */

+#define EXTI_EMR1_EM15_Pos         (15U)

+#define EXTI_EMR1_EM15_Msk         (0x1UL << EXTI_EMR1_EM15_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR1_EM15             EXTI_EMR1_EM15_Msk                          /*!< Event Mask on line 15 */

+#define EXTI_EMR1_EM16_Pos         (16U)

+#define EXTI_EMR1_EM16_Msk         (0x1UL << EXTI_EMR1_EM16_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR1_EM16             EXTI_EMR1_EM16_Msk                          /*!< Event Mask on line 16 */

+#define EXTI_EMR1_EM17_Pos         (17U)

+#define EXTI_EMR1_EM17_Msk         (0x1UL << EXTI_EMR1_EM17_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR1_EM17             EXTI_EMR1_EM17_Msk                          /*!< Event Mask on line 17 */

+#define EXTI_EMR1_EM18_Pos         (18U)

+#define EXTI_EMR1_EM18_Msk         (0x1UL << EXTI_EMR1_EM18_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR1_EM18             EXTI_EMR1_EM18_Msk                          /*!< Event Mask on line 18 */

+#define EXTI_EMR1_EM20_Pos         (20U)

+#define EXTI_EMR1_EM20_Msk         (0x1UL << EXTI_EMR1_EM20_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR1_EM20             EXTI_EMR1_EM20_Msk                          /*!< Event Mask on line 20 */

+#define EXTI_EMR1_EM21_Pos         (21U)

+#define EXTI_EMR1_EM21_Msk         (0x1UL << EXTI_EMR1_EM21_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR1_EM21             EXTI_EMR1_EM21_Msk                          /*!< Event Mask on line 21 */

+#define EXTI_EMR1_EM22_Pos         (22U)

+#define EXTI_EMR1_EM22_Msk         (0x1UL << EXTI_EMR1_EM22_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR1_EM22             EXTI_EMR1_EM22_Msk                          /*!< Event Mask on line 22 */

+#define EXTI_EMR1_EM23_Pos         (23U)

+#define EXTI_EMR1_EM23_Msk         (0x1UL << EXTI_EMR1_EM23_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR1_EM23             EXTI_EMR1_EM23_Msk                          /*!< Event Mask on line 23 */

+#define EXTI_EMR1_EM24_Pos         (24U)

+#define EXTI_EMR1_EM24_Msk         (0x1UL << EXTI_EMR1_EM24_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR1_EM24             EXTI_EMR1_EM24_Msk                          /*!< Event Mask on line 24 */

+#define EXTI_EMR1_EM25_Pos         (25U)

+#define EXTI_EMR1_EM25_Msk         (0x1UL << EXTI_EMR1_EM25_Pos)               /*!< 0x02000000 */

+#define EXTI_EMR1_EM25             EXTI_EMR1_EM25_Msk                          /*!< Event Mask on line 25 */

+#define EXTI_EMR1_EM26_Pos         (26U)

+#define EXTI_EMR1_EM26_Msk         (0x1UL << EXTI_EMR1_EM26_Pos)               /*!< 0x04000000 */

+#define EXTI_EMR1_EM26             EXTI_EMR1_EM26_Msk                          /*!< Event Mask on line 26 */

+#define EXTI_EMR1_EM27_Pos         (27U)

+#define EXTI_EMR1_EM27_Msk         (0x1UL << EXTI_EMR1_EM27_Pos)               /*!< 0x08000000 */

+#define EXTI_EMR1_EM27             EXTI_EMR1_EM27_Msk                          /*!< Event Mask on line 27 */

+#define EXTI_EMR1_EM28_Pos         (28U)

+#define EXTI_EMR1_EM28_Msk         (0x1UL << EXTI_EMR1_EM28_Pos)               /*!< 0x10000000 */

+#define EXTI_EMR1_EM28             EXTI_EMR1_EM28_Msk                          /*!< Event Mask on line 28 */

+#define EXTI_EMR1_EM29_Pos         (29U)

+#define EXTI_EMR1_EM29_Msk         (0x1UL << EXTI_EMR1_EM29_Pos)               /*!< 0x20000000 */

+#define EXTI_EMR1_EM29             EXTI_EMR1_EM29_Msk                          /*!< Event Mask on line 29 */

+#define EXTI_EMR1_EM30_Pos         (30U)

+#define EXTI_EMR1_EM30_Msk         (0x1UL << EXTI_EMR1_EM30_Pos)               /*!< 0x40000000 */

+#define EXTI_EMR1_EM30             EXTI_EMR1_EM30_Msk                          /*!< Event Mask on line 30 */

+#define EXTI_EMR1_EM31_Pos         (31U)

+#define EXTI_EMR1_EM31_Msk         (0x1UL << EXTI_EMR1_EM31_Pos)               /*!< 0x80000000 */

+#define EXTI_EMR1_EM31             EXTI_EMR1_EM31_Msk                          /*!< Event Mask on line 31 */

+

+/*******************  Bit definition for EXTI_PR1 register  ********************/

+#define EXTI_PR1_PR_Pos            (0U)

+#define EXTI_PR1_PR_Msk            (0x3FFFFFUL << EXTI_PR1_PR_Pos)             /*!< 0x003FFFFF */

+#define EXTI_PR1_PR                EXTI_PR1_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR1_PR0_Pos           (0U)

+#define EXTI_PR1_PR0_Msk           (0x1UL << EXTI_PR1_PR0_Pos)                 /*!< 0x00000001 */

+#define EXTI_PR1_PR0               EXTI_PR1_PR0_Msk                            /*!< Pending bit for line 0 */

+#define EXTI_PR1_PR1_Pos           (1U)

+#define EXTI_PR1_PR1_Msk           (0x1UL << EXTI_PR1_PR1_Pos)                 /*!< 0x00000002 */

+#define EXTI_PR1_PR1               EXTI_PR1_PR1_Msk                            /*!< Pending bit for line 1 */

+#define EXTI_PR1_PR2_Pos           (2U)

+#define EXTI_PR1_PR2_Msk           (0x1UL << EXTI_PR1_PR2_Pos)                 /*!< 0x00000004 */

+#define EXTI_PR1_PR2               EXTI_PR1_PR2_Msk                            /*!< Pending bit for line 2 */

+#define EXTI_PR1_PR3_Pos           (3U)

+#define EXTI_PR1_PR3_Msk           (0x1UL << EXTI_PR1_PR3_Pos)                 /*!< 0x00000008 */

+#define EXTI_PR1_PR3               EXTI_PR1_PR3_Msk                            /*!< Pending bit for line 3 */

+#define EXTI_PR1_PR4_Pos           (4U)

+#define EXTI_PR1_PR4_Msk           (0x1UL << EXTI_PR1_PR4_Pos)                 /*!< 0x00000010 */

+#define EXTI_PR1_PR4               EXTI_PR1_PR4_Msk                            /*!< Pending bit for line 4 */

+#define EXTI_PR1_PR5_Pos           (5U)

+#define EXTI_PR1_PR5_Msk           (0x1UL << EXTI_PR1_PR5_Pos)                 /*!< 0x00000020 */

+#define EXTI_PR1_PR5               EXTI_PR1_PR5_Msk                            /*!< Pending bit for line 5 */

+#define EXTI_PR1_PR6_Pos           (6U)

+#define EXTI_PR1_PR6_Msk           (0x1UL << EXTI_PR1_PR6_Pos)                 /*!< 0x00000040 */

+#define EXTI_PR1_PR6               EXTI_PR1_PR6_Msk                            /*!< Pending bit for line 6 */

+#define EXTI_PR1_PR7_Pos           (7U)

+#define EXTI_PR1_PR7_Msk           (0x1UL << EXTI_PR1_PR7_Pos)                 /*!< 0x00000080 */

+#define EXTI_PR1_PR7               EXTI_PR1_PR7_Msk                            /*!< Pending bit for line 7 */

+#define EXTI_PR1_PR8_Pos           (8U)

+#define EXTI_PR1_PR8_Msk           (0x1UL << EXTI_PR1_PR8_Pos)                 /*!< 0x00000100 */

+#define EXTI_PR1_PR8               EXTI_PR1_PR8_Msk                            /*!< Pending bit for line 8 */

+#define EXTI_PR1_PR9_Pos           (9U)

+#define EXTI_PR1_PR9_Msk           (0x1UL << EXTI_PR1_PR9_Pos)                 /*!< 0x00000200 */

+#define EXTI_PR1_PR9               EXTI_PR1_PR9_Msk                            /*!< Pending bit for line 9 */

+#define EXTI_PR1_PR10_Pos          (10U)

+#define EXTI_PR1_PR10_Msk          (0x1UL << EXTI_PR1_PR10_Pos)                /*!< 0x00000400 */

+#define EXTI_PR1_PR10              EXTI_PR1_PR10_Msk                           /*!< Pending bit for line 10 */

+#define EXTI_PR1_PR11_Pos          (11U)

+#define EXTI_PR1_PR11_Msk          (0x1UL << EXTI_PR1_PR11_Pos)                /*!< 0x00000800 */

+#define EXTI_PR1_PR11              EXTI_PR1_PR11_Msk                           /*!< Pending bit for line 11 */

+#define EXTI_PR1_PR12_Pos          (12U)

+#define EXTI_PR1_PR12_Msk          (0x1UL << EXTI_PR1_PR12_Pos)                /*!< 0x00001000 */

+#define EXTI_PR1_PR12              EXTI_PR1_PR12_Msk                           /*!< Pending bit for line 12 */

+#define EXTI_PR1_PR13_Pos          (13U)

+#define EXTI_PR1_PR13_Msk          (0x1UL << EXTI_PR1_PR13_Pos)                /*!< 0x00002000 */

+#define EXTI_PR1_PR13              EXTI_PR1_PR13_Msk                           /*!< Pending bit for line 13 */

+#define EXTI_PR1_PR14_Pos          (14U)

+#define EXTI_PR1_PR14_Msk          (0x1UL << EXTI_PR1_PR14_Pos)                /*!< 0x00004000 */

+#define EXTI_PR1_PR14              EXTI_PR1_PR14_Msk                           /*!< Pending bit for line 14 */

+#define EXTI_PR1_PR15_Pos          (15U)

+#define EXTI_PR1_PR15_Msk          (0x1UL << EXTI_PR1_PR15_Pos)                /*!< 0x00008000 */

+#define EXTI_PR1_PR15              EXTI_PR1_PR15_Msk                           /*!< Pending bit for line 15 */

+#define EXTI_PR1_PR16_Pos          (16U)

+#define EXTI_PR1_PR16_Msk          (0x1UL << EXTI_PR1_PR16_Pos)                /*!< 0x00010000 */

+#define EXTI_PR1_PR16              EXTI_PR1_PR16_Msk                           /*!< Pending bit for line 16 */

+#define EXTI_PR1_PR17_Pos          (17U)

+#define EXTI_PR1_PR17_Msk          (0x1UL << EXTI_PR1_PR17_Pos)                /*!< 0x00020000 */

+#define EXTI_PR1_PR17              EXTI_PR1_PR17_Msk                           /*!< Pending bit for line 17 */

+#define EXTI_PR1_PR18_Pos          (18U)

+#define EXTI_PR1_PR18_Msk          (0x1UL << EXTI_PR1_PR18_Pos)                /*!< 0x00040000 */

+#define EXTI_PR1_PR18              EXTI_PR1_PR18_Msk                           /*!< Pending bit for line 18 */

+#define EXTI_PR1_PR19_Pos          (19U)

+#define EXTI_PR1_PR19_Msk          (0x1UL << EXTI_PR1_PR19_Pos)                /*!< 0x00080000 */

+#define EXTI_PR1_PR19              EXTI_PR1_PR19_Msk                           /*!< Pending bit for line 19 */

+#define EXTI_PR1_PR20_Pos          (20U)

+#define EXTI_PR1_PR20_Msk          (0x1UL << EXTI_PR1_PR20_Pos)                /*!< 0x00100000 */

+#define EXTI_PR1_PR20              EXTI_PR1_PR20_Msk                           /*!< Pending bit for line 20 */

+#define EXTI_PR1_PR21_Pos          (21U)

+#define EXTI_PR1_PR21_Msk          (0x1UL << EXTI_PR1_PR21_Pos)                /*!< 0x00200000 */

+#define EXTI_PR1_PR21              EXTI_PR1_PR21_Msk                           /*!< Pending bit for line 21 */

+

+/*******************  Bit definition for EXTI_IMR2 register  *******************/

+#define EXTI_IMR2_IM_Pos           (0U)

+#define EXTI_IMR2_IM_Msk           (0xFFFF8FFFUL << EXTI_IMR2_IM_Pos)          /*!< 0xFFFF8FFF */

+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            /*!< Interrupt Mask            */

+#define EXTI_IMR2_IM32_Pos         (0U)

+#define EXTI_IMR2_IM32_Msk         (0x1UL << EXTI_IMR2_IM32_Pos)               /*!< 0x00000001 */

+#define EXTI_IMR2_IM32             EXTI_IMR2_IM32_Msk                          /*!< Interrupt Mask on line 32 */

+#define EXTI_IMR2_IM33_Pos         (1U)

+#define EXTI_IMR2_IM33_Msk         (0x1UL << EXTI_IMR2_IM33_Pos)               /*!< 0x00000002 */

+#define EXTI_IMR2_IM33             EXTI_IMR2_IM33_Msk                          /*!< Interrupt Mask on line 33 */

+#define EXTI_IMR2_IM34_Pos         (2U)

+#define EXTI_IMR2_IM34_Msk         (0x1UL << EXTI_IMR2_IM34_Pos)               /*!< 0x00000004 */

+#define EXTI_IMR2_IM34             EXTI_IMR2_IM34_Msk                          /*!< Interrupt Mask on line 34 */

+#define EXTI_IMR2_IM35_Pos         (3U)

+#define EXTI_IMR2_IM35_Msk         (0x1UL << EXTI_IMR2_IM35_Pos)               /*!< 0x00000008 */

+#define EXTI_IMR2_IM35             EXTI_IMR2_IM35_Msk                          /*!< Interrupt Mask on line 35 */

+#define EXTI_IMR2_IM36_Pos         (4U)

+#define EXTI_IMR2_IM36_Msk         (0x1UL << EXTI_IMR2_IM36_Pos)               /*!< 0x00000010 */

+#define EXTI_IMR2_IM36             EXTI_IMR2_IM36_Msk                          /*!< Interrupt Mask on line 36 */

+#define EXTI_IMR2_IM37_Pos         (5U)

+#define EXTI_IMR2_IM37_Msk         (0x1UL << EXTI_IMR2_IM37_Pos)               /*!< 0x00000020 */

+#define EXTI_IMR2_IM37             EXTI_IMR2_IM37_Msk                          /*!< Interrupt Mask on line 37 */

+#define EXTI_IMR2_IM38_Pos         (6U)

+#define EXTI_IMR2_IM38_Msk         (0x1UL << EXTI_IMR2_IM38_Pos)               /*!< 0x00000040 */

+#define EXTI_IMR2_IM38             EXTI_IMR2_IM38_Msk                          /*!< Interrupt Mask on line 38 */

+#define EXTI_IMR2_IM39_Pos         (7U)

+#define EXTI_IMR2_IM39_Msk         (0x1UL << EXTI_IMR2_IM39_Pos)               /*!< 0x00000080 */

+#define EXTI_IMR2_IM39             EXTI_IMR2_IM39_Msk                          /*!< Interrupt Mask on line 39 */

+#define EXTI_IMR2_IM40_Pos         (8U)

+#define EXTI_IMR2_IM40_Msk         (0x1UL << EXTI_IMR2_IM40_Pos)               /*!< 0x00000100 */

+#define EXTI_IMR2_IM40             EXTI_IMR2_IM40_Msk                          /*!< Interrupt Mask on line 40 */

+#define EXTI_IMR2_IM41_Pos         (9U)

+#define EXTI_IMR2_IM41_Msk         (0x1UL << EXTI_IMR2_IM41_Pos)               /*!< 0x00000200 */

+#define EXTI_IMR2_IM41             EXTI_IMR2_IM41_Msk                          /*!< Interrupt Mask on line 41 */

+#define EXTI_IMR2_IM42_Pos         (10U)

+#define EXTI_IMR2_IM42_Msk         (0x1UL << EXTI_IMR2_IM42_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR2_IM42             EXTI_IMR2_IM42_Msk                          /*!< Interrupt Mask on line 42 */

+#define EXTI_IMR2_IM43_Pos         (11U)

+#define EXTI_IMR2_IM43_Msk         (0x1UL << EXTI_IMR2_IM43_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR2_IM43             EXTI_IMR2_IM43_Msk                          /*!< Interrupt Mask on line 43 */

+#define EXTI_IMR2_IM47_Pos         (15U)

+#define EXTI_IMR2_IM47_Msk         (0x1UL << EXTI_IMR2_IM47_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR2_IM47             EXTI_IMR2_IM47_Msk                          /*!< Interrupt Mask on line 47 */

+#define EXTI_IMR2_IM48_Pos         (16U)

+#define EXTI_IMR2_IM48_Msk         (0x1UL << EXTI_IMR2_IM48_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR2_IM48             EXTI_IMR2_IM48_Msk                          /*!< Interrupt Mask on line 48 */

+#define EXTI_IMR2_IM49_Pos         (17U)

+#define EXTI_IMR2_IM49_Msk         (0x1UL << EXTI_IMR2_IM49_Pos)               /*!< 0x00020000 */

+#define EXTI_IMR2_IM49             EXTI_IMR2_IM49_Msk                          /*!< Interrupt Mask on line 49 */

+#define EXTI_IMR2_IM50_Pos         (18U)

+#define EXTI_IMR2_IM50_Msk         (0x1UL << EXTI_IMR2_IM50_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR2_IM50             EXTI_IMR2_IM50_Msk                          /*!< Interrupt Mask on line 50 */

+#define EXTI_IMR2_IM51_Pos         (19U)

+#define EXTI_IMR2_IM51_Msk         (0x1UL << EXTI_IMR2_IM51_Pos)               /*!< 0x00080000 */

+#define EXTI_IMR2_IM51             EXTI_IMR2_IM51_Msk                          /*!< Interrupt Mask on line 51 */

+#define EXTI_IMR2_IM52_Pos         (20U)

+#define EXTI_IMR2_IM52_Msk         (0x1UL << EXTI_IMR2_IM52_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR2_IM52             EXTI_IMR2_IM52_Msk                          /*!< Interrupt Mask on line 52 */

+#define EXTI_IMR2_IM53_Pos         (21U)

+#define EXTI_IMR2_IM53_Msk         (0x1UL << EXTI_IMR2_IM53_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR2_IM53             EXTI_IMR2_IM53_Msk                          /*!< Interrupt Mask on line 53 */

+#define EXTI_IMR2_IM54_Pos         (22U)

+#define EXTI_IMR2_IM54_Msk         (0x1UL << EXTI_IMR2_IM54_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR2_IM54             EXTI_IMR2_IM54_Msk                          /*!< Interrupt Mask on line 54 */

+#define EXTI_IMR2_IM55_Pos         (23U)

+#define EXTI_IMR2_IM55_Msk         (0x1UL << EXTI_IMR2_IM55_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR2_IM55             EXTI_IMR2_IM55_Msk                          /*!< Interrupt Mask on line 55 */

+#define EXTI_IMR2_IM56_Pos         (24U)

+#define EXTI_IMR2_IM56_Msk         (0x1UL << EXTI_IMR2_IM56_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR2_IM56             EXTI_IMR2_IM56_Msk                          /*!< Interrupt Mask on line 56 */

+#define EXTI_IMR2_IM57_Pos         (25U)

+#define EXTI_IMR2_IM57_Msk         (0x1UL << EXTI_IMR2_IM57_Pos)               /*!< 0x02000000 */

+#define EXTI_IMR2_IM57             EXTI_IMR2_IM57_Msk                          /*!< Interrupt Mask on line 57 */

+#define EXTI_IMR2_IM58_Pos         (26U)

+#define EXTI_IMR2_IM58_Msk         (0x1UL << EXTI_IMR2_IM58_Pos)               /*!< 0x04000000 */

+#define EXTI_IMR2_IM58             EXTI_IMR2_IM58_Msk                          /*!< Interrupt Mask on line 58 */

+#define EXTI_IMR2_IM59_Pos         (27U)

+#define EXTI_IMR2_IM59_Msk         (0x1UL << EXTI_IMR2_IM59_Pos)               /*!< 0x08000000 */

+#define EXTI_IMR2_IM59             EXTI_IMR2_IM59_Msk                          /*!< Interrupt Mask on line 59 */

+#define EXTI_IMR2_IM60_Pos         (28U)

+#define EXTI_IMR2_IM60_Msk         (0x1UL << EXTI_IMR2_IM60_Pos)               /*!< 0x10000000 */

+#define EXTI_IMR2_IM60             EXTI_IMR2_IM60_Msk                          /*!< Interrupt Mask on line 60 */

+#define EXTI_IMR2_IM61_Pos         (29U)

+#define EXTI_IMR2_IM61_Msk         (0x1UL << EXTI_IMR2_IM61_Pos)               /*!< 0x20000000 */

+#define EXTI_IMR2_IM61             EXTI_IMR2_IM61_Msk                          /*!< Interrupt Mask on line 61 */

+#define EXTI_IMR2_IM62_Pos         (30U)

+#define EXTI_IMR2_IM62_Msk         (0x1UL << EXTI_IMR2_IM62_Pos)               /*!< 0x40000000 */

+#define EXTI_IMR2_IM62             EXTI_IMR2_IM62_Msk                          /*!< Interrupt Mask on line 62 */

+#define EXTI_IMR2_IM63_Pos         (31U)

+#define EXTI_IMR2_IM63_Msk         (0x1UL << EXTI_IMR2_IM63_Pos)               /*!< 0x80000000 */

+#define EXTI_IMR2_IM63             EXTI_IMR2_IM63_Msk                          /*!< Interrupt Mask on line 63 */

+

+/*******************  Bit definition for EXTI_EMR2 register  *******************/

+#define EXTI_EMR2_EM_Pos           (0U)

+#define EXTI_EMR2_EM_Msk           (0xFFFF8FFFUL << EXTI_EMR2_EM_Pos)          /*!< 0xFFFF8FFF */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            /*!< Event Mask           */

+#define EXTI_EMR2_EM32_Pos         (0U)

+#define EXTI_EMR2_EM32_Msk         (0x1UL << EXTI_EMR2_EM32_Pos)               /*!< 0x00000001 */

+#define EXTI_EMR2_EM32             EXTI_EMR2_EM32_Msk                          /*!< Event Mask on line 32*/

+#define EXTI_EMR2_EM33_Pos         (1U)

+#define EXTI_EMR2_EM33_Msk         (0x1UL << EXTI_EMR2_EM33_Pos)               /*!< 0x00000002 */

+#define EXTI_EMR2_EM33             EXTI_EMR2_EM33_Msk                          /*!< Event Mask on line 33*/

+#define EXTI_EMR2_EM34_Pos         (2U)

+#define EXTI_EMR2_EM34_Msk         (0x1UL << EXTI_EMR2_EM34_Pos)               /*!< 0x00000004 */

+#define EXTI_EMR2_EM34             EXTI_EMR2_EM34_Msk                          /*!< Event Mask on line 34*/

+#define EXTI_EMR2_EM35_Pos         (3U)

+#define EXTI_EMR2_EM35_Msk         (0x1UL << EXTI_EMR2_EM35_Pos)               /*!< 0x00000008 */

+#define EXTI_EMR2_EM35             EXTI_EMR2_EM35_Msk                          /*!< Event Mask on line 35*/

+#define EXTI_EMR2_EM36_Pos         (4U)

+#define EXTI_EMR2_EM36_Msk         (0x1UL << EXTI_EMR2_EM36_Pos)               /*!< 0x00000010 */

+#define EXTI_EMR2_EM36             EXTI_EMR2_EM36_Msk                          /*!< Event Mask on line 36*/

+#define EXTI_EMR2_EM37_Pos         (5U)

+#define EXTI_EMR2_EM37_Msk         (0x1UL << EXTI_EMR2_EM37_Pos)               /*!< 0x00000020 */

+#define EXTI_EMR2_EM37             EXTI_EMR2_EM37_Msk                          /*!< Event Mask on line 37*/

+#define EXTI_EMR2_EM38_Pos         (6U)

+#define EXTI_EMR2_EM38_Msk         (0x1UL << EXTI_EMR2_EM38_Pos)               /*!< 0x00000040 */

+#define EXTI_EMR2_EM38             EXTI_EMR2_EM38_Msk                          /*!< Event Mask on line 38*/

+#define EXTI_EMR2_EM39_Pos         (7U)

+#define EXTI_EMR2_EM39_Msk         (0x1UL << EXTI_EMR2_EM39_Pos)               /*!< 0x00000080 */

+#define EXTI_EMR2_EM39             EXTI_EMR2_EM39_Msk                          /*!< Event Mask on line 39*/

+#define EXTI_EMR2_EM40_Pos         (8U)

+#define EXTI_EMR2_EM40_Msk         (0x1UL << EXTI_EMR2_EM40_Pos)               /*!< 0x00000100 */

+#define EXTI_EMR2_EM40             EXTI_EMR2_EM40_Msk                          /*!< Event Mask on line 40*/

+#define EXTI_EMR2_EM41_Pos         (9U)

+#define EXTI_EMR2_EM41_Msk         (0x1UL << EXTI_EMR2_EM41_Pos)               /*!< 0x00000200 */

+#define EXTI_EMR2_EM41             EXTI_EMR2_EM41_Msk                          /*!< Event Mask on line 41*/

+#define EXTI_EMR2_EM42_Pos         (10U)

+#define EXTI_EMR2_EM42_Msk         (0x1UL << EXTI_EMR2_EM42_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR2_EM42             EXTI_EMR2_EM42_Msk                          /*!< Event Mask on line 42 */

+#define EXTI_EMR2_EM43_Pos         (11U)

+#define EXTI_EMR2_EM43_Msk         (0x1UL << EXTI_EMR2_EM43_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR2_EM43             EXTI_EMR2_EM43_Msk                          /*!< Event Mask on line 43 */

+#define EXTI_EMR2_EM47_Pos         (15U)

+#define EXTI_EMR2_EM47_Msk         (0x1UL << EXTI_EMR2_EM47_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR2_EM47             EXTI_EMR2_EM47_Msk                          /*!< Event Mask on line 47 */

+#define EXTI_EMR2_EM48_Pos         (16U)

+#define EXTI_EMR2_EM48_Msk         (0x1UL << EXTI_EMR2_EM48_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR2_EM48             EXTI_EMR2_EM48_Msk                          /*!< Event Mask on line 48 */

+#define EXTI_EMR2_EM49_Pos         (17U)

+#define EXTI_EMR2_EM49_Msk         (0x1UL << EXTI_EMR2_EM49_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR2_EM49             EXTI_EMR2_EM49_Msk                          /*!< Event Mask on line 49 */

+#define EXTI_EMR2_EM50_Pos         (18U)

+#define EXTI_EMR2_EM50_Msk         (0x1UL << EXTI_EMR2_EM50_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR2_EM50             EXTI_EMR2_EM50_Msk                          /*!< Event Mask on line 50 */

+#define EXTI_EMR2_EM51_Pos         (19U)

+#define EXTI_EMR2_EM51_Msk         (0x1UL << EXTI_EMR2_EM51_Pos)               /*!< 0x00080000 */

+#define EXTI_EMR2_EM51             EXTI_EMR2_EM51_Msk                          /*!< Event Mask on line 51 */

+#define EXTI_EMR2_EM52_Pos         (20U)

+#define EXTI_EMR2_EM52_Msk         (0x1UL << EXTI_EMR2_EM52_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR2_EM52             EXTI_EMR2_EM52_Msk                          /*!< Event Mask on line 52 */

+#define EXTI_EMR2_EM53_Pos         (21U)

+#define EXTI_EMR2_EM53_Msk         (0x1UL << EXTI_EMR2_EM53_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR2_EM53             EXTI_EMR2_EM53_Msk                          /*!< Event Mask on line 53 */

+#define EXTI_EMR2_EM54_Pos         (22U)

+#define EXTI_EMR2_EM54_Msk         (0x1UL << EXTI_EMR2_EM54_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR2_EM54             EXTI_EMR2_EM54_Msk                          /*!< Event Mask on line 54 */

+#define EXTI_EMR2_EM55_Pos         (23U)

+#define EXTI_EMR2_EM55_Msk         (0x1UL << EXTI_EMR2_EM55_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR2_EM55             EXTI_EMR2_EM55_Msk                          /*!< Event Mask on line 55 */

+#define EXTI_EMR2_EM56_Pos         (24U)

+#define EXTI_EMR2_EM56_Msk         (0x1UL << EXTI_EMR2_EM56_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR2_EM56             EXTI_EMR2_EM56_Msk                          /*!< Event Mask on line 56 */

+#define EXTI_EMR2_EM57_Pos         (25U)

+#define EXTI_EMR2_EM57_Msk         (0x1UL << EXTI_EMR2_EM57_Pos)               /*!< 0x02000000 */

+#define EXTI_EMR2_EM57             EXTI_EMR2_EM57_Msk                          /*!< Event Mask on line 57 */

+#define EXTI_EMR2_EM58_Pos         (26U)

+#define EXTI_EMR2_EM58_Msk         (0x1UL << EXTI_EMR2_EM58_Pos)               /*!< 0x04000000 */

+#define EXTI_EMR2_EM58             EXTI_EMR2_EM58_Msk                          /*!< Event Mask on line 58 */

+#define EXTI_EMR2_EM59_Pos         (27U)

+#define EXTI_EMR2_EM59_Msk         (0x1UL << EXTI_EMR2_EM59_Pos)               /*!< 0x08000000 */

+#define EXTI_EMR2_EM59             EXTI_EMR2_EM59_Msk                          /*!< Event Mask on line 59 */

+#define EXTI_EMR2_EM60_Pos         (28U)

+#define EXTI_EMR2_EM60_Msk         (0x1UL << EXTI_EMR2_EM60_Pos)               /*!< 0x10000000 */

+#define EXTI_EMR2_EM60             EXTI_EMR2_EM60_Msk                          /*!< Event Mask on line 60 */

+#define EXTI_EMR2_EM61_Pos         (29U)

+#define EXTI_EMR2_EM61_Msk         (0x1UL << EXTI_EMR2_EM61_Pos)               /*!< 0x20000000 */

+#define EXTI_EMR2_EM61             EXTI_EMR2_EM61_Msk                          /*!< Event Mask on line 61 */

+#define EXTI_EMR2_EM62_Pos         (30U)

+#define EXTI_EMR2_EM62_Msk         (0x1UL << EXTI_EMR2_EM62_Pos)               /*!< 0x40000000 */

+#define EXTI_EMR2_EM62             EXTI_EMR2_EM62_Msk                          /*!< Event Mask on line 62 */

+#define EXTI_EMR2_EM63_Pos         (31U)

+#define EXTI_EMR2_EM63_Msk         (0x1UL << EXTI_EMR2_EM63_Pos)               /*!< 0x80000000 */

+#define EXTI_EMR2_EM63             EXTI_EMR2_EM63_Msk                          /*!< Event Mask on line 63 */

+

+/*******************  Bit definition for EXTI_PR2 register  ********************/

+#define EXTI_PR2_PR_Pos            (17U)

+#define EXTI_PR2_PR_Msk            (0x5UL << EXTI_PR2_PR_Pos)                  /*!< 0x000A0000 */

+#define EXTI_PR2_PR                EXTI_PR2_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR2_PR49_Pos          (17U)

+#define EXTI_PR2_PR49_Msk          (0x1UL << EXTI_PR2_PR49_Pos)                /*!< 0x00020000 */

+#define EXTI_PR2_PR49              EXTI_PR2_PR49_Msk                           /*!< Pending bit for line 49 */

+#define EXTI_PR2_PR51_Pos          (19U)

+#define EXTI_PR2_PR51_Msk          (0x1UL << EXTI_PR2_PR51_Pos)                /*!< 0x00080000 */

+#define EXTI_PR2_PR51              EXTI_PR2_PR51_Msk                           /*!< Pending bit for line 51 */

+

+/*******************  Bit definition for EXTI_IMR3 register  *******************/

+#define EXTI_IMR3_IM_Pos           (0U)

+#define EXTI_IMR3_IM_Msk           (0x001A527FFUL << EXTI_IMR3_IM_Pos)         /*!< 0x001A527FF */

+#define EXTI_IMR3_IM               EXTI_IMR3_IM_Msk                            /*!< Interrupt Mask            */

+#define EXTI_IMR3_IM64_Pos         (0U)

+#define EXTI_IMR3_IM64_Msk         (0x1UL << EXTI_IMR3_IM64_Pos)               /*!< 0x00000001 */

+#define EXTI_IMR3_IM64             EXTI_IMR3_IM64_Msk                          /*!< Interrupt Mask on line 64 */

+#define EXTI_IMR3_IM65_Pos         (1U)

+#define EXTI_IMR3_IM65_Msk         (0x1UL << EXTI_IMR3_IM65_Pos)               /*!< 0x00000002 */

+#define EXTI_IMR3_IM65             EXTI_IMR3_IM65_Msk                          /*!< Interrupt Mask on line 65 */

+#define EXTI_IMR3_IM66_Pos         (2U)

+#define EXTI_IMR3_IM66_Msk         (0x1UL << EXTI_IMR3_IM66_Pos)               /*!< 0x00000004 */

+#define EXTI_IMR3_IM66             EXTI_IMR3_IM66_Msk                          /*!< Interrupt Mask on line 66 */

+#define EXTI_IMR3_IM67_Pos         (3U)

+#define EXTI_IMR3_IM67_Msk         (0x1UL << EXTI_IMR3_IM67_Pos)               /*!< 0x00000008 */

+#define EXTI_IMR3_IM67             EXTI_IMR3_IM67_Msk                          /*!< Interrupt Mask on line 67 */

+#define EXTI_IMR3_IM68_Pos         (4U)

+#define EXTI_IMR3_IM68_Msk         (0x1UL << EXTI_IMR3_IM68_Pos)               /*!< 0x00000010 */

+#define EXTI_IMR3_IM68             EXTI_IMR3_IM68_Msk                          /*!< Interrupt Mask on line 68 */

+#define EXTI_IMR3_IM69_Pos         (5U)

+#define EXTI_IMR3_IM69_Msk         (0x1UL << EXTI_IMR3_IM69_Pos)               /*!< 0x00000020 */

+#define EXTI_IMR3_IM69             EXTI_IMR3_IM69_Msk                          /*!< Interrupt Mask on line 69 */

+#define EXTI_IMR3_IM70_Pos         (6U)

+#define EXTI_IMR3_IM70_Msk         (0x1UL << EXTI_IMR3_IM70_Pos)               /*!< 0x00000040 */

+#define EXTI_IMR3_IM70             EXTI_IMR3_IM70_Msk                          /*!< Interrupt Mask on line 70 */

+#define EXTI_IMR3_IM71_Pos         (7U)

+#define EXTI_IMR3_IM71_Msk         (0x1UL << EXTI_IMR3_IM71_Pos)               /*!< 0x00000080 */

+#define EXTI_IMR3_IM71             EXTI_IMR3_IM71_Msk                          /*!< Interrupt Mask on line 71 */

+#define EXTI_IMR3_IM72_Pos         (8U)

+#define EXTI_IMR3_IM72_Msk         (0x1UL << EXTI_IMR3_IM72_Pos)               /*!< 0x00000100 */

+#define EXTI_IMR3_IM72             EXTI_IMR3_IM72_Msk                          /*!< Interrupt Mask on line 72 */

+#define EXTI_IMR3_IM73_Pos         (9U)

+#define EXTI_IMR3_IM73_Msk         (0x1UL << EXTI_IMR3_IM73_Pos)               /*!< 0x00000200 */

+#define EXTI_IMR3_IM73             EXTI_IMR3_IM73_Msk                          /*!< Interrupt Mask on line 73 */

+#define EXTI_IMR3_IM74_Pos         (10U)

+#define EXTI_IMR3_IM74_Msk         (0x1UL << EXTI_IMR3_IM74_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR3_IM74             EXTI_IMR3_IM74_Msk                          /*!< Interrupt Mask on line 74 */

+#define EXTI_IMR3_IM77_Pos         (13U)

+#define EXTI_IMR3_IM77_Msk         (0x1UL << EXTI_IMR3_IM77_Pos)               /*!< 0x00002000 */

+#define EXTI_IMR3_IM77             EXTI_IMR3_IM77_Msk                          /*!< Interrupt Mask on line 77 */

+#define EXTI_IMR3_IM80_Pos         (16U)

+#define EXTI_IMR3_IM80_Msk         (0x1UL << EXTI_IMR3_IM80_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR3_IM80             EXTI_IMR3_IM80_Msk                          /*!< Interrupt Mask on line 80 */

+#define EXTI_IMR3_IM82_Pos         (18U)

+#define EXTI_IMR3_IM82_Msk         (0x1UL << EXTI_IMR3_IM82_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR3_IM82             EXTI_IMR3_IM82_Msk                          /*!< Interrupt Mask on line 82 */

+#define EXTI_IMR3_IM85_Pos         (21U)

+#define EXTI_IMR3_IM85_Msk         (0x1UL << EXTI_IMR3_IM85_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR3_IM85             EXTI_IMR3_IM85_Msk                          /*!< Interrupt Mask on line 85 */

+#define EXTI_IMR3_IM87_Pos         (23U)

+#define EXTI_IMR3_IM87_Msk         (0x1UL << EXTI_IMR3_IM87_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR3_IM87             EXTI_IMR3_IM87_Msk                          /*!< Interrupt Mask on line 87 */

+

+

+#define EXTI_IMR3_IM88_Pos         (24U)

+#define EXTI_IMR3_IM88_Msk         (0x1UL << EXTI_IMR3_IM88_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR3_IM88             EXTI_IMR3_IM88_Msk                          /*!< Interrupt Mask on line 88 */

+

+/*******************  Bit definition for EXTI_EMR3 register  *******************/

+#define EXTI_EMR3_EM_Pos           (0U)

+#define EXTI_EMR3_EM_Msk           (0x01A527FFUL << EXTI_EMR3_EM_Pos)          /*!< 0x01A527FF */

+#define EXTI_EMR3_EM               EXTI_EMR3_EM_Msk                            /*!< Event Mask           */

+#define EXTI_EMR3_EM64_Pos         (0U)

+#define EXTI_EMR3_EM64_Msk         (0x1UL << EXTI_EMR3_EM64_Pos)               /*!< 0x00000001 */

+#define EXTI_EMR3_EM64             EXTI_EMR3_EM64_Msk                          /*!< Event Mask on line 64*/

+#define EXTI_EMR3_EM65_Pos         (1U)

+#define EXTI_EMR3_EM65_Msk         (0x1UL << EXTI_EMR3_EM65_Pos)               /*!< 0x00000002 */

+#define EXTI_EMR3_EM65             EXTI_EMR3_EM65_Msk                          /*!< Event Mask on line 65*/

+#define EXTI_EMR3_EM66_Pos         (2U)

+#define EXTI_EMR3_EM66_Msk         (0x1UL << EXTI_EMR3_EM66_Pos)               /*!< 0x00000004 */

+#define EXTI_EMR3_EM66             EXTI_EMR3_EM66_Msk                          /*!< Event Mask on line 66*/

+#define EXTI_EMR3_EM67_Pos         (3U)

+#define EXTI_EMR3_EM67_Msk         (0x1UL << EXTI_EMR3_EM67_Pos)               /*!< 0x00000008 */

+#define EXTI_EMR3_EM67             EXTI_EMR3_EM67_Msk                          /*!< Event Mask on line 67*/

+#define EXTI_EMR3_EM68_Pos         (4U)

+#define EXTI_EMR3_EM68_Msk         (0x1UL << EXTI_EMR3_EM68_Pos)               /*!< 0x00000010 */

+#define EXTI_EMR3_EM68             EXTI_EMR3_EM68_Msk                          /*!< Event Mask on line 68*/

+#define EXTI_EMR3_EM69_Pos         (5U)

+#define EXTI_EMR3_EM69_Msk         (0x1UL << EXTI_EMR3_EM69_Pos)               /*!< 0x00000020 */

+#define EXTI_EMR3_EM69             EXTI_EMR3_EM69_Msk                          /*!< Event Mask on line 69*/

+#define EXTI_EMR3_EM70_Pos         (6U)

+#define EXTI_EMR3_EM70_Msk         (0x1UL << EXTI_EMR3_EM70_Pos)               /*!< 0x00000040 */

+#define EXTI_EMR3_EM70             EXTI_EMR3_EM70_Msk                          /*!< Event Mask on line 70*/

+#define EXTI_EMR3_EM71_Pos         (7U)

+#define EXTI_EMR3_EM71_Msk         (0x1UL << EXTI_EMR3_EM71_Pos)               /*!< 0x00000080 */

+#define EXTI_EMR3_EM71             EXTI_EMR3_EM71_Msk                          /*!< Event Mask on line 71*/

+#define EXTI_EMR3_EM72_Pos         (8U)

+#define EXTI_EMR3_EM72_Msk         (0x1UL << EXTI_EMR3_EM72_Pos)               /*!< 0x00000100 */

+#define EXTI_EMR3_EM72             EXTI_EMR3_EM72_Msk                          /*!< Event Mask on line 72*/

+#define EXTI_EMR3_EM73_Pos         (9U)

+#define EXTI_EMR3_EM73_Msk         (0x1UL << EXTI_EMR3_EM73_Pos)               /*!< 0x00000200 */

+#define EXTI_EMR3_EM73             EXTI_EMR3_EM73_Msk                          /*!< Event Mask on line 73*/

+#define EXTI_EMR3_EM74_Pos         (10U)

+#define EXTI_EMR3_EM74_Msk         (0x1UL << EXTI_EMR3_EM74_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR3_EM74             EXTI_EMR3_EM74_Msk                          /*!< Event Mask on line 74 */

+#define EXTI_EMR3_EM77_Pos         (13U)

+#define EXTI_EMR3_EM77_Msk         (0x1UL << EXTI_EMR3_EM77_Pos)               /*!< 0x00002000 */

+#define EXTI_EMR3_EM77             EXTI_EMR3_EM77_Msk                          /*!< Event Mask on line 77 */

+#define EXTI_EMR3_EM80_Pos         (16U)

+#define EXTI_EMR3_EM80_Msk         (0x1UL << EXTI_EMR3_EM80_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR3_EM80             EXTI_EMR3_EM80_Msk                          /*!< Event Mask on line 80 */

+#define EXTI_EMR3_EM81_Pos         (17U)

+#define EXTI_EMR3_EM81_Msk         (0x1UL << EXTI_EMR3_EM81_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR3_EM81             EXTI_EMR3_EM81_Msk                          /*!< Event Mask on line 81 */

+#define EXTI_EMR3_EM82_Pos         (18U)

+#define EXTI_EMR3_EM82_Msk         (0x1UL << EXTI_EMR3_EM82_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR3_EM82             EXTI_EMR3_EM82_Msk                          /*!< Event Mask on line 82 */

+#define EXTI_EMR3_EM85_Pos         (21U)

+#define EXTI_EMR3_EM85_Msk         (0x1UL << EXTI_EMR3_EM85_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR3_EM85             EXTI_EMR3_EM85_Msk                          /*!< Event Mask on line 85 */

+#define EXTI_EMR3_EM87_Pos         (23U)

+#define EXTI_EMR3_EM87_Msk         (0x1UL << EXTI_EMR3_EM87_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR3_EM87             EXTI_EMR3_EM87_Msk                          /*!< Event Mask on line 87 */

+

+#define EXTI_EMR3_EM88_Pos         (24U)

+#define EXTI_EMR3_EM88_Msk         (0x1UL << EXTI_EMR3_EM88_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR3_EM88             EXTI_EMR3_EM88_Msk                          /*!< Event Mask on line 88 */

+

+/*******************  Bit definition for EXTI_PR3 register  ********************/

+#define EXTI_PR3_PR_Pos            (18U)

+#define EXTI_PR3_PR_Msk            (0x9UL << EXTI_PR3_PR_Pos)                  /*!< 0x00240000 */

+#define EXTI_PR3_PR                EXTI_PR3_PR_Msk                             /*!< Pending bit             */

+#define EXTI_PR3_PR82_Pos          (18U)

+#define EXTI_PR3_PR82_Msk          (0x1UL << EXTI_PR3_PR82_Pos)                /*!< 0x00040000 */

+#define EXTI_PR3_PR82              EXTI_PR3_PR82_Msk                           /*!< Pending bit for line 82 */

+#define EXTI_PR3_PR85_Pos          (21U)

+#define EXTI_PR3_PR85_Msk          (0x1UL << EXTI_PR3_PR85_Pos)                /*!< 0x00200000 */

+#define EXTI_PR3_PR85              EXTI_PR3_PR85_Msk                           /*!< Pending bit for line 85 */

+/******************************************************************************/

+/*                                                                            */

+/*                                    FLASH                                   */

+/*                                                                            */

+/******************************************************************************/

+/*

+* @brief FLASH Global Defines

+*/

+#define FLASH_SECTOR_TOTAL                   128U                  /* 128 sectors */

+#define FLASH_SIZE                           0x200000UL            /* 2 MB   */

+#define FLASH_BANK_SIZE                      (FLASH_SIZE >> 1)     /* 1 MB   */

+#define FLASH_SECTOR_SIZE                    0x00002000UL          /* 8 KB   */

+#define FLASH_LATENCY_DEFAULT                FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycles */

+#define FLASH_NB_32BITWORD_IN_FLASHWORD      4U                    /* 128 bits */

+#define DUAL_BANK                                                  /* Dual-bank Flash */

+

+/*******************  Bits definition for FLASH_ACR register  **********************/

+#define FLASH_ACR_LATENCY_Pos                (0U)

+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */

+#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */

+#define FLASH_ACR_LATENCY_0WS                (0x00000000UL)

+#define FLASH_ACR_LATENCY_1WS                (0x00000001UL)

+#define FLASH_ACR_LATENCY_2WS                (0x00000002UL)

+#define FLASH_ACR_LATENCY_3WS                (0x00000003UL)

+#define FLASH_ACR_LATENCY_4WS                (0x00000004UL)

+#define FLASH_ACR_LATENCY_5WS                (0x00000005UL)

+#define FLASH_ACR_LATENCY_6WS                (0x00000006UL)

+#define FLASH_ACR_LATENCY_7WS                (0x00000007UL)

+#define FLASH_ACR_LATENCY_8WS                (0x00000008UL)

+#define FLASH_ACR_LATENCY_9WS                (0x00000009UL)

+#define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)

+#define FLASH_ACR_LATENCY_11WS               (0x0000000BUL)

+#define FLASH_ACR_LATENCY_12WS               (0x0000000CUL)

+#define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)

+#define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)

+#define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)

+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)

+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */

+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */

+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */

+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */

+

+/*******************  Bits definition for FLASH_CR register  ***********************/

+#define FLASH_CR_LOCK_Pos                    (0U)

+#define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */

+#define FLASH_CR_LOCK                        FLASH_CR_LOCK_Msk                 /*!< Configuration lock bit */

+#define FLASH_CR_PG_Pos                      (1U)

+#define FLASH_CR_PG_Msk                      (0x1UL << FLASH_CR_PG_Pos)        /*!< 0x00000002 */

+#define FLASH_CR_PG                          FLASH_CR_PG_Msk                   /*!< Internal buffer control bit */

+#define FLASH_CR_SER_Pos                     (2U)

+#define FLASH_CR_SER_Msk                     (0x1UL << FLASH_CR_SER_Pos)       /*!< 0x00000004 */

+#define FLASH_CR_SER                         FLASH_CR_SER_Msk                  /*!< Sector erase request */

+#define FLASH_CR_BER_Pos                     (3U)

+#define FLASH_CR_BER_Msk                     (0x1UL << FLASH_CR_BER_Pos)       /*!< 0x00000008 */

+#define FLASH_CR_BER                         FLASH_CR_BER_Msk                  /*!< Bank erase request */

+#define FLASH_CR_FW_Pos                      (4U)

+#define FLASH_CR_FW_Msk                      (0x1UL << FLASH_CR_FW_Pos)        /*!< 0x00000010 */

+#define FLASH_CR_FW                          FLASH_CR_FW_Msk                   /*!< Write forcing control bit */

+#define FLASH_CR_START_Pos                   (5U)

+#define FLASH_CR_START_Msk                   (0x1UL << FLASH_CR_START_Pos)     /*!< 0x00000020 */

+#define FLASH_CR_START                       FLASH_CR_START_Msk                /*!< Erase start control bit */

+#define FLASH_CR_SNB_Pos                     (6U)

+#define FLASH_CR_SNB_Msk                     (0x7FUL << FLASH_CR_SNB_Pos)      /*!< 0x00001FC0 */

+#define FLASH_CR_SNB                         FLASH_CR_SNB_Msk                  /*!< Sector erase selection number */

+#define FLASH_CR_SNB_0                       (0x01UL << FLASH_CR_SNB_Pos)      /*!< 0x00000040 */

+#define FLASH_CR_SNB_1                       (0x02UL << FLASH_CR_SNB_Pos)      /*!< 0x00000080 */

+#define FLASH_CR_SNB_2                       (0x04UL << FLASH_CR_SNB_Pos)      /*!< 0x00000100 */

+#define FLASH_CR_SNB_3                       (0x08UL << FLASH_CR_SNB_Pos)      /*!< 0x00000200 */

+#define FLASH_CR_SNB_4                       (0x10UL << FLASH_CR_SNB_Pos)      /*!< 0x00000400 */

+#define FLASH_CR_SNB_5                       (0x20UL << FLASH_CR_SNB_Pos)      /*!< 0x00000800 */

+#define FLASH_CR_SNB_6                       (0x40UL << FLASH_CR_SNB_Pos)      /*!< 0x00001000 */

+#define FLASH_CR_CRC_EN_Pos                  (15U)

+#define FLASH_CR_CRC_EN_Msk                  (0x1UL << FLASH_CR_CRC_EN_Pos)    /*!< 0x00008000 */

+#define FLASH_CR_CRC_EN                      FLASH_CR_CRC_EN_Msk               /*!< CRC control bit */

+#define FLASH_CR_EOPIE_Pos                   (16U)

+#define FLASH_CR_EOPIE_Msk                   (0x1UL << FLASH_CR_EOPIE_Pos)     /*!< 0x00010000 */

+#define FLASH_CR_EOPIE                       FLASH_CR_EOPIE_Msk                /*!< End-of-program interrupt control bit */

+#define FLASH_CR_WRPERRIE_Pos                (17U)

+#define FLASH_CR_WRPERRIE_Msk                (0x1UL << FLASH_CR_WRPERRIE_Pos)  /*!< 0x00020000 */

+#define FLASH_CR_WRPERRIE                    FLASH_CR_WRPERRIE_Msk             /*!< Write protection error interrupt enable bit */

+#define FLASH_CR_PGSERRIE_Pos                (18U)

+#define FLASH_CR_PGSERRIE_Msk                (0x1UL << FLASH_CR_PGSERRIE_Pos)  /*!< 0x00040000 */

+#define FLASH_CR_PGSERRIE                    FLASH_CR_PGSERRIE_Msk             /*!< Programming sequence error interrupt enable bit */

+#define FLASH_CR_STRBERRIE_Pos               (19U)

+#define FLASH_CR_STRBERRIE_Msk               (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */

+#define FLASH_CR_STRBERRIE                   FLASH_CR_STRBERRIE_Msk            /*!< Strobe error interrupt enable bit */

+#define FLASH_CR_INCERRIE_Pos                (21U)

+#define FLASH_CR_INCERRIE_Msk                (0x1UL << FLASH_CR_INCERRIE_Pos)  /*!< 0x00200000 */

+#define FLASH_CR_INCERRIE                    FLASH_CR_INCERRIE_Msk             /*!< Inconsistency error interrupt enable bit */

+#define FLASH_CR_RDPERRIE_Pos                (23U)

+#define FLASH_CR_RDPERRIE_Msk                (0x1UL << FLASH_CR_RDPERRIE_Pos)  /*!< 0x00800000 */

+#define FLASH_CR_RDPERRIE                    FLASH_CR_RDPERRIE_Msk             /*!< Read protection error interrupt enable bit */

+#define FLASH_CR_RDSERRIE_Pos                (24U)

+#define FLASH_CR_RDSERRIE_Msk                (0x1UL << FLASH_CR_RDSERRIE_Pos)  /*!< 0x01000000 */

+#define FLASH_CR_RDSERRIE                    FLASH_CR_RDSERRIE_Msk             /*!< Secure error interrupt enable bit */

+#define FLASH_CR_SNECCERRIE_Pos              (25U)

+#define FLASH_CR_SNECCERRIE_Msk              (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */

+#define FLASH_CR_SNECCERRIE                  FLASH_CR_SNECCERRIE_Msk            /*!< ECC single correction error interrupt enable bit */

+#define FLASH_CR_DBECCERRIE_Pos              (26U)

+#define FLASH_CR_DBECCERRIE_Msk              (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */

+#define FLASH_CR_DBECCERRIE                  FLASH_CR_DBECCERRIE_Msk            /*!< ECC double detection error interrupt enable bit */

+#define FLASH_CR_CRCENDIE_Pos                (27U)

+#define FLASH_CR_CRCENDIE_Msk                (0x1UL << FLASH_CR_CRCENDIE_Pos)  /*!< 0x08000000 */

+#define FLASH_CR_CRCENDIE                    FLASH_CR_CRCENDIE_Msk             /*!< CRC end of calculation interrupt enable bit */

+#define FLASH_CR_CRCRDERRIE_Pos              (28U)

+#define FLASH_CR_CRCRDERRIE_Msk              (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */

+#define FLASH_CR_CRCRDERRIE                  FLASH_CR_CRCRDERRIE_Msk            /*!< CRC read error interrupt enable bit */

+

+/*******************  Bits definition for FLASH_SR register  ***********************/

+#define FLASH_SR_BSY_Pos                     (0U)

+#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)       /*!< 0x00000001 */

+#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy flag */

+#define FLASH_SR_WBNE_Pos                    (1U)

+#define FLASH_SR_WBNE_Msk                    (0x1UL << FLASH_SR_WBNE_Pos)      /*!< 0x00000002 */

+#define FLASH_SR_WBNE                        FLASH_SR_WBNE_Msk                 /*!< Write buffer not empty flag */

+#define FLASH_SR_QW_Pos                      (2U)

+#define FLASH_SR_QW_Msk                      (0x1UL << FLASH_SR_QW_Pos)        /*!< 0x00000004 */

+#define FLASH_SR_QW                          FLASH_SR_QW_Msk                   /*!< Wait queue flag */

+#define FLASH_SR_CRC_BUSY_Pos                (3U)

+#define FLASH_SR_CRC_BUSY_Msk                (0x1UL << FLASH_SR_CRC_BUSY_Pos)  /*!< 0x00000008 */

+#define FLASH_SR_CRC_BUSY                    FLASH_SR_CRC_BUSY_Msk             /*!< CRC busy flag */

+#define FLASH_SR_EOP_Pos                     (16U)

+#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)       /*!< 0x00010000 */

+#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End-of-program flag */

+#define FLASH_SR_WRPERR_Pos                  (17U)

+#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)    /*!< 0x00020000 */

+#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protection error flag */

+#define FLASH_SR_PGSERR_Pos                  (18U)

+#define FLASH_SR_PGSERR_Msk                  (0x1UL << FLASH_SR_PGSERR_Pos)    /*!< 0x00040000 */

+#define FLASH_SR_PGSERR                      FLASH_SR_PGSERR_Msk               /*!< Programming sequence error flag */

+#define FLASH_SR_STRBERR_Pos                 (19U)

+#define FLASH_SR_STRBERR_Msk                 (0x1UL << FLASH_SR_STRBERR_Pos)   /*!< 0x00080000 */

+#define FLASH_SR_STRBERR                     FLASH_SR_STRBERR_Msk              /*!< Strobe error flag */

+#define FLASH_SR_INCERR_Pos                  (21U)

+#define FLASH_SR_INCERR_Msk                  (0x1UL << FLASH_SR_INCERR_Pos)    /*!< 0x00200000 */

+#define FLASH_SR_INCERR                      FLASH_SR_INCERR_Msk               /*!< Inconsistency error flag */

+#define FLASH_SR_RDPERR_Pos                  (23U)

+#define FLASH_SR_RDPERR_Msk                  (0x1UL << FLASH_SR_RDPERR_Pos)    /*!< 0x00800000 */

+#define FLASH_SR_RDPERR                      FLASH_SR_RDPERR_Msk               /*!< Read protection error flag */

+#define FLASH_SR_RDSERR_Pos                  (24U)

+#define FLASH_SR_RDSERR_Msk                  (0x1UL << FLASH_SR_RDSERR_Pos)    /*!< 0x01000000 */

+#define FLASH_SR_RDSERR                      FLASH_SR_RDSERR_Msk               /*!< Secure error flag */

+#define FLASH_SR_SNECCERR_Pos                (25U)

+#define FLASH_SR_SNECCERR_Msk                (0x1UL << FLASH_SR_SNECCERR_Pos)  /*!< 0x02000000 */

+#define FLASH_SR_SNECCERR                    FLASH_SR_SNECCERR_Msk             /*!< Single correction error flag */

+#define FLASH_SR_DBECCERR_Pos                (26U)

+#define FLASH_SR_DBECCERR_Msk                (0x1UL << FLASH_SR_DBECCERR_Pos)  /*!< 0x04000000 */

+#define FLASH_SR_DBECCERR                    FLASH_SR_DBECCERR_Msk             /*!< ECC double detection error flag */

+#define FLASH_SR_CRCEND_Pos                  (27U)

+#define FLASH_SR_CRCEND_Msk                  (0x1UL << FLASH_SR_CRCEND_Pos)    /*!< 0x08000000 */

+#define FLASH_SR_CRCEND                      FLASH_SR_CRCEND_Msk               /*!< CRC end of calculation flag */

+#define FLASH_SR_CRCRDERR_Pos                (28U)

+#define FLASH_SR_CRCRDERR_Msk                (0x1UL << FLASH_SR_CRCRDERR_Pos)  /*!< 0x10000000 */

+#define FLASH_SR_CRCRDERR                    FLASH_SR_CRCRDERR_Msk             /*!< CRC read error flag */

+

+/*******************  Bits definition for FLASH_CCR register  *******************/

+#define FLASH_CCR_CLR_EOP_Pos                (16U)

+#define FLASH_CCR_CLR_EOP_Msk                (0x1UL << FLASH_CCR_CLR_EOP_Pos)  /*!< 0x00010000 */

+#define FLASH_CCR_CLR_EOP                    FLASH_CCR_CLR_EOP_Msk             /*!< EOP flag clear bit */

+#define FLASH_CCR_CLR_WRPERR_Pos             (17U)

+#define FLASH_CCR_CLR_WRPERR_Msk             (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */

+#define FLASH_CCR_CLR_WRPERR                 FLASH_CCR_CLR_WRPERR_Msk            /*!< WRPERR flag clear bit */

+#define FLASH_CCR_CLR_PGSERR_Pos             (18U)

+#define FLASH_CCR_CLR_PGSERR_Msk             (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */

+#define FLASH_CCR_CLR_PGSERR                 FLASH_CCR_CLR_PGSERR_Msk            /*!< PGSERR flag clear bit */

+#define FLASH_CCR_CLR_STRBERR_Pos            (19U)

+#define FLASH_CCR_CLR_STRBERR_Msk            (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */

+#define FLASH_CCR_CLR_STRBERR                FLASH_CCR_CLR_STRBERR_Msk            /*!< STRBERR flag clear bit */

+#define FLASH_CCR_CLR_INCERR_Pos             (21U)

+#define FLASH_CCR_CLR_INCERR_Msk             (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */

+#define FLASH_CCR_CLR_INCERR                 FLASH_CCR_CLR_INCERR_Msk            /*!< INCERR flag clear bit */

+#define FLASH_CCR_CLR_RDPERR_Pos             (23U)

+#define FLASH_CCR_CLR_RDPERR_Msk             (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */

+#define FLASH_CCR_CLR_RDPERR                 FLASH_CCR_CLR_RDPERR_Msk            /*!< RDPERR flag clear bit */

+#define FLASH_CCR_CLR_RDSERR_Pos             (24U)

+#define FLASH_CCR_CLR_RDSERR_Msk             (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */

+#define FLASH_CCR_CLR_RDSERR                 FLASH_CCR_CLR_RDSERR_Msk            /*!< RDSERR flag clear bit */

+#define FLASH_CCR_CLR_SNECCERR_Pos           (25U)

+#define FLASH_CCR_CLR_SNECCERR_Msk           (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */

+#define FLASH_CCR_CLR_SNECCERR               FLASH_CCR_CLR_SNECCERR_Msk            /*!< SNECCERR flag clear bit */

+#define FLASH_CCR_CLR_DBECCERR_Pos           (26U)

+#define FLASH_CCR_CLR_DBECCERR_Msk           (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */

+#define FLASH_CCR_CLR_DBECCERR               FLASH_CCR_CLR_DBECCERR_Msk            /*!< DBECCERR flag clear bit */

+#define FLASH_CCR_CLR_CRCEND_Pos             (27U)

+#define FLASH_CCR_CLR_CRCEND_Msk             (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */

+#define FLASH_CCR_CLR_CRCEND                 FLASH_CCR_CLR_CRCEND_Msk            /*!< CRCEND flag clear bit */

+#define FLASH_CCR_CLR_CRCRDERR_Pos           (28U)

+#define FLASH_CCR_CLR_CRCRDERR_Msk           (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */

+#define FLASH_CCR_CLR_CRCRDERR               FLASH_CCR_CLR_CRCRDERR_Msk            /*!< CRCRDERR flag clear bit */

+

+/*******************  Bits definition for FLASH_OPTCR register  *******************/

+#define FLASH_OPTCR_OPTLOCK_Pos              (0U)

+#define FLASH_OPTCR_OPTLOCK_Msk              (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)  /*!< 0x00000001 */

+#define FLASH_OPTCR_OPTLOCK                  FLASH_OPTCR_OPTLOCK_Msk             /*!< FLASH_OPTCR lock option configuration bit */

+#define FLASH_OPTCR_OPTSTART_Pos             (1U)

+#define FLASH_OPTCR_OPTSTART_Msk             (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */

+#define FLASH_OPTCR_OPTSTART                 FLASH_OPTCR_OPTSTART_Msk            /*!< Option byte start change option configuration bit */

+#define FLASH_OPTCR_MER_Pos                  (4U)

+#define FLASH_OPTCR_MER_Msk                  (0x1UL << FLASH_OPTCR_MER_Pos)      /*!< 0x00000010 */

+#define FLASH_OPTCR_MER                      FLASH_OPTCR_MER_Msk                 /*!< Mass erase request */

+#define FLASH_OPTCR_PG_OTP_Pos               (5U)

+#define FLASH_OPTCR_PG_OTP_Msk               (0x1UL << FLASH_OPTCR_PG_OTP_Pos)   /*!< 0x00000020 */

+#define FLASH_OPTCR_PG_OTP                   FLASH_OPTCR_PG_OTP_Msk              /*!< OTP program control bit */

+#define FLASH_OPTCR_OPTCHANGEERRIE_Pos       (30U)

+#define FLASH_OPTCR_OPTCHANGEERRIE_Msk       (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */

+#define FLASH_OPTCR_OPTCHANGEERRIE           FLASH_OPTCR_OPTCHANGEERRIE_Msk            /*!< Option byte change error interrupt enable bit */

+#define FLASH_OPTCR_SWAP_BANK_Pos            (31U)

+#define FLASH_OPTCR_SWAP_BANK_Msk            (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */

+#define FLASH_OPTCR_SWAP_BANK                FLASH_OPTCR_SWAP_BANK_Msk            /*!< Bank swapping option configuration bit */

+

+/*******************  Bits definition for FLASH_OPTSR register  ***************/

+#define FLASH_OPTSR_OPT_BUSY_Pos             (0U)

+#define FLASH_OPTSR_OPT_BUSY_Msk             (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */

+#define FLASH_OPTSR_OPT_BUSY                 FLASH_OPTSR_OPT_BUSY_Msk            /*!< Option byte change ongoing flag */

+#define FLASH_OPTSR_BOR_LEV_Pos              (2U)

+#define FLASH_OPTSR_BOR_LEV_Msk              (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */

+#define FLASH_OPTSR_BOR_LEV                  FLASH_OPTSR_BOR_LEV_Msk            /*!< Brownout level option status bit */

+#define FLASH_OPTSR_BOR_LEV_0                (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */

+#define FLASH_OPTSR_BOR_LEV_1                (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */

+#define FLASH_OPTSR_IWDG1_SW_Pos             (4U)

+#define FLASH_OPTSR_IWDG1_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */

+#define FLASH_OPTSR_IWDG1_SW                 FLASH_OPTSR_IWDG1_SW_Msk            /*!< IWDG1 control mode option status bit */

+#define FLASH_OPTSR_NRST_STOP_D1_Pos         (6U)

+#define FLASH_OPTSR_NRST_STOP_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */

+#define FLASH_OPTSR_NRST_STOP_D1             FLASH_OPTSR_NRST_STOP_D1_Msk            /*!< D1 domain DStop entry reset option status bit */

+#define FLASH_OPTSR_NRST_STBY_D1_Pos         (7U)

+#define FLASH_OPTSR_NRST_STBY_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */

+#define FLASH_OPTSR_NRST_STBY_D1             FLASH_OPTSR_NRST_STBY_D1_Msk            /*!< D1 domain DStandby entry reset option status bit */

+#define FLASH_OPTSR_RDP_Pos                  (8U)

+#define FLASH_OPTSR_RDP_Msk                  (0xFFUL << FLASH_OPTSR_RDP_Pos)   /*!< 0x0000FF00 */

+#define FLASH_OPTSR_RDP                      FLASH_OPTSR_RDP_Msk               /*!< Readout protection level option status byte */

+#define FLASH_OPTSR_VDDMMC_HSLV_Pos          (16U)

+#define FLASH_OPTSR_VDDMMC_HSLV_Msk          (0x1UL << FLASH_OPTSR_VDDMMC_HSLV_Pos) /*!< 0x00010000 */

+#define FLASH_OPTSR_VDDMMC_HSLV              FLASH_OPTSR_VDDMMC_HSLV_Msk            /*!< VDDMMC I/O high-speed at low-voltage status bit (below 2.5V) */

+#define FLASH_OPTSR_FZ_IWDG_STOP_Pos         (17U)

+#define FLASH_OPTSR_FZ_IWDG_STOP_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */

+#define FLASH_OPTSR_FZ_IWDG_STOP             FLASH_OPTSR_FZ_IWDG_STOP_Msk            /*!< IWDG Stop mode freeze option status bit */

+#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos         (18U)

+#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */

+#define FLASH_OPTSR_FZ_IWDG_SDBY             FLASH_OPTSR_FZ_IWDG_SDBY_Msk            /*!< IWDG Standby mode freeze option status bit */

+#define FLASH_OPTSR_ST_RAM_SIZE_Pos          (19U)

+#define FLASH_OPTSR_ST_RAM_SIZE_Msk          (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */

+#define FLASH_OPTSR_ST_RAM_SIZE              FLASH_OPTSR_ST_RAM_SIZE_Msk            /*!< ST RAM size option status */

+#define FLASH_OPTSR_ST_RAM_SIZE_0            (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */

+#define FLASH_OPTSR_ST_RAM_SIZE_1            (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */

+#define FLASH_OPTSR_SECURITY_Pos             (21U)

+#define FLASH_OPTSR_SECURITY_Msk             (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */

+#define FLASH_OPTSR_SECURITY                 FLASH_OPTSR_SECURITY_Msk            /*!< Security enable option status bit */

+#define FLASH_OPTSR_IO_HSLV_Pos              (29U)

+#define FLASH_OPTSR_IO_HSLV_Msk              (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */

+#define FLASH_OPTSR_IO_HSLV                  FLASH_OPTSR_IO_HSLV_Msk            /*!< I/O high-speed at low-voltage status bit */

+#define FLASH_OPTSR_OPTCHANGEERR_Pos         (30U)

+#define FLASH_OPTSR_OPTCHANGEERR_Msk         (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */

+#define FLASH_OPTSR_OPTCHANGEERR             FLASH_OPTSR_OPTCHANGEERR_Msk            /*!< Option byte change error flag */

+#define FLASH_OPTSR_SWAP_BANK_OPT_Pos        (31U)

+#define FLASH_OPTSR_SWAP_BANK_OPT_Msk        (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */

+#define FLASH_OPTSR_SWAP_BANK_OPT            FLASH_OPTSR_SWAP_BANK_OPT_Msk            /*!< Bank swapping option status bit */

+

+/*******************  Bits definition for FLASH_OPTCCR register  *******************/

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos    (30U)

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk    (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR        FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk            /*!< OPTCHANGEERR reset bit */

+

+/*******************  Bits definition for FLASH_PRAR register  *********************/

+#define FLASH_PRAR_PROT_AREA_START_Pos       (0U)

+#define FLASH_PRAR_PROT_AREA_START_Msk       (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */

+#define FLASH_PRAR_PROT_AREA_START           FLASH_PRAR_PROT_AREA_START_Msk              /*!< PCROP area start status bits */

+#define FLASH_PRAR_PROT_AREA_END_Pos         (16U)

+#define FLASH_PRAR_PROT_AREA_END_Msk         (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */

+#define FLASH_PRAR_PROT_AREA_END             FLASH_PRAR_PROT_AREA_END_Msk              /*!< PCROP area end status bits */

+#define FLASH_PRAR_DMEP_Pos                  (31U)

+#define FLASH_PRAR_DMEP_Msk                  (0x1UL << FLASH_PRAR_DMEP_Pos)    /*!< 0x80000000 */

+#define FLASH_PRAR_DMEP                      FLASH_PRAR_DMEP_Msk               /*!< PCROP protected erase enable option status bit */

+

+/*******************  Bits definition for FLASH_SCAR register  *********************/

+#define FLASH_SCAR_SEC_AREA_START_Pos        (0U)

+#define FLASH_SCAR_SEC_AREA_START_Msk        (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */

+#define FLASH_SCAR_SEC_AREA_START            FLASH_SCAR_SEC_AREA_START_Msk              /*!< Secure-only area start status bits */

+#define FLASH_SCAR_SEC_AREA_END_Pos          (16U)

+#define FLASH_SCAR_SEC_AREA_END_Msk          (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */

+#define FLASH_SCAR_SEC_AREA_END              FLASH_SCAR_SEC_AREA_END_Msk              /*!< Secure-only area end status bits */

+#define FLASH_SCAR_DMES_Pos                  (31U)

+#define FLASH_SCAR_DMES_Msk                  (0x1UL << FLASH_SCAR_DMES_Pos)    /*!< 0x80000000 */

+#define FLASH_SCAR_DMES                      FLASH_SCAR_DMES_Msk               /*!< Secure access protected erase enable option status bit */

+

+/*******************  Bits definition for FLASH_WPSN register  *********************/

+#define FLASH_WPSN_WRPSN_Pos                 (0U)

+#define FLASH_WPSN_WRPSN_Msk                 (0xFFFFFFFFUL << FLASH_WPSN_WRPSN_Pos)  /*!< 0xFFFFFFFF */

+#define FLASH_WPSN_WRPSN                     FLASH_WPSN_WRPSN_Msk              /*!< Sector write protection option status byte */

+

+/*******************  Bits definition for FLASH_BOOT_CUR register  ****************/

+#define FLASH_BOOT_ADD0_Pos                  (0U)

+#define FLASH_BOOT_ADD0_Msk                  (0xFFFFUL << FLASH_BOOT_ADD0_Pos) /*!< 0x0000FFFF */

+#define FLASH_BOOT_ADD0                      FLASH_BOOT_ADD0_Msk               /*!< Arm Cortex-M7 boot address 0 */

+#define FLASH_BOOT_ADD1_Pos                  (16U)

+#define FLASH_BOOT_ADD1_Msk                  (0xFFFFUL << FLASH_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */

+#define FLASH_BOOT_ADD1                      FLASH_BOOT_ADD1_Msk               /*!< Arm Cortex-M7 boot address 1 */

+

+

+/*******************  Bits definition for FLASH_CRCCR register  ********************/

+#define FLASH_CRCCR_CRC_SECT_Pos             (0U)

+#define FLASH_CRCCR_CRC_SECT_Msk             (0x3FUL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x0000003F */

+#define FLASH_CRCCR_CRC_SECT                 FLASH_CRCCR_CRC_SECT_Msk             /*!< CRC sector number */

+#define FLASH_CRCCR_CRC_BY_SECT_Pos          (8U)

+#define FLASH_CRCCR_CRC_BY_SECT_Msk          (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */

+#define FLASH_CRCCR_CRC_BY_SECT              FLASH_CRCCR_CRC_BY_SECT_Msk            /*!< CRC sector mode select bit */

+#define FLASH_CRCCR_ADD_SECT_Pos             (9U)

+#define FLASH_CRCCR_ADD_SECT_Msk             (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */

+#define FLASH_CRCCR_ADD_SECT                 FLASH_CRCCR_ADD_SECT_Msk            /*!< CRC sector select bit */

+#define FLASH_CRCCR_CLEAN_SECT_Pos           (10U)

+#define FLASH_CRCCR_CLEAN_SECT_Msk           (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */

+#define FLASH_CRCCR_CLEAN_SECT               FLASH_CRCCR_CLEAN_SECT_Msk            /*!< CRC sector list clear bit */

+#define FLASH_CRCCR_START_CRC_Pos            (16U)

+#define FLASH_CRCCR_START_CRC_Msk            (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */

+#define FLASH_CRCCR_START_CRC                FLASH_CRCCR_START_CRC_Msk            /*!< CRC start bit */

+#define FLASH_CRCCR_CLEAN_CRC_Pos            (17U)

+#define FLASH_CRCCR_CLEAN_CRC_Msk            (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */

+#define FLASH_CRCCR_CLEAN_CRC                FLASH_CRCCR_CLEAN_CRC_Msk            /*!< CRC clear bit */

+#define FLASH_CRCCR_CRC_BURST_Pos            (20U)

+#define FLASH_CRCCR_CRC_BURST_Msk            (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */

+#define FLASH_CRCCR_CRC_BURST                FLASH_CRCCR_CRC_BURST_Msk            /*!< CRC burst size */

+#define FLASH_CRCCR_CRC_BURST_0              (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */

+#define FLASH_CRCCR_CRC_BURST_1              (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */

+#define FLASH_CRCCR_ALL_BANK_Pos             (22U)

+#define FLASH_CRCCR_ALL_BANK_Msk             (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */

+#define FLASH_CRCCR_ALL_BANK                 FLASH_CRCCR_ALL_BANK_Msk            /*!< CRC select bit */

+

+/*******************  Bits definition for FLASH_CRCSADD register  ****************/

+#define FLASH_CRCSADD_CRC_START_ADDR_Pos     (0U)

+#define FLASH_CRCSADD_CRC_START_ADDR_Msk     (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCSADD_CRC_START_ADDR         FLASH_CRCSADD_CRC_START_ADDR_Msk                   /*!< CRC start address */

+

+/*******************  Bits definition for FLASH_CRCEADD register  ****************/

+#define FLASH_CRCEADD_CRC_END_ADDR_Pos       (0U)

+#define FLASH_CRCEADD_CRC_END_ADDR_Msk       (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCEADD_CRC_END_ADDR           FLASH_CRCEADD_CRC_END_ADDR_Msk                   /*!< CRC end address */

+

+/*******************  Bits definition for FLASH_CRCDATA register  ***************/

+#define FLASH_CRCDATA_CRC_DATA_Pos           (0U)

+#define FLASH_CRCDATA_CRC_DATA_Msk           (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCDATA_CRC_DATA               FLASH_CRCDATA_CRC_DATA_Msk                   /*!< CRC result */

+

+/*******************  Bits definition for FLASH_ECC_FA register  *******************/

+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos       (0U)

+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk       (0xFFFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x0000FFFF */

+#define FLASH_ECC_FA_FAIL_ECC_ADDR           FLASH_ECC_FA_FAIL_ECC_ADDR_Msk               /*!< ECC error address */

+#define FLASH_ECC_FA_OTP_FAIL_ECC_Pos        (31U)

+#define FLASH_ECC_FA_OTP_FAIL_ECC_Msk        (0x1UL << FLASH_ECC_FA_OTP_FAIL_ECC_Pos) /*!< 0x80000000 */

+#define FLASH_ECC_FA_OTP_FAIL_ECC            FLASH_ECC_FA_OTP_FAIL_ECC_Msk            /*!< OTP ECC error bit */

+

+/*******************  Bits definition for FLASH_OTPBL register  *******************/

+#define FLASH_OTPBL_LOCKBL_Pos               (0U)

+#define FLASH_OTPBL_LOCKBL_Msk               (0xFFFFUL << FLASH_OTPBL_LOCKBL_Pos) /*!< 0x0000FFFF */

+#define FLASH_OTPBL_LOCKBL                   FLASH_OTPBL_LOCKBL_Msk               /*!< OTP Block Lock */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          Flexible Memory Controller                        */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for FMC_BCR1 register  *******************/

+#define FMC_BCR1_CCLKEN_Pos        (20U)

+#define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */

+#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continous clock enable     */

+#define FMC_BCR1_WFDIS_Pos         (21U)

+#define FMC_BCR1_WFDIS_Msk         (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */

+#define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */

+

+#define FMC_BCR1_BMAP_Pos          (24U)

+#define FMC_BCR1_BMAP_Msk          (0x3UL << FMC_BCR1_BMAP_Pos)                /*!< 0x03000000 */

+#define FMC_BCR1_BMAP              FMC_BCR1_BMAP_Msk                           /*!<BMAP[1:0] FMC bank mapping */

+#define FMC_BCR1_BMAP_0            (0x1UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x01000000 */

+#define FMC_BCR1_BMAP_1            (0x2UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x02000000 */

+

+#define FMC_BCR1_FMCEN_Pos         (31U)

+#define FMC_BCR1_FMCEN_Msk         (0x1UL << FMC_BCR1_FMCEN_Pos)               /*!< 0x80000000 */

+#define FMC_BCR1_FMCEN             FMC_BCR1_FMCEN_Msk                          /*!<FMC controller Enable */

+/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/

+#define FMC_BCRx_MBKEN_Pos         (0U)

+#define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */

+#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */

+#define FMC_BCRx_MUXEN_Pos         (1U)

+#define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */

+#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */

+

+#define FMC_BCRx_MTYP_Pos          (2U)

+#define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */

+#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */

+#define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000004 */

+#define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000008 */

+

+#define FMC_BCRx_MWID_Pos          (4U)

+#define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */

+#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */

+#define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000010 */

+#define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000020 */

+

+#define FMC_BCRx_FACCEN_Pos        (6U)

+#define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */

+#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */

+#define FMC_BCRx_BURSTEN_Pos       (8U)

+#define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */

+#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */

+#define FMC_BCRx_WAITPOL_Pos       (9U)

+#define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */

+#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */

+#define FMC_BCRx_WAITCFG_Pos       (11U)

+#define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */

+#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */

+#define FMC_BCRx_WREN_Pos          (12U)

+#define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */

+#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */

+#define FMC_BCRx_WAITEN_Pos        (13U)

+#define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */

+#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */

+#define FMC_BCRx_EXTMOD_Pos        (14U)

+#define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */

+#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */

+#define FMC_BCRx_ASYNCWAIT_Pos     (15U)

+#define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */

+#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */

+

+#define FMC_BCRx_CPSIZE_Pos        (16U)

+#define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */

+#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<PSIZE[2:0] bits CRAM Page Size */

+#define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00010000 */

+#define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00020000 */

+#define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00040000 */

+

+#define FMC_BCRx_CBURSTRW_Pos      (19U)

+#define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */

+#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */

+

+/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/

+#define FMC_BTRx_ADDSET_Pos        (0U)

+#define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */

+#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */

+#define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000001 */

+#define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000002 */

+#define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000004 */

+#define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000008 */

+

+#define FMC_BTRx_ADDHLD_Pos        (4U)

+#define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */

+#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */

+#define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000010 */

+#define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000020 */

+#define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000040 */

+#define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000080 */

+

+#define FMC_BTRx_DATAST_Pos        (8U)

+#define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */

+#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */

+#define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000100 */

+#define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000200 */

+#define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000400 */

+#define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000800 */

+#define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00001000 */

+#define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00002000 */

+#define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00004000 */

+#define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00008000 */

+

+#define FMC_BTRx_BUSTURN_Pos       (16U)

+#define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */

+#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */

+#define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00010000 */

+#define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00020000 */

+#define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00040000 */

+#define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00080000 */

+

+#define FMC_BTRx_CLKDIV_Pos        (20U)

+#define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */

+#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */

+#define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00100000 */

+#define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00200000 */

+#define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00400000 */

+#define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00800000 */

+

+#define FMC_BTRx_DATLAT_Pos        (24U)

+#define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */

+#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */

+#define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x01000000 */

+#define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x02000000 */

+#define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x04000000 */

+#define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x08000000 */

+

+#define FMC_BTRx_ACCMOD_Pos        (28U)

+#define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */

+#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */

+#define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x10000000 */

+#define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x20000000 */

+

+/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/

+#define FMC_BWTRx_ADDSET_Pos       (0U)

+#define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */

+#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */

+#define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000001 */

+#define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000002 */

+#define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000004 */

+#define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000008 */

+

+#define FMC_BWTRx_ADDHLD_Pos       (4U)

+#define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */

+#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */

+#define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000010 */

+#define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000020 */

+#define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000040 */

+#define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000080 */

+

+#define FMC_BWTRx_DATAST_Pos       (8U)

+#define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */

+#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */

+#define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000100 */

+#define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000200 */

+#define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000400 */

+#define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000800 */

+#define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00001000 */

+#define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00002000 */

+#define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00004000 */

+#define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00008000 */

+

+#define FMC_BWTRx_BUSTURN_Pos      (16U)

+#define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */

+#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */

+#define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00010000 */

+#define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00020000 */

+#define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00040000 */

+#define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00080000 */

+

+#define FMC_BWTRx_ACCMOD_Pos       (28U)

+#define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */

+#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */

+#define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x10000000 */

+#define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x20000000 */

+

+/******************  Bit definition for FMC_PCR register  *******************/

+#define FMC_PCR_PWAITEN_Pos        (1U)

+#define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */

+#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */

+#define FMC_PCR_PBKEN_Pos          (2U)

+#define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */

+#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */

+

+#define FMC_PCR_PWID_Pos           (4U)

+#define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */

+#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */

+#define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */

+#define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */

+

+#define FMC_PCR_ECCEN_Pos          (6U)

+#define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */

+#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */

+

+#define FMC_PCR_TCLR_Pos           (9U)

+#define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */

+#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */

+#define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */

+#define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */

+#define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */

+#define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */

+

+#define FMC_PCR_TAR_Pos            (13U)

+#define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */

+#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */

+#define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */

+#define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */

+#define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */

+#define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */

+

+#define FMC_PCR_ECCPS_Pos          (17U)

+#define FMC_PCR_ECCPS_Msk          (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */

+#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */

+#define FMC_PCR_ECCPS_0            (0x1UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */

+#define FMC_PCR_ECCPS_1            (0x2UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */

+#define FMC_PCR_ECCPS_2            (0x4UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */

+

+/*******************  Bit definition for FMC_SR register  *******************/

+#define FMC_SR_IRS_Pos             (0U)

+#define FMC_SR_IRS_Msk             (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */

+#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */

+#define FMC_SR_ILS_Pos             (1U)

+#define FMC_SR_ILS_Msk             (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */

+#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */

+#define FMC_SR_IFS_Pos             (2U)

+#define FMC_SR_IFS_Msk             (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */

+#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */

+#define FMC_SR_IREN_Pos            (3U)

+#define FMC_SR_IREN_Msk            (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */

+#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */

+#define FMC_SR_ILEN_Pos            (4U)

+#define FMC_SR_ILEN_Msk            (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */

+#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */

+#define FMC_SR_IFEN_Pos            (5U)

+#define FMC_SR_IFEN_Msk            (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */

+#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */

+#define FMC_SR_FEMPT_Pos           (6U)

+#define FMC_SR_FEMPT_Msk           (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */

+#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */

+

+/******************  Bit definition for FMC_PMEM register  ******************/

+#define FMC_PMEM_MEMSET_Pos       (0U)

+#define FMC_PMEM_MEMSET_Msk       (0xFFUL << FMC_PMEM_MEMSET_Pos)            /*!< 0x000000FF */

+#define FMC_PMEM_MEMSET           FMC_PMEM_MEMSET_Msk                        /*!<MEMSET[7:0] bits (Common memory setup time) */

+#define FMC_PMEM_MEMSET_0         (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */

+#define FMC_PMEM_MEMSET_1         (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */

+#define FMC_PMEM_MEMSET_2         (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */

+#define FMC_PMEM_MEMSET_3         (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */

+#define FMC_PMEM_MEMSET_4         (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */

+#define FMC_PMEM_MEMSET_5         (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */

+#define FMC_PMEM_MEMSET_6         (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */

+#define FMC_PMEM_MEMSET_7         (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */

+

+#define FMC_PMEM_MEMWAIT_Pos      (8U)

+#define FMC_PMEM_MEMWAIT_Msk      (0xFFUL << FMC_PMEM_MEMWAIT_Pos)           /*!< 0x0000FF00 */

+#define FMC_PMEM_MEMWAIT          FMC_PMEM_MEMWAIT_Msk                       /*!<MEMWAIT[7:0] bits (Common memory wait time) */

+#define FMC_PMEM_MEMWAIT_0        (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */

+#define FMC_PMEM_MEMWAIT_1        (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */

+#define FMC_PMEM_MEMWAIT_2        (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */

+#define FMC_PMEM_MEMWAIT_3        (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */

+#define FMC_PMEM_MEMWAIT_4        (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */

+#define FMC_PMEM_MEMWAIT_5        (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */

+#define FMC_PMEM_MEMWAIT_6        (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */

+#define FMC_PMEM_MEMWAIT_7        (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */

+

+#define FMC_PMEM_MEMHOLD_Pos      (16U)

+#define FMC_PMEM_MEMHOLD_Msk      (0xFFUL << FMC_PMEM_MEMHOLD_Pos)           /*!< 0x00FF0000 */

+#define FMC_PMEM_MEMHOLD          FMC_PMEM_MEMHOLD_Msk                       /*!<MEMHOLD[7:0] bits (Common memory hold time) */

+#define FMC_PMEM_MEMHOLD_0        (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */

+#define FMC_PMEM_MEMHOLD_1        (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */

+#define FMC_PMEM_MEMHOLD_2        (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */

+#define FMC_PMEM_MEMHOLD_3        (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */

+#define FMC_PMEM_MEMHOLD_4        (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */

+#define FMC_PMEM_MEMHOLD_5        (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */

+#define FMC_PMEM_MEMHOLD_6        (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */

+#define FMC_PMEM_MEMHOLD_7        (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */

+

+#define FMC_PMEM_MEMHIZ_Pos       (24U)

+#define FMC_PMEM_MEMHIZ_Msk       (0xFFUL << FMC_PMEM_MEMHIZ_Pos)            /*!< 0xFF000000 */

+#define FMC_PMEM_MEMHIZ           FMC_PMEM_MEMHIZ_Msk                        /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */

+#define FMC_PMEM_MEMHIZ_0         (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */

+#define FMC_PMEM_MEMHIZ_1         (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */

+#define FMC_PMEM_MEMHIZ_2         (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */

+#define FMC_PMEM_MEMHIZ_3         (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */

+#define FMC_PMEM_MEMHIZ_4         (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */

+#define FMC_PMEM_MEMHIZ_5         (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */

+#define FMC_PMEM_MEMHIZ_6         (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */

+#define FMC_PMEM_MEMHIZ_7         (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */

+

+/******************  Bit definition for FMC_PATT register  ******************/

+#define FMC_PATT_ATTSET_Pos       (0U)

+#define FMC_PATT_ATTSET_Msk       (0xFFUL << FMC_PATT_ATTSET_Pos)            /*!< 0x000000FF */

+#define FMC_PATT_ATTSET           FMC_PATT_ATTSET_Msk                        /*!<ATTSET[7:0] bits (Attribute memory setup time) */

+#define FMC_PATT_ATTSET_0         (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */

+#define FMC_PATT_ATTSET_1         (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */

+#define FMC_PATT_ATTSET_2         (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */

+#define FMC_PATT_ATTSET_3         (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */

+#define FMC_PATT_ATTSET_4         (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */

+#define FMC_PATT_ATTSET_5         (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */

+#define FMC_PATT_ATTSET_6         (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */

+#define FMC_PATT_ATTSET_7         (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */

+

+#define FMC_PATT_ATTWAIT_Pos      (8U)

+#define FMC_PATT_ATTWAIT_Msk      (0xFFUL << FMC_PATT_ATTWAIT_Pos)           /*!< 0x0000FF00 */

+#define FMC_PATT_ATTWAIT          FMC_PATT_ATTWAIT_Msk                       /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */

+#define FMC_PATT_ATTWAIT_0        (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */

+#define FMC_PATT_ATTWAIT_1        (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */

+#define FMC_PATT_ATTWAIT_2        (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */

+#define FMC_PATT_ATTWAIT_3        (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */

+#define FMC_PATT_ATTWAIT_4        (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */

+#define FMC_PATT_ATTWAIT_5        (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */

+#define FMC_PATT_ATTWAIT_6        (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */

+#define FMC_PATT_ATTWAIT_7        (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */

+

+#define FMC_PATT_ATTHOLD_Pos      (16U)

+#define FMC_PATT_ATTHOLD_Msk      (0xFFUL << FMC_PATT_ATTHOLD_Pos)           /*!< 0x00FF0000 */

+#define FMC_PATT_ATTHOLD          FMC_PATT_ATTHOLD_Msk                       /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */

+#define FMC_PATT_ATTHOLD_0        (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */

+#define FMC_PATT_ATTHOLD_1        (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */

+#define FMC_PATT_ATTHOLD_2        (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */

+#define FMC_PATT_ATTHOLD_3        (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */

+#define FMC_PATT_ATTHOLD_4        (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */

+#define FMC_PATT_ATTHOLD_5        (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */

+#define FMC_PATT_ATTHOLD_6        (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */

+#define FMC_PATT_ATTHOLD_7        (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */

+

+#define FMC_PATT_ATTHIZ_Pos       (24U)

+#define FMC_PATT_ATTHIZ_Msk       (0xFFUL << FMC_PATT_ATTHIZ_Pos)            /*!< 0xFF000000 */

+#define FMC_PATT_ATTHIZ           FMC_PATT_ATTHIZ_Msk                        /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */

+#define FMC_PATT_ATTHIZ_0         (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */

+#define FMC_PATT_ATTHIZ_1         (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */

+#define FMC_PATT_ATTHIZ_2         (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */

+#define FMC_PATT_ATTHIZ_3         (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */

+#define FMC_PATT_ATTHIZ_4         (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */

+#define FMC_PATT_ATTHIZ_5         (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */

+#define FMC_PATT_ATTHIZ_6         (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */

+#define FMC_PATT_ATTHIZ_7         (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */

+

+/******************  Bit definition for FMC_ECCR3 register  ******************/

+#define FMC_ECCR3_ECC3_Pos         (0U)

+#define FMC_ECCR3_ECC3_Msk         (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)        /*!< 0xFFFFFFFF */

+#define FMC_ECCR3_ECC3             FMC_ECCR3_ECC3_Msk                          /*!<ECC result */

+

+/******************  Bit definition for FMC_SDCRx registers (x=1..4)  *********/

+#define FMC_SDCRx_NC_Pos           (0U)

+#define FMC_SDCRx_NC_Msk           (0x3UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000003 */

+#define FMC_SDCRx_NC               FMC_SDCRx_NC_Msk                            /*!<NC[1:0] bits (Number of column bits) */

+#define FMC_SDCRx_NC_0             (0x1UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000001 */

+#define FMC_SDCRx_NC_1             (0x2UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000002 */

+

+#define FMC_SDCRx_NR_Pos           (2U)

+#define FMC_SDCRx_NR_Msk           (0x3UL << FMC_SDCRx_NR_Pos)                 /*!< 0x0000000C */

+#define FMC_SDCRx_NR               FMC_SDCRx_NR_Msk                            /*!<NR[1:0] bits (Number of row bits) */

+#define FMC_SDCRx_NR_0             (0x1UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000004 */

+#define FMC_SDCRx_NR_1             (0x2UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000008 */

+

+#define FMC_SDCRx_MWID_Pos         (4U)

+#define FMC_SDCRx_MWID_Msk         (0x3UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000030 */

+#define FMC_SDCRx_MWID             FMC_SDCRx_MWID_Msk                          /*!<NR[1:0] bits (Number of row bits) */

+#define FMC_SDCRx_MWID_0           (0x1UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000010 */

+#define FMC_SDCRx_MWID_1           (0x2UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000020 */

+

+#define FMC_SDCRx_NB_Pos           (6U)

+#define FMC_SDCRx_NB_Msk           (0x1UL << FMC_SDCRx_NB_Pos)                 /*!< 0x00000040 */

+#define FMC_SDCRx_NB               FMC_SDCRx_NB_Msk                            /*!<Number of internal bank */

+

+#define FMC_SDCRx_CAS_Pos          (7U)

+#define FMC_SDCRx_CAS_Msk          (0x3UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000180 */

+#define FMC_SDCRx_CAS              FMC_SDCRx_CAS_Msk                           /*!<CAS[1:0] bits (CAS latency) */

+#define FMC_SDCRx_CAS_0            (0x1UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000080 */

+#define FMC_SDCRx_CAS_1            (0x2UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000100 */

+

+#define FMC_SDCRx_WP_Pos           (9U)

+#define FMC_SDCRx_WP_Msk           (0x1UL << FMC_SDCRx_WP_Pos)                 /*!< 0x00000200 */

+#define FMC_SDCRx_WP               FMC_SDCRx_WP_Msk                            /*!<Write protection */

+

+#define FMC_SDCRx_SDCLK_Pos        (10U)

+#define FMC_SDCRx_SDCLK_Msk        (0x3UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000C00 */

+#define FMC_SDCRx_SDCLK            FMC_SDCRx_SDCLK_Msk                         /*!<SDRAM clock configuration */

+#define FMC_SDCRx_SDCLK_0          (0x1UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000400 */

+#define FMC_SDCRx_SDCLK_1          (0x2UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000800 */

+

+#define FMC_SDCRx_RBURST_Pos       (12U)

+#define FMC_SDCRx_RBURST_Msk       (0x1UL << FMC_SDCRx_RBURST_Pos)             /*!< 0x00001000 */

+#define FMC_SDCRx_RBURST           FMC_SDCRx_RBURST_Msk                        /*!<Read burst */

+

+#define FMC_SDCRx_RPIPE_Pos        (13U)

+#define FMC_SDCRx_RPIPE_Msk        (0x3UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00006000 */

+#define FMC_SDCRx_RPIPE            FMC_SDCRx_RPIPE_Msk                         /*!<Write protection */

+#define FMC_SDCRx_RPIPE_0          (0x1UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00002000 */

+#define FMC_SDCRx_RPIPE_1          (0x2UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00004000 */

+

+/******************  Bit definition for FMC_SDTRx(1,2) register  ******************/

+#define FMC_SDTRx_TMRD_Pos         (0U)

+#define FMC_SDTRx_TMRD_Msk         (0xFUL << FMC_SDTRx_TMRD_Pos)               /*!< 0x0000000F */

+#define FMC_SDTRx_TMRD             FMC_SDTRx_TMRD_Msk                          /*!<TMRD[3:0] bits (Load mode register to active) */

+#define FMC_SDTRx_TMRD_0           (0x1UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000001 */

+#define FMC_SDTRx_TMRD_1           (0x2UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000002 */

+#define FMC_SDTRx_TMRD_2           (0x4UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000004 */

+#define FMC_SDTRx_TMRD_3           (0x8UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000008 */

+

+#define FMC_SDTRx_TXSR_Pos         (4U)

+#define FMC_SDTRx_TXSR_Msk         (0xFUL << FMC_SDTRx_TXSR_Pos)               /*!< 0x000000F0 */

+#define FMC_SDTRx_TXSR             FMC_SDTRx_TXSR_Msk                          /*!<TXSR[3:0] bits (Exit self refresh) */

+#define FMC_SDTRx_TXSR_0           (0x1UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000010 */

+#define FMC_SDTRx_TXSR_1           (0x2UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000020 */

+#define FMC_SDTRx_TXSR_2           (0x4UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000040 */

+#define FMC_SDTRx_TXSR_3           (0x8UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000080 */

+

+#define FMC_SDTRx_TRAS_Pos         (8U)

+#define FMC_SDTRx_TRAS_Msk         (0xFUL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000F00 */

+#define FMC_SDTRx_TRAS             FMC_SDTRx_TRAS_Msk                          /*!<TRAS[3:0] bits (Self refresh time) */

+#define FMC_SDTRx_TRAS_0           (0x1UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000100 */

+#define FMC_SDTRx_TRAS_1           (0x2UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000200 */

+#define FMC_SDTRx_TRAS_2           (0x4UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000400 */

+#define FMC_SDTRx_TRAS_3           (0x8UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000800 */

+

+#define FMC_SDTRx_TRC_Pos          (12U)

+#define FMC_SDTRx_TRC_Msk          (0xFUL << FMC_SDTRx_TRC_Pos)                /*!< 0x0000F000 */

+#define FMC_SDTRx_TRC              FMC_SDTRx_TRC_Msk                           /*!<TRC[2:0] bits (Row cycle delay) */

+#define FMC_SDTRx_TRC_0            (0x1UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00001000 */

+#define FMC_SDTRx_TRC_1            (0x2UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00002000 */

+#define FMC_SDTRx_TRC_2            (0x4UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00004000 */

+

+#define FMC_SDTRx_TWR_Pos          (16U)

+#define FMC_SDTRx_TWR_Msk          (0xFUL << FMC_SDTRx_TWR_Pos)                /*!< 0x000F0000 */

+#define FMC_SDTRx_TWR              FMC_SDTRx_TWR_Msk                           /*!<TRC[2:0] bits (Write recovery delay) */

+#define FMC_SDTRx_TWR_0            (0x1UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00010000 */

+#define FMC_SDTRx_TWR_1            (0x2UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00020000 */

+#define FMC_SDTRx_TWR_2            (0x4UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00040000 */

+

+#define FMC_SDTRx_TRP_Pos          (20U)

+#define FMC_SDTRx_TRP_Msk          (0xFUL << FMC_SDTRx_TRP_Pos)                /*!< 0x00F00000 */

+#define FMC_SDTRx_TRP              FMC_SDTRx_TRP_Msk                           /*!<TRP[2:0] bits (Row precharge delay) */

+#define FMC_SDTRx_TRP_0            (0x1UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00100000 */

+#define FMC_SDTRx_TRP_1            (0x2UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00200000 */

+#define FMC_SDTRx_TRP_2            (0x4UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00400000 */

+

+#define FMC_SDTRx_TRCD_Pos         (24U)

+#define FMC_SDTRx_TRCD_Msk         (0xFUL << FMC_SDTRx_TRCD_Pos)               /*!< 0x0F000000 */

+#define FMC_SDTRx_TRCD             FMC_SDTRx_TRCD_Msk                          /*!<TRP[2:0] bits (Row to column delay) */

+#define FMC_SDTRx_TRCD_0           (0x1UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x01000000 */

+#define FMC_SDTRx_TRCD_1           (0x2UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x02000000 */

+#define FMC_SDTRx_TRCD_2           (0x4UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x04000000 */

+

+/******************  Bit definition for FMC_SDCMR register  ******************/

+#define FMC_SDCMR_MODE_Pos         (0U)

+#define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */

+#define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */

+#define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */

+#define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */

+#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */

+

+#define FMC_SDCMR_CTB2_Pos         (3U)

+#define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */

+#define FMC_SDCMR_CTB2             FMC_SDCMR_CTB2_Msk                          /*!<Command target 2 */

+

+#define FMC_SDCMR_CTB1_Pos         (4U)

+#define FMC_SDCMR_CTB1_Msk         (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */

+#define FMC_SDCMR_CTB1             FMC_SDCMR_CTB1_Msk                          /*!<Command target 1 */

+

+#define FMC_SDCMR_NRFS_Pos         (5U)

+#define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */

+#define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!<NRFS[3:0] bits (Number of auto-refresh) */

+#define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000020 */

+#define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000040 */

+#define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000080 */

+#define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000100 */

+

+#define FMC_SDCMR_MRD_Pos          (9U)

+#define FMC_SDCMR_MRD_Msk          (0x1FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */

+#define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!<MRD[12:0] bits (Mode register definition) */

+

+/******************  Bit definition for FMC_SDRTR register  ******************/

+#define FMC_SDRTR_CRE_Pos          (0U)

+#define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */

+#define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!<Clear refresh error flag */

+

+#define FMC_SDRTR_COUNT_Pos        (1U)

+#define FMC_SDRTR_COUNT_Msk        (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */

+#define FMC_SDRTR_COUNT            FMC_SDRTR_COUNT_Msk                         /*!<COUNT[12:0] bits (Refresh timer count) */

+

+#define FMC_SDRTR_REIE_Pos         (14U)

+#define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */

+#define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!<RES interupt enable */

+

+/******************  Bit definition for FMC_SDSR register  ******************/

+#define FMC_SDSR_RE_Pos            (0U)

+#define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */

+#define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!<Refresh error flag */

+

+#define FMC_SDSR_MODES1_Pos        (1U)

+#define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */

+#define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!<MODES1[1:0]bits (Status mode for bank 1) */

+#define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000002 */

+#define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000004 */

+

+#define FMC_SDSR_MODES2_Pos        (3U)

+#define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */

+#define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!<MODES2[1:0]bits (Status mode for bank 2) */

+#define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000008 */

+#define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000010 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                       Graphic MMU (GFXMMU)                                 */

+/*                                                                            */

+/******************************************************************************/

+/****************** Bits definition for GFXMMU_CR register ********************/

+#define GFXMMU_CR_B0OIE_Pos                (0U)

+#define GFXMMU_CR_B0OIE_Msk                (0x1UL << GFXMMU_CR_B0OIE_Pos)       /*!< 0x00000001 */

+#define GFXMMU_CR_B0OIE                    GFXMMU_CR_B0OIE_Msk                 /*!< Buffer 0 overflow interrupt enable */

+#define GFXMMU_CR_B1OIE_Pos                (1U)

+#define GFXMMU_CR_B1OIE_Msk                (0x1UL << GFXMMU_CR_B1OIE_Pos)       /*!< 0x00000002 */

+#define GFXMMU_CR_B1OIE                    GFXMMU_CR_B1OIE_Msk                 /*!< Buffer 1 overflow interrupt enable */

+#define GFXMMU_CR_B2OIE_Pos                (2U)

+#define GFXMMU_CR_B2OIE_Msk                (0x1UL << GFXMMU_CR_B2OIE_Pos)       /*!< 0x00000004 */

+#define GFXMMU_CR_B2OIE                    GFXMMU_CR_B2OIE_Msk                 /*!< Buffer 2 overflow interrupt enable */

+#define GFXMMU_CR_B3OIE_Pos                (3U)

+#define GFXMMU_CR_B3OIE_Msk                (0x1UL << GFXMMU_CR_B3OIE_Pos)       /*!< 0x00000008 */

+#define GFXMMU_CR_B3OIE                    GFXMMU_CR_B3OIE_Msk                 /*!< Buffer 3 overflow interrupt enable */

+#define GFXMMU_CR_AMEIE_Pos                (4U)

+#define GFXMMU_CR_AMEIE_Msk                (0x1UL << GFXMMU_CR_AMEIE_Pos)       /*!< 0x00000010 */

+#define GFXMMU_CR_AMEIE                    GFXMMU_CR_AMEIE_Msk                 /*!< AHB master error interrupt enable */

+#define GFXMMU_CR_192BM_Pos                (6U)

+#define GFXMMU_CR_192BM_Msk                (0x1UL << GFXMMU_CR_192BM_Pos)       /*!< 0x00000040 */

+#define GFXMMU_CR_192BM                    GFXMMU_CR_192BM_Msk                 /*!< 192 block mode */

+#define GFXMMU_CR_CE_Pos                   (7U)

+#define GFXMMU_CR_CE_Msk                   (0x1UL << GFXMMU_CR_CE_Pos)          /*!< 0x00000080 */

+#define GFXMMU_CR_CE                       GFXMMU_CR_CE_Msk                    /*!< Cache Enable */

+#define GFXMMU_CR_CL_Pos                   (8U)

+#define GFXMMU_CR_CL_Msk                   (0x1UL << GFXMMU_CR_CL_Pos)          /*!< 0x00000100 */

+#define GFXMMU_CR_CL                       GFXMMU_CR_CL_Msk                    /*!< Cache Lock */

+#define GFXMMU_CR_CLB_Pos                  (9U)

+#define GFXMMU_CR_CLB_Msk                  (0x3UL << GFXMMU_CR_CLB_Pos)         /*!< 0x00000600 */

+#define GFXMMU_CR_CLB                      GFXMMU_CR_CLB_Msk                   /*!< CLB[1:0]: Cache Lock Buffer */

+#define GFXMMU_CR_CLB_0                    (0x1UL << GFXMMU_CR_CLB_Pos)         /*!< Cache locked on buffer 1 */

+#define GFXMMU_CR_CLB_1                    (0x2UL << GFXMMU_CR_CLB_Pos)         /*!< Cache locked on buffer 2 */

+#define GFXMMU_CR_FC_Pos                   (11U)

+#define GFXMMU_CR_FC_Msk                   (0x1UL << GFXMMU_CR_FC_Pos)          /*!< 0x00000800 */

+#define GFXMMU_CR_FC                       GFXMMU_CR_FC_Msk                    /*!< Force Caching */

+#define GFXMMU_CR_PD_Pos                   (12U)

+#define GFXMMU_CR_PD_Msk                   (0x1UL << GFXMMU_CR_PD_Pos)          /*!< 0x00001000 */

+#define GFXMMU_CR_PD                       GFXMMU_CR_PD_Msk                    /*!< Prefetch Disable */

+#define GFXMMU_CR_OC_Pos                   (16U)

+#define GFXMMU_CR_OC_Msk                   (0x1UL << GFXMMU_CR_OC_Pos)          /*!< 0x00002000 */

+#define GFXMMU_CR_OC                       GFXMMU_CR_OC_Msk                    /*!< Outter Cachability */

+#define GFXMMU_CR_OB_Pos                   (17U)

+#define GFXMMU_CR_OB_Msk                   (0x1UL << GFXMMU_CR_OB_Pos)          /*!< 0x00002000 */

+#define GFXMMU_CR_OB                       GFXMMU_CR_OB_Msk                    /*!< Outter Bufferability */

+

+/****************** Bits definition for GFXMMU_SR register ********************/

+#define GFXMMU_SR_B0OF_Pos                 (0U)

+#define GFXMMU_SR_B0OF_Msk                 (0x1UL << GFXMMU_SR_B0OF_Pos)        /*!< 0x00000001 */

+#define GFXMMU_SR_B0OF                     GFXMMU_SR_B0OF_Msk                  /*!< Buffer 0 overflow flag */

+#define GFXMMU_SR_B1OF_Pos                 (1U)

+#define GFXMMU_SR_B1OF_Msk                 (0x1UL << GFXMMU_SR_B1OF_Pos)        /*!< 0x00000002 */

+#define GFXMMU_SR_B1OF                     GFXMMU_SR_B1OF_Msk                  /*!< Buffer 1 overflow flag */

+#define GFXMMU_SR_B2OF_Pos                 (2U)

+#define GFXMMU_SR_B2OF_Msk                 (0x1UL << GFXMMU_SR_B2OF_Pos)        /*!< 0x00000004 */

+#define GFXMMU_SR_B2OF                     GFXMMU_SR_B2OF_Msk                  /*!< Buffer 2 overflow flag */

+#define GFXMMU_SR_B3OF_Pos                 (3U)

+#define GFXMMU_SR_B3OF_Msk                 (0x1UL << GFXMMU_SR_B3OF_Pos)        /*!< 0x00000008 */

+#define GFXMMU_SR_B3OF                     GFXMMU_SR_B3OF_Msk                  /*!< Buffer 3 overflow flag */

+#define GFXMMU_SR_AMEF_Pos                 (4U)

+#define GFXMMU_SR_AMEF_Msk                 (0x1UL << GFXMMU_SR_AMEF_Pos)        /*!< 0x00000010 */

+#define GFXMMU_SR_AMEF                     GFXMMU_SR_AMEF_Msk                  /*!< AHB master error flag */

+

+/****************** Bits definition for GFXMMU_FCR register *******************/

+#define GFXMMU_FCR_CB0OF_Pos               (0U)

+#define GFXMMU_FCR_CB0OF_Msk               (0x1UL << GFXMMU_FCR_CB0OF_Pos)      /*!< 0x00000001 */

+#define GFXMMU_FCR_CB0OF                   GFXMMU_FCR_CB0OF_Msk                /*!< Clear buffer 0 overflow flag */

+#define GFXMMU_FCR_CB1OF_Pos               (1U)

+#define GFXMMU_FCR_CB1OF_Msk               (0x1UL << GFXMMU_FCR_CB1OF_Pos)      /*!< 0x00000002 */

+#define GFXMMU_FCR_CB1OF                   GFXMMU_FCR_CB1OF_Msk                /*!< Clear buffer 1 overflow flag */

+#define GFXMMU_FCR_CB2OF_Pos               (2U)

+#define GFXMMU_FCR_CB2OF_Msk               (0x1UL << GFXMMU_FCR_CB2OF_Pos)      /*!< 0x00000004 */

+#define GFXMMU_FCR_CB2OF                   GFXMMU_FCR_CB2OF_Msk                /*!< Clear buffer 2 overflow flag */

+#define GFXMMU_FCR_CB3OF_Pos               (3U)

+#define GFXMMU_FCR_CB3OF_Msk               (0x1UL << GFXMMU_FCR_CB3OF_Pos)      /*!< 0x00000008 */

+#define GFXMMU_FCR_CB3OF                   GFXMMU_FCR_CB3OF_Msk                /*!< Clear buffer 3 overflow flag */

+#define GFXMMU_FCR_CAMEF_Pos               (4U)

+#define GFXMMU_FCR_CAMEF_Msk               (0x1UL << GFXMMU_FCR_CAMEF_Pos)      /*!< 0x00000010 */

+#define GFXMMU_FCR_CAMEF                   GFXMMU_FCR_CAMEF_Msk                /*!< Clear AHB master error flag */

+

+/****************** Bits definition for GFXMMU_CCR register *******************/

+#define GFXMMU_CCR_FF_Pos                  (0U)

+#define GFXMMU_CCR_FF_Msk                  (0x1UL << GFXMMU_CCR_FF_Pos)         /*!< 0x00000001 */

+#define GFXMMU_CCR_FF                      GFXMMU_CCR_FF_Msk                   /*!< Clear buffer 0 overflow flag */

+#define GFXMMU_CCR_FI_Pos                  (1U)

+#define GFXMMU_CCR_FI_Msk                  (0x1UL << GFXMMU_CCR_FI_Pos)         /*!< 0x00000002 */

+#define GFXMMU_CCR_FI                      GFXMMU_CCR_FI_Msk                   /*!< Clear buffer 1 overflow flag */

+

+/****************** Bits definition for GFXMMU_DVR register *******************/

+#define GFXMMU_DVR_DV_Pos                  (0U)

+#define GFXMMU_DVR_DV_Msk                  (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos)  /*!< 0xFFFFFFFF */

+#define GFXMMU_DVR_DV                      GFXMMU_DVR_DV_Msk                   /*!< DV[31:0] bits (Default value) */

+

+/****************** Bits definition for GFXMMU_B0CR register ******************/

+#define GFXMMU_B0CR_PBO_Pos                (4U)

+#define GFXMMU_B0CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B0CR_PBO_Pos)   /*!< 0x007FFFF0 */

+#define GFXMMU_B0CR_PBO                    GFXMMU_B0CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */

+#define GFXMMU_B0CR_PBBA_Pos               (23U)

+#define GFXMMU_B0CR_PBBA_Msk               (0x1FFUL << GFXMMU_B0CR_PBBA_Pos)    /*!< 0xFF800000 */

+#define GFXMMU_B0CR_PBBA                   GFXMMU_B0CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */

+

+/****************** Bits definition for GFXMMU_B1CR register ******************/

+#define GFXMMU_B1CR_PBO_Pos                (4U)

+#define GFXMMU_B1CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos)   /*!< 0x007FFFF0 */

+#define GFXMMU_B1CR_PBO                    GFXMMU_B1CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */

+#define GFXMMU_B1CR_PBBA_Pos               (23U)

+#define GFXMMU_B1CR_PBBA_Msk               (0x1FFUL << GFXMMU_B1CR_PBBA_Pos)    /*!< 0xFF800000 */

+#define GFXMMU_B1CR_PBBA                   GFXMMU_B1CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */

+

+/****************** Bits definition for GFXMMU_B2CR register ******************/

+#define GFXMMU_B2CR_PBO_Pos                (4U)

+#define GFXMMU_B2CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B2CR_PBO_Pos)   /*!< 0x007FFFF0 */

+#define GFXMMU_B2CR_PBO                    GFXMMU_B2CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */

+#define GFXMMU_B2CR_PBBA_Pos               (23U)

+#define GFXMMU_B2CR_PBBA_Msk               (0x1FFUL << GFXMMU_B2CR_PBBA_Pos)    /*!< 0xFF800000 */

+#define GFXMMU_B2CR_PBBA                   GFXMMU_B2CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */

+

+/****************** Bits definition for GFXMMU_B3CR register ******************/

+#define GFXMMU_B3CR_PBO_Pos                (4U)

+#define GFXMMU_B3CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B3CR_PBO_Pos)   /*!< 0x007FFFF0 */

+#define GFXMMU_B3CR_PBO                    GFXMMU_B3CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */

+#define GFXMMU_B3CR_PBBA_Pos               (23U)

+#define GFXMMU_B3CR_PBBA_Msk               (0x1FFUL << GFXMMU_B3CR_PBBA_Pos)    /*!< 0xFF800000 */

+#define GFXMMU_B3CR_PBBA                   GFXMMU_B3CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */

+

+/****************** Bits definition for GFXMMU_LUTxL register *****************/

+#define GFXMMU_LUTxL_EN_Pos                (0U)

+#define GFXMMU_LUTxL_EN_Msk                (0x1UL << GFXMMU_LUTxL_EN_Pos)       /*!< 0x00000001 */

+#define GFXMMU_LUTxL_EN                    GFXMMU_LUTxL_EN_Msk                 /*!< Enable */

+#define GFXMMU_LUTxL_FVB_Pos               (8U)

+#define GFXMMU_LUTxL_FVB_Msk               (0xFFUL << GFXMMU_LUTxL_FVB_Pos)     /*!< 0x0000FF00 */

+#define GFXMMU_LUTxL_FVB                   GFXMMU_LUTxL_FVB_Msk                /*!< FVB[7:0] bits (First visible block) */

+#define GFXMMU_LUTxL_LVB_Pos               (16U)

+#define GFXMMU_LUTxL_LVB_Msk               (0xFFUL << GFXMMU_LUTxL_LVB_Pos)     /*!< 0x00FF0000 */

+#define GFXMMU_LUTxL_LVB                   GFXMMU_LUTxL_LVB_Msk                /*!< LVB[7:0] bits (Last visible block) */

+

+/****************** Bits definition for GFXMMU_LUTxH register *****************/

+#define GFXMMU_LUTxH_LO_Pos                (4U)

+#define GFXMMU_LUTxH_LO_Msk                (0x3FFFFUL << GFXMMU_LUTxH_LO_Pos)   /*!< 0x003FFFF0 */

+#define GFXMMU_LUTxH_LO                    GFXMMU_LUTxH_LO_Msk                 /*!< LO[21:4] bits (Line offset) */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            General Purpose I/O                             */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bits definition for GPIO_MODER register  *****************/

+#define GPIO_MODER_MODE0_Pos           (0U)

+#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */

+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk

+#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */

+#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */

+

+#define GPIO_MODER_MODE1_Pos           (2U)

+#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */

+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk

+#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */

+#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */

+

+#define GPIO_MODER_MODE2_Pos           (4U)

+#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */

+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk

+#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */

+#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */

+

+#define GPIO_MODER_MODE3_Pos           (6U)

+#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */

+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk

+#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */

+#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */

+

+#define GPIO_MODER_MODE4_Pos           (8U)

+#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */

+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk

+#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */

+#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */

+

+#define GPIO_MODER_MODE5_Pos           (10U)

+#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */

+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk

+#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */

+#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */

+

+#define GPIO_MODER_MODE6_Pos           (12U)

+#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */

+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk

+#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */

+#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */

+

+#define GPIO_MODER_MODE7_Pos           (14U)

+#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */

+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk

+#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */

+#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */

+

+#define GPIO_MODER_MODE8_Pos           (16U)

+#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */

+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk

+#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */

+#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */

+

+#define GPIO_MODER_MODE9_Pos           (18U)

+#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */

+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk

+#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */

+#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */

+

+#define GPIO_MODER_MODE10_Pos          (20U)

+#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */

+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk

+#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */

+#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */

+

+#define GPIO_MODER_MODE11_Pos          (22U)

+#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */

+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk

+#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */

+#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */

+

+#define GPIO_MODER_MODE12_Pos          (24U)

+#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */

+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk

+#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */

+#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */

+

+#define GPIO_MODER_MODE13_Pos          (26U)

+#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */

+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk

+#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */

+#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */

+

+#define GPIO_MODER_MODE14_Pos          (28U)

+#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */

+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk

+#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */

+#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */

+

+#define GPIO_MODER_MODE15_Pos          (30U)

+#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */

+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk

+#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */

+#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_OTYPER register  ****************/

+#define GPIO_OTYPER_OT0_Pos            (0U)

+#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */

+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk

+#define GPIO_OTYPER_OT1_Pos            (1U)

+#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */

+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk

+#define GPIO_OTYPER_OT2_Pos            (2U)

+#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */

+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk

+#define GPIO_OTYPER_OT3_Pos            (3U)

+#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */

+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk

+#define GPIO_OTYPER_OT4_Pos            (4U)

+#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */

+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk

+#define GPIO_OTYPER_OT5_Pos            (5U)

+#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */

+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk

+#define GPIO_OTYPER_OT6_Pos            (6U)

+#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */

+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk

+#define GPIO_OTYPER_OT7_Pos            (7U)

+#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */

+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk

+#define GPIO_OTYPER_OT8_Pos            (8U)

+#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */

+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk

+#define GPIO_OTYPER_OT9_Pos            (9U)

+#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */

+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk

+#define GPIO_OTYPER_OT10_Pos           (10U)

+#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */

+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk

+#define GPIO_OTYPER_OT11_Pos           (11U)

+#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */

+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk

+#define GPIO_OTYPER_OT12_Pos           (12U)

+#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */

+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk

+#define GPIO_OTYPER_OT13_Pos           (13U)

+#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */

+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk

+#define GPIO_OTYPER_OT14_Pos           (14U)

+#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */

+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk

+#define GPIO_OTYPER_OT15_Pos           (15U)

+#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */

+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk

+

+/******************  Bits definition for GPIO_OSPEEDR register  ***************/

+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)

+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */

+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk

+#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */

+#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */

+

+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)

+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */

+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk

+#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */

+#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */

+

+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)

+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */

+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk

+#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */

+#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */

+

+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)

+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */

+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk

+#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */

+#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */

+

+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)

+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */

+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk

+#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */

+#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */

+

+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)

+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */

+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk

+#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */

+#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */

+

+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)

+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */

+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk

+#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */

+#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */

+

+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)

+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */

+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk

+#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */

+#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */

+

+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)

+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */

+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk

+#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */

+#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */

+

+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)

+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */

+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk

+#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */

+#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */

+

+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)

+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */

+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk

+#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */

+#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */

+

+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)

+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */

+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk

+#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */

+#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */

+

+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)

+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */

+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk

+#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */

+#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */

+

+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)

+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */

+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk

+#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */

+#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */

+

+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)

+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */

+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk

+#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */

+#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */

+

+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)

+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */

+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk

+#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */

+#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_PUPDR register  *****************/

+#define GPIO_PUPDR_PUPD0_Pos           (0U)

+#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */

+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk

+#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */

+#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */

+

+#define GPIO_PUPDR_PUPD1_Pos           (2U)

+#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */

+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk

+#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */

+#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */

+

+#define GPIO_PUPDR_PUPD2_Pos           (4U)

+#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */

+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk

+#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */

+#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */

+

+#define GPIO_PUPDR_PUPD3_Pos           (6U)

+#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */

+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk

+#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */

+#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */

+

+#define GPIO_PUPDR_PUPD4_Pos           (8U)

+#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */

+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk

+#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */

+#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */

+

+#define GPIO_PUPDR_PUPD5_Pos           (10U)

+#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */

+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk

+#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */

+#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */

+

+#define GPIO_PUPDR_PUPD6_Pos           (12U)

+#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */

+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk

+#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */

+#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */

+

+#define GPIO_PUPDR_PUPD7_Pos           (14U)

+#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */

+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk

+#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */

+#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */

+

+#define GPIO_PUPDR_PUPD8_Pos           (16U)

+#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */

+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk

+#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */

+#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */

+

+#define GPIO_PUPDR_PUPD9_Pos           (18U)

+#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */

+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk

+#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */

+#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */

+

+#define GPIO_PUPDR_PUPD10_Pos          (20U)

+#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */

+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk

+#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */

+#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */

+

+#define GPIO_PUPDR_PUPD11_Pos          (22U)

+#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */

+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk

+#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */

+#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */

+

+#define GPIO_PUPDR_PUPD12_Pos          (24U)

+#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */

+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk

+#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */

+#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */

+

+#define GPIO_PUPDR_PUPD13_Pos          (26U)

+#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */

+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk

+#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */

+#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */

+

+#define GPIO_PUPDR_PUPD14_Pos          (28U)

+#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */

+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk

+#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */

+#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */

+

+#define GPIO_PUPDR_PUPD15_Pos          (30U)

+#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */

+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk

+#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */

+#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_IDR register  *******************/

+#define GPIO_IDR_ID0_Pos               (0U)

+#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */

+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk

+#define GPIO_IDR_ID1_Pos               (1U)

+#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */

+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk

+#define GPIO_IDR_ID2_Pos               (2U)

+#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */

+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk

+#define GPIO_IDR_ID3_Pos               (3U)

+#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */

+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk

+#define GPIO_IDR_ID4_Pos               (4U)

+#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */

+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk

+#define GPIO_IDR_ID5_Pos               (5U)

+#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */

+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk

+#define GPIO_IDR_ID6_Pos               (6U)

+#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */

+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk

+#define GPIO_IDR_ID7_Pos               (7U)

+#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */

+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk

+#define GPIO_IDR_ID8_Pos               (8U)

+#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */

+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk

+#define GPIO_IDR_ID9_Pos               (9U)

+#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */

+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk

+#define GPIO_IDR_ID10_Pos              (10U)

+#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */

+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk

+#define GPIO_IDR_ID11_Pos              (11U)

+#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */

+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk

+#define GPIO_IDR_ID12_Pos              (12U)

+#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */

+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk

+#define GPIO_IDR_ID13_Pos              (13U)

+#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */

+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk

+#define GPIO_IDR_ID14_Pos              (14U)

+#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */

+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk

+#define GPIO_IDR_ID15_Pos              (15U)

+#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */

+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk

+

+/******************  Bits definition for GPIO_ODR register  *******************/

+#define GPIO_ODR_OD0_Pos               (0U)

+#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */

+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk

+#define GPIO_ODR_OD1_Pos               (1U)

+#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */

+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk

+#define GPIO_ODR_OD2_Pos               (2U)

+#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */

+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk

+#define GPIO_ODR_OD3_Pos               (3U)

+#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */

+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk

+#define GPIO_ODR_OD4_Pos               (4U)

+#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */

+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk

+#define GPIO_ODR_OD5_Pos               (5U)

+#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */

+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk

+#define GPIO_ODR_OD6_Pos               (6U)

+#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */

+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk

+#define GPIO_ODR_OD7_Pos               (7U)

+#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */

+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk

+#define GPIO_ODR_OD8_Pos               (8U)

+#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */

+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk

+#define GPIO_ODR_OD9_Pos               (9U)

+#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */

+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk

+#define GPIO_ODR_OD10_Pos              (10U)

+#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */

+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk

+#define GPIO_ODR_OD11_Pos              (11U)

+#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */

+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk

+#define GPIO_ODR_OD12_Pos              (12U)

+#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */

+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk

+#define GPIO_ODR_OD13_Pos              (13U)

+#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */

+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk

+#define GPIO_ODR_OD14_Pos              (14U)

+#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */

+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk

+#define GPIO_ODR_OD15_Pos              (15U)

+#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */

+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk

+

+/******************  Bits definition for GPIO_BSRR register  ******************/

+#define GPIO_BSRR_BS0_Pos              (0U)

+#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */

+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk

+#define GPIO_BSRR_BS1_Pos              (1U)

+#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */

+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk

+#define GPIO_BSRR_BS2_Pos              (2U)

+#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */

+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk

+#define GPIO_BSRR_BS3_Pos              (3U)

+#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */

+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk

+#define GPIO_BSRR_BS4_Pos              (4U)

+#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */

+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk

+#define GPIO_BSRR_BS5_Pos              (5U)

+#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */

+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk

+#define GPIO_BSRR_BS6_Pos              (6U)

+#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */

+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk

+#define GPIO_BSRR_BS7_Pos              (7U)

+#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */

+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk

+#define GPIO_BSRR_BS8_Pos              (8U)

+#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */

+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk

+#define GPIO_BSRR_BS9_Pos              (9U)

+#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */

+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk

+#define GPIO_BSRR_BS10_Pos             (10U)

+#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */

+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk

+#define GPIO_BSRR_BS11_Pos             (11U)

+#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */

+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk

+#define GPIO_BSRR_BS12_Pos             (12U)

+#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */

+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk

+#define GPIO_BSRR_BS13_Pos             (13U)

+#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */

+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk

+#define GPIO_BSRR_BS14_Pos             (14U)

+#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */

+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk

+#define GPIO_BSRR_BS15_Pos             (15U)

+#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */

+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk

+#define GPIO_BSRR_BR0_Pos              (16U)

+#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */

+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk

+#define GPIO_BSRR_BR1_Pos              (17U)

+#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */

+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk

+#define GPIO_BSRR_BR2_Pos              (18U)

+#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */

+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk

+#define GPIO_BSRR_BR3_Pos              (19U)

+#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */

+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk

+#define GPIO_BSRR_BR4_Pos              (20U)

+#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */

+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk

+#define GPIO_BSRR_BR5_Pos              (21U)

+#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */

+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk

+#define GPIO_BSRR_BR6_Pos              (22U)

+#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */

+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk

+#define GPIO_BSRR_BR7_Pos              (23U)

+#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */

+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk

+#define GPIO_BSRR_BR8_Pos              (24U)

+#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */

+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk

+#define GPIO_BSRR_BR9_Pos              (25U)

+#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */

+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk

+#define GPIO_BSRR_BR10_Pos             (26U)

+#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */

+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk

+#define GPIO_BSRR_BR11_Pos             (27U)

+#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */

+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk

+#define GPIO_BSRR_BR12_Pos             (28U)

+#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */

+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk

+#define GPIO_BSRR_BR13_Pos             (29U)

+#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */

+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk

+#define GPIO_BSRR_BR14_Pos             (30U)

+#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */

+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk

+#define GPIO_BSRR_BR15_Pos             (31U)

+#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */

+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk

+

+/****************** Bit definition for GPIO_LCKR register *********************/

+#define GPIO_LCKR_LCK0_Pos             (0U)

+#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */

+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk

+#define GPIO_LCKR_LCK1_Pos             (1U)

+#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */

+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk

+#define GPIO_LCKR_LCK2_Pos             (2U)

+#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */

+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk

+#define GPIO_LCKR_LCK3_Pos             (3U)

+#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */

+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk

+#define GPIO_LCKR_LCK4_Pos             (4U)

+#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */

+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk

+#define GPIO_LCKR_LCK5_Pos             (5U)

+#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */

+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk

+#define GPIO_LCKR_LCK6_Pos             (6U)

+#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */

+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk

+#define GPIO_LCKR_LCK7_Pos             (7U)

+#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */

+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk

+#define GPIO_LCKR_LCK8_Pos             (8U)

+#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */

+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk

+#define GPIO_LCKR_LCK9_Pos             (9U)

+#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */

+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk

+#define GPIO_LCKR_LCK10_Pos            (10U)

+#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */

+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk

+#define GPIO_LCKR_LCK11_Pos            (11U)

+#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */

+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk

+#define GPIO_LCKR_LCK12_Pos            (12U)

+#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */

+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk

+#define GPIO_LCKR_LCK13_Pos            (13U)

+#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */

+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk

+#define GPIO_LCKR_LCK14_Pos            (14U)

+#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */

+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk

+#define GPIO_LCKR_LCK15_Pos            (15U)

+#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */

+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk

+#define GPIO_LCKR_LCKK_Pos             (16U)

+#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */

+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk

+

+/****************** Bit definition for GPIO_AFRL register  ********************/

+#define GPIO_AFRL_AFSEL0_Pos           (0U)

+#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */

+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk

+#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */

+#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */

+#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */

+#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */

+#define GPIO_AFRL_AFSEL1_Pos           (4U)

+#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */

+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk

+#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */

+#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */

+#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */

+#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */

+#define GPIO_AFRL_AFSEL2_Pos           (8U)

+#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */

+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk

+#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */

+#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */

+#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */

+#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */

+#define GPIO_AFRL_AFSEL3_Pos           (12U)

+#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */

+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk

+#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */

+#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */

+#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */

+#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */

+#define GPIO_AFRL_AFSEL4_Pos           (16U)

+#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */

+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk

+#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */

+#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */

+#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */

+#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */

+#define GPIO_AFRL_AFSEL5_Pos           (20U)

+#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */

+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk

+#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */

+#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */

+#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */

+#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */

+#define GPIO_AFRL_AFSEL6_Pos           (24U)

+#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */

+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk

+#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */

+#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */

+#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */

+#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */

+#define GPIO_AFRL_AFSEL7_Pos           (28U)

+#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */

+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk

+#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */

+#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */

+#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */

+#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */

+

+/* Legacy defines */

+#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0

+#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1

+#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2

+#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3

+#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4

+#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5

+#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6

+#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7

+

+/****************** Bit definition for GPIO_AFRH register  ********************/

+#define GPIO_AFRH_AFSEL8_Pos           (0U)

+#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */

+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk

+#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */

+#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */

+#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */

+#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */

+#define GPIO_AFRH_AFSEL9_Pos           (4U)

+#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */

+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk

+#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */

+#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */

+#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */

+#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */

+#define GPIO_AFRH_AFSEL10_Pos          (8U)

+#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */

+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk

+#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */

+#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */

+#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */

+#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */

+#define GPIO_AFRH_AFSEL11_Pos          (12U)

+#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */

+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk

+#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */

+#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */

+#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */

+#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */

+#define GPIO_AFRH_AFSEL12_Pos          (16U)

+#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */

+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk

+#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */

+#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */

+#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */

+#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */

+#define GPIO_AFRH_AFSEL13_Pos          (20U)

+#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */

+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk

+#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */

+#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */

+#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */

+#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */

+#define GPIO_AFRH_AFSEL14_Pos          (24U)

+#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */

+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk

+#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */

+#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */

+#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */

+#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */

+#define GPIO_AFRH_AFSEL15_Pos          (28U)

+#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */

+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk

+#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */

+#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */

+#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */

+#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */

+

+/* Legacy defines */

+#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8

+#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9

+#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10

+#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11

+#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12

+#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13

+#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14

+#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15

+

+/******************************************************************************/

+/*                                                                            */

+/*                        HSEM HW Semaphore                                   */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for HSEM_R register  ********************/

+#define HSEM_R_PROCID_Pos         (0U)

+#define HSEM_R_PROCID_Msk         (0xFFUL << HSEM_R_PROCID_Pos)                /*!< 0x000000FF */

+#define HSEM_R_PROCID             HSEM_R_PROCID_Msk                            /*!<Semaphore ProcessID */

+#define HSEM_R_COREID_Pos         (8U)

+#define HSEM_R_COREID_Msk         (0xFFUL << HSEM_R_COREID_Pos)                /*!< 0x0000FF00 */

+#define HSEM_R_COREID             HSEM_R_COREID_Msk                            /*!<Semaphore CoreID.   */

+#define HSEM_R_LOCK_Pos           (31U)

+#define HSEM_R_LOCK_Msk           (0x1UL << HSEM_R_LOCK_Pos)                   /*!< 0x80000000 */

+#define HSEM_R_LOCK               HSEM_R_LOCK_Msk                              /*!<Lock indication.    */

+

+/********************  Bit definition for HSEM_RLR register  ******************/

+#define HSEM_RLR_PROCID_Pos       (0U)

+#define HSEM_RLR_PROCID_Msk       (0xFFUL << HSEM_RLR_PROCID_Pos)              /*!< 0x000000FF */

+#define HSEM_RLR_PROCID           HSEM_RLR_PROCID_Msk                          /*!<Semaphore ProcessID */

+#define HSEM_RLR_COREID_Pos       (8U)

+#define HSEM_RLR_COREID_Msk       (0xFFUL << HSEM_RLR_COREID_Pos)              /*!< 0x0000FF00 */

+#define HSEM_RLR_COREID           HSEM_RLR_COREID_Msk                          /*!<Semaphore CoreID.   */

+#define HSEM_RLR_LOCK_Pos         (31U)

+#define HSEM_RLR_LOCK_Msk         (0x1UL << HSEM_RLR_LOCK_Pos)                 /*!< 0x80000000 */

+#define HSEM_RLR_LOCK             HSEM_RLR_LOCK_Msk                            /*!<Lock indication.    */

+

+/********************  Bit definition for HSEM_C1IER register  *****************/

+#define HSEM_C1IER_ISE0_Pos       (0U)

+#define HSEM_C1IER_ISE0_Msk       (0x1UL << HSEM_C1IER_ISE0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1IER_ISE0           HSEM_C1IER_ISE0_Msk                          /*!<semaphore 0 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE1_Pos       (1U)

+#define HSEM_C1IER_ISE1_Msk       (0x1UL << HSEM_C1IER_ISE1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1IER_ISE1           HSEM_C1IER_ISE1_Msk                          /*!<semaphore 1 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE2_Pos       (2U)

+#define HSEM_C1IER_ISE2_Msk       (0x1UL << HSEM_C1IER_ISE2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1IER_ISE2           HSEM_C1IER_ISE2_Msk                          /*!<semaphore 2 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE3_Pos       (3U)

+#define HSEM_C1IER_ISE3_Msk       (0x1UL << HSEM_C1IER_ISE3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1IER_ISE3           HSEM_C1IER_ISE3_Msk                          /*!<semaphore 3 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE4_Pos       (4U)

+#define HSEM_C1IER_ISE4_Msk       (0x1UL << HSEM_C1IER_ISE4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1IER_ISE4           HSEM_C1IER_ISE4_Msk                          /*!<semaphore 4 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE5_Pos       (5U)

+#define HSEM_C1IER_ISE5_Msk       (0x1UL << HSEM_C1IER_ISE5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1IER_ISE5           HSEM_C1IER_ISE5_Msk                          /*!<semaphore 5 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE6_Pos       (6U)

+#define HSEM_C1IER_ISE6_Msk       (0x1UL << HSEM_C1IER_ISE6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1IER_ISE6           HSEM_C1IER_ISE6_Msk                          /*!<semaphore 6 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE7_Pos       (7U)

+#define HSEM_C1IER_ISE7_Msk       (0x1UL << HSEM_C1IER_ISE7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1IER_ISE7           HSEM_C1IER_ISE7_Msk                          /*!<semaphore 7 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE8_Pos       (8U)

+#define HSEM_C1IER_ISE8_Msk       (0x1UL << HSEM_C1IER_ISE8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1IER_ISE8           HSEM_C1IER_ISE8_Msk                          /*!<semaphore 8 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE9_Pos       (9U)

+#define HSEM_C1IER_ISE9_Msk       (0x1UL << HSEM_C1IER_ISE9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1IER_ISE9           HSEM_C1IER_ISE9_Msk                          /*!<semaphore 9 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE10_Pos      (10U)

+#define HSEM_C1IER_ISE10_Msk      (0x1UL << HSEM_C1IER_ISE10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1IER_ISE10          HSEM_C1IER_ISE10_Msk                         /*!<semaphore 10 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE11_Pos      (11U)

+#define HSEM_C1IER_ISE11_Msk      (0x1UL << HSEM_C1IER_ISE11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1IER_ISE11          HSEM_C1IER_ISE11_Msk                         /*!<semaphore 11 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE12_Pos      (12U)

+#define HSEM_C1IER_ISE12_Msk      (0x1UL << HSEM_C1IER_ISE12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1IER_ISE12          HSEM_C1IER_ISE12_Msk                         /*!<semaphore 12 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE13_Pos      (13U)

+#define HSEM_C1IER_ISE13_Msk      (0x1UL << HSEM_C1IER_ISE13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1IER_ISE13          HSEM_C1IER_ISE13_Msk                         /*!<semaphore 13 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE14_Pos      (14U)

+#define HSEM_C1IER_ISE14_Msk      (0x1UL << HSEM_C1IER_ISE14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1IER_ISE14          HSEM_C1IER_ISE14_Msk                         /*!<semaphore 14 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE15_Pos      (15U)

+#define HSEM_C1IER_ISE15_Msk      (0x1UL << HSEM_C1IER_ISE15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1IER_ISE15          HSEM_C1IER_ISE15_Msk                         /*!<semaphore 15 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE16_Pos      (16U)

+#define HSEM_C1IER_ISE16_Msk      (0x1UL << HSEM_C1IER_ISE16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1IER_ISE16          HSEM_C1IER_ISE16_Msk                         /*!<semaphore 16 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE17_Pos      (17U)

+#define HSEM_C1IER_ISE17_Msk      (0x1UL << HSEM_C1IER_ISE17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1IER_ISE17          HSEM_C1IER_ISE17_Msk                         /*!<semaphore 17 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE18_Pos      (18U)

+#define HSEM_C1IER_ISE18_Msk      (0x1UL << HSEM_C1IER_ISE18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1IER_ISE18          HSEM_C1IER_ISE18_Msk                         /*!<semaphore 18 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE19_Pos      (19U)

+#define HSEM_C1IER_ISE19_Msk      (0x1UL << HSEM_C1IER_ISE19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1IER_ISE19          HSEM_C1IER_ISE19_Msk                         /*!<semaphore 19 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE20_Pos      (20U)

+#define HSEM_C1IER_ISE20_Msk      (0x1UL << HSEM_C1IER_ISE20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1IER_ISE20          HSEM_C1IER_ISE20_Msk                         /*!<semaphore 20 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE21_Pos      (21U)

+#define HSEM_C1IER_ISE21_Msk      (0x1UL << HSEM_C1IER_ISE21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1IER_ISE21          HSEM_C1IER_ISE21_Msk                         /*!<semaphore 21 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE22_Pos      (22U)

+#define HSEM_C1IER_ISE22_Msk      (0x1UL << HSEM_C1IER_ISE22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1IER_ISE22          HSEM_C1IER_ISE22_Msk                         /*!<semaphore 22 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE23_Pos      (23U)

+#define HSEM_C1IER_ISE23_Msk      (0x1UL << HSEM_C1IER_ISE23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1IER_ISE23          HSEM_C1IER_ISE23_Msk                         /*!<semaphore 23 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE24_Pos      (24U)

+#define HSEM_C1IER_ISE24_Msk      (0x1UL << HSEM_C1IER_ISE24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1IER_ISE24          HSEM_C1IER_ISE24_Msk                         /*!<semaphore 24 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE25_Pos      (25U)

+#define HSEM_C1IER_ISE25_Msk      (0x1UL << HSEM_C1IER_ISE25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1IER_ISE25          HSEM_C1IER_ISE25_Msk                         /*!<semaphore 25 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE26_Pos      (26U)

+#define HSEM_C1IER_ISE26_Msk      (0x1UL << HSEM_C1IER_ISE26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1IER_ISE26          HSEM_C1IER_ISE26_Msk                         /*!<semaphore 26 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE27_Pos      (27U)

+#define HSEM_C1IER_ISE27_Msk      (0x1UL << HSEM_C1IER_ISE27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1IER_ISE27          HSEM_C1IER_ISE27_Msk                         /*!<semaphore 27 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE28_Pos      (28U)

+#define HSEM_C1IER_ISE28_Msk      (0x1UL << HSEM_C1IER_ISE28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1IER_ISE28          HSEM_C1IER_ISE28_Msk                         /*!<semaphore 28 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE29_Pos      (29U)

+#define HSEM_C1IER_ISE29_Msk      (0x1UL << HSEM_C1IER_ISE29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1IER_ISE29          HSEM_C1IER_ISE29_Msk                         /*!<semaphore 29 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE30_Pos      (30U)

+#define HSEM_C1IER_ISE30_Msk      (0x1UL << HSEM_C1IER_ISE30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1IER_ISE30          HSEM_C1IER_ISE30_Msk                         /*!<semaphore 30 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE31_Pos      (31U)

+#define HSEM_C1IER_ISE31_Msk      (0x1UL << HSEM_C1IER_ISE31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1IER_ISE31          HSEM_C1IER_ISE31_Msk                         /*!<semaphore 31 interrupt 0 enable bit. */

+

+/********************  Bit definition for HSEM_C1ICR register  *****************/

+#define HSEM_C1ICR_ISC0_Pos       (0U)

+#define HSEM_C1ICR_ISC0_Msk       (0x1UL << HSEM_C1ICR_ISC0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1ICR_ISC0           HSEM_C1ICR_ISC0_Msk                          /*!<semaphore 0 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC1_Pos       (1U)

+#define HSEM_C1ICR_ISC1_Msk       (0x1UL << HSEM_C1ICR_ISC1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1ICR_ISC1           HSEM_C1ICR_ISC1_Msk                          /*!<semaphore 1 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC2_Pos       (2U)

+#define HSEM_C1ICR_ISC2_Msk       (0x1UL << HSEM_C1ICR_ISC2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1ICR_ISC2           HSEM_C1ICR_ISC2_Msk                          /*!<semaphore 2 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC3_Pos       (3U)

+#define HSEM_C1ICR_ISC3_Msk       (0x1UL << HSEM_C1ICR_ISC3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1ICR_ISC3           HSEM_C1ICR_ISC3_Msk                          /*!<semaphore 3 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC4_Pos       (4U)

+#define HSEM_C1ICR_ISC4_Msk       (0x1UL << HSEM_C1ICR_ISC4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1ICR_ISC4           HSEM_C1ICR_ISC4_Msk                          /*!<semaphore 4 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC5_Pos       (5U)

+#define HSEM_C1ICR_ISC5_Msk       (0x1UL << HSEM_C1ICR_ISC5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1ICR_ISC5           HSEM_C1ICR_ISC5_Msk                          /*!<semaphore 5 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC6_Pos       (6U)

+#define HSEM_C1ICR_ISC6_Msk       (0x1UL << HSEM_C1ICR_ISC6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1ICR_ISC6           HSEM_C1ICR_ISC6_Msk                          /*!<semaphore 6 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC7_Pos       (7U)

+#define HSEM_C1ICR_ISC7_Msk       (0x1UL << HSEM_C1ICR_ISC7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1ICR_ISC7           HSEM_C1ICR_ISC7_Msk                          /*!<semaphore 7 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC8_Pos       (8U)

+#define HSEM_C1ICR_ISC8_Msk       (0x1UL << HSEM_C1ICR_ISC8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1ICR_ISC8           HSEM_C1ICR_ISC8_Msk                          /*!<semaphore 8 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC9_Pos       (9U)

+#define HSEM_C1ICR_ISC9_Msk       (0x1UL << HSEM_C1ICR_ISC9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1ICR_ISC9           HSEM_C1ICR_ISC9_Msk                          /*!<semaphore 9 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC10_Pos      (10U)

+#define HSEM_C1ICR_ISC10_Msk      (0x1UL << HSEM_C1ICR_ISC10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1ICR_ISC10          HSEM_C1ICR_ISC10_Msk                         /*!<semaphore 10 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC11_Pos      (11U)

+#define HSEM_C1ICR_ISC11_Msk      (0x1UL << HSEM_C1ICR_ISC11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1ICR_ISC11          HSEM_C1ICR_ISC11_Msk                         /*!<semaphore 11 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC12_Pos      (12U)

+#define HSEM_C1ICR_ISC12_Msk      (0x1UL << HSEM_C1ICR_ISC12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1ICR_ISC12          HSEM_C1ICR_ISC12_Msk                         /*!<semaphore 12 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC13_Pos      (13U)

+#define HSEM_C1ICR_ISC13_Msk      (0x1UL << HSEM_C1ICR_ISC13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1ICR_ISC13          HSEM_C1ICR_ISC13_Msk                         /*!<semaphore 13 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC14_Pos      (14U)

+#define HSEM_C1ICR_ISC14_Msk      (0x1UL << HSEM_C1ICR_ISC14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1ICR_ISC14          HSEM_C1ICR_ISC14_Msk                         /*!<semaphore 14 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC15_Pos      (15U)

+#define HSEM_C1ICR_ISC15_Msk      (0x1UL << HSEM_C1ICR_ISC15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1ICR_ISC15          HSEM_C1ICR_ISC15_Msk                         /*!<semaphore 15 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC16_Pos      (16U)

+#define HSEM_C1ICR_ISC16_Msk      (0x1UL << HSEM_C1ICR_ISC16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1ICR_ISC16          HSEM_C1ICR_ISC16_Msk                         /*!<semaphore 16 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC17_Pos      (17U)

+#define HSEM_C1ICR_ISC17_Msk      (0x1UL << HSEM_C1ICR_ISC17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1ICR_ISC17          HSEM_C1ICR_ISC17_Msk                         /*!<semaphore 17 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC18_Pos      (18U)

+#define HSEM_C1ICR_ISC18_Msk      (0x1UL << HSEM_C1ICR_ISC18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1ICR_ISC18          HSEM_C1ICR_ISC18_Msk                         /*!<semaphore 18 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC19_Pos      (19U)

+#define HSEM_C1ICR_ISC19_Msk      (0x1UL << HSEM_C1ICR_ISC19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1ICR_ISC19          HSEM_C1ICR_ISC19_Msk                         /*!<semaphore 19 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC20_Pos      (20U)

+#define HSEM_C1ICR_ISC20_Msk      (0x1UL << HSEM_C1ICR_ISC20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1ICR_ISC20          HSEM_C1ICR_ISC20_Msk                         /*!<semaphore 20 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC21_Pos      (21U)

+#define HSEM_C1ICR_ISC21_Msk      (0x1UL << HSEM_C1ICR_ISC21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1ICR_ISC21          HSEM_C1ICR_ISC21_Msk                         /*!<semaphore 21 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC22_Pos      (22U)

+#define HSEM_C1ICR_ISC22_Msk      (0x1UL << HSEM_C1ICR_ISC22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1ICR_ISC22          HSEM_C1ICR_ISC22_Msk                         /*!<semaphore 22 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC23_Pos      (23U)

+#define HSEM_C1ICR_ISC23_Msk      (0x1UL << HSEM_C1ICR_ISC23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1ICR_ISC23          HSEM_C1ICR_ISC23_Msk                         /*!<semaphore 23 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC24_Pos      (24U)

+#define HSEM_C1ICR_ISC24_Msk      (0x1UL << HSEM_C1ICR_ISC24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1ICR_ISC24          HSEM_C1ICR_ISC24_Msk                         /*!<semaphore 24 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC25_Pos      (25U)

+#define HSEM_C1ICR_ISC25_Msk      (0x1UL << HSEM_C1ICR_ISC25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1ICR_ISC25          HSEM_C1ICR_ISC25_Msk                         /*!<semaphore 25 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC26_Pos      (26U)

+#define HSEM_C1ICR_ISC26_Msk      (0x1UL << HSEM_C1ICR_ISC26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1ICR_ISC26          HSEM_C1ICR_ISC26_Msk                         /*!<semaphore 26 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC27_Pos      (27U)

+#define HSEM_C1ICR_ISC27_Msk      (0x1UL << HSEM_C1ICR_ISC27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1ICR_ISC27          HSEM_C1ICR_ISC27_Msk                         /*!<semaphore 27 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC28_Pos      (28U)

+#define HSEM_C1ICR_ISC28_Msk      (0x1UL << HSEM_C1ICR_ISC28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1ICR_ISC28          HSEM_C1ICR_ISC28_Msk                         /*!<semaphore 28 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC29_Pos      (29U)

+#define HSEM_C1ICR_ISC29_Msk      (0x1UL << HSEM_C1ICR_ISC29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1ICR_ISC29          HSEM_C1ICR_ISC29_Msk                         /*!<semaphore 29 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC30_Pos      (30U)

+#define HSEM_C1ICR_ISC30_Msk      (0x1UL << HSEM_C1ICR_ISC30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1ICR_ISC30          HSEM_C1ICR_ISC30_Msk                         /*!<semaphore 30 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC31_Pos      (31U)

+#define HSEM_C1ICR_ISC31_Msk      (0x1UL << HSEM_C1ICR_ISC31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1ICR_ISC31          HSEM_C1ICR_ISC31_Msk                         /*!<semaphore 31 interrupt 0 clear bit. */

+

+/********************  Bit definition for HSEM_C1ISR register  *****************/

+#define HSEM_C1ISR_ISF0_Pos       (0U)

+#define HSEM_C1ISR_ISF0_Msk       (0x1UL << HSEM_C1ISR_ISF0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1ISR_ISF0           HSEM_C1ISR_ISF0_Msk                          /*!<semaphore 0 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF1_Pos       (1U)

+#define HSEM_C1ISR_ISF1_Msk       (0x1UL << HSEM_C1ISR_ISF1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1ISR_ISF1           HSEM_C1ISR_ISF1_Msk                          /*!<semaphore 1 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF2_Pos       (2U)

+#define HSEM_C1ISR_ISF2_Msk       (0x1UL << HSEM_C1ISR_ISF2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1ISR_ISF2           HSEM_C1ISR_ISF2_Msk                          /*!<semaphore 2 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF3_Pos       (3U)

+#define HSEM_C1ISR_ISF3_Msk       (0x1UL << HSEM_C1ISR_ISF3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1ISR_ISF3           HSEM_C1ISR_ISF3_Msk                          /*!<semaphore 3 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF4_Pos       (4U)

+#define HSEM_C1ISR_ISF4_Msk       (0x1UL << HSEM_C1ISR_ISF4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1ISR_ISF4           HSEM_C1ISR_ISF4_Msk                          /*!<semaphore 4 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF5_Pos       (5U)

+#define HSEM_C1ISR_ISF5_Msk       (0x1UL << HSEM_C1ISR_ISF5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1ISR_ISF5           HSEM_C1ISR_ISF5_Msk                          /*!<semaphore 5 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF6_Pos       (6U)

+#define HSEM_C1ISR_ISF6_Msk       (0x1UL << HSEM_C1ISR_ISF6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1ISR_ISF6           HSEM_C1ISR_ISF6_Msk                          /*!<semaphore 6 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF7_Pos       (7U)

+#define HSEM_C1ISR_ISF7_Msk       (0x1UL << HSEM_C1ISR_ISF7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1ISR_ISF7           HSEM_C1ISR_ISF7_Msk                          /*!<semaphore 7 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF8_Pos       (8U)

+#define HSEM_C1ISR_ISF8_Msk       (0x1UL << HSEM_C1ISR_ISF8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1ISR_ISF8           HSEM_C1ISR_ISF8_Msk                          /*!<semaphore 8 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF9_Pos       (9U)

+#define HSEM_C1ISR_ISF9_Msk       (0x1UL << HSEM_C1ISR_ISF9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1ISR_ISF9           HSEM_C1ISR_ISF9_Msk                          /*!<semaphore 9 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF10_Pos      (10U)

+#define HSEM_C1ISR_ISF10_Msk      (0x1UL << HSEM_C1ISR_ISF10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1ISR_ISF10          HSEM_C1ISR_ISF10_Msk                         /*!<semaphore 10 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF11_Pos      (11U)

+#define HSEM_C1ISR_ISF11_Msk      (0x1UL << HSEM_C1ISR_ISF11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1ISR_ISF11          HSEM_C1ISR_ISF11_Msk                         /*!<semaphore 11 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF12_Pos      (12U)

+#define HSEM_C1ISR_ISF12_Msk      (0x1UL << HSEM_C1ISR_ISF12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1ISR_ISF12          HSEM_C1ISR_ISF12_Msk                         /*!<semaphore 12 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF13_Pos      (13U)

+#define HSEM_C1ISR_ISF13_Msk      (0x1UL << HSEM_C1ISR_ISF13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1ISR_ISF13          HSEM_C1ISR_ISF13_Msk                         /*!<semaphore 13 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF14_Pos      (14U)

+#define HSEM_C1ISR_ISF14_Msk      (0x1UL << HSEM_C1ISR_ISF14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1ISR_ISF14          HSEM_C1ISR_ISF14_Msk                         /*!<semaphore 14 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF15_Pos      (15U)

+#define HSEM_C1ISR_ISF15_Msk      (0x1UL << HSEM_C1ISR_ISF15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1ISR_ISF15          HSEM_C1ISR_ISF15_Msk                         /*!<semaphore 15 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF16_Pos      (16U)

+#define HSEM_C1ISR_ISF16_Msk      (0x1UL << HSEM_C1ISR_ISF16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1ISR_ISF16          HSEM_C1ISR_ISF16_Msk                         /*!<semaphore 16 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF17_Pos      (17U)

+#define HSEM_C1ISR_ISF17_Msk      (0x1UL << HSEM_C1ISR_ISF17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1ISR_ISF17          HSEM_C1ISR_ISF17_Msk                         /*!<semaphore 17 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF18_Pos      (18U)

+#define HSEM_C1ISR_ISF18_Msk      (0x1UL << HSEM_C1ISR_ISF18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1ISR_ISF18          HSEM_C1ISR_ISF18_Msk                         /*!<semaphore 18 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF19_Pos      (19U)

+#define HSEM_C1ISR_ISF19_Msk      (0x1UL << HSEM_C1ISR_ISF19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1ISR_ISF19          HSEM_C1ISR_ISF19_Msk                         /*!<semaphore 19 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF20_Pos      (20U)

+#define HSEM_C1ISR_ISF20_Msk      (0x1UL << HSEM_C1ISR_ISF20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1ISR_ISF20          HSEM_C1ISR_ISF20_Msk                         /*!<semaphore 20 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF21_Pos      (21U)

+#define HSEM_C1ISR_ISF21_Msk      (0x1UL << HSEM_C1ISR_ISF21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1ISR_ISF21          HSEM_C1ISR_ISF21_Msk                         /*!<semaphore 21 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF22_Pos      (22U)

+#define HSEM_C1ISR_ISF22_Msk      (0x1UL << HSEM_C1ISR_ISF22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1ISR_ISF22          HSEM_C1ISR_ISF22_Msk                         /*!<semaphore 22 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF23_Pos      (23U)

+#define HSEM_C1ISR_ISF23_Msk      (0x1UL << HSEM_C1ISR_ISF23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1ISR_ISF23          HSEM_C1ISR_ISF23_Msk                         /*!<semaphore 23 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF24_Pos      (24U)

+#define HSEM_C1ISR_ISF24_Msk      (0x1UL << HSEM_C1ISR_ISF24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1ISR_ISF24          HSEM_C1ISR_ISF24_Msk                         /*!<semaphore 24 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF25_Pos      (25U)

+#define HSEM_C1ISR_ISF25_Msk      (0x1UL << HSEM_C1ISR_ISF25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1ISR_ISF25          HSEM_C1ISR_ISF25_Msk                         /*!<semaphore 25 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF26_Pos      (26U)

+#define HSEM_C1ISR_ISF26_Msk      (0x1UL << HSEM_C1ISR_ISF26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1ISR_ISF26          HSEM_C1ISR_ISF26_Msk                         /*!<semaphore 26 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF27_Pos      (27U)

+#define HSEM_C1ISR_ISF27_Msk      (0x1UL << HSEM_C1ISR_ISF27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1ISR_ISF27          HSEM_C1ISR_ISF27_Msk                         /*!<semaphore 27 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF28_Pos      (28U)

+#define HSEM_C1ISR_ISF28_Msk      (0x1UL << HSEM_C1ISR_ISF28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1ISR_ISF28          HSEM_C1ISR_ISF28_Msk                         /*!<semaphore 28 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF29_Pos      (29U)

+#define HSEM_C1ISR_ISF29_Msk      (0x1UL << HSEM_C1ISR_ISF29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1ISR_ISF29          HSEM_C1ISR_ISF29_Msk                         /*!<semaphore 29 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF30_Pos      (30U)

+#define HSEM_C1ISR_ISF30_Msk      (0x1UL << HSEM_C1ISR_ISF30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1ISR_ISF30          HSEM_C1ISR_ISF30_Msk                         /*!<semaphore 30 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF31_Pos      (31U)

+#define HSEM_C1ISR_ISF31_Msk      (0x1UL << HSEM_C1ISR_ISF31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1ISR_ISF31          HSEM_C1ISR_ISF31_Msk                         /*!<semaphore 31 interrupt 0 status bit. */

+

+/********************  Bit definition for HSEM_C1MISR register  *****************/

+#define HSEM_C1MISR_MISF0_Pos     (0U)

+#define HSEM_C1MISR_MISF0_Msk     (0x1UL << HSEM_C1MISR_MISF0_Pos)             /*!< 0x00000001 */

+#define HSEM_C1MISR_MISF0         HSEM_C1MISR_MISF0_Msk                        /*!<semaphore 0 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF1_Pos     (1U)

+#define HSEM_C1MISR_MISF1_Msk     (0x1UL << HSEM_C1MISR_MISF1_Pos)             /*!< 0x00000002 */

+#define HSEM_C1MISR_MISF1         HSEM_C1MISR_MISF1_Msk                        /*!<semaphore 1 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF2_Pos     (2U)

+#define HSEM_C1MISR_MISF2_Msk     (0x1UL << HSEM_C1MISR_MISF2_Pos)             /*!< 0x00000004 */

+#define HSEM_C1MISR_MISF2         HSEM_C1MISR_MISF2_Msk                        /*!<semaphore 2 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF3_Pos     (3U)

+#define HSEM_C1MISR_MISF3_Msk     (0x1UL << HSEM_C1MISR_MISF3_Pos)             /*!< 0x00000008 */

+#define HSEM_C1MISR_MISF3         HSEM_C1MISR_MISF3_Msk                        /*!<semaphore 3 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF4_Pos     (4U)

+#define HSEM_C1MISR_MISF4_Msk     (0x1UL << HSEM_C1MISR_MISF4_Pos)             /*!< 0x00000010 */

+#define HSEM_C1MISR_MISF4         HSEM_C1MISR_MISF4_Msk                        /*!<semaphore 4 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF5_Pos     (5U)

+#define HSEM_C1MISR_MISF5_Msk     (0x1UL << HSEM_C1MISR_MISF5_Pos)             /*!< 0x00000020 */

+#define HSEM_C1MISR_MISF5         HSEM_C1MISR_MISF5_Msk                        /*!<semaphore 5 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF6_Pos     (6U)

+#define HSEM_C1MISR_MISF6_Msk     (0x1UL << HSEM_C1MISR_MISF6_Pos)             /*!< 0x00000040 */

+#define HSEM_C1MISR_MISF6         HSEM_C1MISR_MISF6_Msk                        /*!<semaphore 6 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF7_Pos     (7U)

+#define HSEM_C1MISR_MISF7_Msk     (0x1UL << HSEM_C1MISR_MISF7_Pos)             /*!< 0x00000080 */

+#define HSEM_C1MISR_MISF7         HSEM_C1MISR_MISF7_Msk                        /*!<semaphore 7 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF8_Pos     (8U)

+#define HSEM_C1MISR_MISF8_Msk     (0x1UL << HSEM_C1MISR_MISF8_Pos)             /*!< 0x00000100 */

+#define HSEM_C1MISR_MISF8         HSEM_C1MISR_MISF8_Msk                        /*!<semaphore 8 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF9_Pos     (9U)

+#define HSEM_C1MISR_MISF9_Msk     (0x1UL << HSEM_C1MISR_MISF9_Pos)             /*!< 0x00000200 */

+#define HSEM_C1MISR_MISF9         HSEM_C1MISR_MISF9_Msk                        /*!<semaphore 9 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF10_Pos    (10U)

+#define HSEM_C1MISR_MISF10_Msk    (0x1UL << HSEM_C1MISR_MISF10_Pos)            /*!< 0x00000400 */

+#define HSEM_C1MISR_MISF10        HSEM_C1MISR_MISF10_Msk                       /*!<semaphore 10 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF11_Pos    (11U)

+#define HSEM_C1MISR_MISF11_Msk    (0x1UL << HSEM_C1MISR_MISF11_Pos)            /*!< 0x00000800 */

+#define HSEM_C1MISR_MISF11        HSEM_C1MISR_MISF11_Msk                       /*!<semaphore 11 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF12_Pos    (12U)

+#define HSEM_C1MISR_MISF12_Msk    (0x1UL << HSEM_C1MISR_MISF12_Pos)            /*!< 0x00001000 */

+#define HSEM_C1MISR_MISF12        HSEM_C1MISR_MISF12_Msk                       /*!<semaphore 12 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF13_Pos    (13U)

+#define HSEM_C1MISR_MISF13_Msk    (0x1UL << HSEM_C1MISR_MISF13_Pos)            /*!< 0x00002000 */

+#define HSEM_C1MISR_MISF13        HSEM_C1MISR_MISF13_Msk                       /*!<semaphore 13 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF14_Pos    (14U)

+#define HSEM_C1MISR_MISF14_Msk    (0x1UL << HSEM_C1MISR_MISF14_Pos)            /*!< 0x00004000 */

+#define HSEM_C1MISR_MISF14        HSEM_C1MISR_MISF14_Msk                       /*!<semaphore 14 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF15_Pos    (15U)

+#define HSEM_C1MISR_MISF15_Msk    (0x1UL << HSEM_C1MISR_MISF15_Pos)            /*!< 0x00008000 */

+#define HSEM_C1MISR_MISF15        HSEM_C1MISR_MISF15_Msk                       /*!<semaphore 15 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF16_Pos    (16U)

+#define HSEM_C1MISR_MISF16_Msk    (0x1UL << HSEM_C1MISR_MISF16_Pos)            /*!< 0x00010000 */

+#define HSEM_C1MISR_MISF16        HSEM_C1MISR_MISF16_Msk                       /*!<semaphore 16 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF17_Pos    (17U)

+#define HSEM_C1MISR_MISF17_Msk    (0x1UL << HSEM_C1MISR_MISF17_Pos)            /*!< 0x00020000 */

+#define HSEM_C1MISR_MISF17        HSEM_C1MISR_MISF17_Msk                       /*!<semaphore 17 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF18_Pos    (18U)

+#define HSEM_C1MISR_MISF18_Msk    (0x1UL << HSEM_C1MISR_MISF18_Pos)            /*!< 0x00040000 */

+#define HSEM_C1MISR_MISF18        HSEM_C1MISR_MISF18_Msk                       /*!<semaphore 18 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF19_Pos    (19U)

+#define HSEM_C1MISR_MISF19_Msk    (0x1UL << HSEM_C1MISR_MISF19_Pos)            /*!< 0x00080000 */

+#define HSEM_C1MISR_MISF19        HSEM_C1MISR_MISF19_Msk                       /*!<semaphore 19 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF20_Pos    (20U)

+#define HSEM_C1MISR_MISF20_Msk    (0x1UL << HSEM_C1MISR_MISF20_Pos)            /*!< 0x00100000 */

+#define HSEM_C1MISR_MISF20        HSEM_C1MISR_MISF20_Msk                       /*!<semaphore 20 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF21_Pos    (21U)

+#define HSEM_C1MISR_MISF21_Msk    (0x1UL << HSEM_C1MISR_MISF21_Pos)            /*!< 0x00200000 */

+#define HSEM_C1MISR_MISF21        HSEM_C1MISR_MISF21_Msk                       /*!<semaphore 21 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF22_Pos    (22U)

+#define HSEM_C1MISR_MISF22_Msk    (0x1UL << HSEM_C1MISR_MISF22_Pos)            /*!< 0x00400000 */

+#define HSEM_C1MISR_MISF22        HSEM_C1MISR_MISF22_Msk                       /*!<semaphore 22 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF23_Pos    (23U)

+#define HSEM_C1MISR_MISF23_Msk    (0x1UL << HSEM_C1MISR_MISF23_Pos)            /*!< 0x00800000 */

+#define HSEM_C1MISR_MISF23        HSEM_C1MISR_MISF23_Msk                       /*!<semaphore 23 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF24_Pos    (24U)

+#define HSEM_C1MISR_MISF24_Msk    (0x1UL << HSEM_C1MISR_MISF24_Pos)            /*!< 0x01000000 */

+#define HSEM_C1MISR_MISF24        HSEM_C1MISR_MISF24_Msk                       /*!<semaphore 24 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF25_Pos    (25U)

+#define HSEM_C1MISR_MISF25_Msk    (0x1UL << HSEM_C1MISR_MISF25_Pos)            /*!< 0x02000000 */

+#define HSEM_C1MISR_MISF25        HSEM_C1MISR_MISF25_Msk                       /*!<semaphore 25 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF26_Pos    (26U)

+#define HSEM_C1MISR_MISF26_Msk    (0x1UL << HSEM_C1MISR_MISF26_Pos)            /*!< 0x04000000 */

+#define HSEM_C1MISR_MISF26        HSEM_C1MISR_MISF26_Msk                       /*!<semaphore 26 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF27_Pos    (27U)

+#define HSEM_C1MISR_MISF27_Msk    (0x1UL << HSEM_C1MISR_MISF27_Pos)            /*!< 0x08000000 */

+#define HSEM_C1MISR_MISF27        HSEM_C1MISR_MISF27_Msk                       /*!<semaphore 27 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF28_Pos    (28U)

+#define HSEM_C1MISR_MISF28_Msk    (0x1UL << HSEM_C1MISR_MISF28_Pos)            /*!< 0x10000000 */

+#define HSEM_C1MISR_MISF28        HSEM_C1MISR_MISF28_Msk                       /*!<semaphore 28 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF29_Pos    (29U)

+#define HSEM_C1MISR_MISF29_Msk    (0x1UL << HSEM_C1MISR_MISF29_Pos)            /*!< 0x20000000 */

+#define HSEM_C1MISR_MISF29        HSEM_C1MISR_MISF29_Msk                       /*!<semaphore 29 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF30_Pos    (30U)

+#define HSEM_C1MISR_MISF30_Msk    (0x1UL << HSEM_C1MISR_MISF30_Pos)            /*!< 0x40000000 */

+#define HSEM_C1MISR_MISF30        HSEM_C1MISR_MISF30_Msk                       /*!<semaphore 30 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF31_Pos    (31U)

+#define HSEM_C1MISR_MISF31_Msk    (0x1UL << HSEM_C1MISR_MISF31_Pos)            /*!< 0x80000000 */

+#define HSEM_C1MISR_MISF31        HSEM_C1MISR_MISF31_Msk                       /*!<semaphore 31 interrupt 0 masked status bit. */

+

+/********************  Bit definition for HSEM_CR register  *****************/

+#define HSEM_CR_COREID_Pos        (8U)

+#define HSEM_CR_COREID_Msk        (0xFFUL << HSEM_CR_COREID_Pos)               /*!< 0x0000FF00 */

+#define HSEM_CR_COREID            HSEM_CR_COREID_Msk                           /*!<CoreID of semaphores to be cleared. */

+#define HSEM_CR_KEY_Pos           (16U)

+#define HSEM_CR_KEY_Msk           (0xFFFFUL << HSEM_CR_KEY_Pos)                /*!< 0xFFFF0000 */

+#define HSEM_CR_KEY               HSEM_CR_KEY_Msk                              /*!<semaphores clear key. */

+

+/********************  Bit definition for HSEM_KEYR register  *****************/

+#define HSEM_KEYR_KEY_Pos         (16U)

+#define HSEM_KEYR_KEY_Msk         (0xFFFFUL << HSEM_KEYR_KEY_Pos)              /*!< 0xFFFF0000 */

+#define HSEM_KEYR_KEY             HSEM_KEYR_KEY_Msk                            /*!<semaphores clear key. */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      Inter-integrated Circuit Interface (I2C)              */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for I2C_CR1 register  *******************/

+#define I2C_CR1_PE_Pos               (0U)

+#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */

+#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */

+#define I2C_CR1_TXIE_Pos             (1U)

+#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */

+#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */

+#define I2C_CR1_RXIE_Pos             (2U)

+#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */

+#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */

+#define I2C_CR1_ADDRIE_Pos           (3U)

+#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */

+#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */

+#define I2C_CR1_NACKIE_Pos           (4U)

+#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */

+#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */

+#define I2C_CR1_STOPIE_Pos           (5U)

+#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */

+#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */

+#define I2C_CR1_TCIE_Pos             (6U)

+#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */

+#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */

+#define I2C_CR1_ERRIE_Pos            (7U)

+#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */

+#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */

+#define I2C_CR1_DNF_Pos              (8U)

+#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */

+#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */

+#define I2C_CR1_ANFOFF_Pos           (12U)

+#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */

+#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */

+#define I2C_CR1_TXDMAEN_Pos          (14U)

+#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */

+#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */

+#define I2C_CR1_RXDMAEN_Pos          (15U)

+#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */

+#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */

+#define I2C_CR1_SBC_Pos              (16U)

+#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */

+#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */

+#define I2C_CR1_NOSTRETCH_Pos        (17U)

+#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */

+#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */

+#define I2C_CR1_WUPEN_Pos            (18U)

+#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */

+#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */

+#define I2C_CR1_GCEN_Pos             (19U)

+#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */

+#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */

+#define I2C_CR1_SMBHEN_Pos           (20U)

+#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */

+#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */

+#define I2C_CR1_SMBDEN_Pos           (21U)

+#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */

+#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */

+#define I2C_CR1_ALERTEN_Pos          (22U)

+#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */

+#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */

+#define I2C_CR1_PECEN_Pos            (23U)

+#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */

+#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */

+

+/******************  Bit definition for I2C_CR2 register  ********************/

+#define I2C_CR2_SADD_Pos             (0U)

+#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */

+#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */

+#define I2C_CR2_RD_WRN_Pos           (10U)

+#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */

+#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */

+#define I2C_CR2_ADD10_Pos            (11U)

+#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */

+#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */

+#define I2C_CR2_HEAD10R_Pos          (12U)

+#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */

+#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */

+#define I2C_CR2_START_Pos            (13U)

+#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */

+#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */

+#define I2C_CR2_STOP_Pos             (14U)

+#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */

+#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */

+#define I2C_CR2_NACK_Pos             (15U)

+#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */

+#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */

+#define I2C_CR2_NBYTES_Pos           (16U)

+#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */

+#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */

+#define I2C_CR2_RELOAD_Pos           (24U)

+#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */

+#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */

+#define I2C_CR2_AUTOEND_Pos          (25U)

+#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */

+#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */

+#define I2C_CR2_PECBYTE_Pos          (26U)

+#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */

+#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */

+

+/*******************  Bit definition for I2C_OAR1 register  ******************/

+#define I2C_OAR1_OA1_Pos             (0U)

+#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */

+#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */

+#define I2C_OAR1_OA1MODE_Pos         (10U)

+#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */

+#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */

+#define I2C_OAR1_OA1EN_Pos           (15U)

+#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */

+#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */

+

+/*******************  Bit definition for I2C_OAR2 register  ******************/

+#define I2C_OAR2_OA2_Pos             (1U)

+#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */

+#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */

+#define I2C_OAR2_OA2MSK_Pos          (8U)

+#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */

+#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */

+#define I2C_OAR2_OA2NOMASK           0x00000000UL                              /*!< No mask */

+#define I2C_OAR2_OA2MASK01_Pos       (8U)

+#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */

+#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared */

+#define I2C_OAR2_OA2MASK02_Pos       (9U)

+#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */

+#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */

+#define I2C_OAR2_OA2MASK03_Pos       (8U)

+#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */

+#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */

+#define I2C_OAR2_OA2MASK04_Pos       (10U)

+#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */

+#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */

+#define I2C_OAR2_OA2MASK05_Pos       (8U)

+#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */

+#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */

+#define I2C_OAR2_OA2MASK06_Pos       (9U)

+#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */

+#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared */

+#define I2C_OAR2_OA2MASK07_Pos       (8U)

+#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */

+#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done */

+#define I2C_OAR2_OA2EN_Pos           (15U)

+#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */

+#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */

+

+/*******************  Bit definition for I2C_TIMINGR register *******************/

+#define I2C_TIMINGR_SCLL_Pos         (0U)

+#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */

+#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */

+#define I2C_TIMINGR_SCLH_Pos         (8U)

+#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */

+#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */

+#define I2C_TIMINGR_SDADEL_Pos       (16U)

+#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */

+#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */

+#define I2C_TIMINGR_SCLDEL_Pos       (20U)

+#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */

+#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */

+#define I2C_TIMINGR_PRESC_Pos        (28U)

+#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */

+#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */

+

+/******************* Bit definition for I2C_TIMEOUTR register *******************/

+#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)

+#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */

+#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */

+#define I2C_TIMEOUTR_TIDLE_Pos       (12U)

+#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */

+#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */

+#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)

+#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */

+#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */

+#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)

+#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */

+#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/

+#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)

+#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */

+#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */

+

+/******************  Bit definition for I2C_ISR register  *********************/

+#define I2C_ISR_TXE_Pos              (0U)

+#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */

+#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */

+#define I2C_ISR_TXIS_Pos             (1U)

+#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */

+#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */

+#define I2C_ISR_RXNE_Pos             (2U)

+#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */

+#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */

+#define I2C_ISR_ADDR_Pos             (3U)

+#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */

+#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/

+#define I2C_ISR_NACKF_Pos            (4U)

+#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */

+#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */

+#define I2C_ISR_STOPF_Pos            (5U)

+#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */

+#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */

+#define I2C_ISR_TC_Pos               (6U)

+#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */

+#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */

+#define I2C_ISR_TCR_Pos              (7U)

+#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */

+#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */

+#define I2C_ISR_BERR_Pos             (8U)

+#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */

+#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */

+#define I2C_ISR_ARLO_Pos             (9U)

+#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */

+#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */

+#define I2C_ISR_OVR_Pos              (10U)

+#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */

+#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */

+#define I2C_ISR_PECERR_Pos           (11U)

+#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */

+#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */

+#define I2C_ISR_TIMEOUT_Pos          (12U)

+#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */

+#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */

+#define I2C_ISR_ALERT_Pos            (13U)

+#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */

+#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */

+#define I2C_ISR_BUSY_Pos             (15U)

+#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */

+#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */

+#define I2C_ISR_DIR_Pos              (16U)

+#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */

+#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */

+#define I2C_ISR_ADDCODE_Pos          (17U)

+#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */

+#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */

+

+/******************  Bit definition for I2C_ICR register  *********************/

+#define I2C_ICR_ADDRCF_Pos           (3U)

+#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */

+#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */

+#define I2C_ICR_NACKCF_Pos           (4U)

+#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */

+#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */

+#define I2C_ICR_STOPCF_Pos           (5U)

+#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */

+#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */

+#define I2C_ICR_BERRCF_Pos           (8U)

+#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */

+#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */

+#define I2C_ICR_ARLOCF_Pos           (9U)

+#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */

+#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */

+#define I2C_ICR_OVRCF_Pos            (10U)

+#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */

+#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */

+#define I2C_ICR_PECCF_Pos            (11U)

+#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */

+#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */

+#define I2C_ICR_TIMOUTCF_Pos         (12U)

+#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */

+#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */

+#define I2C_ICR_ALERTCF_Pos          (13U)

+#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */

+#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */

+

+/******************  Bit definition for I2C_PECR register  *********************/

+#define I2C_PECR_PEC_Pos             (0U)

+#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */

+#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */

+

+/******************  Bit definition for I2C_RXDR register  *********************/

+#define I2C_RXDR_RXDATA_Pos          (0U)

+#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */

+#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */

+

+/******************  Bit definition for I2C_TXDR register  *********************/

+#define I2C_TXDR_TXDATA_Pos          (0U)

+#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */

+#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           Independent WATCHDOG                             */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for IWDG_KR register  ********************/

+#define IWDG_KR_KEY_Pos      (0U)

+#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */

+#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */

+

+/*******************  Bit definition for IWDG_PR register  ********************/

+#define IWDG_PR_PR_Pos       (0U)

+#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */

+#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */

+#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */

+#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */

+#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */

+

+/*******************  Bit definition for IWDG_RLR register  *******************/

+#define IWDG_RLR_RL_Pos      (0U)

+#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */

+#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */

+

+/*******************  Bit definition for IWDG_SR register  ********************/

+#define IWDG_SR_PVU_Pos      (0U)

+#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */

+#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */

+#define IWDG_SR_RVU_Pos      (1U)

+#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */

+#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */

+#define IWDG_SR_WVU_Pos      (2U)

+#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */

+#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */

+

+/*******************  Bit definition for IWDG_KR register  ********************/

+#define IWDG_WINR_WIN_Pos    (0U)

+#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */

+#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */

+

+/******************************************************************************/

+/*                                                                            */

+/*                        JPEG Encoder/Decoder                                */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for CONFR0 register  ********************/

+#define JPEG_CONFR0_START_Pos           (0U)

+#define JPEG_CONFR0_START_Msk           (0x1UL << JPEG_CONFR0_START_Pos)       /*!< 0x00000001 */

+#define JPEG_CONFR0_START               JPEG_CONFR0_START_Msk                  /*!<Start/Stop bit */

+

+/********************  Bit definition for CONFR1 register  ********************/

+#define JPEG_CONFR1_NF_Pos              (0U)

+#define JPEG_CONFR1_NF_Msk              (0x3UL << JPEG_CONFR1_NF_Pos)          /*!< 0x00000003 */

+#define JPEG_CONFR1_NF                  JPEG_CONFR1_NF_Msk                     /*!<Number of color components */

+#define JPEG_CONFR1_NF_0                (0x1UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000001 */

+#define JPEG_CONFR1_NF_1                (0x2UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000002 */

+#define JPEG_CONFR1_DE_Pos              (3U)

+#define JPEG_CONFR1_DE_Msk              (0x1UL << JPEG_CONFR1_DE_Pos)          /*!< 0x00000008 */

+#define JPEG_CONFR1_DE                  JPEG_CONFR1_DE_Msk                     /*!<Decoding Enable */

+#define JPEG_CONFR1_COLORSPACE_Pos      (4U)

+#define JPEG_CONFR1_COLORSPACE_Msk      (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)  /*!< 0x00000030 */

+#define JPEG_CONFR1_COLORSPACE          JPEG_CONFR1_COLORSPACE_Msk             /*!<Color Space */

+#define JPEG_CONFR1_COLORSPACE_0        (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000010 */

+#define JPEG_CONFR1_COLORSPACE_1        (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000020 */

+#define JPEG_CONFR1_NS_Pos              (6U)

+#define JPEG_CONFR1_NS_Msk              (0x3UL << JPEG_CONFR1_NS_Pos)          /*!< 0x000000C0 */

+#define JPEG_CONFR1_NS                  JPEG_CONFR1_NS_Msk                     /*!<Number of components for Scan */

+#define JPEG_CONFR1_NS_0                (0x1UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR1_NS_1                (0x2UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR1_HDR_Pos             (8U)

+#define JPEG_CONFR1_HDR_Msk             (0x1UL << JPEG_CONFR1_HDR_Pos)         /*!< 0x00000100 */

+#define JPEG_CONFR1_HDR                 JPEG_CONFR1_HDR_Msk                    /*!<Header Processing On/Off */

+#define JPEG_CONFR1_YSIZE_Pos           (16U)

+#define JPEG_CONFR1_YSIZE_Msk           (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)    /*!< 0xFFFF0000 */

+#define JPEG_CONFR1_YSIZE               JPEG_CONFR1_YSIZE_Msk                  /*!<Number of lines in source image */

+

+/********************  Bit definition for CONFR2 register  ********************/

+#define JPEG_CONFR2_NMCU_Pos            (0U)

+#define JPEG_CONFR2_NMCU_Msk            (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)  /*!< 0x03FFFFFF */

+#define JPEG_CONFR2_NMCU                JPEG_CONFR2_NMCU_Msk                   /*!<Number of MCU units minus 1 to encode */

+

+/********************  Bit definition for CONFR3 register  ********************/

+#define JPEG_CONFR3_XSIZE_Pos           (16U)

+#define JPEG_CONFR3_XSIZE_Msk           (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)    /*!< 0xFFFF0000 */

+#define JPEG_CONFR3_XSIZE               JPEG_CONFR3_XSIZE_Msk                  /*!<Number of pixels per line */

+

+/********************  Bit definition for CONFR4 register  ********************/

+#define JPEG_CONFR4_HD_Pos              (0U)

+#define JPEG_CONFR4_HD_Msk              (0x1UL << JPEG_CONFR4_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR4_HD                  JPEG_CONFR4_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR4_HA_Pos              (1U)

+#define JPEG_CONFR4_HA_Msk              (0x1UL << JPEG_CONFR4_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR4_HA                  JPEG_CONFR4_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR4_QT_Pos              (2U)

+#define JPEG_CONFR4_QT_Msk              (0x3UL << JPEG_CONFR4_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR4_QT                  JPEG_CONFR4_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR4_QT_0                (0x1UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR4_QT_1                (0x2UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR4_NB_Pos              (4U)

+#define JPEG_CONFR4_NB_Msk              (0xFUL << JPEG_CONFR4_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR4_NB                  JPEG_CONFR4_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR4_NB_0                (0x1UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR4_NB_1                (0x2UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR4_NB_2                (0x4UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR4_NB_3                (0x8UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR4_VSF_Pos             (8U)

+#define JPEG_CONFR4_VSF_Msk             (0xFUL << JPEG_CONFR4_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR4_VSF                 JPEG_CONFR4_VSF_Msk                    /*!<Vertical sampling factor for component 1 */

+#define JPEG_CONFR4_VSF_0               (0x1UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR4_VSF_1               (0x2UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR4_VSF_2               (0x4UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR4_VSF_3               (0x8UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR4_HSF_Pos             (12U)

+#define JPEG_CONFR4_HSF_Msk             (0xFUL << JPEG_CONFR4_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR4_HSF                 JPEG_CONFR4_HSF_Msk                    /*!<Horizontal sampling factor for component 1 */

+#define JPEG_CONFR4_HSF_0               (0x1UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR4_HSF_1               (0x2UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR4_HSF_2               (0x4UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR4_HSF_3               (0x8UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR5 register  ********************/

+#define JPEG_CONFR5_HD_Pos              (0U)

+#define JPEG_CONFR5_HD_Msk              (0x1UL << JPEG_CONFR5_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR5_HD                  JPEG_CONFR5_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR5_HA_Pos              (1U)

+#define JPEG_CONFR5_HA_Msk              (0x1UL << JPEG_CONFR5_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR5_HA                  JPEG_CONFR5_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR5_QT_Pos              (2U)

+#define JPEG_CONFR5_QT_Msk              (0x3UL << JPEG_CONFR5_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR5_QT                  JPEG_CONFR5_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR5_QT_0                (0x1UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR5_QT_1                (0x2UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR5_NB_Pos              (4U)

+#define JPEG_CONFR5_NB_Msk              (0xFUL << JPEG_CONFR5_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR5_NB                  JPEG_CONFR5_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR5_NB_0                (0x1UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR5_NB_1                (0x2UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR5_NB_2                (0x4UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR5_NB_3                (0x8UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR5_VSF_Pos             (8U)

+#define JPEG_CONFR5_VSF_Msk             (0xFUL << JPEG_CONFR5_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR5_VSF                 JPEG_CONFR5_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR5_VSF_0               (0x1UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR5_VSF_1               (0x2UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR5_VSF_2               (0x4UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR5_VSF_3               (0x8UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR5_HSF_Pos             (12U)

+#define JPEG_CONFR5_HSF_Msk             (0xFUL << JPEG_CONFR5_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR5_HSF                 JPEG_CONFR5_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR5_HSF_0               (0x1UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR5_HSF_1               (0x2UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR5_HSF_2               (0x4UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR5_HSF_3               (0x8UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR6 register  ********************/

+#define JPEG_CONFR6_HD_Pos              (0U)

+#define JPEG_CONFR6_HD_Msk              (0x1UL << JPEG_CONFR6_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR6_HD                  JPEG_CONFR6_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR6_HA_Pos              (1U)

+#define JPEG_CONFR6_HA_Msk              (0x1UL << JPEG_CONFR6_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR6_HA                  JPEG_CONFR6_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR6_QT_Pos              (2U)

+#define JPEG_CONFR6_QT_Msk              (0x3UL << JPEG_CONFR6_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR6_QT                  JPEG_CONFR6_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR6_QT_0                (0x1UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR6_QT_1                (0x2UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR6_NB_Pos              (4U)

+#define JPEG_CONFR6_NB_Msk              (0xFUL << JPEG_CONFR6_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR6_NB                  JPEG_CONFR6_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR6_NB_0                (0x1UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR6_NB_1                (0x2UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR6_NB_2                (0x4UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR6_NB_3                (0x8UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR6_VSF_Pos             (8U)

+#define JPEG_CONFR6_VSF_Msk             (0xFUL << JPEG_CONFR6_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR6_VSF                 JPEG_CONFR6_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR6_VSF_0               (0x1UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR6_VSF_1               (0x2UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR6_VSF_2               (0x4UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR6_VSF_3               (0x8UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR6_HSF_Pos             (12U)

+#define JPEG_CONFR6_HSF_Msk             (0xFUL << JPEG_CONFR6_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR6_HSF                 JPEG_CONFR6_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR6_HSF_0               (0x1UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR6_HSF_1               (0x2UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR6_HSF_2               (0x4UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR6_HSF_3               (0x8UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR7 register  ********************/

+#define JPEG_CONFR7_HD_Pos              (0U)

+#define JPEG_CONFR7_HD_Msk              (0x1UL << JPEG_CONFR7_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR7_HD                  JPEG_CONFR7_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR7_HA_Pos              (1U)

+#define JPEG_CONFR7_HA_Msk              (0x1UL << JPEG_CONFR7_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR7_HA                  JPEG_CONFR7_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR7_QT_Pos              (2U)

+#define JPEG_CONFR7_QT_Msk              (0x3UL << JPEG_CONFR7_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR7_QT                  JPEG_CONFR7_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR7_QT_0                (0x1UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR7_QT_1                (0x2UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR7_NB_Pos              (4U)

+#define JPEG_CONFR7_NB_Msk              (0xFUL << JPEG_CONFR7_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR7_NB                  JPEG_CONFR7_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR7_NB_0                (0x1UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR7_NB_1                (0x2UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR7_NB_2                (0x4UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR7_NB_3                (0x8UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR7_VSF_Pos             (8U)

+#define JPEG_CONFR7_VSF_Msk             (0xFUL << JPEG_CONFR7_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR7_VSF                 JPEG_CONFR7_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR7_VSF_0               (0x1UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR7_VSF_1               (0x2UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR7_VSF_2               (0x4UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR7_VSF_3               (0x8UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR7_HSF_Pos             (12U)

+#define JPEG_CONFR7_HSF_Msk             (0xFUL << JPEG_CONFR7_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR7_HSF                 JPEG_CONFR7_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR7_HSF_0               (0x1UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR7_HSF_1               (0x2UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR7_HSF_2               (0x4UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR7_HSF_3               (0x8UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CR register  ********************/

+#define JPEG_CR_JCEN_Pos                (0U)

+#define JPEG_CR_JCEN_Msk                (0x1UL << JPEG_CR_JCEN_Pos)            /*!< 0x00000001 */

+#define JPEG_CR_JCEN                    JPEG_CR_JCEN_Msk                       /*!<Enable the JPEG Codec Core */

+#define JPEG_CR_IFTIE_Pos               (1U)

+#define JPEG_CR_IFTIE_Msk               (0x1UL << JPEG_CR_IFTIE_Pos)           /*!< 0x00000002 */

+#define JPEG_CR_IFTIE                   JPEG_CR_IFTIE_Msk                      /*!<Input FIFO Threshold Interrupt Enable */

+#define JPEG_CR_IFNFIE_Pos              (2U)

+#define JPEG_CR_IFNFIE_Msk              (0x1UL << JPEG_CR_IFNFIE_Pos)          /*!< 0x00000004 */

+#define JPEG_CR_IFNFIE                  JPEG_CR_IFNFIE_Msk                     /*!<Input FIFO Not Full Interrupt Enable */

+#define JPEG_CR_OFTIE_Pos               (3U)

+#define JPEG_CR_OFTIE_Msk               (0x1UL << JPEG_CR_OFTIE_Pos)           /*!< 0x00000008 */

+#define JPEG_CR_OFTIE                   JPEG_CR_OFTIE_Msk                      /*!<Output FIFO Threshold Interrupt Enable */

+#define JPEG_CR_OFNEIE_Pos              (4U)

+#define JPEG_CR_OFNEIE_Msk              (0x1UL << JPEG_CR_OFNEIE_Pos)          /*!< 0x00000010 */

+#define JPEG_CR_OFNEIE                  JPEG_CR_OFNEIE_Msk                     /*!<Output FIFO Not Empty Interrupt Enable */

+#define JPEG_CR_EOCIE_Pos               (5U)

+#define JPEG_CR_EOCIE_Msk               (0x1UL << JPEG_CR_EOCIE_Pos)           /*!< 0x00000020 */

+#define JPEG_CR_EOCIE                   JPEG_CR_EOCIE_Msk                      /*!<End of Conversion Interrupt Enable */

+#define JPEG_CR_HPDIE_Pos               (6U)

+#define JPEG_CR_HPDIE_Msk               (0x1UL << JPEG_CR_HPDIE_Pos)           /*!< 0x00000040 */

+#define JPEG_CR_HPDIE                   JPEG_CR_HPDIE_Msk                      /*!<Header Parsing Done Interrupt Enable */

+#define JPEG_CR_IFF_Pos                 (13U)

+#define JPEG_CR_IFF_Msk                 (0x1UL << JPEG_CR_IFF_Pos)             /*!< 0x00002000 */

+#define JPEG_CR_IFF                     JPEG_CR_IFF_Msk                        /*!<Flush the input FIFO */

+#define JPEG_CR_OFF_Pos                 (14U)

+#define JPEG_CR_OFF_Msk                 (0x1UL << JPEG_CR_OFF_Pos)             /*!< 0x00004000 */

+#define JPEG_CR_OFF                     JPEG_CR_OFF_Msk                        /*!<Flush the output FIFO */

+

+/********************  Bit definition for SR register  ********************/

+#define JPEG_SR_IFTF_Pos                (1U)

+#define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */

+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is bellow its threshold flag */

+#define JPEG_SR_IFNFF_Pos               (2U)

+#define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */

+#define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */

+#define JPEG_SR_OFTF_Pos                (3U)

+#define JPEG_SR_OFTF_Msk                (0x1UL << JPEG_SR_OFTF_Pos)            /*!< 0x00000008 */

+#define JPEG_SR_OFTF                    JPEG_SR_OFTF_Msk                       /*!<Output FIFO is not empty and has reach its threshold */

+#define JPEG_SR_OFNEF_Pos               (4U)

+#define JPEG_SR_OFNEF_Msk               (0x1UL << JPEG_SR_OFNEF_Pos)           /*!< 0x00000010 */

+#define JPEG_SR_OFNEF                   JPEG_SR_OFNEF_Msk                      /*!<Output FIFO is not empty, a data is available */

+#define JPEG_SR_EOCF_Pos                (5U)

+#define JPEG_SR_EOCF_Msk                (0x1UL << JPEG_SR_EOCF_Pos)            /*!< 0x00000020 */

+#define JPEG_SR_EOCF                    JPEG_SR_EOCF_Msk                       /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */

+#define JPEG_SR_HPDF_Pos                (6U)

+#define JPEG_SR_HPDF_Msk                (0x1UL << JPEG_SR_HPDF_Pos)            /*!< 0x00000040 */

+#define JPEG_SR_HPDF                    JPEG_SR_HPDF_Msk                       /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */

+#define JPEG_SR_COF_Pos                 (7U)

+#define JPEG_SR_COF_Msk                 (0x1UL << JPEG_SR_COF_Pos)             /*!< 0x00000080 */

+#define JPEG_SR_COF                     JPEG_SR_COF_Msk                        /*!<JPEG Codec operation on going flag */

+

+/********************  Bit definition for CFR register  ********************/

+#define JPEG_CFR_CEOCF_Pos              (4U)

+#define JPEG_CFR_CEOCF_Msk              (0x1UL << JPEG_CFR_CEOCF_Pos)          /*!< 0x00000010 */

+#define JPEG_CFR_CEOCF                  JPEG_CFR_CEOCF_Msk                     /*!<Clear End of Conversion Flag */

+#define JPEG_CFR_CHPDF_Pos              (5U)

+#define JPEG_CFR_CHPDF_Msk              (0x1UL << JPEG_CFR_CHPDF_Pos)          /*!< 0x00000020 */

+#define JPEG_CFR_CHPDF                  JPEG_CFR_CHPDF_Msk                     /*!<Clear Header Parsing Done Flag */

+

+/********************  Bit definition for DIR register  ********************/

+#define JPEG_DIR_DATAIN_Pos             (0U)

+#define JPEG_DIR_DATAIN_Msk             (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)  /*!< 0xFFFFFFFF */

+#define JPEG_DIR_DATAIN                 JPEG_DIR_DATAIN_Msk                    /*!<Data Input FIFO */

+

+/********************  Bit definition for DOR register  ********************/

+#define JPEG_DOR_DATAOUT_Pos            (0U)

+#define JPEG_DOR_DATAOUT_Msk            (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */

+#define JPEG_DOR_DATAOUT                JPEG_DOR_DATAOUT_Msk                   /*!<Data Output FIFO */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      LCD-TFT Display Controller (LTDC)                     */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for LTDC_SSCR register  *****************/

+

+#define LTDC_SSCR_VSH_Pos            (0U)

+#define LTDC_SSCR_VSH_Msk            (0x7FFUL << LTDC_SSCR_VSH_Pos)            /*!< 0x000007FF */

+#define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height  */

+#define LTDC_SSCR_HSW_Pos            (16U)

+#define LTDC_SSCR_HSW_Msk            (0xFFFUL << LTDC_SSCR_HSW_Pos)            /*!< 0x0FFF0000 */

+#define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */

+

+/********************  Bit definition for LTDC_BPCR register  *****************/

+

+#define LTDC_BPCR_AVBP_Pos           (0U)

+#define LTDC_BPCR_AVBP_Msk           (0x7FFUL << LTDC_BPCR_AVBP_Pos)           /*!< 0x000007FF */

+#define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch   */

+#define LTDC_BPCR_AHBP_Pos           (16U)

+#define LTDC_BPCR_AHBP_Msk           (0xFFFUL << LTDC_BPCR_AHBP_Pos)           /*!< 0x0FFF0000 */

+#define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */

+

+/********************  Bit definition for LTDC_AWCR register  *****************/

+

+#define LTDC_AWCR_AAH_Pos            (0U)

+#define LTDC_AWCR_AAH_Msk            (0x7FFUL << LTDC_AWCR_AAH_Pos)            /*!< 0x000007FF */

+#define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active heigh */

+#define LTDC_AWCR_AAW_Pos            (16U)

+#define LTDC_AWCR_AAW_Msk            (0xFFFUL << LTDC_AWCR_AAW_Pos)            /*!< 0x0FFF0000 */

+#define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */

+

+/********************  Bit definition for LTDC_TWCR register  *****************/

+

+#define LTDC_TWCR_TOTALH_Pos         (0U)

+#define LTDC_TWCR_TOTALH_Msk         (0x7FFUL << LTDC_TWCR_TOTALH_Pos)         /*!< 0x000007FF */

+#define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total Heigh */

+#define LTDC_TWCR_TOTALW_Pos         (16U)

+#define LTDC_TWCR_TOTALW_Msk         (0xFFFUL << LTDC_TWCR_TOTALW_Pos)         /*!< 0x0FFF0000 */

+#define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */

+

+/********************  Bit definition for LTDC_GCR register  ******************/

+

+#define LTDC_GCR_LTDCEN_Pos          (0U)

+#define LTDC_GCR_LTDCEN_Msk          (0x1UL << LTDC_GCR_LTDCEN_Pos)            /*!< 0x00000001 */

+#define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit       */

+#define LTDC_GCR_DBW_Pos             (4U)

+#define LTDC_GCR_DBW_Msk             (0x7UL << LTDC_GCR_DBW_Pos)               /*!< 0x00000070 */

+#define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width                   */

+#define LTDC_GCR_DGW_Pos             (8U)

+#define LTDC_GCR_DGW_Msk             (0x7UL << LTDC_GCR_DGW_Pos)               /*!< 0x00000700 */

+#define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width                  */

+#define LTDC_GCR_DRW_Pos             (12U)

+#define LTDC_GCR_DRW_Msk             (0x7UL << LTDC_GCR_DRW_Pos)               /*!< 0x00007000 */

+#define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width                    */

+#define LTDC_GCR_DEN_Pos             (16U)

+#define LTDC_GCR_DEN_Msk             (0x1UL << LTDC_GCR_DEN_Pos)               /*!< 0x00010000 */

+#define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable                       */

+#define LTDC_GCR_PCPOL_Pos           (28U)

+#define LTDC_GCR_PCPOL_Msk           (0x1UL << LTDC_GCR_PCPOL_Pos)             /*!< 0x10000000 */

+#define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity                */

+#define LTDC_GCR_DEPOL_Pos           (29U)

+#define LTDC_GCR_DEPOL_Msk           (0x1UL << LTDC_GCR_DEPOL_Pos)             /*!< 0x20000000 */

+#define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity                */

+#define LTDC_GCR_VSPOL_Pos           (30U)

+#define LTDC_GCR_VSPOL_Msk           (0x1UL << LTDC_GCR_VSPOL_Pos)             /*!< 0x40000000 */

+#define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity   */

+#define LTDC_GCR_HSPOL_Pos           (31U)

+#define LTDC_GCR_HSPOL_Msk           (0x1UL << LTDC_GCR_HSPOL_Pos)             /*!< 0x80000000 */

+#define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */

+

+

+/********************  Bit definition for LTDC_SRCR register  *****************/

+

+#define LTDC_SRCR_IMR_Pos            (0U)

+#define LTDC_SRCR_IMR_Msk            (0x1UL << LTDC_SRCR_IMR_Pos)              /*!< 0x00000001 */

+#define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload         */

+#define LTDC_SRCR_VBR_Pos            (1U)

+#define LTDC_SRCR_VBR_Msk            (0x1UL << LTDC_SRCR_VBR_Pos)              /*!< 0x00000002 */

+#define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */

+

+/********************  Bit definition for LTDC_BCCR register  *****************/

+

+#define LTDC_BCCR_BCBLUE_Pos         (0U)

+#define LTDC_BCCR_BCBLUE_Msk         (0xFFUL << LTDC_BCCR_BCBLUE_Pos)          /*!< 0x000000FF */

+#define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value  */

+#define LTDC_BCCR_BCGREEN_Pos        (8U)

+#define LTDC_BCCR_BCGREEN_Msk        (0xFFUL << LTDC_BCCR_BCGREEN_Pos)         /*!< 0x0000FF00 */

+#define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */

+#define LTDC_BCCR_BCRED_Pos          (16U)

+#define LTDC_BCCR_BCRED_Msk          (0xFFUL << LTDC_BCCR_BCRED_Pos)           /*!< 0x00FF0000 */

+#define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value   */

+

+/********************  Bit definition for LTDC_IER register  ******************/

+

+#define LTDC_IER_LIE_Pos             (0U)

+#define LTDC_IER_LIE_Msk             (0x1UL << LTDC_IER_LIE_Pos)               /*!< 0x00000001 */

+#define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable            */

+#define LTDC_IER_FUIE_Pos            (1U)

+#define LTDC_IER_FUIE_Msk            (0x1UL << LTDC_IER_FUIE_Pos)              /*!< 0x00000002 */

+#define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable   */

+#define LTDC_IER_TERRIE_Pos          (2U)

+#define LTDC_IER_TERRIE_Msk          (0x1UL << LTDC_IER_TERRIE_Pos)            /*!< 0x00000004 */

+#define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable  */

+#define LTDC_IER_RRIE_Pos            (3U)

+#define LTDC_IER_RRIE_Msk            (0x1UL << LTDC_IER_RRIE_Pos)              /*!< 0x00000008 */

+#define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */

+

+/********************  Bit definition for LTDC_ISR register  ******************/

+

+#define LTDC_ISR_LIF_Pos             (0U)

+#define LTDC_ISR_LIF_Msk             (0x1UL << LTDC_ISR_LIF_Pos)               /*!< 0x00000001 */

+#define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */

+#define LTDC_ISR_FUIF_Pos            (1U)

+#define LTDC_ISR_FUIF_Msk            (0x1UL << LTDC_ISR_FUIF_Pos)              /*!< 0x00000002 */

+#define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */

+#define LTDC_ISR_TERRIF_Pos          (2U)

+#define LTDC_ISR_TERRIF_Msk          (0x1UL << LTDC_ISR_TERRIF_Pos)            /*!< 0x00000004 */

+#define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */

+#define LTDC_ISR_RRIF_Pos            (3U)

+#define LTDC_ISR_RRIF_Msk            (0x1UL << LTDC_ISR_RRIF_Pos)              /*!< 0x00000008 */

+#define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */

+

+/********************  Bit definition for LTDC_ICR register  ******************/

+

+#define LTDC_ICR_CLIF_Pos            (0U)

+#define LTDC_ICR_CLIF_Msk            (0x1UL << LTDC_ICR_CLIF_Pos)              /*!< 0x00000001 */

+#define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */

+#define LTDC_ICR_CFUIF_Pos           (1U)

+#define LTDC_ICR_CFUIF_Msk           (0x1UL << LTDC_ICR_CFUIF_Pos)             /*!< 0x00000002 */

+#define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */

+#define LTDC_ICR_CTERRIF_Pos         (2U)

+#define LTDC_ICR_CTERRIF_Msk         (0x1UL << LTDC_ICR_CTERRIF_Pos)           /*!< 0x00000004 */

+#define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */

+#define LTDC_ICR_CRRIF_Pos           (3U)

+#define LTDC_ICR_CRRIF_Msk           (0x1UL << LTDC_ICR_CRRIF_Pos)             /*!< 0x00000008 */

+#define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */

+

+/********************  Bit definition for LTDC_LIPCR register  ****************/

+

+#define LTDC_LIPCR_LIPOS_Pos         (0U)

+#define LTDC_LIPCR_LIPOS_Msk         (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)         /*!< 0x000007FF */

+#define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */

+

+/********************  Bit definition for LTDC_CPSR register  *****************/

+

+#define LTDC_CPSR_CYPOS_Pos          (0U)

+#define LTDC_CPSR_CYPOS_Msk          (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)         /*!< 0x0000FFFF */

+#define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */

+#define LTDC_CPSR_CXPOS_Pos          (16U)

+#define LTDC_CPSR_CXPOS_Msk          (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)         /*!< 0xFFFF0000 */

+#define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */

+

+/********************  Bit definition for LTDC_CDSR register  *****************/

+

+#define LTDC_CDSR_VDES_Pos           (0U)

+#define LTDC_CDSR_VDES_Msk           (0x1UL << LTDC_CDSR_VDES_Pos)             /*!< 0x00000001 */

+#define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status       */

+#define LTDC_CDSR_HDES_Pos           (1U)

+#define LTDC_CDSR_HDES_Msk           (0x1UL << LTDC_CDSR_HDES_Pos)             /*!< 0x00000002 */

+#define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status     */

+#define LTDC_CDSR_VSYNCS_Pos         (2U)

+#define LTDC_CDSR_VSYNCS_Msk         (0x1UL << LTDC_CDSR_VSYNCS_Pos)           /*!< 0x00000004 */

+#define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status   */

+#define LTDC_CDSR_HSYNCS_Pos         (3U)

+#define LTDC_CDSR_HSYNCS_Msk         (0x1UL << LTDC_CDSR_HSYNCS_Pos)           /*!< 0x00000008 */

+#define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */

+

+/********************  Bit definition for LTDC_LxCR register  *****************/

+

+#define LTDC_LxCR_LEN_Pos            (0U)

+#define LTDC_LxCR_LEN_Msk            (0x1UL << LTDC_LxCR_LEN_Pos)              /*!< 0x00000001 */

+#define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable              */

+#define LTDC_LxCR_COLKEN_Pos         (1U)

+#define LTDC_LxCR_COLKEN_Msk         (0x1UL << LTDC_LxCR_COLKEN_Pos)           /*!< 0x00000002 */

+#define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable       */

+#define LTDC_LxCR_CLUTEN_Pos         (4U)

+#define LTDC_LxCR_CLUTEN_Msk         (0x1UL << LTDC_LxCR_CLUTEN_Pos)           /*!< 0x00000010 */

+#define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */

+

+/********************  Bit definition for LTDC_LxWHPCR register  **************/

+

+#define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)

+#define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)     /*!< 0x00000FFF */

+#define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */

+#define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)

+#define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)    /*!< 0xFFFF0000 */

+#define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position  */

+

+/********************  Bit definition for LTDC_LxWVPCR register  **************/

+

+#define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)

+#define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)     /*!< 0x00000FFF */

+#define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */

+#define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)

+#define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)    /*!< 0xFFFF0000 */

+#define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position  */

+

+/********************  Bit definition for LTDC_LxCKCR register  ***************/

+

+#define LTDC_LxCKCR_CKBLUE_Pos       (0U)

+#define LTDC_LxCKCR_CKBLUE_Msk       (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value  */

+#define LTDC_LxCKCR_CKGREEN_Pos      (8U)

+#define LTDC_LxCKCR_CKGREEN_Msk      (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */

+#define LTDC_LxCKCR_CKRED_Pos        (16U)

+#define LTDC_LxCKCR_CKRED_Msk        (0xFFUL << LTDC_LxCKCR_CKRED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value   */

+

+/********************  Bit definition for LTDC_LxPFCR register  ***************/

+

+#define LTDC_LxPFCR_PF_Pos           (0U)

+#define LTDC_LxPFCR_PF_Msk           (0x7UL << LTDC_LxPFCR_PF_Pos)             /*!< 0x00000007 */

+#define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */

+

+/********************  Bit definition for LTDC_LxCACR register  ***************/

+

+#define LTDC_LxCACR_CONSTA_Pos       (0U)

+#define LTDC_LxCACR_CONSTA_Msk       (0xFFUL << LTDC_LxCACR_CONSTA_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */

+

+/********************  Bit definition for LTDC_LxDCCR register  ***************/

+

+#define LTDC_LxDCCR_DCBLUE_Pos       (0U)

+#define LTDC_LxDCCR_DCBLUE_Msk       (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue  */

+#define LTDC_LxDCCR_DCGREEN_Pos      (8U)

+#define LTDC_LxDCCR_DCGREEN_Msk      (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */

+#define LTDC_LxDCCR_DCRED_Pos        (16U)

+#define LTDC_LxDCCR_DCRED_Msk        (0xFFUL << LTDC_LxDCCR_DCRED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red   */

+#define LTDC_LxDCCR_DCALPHA_Pos      (24U)

+#define LTDC_LxDCCR_DCALPHA_Msk      (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)       /*!< 0xFF000000 */

+#define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */

+

+/********************  Bit definition for LTDC_LxBFCR register  ***************/

+

+#define LTDC_LxBFCR_BF2_Pos          (0U)

+#define LTDC_LxBFCR_BF2_Msk          (0x7UL << LTDC_LxBFCR_BF2_Pos)            /*!< 0x00000007 */

+#define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */

+#define LTDC_LxBFCR_BF1_Pos          (8U)

+#define LTDC_LxBFCR_BF1_Msk          (0x7UL << LTDC_LxBFCR_BF1_Pos)            /*!< 0x00000700 */

+#define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */

+

+/********************  Bit definition for LTDC_LxCFBAR register  **************/

+

+#define LTDC_LxCFBAR_CFBADD_Pos      (0U)

+#define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */

+#define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */

+

+/********************  Bit definition for LTDC_LxCFBLR register  **************/

+

+#define LTDC_LxCFBLR_CFBLL_Pos       (0U)

+#define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)      /*!< 0x00001FFF */

+#define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length    */

+#define LTDC_LxCFBLR_CFBP_Pos        (16U)

+#define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)       /*!< 0x1FFF0000 */

+#define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */

+

+/********************  Bit definition for LTDC_LxCFBLNR register  *************/

+

+#define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)

+#define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)    /*!< 0x000007FF */

+#define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */

+

+/********************  Bit definition for LTDC_LxCLUTWR register  *************/

+

+#define LTDC_LxCLUTWR_BLUE_Pos       (0U)

+#define LTDC_LxCLUTWR_BLUE_Msk       (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value   */

+#define LTDC_LxCLUTWR_GREEN_Pos      (8U)

+#define LTDC_LxCLUTWR_GREEN_Msk      (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value  */

+#define LTDC_LxCLUTWR_RED_Pos        (16U)

+#define LTDC_LxCLUTWR_RED_Msk        (0xFFUL << LTDC_LxCLUTWR_RED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value    */

+#define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)

+#define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)     /*!< 0xFF000000 */

+#define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                     MDMA                                   */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for MDMA_GISR0 register  ****************/

+#define MDMA_GISR0_GIF0_Pos       (0U)

+#define MDMA_GISR0_GIF0_Msk       (0x1UL << MDMA_GISR0_GIF0_Pos)               /*!< 0x00000001 */

+#define MDMA_GISR0_GIF0           MDMA_GISR0_GIF0_Msk                          /*!< Channel 0 global interrupt flag */

+#define MDMA_GISR0_GIF1_Pos       (1U)

+#define MDMA_GISR0_GIF1_Msk       (0x1UL << MDMA_GISR0_GIF1_Pos)               /*!< 0x00000002 */

+#define MDMA_GISR0_GIF1           MDMA_GISR0_GIF1_Msk                          /*!< Channel 1 global interrupt flag */

+#define MDMA_GISR0_GIF2_Pos       (2U)

+#define MDMA_GISR0_GIF2_Msk       (0x1UL << MDMA_GISR0_GIF2_Pos)               /*!< 0x00000004 */

+#define MDMA_GISR0_GIF2           MDMA_GISR0_GIF2_Msk                          /*!< Channel 2 global interrupt flag */

+#define MDMA_GISR0_GIF3_Pos       (3U)

+#define MDMA_GISR0_GIF3_Msk       (0x1UL << MDMA_GISR0_GIF3_Pos)               /*!< 0x00000008 */

+#define MDMA_GISR0_GIF3           MDMA_GISR0_GIF3_Msk                          /*!< Channel 3 global interrupt flag */

+#define MDMA_GISR0_GIF4_Pos       (4U)

+#define MDMA_GISR0_GIF4_Msk       (0x1UL << MDMA_GISR0_GIF4_Pos)               /*!< 0x00000010 */

+#define MDMA_GISR0_GIF4           MDMA_GISR0_GIF4_Msk                          /*!< Channel 4 global interrupt flag */

+#define MDMA_GISR0_GIF5_Pos       (5U)

+#define MDMA_GISR0_GIF5_Msk       (0x1UL << MDMA_GISR0_GIF5_Pos)               /*!< 0x00000020 */

+#define MDMA_GISR0_GIF5           MDMA_GISR0_GIF5_Msk                          /*!< Channel 5 global interrupt flag */

+#define MDMA_GISR0_GIF6_Pos       (6U)

+#define MDMA_GISR0_GIF6_Msk       (0x1UL << MDMA_GISR0_GIF6_Pos)               /*!< 0x00000040 */

+#define MDMA_GISR0_GIF6           MDMA_GISR0_GIF6_Msk                          /*!< Channel 6 global interrupt flag */

+#define MDMA_GISR0_GIF7_Pos       (7U)

+#define MDMA_GISR0_GIF7_Msk       (0x1UL << MDMA_GISR0_GIF7_Pos)               /*!< 0x00000080 */

+#define MDMA_GISR0_GIF7           MDMA_GISR0_GIF7_Msk                          /*!< Channel 7 global interrupt flag */

+#define MDMA_GISR0_GIF8_Pos       (8U)

+#define MDMA_GISR0_GIF8_Msk       (0x1UL << MDMA_GISR0_GIF8_Pos)               /*!< 0x00000100 */

+#define MDMA_GISR0_GIF8           MDMA_GISR0_GIF8_Msk                          /*!< Channel 8 global interrupt flag */

+#define MDMA_GISR0_GIF9_Pos       (9U)

+#define MDMA_GISR0_GIF9_Msk       (0x1UL << MDMA_GISR0_GIF9_Pos)               /*!< 0x00000200 */

+#define MDMA_GISR0_GIF9           MDMA_GISR0_GIF9_Msk                          /*!< Channel 9 global interrupt flag */

+#define MDMA_GISR0_GIF10_Pos      (10U)

+#define MDMA_GISR0_GIF10_Msk      (0x1UL << MDMA_GISR0_GIF10_Pos)              /*!< 0x00000400 */

+#define MDMA_GISR0_GIF10          MDMA_GISR0_GIF10_Msk                         /*!< Channel 10 global interrupt flag */

+#define MDMA_GISR0_GIF11_Pos      (11U)

+#define MDMA_GISR0_GIF11_Msk      (0x1UL << MDMA_GISR0_GIF11_Pos)              /*!< 0x00000800 */

+#define MDMA_GISR0_GIF11          MDMA_GISR0_GIF11_Msk                         /*!< Channel 11 global interrupt flag */

+#define MDMA_GISR0_GIF12_Pos      (12U)

+#define MDMA_GISR0_GIF12_Msk      (0x1UL << MDMA_GISR0_GIF12_Pos)              /*!< 0x00001000 */

+#define MDMA_GISR0_GIF12          MDMA_GISR0_GIF12_Msk                         /*!< Channel 12 global interrupt flag */

+#define MDMA_GISR0_GIF13_Pos      (13U)

+#define MDMA_GISR0_GIF13_Msk      (0x1UL << MDMA_GISR0_GIF13_Pos)              /*!< 0x00002000 */

+#define MDMA_GISR0_GIF13          MDMA_GISR0_GIF13_Msk                         /*!< Channel 13 global interrupt flag */

+#define MDMA_GISR0_GIF14_Pos      (14U)

+#define MDMA_GISR0_GIF14_Msk      (0x1UL << MDMA_GISR0_GIF14_Pos)              /*!< 0x00004000 */

+#define MDMA_GISR0_GIF14          MDMA_GISR0_GIF14_Msk                         /*!< Channel 14 global interrupt flag */

+#define MDMA_GISR0_GIF15_Pos      (15U)

+#define MDMA_GISR0_GIF15_Msk      (0x1UL << MDMA_GISR0_GIF15_Pos)              /*!< 0x00008000 */

+#define MDMA_GISR0_GIF15          MDMA_GISR0_GIF15_Msk                         /*!< Channel 15 global interrupt flag */

+

+/********************  Bit definition for MDMA_CxISR register  ****************/

+#define MDMA_CISR_TEIF_Pos        (0U)

+#define MDMA_CISR_TEIF_Msk        (0x1UL << MDMA_CISR_TEIF_Pos)                /*!< 0x00000001 */

+#define MDMA_CISR_TEIF            MDMA_CISR_TEIF_Msk                           /*!< Channel x transfer error interrupt flag */

+#define MDMA_CISR_CTCIF_Pos       (1U)

+#define MDMA_CISR_CTCIF_Msk       (0x1UL << MDMA_CISR_CTCIF_Pos)               /*!< 0x00000002 */

+#define MDMA_CISR_CTCIF           MDMA_CISR_CTCIF_Msk                          /*!< Channel x Channel Transfer Complete interrupt flag */

+#define MDMA_CISR_BRTIF_Pos       (2U)

+#define MDMA_CISR_BRTIF_Msk       (0x1UL << MDMA_CISR_BRTIF_Pos)               /*!< 0x00000004 */

+#define MDMA_CISR_BRTIF           MDMA_CISR_BRTIF_Msk                          /*!< Channel x block repeat transfer complete interrupt flag */

+#define MDMA_CISR_BTIF_Pos        (3U)

+#define MDMA_CISR_BTIF_Msk        (0x1UL << MDMA_CISR_BTIF_Pos)                /*!< 0x00000008 */

+#define MDMA_CISR_BTIF            MDMA_CISR_BTIF_Msk                           /*!< Channel x block transfer complete interrupt flag */

+#define MDMA_CISR_TCIF_Pos        (4U)

+#define MDMA_CISR_TCIF_Msk        (0x1UL << MDMA_CISR_TCIF_Pos)                /*!< 0x00000010 */

+#define MDMA_CISR_TCIF            MDMA_CISR_TCIF_Msk                           /*!< Channel x buffer transfer complete interrupt flag */

+#define MDMA_CISR_CRQA_Pos        (16U)

+#define MDMA_CISR_CRQA_Msk        (0x1UL << MDMA_CISR_CRQA_Pos)                /*!< 0x00010000 */

+#define MDMA_CISR_CRQA            MDMA_CISR_CRQA_Msk                           /*!< Channel x ReQest Active flag */

+

+/********************  Bit definition for MDMA_CxIFCR register  ****************/

+#define MDMA_CIFCR_CTEIF_Pos      (0U)

+#define MDMA_CIFCR_CTEIF_Msk      (0x1UL << MDMA_CIFCR_CTEIF_Pos)              /*!< 0x00000001 */

+#define MDMA_CIFCR_CTEIF          MDMA_CIFCR_CTEIF_Msk                         /*!< Channel x clear transfer error interrupt flag */

+#define MDMA_CIFCR_CCTCIF_Pos     (1U)

+#define MDMA_CIFCR_CCTCIF_Msk     (0x1UL << MDMA_CIFCR_CCTCIF_Pos)             /*!< 0x00000002 */

+#define MDMA_CIFCR_CCTCIF         MDMA_CIFCR_CCTCIF_Msk                        /*!< Clear Channel transfer complete interrupt flag for channel x */

+#define MDMA_CIFCR_CBRTIF_Pos     (2U)

+#define MDMA_CIFCR_CBRTIF_Msk     (0x1UL << MDMA_CIFCR_CBRTIF_Pos)             /*!< 0x00000004 */

+#define MDMA_CIFCR_CBRTIF         MDMA_CIFCR_CBRTIF_Msk                        /*!< Channel x clear block repeat transfer complete interrupt flag */

+#define MDMA_CIFCR_CBTIF_Pos      (3U)

+#define MDMA_CIFCR_CBTIF_Msk      (0x1UL << MDMA_CIFCR_CBTIF_Pos)              /*!< 0x00000008 */

+#define MDMA_CIFCR_CBTIF          MDMA_CIFCR_CBTIF_Msk                         /*!< Channel x Clear block transfer complete interrupt flag */

+#define MDMA_CIFCR_CLTCIF_Pos     (4U)

+#define MDMA_CIFCR_CLTCIF_Msk     (0x1UL << MDMA_CIFCR_CLTCIF_Pos)             /*!< 0x00000010 */

+#define MDMA_CIFCR_CLTCIF         MDMA_CIFCR_CLTCIF_Msk                        /*!< CLear Transfer buffer Complete Interrupt Flag for channel */

+

+/********************  Bit definition for MDMA_CxESR register  ****************/

+#define MDMA_CESR_TEA_Pos         (0U)

+#define MDMA_CESR_TEA_Msk         (0x7FUL << MDMA_CESR_TEA_Pos)                /*!< 0x0000007F */

+#define MDMA_CESR_TEA             MDMA_CESR_TEA_Msk                            /*!< Transfer Error Address */

+#define MDMA_CESR_TED_Pos         (7U)

+#define MDMA_CESR_TED_Msk         (0x1UL << MDMA_CESR_TED_Pos)                 /*!< 0x00000080 */

+#define MDMA_CESR_TED             MDMA_CESR_TED_Msk                            /*!< Transfer Error Direction */

+#define MDMA_CESR_TELD_Pos        (8U)

+#define MDMA_CESR_TELD_Msk        (0x1UL << MDMA_CESR_TELD_Pos)                /*!< 0x00000100 */

+#define MDMA_CESR_TELD            MDMA_CESR_TELD_Msk                           /*!< Transfer Error Link Data */

+#define MDMA_CESR_TEMD_Pos        (9U)

+#define MDMA_CESR_TEMD_Msk        (0x1UL << MDMA_CESR_TEMD_Pos)                /*!< 0x00000200 */

+#define MDMA_CESR_TEMD            MDMA_CESR_TEMD_Msk                           /*!< Transfer Error Mask Data */

+#define MDMA_CESR_ASE_Pos         (10U)

+#define MDMA_CESR_ASE_Msk         (0x1UL << MDMA_CESR_ASE_Pos)                 /*!< 0x00000400 */

+#define MDMA_CESR_ASE             MDMA_CESR_ASE_Msk                            /*!< Address/Size Error       */

+#define MDMA_CESR_BSE_Pos         (11U)

+#define MDMA_CESR_BSE_Msk         (0x1UL << MDMA_CESR_BSE_Pos)                 /*!< 0x00000800 */

+#define MDMA_CESR_BSE             MDMA_CESR_BSE_Msk                            /*!< Block Size Error         */

+

+/********************  Bit definition for MDMA_CxCR register  ****************/

+#define MDMA_CCR_EN_Pos           (0U)

+#define MDMA_CCR_EN_Msk           (0x1UL << MDMA_CCR_EN_Pos)                   /*!< 0x00000001 */

+#define MDMA_CCR_EN               MDMA_CCR_EN_Msk                              /*!< Channel enable / flag channel ready when read low */

+#define MDMA_CCR_TEIE_Pos         (1U)

+#define MDMA_CCR_TEIE_Msk         (0x1UL << MDMA_CCR_TEIE_Pos)                 /*!< 0x00000002 */

+#define MDMA_CCR_TEIE             MDMA_CCR_TEIE_Msk                            /*!< Transfer error interrupt enable */

+#define MDMA_CCR_CTCIE_Pos        (2U)

+#define MDMA_CCR_CTCIE_Msk        (0x1UL << MDMA_CCR_CTCIE_Pos)                /*!< 0x00000004 */

+#define MDMA_CCR_CTCIE            MDMA_CCR_CTCIE_Msk                           /*!< Channel Transfer Complete interrupt enable */

+#define MDMA_CCR_BRTIE_Pos        (3U)

+#define MDMA_CCR_BRTIE_Msk        (0x1UL << MDMA_CCR_BRTIE_Pos)                /*!< 0x00000008 */

+#define MDMA_CCR_BRTIE            MDMA_CCR_BRTIE_Msk                           /*!< Block Repeat transfer interrupt enable */

+#define MDMA_CCR_BTIE_Pos         (4U)

+#define MDMA_CCR_BTIE_Msk         (0x1UL << MDMA_CCR_BTIE_Pos)                 /*!< 0x00000010 */

+#define MDMA_CCR_BTIE             MDMA_CCR_BTIE_Msk                            /*!< Block Transfer interrupt enable */

+#define MDMA_CCR_TCIE_Pos         (5U)

+#define MDMA_CCR_TCIE_Msk         (0x1UL << MDMA_CCR_TCIE_Pos)                 /*!< 0x00000020 */

+#define MDMA_CCR_TCIE             MDMA_CCR_TCIE_Msk                            /*!< buffer Transfer Complete interrupt enable */

+#define MDMA_CCR_PL_Pos           (6U)

+#define MDMA_CCR_PL_Msk           (0x3UL << MDMA_CCR_PL_Pos)                   /*!< 0x000000C0 */

+#define MDMA_CCR_PL               MDMA_CCR_PL_Msk                              /*!< Priority level */

+#define MDMA_CCR_PL_0             (0x1UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000040 */

+#define MDMA_CCR_PL_1             (0x2UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000080 */

+#define MDMA_CCR_BEX_Pos          (12U)

+#define MDMA_CCR_BEX_Msk          (0x1UL << MDMA_CCR_BEX_Pos)                  /*!< 0x00001000 */

+#define MDMA_CCR_BEX              MDMA_CCR_BEX_Msk                             /*!< Byte Endianess eXchange */

+#define MDMA_CCR_HEX_Pos          (13U)

+#define MDMA_CCR_HEX_Msk          (0x1UL << MDMA_CCR_HEX_Pos)                  /*!< 0x00002000 */

+#define MDMA_CCR_HEX              MDMA_CCR_HEX_Msk                             /*!< Half word Endianess eXchange */

+#define MDMA_CCR_WEX_Pos          (14U)

+#define MDMA_CCR_WEX_Msk          (0x1UL << MDMA_CCR_WEX_Pos)                  /*!< 0x00004000 */

+#define MDMA_CCR_WEX              MDMA_CCR_WEX_Msk                             /*!< Word Endianess eXchange */

+#define MDMA_CCR_SWRQ_Pos         (16U)

+#define MDMA_CCR_SWRQ_Msk         (0x1UL << MDMA_CCR_SWRQ_Pos)                 /*!< 0x00010000 */

+#define MDMA_CCR_SWRQ             MDMA_CCR_SWRQ_Msk                            /*!< SW ReQuest */

+

+/********************  Bit definition for MDMA_CxTCR register  ****************/

+#define MDMA_CTCR_SINC_Pos        (0U)

+#define MDMA_CTCR_SINC_Msk        (0x3UL << MDMA_CTCR_SINC_Pos)                /*!< 0x00000003 */

+#define MDMA_CTCR_SINC            MDMA_CTCR_SINC_Msk                           /*!< Source increment mode */

+#define MDMA_CTCR_SINC_0          (0x1UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000001 */

+#define MDMA_CTCR_SINC_1          (0x2UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000002 */

+#define MDMA_CTCR_DINC_Pos        (2U)

+#define MDMA_CTCR_DINC_Msk        (0x3UL << MDMA_CTCR_DINC_Pos)                /*!< 0x0000000C */

+#define MDMA_CTCR_DINC            MDMA_CTCR_DINC_Msk                           /*!< Source increment mode */

+#define MDMA_CTCR_DINC_0          (0x1UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000004 */

+#define MDMA_CTCR_DINC_1          (0x2UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000008 */

+#define MDMA_CTCR_SSIZE_Pos       (4U)

+#define MDMA_CTCR_SSIZE_Msk       (0x3UL << MDMA_CTCR_SSIZE_Pos)               /*!< 0x00000030 */

+#define MDMA_CTCR_SSIZE           MDMA_CTCR_SSIZE_Msk                          /*!< Source data size */

+#define MDMA_CTCR_SSIZE_0         (0x1UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000010 */

+#define MDMA_CTCR_SSIZE_1         (0x2UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000020 */

+#define MDMA_CTCR_DSIZE_Pos       (6U)

+#define MDMA_CTCR_DSIZE_Msk       (0x3UL << MDMA_CTCR_DSIZE_Pos)               /*!< 0x000000C0 */

+#define MDMA_CTCR_DSIZE           MDMA_CTCR_DSIZE_Msk                          /*!< Destination data size */

+#define MDMA_CTCR_DSIZE_0         (0x1UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000040 */

+#define MDMA_CTCR_DSIZE_1         (0x2UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000080 */

+#define MDMA_CTCR_SINCOS_Pos      (8U)

+#define MDMA_CTCR_SINCOS_Msk      (0x3UL << MDMA_CTCR_SINCOS_Pos)              /*!< 0x00000300 */

+#define MDMA_CTCR_SINCOS          MDMA_CTCR_SINCOS_Msk                         /*!< Source increment offset size */

+#define MDMA_CTCR_SINCOS_0        (0x1UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000100 */

+#define MDMA_CTCR_SINCOS_1        (0x2UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000200 */

+#define MDMA_CTCR_DINCOS_Pos      (10U)

+#define MDMA_CTCR_DINCOS_Msk      (0x3UL << MDMA_CTCR_DINCOS_Pos)              /*!< 0x00000C00 */

+#define MDMA_CTCR_DINCOS          MDMA_CTCR_DINCOS_Msk                         /*!< Destination increment offset size */

+#define MDMA_CTCR_DINCOS_0        (0x1UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000400 */

+#define MDMA_CTCR_DINCOS_1        (0x2UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000800 */

+#define MDMA_CTCR_SBURST_Pos      (12U)

+#define MDMA_CTCR_SBURST_Msk      (0x7UL << MDMA_CTCR_SBURST_Pos)              /*!< 0x00007000 */

+#define MDMA_CTCR_SBURST          MDMA_CTCR_SBURST_Msk                         /*!< Source burst transfer configuration */

+#define MDMA_CTCR_SBURST_0        (0x1UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00001000 */

+#define MDMA_CTCR_SBURST_1        (0x2UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00002000 */

+#define MDMA_CTCR_SBURST_2        (0x4UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00004000 */

+#define MDMA_CTCR_DBURST_Pos      (15U)

+#define MDMA_CTCR_DBURST_Msk      (0x7UL << MDMA_CTCR_DBURST_Pos)              /*!< 0x00038000 */

+#define MDMA_CTCR_DBURST          MDMA_CTCR_DBURST_Msk                         /*!< Destination burst transfer configuration */

+#define MDMA_CTCR_DBURST_0        (0x1UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00008000 */

+#define MDMA_CTCR_DBURST_1        (0x2UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00010000 */

+#define MDMA_CTCR_DBURST_2        (0x4UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00020000 */

+#define MDMA_CTCR_TLEN_Pos        (18U)

+#define MDMA_CTCR_TLEN_Msk        (0x7FUL << MDMA_CTCR_TLEN_Pos)               /*!< 0x01FC0000 */

+#define MDMA_CTCR_TLEN            MDMA_CTCR_TLEN_Msk                           /*!< buffer Transfer Length (number of bytes - 1) */

+#define MDMA_CTCR_PKE_Pos         (25U)

+#define MDMA_CTCR_PKE_Msk         (0x1UL << MDMA_CTCR_PKE_Pos)                 /*!< 0x02000000 */

+#define MDMA_CTCR_PKE             MDMA_CTCR_PKE_Msk                            /*!< PacK Enable */

+#define MDMA_CTCR_PAM_Pos         (26U)

+#define MDMA_CTCR_PAM_Msk         (0x3UL << MDMA_CTCR_PAM_Pos)                 /*!< 0x0C000000 */

+#define MDMA_CTCR_PAM             MDMA_CTCR_PAM_Msk                            /*!< Padding/Alignement Mode */

+#define MDMA_CTCR_PAM_0           (0x1UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x4000000 */

+#define MDMA_CTCR_PAM_1           (0x2UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x8000000 */

+#define MDMA_CTCR_TRGM_Pos        (28U)

+#define MDMA_CTCR_TRGM_Msk        (0x3UL << MDMA_CTCR_TRGM_Pos)                /*!< 0x30000000 */

+#define MDMA_CTCR_TRGM            MDMA_CTCR_TRGM_Msk                           /*!< Trigger Mode */

+#define MDMA_CTCR_TRGM_0          (0x1UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x10000000 */

+#define MDMA_CTCR_TRGM_1          (0x2UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x20000000 */

+#define MDMA_CTCR_SWRM_Pos        (30U)

+#define MDMA_CTCR_SWRM_Msk        (0x1UL << MDMA_CTCR_SWRM_Pos)                /*!< 0x40000000 */

+#define MDMA_CTCR_SWRM            MDMA_CTCR_SWRM_Msk                           /*!< SW Request Mode */

+#define MDMA_CTCR_BWM_Pos         (31U)

+#define MDMA_CTCR_BWM_Msk         (0x1UL << MDMA_CTCR_BWM_Pos)                 /*!< 0x80000000 */

+#define MDMA_CTCR_BWM             MDMA_CTCR_BWM_Msk                            /*!< Bufferable Write Mode */

+

+/********************  Bit definition for MDMA_CxBNDTR register  ****************/

+#define MDMA_CBNDTR_BNDT_Pos      (0U)

+#define MDMA_CBNDTR_BNDT_Msk      (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos)          /*!< 0x0001FFFF */

+#define MDMA_CBNDTR_BNDT          MDMA_CBNDTR_BNDT_Msk                         /*!< Block Number of data bytes to transfer */

+#define MDMA_CBNDTR_BRSUM_Pos     (18U)

+#define MDMA_CBNDTR_BRSUM_Msk     (0x1UL << MDMA_CBNDTR_BRSUM_Pos)             /*!< 0x00040000 */

+#define MDMA_CBNDTR_BRSUM         MDMA_CBNDTR_BRSUM_Msk                        /*!< Block Repeat Source address Update Mode */

+#define MDMA_CBNDTR_BRDUM_Pos     (19U)

+#define MDMA_CBNDTR_BRDUM_Msk     (0x1UL << MDMA_CBNDTR_BRDUM_Pos)             /*!< 0x00080000 */

+#define MDMA_CBNDTR_BRDUM         MDMA_CBNDTR_BRDUM_Msk                        /*!< Block Repeat Destination address Update Mode */

+#define MDMA_CBNDTR_BRC_Pos       (20U)

+#define MDMA_CBNDTR_BRC_Msk       (0xFFFUL << MDMA_CBNDTR_BRC_Pos)             /*!< 0xFFF00000 */

+#define MDMA_CBNDTR_BRC           MDMA_CBNDTR_BRC_Msk                          /*!< Block Repeat Count */

+

+/********************  Bit definition for MDMA_CxSAR register  ****************/

+#define MDMA_CSAR_SAR_Pos         (0U)

+#define MDMA_CSAR_SAR_Msk         (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CSAR_SAR             MDMA_CSAR_SAR_Msk                            /*!< Source address */

+

+/********************  Bit definition for MDMA_CxDAR register  ****************/

+#define MDMA_CDAR_DAR_Pos         (0U)

+#define MDMA_CDAR_DAR_Msk         (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CDAR_DAR             MDMA_CDAR_DAR_Msk                            /*!< Destination address */

+

+/********************  Bit definition for MDMA_CxBRUR  ************************/

+#define MDMA_CBRUR_SUV_Pos        (0U)

+#define MDMA_CBRUR_SUV_Msk        (0xFFFFUL << MDMA_CBRUR_SUV_Pos)             /*!< 0x0000FFFF */

+#define MDMA_CBRUR_SUV            MDMA_CBRUR_SUV_Msk                           /*!< Source address Update Value */

+#define MDMA_CBRUR_DUV_Pos        (16U)

+#define MDMA_CBRUR_DUV_Msk        (0xFFFFUL << MDMA_CBRUR_DUV_Pos)             /*!< 0xFFFF0000 */

+#define MDMA_CBRUR_DUV            MDMA_CBRUR_DUV_Msk                           /*!< Destination address Update Value */

+

+/********************  Bit definition for MDMA_CxLAR  *************************/

+#define MDMA_CLAR_LAR_Pos         (0U)

+#define MDMA_CLAR_LAR_Msk         (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CLAR_LAR             MDMA_CLAR_LAR_Msk                            /*!< Link Address Register */

+

+/********************  Bit definition for MDMA_CxTBR)  ************************/

+#define MDMA_CTBR_TSEL_Pos        (0U)

+#define MDMA_CTBR_TSEL_Msk        (0xFFUL << MDMA_CTBR_TSEL_Pos)               /*!< 0x000000FF */

+#define MDMA_CTBR_TSEL            MDMA_CTBR_TSEL_Msk                           /*!< Trigger SELection */

+#define MDMA_CTBR_SBUS_Pos        (16U)

+#define MDMA_CTBR_SBUS_Msk        (0x1UL << MDMA_CTBR_SBUS_Pos)                /*!< 0x00010000 */

+#define MDMA_CTBR_SBUS            MDMA_CTBR_SBUS_Msk                           /*!< Source BUS select */

+#define MDMA_CTBR_DBUS_Pos        (17U)

+#define MDMA_CTBR_DBUS_Msk        (0x1UL << MDMA_CTBR_DBUS_Pos)                /*!< 0x00020000 */

+#define MDMA_CTBR_DBUS            MDMA_CTBR_DBUS_Msk                           /*!< Destination BUS select */

+

+/********************  Bit definition for MDMA_CxMAR)  ************************/

+#define MDMA_CMAR_MAR_Pos         (0U)

+#define MDMA_CMAR_MAR_Msk         (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CMAR_MAR             MDMA_CMAR_MAR_Msk                            /*!< Mask address */

+

+/********************  Bit definition for MDMA_CxMDR)  ************************/

+#define MDMA_CMDR_MDR_Pos         (0U)

+#define MDMA_CMDR_MDR_Msk         (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CMDR_MDR             MDMA_CMDR_MDR_Msk                            /*!< Mask Data */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Operational Amplifier (OPAMP)                      */

+/*                                                                            */

+/******************************************************************************/

+/*********************  Bit definition for OPAMPx_CSR register  ***************/

+#define OPAMP_CSR_OPAMPxEN_Pos           (0U)

+#define OPAMP_CSR_OPAMPxEN_Msk           (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)     /*!< 0x00000001 */

+#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */

+#define OPAMP_CSR_FORCEVP_Pos            (1U)

+#define OPAMP_CSR_FORCEVP_Msk            (0x1UL << OPAMP_CSR_FORCEVP_Pos)      /*!< 0x00000002 */

+#define OPAMP_CSR_FORCEVP                OPAMP_CSR_FORCEVP_Msk                 /*!< Force internal reference on VP */

+

+#define OPAMP_CSR_VPSEL_Pos              (2U)

+#define OPAMP_CSR_VPSEL_Msk              (0x3UL << OPAMP_CSR_VPSEL_Pos)        /*!< 0x0000000C */

+#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */

+#define OPAMP_CSR_VPSEL_0                (0x1UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000004 */

+#define OPAMP_CSR_VPSEL_1                (0x2UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000008 */

+

+#define OPAMP_CSR_VMSEL_Pos              (5U)

+#define OPAMP_CSR_VMSEL_Msk              (0x3UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000060 */

+#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */

+#define OPAMP_CSR_VMSEL_0                (0x1UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000020 */

+#define OPAMP_CSR_VMSEL_1                (0x2UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000040 */

+

+#define OPAMP_CSR_OPAHSM_Pos             (8U)

+#define OPAMP_CSR_OPAHSM_Msk             (0x1UL << OPAMP_CSR_OPAHSM_Pos)       /*!< 0x00000100 */

+#define OPAMP_CSR_OPAHSM                 OPAMP_CSR_OPAHSM_Msk                  /*!< Operational amplifier high speed mode */

+#define OPAMP_CSR_CALON_Pos              (11U)

+#define OPAMP_CSR_CALON_Msk              (0x1UL << OPAMP_CSR_CALON_Pos)        /*!< 0x00000800 */

+#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */

+

+#define OPAMP_CSR_CALSEL_Pos             (12U)

+#define OPAMP_CSR_CALSEL_Msk             (0x3UL << OPAMP_CSR_CALSEL_Pos)       /*!< 0x00003000 */

+#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */

+#define OPAMP_CSR_CALSEL_0               (0x1UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00001000 */

+#define OPAMP_CSR_CALSEL_1               (0x2UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */

+

+#define OPAMP_CSR_PGGAIN_Pos             (14U)

+#define OPAMP_CSR_PGGAIN_Msk             (0xFUL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x0003C000 */

+#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */

+#define OPAMP_CSR_PGGAIN_0               (0x1UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00004000 */

+#define OPAMP_CSR_PGGAIN_1               (0x2UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00008000 */

+#define OPAMP_CSR_PGGAIN_2               (0x4UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00010000 */

+#define OPAMP_CSR_PGGAIN_3               (0x8UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00020000 */

+

+#define OPAMP_CSR_USERTRIM_Pos           (18U)

+#define OPAMP_CSR_USERTRIM_Msk           (0x1UL << OPAMP_CSR_USERTRIM_Pos)     /*!< 0x00040000 */

+#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */

+#define OPAMP_CSR_TSTREF_Pos             (29U)

+#define OPAMP_CSR_TSTREF_Msk             (0x1UL << OPAMP_CSR_TSTREF_Pos)       /*!< 0x20000000 */

+#define OPAMP_CSR_TSTREF                 OPAMP_CSR_TSTREF_Msk                  /*!< OpAmp calibration reference voltage output control */

+#define OPAMP_CSR_CALOUT_Pos             (30U)

+#define OPAMP_CSR_CALOUT_Msk             (0x1UL << OPAMP_CSR_CALOUT_Pos)       /*!< 0x40000000 */

+#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier calibration output */

+

+/*********************  Bit definition for OPAMP1_CSR register  ***************/

+#define OPAMP1_CSR_OPAEN_Pos              (0U)

+#define OPAMP1_CSR_OPAEN_Msk              (0x1UL << OPAMP1_CSR_OPAEN_Pos)      /*!< 0x00000001 */

+#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */

+#define OPAMP1_CSR_FORCEVP_Pos            (1U)

+#define OPAMP1_CSR_FORCEVP_Msk            (0x1UL << OPAMP1_CSR_FORCEVP_Pos)    /*!< 0x00000002 */

+#define OPAMP1_CSR_FORCEVP                OPAMP1_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */

+

+#define OPAMP1_CSR_VPSEL_Pos              (2U)

+#define OPAMP1_CSR_VPSEL_Msk              (0x3UL << OPAMP1_CSR_VPSEL_Pos)      /*!< 0x0000000C */

+#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */

+#define OPAMP1_CSR_VPSEL_0                (0x1UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000004 */

+#define OPAMP1_CSR_VPSEL_1                (0x2UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000008 */

+

+#define OPAMP1_CSR_VMSEL_Pos              (5U)

+#define OPAMP1_CSR_VMSEL_Msk              (0x3UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000060 */

+#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */

+#define OPAMP1_CSR_VMSEL_0                (0x1UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000020 */

+#define OPAMP1_CSR_VMSEL_1                (0x2UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000040 */

+

+#define OPAMP1_CSR_OPAHSM_Pos             (8U)

+#define OPAMP1_CSR_OPAHSM_Msk             (0x1UL << OPAMP1_CSR_OPAHSM_Pos)     /*!< 0x00000100 */

+#define OPAMP1_CSR_OPAHSM                 OPAMP1_CSR_OPAHSM_Msk                /*!< Operational amplifier1 high speed mode */

+#define OPAMP1_CSR_CALON_Pos              (11U)

+#define OPAMP1_CSR_CALON_Msk              (0x1UL << OPAMP1_CSR_CALON_Pos)      /*!< 0x00000800 */

+#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */

+

+#define OPAMP1_CSR_CALSEL_Pos             (12U)

+#define OPAMP1_CSR_CALSEL_Msk             (0x3UL << OPAMP1_CSR_CALSEL_Pos)     /*!< 0x00003000 */

+#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */

+#define OPAMP1_CSR_CALSEL_0               (0x1UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00001000 */

+#define OPAMP1_CSR_CALSEL_1               (0x2UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */

+

+#define OPAMP1_CSR_PGGAIN_Pos             (14U)

+#define OPAMP1_CSR_PGGAIN_Msk             (0xFUL << OPAMP1_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */

+#define OPAMP1_CSR_PGGAIN                 OPAMP1_CSR_PGGAIN_Msk                /*!< Operational amplifier1 Programmable amplifier gain value */

+#define OPAMP1_CSR_PGGAIN_0               (0x1UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00004000 */

+#define OPAMP1_CSR_PGGAIN_1               (0x2UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00008000 */

+#define OPAMP1_CSR_PGGAIN_2               (0x4UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00010000 */

+#define OPAMP1_CSR_PGGAIN_3               (0x8UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00020000 */

+

+#define OPAMP1_CSR_USERTRIM_Pos           (18U)

+#define OPAMP1_CSR_USERTRIM_Msk           (0x1UL << OPAMP1_CSR_USERTRIM_Pos)   /*!< 0x00040000 */

+#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */

+#define OPAMP1_CSR_TSTREF_Pos             (29U)

+#define OPAMP1_CSR_TSTREF_Msk             (0x1UL << OPAMP1_CSR_TSTREF_Pos)     /*!< 0x20000000 */

+#define OPAMP1_CSR_TSTREF                 OPAMP1_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */

+#define OPAMP1_CSR_CALOUT_Pos             (30U)

+#define OPAMP1_CSR_CALOUT_Msk             (0x1UL << OPAMP1_CSR_CALOUT_Pos)     /*!< 0x40000000 */

+#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */

+

+/*********************  Bit definition for OPAMP2_CSR register  ***************/

+#define OPAMP2_CSR_OPAEN_Pos              (0U)

+#define OPAMP2_CSR_OPAEN_Msk              (0x1UL << OPAMP2_CSR_OPAEN_Pos)      /*!< 0x00000001 */

+#define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */

+#define OPAMP2_CSR_FORCEVP_Pos            (1U)

+#define OPAMP2_CSR_FORCEVP_Msk            (0x1UL << OPAMP2_CSR_FORCEVP_Pos)    /*!< 0x00000002 */

+#define OPAMP2_CSR_FORCEVP                OPAMP2_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */

+

+#define OPAMP2_CSR_VPSEL_Pos              (2U)

+#define OPAMP2_CSR_VPSEL_Msk              (0x3UL << OPAMP2_CSR_VPSEL_Pos)      /*!< 0x0000000C */

+#define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */

+#define OPAMP2_CSR_VPSEL_0                (0x1UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000004 */

+#define OPAMP2_CSR_VPSEL_1                (0x2UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000008 */

+

+#define OPAMP2_CSR_VMSEL_Pos              (5U)

+#define OPAMP2_CSR_VMSEL_Msk              (0x3UL << OPAMP2_CSR_VMSEL_Pos)      /*!< 0x00000060 */

+#define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */

+#define OPAMP2_CSR_VMSEL_0                (0x1UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000020 */

+#define OPAMP2_CSR_VMSEL_1                (0x2UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000040 */

+

+#define OPAMP2_CSR_OPAHSM_Pos             (8U)

+#define OPAMP2_CSR_OPAHSM_Msk             (0x1UL << OPAMP2_CSR_OPAHSM_Pos)     /*!< 0x00000100 */

+#define OPAMP2_CSR_OPAHSM                 OPAMP2_CSR_OPAHSM_Msk                /*!< Operational amplifier2 high speed mode */

+#define OPAMP2_CSR_CALON_Pos              (11U)

+#define OPAMP2_CSR_CALON_Msk              (0x1UL << OPAMP2_CSR_CALON_Pos)      /*!< 0x00000800 */

+#define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */

+

+#define OPAMP2_CSR_CALSEL_Pos             (12U)

+#define OPAMP2_CSR_CALSEL_Msk             (0x3UL << OPAMP2_CSR_CALSEL_Pos)     /*!< 0x00003000 */

+#define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */

+#define OPAMP2_CSR_CALSEL_0               (0x1UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00001000 */

+#define OPAMP2_CSR_CALSEL_1               (0x2UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */

+

+#define OPAMP2_CSR_PGGAIN_Pos             (14U)

+#define OPAMP2_CSR_PGGAIN_Msk             (0xFUL << OPAMP2_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */

+#define OPAMP2_CSR_PGGAIN                 OPAMP2_CSR_PGGAIN_Msk                /*!< Operational amplifier2 Programmable amplifier gain value */

+#define OPAMP2_CSR_PGGAIN_0               (0x1UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00004000 */

+#define OPAMP2_CSR_PGGAIN_1               (0x2UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00008000 */

+#define OPAMP2_CSR_PGGAIN_2               (0x4UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00010000 */

+#define OPAMP2_CSR_PGGAIN_3               (0x8UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00020000 */

+

+#define OPAMP2_CSR_USERTRIM_Pos           (18U)

+#define OPAMP2_CSR_USERTRIM_Msk           (0x1UL << OPAMP2_CSR_USERTRIM_Pos)   /*!< 0x00040000 */

+#define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */

+#define OPAMP2_CSR_TSTREF_Pos             (29U)

+#define OPAMP2_CSR_TSTREF_Msk             (0x1UL << OPAMP2_CSR_TSTREF_Pos)     /*!< 0x20000000 */

+#define OPAMP2_CSR_TSTREF                 OPAMP2_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */

+#define OPAMP2_CSR_CALOUT_Pos             (30U)

+#define OPAMP2_CSR_CALOUT_Msk             (0x1UL << OPAMP2_CSR_CALOUT_Pos)     /*!< 0x40000000 */

+#define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */

+

+/*******************  Bit definition for OPAMP_OTR register  ******************/

+#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */

+#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP1_OTR register  ******************/

+#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */

+#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP2_OTR register  ******************/

+#define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */

+#define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP_HSOTR register  ****************/

+#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP_HSOTR_TRIMHSOFFSETN        OPAMP_HSOTR_TRIMHSOFFSETN_Msk         /*!< Trim for NMOS differential pairs */

+#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP_HSOTR_TRIMHSOFFSETP        OPAMP_HSOTR_TRIMHSOFFSETP_Msk         /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP1_HSOTR register  ****************/

+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP1_HSOTR_TRIMHSOFFSETN        OPAMP1_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */

+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP1_HSOTR_TRIMHSOFFSETP        OPAMP1_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP2_HSOTR register  ****************/

+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP2_HSOTR_TRIMHSOFFSETN        OPAMP2_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */

+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP2_HSOTR_TRIMHSOFFSETP        OPAMP2_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */

+

+/******************************************************************************/

+/*                                                                            */

+/*                Parallel Synchronous Slave Interface (PSSI )                */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for PSSI_CR register  *******************/

+#define PSSI_CR_OUTEN_Pos               (31U)

+#define PSSI_CR_OUTEN_Msk               (0x1UL << PSSI_CR_OUTEN_Pos)           /*!< 0x80000000 */

+#define PSSI_CR_OUTEN                   PSSI_CR_OUTEN_Msk                      /*!< Data direction selection */

+#define PSSI_CR_DMAEN_Pos               (30U)

+#define PSSI_CR_DMAEN_Msk               (0x1UL << PSSI_CR_DMAEN_Pos)           /*!< 0x40000000 */

+#define PSSI_CR_DMAEN                   PSSI_CR_DMAEN_Msk                      /*!< DMA enable */

+#define PSSI_CR_DERDYCFG_Pos            (18U)

+#define PSSI_CR_DERDYCFG_Msk            (0x7UL << PSSI_CR_DERDYCFG_Pos)        /*!< 0x001C0000 */

+#define PSSI_CR_DERDYCFG                PSSI_CR_DERDYCFG_Msk                   /*!< Data enable and ready configuration */

+#define PSSI_CR_ENABLE_Pos              (14U)

+#define PSSI_CR_ENABLE_Msk              (0x1UL << PSSI_CR_ENABLE_Pos)          /*!< 0x00004000 */

+#define PSSI_CR_ENABLE                  PSSI_CR_ENABLE_Msk                     /*!< PSSI enable */

+#define PSSI_CR_EDM_Pos                 (10U)

+#define PSSI_CR_EDM_Msk                 (0x3UL << PSSI_CR_EDM_Pos)             /*!< 0x00000C00 */

+#define PSSI_CR_EDM                     PSSI_CR_EDM_Msk                        /*!< Extended data mode */

+#define PSSI_CR_RDYPOL_Pos              (8U)

+#define PSSI_CR_RDYPOL_Msk              (0x1UL << PSSI_CR_RDYPOL_Pos)          /*!< 0x00000C00 */

+#define PSSI_CR_RDYPOL                  PSSI_CR_RDYPOL_Msk                     /*!< Ready polarity */

+#define PSSI_CR_DEPOL_Pos               (6U)

+#define PSSI_CR_DEPOL_Msk               (0x1UL << PSSI_CR_DEPOL_Pos)           /*!< 0x00000C00 */

+#define PSSI_CR_DEPOL                   PSSI_CR_DEPOL_Msk                      /*!<  Data enable polarity */

+#define PSSI_CR_CKPOL_Pos               (5U)

+#define PSSI_CR_CKPOL_Msk               (0x1UL << PSSI_CR_CKPOL_Pos)           /*!< 0x00000C00 */

+#define PSSI_CR_CKPOL                   PSSI_CR_CKPOL_Msk                      /*!< Parallel data clock polarity */

+/********************  Bit definition for PSSI_SR register  *******************/

+#define PSSI_SR_RTT1B_Pos               (3U)

+#define PSSI_SR_RTT1B_Msk               (0x1UL << PSSI_SR_RTT1B_Pos)           /*!< 0x00000008 */

+#define PSSI_SR_RTT1B                   PSSI_SR_RTT1B_Msk                      /*!< Ready to transfer one byte */

+#define PSSI_SR_RTT4B_Pos               (2U)

+#define PSSI_SR_RTT4B_Msk               (0x1UL << PSSI_SR_RTT4B_Pos)           /*!< 0x00000004 */

+#define PSSI_SR_RTT4B                   PSSI_SR_RTT4B_Msk                      /*!< Ready to transfer four bytes */

+/********************  Bit definition for PSSI_RIS register  *******************/

+#define PSSI_RIS_OVR_RIS_Pos            (1U)

+#define PSSI_RIS_OVR_RIS_Msk            (0x1UL << PSSI_RIS_OVR_RIS_Pos)        /*!< 0x00000002 */

+#define PSSI_RIS_OVR_RIS                PSSI_RIS_OVR_RIS_Msk                   /*!< Data buffer overrun/underrun raw interrupt status */

+/********************  Bit definition for PSSI_IER register  *******************/

+#define PSSI_IER_OVR_IE_Pos             (1U)

+#define PSSI_IER_OVR_IE_Msk             (0x1UL << PSSI_IER_OVR_IE_Pos)         /*!< 0x00000002 */

+#define PSSI_IER_OVR_IE                 PSSI_IER_OVR_IE_Msk                    /*!< Data buffer overrun/underrun interrupt enable */

+/********************  Bit definition for PSSI_MIS register  *******************/

+#define PSSI_MIS_OVR_MIS_Pos            (1U)

+#define PSSI_MIS_OVR_MIS_Msk            (0x1UL << PSSI_MIS_OVR_MIS_Pos)        /*!< 0x00000002 */

+#define PSSI_MIS_OVR_MIS                PSSI_MIS_OVR_MIS_Msk                   /*!< Data buffer overrun/underrun masked interrupt status */

+/********************  Bit definition for PSSI_ICR register  *******************/

+#define PSSI_ICR_OVR_ISC_Pos            (1U)

+#define PSSI_ICR_OVR_ISC_Msk            (0x1UL << PSSI_ICR_OVR_ISC_Pos)        /*!< 0x00000002 */

+#define PSSI_ICR_OVR_ISC                PSSI_ICR_OVR_ISC_Msk                   /*!< Data buffer overrun/underrun interrupt status clear */

+/********************  Bit definition for PSSI_DR register  *******************/

+#define PSSI_DR_DR_Pos                  (0U)

+#define PSSI_DR_DR_Msk                  (0xFFFFFFFFUL << PSSI_DR_DR_Pos)       /*!< 0xFFFFFFF */

+#define PSSI_DR_DR                      PSSI_DR_DR_Msk                         /*!< Data register  */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             Power Control                                  */

+/*                                                                            */

+/******************************************************************************/

+/*************************  NUMBER OF POWER DOMAINS  **************************/

+#define POWER_DOMAINS_NUMBER           2U                                      /*!< 2 Domains */

+

+/********************  Bit definition for PWR_CR1 register  *******************/

+#define PWR_CR1_SRDRAMSO_Pos           (27U)

+#define PWR_CR1_SRDRAMSO_Msk           (0x1UL << PWR_CR1_SRDRAMSO_Pos)         /*!< 0x08000000 */

+#define PWR_CR1_SRDRAMSO               PWR_CR1_SRDRAMSO_Msk                    /*!< SmartRun Domain AHB Memory Shut-Off in DStop/DStop2 Low-Power Mode */

+#define PWR_CR1_HSITFSO_Pos            (26U)

+#define PWR_CR1_HSITFSO_Msk            (0x1UL << PWR_CR1_HSITFSO_Pos)          /*!< 0x04000000 */

+#define PWR_CR1_HSITFSO                PWR_CR1_HSITFSO_Msk                     /*!< High-Speed Interfaces USB and FDCAN Memories Shut-off in DStop/DStop2 Mode */

+#define PWR_CR1_GFXSO_Pos              (25U)

+#define PWR_CR1_GFXSO_Msk              (0x1UL << PWR_CR1_GFXSO_Pos)            /*!< 0x02000000 */

+#define PWR_CR1_GFXSO                  PWR_CR1_GFXSO_Msk                       /*!< GFXMMU and JPEG Memories Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_ITCMSO_Pos             (24U)

+#define PWR_CR1_ITCMSO_Msk             (0x1UL << PWR_CR1_ITCMSO_Pos)           /*!< 0x01000000 */

+#define PWR_CR1_ITCMSO                 PWR_CR1_ITCMSO_Msk                      /*!< Instruction TCM and ETM Memories Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_AHBRAM2SO_Pos          (23U)

+#define PWR_CR1_AHBRAM2SO_Msk          (0x1UL << PWR_CR1_AHBRAM2SO_Pos)        /*!< 0x00800000 */

+#define PWR_CR1_AHBRAM2SO              PWR_CR1_AHBRAM2SO_Msk                   /*!< AHB RAM2 Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_AHBRAM1SO_Pos          (22U)

+#define PWR_CR1_AHBRAM1SO_Msk          (0x1UL << PWR_CR1_AHBRAM1SO_Pos)        /*!< 0x00400000 */

+#define PWR_CR1_AHBRAM1SO              PWR_CR1_AHBRAM1SO_Msk                   /*!< AHB RAM1 Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_AXIRAM3SO_Pos          (21U)

+#define PWR_CR1_AXIRAM3SO_Msk          (0x1UL << PWR_CR1_AXIRAM3SO_Pos)        /*!< 0x00200000 */

+#define PWR_CR1_AXIRAM3SO              PWR_CR1_AXIRAM3SO_Msk                   /*!< AXI RAM3 Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_AXIRAM2SO_Pos          (20U)

+#define PWR_CR1_AXIRAM2SO_Msk          (0x1UL << PWR_CR1_AXIRAM2SO_Pos)        /*!< 0x00100000 */

+#define PWR_CR1_AXIRAM2SO              PWR_CR1_AXIRAM2SO_Msk                   /*!< AXI RAM2 Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_AXIRAM1SO_Pos          (19U)

+#define PWR_CR1_AXIRAM1SO_Msk          (0x1UL << PWR_CR1_AXIRAM1SO_Pos)        /*!< 0x00080000 */

+#define PWR_CR1_AXIRAM1SO              PWR_CR1_AXIRAM1SO_Msk                   /*!< AXI RAM1 Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_ALS_Pos                (17U)

+#define PWR_CR1_ALS_Msk                (0x3UL << PWR_CR1_ALS_Pos)              /*!< 0x00060000 */

+#define PWR_CR1_ALS                    PWR_CR1_ALS_Msk                         /*!< Analog Voltage Detector level selection */

+#define PWR_CR1_ALS_0                  (0x1UL << PWR_CR1_ALS_Pos)              /*!< 0x00020000 */

+#define PWR_CR1_ALS_1                  (0x2UL << PWR_CR1_ALS_Pos)              /*!< 0x00040000 */

+#define PWR_CR1_AVDEN_Pos              (16U)

+#define PWR_CR1_AVDEN_Msk              (0x1UL << PWR_CR1_AVDEN_Pos)            /*!< 0x00010000 */

+#define PWR_CR1_AVDEN                  PWR_CR1_AVDEN_Msk                       /*!< Analog Voltage Detector Enable */

+#define PWR_CR1_SVOS_Pos               (14U)

+#define PWR_CR1_SVOS_Msk               (0x3UL << PWR_CR1_SVOS_Pos)             /*!< 0x0000C000 */

+#define PWR_CR1_SVOS                   PWR_CR1_SVOS_Msk                        /*!< System STOP mode Voltage Scaling selection */

+#define PWR_CR1_SVOS_0                 (0x1UL << PWR_CR1_SVOS_Pos)             /*!< 0x00004000 */

+#define PWR_CR1_SVOS_1                 (0x2UL << PWR_CR1_SVOS_Pos)             /*!< 0x00008000 */

+#define PWR_CR1_AVD_READY_Pos          (13U)

+#define PWR_CR1_AVD_READY_Msk          (0x1UL << PWR_CR1_AVD_READY_Pos)        /*!< 0x00002000 */

+#define PWR_CR1_AVD_READY              PWR_CR1_AVD_READY_Msk                   /*!< Analog Voltage Ready. */

+#define PWR_CR1_BOOSTE_Pos             (12U)

+#define PWR_CR1_BOOSTE_Msk             (0x1UL << PWR_CR1_BOOSTE_Pos)           /*!< 0x00001000 */

+#define PWR_CR1_BOOSTE                 PWR_CR1_BOOSTE_Msk                      /*!< Analog Switch VBoost control */

+#define PWR_CR1_FLPS_Pos               (9U)

+#define PWR_CR1_FLPS_Msk               (0x1UL << PWR_CR1_FLPS_Pos)             /*!< 0x00000200 */

+#define PWR_CR1_FLPS                   PWR_CR1_FLPS_Msk                        /*!< Flash low power mode in DSTOP */

+#define PWR_CR1_DBP_Pos                (8U)

+#define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */

+#define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable Back-up domain Protection */

+#define PWR_CR1_PLS_Pos                (5U)

+#define PWR_CR1_PLS_Msk                (0x7UL << PWR_CR1_PLS_Pos)              /*!< 0x000000E0 */

+#define PWR_CR1_PLS                    PWR_CR1_PLS_Msk                         /*!< Programmable Voltage Detector level selection */

+#define PWR_CR1_PLS_0                  (0x1UL << PWR_CR1_PLS_Pos)              /*!< 0x00000020 */

+#define PWR_CR1_PLS_1                  (0x2UL << PWR_CR1_PLS_Pos)              /*!< 0x00000040 */

+#define PWR_CR1_PLS_2                  (0x4UL << PWR_CR1_PLS_Pos)              /*!< 0x00000080 */

+#define PWR_CR1_PVDEN_Pos              (4U)

+#define PWR_CR1_PVDEN_Msk              (0x1UL << PWR_CR1_PVDEN_Pos)            /*!< 0x00000010 */

+#define PWR_CR1_PVDEN                  PWR_CR1_PVDEN_Msk                       /*!< Programmable Voltage detector enable */

+#define PWR_CR1_LPDS_Pos               (0U)

+#define PWR_CR1_LPDS_Msk               (0x1UL << PWR_CR1_LPDS_Pos)             /*!< 0x00000001 */

+#define PWR_CR1_LPDS                   PWR_CR1_LPDS_Msk                        /*!< Low Power Deepsleep with SVOS3 */

+

+/*!< PVD level configuration */

+#define PWR_CR1_PLS_LEV0               (0UL)                                   /*!< PVD level 0 */

+#define PWR_CR1_PLS_LEV1_Pos           (5U)

+#define PWR_CR1_PLS_LEV1_Msk           (0x1UL << PWR_CR1_PLS_LEV1_Pos)         /*!< 0x00000020 */

+#define PWR_CR1_PLS_LEV1               PWR_CR1_PLS_LEV1_Msk                    /*!< PVD level 1 */

+#define PWR_CR1_PLS_LEV2_Pos           (6U)

+#define PWR_CR1_PLS_LEV2_Msk           (0x1UL << PWR_CR1_PLS_LEV2_Pos)         /*!< 0x00000040 */

+#define PWR_CR1_PLS_LEV2               PWR_CR1_PLS_LEV2_Msk                    /*!< PVD level 2 */

+#define PWR_CR1_PLS_LEV3_Pos           (5U)

+#define PWR_CR1_PLS_LEV3_Msk           (0x3UL << PWR_CR1_PLS_LEV3_Pos)         /*!< 0x00000060 */

+#define PWR_CR1_PLS_LEV3               PWR_CR1_PLS_LEV3_Msk                    /*!< PVD level 3 */

+#define PWR_CR1_PLS_LEV4_Pos           (7U)

+#define PWR_CR1_PLS_LEV4_Msk           (0x1UL << PWR_CR1_PLS_LEV4_Pos)         /*!< 0x00000080 */

+#define PWR_CR1_PLS_LEV4               PWR_CR1_PLS_LEV4_Msk                    /*!< PVD level 4 */

+#define PWR_CR1_PLS_LEV5_Pos           (5U)

+#define PWR_CR1_PLS_LEV5_Msk           (0x5UL << PWR_CR1_PLS_LEV5_Pos)         /*!< 0x000000A0 */

+#define PWR_CR1_PLS_LEV5               PWR_CR1_PLS_LEV5_Msk                    /*!< PVD level 5 */

+#define PWR_CR1_PLS_LEV6_Pos           (6U)

+#define PWR_CR1_PLS_LEV6_Msk           (0x3UL << PWR_CR1_PLS_LEV6_Pos)         /*!< 0x000000C0 */

+#define PWR_CR1_PLS_LEV6               PWR_CR1_PLS_LEV6_Msk                    /*!< PVD level 6 */

+#define PWR_CR1_PLS_LEV7_Pos           (5U)

+#define PWR_CR1_PLS_LEV7_Msk           (0x7UL << PWR_CR1_PLS_LEV7_Pos)         /*!< 0x000000E0 */

+#define PWR_CR1_PLS_LEV7               PWR_CR1_PLS_LEV7_Msk                    /*!< PVD level 7 */

+

+/*!< AVD level configuration */

+#define PWR_CR1_ALS_LEV0               (0UL)                                   /*!< AVD level 0 */

+#define PWR_CR1_ALS_LEV1_Pos           (17U)

+#define PWR_CR1_ALS_LEV1_Msk           (0x1UL << PWR_CR1_ALS_LEV1_Pos)         /*!< 0x00020000 */

+#define PWR_CR1_ALS_LEV1               PWR_CR1_ALS_LEV1_Msk                    /*!< AVD level 1 */

+#define PWR_CR1_ALS_LEV2_Pos           (18U)

+#define PWR_CR1_ALS_LEV2_Msk           (0x1UL << PWR_CR1_ALS_LEV2_Pos)         /*!< 0x00040000 */

+#define PWR_CR1_ALS_LEV2               PWR_CR1_ALS_LEV2_Msk                    /*!< AVD level 2 */

+#define PWR_CR1_ALS_LEV3_Pos           (17U)

+#define PWR_CR1_ALS_LEV3_Msk           (0x3UL << PWR_CR1_ALS_LEV3_Pos)         /*!< 0x00060000 */

+#define PWR_CR1_ALS_LEV3               PWR_CR1_ALS_LEV3_Msk                    /*!< AVD level 3 */

+

+/********************  Bit definition for PWR_CSR1 register  ******************/

+#define PWR_CSR1_MMCVDO_Pos            (17U)

+#define PWR_CSR1_MMCVDO_Msk            (0x1UL << PWR_CSR1_MMCVDO_Pos)          /*!< 0x00020000                        */

+#define PWR_CSR1_MMCVDO                PWR_CSR1_MMCVDO_Msk                     /*!< voltage detector output on VDDMMC */

+#define PWR_CSR1_AVDO_Pos              (16U)

+#define PWR_CSR1_AVDO_Msk              (0x1UL << PWR_CSR1_AVDO_Pos)            /*!< 0x00010000 */

+#define PWR_CSR1_AVDO                  PWR_CSR1_AVDO_Msk                       /*!< Analog Voltage Detect Output */

+#define PWR_CSR1_ACTVOS_Pos            (14U)

+#define PWR_CSR1_ACTVOS_Msk            (0x3UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x0000C000 */

+#define PWR_CSR1_ACTVOS                PWR_CSR1_ACTVOS_Msk                     /*!< Current actual used VOS for VDD11 Voltage Scaling */

+#define PWR_CSR1_ACTVOS_0              (0x1UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00004000 */

+#define PWR_CSR1_ACTVOS_1              (0x2UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00008000 */

+#define PWR_CSR1_ACTVOSRDY_Pos         (13U)

+#define PWR_CSR1_ACTVOSRDY_Msk         (0x1UL << PWR_CSR1_ACTVOSRDY_Pos)       /*!< 0x00002000 */

+#define PWR_CSR1_ACTVOSRDY             PWR_CSR1_ACTVOSRDY_Msk                  /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling  */

+#define PWR_CSR1_PVDO_Pos              (4U)

+#define PWR_CSR1_PVDO_Msk              (0x1UL << PWR_CSR1_PVDO_Pos)            /*!< 0x00000010 */

+#define PWR_CSR1_PVDO                  PWR_CSR1_PVDO_Msk                       /*!< Programmable Voltage Detect Output */

+

+/********************  Bit definition for PWR_CR2 register  *******************/

+#define PWR_CR2_TEMPH_Pos              (23U)

+#define PWR_CR2_TEMPH_Msk              (0x1UL << PWR_CR2_TEMPH_Pos)            /*!< 0x00800000 */

+#define PWR_CR2_TEMPH                  PWR_CR2_TEMPH_Msk                       /*!< Monitored temperature level above high threshold */

+#define PWR_CR2_TEMPL_Pos              (22U)

+#define PWR_CR2_TEMPL_Msk              (0x1UL << PWR_CR2_TEMPL_Pos)            /*!< 0x00400000 */

+#define PWR_CR2_TEMPL                  PWR_CR2_TEMPL_Msk                       /*!< Monitored temperature level above low threshold */

+#define PWR_CR2_VBATH_Pos              (21U)

+#define PWR_CR2_VBATH_Msk              (0x1UL << PWR_CR2_VBATH_Pos)            /*!< 0x00200000 */

+#define PWR_CR2_VBATH                  PWR_CR2_VBATH_Msk                       /*!< Monitored VBAT level above high threshold */

+#define PWR_CR2_VBATL_Pos              (20U)

+#define PWR_CR2_VBATL_Msk              (0x1UL << PWR_CR2_VBATL_Pos)            /*!< 0x00100000 */

+#define PWR_CR2_VBATL                  PWR_CR2_VBATL_Msk                       /*!< Monitored VBAT level above low threshold */

+#define PWR_CR2_BRRDY_Pos              (16U)

+#define PWR_CR2_BRRDY_Msk              (0x1UL << PWR_CR2_BRRDY_Pos)            /*!< 0x00010000 */

+#define PWR_CR2_BRRDY                  PWR_CR2_BRRDY_Msk                       /*!< Backup regulator ready */

+#define PWR_CR2_MONEN_Pos              (4U)

+#define PWR_CR2_MONEN_Msk              (0x1UL << PWR_CR2_MONEN_Pos)            /*!< 0x00000010 */

+#define PWR_CR2_MONEN                  PWR_CR2_MONEN_Msk                       /*!< VBAT and temperature monitoring enable */

+#define PWR_CR2_BREN_Pos               (0U)

+#define PWR_CR2_BREN_Msk               (0x1UL << PWR_CR2_BREN_Pos)             /*!< 0x00000001 */

+#define PWR_CR2_BREN                   PWR_CR2_BREN_Msk                        /*!< Backup regulator enable */

+

+/********************  Bit definition for PWR_CR3 register  *******************/

+#define PWR_CR3_USB33RDY_Pos           (26U)

+#define PWR_CR3_USB33RDY_Msk           (0x1UL << PWR_CR3_USB33RDY_Pos)         /*!< 0x04000000 */

+#define PWR_CR3_USB33RDY               PWR_CR3_USB33RDY_Msk                    /*!< USB supply ready */

+#define PWR_CR3_USBREGEN_Pos           (25U)

+#define PWR_CR3_USBREGEN_Msk           (0x1UL << PWR_CR3_USBREGEN_Pos)         /*!< 0x02000000 */

+#define PWR_CR3_USBREGEN               PWR_CR3_USBREGEN_Msk                    /*!< USB regulator enable */

+#define PWR_CR3_USB33DEN_Pos           (24U)

+#define PWR_CR3_USB33DEN_Msk           (0x1UL << PWR_CR3_USB33DEN_Pos)         /*!< 0x01000000 */

+#define PWR_CR3_USB33DEN               PWR_CR3_USB33DEN_Msk                    /*!< VDD33_USB voltage level detector enable */

+#define PWR_CR3_SMPSEXTRDY_Pos         (16U)

+#define PWR_CR3_SMPSEXTRDY_Msk         (0x1UL << PWR_CR3_SMPSEXTRDY_Pos)       /*!< 0x00010000 */

+#define PWR_CR3_SMPSEXTRDY             PWR_CR3_SMPSEXTRDY_Msk                  /*!< SMPS External supply ready */

+#define PWR_CR3_VBRS_Pos               (9U)

+#define PWR_CR3_VBRS_Msk               (0x1UL << PWR_CR3_VBRS_Pos)             /*!< 0x00000200 */

+#define PWR_CR3_VBRS                   PWR_CR3_VBRS_Msk                        /*!< VBAT charging resistor selection */

+#define PWR_CR3_VBE_Pos                (8U)

+#define PWR_CR3_VBE_Msk                (0x1UL << PWR_CR3_VBE_Pos)              /*!< 0x00000100 */

+#define PWR_CR3_VBE                    PWR_CR3_VBE_Msk                         /*!< VBAT charging enable */

+#define PWR_CR3_SMPSLEVEL_Pos          (4U)

+#define PWR_CR3_SMPSLEVEL_Msk          (0x3UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000030 */

+#define PWR_CR3_SMPSLEVEL              PWR_CR3_SMPSLEVEL_Msk                   /*!< SMPS output Voltage */

+#define PWR_CR3_SMPSLEVEL_0            (0x1UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000010 */

+#define PWR_CR3_SMPSLEVEL_1            (0x2UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000020 */

+#define PWR_CR3_SMPSEXTHP_Pos          (3U)

+#define PWR_CR3_SMPSEXTHP_Msk          (0x1UL << PWR_CR3_SMPSEXTHP_Pos)        /*!< 0x00000008 */

+#define PWR_CR3_SMPSEXTHP              PWR_CR3_SMPSEXTHP_Msk                   /*!< SMPS forced ON and in High Power MR mode */

+#define PWR_CR3_SMPSEN_Pos             (2U)

+#define PWR_CR3_SMPSEN_Msk             (0x1UL << PWR_CR3_SMPSEN_Pos)           /*!< 0x00000004 */

+#define PWR_CR3_SMPSEN                 PWR_CR3_SMPSEN_Msk                      /*!< SMPS Enable */

+#define PWR_CR3_LDOEN_Pos              (1U)

+#define PWR_CR3_LDOEN_Msk              (0x1UL << PWR_CR3_LDOEN_Pos)            /*!< 0x00000002 */

+#define PWR_CR3_LDOEN                  PWR_CR3_LDOEN_Msk                       /*!< Low Drop Output regulator enable */

+#define PWR_CR3_BYPASS_Pos             (0U)

+#define PWR_CR3_BYPASS_Msk             (0x1UL << PWR_CR3_BYPASS_Pos)           /*!< 0x00000001 */

+#define PWR_CR3_BYPASS                 PWR_CR3_BYPASS_Msk                      /*!< Power Management Unit bypass */

+

+/********************  Bit definition for PWR_CPUCR register  *****************/

+#define PWR_CPUCR_RUN_SRD_Pos          (11U)

+#define PWR_CPUCR_RUN_SRD_Msk          (0x1UL << PWR_CPUCR_RUN_SRD_Pos)        /*!< 0x00000800 */

+#define PWR_CPUCR_RUN_SRD              PWR_CPUCR_RUN_SRD_Msk                   /*!< Keep system SRD domain in RUN mode regardless of the CPU sub-systems modes */

+#define PWR_CPUCR_CSSF_Pos             (9U)

+#define PWR_CPUCR_CSSF_Msk             (0x1UL << PWR_CPUCR_CSSF_Pos)           /*!< 0x00000200 */

+#define PWR_CPUCR_CSSF                 PWR_CPUCR_CSSF_Msk                      /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */

+#define PWR_CPUCR_SBF_Pos              (6U)

+#define PWR_CPUCR_SBF_Msk              (0x1UL << PWR_CPUCR_SBF_Pos)            /*!< 0x00000040 */

+#define PWR_CPUCR_SBF                  PWR_CPUCR_SBF_Msk                       /*!< System STANDBY Flag */

+#define PWR_CPUCR_STOPF_Pos            (5U)

+#define PWR_CPUCR_STOPF_Msk            (0x1UL << PWR_CPUCR_STOPF_Pos)          /*!< 0x00000020 */

+#define PWR_CPUCR_STOPF                PWR_CPUCR_STOPF_Msk                     /*!< STOP Flag */

+#define PWR_CPUCR_PDDS_SRD_Pos         (2U)

+#define PWR_CPUCR_PDDS_SRD_Msk         (0x1UL << PWR_CPUCR_PDDS_SRD_Pos)       /*!< 0x00000004 */

+#define PWR_CPUCR_PDDS_SRD             PWR_CPUCR_PDDS_SRD_Msk                  /*!< System SRD domain Power Down Deepsleep */

+#define PWR_CPUCR_RETDS_CD_Pos         (0U)

+#define PWR_CPUCR_RETDS_CD_Msk         (0x1UL << PWR_CPUCR_RETDS_CD_Pos)       /*!< 0x00000001 */

+#define PWR_CPUCR_RETDS_CD             PWR_CPUCR_RETDS_CD_Msk                  /*!< CD domain Power Down Deepsleep selection */

+/********************  Bit definition for PWR_SRDCR register  *****************/

+#define PWR_SRDCR_VOS_Pos              (14U)

+#define PWR_SRDCR_VOS_Msk              (0x3UL << PWR_SRDCR_VOS_Pos)             /*!< 0x0000C000 */

+#define PWR_SRDCR_VOS                  PWR_SRDCR_VOS_Msk                        /*!< Voltage Scaling selection according performance */

+#define PWR_SRDCR_VOS_0                (0x1UL << PWR_SRDCR_VOS_Pos)             /*!< 0x00004000 */

+#define PWR_SRDCR_VOS_1                (0x2UL << PWR_SRDCR_VOS_Pos)             /*!< 0x00008000 */

+#define PWR_SRDCR_VOSRDY_Pos           (13U)

+#define PWR_SRDCR_VOSRDY_Msk           (0x1UL << PWR_SRDCR_VOSRDY_Pos)          /*!< 0x00002000 */

+#define PWR_SRDCR_VOSRDY               PWR_SRDCR_VOSRDY_Msk                     /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */

+/******************  Bit definition for PWR_WKUPCR register  ******************/

+#define PWR_WKUPCR_WKUPC6_Pos          (5U)

+#define PWR_WKUPCR_WKUPC6_Msk          (0x1UL << PWR_WKUPCR_WKUPC6_Pos)        /*!< 0x00000020 */

+#define PWR_WKUPCR_WKUPC6              PWR_WKUPCR_WKUPC6_Msk                   /*!< Clear Wakeup Pin Flag 6 */

+#define PWR_WKUPCR_WKUPC5_Pos          (4U)

+#define PWR_WKUPCR_WKUPC5_Msk          (0x1UL << PWR_WKUPCR_WKUPC5_Pos)        /*!< 0x00000010 */

+#define PWR_WKUPCR_WKUPC5              PWR_WKUPCR_WKUPC5_Msk                   /*!< Clear Wakeup Pin Flag 5 */

+#define PWR_WKUPCR_WKUPC4_Pos          (3U)

+#define PWR_WKUPCR_WKUPC4_Msk          (0x1UL << PWR_WKUPCR_WKUPC4_Pos)        /*!< 0x00000008 */

+#define PWR_WKUPCR_WKUPC4              PWR_WKUPCR_WKUPC4_Msk                   /*!< Clear Wakeup Pin Flag 4 */

+#define PWR_WKUPCR_WKUPC3_Pos          (2U)

+#define PWR_WKUPCR_WKUPC3_Msk          (0x1UL << PWR_WKUPCR_WKUPC3_Pos)        /*!< 0x00000004 */

+#define PWR_WKUPCR_WKUPC3              PWR_WKUPCR_WKUPC3_Msk                   /*!< Clear Wakeup Pin Flag 3 */

+#define PWR_WKUPCR_WKUPC2_Pos          (1U)

+#define PWR_WKUPCR_WKUPC2_Msk          (0x1UL << PWR_WKUPCR_WKUPC2_Pos)        /*!< 0x00000002 */

+#define PWR_WKUPCR_WKUPC2              PWR_WKUPCR_WKUPC2_Msk                   /*!< Clear Wakeup Pin Flag 2 */

+#define PWR_WKUPCR_WKUPC1_Pos          (0U)

+#define PWR_WKUPCR_WKUPC1_Msk          (0x1UL << PWR_WKUPCR_WKUPC1_Pos)        /*!< 0x00000001 */

+#define PWR_WKUPCR_WKUPC1              PWR_WKUPCR_WKUPC1_Msk                   /*!< Clear Wakeup Pin Flag 1 */

+

+/********************  Bit definition for PWR_WKUPFR register  ****************/

+#define PWR_WKUPFR_WKUPF6_Pos          (5U)

+#define PWR_WKUPFR_WKUPF6_Msk          (0x1UL << PWR_WKUPFR_WKUPF6_Pos)        /*!< 0x00000020 */

+#define PWR_WKUPFR_WKUPF6              PWR_WKUPFR_WKUPF6_Msk                   /*!< Wakeup Pin Flag 6 */

+#define PWR_WKUPFR_WKUPF5_Pos          (4U)

+#define PWR_WKUPFR_WKUPF5_Msk          (0x1UL << PWR_WKUPFR_WKUPF5_Pos)        /*!< 0x00000010 */

+#define PWR_WKUPFR_WKUPF5              PWR_WKUPFR_WKUPF5_Msk                   /*!< Wakeup Pin Flag 5 */

+#define PWR_WKUPFR_WKUPF4_Pos          (3U)

+#define PWR_WKUPFR_WKUPF4_Msk          (0x1UL << PWR_WKUPFR_WKUPF4_Pos)        /*!< 0x00000008 */

+#define PWR_WKUPFR_WKUPF4              PWR_WKUPFR_WKUPF4_Msk                   /*!< Wakeup Pin Flag 4 */

+#define PWR_WKUPFR_WKUPF3_Pos          (2U)

+#define PWR_WKUPFR_WKUPF3_Msk          (0x1UL << PWR_WKUPFR_WKUPF3_Pos)        /*!< 0x00000004 */

+#define PWR_WKUPFR_WKUPF3              PWR_WKUPFR_WKUPF3_Msk                   /*!< Wakeup Pin Flag 3 */

+#define PWR_WKUPFR_WKUPF2_Pos          (1U)

+#define PWR_WKUPFR_WKUPF2_Msk          (0x1UL << PWR_WKUPFR_WKUPF2_Pos)        /*!< 0x00000002 */

+#define PWR_WKUPFR_WKUPF2              PWR_WKUPFR_WKUPF2_Msk                   /*!< Wakeup Pin Flag 2 */

+#define PWR_WKUPFR_WKUPF1_Pos          (0U)

+#define PWR_WKUPFR_WKUPF1_Msk          (0x1UL << PWR_WKUPFR_WKUPF1_Pos)        /*!< 0x00000001 */

+#define PWR_WKUPFR_WKUPF1              PWR_WKUPFR_WKUPF1_Msk                   /*!< Wakeup Pin Flag 1 */

+

+/******************  Bit definition for PWR_WKUPEPR register  *****************/

+#define PWR_WKUPEPR_WKUPPUPD6_Pos      (26U)

+#define PWR_WKUPEPR_WKUPPUPD6_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x0C000000 */

+#define PWR_WKUPEPR_WKUPPUPD6          PWR_WKUPEPR_WKUPPUPD6_Msk               /*!< Wakeup Pin pull configuration for WKUP6 */

+#define PWR_WKUPEPR_WKUPPUPD6_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x04000000 */

+#define PWR_WKUPEPR_WKUPPUPD6_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x08000000 */

+#define PWR_WKUPEPR_WKUPPUPD5_Pos      (24U)

+#define PWR_WKUPEPR_WKUPPUPD5_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x03000000 */

+#define PWR_WKUPEPR_WKUPPUPD5          PWR_WKUPEPR_WKUPPUPD5_Msk               /*!< Wakeup Pin pull configuration for WKUP5 */

+#define PWR_WKUPEPR_WKUPPUPD5_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x01000000 */

+#define PWR_WKUPEPR_WKUPPUPD5_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x02000000 */

+#define PWR_WKUPEPR_WKUPPUPD4_Pos      (22U)

+#define PWR_WKUPEPR_WKUPPUPD4_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00C00000 */

+#define PWR_WKUPEPR_WKUPPUPD4          PWR_WKUPEPR_WKUPPUPD4_Msk               /*!< Wakeup Pin pull configuration for WKUP4 */

+#define PWR_WKUPEPR_WKUPPUPD4_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00400000 */

+#define PWR_WKUPEPR_WKUPPUPD4_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00800000 */

+#define PWR_WKUPEPR_WKUPPUPD3_Pos      (20U)

+#define PWR_WKUPEPR_WKUPPUPD3_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00300000 */

+#define PWR_WKUPEPR_WKUPPUPD3          PWR_WKUPEPR_WKUPPUPD3_Msk               /*!< Wakeup Pin pull configuration for WKUP3 */

+#define PWR_WKUPEPR_WKUPPUPD3_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00100000 */

+#define PWR_WKUPEPR_WKUPPUPD3_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00200000 */

+#define PWR_WKUPEPR_WKUPPUPD2_Pos      (18U)

+#define PWR_WKUPEPR_WKUPPUPD2_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x000C0000 */

+#define PWR_WKUPEPR_WKUPPUPD2          PWR_WKUPEPR_WKUPPUPD2_Msk               /*!< Wakeup Pin pull configuration for WKUP2 */

+#define PWR_WKUPEPR_WKUPPUPD2_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00040000 */

+#define PWR_WKUPEPR_WKUPPUPD2_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00080000 */

+#define PWR_WKUPEPR_WKUPPUPD1_Pos      (16U)

+#define PWR_WKUPEPR_WKUPPUPD1_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00030000 */

+#define PWR_WKUPEPR_WKUPPUPD1          PWR_WKUPEPR_WKUPPUPD1_Msk               /*!< Wakeup Pin pull configuration for WKUP1 */

+#define PWR_WKUPEPR_WKUPPUPD1_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00010000 */

+#define PWR_WKUPEPR_WKUPPUPD1_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00020000 */

+#define PWR_WKUPEPR_WKUPP6_Pos         (13U)

+#define PWR_WKUPEPR_WKUPP6_Msk         (0x1UL << PWR_WKUPEPR_WKUPP6_Pos)       /*!< 0x00002000 */

+#define PWR_WKUPEPR_WKUPP6             PWR_WKUPEPR_WKUPP6_Msk                  /*!< Wakeup Pin Polarity for WKUP6 */

+#define PWR_WKUPEPR_WKUPP5_Pos         (12U)

+#define PWR_WKUPEPR_WKUPP5_Msk         (0x1UL << PWR_WKUPEPR_WKUPP5_Pos)       /*!< 0x00001000 */

+#define PWR_WKUPEPR_WKUPP5             PWR_WKUPEPR_WKUPP5_Msk                  /*!< Wakeup Pin Polarity for WKUP5 */

+#define PWR_WKUPEPR_WKUPP4_Pos         (11U)

+#define PWR_WKUPEPR_WKUPP4_Msk         (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)       /*!< 0x00000800 */

+#define PWR_WKUPEPR_WKUPP4             PWR_WKUPEPR_WKUPP4_Msk                  /*!< Wakeup Pin Polarity for WKUP4 */

+#define PWR_WKUPEPR_WKUPP3_Pos         (10U)

+#define PWR_WKUPEPR_WKUPP3_Msk         (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)       /*!< 0x00000400 */

+#define PWR_WKUPEPR_WKUPP3             PWR_WKUPEPR_WKUPP3_Msk                  /*!< Wakeup Pin Polarity for WKUP3 */

+#define PWR_WKUPEPR_WKUPP2_Pos         (9U)

+#define PWR_WKUPEPR_WKUPP2_Msk         (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)       /*!< 0x00000200 */

+#define PWR_WKUPEPR_WKUPP2             PWR_WKUPEPR_WKUPP2_Msk                  /*!< Wakeup Pin Polarity for WKUP2 */

+#define PWR_WKUPEPR_WKUPP1_Pos         (8U)

+#define PWR_WKUPEPR_WKUPP1_Msk         (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)       /*!< 0x00000100 */

+#define PWR_WKUPEPR_WKUPP1             PWR_WKUPEPR_WKUPP1_Msk                  /*!< Wakeup Pin Polarity for WKUP1 */

+#define PWR_WKUPEPR_WKUPEN6_Pos        (5U)

+#define PWR_WKUPEPR_WKUPEN6_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos)      /*!< 0x00000020 */

+#define PWR_WKUPEPR_WKUPEN6            PWR_WKUPEPR_WKUPEN6_Msk                 /*!< Enable Wakeup Pin WKUP6 */

+#define PWR_WKUPEPR_WKUPEN5_Pos        (4U)

+#define PWR_WKUPEPR_WKUPEN5_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos)      /*!< 0x00000010 */

+#define PWR_WKUPEPR_WKUPEN5            PWR_WKUPEPR_WKUPEN5_Msk                 /*!< Enable Wakeup Pin WKUP5 */

+#define PWR_WKUPEPR_WKUPEN4_Pos        (3U)

+#define PWR_WKUPEPR_WKUPEN4_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)      /*!< 0x00000008 */

+#define PWR_WKUPEPR_WKUPEN4            PWR_WKUPEPR_WKUPEN4_Msk                 /*!< Enable Wakeup Pin WKUP4 */

+#define PWR_WKUPEPR_WKUPEN3_Pos        (2U)

+#define PWR_WKUPEPR_WKUPEN3_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)      /*!< 0x00000004 */

+#define PWR_WKUPEPR_WKUPEN3            PWR_WKUPEPR_WKUPEN3_Msk                 /*!< Enable Wakeup Pin WKUP3 */

+#define PWR_WKUPEPR_WKUPEN2_Pos        (1U)

+#define PWR_WKUPEPR_WKUPEN2_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)      /*!< 0x00000002 */

+#define PWR_WKUPEPR_WKUPEN2            PWR_WKUPEPR_WKUPEN2_Msk                 /*!< Enable Wakeup Pin WKUP2 */

+#define PWR_WKUPEPR_WKUPEN1_Pos        (0U)

+#define PWR_WKUPEPR_WKUPEN1_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)      /*!< 0x00000001 */

+#define PWR_WKUPEPR_WKUPEN1            PWR_WKUPEPR_WKUPEN1_Msk                 /*!< Enable Wakeup Pin WKUP1 */

+#define PWR_WKUPEPR_WKUPEN_Pos         (0U)

+#define PWR_WKUPEPR_WKUPEN_Msk         (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos)      /*!< 0x0000003F */

+#define PWR_WKUPEPR_WKUPEN             PWR_WKUPEPR_WKUPEN_Msk                  /*!< Enable all Wakeup Pin */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Reset and Clock Control                            */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  RCC VERSION  ********************************/

+#define RCC_VER_2_0

+

+/********************  Bit definition for RCC_CR register  ********************/

+#define RCC_CR_HSION_Pos                       (0U)

+#define RCC_CR_HSION_Msk                       (0x1UL << RCC_CR_HSION_Pos)     /*!< 0x00000001 */

+#define RCC_CR_HSION                           RCC_CR_HSION_Msk                /*!< Internal High Speed clock enable */

+#define RCC_CR_HSIKERON_Pos                    (1U)

+#define RCC_CR_HSIKERON_Msk                    (0x1UL << RCC_CR_HSIKERON_Pos)  /*!< 0x00000002 */

+#define RCC_CR_HSIKERON                        RCC_CR_HSIKERON_Msk             /*!< Internal High Speed clock enable for some IPs Kernel */

+#define RCC_CR_HSIRDY_Pos                      (2U)

+#define RCC_CR_HSIRDY_Msk                      (0x1UL << RCC_CR_HSIRDY_Pos)    /*!< 0x00000004 */

+#define RCC_CR_HSIRDY                          RCC_CR_HSIRDY_Msk               /*!< Internal High Speed clock ready flag */

+#define RCC_CR_HSIDIV_Pos                      (3U)

+#define RCC_CR_HSIDIV_Msk                      (0x3UL << RCC_CR_HSIDIV_Pos)    /*!< 0x00000018 */

+#define RCC_CR_HSIDIV                          RCC_CR_HSIDIV_Msk               /*!< Internal High Speed clock divider selection */

+#define RCC_CR_HSIDIV_1                        (0x0UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000000 */

+#define RCC_CR_HSIDIV_2                        (0x1UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000008 */

+#define RCC_CR_HSIDIV_4                        (0x2UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000010 */

+#define RCC_CR_HSIDIV_8                        (0x3UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000018 */

+

+#define RCC_CR_HSIDIVF_Pos                     (5U)

+#define RCC_CR_HSIDIVF_Msk                     (0x1UL << RCC_CR_HSIDIVF_Pos)   /*!< 0x00000020 */

+#define RCC_CR_HSIDIVF                         RCC_CR_HSIDIVF_Msk              /*!< HSI Divider flag */

+#define RCC_CR_CSION_Pos                       (7U)

+#define RCC_CR_CSION_Msk                       (0x1UL << RCC_CR_CSION_Pos)     /*!< 0x00000080 */

+#define RCC_CR_CSION                           RCC_CR_CSION_Msk                /*!< The Internal RC 4MHz oscillator clock enable */

+#define RCC_CR_CSIRDY_Pos                      (8U)

+#define RCC_CR_CSIRDY_Msk                      (0x1UL << RCC_CR_CSIRDY_Pos)    /*!< 0x00000100 */

+#define RCC_CR_CSIRDY                          RCC_CR_CSIRDY_Msk               /*!< The Internal RC 4MHz oscillator clock ready */

+#define RCC_CR_CSIKERON_Pos                    (9U)

+#define RCC_CR_CSIKERON_Msk                    (0x1UL << RCC_CR_CSIKERON_Pos)  /*!< 0x00000200 */

+#define RCC_CR_CSIKERON                        RCC_CR_CSIKERON_Msk             /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */

+#define RCC_CR_HSI48ON_Pos                     (12U)

+#define RCC_CR_HSI48ON_Msk                     (0x1UL << RCC_CR_HSI48ON_Pos)   /*!< 0x00001000 */

+#define RCC_CR_HSI48ON                         RCC_CR_HSI48ON_Msk              /*!< HSI48 clock enable clock enable  */

+#define RCC_CR_HSI48RDY_Pos                    (13U)

+#define RCC_CR_HSI48RDY_Msk                    (0x1UL << RCC_CR_HSI48RDY_Pos)  /*!< 0x00002000 */

+#define RCC_CR_HSI48RDY                        RCC_CR_HSI48RDY_Msk             /*!< HSI48 clock ready */

+

+#define RCC_CR_CPUCKRDY_Pos                     (14U)

+#define RCC_CR_CPUCKRDY_Msk                     (0x1UL << RCC_CR_CPUCKRDY_Pos)   /*!< 0x00004000 */

+#define RCC_CR_CPUCKRDY                         RCC_CR_CPUCKRDY_Msk              /*!< CPU domain clocks ready flag  */

+#define RCC_CR_CDCKRDY_Pos                     (15U)

+#define RCC_CR_CDCKRDY_Msk                     (0x1UL << RCC_CR_CDCKRDY_Pos)   /*!< 0x00008000 */

+#define RCC_CR_CDCKRDY                         RCC_CR_CDCKRDY_Msk              /*!< CD domain clocks ready flag */

+

+#define RCC_CR_HSEON_Pos                       (16U)

+#define RCC_CR_HSEON_Msk                       (0x1UL << RCC_CR_HSEON_Pos)     /*!< 0x00010000 */

+#define RCC_CR_HSEON                           RCC_CR_HSEON_Msk                /*!< External High Speed clock enable */

+#define RCC_CR_HSERDY_Pos                      (17U)

+#define RCC_CR_HSERDY_Msk                      (0x1UL << RCC_CR_HSERDY_Pos)    /*!< 0x00020000 */

+#define RCC_CR_HSERDY                          RCC_CR_HSERDY_Msk               /*!< External High Speed clock ready */

+#define RCC_CR_HSEBYP_Pos                      (18U)

+#define RCC_CR_HSEBYP_Msk                      (0x1UL << RCC_CR_HSEBYP_Pos)    /*!< 0x00040000 */

+#define RCC_CR_HSEBYP                          RCC_CR_HSEBYP_Msk               /*!< External High Speed clock Bypass */

+#define RCC_CR_CSSHSEON_Pos                    (19U)

+#define RCC_CR_CSSHSEON_Msk                    (0x1UL << RCC_CR_CSSHSEON_Pos)  /*!< 0x00080000 */

+#define RCC_CR_CSSHSEON                        RCC_CR_CSSHSEON_Msk             /*!< HSE Clock security System enable */

+

+#define RCC_CR_HSEEXT_Pos                    (20U)

+#define RCC_CR_HSEEXT_Msk                    (0x1UL << RCC_CR_HSEEXT_Pos)  /*!< 0x00080000 */

+#define RCC_CR_HSEEXT                        RCC_CR_HSEEXT_Msk             /*!< HSE Clock security System enable */

+

+#define RCC_CR_PLL1ON_Pos                      (24U)

+#define RCC_CR_PLL1ON_Msk                      (0x1UL << RCC_CR_PLL1ON_Pos)    /*!< 0x01000000 */

+#define RCC_CR_PLL1ON                          RCC_CR_PLL1ON_Msk               /*!< System PLL1 clock enable */

+#define RCC_CR_PLL1RDY_Pos                     (25U)

+#define RCC_CR_PLL1RDY_Msk                     (0x1UL << RCC_CR_PLL1RDY_Pos)   /*!< 0x02000000 */

+#define RCC_CR_PLL1RDY                         RCC_CR_PLL1RDY_Msk              /*!< System PLL1 clock ready */

+#define RCC_CR_PLL2ON_Pos                      (26U)

+#define RCC_CR_PLL2ON_Msk                      (0x1UL << RCC_CR_PLL2ON_Pos)    /*!< 0x04000000 */

+#define RCC_CR_PLL2ON                          RCC_CR_PLL2ON_Msk               /*!< System PLL2 clock enable */

+#define RCC_CR_PLL2RDY_Pos                     (27U)

+#define RCC_CR_PLL2RDY_Msk                     (0x1UL << RCC_CR_PLL2RDY_Pos)   /*!< 0x08000000 */

+#define RCC_CR_PLL2RDY                         RCC_CR_PLL2RDY_Msk              /*!< System PLL2 clock ready */

+#define RCC_CR_PLL3ON_Pos                      (28U)

+#define RCC_CR_PLL3ON_Msk                      (0x1UL << RCC_CR_PLL3ON_Pos)    /*!< 0x10000000 */

+#define RCC_CR_PLL3ON                          RCC_CR_PLL3ON_Msk               /*!< System PLL3 clock enable */

+#define RCC_CR_PLL3RDY_Pos                     (29U)

+#define RCC_CR_PLL3RDY_Msk                     (0x1UL << RCC_CR_PLL3RDY_Pos)   /*!< 0x20000000 */

+#define RCC_CR_PLL3RDY                         RCC_CR_PLL3RDY_Msk              /*!< System PLL3 clock ready */

+

+/*Legacy */

+#define RCC_CR_PLLON_Pos                       (24U)

+#define RCC_CR_PLLON_Msk                       (0x1UL << RCC_CR_PLLON_Pos)     /*!< 0x01000000 */

+#define RCC_CR_PLLON                           RCC_CR_PLLON_Msk                /*!< System PLL clock enable */

+#define RCC_CR_PLLRDY_Pos                      (25U)

+#define RCC_CR_PLLRDY_Msk                      (0x1UL << RCC_CR_PLLRDY_Pos)    /*!< 0x02000000 */

+#define RCC_CR_PLLRDY                          RCC_CR_PLLRDY_Msk               /*!< System PLL clock ready */

+

+/********************  Bit definition for RCC_HSICFGR register  ***************/

+/*!< HSICAL configuration */

+#define RCC_HSICFGR_HSICAL_Pos                 (0U)

+#define RCC_HSICFGR_HSICAL_Msk                 (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */

+#define RCC_HSICFGR_HSICAL                     RCC_HSICFGR_HSICAL_Msk          /*!< HSICAL[11:0] bits */

+#define RCC_HSICFGR_HSICAL_0                   (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */

+#define RCC_HSICFGR_HSICAL_1                   (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */

+#define RCC_HSICFGR_HSICAL_2                   (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */

+#define RCC_HSICFGR_HSICAL_3                   (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */

+#define RCC_HSICFGR_HSICAL_4                   (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */

+#define RCC_HSICFGR_HSICAL_5                   (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */

+#define RCC_HSICFGR_HSICAL_6                   (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */

+#define RCC_HSICFGR_HSICAL_7                   (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */

+#define RCC_HSICFGR_HSICAL_8                   (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */

+#define RCC_HSICFGR_HSICAL_9                   (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */

+#define RCC_HSICFGR_HSICAL_10                  (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */

+#define RCC_HSICFGR_HSICAL_11                  (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */

+

+/*!< HSITRIM configuration */

+#define RCC_HSICFGR_HSITRIM_Pos                (24U)

+#define RCC_HSICFGR_HSITRIM_Msk                (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */

+#define RCC_HSICFGR_HSITRIM                    RCC_HSICFGR_HSITRIM_Msk         /*!< HSITRIM[6:0] bits */

+#define RCC_HSICFGR_HSITRIM_0                  (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */

+#define RCC_HSICFGR_HSITRIM_1                  (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */

+#define RCC_HSICFGR_HSITRIM_2                  (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */

+#define RCC_HSICFGR_HSITRIM_3                  (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */

+#define RCC_HSICFGR_HSITRIM_4                  (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */

+#define RCC_HSICFGR_HSITRIM_5                  (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */

+#define RCC_HSICFGR_HSITRIM_6                  (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */

+

+

+/********************  Bit definition for RCC_CRRCR register  *****************/

+

+/*!< HSI48CAL configuration */

+#define RCC_CRRCR_HSI48CAL_Pos                 (0U)

+#define RCC_CRRCR_HSI48CAL_Msk                 (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */

+#define RCC_CRRCR_HSI48CAL                     RCC_CRRCR_HSI48CAL_Msk          /*!< HSI48CAL[9:0] bits */

+#define RCC_CRRCR_HSI48CAL_0                   (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */

+#define RCC_CRRCR_HSI48CAL_1                   (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */

+#define RCC_CRRCR_HSI48CAL_2                   (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */

+#define RCC_CRRCR_HSI48CAL_3                   (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */

+#define RCC_CRRCR_HSI48CAL_4                   (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */

+#define RCC_CRRCR_HSI48CAL_5                   (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */

+#define RCC_CRRCR_HSI48CAL_6                   (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */

+#define RCC_CRRCR_HSI48CAL_7                   (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */

+#define RCC_CRRCR_HSI48CAL_8                   (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */

+#define RCC_CRRCR_HSI48CAL_9                   (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */

+

+

+/********************  Bit definition for RCC_CSICFGR register  *****************/

+/*!< CSICAL configuration */

+#define RCC_CSICFGR_CSICAL_Pos                 (0U)

+#define RCC_CSICFGR_CSICAL_Msk                 (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */

+#define RCC_CSICFGR_CSICAL                     RCC_CSICFGR_CSICAL_Msk          /*!< CSICAL[7:0] bits */

+#define RCC_CSICFGR_CSICAL_0                   (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */

+#define RCC_CSICFGR_CSICAL_1                   (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */

+#define RCC_CSICFGR_CSICAL_2                   (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */

+#define RCC_CSICFGR_CSICAL_3                   (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */

+#define RCC_CSICFGR_CSICAL_4                   (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */

+#define RCC_CSICFGR_CSICAL_5                   (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */

+#define RCC_CSICFGR_CSICAL_6                   (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */

+#define RCC_CSICFGR_CSICAL_7                   (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */

+

+/*!< CSITRIM configuration */

+#define RCC_CSICFGR_CSITRIM_Pos                (24U)

+#define RCC_CSICFGR_CSITRIM_Msk                (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */

+#define RCC_CSICFGR_CSITRIM                    RCC_CSICFGR_CSITRIM_Msk         /*!< CSITRIM[5:0] bits */

+#define RCC_CSICFGR_CSITRIM_0                  (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */

+#define RCC_CSICFGR_CSITRIM_1                  (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */

+#define RCC_CSICFGR_CSITRIM_2                  (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */

+#define RCC_CSICFGR_CSITRIM_3                  (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */

+#define RCC_CSICFGR_CSITRIM_4                  (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */

+#define RCC_CSICFGR_CSITRIM_5                  (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */

+

+/********************  Bit definition for RCC_CFGR register  ******************/

+/*!< SW configuration */

+#define RCC_CFGR_SW_Pos                        (0U)

+#define RCC_CFGR_SW_Msk                        (0x7UL << RCC_CFGR_SW_Pos)           /*!< 0x00000007 */

+#define RCC_CFGR_SW                            RCC_CFGR_SW_Msk                     /*!< SW[2:0] bits (System clock Switch) */

+#define RCC_CFGR_SW_0                          (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */

+#define RCC_CFGR_SW_1                          (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */

+#define RCC_CFGR_SW_2                          (0x4UL << RCC_CFGR_SW_Pos)           /*!< 0x00000004 */

+

+#define RCC_CFGR_SW_HSI                        (0x00000000UL)                       /*!< HSI selection as system clock */

+#define RCC_CFGR_SW_CSI                        (0x00000001UL)                       /*!< CSI selection as system clock */

+#define RCC_CFGR_SW_HSE                        (0x00000002UL)                       /*!< HSE selection as system clock */

+#define RCC_CFGR_SW_PLL1                       (0x00000003UL)                       /*!< PLL1 selection as system clock */

+

+/*!< SWS configuration */

+#define RCC_CFGR_SWS_Pos                       (3U)

+#define RCC_CFGR_SWS_Msk                       (0x7UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000038 */

+#define RCC_CFGR_SWS                           RCC_CFGR_SWS_Msk                    /*!< SWS[2:0] bits (System Clock Switch Status) */

+#define RCC_CFGR_SWS_0                         (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */

+#define RCC_CFGR_SWS_1                         (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000010 */

+#define RCC_CFGR_SWS_2                         (0x4UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000020 */

+

+#define RCC_CFGR_SWS_HSI                       (0x00000000UL)                       /*!< HSI used as system clock */

+#define RCC_CFGR_SWS_CSI                       (0x00000008UL)                       /*!< CSI used as system clock */

+#define RCC_CFGR_SWS_HSE                       (0x00000010UL)                       /*!< HSE used as system clock */

+#define RCC_CFGR_SWS_PLL1                      (0x00000018UL)                       /*!< PLL1 used as system clock */

+

+#define RCC_CFGR_STOPWUCK_Pos                  (6U)

+#define RCC_CFGR_STOPWUCK_Msk                  (0x1UL << RCC_CFGR_STOPWUCK_Pos)     /*!< 0x00000040 */

+#define RCC_CFGR_STOPWUCK                      RCC_CFGR_STOPWUCK_Msk                /*!< Wake Up from stop and CSS backup clock selection */

+

+#define RCC_CFGR_STOPKERWUCK_Pos               (7U)

+#define RCC_CFGR_STOPKERWUCK_Msk               (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)  /*!< 0x00000080 */

+#define RCC_CFGR_STOPKERWUCK                   RCC_CFGR_STOPKERWUCK_Msk             /*!< Kernel Clock Selection after a Wake Up from STOP */

+

+/*!< RTCPRE configuration */

+#define RCC_CFGR_RTCPRE_Pos                    (8U)

+#define RCC_CFGR_RTCPRE_Msk                    (0x3FUL << RCC_CFGR_RTCPRE_Pos)

+#define RCC_CFGR_RTCPRE                        RCC_CFGR_RTCPRE_Msk                  /*!< 0x00003F00 */

+#define RCC_CFGR_RTCPRE_0                      (0x1UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000100 */

+#define RCC_CFGR_RTCPRE_1                      (0x2UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000200 */

+#define RCC_CFGR_RTCPRE_2                      (0x4UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000400 */

+#define RCC_CFGR_RTCPRE_3                      (0x8UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000800 */

+#define RCC_CFGR_RTCPRE_4                      (0x10UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00001000 */

+#define RCC_CFGR_RTCPRE_5                      (0x20UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00002000 */

+

+

+/*!< TIMPRE configuration */

+#define RCC_CFGR_TIMPRE_Pos                    (15U)

+#define RCC_CFGR_TIMPRE_Msk                    (0x1UL << RCC_CFGR_TIMPRE_Pos)

+#define RCC_CFGR_TIMPRE                        RCC_CFGR_TIMPRE_Msk                  /*!< 0x00008000 */

+

+/*!< MCO1 configuration */

+#define RCC_CFGR_MCO1_Pos                      (22U)

+#define RCC_CFGR_MCO1_Msk                      (0x7UL << RCC_CFGR_MCO1_Pos)

+#define RCC_CFGR_MCO1                          RCC_CFGR_MCO1_Msk                       /*!< 0x01C00000 */

+#define RCC_CFGR_MCO1_0                        (0x1UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00400000 */

+#define RCC_CFGR_MCO1_1                        (0x2UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00800000 */

+#define RCC_CFGR_MCO1_2                        (0x4UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x01000000 */

+

+#define RCC_CFGR_MCO1PRE_Pos                   (18U)

+#define RCC_CFGR_MCO1PRE_Msk                   (0xFUL << RCC_CFGR_MCO1PRE_Pos)

+#define RCC_CFGR_MCO1PRE                       RCC_CFGR_MCO1PRE_Msk                    /*!< 0x003C0000 */

+#define RCC_CFGR_MCO1PRE_0                     (0x1UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00040000 */

+#define RCC_CFGR_MCO1PRE_1                     (0x2UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00080000 */

+#define RCC_CFGR_MCO1PRE_2                     (0x4UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00100000 */

+#define RCC_CFGR_MCO1PRE_3                     (0x8UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00200000 */

+

+#define RCC_CFGR_MCO2PRE_Pos                   (25U)

+#define RCC_CFGR_MCO2PRE_Msk                   (0xFUL << RCC_CFGR_MCO2PRE_Pos)

+#define RCC_CFGR_MCO2PRE                       RCC_CFGR_MCO2PRE_Msk                    /*!< 0x1E000000 */

+#define RCC_CFGR_MCO2PRE_0                     (0x1UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x02000000 */

+#define RCC_CFGR_MCO2PRE_1                     (0x2UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x04000000 */

+#define RCC_CFGR_MCO2PRE_2                     (0x4UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x08000000 */

+#define RCC_CFGR_MCO2PRE_3                     (0x8UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x10000000 */

+

+#define RCC_CFGR_MCO2_Pos                      (29U)

+#define RCC_CFGR_MCO2_Msk                      (0x7UL << RCC_CFGR_MCO2_Pos)

+#define RCC_CFGR_MCO2                          RCC_CFGR_MCO2_Msk                       /*!< 0xE0000000 */

+#define RCC_CFGR_MCO2_0                        (0x1UL << RCC_CFGR_MCO2_Pos)             /*!< 0x20000000 */

+#define RCC_CFGR_MCO2_1                        (0x2UL << RCC_CFGR_MCO2_Pos)             /*!< 0x40000000 */

+#define RCC_CFGR_MCO2_2                        (0x4UL << RCC_CFGR_MCO2_Pos)             /*!< 0x80000000 */

+

+/********************  Bit definition for RCC_D1CFGR register  ******************/

+/*!< D1HPRE configuration */

+#define RCC_CDCFGR1_HPRE_Pos                    (0U)

+#define RCC_CDCFGR1_HPRE_Msk                    (0xFUL << RCC_CDCFGR1_HPRE_Pos)  /*!< 0x0000000F */

+#define RCC_CDCFGR1_HPRE                        RCC_CDCFGR1_HPRE_Msk             /*!< HPRE[3:0] bits (AHB3 prescaler) */

+#define RCC_CDCFGR1_HPRE_0                      (0x1UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000001 */

+#define RCC_CDCFGR1_HPRE_1                      (0x2UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000002 */

+#define RCC_CDCFGR1_HPRE_2                      (0x4UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000004 */

+#define RCC_CDCFGR1_HPRE_3                      (0x8UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000008 */

+

+#define RCC_CDCFGR1_HPRE_DIV1                   ((uint32_t)0x00000000)                 /*!< AHB3 Clock not divided */

+#define RCC_CDCFGR1_HPRE_DIV2_Pos               (3U)

+#define RCC_CDCFGR1_HPRE_DIV2_Msk               (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos)   /*!< 0x00000008 */

+#define RCC_CDCFGR1_HPRE_DIV2                   RCC_CDCFGR1_HPRE_DIV2_Msk              /*!< AHB3 Clock divided by 2 */

+#define RCC_CDCFGR1_HPRE_DIV4_Pos               (0U)

+#define RCC_CDCFGR1_HPRE_DIV4_Msk               (0x9UL << RCC_CDCFGR1_HPRE_DIV4_Pos)   /*!< 0x00000009 */

+#define RCC_CDCFGR1_HPRE_DIV4                   RCC_CDCFGR1_HPRE_DIV4_Msk              /*!< AHB3 Clock divided by 4 */

+#define RCC_CDCFGR1_HPRE_DIV8_Pos               (1U)

+#define RCC_CDCFGR1_HPRE_DIV8_Msk               (0x5UL << RCC_CDCFGR1_HPRE_DIV8_Pos)   /*!< 0x0000000A */

+#define RCC_CDCFGR1_HPRE_DIV8                   RCC_CDCFGR1_HPRE_DIV8_Msk              /*!< AHB3 Clock divided by 8 */

+#define RCC_CDCFGR1_HPRE_DIV16_Pos              (0U)

+#define RCC_CDCFGR1_HPRE_DIV16_Msk              (0xBUL << RCC_CDCFGR1_HPRE_DIV16_Pos)  /*!< 0x0000000B */

+#define RCC_CDCFGR1_HPRE_DIV16                  RCC_CDCFGR1_HPRE_DIV16_Msk             /*!< AHB3 Clock divided by 16 */

+#define RCC_CDCFGR1_HPRE_DIV64_Pos              (2U)

+#define RCC_CDCFGR1_HPRE_DIV64_Msk              (0x3UL << RCC_CDCFGR1_HPRE_DIV64_Pos)  /*!< 0x0000000C */

+#define RCC_CDCFGR1_HPRE_DIV64                  RCC_CDCFGR1_HPRE_DIV64_Msk             /*!< AHB3 Clock divided by 64 */

+#define RCC_CDCFGR1_HPRE_DIV128_Pos             (0U)

+#define RCC_CDCFGR1_HPRE_DIV128_Msk             (0xDUL << RCC_CDCFGR1_HPRE_DIV128_Pos) /*!< 0x0000000D */

+#define RCC_CDCFGR1_HPRE_DIV128                 RCC_CDCFGR1_HPRE_DIV128_Msk            /*!< AHB3 Clock divided by 128 */

+#define RCC_CDCFGR1_HPRE_DIV256_Pos             (1U)

+#define RCC_CDCFGR1_HPRE_DIV256_Msk             (0x7UL << RCC_CDCFGR1_HPRE_DIV256_Pos) /*!< 0x0000000E */

+#define RCC_CDCFGR1_HPRE_DIV256                 RCC_CDCFGR1_HPRE_DIV256_Msk            /*!< AHB3 Clock divided by 256 */

+#define RCC_CDCFGR1_HPRE_DIV512_Pos             (0U)

+#define RCC_CDCFGR1_HPRE_DIV512_Msk             (0xFUL << RCC_CDCFGR1_HPRE_DIV512_Pos) /*!< 0x0000000F */

+#define RCC_CDCFGR1_HPRE_DIV512                 RCC_CDCFGR1_HPRE_DIV512_Msk            /*!< AHB3 Clock divided by 512 */

+

+/*!< D1PPRE configuration */

+#define RCC_CDCFGR1_CDPPRE_Pos                  (4U)

+#define RCC_CDCFGR1_CDPPRE_Msk                  (0x7UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000070 */

+#define RCC_CDCFGR1_CDPPRE                      RCC_CDCFGR1_CDPPRE_Msk                 /*!< CDPRE[2:0] bits (APB3 prescaler) */

+#define RCC_CDCFGR1_CDPPRE_0                    (0x1UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000010 */

+#define RCC_CDCFGR1_CDPPRE_1                    (0x2UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000020 */

+#define RCC_CDCFGR1_CDPPRE_2                    (0x4UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000040 */

+

+#define RCC_CDCFGR1_CDPPRE_DIV1                 ((uint32_t)0x00000000)                 /*!< APB3 clock not divided */

+#define RCC_CDCFGR1_CDPPRE_DIV2_Pos             (6U)

+#define RCC_CDCFGR1_CDPPRE_DIV2_Msk             (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_CDCFGR1_CDPPRE_DIV2                 RCC_CDCFGR1_CDPPRE_DIV2_Msk            /*!< APB3 clock divided by 2 */

+#define RCC_CDCFGR1_CDPPRE_DIV4_Pos             (4U)

+#define RCC_CDCFGR1_CDPPRE_DIV4_Msk             (0x5UL << RCC_CDCFGR1_CDPPRE_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_CDCFGR1_CDPPRE_DIV4                 RCC_CDCFGR1_CDPPRE_DIV4_Msk            /*!< APB3 clock divided by 4 */

+#define RCC_CDCFGR1_CDPPRE_DIV8_Pos             (5U)

+#define RCC_CDCFGR1_CDPPRE_DIV8_Msk             (0x3UL << RCC_CDCFGR1_CDPPRE_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_CDCFGR1_CDPPRE_DIV8                 RCC_CDCFGR1_CDPPRE_DIV8_Msk            /*!< APB3 clock divided by 8 */

+#define RCC_CDCFGR1_CDPPRE_DIV16_Pos            (4U)

+#define RCC_CDCFGR1_CDPPRE_DIV16_Msk            (0x7UL << RCC_CDCFGR1_CDPPRE_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_CDCFGR1_CDPPRE_DIV16                RCC_CDCFGR1_CDPPRE_DIV16_Msk            /*!< APB3 clock divided by 16 */

+

+#define RCC_CDCFGR1_CDCPRE_Pos                  (8U)

+#define RCC_CDCFGR1_CDCPRE_Msk                  (0xFUL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000F00 */

+#define RCC_CDCFGR1_CDCPRE                      RCC_CDCFGR1_CDCPRE_Msk                  /*!< CDCPRE[2:0] bits (Domain 1 Core prescaler) */

+#define RCC_CDCFGR1_CDCPRE_0                    (0x1UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000100 */

+#define RCC_CDCFGR1_CDCPRE_1                    (0x2UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000200 */

+#define RCC_CDCFGR1_CDCPRE_2                    (0x4UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000400 */

+#define RCC_CDCFGR1_CDCPRE_3                    (0x8UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000800 */

+

+#define RCC_CDCFGR1_CDCPRE_DIV1                 ((uint32_t)0x00000000)                  /*!< Domain 1 Core clock not divided */

+#define RCC_CDCFGR1_CDCPRE_DIV2_Pos             (11U)

+#define RCC_CDCFGR1_CDCPRE_DIV2_Msk             (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos)  /*!< 0x00000800 */

+#define RCC_CDCFGR1_CDCPRE_DIV2                 RCC_CDCFGR1_CDCPRE_DIV2_Msk             /*!< Domain 1 Core clock divided by 2 */

+#define RCC_CDCFGR1_CDCPRE_DIV4_Pos             (8U)

+#define RCC_CDCFGR1_CDCPRE_DIV4_Msk             (0x9UL << RCC_CDCFGR1_CDCPRE_DIV4_Pos)  /*!< 0x00000900 */

+#define RCC_CDCFGR1_CDCPRE_DIV4                 RCC_CDCFGR1_CDCPRE_DIV4_Msk             /*!< Domain 1 Core clock divided by 4 */

+#define RCC_CDCFGR1_CDCPRE_DIV8_Pos             (9U)

+#define RCC_CDCFGR1_CDCPRE_DIV8_Msk             (0x5UL << RCC_CDCFGR1_CDCPRE_DIV8_Pos)  /*!< 0x00000A00 */

+#define RCC_CDCFGR1_CDCPRE_DIV8                 RCC_CDCFGR1_CDCPRE_DIV8_Msk             /*!< Domain 1 Core clock divided by 8 */

+#define RCC_CDCFGR1_CDCPRE_DIV16_Pos            (8U)

+#define RCC_CDCFGR1_CDCPRE_DIV16_Msk            (0xBUL << RCC_CDCFGR1_CDCPRE_DIV16_Pos) /*!< 0x00000B00 */

+#define RCC_CDCFGR1_CDCPRE_DIV16                RCC_CDCFGR1_CDCPRE_DIV16_Msk            /*!< Domain 1 Core clock divided by 16 */

+#define RCC_CDCFGR1_CDCPRE_DIV64_Pos            (10U)

+#define RCC_CDCFGR1_CDCPRE_DIV64_Msk            (0x3UL << RCC_CDCFGR1_CDCPRE_DIV64_Pos) /*!< 0x00000C00 */

+#define RCC_CDCFGR1_CDCPRE_DIV64                RCC_CDCFGR1_CDCPRE_DIV64_Msk            /*!< Domain 1 Core clock divided by 64 */

+#define RCC_CDCFGR1_CDCPRE_DIV128_Pos           (8U)

+#define RCC_CDCFGR1_CDCPRE_DIV128_Msk           (0xDUL << RCC_CDCFGR1_CDCPRE_DIV128_Pos)/*!< 0x00000D00 */

+#define RCC_CDCFGR1_CDCPRE_DIV128               RCC_CDCFGR1_CDCPRE_DIV128_Msk           /*!< Domain 1 Core clock divided by 128 */

+#define RCC_CDCFGR1_CDCPRE_DIV256_Pos           (9U)

+#define RCC_CDCFGR1_CDCPRE_DIV256_Msk           (0x7UL << RCC_CDCFGR1_CDCPRE_DIV256_Pos)/*!< 0x00000E00 */

+#define RCC_CDCFGR1_CDCPRE_DIV256               RCC_CDCFGR1_CDCPRE_DIV256_Msk           /*!< Domain 1 Core clock divided by 256 */

+#define RCC_CDCFGR1_CDCPRE_DIV512_Pos           (8U)

+#define RCC_CDCFGR1_CDCPRE_DIV512_Msk           (0xFUL << RCC_CDCFGR1_CDCPRE_DIV512_Pos)/*!< 0x00000F00 */

+#define RCC_CDCFGR1_CDCPRE_DIV512               RCC_CDCFGR1_CDCPRE_DIV512_Msk           /*!< Domain 1 Core clock divided by 512 */

+

+/********************  Bit definition for RCC_CDCFGR2 register  ******************/

+/*!< CDPPRE1 configuration */

+#define RCC_CDCFGR2_CDPPRE1_Pos                 (4U)

+#define RCC_CDCFGR2_CDPPRE1_Msk                 (0x7UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000070 */

+#define RCC_CDCFGR2_CDPPRE1                     RCC_CDCFGR2_CDPPRE1_Msk          /*!< D1PPRE1[2:0] bits (APB1 prescaler) */

+#define RCC_CDCFGR2_CDPPRE1_0                   (0x1UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000010 */

+#define RCC_CDCFGR2_CDPPRE1_1                   (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */

+#define RCC_CDCFGR2_CDPPRE1_2                   (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */

+

+#define RCC_CDCFGR2_CDPPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */

+#define RCC_CDCFGR2_CDPPRE1_DIV2_Pos            (6U)

+#define RCC_CDCFGR2_CDPPRE1_DIV2_Msk            (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_CDCFGR2_CDPPRE1_DIV2                RCC_CDCFGR2_CDPPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */

+#define RCC_CDCFGR2_CDPPRE1_DIV4_Pos            (4U)

+#define RCC_CDCFGR2_CDPPRE1_DIV4_Msk            (0x5UL << RCC_CDCFGR2_CDPPRE1_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_CDCFGR2_CDPPRE1_DIV4                RCC_CDCFGR2_CDPPRE1_DIV4_Msk     /*!< APB1 clock divided by 4 */

+#define RCC_CDCFGR2_CDPPRE1_DIV8_Pos            (5U)

+#define RCC_CDCFGR2_CDPPRE1_DIV8_Msk            (0x3UL << RCC_CDCFGR2_CDPPRE1_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_CDCFGR2_CDPPRE1_DIV8                RCC_CDCFGR2_CDPPRE1_DIV8_Msk     /*!< APB1 clock divided by 8 */

+#define RCC_CDCFGR2_CDPPRE1_DIV16_Pos           (4U)

+#define RCC_CDCFGR2_CDPPRE1_DIV16_Msk           (0x7UL << RCC_CDCFGR2_CDPPRE1_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_CDCFGR2_CDPPRE1_DIV16               RCC_CDCFGR2_CDPPRE1_DIV16_Msk    /*!< APB1 clock divided by 16 */

+

+/*!< CDPPRE2 configuration */

+#define RCC_CDCFGR2_CDPPRE2_Pos                 (8U)

+#define RCC_CDCFGR2_CDPPRE2_Msk                 (0x7UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000700 */

+#define RCC_CDCFGR2_CDPPRE2                     RCC_CDCFGR2_CDPPRE2_Msk          /*!< CDPPRE2[2:0] bits (APB2 prescaler) */

+#define RCC_CDCFGR2_CDPPRE2_0                   (0x1UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000100 */

+#define RCC_CDCFGR2_CDPPRE2_1                   (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */

+#define RCC_CDCFGR2_CDPPRE2_2                   (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */

+

+#define RCC_CDCFGR2_CDPPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */

+#define RCC_CDCFGR2_CDPPRE2_DIV2_Pos            (10U)

+#define RCC_CDCFGR2_CDPPRE2_DIV2_Msk            (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */

+#define RCC_CDCFGR2_CDPPRE2_DIV2                RCC_CDCFGR2_CDPPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */

+#define RCC_CDCFGR2_CDPPRE2_DIV4_Pos            (8U)

+#define RCC_CDCFGR2_CDPPRE2_DIV4_Msk            (0x5UL << RCC_CDCFGR2_CDPPRE2_DIV4_Pos) /*!< 0x00000500 */

+#define RCC_CDCFGR2_CDPPRE2_DIV4                RCC_CDCFGR2_CDPPRE2_DIV4_Msk     /*!< APB2 clock divided by 4 */

+#define RCC_CDCFGR2_CDPPRE2_DIV8_Pos            (9U)

+#define RCC_CDCFGR2_CDPPRE2_DIV8_Msk            (0x3UL << RCC_CDCFGR2_CDPPRE2_DIV8_Pos) /*!< 0x00000600 */

+#define RCC_CDCFGR2_CDPPRE2_DIV8                RCC_CDCFGR2_CDPPRE2_DIV8_Msk     /*!< APB2 clock divided by 8 */

+#define RCC_CDCFGR2_CDPPRE2_DIV16_Pos           (8U)

+#define RCC_CDCFGR2_CDPPRE2_DIV16_Msk           (0x7UL << RCC_CDCFGR2_CDPPRE2_DIV16_Pos) /*!< 0x00000700 */

+#define RCC_CDCFGR2_CDPPRE2_DIV16               RCC_CDCFGR2_CDPPRE2_DIV16_Msk    /*!< APB2 clock divided by 16 */

+

+/********************  Bit definition for RCC_SRDCFGR register  ******************/

+/*!< SRDPPRE configuration */

+#define RCC_SRDCFGR_SRDPPRE_Pos                  (4U)

+#define RCC_SRDCFGR_SRDPPRE_Msk                  (0x7UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000070 */

+#define RCC_SRDCFGR_SRDPPRE                      RCC_SRDCFGR_SRDPPRE_Msk           /*!< SRDPPRE1[2:0] bits (APB4 prescaler) */

+#define RCC_SRDCFGR_SRDPPRE_0                    (0x1UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000010 */

+#define RCC_SRDCFGR_SRDPPRE_1                    (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */

+#define RCC_SRDCFGR_SRDPPRE_2                    (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */

+

+#define RCC_SRDCFGR_SRDPPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */

+#define RCC_SRDCFGR_SRDPPRE_DIV2_Pos             (6U)

+#define RCC_SRDCFGR_SRDPPRE_DIV2_Msk             (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_SRDCFGR_SRDPPRE_DIV2                 RCC_SRDCFGR_SRDPPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */

+#define RCC_SRDCFGR_SRDPPRE_DIV4_Pos             (4U)

+#define RCC_SRDCFGR_SRDPPRE_DIV4_Msk             (0x5UL << RCC_SRDCFGR_SRDPPRE_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_SRDCFGR_SRDPPRE_DIV4                 RCC_SRDCFGR_SRDPPRE_DIV4_Msk      /*!< APB4 clock divided by 4 */

+#define RCC_SRDCFGR_SRDPPRE_DIV8_Pos             (5U)

+#define RCC_SRDCFGR_SRDPPRE_DIV8_Msk             (0x3UL << RCC_SRDCFGR_SRDPPRE_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_SRDCFGR_SRDPPRE_DIV8                 RCC_SRDCFGR_SRDPPRE_DIV8_Msk      /*!< APB4 clock divided by 8 */

+#define RCC_SRDCFGR_SRDPPRE_DIV16_Pos            (4U)

+#define RCC_SRDCFGR_SRDPPRE_DIV16_Msk            (0x7UL << RCC_SRDCFGR_SRDPPRE_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_SRDCFGR_SRDPPRE_DIV16                RCC_SRDCFGR_SRDPPRE_DIV16_Msk     /*!< APB4 clock divided by 16 */

+

+/********************  Bit definition for RCC_PLLCKSELR register  *************/

+

+#define RCC_PLLCKSELR_PLLSRC_Pos               (0U)

+#define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */

+#define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk

+

+#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)

+#define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */

+#define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_HSE_Pos           (1U)

+#define RCC_PLLCKSELR_PLLSRC_HSE_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */

+#define RCC_PLLCKSELR_PLLSRC_HSE               RCC_PLLCKSELR_PLLSRC_HSE_Msk    /*!< HSE source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_NONE_Pos          (0U)

+#define RCC_PLLCKSELR_PLLSRC_NONE_Msk          (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */

+#define RCC_PLLCKSELR_PLLSRC_NONE              RCC_PLLCKSELR_PLLSRC_NONE_Msk   /*!< No source clock selected  */

+

+#define RCC_PLLCKSELR_DIVM1_Pos                (4U)

+#define RCC_PLLCKSELR_DIVM1_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */

+#define RCC_PLLCKSELR_DIVM1                    RCC_PLLCKSELR_DIVM1_Msk

+#define RCC_PLLCKSELR_DIVM1_0                  (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */

+#define RCC_PLLCKSELR_DIVM1_1                  (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */

+#define RCC_PLLCKSELR_DIVM1_2                  (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */

+#define RCC_PLLCKSELR_DIVM1_3                  (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */

+#define RCC_PLLCKSELR_DIVM1_4                  (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */

+#define RCC_PLLCKSELR_DIVM1_5                  (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */

+

+#define RCC_PLLCKSELR_DIVM2_Pos                (12U)

+#define RCC_PLLCKSELR_DIVM2_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */

+#define RCC_PLLCKSELR_DIVM2                    RCC_PLLCKSELR_DIVM2_Msk

+#define RCC_PLLCKSELR_DIVM2_0                  (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */

+#define RCC_PLLCKSELR_DIVM2_1                  (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */

+#define RCC_PLLCKSELR_DIVM2_2                  (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */

+#define RCC_PLLCKSELR_DIVM2_3                  (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */

+#define RCC_PLLCKSELR_DIVM2_4                  (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */

+#define RCC_PLLCKSELR_DIVM2_5                  (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */

+

+#define RCC_PLLCKSELR_DIVM3_Pos                (20U)

+#define RCC_PLLCKSELR_DIVM3_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */

+#define RCC_PLLCKSELR_DIVM3                    RCC_PLLCKSELR_DIVM3_Msk

+#define RCC_PLLCKSELR_DIVM3_0                  (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */

+#define RCC_PLLCKSELR_DIVM3_1                  (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */

+#define RCC_PLLCKSELR_DIVM3_2                  (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */

+#define RCC_PLLCKSELR_DIVM3_3                  (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */

+#define RCC_PLLCKSELR_DIVM3_4                  (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */

+#define RCC_PLLCKSELR_DIVM3_5                  (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */

+

+/********************  Bit definition for RCC_PLLCFGR register  ***************/

+

+#define RCC_PLLCFGR_PLL1FRACEN_Pos             (0U)

+#define RCC_PLLCFGR_PLL1FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */

+#define RCC_PLLCFGR_PLL1FRACEN                 RCC_PLLCFGR_PLL1FRACEN_Msk

+#define RCC_PLLCFGR_PLL1VCOSEL_Pos             (1U)

+#define RCC_PLLCFGR_PLL1VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */

+#define RCC_PLLCFGR_PLL1VCOSEL                 RCC_PLLCFGR_PLL1VCOSEL_Msk

+#define RCC_PLLCFGR_PLL1RGE_Pos                (2U)

+#define RCC_PLLCFGR_PLL1RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */

+#define RCC_PLLCFGR_PLL1RGE                    RCC_PLLCFGR_PLL1RGE_Msk

+#define RCC_PLLCFGR_PLL1RGE_0                  (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL1RGE_1                  (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */

+#define RCC_PLLCFGR_PLL1RGE_2                  (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */

+#define RCC_PLLCFGR_PLL1RGE_3                  (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */

+

+#define RCC_PLLCFGR_PLL2FRACEN_Pos             (4U)

+#define RCC_PLLCFGR_PLL2FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */

+#define RCC_PLLCFGR_PLL2FRACEN                 RCC_PLLCFGR_PLL2FRACEN_Msk

+#define RCC_PLLCFGR_PLL2VCOSEL_Pos             (5U)

+#define RCC_PLLCFGR_PLL2VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */

+#define RCC_PLLCFGR_PLL2VCOSEL                 RCC_PLLCFGR_PLL2VCOSEL_Msk

+#define RCC_PLLCFGR_PLL2RGE_Pos                (6U)

+#define RCC_PLLCFGR_PLL2RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */

+#define RCC_PLLCFGR_PLL2RGE                    RCC_PLLCFGR_PLL2RGE_Msk

+#define RCC_PLLCFGR_PLL2RGE_0                  (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL2RGE_1                  (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */

+#define RCC_PLLCFGR_PLL2RGE_2                  (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */

+#define RCC_PLLCFGR_PLL2RGE_3                  (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */

+

+#define RCC_PLLCFGR_PLL3FRACEN_Pos             (8U)

+#define RCC_PLLCFGR_PLL3FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */

+#define RCC_PLLCFGR_PLL3FRACEN                 RCC_PLLCFGR_PLL3FRACEN_Msk

+#define RCC_PLLCFGR_PLL3VCOSEL_Pos             (9U)

+#define RCC_PLLCFGR_PLL3VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */

+#define RCC_PLLCFGR_PLL3VCOSEL                 RCC_PLLCFGR_PLL3VCOSEL_Msk

+#define RCC_PLLCFGR_PLL3RGE_Pos                (10U)

+#define RCC_PLLCFGR_PLL3RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */

+#define RCC_PLLCFGR_PLL3RGE                    RCC_PLLCFGR_PLL3RGE_Msk

+#define RCC_PLLCFGR_PLL3RGE_0                  (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL3RGE_1                  (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */

+#define RCC_PLLCFGR_PLL3RGE_2                  (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */

+#define RCC_PLLCFGR_PLL3RGE_3                  (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */

+

+#define RCC_PLLCFGR_DIVP1EN_Pos                (16U)

+#define RCC_PLLCFGR_DIVP1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */

+#define RCC_PLLCFGR_DIVP1EN                    RCC_PLLCFGR_DIVP1EN_Msk

+#define RCC_PLLCFGR_DIVQ1EN_Pos                (17U)

+#define RCC_PLLCFGR_DIVQ1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */

+#define RCC_PLLCFGR_DIVQ1EN                    RCC_PLLCFGR_DIVQ1EN_Msk

+#define RCC_PLLCFGR_DIVR1EN_Pos                (18U)

+#define RCC_PLLCFGR_DIVR1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */

+#define RCC_PLLCFGR_DIVR1EN                    RCC_PLLCFGR_DIVR1EN_Msk

+

+#define RCC_PLLCFGR_DIVP2EN_Pos                (19U)

+#define RCC_PLLCFGR_DIVP2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */

+#define RCC_PLLCFGR_DIVP2EN                    RCC_PLLCFGR_DIVP2EN_Msk

+#define RCC_PLLCFGR_DIVQ2EN_Pos                (20U)

+#define RCC_PLLCFGR_DIVQ2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */

+#define RCC_PLLCFGR_DIVQ2EN                    RCC_PLLCFGR_DIVQ2EN_Msk

+#define RCC_PLLCFGR_DIVR2EN_Pos                (21U)

+#define RCC_PLLCFGR_DIVR2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */

+#define RCC_PLLCFGR_DIVR2EN                    RCC_PLLCFGR_DIVR2EN_Msk

+

+#define RCC_PLLCFGR_DIVP3EN_Pos                (22U)

+#define RCC_PLLCFGR_DIVP3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */

+#define RCC_PLLCFGR_DIVP3EN                    RCC_PLLCFGR_DIVP3EN_Msk

+#define RCC_PLLCFGR_DIVQ3EN_Pos                (23U)

+#define RCC_PLLCFGR_DIVQ3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */

+#define RCC_PLLCFGR_DIVQ3EN                    RCC_PLLCFGR_DIVQ3EN_Msk

+#define RCC_PLLCFGR_DIVR3EN_Pos                (24U)

+#define RCC_PLLCFGR_DIVR3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */

+#define RCC_PLLCFGR_DIVR3EN                    RCC_PLLCFGR_DIVR3EN_Msk

+

+

+/********************  Bit definition for RCC_PLL1DIVR register  ***************/

+#define RCC_PLL1DIVR_N1_Pos                    (0U)

+#define RCC_PLL1DIVR_N1_Msk                    (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */

+#define RCC_PLL1DIVR_N1                        RCC_PLL1DIVR_N1_Msk

+#define RCC_PLL1DIVR_P1_Pos                    (9U)

+#define RCC_PLL1DIVR_P1_Msk                    (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL1DIVR_P1                        RCC_PLL1DIVR_P1_Msk

+#define RCC_PLL1DIVR_Q1_Pos                    (16U)

+#define RCC_PLL1DIVR_Q1_Msk                    (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */

+#define RCC_PLL1DIVR_Q1                        RCC_PLL1DIVR_Q1_Msk

+#define RCC_PLL1DIVR_R1_Pos                    (24U)

+#define RCC_PLL1DIVR_R1_Msk                    (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */

+#define RCC_PLL1DIVR_R1                        RCC_PLL1DIVR_R1_Msk

+

+/********************  Bit definition for RCC_PLL1FRACR register  ***************/

+#define RCC_PLL1FRACR_FRACN1_Pos               (3U)

+#define RCC_PLL1FRACR_FRACN1_Msk               (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL1FRACR_FRACN1                   RCC_PLL1FRACR_FRACN1_Msk

+

+/********************  Bit definition for RCC_PLL2DIVR register  ***************/

+#define RCC_PLL2DIVR_N2_Pos                    (0U)

+#define RCC_PLL2DIVR_N2_Msk                    (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */

+#define RCC_PLL2DIVR_N2                        RCC_PLL2DIVR_N2_Msk

+#define RCC_PLL2DIVR_P2_Pos                    (9U)

+#define RCC_PLL2DIVR_P2_Msk                    (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL2DIVR_P2                        RCC_PLL2DIVR_P2_Msk

+#define RCC_PLL2DIVR_Q2_Pos                    (16U)

+#define RCC_PLL2DIVR_Q2_Msk                    (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */

+#define RCC_PLL2DIVR_Q2                        RCC_PLL2DIVR_Q2_Msk

+#define RCC_PLL2DIVR_R2_Pos                    (24U)

+#define RCC_PLL2DIVR_R2_Msk                    (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */

+#define RCC_PLL2DIVR_R2                        RCC_PLL2DIVR_R2_Msk

+

+/********************  Bit definition for RCC_PLL2FRACR register  ***************/

+#define RCC_PLL2FRACR_FRACN2_Pos               (3U)

+#define RCC_PLL2FRACR_FRACN2_Msk               (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL2FRACR_FRACN2                   RCC_PLL2FRACR_FRACN2_Msk

+

+/********************  Bit definition for RCC_PLL3DIVR register  ***************/

+#define RCC_PLL3DIVR_N3_Pos                    (0U)

+#define RCC_PLL3DIVR_N3_Msk                    (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */

+#define RCC_PLL3DIVR_N3                        RCC_PLL3DIVR_N3_Msk

+#define RCC_PLL3DIVR_P3_Pos                    (9U)

+#define RCC_PLL3DIVR_P3_Msk                    (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL3DIVR_P3                        RCC_PLL3DIVR_P3_Msk

+#define RCC_PLL3DIVR_Q3_Pos                    (16U)

+#define RCC_PLL3DIVR_Q3_Msk                    (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */

+#define RCC_PLL3DIVR_Q3                        RCC_PLL3DIVR_Q3_Msk

+#define RCC_PLL3DIVR_R3_Pos                    (24U)

+#define RCC_PLL3DIVR_R3_Msk                    (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */

+#define RCC_PLL3DIVR_R3                        RCC_PLL3DIVR_R3_Msk

+

+/********************  Bit definition for RCC_PLL3FRACR register  ***************/

+#define RCC_PLL3FRACR_FRACN3_Pos               (3U)

+#define RCC_PLL3FRACR_FRACN3_Msk               (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL3FRACR_FRACN3                   RCC_PLL3FRACR_FRACN3_Msk

+

+/********************  Bit definition for RCC_CDCCIPR register  ***************/

+#define RCC_CDCCIPR_FMCSEL_Pos                 (0U)

+#define RCC_CDCCIPR_FMCSEL_Msk                 (0x3UL << RCC_CDCCIPR_FMCSEL_Pos)     /*!< 0x00000003 */

+#define RCC_CDCCIPR_FMCSEL                     RCC_CDCCIPR_FMCSEL_Msk

+#define RCC_CDCCIPR_FMCSEL_0                   (0x1UL << RCC_CDCCIPR_FMCSEL_Pos)     /*!< 0x00000001 */

+#define RCC_CDCCIPR_FMCSEL_1                   (0x2UL << RCC_CDCCIPR_FMCSEL_Pos)     /*!< 0x00000002 */

+#define RCC_CDCCIPR_OCTOSPISEL_Pos             (4U)

+#define RCC_CDCCIPR_OCTOSPISEL_Msk             (0x3UL << RCC_CDCCIPR_OCTOSPISEL_Pos) /*!< 0x00000030 */

+#define RCC_CDCCIPR_OCTOSPISEL                 RCC_CDCCIPR_OCTOSPISEL_Msk

+#define RCC_CDCCIPR_OCTOSPISEL_0               (0x1UL << RCC_CDCCIPR_OCTOSPISEL_Pos) /*!< 0x00000010 */

+#define RCC_CDCCIPR_OCTOSPISEL_1               (0x2UL << RCC_CDCCIPR_OCTOSPISEL_Pos) /*!< 0x00000020 */

+#define RCC_CDCCIPR_SDMMCSEL_Pos               (16U)

+#define RCC_CDCCIPR_SDMMCSEL_Msk               (0x1UL << RCC_CDCCIPR_SDMMCSEL_Pos)   /*!< 0x00010000 */

+#define RCC_CDCCIPR_SDMMCSEL                   RCC_CDCCIPR_SDMMCSEL_Msk

+#define RCC_CDCCIPR_CKPERSEL_Pos               (28U)

+#define RCC_CDCCIPR_CKPERSEL_Msk               (0x3UL << RCC_CDCCIPR_CKPERSEL_Pos)   /*!< 0x30000000 */

+#define RCC_CDCCIPR_CKPERSEL                   RCC_CDCCIPR_CKPERSEL_Msk

+#define RCC_CDCCIPR_CKPERSEL_0                 (0x1UL << RCC_CDCCIPR_CKPERSEL_Pos)   /*!< 0x10000000 */

+#define RCC_CDCCIPR_CKPERSEL_1                 (0x2UL << RCC_CDCCIPR_CKPERSEL_Pos)   /*!< 0x20000000 */

+

+/********************  Bit definition for RCC_CDCCIP1R register  ***************/

+#define RCC_CDCCIP1R_SAI1SEL_Pos               (0U)

+#define RCC_CDCCIP1R_SAI1SEL_Msk               (0x7UL << RCC_CDCCIP1R_SAI1SEL_Pos)   /*!< 0x00000007 */

+#define RCC_CDCCIP1R_SAI1SEL                   RCC_CDCCIP1R_SAI1SEL_Msk

+#define RCC_CDCCIP1R_SAI1SEL_0                 (0x1UL << RCC_CDCCIP1R_SAI1SEL_Pos)   /*!< 0x00000001 */

+#define RCC_CDCCIP1R_SAI1SEL_1                 (0x2UL << RCC_CDCCIP1R_SAI1SEL_Pos)   /*!< 0x00000002 */

+#define RCC_CDCCIP1R_SAI1SEL_2                 (0x4UL << RCC_CDCCIP1R_SAI1SEL_Pos)   /*!< 0x00000004 */

+

+#define RCC_CDCCIP1R_SAI2ASEL_Pos              (6U)

+#define RCC_CDCCIP1R_SAI2ASEL_Msk              (0x7UL << RCC_CDCCIP1R_SAI2ASEL_Pos)  /*!< 0x000001C0 */

+#define RCC_CDCCIP1R_SAI2ASEL                  RCC_CDCCIP1R_SAI2ASEL_Msk

+#define RCC_CDCCIP1R_SAI2ASEL_0                (0x1UL << RCC_CDCCIP1R_SAI2ASEL_Pos)  /*!< 0x00000040 */

+#define RCC_CDCCIP1R_SAI2ASEL_1                (0x2UL << RCC_CDCCIP1R_SAI2ASEL_Pos)  /*!< 0x00000080 */

+#define RCC_CDCCIP1R_SAI2ASEL_2                (0x4UL << RCC_CDCCIP1R_SAI2ASEL_Pos)  /*!< 0x00000100 */

+

+#define RCC_CDCCIP1R_SAI2BSEL_Pos              (9U)

+#define RCC_CDCCIP1R_SAI2BSEL_Msk              (0x7UL << RCC_CDCCIP1R_SAI2BSEL_Pos)  /*!< 0x00000E00 */

+#define RCC_CDCCIP1R_SAI2BSEL                  RCC_CDCCIP1R_SAI2BSEL_Msk

+#define RCC_CDCCIP1R_SAI2BSEL_0                (0x1UL << RCC_CDCCIP1R_SAI2BSEL_Pos)  /*!< 0x00000200 */

+#define RCC_CDCCIP1R_SAI2BSEL_1                (0x2UL << RCC_CDCCIP1R_SAI2BSEL_Pos)  /*!< 0x00000400 */

+#define RCC_CDCCIP1R_SAI2BSEL_2                (0x4UL << RCC_CDCCIP1R_SAI2BSEL_Pos)  /*!< 0x00000800 */

+

+#define RCC_CDCCIP1R_SPI123SEL_Pos             (12U)

+#define RCC_CDCCIP1R_SPI123SEL_Msk             (0x7UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */

+#define RCC_CDCCIP1R_SPI123SEL                 RCC_CDCCIP1R_SPI123SEL_Msk

+#define RCC_CDCCIP1R_SPI123SEL_0               (0x1UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */

+#define RCC_CDCCIP1R_SPI123SEL_1               (0x2UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */

+#define RCC_CDCCIP1R_SPI123SEL_2               (0x4UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */

+

+#define RCC_CDCCIP1R_SPI45SEL_Pos              (16U)

+#define RCC_CDCCIP1R_SPI45SEL_Msk              (0x7UL << RCC_CDCCIP1R_SPI45SEL_Pos)  /*!< 0x00070000 */

+#define RCC_CDCCIP1R_SPI45SEL                  RCC_CDCCIP1R_SPI45SEL_Msk

+#define RCC_CDCCIP1R_SPI45SEL_0                (0x1UL << RCC_CDCCIP1R_SPI45SEL_Pos)  /*!< 0x00010000 */

+#define RCC_CDCCIP1R_SPI45SEL_1                (0x2UL << RCC_CDCCIP1R_SPI45SEL_Pos)  /*!< 0x00020000 */

+#define RCC_CDCCIP1R_SPI45SEL_2                (0x4UL << RCC_CDCCIP1R_SPI45SEL_Pos)  /*!< 0x00040000 */

+

+#define RCC_CDCCIP1R_SPDIFSEL_Pos              (20U)

+#define RCC_CDCCIP1R_SPDIFSEL_Msk              (0x3UL << RCC_CDCCIP1R_SPDIFSEL_Pos)  /*!< 0x00300000 */

+#define RCC_CDCCIP1R_SPDIFSEL                  RCC_CDCCIP1R_SPDIFSEL_Msk

+#define RCC_CDCCIP1R_SPDIFSEL_0                (0x1UL << RCC_CDCCIP1R_SPDIFSEL_Pos)  /*!< 0x00100000 */

+#define RCC_CDCCIP1R_SPDIFSEL_1                (0x2UL << RCC_CDCCIP1R_SPDIFSEL_Pos)  /*!< 0x00200000 */

+

+#define RCC_CDCCIP1R_DFSDM1SEL_Pos             (24U)

+#define RCC_CDCCIP1R_DFSDM1SEL_Msk             (0x1UL << RCC_CDCCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */

+#define RCC_CDCCIP1R_DFSDM1SEL                 RCC_CDCCIP1R_DFSDM1SEL_Msk

+

+#define RCC_CDCCIP1R_FDCANSEL_Pos              (28U)

+#define RCC_CDCCIP1R_FDCANSEL_Msk              (0x3UL << RCC_CDCCIP1R_FDCANSEL_Pos)  /*!< 0x30000000 */

+#define RCC_CDCCIP1R_FDCANSEL                  RCC_CDCCIP1R_FDCANSEL_Msk

+#define RCC_CDCCIP1R_FDCANSEL_0                (0x1UL << RCC_CDCCIP1R_FDCANSEL_Pos)  /*!< 0x10000000 */

+#define RCC_CDCCIP1R_FDCANSEL_1                (0x2UL << RCC_CDCCIP1R_FDCANSEL_Pos)  /*!< 0x20000000 */

+

+#define RCC_CDCCIP1R_SWPSEL_Pos                (31U)

+#define RCC_CDCCIP1R_SWPSEL_Msk                (0x1UL << RCC_CDCCIP1R_SWPSEL_Pos)    /*!< 0x80000000 */

+#define RCC_CDCCIP1R_SWPSEL                    RCC_CDCCIP1R_SWPSEL_Msk

+

+/********************  Bit definition for RCC_CDCCIP2R register  ***************/

+#define RCC_CDCCIP2R_USART234578SEL_Pos        (0U)

+#define RCC_CDCCIP2R_USART234578SEL_Msk        (0x7UL << RCC_CDCCIP2R_USART234578SEL_Pos)   /*!< 0x00000007 */

+#define RCC_CDCCIP2R_USART234578SEL            RCC_CDCCIP2R_USART234578SEL_Msk

+#define RCC_CDCCIP2R_USART234578SEL_0          (0x1UL << RCC_CDCCIP2R_USART234578SEL_Pos)   /*!< 0x00000001 */

+#define RCC_CDCCIP2R_USART234578SEL_1          (0x2UL << RCC_CDCCIP2R_USART234578SEL_Pos)   /*!< 0x00000002 */

+#define RCC_CDCCIP2R_USART234578SEL_2          (0x4UL << RCC_CDCCIP2R_USART234578SEL_Pos)   /*!< 0x00000004 */

+

+#define RCC_CDCCIP2R_USART16910SEL_Pos         (3U)

+#define RCC_CDCCIP2R_USART16910SEL_Msk         (0x7UL << RCC_CDCCIP2R_USART16910SEL_Pos)    /*!< 0x00000038 */

+#define RCC_CDCCIP2R_USART16910SEL             RCC_CDCCIP2R_USART16910SEL_Msk

+#define RCC_CDCCIP2R_USART16910SEL_0           (0x1UL << RCC_CDCCIP2R_USART16910SEL_Pos)    /*!< 0x00000008 */

+#define RCC_CDCCIP2R_USART16910SEL_1           (0x2UL << RCC_CDCCIP2R_USART16910SEL_Pos)    /*!< 0x00000010 */

+#define RCC_CDCCIP2R_USART16910SEL_2           (0x4UL << RCC_CDCCIP2R_USART16910SEL_Pos)    /*!< 0x00000020 */

+

+#define RCC_CDCCIP2R_RNGSEL_Pos                (8U)

+#define RCC_CDCCIP2R_RNGSEL_Msk                (0x3UL << RCC_CDCCIP2R_RNGSEL_Pos)           /*!< 0x00000300 */

+#define RCC_CDCCIP2R_RNGSEL                    RCC_CDCCIP2R_RNGSEL_Msk

+#define RCC_CDCCIP2R_RNGSEL_0                  (0x1UL << RCC_CDCCIP2R_RNGSEL_Pos)           /*!< 0x00000100 */

+#define RCC_CDCCIP2R_RNGSEL_1                  (0x2UL << RCC_CDCCIP2R_RNGSEL_Pos)           /*!< 0x00000200 */

+

+#define RCC_CDCCIP2R_I2C123SEL_Pos             (12U)

+#define RCC_CDCCIP2R_I2C123SEL_Msk             (0x3UL << RCC_CDCCIP2R_I2C123SEL_Pos)        /*!< 0x00003000 */

+#define RCC_CDCCIP2R_I2C123SEL                 RCC_CDCCIP2R_I2C123SEL_Msk

+#define RCC_CDCCIP2R_I2C123SEL_0               (0x1UL << RCC_CDCCIP2R_I2C123SEL_Pos)        /*!< 0x00001000 */

+#define RCC_CDCCIP2R_I2C123SEL_1               (0x2UL << RCC_CDCCIP2R_I2C123SEL_Pos)        /*!< 0x00002000 */

+

+#define RCC_CDCCIP2R_USBSEL_Pos                (20U)

+#define RCC_CDCCIP2R_USBSEL_Msk                (0x3UL << RCC_CDCCIP2R_USBSEL_Pos)           /*!< 0x00300000 */

+#define RCC_CDCCIP2R_USBSEL                    RCC_CDCCIP2R_USBSEL_Msk

+#define RCC_CDCCIP2R_USBSEL_0                  (0x1UL << RCC_CDCCIP2R_USBSEL_Pos)           /*!< 0x00100000 */

+#define RCC_CDCCIP2R_USBSEL_1                  (0x2UL << RCC_CDCCIP2R_USBSEL_Pos)           /*!< 0x00200000 */

+

+#define RCC_CDCCIP2R_CECSEL_Pos                (22U)

+#define RCC_CDCCIP2R_CECSEL_Msk                (0x3UL << RCC_CDCCIP2R_CECSEL_Pos)           /*!< 0x00C00000 */

+#define RCC_CDCCIP2R_CECSEL                    RCC_CDCCIP2R_CECSEL_Msk

+#define RCC_CDCCIP2R_CECSEL_0                  (0x1UL << RCC_CDCCIP2R_CECSEL_Pos)           /*!< 0x00400000 */

+#define RCC_CDCCIP2R_CECSEL_1                  (0x2UL << RCC_CDCCIP2R_CECSEL_Pos)           /*!< 0x00800000 */

+

+#define RCC_CDCCIP2R_LPTIM1SEL_Pos             (28U)

+#define RCC_CDCCIP2R_LPTIM1SEL_Msk             (0x7UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)        /*!< 0x70000000 */

+#define RCC_CDCCIP2R_LPTIM1SEL                 RCC_CDCCIP2R_LPTIM1SEL_Msk

+#define RCC_CDCCIP2R_LPTIM1SEL_0               (0x1UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)        /*!< 0x10000000 */

+#define RCC_CDCCIP2R_LPTIM1SEL_1               (0x2UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)        /*!< 0x20000000 */

+#define RCC_CDCCIP2R_LPTIM1SEL_2               (0x4UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)        /*!< 0x40000000 */

+

+/********************  Bit definition for RCC_SRDCCIPR register  ***************/

+#define RCC_SRDCCIPR_LPUART1SEL_Pos             (0U)

+#define RCC_SRDCCIPR_LPUART1SEL_Msk             (0x7UL << RCC_SRDCCIPR_LPUART1SEL_Pos)      /*!< 0x00000007 */

+#define RCC_SRDCCIPR_LPUART1SEL                 RCC_SRDCCIPR_LPUART1SEL_Msk

+#define RCC_SRDCCIPR_LPUART1SEL_0               (0x1UL << RCC_SRDCCIPR_LPUART1SEL_Pos)      /*!< 0x00000001 */

+#define RCC_SRDCCIPR_LPUART1SEL_1               (0x2UL << RCC_SRDCCIPR_LPUART1SEL_Pos)      /*!< 0x00000002 */

+#define RCC_SRDCCIPR_LPUART1SEL_2               (0x4UL << RCC_SRDCCIPR_LPUART1SEL_Pos)      /*!< 0x00000004 */

+

+#define RCC_SRDCCIPR_I2C4SEL_Pos                (8U)

+#define RCC_SRDCCIPR_I2C4SEL_Msk                (0x3UL << RCC_SRDCCIPR_I2C4SEL_Pos)         /*!< 0x00000300 */

+#define RCC_SRDCCIPR_I2C4SEL                    RCC_SRDCCIPR_I2C4SEL_Msk

+#define RCC_SRDCCIPR_I2C4SEL_0                  (0x1UL << RCC_SRDCCIPR_I2C4SEL_Pos)         /*!< 0x00000100 */

+#define RCC_SRDCCIPR_I2C4SEL_1                  (0x2UL << RCC_SRDCCIPR_I2C4SEL_Pos)         /*!< 0x00000200 */

+

+#define RCC_SRDCCIPR_LPTIM2SEL_Pos              (10U)

+#define RCC_SRDCCIPR_LPTIM2SEL_Msk              (0x7UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)       /*!< 0x00001C00 */

+#define RCC_SRDCCIPR_LPTIM2SEL                  RCC_SRDCCIPR_LPTIM2SEL_Msk

+#define RCC_SRDCCIPR_LPTIM2SEL_0                (0x1UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)       /*!< 0x00000400 */

+#define RCC_SRDCCIPR_LPTIM2SEL_1                (0x2UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)       /*!< 0x00000800 */

+#define RCC_SRDCCIPR_LPTIM2SEL_2                (0x4UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)       /*!< 0x00001000 */

+

+#define RCC_SRDCCIPR_LPTIM3SEL_Pos            (13U)

+#define RCC_SRDCCIPR_LPTIM3SEL_Msk            (0x7UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)         /*!< 0x0000E000 */

+#define RCC_SRDCCIPR_LPTIM3SEL                RCC_SRDCCIPR_LPTIM3SEL_Msk

+#define RCC_SRDCCIPR_LPTIM3SEL_0              (0x1UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)         /*!< 0x00002000 */

+#define RCC_SRDCCIPR_LPTIM3SEL_1              (0x2UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)         /*!< 0x00004000 */

+#define RCC_SRDCCIPR_LPTIM3SEL_2              (0x4UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)         /*!< 0x00008000 */

+

+#define RCC_SRDCCIPR_ADCSEL_Pos                 (16U)

+#define RCC_SRDCCIPR_ADCSEL_Msk                 (0x3UL << RCC_SRDCCIPR_ADCSEL_Pos)          /*!< 0x00030000 */

+#define RCC_SRDCCIPR_ADCSEL                     RCC_SRDCCIPR_ADCSEL_Msk

+#define RCC_SRDCCIPR_ADCSEL_0                   (0x1UL << RCC_SRDCCIPR_ADCSEL_Pos)          /*!< 0x00010000 */

+#define RCC_SRDCCIPR_ADCSEL_1                   (0x2UL << RCC_SRDCCIPR_ADCSEL_Pos)          /*!< 0x00020000 */

+

+#define RCC_SRDCCIPR_DFSDM2SEL_Pos              (27U)

+#define RCC_SRDCCIPR_DFSDM2SEL_Msk              (0x1UL << RCC_SRDCCIPR_DFSDM2SEL_Pos)       /*!< 0x08000000 */

+#define RCC_SRDCCIPR_DFSDM2SEL                   RCC_SRDCCIPR_DFSDM2SEL_Msk

+

+#define RCC_SRDCCIPR_SPI6SEL_Pos                (28U)

+#define RCC_SRDCCIPR_SPI6SEL_Msk                (0x7UL << RCC_SRDCCIPR_SPI6SEL_Pos)         /*!< 0x70000000 */

+#define RCC_SRDCCIPR_SPI6SEL                    RCC_SRDCCIPR_SPI6SEL_Msk

+#define RCC_SRDCCIPR_SPI6SEL_0                  (0x1UL << RCC_SRDCCIPR_SPI6SEL_Pos)         /*!< 0x10000000 */

+#define RCC_SRDCCIPR_SPI6SEL_1                  (0x2UL << RCC_SRDCCIPR_SPI6SEL_Pos)         /*!< 0x20000000 */

+#define RCC_SRDCCIPR_SPI6SEL_2                  (0x4UL << RCC_SRDCCIPR_SPI6SEL_Pos)         /*!< 0x40000000 */

+

+/********************  Bit definition for RCC_CIER register  ******************/

+#define RCC_CIER_LSIRDYIE_Pos                  (0U)

+#define RCC_CIER_LSIRDYIE_Msk                  (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */

+#define RCC_CIER_LSIRDYIE                      RCC_CIER_LSIRDYIE_Msk

+#define RCC_CIER_LSERDYIE_Pos                  (1U)

+#define RCC_CIER_LSERDYIE_Msk                  (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */

+#define RCC_CIER_LSERDYIE                      RCC_CIER_LSERDYIE_Msk

+#define RCC_CIER_HSIRDYIE_Pos                  (2U)

+#define RCC_CIER_HSIRDYIE_Msk                  (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */

+#define RCC_CIER_HSIRDYIE                      RCC_CIER_HSIRDYIE_Msk

+#define RCC_CIER_HSERDYIE_Pos                  (3U)

+#define RCC_CIER_HSERDYIE_Msk                  (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */

+#define RCC_CIER_HSERDYIE                      RCC_CIER_HSERDYIE_Msk

+#define RCC_CIER_CSIRDYIE_Pos                  (4U)

+#define RCC_CIER_CSIRDYIE_Msk                  (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */

+#define RCC_CIER_CSIRDYIE                      RCC_CIER_CSIRDYIE_Msk

+#define RCC_CIER_HSI48RDYIE_Pos                (5U)

+#define RCC_CIER_HSI48RDYIE_Msk                (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */

+#define RCC_CIER_HSI48RDYIE                    RCC_CIER_HSI48RDYIE_Msk

+#define RCC_CIER_PLL1RDYIE_Pos                 (6U)

+#define RCC_CIER_PLL1RDYIE_Msk                 (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */

+#define RCC_CIER_PLL1RDYIE                     RCC_CIER_PLL1RDYIE_Msk

+#define RCC_CIER_PLL2RDYIE_Pos                 (7U)

+#define RCC_CIER_PLL2RDYIE_Msk                 (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */

+#define RCC_CIER_PLL2RDYIE                     RCC_CIER_PLL2RDYIE_Msk

+#define RCC_CIER_PLL3RDYIE_Pos                 (8U)

+#define RCC_CIER_PLL3RDYIE_Msk                 (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */

+#define RCC_CIER_PLL3RDYIE                     RCC_CIER_PLL3RDYIE_Msk

+#define RCC_CIER_LSECSSIE_Pos                  (9U)

+#define RCC_CIER_LSECSSIE_Msk                  (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */

+#define RCC_CIER_LSECSSIE                      RCC_CIER_LSECSSIE_Msk

+

+/********************  Bit definition for RCC_CIFR register  ******************/

+#define RCC_CIFR_LSIRDYF_Pos                   (0U)

+#define RCC_CIFR_LSIRDYF_Msk                   (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */

+#define RCC_CIFR_LSIRDYF                       RCC_CIFR_LSIRDYF_Msk

+#define RCC_CIFR_LSERDYF_Pos                   (1U)

+#define RCC_CIFR_LSERDYF_Msk                   (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */

+#define RCC_CIFR_LSERDYF                       RCC_CIFR_LSERDYF_Msk

+#define RCC_CIFR_HSIRDYF_Pos                   (2U)

+#define RCC_CIFR_HSIRDYF_Msk                   (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */

+#define RCC_CIFR_HSIRDYF                       RCC_CIFR_HSIRDYF_Msk

+#define RCC_CIFR_HSERDYF_Pos                   (3U)

+#define RCC_CIFR_HSERDYF_Msk                   (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */

+#define RCC_CIFR_HSERDYF                       RCC_CIFR_HSERDYF_Msk

+#define RCC_CIFR_CSIRDYF_Pos                   (4U)

+#define RCC_CIFR_CSIRDYF_Msk                   (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */

+#define RCC_CIFR_CSIRDYF                       RCC_CIFR_CSIRDYF_Msk

+#define RCC_CIFR_HSI48RDYF_Pos                 (5U)

+#define RCC_CIFR_HSI48RDYF_Msk                 (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */

+#define RCC_CIFR_HSI48RDYF                     RCC_CIFR_HSI48RDYF_Msk

+#define RCC_CIFR_PLLRDYF_Pos                   (6U)

+#define RCC_CIFR_PLLRDYF_Msk                   (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */

+#define RCC_CIFR_PLLRDYF                       RCC_CIFR_PLLRDYF_Msk

+#define RCC_CIFR_PLL2RDYF_Pos                  (7U)

+#define RCC_CIFR_PLL2RDYF_Msk                  (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */

+#define RCC_CIFR_PLL2RDYF                      RCC_CIFR_PLL2RDYF_Msk

+#define RCC_CIFR_PLL3RDYF_Pos                  (8U)

+#define RCC_CIFR_PLL3RDYF_Msk                  (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */

+#define RCC_CIFR_PLL3RDYF                      RCC_CIFR_PLL3RDYF_Msk

+#define RCC_CIFR_LSECSSF_Pos                   (9U)

+#define RCC_CIFR_LSECSSF_Msk                   (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */

+#define RCC_CIFR_LSECSSF                       RCC_CIFR_LSECSSF_Msk

+#define RCC_CIFR_HSECSSF_Pos                   (10U)

+#define RCC_CIFR_HSECSSF_Msk                   (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */

+#define RCC_CIFR_HSECSSF                       RCC_CIFR_HSECSSF_Msk

+

+/********************  Bit definition for RCC_CICR register  ******************/

+#define RCC_CICR_LSIRDYC_Pos                   (0U)

+#define RCC_CICR_LSIRDYC_Msk                   (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */

+#define RCC_CICR_LSIRDYC                       RCC_CICR_LSIRDYC_Msk

+#define RCC_CICR_LSERDYC_Pos                   (1U)

+#define RCC_CICR_LSERDYC_Msk                   (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */

+#define RCC_CICR_LSERDYC                       RCC_CICR_LSERDYC_Msk

+#define RCC_CICR_HSIRDYC_Pos                   (2U)

+#define RCC_CICR_HSIRDYC_Msk                   (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */

+#define RCC_CICR_HSIRDYC                       RCC_CICR_HSIRDYC_Msk

+#define RCC_CICR_HSERDYC_Pos                   (3U)

+#define RCC_CICR_HSERDYC_Msk                   (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */

+#define RCC_CICR_HSERDYC                       RCC_CICR_HSERDYC_Msk

+#define RCC_CICR_CSIRDYC_Pos                   (4U)

+#define RCC_CICR_CSIRDYC_Msk                   (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */

+#define RCC_CICR_CSIRDYC                       RCC_CICR_CSIRDYC_Msk

+#define RCC_CICR_HSI48RDYC_Pos                 (5U)

+#define RCC_CICR_HSI48RDYC_Msk                 (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */

+#define RCC_CICR_HSI48RDYC                     RCC_CICR_HSI48RDYC_Msk

+#define RCC_CICR_PLLRDYC_Pos                   (6U)

+#define RCC_CICR_PLLRDYC_Msk                   (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */

+#define RCC_CICR_PLLRDYC                       RCC_CICR_PLLRDYC_Msk

+#define RCC_CICR_PLL2RDYC_Pos                  (7U)

+#define RCC_CICR_PLL2RDYC_Msk                  (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */

+#define RCC_CICR_PLL2RDYC                      RCC_CICR_PLL2RDYC_Msk

+#define RCC_CICR_PLL3RDYC_Pos                  (8U)

+#define RCC_CICR_PLL3RDYC_Msk                  (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */

+#define RCC_CICR_PLL3RDYC                      RCC_CICR_PLL3RDYC_Msk

+#define RCC_CICR_LSECSSC_Pos                   (9U)

+#define RCC_CICR_LSECSSC_Msk                   (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */

+#define RCC_CICR_LSECSSC                       RCC_CICR_LSECSSC_Msk

+#define RCC_CICR_HSECSSC_Pos                   (10U)

+#define RCC_CICR_HSECSSC_Msk                   (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */

+#define RCC_CICR_HSECSSC                       RCC_CICR_HSECSSC_Msk

+

+/********************  Bit definition for RCC_BDCR register  ******************/

+#define RCC_BDCR_LSEON_Pos                     (0U)

+#define RCC_BDCR_LSEON_Msk                     (0x1UL << RCC_BDCR_LSEON_Pos)   /*!< 0x00000001 */

+#define RCC_BDCR_LSEON                         RCC_BDCR_LSEON_Msk

+#define RCC_BDCR_LSERDY_Pos                    (1U)

+#define RCC_BDCR_LSERDY_Msk                    (0x1UL << RCC_BDCR_LSERDY_Pos)  /*!< 0x00000002 */

+#define RCC_BDCR_LSERDY                        RCC_BDCR_LSERDY_Msk

+#define RCC_BDCR_LSEBYP_Pos                    (2U)

+#define RCC_BDCR_LSEBYP_Msk                    (0x1UL << RCC_BDCR_LSEBYP_Pos)  /*!< 0x00000004 */

+#define RCC_BDCR_LSEBYP                        RCC_BDCR_LSEBYP_Msk

+

+#define RCC_BDCR_LSEDRV_Pos                    (3U)

+#define RCC_BDCR_LSEDRV_Msk                    (0x3UL << RCC_BDCR_LSEDRV_Pos)  /*!< 0x00000018 */

+#define RCC_BDCR_LSEDRV                        RCC_BDCR_LSEDRV_Msk

+#define RCC_BDCR_LSEDRV_0                      (0x1UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000008 */

+#define RCC_BDCR_LSEDRV_1                      (0x2UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000010 */

+

+#define RCC_BDCR_LSECSSON_Pos                  (5U)

+#define RCC_BDCR_LSECSSON_Msk                  (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */

+#define RCC_BDCR_LSECSSON                      RCC_BDCR_LSECSSON_Msk

+#define RCC_BDCR_LSECSSD_Pos                   (6U)

+#define RCC_BDCR_LSECSSD_Msk                   (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */

+#define RCC_BDCR_LSECSSD                       RCC_BDCR_LSECSSD_Msk

+#define RCC_BDCR_LSEEXT_Pos                    (7U)

+#define RCC_BDCR_LSEEXT_Msk                    (0x1UL << RCC_BDCR_LSEEXT_Pos)  /*!< 0x00000080 */

+#define RCC_BDCR_LSEEXT                        RCC_BDCR_LSEEXT_Msk

+

+#define RCC_BDCR_RTCSEL_Pos                    (8U)

+#define RCC_BDCR_RTCSEL_Msk                    (0x3UL << RCC_BDCR_RTCSEL_Pos)  /*!< 0x00000300 */

+#define RCC_BDCR_RTCSEL                        RCC_BDCR_RTCSEL_Msk

+#define RCC_BDCR_RTCSEL_0                      (0x1UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000100 */

+#define RCC_BDCR_RTCSEL_1                      (0x2UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000200 */

+

+#define RCC_BDCR_RTCEN_Pos                     (15U)

+#define RCC_BDCR_RTCEN_Msk                     (0x1UL << RCC_BDCR_RTCEN_Pos)   /*!< 0x00008000 */

+#define RCC_BDCR_RTCEN                         RCC_BDCR_RTCEN_Msk

+#define RCC_BDCR_VSWRST_Pos                    (16U)

+#define RCC_BDCR_VSWRST_Msk                    (0x1UL << RCC_BDCR_VSWRST_Pos)   /*!< 0x00010000 */

+#define RCC_BDCR_VSWRST                        RCC_BDCR_VSWRST_Msk

+/* Legacy define */

+#define RCC_BDCR_BDRST_Pos                     RCC_BDCR_VSWRST_Pos

+#define RCC_BDCR_BDRST_Msk                     RCC_BDCR_VSWRST_Msk

+#define RCC_BDCR_BDRST                         RCC_BDCR_VSWRST

+/********************  Bit definition for RCC_CSR register  *******************/

+#define RCC_CSR_LSION_Pos                      (0U)

+#define RCC_CSR_LSION_Msk                      (0x1UL << RCC_CSR_LSION_Pos)    /*!< 0x00000001 */

+#define RCC_CSR_LSION                          RCC_CSR_LSION_Msk

+#define RCC_CSR_LSIRDY_Pos                     (1U)

+#define RCC_CSR_LSIRDY_Msk                     (0x1UL << RCC_CSR_LSIRDY_Pos)   /*!< 0x00000002 */

+#define RCC_CSR_LSIRDY                         RCC_CSR_LSIRDY_Msk

+

+

+/********************  Bit definition for RCC_AHB3ENR register  **************/

+#define RCC_AHB3ENR_MDMAEN_Pos                 (0U)

+#define RCC_AHB3ENR_MDMAEN_Msk                 (0x1UL << RCC_AHB3ENR_MDMAEN_Pos)       /*!< 0x00000001 */

+#define RCC_AHB3ENR_MDMAEN                     RCC_AHB3ENR_MDMAEN_Msk

+#define RCC_AHB3ENR_DMA2DEN_Pos                (4U)

+#define RCC_AHB3ENR_DMA2DEN_Msk                (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos)      /*!< 0x00000010 */

+#define RCC_AHB3ENR_DMA2DEN                    RCC_AHB3ENR_DMA2DEN_Msk

+#define RCC_AHB3ENR_JPGDECEN_Pos               (5U)

+#define RCC_AHB3ENR_JPGDECEN_Msk               (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos)     /*!< 0x00000020 */

+#define RCC_AHB3ENR_JPGDECEN                   RCC_AHB3ENR_JPGDECEN_Msk

+#define RCC_AHB3ENR_FMCEN_Pos                  (12U)

+#define RCC_AHB3ENR_FMCEN_Msk                  (0x1UL << RCC_AHB3ENR_FMCEN_Pos)        /*!< 0x00001000 */

+#define RCC_AHB3ENR_FMCEN                      RCC_AHB3ENR_FMCEN_Msk

+#define RCC_AHB3ENR_OSPI1EN_Pos                (14U)

+#define RCC_AHB3ENR_OSPI1EN_Msk                (0x1UL << RCC_AHB3ENR_OSPI1EN_Pos)      /*!< 0x00004000 */

+#define RCC_AHB3ENR_OSPI1EN                    RCC_AHB3ENR_OSPI1EN_Msk

+#define RCC_AHB3ENR_SDMMC1EN_Pos               (16U)

+#define RCC_AHB3ENR_SDMMC1EN_Msk               (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos)     /*!< 0x00010000 */

+#define RCC_AHB3ENR_SDMMC1EN                   RCC_AHB3ENR_SDMMC1EN_Msk

+#define RCC_AHB3ENR_OSPI2EN_Pos                (19U)

+#define RCC_AHB3ENR_OSPI2EN_Msk                (0x1UL << RCC_AHB3ENR_OSPI2EN_Pos)      /*!< 0x00040000 */

+#define RCC_AHB3ENR_OSPI2EN                    RCC_AHB3ENR_OSPI2EN_Msk

+#define RCC_AHB3ENR_IOMNGREN_Pos               (21U)

+#define RCC_AHB3ENR_IOMNGREN_Msk               (0x1UL << RCC_AHB3ENR_IOMNGREN_Pos)     /*!< 0x00100000 */

+#define RCC_AHB3ENR_IOMNGREN                   RCC_AHB3ENR_IOMNGREN_Msk

+#define RCC_AHB3ENR_GFXMMUEN_Pos               (24U)

+#define RCC_AHB3ENR_GFXMMUEN_Msk               (0x1UL << RCC_AHB3ENR_GFXMMUEN_Pos)     /*!< 0x00800000 */

+#define RCC_AHB3ENR_GFXMMUEN                   RCC_AHB3ENR_GFXMMUEN_Msk

+

+/********************  Bit definition for RCC_AHB1ENR register  ***************/

+#define RCC_AHB1ENR_DMA1EN_Pos                 (0U)

+#define RCC_AHB1ENR_DMA1EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)          /*!< 0x00000001 */

+#define RCC_AHB1ENR_DMA1EN                     RCC_AHB1ENR_DMA1EN_Msk

+#define RCC_AHB1ENR_DMA2EN_Pos                 (1U)

+#define RCC_AHB1ENR_DMA2EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)          /*!< 0x00000002 */

+#define RCC_AHB1ENR_DMA2EN                     RCC_AHB1ENR_DMA2EN_Msk

+#define RCC_AHB1ENR_ADC12EN_Pos                (5U)

+#define RCC_AHB1ENR_ADC12EN_Msk                (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)         /*!< 0x00000020 */

+#define RCC_AHB1ENR_ADC12EN                    RCC_AHB1ENR_ADC12EN_Msk

+#define RCC_AHB1ENR_CRCEN_Pos                  (9U)

+#define RCC_AHB1ENR_CRCEN_Msk                  (0x1UL << RCC_AHB1ENR_CRCEN_Pos)           /*!< 0x00000200 */

+#define RCC_AHB1ENR_CRCEN                      RCC_AHB1ENR_CRCEN_Msk

+#define RCC_AHB1ENR_USB1OTGHSEN_Pos            (25U)

+#define RCC_AHB1ENR_USB1OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos)     /*!< 0x02000000 */

+#define RCC_AHB1ENR_USB1OTGHSEN                RCC_AHB1ENR_USB1OTGHSEN_Msk

+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos        (26U)

+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */

+#define RCC_AHB1ENR_USB1OTGHSULPIEN            RCC_AHB1ENR_USB1OTGHSULPIEN_Msk

+

+/********************  Bit definition for RCC_AHB2ENR register  ***************/

+#define RCC_AHB2ENR_DCMI_PSSIEN_Pos            (0U)

+#define RCC_AHB2ENR_DCMI_PSSIEN_Msk            (0x1UL << RCC_AHB2ENR_DCMI_PSSIEN_Pos)     /*!< 0x00000001 */

+#define RCC_AHB2ENR_DCMI_PSSIEN                RCC_AHB2ENR_DCMI_PSSIEN_Msk

+#define RCC_AHB2ENR_HSEMEN_Pos                 (2U)

+#define RCC_AHB2ENR_HSEMEN_Msk                 (0x1UL << RCC_AHB2ENR_HSEMEN_Pos)          /*!< 0x00000004 */

+#define RCC_AHB2ENR_HSEMEN                     RCC_AHB2ENR_HSEMEN_Msk

+#define RCC_AHB2ENR_RNGEN_Pos                  (6U)

+#define RCC_AHB2ENR_RNGEN_Msk                  (0x1UL << RCC_AHB2ENR_RNGEN_Pos)           /*!< 0x00000040 */

+#define RCC_AHB2ENR_RNGEN                      RCC_AHB2ENR_RNGEN_Msk

+#define RCC_AHB2ENR_SDMMC2EN_Pos               (9U)

+#define RCC_AHB2ENR_SDMMC2EN_Msk               (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)        /*!< 0x00000200 */

+#define RCC_AHB2ENR_SDMMC2EN                   RCC_AHB2ENR_SDMMC2EN_Msk

+#define RCC_AHB2ENR_BDMA1EN_Pos                (11U)

+#define RCC_AHB2ENR_BDMA1EN_Msk                (0x1UL << RCC_AHB2ENR_BDMA1EN_Pos)         /*!< 0x00000800 */

+#define RCC_AHB2ENR_BDMA1EN                    RCC_AHB2ENR_BDMA1EN_Msk

+#define RCC_AHB2ENR_AHBSRAM1EN_Pos             (29U)

+#define RCC_AHB2ENR_AHBSRAM1EN_Msk             (0x1UL << RCC_AHB2ENR_AHBSRAM1EN_Pos)       /*!< 0x20000000 */

+#define RCC_AHB2ENR_AHBSRAM1EN                 RCC_AHB2ENR_AHBSRAM1EN_Msk

+#define RCC_AHB2ENR_AHBSRAM2EN_Pos             (30U)

+#define RCC_AHB2ENR_AHBSRAM2EN_Msk             (0x1UL << RCC_AHB2ENR_AHBSRAM2EN_Pos)       /*!< 0x40000000 */

+#define RCC_AHB2ENR_AHBSRAM2EN                 RCC_AHB2ENR_AHBSRAM2EN_Msk

+

+/* Legacy define */

+#define RCC_AHB2ENR_DCMIEN_Pos                 RCC_AHB2ENR_DCMI_PSSIEN_Pos

+#define RCC_AHB2ENR_DCMIEN_Msk                 RCC_AHB2ENR_DCMI_PSSIEN_Msk

+#define RCC_AHB2ENR_DCMIEN                     RCC_AHB2ENR_DCMI_PSSIEN

+

+/********************  Bit definition for RCC_AHB4ENR register  ******************/

+#define RCC_AHB4ENR_GPIOAEN_Pos                (0U)

+#define RCC_AHB4ENR_GPIOAEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)         /*!< 0x00000001 */

+#define RCC_AHB4ENR_GPIOAEN                    RCC_AHB4ENR_GPIOAEN_Msk

+#define RCC_AHB4ENR_GPIOBEN_Pos                (1U)

+#define RCC_AHB4ENR_GPIOBEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)         /*!< 0x00000002 */

+#define RCC_AHB4ENR_GPIOBEN                    RCC_AHB4ENR_GPIOBEN_Msk

+#define RCC_AHB4ENR_GPIOCEN_Pos                (2U)

+#define RCC_AHB4ENR_GPIOCEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)         /*!< 0x00000004 */

+#define RCC_AHB4ENR_GPIOCEN                    RCC_AHB4ENR_GPIOCEN_Msk

+#define RCC_AHB4ENR_GPIODEN_Pos                (3U)

+#define RCC_AHB4ENR_GPIODEN_Msk                (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)         /*!< 0x00000008 */

+#define RCC_AHB4ENR_GPIODEN                    RCC_AHB4ENR_GPIODEN_Msk

+#define RCC_AHB4ENR_GPIOEEN_Pos                (4U)

+#define RCC_AHB4ENR_GPIOEEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)         /*!< 0x00000010 */

+#define RCC_AHB4ENR_GPIOEEN                    RCC_AHB4ENR_GPIOEEN_Msk

+#define RCC_AHB4ENR_GPIOFEN_Pos                (5U)

+#define RCC_AHB4ENR_GPIOFEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)         /*!< 0x00000020 */

+#define RCC_AHB4ENR_GPIOFEN                    RCC_AHB4ENR_GPIOFEN_Msk

+#define RCC_AHB4ENR_GPIOGEN_Pos                (6U)

+#define RCC_AHB4ENR_GPIOGEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)         /*!< 0x00000040 */

+#define RCC_AHB4ENR_GPIOGEN                    RCC_AHB4ENR_GPIOGEN_Msk

+#define RCC_AHB4ENR_GPIOHEN_Pos                (7U)

+#define RCC_AHB4ENR_GPIOHEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)         /*!< 0x00000080 */

+#define RCC_AHB4ENR_GPIOHEN                    RCC_AHB4ENR_GPIOHEN_Msk

+#define RCC_AHB4ENR_GPIOIEN_Pos                (8U)

+#define RCC_AHB4ENR_GPIOIEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos)         /*!< 0x00000100 */

+#define RCC_AHB4ENR_GPIOIEN                    RCC_AHB4ENR_GPIOIEN_Msk

+#define RCC_AHB4ENR_GPIOJEN_Pos                (9U)

+#define RCC_AHB4ENR_GPIOJEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos)         /*!< 0x00000200 */

+#define RCC_AHB4ENR_GPIOJEN                    RCC_AHB4ENR_GPIOJEN_Msk

+#define RCC_AHB4ENR_GPIOKEN_Pos                (10U)

+#define RCC_AHB4ENR_GPIOKEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos)         /*!< 0x00000400 */

+#define RCC_AHB4ENR_GPIOKEN                    RCC_AHB4ENR_GPIOKEN_Msk

+#define RCC_AHB4ENR_BDMA2EN_Pos                (21U)

+#define RCC_AHB4ENR_BDMA2EN_Msk                (0x1UL << RCC_AHB4ENR_BDMA2EN_Pos)         /*!< 0x00080000 */

+#define RCC_AHB4ENR_BDMA2EN                    RCC_AHB4ENR_BDMA2EN_Msk

+#define RCC_AHB4ENR_BKPRAMEN_Pos               (28U)

+#define RCC_AHB4ENR_BKPRAMEN_Msk               (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)        /*!< 0x10000000 */

+#define RCC_AHB4ENR_BKPRAMEN                   RCC_AHB4ENR_BKPRAMEN_Msk

+#define RCC_AHB4ENR_SRDSRAMEN_Pos              (29U)

+#define RCC_AHB4ENR_SRDSRAMEN_Msk              (0x1UL << RCC_AHB4ENR_SRDSRAMEN_Pos)       /*!< 0x20000000 */

+#define RCC_AHB4ENR_SRDSRAMEN                  RCC_AHB4ENR_SRDSRAMEN_Msk

+

+/********************  Bit definition for RCC_APB3ENR register  ******************/

+#define RCC_APB3ENR_LTDCEN_Pos                 (3U)

+#define RCC_APB3ENR_LTDCEN_Msk                 (0x1UL << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */

+#define RCC_APB3ENR_LTDCEN                     RCC_APB3ENR_LTDCEN_Msk

+#define RCC_APB3ENR_WWDGEN_Pos                 (6U)

+#define RCC_APB3ENR_WWDGEN_Msk                 (0x1UL << RCC_APB3ENR_WWDGEN_Pos) /*!< 0x00000040 */

+#define RCC_APB3ENR_WWDGEN                     RCC_APB3ENR_WWDGEN_Msk

+

+/* Legacy define */

+#define RCC_APB3ENR_WWDG1EN_Pos                 RCC_APB3ENR_WWDGEN_Pos

+#define RCC_APB3ENR_WWDG1EN_Msk                 RCC_APB3ENR_WWDGEN_Msk

+#define RCC_APB3ENR_WWDG1EN                     RCC_APB3ENR_WWDGEN

+/********************  Bit definition for RCC_APB1LENR register  ******************/

+

+#define RCC_APB1LENR_TIM2EN_Pos                (0U)

+#define RCC_APB1LENR_TIM2EN_Msk                (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */

+#define RCC_APB1LENR_TIM2EN                    RCC_APB1LENR_TIM2EN_Msk

+#define RCC_APB1LENR_TIM3EN_Pos                (1U)

+#define RCC_APB1LENR_TIM3EN_Msk                (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */

+#define RCC_APB1LENR_TIM3EN                    RCC_APB1LENR_TIM3EN_Msk

+#define RCC_APB1LENR_TIM4EN_Pos                (2U)

+#define RCC_APB1LENR_TIM4EN_Msk                (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */

+#define RCC_APB1LENR_TIM4EN                    RCC_APB1LENR_TIM4EN_Msk

+#define RCC_APB1LENR_TIM5EN_Pos                (3U)

+#define RCC_APB1LENR_TIM5EN_Msk                (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */

+#define RCC_APB1LENR_TIM5EN                    RCC_APB1LENR_TIM5EN_Msk

+#define RCC_APB1LENR_TIM6EN_Pos                (4U)

+#define RCC_APB1LENR_TIM6EN_Msk                (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */

+#define RCC_APB1LENR_TIM6EN                    RCC_APB1LENR_TIM6EN_Msk

+#define RCC_APB1LENR_TIM7EN_Pos                (5U)

+#define RCC_APB1LENR_TIM7EN_Msk                (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */

+#define RCC_APB1LENR_TIM7EN                    RCC_APB1LENR_TIM7EN_Msk

+#define RCC_APB1LENR_TIM12EN_Pos               (6U)

+#define RCC_APB1LENR_TIM12EN_Msk               (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */

+#define RCC_APB1LENR_TIM12EN                   RCC_APB1LENR_TIM12EN_Msk

+#define RCC_APB1LENR_TIM13EN_Pos               (7U)

+#define RCC_APB1LENR_TIM13EN_Msk               (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */

+#define RCC_APB1LENR_TIM13EN                   RCC_APB1LENR_TIM13EN_Msk

+#define RCC_APB1LENR_TIM14EN_Pos               (8U)

+#define RCC_APB1LENR_TIM14EN_Msk               (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */

+#define RCC_APB1LENR_TIM14EN                   RCC_APB1LENR_TIM14EN_Msk

+#define RCC_APB1LENR_LPTIM1EN_Pos              (9U)

+#define RCC_APB1LENR_LPTIM1EN_Msk              (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */

+#define RCC_APB1LENR_LPTIM1EN                  RCC_APB1LENR_LPTIM1EN_Msk

+

+

+#define RCC_APB1LENR_SPI2EN_Pos                (14U)

+#define RCC_APB1LENR_SPI2EN_Msk                (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */

+#define RCC_APB1LENR_SPI2EN                    RCC_APB1LENR_SPI2EN_Msk

+#define RCC_APB1LENR_SPI3EN_Pos                (15U)

+#define RCC_APB1LENR_SPI3EN_Msk                (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */

+#define RCC_APB1LENR_SPI3EN                    RCC_APB1LENR_SPI3EN_Msk

+#define RCC_APB1LENR_SPDIFRXEN_Pos             (16U)

+#define RCC_APB1LENR_SPDIFRXEN_Msk             (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */

+#define RCC_APB1LENR_SPDIFRXEN                 RCC_APB1LENR_SPDIFRXEN_Msk

+#define RCC_APB1LENR_USART2EN_Pos              (17U)

+#define RCC_APB1LENR_USART2EN_Msk              (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */

+#define RCC_APB1LENR_USART2EN                  RCC_APB1LENR_USART2EN_Msk

+#define RCC_APB1LENR_USART3EN_Pos              (18U)

+#define RCC_APB1LENR_USART3EN_Msk              (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */

+#define RCC_APB1LENR_USART3EN                  RCC_APB1LENR_USART3EN_Msk

+#define RCC_APB1LENR_UART4EN_Pos               (19U)

+#define RCC_APB1LENR_UART4EN_Msk               (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */

+#define RCC_APB1LENR_UART4EN                   RCC_APB1LENR_UART4EN_Msk

+#define RCC_APB1LENR_UART5EN_Pos               (20U)

+#define RCC_APB1LENR_UART5EN_Msk               (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */

+#define RCC_APB1LENR_UART5EN                   RCC_APB1LENR_UART5EN_Msk

+#define RCC_APB1LENR_I2C1EN_Pos                (21U)

+#define RCC_APB1LENR_I2C1EN_Msk                (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */

+#define RCC_APB1LENR_I2C1EN                    RCC_APB1LENR_I2C1EN_Msk

+#define RCC_APB1LENR_I2C2EN_Pos                (22U)

+#define RCC_APB1LENR_I2C2EN_Msk                (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */

+#define RCC_APB1LENR_I2C2EN                    RCC_APB1LENR_I2C2EN_Msk

+#define RCC_APB1LENR_I2C3EN_Pos                (23U)

+#define RCC_APB1LENR_I2C3EN_Msk                (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */

+#define RCC_APB1LENR_I2C3EN                    RCC_APB1LENR_I2C3EN_Msk

+#define RCC_APB1LENR_CECEN_Pos                 (27U)

+#define RCC_APB1LENR_CECEN_Msk                 (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */

+#define RCC_APB1LENR_CECEN                     RCC_APB1LENR_CECEN_Msk

+#define RCC_APB1LENR_DAC12EN_Pos               (29U)

+#define RCC_APB1LENR_DAC12EN_Msk               (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */

+#define RCC_APB1LENR_DAC12EN                   RCC_APB1LENR_DAC12EN_Msk

+#define RCC_APB1LENR_UART7EN_Pos               (30U)

+#define RCC_APB1LENR_UART7EN_Msk               (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */

+#define RCC_APB1LENR_UART7EN                   RCC_APB1LENR_UART7EN_Msk

+#define RCC_APB1LENR_UART8EN_Pos               (31U)

+#define RCC_APB1LENR_UART8EN_Msk               (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */

+#define RCC_APB1LENR_UART8EN                   RCC_APB1LENR_UART8EN_Msk

+

+/* Legacy define */

+#define RCC_APB1LENR_HDMICECEN_Pos             RCC_APB1LENR_CECEN_Pos

+#define RCC_APB1LENR_HDMICECEN_Msk             RCC_APB1LENR_CECEN_Msk

+#define RCC_APB1LENR_HDMICECEN                 RCC_APB1LENR_CECEN

+/********************  Bit definition for RCC_APB1HENR register  ******************/

+#define RCC_APB1HENR_CRSEN_Pos                 (1U)

+#define RCC_APB1HENR_CRSEN_Msk                 (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1HENR_CRSEN                     RCC_APB1HENR_CRSEN_Msk

+#define RCC_APB1HENR_SWPMIEN_Pos               (2U)

+#define RCC_APB1HENR_SWPMIEN_Msk               (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1HENR_SWPMIEN                   RCC_APB1HENR_SWPMIEN_Msk

+#define RCC_APB1HENR_OPAMPEN_Pos               (4U)

+#define RCC_APB1HENR_OPAMPEN_Msk               (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1HENR_OPAMPEN                   RCC_APB1HENR_OPAMPEN_Msk

+#define RCC_APB1HENR_MDIOSEN_Pos               (5U)

+#define RCC_APB1HENR_MDIOSEN_Msk               (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1HENR_MDIOSEN                   RCC_APB1HENR_MDIOSEN_Msk

+#define RCC_APB1HENR_FDCANEN_Pos               (8U)

+#define RCC_APB1HENR_FDCANEN_Msk               (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1HENR_FDCANEN                   RCC_APB1HENR_FDCANEN_Msk

+

+/********************  Bit definition for RCC_APB2ENR register  ******************/

+#define RCC_APB2ENR_TIM1EN_Pos                 (0U)

+#define RCC_APB2ENR_TIM1EN_Msk                 (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */

+#define RCC_APB2ENR_TIM1EN                     RCC_APB2ENR_TIM1EN_Msk

+#define RCC_APB2ENR_TIM8EN_Pos                 (1U)

+#define RCC_APB2ENR_TIM8EN_Msk                 (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */

+#define RCC_APB2ENR_TIM8EN                     RCC_APB2ENR_TIM8EN_Msk

+#define RCC_APB2ENR_USART1EN_Pos               (4U)

+#define RCC_APB2ENR_USART1EN_Msk               (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */

+#define RCC_APB2ENR_USART1EN                   RCC_APB2ENR_USART1EN_Msk

+#define RCC_APB2ENR_USART6EN_Pos               (5U)

+#define RCC_APB2ENR_USART6EN_Msk               (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */

+#define RCC_APB2ENR_USART6EN                   RCC_APB2ENR_USART6EN_Msk

+#define RCC_APB2ENR_UART9EN_Pos                (6U)

+#define RCC_APB2ENR_UART9EN_Msk                (0x1UL << RCC_APB2ENR_UART9EN_Pos) /*!< 0x00000040 */

+#define RCC_APB2ENR_UART9EN                    RCC_APB2ENR_UART9EN_Msk

+#define RCC_APB2ENR_USART10EN_Pos              (7U)

+#define RCC_APB2ENR_USART10EN_Msk              (0x1UL << RCC_APB2ENR_USART10EN_Pos) /*!< 0x00000080 */

+#define RCC_APB2ENR_USART10EN                   RCC_APB2ENR_USART10EN_Msk

+#define RCC_APB2ENR_SPI1EN_Pos                 (12U)

+#define RCC_APB2ENR_SPI1EN_Msk                 (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */

+#define RCC_APB2ENR_SPI1EN                     RCC_APB2ENR_SPI1EN_Msk

+#define RCC_APB2ENR_SPI4EN_Pos                 (13U)

+#define RCC_APB2ENR_SPI4EN_Msk                 (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */

+#define RCC_APB2ENR_SPI4EN                     RCC_APB2ENR_SPI4EN_Msk

+#define RCC_APB2ENR_TIM15EN_Pos                (16U)

+#define RCC_APB2ENR_TIM15EN_Msk                (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */

+#define RCC_APB2ENR_TIM15EN                    RCC_APB2ENR_TIM15EN_Msk

+#define RCC_APB2ENR_TIM16EN_Pos                (17U)

+#define RCC_APB2ENR_TIM16EN_Msk                (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */

+#define RCC_APB2ENR_TIM16EN                    RCC_APB2ENR_TIM16EN_Msk

+#define RCC_APB2ENR_TIM17EN_Pos                (18U)

+#define RCC_APB2ENR_TIM17EN_Msk                (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */

+#define RCC_APB2ENR_TIM17EN                    RCC_APB2ENR_TIM17EN_Msk

+#define RCC_APB2ENR_SPI5EN_Pos                 (20U)

+#define RCC_APB2ENR_SPI5EN_Msk                 (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */

+#define RCC_APB2ENR_SPI5EN                     RCC_APB2ENR_SPI5EN_Msk

+#define RCC_APB2ENR_SAI1EN_Pos                 (22U)

+#define RCC_APB2ENR_SAI1EN_Msk                 (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */

+#define RCC_APB2ENR_SAI1EN                     RCC_APB2ENR_SAI1EN_Msk

+#define RCC_APB2ENR_SAI2EN_Pos                 (23U)

+#define RCC_APB2ENR_SAI2EN_Msk                 (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */

+#define RCC_APB2ENR_SAI2EN                     RCC_APB2ENR_SAI2EN_Msk

+#define RCC_APB2ENR_DFSDM1EN_Pos               (30U)

+#define RCC_APB2ENR_DFSDM1EN_Msk               (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x40000000 */

+#define RCC_APB2ENR_DFSDM1EN                   RCC_APB2ENR_DFSDM1EN_Msk

+

+/********************  Bit definition for RCC_APB4ENR register  ******************/

+#define RCC_APB4ENR_SYSCFGEN_Pos               (1U)

+#define RCC_APB4ENR_SYSCFGEN_Msk               (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */

+#define RCC_APB4ENR_SYSCFGEN                   RCC_APB4ENR_SYSCFGEN_Msk

+#define RCC_APB4ENR_LPUART1EN_Pos              (3U)

+#define RCC_APB4ENR_LPUART1EN_Msk              (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */

+#define RCC_APB4ENR_LPUART1EN                  RCC_APB4ENR_LPUART1EN_Msk

+#define RCC_APB4ENR_SPI6EN_Pos                 (5U)

+#define RCC_APB4ENR_SPI6EN_Msk                 (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */

+#define RCC_APB4ENR_SPI6EN                     RCC_APB4ENR_SPI6EN_Msk

+#define RCC_APB4ENR_I2C4EN_Pos                 (7U)

+#define RCC_APB4ENR_I2C4EN_Msk                 (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */

+#define RCC_APB4ENR_I2C4EN                     RCC_APB4ENR_I2C4EN_Msk

+#define RCC_APB4ENR_LPTIM2EN_Pos               (9U)

+#define RCC_APB4ENR_LPTIM2EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */

+#define RCC_APB4ENR_LPTIM2EN                   RCC_APB4ENR_LPTIM2EN_Msk

+#define RCC_APB4ENR_LPTIM3EN_Pos               (10U)

+#define RCC_APB4ENR_LPTIM3EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */

+#define RCC_APB4ENR_LPTIM3EN                   RCC_APB4ENR_LPTIM3EN_Msk

+#define RCC_APB4ENR_DAC2EN_Pos                 (13U)

+#define RCC_APB4ENR_DAC2EN_Msk                 (0x1UL << RCC_APB4ENR_DAC2EN_Pos) /*!< 0x00002000 */

+#define RCC_APB4ENR_DAC2EN                     RCC_APB4ENR_DAC2EN_Msk

+#define RCC_APB4ENR_COMP12EN_Pos               (14U)

+#define RCC_APB4ENR_COMP12EN_Msk               (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */

+#define RCC_APB4ENR_COMP12EN                   RCC_APB4ENR_COMP12EN_Msk

+#define RCC_APB4ENR_VREFEN_Pos                 (15U)

+#define RCC_APB4ENR_VREFEN_Msk                 (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */

+#define RCC_APB4ENR_VREFEN                     RCC_APB4ENR_VREFEN_Msk

+#define RCC_APB4ENR_RTCAPBEN_Pos               (16U)

+#define RCC_APB4ENR_RTCAPBEN_Msk               (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */

+#define RCC_APB4ENR_RTCAPBEN                   RCC_APB4ENR_RTCAPBEN_Msk

+

+#define RCC_APB4ENR_DTSEN_Pos                  (26U)

+#define RCC_APB4ENR_DTSEN_Msk                  (0x1UL << RCC_APB4ENR_DTSEN_Pos) /*!< 0x04000000 */

+#define RCC_APB4ENR_DTSEN                      RCC_APB4ENR_DTSEN_Msk

+#define RCC_APB4ENR_DFSDM2EN_Pos               (27U)

+#define RCC_APB4ENR_DFSDM2EN_Msk               (0x1UL << RCC_APB4ENR_DFSDM2EN_Pos) /*!< 0x08000000 */

+#define RCC_APB4ENR_DFSDM2EN                   RCC_APB4ENR_DFSDM2EN_Msk

+

+/********************  Bit definition for RCC_AHB3RSTR register  ***************/

+#define RCC_AHB3RSTR_MDMARST_Pos               (0U)

+#define RCC_AHB3RSTR_MDMARST_Msk               (0x1UL << RCC_AHB3RSTR_MDMARST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB3RSTR_MDMARST                   RCC_AHB3RSTR_MDMARST_Msk

+#define RCC_AHB3RSTR_DMA2DRST_Pos              (4U)

+#define RCC_AHB3RSTR_DMA2DRST_Msk              (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos)     /*!< 0x00000010 */

+#define RCC_AHB3RSTR_DMA2DRST                  RCC_AHB3RSTR_DMA2DRST_Msk

+#define RCC_AHB3RSTR_JPGDECRST_Pos             (5U)

+#define RCC_AHB3RSTR_JPGDECRST_Msk             (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos)    /*!< 0x00000020 */

+#define RCC_AHB3RSTR_JPGDECRST                 RCC_AHB3RSTR_JPGDECRST_Msk

+#define RCC_AHB3RSTR_FMCRST_Pos                (12U)

+#define RCC_AHB3RSTR_FMCRST_Msk                (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)      /*!< 0x00001000 */

+#define RCC_AHB3RSTR_FMCRST                    RCC_AHB3RSTR_FMCRST_Msk

+#define RCC_AHB3RSTR_OSPI1RST_Pos              (14U)

+#define RCC_AHB3RSTR_OSPI1RST_Msk              (0x1UL << RCC_AHB3RSTR_OSPI1RST_Pos)    /*!< 0x00004000 */

+#define RCC_AHB3RSTR_OSPI1RST                   RCC_AHB3RSTR_OSPI1RST_Msk

+#define RCC_AHB3RSTR_SDMMC1RST_Pos             (16U)

+#define RCC_AHB3RSTR_SDMMC1RST_Msk             (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos)   /*!< 0x00010000 */

+#define RCC_AHB3RSTR_SDMMC1RST                 RCC_AHB3RSTR_SDMMC1RST_Msk

+#define RCC_AHB3RSTR_OSPI2RST_Pos              (19U)

+#define RCC_AHB3RSTR_OSPI2RST_Msk              (0x1UL << RCC_AHB3RSTR_OSPI2RST_Pos)    /*!< 0x00008000 */

+#define RCC_AHB3RSTR_OSPI2RST                  RCC_AHB3RSTR_OSPI2RST_Msk

+#define RCC_AHB3RSTR_IOMNGRRST_Pos             (21U)

+#define RCC_AHB3RSTR_IOMNGRRST_Msk             (0x1UL << RCC_AHB3RSTR_IOMNGRRST_Pos)   /*!< 0x00020000 */

+#define RCC_AHB3RSTR_IOMNGRRST                 RCC_AHB3RSTR_IOMNGRRST_Msk

+#define RCC_AHB3RSTR_GFXMMURST_Pos             (24U)

+#define RCC_AHB3RSTR_GFXMMURST_Msk             (0x1UL << RCC_AHB3RSTR_GFXMMURST_Pos)   /*!< 0x00100000 */

+#define RCC_AHB3RSTR_GFXMMURST                 RCC_AHB3RSTR_GFXMMURST_Msk

+

+

+/********************  Bit definition for RCC_AHB1RSTR register  ***************/

+#define RCC_AHB1RSTR_DMA1RST_Pos               (0U)

+#define RCC_AHB1RSTR_DMA1RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB1RSTR_DMA1RST                   RCC_AHB1RSTR_DMA1RST_Msk

+#define RCC_AHB1RSTR_DMA2RST_Pos               (1U)

+#define RCC_AHB1RSTR_DMA2RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)      /*!< 0x00000002 */

+#define RCC_AHB1RSTR_DMA2RST                   RCC_AHB1RSTR_DMA2RST_Msk

+#define RCC_AHB1RSTR_ADC12RST_Pos              (5U)

+#define RCC_AHB1RSTR_ADC12RST_Msk              (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)     /*!< 0x00000020 */

+#define RCC_AHB1RSTR_ADC12RST                  RCC_AHB1RSTR_ADC12RST_Msk

+#define RCC_AHB1RSTR_CRCRST_Pos                (9U)

+#define RCC_AHB1RSTR_CRCRST_Msk                (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)       /*!< 0x00000200 */

+#define RCC_AHB1RSTR_CRCRST                    RCC_AHB1RSTR_CRCRST_Msk

+#define RCC_AHB1RSTR_USB1OTGHSRST_Pos          (25U)

+#define RCC_AHB1RSTR_USB1OTGHSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */

+#define RCC_AHB1RSTR_USB1OTGHSRST              RCC_AHB1RSTR_USB1OTGHSRST_Msk

+

+/********************  Bit definition for RCC_AHB2RSTR register  ***************/

+#define RCC_AHB2RSTR_DCMI_PSSIRST_Pos          (0U)

+#define RCC_AHB2RSTR_DCMI_PSSIRST_Msk          (0x1UL << RCC_AHB2RSTR_DCMI_PSSIRST_Pos)  /*!< 0x00000001 */

+#define RCC_AHB2RSTR_DCMI_PSSIRST              RCC_AHB2RSTR_DCMI_PSSIRST_Msk

+#define RCC_AHB2RSTR_HSEMRST_Pos               (2U)

+#define RCC_AHB2RSTR_HSEMRST_Msk               (0x1UL << RCC_AHB2RSTR_HSEMRST_Pos)       /*!< 0x00000004 */

+#define RCC_AHB2RSTR_HSEMRST                   RCC_AHB2RSTR_HSEMRST_Msk

+#define RCC_AHB2RSTR_RNGRST_Pos                (6U)

+#define RCC_AHB2RSTR_RNGRST_Msk                (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)        /*!< 0x00000040 */

+#define RCC_AHB2RSTR_RNGRST                    RCC_AHB2RSTR_RNGRST_Msk

+#define RCC_AHB2RSTR_SDMMC2RST_Pos             (9U)

+#define RCC_AHB2RSTR_SDMMC2RST_Msk             (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)     /*!< 0x00000200 */

+#define RCC_AHB2RSTR_SDMMC2RST                 RCC_AHB2RSTR_SDMMC2RST_Msk

+#define RCC_AHB2RSTR_BDMA1RST_Pos              (11U)

+#define RCC_AHB2RSTR_BDMA1RST_Msk              (0x1UL << RCC_AHB2RSTR_BDMA1RST_Pos)      /*!< 0x00000200 */

+#define RCC_AHB2RSTR_BDMA1RST                  RCC_AHB2RSTR_BDMA1RST_Msk

+

+/* Legacy define */

+#define RCC_AHB2RSTR_DCMIRST_Pos               RCC_AHB2RSTR_DCMI_PSSIRST_Pos

+#define RCC_AHB2RSTR_DCMIRST_Msk               RCC_AHB2RSTR_DCMI_PSSIRST_Msk

+#define RCC_AHB2RSTR_DCMIRST                   RCC_AHB2RSTR_DCMI_PSSIRST

+/********************  Bit definition for RCC_AHB4RSTR register  ******************/

+#define RCC_AHB4RSTR_GPIOARST_Pos              (0U)

+#define RCC_AHB4RSTR_GPIOARST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB4RSTR_GPIOARST                  RCC_AHB4RSTR_GPIOARST_Msk

+#define RCC_AHB4RSTR_GPIOBRST_Pos              (1U)

+#define RCC_AHB4RSTR_GPIOBRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)      /*!< 0x00000002 */

+#define RCC_AHB4RSTR_GPIOBRST                  RCC_AHB4RSTR_GPIOBRST_Msk

+#define RCC_AHB4RSTR_GPIOCRST_Pos              (2U)

+#define RCC_AHB4RSTR_GPIOCRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)      /*!< 0x00000004 */

+#define RCC_AHB4RSTR_GPIOCRST                  RCC_AHB4RSTR_GPIOCRST_Msk

+#define RCC_AHB4RSTR_GPIODRST_Pos              (3U)

+#define RCC_AHB4RSTR_GPIODRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)      /*!< 0x00000008 */

+#define RCC_AHB4RSTR_GPIODRST                  RCC_AHB4RSTR_GPIODRST_Msk

+#define RCC_AHB4RSTR_GPIOERST_Pos              (4U)

+#define RCC_AHB4RSTR_GPIOERST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)      /*!< 0x00000010 */

+#define RCC_AHB4RSTR_GPIOERST                  RCC_AHB4RSTR_GPIOERST_Msk

+#define RCC_AHB4RSTR_GPIOFRST_Pos              (5U)

+#define RCC_AHB4RSTR_GPIOFRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)       /*!< 0x00000020 */

+#define RCC_AHB4RSTR_GPIOFRST                  RCC_AHB4RSTR_GPIOFRST_Msk

+#define RCC_AHB4RSTR_GPIOGRST_Pos              (6U)

+#define RCC_AHB4RSTR_GPIOGRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)       /*!< 0x00000040 */

+#define RCC_AHB4RSTR_GPIOGRST                  RCC_AHB4RSTR_GPIOGRST_Msk

+#define RCC_AHB4RSTR_GPIOHRST_Pos              (7U)

+#define RCC_AHB4RSTR_GPIOHRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)       /*!< 0x00000080 */

+#define RCC_AHB4RSTR_GPIOHRST                  RCC_AHB4RSTR_GPIOHRST_Msk

+#define RCC_AHB4RSTR_GPIOIRST_Pos              (8U)

+#define RCC_AHB4RSTR_GPIOIRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos)       /*!< 0x00000100 */

+#define RCC_AHB4RSTR_GPIOIRST                  RCC_AHB4RSTR_GPIOIRST_Msk

+#define RCC_AHB4RSTR_GPIOJRST_Pos              (9U)

+#define RCC_AHB4RSTR_GPIOJRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos)       /*!< 0x00000200 */

+#define RCC_AHB4RSTR_GPIOJRST                  RCC_AHB4RSTR_GPIOJRST_Msk

+#define RCC_AHB4RSTR_GPIOKRST_Pos              (10U)

+#define RCC_AHB4RSTR_GPIOKRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos)       /*!< 0x00000400 */

+#define RCC_AHB4RSTR_GPIOKRST                  RCC_AHB4RSTR_GPIOKRST_Msk

+#define RCC_AHB4RSTR_BDMA2RST_Pos              (21U)

+#define RCC_AHB4RSTR_BDMA2RST_Msk              (0x1UL << RCC_AHB4RSTR_BDMA2RST_Pos)       /*!< 0x00200000 */

+#define RCC_AHB4RSTR_BDMA2RST                   RCC_AHB4RSTR_BDMA2RST_Msk

+

+

+/********************  Bit definition for RCC_APB3RSTR register  ******************/

+#define RCC_APB3RSTR_LTDCRST_Pos               (3U)

+#define RCC_APB3RSTR_LTDCRST_Msk               (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */

+#define RCC_APB3RSTR_LTDCRST                   RCC_APB3RSTR_LTDCRST_Msk

+

+/********************  Bit definition for RCC_APB1LRSTR register  ******************/

+

+#define RCC_APB1LRSTR_TIM2RST_Pos              (0U)

+#define RCC_APB1LRSTR_TIM2RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */

+#define RCC_APB1LRSTR_TIM2RST                  RCC_APB1LRSTR_TIM2RST_Msk

+#define RCC_APB1LRSTR_TIM3RST_Pos              (1U)

+#define RCC_APB1LRSTR_TIM3RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */

+#define RCC_APB1LRSTR_TIM3RST                  RCC_APB1LRSTR_TIM3RST_Msk

+#define RCC_APB1LRSTR_TIM4RST_Pos              (2U)

+#define RCC_APB1LRSTR_TIM4RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */

+#define RCC_APB1LRSTR_TIM4RST                  RCC_APB1LRSTR_TIM4RST_Msk

+#define RCC_APB1LRSTR_TIM5RST_Pos              (3U)

+#define RCC_APB1LRSTR_TIM5RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */

+#define RCC_APB1LRSTR_TIM5RST                  RCC_APB1LRSTR_TIM5RST_Msk

+#define RCC_APB1LRSTR_TIM6RST_Pos              (4U)

+#define RCC_APB1LRSTR_TIM6RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */

+#define RCC_APB1LRSTR_TIM6RST                  RCC_APB1LRSTR_TIM6RST_Msk

+#define RCC_APB1LRSTR_TIM7RST_Pos              (5U)

+#define RCC_APB1LRSTR_TIM7RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */

+#define RCC_APB1LRSTR_TIM7RST                  RCC_APB1LRSTR_TIM7RST_Msk

+#define RCC_APB1LRSTR_TIM12RST_Pos             (6U)

+#define RCC_APB1LRSTR_TIM12RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */

+#define RCC_APB1LRSTR_TIM12RST                 RCC_APB1LRSTR_TIM12RST_Msk

+#define RCC_APB1LRSTR_TIM13RST_Pos             (7U)

+#define RCC_APB1LRSTR_TIM13RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */

+#define RCC_APB1LRSTR_TIM13RST                 RCC_APB1LRSTR_TIM13RST_Msk

+#define RCC_APB1LRSTR_TIM14RST_Pos             (8U)

+#define RCC_APB1LRSTR_TIM14RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */

+#define RCC_APB1LRSTR_TIM14RST                 RCC_APB1LRSTR_TIM14RST_Msk

+#define RCC_APB1LRSTR_LPTIM1RST_Pos            (9U)

+#define RCC_APB1LRSTR_LPTIM1RST_Msk            (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */

+#define RCC_APB1LRSTR_LPTIM1RST                RCC_APB1LRSTR_LPTIM1RST_Msk

+#define RCC_APB1LRSTR_SPI2RST_Pos              (14U)

+#define RCC_APB1LRSTR_SPI2RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */

+#define RCC_APB1LRSTR_SPI2RST                  RCC_APB1LRSTR_SPI2RST_Msk

+#define RCC_APB1LRSTR_SPI3RST_Pos              (15U)

+#define RCC_APB1LRSTR_SPI3RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */

+#define RCC_APB1LRSTR_SPI3RST                  RCC_APB1LRSTR_SPI3RST_Msk

+#define RCC_APB1LRSTR_SPDIFRXRST_Pos           (16U)

+#define RCC_APB1LRSTR_SPDIFRXRST_Msk           (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */

+#define RCC_APB1LRSTR_SPDIFRXRST               RCC_APB1LRSTR_SPDIFRXRST_Msk

+#define RCC_APB1LRSTR_USART2RST_Pos            (17U)

+#define RCC_APB1LRSTR_USART2RST_Msk            (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */

+#define RCC_APB1LRSTR_USART2RST                RCC_APB1LRSTR_USART2RST_Msk

+#define RCC_APB1LRSTR_USART3RST_Pos            (18U)

+#define RCC_APB1LRSTR_USART3RST_Msk            (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */

+#define RCC_APB1LRSTR_USART3RST                RCC_APB1LRSTR_USART3RST_Msk

+#define RCC_APB1LRSTR_UART4RST_Pos             (19U)

+#define RCC_APB1LRSTR_UART4RST_Msk             (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */

+#define RCC_APB1LRSTR_UART4RST                 RCC_APB1LRSTR_UART4RST_Msk

+#define RCC_APB1LRSTR_UART5RST_Pos             (20U)

+#define RCC_APB1LRSTR_UART5RST_Msk             (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */

+#define RCC_APB1LRSTR_UART5RST                 RCC_APB1LRSTR_UART5RST_Msk

+#define RCC_APB1LRSTR_I2C1RST_Pos              (21U)

+#define RCC_APB1LRSTR_I2C1RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */

+#define RCC_APB1LRSTR_I2C1RST                  RCC_APB1LRSTR_I2C1RST_Msk

+#define RCC_APB1LRSTR_I2C2RST_Pos              (22U)

+#define RCC_APB1LRSTR_I2C2RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */

+#define RCC_APB1LRSTR_I2C2RST                  RCC_APB1LRSTR_I2C2RST_Msk

+#define RCC_APB1LRSTR_I2C3RST_Pos              (23U)

+#define RCC_APB1LRSTR_I2C3RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */

+#define RCC_APB1LRSTR_I2C3RST                  RCC_APB1LRSTR_I2C3RST_Msk

+#define RCC_APB1LRSTR_CECRST_Pos               (27U)

+#define RCC_APB1LRSTR_CECRST_Msk               (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */

+#define RCC_APB1LRSTR_CECRST                   RCC_APB1LRSTR_CECRST_Msk

+#define RCC_APB1LRSTR_DAC12RST_Pos             (29U)

+#define RCC_APB1LRSTR_DAC12RST_Msk             (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */

+#define RCC_APB1LRSTR_DAC12RST                 RCC_APB1LRSTR_DAC12RST_Msk

+#define RCC_APB1LRSTR_UART7RST_Pos             (30U)

+#define RCC_APB1LRSTR_UART7RST_Msk             (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */

+#define RCC_APB1LRSTR_UART7RST                 RCC_APB1LRSTR_UART7RST_Msk

+#define RCC_APB1LRSTR_UART8RST_Pos             (31U)

+#define RCC_APB1LRSTR_UART8RST_Msk             (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */

+#define RCC_APB1LRSTR_UART8RST                 RCC_APB1LRSTR_UART8RST_Msk

+

+/* Legacy define */

+#define RCC_APB1LRSTR_HDMICECRST_Pos           RCC_APB1LRSTR_CECRST_Pos

+#define RCC_APB1LRSTR_HDMICECRST_Msk           RCC_APB1LRSTR_CECRST_Msk

+#define RCC_APB1LRSTR_HDMICECRST               RCC_APB1LRSTR_CECRST

+/********************  Bit definition for RCC_APB1HRSTR register  ******************/

+#define RCC_APB1HRSTR_CRSRST_Pos               (1U)

+#define RCC_APB1HRSTR_CRSRST_Msk               (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */

+#define RCC_APB1HRSTR_CRSRST                   RCC_APB1HRSTR_CRSRST_Msk

+#define RCC_APB1HRSTR_SWPMIRST_Pos             (2U)

+#define RCC_APB1HRSTR_SWPMIRST_Msk             (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */

+#define RCC_APB1HRSTR_SWPMIRST                 RCC_APB1HRSTR_SWPMIRST_Msk

+#define RCC_APB1HRSTR_OPAMPRST_Pos             (4U)

+#define RCC_APB1HRSTR_OPAMPRST_Msk             (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */

+#define RCC_APB1HRSTR_OPAMPRST                 RCC_APB1HRSTR_OPAMPRST_Msk

+#define RCC_APB1HRSTR_MDIOSRST_Pos             (5U)

+#define RCC_APB1HRSTR_MDIOSRST_Msk             (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */

+#define RCC_APB1HRSTR_MDIOSRST                 RCC_APB1HRSTR_MDIOSRST_Msk

+#define RCC_APB1HRSTR_FDCANRST_Pos             (8U)

+#define RCC_APB1HRSTR_FDCANRST_Msk             (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */

+#define RCC_APB1HRSTR_FDCANRST                 RCC_APB1HRSTR_FDCANRST_Msk

+

+/********************  Bit definition for RCC_APB2RSTR register  ******************/

+#define RCC_APB2RSTR_TIM1RST_Pos               (0U)

+#define RCC_APB2RSTR_TIM1RST_Msk               (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */

+#define RCC_APB2RSTR_TIM1RST                   RCC_APB2RSTR_TIM1RST_Msk

+#define RCC_APB2RSTR_TIM8RST_Pos               (1U)

+#define RCC_APB2RSTR_TIM8RST_Msk               (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */

+#define RCC_APB2RSTR_TIM8RST                   RCC_APB2RSTR_TIM8RST_Msk

+#define RCC_APB2RSTR_USART1RST_Pos             (4U)

+#define RCC_APB2RSTR_USART1RST_Msk             (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */

+#define RCC_APB2RSTR_USART1RST                 RCC_APB2RSTR_USART1RST_Msk

+#define RCC_APB2RSTR_USART6RST_Pos             (5U)

+#define RCC_APB2RSTR_USART6RST_Msk             (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */

+#define RCC_APB2RSTR_USART6RST                 RCC_APB2RSTR_USART6RST_Msk

+#define RCC_APB2RSTR_UART9RST_Pos              (6U)

+#define RCC_APB2RSTR_UART9RST_Msk              (0x1UL << RCC_APB2RSTR_UART9RST_Pos) /*!< 0x00000040 */

+#define RCC_APB2RSTR_UART9RST                  RCC_APB2RSTR_UART9RST_Msk

+#define RCC_APB2RSTR_USART10RST_Pos            (7U)

+#define RCC_APB2RSTR_USART10RST_Msk            (0x1UL << RCC_APB2RSTR_USART10RST_Pos) /*!< 0x00000080 */

+#define RCC_APB2RSTR_USART10RST                RCC_APB2RSTR_USART10RST_Msk

+#define RCC_APB2RSTR_SPI1RST_Pos               (12U)

+#define RCC_APB2RSTR_SPI1RST_Msk               (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */

+#define RCC_APB2RSTR_SPI1RST                   RCC_APB2RSTR_SPI1RST_Msk

+#define RCC_APB2RSTR_SPI4RST_Pos               (13U)

+#define RCC_APB2RSTR_SPI4RST_Msk               (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */

+#define RCC_APB2RSTR_SPI4RST                   RCC_APB2RSTR_SPI4RST_Msk

+#define RCC_APB2RSTR_TIM15RST_Pos              (16U)

+#define RCC_APB2RSTR_TIM15RST_Msk              (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */

+#define RCC_APB2RSTR_TIM15RST                  RCC_APB2RSTR_TIM15RST_Msk

+#define RCC_APB2RSTR_TIM16RST_Pos              (17U)

+#define RCC_APB2RSTR_TIM16RST_Msk              (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */

+#define RCC_APB2RSTR_TIM16RST                  RCC_APB2RSTR_TIM16RST_Msk

+#define RCC_APB2RSTR_TIM17RST_Pos              (18U)

+#define RCC_APB2RSTR_TIM17RST_Msk              (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */

+#define RCC_APB2RSTR_TIM17RST                  RCC_APB2RSTR_TIM17RST_Msk

+#define RCC_APB2RSTR_SPI5RST_Pos               (20U)

+#define RCC_APB2RSTR_SPI5RST_Msk               (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */

+#define RCC_APB2RSTR_SPI5RST                   RCC_APB2RSTR_SPI5RST_Msk

+#define RCC_APB2RSTR_SAI1RST_Pos               (22U)

+#define RCC_APB2RSTR_SAI1RST_Msk               (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */

+#define RCC_APB2RSTR_SAI1RST                   RCC_APB2RSTR_SAI1RST_Msk

+#define RCC_APB2RSTR_SAI2RST_Pos               (23U)

+#define RCC_APB2RSTR_SAI2RST_Msk               (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */

+#define RCC_APB2RSTR_SAI2RST                   RCC_APB2RSTR_SAI2RST_Msk

+#define RCC_APB2RSTR_DFSDM1RST_Pos             (30U)

+#define RCC_APB2RSTR_DFSDM1RST_Msk             (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */

+#define RCC_APB2RSTR_DFSDM1RST                 RCC_APB2RSTR_DFSDM1RST_Msk

+

+/********************  Bit definition for RCC_APB4RSTR register  ******************/

+#define RCC_APB4RSTR_SYSCFGRST_Pos             (1U)

+#define RCC_APB4RSTR_SYSCFGRST_Msk             (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */

+#define RCC_APB4RSTR_SYSCFGRST                 RCC_APB4RSTR_SYSCFGRST_Msk

+#define RCC_APB4RSTR_LPUART1RST_Pos            (3U)

+#define RCC_APB4RSTR_LPUART1RST_Msk            (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */

+#define RCC_APB4RSTR_LPUART1RST                RCC_APB4RSTR_LPUART1RST_Msk

+#define RCC_APB4RSTR_SPI6RST_Pos               (5U)

+#define RCC_APB4RSTR_SPI6RST_Msk               (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */

+#define RCC_APB4RSTR_SPI6RST                   RCC_APB4RSTR_SPI6RST_Msk

+#define RCC_APB4RSTR_I2C4RST_Pos               (7U)

+#define RCC_APB4RSTR_I2C4RST_Msk               (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */

+#define RCC_APB4RSTR_I2C4RST                   RCC_APB4RSTR_I2C4RST_Msk

+#define RCC_APB4RSTR_LPTIM2RST_Pos             (9U)

+#define RCC_APB4RSTR_LPTIM2RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */

+#define RCC_APB4RSTR_LPTIM2RST                 RCC_APB4RSTR_LPTIM2RST_Msk

+#define RCC_APB4RSTR_LPTIM3RST_Pos             (10U)

+#define RCC_APB4RSTR_LPTIM3RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */

+#define RCC_APB4RSTR_LPTIM3RST                 RCC_APB4RSTR_LPTIM3RST_Msk

+#define RCC_APB4RSTR_DAC2RST_Pos               (13U)

+#define RCC_APB4RSTR_DAC2RST_Msk               (0x1UL << RCC_APB4RSTR_DAC2RST_Pos) /*!< 0x00001000 */

+#define RCC_APB4RSTR_DAC2RST                    RCC_APB4RSTR_DAC2RST_Msk

+#define RCC_APB4RSTR_COMP12RST_Pos             (14U)

+#define RCC_APB4RSTR_COMP12RST_Msk             (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */

+#define RCC_APB4RSTR_COMP12RST                 RCC_APB4RSTR_COMP12RST_Msk

+#define RCC_APB4RSTR_VREFRST_Pos               (15U)

+#define RCC_APB4RSTR_VREFRST_Msk               (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */

+#define RCC_APB4RSTR_VREFRST                   RCC_APB4RSTR_VREFRST_Msk

+

+#define RCC_APB4RSTR_DTSRST_Pos                (26U)

+#define RCC_APB4RSTR_DTSRST_Msk                (0x1UL << RCC_APB4RSTR_DTSRST_Pos) /*!< 0x04000000 */

+#define RCC_APB4RSTR_DTSRST                    RCC_APB4RSTR_DTSRST_Msk

+#define RCC_APB4RSTR_DFSDM2RST_Pos             (27U)

+#define RCC_APB4RSTR_DFSDM2RST_Msk             (0x1UL << RCC_APB4RSTR_DFSDM2RST_Pos) /*!< 0x08000000 */

+#define RCC_APB4RSTR_DFSDM2RST                 RCC_APB4RSTR_DFSDM2RST_Msk

+

+

+/********************  Bit definition for RCC_SRDAMR register  ********************/

+#define RCC_SRDAMR_BDMA2AMEN_Pos               (0U)

+#define RCC_SRDAMR_BDMA2AMEN_Msk               (0x1UL << RCC_SRDAMR_BDMA2AMEN_Pos) /*!< 0x00000001 */

+#define RCC_SRDAMR_BDMA2AMEN                   RCC_SRDAMR_BDMA2AMEN_Msk

+#define RCC_SRDAMR_GPIOAMEN_Pos                (1U)

+#define RCC_SRDAMR_GPIOAMEN_Msk                (0x1UL << RCC_SRDAMR_GPIOAMEN_Pos) /*!< 0x00000001 */

+#define RCC_SRDAMR_GPIOAMEN                    RCC_SRDAMR_GPIOAMEN_Msk

+#define RCC_SRDAMR_LPUART1AMEN_Pos             (3U)

+#define RCC_SRDAMR_LPUART1AMEN_Msk             (0x1UL << RCC_SRDAMR_LPUART1AMEN_Pos) /*!< 0x00000008 */

+#define RCC_SRDAMR_LPUART1AMEN                 RCC_SRDAMR_LPUART1AMEN_Msk

+#define RCC_SRDAMR_SPI6AMEN_Pos                (5U)

+#define RCC_SRDAMR_SPI6AMEN_Msk                (0x1UL << RCC_SRDAMR_SPI6AMEN_Pos) /*!< 0x00000020 */

+#define RCC_SRDAMR_SPI6AMEN                    RCC_SRDAMR_SPI6AMEN_Msk

+#define RCC_SRDAMR_I2C4AMEN_Pos                (7U)

+#define RCC_SRDAMR_I2C4AMEN_Msk                (0x1UL << RCC_SRDAMR_I2C4AMEN_Pos) /*!< 0x00000080 */

+#define RCC_SRDAMR_I2C4AMEN                    RCC_SRDAMR_I2C4AMEN_Msk

+#define RCC_SRDAMR_LPTIM2AMEN_Pos              (9U)

+#define RCC_SRDAMR_LPTIM2AMEN_Msk              (0x1UL << RCC_SRDAMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */

+#define RCC_SRDAMR_LPTIM2AMEN                  RCC_SRDAMR_LPTIM2AMEN_Msk

+#define RCC_SRDAMR_LPTIM3AMEN_Pos              (10U)

+#define RCC_SRDAMR_LPTIM3AMEN_Msk              (0x1UL << RCC_SRDAMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */

+#define RCC_SRDAMR_LPTIM3AMEN                  RCC_SRDAMR_LPTIM3AMEN_Msk

+#define RCC_SRDAMR_DAC2AMEN_Pos                (13U)

+#define RCC_SRDAMR_DAC2AMEN_Msk                (0x1UL << RCC_SRDAMR_DAC2AMEN_Pos) /*!< 0x00004000 */

+#define RCC_SRDAMR_DAC2AMEN                    RCC_SRDAMR_DAC2AMEN_Msk

+#define RCC_SRDAMR_COMP12AMEN_Pos              (14U)

+#define RCC_SRDAMR_COMP12AMEN_Msk              (0x1UL << RCC_SRDAMR_COMP12AMEN_Pos) /*!< 0x00004000 */

+#define RCC_SRDAMR_COMP12AMEN                  RCC_SRDAMR_COMP12AMEN_Msk

+#define RCC_SRDAMR_VREFAMEN_Pos                (15U)

+#define RCC_SRDAMR_VREFAMEN_Msk                (0x1UL << RCC_SRDAMR_VREFAMEN_Pos) /*!< 0x00008000 */

+#define RCC_SRDAMR_VREFAMEN                     RCC_SRDAMR_VREFAMEN_Msk

+#define RCC_SRDAMR_RTCAMEN_Pos                 (16U)

+#define RCC_SRDAMR_RTCAMEN_Msk                 (0x1UL << RCC_SRDAMR_RTCAMEN_Pos) /*!< 0x00010000 */

+#define RCC_SRDAMR_RTCAMEN                     RCC_SRDAMR_RTCAMEN_Msk

+#define RCC_SRDAMR_DTSAMEN_Pos                 (26U)

+#define RCC_SRDAMR_DTSAMEN_Msk                 (0x1UL << RCC_SRDAMR_DTSAMEN_Pos) /*!< 0x04000000 */

+#define RCC_SRDAMR_DTSAMEN                     RCC_SRDAMR_DTSAMEN_Msk

+#define RCC_SRDAMR_DFSDM2AMEN_Pos              (27U)

+#define RCC_SRDAMR_DFSDM2AMEN_Msk              (0x1UL << RCC_SRDAMR_DFSDM2AMEN_Pos) /*!< 0x20000000 */

+#define RCC_SRDAMR_DFSDM2AMEN                   RCC_SRDAMR_DFSDM2AMEN_Msk

+#define RCC_SRDAMR_BKPRAMAMEN_Pos              (28U)

+#define RCC_SRDAMR_BKPRAMAMEN_Msk              (0x1UL << RCC_SRDAMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */

+#define RCC_SRDAMR_BKPRAMAMEN                  RCC_SRDAMR_BKPRAMAMEN_Msk

+#define RCC_SRDAMR_SRDSRAMAMEN_Pos             (29U)

+#define RCC_SRDAMR_SRDSRAMAMEN_Msk             (0x1UL << RCC_SRDAMR_SRDSRAMAMEN_Pos) /*!< 0x20000000 */

+#define RCC_SRDAMR_SRDSRAMAMEN                  RCC_SRDAMR_SRDSRAMAMEN_Msk

+/********************  Bit definition for RCC_CKGAENR register  ********************/

+#define RCC_CKGAENR_AXICKG_Pos                 (0U)

+#define RCC_CKGAENR_AXICKG_Msk                 (0x1UL << RCC_CKGAENR_AXICKG_Pos) /*!< 0x00000001 */

+#define RCC_CKGAENR_AXICKG                      RCC_CKGAENR_AXICKG_Msk

+#define RCC_CKGAENR_AHBCKG_Pos                 (1U)

+#define RCC_CKGAENR_AHBCKG_Msk                 (0x1UL << RCC_CKGAENR_AHBCKG_Pos) /*!< 0x00000002 */

+#define RCC_CKGAENR_AHBCKG                     RCC_CKGAENR_AHBCKG_Msk

+#define RCC_CKGAENR_CPUCKG_Pos                 (2U)

+#define RCC_CKGAENR_CPUCKG_Msk                 (0x1UL << RCC_CKGAENR_CPUCKG_Pos) /*!< 0x00000004 */

+#define RCC_CKGAENR_CPUCKG                     RCC_CKGAENR_CPUCKG_Msk

+#define RCC_CKGAENR_SDMMCCKG_Pos               (3U)

+#define RCC_CKGAENR_SDMMCCKG_Msk               (0x1UL << RCC_CKGAENR_SDMMCCKG_Pos) /*!< 0x00000008 */

+#define RCC_CKGAENR_SDMMCCKG                    RCC_CKGAENR_SDMMCCKG_Msk

+#define RCC_CKGAENR_MDMACKG_Pos                (4U)

+#define RCC_CKGAENR_MDMACKG_Msk                (0x1UL << RCC_CKGAENR_MDMACKG_Pos) /*!< 0x00000010 */

+#define RCC_CKGAENR_MDMACKG                    RCC_CKGAENR_MDMACKG_Msk

+#define RCC_CKGAENR_DMA2DCKG_Pos               (5U)

+#define RCC_CKGAENR_DMA2DCKG_Msk               (0x1UL << RCC_CKGAENR_DMA2DCKG_Pos) /*!< 0x00000020 */

+#define RCC_CKGAENR_DMA2DCKG                    RCC_CKGAENR_DMA2DCKG_Msk

+#define RCC_CKGAENR_LTDCCKG_Pos                (6U)

+#define RCC_CKGAENR_LTDCCKG_Msk                (0x1UL << RCC_CKGAENR_LTDCCKG_Pos) /*!< 0x00000040 */

+#define RCC_CKGAENR_LTDCCKG                    RCC_CKGAENR_LTDCCKG_Msk

+#define RCC_CKGAENR_GFXMMUMCKG_Pos             (7U)

+#define RCC_CKGAENR_GFXMMUMCKG_Msk             (0x1UL << RCC_CKGAENR_GFXMMUMCKG_Pos) /*!< 0x00000080 */

+#define RCC_CKGAENR_GFXMMUMCKG                 RCC_CKGAENR_GFXMMUMCKG_Msk

+#define RCC_CKGAENR_AHB12CKG_Pos               (8U)

+#define RCC_CKGAENR_AHB12CKG_Msk               (0x1UL << RCC_CKGAENR_AHB12CKG_Pos) /*!< 0x00000100 */

+#define RCC_CKGAENR_AHB12CKG                   RCC_CKGAENR_AHB12CKG_Msk

+#define RCC_CKGAENR_AHB34CKG_Pos               (9U)

+#define RCC_CKGAENR_AHB34CKG_Msk               (0x1UL << RCC_CKGAENR_AHB34CKG_Pos) /*!< 0x00000200 */

+#define RCC_CKGAENR_AHB34CKG                   RCC_CKGAENR_AHB34CKG_Msk

+#define RCC_CKGAENR_FLIFTCKG_Pos               (10U)

+#define RCC_CKGAENR_FLIFTCKG_Msk               (0x1UL << RCC_CKGAENR_FLIFTCKG_Pos) /*!< 0x00000400 */

+#define RCC_CKGAENR_FLIFTCKG                   RCC_CKGAENR_FLIFTCKG_Msk

+#define RCC_CKGAENR_OCTOSPI2CKG_Pos            (11U)

+#define RCC_CKGAENR_OCTOSPI2CKG_Msk            (0x1UL << RCC_CKGAENR_OCTOSPI2CKG_Pos) /*!< 0x00000800 */

+#define RCC_CKGAENR_OCTOSPI2CKG                RCC_CKGAENR_OCTOSPI2CKG_Msk

+#define RCC_CKGAENR_FMCCKG_Pos                 (12U)

+#define RCC_CKGAENR_FMCCKG_Msk                 (0x1UL << RCC_CKGAENR_FMCCKG_Pos) /*!< 0x00001000 */

+#define RCC_CKGAENR_FMCCKG                     RCC_CKGAENR_FMCCKG_Msk

+#define RCC_CKGAENR_OCTOSPI1CKG_Pos            (13U)

+#define RCC_CKGAENR_OCTOSPI1CKG_Msk            (0x1UL << RCC_CKGAENR_OCTOSPI1CKG_Pos) /*!< 0x00002000 */

+#define RCC_CKGAENR_OCTOSPI1CKG                RCC_CKGAENR_OCTOSPI1CKG_Msk

+#define RCC_CKGAENR_AXIRAM1CKG_Pos             (14U)

+#define RCC_CKGAENR_AXIRAM1CKG_Msk             (0x1UL << RCC_CKGAENR_AXIRAM1CKG_Pos) /*!< 0x00004000 */

+#define RCC_CKGAENR_AXIRAM1CKG                 RCC_CKGAENR_AXIRAM1CKG_Msk

+#define RCC_CKGAENR_AXIRAM2CKG_Pos             (15U)

+#define RCC_CKGAENR_AXIRAM2CKG_Msk             (0x1UL << RCC_CKGAENR_AXIRAM2CKG_Pos) /*!< 0x00008000 */

+#define RCC_CKGAENR_AXIRAM2CKG                 RCC_CKGAENR_AXIRAM2CKG_Msk

+#define RCC_CKGAENR_AXIRAM3CKG_Pos             (16U)

+#define RCC_CKGAENR_AXIRAM3CKG_Msk             (0x1UL << RCC_CKGAENR_AXIRAM3CKG_Pos) /*!< 0x00010000 */

+#define RCC_CKGAENR_AXIRAM3CKG                 RCC_CKGAENR_AXIRAM3CKG_Msk

+#define RCC_CKGAENR_GFXMMUSCKG_Pos             (17U)

+#define RCC_CKGAENR_GFXMMUSCKG_Msk             (0x1UL << RCC_CKGAENR_GFXMMUSCKG_Pos) /*!< 0x00020000 */

+#define RCC_CKGAENR_GFXMMUSCKG                 RCC_CKGAENR_GFXMMUSCKG_Msk

+#define RCC_CKGAENR_ECCRAMCKG_Pos              (29U)

+#define RCC_CKGAENR_ECCRAMCKG_Msk              (0x1UL << RCC_CKGAENR_ECCRAMCKG_Pos) /*!< 0x20000000 */

+#define RCC_CKGAENR_ECCRAMCKG                  RCC_CKGAENR_ECCRAMCKG_Msk

+#define RCC_CKGAENR_EXTICKG_Pos                (30U)

+#define RCC_CKGAENR_EXTICKG_Msk                (0x1UL << RCC_CKGAENR_EXTICKG_Pos) /*!< 0x40000000 */

+#define RCC_CKGAENR_EXTICKG                    RCC_CKGAENR_EXTICKG_Msk

+#define RCC_CKGAENR_JTAGCKG_Pos                (31U)

+#define RCC_CKGAENR_JTAGCKG_Msk                (0x1UL << RCC_CKGAENR_JTAGCKG_Pos) /*!< 0x80000008 */

+#define RCC_CKGAENR_JTAGCKG                    RCC_CKGAENR_JTAGCKG_Msk

+/********************  Bit definition for RCC_AHB3LPENR register  **************/

+#define RCC_AHB3LPENR_MDMALPEN_Pos             (0U)

+#define RCC_AHB3LPENR_MDMALPEN_Msk             (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos)         /*!< 0x00000001 */

+#define RCC_AHB3LPENR_MDMALPEN                 RCC_AHB3LPENR_MDMALPEN_Msk

+#define RCC_AHB3LPENR_DMA2DLPEN_Pos            (4U)

+#define RCC_AHB3LPENR_DMA2DLPEN_Msk            (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos)        /*!< 0x00000010 */

+#define RCC_AHB3LPENR_DMA2DLPEN                RCC_AHB3LPENR_DMA2DLPEN_Msk

+#define RCC_AHB3LPENR_JPGDECLPEN_Pos           (5U)

+#define RCC_AHB3LPENR_JPGDECLPEN_Msk           (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos)       /*!< 0x00000020 */

+#define RCC_AHB3LPENR_JPGDECLPEN               RCC_AHB3LPENR_JPGDECLPEN_Msk

+#define RCC_AHB3LPENR_FLASHLPEN_Pos            (8U)

+#define RCC_AHB3LPENR_FLASHLPEN_Msk            (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos)        /*!< 0x00000100 */

+#define RCC_AHB3LPENR_FLASHLPEN                RCC_AHB3LPENR_FLASHLPEN_Msk

+#define RCC_AHB3LPENR_FMCLPEN_Pos              (12U)

+#define RCC_AHB3LPENR_FMCLPEN_Msk              (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)          /*!< 0x00001000 */

+#define RCC_AHB3LPENR_FMCLPEN                  RCC_AHB3LPENR_FMCLPEN_Msk

+#define RCC_AHB3LPENR_OSPI1LPEN_Pos            (14U)

+#define RCC_AHB3LPENR_OSPI1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_OSPI1LPEN_Pos)        /*!< 0x00004000 */

+#define RCC_AHB3LPENR_OSPI1LPEN                RCC_AHB3LPENR_OSPI1LPEN_Msk

+#define RCC_AHB3LPENR_SDMMC1LPEN_Pos           (16U)

+#define RCC_AHB3LPENR_SDMMC1LPEN_Msk           (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos)       /*!< 0x00010000 */

+#define RCC_AHB3LPENR_SDMMC1LPEN               RCC_AHB3LPENR_SDMMC1LPEN_Msk

+#define RCC_AHB3LPENR_OSPI2LPEN_Pos            (19U)

+#define RCC_AHB3LPENR_OSPI2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_OSPI2LPEN_Pos)        /*!< 0x00080000 */

+#define RCC_AHB3LPENR_OSPI2LPEN                RCC_AHB3LPENR_OSPI2LPEN_Msk

+#define RCC_AHB3LPENR_IOMNGRLPEN_Pos           (21U)

+#define RCC_AHB3LPENR_IOMNGRLPEN_Msk           (0x1UL << RCC_AHB3LPENR_IOMNGRLPEN_Pos)       /*!< 0x00200000 */

+#define RCC_AHB3LPENR_IOMNGRLPEN               RCC_AHB3LPENR_IOMNGRLPEN_Msk

+#define RCC_AHB3LPENR_GFXMMULPEN_Pos           (24U)

+#define RCC_AHB3LPENR_GFXMMULPEN_Msk           (0x1UL << RCC_AHB3LPENR_GFXMMULPEN_Pos)       /*!< 0x01000000 */

+#define RCC_AHB3LPENR_GFXMMULPEN               RCC_AHB3LPENR_GFXMMULPEN_Msk

+#define RCC_AHB3LPENR_AXISRAM2LPEN_Pos         (26U)

+#define RCC_AHB3LPENR_AXISRAM2LPEN_Msk         (0x1UL << RCC_AHB3LPENR_AXISRAM2LPEN_Pos)     /*!< 0x02000000 */

+#define RCC_AHB3LPENR_AXISRAM2LPEN             RCC_AHB3LPENR_AXISRAM2LPEN_Msk

+#define RCC_AHB3LPENR_AXISRAM3LPEN_Pos         (27U)

+#define RCC_AHB3LPENR_AXISRAM3LPEN_Msk         (0x1UL << RCC_AHB3LPENR_AXISRAM3LPEN_Pos)     /*!< 0x04000000 */

+#define RCC_AHB3LPENR_AXISRAM3LPEN             RCC_AHB3LPENR_AXISRAM3LPEN_Msk

+#define RCC_AHB3LPENR_DTCM1LPEN_Pos            (28U)

+#define RCC_AHB3LPENR_DTCM1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos)        /*!< 0x10000000 */

+#define RCC_AHB3LPENR_DTCM1LPEN                RCC_AHB3LPENR_DTCM1LPEN_Msk

+#define RCC_AHB3LPENR_DTCM2LPEN_Pos            (29U)

+#define RCC_AHB3LPENR_DTCM2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos)        /*!< 0x20000000 */

+#define RCC_AHB3LPENR_DTCM2LPEN                RCC_AHB3LPENR_DTCM2LPEN_Msk

+#define RCC_AHB3LPENR_ITCMLPEN_Pos             (30U)

+#define RCC_AHB3LPENR_ITCMLPEN_Msk             (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos)         /*!< 0x40000000 */

+#define RCC_AHB3LPENR_ITCMLPEN                 RCC_AHB3LPENR_ITCMLPEN_Msk

+#define RCC_AHB3LPENR_AXISRAM1LPEN_Pos         (31U)

+#define RCC_AHB3LPENR_AXISRAM1LPEN_Msk         (0x1UL << RCC_AHB3LPENR_AXISRAM1LPEN_Pos)      /*!< 0x80000000 */

+#define RCC_AHB3LPENR_AXISRAM1LPEN             RCC_AHB3LPENR_AXISRAM1LPEN_Msk

+

+

+/* Legacy define */

+#define RCC_AHB3LPENR_AXISRAMLPEN_Pos          RCC_AHB3LPENR_AXISRAM1LPEN_Pos

+#define RCC_AHB3LPENR_AXISRAMLPEN_Msk          RCC_AHB3LPENR_AXISRAM1LPEN_Msk

+#define RCC_AHB3LPENR_AXISRAMLPEN              RCC_AHB3LPENR_AXISRAM1LPEN

+/********************  Bit definition for RCC_AHB1LPENR register  ***************/

+#define RCC_AHB1LPENR_DMA1LPEN_Pos             (0U)

+#define RCC_AHB1LPENR_DMA1LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB1LPENR_DMA1LPEN                 RCC_AHB1LPENR_DMA1LPEN_Msk

+#define RCC_AHB1LPENR_DMA2LPEN_Pos             (1U)

+#define RCC_AHB1LPENR_DMA2LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */

+#define RCC_AHB1LPENR_DMA2LPEN                 RCC_AHB1LPENR_DMA2LPEN_Msk

+#define RCC_AHB1LPENR_ADC12LPEN_Pos            (5U)

+#define RCC_AHB1LPENR_ADC12LPEN_Msk            (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB1LPENR_ADC12LPEN                RCC_AHB1LPENR_ADC12LPEN_Msk

+#define RCC_AHB1LPENR_CRCLPEN_Pos              (9U)

+#define RCC_AHB1LPENR_CRCLPEN_Msk              (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00008000 */

+#define RCC_AHB1LPENR_CRCLPEN                   RCC_AHB1LPENR_CRCLPEN_Msk

+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos        (25U)

+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */

+#define RCC_AHB1LPENR_USB1OTGHSLPEN            RCC_AHB1LPENR_USB1OTGHSLPEN_Msk

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos    (26U)

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN        RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk

+

+/********************  Bit definition for RCC_AHB2LPENR register  ***************/

+#define RCC_AHB2LPENR_DCMI_PSSILPEN_Pos        (0U)

+#define RCC_AHB2LPENR_DCMI_PSSILPEN_Msk        (0x1UL << RCC_AHB2LPENR_DCMI_PSSILPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB2LPENR_DCMI_PSSILPEN            RCC_AHB2LPENR_DCMI_PSSILPEN_Msk

+#define RCC_AHB2LPENR_RNGLPEN_Pos              (6U)

+#define RCC_AHB2LPENR_RNGLPEN_Msk              (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */

+#define RCC_AHB2LPENR_RNGLPEN                  RCC_AHB2LPENR_RNGLPEN_Msk

+#define RCC_AHB2LPENR_SDMMC2LPEN_Pos           (9U)

+#define RCC_AHB2LPENR_SDMMC2LPEN_Msk           (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */

+#define RCC_AHB2LPENR_SDMMC2LPEN               RCC_AHB2LPENR_SDMMC2LPEN_Msk

+#define RCC_AHB2LPENR_BDMA1LPEN_Pos            (11U)

+#define RCC_AHB2LPENR_BDMA1LPEN_Msk            (0x1UL << RCC_AHB2LPENR_BDMA1LPEN_Pos)   /*!< 0x00000800 */

+#define RCC_AHB2LPENR_BDMA1LPEN                RCC_AHB2LPENR_BDMA1LPEN_Msk

+#define RCC_AHB2LPENR_AHBSRAM1LPEN_Pos         (29U)

+#define RCC_AHB2LPENR_AHBSRAM1LPEN_Msk         (0x1UL << RCC_AHB2LPENR_AHBSRAM1LPEN_Pos) /*!< 0x20000000 */

+#define RCC_AHB2LPENR_AHBSRAM1LPEN             RCC_AHB2LPENR_AHBSRAM1LPEN_Msk

+#define RCC_AHB2LPENR_AHBSRAM2LPEN_Pos         (30U)

+#define RCC_AHB2LPENR_AHBSRAM2LPEN_Msk         (0x1UL << RCC_AHB2LPENR_AHBSRAM2LPEN_Pos) /*!< 0x40000000 */

+#define RCC_AHB2LPENR_AHBSRAM2LPEN             RCC_AHB2LPENR_AHBSRAM2LPEN_Msk

+

+/* Legacy define */

+#define RCC_AHB2LPENR_DFSDMDMALPEN_Pos         RCC_AHB2LPENR_BDMA1LPEN_Pos

+#define RCC_AHB2LPENR_DFSDMDMALPEN_Msk         RCC_AHB2LPENR_BDMA1LPEN_Msk

+#define RCC_AHB2LPENR_DFSDMDMALPEN             RCC_AHB2LPENR_BDMA1LPEN

+#define RCC_AHB2LPENR_DCMILPEN_Pos             RCC_AHB2LPENR_DCMI_PSSILPEN_Pos

+#define RCC_AHB2LPENR_DCMILPEN_Msk             RCC_AHB2LPENR_DCMI_PSSILPEN_Msk

+#define RCC_AHB2LPENR_DCMILPEN                 RCC_AHB2LPENR_DCMI_PSSILPEN

+

+/********************  Bit definition for RCC_AHB4LPENR register  ******************/

+#define RCC_AHB4LPENR_GPIOALPEN_Pos            (0U)

+#define RCC_AHB4LPENR_GPIOALPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB4LPENR_GPIOALPEN                RCC_AHB4LPENR_GPIOALPEN_Msk

+#define RCC_AHB4LPENR_GPIOBLPEN_Pos            (1U)

+#define RCC_AHB4LPENR_GPIOBLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */

+#define RCC_AHB4LPENR_GPIOBLPEN                RCC_AHB4LPENR_GPIOBLPEN_Msk

+#define RCC_AHB4LPENR_GPIOCLPEN_Pos            (2U)

+#define RCC_AHB4LPENR_GPIOCLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */

+#define RCC_AHB4LPENR_GPIOCLPEN                RCC_AHB4LPENR_GPIOCLPEN_Msk

+#define RCC_AHB4LPENR_GPIODLPEN_Pos            (3U)

+#define RCC_AHB4LPENR_GPIODLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */

+#define RCC_AHB4LPENR_GPIODLPEN                RCC_AHB4LPENR_GPIODLPEN_Msk

+#define RCC_AHB4LPENR_GPIOELPEN_Pos            (4U)

+#define RCC_AHB4LPENR_GPIOELPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */

+#define RCC_AHB4LPENR_GPIOELPEN                RCC_AHB4LPENR_GPIOELPEN_Msk

+#define RCC_AHB4LPENR_GPIOFLPEN_Pos            (5U)

+#define RCC_AHB4LPENR_GPIOFLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB4LPENR_GPIOFLPEN                RCC_AHB4LPENR_GPIOFLPEN_Msk

+#define RCC_AHB4LPENR_GPIOGLPEN_Pos            (6U)

+#define RCC_AHB4LPENR_GPIOGLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */

+#define RCC_AHB4LPENR_GPIOGLPEN                RCC_AHB4LPENR_GPIOGLPEN_Msk

+#define RCC_AHB4LPENR_GPIOHLPEN_Pos            (7U)

+#define RCC_AHB4LPENR_GPIOHLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */

+#define RCC_AHB4LPENR_GPIOHLPEN                RCC_AHB4LPENR_GPIOHLPEN_Msk

+#define RCC_AHB4LPENR_GPIOILPEN_Pos            (8U)

+#define RCC_AHB4LPENR_GPIOILPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */

+#define RCC_AHB4LPENR_GPIOILPEN                RCC_AHB4LPENR_GPIOILPEN_Msk

+#define RCC_AHB4LPENR_GPIOJLPEN_Pos            (9U)

+#define RCC_AHB4LPENR_GPIOJLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */

+#define RCC_AHB4LPENR_GPIOJLPEN                RCC_AHB4LPENR_GPIOJLPEN_Msk

+#define RCC_AHB4LPENR_GPIOKLPEN_Pos            (10U)

+#define RCC_AHB4LPENR_GPIOKLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */

+#define RCC_AHB4LPENR_GPIOKLPEN                RCC_AHB4LPENR_GPIOKLPEN_Msk

+#define RCC_AHB4LPENR_BDMA2LPEN_Pos             (21U)

+#define RCC_AHB4LPENR_BDMA2LPEN_Msk             (0x1UL << RCC_AHB4LPENR_BDMA2LPEN_Pos) /*!< 0x00200000 */

+#define RCC_AHB4LPENR_BDMA2LPEN                 RCC_AHB4LPENR_BDMA2LPEN_Msk

+#define RCC_AHB4LPENR_BKPRAMLPEN_Pos           (28U)

+#define RCC_AHB4LPENR_BKPRAMLPEN_Msk           (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */

+#define RCC_AHB4LPENR_BKPRAMLPEN               RCC_AHB4LPENR_BKPRAMLPEN_Msk

+#define RCC_AHB4LPENR_SRDSRAMLPEN_Pos          (29U)

+#define RCC_AHB4LPENR_SRDSRAMLPEN_Msk          (0x1UL << RCC_AHB4LPENR_SRDSRAMLPEN_Pos) /*!< 0x20000000 */

+#define RCC_AHB4LPENR_SRDSRAMLPEN              RCC_AHB4LPENR_SRDSRAMLPEN_Msk

+

+/********************  Bit definition for RCC_APB3LPENR register  ******************/

+#define RCC_APB3LPENR_LTDCLPEN_Pos             (3U)

+#define RCC_APB3LPENR_LTDCLPEN_Msk             (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB3LPENR_LTDCLPEN                 RCC_APB3LPENR_LTDCLPEN_Msk

+#define RCC_APB3LPENR_WWDGLPEN_Pos             (6U)

+#define RCC_APB3LPENR_WWDGLPEN_Msk             (0x1UL << RCC_APB3LPENR_WWDGLPEN_Pos)  /*!< 0x00000040 */

+#define RCC_APB3LPENR_WWDGLPEN                 RCC_APB3LPENR_WWDGLPEN_Msk

+

+/* Legacy define */

+#define RCC_APB3LPENR_WWDG1LPEN_Pos            RCC_APB3LPENR_WWDGLPEN_Pos

+#define RCC_APB3LPENR_WWDG1LPEN_Msk            RCC_APB3LPENR_WWDGLPEN_Msk

+#define RCC_APB3LPENR_WWDG1LPEN                RCC_APB3LPENR_WWDGLPEN

+/********************  Bit definition for RCC_APB1LLPENR register  ******************/

+

+#define RCC_APB1LLPENR_TIM2LPEN_Pos            (0U)

+#define RCC_APB1LLPENR_TIM2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */

+#define RCC_APB1LLPENR_TIM2LPEN                RCC_APB1LLPENR_TIM2LPEN_Msk

+#define RCC_APB1LLPENR_TIM3LPEN_Pos            (1U)

+#define RCC_APB1LLPENR_TIM3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1LLPENR_TIM3LPEN                RCC_APB1LLPENR_TIM3LPEN_Msk

+#define RCC_APB1LLPENR_TIM4LPEN_Pos            (2U)

+#define RCC_APB1LLPENR_TIM4LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1LLPENR_TIM4LPEN                RCC_APB1LLPENR_TIM4LPEN_Msk

+#define RCC_APB1LLPENR_TIM5LPEN_Pos            (3U)

+#define RCC_APB1LLPENR_TIM5LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB1LLPENR_TIM5LPEN                RCC_APB1LLPENR_TIM5LPEN_Msk

+#define RCC_APB1LLPENR_TIM6LPEN_Pos            (4U)

+#define RCC_APB1LLPENR_TIM6LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1LLPENR_TIM6LPEN                RCC_APB1LLPENR_TIM6LPEN_Msk

+#define RCC_APB1LLPENR_TIM7LPEN_Pos            (5U)

+#define RCC_APB1LLPENR_TIM7LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1LLPENR_TIM7LPEN                RCC_APB1LLPENR_TIM7LPEN_Msk

+#define RCC_APB1LLPENR_TIM12LPEN_Pos           (6U)

+#define RCC_APB1LLPENR_TIM12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */

+#define RCC_APB1LLPENR_TIM12LPEN               RCC_APB1LLPENR_TIM12LPEN_Msk

+#define RCC_APB1LLPENR_TIM13LPEN_Pos           (7U)

+#define RCC_APB1LLPENR_TIM13LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB1LLPENR_TIM13LPEN               RCC_APB1LLPENR_TIM13LPEN_Msk

+#define RCC_APB1LLPENR_TIM14LPEN_Pos           (8U)

+#define RCC_APB1LLPENR_TIM14LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1LLPENR_TIM14LPEN               RCC_APB1LLPENR_TIM14LPEN_Msk

+#define RCC_APB1LLPENR_LPTIM1LPEN_Pos          (9U)

+#define RCC_APB1LLPENR_LPTIM1LPEN_Msk          (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */

+#define RCC_APB1LLPENR_LPTIM1LPEN              RCC_APB1LLPENR_LPTIM1LPEN_Msk

+

+

+#define RCC_APB1LLPENR_SPI2LPEN_Pos            (14U)

+#define RCC_APB1LLPENR_SPI2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */

+#define RCC_APB1LLPENR_SPI2LPEN                RCC_APB1LLPENR_SPI2LPEN_Msk

+#define RCC_APB1LLPENR_SPI3LPEN_Pos            (15U)

+#define RCC_APB1LLPENR_SPI3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */

+#define RCC_APB1LLPENR_SPI3LPEN                RCC_APB1LLPENR_SPI3LPEN_Msk

+#define RCC_APB1LLPENR_SPDIFRXLPEN_Pos         (16U)

+#define RCC_APB1LLPENR_SPDIFRXLPEN_Msk         (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB1LLPENR_SPDIFRXLPEN             RCC_APB1LLPENR_SPDIFRXLPEN_Msk

+#define RCC_APB1LLPENR_USART2LPEN_Pos          (17U)

+#define RCC_APB1LLPENR_USART2LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */

+#define RCC_APB1LLPENR_USART2LPEN              RCC_APB1LLPENR_USART2LPEN_Msk

+#define RCC_APB1LLPENR_USART3LPEN_Pos          (18U)

+#define RCC_APB1LLPENR_USART3LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */

+#define RCC_APB1LLPENR_USART3LPEN              RCC_APB1LLPENR_USART3LPEN_Msk

+#define RCC_APB1LLPENR_UART4LPEN_Pos           (19U)

+#define RCC_APB1LLPENR_UART4LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */

+#define RCC_APB1LLPENR_UART4LPEN               RCC_APB1LLPENR_UART4LPEN_Msk

+#define RCC_APB1LLPENR_UART5LPEN_Pos           (20U)

+#define RCC_APB1LLPENR_UART5LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */

+#define RCC_APB1LLPENR_UART5LPEN               RCC_APB1LLPENR_UART5LPEN_Msk

+#define RCC_APB1LLPENR_I2C1LPEN_Pos            (21U)

+#define RCC_APB1LLPENR_I2C1LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */

+#define RCC_APB1LLPENR_I2C1LPEN                RCC_APB1LLPENR_I2C1LPEN_Msk

+#define RCC_APB1LLPENR_I2C2LPEN_Pos            (22U)

+#define RCC_APB1LLPENR_I2C2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */

+#define RCC_APB1LLPENR_I2C2LPEN                RCC_APB1LLPENR_I2C2LPEN_Msk

+#define RCC_APB1LLPENR_I2C3LPEN_Pos            (23U)

+#define RCC_APB1LLPENR_I2C3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */

+#define RCC_APB1LLPENR_I2C3LPEN                RCC_APB1LLPENR_I2C3LPEN_Msk

+#define RCC_APB1LLPENR_CECLPEN_Pos             (27U)

+#define RCC_APB1LLPENR_CECLPEN_Msk             (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */

+#define RCC_APB1LLPENR_CECLPEN                 RCC_APB1LLPENR_CECLPEN_Msk

+#define RCC_APB1LLPENR_DAC12LPEN_Pos           (29U)

+#define RCC_APB1LLPENR_DAC12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */

+#define RCC_APB1LLPENR_DAC12LPEN               RCC_APB1LLPENR_DAC12LPEN_Msk

+#define RCC_APB1LLPENR_UART7LPEN_Pos           (30U)

+#define RCC_APB1LLPENR_UART7LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */

+#define RCC_APB1LLPENR_UART7LPEN               RCC_APB1LLPENR_UART7LPEN_Msk

+#define RCC_APB1LLPENR_UART8LPEN_Pos           (31U)

+#define RCC_APB1LLPENR_UART8LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */

+#define RCC_APB1LLPENR_UART8LPEN               RCC_APB1LLPENR_UART8LPEN_Msk

+

+/* Legacy define */

+#define RCC_APB1LLPENR_HDMICECEN_Pos           RCC_APB1LLPENR_CECLPEN_Pos

+#define RCC_APB1LLPENR_HDMICECEN_Msk           RCC_APB1LLPENR_CECLPEN_Msk

+#define RCC_APB1LLPENR_HDMICECEN               RCC_APB1LLPENR_CECLPEN

+/********************  Bit definition for RCC_APB1HLPENR register  ******************/

+#define RCC_APB1HLPENR_CRSLPEN_Pos             (1U)

+#define RCC_APB1HLPENR_CRSLPEN_Msk             (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1HLPENR_CRSLPEN                 RCC_APB1HLPENR_CRSLPEN_Msk

+#define RCC_APB1HLPENR_SWPMILPEN_Pos           (2U)

+#define RCC_APB1HLPENR_SWPMILPEN_Msk           (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1HLPENR_SWPMILPEN               RCC_APB1HLPENR_SWPMILPEN_Msk

+#define RCC_APB1HLPENR_OPAMPLPEN_Pos           (4U)

+#define RCC_APB1HLPENR_OPAMPLPEN_Msk           (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1HLPENR_OPAMPLPEN               RCC_APB1HLPENR_OPAMPLPEN_Msk

+#define RCC_APB1HLPENR_MDIOSLPEN_Pos           (5U)

+#define RCC_APB1HLPENR_MDIOSLPEN_Msk           (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1HLPENR_MDIOSLPEN               RCC_APB1HLPENR_MDIOSLPEN_Msk

+#define RCC_APB1HLPENR_FDCANLPEN_Pos           (8U)

+#define RCC_APB1HLPENR_FDCANLPEN_Msk           (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1HLPENR_FDCANLPEN               RCC_APB1HLPENR_FDCANLPEN_Msk

+

+/********************  Bit definition for RCC_APB2LPENR register  ******************/

+#define RCC_APB2LPENR_TIM1LPEN_Pos             (0U)

+#define RCC_APB2LPENR_TIM1LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */

+#define RCC_APB2LPENR_TIM1LPEN                 RCC_APB2LPENR_TIM1LPEN_Msk

+#define RCC_APB2LPENR_TIM8LPEN_Pos             (1U)

+#define RCC_APB2LPENR_TIM8LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB2LPENR_TIM8LPEN                 RCC_APB2LPENR_TIM8LPEN_Msk

+#define RCC_APB2LPENR_USART1LPEN_Pos           (4U)

+#define RCC_APB2LPENR_USART1LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB2LPENR_USART1LPEN               RCC_APB2LPENR_USART1LPEN_Msk

+#define RCC_APB2LPENR_USART6LPEN_Pos           (5U)

+#define RCC_APB2LPENR_USART6LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB2LPENR_USART6LPEN               RCC_APB2LPENR_USART6LPEN_Msk

+#define RCC_APB2LPENR_UART9LPEN_Pos            (6U)

+#define RCC_APB2LPENR_UART9LPEN_Msk            (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos) /*!< 0x00000040 */

+#define RCC_APB2LPENR_UART9LPEN                 RCC_APB2LPENR_UART9LPEN_Msk

+#define RCC_APB2LPENR_USART10LPEN_Pos          (7U)

+#define RCC_APB2LPENR_USART10LPEN_Msk          (0x1UL << RCC_APB2LPENR_USART10LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB2LPENR_USART10LPEN               RCC_APB2LPENR_USART10LPEN_Msk

+#define RCC_APB2LPENR_SPI1LPEN_Pos             (12U)

+#define RCC_APB2LPENR_SPI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */

+#define RCC_APB2LPENR_SPI1LPEN                 RCC_APB2LPENR_SPI1LPEN_Msk

+#define RCC_APB2LPENR_SPI4LPEN_Pos             (13U)

+#define RCC_APB2LPENR_SPI4LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */

+#define RCC_APB2LPENR_SPI4LPEN                 RCC_APB2LPENR_SPI4LPEN_Msk

+#define RCC_APB2LPENR_TIM15LPEN_Pos            (16U)

+#define RCC_APB2LPENR_TIM15LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB2LPENR_TIM15LPEN                RCC_APB2LPENR_TIM15LPEN_Msk

+#define RCC_APB2LPENR_TIM16LPEN_Pos            (17U)

+#define RCC_APB2LPENR_TIM16LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */

+#define RCC_APB2LPENR_TIM16LPEN                RCC_APB2LPENR_TIM16LPEN_Msk

+#define RCC_APB2LPENR_TIM17LPEN_Pos            (18U)

+#define RCC_APB2LPENR_TIM17LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */

+#define RCC_APB2LPENR_TIM17LPEN                RCC_APB2LPENR_TIM17LPEN_Msk

+#define RCC_APB2LPENR_SPI5LPEN_Pos             (20U)

+#define RCC_APB2LPENR_SPI5LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */

+#define RCC_APB2LPENR_SPI5LPEN                 RCC_APB2LPENR_SPI5LPEN_Msk

+#define RCC_APB2LPENR_SAI1LPEN_Pos             (22U)

+#define RCC_APB2LPENR_SAI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */

+#define RCC_APB2LPENR_SAI1LPEN                 RCC_APB2LPENR_SAI1LPEN_Msk

+#define RCC_APB2LPENR_SAI2LPEN_Pos             (23U)

+#define RCC_APB2LPENR_SAI2LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */

+#define RCC_APB2LPENR_SAI2LPEN                 RCC_APB2LPENR_SAI2LPEN_Msk

+#define RCC_APB2LPENR_DFSDM1LPEN_Pos           (30U)

+#define RCC_APB2LPENR_DFSDM1LPEN_Msk           (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x40000000 */

+#define RCC_APB2LPENR_DFSDM1LPEN               RCC_APB2LPENR_DFSDM1LPEN_Msk

+

+/********************  Bit definition for RCC_APB4LPENR register  ******************/

+#define RCC_APB4LPENR_SYSCFGLPEN_Pos           (1U)

+#define RCC_APB4LPENR_SYSCFGLPEN_Msk           (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB4LPENR_SYSCFGLPEN               RCC_APB4LPENR_SYSCFGLPEN_Msk

+#define RCC_APB4LPENR_LPUART1LPEN_Pos          (3U)

+#define RCC_APB4LPENR_LPUART1LPEN_Msk          (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB4LPENR_LPUART1LPEN              RCC_APB4LPENR_LPUART1LPEN_Msk

+#define RCC_APB4LPENR_SPI6LPEN_Pos             (5U)

+#define RCC_APB4LPENR_SPI6LPEN_Msk             (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB4LPENR_SPI6LPEN                 RCC_APB4LPENR_SPI6LPEN_Msk

+#define RCC_APB4LPENR_I2C4LPEN_Pos             (7U)

+#define RCC_APB4LPENR_I2C4LPEN_Msk             (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB4LPENR_I2C4LPEN                 RCC_APB4LPENR_I2C4LPEN_Msk

+#define RCC_APB4LPENR_LPTIM2LPEN_Pos           (9U)

+#define RCC_APB4LPENR_LPTIM2LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */

+#define RCC_APB4LPENR_LPTIM2LPEN               RCC_APB4LPENR_LPTIM2LPEN_Msk

+#define RCC_APB4LPENR_LPTIM3LPEN_Pos           (10U)

+#define RCC_APB4LPENR_LPTIM3LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */

+#define RCC_APB4LPENR_LPTIM3LPEN               RCC_APB4LPENR_LPTIM3LPEN_Msk

+#define RCC_APB4LPENR_DAC2LPEN_Pos             (13U)

+#define RCC_APB4LPENR_DAC2LPEN_Msk             (0x1UL << RCC_APB4LPENR_DAC2LPEN_Pos) /*!< 0x00002000 */

+#define RCC_APB4LPENR_DAC2LPEN                 RCC_APB4LPENR_DAC2LPEN_Msk

+#define RCC_APB4LPENR_COMP12LPEN_Pos           (14U)

+#define RCC_APB4LPENR_COMP12LPEN_Msk           (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */

+#define RCC_APB4LPENR_COMP12LPEN               RCC_APB4LPENR_COMP12LPEN_Msk

+#define RCC_APB4LPENR_VREFLPEN_Pos             (15U)

+#define RCC_APB4LPENR_VREFLPEN_Msk             (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */

+#define RCC_APB4LPENR_VREFLPEN                 RCC_APB4LPENR_VREFLPEN_Msk

+#define RCC_APB4LPENR_RTCAPBLPEN_Pos           (16U)

+#define RCC_APB4LPENR_RTCAPBLPEN_Msk           (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB4LPENR_RTCAPBLPEN               RCC_APB4LPENR_RTCAPBLPEN_Msk

+

+#define RCC_APB4LPENR_DTSLPEN_Pos              (26U)

+#define RCC_APB4LPENR_DTSLPEN_Msk              (0x1UL << RCC_APB4LPENR_DTSLPEN_Pos) /*!< 0x04000000 */

+#define RCC_APB4LPENR_DTSLPEN                  RCC_APB4LPENR_DTSLPEN_Msk

+#define RCC_APB4LPENR_DFSDM2LPEN_Pos           (27U)

+#define RCC_APB4LPENR_DFSDM2LPEN_Msk           (0x1UL << RCC_APB4LPENR_DFSDM2LPEN_Pos) /*!< 0x08000000 */

+#define RCC_APB4LPENR_DFSDM2LPEN                RCC_APB4LPENR_DFSDM2LPEN_Msk

+

+/********************  Bit definition for RCC_RSR register  *******************/

+#define RCC_RSR_RMVF_Pos                       (16U)

+#define RCC_RSR_RMVF_Msk                       (0x1UL << RCC_RSR_RMVF_Pos)     /*!< 0x00010000 */

+#define RCC_RSR_RMVF                           RCC_RSR_RMVF_Msk

+#define RCC_RSR_CDRSTF_Pos                     (19U)

+#define RCC_RSR_CDRSTF_Msk                     (0x1UL << RCC_RSR_CDRSTF_Pos)   /*!< 0x00080000 */

+#define RCC_RSR_CDRSTF                         RCC_RSR_CDRSTF_Msk

+#define RCC_RSR_BORRSTF_Pos                    (21U)

+#define RCC_RSR_BORRSTF_Msk                    (0x1UL << RCC_RSR_BORRSTF_Pos)  /*!< 0x00200000 */

+#define RCC_RSR_BORRSTF                        RCC_RSR_BORRSTF_Msk

+#define RCC_RSR_PINRSTF_Pos                    (22U)

+#define RCC_RSR_PINRSTF_Msk                    (0x1UL << RCC_RSR_PINRSTF_Pos)  /*!< 0x00400000 */

+#define RCC_RSR_PINRSTF                        RCC_RSR_PINRSTF_Msk

+#define RCC_RSR_PORRSTF_Pos                    (23U)

+#define RCC_RSR_PORRSTF_Msk                    (0x1UL << RCC_RSR_PORRSTF_Pos)  /*!< 0x00800000 */

+#define RCC_RSR_PORRSTF                        RCC_RSR_PORRSTF_Msk

+#define RCC_RSR_SFTRSTF_Pos                    (24U)

+#define RCC_RSR_SFTRSTF_Msk                    (0x1UL << RCC_RSR_SFTRSTF_Pos)  /*!< 0x01000000 */

+#define RCC_RSR_SFTRSTF                        RCC_RSR_SFTRSTF_Msk

+#define RCC_RSR_IWDGRSTF_Pos                   (26U)

+#define RCC_RSR_IWDGRSTF_Msk                   (0x1UL << RCC_RSR_IWDGRSTF_Pos) /*!< 0x04000000 */

+#define RCC_RSR_IWDGRSTF                       RCC_RSR_IWDGRSTF_Msk

+#define RCC_RSR_WWDGRSTF_Pos                   (28U)

+#define RCC_RSR_WWDGRSTF_Msk                   (0x1UL << RCC_RSR_WWDGRSTF_Pos) /*!< 0x10000000 */

+#define RCC_RSR_WWDGRSTF                       RCC_RSR_WWDGRSTF_Msk

+

+#define RCC_RSR_LPWRRSTF_Pos                   (30U)

+#define RCC_RSR_LPWRRSTF_Msk                   (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */

+#define RCC_RSR_LPWRRSTF                       RCC_RSR_LPWRRSTF_Msk

+

+

+/* Legacy define */

+#define RCC_RSR_IWDG1RSTF_Pos                  RCC_RSR_IWDGRSTF_Pos

+#define RCC_RSR_IWDG1RSTF_Msk                  RCC_RSR_IWDGRSTF_Msk

+#define RCC_RSR_IWDG1RSTF                      RCC_RSR_IWDGRSTF

+#define RCC_RSR_WWDG1RSTF_Pos                  RCC_RSR_WWDGRSTF_Pos

+#define RCC_RSR_WWDG1RSTF_Msk                  RCC_RSR_WWDGRSTF_Msk

+#define RCC_RSR_WWDG1RSTF                      RCC_RSR_WWDGRSTF

+/******************************************************************************/

+/*                                                                            */

+/*                                    RNG                                     */

+/*                                                                            */

+/******************************************************************************/

+/***************************    RNG VER  **************************************/

+#define RNG_VER_3_1

+/********************  Bits definition for RNG_CR register  *******************/

+#define RNG_CR_RNGEN_Pos    (2U)

+#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */

+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk

+#define RNG_CR_IE_Pos       (3U)

+#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */

+#define RNG_CR_IE           RNG_CR_IE_Msk

+#define RNG_CR_CED_Pos      (5U)

+#define RNG_CR_CED_Msk      (0x1UL << RNG_CR_CED_Pos)                          /*!< 0x00000020 */

+#define RNG_CR_CED          RNG_CR_CED_Msk

+#define RNG_CR_RNG_CONFIG3_Pos      (8U)

+#define RNG_CR_RNG_CONFIG3_Msk      (0xFUL << RNG_CR_RNG_CONFIG3_Pos)          /*!< 0x00000F00 */

+#define RNG_CR_RNG_CONFIG3          RNG_CR_RNG_CONFIG3_Msk

+#define RNG_CR_NISTC_Pos            (12U)

+#define RNG_CR_NISTC_Msk            (0x1UL << RNG_CR_NISTC_Pos)                /*!< 0x00001000 */

+#define RNG_CR_NISTC                RNG_CR_NISTC_Msk

+#define RNG_CR_RNG_CONFIG2_Pos      (13U)

+#define RNG_CR_RNG_CONFIG2_Msk      (0x7UL << RNG_CR_RNG_CONFIG2_Pos)          /*!< 0x0000E000 */

+#define RNG_CR_RNG_CONFIG2          RNG_CR_RNG_CONFIG2_Msk

+#define RNG_CR_CLKDIV_Pos           (16U)

+#define RNG_CR_CLKDIV_Msk           (0xFUL << RNG_CR_CLKDIV_Pos)               /*!< 0x000F0000 */

+#define RNG_CR_CLKDIV               RNG_CR_CLKDIV_Msk

+#define RNG_CR_CLKDIV_0             (0x1U << RNG_CR_CLKDIV_Pos)                /*!< 0x00010000 */

+#define RNG_CR_CLKDIV_1             (0x2U << RNG_CR_CLKDIV_Pos)                /*!< 0x00020000 */

+#define RNG_CR_CLKDIV_2             (0x4U << RNG_CR_CLKDIV_Pos)                /*!< 0x00040000 */

+#define RNG_CR_CLKDIV_3             (0x8U << RNG_CR_CLKDIV_Pos)                /*!< 0x00080000 */

+#define RNG_CR_RNG_CONFIG1_Pos      (20U)

+#define RNG_CR_RNG_CONFIG1_Msk      (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)         /*!< 0x03F00000 */

+#define RNG_CR_RNG_CONFIG1          RNG_CR_RNG_CONFIG1_Msk

+#define RNG_CR_CONDRST_Pos         (30U)

+#define RNG_CR_CONDRST_Msk         (0x1UL << RNG_CR_CONDRST_Pos)                  /*!< 0x40000000 */

+#define RNG_CR_CONDRST             RNG_CR_CONDRST_Msk

+#define RNG_CR_CONFIGLOCK_Pos      (31U)

+#define RNG_CR_CONFIGLOCK_Msk      (0x1UL << RNG_CR_CONFIGLOCK_Pos)            /*!< 0x80000000 */

+#define RNG_CR_CONFIGLOCK          RNG_CR_CONFIGLOCK_Msk

+

+/********************  Bits definition for RNG_SR register  *******************/

+#define RNG_SR_DRDY_Pos     (0U)

+#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */

+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk

+#define RNG_SR_CECS_Pos     (1U)

+#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */

+#define RNG_SR_CECS         RNG_SR_CECS_Msk

+#define RNG_SR_SECS_Pos     (2U)

+#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */

+#define RNG_SR_SECS         RNG_SR_SECS_Msk

+#define RNG_SR_CEIS_Pos     (5U)

+#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */

+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk

+#define RNG_SR_SEIS_Pos     (6U)

+#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */

+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                           Real-Time Clock (RTC)                            */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for RTC_TR register  *******************/

+#define RTC_TR_PM_Pos                  (22U)

+#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */

+#define RTC_TR_PM                      RTC_TR_PM_Msk

+#define RTC_TR_HT_Pos                  (20U)

+#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */

+#define RTC_TR_HT                      RTC_TR_HT_Msk

+#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */

+#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */

+#define RTC_TR_HU_Pos                  (16U)

+#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */

+#define RTC_TR_HU                      RTC_TR_HU_Msk

+#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */

+#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */

+#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */

+#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */

+#define RTC_TR_MNT_Pos                 (12U)

+#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */

+#define RTC_TR_MNT                     RTC_TR_MNT_Msk

+#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */

+#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */

+#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */

+#define RTC_TR_MNU_Pos                 (8U)

+#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */

+#define RTC_TR_MNU                     RTC_TR_MNU_Msk

+#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */

+#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */

+#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */

+#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */

+#define RTC_TR_ST_Pos                  (4U)

+#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */

+#define RTC_TR_ST                      RTC_TR_ST_Msk

+#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */

+#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */

+#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */

+#define RTC_TR_SU_Pos                  (0U)

+#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */

+#define RTC_TR_SU                      RTC_TR_SU_Msk

+#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */

+#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */

+#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */

+#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_DR register  *******************/

+#define RTC_DR_YT_Pos                  (20U)

+#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */

+#define RTC_DR_YT                      RTC_DR_YT_Msk

+#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */

+#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */

+#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */

+#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */

+#define RTC_DR_YU_Pos                  (16U)

+#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */

+#define RTC_DR_YU                      RTC_DR_YU_Msk

+#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */

+#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */

+#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */

+#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */

+#define RTC_DR_WDU_Pos                 (13U)

+#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */

+#define RTC_DR_WDU                     RTC_DR_WDU_Msk

+#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */

+#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */

+#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */

+#define RTC_DR_MT_Pos                  (12U)

+#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */

+#define RTC_DR_MT                      RTC_DR_MT_Msk

+#define RTC_DR_MU_Pos                  (8U)

+#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */

+#define RTC_DR_MU                      RTC_DR_MU_Msk

+#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */

+#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */

+#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */

+#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */

+#define RTC_DR_DT_Pos                  (4U)

+#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */

+#define RTC_DR_DT                      RTC_DR_DT_Msk

+#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */

+#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */

+#define RTC_DR_DU_Pos                  (0U)

+#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */

+#define RTC_DR_DU                      RTC_DR_DU_Msk

+#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */

+#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */

+#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */

+#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_CR register  *******************/

+#define RTC_CR_OUT2EN_Pos            (31U)

+#define RTC_CR_OUT2EN_Msk            (0x1UL << RTC_CR_OUT2EN_Pos)              /*!< 0x80000000 */

+#define RTC_CR_OUT2EN                RTC_CR_OUT2EN_Msk                         /*!<RTC_OUT2 output enable */

+#define RTC_CR_TAMPALRM_TYPE_Pos     (30U)

+#define RTC_CR_TAMPALRM_TYPE_Msk     (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)       /*!< 0x40000000 */

+#define RTC_CR_TAMPALRM_TYPE         RTC_CR_TAMPALRM_TYPE_Msk                  /*!<TAMPALARM output type  */

+#define RTC_CR_TAMPALRM_PU_Pos       (29U)

+#define RTC_CR_TAMPALRM_PU_Msk       (0x1UL << RTC_CR_TAMPALRM_PU_Pos)         /*!< 0x20000000 */

+#define RTC_CR_TAMPALRM_PU           RTC_CR_TAMPALRM_PU_Msk                    /*!<TAMPALARM output pull-up config */

+#define RTC_CR_TAMPOE_Pos            (26U)

+#define RTC_CR_TAMPOE_Msk            (0x1UL << RTC_CR_TAMPOE_Pos)              /*!< 0x04000000 */

+#define RTC_CR_TAMPOE                RTC_CR_TAMPOE_Msk                         /*!<Tamper detection output enable on TAMPALARM  */

+#define RTC_CR_TAMPTS_Pos            (25U)

+#define RTC_CR_TAMPTS_Msk            (0x1UL << RTC_CR_TAMPTS_Pos)              /*!< 0x02000000 */

+#define RTC_CR_TAMPTS                RTC_CR_TAMPTS_Msk                         /*!<Activate timestamp on tamper detection event  */

+#define RTC_CR_ITSE_Pos                (24U)

+#define RTC_CR_ITSE_Msk                (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */

+#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk

+#define RTC_CR_COE_Pos                 (23U)

+#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */

+#define RTC_CR_COE                     RTC_CR_COE_Msk

+#define RTC_CR_OSEL_Pos                (21U)

+#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */

+#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk

+#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */

+#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */

+#define RTC_CR_POL_Pos                 (20U)

+#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */

+#define RTC_CR_POL                     RTC_CR_POL_Msk

+#define RTC_CR_COSEL_Pos               (19U)

+#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */

+#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk

+#define RTC_CR_BKP_Pos                 (18U)

+#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */

+#define RTC_CR_BKP                     RTC_CR_BKP_Msk

+#define RTC_CR_SUB1H_Pos               (17U)

+#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */

+#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk

+#define RTC_CR_ADD1H_Pos               (16U)

+#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */

+#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk

+#define RTC_CR_TSIE_Pos                (15U)

+#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */

+#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk

+#define RTC_CR_WUTIE_Pos               (14U)

+#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */

+#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk

+#define RTC_CR_ALRBIE_Pos              (13U)

+#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */

+#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk

+#define RTC_CR_ALRAIE_Pos              (12U)

+#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */

+#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk

+#define RTC_CR_TSE_Pos                 (11U)

+#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */

+#define RTC_CR_TSE                     RTC_CR_TSE_Msk

+#define RTC_CR_WUTE_Pos                (10U)

+#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */

+#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk

+#define RTC_CR_ALRBE_Pos               (9U)

+#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */

+#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk

+#define RTC_CR_ALRAE_Pos               (8U)

+#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */

+#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk

+#define RTC_CR_FMT_Pos                 (6U)

+#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */

+#define RTC_CR_FMT                     RTC_CR_FMT_Msk

+#define RTC_CR_BYPSHAD_Pos             (5U)

+#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */

+#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk

+#define RTC_CR_REFCKON_Pos             (4U)

+#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */

+#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk

+#define RTC_CR_TSEDGE_Pos              (3U)

+#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */

+#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk

+#define RTC_CR_WUCKSEL_Pos             (0U)

+#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */

+#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk

+#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */

+#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */

+#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */

+

+/********************  Bits definition for RTC_ICSR register  ******************/

+#define RTC_ICSR_RECALPF_Pos         (16U)

+#define RTC_ICSR_RECALPF_Msk         (0x1UL << RTC_ICSR_RECALPF_Pos)           /*!< 0x00010000 */

+#define RTC_ICSR_RECALPF             RTC_ICSR_RECALPF_Msk

+#define RTC_ICSR_INIT_Pos            (7U)

+#define RTC_ICSR_INIT_Msk            (0x1UL << RTC_ICSR_INIT_Pos)              /*!< 0x00000080 */

+#define RTC_ICSR_INIT                RTC_ICSR_INIT_Msk

+#define RTC_ICSR_INITF_Pos           (6U)

+#define RTC_ICSR_INITF_Msk           (0x1UL << RTC_ICSR_INITF_Pos)             /*!< 0x00000040 */

+#define RTC_ICSR_INITF               RTC_ICSR_INITF_Msk

+#define RTC_ICSR_RSF_Pos             (5U)

+#define RTC_ICSR_RSF_Msk             (0x1UL << RTC_ICSR_RSF_Pos)               /*!< 0x00000020 */

+#define RTC_ICSR_RSF                 RTC_ICSR_RSF_Msk

+#define RTC_ICSR_INITS_Pos           (4U)

+#define RTC_ICSR_INITS_Msk           (0x1UL << RTC_ICSR_INITS_Pos)             /*!< 0x00000010 */

+#define RTC_ICSR_INITS               RTC_ICSR_INITS_Msk

+#define RTC_ICSR_SHPF_Pos            (3U)

+#define RTC_ICSR_SHPF_Msk            (0x1UL << RTC_ICSR_SHPF_Pos)              /*!< 0x00000008 */

+#define RTC_ICSR_SHPF                RTC_ICSR_SHPF_Msk

+#define RTC_ICSR_WUTWF_Pos           (2U)

+#define RTC_ICSR_WUTWF_Msk           (0x1UL << RTC_ICSR_WUTWF_Pos)             /*!< 0x00000004 */

+#define RTC_ICSR_WUTWF               RTC_ICSR_WUTWF_Msk

+#define RTC_ICSR_ALRBWF_Pos          (1U)

+#define RTC_ICSR_ALRBWF_Msk          (0x1UL << RTC_ICSR_ALRBWF_Pos)            /*!< 0x00000002 */

+#define RTC_ICSR_ALRBWF              RTC_ICSR_ALRBWF_Msk

+#define RTC_ICSR_ALRAWF_Pos          (0U)

+#define RTC_ICSR_ALRAWF_Msk          (0x1UL << RTC_ICSR_ALRAWF_Pos)            /*!< 0x00000001 */

+#define RTC_ICSR_ALRAWF              RTC_ICSR_ALRAWF_Msk

+

+/********************  Bits definition for RTC_PRER register  *****************/

+#define RTC_PRER_PREDIV_A_Pos          (16U)

+#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */

+#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk

+#define RTC_PRER_PREDIV_S_Pos          (0U)

+#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */

+#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk

+

+/********************  Bits definition for RTC_WUTR register  *****************/

+#define RTC_WUTR_WUT_Pos               (0U)

+#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */

+#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk

+

+/********************  Bits definition for RTC_ALRMAR register  ***************/

+#define RTC_ALRMAR_MSK4_Pos            (31U)

+#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */

+#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk

+#define RTC_ALRMAR_WDSEL_Pos           (30U)

+#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */

+#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk

+#define RTC_ALRMAR_DT_Pos              (28U)

+#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */

+#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk

+#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */

+#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */

+#define RTC_ALRMAR_DU_Pos              (24U)

+#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */

+#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk

+#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */

+#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */

+#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */

+#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */

+#define RTC_ALRMAR_MSK3_Pos            (23U)

+#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */

+#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk

+#define RTC_ALRMAR_PM_Pos              (22U)

+#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */

+#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk

+#define RTC_ALRMAR_HT_Pos              (20U)

+#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */

+#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk

+#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */

+#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */

+#define RTC_ALRMAR_HU_Pos              (16U)

+#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */

+#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk

+#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */

+#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */

+#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */

+#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */

+#define RTC_ALRMAR_MSK2_Pos            (15U)

+#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */

+#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk

+#define RTC_ALRMAR_MNT_Pos             (12U)

+#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */

+#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk

+#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */

+#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */

+#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */

+#define RTC_ALRMAR_MNU_Pos             (8U)

+#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */

+#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk

+#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */

+#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */

+#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */

+#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */

+#define RTC_ALRMAR_MSK1_Pos            (7U)

+#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */

+#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk

+#define RTC_ALRMAR_ST_Pos              (4U)

+#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */

+#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk

+#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */

+#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */

+#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */

+#define RTC_ALRMAR_SU_Pos              (0U)

+#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */

+#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk

+#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */

+#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */

+#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */

+#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_ALRMBR register  ***************/

+#define RTC_ALRMBR_MSK4_Pos            (31U)

+#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */

+#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk

+#define RTC_ALRMBR_WDSEL_Pos           (30U)

+#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */

+#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk

+#define RTC_ALRMBR_DT_Pos              (28U)

+#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */

+#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk

+#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */

+#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */

+#define RTC_ALRMBR_DU_Pos              (24U)

+#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */

+#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk

+#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */

+#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */

+#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */

+#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */

+#define RTC_ALRMBR_MSK3_Pos            (23U)

+#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */

+#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk

+#define RTC_ALRMBR_PM_Pos              (22U)

+#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */

+#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk

+#define RTC_ALRMBR_HT_Pos              (20U)

+#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */

+#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk

+#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */

+#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */

+#define RTC_ALRMBR_HU_Pos              (16U)

+#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */

+#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk

+#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */

+#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */

+#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */

+#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */

+#define RTC_ALRMBR_MSK2_Pos            (15U)

+#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */

+#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk

+#define RTC_ALRMBR_MNT_Pos             (12U)

+#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */

+#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk

+#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */

+#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */

+#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */

+#define RTC_ALRMBR_MNU_Pos             (8U)

+#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */

+#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk

+#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */

+#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */

+#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */

+#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */

+#define RTC_ALRMBR_MSK1_Pos            (7U)

+#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */

+#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk

+#define RTC_ALRMBR_ST_Pos              (4U)

+#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */

+#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk

+#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */

+#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */

+#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */

+#define RTC_ALRMBR_SU_Pos              (0U)

+#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */

+#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk

+#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */

+#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */

+#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */

+#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_WPR register  ******************/

+#define RTC_WPR_KEY_Pos                (0U)

+#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */

+#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk

+

+/********************  Bits definition for RTC_SSR register  ******************/

+#define RTC_SSR_SS_Pos                 (0U)

+#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)            /*!< 0x0000FFFF */

+#define RTC_SSR_SS                     RTC_SSR_SS_Msk

+

+/********************  Bits definition for RTC_SHIFTR register  ***************/

+#define RTC_SHIFTR_SUBFS_Pos           (0U)

+#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */

+#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk

+#define RTC_SHIFTR_ADD1S_Pos           (31U)

+#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */

+#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk

+

+/********************  Bits definition for RTC_TSTR register  *****************/

+#define RTC_TSTR_PM_Pos                (22U)

+#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */

+#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk

+#define RTC_TSTR_HT_Pos                (20U)

+#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */

+#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk

+#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */

+#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */

+#define RTC_TSTR_HU_Pos                (16U)

+#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */

+#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk

+#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */

+#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */

+#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */

+#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */

+#define RTC_TSTR_MNT_Pos               (12U)

+#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */

+#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk

+#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */

+#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */

+#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */

+#define RTC_TSTR_MNU_Pos               (8U)

+#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */

+#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk

+#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */

+#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */

+#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */

+#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */

+#define RTC_TSTR_ST_Pos                (4U)

+#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */

+#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk

+#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */

+#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */

+#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */

+#define RTC_TSTR_SU_Pos                (0U)

+#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */

+#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk

+#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */

+#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */

+#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */

+#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_TSDR register  *****************/

+#define RTC_TSDR_WDU_Pos               (13U)

+#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */

+#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk

+#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */

+#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */

+#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */

+#define RTC_TSDR_MT_Pos                (12U)

+#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */

+#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk

+#define RTC_TSDR_MU_Pos                (8U)

+#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */

+#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk

+#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */

+#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */

+#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */

+#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */

+#define RTC_TSDR_DT_Pos                (4U)

+#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */

+#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk

+#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */

+#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */

+#define RTC_TSDR_DU_Pos                (0U)

+#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */

+#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk

+#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */

+#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */

+#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */

+#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_TSSSR register  ****************/

+#define RTC_TSSSR_SS_Pos               (0U)

+#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)          /*!< 0x0000FFFF */

+#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk

+

+/********************  Bits definition for RTC_CALR register  *****************/

+#define RTC_CALR_CALP_Pos              (15U)

+#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */

+#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk

+#define RTC_CALR_CALW8_Pos             (14U)

+#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */

+#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk

+#define RTC_CALR_CALW16_Pos            (13U)

+#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */

+#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk

+#define RTC_CALR_CALM_Pos              (0U)

+#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */

+#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk

+#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */

+#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */

+#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */

+#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */

+#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */

+#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */

+#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */

+#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */

+#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */

+

+

+/********************  Bits definition for RTC_ALRMASSR register  *************/

+#define RTC_ALRMASSR_MASKSS_Pos        (24U)

+#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x0F000000 */

+#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk

+#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */

+#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */

+#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */

+#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */

+#define RTC_ALRMASSR_SS_Pos            (0U)

+#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */

+#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk

+

+/********************  Bits definition for RTC_ALRMBSSR register  *************/

+#define RTC_ALRMBSSR_MASKSS_Pos        (24U)

+#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x0F000000 */

+#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk

+#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */

+#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */

+#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */

+#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */

+#define RTC_ALRMBSSR_SS_Pos            (0U)

+#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */

+#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk

+

+

+/********************  Bits definition for RTC_SR register  *******************/

+#define RTC_SR_ITSF_Pos              (5U)

+#define RTC_SR_ITSF_Msk              (0x1UL << RTC_SR_ITSF_Pos)                 /*!< 0x00000020 */

+#define RTC_SR_ITSF                  RTC_SR_ITSF_Msk

+#define RTC_SR_TSOVF_Pos             (4U)

+#define RTC_SR_TSOVF_Msk             (0x1UL << RTC_SR_TSOVF_Pos)                /*!< 0x00000010 */

+#define RTC_SR_TSOVF                 RTC_SR_TSOVF_Msk

+#define RTC_SR_TSF_Pos               (3U)

+#define RTC_SR_TSF_Msk               (0x1UL << RTC_SR_TSF_Pos)                  /*!< 0x00000008 */

+#define RTC_SR_TSF                   RTC_SR_TSF_Msk

+#define RTC_SR_WUTF_Pos              (2U)

+#define RTC_SR_WUTF_Msk              (0x1UL << RTC_SR_WUTF_Pos)                 /*!< 0x00000004 */

+#define RTC_SR_WUTF                  RTC_SR_WUTF_Msk

+#define RTC_SR_ALRBF_Pos             (1U)

+#define RTC_SR_ALRBF_Msk             (0x1UL << RTC_SR_ALRBF_Pos)                /*!< 0x00000002 */

+#define RTC_SR_ALRBF                 RTC_SR_ALRBF_Msk

+#define RTC_SR_ALRAF_Pos             (0U)

+#define RTC_SR_ALRAF_Msk             (0x1UL << RTC_SR_ALRAF_Pos)                /*!< 0x00000001 */

+#define RTC_SR_ALRAF                 RTC_SR_ALRAF_Msk

+

+/********************  Bits definition for RTC_MISR register  *****************/

+#define RTC_MISR_ITSMF_Pos           (5U)

+#define RTC_MISR_ITSMF_Msk           (0x1UL << RTC_MISR_ITSMF_Pos)              /*!< 0x00000020 */

+#define RTC_MISR_ITSMF               RTC_MISR_ITSMF_Msk

+#define RTC_MISR_TSOVMF_Pos          (4U)

+#define RTC_MISR_TSOVMF_Msk          (0x1UL << RTC_MISR_TSOVMF_Pos)             /*!< 0x00000010 */

+#define RTC_MISR_TSOVMF              RTC_MISR_TSOVMF_Msk

+#define RTC_MISR_TSMF_Pos            (3U)

+#define RTC_MISR_TSMF_Msk            (0x1UL << RTC_MISR_TSMF_Pos)               /*!< 0x00000008 */

+#define RTC_MISR_TSMF                RTC_MISR_TSMF_Msk

+#define RTC_MISR_WUTMF_Pos           (2U)

+#define RTC_MISR_WUTMF_Msk           (0x1UL << RTC_MISR_WUTMF_Pos)              /*!< 0x00000004 */

+#define RTC_MISR_WUTMF               RTC_MISR_WUTMF_Msk

+#define RTC_MISR_ALRBMF_Pos          (1U)

+#define RTC_MISR_ALRBMF_Msk          (0x1UL << RTC_MISR_ALRBMF_Pos)             /*!< 0x00000002 */

+#define RTC_MISR_ALRBMF              RTC_MISR_ALRBMF_Msk

+#define RTC_MISR_ALRAMF_Pos          (0U)

+#define RTC_MISR_ALRAMF_Msk          (0x1UL << RTC_MISR_ALRAMF_Pos)             /*!< 0x00000001 */

+#define RTC_MISR_ALRAMF              RTC_MISR_ALRAMF_Msk

+

+/********************  Bits definition for RTC_SCR register  ******************/

+#define RTC_SCR_CITSF_Pos            (5U)

+#define RTC_SCR_CITSF_Msk            (0x1UL << RTC_SCR_CITSF_Pos)               /*!< 0x00000020 */

+#define RTC_SCR_CITSF                RTC_SCR_CITSF_Msk

+#define RTC_SCR_CTSOVF_Pos           (4U)

+#define RTC_SCR_CTSOVF_Msk           (0x1UL << RTC_SCR_CTSOVF_Pos)              /*!< 0x00000010 */

+#define RTC_SCR_CTSOVF               RTC_SCR_CTSOVF_Msk

+#define RTC_SCR_CTSF_Pos             (3U)

+#define RTC_SCR_CTSF_Msk             (0x1UL << RTC_SCR_CTSF_Pos)                /*!< 0x00000008 */

+#define RTC_SCR_CTSF                 RTC_SCR_CTSF_Msk

+#define RTC_SCR_CWUTF_Pos            (2U)

+#define RTC_SCR_CWUTF_Msk            (0x1UL << RTC_SCR_CWUTF_Pos)               /*!< 0x00000004 */

+#define RTC_SCR_CWUTF                RTC_SCR_CWUTF_Msk

+#define RTC_SCR_CALRBF_Pos           (1U)

+#define RTC_SCR_CALRBF_Msk           (0x1UL << RTC_SCR_CALRBF_Pos)              /*!< 0x00000002 */

+#define RTC_SCR_CALRBF               RTC_SCR_CALRBF_Msk

+#define RTC_SCR_CALRAF_Pos           (0U)

+#define RTC_SCR_CALRAF_Msk           (0x1UL << RTC_SCR_CALRAF_Pos)              /*!< 0x00000001 */

+#define RTC_SCR_CALRAF               RTC_SCR_CALRAF_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                     Tamper and backup register (TAMP)                      */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for TAMP_CR1 register  *****************/

+#define TAMP_CR1_TAMP1E_Pos          (0U)

+#define TAMP_CR1_TAMP1E_Msk          (0x1UL << TAMP_CR1_TAMP1E_Pos)            /*!< 0x00000001 */

+#define TAMP_CR1_TAMP1E              TAMP_CR1_TAMP1E_Msk

+#define TAMP_CR1_TAMP2E_Pos          (1U)

+#define TAMP_CR1_TAMP2E_Msk          (0x1UL << TAMP_CR1_TAMP2E_Pos)            /*!< 0x00000002 */

+#define TAMP_CR1_TAMP2E              TAMP_CR1_TAMP2E_Msk

+#define TAMP_CR1_TAMP3E_Pos          (2U)

+#define TAMP_CR1_TAMP3E_Msk          (0x1UL << TAMP_CR1_TAMP3E_Pos)            /*!< 0x00000004 */

+#define TAMP_CR1_TAMP3E              TAMP_CR1_TAMP3E_Msk

+#define TAMP_CR1_ITAMP1E_Pos         (16U)

+#define TAMP_CR1_ITAMP1E_Msk         (0x1UL << TAMP_CR1_ITAMP1E_Pos)           /*!< 0x00010000 */

+#define TAMP_CR1_ITAMP1E             TAMP_CR1_ITAMP1E_Msk

+#define TAMP_CR1_ITAMP2E_Pos         (17U)

+#define TAMP_CR1_ITAMP2E_Msk         (0x1UL << TAMP_CR1_ITAMP2E_Pos)           /*!< 0x00020000 */

+#define TAMP_CR1_ITAMP2E             TAMP_CR1_ITAMP2E_Msk

+#define TAMP_CR1_ITAMP3E_Pos         (18U)

+#define TAMP_CR1_ITAMP3E_Msk         (0x1UL << TAMP_CR1_ITAMP3E_Pos)           /*!< 0x00040000 */

+#define TAMP_CR1_ITAMP3E             TAMP_CR1_ITAMP3E_Msk

+#define TAMP_CR1_ITAMP4E_Pos         (19U)

+#define TAMP_CR1_ITAMP4E_Msk         (0x1UL << TAMP_CR1_ITAMP4E_Pos)           /*!< 0x00080000 */

+#define TAMP_CR1_ITAMP4E             TAMP_CR1_ITAMP4E_Msk

+#define TAMP_CR1_ITAMP5E_Pos         (20U)

+#define TAMP_CR1_ITAMP5E_Msk         (0x1UL << TAMP_CR1_ITAMP5E_Pos)           /*!< 0x00100000 */

+#define TAMP_CR1_ITAMP5E             TAMP_CR1_ITAMP5E_Msk

+#define TAMP_CR1_ITAMP6E_Pos         (21U)

+#define TAMP_CR1_ITAMP6E_Msk         (0x1UL << TAMP_CR1_ITAMP6E_Pos)           /*!< 0x00200000 */

+#define TAMP_CR1_ITAMP6E             TAMP_CR1_ITAMP6E_Msk

+#define TAMP_CR1_ITAMP8E_Pos         (23U)

+#define TAMP_CR1_ITAMP8E_Msk         (0x1UL << TAMP_CR1_ITAMP8E_Pos)           /*!< 0x00800000 */

+#define TAMP_CR1_ITAMP8E             TAMP_CR1_ITAMP8E_Msk

+

+/********************  Bits definition for TAMP_CR2 register  *****************/

+#define TAMP_CR2_TAMP1NOERASE_Pos    (0U)

+#define TAMP_CR2_TAMP1NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)      /*!< 0x00000001 */

+#define TAMP_CR2_TAMP1NOERASE        TAMP_CR2_TAMP1NOERASE_Msk

+#define TAMP_CR2_TAMP2NOERASE_Pos    (1U)

+#define TAMP_CR2_TAMP2NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)      /*!< 0x00000002 */

+#define TAMP_CR2_TAMP2NOERASE        TAMP_CR2_TAMP2NOERASE_Msk

+#define TAMP_CR2_TAMP3NOERASE_Pos    (2U)

+#define TAMP_CR2_TAMP3NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos)      /*!< 0x00000004 */

+#define TAMP_CR2_TAMP3NOERASE        TAMP_CR2_TAMP3NOERASE_Msk

+#define TAMP_CR2_TAMP1MSK_Pos        (16U)

+#define TAMP_CR2_TAMP1MSK_Msk        (0x1UL << TAMP_CR2_TAMP1MSK_Pos)          /*!< 0x00010000 */

+#define TAMP_CR2_TAMP1MSK            TAMP_CR2_TAMP1MSK_Msk

+#define TAMP_CR2_TAMP2MSK_Pos        (17U)

+#define TAMP_CR2_TAMP2MSK_Msk        (0x1UL << TAMP_CR2_TAMP2MSK_Pos)          /*!< 0x00020000 */

+#define TAMP_CR2_TAMP2MSK            TAMP_CR2_TAMP2MSK_Msk

+#define TAMP_CR2_TAMP3MSK_Pos        (18U)

+#define TAMP_CR2_TAMP3MSK_Msk        (0x1UL << TAMP_CR2_TAMP3MSK_Pos)          /*!< 0x00040000 */

+#define TAMP_CR2_TAMP3MSK            TAMP_CR2_TAMP3MSK_Msk

+#define TAMP_CR2_TAMP1TRG_Pos        (24U)

+#define TAMP_CR2_TAMP1TRG_Msk        (0x1UL << TAMP_CR2_TAMP1TRG_Pos)          /*!< 0x01000000 */

+#define TAMP_CR2_TAMP1TRG            TAMP_CR2_TAMP1TRG_Msk

+#define TAMP_CR2_TAMP2TRG_Pos        (25U)

+#define TAMP_CR2_TAMP2TRG_Msk        (0x1UL << TAMP_CR2_TAMP2TRG_Pos)          /*!< 0x02000000 */

+#define TAMP_CR2_TAMP2TRG            TAMP_CR2_TAMP2TRG_Msk

+#define TAMP_CR2_TAMP3TRG_Pos        (26U)

+#define TAMP_CR2_TAMP3TRG_Msk        (0x1UL << TAMP_CR2_TAMP3TRG_Pos)          /*!< 0x04000000 */

+#define TAMP_CR2_TAMP3TRG            TAMP_CR2_TAMP3TRG_Msk

+

+/********************  Bits definition for TAMP_FLTCR register  ***************/

+#define TAMP_FLTCR_TAMPFREQ_Pos      (0U)

+#define TAMP_FLTCR_TAMPFREQ_Msk      (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000007 */

+#define TAMP_FLTCR_TAMPFREQ          TAMP_FLTCR_TAMPFREQ_Msk

+#define TAMP_FLTCR_TAMPFREQ_0        (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000001 */

+#define TAMP_FLTCR_TAMPFREQ_1        (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000002 */

+#define TAMP_FLTCR_TAMPFREQ_2        (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000004 */

+#define TAMP_FLTCR_TAMPFLT_Pos       (3U)

+#define TAMP_FLTCR_TAMPFLT_Msk       (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000018 */

+#define TAMP_FLTCR_TAMPFLT           TAMP_FLTCR_TAMPFLT_Msk

+#define TAMP_FLTCR_TAMPFLT_0         (0x1UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000008 */

+#define TAMP_FLTCR_TAMPFLT_1         (0x2UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000010 */

+#define TAMP_FLTCR_TAMPPRCH_Pos      (5U)

+#define TAMP_FLTCR_TAMPPRCH_Msk      (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000060 */

+#define TAMP_FLTCR_TAMPPRCH          TAMP_FLTCR_TAMPPRCH_Msk

+#define TAMP_FLTCR_TAMPPRCH_0        (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000020 */

+#define TAMP_FLTCR_TAMPPRCH_1        (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000040 */

+#define TAMP_FLTCR_TAMPPUDIS_Pos     (7U)

+#define TAMP_FLTCR_TAMPPUDIS_Msk     (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)        /*!< 0x00000080 */

+#define TAMP_FLTCR_TAMPPUDIS         TAMP_FLTCR_TAMPPUDIS_Msk

+

+/*******************  Bits definition for TAMP_ATCR1 register  ****************/

+#define TAMP_ATCR1_TAMP1AM_Pos       (0U)

+#define TAMP_ATCR1_TAMP1AM_Msk       (0x1UL << TAMP_ATCR1_TAMP1AM_Pos)         /*!< 0x00000001 */

+#define TAMP_ATCR1_TAMP1AM           TAMP_ATCR1_TAMP1AM_Msk

+#define TAMP_ATCR1_TAMP2AM_Pos       (1U)

+#define TAMP_ATCR1_TAMP2AM_Msk       (0x1UL << TAMP_ATCR1_TAMP2AM_Pos)         /*!< 0x00000002 */

+#define TAMP_ATCR1_TAMP2AM           TAMP_ATCR1_TAMP2AM_Msk

+#define TAMP_ATCR1_TAMP3AM_Pos       (2U)

+#define TAMP_ATCR1_TAMP3AM_Msk       (0x1UL << TAMP_ATCR1_TAMP3AM_Pos)         /*!< 0x00000004 */

+#define TAMP_ATCR1_TAMP3AM           TAMP_ATCR1_TAMP3AM_Msk

+#define TAMP_ATCR1_ATOSEL1_Pos       (8U)

+#define TAMP_ATCR1_ATOSEL1_Msk       (0x3UL << TAMP_ATCR1_ATOSEL1_Pos)          /*!< 0x00000300 */

+#define TAMP_ATCR1_ATOSEL1            TAMP_ATCR1_ATOSEL1_Msk

+#define TAMP_ATCR1_ATOSEL1_0         (0x1UL << TAMP_ATCR1_ATOSEL1_Pos)         /*!< 0x00000100 */

+#define TAMP_ATCR1_ATOSEL1_1         (0x2UL << TAMP_ATCR1_ATOSEL1_Pos)         /*!< 0x00000200 */

+#define TAMP_ATCR1_ATOSEL2_Pos       (10U)

+#define TAMP_ATCR1_ATOSEL2_Msk       (0x3UL << TAMP_ATCR1_ATOSEL2_Pos)          /*!< 0x00000C00 */

+#define TAMP_ATCR1_ATOSEL2            TAMP_ATCR1_ATOSEL2_Msk

+#define TAMP_ATCR1_ATOSEL2_0         (0x1UL << TAMP_ATCR1_ATOSEL2_Pos)         /*!< 0x00000400 */

+#define TAMP_ATCR1_ATOSEL2_1         (0x2UL << TAMP_ATCR1_ATOSEL2_Pos)         /*!< 0x00000800 */

+#define TAMP_ATCR1_ATOSEL3_Pos       (12U)

+#define TAMP_ATCR1_ATOSEL3_Msk       (0x3UL << TAMP_ATCR1_ATOSEL3_Pos)          /*!< 0x00003000 */

+#define TAMP_ATCR1_ATOSEL3            TAMP_ATCR1_ATOSEL3_Msk

+#define TAMP_ATCR1_ATOSEL3_0         (0x1UL << TAMP_ATCR1_ATOSEL3_Pos)         /*!< 0x00001000 */

+#define TAMP_ATCR1_ATOSEL3_1         (0x2UL << TAMP_ATCR1_ATOSEL3_Pos)         /*!< 0x00002000 */

+#define TAMP_ATCR1_ATOSEL4_Pos       (14U)

+#define TAMP_ATCR1_ATOSEL4_Msk       (0x3UL << TAMP_ATCR1_ATOSEL4_Pos)          /*!< 0x0000C000 */

+#define TAMP_ATCR1_ATOSEL4            TAMP_ATCR1_ATOSEL4_Msk

+#define TAMP_ATCR1_ATOSEL4_0         (0x1UL << TAMP_ATCR1_ATOSEL4_Pos)         /*!< 0x00004000 */

+#define TAMP_ATCR1_ATOSEL4_1         (0x2UL << TAMP_ATCR1_ATOSEL4_Pos)         /*!< 0x00008000 */

+#define TAMP_ATCR1_ATCKSEL_Pos       (16U)

+#define TAMP_ATCR1_ATCKSEL_Msk       (0x7UL << TAMP_ATCR1_ATCKSEL_Pos)          /*!< 0x00070000 */

+#define TAMP_ATCR1_ATCKSEL            TAMP_ATCR1_ATCKSEL_Msk

+#define TAMP_ATCR1_ATCKSEL_0         (0x1UL << TAMP_ATCR1_ATCKSEL_Pos)         /*!< 0x00010000 */

+#define TAMP_ATCR1_ATCKSEL_1         (0x2UL << TAMP_ATCR1_ATCKSEL_Pos)         /*!< 0x00020000 */

+#define TAMP_ATCR1_ATCKSEL_2         (0x4UL << TAMP_ATCR1_ATCKSEL_Pos)         /*!< 0x00040000 */

+#define TAMP_ATCR1_ATPER_Pos         (24U)

+#define TAMP_ATCR1_ATPER_Msk         (0x7UL << TAMP_ATCR1_ATPER_Pos)           /*!< 0x07000000 */

+#define TAMP_ATCR1_ATPER             TAMP_ATCR1_ATPER_Msk

+#define TAMP_ATCR1_ATOSHARE_Pos      (30U)

+#define TAMP_ATCR1_ATOSHARE_Msk      (0x1UL << TAMP_ATCR1_ATOSHARE_Pos)        /*!< 0x40000000 */

+#define TAMP_ATCR1_ATOSHARE          TAMP_ATCR1_ATOSHARE_Msk

+#define TAMP_ATCR1_FLTEN_Pos         (31U)

+#define TAMP_ATCR1_FLTEN_Msk         (0x1UL << TAMP_ATCR1_FLTEN_Pos)           /*!< 0x80000000 */

+#define TAMP_ATCR1_FLTEN             TAMP_ATCR1_FLTEN_Msk

+

+/********************  Bits definition for TAMP_ATSEEDR register  *************/

+#define TAMP_ATSEEDR_SEED_Pos        (0U)

+#define TAMP_ATSEEDR_SEED_Msk        (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos)   /*!< 0xFFFFFFFF */

+#define TAMP_ATSEEDR_SEED            TAMP_ATSEEDR_SEED_Msk

+

+/********************  Bits definition for TAMP_ATOR register  ****************/

+#define TAMP_ATOR_PRNG_Pos           (0U)

+#define TAMP_ATOR_PRNG_Msk           (0x000000FFUL << TAMP_ATOR_PRNG_Pos)      /*!< 0x000000FF */

+#define TAMP_ATOR_PRNG               TAMP_ATOR_PRNG_Msk

+#define TAMP_ATOR_SEEDF_Pos          (14U)

+#define TAMP_ATOR_SEEDF_Msk          (0x01UL << TAMP_ATOR_SEEDF_Pos)           /*!< 0x00004000 */

+#define TAMP_ATOR_SEEDF              TAMP_ATOR_SEEDF_Msk

+#define TAMP_ATOR_INITS_Pos          (15U)

+#define TAMP_ATOR_INITS_Msk          (0x01UL << TAMP_ATOR_INITS_Pos)           /*!< 0x00008000 */

+#define TAMP_ATOR_INITS              TAMP_ATOR_INITS_Msk

+

+/********************  Bits definition for TAMP_IER register  *****************/

+#define TAMP_IER_TAMP1IE_Pos         (0U)

+#define TAMP_IER_TAMP1IE_Msk         (0x1UL << TAMP_IER_TAMP1IE_Pos)           /*!< 0x00000001 */

+#define TAMP_IER_TAMP1IE             TAMP_IER_TAMP1IE_Msk

+#define TAMP_IER_TAMP2IE_Pos         (1U)

+#define TAMP_IER_TAMP2IE_Msk         (0x1UL << TAMP_IER_TAMP2IE_Pos)           /*!< 0x00000002 */

+#define TAMP_IER_TAMP2IE             TAMP_IER_TAMP2IE_Msk

+#define TAMP_IER_TAMP3IE_Pos         (2U)

+#define TAMP_IER_TAMP3IE_Msk         (0x1UL << TAMP_IER_TAMP3IE_Pos)           /*!< 0x00000004 */

+#define TAMP_IER_TAMP3IE             TAMP_IER_TAMP3IE_Msk

+#define TAMP_IER_ITAMP1IE_Pos        (16U)

+#define TAMP_IER_ITAMP1IE_Msk        (0x1UL << TAMP_IER_ITAMP1IE_Pos)          /*!< 0x00010000 */

+#define TAMP_IER_ITAMP1IE            TAMP_IER_ITAMP1IE_Msk

+#define TAMP_IER_ITAMP2IE_Pos        (17U)

+#define TAMP_IER_ITAMP2IE_Msk        (0x1UL << TAMP_IER_ITAMP2IE_Pos)          /*!< 0x00020000 */

+#define TAMP_IER_ITAMP2IE            TAMP_IER_ITAMP2IE_Msk

+#define TAMP_IER_ITAMP3IE_Pos        (18U)

+#define TAMP_IER_ITAMP3IE_Msk        (0x1UL << TAMP_IER_ITAMP3IE_Pos)          /*!< 0x00040000 */

+#define TAMP_IER_ITAMP3IE            TAMP_IER_ITAMP3IE_Msk

+#define TAMP_IER_ITAMP4IE_Pos        (19U)

+#define TAMP_IER_ITAMP4IE_Msk        (0x1UL << TAMP_IER_ITAMP4IE_Pos)          /*!< 0x00080000 */

+#define TAMP_IER_ITAMP4IE            TAMP_IER_ITAMP4IE_Msk

+#define TAMP_IER_ITAMP5IE_Pos        (20U)

+#define TAMP_IER_ITAMP5IE_Msk        (0x1UL << TAMP_IER_ITAMP5IE_Pos)          /*!< 0x00100000 */

+#define TAMP_IER_ITAMP5IE            TAMP_IER_ITAMP5IE_Msk

+#define TAMP_IER_ITAMP6IE_Pos        (21U)

+#define TAMP_IER_ITAMP6IE_Msk        (0x1UL << TAMP_IER_ITAMP6IE_Pos)          /*!< 0x00200000 */

+#define TAMP_IER_ITAMP6IE            TAMP_IER_ITAMP6IE_Msk

+#define TAMP_IER_ITAMP8IE_Pos        (23U)

+#define TAMP_IER_ITAMP8IE_Msk        (0x1UL << TAMP_IER_ITAMP8IE_Pos)          /*!< 0x00800000 */

+#define TAMP_IER_ITAMP8IE            TAMP_IER_ITAMP8IE_Msk

+

+/********************  Bits definition for TAMP_SR register  *****************/

+#define TAMP_SR_TAMP1F_Pos           (0U)

+#define TAMP_SR_TAMP1F_Msk           (0x1UL << TAMP_SR_TAMP1F_Pos)             /*!< 0x00000001 */

+#define TAMP_SR_TAMP1F               TAMP_SR_TAMP1F_Msk

+#define TAMP_SR_TAMP2F_Pos           (1U)

+#define TAMP_SR_TAMP2F_Msk           (0x1UL << TAMP_SR_TAMP2F_Pos)             /*!< 0x00000002 */

+#define TAMP_SR_TAMP2F               TAMP_SR_TAMP2F_Msk

+#define TAMP_SR_TAMP3F_Pos           (2U)

+#define TAMP_SR_TAMP3F_Msk           (0x1UL << TAMP_SR_TAMP3F_Pos)             /*!< 0x00000004 */

+#define TAMP_SR_TAMP3F               TAMP_SR_TAMP3F_Msk

+#define TAMP_SR_ITAMP1F_Pos          (16U)

+#define TAMP_SR_ITAMP1F_Msk          (0x1UL << TAMP_SR_ITAMP1F_Pos)            /*!< 0x00010000 */

+#define TAMP_SR_ITAMP1F              TAMP_SR_ITAMP1F_Msk

+#define TAMP_SR_ITAMP2F_Pos          (17U)

+#define TAMP_SR_ITAMP2F_Msk          (0x1UL << TAMP_SR_ITAMP2F_Pos)            /*!< 0x00020000 */

+#define TAMP_SR_ITAMP2F              TAMP_SR_ITAMP2F_Msk

+#define TAMP_SR_ITAMP3F_Pos          (18U)

+#define TAMP_SR_ITAMP3F_Msk          (0x1UL << TAMP_SR_ITAMP3F_Pos)            /*!< 0x00040000 */

+#define TAMP_SR_ITAMP3F              TAMP_SR_ITAMP3F_Msk

+#define TAMP_SR_ITAMP4F_Pos          (19U)

+#define TAMP_SR_ITAMP4F_Msk          (0x1UL << TAMP_SR_ITAMP4F_Pos)            /*!< 0x00080000 */

+#define TAMP_SR_ITAMP4F              TAMP_SR_ITAMP4F_Msk

+#define TAMP_SR_ITAMP5F_Pos          (20U)

+#define TAMP_SR_ITAMP5F_Msk          (0x1UL << TAMP_SR_ITAMP5F_Pos)            /*!< 0x00100000 */

+#define TAMP_SR_ITAMP5F              TAMP_SR_ITAMP5F_Msk

+#define TAMP_SR_ITAMP6F_Pos          (21U)

+#define TAMP_SR_ITAMP6F_Msk          (0x1UL << TAMP_SR_ITAMP6F_Pos)            /*!< 0x00200000 */

+#define TAMP_SR_ITAMP6F              TAMP_SR_ITAMP6F_Msk

+#define TAMP_SR_ITAMP8F_Pos          (23U)

+#define TAMP_SR_ITAMP8F_Msk          (0x1UL << TAMP_SR_ITAMP8F_Pos)            /*!< 0x00800000 */

+#define TAMP_SR_ITAMP8F              TAMP_SR_ITAMP8F_Msk

+

+/********************  Bits definition for TAMP_MISR register  ************ *****/

+#define TAMP_MISR_TAMP1MF_Pos        (0U)

+#define TAMP_MISR_TAMP1MF_Msk        (0x1UL << TAMP_MISR_TAMP1MF_Pos)           /*!< 0x00000001 */

+#define TAMP_MISR_TAMP1MF            TAMP_MISR_TAMP1MF_Msk

+#define TAMP_MISR_TAMP2MF_Pos        (1U)

+#define TAMP_MISR_TAMP2MF_Msk        (0x1UL << TAMP_MISR_TAMP2MF_Pos)           /*!< 0x00000002 */

+#define TAMP_MISR_TAMP2MF            TAMP_MISR_TAMP2MF_Msk

+#define TAMP_MISR_TAMP3MF_Pos        (2U)

+#define TAMP_MISR_TAMP3MF_Msk        (0x1UL << TAMP_MISR_TAMP3MF_Pos)          /*!< 0x00000004 */

+#define TAMP_MISR_TAMP3MF            TAMP_MISR_TAMP3MF_Msk

+#define TAMP_MISR_ITAMP1MF_Pos       (16U)

+#define TAMP_MISR_ITAMP1MF_Msk       (0x1UL << TAMP_MISR_ITAMP1MF_Pos)         /*!< 0x00010000 */

+#define TAMP_MISR_ITAMP1MF           TAMP_MISR_ITAMP1MF_Msk

+#define TAMP_MISR_ITAMP2MF_Pos       (17U)

+#define TAMP_MISR_ITAMP2MF_Msk       (0x1UL << TAMP_MISR_ITAMP2MF_Pos)         /*!< 0x00020000 */

+#define TAMP_MISR_ITAMP2MF           TAMP_MISR_ITAMP2MF_Msk

+#define TAMP_MISR_ITAMP3MF_Pos       (18U)

+#define TAMP_MISR_ITAMP3MF_Msk       (0x1UL << TAMP_MISR_ITAMP3MF_Pos)         /*!< 0x00040000 */

+#define TAMP_MISR_ITAMP3MF           TAMP_MISR_ITAMP3MF_Msk

+#define TAMP_MISR_ITAMP4MF_Pos       (19U)

+#define TAMP_MISR_ITAMP4MF_Msk       (0x1UL << TAMP_MISR_ITAMP4MF_Pos)         /*!< 0x00080000 */

+#define TAMP_MISR_ITAMP4MF           TAMP_MISR_ITAMP4MF_Msk

+#define TAMP_MISR_ITAMP5MF_Pos       (20U)

+#define TAMP_MISR_ITAMP5MF_Msk       (0x1UL << TAMP_MISR_ITAMP5MF_Pos)         /*!< 0x00100000 */

+#define TAMP_MISR_ITAMP5MF           TAMP_MISR_ITAMP5MF_Msk

+#define TAMP_MISR_ITAMP6MF_Pos       (21U)

+#define TAMP_MISR_ITAMP6MF_Msk       (0x1UL << TAMP_MISR_ITAMP6MF_Pos)         /*!< 0x00200000 */

+#define TAMP_MISR_ITAMP6MF           TAMP_MISR_ITAMP6MF_Msk

+#define TAMP_MISR_ITAMP8MF_Pos       (23U)

+#define TAMP_MISR_ITAMP8MF_Msk       (0x1UL << TAMP_MISR_ITAMP8MF_Pos)         /*!< 0x00800000 */

+#define TAMP_MISR_ITAMP8MF           TAMP_MISR_ITAMP8MF_Msk

+

+/********************  Bits definition for TAMP_SCR register  *****************/

+#define TAMP_SCR_CTAMP1F_Pos         (0U)

+#define TAMP_SCR_CTAMP1F_Msk         (0x1UL << TAMP_SCR_CTAMP1F_Pos)            /*!< 0x00000001 */

+#define TAMP_SCR_CTAMP1F             TAMP_SCR_CTAMP1F_Msk

+#define TAMP_SCR_CTAMP2F_Pos         (1U)

+#define TAMP_SCR_CTAMP2F_Msk         (0x1UL << TAMP_SCR_CTAMP2F_Pos)            /*!< 0x00000002 */

+#define TAMP_SCR_CTAMP2F             TAMP_SCR_CTAMP2F_Msk

+#define TAMP_SCR_CTAMP3F_Pos         (2U)

+#define TAMP_SCR_CTAMP3F_Msk         (0x1UL << TAMP_SCR_CTAMP3F_Pos)           /*!< 0x00000004 */

+#define TAMP_SCR_CTAMP3F             TAMP_SCR_CTAMP3F_Msk

+#define TAMP_SCR_CITAMP1F_Pos        (16U)

+#define TAMP_SCR_CITAMP1F_Msk        (0x1UL << TAMP_SCR_CITAMP1F_Pos)          /*!< 0x00010000 */

+#define TAMP_SCR_CITAMP1F            TAMP_SCR_CITAMP1F_Msk

+#define TAMP_SCR_CITAMP2F_Pos        (17U)

+#define TAMP_SCR_CITAMP2F_Msk        (0x1UL << TAMP_SCR_CITAMP2F_Pos)          /*!< 0x00020000 */

+#define TAMP_SCR_CITAMP2F            TAMP_SCR_CITAMP2F_Msk

+#define TAMP_SCR_CITAMP3F_Pos        (18U)

+#define TAMP_SCR_CITAMP3F_Msk        (0x1UL << TAMP_SCR_CITAMP3F_Pos)          /*!< 0x00040000 */

+#define TAMP_SCR_CITAMP3F            TAMP_SCR_CITAMP3F_Msk

+#define TAMP_SCR_CITAMP4F_Pos        (19U)

+#define TAMP_SCR_CITAMP4F_Msk        (0x1UL << TAMP_SCR_CITAMP4F_Pos)          /*!< 0x00080000 */

+#define TAMP_SCR_CITAMP4F            TAMP_SCR_CITAMP4F_Msk

+#define TAMP_SCR_CITAMP5F_Pos        (20U)

+#define TAMP_SCR_CITAMP5F_Msk        (0x1UL << TAMP_SCR_CITAMP5F_Pos)          /*!< 0x00100000 */

+#define TAMP_SCR_CITAMP5F            TAMP_SCR_CITAMP5F_Msk

+#define TAMP_SCR_CITAMP6F_Pos        (21U)

+#define TAMP_SCR_CITAMP6F_Msk        (0x1UL << TAMP_SCR_CITAMP6F_Pos)          /*!< 0x00200000 */

+#define TAMP_SCR_CITAMP6F            TAMP_SCR_CITAMP6F_Msk

+#define TAMP_SCR_CITAMP8F_Pos        (23U)

+#define TAMP_SCR_CITAMP8F_Msk        (0x1UL << TAMP_SCR_CITAMP8F_Pos)          /*!< 0x00800000 */

+#define TAMP_SCR_CITAMP8F            TAMP_SCR_CITAMP8F_Msk

+

+/********************  Bits definition for TAMP_COUNTR register  **************/

+#define TAMP_COUNTR_Pos              (16U)

+#define TAMP_COUNTR_Msk              (0xFFFFUL << TAMP_COUNTR_Pos)             /*!< 0xFFFF0000 */

+#define TAMP_COUNTR                  TAMP_COUNTR_Msk

+

+/********************  Bits definition for TAMP_OR register  ******************/

+#define TAMP_OR_OUT3_RMP_Pos         (0U)

+#define TAMP_OR_OUT3_RMP_Msk         (0x1UL << TAMP_OR_OUT3_RMP_Pos)           /*!< 0x00000001 */

+#define TAMP_OR_OUT3_RMP             TAMP_OR_OUT3_RMP_Msk

+

+/********************  Bits definition for TAMP_BKP0R register  ***************/

+#define TAMP_BKP0R_Pos               (0U)

+#define TAMP_BKP0R_Msk               (0xFFFFFFFFUL << TAMP_BKP0R_Pos)           /*!< 0xFFFFFFFF */

+#define TAMP_BKP0R                   TAMP_BKP0R_Msk

+

+/********************  Bits definition for TAMP_BKP1R register  ****************/

+#define TAMP_BKP1R_Pos               (0U)

+#define TAMP_BKP1R_Msk               (0xFFFFFFFFUL << TAMP_BKP1R_Pos)           /*!< 0xFFFFFFFF */

+#define TAMP_BKP1R                   TAMP_BKP1R_Msk

+

+/********************  Bits definition for TAMP_BKP2R register  ****************/

+#define TAMP_BKP2R_Pos               (0U)

+#define TAMP_BKP2R_Msk               (0xFFFFFFFFUL << TAMP_BKP2R_Pos)           /*!< 0xFFFFFFFF */

+#define TAMP_BKP2R                   TAMP_BKP2R_Msk

+

+/********************  Bits definition for TAMP_BKP3R register  ****************/

+#define TAMP_BKP3R_Pos               (0U)

+#define TAMP_BKP3R_Msk               (0xFFFFFFFFUL << TAMP_BKP3R_Pos)           /*!< 0xFFFFFFFF */

+#define TAMP_BKP3R                   TAMP_BKP3R_Msk

+

+/********************  Bits definition for TAMP_BKP4R register  ****************/

+#define TAMP_BKP4R_Pos               (0U)

+#define TAMP_BKP4R_Msk               (0xFFFFFFFFUL << TAMP_BKP4R_Pos)           /*!< 0xFFFFFFFF */

+#define TAMP_BKP4R                   TAMP_BKP4R_Msk

+

+/********************  Bits definition for TAMP_BKP5R register  ****************/

+#define TAMP_BKP5R_Pos               (0U)

+#define TAMP_BKP5R_Msk               (0xFFFFFFFFUL << TAMP_BKP5R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP5R                   TAMP_BKP5R_Msk

+

+/********************  Bits definition for TAMP_BKP6R register  ****************/

+#define TAMP_BKP6R_Pos               (0U)

+#define TAMP_BKP6R_Msk               (0xFFFFFFFFUL << TAMP_BKP6R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP6R                   TAMP_BKP6R_Msk

+

+/********************  Bits definition for TAMP_BKP7R register  ****************/

+#define TAMP_BKP7R_Pos               (0U)

+#define TAMP_BKP7R_Msk               (0xFFFFFFFFUL << TAMP_BKP7R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP7R                   TAMP_BKP7R_Msk

+

+/********************  Bits definition for TAMP_BKP8R register  ****************/

+#define TAMP_BKP8R_Pos               (0U)

+#define TAMP_BKP8R_Msk               (0xFFFFFFFFUL << TAMP_BKP8R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP8R                   TAMP_BKP8R_Msk

+

+/********************  Bits definition for TAMP_BKP9R register  ****************/

+#define TAMP_BKP9R_Pos               (0U)

+#define TAMP_BKP9R_Msk               (0xFFFFFFFFUL << TAMP_BKP9R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP9R                   TAMP_BKP9R_Msk

+

+/********************  Bits definition for TAMP_BKP10R register  ***************/

+#define TAMP_BKP10R_Pos              (0U)

+#define TAMP_BKP10R_Msk              (0xFFFFFFFFUL << TAMP_BKP10R_Pos)         /*!< 0xFFFFFFFF */

+#define TAMP_BKP10R                  TAMP_BKP10R_Msk

+

+/********************  Bits definition for TAMP_BKP11R register  ***************/

+#define TAMP_BKP11R_Pos              (0U)

+#define TAMP_BKP11R_Msk              (0xFFFFFFFFUL << TAMP_BKP11R_Pos)         /*!< 0xFFFFFFFF */

+#define TAMP_BKP11R                  TAMP_BKP11R_Msk

+

+/********************  Bits definition for TAMP_BKP12R register  ***************/

+#define TAMP_BKP12R_Pos              (0U)

+#define TAMP_BKP12R_Msk              (0xFFFFFFFFUL << TAMP_BKP12R_Pos)         /*!< 0xFFFFFFFF */

+#define TAMP_BKP12R                  TAMP_BKP12R_Msk

+

+/********************  Bits definition for TAMP_BKP13R register  ***************/

+#define TAMP_BKP13R_Pos              (0U)

+#define TAMP_BKP13R_Msk              (0xFFFFFFFFUL << TAMP_BKP13R_Pos)         /*!< 0xFFFFFFFF */

+#define TAMP_BKP13R                  TAMP_BKP13R_Msk

+

+/********************  Bits definition for TAMP_BKP14R register  ***************/

+#define TAMP_BKP14R_Pos              (0U)

+#define TAMP_BKP14R_Msk              (0xFFFFFFFFUL << TAMP_BKP14R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP14R                  TAMP_BKP14R_Msk

+

+/********************  Bits definition for TAMP_BKP15R register  ***************/

+#define TAMP_BKP15R_Pos              (0U)

+#define TAMP_BKP15R_Msk              (0xFFFFFFFFUL << TAMP_BKP15R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP15R                  TAMP_BKP15R_Msk

+

+/********************  Bits definition for TAMP_BKP16R register  ***************/

+#define TAMP_BKP16R_Pos              (0U)

+#define TAMP_BKP16R_Msk              (0xFFFFFFFFUL << TAMP_BKP16R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP16R                  TAMP_BKP16R_Msk

+

+/********************  Bits definition for TAMP_BKP17R register  ***************/

+#define TAMP_BKP17R_Pos              (0U)

+#define TAMP_BKP17R_Msk              (0xFFFFFFFFUL << TAMP_BKP17R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP17R                  TAMP_BKP17R_Msk

+

+/********************  Bits definition for TAMP_BKP18R register  ***************/

+#define TAMP_BKP18R_Pos              (0U)

+#define TAMP_BKP18R_Msk              (0xFFFFFFFFUL << TAMP_BKP18R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP18R                  TAMP_BKP18R_Msk

+

+/********************  Bits definition for TAMP_BKP19R register  ***************/

+#define TAMP_BKP19R_Pos              (0U)

+#define TAMP_BKP19R_Msk              (0xFFFFFFFFUL << TAMP_BKP19R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP19R                  TAMP_BKP19R_Msk

+

+/********************  Bits definition for TAMP_BKP20R register  ***************/

+#define TAMP_BKP20R_Pos              (0U)

+#define TAMP_BKP20R_Msk              (0xFFFFFFFFUL << TAMP_BKP20R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP20R                  TAMP_BKP20R_Msk

+

+/********************  Bits definition for TAMP_BKP21R register  ***************/

+#define TAMP_BKP21R_Pos              (0U)

+#define TAMP_BKP21R_Msk              (0xFFFFFFFFUL << TAMP_BKP21R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP21R                  TAMP_BKP21R_Msk

+

+/********************  Bits definition for TAMP_BKP22R register  ***************/

+#define TAMP_BKP22R_Pos              (0U)

+#define TAMP_BKP22R_Msk              (0xFFFFFFFFUL << TAMP_BKP22R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP22R                  TAMP_BKP22R_Msk

+

+/********************  Bits definition for TAMP_BKP23R register  ***************/

+#define TAMP_BKP23R_Pos              (0U)

+#define TAMP_BKP23R_Msk              (0xFFFFFFFFUL << TAMP_BKP23R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP23R                  TAMP_BKP23R_Msk

+

+/********************  Bits definition for TAMP_BKP24R register  ***************/

+#define TAMP_BKP24R_Pos              (0U)

+#define TAMP_BKP24R_Msk              (0xFFFFFFFFUL << TAMP_BKP24R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP24R                  TAMP_BKP24R_Msk

+

+/********************  Bits definition for TAMP_BKP25R register  ***************/

+#define TAMP_BKP25R_Pos              (0U)

+#define TAMP_BKP25R_Msk              (0xFFFFFFFFUL << TAMP_BKP25R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP25R                  TAMP_BKP25R_Msk

+

+/********************  Bits definition for TAMP_BKP26R register  ***************/

+#define TAMP_BKP26R_Pos              (0U)

+#define TAMP_BKP26R_Msk              (0xFFFFFFFFUL << TAMP_BKP26R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP26R                  TAMP_BKP26R_Msk

+

+/********************  Bits definition for TAMP_BKP27R register  ***************/

+#define TAMP_BKP27R_Pos              (0U)

+#define TAMP_BKP27R_Msk              (0xFFFFFFFFUL << TAMP_BKP27R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP27R                  TAMP_BKP27R_Msk

+

+/********************  Bits definition for TAMP_BKP28R register  ***************/

+#define TAMP_BKP28R_Pos              (0U)

+#define TAMP_BKP28R_Msk              (0xFFFFFFFFUL << TAMP_BKP28R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP28R                  TAMP_BKP28R_Msk

+

+/********************  Bits definition for TAMP_BKP29R register  ***************/

+#define TAMP_BKP29R_Pos              (0U)

+#define TAMP_BKP29R_Msk              (0xFFFFFFFFUL << TAMP_BKP29R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP29R                  TAMP_BKP29R_Msk

+

+/********************  Bits definition for TAMP_BKP30R register  ***************/

+#define TAMP_BKP30R_Pos              (0U)

+#define TAMP_BKP30R_Msk              (0xFFFFFFFFUL << TAMP_BKP30R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP30R                  TAMP_BKP30R_Msk

+

+/********************  Bits definition for TAMP_BKP31R register  ***************/

+#define TAMP_BKP31R_Pos              (0U)

+#define TAMP_BKP31R_Msk              (0xFFFFFFFFUL << TAMP_BKP31R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP31R                  TAMP_BKP31R_Msk

+

+/******************** Number of backup registers ******************************/

+#define TAMP_BKP_NUMBER_Pos             (5U)

+#define TAMP_BKP_NUMBER_Msk             (0x1UL << TAMP_BKP_NUMBER_Pos)         /*!< 0x00000080 */

+#define TAMP_BKP_NUMBER                 TAMP_BKP_NUMBER_Msk                    /*!< 32 BKPREG  */

+

+/******************************************************************************/

+/*                                                                            */

+/*                              SPDIF-RX Interface                            */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for SPDIF_CR register  ******************/

+#define SPDIFRX_CR_SPDIFEN_Pos      (0U)

+#define SPDIFRX_CR_SPDIFEN_Msk      (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)          /*!< 0x00000003 */

+#define SPDIFRX_CR_SPDIFEN          SPDIFRX_CR_SPDIFEN_Msk                     /*!<Peripheral Block Enable                      */

+#define SPDIFRX_CR_RXDMAEN_Pos      (2U)

+#define SPDIFRX_CR_RXDMAEN_Msk      (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)          /*!< 0x00000004 */

+#define SPDIFRX_CR_RXDMAEN          SPDIFRX_CR_RXDMAEN_Msk                     /*!<Receiver DMA Enable for data flow            */

+#define SPDIFRX_CR_RXSTEO_Pos       (3U)

+#define SPDIFRX_CR_RXSTEO_Msk       (0x1UL << SPDIFRX_CR_RXSTEO_Pos)           /*!< 0x00000008 */

+#define SPDIFRX_CR_RXSTEO           SPDIFRX_CR_RXSTEO_Msk                      /*!<Stereo Mode                                  */

+#define SPDIFRX_CR_DRFMT_Pos        (4U)

+#define SPDIFRX_CR_DRFMT_Msk        (0x3UL << SPDIFRX_CR_DRFMT_Pos)            /*!< 0x00000030 */

+#define SPDIFRX_CR_DRFMT            SPDIFRX_CR_DRFMT_Msk                       /*!<RX Data format                               */

+#define SPDIFRX_CR_PMSK_Pos         (6U)

+#define SPDIFRX_CR_PMSK_Msk         (0x1UL << SPDIFRX_CR_PMSK_Pos)             /*!< 0x00000040 */

+#define SPDIFRX_CR_PMSK             SPDIFRX_CR_PMSK_Msk                        /*!<Mask Parity error bit                        */

+#define SPDIFRX_CR_VMSK_Pos         (7U)

+#define SPDIFRX_CR_VMSK_Msk         (0x1UL << SPDIFRX_CR_VMSK_Pos)             /*!< 0x00000080 */

+#define SPDIFRX_CR_VMSK             SPDIFRX_CR_VMSK_Msk                        /*!<Mask of Validity bit                         */

+#define SPDIFRX_CR_CUMSK_Pos        (8U)

+#define SPDIFRX_CR_CUMSK_Msk        (0x1UL << SPDIFRX_CR_CUMSK_Pos)            /*!< 0x00000100 */

+#define SPDIFRX_CR_CUMSK            SPDIFRX_CR_CUMSK_Msk                       /*!<Mask of channel status and user bits         */

+#define SPDIFRX_CR_PTMSK_Pos        (9U)

+#define SPDIFRX_CR_PTMSK_Msk        (0x1UL << SPDIFRX_CR_PTMSK_Pos)            /*!< 0x00000200 */

+#define SPDIFRX_CR_PTMSK            SPDIFRX_CR_PTMSK_Msk                       /*!<Mask of Preamble Type bits                   */

+#define SPDIFRX_CR_CBDMAEN_Pos      (10U)

+#define SPDIFRX_CR_CBDMAEN_Msk      (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)          /*!< 0x00000400 */

+#define SPDIFRX_CR_CBDMAEN          SPDIFRX_CR_CBDMAEN_Msk                     /*!<Control Buffer DMA ENable for control flow   */

+#define SPDIFRX_CR_CHSEL_Pos        (11U)

+#define SPDIFRX_CR_CHSEL_Msk        (0x1UL << SPDIFRX_CR_CHSEL_Pos)            /*!< 0x00000800 */

+#define SPDIFRX_CR_CHSEL            SPDIFRX_CR_CHSEL_Msk                       /*!<Channel Selection                            */

+#define SPDIFRX_CR_NBTR_Pos         (12U)

+#define SPDIFRX_CR_NBTR_Msk         (0x3UL << SPDIFRX_CR_NBTR_Pos)             /*!< 0x00003000 */

+#define SPDIFRX_CR_NBTR             SPDIFRX_CR_NBTR_Msk                        /*!<Maximum allowed re-tries during synchronization phase */

+#define SPDIFRX_CR_WFA_Pos          (14U)

+#define SPDIFRX_CR_WFA_Msk          (0x1UL << SPDIFRX_CR_WFA_Pos)              /*!< 0x00004000 */

+#define SPDIFRX_CR_WFA              SPDIFRX_CR_WFA_Msk                         /*!<Wait For Activity     */

+#define SPDIFRX_CR_INSEL_Pos        (16U)

+#define SPDIFRX_CR_INSEL_Msk        (0x7UL << SPDIFRX_CR_INSEL_Pos)            /*!< 0x00070000 */

+#define SPDIFRX_CR_INSEL            SPDIFRX_CR_INSEL_Msk                       /*!<SPDIF input selection */

+#define SPDIFRX_CR_CKSEN_Pos        (20U)

+#define SPDIFRX_CR_CKSEN_Msk        (0x1UL << SPDIFRX_CR_CKSEN_Pos)            /*!< 0x00100000 */

+#define SPDIFRX_CR_CKSEN            SPDIFRX_CR_CKSEN_Msk                       /*!<Symbol Clock Enable */

+#define SPDIFRX_CR_CKSBKPEN_Pos     (21U)

+#define SPDIFRX_CR_CKSBKPEN_Msk     (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)         /*!< 0x00200000 */

+#define SPDIFRX_CR_CKSBKPEN         SPDIFRX_CR_CKSBKPEN_Msk                    /*!<Backup Symbol Clock Enable */

+

+/*******************  Bit definition for SPDIFRX_IMR register  *******************/

+#define SPDIFRX_IMR_RXNEIE_Pos      (0U)

+#define SPDIFRX_IMR_RXNEIE_Msk      (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)          /*!< 0x00000001 */

+#define SPDIFRX_IMR_RXNEIE          SPDIFRX_IMR_RXNEIE_Msk                     /*!<RXNE interrupt enable                              */

+#define SPDIFRX_IMR_CSRNEIE_Pos     (1U)

+#define SPDIFRX_IMR_CSRNEIE_Msk     (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)         /*!< 0x00000002 */

+#define SPDIFRX_IMR_CSRNEIE         SPDIFRX_IMR_CSRNEIE_Msk                    /*!<Control Buffer Ready Interrupt Enable              */

+#define SPDIFRX_IMR_PERRIE_Pos      (2U)

+#define SPDIFRX_IMR_PERRIE_Msk      (0x1UL << SPDIFRX_IMR_PERRIE_Pos)          /*!< 0x00000004 */

+#define SPDIFRX_IMR_PERRIE          SPDIFRX_IMR_PERRIE_Msk                     /*!<Parity error interrupt enable                      */

+#define SPDIFRX_IMR_OVRIE_Pos       (3U)

+#define SPDIFRX_IMR_OVRIE_Msk       (0x1UL << SPDIFRX_IMR_OVRIE_Pos)           /*!< 0x00000008 */

+#define SPDIFRX_IMR_OVRIE           SPDIFRX_IMR_OVRIE_Msk                      /*!<Overrun error Interrupt Enable                     */

+#define SPDIFRX_IMR_SBLKIE_Pos      (4U)

+#define SPDIFRX_IMR_SBLKIE_Msk      (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)          /*!< 0x00000010 */

+#define SPDIFRX_IMR_SBLKIE          SPDIFRX_IMR_SBLKIE_Msk                     /*!<Synchronization Block Detected Interrupt Enable    */

+#define SPDIFRX_IMR_SYNCDIE_Pos     (5U)

+#define SPDIFRX_IMR_SYNCDIE_Msk     (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)         /*!< 0x00000020 */

+#define SPDIFRX_IMR_SYNCDIE         SPDIFRX_IMR_SYNCDIE_Msk                    /*!<Synchronization Done                               */

+#define SPDIFRX_IMR_IFEIE_Pos       (6U)

+#define SPDIFRX_IMR_IFEIE_Msk       (0x1UL << SPDIFRX_IMR_IFEIE_Pos)           /*!< 0x00000040 */

+#define SPDIFRX_IMR_IFEIE           SPDIFRX_IMR_IFEIE_Msk                      /*!<Serial Interface Error Interrupt Enable            */

+

+/*******************  Bit definition for SPDIFRX_SR register  *******************/

+#define SPDIFRX_SR_RXNE_Pos         (0U)

+#define SPDIFRX_SR_RXNE_Msk         (0x1UL << SPDIFRX_SR_RXNE_Pos)             /*!< 0x00000001 */

+#define SPDIFRX_SR_RXNE             SPDIFRX_SR_RXNE_Msk                        /*!<Read data register not empty                          */

+#define SPDIFRX_SR_CSRNE_Pos        (1U)

+#define SPDIFRX_SR_CSRNE_Msk        (0x1UL << SPDIFRX_SR_CSRNE_Pos)            /*!< 0x00000002 */

+#define SPDIFRX_SR_CSRNE            SPDIFRX_SR_CSRNE_Msk                       /*!<The Control Buffer register is not empty              */

+#define SPDIFRX_SR_PERR_Pos         (2U)

+#define SPDIFRX_SR_PERR_Msk         (0x1UL << SPDIFRX_SR_PERR_Pos)             /*!< 0x00000004 */

+#define SPDIFRX_SR_PERR             SPDIFRX_SR_PERR_Msk                        /*!<Parity error                                          */

+#define SPDIFRX_SR_OVR_Pos          (3U)

+#define SPDIFRX_SR_OVR_Msk          (0x1UL << SPDIFRX_SR_OVR_Pos)              /*!< 0x00000008 */

+#define SPDIFRX_SR_OVR              SPDIFRX_SR_OVR_Msk                         /*!<Overrun error                                         */

+#define SPDIFRX_SR_SBD_Pos          (4U)

+#define SPDIFRX_SR_SBD_Msk          (0x1UL << SPDIFRX_SR_SBD_Pos)              /*!< 0x00000010 */

+#define SPDIFRX_SR_SBD              SPDIFRX_SR_SBD_Msk                         /*!<Synchronization Block Detected                        */

+#define SPDIFRX_SR_SYNCD_Pos        (5U)

+#define SPDIFRX_SR_SYNCD_Msk        (0x1UL << SPDIFRX_SR_SYNCD_Pos)            /*!< 0x00000020 */

+#define SPDIFRX_SR_SYNCD            SPDIFRX_SR_SYNCD_Msk                       /*!<Synchronization Done                                  */

+#define SPDIFRX_SR_FERR_Pos         (6U)

+#define SPDIFRX_SR_FERR_Msk         (0x1UL << SPDIFRX_SR_FERR_Pos)             /*!< 0x00000040 */

+#define SPDIFRX_SR_FERR             SPDIFRX_SR_FERR_Msk                        /*!<Framing error                                         */

+#define SPDIFRX_SR_SERR_Pos         (7U)

+#define SPDIFRX_SR_SERR_Msk         (0x1UL << SPDIFRX_SR_SERR_Pos)             /*!< 0x00000080 */

+#define SPDIFRX_SR_SERR             SPDIFRX_SR_SERR_Msk                        /*!<Synchronization error                                 */

+#define SPDIFRX_SR_TERR_Pos         (8U)

+#define SPDIFRX_SR_TERR_Msk         (0x1UL << SPDIFRX_SR_TERR_Pos)             /*!< 0x00000100 */

+#define SPDIFRX_SR_TERR             SPDIFRX_SR_TERR_Msk                        /*!<Time-out error                                        */

+#define SPDIFRX_SR_WIDTH5_Pos       (16U)

+#define SPDIFRX_SR_WIDTH5_Msk       (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)        /*!< 0x7FFF0000 */

+#define SPDIFRX_SR_WIDTH5           SPDIFRX_SR_WIDTH5_Msk                      /*!<Duration of 5 symbols counted with spdif_clk          */

+

+/*******************  Bit definition for SPDIFRX_IFCR register  *******************/

+#define SPDIFRX_IFCR_PERRCF_Pos     (2U)

+#define SPDIFRX_IFCR_PERRCF_Msk     (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)         /*!< 0x00000004 */

+#define SPDIFRX_IFCR_PERRCF         SPDIFRX_IFCR_PERRCF_Msk                    /*!<Clears the Parity error flag                         */

+#define SPDIFRX_IFCR_OVRCF_Pos      (3U)

+#define SPDIFRX_IFCR_OVRCF_Msk      (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)          /*!< 0x00000008 */

+#define SPDIFRX_IFCR_OVRCF          SPDIFRX_IFCR_OVRCF_Msk                     /*!<Clears the Overrun error flag                        */

+#define SPDIFRX_IFCR_SBDCF_Pos      (4U)

+#define SPDIFRX_IFCR_SBDCF_Msk      (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)          /*!< 0x00000010 */

+#define SPDIFRX_IFCR_SBDCF          SPDIFRX_IFCR_SBDCF_Msk                     /*!<Clears the Synchronization Block Detected flag       */

+#define SPDIFRX_IFCR_SYNCDCF_Pos    (5U)

+#define SPDIFRX_IFCR_SYNCDCF_Msk    (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)        /*!< 0x00000020 */

+#define SPDIFRX_IFCR_SYNCDCF        SPDIFRX_IFCR_SYNCDCF_Msk                   /*!<Clears the Synchronization Done flag                 */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/

+#define SPDIFRX_DR0_DR_Pos          (0U)

+#define SPDIFRX_DR0_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)         /*!< 0x00FFFFFF */

+#define SPDIFRX_DR0_DR              SPDIFRX_DR0_DR_Msk                         /*!<Data value            */

+#define SPDIFRX_DR0_PE_Pos          (24U)

+#define SPDIFRX_DR0_PE_Msk          (0x1UL << SPDIFRX_DR0_PE_Pos)              /*!< 0x01000000 */

+#define SPDIFRX_DR0_PE              SPDIFRX_DR0_PE_Msk                         /*!<Parity Error bit      */

+#define SPDIFRX_DR0_V_Pos           (25U)

+#define SPDIFRX_DR0_V_Msk           (0x1UL << SPDIFRX_DR0_V_Pos)               /*!< 0x02000000 */

+#define SPDIFRX_DR0_V               SPDIFRX_DR0_V_Msk                          /*!<Validity bit          */

+#define SPDIFRX_DR0_U_Pos           (26U)

+#define SPDIFRX_DR0_U_Msk           (0x1UL << SPDIFRX_DR0_U_Pos)               /*!< 0x04000000 */

+#define SPDIFRX_DR0_U               SPDIFRX_DR0_U_Msk                          /*!<User bit              */

+#define SPDIFRX_DR0_C_Pos           (27U)

+#define SPDIFRX_DR0_C_Msk           (0x1UL << SPDIFRX_DR0_C_Pos)               /*!< 0x08000000 */

+#define SPDIFRX_DR0_C               SPDIFRX_DR0_C_Msk                          /*!<Channel Status bit    */

+#define SPDIFRX_DR0_PT_Pos          (28U)

+#define SPDIFRX_DR0_PT_Msk          (0x3UL << SPDIFRX_DR0_PT_Pos)              /*!< 0x30000000 */

+#define SPDIFRX_DR0_PT              SPDIFRX_DR0_PT_Msk                         /*!<Preamble Type         */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/

+#define SPDIFRX_DR1_DR_Pos          (8U)

+#define SPDIFRX_DR1_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)         /*!< 0xFFFFFF00 */

+#define SPDIFRX_DR1_DR              SPDIFRX_DR1_DR_Msk                         /*!<Data value            */

+#define SPDIFRX_DR1_PT_Pos          (4U)

+#define SPDIFRX_DR1_PT_Msk          (0x3UL << SPDIFRX_DR1_PT_Pos)              /*!< 0x00000030 */

+#define SPDIFRX_DR1_PT              SPDIFRX_DR1_PT_Msk                         /*!<Preamble Type         */

+#define SPDIFRX_DR1_C_Pos           (3U)

+#define SPDIFRX_DR1_C_Msk           (0x1UL << SPDIFRX_DR1_C_Pos)               /*!< 0x00000008 */

+#define SPDIFRX_DR1_C               SPDIFRX_DR1_C_Msk                          /*!<Channel Status bit    */

+#define SPDIFRX_DR1_U_Pos           (2U)

+#define SPDIFRX_DR1_U_Msk           (0x1UL << SPDIFRX_DR1_U_Pos)               /*!< 0x00000004 */

+#define SPDIFRX_DR1_U               SPDIFRX_DR1_U_Msk                          /*!<User bit              */

+#define SPDIFRX_DR1_V_Pos           (1U)

+#define SPDIFRX_DR1_V_Msk           (0x1UL << SPDIFRX_DR1_V_Pos)               /*!< 0x00000002 */

+#define SPDIFRX_DR1_V               SPDIFRX_DR1_V_Msk                          /*!<Validity bit          */

+#define SPDIFRX_DR1_PE_Pos          (0U)

+#define SPDIFRX_DR1_PE_Msk          (0x1UL << SPDIFRX_DR1_PE_Pos)              /*!< 0x00000001 */

+#define SPDIFRX_DR1_PE              SPDIFRX_DR1_PE_Msk                         /*!<Parity Error bit      */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/

+#define SPDIFRX_DR1_DRNL1_Pos       (16U)

+#define SPDIFRX_DR1_DRNL1_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)        /*!< 0xFFFF0000 */

+#define SPDIFRX_DR1_DRNL1           SPDIFRX_DR1_DRNL1_Msk                      /*!<Data value Channel B      */

+#define SPDIFRX_DR1_DRNL2_Pos       (0U)

+#define SPDIFRX_DR1_DRNL2_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)        /*!< 0x0000FFFF */

+#define SPDIFRX_DR1_DRNL2           SPDIFRX_DR1_DRNL2_Msk                      /*!<Data value Channel A      */

+

+/*******************  Bit definition for SPDIFRX_CSR register   *******************/

+#define SPDIFRX_CSR_USR_Pos         (0U)

+#define SPDIFRX_CSR_USR_Msk         (0xFFFFUL << SPDIFRX_CSR_USR_Pos)          /*!< 0x0000FFFF */

+#define SPDIFRX_CSR_USR             SPDIFRX_CSR_USR_Msk                        /*!<User data information           */

+#define SPDIFRX_CSR_CS_Pos          (16U)

+#define SPDIFRX_CSR_CS_Msk          (0xFFUL << SPDIFRX_CSR_CS_Pos)             /*!< 0x00FF0000 */

+#define SPDIFRX_CSR_CS              SPDIFRX_CSR_CS_Msk                         /*!<Channel A status information    */

+#define SPDIFRX_CSR_SOB_Pos         (24U)

+#define SPDIFRX_CSR_SOB_Msk         (0x1UL << SPDIFRX_CSR_SOB_Pos)             /*!< 0x01000000 */

+#define SPDIFRX_CSR_SOB             SPDIFRX_CSR_SOB_Msk                        /*!<Start Of Block                  */

+

+/*******************  Bit definition for SPDIFRX_DIR register    *******************/

+#define SPDIFRX_DIR_THI_Pos         (0U)

+#define SPDIFRX_DIR_THI_Msk         (0x1FFFUL << SPDIFRX_DIR_THI_Pos)          /*!< 0x00001FFF */

+#define SPDIFRX_DIR_THI             SPDIFRX_DIR_THI_Msk                        /*!<Threshold LOW      */

+#define SPDIFRX_DIR_TLO_Pos         (16U)

+#define SPDIFRX_DIR_TLO_Msk         (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)          /*!< 0x1FFF0000 */

+#define SPDIFRX_DIR_TLO             SPDIFRX_DIR_TLO_Msk                        /*!<Threshold HIGH     */

+

+/*******************  Bit definition for SPDIFRX_VERR register    *******************/

+#define SPDIFRX_VERR_MINREV_Pos     (0U)

+#define SPDIFRX_VERR_MINREV_Msk     (0xFUL << SPDIFRX_VERR_MINREV_Pos)         /*!< 0x0000000F */

+#define SPDIFRX_VERR_MINREV         SPDIFRX_VERR_MINREV_Msk                    /*!<SPDIFRX Minor revision     */

+#define SPDIFRX_VERR_MAJREV_Pos     (4U)

+#define SPDIFRX_VERR_MAJREV_Msk     (0xFUL << SPDIFRX_VERR_MAJREV_Pos)         /*!< 0x000000F0 */

+#define SPDIFRX_VERR_MAJREV         SPDIFRX_VERR_MAJREV_Msk                    /*!<SPDIFRX Major revision     */

+

+/*******************  Bit definition for SPDIFRX_IDR register    *******************/

+#define SPDIFRX_IDR_ID_Pos          (0U)

+#define SPDIFRX_IDR_ID_Msk          (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos)       /*!< 0xFFFFFFFF */

+#define SPDIFRX_IDR_ID              SPDIFRX_IDR_ID_Msk                         /*!<SPDIFRX identifier     */

+

+/*******************  Bit definition for SPDIFRX_SIDR register    *******************/

+#define SPDIFRX_SIDR_SID_Pos        (0U)

+#define SPDIFRX_SIDR_SID_Msk        (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos)     /*!< 0xFFFFFFFF */

+#define SPDIFRX_SIDR_SID            SPDIFRX_SIDR_SID_Msk                       /*!<Size of the memory region allocated to SPDIFRX registers */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          Serial Audio Interface                            */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  SAI VERSION  ********************************/

+#define SAI_VER_V2_1

+

+/********************  Bit definition for SAI_GCR register  *******************/

+#define SAI_GCR_SYNCIN_Pos         (0U)

+#define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000003 */

+#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */

+#define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */

+#define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */

+

+#define SAI_GCR_SYNCOUT_Pos        (4U)

+#define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000030 */

+#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */

+#define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */

+#define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */

+

+/*******************  Bit definition for SAI_xCR1 register  *******************/

+#define SAI_xCR1_MODE_Pos          (0U)

+#define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */

+#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */

+#define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */

+#define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */

+

+#define SAI_xCR1_PRTCFG_Pos        (2U)

+#define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */

+#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */

+#define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */

+#define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */

+

+#define SAI_xCR1_DS_Pos            (5U)

+#define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */

+#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */

+#define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */

+#define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */

+#define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */

+

+#define SAI_xCR1_LSBFIRST_Pos      (8U)

+#define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */

+#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */

+#define SAI_xCR1_CKSTR_Pos         (9U)

+#define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */

+#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */

+

+#define SAI_xCR1_SYNCEN_Pos        (10U)

+#define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */

+#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */

+#define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */

+#define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */

+

+#define SAI_xCR1_MONO_Pos          (12U)

+#define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */

+#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */

+#define SAI_xCR1_OUTDRIV_Pos       (13U)

+#define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */

+#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */

+#define SAI_xCR1_SAIEN_Pos         (16U)

+#define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */

+#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */

+#define SAI_xCR1_DMAEN_Pos         (17U)

+#define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */

+#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */

+#define SAI_xCR1_NODIV_Pos         (19U)

+#define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */

+#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */

+

+#define SAI_xCR1_MCKDIV_Pos        (20U)

+#define SAI_xCR1_MCKDIV_Msk        (0x3FUL << SAI_xCR1_MCKDIV_Pos)             /*!< 0x03F00000 */

+#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[5:0] (Master ClocK Divider)  */

+#define SAI_xCR1_MCKDIV_0          (0x01UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00100000 */

+#define SAI_xCR1_MCKDIV_1          (0x02UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00200000 */

+#define SAI_xCR1_MCKDIV_2          (0x04UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00400000 */

+#define SAI_xCR1_MCKDIV_3          (0x08UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00800000 */

+#define SAI_xCR1_MCKDIV_4          (0x10UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x01000000 */

+#define SAI_xCR1_MCKDIV_5          (0x20UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x02000000 */

+

+#define SAI_xCR1_MCKEN_Pos         (27U)

+#define SAI_xCR1_MCKEN_Msk         (0x1UL << SAI_xCR1_MCKEN_Pos)               /*!< 0x08000000 */

+#define SAI_xCR1_MCKEN             SAI_xCR1_MCKEN_Msk                          /*!<Master ClocK enable */

+

+#define SAI_xCR1_OSR_Pos           (26U)

+#define SAI_xCR1_OSR_Msk           (0x1UL << SAI_xCR1_OSR_Pos)                 /*!< 0x04000000 */

+#define SAI_xCR1_OSR               SAI_xCR1_OSR_Msk                            /*!<OverSampling Ratio for master clock  */

+

+/* Legacy define */

+#define  SAI_xCR1_NOMCK               SAI_xCR1_NODIV

+

+/*******************  Bit definition for SAI_xCR2 register  *******************/

+#define SAI_xCR2_FTH_Pos           (0U)

+#define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */

+#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */

+#define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */

+#define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */

+#define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */

+

+#define SAI_xCR2_FFLUSH_Pos        (3U)

+#define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */

+#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */

+#define SAI_xCR2_TRIS_Pos          (4U)

+#define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */

+#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */

+#define SAI_xCR2_MUTE_Pos          (5U)

+#define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */

+#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */

+#define SAI_xCR2_MUTEVAL_Pos       (6U)

+#define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */

+#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */

+

+#define SAI_xCR2_MUTECNT_Pos       (7U)

+#define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */

+#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */

+#define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */

+#define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */

+#define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */

+#define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */

+#define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */

+#define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */

+

+#define SAI_xCR2_CPL_Pos           (13U)

+#define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */

+#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */

+

+#define SAI_xCR2_COMP_Pos          (14U)

+#define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */

+#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */

+#define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */

+#define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */

+

+/******************  Bit definition for SAI_xFRCR register  *******************/

+#define SAI_xFRCR_FRL_Pos          (0U)

+#define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */

+#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](FRame Length)  */

+#define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */

+#define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */

+#define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */

+#define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */

+#define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */

+#define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */

+#define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */

+#define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */

+

+#define SAI_xFRCR_FSALL_Pos        (8U)

+#define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */

+#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FSALL[6:0] (Frame Synchronization Active Level Length)  */

+#define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */

+#define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */

+#define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */

+#define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */

+#define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */

+#define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */

+#define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */

+

+#define SAI_xFRCR_FSDEF_Pos        (16U)

+#define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */

+#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!<Frame Synchronization Definition  */

+#define SAI_xFRCR_FSPOL_Pos        (17U)

+#define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */

+#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */

+#define SAI_xFRCR_FSOFF_Pos        (18U)

+#define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */

+#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */

+

+/* Legacy define */

+#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL

+

+/******************  Bit definition for SAI_xSLOTR register  *******************/

+#define SAI_xSLOTR_FBOFF_Pos       (0U)

+#define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */

+#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FBOFF[4:0](First Bit Offset)  */

+#define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */

+#define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */

+#define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */

+#define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */

+#define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */

+

+#define SAI_xSLOTR_SLOTSZ_Pos      (6U)

+#define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */

+#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */

+#define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */

+#define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */

+

+#define SAI_xSLOTR_NBSLOT_Pos      (8U)

+#define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */

+#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */

+#define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */

+#define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */

+#define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */

+#define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */

+

+#define SAI_xSLOTR_SLOTEN_Pos      (16U)

+#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */

+#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */

+

+/*******************  Bit definition for SAI_xIMR register  *******************/

+#define SAI_xIMR_OVRUDRIE_Pos      (0U)

+#define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */

+#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */

+#define SAI_xIMR_MUTEDETIE_Pos     (1U)

+#define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */

+#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */

+#define SAI_xIMR_WCKCFGIE_Pos      (2U)

+#define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */

+#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */

+#define SAI_xIMR_FREQIE_Pos        (3U)

+#define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */

+#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */

+#define SAI_xIMR_CNRDYIE_Pos       (4U)

+#define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */

+#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */

+#define SAI_xIMR_AFSDETIE_Pos      (5U)

+#define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */

+#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */

+#define SAI_xIMR_LFSDETIE_Pos      (6U)

+#define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */

+#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */

+

+/********************  Bit definition for SAI_xSR register  *******************/

+#define SAI_xSR_OVRUDR_Pos         (0U)

+#define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */

+#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */

+#define SAI_xSR_MUTEDET_Pos        (1U)

+#define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */

+#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */

+#define SAI_xSR_WCKCFG_Pos         (2U)

+#define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */

+#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */

+#define SAI_xSR_FREQ_Pos           (3U)

+#define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */

+#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */

+#define SAI_xSR_CNRDY_Pos          (4U)

+#define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */

+#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */

+#define SAI_xSR_AFSDET_Pos         (5U)

+#define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */

+#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */

+#define SAI_xSR_LFSDET_Pos         (6U)

+#define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */

+#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */

+

+#define SAI_xSR_FLVL_Pos           (16U)

+#define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */

+#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */

+#define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */

+#define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */

+#define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */

+

+/******************  Bit definition for SAI_xCLRFR register  ******************/

+#define SAI_xCLRFR_COVRUDR_Pos     (0U)

+#define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */

+#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */

+#define SAI_xCLRFR_CMUTEDET_Pos    (1U)

+#define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */

+#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */

+#define SAI_xCLRFR_CWCKCFG_Pos     (2U)

+#define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */

+#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */

+#define SAI_xCLRFR_CFREQ_Pos       (3U)

+#define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */

+#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */

+#define SAI_xCLRFR_CCNRDY_Pos      (4U)

+#define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */

+#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */

+#define SAI_xCLRFR_CAFSDET_Pos     (5U)

+#define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */

+#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */

+#define SAI_xCLRFR_CLFSDET_Pos     (6U)

+#define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */

+#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */

+

+/******************  Bit definition for SAI_xDR register  *********************/

+#define SAI_xDR_DATA_Pos           (0U)

+#define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */

+#define SAI_xDR_DATA               SAI_xDR_DATA_Msk

+

+/*******************  Bit definition for SAI_PDMCR register  ******************/

+#define SAI_PDMCR_PDMEN_Pos        (0U)

+#define SAI_PDMCR_PDMEN_Msk        (0x1UL << SAI_PDMCR_PDMEN_Pos)              /*!< 0x00000001 */

+#define SAI_PDMCR_PDMEN            SAI_PDMCR_PDMEN_Msk                         /*!<PDM Enable                                          */

+

+#define SAI_PDMCR_MICNBR_Pos       (4U)

+#define SAI_PDMCR_MICNBR_Msk       (0x3UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000030 */

+#define SAI_PDMCR_MICNBR           SAI_PDMCR_MICNBR_Msk                        /*!<Number of microphones                               */

+#define SAI_PDMCR_MICNBR_0         (0x1UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000010 */

+#define SAI_PDMCR_MICNBR_1         (0x2UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000020 */

+

+#define SAI_PDMCR_CKEN1_Pos        (8U)

+#define SAI_PDMCR_CKEN1_Msk        (0x1UL << SAI_PDMCR_CKEN1_Pos)              /*!< 0x00000100 */

+#define SAI_PDMCR_CKEN1            SAI_PDMCR_CKEN1_Msk                         /*!<Clock enable of bitstream clock number 1            */

+#define SAI_PDMCR_CKEN2_Pos        (9U)

+#define SAI_PDMCR_CKEN2_Msk        (0x1UL << SAI_PDMCR_CKEN2_Pos)              /*!< 0x00000200 */

+#define SAI_PDMCR_CKEN2            SAI_PDMCR_CKEN2_Msk                         /*!<Clock enable of bitstream clock number 2            */

+#define SAI_PDMCR_CKEN3_Pos        (10U)

+#define SAI_PDMCR_CKEN3_Msk        (0x1UL << SAI_PDMCR_CKEN3_Pos)              /*!< 0x00000400 */

+#define SAI_PDMCR_CKEN3            SAI_PDMCR_CKEN3_Msk                         /*!<Clock enable of bitstream clock number 3            */

+#define SAI_PDMCR_CKEN4_Pos        (11U)

+#define SAI_PDMCR_CKEN4_Msk        (0x1UL << SAI_PDMCR_CKEN4_Pos)              /*!< 0x00000800 */

+#define SAI_PDMCR_CKEN4            SAI_PDMCR_CKEN4_Msk                         /*!<Clock enable of bitstream clock number 4            */

+

+/******************  Bit definition for SAI_PDMDLY register  ******************/

+#define SAI_PDMDLY_DLYM1L_Pos      (0U)

+#define SAI_PDMDLY_DLYM1L_Msk      (0x7UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000007 */

+#define SAI_PDMDLY_DLYM1L          SAI_PDMDLY_DLYM1L_Msk                       /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */

+#define SAI_PDMDLY_DLYM1L_0        (0x1UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000001 */

+#define SAI_PDMDLY_DLYM1L_1        (0x2UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000002 */

+#define SAI_PDMDLY_DLYM1L_2        (0x4UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000004 */

+

+#define SAI_PDMDLY_DLYM1R_Pos      (4U)

+#define SAI_PDMDLY_DLYM1R_Msk      (0x7UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000070 */

+#define SAI_PDMDLY_DLYM1R          SAI_PDMDLY_DLYM1R_Msk                       /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */

+#define SAI_PDMDLY_DLYM1R_0        (0x1UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000010 */

+#define SAI_PDMDLY_DLYM1R_1        (0x2UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000020 */

+#define SAI_PDMDLY_DLYM1R_2        (0x4UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000040 */

+

+#define SAI_PDMDLY_DLYM2L_Pos      (8U)

+#define SAI_PDMDLY_DLYM2L_Msk      (0x7UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000700 */

+#define SAI_PDMDLY_DLYM2L          SAI_PDMDLY_DLYM2L_Msk                       /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */

+#define SAI_PDMDLY_DLYM2L_0        (0x1UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000100 */

+#define SAI_PDMDLY_DLYM2L_1        (0x2UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000200 */

+#define SAI_PDMDLY_DLYM2L_2        (0x4UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000400 */

+

+#define SAI_PDMDLY_DLYM2R_Pos      (12U)

+#define SAI_PDMDLY_DLYM2R_Msk      (0x7UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00007000 */

+#define SAI_PDMDLY_DLYM2R          SAI_PDMDLY_DLYM2R_Msk                       /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/

+#define SAI_PDMDLY_DLYM2R_0        (0x1UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00001000 */

+#define SAI_PDMDLY_DLYM2R_1        (0x2UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00002000 */

+#define SAI_PDMDLY_DLYM2R_2        (0x4UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00004000 */

+

+#define SAI_PDMDLY_DLYM3L_Pos      (16U)

+#define SAI_PDMDLY_DLYM3L_Msk      (0x7UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00070000 */

+#define SAI_PDMDLY_DLYM3L          SAI_PDMDLY_DLYM3L_Msk                       /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/

+#define SAI_PDMDLY_DLYM3L_0        (0x1UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00010000 */

+#define SAI_PDMDLY_DLYM3L_1        (0x2UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00020000 */

+#define SAI_PDMDLY_DLYM3L_2        (0x4UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00040000 */

+

+#define SAI_PDMDLY_DLYM3R_Pos      (20U)

+#define SAI_PDMDLY_DLYM3R_Msk      (0x7UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00700000 */

+#define SAI_PDMDLY_DLYM3R          SAI_PDMDLY_DLYM3R_Msk                       /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/

+#define SAI_PDMDLY_DLYM3R_0        (0x1UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00100000 */

+#define SAI_PDMDLY_DLYM3R_1        (0x2UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00200000 */

+#define SAI_PDMDLY_DLYM3R_2        (0x4UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00400000 */

+

+#define SAI_PDMDLY_DLYM4L_Pos      (24U)

+#define SAI_PDMDLY_DLYM4L_Msk      (0x7UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x07000000 */

+#define SAI_PDMDLY_DLYM4L          SAI_PDMDLY_DLYM4L_Msk                       /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/

+#define SAI_PDMDLY_DLYM4L_0        (0x1UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x01000000 */

+#define SAI_PDMDLY_DLYM4L_1        (0x2UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x02000000 */

+#define SAI_PDMDLY_DLYM4L_2        (0x4UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x04000000 */

+

+#define SAI_PDMDLY_DLYM4R_Pos      (28U)

+#define SAI_PDMDLY_DLYM4R_Msk      (0x7UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x70000000 */

+#define SAI_PDMDLY_DLYM4R          SAI_PDMDLY_DLYM4R_Msk                       /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/

+#define SAI_PDMDLY_DLYM4R_0        (0x1UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x10000000 */

+#define SAI_PDMDLY_DLYM4R_1        (0x2UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x20000000 */

+#define SAI_PDMDLY_DLYM4R_2        (0x4UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x40000000 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           SDMMC Interface                                  */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for SDMMC_POWER register  ******************/

+#define SDMMC_POWER_PWRCTRL_Pos          (0U)

+#define SDMMC_POWER_PWRCTRL_Msk          (0x3UL << SDMMC_POWER_PWRCTRL_Pos)    /*!< 0x00000003 */

+#define SDMMC_POWER_PWRCTRL              SDMMC_POWER_PWRCTRL_Msk               /*!<PWRCTRL[1:0] bits (Power supply control bits) */

+#define SDMMC_POWER_PWRCTRL_0            (0x1UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000001 */

+#define SDMMC_POWER_PWRCTRL_1            (0x2UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000002 */

+#define SDMMC_POWER_VSWITCH_Pos          (2U)

+#define SDMMC_POWER_VSWITCH_Msk          (0x1UL << SDMMC_POWER_VSWITCH_Pos)    /*!< 0x00000004 */

+#define SDMMC_POWER_VSWITCH              SDMMC_POWER_VSWITCH_Msk               /*!<Voltage switch sequence start */

+#define SDMMC_POWER_VSWITCHEN_Pos        (3U)

+#define SDMMC_POWER_VSWITCHEN_Msk        (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)  /*!< 0x00000008 */

+#define SDMMC_POWER_VSWITCHEN            SDMMC_POWER_VSWITCHEN_Msk             /*!<Voltage switch procedure enable */

+#define SDMMC_POWER_DIRPOL_Pos           (4U)

+#define SDMMC_POWER_DIRPOL_Msk           (0x1UL << SDMMC_POWER_DIRPOL_Pos)     /*!< 0x00000010 */

+#define SDMMC_POWER_DIRPOL               SDMMC_POWER_DIRPOL_Msk                /*!<Data and Command direction signals polarity selection */

+

+/******************  Bit definition for SDMMC_CLKCR register  ******************/

+#define SDMMC_CLKCR_CLKDIV_Pos           (0U)

+#define SDMMC_CLKCR_CLKDIV_Msk           (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)   /*!< 0x000003FF */

+#define SDMMC_CLKCR_CLKDIV               SDMMC_CLKCR_CLKDIV_Msk                /*!<Clock divide factor             */

+#define SDMMC_CLKCR_PWRSAV_Pos           (12U)

+#define SDMMC_CLKCR_PWRSAV_Msk           (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)     /*!< 0x00001000 */

+#define SDMMC_CLKCR_PWRSAV               SDMMC_CLKCR_PWRSAV_Msk                /*!<Power saving configuration bit  */

+

+#define SDMMC_CLKCR_WIDBUS_Pos           (14U)

+#define SDMMC_CLKCR_WIDBUS_Msk           (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)     /*!< 0x0000C000 */

+#define SDMMC_CLKCR_WIDBUS               SDMMC_CLKCR_WIDBUS_Msk                /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */

+#define SDMMC_CLKCR_WIDBUS_0             (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00004000 */

+#define SDMMC_CLKCR_WIDBUS_1             (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00008000 */

+

+#define SDMMC_CLKCR_NEGEDGE_Pos          (16U)

+#define SDMMC_CLKCR_NEGEDGE_Msk          (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)    /*!< 0x00010000 */

+#define SDMMC_CLKCR_NEGEDGE              SDMMC_CLKCR_NEGEDGE_Msk               /*!<SDMMC_CK dephasing selection bit */

+#define SDMMC_CLKCR_HWFC_EN_Pos          (17U)

+#define SDMMC_CLKCR_HWFC_EN_Msk          (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)    /*!< 0x00020000 */

+#define SDMMC_CLKCR_HWFC_EN              SDMMC_CLKCR_HWFC_EN_Msk               /*!<HW Flow Control enable           */

+#define SDMMC_CLKCR_DDR_Pos              (18U)

+#define SDMMC_CLKCR_DDR_Msk              (0x1UL << SDMMC_CLKCR_DDR_Pos)        /*!< 0x00040000 */

+#define SDMMC_CLKCR_DDR                  SDMMC_CLKCR_DDR_Msk                   /*!<Data rate signaling selection    */

+#define SDMMC_CLKCR_BUSSPEED_Pos         (19U)

+#define SDMMC_CLKCR_BUSSPEED_Msk         (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)   /*!< 0x00080000 */

+#define SDMMC_CLKCR_BUSSPEED             SDMMC_CLKCR_BUSSPEED_Msk              /*!<Bus speed mode selection         */

+#define SDMMC_CLKCR_SELCLKRX_Pos         (20U)

+#define SDMMC_CLKCR_SELCLKRX_Msk         (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)   /*!< 0x00300000 */

+#define SDMMC_CLKCR_SELCLKRX             SDMMC_CLKCR_SELCLKRX_Msk              /*!<SELCLKRX[1:0] bits (Receive clock selection) */

+#define SDMMC_CLKCR_SELCLKRX_0           (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00100000 */

+#define SDMMC_CLKCR_SELCLKRX_1           (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00200000 */

+

+/*******************  Bit definition for SDMMC_ARG register  *******************/

+#define SDMMC_ARG_CMDARG_Pos             (0U)

+#define SDMMC_ARG_CMDARG_Msk             (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_ARG_CMDARG                 SDMMC_ARG_CMDARG_Msk                  /*!<Command argument */

+

+/*******************  Bit definition for SDMMC_CMD register  *******************/

+#define SDMMC_CMD_CMDINDEX_Pos           (0U)

+#define SDMMC_CMD_CMDINDEX_Msk           (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)    /*!< 0x0000003F */

+#define SDMMC_CMD_CMDINDEX               SDMMC_CMD_CMDINDEX_Msk                /*!<Command Index                               */

+#define SDMMC_CMD_CMDTRANS_Pos           (6U)

+#define SDMMC_CMD_CMDTRANS_Msk           (0x1UL << SDMMC_CMD_CMDTRANS_Pos)     /*!< 0x00000040 */

+#define SDMMC_CMD_CMDTRANS               SDMMC_CMD_CMDTRANS_Msk                /*!<CPSM Treats command as a Data Transfer      */

+#define SDMMC_CMD_CMDSTOP_Pos            (7U)

+#define SDMMC_CMD_CMDSTOP_Msk            (0x1UL << SDMMC_CMD_CMDSTOP_Pos)      /*!< 0x00000080 */

+#define SDMMC_CMD_CMDSTOP                SDMMC_CMD_CMDSTOP_Msk                 /*!<CPSM Treats command as a Stop               */

+

+#define SDMMC_CMD_WAITRESP_Pos           (8U)

+#define SDMMC_CMD_WAITRESP_Msk           (0x3UL << SDMMC_CMD_WAITRESP_Pos)     /*!< 0x00000300 */

+#define SDMMC_CMD_WAITRESP               SDMMC_CMD_WAITRESP_Msk                /*!<WAITRESP[1:0] bits (Wait for response bits) */

+#define SDMMC_CMD_WAITRESP_0             (0x1UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000100 */

+#define SDMMC_CMD_WAITRESP_1             (0x2UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000200 */

+

+#define SDMMC_CMD_WAITINT_Pos            (10U)

+#define SDMMC_CMD_WAITINT_Msk            (0x1UL << SDMMC_CMD_WAITINT_Pos)      /*!< 0x00000400 */

+#define SDMMC_CMD_WAITINT                SDMMC_CMD_WAITINT_Msk                 /*!<CPSM Waits for Interrupt Request                               */

+#define SDMMC_CMD_WAITPEND_Pos           (11U)

+#define SDMMC_CMD_WAITPEND_Msk           (0x1UL << SDMMC_CMD_WAITPEND_Pos)     /*!< 0x00000800 */

+#define SDMMC_CMD_WAITPEND               SDMMC_CMD_WAITPEND_Msk                /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */

+#define SDMMC_CMD_CPSMEN_Pos             (12U)

+#define SDMMC_CMD_CPSMEN_Msk             (0x1UL << SDMMC_CMD_CPSMEN_Pos)       /*!< 0x00001000 */

+#define SDMMC_CMD_CPSMEN                 SDMMC_CMD_CPSMEN_Msk                  /*!<Command path state machine (CPSM) Enable bit                   */

+#define SDMMC_CMD_DTHOLD_Pos             (13U)

+#define SDMMC_CMD_DTHOLD_Msk             (0x1UL << SDMMC_CMD_DTHOLD_Pos)       /*!< 0x00002000 */

+#define SDMMC_CMD_DTHOLD                 SDMMC_CMD_DTHOLD_Msk                  /*!<Hold new data block transmission and reception in the DPSM     */

+#define SDMMC_CMD_BOOTMODE_Pos           (14U)

+#define SDMMC_CMD_BOOTMODE_Msk           (0x1UL << SDMMC_CMD_BOOTMODE_Pos)     /*!< 0x00004000 */

+#define SDMMC_CMD_BOOTMODE               SDMMC_CMD_BOOTMODE_Msk                /*!<Boot mode                                                      */

+#define SDMMC_CMD_BOOTEN_Pos             (15U)

+#define SDMMC_CMD_BOOTEN_Msk             (0x1UL << SDMMC_CMD_BOOTEN_Pos)       /*!< 0x00008000 */

+#define SDMMC_CMD_BOOTEN                 SDMMC_CMD_BOOTEN_Msk                  /*!<Enable Boot mode procedure                                     */

+#define SDMMC_CMD_CMDSUSPEND_Pos         (16U)

+#define SDMMC_CMD_CMDSUSPEND_Msk         (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)   /*!< 0x00010000 */

+#define SDMMC_CMD_CMDSUSPEND             SDMMC_CMD_CMDSUSPEND_Msk              /*!<CPSM Treats command as a Suspend or Resume command             */

+

+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/

+#define SDMMC_RESPCMD_RESPCMD_Pos        (0U)

+#define SDMMC_RESPCMD_RESPCMD_Msk        (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */

+#define SDMMC_RESPCMD_RESPCMD            SDMMC_RESPCMD_RESPCMD_Msk             /*!<Response command index */

+

+/******************  Bit definition for SDMMC_RESP0 register  ******************/

+#define SDMMC_RESP0_CARDSTATUS0_Pos      (0U)

+#define SDMMC_RESP0_CARDSTATUS0_Msk      (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP0_CARDSTATUS0          SDMMC_RESP0_CARDSTATUS0_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP1 register  ******************/

+#define SDMMC_RESP1_CARDSTATUS1_Pos      (0U)

+#define SDMMC_RESP1_CARDSTATUS1_Msk      (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP1_CARDSTATUS1          SDMMC_RESP1_CARDSTATUS1_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP2 register  ******************/

+#define SDMMC_RESP2_CARDSTATUS2_Pos      (0U)

+#define SDMMC_RESP2_CARDSTATUS2_Msk      (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP2_CARDSTATUS2          SDMMC_RESP2_CARDSTATUS2_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP3 register  ******************/

+#define SDMMC_RESP3_CARDSTATUS3_Pos      (0U)

+#define SDMMC_RESP3_CARDSTATUS3_Msk      (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP3_CARDSTATUS3          SDMMC_RESP3_CARDSTATUS3_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP4 register  ******************/

+#define SDMMC_RESP4_CARDSTATUS4_Pos      (0U)

+#define SDMMC_RESP4_CARDSTATUS4_Msk      (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP4_CARDSTATUS4          SDMMC_RESP4_CARDSTATUS4_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_DTIMER register  *****************/

+#define SDMMC_DTIMER_DATATIME_Pos        (0U)

+#define SDMMC_DTIMER_DATATIME_Msk        (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_DTIMER_DATATIME            SDMMC_DTIMER_DATATIME_Msk             /*!<Data timeout period. */

+

+/******************  Bit definition for SDMMC_DLEN register  *******************/

+#define SDMMC_DLEN_DATALENGTH_Pos        (0U)

+#define SDMMC_DLEN_DATALENGTH_Msk        (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_DLEN_DATALENGTH            SDMMC_DLEN_DATALENGTH_Msk             /*!<Data length value    */

+

+/******************  Bit definition for SDMMC_DCTRL register  ******************/

+#define SDMMC_DCTRL_DTEN_Pos             (0U)

+#define SDMMC_DCTRL_DTEN_Msk             (0x1UL << SDMMC_DCTRL_DTEN_Pos)       /*!< 0x00000001 */

+#define SDMMC_DCTRL_DTEN                 SDMMC_DCTRL_DTEN_Msk                  /*!<Data transfer enabled bit                */

+#define SDMMC_DCTRL_DTDIR_Pos            (1U)

+#define SDMMC_DCTRL_DTDIR_Msk            (0x1UL << SDMMC_DCTRL_DTDIR_Pos)      /*!< 0x00000002 */

+#define SDMMC_DCTRL_DTDIR                SDMMC_DCTRL_DTDIR_Msk                 /*!<Data transfer direction selection        */

+#define SDMMC_DCTRL_DTMODE_Pos           (2U)

+#define SDMMC_DCTRL_DTMODE_Msk           (0x3UL << SDMMC_DCTRL_DTMODE_Pos)     /*!< 0x0000000C */

+#define SDMMC_DCTRL_DTMODE               SDMMC_DCTRL_DTMODE_Msk                /*!<DTMODE[1:0] Data transfer mode selection */

+#define SDMMC_DCTRL_DTMODE_0             (0x1UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000004 */

+#define SDMMC_DCTRL_DTMODE_1             (0x2UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000008 */

+

+#define SDMMC_DCTRL_DBLOCKSIZE_Pos       (4U)

+#define SDMMC_DCTRL_DBLOCKSIZE_Msk       (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */

+#define SDMMC_DCTRL_DBLOCKSIZE           SDMMC_DCTRL_DBLOCKSIZE_Msk            /*!<DBLOCKSIZE[3:0] bits (Data block size) */

+#define SDMMC_DCTRL_DBLOCKSIZE_0         (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000010 */

+#define SDMMC_DCTRL_DBLOCKSIZE_1         (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000020 */

+#define SDMMC_DCTRL_DBLOCKSIZE_2         (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000040 */

+#define SDMMC_DCTRL_DBLOCKSIZE_3         (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000080 */

+

+#define SDMMC_DCTRL_RWSTART_Pos          (8U)

+#define SDMMC_DCTRL_RWSTART_Msk          (0x1UL << SDMMC_DCTRL_RWSTART_Pos)    /*!< 0x00000100 */

+#define SDMMC_DCTRL_RWSTART              SDMMC_DCTRL_RWSTART_Msk               /*!<Read wait start                                 */

+#define SDMMC_DCTRL_RWSTOP_Pos           (9U)

+#define SDMMC_DCTRL_RWSTOP_Msk           (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)     /*!< 0x00000200 */

+#define SDMMC_DCTRL_RWSTOP               SDMMC_DCTRL_RWSTOP_Msk                /*!<Read wait stop                                  */

+#define SDMMC_DCTRL_RWMOD_Pos            (10U)

+#define SDMMC_DCTRL_RWMOD_Msk            (0x1UL << SDMMC_DCTRL_RWMOD_Pos)      /*!< 0x00000400 */

+#define SDMMC_DCTRL_RWMOD                SDMMC_DCTRL_RWMOD_Msk                 /*!<Read wait mode                                  */

+#define SDMMC_DCTRL_SDIOEN_Pos           (11U)

+#define SDMMC_DCTRL_SDIOEN_Msk           (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)     /*!< 0x00000800 */

+#define SDMMC_DCTRL_SDIOEN               SDMMC_DCTRL_SDIOEN_Msk                /*!<SD I/O enable functions                         */

+#define SDMMC_DCTRL_BOOTACKEN_Pos        (12U)

+#define SDMMC_DCTRL_BOOTACKEN_Msk        (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)  /*!< 0x00001000 */

+#define SDMMC_DCTRL_BOOTACKEN            SDMMC_DCTRL_BOOTACKEN_Msk             /*!<Enable the reception of the Boot Acknowledgment */

+#define SDMMC_DCTRL_FIFORST_Pos          (13U)

+#define SDMMC_DCTRL_FIFORST_Msk          (0x1UL << SDMMC_DCTRL_FIFORST_Pos)    /*!< 0x00002000 */

+#define SDMMC_DCTRL_FIFORST              SDMMC_DCTRL_FIFORST_Msk               /*!<FIFO reset                                      */

+

+/******************  Bit definition for SDMMC_DCOUNT register  *****************/

+#define SDMMC_DCOUNT_DATACOUNT_Pos       (0U)

+#define SDMMC_DCOUNT_DATACOUNT_Msk       (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_DCOUNT_DATACOUNT           SDMMC_DCOUNT_DATACOUNT_Msk            /*!<Data count value */

+

+/******************  Bit definition for SDMMC_STA register  ********************/

+#define SDMMC_STA_CCRCFAIL_Pos           (0U)

+#define SDMMC_STA_CCRCFAIL_Msk           (0x1UL << SDMMC_STA_CCRCFAIL_Pos)     /*!< 0x00000001 */

+#define SDMMC_STA_CCRCFAIL               SDMMC_STA_CCRCFAIL_Msk                /*!<Command response received (CRC check failed)  */

+#define SDMMC_STA_DCRCFAIL_Pos           (1U)

+#define SDMMC_STA_DCRCFAIL_Msk           (0x1UL << SDMMC_STA_DCRCFAIL_Pos)     /*!< 0x00000002 */

+#define SDMMC_STA_DCRCFAIL               SDMMC_STA_DCRCFAIL_Msk                /*!<Data block sent/received (CRC check failed)   */

+#define SDMMC_STA_CTIMEOUT_Pos           (2U)

+#define SDMMC_STA_CTIMEOUT_Msk           (0x1UL << SDMMC_STA_CTIMEOUT_Pos)     /*!< 0x00000004 */

+#define SDMMC_STA_CTIMEOUT               SDMMC_STA_CTIMEOUT_Msk                /*!<Command response timeout                      */

+#define SDMMC_STA_DTIMEOUT_Pos           (3U)

+#define SDMMC_STA_DTIMEOUT_Msk           (0x1UL << SDMMC_STA_DTIMEOUT_Pos)     /*!< 0x00000008 */

+#define SDMMC_STA_DTIMEOUT               SDMMC_STA_DTIMEOUT_Msk                /*!<Data timeout                                  */

+#define SDMMC_STA_TXUNDERR_Pos           (4U)

+#define SDMMC_STA_TXUNDERR_Msk           (0x1UL << SDMMC_STA_TXUNDERR_Pos)     /*!< 0x00000010 */

+#define SDMMC_STA_TXUNDERR               SDMMC_STA_TXUNDERR_Msk                /*!<Transmit FIFO underrun error                  */

+#define SDMMC_STA_RXOVERR_Pos            (5U)

+#define SDMMC_STA_RXOVERR_Msk            (0x1UL << SDMMC_STA_RXOVERR_Pos)      /*!< 0x00000020 */

+#define SDMMC_STA_RXOVERR                SDMMC_STA_RXOVERR_Msk                 /*!<Received FIFO overrun error                   */

+#define SDMMC_STA_CMDREND_Pos            (6U)

+#define SDMMC_STA_CMDREND_Msk            (0x1UL << SDMMC_STA_CMDREND_Pos)      /*!< 0x00000040 */

+#define SDMMC_STA_CMDREND                SDMMC_STA_CMDREND_Msk                 /*!<Command response received (CRC check passed)  */

+#define SDMMC_STA_CMDSENT_Pos            (7U)

+#define SDMMC_STA_CMDSENT_Msk            (0x1UL << SDMMC_STA_CMDSENT_Pos)      /*!< 0x00000080 */

+#define SDMMC_STA_CMDSENT                SDMMC_STA_CMDSENT_Msk                 /*!<Command sent (no response required)           */

+#define SDMMC_STA_DATAEND_Pos            (8U)

+#define SDMMC_STA_DATAEND_Msk            (0x1UL << SDMMC_STA_DATAEND_Pos)      /*!< 0x00000100 */

+#define SDMMC_STA_DATAEND                SDMMC_STA_DATAEND_Msk                 /*!<Data end (data counter, SDIDCOUNT, is zero)   */

+#define SDMMC_STA_DHOLD_Pos              (9U)

+#define SDMMC_STA_DHOLD_Msk              (0x1UL << SDMMC_STA_DHOLD_Pos)        /*!< 0x00000200 */

+#define SDMMC_STA_DHOLD                  SDMMC_STA_DHOLD_Msk                   /*!<Data transfer Hold                                                      */

+#define SDMMC_STA_DBCKEND_Pos            (10U)

+#define SDMMC_STA_DBCKEND_Msk            (0x1UL << SDMMC_STA_DBCKEND_Pos)      /*!< 0x00000400 */

+#define SDMMC_STA_DBCKEND                SDMMC_STA_DBCKEND_Msk                 /*!<Data block sent/received (CRC check passed)   */

+#define SDMMC_STA_DABORT_Pos             (11U)

+#define SDMMC_STA_DABORT_Msk             (0x1UL << SDMMC_STA_DABORT_Pos)       /*!< 0x00000800 */

+#define SDMMC_STA_DABORT                 SDMMC_STA_DABORT_Msk                  /*!<Data transfer aborted by CMD12                                          */

+#define SDMMC_STA_DPSMACT_Pos            (12U)

+#define SDMMC_STA_DPSMACT_Msk            (0x1UL << SDMMC_STA_DPSMACT_Pos)      /*!< 0x00001000 */

+#define SDMMC_STA_DPSMACT                SDMMC_STA_DPSMACT_Msk                 /*!<Data path state machine active                                       */

+#define SDMMC_STA_CPSMACT_Pos            (13U)

+#define SDMMC_STA_CPSMACT_Msk            (0x1UL << SDMMC_STA_CPSMACT_Pos)      /*!< 0x00002000 */

+#define SDMMC_STA_CPSMACT                SDMMC_STA_CPSMACT_Msk                 /*!<Command path state machine active                                          */

+#define SDMMC_STA_TXFIFOHE_Pos           (14U)

+#define SDMMC_STA_TXFIFOHE_Msk           (0x1UL << SDMMC_STA_TXFIFOHE_Pos)     /*!< 0x00004000 */

+#define SDMMC_STA_TXFIFOHE               SDMMC_STA_TXFIFOHE_Msk                /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */

+#define SDMMC_STA_RXFIFOHF_Pos           (15U)

+#define SDMMC_STA_RXFIFOHF_Msk           (0x1UL << SDMMC_STA_RXFIFOHF_Pos)     /*!< 0x00008000 */

+#define SDMMC_STA_RXFIFOHF               SDMMC_STA_RXFIFOHF_Msk                /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */

+#define SDMMC_STA_TXFIFOF_Pos            (16U)

+#define SDMMC_STA_TXFIFOF_Msk            (0x1UL << SDMMC_STA_TXFIFOF_Pos)      /*!< 0x00010000 */

+#define SDMMC_STA_TXFIFOF                SDMMC_STA_TXFIFOF_Msk                 /*!<Transmit FIFO full                            */

+#define SDMMC_STA_RXFIFOF_Pos            (17U)

+#define SDMMC_STA_RXFIFOF_Msk            (0x1UL << SDMMC_STA_RXFIFOF_Pos)      /*!< 0x00020000 */

+#define SDMMC_STA_RXFIFOF                SDMMC_STA_RXFIFOF_Msk                 /*!<Receive FIFO full                             */

+#define SDMMC_STA_TXFIFOE_Pos            (18U)

+#define SDMMC_STA_TXFIFOE_Msk            (0x1UL << SDMMC_STA_TXFIFOE_Pos)      /*!< 0x00040000 */

+#define SDMMC_STA_TXFIFOE                SDMMC_STA_TXFIFOE_Msk                 /*!<Transmit FIFO empty                           */

+#define SDMMC_STA_RXFIFOE_Pos            (19U)

+#define SDMMC_STA_RXFIFOE_Msk            (0x1UL << SDMMC_STA_RXFIFOE_Pos)      /*!< 0x00080000 */

+#define SDMMC_STA_RXFIFOE                SDMMC_STA_RXFIFOE_Msk                 /*!<Receive FIFO empty                            */

+#define SDMMC_STA_BUSYD0_Pos             (20U)

+#define SDMMC_STA_BUSYD0_Msk             (0x1UL << SDMMC_STA_BUSYD0_Pos)       /*!< 0x00100000 */

+#define SDMMC_STA_BUSYD0                 SDMMC_STA_BUSYD0_Msk                  /*!<Inverted value of SDMMC_D0 line (Busy)                                  */

+#define SDMMC_STA_BUSYD0END_Pos          (21U)

+#define SDMMC_STA_BUSYD0END_Msk          (0x1UL << SDMMC_STA_BUSYD0END_Pos)    /*!< 0x00200000 */

+#define SDMMC_STA_BUSYD0END              SDMMC_STA_BUSYD0END_Msk               /*!<End of SDMMC_D0 Busy following a CMD response detected                  */

+#define SDMMC_STA_SDIOIT_Pos             (22U)

+#define SDMMC_STA_SDIOIT_Msk             (0x1UL << SDMMC_STA_SDIOIT_Pos)       /*!< 0x00400000 */

+#define SDMMC_STA_SDIOIT                 SDMMC_STA_SDIOIT_Msk                  /*!<SDIO interrupt received                                                 */

+#define SDMMC_STA_ACKFAIL_Pos            (23U)

+#define SDMMC_STA_ACKFAIL_Msk            (0x1UL << SDMMC_STA_ACKFAIL_Pos)      /*!< 0x00800000 */

+#define SDMMC_STA_ACKFAIL                SDMMC_STA_ACKFAIL_Msk                 /*!<Boot Acknowledgment received (BootAck check fail)                       */

+#define SDMMC_STA_ACKTIMEOUT_Pos         (24U)

+#define SDMMC_STA_ACKTIMEOUT_Msk         (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)   /*!< 0x01000000 */

+#define SDMMC_STA_ACKTIMEOUT             SDMMC_STA_ACKTIMEOUT_Msk              /*!<Boot Acknowledgment timeout                                             */

+#define SDMMC_STA_VSWEND_Pos             (25U)

+#define SDMMC_STA_VSWEND_Msk             (0x1UL << SDMMC_STA_VSWEND_Pos)       /*!< 0x02000000 */

+#define SDMMC_STA_VSWEND                 SDMMC_STA_VSWEND_Msk                  /*!<Voltage switch critical timing section completion                       */

+#define SDMMC_STA_CKSTOP_Pos             (26U)

+#define SDMMC_STA_CKSTOP_Msk             (0x1UL << SDMMC_STA_CKSTOP_Pos)       /*!< 0x04000000 */

+#define SDMMC_STA_CKSTOP                 SDMMC_STA_CKSTOP_Msk                  /*!<SDMMC_CK stopped in Voltage switch procedure                            */

+#define SDMMC_STA_IDMATE_Pos             (27U)

+#define SDMMC_STA_IDMATE_Msk             (0x1UL << SDMMC_STA_IDMATE_Pos)       /*!< 0x08000000 */

+#define SDMMC_STA_IDMATE                 SDMMC_STA_IDMATE_Msk                  /*!<IDMA transfer error                                                     */

+#define SDMMC_STA_IDMABTC_Pos            (28U)

+#define SDMMC_STA_IDMABTC_Msk            (0x1UL << SDMMC_STA_IDMABTC_Pos)      /*!< 0x10000000 */

+#define SDMMC_STA_IDMABTC                SDMMC_STA_IDMABTC_Msk                 /*!<IDMA buffer transfer complete                                           */

+

+/*******************  Bit definition for SDMMC_ICR register  *******************/

+#define SDMMC_ICR_CCRCFAILC_Pos          (0U)

+#define SDMMC_ICR_CCRCFAILC_Msk          (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)    /*!< 0x00000001 */

+#define SDMMC_ICR_CCRCFAILC              SDMMC_ICR_CCRCFAILC_Msk               /*!<CCRCFAIL flag clear bit */

+#define SDMMC_ICR_DCRCFAILC_Pos          (1U)

+#define SDMMC_ICR_DCRCFAILC_Msk          (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)    /*!< 0x00000002 */

+#define SDMMC_ICR_DCRCFAILC              SDMMC_ICR_DCRCFAILC_Msk               /*!<DCRCFAIL flag clear bit */

+#define SDMMC_ICR_CTIMEOUTC_Pos          (2U)

+#define SDMMC_ICR_CTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)    /*!< 0x00000004 */

+#define SDMMC_ICR_CTIMEOUTC              SDMMC_ICR_CTIMEOUTC_Msk               /*!<CTIMEOUT flag clear bit */

+#define SDMMC_ICR_DTIMEOUTC_Pos          (3U)

+#define SDMMC_ICR_DTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)    /*!< 0x00000008 */

+#define SDMMC_ICR_DTIMEOUTC              SDMMC_ICR_DTIMEOUTC_Msk               /*!<DTIMEOUT flag clear bit */

+#define SDMMC_ICR_TXUNDERRC_Pos          (4U)

+#define SDMMC_ICR_TXUNDERRC_Msk          (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)    /*!< 0x00000010 */

+#define SDMMC_ICR_TXUNDERRC              SDMMC_ICR_TXUNDERRC_Msk               /*!<TXUNDERR flag clear bit */

+#define SDMMC_ICR_RXOVERRC_Pos           (5U)

+#define SDMMC_ICR_RXOVERRC_Msk           (0x1UL << SDMMC_ICR_RXOVERRC_Pos)     /*!< 0x00000020 */

+#define SDMMC_ICR_RXOVERRC               SDMMC_ICR_RXOVERRC_Msk                /*!<RXOVERR flag clear bit  */

+#define SDMMC_ICR_CMDRENDC_Pos           (6U)

+#define SDMMC_ICR_CMDRENDC_Msk           (0x1UL << SDMMC_ICR_CMDRENDC_Pos)     /*!< 0x00000040 */

+#define SDMMC_ICR_CMDRENDC               SDMMC_ICR_CMDRENDC_Msk                /*!<CMDREND flag clear bit  */

+#define SDMMC_ICR_CMDSENTC_Pos           (7U)

+#define SDMMC_ICR_CMDSENTC_Msk           (0x1UL << SDMMC_ICR_CMDSENTC_Pos)     /*!< 0x00000080 */

+#define SDMMC_ICR_CMDSENTC               SDMMC_ICR_CMDSENTC_Msk                /*!<CMDSENT flag clear bit  */

+#define SDMMC_ICR_DATAENDC_Pos           (8U)

+#define SDMMC_ICR_DATAENDC_Msk           (0x1UL << SDMMC_ICR_DATAENDC_Pos)     /*!< 0x00000100 */

+#define SDMMC_ICR_DATAENDC               SDMMC_ICR_DATAENDC_Msk                /*!<DATAEND flag clear bit  */

+#define SDMMC_ICR_DHOLDC_Pos             (9U)

+#define SDMMC_ICR_DHOLDC_Msk             (0x1UL << SDMMC_ICR_DHOLDC_Pos)       /*!< 0x00000200 */

+#define SDMMC_ICR_DHOLDC                 SDMMC_ICR_DHOLDC_Msk                  /*!<DHOLD flag clear bit       */

+#define SDMMC_ICR_DBCKENDC_Pos           (10U)

+#define SDMMC_ICR_DBCKENDC_Msk           (0x1UL << SDMMC_ICR_DBCKENDC_Pos)     /*!< 0x00000400 */

+#define SDMMC_ICR_DBCKENDC               SDMMC_ICR_DBCKENDC_Msk                /*!<DBCKEND flag clear bit  */

+#define SDMMC_ICR_DABORTC_Pos            (11U)

+#define SDMMC_ICR_DABORTC_Msk            (0x1UL << SDMMC_ICR_DABORTC_Pos)      /*!< 0x00000800 */

+#define SDMMC_ICR_DABORTC                SDMMC_ICR_DABORTC_Msk                 /*!<DABORTC flag clear bit     */

+#define SDMMC_ICR_BUSYD0ENDC_Pos         (21U)

+#define SDMMC_ICR_BUSYD0ENDC_Msk         (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)   /*!< 0x00200000 */

+#define SDMMC_ICR_BUSYD0ENDC             SDMMC_ICR_BUSYD0ENDC_Msk              /*!<BUSYD0ENDC flag clear bit  */

+#define SDMMC_ICR_SDIOITC_Pos            (22U)

+#define SDMMC_ICR_SDIOITC_Msk            (0x1UL << SDMMC_ICR_SDIOITC_Pos)      /*!< 0x00400000 */

+#define SDMMC_ICR_SDIOITC                SDMMC_ICR_SDIOITC_Msk                 /*!<SDIOIT flag clear bit      */

+#define SDMMC_ICR_ACKFAILC_Pos           (23U)

+#define SDMMC_ICR_ACKFAILC_Msk           (0x1UL << SDMMC_ICR_ACKFAILC_Pos)     /*!< 0x00800000 */

+#define SDMMC_ICR_ACKFAILC               SDMMC_ICR_ACKFAILC_Msk                /*!<ACKFAILC flag clear bit    */

+#define SDMMC_ICR_ACKTIMEOUTC_Pos        (24U)

+#define SDMMC_ICR_ACKTIMEOUTC_Msk        (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)  /*!< 0x01000000 */

+#define SDMMC_ICR_ACKTIMEOUTC            SDMMC_ICR_ACKTIMEOUTC_Msk             /*!<ACKTIMEOUTC flag clear bit */

+#define SDMMC_ICR_VSWENDC_Pos            (25U)

+#define SDMMC_ICR_VSWENDC_Msk            (0x1UL << SDMMC_ICR_VSWENDC_Pos)      /*!< 0x02000000 */

+#define SDMMC_ICR_VSWENDC                SDMMC_ICR_VSWENDC_Msk                 /*!<VSWENDC flag clear bit     */

+#define SDMMC_ICR_CKSTOPC_Pos            (26U)

+#define SDMMC_ICR_CKSTOPC_Msk            (0x1UL << SDMMC_ICR_CKSTOPC_Pos)      /*!< 0x04000000 */

+#define SDMMC_ICR_CKSTOPC                SDMMC_ICR_CKSTOPC_Msk                 /*!<CKSTOPC flag clear bit     */

+#define SDMMC_ICR_IDMATEC_Pos            (27U)

+#define SDMMC_ICR_IDMATEC_Msk            (0x1UL << SDMMC_ICR_IDMATEC_Pos)      /*!< 0x08000000 */

+#define SDMMC_ICR_IDMATEC                SDMMC_ICR_IDMATEC_Msk                 /*!<IDMATEC flag clear bit     */

+#define SDMMC_ICR_IDMABTCC_Pos           (28U)

+#define SDMMC_ICR_IDMABTCC_Msk           (0x1UL << SDMMC_ICR_IDMABTCC_Pos)     /*!< 0x10000000 */

+#define SDMMC_ICR_IDMABTCC               SDMMC_ICR_IDMABTCC_Msk                /*!<IDMABTCC flag clear bit    */

+

+/******************  Bit definition for SDMMC_MASK register  *******************/

+#define SDMMC_MASK_CCRCFAILIE_Pos        (0U)

+#define SDMMC_MASK_CCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)  /*!< 0x00000001 */

+#define SDMMC_MASK_CCRCFAILIE            SDMMC_MASK_CCRCFAILIE_Msk             /*!<Command CRC Fail Interrupt Enable          */

+#define SDMMC_MASK_DCRCFAILIE_Pos        (1U)

+#define SDMMC_MASK_DCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)  /*!< 0x00000002 */

+#define SDMMC_MASK_DCRCFAILIE            SDMMC_MASK_DCRCFAILIE_Msk             /*!<Data CRC Fail Interrupt Enable             */

+#define SDMMC_MASK_CTIMEOUTIE_Pos        (2U)

+#define SDMMC_MASK_CTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)  /*!< 0x00000004 */

+#define SDMMC_MASK_CTIMEOUTIE            SDMMC_MASK_CTIMEOUTIE_Msk             /*!<Command TimeOut Interrupt Enable           */

+#define SDMMC_MASK_DTIMEOUTIE_Pos        (3U)

+#define SDMMC_MASK_DTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)  /*!< 0x00000008 */

+#define SDMMC_MASK_DTIMEOUTIE            SDMMC_MASK_DTIMEOUTIE_Msk             /*!<Data TimeOut Interrupt Enable              */

+#define SDMMC_MASK_TXUNDERRIE_Pos        (4U)

+#define SDMMC_MASK_TXUNDERRIE_Msk        (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)  /*!< 0x00000010 */

+#define SDMMC_MASK_TXUNDERRIE            SDMMC_MASK_TXUNDERRIE_Msk             /*!<Tx FIFO UnderRun Error Interrupt Enable    */

+#define SDMMC_MASK_RXOVERRIE_Pos         (5U)

+#define SDMMC_MASK_RXOVERRIE_Msk         (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)   /*!< 0x00000020 */

+#define SDMMC_MASK_RXOVERRIE             SDMMC_MASK_RXOVERRIE_Msk              /*!<Rx FIFO OverRun Error Interrupt Enable     */

+#define SDMMC_MASK_CMDRENDIE_Pos         (6U)

+#define SDMMC_MASK_CMDRENDIE_Msk         (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)   /*!< 0x00000040 */

+#define SDMMC_MASK_CMDRENDIE             SDMMC_MASK_CMDRENDIE_Msk              /*!<Command Response Received Interrupt Enable */

+#define SDMMC_MASK_CMDSENTIE_Pos         (7U)

+#define SDMMC_MASK_CMDSENTIE_Msk         (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)   /*!< 0x00000080 */

+#define SDMMC_MASK_CMDSENTIE             SDMMC_MASK_CMDSENTIE_Msk              /*!<Command Sent Interrupt Enable              */

+#define SDMMC_MASK_DATAENDIE_Pos         (8U)

+#define SDMMC_MASK_DATAENDIE_Msk         (0x1UL << SDMMC_MASK_DATAENDIE_Pos)   /*!< 0x00000100 */

+#define SDMMC_MASK_DATAENDIE             SDMMC_MASK_DATAENDIE_Msk              /*!<Data End Interrupt Enable                  */

+#define SDMMC_MASK_DHOLDIE_Pos           (9U)

+#define SDMMC_MASK_DHOLDIE_Msk           (0x1UL << SDMMC_MASK_DHOLDIE_Pos)     /*!< 0x00000200 */

+#define SDMMC_MASK_DHOLDIE               SDMMC_MASK_DHOLDIE_Msk                /*!<Data Hold Interrupt Enable                 */

+#define SDMMC_MASK_DBCKENDIE_Pos         (10U)

+#define SDMMC_MASK_DBCKENDIE_Msk         (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)   /*!< 0x00000400 */

+#define SDMMC_MASK_DBCKENDIE             SDMMC_MASK_DBCKENDIE_Msk              /*!<Data Block End Interrupt Enable            */

+#define SDMMC_MASK_DABORTIE_Pos          (11U)

+#define SDMMC_MASK_DABORTIE_Msk          (0x1UL << SDMMC_MASK_DABORTIE_Pos)    /*!< 0x00000800 */

+#define SDMMC_MASK_DABORTIE              SDMMC_MASK_DABORTIE_Msk               /*!<Data transfer aborted interrupt enable     */

+

+#define SDMMC_MASK_TXFIFOHEIE_Pos        (14U)

+#define SDMMC_MASK_TXFIFOHEIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)  /*!< 0x00004000 */

+#define SDMMC_MASK_TXFIFOHEIE            SDMMC_MASK_TXFIFOHEIE_Msk             /*!<Tx FIFO Half Empty interrupt Enable        */

+#define SDMMC_MASK_RXFIFOHFIE_Pos        (15U)

+#define SDMMC_MASK_RXFIFOHFIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)  /*!< 0x00008000 */

+#define SDMMC_MASK_RXFIFOHFIE            SDMMC_MASK_RXFIFOHFIE_Msk             /*!<Rx FIFO Half Full interrupt Enable         */

+

+#define SDMMC_MASK_RXFIFOFIE_Pos         (17U)

+#define SDMMC_MASK_RXFIFOFIE_Msk         (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)   /*!< 0x00020000 */

+#define SDMMC_MASK_RXFIFOFIE             SDMMC_MASK_RXFIFOFIE_Msk              /*!<Rx FIFO Full interrupt Enable              */

+#define SDMMC_MASK_TXFIFOEIE_Pos         (18U)

+#define SDMMC_MASK_TXFIFOEIE_Msk         (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)   /*!< 0x00040000 */

+#define SDMMC_MASK_TXFIFOEIE             SDMMC_MASK_TXFIFOEIE_Msk              /*!<Tx FIFO Empty interrupt Enable             */

+

+#define SDMMC_MASK_BUSYD0ENDIE_Pos       (21U)

+#define SDMMC_MASK_BUSYD0ENDIE_Msk       (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */

+#define SDMMC_MASK_BUSYD0ENDIE           SDMMC_MASK_BUSYD0ENDIE_Msk            /*!<BUSYD0ENDIE interrupt Enable */

+#define SDMMC_MASK_SDIOITIE_Pos           (22U)

+#define SDMMC_MASK_SDIOITIE_Msk           (0x1UL << SDMMC_MASK_SDIOITIE_Pos)     /*!< 0x00400000 */

+#define SDMMC_MASK_SDIOITIE               SDMMC_MASK_SDIOITIE_Msk                /*!<SDMMC Mode Interrupt Received interrupt Enable */

+#define SDMMC_MASK_ACKFAILIE_Pos         (23U)

+#define SDMMC_MASK_ACKFAILIE_Msk         (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)   /*!< 0x00800000 */

+#define SDMMC_MASK_ACKFAILIE             SDMMC_MASK_ACKFAILIE_Msk              /*!<Acknowledgment Fail Interrupt Enable */

+#define SDMMC_MASK_ACKTIMEOUTIE_Pos      (24U)

+#define SDMMC_MASK_ACKTIMEOUTIE_Msk      (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */

+#define SDMMC_MASK_ACKTIMEOUTIE          SDMMC_MASK_ACKTIMEOUTIE_Msk           /*!<Acknowledgment timeout Interrupt Enable */

+#define SDMMC_MASK_VSWENDIE_Pos          (25U)

+#define SDMMC_MASK_VSWENDIE_Msk          (0x1UL << SDMMC_MASK_VSWENDIE_Pos)    /*!< 0x02000000 */

+#define SDMMC_MASK_VSWENDIE              SDMMC_MASK_VSWENDIE_Msk               /*!<Voltage switch critical timing section completion Interrupt Enable */

+#define SDMMC_MASK_CKSTOPIE_Pos          (26U)

+#define SDMMC_MASK_CKSTOPIE_Msk          (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)    /*!< 0x04000000 */

+#define SDMMC_MASK_CKSTOPIE              SDMMC_MASK_CKSTOPIE_Msk               /*!<Voltage Switch clock stopped Interrupt Enable */

+#define SDMMC_MASK_IDMABTCIE_Pos         (28U)

+#define SDMMC_MASK_IDMABTCIE_Msk         (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)   /*!< 0x10000000 */

+#define SDMMC_MASK_IDMABTCIE             SDMMC_MASK_IDMABTCIE_Msk              /*!<IDMA buffer transfer complete Interrupt Enable */

+

+/*****************  Bit definition for SDMMC_ACKTIME register  *****************/

+#define SDMMC_ACKTIME_ACKTIME_Pos        (0U)

+#define SDMMC_ACKTIME_ACKTIME_Msk        (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_ACKTIME_ACKTIME            SDMMC_ACKTIME_ACKTIME_Msk             /*!<Boot acknowledgment timeout period */

+

+/******************  Bit definition for SDMMC_FIFO register  *******************/

+#define SDMMC_FIFO_FIFODATA_Pos          (0U)

+#define SDMMC_FIFO_FIFODATA_Msk          (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_FIFO_FIFODATA              SDMMC_FIFO_FIFODATA_Msk               /*!<Receive and transmit FIFO data */

+

+/******************  Bit definition for SDMMC_IDMACTRL register ****************/

+#define SDMMC_IDMA_IDMAEN_Pos            (0U)

+#define SDMMC_IDMA_IDMAEN_Msk            (0x1UL << SDMMC_IDMA_IDMAEN_Pos)      /*!< 0x00000001 */

+#define SDMMC_IDMA_IDMAEN                SDMMC_IDMA_IDMAEN_Msk                 /*!< Enable the internal DMA of the SDMMC peripheral */

+#define SDMMC_IDMA_IDMABMODE_Pos         (1U)

+#define SDMMC_IDMA_IDMABMODE_Msk         (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)   /*!< 0x00000002 */

+#define SDMMC_IDMA_IDMABMODE             SDMMC_IDMA_IDMABMODE_Msk              /*!< Enable double buffer mode for IDMA */

+#define SDMMC_IDMA_IDMABACT_Pos          (2U)

+#define SDMMC_IDMA_IDMABACT_Msk          (0x1UL << SDMMC_IDMA_IDMABACT_Pos)    /*!< 0x00000004 */

+#define SDMMC_IDMA_IDMABACT              SDMMC_IDMA_IDMABACT_Msk               /*!< Uses buffer 1 when double buffer mode is selected */

+

+/*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/

+#define SDMMC_IDMABSIZE_IDMABNDT_Pos     (5U)

+#define SDMMC_IDMABSIZE_IDMABNDT_Msk     (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */

+#define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */

+

+/*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/

+#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */

+

+/*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/

+#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                        Delay Block Interface (DLYB)                        */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for DLYB_CR register  ********************/

+#define DLYB_CR_DEN_Pos         (0U)

+#define DLYB_CR_DEN_Msk         (0x1UL << DLYB_CR_DEN_Pos)                     /*!< 0x00000001 */

+#define DLYB_CR_DEN             DLYB_CR_DEN_Msk                                /*!<Delay Block enable */

+#define DLYB_CR_SEN_Pos         (1U)

+#define DLYB_CR_SEN_Msk         (0x1UL << DLYB_CR_SEN_Pos)                     /*!< 0x00000002 */

+#define DLYB_CR_SEN             DLYB_CR_SEN_Msk                                /*!<Sampler length enable */

+

+

+/*******************  Bit definition for DLYB_CFGR register  ********************/

+#define DLYB_CFGR_SEL_Pos       (0U)

+#define DLYB_CFGR_SEL_Msk       (0xFUL << DLYB_CFGR_SEL_Pos)                   /*!< 0x0000000F */

+#define DLYB_CFGR_SEL           DLYB_CFGR_SEL_Msk                              /*!<Select the phase for the Output clock[3:0] */

+#define DLYB_CFGR_SEL_0         (0x1UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000001 */

+#define DLYB_CFGR_SEL_1         (0x2UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000002 */

+#define DLYB_CFGR_SEL_2         (0x3UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000003 */

+#define DLYB_CFGR_SEL_3         (0x8UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000008 */

+

+#define DLYB_CFGR_UNIT_Pos      (8U)

+#define DLYB_CFGR_UNIT_Msk      (0x7FUL << DLYB_CFGR_UNIT_Pos)                 /*!< 0x00007F00 */

+#define DLYB_CFGR_UNIT          DLYB_CFGR_UNIT_Msk                             /*!<Delay Defines the delay of a Unit delay cell[6:0] */

+#define DLYB_CFGR_UNIT_0        (0x01UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000100 */

+#define DLYB_CFGR_UNIT_1        (0x02UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000200 */

+#define DLYB_CFGR_UNIT_2        (0x04UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000400 */

+#define DLYB_CFGR_UNIT_3        (0x08UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000800 */

+#define DLYB_CFGR_UNIT_4        (0x10UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00001000 */

+#define DLYB_CFGR_UNIT_5        (0x20UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00002000 */

+#define DLYB_CFGR_UNIT_6        (0x40UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00004000 */

+

+#define DLYB_CFGR_LNG_Pos       (16U)

+#define DLYB_CFGR_LNG_Msk       (0xFFFUL << DLYB_CFGR_LNG_Pos)                 /*!< 0x0FFF0000 */

+#define DLYB_CFGR_LNG           DLYB_CFGR_LNG_Msk                              /*!<Delay line length value[11:0] */

+#define DLYB_CFGR_LNG_0         (0x001UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00010000 */

+#define DLYB_CFGR_LNG_1         (0x002UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00020000 */

+#define DLYB_CFGR_LNG_2         (0x004UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00040000 */

+#define DLYB_CFGR_LNG_3         (0x008UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00080000 */

+#define DLYB_CFGR_LNG_4         (0x010UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00100000 */

+#define DLYB_CFGR_LNG_5         (0x020UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00200000 */

+#define DLYB_CFGR_LNG_6         (0x040UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00400000 */

+#define DLYB_CFGR_LNG_7         (0x080UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00800000 */

+#define DLYB_CFGR_LNG_8         (0x100UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x01000000 */

+#define DLYB_CFGR_LNG_9         (0x200UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x02000000 */

+#define DLYB_CFGR_LNG_10        (0x400UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x04000000 */

+#define DLYB_CFGR_LNG_11        (0x800UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x08000000 */

+

+#define DLYB_CFGR_LNGF_Pos      (31U)

+#define DLYB_CFGR_LNGF_Msk      (0x1UL << DLYB_CFGR_LNGF_Pos)                  /*!< 0x80000000 */

+#define DLYB_CFGR_LNGF          DLYB_CFGR_LNGF_Msk                             /*!<Length valid flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                   Serial Peripheral Interface (SPI/I2S)                    */

+/*                                                                            */

+/******************************************************************************/

+#define SPI_SPI6I2S_SUPPORT       /*!<SPI6 I2S support feature */

+/*******************  Bit definition for SPI_CR1 register  ********************/

+#define SPI_CR1_SPE_Pos             (0U)

+#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000001 */

+#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<Serial Peripheral Enable                         */

+#define SPI_CR1_MASRX_Pos           (8U)

+#define SPI_CR1_MASRX_Msk           (0x1UL << SPI_CR1_MASRX_Pos)               /*!< 0x00000100 */

+#define SPI_CR1_MASRX               SPI_CR1_MASRX_Msk                          /*!<Master automatic SUSP in Receive mode            */

+#define SPI_CR1_CSTART_Pos          (9U)

+#define SPI_CR1_CSTART_Msk          (0x1UL << SPI_CR1_CSTART_Pos)              /*!< 0x00000200 */

+#define SPI_CR1_CSTART              SPI_CR1_CSTART_Msk                         /*!<Master transfer start                            */

+#define SPI_CR1_CSUSP_Pos           (10U)

+#define SPI_CR1_CSUSP_Msk           (0x1UL << SPI_CR1_CSUSP_Pos)               /*!< 0x00000400 */

+#define SPI_CR1_CSUSP               SPI_CR1_CSUSP_Msk                          /*!<Master SUSPend request                           */

+#define SPI_CR1_HDDIR_Pos           (11U)

+#define SPI_CR1_HDDIR_Msk           (0x1UL << SPI_CR1_HDDIR_Pos)               /*!< 0x00000800 */

+#define SPI_CR1_HDDIR               SPI_CR1_HDDIR_Msk                          /*!<Rx/Tx direction at Half-duplex mode              */

+#define SPI_CR1_SSI_Pos             (12U)

+#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00001000 */

+#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal SS signal input level                   */

+#define SPI_CR1_CRC33_17_Pos        (13U)

+#define SPI_CR1_CRC33_17_Msk        (0x1UL << SPI_CR1_CRC33_17_Pos)            /*!< 0x00002000 */

+#define SPI_CR1_CRC33_17             SPI_CR1_CRC33_17_Msk                      /*!<32-bit CRC polynomial configuration              */

+#define SPI_CR1_RCRCINI_Pos         (14U)

+#define SPI_CR1_RCRCINI_Msk         (0x1UL << SPI_CR1_RCRCINI_Pos)             /*!< 0x00004000 */

+#define SPI_CR1_RCRCINI             SPI_CR1_RCRCINI_Msk                        /*!<CRC init pattern control for receiver            */

+#define SPI_CR1_TCRCINI_Pos         (15U)

+#define SPI_CR1_TCRCINI_Msk         (0x1UL << SPI_CR1_TCRCINI_Pos)             /*!< 0x00008000 */

+#define SPI_CR1_TCRCINI             SPI_CR1_TCRCINI_Msk                        /*!<CRC init pattern control for transmitter         */

+#define SPI_CR1_IOLOCK_Pos          (16U)

+#define SPI_CR1_IOLOCK_Msk          (0x1UL << SPI_CR1_IOLOCK_Pos)              /*!< 0x00010000 */

+#define SPI_CR1_IOLOCK              SPI_CR1_IOLOCK_Msk                         /*!<Locking the AF configuration of associated IOs   */

+

+/*******************  Bit definition for SPI_CR2 register  ********************/

+#define SPI_CR2_TSER_Pos            (16U)

+#define SPI_CR2_TSER_Msk            (0xFFFFUL << SPI_CR2_TSER_Pos)             /*!< 0xFFFF0000 */

+#define SPI_CR2_TSER                SPI_CR2_TSER_Msk                           /*!<Number of data transfer extension                */

+#define SPI_CR2_TSIZE_Pos           (0U)

+#define SPI_CR2_TSIZE_Msk           (0xFFFFUL << SPI_CR2_TSIZE_Pos)            /*!< 0x0000FFFF */

+#define SPI_CR2_TSIZE               SPI_CR2_TSIZE_Msk                          /*!<Number of data at current transfer               */

+

+/*******************  Bit definition for SPI_CFG1 register  ********************/

+#define SPI_CFG1_DSIZE_Pos          (0U)

+#define SPI_CFG1_DSIZE_Msk          (0x1FUL << SPI_CFG1_DSIZE_Pos)             /*!< 0x0000001F */

+#define SPI_CFG1_DSIZE              SPI_CFG1_DSIZE_Msk                         /*!<DSIZE[4:0]: Bits number in single SPI data frame */

+#define SPI_CFG1_DSIZE_0            (0x01UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000001 */

+#define SPI_CFG1_DSIZE_1            (0x02UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000002 */

+#define SPI_CFG1_DSIZE_2            (0x04UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000004 */

+#define SPI_CFG1_DSIZE_3            (0x08UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000008 */

+#define SPI_CFG1_DSIZE_4            (0x10UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000010 */

+

+#define SPI_CFG1_FTHLV_Pos          (5U)

+#define SPI_CFG1_FTHLV_Msk          (0xFUL << SPI_CFG1_FTHLV_Pos)              /*!< 0x000001E0 */

+#define SPI_CFG1_FTHLV              SPI_CFG1_FTHLV_Msk                         /*!<FTHVL [3:0]: FIFO threshold level*/

+#define SPI_CFG1_FTHLV_0            (0x1UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000020 */

+#define SPI_CFG1_FTHLV_1            (0x2UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000040 */

+#define SPI_CFG1_FTHLV_2            (0x4UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000080 */

+#define SPI_CFG1_FTHLV_3            (0x8UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000100 */

+

+#define SPI_CFG1_UDRCFG_Pos         (9U)

+#define SPI_CFG1_UDRCFG_Msk         (0x3UL << SPI_CFG1_UDRCFG_Pos)             /*!< 0x00000600 */

+#define SPI_CFG1_UDRCFG             SPI_CFG1_UDRCFG_Msk                        /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */

+#define SPI_CFG1_UDRCFG_0           (0x1UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000200 */

+#define SPI_CFG1_UDRCFG_1           (0x2UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000400 */

+

+

+#define SPI_CFG1_UDRDET_Pos         (11U)

+#define SPI_CFG1_UDRDET_Msk         (0x3UL << SPI_CFG1_UDRDET_Pos)             /*!< 0x00001800 */

+#define SPI_CFG1_UDRDET             SPI_CFG1_UDRDET_Msk                        /*!<UDRDET[1:0]: Detection of underrun condition     */

+#define SPI_CFG1_UDRDET_0           (0x1UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00000800 */

+#define SPI_CFG1_UDRDET_1           (0x2UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00001000 */

+

+#define SPI_CFG1_RXDMAEN_Pos        (14U)

+#define SPI_CFG1_RXDMAEN_Msk        (0x1UL << SPI_CFG1_RXDMAEN_Pos)            /*!< 0x00004000 */

+#define SPI_CFG1_RXDMAEN            SPI_CFG1_RXDMAEN_Msk                       /*!<Rx DMA stream enable                */

+#define SPI_CFG1_TXDMAEN_Pos        (15U)

+#define SPI_CFG1_TXDMAEN_Msk        (0x1UL << SPI_CFG1_TXDMAEN_Pos)            /*!< 0x00008000 */

+#define SPI_CFG1_TXDMAEN            SPI_CFG1_TXDMAEN_Msk                       /*!<Tx DMA stream enable                */

+

+#define SPI_CFG1_CRCSIZE_Pos        (16U)

+#define SPI_CFG1_CRCSIZE_Msk        (0x1FUL << SPI_CFG1_CRCSIZE_Pos)           /*!< 0x001F0000 */

+#define SPI_CFG1_CRCSIZE            SPI_CFG1_CRCSIZE_Msk                       /*!<CRCSIZE [4:0]: Length of CRC frame*/

+#define SPI_CFG1_CRCSIZE_0          (0x01UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00010000 */

+#define SPI_CFG1_CRCSIZE_1          (0x02UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00020000 */

+#define SPI_CFG1_CRCSIZE_2          (0x04UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00040000 */

+#define SPI_CFG1_CRCSIZE_3          (0x08UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00080000 */

+#define SPI_CFG1_CRCSIZE_4          (0x10UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00100000 */

+

+#define SPI_CFG1_CRCEN_Pos          (22U)

+#define SPI_CFG1_CRCEN_Msk          (0x1UL << SPI_CFG1_CRCEN_Pos)              /*!< 0x00400000 */

+#define SPI_CFG1_CRCEN              SPI_CFG1_CRCEN_Msk                         /*!<Hardware CRC computation enable */

+

+#define SPI_CFG1_MBR_Pos            (28U)

+#define SPI_CFG1_MBR_Msk            (0x7UL << SPI_CFG1_MBR_Pos)                /*!< 0x70000000 */

+#define SPI_CFG1_MBR                SPI_CFG1_MBR_Msk                           /*!<Master baud rate                */

+#define SPI_CFG1_MBR_0              (0x1UL << SPI_CFG1_MBR_Pos)                 /*!< 0x10000000 */

+#define SPI_CFG1_MBR_1              (0x2UL << SPI_CFG1_MBR_Pos)                 /*!< 0x20000000 */

+#define SPI_CFG1_MBR_2              (0x4UL << SPI_CFG1_MBR_Pos)                 /*!< 0x40000000 */

+

+/*******************  Bit definition for SPI_CFG2 register  ********************/

+#define SPI_CFG2_MSSI_Pos           (0U)

+#define SPI_CFG2_MSSI_Msk           (0xFUL << SPI_CFG2_MSSI_Pos)               /*!< 0x0000000F */

+#define SPI_CFG2_MSSI               SPI_CFG2_MSSI_Msk                          /*!<Master SS Idleness */

+#define SPI_CFG2_MSSI_0             (0x1UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000001 */

+#define SPI_CFG2_MSSI_1             (0x2UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000002 */

+#define SPI_CFG2_MSSI_2             (0x4UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000004 */

+#define SPI_CFG2_MSSI_3             (0x8UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000008 */

+

+#define SPI_CFG2_MIDI_Pos           (4U)

+#define SPI_CFG2_MIDI_Msk           (0xFUL << SPI_CFG2_MIDI_Pos)               /*!< 0x000000F0 */

+#define SPI_CFG2_MIDI               SPI_CFG2_MIDI_Msk                          /*!<Master Inter-Data Idleness */

+#define SPI_CFG2_MIDI_0             (0x1UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000010 */

+#define SPI_CFG2_MIDI_1             (0x2UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000020 */

+#define SPI_CFG2_MIDI_2             (0x4UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000040 */

+#define SPI_CFG2_MIDI_3             (0x8UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000080 */

+

+#define SPI_CFG2_IOSWP_Pos          (15U)

+#define SPI_CFG2_IOSWP_Msk          (0x1UL << SPI_CFG2_IOSWP_Pos)              /*!< 0x00008000 */

+#define SPI_CFG2_IOSWP              SPI_CFG2_IOSWP_Msk                         /*!<Swap functionality of MISO and MOSI pins */

+

+#define SPI_CFG2_COMM_Pos           (17U)

+#define SPI_CFG2_COMM_Msk           (0x3UL << SPI_CFG2_COMM_Pos)               /*!< 0x00060000 */

+#define SPI_CFG2_COMM               SPI_CFG2_COMM_Msk                          /*!<COMM [1:0]: SPI Communication Mode*/

+#define SPI_CFG2_COMM_0             (0x1UL << SPI_CFG2_COMM_Pos)                /*!< 0x00020000 */

+#define SPI_CFG2_COMM_1             (0x2UL << SPI_CFG2_COMM_Pos)                /*!< 0x00040000 */

+

+#define SPI_CFG2_SP_Pos             (19U)

+#define SPI_CFG2_SP_Msk             (0x7UL << SPI_CFG2_SP_Pos)                 /*!< 0x00380000 */

+#define SPI_CFG2_SP                 SPI_CFG2_SP_Msk                            /*!<SP[2:0]: Serial Protocol */

+#define SPI_CFG2_SP_0               (0x1UL << SPI_CFG2_SP_Pos)                  /*!< 0x00080000 */

+#define SPI_CFG2_SP_1               (0x2UL << SPI_CFG2_SP_Pos)                  /*!< 0x00100000 */

+#define SPI_CFG2_SP_2               (0x4UL << SPI_CFG2_SP_Pos)                  /*!< 0x00200000 */

+

+#define SPI_CFG2_MASTER_Pos         (22U)

+#define SPI_CFG2_MASTER_Msk         (0x1UL << SPI_CFG2_MASTER_Pos)             /*!< 0x00400000 */

+#define SPI_CFG2_MASTER             SPI_CFG2_MASTER_Msk                        /*!<SPI Master           */

+#define SPI_CFG2_LSBFRST_Pos        (23U)

+#define SPI_CFG2_LSBFRST_Msk        (0x1UL << SPI_CFG2_LSBFRST_Pos)            /*!< 0x00800000 */

+#define SPI_CFG2_LSBFRST            SPI_CFG2_LSBFRST_Msk                       /*!<Data frame format               */

+#define SPI_CFG2_CPHA_Pos           (24U)

+#define SPI_CFG2_CPHA_Msk           (0x1UL << SPI_CFG2_CPHA_Pos)               /*!< 0x01000000 */

+#define SPI_CFG2_CPHA               SPI_CFG2_CPHA_Msk                          /*!<Clock Phase      */

+#define SPI_CFG2_CPOL_Pos           (25U)

+#define SPI_CFG2_CPOL_Msk           (0x1UL << SPI_CFG2_CPOL_Pos)               /*!< 0x02000000 */

+#define SPI_CFG2_CPOL               SPI_CFG2_CPOL_Msk                          /*!<Clock Polarity   */

+#define SPI_CFG2_SSM_Pos            (26U)

+#define SPI_CFG2_SSM_Msk            (0x1UL << SPI_CFG2_SSM_Pos)                /*!< 0x04000000 */

+#define SPI_CFG2_SSM                SPI_CFG2_SSM_Msk                           /*!<Software slave management */

+

+#define SPI_CFG2_SSIOP_Pos          (28U)

+#define SPI_CFG2_SSIOP_Msk          (0x1UL << SPI_CFG2_SSIOP_Pos)              /*!< 0x10000000 */

+#define SPI_CFG2_SSIOP              SPI_CFG2_SSIOP_Msk                         /*!<SS input/output polarity */

+#define SPI_CFG2_SSOE_Pos           (29U)

+#define SPI_CFG2_SSOE_Msk           (0x1UL << SPI_CFG2_SSOE_Pos)               /*!< 0x20000000 */

+#define SPI_CFG2_SSOE               SPI_CFG2_SSOE_Msk                          /*!<SS output enable */

+#define SPI_CFG2_SSOM_Pos           (30U)

+#define SPI_CFG2_SSOM_Msk           (0x1UL << SPI_CFG2_SSOM_Pos)               /*!< 0x40000000 */

+#define SPI_CFG2_SSOM               SPI_CFG2_SSOM_Msk                          /*!<SS output management in master mode */

+

+#define SPI_CFG2_AFCNTR_Pos         (31U)

+#define SPI_CFG2_AFCNTR_Msk         (0x1UL << SPI_CFG2_AFCNTR_Pos)             /*!< 0x80000000 */

+#define SPI_CFG2_AFCNTR             SPI_CFG2_AFCNTR_Msk                        /*!<Alternate function GPIOs control */

+

+/*******************  Bit definition for SPI_IER register  ********************/

+#define SPI_IER_RXPIE_Pos           (0U)

+#define SPI_IER_RXPIE_Msk           (0x1UL << SPI_IER_RXPIE_Pos)               /*!< 0x00000001 */

+#define SPI_IER_RXPIE               SPI_IER_RXPIE_Msk                          /*!<RXP Interrupt Enable            */

+#define SPI_IER_TXPIE_Pos           (1U)

+#define SPI_IER_TXPIE_Msk           (0x1UL << SPI_IER_TXPIE_Pos)               /*!< 0x00000002 */

+#define SPI_IER_TXPIE               SPI_IER_TXPIE_Msk                          /*!<TXP interrupt enable            */

+#define SPI_IER_DXPIE_Pos           (2U)

+#define SPI_IER_DXPIE_Msk           (0x1UL << SPI_IER_DXPIE_Pos)               /*!< 0x00000004 */

+#define SPI_IER_DXPIE               SPI_IER_DXPIE_Msk                          /*!<DXP interrupt enable            */

+#define SPI_IER_EOTIE_Pos           (3U)

+#define SPI_IER_EOTIE_Msk           (0x1UL << SPI_IER_EOTIE_Pos)               /*!< 0x00000008 */

+#define SPI_IER_EOTIE               SPI_IER_EOTIE_Msk                          /*!<EOT/SUSP/TXC interrupt enable   */

+#define SPI_IER_TXTFIE_Pos          (4U)

+#define SPI_IER_TXTFIE_Msk          (0x1UL << SPI_IER_TXTFIE_Pos)              /*!< 0x00000010 */

+#define SPI_IER_TXTFIE              SPI_IER_TXTFIE_Msk                         /*!<TXTF interrupt enable           */

+#define SPI_IER_UDRIE_Pos           (5U)

+#define SPI_IER_UDRIE_Msk           (0x1UL << SPI_IER_UDRIE_Pos)               /*!< 0x00000020 */

+#define SPI_IER_UDRIE               SPI_IER_UDRIE_Msk                          /*!<UDR interrupt enable            */

+#define SPI_IER_OVRIE_Pos           (6U)

+#define SPI_IER_OVRIE_Msk           (0x1UL << SPI_IER_OVRIE_Pos)               /*!< 0x00000040 */

+#define SPI_IER_OVRIE               SPI_IER_OVRIE_Msk                          /*!<OVR interrupt enable            */

+#define SPI_IER_CRCEIE_Pos          (7U)

+#define SPI_IER_CRCEIE_Msk          (0x1UL << SPI_IER_CRCEIE_Pos)               /*!< 0x00000080 */

+#define SPI_IER_CRCEIE              SPI_IER_CRCEIE_Msk                          /*!<CRCE interrupt enable           */

+#define SPI_IER_TIFREIE_Pos         (8U)

+#define SPI_IER_TIFREIE_Msk         (0x1UL << SPI_IER_TIFREIE_Pos)             /*!< 0x00000100 */

+#define SPI_IER_TIFREIE             SPI_IER_TIFREIE_Msk                        /*!<TI Frame Error interrupt enable */

+#define SPI_IER_MODFIE_Pos          (9U)

+#define SPI_IER_MODFIE_Msk          (0x1UL << SPI_IER_MODFIE_Pos)              /*!< 0x00000200 */

+#define SPI_IER_MODFIE              SPI_IER_MODFIE_Msk                         /*!<MODF interrupt enable           */

+#define SPI_IER_TSERFIE_Pos         (10U)

+#define SPI_IER_TSERFIE_Msk         (0x1UL << SPI_IER_TSERFIE_Pos)              /*!< 0x00000400 */

+#define SPI_IER_TSERFIE             SPI_IER_TSERFIE_Msk                        /*!<TSERF interrupt enable          */

+

+/*******************  Bit definition for SPI_SR register  ********************/

+#define SPI_SR_RXP_Pos              (0U)

+#define SPI_SR_RXP_Msk              (0x1UL << SPI_SR_RXP_Pos)                  /*!< 0x00000001 */

+#define SPI_SR_RXP                  SPI_SR_RXP_Msk                             /*!<Rx-Packet available             */

+#define SPI_SR_TXP_Pos              (1U)

+#define SPI_SR_TXP_Msk              (0x1UL << SPI_SR_TXP_Pos)                  /*!< 0x00000002 */

+#define SPI_SR_TXP                  SPI_SR_TXP_Msk                             /*!<Tx-Packet space available       */

+#define SPI_SR_DXP_Pos              (2U)

+#define SPI_SR_DXP_Msk              (0x1UL << SPI_SR_DXP_Pos)                  /*!< 0x00000004 */

+#define SPI_SR_DXP                  SPI_SR_DXP_Msk                             /*!<Duplex Packet available         */

+#define SPI_SR_EOT_Pos              (3U)

+#define SPI_SR_EOT_Msk              (0x1UL << SPI_SR_EOT_Pos)                  /*!< 0x00000008 */

+#define SPI_SR_EOT                  SPI_SR_EOT_Msk                             /*!<Duplex Packet available         */

+#define SPI_SR_TXTF_Pos             (4U)

+#define SPI_SR_TXTF_Msk             (0x1UL << SPI_SR_TXTF_Pos)                 /*!< 0x00000010 */

+#define SPI_SR_TXTF                 SPI_SR_TXTF_Msk                            /*!<Transmission Transfer Filled    */

+#define SPI_SR_UDR_Pos              (5U)

+#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000020 */

+#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<UDR at Slave transmission       */

+#define SPI_SR_OVR_Pos              (6U)

+#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */

+#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Rx-Packet available             */

+#define SPI_SR_CRCE_Pos             (7U)

+#define SPI_SR_CRCE_Msk             (0x1UL << SPI_SR_CRCE_Pos)                 /*!< 0x00000080 */

+#define SPI_SR_CRCE                 SPI_SR_CRCE_Msk                            /*!<CRC Error Detected              */

+#define SPI_SR_TIFRE_Pos            (8U)

+#define SPI_SR_TIFRE_Msk            (0x1UL << SPI_SR_TIFRE_Pos)                /*!< 0x00000100 */

+#define SPI_SR_TIFRE                SPI_SR_TIFRE_Msk                           /*!<TI frame format error Detected  */

+#define SPI_SR_MODF_Pos             (9U)

+#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000200 */

+#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode Fault Detected             */

+#define SPI_SR_TSERF_Pos            (10U)

+#define SPI_SR_TSERF_Msk            (0x1UL << SPI_SR_TSERF_Pos)                /*!< 0x00000400 */

+#define SPI_SR_TSERF                SPI_SR_TSERF_Msk                           /*!<Number of SPI data to be transacted reloaded     */

+#define SPI_SR_SUSP_Pos             (11U)

+#define SPI_SR_SUSP_Msk             (0x1UL << SPI_SR_SUSP_Pos)                 /*!< 0x00000800 */

+#define SPI_SR_SUSP                 SPI_SR_SUSP_Msk                            /*!<SUSP is set by hardware  */

+#define SPI_SR_TXC_Pos              (12U)

+#define SPI_SR_TXC_Msk              (0x1UL << SPI_SR_TXC_Pos)                  /*!< 0x00001000 */

+#define SPI_SR_TXC                  SPI_SR_TXC_Msk                             /*!<TxFIFO transmission complete */

+#define SPI_SR_RXPLVL_Pos           (13U)

+#define SPI_SR_RXPLVL_Msk           (0x3UL << SPI_SR_RXPLVL_Pos)               /*!< 0x00006000 */

+#define SPI_SR_RXPLVL               SPI_SR_RXPLVL_Msk                          /*!<RxFIFO Packing Level                             */

+#define SPI_SR_RXPLVL_0             (0x1UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00002000 */

+#define SPI_SR_RXPLVL_1             (0x2UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00004000 */

+#define SPI_SR_RXWNE_Pos            (15U)

+#define SPI_SR_RXWNE_Msk            (0x1UL << SPI_SR_RXWNE_Pos)                /*!< 0x00008000 */

+#define SPI_SR_RXWNE                SPI_SR_RXWNE_Msk                           /*!<Rx FIFO Word Not Empty                           */

+#define SPI_SR_CTSIZE_Pos           (16U)

+#define SPI_SR_CTSIZE_Msk           (0xFFFFUL << SPI_SR_CTSIZE_Pos)            /*!< 0xFFFF0000 */

+#define SPI_SR_CTSIZE               SPI_SR_CTSIZE_Msk                          /*!<Number of data frames remaining in TSIZE         */

+

+/*******************  Bit definition for SPI_IFCR register  ********************/

+#define SPI_IFCR_EOTC_Pos           (3U)

+#define SPI_IFCR_EOTC_Msk           (0x1UL << SPI_IFCR_EOTC_Pos)               /*!< 0x00000008 */

+#define SPI_IFCR_EOTC               SPI_IFCR_EOTC_Msk                          /*!<End Of Transfer flag clear              */

+#define SPI_IFCR_TXTFC_Pos          (4U)

+#define SPI_IFCR_TXTFC_Msk          (0x1UL << SPI_IFCR_TXTFC_Pos)              /*!< 0x00000010 */

+#define SPI_IFCR_TXTFC              SPI_IFCR_TXTFC_Msk                         /*!<Transmission Transfer Filled flag clear */

+#define SPI_IFCR_UDRC_Pos           (5U)

+#define SPI_IFCR_UDRC_Msk           (0x1UL << SPI_IFCR_UDRC_Pos)               /*!< 0x00000020 */

+#define SPI_IFCR_UDRC               SPI_IFCR_UDRC_Msk                          /*!<Underrun flag clear                     */

+#define SPI_IFCR_OVRC_Pos           (6U)

+#define SPI_IFCR_OVRC_Msk           (0x1UL << SPI_IFCR_OVRC_Pos)               /*!< 0x00000040 */

+#define SPI_IFCR_OVRC               SPI_IFCR_OVRC_Msk                          /*!<Overrun flag clear                      */

+#define SPI_IFCR_CRCEC_Pos          (7U)

+#define SPI_IFCR_CRCEC_Msk          (0x1UL << SPI_IFCR_CRCEC_Pos)              /*!< 0x00000080 */

+#define SPI_IFCR_CRCEC              SPI_IFCR_CRCEC_Msk                         /*!<CRC Error flag clear                    */

+#define SPI_IFCR_TIFREC_Pos         (8U)

+#define SPI_IFCR_TIFREC_Msk         (0x1UL << SPI_IFCR_TIFREC_Pos)             /*!< 0x00000100 */

+#define SPI_IFCR_TIFREC             SPI_IFCR_TIFREC_Msk                        /*!<TI frame format error flag clear        */

+#define SPI_IFCR_MODFC_Pos          (9U)

+#define SPI_IFCR_MODFC_Msk          (0x1UL << SPI_IFCR_MODFC_Pos)              /*!< 0x00000200 */

+#define SPI_IFCR_MODFC              SPI_IFCR_MODFC_Msk                         /*!<Mode Fault flag clear                   */

+#define SPI_IFCR_TSERFC_Pos         (10U)

+#define SPI_IFCR_TSERFC_Msk         (0x1UL << SPI_IFCR_TSERFC_Pos)             /*!< 0x00000400 */

+#define SPI_IFCR_TSERFC             SPI_IFCR_TSERFC_Msk                        /*!<TSERFC flag clear                       */

+#define SPI_IFCR_SUSPC_Pos          (11U)

+#define SPI_IFCR_SUSPC_Msk          (0x1UL << SPI_IFCR_SUSPC_Pos)              /*!< 0x00000800 */

+#define SPI_IFCR_SUSPC              SPI_IFCR_SUSPC_Msk                         /*!<SUSPend flag clear                      */

+

+/*******************  Bit definition for SPI_TXDR register  ********************/

+#define SPI_TXDR_TXDR_Pos           (0U)

+#define SPI_TXDR_TXDR_Msk           (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)        /*!< 0xFFFFFFFF */

+#define SPI_TXDR_TXDR               SPI_TXDR_TXDR_Msk                          /* Transmit Data Register */

+

+/*******************  Bit definition for SPI_RXDR register  ********************/

+#define SPI_RXDR_RXDR_Pos           (0U)

+#define SPI_RXDR_RXDR_Msk           (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)        /*!< 0xFFFFFFFF */

+#define SPI_RXDR_RXDR               SPI_RXDR_RXDR_Msk                          /* Receive Data Register  */

+

+/*******************  Bit definition for SPI_CRCPOLY register  ********************/

+#define SPI_CRCPOLY_CRCPOLY_Pos     (0U)

+#define SPI_CRCPOLY_CRCPOLY_Msk     (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)  /*!< 0xFFFFFFFF */

+#define SPI_CRCPOLY_CRCPOLY         SPI_CRCPOLY_CRCPOLY_Msk                    /* CRC Polynomial register  */

+

+/*******************  Bit definition for SPI_TXCRC register  ********************/

+#define SPI_TXCRC_TXCRC_Pos         (0U)

+#define SPI_TXCRC_TXCRC_Msk         (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_TXCRC_TXCRC             SPI_TXCRC_TXCRC_Msk                        /* CRCRegister for transmitter */

+

+/*******************  Bit definition for SPI_RXCRC register  ********************/

+#define SPI_RXCRC_RXCRC_Pos         (0U)

+#define SPI_RXCRC_RXCRC_Msk         (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_RXCRC_RXCRC             SPI_RXCRC_RXCRC_Msk                        /* CRCRegister for receiver */

+

+/*******************  Bit definition for SPI_UDRDR register  ********************/

+#define SPI_UDRDR_UDRDR_Pos         (0U)

+#define SPI_UDRDR_UDRDR_Msk         (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_UDRDR_UDRDR             SPI_UDRDR_UDRDR_Msk                        /* Data at slave underrun condition */

+

+/******************  Bit definition for SPI_I2SCFGR register  *****************/

+#define SPI_I2SCFGR_I2SMOD_Pos      (0U)

+#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000001 */

+#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */

+#define SPI_I2SCFGR_I2SCFG_Pos      (1U)

+#define SPI_I2SCFGR_I2SCFG_Msk      (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x0000000E */

+#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[2:0] I2S configuration mode                */

+#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000002 */

+#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000004 */

+#define SPI_I2SCFGR_I2SCFG_2        (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000008 */

+#define SPI_I2SCFGR_I2SSTD_Pos      (4U)

+#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */

+#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] I2S standard selection                */

+#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */

+#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */

+#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)

+#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */

+#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                         */

+#define SPI_I2SCFGR_DATLEN_Pos      (8U)

+#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000300 */

+#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] Data length to be transferred         */

+#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000100 */

+#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000200 */

+#define SPI_I2SCFGR_CHLEN_Pos       (10U)

+#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000400 */

+#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */

+#define SPI_I2SCFGR_CKPOL_Pos       (11U)

+#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000800 */

+#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<Steady state clock polarity                       */

+#define SPI_I2SCFGR_FIXCH_Pos       (12U)

+#define SPI_I2SCFGR_FIXCH_Msk       (0x1UL << SPI_I2SCFGR_FIXCH_Pos)           /*!< 0x00001000 */

+#define SPI_I2SCFGR_FIXCH           SPI_I2SCFGR_FIXCH_Msk                      /*!<Fixed channel length in SLAVE                     */

+#define SPI_I2SCFGR_WSINV_Pos       (13U)

+#define SPI_I2SCFGR_WSINV_Msk       (0x1UL << SPI_I2SCFGR_WSINV_Pos)           /*!< 0x00002000 */

+#define SPI_I2SCFGR_WSINV           SPI_I2SCFGR_WSINV_Msk                      /*!<Word select inversion                             */

+#define SPI_I2SCFGR_DATFMT_Pos      (14U)

+#define SPI_I2SCFGR_DATFMT_Msk      (0x1UL << SPI_I2SCFGR_DATFMT_Pos)          /*!< 0x00004000 */

+#define SPI_I2SCFGR_DATFMT          SPI_I2SCFGR_DATFMT_Msk                     /*!<Data format                                       */

+#define SPI_I2SCFGR_I2SDIV_Pos      (16U)

+#define SPI_I2SCFGR_I2SDIV_Msk      (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)         /*!< 0x00FF0000 */

+#define SPI_I2SCFGR_I2SDIV          SPI_I2SCFGR_I2SDIV_Msk                     /*!<I2S Linear prescaler */

+#define SPI_I2SCFGR_ODD_Pos         (24U)

+#define SPI_I2SCFGR_ODD_Msk         (0x1UL << SPI_I2SCFGR_ODD_Pos)             /*!< 0x01000000 */

+#define SPI_I2SCFGR_ODD             SPI_I2SCFGR_ODD_Msk                        /*!<Odd factor for the prescaler */

+#define SPI_I2SCFGR_MCKOE_Pos       (25U)

+#define SPI_I2SCFGR_MCKOE_Msk       (0x1UL << SPI_I2SCFGR_MCKOE_Pos)           /*!< 0x02000000 */

+#define SPI_I2SCFGR_MCKOE           SPI_I2SCFGR_MCKOE_Msk                      /*!<Master Clock Output Enable */

+

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                 SYSCFG                                     */

+/*                                                                            */

+/******************************************************************************/

+

+/******************  Bit definition for SYSCFG_PMCR register  ******************/

+#define SYSCFG_PMCR_I2C1_FMP_Pos        (0U)

+#define SYSCFG_PMCR_I2C1_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos)    /*!< 0x00000001 */

+#define SYSCFG_PMCR_I2C1_FMP            SYSCFG_PMCR_I2C1_FMP_Msk               /*!< I2C1 Fast mode plus */

+#define SYSCFG_PMCR_I2C2_FMP_Pos        (1U)

+#define SYSCFG_PMCR_I2C2_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos)    /*!< 0x00000002 */

+#define SYSCFG_PMCR_I2C2_FMP            SYSCFG_PMCR_I2C2_FMP_Msk               /*!< I2C2 Fast mode plus */

+#define SYSCFG_PMCR_I2C3_FMP_Pos        (2U)

+#define SYSCFG_PMCR_I2C3_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos)    /*!< 0x00000004 */

+#define SYSCFG_PMCR_I2C3_FMP            SYSCFG_PMCR_I2C3_FMP_Msk               /*!< I2C3 Fast mode plus */

+#define SYSCFG_PMCR_I2C4_FMP_Pos        (3U)

+#define SYSCFG_PMCR_I2C4_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos)    /*!< 0x00000008 */

+#define SYSCFG_PMCR_I2C4_FMP            SYSCFG_PMCR_I2C4_FMP_Msk               /*!< I2C4 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB6_FMP_Pos     (4U)

+#define SYSCFG_PMCR_I2C_PB6_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */

+#define SYSCFG_PMCR_I2C_PB6_FMP         SYSCFG_PMCR_I2C_PB6_FMP_Msk            /*!< I2C PB6 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB7_FMP_Pos     (5U)

+#define SYSCFG_PMCR_I2C_PB7_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */

+#define SYSCFG_PMCR_I2C_PB7_FMP         SYSCFG_PMCR_I2C_PB7_FMP_Msk            /*!< I2C PB7 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB8_FMP_Pos     (6U)

+#define SYSCFG_PMCR_I2C_PB8_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */

+#define SYSCFG_PMCR_I2C_PB8_FMP         SYSCFG_PMCR_I2C_PB8_FMP_Msk            /*!< I2C PB8 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB9_FMP_Pos     (7U)

+#define SYSCFG_PMCR_I2C_PB9_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */

+#define SYSCFG_PMCR_I2C_PB9_FMP         SYSCFG_PMCR_I2C_PB9_FMP_Msk            /*!< I2C PB9 Fast mode plus */

+#define SYSCFG_PMCR_PA0SO_Pos           (24U)

+#define SYSCFG_PMCR_PA0SO_Msk           (0x1UL << SYSCFG_PMCR_PA0SO_Pos)       /*!< 0x01000000 */

+#define SYSCFG_PMCR_PA0SO               SYSCFG_PMCR_PA0SO_Msk                  /*!< PA0 Switch Open */

+#define SYSCFG_PMCR_PA1SO_Pos           (25U)

+#define SYSCFG_PMCR_PA1SO_Msk           (0x1UL << SYSCFG_PMCR_PA1SO_Pos)       /*!< 0x02000000 */

+#define SYSCFG_PMCR_PA1SO               SYSCFG_PMCR_PA1SO_Msk                  /*!< PA1 Switch Open */

+#define SYSCFG_PMCR_PC2SO_Pos           (26U)

+#define SYSCFG_PMCR_PC2SO_Msk           (0x1UL << SYSCFG_PMCR_PC2SO_Pos)       /*!< 0x04000000 */

+#define SYSCFG_PMCR_PC2SO               SYSCFG_PMCR_PC2SO_Msk                  /*!< PC2 Switch Open */

+#define SYSCFG_PMCR_PC3SO_Pos           (27U)

+#define SYSCFG_PMCR_PC3SO_Msk           (0x1UL << SYSCFG_PMCR_PC3SO_Pos)       /*!< 0x08000000 */

+#define SYSCFG_PMCR_PC3SO               SYSCFG_PMCR_PC3SO_Msk                  /*!< PC3 Switch Open */

+

+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/

+#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)

+#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */

+#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)

+#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */

+#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)

+#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000F00 */

+#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */

+#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)

+#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x0000F000 */

+#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */

+/**

+  * @brief   EXTI0 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */

+

+/**

+  * @brief   EXTI1 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */

+/**

+  * @brief   EXTI2 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */

+

+/**

+  * @brief   EXTI3 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/

+#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)

+#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */

+#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)

+#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */

+#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)

+#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000F00 */

+#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */

+#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)

+#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x0000F000 */

+#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */

+/**

+  * @brief   EXTI4 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */

+/**

+  * @brief   EXTI5 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */

+/**

+  * @brief   EXTI6 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */

+

+/**

+  * @brief   EXTI7 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/

+#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)

+#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */

+#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)

+#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */

+#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)

+#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000F00 */

+#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */

+#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)

+#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x0000F000 */

+#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */

+

+/**

+  * @brief   EXTI8 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */

+

+/**

+  * @brief   EXTI9 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */

+

+/**

+  * @brief   EXTI10 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */

+

+/**

+  * @brief   EXTI11 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/

+#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)

+#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x0000000F */

+#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */

+#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)

+#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x000000F0 */

+#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */

+#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)

+#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000F00 */

+#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */

+#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)

+#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x0000F000 */

+#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */

+/**

+  * @brief   EXTI12 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */

+/**

+  * @brief   EXTI13 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */

+/**

+  * @brief   EXTI14 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */

+/**

+  * @brief   EXTI15 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */

+

+/******************  Bit definition for SYSCFG_CFGR register  ******************/

+#define SYSCFG_CFGR_PVDL_Pos            (2U)

+#define SYSCFG_CFGR_PVDL_Msk            (0x1UL << SYSCFG_CFGR_PVDL_Pos)        /*!< 0x00000004 */

+#define SYSCFG_CFGR_PVDL                SYSCFG_CFGR_PVDL_Msk                   /*!<PVD lock enable bit */

+#define SYSCFG_CFGR_FLASHL_Pos          (3U)

+#define SYSCFG_CFGR_FLASHL_Msk          (0x1UL << SYSCFG_CFGR_FLASHL_Pos)      /*!< 0x00000008 */

+#define SYSCFG_CFGR_FLASHL              SYSCFG_CFGR_FLASHL_Msk                 /*!<FLASH double ECC error lock bit */

+#define SYSCFG_CFGR_CM7L_Pos            (6U)

+#define SYSCFG_CFGR_CM7L_Msk            (0x1UL << SYSCFG_CFGR_CM7L_Pos)        /*!< 0x00000040 */

+#define SYSCFG_CFGR_CM7L                SYSCFG_CFGR_CM7L_Msk                   /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */

+#define SYSCFG_CFGR_DTCML_Pos           (13U)

+#define SYSCFG_CFGR_DTCML_Msk           (0x1UL << SYSCFG_CFGR_DTCML_Pos)       /*!< 0x00002000 */

+#define SYSCFG_CFGR_DTCML               SYSCFG_CFGR_DTCML_Msk                  /*!<DTCM double ECC error lock bit */

+#define SYSCFG_CFGR_ITCML_Pos           (14U)

+#define SYSCFG_CFGR_ITCML_Msk           (0x1UL << SYSCFG_CFGR_ITCML_Pos)       /*!< 0x00004000 */

+#define SYSCFG_CFGR_ITCML               SYSCFG_CFGR_ITCML_Msk                  /*!<ITCM double ECC error lock bit */

+/******************  Bit definition for SYSCFG_CCCSR register  ******************/

+#define SYSCFG_CCCSR_EN_Pos             (0U)

+#define SYSCFG_CCCSR_EN_Msk             (0x1UL << SYSCFG_CCCSR_EN_Pos)         /*!< 0x00000001 */

+#define SYSCFG_CCCSR_EN                 SYSCFG_CCCSR_EN_Msk                    /*!< I/O compensation cell enable */

+#define SYSCFG_CCCSR_CS_Pos             (1U)

+#define SYSCFG_CCCSR_CS_Msk             (0x1UL << SYSCFG_CCCSR_CS_Pos)         /*!< 0x00000002 */

+#define SYSCFG_CCCSR_CS                 SYSCFG_CCCSR_CS_Msk                    /*!< I/O compensation cell code selection */

+#define SYSCFG_CCCSR_CS_MMC_Pos         (3U)

+#define SYSCFG_CCCSR_CS_MMC_Msk         (0x1UL << SYSCFG_CCCSR_CS_MMC_Pos)         /*!< 0x00000004 */

+#define SYSCFG_CCCSR_CS_MMC             SYSCFG_CCCSR_CS_MMC_Msk                    /*!< I/O compensation cell code selection */

+#define SYSCFG_CCCSR_READY_Pos          (8U)

+#define SYSCFG_CCCSR_READY_Msk          (0x1UL << SYSCFG_CCCSR_READY_Pos)      /*!< 0x00000100 */

+#define SYSCFG_CCCSR_READY              SYSCFG_CCCSR_READY_Msk                 /*!< I/O compensation cell ready flag */

+#define SYSCFG_CCCSR_HSLV0_Pos           (16U)

+#define SYSCFG_CCCSR_HSLV0_Msk           (0x1UL << SYSCFG_CCCSR_HSLV0_Pos)       /*!< 0x00010000 */

+#define SYSCFG_CCCSR_HSLV0               SYSCFG_CCCSR_HSLV0_Msk                  /*!< High-speed at low-voltage */

+#define SYSCFG_CCCSR_HSLV1_Pos           (17U)

+#define SYSCFG_CCCSR_HSLV1_Msk           (0x1UL << SYSCFG_CCCSR_HSLV1_Pos)       /*!< 0x00020000 */

+#define SYSCFG_CCCSR_HSLV1               SYSCFG_CCCSR_HSLV1_Msk                  /*!< High-speed at low-voltage */

+#define SYSCFG_CCCSR_HSLV2_Pos           (18U)

+#define SYSCFG_CCCSR_HSLV2_Msk           (0x1UL << SYSCFG_CCCSR_HSLV2_Pos)       /*!< 0x00040000 */

+#define SYSCFG_CCCSR_HSLV2               SYSCFG_CCCSR_HSLV2_Msk                  /*!< High-speed at low-voltage */

+#define SYSCFG_CCCSR_HSLV3_Pos           (19U)

+#define SYSCFG_CCCSR_HSLV3_Msk           (0x1UL << SYSCFG_CCCSR_HSLV3_Pos)       /*!< 0x00080000 */

+#define SYSCFG_CCCSR_HSLV3               SYSCFG_CCCSR_HSLV3_Msk                  /*!< High-speed at low-voltage */

+/******************  Bit definition for SYSCFG_CCVR register  *******************/

+#define SYSCFG_CCVR_NCV_Pos             (0U)

+#define SYSCFG_CCVR_NCV_Msk             (0xFUL << SYSCFG_CCVR_NCV_Pos)         /*!< 0x0000000F */

+#define SYSCFG_CCVR_NCV                 SYSCFG_CCVR_NCV_Msk                    /*!< NMOS compensation value */

+#define SYSCFG_CCVR_PCV_Pos             (4U)

+#define SYSCFG_CCVR_PCV_Msk             (0xFUL << SYSCFG_CCVR_PCV_Pos)         /*!< 0x000000F0 */

+#define SYSCFG_CCVR_PCV                 SYSCFG_CCVR_PCV_Msk                    /*!< PMOS compensation value */

+

+/******************  Bit definition for SYSCFG_CCCR register  *******************/

+#define SYSCFG_CCCR_NCC_Pos             (0U)

+#define SYSCFG_CCCR_NCC_Msk             (0xFUL << SYSCFG_CCCR_NCC_Pos)         /*!< 0x0000000F */

+#define SYSCFG_CCCR_NCC                 SYSCFG_CCCR_NCC_Msk                    /*!< NMOS compensation code */

+#define SYSCFG_CCCR_PCC_Pos             (4U)

+#define SYSCFG_CCCR_PCC_Msk             (0xFUL << SYSCFG_CCCR_PCC_Pos)         /*!< 0x000000F0 */

+#define SYSCFG_CCCR_PCC                 SYSCFG_CCCR_PCC_Msk                    /*!< PMOS compensation code */

+#define SYSCFG_CCCR_NCC_MMC_Pos         (8U)

+#define SYSCFG_CCCR_NCC_MMC_Msk         (0xFUL << SYSCFG_CCCR_NCC_MMC_Pos)     /*!< 0x00000F00 */

+#define SYSCFG_CCCR_NCC_MMC             SYSCFG_CCCR_NCC_MMC_Msk                /*!< NMOS compensation code */

+#define SYSCFG_CCCR_PCC_MMC_Pos         (12U)

+#define SYSCFG_CCCR_PCC_MMC_Msk         (0xFUL << SYSCFG_CCCR_PCC_MMC_Pos)     /*!< 0x0000F000 */

+#define SYSCFG_CCCR_PCC_MMC             SYSCFG_CCCR_PCC_MMC_Msk                /*!< PMOS compensation code */

+/******************************************************************************/

+/*                                                                            */

+/*                    Digital Temperature Sensor (DTS)                        */

+/*                                                                            */

+/******************************************************************************/

+

+/******************  Bit definition for DTS_CFGR1 register  ******************/

+#define DTS_CFGR1_TS1_EN_Pos               (0U)

+#define DTS_CFGR1_TS1_EN_Msk               (0x1UL << DTS_CFGR1_TS1_EN_Pos) /*!< 0x00000001 */

+#define DTS_CFGR1_TS1_EN                   DTS_CFGR1_TS1_EN_Msk        /*!< DTS Enable */

+#define DTS_CFGR1_TS1_START_Pos            (4U)

+#define DTS_CFGR1_TS1_START_Msk            (0x1UL << DTS_CFGR1_TS1_START_Pos) /*!< 0x00000010 */

+#define DTS_CFGR1_TS1_START                DTS_CFGR1_TS1_START_Msk     /*!< Proceed to a frequency measurement on DTS */

+#define DTS_CFGR1_TS1_INTRIG_SEL_Pos       (8U)

+#define DTS_CFGR1_TS1_INTRIG_SEL_Msk       (0xFUL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000F00 */

+#define DTS_CFGR1_TS1_INTRIG_SEL           DTS_CFGR1_TS1_INTRIG_SEL_Msk /*!< Input triggers selection bits [3:0] for DTS */

+#define DTS_CFGR1_TS1_INTRIG_SEL_0         (0x1UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000100 */

+#define DTS_CFGR1_TS1_INTRIG_SEL_1         (0x2UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000200 */

+#define DTS_CFGR1_TS1_INTRIG_SEL_2         (0x4UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000400 */

+#define DTS_CFGR1_TS1_INTRIG_SEL_3         (0x8UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000800 */

+#define DTS_CFGR1_TS1_SMP_TIME_Pos         (16U)

+#define DTS_CFGR1_TS1_SMP_TIME_Msk         (0xFUL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x000F0000 */

+#define DTS_CFGR1_TS1_SMP_TIME             DTS_CFGR1_TS1_SMP_TIME_Msk  /*!< Sample time [3:0] for DTS */

+#define DTS_CFGR1_TS1_SMP_TIME_0           (0x1UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00010000 */

+#define DTS_CFGR1_TS1_SMP_TIME_1           (0x2UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00020000 */

+#define DTS_CFGR1_TS1_SMP_TIME_2           (0x4UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00040000 */

+#define DTS_CFGR1_TS1_SMP_TIME_3           (0x8UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00080000 */

+#define DTS_CFGR1_REFCLK_SEL_Pos           (20U)

+#define DTS_CFGR1_REFCLK_SEL_Msk           (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */

+#define DTS_CFGR1_REFCLK_SEL               DTS_CFGR1_REFCLK_SEL_Msk    /*!< Reference Clock Selection */

+#define DTS_CFGR1_Q_MEAS_OPT_Pos           (21U)

+#define DTS_CFGR1_Q_MEAS_OPT_Msk           (0x1UL << DTS_CFGR1_Q_MEAS_OPT_Pos) /*!< 0x00200000 */

+#define DTS_CFGR1_Q_MEAS_OPT               DTS_CFGR1_Q_MEAS_OPT_Msk    /*!< Quick measure option bit  */

+#define DTS_CFGR1_HSREF_CLK_DIV_Pos        (24U)

+#define DTS_CFGR1_HSREF_CLK_DIV_Msk        (0x7FUL << DTS_CFGR1_HSREF_CLK_DIV_Pos) /*!< 0x7F000000 */

+#define DTS_CFGR1_HSREF_CLK_DIV            DTS_CFGR1_HSREF_CLK_DIV_Msk /*!< High Speed Clock Divider Ratio [6:0]*/

+

+/******************  Bit definition for DTS_T0VALR1 register  ******************/

+#define DTS_T0VALR1_TS1_FMT0_Pos           (0U)

+#define DTS_T0VALR1_TS1_FMT0_Msk           (0xFFFFUL << DTS_T0VALR1_TS1_FMT0_Pos) /*!< 0x0000FFFF */

+#define DTS_T0VALR1_TS1_FMT0               DTS_T0VALR1_TS1_FMT0_Msk    /*!< Engineering value of the measured frequency at T0 for DTS */

+#define DTS_T0VALR1_TS1_T0_Pos             (16U)

+#define DTS_T0VALR1_TS1_T0_Msk             (0x3UL << DTS_T0VALR1_TS1_T0_Pos) /*!< 0x00030000 */

+#define DTS_T0VALR1_TS1_T0                 DTS_T0VALR1_TS1_T0_Msk      /*!< Engineering value of the DTSerature T0 for DTS */

+

+/******************  Bit definition for DTS_RAMPVALR register  ******************/

+#define DTS_RAMPVALR_TS1_RAMP_COEFF_Pos    (0U)

+#define DTS_RAMPVALR_TS1_RAMP_COEFF_Msk    (0xFFFFUL << DTS_RAMPVALR_TS1_RAMP_COEFF_Pos) /*!< 0x0000FFFF */

+#define DTS_RAMPVALR_TS1_RAMP_COEFF        DTS_RAMPVALR_TS1_RAMP_COEFF_Msk /*!< Engineering value of the ramp coefficient for DTS */

+

+/******************  Bit definition for DTS_ITR1 register      ******************/

+#define DTS_ITR1_TS1_LITTHD_Pos            (0U)

+#define DTS_ITR1_TS1_LITTHD_Msk            (0xFFFFUL << DTS_ITR1_TS1_LITTHD_Pos) /*!< 0x0000FFFF */

+#define DTS_ITR1_TS1_LITTHD                DTS_ITR1_TS1_LITTHD_Msk     /*!< Low interrupt threshold[15:0] for DTS */

+#define DTS_ITR1_TS1_HITTHD_Pos            (16U)

+#define DTS_ITR1_TS1_HITTHD_Msk            (0xFFFFUL << DTS_ITR1_TS1_HITTHD_Pos) /*!< 0xFFFF0000 */

+#define DTS_ITR1_TS1_HITTHD                DTS_ITR1_TS1_HITTHD_Msk     /*!< High interrupt threshold[15:0] for DTS */

+

+/******************  Bit definition for DTS_DR register        ******************/

+#define DTS_DR_TS1_MFREQ_Pos               (0U)

+#define DTS_DR_TS1_MFREQ_Msk               (0xFFFFUL << DTS_DR_TS1_MFREQ_Pos) /*!< 0x0000FFFF */

+#define DTS_DR_TS1_MFREQ                   DTS_DR_TS1_MFREQ_Msk        /*!< Measured Frequency[15:0] for DTS */

+

+/******************  Bit definition for DTS_SR register        ******************/

+#define DTS_SR_TS1_ITEF_Pos                (0U)

+#define DTS_SR_TS1_ITEF_Msk                (0x1UL << DTS_SR_TS1_ITEF_Pos) /*!< 0x00000001 */

+#define DTS_SR_TS1_ITEF                    DTS_SR_TS1_ITEF_Msk         /*!< Interrupt flag for end of measure for DTS */

+#define DTS_SR_TS1_ITLF_Pos                (1U)

+#define DTS_SR_TS1_ITLF_Msk                (0x1UL << DTS_SR_TS1_ITLF_Pos) /*!< 0x00000002 */

+#define DTS_SR_TS1_ITLF                    DTS_SR_TS1_ITLF_Msk         /*!< Interrupt flag for low threshold for DTS  */

+#define DTS_SR_TS1_ITHF_Pos                (2U)

+#define DTS_SR_TS1_ITHF_Msk                (0x1UL << DTS_SR_TS1_ITHF_Pos) /*!< 0x00000004 */

+#define DTS_SR_TS1_ITHF                    DTS_SR_TS1_ITHF_Msk         /*!< Interrupt flag for high threshold for DTS */

+#define DTS_SR_TS1_AITEF_Pos               (4U)

+#define DTS_SR_TS1_AITEF_Msk               (0x1UL << DTS_SR_TS1_AITEF_Pos) /*!< 0x00000010 */

+#define DTS_SR_TS1_AITEF                   DTS_SR_TS1_AITEF_Msk        /*!< Asynchronous interrupt flag for end of measure for DTS */

+#define DTS_SR_TS1_AITLF_Pos               (5U)

+#define DTS_SR_TS1_AITLF_Msk               (0x1UL << DTS_SR_TS1_AITLF_Pos) /*!< 0x00000020 */

+#define DTS_SR_TS1_AITLF                   DTS_SR_TS1_AITLF_Msk        /*!< Asynchronous interrupt flag for low threshold for DTS  */

+#define DTS_SR_TS1_AITHF_Pos               (6U)

+#define DTS_SR_TS1_AITHF_Msk               (0x1UL << DTS_SR_TS1_AITHF_Pos) /*!< 0x00000040 */

+#define DTS_SR_TS1_AITHF                   DTS_SR_TS1_AITHF_Msk        /*!< Asynchronous interrupt flag for high threshold for DTS */

+#define DTS_SR_TS1_RDY_Pos                 (15U)

+#define DTS_SR_TS1_RDY_Msk                 (0x1UL << DTS_SR_TS1_RDY_Pos) /*!< 0x00008000 */

+#define DTS_SR_TS1_RDY                     DTS_SR_TS1_RDY_Msk          /*!< DTS ready flag */

+

+/******************  Bit definition for DTS_ITENR register      ******************/

+#define DTS_ITENR_TS1_ITEEN_Pos            (0U)

+#define DTS_ITENR_TS1_ITEEN_Msk            (0x1UL << DTS_ITENR_TS1_ITEEN_Pos) /*!< 0x00000001 */

+#define DTS_ITENR_TS1_ITEEN                DTS_ITENR_TS1_ITEEN_Msk     /*!< Enable interrupt flag for end of measure for DTS */

+#define DTS_ITENR_TS1_ITLEN_Pos            (1U)

+#define DTS_ITENR_TS1_ITLEN_Msk            (0x1UL << DTS_ITENR_TS1_ITLEN_Pos) /*!< 0x00000002 */

+#define DTS_ITENR_TS1_ITLEN                DTS_ITENR_TS1_ITLEN_Msk     /*!< Enable interrupt flag for low threshold for DTS  */

+#define DTS_ITENR_TS1_ITHEN_Pos            (2U)

+#define DTS_ITENR_TS1_ITHEN_Msk            (0x1UL << DTS_ITENR_TS1_ITHEN_Pos) /*!< 0x00000004 */

+#define DTS_ITENR_TS1_ITHEN                DTS_ITENR_TS1_ITHEN_Msk     /*!< Enable interrupt flag for high threshold for DTS */

+#define DTS_ITENR_TS1_AITEEN_Pos           (4U)

+#define DTS_ITENR_TS1_AITEEN_Msk           (0x1UL << DTS_ITENR_TS1_AITEEN_Pos) /*!< 0x00000010 */

+#define DTS_ITENR_TS1_AITEEN               DTS_ITENR_TS1_AITEEN_Msk    /*!< Enable asynchronous interrupt flag for end of measure for DTS */

+#define DTS_ITENR_TS1_AITLEN_Pos           (5U)

+#define DTS_ITENR_TS1_AITLEN_Msk           (0x1UL << DTS_ITENR_TS1_AITLEN_Pos) /*!< 0x00000020 */

+#define DTS_ITENR_TS1_AITLEN               DTS_ITENR_TS1_AITLEN_Msk    /*!< Enable Asynchronous interrupt flag for low threshold for DTS  */

+#define DTS_ITENR_TS1_AITHEN_Pos           (6U)

+#define DTS_ITENR_TS1_AITHEN_Msk           (0x1UL << DTS_ITENR_TS1_AITHEN_Pos) /*!< 0x00000040 */

+#define DTS_ITENR_TS1_AITHEN               DTS_ITENR_TS1_AITHEN_Msk    /*!< Enable asynchronous interrupt flag for high threshold for DTS */

+

+/******************  Bit definition for DTS_ICIFR register      ******************/

+#define DTS_ICIFR_TS1_CITEF_Pos            (0U)

+#define DTS_ICIFR_TS1_CITEF_Msk            (0x1UL << DTS_ICIFR_TS1_CITEF_Pos) /*!< 0x00000001 */

+#define DTS_ICIFR_TS1_CITEF                DTS_ICIFR_TS1_CITEF_Msk     /*!< Clear the IT flag for End Of Measure for DTS */

+#define DTS_ICIFR_TS1_CITLF_Pos            (1U)

+#define DTS_ICIFR_TS1_CITLF_Msk            (0x1UL << DTS_ICIFR_TS1_CITLF_Pos) /*!< 0x00000002 */

+#define DTS_ICIFR_TS1_CITLF                DTS_ICIFR_TS1_CITLF_Msk     /*!< Clear the IT flag for low threshold for DTS  */

+#define DTS_ICIFR_TS1_CITHF_Pos            (2U)

+#define DTS_ICIFR_TS1_CITHF_Msk            (0x1UL << DTS_ICIFR_TS1_CITHF_Pos) /*!< 0x00000004 */

+#define DTS_ICIFR_TS1_CITHF                DTS_ICIFR_TS1_CITHF_Msk     /*!< Clear the IT flag for high threshold on DTS  */

+#define DTS_ICIFR_TS1_CAITEF_Pos           (4U)

+#define DTS_ICIFR_TS1_CAITEF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITEF_Pos) /*!< 0x00000010 */

+#define DTS_ICIFR_TS1_CAITEF               DTS_ICIFR_TS1_CAITEF_Msk    /*!< Clear the asynchronous IT flag for End Of Measure for DTS */

+#define DTS_ICIFR_TS1_CAITLF_Pos           (5U)

+#define DTS_ICIFR_TS1_CAITLF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITLF_Pos) /*!< 0x00000020 */

+#define DTS_ICIFR_TS1_CAITLF               DTS_ICIFR_TS1_CAITLF_Msk    /*!< Clear the asynchronous IT flag for low threshold for DTS  */

+#define DTS_ICIFR_TS1_CAITHF_Pos           (6U)

+#define DTS_ICIFR_TS1_CAITHF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITHF_Pos) /*!< 0x00000040 */

+#define DTS_ICIFR_TS1_CAITHF               DTS_ICIFR_TS1_CAITHF_Msk    /*!< Clear the asynchronous IT flag for high threshold on DTS  */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    TIM                                     */

+/*                                                                            */

+/******************************************************************************/

+#define TIM_BREAK_INPUT_SUPPORT             /*!<TIM Break input feature */

+

+/*******************  Bit definition for TIM_CR1 register  ********************/

+#define TIM_CR1_CEN_Pos           (0U)

+#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */

+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */

+#define TIM_CR1_UDIS_Pos          (1U)

+#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */

+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */

+#define TIM_CR1_URS_Pos           (2U)

+#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */

+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */

+#define TIM_CR1_OPM_Pos           (3U)

+#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */

+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */

+#define TIM_CR1_DIR_Pos           (4U)

+#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */

+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */

+

+#define TIM_CR1_CMS_Pos           (5U)

+#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */

+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */

+#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */

+#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */

+

+#define TIM_CR1_ARPE_Pos          (7U)

+#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */

+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */

+

+#define TIM_CR1_CKD_Pos           (8U)

+#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */

+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */

+#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */

+#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */

+

+#define TIM_CR1_UIFREMAP_Pos      (11U)

+#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */

+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */

+

+/*******************  Bit definition for TIM_CR2 register  ********************/

+#define TIM_CR2_CCPC_Pos          (0U)

+#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */

+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */

+#define TIM_CR2_CCUS_Pos          (2U)

+#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */

+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */

+#define TIM_CR2_CCDS_Pos          (3U)

+#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */

+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */

+

+#define TIM_CR2_MMS_Pos           (4U)

+#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */

+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */

+#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */

+#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */

+#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */

+

+#define TIM_CR2_TI1S_Pos          (7U)

+#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */

+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */

+#define TIM_CR2_OIS1_Pos          (8U)

+#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */

+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */

+#define TIM_CR2_OIS1N_Pos         (9U)

+#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */

+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */

+#define TIM_CR2_OIS2_Pos          (10U)

+#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */

+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */

+#define TIM_CR2_OIS2N_Pos         (11U)

+#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */

+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */

+#define TIM_CR2_OIS3_Pos          (12U)

+#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */

+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */

+#define TIM_CR2_OIS3N_Pos         (13U)

+#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */

+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */

+#define TIM_CR2_OIS4_Pos          (14U)

+#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */

+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */

+#define TIM_CR2_OIS5_Pos          (16U)

+#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */

+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */

+#define TIM_CR2_OIS6_Pos          (17U)

+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */

+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */

+

+#define TIM_CR2_MMS2_Pos          (20U)

+#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */

+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */

+#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */

+#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */

+#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */

+#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */

+

+/*******************  Bit definition for TIM_SMCR register  *******************/

+#define TIM_SMCR_SMS_Pos          (0U)

+#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */

+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */

+#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */

+#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */

+#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */

+#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */

+

+#define TIM_SMCR_TS_Pos           (4U)

+#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */

+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[4:0] bits (Trigger selection) */

+#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)                /*!< 0x00000010 */

+#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)                /*!< 0x00000020 */

+#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)                /*!< 0x00000040 */

+#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)                /*!< 0x00100000 */

+#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)                /*!< 0x00200000 */

+

+#define TIM_SMCR_MSM_Pos          (7U)

+#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */

+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */

+

+#define TIM_SMCR_ETF_Pos          (8U)

+#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */

+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */

+#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */

+#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */

+#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */

+#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */

+

+#define TIM_SMCR_ETPS_Pos         (12U)

+#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */

+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */

+#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */

+#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */

+

+#define TIM_SMCR_ECE_Pos          (14U)

+#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */

+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */

+#define TIM_SMCR_ETP_Pos          (15U)

+#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */

+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */

+

+/*******************  Bit definition for TIM_DIER register  *******************/

+#define TIM_DIER_UIE_Pos          (0U)

+#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */

+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */

+#define TIM_DIER_CC1IE_Pos        (1U)

+#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */

+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */

+#define TIM_DIER_CC2IE_Pos        (2U)

+#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */

+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */

+#define TIM_DIER_CC3IE_Pos        (3U)

+#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */

+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */

+#define TIM_DIER_CC4IE_Pos        (4U)

+#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */

+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */

+#define TIM_DIER_COMIE_Pos        (5U)

+#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */

+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */

+#define TIM_DIER_TIE_Pos          (6U)

+#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */

+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */

+#define TIM_DIER_BIE_Pos          (7U)

+#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */

+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */

+#define TIM_DIER_UDE_Pos          (8U)

+#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */

+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */

+#define TIM_DIER_CC1DE_Pos        (9U)

+#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */

+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */

+#define TIM_DIER_CC2DE_Pos        (10U)

+#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */

+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */

+#define TIM_DIER_CC3DE_Pos        (11U)

+#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */

+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */

+#define TIM_DIER_CC4DE_Pos        (12U)

+#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */

+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */

+#define TIM_DIER_COMDE_Pos        (13U)

+#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */

+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */

+#define TIM_DIER_TDE_Pos          (14U)

+#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */

+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */

+

+/********************  Bit definition for TIM_SR register  ********************/

+#define TIM_SR_UIF_Pos            (0U)

+#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */

+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */

+#define TIM_SR_CC1IF_Pos          (1U)

+#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */

+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */

+#define TIM_SR_CC2IF_Pos          (2U)

+#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */

+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */

+#define TIM_SR_CC3IF_Pos          (3U)

+#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */

+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */

+#define TIM_SR_CC4IF_Pos          (4U)

+#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */

+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */

+#define TIM_SR_COMIF_Pos          (5U)

+#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */

+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */

+#define TIM_SR_TIF_Pos            (6U)

+#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */

+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */

+#define TIM_SR_BIF_Pos            (7U)

+#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */

+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */

+#define TIM_SR_B2IF_Pos           (8U)

+#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */

+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break2 interrupt Flag */

+#define TIM_SR_CC1OF_Pos          (9U)

+#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */

+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */

+#define TIM_SR_CC2OF_Pos          (10U)

+#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */

+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */

+#define TIM_SR_CC3OF_Pos          (11U)

+#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */

+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */

+#define TIM_SR_CC4OF_Pos          (12U)

+#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */

+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */

+#define TIM_SR_CC5IF_Pos          (16U)

+#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */

+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */

+#define TIM_SR_CC6IF_Pos          (17U)

+#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */

+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */

+#define TIM_SR_SBIF_Pos           (13U)

+#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */

+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!< System Break Flag */

+

+/*******************  Bit definition for TIM_EGR register  ********************/

+#define TIM_EGR_UG_Pos            (0U)

+#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */

+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */

+#define TIM_EGR_CC1G_Pos          (1U)

+#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */

+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */

+#define TIM_EGR_CC2G_Pos          (2U)

+#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */

+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */

+#define TIM_EGR_CC3G_Pos          (3U)

+#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */

+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */

+#define TIM_EGR_CC4G_Pos          (4U)

+#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */

+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */

+#define TIM_EGR_COMG_Pos          (5U)

+#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */

+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */

+#define TIM_EGR_TG_Pos            (6U)

+#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */

+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */

+#define TIM_EGR_BG_Pos            (7U)

+#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */

+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */

+#define TIM_EGR_B2G_Pos           (8U)

+#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */

+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break Generation */

+

+

+/******************  Bit definition for TIM_CCMR1 register  *******************/

+#define TIM_CCMR1_CC1S_Pos        (0U)

+#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */

+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */

+#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */

+#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */

+

+#define TIM_CCMR1_OC1FE_Pos       (2U)

+#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */

+#define TIM_CCMR1_OC1PE_Pos       (3U)

+#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */

+

+#define TIM_CCMR1_OC1M_Pos        (4U)

+#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */

+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */

+#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */

+#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */

+#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */

+#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR1_OC1CE_Pos       (7U)

+#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */

+

+#define TIM_CCMR1_CC2S_Pos        (8U)

+#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */

+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */

+#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */

+#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */

+

+#define TIM_CCMR1_OC2FE_Pos       (10U)

+#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */

+#define TIM_CCMR1_OC2PE_Pos       (11U)

+#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */

+

+#define TIM_CCMR1_OC2M_Pos        (12U)

+#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */

+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */

+#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */

+#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */

+#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */

+#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */

+

+#define TIM_CCMR1_OC2CE_Pos       (15U)

+#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */

+

+/*----------------------------------------------------------------------------*/

+

+#define TIM_CCMR1_IC1PSC_Pos      (2U)

+#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */

+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */

+#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */

+

+#define TIM_CCMR1_IC1F_Pos        (4U)

+#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */

+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */

+#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */

+

+#define TIM_CCMR1_IC2PSC_Pos      (10U)

+#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */

+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */

+#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */

+

+#define TIM_CCMR1_IC2F_Pos        (12U)

+#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */

+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */

+#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */

+

+/******************  Bit definition for TIM_CCMR2 register  *******************/

+#define TIM_CCMR2_CC3S_Pos        (0U)

+#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */

+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */

+#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */

+#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */

+

+#define TIM_CCMR2_OC3FE_Pos       (2U)

+#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */

+#define TIM_CCMR2_OC3PE_Pos       (3U)

+#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */

+

+#define TIM_CCMR2_OC3M_Pos        (4U)

+#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */

+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */

+#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR2_OC3CE_Pos       (7U)

+#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */

+

+#define TIM_CCMR2_CC4S_Pos        (8U)

+#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */

+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */

+#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */

+#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */

+

+#define TIM_CCMR2_OC4FE_Pos       (10U)

+#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */

+#define TIM_CCMR2_OC4PE_Pos       (11U)

+#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */

+

+#define TIM_CCMR2_OC4M_Pos        (12U)

+#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */

+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */

+#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */

+

+#define TIM_CCMR2_OC4CE_Pos       (15U)

+#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */

+

+/*----------------------------------------------------------------------------*/

+

+#define TIM_CCMR2_IC3PSC_Pos      (2U)

+#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */

+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */

+#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */

+

+#define TIM_CCMR2_IC3F_Pos        (4U)

+#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */

+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */

+#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */

+

+#define TIM_CCMR2_IC4PSC_Pos      (10U)

+#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */

+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */

+#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */

+

+#define TIM_CCMR2_IC4F_Pos        (12U)

+#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */

+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */

+#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */

+

+/*******************  Bit definition for TIM_CCER register  *******************/

+#define TIM_CCER_CC1E_Pos         (0U)

+#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */

+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */

+#define TIM_CCER_CC1P_Pos         (1U)

+#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */

+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */

+#define TIM_CCER_CC1NE_Pos        (2U)

+#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */

+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */

+#define TIM_CCER_CC1NP_Pos        (3U)

+#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */

+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */

+#define TIM_CCER_CC2E_Pos         (4U)

+#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */

+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */

+#define TIM_CCER_CC2P_Pos         (5U)

+#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */

+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */

+#define TIM_CCER_CC2NE_Pos        (6U)

+#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */

+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */

+#define TIM_CCER_CC2NP_Pos        (7U)

+#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */

+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */

+#define TIM_CCER_CC3E_Pos         (8U)

+#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */

+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */

+#define TIM_CCER_CC3P_Pos         (9U)

+#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */

+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */

+#define TIM_CCER_CC3NE_Pos        (10U)

+#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */

+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */

+#define TIM_CCER_CC3NP_Pos        (11U)

+#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */

+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */

+#define TIM_CCER_CC4E_Pos         (12U)

+#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */

+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */

+#define TIM_CCER_CC4P_Pos         (13U)

+#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */

+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */

+#define TIM_CCER_CC4NP_Pos        (15U)

+#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */

+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */

+#define TIM_CCER_CC5E_Pos         (16U)

+#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */

+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */

+#define TIM_CCER_CC5P_Pos         (17U)

+#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */

+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */

+#define TIM_CCER_CC6E_Pos         (20U)

+#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */

+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */

+#define TIM_CCER_CC6P_Pos         (21U)

+#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */

+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */

+/*******************  Bit definition for TIM_CNT register  ********************/

+#define TIM_CNT_CNT_Pos           (0U)

+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */

+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */

+#define TIM_CNT_UIFCPY_Pos        (31U)

+#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */

+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy */

+/*******************  Bit definition for TIM_PSC register  ********************/

+#define TIM_PSC_PSC_Pos           (0U)

+#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */

+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */

+

+/*******************  Bit definition for TIM_ARR register  ********************/

+#define TIM_ARR_ARR_Pos           (0U)

+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */

+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */

+

+/*******************  Bit definition for TIM_RCR register  ********************/

+#define TIM_RCR_REP_Pos           (0U)

+#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                  /*!< 0x000000FF */

+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */

+

+/*******************  Bit definition for TIM_CCR1 register  *******************/

+#define TIM_CCR1_CCR1_Pos         (0U)

+#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */

+

+/*******************  Bit definition for TIM_CCR2 register  *******************/

+#define TIM_CCR2_CCR2_Pos         (0U)

+#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */

+

+/*******************  Bit definition for TIM_CCR3 register  *******************/

+#define TIM_CCR3_CCR3_Pos         (0U)

+#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */

+

+/*******************  Bit definition for TIM_CCR4 register  *******************/

+#define TIM_CCR4_CCR4_Pos         (0U)

+#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */

+

+/*******************  Bit definition for TIM_CCR5 register  *******************/

+#define TIM_CCR5_CCR5_Pos         (0U)

+#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */

+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */

+#define TIM_CCR5_GC5C1_Pos        (29U)

+#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */

+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */

+#define TIM_CCR5_GC5C2_Pos        (30U)

+#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */

+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */

+#define TIM_CCR5_GC5C3_Pos        (31U)

+#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */

+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */

+

+/*******************  Bit definition for TIM_CCR6 register  *******************/

+#define TIM_CCR6_CCR6_Pos         (0U)

+#define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */

+

+/*******************  Bit definition for TIM_BDTR register  *******************/

+#define TIM_BDTR_DTG_Pos          (0U)

+#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */

+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */

+#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */

+#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */

+#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */

+#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */

+#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */

+#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */

+#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */

+#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */

+

+#define TIM_BDTR_LOCK_Pos         (8U)

+#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */

+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */

+#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */

+#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */

+

+#define TIM_BDTR_OSSI_Pos         (10U)

+#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */

+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */

+#define TIM_BDTR_OSSR_Pos         (11U)

+#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */

+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */

+#define TIM_BDTR_BKE_Pos          (12U)

+#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */

+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break1 */

+#define TIM_BDTR_BKP_Pos          (13U)

+#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */

+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break1 */

+#define TIM_BDTR_AOE_Pos          (14U)

+#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */

+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */

+#define TIM_BDTR_MOE_Pos          (15U)

+#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */

+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */

+

+#define TIM_BDTR_BKF_Pos          (16U)

+#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */

+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break1 */

+#define TIM_BDTR_BK2F_Pos         (20U)

+#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */

+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break2 */

+

+#define TIM_BDTR_BK2E_Pos         (24U)

+#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */

+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break2 */

+#define TIM_BDTR_BK2P_Pos         (25U)

+#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */

+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */

+

+/*******************  Bit definition for TIM_DCR register  ********************/

+#define TIM_DCR_DBA_Pos           (0U)

+#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */

+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */

+#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */

+#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */

+#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */

+#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */

+#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */

+

+#define TIM_DCR_DBL_Pos           (8U)

+#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */

+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */

+#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */

+#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */

+#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */

+#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */

+#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */

+

+/*******************  Bit definition for TIM_DMAR register  *******************/

+#define TIM_DMAR_DMAB_Pos         (0U)

+#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */

+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */

+

+/******************  Bit definition for TIM_CCMR3 register  *******************/

+#define TIM_CCMR3_OC5FE_Pos       (2U)

+#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */

+#define TIM_CCMR3_OC5PE_Pos       (3U)

+#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */

+

+#define TIM_CCMR3_OC5M_Pos        (4U)

+#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */

+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */

+#define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR3_OC5CE_Pos       (7U)

+#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */

+

+#define TIM_CCMR3_OC6FE_Pos       (10U)

+#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 4 Fast enable */

+#define TIM_CCMR3_OC6PE_Pos       (11U)

+#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */

+

+#define TIM_CCMR3_OC6M_Pos        (12U)

+#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */

+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */

+#define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */

+

+#define TIM_CCMR3_OC6CE_Pos       (15U)

+#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 4 Clear Enable */

+/*******************  Bit definition for TIM1_AF1 register  *********************/

+#define TIM1_AF1_BKINE_Pos        (0U)

+#define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */

+#define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */

+#define TIM1_AF1_BKCMP1E_Pos      (1U)

+#define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */

+#define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM1_AF1_BKCMP2E_Pos      (2U)

+#define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */

+#define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit */

+#define TIM1_AF1_BKDF1BK0E_Pos    (8U)

+#define TIM1_AF1_BKDF1BK0E_Msk    (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)            /*!< 0x00000100 */

+#define TIM1_AF1_BKDF1BK0E        TIM1_AF1_BKDF1BK0E_Msk                       /*!<BKDF1BK0E Break input DFSDM Break 0 */

+#define TIM1_AF1_BKINP_Pos        (9U)

+#define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */

+#define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */

+#define TIM1_AF1_BKCMP1P_Pos      (10U)

+#define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */

+#define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM1_AF1_BKCMP2P_Pos      (11U)

+#define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */

+#define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */

+

+#define TIM1_AF1_ETRSEL_Pos       (14U)

+#define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */

+#define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */

+#define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00004000 */

+#define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00008000 */

+#define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00010000 */

+#define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM1_AF2 register  *********************/

+#define TIM1_AF2_BK2INE_Pos       (0U)

+#define TIM1_AF2_BK2INE_Msk       (0x1UL << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */

+#define TIM1_AF2_BK2INE           TIM1_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */

+#define TIM1_AF2_BK2CMP1E_Pos     (1U)

+#define TIM1_AF2_BK2CMP1E_Msk     (0x1UL << TIM1_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */

+#define TIM1_AF2_BK2CMP1E         TIM1_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */

+#define TIM1_AF2_BK2CMP2E_Pos     (2U)

+#define TIM1_AF2_BK2CMP2E_Msk     (0x1UL << TIM1_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */

+#define TIM1_AF2_BK2CMP2E         TIM1_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */

+#define TIM1_AF2_BK2DFBK1E_Pos    (8U)

+#define TIM1_AF2_BK2DFBK1E_Msk    (0x1UL << TIM1_AF2_BK2DFBK1E_Pos)            /*!< 0x00000100 */

+#define TIM1_AF2_BK2DFBK1E        TIM1_AF2_BK2DFBK1E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 1 */

+#define TIM1_AF2_BK2INP_Pos       (9U)

+#define TIM1_AF2_BK2INP_Msk       (0x1UL << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */

+#define TIM1_AF2_BK2INP           TIM1_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */

+#define TIM1_AF2_BK2CMP1P_Pos     (10U)

+#define TIM1_AF2_BK2CMP1P_Msk     (0x1UL << TIM1_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */

+#define TIM1_AF2_BK2CMP1P         TIM1_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */

+#define TIM1_AF2_BK2CMP2P_Pos     (11U)

+#define TIM1_AF2_BK2CMP2P_Msk     (0x1UL << TIM1_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */

+#define TIM1_AF2_BK2CMP2P         TIM1_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */

+

+/*******************  Bit definition for TIM_TISEL register  *********************/

+#define TIM_TISEL_TI1SEL_Pos      (0U)

+#define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */

+#define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/

+#define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000001 */

+#define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000002 */

+#define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000004 */

+#define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000008 */

+

+#define TIM_TISEL_TI2SEL_Pos      (8U)

+#define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */

+#define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/

+#define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000100 */

+#define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000200 */

+#define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000400 */

+#define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000800 */

+

+#define TIM_TISEL_TI3SEL_Pos      (16U)

+#define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */

+#define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/

+#define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00010000 */

+#define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00020000 */

+#define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00040000 */

+#define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00080000 */

+

+#define TIM_TISEL_TI4SEL_Pos      (24U)

+#define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */

+#define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/

+#define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x01000000 */

+#define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x02000000 */

+#define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x04000000 */

+#define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x08000000 */

+

+/*******************  Bit definition for TIM8_AF1 register  *********************/

+#define TIM8_AF1_BKINE_Pos        (0U)

+#define TIM8_AF1_BKINE_Msk        (0x1UL << TIM8_AF1_BKINE_Pos)                /*!< 0x00000001 */

+#define TIM8_AF1_BKINE            TIM8_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */

+#define TIM8_AF1_BKCMP1E_Pos      (1U)

+#define TIM8_AF1_BKCMP1E_Msk      (0x1UL << TIM8_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */

+#define TIM8_AF1_BKCMP1E          TIM8_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM8_AF1_BKCMP2E_Pos      (2U)

+#define TIM8_AF1_BKCMP2E_Msk      (0x1UL << TIM8_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */

+#define TIM8_AF1_BKCMP2E          TIM8_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM8_AF1_BKDFBK2E_Pos     (8U)

+#define TIM8_AF1_BKDFBK2E_Msk     (0x1UL << TIM8_AF1_BKDFBK2E_Pos)             /*!< 0x00000100 */

+#define TIM8_AF1_BKDFBK2E         TIM8_AF1_BKDFBK2E_Msk                        /*!<BKDFBK2E Break input DFSDM Break 2 */

+#define TIM8_AF1_BKINP_Pos        (9U)

+#define TIM8_AF1_BKINP_Msk        (0x1UL << TIM8_AF1_BKINP_Pos)                /*!< 0x00000200 */

+#define TIM8_AF1_BKINP            TIM8_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */

+#define TIM8_AF1_BKCMP1P_Pos      (10U)

+#define TIM8_AF1_BKCMP1P_Msk      (0x1UL << TIM8_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */

+#define TIM8_AF1_BKCMP1P          TIM8_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM8_AF1_BKCMP2P_Pos      (11U)

+#define TIM8_AF1_BKCMP2P_Msk      (0x1UL << TIM8_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */

+#define TIM8_AF1_BKCMP2P          TIM8_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */

+

+#define TIM8_AF1_ETRSEL_Pos       (14U)

+#define TIM8_AF1_ETRSEL_Msk       (0xFUL << TIM8_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */

+#define TIM8_AF1_ETRSEL           TIM8_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */

+#define TIM8_AF1_ETRSEL_0         (0x1UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00004000 */

+#define TIM8_AF1_ETRSEL_1         (0x2UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00008000 */

+#define TIM8_AF1_ETRSEL_2         (0x4UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00010000 */

+#define TIM8_AF1_ETRSEL_3         (0x8UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00020000 */

+/*******************  Bit definition for TIM8_AF2 register  *********************/

+#define TIM8_AF2_BK2INE_Pos       (0U)

+#define TIM8_AF2_BK2INE_Msk       (0x1UL << TIM8_AF2_BK2INE_Pos)               /*!< 0x00000001 */

+#define TIM8_AF2_BK2INE           TIM8_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */

+#define TIM8_AF2_BK2CMP1E_Pos     (1U)

+#define TIM8_AF2_BK2CMP1E_Msk     (0x1UL << TIM8_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */

+#define TIM8_AF2_BK2CMP1E         TIM8_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */

+#define TIM8_AF2_BK2CMP2E_Pos     (2U)

+#define TIM8_AF2_BK2CMP2E_Msk     (0x1UL << TIM8_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */

+#define TIM8_AF2_BK2CMP2E         TIM8_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */

+#define TIM8_AF2_BK2DFBK3E_Pos    (8U)

+#define TIM8_AF2_BK2DFBK3E_Msk    (0x1UL << TIM8_AF2_BK2DFBK3E_Pos)            /*!< 0x00000100 */

+#define TIM8_AF2_BK2DFBK3E        TIM8_AF2_BK2DFBK3E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 3 */

+#define TIM8_AF2_BK2INP_Pos       (9U)

+#define TIM8_AF2_BK2INP_Msk       (0x1UL << TIM8_AF2_BK2INP_Pos)               /*!< 0x00000200 */

+#define TIM8_AF2_BK2INP           TIM8_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */

+#define TIM8_AF2_BK2CMP1P_Pos     (10U)

+#define TIM8_AF2_BK2CMP1P_Msk     (0x1UL << TIM8_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */

+#define TIM8_AF2_BK2CMP1P         TIM8_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */

+#define TIM8_AF2_BK2CMP2P_Pos     (11U)

+#define TIM8_AF2_BK2CMP2P_Msk     (0x1UL << TIM8_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */

+#define TIM8_AF2_BK2CMP2P         TIM8_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */

+

+/*******************  Bit definition for TIM2_AF1 register  *********************/

+#define TIM2_AF1_ETRSEL_Pos      (14U)

+#define TIM2_AF1_ETRSEL_Msk      (0xFUL << TIM2_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM2_AF1_ETRSEL          TIM2_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */

+#define TIM2_AF1_ETRSEL_0        (0x1UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM2_AF1_ETRSEL_1        (0x2UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM2_AF1_ETRSEL_2        (0x4UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM2_AF1_ETRSEL_3        (0x8UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM3_AF1 register  *********************/

+#define TIM3_AF1_ETRSEL_Pos      (14U)

+#define TIM3_AF1_ETRSEL_Msk      (0xFUL << TIM3_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM3_AF1_ETRSEL          TIM3_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */

+#define TIM3_AF1_ETRSEL_0        (0x1UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM3_AF1_ETRSEL_1        (0x2UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM3_AF1_ETRSEL_2        (0x4UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM3_AF1_ETRSEL_3        (0x8UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM5_AF1 register  *********************/

+#define TIM5_AF1_ETRSEL_Pos      (14U)

+#define TIM5_AF1_ETRSEL_Msk      (0xFUL << TIM5_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM5_AF1_ETRSEL          TIM5_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */

+#define TIM5_AF1_ETRSEL_0        (0x1UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM5_AF1_ETRSEL_1        (0x2UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM5_AF1_ETRSEL_2        (0x4UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM5_AF1_ETRSEL_3        (0x8UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM15_AF1 register  *********************/

+#define TIM15_AF1_BKINE_Pos        (0U)

+#define TIM15_AF1_BKINE_Msk        (0x1UL << TIM15_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM15_AF1_BKINE            TIM15_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM15_AF1_BKCMP1E_Pos      (1U)

+#define TIM15_AF1_BKCMP1E_Msk      (0x1UL << TIM15_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM15_AF1_BKCMP1E          TIM15_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM15_AF1_BKCMP2E_Pos      (2U)

+#define TIM15_AF1_BKCMP2E_Msk      (0x1UL << TIM15_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM15_AF1_BKCMP2E          TIM15_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM15_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM15_AF1_BKDF1BK2E_Msk    (0x1UL << TIM15_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM15_AF1_BKDF1BK2E        TIM15_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[0] enable */

+#define TIM15_AF1_BKINP_Pos        (9U)

+#define TIM15_AF1_BKINP_Msk        (0x1UL << TIM15_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM15_AF1_BKINP            TIM15_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM15_AF1_BKCMP1P_Pos      (10U)

+#define TIM15_AF1_BKCMP1P_Msk      (0x1UL << TIM15_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM15_AF1_BKCMP1P          TIM15_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM15_AF1_BKCMP2P_Pos      (11U)

+#define TIM15_AF1_BKCMP2P_Msk      (0x1UL << TIM15_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM15_AF1_BKCMP2P          TIM15_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/*******************  Bit definition for TIM16_ register  *********************/

+#define TIM16_AF1_BKINE_Pos        (0U)

+#define TIM16_AF1_BKINE_Msk        (0x1UL << TIM16_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM16_AF1_BKINE            TIM16_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM16_AF1_BKCMP1E_Pos      (1U)

+#define TIM16_AF1_BKCMP1E_Msk      (0x1UL << TIM16_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM16_AF1_BKCMP1E          TIM16_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM16_AF1_BKCMP2E_Pos      (2U)

+#define TIM16_AF1_BKCMP2E_Msk      (0x1UL << TIM16_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM16_AF1_BKCMP2E          TIM16_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM16_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM16_AF1_BKDF1BK2E_Msk    (0x1UL << TIM16_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM16_AF1_BKDF1BK2E        TIM16_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[1] enable */

+#define TIM16_AF1_BKINP_Pos        (9U)

+#define TIM16_AF1_BKINP_Msk        (0x1UL << TIM16_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM16_AF1_BKINP            TIM16_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM16_AF1_BKCMP1P_Pos      (10U)

+#define TIM16_AF1_BKCMP1P_Msk      (0x1UL << TIM16_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM16_AF1_BKCMP1P          TIM16_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM16_AF1_BKCMP2P_Pos      (11U)

+#define TIM16_AF1_BKCMP2P_Msk      (0x1UL << TIM16_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM16_AF1_BKCMP2P          TIM16_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/*******************  Bit definition for TIM17_AF1 register  *********************/

+#define TIM17_AF1_BKINE_Pos        (0U)

+#define TIM17_AF1_BKINE_Msk        (0x1UL << TIM17_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM17_AF1_BKINE            TIM17_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM17_AF1_BKCMP1E_Pos      (1U)

+#define TIM17_AF1_BKCMP1E_Msk      (0x1UL << TIM17_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM17_AF1_BKCMP1E          TIM17_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM17_AF1_BKCMP2E_Pos      (2U)

+#define TIM17_AF1_BKCMP2E_Msk      (0x1UL << TIM17_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM17_AF1_BKCMP2E          TIM17_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM17_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM17_AF1_BKDF1BK2E_Msk    (0x1UL << TIM17_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM17_AF1_BKDF1BK2E        TIM17_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[2] enable */

+#define TIM17_AF1_BKINP_Pos        (9U)

+#define TIM17_AF1_BKINP_Msk        (0x1UL << TIM17_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM17_AF1_BKINP            TIM17_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM17_AF1_BKCMP1P_Pos      (10U)

+#define TIM17_AF1_BKCMP1P_Msk      (0x1UL << TIM17_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM17_AF1_BKCMP1P          TIM17_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM17_AF1_BKCMP2P_Pos      (11U)

+#define TIM17_AF1_BKCMP2P_Msk      (0x1UL << TIM17_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM17_AF1_BKCMP2P          TIM17_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Low Power Timer (LPTTIM)                           */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for LPTIM_ISR register  *******************/

+#define LPTIM_ISR_CMPM_Pos          (0U)

+#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */

+#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */

+#define LPTIM_ISR_ARRM_Pos          (1U)

+#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */

+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */

+#define LPTIM_ISR_EXTTRIG_Pos       (2U)

+#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */

+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */

+#define LPTIM_ISR_CMPOK_Pos         (3U)

+#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */

+#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */

+#define LPTIM_ISR_ARROK_Pos         (4U)

+#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */

+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */

+#define LPTIM_ISR_UP_Pos            (5U)

+#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */

+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */

+#define LPTIM_ISR_DOWN_Pos          (6U)

+#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */

+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */

+

+/******************  Bit definition for LPTIM_ICR register  *******************/

+#define LPTIM_ICR_CMPMCF_Pos        (0U)

+#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */

+#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */

+#define LPTIM_ICR_ARRMCF_Pos        (1U)

+#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */

+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */

+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)

+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */

+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */

+#define LPTIM_ICR_CMPOKCF_Pos       (3U)

+#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */

+#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */

+#define LPTIM_ICR_ARROKCF_Pos       (4U)

+#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */

+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */

+#define LPTIM_ICR_UPCF_Pos          (5U)

+#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */

+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */

+#define LPTIM_ICR_DOWNCF_Pos        (6U)

+#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */

+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */

+

+/******************  Bit definition for LPTIM_IER register ********************/

+#define LPTIM_IER_CMPMIE_Pos        (0U)

+#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */

+#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */

+#define LPTIM_IER_ARRMIE_Pos        (1U)

+#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */

+#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */

+#define LPTIM_IER_EXTTRIGIE_Pos     (2U)

+#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */

+#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */

+#define LPTIM_IER_CMPOKIE_Pos       (3U)

+#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */

+#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */

+#define LPTIM_IER_ARROKIE_Pos       (4U)

+#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */

+#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */

+#define LPTIM_IER_UPIE_Pos          (5U)

+#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */

+#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */

+#define LPTIM_IER_DOWNIE_Pos        (6U)

+#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */

+#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */

+

+/******************  Bit definition for LPTIM_CFGR register *******************/

+#define LPTIM_CFGR_CKSEL_Pos        (0U)

+#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */

+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */

+

+#define LPTIM_CFGR_CKPOL_Pos        (1U)

+#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */

+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */

+#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */

+#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */

+

+#define LPTIM_CFGR_CKFLT_Pos        (3U)

+#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */

+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */

+#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */

+#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */

+

+#define LPTIM_CFGR_TRGFLT_Pos       (6U)

+#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */

+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */

+#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */

+#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */

+

+#define LPTIM_CFGR_PRESC_Pos        (9U)

+#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */

+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */

+#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */

+#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */

+#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */

+

+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)

+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */

+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */

+#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */

+#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */

+#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */

+

+#define LPTIM_CFGR_TRIGEN_Pos       (17U)

+#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */

+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */

+#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */

+#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */

+

+#define LPTIM_CFGR_TIMOUT_Pos       (19U)

+#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */

+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */

+#define LPTIM_CFGR_WAVE_Pos         (20U)

+#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */

+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */

+#define LPTIM_CFGR_WAVPOL_Pos       (21U)

+#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */

+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */

+#define LPTIM_CFGR_PRELOAD_Pos      (22U)

+#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */

+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */

+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)

+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */

+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */

+#define LPTIM_CFGR_ENC_Pos          (24U)

+#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */

+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */

+

+/******************  Bit definition for LPTIM_CR register  ********************/

+#define LPTIM_CR_ENABLE_Pos         (0U)

+#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */

+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */

+#define LPTIM_CR_SNGSTRT_Pos        (1U)

+#define LPTIM_CR_SNGSTRT_Msk        (0x40001UL << LPTIM_CR_SNGSTRT_Pos)        /*!< 0x00080002 */

+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */

+#define LPTIM_CR_CNTSTRT_Pos        (2U)

+#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */

+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */

+#define LPTIM_CR_COUNTRST_Pos       (3U)

+#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */

+#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Timer Counter reset in synchronous mode*/

+#define LPTIM_CR_RSTARE_Pos         (4U)

+#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */

+#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Timer Counter reset after read enable (asynchronously)*/

+

+

+/******************  Bit definition for LPTIM_CMP register  *******************/

+#define LPTIM_CMP_CMP_Pos           (0U)

+#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */

+

+/******************  Bit definition for LPTIM_ARR register  *******************/

+#define LPTIM_ARR_ARR_Pos           (0U)

+#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */

+

+/******************  Bit definition for LPTIM_CNT register  *******************/

+#define LPTIM_CNT_CNT_Pos           (0U)

+#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */

+

+/******************  Bit definition for LPTIM_CFGR2 register  *****************/

+#define LPTIM_CFGR2_IN1SEL_Pos      (0U)

+#define LPTIM_CFGR2_IN1SEL_Msk      (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000003 */

+#define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< IN1SEL[1:0] bits (Remap selection) */

+#define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000001 */

+#define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000002 */

+#define LPTIM_CFGR2_IN2SEL_Pos      (4U)

+#define LPTIM_CFGR2_IN2SEL_Msk      (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000030 */

+#define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< IN2SEL[5:4] bits (Remap selection) */

+#define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000010 */

+#define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000020 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    OCTOSPI                                 */

+/*                                                                            */

+/******************************************************************************/

+/*****************  Bit definition for OCTOSPI_CR register  *******************/

+#define OCTOSPI_CR_EN_Pos              (0U)

+#define OCTOSPI_CR_EN_Msk              (0x1UL << OCTOSPI_CR_EN_Pos)             /*!< 0x00000001 */

+#define OCTOSPI_CR_EN                  OCTOSPI_CR_EN_Msk                       /*!< Enable */

+#define OCTOSPI_CR_ABORT_Pos           (1U)

+#define OCTOSPI_CR_ABORT_Msk           (0x1UL << OCTOSPI_CR_ABORT_Pos)          /*!< 0x00000002 */

+#define OCTOSPI_CR_ABORT               OCTOSPI_CR_ABORT_Msk                    /*!< Abort request */

+#define OCTOSPI_CR_DMAEN_Pos           (2U)

+#define OCTOSPI_CR_DMAEN_Msk           (0x1UL << OCTOSPI_CR_DMAEN_Pos)          /*!< 0x00000004 */

+#define OCTOSPI_CR_DMAEN               OCTOSPI_CR_DMAEN_Msk                    /*!< DMA Enable */

+#define OCTOSPI_CR_TCEN_Pos            (3U)

+#define OCTOSPI_CR_TCEN_Msk            (0x1UL << OCTOSPI_CR_TCEN_Pos)           /*!< 0x00000008 */

+#define OCTOSPI_CR_TCEN                OCTOSPI_CR_TCEN_Msk                     /*!< Timeout Counter Enable */

+#define OCTOSPI_CR_DQM_Pos             (6U)

+#define OCTOSPI_CR_DQM_Msk             (0x1UL << OCTOSPI_CR_DQM_Pos)            /*!< 0x00000040 */

+#define OCTOSPI_CR_DQM                 OCTOSPI_CR_DQM_Msk                      /*!< Dual-Quad Mode */

+#define OCTOSPI_CR_FSEL_Pos            (7U)

+#define OCTOSPI_CR_FSEL_Msk            (0x1UL << OCTOSPI_CR_FSEL_Pos)           /*!< 0x00000080 */

+#define OCTOSPI_CR_FSEL                OCTOSPI_CR_FSEL_Msk                     /*!< Flash Select */

+#define OCTOSPI_CR_FTHRES_Pos          (8U)

+#define OCTOSPI_CR_FTHRES_Msk          (0x1FUL << OCTOSPI_CR_FTHRES_Pos)        /*!< 0x00001F00 */

+#define OCTOSPI_CR_FTHRES              OCTOSPI_CR_FTHRES_Msk                   /*!< FIFO Threshold Level */

+#define OCTOSPI_CR_TEIE_Pos            (16U)

+#define OCTOSPI_CR_TEIE_Msk            (0x1UL << OCTOSPI_CR_TEIE_Pos)           /*!< 0x00010000 */

+#define OCTOSPI_CR_TEIE                OCTOSPI_CR_TEIE_Msk                     /*!< Transfer Error Interrupt Enable */

+#define OCTOSPI_CR_TCIE_Pos            (17U)

+#define OCTOSPI_CR_TCIE_Msk            (0x1UL << OCTOSPI_CR_TCIE_Pos)           /*!< 0x00020000 */

+#define OCTOSPI_CR_TCIE                OCTOSPI_CR_TCIE_Msk                     /*!< Transfer Complete Interrupt Enable */

+#define OCTOSPI_CR_FTIE_Pos            (18U)

+#define OCTOSPI_CR_FTIE_Msk            (0x1UL << OCTOSPI_CR_FTIE_Pos)           /*!< 0x00040000 */

+#define OCTOSPI_CR_FTIE                OCTOSPI_CR_FTIE_Msk                     /*!< FIFO Threshold Interrupt Enable */

+#define OCTOSPI_CR_SMIE_Pos            (19U)

+#define OCTOSPI_CR_SMIE_Msk            (0x1UL << OCTOSPI_CR_SMIE_Pos)           /*!< 0x00080000 */

+#define OCTOSPI_CR_SMIE                OCTOSPI_CR_SMIE_Msk                     /*!< Status Match Interrupt Enable */

+#define OCTOSPI_CR_TOIE_Pos            (20U)

+#define OCTOSPI_CR_TOIE_Msk            (0x1UL << OCTOSPI_CR_TOIE_Pos)           /*!< 0x00100000 */

+#define OCTOSPI_CR_TOIE                OCTOSPI_CR_TOIE_Msk                     /*!< TimeOut Interrupt Enable */

+#define OCTOSPI_CR_APMS_Pos            (22U)

+#define OCTOSPI_CR_APMS_Msk            (0x1UL << OCTOSPI_CR_APMS_Pos)           /*!< 0x00400000 */

+#define OCTOSPI_CR_APMS                OCTOSPI_CR_APMS_Msk                     /*!< Automatic Poll Mode Stop */

+#define OCTOSPI_CR_PMM_Pos             (23U)

+#define OCTOSPI_CR_PMM_Msk             (0x1UL << OCTOSPI_CR_PMM_Pos)            /*!< 0x00800000 */

+#define OCTOSPI_CR_PMM                 OCTOSPI_CR_PMM_Msk                      /*!< Polling Match Mode */

+#define OCTOSPI_CR_FMODE_Pos           (28U)

+#define OCTOSPI_CR_FMODE_Msk           (0x3UL << OCTOSPI_CR_FMODE_Pos)          /*!< 0x30000000 */

+#define OCTOSPI_CR_FMODE               OCTOSPI_CR_FMODE_Msk                    /*!< Functional Mode */

+#define OCTOSPI_CR_FMODE_0             (0x1UL << OCTOSPI_CR_FMODE_Pos)          /*!< 0x10000000 */

+#define OCTOSPI_CR_FMODE_1             (0x2UL << OCTOSPI_CR_FMODE_Pos)          /*!< 0x20000000 */

+

+/****************  Bit definition for OCTOSPI_DCR1 register  ******************/

+#define OCTOSPI_DCR1_CKMODE_Pos        (0U)

+#define OCTOSPI_DCR1_CKMODE_Msk        (0x1UL << OCTOSPI_DCR1_CKMODE_Pos)       /*!< 0x00000001 */

+#define OCTOSPI_DCR1_CKMODE            OCTOSPI_DCR1_CKMODE_Msk                 /*!< Mode 0 / Mode 3 */

+#define OCTOSPI_DCR1_FRCK_Pos          (1U)

+#define OCTOSPI_DCR1_FRCK_Msk          (0x1UL << OCTOSPI_DCR1_FRCK_Pos)         /*!< 0x00000002 */

+#define OCTOSPI_DCR1_FRCK              OCTOSPI_DCR1_FRCK_Msk                   /*!< Free Running Clock */

+#define OCTOSPI_DCR1_DLYBYP_Pos        (3U)

+#define OCTOSPI_DCR1_DLYBYP_Msk        (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos)       /*!< 0x00000008 */

+#define OCTOSPI_DCR1_DLYBYP            OCTOSPI_DCR1_DLYBYP_Msk                 /*!< Delay Block */

+#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)

+#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */

+#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */

+#define OCTOSPI_DCR1_CSHT_Pos          (8U)

+#define OCTOSPI_DCR1_CSHT_Msk          (0x7UL << OCTOSPI_DCR1_CSHT_Pos)         /*!< 0x00000700 */

+#define OCTOSPI_DCR1_CSHT              OCTOSPI_DCR1_CSHT_Msk                   /*!< Chip Select High Time */

+#define OCTOSPI_DCR1_DEVSIZE_Pos       (16U)

+#define OCTOSPI_DCR1_DEVSIZE_Msk       (0x1FUL << OCTOSPI_DCR1_DEVSIZE_Pos)     /*!< 0x001F0000 */

+#define OCTOSPI_DCR1_DEVSIZE           OCTOSPI_DCR1_DEVSIZE_Msk                /*!< Device Size */

+#define OCTOSPI_DCR1_MTYP_Pos          (24U)

+#define OCTOSPI_DCR1_MTYP_Msk          (0x7UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x07000000 */

+#define OCTOSPI_DCR1_MTYP              OCTOSPI_DCR1_MTYP_Msk                   /*!< Memory Type */

+#define OCTOSPI_DCR1_MTYP_0            (0x1UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x01000000 */

+#define OCTOSPI_DCR1_MTYP_1            (0x2UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x02000000 */

+#define OCTOSPI_DCR1_MTYP_2            (0x4UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x04000000 */

+

+/****************  Bit definition for OCTOSPI_DCR2 register  ******************/

+#define OCTOSPI_DCR2_PRESCALER_Pos     (0U)

+#define OCTOSPI_DCR2_PRESCALER_Msk     (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos)   /*!< 0x000000FF */

+#define OCTOSPI_DCR2_PRESCALER         OCTOSPI_DCR2_PRESCALER_Msk              /*!< Clock prescaler */

+#define OCTOSPI_DCR2_WRAPSIZE_Pos      (16U)

+#define OCTOSPI_DCR2_WRAPSIZE_Msk      (0x7UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00070000 */

+#define OCTOSPI_DCR2_WRAPSIZE          OCTOSPI_DCR2_WRAPSIZE_Msk               /*!< Wrap Size */

+#define OCTOSPI_DCR2_WRAPSIZE_0        (0x1UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00010000 */

+#define OCTOSPI_DCR2_WRAPSIZE_1        (0x2UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00020000 */

+#define OCTOSPI_DCR2_WRAPSIZE_2        (0x4UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00040000 */

+

+/****************  Bit definition for OCTOSPI_DCR3 register  ******************/

+#define OCTOSPI_DCR3_MAXTRAN_Pos       (0U)

+#define OCTOSPI_DCR3_MAXTRAN_Msk       (0xFFUL << OCTOSPI_DCR3_MAXTRAN_Pos)     /*!< 0x000000FF */

+#define OCTOSPI_DCR3_MAXTRAN           OCTOSPI_DCR3_MAXTRAN_Msk                /*!< Maximum Transfer */

+#define OCTOSPI_DCR3_CSBOUND_Pos       (16U)

+#define OCTOSPI_DCR3_CSBOUND_Msk       (0x1FUL << OCTOSPI_DCR3_CSBOUND_Pos)     /*!< 0x001F0000 */

+#define OCTOSPI_DCR3_CSBOUND           OCTOSPI_DCR3_CSBOUND_Msk                /*!< CS Boundary */

+

+/****************  Bit definition for OCTOSPI_DCR4 register  ******************/

+#define OCTOSPI_DCR4_REFRESH_Pos       (0U)

+#define OCTOSPI_DCR4_REFRESH_Msk       (0xFFFFFFFFUL << OCTOSPI_DCR4_REFRESH_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_DCR4_REFRESH           OCTOSPI_DCR4_REFRESH_Msk                /*!< Refresh rate */

+

+/*****************  Bit definition for OCTOSPI_SR register  *******************/

+#define OCTOSPI_SR_TEF_Pos             (0U)

+#define OCTOSPI_SR_TEF_Msk             (0x1UL << OCTOSPI_SR_TEF_Pos)            /*!< 0x00000001 */

+#define OCTOSPI_SR_TEF                 OCTOSPI_SR_TEF_Msk                      /*!< Transfer Error Flag */

+#define OCTOSPI_SR_TCF_Pos             (1U)

+#define OCTOSPI_SR_TCF_Msk             (0x1UL << OCTOSPI_SR_TCF_Pos)            /*!< 0x00000002 */

+#define OCTOSPI_SR_TCF                 OCTOSPI_SR_TCF_Msk                      /*!< Transfer Complete Flag */

+#define OCTOSPI_SR_FTF_Pos             (2U)

+#define OCTOSPI_SR_FTF_Msk             (0x1UL << OCTOSPI_SR_FTF_Pos)            /*!< 0x00000004 */

+#define OCTOSPI_SR_FTF                 OCTOSPI_SR_FTF_Msk                      /*!< FIFO Threshold Flag */

+#define OCTOSPI_SR_SMF_Pos             (3U)

+#define OCTOSPI_SR_SMF_Msk             (0x1UL << OCTOSPI_SR_SMF_Pos)            /*!< 0x00000008 */

+#define OCTOSPI_SR_SMF                 OCTOSPI_SR_SMF_Msk                      /*!< Status Match Flag */

+#define OCTOSPI_SR_TOF_Pos             (4U)

+#define OCTOSPI_SR_TOF_Msk             (0x1UL << OCTOSPI_SR_TOF_Pos)            /*!< 0x00000010 */

+#define OCTOSPI_SR_TOF                 OCTOSPI_SR_TOF_Msk                      /*!< Timeout Flag */

+#define OCTOSPI_SR_BUSY_Pos            (5U)

+#define OCTOSPI_SR_BUSY_Msk            (0x1UL << OCTOSPI_SR_BUSY_Pos)           /*!< 0x00000020 */

+#define OCTOSPI_SR_BUSY                OCTOSPI_SR_BUSY_Msk                     /*!< Busy */

+#define OCTOSPI_SR_FLEVEL_Pos          (8U)

+#define OCTOSPI_SR_FLEVEL_Msk          (0x3FUL << OCTOSPI_SR_FLEVEL_Pos)        /*!< 0x00003F00 */

+#define OCTOSPI_SR_FLEVEL              OCTOSPI_SR_FLEVEL_Msk                   /*!< FIFO Level */

+

+/****************  Bit definition for OCTOSPI_FCR register  *******************/

+#define OCTOSPI_FCR_CTEF_Pos           (0U)

+#define OCTOSPI_FCR_CTEF_Msk           (0x1UL << OCTOSPI_FCR_CTEF_Pos)          /*!< 0x00000001 */

+#define OCTOSPI_FCR_CTEF               OCTOSPI_FCR_CTEF_Msk                    /*!< Clear Transfer Error Flag */

+#define OCTOSPI_FCR_CTCF_Pos           (1U)

+#define OCTOSPI_FCR_CTCF_Msk           (0x1UL << OCTOSPI_FCR_CTCF_Pos)          /*!< 0x00000002 */

+#define OCTOSPI_FCR_CTCF               OCTOSPI_FCR_CTCF_Msk                    /*!< Clear Transfer Complete Flag */

+#define OCTOSPI_FCR_CSMF_Pos           (3U)

+#define OCTOSPI_FCR_CSMF_Msk           (0x1UL << OCTOSPI_FCR_CSMF_Pos)          /*!< 0x00000008 */

+#define OCTOSPI_FCR_CSMF               OCTOSPI_FCR_CSMF_Msk                    /*!< Clear Status Match Flag */

+#define OCTOSPI_FCR_CTOF_Pos           (4U)

+#define OCTOSPI_FCR_CTOF_Msk           (0x1UL << OCTOSPI_FCR_CTOF_Pos)          /*!< 0x00000010 */

+#define OCTOSPI_FCR_CTOF               OCTOSPI_FCR_CTOF_Msk                    /*!< Clear Timeout Flag */

+

+/****************  Bit definition for OCTOSPI_DLR register  *******************/

+#define OCTOSPI_DLR_DL_Pos             (0U)

+#define OCTOSPI_DLR_DL_Msk             (0xFFFFFFFFUL << OCTOSPI_DLR_DL_Pos)     /*!< 0xFFFFFFFF */

+#define OCTOSPI_DLR_DL                 OCTOSPI_DLR_DL_Msk                      /*!< Data Length */

+

+/*****************  Bit definition for OCTOSPI_AR register  *******************/

+#define OCTOSPI_AR_ADDRESS_Pos         (0U)

+#define OCTOSPI_AR_ADDRESS_Msk         (0xFFFFFFFFUL << OCTOSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_AR_ADDRESS             OCTOSPI_AR_ADDRESS_Msk                  /*!< Address */

+

+/*****************  Bit definition for OCTOSPI_DR register  *******************/

+#define OCTOSPI_DR_DATA_Pos            (0U)

+#define OCTOSPI_DR_DATA_Msk            (0xFFFFFFFFUL << OCTOSPI_DR_DATA_Pos)    /*!< 0xFFFFFFFF */

+#define OCTOSPI_DR_DATA                OCTOSPI_DR_DATA_Msk                     /*!< Data */

+

+/***************  Bit definition for OCTOSPI_PSMKR register  ******************/

+#define OCTOSPI_PSMKR_MASK_Pos         (0U)

+#define OCTOSPI_PSMKR_MASK_Msk         (0xFFFFFFFFUL << OCTOSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_PSMKR_MASK             OCTOSPI_PSMKR_MASK_Msk                  /*!< Status mask */

+

+/***************  Bit definition for OCTOSPI_PSMAR register  ******************/

+#define OCTOSPI_PSMAR_MATCH_Pos        (0U)

+#define OCTOSPI_PSMAR_MATCH_Msk        (0xFFFFFFFFUL << OCTOSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_PSMAR_MATCH            OCTOSPI_PSMAR_MATCH_Msk                 /*!< Status match */

+

+/****************  Bit definition for OCTOSPI_PIR register  *******************/

+#define OCTOSPI_PIR_INTERVAL_Pos       (0U)

+#define OCTOSPI_PIR_INTERVAL_Msk       (0xFFFFUL << OCTOSPI_PIR_INTERVAL_Pos)   /*!< 0x0000FFFF */

+#define OCTOSPI_PIR_INTERVAL           OCTOSPI_PIR_INTERVAL_Msk                /*!< Polling Interval */

+

+/****************  Bit definition for OCTOSPI_CCR register  *******************/

+#define OCTOSPI_CCR_IMODE_Pos          (0U)

+#define OCTOSPI_CCR_IMODE_Msk          (0x7UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000007 */

+#define OCTOSPI_CCR_IMODE              OCTOSPI_CCR_IMODE_Msk                   /*!< Instruction Mode */

+#define OCTOSPI_CCR_IMODE_0            (0x1UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000001 */

+#define OCTOSPI_CCR_IMODE_1            (0x2UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000002 */

+#define OCTOSPI_CCR_IMODE_2            (0x4UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000004 */

+#define OCTOSPI_CCR_IDTR_Pos           (3U)

+#define OCTOSPI_CCR_IDTR_Msk           (0x1UL << OCTOSPI_CCR_IDTR_Pos)          /*!< 0x00000008 */

+#define OCTOSPI_CCR_IDTR               OCTOSPI_CCR_IDTR_Msk                    /*!< Instruction Double Transfer Rate */

+#define OCTOSPI_CCR_ISIZE_Pos          (4U)

+#define OCTOSPI_CCR_ISIZE_Msk          (0x3UL << OCTOSPI_CCR_ISIZE_Pos)         /*!< 0x00000030 */

+#define OCTOSPI_CCR_ISIZE              OCTOSPI_CCR_ISIZE_Msk                   /*!< Instruction Size */

+#define OCTOSPI_CCR_ISIZE_0            (0x1UL << OCTOSPI_CCR_ISIZE_Pos)         /*!< 0x00000010 */

+#define OCTOSPI_CCR_ISIZE_1            (0x2UL << OCTOSPI_CCR_ISIZE_Pos)         /*!< 0x00000020 */

+#define OCTOSPI_CCR_ADMODE_Pos         (8U)

+#define OCTOSPI_CCR_ADMODE_Msk         (0x7UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000700 */

+#define OCTOSPI_CCR_ADMODE             OCTOSPI_CCR_ADMODE_Msk                  /*!< Address Mode */

+#define OCTOSPI_CCR_ADMODE_0           (0x1UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000100 */

+#define OCTOSPI_CCR_ADMODE_1           (0x2UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000200 */

+#define OCTOSPI_CCR_ADMODE_2           (0x4UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000400 */

+#define OCTOSPI_CCR_ADDTR_Pos          (11U)

+#define OCTOSPI_CCR_ADDTR_Msk          (0x1UL << OCTOSPI_CCR_ADDTR_Pos)         /*!< 0x00000800 */

+#define OCTOSPI_CCR_ADDTR              OCTOSPI_CCR_ADDTR_Msk                   /*!< Address Double Transfer Rate */

+#define OCTOSPI_CCR_ADSIZE_Pos         (12U)

+#define OCTOSPI_CCR_ADSIZE_Msk         (0x3UL << OCTOSPI_CCR_ADSIZE_Pos)        /*!< 0x00003000 */

+#define OCTOSPI_CCR_ADSIZE             OCTOSPI_CCR_ADSIZE_Msk                  /*!< Address Size */

+#define OCTOSPI_CCR_ADSIZE_0           (0x1UL << OCTOSPI_CCR_ADSIZE_Pos)        /*!< 0x00001000 */

+#define OCTOSPI_CCR_ADSIZE_1           (0x2UL << OCTOSPI_CCR_ADSIZE_Pos)        /*!< 0x00002000 */

+#define OCTOSPI_CCR_ABMODE_Pos         (16U)

+#define OCTOSPI_CCR_ABMODE_Msk         (0x7UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00070000 */

+#define OCTOSPI_CCR_ABMODE             OCTOSPI_CCR_ABMODE_Msk                  /*!< Alternate Bytes Mode */

+#define OCTOSPI_CCR_ABMODE_0           (0x1UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00010000 */

+#define OCTOSPI_CCR_ABMODE_1           (0x2UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00020000 */

+#define OCTOSPI_CCR_ABMODE_2           (0x4UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00040000 */

+#define OCTOSPI_CCR_ABDTR_Pos          (19U)

+#define OCTOSPI_CCR_ABDTR_Msk          (0x1UL << OCTOSPI_CCR_ABDTR_Pos)         /*!< 0x00080000 */

+#define OCTOSPI_CCR_ABDTR              OCTOSPI_CCR_ABDTR_Msk                   /*!< Alternate Bytes Double Transfer Rate */

+#define OCTOSPI_CCR_ABSIZE_Pos         (20U)

+#define OCTOSPI_CCR_ABSIZE_Msk         (0x3UL << OCTOSPI_CCR_ABSIZE_Pos)        /*!< 0x00300000 */

+#define OCTOSPI_CCR_ABSIZE             OCTOSPI_CCR_ABSIZE_Msk                  /*!< Alternate Bytes Size */

+#define OCTOSPI_CCR_ABSIZE_0           (0x1UL << OCTOSPI_CCR_ABSIZE_Pos)        /*!< 0x00100000 */

+#define OCTOSPI_CCR_ABSIZE_1           (0x2UL << OCTOSPI_CCR_ABSIZE_Pos)        /*!< 0x00200000 */

+#define OCTOSPI_CCR_DMODE_Pos          (24U)

+#define OCTOSPI_CCR_DMODE_Msk          (0x7UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x07000000 */

+#define OCTOSPI_CCR_DMODE              OCTOSPI_CCR_DMODE_Msk                   /*!< Data Mode */

+#define OCTOSPI_CCR_DMODE_0            (0x1UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x01000000 */

+#define OCTOSPI_CCR_DMODE_1            (0x2UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x02000000 */

+#define OCTOSPI_CCR_DMODE_2            (0x4UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x04000000 */

+#define OCTOSPI_CCR_DDTR_Pos           (27U)

+#define OCTOSPI_CCR_DDTR_Msk           (0x1UL << OCTOSPI_CCR_DDTR_Pos)          /*!< 0x08000000 */

+#define OCTOSPI_CCR_DDTR               OCTOSPI_CCR_DDTR_Msk                    /*!< Data Double Transfer Rate */

+#define OCTOSPI_CCR_DQSE_Pos           (29U)

+#define OCTOSPI_CCR_DQSE_Msk           (0x1UL << OCTOSPI_CCR_DQSE_Pos)          /*!< 0x20000000 */

+#define OCTOSPI_CCR_DQSE               OCTOSPI_CCR_DQSE_Msk                    /*!< DQS Enable */

+#define OCTOSPI_CCR_SIOO_Pos           (31U)

+#define OCTOSPI_CCR_SIOO_Msk           (0x1UL << OCTOSPI_CCR_SIOO_Pos)          /*!< 0x80000000 */

+#define OCTOSPI_CCR_SIOO               OCTOSPI_CCR_SIOO_Msk                    /*!< Send Instruction Only Once Mode */

+

+/****************  Bit definition for OCTOSPI_TCR register  *******************/

+#define OCTOSPI_TCR_DCYC_Pos           (0U)

+#define OCTOSPI_TCR_DCYC_Msk           (0x1FUL << OCTOSPI_TCR_DCYC_Pos)         /*!< 0x0000001F */

+#define OCTOSPI_TCR_DCYC               OCTOSPI_TCR_DCYC_Msk                    /*!< Number of Dummy Cycles */

+#define OCTOSPI_TCR_DHQC_Pos           (28U)

+#define OCTOSPI_TCR_DHQC_Msk           (0x1UL << OCTOSPI_TCR_DHQC_Pos)          /*!< 0x10000000 */

+#define OCTOSPI_TCR_DHQC               OCTOSPI_TCR_DHQC_Msk                    /*!< Delay Hold Quarter Cycle */

+#define OCTOSPI_TCR_SSHIFT_Pos         (30U)

+#define OCTOSPI_TCR_SSHIFT_Msk         (0x1UL << OCTOSPI_TCR_SSHIFT_Pos)        /*!< 0x40000000 */

+#define OCTOSPI_TCR_SSHIFT             OCTOSPI_TCR_SSHIFT_Msk                  /*!< Sample Shift */

+

+/*****************  Bit definition for OCTOSPI_IR register  *******************/

+#define OCTOSPI_IR_INSTRUCTION_Pos     (0U)

+#define OCTOSPI_IR_INSTRUCTION_Msk     (0xFFFFFFFFUL << OCTOSPI_IR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_IR_INSTRUCTION         OCTOSPI_IR_INSTRUCTION_Msk              /*!< Instruction */

+

+/****************  Bit definition for OCTOSPI_ABR register  *******************/

+#define OCTOSPI_ABR_ALTERNATE_Pos      (0U)

+#define OCTOSPI_ABR_ALTERNATE_Msk      (0xFFFFFFFFUL << OCTOSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_ABR_ALTERNATE          OCTOSPI_ABR_ALTERNATE_Msk               /*!< Alternate Bytes */

+

+/****************  Bit definition for OCTOSPI_LPTR register  ******************/

+#define OCTOSPI_LPTR_TIMEOUT_Pos       (0U)

+#define OCTOSPI_LPTR_TIMEOUT_Msk       (0xFFFFUL << OCTOSPI_LPTR_TIMEOUT_Pos)   /*!< 0x0000FFFF */

+#define OCTOSPI_LPTR_TIMEOUT           OCTOSPI_LPTR_TIMEOUT_Msk                /*!< Timeout period */

+

+/****************  Bit definition for OCTOSPI_WPCCR register  *******************/

+#define OCTOSPI_WPCCR_IMODE_Pos        (0U)

+#define OCTOSPI_WPCCR_IMODE_Msk        (0x7UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000007 */

+#define OCTOSPI_WPCCR_IMODE            OCTOSPI_WPCCR_IMODE_Msk                 /*!< Instruction Mode */

+#define OCTOSPI_WPCCR_IMODE_0          (0x1UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000001 */

+#define OCTOSPI_WPCCR_IMODE_1          (0x2UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000002 */

+#define OCTOSPI_WPCCR_IMODE_2          (0x4UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000004 */

+#define OCTOSPI_WPCCR_IDTR_Pos         (3U)

+#define OCTOSPI_WPCCR_IDTR_Msk         (0x1UL << OCTOSPI_WPCCR_IDTR_Pos)        /*!< 0x00000008 */

+#define OCTOSPI_WPCCR_IDTR             OCTOSPI_WPCCR_IDTR_Msk                  /*!< Instruction Double Transfer Rate */

+#define OCTOSPI_WPCCR_ISIZE_Pos        (4U)

+#define OCTOSPI_WPCCR_ISIZE_Msk        (0x3UL << OCTOSPI_WPCCR_ISIZE_Pos)       /*!< 0x00000030 */

+#define OCTOSPI_WPCCR_ISIZE            OCTOSPI_WPCCR_ISIZE_Msk                 /*!< Instruction Size */

+#define OCTOSPI_WPCCR_ISIZE_0          (0x1UL << OCTOSPI_WPCCR_ISIZE_Pos)       /*!< 0x00000010 */

+#define OCTOSPI_WPCCR_ISIZE_1          (0x2UL << OCTOSPI_WPCCR_ISIZE_Pos)       /*!< 0x00000020 */

+#define OCTOSPI_WPCCR_ADMODE_Pos       (8U)

+#define OCTOSPI_WPCCR_ADMODE_Msk       (0x7UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000700 */

+#define OCTOSPI_WPCCR_ADMODE           OCTOSPI_WPCCR_ADMODE_Msk                /*!< Address Mode */

+#define OCTOSPI_WPCCR_ADMODE_0         (0x1UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000100 */

+#define OCTOSPI_WPCCR_ADMODE_1         (0x2UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000200 */

+#define OCTOSPI_WPCCR_ADMODE_2         (0x4UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000400 */

+#define OCTOSPI_WPCCR_ADDTR_Pos        (11U)

+#define OCTOSPI_WPCCR_ADDTR_Msk        (0x1UL << OCTOSPI_WPCCR_ADDTR_Pos)       /*!< 0x00000800 */

+#define OCTOSPI_WPCCR_ADDTR            OCTOSPI_WPCCR_ADDTR_Msk                 /*!< Address Double Transfer Rate */

+#define OCTOSPI_WPCCR_ADSIZE_Pos       (12U)

+#define OCTOSPI_WPCCR_ADSIZE_Msk       (0x3UL << OCTOSPI_WPCCR_ADSIZE_Pos)      /*!< 0x00003000 */

+#define OCTOSPI_WPCCR_ADSIZE           OCTOSPI_WPCCR_ADSIZE_Msk                /*!< Address Size */

+#define OCTOSPI_WPCCR_ADSIZE_0         (0x1UL << OCTOSPI_WPCCR_ADSIZE_Pos)      /*!< 0x00001000 */

+#define OCTOSPI_WPCCR_ADSIZE_1         (0x2UL << OCTOSPI_WPCCR_ADSIZE_Pos)      /*!< 0x00002000 */

+#define OCTOSPI_WPCCR_ABMODE_Pos       (16U)

+#define OCTOSPI_WPCCR_ABMODE_Msk       (0x7UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00070000 */

+#define OCTOSPI_WPCCR_ABMODE           OCTOSPI_WPCCR_ABMODE_Msk                /*!< Alternate Bytes Mode */

+#define OCTOSPI_WPCCR_ABMODE_0         (0x1UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00010000 */

+#define OCTOSPI_WPCCR_ABMODE_1         (0x2UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00020000 */

+#define OCTOSPI_WPCCR_ABMODE_2         (0x4UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00040000 */

+#define OCTOSPI_WPCCR_ABDTR_Pos        (19U)

+#define OCTOSPI_WPCCR_ABDTR_Msk        (0x1UL << OCTOSPI_WPCCR_ABDTR_Pos)       /*!< 0x00080000 */

+#define OCTOSPI_WPCCR_ABDTR            OCTOSPI_WPCCR_ABDTR_Msk                 /*!< Alternate Bytes Double Transfer Rate */

+#define OCTOSPI_WPCCR_ABSIZE_Pos       (20U)

+#define OCTOSPI_WPCCR_ABSIZE_Msk       (0x3UL << OCTOSPI_WPCCR_ABSIZE_Pos)      /*!< 0x00300000 */

+#define OCTOSPI_WPCCR_ABSIZE           OCTOSPI_WPCCR_ABSIZE_Msk                /*!< Alternate Bytes Size */

+#define OCTOSPI_WPCCR_ABSIZE_0         (0x1UL << OCTOSPI_WPCCR_ABSIZE_Pos)      /*!< 0x00100000 */

+#define OCTOSPI_WPCCR_ABSIZE_1         (0x2UL << OCTOSPI_WPCCR_ABSIZE_Pos)      /*!< 0x00200000 */

+#define OCTOSPI_WPCCR_DMODE_Pos        (24U)

+#define OCTOSPI_WPCCR_DMODE_Msk        (0x7UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x07000000 */

+#define OCTOSPI_WPCCR_DMODE            OCTOSPI_WPCCR_DMODE_Msk                 /*!< Data Mode */

+#define OCTOSPI_WPCCR_DMODE_0          (0x1UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x01000000 */

+#define OCTOSPI_WPCCR_DMODE_1          (0x2UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x02000000 */

+#define OCTOSPI_WPCCR_DMODE_2          (0x4UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x04000000 */

+#define OCTOSPI_WPCCR_DDTR_Pos         (27U)

+#define OCTOSPI_WPCCR_DDTR_Msk         (0x1UL << OCTOSPI_WPCCR_DDTR_Pos)        /*!< 0x08000000 */

+#define OCTOSPI_WPCCR_DDTR             OCTOSPI_WPCCR_DDTR_Msk                  /*!< Data Double Transfer Rate */

+#define OCTOSPI_WPCCR_DQSE_Pos         (29U)

+#define OCTOSPI_WPCCR_DQSE_Msk         (0x1UL << OCTOSPI_WPCCR_DQSE_Pos)        /*!< 0x20000000 */

+#define OCTOSPI_WPCCR_DQSE             OCTOSPI_WPCCR_DQSE_Msk                  /*!< DQS Enable */

+#define OCTOSPI_WPCCR_SIOO_Pos         (31U)

+#define OCTOSPI_WPCCR_SIOO_Msk         (0x1UL << OCTOSPI_WPCCR_SIOO_Pos)        /*!< 0x80000000 */

+#define OCTOSPI_WPCCR_SIOO             OCTOSPI_WPCCR_SIOO_Msk                  /*!< Send Instruction Only Once Mode */

+

+/****************  Bit definition for OCTOSPI_WPTCR register  *******************/

+#define OCTOSPI_WPTCR_DCYC_Pos         (0U)

+#define OCTOSPI_WPTCR_DCYC_Msk         (0x1FUL << OCTOSPI_WPTCR_DCYC_Pos)       /*!< 0x0000001F */

+#define OCTOSPI_WPTCR_DCYC             OCTOSPI_WPTCR_DCYC_Msk                  /*!< Number of Dummy Cycles */

+#define OCTOSPI_WPTCR_DHQC_Pos         (28U)

+#define OCTOSPI_WPTCR_DHQC_Msk         (0x1UL << OCTOSPI_WPTCR_DHQC_Pos)        /*!< 0x10000000 */

+#define OCTOSPI_WPTCR_DHQC             OCTOSPI_WPTCR_DHQC_Msk                  /*!< Delay Hold Quarter Cycle */

+#define OCTOSPI_WPTCR_SSHIFT_Pos       (30U)

+#define OCTOSPI_WPTCR_SSHIFT_Msk       (0x1UL << OCTOSPI_WPTCR_SSHIFT_Pos)      /*!< 0x40000000 */

+#define OCTOSPI_WPTCR_SSHIFT           OCTOSPI_WPTCR_SSHIFT_Msk                /*!< Sample Shift */

+

+/*****************  Bit definition for OCTOSPI_WPIR register  *******************/

+#define OCTOSPI_WPIR_INSTRUCTION_Pos   (0U)

+#define OCTOSPI_WPIR_INSTRUCTION_Msk   (0xFFFFFFFFUL << OCTOSPI_WPIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_WPIR_INSTRUCTION       OCTOSPI_WPIR_INSTRUCTION_Msk            /*!< Instruction */

+

+/****************  Bit definition for OCTOSPI_WPABR register  *******************/

+#define OCTOSPI_WPABR_ALTERNATE_Pos    (0U)

+#define OCTOSPI_WPABR_ALTERNATE_Msk    (0xFFFFFFFFUL << OCTOSPI_WPABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_WPABR_ALTERNATE        OCTOSPI_WPABR_ALTERNATE_Msk             /*!< Alternate Bytes */

+

+/****************  Bit definition for OCTOSPI_WCCR register  ******************/

+#define OCTOSPI_WCCR_IMODE_Pos         (0U)

+#define OCTOSPI_WCCR_IMODE_Msk         (0x7UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000007 */

+#define OCTOSPI_WCCR_IMODE             OCTOSPI_WCCR_IMODE_Msk                  /*!< Instruction Mode */

+#define OCTOSPI_WCCR_IMODE_0           (0x1UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000001 */

+#define OCTOSPI_WCCR_IMODE_1           (0x2UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000002 */

+#define OCTOSPI_WCCR_IMODE_2           (0x4UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000004 */

+#define OCTOSPI_WCCR_IDTR_Pos          (3U)

+#define OCTOSPI_WCCR_IDTR_Msk          (0x1UL << OCTOSPI_WCCR_IDTR_Pos)         /*!< 0x00000008 */

+#define OCTOSPI_WCCR_IDTR              OCTOSPI_WCCR_IDTR_Msk                   /*!< Instruction Double Transfer Rate */

+#define OCTOSPI_WCCR_ISIZE_Pos         (4U)

+#define OCTOSPI_WCCR_ISIZE_Msk         (0x3UL << OCTOSPI_WCCR_ISIZE_Pos)        /*!< 0x00000030 */

+#define OCTOSPI_WCCR_ISIZE             OCTOSPI_WCCR_ISIZE_Msk                  /*!< Instruction Size */

+#define OCTOSPI_WCCR_ISIZE_0           (0x1UL << OCTOSPI_WCCR_ISIZE_Pos)        /*!< 0x00000010 */

+#define OCTOSPI_WCCR_ISIZE_1           (0x2UL << OCTOSPI_WCCR_ISIZE_Pos)        /*!< 0x00000020 */

+#define OCTOSPI_WCCR_ADMODE_Pos        (8U)

+#define OCTOSPI_WCCR_ADMODE_Msk        (0x7UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000700 */

+#define OCTOSPI_WCCR_ADMODE            OCTOSPI_WCCR_ADMODE_Msk                 /*!< Address Mode */

+#define OCTOSPI_WCCR_ADMODE_0          (0x1UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000100 */

+#define OCTOSPI_WCCR_ADMODE_1          (0x2UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000200 */

+#define OCTOSPI_WCCR_ADMODE_2          (0x4UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000400 */

+#define OCTOSPI_WCCR_ADDTR_Pos         (11U)

+#define OCTOSPI_WCCR_ADDTR_Msk         (0x1UL << OCTOSPI_WCCR_ADDTR_Pos)        /*!< 0x00000800 */

+#define OCTOSPI_WCCR_ADDTR             OCTOSPI_WCCR_ADDTR_Msk                  /*!< Address Double Transfer Rate */

+#define OCTOSPI_WCCR_ADSIZE_Pos        (12U)

+#define OCTOSPI_WCCR_ADSIZE_Msk        (0x3UL << OCTOSPI_WCCR_ADSIZE_Pos)       /*!< 0x00003000 */

+#define OCTOSPI_WCCR_ADSIZE            OCTOSPI_WCCR_ADSIZE_Msk                 /*!< Address Size */

+#define OCTOSPI_WCCR_ADSIZE_0          (0x1UL << OCTOSPI_WCCR_ADSIZE_Pos)       /*!< 0x00001000 */

+#define OCTOSPI_WCCR_ADSIZE_1          (0x2UL << OCTOSPI_WCCR_ADSIZE_Pos)       /*!< 0x00002000 */

+#define OCTOSPI_WCCR_ABMODE_Pos        (16U)

+#define OCTOSPI_WCCR_ABMODE_Msk        (0x7UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00070000 */

+#define OCTOSPI_WCCR_ABMODE            OCTOSPI_WCCR_ABMODE_Msk                 /*!< Alternate Bytes Mode */

+#define OCTOSPI_WCCR_ABMODE_0          (0x1UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00010000 */

+#define OCTOSPI_WCCR_ABMODE_1          (0x2UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00020000 */

+#define OCTOSPI_WCCR_ABMODE_2          (0x4UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00040000 */

+#define OCTOSPI_WCCR_ABDTR_Pos         (19U)

+#define OCTOSPI_WCCR_ABDTR_Msk         (0x1UL << OCTOSPI_WCCR_ABDTR_Pos)        /*!< 0x00080000 */

+#define OCTOSPI_WCCR_ABDTR             OCTOSPI_WCCR_ABDTR_Msk                  /*!< Alternate Bytes Double Transfer Rate */

+#define OCTOSPI_WCCR_ABSIZE_Pos        (20U)

+#define OCTOSPI_WCCR_ABSIZE_Msk        (0x3UL << OCTOSPI_WCCR_ABSIZE_Pos)       /*!< 0x00300000 */

+#define OCTOSPI_WCCR_ABSIZE            OCTOSPI_WCCR_ABSIZE_Msk                 /*!< Alternate Bytes Size */

+#define OCTOSPI_WCCR_ABSIZE_0          (0x1UL << OCTOSPI_WCCR_ABSIZE_Pos)       /*!< 0x00100000 */

+#define OCTOSPI_WCCR_ABSIZE_1          (0x2UL << OCTOSPI_WCCR_ABSIZE_Pos)       /*!< 0x00200000 */

+#define OCTOSPI_WCCR_DMODE_Pos         (24U)

+#define OCTOSPI_WCCR_DMODE_Msk         (0x7UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x07000000 */

+#define OCTOSPI_WCCR_DMODE             OCTOSPI_WCCR_DMODE_Msk                  /*!< Data Mode */

+#define OCTOSPI_WCCR_DMODE_0           (0x1UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x01000000 */

+#define OCTOSPI_WCCR_DMODE_1           (0x2UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x02000000 */

+#define OCTOSPI_WCCR_DMODE_2           (0x4UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x04000000 */

+#define OCTOSPI_WCCR_DDTR_Pos          (27U)

+#define OCTOSPI_WCCR_DDTR_Msk          (0x1UL << OCTOSPI_WCCR_DDTR_Pos)         /*!< 0x08000000 */

+#define OCTOSPI_WCCR_DDTR              OCTOSPI_WCCR_DDTR_Msk                   /*!< Data Double Transfer Rate */

+#define OCTOSPI_WCCR_DQSE_Pos          (29U)

+#define OCTOSPI_WCCR_DQSE_Msk          (0x1UL << OCTOSPI_WCCR_DQSE_Pos)         /*!< 0x20000000 */

+#define OCTOSPI_WCCR_DQSE              OCTOSPI_WCCR_DQSE_Msk                   /*!< DQS Enable */

+#define OCTOSPI_WCCR_SIOO_Pos          (31U)

+#define OCTOSPI_WCCR_SIOO_Msk          (0x1UL << OCTOSPI_WCCR_SIOO_Pos)         /*!< 0x80000000 */

+#define OCTOSPI_WCCR_SIOO              OCTOSPI_WCCR_SIOO_Msk                   /*!< Send Instruction Only Once Mode */

+

+/****************  Bit definition for OCTOSPI_WTCR register  ******************/

+#define OCTOSPI_WTCR_DCYC_Pos          (0U)

+#define OCTOSPI_WTCR_DCYC_Msk          (0x1FUL << OCTOSPI_WTCR_DCYC_Pos)        /*!< 0x0000001F */

+#define OCTOSPI_WTCR_DCYC              OCTOSPI_WTCR_DCYC_Msk                   /*!< Number of Dummy Cycles */

+

+/****************  Bit definition for OCTOSPI_WIR register  *******************/

+#define OCTOSPI_WIR_INSTRUCTION_Pos    (0U)

+#define OCTOSPI_WIR_INSTRUCTION_Msk    (0xFFFFFFFFUL << OCTOSPI_WIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_WIR_INSTRUCTION        OCTOSPI_WIR_INSTRUCTION_Msk             /*!< Instruction */

+

+/****************  Bit definition for OCTOSPI_WABR register  ******************/

+#define OCTOSPI_WABR_ALTERNATE_Pos     (0U)

+#define OCTOSPI_WABR_ALTERNATE_Msk     (0xFFFFFFFFUL << OCTOSPI_WABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_WABR_ALTERNATE         OCTOSPI_WABR_ALTERNATE_Msk              /*!< Alternate Bytes */

+

+/****************  Bit definition for OCTOSPI_HLCR register  ******************/

+#define OCTOSPI_HLCR_LM_Pos            (0U)

+#define OCTOSPI_HLCR_LM_Msk            (0x1UL << OCTOSPI_HLCR_LM_Pos)           /*!< 0x00000001 */

+#define OCTOSPI_HLCR_LM                OCTOSPI_HLCR_LM_Msk                     /*!< Latency Mode */

+#define OCTOSPI_HLCR_WZL_Pos           (1U)

+#define OCTOSPI_HLCR_WZL_Msk           (0x1UL << OCTOSPI_HLCR_WZL_Pos)          /*!< 0x00000002 */

+#define OCTOSPI_HLCR_WZL               OCTOSPI_HLCR_WZL_Msk                    /*!< Write Zero Latency */

+#define OCTOSPI_HLCR_TACC_Pos          (8U)

+#define OCTOSPI_HLCR_TACC_Msk          (0xFFUL << OCTOSPI_HLCR_TACC_Pos)        /*!< 0x0000FF00 */

+#define OCTOSPI_HLCR_TACC              OCTOSPI_HLCR_TACC_Msk                   /*!< Access Time */

+#define OCTOSPI_HLCR_TRWR_Pos          (16U)

+#define OCTOSPI_HLCR_TRWR_Msk          (0xFFUL << OCTOSPI_HLCR_TRWR_Pos)        /*!< 0x00FF0000 */

+#define OCTOSPI_HLCR_TRWR              OCTOSPI_HLCR_TRWR_Msk                   /*!< Read Write Recovery Time */

+

+/****************  Bit definition for OCTOSPI_VER register  *******************/

+#define OCTOSPI_VER_VER_Pos            (0U)

+#define OCTOSPI_VER_VER_Msk            (0xFFUL << OCTOSPI_VER_VER_Pos)          /*!< 0x000000FF */

+#define OCTOSPI_VER_VER                OCTOSPI_VER_VER_Msk                     /*!< Version */

+

+/*****************  Bit definition for OCTOSPI_ID register  *******************/

+#define OCTOSPI_ID_ID_Pos              (0U)

+#define OCTOSPI_ID_ID_Msk              (0xFFFFFFFFUL << OCTOSPI_ID_ID_Pos)      /*!< 0xFFFFFFFF */

+#define OCTOSPI_ID_ID                  OCTOSPI_ID_ID_Msk                       /*!< Identification */

+

+/****************  Bit definition for OCTOSPI_MID register  *******************/

+#define OCTOSPI_MID_MID_Pos            (0U)

+#define OCTOSPI_MID_MID_Msk            (0xFFFFFFFFUL << OCTOSPI_MID_MID_Pos)    /*!< 0xFFFFFFFF */

+#define OCTOSPI_MID_MID                OCTOSPI_MID_MID_Msk                     /*!< Magic ID */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                  OCTOSPIM                                  */

+/*                                                                            */

+/******************************************************************************/

+

+/***************  Bit definition for OCTOSPIM_CR register  ********************/

+#define OCTOSPIM_CR_MUXEN_Pos          (0U)

+#define OCTOSPIM_CR_MUXEN_Msk          (0x1UL << OCTOSPIM_CR_MUXEN_Pos)        /*!< 0x00000001 */

+#define OCTOSPIM_CR_MUXEN              OCTOSPIM_CR_MUXEN_Msk                   /*!< Multiplexed mode enable */

+#define OCTOSPIM_CR_REQ2ACK_TIME_Pos   (16U)

+#define OCTOSPIM_CR_REQ2ACK_TIME_Msk   (0xFFUL << OCTOSPIM_CR_REQ2ACK_TIME_Pos)/*!< 0x00FF0000 */

+#define OCTOSPIM_CR_REQ2ACK_TIME       OCTOSPIM_CR_REQ2ACK_TIME_Msk            /*!< REQ to ACK time */

+

+/***************  Bit definition for OCTOSPIM_PCR register  *******************/

+#define OCTOSPIM_PCR_CLKEN_Pos         (0U)

+#define OCTOSPIM_PCR_CLKEN_Msk         (0x1UL << OCTOSPIM_PCR_CLKEN_Pos)        /*!< 0x00000001 */

+#define OCTOSPIM_PCR_CLKEN             OCTOSPIM_PCR_CLKEN_Msk                   /*!< CLK/CLKn Enable for Port n */

+#define OCTOSPIM_PCR_CLKSRC_Pos        (1U)

+#define OCTOSPIM_PCR_CLKSRC_Msk        (0x1UL << OCTOSPIM_PCR_CLKSRC_Pos)       /*!< 0x00000002 */

+#define OCTOSPIM_PCR_CLKSRC            OCTOSPIM_PCR_CLKSRC_Msk                  /*!< CLK/CLKn Source for Port n */

+#define OCTOSPIM_PCR_DQSEN_Pos         (4U)

+#define OCTOSPIM_PCR_DQSEN_Msk         (0x1UL << OCTOSPIM_PCR_DQSEN_Pos)        /*!< 0x00000010 */

+#define OCTOSPIM_PCR_DQSEN             OCTOSPIM_PCR_DQSEN_Msk                   /*!< DQS Enable for Port n */

+#define OCTOSPIM_PCR_DQSSRC_Pos        (5U)

+#define OCTOSPIM_PCR_DQSSRC_Msk        (0x1UL << OCTOSPIM_PCR_DQSSRC_Pos)       /*!< 0x00000020 */

+#define OCTOSPIM_PCR_DQSSRC            OCTOSPIM_PCR_DQSSRC_Msk                  /*!< DQS Source for Port n */

+#define OCTOSPIM_PCR_NCSEN_Pos         (8U)

+#define OCTOSPIM_PCR_NCSEN_Msk         (0x1UL << OCTOSPIM_PCR_NCSEN_Pos)        /*!< 0x00000100 */

+#define OCTOSPIM_PCR_NCSEN             OCTOSPIM_PCR_NCSEN_Msk                   /*!< nCS Enable for Port n */

+#define OCTOSPIM_PCR_NCSSRC_Pos        (9U)

+#define OCTOSPIM_PCR_NCSSRC_Msk        (0x1UL << OCTOSPIM_PCR_NCSSRC_Pos)       /*!< 0x00000200 */

+#define OCTOSPIM_PCR_NCSSRC            OCTOSPIM_PCR_NCSSRC_Msk                  /*!< nCS Source for Port n */

+#define OCTOSPIM_PCR_IOLEN_Pos         (16U)

+#define OCTOSPIM_PCR_IOLEN_Msk         (0x1UL << OCTOSPIM_PCR_IOLEN_Pos)        /*!< 0x00010000 */

+#define OCTOSPIM_PCR_IOLEN             OCTOSPIM_PCR_IOLEN_Msk                   /*!< IO[3:0] Enable for Port n */

+#define OCTOSPIM_PCR_IOLSRC_Pos        (17U)

+#define OCTOSPIM_PCR_IOLSRC_Msk        (0x3UL << OCTOSPIM_PCR_IOLSRC_Pos)       /*!< 0x00060000 */

+#define OCTOSPIM_PCR_IOLSRC            OCTOSPIM_PCR_IOLSRC_Msk                  /*!< IO[3:0] Source for Port n */

+#define OCTOSPIM_PCR_IOLSRC_0          (0x1UL << OCTOSPIM_PCR_IOLSRC_Pos)       /*!< 0x00020000 */

+#define OCTOSPIM_PCR_IOLSRC_1          (0x2UL << OCTOSPIM_PCR_IOLSRC_Pos)       /*!< 0x00040000 */

+#define OCTOSPIM_PCR_IOHEN_Pos         (24U)

+#define OCTOSPIM_PCR_IOHEN_Msk         (0x1UL << OCTOSPIM_PCR_IOHEN_Pos)        /*!< 0x01000000 */

+#define OCTOSPIM_PCR_IOHEN             OCTOSPIM_PCR_IOHEN_Msk                   /*!< IO[7:4] Enable for Port n */

+#define OCTOSPIM_PCR_IOHSRC_Pos        (25U)

+#define OCTOSPIM_PCR_IOHSRC_Msk        (0x3UL << OCTOSPIM_PCR_IOHSRC_Pos)       /*!< 0x06000000 */

+#define OCTOSPIM_PCR_IOHSRC            OCTOSPIM_PCR_IOHSRC_Msk                  /*!< IO[7:4] Source for Port n */

+#define OCTOSPIM_PCR_IOHSRC_0          (0x1UL << OCTOSPIM_PCR_IOHSRC_Pos)       /*!< 0x02000000 */

+#define OCTOSPIM_PCR_IOHSRC_1          (0x2UL << OCTOSPIM_PCR_IOHSRC_Pos)       /*!< 0x04000000 */

+/******************************************************************************/

+/*                                                                            */

+/*                      Analog Comparators (COMP)                             */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for COMP_SR register  ********************/

+#define COMP_SR_C1VAL_Pos            (0U)

+#define COMP_SR_C1VAL_Msk            (0x1UL << COMP_SR_C1VAL_Pos)              /*!< 0x00000001 */

+#define COMP_SR_C1VAL                COMP_SR_C1VAL_Msk

+#define COMP_SR_C2VAL_Pos            (1U)

+#define COMP_SR_C2VAL_Msk            (0x1UL << COMP_SR_C2VAL_Pos)              /*!< 0x00000002 */

+#define COMP_SR_C2VAL                COMP_SR_C2VAL_Msk

+#define COMP_SR_C1IF_Pos             (16U)

+#define COMP_SR_C1IF_Msk             (0x1UL << COMP_SR_C1IF_Pos)               /*!< 0x00010000 */

+#define COMP_SR_C1IF                 COMP_SR_C1IF_Msk

+#define COMP_SR_C2IF_Pos             (17U)

+#define COMP_SR_C2IF_Msk             (0x1UL << COMP_SR_C2IF_Pos)               /*!< 0x00020000 */

+#define COMP_SR_C2IF                 COMP_SR_C2IF_Msk

+/*******************  Bit definition for COMP_ICFR register  ********************/

+#define COMP_ICFR_C1IF_Pos           (16U)

+#define COMP_ICFR_C1IF_Msk           (0x1UL << COMP_ICFR_C1IF_Pos)             /*!< 0x00010000 */

+#define COMP_ICFR_C1IF               COMP_ICFR_C1IF_Msk

+#define COMP_ICFR_C2IF_Pos           (17U)

+#define COMP_ICFR_C2IF_Msk           (0x1UL << COMP_ICFR_C2IF_Pos)             /*!< 0x00020000 */

+#define COMP_ICFR_C2IF               COMP_ICFR_C2IF_Msk

+/*******************  Bit definition for COMP_OR register  ********************/

+#define COMP_OR_AFOPA6_Pos           (0U)

+#define COMP_OR_AFOPA6_Msk           (0x1UL << COMP_OR_AFOPA6_Pos)             /*!< 0x00000001 */

+#define COMP_OR_AFOPA6               COMP_OR_AFOPA6_Msk

+#define COMP_OR_AFOPA8_Pos           (1U)

+#define COMP_OR_AFOPA8_Msk           (0x1UL << COMP_OR_AFOPA8_Pos)             /*!< 0x00000002 */

+#define COMP_OR_AFOPA8               COMP_OR_AFOPA8_Msk

+#define COMP_OR_AFOPB12_Pos          (2U)

+#define COMP_OR_AFOPB12_Msk          (0x1UL << COMP_OR_AFOPB12_Pos)            /*!< 0x00000004 */

+#define COMP_OR_AFOPB12              COMP_OR_AFOPB12_Msk

+#define COMP_OR_AFOPE6_Pos           (3U)

+#define COMP_OR_AFOPE6_Msk           (0x1UL << COMP_OR_AFOPE6_Pos)             /*!< 0x00000008 */

+#define COMP_OR_AFOPE6               COMP_OR_AFOPE6_Msk

+#define COMP_OR_AFOPE15_Pos          (4U)

+#define COMP_OR_AFOPE15_Msk          (0x1UL << COMP_OR_AFOPE15_Pos)            /*!< 0x00000010 */

+#define COMP_OR_AFOPE15              COMP_OR_AFOPE15_Msk

+#define COMP_OR_AFOPG2_Pos           (5U)

+#define COMP_OR_AFOPG2_Msk           (0x1UL << COMP_OR_AFOPG2_Pos)             /*!< 0x00000020 */

+#define COMP_OR_AFOPG2               COMP_OR_AFOPG2_Msk

+#define COMP_OR_AFOPG3_Pos           (6U)

+#define COMP_OR_AFOPG3_Msk           (0x1UL << COMP_OR_AFOPG3_Pos)             /*!< 0x00000040 */

+#define COMP_OR_AFOPG3               COMP_OR_AFOPG3_Msk

+#define COMP_OR_AFOPG4_Pos           (7U)

+#define COMP_OR_AFOPG4_Msk           (0x1UL << COMP_OR_AFOPG4_Pos)             /*!< 0x00000080 */

+#define COMP_OR_AFOPG4               COMP_OR_AFOPG4_Msk

+#define COMP_OR_AFOPI1_Pos           (8U)

+#define COMP_OR_AFOPI1_Msk           (0x1UL << COMP_OR_AFOPI1_Pos)             /*!< 0x00000100 */

+#define COMP_OR_AFOPI1               COMP_OR_AFOPI1_Msk

+#define COMP_OR_AFOPI4_Pos           (9U)

+#define COMP_OR_AFOPI4_Msk           (0x1UL << COMP_OR_AFOPI4_Pos)             /*!< 0x00000200 */

+#define COMP_OR_AFOPI4               COMP_OR_AFOPI4_Msk

+#define COMP_OR_AFOPK2_Pos           (10U)

+#define COMP_OR_AFOPK2_Msk           (0x1UL << COMP_OR_AFOPK2_Pos)             /*!< 0x00000400 */

+#define COMP_OR_AFOPK2               COMP_OR_AFOPK2_Msk

+

+/*!< ******************  Bit definition for COMP_CFGRx register  ********************/

+#define COMP_CFGRx_EN_Pos            (0U)

+#define COMP_CFGRx_EN_Msk            (0x1UL << COMP_CFGRx_EN_Pos)              /*!< 0x00000001 */

+#define COMP_CFGRx_EN                COMP_CFGRx_EN_Msk                         /*!< COMPx enable bit                     */

+#define COMP_CFGRx_BRGEN_Pos         (1U)

+#define COMP_CFGRx_BRGEN_Msk         (0x1UL << COMP_CFGRx_BRGEN_Pos)           /*!< 0x00000002 */

+#define COMP_CFGRx_BRGEN             COMP_CFGRx_BRGEN_Msk                      /*!< COMPx Scaler bridge enable           */

+#define COMP_CFGRx_SCALEN_Pos        (2U)

+#define COMP_CFGRx_SCALEN_Msk        (0x1UL << COMP_CFGRx_SCALEN_Pos)          /*!< 0x00000004 */

+#define COMP_CFGRx_SCALEN            COMP_CFGRx_SCALEN_Msk                     /*!< COMPx Voltage scaler enable bit      */

+#define COMP_CFGRx_POLARITY_Pos      (3U)

+#define COMP_CFGRx_POLARITY_Msk      (0x1UL << COMP_CFGRx_POLARITY_Pos)        /*!< 0x00000008 */

+#define COMP_CFGRx_POLARITY          COMP_CFGRx_POLARITY_Msk                   /*!< COMPx  polarity selection bit        */

+#define COMP_CFGRx_WINMODE_Pos       (4U)

+#define COMP_CFGRx_WINMODE_Msk       (0x1UL << COMP_CFGRx_WINMODE_Pos)         /*!< 0x00000010 */

+#define COMP_CFGRx_WINMODE           COMP_CFGRx_WINMODE_Msk                    /*!< COMPx Windows mode selection bit     */

+#define COMP_CFGRx_ITEN_Pos          (6U)

+#define COMP_CFGRx_ITEN_Msk          (0x1UL << COMP_CFGRx_ITEN_Pos)            /*!< 0x00000040 */

+#define COMP_CFGRx_ITEN              COMP_CFGRx_ITEN_Msk                       /*!< COMPx  interrupt enable              */

+#define COMP_CFGRx_HYST_Pos          (8U)

+#define COMP_CFGRx_HYST_Msk          (0x3UL << COMP_CFGRx_HYST_Pos)            /*!< 0x00000300 */

+#define COMP_CFGRx_HYST              COMP_CFGRx_HYST_Msk                       /*!< COMPx  hysteresis selection bits     */

+#define COMP_CFGRx_HYST_0            (0x1UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000100 */

+#define COMP_CFGRx_HYST_1            (0x2UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000200 */

+#define COMP_CFGRx_PWRMODE_Pos       (12U)

+#define COMP_CFGRx_PWRMODE_Msk       (0x3UL << COMP_CFGRx_PWRMODE_Pos)         /*!< 0x00003000 */

+#define COMP_CFGRx_PWRMODE           COMP_CFGRx_PWRMODE_Msk                    /*!< COMPx Power Mode of the comparator   */

+#define COMP_CFGRx_PWRMODE_0         (0x1UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00001000 */

+#define COMP_CFGRx_PWRMODE_1         (0x2UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00002000 */

+#define COMP_CFGRx_INMSEL_Pos        (16U)

+#define COMP_CFGRx_INMSEL_Msk        (0xFUL << COMP_CFGRx_INMSEL_Pos)          /*!< 0x000F0000 */

+#define COMP_CFGRx_INMSEL            COMP_CFGRx_INMSEL_Msk                     /*!< COMPx  input minus selection bit  */

+#define COMP_CFGRx_INMSEL_0          (0x1UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00010000 */

+#define COMP_CFGRx_INMSEL_1          (0x2UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00020000 */

+#define COMP_CFGRx_INMSEL_2          (0x4UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00040000 */

+#define COMP_CFGRx_INMSEL_3          (0x8UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00080000 */

+#define COMP_CFGRx_INPSEL_Pos        (20U)

+#define COMP_CFGRx_INPSEL_Msk        (0x1UL << COMP_CFGRx_INPSEL_Pos)          /*!< 0x00100000 */

+#define COMP_CFGRx_INPSEL            COMP_CFGRx_INPSEL_Msk                     /*!< COMPx  input plus selection bit       */

+#define COMP_CFGRx_INP2SEL_Pos        (22U)

+#define COMP_CFGRx_INP2SEL_Msk        (0x1UL << COMP_CFGRx_INP2SEL_Pos)        /*!< 0x00400000 */

+#define COMP_CFGRx_INP2SEL            COMP_CFGRx_INP2SEL_Msk                   /*!< COMPx  input plus 2 selection bit     */

+#define COMP_CFGRx_BLANKING_Pos      (24U)

+#define COMP_CFGRx_BLANKING_Msk      (0xFUL << COMP_CFGRx_BLANKING_Pos)        /*!< 0x0F000000 */

+#define COMP_CFGRx_BLANKING          COMP_CFGRx_BLANKING_Msk                   /*!< COMPx  blanking source selection bits */

+#define COMP_CFGRx_BLANKING_0        (0x1UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x01000000 */

+#define COMP_CFGRx_BLANKING_1        (0x2UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x02000000 */

+#define COMP_CFGRx_BLANKING_2        (0x4UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x04000000 */

+#define COMP_CFGRx_LOCK_Pos          (31U)

+#define COMP_CFGRx_LOCK_Msk          (0x1UL << COMP_CFGRx_LOCK_Pos)            /*!< 0x80000000 */

+#define COMP_CFGRx_LOCK              COMP_CFGRx_LOCK_Msk                       /*!< COMPx Lock Bit                        */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for USART_CR1 register  *******************/

+#define USART_CR1_UE_Pos                (0U)

+#define USART_CR1_UE_Msk                (0x1UL << USART_CR1_UE_Pos)            /*!< 0x00000001 */

+#define USART_CR1_UE                    USART_CR1_UE_Msk                       /*!< USART Enable */

+#define USART_CR1_UESM_Pos              (1U)

+#define USART_CR1_UESM_Msk              (0x1UL << USART_CR1_UESM_Pos)          /*!< 0x00000002 */

+#define USART_CR1_UESM                  USART_CR1_UESM_Msk                     /*!< USART Enable in STOP Mode */

+#define USART_CR1_RE_Pos                (2U)

+#define USART_CR1_RE_Msk                (0x1UL << USART_CR1_RE_Pos)            /*!< 0x00000004 */

+#define USART_CR1_RE                    USART_CR1_RE_Msk                       /*!< Receiver Enable */

+#define USART_CR1_TE_Pos                (3U)

+#define USART_CR1_TE_Msk                (0x1UL << USART_CR1_TE_Pos)            /*!< 0x00000008 */

+#define USART_CR1_TE                    USART_CR1_TE_Msk                       /*!< Transmitter Enable */

+#define USART_CR1_IDLEIE_Pos            (4U)

+#define USART_CR1_IDLEIE_Msk            (0x1UL << USART_CR1_IDLEIE_Pos)        /*!< 0x00000010 */

+#define USART_CR1_IDLEIE                USART_CR1_IDLEIE_Msk                   /*!< IDLE Interrupt Enable */

+#define USART_CR1_RXNEIE_RXFNEIE_Pos    (5U)

+#define USART_CR1_RXNEIE_RXFNEIE_Msk    (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */

+#define USART_CR1_RXNEIE_RXFNEIE        USART_CR1_RXNEIE_RXFNEIE_Msk           /*!< RXNE and RX FIFO Not Empty Interrupt Enable */

+#define USART_CR1_TCIE_Pos              (6U)

+#define USART_CR1_TCIE_Msk              (0x1UL << USART_CR1_TCIE_Pos)          /*!< 0x00000040 */

+#define USART_CR1_TCIE                  USART_CR1_TCIE_Msk                     /*!< Transmission Complete Interrupt Enable */

+#define USART_CR1_TXEIE_TXFNFIE_Pos     (7U)

+#define USART_CR1_TXEIE_TXFNFIE_Msk     (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */

+#define USART_CR1_TXEIE_TXFNFIE         USART_CR1_TXEIE_TXFNFIE_Msk            /*!< TXE and TX FIFO Not Full Interrupt Enable */

+#define USART_CR1_PEIE_Pos              (8U)

+#define USART_CR1_PEIE_Msk              (0x1UL << USART_CR1_PEIE_Pos)          /*!< 0x00000100 */

+#define USART_CR1_PEIE                  USART_CR1_PEIE_Msk                     /*!< PE Interrupt Enable */

+#define USART_CR1_PS_Pos                (9U)

+#define USART_CR1_PS_Msk                (0x1UL << USART_CR1_PS_Pos)            /*!< 0x00000200 */

+#define USART_CR1_PS                    USART_CR1_PS_Msk                       /*!< Parity Selection */

+#define USART_CR1_PCE_Pos               (10U)

+#define USART_CR1_PCE_Msk               (0x1UL << USART_CR1_PCE_Pos)           /*!< 0x00000400 */

+#define USART_CR1_PCE                   USART_CR1_PCE_Msk                      /*!< Parity Control Enable */

+#define USART_CR1_WAKE_Pos              (11U)

+#define USART_CR1_WAKE_Msk              (0x1UL << USART_CR1_WAKE_Pos)          /*!< 0x00000800 */

+#define USART_CR1_WAKE                  USART_CR1_WAKE_Msk                     /*!< Receiver Wakeup method */

+#define USART_CR1_M_Pos                 (12U)

+#define USART_CR1_M_Msk                 (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */

+#define USART_CR1_M                     USART_CR1_M_Msk                        /*!< Word length */

+#define USART_CR1_M0_Pos                (12U)

+#define USART_CR1_M0_Msk                (0x1UL << USART_CR1_M0_Pos)            /*!< 0x00001000 */

+#define USART_CR1_M0                    USART_CR1_M0_Msk                       /*!< Word length - Bit 0 */

+#define USART_CR1_MME_Pos               (13U)

+#define USART_CR1_MME_Msk               (0x1UL << USART_CR1_MME_Pos)           /*!< 0x00002000 */

+#define USART_CR1_MME                   USART_CR1_MME_Msk                      /*!< Mute Mode Enable */

+#define USART_CR1_CMIE_Pos              (14U)

+#define USART_CR1_CMIE_Msk              (0x1UL << USART_CR1_CMIE_Pos)          /*!< 0x00004000 */

+#define USART_CR1_CMIE                  USART_CR1_CMIE_Msk                     /*!< Character match interrupt enable */

+#define USART_CR1_OVER8_Pos             (15U)

+#define USART_CR1_OVER8_Msk             (0x1UL << USART_CR1_OVER8_Pos)         /*!< 0x00008000 */

+#define USART_CR1_OVER8                 USART_CR1_OVER8_Msk                    /*!< Oversampling by 8-bit or 16-bit mode */

+#define USART_CR1_DEDT_Pos              (16U)

+#define USART_CR1_DEDT_Msk              (0x1FUL << USART_CR1_DEDT_Pos)         /*!< 0x001F0000 */

+#define USART_CR1_DEDT                  USART_CR1_DEDT_Msk                     /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */

+#define USART_CR1_DEDT_0                (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */

+#define USART_CR1_DEDT_1                (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */

+#define USART_CR1_DEDT_2                (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */

+#define USART_CR1_DEDT_3                (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */

+#define USART_CR1_DEDT_4                (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */

+#define USART_CR1_DEAT_Pos              (21U)

+#define USART_CR1_DEAT_Msk              (0x1FUL << USART_CR1_DEAT_Pos)         /*!< 0x03E00000 */

+#define USART_CR1_DEAT                  USART_CR1_DEAT_Msk                     /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */

+#define USART_CR1_DEAT_0                (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */

+#define USART_CR1_DEAT_1                (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */

+#define USART_CR1_DEAT_2                (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */

+#define USART_CR1_DEAT_3                (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */

+#define USART_CR1_DEAT_4                (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */

+#define USART_CR1_RTOIE_Pos             (26U)

+#define USART_CR1_RTOIE_Msk             (0x1UL << USART_CR1_RTOIE_Pos)         /*!< 0x04000000 */

+#define USART_CR1_RTOIE                 USART_CR1_RTOIE_Msk                    /*!< Receive Time Out interrupt enable */

+#define USART_CR1_EOBIE_Pos             (27U)

+#define USART_CR1_EOBIE_Msk             (0x1UL << USART_CR1_EOBIE_Pos)         /*!< 0x08000000 */

+#define USART_CR1_EOBIE                 USART_CR1_EOBIE_Msk                    /*!< End of Block interrupt enable */

+#define USART_CR1_M1_Pos                (28U)

+#define USART_CR1_M1_Msk                (0x1UL << USART_CR1_M1_Pos)            /*!< 0x10000000 */

+#define USART_CR1_M1                    USART_CR1_M1_Msk                       /*!< Word length - Bit 1 */

+#define USART_CR1_FIFOEN_Pos            (29U)

+#define USART_CR1_FIFOEN_Msk            (0x1UL << USART_CR1_FIFOEN_Pos)        /*!< 0x20000000 */

+#define USART_CR1_FIFOEN                USART_CR1_FIFOEN_Msk                   /*!< FIFO mode enable */

+#define USART_CR1_TXFEIE_Pos            (30U)

+#define USART_CR1_TXFEIE_Msk            (0x1UL << USART_CR1_TXFEIE_Pos)        /*!< 0x40000000 */

+#define USART_CR1_TXFEIE                USART_CR1_TXFEIE_Msk                   /*!< TXFIFO empty interrupt enable */

+#define USART_CR1_RXFFIE_Pos            (31U)

+#define USART_CR1_RXFFIE_Msk            (0x1UL << USART_CR1_RXFFIE_Pos)        /*!< 0x80000000 */

+#define USART_CR1_RXFFIE                USART_CR1_RXFFIE_Msk                   /*!< RXFIFO Full interrupt enable */

+

+/* Legacy define */

+#define  USART_CR1_RXNEIE  USART_CR1_RXNEIE_RXFNEIE

+#define  USART_CR1_TXEIE   USART_CR1_TXEIE_TXFNFIE

+

+/******************  Bit definition for USART_CR2 register  *******************/

+#define USART_CR2_SLVEN_Pos             (0U)

+#define USART_CR2_SLVEN_Msk             (0x1UL << USART_CR2_SLVEN_Pos)         /*!< 0x00000001 */

+#define USART_CR2_SLVEN                 USART_CR2_SLVEN_Msk                    /*!< Synchronous Slave mode Enable */

+#define USART_CR2_DIS_NSS_Pos           (3U)

+#define USART_CR2_DIS_NSS_Msk           (0x1UL << USART_CR2_DIS_NSS_Pos)       /*!< 0x00000008 */

+#define USART_CR2_DIS_NSS               USART_CR2_DIS_NSS_Msk                  /*!< Negative Slave Select (NSS) pin management */

+#define USART_CR2_ADDM7_Pos             (4U)

+#define USART_CR2_ADDM7_Msk             (0x1UL << USART_CR2_ADDM7_Pos)         /*!< 0x00000010 */

+#define USART_CR2_ADDM7                 USART_CR2_ADDM7_Msk                    /*!< 7-bit or 4-bit Address Detection */

+#define USART_CR2_LBDL_Pos              (5U)

+#define USART_CR2_LBDL_Msk              (0x1UL << USART_CR2_LBDL_Pos)          /*!< 0x00000020 */

+#define USART_CR2_LBDL                  USART_CR2_LBDL_Msk                     /*!< LIN Break Detection Length */

+#define USART_CR2_LBDIE_Pos             (6U)

+#define USART_CR2_LBDIE_Msk             (0x1UL << USART_CR2_LBDIE_Pos)         /*!< 0x00000040 */

+#define USART_CR2_LBDIE                 USART_CR2_LBDIE_Msk                    /*!< LIN Break Detection Interrupt Enable */

+#define USART_CR2_LBCL_Pos              (8U)

+#define USART_CR2_LBCL_Msk              (0x1UL << USART_CR2_LBCL_Pos)          /*!< 0x00000100 */

+#define USART_CR2_LBCL                  USART_CR2_LBCL_Msk                     /*!< Last Bit Clock pulse */

+#define USART_CR2_CPHA_Pos              (9U)

+#define USART_CR2_CPHA_Msk              (0x1UL << USART_CR2_CPHA_Pos)          /*!< 0x00000200 */

+#define USART_CR2_CPHA                  USART_CR2_CPHA_Msk                     /*!< Clock Phase */

+#define USART_CR2_CPOL_Pos              (10U)

+#define USART_CR2_CPOL_Msk              (0x1UL << USART_CR2_CPOL_Pos)          /*!< 0x00000400 */

+#define USART_CR2_CPOL                  USART_CR2_CPOL_Msk                     /*!< Clock Polarity */

+#define USART_CR2_CLKEN_Pos             (11U)

+#define USART_CR2_CLKEN_Msk             (0x1UL << USART_CR2_CLKEN_Pos)         /*!< 0x00000800 */

+#define USART_CR2_CLKEN                 USART_CR2_CLKEN_Msk                    /*!< Clock Enable */

+#define USART_CR2_STOP_Pos              (12U)

+#define USART_CR2_STOP_Msk              (0x3UL << USART_CR2_STOP_Pos)          /*!< 0x00003000 */

+#define USART_CR2_STOP                  USART_CR2_STOP_Msk                     /*!< STOP[1:0] bits (STOP bits) */

+#define USART_CR2_STOP_0                (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */

+#define USART_CR2_STOP_1                (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */

+#define USART_CR2_LINEN_Pos             (14U)

+#define USART_CR2_LINEN_Msk             (0x1UL << USART_CR2_LINEN_Pos)         /*!< 0x00004000 */

+#define USART_CR2_LINEN                 USART_CR2_LINEN_Msk                    /*!< LIN mode enable */

+#define USART_CR2_SWAP_Pos              (15U)

+#define USART_CR2_SWAP_Msk              (0x1UL << USART_CR2_SWAP_Pos)          /*!< 0x00008000 */

+#define USART_CR2_SWAP                  USART_CR2_SWAP_Msk                     /*!< SWAP TX/RX pins */

+#define USART_CR2_RXINV_Pos             (16U)

+#define USART_CR2_RXINV_Msk             (0x1UL << USART_CR2_RXINV_Pos)         /*!< 0x00010000 */

+#define USART_CR2_RXINV                 USART_CR2_RXINV_Msk                    /*!< RX pin active level inversion */

+#define USART_CR2_TXINV_Pos             (17U)

+#define USART_CR2_TXINV_Msk             (0x1UL << USART_CR2_TXINV_Pos)         /*!< 0x00020000 */

+#define USART_CR2_TXINV                 USART_CR2_TXINV_Msk                    /*!< TX pin active level inversion */

+#define USART_CR2_DATAINV_Pos           (18U)

+#define USART_CR2_DATAINV_Msk           (0x1UL << USART_CR2_DATAINV_Pos)       /*!< 0x00040000 */

+#define USART_CR2_DATAINV               USART_CR2_DATAINV_Msk                  /*!< Binary data inversion */

+#define USART_CR2_MSBFIRST_Pos          (19U)

+#define USART_CR2_MSBFIRST_Msk          (0x1UL << USART_CR2_MSBFIRST_Pos)      /*!< 0x00080000 */

+#define USART_CR2_MSBFIRST              USART_CR2_MSBFIRST_Msk                 /*!< Most Significant Bit First */

+#define USART_CR2_ABREN_Pos             (20U)

+#define USART_CR2_ABREN_Msk             (0x1UL << USART_CR2_ABREN_Pos)         /*!< 0x00100000 */

+#define USART_CR2_ABREN                 USART_CR2_ABREN_Msk                    /*!< Auto Baud-Rate Enable*/

+#define USART_CR2_ABRMODE_Pos           (21U)

+#define USART_CR2_ABRMODE_Msk           (0x3UL << USART_CR2_ABRMODE_Pos)       /*!< 0x00600000 */

+#define USART_CR2_ABRMODE               USART_CR2_ABRMODE_Msk                  /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */

+#define USART_CR2_ABRMODE_0             (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */

+#define USART_CR2_ABRMODE_1             (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */

+#define USART_CR2_RTOEN_Pos             (23U)

+#define USART_CR2_RTOEN_Msk             (0x1UL << USART_CR2_RTOEN_Pos)         /*!< 0x00800000 */

+#define USART_CR2_RTOEN                 USART_CR2_RTOEN_Msk                    /*!< Receiver Time-Out enable */

+#define USART_CR2_ADD_Pos               (24U)

+#define USART_CR2_ADD_Msk               (0xFFUL << USART_CR2_ADD_Pos)          /*!< 0xFF000000 */

+#define USART_CR2_ADD                   USART_CR2_ADD_Msk                      /*!< Address of the USART node */

+

+/******************  Bit definition for USART_CR3 register  *******************/

+#define USART_CR3_EIE_Pos               (0U)

+#define USART_CR3_EIE_Msk               (0x1UL << USART_CR3_EIE_Pos)           /*!< 0x00000001 */

+#define USART_CR3_EIE                   USART_CR3_EIE_Msk                      /*!< Error Interrupt Enable */

+#define USART_CR3_IREN_Pos              (1U)

+#define USART_CR3_IREN_Msk              (0x1UL << USART_CR3_IREN_Pos)          /*!< 0x00000002 */

+#define USART_CR3_IREN                  USART_CR3_IREN_Msk                     /*!< IrDA mode Enable */

+#define USART_CR3_IRLP_Pos              (2U)

+#define USART_CR3_IRLP_Msk              (0x1UL << USART_CR3_IRLP_Pos)          /*!< 0x00000004 */

+#define USART_CR3_IRLP                  USART_CR3_IRLP_Msk                     /*!< IrDA Low-Power */

+#define USART_CR3_HDSEL_Pos             (3U)

+#define USART_CR3_HDSEL_Msk             (0x1UL << USART_CR3_HDSEL_Pos)         /*!< 0x00000008 */

+#define USART_CR3_HDSEL                 USART_CR3_HDSEL_Msk                    /*!< Half-Duplex Selection */

+#define USART_CR3_NACK_Pos              (4U)

+#define USART_CR3_NACK_Msk              (0x1UL << USART_CR3_NACK_Pos)          /*!< 0x00000010 */

+#define USART_CR3_NACK                  USART_CR3_NACK_Msk                     /*!< SmartCard NACK enable */

+#define USART_CR3_SCEN_Pos              (5U)

+#define USART_CR3_SCEN_Msk              (0x1UL << USART_CR3_SCEN_Pos)          /*!< 0x00000020 */

+#define USART_CR3_SCEN                  USART_CR3_SCEN_Msk                     /*!< SmartCard mode enable */

+#define USART_CR3_DMAR_Pos              (6U)

+#define USART_CR3_DMAR_Msk              (0x1UL << USART_CR3_DMAR_Pos)          /*!< 0x00000040 */

+#define USART_CR3_DMAR                  USART_CR3_DMAR_Msk                     /*!< DMA Enable Receiver */

+#define USART_CR3_DMAT_Pos              (7U)

+#define USART_CR3_DMAT_Msk              (0x1UL << USART_CR3_DMAT_Pos)          /*!< 0x00000080 */

+#define USART_CR3_DMAT                  USART_CR3_DMAT_Msk                     /*!< DMA Enable Transmitter */

+#define USART_CR3_RTSE_Pos              (8U)

+#define USART_CR3_RTSE_Msk              (0x1UL << USART_CR3_RTSE_Pos)          /*!< 0x00000100 */

+#define USART_CR3_RTSE                  USART_CR3_RTSE_Msk                     /*!< RTS Enable */

+#define USART_CR3_CTSE_Pos              (9U)

+#define USART_CR3_CTSE_Msk              (0x1UL << USART_CR3_CTSE_Pos)          /*!< 0x00000200 */

+#define USART_CR3_CTSE                  USART_CR3_CTSE_Msk                     /*!< CTS Enable */

+#define USART_CR3_CTSIE_Pos             (10U)

+#define USART_CR3_CTSIE_Msk             (0x1UL << USART_CR3_CTSIE_Pos)         /*!< 0x00000400 */

+#define USART_CR3_CTSIE                 USART_CR3_CTSIE_Msk                    /*!< CTS Interrupt Enable */

+#define USART_CR3_ONEBIT_Pos            (11U)

+#define USART_CR3_ONEBIT_Msk            (0x1UL << USART_CR3_ONEBIT_Pos)        /*!< 0x00000800 */

+#define USART_CR3_ONEBIT                USART_CR3_ONEBIT_Msk                   /*!< One sample bit method enable */

+#define USART_CR3_OVRDIS_Pos            (12U)

+#define USART_CR3_OVRDIS_Msk            (0x1UL << USART_CR3_OVRDIS_Pos)        /*!< 0x00001000 */

+#define USART_CR3_OVRDIS                USART_CR3_OVRDIS_Msk                   /*!< Overrun Disable */

+#define USART_CR3_DDRE_Pos              (13U)

+#define USART_CR3_DDRE_Msk              (0x1UL << USART_CR3_DDRE_Pos)          /*!< 0x00002000 */

+#define USART_CR3_DDRE                  USART_CR3_DDRE_Msk                     /*!< DMA Disable on Reception Error */

+#define USART_CR3_DEM_Pos               (14U)

+#define USART_CR3_DEM_Msk               (0x1UL << USART_CR3_DEM_Pos)           /*!< 0x00004000 */

+#define USART_CR3_DEM                   USART_CR3_DEM_Msk                      /*!< Driver Enable Mode */

+#define USART_CR3_DEP_Pos               (15U)

+#define USART_CR3_DEP_Msk               (0x1UL << USART_CR3_DEP_Pos)           /*!< 0x00008000 */

+#define USART_CR3_DEP                   USART_CR3_DEP_Msk                      /*!< Driver Enable Polarity Selection */

+#define USART_CR3_SCARCNT_Pos           (17U)

+#define USART_CR3_SCARCNT_Msk           (0x7UL << USART_CR3_SCARCNT_Pos)       /*!< 0x000E0000 */

+#define USART_CR3_SCARCNT               USART_CR3_SCARCNT_Msk                  /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */

+#define USART_CR3_SCARCNT_0             (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */

+#define USART_CR3_SCARCNT_1             (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */

+#define USART_CR3_SCARCNT_2             (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */

+#define USART_CR3_WUS_Pos               (20U)

+#define USART_CR3_WUS_Msk               (0x3UL << USART_CR3_WUS_Pos)           /*!< 0x00300000 */

+#define USART_CR3_WUS                   USART_CR3_WUS_Msk                      /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */

+#define USART_CR3_WUS_0                 (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */

+#define USART_CR3_WUS_1                 (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */

+#define USART_CR3_WUFIE_Pos             (22U)

+#define USART_CR3_WUFIE_Msk             (0x1UL << USART_CR3_WUFIE_Pos)         /*!< 0x00400000 */

+#define USART_CR3_WUFIE                 USART_CR3_WUFIE_Msk                    /*!< Wake Up Interrupt Enable */

+#define USART_CR3_TXFTIE_Pos            (23U)

+#define USART_CR3_TXFTIE_Msk            (0x1UL << USART_CR3_TXFTIE_Pos)        /*!< 0x00800000 */

+#define USART_CR3_TXFTIE                USART_CR3_TXFTIE_Msk                   /*!< TXFIFO threshold interrupt enable */

+#define USART_CR3_TCBGTIE_Pos           (24U)

+#define USART_CR3_TCBGTIE_Msk           (0x1UL << USART_CR3_TCBGTIE_Pos)       /*!< 0x01000000 */

+#define USART_CR3_TCBGTIE               USART_CR3_TCBGTIE_Msk                  /*!< Transmission Complete before guard time, interrupt enable */

+#define USART_CR3_RXFTCFG_Pos           (25U)

+#define USART_CR3_RXFTCFG_Msk           (0x7UL << USART_CR3_RXFTCFG_Pos)       /*!< 0x0E000000 */

+#define USART_CR3_RXFTCFG               USART_CR3_RXFTCFG_Msk                  /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */

+#define USART_CR3_RXFTCFG_0             (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */

+#define USART_CR3_RXFTCFG_1             (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */

+#define USART_CR3_RXFTCFG_2             (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */

+#define USART_CR3_RXFTIE_Pos            (28U)

+#define USART_CR3_RXFTIE_Msk            (0x1UL << USART_CR3_RXFTIE_Pos)        /*!< 0x10000000 */

+#define USART_CR3_RXFTIE                USART_CR3_RXFTIE_Msk                   /*!< RXFIFO threshold interrupt enable */

+#define USART_CR3_TXFTCFG_Pos           (29U)

+#define USART_CR3_TXFTCFG_Msk           (0x7UL << USART_CR3_TXFTCFG_Pos)       /*!< 0xE0000000 */

+#define USART_CR3_TXFTCFG               USART_CR3_TXFTCFG_Msk                  /*!< TXFIFO [2:0] threshold configuration */

+#define USART_CR3_TXFTCFG_0             (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */

+#define USART_CR3_TXFTCFG_1             (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */

+#define USART_CR3_TXFTCFG_2             (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */

+

+/******************  Bit definition for USART_BRR register  *******************/

+#define USART_BRR_DIV_FRACTION_Pos      (0U)

+#define USART_BRR_DIV_FRACTION_Msk      (0xFUL << USART_BRR_DIV_FRACTION_Pos)  /*!< 0x0000000F */

+#define USART_BRR_DIV_FRACTION          USART_BRR_DIV_FRACTION_Msk             /*!< Fraction of USARTDIV */

+#define USART_BRR_DIV_MANTISSA_Pos      (4U)

+#define USART_BRR_DIV_MANTISSA_Msk      (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */

+#define USART_BRR_DIV_MANTISSA          USART_BRR_DIV_MANTISSA_Msk             /*!< Mantissa of USARTDIV */

+

+/******************  Bit definition for USART_GTPR register  ******************/

+#define USART_GTPR_PSC_Pos              (0U)

+#define USART_GTPR_PSC_Msk              (0xFFUL << USART_GTPR_PSC_Pos)         /*!< 0x000000FF */

+#define USART_GTPR_PSC                  USART_GTPR_PSC_Msk                     /*!< PSC[7:0] bits (Prescaler value) */

+#define USART_GTPR_GT_Pos               (8U)

+#define USART_GTPR_GT_Msk               (0xFFUL << USART_GTPR_GT_Pos)          /*!< 0x0000FF00 */

+#define USART_GTPR_GT                   USART_GTPR_GT_Msk                      /*!< GT[7:0] bits (Guard time value) */

+

+/*******************  Bit definition for USART_RTOR register  *****************/

+#define USART_RTOR_RTO_Pos              (0U)

+#define USART_RTOR_RTO_Msk              (0xFFFFFFUL << USART_RTOR_RTO_Pos)     /*!< 0x00FFFFFF */

+#define USART_RTOR_RTO                  USART_RTOR_RTO_Msk                     /*!< Receiver Time Out Value */

+#define USART_RTOR_BLEN_Pos             (24U)

+#define USART_RTOR_BLEN_Msk             (0xFFUL << USART_RTOR_BLEN_Pos)        /*!< 0xFF000000 */

+#define USART_RTOR_BLEN                 USART_RTOR_BLEN_Msk                    /*!< Block Length */

+

+/*******************  Bit definition for USART_RQR register  ******************/

+#define USART_RQR_ABRRQ_Pos             (0U)

+#define USART_RQR_ABRRQ_Msk             (0x1UL << USART_RQR_ABRRQ_Pos)         /*!< 0x00000001 */

+#define USART_RQR_ABRRQ                 USART_RQR_ABRRQ_Msk                    /*!< Auto-Baud Rate Request */

+#define USART_RQR_SBKRQ_Pos             (1U)

+#define USART_RQR_SBKRQ_Msk             (0x1UL << USART_RQR_SBKRQ_Pos)         /*!< 0x00000002 */

+#define USART_RQR_SBKRQ                 USART_RQR_SBKRQ_Msk                    /*!< Send Break Request */

+#define USART_RQR_MMRQ_Pos              (2U)

+#define USART_RQR_MMRQ_Msk              (0x1UL << USART_RQR_MMRQ_Pos)          /*!< 0x00000004 */

+#define USART_RQR_MMRQ                  USART_RQR_MMRQ_Msk                     /*!< Mute Mode Request */

+#define USART_RQR_RXFRQ_Pos             (3U)

+#define USART_RQR_RXFRQ_Msk             (0x1UL << USART_RQR_RXFRQ_Pos)         /*!< 0x00000008 */

+#define USART_RQR_RXFRQ                 USART_RQR_RXFRQ_Msk                    /*!< Receive Data flush Request */

+#define USART_RQR_TXFRQ_Pos             (4U)

+#define USART_RQR_TXFRQ_Msk             (0x1UL << USART_RQR_TXFRQ_Pos)         /*!< 0x00000010 */

+#define USART_RQR_TXFRQ                 USART_RQR_TXFRQ_Msk                    /*!< Transmit data flush Request */

+

+/*******************  Bit definition for USART_ISR register  ******************/

+#define USART_ISR_PE_Pos                (0U)

+#define USART_ISR_PE_Msk                (0x1UL << USART_ISR_PE_Pos)            /*!< 0x00000001 */

+#define USART_ISR_PE                    USART_ISR_PE_Msk                       /*!< Parity Error */

+#define USART_ISR_FE_Pos                (1U)

+#define USART_ISR_FE_Msk                (0x1UL << USART_ISR_FE_Pos)            /*!< 0x00000002 */

+#define USART_ISR_FE                    USART_ISR_FE_Msk                       /*!< Framing Error */

+#define USART_ISR_NE_Pos                (2U)

+#define USART_ISR_NE_Msk                (0x1UL << USART_ISR_NE_Pos)            /*!< 0x00000004 */

+#define USART_ISR_NE                    USART_ISR_NE_Msk                       /*!< Noise detected Flag */

+#define USART_ISR_ORE_Pos               (3U)

+#define USART_ISR_ORE_Msk               (0x1UL << USART_ISR_ORE_Pos)           /*!< 0x00000008 */

+#define USART_ISR_ORE                   USART_ISR_ORE_Msk                      /*!< OverRun Error */

+#define USART_ISR_IDLE_Pos              (4U)

+#define USART_ISR_IDLE_Msk              (0x1UL << USART_ISR_IDLE_Pos)          /*!< 0x00000010 */

+#define USART_ISR_IDLE                  USART_ISR_IDLE_Msk                     /*!< IDLE line detected */

+#define USART_ISR_RXNE_RXFNE_Pos        (5U)

+#define USART_ISR_RXNE_RXFNE_Msk        (0x1UL << USART_ISR_RXNE_RXFNE_Pos)    /*!< 0x00000020 */

+#define USART_ISR_RXNE_RXFNE            USART_ISR_RXNE_RXFNE_Msk               /*!< Read Data Register or RX FIFO Not Empty */

+#define USART_ISR_TC_Pos                (6U)

+#define USART_ISR_TC_Msk                (0x1UL << USART_ISR_TC_Pos)            /*!< 0x00000040 */

+#define USART_ISR_TC                    USART_ISR_TC_Msk                       /*!< Transmission Complete */

+#define USART_ISR_TXE_TXFNF_Pos         (7U)

+#define USART_ISR_TXE_TXFNF_Msk         (0x1UL << USART_ISR_TXE_TXFNF_Pos)     /*!< 0x00000080 */

+#define USART_ISR_TXE_TXFNF             USART_ISR_TXE_TXFNF_Msk                /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */

+#define USART_ISR_LBDF_Pos              (8U)

+#define USART_ISR_LBDF_Msk              (0x1UL << USART_ISR_LBDF_Pos)          /*!< 0x00000100 */

+#define USART_ISR_LBDF                  USART_ISR_LBDF_Msk                     /*!< LIN Break Detection Flag */

+#define USART_ISR_CTSIF_Pos             (9U)

+#define USART_ISR_CTSIF_Msk             (0x1UL << USART_ISR_CTSIF_Pos)         /*!< 0x00000200 */

+#define USART_ISR_CTSIF                 USART_ISR_CTSIF_Msk                    /*!< CTS interrupt flag */

+#define USART_ISR_CTS_Pos               (10U)

+#define USART_ISR_CTS_Msk               (0x1UL << USART_ISR_CTS_Pos)           /*!< 0x00000400 */

+#define USART_ISR_CTS                   USART_ISR_CTS_Msk                      /*!< CTS flag */

+#define USART_ISR_RTOF_Pos              (11U)

+#define USART_ISR_RTOF_Msk              (0x1UL << USART_ISR_RTOF_Pos)          /*!< 0x00000800 */

+#define USART_ISR_RTOF                  USART_ISR_RTOF_Msk                     /*!< Receiver Time Out */

+#define USART_ISR_EOBF_Pos              (12U)

+#define USART_ISR_EOBF_Msk              (0x1UL << USART_ISR_EOBF_Pos)          /*!< 0x00001000 */

+#define USART_ISR_EOBF                  USART_ISR_EOBF_Msk                     /*!< End Of Block Flag */

+#define USART_ISR_UDR_Pos               (13U)

+#define USART_ISR_UDR_Msk               (0x1UL << USART_ISR_UDR_Pos)           /*!< 0x00002000 */

+#define USART_ISR_UDR                   USART_ISR_UDR_Msk                      /*!< SPI slave underrun error flag */

+#define USART_ISR_ABRE_Pos              (14U)

+#define USART_ISR_ABRE_Msk              (0x1UL << USART_ISR_ABRE_Pos)          /*!< 0x00004000 */

+#define USART_ISR_ABRE                  USART_ISR_ABRE_Msk                     /*!< Auto-Baud Rate Error */

+#define USART_ISR_ABRF_Pos              (15U)

+#define USART_ISR_ABRF_Msk              (0x1UL << USART_ISR_ABRF_Pos)          /*!< 0x00008000 */

+#define USART_ISR_ABRF                  USART_ISR_ABRF_Msk                     /*!< Auto-Baud Rate Flag */

+#define USART_ISR_BUSY_Pos              (16U)

+#define USART_ISR_BUSY_Msk              (0x1UL << USART_ISR_BUSY_Pos)          /*!< 0x00010000 */

+#define USART_ISR_BUSY                  USART_ISR_BUSY_Msk                     /*!< Busy Flag */

+#define USART_ISR_CMF_Pos               (17U)

+#define USART_ISR_CMF_Msk               (0x1UL << USART_ISR_CMF_Pos)           /*!< 0x00020000 */

+#define USART_ISR_CMF                   USART_ISR_CMF_Msk                      /*!< Character Match Flag */

+#define USART_ISR_SBKF_Pos              (18U)

+#define USART_ISR_SBKF_Msk              (0x1UL << USART_ISR_SBKF_Pos)          /*!< 0x00040000 */

+#define USART_ISR_SBKF                  USART_ISR_SBKF_Msk                     /*!< Send Break Flag */

+#define USART_ISR_RWU_Pos               (19U)

+#define USART_ISR_RWU_Msk               (0x1UL << USART_ISR_RWU_Pos)           /*!< 0x00080000 */

+#define USART_ISR_RWU                   USART_ISR_RWU_Msk                      /*!< Receive Wake Up from mute mode Flag */

+#define USART_ISR_WUF_Pos               (20U)

+#define USART_ISR_WUF_Msk               (0x1UL << USART_ISR_WUF_Pos)           /*!< 0x00100000 */

+#define USART_ISR_WUF                   USART_ISR_WUF_Msk                      /*!< Wake Up from stop mode Flag */

+#define USART_ISR_TEACK_Pos             (21U)

+#define USART_ISR_TEACK_Msk             (0x1UL << USART_ISR_TEACK_Pos)         /*!< 0x00200000 */

+#define USART_ISR_TEACK                 USART_ISR_TEACK_Msk                    /*!< Transmit Enable Acknowledge Flag */

+#define USART_ISR_REACK_Pos             (22U)

+#define USART_ISR_REACK_Msk             (0x1UL << USART_ISR_REACK_Pos)         /*!< 0x00400000 */

+#define USART_ISR_REACK                 USART_ISR_REACK_Msk                    /*!< Receive Enable Acknowledge Flag */

+#define USART_ISR_TXFE_Pos              (23U)

+#define USART_ISR_TXFE_Msk              (0x1UL << USART_ISR_TXFE_Pos)          /*!< 0x00800000 */

+#define USART_ISR_TXFE                  USART_ISR_TXFE_Msk                     /*!< TXFIFO Empty */

+#define USART_ISR_RXFF_Pos              (24U)

+#define USART_ISR_RXFF_Msk              (0x1UL << USART_ISR_RXFF_Pos)          /*!< 0x01000000 */

+#define USART_ISR_RXFF                  USART_ISR_RXFF_Msk                     /*!< RXFIFO Full Flag */

+#define USART_ISR_TCBGT_Pos             (25U)

+#define USART_ISR_TCBGT_Msk             (0x1UL << USART_ISR_TCBGT_Pos)         /*!< 0x02000000 */

+#define USART_ISR_TCBGT                 USART_ISR_TCBGT_Msk                    /*!< Transmission complete before guard time Flag */

+#define USART_ISR_RXFT_Pos              (26U)

+#define USART_ISR_RXFT_Msk              (0x1UL << USART_ISR_RXFT_Pos)          /*!< 0x04000000 */

+#define USART_ISR_RXFT                  USART_ISR_RXFT_Msk                     /*!< RXFIFO threshold Flag */

+#define USART_ISR_TXFT_Pos              (27U)

+#define USART_ISR_TXFT_Msk              (0x1UL << USART_ISR_TXFT_Pos)          /*!< 0x08000000 */

+#define USART_ISR_TXFT                  USART_ISR_TXFT_Msk                     /*!< TXFIFO threshold Flag */

+

+/*******************  Bit definition for USART_ICR register  ******************/

+#define USART_ICR_PECF_Pos              (0U)

+#define USART_ICR_PECF_Msk              (0x1UL << USART_ICR_PECF_Pos)          /*!< 0x00000001 */

+#define USART_ICR_PECF                  USART_ICR_PECF_Msk                     /*!< Parity Error Clear Flag */

+#define USART_ICR_FECF_Pos              (1U)

+#define USART_ICR_FECF_Msk              (0x1UL << USART_ICR_FECF_Pos)          /*!< 0x00000002 */

+#define USART_ICR_FECF                  USART_ICR_FECF_Msk                     /*!< Framing Error Clear Flag */

+#define USART_ICR_NECF_Pos              (2U)

+#define USART_ICR_NECF_Msk              (0x1UL << USART_ICR_NECF_Pos)          /*!< 0x00000004 */

+#define USART_ICR_NECF                  USART_ICR_NECF_Msk                     /*!< Noise detected Clear Flag */

+#define USART_ICR_ORECF_Pos             (3U)

+#define USART_ICR_ORECF_Msk             (0x1UL << USART_ICR_ORECF_Pos)         /*!< 0x00000008 */

+#define USART_ICR_ORECF                 USART_ICR_ORECF_Msk                    /*!< OverRun Error Clear Flag */

+#define USART_ICR_IDLECF_Pos            (4U)

+#define USART_ICR_IDLECF_Msk            (0x1UL << USART_ICR_IDLECF_Pos)        /*!< 0x00000010 */

+#define USART_ICR_IDLECF                USART_ICR_IDLECF_Msk                   /*!< IDLE line detected Clear Flag */

+#define USART_ICR_TXFECF_Pos            (5U)

+#define USART_ICR_TXFECF_Msk            (0x1UL << USART_ICR_TXFECF_Pos)        /*!< 0x00000020 */

+#define USART_ICR_TXFECF                USART_ICR_TXFECF_Msk                   /*!< TXFIFO empty clear flag */

+#define USART_ICR_TCCF_Pos              (6U)

+#define USART_ICR_TCCF_Msk              (0x1UL << USART_ICR_TCCF_Pos)          /*!< 0x00000040 */

+#define USART_ICR_TCCF                  USART_ICR_TCCF_Msk                     /*!< Transmission Complete Clear Flag */

+#define USART_ICR_TCBGTCF_Pos           (7U)

+#define USART_ICR_TCBGTCF_Msk           (0x1UL << USART_ICR_TCBGTCF_Pos)       /*!< 0x00000080 */

+#define USART_ICR_TCBGTCF               USART_ICR_TCBGTCF_Msk                  /*!< Transmission complete before guard time Clear Flag */

+#define USART_ICR_LBDCF_Pos             (8U)

+#define USART_ICR_LBDCF_Msk             (0x1UL << USART_ICR_LBDCF_Pos)         /*!< 0x00000100 */

+#define USART_ICR_LBDCF                 USART_ICR_LBDCF_Msk                    /*!< LIN Break Detection Clear Flag */

+#define USART_ICR_CTSCF_Pos             (9U)

+#define USART_ICR_CTSCF_Msk             (0x1UL << USART_ICR_CTSCF_Pos)         /*!< 0x00000200 */

+#define USART_ICR_CTSCF                 USART_ICR_CTSCF_Msk                    /*!< CTS Interrupt Clear Flag */

+#define USART_ICR_RTOCF_Pos             (11U)

+#define USART_ICR_RTOCF_Msk             (0x1UL << USART_ICR_RTOCF_Pos)         /*!< 0x00000800 */

+#define USART_ICR_RTOCF                 USART_ICR_RTOCF_Msk                    /*!< Receiver Time Out Clear Flag */

+#define USART_ICR_EOBCF_Pos             (12U)

+#define USART_ICR_EOBCF_Msk             (0x1UL << USART_ICR_EOBCF_Pos)         /*!< 0x00001000 */

+#define USART_ICR_EOBCF                 USART_ICR_EOBCF_Msk                    /*!< End Of Block Clear Flag */

+#define USART_ICR_UDRCF_Pos             (13U)

+#define USART_ICR_UDRCF_Msk             (0x1UL << USART_ICR_UDRCF_Pos)         /*!< 0x00002000 */

+#define USART_ICR_UDRCF                 USART_ICR_UDRCF_Msk                    /*!< SPI slave underrun clear flag */

+#define USART_ICR_CMCF_Pos              (17U)

+#define USART_ICR_CMCF_Msk              (0x1UL << USART_ICR_CMCF_Pos)          /*!< 0x00020000 */

+#define USART_ICR_CMCF                  USART_ICR_CMCF_Msk                     /*!< Character Match Clear Flag */

+#define USART_ICR_WUCF_Pos              (20U)

+#define USART_ICR_WUCF_Msk              (0x1UL << USART_ICR_WUCF_Pos)          /*!< 0x00100000 */

+#define USART_ICR_WUCF                  USART_ICR_WUCF_Msk                     /*!< Wake Up from stop mode Clear Flag */

+

+/*******************  Bit definition for USART_RDR register  ******************/

+#define USART_RDR_RDR_Pos               (0U)

+#define USART_RDR_RDR_Msk               (0x1FFUL << USART_RDR_RDR_Pos)         /*!< 0x000001FF */

+#define USART_RDR_RDR                   USART_RDR_RDR_Msk                      /*!< RDR[8:0] bits (Receive Data value) */

+

+/*******************  Bit definition for USART_TDR register  ******************/

+#define USART_TDR_TDR_Pos               (0U)

+#define USART_TDR_TDR_Msk               (0x1FFUL << USART_TDR_TDR_Pos)         /*!< 0x000001FF */

+#define USART_TDR_TDR                   USART_TDR_TDR_Msk                      /*!< TDR[8:0] bits (Transmit Data value) */

+

+/*******************  Bit definition for USART_PRESC register  ******************/

+#define USART_PRESC_PRESCALER_Pos       (0U)

+#define USART_PRESC_PRESCALER_Msk       (0xFUL << USART_PRESC_PRESCALER_Pos)   /*!< 0x0000000F */

+#define USART_PRESC_PRESCALER           USART_PRESC_PRESCALER_Msk              /*!< PRESCALER[3:0] bits (Clock prescaler) */

+#define USART_PRESC_PRESCALER_0         (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */

+#define USART_PRESC_PRESCALER_1         (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */

+#define USART_PRESC_PRESCALER_2         (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */

+#define USART_PRESC_PRESCALER_3         (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */

+

+/******************************************************************************/

+/*                                                                            */

+/*           Single Wire Protocol Master Interface (SWPMI)                    */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for SWPMI_CR register   ********************/

+#define SWPMI_CR_RXDMA_Pos       (0U)

+#define SWPMI_CR_RXDMA_Msk       (0x1UL << SWPMI_CR_RXDMA_Pos)                 /*!< 0x00000001 */

+#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */

+#define SWPMI_CR_TXDMA_Pos       (1U)

+#define SWPMI_CR_TXDMA_Msk       (0x1UL << SWPMI_CR_TXDMA_Pos)                 /*!< 0x00000002 */

+#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */

+#define SWPMI_CR_RXMODE_Pos      (2U)

+#define SWPMI_CR_RXMODE_Msk      (0x1UL << SWPMI_CR_RXMODE_Pos)                /*!< 0x00000004 */

+#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */

+#define SWPMI_CR_TXMODE_Pos      (3U)

+#define SWPMI_CR_TXMODE_Msk      (0x1UL << SWPMI_CR_TXMODE_Pos)                /*!< 0x00000008 */

+#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */

+#define SWPMI_CR_LPBK_Pos        (4U)

+#define SWPMI_CR_LPBK_Msk        (0x1UL << SWPMI_CR_LPBK_Pos)                  /*!< 0x00000010 */

+#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */

+#define SWPMI_CR_SWPACT_Pos      (5U)

+#define SWPMI_CR_SWPACT_Msk      (0x1UL << SWPMI_CR_SWPACT_Pos)                /*!< 0x00000020 */

+#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */

+#define SWPMI_CR_DEACT_Pos       (10U)

+#define SWPMI_CR_DEACT_Msk       (0x1UL << SWPMI_CR_DEACT_Pos)                 /*!< 0x00000400 */

+#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */

+#define SWPMI_CR_SWPEN_Pos       (11U)

+#define SWPMI_CR_SWPEN_Msk       (0x1UL << SWPMI_CR_SWPEN_Pos)                 /*!< 0x00000800 */

+#define SWPMI_CR_SWPEN           SWPMI_CR_SWPEN_Msk                            /*!<Single wire protocol master transceiver enable       */

+

+/*******************  Bit definition for SWPMI_BRR register  ********************/

+#define SWPMI_BRR_BR_Pos         (0U)

+#define SWPMI_BRR_BR_Msk         (0xFFUL << SWPMI_BRR_BR_Pos)                  /*!< 0x000000FF */

+#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[7:0] bits (Bitrate prescaler) */

+

+/*******************  Bit definition for SWPMI_ISR register  ********************/

+#define SWPMI_ISR_RXBFF_Pos      (0U)

+#define SWPMI_ISR_RXBFF_Msk      (0x1UL << SWPMI_ISR_RXBFF_Pos)                /*!< 0x00000001 */

+#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */

+#define SWPMI_ISR_TXBEF_Pos      (1U)

+#define SWPMI_ISR_TXBEF_Msk      (0x1UL << SWPMI_ISR_TXBEF_Pos)                /*!< 0x00000002 */

+#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */

+#define SWPMI_ISR_RXBERF_Pos     (2U)

+#define SWPMI_ISR_RXBERF_Msk     (0x1UL << SWPMI_ISR_RXBERF_Pos)               /*!< 0x00000004 */

+#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */

+#define SWPMI_ISR_RXOVRF_Pos     (3U)

+#define SWPMI_ISR_RXOVRF_Msk     (0x1UL << SWPMI_ISR_RXOVRF_Pos)               /*!< 0x00000008 */

+#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */

+#define SWPMI_ISR_TXUNRF_Pos     (4U)

+#define SWPMI_ISR_TXUNRF_Msk     (0x1UL << SWPMI_ISR_TXUNRF_Pos)               /*!< 0x00000010 */

+#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */

+#define SWPMI_ISR_RXNE_Pos       (5U)

+#define SWPMI_ISR_RXNE_Msk       (0x1UL << SWPMI_ISR_RXNE_Pos)                 /*!< 0x00000020 */

+#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */

+#define SWPMI_ISR_TXE_Pos        (6U)

+#define SWPMI_ISR_TXE_Msk        (0x1UL << SWPMI_ISR_TXE_Pos)                  /*!< 0x00000040 */

+#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */

+#define SWPMI_ISR_TCF_Pos        (7U)

+#define SWPMI_ISR_TCF_Msk        (0x1UL << SWPMI_ISR_TCF_Pos)                  /*!< 0x00000080 */

+#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */

+#define SWPMI_ISR_SRF_Pos        (8U)

+#define SWPMI_ISR_SRF_Msk        (0x1UL << SWPMI_ISR_SRF_Pos)                  /*!< 0x00000100 */

+#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */

+#define SWPMI_ISR_SUSP_Pos       (9U)

+#define SWPMI_ISR_SUSP_Msk       (0x1UL << SWPMI_ISR_SUSP_Pos)                 /*!< 0x00000200 */

+#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */

+#define SWPMI_ISR_DEACTF_Pos     (10U)

+#define SWPMI_ISR_DEACTF_Msk     (0x1UL << SWPMI_ISR_DEACTF_Pos)               /*!< 0x00000400 */

+#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */

+#define SWPMI_ISR_RDYF_Pos       (11U)

+#define SWPMI_ISR_RDYF_Msk       (0x1UL << SWPMI_ISR_RDYF_Pos)                 /*!< 0x00000800 */

+#define SWPMI_ISR_RDYF           SWPMI_ISR_RDYF_Msk                            /*!<Transceiver ready flag          */

+

+/*******************  Bit definition for SWPMI_ICR register  ********************/

+#define SWPMI_ICR_CRXBFF_Pos     (0U)

+#define SWPMI_ICR_CRXBFF_Msk     (0x1UL << SWPMI_ICR_CRXBFF_Pos)               /*!< 0x00000001 */

+#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */

+#define SWPMI_ICR_CTXBEF_Pos     (1U)

+#define SWPMI_ICR_CTXBEF_Msk     (0x1UL << SWPMI_ICR_CTXBEF_Pos)               /*!< 0x00000002 */

+#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */

+#define SWPMI_ICR_CRXBERF_Pos    (2U)

+#define SWPMI_ICR_CRXBERF_Msk    (0x1UL << SWPMI_ICR_CRXBERF_Pos)              /*!< 0x00000004 */

+#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */

+#define SWPMI_ICR_CRXOVRF_Pos    (3U)

+#define SWPMI_ICR_CRXOVRF_Msk    (0x1UL << SWPMI_ICR_CRXOVRF_Pos)              /*!< 0x00000008 */

+#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */

+#define SWPMI_ICR_CTXUNRF_Pos    (4U)

+#define SWPMI_ICR_CTXUNRF_Msk    (0x1UL << SWPMI_ICR_CTXUNRF_Pos)              /*!< 0x00000010 */

+#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */

+#define SWPMI_ICR_CTCF_Pos       (7U)

+#define SWPMI_ICR_CTCF_Msk       (0x1UL << SWPMI_ICR_CTCF_Pos)                 /*!< 0x00000080 */

+#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */

+#define SWPMI_ICR_CSRF_Pos       (8U)

+#define SWPMI_ICR_CSRF_Msk       (0x1UL << SWPMI_ICR_CSRF_Pos)                 /*!< 0x00000100 */

+#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */

+#define SWPMI_ICR_CRDYF_Pos      (11U)

+#define SWPMI_ICR_CRDYF_Msk      (0x1UL << SWPMI_ICR_CRDYF_Pos)                /*!< 0x00000800 */

+#define SWPMI_ICR_CRDYF          SWPMI_ICR_CRDYF_Msk                           /*!<Clear transceiver ready flag         */

+

+/*******************  Bit definition for SWPMI_IER register  ********************/

+#define SWPMI_IER_RXBFIE_Pos     (0U)

+#define SWPMI_IER_RXBFIE_Msk     (0x1UL << SWPMI_IER_RXBFIE_Pos)               /*!< 0x00000001 */

+#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */

+#define SWPMI_IER_TXBEIE_Pos     (1U)

+#define SWPMI_IER_TXBEIE_Msk     (0x1UL << SWPMI_IER_TXBEIE_Pos)               /*!< 0x00000002 */

+#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */

+#define SWPMI_IER_RXBERIE_Pos    (2U)

+#define SWPMI_IER_RXBERIE_Msk    (0x1UL << SWPMI_IER_RXBERIE_Pos)              /*!< 0x00000004 */

+#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */

+#define SWPMI_IER_RXOVRIE_Pos    (3U)

+#define SWPMI_IER_RXOVRIE_Msk    (0x1UL << SWPMI_IER_RXOVRIE_Pos)              /*!< 0x00000008 */

+#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */

+#define SWPMI_IER_TXUNRIE_Pos    (4U)

+#define SWPMI_IER_TXUNRIE_Msk    (0x1UL << SWPMI_IER_TXUNRIE_Pos)              /*!< 0x00000010 */

+#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */

+#define SWPMI_IER_RIE_Pos        (5U)

+#define SWPMI_IER_RIE_Msk        (0x1UL << SWPMI_IER_RIE_Pos)                  /*!< 0x00000020 */

+#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */

+#define SWPMI_IER_TIE_Pos        (6U)

+#define SWPMI_IER_TIE_Msk        (0x1UL << SWPMI_IER_TIE_Pos)                  /*!< 0x00000040 */

+#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */

+#define SWPMI_IER_TCIE_Pos       (7U)

+#define SWPMI_IER_TCIE_Msk       (0x1UL << SWPMI_IER_TCIE_Pos)                 /*!< 0x00000080 */

+#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */

+#define SWPMI_IER_SRIE_Pos       (8U)

+#define SWPMI_IER_SRIE_Msk       (0x1UL << SWPMI_IER_SRIE_Pos)                 /*!< 0x00000100 */

+#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */

+#define SWPMI_IER_RDYIE_Pos      (11U)

+#define SWPMI_IER_RDYIE_Msk      (0x1UL << SWPMI_IER_RDYIE_Pos)                /*!< 0x00000800 */

+#define SWPMI_IER_RDYIE          SWPMI_IER_RDYIE_Msk                           /*!<Transceiver ready interrupt enable          */

+

+/*******************  Bit definition for SWPMI_RFL register  ********************/

+#define SWPMI_RFL_RFL_Pos        (0U)

+#define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */

+#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */

+#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */

+

+/*******************  Bit definition for SWPMI_TDR register  ********************/

+#define SWPMI_TDR_TD_Pos         (0U)

+#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)            /*!< 0xFFFFFFFF */

+#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */

+

+/*******************  Bit definition for SWPMI_RDR register  ********************/

+#define SWPMI_RDR_RD_Pos         (0U)

+#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)            /*!< 0xFFFFFFFF */

+#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Recive Data Register           */

+

+

+/*******************  Bit definition for SWPMI_OR register  ********************/

+#define SWPMI_OR_TBYP_Pos        (0U)

+#define SWPMI_OR_TBYP_Msk        (0x1UL << SWPMI_OR_TBYP_Pos)                  /*!< 0x00000001 */

+#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */

+#define SWPMI_OR_CLASS_Pos       (1U)

+#define SWPMI_OR_CLASS_Msk       (0x1UL << SWPMI_OR_CLASS_Pos)                 /*!< 0x00000002 */

+#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP CLASS selection */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            Window WATCHDOG                                 */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for WWDG_CR register  ********************/

+#define WWDG_CR_T_Pos           (0U)

+#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */

+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */

+#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */

+#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */

+#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */

+#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */

+#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */

+#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */

+#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */

+

+#define WWDG_CR_WDGA_Pos        (7U)

+#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */

+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */

+

+/*******************  Bit definition for WWDG_CFR register  *******************/

+#define WWDG_CFR_W_Pos          (0U)

+#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */

+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */

+#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */

+#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */

+#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */

+#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */

+#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */

+#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */

+#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */

+

+#define WWDG_CFR_EWI_Pos        (9U)

+#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */

+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */

+

+#define WWDG_CFR_WDGTB_Pos      (11U)

+#define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */

+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */

+#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000800 */

+#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00001000 */

+#define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00002000 */

+

+/*******************  Bit definition for WWDG_SR register  ********************/

+#define WWDG_SR_EWIF_Pos        (0U)

+#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */

+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                DBG                                         */

+/*                                                                            */

+/******************************************************************************/

+/*********************************  DEVICE ID  ********************************/

+#define STM32H7_DEV_ID           0x480UL

+

+/********************  Bit definition for DBGMCU_IDCODE register  *************/

+#define DBGMCU_IDCODE_DEV_ID_Pos          (0U)

+#define DBGMCU_IDCODE_DEV_ID_Msk          (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */

+#define DBGMCU_IDCODE_DEV_ID              DBGMCU_IDCODE_DEV_ID_Msk

+#define DBGMCU_IDCODE_REV_ID_Pos          (16U)

+#define DBGMCU_IDCODE_REV_ID_Msk          (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */

+#define DBGMCU_IDCODE_REV_ID              DBGMCU_IDCODE_REV_ID_Msk

+

+/********************  Bit definition for DBGMCU_CR register  *****************/

+#define DBGMCU_CR_DBG_SLEEPCD_Pos         (0U)

+#define DBGMCU_CR_DBG_SLEEPCD_Msk         (0x1UL << DBGMCU_CR_DBG_SLEEPCD_Pos) /*!< 0x00000001 */

+#define DBGMCU_CR_DBG_SLEEPCD             DBGMCU_CR_DBG_SLEEPCD_Msk

+#define DBGMCU_CR_DBG_STOPCD_Pos          (1U)

+#define DBGMCU_CR_DBG_STOPCD_Msk          (0x1UL << DBGMCU_CR_DBG_STOPCD_Pos)  /*!< 0x00000002 */

+#define DBGMCU_CR_DBG_STOPCD              DBGMCU_CR_DBG_STOPCD_Msk

+#define DBGMCU_CR_DBG_STANDBYCD_Pos       (2U)

+#define DBGMCU_CR_DBG_STANDBYCD_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYCD_Pos) /*!< 0x00000004 */

+#define DBGMCU_CR_DBG_STANDBYCD           DBGMCU_CR_DBG_STANDBYCD_Msk

+

+/* Legacy defines */

+#define DBGMCU_CR_DBG_SLEEPD1_Pos         DBGMCU_CR_DBG_SLEEPCD_Pos

+#define DBGMCU_CR_DBG_SLEEPD1_Msk         DBGMCU_CR_DBG_SLEEPCD_Msk

+#define DBGMCU_CR_DBG_SLEEPD1             DBGMCU_CR_DBG_SLEEPCD

+#define DBGMCU_CR_DBG_STOPD1_Pos          DBGMCU_CR_DBG_STOPCD_Pos

+#define DBGMCU_CR_DBG_STOPD1_Msk          DBGMCU_CR_DBG_STOPCD_Msk

+#define DBGMCU_CR_DBG_STOPD1              DBGMCU_CR_DBG_STOPCD

+#define DBGMCU_CR_DBG_STANDBYD1_Pos       DBGMCU_CR_DBG_STANDBYCD_Pos

+#define DBGMCU_CR_DBG_STANDBYD1_Msk       DBGMCU_CR_DBG_STANDBYCD_Msk

+#define DBGMCU_CR_DBG_STANDBYD1           DBGMCU_CR_DBG_STANDBYCD

+#define DBGMCU_CR_DBG_STOPSRD_Pos          (7U)

+#define DBGMCU_CR_DBG_STOPSRD_Msk          (0x1UL << DBGMCU_CR_DBG_STOPSRD_Pos)  /*!< 0x00000080 */

+#define DBGMCU_CR_DBG_STOPSRD              DBGMCU_CR_DBG_STOPSRD_Msk

+#define DBGMCU_CR_DBG_STANDBYSRD_Pos       (8U)

+#define DBGMCU_CR_DBG_STANDBYSRD_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYSRD_Pos) /*!< 0x00000100 */

+#define DBGMCU_CR_DBG_STANDBYSRD           DBGMCU_CR_DBG_STANDBYSRD_Msk

+

+/* Legacy defines */

+#define DBGMCU_CR_DBG_STOPD3_Pos          DBGMCU_CR_DBG_STOPSRD_Pos

+#define DBGMCU_CR_DBG_STOPD3_Msk          DBGMCU_CR_DBG_STOPSRD_Msk

+#define DBGMCU_CR_DBG_STOPD3              DBGMCU_CR_DBG_STOPSRD

+#define DBGMCU_CR_DBG_STANDBYD3_Pos       DBGMCU_CR_DBG_STANDBYSRD_Pos

+#define DBGMCU_CR_DBG_STANDBYD3_Msk       DBGMCU_CR_DBG_STANDBYSRD_Msk

+#define DBGMCU_CR_DBG_STANDBYD3           DBGMCU_CR_DBG_STANDBYSRD

+

+#define DBGMCU_CR_DBG_TRACECKEN_Pos       (20U)

+#define DBGMCU_CR_DBG_TRACECKEN_Msk       (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */

+#define DBGMCU_CR_DBG_TRACECKEN           DBGMCU_CR_DBG_TRACECKEN_Msk

+#define DBGMCU_CR_DBG_CKCDEN_Pos          (21U)

+#define DBGMCU_CR_DBG_CKCDEN_Msk          (0x1UL << DBGMCU_CR_DBG_CKCDEN_Pos)  /*!< 0x00200000 */

+#define DBGMCU_CR_DBG_CKCDEN              DBGMCU_CR_DBG_CKCDEN_Msk

+#define DBGMCU_CR_DBG_CKSRDEN_Pos          (22U)

+#define DBGMCU_CR_DBG_CKSRDEN_Msk          (0x1UL << DBGMCU_CR_DBG_CKSRDEN_Pos)  /*!< 0x00400000 */

+#define DBGMCU_CR_DBG_CKSRDEN              DBGMCU_CR_DBG_CKSRDEN_Msk

+

+/* Legacy defines */

+#define DBGMCU_CR_DBG_CKD1EN_Pos          DBGMCU_CR_DBG_CKCDEN_Pos

+#define DBGMCU_CR_DBG_CKD1EN_Msk          DBGMCU_CR_DBG_CKCDEN_Msk

+#define DBGMCU_CR_DBG_CKD1EN              DBGMCU_CR_DBG_CKCDEN

+#define DBGMCU_CR_DBG_CKD3EN_Pos          DBGMCU_CR_DBG_CKSRDEN_Pos

+#define DBGMCU_CR_DBG_CKD3EN_Msk          DBGMCU_CR_DBG_CKSRDEN_Msk

+#define DBGMCU_CR_DBG_CKD3EN              DBGMCU_CR_DBG_CKSRDEN

+

+#define DBGMCU_CR_DBG_TRGOEN_Pos          (28U)

+#define DBGMCU_CR_DBG_TRGOEN_Msk          (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)  /*!< 0x10000000 */

+#define DBGMCU_CR_DBG_TRGOEN              DBGMCU_CR_DBG_TRGOEN_Msk

+

+/********************  Bit definition for APB3FZ1 register  ************/

+#define DBGMCU_APB3FZ1_DBG_WWDG1_Pos      (6U)

+#define DBGMCU_APB3FZ1_DBG_WWDG1_Msk      (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB3FZ1_DBG_WWDG1          DBGMCU_APB3FZ1_DBG_WWDG1_Msk

+/********************  Bit definition for APB1LFZ1 register  ************/

+#define DBGMCU_APB1LFZ1_DBG_TIM2_Pos      (0U)

+#define DBGMCU_APB1LFZ1_DBG_TIM2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB1LFZ1_DBG_TIM2          DBGMCU_APB1LFZ1_DBG_TIM2_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM3_Pos      (1U)

+#define DBGMCU_APB1LFZ1_DBG_TIM3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB1LFZ1_DBG_TIM3          DBGMCU_APB1LFZ1_DBG_TIM3_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM4_Pos      (2U)

+#define DBGMCU_APB1LFZ1_DBG_TIM4_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */

+#define DBGMCU_APB1LFZ1_DBG_TIM4          DBGMCU_APB1LFZ1_DBG_TIM4_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM5_Pos      (3U)

+#define DBGMCU_APB1LFZ1_DBG_TIM5_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */

+#define DBGMCU_APB1LFZ1_DBG_TIM5          DBGMCU_APB1LFZ1_DBG_TIM5_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM6_Pos      (4U)

+#define DBGMCU_APB1LFZ1_DBG_TIM6_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */

+#define DBGMCU_APB1LFZ1_DBG_TIM6          DBGMCU_APB1LFZ1_DBG_TIM6_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM7_Pos      (5U)

+#define DBGMCU_APB1LFZ1_DBG_TIM7_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */

+#define DBGMCU_APB1LFZ1_DBG_TIM7          DBGMCU_APB1LFZ1_DBG_TIM7_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM12_Pos     (6U)

+#define DBGMCU_APB1LFZ1_DBG_TIM12_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB1LFZ1_DBG_TIM12         DBGMCU_APB1LFZ1_DBG_TIM12_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM13_Pos     (7U)

+#define DBGMCU_APB1LFZ1_DBG_TIM13_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB1LFZ1_DBG_TIM13         DBGMCU_APB1LFZ1_DBG_TIM13_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM14_Pos     (8U)

+#define DBGMCU_APB1LFZ1_DBG_TIM14_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */

+#define DBGMCU_APB1LFZ1_DBG_TIM14         DBGMCU_APB1LFZ1_DBG_TIM14_Msk

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos    (9U)

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1        DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C1_Pos      (21U)

+#define DBGMCU_APB1LFZ1_DBG_I2C1_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C1          DBGMCU_APB1LFZ1_DBG_I2C1_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C2_Pos      (22U)

+#define DBGMCU_APB1LFZ1_DBG_I2C2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C2          DBGMCU_APB1LFZ1_DBG_I2C2_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C3_Pos      (23U)

+#define DBGMCU_APB1LFZ1_DBG_I2C3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C3          DBGMCU_APB1LFZ1_DBG_I2C3_Msk

+

+/********************  Bit definition for APB2FZ1 register  ************/

+#define DBGMCU_APB2FZ1_DBG_TIM1_Pos       (0U)

+#define DBGMCU_APB2FZ1_DBG_TIM1_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB2FZ1_DBG_TIM1           DBGMCU_APB2FZ1_DBG_TIM1_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM8_Pos       (1U)

+#define DBGMCU_APB2FZ1_DBG_TIM8_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB2FZ1_DBG_TIM8           DBGMCU_APB2FZ1_DBG_TIM8_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM15_Pos      (16U)

+#define DBGMCU_APB2FZ1_DBG_TIM15_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB2FZ1_DBG_TIM15          DBGMCU_APB2FZ1_DBG_TIM15_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM16_Pos      (17U)

+#define DBGMCU_APB2FZ1_DBG_TIM16_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */

+#define DBGMCU_APB2FZ1_DBG_TIM16          DBGMCU_APB2FZ1_DBG_TIM16_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM17_Pos      (18U)

+#define DBGMCU_APB2FZ1_DBG_TIM17_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB2FZ1_DBG_TIM17          DBGMCU_APB2FZ1_DBG_TIM17_Msk

+/********************  Bit definition for APB4FZ1 register  ************/

+#define DBGMCU_APB4FZ1_DBG_I2C4_Pos       (7U)

+#define DBGMCU_APB4FZ1_DBG_I2C4_Msk       (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB4FZ1_DBG_I2C4           DBGMCU_APB4FZ1_DBG_I2C4_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos     (9U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM2         DBGMCU_APB4FZ1_DBG_LPTIM2_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos     (10U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM3         DBGMCU_APB4FZ1_DBG_LPTIM3_Msk

+#define DBGMCU_APB4FZ1_DBG_RTC_Pos        (16U)

+#define DBGMCU_APB4FZ1_DBG_RTC_Msk        (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB4FZ1_DBG_RTC            DBGMCU_APB4FZ1_DBG_RTC_Msk

+#define DBGMCU_APB4FZ1_DBG_IWDG1_Pos      (18U)

+#define DBGMCU_APB4FZ1_DBG_IWDG1_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB4FZ1_DBG_IWDG1          DBGMCU_APB4FZ1_DBG_IWDG1_Msk

+/******************************************************************************/

+/*                                                                            */

+/*                             RAM ECC monitoring                             */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for RAMECC_IER register  ******************/

+#define RAMECC_IER_GECCDEBWIE_Pos         (3U)

+#define RAMECC_IER_GECCDEBWIE_Msk         (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)  /*!< 0x00000008 */

+#define RAMECC_IER_GECCDEBWIE             RAMECC_IER_GECCDEBWIE_Msk             /*!< Global ECC double error on byte write (BW) interrupt enable */

+#define RAMECC_IER_GECCDEIE_Pos           (2U)

+#define RAMECC_IER_GECCDEIE_Msk           (0x1UL << RAMECC_IER_GECCDEIE_Pos)    /*!< 0x00000004 */

+#define RAMECC_IER_GECCDEIE               RAMECC_IER_GECCDEIE_Msk               /*!< Global ECC double error interrupt enable */

+#define RAMECC_IER_GECCSEIE_Pos           (1U)

+#define RAMECC_IER_GECCSEIE_Msk           (0x1UL << RAMECC_IER_GECCSEIE_Pos)    /*!< 0x00000002 */

+#define RAMECC_IER_GECCSEIE               RAMECC_IER_GECCSEIE_Msk               /*!< Global ECC single error interrupt enable */

+#define RAMECC_IER_GIE_Pos                (0U)

+#define RAMECC_IER_GIE_Msk                (0x1UL << RAMECC_IER_GIE_Pos)         /*!< 0x00000001 */

+#define RAMECC_IER_GIE                    RAMECC_IER_GIE_Msk                    /*!< Global interrupt enable */

+

+/*******************  Bit definition for RAMECC_CR register  ******************/

+#define RAMECC_CR_ECCELEN_Pos             (5U)

+#define RAMECC_CR_ECCELEN_Msk             (0x1UL << RAMECC_CR_ECCELEN_Pos)      /*!< 0x00000020 */

+#define RAMECC_CR_ECCELEN                 RAMECC_CR_ECCELEN_Msk                 /*!< ECC error latching enable */

+#define RAMECC_CR_ECCDEBWIE_Pos           (4U)

+#define RAMECC_CR_ECCDEBWIE_Msk           (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)    /*!< 0x00000010 */

+#define RAMECC_CR_ECCDEBWIE               RAMECC_CR_ECCDEBWIE_Msk               /*!< ECC double error on byte write (BW) interrupt enable */

+#define RAMECC_CR_ECCDEIE_Pos             (3U)

+#define RAMECC_CR_ECCDEIE_Msk             (0x1UL << RAMECC_CR_ECCDEIE_Pos)      /*!< 0x00000008 */

+#define RAMECC_CR_ECCDEIE                 RAMECC_CR_ECCDEIE_Msk                 /*!< ECC double error interrupt enable */

+#define RAMECC_CR_ECCSEIE_Pos             (2U)

+#define RAMECC_CR_ECCSEIE_Msk             (0x1UL << RAMECC_CR_ECCSEIE_Pos)      /*!< 0x00000004 */

+#define RAMECC_CR_ECCSEIE                 RAMECC_CR_ECCSEIE_Msk                 /*!< ECC single error interrupt enable */

+

+/*******************  Bit definition for RAMECC_SR register  ******************/

+#define RAMECC_SR_DEBWDF_Pos             (2U)

+#define RAMECC_SR_DEBWDF_Msk             (0x1UL << RAMECC_SR_DEBWDF_Pos)        /*!< 0x00000004 */

+#define RAMECC_SR_DEBWDF                 RAMECC_SR_DEBWDF_Msk                   /*!< ECC double error on byte write (BW) detected flag */

+#define RAMECC_SR_DEDF_Pos               (1U)

+#define RAMECC_SR_DEDF_Msk               (0x1UL << RAMECC_SR_DEDF_Pos)          /*!< 0x00000002 */

+#define RAMECC_SR_DEDF                   RAMECC_SR_DEDF_Msk                     /*!< ECC double error detected flag */

+#define RAMECC_SR_SEDCF_Pos              (0U)

+#define RAMECC_SR_SEDCF_Msk              (0x1UL << RAMECC_SR_SEDCF_Pos)         /*!< 0x00000001 */

+#define RAMECC_SR_SEDCF                  RAMECC_SR_SEDCF_Msk                    /*!< ECC single error detected and corrected flag */

+

+/******************  Bit definition for RAMECC_FAR register  ******************/

+#define RAMECC_FAR_FADD_Pos              (0U)

+#define RAMECC_FAR_FADD_Msk              (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)  /*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FADD                  RAMECC_FAR_FADD_Msk                    /*!< ECC error failing address */

+

+/******************  Bit definition for RAMECC_FDRL register  *****************/

+#define RAMECC_FAR_FDATAL_Pos            (0U)

+#define RAMECC_FAR_FDATAL_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FDATAL                RAMECC_FAR_FDATAL_Msk                  /*!< ECC error failing address */

+

+/******************  Bit definition for RAMECC_FDRH register  *****************/

+#define RAMECC_FAR_FDATAH_Pos            (0U)

+#define RAMECC_FAR_FDATAH_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FDATAH                RAMECC_FAR_FDATAH_Msk                  /* Failing data high (64-bit memory) */

+

+/*****************  Bit definition for RAMECC_FECR register  ******************/

+#define RAMECC_FECR_FEC_Pos              (0U)

+#define RAMECC_FECR_FEC_Msk              (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)  /*!< 0xFFFFFFFF */

+#define RAMECC_FECR_FEC                  RAMECC_FECR_FEC_Msk                    /*!< Failing error code */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                MDIOS                                        */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for MDIOS_CR register  *******************/

+#define MDIOS_CR_EN_Pos                (0U)

+#define MDIOS_CR_EN_Msk                (0x1UL << MDIOS_CR_EN_Pos)              /*!< 0x00000001 */

+#define MDIOS_CR_EN                    MDIOS_CR_EN_Msk                         /*!<  MDIOS slave peripheral enable */

+#define MDIOS_CR_WRIE_Pos              (1U)

+#define MDIOS_CR_WRIE_Msk              (0x1UL << MDIOS_CR_WRIE_Pos)            /*!< 0x00000002 */

+#define MDIOS_CR_WRIE                  MDIOS_CR_WRIE_Msk                       /*!<  MDIOS slave register write interrupt enable. */

+#define MDIOS_CR_RDIE_Pos              (2U)

+#define MDIOS_CR_RDIE_Msk              (0x1UL << MDIOS_CR_RDIE_Pos)            /*!< 0x00000004 */

+#define MDIOS_CR_RDIE                  MDIOS_CR_RDIE_Msk                       /*!<  MDIOS slave register read interrupt enable. */

+#define MDIOS_CR_EIE_Pos               (3U)

+#define MDIOS_CR_EIE_Msk               (0x1UL << MDIOS_CR_EIE_Pos)             /*!< 0x00000008 */

+#define MDIOS_CR_EIE                   MDIOS_CR_EIE_Msk                        /*!<  MDIOS slave register error interrupt enable. */

+#define MDIOS_CR_DPC_Pos               (7U)

+#define MDIOS_CR_DPC_Msk               (0x1UL << MDIOS_CR_DPC_Pos)             /*!< 0x00000080 */

+#define MDIOS_CR_DPC                   MDIOS_CR_DPC_Msk                        /*!<  MDIOS slave disable preamble check. */

+#define MDIOS_CR_PORT_ADDRESS_Pos      (8U)

+#define MDIOS_CR_PORT_ADDRESS_Msk      (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)   /*!< 0x00001F00 */

+#define MDIOS_CR_PORT_ADDRESS          MDIOS_CR_PORT_ADDRESS_Msk               /*!<  MDIOS slave port address mask. */

+#define MDIOS_CR_PORT_ADDRESS_0        (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000100 */

+#define MDIOS_CR_PORT_ADDRESS_1        (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000200 */

+#define MDIOS_CR_PORT_ADDRESS_2        (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000400 */

+#define MDIOS_CR_PORT_ADDRESS_3        (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000800 */

+#define MDIOS_CR_PORT_ADDRESS_4        (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001000 */

+

+/********************  Bit definition for MDIOS_SR register  *******************/

+#define MDIOS_SR_PERF_Pos              (0U)

+#define MDIOS_SR_PERF_Msk              (0x1UL << MDIOS_SR_PERF_Pos)            /*!< 0x00000001 */

+#define MDIOS_SR_PERF                  MDIOS_SR_PERF_Msk                       /*!<  MDIOS slave turnaround error flag*/

+#define MDIOS_SR_SERF_Pos              (1U)

+#define MDIOS_SR_SERF_Msk              (0x1UL << MDIOS_SR_SERF_Pos)            /*!< 0x00000002 */

+#define MDIOS_SR_SERF                  MDIOS_SR_SERF_Msk                       /*!<  MDIOS slave start error flag */

+#define MDIOS_SR_TERF_Pos              (2U)

+#define MDIOS_SR_TERF_Msk              (0x1UL << MDIOS_SR_TERF_Pos)            /*!< 0x00000004 */

+#define MDIOS_SR_TERF                  MDIOS_SR_TERF_Msk                       /*!<  MDIOS slave preamble error flag */

+

+/********************  Bit definition for MDIOS_CLRFR register  *******************/

+#define MDIOS_SR_CPERF_Pos             (0U)

+#define MDIOS_SR_CPERF_Msk             (0x1UL << MDIOS_SR_CPERF_Pos)           /*!< 0x00000001 */

+#define MDIOS_SR_CPERF                 MDIOS_SR_CPERF_Msk                      /*!<  MDIOS slave Clear the turnaround error flag */

+#define MDIOS_SR_CSERF_Pos             (1U)

+#define MDIOS_SR_CSERF_Msk             (0x1UL << MDIOS_SR_CSERF_Pos)           /*!< 0x00000002 */

+#define MDIOS_SR_CSERF                 MDIOS_SR_CSERF_Msk                      /*!<  MDIOS slave Clear the start error flag */

+#define MDIOS_SR_CTERF_Pos             (2U)

+#define MDIOS_SR_CTERF_Msk             (0x1UL << MDIOS_SR_CTERF_Pos)           /*!< 0x00000004 */

+#define MDIOS_SR_CTERF                 MDIOS_SR_CTERF_Msk                      /*!<  MDIOS slave Clear the preamble error flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                       USB_OTG                              */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/

+#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)

+#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */

+#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */

+#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)

+#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */

+#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */

+#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)

+#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */

+#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */

+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)

+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */

+#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */

+#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)

+#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */

+#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */

+#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)

+#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */

+#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */

+#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)

+#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */

+#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */

+#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)

+#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */

+#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */

+#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)

+#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */

+#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */

+#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)

+#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */

+#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */

+#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)

+#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */

+#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */

+#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)

+#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */

+#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */

+#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)

+#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */

+#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */

+#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)

+#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */

+#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */

+#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)

+#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */

+#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */

+#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)

+#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */

+#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */

+#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)

+#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */

+#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */

+#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)

+#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */

+#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */

+

+/********************  Bit definition forUSB_OTG_HCFG register  ********************/

+

+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)

+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */

+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */

+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)

+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */

+

+/********************  Bit definition forUSB_OTG_DCFG register  ********************/

+

+#define USB_OTG_DCFG_DSPD_Pos                    (0U)

+#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */

+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */

+#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */

+#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)

+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */

+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */

+

+#define USB_OTG_DCFG_DAD_Pos                     (4U)

+#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */

+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */

+#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */

+#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */

+#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */

+#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */

+#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */

+#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */

+#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */

+

+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)

+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */

+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */

+#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */

+#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */

+

+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)

+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */

+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */

+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */

+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */

+

+/********************  Bit definition forUSB_OTG_PCGCR register  ********************/

+#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)

+#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */

+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */

+#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)

+#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */

+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */

+#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)

+#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */

+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */

+

+/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/

+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)

+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */

+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */

+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)

+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */

+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */

+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)

+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */

+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */

+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)

+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */

+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */

+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)

+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */

+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */

+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)

+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */

+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */

+

+/********************  Bit definition forUSB_OTG_DCTL register  ********************/

+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)

+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */

+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */

+#define USB_OTG_DCTL_SDIS_Pos                    (1U)

+#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */

+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */

+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)

+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */

+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */

+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)

+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */

+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */

+

+#define USB_OTG_DCTL_TCTL_Pos                    (4U)

+#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */

+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */

+#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */

+#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */

+#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */

+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)

+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */

+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */

+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)

+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */

+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */

+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)

+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */

+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */

+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)

+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */

+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */

+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)

+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */

+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */

+

+/********************  Bit definition forUSB_OTG_HFIR register  ********************/

+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)

+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */

+

+/********************  Bit definition forUSB_OTG_HFNUM register  ********************/

+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)

+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */

+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)

+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */

+

+/********************  Bit definition forUSB_OTG_DSTS register  ********************/

+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)

+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */

+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */

+

+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)

+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */

+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */

+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */

+#define USB_OTG_DSTS_EERR_Pos                    (3U)

+#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */

+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */

+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)

+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */

+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */

+

+/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/

+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)

+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */

+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */

+

+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)

+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */

+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */

+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */

+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */

+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */

+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */

+#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */

+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)

+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */

+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */

+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)

+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */

+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */

+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)

+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */

+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */

+

+/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/

+

+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)

+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */

+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */

+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */

+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */

+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */

+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)

+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */

+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */

+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)

+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */

+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */

+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)

+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */

+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */

+

+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)

+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */

+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */

+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */

+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */

+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */

+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */

+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)

+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */

+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */

+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)

+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */

+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */

+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)

+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */

+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */

+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)

+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */

+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */

+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)

+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */

+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */

+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)

+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */

+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */

+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)

+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */

+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */

+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)

+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */

+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */

+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)

+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */

+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */

+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)

+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */

+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */

+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)

+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */

+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */

+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)

+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */

+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */

+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)

+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */

+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */

+

+/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/

+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)

+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */

+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */

+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)

+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */

+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */

+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)

+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */

+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */

+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)

+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */

+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */

+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)

+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */

+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */

+

+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)

+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */

+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */

+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */

+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */

+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */

+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */

+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */

+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)

+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */

+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */

+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)

+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */

+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */

+

+/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/

+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)

+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */

+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)

+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */

+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)

+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */

+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)

+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */

+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)

+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */

+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)

+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */

+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)

+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */

+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)

+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */

+

+/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/

+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)

+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */

+

+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)

+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */

+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */

+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */

+

+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)

+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */

+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */

+

+/********************  Bit definition forUSB_OTG_HAINT register  ********************/

+#define USB_OTG_HAINT_HAINT_Pos                  (0U)

+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */

+

+/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/

+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)

+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */

+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)

+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */

+#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)

+#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */

+#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask               */

+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)

+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */

+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)

+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */

+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)

+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */

+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)

+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */

+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)

+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */

+#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)

+#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */

+#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)

+#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask               */

+#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)

+#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask               */

+#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)

+#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                */

+

+/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/

+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)

+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */

+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */

+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)

+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */

+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */

+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)

+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */

+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */

+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)

+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */

+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */

+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)

+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */

+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */

+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)

+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */

+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */

+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)

+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */

+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */

+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)

+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */

+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */

+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)

+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */

+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */

+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)

+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */

+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */

+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)

+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */

+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */

+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)

+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */

+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */

+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)

+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */

+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */

+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)

+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */

+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */

+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)

+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */

+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */

+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)

+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */

+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */

+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)

+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */

+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */

+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)

+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */

+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */

+#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)

+#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */

+#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */

+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)

+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */

+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */

+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)

+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */

+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */

+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)

+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */

+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */

+#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)

+#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */

+#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */

+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)

+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */

+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */

+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)

+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */

+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */

+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)

+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */

+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */

+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)

+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */

+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */

+

+/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/

+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)

+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */

+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */

+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)

+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */

+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */

+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)

+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */

+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */

+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)

+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */

+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */

+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)

+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */

+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */

+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)

+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */

+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */

+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)

+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */

+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */

+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)

+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */

+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */

+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)

+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */

+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */

+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)

+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */

+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */

+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)

+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */

+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */

+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)

+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */

+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */

+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)

+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */

+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */

+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)

+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */

+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */

+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)

+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */

+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */

+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)

+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */

+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */

+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)

+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */

+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */

+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)

+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */

+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */

+#define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)

+#define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */

+#define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */

+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)

+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */

+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */

+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)

+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */

+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */

+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)

+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */

+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */

+#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)

+#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */

+#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */

+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)

+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */

+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */

+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)

+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */

+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */

+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)

+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */

+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */

+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)

+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */

+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */

+

+/********************  Bit definition forUSB_OTG_DAINT register  ********************/

+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)

+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */

+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)

+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */

+

+/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/

+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)

+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */

+

+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/

+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)

+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */

+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */

+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)

+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */

+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */

+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)

+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */

+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */

+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)

+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */

+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */

+

+/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/

+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)

+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */

+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)

+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */

+

+/********************  Bit definition for OTG register  ********************/

+

+#define USB_OTG_CHNUM_Pos                        (0U)

+#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)  /*!< 0x0000000F */

+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */

+#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */

+#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */

+#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */

+#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */

+#define USB_OTG_BCNT_Pos                         (4U)

+#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */

+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */

+

+#define USB_OTG_DPID_Pos                         (15U)

+#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)   /*!< 0x00018000 */

+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */

+#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */

+#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */

+

+#define USB_OTG_PKTSTS_Pos                       (17U)

+#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */

+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */

+#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */

+#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */

+#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */

+#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */

+

+#define USB_OTG_EPNUM_Pos                        (0U)

+#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)  /*!< 0x0000000F */

+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */

+#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */

+#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */

+#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */

+#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */

+

+#define USB_OTG_FRMNUM_Pos                       (21U)

+#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */

+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */

+#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */

+#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */

+#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */

+#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */

+

+/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/

+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)

+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/

+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)

+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */

+

+/********************  Bit definition for OTG register  ********************/

+#define USB_OTG_NPTXFSA_Pos                      (0U)

+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */

+#define USB_OTG_NPTXFD_Pos                       (16U)

+#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */

+#define USB_OTG_TX0FSA_Pos                       (0U)

+#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */

+#define USB_OTG_TX0FD_Pos                        (16U)

+#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */

+

+/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/

+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)

+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */

+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */

+

+/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/

+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)

+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */

+

+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)

+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */

+

+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)

+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/

+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)

+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */

+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */

+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)

+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */

+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */

+

+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)

+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */

+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */

+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */

+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)

+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */

+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */

+

+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)

+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */

+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */

+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)

+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */

+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */

+

+/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */

+

+/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/

+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)

+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */

+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */

+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)

+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */

+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */

+

+/********************  Bit definition forUSB_OTG_GCCFG register  ********************/

+#define USB_OTG_GCCFG_DCDET_Pos                  (0U)

+#define USB_OTG_GCCFG_DCDET_Msk                  (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */

+#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */

+#define USB_OTG_GCCFG_PDET_Pos                   (1U)

+#define USB_OTG_GCCFG_PDET_Msk                   (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */

+#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */

+#define USB_OTG_GCCFG_SDET_Pos                   (2U)

+#define USB_OTG_GCCFG_SDET_Msk                   (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */

+#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */

+#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)

+#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */

+#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */

+#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)

+#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */

+#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */

+#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)

+#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */

+#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */

+#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)

+#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */

+#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/

+#define USB_OTG_GCCFG_PDEN_Pos                   (19U)

+#define USB_OTG_GCCFG_PDEN_Msk                   (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */

+#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/

+#define USB_OTG_GCCFG_SDEN_Pos                   (20U)

+#define USB_OTG_GCCFG_SDEN_Msk                   (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */

+#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */

+#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)

+#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */

+#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */

+

+/********************  Bit definition forUSB_OTG_GPWRDN) register  ********************/

+#define USB_OTG_GPWRDN_ADPMEN_Pos                (0U)

+#define USB_OTG_GPWRDN_ADPMEN_Msk                (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */

+#define USB_OTG_GPWRDN_ADPMEN                    USB_OTG_GPWRDN_ADPMEN_Msk     /*!< ADP module enable */

+#define USB_OTG_GPWRDN_ADPIF_Pos                 (23U)

+#define USB_OTG_GPWRDN_ADPIF_Msk                 (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */

+#define USB_OTG_GPWRDN_ADPIF                     USB_OTG_GPWRDN_ADPIF_Msk      /*!< ADP Interrupt flag */

+

+/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/

+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)

+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */

+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)

+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */

+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */

+

+/********************  Bit definition forUSB_OTG_CID register  ********************/

+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)

+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */

+

+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/

+#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)

+#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */

+#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */

+#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)

+#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */

+#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */

+#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)

+#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */

+#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */

+#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)

+#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */

+#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */

+#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)

+#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */

+#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */

+#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)

+#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */

+#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */

+#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)

+#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */

+#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */

+#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)

+#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */

+#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */

+#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)

+#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */

+#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */

+#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)

+#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */

+#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */

+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)

+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */

+#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */

+#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)

+#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */

+#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */

+#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)

+#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */

+#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */

+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)

+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */

+#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */

+#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)

+#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */

+#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */

+

+/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/

+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)

+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */

+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)

+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */

+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)

+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */

+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)

+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */

+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)

+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */

+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)

+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */

+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)

+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */

+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)

+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */

+

+/********************  Bit definition forUSB_OTG_HPRT register  ********************/

+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)

+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */

+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */

+#define USB_OTG_HPRT_PCDET_Pos                   (1U)

+#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */

+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */

+#define USB_OTG_HPRT_PENA_Pos                    (2U)

+#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */

+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */

+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)

+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */

+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */

+#define USB_OTG_HPRT_POCA_Pos                    (4U)

+#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */

+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */

+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)

+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */

+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */

+#define USB_OTG_HPRT_PRES_Pos                    (6U)

+#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */

+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume   */

+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)

+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */

+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend  */

+#define USB_OTG_HPRT_PRST_Pos                    (8U)

+#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */

+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset    */

+

+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)

+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */

+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */

+#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */

+#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */

+#define USB_OTG_HPRT_PPWR_Pos                    (12U)

+#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */

+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */

+

+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)

+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */

+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */

+#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */

+#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */

+#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */

+#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */

+

+#define USB_OTG_HPRT_PSPD_Pos                    (17U)

+#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */

+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */

+#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */

+#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */

+

+/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/

+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)

+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)

+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)

+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */

+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)

+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */

+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)

+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */

+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)

+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */

+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)

+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)

+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)

+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)

+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */

+

+/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/

+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)

+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */

+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)

+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/

+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)

+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */

+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)

+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */

+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */

+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)

+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */

+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */

+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)

+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */

+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */

+

+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)

+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */

+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */

+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)

+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */

+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */

+

+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)

+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */

+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */

+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */

+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */

+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */

+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */

+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)

+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */

+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */

+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)

+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */

+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */

+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)

+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */

+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)

+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */

+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)

+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */

+

+/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/

+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)

+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */

+

+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)

+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */

+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */

+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */

+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */

+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */

+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */

+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)

+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */

+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */

+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)

+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */

+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */

+

+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)

+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */

+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */

+

+#define USB_OTG_HCCHAR_MC_Pos                    (20U)

+#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */

+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */

+#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */

+#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */

+

+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)

+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */

+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */

+#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */

+#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */

+#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */

+#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */

+#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */

+#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */

+#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */

+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)

+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */

+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)

+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */

+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)

+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */

+

+/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/

+

+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)

+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */

+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */

+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */

+

+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)

+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */

+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */

+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */

+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */

+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */

+

+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)

+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */

+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */

+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */

+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */

+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)

+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */

+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */

+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)

+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */

+

+/********************  Bit definition forUSB_OTG_HCINT register  ********************/

+#define USB_OTG_HCINT_XFRC_Pos                   (0U)

+#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */

+#define USB_OTG_HCINT_CHH_Pos                    (1U)

+#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */

+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)

+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */

+#define USB_OTG_HCINT_STALL_Pos                  (3U)

+#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */

+#define USB_OTG_HCINT_NAK_Pos                    (4U)

+#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */

+#define USB_OTG_HCINT_ACK_Pos                    (5U)

+#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */

+#define USB_OTG_HCINT_NYET_Pos                   (6U)

+#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */

+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */

+#define USB_OTG_HCINT_TXERR_Pos                  (7U)

+#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */

+#define USB_OTG_HCINT_BBERR_Pos                  (8U)

+#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */

+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)

+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */

+#define USB_OTG_HCINT_DTERR_Pos                  (10U)

+#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */

+

+/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/

+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)

+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */

+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)

+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */

+#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)

+#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */

+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)

+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */

+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)

+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */

+#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)

+#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */

+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)

+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */

+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)

+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */

+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */

+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)

+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */

+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)

+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */

+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)

+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */

+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */

+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)

+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */

+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */

+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)

+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */

+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */

+

+/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/

+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)

+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */

+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)

+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */

+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)

+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */

+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)

+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */

+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)

+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */

+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)

+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */

+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)

+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */

+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */

+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)

+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */

+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)

+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */

+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)

+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */

+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)

+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */

+

+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/

+

+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)

+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */

+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)

+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */

+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)

+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */

+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */

+/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/

+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)

+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */

+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)

+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */

+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)

+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */

+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)

+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */

+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */

+#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */

+#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/

+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)

+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */

+

+/********************  Bit definition forUSB_OTG_HCDMA register  ********************/

+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)

+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */

+

+/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/

+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)

+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */

+

+/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/

+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)

+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */

+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)

+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/

+

+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)

+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */

+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)

+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */

+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */

+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)

+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */

+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */

+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)

+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */

+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)

+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */

+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */

+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)

+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */

+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */

+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)

+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */

+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */

+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)

+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */

+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */

+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)

+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */

+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */

+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)

+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */

+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)

+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */

+

+/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/

+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)

+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */

+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)

+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */

+#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)

+#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */

+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)

+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */

+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)

+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */

+#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)

+#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< OUT Status Phase Received interrupt */

+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)

+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */

+#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)

+#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */

+#define USB_OTG_DOEPINT_BNA_Pos                  (9U)

+#define USB_OTG_DOEPINT_BNA_Msk                  (0x1UL << USB_OTG_DOEPINT_BNA_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPINT_BNA                      USB_OTG_DOEPINT_BNA_Msk   /*!< Buffer not available interrupt */

+#define USB_OTG_DOEPINT_BERR_Pos                 (12U)

+#define USB_OTG_DOEPINT_BERR_Msk                 (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPINT_BERR                      USB_OTG_DOEPINT_BERR_Msk   /*!< Babble error interrupt */

+#define USB_OTG_DOEPINT_NAK_Pos                  (13U)

+#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */

+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)

+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */

+#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)

+#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */

+#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */

+

+/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/

+

+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)

+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */

+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)

+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */

+

+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)

+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */

+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */

+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */

+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition for PCGCCTL register  ********************/

+#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)

+#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */

+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */

+#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)

+#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */

+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */

+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)

+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */

+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/** @addtogroup Exported_macros

+  * @{

+  */

+

+/******************************* ADC Instances ********************************/

+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \

+                                       ((INSTANCE) == ADC2))

+

+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)

+

+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)

+

+/******************************** COMP Instances ******************************/

+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \

+                                       ((INSTANCE) == COMP2))

+

+#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)

+/******************** COMP Instances with window mode capability **************/

+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)

+

+/******************************** DTS Instances ******************************/

+#define IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS)

+

+/******************************* CRC Instances ********************************/

+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

+

+/******************************* DAC Instances ********************************/

+#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1)|| \

+                                       ((INSTANCE) == DAC2))

+/******************************* DCMI Instances *******************************/

+#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)

+

+/******************************* DELAYBLOCK Instances *******************************/

+#define IS_DLYB_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DLYB_SDMMC1) || \

+                                         ((INSTANCE) == DLYB_SDMMC2) || \

+                                         ((INSTANCE) == DLYB_OCTOSPI1) || \

+                                         ((INSTANCE) == DLYB_OCTOSPI2) )

+/****************************** DFSDM Instances *******************************/

+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \

+                                         ((INSTANCE) == DFSDM1_Filter1) || \

+                                         ((INSTANCE) == DFSDM1_Filter2) || \

+                                         ((INSTANCE) == DFSDM1_Filter3) || \

+                                         ((INSTANCE) == DFSDM1_Filter4) || \

+                                         ((INSTANCE) == DFSDM1_Filter5) || \

+                                         ((INSTANCE) == DFSDM1_Filter6) || \

+                                         ((INSTANCE) == DFSDM1_Filter7) || \

+                                         ((INSTANCE) == DFSDM2_Filter0))

+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \

+                                                 ((INSTANCE) == DFSDM1_Channel1) || \

+                                                 ((INSTANCE) == DFSDM1_Channel2) || \

+                                                 ((INSTANCE) == DFSDM1_Channel3) || \

+                                                 ((INSTANCE) == DFSDM1_Channel4) || \

+                                                 ((INSTANCE) == DFSDM1_Channel5) || \

+                                                 ((INSTANCE) == DFSDM1_Channel6) || \

+                                                 ((INSTANCE) == DFSDM1_Channel7) || \

+                                                 ((INSTANCE) == DFSDM2_Channel0) || \

+                                                 ((INSTANCE) == DFSDM2_Channel1))

+/****************************** RAMECC Instances ******************************/

+#define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC_Monitor1)   || \

+                                                  ((INSTANCE) == RAMECC_Monitor2)   || \

+                                                  ((INSTANCE) == RAMECC_Monitor3))

+

+/******************************** DMA Instances *******************************/

+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \

+                                       ((INSTANCE) == DMA1_Stream1)   || \

+                                       ((INSTANCE) == DMA1_Stream2)   || \

+                                       ((INSTANCE) == DMA1_Stream3)   || \

+                                       ((INSTANCE) == DMA1_Stream4)   || \

+                                       ((INSTANCE) == DMA1_Stream5)   || \

+                                       ((INSTANCE) == DMA1_Stream6)   || \

+                                       ((INSTANCE) == DMA1_Stream7)   || \

+                                       ((INSTANCE) == DMA2_Stream0)   || \

+                                       ((INSTANCE) == DMA2_Stream1)   || \

+                                       ((INSTANCE) == DMA2_Stream2)   || \

+                                       ((INSTANCE) == DMA2_Stream3)   || \

+                                       ((INSTANCE) == DMA2_Stream4)   || \

+                                       ((INSTANCE) == DMA2_Stream5)   || \

+                                       ((INSTANCE) == DMA2_Stream6)   || \

+                                       ((INSTANCE) == DMA2_Stream7)   || \

+                                       ((INSTANCE) == BDMA1_Channel0) || \

+                                       ((INSTANCE) == BDMA1_Channel1) || \

+                                       ((INSTANCE) == BDMA1_Channel2) || \

+                                       ((INSTANCE) == BDMA1_Channel3) || \

+                                       ((INSTANCE) == BDMA1_Channel4) || \

+                                       ((INSTANCE) == BDMA1_Channel5) || \

+                                       ((INSTANCE) == BDMA1_Channel6) || \

+                                       ((INSTANCE) == BDMA1_Channel7) || \

+                                       ((INSTANCE) == BDMA2_Channel0) || \

+                                       ((INSTANCE) == BDMA2_Channel1) || \

+                                       ((INSTANCE) == BDMA2_Channel2) || \

+                                       ((INSTANCE) == BDMA2_Channel3) || \

+                                       ((INSTANCE) == BDMA2_Channel4) || \

+                                       ((INSTANCE) == BDMA2_Channel5) || \

+                                       ((INSTANCE) == BDMA2_Channel6) || \

+                                       ((INSTANCE) == BDMA2_Channel7))

+

+/****************************** BDMA CHANNEL Instances ***************************/

+#define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA1_Channel0) || \

+                                            ((INSTANCE) == BDMA1_Channel1) || \

+                                            ((INSTANCE) == BDMA1_Channel2) || \

+                                            ((INSTANCE) == BDMA1_Channel3) || \

+                                            ((INSTANCE) == BDMA1_Channel4) || \

+                                            ((INSTANCE) == BDMA1_Channel5) || \

+                                            ((INSTANCE) == BDMA1_Channel6) || \

+                                            ((INSTANCE) == BDMA1_Channel7) || \

+                                            ((INSTANCE) == BDMA2_Channel0) || \

+                                            ((INSTANCE) == BDMA2_Channel1) || \

+                                            ((INSTANCE) == BDMA2_Channel2) || \

+                                            ((INSTANCE) == BDMA2_Channel3) || \

+                                            ((INSTANCE) == BDMA2_Channel4) || \

+                                            ((INSTANCE) == BDMA2_Channel5) || \

+                                            ((INSTANCE) == BDMA2_Channel6) || \

+                                            ((INSTANCE) == BDMA2_Channel7))

+

+/****************************** DMA DMAMUX ALL Instances ***************************/

+#define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)    || \

+                                               ((INSTANCE) == DMA1_Stream1)    || \

+                                               ((INSTANCE) == DMA1_Stream2)    || \

+                                               ((INSTANCE) == DMA1_Stream3)    || \

+                                               ((INSTANCE) == DMA1_Stream4)    || \

+                                               ((INSTANCE) == DMA1_Stream5)    || \

+                                               ((INSTANCE) == DMA1_Stream6)    || \

+                                               ((INSTANCE) == DMA1_Stream7)    || \

+                                               ((INSTANCE) == DMA2_Stream0)    || \

+                                               ((INSTANCE) == DMA2_Stream1)    || \

+                                               ((INSTANCE) == DMA2_Stream2)    || \

+                                               ((INSTANCE) == DMA2_Stream3)    || \

+                                               ((INSTANCE) == DMA2_Stream4)    || \

+                                               ((INSTANCE) == DMA2_Stream5)    || \

+                                               ((INSTANCE) == DMA2_Stream6)    || \

+                                               ((INSTANCE) == DMA2_Stream7)    || \

+                                               ((INSTANCE) == BDMA2_Channel0)  || \

+                                               ((INSTANCE) == BDMA2_Channel1)  || \

+                                               ((INSTANCE) == BDMA2_Channel2)  || \

+                                               ((INSTANCE) == BDMA2_Channel3)  || \

+                                               ((INSTANCE) == BDMA2_Channel4)  || \

+                                               ((INSTANCE) == BDMA2_Channel5)  || \

+                                               ((INSTANCE) == BDMA2_Channel6)  || \

+                                               ((INSTANCE) == BDMA2_Channel7))

+

+/****************************** BDMA DMAMUX Instances ***************************/

+#define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == BDMA2_Channel0) || \

+                                                    ((INSTANCE) == BDMA2_Channel1) || \

+                                                    ((INSTANCE) == BDMA2_Channel2) || \

+                                                    ((INSTANCE) == BDMA2_Channel3) || \

+                                                    ((INSTANCE) == BDMA2_Channel4) || \

+                                                    ((INSTANCE) == BDMA2_Channel5) || \

+                                                    ((INSTANCE) == BDMA2_Channel6) || \

+                                                    ((INSTANCE) == BDMA2_Channel7))

+

+/****************************** DMA STREAM Instances ***************************/

+#define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \

+                                          ((INSTANCE) == DMA1_Stream1)   || \

+                                          ((INSTANCE) == DMA1_Stream2)   || \

+                                          ((INSTANCE) == DMA1_Stream3)   || \

+                                          ((INSTANCE) == DMA1_Stream4)   || \

+                                          ((INSTANCE) == DMA1_Stream5)   || \

+                                          ((INSTANCE) == DMA1_Stream6)   || \

+                                          ((INSTANCE) == DMA1_Stream7)   || \

+                                          ((INSTANCE) == DMA2_Stream0)   || \

+                                          ((INSTANCE) == DMA2_Stream1)   || \

+                                          ((INSTANCE) == DMA2_Stream2)   || \

+                                          ((INSTANCE) == DMA2_Stream3)   || \

+                                          ((INSTANCE) == DMA2_Stream4)   || \

+                                          ((INSTANCE) == DMA2_Stream5)   || \

+                                          ((INSTANCE) == DMA2_Stream6)   || \

+                                          ((INSTANCE) == DMA2_Stream7))

+

+/****************************** DMA DMAMUX Instances ***************************/

+#define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)   || \

+                                                  ((INSTANCE) == DMA1_Stream1)   || \

+                                                  ((INSTANCE) == DMA1_Stream2)   || \

+                                                  ((INSTANCE) == DMA1_Stream3)   || \

+                                                  ((INSTANCE) == DMA1_Stream4)   || \

+                                                  ((INSTANCE) == DMA1_Stream5)   || \

+                                                  ((INSTANCE) == DMA1_Stream6)   || \

+                                                  ((INSTANCE) == DMA1_Stream7)   || \

+                                                  ((INSTANCE) == DMA2_Stream0)   || \

+                                                  ((INSTANCE) == DMA2_Stream1)   || \

+                                                  ((INSTANCE) == DMA2_Stream2)   || \

+                                                  ((INSTANCE) == DMA2_Stream3)   || \

+                                                  ((INSTANCE) == DMA2_Stream4)   || \

+                                                  ((INSTANCE) == DMA2_Stream5)   || \

+                                                  ((INSTANCE) == DMA2_Stream6)   || \

+                                                  ((INSTANCE) == DMA2_Stream7))

+

+/******************************** DMA Request Generator Instances **************/

+#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator1) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator2) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator3) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator4) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator5) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator6) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator7) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator0) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator1) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator2) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator3) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator4) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator5) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator6) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator7))

+

+/******************************* DMA2D Instances *******************************/

+#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)

+

+/****************************** PSSI Instance *********************************/

+#define IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI)

+

+/******************************** MDMA Request Generator Instances **************/

+#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0)  || \

+                                               ((INSTANCE) == MDMA_Channel1)  || \

+                                               ((INSTANCE) == MDMA_Channel2)  || \

+                                               ((INSTANCE) == MDMA_Channel3)  || \

+                                               ((INSTANCE) == MDMA_Channel4)  || \

+                                               ((INSTANCE) == MDMA_Channel5)  || \

+                                               ((INSTANCE) == MDMA_Channel6)  || \

+                                               ((INSTANCE) == MDMA_Channel7)  || \

+                                               ((INSTANCE) == MDMA_Channel8)  || \

+                                               ((INSTANCE) == MDMA_Channel9)  || \

+                                               ((INSTANCE) == MDMA_Channel10) || \

+                                               ((INSTANCE) == MDMA_Channel11) || \

+                                               ((INSTANCE) == MDMA_Channel12) || \

+                                               ((INSTANCE) == MDMA_Channel13) || \

+                                               ((INSTANCE) == MDMA_Channel14) || \

+                                               ((INSTANCE) == MDMA_Channel15))

+

+

+/******************************* FDCAN Instances ******************************/

+#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \

+                                             ((__INSTANCE__) == FDCAN2))

+

+#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)

+

+/******************************* GFXMMU Instances *******************************/

+#define IS_GFXMMU_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GFXMMU)

+

+/******************************* GPIO Instances *******************************/

+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \

+                                        ((INSTANCE) == GPIOB) || \

+                                        ((INSTANCE) == GPIOC) || \

+                                        ((INSTANCE) == GPIOD) || \

+                                        ((INSTANCE) == GPIOE) || \

+                                        ((INSTANCE) == GPIOF) || \

+                                        ((INSTANCE) == GPIOG) || \

+                                        ((INSTANCE) == GPIOH) || \

+                                        ((INSTANCE) == GPIOI) || \

+                                        ((INSTANCE) == GPIOJ) || \

+                                        ((INSTANCE) == GPIOK))

+

+/******************************* GPIO AF Instances ****************************/

+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)

+

+/**************************** GPIO Lock Instances *****************************/

+/* On H7, all GPIO Bank support the Lock mechanism */

+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)

+

+/******************************** HSEM Instances *******************************/

+#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)

+#define HSEM_CPU1_COREID         (0x00000001U) /* Semaphore Core CM7 ID */

+#define HSEM_CR_COREID_CPU1      (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)

+#define HSEM_CR_COREID_CURRENT   (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)

+

+#define HSEM_SEMID_MIN     (0U)       /* HSEM ID Min*/

+#define HSEM_SEMID_MAX     (15U)      /* HSEM ID Max */

+

+#define HSEM_PROCESSID_MIN (0U)       /* HSEM Process ID Min */

+#define HSEM_PROCESSID_MAX (255U)     /* HSEM Process ID Max */

+

+#define HSEM_CLEAR_KEY_MIN (0U)       /* HSEM clear Key Min value */

+#define HSEM_CLEAR_KEY_MAX (0xFFFFU)  /* HSEM clear Key Max value */

+

+/******************************** I2C Instances *******************************/

+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

+                                       ((INSTANCE) == I2C2) || \

+                                       ((INSTANCE) == I2C3) || \

+                                       ((INSTANCE) == I2C4))

+/************** I2C Instances : wakeup capability from stop modes *************/

+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)

+

+/****************************** SMBUS Instances *******************************/

+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

+                                         ((INSTANCE) == I2C2) || \

+                                         ((INSTANCE) == I2C3) || \

+                                         ((INSTANCE) == I2C4))

+/******************************** I2S Instances *******************************/

+#define IS_I2S_ALL_INSTANCE(INSTANCE)   (((INSTANCE) == SPI1) || \

+                                         ((INSTANCE) == SPI2) || \

+                                         ((INSTANCE) == SPI3) || \

+                                         ((INSTANCE) == SPI6))

+

+/****************************** LTDC Instances ********************************/

+#define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)

+

+/******************************* RNG Instances ********************************/

+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)

+

+/****************************** RTC Instances *********************************/

+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)

+

+/****************************** SDMMC Instances *********************************/

+#define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \

+                                           ((_INSTANCE_) == SDMMC2))

+

+/******************************** SMBUS Instances *****************************/

+#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)

+

+/******************************** SPI Instances *******************************/

+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \

+                                       ((INSTANCE) == SPI2) || \

+                                       ((INSTANCE) == SPI3) || \

+                                       ((INSTANCE) == SPI4) || \

+                                       ((INSTANCE) == SPI5) || \

+                                       ((INSTANCE) == SPI6))

+

+#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \

+                                           ((INSTANCE) == SPI2) || \

+                                           ((INSTANCE) == SPI3))

+

+/******************************** SWPMI Instances *****************************/

+#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)

+

+/****************** LPTIM Instances : All supported instances *****************/

+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \

+                                         ((INSTANCE) == LPTIM2) || \

+                                         ((INSTANCE) == LPTIM3))

+

+/****************** LPTIM Instances : supporting encoder interface **************/

+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \

+                                                           ((INSTANCE) == LPTIM2))

+

+/****************** TIM Instances : All supported instances *******************/

+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM6)   || \

+                                         ((INSTANCE) == TIM7)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM13)  || \

+                                         ((INSTANCE) == TIM14)  || \

+                                         ((INSTANCE) == TIM15)  || \

+                                         ((INSTANCE) == TIM16)  || \

+                                         ((INSTANCE) == TIM17))

+

+/************* TIM Instances : at least 1 capture/compare channel *************/

+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM13)  || \

+                                         ((INSTANCE) == TIM14)  || \

+                                         ((INSTANCE) == TIM15)  || \

+                                         ((INSTANCE) == TIM16)  || \

+                                         ((INSTANCE) == TIM17))

+

+/************ TIM Instances : at least 2 capture/compare channels *************/

+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM15))

+

+/************ TIM Instances : at least 3 capture/compare channels *************/

+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8))

+

+/************ TIM Instances : at least 4 capture/compare channels *************/

+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8))

+

+/************ TIM Instances : at least 5 capture/compare channels *************/

+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM8))

+/************ TIM Instances : at least 6 capture/compare channels *************/

+#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM8))

+

+/******************** TIM Instances : Advanced-control timers *****************/

+#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \

+                                                ((__INSTANCE__) == TIM8))

+

+/******************** TIM Instances : Advanced-control timers *****************/

+

+/******************* TIM Instances : Timer input XOR function *****************/

+#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : DMA requests generation (UDE) *************/

+#define IS_TIM_DMA_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM6)   || \

+                                           ((INSTANCE) == TIM7)   || \

+                                           ((INSTANCE) == TIM8)   || \

+                                           ((INSTANCE) == TIM15)  || \

+                                           ((INSTANCE) == TIM16)  || \

+                                           ((INSTANCE) == TIM17))

+

+/************ TIM Instances : DMA requests generation (CCxDE) *****************/

+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15)  || \

+                                            ((INSTANCE) == TIM16)  || \

+                                            ((INSTANCE) == TIM17))

+

+/************ TIM Instances : DMA requests generation (COMDE) *****************/

+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15))

+

+/******************** TIM Instances : DMA burst feature ***********************/

+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8))

+

+/*************** TIM Instances : external trigger reamp input available *******/

+#define IS_TIM_ETR_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : remapping capability **********************/

+#define IS_TIM_REMAP_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \

+                                          ((INSTANCE) == TIM2)  || \

+                                          ((INSTANCE) == TIM3)  || \

+                                          ((INSTANCE) == TIM5)  || \

+                                          ((INSTANCE) == TIM8)  || \

+                                          ((INSTANCE) == TIM16) || \

+                                          ((INSTANCE) == TIM17))

+

+/*************** TIM Instances : external trigger reamp input available *******/

+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                              ((INSTANCE) == TIM2)   || \

+                                              ((INSTANCE) == TIM3)   || \

+                                              ((INSTANCE) == TIM5)   || \

+                                              ((INSTANCE) == TIM8))

+

+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/

+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM6)   || \

+                                            ((INSTANCE) == TIM7)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15))

+

+/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/

+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM8)   || \

+                                           ((INSTANCE) == TIM12))

+

+/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/

+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM8))

+

+/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/

+#define IS_TIM_TISEL_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)   || \

+                                          ((INSTANCE) == TIM2)   || \

+                                          ((INSTANCE) == TIM3)   || \

+                                          ((INSTANCE) == TIM4)   || \

+                                          ((INSTANCE) == TIM5)   || \

+                                          ((INSTANCE) == TIM8)   || \

+                                          ((INSTANCE) == TIM15)  || \

+                                          ((INSTANCE) == TIM16)  || \

+                                          ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting commutation event *************/

+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \

+                                                     ((INSTANCE) == TIM8)    || \

+                                                     ((INSTANCE) == TIM15)   || \

+                                                     ((INSTANCE) == TIM16)   || \

+                                                     ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting encoder interface **************/

+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1)  || \

+                                                      ((__INSTANCE__) == TIM2)      || \

+                                                      ((__INSTANCE__) == TIM3)      || \

+                                                      ((__INSTANCE__) == TIM4)      || \

+                                                      ((__INSTANCE__) == TIM5)      || \

+                                                      ((__INSTANCE__) == TIM8))

+

+/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/

+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                                       ((INSTANCE) == TIM8))

+/******************* TIM Instances : output(s) available **********************/

+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \

+    ((((INSTANCE) == TIM1) &&                  \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4) ||          \

+      ((CHANNEL) == TIM_CHANNEL_5) ||          \

+      ((CHANNEL) == TIM_CHANNEL_6)))           \

+     ||                                        \

+     (((INSTANCE) == TIM2) &&                  \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM3) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1)||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM4) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM5) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM8) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4) ||          \

+      ((CHANNEL) == TIM_CHANNEL_5) ||          \

+      ((CHANNEL) == TIM_CHANNEL_6)))           \

+  ||                                           \

+     (((INSTANCE) == TIM12) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2)))           \

+  ||                                           \

+     (((INSTANCE) == TIM13) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM14) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM15) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+     ((CHANNEL) == TIM_CHANNEL_2)))            \

+  ||                                           \

+     (((INSTANCE) == TIM16) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM17) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1))))

+

+/****************** TIM Instances : supporting the break function *************/

+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\

+      (((INSTANCE) == TIM1)    || \

+      ((INSTANCE) == TIM8)     || \

+       ((INSTANCE) == TIM15)   || \

+       ((INSTANCE) == TIM16)   || \

+       ((INSTANCE) == TIM17))

+

+/************** TIM Instances : supporting Break source selection *************/

+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \

+                                               ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting complementary output(s) ********/

+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \

+   ((((INSTANCE) == TIM1) &&                    \

+     (((CHANNEL) == TIM_CHANNEL_1) ||           \

+      ((CHANNEL) == TIM_CHANNEL_2) ||           \

+      ((CHANNEL) == TIM_CHANNEL_3)))            \

+ ||                                             \

+      (((INSTANCE) == TIM8) &&                  \

+      (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||           \

+      ((CHANNEL) == TIM_CHANNEL_3)))            \

+    ||                                          \

+    (((INSTANCE) == TIM15) &&                   \

+      ((CHANNEL) == TIM_CHANNEL_1))             \

+    ||                                          \

+    (((INSTANCE) == TIM16) &&                   \

+     ((CHANNEL) == TIM_CHANNEL_1))              \

+    ||                                          \

+    (((INSTANCE) == TIM17) &&                   \

+     ((CHANNEL) == TIM_CHANNEL_1)))

+

+/****************** TIM Instances : supporting counting mode selection ********/

+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting repetition counter *************/

+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15)   || \

+   ((INSTANCE) == TIM16)   || \

+   ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting synchronization ****************/

+#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\

+    (((__INSTANCE__) == TIM1)    || \

+     ((__INSTANCE__) == TIM2)    || \

+     ((__INSTANCE__) == TIM3)    || \

+     ((__INSTANCE__) == TIM4)    || \

+     ((__INSTANCE__) == TIM5)    || \

+     ((__INSTANCE__) == TIM6)    || \

+     ((__INSTANCE__) == TIM8)    || \

+     ((__INSTANCE__) == TIM12)   || \

+     ((__INSTANCE__) == TIM15))

+

+/****************** TIM Instances : supporting clock division *****************/

+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15)   || \

+   ((INSTANCE) == TIM16)   || \

+   ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting external clock mode 1 for ETRF input */

+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting external clock mode 2 **********/

+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\

+ (((INSTANCE) == TIM1)     || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/

+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/

+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : supporting OCxREF clear *******************/

+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3))

+

+/****************** TIM Instances : TIM_32B_COUNTER ***************************/

+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM5))

+

+/****************** TIM Instances : TIM_BKIN2 ***************************/

+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting Hall sensor interface **********/

+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)  || \

+                                                             ((__INSTANCE__) == TIM2)  || \

+                                                             ((__INSTANCE__) == TIM3)  || \

+                                                             ((__INSTANCE__) == TIM4)  || \

+                                                             ((__INSTANCE__) == TIM5)  || \

+                                                             ((__INSTANCE__) == TIM15) || \

+                                                             ((__INSTANCE__) == TIM8))

+

+/******************** USART Instances : Synchronous mode **********************/

+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                     ((INSTANCE) == USART2) || \

+                                     ((INSTANCE) == USART3) || \

+                                     ((INSTANCE) == USART6) || \

+                                     ((INSTANCE) == USART10))

+

+/******************** USART Instances : SPI slave mode ************************/

+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                              ((INSTANCE) == USART2) || \

+                                              ((INSTANCE) == USART3) || \

+                                              ((INSTANCE) == USART6) || \

+                                              ((INSTANCE) == USART10))

+

+/******************** UART Instances : Asynchronous mode **********************/

+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                    ((INSTANCE) == USART2) || \

+                                    ((INSTANCE) == USART3) || \

+                                    ((INSTANCE) == UART4)  || \

+                                    ((INSTANCE) == UART5)  || \

+                                    ((INSTANCE) == USART6) || \

+                                    ((INSTANCE) == UART7)  || \

+                                    ((INSTANCE) == UART8)  || \

+                                    ((INSTANCE) == UART9)  || \

+                                    ((INSTANCE) == USART10))

+

+/******************** UART Instances : FIFO mode.******************************/

+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                         ((INSTANCE) == USART2) || \

+                                         ((INSTANCE) == USART3) || \

+                                         ((INSTANCE) == UART4)  || \

+                                         ((INSTANCE) == UART5)  || \

+                                         ((INSTANCE) == USART6) || \

+                                         ((INSTANCE) == UART7)  || \

+                                         ((INSTANCE) == UART8)  || \

+                                         ((INSTANCE) == UART9)  || \

+                                         ((INSTANCE) == USART10)|| \

+                                         ((INSTANCE) == LPUART1))

+

+/****************** UART Instances : Auto Baud Rate detection *****************/

+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                            ((INSTANCE) == USART2) || \

+                                                            ((INSTANCE) == USART3) || \

+                                                            ((INSTANCE) == UART4)  || \

+                                                            ((INSTANCE) == UART5)  || \

+                                                            ((INSTANCE) == USART6) || \

+                                                            ((INSTANCE) == UART7)  || \

+                                                            ((INSTANCE) == UART8)  || \

+                                                            ((INSTANCE) == UART9)  || \

+                                                            ((INSTANCE) == USART10))

+

+/*********************** UART Instances : Driver Enable ***********************/

+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                  ((INSTANCE) == USART2) || \

+                                                  ((INSTANCE) == USART3) || \

+                                                  ((INSTANCE) == UART4)  || \

+                                                  ((INSTANCE) == UART5)  || \

+                                                  ((INSTANCE) == USART6) || \

+                                                  ((INSTANCE) == UART7)  || \

+                                                  ((INSTANCE) == UART8)  || \

+                                                  ((INSTANCE) == UART9)  || \

+                                                  ((INSTANCE) == USART10)|| \

+                                                  ((INSTANCE) == LPUART1))

+

+/********************* UART Instances : Half-Duplex mode **********************/

+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                               ((INSTANCE) == USART2) || \

+                                               ((INSTANCE) == USART3) || \

+                                               ((INSTANCE) == UART4)  || \

+                                               ((INSTANCE) == UART5)  || \

+                                               ((INSTANCE) == USART6) || \

+                                               ((INSTANCE) == UART7)  || \

+                                               ((INSTANCE) == UART8)  || \

+                                               ((INSTANCE) == UART9)  || \

+                                               ((INSTANCE) == USART10)|| \

+                                               ((INSTANCE) == LPUART1))

+

+/******************* UART Instances : Hardware Flow control *******************/

+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                           ((INSTANCE) == USART2) || \

+                                           ((INSTANCE) == USART3) || \

+                                           ((INSTANCE) == UART4)  || \

+                                           ((INSTANCE) == UART5)  || \

+                                           ((INSTANCE) == USART6) || \

+                                           ((INSTANCE) == UART7)  || \

+                                           ((INSTANCE) == UART8)  || \

+                                           ((INSTANCE) == UART9)  || \

+                                           ((INSTANCE) == USART10)|| \

+                                           ((INSTANCE) == LPUART1))

+

+/************************* UART Instances : LIN mode **************************/

+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                        ((INSTANCE) == USART2) || \

+                                        ((INSTANCE) == USART3) || \

+                                        ((INSTANCE) == UART4)  || \

+                                        ((INSTANCE) == UART5)  || \

+                                        ((INSTANCE) == USART6) || \

+                                        ((INSTANCE) == UART7)  || \

+                                        ((INSTANCE) == UART8)  || \

+                                        ((INSTANCE) == UART9)  || \

+                                        ((INSTANCE) == USART10))

+

+/****************** UART Instances : Wake-up from Stop mode *******************/

+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                    ((INSTANCE) == USART2) || \

+                                                    ((INSTANCE) == USART3) || \

+                                                    ((INSTANCE) == UART4)  || \

+                                                    ((INSTANCE) == UART5)  || \

+                                                    ((INSTANCE) == USART6) || \

+                                                    ((INSTANCE) == UART7)  || \

+                                                    ((INSTANCE) == UART8)  || \

+                                                    ((INSTANCE) == UART9)  || \

+                                                    ((INSTANCE) == USART10)|| \

+                                                    ((INSTANCE) == LPUART1))

+

+/************************* UART Instances : IRDA mode *************************/

+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                    ((INSTANCE) == USART2) || \

+                                    ((INSTANCE) == USART3) || \

+                                    ((INSTANCE) == UART4)  || \

+                                    ((INSTANCE) == UART5)  || \

+                                    ((INSTANCE) == USART6) || \

+                                    ((INSTANCE) == UART7)  || \

+                                    ((INSTANCE) == UART8)  || \

+                                    ((INSTANCE) == UART9)  || \

+                                    ((INSTANCE) == USART10))

+

+/********************* USART Instances : Smard card mode **********************/

+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                         ((INSTANCE) == USART2) || \

+                                         ((INSTANCE) == USART3) || \

+                                         ((INSTANCE) == USART6) ||\

+                                         ((INSTANCE) == USART10))

+

+/****************************** LPUART Instance *******************************/

+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)

+

+/****************************** IWDG Instances ********************************/

+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG1)

+/****************************** USB Instances ********************************/

+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)

+

+/****************************** WWDG Instances ********************************/

+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG1)

+/****************************** MDIOS Instances ********************************/

+#define IS_MDIOS_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == MDIOS)

+

+/****************************** CEC Instances *********************************/

+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)

+

+/****************************** SAI Instances ********************************/

+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \

+                                       ((INSTANCE) == SAI1_Block_B) || \

+                                       ((INSTANCE) == SAI2_Block_A) || \

+                                       ((INSTANCE) == SAI2_Block_B))

+

+/****************************** SPDIFRX Instances ********************************/

+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)

+

+/****************************** OPAMP Instances *******************************/

+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \

+                                         ((INSTANCE) == OPAMP2))

+

+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)

+

+/*********************** USB OTG PCD Instances ********************************/

+#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS)

+

+/*********************** USB OTG HCD Instances ********************************/

+#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS)

+

+/******************************************************************************/

+/*  For a painless codes migration between the STM32H7xx device product       */

+/*  lines, or with STM32F7xx devices the aliases defined below are put        */

+/*   in place to overcome the differences in the interrupt handlers and IRQn  */

+/*   definitions. No need to update developed interrupt code when moving      */

+/*  across product lines within the same STM32H7 Family                       */

+/******************************************************************************/

+

+/* Aliases for __IRQn */

+#define  HASH_RNG_IRQn                  RNG_IRQn

+#define  TIM1_BRK_TIM9_IRQn             TIM1_BRK_IRQn

+#define  TIM1_UP_TIM10_IRQn             TIM1_UP_IRQn

+#define  TIM1_TRG_COM_TIM11_IRQn        TIM1_TRG_COM_IRQn

+#define  PVD_IRQn                       PVD_AVD_IRQn

+

+/* Aliases for BDMA __IRQn */

+#define  BDMA_Channel0_IRQn             BDMA2_Channel0_IRQn

+#define  BDMA_Channel1_IRQn             BDMA2_Channel1_IRQn

+#define  BDMA_Channel2_IRQn             BDMA2_Channel2_IRQn

+#define  BDMA_Channel3_IRQn             BDMA2_Channel3_IRQn

+#define  BDMA_Channel4_IRQn             BDMA2_Channel4_IRQn

+#define  BDMA_Channel5_IRQn             BDMA2_Channel5_IRQn

+#define  BDMA_Channel6_IRQn             BDMA2_Channel6_IRQn

+#define  BDMA_Channel7_IRQn             BDMA2_Channel7_IRQn

+

+/* Aliases for PWR __IRQn */

+#define  PVD_AVD_IRQn                   PVD_PVM_IRQn

+

+/* Aliases for DCMI/PSSI __IRQn */

+#define  DCMI_IRQn                      DCMI_PSSI_IRQn

+

+/* Aliases for __IRQHandler */

+#define  HASH_RNG_IRQHandler           RNG_IRQHandler

+#define TIM1_BRK_TIM9_IRQHandler       TIM1_BRK_IRQHandler

+#define TIM1_UP_TIM9_IRQHandler        TIM1_UP_IRQHandler

+#define TIM1_TRG_COM_TIM11_IRQHandler  TIM1_TRG_COM_IRQHandler

+#define PVD_IRQHandler                 PVD_AVD_IRQHandler

+

+

+/* Aliases for BDMA __IRQHandler */

+#define  BDMA_Channel0_IRQHandler      BDMA2_Channel0_IRQHandler

+#define  BDMA_Channel1_IRQHandler      BDMA2_Channel1_IRQHandler

+#define  BDMA_Channel2_IRQHandler      BDMA2_Channel2_IRQHandler

+#define  BDMA_Channel3_IRQHandler      BDMA2_Channel3_IRQHandler

+#define  BDMA_Channel4_IRQHandler      BDMA2_Channel4_IRQHandler

+#define  BDMA_Channel5_IRQHandler      BDMA2_Channel5_IRQHandler

+#define  BDMA_Channel6_IRQHandler      BDMA2_Channel6_IRQHandler

+#define  BDMA_Channel7_IRQHandler      BDMA2_Channel7_IRQHandler

+

+/* Aliases for PWR __IRQHandler */

+#define  PVD_AVD_IRQHandler            PVD_PVM_IRQHandler

+

+/* Aliases for DCMI/PSSI __IRQHandler */

+#define  DCMI_IRQHandler               DCMI_PSSI_IRQHandler

+

+/* Alias for BDMA defines */

+#define BDMA_BASE              BDMA2_BASE

+#define BDMA_Channel0_BASE     BDMA2_Channel0_BASE

+#define BDMA_Channel1_BASE     BDMA2_Channel1_BASE

+#define BDMA_Channel2_BASE     BDMA2_Channel2_BASE

+#define BDMA_Channel3_BASE     BDMA2_Channel3_BASE

+#define BDMA_Channel4_BASE     BDMA2_Channel4_BASE

+#define BDMA_Channel5_BASE     BDMA2_Channel5_BASE

+#define BDMA_Channel6_BASE     BDMA2_Channel6_BASE

+#define BDMA_Channel7_BASE     BDMA2_Channel7_BASE

+

+#define BDMA                   BDMA2

+#define BDMA_Channel0          BDMA2_Channel0

+#define BDMA_Channel1          BDMA2_Channel1

+#define BDMA_Channel2          BDMA2_Channel2

+#define BDMA_Channel3          BDMA2_Channel3

+#define BDMA_Channel4          BDMA2_Channel4

+#define BDMA_Channel5          BDMA2_Channel5

+#define BDMA_Channel6          BDMA2_Channel6

+#define BDMA_Channel7          BDMA2_Channel7

+

+/* Alias for PWR defines */

+#define PWR_CPUCR_RUN_D3       PWR_CPUCR_RUN_SRD

+#define PWR_CPUCR_PDDS_D3      PWR_CPUCR_PDDS_SRD

+#define PWR_CPUCR_PDDS_D1      PWR_CPUCR_RETDS_CD

+

+#define PWR_D3CR_VOS           PWR_SRDCR_VOS

+

+#define PWR_D3CR_VOS_0         PWR_SRDCR_VOS_0

+#define PWR_D3CR_VOS_1         PWR_SRDCR_VOS_1

+#define PWR_D3CR_VOSRDY        PWR_SRDCR_VOSRDY

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif /* __cplusplus */

+

+#endif /* STM32H7A3xxQ_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7b0xx.h b/bsps/arm/stm32h7/include/stm32h7b0xx.h
new file mode 100644
index 0000000000..be0ad6399a
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7b0xx.h
@@ -0,0 +1,22894 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7b0xx.h

+  * @author  MCD Application Team

+  * @brief   CMSIS STM32H7B0xx Device Peripheral Access Layer Header File.

+  *

+  *          This file contains:

+  *           - Data structures and the address mapping for all peripherals

+  *           - Peripheral's registers declarations and bits definition

+  *           - Macros to access peripheral's registers hardware

+  *

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/** @addtogroup CMSIS_Device

+  * @{

+  */

+

+/** @addtogroup stm32h7b0xx

+  * @{

+  */

+

+#ifndef STM32H7B0xx_H

+#define STM32H7B0xx_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif /* __cplusplus */

+

+/** @addtogroup Peripheral_interrupt_number_definition

+  * @{

+  */

+

+/**

+ * @brief STM32H7XX Interrupt Number Definition, according to the selected device

+ *        in @ref Library_configuration_section

+ */

+typedef enum

+{

+/******  Cortex-M Processor Exceptions Numbers *****************************************************************/

+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */

+  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */

+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */

+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */

+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */

+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M SV Call Interrupt                                     */

+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M Debug Monitor Interrupt                               */

+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M Pend SV Interrupt                                     */

+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M System Tick Interrupt                                 */

+/******  STM32 specific Interrupt Numbers **********************************************************************/

+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)                   */

+  PVD_PVM_IRQn                = 1,      /*!< PVD/PVM through EXTI Line detection Interrupt                     */

+  RTC_TAMP_STAMP_CSS_LSE_IRQn = 2,      /*!< Tamper, TimeStamp, CSS and LSE interrupts through the EXTI line   */

+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */

+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */

+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */

+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */

+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */

+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */

+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */

+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */

+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */

+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */

+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */

+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */

+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */

+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */

+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */

+  ADC_IRQn                    = 18,     /*!< ADC1 and  ADC2 global Interrupts                                  */

+  FDCAN1_IT0_IRQn             = 19,     /*!< FDCAN1 Interrupt line 0                                           */

+  FDCAN2_IT0_IRQn             = 20,     /*!< FDCAN2 Interrupt line 0                                           */

+  FDCAN1_IT1_IRQn             = 21,     /*!< FDCAN1 Interrupt line 1                                           */

+  FDCAN2_IT1_IRQn             = 22,     /*!< FDCAN2 Interrupt line 1                                           */

+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */

+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                              */

+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                             */

+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt                            */

+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */

+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */

+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */

+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */

+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */

+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */

+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */

+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */

+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */

+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */

+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */

+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */

+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */

+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */

+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */

+  DFSDM2_IRQn                 = 42,     /*!< DFSDM2 global Interrupt                                           */

+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */

+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */

+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */

+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */

+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */

+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */

+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */

+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */

+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */

+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */

+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */

+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */

+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */

+  DMA2_Stream0_IRQn           = 56,     /*!<   DMA2 Stream 0 global Interrupt                                  */

+  DMA2_Stream1_IRQn           = 57,     /*!<   DMA2 Stream 1 global Interrupt                                  */

+  DMA2_Stream2_IRQn           = 58,     /*!<   DMA2 Stream 2 global Interrupt                                  */

+  DMA2_Stream3_IRQn           = 59,     /*!<   DMA2 Stream 3 global Interrupt                                  */

+  DMA2_Stream4_IRQn           = 60,     /*!<   DMA2 Stream 4 global Interrupt                                  */

+  FDCAN_CAL_IRQn              = 63,     /*!< FDCAN Calibration unit Interrupt                                  */

+  DFSDM1_FLT4_IRQn            = 64,     /*!< DFSDM Filter4 Interrupt                                           */

+  DFSDM1_FLT5_IRQn            = 65,     /*!< DFSDM Filter5 Interrupt                                           */

+  DFSDM1_FLT6_IRQn            = 66,     /*!< DFSDM Filter6 Interrupt                                           */

+  DFSDM1_FLT7_IRQn            = 67,     /*!< DFSDM Filter7 Interrupt                                           */

+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */

+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */

+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */

+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */

+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */

+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */

+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */

+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */

+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */

+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */

+  DCMI_PSSI_IRQn              = 78,     /*!< DCMI and PSSI global interrupt                                    */

+  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */

+  HASH_RNG_IRQn               = 80,     /*!< HASH and RNG global interrupt                                     */

+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */

+  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */

+  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */

+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */

+  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */

+  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */

+  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */

+  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */

+  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */

+  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */

+  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */

+  OCTOSPI1_IRQn               = 92,     /*!< OCTOSPI1 global interrupt                                         */

+  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */

+  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */

+  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */

+  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */

+  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */

+  DMAMUX1_OVR_IRQn            = 102,    /*!<DMAMUX1 Overrun interrupt                                          */

+  DFSDM1_FLT0_IRQn            = 110,    /*!<DFSDM Filter1 Interrupt                                            */

+  DFSDM1_FLT1_IRQn            = 111,    /*!<DFSDM Filter2 Interrupt                                            */

+  DFSDM1_FLT2_IRQn            = 112,    /*!<DFSDM Filter3 Interrupt                                            */

+  DFSDM1_FLT3_IRQn            = 113,    /*!<DFSDM Filter4 Interrupt                                            */

+  SWPMI1_IRQn                 = 115,    /*!< Serial Wire Interface 1 global interrupt                          */

+  TIM15_IRQn                  = 116,    /*!< TIM15 global Interrupt                                            */

+  TIM16_IRQn                  = 117,    /*!< TIM16 global Interrupt                                            */

+  TIM17_IRQn                  = 118,    /*!< TIM17 global Interrupt                                            */

+  MDIOS_WKUP_IRQn             = 119,    /*!< MDIOS Wakeup  Interrupt                                           */

+  MDIOS_IRQn                  = 120,    /*!< MDIOS global Interrupt                                            */

+  JPEG_IRQn                   = 121,    /*!< JPEG global Interrupt                                             */

+  MDMA_IRQn                   = 122,    /*!< MDMA global Interrupt                                             */

+  SDMMC2_IRQn                 = 124,    /*!< SDMMC2 global Interrupt                                           */

+  HSEM1_IRQn                  = 125,    /*!< HSEM1 global Interrupt                                            */

+  DAC2_IRQn                   = 127,    /*!< DAC2 global Interrupt                                             */

+  DMAMUX2_OVR_IRQn            = 128,    /*!<DMAMUX2 Overrun interrupt                                          */

+  BDMA2_Channel0_IRQn         = 129,    /*!< BDMA2 Channel 0 global Interrupt                                  */

+  BDMA2_Channel1_IRQn         = 130,    /*!< BDMA2 Channel 1 global Interrupt                                  */

+  BDMA2_Channel2_IRQn         = 131,    /*!< BDMA2 Channel 2 global Interrupt                                  */

+  BDMA2_Channel3_IRQn         = 132,    /*!< BDMA2 Channel 3 global Interrupt                                  */

+  BDMA2_Channel4_IRQn         = 133,    /*!< BDMA2 Channel 4 global Interrupt                                  */

+  BDMA2_Channel5_IRQn         = 134,    /*!< BDMA2 Channel 5 global Interrupt                                  */

+  BDMA2_Channel6_IRQn         = 135,    /*!< BDMA2 Channel 6 global Interrupt                                  */

+  BDMA2_Channel7_IRQn         = 136,    /*!< BDMA2 Channel 7 global Interrupt                                  */

+  COMP_IRQn                   = 137 ,   /*!< COMP global Interrupt                                             */

+  LPTIM2_IRQn                 = 138,    /*!< LP TIM2 global interrupt                                          */

+  LPTIM3_IRQn                 = 139,    /*!< LP TIM3 global interrupt                                          */

+  UART9_IRQn                  = 140,    /*!< UART9 global interrupt                                            */

+  USART10_IRQn                = 141,    /*!< USART10 global interrupt                                          */

+  LPUART1_IRQn                = 142,    /*!< LP UART1 interrupt                                                */

+  WWDG_RST_IRQn               = 143,    /*!<Window Watchdog Event interrupt                                    */

+  CRS_IRQn                    = 144,    /*!< Clock Recovery Global Interrupt                                   */

+  ECC_IRQn                    = 145,    /*!< ECC diagnostic Global Interrupt                                   */

+  DTS_IRQn                    = 147,    /*!< Digital Temperature Sensor Global Interrupt                       */

+  WAKEUP_PIN_IRQn             = 149,    /*!< Interrupt for all 6 wake-up pins                                  */

+  OCTOSPI2_IRQn               = 150,    /*!< OctoSPI2 global interrupt                                         */

+  OTFDEC1_IRQn                = 151,    /*!< OTFDEC1 global interrupt                                          */

+  OTFDEC2_IRQn                = 152,    /*!< OTFDEC2 global interrupt                                          */

+  GFXMMU_IRQn                 = 153,    /*!< GFXMMU global interrupt                                           */

+  BDMA1_IRQn                  = 154,    /*!< BDMA1 for DFSM global interrupt                                   */

+} IRQn_Type;

+

+/**

+  * @}

+  */

+

+/** @addtogroup Configuration_section_for_CMSIS

+  * @{

+  */

+

+

+

+

+/**

+  * @brief Configuration of the Cortex-M7 Processor and Core Peripherals

+   */

+#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */

+#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */

+#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */

+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */

+#define __FPU_PRESENT             1       /*!< FPU present                                   */

+#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */

+#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */

+#include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */

+

+/**

+  * @}

+  */

+

+

+

+

+#include "system_stm32h7xx.h"

+#include <stdint.h>

+

+/** @addtogroup Peripheral_registers_structures

+  * @{

+  */

+

+/**

+  * @brief Analog to Digital Converter

+  */

+

+typedef struct

+{

+  __IO uint32_t ISR;              /*!< ADC Interrupt and Status Register,                          Address offset: 0x00 */

+  __IO uint32_t IER;              /*!< ADC Interrupt Enable Register,                              Address offset: 0x04 */

+  __IO uint32_t CR;               /*!< ADC control register,                                       Address offset: 0x08 */

+  __IO uint32_t CFGR;             /*!< ADC Configuration register,                                 Address offset: 0x0C */

+  __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                               Address offset: 0x10 */

+  __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                                 Address offset: 0x14 */

+  __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                                 Address offset: 0x18 */

+  __IO uint32_t PCSEL;            /*!< ADC pre-channel selection,                                  Address offset: 0x1C */

+  __IO uint32_t LTR1;             /*!< ADC watchdog Lower threshold register 1,                    Address offset: 0x20 */

+  __IO uint32_t HTR1;             /*!< ADC watchdog higher threshold register 1,                   Address offset: 0x24 */

+  uint32_t      RESERVED1;        /*!< Reserved, 0x028                                                                  */

+  uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                                  */

+  __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                            Address offset: 0x30 */

+  __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                            Address offset: 0x34 */

+  __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                            Address offset: 0x38 */

+  __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                            Address offset: 0x3C */

+  __IO uint32_t DR;               /*!< ADC regular data register,                                  Address offset: 0x40 */

+  uint32_t      RESERVED3;        /*!< Reserved, 0x044                                                                  */

+  uint32_t      RESERVED4;        /*!< Reserved, 0x048                                                                  */

+  __IO uint32_t JSQR;             /*!< ADC injected sequence register,                             Address offset: 0x4C */

+  uint32_t      RESERVED5[4];     /*!< Reserved, 0x050 - 0x05C                                                          */

+  __IO uint32_t OFR1;             /*!< ADC offset register 1,                                      Address offset: 0x60 */

+  __IO uint32_t OFR2;             /*!< ADC offset register 2,                                      Address offset: 0x64 */

+  __IO uint32_t OFR3;             /*!< ADC offset register 3,                                      Address offset: 0x68 */

+  __IO uint32_t OFR4;             /*!< ADC offset register 4,                                      Address offset: 0x6C */

+  uint32_t      RESERVED6[4];     /*!< Reserved, 0x070 - 0x07C                                                          */

+  __IO uint32_t JDR1;             /*!< ADC injected data register 1,                               Address offset: 0x80 */

+  __IO uint32_t JDR2;             /*!< ADC injected data register 2,                               Address offset: 0x84 */

+  __IO uint32_t JDR3;             /*!< ADC injected data register 3,                               Address offset: 0x88 */

+  __IO uint32_t JDR4;             /*!< ADC injected data register 4,                               Address offset: 0x8C */

+  uint32_t      RESERVED7[4];     /*!< Reserved, 0x090 - 0x09C                                                          */

+  __IO uint32_t AWD2CR;           /*!< ADC  Analog Watchdog 2 Configuration Register,              Address offset: 0xA0 */

+  __IO uint32_t AWD3CR;           /*!< ADC  Analog Watchdog 3 Configuration Register,              Address offset: 0xA4 */

+  uint32_t      RESERVED8;        /*!< Reserved, 0x0A8                                                                  */

+  uint32_t      RESERVED9;        /*!< Reserved, 0x0AC                                                                  */

+  __IO uint32_t LTR2;             /*!< ADC watchdog Lower threshold register 2,                    Address offset: 0xB0 */

+  __IO uint32_t HTR2;             /*!< ADC watchdog Higher threshold register 2,                   Address offset: 0xB4 */

+  __IO uint32_t LTR3;             /*!< ADC watchdog Lower threshold register 3,                    Address offset: 0xB8 */

+  __IO uint32_t HTR3;             /*!< ADC watchdog Higher threshold register 3,                   Address offset: 0xBC */

+  __IO uint32_t DIFSEL;           /*!< ADC  Differential Mode Selection Register,                  Address offset: 0xC0 */

+  __IO uint32_t CALFACT;          /*!< ADC  Calibration Factors,                                   Address offset: 0xC4 */

+  __IO uint32_t CALFACT2;         /*!< ADC  Linearity Calibration Factors,                         Address offset: 0xC8 */

+} ADC_TypeDef;

+

+

+typedef struct

+{

+__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */

+uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */

+__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */

+__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */

+__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */

+

+} ADC_Common_TypeDef;

+

+

+/**

+  * @brief VREFBUF

+  */

+

+typedef struct

+{

+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */

+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */

+} VREFBUF_TypeDef;

+

+

+/**

+  * @brief FD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */

+  __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */

+  __IO uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */

+  __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */

+  __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */

+  __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */

+  __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */

+  __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */

+  __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */

+  __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */

+  __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */

+  __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */

+  __IO uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */

+  __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */

+  __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */

+  __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */

+  __IO uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */

+  __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */

+  __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */

+  __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */

+  __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */

+  __IO uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */

+  __IO uint32_t GFC;          /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */

+  __IO uint32_t SIDFC;        /*!< FDCAN Standard ID Filter Configuration register,                 Address offset: 0x084 */

+  __IO uint32_t XIDFC;        /*!< FDCAN Extended ID Filter Configuration register,                 Address offset: 0x088 */

+  __IO uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */

+  __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x090 */

+  __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x094 */

+  __IO uint32_t NDAT1;        /*!< FDCAN New Data 1 register,                                       Address offset: 0x098 */

+  __IO uint32_t NDAT2;        /*!< FDCAN New Data 2 register,                                       Address offset: 0x09C */

+  __IO uint32_t RXF0C;        /*!< FDCAN Rx FIFO 0 Configuration register,                          Address offset: 0x0A0 */

+  __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x0A4 */

+  __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x0A8 */

+  __IO uint32_t RXBC;         /*!< FDCAN Rx Buffer Configuration register,                          Address offset: 0x0AC */

+  __IO uint32_t RXF1C;        /*!< FDCAN Rx FIFO 1 Configuration register,                          Address offset: 0x0B0 */

+  __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x0B4 */

+  __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x0B8 */

+  __IO uint32_t RXESC;        /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register,        Address offset: 0x0BC */

+  __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */

+  __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */

+  __IO uint32_t TXESC;        /*!< FDCAN Tx Buffer Element Size Configuration register,             Address offset: 0x0C8 */

+  __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0CC */

+  __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0D0 */

+  __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D4 */

+  __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D8 */

+  __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0DC */

+  __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0E0 */

+  __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */

+  __IO uint32_t RESERVED6[2]; /*!< Reserved,                                                                0x0E8 - 0x0EC */

+  __IO uint32_t TXEFC;        /*!< FDCAN Tx Event FIFO Configuration register,                      Address offset: 0x0F0 */

+  __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0F4 */

+  __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0F8 */

+  __IO uint32_t RESERVED7;    /*!< Reserved,                                                                        0x0FC */

+} FDCAN_GlobalTypeDef;

+

+/**

+  * @brief TTFD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t TTTMC;          /*!< TT Trigger Memory Configuration register,    Address offset: 0x100 */

+  __IO uint32_t TTRMC;          /*!< TT Reference Message Configuration register, Address offset: 0x104 */

+  __IO uint32_t TTOCF;          /*!< TT Operation Configuration register,         Address offset: 0x108 */

+  __IO uint32_t TTMLM;          /*!< TT Matrix Limits register,                   Address offset: 0x10C */

+  __IO uint32_t TURCF;          /*!< TUR Configuration register,                  Address offset: 0x110 */

+  __IO uint32_t TTOCN;          /*!< TT Operation Control register,               Address offset: 0x114 */

+  __IO uint32_t TTGTP;          /*!< TT Global Time Preset register,              Address offset: 0x118 */

+  __IO uint32_t TTTMK;          /*!< TT Time Mark register,                       Address offset: 0x11C */

+  __IO uint32_t TTIR;           /*!< TT Interrupt register,                       Address offset: 0x120 */

+  __IO uint32_t TTIE;           /*!< TT Interrupt Enable register,                Address offset: 0x124 */

+  __IO uint32_t TTILS;          /*!< TT Interrupt Line Select register,           Address offset: 0x128 */

+  __IO uint32_t TTOST;          /*!< TT Operation Status register,                Address offset: 0x12C */

+  __IO uint32_t TURNA;          /*!< TT TUR Numerator Actual register,            Address offset: 0x130 */

+  __IO uint32_t TTLGT;          /*!< TT Local and Global Time register,           Address offset: 0x134 */

+  __IO uint32_t TTCTC;          /*!< TT Cycle Time and Count register,            Address offset: 0x138 */

+  __IO uint32_t TTCPT;          /*!< TT Capture Time register,                    Address offset: 0x13C */

+  __IO uint32_t TTCSM;          /*!< TT Cycle Sync Mark register,                 Address offset: 0x140 */

+  __IO uint32_t RESERVED1[111]; /*!< Reserved,                                            0x144 - 0x2FC */

+  __IO uint32_t TTTS;           /*!< TT Trigger Select register,                  Address offset: 0x300 */

+} TTCAN_TypeDef;

+

+/**

+  * @brief FD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t CREL;  /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */

+  __IO uint32_t CCFG;  /*!< Calibration Configuration register,           Address offset: 0x04 */

+  __IO uint32_t CSTAT; /*!< Calibration Status register,                  Address offset: 0x08 */

+  __IO uint32_t CWD;   /*!< Calibration Watchdog register,                Address offset: 0x0C */

+  __IO uint32_t IR;    /*!< CCU Interrupt register,                       Address offset: 0x10 */

+  __IO uint32_t IE;    /*!< CCU Interrupt Enable register,                Address offset: 0x14 */

+} FDCAN_ClockCalibrationUnit_TypeDef;

+

+

+/**

+  * @brief Consumer Electronics Control

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;           /*!< CEC control register,              Address offset:0x00 */

+  __IO uint32_t CFGR;         /*!< CEC configuration register,        Address offset:0x04 */

+  __IO uint32_t TXDR;         /*!< CEC Tx data register ,             Address offset:0x08 */

+  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,              Address offset:0x0C */

+  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register, Address offset:0x10 */

+  __IO uint32_t IER;          /*!< CEC interrupt enable register,     Address offset:0x14 */

+}CEC_TypeDef;

+

+/**

+  * @brief CRC calculation unit

+  */

+

+typedef struct

+{

+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */

+  __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */

+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */

+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */

+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */

+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */

+} CRC_TypeDef;

+

+

+/**

+  * @brief Clock Recovery System

+  */

+typedef struct

+{

+__IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */

+__IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */

+__IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */

+__IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */

+} CRS_TypeDef;

+

+

+/**

+  * @brief Digital to Analog Converter

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */

+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */

+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */

+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */

+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */

+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */

+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */

+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */

+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */

+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */

+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */

+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */

+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */

+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */

+  __IO uint32_t CCR;      /*!< DAC calibration control register,                        Address offset: 0x38 */

+  __IO uint32_t MCR;      /*!< DAC mode control register,                               Address offset: 0x3C */

+  __IO uint32_t SHSR1;    /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */

+  __IO uint32_t SHSR2;    /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */

+  __IO uint32_t SHHR;     /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */

+  __IO uint32_t SHRR;     /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */

+} DAC_TypeDef;

+

+/**

+  * @brief DFSDM module registers

+  */

+typedef struct

+{

+  __IO uint32_t FLTCR1;          /*!< DFSDM control register1,                          Address offset: 0x100 */

+  __IO uint32_t FLTCR2;          /*!< DFSDM control register2,                          Address offset: 0x104 */

+  __IO uint32_t FLTISR;          /*!< DFSDM interrupt and status register,              Address offset: 0x108 */

+  __IO uint32_t FLTICR;          /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */

+  __IO uint32_t FLTJCHGR;        /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */

+  __IO uint32_t FLTFCR;          /*!< DFSDM filter control register,                    Address offset: 0x114 */

+  __IO uint32_t FLTJDATAR;       /*!< DFSDM data register for injected group,           Address offset: 0x118 */

+  __IO uint32_t FLTRDATAR;       /*!< DFSDM data register for regular group,            Address offset: 0x11C */

+  __IO uint32_t FLTAWHTR;        /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */

+  __IO uint32_t FLTAWLTR;        /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */

+  __IO uint32_t FLTAWSR;         /*!< DFSDM analog watchdog status register             Address offset: 0x128 */

+  __IO uint32_t FLTAWCFR;        /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */

+  __IO uint32_t FLTEXMAX;        /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */

+  __IO uint32_t FLTEXMIN;        /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */

+  __IO uint32_t FLTCNVTIMR;      /*!< DFSDM conversion timer,                           Address offset: 0x138 */

+} DFSDM_Filter_TypeDef;

+

+/**

+  * @brief DFSDM channel configuration registers

+  */

+typedef struct

+{

+  __IO uint32_t CHCFGR1;      /*!< DFSDM channel configuration register1,            Address offset: 0x00 */

+  __IO uint32_t CHCFGR2;      /*!< DFSDM channel configuration register2,            Address offset: 0x04 */

+  __IO uint32_t CHAWSCDR;     /*!< DFSDM channel analog watchdog and

+                                   short circuit detector register,                  Address offset: 0x08 */

+  __IO uint32_t CHWDATAR;     /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */

+  __IO uint32_t CHDATINR;     /*!< DFSDM channel data input register,                Address offset: 0x10 */

+  __IO uint32_t CHDLYR;       /*!< DFSDM channel delay register,                     Address offset: 0x14 */

+} DFSDM_Channel_TypeDef;

+

+/**

+  * @brief Debug MCU

+  */

+typedef struct

+{

+  __IO uint32_t IDCODE;        /*!< MCU device ID code,                     Address offset: 0x00 */

+  __IO uint32_t CR;            /*!< Debug MCU configuration register,       Address offset: 0x04 */

+  uint32_t RESERVED4[11];      /*!< Reserved,                             Address offset: 0x08 */

+  __IO uint32_t APB3FZ1;     /*!< Debug MCU APB3FZ1 freeze register,    Address offset: 0x34 */

+  uint32_t RESERVED5;          /*!< Reserved,                             Address offset: 0x38 */

+  __IO uint32_t APB1LFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x3C */

+  uint32_t RESERVED6;          /*!< Reserved,                             Address offset: 0x40 */

+  __IO uint32_t APB1HFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x44 */

+  uint32_t RESERVED7;          /*!< Reserved,                             Address offset: 0x48 */

+  __IO uint32_t APB2FZ1;     /*!< Debug MCU APB2FZ1 freeze register,    Address offset: 0x4C */

+  uint32_t RESERVED8;          /*!< Reserved,                             Address offset: 0x50 */

+  __IO uint32_t APB4FZ1;     /*!< Debug MCU APB4FZ1 freeze register,    Address offset: 0x54 */

+}DBGMCU_TypeDef;

+/**

+  * @brief DCMI

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */

+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */

+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */

+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */

+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */

+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */

+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */

+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */

+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */

+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */

+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */

+} DCMI_TypeDef;

+

+/**

+  * @brief PSSI

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;             /*!< PSSI control register 1,               Address offset: 0x000 */

+  __IO uint32_t SR;             /*!< PSSI status register,                  Address offset: 0x004 */

+  __IO uint32_t RIS;            /*!< PSSI raw interrupt status register,    Address offset: 0x008 */

+  __IO uint32_t IER;            /*!< PSSI interrupt enable register,        Address offset: 0x00C */

+  __IO uint32_t MIS;            /*!< PSSI masked interrupt status register, Address offset: 0x010 */

+  __IO uint32_t ICR;            /*!< PSSI interrupt clear register,         Address offset: 0x014 */

+  __IO uint32_t RESERVED1[4];   /*!< Reserved,                                      0x018 - 0x024 */

+  __IO uint32_t DR;             /*!< PSSI data register,                    Address offset: 0x028 */

+  __IO uint32_t RESERVED2[241]; /*!< Reserved,                                      0x02C - 0x3EC */

+  __IO uint32_t HWCFGR;         /*!< PSSI IP HW configuration register,     Address offset: 0x3F0 */

+  __IO uint32_t VERR;           /*!< PSSI IP version register,              Address offset: 0x3F4 */

+  __IO uint32_t IPIDR;          /*!< PSSI IP ID register,                   Address offset: 0x3F8 */

+  __IO uint32_t SIDR;           /*!< PSSI SIZE ID register,                 Address offset: 0x3FC */

+} PSSI_TypeDef;

+

+/**

+  * @brief DMA Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */

+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */

+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */

+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */

+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */

+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */

+} DMA_Stream_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */

+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */

+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */

+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */

+} DMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CCR;          /*!< DMA channel x configuration register          */

+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register         */

+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register     */

+  __IO uint32_t CM0AR;        /*!< DMA channel x memory 0 address register       */

+  __IO uint32_t CM1AR;        /*!< DMA channel x memory 1 address register       */

+} BDMA_Channel_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */

+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */

+} BDMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CCR;        /*!< DMA Multiplexer Channel x Control Register   */

+}DMAMUX_Channel_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CSR;      /*!< DMA Channel Status Register     */

+  __IO uint32_t  CFR;      /*!< DMA Channel Clear Flag Register */

+}DMAMUX_ChannelStatus_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  RGCR;        /*!< DMA Request Generator x Control Register   */

+}DMAMUX_RequestGen_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  RGSR;        /*!< DMA Request Generator Status Register       */

+  __IO uint32_t  RGCFR;       /*!< DMA Request Generator Clear Flag Register   */

+}DMAMUX_RequestGenStatus_TypeDef;

+

+/**

+  * @brief MDMA Controller

+  */

+typedef struct

+{

+  __IO uint32_t  GISR0;   /*!< MDMA Global Interrupt/Status Register 0,          Address offset: 0x00 */

+}MDMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CISR;      /*!< MDMA channel x interrupt/status register,             Address offset: 0x40 */

+  __IO uint32_t  CIFCR;     /*!< MDMA channel x interrupt flag clear register,         Address offset: 0x44 */

+  __IO uint32_t  CESR;      /*!< MDMA Channel x error status register,                 Address offset: 0x48 */

+  __IO uint32_t  CCR;       /*!< MDMA channel x control register,                      Address offset: 0x4C */

+  __IO uint32_t  CTCR;      /*!< MDMA channel x Transfer Configuration register,       Address offset: 0x50 */

+  __IO uint32_t  CBNDTR;    /*!< MDMA Channel x block number of data register,         Address offset: 0x54 */

+  __IO uint32_t  CSAR;      /*!< MDMA channel x source address register,               Address offset: 0x58 */

+  __IO uint32_t  CDAR;      /*!< MDMA channel x destination address register,          Address offset: 0x5C */

+  __IO uint32_t  CBRUR;     /*!< MDMA channel x Block Repeat address Update register,  Address offset: 0x60 */

+  __IO uint32_t  CLAR;      /*!< MDMA channel x Link Address register,                 Address offset: 0x64 */

+  __IO uint32_t  CTBR;      /*!< MDMA channel x Trigger and Bus selection Register,    Address offset: 0x68 */

+  uint32_t       RESERVED0; /*!< Reserved, 0x68                                                             */

+  __IO uint32_t  CMAR;      /*!< MDMA channel x Mask address register,                 Address offset: 0x70 */

+  __IO uint32_t  CMDR;      /*!< MDMA channel x Mask Data register,                    Address offset: 0x74 */

+}MDMA_Channel_TypeDef;

+

+/**

+  * @brief DMA2D Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */

+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */

+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */

+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */

+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */

+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */

+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */

+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */

+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */

+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */

+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */

+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */

+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */

+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */

+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */

+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */

+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */

+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */

+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */

+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */

+  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */

+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */

+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */

+} DMA2D_TypeDef;

+

+

+/**

+  * @brief External Interrupt/Event Controller

+  */

+

+typedef struct

+{

+__IO uint32_t RTSR1;               /*!< EXTI Rising trigger selection register,          Address offset: 0x00 */

+__IO uint32_t FTSR1;               /*!< EXTI Falling trigger selection register,         Address offset: 0x04 */

+__IO uint32_t SWIER1;              /*!< EXTI Software interrupt event register,          Address offset: 0x08 */

+__IO uint32_t D3PMR1;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */

+__IO uint32_t D3PCR1L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L)     Address offset: 0x10 */

+__IO uint32_t D3PCR1H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H)   Address offset: 0x14 */

+uint32_t      RESERVED1[2];        /*!< Reserved,                                        0x18 to 0x1C         */

+__IO uint32_t RTSR2;               /*!< EXTI Rising trigger selection register,          Address offset: 0x20 */

+__IO uint32_t FTSR2;               /*!< EXTI Falling trigger selection register,         Address offset: 0x24 */

+__IO uint32_t SWIER2;              /*!< EXTI Software interrupt event register,          Address offset: 0x28 */

+__IO uint32_t D3PMR2;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */

+__IO uint32_t D3PCR2L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L)  Address offset: 0x30 */

+__IO uint32_t D3PCR2H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */

+uint32_t      RESERVED2[2];        /*!< Reserved,                                        0x38 to 0x3C         */

+__IO uint32_t RTSR3;               /*!< EXTI Rising trigger selection register,          Address offset: 0x40 */

+__IO uint32_t FTSR3;               /*!< EXTI Falling trigger selection register,         Address offset: 0x44 */

+__IO uint32_t SWIER3;              /*!< EXTI Software interrupt event register,          Address offset: 0x48 */

+__IO uint32_t D3PMR3;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */

+__IO uint32_t D3PCR3L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */

+__IO uint32_t D3PCR3H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */

+uint32_t      RESERVED3[10];       /*!< Reserved,                                        0x58 to 0x7C         */

+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                    Address offset: 0x80 */

+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                        Address offset: 0x84 */

+__IO uint32_t PR1;                 /*!< EXTI Pending register,                           Address offset: 0x88 */

+uint32_t      RESERVED4;           /*!< Reserved,                                        0x8C                 */

+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                    Address offset: 0x90 */

+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                        Address offset: 0x94 */

+__IO uint32_t PR2;                 /*!< EXTI Pending register,                           Address offset: 0x98 */

+uint32_t      RESERVED5;           /*!< Reserved,                                        0x9C                 */

+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                    Address offset: 0xA0 */

+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                        Address offset: 0xA4 */

+__IO uint32_t PR3;                 /*!< EXTI Pending register,                           Address offset: 0xA8 */

+}EXTI_TypeDef;

+

+typedef struct

+{

+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                Address offset: 0x00 */

+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                    Address offset: 0x04 */

+__IO uint32_t PR1;                 /*!< EXTI Pending register,                       Address offset: 0x08 */

+uint32_t      RESERVED1;           /*!< Reserved, 0x0C                                                    */

+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                Address offset: 0x10 */

+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                    Address offset: 0x14 */

+__IO uint32_t PR2;                 /*!< EXTI Pending register,                       Address offset: 0x18 */

+uint32_t      RESERVED2;           /*!< Reserved, 0x1C                                                    */

+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                Address offset: 0x20 */

+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                    Address offset: 0x24 */

+__IO uint32_t PR3;                 /*!< EXTI Pending register,                       Address offset: 0x28 */

+}EXTI_Core_TypeDef;

+

+

+/**

+  * @brief FLASH Registers

+  */

+

+typedef struct

+{

+  __IO uint32_t ACR;             /*!< FLASH access control register,                            Address offset: 0x00  */

+  __IO uint32_t KEYR1;           /*!< Flash Key Register for bank1,                             Address offset: 0x04  */

+  __IO uint32_t OPTKEYR;         /*!< Flash Option Key Register,                                Address offset: 0x08  */

+  __IO uint32_t CR1;             /*!< Flash Control Register for bank1,                         Address offset: 0x0C  */

+  __IO uint32_t SR1;             /*!< Flash Status Register for bank1,                          Address offset: 0x10  */

+  __IO uint32_t CCR1;            /*!< Flash Control Register for bank1,                         Address offset: 0x14  */

+  __IO uint32_t OPTCR;           /*!< Flash Option Control Register,                            Address offset: 0x18  */

+  __IO uint32_t OPTSR_CUR;       /*!< Flash Option Status Current Register,                     Address offset: 0x1C  */

+  __IO uint32_t OPTSR_PRG;       /*!< Flash Option Status to Program Register,                  Address offset: 0x20  */

+  __IO uint32_t OPTCCR;          /*!< Flash Option Clear Control Register,                      Address offset: 0x24  */

+  __IO uint32_t PRAR_CUR1;       /*!< Flash Current Protection Address Register for bank1,      Address offset: 0x28  */

+  __IO uint32_t PRAR_PRG1;       /*!< Flash Protection Address to Program Register for bank1,   Address offset: 0x2C  */

+  __IO uint32_t SCAR_CUR1;       /*!< Flash Current Secure Address Register for bank1,          Address offset: 0x30  */

+  __IO uint32_t SCAR_PRG1;       /*!< Flash Secure Address to Program Register for bank1,       Address offset: 0x34  */

+  __IO uint32_t WPSN_CUR1;       /*!< Flash Current Write Protection Register on bank1,         Address offset: 0x38  */

+  __IO uint32_t WPSN_PRG1;       /*!< Flash Write Protection to Program Register on bank1,      Address offset: 0x3C  */

+  __IO uint32_t BOOT_CUR;        /*!< Flash Current Boot Address for Pelican Core Register,     Address offset: 0x40  */

+  __IO uint32_t BOOT_PRG;        /*!< Flash Boot Address to Program for Pelican Core Register,  Address offset: 0x44  */

+  uint32_t      RESERVED0[2];    /*!< Reserved, 0x48 to 0x4C                                                          */

+  __IO uint32_t CRCCR1;          /*!< Flash CRC Control register For Bank1 Register ,           Address offset: 0x50  */

+  __IO uint32_t CRCSADD1;        /*!< Flash CRC Start Address Register for Bank1 ,              Address offset: 0x54  */

+  __IO uint32_t CRCEADD1;        /*!< Flash CRC End Address Register for Bank1 ,                Address offset: 0x58  */

+  __IO uint32_t CRCDATA;         /*!< Flash CRC Data Register for Bank1 ,                       Address offset: 0x5C  */

+  __IO uint32_t ECC_FA1;         /*!< Flash ECC Fail Address For Bank1 Register ,               Address offset: 0x60  */

+  uint32_t      RESERVED;        /*!< Reserved, 0x64                                                                  */

+  __IO uint32_t OTPBL_CUR;       /*!< Flash Current OTP Block Lock Register,                    Address offset: 0x68  */

+  __IO uint32_t OTPBL_PRG;       /*!< Flash OTP Block Lock to Program Register,                 Address offset: 0x6C  */

+  uint32_t      RESERVED1[37];   /*!< Reserved, 0x70 to 0x100                                                         */

+  __IO uint32_t KEYR2;           /*!< Flash Key Register for bank2,                             Address offset: 0x104 */

+  uint32_t      RESERVED2;       /*!< Reserved, 0x108                                                                 */

+  __IO uint32_t CR2;             /*!< Flash Control Register for bank2,                         Address offset: 0x10C */

+  __IO uint32_t SR2;             /*!< Flash Status Register for bank2,                          Address offset: 0x110 */

+  __IO uint32_t CCR2;            /*!< Flash Status Register for bank2,                          Address offset: 0x114 */

+  uint32_t      RESERVED3[4];    /*!< Reserved, 0x118 to 0x124                                                        */

+  __IO uint32_t PRAR_CUR2;       /*!< Flash Current Protection Address Register for bank2,      Address offset: 0x128 */

+  __IO uint32_t PRAR_PRG2;       /*!< Flash Protection Address to Program Register for bank2,   Address offset: 0x12C */

+  __IO uint32_t SCAR_CUR2;       /*!< Flash Current Secure Address Register for bank2,          Address offset: 0x130 */

+  __IO uint32_t SCAR_PRG2;       /*!< Flash Secure Address Register for bank2,                  Address offset: 0x134 */

+  __IO uint32_t WPSN_CUR2;       /*!< Flash Current Write Protection Register on bank2,         Address offset: 0x138 */

+  __IO uint32_t WPSN_PRG2;       /*!< Flash Write Protection to Program Register on bank2,      Address offset: 0x13C */

+  uint32_t      RESERVED4[4];    /*!< Reserved, 0x140 to 0x14C                                                        */

+  __IO uint32_t CRCCR2;          /*!< Flash CRC Control register For Bank2 Register ,           Address offset: 0x150 */

+  __IO uint32_t CRCSADD2;        /*!< Flash CRC Start Address Register for Bank2 ,              Address offset: 0x154 */

+  __IO uint32_t CRCEADD2;        /*!< Flash CRC End Address Register for Bank2 ,                Address offset: 0x158 */

+  __IO uint32_t CRCDATA2;        /*!< Flash CRC Data Register for Bank2 ,                       Address offset: 0x15C */

+  __IO uint32_t ECC_FA2;         /*!< Flash ECC Fail Address For Bank2 Register ,               Address offset: 0x160 */

+} FLASH_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */

+} FMC_Bank1_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank1E

+  */

+

+typedef struct

+{

+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */

+} FMC_Bank1E_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank2

+  */

+

+typedef struct

+{

+  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */

+  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */

+  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */

+  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */

+  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */

+  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */

+} FMC_Bank2_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank3

+  */

+

+typedef struct

+{

+  __IO uint32_t PCR;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */

+  __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */

+  __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */

+  __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */

+  uint32_t      RESERVED;  /*!< Reserved, 0x90                                                            */

+  __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */

+} FMC_Bank3_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank5 and 6

+  */

+

+

+typedef struct

+{

+  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */

+  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */

+  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */

+  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */

+  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */

+} FMC_Bank5_6_TypeDef;

+

+/**

+  * @brief GFXMMU registers

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;              /*!< GFXMMU configuration register,                     Address offset: 0x00 */

+  __IO uint32_t SR;              /*!< GFXMMU status register,                            Address offset: 0x04 */

+  __IO uint32_t FCR;             /*!< GFXMMU flag clear register,                        Address offset: 0x08 */

+  __IO uint32_t CCR;             /*!< GFXMMU Cache Control Register,                     Address offset: 0x0C */

+  __IO uint32_t DVR;             /*!< GFXMMU default value register,                     Address offset: 0x10 */

+       uint32_t RESERVED1[3];    /*!< Reserved1,                                         Address offset: 0x14 to 0x1C */

+  __IO uint32_t B0CR;            /*!< GFXMMU buffer 0 configuration register,            Address offset: 0x20 */

+  __IO uint32_t B1CR;            /*!< GFXMMU buffer 1 configuration register,            Address offset: 0x24 */

+  __IO uint32_t B2CR;            /*!< GFXMMU buffer 2 configuration register,            Address offset: 0x28 */

+  __IO uint32_t B3CR;            /*!< GFXMMU buffer 3 configuration register,            Address offset: 0x2C */

+       uint32_t RESERVED2[1012]; /*!< Reserved2,                                         Address offset: 0x30 to 0xFFC */

+  __IO uint32_t LUT[2048];       /*!< GFXMMU LUT registers,                              Address offset: 0x1000 to 0x2FFC

+                                      For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */

+} GFXMMU_TypeDef;

+/**

+  * @brief General Purpose I/O

+  */

+

+typedef struct

+{

+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */

+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */

+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */

+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */

+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */

+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */

+  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset,               Address offset: 0x18      */

+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */

+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */

+} GPIO_TypeDef;

+

+/**

+  * @brief Operational Amplifier (OPAMP)

+  */

+

+typedef struct

+{

+  __IO uint32_t CSR;          /*!< OPAMP control/status register,                      Address offset: 0x00 */

+  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,     Address offset: 0x04 */

+  __IO uint32_t HSOTR;        /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */

+} OPAMP_TypeDef;

+

+/**

+  * @brief System configuration controller

+  */

+

+typedef struct

+{

+ uint32_t RESERVED1;           /*!< Reserved,                                           Address offset: 0x00        */

+ __IO uint32_t PMCR;           /*!< SYSCFG peripheral mode configuration register,      Address offset: 0x04        */

+ __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration registers,  Address offset: 0x08-0x14   */

+ __IO uint32_t CFGR;           /*!< SYSCFG configuration registers,                     Address offset: 0x18        */

+ uint32_t RESERVED2;           /*!< Reserved,                                           Address offset: 0x1C        */

+ __IO uint32_t CCCSR;          /*!< SYSCFG compensation cell control/status register,   Address offset: 0x20        */

+ __IO uint32_t CCVR;           /*!< SYSCFG compensation cell value register,            Address offset: 0x24        */

+ __IO uint32_t CCCR;           /*!< SYSCFG compensation cell code register,             Address offset: 0x28        */

+

+} SYSCFG_TypeDef;

+

+/**

+  * @brief Inter-integrated Circuit Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */

+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */

+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */

+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */

+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */

+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */

+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */

+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */

+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */

+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */

+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */

+} I2C_TypeDef;

+

+/**

+  * @brief Independent WATCHDOG

+  */

+

+typedef struct

+{

+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */

+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */

+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */

+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */

+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */

+} IWDG_TypeDef;

+

+

+/**

+  * @brief JPEG Codec

+  */

+typedef struct

+{

+  __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */

+  __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */

+  __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */

+  __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */

+  __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */

+  __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */

+  __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */

+  __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */

+  uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */

+  __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */

+  __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */

+  __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */

+  uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */

+  __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */

+  __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */

+  uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */

+  __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */

+  __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */

+  __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */

+  __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */

+  __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */

+  __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */

+  __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */

+  __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */

+  uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */

+  __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0,                 Address offset: 500h-65Ch */

+  __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1,                 Address offset: 660h-7BCh */

+  __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encodor, DC Huffman table 0,                 Address offset: 7C0h-7DCh */

+  __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encodor, DC Huffman table 1,                 Address offset: 7E0h-7FCh */

+

+} JPEG_TypeDef;

+

+/**

+  * @brief LCD-TFT Display Controller

+  */

+

+typedef struct

+{

+  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04                                                       */

+  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */

+  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */

+  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */

+  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */

+  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */

+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20                                                       */

+  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */

+  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28                                                            */

+  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */

+  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30                                                            */

+  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */

+  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */

+  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */

+  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */

+  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */

+  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */

+} LTDC_TypeDef;

+

+/**

+  * @brief LCD-TFT Display layer x Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */

+  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */

+  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */

+  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */

+  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */

+  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */

+  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */

+  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */

+  uint32_t      RESERVED0[2];  /*!< Reserved */

+  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */

+  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */

+  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */

+  uint32_t      RESERVED1[3];  /*!< Reserved */

+  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */

+

+} LTDC_Layer_TypeDef;

+

+/**

+  * @brief Power Control

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;       /*!< PWR power control register 1,            Address offset: 0x00 */

+  __IO uint32_t CSR1;      /*!< PWR power control status register 1,     Address offset: 0x04 */

+  __IO uint32_t CR2;       /*!< PWR power control register 2,            Address offset: 0x08 */

+  __IO uint32_t CR3;       /*!< PWR power control register 3,            Address offset: 0x0C */

+  __IO uint32_t CPUCR;     /*!< PWR CPU control register,                Address offset: 0x10 */

+       uint32_t RESERVED0; /*!< Reserved,                                Address offset: 0x14 */

+  __IO uint32_t SRDCR;     /*!< PWR SRD domain control register,         Address offset: 0x18 */

+       uint32_t RESERVED1; /*!< Reserved,                                Address offset: 0x1C */

+  __IO uint32_t WKUPCR;    /*!< PWR wakeup clear register,               Address offset: 0x20 */

+  __IO uint32_t WKUPFR;    /*!< PWR wakeup flag register,                Address offset: 0x24 */

+  __IO uint32_t WKUPEPR;   /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */

+} PWR_TypeDef;

+

+/**

+  * @brief Reset and Clock Control

+  */

+

+typedef struct

+{

+ __IO uint32_t CR;             /*!< RCC clock control register,                                              Address offset: 0x00  */

+ __IO uint32_t HSICFGR;        /*!< HSI Clock Calibration Register,                                          Address offset: 0x04  */

+ __IO uint32_t CRRCR;          /*!< Clock Recovery RC  Register,                                             Address offset: 0x08  */

+ __IO uint32_t CSICFGR;        /*!< CSI Clock Calibration Register,                                          Address offset: 0x0C  */

+ __IO uint32_t CFGR;           /*!< RCC clock configuration register,                                        Address offset: 0x10  */

+ uint32_t     RESERVED1;       /*!< Reserved,                                                                Address offset: 0x14  */

+ __IO uint32_t CDCFGR1;         /*!< RCC Domain 1 configuration register,                                    Address offset: 0x18  */

+ __IO uint32_t CDCFGR2;         /*!< RCC Domain 2 configuration register,                                    Address offset: 0x1C  */

+ __IO uint32_t SRDCFGR;         /*!< RCC Domain 3 configuration register,                                    Address offset: 0x20  */

+ uint32_t     RESERVED2;       /*!< Reserved,                                                                Address offset: 0x24  */

+ __IO uint32_t PLLCKSELR;      /*!< RCC PLLs Clock Source Selection Register,                                Address offset: 0x28  */

+ __IO uint32_t PLLCFGR;        /*!< RCC PLLs  Configuration Register,                                        Address offset: 0x2C  */

+ __IO uint32_t PLL1DIVR;       /*!< RCC PLL1 Dividers Configuration Register,                                Address offset: 0x30  */

+ __IO uint32_t PLL1FRACR;      /*!< RCC PLL1 Fractional Divider Configuration Register,                      Address offset: 0x34  */

+ __IO uint32_t PLL2DIVR;       /*!< RCC PLL2 Dividers Configuration Register,                                Address offset: 0x38  */

+ __IO uint32_t PLL2FRACR;      /*!< RCC PLL2 Fractional Divider Configuration Register,                      Address offset: 0x3C  */

+ __IO uint32_t PLL3DIVR;       /*!< RCC PLL3 Dividers Configuration Register,                                Address offset: 0x40  */

+ __IO uint32_t PLL3FRACR;      /*!< RCC PLL3 Fractional Divider Configuration Register,                      Address offset: 0x44  */

+ uint32_t      RESERVED3;      /*!< Reserved,                                                                Address offset: 0x48  */

+ __IO uint32_t  CDCCIPR;       /*!< RCC Domain 1 Kernel Clock Configuration Register                         Address offset: 0x4C  */

+ __IO uint32_t  CDCCIP1R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x50  */

+ __IO uint32_t  CDCCIP2R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x54  */

+ __IO uint32_t  SRDCCIPR;       /*!< RCC Domain 3 Kernel Clock Configuration Register                         Address offset: 0x58  */

+ uint32_t      RESERVED4;      /*!< Reserved,                                                                Address offset: 0x5C  */

+ __IO uint32_t  CIER;          /*!< RCC Clock Source Interrupt Enable Register                               Address offset: 0x60  */

+ __IO uint32_t  CIFR;          /*!< RCC Clock Source Interrupt Flag Register                                 Address offset: 0x64  */

+ __IO uint32_t  CICR;          /*!< RCC Clock Source Interrupt Clear Register                                Address offset: 0x68  */

+ uint32_t     RESERVED5;       /*!< Reserved,                                                                Address offset: 0x6C  */

+ __IO uint32_t  BDCR;          /*!< RCC Vswitch Backup Domain Control Register,                              Address offset: 0x70  */

+ __IO uint32_t  CSR;           /*!< RCC clock control & status register,                                     Address offset: 0x74  */

+ uint32_t     RESERVED6;       /*!< Reserved,                                                                Address offset: 0x78  */

+ __IO uint32_t AHB3RSTR;       /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x7C  */

+ __IO uint32_t AHB1RSTR;       /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x80  */

+ __IO uint32_t AHB2RSTR;       /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x84  */

+ __IO uint32_t AHB4RSTR;       /*!< RCC AHB4 peripheral reset register,                                      Address offset: 0x88  */

+ __IO uint32_t APB3RSTR;       /*!< RCC APB3 peripheral reset register,                                      Address offset: 0x8C  */

+ __IO uint32_t APB1LRSTR;      /*!< RCC APB1 peripheral reset Low Word register,                             Address offset: 0x90  */

+ __IO uint32_t APB1HRSTR;      /*!< RCC APB1 peripheral reset High Word register,                            Address offset: 0x94  */

+ __IO uint32_t APB2RSTR;       /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x98  */

+ __IO uint32_t APB4RSTR;       /*!< RCC APB4 peripheral reset register,                                      Address offset: 0x9C  */

+ uint32_t     RESERVED7;       /*!< Reserved,                                                                Address offset: 0xA0  */

+ uint32_t     RESERVED8;       /*!< Reserved,                                                                Address offset: 0xA4  */

+ __IO uint32_t SRDAMR;         /*!< RCC Domain 3 Autonomous Mode Register,                                   Address offset: 0xA8  */

+  uint32_t     RESERVED9;      /*!< Reserved, 0xAC-0xAF                                                      Address offset: 0xAC  */

+ __IO uint32_t CKGAENR;        /*!< AXI Clocks Gating Enable Register,                                       Address offset: 0xB0  */

+  uint32_t     RESERVED10[31];   /*!< Reserved, 0xAC-0xAF                                                    Address offset: 0xAC  */

+ __IO uint32_t RSR;            /*!< RCC Reset status register,                                               Address offset: 0xD0  */

+ __IO uint32_t AHB3ENR;        /*!< RCC AHB3 peripheral clock  register,                                     Address offset: 0xD4  */

+ __IO uint32_t AHB1ENR;        /*!< RCC AHB1 peripheral clock  register,                                     Address offset: 0xD8  */

+ __IO uint32_t AHB2ENR;        /*!< RCC AHB2 peripheral clock  register,                                     Address offset: 0xDC  */

+ __IO uint32_t AHB4ENR;        /*!< RCC AHB4 peripheral clock  register,                                     Address offset: 0xE0  */

+ __IO uint32_t APB3ENR;        /*!< RCC APB3 peripheral clock  register,                                     Address offset: 0xE4  */

+ __IO uint32_t APB1LENR;       /*!< RCC APB1 peripheral clock  Low Word register,                            Address offset: 0xE8  */

+ __IO uint32_t APB1HENR;       /*!< RCC APB1 peripheral clock  High Word register,                           Address offset: 0xEC  */

+ __IO uint32_t APB2ENR;        /*!< RCC APB2 peripheral clock  register,                                     Address offset: 0xF0  */

+ __IO uint32_t APB4ENR;        /*!< RCC APB4 peripheral clock  register,                                     Address offset: 0xF4  */

+ uint32_t      RESERVED12;      /*!< Reserved,                                                                Address offset: 0xF8  */

+ __IO uint32_t AHB3LPENR;      /*!< RCC AHB3 peripheral sleep clock  register,                               Address offset: 0xFC  */

+ __IO uint32_t AHB1LPENR;      /*!< RCC AHB1 peripheral sleep clock  register,                               Address offset: 0x100 */

+ __IO uint32_t AHB2LPENR;      /*!< RCC AHB2 peripheral sleep clock  register,                               Address offset: 0x104 */

+ __IO uint32_t AHB4LPENR;      /*!< RCC AHB4 peripheral sleep clock  register,                               Address offset: 0x108 */

+ __IO uint32_t APB3LPENR;      /*!< RCC APB3 peripheral sleep clock  register,                               Address offset: 0x10C */

+ __IO uint32_t APB1LLPENR;     /*!< RCC APB1 peripheral sleep clock  Low Word register,                      Address offset: 0x110 */

+ __IO uint32_t APB1HLPENR;     /*!< RCC APB1 peripheral sleep clock  High Word register,                     Address offset: 0x114 */

+ __IO uint32_t APB2LPENR;      /*!< RCC APB2 peripheral sleep clock  register,                               Address offset: 0x118 */

+ __IO uint32_t APB4LPENR;      /*!< RCC APB4 peripheral sleep clock  register,                               Address offset: 0x11C */

+ uint32_t     RESERVED13[4];   /*!< Reserved, 0x120-0x12C                                                    Address offset: 0x120 */

+

+} RCC_TypeDef;

+

+

+/**

+  * @brief Real-Time Clock

+  */

+typedef struct

+{

+  __IO uint32_t TR;             /*!< RTC time register,                              Address offset: 0x00 */

+  __IO uint32_t DR;             /*!< RTC date register,                              Address offset: 0x04 */

+  __IO uint32_t SSR;            /*!< RTC sub second register,                        Address offset: 0x08 */

+  __IO uint32_t ICSR;           /*!< RTC initialization control and status register, Address offset: 0x0C */

+  __IO uint32_t PRER;           /*!< RTC prescaler register,                         Address offset: 0x10 */

+  __IO uint32_t WUTR;           /*!< RTC wakeup timer register,                      Address offset: 0x14 */

+  __IO uint32_t CR;             /*!< RTC control register,                           Address offset: 0x18 */

+       uint32_t RESERVED0;      /*!< Reserved,                                       Address offset: 0x1C */

+       uint32_t RESERVED1;      /*!< Reserved,                                       Address offset: 0x20 */

+  __IO uint32_t WPR;            /*!< RTC write protection register,                  Address offset: 0x24 */

+  __IO uint32_t CALR;           /*!< RTC calibration register,                       Address offset: 0x28 */

+  __IO uint32_t SHIFTR;         /*!< RTC shift control register,                     Address offset: 0x2C */

+  __IO uint32_t TSTR;           /*!< RTC time stamp time register,                   Address offset: 0x30 */

+  __IO uint32_t TSDR;           /*!< RTC time stamp date register,                   Address offset: 0x34 */

+  __IO uint32_t TSSSR;          /*!< RTC time-stamp sub second register,             Address offset: 0x38 */

+       uint32_t RESERVED2;      /*!< Reserved,                                       Address offset: 0x3C */

+  __IO uint32_t ALRMAR;         /*!< RTC alarm A register,                           Address offset: 0x40 */

+  __IO uint32_t ALRMASSR;       /*!< RTC alarm A sub second register,                Address offset: 0x44 */

+  __IO uint32_t ALRMBR;         /*!< RTC alarm B register,                           Address offset: 0x48 */

+  __IO uint32_t ALRMBSSR;       /*!< RTC alarm B sub second register,                Address offset: 0x4C */

+  __IO uint32_t SR;             /*!< RTC Status register,                            Address offset: 0x50 */

+  __IO uint32_t MISR;           /*!< RTC masked interrupt status register,           Address offset: 0x54 */

+       uint32_t RESERVED3;      /*!< Reserved,                                       Address offset: 0x58 */

+  __IO uint32_t SCR;            /*!< RTC status Clear register,                      Address offset: 0x5C */

+  __IO uint32_t CFGR;           /*!< RTC configuration register,                     Address offset: 0x60 */

+} RTC_TypeDef;

+

+/**

+  * @brief Tamper and backup registers

+  */

+typedef struct

+{

+  __IO uint32_t CR1;            /*!< TAMP configuration register 1,            Address offset: 0x00 */

+  __IO uint32_t CR2;            /*!< TAMP configuration register 2,            Address offset: 0x04 */

+       uint32_t RESERVED0;      /*!< Reserved,                                 Address offset: 0x08 */

+  __IO uint32_t FLTCR;          /*!< TAMP filter control register,             Address offset: 0x0C */

+  __IO uint32_t ATCR1;          /*!< TAMP active tamper control register,      Address offset: 0x10 */

+  __IO uint32_t ATSEEDR;        /*!< TAMP active tamper seed register,         Address offset: 0x14 */

+  __IO uint32_t ATOR;           /*!< TAMP active tamper output register,       Address offset: 0x18 */

+       uint32_t RESERVED1[4];   /*!< Reserved,                                 Address offset: 0x1C -- 0x28 */

+  __IO uint32_t IER;            /*!< TAMP interrupt enable register,           Address offset: 0x2C */

+  __IO uint32_t SR;             /*!< TAMP status register,                     Address offset: 0x30 */

+  __IO uint32_t MISR;           /*!< TAMP masked interrupt status register,    Address offset: 0x34 */

+       uint32_t RESERVED2;      /*!< Reserved,                                 Address offset: 0x38 */

+  __IO uint32_t SCR;            /*!< TAMP status clear register,               Address offset: 0x3C */

+  __IO uint32_t COUNTR;         /*!< TAMP monotonic counter register,          Address offset: 0x40 */

+       uint32_t RESERVED3[3];   /*!< Reserved,                                 Address offset: 0x44 -- 0x4C */

+  __IO uint32_t CFGR;           /*!< TAMP configuration register,              Address offset: 0x50 */

+       uint32_t RESERVED4[43];  /*!< Reserved,                                 Address offset: 0x54 -- 0xFC */

+  __IO uint32_t BKP0R;          /*!< TAMP backup register 0,                   Address offset: 0x100 */

+  __IO uint32_t BKP1R;          /*!< TAMP backup register 1,                   Address offset: 0x104 */

+  __IO uint32_t BKP2R;          /*!< TAMP backup register 2,                   Address offset: 0x108 */

+  __IO uint32_t BKP3R;          /*!< TAMP backup register 3,                   Address offset: 0x10C */

+  __IO uint32_t BKP4R;          /*!< TAMP backup register 4,                   Address offset: 0x110 */

+  __IO uint32_t BKP5R;          /*!< TAMP backup register 5,                   Address offset: 0x114 */

+  __IO uint32_t BKP6R;          /*!< TAMP backup register 6,                   Address offset: 0x118 */

+  __IO uint32_t BKP7R;          /*!< TAMP backup register 7,                   Address offset: 0x11C */

+  __IO uint32_t BKP8R;          /*!< TAMP backup register 8,                   Address offset: 0x120 */

+  __IO uint32_t BKP9R;          /*!< TAMP backup register 9,                   Address offset: 0x124 */

+  __IO uint32_t BKP10R;         /*!< TAMP backup register 10,                  Address offset: 0x128 */

+  __IO uint32_t BKP11R;         /*!< TAMP backup register 11,                  Address offset: 0x12C */

+  __IO uint32_t BKP12R;         /*!< TAMP backup register 12,                  Address offset: 0x130 */

+  __IO uint32_t BKP13R;         /*!< TAMP backup register 13,                  Address offset: 0x134 */

+  __IO uint32_t BKP14R;         /*!< TAMP backup register 14,                  Address offset: 0x138 */

+  __IO uint32_t BKP15R;         /*!< TAMP backup register 15,                  Address offset: 0x13C */

+  __IO uint32_t BKP16R;         /*!< TAMP backup register 16,                  Address offset: 0x140 */

+  __IO uint32_t BKP17R;         /*!< TAMP backup register 17,                  Address offset: 0x144 */

+  __IO uint32_t BKP18R;         /*!< TAMP backup register 18,                  Address offset: 0x148 */

+  __IO uint32_t BKP19R;         /*!< TAMP backup register 19,                  Address offset: 0x14C */

+  __IO uint32_t BKP20R;         /*!< TAMP backup register 20,                  Address offset: 0x150 */

+  __IO uint32_t BKP21R;         /*!< TAMP backup register 21,                  Address offset: 0x154 */

+  __IO uint32_t BKP22R;         /*!< TAMP backup register 22,                  Address offset: 0x158 */

+  __IO uint32_t BKP23R;         /*!< TAMP backup register 23,                  Address offset: 0x15C */

+  __IO uint32_t BKP24R;         /*!< TAMP backup register 24,                  Address offset: 0x160 */

+  __IO uint32_t BKP25R;         /*!< TAMP backup register 25,                  Address offset: 0x164 */

+  __IO uint32_t BKP26R;         /*!< TAMP backup register 26,                  Address offset: 0x168 */

+  __IO uint32_t BKP27R;         /*!< TAMP backup register 27,                  Address offset: 0x16C */

+  __IO uint32_t BKP28R;         /*!< TAMP backup register 28,                  Address offset: 0x170 */

+  __IO uint32_t BKP29R;         /*!< TAMP backup register 29,                  Address offset: 0x174 */

+  __IO uint32_t BKP30R;         /*!< TAMP backup register 30,                  Address offset: 0x178 */

+  __IO uint32_t BKP31R;         /*!< TAMP backup register 31,                  Address offset: 0x17C */

+} TAMP_TypeDef;

+

+/**

+  * @brief Serial Audio Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t GCR;           /*!< SAI global configuration register, Address offset: 0x00 */

+  uint32_t      RESERVED0[16]; /*!< Reserved, 0x04 - 0x43                                   */

+  __IO uint32_t PDMCR;         /*!< SAI PDM control register,          Address offset: 0x44 */

+  __IO uint32_t PDMDLY;        /*!< SAI PDM delay register,            Address offset: 0x48 */

+} SAI_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */

+  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */

+  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */

+  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */

+  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */

+  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */

+  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */

+  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */

+} SAI_Block_TypeDef;

+

+/**

+  * @brief SPDIF-RX Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */

+  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */

+  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */

+  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */

+  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */

+  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */

+  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */

+  uint32_t        RESERVED2;    /*!< Reserved,  0x1A                                          */

+} SPDIFRX_TypeDef;

+

+

+/**

+  * @brief Secure digital input/output Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t POWER;          /*!< SDMMC power control register,             Address offset: 0x00  */

+  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,             Address offset: 0x04  */

+  __IO uint32_t ARG;            /*!< SDMMC argument register,                  Address offset: 0x08  */

+  __IO uint32_t CMD;            /*!< SDMMC command register,                   Address offset: 0x0C  */

+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register,          Address offset: 0x10  */

+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                Address offset: 0x14  */

+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                Address offset: 0x18  */

+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                Address offset: 0x1C  */

+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                Address offset: 0x20  */

+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                Address offset: 0x24  */

+  __IO uint32_t DLEN;           /*!< SDMMC data length register,               Address offset: 0x28  */

+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,              Address offset: 0x2C  */

+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,              Address offset: 0x30  */

+  __I uint32_t  STA;            /*!< SDMMC status register,                    Address offset: 0x34  */

+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,           Address offset: 0x38  */

+  __IO uint32_t MASK;           /*!< SDMMC mask register,                      Address offset: 0x3C  */

+  __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,     Address offset: 0x40  */

+  uint32_t      RESERVED0[3];   /*!< Reserved, 0x44 - 0x4C - 0x4C                                    */

+  __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,               Address offset: 0x50  */

+  __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,           Address offset: 0x54  */

+  __IO uint32_t IDMABASE0;      /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58  */

+  __IO uint32_t IDMABASE1;      /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C  */

+  uint32_t      RESERVED1[8];   /*!< Reserved, 0x60-0x7C                                             */

+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,                 Address offset: 0x80  */

+  uint32_t      RESERVED2[222]; /*!< Reserved, 0x84-0x3F8                                            */

+  __IO uint32_t IPVR;           /*!< SDMMC data FIFO register,                 Address offset: 0x3FC */

+} SDMMC_TypeDef;

+

+

+/**

+  * @brief Delay Block DLYB

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;          /*!< DELAY BLOCK control register,  Address offset: 0x00 */

+  __IO uint32_t CFGR;        /*!< DELAY BLOCK configuration register,  Address offset: 0x04 */

+} DLYB_TypeDef;

+

+/**

+  * @brief HW Semaphore HSEM

+  */

+

+typedef struct

+{

+  __IO uint32_t R[32];      /*!< 2-step write lock and read back registers,     Address offset: 00h-7Ch  */

+  __IO uint32_t RLR[32];    /*!< 1-step read lock registers,                    Address offset: 80h-FCh  */

+  __IO uint32_t C1IER;      /*!< HSEM Interrupt enable register ,             Address offset: 100h     */

+  __IO uint32_t C1ICR;      /*!< HSEM Interrupt clear register ,              Address offset: 104h     */

+  __IO uint32_t C1ISR;      /*!< HSEM Interrupt Status register ,             Address offset: 108h     */

+  __IO uint32_t C1MISR;     /*!< HSEM Interrupt Masked Status register ,      Address offset: 10Ch     */

+  uint32_t  Reserved[12];   /* Reserved                                       Address offset: 110h-13Ch  */

+  __IO uint32_t CR;         /*!< HSEM Semaphore clear register ,                Address offset: 140h      */

+  __IO uint32_t KEYR;       /*!< HSEM Semaphore clear key register ,            Address offset: 144h      */

+

+} HSEM_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t IER;        /*!< HSEM interrupt enable register ,                Address offset:   0h     */

+  __IO uint32_t ICR;        /*!< HSEM interrupt clear register ,                 Address offset:   4h     */

+  __IO uint32_t ISR;        /*!< HSEM interrupt status register ,                Address offset:   8h     */

+  __IO uint32_t MISR;       /*!< HSEM masked interrupt status register ,         Address offset:   Ch     */

+} HSEM_Common_TypeDef;

+

+/**

+  * @brief Serial Peripheral Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */

+  __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */

+  __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */

+  __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */

+  __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */

+  __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */

+  __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */

+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */

+  __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */

+  uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */

+  __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */

+  uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */

+  __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */

+  __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */

+  __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */

+  __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */

+  __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */

+

+} SPI_TypeDef;

+

+/**

+  * @brief DTS

+  */

+typedef struct

+{

+  __IO uint32_t CFGR1;         /*!< DTS configuration register,                Address offset: 0x00 */

+  uint32_t RESERVED0;          /*!< Reserved,                                  Address offset: 0x04 */

+  __IO uint32_t T0VALR1;       /*!< DTS T0 Value register,                     Address offset: 0x08 */

+  uint32_t RESERVED1;          /*!< Reserved,                                  Address offset: 0x0C */

+  __IO uint32_t RAMPVALR;      /*!< DTS Ramp value register,                   Address offset: 0x10 */

+  __IO uint32_t ITR1;          /*!< DTS Interrupt threshold register,          Address offset: 0x14 */

+  uint32_t RESERVED2;          /*!< Reserved,                                  Address offset: 0x18 */

+  __IO uint32_t DR;            /*!< DTS data register,                         Address offset: 0x1C */

+  __IO uint32_t SR;            /*!< DTS status register                        Address offset: 0x20 */

+  __IO uint32_t ITENR;         /*!< DTS Interrupt enable register,             Address offset: 0x24 */

+  __IO uint32_t ICIFR;         /*!< DTS Clear Interrupt flag register,         Address offset: 0x28 */

+  __IO uint32_t OR;            /*!< DTS option register 1,                     Address offset: 0x2C */

+}

+DTS_TypeDef;

+

+/**

+  * @brief TIM

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */

+  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */

+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */

+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */

+  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */

+  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */

+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */

+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */

+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */

+  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */

+  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */

+  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */

+  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */

+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */

+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */

+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */

+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */

+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */

+  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */

+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */

+  uint32_t      RESERVED1;   /*!< Reserved, 0x50                                                 */

+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */

+  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */

+  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */

+  __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */

+  __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */

+  __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x68 */

+} TIM_TypeDef;

+

+/**

+  * @brief LPTIMIMER

+  */

+typedef struct

+{

+  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,         Address offset: 0x00 */

+  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,              Address offset: 0x04 */

+  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,             Address offset: 0x08 */

+  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                Address offset: 0x0C */

+  __IO uint32_t CR;       /*!< LPTIM Control register,                      Address offset: 0x10 */

+  __IO uint32_t CMP;      /*!< LPTIM Compare register,                      Address offset: 0x14 */

+  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                   Address offset: 0x18 */

+  __IO uint32_t CNT;      /*!< LPTIM Counter register,                      Address offset: 0x1C */

+  uint32_t  RESERVED1;    /*!< Reserved, 0x20                                                    */

+  __IO uint32_t CFGR2;    /*!< LPTIM Configuration register,                Address offset: 0x24 */

+} LPTIM_TypeDef;

+

+/**

+  * @brief Comparator

+  */

+typedef struct

+{

+  __IO uint32_t SR;        /*!< Comparator status register,                    Address offset: 0x00 */

+  __IO uint32_t ICFR;      /*!< Comparator interrupt clear flag register,       Address offset: 0x04 */

+  __IO uint32_t OR;        /*!< Comparator option register,                  Address offset: 0x08 */

+} COMPOPT_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CFGR;      /*!< Comparator configuration register  ,           Address offset: 0x00 */

+} COMP_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CFGR;       /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */

+} COMP_Common_TypeDef;

+/**

+  * @brief Universal Synchronous Asynchronous Receiver Transmitter

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */

+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */

+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */

+  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */

+  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */

+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */

+  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */

+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */

+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */

+  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */

+  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */

+  __IO uint32_t PRESC;  /*!< USART clock Prescaler register,           Address offset: 0x2C */

+} USART_TypeDef;

+

+/**

+  * @brief Single Wire Protocol Master Interface SPWMI

+  */

+typedef struct

+{

+  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */

+  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */

+    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */

+  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */

+  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */

+  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */

+  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */

+  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */

+  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */

+  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */

+} SWPMI_TypeDef;

+

+/**

+  * @brief Window WATCHDOG

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */

+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */

+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */

+} WWDG_TypeDef;

+

+

+/**

+  * @brief RAM_ECC_Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t CR;           /*!< RAMECC monitor configuration register          */

+  __IO uint32_t SR;           /*!< RAMECC monitor status register                 */

+  __IO uint32_t FAR;          /*!< RAMECC monitor failing address register        */

+  __IO uint32_t FDRL;         /*!< RAMECC monitor failing data low register       */

+  __IO uint32_t FDRH;         /*!< RAMECC monitor failing data high register      */

+  __IO uint32_t FECR;         /*!< RAMECC monitor failing ECC error code register */

+} RAMECC_MonitorTypeDef;

+

+typedef struct

+{

+  __IO uint32_t IER;          /*!< RAMECC interrupt enable register */

+} RAMECC_TypeDef;

+/**

+  * @}

+  */

+

+

+/**

+  * @brief Crypto Processor

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */

+  __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */

+  __IO uint32_t DIN;         /*!< CRYP data input register,                                Address offset: 0x08 */

+  __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */

+  __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */

+  __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */

+  __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */

+  __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */

+  __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */

+  __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */

+  __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */

+  __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */

+  __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */

+  __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */

+  __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */

+  __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */

+  __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */

+  __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */

+  __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */

+  __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */

+  __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */

+  __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */

+  __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */

+  __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */

+  __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */

+  __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */

+  __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */

+  __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */

+  __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */

+  __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */

+  __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */

+  __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */

+  __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */

+  __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */

+  __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */

+  __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */

+} CRYP_TypeDef;

+

+/**

+  * @brief HASH

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */

+  __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */

+  __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */

+  __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */

+  __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */

+  __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */

+       uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */

+  __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */

+} HASH_TypeDef;

+

+/**

+  * @brief HASH_DIGEST

+  */

+

+typedef struct

+{

+  __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */

+} HASH_DIGEST_TypeDef;

+

+

+/**

+  * @brief RNG

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */

+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */

+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */

+  uint32_t RESERVED;

+  __IO uint32_t HTCR;  /*!< RNG health test configuration register, Address offset: 0x10 */

+} RNG_TypeDef;

+

+/**

+  * @brief MDIOS

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;

+  __IO uint32_t WRFR;

+  __IO uint32_t CWRFR;

+  __IO uint32_t RDFR;

+  __IO uint32_t CRDFR;

+  __IO uint32_t SR;

+  __IO uint32_t CLRFR;

+  uint32_t RESERVED[57];

+  __IO uint32_t DINR0;

+  __IO uint32_t DINR1;

+  __IO uint32_t DINR2;

+  __IO uint32_t DINR3;

+  __IO uint32_t DINR4;

+  __IO uint32_t DINR5;

+  __IO uint32_t DINR6;

+  __IO uint32_t DINR7;

+  __IO uint32_t DINR8;

+  __IO uint32_t DINR9;

+  __IO uint32_t DINR10;

+  __IO uint32_t DINR11;

+  __IO uint32_t DINR12;

+  __IO uint32_t DINR13;

+  __IO uint32_t DINR14;

+  __IO uint32_t DINR15;

+  __IO uint32_t DINR16;

+  __IO uint32_t DINR17;

+  __IO uint32_t DINR18;

+  __IO uint32_t DINR19;

+  __IO uint32_t DINR20;

+  __IO uint32_t DINR21;

+  __IO uint32_t DINR22;

+  __IO uint32_t DINR23;

+  __IO uint32_t DINR24;

+  __IO uint32_t DINR25;

+  __IO uint32_t DINR26;

+  __IO uint32_t DINR27;

+  __IO uint32_t DINR28;

+  __IO uint32_t DINR29;

+  __IO uint32_t DINR30;

+  __IO uint32_t DINR31;

+  __IO uint32_t DOUTR0;

+  __IO uint32_t DOUTR1;

+  __IO uint32_t DOUTR2;

+  __IO uint32_t DOUTR3;

+  __IO uint32_t DOUTR4;

+  __IO uint32_t DOUTR5;

+  __IO uint32_t DOUTR6;

+  __IO uint32_t DOUTR7;

+  __IO uint32_t DOUTR8;

+  __IO uint32_t DOUTR9;

+  __IO uint32_t DOUTR10;

+  __IO uint32_t DOUTR11;

+  __IO uint32_t DOUTR12;

+  __IO uint32_t DOUTR13;

+  __IO uint32_t DOUTR14;

+  __IO uint32_t DOUTR15;

+  __IO uint32_t DOUTR16;

+  __IO uint32_t DOUTR17;

+  __IO uint32_t DOUTR18;

+  __IO uint32_t DOUTR19;

+  __IO uint32_t DOUTR20;

+  __IO uint32_t DOUTR21;

+  __IO uint32_t DOUTR22;

+  __IO uint32_t DOUTR23;

+  __IO uint32_t DOUTR24;

+  __IO uint32_t DOUTR25;

+  __IO uint32_t DOUTR26;

+  __IO uint32_t DOUTR27;

+  __IO uint32_t DOUTR28;

+  __IO uint32_t DOUTR29;

+  __IO uint32_t DOUTR30;

+  __IO uint32_t DOUTR31;

+} MDIOS_TypeDef;

+

+

+/**

+  * @brief USB_OTG_Core_Registers

+  */

+typedef struct

+{

+ __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */

+  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */

+  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */

+  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */

+  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */

+  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */

+  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */

+  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */

+  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */

+  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */

+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */

+  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */

+  uint32_t Reserved30[2];             /*!< Reserved                                     030h */

+  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */

+  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */

+  __IO uint32_t GSNPSID;              /* USB_OTG core ID                                040h*/

+  __IO uint32_t GHWCFG1;              /* User HW config1                                044h*/

+  __IO uint32_t GHWCFG2;              /* User HW config2                                048h*/

+  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */

+  uint32_t  Reserved6;                /*!< Reserved                                     050h */

+  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */

+  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */

+  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */

+   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */

+    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */

+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */

+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */

+} USB_OTG_GlobalTypeDef;

+

+

+/**

+  * @brief USB_OTG_device_Registers

+  */

+typedef struct

+{

+  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */

+  __IO uint32_t DCTL;            /*!< dev Control Register         804h */

+  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */

+  uint32_t Reserved0C;           /*!< Reserved                     80Ch */

+  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */

+  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */

+  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */

+  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */

+  uint32_t  Reserved20;          /*!< Reserved                     820h */

+  uint32_t Reserved9;            /*!< Reserved                     824h */

+  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */

+  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */

+  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */

+  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */

+  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */

+  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */

+  uint32_t Reserved40;           /*!< dedicated EP mask            840h */

+  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */

+  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */

+  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */

+} USB_OTG_DeviceTypeDef;

+

+

+/**

+  * @brief USB_OTG_IN_Endpoint-Specific_Register

+  */

+typedef struct

+{

+  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */

+  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */

+  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */

+  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */

+  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */

+  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */

+  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */

+  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */

+} USB_OTG_INEndpointTypeDef;

+

+

+/**

+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */

+  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */

+  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */

+  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */

+  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */

+  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */

+  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */

+} USB_OTG_OUTEndpointTypeDef;

+

+

+/**

+  * @brief USB_OTG_Host_Mode_Register_Structures

+  */

+typedef struct

+{

+  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */

+  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */

+  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */

+  uint32_t Reserved40C;           /*!< Reserved                             40Ch */

+  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */

+  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */

+  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */

+} USB_OTG_HostTypeDef;

+

+/**

+  * @brief USB_OTG_Host_Channel_Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */

+  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */

+  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */

+  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */

+  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */

+  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */

+  uint32_t Reserved[2];           /*!< Reserved                                      */

+} USB_OTG_HostChannelTypeDef;

+/**

+  * @}

+  */

+

+/**

+  * @brief OCTO Serial Peripheral Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;          /*!< OCTOSPI Control register,                           Address offset: 0x000 */

+  uint32_t RESERVED;         /*!< Reserved,                                           Address offset: 0x004 */

+  __IO uint32_t DCR1;        /*!< OCTOSPI Device Configuration register 1,            Address offset: 0x008 */

+  __IO uint32_t DCR2;        /*!< OCTOSPI Device Configuration register 2,            Address offset: 0x00C */

+  __IO uint32_t DCR3;        /*!< OCTOSPI Device Configuration register 3,            Address offset: 0x010 */

+  __IO uint32_t DCR4;        /*!< OCTOSPI Device Configuration register 4,            Address offset: 0x014 */

+  uint32_t RESERVED1[2];     /*!< Reserved,                                           Address offset: 0x018-0x01C */

+  __IO uint32_t SR;          /*!< OCTOSPI Status register,                            Address offset: 0x020 */

+  __IO uint32_t FCR;         /*!< OCTOSPI Flag Clear register,                        Address offset: 0x024 */

+  uint32_t RESERVED2[6];     /*!< Reserved,                                           Address offset: 0x028-0x03C */

+  __IO uint32_t DLR;         /*!< OCTOSPI Data Length register,                       Address offset: 0x040 */

+  uint32_t RESERVED3;        /*!< Reserved,                                           Address offset: 0x044 */

+  __IO uint32_t AR;          /*!< OCTOSPI Address register,                           Address offset: 0x048 */

+  uint32_t RESERVED4;        /*!< Reserved,                                           Address offset: 0x04C */

+  __IO uint32_t DR;          /*!< OCTOSPI Data register,                              Address offset: 0x050 */

+  uint32_t RESERVED5[11];    /*!< Reserved,                                           Address offset: 0x054-0x07C */

+  __IO uint32_t PSMKR;       /*!< OCTOSPI Polling Status Mask register,               Address offset: 0x080 */

+  uint32_t RESERVED6;        /*!< Reserved,                                           Address offset: 0x084 */

+  __IO uint32_t PSMAR;       /*!< OCTOSPI Polling Status Match register,              Address offset: 0x088 */

+  uint32_t RESERVED7;        /*!< Reserved,                                           Address offset: 0x08C */

+  __IO uint32_t PIR;         /*!< OCTOSPI Polling Interval register,                  Address offset: 0x090 */

+  uint32_t RESERVED8[27];    /*!< Reserved,                                           Address offset: 0x094-0x0FC */

+  __IO uint32_t CCR;         /*!< OCTOSPI Communication Configuration register,       Address offset: 0x100 */

+  uint32_t RESERVED9;        /*!< Reserved,                                           Address offset: 0x104 */

+  __IO uint32_t TCR;         /*!< OCTOSPI Timing Configuration register,              Address offset: 0x108 */

+  uint32_t RESERVED10;       /*!< Reserved,                                           Address offset: 0x10C */

+  __IO uint32_t IR;          /*!< OCTOSPI Instruction register,                       Address offset: 0x110 */

+  uint32_t RESERVED11[3];    /*!< Reserved,                                           Address offset: 0x114-0x11C */

+  __IO uint32_t ABR;         /*!< OCTOSPI Alternate Bytes register,                   Address offset: 0x120 */

+  uint32_t RESERVED12[3];    /*!< Reserved,                                           Address offset: 0x124-0x12C */

+  __IO uint32_t LPTR;        /*!< OCTOSPI Low Power Timeout register,                 Address offset: 0x130 */

+  uint32_t RESERVED13[3];    /*!< Reserved,                                           Address offset: 0x134-0x13C */

+  __IO uint32_t WPCCR;       /*!< OCTOSPI Wrap Communication Configuration register,  Address offset: 0x140 */

+  uint32_t RESERVED14;       /*!< Reserved,                                           Address offset: 0x144 */

+  __IO uint32_t WPTCR;       /*!< OCTOSPI Wrap Timing Configuration register,         Address offset: 0x148 */

+  uint32_t RESERVED15;       /*!< Reserved,                                           Address offset: 0x14C */

+  __IO uint32_t WPIR;        /*!< OCTOSPI Wrap Instruction register,                  Address offset: 0x150 */

+  uint32_t RESERVED16[3];    /*!< Reserved,                                           Address offset: 0x154-0x15C */

+  __IO uint32_t WPABR;       /*!< OCTOSPI Wrap Alternate Bytes register,              Address offset: 0x160 */

+  uint32_t RESERVED17[7];    /*!< Reserved,                                           Address offset: 0x164-0x17C */

+  __IO uint32_t WCCR;        /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */

+  uint32_t RESERVED18;       /*!< Reserved,                                           Address offset: 0x184 */

+  __IO uint32_t WTCR;        /*!< OCTOSPI Write Timing Configuration register,        Address offset: 0x188 */

+  uint32_t RESERVED19;       /*!< Reserved,                                           Address offset: 0x18C */

+  __IO uint32_t WIR;         /*!< OCTOSPI Write Instruction register,                 Address offset: 0x190 */

+  uint32_t RESERVED20[3];    /*!< Reserved,                                           Address offset: 0x194-0x19C */

+  __IO uint32_t WABR;        /*!< OCTOSPI Write Alternate Bytes register,             Address offset: 0x1A0 */

+  uint32_t RESERVED21[23];   /*!< Reserved,                                           Address offset: 0x1A4-0x1FC */

+  __IO uint32_t HLCR;        /*!< OCTOSPI Hyperbus Latency Configuration register,    Address offset: 0x200 */

+  uint32_t RESERVED22[122];  /*!< Reserved,                                           Address offset: 0x204-0x3EC */

+  __IO uint32_t HWCFGR;      /*!< OCTOSPI HW Configuration register,                  Address offset: 0x3F0 */

+  __IO uint32_t VER;         /*!< OCTOSPI Version register,                           Address offset: 0x3F4 */

+  __IO uint32_t ID;          /*!< OCTOSPI Identification register,                    Address offset: 0x3F8 */

+  __IO uint32_t MID;         /*!< OCTOPSI HW Magic ID register,                       Address offset: 0x3FC */

+} OCTOSPI_TypeDef;

+

+/**

+  * @}

+  */

+/**

+  * @brief OCTO Serial Peripheral Interface IO Manager

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;          /*!< OCTOSPI IO Manager Control register,                 Address offset: 0x00 */

+  __IO uint32_t PCR[3];      /*!< OCTOSPI IO Manager Port[1:3] Configuration register, Address offset: 0x04-0x20 */

+} OCTOSPIM_TypeDef;

+

+/**

+  * @}

+  */

+

+/**

+  * @brief OTFD register

+  */

+typedef struct

+{

+  __IO uint32_t REG_CONFIGR;

+  __IO uint32_t REG_START_ADDR;

+  __IO uint32_t REG_END_ADDR;

+  __IO uint32_t REG_NONCER0;

+  __IO uint32_t REG_NONCER1;

+  __IO uint32_t REG_KEYR0;

+  __IO uint32_t REG_KEYR1;

+  __IO uint32_t REG_KEYR2;

+  __IO uint32_t REG_KEYR3;

+} OTFDEC_Region_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CR;

+  uint32_t RESERVED1[191];

+  __IO uint32_t ISR;

+  __IO uint32_t ICR;

+  __IO uint32_t IER;

+  uint32_t RESERVED2[56];

+  __IO uint32_t HWCFGR2;

+  __IO uint32_t HWCFGR1;

+  __IO uint32_t VERR;

+  __IO uint32_t IPIDR;

+  __IO uint32_t SIDR;

+} OTFDEC_TypeDef;

+/**

+  * @}

+  */

+

+/** @addtogroup Peripheral_memory_map

+  * @{

+  */

+#define CD_ITCMRAM_BASE           (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM  */

+#define CD_DTCMRAM_BASE           (0x20000000UL) /*!< Base address of : 128KB (2x64KB) system data RAM accessible over DTCM                   */

+#define CD_AXIFLASH_BASE          (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI                */

+

+#define CD_AXISRAM1_BASE          (0x24000000UL) /*!< Base address of : (up to 256KB) system data RAM1 accessible over over AXI                */

+#define CD_AXISRAM2_BASE          (0x24040000UL) /*!< Base address of : (up to 384KB) system data RAM2 accessible over over AXI                */

+#define CD_AXISRAM3_BASE          (0x240A0000UL) /*!< Base address of : (up to 384KB) system data RAM3 accessible over over AXI                */

+#define CD_AHBSRAM1_BASE          (0x30000000UL) /*!< Base address of : (up to 64KB) system data RAM1 accessible over over AXI->AHB Bridge     */

+#define CD_AHBSRAM2_BASE          (0x30010000UL) /*!< Base address of : (up to 64KB) system data RAM2 accessible over over AXI->AHB Bridge     */

+

+#define SRD_BKPSRAM_BASE           (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge                                */

+#define SRD_SRAM_BASE              (0x38000000UL) /*!< Base address of : Backup SRAM(32 KB) over AXI->AHB Bridge                               */

+

+#define OCTOSPI1_BASE             (0x90000000UL) /*!< Base address of : OCTOSPI1 memories  accessible over AXI                                 */

+#define OCTOSPI2_BASE             (0x70000000UL) /*!< Base address of : OCTOSPI2 memories  accessible over AXI                                 */

+

+#define FLASH_BANK1_BASE          (0x08000000UL) /*!< Base address of : (up to 128 KB) Flash Bank1 accessible over AXI                         */

+#define FLASH_BANK2_BASE          (0x08100000UL) /*!< For legacy only , Flash bank 2 not available on STM32H7B0xx value line                   */

+#define FLASH_END                 (0x0801FFFFUL) /*!< FLASH end address                                                                        */

+

+/* Legacy define */

+#define FLASH_BASE                FLASH_BANK1_BASE

+#define D1_AXISRAM_BASE           CD_AXISRAM1_BASE

+

+#define FLASH_OTP_BASE            (0x08FFF000UL) /*!< Base address of : (up to 1KB) embedded FLASH Bank1 OTP Area                           */

+#define FLASH_OTP_END             (0x08FFF3FFUL) /*!< End address of : (up to 1KB) embedded FLASH Bank1 OTP Area                            */

+

+

+/*!< Device electronic signature memory map */

+#define UID_BASE                  (0x08FFF800UL)            /*!< Unique device ID register base address */

+#define FLASHSIZE_BASE            (0x08FFF80CUL)            /*!< FLASH Size register base address */

+#define PACKAGE_BASE              (0x08FFF80EUL)            /*!< Package Data register base address */

+

+#define PERIPH_BASE               (0x40000000UL) /*!< Base address of : AHB/ABP Peripherals                                                    */

+/*!< Peripheral memory map */

+#define CD_APB1PERIPH_BASE        PERIPH_BASE                   /*!<  D2_APB1PERIPH_BASE        PERIPH_BASE                                    */

+#define CD_APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)   /*!<  D2_APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)                    */

+#define CD_AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)   /*!<  D2_AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)                    */

+#define CD_AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)   /*!<  D2_AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)                    */

+

+#define CD_APB3PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)   /*!<  D1_APB1PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)                    */

+#define CD_AHB3PERIPH_BASE       (PERIPH_BASE + 0x12000000UL)   /*!<  D1_AHB1PERIPH_BASE       (PERIPH_BASE + 0x12000000UL)                    */

+

+#define SRD_APB4PERIPH_BASE      (PERIPH_BASE + 0x18000000UL)   /*!<  D3_APB1PERIPH_BASE       (PERIPH_BASE + 0x18000000UL)                    */

+#define SRD_AHB4PERIPH_BASE      (PERIPH_BASE + 0x18020000UL)   /*!<  D3_AHB1PERIPH_BASE       (PERIPH_BASE + 0x18020000UL)                    */

+

+/*!< Legacy Peripheral memory map */

+#define APB1PERIPH_BASE        PERIPH_BASE

+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)

+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)

+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)

+

+/*!< CD_AHB3PERIPH peripherals */

+#define MDMA_BASE             (CD_AHB3PERIPH_BASE + 0x0000UL)

+#define DMA2D_BASE            (CD_AHB3PERIPH_BASE + 0x1000UL)

+#define FLASH_R_BASE          (CD_AHB3PERIPH_BASE + 0x2000UL)

+#define JPGDEC_BASE           (CD_AHB3PERIPH_BASE + 0x3000UL)

+#define FMC_R_BASE            (CD_AHB3PERIPH_BASE + 0x4000UL)

+#define OCTOSPI1_R_BASE       (CD_AHB3PERIPH_BASE + 0x5000UL)

+#define DLYB_OCTOSPI1_BASE    (CD_AHB3PERIPH_BASE + 0x6000UL)

+#define SDMMC1_BASE           (CD_AHB3PERIPH_BASE + 0x7000UL)

+#define DLYB_SDMMC1_BASE      (CD_AHB3PERIPH_BASE + 0x8000UL)

+#define RAMECC_BASE           (CD_AHB3PERIPH_BASE + 0x9000UL)

+#define OCTOSPI2_R_BASE       (CD_AHB3PERIPH_BASE + 0xA000UL)

+#define DLYB_OCTOSPI2_BASE    (CD_AHB3PERIPH_BASE + 0xB000UL)

+#define OCTOSPIM_BASE         (CD_AHB3PERIPH_BASE + 0xB400UL)

+

+/*!< CD_AHB1PERIPH peripherals */

+

+#define DMA1_BASE               (CD_AHB1PERIPH_BASE + 0x0000UL)

+#define DMA2_BASE               (CD_AHB1PERIPH_BASE + 0x0400UL)

+#define DMAMUX1_BASE            (CD_AHB1PERIPH_BASE + 0x0800UL)

+#define ADC1_BASE               (CD_AHB1PERIPH_BASE + 0x2000UL)

+#define ADC2_BASE               (CD_AHB1PERIPH_BASE + 0x2100UL)

+#define ADC12_COMMON_BASE       (CD_AHB1PERIPH_BASE + 0x2300UL)

+#define CRC_BASE                (CD_AHB1PERIPH_BASE + 0x3000UL)

+

+/*!< USB registers base address */

+#define USB1_OTG_HS_PERIPH_BASE              (0x40040000UL)

+#define USB_OTG_GLOBAL_BASE                  (0x000UL)

+#define USB_OTG_DEVICE_BASE                  (0x800UL)

+#define USB_OTG_IN_ENDPOINT_BASE             (0x900UL)

+#define USB_OTG_OUT_ENDPOINT_BASE            (0xB00UL)

+#define USB_OTG_EP_REG_SIZE                  (0x20UL)

+#define USB_OTG_HOST_BASE                    (0x400UL)

+#define USB_OTG_HOST_PORT_BASE               (0x440UL)

+#define USB_OTG_HOST_CHANNEL_BASE            (0x500UL)

+#define USB_OTG_HOST_CHANNEL_SIZE            (0x20UL)

+#define USB_OTG_PCGCCTL_BASE                 (0xE00UL)

+#define USB_OTG_FIFO_BASE                    (0x1000UL)

+#define USB_OTG_FIFO_SIZE                    (0x1000UL)

+

+/*!< CD_AHB2PERIPH peripherals */

+

+#define DCMI_BASE              (CD_AHB2PERIPH_BASE + 0x0000UL)

+#define PSSI_BASE              (CD_AHB2PERIPH_BASE + 0x0400UL)

+#define HSEM_BASE              (CD_AHB2PERIPH_BASE + 0x0800UL)

+#define CRYP_BASE              (CD_AHB2PERIPH_BASE + 0x1000UL)

+#define HASH_BASE              (CD_AHB2PERIPH_BASE + 0x1400UL)

+#define HASH_DIGEST_BASE       (CD_AHB2PERIPH_BASE + 0x1710UL)

+#define RNG_BASE               (CD_AHB2PERIPH_BASE + 0x1800UL)

+#define SDMMC2_BASE            (CD_AHB2PERIPH_BASE + 0x2400UL)

+#define DLYB_SDMMC2_BASE       (CD_AHB2PERIPH_BASE + 0x2800UL)

+#define BDMA1_BASE             (CD_AHB2PERIPH_BASE + 0x2C00UL)

+

+/*!< SRD_AHB4PERIPH peripherals */

+#define GPIOA_BASE            (SRD_AHB4PERIPH_BASE + 0x0000UL)

+#define GPIOB_BASE            (SRD_AHB4PERIPH_BASE + 0x0400UL)

+#define GPIOC_BASE            (SRD_AHB4PERIPH_BASE + 0x0800UL)

+#define GPIOD_BASE            (SRD_AHB4PERIPH_BASE + 0x0C00UL)

+#define GPIOE_BASE            (SRD_AHB4PERIPH_BASE + 0x1000UL)

+#define GPIOF_BASE            (SRD_AHB4PERIPH_BASE + 0x1400UL)

+#define GPIOG_BASE            (SRD_AHB4PERIPH_BASE + 0x1800UL)

+#define GPIOH_BASE            (SRD_AHB4PERIPH_BASE + 0x1C00UL)

+#define GPIOI_BASE            (SRD_AHB4PERIPH_BASE + 0x2000UL)

+#define GPIOJ_BASE            (SRD_AHB4PERIPH_BASE + 0x2400UL)

+#define GPIOK_BASE            (SRD_AHB4PERIPH_BASE + 0x2800UL)

+#define RCC_BASE              (SRD_AHB4PERIPH_BASE + 0x4400UL)

+#define PWR_BASE              (SRD_AHB4PERIPH_BASE + 0x4800UL)

+#define BDMA2_BASE            (SRD_AHB4PERIPH_BASE + 0x5400UL)

+#define DMAMUX2_BASE          (SRD_AHB4PERIPH_BASE + 0x5800UL)

+

+/*!< CD_APB3PERIPH peripherals */

+#define LTDC_BASE             (CD_APB3PERIPH_BASE + 0x1000UL)

+#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84UL)

+#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104UL)

+#define WWDG1_BASE            (CD_APB3PERIPH_BASE + 0x3000UL)

+

+/*!< CD_APB1PERIPH peripherals */

+#define TIM2_BASE             (CD_APB1PERIPH_BASE + 0x0000UL)

+#define TIM3_BASE             (CD_APB1PERIPH_BASE + 0x0400UL)

+#define TIM4_BASE             (CD_APB1PERIPH_BASE + 0x0800UL)

+#define TIM5_BASE             (CD_APB1PERIPH_BASE + 0x0C00UL)

+#define TIM6_BASE             (CD_APB1PERIPH_BASE + 0x1000UL)

+#define TIM7_BASE             (CD_APB1PERIPH_BASE + 0x1400UL)

+#define TIM12_BASE            (CD_APB1PERIPH_BASE + 0x1800UL)

+#define TIM13_BASE            (CD_APB1PERIPH_BASE + 0x1C00UL)

+#define TIM14_BASE            (CD_APB1PERIPH_BASE + 0x2000UL)

+#define LPTIM1_BASE           (CD_APB1PERIPH_BASE + 0x2400UL)

+

+#define SPI2_BASE             (CD_APB1PERIPH_BASE + 0x3800UL)

+#define SPI3_BASE             (CD_APB1PERIPH_BASE + 0x3C00UL)

+#define SPDIFRX_BASE          (CD_APB1PERIPH_BASE + 0x4000UL)

+#define USART2_BASE           (CD_APB1PERIPH_BASE + 0x4400UL)

+#define USART3_BASE           (CD_APB1PERIPH_BASE + 0x4800UL)

+#define UART4_BASE            (CD_APB1PERIPH_BASE + 0x4C00UL)

+#define UART5_BASE            (CD_APB1PERIPH_BASE + 0x5000UL)

+#define I2C1_BASE             (CD_APB1PERIPH_BASE + 0x5400UL)

+#define I2C2_BASE             (CD_APB1PERIPH_BASE + 0x5800UL)

+#define I2C3_BASE             (CD_APB1PERIPH_BASE + 0x5C00UL)

+#define CEC_BASE              (CD_APB1PERIPH_BASE + 0x6C00UL)

+#define DAC1_BASE             (CD_APB1PERIPH_BASE + 0x7400UL)

+#define UART7_BASE            (CD_APB1PERIPH_BASE + 0x7800UL)

+#define UART8_BASE            (CD_APB1PERIPH_BASE + 0x7C00UL)

+#define CRS_BASE              (CD_APB1PERIPH_BASE + 0x8400UL)

+#define SWPMI1_BASE           (CD_APB1PERIPH_BASE + 0x8800UL)

+#define OPAMP_BASE            (CD_APB1PERIPH_BASE + 0x9000UL)

+#define OPAMP1_BASE           (CD_APB1PERIPH_BASE + 0x9000UL)

+#define OPAMP2_BASE           (CD_APB1PERIPH_BASE + 0x9010UL)

+#define MDIOS_BASE            (CD_APB1PERIPH_BASE + 0x9400UL)

+#define FDCAN1_BASE           (CD_APB1PERIPH_BASE + 0xA000UL)

+#define FDCAN2_BASE           (CD_APB1PERIPH_BASE + 0xA400UL)

+#define FDCAN_CCU_BASE        (CD_APB1PERIPH_BASE + 0xA800UL)

+#define SRAMCAN_BASE          (CD_APB1PERIPH_BASE + 0xAC00UL)

+

+/*!< CD_APB2PERIPH peripherals */

+

+#define TIM1_BASE             (CD_APB2PERIPH_BASE + 0x0000UL)

+#define TIM8_BASE             (CD_APB2PERIPH_BASE + 0x0400UL)

+#define USART1_BASE           (CD_APB2PERIPH_BASE + 0x1000UL)

+#define USART6_BASE           (CD_APB2PERIPH_BASE + 0x1400UL)

+#define UART9_BASE            (CD_APB2PERIPH_BASE + 0x1800UL)

+#define USART10_BASE          (CD_APB2PERIPH_BASE + 0x1C00UL)

+#define SPI1_BASE             (CD_APB2PERIPH_BASE + 0x3000UL)

+#define SPI4_BASE             (CD_APB2PERIPH_BASE + 0x3400UL)

+#define TIM15_BASE            (CD_APB2PERIPH_BASE + 0x4000UL)

+#define TIM16_BASE            (CD_APB2PERIPH_BASE + 0x4400UL)

+#define TIM17_BASE            (CD_APB2PERIPH_BASE + 0x4800UL)

+#define SPI5_BASE             (CD_APB2PERIPH_BASE + 0x5000UL)

+#define SAI1_BASE             (CD_APB2PERIPH_BASE + 0x5800UL)

+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)

+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)

+#define SAI2_BASE             (CD_APB2PERIPH_BASE + 0x5C00UL)

+#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004UL)

+#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024UL)

+#define DFSDM1_BASE           (CD_APB2PERIPH_BASE + 0x7800UL)

+#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00UL)

+#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20UL)

+#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40UL)

+#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60UL)

+#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80UL)

+#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0UL)

+#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0UL)

+#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0UL)

+#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)

+#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)

+#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)

+#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)

+#define DFSDM1_Filter4_BASE   (DFSDM1_BASE + 0x300UL)

+#define DFSDM1_Filter5_BASE   (DFSDM1_BASE + 0x380UL)

+#define DFSDM1_Filter6_BASE   (DFSDM1_BASE + 0x400UL)

+#define DFSDM1_Filter7_BASE   (DFSDM1_BASE + 0x480UL)

+/*!< SRD_APB4PERIPH peripherals */

+#define EXTI_BASE             (SRD_APB4PERIPH_BASE + 0x0000UL)

+#define EXTI_D1_BASE          (EXTI_BASE + 0x0080UL)

+#define SYSCFG_BASE           (SRD_APB4PERIPH_BASE + 0x0400UL)

+#define LPUART1_BASE          (SRD_APB4PERIPH_BASE + 0x0C00UL)

+#define SPI6_BASE             (SRD_APB4PERIPH_BASE + 0x1400UL)

+#define I2C4_BASE             (SRD_APB4PERIPH_BASE + 0x1C00UL)

+#define LPTIM2_BASE           (SRD_APB4PERIPH_BASE + 0x2400UL)

+#define LPTIM3_BASE           (SRD_APB4PERIPH_BASE + 0x2800UL)

+#define DAC2_BASE             (SRD_APB4PERIPH_BASE + 0x3400UL)

+#define COMP12_BASE           (SRD_APB4PERIPH_BASE + 0x3800UL)

+#define COMP1_BASE            (COMP12_BASE + 0x0CUL)

+#define COMP2_BASE            (COMP12_BASE + 0x10UL)

+#define VREFBUF_BASE          (SRD_APB4PERIPH_BASE + 0x3C00UL)

+#define RTC_BASE              (SRD_APB4PERIPH_BASE + 0x4000UL)

+#define TAMP_BASE             (SRD_APB4PERIPH_BASE + 0x4400UL)

+#define IWDG1_BASE            (SRD_APB4PERIPH_BASE + 0x4800UL)

+

+#define DTS_BASE              (SRD_APB4PERIPH_BASE + 0x6800UL)

+

+#define DFSDM2_BASE           (SRD_APB4PERIPH_BASE + 0x6C00UL)

+#define DFSDM2_Channel0_BASE  (DFSDM2_BASE + 0x00UL)

+#define DFSDM2_Channel1_BASE  (DFSDM2_BASE + 0x20UL)

+#define DFSDM2_FLT0_BASE      (DFSDM2_BASE + 0x100UL)

+

+/*!< CD_AHB3PERIPH peripherals */

+

+#define OTFDEC1_BASE          (CD_AHB3PERIPH_BASE + 0xB800UL)

+#define OTFDEC1_REGION1_BASE  (OTFDEC1_BASE + 0x20UL)

+#define OTFDEC1_REGION2_BASE  (OTFDEC1_BASE + 0x50UL)

+#define OTFDEC1_REGION3_BASE  (OTFDEC1_BASE + 0x80UL)

+#define OTFDEC1_REGION4_BASE  (OTFDEC1_BASE + 0xB0UL)

+#define OTFDEC2_BASE          (CD_AHB3PERIPH_BASE + 0xBC00UL)

+#define OTFDEC2_REGION1_BASE  (OTFDEC2_BASE + 0x20UL)

+#define OTFDEC2_REGION2_BASE  (OTFDEC2_BASE + 0x50UL)

+#define OTFDEC2_REGION3_BASE  (OTFDEC2_BASE + 0x80UL)

+#define OTFDEC2_REGION4_BASE  (OTFDEC2_BASE + 0xB0UL)

+#define GFXMMU_BASE           (CD_AHB3PERIPH_BASE + 0xC000UL)

+

+#define BDMA1_Channel0_BASE    (BDMA1_BASE + 0x0008UL)

+#define BDMA1_Channel1_BASE    (BDMA1_BASE + 0x001CUL)

+#define BDMA1_Channel2_BASE    (BDMA1_BASE + 0x0030UL)

+#define BDMA1_Channel3_BASE    (BDMA1_BASE + 0x0044UL)

+#define BDMA1_Channel4_BASE    (BDMA1_BASE + 0x0058UL)

+#define BDMA1_Channel5_BASE    (BDMA1_BASE + 0x006CUL)

+#define BDMA1_Channel6_BASE    (BDMA1_BASE + 0x0080UL)

+#define BDMA1_Channel7_BASE    (BDMA1_BASE + 0x0094UL)

+

+#define BDMA2_Channel0_BASE    (BDMA2_BASE + 0x0008UL)

+#define BDMA2_Channel1_BASE    (BDMA2_BASE + 0x001CUL)

+#define BDMA2_Channel2_BASE    (BDMA2_BASE + 0x0030UL)

+#define BDMA2_Channel3_BASE    (BDMA2_BASE + 0x0044UL)

+#define BDMA2_Channel4_BASE    (BDMA2_BASE + 0x0058UL)

+#define BDMA2_Channel5_BASE    (BDMA2_BASE + 0x006CUL)

+#define BDMA2_Channel6_BASE    (BDMA2_BASE + 0x0080UL)

+#define BDMA2_Channel7_BASE    (BDMA2_BASE + 0x0094UL)

+

+

+#define DMAMUX2_Channel0_BASE    (DMAMUX2_BASE)

+#define DMAMUX2_Channel1_BASE    (DMAMUX2_BASE + 0x0004UL)

+#define DMAMUX2_Channel2_BASE    (DMAMUX2_BASE + 0x0008UL)

+#define DMAMUX2_Channel3_BASE    (DMAMUX2_BASE + 0x000CUL)

+#define DMAMUX2_Channel4_BASE    (DMAMUX2_BASE + 0x0010UL)

+#define DMAMUX2_Channel5_BASE    (DMAMUX2_BASE + 0x0014UL)

+#define DMAMUX2_Channel6_BASE    (DMAMUX2_BASE + 0x0018UL)

+#define DMAMUX2_Channel7_BASE    (DMAMUX2_BASE + 0x001CUL)

+

+#define DMAMUX2_RequestGenerator0_BASE  (DMAMUX2_BASE + 0x0100UL)

+#define DMAMUX2_RequestGenerator1_BASE  (DMAMUX2_BASE + 0x0104UL)

+#define DMAMUX2_RequestGenerator2_BASE  (DMAMUX2_BASE + 0x0108UL)

+#define DMAMUX2_RequestGenerator3_BASE  (DMAMUX2_BASE + 0x010CUL)

+#define DMAMUX2_RequestGenerator4_BASE  (DMAMUX2_BASE + 0x0110UL)

+#define DMAMUX2_RequestGenerator5_BASE  (DMAMUX2_BASE + 0x0114UL)

+#define DMAMUX2_RequestGenerator6_BASE  (DMAMUX2_BASE + 0x0118UL)

+#define DMAMUX2_RequestGenerator7_BASE  (DMAMUX2_BASE + 0x011CUL)

+

+#define DMAMUX2_ChannelStatus_BASE      (DMAMUX2_BASE + 0x0080UL)

+#define DMAMUX2_RequestGenStatus_BASE   (DMAMUX2_BASE + 0x0140UL)

+

+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)

+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)

+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)

+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)

+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)

+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)

+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)

+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)

+

+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)

+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)

+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)

+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)

+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)

+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)

+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)

+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)

+

+

+#define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)

+#define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)

+#define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)

+#define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)

+#define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)

+#define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)

+#define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0018UL)

+#define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x001CUL)

+#define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0020UL)

+#define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x0024UL)

+#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)

+#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)

+#define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)

+#define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)

+#define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)

+#define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)

+

+#define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)

+#define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)

+#define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)

+#define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)

+#define DMAMUX1_RequestGenerator4_BASE  (DMAMUX1_BASE + 0x0110UL)

+#define DMAMUX1_RequestGenerator5_BASE  (DMAMUX1_BASE + 0x0114UL)

+#define DMAMUX1_RequestGenerator6_BASE  (DMAMUX1_BASE + 0x0118UL)

+#define DMAMUX1_RequestGenerator7_BASE  (DMAMUX1_BASE + 0x011CUL)

+

+#define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)

+#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)

+

+/*!< FMC Banks registers base  address */

+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)

+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)

+#define FMC_Bank2_R_BASE      (FMC_R_BASE + 0x0060UL)

+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)

+#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)

+

+/* Debug MCU registers base address */

+#define DBGMCU_BASE           (0x5C001000UL)

+

+#define MDMA_Channel0_BASE    (MDMA_BASE + 0x00000040UL)

+#define MDMA_Channel1_BASE    (MDMA_BASE + 0x00000080UL)

+#define MDMA_Channel2_BASE    (MDMA_BASE + 0x000000C0UL)

+#define MDMA_Channel3_BASE    (MDMA_BASE + 0x00000100UL)

+#define MDMA_Channel4_BASE    (MDMA_BASE + 0x00000140UL)

+#define MDMA_Channel5_BASE    (MDMA_BASE + 0x00000180UL)

+#define MDMA_Channel6_BASE    (MDMA_BASE + 0x000001C0UL)

+#define MDMA_Channel7_BASE    (MDMA_BASE + 0x00000200UL)

+#define MDMA_Channel8_BASE    (MDMA_BASE + 0x00000240UL)

+#define MDMA_Channel9_BASE    (MDMA_BASE + 0x00000280UL)

+#define MDMA_Channel10_BASE   (MDMA_BASE + 0x000002C0UL)

+#define MDMA_Channel11_BASE   (MDMA_BASE + 0x00000300UL)

+#define MDMA_Channel12_BASE   (MDMA_BASE + 0x00000340UL)

+#define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)

+#define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)

+#define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)

+#define MDMA_Channel16_BASE   (MDMA_BASE + 0x00000440UL)

+

+/* GFXMMU virtual buffers base address */

+#define GFXMMU_VIRTUAL_BUFFERS_BASE  (0x25000000UL)

+#define GFXMMU_VIRTUAL_BUFFER0_BASE  (GFXMMU_VIRTUAL_BUFFERS_BASE)

+#define GFXMMU_VIRTUAL_BUFFER1_BASE  (GFXMMU_VIRTUAL_BUFFERS_BASE + 0x400000UL)

+#define GFXMMU_VIRTUAL_BUFFER2_BASE  (GFXMMU_VIRTUAL_BUFFERS_BASE + 0x800000UL)

+#define GFXMMU_VIRTUAL_BUFFER3_BASE  (GFXMMU_VIRTUAL_BUFFERS_BASE + 0xC00000UL)

+

+#define RAMECC_Monitor1_BASE (RAMECC_BASE + 0x20UL)

+#define RAMECC_Monitor2_BASE (RAMECC_BASE + 0x40UL)

+#define RAMECC_Monitor3_BASE (RAMECC_BASE + 0x60UL)

+

+/**

+  * @}

+  */

+

+/** @addtogroup Peripheral_declaration

+  * @{

+  */

+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)

+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)

+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)

+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)

+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)

+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)

+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)

+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)

+#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)

+#define RTC                 ((RTC_TypeDef *) RTC_BASE)

+#define TAMP                ((TAMP_TypeDef *) TAMP_BASE)

+#define WWDG1               ((WWDG_TypeDef *) WWDG1_BASE)

+

+

+#define IWDG1               ((IWDG_TypeDef *) IWDG1_BASE)

+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)

+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)

+#define SPI4                ((SPI_TypeDef *) SPI4_BASE)

+#define SPI5                ((SPI_TypeDef *) SPI5_BASE)

+#define SPI6                ((SPI_TypeDef *) SPI6_BASE)

+#define USART2              ((USART_TypeDef *) USART2_BASE)

+#define USART3              ((USART_TypeDef *) USART3_BASE)

+#define USART6              ((USART_TypeDef *) USART6_BASE)

+#define USART10             ((USART_TypeDef *) USART10_BASE)

+#define UART7               ((USART_TypeDef *) UART7_BASE)

+#define UART8               ((USART_TypeDef *) UART8_BASE)

+#define UART9               ((USART_TypeDef *) UART9_BASE)

+#define CRS                 ((CRS_TypeDef *) CRS_BASE)

+#define UART4               ((USART_TypeDef *) UART4_BASE)

+#define UART5               ((USART_TypeDef *) UART5_BASE)

+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)

+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)

+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)

+#define I2C4                ((I2C_TypeDef *) I2C4_BASE)

+#define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

+#define FDCAN2              ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

+#define FDCAN_CCU           ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

+#define CEC                 ((CEC_TypeDef *) CEC_BASE)

+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)

+#define PWR                 ((PWR_TypeDef *) PWR_BASE)

+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)

+#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)

+#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)

+#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)

+#define LPTIM3              ((LPTIM_TypeDef *) LPTIM3_BASE)

+#define DTS                 ((DTS_TypeDef *) DTS_BASE)

+

+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)

+#define COMP12              ((COMPOPT_TypeDef *) COMP12_BASE)

+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)

+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)

+#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)

+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)

+#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)

+#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)

+

+

+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)

+#define EXTI_D1             ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)

+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)

+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)

+#define USART1              ((USART_TypeDef *) USART1_BASE)

+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)

+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)

+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)

+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)

+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)

+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

+#define SAI2                ((SAI_TypeDef *) SAI2_BASE)

+#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)

+#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)

+

+#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

+#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

+#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

+#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

+#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

+#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

+#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

+#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

+#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

+#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

+#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

+#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

+#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

+#define DFSDM1_Filter4      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter4_BASE)

+#define DFSDM1_Filter5      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter5_BASE)

+#define DFSDM1_Filter6      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter6_BASE)

+#define DFSDM1_Filter7      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter7_BASE)

+#define DFSDM2_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel0_BASE)

+#define DFSDM2_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel1_BASE)

+#define DFSDM2_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM2_FLT0_BASE)

+#define DMA2D               ((DMA2D_TypeDef *) DMA2D_BASE)

+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)

+#define PSSI                ((PSSI_TypeDef *) PSSI_BASE)

+#define RCC                 ((RCC_TypeDef *) RCC_BASE)

+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)

+#define CRC                 ((CRC_TypeDef *) CRC_BASE)

+

+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)

+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)

+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)

+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)

+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)

+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)

+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)

+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)

+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)

+#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)

+#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)

+

+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)

+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)

+#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

+

+#define CRYP                ((CRYP_TypeDef *) CRYP_BASE)

+#define HASH                ((HASH_TypeDef *) HASH_BASE)

+#define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)

+#define RNG                 ((RNG_TypeDef *) RNG_BASE)

+#define SDMMC2              ((SDMMC_TypeDef *) SDMMC2_BASE)

+#define DLYB_SDMMC2         ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

+

+#define BDMA1                ((BDMA_TypeDef *) BDMA1_BASE)

+#define BDMA1_Channel0       ((BDMA_Channel_TypeDef *) BDMA1_Channel0_BASE)

+#define BDMA1_Channel1       ((BDMA_Channel_TypeDef *) BDMA1_Channel1_BASE)

+#define BDMA1_Channel2       ((BDMA_Channel_TypeDef *) BDMA1_Channel2_BASE)

+#define BDMA1_Channel3       ((BDMA_Channel_TypeDef *) BDMA1_Channel3_BASE)

+#define BDMA1_Channel4       ((BDMA_Channel_TypeDef *) BDMA1_Channel4_BASE)

+#define BDMA1_Channel5       ((BDMA_Channel_TypeDef *) BDMA1_Channel5_BASE)

+#define BDMA1_Channel6       ((BDMA_Channel_TypeDef *) BDMA1_Channel6_BASE)

+#define BDMA1_Channel7       ((BDMA_Channel_TypeDef *) BDMA1_Channel7_BASE)

+

+#define BDMA2                ((BDMA_TypeDef *) BDMA2_BASE)

+#define BDMA2_Channel0       ((BDMA_Channel_TypeDef *) BDMA2_Channel0_BASE)

+#define BDMA2_Channel1       ((BDMA_Channel_TypeDef *) BDMA2_Channel1_BASE)

+#define BDMA2_Channel2       ((BDMA_Channel_TypeDef *) BDMA2_Channel2_BASE)

+#define BDMA2_Channel3       ((BDMA_Channel_TypeDef *) BDMA2_Channel3_BASE)

+#define BDMA2_Channel4       ((BDMA_Channel_TypeDef *) BDMA2_Channel4_BASE)

+#define BDMA2_Channel5       ((BDMA_Channel_TypeDef *) BDMA2_Channel5_BASE)

+#define BDMA2_Channel6       ((BDMA_Channel_TypeDef *) BDMA2_Channel6_BASE)

+#define BDMA2_Channel7       ((BDMA_Channel_TypeDef *) BDMA2_Channel7_BASE)

+

+#define RAMECC               ((RAMECC_TypeDef *)RAMECC_BASE)

+#define RAMECC_Monitor1      ((RAMECC_MonitorTypeDef *)RAMECC_Monitor1_BASE)

+#define RAMECC_Monitor2      ((RAMECC_MonitorTypeDef *)RAMECC_Monitor2_BASE)

+#define RAMECC_Monitor3      ((RAMECC_MonitorTypeDef *)RAMECC_Monitor3_BASE)

+

+#define DMAMUX2                ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

+#define DMAMUX2_Channel0       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

+#define DMAMUX2_Channel1       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

+#define DMAMUX2_Channel2       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

+#define DMAMUX2_Channel3       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

+#define DMAMUX2_Channel4       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

+#define DMAMUX2_Channel5       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

+#define DMAMUX2_Channel6       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

+#define DMAMUX2_Channel7       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

+

+

+#define DMAMUX2_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

+#define DMAMUX2_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

+#define DMAMUX2_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

+#define DMAMUX2_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

+#define DMAMUX2_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

+#define DMAMUX2_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

+#define DMAMUX2_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

+#define DMAMUX2_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

+

+#define DMAMUX2_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

+#define DMAMUX2_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

+

+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)

+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

+

+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)

+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

+

+

+#define DMAMUX1              ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

+#define DMAMUX1_Channel0     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

+#define DMAMUX1_Channel1     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

+#define DMAMUX1_Channel2     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

+#define DMAMUX1_Channel3     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

+#define DMAMUX1_Channel4     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

+#define DMAMUX1_Channel5     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

+#define DMAMUX1_Channel6     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

+#define DMAMUX1_Channel7     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

+#define DMAMUX1_Channel8     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

+#define DMAMUX1_Channel9     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

+#define DMAMUX1_Channel10    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

+#define DMAMUX1_Channel11    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

+#define DMAMUX1_Channel12    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

+#define DMAMUX1_Channel13    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

+#define DMAMUX1_Channel14    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

+#define DMAMUX1_Channel15    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

+

+#define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

+#define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

+#define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

+#define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

+#define DMAMUX1_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

+#define DMAMUX1_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

+#define DMAMUX1_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

+#define DMAMUX1_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

+

+#define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *)    DMAMUX1_ChannelStatus_BASE)

+#define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

+

+

+#define FMC_Bank1_R           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

+#define FMC_Bank1E_R          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

+#define FMC_Bank2_R           ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

+#define FMC_Bank3_R           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

+#define FMC_Bank5_6_R         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

+

+#define DAC2                ((DAC_TypeDef *) DAC2_BASE)

+#define OCTOSPI1            ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)

+#define DLYB_OCTOSPI1       ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE)

+#define OCTOSPI2            ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)

+#define DLYB_OCTOSPI2       ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE)

+#define OCTOSPIM            ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)

+

+#define OTFDEC1               ((OTFDEC_TypeDef *) OTFDEC1_BASE)

+#define OTFDEC1_REGION1       ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE)

+#define OTFDEC1_REGION2       ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE)

+#define OTFDEC1_REGION3       ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE)

+#define OTFDEC1_REGION4       ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE)

+

+#define OTFDEC2               ((OTFDEC_TypeDef *) OTFDEC2_BASE)

+#define OTFDEC2_REGION1       ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE)

+#define OTFDEC2_REGION2       ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE)

+#define OTFDEC2_REGION3       ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE)

+#define OTFDEC2_REGION4       ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE)

+#define GFXMMU              ((GFXMMU_TypeDef *) GFXMMU_BASE)

+

+#define SDMMC1                ((SDMMC_TypeDef *) SDMMC1_BASE)

+#define DLYB_SDMMC1           ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

+

+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)

+

+#define JPEG                ((JPEG_TypeDef *) JPGDEC_BASE)

+#define HSEM                ((HSEM_TypeDef *) HSEM_BASE)

+#define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

+

+#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)

+#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

+#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

+

+#define MDIOS               ((MDIOS_TypeDef *) MDIOS_BASE)

+

+#define MDMA                ((MDMA_TypeDef *)MDMA_BASE)

+#define MDMA_Channel0       ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

+#define MDMA_Channel1       ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

+#define MDMA_Channel2       ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

+#define MDMA_Channel3       ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

+#define MDMA_Channel4       ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

+#define MDMA_Channel5       ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

+#define MDMA_Channel6       ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

+#define MDMA_Channel7       ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

+#define MDMA_Channel8       ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

+#define MDMA_Channel9       ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

+#define MDMA_Channel10      ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

+#define MDMA_Channel11      ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

+#define MDMA_Channel12      ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

+#define MDMA_Channel13      ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

+#define MDMA_Channel14      ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

+#define MDMA_Channel15      ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

+

+

+#define USB1_OTG_HS         ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

+

+/* Legacy defines */

+#define USB_OTG_HS                   USB1_OTG_HS

+#define USB_OTG_HS_PERIPH_BASE       USB1_OTG_HS_PERIPH_BASE

+

+/**

+  * @}

+  */

+

+/** @addtogroup Exported_constants

+  * @{

+  */

+

+  /** @addtogroup Peripheral_Registers_Bits_Definition

+  * @{

+  */

+

+/******************************************************************************/

+/*                         Peripheral Registers_Bits_Definition               */

+/******************************************************************************/

+

+/******************************************************************************/

+/*                                                                            */

+/*                        Analog to Digital Converter                         */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  ADC VERSION  ********************************/

+#define ADC_VER_V5_3

+/********************  Bit definition for ADC_ISR register  ********************/

+#define ADC_ISR_ADRDY_Pos                 (0U)

+#define ADC_ISR_ADRDY_Msk                 (0x1UL << ADC_ISR_ADRDY_Pos)         /*!< 0x00000001 */

+#define ADC_ISR_ADRDY                     ADC_ISR_ADRDY_Msk                    /*!< ADC Ready (ADRDY) flag  */

+#define ADC_ISR_EOSMP_Pos                 (1U)

+#define ADC_ISR_EOSMP_Msk                 (0x1UL << ADC_ISR_EOSMP_Pos)         /*!< 0x00000002 */

+#define ADC_ISR_EOSMP                     ADC_ISR_EOSMP_Msk                    /*!< ADC End of Sampling flag */

+#define ADC_ISR_EOC_Pos                   (2U)

+#define ADC_ISR_EOC_Msk                   (0x1UL << ADC_ISR_EOC_Pos)           /*!< 0x00000004 */

+#define ADC_ISR_EOC                       ADC_ISR_EOC_Msk                      /*!< ADC End of Regular Conversion flag */

+#define ADC_ISR_EOS_Pos                   (3U)

+#define ADC_ISR_EOS_Msk                   (0x1UL << ADC_ISR_EOS_Pos)           /*!< 0x00000008 */

+#define ADC_ISR_EOS                       ADC_ISR_EOS_Msk                      /*!< ADC End of Regular sequence of Conversions flag */

+#define ADC_ISR_OVR_Pos                   (4U)

+#define ADC_ISR_OVR_Msk                   (0x1UL << ADC_ISR_OVR_Pos)           /*!< 0x00000010 */

+#define ADC_ISR_OVR                       ADC_ISR_OVR_Msk                      /*!< ADC overrun flag */

+#define ADC_ISR_JEOC_Pos                  (5U)

+#define ADC_ISR_JEOC_Msk                  (0x1UL << ADC_ISR_JEOC_Pos)          /*!< 0x00000020 */

+#define ADC_ISR_JEOC                      ADC_ISR_JEOC_Msk                     /*!< ADC End of Injected Conversion flag */

+#define ADC_ISR_JEOS_Pos                  (6U)

+#define ADC_ISR_JEOS_Msk                  (0x1UL << ADC_ISR_JEOS_Pos)          /*!< 0x00000040 */

+#define ADC_ISR_JEOS                      ADC_ISR_JEOS_Msk                     /*!< ADC End of Injected sequence of Conversions flag */

+#define ADC_ISR_AWD1_Pos                  (7U)

+#define ADC_ISR_AWD1_Msk                  (0x1UL << ADC_ISR_AWD1_Pos)          /*!< 0x00000080 */

+#define ADC_ISR_AWD1                      ADC_ISR_AWD1_Msk                     /*!< ADC Analog watchdog 1 flag */

+#define ADC_ISR_AWD2_Pos                  (8U)

+#define ADC_ISR_AWD2_Msk                  (0x1UL << ADC_ISR_AWD2_Pos)          /*!< 0x00000100 */

+#define ADC_ISR_AWD2                      ADC_ISR_AWD2_Msk                     /*!< ADC Analog watchdog 2 flag */

+#define ADC_ISR_AWD3_Pos                  (9U)

+#define ADC_ISR_AWD3_Msk                  (0x1UL << ADC_ISR_AWD3_Pos)          /*!< 0x00000200 */

+#define ADC_ISR_AWD3                      ADC_ISR_AWD3_Msk                     /*!< ADC Analog watchdog 3 flag */

+#define ADC_ISR_JQOVF_Pos                 (10U)

+#define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */

+#define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */

+

+/********************  Bit definition for ADC_IER register  ********************/

+#define ADC_IER_ADRDYIE_Pos               (0U)

+#define ADC_IER_ADRDYIE_Msk               (0x1UL << ADC_IER_ADRDYIE_Pos)       /*!< 0x00000001 */

+#define ADC_IER_ADRDYIE                   ADC_IER_ADRDYIE_Msk                  /*!< ADC Ready (ADRDY) interrupt source */

+#define ADC_IER_EOSMPIE_Pos               (1U)

+#define ADC_IER_EOSMPIE_Msk               (0x1UL << ADC_IER_EOSMPIE_Pos)       /*!< 0x00000002 */

+#define ADC_IER_EOSMPIE                   ADC_IER_EOSMPIE_Msk                  /*!< ADC End of Sampling interrupt source */

+#define ADC_IER_EOCIE_Pos                 (2U)

+#define ADC_IER_EOCIE_Msk                 (0x1UL << ADC_IER_EOCIE_Pos)         /*!< 0x00000004 */

+#define ADC_IER_EOCIE                     ADC_IER_EOCIE_Msk                    /*!< ADC End of Regular Conversion interrupt source */

+#define ADC_IER_EOSIE_Pos                 (3U)

+#define ADC_IER_EOSIE_Msk                 (0x1UL << ADC_IER_EOSIE_Pos)         /*!< 0x00000008 */

+#define ADC_IER_EOSIE                     ADC_IER_EOSIE_Msk                    /*!< ADC End of Regular sequence of Conversions interrupt source */

+#define ADC_IER_OVRIE_Pos                 (4U)

+#define ADC_IER_OVRIE_Msk                 (0x1UL << ADC_IER_OVRIE_Pos)         /*!< 0x00000010 */

+#define ADC_IER_OVRIE                     ADC_IER_OVRIE_Msk                    /*!< ADC overrun interrupt source */

+#define ADC_IER_JEOCIE_Pos                (5U)

+#define ADC_IER_JEOCIE_Msk                (0x1UL << ADC_IER_JEOCIE_Pos)        /*!< 0x00000020 */

+#define ADC_IER_JEOCIE                    ADC_IER_JEOCIE_Msk                   /*!< ADC End of Injected Conversion interrupt source */

+#define ADC_IER_JEOSIE_Pos                (6U)

+#define ADC_IER_JEOSIE_Msk                (0x1UL << ADC_IER_JEOSIE_Pos)        /*!< 0x00000040 */

+#define ADC_IER_JEOSIE                    ADC_IER_JEOSIE_Msk                   /*!< ADC End of Injected sequence of Conversions interrupt source */

+#define ADC_IER_AWD1IE_Pos                (7U)

+#define ADC_IER_AWD1IE_Msk                (0x1UL << ADC_IER_AWD1IE_Pos)        /*!< 0x00000080 */

+#define ADC_IER_AWD1IE                    ADC_IER_AWD1IE_Msk                   /*!< ADC Analog watchdog 1 interrupt source */

+#define ADC_IER_AWD2IE_Pos                (8U)

+#define ADC_IER_AWD2IE_Msk                (0x1UL << ADC_IER_AWD2IE_Pos)        /*!< 0x00000100 */

+#define ADC_IER_AWD2IE                    ADC_IER_AWD2IE_Msk                   /*!< ADC Analog watchdog 2 interrupt source */

+#define ADC_IER_AWD3IE_Pos                (9U)

+#define ADC_IER_AWD3IE_Msk                (0x1UL << ADC_IER_AWD3IE_Pos)        /*!< 0x00000200 */

+#define ADC_IER_AWD3IE                    ADC_IER_AWD3IE_Msk                   /*!< ADC Analog watchdog 3 interrupt source */

+#define ADC_IER_JQOVFIE_Pos               (10U)

+#define ADC_IER_JQOVFIE_Msk               (0x1UL << ADC_IER_JQOVFIE_Pos)       /*!< 0x00000400 */

+#define ADC_IER_JQOVFIE                   ADC_IER_JQOVFIE_Msk                  /*!< ADC Injected Context Queue Overflow interrupt source */

+

+/********************  Bit definition for ADC_CR register  ********************/

+#define ADC_CR_ADEN_Pos                   (0U)

+#define ADC_CR_ADEN_Msk                   (0x1UL << ADC_CR_ADEN_Pos)           /*!< 0x00000001 */

+#define ADC_CR_ADEN                       ADC_CR_ADEN_Msk                      /*!< ADC Enable control */

+#define ADC_CR_ADDIS_Pos                  (1U)

+#define ADC_CR_ADDIS_Msk                  (0x1UL << ADC_CR_ADDIS_Pos)          /*!< 0x00000002 */

+#define ADC_CR_ADDIS                      ADC_CR_ADDIS_Msk                     /*!< ADC Disable command */

+#define ADC_CR_ADSTART_Pos                (2U)

+#define ADC_CR_ADSTART_Msk                (0x1UL << ADC_CR_ADSTART_Pos)        /*!< 0x00000004 */

+#define ADC_CR_ADSTART                    ADC_CR_ADSTART_Msk                   /*!< ADC Start of Regular conversion */

+#define ADC_CR_JADSTART_Pos               (3U)

+#define ADC_CR_JADSTART_Msk               (0x1UL << ADC_CR_JADSTART_Pos)       /*!< 0x00000008 */

+#define ADC_CR_JADSTART                   ADC_CR_JADSTART_Msk                  /*!< ADC Start of injected conversion */

+#define ADC_CR_ADSTP_Pos                  (4U)

+#define ADC_CR_ADSTP_Msk                  (0x1UL << ADC_CR_ADSTP_Pos)          /*!< 0x00000010 */

+#define ADC_CR_ADSTP                      ADC_CR_ADSTP_Msk                     /*!< ADC Stop of Regular conversion */

+#define ADC_CR_JADSTP_Pos                 (5U)

+#define ADC_CR_JADSTP_Msk                 (0x1UL << ADC_CR_JADSTP_Pos)         /*!< 0x00000020 */

+#define ADC_CR_JADSTP                     ADC_CR_JADSTP_Msk                    /*!< ADC Stop of injected conversion */

+#define ADC_CR_BOOST_Pos                  (8U)

+#define ADC_CR_BOOST_Msk                  (0x3UL << ADC_CR_BOOST_Pos)          /*!< 0x00000300 */

+#define ADC_CR_BOOST                      ADC_CR_BOOST_Msk                     /*!< ADC Boost Mode configuration */

+#define ADC_CR_BOOST_0                    (0x1UL << ADC_CR_BOOST_Pos)           /*!< 0x00000100 */

+#define ADC_CR_BOOST_1                    (0x2UL << ADC_CR_BOOST_Pos)           /*!< 0x00000200 */

+#define ADC_CR_ADCALLIN_Pos               (16U)

+#define ADC_CR_ADCALLIN_Msk               (0x1UL << ADC_CR_ADCALLIN_Pos)       /*!< 0x00010000 */

+#define ADC_CR_ADCALLIN                   ADC_CR_ADCALLIN_Msk                  /*!< ADC Linearity calibration */

+#define ADC_CR_LINCALRDYW1_Pos            (22U)

+#define ADC_CR_LINCALRDYW1_Msk            (0x1UL << ADC_CR_LINCALRDYW1_Pos)    /*!< 0x00400000 */

+#define ADC_CR_LINCALRDYW1                ADC_CR_LINCALRDYW1_Msk               /*!< ADC Linearity calibration ready Word 1 */

+#define ADC_CR_LINCALRDYW2_Pos            (23U)

+#define ADC_CR_LINCALRDYW2_Msk            (0x1UL << ADC_CR_LINCALRDYW2_Pos)    /*!< 0x00800000 */

+#define ADC_CR_LINCALRDYW2                ADC_CR_LINCALRDYW2_Msk               /*!< ADC Linearity calibration ready Word 2 */

+#define ADC_CR_LINCALRDYW3_Pos            (24U)

+#define ADC_CR_LINCALRDYW3_Msk            (0x1UL << ADC_CR_LINCALRDYW3_Pos)    /*!< 0x01000000 */

+#define ADC_CR_LINCALRDYW3                ADC_CR_LINCALRDYW3_Msk               /*!< ADC Linearity calibration ready Word 3 */

+#define ADC_CR_LINCALRDYW4_Pos            (25U)

+#define ADC_CR_LINCALRDYW4_Msk            (0x1UL << ADC_CR_LINCALRDYW4_Pos)    /*!< 0x02000000 */

+#define ADC_CR_LINCALRDYW4                ADC_CR_LINCALRDYW4_Msk               /*!< ADC Linearity calibration ready Word 4 */

+#define ADC_CR_LINCALRDYW5_Pos            (26U)

+#define ADC_CR_LINCALRDYW5_Msk            (0x1UL << ADC_CR_LINCALRDYW5_Pos)    /*!< 0x04000000 */

+#define ADC_CR_LINCALRDYW5                ADC_CR_LINCALRDYW5_Msk               /*!< ADC Linearity calibration ready Word 5 */

+#define ADC_CR_LINCALRDYW6_Pos            (27U)

+#define ADC_CR_LINCALRDYW6_Msk            (0x1UL << ADC_CR_LINCALRDYW6_Pos)    /*!< 0x08000000 */

+#define ADC_CR_LINCALRDYW6                ADC_CR_LINCALRDYW6_Msk               /*!< ADC Linearity calibration ready Word 6 */

+#define ADC_CR_ADVREGEN_Pos               (28U)

+#define ADC_CR_ADVREGEN_Msk               (0x1UL << ADC_CR_ADVREGEN_Pos)       /*!< 0x10000000 */

+#define ADC_CR_ADVREGEN                   ADC_CR_ADVREGEN_Msk                  /*!< ADC Voltage regulator Enable */

+#define ADC_CR_DEEPPWD_Pos                (29U)

+#define ADC_CR_DEEPPWD_Msk                (0x1UL << ADC_CR_DEEPPWD_Pos)        /*!< 0x20000000 */

+#define ADC_CR_DEEPPWD                    ADC_CR_DEEPPWD_Msk                   /*!< ADC Deep power down Enable */

+#define ADC_CR_ADCALDIF_Pos               (30U)

+#define ADC_CR_ADCALDIF_Msk               (0x1UL << ADC_CR_ADCALDIF_Pos)       /*!< 0x40000000 */

+#define ADC_CR_ADCALDIF                   ADC_CR_ADCALDIF_Msk                  /*!< ADC Differential Mode for calibration */

+#define ADC_CR_ADCAL_Pos                  (31U)

+#define ADC_CR_ADCAL_Msk                  (0x1UL << ADC_CR_ADCAL_Pos)          /*!< 0x80000000 */

+#define ADC_CR_ADCAL                      ADC_CR_ADCAL_Msk                     /*!< ADC Calibration */

+

+/********************  Bit definition for ADC_CFGR register  ********************/

+#define ADC_CFGR_DMNGT_Pos                (0U)

+#define ADC_CFGR_DMNGT_Msk                (0x3UL << ADC_CFGR_DMNGT_Pos)        /*!< 0x00000003 */

+#define ADC_CFGR_DMNGT                    ADC_CFGR_DMNGT_Msk                   /*!< ADC Data Management configuration */

+#define ADC_CFGR_DMNGT_0                  (0x1UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000001 */

+#define ADC_CFGR_DMNGT_1                  (0x2UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000002 */

+

+#define ADC_CFGR_RES_Pos                  (2U)

+#define ADC_CFGR_RES_Msk                  (0x7UL << ADC_CFGR_RES_Pos)          /*!< 0x0000001C */

+#define ADC_CFGR_RES                      ADC_CFGR_RES_Msk                     /*!< ADC Data resolution */

+#define ADC_CFGR_RES_0                    (0x1UL << ADC_CFGR_RES_Pos)           /*!< 0x00000004 */

+#define ADC_CFGR_RES_1                    (0x2UL << ADC_CFGR_RES_Pos)           /*!< 0x00000008 */

+#define ADC_CFGR_RES_2                    (0x4UL << ADC_CFGR_RES_Pos)           /*!< 0x00000010 */

+

+#define ADC_CFGR_EXTSEL_Pos               (5U)

+#define ADC_CFGR_EXTSEL_Msk               (0x1FUL << ADC_CFGR_EXTSEL_Pos)      /*!< 0x000003E0 */

+#define ADC_CFGR_EXTSEL                   ADC_CFGR_EXTSEL_Msk                  /*!< ADC External trigger selection for regular group */

+#define ADC_CFGR_EXTSEL_0                 (0x01UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000020 */

+#define ADC_CFGR_EXTSEL_1                 (0x02UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000040 */

+#define ADC_CFGR_EXTSEL_2                 (0x04UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000080 */

+#define ADC_CFGR_EXTSEL_3                 (0x08UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000100 */

+#define ADC_CFGR_EXTSEL_4                 (0x10UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000200 */

+

+#define ADC_CFGR_EXTEN_Pos                (10U)

+#define ADC_CFGR_EXTEN_Msk                (0x3UL << ADC_CFGR_EXTEN_Pos)        /*!< 0x00000C00 */

+#define ADC_CFGR_EXTEN                    ADC_CFGR_EXTEN_Msk                   /*!< ADC External trigger enable and polarity selection for regular channels */

+#define ADC_CFGR_EXTEN_0                  (0x1UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000400 */

+#define ADC_CFGR_EXTEN_1                  (0x2UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000800 */

+

+#define ADC_CFGR_OVRMOD_Pos               (12U)

+#define ADC_CFGR_OVRMOD_Msk               (0x1UL << ADC_CFGR_OVRMOD_Pos)       /*!< 0x00001000 */

+#define ADC_CFGR_OVRMOD                   ADC_CFGR_OVRMOD_Msk                  /*!< ADC overrun mode */

+#define ADC_CFGR_CONT_Pos                 (13U)

+#define ADC_CFGR_CONT_Msk                 (0x1UL << ADC_CFGR_CONT_Pos)         /*!< 0x00002000 */

+#define ADC_CFGR_CONT                     ADC_CFGR_CONT_Msk                    /*!< ADC Single/continuous conversion mode for regular conversion */

+#define ADC_CFGR_AUTDLY_Pos               (14U)

+#define ADC_CFGR_AUTDLY_Msk               (0x1UL << ADC_CFGR_AUTDLY_Pos)       /*!< 0x00004000 */

+#define ADC_CFGR_AUTDLY                   ADC_CFGR_AUTDLY_Msk                  /*!< ADC Delayed conversion mode */

+

+#define ADC_CFGR_DISCEN_Pos               (16U)

+#define ADC_CFGR_DISCEN_Msk               (0x1UL << ADC_CFGR_DISCEN_Pos)       /*!< 0x00010000 */

+#define ADC_CFGR_DISCEN                   ADC_CFGR_DISCEN_Msk                  /*!< ADC Discontinuous mode for regular channels */

+

+#define ADC_CFGR_DISCNUM_Pos              (17U)

+#define ADC_CFGR_DISCNUM_Msk              (0x7UL << ADC_CFGR_DISCNUM_Pos)      /*!< 0x000E0000 */

+#define ADC_CFGR_DISCNUM                  ADC_CFGR_DISCNUM_Msk                 /*!< ADC Discontinuous mode channel count */

+#define ADC_CFGR_DISCNUM_0                (0x1UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00020000 */

+#define ADC_CFGR_DISCNUM_1                (0x2UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00040000 */

+#define ADC_CFGR_DISCNUM_2                (0x4UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00080000 */

+

+#define ADC_CFGR_JDISCEN_Pos              (20U)

+#define ADC_CFGR_JDISCEN_Msk              (0x1UL << ADC_CFGR_JDISCEN_Pos)      /*!< 0x00100000 */

+#define ADC_CFGR_JDISCEN                  ADC_CFGR_JDISCEN_Msk                 /*!< ADC Discontinuous mode on injected channels */

+#define ADC_CFGR_JQM_Pos                  (21U)

+#define ADC_CFGR_JQM_Msk                  (0x1UL << ADC_CFGR_JQM_Pos)          /*!< 0x00200000 */

+#define ADC_CFGR_JQM                      ADC_CFGR_JQM_Msk                     /*!< ADC JSQR Queue mode */

+#define ADC_CFGR_AWD1SGL_Pos              (22U)

+#define ADC_CFGR_AWD1SGL_Msk              (0x1UL << ADC_CFGR_AWD1SGL_Pos)      /*!< 0x00400000 */

+#define ADC_CFGR_AWD1SGL                  ADC_CFGR_AWD1SGL_Msk                 /*!< Enable the watchdog 1 on a single channel or on all channels */

+#define ADC_CFGR_AWD1EN_Pos               (23U)

+#define ADC_CFGR_AWD1EN_Msk               (0x1UL << ADC_CFGR_AWD1EN_Pos)       /*!< 0x00800000 */

+#define ADC_CFGR_AWD1EN                   ADC_CFGR_AWD1EN_Msk                  /*!< ADC Analog watchdog 1 enable on regular Channels */

+#define ADC_CFGR_JAWD1EN_Pos              (24U)

+#define ADC_CFGR_JAWD1EN_Msk              (0x1UL << ADC_CFGR_JAWD1EN_Pos)      /*!< 0x01000000 */

+#define ADC_CFGR_JAWD1EN                  ADC_CFGR_JAWD1EN_Msk                 /*!< ADC Analog watchdog 1 enable on injected Channels */

+#define ADC_CFGR_JAUTO_Pos                (25U)

+#define ADC_CFGR_JAUTO_Msk                (0x1UL << ADC_CFGR_JAUTO_Pos)        /*!< 0x02000000 */

+#define ADC_CFGR_JAUTO                    ADC_CFGR_JAUTO_Msk                   /*!< ADC Automatic injected group conversion */

+

+#define ADC_CFGR_AWD1CH_Pos               (26U)

+#define ADC_CFGR_AWD1CH_Msk               (0x1FUL << ADC_CFGR_AWD1CH_Pos)      /*!< 0x7C000000 */

+#define ADC_CFGR_AWD1CH                   ADC_CFGR_AWD1CH_Msk                  /*!< ADC Analog watchdog 1 Channel selection */

+#define ADC_CFGR_AWD1CH_0                 (0x01UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x04000000 */

+#define ADC_CFGR_AWD1CH_1                 (0x02UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x08000000 */

+#define ADC_CFGR_AWD1CH_2                 (0x04UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x10000000 */

+#define ADC_CFGR_AWD1CH_3                 (0x08UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x20000000 */

+#define ADC_CFGR_AWD1CH_4                 (0x10UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x40000000 */

+

+#define ADC_CFGR_JQDIS_Pos                (31U)

+#define ADC_CFGR_JQDIS_Msk                (0x1UL << ADC_CFGR_JQDIS_Pos)        /*!< 0x80000000 */

+#define ADC_CFGR_JQDIS                    ADC_CFGR_JQDIS_Msk                   /*!< ADC Injected queue disable */

+

+/********************  Bit definition for ADC_CFGR2 register  ********************/

+#define ADC_CFGR2_ROVSE_Pos               (0U)

+#define ADC_CFGR2_ROVSE_Msk               (0x1UL << ADC_CFGR2_ROVSE_Pos)       /*!< 0x00000001 */

+#define ADC_CFGR2_ROVSE                   ADC_CFGR2_ROVSE_Msk                  /*!< ADC Regular group oversampler enable */

+#define ADC_CFGR2_JOVSE_Pos               (1U)

+#define ADC_CFGR2_JOVSE_Msk               (0x1UL << ADC_CFGR2_JOVSE_Pos)       /*!< 0x00000002 */

+#define ADC_CFGR2_JOVSE                   ADC_CFGR2_JOVSE_Msk                  /*!< ADC Injected group oversampler enable */

+

+#define ADC_CFGR2_OVSS_Pos                (5U)

+#define ADC_CFGR2_OVSS_Msk                (0xFUL << ADC_CFGR2_OVSS_Pos)        /*!< 0x000001E0 */

+#define ADC_CFGR2_OVSS                    ADC_CFGR2_OVSS_Msk                   /*!< ADC Regular Oversampling shift */

+#define ADC_CFGR2_OVSS_0                  (0x1UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000020 */

+#define ADC_CFGR2_OVSS_1                  (0x2UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000040 */

+#define ADC_CFGR2_OVSS_2                  (0x4UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000080 */

+#define ADC_CFGR2_OVSS_3                  (0x8UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000100 */

+

+#define ADC_CFGR2_TROVS_Pos               (9U)

+#define ADC_CFGR2_TROVS_Msk               (0x1UL << ADC_CFGR2_TROVS_Pos)       /*!< 0x00000200 */

+#define ADC_CFGR2_TROVS                   ADC_CFGR2_TROVS_Msk                  /*!< ADC Triggered regular Oversampling */

+#define ADC_CFGR2_ROVSM_Pos               (10U)

+#define ADC_CFGR2_ROVSM_Msk               (0x1UL << ADC_CFGR2_ROVSM_Pos)       /*!< 0x00000400 */

+#define ADC_CFGR2_ROVSM                   ADC_CFGR2_ROVSM_Msk                  /*!< ADC Regular oversampling mode */

+

+#define ADC_CFGR2_RSHIFT1_Pos             (11U)

+#define ADC_CFGR2_RSHIFT1_Msk             (0x1UL << ADC_CFGR2_RSHIFT1_Pos)     /*!< 0x00000800 */

+#define ADC_CFGR2_RSHIFT1                 ADC_CFGR2_RSHIFT1_Msk                /*!< ADC Right-shift data after Offset 1 correction */

+#define ADC_CFGR2_RSHIFT2_Pos             (12U)

+#define ADC_CFGR2_RSHIFT2_Msk             (0x1UL << ADC_CFGR2_RSHIFT2_Pos)     /*!< 0x00001000 */

+#define ADC_CFGR2_RSHIFT2                 ADC_CFGR2_RSHIFT2_Msk                /*!< ADC Right-shift data after Offset 2 correction */

+#define ADC_CFGR2_RSHIFT3_Pos             (13U)

+#define ADC_CFGR2_RSHIFT3_Msk             (0x1UL << ADC_CFGR2_RSHIFT3_Pos)     /*!< 0x00002000 */

+#define ADC_CFGR2_RSHIFT3                 ADC_CFGR2_RSHIFT3_Msk                /*!< ADC Right-shift data after Offset 3 correction */

+#define ADC_CFGR2_RSHIFT4_Pos             (14U)

+#define ADC_CFGR2_RSHIFT4_Msk             (0x1UL << ADC_CFGR2_RSHIFT4_Pos)     /*!< 0x00004000 */

+#define ADC_CFGR2_RSHIFT4                 ADC_CFGR2_RSHIFT4_Msk                /*!< ADC Right-shift data after Offset 4 correction */

+

+#define ADC_CFGR2_OVSR_Pos                (16U)

+#define ADC_CFGR2_OVSR_Msk                (0x3FFUL << ADC_CFGR2_OVSR_Pos)      /*!< 0x03FF0000 */

+#define ADC_CFGR2_OVSR                    ADC_CFGR2_OVSR_Msk                   /*!< ADC oversampling Ratio */

+#define ADC_CFGR2_OVSR_0                  (0x001UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00010000 */

+#define ADC_CFGR2_OVSR_1                  (0x002UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00020000 */

+#define ADC_CFGR2_OVSR_2                  (0x004UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00040000 */

+#define ADC_CFGR2_OVSR_3                  (0x008UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00080000 */

+#define ADC_CFGR2_OVSR_4                  (0x010UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00100000 */

+#define ADC_CFGR2_OVSR_5                  (0x020UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00200000 */

+#define ADC_CFGR2_OVSR_6                  (0x040UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00400000 */

+#define ADC_CFGR2_OVSR_7                  (0x080UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00800000 */

+#define ADC_CFGR2_OVSR_8                  (0x100UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x01000000 */

+#define ADC_CFGR2_OVSR_9                  (0x200UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x02000000 */

+

+#define ADC_CFGR2_LSHIFT_Pos              (28U)

+#define ADC_CFGR2_LSHIFT_Msk              (0xFUL << ADC_CFGR2_LSHIFT_Pos)      /*!< 0xF0000000 */

+#define ADC_CFGR2_LSHIFT                  ADC_CFGR2_LSHIFT_Msk                 /*!< ADC Left shift factor */

+#define ADC_CFGR2_LSHIFT_0                (0x1UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x10000000 */

+#define ADC_CFGR2_LSHIFT_1                (0x2UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x20000000 */

+#define ADC_CFGR2_LSHIFT_2                (0x4UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x40000000 */

+#define ADC_CFGR2_LSHIFT_3                (0x8UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_SMPR1 register  ********************/

+#define ADC_SMPR1_SMP0_Pos                (0U)

+#define ADC_SMPR1_SMP0_Msk                (0x7UL << ADC_SMPR1_SMP0_Pos)        /*!< 0x00000007 */

+#define ADC_SMPR1_SMP0                    ADC_SMPR1_SMP0_Msk                   /*!< ADC Channel 0 Sampling time selection  */

+#define ADC_SMPR1_SMP0_0                  (0x1UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000001 */

+#define ADC_SMPR1_SMP0_1                  (0x2UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000002 */

+#define ADC_SMPR1_SMP0_2                  (0x4UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000004 */

+

+#define ADC_SMPR1_SMP1_Pos                (3U)

+#define ADC_SMPR1_SMP1_Msk                (0x7UL << ADC_SMPR1_SMP1_Pos)        /*!< 0x00000038 */

+#define ADC_SMPR1_SMP1                    ADC_SMPR1_SMP1_Msk                   /*!< ADC Channel 1 Sampling time selection  */

+#define ADC_SMPR1_SMP1_0                  (0x1UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000008 */

+#define ADC_SMPR1_SMP1_1                  (0x2UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000010 */

+#define ADC_SMPR1_SMP1_2                  (0x4UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000020 */

+

+#define ADC_SMPR1_SMP2_Pos                (6U)

+#define ADC_SMPR1_SMP2_Msk                (0x7UL << ADC_SMPR1_SMP2_Pos)        /*!< 0x000001C0 */

+#define ADC_SMPR1_SMP2                    ADC_SMPR1_SMP2_Msk                   /*!< ADC Channel 2 Sampling time selection  */

+#define ADC_SMPR1_SMP2_0                  (0x1UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000040 */

+#define ADC_SMPR1_SMP2_1                  (0x2UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000080 */

+#define ADC_SMPR1_SMP2_2                  (0x4UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000100 */

+

+#define ADC_SMPR1_SMP3_Pos                (9U)

+#define ADC_SMPR1_SMP3_Msk                (0x7UL << ADC_SMPR1_SMP3_Pos)        /*!< 0x00000E00 */

+#define ADC_SMPR1_SMP3                    ADC_SMPR1_SMP3_Msk                   /*!< ADC Channel 3 Sampling time selection  */

+#define ADC_SMPR1_SMP3_0                  (0x1UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000200 */

+#define ADC_SMPR1_SMP3_1                  (0x2UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000400 */

+#define ADC_SMPR1_SMP3_2                  (0x4UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000800 */

+

+#define ADC_SMPR1_SMP4_Pos                (12U)

+#define ADC_SMPR1_SMP4_Msk                (0x7UL << ADC_SMPR1_SMP4_Pos)        /*!< 0x00007000 */

+#define ADC_SMPR1_SMP4                    ADC_SMPR1_SMP4_Msk                   /*!< ADC Channel 4 Sampling time selection  */

+#define ADC_SMPR1_SMP4_0                  (0x1UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00001000 */

+#define ADC_SMPR1_SMP4_1                  (0x2UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00002000 */

+#define ADC_SMPR1_SMP4_2                  (0x4UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00004000 */

+

+#define ADC_SMPR1_SMP5_Pos                (15U)

+#define ADC_SMPR1_SMP5_Msk                (0x7UL << ADC_SMPR1_SMP5_Pos)        /*!< 0x00038000 */

+#define ADC_SMPR1_SMP5                    ADC_SMPR1_SMP5_Msk                   /*!< ADC Channel 5 Sampling time selection  */

+#define ADC_SMPR1_SMP5_0                  (0x1UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00008000 */

+#define ADC_SMPR1_SMP5_1                  (0x2UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00010000 */

+#define ADC_SMPR1_SMP5_2                  (0x4UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00020000 */

+

+#define ADC_SMPR1_SMP6_Pos                (18U)

+#define ADC_SMPR1_SMP6_Msk                (0x7UL << ADC_SMPR1_SMP6_Pos)        /*!< 0x001C0000 */

+#define ADC_SMPR1_SMP6                    ADC_SMPR1_SMP6_Msk                   /*!< ADC Channel 6 Sampling time selection  */

+#define ADC_SMPR1_SMP6_0                  (0x1UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00040000 */

+#define ADC_SMPR1_SMP6_1                  (0x2UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00080000 */

+#define ADC_SMPR1_SMP6_2                  (0x4UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00100000 */

+

+#define ADC_SMPR1_SMP7_Pos                (21U)

+#define ADC_SMPR1_SMP7_Msk                (0x7UL << ADC_SMPR1_SMP7_Pos)        /*!< 0x00E00000 */

+#define ADC_SMPR1_SMP7                    ADC_SMPR1_SMP7_Msk                   /*!< ADC Channel 7 Sampling time selection  */

+#define ADC_SMPR1_SMP7_0                  (0x1UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00200000 */

+#define ADC_SMPR1_SMP7_1                  (0x2UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00400000 */

+#define ADC_SMPR1_SMP7_2                  (0x4UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00800000 */

+

+#define ADC_SMPR1_SMP8_Pos                (24U)

+#define ADC_SMPR1_SMP8_Msk                (0x7UL << ADC_SMPR1_SMP8_Pos)        /*!< 0x07000000 */

+#define ADC_SMPR1_SMP8                    ADC_SMPR1_SMP8_Msk                   /*!< ADC Channel 8 Sampling time selection  */

+#define ADC_SMPR1_SMP8_0                  (0x1UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x01000000 */

+#define ADC_SMPR1_SMP8_1                  (0x2UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x02000000 */

+#define ADC_SMPR1_SMP8_2                  (0x4UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x04000000 */

+

+#define ADC_SMPR1_SMP9_Pos                (27U)

+#define ADC_SMPR1_SMP9_Msk                (0x7UL << ADC_SMPR1_SMP9_Pos)        /*!< 0x38000000 */

+#define ADC_SMPR1_SMP9                    ADC_SMPR1_SMP9_Msk                   /*!< ADC Channel 9 Sampling time selection  */

+#define ADC_SMPR1_SMP9_0                  (0x1UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x08000000 */

+#define ADC_SMPR1_SMP9_1                  (0x2UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x10000000 */

+#define ADC_SMPR1_SMP9_2                  (0x4UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x20000000 */

+

+/********************  Bit definition for ADC_SMPR2 register  ********************/

+#define ADC_SMPR2_SMP10_Pos               (0U)

+#define ADC_SMPR2_SMP10_Msk               (0x7UL << ADC_SMPR2_SMP10_Pos)       /*!< 0x00000007 */

+#define ADC_SMPR2_SMP10                   ADC_SMPR2_SMP10_Msk                  /*!< ADC Channel 10 Sampling time selection  */

+#define ADC_SMPR2_SMP10_0                 (0x1UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000001 */

+#define ADC_SMPR2_SMP10_1                 (0x2UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000002 */

+#define ADC_SMPR2_SMP10_2                 (0x4UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000004 */

+

+#define ADC_SMPR2_SMP11_Pos               (3U)

+#define ADC_SMPR2_SMP11_Msk               (0x7UL << ADC_SMPR2_SMP11_Pos)       /*!< 0x00000038 */

+#define ADC_SMPR2_SMP11                   ADC_SMPR2_SMP11_Msk                  /*!< ADC Channel 11 Sampling time selection  */

+#define ADC_SMPR2_SMP11_0                 (0x1UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000008 */

+#define ADC_SMPR2_SMP11_1                 (0x2UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000010 */

+#define ADC_SMPR2_SMP11_2                 (0x4UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000020 */

+

+#define ADC_SMPR2_SMP12_Pos               (6U)

+#define ADC_SMPR2_SMP12_Msk               (0x7UL << ADC_SMPR2_SMP12_Pos)       /*!< 0x000001C0 */

+#define ADC_SMPR2_SMP12                   ADC_SMPR2_SMP12_Msk                  /*!< ADC Channel 12 Sampling time selection  */

+#define ADC_SMPR2_SMP12_0                 (0x1UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000040 */

+#define ADC_SMPR2_SMP12_1                 (0x2UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000080 */

+#define ADC_SMPR2_SMP12_2                 (0x4UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000100 */

+

+#define ADC_SMPR2_SMP13_Pos               (9U)

+#define ADC_SMPR2_SMP13_Msk               (0x7UL << ADC_SMPR2_SMP13_Pos)       /*!< 0x00000E00 */

+#define ADC_SMPR2_SMP13                   ADC_SMPR2_SMP13_Msk                  /*!< ADC Channel 13 Sampling time selection  */

+#define ADC_SMPR2_SMP13_0                 (0x1UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000200 */

+#define ADC_SMPR2_SMP13_1                 (0x2UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000400 */

+#define ADC_SMPR2_SMP13_2                 (0x4UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000800 */

+

+#define ADC_SMPR2_SMP14_Pos               (12U)

+#define ADC_SMPR2_SMP14_Msk               (0x7UL << ADC_SMPR2_SMP14_Pos)       /*!< 0x00007000 */

+#define ADC_SMPR2_SMP14                   ADC_SMPR2_SMP14_Msk                  /*!< ADC Channel 14 Sampling time selection  */

+#define ADC_SMPR2_SMP14_0                 (0x1UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00001000 */

+#define ADC_SMPR2_SMP14_1                 (0x2UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00002000 */

+#define ADC_SMPR2_SMP14_2                 (0x4UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00004000 */

+

+#define ADC_SMPR2_SMP15_Pos               (15U)

+#define ADC_SMPR2_SMP15_Msk               (0x7UL << ADC_SMPR2_SMP15_Pos)       /*!< 0x00038000 */

+#define ADC_SMPR2_SMP15                   ADC_SMPR2_SMP15_Msk                  /*!< ADC Channel 15 Sampling time selection  */

+#define ADC_SMPR2_SMP15_0                 (0x1UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00008000 */

+#define ADC_SMPR2_SMP15_1                 (0x2UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00010000 */

+#define ADC_SMPR2_SMP15_2                 (0x4UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00020000 */

+

+#define ADC_SMPR2_SMP16_Pos               (18U)

+#define ADC_SMPR2_SMP16_Msk               (0x7UL << ADC_SMPR2_SMP16_Pos)       /*!< 0x001C0000 */

+#define ADC_SMPR2_SMP16                   ADC_SMPR2_SMP16_Msk                  /*!< ADC Channel 16 Sampling time selection  */

+#define ADC_SMPR2_SMP16_0                 (0x1UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00040000 */

+#define ADC_SMPR2_SMP16_1                 (0x2UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00080000 */

+#define ADC_SMPR2_SMP16_2                 (0x4UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00100000 */

+

+#define ADC_SMPR2_SMP17_Pos               (21U)

+#define ADC_SMPR2_SMP17_Msk               (0x7UL << ADC_SMPR2_SMP17_Pos)       /*!< 0x00E00000 */

+#define ADC_SMPR2_SMP17                   ADC_SMPR2_SMP17_Msk                  /*!< ADC Channel 17 Sampling time selection  */

+#define ADC_SMPR2_SMP17_0                 (0x1UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00200000 */

+#define ADC_SMPR2_SMP17_1                 (0x2UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00400000 */

+#define ADC_SMPR2_SMP17_2                 (0x4UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00800000 */

+

+#define ADC_SMPR2_SMP18_Pos               (24U)

+#define ADC_SMPR2_SMP18_Msk               (0x7UL << ADC_SMPR2_SMP18_Pos)       /*!< 0x07000000 */

+#define ADC_SMPR2_SMP18                   ADC_SMPR2_SMP18_Msk                  /*!< ADC Channel 18 Sampling time selection  */

+#define ADC_SMPR2_SMP18_0                 (0x1UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x01000000 */

+#define ADC_SMPR2_SMP18_1                 (0x2UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x02000000 */

+#define ADC_SMPR2_SMP18_2                 (0x4UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x04000000 */

+

+#define ADC_SMPR2_SMP19_Pos               (27U)

+#define ADC_SMPR2_SMP19_Msk               (0x7UL << ADC_SMPR2_SMP19_Pos)       /*!< 0x38000000 */

+#define ADC_SMPR2_SMP19                   ADC_SMPR2_SMP19_Msk                  /*!< ADC Channel 19 Sampling time selection  */

+#define ADC_SMPR2_SMP19_0                 (0x1UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x08000000 */

+#define ADC_SMPR2_SMP19_1                 (0x2UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x10000000 */

+#define ADC_SMPR2_SMP19_2                 (0x4UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x20000000 */

+

+/********************  Bit definition for ADC_PCSEL register  ********************/

+#define ADC_PCSEL_PCSEL_Pos               (0U)

+#define ADC_PCSEL_PCSEL_Msk               (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)   /*!< 0x000FFFFF */

+#define ADC_PCSEL_PCSEL                   ADC_PCSEL_PCSEL_Msk                  /*!< ADC pre channel selection */

+#define ADC_PCSEL_PCSEL_0                 (0x00001UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */

+#define ADC_PCSEL_PCSEL_1                 (0x00002UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */

+#define ADC_PCSEL_PCSEL_2                 (0x00004UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */

+#define ADC_PCSEL_PCSEL_3                 (0x00008UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */

+#define ADC_PCSEL_PCSEL_4                 (0x00010UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */

+#define ADC_PCSEL_PCSEL_5                 (0x00020UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */

+#define ADC_PCSEL_PCSEL_6                 (0x00040UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */

+#define ADC_PCSEL_PCSEL_7                 (0x00080UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */

+#define ADC_PCSEL_PCSEL_8                 (0x00100UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */

+#define ADC_PCSEL_PCSEL_9                 (0x00200UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */

+#define ADC_PCSEL_PCSEL_10                (0x00400UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */

+#define ADC_PCSEL_PCSEL_11                (0x00800UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */

+#define ADC_PCSEL_PCSEL_12                (0x01000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */

+#define ADC_PCSEL_PCSEL_13                (0x02000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */

+#define ADC_PCSEL_PCSEL_14                (0x04000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */

+#define ADC_PCSEL_PCSEL_15                (0x08000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */

+#define ADC_PCSEL_PCSEL_16                (0x10000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */

+#define ADC_PCSEL_PCSEL_17                (0x20000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */

+#define ADC_PCSEL_PCSEL_18                (0x40000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */

+#define ADC_PCSEL_PCSEL_19                (0x80000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00080000 */

+

+/*****************  Bit definition for ADC_LTR1, 2, 3 registers *****************/

+#define ADC_LTR_LT_Pos                    (0U)

+#define ADC_LTR_LT_Msk                    (0x3FFFFFFUL << ADC_LTR_LT_Pos)      /*!< 0x03FFFFFF */

+#define ADC_LTR_LT                        ADC_LTR_LT_Msk                       /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */

+

+/*****************  Bit definition for ADC_HTR1, 2, 3 registers  ****************/

+#define ADC_HTR_HT_Pos                    (0U)

+#define ADC_HTR_HT_Msk                    (0x3FFFFFFUL << ADC_HTR_HT_Pos)      /*!< 0x03FFFFFF */

+#define ADC_HTR_HT                        ADC_HTR_HT_Msk                       /*!< ADC Analog watchdog 1,2 and 3 higher threshold */

+

+

+/********************  Bit definition for ADC_SQR1 register  ********************/

+#define ADC_SQR1_L_Pos                    (0U)

+#define ADC_SQR1_L_Msk                    (0xFUL << ADC_SQR1_L_Pos)            /*!< 0x0000000F */

+#define ADC_SQR1_L                        ADC_SQR1_L_Msk                       /*!< ADC regular channel sequence lenght */

+#define ADC_SQR1_L_0                      (0x1UL << ADC_SQR1_L_Pos)             /*!< 0x00000001 */

+#define ADC_SQR1_L_1                      (0x2UL << ADC_SQR1_L_Pos)             /*!< 0x00000002 */

+#define ADC_SQR1_L_2                      (0x4UL << ADC_SQR1_L_Pos)             /*!< 0x00000004 */

+#define ADC_SQR1_L_3                      (0x8UL << ADC_SQR1_L_Pos)             /*!< 0x00000008 */

+

+#define ADC_SQR1_SQ1_Pos                  (6U)

+#define ADC_SQR1_SQ1_Msk                  (0x1FUL << ADC_SQR1_SQ1_Pos)         /*!< 0x000007C0 */

+#define ADC_SQR1_SQ1                      ADC_SQR1_SQ1_Msk                     /*!< ADC 1st conversion in regular sequence */

+#define ADC_SQR1_SQ1_0                    (0x01UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000040 */

+#define ADC_SQR1_SQ1_1                    (0x02UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000080 */

+#define ADC_SQR1_SQ1_2                    (0x04UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000100 */

+#define ADC_SQR1_SQ1_3                    (0x08UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000200 */

+#define ADC_SQR1_SQ1_4                    (0x10UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000400 */

+

+#define ADC_SQR1_SQ2_Pos                  (12U)

+#define ADC_SQR1_SQ2_Msk                  (0x1FUL << ADC_SQR1_SQ2_Pos)         /*!< 0x0001F000 */

+#define ADC_SQR1_SQ2                      ADC_SQR1_SQ2_Msk                     /*!< ADC 2nd conversion in regular sequence */

+#define ADC_SQR1_SQ2_0                    (0x01UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00001000 */

+#define ADC_SQR1_SQ2_1                    (0x02UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00002000 */

+#define ADC_SQR1_SQ2_2                    (0x04UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00004000 */

+#define ADC_SQR1_SQ2_3                    (0x08UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00008000 */

+#define ADC_SQR1_SQ2_4                    (0x10UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00010000 */

+

+#define ADC_SQR1_SQ3_Pos                  (18U)

+#define ADC_SQR1_SQ3_Msk                  (0x1FUL << ADC_SQR1_SQ3_Pos)         /*!< 0x007C0000 */

+#define ADC_SQR1_SQ3                      ADC_SQR1_SQ3_Msk                     /*!< ADC 3rd conversion in regular sequence */

+#define ADC_SQR1_SQ3_0                    (0x01UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00040000 */

+#define ADC_SQR1_SQ3_1                    (0x02UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00080000 */

+#define ADC_SQR1_SQ3_2                    (0x04UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00100000 */

+#define ADC_SQR1_SQ3_3                    (0x08UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00200000 */

+#define ADC_SQR1_SQ3_4                    (0x10UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00400000 */

+

+#define ADC_SQR1_SQ4_Pos                  (24U)

+#define ADC_SQR1_SQ4_Msk                  (0x1FUL << ADC_SQR1_SQ4_Pos)         /*!< 0x1F000000 */

+#define ADC_SQR1_SQ4                      ADC_SQR1_SQ4_Msk                     /*!< ADC 4th conversion in regular sequence */

+#define ADC_SQR1_SQ4_0                    (0x01UL << ADC_SQR1_SQ4_Pos)          /*!< 0x01000000 */

+#define ADC_SQR1_SQ4_1                    (0x02UL << ADC_SQR1_SQ4_Pos)          /*!< 0x02000000 */

+#define ADC_SQR1_SQ4_2                    (0x04UL << ADC_SQR1_SQ4_Pos)          /*!< 0x04000000 */

+#define ADC_SQR1_SQ4_3                    (0x08UL << ADC_SQR1_SQ4_Pos)          /*!< 0x08000000 */

+#define ADC_SQR1_SQ4_4                    (0x10UL << ADC_SQR1_SQ4_Pos)          /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR2 register  ********************/

+#define ADC_SQR2_SQ5_Pos                  (0U)

+#define ADC_SQR2_SQ5_Msk                  (0x1FUL << ADC_SQR2_SQ5_Pos)         /*!< 0x0000001F */

+#define ADC_SQR2_SQ5                      ADC_SQR2_SQ5_Msk                     /*!< ADC 5th conversion in regular sequence */

+#define ADC_SQR2_SQ5_0                    (0x01UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000001 */

+#define ADC_SQR2_SQ5_1                    (0x02UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000002 */

+#define ADC_SQR2_SQ5_2                    (0x04UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000004 */

+#define ADC_SQR2_SQ5_3                    (0x08UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000008 */

+#define ADC_SQR2_SQ5_4                    (0x10UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000010 */

+

+#define ADC_SQR2_SQ6_Pos                  (6U)

+#define ADC_SQR2_SQ6_Msk                  (0x1FUL << ADC_SQR2_SQ6_Pos)         /*!< 0x000007C0 */

+#define ADC_SQR2_SQ6                      ADC_SQR2_SQ6_Msk                     /*!< ADC 6th conversion in regular sequence */

+#define ADC_SQR2_SQ6_0                    (0x01UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000040 */

+#define ADC_SQR2_SQ6_1                    (0x02UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000080 */

+#define ADC_SQR2_SQ6_2                    (0x04UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000100 */

+#define ADC_SQR2_SQ6_3                    (0x08UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000200 */

+#define ADC_SQR2_SQ6_4                    (0x10UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000400 */

+

+#define ADC_SQR2_SQ7_Pos                  (12U)

+#define ADC_SQR2_SQ7_Msk                  (0x1FUL << ADC_SQR2_SQ7_Pos)         /*!< 0x0001F000 */

+#define ADC_SQR2_SQ7                      ADC_SQR2_SQ7_Msk                     /*!< ADC 7th conversion in regular sequence */

+#define ADC_SQR2_SQ7_0                    (0x01UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00001000 */

+#define ADC_SQR2_SQ7_1                    (0x02UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00002000 */

+#define ADC_SQR2_SQ7_2                    (0x04UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00004000 */

+#define ADC_SQR2_SQ7_3                    (0x08UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00008000 */

+#define ADC_SQR2_SQ7_4                    (0x10UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00010000 */

+

+#define ADC_SQR2_SQ8_Pos                  (18U)

+#define ADC_SQR2_SQ8_Msk                  (0x1FUL << ADC_SQR2_SQ8_Pos)         /*!< 0x007C0000 */

+#define ADC_SQR2_SQ8                      ADC_SQR2_SQ8_Msk                     /*!< ADC 8th conversion in regular sequence */

+#define ADC_SQR2_SQ8_0                    (0x01UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00040000 */

+#define ADC_SQR2_SQ8_1                    (0x02UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00080000 */

+#define ADC_SQR2_SQ8_2                    (0x04UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00100000 */

+#define ADC_SQR2_SQ8_3                    (0x08UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00200000 */

+#define ADC_SQR2_SQ8_4                    (0x10UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00400000 */

+

+#define ADC_SQR2_SQ9_Pos                  (24U)

+#define ADC_SQR2_SQ9_Msk                  (0x1FUL << ADC_SQR2_SQ9_Pos)         /*!< 0x1F000000 */

+#define ADC_SQR2_SQ9                      ADC_SQR2_SQ9_Msk                     /*!< ADC 9th conversion in regular sequence */

+#define ADC_SQR2_SQ9_0                    (0x01UL << ADC_SQR2_SQ9_Pos)          /*!< 0x01000000 */

+#define ADC_SQR2_SQ9_1                    (0x02UL << ADC_SQR2_SQ9_Pos)          /*!< 0x02000000 */

+#define ADC_SQR2_SQ9_2                    (0x04UL << ADC_SQR2_SQ9_Pos)          /*!< 0x04000000 */

+#define ADC_SQR2_SQ9_3                    (0x08UL << ADC_SQR2_SQ9_Pos)          /*!< 0x08000000 */

+#define ADC_SQR2_SQ9_4                    (0x10UL << ADC_SQR2_SQ9_Pos)          /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR3 register  ********************/

+#define ADC_SQR3_SQ10_Pos                 (0U)

+#define ADC_SQR3_SQ10_Msk                 (0x1FUL << ADC_SQR3_SQ10_Pos)        /*!< 0x0000001F */

+#define ADC_SQR3_SQ10                     ADC_SQR3_SQ10_Msk                    /*!< ADC 10th conversion in regular sequence */

+#define ADC_SQR3_SQ10_0                   (0x01UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000001 */

+#define ADC_SQR3_SQ10_1                   (0x02UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000002 */

+#define ADC_SQR3_SQ10_2                   (0x04UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000004 */

+#define ADC_SQR3_SQ10_3                   (0x08UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000008 */

+#define ADC_SQR3_SQ10_4                   (0x10UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000010 */

+

+#define ADC_SQR3_SQ11_Pos                 (6U)

+#define ADC_SQR3_SQ11_Msk                 (0x1FUL << ADC_SQR3_SQ11_Pos)        /*!< 0x000007C0 */

+#define ADC_SQR3_SQ11                     ADC_SQR3_SQ11_Msk                    /*!< ADC 11th conversion in regular sequence */

+#define ADC_SQR3_SQ11_0                   (0x01UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000040 */

+#define ADC_SQR3_SQ11_1                   (0x02UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000080 */

+#define ADC_SQR3_SQ11_2                   (0x04UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000100 */

+#define ADC_SQR3_SQ11_3                   (0x08UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000200 */

+#define ADC_SQR3_SQ11_4                   (0x10UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000400 */

+

+#define ADC_SQR3_SQ12_Pos                 (12U)

+#define ADC_SQR3_SQ12_Msk                 (0x1FUL << ADC_SQR3_SQ12_Pos)        /*!< 0x0001F000 */

+#define ADC_SQR3_SQ12                     ADC_SQR3_SQ12_Msk                    /*!< ADC 12th conversion in regular sequence */

+#define ADC_SQR3_SQ12_0                   (0x01UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00001000 */

+#define ADC_SQR3_SQ12_1                   (0x02UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00002000 */

+#define ADC_SQR3_SQ12_2                   (0x04UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00004000 */

+#define ADC_SQR3_SQ12_3                   (0x08UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00008000 */

+#define ADC_SQR3_SQ12_4                   (0x10UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00010000 */

+

+#define ADC_SQR3_SQ13_Pos                 (18U)

+#define ADC_SQR3_SQ13_Msk                 (0x1FUL << ADC_SQR3_SQ13_Pos)        /*!< 0x007C0000 */

+#define ADC_SQR3_SQ13                     ADC_SQR3_SQ13_Msk                    /*!< ADC 13th conversion in regular sequence */

+#define ADC_SQR3_SQ13_0                   (0x01UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00040000 */

+#define ADC_SQR3_SQ13_1                   (0x02UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00080000 */

+#define ADC_SQR3_SQ13_2                   (0x04UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00100000 */

+#define ADC_SQR3_SQ13_3                   (0x08UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00200000 */

+#define ADC_SQR3_SQ13_4                   (0x10UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00400000 */

+

+#define ADC_SQR3_SQ14_Pos                 (24U)

+#define ADC_SQR3_SQ14_Msk                 (0x1FUL << ADC_SQR3_SQ14_Pos)        /*!< 0x1F000000 */

+#define ADC_SQR3_SQ14                     ADC_SQR3_SQ14_Msk                    /*!< ADC 14th conversion in regular sequence */

+#define ADC_SQR3_SQ14_0                   (0x01UL << ADC_SQR3_SQ14_Pos)         /*!< 0x01000000 */

+#define ADC_SQR3_SQ14_1                   (0x02UL << ADC_SQR3_SQ14_Pos)         /*!< 0x02000000 */

+#define ADC_SQR3_SQ14_2                   (0x04UL << ADC_SQR3_SQ14_Pos)         /*!< 0x04000000 */

+#define ADC_SQR3_SQ14_3                   (0x08UL << ADC_SQR3_SQ14_Pos)         /*!< 0x08000000 */

+#define ADC_SQR3_SQ14_4                   (0x10UL << ADC_SQR3_SQ14_Pos)         /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR4 register  ********************/

+#define ADC_SQR4_SQ15_Pos                 (0U)

+#define ADC_SQR4_SQ15_Msk                 (0x1FUL << ADC_SQR4_SQ15_Pos)        /*!< 0x0000001F */

+#define ADC_SQR4_SQ15                     ADC_SQR4_SQ15_Msk                    /*!< ADC 15th conversion in regular sequence */

+#define ADC_SQR4_SQ15_0                   (0x01UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000001 */

+#define ADC_SQR4_SQ15_1                   (0x02UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000002 */

+#define ADC_SQR4_SQ15_2                   (0x04UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000004 */

+#define ADC_SQR4_SQ15_3                   (0x08UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000008 */

+#define ADC_SQR4_SQ15_4                   (0x10UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000010 */

+

+#define ADC_SQR4_SQ16_Pos                 (6U)

+#define ADC_SQR4_SQ16_Msk                 (0x1FUL << ADC_SQR4_SQ16_Pos)        /*!< 0x000007C0 */

+#define ADC_SQR4_SQ16                     ADC_SQR4_SQ16_Msk                    /*!< ADC 16th conversion in regular sequence */

+#define ADC_SQR4_SQ16_0                   (0x01UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000040 */

+#define ADC_SQR4_SQ16_1                   (0x02UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000080 */

+#define ADC_SQR4_SQ16_2                   (0x04UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000100 */

+#define ADC_SQR4_SQ16_3                   (0x08UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000200 */

+#define ADC_SQR4_SQ16_4                   (0x10UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000400 */

+/********************  Bit definition for ADC_DR register  ********************/

+#define ADC_DR_RDATA_Pos                  (0U)

+#define ADC_DR_RDATA_Msk                  (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)   /*!< 0xFFFFFFFF */

+#define ADC_DR_RDATA                      ADC_DR_RDATA_Msk                     /*!< ADC regular Data converted */

+

+/********************  Bit definition for ADC_JSQR register  ********************/

+#define ADC_JSQR_JL_Pos                   (0U)

+#define ADC_JSQR_JL_Msk                   (0x3UL << ADC_JSQR_JL_Pos)           /*!< 0x00000003 */

+#define ADC_JSQR_JL                       ADC_JSQR_JL_Msk                      /*!< ADC injected channel sequence length */

+#define ADC_JSQR_JL_0                     (0x1UL << ADC_JSQR_JL_Pos)           /*!< 0x00000001 */

+#define ADC_JSQR_JL_1                     (0x2UL << ADC_JSQR_JL_Pos)           /*!< 0x00000002 */

+

+#define ADC_JSQR_JEXTSEL_Pos              (2U)

+#define ADC_JSQR_JEXTSEL_Msk              (0x1FUL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x0000007C */

+#define ADC_JSQR_JEXTSEL                  ADC_JSQR_JEXTSEL_Msk                 /*!< ADC external trigger selection for injected group */

+#define ADC_JSQR_JEXTSEL_0                (0x01UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000004 */

+#define ADC_JSQR_JEXTSEL_1                (0x02UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000008 */

+#define ADC_JSQR_JEXTSEL_2                (0x04UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000010 */

+#define ADC_JSQR_JEXTSEL_3                (0x08UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000020 */

+#define ADC_JSQR_JEXTSEL_4                (0x10UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000040 */

+

+#define ADC_JSQR_JEXTEN_Pos               (7U)

+#define ADC_JSQR_JEXTEN_Msk               (0x3UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000180 */

+#define ADC_JSQR_JEXTEN                   ADC_JSQR_JEXTEN_Msk                  /*!< ADC external trigger enable and polarity selection for injected channels */

+#define ADC_JSQR_JEXTEN_0                 (0x1UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000080 */

+#define ADC_JSQR_JEXTEN_1                 (0x2UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000100 */

+

+#define ADC_JSQR_JSQ1_Pos                 (9U)

+#define ADC_JSQR_JSQ1_Msk                 (0x1FUL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00003E00 */

+#define ADC_JSQR_JSQ1                     ADC_JSQR_JSQ1_Msk                    /*!< ADC 1st conversion in injected sequence */

+#define ADC_JSQR_JSQ1_0                   (0x01UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000200 */

+#define ADC_JSQR_JSQ1_1                   (0x02UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000400 */

+#define ADC_JSQR_JSQ1_2                   (0x04UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000800 */

+#define ADC_JSQR_JSQ1_3                   (0x08UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00001000 */

+#define ADC_JSQR_JSQ1_4                   (0x10UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00002000 */

+

+#define ADC_JSQR_JSQ2_Pos                 (15U)

+#define ADC_JSQR_JSQ2_Msk                 (0x1FUL << ADC_JSQR_JSQ2_Pos)        /*!< 0x000F8000 */

+#define ADC_JSQR_JSQ2                     ADC_JSQR_JSQ2_Msk                    /*!< ADC 2nd conversion in injected sequence */

+#define ADC_JSQR_JSQ2_0                   (0x01UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00008000 */

+#define ADC_JSQR_JSQ2_1                   (0x02UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00010000 */

+#define ADC_JSQR_JSQ2_2                   (0x04UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00020000 */

+#define ADC_JSQR_JSQ2_3                   (0x08UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00040000 */

+#define ADC_JSQR_JSQ2_4                   (0x10UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00080000 */

+

+#define ADC_JSQR_JSQ3_Pos                 (21U)

+#define ADC_JSQR_JSQ3_Msk                 (0x1FUL << ADC_JSQR_JSQ3_Pos)        /*!< 0x03E00000 */

+#define ADC_JSQR_JSQ3                     ADC_JSQR_JSQ3_Msk                    /*!< ADC 3rd conversion in injected sequence */

+#define ADC_JSQR_JSQ3_0                   (0x01UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00200000 */

+#define ADC_JSQR_JSQ3_1                   (0x02UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00400000 */

+#define ADC_JSQR_JSQ3_2                   (0x04UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00800000 */

+#define ADC_JSQR_JSQ3_3                   (0x08UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x01000000 */

+#define ADC_JSQR_JSQ3_4                   (0x10UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x02000000 */

+

+#define ADC_JSQR_JSQ4_Pos                 (27U)

+#define ADC_JSQR_JSQ4_Msk                 (0x1FUL << ADC_JSQR_JSQ4_Pos)        /*!< 0xF8000000 */

+#define ADC_JSQR_JSQ4                     ADC_JSQR_JSQ4_Msk                    /*!< ADC 4th conversion in injected sequence */

+#define ADC_JSQR_JSQ4_0                   (0x01UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x08000000 */

+#define ADC_JSQR_JSQ4_1                   (0x02UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x10000000 */

+#define ADC_JSQR_JSQ4_2                   (0x04UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x20000000 */

+#define ADC_JSQR_JSQ4_3                   (0x08UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x40000000 */

+#define ADC_JSQR_JSQ4_4                   (0x10UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_OFR1 register  ********************/

+#define ADC_OFR1_OFFSET1_Pos              (0U)

+#define ADC_OFR1_OFFSET1_Msk              (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR1_OFFSET1                  ADC_OFR1_OFFSET1_Msk                  /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */

+#define ADC_OFR1_OFFSET1_0                (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */

+#define ADC_OFR1_OFFSET1_1                (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */

+#define ADC_OFR1_OFFSET1_2                (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */

+#define ADC_OFR1_OFFSET1_3                (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */

+#define ADC_OFR1_OFFSET1_4                (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */

+#define ADC_OFR1_OFFSET1_5                (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */

+#define ADC_OFR1_OFFSET1_6                (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */

+#define ADC_OFR1_OFFSET1_7                (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */

+#define ADC_OFR1_OFFSET1_8                (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */

+#define ADC_OFR1_OFFSET1_9                (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */

+#define ADC_OFR1_OFFSET1_10               (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */

+#define ADC_OFR1_OFFSET1_11               (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */

+#define ADC_OFR1_OFFSET1_12               (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */

+#define ADC_OFR1_OFFSET1_13               (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */

+#define ADC_OFR1_OFFSET1_14               (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */

+#define ADC_OFR1_OFFSET1_15               (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */

+#define ADC_OFR1_OFFSET1_16               (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */

+#define ADC_OFR1_OFFSET1_17               (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */

+#define ADC_OFR1_OFFSET1_18               (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */

+#define ADC_OFR1_OFFSET1_19               (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */

+#define ADC_OFR1_OFFSET1_20               (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */

+#define ADC_OFR1_OFFSET1_21               (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */

+#define ADC_OFR1_OFFSET1_22               (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */

+#define ADC_OFR1_OFFSET1_23               (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */

+#define ADC_OFR1_OFFSET1_24               (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */

+#define ADC_OFR1_OFFSET1_25               (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR1_OFFSET1_CH_Pos           (26U)

+#define ADC_OFR1_OFFSET1_CH_Msk           (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR1_OFFSET1_CH               ADC_OFR1_OFFSET1_CH_Msk               /*!< ADC Channel selection for the data offset 1 */

+#define ADC_OFR1_OFFSET1_CH_0             (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR1_OFFSET1_CH_1             (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR1_OFFSET1_CH_2             (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR1_OFFSET1_CH_3             (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR1_OFFSET1_CH_4             (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR1_SSATE_Pos                (31U)

+#define ADC_OFR1_SSATE_Msk                (0x1UL << ADC_OFR1_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR1_SSATE                    ADC_OFR1_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR2 register  ********************/

+#define ADC_OFR2_OFFSET2_Pos              (0U)

+#define ADC_OFR2_OFFSET2_Msk              (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR2_OFFSET2                  ADC_OFR2_OFFSET2_Msk                  /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */

+#define ADC_OFR2_OFFSET2_0                (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */

+#define ADC_OFR2_OFFSET2_1                (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */

+#define ADC_OFR2_OFFSET2_2                (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */

+#define ADC_OFR2_OFFSET2_3                (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */

+#define ADC_OFR2_OFFSET2_4                (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */

+#define ADC_OFR2_OFFSET2_5                (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */

+#define ADC_OFR2_OFFSET2_6                (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */

+#define ADC_OFR2_OFFSET2_7                (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */

+#define ADC_OFR2_OFFSET2_8                (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */

+#define ADC_OFR2_OFFSET2_9                (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */

+#define ADC_OFR2_OFFSET2_10               (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */

+#define ADC_OFR2_OFFSET2_11               (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */

+#define ADC_OFR2_OFFSET2_12               (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */

+#define ADC_OFR2_OFFSET2_13               (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */

+#define ADC_OFR2_OFFSET2_14               (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */

+#define ADC_OFR2_OFFSET2_15               (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */

+#define ADC_OFR2_OFFSET2_16               (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */

+#define ADC_OFR2_OFFSET2_17               (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */

+#define ADC_OFR2_OFFSET2_18               (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */

+#define ADC_OFR2_OFFSET2_19               (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */

+#define ADC_OFR2_OFFSET2_20               (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */

+#define ADC_OFR2_OFFSET2_21               (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */

+#define ADC_OFR2_OFFSET2_22               (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */

+#define ADC_OFR2_OFFSET2_23               (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */

+#define ADC_OFR2_OFFSET2_24               (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */

+#define ADC_OFR2_OFFSET2_25               (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR2_OFFSET2_CH_Pos           (26U)

+#define ADC_OFR2_OFFSET2_CH_Msk           (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR2_OFFSET2_CH               ADC_OFR2_OFFSET2_CH_Msk               /*!< ADC Channel selection for the data offset 2 */

+#define ADC_OFR2_OFFSET2_CH_0             (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR2_OFFSET2_CH_1             (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR2_OFFSET2_CH_2             (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR2_OFFSET2_CH_3             (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR2_OFFSET2_CH_4             (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR2_SSATE_Pos                (31U)

+#define ADC_OFR2_SSATE_Msk                (0x1UL << ADC_OFR2_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR2_SSATE                    ADC_OFR2_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR3 register  ********************/

+#define ADC_OFR3_OFFSET3_Pos              (0U)

+#define ADC_OFR3_OFFSET3_Msk              (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR3_OFFSET3                  ADC_OFR3_OFFSET3_Msk                  /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */

+#define ADC_OFR3_OFFSET3_0                (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */

+#define ADC_OFR3_OFFSET3_1                (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */

+#define ADC_OFR3_OFFSET3_2                (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */

+#define ADC_OFR3_OFFSET3_3                (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */

+#define ADC_OFR3_OFFSET3_4                (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */

+#define ADC_OFR3_OFFSET3_5                (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */

+#define ADC_OFR3_OFFSET3_6                (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */

+#define ADC_OFR3_OFFSET3_7                (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */

+#define ADC_OFR3_OFFSET3_8                (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */

+#define ADC_OFR3_OFFSET3_9                (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */

+#define ADC_OFR3_OFFSET3_10               (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */

+#define ADC_OFR3_OFFSET3_11               (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */

+#define ADC_OFR3_OFFSET3_12               (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */

+#define ADC_OFR3_OFFSET3_13               (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */

+#define ADC_OFR3_OFFSET3_14               (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */

+#define ADC_OFR3_OFFSET3_15               (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */

+#define ADC_OFR3_OFFSET3_16               (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */

+#define ADC_OFR3_OFFSET3_17               (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */

+#define ADC_OFR3_OFFSET3_18               (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */

+#define ADC_OFR3_OFFSET3_19               (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */

+#define ADC_OFR3_OFFSET3_20               (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */

+#define ADC_OFR3_OFFSET3_21               (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */

+#define ADC_OFR3_OFFSET3_22               (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */

+#define ADC_OFR3_OFFSET3_23               (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */

+#define ADC_OFR3_OFFSET3_24               (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */

+#define ADC_OFR3_OFFSET3_25               (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR3_OFFSET3_CH_Pos           (26U)

+#define ADC_OFR3_OFFSET3_CH_Msk           (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR3_OFFSET3_CH               ADC_OFR3_OFFSET3_CH_Msk               /*!< ADC Channel selection for the data offset 3 */

+#define ADC_OFR3_OFFSET3_CH_0             (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR3_OFFSET3_CH_1             (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR3_OFFSET3_CH_2             (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR3_OFFSET3_CH_3             (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR3_OFFSET3_CH_4             (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR3_SSATE_Pos                (31U)

+#define ADC_OFR3_SSATE_Msk                (0x1UL << ADC_OFR3_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR3_SSATE                    ADC_OFR3_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR4 register  ********************/

+#define ADC_OFR4_OFFSET4_Pos              (0U)

+#define ADC_OFR4_OFFSET4_Msk              (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR4_OFFSET4                  ADC_OFR4_OFFSET4_Msk                  /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */

+#define ADC_OFR4_OFFSET4_0                (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */

+#define ADC_OFR4_OFFSET4_1                (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */

+#define ADC_OFR4_OFFSET4_2                (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */

+#define ADC_OFR4_OFFSET4_3                (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */

+#define ADC_OFR4_OFFSET4_4                (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */

+#define ADC_OFR4_OFFSET4_5                (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */

+#define ADC_OFR4_OFFSET4_6                (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */

+#define ADC_OFR4_OFFSET4_7                (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */

+#define ADC_OFR4_OFFSET4_8                (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */

+#define ADC_OFR4_OFFSET4_9                (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */

+#define ADC_OFR4_OFFSET4_10               (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */

+#define ADC_OFR4_OFFSET4_11               (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */

+#define ADC_OFR4_OFFSET4_12               (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */

+#define ADC_OFR4_OFFSET4_13               (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */

+#define ADC_OFR4_OFFSET4_14               (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */

+#define ADC_OFR4_OFFSET4_15               (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */

+#define ADC_OFR4_OFFSET4_16               (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */

+#define ADC_OFR4_OFFSET4_17               (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */

+#define ADC_OFR4_OFFSET4_18               (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */

+#define ADC_OFR4_OFFSET4_19               (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */

+#define ADC_OFR4_OFFSET4_20               (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */

+#define ADC_OFR4_OFFSET4_21               (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */

+#define ADC_OFR4_OFFSET4_22               (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */

+#define ADC_OFR4_OFFSET4_23               (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */

+#define ADC_OFR4_OFFSET4_24               (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */

+#define ADC_OFR4_OFFSET4_25               (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR4_OFFSET4_CH_Pos           (26U)

+#define ADC_OFR4_OFFSET4_CH_Msk           (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR4_OFFSET4_CH               ADC_OFR4_OFFSET4_CH_Msk               /*!< ADC Channel selection for the data offset 4 */

+#define ADC_OFR4_OFFSET4_CH_0             (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR4_OFFSET4_CH_1             (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR4_OFFSET4_CH_2             (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR4_OFFSET4_CH_3             (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR4_OFFSET4_CH_4             (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR4_SSATE_Pos                (31U)

+#define ADC_OFR4_SSATE_Msk                (0x1UL << ADC_OFR4_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR4_SSATE                    ADC_OFR4_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_JDR1 register  ********************/

+#define ADC_JDR1_JDATA_Pos                (0U)

+#define ADC_JDR1_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR1_JDATA                    ADC_JDR1_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR1_JDATA_0                  (0x00000001UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR1_JDATA_1                  (0x00000002UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR1_JDATA_2                  (0x00000004UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR1_JDATA_3                  (0x00000008UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR1_JDATA_4                  (0x00000010UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR1_JDATA_5                  (0x00000020UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR1_JDATA_6                  (0x00000040UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR1_JDATA_7                  (0x00000080UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR1_JDATA_8                  (0x00000100UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR1_JDATA_9                  (0x00000200UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR1_JDATA_10                 (0x00000400UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR1_JDATA_11                 (0x00000800UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR1_JDATA_12                 (0x00001000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR1_JDATA_13                 (0x00002000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR1_JDATA_14                 (0x00004000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR1_JDATA_15                 (0x00008000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR1_JDATA_16                 (0x00010000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR1_JDATA_17                 (0x00020000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR1_JDATA_18                 (0x00040000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR1_JDATA_19                 (0x00080000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR1_JDATA_20                 (0x00100000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR1_JDATA_21                 (0x00200000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR1_JDATA_22                 (0x00400000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR1_JDATA_23                 (0x00800000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR1_JDATA_24                 (0x01000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR1_JDATA_25                 (0x02000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR1_JDATA_26                 (0x04000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR1_JDATA_27                 (0x08000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR1_JDATA_28                 (0x10000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR1_JDATA_29                 (0x20000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR1_JDATA_30                 (0x40000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR1_JDATA_31                 (0x80000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR2 register  ********************/

+#define ADC_JDR2_JDATA_Pos                (0U)

+#define ADC_JDR2_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR2_JDATA                    ADC_JDR2_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR2_JDATA_0                  (0x00000001UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR2_JDATA_1                  (0x00000002UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR2_JDATA_2                  (0x00000004UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR2_JDATA_3                  (0x00000008UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR2_JDATA_4                  (0x00000010UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR2_JDATA_5                  (0x00000020UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR2_JDATA_6                  (0x00000040UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR2_JDATA_7                  (0x00000080UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR2_JDATA_8                  (0x00000100UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR2_JDATA_9                  (0x00000200UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR2_JDATA_10                 (0x00000400UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR2_JDATA_11                 (0x00000800UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR2_JDATA_12                 (0x00001000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR2_JDATA_13                 (0x00002000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR2_JDATA_14                 (0x00004000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR2_JDATA_15                 (0x00008000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR2_JDATA_16                 (0x00010000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR2_JDATA_17                 (0x00020000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR2_JDATA_18                 (0x00040000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR2_JDATA_19                 (0x00080000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR2_JDATA_20                 (0x00100000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR2_JDATA_21                 (0x00200000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR2_JDATA_22                 (0x00400000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR2_JDATA_23                 (0x00800000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR2_JDATA_24                 (0x01000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR2_JDATA_25                 (0x02000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR2_JDATA_26                 (0x04000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR2_JDATA_27                 (0x08000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR2_JDATA_28                 (0x10000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR2_JDATA_29                 (0x20000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR2_JDATA_30                 (0x40000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR2_JDATA_31                 (0x80000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR3 register  ********************/

+#define ADC_JDR3_JDATA_Pos                (0U)

+#define ADC_JDR3_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR3_JDATA                    ADC_JDR3_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR3_JDATA_0                  (0x00000001UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR3_JDATA_1                  (0x00000002UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR3_JDATA_2                  (0x00000004UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR3_JDATA_3                  (0x00000008UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR3_JDATA_4                  (0x00000010UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR3_JDATA_5                  (0x00000020UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR3_JDATA_6                  (0x00000040UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR3_JDATA_7                  (0x00000080UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR3_JDATA_8                  (0x00000100UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR3_JDATA_9                  (0x00000200UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR3_JDATA_10                 (0x00000400UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR3_JDATA_11                 (0x00000800UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR3_JDATA_12                 (0x00001000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR3_JDATA_13                 (0x00002000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR3_JDATA_14                 (0x00004000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR3_JDATA_15                 (0x00008000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR3_JDATA_16                 (0x00010000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR3_JDATA_17                 (0x00020000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR3_JDATA_18                 (0x00040000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR3_JDATA_19                 (0x00080000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR3_JDATA_20                 (0x00100000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR3_JDATA_21                 (0x00200000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR3_JDATA_22                 (0x00400000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR3_JDATA_23                 (0x00800000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR3_JDATA_24                 (0x01000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR3_JDATA_25                 (0x02000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR3_JDATA_26                 (0x04000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR3_JDATA_27                 (0x08000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR3_JDATA_28                 (0x10000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR3_JDATA_29                 (0x20000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR3_JDATA_30                 (0x40000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR3_JDATA_31                 (0x80000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR4 register  ********************/

+#define ADC_JDR4_JDATA_Pos                (0U)

+#define ADC_JDR4_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR4_JDATA                    ADC_JDR4_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR4_JDATA_0                  (0x00000001UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR4_JDATA_1                  (0x00000002UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR4_JDATA_2                  (0x00000004UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR4_JDATA_3                  (0x00000008UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR4_JDATA_4                  (0x00000010UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR4_JDATA_5                  (0x00000020UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR4_JDATA_6                  (0x00000040UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR4_JDATA_7                  (0x00000080UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR4_JDATA_8                  (0x00000100UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR4_JDATA_9                  (0x00000200UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR4_JDATA_10                 (0x00000400UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR4_JDATA_11                 (0x00000800UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR4_JDATA_12                 (0x00001000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR4_JDATA_13                 (0x00002000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR4_JDATA_14                 (0x00004000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR4_JDATA_15                 (0x00008000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR4_JDATA_16                 (0x00010000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR4_JDATA_17                 (0x00020000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR4_JDATA_18                 (0x00040000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR4_JDATA_19                 (0x00080000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR4_JDATA_20                 (0x00100000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR4_JDATA_21                 (0x00200000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR4_JDATA_22                 (0x00400000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR4_JDATA_23                 (0x00800000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR4_JDATA_24                 (0x01000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR4_JDATA_25                 (0x02000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR4_JDATA_26                 (0x04000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR4_JDATA_27                 (0x08000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR4_JDATA_28                 (0x10000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR4_JDATA_29                 (0x20000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR4_JDATA_30                 (0x40000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR4_JDATA_31                 (0x80000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_AWD2CR register  ********************/

+#define ADC_AWD2CR_AWD2CH_Pos             (0U)

+#define ADC_AWD2CR_AWD2CH_Msk             (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x000FFFFF */

+#define ADC_AWD2CR_AWD2CH                 ADC_AWD2CR_AWD2CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */

+#define ADC_AWD2CR_AWD2CH_0               (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000001 */

+#define ADC_AWD2CR_AWD2CH_1               (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000002 */

+#define ADC_AWD2CR_AWD2CH_2               (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000004 */

+#define ADC_AWD2CR_AWD2CH_3               (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000008 */

+#define ADC_AWD2CR_AWD2CH_4               (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000010 */

+#define ADC_AWD2CR_AWD2CH_5               (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000020 */

+#define ADC_AWD2CR_AWD2CH_6               (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000040 */

+#define ADC_AWD2CR_AWD2CH_7               (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000080 */

+#define ADC_AWD2CR_AWD2CH_8               (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000100 */

+#define ADC_AWD2CR_AWD2CH_9               (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000200 */

+#define ADC_AWD2CR_AWD2CH_10              (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000400 */

+#define ADC_AWD2CR_AWD2CH_11              (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000800 */

+#define ADC_AWD2CR_AWD2CH_12              (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00001000 */

+#define ADC_AWD2CR_AWD2CH_13              (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00002000 */

+#define ADC_AWD2CR_AWD2CH_14              (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00004000 */

+#define ADC_AWD2CR_AWD2CH_15              (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00008000 */

+#define ADC_AWD2CR_AWD2CH_16              (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00010000 */

+#define ADC_AWD2CR_AWD2CH_17              (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00020000 */

+#define ADC_AWD2CR_AWD2CH_18              (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */

+#define ADC_AWD2CR_AWD2CH_19              (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_AWD3CR register  ********************/

+#define ADC_AWD3CR_AWD3CH_Pos             (0U)

+#define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x000FFFFF */

+#define ADC_AWD3CR_AWD3CH                 ADC_AWD3CR_AWD3CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */

+#define ADC_AWD3CR_AWD3CH_0               (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000001 */

+#define ADC_AWD3CR_AWD3CH_1               (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000002 */

+#define ADC_AWD3CR_AWD3CH_2               (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000004 */

+#define ADC_AWD3CR_AWD3CH_3               (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000008 */

+#define ADC_AWD3CR_AWD3CH_4               (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000010 */

+#define ADC_AWD3CR_AWD3CH_5               (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000020 */

+#define ADC_AWD3CR_AWD3CH_6               (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000040 */

+#define ADC_AWD3CR_AWD3CH_7               (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000080 */

+#define ADC_AWD3CR_AWD3CH_8               (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000100 */

+#define ADC_AWD3CR_AWD3CH_9               (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000200 */

+#define ADC_AWD3CR_AWD3CH_10              (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000400 */

+#define ADC_AWD3CR_AWD3CH_11              (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000800 */

+#define ADC_AWD3CR_AWD3CH_12              (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00001000 */

+#define ADC_AWD3CR_AWD3CH_13              (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00002000 */

+#define ADC_AWD3CR_AWD3CH_14              (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00004000 */

+#define ADC_AWD3CR_AWD3CH_15              (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00008000 */

+#define ADC_AWD3CR_AWD3CH_16              (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00010000 */

+#define ADC_AWD3CR_AWD3CH_17              (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00020000 */

+#define ADC_AWD3CR_AWD3CH_18              (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */

+#define ADC_AWD3CR_AWD3CH_19              (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_DIFSEL register  ********************/

+#define ADC_DIFSEL_DIFSEL_Pos             (0U)

+#define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */

+#define ADC_DIFSEL_DIFSEL                 ADC_DIFSEL_DIFSEL_Msk                 /*!< ADC differential modes for channels 1 to 18 */

+#define ADC_DIFSEL_DIFSEL_0               (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000001 */

+#define ADC_DIFSEL_DIFSEL_1               (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000002 */

+#define ADC_DIFSEL_DIFSEL_2               (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000004 */

+#define ADC_DIFSEL_DIFSEL_3               (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000008 */

+#define ADC_DIFSEL_DIFSEL_4               (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000010 */

+#define ADC_DIFSEL_DIFSEL_5               (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000020 */

+#define ADC_DIFSEL_DIFSEL_6               (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000040 */

+#define ADC_DIFSEL_DIFSEL_7               (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000080 */

+#define ADC_DIFSEL_DIFSEL_8               (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000100 */

+#define ADC_DIFSEL_DIFSEL_9               (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000200 */

+#define ADC_DIFSEL_DIFSEL_10              (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000400 */

+#define ADC_DIFSEL_DIFSEL_11              (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000800 */

+#define ADC_DIFSEL_DIFSEL_12              (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00001000 */

+#define ADC_DIFSEL_DIFSEL_13              (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00002000 */

+#define ADC_DIFSEL_DIFSEL_14              (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00004000 */

+#define ADC_DIFSEL_DIFSEL_15              (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00008000 */

+#define ADC_DIFSEL_DIFSEL_16              (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00010000 */

+#define ADC_DIFSEL_DIFSEL_17              (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00020000 */

+#define ADC_DIFSEL_DIFSEL_18              (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00040000 */

+#define ADC_DIFSEL_DIFSEL_19              (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_CALFACT register  ********************/

+#define ADC_CALFACT_CALFACT_S_Pos         (0U)

+#define ADC_CALFACT_CALFACT_S_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */

+#define ADC_CALFACT_CALFACT_S             ADC_CALFACT_CALFACT_S_Msk              /*!< ADC calibration factors in single-ended mode */

+#define ADC_CALFACT_CALFACT_S_0           (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */

+#define ADC_CALFACT_CALFACT_S_1           (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */

+#define ADC_CALFACT_CALFACT_S_2           (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */

+#define ADC_CALFACT_CALFACT_S_3           (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */

+#define ADC_CALFACT_CALFACT_S_4           (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */

+#define ADC_CALFACT_CALFACT_S_5           (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */

+#define ADC_CALFACT_CALFACT_S_6           (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */

+#define ADC_CALFACT_CALFACT_S_7           (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */

+#define ADC_CALFACT_CALFACT_S_8           (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */

+#define ADC_CALFACT_CALFACT_S_9           (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */

+#define ADC_CALFACT_CALFACT_S_10          (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */

+#define ADC_CALFACT_CALFACT_D_Pos         (16U)

+#define ADC_CALFACT_CALFACT_D_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */

+#define ADC_CALFACT_CALFACT_D             ADC_CALFACT_CALFACT_D_Msk              /*!< ADC calibration factors in differential mode */

+#define ADC_CALFACT_CALFACT_D_0           (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */

+#define ADC_CALFACT_CALFACT_D_1           (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */

+#define ADC_CALFACT_CALFACT_D_2           (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */

+#define ADC_CALFACT_CALFACT_D_3           (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */

+#define ADC_CALFACT_CALFACT_D_4           (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */

+#define ADC_CALFACT_CALFACT_D_5           (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */

+#define ADC_CALFACT_CALFACT_D_6           (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */

+#define ADC_CALFACT_CALFACT_D_7           (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */

+#define ADC_CALFACT_CALFACT_D_8           (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */

+#define ADC_CALFACT_CALFACT_D_9           (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */

+#define ADC_CALFACT_CALFACT_D_10          (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */

+

+/********************  Bit definition for ADC_CALFACT2 register  ********************/

+#define ADC_CALFACT2_LINCALFACT_Pos       (0U)

+#define ADC_CALFACT2_LINCALFACT_Msk       (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */

+#define ADC_CALFACT2_LINCALFACT           ADC_CALFACT2_LINCALFACT_Msk                   /*!< ADC Linearity calibration factors */

+#define ADC_CALFACT2_LINCALFACT_0         (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */

+#define ADC_CALFACT2_LINCALFACT_1         (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */

+#define ADC_CALFACT2_LINCALFACT_2         (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */

+#define ADC_CALFACT2_LINCALFACT_3         (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */

+#define ADC_CALFACT2_LINCALFACT_4         (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */

+#define ADC_CALFACT2_LINCALFACT_5         (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */

+#define ADC_CALFACT2_LINCALFACT_6         (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */

+#define ADC_CALFACT2_LINCALFACT_7         (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */

+#define ADC_CALFACT2_LINCALFACT_8         (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */

+#define ADC_CALFACT2_LINCALFACT_9         (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */

+#define ADC_CALFACT2_LINCALFACT_10        (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */

+#define ADC_CALFACT2_LINCALFACT_11        (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */

+#define ADC_CALFACT2_LINCALFACT_12        (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */

+#define ADC_CALFACT2_LINCALFACT_13        (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */

+#define ADC_CALFACT2_LINCALFACT_14        (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */

+#define ADC_CALFACT2_LINCALFACT_15        (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */

+#define ADC_CALFACT2_LINCALFACT_16        (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */

+#define ADC_CALFACT2_LINCALFACT_17        (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */

+#define ADC_CALFACT2_LINCALFACT_18        (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */

+#define ADC_CALFACT2_LINCALFACT_19        (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */

+#define ADC_CALFACT2_LINCALFACT_20        (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */

+#define ADC_CALFACT2_LINCALFACT_21        (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */

+#define ADC_CALFACT2_LINCALFACT_22        (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */

+#define ADC_CALFACT2_LINCALFACT_23        (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */

+#define ADC_CALFACT2_LINCALFACT_24        (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */

+#define ADC_CALFACT2_LINCALFACT_25        (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */

+#define ADC_CALFACT2_LINCALFACT_26        (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */

+#define ADC_CALFACT2_LINCALFACT_27        (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */

+#define ADC_CALFACT2_LINCALFACT_28        (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */

+#define ADC_CALFACT2_LINCALFACT_29        (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */

+

+/*************************  ADC Common registers  *****************************/

+/********************  Bit definition for ADC_CSR register  ********************/

+#define ADC_CSR_ADRDY_MST_Pos             (0U)

+#define ADC_CSR_ADRDY_MST_Msk             (0x1UL << ADC_CSR_ADRDY_MST_Pos)     /*!< 0x00000001 */

+#define ADC_CSR_ADRDY_MST                 ADC_CSR_ADRDY_MST_Msk                /*!< Master ADC ready */

+#define ADC_CSR_EOSMP_MST_Pos             (1U)

+#define ADC_CSR_EOSMP_MST_Msk             (0x1UL << ADC_CSR_EOSMP_MST_Pos)     /*!< 0x00000002 */

+#define ADC_CSR_EOSMP_MST                 ADC_CSR_EOSMP_MST_Msk                /*!< End of sampling phase flag of the master ADC */

+#define ADC_CSR_EOC_MST_Pos               (2U)

+#define ADC_CSR_EOC_MST_Msk               (0x1UL << ADC_CSR_EOC_MST_Pos)       /*!< 0x00000004 */

+#define ADC_CSR_EOC_MST                   ADC_CSR_EOC_MST_Msk                  /*!< End of regular conversion of the master ADC */

+#define ADC_CSR_EOS_MST_Pos               (3U)

+#define ADC_CSR_EOS_MST_Msk               (0x1UL << ADC_CSR_EOS_MST_Pos)       /*!< 0x00000008 */

+#define ADC_CSR_EOS_MST                   ADC_CSR_EOS_MST_Msk                  /*!< End of regular sequence flag of the master ADC */

+#define ADC_CSR_OVR_MST_Pos               (4U)

+#define ADC_CSR_OVR_MST_Msk               (0x1UL << ADC_CSR_OVR_MST_Pos)       /*!< 0x00000010 */

+#define ADC_CSR_OVR_MST                   ADC_CSR_OVR_MST_Msk                  /*!< Overrun flag of the master ADC */

+#define ADC_CSR_JEOC_MST_Pos              (5U)

+#define ADC_CSR_JEOC_MST_Msk              (0x1UL << ADC_CSR_JEOC_MST_Pos)      /*!< 0x00000020 */

+#define ADC_CSR_JEOC_MST                  ADC_CSR_JEOC_MST_Msk                 /*!< End of injected conversion of the master ADC */

+#define ADC_CSR_JEOS_MST_Pos              (6U)

+#define ADC_CSR_JEOS_MST_Msk              (0x1UL << ADC_CSR_JEOS_MST_Pos)      /*!< 0x00000040 */

+#define ADC_CSR_JEOS_MST                  ADC_CSR_JEOS_MST_Msk                 /*!< End of injected sequence flag of the master ADC */

+#define ADC_CSR_AWD1_MST_Pos              (7U)

+#define ADC_CSR_AWD1_MST_Msk              (0x1UL << ADC_CSR_AWD1_MST_Pos)      /*!< 0x00000080 */

+#define ADC_CSR_AWD1_MST                  ADC_CSR_AWD1_MST_Msk                 /*!< Analog watchdog 1 flag of the master ADC */

+#define ADC_CSR_AWD2_MST_Pos              (8U)

+#define ADC_CSR_AWD2_MST_Msk              (0x1UL << ADC_CSR_AWD2_MST_Pos)      /*!< 0x00000100 */

+#define ADC_CSR_AWD2_MST                  ADC_CSR_AWD2_MST_Msk                 /*!< Analog watchdog 2 flag of the master ADC */

+#define ADC_CSR_AWD3_MST_Pos              (9U)

+#define ADC_CSR_AWD3_MST_Msk              (0x1UL << ADC_CSR_AWD3_MST_Pos)      /*!< 0x00000200 */

+#define ADC_CSR_AWD3_MST                  ADC_CSR_AWD3_MST_Msk                 /*!< Analog watchdog 3 flag of the master ADC */

+#define ADC_CSR_JQOVF_MST_Pos             (10U)

+#define ADC_CSR_JQOVF_MST_Msk             (0x1UL << ADC_CSR_JQOVF_MST_Pos)     /*!< 0x00000400 */

+#define ADC_CSR_JQOVF_MST                 ADC_CSR_JQOVF_MST_Msk                /*!< Injected context queue overflow flag of the master ADC */

+#define ADC_CSR_ADRDY_SLV_Pos             (16U)

+#define ADC_CSR_ADRDY_SLV_Msk             (0x1UL << ADC_CSR_ADRDY_SLV_Pos)     /*!< 0x00010000 */

+#define ADC_CSR_ADRDY_SLV                 ADC_CSR_ADRDY_SLV_Msk                /*!< Slave ADC ready */

+#define ADC_CSR_EOSMP_SLV_Pos             (17U)

+#define ADC_CSR_EOSMP_SLV_Msk             (0x1UL << ADC_CSR_EOSMP_SLV_Pos)     /*!< 0x00020000 */

+#define ADC_CSR_EOSMP_SLV                 ADC_CSR_EOSMP_SLV_Msk                /*!< End of sampling phase flag of the slave ADC */

+#define ADC_CSR_EOC_SLV_Pos               (18U)

+#define ADC_CSR_EOC_SLV_Msk               (0x1UL << ADC_CSR_EOC_SLV_Pos)       /*!< 0x00040000 */

+#define ADC_CSR_EOC_SLV                   ADC_CSR_EOC_SLV_Msk                  /*!< End of regular conversion of the slave ADC */

+#define ADC_CSR_EOS_SLV_Pos               (19U)

+#define ADC_CSR_EOS_SLV_Msk               (0x1UL << ADC_CSR_EOS_SLV_Pos)       /*!< 0x00080000 */

+#define ADC_CSR_EOS_SLV                   ADC_CSR_EOS_SLV_Msk                  /*!< End of regular sequence flag of the slave ADC */

+#define ADC_CSR_OVR_SLV_Pos               (20U)

+#define ADC_CSR_OVR_SLV_Msk               (0x1UL << ADC_CSR_OVR_SLV_Pos)       /*!< 0x00100000 */

+#define ADC_CSR_OVR_SLV                   ADC_CSR_OVR_SLV_Msk                  /*!< Overrun flag of the slave ADC */

+#define ADC_CSR_JEOC_SLV_Pos              (21U)

+#define ADC_CSR_JEOC_SLV_Msk              (0x1UL << ADC_CSR_JEOC_SLV_Pos)      /*!< 0x00200000 */

+#define ADC_CSR_JEOC_SLV                  ADC_CSR_JEOC_SLV_Msk                 /*!< End of injected conversion of the slave ADC */

+#define ADC_CSR_JEOS_SLV_Pos              (22U)

+#define ADC_CSR_JEOS_SLV_Msk              (0x1UL << ADC_CSR_JEOS_SLV_Pos)      /*!< 0x00400000 */

+#define ADC_CSR_JEOS_SLV                  ADC_CSR_JEOS_SLV_Msk                 /*!< End of injected sequence flag of the slave ADC */

+#define ADC_CSR_AWD1_SLV_Pos              (23U)

+#define ADC_CSR_AWD1_SLV_Msk              (0x1UL << ADC_CSR_AWD1_SLV_Pos)      /*!< 0x00800000 */

+#define ADC_CSR_AWD1_SLV                  ADC_CSR_AWD1_SLV_Msk                 /*!< Analog watchdog 1 flag of the slave ADC */

+#define ADC_CSR_AWD2_SLV_Pos              (24U)

+#define ADC_CSR_AWD2_SLV_Msk              (0x1UL << ADC_CSR_AWD2_SLV_Pos)      /*!< 0x01000000 */

+#define ADC_CSR_AWD2_SLV                  ADC_CSR_AWD2_SLV_Msk                 /*!< Analog watchdog 2 flag of the slave ADC */

+#define ADC_CSR_AWD3_SLV_Pos              (25U)

+#define ADC_CSR_AWD3_SLV_Msk              (0x1UL << ADC_CSR_AWD3_SLV_Pos)      /*!< 0x02000000 */

+#define ADC_CSR_AWD3_SLV                  ADC_CSR_AWD3_SLV_Msk                 /*!< Analog watchdog 3 flag of the slave ADC */

+#define ADC_CSR_JQOVF_SLV_Pos             (26U)

+#define ADC_CSR_JQOVF_SLV_Msk             (0x1UL << ADC_CSR_JQOVF_SLV_Pos)     /*!< 0x04000000 */

+#define ADC_CSR_JQOVF_SLV                 ADC_CSR_JQOVF_SLV_Msk                /*!< Injected context queue overflow flag of the slave ADC */

+

+/********************  Bit definition for ADC_CCR register  ********************/

+#define ADC_CCR_DUAL_Pos                  (0U)

+#define ADC_CCR_DUAL_Msk                  (0x1FUL << ADC_CCR_DUAL_Pos)          /*!< 0x0000001F */

+#define ADC_CCR_DUAL                      ADC_CCR_DUAL_Msk                      /*!< Dual ADC mode selection */

+#define ADC_CCR_DUAL_0                    (0x01UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000001 */

+#define ADC_CCR_DUAL_1                    (0x02UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000002 */

+#define ADC_CCR_DUAL_2                    (0x04UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000004 */

+#define ADC_CCR_DUAL_3                    (0x08UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000008 */

+#define ADC_CCR_DUAL_4                    (0x10UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000010 */

+

+#define ADC_CCR_DELAY_Pos                 (8U)

+#define ADC_CCR_DELAY_Msk                 (0xFUL << ADC_CCR_DELAY_Pos)          /*!< 0x00000F00 */

+#define ADC_CCR_DELAY                     ADC_CCR_DELAY_Msk                     /*!< Delay between 2 sampling phases */

+#define ADC_CCR_DELAY_0                   (0x1UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000100 */

+#define ADC_CCR_DELAY_1                   (0x2UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000200 */

+#define ADC_CCR_DELAY_2                   (0x4UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000400 */

+#define ADC_CCR_DELAY_3                   (0x8UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000800 */

+

+

+#define ADC_CCR_DAMDF_Pos                 (14U)

+#define ADC_CCR_DAMDF_Msk                 (0x3UL << ADC_CCR_DAMDF_Pos)          /*!< 0x0000C000 */

+#define ADC_CCR_DAMDF                     ADC_CCR_DAMDF_Msk                     /*!< Dual ADC mode Data format */

+#define ADC_CCR_DAMDF_0                   (0x1UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00004000 */

+#define ADC_CCR_DAMDF_1                   (0x2UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00008000 */

+

+#define ADC_CCR_CKMODE_Pos                (16U)

+#define ADC_CCR_CKMODE_Msk                (0x3UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00030000 */

+#define ADC_CCR_CKMODE                    ADC_CCR_CKMODE_Msk                    /*!< ADC clock mode */

+#define ADC_CCR_CKMODE_0                  (0x1UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00010000 */

+#define ADC_CCR_CKMODE_1                  (0x2UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00020000 */

+

+#define ADC_CCR_PRESC_Pos                 (18U)

+#define ADC_CCR_PRESC_Msk                 (0xFUL << ADC_CCR_PRESC_Pos)          /*!< 0x003C0000 */

+#define ADC_CCR_PRESC                     ADC_CCR_PRESC_Msk                     /*!< ADC prescaler */

+#define ADC_CCR_PRESC_0                   (0x1UL << ADC_CCR_PRESC_Pos)          /*!< 0x00040000 */

+#define ADC_CCR_PRESC_1                   (0x2UL << ADC_CCR_PRESC_Pos)          /*!< 0x00080000 */

+#define ADC_CCR_PRESC_2                   (0x4UL << ADC_CCR_PRESC_Pos)          /*!< 0x00100000 */

+#define ADC_CCR_PRESC_3                   (0x8UL << ADC_CCR_PRESC_Pos)          /*!< 0x00200000 */

+

+#define ADC_CCR_VREFEN_Pos                (22U)

+#define ADC_CCR_VREFEN_Msk                (0x1UL << ADC_CCR_VREFEN_Pos)         /*!< 0x00400000 */

+#define ADC_CCR_VREFEN                    ADC_CCR_VREFEN_Msk                    /*!< VREFINT enable */

+#define ADC_CCR_TSEN_Pos                  (23U)

+#define ADC_CCR_TSEN_Msk                  (0x1UL << ADC_CCR_TSEN_Pos)           /*!< 0x00800000 */

+#define ADC_CCR_TSEN                      ADC_CCR_TSEN_Msk                      /*!< Temperature sensor enable */

+#define ADC_CCR_VBATEN_Pos                (24U)

+#define ADC_CCR_VBATEN_Msk                (0x1UL << ADC_CCR_VBATEN_Pos)         /*!< 0x01000000 */

+#define ADC_CCR_VBATEN                    ADC_CCR_VBATEN_Msk                    /*!< VBAT enable */

+

+/********************  Bit definition for ADC_CDR register  *******************/

+#define ADC_CDR_RDATA_MST_Pos             (0U)

+#define ADC_CDR_RDATA_MST_Msk             (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)   /*!< 0x0000FFFF */

+#define ADC_CDR_RDATA_MST                 ADC_CDR_RDATA_MST_Msk                 /*!< ADC multimode master group regular conversion data */

+

+#define ADC_CDR_RDATA_SLV_Pos             (16U)

+#define ADC_CDR_RDATA_SLV_Msk             (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)   /*!< 0xFFFF0000 */

+#define ADC_CDR_RDATA_SLV                 ADC_CDR_RDATA_SLV_Msk                 /*!< ADC multimode slave group regular conversion data */

+

+/********************  Bit definition for ADC_CDR2 register  ******************/

+#define ADC_CDR2_RDATA_ALT_Pos            (0U)

+#define ADC_CDR2_RDATA_ALT_Msk            (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */

+#define ADC_CDR2_RDATA_ALT                ADC_CDR2_RDATA_ALT_Msk                   /*!< Regular data of the master/slave alternated ADCs */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                   VREFBUF                                  */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for VREFBUF_CSR register  ****************/

+#define VREFBUF_CSR_ENVR_Pos        (0U)

+#define VREFBUF_CSR_ENVR_Msk        (0x1UL << VREFBUF_CSR_ENVR_Pos)            /*!< 0x00000001 */

+#define VREFBUF_CSR_ENVR            VREFBUF_CSR_ENVR_Msk                       /*!<Voltage reference buffer enable */

+#define VREFBUF_CSR_HIZ_Pos         (1U)

+#define VREFBUF_CSR_HIZ_Msk         (0x1UL << VREFBUF_CSR_HIZ_Pos)             /*!< 0x00000002 */

+#define VREFBUF_CSR_HIZ             VREFBUF_CSR_HIZ_Msk                        /*!<High impedance mode             */

+#define VREFBUF_CSR_VRR_Pos         (3U)

+#define VREFBUF_CSR_VRR_Msk         (0x1UL << VREFBUF_CSR_VRR_Pos)             /*!< 0x00000008 */

+#define VREFBUF_CSR_VRR             VREFBUF_CSR_VRR_Msk                        /*!<Voltage reference buffer ready  */

+#define VREFBUF_CSR_VRS_Pos         (4U)

+#define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */

+#define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */

+

+#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */

+#define VREFBUF_CSR_VRS_OUT2_Pos    (4U)

+#define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */

+#define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */

+#define VREFBUF_CSR_VRS_OUT3_Pos    (5U)

+#define VREFBUF_CSR_VRS_OUT3_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)        /*!< 0x00000020 */

+#define VREFBUF_CSR_VRS_OUT3        VREFBUF_CSR_VRS_OUT3_Msk                   /*!<Voltage reference VREF_OUT3     */

+#define VREFBUF_CSR_VRS_OUT4_Pos    (4U)

+#define VREFBUF_CSR_VRS_OUT4_Msk    (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)        /*!< 0x00000030 */

+#define VREFBUF_CSR_VRS_OUT4        VREFBUF_CSR_VRS_OUT4_Msk                   /*!<Voltage reference VREF_OUT4     */

+

+/*******************  Bit definition for VREFBUF_CCR register  ****************/

+#define VREFBUF_CCR_TRIM_Pos        (0U)

+#define VREFBUF_CCR_TRIM_Msk        (0x3FUL << VREFBUF_CCR_TRIM_Pos)           /*!< 0x0000003F */

+#define VREFBUF_CCR_TRIM            VREFBUF_CCR_TRIM_Msk                       /*!<TRIM[5:0] bits (Trimming code)  */

+

+/******************************************************************************/

+/*                                                                            */

+/*                 Flexible Datarate Controller Area Network                  */

+/*                                                                            */

+/******************************************************************************/

+/*!<FDCAN control and status registers */

+/*****************  Bit definition for FDCAN_CREL register  *******************/

+#define FDCAN_CREL_DAY_Pos        (0U)

+#define FDCAN_CREL_DAY_Msk        (0xFFUL << FDCAN_CREL_DAY_Pos)               /*!< 0x000000FF */

+#define FDCAN_CREL_DAY            FDCAN_CREL_DAY_Msk                           /*!<Timestamp Day                           */

+#define FDCAN_CREL_MON_Pos        (8U)

+#define FDCAN_CREL_MON_Msk        (0xFFUL << FDCAN_CREL_MON_Pos)               /*!< 0x0000FF00 */

+#define FDCAN_CREL_MON            FDCAN_CREL_MON_Msk                           /*!<Timestamp Month                         */

+#define FDCAN_CREL_YEAR_Pos       (16U)

+#define FDCAN_CREL_YEAR_Msk       (0xFUL << FDCAN_CREL_YEAR_Pos)               /*!< 0x000F0000 */

+#define FDCAN_CREL_YEAR           FDCAN_CREL_YEAR_Msk                          /*!<Timestamp Year                          */

+#define FDCAN_CREL_SUBSTEP_Pos    (20U)

+#define FDCAN_CREL_SUBSTEP_Msk    (0xFUL << FDCAN_CREL_SUBSTEP_Pos)            /*!< 0x00F00000 */

+#define FDCAN_CREL_SUBSTEP        FDCAN_CREL_SUBSTEP_Msk                       /*!<Sub-step of Core release                */

+#define FDCAN_CREL_STEP_Pos       (24U)

+#define FDCAN_CREL_STEP_Msk       (0xFUL << FDCAN_CREL_STEP_Pos)               /*!< 0x0F000000 */

+#define FDCAN_CREL_STEP           FDCAN_CREL_STEP_Msk                          /*!<Step of Core release                    */

+#define FDCAN_CREL_REL_Pos        (28U)

+#define FDCAN_CREL_REL_Msk        (0xFUL << FDCAN_CREL_REL_Pos)                /*!< 0xF0000000 */

+#define FDCAN_CREL_REL            FDCAN_CREL_REL_Msk                           /*!<Core release                            */

+

+/*****************  Bit definition for FDCAN_ENDN register  *******************/

+#define FDCAN_ENDN_ETV_Pos        (0U)

+#define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endiannes Test Value                    */

+

+/*****************  Bit definition for FDCAN_DBTP register  *******************/

+#define FDCAN_DBTP_DSJW_Pos       (0U)

+#define FDCAN_DBTP_DSJW_Msk       (0xFUL << FDCAN_DBTP_DSJW_Pos)               /*!< 0x0000000F */

+#define FDCAN_DBTP_DSJW           FDCAN_DBTP_DSJW_Msk                          /*!<Synchronization Jump Width              */

+#define FDCAN_DBTP_DTSEG2_Pos     (4U)

+#define FDCAN_DBTP_DTSEG2_Msk     (0xFUL << FDCAN_DBTP_DTSEG2_Pos)             /*!< 0x000000F0 */

+#define FDCAN_DBTP_DTSEG2         FDCAN_DBTP_DTSEG2_Msk                        /*!<Data time segment after sample point    */

+#define FDCAN_DBTP_DTSEG1_Pos     (8U)

+#define FDCAN_DBTP_DTSEG1_Msk     (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)            /*!< 0x00001F00 */

+#define FDCAN_DBTP_DTSEG1         FDCAN_DBTP_DTSEG1_Msk                        /*!<Data time segment before sample point   */

+#define FDCAN_DBTP_DBRP_Pos       (16U)

+#define FDCAN_DBTP_DBRP_Msk       (0x1FUL << FDCAN_DBTP_DBRP_Pos)              /*!< 0x001F0000 */

+#define FDCAN_DBTP_DBRP           FDCAN_DBTP_DBRP_Msk                          /*!<Data BIt Rate Prescaler                 */

+#define FDCAN_DBTP_TDC_Pos        (23U)

+#define FDCAN_DBTP_TDC_Msk        (0x1UL << FDCAN_DBTP_TDC_Pos)                /*!< 0x00800000 */

+#define FDCAN_DBTP_TDC            FDCAN_DBTP_TDC_Msk                           /*!<Transceiver Delay Compensation          */

+

+/*****************  Bit definition for FDCAN_TEST register  *******************/

+#define FDCAN_TEST_LBCK_Pos       (4U)

+#define FDCAN_TEST_LBCK_Msk       (0x1UL << FDCAN_TEST_LBCK_Pos)               /*!< 0x00000010 */

+#define FDCAN_TEST_LBCK           FDCAN_TEST_LBCK_Msk                          /*!<Loop Back mode                           */

+#define FDCAN_TEST_TX_Pos         (5U)

+#define FDCAN_TEST_TX_Msk         (0x3UL << FDCAN_TEST_TX_Pos)                 /*!< 0x00000060 */

+#define FDCAN_TEST_TX             FDCAN_TEST_TX_Msk                            /*!<Control of Transmit Pin                  */

+#define FDCAN_TEST_RX_Pos         (7U)

+#define FDCAN_TEST_RX_Msk         (0x1UL << FDCAN_TEST_RX_Pos)                 /*!< 0x00000080 */

+#define FDCAN_TEST_RX             FDCAN_TEST_RX_Msk                            /*!<Receive Pin                              */

+

+/*****************  Bit definition for FDCAN_RWD register  ********************/

+#define FDCAN_RWD_WDC_Pos         (0U)

+#define FDCAN_RWD_WDC_Msk         (0xFFUL << FDCAN_RWD_WDC_Pos)                /*!< 0x000000FF */

+#define FDCAN_RWD_WDC             FDCAN_RWD_WDC_Msk                            /*!<Watchdog configuration                   */

+#define FDCAN_RWD_WDV_Pos         (8U)

+#define FDCAN_RWD_WDV_Msk         (0xFFUL << FDCAN_RWD_WDV_Pos)                /*!< 0x0000FF00 */

+#define FDCAN_RWD_WDV             FDCAN_RWD_WDV_Msk                            /*!<Watchdog value                           */

+

+/*****************  Bit definition for FDCAN_CCCR register  ********************/

+#define FDCAN_CCCR_INIT_Pos       (0U)

+#define FDCAN_CCCR_INIT_Msk       (0x1UL << FDCAN_CCCR_INIT_Pos)               /*!< 0x00000001 */

+#define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!<Initialization                           */

+#define FDCAN_CCCR_CCE_Pos        (1U)

+#define FDCAN_CCCR_CCE_Msk        (0x1UL << FDCAN_CCCR_CCE_Pos)                /*!< 0x00000002 */

+#define FDCAN_CCCR_CCE            FDCAN_CCCR_CCE_Msk                           /*!<Configuration Change Enable              */

+#define FDCAN_CCCR_ASM_Pos        (2U)

+#define FDCAN_CCCR_ASM_Msk        (0x1UL << FDCAN_CCCR_ASM_Pos)                /*!< 0x00000004 */

+#define FDCAN_CCCR_ASM            FDCAN_CCCR_ASM_Msk                           /*!<ASM Restricted Operation Mode            */

+#define FDCAN_CCCR_CSA_Pos        (3U)

+#define FDCAN_CCCR_CSA_Msk        (0x1UL << FDCAN_CCCR_CSA_Pos)                /*!< 0x00000008 */

+#define FDCAN_CCCR_CSA            FDCAN_CCCR_CSA_Msk                           /*!<Clock Stop Acknowledge                   */

+#define FDCAN_CCCR_CSR_Pos        (4U)

+#define FDCAN_CCCR_CSR_Msk        (0x1UL << FDCAN_CCCR_CSR_Pos)                /*!< 0x00000010 */

+#define FDCAN_CCCR_CSR            FDCAN_CCCR_CSR_Msk                           /*!<Clock Stop Request                       */

+#define FDCAN_CCCR_MON_Pos        (5U)

+#define FDCAN_CCCR_MON_Msk        (0x1UL << FDCAN_CCCR_MON_Pos)                /*!< 0x00000020 */

+#define FDCAN_CCCR_MON            FDCAN_CCCR_MON_Msk                           /*!<Bus Monitoring Mode                      */

+#define FDCAN_CCCR_DAR_Pos        (6U)

+#define FDCAN_CCCR_DAR_Msk        (0x1UL << FDCAN_CCCR_DAR_Pos)                /*!< 0x00000040 */

+#define FDCAN_CCCR_DAR            FDCAN_CCCR_DAR_Msk                           /*!<Disable Automatic Retransmission         */

+#define FDCAN_CCCR_TEST_Pos       (7U)

+#define FDCAN_CCCR_TEST_Msk       (0x1UL << FDCAN_CCCR_TEST_Pos)               /*!< 0x00000080 */

+#define FDCAN_CCCR_TEST           FDCAN_CCCR_TEST_Msk                          /*!<Test Mode Enable                         */

+#define FDCAN_CCCR_FDOE_Pos       (8U)

+#define FDCAN_CCCR_FDOE_Msk       (0x1UL << FDCAN_CCCR_FDOE_Pos)               /*!< 0x00000100 */

+#define FDCAN_CCCR_FDOE           FDCAN_CCCR_FDOE_Msk                          /*!<FD Operation Enable                      */

+#define FDCAN_CCCR_BRSE_Pos       (9U)

+#define FDCAN_CCCR_BRSE_Msk       (0x1UL << FDCAN_CCCR_BRSE_Pos)               /*!< 0x00000200 */

+#define FDCAN_CCCR_BRSE           FDCAN_CCCR_BRSE_Msk                          /*!<FDCAN Bit Rate Switching                 */

+#define FDCAN_CCCR_PXHD_Pos       (12U)

+#define FDCAN_CCCR_PXHD_Msk       (0x1UL << FDCAN_CCCR_PXHD_Pos)               /*!< 0x00001000 */

+#define FDCAN_CCCR_PXHD           FDCAN_CCCR_PXHD_Msk                          /*!<Protocol Exception Handling Disable      */

+#define FDCAN_CCCR_EFBI_Pos       (13U)

+#define FDCAN_CCCR_EFBI_Msk       (0x1UL << FDCAN_CCCR_EFBI_Pos)               /*!< 0x00002000 */

+#define FDCAN_CCCR_EFBI           FDCAN_CCCR_EFBI_Msk                          /*!<Edge Filtering during Bus Integration    */

+#define FDCAN_CCCR_TXP_Pos        (14U)

+#define FDCAN_CCCR_TXP_Msk        (0x1UL << FDCAN_CCCR_TXP_Pos)                /*!< 0x00004000 */

+#define FDCAN_CCCR_TXP            FDCAN_CCCR_TXP_Msk                           /*!<Two CAN bit times Pause                  */

+#define FDCAN_CCCR_NISO_Pos       (15U)

+#define FDCAN_CCCR_NISO_Msk       (0x1UL << FDCAN_CCCR_NISO_Pos)               /*!< 0x00008000 */

+#define FDCAN_CCCR_NISO           FDCAN_CCCR_NISO_Msk                          /*!<Non ISO Operation                        */

+

+/*****************  Bit definition for FDCAN_NBTP register  ********************/

+#define FDCAN_NBTP_NTSEG2_Pos     (0U)

+#define FDCAN_NBTP_NTSEG2_Msk     (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)            /*!< 0x0000007F */

+#define FDCAN_NBTP_NTSEG2         FDCAN_NBTP_NTSEG2_Msk                        /*!<Nominal Time segment after sample point  */

+#define FDCAN_NBTP_NTSEG1_Pos     (8U)

+#define FDCAN_NBTP_NTSEG1_Msk     (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)            /*!< 0x0000FF00 */

+#define FDCAN_NBTP_NTSEG1         FDCAN_NBTP_NTSEG1_Msk                        /*!<Nominal Time segment before sample point */

+#define FDCAN_NBTP_NBRP_Pos       (16U)

+#define FDCAN_NBTP_NBRP_Msk       (0x1FFUL << FDCAN_NBTP_NBRP_Pos)             /*!< 0x01FF0000 */

+#define FDCAN_NBTP_NBRP           FDCAN_NBTP_NBRP_Msk                          /*!<Bit Rate Prescaler                       */

+#define FDCAN_NBTP_NSJW_Pos       (25U)

+#define FDCAN_NBTP_NSJW_Msk       (0x7FUL << FDCAN_NBTP_NSJW_Pos)              /*!< 0xFE000000 */

+#define FDCAN_NBTP_NSJW           FDCAN_NBTP_NSJW_Msk                          /*!<Nominal (Re)Synchronization Jump Width   */

+

+/*****************  Bit definition for FDCAN_TSCC register  ********************/

+#define FDCAN_TSCC_TSS_Pos        (0U)

+#define FDCAN_TSCC_TSS_Msk        (0x3UL << FDCAN_TSCC_TSS_Pos)                /*!< 0x00000003 */

+#define FDCAN_TSCC_TSS            FDCAN_TSCC_TSS_Msk                           /*!<Timestamp Select                         */

+#define FDCAN_TSCC_TCP_Pos        (16U)

+#define FDCAN_TSCC_TCP_Msk        (0xFUL << FDCAN_TSCC_TCP_Pos)                /*!< 0x000F0000 */

+#define FDCAN_TSCC_TCP            FDCAN_TSCC_TCP_Msk                           /*!<Timestamp Counter Prescaler              */

+

+/*****************  Bit definition for FDCAN_TSCV register  ********************/

+#define FDCAN_TSCV_TSC_Pos        (0U)

+#define FDCAN_TSCV_TSC_Msk        (0xFFFFUL << FDCAN_TSCV_TSC_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TSCV_TSC            FDCAN_TSCV_TSC_Msk                           /*!<Timestamp Counter                        */

+

+/*****************  Bit definition for FDCAN_TOCC register  ********************/

+#define FDCAN_TOCC_ETOC_Pos       (0U)

+#define FDCAN_TOCC_ETOC_Msk       (0x1UL << FDCAN_TOCC_ETOC_Pos)               /*!< 0x00000001 */

+#define FDCAN_TOCC_ETOC           FDCAN_TOCC_ETOC_Msk                          /*!<Enable Timeout Counter                   */

+#define FDCAN_TOCC_TOS_Pos        (1U)

+#define FDCAN_TOCC_TOS_Msk        (0x3UL << FDCAN_TOCC_TOS_Pos)                /*!< 0x00000006 */

+#define FDCAN_TOCC_TOS            FDCAN_TOCC_TOS_Msk                           /*!<Timeout Select                           */

+#define FDCAN_TOCC_TOP_Pos        (16U)

+#define FDCAN_TOCC_TOP_Msk        (0xFFFFUL << FDCAN_TOCC_TOP_Pos)             /*!< 0xFFFF0000 */

+#define FDCAN_TOCC_TOP            FDCAN_TOCC_TOP_Msk                           /*!<Timeout Period                           */

+

+/*****************  Bit definition for FDCAN_TOCV register  ********************/

+#define FDCAN_TOCV_TOC_Pos        (0U)

+#define FDCAN_TOCV_TOC_Msk        (0xFFFFUL << FDCAN_TOCV_TOC_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TOCV_TOC            FDCAN_TOCV_TOC_Msk                           /*!<Timeout Counter                          */

+

+/*****************  Bit definition for FDCAN_ECR register  *********************/

+#define FDCAN_ECR_TEC_Pos         (0U)

+#define FDCAN_ECR_TEC_Msk         (0xFUL << FDCAN_ECR_TEC_Pos)                 /*!< 0x0000000F */

+#define FDCAN_ECR_TEC             FDCAN_ECR_TEC_Msk                            /*!<Transmit Error Counter                   */

+#define FDCAN_ECR_REC_Pos         (8U)

+#define FDCAN_ECR_REC_Msk         (0x7FUL << FDCAN_ECR_REC_Pos)                /*!< 0x00007F00 */

+#define FDCAN_ECR_REC             FDCAN_ECR_REC_Msk                            /*!<Receive Error Counter                    */

+#define FDCAN_ECR_RP_Pos          (15U)

+#define FDCAN_ECR_RP_Msk          (0x1UL << FDCAN_ECR_RP_Pos)                  /*!< 0x00008000 */

+#define FDCAN_ECR_RP              FDCAN_ECR_RP_Msk                             /*!<Receive Error Passive                    */

+#define FDCAN_ECR_CEL_Pos         (16U)

+#define FDCAN_ECR_CEL_Msk         (0xFFUL << FDCAN_ECR_CEL_Pos)                /*!< 0x00FF0000 */

+#define FDCAN_ECR_CEL             FDCAN_ECR_CEL_Msk                            /*!<CAN Error Logging                        */

+

+/*****************  Bit definition for FDCAN_PSR register  *********************/

+#define FDCAN_PSR_LEC_Pos         (0U)

+#define FDCAN_PSR_LEC_Msk         (0x7UL << FDCAN_PSR_LEC_Pos)                 /*!< 0x00000007 */

+#define FDCAN_PSR_LEC             FDCAN_PSR_LEC_Msk                            /*!<Last Error Code                          */

+#define FDCAN_PSR_ACT_Pos         (3U)

+#define FDCAN_PSR_ACT_Msk         (0x3UL << FDCAN_PSR_ACT_Pos)                 /*!< 0x00000018 */

+#define FDCAN_PSR_ACT             FDCAN_PSR_ACT_Msk                            /*!<Activity                                 */

+#define FDCAN_PSR_EP_Pos          (5U)

+#define FDCAN_PSR_EP_Msk          (0x1UL << FDCAN_PSR_EP_Pos)                  /*!< 0x00000020 */

+#define FDCAN_PSR_EP              FDCAN_PSR_EP_Msk                             /*!<Error Passive                            */

+#define FDCAN_PSR_EW_Pos          (6U)

+#define FDCAN_PSR_EW_Msk          (0x1UL << FDCAN_PSR_EW_Pos)                  /*!< 0x00000040 */

+#define FDCAN_PSR_EW              FDCAN_PSR_EW_Msk                             /*!<Warning Status                           */

+#define FDCAN_PSR_BO_Pos          (7U)

+#define FDCAN_PSR_BO_Msk          (0x1UL << FDCAN_PSR_BO_Pos)                  /*!< 0x00000080 */

+#define FDCAN_PSR_BO              FDCAN_PSR_BO_Msk                             /*!<Bus_Off Status                           */

+#define FDCAN_PSR_DLEC_Pos        (8U)

+#define FDCAN_PSR_DLEC_Msk        (0x7UL << FDCAN_PSR_DLEC_Pos)                /*!< 0x00000700 */

+#define FDCAN_PSR_DLEC            FDCAN_PSR_DLEC_Msk                           /*!<Data Last Error Code                     */

+#define FDCAN_PSR_RESI_Pos        (11U)

+#define FDCAN_PSR_RESI_Msk        (0x1UL << FDCAN_PSR_RESI_Pos)                /*!< 0x00000800 */

+#define FDCAN_PSR_RESI            FDCAN_PSR_RESI_Msk                           /*!<ESI flag of last received FDCAN Message  */

+#define FDCAN_PSR_RBRS_Pos        (12U)

+#define FDCAN_PSR_RBRS_Msk        (0x1UL << FDCAN_PSR_RBRS_Pos)                /*!< 0x00001000 */

+#define FDCAN_PSR_RBRS            FDCAN_PSR_RBRS_Msk                           /*!<BRS flag of last received FDCAN Message  */

+#define FDCAN_PSR_REDL_Pos        (13U)

+#define FDCAN_PSR_REDL_Msk        (0x1UL << FDCAN_PSR_REDL_Pos)                /*!< 0x00002000 */

+#define FDCAN_PSR_REDL            FDCAN_PSR_REDL_Msk                           /*!<Received FDCAN Message                   */

+#define FDCAN_PSR_PXE_Pos         (14U)

+#define FDCAN_PSR_PXE_Msk         (0x1UL << FDCAN_PSR_PXE_Pos)                 /*!< 0x00004000 */

+#define FDCAN_PSR_PXE             FDCAN_PSR_PXE_Msk                            /*!<Protocol Exception Event                 */

+#define FDCAN_PSR_TDCV_Pos        (16U)

+#define FDCAN_PSR_TDCV_Msk        (0x7FUL << FDCAN_PSR_TDCV_Pos)               /*!< 0x007F0000 */

+#define FDCAN_PSR_TDCV            FDCAN_PSR_TDCV_Msk                           /*!<Transmitter Delay Compensation Value     */

+

+/*****************  Bit definition for FDCAN_TDCR register  ********************/

+#define FDCAN_TDCR_TDCF_Pos       (0U)

+#define FDCAN_TDCR_TDCF_Msk       (0x7FUL << FDCAN_TDCR_TDCF_Pos)              /*!< 0x0000007F */

+#define FDCAN_TDCR_TDCF           FDCAN_TDCR_TDCF_Msk                          /*!<Transmitter Delay Compensation Filter    */

+#define FDCAN_TDCR_TDCO_Pos       (8U)

+#define FDCAN_TDCR_TDCO_Msk       (0x7FUL << FDCAN_TDCR_TDCO_Pos)              /*!< 0x00007F00 */

+#define FDCAN_TDCR_TDCO           FDCAN_TDCR_TDCO_Msk                          /*!<Transmitter Delay Compensation Offset    */

+

+/*****************  Bit definition for FDCAN_IR register  **********************/

+#define FDCAN_IR_RF0N_Pos         (0U)

+#define FDCAN_IR_RF0N_Msk         (0x1UL << FDCAN_IR_RF0N_Pos)                 /*!< 0x00000001 */

+#define FDCAN_IR_RF0N             FDCAN_IR_RF0N_Msk                            /*!<Rx FIFO 0 New Message                    */

+#define FDCAN_IR_RF0W_Pos         (1U)

+#define FDCAN_IR_RF0W_Msk         (0x1UL << FDCAN_IR_RF0W_Pos)                 /*!< 0x00000002 */

+#define FDCAN_IR_RF0W             FDCAN_IR_RF0W_Msk                            /*!<Rx FIFO 0 Watermark Reached              */

+#define FDCAN_IR_RF0F_Pos         (2U)

+#define FDCAN_IR_RF0F_Msk         (0x1UL << FDCAN_IR_RF0F_Pos)                 /*!< 0x00000004 */

+#define FDCAN_IR_RF0F             FDCAN_IR_RF0F_Msk                            /*!<Rx FIFO 0 Full                           */

+#define FDCAN_IR_RF0L_Pos         (3U)

+#define FDCAN_IR_RF0L_Msk         (0x1UL << FDCAN_IR_RF0L_Pos)                 /*!< 0x00000008 */

+#define FDCAN_IR_RF0L             FDCAN_IR_RF0L_Msk                            /*!<Rx FIFO 0 Message Lost                   */

+#define FDCAN_IR_RF1N_Pos         (4U)

+#define FDCAN_IR_RF1N_Msk         (0x1UL << FDCAN_IR_RF1N_Pos)                 /*!< 0x00000010 */

+#define FDCAN_IR_RF1N             FDCAN_IR_RF1N_Msk                            /*!<Rx FIFO 1 New Message                    */

+#define FDCAN_IR_RF1W_Pos         (5U)

+#define FDCAN_IR_RF1W_Msk         (0x1UL << FDCAN_IR_RF1W_Pos)                 /*!< 0x00000020 */

+#define FDCAN_IR_RF1W             FDCAN_IR_RF1W_Msk                            /*!<Rx FIFO 1 Watermark Reached              */

+#define FDCAN_IR_RF1F_Pos         (6U)

+#define FDCAN_IR_RF1F_Msk         (0x1UL << FDCAN_IR_RF1F_Pos)                 /*!< 0x00000040 */

+#define FDCAN_IR_RF1F             FDCAN_IR_RF1F_Msk                            /*!<Rx FIFO 1 Full                           */

+#define FDCAN_IR_RF1L_Pos         (7U)

+#define FDCAN_IR_RF1L_Msk         (0x1UL << FDCAN_IR_RF1L_Pos)                 /*!< 0x00000080 */

+#define FDCAN_IR_RF1L             FDCAN_IR_RF1L_Msk                            /*!<Rx FIFO 1 Message Lost                   */

+#define FDCAN_IR_HPM_Pos          (8U)

+#define FDCAN_IR_HPM_Msk          (0x1UL << FDCAN_IR_HPM_Pos)                  /*!< 0x00000100 */

+#define FDCAN_IR_HPM              FDCAN_IR_HPM_Msk                             /*!<High Priority Message                    */

+#define FDCAN_IR_TC_Pos           (9U)

+#define FDCAN_IR_TC_Msk           (0x1UL << FDCAN_IR_TC_Pos)                   /*!< 0x00000200 */

+#define FDCAN_IR_TC               FDCAN_IR_TC_Msk                              /*!<Transmission Completed                   */

+#define FDCAN_IR_TCF_Pos          (10U)

+#define FDCAN_IR_TCF_Msk          (0x1UL << FDCAN_IR_TCF_Pos)                  /*!< 0x00000400 */

+#define FDCAN_IR_TCF              FDCAN_IR_TCF_Msk                             /*!<Transmission Cancellation Finished       */

+#define FDCAN_IR_TFE_Pos          (11U)

+#define FDCAN_IR_TFE_Msk          (0x1UL << FDCAN_IR_TFE_Pos)                  /*!< 0x00000800 */

+#define FDCAN_IR_TFE              FDCAN_IR_TFE_Msk                             /*!<Tx FIFO Empty                            */

+#define FDCAN_IR_TEFN_Pos         (12U)

+#define FDCAN_IR_TEFN_Msk         (0x1UL << FDCAN_IR_TEFN_Pos)                 /*!< 0x00001000 */

+#define FDCAN_IR_TEFN             FDCAN_IR_TEFN_Msk                            /*!<Tx Event FIFO New Entry                  */

+#define FDCAN_IR_TEFW_Pos         (13U)

+#define FDCAN_IR_TEFW_Msk         (0x1UL << FDCAN_IR_TEFW_Pos)                 /*!< 0x00002000 */

+#define FDCAN_IR_TEFW             FDCAN_IR_TEFW_Msk                            /*!<Tx Event FIFO Watermark Reached          */

+#define FDCAN_IR_TEFF_Pos         (14U)

+#define FDCAN_IR_TEFF_Msk         (0x1UL << FDCAN_IR_TEFF_Pos)                 /*!< 0x00004000 */

+#define FDCAN_IR_TEFF             FDCAN_IR_TEFF_Msk                            /*!<Tx Event FIFO Full                       */

+#define FDCAN_IR_TEFL_Pos         (15U)

+#define FDCAN_IR_TEFL_Msk         (0x1UL << FDCAN_IR_TEFL_Pos)                 /*!< 0x00008000 */

+#define FDCAN_IR_TEFL             FDCAN_IR_TEFL_Msk                            /*!<Tx Event FIFO Element Lost               */

+#define FDCAN_IR_TSW_Pos          (16U)

+#define FDCAN_IR_TSW_Msk          (0x1UL << FDCAN_IR_TSW_Pos)                  /*!< 0x00010000 */

+#define FDCAN_IR_TSW              FDCAN_IR_TSW_Msk                             /*!<Timestamp Wraparound                     */

+#define FDCAN_IR_MRAF_Pos         (17U)

+#define FDCAN_IR_MRAF_Msk         (0x1UL << FDCAN_IR_MRAF_Pos)                 /*!< 0x00020000 */

+#define FDCAN_IR_MRAF             FDCAN_IR_MRAF_Msk                            /*!<Message RAM Access Failure               */

+#define FDCAN_IR_TOO_Pos          (18U)

+#define FDCAN_IR_TOO_Msk          (0x1UL << FDCAN_IR_TOO_Pos)                  /*!< 0x00040000 */

+#define FDCAN_IR_TOO              FDCAN_IR_TOO_Msk                             /*!<Timeout Occurred                         */

+#define FDCAN_IR_DRX_Pos          (19U)

+#define FDCAN_IR_DRX_Msk          (0x1UL << FDCAN_IR_DRX_Pos)                  /*!< 0x00080000 */

+#define FDCAN_IR_DRX              FDCAN_IR_DRX_Msk                             /*!<Message stored to Dedicated Rx Buffer    */

+#define FDCAN_IR_ELO_Pos          (22U)

+#define FDCAN_IR_ELO_Msk          (0x1UL << FDCAN_IR_ELO_Pos)                  /*!< 0x00400000 */

+#define FDCAN_IR_ELO              FDCAN_IR_ELO_Msk                             /*!<Error Logging Overflow                   */

+#define FDCAN_IR_EP_Pos           (23U)

+#define FDCAN_IR_EP_Msk           (0x1UL << FDCAN_IR_EP_Pos)                   /*!< 0x00800000 */

+#define FDCAN_IR_EP               FDCAN_IR_EP_Msk                              /*!<Error Passive                            */

+#define FDCAN_IR_EW_Pos           (24U)

+#define FDCAN_IR_EW_Msk           (0x1UL << FDCAN_IR_EW_Pos)                   /*!< 0x01000000 */

+#define FDCAN_IR_EW               FDCAN_IR_EW_Msk                              /*!<Warning Status                           */

+#define FDCAN_IR_BO_Pos           (25U)

+#define FDCAN_IR_BO_Msk           (0x1UL << FDCAN_IR_BO_Pos)                   /*!< 0x02000000 */

+#define FDCAN_IR_BO               FDCAN_IR_BO_Msk                              /*!<Bus_Off Status                           */

+#define FDCAN_IR_WDI_Pos          (26U)

+#define FDCAN_IR_WDI_Msk          (0x1UL << FDCAN_IR_WDI_Pos)                  /*!< 0x04000000 */

+#define FDCAN_IR_WDI              FDCAN_IR_WDI_Msk                             /*!<Watchdog Interrupt                       */

+#define FDCAN_IR_PEA_Pos          (27U)

+#define FDCAN_IR_PEA_Msk          (0x1UL << FDCAN_IR_PEA_Pos)                  /*!< 0x08000000 */

+#define FDCAN_IR_PEA              FDCAN_IR_PEA_Msk                             /*!<Protocol Error in Arbitration Phase      */

+#define FDCAN_IR_PED_Pos          (28U)

+#define FDCAN_IR_PED_Msk          (0x1UL << FDCAN_IR_PED_Pos)                  /*!< 0x10000000 */

+#define FDCAN_IR_PED              FDCAN_IR_PED_Msk                             /*!<Protocol Error in Data Phase             */

+#define FDCAN_IR_ARA_Pos          (29U)

+#define FDCAN_IR_ARA_Msk          (0x1UL << FDCAN_IR_ARA_Pos)                  /*!< 0x20000000 */

+#define FDCAN_IR_ARA              FDCAN_IR_ARA_Msk                             /*!<Access to Reserved Address               */

+

+/*****************  Bit definition for FDCAN_IE register  **********************/

+#define FDCAN_IE_RF0NE_Pos        (0U)

+#define FDCAN_IE_RF0NE_Msk        (0x1UL << FDCAN_IE_RF0NE_Pos)                /*!< 0x00000001 */

+#define FDCAN_IE_RF0NE            FDCAN_IE_RF0NE_Msk                           /*!<Rx FIFO 0 New Message Enable                 */

+#define FDCAN_IE_RF0WE_Pos        (1U)

+#define FDCAN_IE_RF0WE_Msk        (0x1UL << FDCAN_IE_RF0WE_Pos)                /*!< 0x00000002 */

+#define FDCAN_IE_RF0WE            FDCAN_IE_RF0WE_Msk                           /*!<Rx FIFO 0 Watermark Reached Enable           */

+#define FDCAN_IE_RF0FE_Pos        (2U)

+#define FDCAN_IE_RF0FE_Msk        (0x1UL << FDCAN_IE_RF0FE_Pos)                /*!< 0x00000004 */

+#define FDCAN_IE_RF0FE            FDCAN_IE_RF0FE_Msk                           /*!<Rx FIFO 0 Full Enable                        */

+#define FDCAN_IE_RF0LE_Pos        (3U)

+#define FDCAN_IE_RF0LE_Msk        (0x1UL << FDCAN_IE_RF0LE_Pos)                /*!< 0x00000008 */

+#define FDCAN_IE_RF0LE            FDCAN_IE_RF0LE_Msk                           /*!<Rx FIFO 0 Message Lost Enable                */

+#define FDCAN_IE_RF1NE_Pos        (4U)

+#define FDCAN_IE_RF1NE_Msk        (0x1UL << FDCAN_IE_RF1NE_Pos)                /*!< 0x00000010 */

+#define FDCAN_IE_RF1NE            FDCAN_IE_RF1NE_Msk                           /*!<Rx FIFO 1 New Message Enable                 */

+#define FDCAN_IE_RF1WE_Pos        (5U)

+#define FDCAN_IE_RF1WE_Msk        (0x1UL << FDCAN_IE_RF1WE_Pos)                /*!< 0x00000020 */

+#define FDCAN_IE_RF1WE            FDCAN_IE_RF1WE_Msk                           /*!<Rx FIFO 1 Watermark Reached Enable           */

+#define FDCAN_IE_RF1FE_Pos        (6U)

+#define FDCAN_IE_RF1FE_Msk        (0x1UL << FDCAN_IE_RF1FE_Pos)                /*!< 0x00000040 */

+#define FDCAN_IE_RF1FE            FDCAN_IE_RF1FE_Msk                           /*!<Rx FIFO 1 Full Enable                        */

+#define FDCAN_IE_RF1LE_Pos        (7U)

+#define FDCAN_IE_RF1LE_Msk        (0x1UL << FDCAN_IE_RF1LE_Pos)                /*!< 0x00000080 */

+#define FDCAN_IE_RF1LE            FDCAN_IE_RF1LE_Msk                           /*!<Rx FIFO 1 Message Lost Enable                */

+#define FDCAN_IE_HPME_Pos         (8U)

+#define FDCAN_IE_HPME_Msk         (0x1UL << FDCAN_IE_HPME_Pos)                 /*!< 0x00000100 */

+#define FDCAN_IE_HPME             FDCAN_IE_HPME_Msk                            /*!<High Priority Message Enable                 */

+#define FDCAN_IE_TCE_Pos          (9U)

+#define FDCAN_IE_TCE_Msk          (0x1UL << FDCAN_IE_TCE_Pos)                  /*!< 0x00000200 */

+#define FDCAN_IE_TCE              FDCAN_IE_TCE_Msk                             /*!<Transmission Completed Enable                */

+#define FDCAN_IE_TCFE_Pos         (10U)

+#define FDCAN_IE_TCFE_Msk         (0x1UL << FDCAN_IE_TCFE_Pos)                 /*!< 0x00000400 */

+#define FDCAN_IE_TCFE             FDCAN_IE_TCFE_Msk                            /*!<Transmission Cancellation Finished Enable    */

+#define FDCAN_IE_TFEE_Pos         (11U)

+#define FDCAN_IE_TFEE_Msk         (0x1UL << FDCAN_IE_TFEE_Pos)                 /*!< 0x00000800 */

+#define FDCAN_IE_TFEE             FDCAN_IE_TFEE_Msk                            /*!<Tx FIFO Empty Enable                         */

+#define FDCAN_IE_TEFNE_Pos        (12U)

+#define FDCAN_IE_TEFNE_Msk        (0x1UL << FDCAN_IE_TEFNE_Pos)                /*!< 0x00001000 */

+#define FDCAN_IE_TEFNE            FDCAN_IE_TEFNE_Msk                           /*!<Tx Event FIFO New Entry Enable               */

+#define FDCAN_IE_TEFWE_Pos        (13U)

+#define FDCAN_IE_TEFWE_Msk        (0x1UL << FDCAN_IE_TEFWE_Pos)                /*!< 0x00002000 */

+#define FDCAN_IE_TEFWE            FDCAN_IE_TEFWE_Msk                           /*!<Tx Event FIFO Watermark Reached Enable       */

+#define FDCAN_IE_TEFFE_Pos        (14U)

+#define FDCAN_IE_TEFFE_Msk        (0x1UL << FDCAN_IE_TEFFE_Pos)                /*!< 0x00004000 */

+#define FDCAN_IE_TEFFE            FDCAN_IE_TEFFE_Msk                           /*!<Tx Event FIFO Full Enable                    */

+#define FDCAN_IE_TEFLE_Pos        (15U)

+#define FDCAN_IE_TEFLE_Msk        (0x1UL << FDCAN_IE_TEFLE_Pos)                /*!< 0x00008000 */

+#define FDCAN_IE_TEFLE            FDCAN_IE_TEFLE_Msk                           /*!<Tx Event FIFO Element Lost Enable            */

+#define FDCAN_IE_TSWE_Pos         (16U)

+#define FDCAN_IE_TSWE_Msk         (0x1UL << FDCAN_IE_TSWE_Pos)                 /*!< 0x00010000 */

+#define FDCAN_IE_TSWE             FDCAN_IE_TSWE_Msk                            /*!<Timestamp Wraparound Enable                  */

+#define FDCAN_IE_MRAFE_Pos        (17U)

+#define FDCAN_IE_MRAFE_Msk        (0x1UL << FDCAN_IE_MRAFE_Pos)                /*!< 0x00020000 */

+#define FDCAN_IE_MRAFE            FDCAN_IE_MRAFE_Msk                           /*!<Message RAM Access Failure Enable            */

+#define FDCAN_IE_TOOE_Pos         (18U)

+#define FDCAN_IE_TOOE_Msk         (0x1UL << FDCAN_IE_TOOE_Pos)                 /*!< 0x00040000 */

+#define FDCAN_IE_TOOE             FDCAN_IE_TOOE_Msk                            /*!<Timeout Occurred Enable                      */

+#define FDCAN_IE_DRXE_Pos         (19U)

+#define FDCAN_IE_DRXE_Msk         (0x1UL << FDCAN_IE_DRXE_Pos)                 /*!< 0x00080000 */

+#define FDCAN_IE_DRXE             FDCAN_IE_DRXE_Msk                            /*!<Message stored to Dedicated Rx Buffer Enable */

+#define FDCAN_IE_BECE_Pos         (20U)

+#define FDCAN_IE_BECE_Msk         (0x1UL << FDCAN_IE_BECE_Pos)                 /*!< 0x00100000 */

+#define FDCAN_IE_BECE             FDCAN_IE_BECE_Msk                            /*!<Bit Error Corrected Interrupt Enable         */

+#define FDCAN_IE_BEUE_Pos         (21U)

+#define FDCAN_IE_BEUE_Msk         (0x1UL << FDCAN_IE_BEUE_Pos)                 /*!< 0x00200000 */

+#define FDCAN_IE_BEUE             FDCAN_IE_BEUE_Msk                            /*!<Bit Error Uncorrected Interrupt Enable       */

+#define FDCAN_IE_ELOE_Pos         (22U)

+#define FDCAN_IE_ELOE_Msk         (0x1UL << FDCAN_IE_ELOE_Pos)                 /*!< 0x00400000 */

+#define FDCAN_IE_ELOE             FDCAN_IE_ELOE_Msk                            /*!<Error Logging Overflow Enable                */

+#define FDCAN_IE_EPE_Pos          (23U)

+#define FDCAN_IE_EPE_Msk          (0x1UL << FDCAN_IE_EPE_Pos)                  /*!< 0x00800000 */

+#define FDCAN_IE_EPE              FDCAN_IE_EPE_Msk                             /*!<Error Passive Enable                         */

+#define FDCAN_IE_EWE_Pos          (24U)

+#define FDCAN_IE_EWE_Msk          (0x1UL << FDCAN_IE_EWE_Pos)                  /*!< 0x01000000 */

+#define FDCAN_IE_EWE              FDCAN_IE_EWE_Msk                             /*!<Warning Status Enable                        */

+#define FDCAN_IE_BOE_Pos          (25U)

+#define FDCAN_IE_BOE_Msk          (0x1UL << FDCAN_IE_BOE_Pos)                  /*!< 0x02000000 */

+#define FDCAN_IE_BOE              FDCAN_IE_BOE_Msk                             /*!<Bus_Off Status Enable                        */

+#define FDCAN_IE_WDIE_Pos         (26U)

+#define FDCAN_IE_WDIE_Msk         (0x1UL << FDCAN_IE_WDIE_Pos)                 /*!< 0x04000000 */

+#define FDCAN_IE_WDIE             FDCAN_IE_WDIE_Msk                            /*!<Watchdog Interrupt Enable                    */

+#define FDCAN_IE_PEAE_Pos         (27U)

+#define FDCAN_IE_PEAE_Msk         (0x1UL << FDCAN_IE_PEAE_Pos)                 /*!< 0x08000000 */

+#define FDCAN_IE_PEAE             FDCAN_IE_PEAE_Msk                            /*!<Protocol Error in Arbitration Phase Enable   */

+#define FDCAN_IE_PEDE_Pos         (28U)

+#define FDCAN_IE_PEDE_Msk         (0x1UL << FDCAN_IE_PEDE_Pos)                 /*!< 0x10000000 */

+#define FDCAN_IE_PEDE             FDCAN_IE_PEDE_Msk                            /*!<Protocol Error in Data Phase Enable          */

+#define FDCAN_IE_ARAE_Pos         (29U)

+#define FDCAN_IE_ARAE_Msk         (0x1UL << FDCAN_IE_ARAE_Pos)                 /*!< 0x20000000 */

+#define FDCAN_IE_ARAE             FDCAN_IE_ARAE_Msk                            /*!<Access to Reserved Address Enable            */

+

+/*****************  Bit definition for FDCAN_ILS register  **********************/

+#define FDCAN_ILS_RF0NL_Pos       (0U)

+#define FDCAN_ILS_RF0NL_Msk       (0x1UL << FDCAN_ILS_RF0NL_Pos)               /*!< 0x00000001 */

+#define FDCAN_ILS_RF0NL           FDCAN_ILS_RF0NL_Msk                          /*!<Rx FIFO 0 New Message Line                  */

+#define FDCAN_ILS_RF0WL_Pos       (1U)

+#define FDCAN_ILS_RF0WL_Msk       (0x1UL << FDCAN_ILS_RF0WL_Pos)               /*!< 0x00000002 */

+#define FDCAN_ILS_RF0WL           FDCAN_ILS_RF0WL_Msk                          /*!<Rx FIFO 0 Watermark Reached Line            */

+#define FDCAN_ILS_RF0FL_Pos       (2U)

+#define FDCAN_ILS_RF0FL_Msk       (0x1UL << FDCAN_ILS_RF0FL_Pos)               /*!< 0x00000004 */

+#define FDCAN_ILS_RF0FL           FDCAN_ILS_RF0FL_Msk                          /*!<Rx FIFO 0 Full Line                         */

+#define FDCAN_ILS_RF0LL_Pos       (3U)

+#define FDCAN_ILS_RF0LL_Msk       (0x1UL << FDCAN_ILS_RF0LL_Pos)               /*!< 0x00000008 */

+#define FDCAN_ILS_RF0LL           FDCAN_ILS_RF0LL_Msk                          /*!<Rx FIFO 0 Message Lost Line                 */

+#define FDCAN_ILS_RF1NL_Pos       (4U)

+#define FDCAN_ILS_RF1NL_Msk       (0x1UL << FDCAN_ILS_RF1NL_Pos)               /*!< 0x00000010 */

+#define FDCAN_ILS_RF1NL           FDCAN_ILS_RF1NL_Msk                          /*!<Rx FIFO 1 New Message Line                  */

+#define FDCAN_ILS_RF1WL_Pos       (5U)

+#define FDCAN_ILS_RF1WL_Msk       (0x1UL << FDCAN_ILS_RF1WL_Pos)               /*!< 0x00000020 */

+#define FDCAN_ILS_RF1WL           FDCAN_ILS_RF1WL_Msk                          /*!<Rx FIFO 1 Watermark Reached Line            */

+#define FDCAN_ILS_RF1FL_Pos       (6U)

+#define FDCAN_ILS_RF1FL_Msk       (0x1UL << FDCAN_ILS_RF1FL_Pos)               /*!< 0x00000040 */

+#define FDCAN_ILS_RF1FL           FDCAN_ILS_RF1FL_Msk                          /*!<Rx FIFO 1 Full Line                         */

+#define FDCAN_ILS_RF1LL_Pos       (7U)

+#define FDCAN_ILS_RF1LL_Msk       (0x1UL << FDCAN_ILS_RF1LL_Pos)               /*!< 0x00000080 */

+#define FDCAN_ILS_RF1LL           FDCAN_ILS_RF1LL_Msk                          /*!<Rx FIFO 1 Message Lost Line                 */

+#define FDCAN_ILS_HPML_Pos        (8U)

+#define FDCAN_ILS_HPML_Msk        (0x1UL << FDCAN_ILS_HPML_Pos)                /*!< 0x00000100 */

+#define FDCAN_ILS_HPML            FDCAN_ILS_HPML_Msk                           /*!<High Priority Message Line                  */

+#define FDCAN_ILS_TCL_Pos         (9U)

+#define FDCAN_ILS_TCL_Msk         (0x1UL << FDCAN_ILS_TCL_Pos)                 /*!< 0x00000200 */

+#define FDCAN_ILS_TCL             FDCAN_ILS_TCL_Msk                            /*!<Transmission Completed Line                 */

+#define FDCAN_ILS_TCFL_Pos        (10U)

+#define FDCAN_ILS_TCFL_Msk        (0x1UL << FDCAN_ILS_TCFL_Pos)                /*!< 0x00000400 */

+#define FDCAN_ILS_TCFL            FDCAN_ILS_TCFL_Msk                           /*!<Transmission Cancellation Finished Line     */

+#define FDCAN_ILS_TFEL_Pos        (11U)

+#define FDCAN_ILS_TFEL_Msk        (0x1UL << FDCAN_ILS_TFEL_Pos)                /*!< 0x00000800 */

+#define FDCAN_ILS_TFEL            FDCAN_ILS_TFEL_Msk                           /*!<Tx FIFO Empty Line                          */

+#define FDCAN_ILS_TEFNL_Pos       (12U)

+#define FDCAN_ILS_TEFNL_Msk       (0x1UL << FDCAN_ILS_TEFNL_Pos)               /*!< 0x00001000 */

+#define FDCAN_ILS_TEFNL           FDCAN_ILS_TEFNL_Msk                          /*!<Tx Event FIFO New Entry Line                */

+#define FDCAN_ILS_TEFWL_Pos       (13U)

+#define FDCAN_ILS_TEFWL_Msk       (0x1UL << FDCAN_ILS_TEFWL_Pos)               /*!< 0x00002000 */

+#define FDCAN_ILS_TEFWL           FDCAN_ILS_TEFWL_Msk                          /*!<Tx Event FIFO Watermark Reached Line        */

+#define FDCAN_ILS_TEFFL_Pos       (14U)

+#define FDCAN_ILS_TEFFL_Msk       (0x1UL << FDCAN_ILS_TEFFL_Pos)               /*!< 0x00004000 */

+#define FDCAN_ILS_TEFFL           FDCAN_ILS_TEFFL_Msk                          /*!<Tx Event FIFO Full Line                     */

+#define FDCAN_ILS_TEFLL_Pos       (15U)

+#define FDCAN_ILS_TEFLL_Msk       (0x1UL << FDCAN_ILS_TEFLL_Pos)               /*!< 0x00008000 */

+#define FDCAN_ILS_TEFLL           FDCAN_ILS_TEFLL_Msk                          /*!<Tx Event FIFO Element Lost Line             */

+#define FDCAN_ILS_TSWL_Pos        (16U)

+#define FDCAN_ILS_TSWL_Msk        (0x1UL << FDCAN_ILS_TSWL_Pos)                /*!< 0x00010000 */

+#define FDCAN_ILS_TSWL            FDCAN_ILS_TSWL_Msk                           /*!<Timestamp Wraparound Line                   */

+#define FDCAN_ILS_MRAFE_Pos       (17U)

+#define FDCAN_ILS_MRAFE_Msk       (0x1UL << FDCAN_ILS_MRAFE_Pos)               /*!< 0x00020000 */

+#define FDCAN_ILS_MRAFE           FDCAN_ILS_MRAFE_Msk                          /*!<Message RAM Access Failure Line             */

+#define FDCAN_ILS_TOOE_Pos        (18U)

+#define FDCAN_ILS_TOOE_Msk        (0x1UL << FDCAN_ILS_TOOE_Pos)                /*!< 0x00040000 */

+#define FDCAN_ILS_TOOE            FDCAN_ILS_TOOE_Msk                           /*!<Timeout Occurred Line                       */

+#define FDCAN_ILS_DRXE_Pos        (19U)

+#define FDCAN_ILS_DRXE_Msk        (0x1UL << FDCAN_ILS_DRXE_Pos)                /*!< 0x00080000 */

+#define FDCAN_ILS_DRXE            FDCAN_ILS_DRXE_Msk                           /*!<Message stored to Dedicated Rx Buffer Line  */

+#define FDCAN_ILS_BECE_Pos        (20U)

+#define FDCAN_ILS_BECE_Msk        (0x1UL << FDCAN_ILS_BECE_Pos)                /*!< 0x00100000 */

+#define FDCAN_ILS_BECE            FDCAN_ILS_BECE_Msk                           /*!<Bit Error Corrected Interrupt Line          */

+#define FDCAN_ILS_BEUE_Pos        (21U)

+#define FDCAN_ILS_BEUE_Msk        (0x1UL << FDCAN_ILS_BEUE_Pos)                /*!< 0x00200000 */

+#define FDCAN_ILS_BEUE            FDCAN_ILS_BEUE_Msk                           /*!<Bit Error Uncorrected Interrupt Line        */

+#define FDCAN_ILS_ELOE_Pos        (22U)

+#define FDCAN_ILS_ELOE_Msk        (0x1UL << FDCAN_ILS_ELOE_Pos)                /*!< 0x00400000 */

+#define FDCAN_ILS_ELOE            FDCAN_ILS_ELOE_Msk                           /*!<Error Logging Overflow Line                 */

+#define FDCAN_ILS_EPE_Pos         (23U)

+#define FDCAN_ILS_EPE_Msk         (0x1UL << FDCAN_ILS_EPE_Pos)                 /*!< 0x00800000 */

+#define FDCAN_ILS_EPE             FDCAN_ILS_EPE_Msk                            /*!<Error Passive Line                          */

+#define FDCAN_ILS_EWE_Pos         (24U)

+#define FDCAN_ILS_EWE_Msk         (0x1UL << FDCAN_ILS_EWE_Pos)                 /*!< 0x01000000 */

+#define FDCAN_ILS_EWE             FDCAN_ILS_EWE_Msk                            /*!<Warning Status Line                         */

+#define FDCAN_ILS_BOE_Pos         (25U)

+#define FDCAN_ILS_BOE_Msk         (0x1UL << FDCAN_ILS_BOE_Pos)                 /*!< 0x02000000 */

+#define FDCAN_ILS_BOE             FDCAN_ILS_BOE_Msk                            /*!<Bus_Off Status Line                         */

+#define FDCAN_ILS_WDIE_Pos        (26U)

+#define FDCAN_ILS_WDIE_Msk        (0x1UL << FDCAN_ILS_WDIE_Pos)                /*!< 0x04000000 */

+#define FDCAN_ILS_WDIE            FDCAN_ILS_WDIE_Msk                           /*!<Watchdog Interrupt Line                     */

+#define FDCAN_ILS_PEAE_Pos        (27U)

+#define FDCAN_ILS_PEAE_Msk        (0x1UL << FDCAN_ILS_PEAE_Pos)                /*!< 0x08000000 */

+#define FDCAN_ILS_PEAE            FDCAN_ILS_PEAE_Msk                           /*!<Protocol Error in Arbitration Phase Line    */

+#define FDCAN_ILS_PEDE_Pos        (28U)

+#define FDCAN_ILS_PEDE_Msk        (0x1UL << FDCAN_ILS_PEDE_Pos)                /*!< 0x10000000 */

+#define FDCAN_ILS_PEDE            FDCAN_ILS_PEDE_Msk                           /*!<Protocol Error in Data Phase Line           */

+#define FDCAN_ILS_ARAE_Pos        (29U)

+#define FDCAN_ILS_ARAE_Msk        (0x1UL << FDCAN_ILS_ARAE_Pos)                /*!< 0x20000000 */

+#define FDCAN_ILS_ARAE            FDCAN_ILS_ARAE_Msk                           /*!<Access to Reserved Address Line             */

+

+/*****************  Bit definition for FDCAN_ILE register  **********************/

+#define FDCAN_ILE_EINT0_Pos       (0U)

+#define FDCAN_ILE_EINT0_Msk       (0x1UL << FDCAN_ILE_EINT0_Pos)               /*!< 0x00000001 */

+#define FDCAN_ILE_EINT0           FDCAN_ILE_EINT0_Msk                          /*!<Enable Interrupt Line 0                   */

+#define FDCAN_ILE_EINT1_Pos       (1U)

+#define FDCAN_ILE_EINT1_Msk       (0x1UL << FDCAN_ILE_EINT1_Pos)               /*!< 0x00000002 */

+#define FDCAN_ILE_EINT1           FDCAN_ILE_EINT1_Msk                          /*!<Enable Interrupt Line 1                   */

+

+/*****************  Bit definition for FDCAN_GFC register  **********************/

+#define FDCAN_GFC_RRFE_Pos        (0U)

+#define FDCAN_GFC_RRFE_Msk        (0x1UL << FDCAN_GFC_RRFE_Pos)                /*!< 0x00000001 */

+#define FDCAN_GFC_RRFE            FDCAN_GFC_RRFE_Msk                           /*!<Reject Remote Frames Extended             */

+#define FDCAN_GFC_RRFS_Pos        (1U)

+#define FDCAN_GFC_RRFS_Msk        (0x1UL << FDCAN_GFC_RRFS_Pos)                /*!< 0x00000002 */

+#define FDCAN_GFC_RRFS            FDCAN_GFC_RRFS_Msk                           /*!<Reject Remote Frames Standard             */

+#define FDCAN_GFC_ANFE_Pos        (2U)

+#define FDCAN_GFC_ANFE_Msk        (0x3UL << FDCAN_GFC_ANFE_Pos)                /*!< 0x0000000C */

+#define FDCAN_GFC_ANFE            FDCAN_GFC_ANFE_Msk                           /*!<Accept Non-matching Frames Extended       */

+#define FDCAN_GFC_ANFS_Pos        (4U)

+#define FDCAN_GFC_ANFS_Msk        (0x3UL << FDCAN_GFC_ANFS_Pos)                /*!< 0x00000030 */

+#define FDCAN_GFC_ANFS            FDCAN_GFC_ANFS_Msk                           /*!<Accept Non-matching Frames Standard       */

+

+/*****************  Bit definition for FDCAN_SIDFC register  ********************/

+#define FDCAN_SIDFC_FLSSA_Pos     (2U)

+#define FDCAN_SIDFC_FLSSA_Msk     (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)          /*!< 0x0000FFFC */

+#define FDCAN_SIDFC_FLSSA         FDCAN_SIDFC_FLSSA_Msk                        /*!<Filter List Standard Start Address        */

+#define FDCAN_SIDFC_LSS_Pos       (16U)

+#define FDCAN_SIDFC_LSS_Msk       (0xFFUL << FDCAN_SIDFC_LSS_Pos)              /*!< 0x00FF0000 */

+#define FDCAN_SIDFC_LSS           FDCAN_SIDFC_LSS_Msk                          /*!<List Size Standard                        */

+

+/*****************  Bit definition for FDCAN_XIDFC register  ********************/

+#define FDCAN_XIDFC_FLESA_Pos     (2U)

+#define FDCAN_XIDFC_FLESA_Msk     (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)          /*!< 0x0000FFFC */

+#define FDCAN_XIDFC_FLESA         FDCAN_XIDFC_FLESA_Msk                        /*!<Filter List Standard Start Address        */

+#define FDCAN_XIDFC_LSE_Pos       (16U)

+#define FDCAN_XIDFC_LSE_Msk       (0x7FUL << FDCAN_XIDFC_LSE_Pos)              /*!< 0x007F0000 */

+#define FDCAN_XIDFC_LSE           FDCAN_XIDFC_LSE_Msk                          /*!<List Size Extended                        */

+

+/*****************  Bit definition for FDCAN_XIDAM register  ********************/

+#define FDCAN_XIDAM_EIDM_Pos      (0U)

+#define FDCAN_XIDAM_EIDM_Msk      (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)       /*!< 0x1FFFFFFF */

+#define FDCAN_XIDAM_EIDM          FDCAN_XIDAM_EIDM_Msk                         /*!<Extended ID Mask                          */

+

+/*****************  Bit definition for FDCAN_HPMS register  *********************/

+#define FDCAN_HPMS_BIDX_Pos       (0U)

+#define FDCAN_HPMS_BIDX_Msk       (0x3FUL << FDCAN_HPMS_BIDX_Pos)              /*!< 0x0000003F */

+#define FDCAN_HPMS_BIDX           FDCAN_HPMS_BIDX_Msk                          /*!<Buffer Index                              */

+#define FDCAN_HPMS_MSI_Pos        (6U)

+#define FDCAN_HPMS_MSI_Msk        (0x3UL << FDCAN_HPMS_MSI_Pos)                /*!< 0x000000C0 */

+#define FDCAN_HPMS_MSI            FDCAN_HPMS_MSI_Msk                           /*!<Message Storage Indicator                 */

+#define FDCAN_HPMS_FIDX_Pos       (8U)

+#define FDCAN_HPMS_FIDX_Msk       (0x7FUL << FDCAN_HPMS_FIDX_Pos)              /*!< 0x00007F00 */

+#define FDCAN_HPMS_FIDX           FDCAN_HPMS_FIDX_Msk                          /*!<Filter Index                              */

+#define FDCAN_HPMS_FLST_Pos       (15U)

+#define FDCAN_HPMS_FLST_Msk       (0x1UL << FDCAN_HPMS_FLST_Pos)               /*!< 0x00008000 */

+#define FDCAN_HPMS_FLST           FDCAN_HPMS_FLST_Msk                          /*!<Filter List                               */

+

+/*****************  Bit definition for FDCAN_NDAT1 register  ********************/

+#define FDCAN_NDAT1_ND0_Pos       (0U)

+#define FDCAN_NDAT1_ND0_Msk       (0x1UL << FDCAN_NDAT1_ND0_Pos)               /*!< 0x00000001 */

+#define FDCAN_NDAT1_ND0           FDCAN_NDAT1_ND0_Msk                          /*!<New Data flag of Rx Buffer 0              */

+#define FDCAN_NDAT1_ND1_Pos       (1U)

+#define FDCAN_NDAT1_ND1_Msk       (0x1UL << FDCAN_NDAT1_ND1_Pos)               /*!< 0x00000002 */

+#define FDCAN_NDAT1_ND1           FDCAN_NDAT1_ND1_Msk                          /*!<New Data flag of Rx Buffer 1              */

+#define FDCAN_NDAT1_ND2_Pos       (2U)

+#define FDCAN_NDAT1_ND2_Msk       (0x1UL << FDCAN_NDAT1_ND2_Pos)               /*!< 0x00000004 */

+#define FDCAN_NDAT1_ND2           FDCAN_NDAT1_ND2_Msk                          /*!<New Data flag of Rx Buffer 2              */

+#define FDCAN_NDAT1_ND3_Pos       (3U)

+#define FDCAN_NDAT1_ND3_Msk       (0x1UL << FDCAN_NDAT1_ND3_Pos)               /*!< 0x00000008 */

+#define FDCAN_NDAT1_ND3           FDCAN_NDAT1_ND3_Msk                          /*!<New Data flag of Rx Buffer 3              */

+#define FDCAN_NDAT1_ND4_Pos       (4U)

+#define FDCAN_NDAT1_ND4_Msk       (0x1UL << FDCAN_NDAT1_ND4_Pos)               /*!< 0x00000010 */

+#define FDCAN_NDAT1_ND4           FDCAN_NDAT1_ND4_Msk                          /*!<New Data flag of Rx Buffer 4              */

+#define FDCAN_NDAT1_ND5_Pos       (5U)

+#define FDCAN_NDAT1_ND5_Msk       (0x1UL << FDCAN_NDAT1_ND5_Pos)               /*!< 0x00000020 */

+#define FDCAN_NDAT1_ND5           FDCAN_NDAT1_ND5_Msk                          /*!<New Data flag of Rx Buffer 5              */

+#define FDCAN_NDAT1_ND6_Pos       (6U)

+#define FDCAN_NDAT1_ND6_Msk       (0x1UL << FDCAN_NDAT1_ND6_Pos)               /*!< 0x00000040 */

+#define FDCAN_NDAT1_ND6           FDCAN_NDAT1_ND6_Msk                          /*!<New Data flag of Rx Buffer 6              */

+#define FDCAN_NDAT1_ND7_Pos       (7U)

+#define FDCAN_NDAT1_ND7_Msk       (0x1UL << FDCAN_NDAT1_ND7_Pos)               /*!< 0x00000080 */

+#define FDCAN_NDAT1_ND7           FDCAN_NDAT1_ND7_Msk                          /*!<New Data flag of Rx Buffer 7              */

+#define FDCAN_NDAT1_ND8_Pos       (8U)

+#define FDCAN_NDAT1_ND8_Msk       (0x1UL << FDCAN_NDAT1_ND8_Pos)               /*!< 0x00000100 */

+#define FDCAN_NDAT1_ND8           FDCAN_NDAT1_ND8_Msk                          /*!<New Data flag of Rx Buffer 8              */

+#define FDCAN_NDAT1_ND9_Pos       (9U)

+#define FDCAN_NDAT1_ND9_Msk       (0x1UL << FDCAN_NDAT1_ND9_Pos)               /*!< 0x00000200 */

+#define FDCAN_NDAT1_ND9           FDCAN_NDAT1_ND9_Msk                          /*!<New Data flag of Rx Buffer 9              */

+#define FDCAN_NDAT1_ND10_Pos      (10U)

+#define FDCAN_NDAT1_ND10_Msk      (0x1UL << FDCAN_NDAT1_ND10_Pos)              /*!< 0x00000400 */

+#define FDCAN_NDAT1_ND10          FDCAN_NDAT1_ND10_Msk                         /*!<New Data flag of Rx Buffer 10             */

+#define FDCAN_NDAT1_ND11_Pos      (11U)

+#define FDCAN_NDAT1_ND11_Msk      (0x1UL << FDCAN_NDAT1_ND11_Pos)              /*!< 0x00000800 */

+#define FDCAN_NDAT1_ND11          FDCAN_NDAT1_ND11_Msk                         /*!<New Data flag of Rx Buffer 11             */

+#define FDCAN_NDAT1_ND12_Pos      (12U)

+#define FDCAN_NDAT1_ND12_Msk      (0x1UL << FDCAN_NDAT1_ND12_Pos)              /*!< 0x00001000 */

+#define FDCAN_NDAT1_ND12          FDCAN_NDAT1_ND12_Msk                         /*!<New Data flag of Rx Buffer 12             */

+#define FDCAN_NDAT1_ND13_Pos      (13U)

+#define FDCAN_NDAT1_ND13_Msk      (0x1UL << FDCAN_NDAT1_ND13_Pos)              /*!< 0x00002000 */

+#define FDCAN_NDAT1_ND13          FDCAN_NDAT1_ND13_Msk                         /*!<New Data flag of Rx Buffer 13             */

+#define FDCAN_NDAT1_ND14_Pos      (14U)

+#define FDCAN_NDAT1_ND14_Msk      (0x1UL << FDCAN_NDAT1_ND14_Pos)              /*!< 0x00004000 */

+#define FDCAN_NDAT1_ND14          FDCAN_NDAT1_ND14_Msk                         /*!<New Data flag of Rx Buffer 14             */

+#define FDCAN_NDAT1_ND15_Pos      (15U)

+#define FDCAN_NDAT1_ND15_Msk      (0x1UL << FDCAN_NDAT1_ND15_Pos)              /*!< 0x00008000 */

+#define FDCAN_NDAT1_ND15          FDCAN_NDAT1_ND15_Msk                         /*!<New Data flag of Rx Buffer 15             */

+#define FDCAN_NDAT1_ND16_Pos      (16U)

+#define FDCAN_NDAT1_ND16_Msk      (0x1UL << FDCAN_NDAT1_ND16_Pos)              /*!< 0x00010000 */

+#define FDCAN_NDAT1_ND16          FDCAN_NDAT1_ND16_Msk                         /*!<New Data flag of Rx Buffer 16             */

+#define FDCAN_NDAT1_ND17_Pos      (17U)

+#define FDCAN_NDAT1_ND17_Msk      (0x1UL << FDCAN_NDAT1_ND17_Pos)              /*!< 0x00020000 */

+#define FDCAN_NDAT1_ND17          FDCAN_NDAT1_ND17_Msk                         /*!<New Data flag of Rx Buffer 17             */

+#define FDCAN_NDAT1_ND18_Pos      (18U)

+#define FDCAN_NDAT1_ND18_Msk      (0x1UL << FDCAN_NDAT1_ND18_Pos)              /*!< 0x00040000 */

+#define FDCAN_NDAT1_ND18          FDCAN_NDAT1_ND18_Msk                         /*!<New Data flag of Rx Buffer 18             */

+#define FDCAN_NDAT1_ND19_Pos      (19U)

+#define FDCAN_NDAT1_ND19_Msk      (0x1UL << FDCAN_NDAT1_ND19_Pos)              /*!< 0x00080000 */

+#define FDCAN_NDAT1_ND19          FDCAN_NDAT1_ND19_Msk                         /*!<New Data flag of Rx Buffer 19             */

+#define FDCAN_NDAT1_ND20_Pos      (20U)

+#define FDCAN_NDAT1_ND20_Msk      (0x1UL << FDCAN_NDAT1_ND20_Pos)              /*!< 0x00100000 */

+#define FDCAN_NDAT1_ND20          FDCAN_NDAT1_ND20_Msk                         /*!<New Data flag of Rx Buffer 20             */

+#define FDCAN_NDAT1_ND21_Pos      (21U)

+#define FDCAN_NDAT1_ND21_Msk      (0x1UL << FDCAN_NDAT1_ND21_Pos)              /*!< 0x00200000 */

+#define FDCAN_NDAT1_ND21          FDCAN_NDAT1_ND21_Msk                         /*!<New Data flag of Rx Buffer 21             */

+#define FDCAN_NDAT1_ND22_Pos      (22U)

+#define FDCAN_NDAT1_ND22_Msk      (0x1UL << FDCAN_NDAT1_ND22_Pos)              /*!< 0x00400000 */

+#define FDCAN_NDAT1_ND22          FDCAN_NDAT1_ND22_Msk                         /*!<New Data flag of Rx Buffer 22             */

+#define FDCAN_NDAT1_ND23_Pos      (23U)

+#define FDCAN_NDAT1_ND23_Msk      (0x1UL << FDCAN_NDAT1_ND23_Pos)              /*!< 0x00800000 */

+#define FDCAN_NDAT1_ND23          FDCAN_NDAT1_ND23_Msk                         /*!<New Data flag of Rx Buffer 23             */

+#define FDCAN_NDAT1_ND24_Pos      (24U)

+#define FDCAN_NDAT1_ND24_Msk      (0x1UL << FDCAN_NDAT1_ND24_Pos)              /*!< 0x01000000 */

+#define FDCAN_NDAT1_ND24          FDCAN_NDAT1_ND24_Msk                         /*!<New Data flag of Rx Buffer 24             */

+#define FDCAN_NDAT1_ND25_Pos      (25U)

+#define FDCAN_NDAT1_ND25_Msk      (0x1UL << FDCAN_NDAT1_ND25_Pos)              /*!< 0x02000000 */

+#define FDCAN_NDAT1_ND25          FDCAN_NDAT1_ND25_Msk                         /*!<New Data flag of Rx Buffer 25             */

+#define FDCAN_NDAT1_ND26_Pos      (26U)

+#define FDCAN_NDAT1_ND26_Msk      (0x1UL << FDCAN_NDAT1_ND26_Pos)              /*!< 0x04000000 */

+#define FDCAN_NDAT1_ND26          FDCAN_NDAT1_ND26_Msk                         /*!<New Data flag of Rx Buffer 26             */

+#define FDCAN_NDAT1_ND27_Pos      (27U)

+#define FDCAN_NDAT1_ND27_Msk      (0x1UL << FDCAN_NDAT1_ND27_Pos)              /*!< 0x08000000 */

+#define FDCAN_NDAT1_ND27          FDCAN_NDAT1_ND27_Msk                         /*!<New Data flag of Rx Buffer 27             */

+#define FDCAN_NDAT1_ND28_Pos      (28U)

+#define FDCAN_NDAT1_ND28_Msk      (0x1UL << FDCAN_NDAT1_ND28_Pos)              /*!< 0x10000000 */

+#define FDCAN_NDAT1_ND28          FDCAN_NDAT1_ND28_Msk                         /*!<New Data flag of Rx Buffer 28             */

+#define FDCAN_NDAT1_ND29_Pos      (29U)

+#define FDCAN_NDAT1_ND29_Msk      (0x1UL << FDCAN_NDAT1_ND29_Pos)              /*!< 0x20000000 */

+#define FDCAN_NDAT1_ND29          FDCAN_NDAT1_ND29_Msk                         /*!<New Data flag of Rx Buffer 29             */

+#define FDCAN_NDAT1_ND30_Pos      (30U)

+#define FDCAN_NDAT1_ND30_Msk      (0x1UL << FDCAN_NDAT1_ND30_Pos)              /*!< 0x40000000 */

+#define FDCAN_NDAT1_ND30          FDCAN_NDAT1_ND30_Msk                         /*!<New Data flag of Rx Buffer 30             */

+#define FDCAN_NDAT1_ND31_Pos      (31U)

+#define FDCAN_NDAT1_ND31_Msk      (0x1UL << FDCAN_NDAT1_ND31_Pos)              /*!< 0x80000000 */

+#define FDCAN_NDAT1_ND31          FDCAN_NDAT1_ND31_Msk                         /*!<New Data flag of Rx Buffer 31             */

+

+/*****************  Bit definition for FDCAN_NDAT2 register  ********************/

+#define FDCAN_NDAT2_ND32_Pos      (0U)

+#define FDCAN_NDAT2_ND32_Msk      (0x1UL << FDCAN_NDAT2_ND32_Pos)              /*!< 0x00000001 */

+#define FDCAN_NDAT2_ND32          FDCAN_NDAT2_ND32_Msk                         /*!<New Data flag of Rx Buffer 32             */

+#define FDCAN_NDAT2_ND33_Pos      (1U)

+#define FDCAN_NDAT2_ND33_Msk      (0x1UL << FDCAN_NDAT2_ND33_Pos)              /*!< 0x00000002 */

+#define FDCAN_NDAT2_ND33          FDCAN_NDAT2_ND33_Msk                         /*!<New Data flag of Rx Buffer 33             */

+#define FDCAN_NDAT2_ND34_Pos      (2U)

+#define FDCAN_NDAT2_ND34_Msk      (0x1UL << FDCAN_NDAT2_ND34_Pos)              /*!< 0x00000004 */

+#define FDCAN_NDAT2_ND34          FDCAN_NDAT2_ND34_Msk                         /*!<New Data flag of Rx Buffer 34             */

+#define FDCAN_NDAT2_ND35_Pos      (3U)

+#define FDCAN_NDAT2_ND35_Msk      (0x1UL << FDCAN_NDAT2_ND35_Pos)              /*!< 0x00000008 */

+#define FDCAN_NDAT2_ND35          FDCAN_NDAT2_ND35_Msk                         /*!<New Data flag of Rx Buffer 35             */

+#define FDCAN_NDAT2_ND36_Pos      (4U)

+#define FDCAN_NDAT2_ND36_Msk      (0x1UL << FDCAN_NDAT2_ND36_Pos)              /*!< 0x00000010 */

+#define FDCAN_NDAT2_ND36          FDCAN_NDAT2_ND36_Msk                         /*!<New Data flag of Rx Buffer 36             */

+#define FDCAN_NDAT2_ND37_Pos      (5U)

+#define FDCAN_NDAT2_ND37_Msk      (0x1UL << FDCAN_NDAT2_ND37_Pos)              /*!< 0x00000020 */

+#define FDCAN_NDAT2_ND37          FDCAN_NDAT2_ND37_Msk                         /*!<New Data flag of Rx Buffer 37             */

+#define FDCAN_NDAT2_ND38_Pos      (6U)

+#define FDCAN_NDAT2_ND38_Msk      (0x1UL << FDCAN_NDAT2_ND38_Pos)              /*!< 0x00000040 */

+#define FDCAN_NDAT2_ND38          FDCAN_NDAT2_ND38_Msk                         /*!<New Data flag of Rx Buffer 38             */

+#define FDCAN_NDAT2_ND39_Pos      (7U)

+#define FDCAN_NDAT2_ND39_Msk      (0x1UL << FDCAN_NDAT2_ND39_Pos)              /*!< 0x00000080 */

+#define FDCAN_NDAT2_ND39          FDCAN_NDAT2_ND39_Msk                         /*!<New Data flag of Rx Buffer 39             */

+#define FDCAN_NDAT2_ND40_Pos      (8U)

+#define FDCAN_NDAT2_ND40_Msk      (0x1UL << FDCAN_NDAT2_ND40_Pos)              /*!< 0x00000100 */

+#define FDCAN_NDAT2_ND40          FDCAN_NDAT2_ND40_Msk                         /*!<New Data flag of Rx Buffer 40             */

+#define FDCAN_NDAT2_ND41_Pos      (9U)

+#define FDCAN_NDAT2_ND41_Msk      (0x1UL << FDCAN_NDAT2_ND41_Pos)              /*!< 0x00000200 */

+#define FDCAN_NDAT2_ND41          FDCAN_NDAT2_ND41_Msk                         /*!<New Data flag of Rx Buffer 41             */

+#define FDCAN_NDAT2_ND42_Pos      (10U)

+#define FDCAN_NDAT2_ND42_Msk      (0x1UL << FDCAN_NDAT2_ND42_Pos)              /*!< 0x00000400 */

+#define FDCAN_NDAT2_ND42          FDCAN_NDAT2_ND42_Msk                         /*!<New Data flag of Rx Buffer 42             */

+#define FDCAN_NDAT2_ND43_Pos      (11U)

+#define FDCAN_NDAT2_ND43_Msk      (0x1UL << FDCAN_NDAT2_ND43_Pos)              /*!< 0x00000800 */

+#define FDCAN_NDAT2_ND43          FDCAN_NDAT2_ND43_Msk                         /*!<New Data flag of Rx Buffer 43             */

+#define FDCAN_NDAT2_ND44_Pos      (12U)

+#define FDCAN_NDAT2_ND44_Msk      (0x1UL << FDCAN_NDAT2_ND44_Pos)              /*!< 0x00001000 */

+#define FDCAN_NDAT2_ND44          FDCAN_NDAT2_ND44_Msk                         /*!<New Data flag of Rx Buffer 44             */

+#define FDCAN_NDAT2_ND45_Pos      (13U)

+#define FDCAN_NDAT2_ND45_Msk      (0x1UL << FDCAN_NDAT2_ND45_Pos)              /*!< 0x00002000 */

+#define FDCAN_NDAT2_ND45          FDCAN_NDAT2_ND45_Msk                         /*!<New Data flag of Rx Buffer 45             */

+#define FDCAN_NDAT2_ND46_Pos      (14U)

+#define FDCAN_NDAT2_ND46_Msk      (0x1UL << FDCAN_NDAT2_ND46_Pos)              /*!< 0x00004000 */

+#define FDCAN_NDAT2_ND46          FDCAN_NDAT2_ND46_Msk                         /*!<New Data flag of Rx Buffer 46             */

+#define FDCAN_NDAT2_ND47_Pos      (15U)

+#define FDCAN_NDAT2_ND47_Msk      (0x1UL << FDCAN_NDAT2_ND47_Pos)              /*!< 0x00008000 */

+#define FDCAN_NDAT2_ND47          FDCAN_NDAT2_ND47_Msk                         /*!<New Data flag of Rx Buffer 47             */

+#define FDCAN_NDAT2_ND48_Pos      (16U)

+#define FDCAN_NDAT2_ND48_Msk      (0x1UL << FDCAN_NDAT2_ND48_Pos)              /*!< 0x00010000 */

+#define FDCAN_NDAT2_ND48          FDCAN_NDAT2_ND48_Msk                         /*!<New Data flag of Rx Buffer 48             */

+#define FDCAN_NDAT2_ND49_Pos      (17U)

+#define FDCAN_NDAT2_ND49_Msk      (0x1UL << FDCAN_NDAT2_ND49_Pos)              /*!< 0x00020000 */

+#define FDCAN_NDAT2_ND49          FDCAN_NDAT2_ND49_Msk                         /*!<New Data flag of Rx Buffer 49             */

+#define FDCAN_NDAT2_ND50_Pos      (18U)

+#define FDCAN_NDAT2_ND50_Msk      (0x1UL << FDCAN_NDAT2_ND50_Pos)              /*!< 0x00040000 */

+#define FDCAN_NDAT2_ND50          FDCAN_NDAT2_ND50_Msk                         /*!<New Data flag of Rx Buffer 50             */

+#define FDCAN_NDAT2_ND51_Pos      (19U)

+#define FDCAN_NDAT2_ND51_Msk      (0x1UL << FDCAN_NDAT2_ND51_Pos)              /*!< 0x00080000 */

+#define FDCAN_NDAT2_ND51          FDCAN_NDAT2_ND51_Msk                         /*!<New Data flag of Rx Buffer 51             */

+#define FDCAN_NDAT2_ND52_Pos      (20U)

+#define FDCAN_NDAT2_ND52_Msk      (0x1UL << FDCAN_NDAT2_ND52_Pos)              /*!< 0x00100000 */

+#define FDCAN_NDAT2_ND52          FDCAN_NDAT2_ND52_Msk                         /*!<New Data flag of Rx Buffer 52             */

+#define FDCAN_NDAT2_ND53_Pos      (21U)

+#define FDCAN_NDAT2_ND53_Msk      (0x1UL << FDCAN_NDAT2_ND53_Pos)              /*!< 0x00200000 */

+#define FDCAN_NDAT2_ND53          FDCAN_NDAT2_ND53_Msk                         /*!<New Data flag of Rx Buffer 53             */

+#define FDCAN_NDAT2_ND54_Pos      (22U)

+#define FDCAN_NDAT2_ND54_Msk      (0x1UL << FDCAN_NDAT2_ND54_Pos)              /*!< 0x00400000 */

+#define FDCAN_NDAT2_ND54          FDCAN_NDAT2_ND54_Msk                         /*!<New Data flag of Rx Buffer 54             */

+#define FDCAN_NDAT2_ND55_Pos      (23U)

+#define FDCAN_NDAT2_ND55_Msk      (0x1UL << FDCAN_NDAT2_ND55_Pos)              /*!< 0x00800000 */

+#define FDCAN_NDAT2_ND55          FDCAN_NDAT2_ND55_Msk                         /*!<New Data flag of Rx Buffer 55             */

+#define FDCAN_NDAT2_ND56_Pos      (24U)

+#define FDCAN_NDAT2_ND56_Msk      (0x1UL << FDCAN_NDAT2_ND56_Pos)              /*!< 0x01000000 */

+#define FDCAN_NDAT2_ND56          FDCAN_NDAT2_ND56_Msk                         /*!<New Data flag of Rx Buffer 56             */

+#define FDCAN_NDAT2_ND57_Pos      (25U)

+#define FDCAN_NDAT2_ND57_Msk      (0x1UL << FDCAN_NDAT2_ND57_Pos)              /*!< 0x02000000 */

+#define FDCAN_NDAT2_ND57          FDCAN_NDAT2_ND57_Msk                         /*!<New Data flag of Rx Buffer 57             */

+#define FDCAN_NDAT2_ND58_Pos      (26U)

+#define FDCAN_NDAT2_ND58_Msk      (0x1UL << FDCAN_NDAT2_ND58_Pos)              /*!< 0x04000000 */

+#define FDCAN_NDAT2_ND58          FDCAN_NDAT2_ND58_Msk                         /*!<New Data flag of Rx Buffer 58             */

+#define FDCAN_NDAT2_ND59_Pos      (27U)

+#define FDCAN_NDAT2_ND59_Msk      (0x1UL << FDCAN_NDAT2_ND59_Pos)              /*!< 0x08000000 */

+#define FDCAN_NDAT2_ND59          FDCAN_NDAT2_ND59_Msk                         /*!<New Data flag of Rx Buffer 59             */

+#define FDCAN_NDAT2_ND60_Pos      (28U)

+#define FDCAN_NDAT2_ND60_Msk      (0x1UL << FDCAN_NDAT2_ND60_Pos)              /*!< 0x10000000 */

+#define FDCAN_NDAT2_ND60          FDCAN_NDAT2_ND60_Msk                         /*!<New Data flag of Rx Buffer 60             */

+#define FDCAN_NDAT2_ND61_Pos      (29U)

+#define FDCAN_NDAT2_ND61_Msk      (0x1UL << FDCAN_NDAT2_ND61_Pos)              /*!< 0x20000000 */

+#define FDCAN_NDAT2_ND61          FDCAN_NDAT2_ND61_Msk                         /*!<New Data flag of Rx Buffer 61             */

+#define FDCAN_NDAT2_ND62_Pos      (30U)

+#define FDCAN_NDAT2_ND62_Msk      (0x1UL << FDCAN_NDAT2_ND62_Pos)              /*!< 0x40000000 */

+#define FDCAN_NDAT2_ND62          FDCAN_NDAT2_ND62_Msk                         /*!<New Data flag of Rx Buffer 62             */

+#define FDCAN_NDAT2_ND63_Pos      (31U)

+#define FDCAN_NDAT2_ND63_Msk      (0x1UL << FDCAN_NDAT2_ND63_Pos)              /*!< 0x80000000 */

+#define FDCAN_NDAT2_ND63          FDCAN_NDAT2_ND63_Msk                         /*!<New Data flag of Rx Buffer 63             */

+

+/*****************  Bit definition for FDCAN_RXF0C register  ********************/

+#define FDCAN_RXF0C_F0SA_Pos      (2U)

+#define FDCAN_RXF0C_F0SA_Msk      (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_RXF0C_F0SA          FDCAN_RXF0C_F0SA_Msk                         /*!<Rx FIFO 0 Start Address                   */

+#define FDCAN_RXF0C_F0S_Pos       (16U)

+#define FDCAN_RXF0C_F0S_Msk       (0x7FUL << FDCAN_RXF0C_F0S_Pos)              /*!< 0x007F0000 */

+#define FDCAN_RXF0C_F0S           FDCAN_RXF0C_F0S_Msk                          /*!<Number of Rx FIFO 0 elements              */

+#define FDCAN_RXF0C_F0WM_Pos      (24U)

+#define FDCAN_RXF0C_F0WM_Msk      (0x7FUL << FDCAN_RXF0C_F0WM_Pos)             /*!< 0x7F000000 */

+#define FDCAN_RXF0C_F0WM          FDCAN_RXF0C_F0WM_Msk                         /*!<FIFO 0 Watermark                          */

+#define FDCAN_RXF0C_F0OM_Pos      (31U)

+#define FDCAN_RXF0C_F0OM_Msk      (0x1UL << FDCAN_RXF0C_F0OM_Pos)              /*!< 0x80000000 */

+#define FDCAN_RXF0C_F0OM          FDCAN_RXF0C_F0OM_Msk                         /*!<FIFO 0 Operation Mode                     */

+

+/*****************  Bit definition for FDCAN_RXF0S register  ********************/

+#define FDCAN_RXF0S_F0FL_Pos      (0U)

+#define FDCAN_RXF0S_F0FL_Msk      (0x7FUL << FDCAN_RXF0S_F0FL_Pos)             /*!< 0x0000007F */

+#define FDCAN_RXF0S_F0FL          FDCAN_RXF0S_F0FL_Msk                         /*!<Rx FIFO 0 Fill Level                      */

+#define FDCAN_RXF0S_F0GI_Pos      (8U)

+#define FDCAN_RXF0S_F0GI_Msk      (0x3FUL << FDCAN_RXF0S_F0GI_Pos)             /*!< 0x00003F00 */

+#define FDCAN_RXF0S_F0GI          FDCAN_RXF0S_F0GI_Msk                         /*!<Rx FIFO 0 Get Index                       */

+#define FDCAN_RXF0S_F0PI_Pos      (16U)

+#define FDCAN_RXF0S_F0PI_Msk      (0x3FUL << FDCAN_RXF0S_F0PI_Pos)             /*!< 0x003F0000 */

+#define FDCAN_RXF0S_F0PI          FDCAN_RXF0S_F0PI_Msk                         /*!<Rx FIFO 0 Put Index                       */

+#define FDCAN_RXF0S_F0F_Pos       (24U)

+#define FDCAN_RXF0S_F0F_Msk       (0x1UL << FDCAN_RXF0S_F0F_Pos)               /*!< 0x01000000 */

+#define FDCAN_RXF0S_F0F           FDCAN_RXF0S_F0F_Msk                          /*!<Rx FIFO 0 Full                            */

+#define FDCAN_RXF0S_RF0L_Pos      (25U)

+#define FDCAN_RXF0S_RF0L_Msk      (0x1UL << FDCAN_RXF0S_RF0L_Pos)              /*!< 0x02000000 */

+#define FDCAN_RXF0S_RF0L          FDCAN_RXF0S_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                    */

+

+/*****************  Bit definition for FDCAN_RXF0A register  ********************/

+#define FDCAN_RXF0A_F0AI_Pos      (0U)

+#define FDCAN_RXF0A_F0AI_Msk      (0x3FUL << FDCAN_RXF0A_F0AI_Pos)             /*!< 0x0000003F */

+#define FDCAN_RXF0A_F0AI          FDCAN_RXF0A_F0AI_Msk                         /*!<Rx FIFO 0 Acknowledge Index               */

+

+/*****************  Bit definition for FDCAN_RXBC register  ********************/

+#define FDCAN_RXBC_RBSA_Pos       (2U)

+#define FDCAN_RXBC_RBSA_Msk       (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)            /*!< 0x0000FFFC */

+#define FDCAN_RXBC_RBSA           FDCAN_RXBC_RBSA_Msk                          /*!<Rx Buffer Start Address                   */

+

+/*****************  Bit definition for FDCAN_RXF1C register  ********************/

+#define FDCAN_RXF1C_F1SA_Pos      (2U)

+#define FDCAN_RXF1C_F1SA_Msk      (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_RXF1C_F1SA          FDCAN_RXF1C_F1SA_Msk                         /*!<Rx FIFO 1 Start Address                   */

+#define FDCAN_RXF1C_F1S_Pos       (16U)

+#define FDCAN_RXF1C_F1S_Msk       (0x7FUL << FDCAN_RXF1C_F1S_Pos)              /*!< 0x007F0000 */

+#define FDCAN_RXF1C_F1S           FDCAN_RXF1C_F1S_Msk                          /*!<Number of Rx FIFO 1 elements              */

+#define FDCAN_RXF1C_F1WM_Pos      (24U)

+#define FDCAN_RXF1C_F1WM_Msk      (0x7FUL << FDCAN_RXF1C_F1WM_Pos)             /*!< 0x7F000000 */

+#define FDCAN_RXF1C_F1WM          FDCAN_RXF1C_F1WM_Msk                         /*!<Rx FIFO 1 Watermark                       */

+#define FDCAN_RXF1C_F1OM_Pos      (31U)

+#define FDCAN_RXF1C_F1OM_Msk      (0x1UL << FDCAN_RXF1C_F1OM_Pos)              /*!< 0x80000000 */

+#define FDCAN_RXF1C_F1OM          FDCAN_RXF1C_F1OM_Msk                         /*!<FIFO 1 Operation Mode                     */

+

+/*****************  Bit definition for FDCAN_RXF1S register  ********************/

+#define FDCAN_RXF1S_F1FL_Pos      (0U)

+#define FDCAN_RXF1S_F1FL_Msk      (0x7FUL << FDCAN_RXF1S_F1FL_Pos)             /*!< 0x0000007F */

+#define FDCAN_RXF1S_F1FL          FDCAN_RXF1S_F1FL_Msk                         /*!<Rx FIFO 1 Fill Level                      */

+#define FDCAN_RXF1S_F1GI_Pos      (8U)

+#define FDCAN_RXF1S_F1GI_Msk      (0x3FUL << FDCAN_RXF1S_F1GI_Pos)             /*!< 0x00003F00 */

+#define FDCAN_RXF1S_F1GI          FDCAN_RXF1S_F1GI_Msk                         /*!<Rx FIFO 1 Get Index                       */

+#define FDCAN_RXF1S_F1PI_Pos      (16U)

+#define FDCAN_RXF1S_F1PI_Msk      (0x3FUL << FDCAN_RXF1S_F1PI_Pos)             /*!< 0x003F0000 */

+#define FDCAN_RXF1S_F1PI          FDCAN_RXF1S_F1PI_Msk                         /*!<Rx FIFO 1 Put Index                       */

+#define FDCAN_RXF1S_F1F_Pos       (24U)

+#define FDCAN_RXF1S_F1F_Msk       (0x1UL << FDCAN_RXF1S_F1F_Pos)               /*!< 0x01000000 */

+#define FDCAN_RXF1S_F1F           FDCAN_RXF1S_F1F_Msk                          /*!<Rx FIFO 1 Full                            */

+#define FDCAN_RXF1S_RF1L_Pos      (25U)

+#define FDCAN_RXF1S_RF1L_Msk      (0x1UL << FDCAN_RXF1S_RF1L_Pos)              /*!< 0x02000000 */

+#define FDCAN_RXF1S_RF1L          FDCAN_RXF1S_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                    */

+

+/*****************  Bit definition for FDCAN_RXF1A register  ********************/

+#define FDCAN_RXF1A_F1AI_Pos      (0U)

+#define FDCAN_RXF1A_F1AI_Msk      (0x3FUL << FDCAN_RXF1A_F1AI_Pos)             /*!< 0x0000003F */

+#define FDCAN_RXF1A_F1AI          FDCAN_RXF1A_F1AI_Msk                         /*!<Rx FIFO 1 Acknowledge Index               */

+

+/*****************  Bit definition for FDCAN_RXESC register  ********************/

+#define FDCAN_RXESC_F0DS_Pos      (0U)

+#define FDCAN_RXESC_F0DS_Msk      (0x7UL << FDCAN_RXESC_F0DS_Pos)              /*!< 0x00000007 */

+#define FDCAN_RXESC_F0DS          FDCAN_RXESC_F0DS_Msk                         /*!<Rx FIFO 1 Data Field Size                 */

+#define FDCAN_RXESC_F1DS_Pos      (4U)

+#define FDCAN_RXESC_F1DS_Msk      (0x7UL << FDCAN_RXESC_F1DS_Pos)              /*!< 0x00000070 */

+#define FDCAN_RXESC_F1DS          FDCAN_RXESC_F1DS_Msk                         /*!<Rx FIFO 0 Data Field Size                 */

+#define FDCAN_RXESC_RBDS_Pos      (8U)

+#define FDCAN_RXESC_RBDS_Msk      (0x7UL << FDCAN_RXESC_RBDS_Pos)              /*!< 0x00000700 */

+#define FDCAN_RXESC_RBDS          FDCAN_RXESC_RBDS_Msk                         /*!<Rx Buffer Data Field Size                 */

+

+/*****************  Bit definition for FDCAN_TXBC register  *********************/

+#define FDCAN_TXBC_TBSA_Pos       (2U)

+#define FDCAN_TXBC_TBSA_Msk       (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)            /*!< 0x0000FFFC */

+#define FDCAN_TXBC_TBSA           FDCAN_TXBC_TBSA_Msk                          /*!<Tx Buffers Start Address                  */

+#define FDCAN_TXBC_NDTB_Pos       (16U)

+#define FDCAN_TXBC_NDTB_Msk       (0x3FUL << FDCAN_TXBC_NDTB_Pos)              /*!< 0x003F0000 */

+#define FDCAN_TXBC_NDTB           FDCAN_TXBC_NDTB_Msk                          /*!<Number of Dedicated Transmit Buffers      */

+#define FDCAN_TXBC_TFQS_Pos       (24U)

+#define FDCAN_TXBC_TFQS_Msk       (0x3FUL << FDCAN_TXBC_TFQS_Pos)              /*!< 0x3F000000 */

+#define FDCAN_TXBC_TFQS           FDCAN_TXBC_TFQS_Msk                          /*!<Transmit FIFO/Queue Size                  */

+#define FDCAN_TXBC_TFQM_Pos       (30U)

+#define FDCAN_TXBC_TFQM_Msk       (0x1UL << FDCAN_TXBC_TFQM_Pos)               /*!< 0x40000000 */

+#define FDCAN_TXBC_TFQM           FDCAN_TXBC_TFQM_Msk                          /*!<Tx FIFO/Queue Mode                        */

+

+/*****************  Bit definition for FDCAN_TXFQS register  *********************/

+#define FDCAN_TXFQS_TFFL_Pos      (0U)

+#define FDCAN_TXFQS_TFFL_Msk      (0x3FUL << FDCAN_TXFQS_TFFL_Pos)             /*!< 0x0000003F */

+#define FDCAN_TXFQS_TFFL          FDCAN_TXFQS_TFFL_Msk                         /*!<Tx FIFO Free Level                        */

+#define FDCAN_TXFQS_TFGI_Pos      (8U)

+#define FDCAN_TXFQS_TFGI_Msk      (0x1FUL << FDCAN_TXFQS_TFGI_Pos)             /*!< 0x00001F00 */

+#define FDCAN_TXFQS_TFGI          FDCAN_TXFQS_TFGI_Msk                         /*!<Tx FIFO Get Index                         */

+#define FDCAN_TXFQS_TFQPI_Pos     (16U)

+#define FDCAN_TXFQS_TFQPI_Msk     (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)            /*!< 0x001F0000 */

+#define FDCAN_TXFQS_TFQPI         FDCAN_TXFQS_TFQPI_Msk                        /*!<Tx FIFO/Queue Put Index                   */

+#define FDCAN_TXFQS_TFQF_Pos      (21U)

+#define FDCAN_TXFQS_TFQF_Msk      (0x1UL << FDCAN_TXFQS_TFQF_Pos)              /*!< 0x00200000 */

+#define FDCAN_TXFQS_TFQF          FDCAN_TXFQS_TFQF_Msk                         /*!<Tx FIFO/Queue Full                        */

+

+/*****************  Bit definition for FDCAN_TXESC register  *********************/

+#define FDCAN_TXESC_TBDS_Pos      (0U)

+#define FDCAN_TXESC_TBDS_Msk      (0x7UL << FDCAN_TXESC_TBDS_Pos)              /*!< 0x00000007 */

+#define FDCAN_TXESC_TBDS          FDCAN_TXESC_TBDS_Msk                         /*!<Tx Buffer Data Field Size                 */

+

+/*****************  Bit definition for FDCAN_TXBRP register  *********************/

+#define FDCAN_TXBRP_TRP_Pos       (0U)

+#define FDCAN_TXBRP_TRP_Msk       (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)        /*!< 0xFFFFFFFF */

+#define FDCAN_TXBRP_TRP           FDCAN_TXBRP_TRP_Msk                          /*!<Transmission Request Pending              */

+

+/*****************  Bit definition for FDCAN_TXBAR register  *********************/

+#define FDCAN_TXBAR_AR_Pos        (0U)

+#define FDCAN_TXBAR_AR_Msk        (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBAR_AR            FDCAN_TXBAR_AR_Msk                           /*!<Add Request                               */

+

+/*****************  Bit definition for FDCAN_TXBCR register  *********************/

+#define FDCAN_TXBCR_CR_Pos        (0U)

+#define FDCAN_TXBCR_CR_Msk        (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCR_CR            FDCAN_TXBCR_CR_Msk                           /*!<Cancellation Request                      */

+

+/*****************  Bit definition for FDCAN_TXBTO register  *********************/

+#define FDCAN_TXBTO_TO_Pos        (0U)

+#define FDCAN_TXBTO_TO_Msk        (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBTO_TO            FDCAN_TXBTO_TO_Msk                           /*!<Transmission Occurred                     */

+

+/*****************  Bit definition for FDCAN_TXBCF register  *********************/

+#define FDCAN_TXBCF_CF_Pos        (0U)

+#define FDCAN_TXBCF_CF_Msk        (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCF_CF            FDCAN_TXBCF_CF_Msk                           /*!<Cancellation Finished                     */

+

+/*****************  Bit definition for FDCAN_TXBTIE register  ********************/

+#define FDCAN_TXBTIE_TIE_Pos      (0U)

+#define FDCAN_TXBTIE_TIE_Msk      (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)       /*!< 0xFFFFFFFF */

+#define FDCAN_TXBTIE_TIE          FDCAN_TXBTIE_TIE_Msk                         /*!<Transmission Interrupt Enable             */

+

+/*****************  Bit definition for FDCAN_ TXBCIE register  *******************/

+#define FDCAN_TXBCIE_CFIE_Pos     (0U)

+#define FDCAN_TXBCIE_CFIE_Msk     (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)      /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCIE_CFIE         FDCAN_TXBCIE_CFIE_Msk                        /*!<Cancellation Finished Interrupt Enable    */

+

+/*****************  Bit definition for FDCAN_TXEFC register  *********************/

+#define FDCAN_TXEFC_EFSA_Pos      (2U)

+#define FDCAN_TXEFC_EFSA_Msk      (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_TXEFC_EFSA          FDCAN_TXEFC_EFSA_Msk                         /*!<Event FIFO Start Address                  */

+#define FDCAN_TXEFC_EFS_Pos       (16U)

+#define FDCAN_TXEFC_EFS_Msk       (0x3FUL << FDCAN_TXEFC_EFS_Pos)              /*!< 0x003F0000 */

+#define FDCAN_TXEFC_EFS           FDCAN_TXEFC_EFS_Msk                          /*!<Event FIFO Size                           */

+#define FDCAN_TXEFC_EFWM_Pos      (24U)

+#define FDCAN_TXEFC_EFWM_Msk      (0x3FUL << FDCAN_TXEFC_EFWM_Pos)             /*!< 0x3F000000 */

+#define FDCAN_TXEFC_EFWM          FDCAN_TXEFC_EFWM_Msk                         /*!<Event FIFO Watermark                      */

+

+/*****************  Bit definition for FDCAN_TXEFS register  *********************/

+#define FDCAN_TXEFS_EFFL_Pos      (0U)

+#define FDCAN_TXEFS_EFFL_Msk      (0x3FUL << FDCAN_TXEFS_EFFL_Pos)             /*!< 0x0000003F */

+#define FDCAN_TXEFS_EFFL          FDCAN_TXEFS_EFFL_Msk                         /*!<Event FIFO Fill Level                     */

+#define FDCAN_TXEFS_EFGI_Pos      (8U)

+#define FDCAN_TXEFS_EFGI_Msk      (0x1FUL << FDCAN_TXEFS_EFGI_Pos)             /*!< 0x00001F00 */

+#define FDCAN_TXEFS_EFGI          FDCAN_TXEFS_EFGI_Msk                         /*!<Event FIFO Get Index                      */

+#define FDCAN_TXEFS_EFPI_Pos      (16U)

+#define FDCAN_TXEFS_EFPI_Msk      (0x1FUL << FDCAN_TXEFS_EFPI_Pos)             /*!< 0x001F0000 */

+#define FDCAN_TXEFS_EFPI          FDCAN_TXEFS_EFPI_Msk                         /*!<Event FIFO Put Index                      */

+#define FDCAN_TXEFS_EFF_Pos       (24U)

+#define FDCAN_TXEFS_EFF_Msk       (0x1UL << FDCAN_TXEFS_EFF_Pos)               /*!< 0x01000000 */

+#define FDCAN_TXEFS_EFF           FDCAN_TXEFS_EFF_Msk                          /*!<Event FIFO Full                           */

+#define FDCAN_TXEFS_TEFL_Pos      (25U)

+#define FDCAN_TXEFS_TEFL_Msk      (0x1UL << FDCAN_TXEFS_TEFL_Pos)              /*!< 0x02000000 */

+#define FDCAN_TXEFS_TEFL          FDCAN_TXEFS_TEFL_Msk                         /*!<Tx Event FIFO Element Lost                */

+

+/*****************  Bit definition for FDCAN_TXEFA register  *********************/

+#define FDCAN_TXEFA_EFAI_Pos      (0U)

+#define FDCAN_TXEFA_EFAI_Msk      (0x1FUL << FDCAN_TXEFA_EFAI_Pos)             /*!< 0x0000001F */

+#define FDCAN_TXEFA_EFAI          FDCAN_TXEFA_EFAI_Msk                         /*!<Event FIFO Acknowledge Index              */

+

+/*****************  Bit definition for FDCAN_TTTMC register  *********************/

+#define FDCAN_TTTMC_TMSA_Pos      (2U)

+#define FDCAN_TTTMC_TMSA_Msk      (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_TTTMC_TMSA          FDCAN_TTTMC_TMSA_Msk                         /*!<Trigger Memory Start Address              */

+#define FDCAN_TTTMC_TME_Pos       (16U)

+#define FDCAN_TTTMC_TME_Msk       (0x7FUL << FDCAN_TTTMC_TME_Pos)              /*!< 0x007F0000 */

+#define FDCAN_TTTMC_TME           FDCAN_TTTMC_TME_Msk                          /*!<Trigger Memory Elements                   */

+

+/*****************  Bit definition for FDCAN_TTRMC register  *********************/

+#define FDCAN_TTRMC_RID_Pos       (0U)

+#define FDCAN_TTRMC_RID_Msk       (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)        /*!< 0x1FFFFFFF */

+#define FDCAN_TTRMC_RID           FDCAN_TTRMC_RID_Msk                          /*!<Reference Identifier                      */

+#define FDCAN_TTRMC_XTD_Pos       (30U)

+#define FDCAN_TTRMC_XTD_Msk       (0x1UL << FDCAN_TTRMC_XTD_Pos)               /*!< 0x40000000 */

+#define FDCAN_TTRMC_XTD           FDCAN_TTRMC_XTD_Msk                          /*!< Extended Identifier                      */

+#define FDCAN_TTRMC_RMPS_Pos      (31U)

+#define FDCAN_TTRMC_RMPS_Msk      (0x1UL << FDCAN_TTRMC_RMPS_Pos)              /*!< 0x80000000 */

+#define FDCAN_TTRMC_RMPS          FDCAN_TTRMC_RMPS_Msk                         /*!<Reference Message Payload Select          */

+

+/*****************  Bit definition for FDCAN_TTOCF register  *********************/

+#define FDCAN_TTOCF_OM_Pos        (0U)

+#define FDCAN_TTOCF_OM_Msk        (0x3UL << FDCAN_TTOCF_OM_Pos)                /*!< 0x00000003 */

+#define FDCAN_TTOCF_OM            FDCAN_TTOCF_OM_Msk                           /*!<Operation Mode                            */

+#define FDCAN_TTOCF_GEN_Pos       (3U)

+#define FDCAN_TTOCF_GEN_Msk       (0x1UL << FDCAN_TTOCF_GEN_Pos)               /*!< 0x00000008 */

+#define FDCAN_TTOCF_GEN           FDCAN_TTOCF_GEN_Msk                          /*!<Gap Enable                                */

+#define FDCAN_TTOCF_TM_Pos        (4U)

+#define FDCAN_TTOCF_TM_Msk        (0x1UL << FDCAN_TTOCF_TM_Pos)                /*!< 0x00000010 */

+#define FDCAN_TTOCF_TM            FDCAN_TTOCF_TM_Msk                           /*!<Time Master                               */

+#define FDCAN_TTOCF_LDSDL_Pos     (5U)

+#define FDCAN_TTOCF_LDSDL_Msk     (0x7UL << FDCAN_TTOCF_LDSDL_Pos)             /*!< 0x000000E0 */

+#define FDCAN_TTOCF_LDSDL         FDCAN_TTOCF_LDSDL_Msk                        /*!<LD of Synchronization Deviation Limit     */

+#define FDCAN_TTOCF_IRTO_Pos      (8U)

+#define FDCAN_TTOCF_IRTO_Msk      (0x7FUL << FDCAN_TTOCF_IRTO_Pos)             /*!< 0x00007F00 */

+#define FDCAN_TTOCF_IRTO          FDCAN_TTOCF_IRTO_Msk                         /*!<Initial Reference Trigger Offset          */

+#define FDCAN_TTOCF_EECS_Pos      (15U)

+#define FDCAN_TTOCF_EECS_Msk      (0x1UL << FDCAN_TTOCF_EECS_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTOCF_EECS          FDCAN_TTOCF_EECS_Msk                         /*!<Enable External Clock Synchronization     */

+#define FDCAN_TTOCF_AWL_Pos       (16U)

+#define FDCAN_TTOCF_AWL_Msk       (0xFFUL << FDCAN_TTOCF_AWL_Pos)              /*!< 0x00FF0000 */

+#define FDCAN_TTOCF_AWL           FDCAN_TTOCF_AWL_Msk                          /*!<Application Watchdog Limit                */

+#define FDCAN_TTOCF_EGTF_Pos      (24U)

+#define FDCAN_TTOCF_EGTF_Msk      (0x1UL << FDCAN_TTOCF_EGTF_Pos)              /*!< 0x01000000 */

+#define FDCAN_TTOCF_EGTF          FDCAN_TTOCF_EGTF_Msk                         /*!<Enable Global Time Filtering              */

+#define FDCAN_TTOCF_ECC_Pos       (25U)

+#define FDCAN_TTOCF_ECC_Msk       (0x1UL << FDCAN_TTOCF_ECC_Pos)               /*!< 0x02000000 */

+#define FDCAN_TTOCF_ECC           FDCAN_TTOCF_ECC_Msk                          /*!<Enable Clock Calibration                  */

+#define FDCAN_TTOCF_EVTP_Pos      (26U)

+#define FDCAN_TTOCF_EVTP_Msk      (0x1UL << FDCAN_TTOCF_EVTP_Pos)              /*!< 0x04000000 */

+#define FDCAN_TTOCF_EVTP          FDCAN_TTOCF_EVTP_Msk                         /*!<Event Trigger Polarity                    */

+

+/*****************  Bit definition for FDCAN_TTMLM register  *********************/

+#define FDCAN_TTMLM_CCM_Pos       (0U)

+#define FDCAN_TTMLM_CCM_Msk       (0x3FUL << FDCAN_TTMLM_CCM_Pos)              /*!< 0x0000003F */

+#define FDCAN_TTMLM_CCM           FDCAN_TTMLM_CCM_Msk                          /*!<Cycle Count Max                           */

+#define FDCAN_TTMLM_CSS_Pos       (6U)

+#define FDCAN_TTMLM_CSS_Msk       (0x3UL << FDCAN_TTMLM_CSS_Pos)               /*!< 0x000000C0 */

+#define FDCAN_TTMLM_CSS           FDCAN_TTMLM_CSS_Msk                          /*!<Cycle Start Synchronization               */

+#define FDCAN_TTMLM_TXEW_Pos      (8U)

+#define FDCAN_TTMLM_TXEW_Msk      (0xFUL << FDCAN_TTMLM_TXEW_Pos)              /*!< 0x00000F00 */

+#define FDCAN_TTMLM_TXEW          FDCAN_TTMLM_TXEW_Msk                         /*!<Tx Enable Window                          */

+#define FDCAN_TTMLM_ENTT_Pos      (16U)

+#define FDCAN_TTMLM_ENTT_Msk      (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)            /*!< 0x0FFF0000 */

+#define FDCAN_TTMLM_ENTT          FDCAN_TTMLM_ENTT_Msk                         /*!<Expected Number of Tx Triggers            */

+

+/*****************  Bit definition for FDCAN_TURCF register  *********************/

+#define FDCAN_TURCF_NCL_Pos       (0U)

+#define FDCAN_TURCF_NCL_Msk       (0xFFFFUL << FDCAN_TURCF_NCL_Pos)            /*!< 0x0000FFFF */

+#define FDCAN_TURCF_NCL           FDCAN_TURCF_NCL_Msk                          /*!<Numerator Configuration Low               */

+#define FDCAN_TURCF_DC_Pos        (16U)

+#define FDCAN_TURCF_DC_Msk        (0x3FFFUL << FDCAN_TURCF_DC_Pos)             /*!< 0x3FFF0000 */

+#define FDCAN_TURCF_DC            FDCAN_TURCF_DC_Msk                           /*!<Denominator Configuration                 */

+#define FDCAN_TURCF_ELT_Pos       (31U)

+#define FDCAN_TURCF_ELT_Msk       (0x1UL << FDCAN_TURCF_ELT_Pos)               /*!< 0x80000000 */

+#define FDCAN_TURCF_ELT           FDCAN_TURCF_ELT_Msk                          /*!<Enable Local Time                         */

+

+/*****************  Bit definition for FDCAN_TTOCN register  ********************/

+#define FDCAN_TTOCN_SGT_Pos       (0U)

+#define FDCAN_TTOCN_SGT_Msk       (0x1UL << FDCAN_TTOCN_SGT_Pos)               /*!< 0x00000001 */

+#define FDCAN_TTOCN_SGT           FDCAN_TTOCN_SGT_Msk                          /*!<Set Global time                           */

+#define FDCAN_TTOCN_ECS_Pos       (1U)

+#define FDCAN_TTOCN_ECS_Msk       (0x1UL << FDCAN_TTOCN_ECS_Pos)               /*!< 0x00000002 */

+#define FDCAN_TTOCN_ECS           FDCAN_TTOCN_ECS_Msk                          /*!<External Clock Synchronization            */

+#define FDCAN_TTOCN_SWP_Pos       (2U)

+#define FDCAN_TTOCN_SWP_Msk       (0x1UL << FDCAN_TTOCN_SWP_Pos)               /*!< 0x00000004 */

+#define FDCAN_TTOCN_SWP           FDCAN_TTOCN_SWP_Msk                          /*!<Stop Watch Polarity                       */

+#define FDCAN_TTOCN_SWS_Pos       (3U)

+#define FDCAN_TTOCN_SWS_Msk       (0x3UL << FDCAN_TTOCN_SWS_Pos)               /*!< 0x00000018 */

+#define FDCAN_TTOCN_SWS           FDCAN_TTOCN_SWS_Msk                          /*!<Stop Watch Source                         */

+#define FDCAN_TTOCN_RTIE_Pos      (5U)

+#define FDCAN_TTOCN_RTIE_Msk      (0x1UL << FDCAN_TTOCN_RTIE_Pos)              /*!< 0x00000020 */

+#define FDCAN_TTOCN_RTIE          FDCAN_TTOCN_RTIE_Msk                         /*!<Register Time Mark Interrupt Pulse Enable */

+#define FDCAN_TTOCN_TMC_Pos       (6U)

+#define FDCAN_TTOCN_TMC_Msk       (0x3UL << FDCAN_TTOCN_TMC_Pos)               /*!< 0x000000C0 */

+#define FDCAN_TTOCN_TMC           FDCAN_TTOCN_TMC_Msk                          /*!<Register Time Mark Compare                */

+#define FDCAN_TTOCN_TTIE_Pos      (8U)

+#define FDCAN_TTOCN_TTIE_Msk      (0x1UL << FDCAN_TTOCN_TTIE_Pos)              /*!< 0x00000100 */

+#define FDCAN_TTOCN_TTIE          FDCAN_TTOCN_TTIE_Msk                         /*!<Trigger Time Mark Interrupt Pulse Enable  */

+#define FDCAN_TTOCN_GCS_Pos       (9U)

+#define FDCAN_TTOCN_GCS_Msk       (0x1UL << FDCAN_TTOCN_GCS_Pos)               /*!< 0x00000200 */

+#define FDCAN_TTOCN_GCS           FDCAN_TTOCN_GCS_Msk                          /*!<Gap Control Select                        */

+#define FDCAN_TTOCN_FGP_Pos       (10U)

+#define FDCAN_TTOCN_FGP_Msk       (0x1UL << FDCAN_TTOCN_FGP_Pos)               /*!< 0x00000400 */

+#define FDCAN_TTOCN_FGP           FDCAN_TTOCN_FGP_Msk                          /*!<Finish Gap                                */

+#define FDCAN_TTOCN_TMG_Pos       (11U)

+#define FDCAN_TTOCN_TMG_Msk       (0x1UL << FDCAN_TTOCN_TMG_Pos)               /*!< 0x00000800 */

+#define FDCAN_TTOCN_TMG           FDCAN_TTOCN_TMG_Msk                          /*!<Time Mark Gap                             */

+#define FDCAN_TTOCN_NIG_Pos       (12U)

+#define FDCAN_TTOCN_NIG_Msk       (0x1UL << FDCAN_TTOCN_NIG_Pos)               /*!< 0x00001000 */

+#define FDCAN_TTOCN_NIG           FDCAN_TTOCN_NIG_Msk                          /*!<Next is Gap                               */

+#define FDCAN_TTOCN_ESCN_Pos      (13U)

+#define FDCAN_TTOCN_ESCN_Msk      (0x1UL << FDCAN_TTOCN_ESCN_Pos)              /*!< 0x00002000 */

+#define FDCAN_TTOCN_ESCN          FDCAN_TTOCN_ESCN_Msk                         /*!<External Synchronization Control          */

+#define FDCAN_TTOCN_LCKC_Pos      (15U)

+#define FDCAN_TTOCN_LCKC_Msk      (0x1UL << FDCAN_TTOCN_LCKC_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTOCN_LCKC          FDCAN_TTOCN_LCKC_Msk                         /*!<TT Operation Control Register Locked      */

+

+/*****************  Bit definition for FDCAN_TTGTP register  ********************/

+#define FDCAN_TTGTP_TP_Pos        (0U)

+#define FDCAN_TTGTP_TP_Msk        (0xFFFFUL << FDCAN_TTGTP_TP_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTGTP_TP            FDCAN_TTGTP_TP_Msk                           /*!<Time Preset                               */

+#define FDCAN_TTGTP_CTP_Pos       (16U)

+#define FDCAN_TTGTP_CTP_Msk       (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)            /*!< 0xFFFF0000 */

+#define FDCAN_TTGTP_CTP           FDCAN_TTGTP_CTP_Msk                          /*!<Cycle Time Target Phase                   */

+

+/*****************  Bit definition for FDCAN_TTTMK register  ********************/

+#define FDCAN_TTTMK_TM_Pos        (0U)

+#define FDCAN_TTTMK_TM_Msk        (0xFFFFUL << FDCAN_TTTMK_TM_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTTMK_TM            FDCAN_TTTMK_TM_Msk                           /*!<Time Mark                                 */

+#define FDCAN_TTTMK_TICC_Pos      (16U)

+#define FDCAN_TTTMK_TICC_Msk      (0x7FUL << FDCAN_TTTMK_TICC_Pos)             /*!< 0x007F0000 */

+#define FDCAN_TTTMK_TICC          FDCAN_TTTMK_TICC_Msk                         /*!<Time Mark Cycle Code                      */

+#define FDCAN_TTTMK_LCKM_Pos      (31U)

+#define FDCAN_TTTMK_LCKM_Msk      (0x1UL << FDCAN_TTTMK_LCKM_Pos)              /*!< 0x80000000 */

+#define FDCAN_TTTMK_LCKM          FDCAN_TTTMK_LCKM_Msk                         /*!<TT Time Mark Register Locked              */

+

+/*****************  Bit definition for FDCAN_TTIR register  ********************/

+#define FDCAN_TTIR_SBC_Pos        (0U)

+#define FDCAN_TTIR_SBC_Msk        (0x1UL << FDCAN_TTIR_SBC_Pos)                /*!< 0x00000001 */

+#define FDCAN_TTIR_SBC            FDCAN_TTIR_SBC_Msk                           /*!<Start of Basic Cycle                      */

+#define FDCAN_TTIR_SMC_Pos        (1U)

+#define FDCAN_TTIR_SMC_Msk        (0x1UL << FDCAN_TTIR_SMC_Pos)                /*!< 0x00000002 */

+#define FDCAN_TTIR_SMC            FDCAN_TTIR_SMC_Msk                           /*!<Start of Matrix Cycle                     */

+#define FDCAN_TTIR_CSM_Pos        (2U)

+#define FDCAN_TTIR_CSM_Msk        (0x1UL << FDCAN_TTIR_CSM_Pos)                /*!< 0x00000004 */

+#define FDCAN_TTIR_CSM            FDCAN_TTIR_CSM_Msk                           /*!<Change of Synchronization Mode            */

+#define FDCAN_TTIR_SOG_Pos        (3U)

+#define FDCAN_TTIR_SOG_Msk        (0x1UL << FDCAN_TTIR_SOG_Pos)                /*!< 0x00000008 */

+#define FDCAN_TTIR_SOG            FDCAN_TTIR_SOG_Msk                           /*!<Start of Gap                              */

+#define FDCAN_TTIR_RTMI_Pos       (4U)

+#define FDCAN_TTIR_RTMI_Msk       (0x1UL << FDCAN_TTIR_RTMI_Pos)               /*!< 0x00000010 */

+#define FDCAN_TTIR_RTMI           FDCAN_TTIR_RTMI_Msk                          /*!<Register Time Mark Interrupt              */

+#define FDCAN_TTIR_TTMI_Pos       (5U)

+#define FDCAN_TTIR_TTMI_Msk       (0x1UL << FDCAN_TTIR_TTMI_Pos)               /*!< 0x00000020 */

+#define FDCAN_TTIR_TTMI           FDCAN_TTIR_TTMI_Msk                          /*!<Trigger Time Mark Event Internal          */

+#define FDCAN_TTIR_SWE_Pos        (6U)

+#define FDCAN_TTIR_SWE_Msk        (0x1UL << FDCAN_TTIR_SWE_Pos)                /*!< 0x00000040 */

+#define FDCAN_TTIR_SWE            FDCAN_TTIR_SWE_Msk                           /*!<Stop Watch Event                          */

+#define FDCAN_TTIR_GTW_Pos        (7U)

+#define FDCAN_TTIR_GTW_Msk        (0x1UL << FDCAN_TTIR_GTW_Pos)                /*!< 0x00000080 */

+#define FDCAN_TTIR_GTW            FDCAN_TTIR_GTW_Msk                           /*!<Global Time Wrap                          */

+#define FDCAN_TTIR_GTD_Pos        (8U)

+#define FDCAN_TTIR_GTD_Msk        (0x1UL << FDCAN_TTIR_GTD_Pos)                /*!< 0x00000100 */

+#define FDCAN_TTIR_GTD            FDCAN_TTIR_GTD_Msk                           /*!<Global Time Discontinuity                 */

+#define FDCAN_TTIR_GTE_Pos        (9U)

+#define FDCAN_TTIR_GTE_Msk        (0x1UL << FDCAN_TTIR_GTE_Pos)                /*!< 0x00000200 */

+#define FDCAN_TTIR_GTE            FDCAN_TTIR_GTE_Msk                           /*!<Global Time Error                         */

+#define FDCAN_TTIR_TXU_Pos        (10U)

+#define FDCAN_TTIR_TXU_Msk        (0x1UL << FDCAN_TTIR_TXU_Pos)                /*!< 0x00000400 */

+#define FDCAN_TTIR_TXU            FDCAN_TTIR_TXU_Msk                           /*!<Tx Count Underflow                        */

+#define FDCAN_TTIR_TXO_Pos        (11U)

+#define FDCAN_TTIR_TXO_Msk        (0x1UL << FDCAN_TTIR_TXO_Pos)                /*!< 0x00000800 */

+#define FDCAN_TTIR_TXO            FDCAN_TTIR_TXO_Msk                           /*!<Tx Count Overflow                         */

+#define FDCAN_TTIR_SE1_Pos        (12U)

+#define FDCAN_TTIR_SE1_Msk        (0x1UL << FDCAN_TTIR_SE1_Pos)                /*!< 0x00001000 */

+#define FDCAN_TTIR_SE1            FDCAN_TTIR_SE1_Msk                           /*!<Scheduling Error 1                        */

+#define FDCAN_TTIR_SE2_Pos        (13U)

+#define FDCAN_TTIR_SE2_Msk        (0x1UL << FDCAN_TTIR_SE2_Pos)                /*!< 0x00002000 */

+#define FDCAN_TTIR_SE2            FDCAN_TTIR_SE2_Msk                           /*!<Scheduling Error 2                        */

+#define FDCAN_TTIR_ELC_Pos        (14U)

+#define FDCAN_TTIR_ELC_Msk        (0x1UL << FDCAN_TTIR_ELC_Pos)                /*!< 0x00004000 */

+#define FDCAN_TTIR_ELC            FDCAN_TTIR_ELC_Msk                           /*!<Error Level Changed                       */

+#define FDCAN_TTIR_IWT_Pos        (15U)

+#define FDCAN_TTIR_IWT_Msk        (0x1UL << FDCAN_TTIR_IWT_Pos)                /*!< 0x00008000 */

+#define FDCAN_TTIR_IWT            FDCAN_TTIR_IWT_Msk                           /*!<Initialization Watch Trigger              */

+#define FDCAN_TTIR_WT_Pos         (16U)

+#define FDCAN_TTIR_WT_Msk         (0x1UL << FDCAN_TTIR_WT_Pos)                 /*!< 0x00010000 */

+#define FDCAN_TTIR_WT             FDCAN_TTIR_WT_Msk                            /*!<Watch Trigger                             */

+#define FDCAN_TTIR_AW_Pos         (17U)

+#define FDCAN_TTIR_AW_Msk         (0x1UL << FDCAN_TTIR_AW_Pos)                 /*!< 0x00020000 */

+#define FDCAN_TTIR_AW             FDCAN_TTIR_AW_Msk                            /*!<Application Watchdog                      */

+#define FDCAN_TTIR_CER_Pos        (18U)

+#define FDCAN_TTIR_CER_Msk        (0x1UL << FDCAN_TTIR_CER_Pos)                /*!< 0x00040000 */

+#define FDCAN_TTIR_CER            FDCAN_TTIR_CER_Msk                           /*!<Configuration Error                       */

+

+/*****************  Bit definition for FDCAN_TTIE register  ********************/

+#define FDCAN_TTIE_SBCE_Pos       (0U)

+#define FDCAN_TTIE_SBCE_Msk       (0x1UL << FDCAN_TTIE_SBCE_Pos)               /*!< 0x00000001 */

+#define FDCAN_TTIE_SBCE           FDCAN_TTIE_SBCE_Msk                          /*!<Start of Basic Cycle Interrupt Enable             */

+#define FDCAN_TTIE_SMCE_Pos       (1U)

+#define FDCAN_TTIE_SMCE_Msk       (0x1UL << FDCAN_TTIE_SMCE_Pos)               /*!< 0x00000002 */

+#define FDCAN_TTIE_SMCE           FDCAN_TTIE_SMCE_Msk                          /*!<Start of Matrix Cycle Interrupt Enable            */

+#define FDCAN_TTIE_CSME_Pos       (2U)

+#define FDCAN_TTIE_CSME_Msk       (0x1UL << FDCAN_TTIE_CSME_Pos)               /*!< 0x00000004 */

+#define FDCAN_TTIE_CSME           FDCAN_TTIE_CSME_Msk                          /*!<Change of Synchronization Mode Interrupt Enable   */

+#define FDCAN_TTIE_SOGE_Pos       (3U)

+#define FDCAN_TTIE_SOGE_Msk       (0x1UL << FDCAN_TTIE_SOGE_Pos)               /*!< 0x00000008 */

+#define FDCAN_TTIE_SOGE           FDCAN_TTIE_SOGE_Msk                          /*!<Start of Gap Interrupt Enable                     */

+#define FDCAN_TTIE_RTMIE_Pos      (4U)

+#define FDCAN_TTIE_RTMIE_Msk      (0x1UL << FDCAN_TTIE_RTMIE_Pos)              /*!< 0x00000010 */

+#define FDCAN_TTIE_RTMIE          FDCAN_TTIE_RTMIE_Msk                         /*!<Register Time Mark Interrupt Interrupt Enable     */

+#define FDCAN_TTIE_TTMIE_Pos      (5U)

+#define FDCAN_TTIE_TTMIE_Msk      (0x1UL << FDCAN_TTIE_TTMIE_Pos)              /*!< 0x00000020 */

+#define FDCAN_TTIE_TTMIE          FDCAN_TTIE_TTMIE_Msk                         /*!<Trigger Time Mark Event Internal Interrupt Enable */

+#define FDCAN_TTIE_SWEE_Pos       (6U)

+#define FDCAN_TTIE_SWEE_Msk       (0x1UL << FDCAN_TTIE_SWEE_Pos)               /*!< 0x00000040 */

+#define FDCAN_TTIE_SWEE           FDCAN_TTIE_SWEE_Msk                          /*!<Stop Watch Event Interrupt Enable                 */

+#define FDCAN_TTIE_GTWE_Pos       (7U)

+#define FDCAN_TTIE_GTWE_Msk       (0x1UL << FDCAN_TTIE_GTWE_Pos)               /*!< 0x00000080 */

+#define FDCAN_TTIE_GTWE           FDCAN_TTIE_GTWE_Msk                          /*!<Global Time Wrap Interrupt Enable                 */

+#define FDCAN_TTIE_GTDE_Pos       (8U)

+#define FDCAN_TTIE_GTDE_Msk       (0x1UL << FDCAN_TTIE_GTDE_Pos)               /*!< 0x00000100 */

+#define FDCAN_TTIE_GTDE           FDCAN_TTIE_GTDE_Msk                          /*!<Global Time Discontinuity Interrupt Enable        */

+#define FDCAN_TTIE_GTEE_Pos       (9U)

+#define FDCAN_TTIE_GTEE_Msk       (0x1UL << FDCAN_TTIE_GTEE_Pos)               /*!< 0x00000200 */

+#define FDCAN_TTIE_GTEE           FDCAN_TTIE_GTEE_Msk                          /*!<Global Time Error Interrupt Enable                */

+#define FDCAN_TTIE_TXUE_Pos       (10U)

+#define FDCAN_TTIE_TXUE_Msk       (0x1UL << FDCAN_TTIE_TXUE_Pos)               /*!< 0x00000400 */

+#define FDCAN_TTIE_TXUE           FDCAN_TTIE_TXUE_Msk                          /*!<Tx Count Underflow Interrupt Enable               */

+#define FDCAN_TTIE_TXOE_Pos       (11U)

+#define FDCAN_TTIE_TXOE_Msk       (0x1UL << FDCAN_TTIE_TXOE_Pos)               /*!< 0x00000800 */

+#define FDCAN_TTIE_TXOE           FDCAN_TTIE_TXOE_Msk                          /*!<Tx Count Overflow Interrupt Enable                */

+#define FDCAN_TTIE_SE1E_Pos       (12U)

+#define FDCAN_TTIE_SE1E_Msk       (0x1UL << FDCAN_TTIE_SE1E_Pos)               /*!< 0x00001000 */

+#define FDCAN_TTIE_SE1E           FDCAN_TTIE_SE1E_Msk                          /*!<Scheduling Error 1 Interrupt Enable               */

+#define FDCAN_TTIE_SE2E_Pos       (13U)

+#define FDCAN_TTIE_SE2E_Msk       (0x1UL << FDCAN_TTIE_SE2E_Pos)               /*!< 0x00002000 */

+#define FDCAN_TTIE_SE2E           FDCAN_TTIE_SE2E_Msk                          /*!<Scheduling Error 2 Interrupt Enable               */

+#define FDCAN_TTIE_ELCE_Pos       (14U)

+#define FDCAN_TTIE_ELCE_Msk       (0x1UL << FDCAN_TTIE_ELCE_Pos)               /*!< 0x00004000 */

+#define FDCAN_TTIE_ELCE           FDCAN_TTIE_ELCE_Msk                          /*!<Error Level Changed Interrupt Enable              */

+#define FDCAN_TTIE_IWTE_Pos       (15U)

+#define FDCAN_TTIE_IWTE_Msk       (0x1UL << FDCAN_TTIE_IWTE_Pos)               /*!< 0x00008000 */

+#define FDCAN_TTIE_IWTE           FDCAN_TTIE_IWTE_Msk                          /*!<Initialization Watch Trigger Interrupt Enable     */

+#define FDCAN_TTIE_WTE_Pos        (16U)

+#define FDCAN_TTIE_WTE_Msk        (0x1UL << FDCAN_TTIE_WTE_Pos)                /*!< 0x00010000 */

+#define FDCAN_TTIE_WTE            FDCAN_TTIE_WTE_Msk                           /*!<Watch Trigger Interrupt Enable                    */

+#define FDCAN_TTIE_AWE_Pos        (17U)

+#define FDCAN_TTIE_AWE_Msk        (0x1UL << FDCAN_TTIE_AWE_Pos)                /*!< 0x00020000 */

+#define FDCAN_TTIE_AWE            FDCAN_TTIE_AWE_Msk                           /*!<Application Watchdog Interrupt Enable             */

+#define FDCAN_TTIE_CERE_Pos       (18U)

+#define FDCAN_TTIE_CERE_Msk       (0x1UL << FDCAN_TTIE_CERE_Pos)               /*!< 0x00040000 */

+#define FDCAN_TTIE_CERE           FDCAN_TTIE_CERE_Msk                          /*!<Configuration Error Interrupt Enable              */

+

+/*****************  Bit definition for FDCAN_TTILS register  ********************/

+#define FDCAN_TTILS_SBCS_Pos      (0U)

+#define FDCAN_TTILS_SBCS_Msk      (0x1UL << FDCAN_TTILS_SBCS_Pos)              /*!< 0x00000001 */

+#define FDCAN_TTILS_SBCS          FDCAN_TTILS_SBCS_Msk                         /*!<Start of Basic Cycle Interrupt Line               */

+#define FDCAN_TTILS_SMCS_Pos      (1U)

+#define FDCAN_TTILS_SMCS_Msk      (0x1UL << FDCAN_TTILS_SMCS_Pos)              /*!< 0x00000002 */

+#define FDCAN_TTILS_SMCS          FDCAN_TTILS_SMCS_Msk                         /*!<Start of Matrix Cycle Interrupt Line              */

+#define FDCAN_TTILS_CSMS_Pos      (2U)

+#define FDCAN_TTILS_CSMS_Msk      (0x1UL << FDCAN_TTILS_CSMS_Pos)              /*!< 0x00000004 */

+#define FDCAN_TTILS_CSMS          FDCAN_TTILS_CSMS_Msk                         /*!<Change of Synchronization Mode Interrupt Line     */

+#define FDCAN_TTILS_SOGS_Pos      (3U)

+#define FDCAN_TTILS_SOGS_Msk      (0x1UL << FDCAN_TTILS_SOGS_Pos)              /*!< 0x00000008 */

+#define FDCAN_TTILS_SOGS          FDCAN_TTILS_SOGS_Msk                         /*!<Start of Gap Interrupt Line                       */

+#define FDCAN_TTILS_RTMIS_Pos     (4U)

+#define FDCAN_TTILS_RTMIS_Msk     (0x1UL << FDCAN_TTILS_RTMIS_Pos)             /*!< 0x00000010 */

+#define FDCAN_TTILS_RTMIS         FDCAN_TTILS_RTMIS_Msk                        /*!<Register Time Mark Interrupt Interrupt Line       */

+#define FDCAN_TTILS_TTMIS_Pos     (5U)

+#define FDCAN_TTILS_TTMIS_Msk     (0x1UL << FDCAN_TTILS_TTMIS_Pos)             /*!< 0x00000020 */

+#define FDCAN_TTILS_TTMIS         FDCAN_TTILS_TTMIS_Msk                        /*!<Trigger Time Mark Event Internal Interrupt Line   */

+#define FDCAN_TTILS_SWES_Pos      (6U)

+#define FDCAN_TTILS_SWES_Msk      (0x1UL << FDCAN_TTILS_SWES_Pos)              /*!< 0x00000040 */

+#define FDCAN_TTILS_SWES          FDCAN_TTILS_SWES_Msk                         /*!<Stop Watch Event Interrupt Line                   */

+#define FDCAN_TTILS_GTWS_Pos      (7U)

+#define FDCAN_TTILS_GTWS_Msk      (0x1UL << FDCAN_TTILS_GTWS_Pos)              /*!< 0x00000080 */

+#define FDCAN_TTILS_GTWS          FDCAN_TTILS_GTWS_Msk                         /*!<Global Time Wrap Interrupt Line                   */

+#define FDCAN_TTILS_GTDS_Pos      (8U)

+#define FDCAN_TTILS_GTDS_Msk      (0x1UL << FDCAN_TTILS_GTDS_Pos)              /*!< 0x00000100 */

+#define FDCAN_TTILS_GTDS          FDCAN_TTILS_GTDS_Msk                         /*!<Global Time Discontinuity Interrupt Line          */

+#define FDCAN_TTILS_GTES_Pos      (9U)

+#define FDCAN_TTILS_GTES_Msk      (0x1UL << FDCAN_TTILS_GTES_Pos)              /*!< 0x00000200 */

+#define FDCAN_TTILS_GTES          FDCAN_TTILS_GTES_Msk                         /*!<Global Time Error Interrupt Line                  */

+#define FDCAN_TTILS_TXUS_Pos      (10U)

+#define FDCAN_TTILS_TXUS_Msk      (0x1UL << FDCAN_TTILS_TXUS_Pos)              /*!< 0x00000400 */

+#define FDCAN_TTILS_TXUS          FDCAN_TTILS_TXUS_Msk                         /*!<Tx Count Underflow Interrupt Line                 */

+#define FDCAN_TTILS_TXOS_Pos      (11U)

+#define FDCAN_TTILS_TXOS_Msk      (0x1UL << FDCAN_TTILS_TXOS_Pos)              /*!< 0x00000800 */

+#define FDCAN_TTILS_TXOS          FDCAN_TTILS_TXOS_Msk                         /*!<Tx Count Overflow Interrupt Line                  */

+#define FDCAN_TTILS_SE1S_Pos      (12U)

+#define FDCAN_TTILS_SE1S_Msk      (0x1UL << FDCAN_TTILS_SE1S_Pos)              /*!< 0x00001000 */

+#define FDCAN_TTILS_SE1S          FDCAN_TTILS_SE1S_Msk                         /*!<Scheduling Error 1 Interrupt Line                 */

+#define FDCAN_TTILS_SE2S_Pos      (13U)

+#define FDCAN_TTILS_SE2S_Msk      (0x1UL << FDCAN_TTILS_SE2S_Pos)              /*!< 0x00002000 */

+#define FDCAN_TTILS_SE2S          FDCAN_TTILS_SE2S_Msk                         /*!<Scheduling Error 2 Interrupt Line                 */

+#define FDCAN_TTILS_ELCS_Pos      (14U)

+#define FDCAN_TTILS_ELCS_Msk      (0x1UL << FDCAN_TTILS_ELCS_Pos)              /*!< 0x00004000 */

+#define FDCAN_TTILS_ELCS          FDCAN_TTILS_ELCS_Msk                         /*!<Error Level Changed Interrupt Line                */

+#define FDCAN_TTILS_IWTS_Pos      (15U)

+#define FDCAN_TTILS_IWTS_Msk      (0x1UL << FDCAN_TTILS_IWTS_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTILS_IWTS          FDCAN_TTILS_IWTS_Msk                         /*!<Initialization Watch Trigger Interrupt Line       */

+#define FDCAN_TTILS_WTS_Pos       (16U)

+#define FDCAN_TTILS_WTS_Msk       (0x1UL << FDCAN_TTILS_WTS_Pos)               /*!< 0x00010000 */

+#define FDCAN_TTILS_WTS           FDCAN_TTILS_WTS_Msk                          /*!<Watch Trigger Interrupt Line                      */

+#define FDCAN_TTILS_AWS_Pos       (17U)

+#define FDCAN_TTILS_AWS_Msk       (0x1UL << FDCAN_TTILS_AWS_Pos)               /*!< 0x00020000 */

+#define FDCAN_TTILS_AWS           FDCAN_TTILS_AWS_Msk                          /*!<Application Watchdog Interrupt Line               */

+#define FDCAN_TTILS_CERS_Pos      (18U)

+#define FDCAN_TTILS_CERS_Msk      (0x1UL << FDCAN_TTILS_CERS_Pos)              /*!< 0x00040000 */

+#define FDCAN_TTILS_CERS          FDCAN_TTILS_CERS_Msk                         /*!<Configuration Error Interrupt Line                */

+

+/*****************  Bit definition for FDCAN_TTOST register  ********************/

+#define FDCAN_TTOST_EL_Pos        (0U)

+#define FDCAN_TTOST_EL_Msk        (0x3UL << FDCAN_TTOST_EL_Pos)                /*!< 0x00000003 */

+#define FDCAN_TTOST_EL            FDCAN_TTOST_EL_Msk                           /*!<Error Level                              */

+#define FDCAN_TTOST_MS_Pos        (2U)

+#define FDCAN_TTOST_MS_Msk        (0x3UL << FDCAN_TTOST_MS_Pos)                /*!< 0x0000000C */

+#define FDCAN_TTOST_MS            FDCAN_TTOST_MS_Msk                           /*!<Master State                             */

+#define FDCAN_TTOST_SYS_Pos       (4U)

+#define FDCAN_TTOST_SYS_Msk       (0x3UL << FDCAN_TTOST_SYS_Pos)               /*!< 0x00000030 */

+#define FDCAN_TTOST_SYS           FDCAN_TTOST_SYS_Msk                          /*!<Synchronization State                    */

+#define FDCAN_TTOST_QGTP_Pos      (6U)

+#define FDCAN_TTOST_QGTP_Msk      (0x1UL << FDCAN_TTOST_QGTP_Pos)              /*!< 0x00000040 */

+#define FDCAN_TTOST_QGTP          FDCAN_TTOST_QGTP_Msk                         /*!<Quality of Global Time Phase             */

+#define FDCAN_TTOST_QCS_Pos       (7U)

+#define FDCAN_TTOST_QCS_Msk       (0x1UL << FDCAN_TTOST_QCS_Pos)               /*!< 0x00000080 */

+#define FDCAN_TTOST_QCS           FDCAN_TTOST_QCS_Msk                          /*!<Quality of Clock Speed                   */

+#define FDCAN_TTOST_RTO_Pos       (8U)

+#define FDCAN_TTOST_RTO_Msk       (0xFFUL << FDCAN_TTOST_RTO_Pos)              /*!< 0x0000FF00 */

+#define FDCAN_TTOST_RTO           FDCAN_TTOST_RTO_Msk                          /*!<Reference Trigger Offset                 */

+#define FDCAN_TTOST_WGTD_Pos      (22U)

+#define FDCAN_TTOST_WGTD_Msk      (0x1UL << FDCAN_TTOST_WGTD_Pos)              /*!< 0x00400000 */

+#define FDCAN_TTOST_WGTD          FDCAN_TTOST_WGTD_Msk                         /*!<Wait for Global Time Discontinuity       */

+#define FDCAN_TTOST_GFI_Pos       (23U)

+#define FDCAN_TTOST_GFI_Msk       (0x1UL << FDCAN_TTOST_GFI_Pos)               /*!< 0x00800000 */

+#define FDCAN_TTOST_GFI           FDCAN_TTOST_GFI_Msk                          /*!<Gap Finished Indicator                   */

+#define FDCAN_TTOST_TMP_Pos       (24U)

+#define FDCAN_TTOST_TMP_Msk       (0x7UL << FDCAN_TTOST_TMP_Pos)               /*!< 0x07000000 */

+#define FDCAN_TTOST_TMP           FDCAN_TTOST_TMP_Msk                          /*!<Time Master Priority                     */

+#define FDCAN_TTOST_GSI_Pos       (27U)

+#define FDCAN_TTOST_GSI_Msk       (0x1UL << FDCAN_TTOST_GSI_Pos)               /*!< 0x08000000 */

+#define FDCAN_TTOST_GSI           FDCAN_TTOST_GSI_Msk                          /*!<Gap Started Indicator                    */

+#define FDCAN_TTOST_WFE_Pos       (28U)

+#define FDCAN_TTOST_WFE_Msk       (0x1UL << FDCAN_TTOST_WFE_Pos)               /*!< 0x10000000 */

+#define FDCAN_TTOST_WFE           FDCAN_TTOST_WFE_Msk                          /*!<Wait for Event                           */

+#define FDCAN_TTOST_AWE_Pos       (29U)

+#define FDCAN_TTOST_AWE_Msk       (0x1UL << FDCAN_TTOST_AWE_Pos)               /*!< 0x20000000 */

+#define FDCAN_TTOST_AWE           FDCAN_TTOST_AWE_Msk                          /*!<Application Watchdog Event               */

+#define FDCAN_TTOST_WECS_Pos      (30U)

+#define FDCAN_TTOST_WECS_Msk      (0x1UL << FDCAN_TTOST_WECS_Pos)              /*!< 0x40000000 */

+#define FDCAN_TTOST_WECS          FDCAN_TTOST_WECS_Msk                         /*!<Wait for External Clock Synchronization  */

+#define FDCAN_TTOST_SPL_Pos       (31U)

+#define FDCAN_TTOST_SPL_Msk       (0x1UL << FDCAN_TTOST_SPL_Pos)               /*!< 0x80000000 */

+#define FDCAN_TTOST_SPL           FDCAN_TTOST_SPL_Msk                          /*!<Schedule Phase Lock                      */

+

+/*****************  Bit definition for FDCAN_TURNA register  ********************/

+#define FDCAN_TURNA_NAV_Pos       (0U)

+#define FDCAN_TURNA_NAV_Msk       (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)           /*!< 0x0003FFFF */

+#define FDCAN_TURNA_NAV           FDCAN_TURNA_NAV_Msk                          /*!<Numerator Actual Value                   */

+

+/*****************  Bit definition for FDCAN_TTLGT register  ********************/

+#define FDCAN_TTLGT_LT_Pos        (0U)

+#define FDCAN_TTLGT_LT_Msk        (0xFFFFUL << FDCAN_TTLGT_LT_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTLGT_LT            FDCAN_TTLGT_LT_Msk                           /*!<Local Time                               */

+#define FDCAN_TTLGT_GT_Pos        (16U)

+#define FDCAN_TTLGT_GT_Msk        (0xFFFFUL << FDCAN_TTLGT_GT_Pos)             /*!< 0xFFFF0000 */

+#define FDCAN_TTLGT_GT            FDCAN_TTLGT_GT_Msk                           /*!<Global Time                              */

+

+/*****************  Bit definition for FDCAN_TTCTC register  ********************/

+#define FDCAN_TTCTC_CT_Pos        (0U)

+#define FDCAN_TTCTC_CT_Msk        (0xFFFFUL << FDCAN_TTCTC_CT_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTCTC_CT            FDCAN_TTCTC_CT_Msk                           /*!<Cycle Time                               */

+#define FDCAN_TTCTC_CC_Pos        (16U)

+#define FDCAN_TTCTC_CC_Msk        (0x3FUL << FDCAN_TTCTC_CC_Pos)               /*!< 0x003F0000 */

+#define FDCAN_TTCTC_CC            FDCAN_TTCTC_CC_Msk                           /*!<Cycle Count                              */

+

+/*****************  Bit definition for FDCAN_TTCPT register  ********************/

+#define FDCAN_TTCPT_CCV_Pos       (0U)

+#define FDCAN_TTCPT_CCV_Msk       (0x3FUL << FDCAN_TTCPT_CCV_Pos)              /*!< 0x0000003F */

+#define FDCAN_TTCPT_CCV           FDCAN_TTCPT_CCV_Msk                          /*!<Cycle Count Value                        */

+#define FDCAN_TTCPT_SWV_Pos       (16U)

+#define FDCAN_TTCPT_SWV_Msk       (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)            /*!< 0xFFFF0000 */

+#define FDCAN_TTCPT_SWV           FDCAN_TTCPT_SWV_Msk                          /*!<Stop Watch Value                         */

+

+/*****************  Bit definition for FDCAN_TTCSM register  ********************/

+#define FDCAN_TTCSM_CSM_Pos       (0U)

+#define FDCAN_TTCSM_CSM_Msk       (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)            /*!< 0x0000FFFF */

+#define FDCAN_TTCSM_CSM           FDCAN_TTCSM_CSM_Msk                          /*!<Cycle Sync Mark                          */

+

+/*****************  Bit definition for FDCAN_TTTS register  *********************/

+#define FDCAN_TTTS_SWTSEL_Pos     (0U)

+#define FDCAN_TTTS_SWTSEL_Msk     (0x3UL << FDCAN_TTTS_SWTSEL_Pos)             /*!< 0x00000003 */

+#define FDCAN_TTTS_SWTSEL         FDCAN_TTTS_SWTSEL_Msk                        /*!<Stop watch trigger input selection       */

+#define FDCAN_TTTS_EVTSEL_Pos     (4U)

+#define FDCAN_TTTS_EVTSEL_Msk     (0x3UL << FDCAN_TTTS_EVTSEL_Pos)             /*!< 0x00000030 */

+#define FDCAN_TTTS_EVTSEL         FDCAN_TTTS_EVTSEL_Msk                        /*!<Event trigger input selection            */

+

+/********************************************************************************/

+/*                                                                              */

+/*                      FDCANCCU (Clock Calibration unit)                       */

+/*                                                                              */

+/********************************************************************************/

+

+/*****************  Bit definition for FDCANCCU_CREL register  ******************/

+#define FDCANCCU_CREL_DAY_Pos        (0U)

+#define FDCANCCU_CREL_DAY_Msk        (0xFFUL << FDCANCCU_CREL_DAY_Pos)         /*!< 0x000000FF */

+#define FDCANCCU_CREL_DAY            FDCANCCU_CREL_DAY_Msk                     /*!<Timestamp Day                           */

+#define FDCANCCU_CREL_MON_Pos        (8U)

+#define FDCANCCU_CREL_MON_Msk        (0xFFUL << FDCANCCU_CREL_MON_Pos)         /*!< 0x0000FF00 */

+#define FDCANCCU_CREL_MON            FDCANCCU_CREL_MON_Msk                     /*!<Timestamp Month                         */

+#define FDCANCCU_CREL_YEAR_Pos       (16U)

+#define FDCANCCU_CREL_YEAR_Msk       (0xFUL << FDCANCCU_CREL_YEAR_Pos)         /*!< 0x000F0000 */

+#define FDCANCCU_CREL_YEAR           FDCANCCU_CREL_YEAR_Msk                    /*!<Timestamp Year                          */

+#define FDCANCCU_CREL_SUBSTEP_Pos    (20U)

+#define FDCANCCU_CREL_SUBSTEP_Msk    (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)      /*!< 0x00F00000 */

+#define FDCANCCU_CREL_SUBSTEP        FDCANCCU_CREL_SUBSTEP_Msk                 /*!<Sub-step of Core release                */

+#define FDCANCCU_CREL_STEP_Pos       (24U)

+#define FDCANCCU_CREL_STEP_Msk       (0xFUL << FDCANCCU_CREL_STEP_Pos)         /*!< 0x0F000000 */

+#define FDCANCCU_CREL_STEP           FDCANCCU_CREL_STEP_Msk                    /*!<Step of Core release                    */

+#define FDCANCCU_CREL_REL_Pos        (28U)

+#define FDCANCCU_CREL_REL_Msk        (0xFUL << FDCANCCU_CREL_REL_Pos)          /*!< 0xF0000000 */

+#define FDCANCCU_CREL_REL            FDCANCCU_CREL_REL_Msk                     /*!<Core release                            */

+

+/*****************  Bit definition for FDCANCCU_CCFG register  ******************/

+#define FDCANCCU_CCFG_TQBT_Pos       (0U)

+#define FDCANCCU_CCFG_TQBT_Msk       (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)        /*!< 0x0000001F */

+#define FDCANCCU_CCFG_TQBT           FDCANCCU_CCFG_TQBT_Msk                    /*!<Time Quanta per Bit Time                */

+#define FDCANCCU_CCFG_BCC_Pos        (6U)

+#define FDCANCCU_CCFG_BCC_Msk        (0x1UL << FDCANCCU_CCFG_BCC_Pos)          /*!< 0x00000040 */

+#define FDCANCCU_CCFG_BCC            FDCANCCU_CCFG_BCC_Msk                     /*!<Bypass Clock Calibration                */

+#define FDCANCCU_CCFG_CFL_Pos        (7U)

+#define FDCANCCU_CCFG_CFL_Msk        (0x1UL << FDCANCCU_CCFG_CFL_Pos)          /*!< 0x00000080 */

+#define FDCANCCU_CCFG_CFL            FDCANCCU_CCFG_CFL_Msk                     /*!<Calibration Field Length                */

+#define FDCANCCU_CCFG_OCPM_Pos       (8U)

+#define FDCANCCU_CCFG_OCPM_Msk       (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)        /*!< 0x0000FF00 */

+#define FDCANCCU_CCFG_OCPM           FDCANCCU_CCFG_OCPM_Msk                    /*!<Oscillator Clock Periods Minimum        */

+#define FDCANCCU_CCFG_CDIV_Pos       (16U)

+#define FDCANCCU_CCFG_CDIV_Msk       (0xFUL << FDCANCCU_CCFG_CDIV_Pos)         /*!< 0x000F0000 */

+#define FDCANCCU_CCFG_CDIV           FDCANCCU_CCFG_CDIV_Msk                    /*!<Clock Divider                           */

+#define FDCANCCU_CCFG_SWR_Pos        (31U)

+#define FDCANCCU_CCFG_SWR_Msk        (0x1UL << FDCANCCU_CCFG_SWR_Pos)          /*!< 0x80000000 */

+#define FDCANCCU_CCFG_SWR            FDCANCCU_CCFG_SWR_Msk                     /*!<Software Reset                          */

+

+/*****************  Bit definition for FDCANCCU_CSTAT register  *****************/

+#define FDCANCCU_CSTAT_OCPC_Pos      (0U)

+#define FDCANCCU_CSTAT_OCPC_Msk      (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)    /*!< 0x0003FFFF */

+#define FDCANCCU_CSTAT_OCPC          FDCANCCU_CSTAT_OCPC_Msk                   /*!<Oscillator Clock Period Counter        */

+#define FDCANCCU_CSTAT_TQC_Pos       (18U)

+#define FDCANCCU_CSTAT_TQC_Msk       (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)       /*!< 0x1FFC0000 */

+#define FDCANCCU_CSTAT_TQC           FDCANCCU_CSTAT_TQC_Msk                    /*!<Time Quanta Counter                    */

+#define FDCANCCU_CSTAT_CALS_Pos      (30U)

+#define FDCANCCU_CSTAT_CALS_Msk      (0x3UL << FDCANCCU_CSTAT_CALS_Pos)        /*!< 0xC0000000 */

+#define FDCANCCU_CSTAT_CALS          FDCANCCU_CSTAT_CALS_Msk                   /*!<Calibration State                      */

+

+/******************  Bit definition for FDCANCCU_CWD register  ******************/

+#define FDCANCCU_CWD_WDC_Pos         (0U)

+#define FDCANCCU_CWD_WDC_Msk         (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)        /*!< 0x0000FFFF */

+#define FDCANCCU_CWD_WDC             FDCANCCU_CWD_WDC_Msk                      /*!<Watchdog Configuration                 */

+#define FDCANCCU_CWD_WDV_Pos         (16U)

+#define FDCANCCU_CWD_WDV_Msk         (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)        /*!< 0xFFFF0000 */

+#define FDCANCCU_CWD_WDV             FDCANCCU_CWD_WDV_Msk                      /*!<Watchdog Value                         */

+

+/******************  Bit definition for FDCANCCU_IR register  *******************/

+#define FDCANCCU_IR_CWE_Pos          (0U)

+#define FDCANCCU_IR_CWE_Msk          (0x1UL << FDCANCCU_IR_CWE_Pos)            /*!< 0x00000001 */

+#define FDCANCCU_IR_CWE              FDCANCCU_IR_CWE_Msk                       /*!<Calibration Watchdog Event             */

+#define FDCANCCU_IR_CSC_Pos          (1U)

+#define FDCANCCU_IR_CSC_Msk          (0x1UL << FDCANCCU_IR_CSC_Pos)            /*!< 0x00000002 */

+#define FDCANCCU_IR_CSC              FDCANCCU_IR_CSC_Msk                       /*!<Calibration State Changed              */

+

+/******************  Bit definition for FDCANCCU_IE register  *******************/

+#define FDCANCCU_IE_CWEE_Pos         (0U)

+#define FDCANCCU_IE_CWEE_Msk         (0x1UL << FDCANCCU_IE_CWEE_Pos)           /*!< 0x00000001 */

+#define FDCANCCU_IE_CWEE             FDCANCCU_IE_CWEE_Msk                      /*!<Calibration Watchdog Event Enable      */

+#define FDCANCCU_IE_CSCE_Pos         (1U)

+#define FDCANCCU_IE_CSCE_Msk         (0x1UL << FDCANCCU_IE_CSCE_Pos)           /*!< 0x00000002 */

+#define FDCANCCU_IE_CSCE             FDCANCCU_IE_CSCE_Msk                      /*!<Calibration State Changed Enable       */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          HDMI-CEC (CEC)                                    */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for CEC_CR register  *********************/

+#define CEC_CR_CECEN_Pos         (0U)

+#define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                   /*!< 0x00000001 */

+#define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                                */

+#define CEC_CR_TXSOM_Pos         (1U)

+#define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                   /*!< 0x00000002 */

+#define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message                   */

+#define CEC_CR_TXEOM_Pos         (2U)

+#define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                   /*!< 0x00000004 */

+#define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message                     */

+

+/*******************  Bit definition for CEC_CFGR register  *******************/

+#define CEC_CFGR_SFT_Pos         (0U)

+#define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                   /*!< 0x00000007 */

+#define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time                      */

+#define CEC_CFGR_RXTOL_Pos       (3U)

+#define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                 /*!< 0x00000008 */

+#define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                             */

+#define CEC_CFGR_BRESTP_Pos      (4U)

+#define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                /*!< 0x00000010 */

+#define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                               */

+#define CEC_CFGR_BREGEN_Pos      (5U)

+#define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                /*!< 0x00000020 */

+#define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation           */

+#define CEC_CFGR_LBPEGEN_Pos     (6U)

+#define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)               /*!< 0x00000040 */

+#define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error generation      */

+#define CEC_CFGR_SFTOPT_Pos      (8U)

+#define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                /*!< 0x00000100 */

+#define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional             */

+#define CEC_CFGR_BRDNOGEN_Pos    (7U)

+#define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)              /*!< 0x00000080 */

+#define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No error generation         */

+#define CEC_CFGR_OAR_Pos         (16U)

+#define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                /*!< 0x7FFF0000 */

+#define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                           */

+#define CEC_CFGR_LSTN_Pos        (31U)

+#define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                  /*!< 0x80000000 */

+#define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                           */

+

+/*******************  Bit definition for CEC_TXDR register  *******************/

+#define CEC_TXDR_TXD_Pos         (0U)

+#define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                  /*!< 0x000000FF */

+#define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                               */

+

+/*******************  Bit definition for CEC_RXDR register  *******************/

+#define CEC_RXDR_RXD_Pos         (0U)

+#define CEC_RXDR_RXD_Msk         (0xFFUL << CEC_RXDR_RXD_Pos)                  /*!< 0x000000FF */

+#define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                              /*!< CEC Rx Data                               */

+

+/*******************  Bit definition for CEC_ISR register  ********************/

+#define CEC_ISR_RXBR_Pos         (0U)

+#define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                   /*!< 0x00000001 */

+#define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                      */

+#define CEC_ISR_RXEND_Pos        (1U)

+#define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                  /*!< 0x00000002 */

+#define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                      */

+#define CEC_ISR_RXOVR_Pos        (2U)

+#define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                  /*!< 0x00000004 */

+#define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                            */

+#define CEC_ISR_BRE_Pos          (3U)

+#define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                    /*!< 0x00000008 */

+#define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                   */

+#define CEC_ISR_SBPE_Pos         (4U)

+#define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                   /*!< 0x00000010 */

+#define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error             */

+#define CEC_ISR_LBPE_Pos         (5U)

+#define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                   /*!< 0x00000020 */

+#define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error              */

+#define CEC_ISR_RXACKE_Pos       (6U)

+#define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                 /*!< 0x00000040 */

+#define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge                */

+#define CEC_ISR_ARBLST_Pos       (7U)

+#define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                 /*!< 0x00000080 */

+#define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                      */

+#define CEC_ISR_TXBR_Pos         (8U)

+#define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                   /*!< 0x00000100 */

+#define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                       */

+#define CEC_ISR_TXEND_Pos        (9U)

+#define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                  /*!< 0x00000200 */

+#define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                   */

+#define CEC_ISR_TXUDR_Pos        (10U)

+#define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                  /*!< 0x00000400 */

+#define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                    */

+#define CEC_ISR_TXERR_Pos        (11U)

+#define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                  /*!< 0x00000800 */

+#define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                              */

+#define CEC_ISR_TXACKE_Pos       (12U)

+#define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                 /*!< 0x00001000 */

+#define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge                */

+

+/*******************  Bit definition for CEC_IER register  ********************/

+#define CEC_IER_RXBRIE_Pos       (0U)

+#define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                 /*!< 0x00000001 */

+#define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable            */

+#define CEC_IER_RXENDIE_Pos      (1U)

+#define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                /*!< 0x00000002 */

+#define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable            */

+#define CEC_IER_RXOVRIE_Pos      (2U)

+#define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                /*!< 0x00000004 */

+#define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable                  */

+#define CEC_IER_BREIE_Pos        (3U)

+#define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                  /*!< 0x00000008 */

+#define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable         */

+#define CEC_IER_SBPEIE_Pos       (4U)

+#define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                 /*!< 0x00000010 */

+#define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable   */

+#define CEC_IER_LBPEIE_Pos       (5U)

+#define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                 /*!< 0x00000020 */

+#define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable    */

+#define CEC_IER_RXACKEIE_Pos     (6U)

+#define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)               /*!< 0x00000040 */

+#define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable      */

+#define CEC_IER_ARBLSTIE_Pos     (7U)

+#define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)               /*!< 0x00000080 */

+#define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable            */

+#define CEC_IER_TXBRIE_Pos       (8U)

+#define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                 /*!< 0x00000100 */

+#define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable            */

+#define CEC_IER_TXENDIE_Pos      (9U)

+#define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                /*!< 0x00000200 */

+#define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable         */

+#define CEC_IER_TXUDRIE_Pos      (10U)

+#define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                /*!< 0x00000400 */

+#define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable          */

+#define CEC_IER_TXERRIE_Pos      (11U)

+#define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                /*!< 0x00000800 */

+#define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                    */

+#define CEC_IER_TXACKEIE_Pos     (12U)

+#define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)               /*!< 0x00001000 */

+#define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable      */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          CRC calculation unit                              */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for CRC_DR register  *********************/

+#define CRC_DR_DR_Pos            (0U)

+#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */

+#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */

+

+/*******************  Bit definition for CRC_IDR register  ********************/

+#define CRC_IDR_IDR_Pos          (0U)

+#define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */

+#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */

+

+/********************  Bit definition for CRC_CR register  ********************/

+#define CRC_CR_RESET_Pos         (0U)

+#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */

+#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */

+#define CRC_CR_POLYSIZE_Pos      (3U)

+#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */

+#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */

+#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */

+#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */

+#define CRC_CR_REV_IN_Pos        (5U)

+#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */

+#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */

+#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */

+#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */

+#define CRC_CR_REV_OUT_Pos       (7U)

+#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */

+#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */

+

+/*******************  Bit definition for CRC_INIT register  *******************/

+#define CRC_INIT_INIT_Pos        (0U)

+#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */

+#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */

+

+/*******************  Bit definition for CRC_POL register  ********************/

+#define CRC_POL_POL_Pos          (0U)

+#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */

+#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          CRS Clock Recovery System                         */

+/******************************************************************************/

+

+/*******************  Bit definition for CRS_CR register  *********************/

+#define CRS_CR_SYNCOKIE_Pos       (0U)

+#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */

+#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */

+#define CRS_CR_SYNCWARNIE_Pos     (1U)

+#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */

+#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */

+#define CRS_CR_ERRIE_Pos          (2U)

+#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */

+#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */

+#define CRS_CR_ESYNCIE_Pos        (3U)

+#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */

+#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */

+#define CRS_CR_CEN_Pos            (5U)

+#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */

+#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */

+#define CRS_CR_AUTOTRIMEN_Pos     (6U)

+#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */

+#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */

+#define CRS_CR_SWSYNC_Pos         (7U)

+#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */

+#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */

+#define CRS_CR_TRIM_Pos           (8U)

+#define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00003F00 */

+#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */

+

+/*******************  Bit definition for CRS_CFGR register  *********************/

+#define CRS_CFGR_RELOAD_Pos       (0U)

+#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */

+#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */

+#define CRS_CFGR_FELIM_Pos        (16U)

+#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */

+#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */

+

+#define CRS_CFGR_SYNCDIV_Pos      (24U)

+#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */

+#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */

+#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */

+#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */

+#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */

+

+#define CRS_CFGR_SYNCSRC_Pos      (28U)

+#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */

+#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */

+#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */

+#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */

+

+#define CRS_CFGR_SYNCPOL_Pos      (31U)

+#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */

+#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */

+

+/*******************  Bit definition for CRS_ISR register  *********************/

+#define CRS_ISR_SYNCOKF_Pos       (0U)

+#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */

+#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */

+#define CRS_ISR_SYNCWARNF_Pos     (1U)

+#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */

+#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */

+#define CRS_ISR_ERRF_Pos          (2U)

+#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */

+#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */

+#define CRS_ISR_ESYNCF_Pos        (3U)

+#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */

+#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */

+#define CRS_ISR_SYNCERR_Pos       (8U)

+#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */

+#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */

+#define CRS_ISR_SYNCMISS_Pos      (9U)

+#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */

+#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */

+#define CRS_ISR_TRIMOVF_Pos       (10U)

+#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */

+#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */

+#define CRS_ISR_FEDIR_Pos         (15U)

+#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */

+#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */

+#define CRS_ISR_FECAP_Pos         (16U)

+#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */

+#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */

+

+/*******************  Bit definition for CRS_ICR register  *********************/

+#define CRS_ICR_SYNCOKC_Pos       (0U)

+#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */

+#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */

+#define CRS_ICR_SYNCWARNC_Pos     (1U)

+#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */

+#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */

+#define CRS_ICR_ERRC_Pos          (2U)

+#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */

+#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */

+#define CRS_ICR_ESYNCC_Pos        (3U)

+#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */

+#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            Crypto Processor                                */

+/*                                                                            */

+/******************************************************************************/

+/********************************  CRYP VER  **********************************/

+#define  CRYP_VER_2_2

+/******************* Bits definition for CRYP_CR register  ********************/

+#define CRYP_CR_ALGODIR_Pos              (2U)

+#define CRYP_CR_ALGODIR_Msk              (0x1UL << CRYP_CR_ALGODIR_Pos)        /*!< 0x00000004 */

+#define CRYP_CR_ALGODIR                  CRYP_CR_ALGODIR_Msk

+

+#define CRYP_CR_ALGOMODE_Pos             (3U)

+#define CRYP_CR_ALGOMODE_Msk             (0x10007UL << CRYP_CR_ALGOMODE_Pos)   /*!< 0x00080038 */

+#define CRYP_CR_ALGOMODE                 CRYP_CR_ALGOMODE_Msk

+#define CRYP_CR_ALGOMODE_0               (0x00001UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000008 */

+#define CRYP_CR_ALGOMODE_1               (0x00002UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000010 */

+#define CRYP_CR_ALGOMODE_2               (0x00004UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000020 */

+#define CRYP_CR_ALGOMODE_TDES_ECB        ((uint32_t)0x00000000)

+#define CRYP_CR_ALGOMODE_TDES_CBC_Pos    (3U)

+#define CRYP_CR_ALGOMODE_TDES_CBC_Msk    (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */

+#define CRYP_CR_ALGOMODE_TDES_CBC        CRYP_CR_ALGOMODE_TDES_CBC_Msk

+#define CRYP_CR_ALGOMODE_DES_ECB_Pos     (4U)

+#define CRYP_CR_ALGOMODE_DES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_DES_ECB_Pos) /*!< 0x00000010 */

+#define CRYP_CR_ALGOMODE_DES_ECB         CRYP_CR_ALGOMODE_DES_ECB_Msk

+#define CRYP_CR_ALGOMODE_DES_CBC_Pos     (3U)

+#define CRYP_CR_ALGOMODE_DES_CBC_Msk     (0x3UL << CRYP_CR_ALGOMODE_DES_CBC_Pos) /*!< 0x00000018 */

+#define CRYP_CR_ALGOMODE_DES_CBC         CRYP_CR_ALGOMODE_DES_CBC_Msk

+#define CRYP_CR_ALGOMODE_AES_ECB_Pos     (5U)

+#define CRYP_CR_ALGOMODE_AES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */

+#define CRYP_CR_ALGOMODE_AES_ECB         CRYP_CR_ALGOMODE_AES_ECB_Msk

+#define CRYP_CR_ALGOMODE_AES_CBC_Pos     (3U)

+#define CRYP_CR_ALGOMODE_AES_CBC_Msk     (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */

+#define CRYP_CR_ALGOMODE_AES_CBC         CRYP_CR_ALGOMODE_AES_CBC_Msk

+#define CRYP_CR_ALGOMODE_AES_CTR_Pos     (4U)

+#define CRYP_CR_ALGOMODE_AES_CTR_Msk     (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */

+#define CRYP_CR_ALGOMODE_AES_CTR         CRYP_CR_ALGOMODE_AES_CTR_Msk

+#define CRYP_CR_ALGOMODE_AES_KEY_Pos     (3U)

+#define CRYP_CR_ALGOMODE_AES_KEY_Msk     (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */

+#define CRYP_CR_ALGOMODE_AES_KEY         CRYP_CR_ALGOMODE_AES_KEY_Msk

+#define CRYP_CR_ALGOMODE_AES_GCM_Pos     (19U)

+#define CRYP_CR_ALGOMODE_AES_GCM_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_GCM_Pos) /*!< 0x00080000 */

+#define CRYP_CR_ALGOMODE_AES_GCM         CRYP_CR_ALGOMODE_AES_GCM_Msk

+#define CRYP_CR_ALGOMODE_AES_CCM_Pos     (3U)

+#define CRYP_CR_ALGOMODE_AES_CCM_Msk     (0x10001UL << CRYP_CR_ALGOMODE_AES_CCM_Pos) /*!< 0x00080008 */

+#define CRYP_CR_ALGOMODE_AES_CCM         CRYP_CR_ALGOMODE_AES_CCM_Msk

+

+#define CRYP_CR_DATATYPE_Pos             (6U)

+#define CRYP_CR_DATATYPE_Msk             (0x3UL << CRYP_CR_DATATYPE_Pos)       /*!< 0x000000C0 */

+#define CRYP_CR_DATATYPE                 CRYP_CR_DATATYPE_Msk

+#define CRYP_CR_DATATYPE_0               (0x1UL << CRYP_CR_DATATYPE_Pos)        /*!< 0x00000040 */

+#define CRYP_CR_DATATYPE_1               (0x2UL << CRYP_CR_DATATYPE_Pos)        /*!< 0x00000080 */

+#define CRYP_CR_KEYSIZE_Pos              (8U)

+#define CRYP_CR_KEYSIZE_Msk              (0x3UL << CRYP_CR_KEYSIZE_Pos)        /*!< 0x00000300 */

+#define CRYP_CR_KEYSIZE                  CRYP_CR_KEYSIZE_Msk

+#define CRYP_CR_KEYSIZE_0                (0x1UL << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000100 */

+#define CRYP_CR_KEYSIZE_1                (0x2UL << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000200 */

+#define CRYP_CR_FFLUSH_Pos               (14U)

+#define CRYP_CR_FFLUSH_Msk               (0x1UL << CRYP_CR_FFLUSH_Pos)         /*!< 0x00004000 */

+#define CRYP_CR_FFLUSH                   CRYP_CR_FFLUSH_Msk

+#define CRYP_CR_CRYPEN_Pos               (15U)

+#define CRYP_CR_CRYPEN_Msk               (0x1UL << CRYP_CR_CRYPEN_Pos)         /*!< 0x00008000 */

+#define CRYP_CR_CRYPEN                   CRYP_CR_CRYPEN_Msk

+

+#define CRYP_CR_GCM_CCMPH_Pos            (16U)

+#define CRYP_CR_GCM_CCMPH_Msk            (0x3UL << CRYP_CR_GCM_CCMPH_Pos)      /*!< 0x00030000 */

+#define CRYP_CR_GCM_CCMPH                CRYP_CR_GCM_CCMPH_Msk

+#define CRYP_CR_GCM_CCMPH_0              (0x1UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00010000 */

+#define CRYP_CR_GCM_CCMPH_1              (0x2UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00020000 */

+#define CRYP_CR_ALGOMODE_3               ((uint32_t)0x00080000)

+#define CRYP_CR_NPBLB_Pos                (20U)

+#define CRYP_CR_NPBLB_Msk                (0xFUL << CRYP_CR_NPBLB_Pos)          /*!< 0x00F00000 */

+#define CRYP_CR_NPBLB                    CRYP_CR_NPBLB_Msk

+

+/****************** Bits definition for CRYP_SR register  *********************/

+#define CRYP_SR_IFEM_Pos                 (0U)

+#define CRYP_SR_IFEM_Msk                 (0x1UL << CRYP_SR_IFEM_Pos)           /*!< 0x00000001 */

+#define CRYP_SR_IFEM                     CRYP_SR_IFEM_Msk

+#define CRYP_SR_IFNF_Pos                 (1U)

+#define CRYP_SR_IFNF_Msk                 (0x1UL << CRYP_SR_IFNF_Pos)           /*!< 0x00000002 */

+#define CRYP_SR_IFNF                     CRYP_SR_IFNF_Msk

+#define CRYP_SR_OFNE_Pos                 (2U)

+#define CRYP_SR_OFNE_Msk                 (0x1UL << CRYP_SR_OFNE_Pos)           /*!< 0x00000004 */

+#define CRYP_SR_OFNE                     CRYP_SR_OFNE_Msk

+#define CRYP_SR_OFFU_Pos                 (3U)

+#define CRYP_SR_OFFU_Msk                 (0x1UL << CRYP_SR_OFFU_Pos)           /*!< 0x00000008 */

+#define CRYP_SR_OFFU                     CRYP_SR_OFFU_Msk

+#define CRYP_SR_BUSY_Pos                 (4U)

+#define CRYP_SR_BUSY_Msk                 (0x1UL << CRYP_SR_BUSY_Pos)           /*!< 0x00000010 */

+#define CRYP_SR_BUSY                     CRYP_SR_BUSY_Msk

+/****************** Bits definition for CRYP_DMACR register  ******************/

+#define CRYP_DMACR_DIEN_Pos              (0U)

+#define CRYP_DMACR_DIEN_Msk              (0x1UL << CRYP_DMACR_DIEN_Pos)        /*!< 0x00000001 */

+#define CRYP_DMACR_DIEN                  CRYP_DMACR_DIEN_Msk

+#define CRYP_DMACR_DOEN_Pos              (1U)

+#define CRYP_DMACR_DOEN_Msk              (0x1UL << CRYP_DMACR_DOEN_Pos)        /*!< 0x00000002 */

+#define CRYP_DMACR_DOEN                  CRYP_DMACR_DOEN_Msk

+/*****************  Bits definition for CRYP_IMSCR register  ******************/

+#define CRYP_IMSCR_INIM_Pos              (0U)

+#define CRYP_IMSCR_INIM_Msk              (0x1UL << CRYP_IMSCR_INIM_Pos)        /*!< 0x00000001 */

+#define CRYP_IMSCR_INIM                  CRYP_IMSCR_INIM_Msk

+#define CRYP_IMSCR_OUTIM_Pos             (1U)

+#define CRYP_IMSCR_OUTIM_Msk             (0x1UL << CRYP_IMSCR_OUTIM_Pos)       /*!< 0x00000002 */

+#define CRYP_IMSCR_OUTIM                 CRYP_IMSCR_OUTIM_Msk

+/****************** Bits definition for CRYP_RISR register  *******************/

+#define CRYP_RISR_INRIS_Pos              (0U)

+#define CRYP_RISR_INRIS_Msk              (0x1UL << CRYP_RISR_INRIS_Pos)        /*!< 0x00000001 */

+#define CRYP_RISR_INRIS                  CRYP_RISR_INRIS_Msk

+#define CRYP_RISR_OUTRIS_Pos             (1U)

+#define CRYP_RISR_OUTRIS_Msk             (0x1UL << CRYP_RISR_OUTRIS_Pos)       /*!< 0x00000002 */

+#define CRYP_RISR_OUTRIS                 CRYP_RISR_OUTRIS_Msk

+/****************** Bits definition for CRYP_MISR register  *******************/

+#define CRYP_MISR_INMIS_Pos              (0U)

+#define CRYP_MISR_INMIS_Msk              (0x1UL << CRYP_MISR_INMIS_Pos)        /*!< 0x00000001 */

+#define CRYP_MISR_INMIS                  CRYP_MISR_INMIS_Msk

+#define CRYP_MISR_OUTMIS_Pos             (1U)

+#define CRYP_MISR_OUTMIS_Msk             (0x1UL << CRYP_MISR_OUTMIS_Pos)       /*!< 0x00000002 */

+#define CRYP_MISR_OUTMIS                 CRYP_MISR_OUTMIS_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                      Digital to Analog Converter                           */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for DAC_CR register  ********************/

+#define DAC_CR_EN1_Pos              (0U)

+#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */

+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */

+#define DAC_CR_TEN1_Pos             (1U)

+#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */

+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */

+

+#define DAC_CR_TSEL1_Pos            (2U)

+#define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */

+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */

+#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000004 */

+#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */

+#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */

+#define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */

+

+

+#define DAC_CR_WAVE1_Pos            (6U)

+#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */

+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */

+#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */

+#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */

+

+#define DAC_CR_MAMP1_Pos            (8U)

+#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */

+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */

+#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */

+#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */

+#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */

+#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */

+

+#define DAC_CR_DMAEN1_Pos           (12U)

+#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */

+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */

+#define DAC_CR_DMAUDRIE1_Pos        (13U)

+#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */

+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/

+#define DAC_CR_CEN1_Pos             (14U)

+#define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */

+#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/

+

+#define DAC_CR_EN2_Pos              (16U)

+#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */

+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */

+#define DAC_CR_TEN2_Pos             (17U)

+#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */

+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */

+

+#define DAC_CR_TSEL2_Pos            (18U)

+#define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */

+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */

+#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00040000 */

+#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */

+#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */

+#define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */

+

+

+#define DAC_CR_WAVE2_Pos            (22U)

+#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */

+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */

+#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */

+#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */

+

+#define DAC_CR_MAMP2_Pos            (24U)

+#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */

+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */

+#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */

+#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */

+#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */

+#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */

+

+#define DAC_CR_DMAEN2_Pos           (28U)

+#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */

+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */

+#define DAC_CR_DMAUDRIE2_Pos        (29U)

+#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */

+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/

+#define DAC_CR_CEN2_Pos             (30U)

+#define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */

+#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/

+

+/*****************  Bit definition for DAC_SWTRIGR register  ******************/

+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)

+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */

+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */

+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)

+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */

+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */

+

+/*****************  Bit definition for DAC_DHR12R1 register  ******************/

+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)

+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12L1 register  ******************/

+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)

+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8R1 register  ******************/

+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)

+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12R2 register  ******************/

+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)

+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12L2 register  ******************/

+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)

+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8R2 register  ******************/

+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)

+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12RD register  ******************/

+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)

+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */

+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)

+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */

+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12LD register  ******************/

+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)

+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */

+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)

+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */

+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8RD register  ******************/

+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)

+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */

+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)

+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */

+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */

+

+/*******************  Bit definition for DAC_DOR1 register  *******************/

+#define DAC_DOR1_DACC1DOR_Pos       (0U)

+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */

+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */

+

+/*******************  Bit definition for DAC_DOR2 register  *******************/

+#define DAC_DOR2_DACC2DOR_Pos       (0U)

+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */

+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */

+

+/********************  Bit definition for DAC_SR register  ********************/

+#define DAC_SR_DMAUDR1_Pos          (13U)

+#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */

+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */

+#define DAC_SR_CAL_FLAG1_Pos        (14U)

+#define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */

+#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */

+#define DAC_SR_BWST1_Pos            (15U)

+#define DAC_SR_BWST1_Msk            (0x4001UL << DAC_SR_BWST1_Pos)             /*!< 0x20008000 */

+#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */

+

+#define DAC_SR_DMAUDR2_Pos          (29U)

+#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */

+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */

+#define DAC_SR_CAL_FLAG2_Pos        (30U)

+#define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */

+#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */

+#define DAC_SR_BWST2_Pos            (31U)

+#define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */

+#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */

+

+/*******************  Bit definition for DAC_CCR register  ********************/

+#define DAC_CCR_OTRIM1_Pos          (0U)

+#define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */

+#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */

+#define DAC_CCR_OTRIM2_Pos          (16U)

+#define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */

+#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */

+

+/*******************  Bit definition for DAC_MCR register  *******************/

+#define DAC_MCR_MODE1_Pos           (0U)

+#define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */

+#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */

+#define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */

+#define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */

+#define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */

+

+#define DAC_MCR_MODE2_Pos           (16U)

+#define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */

+#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */

+#define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */

+#define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */

+#define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */

+

+/******************  Bit definition for DAC_SHSR1 register  ******************/

+#define DAC_SHSR1_TSAMPLE1_Pos      (0U)

+#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */

+#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */

+

+/******************  Bit definition for DAC_SHSR2 register  ******************/

+#define DAC_SHSR2_TSAMPLE2_Pos      (0U)

+#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */

+#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */

+

+/******************  Bit definition for DAC_SHHR register  ******************/

+#define DAC_SHHR_THOLD1_Pos         (0U)

+#define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */

+#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */

+#define DAC_SHHR_THOLD2_Pos         (16U)

+#define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */

+#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */

+

+/******************  Bit definition for DAC_SHRR register  ******************/

+#define DAC_SHRR_TREFRESH1_Pos      (0U)

+#define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */

+#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */

+#define DAC_SHRR_TREFRESH2_Pos      (16U)

+#define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */

+#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    DCMI                                    */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DCMI_CR register  ******************/

+#define DCMI_CR_CAPTURE_Pos        (0U)

+#define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)              /*!< 0x00000001 */

+#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk

+#define DCMI_CR_CM_Pos             (1U)

+#define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                   /*!< 0x00000002 */

+#define DCMI_CR_CM                 DCMI_CR_CM_Msk

+#define DCMI_CR_CROP_Pos           (2U)

+#define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                 /*!< 0x00000004 */

+#define DCMI_CR_CROP               DCMI_CR_CROP_Msk

+#define DCMI_CR_JPEG_Pos           (3U)

+#define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                 /*!< 0x00000008 */

+#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk

+#define DCMI_CR_ESS_Pos            (4U)

+#define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                  /*!< 0x00000010 */

+#define DCMI_CR_ESS                DCMI_CR_ESS_Msk

+#define DCMI_CR_PCKPOL_Pos         (5U)

+#define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)               /*!< 0x00000020 */

+#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk

+#define DCMI_CR_HSPOL_Pos          (6U)

+#define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                /*!< 0x00000040 */

+#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk

+#define DCMI_CR_VSPOL_Pos          (7U)

+#define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */

+#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk

+#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)

+#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)

+#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)

+#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)

+#define DCMI_CR_CRE_Pos            (12U)

+#define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */

+#define DCMI_CR_CRE                DCMI_CR_CRE_Msk

+#define DCMI_CR_ENABLE_Pos         (14U)

+#define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)               /*!< 0x00004000 */

+#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk

+#define DCMI_CR_BSM_Pos            (16U)

+#define DCMI_CR_BSM_Msk            (0x3UL << DCMI_CR_BSM_Pos)                  /*!< 0x00030000 */

+#define DCMI_CR_BSM                DCMI_CR_BSM_Msk

+#define DCMI_CR_BSM_0              (0x1UL << DCMI_CR_BSM_Pos)                   /*!< 0x00010000 */

+#define DCMI_CR_BSM_1              (0x2UL << DCMI_CR_BSM_Pos)                   /*!< 0x00020000 */

+#define DCMI_CR_OEBS_Pos           (18U)

+#define DCMI_CR_OEBS_Msk           (0x1UL << DCMI_CR_OEBS_Pos)                 /*!< 0x00040000 */

+#define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk

+#define DCMI_CR_LSM_Pos            (19U)

+#define DCMI_CR_LSM_Msk            (0x1UL << DCMI_CR_LSM_Pos)                  /*!< 0x00080000 */

+#define DCMI_CR_LSM                DCMI_CR_LSM_Msk

+#define DCMI_CR_OELS_Pos           (20U)

+#define DCMI_CR_OELS_Msk           (0x1UL << DCMI_CR_OELS_Pos)                 /*!< 0x00100000 */

+#define DCMI_CR_OELS               DCMI_CR_OELS_Msk

+

+/********************  Bits definition for DCMI_SR register  ******************/

+#define DCMI_SR_HSYNC_Pos          (0U)

+#define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                /*!< 0x00000001 */

+#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk

+#define DCMI_SR_VSYNC_Pos          (1U)

+#define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                /*!< 0x00000002 */

+#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk

+#define DCMI_SR_FNE_Pos            (2U)

+#define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                  /*!< 0x00000004 */

+#define DCMI_SR_FNE                DCMI_SR_FNE_Msk

+

+/********************  Bits definition for DCMI_RIS register   ****************/

+#define DCMI_RIS_FRAME_RIS_Pos     (0U)

+#define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)           /*!< 0x00000001 */

+#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk

+#define DCMI_RIS_OVR_RIS_Pos       (1U)

+#define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)             /*!< 0x00000002 */

+#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk

+#define DCMI_RIS_ERR_RIS_Pos       (2U)

+#define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)             /*!< 0x00000004 */

+#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk

+#define DCMI_RIS_VSYNC_RIS_Pos     (3U)

+#define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)           /*!< 0x00000008 */

+#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk

+#define DCMI_RIS_LINE_RIS_Pos      (4U)

+#define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)            /*!< 0x00000010 */

+#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk

+

+/********************  Bits definition for DCMI_IER register  *****************/

+#define DCMI_IER_FRAME_IE_Pos      (0U)

+#define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)            /*!< 0x00000001 */

+#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk

+#define DCMI_IER_OVR_IE_Pos        (1U)

+#define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)              /*!< 0x00000002 */

+#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk

+#define DCMI_IER_ERR_IE_Pos        (2U)

+#define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)              /*!< 0x00000004 */

+#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk

+#define DCMI_IER_VSYNC_IE_Pos      (3U)

+#define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)            /*!< 0x00000008 */

+#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk

+#define DCMI_IER_LINE_IE_Pos       (4U)

+#define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)             /*!< 0x00000010 */

+#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk

+

+

+/********************  Bits definition for DCMI_MIS register  *****************/

+#define DCMI_MIS_FRAME_MIS_Pos     (0U)

+#define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)           /*!< 0x00000001 */

+#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk

+#define DCMI_MIS_OVR_MIS_Pos       (1U)

+#define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)             /*!< 0x00000002 */

+#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk

+#define DCMI_MIS_ERR_MIS_Pos       (2U)

+#define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)             /*!< 0x00000004 */

+#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk

+#define DCMI_MIS_VSYNC_MIS_Pos     (3U)

+#define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)           /*!< 0x00000008 */

+#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk

+#define DCMI_MIS_LINE_MIS_Pos      (4U)

+#define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)            /*!< 0x00000010 */

+#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk

+

+

+/********************  Bits definition for DCMI_ICR register  *****************/

+#define DCMI_ICR_FRAME_ISC_Pos     (0U)

+#define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)           /*!< 0x00000001 */

+#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk

+#define DCMI_ICR_OVR_ISC_Pos       (1U)

+#define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)             /*!< 0x00000002 */

+#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk

+#define DCMI_ICR_ERR_ISC_Pos       (2U)

+#define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)             /*!< 0x00000004 */

+#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk

+#define DCMI_ICR_VSYNC_ISC_Pos     (3U)

+#define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)           /*!< 0x00000008 */

+#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk

+#define DCMI_ICR_LINE_ISC_Pos      (4U)

+#define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)            /*!< 0x00000010 */

+#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk

+

+

+/********************  Bits definition for DCMI_ESCR register  ******************/

+#define DCMI_ESCR_FSC_Pos          (0U)

+#define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)               /*!< 0x000000FF */

+#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk

+#define DCMI_ESCR_LSC_Pos          (8U)

+#define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)               /*!< 0x0000FF00 */

+#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk

+#define DCMI_ESCR_LEC_Pos          (16U)

+#define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)               /*!< 0x00FF0000 */

+#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk

+#define DCMI_ESCR_FEC_Pos          (24U)

+#define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)               /*!< 0xFF000000 */

+#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk

+

+/********************  Bits definition for DCMI_ESUR register  ******************/

+#define DCMI_ESUR_FSU_Pos          (0U)

+#define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)               /*!< 0x000000FF */

+#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk

+#define DCMI_ESUR_LSU_Pos          (8U)

+#define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)               /*!< 0x0000FF00 */

+#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk

+#define DCMI_ESUR_LEU_Pos          (16U)

+#define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)               /*!< 0x00FF0000 */

+#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk

+#define DCMI_ESUR_FEU_Pos          (24U)

+#define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)               /*!< 0xFF000000 */

+#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk

+

+/********************  Bits definition for DCMI_CWSTRT register  ******************/

+#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)

+#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)       /*!< 0x00003FFF */

+#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk

+#define DCMI_CWSTRT_VST_Pos        (16U)

+#define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)           /*!< 0x1FFF0000 */

+#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk

+

+/********************  Bits definition for DCMI_CWSIZE register  ******************/

+#define DCMI_CWSIZE_CAPCNT_Pos     (0U)

+#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)        /*!< 0x00003FFF */

+#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk

+#define DCMI_CWSIZE_VLINE_Pos      (16U)

+#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)         /*!< 0x3FFF0000 */

+#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk

+

+/********************  Bits definition for DCMI_DR register  ******************/

+#define DCMI_DR_BYTE0_Pos          (0U)

+#define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)               /*!< 0x000000FF */

+#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk

+#define DCMI_DR_BYTE1_Pos          (8U)

+#define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)               /*!< 0x0000FF00 */

+#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk

+#define DCMI_DR_BYTE2_Pos          (16U)

+#define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)               /*!< 0x00FF0000 */

+#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk

+#define DCMI_DR_BYTE3_Pos          (24U)

+#define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)               /*!< 0xFF000000 */

+#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                 Digital Filter for Sigma Delta Modulators                  */

+/*                                                                            */

+/******************************************************************************/

+

+/****************   DFSDM channel configuration registers  ********************/

+

+/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/

+#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)

+#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)   /*!< 0x80000000 */

+#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */

+#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)

+#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)  /*!< 0x40000000 */

+#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */

+#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)

+#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */

+#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */

+#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)

+#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x0000C000 */

+#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */

+#define DFSDM_CHCFGR1_DATPACK_1         (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */

+#define DFSDM_CHCFGR1_DATPACK_0         (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */

+#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)

+#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00003000 */

+#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */

+#define DFSDM_CHCFGR1_DATMPX_1          (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */

+#define DFSDM_CHCFGR1_DATMPX_0          (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */

+#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)

+#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)   /*!< 0x00000100 */

+#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */

+#define DFSDM_CHCFGR1_CHEN_Pos          (7U)

+#define DFSDM_CHCFGR1_CHEN_Msk          (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)      /*!< 0x00000080 */

+#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */

+#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)

+#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)    /*!< 0x00000040 */

+#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */

+#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)

+#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)     /*!< 0x00000020 */

+#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */

+#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)

+#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x0000000C */

+#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */

+#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */

+#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */

+#define DFSDM_CHCFGR1_SITP_Pos          (0U)

+#define DFSDM_CHCFGR1_SITP_Msk          (0x3UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000003 */

+#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */

+#define DFSDM_CHCFGR1_SITP_1            (0x2UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */

+#define DFSDM_CHCFGR1_SITP_0            (0x1UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */

+

+/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/

+#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)

+#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */

+#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)

+#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)    /*!< 0x000000F8 */

+#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */

+

+/******************  Bit definition for DFSDM_CHAWSCDR register *****************/

+#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)

+#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00C00000 */

+#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */

+#define DFSDM_CHAWSCDR_AWFORD_1         (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */

+#define DFSDM_CHAWSCDR_AWFORD_0         (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */

+#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)

+#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)  /*!< 0x001F0000 */

+#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */

+#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)

+#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)    /*!< 0x0000F000 */

+#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */

+#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)

+#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)    /*!< 0x000000FF */

+#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */

+

+/****************  Bit definition for DFSDM_CHWDATR register *******************/

+#define DFSDM_CHWDATR_WDATA_Pos         (0U)

+#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)  /*!< 0x0000FFFF */

+#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */

+

+/****************  Bit definition for DFSDM_CHDATINR register *****************/

+#define DFSDM_CHDATINR_INDAT0_Pos       (0U)

+#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */

+#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */

+#define DFSDM_CHDATINR_INDAT1_Pos       (16U)

+#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */

+#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */

+

+/****************  Bit definition for DFSDM_CHDLYR register *****************/

+#define DFSDM_CHDLYR_PLSSKP_Pos         (0U)

+#define DFSDM_CHDLYR_PLSSKP_Msk         (0x3FUL << DFSDM_CHDLYR_PLSSKP_Pos)    /*!< 0x0000003F*/

+#define DFSDM_CHDLYR_PLSSKP             DFSDM_CHDLYR_PLSSKP_Msk

+/************************   DFSDM module registers  ****************************/

+

+/********************  Bit definition for DFSDM_FLTCR1 register *******************/

+#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)

+#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)     /*!< 0x40000000 */

+#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */

+#define DFSDM_FLTCR1_FAST_Pos           (29U)

+#define DFSDM_FLTCR1_FAST_Msk           (0x1UL << DFSDM_FLTCR1_FAST_Pos)       /*!< 0x20000000 */

+#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */

+#define DFSDM_FLTCR1_RCH_Pos            (24U)

+#define DFSDM_FLTCR1_RCH_Msk            (0x7UL << DFSDM_FLTCR1_RCH_Pos)        /*!< 0x07000000 */

+#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */

+#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)

+#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)     /*!< 0x00200000 */

+#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */

+#define DFSDM_FLTCR1_RSYNC_Pos          (19U)

+#define DFSDM_FLTCR1_RSYNC_Msk          (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)      /*!< 0x00080000 */

+#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */

+#define DFSDM_FLTCR1_RCONT_Pos          (18U)

+#define DFSDM_FLTCR1_RCONT_Msk          (0x1UL << DFSDM_FLTCR1_RCONT_Pos)      /*!< 0x00040000 */

+#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */

+#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)

+#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)   /*!< 0x00020000 */

+#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */

+#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)

+#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00006000 */

+#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */

+#define DFSDM_FLTCR1_JEXTEN_1           (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */

+#define DFSDM_FLTCR1_JEXTEN_0           (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */

+#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)

+#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)   /*!< 0x00001F00 */

+#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */

+#define DFSDM_FLTCR1_JEXTSEL_0          (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000100 */

+#define DFSDM_FLTCR1_JEXTSEL_1          (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000200 */

+#define DFSDM_FLTCR1_JEXTSEL_2          (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000400 */

+#define DFSDM_FLTCR1_JEXTSEL_3          (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000800 */

+#define DFSDM_FLTCR1_JEXTSEL_4          (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00001000 */

+

+#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)

+#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)     /*!< 0x00000020 */

+#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */

+#define DFSDM_FLTCR1_JSCAN_Pos          (4U)

+#define DFSDM_FLTCR1_JSCAN_Msk          (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)      /*!< 0x00000010 */

+#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */

+#define DFSDM_FLTCR1_JSYNC_Pos          (3U)

+#define DFSDM_FLTCR1_JSYNC_Msk          (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)      /*!< 0x00000008 */

+#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */

+#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)

+#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)   /*!< 0x00000002 */

+#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */

+#define DFSDM_FLTCR1_DFEN_Pos           (0U)

+#define DFSDM_FLTCR1_DFEN_Msk           (0x1UL << DFSDM_FLTCR1_DFEN_Pos)       /*!< 0x00000001 */

+#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */

+

+/********************  Bit definition for DFSDM_FLTCR2 register *******************/

+#define DFSDM_FLTCR2_AWDCH_Pos          (16U)

+#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)     /*!< 0x00FF0000 */

+#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */

+#define DFSDM_FLTCR2_EXCH_Pos           (8U)

+#define DFSDM_FLTCR2_EXCH_Msk           (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)      /*!< 0x0000FF00 */

+#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */

+#define DFSDM_FLTCR2_CKABIE_Pos         (6U)

+#define DFSDM_FLTCR2_CKABIE_Msk         (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)     /*!< 0x00000040 */

+#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */

+#define DFSDM_FLTCR2_SCDIE_Pos          (5U)

+#define DFSDM_FLTCR2_SCDIE_Msk          (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)      /*!< 0x00000020 */

+#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */

+#define DFSDM_FLTCR2_AWDIE_Pos          (4U)

+#define DFSDM_FLTCR2_AWDIE_Msk          (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)      /*!< 0x00000010 */

+#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */

+#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)

+#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)     /*!< 0x00000008 */

+#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */

+#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)

+#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)     /*!< 0x00000004 */

+#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */

+#define DFSDM_FLTCR2_REOCIE_Pos         (1U)

+#define DFSDM_FLTCR2_REOCIE_Msk         (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)     /*!< 0x00000002 */

+#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */

+#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)

+#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)     /*!< 0x00000001 */

+#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */

+

+/********************  Bit definition for DFSDM_FLTISR register *******************/

+#define DFSDM_FLTISR_SCDF_Pos           (24U)

+#define DFSDM_FLTISR_SCDF_Msk           (0xFFUL << DFSDM_FLTISR_SCDF_Pos)      /*!< 0xFF000000 */

+#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */

+#define DFSDM_FLTISR_CKABF_Pos          (16U)

+#define DFSDM_FLTISR_CKABF_Msk          (0xFFUL << DFSDM_FLTISR_CKABF_Pos)     /*!< 0x00FF0000 */

+#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */

+#define DFSDM_FLTISR_RCIP_Pos           (14U)

+#define DFSDM_FLTISR_RCIP_Msk           (0x1UL << DFSDM_FLTISR_RCIP_Pos)       /*!< 0x00004000 */

+#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */

+#define DFSDM_FLTISR_JCIP_Pos           (13U)

+#define DFSDM_FLTISR_JCIP_Msk           (0x1UL << DFSDM_FLTISR_JCIP_Pos)       /*!< 0x00002000 */

+#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */

+#define DFSDM_FLTISR_AWDF_Pos           (4U)

+#define DFSDM_FLTISR_AWDF_Msk           (0x1UL << DFSDM_FLTISR_AWDF_Pos)       /*!< 0x00000010 */

+#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */

+#define DFSDM_FLTISR_ROVRF_Pos          (3U)

+#define DFSDM_FLTISR_ROVRF_Msk          (0x1UL << DFSDM_FLTISR_ROVRF_Pos)      /*!< 0x00000008 */

+#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */

+#define DFSDM_FLTISR_JOVRF_Pos          (2U)

+#define DFSDM_FLTISR_JOVRF_Msk          (0x1UL << DFSDM_FLTISR_JOVRF_Pos)      /*!< 0x00000004 */

+#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */

+#define DFSDM_FLTISR_REOCF_Pos          (1U)

+#define DFSDM_FLTISR_REOCF_Msk          (0x1UL << DFSDM_FLTISR_REOCF_Pos)      /*!< 0x00000002 */

+#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */

+#define DFSDM_FLTISR_JEOCF_Pos          (0U)

+#define DFSDM_FLTISR_JEOCF_Msk          (0x1UL << DFSDM_FLTISR_JEOCF_Pos)      /*!< 0x00000001 */

+#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */

+

+/********************  Bit definition for DFSDM_FLTICR register *******************/

+#define DFSDM_FLTICR_CLRSCDF_Pos        (24U)

+#define DFSDM_FLTICR_CLRSCDF_Msk        (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)   /*!< 0xFF000000 */

+#define DFSDM_FLTICR_CLRSCDF            DFSDM_FLTICR_CLRSCDF_Msk               /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */

+#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)

+#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)  /*!< 0x00FF0000 */

+#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */

+#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)

+#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)   /*!< 0x00000008 */

+#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */

+#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)

+#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)   /*!< 0x00000004 */

+#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */

+

+/*******************  Bit definition for DFSDM_FLTJCHGR register ******************/

+#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)

+#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)    /*!< 0x000000FF */

+#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */

+

+/********************  Bit definition for DFSDM_FLTFCR register *******************/

+#define DFSDM_FLTFCR_FORD_Pos           (29U)

+#define DFSDM_FLTFCR_FORD_Msk           (0x7UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0xE0000000 */

+#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */

+#define DFSDM_FLTFCR_FORD_2             (0x4UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */

+#define DFSDM_FLTFCR_FORD_1             (0x2UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */

+#define DFSDM_FLTFCR_FORD_0             (0x1UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */

+#define DFSDM_FLTFCR_FOSR_Pos           (16U)

+#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)     /*!< 0x03FF0000 */

+#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */

+#define DFSDM_FLTFCR_IOSR_Pos           (0U)

+#define DFSDM_FLTFCR_IOSR_Msk           (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)      /*!< 0x000000FF */

+#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */

+

+/******************  Bit definition for DFSDM_FLTJDATAR register *****************/

+#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)

+#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */

+#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)

+#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */

+#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */

+

+/******************  Bit definition for DFSDM_FLTRDATAR register *****************/

+#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)

+#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */

+#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)

+#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)   /*!< 0x00000010 */

+#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */

+#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)

+#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */

+#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */

+

+/******************  Bit definition for DFSDM_FLTAWHTR register ******************/

+#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)

+#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */

+#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)

+#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)    /*!< 0x0000000F */

+#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */

+

+/******************  Bit definition for DFSDM_FLTAWLTR register ******************/

+#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)

+#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWHT[23:0] Analog watchdog low threshold */

+#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)

+#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)    /*!< 0x0000000F */

+#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */

+

+/******************  Bit definition for DFSDM_FLTAWSR register ******************/

+#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)

+#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)    /*!< 0x0000FF00 */

+#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */

+#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)

+#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)    /*!< 0x000000FF */

+#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */

+

+/******************  Bit definition for DFSDM_FLTAWCFR) register *****************/

+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)

+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */

+#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */

+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)

+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */

+#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */

+

+/******************  Bit definition for DFSDM_FLTEXMAX register ******************/

+#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)

+#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */

+#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)

+#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)  /*!< 0x00000007 */

+#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */

+

+/******************  Bit definition for DFSDM_FLTEXMIN register ******************/

+#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)

+#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */

+#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)

+#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)  /*!< 0x00000007 */

+#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */

+

+/******************  Bit definition for DFSDM_FLTCNVTIMR register ******************/

+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)

+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */

+#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           BDMA Controller                                  */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for BDMA_ISR register  ********************/

+#define BDMA_ISR_GIF0_Pos       (0U)

+#define BDMA_ISR_GIF0_Msk       (0x1UL << BDMA_ISR_GIF0_Pos)                   /*!< 0x00000001 */

+#define BDMA_ISR_GIF0           BDMA_ISR_GIF0_Msk                              /*!< Channel 0 Global interrupt flag */

+#define BDMA_ISR_TCIF0_Pos      (1U)

+#define BDMA_ISR_TCIF0_Msk      (0x1UL << BDMA_ISR_TCIF0_Pos)                  /*!< 0x00000002 */

+#define BDMA_ISR_TCIF0          BDMA_ISR_TCIF0_Msk                             /*!< Channel 0 Transfer Complete flag */

+#define BDMA_ISR_HTIF0_Pos      (2U)

+#define BDMA_ISR_HTIF0_Msk      (0x1UL << BDMA_ISR_HTIF0_Pos)                  /*!< 0x00000004 */

+#define BDMA_ISR_HTIF0          BDMA_ISR_HTIF0_Msk                             /*!< Channel 0 Half Transfer flag */

+#define BDMA_ISR_TEIF0_Pos      (3U)

+#define BDMA_ISR_TEIF0_Msk      (0x1UL << BDMA_ISR_TEIF0_Pos)                  /*!< 0x00000008 */

+#define BDMA_ISR_TEIF0          BDMA_ISR_TEIF0_Msk                             /*!< Channel 0 Transfer Error flag */

+#define BDMA_ISR_GIF1_Pos       (4U)

+#define BDMA_ISR_GIF1_Msk       (0x1UL << BDMA_ISR_GIF1_Pos)                   /*!< 0x00000010 */

+#define BDMA_ISR_GIF1           BDMA_ISR_GIF1_Msk                              /*!< Channel 1 Global interrupt flag */

+#define BDMA_ISR_TCIF1_Pos      (5U)

+#define BDMA_ISR_TCIF1_Msk      (0x1UL << BDMA_ISR_TCIF1_Pos)                  /*!< 0x00000020 */

+#define BDMA_ISR_TCIF1          BDMA_ISR_TCIF1_Msk                             /*!< Channel 1 Transfer Complete flag */

+#define BDMA_ISR_HTIF1_Pos      (6U)

+#define BDMA_ISR_HTIF1_Msk      (0x1UL << BDMA_ISR_HTIF1_Pos)                  /*!< 0x00000040 */

+#define BDMA_ISR_HTIF1          BDMA_ISR_HTIF1_Msk                             /*!< Channel 1 Half Transfer flag */

+#define BDMA_ISR_TEIF1_Pos      (7U)

+#define BDMA_ISR_TEIF1_Msk      (0x1UL << BDMA_ISR_TEIF1_Pos)                  /*!< 0x00000080 */

+#define BDMA_ISR_TEIF1          BDMA_ISR_TEIF1_Msk                             /*!< Channel 1 Transfer Error flag */

+#define BDMA_ISR_GIF2_Pos       (8U)

+#define BDMA_ISR_GIF2_Msk       (0x1UL << BDMA_ISR_GIF2_Pos)                   /*!< 0x00000100 */

+#define BDMA_ISR_GIF2           BDMA_ISR_GIF2_Msk                              /*!< Channel 2 Global interrupt flag */

+#define BDMA_ISR_TCIF2_Pos      (9U)

+#define BDMA_ISR_TCIF2_Msk      (0x1UL << BDMA_ISR_TCIF2_Pos)                  /*!< 0x00000200 */

+#define BDMA_ISR_TCIF2          BDMA_ISR_TCIF2_Msk                             /*!< Channel 2 Transfer Complete flag */

+#define BDMA_ISR_HTIF2_Pos      (10U)

+#define BDMA_ISR_HTIF2_Msk      (0x1UL << BDMA_ISR_HTIF2_Pos)                  /*!< 0x00000400 */

+#define BDMA_ISR_HTIF2          BDMA_ISR_HTIF2_Msk                             /*!< Channel 2 Half Transfer flag */

+#define BDMA_ISR_TEIF2_Pos      (11U)

+#define BDMA_ISR_TEIF2_Msk      (0x1UL << BDMA_ISR_TEIF2_Pos)                  /*!< 0x00000800 */

+#define BDMA_ISR_TEIF2          BDMA_ISR_TEIF2_Msk                             /*!< Channel 2 Transfer Error flag */

+#define BDMA_ISR_GIF3_Pos       (12U)

+#define BDMA_ISR_GIF3_Msk       (0x1UL << BDMA_ISR_GIF3_Pos)                   /*!< 0x00001000 */

+#define BDMA_ISR_GIF3           BDMA_ISR_GIF3_Msk                              /*!< Channel 3 Global interrupt flag */

+#define BDMA_ISR_TCIF3_Pos      (13U)

+#define BDMA_ISR_TCIF3_Msk      (0x1UL << BDMA_ISR_TCIF3_Pos)                  /*!< 0x00002000 */

+#define BDMA_ISR_TCIF3          BDMA_ISR_TCIF3_Msk                             /*!< Channel 3 Transfer Complete flag */

+#define BDMA_ISR_HTIF3_Pos      (14U)

+#define BDMA_ISR_HTIF3_Msk      (0x1UL << BDMA_ISR_HTIF3_Pos)                  /*!< 0x00004000 */

+#define BDMA_ISR_HTIF3          BDMA_ISR_HTIF3_Msk                             /*!< Channel 3 Half Transfer flag */

+#define BDMA_ISR_TEIF3_Pos      (15U)

+#define BDMA_ISR_TEIF3_Msk      (0x1UL << BDMA_ISR_TEIF3_Pos)                  /*!< 0x00008000 */

+#define BDMA_ISR_TEIF3          BDMA_ISR_TEIF3_Msk                             /*!< Channel 3 Transfer Error flag */

+#define BDMA_ISR_GIF4_Pos       (16U)

+#define BDMA_ISR_GIF4_Msk       (0x1UL << BDMA_ISR_GIF4_Pos)                   /*!< 0x00010000 */

+#define BDMA_ISR_GIF4           BDMA_ISR_GIF4_Msk                              /*!< Channel 4 Global interrupt flag */

+#define BDMA_ISR_TCIF4_Pos      (17U)

+#define BDMA_ISR_TCIF4_Msk      (0x1UL << BDMA_ISR_TCIF4_Pos)                  /*!< 0x00020000 */

+#define BDMA_ISR_TCIF4          BDMA_ISR_TCIF4_Msk                             /*!< Channel 4 Transfer Complete flag */

+#define BDMA_ISR_HTIF4_Pos      (18U)

+#define BDMA_ISR_HTIF4_Msk      (0x1UL << BDMA_ISR_HTIF4_Pos)                  /*!< 0x00040000 */

+#define BDMA_ISR_HTIF4          BDMA_ISR_HTIF4_Msk                             /*!< Channel 4 Half Transfer flag */

+#define BDMA_ISR_TEIF4_Pos      (19U)

+#define BDMA_ISR_TEIF4_Msk      (0x1UL << BDMA_ISR_TEIF4_Pos)                  /*!< 0x00080000 */

+#define BDMA_ISR_TEIF4          BDMA_ISR_TEIF4_Msk                             /*!< Channel 4 Transfer Error flag */

+#define BDMA_ISR_GIF5_Pos       (20U)

+#define BDMA_ISR_GIF5_Msk       (0x1UL << BDMA_ISR_GIF5_Pos)                   /*!< 0x00100000 */

+#define BDMA_ISR_GIF5           BDMA_ISR_GIF5_Msk                              /*!< Channel 5 Global interrupt flag */

+#define BDMA_ISR_TCIF5_Pos      (21U)

+#define BDMA_ISR_TCIF5_Msk      (0x1UL << BDMA_ISR_TCIF5_Pos)                  /*!< 0x00200000 */

+#define BDMA_ISR_TCIF5          BDMA_ISR_TCIF5_Msk                             /*!< Channel 5 Transfer Complete flag */

+#define BDMA_ISR_HTIF5_Pos      (22U)

+#define BDMA_ISR_HTIF5_Msk      (0x1UL << BDMA_ISR_HTIF5_Pos)                  /*!< 0x00400000 */

+#define BDMA_ISR_HTIF5          BDMA_ISR_HTIF5_Msk                             /*!< Channel 5 Half Transfer flag */

+#define BDMA_ISR_TEIF5_Pos      (23U)

+#define BDMA_ISR_TEIF5_Msk      (0x1UL << BDMA_ISR_TEIF5_Pos)                  /*!< 0x00800000 */

+#define BDMA_ISR_TEIF5          BDMA_ISR_TEIF5_Msk                             /*!< Channel 5 Transfer Error flag */

+#define BDMA_ISR_GIF6_Pos       (24U)

+#define BDMA_ISR_GIF6_Msk       (0x1UL << BDMA_ISR_GIF6_Pos)                   /*!< 0x01000000 */

+#define BDMA_ISR_GIF6           BDMA_ISR_GIF6_Msk                              /*!< Channel 6 Global interrupt flag */

+#define BDMA_ISR_TCIF6_Pos      (25U)

+#define BDMA_ISR_TCIF6_Msk      (0x1UL << BDMA_ISR_TCIF6_Pos)                  /*!< 0x02000000 */

+#define BDMA_ISR_TCIF6          BDMA_ISR_TCIF6_Msk                             /*!< Channel 6 Transfer Complete flag */

+#define BDMA_ISR_HTIF6_Pos      (26U)

+#define BDMA_ISR_HTIF6_Msk      (0x1UL << BDMA_ISR_HTIF6_Pos)                  /*!< 0x04000000 */

+#define BDMA_ISR_HTIF6          BDMA_ISR_HTIF6_Msk                             /*!< Channel 6 Half Transfer flag */

+#define BDMA_ISR_TEIF6_Pos      (27U)

+#define BDMA_ISR_TEIF6_Msk      (0x1UL << BDMA_ISR_TEIF6_Pos)                  /*!< 0x08000000 */

+#define BDMA_ISR_TEIF6          BDMA_ISR_TEIF6_Msk                             /*!< Channel 6 Transfer Error flag */

+#define BDMA_ISR_GIF7_Pos       (28U)

+#define BDMA_ISR_GIF7_Msk       (0x1UL << BDMA_ISR_GIF7_Pos)                   /*!< 0x10000000 */

+#define BDMA_ISR_GIF7           BDMA_ISR_GIF7_Msk                              /*!< Channel 7 Global interrupt flag */

+#define BDMA_ISR_TCIF7_Pos      (29U)

+#define BDMA_ISR_TCIF7_Msk      (0x1UL << BDMA_ISR_TCIF7_Pos)                  /*!< 0x20000000 */

+#define BDMA_ISR_TCIF7          BDMA_ISR_TCIF7_Msk                             /*!< Channel 7 Transfer Complete flag */

+#define BDMA_ISR_HTIF7_Pos      (30U)

+#define BDMA_ISR_HTIF7_Msk      (0x1UL << BDMA_ISR_HTIF7_Pos)                  /*!< 0x40000000 */

+#define BDMA_ISR_HTIF7          BDMA_ISR_HTIF7_Msk                             /*!< Channel 7 Half Transfer flag */

+#define BDMA_ISR_TEIF7_Pos      (31U)

+#define BDMA_ISR_TEIF7_Msk      (0x1UL << BDMA_ISR_TEIF7_Pos)                  /*!< 0x80000000 */

+#define BDMA_ISR_TEIF7          BDMA_ISR_TEIF7_Msk                             /*!< Channel 7 Transfer Error flag */

+

+/*******************  Bit definition for BDMA_IFCR register  *******************/

+#define BDMA_IFCR_CGIF0_Pos     (0U)

+#define BDMA_IFCR_CGIF0_Msk     (0x1UL << BDMA_IFCR_CGIF0_Pos)                 /*!< 0x00000001 */

+#define BDMA_IFCR_CGIF0         BDMA_IFCR_CGIF0_Msk                            /*!< Channel 0 Global interrupt clearr */

+#define BDMA_IFCR_CTCIF0_Pos    (1U)

+#define BDMA_IFCR_CTCIF0_Msk    (0x1UL << BDMA_IFCR_CTCIF0_Pos)                /*!< 0x00000002 */

+#define BDMA_IFCR_CTCIF0        BDMA_IFCR_CTCIF0_Msk                           /*!< Channel 0 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF0_Pos    (2U)

+#define BDMA_IFCR_CHTIF0_Msk    (0x1UL << BDMA_IFCR_CHTIF0_Pos)                /*!< 0x00000004 */

+#define BDMA_IFCR_CHTIF0        BDMA_IFCR_CHTIF0_Msk                           /*!< Channel 0 Half Transfer clear */

+#define BDMA_IFCR_CTEIF0_Pos    (3U)

+#define BDMA_IFCR_CTEIF0_Msk    (0x1UL << BDMA_IFCR_CTEIF0_Pos)                /*!< 0x00000008 */

+#define BDMA_IFCR_CTEIF0        BDMA_IFCR_CTEIF0_Msk                           /*!< Channel 0 Transfer Error clear */

+#define BDMA_IFCR_CGIF1_Pos     (4U)

+#define BDMA_IFCR_CGIF1_Msk     (0x1UL << BDMA_IFCR_CGIF1_Pos)                 /*!< 0x00000010 */

+#define BDMA_IFCR_CGIF1         BDMA_IFCR_CGIF1_Msk                            /*!< Channel 1 Global interrupt clear */

+#define BDMA_IFCR_CTCIF1_Pos    (5U)

+#define BDMA_IFCR_CTCIF1_Msk    (0x1UL << BDMA_IFCR_CTCIF1_Pos)                /*!< 0x00000020 */

+#define BDMA_IFCR_CTCIF1        BDMA_IFCR_CTCIF1_Msk                           /*!< Channel 1 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF1_Pos    (6U)

+#define BDMA_IFCR_CHTIF1_Msk    (0x1UL << BDMA_IFCR_CHTIF1_Pos)                /*!< 0x00000040 */

+#define BDMA_IFCR_CHTIF1        BDMA_IFCR_CHTIF1_Msk                           /*!< Channel 1 Half Transfer clear */

+#define BDMA_IFCR_CTEIF1_Pos    (7U)

+#define BDMA_IFCR_CTEIF1_Msk    (0x1UL << BDMA_IFCR_CTEIF1_Pos)                /*!< 0x00000080 */

+#define BDMA_IFCR_CTEIF1        BDMA_IFCR_CTEIF1_Msk                           /*!< Channel 1 Transfer Error clear */

+#define BDMA_IFCR_CGIF2_Pos     (8U)

+#define BDMA_IFCR_CGIF2_Msk     (0x1UL << BDMA_IFCR_CGIF2_Pos)                 /*!< 0x00000100 */

+#define BDMA_IFCR_CGIF2         BDMA_IFCR_CGIF2_Msk                            /*!< Channel 2 Global interrupt clear */

+#define BDMA_IFCR_CTCIF2_Pos    (9U)

+#define BDMA_IFCR_CTCIF2_Msk    (0x1UL << BDMA_IFCR_CTCIF2_Pos)                /*!< 0x00000200 */

+#define BDMA_IFCR_CTCIF2        BDMA_IFCR_CTCIF2_Msk                           /*!< Channel 2 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF2_Pos    (10U)

+#define BDMA_IFCR_CHTIF2_Msk    (0x1UL << BDMA_IFCR_CHTIF2_Pos)                /*!< 0x00000400 */

+#define BDMA_IFCR_CHTIF2        BDMA_IFCR_CHTIF2_Msk                           /*!< Channel 2 Half Transfer clear */

+#define BDMA_IFCR_CTEIF2_Pos    (11U)

+#define BDMA_IFCR_CTEIF2_Msk    (0x1UL << BDMA_IFCR_CTEIF2_Pos)                /*!< 0x00000800 */

+#define BDMA_IFCR_CTEIF2        BDMA_IFCR_CTEIF2_Msk                           /*!< Channel 2 Transfer Error clear */

+#define BDMA_IFCR_CGIF3_Pos     (12U)

+#define BDMA_IFCR_CGIF3_Msk     (0x1UL << BDMA_IFCR_CGIF3_Pos)                 /*!< 0x00001000 */

+#define BDMA_IFCR_CGIF3         BDMA_IFCR_CGIF3_Msk                            /*!< Channel 3 Global interrupt clear */

+#define BDMA_IFCR_CTCIF3_Pos    (13U)

+#define BDMA_IFCR_CTCIF3_Msk    (0x1UL << BDMA_IFCR_CTCIF3_Pos)                /*!< 0x00002000 */

+#define BDMA_IFCR_CTCIF3        BDMA_IFCR_CTCIF3_Msk                           /*!< Channel 3 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF3_Pos    (14U)

+#define BDMA_IFCR_CHTIF3_Msk    (0x1UL << BDMA_IFCR_CHTIF3_Pos)                /*!< 0x00004000 */

+#define BDMA_IFCR_CHTIF3        BDMA_IFCR_CHTIF3_Msk                           /*!< Channel 3 Half Transfer clear */

+#define BDMA_IFCR_CTEIF3_Pos    (15U)

+#define BDMA_IFCR_CTEIF3_Msk    (0x1UL << BDMA_IFCR_CTEIF3_Pos)                /*!< 0x00008000 */

+#define BDMA_IFCR_CTEIF3        BDMA_IFCR_CTEIF3_Msk                           /*!< Channel 3 Transfer Error clear */

+#define BDMA_IFCR_CGIF4_Pos     (16U)

+#define BDMA_IFCR_CGIF4_Msk     (0x1UL << BDMA_IFCR_CGIF4_Pos)                 /*!< 0x00010000 */

+#define BDMA_IFCR_CGIF4         BDMA_IFCR_CGIF4_Msk                            /*!< Channel 4 Global interrupt clear */

+#define BDMA_IFCR_CTCIF4_Pos    (17U)

+#define BDMA_IFCR_CTCIF4_Msk    (0x1UL << BDMA_IFCR_CTCIF4_Pos)                /*!< 0x00020000 */

+#define BDMA_IFCR_CTCIF4        BDMA_IFCR_CTCIF4_Msk                           /*!< Channel 4 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF4_Pos    (18U)

+#define BDMA_IFCR_CHTIF4_Msk    (0x1UL << BDMA_IFCR_CHTIF4_Pos)                /*!< 0x00040000 */

+#define BDMA_IFCR_CHTIF4        BDMA_IFCR_CHTIF4_Msk                           /*!< Channel 4 Half Transfer clear */

+#define BDMA_IFCR_CTEIF4_Pos    (19U)

+#define BDMA_IFCR_CTEIF4_Msk    (0x1UL << BDMA_IFCR_CTEIF4_Pos)                /*!< 0x00080000 */

+#define BDMA_IFCR_CTEIF4        BDMA_IFCR_CTEIF4_Msk                           /*!< Channel 4 Transfer Error clear */

+#define BDMA_IFCR_CGIF5_Pos     (20U)

+#define BDMA_IFCR_CGIF5_Msk     (0x1UL << BDMA_IFCR_CGIF5_Pos)                 /*!< 0x00100000 */

+#define BDMA_IFCR_CGIF5         BDMA_IFCR_CGIF5_Msk                            /*!< Channel 5 Global interrupt clear */

+#define BDMA_IFCR_CTCIF5_Pos    (21U)

+#define BDMA_IFCR_CTCIF5_Msk    (0x1UL << BDMA_IFCR_CTCIF5_Pos)                /*!< 0x00200000 */

+#define BDMA_IFCR_CTCIF5        BDMA_IFCR_CTCIF5_Msk                           /*!< Channel 5 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF5_Pos    (22U)

+#define BDMA_IFCR_CHTIF5_Msk    (0x1UL << BDMA_IFCR_CHTIF5_Pos)                /*!< 0x00400000 */

+#define BDMA_IFCR_CHTIF5        BDMA_IFCR_CHTIF5_Msk                           /*!< Channel 5 Half Transfer clear */

+#define BDMA_IFCR_CTEIF5_Pos    (23U)

+#define BDMA_IFCR_CTEIF5_Msk    (0x1UL << BDMA_IFCR_CTEIF5_Pos)                /*!< 0x00800000 */

+#define BDMA_IFCR_CTEIF5        BDMA_IFCR_CTEIF5_Msk                           /*!< Channel 5 Transfer Error clear */

+#define BDMA_IFCR_CGIF6_Pos     (24U)

+#define BDMA_IFCR_CGIF6_Msk     (0x1UL << BDMA_IFCR_CGIF6_Pos)                 /*!< 0x01000000 */

+#define BDMA_IFCR_CGIF6         BDMA_IFCR_CGIF6_Msk                            /*!< Channel 6 Global interrupt clear */

+#define BDMA_IFCR_CTCIF6_Pos    (25U)

+#define BDMA_IFCR_CTCIF6_Msk    (0x1UL << BDMA_IFCR_CTCIF6_Pos)                /*!< 0x02000000 */

+#define BDMA_IFCR_CTCIF6        BDMA_IFCR_CTCIF6_Msk                           /*!< Channel 6 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF6_Pos    (26U)

+#define BDMA_IFCR_CHTIF6_Msk    (0x1UL << BDMA_IFCR_CHTIF6_Pos)                /*!< 0x04000000 */

+#define BDMA_IFCR_CHTIF6        BDMA_IFCR_CHTIF6_Msk                           /*!< Channel 6 Half Transfer clear */

+#define BDMA_IFCR_CTEIF6_Pos    (27U)

+#define BDMA_IFCR_CTEIF6_Msk    (0x1UL << BDMA_IFCR_CTEIF6_Pos)                /*!< 0x08000000 */

+#define BDMA_IFCR_CTEIF6        BDMA_IFCR_CTEIF6_Msk                           /*!< Channel 6 Transfer Error clear */

+#define BDMA_IFCR_CGIF7_Pos     (28U)

+#define BDMA_IFCR_CGIF7_Msk     (0x1UL << BDMA_IFCR_CGIF7_Pos)                 /*!< 0x10000000 */

+#define BDMA_IFCR_CGIF7         BDMA_IFCR_CGIF7_Msk                            /*!< Channel 7 Global interrupt clear */

+#define BDMA_IFCR_CTCIF7_Pos    (29U)

+#define BDMA_IFCR_CTCIF7_Msk    (0x1UL << BDMA_IFCR_CTCIF7_Pos)                /*!< 0x20000000 */

+#define BDMA_IFCR_CTCIF7        BDMA_IFCR_CTCIF7_Msk                           /*!< Channel 7 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF7_Pos    (30U)

+#define BDMA_IFCR_CHTIF7_Msk    (0x1UL << BDMA_IFCR_CHTIF7_Pos)                /*!< 0x40000000 */

+#define BDMA_IFCR_CHTIF7        BDMA_IFCR_CHTIF7_Msk                           /*!< Channel 7 Half Transfer clear */

+#define BDMA_IFCR_CTEIF7_Pos    (31U)

+#define BDMA_IFCR_CTEIF7_Msk    (0x1UL << BDMA_IFCR_CTEIF7_Pos)                /*!< 0x80000000 */

+#define BDMA_IFCR_CTEIF7        BDMA_IFCR_CTEIF7_Msk                           /*!< Channel 7 Transfer Error clear */

+

+/*******************  Bit definition for BDMA_CCR register  ********************/

+#define BDMA_CCR_EN_Pos         (0U)

+#define BDMA_CCR_EN_Msk         (0x1UL << BDMA_CCR_EN_Pos)                     /*!< 0x00000001 */

+#define BDMA_CCR_EN             BDMA_CCR_EN_Msk                                /*!< Channel enable                      */

+#define BDMA_CCR_TCIE_Pos       (1U)

+#define BDMA_CCR_TCIE_Msk       (0x1UL << BDMA_CCR_TCIE_Pos)                   /*!< 0x00000002 */

+#define BDMA_CCR_TCIE           BDMA_CCR_TCIE_Msk                              /*!< Transfer complete interrupt enable  */

+#define BDMA_CCR_HTIE_Pos       (2U)

+#define BDMA_CCR_HTIE_Msk       (0x1UL << BDMA_CCR_HTIE_Pos)                   /*!< 0x00000004 */

+#define BDMA_CCR_HTIE           BDMA_CCR_HTIE_Msk                              /*!< Half Transfer interrupt enable      */

+#define BDMA_CCR_TEIE_Pos       (3U)

+#define BDMA_CCR_TEIE_Msk       (0x1UL << BDMA_CCR_TEIE_Pos)                   /*!< 0x00000008 */

+#define BDMA_CCR_TEIE           BDMA_CCR_TEIE_Msk                              /*!< Transfer error interrupt enable     */

+#define BDMA_CCR_DIR_Pos        (4U)

+#define BDMA_CCR_DIR_Msk        (0x1UL << BDMA_CCR_DIR_Pos)                    /*!< 0x00000010 */

+#define BDMA_CCR_DIR            BDMA_CCR_DIR_Msk                               /*!< Data transfer direction             */

+#define BDMA_CCR_CIRC_Pos       (5U)

+#define BDMA_CCR_CIRC_Msk       (0x1UL << BDMA_CCR_CIRC_Pos)                   /*!< 0x00000020 */

+#define BDMA_CCR_CIRC           BDMA_CCR_CIRC_Msk                              /*!< Circular mode                       */

+#define BDMA_CCR_PINC_Pos       (6U)

+#define BDMA_CCR_PINC_Msk       (0x1UL << BDMA_CCR_PINC_Pos)                   /*!< 0x00000040 */

+#define BDMA_CCR_PINC           BDMA_CCR_PINC_Msk                              /*!< Peripheral increment mode           */

+#define BDMA_CCR_MINC_Pos       (7U)

+#define BDMA_CCR_MINC_Msk       (0x1UL << BDMA_CCR_MINC_Pos)                   /*!< 0x00000080 */

+#define BDMA_CCR_MINC           BDMA_CCR_MINC_Msk                              /*!< Memory increment mode               */

+

+#define BDMA_CCR_PSIZE_Pos      (8U)

+#define BDMA_CCR_PSIZE_Msk      (0x3UL << BDMA_CCR_PSIZE_Pos)                  /*!< 0x00000300 */

+#define BDMA_CCR_PSIZE          BDMA_CCR_PSIZE_Msk                             /*!< PSIZE[1:0] bits (Peripheral size)   */

+#define BDMA_CCR_PSIZE_0        (0x1UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000100 */

+#define BDMA_CCR_PSIZE_1        (0x2UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000200 */

+

+#define BDMA_CCR_MSIZE_Pos      (10U)

+#define BDMA_CCR_MSIZE_Msk      (0x3UL << BDMA_CCR_MSIZE_Pos)                  /*!< 0x00000C00 */

+#define BDMA_CCR_MSIZE          BDMA_CCR_MSIZE_Msk                             /*!< MSIZE[1:0] bits (Memory size)       */

+#define BDMA_CCR_MSIZE_0        (0x1UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000400 */

+#define BDMA_CCR_MSIZE_1        (0x2UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000800 */

+

+#define BDMA_CCR_PL_Pos         (12U)

+#define BDMA_CCR_PL_Msk         (0x3UL << BDMA_CCR_PL_Pos)                     /*!< 0x00003000 */

+#define BDMA_CCR_PL             BDMA_CCR_PL_Msk                                /*!< PL[1:0] bits(Channel Priority level)*/

+#define BDMA_CCR_PL_0           (0x1UL << BDMA_CCR_PL_Pos)                      /*!< 0x00001000 */

+#define BDMA_CCR_PL_1           (0x2UL << BDMA_CCR_PL_Pos)                      /*!< 0x00002000 */

+

+#define BDMA_CCR_MEM2MEM_Pos    (14U)

+#define BDMA_CCR_MEM2MEM_Msk    (0x1UL << BDMA_CCR_MEM2MEM_Pos)                /*!< 0x00004000 */

+#define BDMA_CCR_MEM2MEM        BDMA_CCR_MEM2MEM_Msk                           /*!< Memory to memory mode               */

+#define BDMA_CCR_DBM_Pos        (15U)

+#define BDMA_CCR_DBM_Msk        (0x1UL << BDMA_CCR_DBM_Pos)                    /*!< 0x0000A000 */

+#define BDMA_CCR_DBM            BDMA_CCR_DBM_Msk                               /*!< Memory to memory mode               */

+#define BDMA_CCR_CT_Pos         (16U)

+#define BDMA_CCR_CT_Msk         (0x1UL << BDMA_CCR_CT_Pos)                     /*!< 0x00010000 */

+#define BDMA_CCR_CT             BDMA_CCR_CT_Msk                                /*!< Memory to memory mode               */

+

+/******************  Bit definition for BDMA_CNDTR register  *******************/

+#define BDMA_CNDTR_NDT_Pos      (0U)

+#define BDMA_CNDTR_NDT_Msk      (0xFFFFUL << BDMA_CNDTR_NDT_Pos)               /*!< 0x0000FFFF */

+#define BDMA_CNDTR_NDT          BDMA_CNDTR_NDT_Msk                             /*!< Number of data to Transfer          */

+

+/******************  Bit definition for BDMA_CPAR register  ********************/

+#define BDMA_CPAR_PA_Pos        (0U)

+#define BDMA_CPAR_PA_Msk        (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CPAR_PA            BDMA_CPAR_PA_Msk                               /*!< Peripheral Address                  */

+

+/******************  Bit definition for BDMA_CM0AR register  ********************/

+#define BDMA_CM0AR_MA_Pos        (0U)

+#define BDMA_CM0AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CM0AR_MA            BDMA_CM0AR_MA_Msk                               /*!< Memory Address                      */

+

+/******************  Bit definition for BDMA_CM1AR register  ********************/

+#define BDMA_CM1AR_MA_Pos        (0U)

+#define BDMA_CM1AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CM1AR_MA            BDMA_CM1AR_MA_Msk                               /*!< Memory Address                      */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             DMA Controller                                 */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DMA_SxCR register  *****************/

+#define DMA_SxCR_MBURST_Pos      (23U)

+#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                /*!< 0x01800000 */

+#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk                           /*!< Memory burst transfer configuration */

+#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */

+#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */

+#define DMA_SxCR_PBURST_Pos      (21U)

+#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                /*!< 0x00600000 */

+#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk                           /*!< Peripheral burst transfer configuration */

+#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */

+#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */

+#define DMA_SxCR_TRBUFF_Pos      (20U)

+#define DMA_SxCR_TRBUFF_Msk      (0x1UL << DMA_SxCR_TRBUFF_Pos)                 /*!< 0x00100000 */

+#define DMA_SxCR_TRBUFF          DMA_SxCR_TRBUFF_Msk                            /*!< bufferable transfers enabled/disable */

+#define DMA_SxCR_CT_Pos          (19U)

+#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                    /*!< 0x00080000 */

+#define DMA_SxCR_CT              DMA_SxCR_CT_Msk                               /*!< Current target (only in double buffer mode) */

+#define DMA_SxCR_DBM_Pos         (18U)

+#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                   /*!< 0x00040000 */

+#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk                              /*!< Double buffer mode */

+#define DMA_SxCR_PL_Pos          (16U)

+#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                    /*!< 0x00030000 */

+#define DMA_SxCR_PL              DMA_SxCR_PL_Msk                               /*!< Priority level */

+#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */

+#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */

+#define DMA_SxCR_PINCOS_Pos      (15U)

+#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                /*!< 0x00008000 */

+#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk                           /*!< Peripheral increment offset size */

+#define DMA_SxCR_MSIZE_Pos       (13U)

+#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                 /*!< 0x00006000 */

+#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk                            /*!< Memory data size */

+#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */

+#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */

+#define DMA_SxCR_PSIZE_Pos       (11U)

+#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                 /*!< 0x00001800 */

+#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk                            /*< Peripheral data size */

+#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */

+#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */

+#define DMA_SxCR_MINC_Pos        (10U)

+#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                  /*!< 0x00000400 */

+#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk                             /*!< Memory increment mode */

+#define DMA_SxCR_PINC_Pos        (9U)

+#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                  /*!< 0x00000200 */

+#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk                             /*!< Peripheral increment mode */

+#define DMA_SxCR_CIRC_Pos        (8U)

+#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                  /*!< 0x00000100 */

+#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk                             /*!< Circular mode */

+#define DMA_SxCR_DIR_Pos         (6U)

+#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                   /*!< 0x000000C0 */

+#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk                              /*!< Data transfer direction */

+#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */

+#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */

+#define DMA_SxCR_PFCTRL_Pos      (5U)

+#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                /*!< 0x00000020 */

+#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk                           /*!< Peripheral flow controller */

+#define DMA_SxCR_TCIE_Pos        (4U)

+#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                  /*!< 0x00000010 */

+#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk                             /*!< Transfer complete interrupt enable */

+#define DMA_SxCR_HTIE_Pos        (3U)

+#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                  /*!< 0x00000008 */

+#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk                             /*!< Half transfer interrupt enable */

+#define DMA_SxCR_TEIE_Pos        (2U)

+#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                  /*!< 0x00000004 */

+#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk                             /*!< Transfer error interrupt enable */

+#define DMA_SxCR_DMEIE_Pos       (1U)

+#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                 /*!< 0x00000002 */

+#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk                            /*!< Direct mode error interrupt enable */

+#define DMA_SxCR_EN_Pos          (0U)

+#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                    /*!< 0x00000001 */

+#define DMA_SxCR_EN              DMA_SxCR_EN_Msk                               /*!< Stream enable / flag stream ready when read low */

+

+/********************  Bits definition for DMA_SxCNDTR register  **************/

+#define DMA_SxNDT_Pos            (0U)

+#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                   /*!< 0x0000FFFF */

+#define DMA_SxNDT                DMA_SxNDT_Msk                                 /*!< Number of data items to transfer */

+#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */

+#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */

+#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */

+#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */

+#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */

+#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */

+#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */

+#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */

+#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */

+#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */

+#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */

+#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */

+#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */

+#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */

+#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */

+#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */

+

+/********************  Bits definition for DMA_SxFCR register  ****************/

+#define DMA_SxFCR_FEIE_Pos       (7U)

+#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                 /*!< 0x00000080 */

+#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk                            /*!< FIFO error interrupt enable */

+#define DMA_SxFCR_FS_Pos         (3U)

+#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                   /*!< 0x00000038 */

+#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk                              /*!< FIFO status */

+#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */

+#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */

+#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */

+#define DMA_SxFCR_DMDIS_Pos      (2U)

+#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                /*!< 0x00000004 */

+#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk                           /*!< Direct mode disable */

+#define DMA_SxFCR_FTH_Pos        (0U)

+#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                  /*!< 0x00000003 */

+#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk                             /*!< FIFO threshold selection */

+#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */

+#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */

+

+/********************  Bits definition for DMA_LISR register  *****************/

+#define DMA_LISR_TCIF3_Pos       (27U)

+#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                 /*!< 0x08000000 */

+#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk                            /*!<  Stream 3 transfer complete interrupt flag */

+#define DMA_LISR_HTIF3_Pos       (26U)

+#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                 /*!< 0x04000000 */

+#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk                            /*!<  Stream 3 half transfer interrupt flag */

+#define DMA_LISR_TEIF3_Pos       (25U)

+#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                 /*!< 0x02000000 */

+#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk                            /*!<  Stream 3 transfer error interrupt flag */

+#define DMA_LISR_DMEIF3_Pos      (24U)

+#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                /*!< 0x01000000 */

+#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk                           /*!<  Stream 3 direct mode error interrupt flag */

+#define DMA_LISR_FEIF3_Pos       (22U)

+#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                 /*!< 0x00400000 */

+#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk                            /*!<  Stream 3 FIFO error interrupt flag */

+#define DMA_LISR_TCIF2_Pos       (21U)

+#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                 /*!< 0x00200000 */

+#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk                            /*!<  Stream 2 transfer complete interrupt flag */

+#define DMA_LISR_HTIF2_Pos       (20U)

+#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                 /*!< 0x00100000 */

+#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk                            /*!<  Stream 2 half transfer interrupt flag */

+#define DMA_LISR_TEIF2_Pos       (19U)

+#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                 /*!< 0x00080000 */

+#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk                            /*!<  Stream 2 transfer error interrupt flag */

+#define DMA_LISR_DMEIF2_Pos      (18U)

+#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                /*!< 0x00040000 */

+#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk                           /*!<  Stream 2 direct mode error interrupt flag */

+#define DMA_LISR_FEIF2_Pos       (16U)

+#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                 /*!< 0x00010000 */

+#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk                            /*!<  Stream 2 FIFO error interrupt flag */

+#define DMA_LISR_TCIF1_Pos       (11U)

+#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                 /*!< 0x00000800 */

+#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk                            /*!<  Stream 1 transfer complete interrupt flag */

+#define DMA_LISR_HTIF1_Pos       (10U)

+#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                 /*!< 0x00000400 */

+#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk                            /*!<  Stream 1 half transfer interrupt flag */

+#define DMA_LISR_TEIF1_Pos       (9U)

+#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                 /*!< 0x00000200 */

+#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk                            /*!<  Stream 1 transfer error interrupt flag */

+#define DMA_LISR_DMEIF1_Pos      (8U)

+#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                /*!< 0x00000100 */

+#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk                           /*!<  Stream 1 direct mode error interrupt flag */

+#define DMA_LISR_FEIF1_Pos       (6U)

+#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                 /*!< 0x00000040 */

+#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk                            /*!<  Stream 1 FIFO error interrupt flag */

+#define DMA_LISR_TCIF0_Pos       (5U)

+#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                 /*!< 0x00000020 */

+#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk                            /*!<  Stream 0 transfer complete interrupt flag */

+#define DMA_LISR_HTIF0_Pos       (4U)

+#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                 /*!< 0x00000010 */

+#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk                            /*!<  Stream 0 half transfer interrupt flag */

+#define DMA_LISR_TEIF0_Pos       (3U)

+#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                 /*!< 0x00000008 */

+#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk                            /*!<  Stream 0 transfer error interrupt flag */

+#define DMA_LISR_DMEIF0_Pos      (2U)

+#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                /*!< 0x00000004 */

+#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk                           /*!<  Stream 0 direct mode error interrupt flag */

+#define DMA_LISR_FEIF0_Pos       (0U)

+#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                 /*!< 0x00000001 */

+#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk                            /*!<  Stream 0 FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_HISR register  *****************/

+#define DMA_HISR_TCIF7_Pos       (27U)

+#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                 /*!< 0x08000000 */

+#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk                            /*!<  Stream 7 transfer complete interrupt flag */

+#define DMA_HISR_HTIF7_Pos       (26U)

+#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                 /*!< 0x04000000 */

+#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk                            /*!<  Stream 7 half transfer interrupt flag */

+#define DMA_HISR_TEIF7_Pos       (25U)

+#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                 /*!< 0x02000000 */

+#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk                            /*!<  Stream 7 transfer error interrupt flag */

+#define DMA_HISR_DMEIF7_Pos      (24U)

+#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                /*!< 0x01000000 */

+#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk                           /*!<  Stream 7 direct mode error interrupt flag */

+#define DMA_HISR_FEIF7_Pos       (22U)

+#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                 /*!< 0x00400000 */

+#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk                            /*!<  Stream 7 FIFO error interrupt flag */

+#define DMA_HISR_TCIF6_Pos       (21U)

+#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                 /*!< 0x00200000 */

+#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk                            /*!<  Stream 6 transfer complete interrupt flag */

+#define DMA_HISR_HTIF6_Pos       (20U)

+#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                 /*!< 0x00100000 */

+#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk                            /*!<  Stream 6 half transfer interrupt flag */

+#define DMA_HISR_TEIF6_Pos       (19U)

+#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                 /*!< 0x00080000 */

+#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk                            /*!<  Stream 6 transfer error interrupt flag */

+#define DMA_HISR_DMEIF6_Pos      (18U)

+#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                /*!< 0x00040000 */

+#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk                           /*!<  Stream 6 direct mode error interrupt flag */

+#define DMA_HISR_FEIF6_Pos       (16U)

+#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                 /*!< 0x00010000 */

+#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk                            /*!<  Stream 6 FIFO error interrupt flag */

+#define DMA_HISR_TCIF5_Pos       (11U)

+#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                 /*!< 0x00000800 */

+#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk                            /*!<  Stream 5 transfer complete interrupt flag */

+#define DMA_HISR_HTIF5_Pos       (10U)

+#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                 /*!< 0x00000400 */

+#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk                            /*!<  Stream 5 half transfer interrupt flag */

+#define DMA_HISR_TEIF5_Pos       (9U)

+#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                 /*!< 0x00000200 */

+#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk                            /*!<  Stream 5 transfer error interrupt flag */

+#define DMA_HISR_DMEIF5_Pos      (8U)

+#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                /*!< 0x00000100 */

+#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk                           /*!<  Stream 5 direct mode error interrupt flag */

+#define DMA_HISR_FEIF5_Pos       (6U)

+#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                 /*!< 0x00000040 */

+#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk                            /*!<  Stream 5 FIFO error interrupt flag */

+#define DMA_HISR_TCIF4_Pos       (5U)

+#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                 /*!< 0x00000020 */

+#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk                            /*!<  Stream 4 transfer complete interrupt flag */

+#define DMA_HISR_HTIF4_Pos       (4U)

+#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                 /*!< 0x00000010 */

+#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk                            /*!<  Stream 4 half transfer interrupt flag */

+#define DMA_HISR_TEIF4_Pos       (3U)

+#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                 /*!< 0x00000008 */

+#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk                            /*!<  Stream 4 transfer error interrupt flag */

+#define DMA_HISR_DMEIF4_Pos      (2U)

+#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                /*!< 0x00000004 */

+#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk                           /*!<  Stream 4 direct mode error interrupt flag */

+#define DMA_HISR_FEIF4_Pos       (0U)

+#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                 /*!< 0x00000001 */

+#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk                            /*!<  Stream 4 FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_LIFCR register  ****************/

+#define DMA_LIFCR_CTCIF3_Pos     (27U)

+#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)               /*!< 0x08000000 */

+#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk                          /*!<  Stream 3 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF3_Pos     (26U)

+#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)               /*!< 0x04000000 */

+#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk                          /*!<  Stream 3 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF3_Pos     (25U)

+#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)               /*!< 0x02000000 */

+#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk                          /*!<  Stream 3 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF3_Pos    (24U)

+#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)              /*!< 0x01000000 */

+#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk                         /*!<  Stream 3 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF3_Pos     (22U)

+#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)               /*!< 0x00400000 */

+#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk                          /*!<  Stream 3 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF2_Pos     (21U)

+#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)               /*!< 0x00200000 */

+#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk                          /*!<  Stream 2 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF2_Pos     (20U)

+#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)               /*!< 0x00100000 */

+#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk                          /*!<  Stream 2 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF2_Pos     (19U)

+#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)               /*!< 0x00080000 */

+#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk                          /*!<  Stream 2 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF2_Pos    (18U)

+#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)              /*!< 0x00040000 */

+#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk                         /*!<  Stream 2 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF2_Pos     (16U)

+#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)               /*!< 0x00010000 */

+#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk                          /*!<  Stream 2 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF1_Pos     (11U)

+#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)               /*!< 0x00000800 */

+#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk                          /*!<  Stream 1 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF1_Pos     (10U)

+#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)               /*!< 0x00000400 */

+#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk                          /*!<  Stream 1 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF1_Pos     (9U)

+#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)               /*!< 0x00000200 */

+#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk                          /*!<  Stream 1 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF1_Pos    (8U)

+#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)              /*!< 0x00000100 */

+#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk                         /*!<  Stream 1 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF1_Pos     (6U)

+#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)               /*!< 0x00000040 */

+#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk                          /*!<  Stream 1 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF0_Pos     (5U)

+#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)               /*!< 0x00000020 */

+#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk                          /*!<  Stream 0 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF0_Pos     (4U)

+#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)               /*!< 0x00000010 */

+#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk                          /*!<  Stream 0 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF0_Pos     (3U)

+#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)               /*!< 0x00000008 */

+#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk                          /*!<  Stream 0 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF0_Pos    (2U)

+#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)              /*!< 0x00000004 */

+#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk                         /*!<  Stream 0 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF0_Pos     (0U)

+#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)               /*!< 0x00000001 */

+#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk                          /*!<  Stream 0 clear FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_HIFCR  register  ****************/

+#define DMA_HIFCR_CTCIF7_Pos     (27U)

+#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)               /*!< 0x08000000 */

+#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk                          /*!<  Stream 7 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF7_Pos     (26U)

+#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)               /*!< 0x04000000 */

+#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk                          /*!<  Stream 7 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF7_Pos     (25U)

+#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)               /*!< 0x02000000 */

+#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk                          /*!<  Stream 7 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF7_Pos    (24U)

+#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)              /*!< 0x01000000 */

+#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk                         /*!<  Stream 7 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF7_Pos     (22U)

+#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)               /*!< 0x00400000 */

+#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk                          /*!<  Stream 7 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF6_Pos     (21U)

+#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)               /*!< 0x00200000 */

+#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk                          /*!<  Stream 6 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF6_Pos     (20U)

+#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)               /*!< 0x00100000 */

+#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk                          /*!<  Stream 6 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF6_Pos     (19U)

+#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)               /*!< 0x00080000 */

+#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk                          /*!<  Stream 6 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF6_Pos    (18U)

+#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)              /*!< 0x00040000 */

+#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk                         /*!<  Stream 6 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF6_Pos     (16U)

+#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)               /*!< 0x00010000 */

+#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk                          /*!<  Stream 6 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF5_Pos     (11U)

+#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)               /*!< 0x00000800 */

+#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk                          /*!<  Stream 5 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF5_Pos     (10U)

+#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)               /*!< 0x00000400 */

+#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk                          /*!<  Stream 5 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF5_Pos     (9U)

+#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)               /*!< 0x00000200 */

+#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk                          /*!<  Stream 5 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF5_Pos    (8U)

+#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)              /*!< 0x00000100 */

+#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk                         /*!<  Stream 5 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF5_Pos     (6U)

+#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)               /*!< 0x00000040 */

+#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk                          /*!<  Stream 5 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF4_Pos     (5U)

+#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)               /*!< 0x00000020 */

+#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk                          /*!<  Stream 4 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF4_Pos     (4U)

+#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)               /*!< 0x00000010 */

+#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk                          /*!<  Stream 4 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF4_Pos     (3U)

+#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)               /*!< 0x00000008 */

+#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk                          /*!<  Stream 4 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF4_Pos    (2U)

+#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)              /*!< 0x00000004 */

+#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk                         /*!<  Stream 4 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF4_Pos     (0U)

+#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)               /*!< 0x00000001 */

+#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk                          /*!<  Stream 4 clear FIFO error interrupt flag */

+

+/******************  Bit definition for DMA_SxPAR register  ********************/

+#define DMA_SxPAR_PA_Pos         (0U)

+#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)            /*!< 0xFFFFFFFF */

+#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */

+

+/******************  Bit definition for DMA_SxM0AR register  ********************/

+#define DMA_SxM0AR_M0A_Pos       (0U)

+#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)          /*!< 0xFFFFFFFF */

+#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory 0 Address */

+

+/******************  Bit definition for DMA_SxM1AR register  ********************/

+#define DMA_SxM1AR_M1A_Pos       (0U)

+#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)          /*!< 0xFFFFFFFF */

+#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory 1 Address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             DMAMUX Controller                              */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DMAMUX_CxCR register  **************/

+#define DMAMUX_CxCR_DMAREQ_ID_Pos      (0U)

+#define DMAMUX_CxCR_DMAREQ_ID_Msk      (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)   /*!< 0x000000FF */

+#define DMAMUX_CxCR_DMAREQ_ID          DMAMUX_CxCR_DMAREQ_ID_Msk               /*!<  DMA request identification */

+#define DMAMUX_CxCR_DMAREQ_ID_0        (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000001 */

+#define DMAMUX_CxCR_DMAREQ_ID_1        (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000002 */

+#define DMAMUX_CxCR_DMAREQ_ID_2        (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000004 */

+#define DMAMUX_CxCR_DMAREQ_ID_3        (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000008 */

+#define DMAMUX_CxCR_DMAREQ_ID_4        (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000010 */

+#define DMAMUX_CxCR_DMAREQ_ID_5        (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000020 */

+#define DMAMUX_CxCR_DMAREQ_ID_6        (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000040 */

+#define DMAMUX_CxCR_DMAREQ_ID_7        (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000080 */

+#define DMAMUX_CxCR_SOIE_Pos           (8U)

+#define DMAMUX_CxCR_SOIE_Msk           (0x1UL << DMAMUX_CxCR_SOIE_Pos)         /*!< 0x00000100 */

+#define DMAMUX_CxCR_SOIE               DMAMUX_CxCR_SOIE_Msk                    /*!<  Synchronization overrun interrupt enable */

+#define DMAMUX_CxCR_EGE_Pos            (9U)

+#define DMAMUX_CxCR_EGE_Msk            (0x1UL << DMAMUX_CxCR_EGE_Pos)          /*!< 0x00000200 */

+#define DMAMUX_CxCR_EGE                DMAMUX_CxCR_EGE_Msk                     /*!<  Event generation enable */

+#define DMAMUX_CxCR_SE_Pos             (16U)

+#define DMAMUX_CxCR_SE_Msk             (0x1UL << DMAMUX_CxCR_SE_Pos)           /*!< 0x00010000 */

+#define DMAMUX_CxCR_SE                 DMAMUX_CxCR_SE_Msk                      /*!<  Synchronization enable */

+#define DMAMUX_CxCR_SPOL_Pos           (17U)

+#define DMAMUX_CxCR_SPOL_Msk           (0x3UL << DMAMUX_CxCR_SPOL_Pos)         /*!< 0x00060000 */

+#define DMAMUX_CxCR_SPOL               DMAMUX_CxCR_SPOL_Msk                    /*!<  Synchronization polarity */

+#define DMAMUX_CxCR_SPOL_0             (0x1UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00020000 */

+#define DMAMUX_CxCR_SPOL_1             (0x2UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00040000 */

+#define DMAMUX_CxCR_NBREQ_Pos          (19U)

+#define DMAMUX_CxCR_NBREQ_Msk          (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)       /*!< 0x00F80000 */

+#define DMAMUX_CxCR_NBREQ              DMAMUX_CxCR_NBREQ_Msk                   /*!<  Number of DMA requests minus 1 to forward */

+#define DMAMUX_CxCR_NBREQ_0            (0x01UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00080000 */

+#define DMAMUX_CxCR_NBREQ_1            (0x02UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00100000 */

+#define DMAMUX_CxCR_NBREQ_2            (0x04UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00200000 */

+#define DMAMUX_CxCR_NBREQ_3            (0x08UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00400000 */

+#define DMAMUX_CxCR_NBREQ_4            (0x10UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00800000 */

+#define DMAMUX_CxCR_SYNC_ID_Pos        (24U)

+#define DMAMUX_CxCR_SYNC_ID_Msk        (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)     /*!< 0x1F000000 */

+#define DMAMUX_CxCR_SYNC_ID            DMAMUX_CxCR_SYNC_ID_Msk                 /*!<  Synchronization identification */

+#define DMAMUX_CxCR_SYNC_ID_0          (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x01000000 */

+#define DMAMUX_CxCR_SYNC_ID_1          (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x02000000 */

+#define DMAMUX_CxCR_SYNC_ID_2          (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x04000000 */

+#define DMAMUX_CxCR_SYNC_ID_3          (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x08000000 */

+#define DMAMUX_CxCR_SYNC_ID_4          (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x10000000 */

+

+/********************  Bits definition for DMAMUX_CSR register  **************/

+#define DMAMUX_CSR_SOF0_Pos            (0U)

+#define DMAMUX_CSR_SOF0_Msk            (0x1UL << DMAMUX_CSR_SOF0_Pos)          /*!< 0x00000001 */

+#define DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0_Msk                     /*!< Channel 0 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF1_Pos            (1U)

+#define DMAMUX_CSR_SOF1_Msk            (0x1UL << DMAMUX_CSR_SOF1_Pos)          /*!< 0x00000002 */

+#define DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1_Msk                     /*!< Channel 1 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF2_Pos            (2U)

+#define DMAMUX_CSR_SOF2_Msk            (0x1UL << DMAMUX_CSR_SOF2_Pos)          /*!< 0x00000004 */

+#define DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2_Msk                     /*!< Channel 2 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF3_Pos            (3U)

+#define DMAMUX_CSR_SOF3_Msk            (0x1UL << DMAMUX_CSR_SOF3_Pos)          /*!< 0x00000008 */

+#define DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3_Msk                     /*!< Channel 3 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF4_Pos            (4U)

+#define DMAMUX_CSR_SOF4_Msk            (0x1UL << DMAMUX_CSR_SOF4_Pos)          /*!< 0x00000010 */

+#define DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4_Msk                     /*!< Channel 4 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF5_Pos            (5U)

+#define DMAMUX_CSR_SOF5_Msk            (0x1UL << DMAMUX_CSR_SOF5_Pos)          /*!< 0x00000020 */

+#define DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5_Msk                     /*!< Channel 5 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF6_Pos            (6U)

+#define DMAMUX_CSR_SOF6_Msk            (0x1UL << DMAMUX_CSR_SOF6_Pos)          /*!< 0x00000040 */

+#define DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6_Msk                     /*!< Channel 6 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF7_Pos            (7U)

+#define DMAMUX_CSR_SOF7_Msk            (0x1UL << DMAMUX_CSR_SOF7_Pos)          /*!< 0x00000080 */

+#define DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7_Msk                     /*!< Channel 7 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF8_Pos            (8U)

+#define DMAMUX_CSR_SOF8_Msk            (0x1UL << DMAMUX_CSR_SOF8_Pos)          /*!< 0x00000100 */

+#define DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8_Msk                     /*!< Channel 8 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF9_Pos            (9U)

+#define DMAMUX_CSR_SOF9_Msk            (0x1UL << DMAMUX_CSR_SOF9_Pos)          /*!< 0x00000200 */

+#define DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9_Msk                     /*!< Channel 9 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF10_Pos           (10U)

+#define DMAMUX_CSR_SOF10_Msk           (0x1UL << DMAMUX_CSR_SOF10_Pos)         /*!< 0x00000400 */

+#define DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10_Msk                    /*!< Channel 10 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF11_Pos           (11U)

+#define DMAMUX_CSR_SOF11_Msk           (0x1UL << DMAMUX_CSR_SOF11_Pos)         /*!< 0x00000800 */

+#define DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11_Msk                    /*!< Channel 11 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF12_Pos           (12U)

+#define DMAMUX_CSR_SOF12_Msk           (0x1UL << DMAMUX_CSR_SOF12_Pos)         /*!< 0x00001000 */

+#define DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12_Msk                    /*!< Channel 12 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF13_Pos           (13U)

+#define DMAMUX_CSR_SOF13_Msk           (0x1UL << DMAMUX_CSR_SOF13_Pos)         /*!< 0x00002000 */

+#define DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13_Msk                    /*!< Channel 13 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF14_Pos           (14U)

+#define DMAMUX_CSR_SOF14_Msk           (0x1UL << DMAMUX_CSR_SOF14_Pos)         /*!< 0x00004000 */

+#define DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14_Msk                    /*!< Channel 14 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF15_Pos           (15U)

+#define DMAMUX_CSR_SOF15_Msk           (0x1UL << DMAMUX_CSR_SOF15_Pos)         /*!< 0x00008000 */

+#define DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15_Msk                    /*!< Channel 15 Synchronization overrun event flag */

+

+/********************  Bits definition for DMAMUX_CFR register  **************/

+#define DMAMUX_CFR_CSOF0_Pos           (0U)

+#define DMAMUX_CFR_CSOF0_Msk           (0x1UL << DMAMUX_CFR_CSOF0_Pos)         /*!< 0x00000001 */

+#define DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0_Msk                    /*!< Channel 0 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF1_Pos           (1U)

+#define DMAMUX_CFR_CSOF1_Msk           (0x1UL << DMAMUX_CFR_CSOF1_Pos)         /*!< 0x00000002 */

+#define DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1_Msk                    /*!< Channel 1 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF2_Pos           (2U)

+#define DMAMUX_CFR_CSOF2_Msk           (0x1UL << DMAMUX_CFR_CSOF2_Pos)         /*!< 0x00000004 */

+#define DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2_Msk                    /*!< Channel 2 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF3_Pos           (3U)

+#define DMAMUX_CFR_CSOF3_Msk           (0x1UL << DMAMUX_CFR_CSOF3_Pos)         /*!< 0x00000008 */

+#define DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3_Msk                    /*!< Channel 3 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF4_Pos           (4U)

+#define DMAMUX_CFR_CSOF4_Msk           (0x1UL << DMAMUX_CFR_CSOF4_Pos)         /*!< 0x00000010 */

+#define DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4_Msk                    /*!< Channel 4 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF5_Pos           (5U)

+#define DMAMUX_CFR_CSOF5_Msk           (0x1UL << DMAMUX_CFR_CSOF5_Pos)         /*!< 0x00000020 */

+#define DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5_Msk                    /*!< Channel 5 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF6_Pos           (6U)

+#define DMAMUX_CFR_CSOF6_Msk           (0x1UL << DMAMUX_CFR_CSOF6_Pos)         /*!< 0x00000040 */

+#define DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6_Msk                    /*!< Channel 6 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF7_Pos           (7U)

+#define DMAMUX_CFR_CSOF7_Msk           (0x1UL << DMAMUX_CFR_CSOF7_Pos)         /*!< 0x00000080 */

+#define DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7_Msk                    /*!< Channel 7 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF8_Pos           (8U)

+#define DMAMUX_CFR_CSOF8_Msk           (0x1UL << DMAMUX_CFR_CSOF8_Pos)         /*!< 0x00000100 */

+#define DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8_Msk                    /*!< Channel 8 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF9_Pos           (9U)

+#define DMAMUX_CFR_CSOF9_Msk           (0x1UL << DMAMUX_CFR_CSOF9_Pos)         /*!< 0x00000200 */

+#define DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9_Msk                    /*!< Channel 9 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF10_Pos          (10U)

+#define DMAMUX_CFR_CSOF10_Msk          (0x1UL << DMAMUX_CFR_CSOF10_Pos)        /*!< 0x00000400 */

+#define DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10_Msk                   /*!< Channel 10 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF11_Pos          (11U)

+#define DMAMUX_CFR_CSOF11_Msk          (0x1UL << DMAMUX_CFR_CSOF11_Pos)        /*!< 0x00000800 */

+#define DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11_Msk                   /*!< Channel 11 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF12_Pos          (12U)

+#define DMAMUX_CFR_CSOF12_Msk          (0x1UL << DMAMUX_CFR_CSOF12_Pos)        /*!< 0x00001000 */

+#define DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12_Msk                   /*!< Channel 12 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF13_Pos          (13U)

+#define DMAMUX_CFR_CSOF13_Msk          (0x1UL << DMAMUX_CFR_CSOF13_Pos)        /*!< 0x00002000 */

+#define DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13_Msk                   /*!< Channel 13 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF14_Pos          (14U)

+#define DMAMUX_CFR_CSOF14_Msk          (0x1UL << DMAMUX_CFR_CSOF14_Pos)        /*!< 0x00004000 */

+#define DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14_Msk                   /*!< Channel 14 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF15_Pos          (15U)

+#define DMAMUX_CFR_CSOF15_Msk          (0x1UL << DMAMUX_CFR_CSOF15_Pos)        /*!< 0x00008000 */

+#define DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15_Msk                   /*!< Channel 15 Clear synchronization overrun event flag */

+

+/********************  Bits definition for DMAMUX_RGxCR register  ************/

+#define DMAMUX_RGxCR_SIG_ID_Pos        (0U)

+#define DMAMUX_RGxCR_SIG_ID_Msk        (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)     /*!< 0x0000001F */

+#define DMAMUX_RGxCR_SIG_ID            DMAMUX_RGxCR_SIG_ID_Msk                 /*!< Signal identification */

+#define DMAMUX_RGxCR_SIG_ID_0          (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000001 */

+#define DMAMUX_RGxCR_SIG_ID_1          (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000002 */

+#define DMAMUX_RGxCR_SIG_ID_2          (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000004 */

+#define DMAMUX_RGxCR_SIG_ID_3          (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000008 */

+#define DMAMUX_RGxCR_SIG_ID_4          (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000010 */

+#define DMAMUX_RGxCR_OIE_Pos           (8U)

+#define DMAMUX_RGxCR_OIE_Msk           (0x1UL << DMAMUX_RGxCR_OIE_Pos)         /*!< 0x00000100 */

+#define DMAMUX_RGxCR_OIE               DMAMUX_RGxCR_OIE_Msk                    /*!< Trigger overrun interrupt enable */

+#define DMAMUX_RGxCR_GE_Pos            (16U)

+#define DMAMUX_RGxCR_GE_Msk            (0x1UL << DMAMUX_RGxCR_GE_Pos)          /*!< 0x00010000 */

+#define DMAMUX_RGxCR_GE                DMAMUX_RGxCR_GE_Msk                     /*!< DMA request generator enable */

+#define DMAMUX_RGxCR_GPOL_Pos          (17U)

+#define DMAMUX_RGxCR_GPOL_Msk          (0x3UL << DMAMUX_RGxCR_GPOL_Pos)        /*!< 0x00060000 */

+#define DMAMUX_RGxCR_GPOL              DMAMUX_RGxCR_GPOL_Msk                   /*!< DMA request generator trigger polarity */

+#define DMAMUX_RGxCR_GPOL_0            (0x1UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00020000 */

+#define DMAMUX_RGxCR_GPOL_1            (0x2UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00040000 */

+#define DMAMUX_RGxCR_GNBREQ_Pos        (19U)

+#define DMAMUX_RGxCR_GNBREQ_Msk        (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)     /*!< 0x00F80000 */

+#define DMAMUX_RGxCR_GNBREQ            DMAMUX_RGxCR_GNBREQ_Msk                 /*!< Number of DMA requests to be generated */

+#define DMAMUX_RGxCR_GNBREQ_0          (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00080000 */

+#define DMAMUX_RGxCR_GNBREQ_1          (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00100000 */

+#define DMAMUX_RGxCR_GNBREQ_2          (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00200000 */

+#define DMAMUX_RGxCR_GNBREQ_3          (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00400000 */

+#define DMAMUX_RGxCR_GNBREQ_4          (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00800000 */

+

+/********************  Bits definition for DMAMUX_RGSR register  **************/

+#define DMAMUX_RGSR_OF0_Pos            (0U)

+#define DMAMUX_RGSR_OF0_Msk            (0x1UL << DMAMUX_RGSR_OF0_Pos)          /*!< 0x00000001 */

+#define DMAMUX_RGSR_OF0                DMAMUX_RGSR_OF0_Msk                     /*!< Request generator channel 0 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF1_Pos            (1U)

+#define DMAMUX_RGSR_OF1_Msk            (0x1UL << DMAMUX_RGSR_OF1_Pos)          /*!< 0x00000002 */

+#define DMAMUX_RGSR_OF1                DMAMUX_RGSR_OF1_Msk                     /*!< Request generator channel 1 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF2_Pos            (2U)

+#define DMAMUX_RGSR_OF2_Msk            (0x1UL << DMAMUX_RGSR_OF2_Pos)          /*!< 0x00000004 */

+#define DMAMUX_RGSR_OF2                DMAMUX_RGSR_OF2_Msk                     /*!< Request generator channel 2 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF3_Pos            (3U)

+#define DMAMUX_RGSR_OF3_Msk            (0x1UL << DMAMUX_RGSR_OF3_Pos)          /*!< 0x00000008 */

+#define DMAMUX_RGSR_OF3                DMAMUX_RGSR_OF3_Msk                     /*!< Request generator channel 3 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF4_Pos            (4U)

+#define DMAMUX_RGSR_OF4_Msk            (0x1UL << DMAMUX_RGSR_OF4_Pos)          /*!< 0x00000010 */

+#define DMAMUX_RGSR_OF4                DMAMUX_RGSR_OF4_Msk                     /*!< Request generator channel 4 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF5_Pos            (5U)

+#define DMAMUX_RGSR_OF5_Msk            (0x1UL << DMAMUX_RGSR_OF5_Pos)          /*!< 0x00000020 */

+#define DMAMUX_RGSR_OF5                DMAMUX_RGSR_OF5_Msk                     /*!< Request generator channel 5 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF6_Pos            (6U)

+#define DMAMUX_RGSR_OF6_Msk            (0x1UL << DMAMUX_RGSR_OF6_Pos)          /*!< 0x00000040 */

+#define DMAMUX_RGSR_OF6                DMAMUX_RGSR_OF6_Msk                     /*!< Request generator channel 6 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF7_Pos            (7U)

+#define DMAMUX_RGSR_OF7_Msk            (0x1UL << DMAMUX_RGSR_OF7_Pos)          /*!< 0x00000080 */

+#define DMAMUX_RGSR_OF7                DMAMUX_RGSR_OF7_Msk                     /*!< Request generator channel 7 Trigger overrun event flag */

+

+/********************  Bits definition for DMAMUX_RGCFR register  **************/

+#define DMAMUX_RGCFR_COF0_Pos          (0U)

+#define DMAMUX_RGCFR_COF0_Msk          (0x1UL << DMAMUX_RGCFR_COF0_Pos)        /*!< 0x00000001 */

+#define DMAMUX_RGCFR_COF0              DMAMUX_RGCFR_COF0_Msk                   /*!< Request generator channel 0 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF1_Pos          (1U)

+#define DMAMUX_RGCFR_COF1_Msk          (0x1UL << DMAMUX_RGCFR_COF1_Pos)        /*!< 0x00000002 */

+#define DMAMUX_RGCFR_COF1              DMAMUX_RGCFR_COF1_Msk                   /*!< Request generator channel 1 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF2_Pos          (2U)

+#define DMAMUX_RGCFR_COF2_Msk          (0x1UL << DMAMUX_RGCFR_COF2_Pos)        /*!< 0x00000004 */

+#define DMAMUX_RGCFR_COF2              DMAMUX_RGCFR_COF2_Msk                   /*!< Request generator channel 2 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF3_Pos          (3U)

+#define DMAMUX_RGCFR_COF3_Msk          (0x1UL << DMAMUX_RGCFR_COF3_Pos)        /*!< 0x00000008 */

+#define DMAMUX_RGCFR_COF3              DMAMUX_RGCFR_COF3_Msk                   /*!< Request generator channel 3 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF4_Pos          (4U)

+#define DMAMUX_RGCFR_COF4_Msk          (0x1UL << DMAMUX_RGCFR_COF4_Pos)        /*!< 0x00000010 */

+#define DMAMUX_RGCFR_COF4              DMAMUX_RGCFR_COF4_Msk                   /*!< Request generator channel 4 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF5_Pos          (5U)

+#define DMAMUX_RGCFR_COF5_Msk          (0x1UL << DMAMUX_RGCFR_COF5_Pos)        /*!< 0x00000020 */

+#define DMAMUX_RGCFR_COF5              DMAMUX_RGCFR_COF5_Msk                   /*!< Request generator channel 5 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF6_Pos          (6U)

+#define DMAMUX_RGCFR_COF6_Msk          (0x1UL << DMAMUX_RGCFR_COF6_Pos)        /*!< 0x00000040 */

+#define DMAMUX_RGCFR_COF6              DMAMUX_RGCFR_COF6_Msk                   /*!< Request generator channel 6 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF7_Pos          (7U)

+#define DMAMUX_RGCFR_COF7_Msk          (0x1UL << DMAMUX_RGCFR_COF7_Pos)        /*!< 0x00000080 */

+#define DMAMUX_RGCFR_COF7              DMAMUX_RGCFR_COF7_Msk                   /*!< Request generator channel 7 Clear trigger overrun event flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         AHB Master DMA2D Controller (DMA2D)                */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for DMA2D_CR register  ******************/

+

+#define DMA2D_CR_START_Pos         (0U)

+#define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)               /*!< 0x00000001 */

+#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer                          */

+#define DMA2D_CR_SUSP_Pos          (1U)

+#define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                /*!< 0x00000002 */

+#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer                        */

+#define DMA2D_CR_ABORT_Pos         (2U)

+#define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)               /*!< 0x00000004 */

+#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer                          */

+#define DMA2D_CR_LOM_Pos           (6U)

+#define DMA2D_CR_LOM_Msk           (0x1UL << DMA2D_CR_LOM_Pos)                 /*!< 0x00000040 */

+#define DMA2D_CR_LOM               DMA2D_CR_LOM_Msk                            /*!< Line Offset Mode                         */

+#define DMA2D_CR_TEIE_Pos          (8U)

+#define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                /*!< 0x00000100 */

+#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable         */

+#define DMA2D_CR_TCIE_Pos          (9U)

+#define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                /*!< 0x00000200 */

+#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable      */

+#define DMA2D_CR_TWIE_Pos          (10U)

+#define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                /*!< 0x00000400 */

+#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable     */

+#define DMA2D_CR_CAEIE_Pos         (11U)

+#define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)               /*!< 0x00000800 */

+#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable      */

+#define DMA2D_CR_CTCIE_Pos         (12U)

+#define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)               /*!< 0x00001000 */

+#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */

+#define DMA2D_CR_CEIE_Pos          (13U)

+#define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                /*!< 0x00002000 */

+#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable    */

+#define DMA2D_CR_MODE_Pos          (16U)

+#define DMA2D_CR_MODE_Msk          (0x7UL << DMA2D_CR_MODE_Pos)                /*!< 0x00070000 */

+#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[2:0]                         */

+#define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */

+#define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */

+#define DMA2D_CR_MODE_2            (0x4UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00040000 */

+

+/********************  Bit definition for DMA2D_ISR register  *****************/

+

+#define DMA2D_ISR_TEIF_Pos         (0U)

+#define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)               /*!< 0x00000001 */

+#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag         */

+#define DMA2D_ISR_TCIF_Pos         (1U)

+#define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)               /*!< 0x00000002 */

+#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag      */

+#define DMA2D_ISR_TWIF_Pos         (2U)

+#define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)               /*!< 0x00000004 */

+#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag     */

+#define DMA2D_ISR_CAEIF_Pos        (3U)

+#define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)              /*!< 0x00000008 */

+#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag      */

+#define DMA2D_ISR_CTCIF_Pos        (4U)

+#define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)              /*!< 0x00000010 */

+#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */

+#define DMA2D_ISR_CEIF_Pos         (5U)

+#define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)               /*!< 0x00000020 */

+#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag    */

+

+/********************  Bit definition for DMA2D_IFCR register  ****************/

+

+#define DMA2D_IFCR_CTEIF_Pos       (0U)

+#define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)             /*!< 0x00000001 */

+#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */

+#define DMA2D_IFCR_CTCIF_Pos       (1U)

+#define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)             /*!< 0x00000002 */

+#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */

+#define DMA2D_IFCR_CTWIF_Pos       (2U)

+#define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)             /*!< 0x00000004 */

+#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */

+#define DMA2D_IFCR_CAECIF_Pos      (3U)

+#define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)            /*!< 0x00000008 */

+#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */

+#define DMA2D_IFCR_CCTCIF_Pos      (4U)

+#define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)            /*!< 0x00000010 */

+#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */

+#define DMA2D_IFCR_CCEIF_Pos       (5U)

+#define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)             /*!< 0x00000020 */

+#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */

+

+/********************  Bit definition for DMA2D_FGMAR register  ***************/

+

+#define DMA2D_FGMAR_MA_Pos         (0U)

+#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)        /*!< 0xFFFFFFFF */

+#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Foreground Memory Address */

+

+/********************  Bit definition for DMA2D_FGOR register  ****************/

+

+#define DMA2D_FGOR_LO_Pos          (0U)

+#define DMA2D_FGOR_LO_Msk          (0xFFFFUL << DMA2D_FGOR_LO_Pos)             /*!< 0x0000FFFF */

+#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */

+

+/********************  Bit definition for DMA2D_BGMAR register  ***************/

+

+#define DMA2D_BGMAR_MA_Pos         (0U)

+#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)        /*!< 0xFFFFFFFF */

+#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Background Memory Address */

+

+/********************  Bit definition for DMA2D_BGOR register  ****************/

+

+#define DMA2D_BGOR_LO_Pos          (0U)

+#define DMA2D_BGOR_LO_Msk          (0xFFFFUL << DMA2D_BGOR_LO_Pos)             /*!< 0x0000FFFF */

+#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */

+

+/********************  Bit definition for DMA2D_FGPFCCR register  *************/

+

+#define DMA2D_FGPFCCR_CM_Pos       (0U)

+#define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x0000000F */

+#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */

+#define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */

+#define DMA2D_FGPFCCR_CCM_Pos      (4U)

+#define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)            /*!< 0x00000010 */

+#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */

+#define DMA2D_FGPFCCR_START_Pos    (5U)

+#define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)          /*!< 0x00000020 */

+#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */

+#define DMA2D_FGPFCCR_CS_Pos       (8U)

+#define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)            /*!< 0x0000FF00 */

+#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */

+#define DMA2D_FGPFCCR_AM_Pos       (16U)

+#define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00030000 */

+#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */

+#define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */

+#define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */

+#define DMA2D_FGPFCCR_CSS_Pos      (18U)

+#define DMA2D_FGPFCCR_CSS_Msk      (0x3UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x000C0000 */

+#define DMA2D_FGPFCCR_CSS          DMA2D_FGPFCCR_CSS_Msk                       /* !< Chroma Sub-Sampling */

+#define DMA2D_FGPFCCR_CSS_0        (0x1UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00040000 */

+#define DMA2D_FGPFCCR_CSS_1        (0x2UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00080000 */

+#define DMA2D_FGPFCCR_AI_Pos       (20U)

+#define DMA2D_FGPFCCR_AI_Msk       (0x1UL << DMA2D_FGPFCCR_AI_Pos)             /*!< 0x00100000 */

+#define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Foreground Input Alpha Inverted */

+#define DMA2D_FGPFCCR_RBS_Pos      (21U)

+#define DMA2D_FGPFCCR_RBS_Msk      (0x1UL << DMA2D_FGPFCCR_RBS_Pos)            /*!< 0x00200000 */

+#define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Foreground Input Red Blue Swap */

+#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)

+#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */

+#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */

+

+/********************  Bit definition for DMA2D_FGCOLR register  **************/

+

+#define DMA2D_FGCOLR_BLUE_Pos      (0U)

+#define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)           /*!< 0x000000FF */

+#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Foreground Blue Value */

+#define DMA2D_FGCOLR_GREEN_Pos     (8U)

+#define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */

+#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Foreground Green Value */

+#define DMA2D_FGCOLR_RED_Pos       (16U)

+#define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)            /*!< 0x00FF0000 */

+#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Foreground Red Value */

+

+/********************  Bit definition for DMA2D_BGPFCCR register  *************/

+

+#define DMA2D_BGPFCCR_CM_Pos       (0U)

+#define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x0000000F */

+#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */

+#define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_BGPFCCR_CM_3         (0x8UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000008 */

+#define DMA2D_BGPFCCR_CCM_Pos      (4U)

+#define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)            /*!< 0x00000010 */

+#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */

+#define DMA2D_BGPFCCR_START_Pos    (5U)

+#define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)          /*!< 0x00000020 */

+#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */

+#define DMA2D_BGPFCCR_CS_Pos       (8U)

+#define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)            /*!< 0x0000FF00 */

+#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */

+#define DMA2D_BGPFCCR_AM_Pos       (16U)

+#define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00030000 */

+#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */

+#define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */

+#define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */

+#define DMA2D_BGPFCCR_AI_Pos       (20U)

+#define DMA2D_BGPFCCR_AI_Msk       (0x1UL << DMA2D_BGPFCCR_AI_Pos)             /*!< 0x00100000 */

+#define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< background Input Alpha Inverted */

+#define DMA2D_BGPFCCR_RBS_Pos      (21U)

+#define DMA2D_BGPFCCR_RBS_Msk      (0x1UL << DMA2D_BGPFCCR_RBS_Pos)            /*!< 0x00200000 */

+#define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Background Input Red Blue Swap */

+#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)

+#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */

+#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */

+

+/********************  Bit definition for DMA2D_BGCOLR register  **************/

+

+#define DMA2D_BGCOLR_BLUE_Pos      (0U)

+#define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)           /*!< 0x000000FF */

+#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Background Blue Value */

+#define DMA2D_BGCOLR_GREEN_Pos     (8U)

+#define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */

+#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Background Green Value */

+#define DMA2D_BGCOLR_RED_Pos       (16U)

+#define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)            /*!< 0x00FF0000 */

+#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Background Red Value */

+

+/********************  Bit definition for DMA2D_FGCMAR register  **************/

+

+#define DMA2D_FGCMAR_MA_Pos        (0U)

+#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */

+#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Foreground CLUT Memory Address */

+

+/********************  Bit definition for DMA2D_BGCMAR register  **************/

+

+#define DMA2D_BGCMAR_MA_Pos        (0U)

+#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */

+#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Background CLUT Memory Address */

+

+/********************  Bit definition for DMA2D_OPFCCR register  **************/

+

+#define DMA2D_OPFCCR_CM_Pos        (0U)

+#define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000007 */

+#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Output Color mode CM[2:0] */

+#define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_OPFCCR_SB_Pos        (8U)

+#define DMA2D_OPFCCR_SB_Msk        (0x1UL << DMA2D_OPFCCR_SB_Pos)              /*!< 0x00000100 */

+#define DMA2D_OPFCCR_SB            DMA2D_OPFCCR_SB_Msk                         /*!< Swap Bytes */

+#define DMA2D_OPFCCR_AI_Pos        (20U)

+#define DMA2D_OPFCCR_AI_Msk        (0x1UL << DMA2D_OPFCCR_AI_Pos)              /*!< 0x00100000 */

+#define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Output Alpha Inverted */

+#define DMA2D_OPFCCR_RBS_Pos       (21U)

+#define DMA2D_OPFCCR_RBS_Msk       (0x1UL << DMA2D_OPFCCR_RBS_Pos)             /*!< 0x00200000 */

+#define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Output Red Blue Swap */

+

+/********************  Bit definition for DMA2D_OCOLR register  ***************/

+

+/*!<Mode_ARGB8888/RGB888 */

+

+#define DMA2D_OCOLR_BLUE_1_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_1_Msk     (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos)            /*0x000000FFU*/

+#define DMA2D_OCOLR_BLUE_1         DMA2D_OCOLR_BLUE_1_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_1_Pos    (8U)

+#define DMA2D_OCOLR_GREEN_1_Msk    (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos)            /*0x0000FF00U)*/

+#define DMA2D_OCOLR_GREEN_1        DMA2D_OCOLR_GREEN_1_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_1_Pos      (16U)

+#define DMA2D_OCOLR_RED_1_Msk      (0xFFUL << DMA2D_OCOLR_RED_1_Pos)            /*0x00FF0000U */

+#define DMA2D_OCOLR_RED_1          DMA2D_OCOLR_RED_1_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_1_Pos    (24U)

+#define DMA2D_OCOLR_ALPHA_1_Msk    (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos)          /*0xFF000000U*/

+#define DMA2D_OCOLR_ALPHA_1        DMA2D_OCOLR_ALPHA_1_Msk                     /*!< Output Alpha Channel Value */

+

+/*!<Mode_RGB565 */

+#define DMA2D_OCOLR_BLUE_2_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_2_Msk     (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos)            /*0x0000001FU*/

+#define DMA2D_OCOLR_BLUE_2         DMA2D_OCOLR_BLUE_2_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_2_Pos    (5U)

+#define DMA2D_OCOLR_GREEN_2_Msk    (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos)          /* 0x000007E0U */

+#define DMA2D_OCOLR_GREEN_2        DMA2D_OCOLR_GREEN_2_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_2_Pos      (11U)

+#define DMA2D_OCOLR_RED_2_Msk      (0xF8UL<<DMA2D_OCOLR_RED_2_Pos)              /*0x0000F800U*/

+#define DMA2D_OCOLR_RED_2          DMA2D_OCOLR_RED_2_Msk                       /*!< Output Red Value */

+

+/*!<Mode_ARGB1555 */

+#define DMA2D_OCOLR_BLUE_3_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_3_Msk     (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos)           /*0x0000001FU*/

+#define DMA2D_OCOLR_BLUE_3         DMA2D_OCOLR_BLUE_3_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_3_Pos    (5U)

+#define DMA2D_OCOLR_GREEN_3_Msk    (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos)          /*0x000003E0U*/

+#define DMA2D_OCOLR_GREEN_3        DMA2D_OCOLR_GREEN_3_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_3_Pos      (10U)

+#define DMA2D_OCOLR_RED_3_Msk      (0x7CUL << DMA2D_OCOLR_RED_3_Pos)            /* 0x00007C00U*/

+#define DMA2D_OCOLR_RED_3          DMA2D_OCOLR_RED_3_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_3_Pos    (15U)

+#define DMA2D_OCOLR_ALPHA_3_Msk    (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos)           /*0x00008000U*/

+#define DMA2D_OCOLR_ALPHA_3        DMA2D_OCOLR_ALPHA_3_Msk                     /*!< Output Alpha Channel Value */

+

+/*!<Mode_ARGB4444 */

+#define DMA2D_OCOLR_BLUE_4_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_4_Msk     (0xFUL << DMA2D_OCOLR_BLUE_4_Pos)            /*0x0000000FU*/

+#define DMA2D_OCOLR_BLUE_4         DMA2D_OCOLR_BLUE_4_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_4_Pos    (4U)

+#define DMA2D_OCOLR_GREEN_4_Msk    (0xFUL << DMA2D_OCOLR_GREEN_4_Pos)           /*0x000000F0U*/

+#define DMA2D_OCOLR_GREEN_4        DMA2D_OCOLR_GREEN_4_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_4_Pos      (8U)

+#define DMA2D_OCOLR_RED_4_Msk      (0xFUL << DMA2D_OCOLR_RED_4_Pos)             /*0x00000F00U*/

+#define DMA2D_OCOLR_RED_4          DMA2D_OCOLR_RED_4_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_4_Pos    (12U)

+#define DMA2D_OCOLR_ALPHA_4_Msk    (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos)            /*0x0000F000U*/

+#define DMA2D_OCOLR_ALPHA_4        DMA2D_OCOLR_ALPHA_4_Msk                     /*!< Output Alpha Channel Value */

+

+/********************  Bit definition for DMA2D_OMAR register  ****************/

+

+#define DMA2D_OMAR_MA_Pos          (0U)

+#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)         /*!< 0xFFFFFFFF */

+#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Output Memory Address */

+

+/********************  Bit definition for DMA2D_OOR register  *****************/

+

+#define DMA2D_OOR_LO_Pos           (0U)

+#define DMA2D_OOR_LO_Msk           (0xFFFFUL << DMA2D_OOR_LO_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Output Line Offset */

+

+/********************  Bit definition for DMA2D_NLR register  *****************/

+

+#define DMA2D_NLR_NL_Pos           (0U)

+#define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */

+#define DMA2D_NLR_PL_Pos           (16U)

+#define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)              /*!< 0x3FFF0000 */

+#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */

+

+/********************  Bit definition for DMA2D_LWR register  *****************/

+

+#define DMA2D_LWR_LW_Pos           (0U)

+#define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */

+

+/********************  Bit definition for DMA2D_AMTCR register  ***************/

+

+#define DMA2D_AMTCR_EN_Pos         (0U)

+#define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)               /*!< 0x00000001 */

+#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */

+#define DMA2D_AMTCR_DT_Pos         (8U)

+#define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)              /*!< 0x0000FF00 */

+#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */

+

+

+/********************  Bit definition for DMA2D_FGCLUT register  **************/

+

+/********************  Bit definition for DMA2D_BGCLUT register  **************/

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                    External Interrupt/Event Controller                     */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for EXTI_RTSR1 register  *******************/

+#define EXTI_RTSR1_TR_Pos          (0U)

+#define EXTI_RTSR1_TR_Msk          (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)           /*!< 0x003FFFFF */

+#define EXTI_RTSR1_TR              EXTI_RTSR1_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR1_TR0_Pos         (0U)

+#define EXTI_RTSR1_TR0_Msk         (0x1UL << EXTI_RTSR1_TR0_Pos)               /*!< 0x00000001 */

+#define EXTI_RTSR1_TR0             EXTI_RTSR1_TR0_Msk                          /*!< Rising trigger event configuration bit of line 0 */

+#define EXTI_RTSR1_TR1_Pos         (1U)

+#define EXTI_RTSR1_TR1_Msk         (0x1UL << EXTI_RTSR1_TR1_Pos)               /*!< 0x00000002 */

+#define EXTI_RTSR1_TR1             EXTI_RTSR1_TR1_Msk                          /*!< Rising trigger event configuration bit of line 1 */

+#define EXTI_RTSR1_TR2_Pos         (2U)

+#define EXTI_RTSR1_TR2_Msk         (0x1UL << EXTI_RTSR1_TR2_Pos)               /*!< 0x00000004 */

+#define EXTI_RTSR1_TR2             EXTI_RTSR1_TR2_Msk                          /*!< Rising trigger event configuration bit of line 2 */

+#define EXTI_RTSR1_TR3_Pos         (3U)

+#define EXTI_RTSR1_TR3_Msk         (0x1UL << EXTI_RTSR1_TR3_Pos)               /*!< 0x00000008 */

+#define EXTI_RTSR1_TR3             EXTI_RTSR1_TR3_Msk                          /*!< Rising trigger event configuration bit of line 3 */

+#define EXTI_RTSR1_TR4_Pos         (4U)

+#define EXTI_RTSR1_TR4_Msk         (0x1UL << EXTI_RTSR1_TR4_Pos)               /*!< 0x00000010 */

+#define EXTI_RTSR1_TR4             EXTI_RTSR1_TR4_Msk                          /*!< Rising trigger event configuration bit of line 4 */

+#define EXTI_RTSR1_TR5_Pos         (5U)

+#define EXTI_RTSR1_TR5_Msk         (0x1UL << EXTI_RTSR1_TR5_Pos)               /*!< 0x00000020 */

+#define EXTI_RTSR1_TR5             EXTI_RTSR1_TR5_Msk                          /*!< Rising trigger event configuration bit of line 5 */

+#define EXTI_RTSR1_TR6_Pos         (6U)

+#define EXTI_RTSR1_TR6_Msk         (0x1UL << EXTI_RTSR1_TR6_Pos)               /*!< 0x00000040 */

+#define EXTI_RTSR1_TR6             EXTI_RTSR1_TR6_Msk                          /*!< Rising trigger event configuration bit of line 6 */

+#define EXTI_RTSR1_TR7_Pos         (7U)

+#define EXTI_RTSR1_TR7_Msk         (0x1UL << EXTI_RTSR1_TR7_Pos)               /*!< 0x00000080 */

+#define EXTI_RTSR1_TR7             EXTI_RTSR1_TR7_Msk                          /*!< Rising trigger event configuration bit of line 7 */

+#define EXTI_RTSR1_TR8_Pos         (8U)

+#define EXTI_RTSR1_TR8_Msk         (0x1UL << EXTI_RTSR1_TR8_Pos)               /*!< 0x00000100 */

+#define EXTI_RTSR1_TR8             EXTI_RTSR1_TR8_Msk                          /*!< Rising trigger event configuration bit of line 8 */

+#define EXTI_RTSR1_TR9_Pos         (9U)

+#define EXTI_RTSR1_TR9_Msk         (0x1UL << EXTI_RTSR1_TR9_Pos)               /*!< 0x00000200 */

+#define EXTI_RTSR1_TR9             EXTI_RTSR1_TR9_Msk                          /*!< Rising trigger event configuration bit of line 9 */

+#define EXTI_RTSR1_TR10_Pos        (10U)

+#define EXTI_RTSR1_TR10_Msk        (0x1UL << EXTI_RTSR1_TR10_Pos)              /*!< 0x00000400 */

+#define EXTI_RTSR1_TR10            EXTI_RTSR1_TR10_Msk                         /*!< Rising trigger event configuration bit of line 10 */

+#define EXTI_RTSR1_TR11_Pos        (11U)

+#define EXTI_RTSR1_TR11_Msk        (0x1UL << EXTI_RTSR1_TR11_Pos)              /*!< 0x00000800 */

+#define EXTI_RTSR1_TR11            EXTI_RTSR1_TR11_Msk                         /*!< Rising trigger event configuration bit of line 11 */

+#define EXTI_RTSR1_TR12_Pos        (12U)

+#define EXTI_RTSR1_TR12_Msk        (0x1UL << EXTI_RTSR1_TR12_Pos)              /*!< 0x00001000 */

+#define EXTI_RTSR1_TR12            EXTI_RTSR1_TR12_Msk                         /*!< Rising trigger event configuration bit of line 12 */

+#define EXTI_RTSR1_TR13_Pos        (13U)

+#define EXTI_RTSR1_TR13_Msk        (0x1UL << EXTI_RTSR1_TR13_Pos)              /*!< 0x00002000 */

+#define EXTI_RTSR1_TR13            EXTI_RTSR1_TR13_Msk                         /*!< Rising trigger event configuration bit of line 13 */

+#define EXTI_RTSR1_TR14_Pos        (14U)

+#define EXTI_RTSR1_TR14_Msk        (0x1UL << EXTI_RTSR1_TR14_Pos)              /*!< 0x00004000 */

+#define EXTI_RTSR1_TR14            EXTI_RTSR1_TR14_Msk                         /*!< Rising trigger event configuration bit of line 14 */

+#define EXTI_RTSR1_TR15_Pos        (15U)

+#define EXTI_RTSR1_TR15_Msk        (0x1UL << EXTI_RTSR1_TR15_Pos)              /*!< 0x00008000 */

+#define EXTI_RTSR1_TR15            EXTI_RTSR1_TR15_Msk                         /*!< Rising trigger event configuration bit of line 15 */

+#define EXTI_RTSR1_TR16_Pos        (16U)

+#define EXTI_RTSR1_TR16_Msk        (0x1UL << EXTI_RTSR1_TR16_Pos)              /*!< 0x00010000 */

+#define EXTI_RTSR1_TR16            EXTI_RTSR1_TR16_Msk                         /*!< Rising trigger event configuration bit of line 16 */

+#define EXTI_RTSR1_TR17_Pos        (17U)

+#define EXTI_RTSR1_TR17_Msk        (0x1UL << EXTI_RTSR1_TR17_Pos)              /*!< 0x00020000 */

+#define EXTI_RTSR1_TR17            EXTI_RTSR1_TR17_Msk                         /*!< Rising trigger event configuration bit of line 17 */

+#define EXTI_RTSR1_TR18_Pos        (18U)

+#define EXTI_RTSR1_TR18_Msk        (0x1UL << EXTI_RTSR1_TR18_Pos)              /*!< 0x00040000 */

+#define EXTI_RTSR1_TR18            EXTI_RTSR1_TR18_Msk                         /*!< Rising trigger event configuration bit of line 18 */

+#define EXTI_RTSR1_TR19_Pos        (19U)

+#define EXTI_RTSR1_TR19_Msk        (0x1UL << EXTI_RTSR1_TR19_Pos)              /*!< 0x00080000 */

+#define EXTI_RTSR1_TR19            EXTI_RTSR1_TR19_Msk                         /*!< Rising trigger event configuration bit of line 19 */

+#define EXTI_RTSR1_TR20_Pos        (20U)

+#define EXTI_RTSR1_TR20_Msk        (0x1UL << EXTI_RTSR1_TR20_Pos)              /*!< 0x00100000 */

+#define EXTI_RTSR1_TR20            EXTI_RTSR1_TR20_Msk                         /*!< Rising trigger event configuration bit of line 20 */

+#define EXTI_RTSR1_TR21_Pos        (21U)

+#define EXTI_RTSR1_TR21_Msk        (0x1UL << EXTI_RTSR1_TR21_Pos)              /*!< 0x00200000 */

+#define EXTI_RTSR1_TR21            EXTI_RTSR1_TR21_Msk                         /*!< Rising trigger event configuration bit of line 21 */

+

+/******************  Bit definition for EXTI_FTSR1 register  *******************/

+#define EXTI_FTSR1_TR_Pos          (0U)

+#define EXTI_FTSR1_TR_Msk          (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)           /*!< 0x003FFFFF */

+#define EXTI_FTSR1_TR              EXTI_FTSR1_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR1_TR0_Pos         (0U)

+#define EXTI_FTSR1_TR0_Msk         (0x1UL << EXTI_FTSR1_TR0_Pos)               /*!< 0x00000001 */

+#define EXTI_FTSR1_TR0             EXTI_FTSR1_TR0_Msk                          /*!< Falling trigger event configuration bit of line 0 */

+#define EXTI_FTSR1_TR1_Pos         (1U)

+#define EXTI_FTSR1_TR1_Msk         (0x1UL << EXTI_FTSR1_TR1_Pos)               /*!< 0x00000002 */

+#define EXTI_FTSR1_TR1             EXTI_FTSR1_TR1_Msk                          /*!< Falling trigger event configuration bit of line 1 */

+#define EXTI_FTSR1_TR2_Pos         (2U)

+#define EXTI_FTSR1_TR2_Msk         (0x1UL << EXTI_FTSR1_TR2_Pos)               /*!< 0x00000004 */

+#define EXTI_FTSR1_TR2             EXTI_FTSR1_TR2_Msk                          /*!< Falling trigger event configuration bit of line 2 */

+#define EXTI_FTSR1_TR3_Pos         (3U)

+#define EXTI_FTSR1_TR3_Msk         (0x1UL << EXTI_FTSR1_TR3_Pos)               /*!< 0x00000008 */

+#define EXTI_FTSR1_TR3             EXTI_FTSR1_TR3_Msk                          /*!< Falling trigger event configuration bit of line 3 */

+#define EXTI_FTSR1_TR4_Pos         (4U)

+#define EXTI_FTSR1_TR4_Msk         (0x1UL << EXTI_FTSR1_TR4_Pos)               /*!< 0x00000010 */

+#define EXTI_FTSR1_TR4             EXTI_FTSR1_TR4_Msk                          /*!< Falling trigger event configuration bit of line 4 */

+#define EXTI_FTSR1_TR5_Pos         (5U)

+#define EXTI_FTSR1_TR5_Msk         (0x1UL << EXTI_FTSR1_TR5_Pos)               /*!< 0x00000020 */

+#define EXTI_FTSR1_TR5             EXTI_FTSR1_TR5_Msk                          /*!< Falling trigger event configuration bit of line 5 */

+#define EXTI_FTSR1_TR6_Pos         (6U)

+#define EXTI_FTSR1_TR6_Msk         (0x1UL << EXTI_FTSR1_TR6_Pos)               /*!< 0x00000040 */

+#define EXTI_FTSR1_TR6             EXTI_FTSR1_TR6_Msk                          /*!< Falling trigger event configuration bit of line 6 */

+#define EXTI_FTSR1_TR7_Pos         (7U)

+#define EXTI_FTSR1_TR7_Msk         (0x1UL << EXTI_FTSR1_TR7_Pos)               /*!< 0x00000080 */

+#define EXTI_FTSR1_TR7             EXTI_FTSR1_TR7_Msk                          /*!< Falling trigger event configuration bit of line 7 */

+#define EXTI_FTSR1_TR8_Pos         (8U)

+#define EXTI_FTSR1_TR8_Msk         (0x1UL << EXTI_FTSR1_TR8_Pos)               /*!< 0x00000100 */

+#define EXTI_FTSR1_TR8             EXTI_FTSR1_TR8_Msk                          /*!< Falling trigger event configuration bit of line 8 */

+#define EXTI_FTSR1_TR9_Pos         (9U)

+#define EXTI_FTSR1_TR9_Msk         (0x1UL << EXTI_FTSR1_TR9_Pos)               /*!< 0x00000200 */

+#define EXTI_FTSR1_TR9             EXTI_FTSR1_TR9_Msk                          /*!< Falling trigger event configuration bit of line 9 */

+#define EXTI_FTSR1_TR10_Pos        (10U)

+#define EXTI_FTSR1_TR10_Msk        (0x1UL << EXTI_FTSR1_TR10_Pos)              /*!< 0x00000400 */

+#define EXTI_FTSR1_TR10            EXTI_FTSR1_TR10_Msk                         /*!< Falling trigger event configuration bit of line 10 */

+#define EXTI_FTSR1_TR11_Pos        (11U)

+#define EXTI_FTSR1_TR11_Msk        (0x1UL << EXTI_FTSR1_TR11_Pos)              /*!< 0x00000800 */

+#define EXTI_FTSR1_TR11            EXTI_FTSR1_TR11_Msk                         /*!< Falling trigger event configuration bit of line 11 */

+#define EXTI_FTSR1_TR12_Pos        (12U)

+#define EXTI_FTSR1_TR12_Msk        (0x1UL << EXTI_FTSR1_TR12_Pos)              /*!< 0x00001000 */

+#define EXTI_FTSR1_TR12            EXTI_FTSR1_TR12_Msk                         /*!< Falling trigger event configuration bit of line 12 */

+#define EXTI_FTSR1_TR13_Pos        (13U)

+#define EXTI_FTSR1_TR13_Msk        (0x1UL << EXTI_FTSR1_TR13_Pos)              /*!< 0x00002000 */

+#define EXTI_FTSR1_TR13            EXTI_FTSR1_TR13_Msk                         /*!< Falling trigger event configuration bit of line 13 */

+#define EXTI_FTSR1_TR14_Pos        (14U)

+#define EXTI_FTSR1_TR14_Msk        (0x1UL << EXTI_FTSR1_TR14_Pos)              /*!< 0x00004000 */

+#define EXTI_FTSR1_TR14            EXTI_FTSR1_TR14_Msk                         /*!< Falling trigger event configuration bit of line 14 */

+#define EXTI_FTSR1_TR15_Pos        (15U)

+#define EXTI_FTSR1_TR15_Msk        (0x1UL << EXTI_FTSR1_TR15_Pos)              /*!< 0x00008000 */

+#define EXTI_FTSR1_TR15            EXTI_FTSR1_TR15_Msk                         /*!< Falling trigger event configuration bit of line 15 */

+#define EXTI_FTSR1_TR16_Pos        (16U)

+#define EXTI_FTSR1_TR16_Msk        (0x1UL << EXTI_FTSR1_TR16_Pos)              /*!< 0x00010000 */

+#define EXTI_FTSR1_TR16            EXTI_FTSR1_TR16_Msk                         /*!< Falling trigger event configuration bit of line 16 */

+#define EXTI_FTSR1_TR17_Pos        (17U)

+#define EXTI_FTSR1_TR17_Msk        (0x1UL << EXTI_FTSR1_TR17_Pos)              /*!< 0x00020000 */

+#define EXTI_FTSR1_TR17            EXTI_FTSR1_TR17_Msk                         /*!< Falling trigger event configuration bit of line 17 */

+#define EXTI_FTSR1_TR18_Pos        (18U)

+#define EXTI_FTSR1_TR18_Msk        (0x1UL << EXTI_FTSR1_TR18_Pos)              /*!< 0x00040000 */

+#define EXTI_FTSR1_TR18            EXTI_FTSR1_TR18_Msk                         /*!< Falling trigger event configuration bit of line 18 */

+#define EXTI_FTSR1_TR19_Pos        (19U)

+#define EXTI_FTSR1_TR19_Msk        (0x1UL << EXTI_FTSR1_TR19_Pos)              /*!< 0x00080000 */

+#define EXTI_FTSR1_TR19            EXTI_FTSR1_TR19_Msk                         /*!< Falling trigger event configuration bit of line 19 */

+#define EXTI_FTSR1_TR20_Pos        (20U)

+#define EXTI_FTSR1_TR20_Msk        (0x1UL << EXTI_FTSR1_TR20_Pos)              /*!< 0x00100000 */

+#define EXTI_FTSR1_TR20            EXTI_FTSR1_TR20_Msk                         /*!< Falling trigger event configuration bit of line 20 */

+#define EXTI_FTSR1_TR21_Pos        (21U)

+#define EXTI_FTSR1_TR21_Msk        (0x1UL << EXTI_FTSR1_TR21_Pos)              /*!< 0x00200000 */

+#define EXTI_FTSR1_TR21            EXTI_FTSR1_TR21_Msk                         /*!< Falling trigger event configuration bit of line 21 */

+

+/******************  Bit definition for EXTI_SWIER1 register  ******************/

+#define EXTI_SWIER1_SWIER0_Pos     (0U)

+#define EXTI_SWIER1_SWIER0_Msk     (0x1UL << EXTI_SWIER1_SWIER0_Pos)           /*!< 0x00000001 */

+#define EXTI_SWIER1_SWIER0         EXTI_SWIER1_SWIER0_Msk                      /*!< Software Interrupt on line 0 */

+#define EXTI_SWIER1_SWIER1_Pos     (1U)

+#define EXTI_SWIER1_SWIER1_Msk     (0x1UL << EXTI_SWIER1_SWIER1_Pos)           /*!< 0x00000002 */

+#define EXTI_SWIER1_SWIER1         EXTI_SWIER1_SWIER1_Msk                      /*!< Software Interrupt on line 1 */

+#define EXTI_SWIER1_SWIER2_Pos     (2U)

+#define EXTI_SWIER1_SWIER2_Msk     (0x1UL << EXTI_SWIER1_SWIER2_Pos)           /*!< 0x00000004 */

+#define EXTI_SWIER1_SWIER2         EXTI_SWIER1_SWIER2_Msk                      /*!< Software Interrupt on line 2 */

+#define EXTI_SWIER1_SWIER3_Pos     (3U)

+#define EXTI_SWIER1_SWIER3_Msk     (0x1UL << EXTI_SWIER1_SWIER3_Pos)           /*!< 0x00000008 */

+#define EXTI_SWIER1_SWIER3         EXTI_SWIER1_SWIER3_Msk                      /*!< Software Interrupt on line 3 */

+#define EXTI_SWIER1_SWIER4_Pos     (4U)

+#define EXTI_SWIER1_SWIER4_Msk     (0x1UL << EXTI_SWIER1_SWIER4_Pos)           /*!< 0x00000010 */

+#define EXTI_SWIER1_SWIER4         EXTI_SWIER1_SWIER4_Msk                      /*!< Software Interrupt on line 4 */

+#define EXTI_SWIER1_SWIER5_Pos     (5U)

+#define EXTI_SWIER1_SWIER5_Msk     (0x1UL << EXTI_SWIER1_SWIER5_Pos)           /*!< 0x00000020 */

+#define EXTI_SWIER1_SWIER5         EXTI_SWIER1_SWIER5_Msk                      /*!< Software Interrupt on line 5 */

+#define EXTI_SWIER1_SWIER6_Pos     (6U)

+#define EXTI_SWIER1_SWIER6_Msk     (0x1UL << EXTI_SWIER1_SWIER6_Pos)           /*!< 0x00000040 */

+#define EXTI_SWIER1_SWIER6         EXTI_SWIER1_SWIER6_Msk                      /*!< Software Interrupt on line 6 */

+#define EXTI_SWIER1_SWIER7_Pos     (7U)

+#define EXTI_SWIER1_SWIER7_Msk     (0x1UL << EXTI_SWIER1_SWIER7_Pos)           /*!< 0x00000080 */

+#define EXTI_SWIER1_SWIER7         EXTI_SWIER1_SWIER7_Msk                      /*!< Software Interrupt on line 7 */

+#define EXTI_SWIER1_SWIER8_Pos     (8U)

+#define EXTI_SWIER1_SWIER8_Msk     (0x1UL << EXTI_SWIER1_SWIER8_Pos)           /*!< 0x00000100 */

+#define EXTI_SWIER1_SWIER8         EXTI_SWIER1_SWIER8_Msk                      /*!< Software Interrupt on line 8 */

+#define EXTI_SWIER1_SWIER9_Pos     (9U)

+#define EXTI_SWIER1_SWIER9_Msk     (0x1UL << EXTI_SWIER1_SWIER9_Pos)           /*!< 0x00000200 */

+#define EXTI_SWIER1_SWIER9         EXTI_SWIER1_SWIER9_Msk                      /*!< Software Interrupt on line 9 */

+#define EXTI_SWIER1_SWIER10_Pos    (10U)

+#define EXTI_SWIER1_SWIER10_Msk    (0x1UL << EXTI_SWIER1_SWIER10_Pos)          /*!< 0x00000400 */

+#define EXTI_SWIER1_SWIER10        EXTI_SWIER1_SWIER10_Msk                     /*!< Software Interrupt on line 10 */

+#define EXTI_SWIER1_SWIER11_Pos    (11U)

+#define EXTI_SWIER1_SWIER11_Msk    (0x1UL << EXTI_SWIER1_SWIER11_Pos)          /*!< 0x00000800 */

+#define EXTI_SWIER1_SWIER11        EXTI_SWIER1_SWIER11_Msk                     /*!< Software Interrupt on line 11 */

+#define EXTI_SWIER1_SWIER12_Pos    (12U)

+#define EXTI_SWIER1_SWIER12_Msk    (0x1UL << EXTI_SWIER1_SWIER12_Pos)          /*!< 0x00001000 */

+#define EXTI_SWIER1_SWIER12        EXTI_SWIER1_SWIER12_Msk                     /*!< Software Interrupt on line 12 */

+#define EXTI_SWIER1_SWIER13_Pos    (13U)

+#define EXTI_SWIER1_SWIER13_Msk    (0x1UL << EXTI_SWIER1_SWIER13_Pos)          /*!< 0x00002000 */

+#define EXTI_SWIER1_SWIER13        EXTI_SWIER1_SWIER13_Msk                     /*!< Software Interrupt on line 13 */

+#define EXTI_SWIER1_SWIER14_Pos    (14U)

+#define EXTI_SWIER1_SWIER14_Msk    (0x1UL << EXTI_SWIER1_SWIER14_Pos)          /*!< 0x00004000 */

+#define EXTI_SWIER1_SWIER14        EXTI_SWIER1_SWIER14_Msk                     /*!< Software Interrupt on line 14 */

+#define EXTI_SWIER1_SWIER15_Pos    (15U)

+#define EXTI_SWIER1_SWIER15_Msk    (0x1UL << EXTI_SWIER1_SWIER15_Pos)          /*!< 0x00008000 */

+#define EXTI_SWIER1_SWIER15        EXTI_SWIER1_SWIER15_Msk                     /*!< Software Interrupt on line 15 */

+#define EXTI_SWIER1_SWIER16_Pos    (16U)

+#define EXTI_SWIER1_SWIER16_Msk    (0x1UL << EXTI_SWIER1_SWIER16_Pos)          /*!< 0x00010000 */

+#define EXTI_SWIER1_SWIER16        EXTI_SWIER1_SWIER16_Msk                     /*!< Software Interrupt on line 16 */

+#define EXTI_SWIER1_SWIER17_Pos    (17U)

+#define EXTI_SWIER1_SWIER17_Msk    (0x1UL << EXTI_SWIER1_SWIER17_Pos)          /*!< 0x00020000 */

+#define EXTI_SWIER1_SWIER17        EXTI_SWIER1_SWIER17_Msk                     /*!< Software Interrupt on line 17 */

+#define EXTI_SWIER1_SWIER18_Pos    (18U)

+#define EXTI_SWIER1_SWIER18_Msk    (0x1UL << EXTI_SWIER1_SWIER18_Pos)          /*!< 0x00040000 */

+#define EXTI_SWIER1_SWIER18        EXTI_SWIER1_SWIER18_Msk                     /*!< Software Interrupt on line 18 */

+#define EXTI_SWIER1_SWIER19_Pos    (19U)

+#define EXTI_SWIER1_SWIER19_Msk    (0x1UL << EXTI_SWIER1_SWIER19_Pos)          /*!< 0x00080000 */

+#define EXTI_SWIER1_SWIER19        EXTI_SWIER1_SWIER19_Msk                     /*!< Software Interrupt on line 19 */

+#define EXTI_SWIER1_SWIER20_Pos    (20U)

+#define EXTI_SWIER1_SWIER20_Msk    (0x1UL << EXTI_SWIER1_SWIER20_Pos)          /*!< 0x00100000 */

+#define EXTI_SWIER1_SWIER20        EXTI_SWIER1_SWIER20_Msk                     /*!< Software Interrupt on line 20 */

+#define EXTI_SWIER1_SWIER21_Pos    (21U)

+#define EXTI_SWIER1_SWIER21_Msk    (0x1UL << EXTI_SWIER1_SWIER21_Pos)          /*!< 0x00200000 */

+#define EXTI_SWIER1_SWIER21        EXTI_SWIER1_SWIER21_Msk                     /*!< Software Interrupt on line 21 */

+

+/******************  Bit definition for EXTI_D3PMR1 register  ******************/

+#define EXTI_D3PMR1_MR0_Pos        (0U)

+#define EXTI_D3PMR1_MR0_Msk        (0x1UL << EXTI_D3PMR1_MR0_Pos)              /*!< 0x00000001 */

+#define EXTI_D3PMR1_MR0            EXTI_D3PMR1_MR0_Msk                         /*!< Pending Mask Event for line 0  */

+#define EXTI_D3PMR1_MR1_Pos        (1U)

+#define EXTI_D3PMR1_MR1_Msk        (0x1UL << EXTI_D3PMR1_MR1_Pos)              /*!< 0x00000002 */

+#define EXTI_D3PMR1_MR1            EXTI_D3PMR1_MR1_Msk                         /*!< Pending Mask Event for line 1  */

+#define EXTI_D3PMR1_MR2_Pos        (2U)

+#define EXTI_D3PMR1_MR2_Msk        (0x1UL << EXTI_D3PMR1_MR2_Pos)              /*!< 0x00000004 */

+#define EXTI_D3PMR1_MR2            EXTI_D3PMR1_MR2_Msk                         /*!< Pending Mask Event for line 2  */

+#define EXTI_D3PMR1_MR3_Pos        (3U)

+#define EXTI_D3PMR1_MR3_Msk        (0x1UL << EXTI_D3PMR1_MR3_Pos)              /*!< 0x00000008 */

+#define EXTI_D3PMR1_MR3            EXTI_D3PMR1_MR3_Msk                         /*!< Pending Mask Event for line 3  */

+#define EXTI_D3PMR1_MR4_Pos        (4U)

+#define EXTI_D3PMR1_MR4_Msk        (0x1UL << EXTI_D3PMR1_MR4_Pos)              /*!< 0x00000010 */

+#define EXTI_D3PMR1_MR4            EXTI_D3PMR1_MR4_Msk                         /*!< Pending Mask Event for line 4  */

+#define EXTI_D3PMR1_MR5_Pos        (5U)

+#define EXTI_D3PMR1_MR5_Msk        (0x1UL << EXTI_D3PMR1_MR5_Pos)              /*!< 0x00000020 */

+#define EXTI_D3PMR1_MR5            EXTI_D3PMR1_MR5_Msk                         /*!< Pending Mask Event for line 5  */

+#define EXTI_D3PMR1_MR6_Pos        (6U)

+#define EXTI_D3PMR1_MR6_Msk        (0x1UL << EXTI_D3PMR1_MR6_Pos)              /*!< 0x00000040 */

+#define EXTI_D3PMR1_MR6            EXTI_D3PMR1_MR6_Msk                         /*!< Pending Mask Event for line 6  */

+#define EXTI_D3PMR1_MR7_Pos        (7U)

+#define EXTI_D3PMR1_MR7_Msk        (0x1UL << EXTI_D3PMR1_MR7_Pos)              /*!< 0x00000080 */

+#define EXTI_D3PMR1_MR7            EXTI_D3PMR1_MR7_Msk                         /*!< Pending Mask Event for line 7  */

+#define EXTI_D3PMR1_MR8_Pos        (8U)

+#define EXTI_D3PMR1_MR8_Msk        (0x1UL << EXTI_D3PMR1_MR8_Pos)              /*!< 0x00000100 */

+#define EXTI_D3PMR1_MR8            EXTI_D3PMR1_MR8_Msk                         /*!< Pending Mask Event for line 8  */

+#define EXTI_D3PMR1_MR9_Pos        (9U)

+#define EXTI_D3PMR1_MR9_Msk        (0x1UL << EXTI_D3PMR1_MR9_Pos)              /*!< 0x00000200 */

+#define EXTI_D3PMR1_MR9            EXTI_D3PMR1_MR9_Msk                         /*!< Pending Mask Event for line 9  */

+#define EXTI_D3PMR1_MR10_Pos       (10U)

+#define EXTI_D3PMR1_MR10_Msk       (0x1UL << EXTI_D3PMR1_MR10_Pos)             /*!< 0x00000400 */

+#define EXTI_D3PMR1_MR10           EXTI_D3PMR1_MR10_Msk                        /*!< Pending Mask Event for line 10 */

+#define EXTI_D3PMR1_MR11_Pos       (11U)

+#define EXTI_D3PMR1_MR11_Msk       (0x1UL << EXTI_D3PMR1_MR11_Pos)             /*!< 0x00000800 */

+#define EXTI_D3PMR1_MR11           EXTI_D3PMR1_MR11_Msk                        /*!< Pending Mask Event for line 11 */

+#define EXTI_D3PMR1_MR12_Pos       (12U)

+#define EXTI_D3PMR1_MR12_Msk       (0x1UL << EXTI_D3PMR1_MR12_Pos)             /*!< 0x00001000 */

+#define EXTI_D3PMR1_MR12           EXTI_D3PMR1_MR12_Msk                        /*!< Pending Mask Event for line 12 */

+#define EXTI_D3PMR1_MR13_Pos       (13U)

+#define EXTI_D3PMR1_MR13_Msk       (0x1UL << EXTI_D3PMR1_MR13_Pos)             /*!< 0x00002000 */

+#define EXTI_D3PMR1_MR13           EXTI_D3PMR1_MR13_Msk                        /*!< Pending Mask Event for line 13 */

+#define EXTI_D3PMR1_MR14_Pos       (14U)

+#define EXTI_D3PMR1_MR14_Msk       (0x1UL << EXTI_D3PMR1_MR14_Pos)             /*!< 0x00004000 */

+#define EXTI_D3PMR1_MR14           EXTI_D3PMR1_MR14_Msk                        /*!< Pending Mask Event for line 14 */

+#define EXTI_D3PMR1_MR15_Pos       (15U)

+#define EXTI_D3PMR1_MR15_Msk       (0x1UL << EXTI_D3PMR1_MR15_Pos)             /*!< 0x00008000 */

+#define EXTI_D3PMR1_MR15           EXTI_D3PMR1_MR15_Msk                        /*!< Pending Mask Event for line 15 */

+#define EXTI_D3PMR1_MR19_Pos       (19U)

+#define EXTI_D3PMR1_MR19_Msk       (0x1UL << EXTI_D3PMR1_MR19_Pos)             /*!< 0x00080000 */

+#define EXTI_D3PMR1_MR19           EXTI_D3PMR1_MR19_Msk                        /*!< Pending Mask Event for line 19 */

+#define EXTI_D3PMR1_MR20_Pos       (20U)

+#define EXTI_D3PMR1_MR20_Msk       (0x1UL << EXTI_D3PMR1_MR20_Pos)             /*!< 0x00100000 */

+#define EXTI_D3PMR1_MR20           EXTI_D3PMR1_MR20_Msk                        /*!< Pending Mask Event for line 20 */

+#define EXTI_D3PMR1_MR21_Pos       (21U)

+#define EXTI_D3PMR1_MR21_Msk       (0x1UL << EXTI_D3PMR1_MR21_Pos)             /*!< 0x00200000 */

+#define EXTI_D3PMR1_MR21           EXTI_D3PMR1_MR21_Msk                        /*!< Pending Mask Event for line 21 */

+#define EXTI_D3PMR1_MR25_Pos       (24U)

+#define EXTI_D3PMR1_MR25_Msk       (0x1UL << EXTI_D3PMR1_MR25_Pos)             /*!< 0x01000000 */

+#define EXTI_D3PMR1_MR25           EXTI_D3PMR1_MR25_Msk                        /*!< Pending Mask Event for line 25 */

+

+/*******************  Bit definition for EXTI_D3PCR1L register  ****************/

+#define EXTI_D3PCR1L_PCS0_Pos       (0U)

+#define EXTI_D3PCR1L_PCS0_Msk       (0x3UL << EXTI_D3PCR1L_PCS0_Pos)           /*!< 0x00000003 */

+#define EXTI_D3PCR1L_PCS0           EXTI_D3PCR1L_PCS0_Msk                      /*!< D3 Pending request clear input signal selection on line 0 */

+#define EXTI_D3PCR1L_PCS1_Pos       (2U)

+#define EXTI_D3PCR1L_PCS1_Msk       (0x3UL << EXTI_D3PCR1L_PCS1_Pos)           /*!< 0x000000C0 */

+#define EXTI_D3PCR1L_PCS1           EXTI_D3PCR1L_PCS1_Msk                      /*!< D3 Pending request clear input signal selection on line 1 */

+#define EXTI_D3PCR1L_PCS2_Pos       (4U)

+#define EXTI_D3PCR1L_PCS2_Msk       (0x3UL << EXTI_D3PCR1L_PCS2_Pos)           /*!< 0x00000030 */

+#define EXTI_D3PCR1L_PCS2           EXTI_D3PCR1L_PCS2_Msk                      /*!< D3 Pending request clear input signal selection on line 2 */

+#define EXTI_D3PCR1L_PCS3_Pos       (6U)

+#define EXTI_D3PCR1L_PCS3_Msk       (0x3UL << EXTI_D3PCR1L_PCS3_Pos)           /*!< 0x000000C0 */

+#define EXTI_D3PCR1L_PCS3           EXTI_D3PCR1L_PCS3_Msk                      /*!< D3 Pending request clear input signal selection on line 3 */

+#define EXTI_D3PCR1L_PCS4_Pos       (8U)

+#define EXTI_D3PCR1L_PCS4_Msk       (0x3UL << EXTI_D3PCR1L_PCS4_Pos)           /*!< 0x00000300 */

+#define EXTI_D3PCR1L_PCS4           EXTI_D3PCR1L_PCS4_Msk                      /*!< D3 Pending request clear input signal selection on line 4 */

+#define EXTI_D3PCR1L_PCS5_Pos       (10U)

+#define EXTI_D3PCR1L_PCS5_Msk       (0x3UL << EXTI_D3PCR1L_PCS5_Pos)           /*!< 0x00000C00 */

+#define EXTI_D3PCR1L_PCS5           EXTI_D3PCR1L_PCS5_Msk                      /*!< D3 Pending request clear input signal selection on line 5 */

+#define EXTI_D3PCR1L_PCS6_Pos       (12U)

+#define EXTI_D3PCR1L_PCS6_Msk       (0x3UL << EXTI_D3PCR1L_PCS6_Pos)           /*!< 0x00003000 */

+#define EXTI_D3PCR1L_PCS6           EXTI_D3PCR1L_PCS6_Msk                      /*!< D3 Pending request clear input signal selection on line 6 */

+#define EXTI_D3PCR1L_PCS7_Pos       (14U)

+#define EXTI_D3PCR1L_PCS7_Msk       (0x3UL << EXTI_D3PCR1L_PCS7_Pos)           /*!< 0x0000C000 */

+#define EXTI_D3PCR1L_PCS7           EXTI_D3PCR1L_PCS7_Msk                      /*!< D3 Pending request clear input signal selection on line 7 */

+#define EXTI_D3PCR1L_PCS8_Pos       (16U)

+#define EXTI_D3PCR1L_PCS8_Msk       (0x3UL << EXTI_D3PCR1L_PCS8_Pos)           /*!< 0x00030000 */

+#define EXTI_D3PCR1L_PCS8           EXTI_D3PCR1L_PCS8_Msk                      /*!< D3 Pending request clear input signal selection on line 8 */

+#define EXTI_D3PCR1L_PCS9_Pos       (18U)

+#define EXTI_D3PCR1L_PCS9_Msk       (0x3UL << EXTI_D3PCR1L_PCS9_Pos)           /*!< 0x000C0000 */

+#define EXTI_D3PCR1L_PCS9           EXTI_D3PCR1L_PCS9_Msk                      /*!< D3 Pending request clear input signal selection on line 9 */

+#define EXTI_D3PCR1L_PCS10_Pos      (20U)

+#define EXTI_D3PCR1L_PCS10_Msk      (0x3UL << EXTI_D3PCR1L_PCS10_Pos)          /*!< 0x00300000 */

+#define EXTI_D3PCR1L_PCS10          EXTI_D3PCR1L_PCS10_Msk                     /*!< D3 Pending request clear input signal selection on line 10*/

+#define EXTI_D3PCR1L_PCS11_Pos      (22U)

+#define EXTI_D3PCR1L_PCS11_Msk      (0x3UL << EXTI_D3PCR1L_PCS11_Pos)          /*!< 0x00C00000 */

+#define EXTI_D3PCR1L_PCS11          EXTI_D3PCR1L_PCS11_Msk                     /*!< D3 Pending request clear input signal selection on line 11*/

+#define EXTI_D3PCR1L_PCS12_Pos      (24U)

+#define EXTI_D3PCR1L_PCS12_Msk      (0x3UL << EXTI_D3PCR1L_PCS12_Pos)          /*!< 0x03000000 */

+#define EXTI_D3PCR1L_PCS12          EXTI_D3PCR1L_PCS12_Msk                     /*!< D3 Pending request clear input signal selection on line 12*/

+#define EXTI_D3PCR1L_PCS13_Pos      (26U)

+#define EXTI_D3PCR1L_PCS13_Msk      (0x3UL << EXTI_D3PCR1L_PCS13_Pos)          /*!< 0x0C000000 */

+#define EXTI_D3PCR1L_PCS13          EXTI_D3PCR1L_PCS13_Msk                     /*!< D3 Pending request clear input signal selection on line 13*/

+#define EXTI_D3PCR1L_PCS14_Pos      (28U)

+#define EXTI_D3PCR1L_PCS14_Msk      (0x3UL << EXTI_D3PCR1L_PCS14_Pos)          /*!< 0x30000000 */

+#define EXTI_D3PCR1L_PCS14          EXTI_D3PCR1L_PCS14_Msk                     /*!< D3 Pending request clear input signal selection on line 14*/

+#define EXTI_D3PCR1L_PCS15_Pos      (30U)

+#define EXTI_D3PCR1L_PCS15_Msk      (0x3UL << EXTI_D3PCR1L_PCS15_Pos)          /*!< 0xC0000000 */

+#define EXTI_D3PCR1L_PCS15          EXTI_D3PCR1L_PCS15_Msk                     /*!< D3 Pending request clear input signal selection on line 15*/

+

+/*******************  Bit definition for EXTI_D3PCR1H register  ****************/

+#define EXTI_D3PCR1H_PCS19_Pos       (6U)

+#define EXTI_D3PCR1H_PCS19_Msk       (0x3UL << EXTI_D3PCR1H_PCS19_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR1H_PCS19           EXTI_D3PCR1H_PCS19_Msk                    /*!< D3 Pending request clear input signal selection on line 19 */

+#define EXTI_D3PCR1H_PCS20_Pos       (8U)

+#define EXTI_D3PCR1H_PCS20_Msk       (0x3UL << EXTI_D3PCR1H_PCS20_Pos)         /*!< 0x00000300 */

+#define EXTI_D3PCR1H_PCS20           EXTI_D3PCR1H_PCS20_Msk                    /*!< D3 Pending request clear input signal selection on line 20 */

+#define EXTI_D3PCR1H_PCS21_Pos       (10U)

+#define EXTI_D3PCR1H_PCS21_Msk       (0x3UL << EXTI_D3PCR1H_PCS21_Pos)         /*!< 0x00000C00 */

+#define EXTI_D3PCR1H_PCS21           EXTI_D3PCR1H_PCS21_Msk                    /*!< D3 Pending request clear input signal selection on line 21 */

+#define EXTI_D3PCR1H_PCS25_Pos       (18U)

+#define EXTI_D3PCR1H_PCS25_Msk       (0x3UL << EXTI_D3PCR1H_PCS25_Pos)         /*!< 0x000C0000 */

+#define EXTI_D3PCR1H_PCS25           EXTI_D3PCR1H_PCS25_Msk                    /*!< D3 Pending request clear input signal selection on line 25 */

+

+/******************  Bit definition for EXTI_RTSR2 register  *******************/

+#define EXTI_RTSR2_TR_Pos          (17U)

+#define EXTI_RTSR2_TR_Msk          (0x5UL << EXTI_RTSR2_TR_Pos)                /*!< 0x000A0000 */

+#define EXTI_RTSR2_TR              EXTI_RTSR2_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR2_TR49_Pos        (17U)

+#define EXTI_RTSR2_TR49_Msk        (0x1UL << EXTI_RTSR2_TR49_Pos)              /*!< 0x00020000 */

+#define EXTI_RTSR2_TR49            EXTI_RTSR2_TR49_Msk                         /*!< Rising trigger event configuration bit of line 49 */

+#define EXTI_RTSR2_TR51_Pos        (19U)

+#define EXTI_RTSR2_TR51_Msk        (0x1UL << EXTI_RTSR2_TR51_Pos)              /*!< 0x00080000 */

+#define EXTI_RTSR2_TR51            EXTI_RTSR2_TR51_Msk                         /*!< Rising trigger event configuration bit of line 51 */

+

+/******************  Bit definition for EXTI_FTSR2 register  *******************/

+#define EXTI_FTSR2_TR_Pos          (17U)

+#define EXTI_FTSR2_TR_Msk          (0x5UL << EXTI_FTSR2_TR_Pos)                /*!< 0x000A0000 */

+#define EXTI_FTSR2_TR              EXTI_FTSR2_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR2_TR49_Pos        (17U)

+#define EXTI_FTSR2_TR49_Msk        (0x1UL << EXTI_FTSR2_TR49_Pos)              /*!< 0x00020000 */

+#define EXTI_FTSR2_TR49            EXTI_FTSR2_TR49_Msk                         /*!< Falling trigger event configuration bit of line 49 */

+#define EXTI_FTSR2_TR51_Pos        (19U)

+#define EXTI_FTSR2_TR51_Msk        (0x1UL << EXTI_FTSR2_TR51_Pos)              /*!< 0x00080000 */

+#define EXTI_FTSR2_TR51            EXTI_FTSR2_TR51_Msk                         /*!< Falling trigger event configuration bit of line 51 */

+

+/******************  Bit definition for EXTI_SWIER2 register  ******************/

+#define EXTI_SWIER2_SWIER49_Pos    (17U)

+#define EXTI_SWIER2_SWIER49_Msk    (0x1UL << EXTI_SWIER2_SWIER49_Pos)          /*!< 0x00020000 */

+#define EXTI_SWIER2_SWIER49        EXTI_SWIER2_SWIER49_Msk                     /*!< Software Interrupt on line 49 */

+#define EXTI_SWIER2_SWIER51_Pos    (19U)

+#define EXTI_SWIER2_SWIER51_Msk    (0x1UL << EXTI_SWIER2_SWIER51_Pos)          /*!< 0x00080000 */

+#define EXTI_SWIER2_SWIER51        EXTI_SWIER2_SWIER51_Msk                     /*!< Software Interrupt on line 51 */

+

+/******************  Bit definition for EXTI_D3PMR2 register  ******************/

+#define EXTI_D3PMR2_MR34_Pos       (2U)

+#define EXTI_D3PMR2_MR34_Msk       (0x1UL << EXTI_D3PMR2_MR34_Pos)             /*!< 0x00000004 */

+#define EXTI_D3PMR2_MR34           EXTI_D3PMR2_MR34_Msk                        /*!< Pending Mask Event for line 34  */

+#define EXTI_D3PMR2_MR35_Pos       (3U)

+#define EXTI_D3PMR2_MR35_Msk       (0x1UL << EXTI_D3PMR2_MR35_Pos)             /*!< 0x00000008 */

+#define EXTI_D3PMR2_MR35           EXTI_D3PMR2_MR35_Msk                        /*!< Pending Mask Event for line 35  */

+#define EXTI_D3PMR2_MR41_Pos       (9U)

+#define EXTI_D3PMR2_MR41_Msk       (0x1UL << EXTI_D3PMR2_MR41_Pos)             /*!< 0x00000200 */

+#define EXTI_D3PMR2_MR41           EXTI_D3PMR2_MR41_Msk                        /*!< Pending Mask Event for line 41  */

+#define EXTI_D3PMR2_MR48_Pos       (16U)

+#define EXTI_D3PMR2_MR48_Msk       (0x1UL << EXTI_D3PMR2_MR48_Pos)             /*!< 0x00010000 */

+#define EXTI_D3PMR2_MR48           EXTI_D3PMR2_MR48_Msk                        /*!< Pending Mask Event for line 48  */

+#define EXTI_D3PMR2_MR49_Pos       (17U)

+#define EXTI_D3PMR2_MR49_Msk       (0x1UL << EXTI_D3PMR2_MR49_Pos)             /*!< 0x00020000 */

+#define EXTI_D3PMR2_MR49           EXTI_D3PMR2_MR49_Msk                        /*!< Pending Mask Event for line 49  */

+#define EXTI_D3PMR2_MR50_Pos       (18U)

+#define EXTI_D3PMR2_MR50_Msk       (0x1UL << EXTI_D3PMR2_MR50_Pos)             /*!< 0x00040000 */

+#define EXTI_D3PMR2_MR50           EXTI_D3PMR2_MR50_Msk                        /*!< Pending Mask Event for line 50  */

+#define EXTI_D3PMR2_MR51_Pos       (19U)

+#define EXTI_D3PMR2_MR51_Msk       (0x1UL << EXTI_D3PMR2_MR51_Pos)             /*!< 0x00080000 */

+#define EXTI_D3PMR2_MR51           EXTI_D3PMR2_MR51_Msk                        /*!< Pending Mask Event for line 51  */

+/*******************  Bit definition for EXTI_D3PCR2L register  ****************/

+#define EXTI_D3PCR2L_PCS34_Pos       (4U)

+#define EXTI_D3PCR2L_PCS34_Msk       (0x3UL << EXTI_D3PCR2L_PCS34_Pos)         /*!< 0x00000030 */

+#define EXTI_D3PCR2L_PCS34           EXTI_D3PCR2L_PCS34_Msk                    /*!< D3 Pending request clear input signal selection on line 34 */

+#define EXTI_D3PCR2L_PCS35_Pos       (6U)

+#define EXTI_D3PCR2L_PCS35_Msk       (0x3UL << EXTI_D3PCR2L_PCS35_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR2L_PCS35           EXTI_D3PCR2L_PCS35_Msk                    /*!< D3 Pending request clear input signal selection on line 35 */

+#define EXTI_D3PCR2L_PCS41_Pos       (18U)

+#define EXTI_D3PCR2L_PCS41_Msk       (0x3UL << EXTI_D3PCR2L_PCS41_Pos)         /*!< 0x000C0000 */

+#define EXTI_D3PCR2L_PCS41           EXTI_D3PCR2L_PCS41_Msk                    /*!< D3 Pending request clear input signal selection on line 41 */

+

+

+/*******************  Bit definition for EXTI_D3PCR2H register  ****************/

+#define EXTI_D3PCR2H_PCS48_Pos       (0U)

+#define EXTI_D3PCR2H_PCS48_Msk       (0x3UL << EXTI_D3PCR2H_PCS48_Pos)         /*!< 0x00000003 */

+#define EXTI_D3PCR2H_PCS48           EXTI_D3PCR2H_PCS48_Msk                    /*!< D3 Pending request clear input signal selection on line 48 */

+#define EXTI_D3PCR2H_PCS49_Pos       (2U)

+#define EXTI_D3PCR2H_PCS49_Msk       (0x3UL << EXTI_D3PCR2H_PCS49_Pos)         /*!< 0x0000000C */

+#define EXTI_D3PCR2H_PCS49           EXTI_D3PCR2H_PCS49_Msk                    /*!< D3 Pending request clear input signal selection on line 49 */

+#define EXTI_D3PCR2H_PCS50_Pos       (4U)

+#define EXTI_D3PCR2H_PCS50_Msk       (0x3UL << EXTI_D3PCR2H_PCS50_Pos)         /*!< 0x00000030 */

+#define EXTI_D3PCR2H_PCS50           EXTI_D3PCR2H_PCS50_Msk                    /*!< D3 Pending request clear input signal selection on line 50 */

+#define EXTI_D3PCR2H_PCS51_Pos       (6U)

+#define EXTI_D3PCR2H_PCS51_Msk       (0x3UL << EXTI_D3PCR2H_PCS51_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR2H_PCS51           EXTI_D3PCR2H_PCS51_Msk                    /*!< D3 Pending request clear input signal selection on line 51 */

+/******************  Bit definition for EXTI_RTSR3 register  *******************/

+#define EXTI_RTSR3_TR_Pos          (18U)

+#define EXTI_RTSR3_TR_Msk          (0x9UL << EXTI_RTSR3_TR_Pos)                /*!< 0x00240000 */

+#define EXTI_RTSR3_TR              EXTI_RTSR3_TR_Msk                           /*!< Rising trigger event configuration bit            */

+#define EXTI_RTSR3_TR82_Pos        (18U)

+#define EXTI_RTSR3_TR82_Msk        (0x1UL << EXTI_RTSR3_TR82_Pos)              /*!< 0x00040000 */

+#define EXTI_RTSR3_TR82            EXTI_RTSR3_TR82_Msk                         /*!< Rising trigger event configuration bit of line 82 */

+#define EXTI_RTSR3_TR85_Pos        (21U)

+#define EXTI_RTSR3_TR85_Msk        (0x1UL << EXTI_RTSR3_TR85_Pos)              /*!< 0x00200000 */

+#define EXTI_RTSR3_TR85            EXTI_RTSR3_TR85_Msk                         /*!< Rising trigger event configuration bit of line 85 */

+

+/******************  Bit definition for EXTI_FTSR3 register  *******************/

+#define EXTI_FTSR3_TR_Pos          (18U)

+#define EXTI_FTSR3_TR_Msk          (0x9UL << EXTI_FTSR3_TR_Pos)                /*!< 0x00240000 */

+#define EXTI_FTSR3_TR              EXTI_FTSR3_TR_Msk                           /*!< Falling trigger event configuration bit            */

+#define EXTI_FTSR3_TR82_Pos        (18U)

+#define EXTI_FTSR3_TR82_Msk        (0x1UL << EXTI_FTSR3_TR82_Pos)              /*!< 0x00040000 */

+#define EXTI_FTSR3_TR82            EXTI_FTSR3_TR82_Msk                         /*!< Falling trigger event configuration bit of line 82 */

+#define EXTI_FTSR3_TR85_Pos        (21U)

+#define EXTI_FTSR3_TR85_Msk        (0x1UL << EXTI_FTSR3_TR85_Pos)              /*!< 0x00200000 */

+#define EXTI_FTSR3_TR85            EXTI_FTSR3_TR85_Msk                         /*!< Falling trigger event configuration bit of line 85 */

+

+/******************  Bit definition for EXTI_SWIER3 register  ******************/

+#define EXTI_SWIER3_SWI_Pos        (18U)

+#define EXTI_SWIER3_SWI_Msk        (0x9UL << EXTI_SWIER3_SWI_Pos)              /*!< 0x00240000 */

+#define EXTI_SWIER3_SWI            EXTI_SWIER3_SWI_Msk                         /*!< Software Interrupt event bit */

+#define EXTI_SWIER3_SWIER82_Pos    (18U)

+#define EXTI_SWIER3_SWIER82_Msk    (0x1UL << EXTI_SWIER3_SWIER82_Pos)          /*!< 0x00040000 */

+#define EXTI_SWIER3_SWIER82        EXTI_SWIER3_SWIER82_Msk                     /*!< Software Interrupt on line 82 */

+#define EXTI_SWIER3_SWIER85_Pos    (21U)

+#define EXTI_SWIER3_SWIER85_Msk    (0x1UL << EXTI_SWIER3_SWIER85_Pos)          /*!< 0x00200000 */

+#define EXTI_SWIER3_SWIER85        EXTI_SWIER3_SWIER85_Msk                     /*!< Software Interrupt on line 85 */

+

+/******************  Bit definition for EXTI_D3PMR3 register  ******************/

+#define EXTI_D3PMR3_MR88_Pos       (24U)

+#define EXTI_D3PMR3_MR88_Msk       (0x1UL << EXTI_D3PMR3_MR88_Pos)             /*!< 0x01000000 */

+#define EXTI_D3PMR3_MR88           EXTI_D3PMR3_MR88_Msk                        /*!< Pending Mask Event for line 88  */

+

+/*******************  Bit definition for EXTI_D3PCR3H register  ****************/

+#define EXTI_D3PCR3H_PCS88_Pos       (16U)

+#define EXTI_D3PCR3H_PCS88_Msk       (0x3UL << EXTI_D3PCR3H_PCS88_Pos)         /*!< 0x00030000 */

+#define EXTI_D3PCR3H_PCS88           EXTI_D3PCR3H_PCS88_Msk                    /*!< D3 Pending request clear input signal selection on line 88 */

+

+/*******************  Bit definition for EXTI_IMR1 register  *******************/

+#define EXTI_IMR1_IM_Pos           (0U)

+#define EXTI_IMR1_IM_Msk           (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)          /*!< 0xFFFFFFFF */

+#define EXTI_IMR1_IM               EXTI_IMR1_IM_Msk                            /*!< Interrupt Mask */

+#define EXTI_IMR1_IM0_Pos          (0U)

+#define EXTI_IMR1_IM0_Msk          (0x1UL << EXTI_IMR1_IM0_Pos)                /*!< 0x00000001 */

+#define EXTI_IMR1_IM0              EXTI_IMR1_IM0_Msk                           /*!< Interrupt Mask on line 0 */

+#define EXTI_IMR1_IM1_Pos          (1U)

+#define EXTI_IMR1_IM1_Msk          (0x1UL << EXTI_IMR1_IM1_Pos)                /*!< 0x00000002 */

+#define EXTI_IMR1_IM1              EXTI_IMR1_IM1_Msk                           /*!< Interrupt Mask on line 1 */

+#define EXTI_IMR1_IM2_Pos          (2U)

+#define EXTI_IMR1_IM2_Msk          (0x1UL << EXTI_IMR1_IM2_Pos)                /*!< 0x00000004 */

+#define EXTI_IMR1_IM2              EXTI_IMR1_IM2_Msk                           /*!< Interrupt Mask on line 2 */

+#define EXTI_IMR1_IM3_Pos          (3U)

+#define EXTI_IMR1_IM3_Msk          (0x1UL << EXTI_IMR1_IM3_Pos)                /*!< 0x00000008 */

+#define EXTI_IMR1_IM3              EXTI_IMR1_IM3_Msk                           /*!< Interrupt Mask on line 3 */

+#define EXTI_IMR1_IM4_Pos          (4U)

+#define EXTI_IMR1_IM4_Msk          (0x1UL << EXTI_IMR1_IM4_Pos)                /*!< 0x00000010 */

+#define EXTI_IMR1_IM4              EXTI_IMR1_IM4_Msk                           /*!< Interrupt Mask on line 4 */

+#define EXTI_IMR1_IM5_Pos          (5U)

+#define EXTI_IMR1_IM5_Msk          (0x1UL << EXTI_IMR1_IM5_Pos)                /*!< 0x00000020 */

+#define EXTI_IMR1_IM5              EXTI_IMR1_IM5_Msk                           /*!< Interrupt Mask on line 5 */

+#define EXTI_IMR1_IM6_Pos          (6U)

+#define EXTI_IMR1_IM6_Msk          (0x1UL << EXTI_IMR1_IM6_Pos)                /*!< 0x00000040 */

+#define EXTI_IMR1_IM6              EXTI_IMR1_IM6_Msk                           /*!< Interrupt Mask on line 6 */

+#define EXTI_IMR1_IM7_Pos          (7U)

+#define EXTI_IMR1_IM7_Msk          (0x1UL << EXTI_IMR1_IM7_Pos)                /*!< 0x00000080 */

+#define EXTI_IMR1_IM7              EXTI_IMR1_IM7_Msk                           /*!< Interrupt Mask on line 7 */

+#define EXTI_IMR1_IM8_Pos          (8U)

+#define EXTI_IMR1_IM8_Msk          (0x1UL << EXTI_IMR1_IM8_Pos)                /*!< 0x00000100 */

+#define EXTI_IMR1_IM8              EXTI_IMR1_IM8_Msk                           /*!< Interrupt Mask on line 8 */

+#define EXTI_IMR1_IM9_Pos          (9U)

+#define EXTI_IMR1_IM9_Msk          (0x1UL << EXTI_IMR1_IM9_Pos)                /*!< 0x00000200 */

+#define EXTI_IMR1_IM9              EXTI_IMR1_IM9_Msk                           /*!< Interrupt Mask on line 9 */

+#define EXTI_IMR1_IM10_Pos         (10U)

+#define EXTI_IMR1_IM10_Msk         (0x1UL << EXTI_IMR1_IM10_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR1_IM10             EXTI_IMR1_IM10_Msk                          /*!< Interrupt Mask on line 10 */

+#define EXTI_IMR1_IM11_Pos         (11U)

+#define EXTI_IMR1_IM11_Msk         (0x1UL << EXTI_IMR1_IM11_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR1_IM11             EXTI_IMR1_IM11_Msk                          /*!< Interrupt Mask on line 11 */

+#define EXTI_IMR1_IM12_Pos         (12U)

+#define EXTI_IMR1_IM12_Msk         (0x1UL << EXTI_IMR1_IM12_Pos)               /*!< 0x00001000 */

+#define EXTI_IMR1_IM12             EXTI_IMR1_IM12_Msk                          /*!< Interrupt Mask on line 12 */

+#define EXTI_IMR1_IM13_Pos         (13U)

+#define EXTI_IMR1_IM13_Msk         (0x1UL << EXTI_IMR1_IM13_Pos)               /*!< 0x00002000 */

+#define EXTI_IMR1_IM13             EXTI_IMR1_IM13_Msk                          /*!< Interrupt Mask on line 13 */

+#define EXTI_IMR1_IM14_Pos         (14U)

+#define EXTI_IMR1_IM14_Msk         (0x1UL << EXTI_IMR1_IM14_Pos)               /*!< 0x00004000 */

+#define EXTI_IMR1_IM14             EXTI_IMR1_IM14_Msk                          /*!< Interrupt Mask on line 14 */

+#define EXTI_IMR1_IM15_Pos         (15U)

+#define EXTI_IMR1_IM15_Msk         (0x1UL << EXTI_IMR1_IM15_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR1_IM15             EXTI_IMR1_IM15_Msk                          /*!< Interrupt Mask on line 15 */

+#define EXTI_IMR1_IM16_Pos         (16U)

+#define EXTI_IMR1_IM16_Msk         (0x1UL << EXTI_IMR1_IM16_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR1_IM16             EXTI_IMR1_IM16_Msk                          /*!< Interrupt Mask on line 16 */

+#define EXTI_IMR1_IM17_Pos         (17U)

+#define EXTI_IMR1_IM17_Msk         (0x1UL << EXTI_IMR1_IM17_Pos)               /*!< 0x00020000 */

+#define EXTI_IMR1_IM17             EXTI_IMR1_IM17_Msk                          /*!< Interrupt Mask on line 17 */

+#define EXTI_IMR1_IM18_Pos         (18U)

+#define EXTI_IMR1_IM18_Msk         (0x1UL << EXTI_IMR1_IM18_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR1_IM18             EXTI_IMR1_IM18_Msk                          /*!< Interrupt Mask on line 18 */

+#define EXTI_IMR1_IM19_Pos         (19U)

+#define EXTI_IMR1_IM19_Msk         (0x1UL << EXTI_IMR1_IM19_Pos)               /*!< 0x00080000 */

+#define EXTI_IMR1_IM19             EXTI_IMR1_IM19_Msk                          /*!< Interrupt Mask on line 19 */

+#define EXTI_IMR1_IM20_Pos         (20U)

+#define EXTI_IMR1_IM20_Msk         (0x1UL << EXTI_IMR1_IM20_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR1_IM20             EXTI_IMR1_IM20_Msk                          /*!< Interrupt Mask on line 20 */

+#define EXTI_IMR1_IM21_Pos         (21U)

+#define EXTI_IMR1_IM21_Msk         (0x1UL << EXTI_IMR1_IM21_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR1_IM21             EXTI_IMR1_IM21_Msk                          /*!< Interrupt Mask on line 21 */

+#define EXTI_IMR1_IM22_Pos         (22U)

+#define EXTI_IMR1_IM22_Msk         (0x1UL << EXTI_IMR1_IM22_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR1_IM22             EXTI_IMR1_IM22_Msk                          /*!< Interrupt Mask on line 22 */

+#define EXTI_IMR1_IM23_Pos         (23U)

+#define EXTI_IMR1_IM23_Msk         (0x1UL << EXTI_IMR1_IM23_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR1_IM23             EXTI_IMR1_IM23_Msk                          /*!< Interrupt Mask on line 23 */

+#define EXTI_IMR1_IM24_Pos         (24U)

+#define EXTI_IMR1_IM24_Msk         (0x1UL << EXTI_IMR1_IM24_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR1_IM24             EXTI_IMR1_IM24_Msk                          /*!< Interrupt Mask on line 24 */

+#define EXTI_IMR1_IM25_Pos         (25U)

+#define EXTI_IMR1_IM25_Msk         (0x1UL << EXTI_IMR1_IM25_Pos)               /*!< 0x02000000 */

+#define EXTI_IMR1_IM25             EXTI_IMR1_IM25_Msk                          /*!< Interrupt Mask on line 25 */

+#define EXTI_IMR1_IM26_Pos         (26U)

+#define EXTI_IMR1_IM26_Msk         (0x1UL << EXTI_IMR1_IM26_Pos)               /*!< 0x04000000 */

+#define EXTI_IMR1_IM26             EXTI_IMR1_IM26_Msk                          /*!< Interrupt Mask on line 26 */

+#define EXTI_IMR1_IM27_Pos         (27U)

+#define EXTI_IMR1_IM27_Msk         (0x1UL << EXTI_IMR1_IM27_Pos)               /*!< 0x08000000 */

+#define EXTI_IMR1_IM27             EXTI_IMR1_IM27_Msk                          /*!< Interrupt Mask on line 27 */

+#define EXTI_IMR1_IM28_Pos         (28U)

+#define EXTI_IMR1_IM28_Msk         (0x1UL << EXTI_IMR1_IM28_Pos)               /*!< 0x10000000 */

+#define EXTI_IMR1_IM28             EXTI_IMR1_IM28_Msk                          /*!< Interrupt Mask on line 28 */

+#define EXTI_IMR1_IM29_Pos         (29U)

+#define EXTI_IMR1_IM29_Msk         (0x1UL << EXTI_IMR1_IM29_Pos)               /*!< 0x20000000 */

+#define EXTI_IMR1_IM29             EXTI_IMR1_IM29_Msk                          /*!< Interrupt Mask on line 29 */

+#define EXTI_IMR1_IM30_Pos         (30U)

+#define EXTI_IMR1_IM30_Msk         (0x1UL << EXTI_IMR1_IM30_Pos)               /*!< 0x40000000 */

+#define EXTI_IMR1_IM30             EXTI_IMR1_IM30_Msk                          /*!< Interrupt Mask on line 30 */

+#define EXTI_IMR1_IM31_Pos         (31U)

+#define EXTI_IMR1_IM31_Msk         (0x1UL << EXTI_IMR1_IM31_Pos)               /*!< 0x80000000 */

+#define EXTI_IMR1_IM31             EXTI_IMR1_IM31_Msk                          /*!< Interrupt Mask on line 31 */

+

+/*******************  Bit definition for EXTI_EMR1 register  *******************/

+#define EXTI_EMR1_EM_Pos           (0U)

+#define EXTI_EMR1_EM_Msk           (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)          /*!< 0xFFFFFFFF */

+#define EXTI_EMR1_EM               EXTI_EMR1_EM_Msk                            /*!< Event Mask */

+#define EXTI_EMR1_EM0_Pos          (0U)

+#define EXTI_EMR1_EM0_Msk          (0x1UL << EXTI_EMR1_EM0_Pos)                /*!< 0x00000001 */

+#define EXTI_EMR1_EM0              EXTI_EMR1_EM0_Msk                           /*!< Event Mask on line 0 */

+#define EXTI_EMR1_EM1_Pos          (1U)

+#define EXTI_EMR1_EM1_Msk          (0x1UL << EXTI_EMR1_EM1_Pos)                /*!< 0x00000002 */

+#define EXTI_EMR1_EM1              EXTI_EMR1_EM1_Msk                           /*!< Event Mask on line 1 */

+#define EXTI_EMR1_EM2_Pos          (2U)

+#define EXTI_EMR1_EM2_Msk          (0x1UL << EXTI_EMR1_EM2_Pos)                /*!< 0x00000004 */

+#define EXTI_EMR1_EM2              EXTI_EMR1_EM2_Msk                           /*!< Event Mask on line 2 */

+#define EXTI_EMR1_EM3_Pos          (3U)

+#define EXTI_EMR1_EM3_Msk          (0x1UL << EXTI_EMR1_EM3_Pos)                /*!< 0x00000008 */

+#define EXTI_EMR1_EM3              EXTI_EMR1_EM3_Msk                           /*!< Event Mask on line 3 */

+#define EXTI_EMR1_EM4_Pos          (4U)

+#define EXTI_EMR1_EM4_Msk          (0x1UL << EXTI_EMR1_EM4_Pos)                /*!< 0x00000010 */

+#define EXTI_EMR1_EM4              EXTI_EMR1_EM4_Msk                           /*!< Event Mask on line 4 */

+#define EXTI_EMR1_EM5_Pos          (5U)

+#define EXTI_EMR1_EM5_Msk          (0x1UL << EXTI_EMR1_EM5_Pos)                /*!< 0x00000020 */

+#define EXTI_EMR1_EM5              EXTI_EMR1_EM5_Msk                           /*!< Event Mask on line 5 */

+#define EXTI_EMR1_EM6_Pos          (6U)

+#define EXTI_EMR1_EM6_Msk          (0x1UL << EXTI_EMR1_EM6_Pos)                /*!< 0x00000040 */

+#define EXTI_EMR1_EM6              EXTI_EMR1_EM6_Msk                           /*!< Event Mask on line 6 */

+#define EXTI_EMR1_EM7_Pos          (7U)

+#define EXTI_EMR1_EM7_Msk          (0x1UL << EXTI_EMR1_EM7_Pos)                /*!< 0x00000080 */

+#define EXTI_EMR1_EM7              EXTI_EMR1_EM7_Msk                           /*!< Event Mask on line 7 */

+#define EXTI_EMR1_EM8_Pos          (8U)

+#define EXTI_EMR1_EM8_Msk          (0x1UL << EXTI_EMR1_EM8_Pos)                /*!< 0x00000100 */

+#define EXTI_EMR1_EM8              EXTI_EMR1_EM8_Msk                           /*!< Event Mask on line 8 */

+#define EXTI_EMR1_EM9_Pos          (9U)

+#define EXTI_EMR1_EM9_Msk          (0x1UL << EXTI_EMR1_EM9_Pos)                /*!< 0x00000200 */

+#define EXTI_EMR1_EM9              EXTI_EMR1_EM9_Msk                           /*!< Event Mask on line 9 */

+#define EXTI_EMR1_EM10_Pos         (10U)

+#define EXTI_EMR1_EM10_Msk         (0x1UL << EXTI_EMR1_EM10_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR1_EM10             EXTI_EMR1_EM10_Msk                          /*!< Event Mask on line 10 */

+#define EXTI_EMR1_EM11_Pos         (11U)

+#define EXTI_EMR1_EM11_Msk         (0x1UL << EXTI_EMR1_EM11_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR1_EM11             EXTI_EMR1_EM11_Msk                          /*!< Event Mask on line 11 */

+#define EXTI_EMR1_EM12_Pos         (12U)

+#define EXTI_EMR1_EM12_Msk         (0x1UL << EXTI_EMR1_EM12_Pos)               /*!< 0x00001000 */

+#define EXTI_EMR1_EM12             EXTI_EMR1_EM12_Msk                          /*!< Event Mask on line 12 */

+#define EXTI_EMR1_EM13_Pos         (13U)

+#define EXTI_EMR1_EM13_Msk         (0x1UL << EXTI_EMR1_EM13_Pos)               /*!< 0x00002000 */

+#define EXTI_EMR1_EM13             EXTI_EMR1_EM13_Msk                          /*!< Event Mask on line 13 */

+#define EXTI_EMR1_EM14_Pos         (14U)

+#define EXTI_EMR1_EM14_Msk         (0x1UL << EXTI_EMR1_EM14_Pos)               /*!< 0x00004000 */

+#define EXTI_EMR1_EM14             EXTI_EMR1_EM14_Msk                          /*!< Event Mask on line 14 */

+#define EXTI_EMR1_EM15_Pos         (15U)

+#define EXTI_EMR1_EM15_Msk         (0x1UL << EXTI_EMR1_EM15_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR1_EM15             EXTI_EMR1_EM15_Msk                          /*!< Event Mask on line 15 */

+#define EXTI_EMR1_EM16_Pos         (16U)

+#define EXTI_EMR1_EM16_Msk         (0x1UL << EXTI_EMR1_EM16_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR1_EM16             EXTI_EMR1_EM16_Msk                          /*!< Event Mask on line 16 */

+#define EXTI_EMR1_EM17_Pos         (17U)

+#define EXTI_EMR1_EM17_Msk         (0x1UL << EXTI_EMR1_EM17_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR1_EM17             EXTI_EMR1_EM17_Msk                          /*!< Event Mask on line 17 */

+#define EXTI_EMR1_EM18_Pos         (18U)

+#define EXTI_EMR1_EM18_Msk         (0x1UL << EXTI_EMR1_EM18_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR1_EM18             EXTI_EMR1_EM18_Msk                          /*!< Event Mask on line 18 */

+#define EXTI_EMR1_EM20_Pos         (20U)

+#define EXTI_EMR1_EM20_Msk         (0x1UL << EXTI_EMR1_EM20_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR1_EM20             EXTI_EMR1_EM20_Msk                          /*!< Event Mask on line 20 */

+#define EXTI_EMR1_EM21_Pos         (21U)

+#define EXTI_EMR1_EM21_Msk         (0x1UL << EXTI_EMR1_EM21_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR1_EM21             EXTI_EMR1_EM21_Msk                          /*!< Event Mask on line 21 */

+#define EXTI_EMR1_EM22_Pos         (22U)

+#define EXTI_EMR1_EM22_Msk         (0x1UL << EXTI_EMR1_EM22_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR1_EM22             EXTI_EMR1_EM22_Msk                          /*!< Event Mask on line 22 */

+#define EXTI_EMR1_EM23_Pos         (23U)

+#define EXTI_EMR1_EM23_Msk         (0x1UL << EXTI_EMR1_EM23_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR1_EM23             EXTI_EMR1_EM23_Msk                          /*!< Event Mask on line 23 */

+#define EXTI_EMR1_EM24_Pos         (24U)

+#define EXTI_EMR1_EM24_Msk         (0x1UL << EXTI_EMR1_EM24_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR1_EM24             EXTI_EMR1_EM24_Msk                          /*!< Event Mask on line 24 */

+#define EXTI_EMR1_EM25_Pos         (25U)

+#define EXTI_EMR1_EM25_Msk         (0x1UL << EXTI_EMR1_EM25_Pos)               /*!< 0x02000000 */

+#define EXTI_EMR1_EM25             EXTI_EMR1_EM25_Msk                          /*!< Event Mask on line 25 */

+#define EXTI_EMR1_EM26_Pos         (26U)

+#define EXTI_EMR1_EM26_Msk         (0x1UL << EXTI_EMR1_EM26_Pos)               /*!< 0x04000000 */

+#define EXTI_EMR1_EM26             EXTI_EMR1_EM26_Msk                          /*!< Event Mask on line 26 */

+#define EXTI_EMR1_EM27_Pos         (27U)

+#define EXTI_EMR1_EM27_Msk         (0x1UL << EXTI_EMR1_EM27_Pos)               /*!< 0x08000000 */

+#define EXTI_EMR1_EM27             EXTI_EMR1_EM27_Msk                          /*!< Event Mask on line 27 */

+#define EXTI_EMR1_EM28_Pos         (28U)

+#define EXTI_EMR1_EM28_Msk         (0x1UL << EXTI_EMR1_EM28_Pos)               /*!< 0x10000000 */

+#define EXTI_EMR1_EM28             EXTI_EMR1_EM28_Msk                          /*!< Event Mask on line 28 */

+#define EXTI_EMR1_EM29_Pos         (29U)

+#define EXTI_EMR1_EM29_Msk         (0x1UL << EXTI_EMR1_EM29_Pos)               /*!< 0x20000000 */

+#define EXTI_EMR1_EM29             EXTI_EMR1_EM29_Msk                          /*!< Event Mask on line 29 */

+#define EXTI_EMR1_EM30_Pos         (30U)

+#define EXTI_EMR1_EM30_Msk         (0x1UL << EXTI_EMR1_EM30_Pos)               /*!< 0x40000000 */

+#define EXTI_EMR1_EM30             EXTI_EMR1_EM30_Msk                          /*!< Event Mask on line 30 */

+#define EXTI_EMR1_EM31_Pos         (31U)

+#define EXTI_EMR1_EM31_Msk         (0x1UL << EXTI_EMR1_EM31_Pos)               /*!< 0x80000000 */

+#define EXTI_EMR1_EM31             EXTI_EMR1_EM31_Msk                          /*!< Event Mask on line 31 */

+

+/*******************  Bit definition for EXTI_PR1 register  ********************/

+#define EXTI_PR1_PR_Pos            (0U)

+#define EXTI_PR1_PR_Msk            (0x3FFFFFUL << EXTI_PR1_PR_Pos)             /*!< 0x003FFFFF */

+#define EXTI_PR1_PR                EXTI_PR1_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR1_PR0_Pos           (0U)

+#define EXTI_PR1_PR0_Msk           (0x1UL << EXTI_PR1_PR0_Pos)                 /*!< 0x00000001 */

+#define EXTI_PR1_PR0               EXTI_PR1_PR0_Msk                            /*!< Pending bit for line 0 */

+#define EXTI_PR1_PR1_Pos           (1U)

+#define EXTI_PR1_PR1_Msk           (0x1UL << EXTI_PR1_PR1_Pos)                 /*!< 0x00000002 */

+#define EXTI_PR1_PR1               EXTI_PR1_PR1_Msk                            /*!< Pending bit for line 1 */

+#define EXTI_PR1_PR2_Pos           (2U)

+#define EXTI_PR1_PR2_Msk           (0x1UL << EXTI_PR1_PR2_Pos)                 /*!< 0x00000004 */

+#define EXTI_PR1_PR2               EXTI_PR1_PR2_Msk                            /*!< Pending bit for line 2 */

+#define EXTI_PR1_PR3_Pos           (3U)

+#define EXTI_PR1_PR3_Msk           (0x1UL << EXTI_PR1_PR3_Pos)                 /*!< 0x00000008 */

+#define EXTI_PR1_PR3               EXTI_PR1_PR3_Msk                            /*!< Pending bit for line 3 */

+#define EXTI_PR1_PR4_Pos           (4U)

+#define EXTI_PR1_PR4_Msk           (0x1UL << EXTI_PR1_PR4_Pos)                 /*!< 0x00000010 */

+#define EXTI_PR1_PR4               EXTI_PR1_PR4_Msk                            /*!< Pending bit for line 4 */

+#define EXTI_PR1_PR5_Pos           (5U)

+#define EXTI_PR1_PR5_Msk           (0x1UL << EXTI_PR1_PR5_Pos)                 /*!< 0x00000020 */

+#define EXTI_PR1_PR5               EXTI_PR1_PR5_Msk                            /*!< Pending bit for line 5 */

+#define EXTI_PR1_PR6_Pos           (6U)

+#define EXTI_PR1_PR6_Msk           (0x1UL << EXTI_PR1_PR6_Pos)                 /*!< 0x00000040 */

+#define EXTI_PR1_PR6               EXTI_PR1_PR6_Msk                            /*!< Pending bit for line 6 */

+#define EXTI_PR1_PR7_Pos           (7U)

+#define EXTI_PR1_PR7_Msk           (0x1UL << EXTI_PR1_PR7_Pos)                 /*!< 0x00000080 */

+#define EXTI_PR1_PR7               EXTI_PR1_PR7_Msk                            /*!< Pending bit for line 7 */

+#define EXTI_PR1_PR8_Pos           (8U)

+#define EXTI_PR1_PR8_Msk           (0x1UL << EXTI_PR1_PR8_Pos)                 /*!< 0x00000100 */

+#define EXTI_PR1_PR8               EXTI_PR1_PR8_Msk                            /*!< Pending bit for line 8 */

+#define EXTI_PR1_PR9_Pos           (9U)

+#define EXTI_PR1_PR9_Msk           (0x1UL << EXTI_PR1_PR9_Pos)                 /*!< 0x00000200 */

+#define EXTI_PR1_PR9               EXTI_PR1_PR9_Msk                            /*!< Pending bit for line 9 */

+#define EXTI_PR1_PR10_Pos          (10U)

+#define EXTI_PR1_PR10_Msk          (0x1UL << EXTI_PR1_PR10_Pos)                /*!< 0x00000400 */

+#define EXTI_PR1_PR10              EXTI_PR1_PR10_Msk                           /*!< Pending bit for line 10 */

+#define EXTI_PR1_PR11_Pos          (11U)

+#define EXTI_PR1_PR11_Msk          (0x1UL << EXTI_PR1_PR11_Pos)                /*!< 0x00000800 */

+#define EXTI_PR1_PR11              EXTI_PR1_PR11_Msk                           /*!< Pending bit for line 11 */

+#define EXTI_PR1_PR12_Pos          (12U)

+#define EXTI_PR1_PR12_Msk          (0x1UL << EXTI_PR1_PR12_Pos)                /*!< 0x00001000 */

+#define EXTI_PR1_PR12              EXTI_PR1_PR12_Msk                           /*!< Pending bit for line 12 */

+#define EXTI_PR1_PR13_Pos          (13U)

+#define EXTI_PR1_PR13_Msk          (0x1UL << EXTI_PR1_PR13_Pos)                /*!< 0x00002000 */

+#define EXTI_PR1_PR13              EXTI_PR1_PR13_Msk                           /*!< Pending bit for line 13 */

+#define EXTI_PR1_PR14_Pos          (14U)

+#define EXTI_PR1_PR14_Msk          (0x1UL << EXTI_PR1_PR14_Pos)                /*!< 0x00004000 */

+#define EXTI_PR1_PR14              EXTI_PR1_PR14_Msk                           /*!< Pending bit for line 14 */

+#define EXTI_PR1_PR15_Pos          (15U)

+#define EXTI_PR1_PR15_Msk          (0x1UL << EXTI_PR1_PR15_Pos)                /*!< 0x00008000 */

+#define EXTI_PR1_PR15              EXTI_PR1_PR15_Msk                           /*!< Pending bit for line 15 */

+#define EXTI_PR1_PR16_Pos          (16U)

+#define EXTI_PR1_PR16_Msk          (0x1UL << EXTI_PR1_PR16_Pos)                /*!< 0x00010000 */

+#define EXTI_PR1_PR16              EXTI_PR1_PR16_Msk                           /*!< Pending bit for line 16 */

+#define EXTI_PR1_PR17_Pos          (17U)

+#define EXTI_PR1_PR17_Msk          (0x1UL << EXTI_PR1_PR17_Pos)                /*!< 0x00020000 */

+#define EXTI_PR1_PR17              EXTI_PR1_PR17_Msk                           /*!< Pending bit for line 17 */

+#define EXTI_PR1_PR18_Pos          (18U)

+#define EXTI_PR1_PR18_Msk          (0x1UL << EXTI_PR1_PR18_Pos)                /*!< 0x00040000 */

+#define EXTI_PR1_PR18              EXTI_PR1_PR18_Msk                           /*!< Pending bit for line 18 */

+#define EXTI_PR1_PR19_Pos          (19U)

+#define EXTI_PR1_PR19_Msk          (0x1UL << EXTI_PR1_PR19_Pos)                /*!< 0x00080000 */

+#define EXTI_PR1_PR19              EXTI_PR1_PR19_Msk                           /*!< Pending bit for line 19 */

+#define EXTI_PR1_PR20_Pos          (20U)

+#define EXTI_PR1_PR20_Msk          (0x1UL << EXTI_PR1_PR20_Pos)                /*!< 0x00100000 */

+#define EXTI_PR1_PR20              EXTI_PR1_PR20_Msk                           /*!< Pending bit for line 20 */

+#define EXTI_PR1_PR21_Pos          (21U)

+#define EXTI_PR1_PR21_Msk          (0x1UL << EXTI_PR1_PR21_Pos)                /*!< 0x00200000 */

+#define EXTI_PR1_PR21              EXTI_PR1_PR21_Msk                           /*!< Pending bit for line 21 */

+

+/*******************  Bit definition for EXTI_IMR2 register  *******************/

+#define EXTI_IMR2_IM_Pos           (0U)

+#define EXTI_IMR2_IM_Msk           (0xFFFF8FFFUL << EXTI_IMR2_IM_Pos)          /*!< 0xFFFF8FFF */

+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            /*!< Interrupt Mask            */

+#define EXTI_IMR2_IM32_Pos         (0U)

+#define EXTI_IMR2_IM32_Msk         (0x1UL << EXTI_IMR2_IM32_Pos)               /*!< 0x00000001 */

+#define EXTI_IMR2_IM32             EXTI_IMR2_IM32_Msk                          /*!< Interrupt Mask on line 32 */

+#define EXTI_IMR2_IM33_Pos         (1U)

+#define EXTI_IMR2_IM33_Msk         (0x1UL << EXTI_IMR2_IM33_Pos)               /*!< 0x00000002 */

+#define EXTI_IMR2_IM33             EXTI_IMR2_IM33_Msk                          /*!< Interrupt Mask on line 33 */

+#define EXTI_IMR2_IM34_Pos         (2U)

+#define EXTI_IMR2_IM34_Msk         (0x1UL << EXTI_IMR2_IM34_Pos)               /*!< 0x00000004 */

+#define EXTI_IMR2_IM34             EXTI_IMR2_IM34_Msk                          /*!< Interrupt Mask on line 34 */

+#define EXTI_IMR2_IM35_Pos         (3U)

+#define EXTI_IMR2_IM35_Msk         (0x1UL << EXTI_IMR2_IM35_Pos)               /*!< 0x00000008 */

+#define EXTI_IMR2_IM35             EXTI_IMR2_IM35_Msk                          /*!< Interrupt Mask on line 35 */

+#define EXTI_IMR2_IM36_Pos         (4U)

+#define EXTI_IMR2_IM36_Msk         (0x1UL << EXTI_IMR2_IM36_Pos)               /*!< 0x00000010 */

+#define EXTI_IMR2_IM36             EXTI_IMR2_IM36_Msk                          /*!< Interrupt Mask on line 36 */

+#define EXTI_IMR2_IM37_Pos         (5U)

+#define EXTI_IMR2_IM37_Msk         (0x1UL << EXTI_IMR2_IM37_Pos)               /*!< 0x00000020 */

+#define EXTI_IMR2_IM37             EXTI_IMR2_IM37_Msk                          /*!< Interrupt Mask on line 37 */

+#define EXTI_IMR2_IM38_Pos         (6U)

+#define EXTI_IMR2_IM38_Msk         (0x1UL << EXTI_IMR2_IM38_Pos)               /*!< 0x00000040 */

+#define EXTI_IMR2_IM38             EXTI_IMR2_IM38_Msk                          /*!< Interrupt Mask on line 38 */

+#define EXTI_IMR2_IM39_Pos         (7U)

+#define EXTI_IMR2_IM39_Msk         (0x1UL << EXTI_IMR2_IM39_Pos)               /*!< 0x00000080 */

+#define EXTI_IMR2_IM39             EXTI_IMR2_IM39_Msk                          /*!< Interrupt Mask on line 39 */

+#define EXTI_IMR2_IM40_Pos         (8U)

+#define EXTI_IMR2_IM40_Msk         (0x1UL << EXTI_IMR2_IM40_Pos)               /*!< 0x00000100 */

+#define EXTI_IMR2_IM40             EXTI_IMR2_IM40_Msk                          /*!< Interrupt Mask on line 40 */

+#define EXTI_IMR2_IM41_Pos         (9U)

+#define EXTI_IMR2_IM41_Msk         (0x1UL << EXTI_IMR2_IM41_Pos)               /*!< 0x00000200 */

+#define EXTI_IMR2_IM41             EXTI_IMR2_IM41_Msk                          /*!< Interrupt Mask on line 41 */

+#define EXTI_IMR2_IM42_Pos         (10U)

+#define EXTI_IMR2_IM42_Msk         (0x1UL << EXTI_IMR2_IM42_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR2_IM42             EXTI_IMR2_IM42_Msk                          /*!< Interrupt Mask on line 42 */

+#define EXTI_IMR2_IM43_Pos         (11U)

+#define EXTI_IMR2_IM43_Msk         (0x1UL << EXTI_IMR2_IM43_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR2_IM43             EXTI_IMR2_IM43_Msk                          /*!< Interrupt Mask on line 43 */

+#define EXTI_IMR2_IM47_Pos         (15U)

+#define EXTI_IMR2_IM47_Msk         (0x1UL << EXTI_IMR2_IM47_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR2_IM47             EXTI_IMR2_IM47_Msk                          /*!< Interrupt Mask on line 47 */

+#define EXTI_IMR2_IM48_Pos         (16U)

+#define EXTI_IMR2_IM48_Msk         (0x1UL << EXTI_IMR2_IM48_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR2_IM48             EXTI_IMR2_IM48_Msk                          /*!< Interrupt Mask on line 48 */

+#define EXTI_IMR2_IM49_Pos         (17U)

+#define EXTI_IMR2_IM49_Msk         (0x1UL << EXTI_IMR2_IM49_Pos)               /*!< 0x00020000 */

+#define EXTI_IMR2_IM49             EXTI_IMR2_IM49_Msk                          /*!< Interrupt Mask on line 49 */

+#define EXTI_IMR2_IM50_Pos         (18U)

+#define EXTI_IMR2_IM50_Msk         (0x1UL << EXTI_IMR2_IM50_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR2_IM50             EXTI_IMR2_IM50_Msk                          /*!< Interrupt Mask on line 50 */

+#define EXTI_IMR2_IM51_Pos         (19U)

+#define EXTI_IMR2_IM51_Msk         (0x1UL << EXTI_IMR2_IM51_Pos)               /*!< 0x00080000 */

+#define EXTI_IMR2_IM51             EXTI_IMR2_IM51_Msk                          /*!< Interrupt Mask on line 51 */

+#define EXTI_IMR2_IM52_Pos         (20U)

+#define EXTI_IMR2_IM52_Msk         (0x1UL << EXTI_IMR2_IM52_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR2_IM52             EXTI_IMR2_IM52_Msk                          /*!< Interrupt Mask on line 52 */

+#define EXTI_IMR2_IM53_Pos         (21U)

+#define EXTI_IMR2_IM53_Msk         (0x1UL << EXTI_IMR2_IM53_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR2_IM53             EXTI_IMR2_IM53_Msk                          /*!< Interrupt Mask on line 53 */

+#define EXTI_IMR2_IM54_Pos         (22U)

+#define EXTI_IMR2_IM54_Msk         (0x1UL << EXTI_IMR2_IM54_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR2_IM54             EXTI_IMR2_IM54_Msk                          /*!< Interrupt Mask on line 54 */

+#define EXTI_IMR2_IM55_Pos         (23U)

+#define EXTI_IMR2_IM55_Msk         (0x1UL << EXTI_IMR2_IM55_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR2_IM55             EXTI_IMR2_IM55_Msk                          /*!< Interrupt Mask on line 55 */

+#define EXTI_IMR2_IM56_Pos         (24U)

+#define EXTI_IMR2_IM56_Msk         (0x1UL << EXTI_IMR2_IM56_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR2_IM56             EXTI_IMR2_IM56_Msk                          /*!< Interrupt Mask on line 56 */

+#define EXTI_IMR2_IM57_Pos         (25U)

+#define EXTI_IMR2_IM57_Msk         (0x1UL << EXTI_IMR2_IM57_Pos)               /*!< 0x02000000 */

+#define EXTI_IMR2_IM57             EXTI_IMR2_IM57_Msk                          /*!< Interrupt Mask on line 57 */

+#define EXTI_IMR2_IM58_Pos         (26U)

+#define EXTI_IMR2_IM58_Msk         (0x1UL << EXTI_IMR2_IM58_Pos)               /*!< 0x04000000 */

+#define EXTI_IMR2_IM58             EXTI_IMR2_IM58_Msk                          /*!< Interrupt Mask on line 58 */

+#define EXTI_IMR2_IM59_Pos         (27U)

+#define EXTI_IMR2_IM59_Msk         (0x1UL << EXTI_IMR2_IM59_Pos)               /*!< 0x08000000 */

+#define EXTI_IMR2_IM59             EXTI_IMR2_IM59_Msk                          /*!< Interrupt Mask on line 59 */

+#define EXTI_IMR2_IM60_Pos         (28U)

+#define EXTI_IMR2_IM60_Msk         (0x1UL << EXTI_IMR2_IM60_Pos)               /*!< 0x10000000 */

+#define EXTI_IMR2_IM60             EXTI_IMR2_IM60_Msk                          /*!< Interrupt Mask on line 60 */

+#define EXTI_IMR2_IM61_Pos         (29U)

+#define EXTI_IMR2_IM61_Msk         (0x1UL << EXTI_IMR2_IM61_Pos)               /*!< 0x20000000 */

+#define EXTI_IMR2_IM61             EXTI_IMR2_IM61_Msk                          /*!< Interrupt Mask on line 61 */

+#define EXTI_IMR2_IM62_Pos         (30U)

+#define EXTI_IMR2_IM62_Msk         (0x1UL << EXTI_IMR2_IM62_Pos)               /*!< 0x40000000 */

+#define EXTI_IMR2_IM62             EXTI_IMR2_IM62_Msk                          /*!< Interrupt Mask on line 62 */

+#define EXTI_IMR2_IM63_Pos         (31U)

+#define EXTI_IMR2_IM63_Msk         (0x1UL << EXTI_IMR2_IM63_Pos)               /*!< 0x80000000 */

+#define EXTI_IMR2_IM63             EXTI_IMR2_IM63_Msk                          /*!< Interrupt Mask on line 63 */

+

+/*******************  Bit definition for EXTI_EMR2 register  *******************/

+#define EXTI_EMR2_EM_Pos           (0U)

+#define EXTI_EMR2_EM_Msk           (0xFFFF8FFFUL << EXTI_EMR2_EM_Pos)          /*!< 0xFFFF8FFF */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            /*!< Event Mask           */

+#define EXTI_EMR2_EM32_Pos         (0U)

+#define EXTI_EMR2_EM32_Msk         (0x1UL << EXTI_EMR2_EM32_Pos)               /*!< 0x00000001 */

+#define EXTI_EMR2_EM32             EXTI_EMR2_EM32_Msk                          /*!< Event Mask on line 32*/

+#define EXTI_EMR2_EM33_Pos         (1U)

+#define EXTI_EMR2_EM33_Msk         (0x1UL << EXTI_EMR2_EM33_Pos)               /*!< 0x00000002 */

+#define EXTI_EMR2_EM33             EXTI_EMR2_EM33_Msk                          /*!< Event Mask on line 33*/

+#define EXTI_EMR2_EM34_Pos         (2U)

+#define EXTI_EMR2_EM34_Msk         (0x1UL << EXTI_EMR2_EM34_Pos)               /*!< 0x00000004 */

+#define EXTI_EMR2_EM34             EXTI_EMR2_EM34_Msk                          /*!< Event Mask on line 34*/

+#define EXTI_EMR2_EM35_Pos         (3U)

+#define EXTI_EMR2_EM35_Msk         (0x1UL << EXTI_EMR2_EM35_Pos)               /*!< 0x00000008 */

+#define EXTI_EMR2_EM35             EXTI_EMR2_EM35_Msk                          /*!< Event Mask on line 35*/

+#define EXTI_EMR2_EM36_Pos         (4U)

+#define EXTI_EMR2_EM36_Msk         (0x1UL << EXTI_EMR2_EM36_Pos)               /*!< 0x00000010 */

+#define EXTI_EMR2_EM36             EXTI_EMR2_EM36_Msk                          /*!< Event Mask on line 36*/

+#define EXTI_EMR2_EM37_Pos         (5U)

+#define EXTI_EMR2_EM37_Msk         (0x1UL << EXTI_EMR2_EM37_Pos)               /*!< 0x00000020 */

+#define EXTI_EMR2_EM37             EXTI_EMR2_EM37_Msk                          /*!< Event Mask on line 37*/

+#define EXTI_EMR2_EM38_Pos         (6U)

+#define EXTI_EMR2_EM38_Msk         (0x1UL << EXTI_EMR2_EM38_Pos)               /*!< 0x00000040 */

+#define EXTI_EMR2_EM38             EXTI_EMR2_EM38_Msk                          /*!< Event Mask on line 38*/

+#define EXTI_EMR2_EM39_Pos         (7U)

+#define EXTI_EMR2_EM39_Msk         (0x1UL << EXTI_EMR2_EM39_Pos)               /*!< 0x00000080 */

+#define EXTI_EMR2_EM39             EXTI_EMR2_EM39_Msk                          /*!< Event Mask on line 39*/

+#define EXTI_EMR2_EM40_Pos         (8U)

+#define EXTI_EMR2_EM40_Msk         (0x1UL << EXTI_EMR2_EM40_Pos)               /*!< 0x00000100 */

+#define EXTI_EMR2_EM40             EXTI_EMR2_EM40_Msk                          /*!< Event Mask on line 40*/

+#define EXTI_EMR2_EM41_Pos         (9U)

+#define EXTI_EMR2_EM41_Msk         (0x1UL << EXTI_EMR2_EM41_Pos)               /*!< 0x00000200 */

+#define EXTI_EMR2_EM41             EXTI_EMR2_EM41_Msk                          /*!< Event Mask on line 41*/

+#define EXTI_EMR2_EM42_Pos         (10U)

+#define EXTI_EMR2_EM42_Msk         (0x1UL << EXTI_EMR2_EM42_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR2_EM42             EXTI_EMR2_EM42_Msk                          /*!< Event Mask on line 42 */

+#define EXTI_EMR2_EM43_Pos         (11U)

+#define EXTI_EMR2_EM43_Msk         (0x1UL << EXTI_EMR2_EM43_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR2_EM43             EXTI_EMR2_EM43_Msk                          /*!< Event Mask on line 43 */

+#define EXTI_EMR2_EM47_Pos         (15U)

+#define EXTI_EMR2_EM47_Msk         (0x1UL << EXTI_EMR2_EM47_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR2_EM47             EXTI_EMR2_EM47_Msk                          /*!< Event Mask on line 47 */

+#define EXTI_EMR2_EM48_Pos         (16U)

+#define EXTI_EMR2_EM48_Msk         (0x1UL << EXTI_EMR2_EM48_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR2_EM48             EXTI_EMR2_EM48_Msk                          /*!< Event Mask on line 48 */

+#define EXTI_EMR2_EM49_Pos         (17U)

+#define EXTI_EMR2_EM49_Msk         (0x1UL << EXTI_EMR2_EM49_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR2_EM49             EXTI_EMR2_EM49_Msk                          /*!< Event Mask on line 49 */

+#define EXTI_EMR2_EM50_Pos         (18U)

+#define EXTI_EMR2_EM50_Msk         (0x1UL << EXTI_EMR2_EM50_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR2_EM50             EXTI_EMR2_EM50_Msk                          /*!< Event Mask on line 50 */

+#define EXTI_EMR2_EM51_Pos         (19U)

+#define EXTI_EMR2_EM51_Msk         (0x1UL << EXTI_EMR2_EM51_Pos)               /*!< 0x00080000 */

+#define EXTI_EMR2_EM51             EXTI_EMR2_EM51_Msk                          /*!< Event Mask on line 51 */

+#define EXTI_EMR2_EM52_Pos         (20U)

+#define EXTI_EMR2_EM52_Msk         (0x1UL << EXTI_EMR2_EM52_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR2_EM52             EXTI_EMR2_EM52_Msk                          /*!< Event Mask on line 52 */

+#define EXTI_EMR2_EM53_Pos         (21U)

+#define EXTI_EMR2_EM53_Msk         (0x1UL << EXTI_EMR2_EM53_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR2_EM53             EXTI_EMR2_EM53_Msk                          /*!< Event Mask on line 53 */

+#define EXTI_EMR2_EM54_Pos         (22U)

+#define EXTI_EMR2_EM54_Msk         (0x1UL << EXTI_EMR2_EM54_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR2_EM54             EXTI_EMR2_EM54_Msk                          /*!< Event Mask on line 54 */

+#define EXTI_EMR2_EM55_Pos         (23U)

+#define EXTI_EMR2_EM55_Msk         (0x1UL << EXTI_EMR2_EM55_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR2_EM55             EXTI_EMR2_EM55_Msk                          /*!< Event Mask on line 55 */

+#define EXTI_EMR2_EM56_Pos         (24U)

+#define EXTI_EMR2_EM56_Msk         (0x1UL << EXTI_EMR2_EM56_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR2_EM56             EXTI_EMR2_EM56_Msk                          /*!< Event Mask on line 56 */

+#define EXTI_EMR2_EM57_Pos         (25U)

+#define EXTI_EMR2_EM57_Msk         (0x1UL << EXTI_EMR2_EM57_Pos)               /*!< 0x02000000 */

+#define EXTI_EMR2_EM57             EXTI_EMR2_EM57_Msk                          /*!< Event Mask on line 57 */

+#define EXTI_EMR2_EM58_Pos         (26U)

+#define EXTI_EMR2_EM58_Msk         (0x1UL << EXTI_EMR2_EM58_Pos)               /*!< 0x04000000 */

+#define EXTI_EMR2_EM58             EXTI_EMR2_EM58_Msk                          /*!< Event Mask on line 58 */

+#define EXTI_EMR2_EM59_Pos         (27U)

+#define EXTI_EMR2_EM59_Msk         (0x1UL << EXTI_EMR2_EM59_Pos)               /*!< 0x08000000 */

+#define EXTI_EMR2_EM59             EXTI_EMR2_EM59_Msk                          /*!< Event Mask on line 59 */

+#define EXTI_EMR2_EM60_Pos         (28U)

+#define EXTI_EMR2_EM60_Msk         (0x1UL << EXTI_EMR2_EM60_Pos)               /*!< 0x10000000 */

+#define EXTI_EMR2_EM60             EXTI_EMR2_EM60_Msk                          /*!< Event Mask on line 60 */

+#define EXTI_EMR2_EM61_Pos         (29U)

+#define EXTI_EMR2_EM61_Msk         (0x1UL << EXTI_EMR2_EM61_Pos)               /*!< 0x20000000 */

+#define EXTI_EMR2_EM61             EXTI_EMR2_EM61_Msk                          /*!< Event Mask on line 61 */

+#define EXTI_EMR2_EM62_Pos         (30U)

+#define EXTI_EMR2_EM62_Msk         (0x1UL << EXTI_EMR2_EM62_Pos)               /*!< 0x40000000 */

+#define EXTI_EMR2_EM62             EXTI_EMR2_EM62_Msk                          /*!< Event Mask on line 62 */

+#define EXTI_EMR2_EM63_Pos         (31U)

+#define EXTI_EMR2_EM63_Msk         (0x1UL << EXTI_EMR2_EM63_Pos)               /*!< 0x80000000 */

+#define EXTI_EMR2_EM63             EXTI_EMR2_EM63_Msk                          /*!< Event Mask on line 63 */

+

+/*******************  Bit definition for EXTI_PR2 register  ********************/

+#define EXTI_PR2_PR_Pos            (17U)

+#define EXTI_PR2_PR_Msk            (0x5UL << EXTI_PR2_PR_Pos)                  /*!< 0x000A0000 */

+#define EXTI_PR2_PR                EXTI_PR2_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR2_PR49_Pos          (17U)

+#define EXTI_PR2_PR49_Msk          (0x1UL << EXTI_PR2_PR49_Pos)                /*!< 0x00020000 */

+#define EXTI_PR2_PR49              EXTI_PR2_PR49_Msk                           /*!< Pending bit for line 49 */

+#define EXTI_PR2_PR51_Pos          (19U)

+#define EXTI_PR2_PR51_Msk          (0x1UL << EXTI_PR2_PR51_Pos)                /*!< 0x00080000 */

+#define EXTI_PR2_PR51              EXTI_PR2_PR51_Msk                           /*!< Pending bit for line 51 */

+

+/*******************  Bit definition for EXTI_IMR3 register  *******************/

+#define EXTI_IMR3_IM_Pos           (0U)

+#define EXTI_IMR3_IM_Msk           (0x001A527FFUL << EXTI_IMR3_IM_Pos)         /*!< 0x001A527FF */

+#define EXTI_IMR3_IM               EXTI_IMR3_IM_Msk                            /*!< Interrupt Mask            */

+#define EXTI_IMR3_IM64_Pos         (0U)

+#define EXTI_IMR3_IM64_Msk         (0x1UL << EXTI_IMR3_IM64_Pos)               /*!< 0x00000001 */

+#define EXTI_IMR3_IM64             EXTI_IMR3_IM64_Msk                          /*!< Interrupt Mask on line 64 */

+#define EXTI_IMR3_IM65_Pos         (1U)

+#define EXTI_IMR3_IM65_Msk         (0x1UL << EXTI_IMR3_IM65_Pos)               /*!< 0x00000002 */

+#define EXTI_IMR3_IM65             EXTI_IMR3_IM65_Msk                          /*!< Interrupt Mask on line 65 */

+#define EXTI_IMR3_IM66_Pos         (2U)

+#define EXTI_IMR3_IM66_Msk         (0x1UL << EXTI_IMR3_IM66_Pos)               /*!< 0x00000004 */

+#define EXTI_IMR3_IM66             EXTI_IMR3_IM66_Msk                          /*!< Interrupt Mask on line 66 */

+#define EXTI_IMR3_IM67_Pos         (3U)

+#define EXTI_IMR3_IM67_Msk         (0x1UL << EXTI_IMR3_IM67_Pos)               /*!< 0x00000008 */

+#define EXTI_IMR3_IM67             EXTI_IMR3_IM67_Msk                          /*!< Interrupt Mask on line 67 */

+#define EXTI_IMR3_IM68_Pos         (4U)

+#define EXTI_IMR3_IM68_Msk         (0x1UL << EXTI_IMR3_IM68_Pos)               /*!< 0x00000010 */

+#define EXTI_IMR3_IM68             EXTI_IMR3_IM68_Msk                          /*!< Interrupt Mask on line 68 */

+#define EXTI_IMR3_IM69_Pos         (5U)

+#define EXTI_IMR3_IM69_Msk         (0x1UL << EXTI_IMR3_IM69_Pos)               /*!< 0x00000020 */

+#define EXTI_IMR3_IM69             EXTI_IMR3_IM69_Msk                          /*!< Interrupt Mask on line 69 */

+#define EXTI_IMR3_IM70_Pos         (6U)

+#define EXTI_IMR3_IM70_Msk         (0x1UL << EXTI_IMR3_IM70_Pos)               /*!< 0x00000040 */

+#define EXTI_IMR3_IM70             EXTI_IMR3_IM70_Msk                          /*!< Interrupt Mask on line 70 */

+#define EXTI_IMR3_IM71_Pos         (7U)

+#define EXTI_IMR3_IM71_Msk         (0x1UL << EXTI_IMR3_IM71_Pos)               /*!< 0x00000080 */

+#define EXTI_IMR3_IM71             EXTI_IMR3_IM71_Msk                          /*!< Interrupt Mask on line 71 */

+#define EXTI_IMR3_IM72_Pos         (8U)

+#define EXTI_IMR3_IM72_Msk         (0x1UL << EXTI_IMR3_IM72_Pos)               /*!< 0x00000100 */

+#define EXTI_IMR3_IM72             EXTI_IMR3_IM72_Msk                          /*!< Interrupt Mask on line 72 */

+#define EXTI_IMR3_IM73_Pos         (9U)

+#define EXTI_IMR3_IM73_Msk         (0x1UL << EXTI_IMR3_IM73_Pos)               /*!< 0x00000200 */

+#define EXTI_IMR3_IM73             EXTI_IMR3_IM73_Msk                          /*!< Interrupt Mask on line 73 */

+#define EXTI_IMR3_IM74_Pos         (10U)

+#define EXTI_IMR3_IM74_Msk         (0x1UL << EXTI_IMR3_IM74_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR3_IM74             EXTI_IMR3_IM74_Msk                          /*!< Interrupt Mask on line 74 */

+#define EXTI_IMR3_IM77_Pos         (13U)

+#define EXTI_IMR3_IM77_Msk         (0x1UL << EXTI_IMR3_IM77_Pos)               /*!< 0x00002000 */

+#define EXTI_IMR3_IM77             EXTI_IMR3_IM77_Msk                          /*!< Interrupt Mask on line 77 */

+#define EXTI_IMR3_IM80_Pos         (16U)

+#define EXTI_IMR3_IM80_Msk         (0x1UL << EXTI_IMR3_IM80_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR3_IM80             EXTI_IMR3_IM80_Msk                          /*!< Interrupt Mask on line 80 */

+#define EXTI_IMR3_IM82_Pos         (18U)

+#define EXTI_IMR3_IM82_Msk         (0x1UL << EXTI_IMR3_IM82_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR3_IM82             EXTI_IMR3_IM82_Msk                          /*!< Interrupt Mask on line 82 */

+#define EXTI_IMR3_IM85_Pos         (21U)

+#define EXTI_IMR3_IM85_Msk         (0x1UL << EXTI_IMR3_IM85_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR3_IM85             EXTI_IMR3_IM85_Msk                          /*!< Interrupt Mask on line 85 */

+#define EXTI_IMR3_IM87_Pos         (23U)

+#define EXTI_IMR3_IM87_Msk         (0x1UL << EXTI_IMR3_IM87_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR3_IM87             EXTI_IMR3_IM87_Msk                          /*!< Interrupt Mask on line 87 */

+

+

+#define EXTI_IMR3_IM88_Pos         (24U)

+#define EXTI_IMR3_IM88_Msk         (0x1UL << EXTI_IMR3_IM88_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR3_IM88             EXTI_IMR3_IM88_Msk                          /*!< Interrupt Mask on line 88 */

+

+/*******************  Bit definition for EXTI_EMR3 register  *******************/

+#define EXTI_EMR3_EM_Pos           (0U)

+#define EXTI_EMR3_EM_Msk           (0x01A527FFUL << EXTI_EMR3_EM_Pos)          /*!< 0x01A527FF */

+#define EXTI_EMR3_EM               EXTI_EMR3_EM_Msk                            /*!< Event Mask           */

+#define EXTI_EMR3_EM64_Pos         (0U)

+#define EXTI_EMR3_EM64_Msk         (0x1UL << EXTI_EMR3_EM64_Pos)               /*!< 0x00000001 */

+#define EXTI_EMR3_EM64             EXTI_EMR3_EM64_Msk                          /*!< Event Mask on line 64*/

+#define EXTI_EMR3_EM65_Pos         (1U)

+#define EXTI_EMR3_EM65_Msk         (0x1UL << EXTI_EMR3_EM65_Pos)               /*!< 0x00000002 */

+#define EXTI_EMR3_EM65             EXTI_EMR3_EM65_Msk                          /*!< Event Mask on line 65*/

+#define EXTI_EMR3_EM66_Pos         (2U)

+#define EXTI_EMR3_EM66_Msk         (0x1UL << EXTI_EMR3_EM66_Pos)               /*!< 0x00000004 */

+#define EXTI_EMR3_EM66             EXTI_EMR3_EM66_Msk                          /*!< Event Mask on line 66*/

+#define EXTI_EMR3_EM67_Pos         (3U)

+#define EXTI_EMR3_EM67_Msk         (0x1UL << EXTI_EMR3_EM67_Pos)               /*!< 0x00000008 */

+#define EXTI_EMR3_EM67             EXTI_EMR3_EM67_Msk                          /*!< Event Mask on line 67*/

+#define EXTI_EMR3_EM68_Pos         (4U)

+#define EXTI_EMR3_EM68_Msk         (0x1UL << EXTI_EMR3_EM68_Pos)               /*!< 0x00000010 */

+#define EXTI_EMR3_EM68             EXTI_EMR3_EM68_Msk                          /*!< Event Mask on line 68*/

+#define EXTI_EMR3_EM69_Pos         (5U)

+#define EXTI_EMR3_EM69_Msk         (0x1UL << EXTI_EMR3_EM69_Pos)               /*!< 0x00000020 */

+#define EXTI_EMR3_EM69             EXTI_EMR3_EM69_Msk                          /*!< Event Mask on line 69*/

+#define EXTI_EMR3_EM70_Pos         (6U)

+#define EXTI_EMR3_EM70_Msk         (0x1UL << EXTI_EMR3_EM70_Pos)               /*!< 0x00000040 */

+#define EXTI_EMR3_EM70             EXTI_EMR3_EM70_Msk                          /*!< Event Mask on line 70*/

+#define EXTI_EMR3_EM71_Pos         (7U)

+#define EXTI_EMR3_EM71_Msk         (0x1UL << EXTI_EMR3_EM71_Pos)               /*!< 0x00000080 */

+#define EXTI_EMR3_EM71             EXTI_EMR3_EM71_Msk                          /*!< Event Mask on line 71*/

+#define EXTI_EMR3_EM72_Pos         (8U)

+#define EXTI_EMR3_EM72_Msk         (0x1UL << EXTI_EMR3_EM72_Pos)               /*!< 0x00000100 */

+#define EXTI_EMR3_EM72             EXTI_EMR3_EM72_Msk                          /*!< Event Mask on line 72*/

+#define EXTI_EMR3_EM73_Pos         (9U)

+#define EXTI_EMR3_EM73_Msk         (0x1UL << EXTI_EMR3_EM73_Pos)               /*!< 0x00000200 */

+#define EXTI_EMR3_EM73             EXTI_EMR3_EM73_Msk                          /*!< Event Mask on line 73*/

+#define EXTI_EMR3_EM74_Pos         (10U)

+#define EXTI_EMR3_EM74_Msk         (0x1UL << EXTI_EMR3_EM74_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR3_EM74             EXTI_EMR3_EM74_Msk                          /*!< Event Mask on line 74 */

+#define EXTI_EMR3_EM77_Pos         (13U)

+#define EXTI_EMR3_EM77_Msk         (0x1UL << EXTI_EMR3_EM77_Pos)               /*!< 0x00002000 */

+#define EXTI_EMR3_EM77             EXTI_EMR3_EM77_Msk                          /*!< Event Mask on line 77 */

+#define EXTI_EMR3_EM80_Pos         (16U)

+#define EXTI_EMR3_EM80_Msk         (0x1UL << EXTI_EMR3_EM80_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR3_EM80             EXTI_EMR3_EM80_Msk                          /*!< Event Mask on line 80 */

+#define EXTI_EMR3_EM81_Pos         (17U)

+#define EXTI_EMR3_EM81_Msk         (0x1UL << EXTI_EMR3_EM81_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR3_EM81             EXTI_EMR3_EM81_Msk                          /*!< Event Mask on line 81 */

+#define EXTI_EMR3_EM82_Pos         (18U)

+#define EXTI_EMR3_EM82_Msk         (0x1UL << EXTI_EMR3_EM82_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR3_EM82             EXTI_EMR3_EM82_Msk                          /*!< Event Mask on line 82 */

+#define EXTI_EMR3_EM85_Pos         (21U)

+#define EXTI_EMR3_EM85_Msk         (0x1UL << EXTI_EMR3_EM85_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR3_EM85             EXTI_EMR3_EM85_Msk                          /*!< Event Mask on line 85 */

+#define EXTI_EMR3_EM87_Pos         (23U)

+#define EXTI_EMR3_EM87_Msk         (0x1UL << EXTI_EMR3_EM87_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR3_EM87             EXTI_EMR3_EM87_Msk                          /*!< Event Mask on line 87 */

+

+#define EXTI_EMR3_EM88_Pos         (24U)

+#define EXTI_EMR3_EM88_Msk         (0x1UL << EXTI_EMR3_EM88_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR3_EM88             EXTI_EMR3_EM88_Msk                          /*!< Event Mask on line 88 */

+

+/*******************  Bit definition for EXTI_PR3 register  ********************/

+#define EXTI_PR3_PR_Pos            (18U)

+#define EXTI_PR3_PR_Msk            (0x9UL << EXTI_PR3_PR_Pos)                  /*!< 0x00240000 */

+#define EXTI_PR3_PR                EXTI_PR3_PR_Msk                             /*!< Pending bit             */

+#define EXTI_PR3_PR82_Pos          (18U)

+#define EXTI_PR3_PR82_Msk          (0x1UL << EXTI_PR3_PR82_Pos)                /*!< 0x00040000 */

+#define EXTI_PR3_PR82              EXTI_PR3_PR82_Msk                           /*!< Pending bit for line 82 */

+#define EXTI_PR3_PR85_Pos          (21U)

+#define EXTI_PR3_PR85_Msk          (0x1UL << EXTI_PR3_PR85_Pos)                /*!< 0x00200000 */

+#define EXTI_PR3_PR85              EXTI_PR3_PR85_Msk                           /*!< Pending bit for line 85 */

+/******************************************************************************/

+/*                                                                            */

+/*                                    FLASH                                   */

+/*                                                                            */

+/******************************************************************************/

+/*

+* @brief FLASH Global Defines

+*/

+#define FLASH_SECTOR_TOTAL                   16U                   /* 16 sectors */

+#define FLASH_SECTOR_SIZE                    0x00002000UL          /* 8 KB       */

+#define FLASH_SIZE                           0x00020000UL          /* 128 KB     */

+#define FLASH_BANK_SIZE                      FLASH_SIZE            /* 128 KB     */

+#define FLASH_LATENCY_DEFAULT                FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycles */

+#define FLASH_NB_32BITWORD_IN_FLASHWORD      4U                    /* 128 bits */

+

+/*******************  Bits definition for FLASH_ACR register  **********************/

+#define FLASH_ACR_LATENCY_Pos                (0U)

+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */

+#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */

+#define FLASH_ACR_LATENCY_0WS                (0x00000000UL)

+#define FLASH_ACR_LATENCY_1WS                (0x00000001UL)

+#define FLASH_ACR_LATENCY_2WS                (0x00000002UL)

+#define FLASH_ACR_LATENCY_3WS                (0x00000003UL)

+#define FLASH_ACR_LATENCY_4WS                (0x00000004UL)

+#define FLASH_ACR_LATENCY_5WS                (0x00000005UL)

+#define FLASH_ACR_LATENCY_6WS                (0x00000006UL)

+#define FLASH_ACR_LATENCY_7WS                (0x00000007UL)

+#define FLASH_ACR_LATENCY_8WS                (0x00000008UL)

+#define FLASH_ACR_LATENCY_9WS                (0x00000009UL)

+#define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)

+#define FLASH_ACR_LATENCY_11WS               (0x0000000BUL)

+#define FLASH_ACR_LATENCY_12WS               (0x0000000CUL)

+#define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)

+#define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)

+#define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)

+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)

+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */

+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */

+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */

+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */

+

+/*******************  Bits definition for FLASH_CR register  ***********************/

+#define FLASH_CR_LOCK_Pos                    (0U)

+#define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */

+#define FLASH_CR_LOCK                        FLASH_CR_LOCK_Msk                 /*!< Configuration lock bit */

+#define FLASH_CR_PG_Pos                      (1U)

+#define FLASH_CR_PG_Msk                      (0x1UL << FLASH_CR_PG_Pos)        /*!< 0x00000002 */

+#define FLASH_CR_PG                          FLASH_CR_PG_Msk                   /*!< Internal buffer control bit */

+#define FLASH_CR_SER_Pos                     (2U)

+#define FLASH_CR_SER_Msk                     (0x1UL << FLASH_CR_SER_Pos)       /*!< 0x00000004 */

+#define FLASH_CR_SER                         FLASH_CR_SER_Msk                  /*!< Sector erase request */

+#define FLASH_CR_BER_Pos                     (3U)

+#define FLASH_CR_BER_Msk                     (0x1UL << FLASH_CR_BER_Pos)       /*!< 0x00000008 */

+#define FLASH_CR_BER                         FLASH_CR_BER_Msk                  /*!< Bank erase request */

+#define FLASH_CR_FW_Pos                      (4U)

+#define FLASH_CR_FW_Msk                      (0x1UL << FLASH_CR_FW_Pos)        /*!< 0x00000010 */

+#define FLASH_CR_FW                          FLASH_CR_FW_Msk                   /*!< Write forcing control bit */

+#define FLASH_CR_START_Pos                   (5U)

+#define FLASH_CR_START_Msk                   (0x1UL << FLASH_CR_START_Pos)     /*!< 0x00000020 */

+#define FLASH_CR_START                       FLASH_CR_START_Msk                /*!< Erase start control bit */

+#define FLASH_CR_SNB_Pos                     (6U)

+#define FLASH_CR_SNB_Msk                     (0x7FUL << FLASH_CR_SNB_Pos)      /*!< 0x00001FC0 */

+#define FLASH_CR_SNB                         FLASH_CR_SNB_Msk                  /*!< Sector erase selection number */

+#define FLASH_CR_SNB_0                       (0x01UL << FLASH_CR_SNB_Pos)      /*!< 0x00000040 */

+#define FLASH_CR_SNB_1                       (0x02UL << FLASH_CR_SNB_Pos)      /*!< 0x00000080 */

+#define FLASH_CR_SNB_2                       (0x04UL << FLASH_CR_SNB_Pos)      /*!< 0x00000100 */

+#define FLASH_CR_SNB_3                       (0x08UL << FLASH_CR_SNB_Pos)      /*!< 0x00000200 */

+#define FLASH_CR_SNB_4                       (0x10UL << FLASH_CR_SNB_Pos)      /*!< 0x00000400 */

+#define FLASH_CR_SNB_5                       (0x20UL << FLASH_CR_SNB_Pos)      /*!< 0x00000800 */

+#define FLASH_CR_SNB_6                       (0x40UL << FLASH_CR_SNB_Pos)      /*!< 0x00001000 */

+#define FLASH_CR_CRC_EN_Pos                  (15U)

+#define FLASH_CR_CRC_EN_Msk                  (0x1UL << FLASH_CR_CRC_EN_Pos)    /*!< 0x00008000 */

+#define FLASH_CR_CRC_EN                      FLASH_CR_CRC_EN_Msk               /*!< CRC control bit */

+#define FLASH_CR_EOPIE_Pos                   (16U)

+#define FLASH_CR_EOPIE_Msk                   (0x1UL << FLASH_CR_EOPIE_Pos)     /*!< 0x00010000 */

+#define FLASH_CR_EOPIE                       FLASH_CR_EOPIE_Msk                /*!< End-of-program interrupt control bit */

+#define FLASH_CR_WRPERRIE_Pos                (17U)

+#define FLASH_CR_WRPERRIE_Msk                (0x1UL << FLASH_CR_WRPERRIE_Pos)  /*!< 0x00020000 */

+#define FLASH_CR_WRPERRIE                    FLASH_CR_WRPERRIE_Msk             /*!< Write protection error interrupt enable bit */

+#define FLASH_CR_PGSERRIE_Pos                (18U)

+#define FLASH_CR_PGSERRIE_Msk                (0x1UL << FLASH_CR_PGSERRIE_Pos)  /*!< 0x00040000 */

+#define FLASH_CR_PGSERRIE                    FLASH_CR_PGSERRIE_Msk             /*!< Programming sequence error interrupt enable bit */

+#define FLASH_CR_STRBERRIE_Pos               (19U)

+#define FLASH_CR_STRBERRIE_Msk               (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */

+#define FLASH_CR_STRBERRIE                   FLASH_CR_STRBERRIE_Msk            /*!< Strobe error interrupt enable bit */

+#define FLASH_CR_INCERRIE_Pos                (21U)

+#define FLASH_CR_INCERRIE_Msk                (0x1UL << FLASH_CR_INCERRIE_Pos)  /*!< 0x00200000 */

+#define FLASH_CR_INCERRIE                    FLASH_CR_INCERRIE_Msk             /*!< Inconsistency error interrupt enable bit */

+#define FLASH_CR_RDPERRIE_Pos                (23U)

+#define FLASH_CR_RDPERRIE_Msk                (0x1UL << FLASH_CR_RDPERRIE_Pos)  /*!< 0x00800000 */

+#define FLASH_CR_RDPERRIE                    FLASH_CR_RDPERRIE_Msk             /*!< Read protection error interrupt enable bit */

+#define FLASH_CR_RDSERRIE_Pos                (24U)

+#define FLASH_CR_RDSERRIE_Msk                (0x1UL << FLASH_CR_RDSERRIE_Pos)  /*!< 0x01000000 */

+#define FLASH_CR_RDSERRIE                    FLASH_CR_RDSERRIE_Msk             /*!< Secure error interrupt enable bit */

+#define FLASH_CR_SNECCERRIE_Pos              (25U)

+#define FLASH_CR_SNECCERRIE_Msk              (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */

+#define FLASH_CR_SNECCERRIE                  FLASH_CR_SNECCERRIE_Msk            /*!< ECC single correction error interrupt enable bit */

+#define FLASH_CR_DBECCERRIE_Pos              (26U)

+#define FLASH_CR_DBECCERRIE_Msk              (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */

+#define FLASH_CR_DBECCERRIE                  FLASH_CR_DBECCERRIE_Msk            /*!< ECC double detection error interrupt enable bit */

+#define FLASH_CR_CRCENDIE_Pos                (27U)

+#define FLASH_CR_CRCENDIE_Msk                (0x1UL << FLASH_CR_CRCENDIE_Pos)  /*!< 0x08000000 */

+#define FLASH_CR_CRCENDIE                    FLASH_CR_CRCENDIE_Msk             /*!< CRC end of calculation interrupt enable bit */

+#define FLASH_CR_CRCRDERRIE_Pos              (28U)

+#define FLASH_CR_CRCRDERRIE_Msk              (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */

+#define FLASH_CR_CRCRDERRIE                  FLASH_CR_CRCRDERRIE_Msk            /*!< CRC read error interrupt enable bit */

+

+/*******************  Bits definition for FLASH_SR register  ***********************/

+#define FLASH_SR_BSY_Pos                     (0U)

+#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)       /*!< 0x00000001 */

+#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy flag */

+#define FLASH_SR_WBNE_Pos                    (1U)

+#define FLASH_SR_WBNE_Msk                    (0x1UL << FLASH_SR_WBNE_Pos)      /*!< 0x00000002 */

+#define FLASH_SR_WBNE                        FLASH_SR_WBNE_Msk                 /*!< Write buffer not empty flag */

+#define FLASH_SR_QW_Pos                      (2U)

+#define FLASH_SR_QW_Msk                      (0x1UL << FLASH_SR_QW_Pos)        /*!< 0x00000004 */

+#define FLASH_SR_QW                          FLASH_SR_QW_Msk                   /*!< Wait queue flag */

+#define FLASH_SR_CRC_BUSY_Pos                (3U)

+#define FLASH_SR_CRC_BUSY_Msk                (0x1UL << FLASH_SR_CRC_BUSY_Pos)  /*!< 0x00000008 */

+#define FLASH_SR_CRC_BUSY                    FLASH_SR_CRC_BUSY_Msk             /*!< CRC busy flag */

+#define FLASH_SR_EOP_Pos                     (16U)

+#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)       /*!< 0x00010000 */

+#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End-of-program flag */

+#define FLASH_SR_WRPERR_Pos                  (17U)

+#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)    /*!< 0x00020000 */

+#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protection error flag */

+#define FLASH_SR_PGSERR_Pos                  (18U)

+#define FLASH_SR_PGSERR_Msk                  (0x1UL << FLASH_SR_PGSERR_Pos)    /*!< 0x00040000 */

+#define FLASH_SR_PGSERR                      FLASH_SR_PGSERR_Msk               /*!< Programming sequence error flag */

+#define FLASH_SR_STRBERR_Pos                 (19U)

+#define FLASH_SR_STRBERR_Msk                 (0x1UL << FLASH_SR_STRBERR_Pos)   /*!< 0x00080000 */

+#define FLASH_SR_STRBERR                     FLASH_SR_STRBERR_Msk              /*!< Strobe error flag */

+#define FLASH_SR_INCERR_Pos                  (21U)

+#define FLASH_SR_INCERR_Msk                  (0x1UL << FLASH_SR_INCERR_Pos)    /*!< 0x00200000 */

+#define FLASH_SR_INCERR                      FLASH_SR_INCERR_Msk               /*!< Inconsistency error flag */

+#define FLASH_SR_RDPERR_Pos                  (23U)

+#define FLASH_SR_RDPERR_Msk                  (0x1UL << FLASH_SR_RDPERR_Pos)    /*!< 0x00800000 */

+#define FLASH_SR_RDPERR                      FLASH_SR_RDPERR_Msk               /*!< Read protection error flag */

+#define FLASH_SR_RDSERR_Pos                  (24U)

+#define FLASH_SR_RDSERR_Msk                  (0x1UL << FLASH_SR_RDSERR_Pos)    /*!< 0x01000000 */

+#define FLASH_SR_RDSERR                      FLASH_SR_RDSERR_Msk               /*!< Secure error flag */

+#define FLASH_SR_SNECCERR_Pos                (25U)

+#define FLASH_SR_SNECCERR_Msk                (0x1UL << FLASH_SR_SNECCERR_Pos)  /*!< 0x02000000 */

+#define FLASH_SR_SNECCERR                    FLASH_SR_SNECCERR_Msk             /*!< Single correction error flag */

+#define FLASH_SR_DBECCERR_Pos                (26U)

+#define FLASH_SR_DBECCERR_Msk                (0x1UL << FLASH_SR_DBECCERR_Pos)  /*!< 0x04000000 */

+#define FLASH_SR_DBECCERR                    FLASH_SR_DBECCERR_Msk             /*!< ECC double detection error flag */

+#define FLASH_SR_CRCEND_Pos                  (27U)

+#define FLASH_SR_CRCEND_Msk                  (0x1UL << FLASH_SR_CRCEND_Pos)    /*!< 0x08000000 */

+#define FLASH_SR_CRCEND                      FLASH_SR_CRCEND_Msk               /*!< CRC end of calculation flag */

+#define FLASH_SR_CRCRDERR_Pos                (28U)

+#define FLASH_SR_CRCRDERR_Msk                (0x1UL << FLASH_SR_CRCRDERR_Pos)  /*!< 0x10000000 */

+#define FLASH_SR_CRCRDERR                    FLASH_SR_CRCRDERR_Msk             /*!< CRC read error flag */

+

+/*******************  Bits definition for FLASH_CCR register  *******************/

+#define FLASH_CCR_CLR_EOP_Pos                (16U)

+#define FLASH_CCR_CLR_EOP_Msk                (0x1UL << FLASH_CCR_CLR_EOP_Pos)  /*!< 0x00010000 */

+#define FLASH_CCR_CLR_EOP                    FLASH_CCR_CLR_EOP_Msk             /*!< EOP flag clear bit */

+#define FLASH_CCR_CLR_WRPERR_Pos             (17U)

+#define FLASH_CCR_CLR_WRPERR_Msk             (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */

+#define FLASH_CCR_CLR_WRPERR                 FLASH_CCR_CLR_WRPERR_Msk            /*!< WRPERR flag clear bit */

+#define FLASH_CCR_CLR_PGSERR_Pos             (18U)

+#define FLASH_CCR_CLR_PGSERR_Msk             (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */

+#define FLASH_CCR_CLR_PGSERR                 FLASH_CCR_CLR_PGSERR_Msk            /*!< PGSERR flag clear bit */

+#define FLASH_CCR_CLR_STRBERR_Pos            (19U)

+#define FLASH_CCR_CLR_STRBERR_Msk            (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */

+#define FLASH_CCR_CLR_STRBERR                FLASH_CCR_CLR_STRBERR_Msk            /*!< STRBERR flag clear bit */

+#define FLASH_CCR_CLR_INCERR_Pos             (21U)

+#define FLASH_CCR_CLR_INCERR_Msk             (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */

+#define FLASH_CCR_CLR_INCERR                 FLASH_CCR_CLR_INCERR_Msk            /*!< INCERR flag clear bit */

+#define FLASH_CCR_CLR_RDPERR_Pos             (23U)

+#define FLASH_CCR_CLR_RDPERR_Msk             (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */

+#define FLASH_CCR_CLR_RDPERR                 FLASH_CCR_CLR_RDPERR_Msk            /*!< RDPERR flag clear bit */

+#define FLASH_CCR_CLR_RDSERR_Pos             (24U)

+#define FLASH_CCR_CLR_RDSERR_Msk             (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */

+#define FLASH_CCR_CLR_RDSERR                 FLASH_CCR_CLR_RDSERR_Msk            /*!< RDSERR flag clear bit */

+#define FLASH_CCR_CLR_SNECCERR_Pos           (25U)

+#define FLASH_CCR_CLR_SNECCERR_Msk           (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */

+#define FLASH_CCR_CLR_SNECCERR               FLASH_CCR_CLR_SNECCERR_Msk            /*!< SNECCERR flag clear bit */

+#define FLASH_CCR_CLR_DBECCERR_Pos           (26U)

+#define FLASH_CCR_CLR_DBECCERR_Msk           (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */

+#define FLASH_CCR_CLR_DBECCERR               FLASH_CCR_CLR_DBECCERR_Msk            /*!< DBECCERR flag clear bit */

+#define FLASH_CCR_CLR_CRCEND_Pos             (27U)

+#define FLASH_CCR_CLR_CRCEND_Msk             (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */

+#define FLASH_CCR_CLR_CRCEND                 FLASH_CCR_CLR_CRCEND_Msk            /*!< CRCEND flag clear bit */

+#define FLASH_CCR_CLR_CRCRDERR_Pos           (28U)

+#define FLASH_CCR_CLR_CRCRDERR_Msk           (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */

+#define FLASH_CCR_CLR_CRCRDERR               FLASH_CCR_CLR_CRCRDERR_Msk            /*!< CRCRDERR flag clear bit */

+

+/*******************  Bits definition for FLASH_OPTCR register  *******************/

+#define FLASH_OPTCR_OPTLOCK_Pos              (0U)

+#define FLASH_OPTCR_OPTLOCK_Msk              (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)  /*!< 0x00000001 */

+#define FLASH_OPTCR_OPTLOCK                  FLASH_OPTCR_OPTLOCK_Msk             /*!< FLASH_OPTCR lock option configuration bit */

+#define FLASH_OPTCR_OPTSTART_Pos             (1U)

+#define FLASH_OPTCR_OPTSTART_Msk             (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */

+#define FLASH_OPTCR_OPTSTART                 FLASH_OPTCR_OPTSTART_Msk            /*!< Option byte start change option configuration bit */

+#define FLASH_OPTCR_MER_Pos                  (4U)

+#define FLASH_OPTCR_MER_Msk                  (0x1UL << FLASH_OPTCR_MER_Pos)      /*!< 0x00000010 */

+#define FLASH_OPTCR_MER                      FLASH_OPTCR_MER_Msk                 /*!< Mass erase request */

+#define FLASH_OPTCR_PG_OTP_Pos               (5U)

+#define FLASH_OPTCR_PG_OTP_Msk               (0x1UL << FLASH_OPTCR_PG_OTP_Pos)   /*!< 0x00000020 */

+#define FLASH_OPTCR_PG_OTP                   FLASH_OPTCR_PG_OTP_Msk              /*!< OTP program control bit */

+#define FLASH_OPTCR_OPTCHANGEERRIE_Pos       (30U)

+#define FLASH_OPTCR_OPTCHANGEERRIE_Msk       (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */

+#define FLASH_OPTCR_OPTCHANGEERRIE           FLASH_OPTCR_OPTCHANGEERRIE_Msk            /*!< Option byte change error interrupt enable bit */

+#define FLASH_OPTCR_SWAP_BANK_Pos            (31U)

+#define FLASH_OPTCR_SWAP_BANK_Msk            (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */

+#define FLASH_OPTCR_SWAP_BANK                FLASH_OPTCR_SWAP_BANK_Msk            /*!< Bank swapping option configuration bit */

+

+/*******************  Bits definition for FLASH_OPTSR register  ***************/

+#define FLASH_OPTSR_OPT_BUSY_Pos             (0U)

+#define FLASH_OPTSR_OPT_BUSY_Msk             (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */

+#define FLASH_OPTSR_OPT_BUSY                 FLASH_OPTSR_OPT_BUSY_Msk            /*!< Option byte change ongoing flag */

+#define FLASH_OPTSR_BOR_LEV_Pos              (2U)

+#define FLASH_OPTSR_BOR_LEV_Msk              (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */

+#define FLASH_OPTSR_BOR_LEV                  FLASH_OPTSR_BOR_LEV_Msk            /*!< Brownout level option status bit */

+#define FLASH_OPTSR_BOR_LEV_0                (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */

+#define FLASH_OPTSR_BOR_LEV_1                (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */

+#define FLASH_OPTSR_IWDG1_SW_Pos             (4U)

+#define FLASH_OPTSR_IWDG1_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */

+#define FLASH_OPTSR_IWDG1_SW                 FLASH_OPTSR_IWDG1_SW_Msk            /*!< IWDG1 control mode option status bit */

+#define FLASH_OPTSR_NRST_STOP_D1_Pos         (6U)

+#define FLASH_OPTSR_NRST_STOP_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */

+#define FLASH_OPTSR_NRST_STOP_D1             FLASH_OPTSR_NRST_STOP_D1_Msk            /*!< D1 domain DStop entry reset option status bit */

+#define FLASH_OPTSR_NRST_STBY_D1_Pos         (7U)

+#define FLASH_OPTSR_NRST_STBY_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */

+#define FLASH_OPTSR_NRST_STBY_D1             FLASH_OPTSR_NRST_STBY_D1_Msk            /*!< D1 domain DStandby entry reset option status bit */

+#define FLASH_OPTSR_RDP_Pos                  (8U)

+#define FLASH_OPTSR_RDP_Msk                  (0xFFUL << FLASH_OPTSR_RDP_Pos)   /*!< 0x0000FF00 */

+#define FLASH_OPTSR_RDP                      FLASH_OPTSR_RDP_Msk               /*!< Readout protection level option status byte */

+#define FLASH_OPTSR_VDDMMC_HSLV_Pos          (16U)

+#define FLASH_OPTSR_VDDMMC_HSLV_Msk          (0x1UL << FLASH_OPTSR_VDDMMC_HSLV_Pos) /*!< 0x00010000 */

+#define FLASH_OPTSR_VDDMMC_HSLV              FLASH_OPTSR_VDDMMC_HSLV_Msk            /*!< VDDMMC I/O high-speed at low-voltage status bit (below 2.5V) */

+#define FLASH_OPTSR_FZ_IWDG_STOP_Pos         (17U)

+#define FLASH_OPTSR_FZ_IWDG_STOP_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */

+#define FLASH_OPTSR_FZ_IWDG_STOP             FLASH_OPTSR_FZ_IWDG_STOP_Msk            /*!< IWDG Stop mode freeze option status bit */

+#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos         (18U)

+#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */

+#define FLASH_OPTSR_FZ_IWDG_SDBY             FLASH_OPTSR_FZ_IWDG_SDBY_Msk            /*!< IWDG Standby mode freeze option status bit */

+#define FLASH_OPTSR_ST_RAM_SIZE_Pos          (19U)

+#define FLASH_OPTSR_ST_RAM_SIZE_Msk          (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */

+#define FLASH_OPTSR_ST_RAM_SIZE              FLASH_OPTSR_ST_RAM_SIZE_Msk            /*!< ST RAM size option status */

+#define FLASH_OPTSR_ST_RAM_SIZE_0            (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */

+#define FLASH_OPTSR_ST_RAM_SIZE_1            (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */

+#define FLASH_OPTSR_SECURITY_Pos             (21U)

+#define FLASH_OPTSR_SECURITY_Msk             (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */

+#define FLASH_OPTSR_SECURITY                 FLASH_OPTSR_SECURITY_Msk            /*!< Security enable option status bit */

+#define FLASH_OPTSR_IO_HSLV_Pos              (29U)

+#define FLASH_OPTSR_IO_HSLV_Msk              (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */

+#define FLASH_OPTSR_IO_HSLV                  FLASH_OPTSR_IO_HSLV_Msk            /*!< I/O high-speed at low-voltage status bit */

+#define FLASH_OPTSR_OPTCHANGEERR_Pos         (30U)

+#define FLASH_OPTSR_OPTCHANGEERR_Msk         (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */

+#define FLASH_OPTSR_OPTCHANGEERR             FLASH_OPTSR_OPTCHANGEERR_Msk            /*!< Option byte change error flag */

+#define FLASH_OPTSR_SWAP_BANK_OPT_Pos        (31U)

+#define FLASH_OPTSR_SWAP_BANK_OPT_Msk        (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */

+#define FLASH_OPTSR_SWAP_BANK_OPT            FLASH_OPTSR_SWAP_BANK_OPT_Msk            /*!< Bank swapping option status bit */

+

+/*******************  Bits definition for FLASH_OPTCCR register  *******************/

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos    (30U)

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk    (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR        FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk            /*!< OPTCHANGEERR reset bit */

+

+/*******************  Bits definition for FLASH_PRAR register  *********************/

+#define FLASH_PRAR_PROT_AREA_START_Pos       (0U)

+#define FLASH_PRAR_PROT_AREA_START_Msk       (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */

+#define FLASH_PRAR_PROT_AREA_START           FLASH_PRAR_PROT_AREA_START_Msk              /*!< PCROP area start status bits */

+#define FLASH_PRAR_PROT_AREA_END_Pos         (16U)

+#define FLASH_PRAR_PROT_AREA_END_Msk         (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */

+#define FLASH_PRAR_PROT_AREA_END             FLASH_PRAR_PROT_AREA_END_Msk              /*!< PCROP area end status bits */

+#define FLASH_PRAR_DMEP_Pos                  (31U)

+#define FLASH_PRAR_DMEP_Msk                  (0x1UL << FLASH_PRAR_DMEP_Pos)    /*!< 0x80000000 */

+#define FLASH_PRAR_DMEP                      FLASH_PRAR_DMEP_Msk               /*!< PCROP protected erase enable option status bit */

+

+/*******************  Bits definition for FLASH_SCAR register  *********************/

+#define FLASH_SCAR_SEC_AREA_START_Pos        (0U)

+#define FLASH_SCAR_SEC_AREA_START_Msk        (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */

+#define FLASH_SCAR_SEC_AREA_START            FLASH_SCAR_SEC_AREA_START_Msk              /*!< Secure-only area start status bits */

+#define FLASH_SCAR_SEC_AREA_END_Pos          (16U)

+#define FLASH_SCAR_SEC_AREA_END_Msk          (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */

+#define FLASH_SCAR_SEC_AREA_END              FLASH_SCAR_SEC_AREA_END_Msk              /*!< Secure-only area end status bits */

+#define FLASH_SCAR_DMES_Pos                  (31U)

+#define FLASH_SCAR_DMES_Msk                  (0x1UL << FLASH_SCAR_DMES_Pos)    /*!< 0x80000000 */

+#define FLASH_SCAR_DMES                      FLASH_SCAR_DMES_Msk               /*!< Secure access protected erase enable option status bit */

+

+/*******************  Bits definition for FLASH_WPSN register  *********************/

+#define FLASH_WPSN_WRPSN_Pos                 (0U)

+#define FLASH_WPSN_WRPSN_Msk                 (0xFFFFFFFFUL << FLASH_WPSN_WRPSN_Pos)  /*!< 0xFFFFFFFF */

+#define FLASH_WPSN_WRPSN                     FLASH_WPSN_WRPSN_Msk              /*!< Sector write protection option status byte */

+

+/*******************  Bits definition for FLASH_BOOT_CUR register  ****************/

+#define FLASH_BOOT_ADD0_Pos                  (0U)

+#define FLASH_BOOT_ADD0_Msk                  (0xFFFFUL << FLASH_BOOT_ADD0_Pos) /*!< 0x0000FFFF */

+#define FLASH_BOOT_ADD0                      FLASH_BOOT_ADD0_Msk               /*!< Arm Cortex-M7 boot address 0 */

+#define FLASH_BOOT_ADD1_Pos                  (16U)

+#define FLASH_BOOT_ADD1_Msk                  (0xFFFFUL << FLASH_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */

+#define FLASH_BOOT_ADD1                      FLASH_BOOT_ADD1_Msk               /*!< Arm Cortex-M7 boot address 1 */

+

+

+/*******************  Bits definition for FLASH_CRCCR register  ********************/

+#define FLASH_CRCCR_CRC_SECT_Pos             (0U)

+#define FLASH_CRCCR_CRC_SECT_Msk             (0x3FUL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x0000003F */

+#define FLASH_CRCCR_CRC_SECT                 FLASH_CRCCR_CRC_SECT_Msk             /*!< CRC sector number */

+#define FLASH_CRCCR_CRC_BY_SECT_Pos          (8U)

+#define FLASH_CRCCR_CRC_BY_SECT_Msk          (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */

+#define FLASH_CRCCR_CRC_BY_SECT              FLASH_CRCCR_CRC_BY_SECT_Msk            /*!< CRC sector mode select bit */

+#define FLASH_CRCCR_ADD_SECT_Pos             (9U)

+#define FLASH_CRCCR_ADD_SECT_Msk             (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */

+#define FLASH_CRCCR_ADD_SECT                 FLASH_CRCCR_ADD_SECT_Msk            /*!< CRC sector select bit */

+#define FLASH_CRCCR_CLEAN_SECT_Pos           (10U)

+#define FLASH_CRCCR_CLEAN_SECT_Msk           (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */

+#define FLASH_CRCCR_CLEAN_SECT               FLASH_CRCCR_CLEAN_SECT_Msk            /*!< CRC sector list clear bit */

+#define FLASH_CRCCR_START_CRC_Pos            (16U)

+#define FLASH_CRCCR_START_CRC_Msk            (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */

+#define FLASH_CRCCR_START_CRC                FLASH_CRCCR_START_CRC_Msk            /*!< CRC start bit */

+#define FLASH_CRCCR_CLEAN_CRC_Pos            (17U)

+#define FLASH_CRCCR_CLEAN_CRC_Msk            (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */

+#define FLASH_CRCCR_CLEAN_CRC                FLASH_CRCCR_CLEAN_CRC_Msk            /*!< CRC clear bit */

+#define FLASH_CRCCR_CRC_BURST_Pos            (20U)

+#define FLASH_CRCCR_CRC_BURST_Msk            (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */

+#define FLASH_CRCCR_CRC_BURST                FLASH_CRCCR_CRC_BURST_Msk            /*!< CRC burst size */

+#define FLASH_CRCCR_CRC_BURST_0              (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */

+#define FLASH_CRCCR_CRC_BURST_1              (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */

+#define FLASH_CRCCR_ALL_BANK_Pos             (22U)

+#define FLASH_CRCCR_ALL_BANK_Msk             (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */

+#define FLASH_CRCCR_ALL_BANK                 FLASH_CRCCR_ALL_BANK_Msk            /*!< CRC select bit */

+

+/*******************  Bits definition for FLASH_CRCSADD register  ****************/

+#define FLASH_CRCSADD_CRC_START_ADDR_Pos     (0U)

+#define FLASH_CRCSADD_CRC_START_ADDR_Msk     (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCSADD_CRC_START_ADDR         FLASH_CRCSADD_CRC_START_ADDR_Msk                   /*!< CRC start address */

+

+/*******************  Bits definition for FLASH_CRCEADD register  ****************/

+#define FLASH_CRCEADD_CRC_END_ADDR_Pos       (0U)

+#define FLASH_CRCEADD_CRC_END_ADDR_Msk       (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCEADD_CRC_END_ADDR           FLASH_CRCEADD_CRC_END_ADDR_Msk                   /*!< CRC end address */

+

+/*******************  Bits definition for FLASH_CRCDATA register  ***************/

+#define FLASH_CRCDATA_CRC_DATA_Pos           (0U)

+#define FLASH_CRCDATA_CRC_DATA_Msk           (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCDATA_CRC_DATA               FLASH_CRCDATA_CRC_DATA_Msk                   /*!< CRC result */

+

+/*******************  Bits definition for FLASH_ECC_FA register  *******************/

+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos       (0U)

+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk       (0xFFFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x0000FFFF */

+#define FLASH_ECC_FA_FAIL_ECC_ADDR           FLASH_ECC_FA_FAIL_ECC_ADDR_Msk               /*!< ECC error address */

+#define FLASH_ECC_FA_OTP_FAIL_ECC_Pos        (31U)

+#define FLASH_ECC_FA_OTP_FAIL_ECC_Msk        (0x1UL << FLASH_ECC_FA_OTP_FAIL_ECC_Pos) /*!< 0x80000000 */

+#define FLASH_ECC_FA_OTP_FAIL_ECC            FLASH_ECC_FA_OTP_FAIL_ECC_Msk            /*!< OTP ECC error bit */

+

+/*******************  Bits definition for FLASH_OTPBL register  *******************/

+#define FLASH_OTPBL_LOCKBL_Pos               (0U)

+#define FLASH_OTPBL_LOCKBL_Msk               (0xFFFFUL << FLASH_OTPBL_LOCKBL_Pos) /*!< 0x0000FFFF */

+#define FLASH_OTPBL_LOCKBL                   FLASH_OTPBL_LOCKBL_Msk               /*!< OTP Block Lock */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          Flexible Memory Controller                        */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for FMC_BCR1 register  *******************/

+#define FMC_BCR1_CCLKEN_Pos        (20U)

+#define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */

+#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continous clock enable     */

+#define FMC_BCR1_WFDIS_Pos         (21U)

+#define FMC_BCR1_WFDIS_Msk         (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */

+#define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */

+

+#define FMC_BCR1_BMAP_Pos          (24U)

+#define FMC_BCR1_BMAP_Msk          (0x3UL << FMC_BCR1_BMAP_Pos)                /*!< 0x03000000 */

+#define FMC_BCR1_BMAP              FMC_BCR1_BMAP_Msk                           /*!<BMAP[1:0] FMC bank mapping */

+#define FMC_BCR1_BMAP_0            (0x1UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x01000000 */

+#define FMC_BCR1_BMAP_1            (0x2UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x02000000 */

+

+#define FMC_BCR1_FMCEN_Pos         (31U)

+#define FMC_BCR1_FMCEN_Msk         (0x1UL << FMC_BCR1_FMCEN_Pos)               /*!< 0x80000000 */

+#define FMC_BCR1_FMCEN             FMC_BCR1_FMCEN_Msk                          /*!<FMC controller Enable */

+/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/

+#define FMC_BCRx_MBKEN_Pos         (0U)

+#define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */

+#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */

+#define FMC_BCRx_MUXEN_Pos         (1U)

+#define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */

+#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */

+

+#define FMC_BCRx_MTYP_Pos          (2U)

+#define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */

+#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */

+#define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000004 */

+#define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000008 */

+

+#define FMC_BCRx_MWID_Pos          (4U)

+#define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */

+#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */

+#define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000010 */

+#define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000020 */

+

+#define FMC_BCRx_FACCEN_Pos        (6U)

+#define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */

+#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */

+#define FMC_BCRx_BURSTEN_Pos       (8U)

+#define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */

+#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */

+#define FMC_BCRx_WAITPOL_Pos       (9U)

+#define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */

+#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */

+#define FMC_BCRx_WAITCFG_Pos       (11U)

+#define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */

+#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */

+#define FMC_BCRx_WREN_Pos          (12U)

+#define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */

+#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */

+#define FMC_BCRx_WAITEN_Pos        (13U)

+#define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */

+#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */

+#define FMC_BCRx_EXTMOD_Pos        (14U)

+#define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */

+#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */

+#define FMC_BCRx_ASYNCWAIT_Pos     (15U)

+#define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */

+#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */

+

+#define FMC_BCRx_CPSIZE_Pos        (16U)

+#define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */

+#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<PSIZE[2:0] bits CRAM Page Size */

+#define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00010000 */

+#define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00020000 */

+#define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00040000 */

+

+#define FMC_BCRx_CBURSTRW_Pos      (19U)

+#define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */

+#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */

+

+/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/

+#define FMC_BTRx_ADDSET_Pos        (0U)

+#define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */

+#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */

+#define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000001 */

+#define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000002 */

+#define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000004 */

+#define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000008 */

+

+#define FMC_BTRx_ADDHLD_Pos        (4U)

+#define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */

+#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */

+#define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000010 */

+#define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000020 */

+#define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000040 */

+#define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000080 */

+

+#define FMC_BTRx_DATAST_Pos        (8U)

+#define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */

+#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */

+#define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000100 */

+#define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000200 */

+#define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000400 */

+#define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000800 */

+#define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00001000 */

+#define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00002000 */

+#define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00004000 */

+#define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00008000 */

+

+#define FMC_BTRx_BUSTURN_Pos       (16U)

+#define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */

+#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */

+#define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00010000 */

+#define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00020000 */

+#define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00040000 */

+#define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00080000 */

+

+#define FMC_BTRx_CLKDIV_Pos        (20U)

+#define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */

+#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */

+#define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00100000 */

+#define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00200000 */

+#define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00400000 */

+#define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00800000 */

+

+#define FMC_BTRx_DATLAT_Pos        (24U)

+#define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */

+#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */

+#define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x01000000 */

+#define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x02000000 */

+#define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x04000000 */

+#define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x08000000 */

+

+#define FMC_BTRx_ACCMOD_Pos        (28U)

+#define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */

+#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */

+#define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x10000000 */

+#define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x20000000 */

+

+/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/

+#define FMC_BWTRx_ADDSET_Pos       (0U)

+#define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */

+#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */

+#define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000001 */

+#define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000002 */

+#define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000004 */

+#define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000008 */

+

+#define FMC_BWTRx_ADDHLD_Pos       (4U)

+#define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */

+#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */

+#define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000010 */

+#define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000020 */

+#define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000040 */

+#define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000080 */

+

+#define FMC_BWTRx_DATAST_Pos       (8U)

+#define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */

+#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */

+#define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000100 */

+#define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000200 */

+#define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000400 */

+#define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000800 */

+#define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00001000 */

+#define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00002000 */

+#define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00004000 */

+#define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00008000 */

+

+#define FMC_BWTRx_BUSTURN_Pos      (16U)

+#define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */

+#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */

+#define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00010000 */

+#define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00020000 */

+#define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00040000 */

+#define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00080000 */

+

+#define FMC_BWTRx_ACCMOD_Pos       (28U)

+#define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */

+#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */

+#define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x10000000 */

+#define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x20000000 */

+

+/******************  Bit definition for FMC_PCR register  *******************/

+#define FMC_PCR_PWAITEN_Pos        (1U)

+#define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */

+#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */

+#define FMC_PCR_PBKEN_Pos          (2U)

+#define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */

+#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */

+

+#define FMC_PCR_PWID_Pos           (4U)

+#define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */

+#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */

+#define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */

+#define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */

+

+#define FMC_PCR_ECCEN_Pos          (6U)

+#define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */

+#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */

+

+#define FMC_PCR_TCLR_Pos           (9U)

+#define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */

+#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */

+#define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */

+#define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */

+#define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */

+#define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */

+

+#define FMC_PCR_TAR_Pos            (13U)

+#define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */

+#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */

+#define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */

+#define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */

+#define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */

+#define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */

+

+#define FMC_PCR_ECCPS_Pos          (17U)

+#define FMC_PCR_ECCPS_Msk          (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */

+#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */

+#define FMC_PCR_ECCPS_0            (0x1UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */

+#define FMC_PCR_ECCPS_1            (0x2UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */

+#define FMC_PCR_ECCPS_2            (0x4UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */

+

+/*******************  Bit definition for FMC_SR register  *******************/

+#define FMC_SR_IRS_Pos             (0U)

+#define FMC_SR_IRS_Msk             (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */

+#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */

+#define FMC_SR_ILS_Pos             (1U)

+#define FMC_SR_ILS_Msk             (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */

+#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */

+#define FMC_SR_IFS_Pos             (2U)

+#define FMC_SR_IFS_Msk             (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */

+#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */

+#define FMC_SR_IREN_Pos            (3U)

+#define FMC_SR_IREN_Msk            (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */

+#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */

+#define FMC_SR_ILEN_Pos            (4U)

+#define FMC_SR_ILEN_Msk            (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */

+#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */

+#define FMC_SR_IFEN_Pos            (5U)

+#define FMC_SR_IFEN_Msk            (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */

+#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */

+#define FMC_SR_FEMPT_Pos           (6U)

+#define FMC_SR_FEMPT_Msk           (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */

+#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */

+

+/******************  Bit definition for FMC_PMEM register  ******************/

+#define FMC_PMEM_MEMSET_Pos       (0U)

+#define FMC_PMEM_MEMSET_Msk       (0xFFUL << FMC_PMEM_MEMSET_Pos)            /*!< 0x000000FF */

+#define FMC_PMEM_MEMSET           FMC_PMEM_MEMSET_Msk                        /*!<MEMSET[7:0] bits (Common memory setup time) */

+#define FMC_PMEM_MEMSET_0         (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */

+#define FMC_PMEM_MEMSET_1         (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */

+#define FMC_PMEM_MEMSET_2         (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */

+#define FMC_PMEM_MEMSET_3         (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */

+#define FMC_PMEM_MEMSET_4         (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */

+#define FMC_PMEM_MEMSET_5         (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */

+#define FMC_PMEM_MEMSET_6         (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */

+#define FMC_PMEM_MEMSET_7         (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */

+

+#define FMC_PMEM_MEMWAIT_Pos      (8U)

+#define FMC_PMEM_MEMWAIT_Msk      (0xFFUL << FMC_PMEM_MEMWAIT_Pos)           /*!< 0x0000FF00 */

+#define FMC_PMEM_MEMWAIT          FMC_PMEM_MEMWAIT_Msk                       /*!<MEMWAIT[7:0] bits (Common memory wait time) */

+#define FMC_PMEM_MEMWAIT_0        (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */

+#define FMC_PMEM_MEMWAIT_1        (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */

+#define FMC_PMEM_MEMWAIT_2        (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */

+#define FMC_PMEM_MEMWAIT_3        (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */

+#define FMC_PMEM_MEMWAIT_4        (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */

+#define FMC_PMEM_MEMWAIT_5        (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */

+#define FMC_PMEM_MEMWAIT_6        (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */

+#define FMC_PMEM_MEMWAIT_7        (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */

+

+#define FMC_PMEM_MEMHOLD_Pos      (16U)

+#define FMC_PMEM_MEMHOLD_Msk      (0xFFUL << FMC_PMEM_MEMHOLD_Pos)           /*!< 0x00FF0000 */

+#define FMC_PMEM_MEMHOLD          FMC_PMEM_MEMHOLD_Msk                       /*!<MEMHOLD[7:0] bits (Common memory hold time) */

+#define FMC_PMEM_MEMHOLD_0        (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */

+#define FMC_PMEM_MEMHOLD_1        (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */

+#define FMC_PMEM_MEMHOLD_2        (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */

+#define FMC_PMEM_MEMHOLD_3        (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */

+#define FMC_PMEM_MEMHOLD_4        (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */

+#define FMC_PMEM_MEMHOLD_5        (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */

+#define FMC_PMEM_MEMHOLD_6        (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */

+#define FMC_PMEM_MEMHOLD_7        (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */

+

+#define FMC_PMEM_MEMHIZ_Pos       (24U)

+#define FMC_PMEM_MEMHIZ_Msk       (0xFFUL << FMC_PMEM_MEMHIZ_Pos)            /*!< 0xFF000000 */

+#define FMC_PMEM_MEMHIZ           FMC_PMEM_MEMHIZ_Msk                        /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */

+#define FMC_PMEM_MEMHIZ_0         (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */

+#define FMC_PMEM_MEMHIZ_1         (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */

+#define FMC_PMEM_MEMHIZ_2         (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */

+#define FMC_PMEM_MEMHIZ_3         (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */

+#define FMC_PMEM_MEMHIZ_4         (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */

+#define FMC_PMEM_MEMHIZ_5         (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */

+#define FMC_PMEM_MEMHIZ_6         (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */

+#define FMC_PMEM_MEMHIZ_7         (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */

+

+/******************  Bit definition for FMC_PATT register  ******************/

+#define FMC_PATT_ATTSET_Pos       (0U)

+#define FMC_PATT_ATTSET_Msk       (0xFFUL << FMC_PATT_ATTSET_Pos)            /*!< 0x000000FF */

+#define FMC_PATT_ATTSET           FMC_PATT_ATTSET_Msk                        /*!<ATTSET[7:0] bits (Attribute memory setup time) */

+#define FMC_PATT_ATTSET_0         (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */

+#define FMC_PATT_ATTSET_1         (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */

+#define FMC_PATT_ATTSET_2         (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */

+#define FMC_PATT_ATTSET_3         (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */

+#define FMC_PATT_ATTSET_4         (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */

+#define FMC_PATT_ATTSET_5         (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */

+#define FMC_PATT_ATTSET_6         (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */

+#define FMC_PATT_ATTSET_7         (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */

+

+#define FMC_PATT_ATTWAIT_Pos      (8U)

+#define FMC_PATT_ATTWAIT_Msk      (0xFFUL << FMC_PATT_ATTWAIT_Pos)           /*!< 0x0000FF00 */

+#define FMC_PATT_ATTWAIT          FMC_PATT_ATTWAIT_Msk                       /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */

+#define FMC_PATT_ATTWAIT_0        (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */

+#define FMC_PATT_ATTWAIT_1        (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */

+#define FMC_PATT_ATTWAIT_2        (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */

+#define FMC_PATT_ATTWAIT_3        (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */

+#define FMC_PATT_ATTWAIT_4        (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */

+#define FMC_PATT_ATTWAIT_5        (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */

+#define FMC_PATT_ATTWAIT_6        (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */

+#define FMC_PATT_ATTWAIT_7        (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */

+

+#define FMC_PATT_ATTHOLD_Pos      (16U)

+#define FMC_PATT_ATTHOLD_Msk      (0xFFUL << FMC_PATT_ATTHOLD_Pos)           /*!< 0x00FF0000 */

+#define FMC_PATT_ATTHOLD          FMC_PATT_ATTHOLD_Msk                       /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */

+#define FMC_PATT_ATTHOLD_0        (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */

+#define FMC_PATT_ATTHOLD_1        (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */

+#define FMC_PATT_ATTHOLD_2        (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */

+#define FMC_PATT_ATTHOLD_3        (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */

+#define FMC_PATT_ATTHOLD_4        (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */

+#define FMC_PATT_ATTHOLD_5        (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */

+#define FMC_PATT_ATTHOLD_6        (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */

+#define FMC_PATT_ATTHOLD_7        (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */

+

+#define FMC_PATT_ATTHIZ_Pos       (24U)

+#define FMC_PATT_ATTHIZ_Msk       (0xFFUL << FMC_PATT_ATTHIZ_Pos)            /*!< 0xFF000000 */

+#define FMC_PATT_ATTHIZ           FMC_PATT_ATTHIZ_Msk                        /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */

+#define FMC_PATT_ATTHIZ_0         (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */

+#define FMC_PATT_ATTHIZ_1         (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */

+#define FMC_PATT_ATTHIZ_2         (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */

+#define FMC_PATT_ATTHIZ_3         (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */

+#define FMC_PATT_ATTHIZ_4         (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */

+#define FMC_PATT_ATTHIZ_5         (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */

+#define FMC_PATT_ATTHIZ_6         (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */

+#define FMC_PATT_ATTHIZ_7         (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */

+

+/******************  Bit definition for FMC_ECCR3 register  ******************/

+#define FMC_ECCR3_ECC3_Pos         (0U)

+#define FMC_ECCR3_ECC3_Msk         (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)        /*!< 0xFFFFFFFF */

+#define FMC_ECCR3_ECC3             FMC_ECCR3_ECC3_Msk                          /*!<ECC result */

+

+/******************  Bit definition for FMC_SDCRx registers (x=1..4)  *********/

+#define FMC_SDCRx_NC_Pos           (0U)

+#define FMC_SDCRx_NC_Msk           (0x3UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000003 */

+#define FMC_SDCRx_NC               FMC_SDCRx_NC_Msk                            /*!<NC[1:0] bits (Number of column bits) */

+#define FMC_SDCRx_NC_0             (0x1UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000001 */

+#define FMC_SDCRx_NC_1             (0x2UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000002 */

+

+#define FMC_SDCRx_NR_Pos           (2U)

+#define FMC_SDCRx_NR_Msk           (0x3UL << FMC_SDCRx_NR_Pos)                 /*!< 0x0000000C */

+#define FMC_SDCRx_NR               FMC_SDCRx_NR_Msk                            /*!<NR[1:0] bits (Number of row bits) */

+#define FMC_SDCRx_NR_0             (0x1UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000004 */

+#define FMC_SDCRx_NR_1             (0x2UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000008 */

+

+#define FMC_SDCRx_MWID_Pos         (4U)

+#define FMC_SDCRx_MWID_Msk         (0x3UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000030 */

+#define FMC_SDCRx_MWID             FMC_SDCRx_MWID_Msk                          /*!<NR[1:0] bits (Number of row bits) */

+#define FMC_SDCRx_MWID_0           (0x1UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000010 */

+#define FMC_SDCRx_MWID_1           (0x2UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000020 */

+

+#define FMC_SDCRx_NB_Pos           (6U)

+#define FMC_SDCRx_NB_Msk           (0x1UL << FMC_SDCRx_NB_Pos)                 /*!< 0x00000040 */

+#define FMC_SDCRx_NB               FMC_SDCRx_NB_Msk                            /*!<Number of internal bank */

+

+#define FMC_SDCRx_CAS_Pos          (7U)

+#define FMC_SDCRx_CAS_Msk          (0x3UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000180 */

+#define FMC_SDCRx_CAS              FMC_SDCRx_CAS_Msk                           /*!<CAS[1:0] bits (CAS latency) */

+#define FMC_SDCRx_CAS_0            (0x1UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000080 */

+#define FMC_SDCRx_CAS_1            (0x2UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000100 */

+

+#define FMC_SDCRx_WP_Pos           (9U)

+#define FMC_SDCRx_WP_Msk           (0x1UL << FMC_SDCRx_WP_Pos)                 /*!< 0x00000200 */

+#define FMC_SDCRx_WP               FMC_SDCRx_WP_Msk                            /*!<Write protection */

+

+#define FMC_SDCRx_SDCLK_Pos        (10U)

+#define FMC_SDCRx_SDCLK_Msk        (0x3UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000C00 */

+#define FMC_SDCRx_SDCLK            FMC_SDCRx_SDCLK_Msk                         /*!<SDRAM clock configuration */

+#define FMC_SDCRx_SDCLK_0          (0x1UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000400 */

+#define FMC_SDCRx_SDCLK_1          (0x2UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000800 */

+

+#define FMC_SDCRx_RBURST_Pos       (12U)

+#define FMC_SDCRx_RBURST_Msk       (0x1UL << FMC_SDCRx_RBURST_Pos)             /*!< 0x00001000 */

+#define FMC_SDCRx_RBURST           FMC_SDCRx_RBURST_Msk                        /*!<Read burst */

+

+#define FMC_SDCRx_RPIPE_Pos        (13U)

+#define FMC_SDCRx_RPIPE_Msk        (0x3UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00006000 */

+#define FMC_SDCRx_RPIPE            FMC_SDCRx_RPIPE_Msk                         /*!<Write protection */

+#define FMC_SDCRx_RPIPE_0          (0x1UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00002000 */

+#define FMC_SDCRx_RPIPE_1          (0x2UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00004000 */

+

+/******************  Bit definition for FMC_SDTRx(1,2) register  ******************/

+#define FMC_SDTRx_TMRD_Pos         (0U)

+#define FMC_SDTRx_TMRD_Msk         (0xFUL << FMC_SDTRx_TMRD_Pos)               /*!< 0x0000000F */

+#define FMC_SDTRx_TMRD             FMC_SDTRx_TMRD_Msk                          /*!<TMRD[3:0] bits (Load mode register to active) */

+#define FMC_SDTRx_TMRD_0           (0x1UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000001 */

+#define FMC_SDTRx_TMRD_1           (0x2UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000002 */

+#define FMC_SDTRx_TMRD_2           (0x4UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000004 */

+#define FMC_SDTRx_TMRD_3           (0x8UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000008 */

+

+#define FMC_SDTRx_TXSR_Pos         (4U)

+#define FMC_SDTRx_TXSR_Msk         (0xFUL << FMC_SDTRx_TXSR_Pos)               /*!< 0x000000F0 */

+#define FMC_SDTRx_TXSR             FMC_SDTRx_TXSR_Msk                          /*!<TXSR[3:0] bits (Exit self refresh) */

+#define FMC_SDTRx_TXSR_0           (0x1UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000010 */

+#define FMC_SDTRx_TXSR_1           (0x2UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000020 */

+#define FMC_SDTRx_TXSR_2           (0x4UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000040 */

+#define FMC_SDTRx_TXSR_3           (0x8UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000080 */

+

+#define FMC_SDTRx_TRAS_Pos         (8U)

+#define FMC_SDTRx_TRAS_Msk         (0xFUL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000F00 */

+#define FMC_SDTRx_TRAS             FMC_SDTRx_TRAS_Msk                          /*!<TRAS[3:0] bits (Self refresh time) */

+#define FMC_SDTRx_TRAS_0           (0x1UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000100 */

+#define FMC_SDTRx_TRAS_1           (0x2UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000200 */

+#define FMC_SDTRx_TRAS_2           (0x4UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000400 */

+#define FMC_SDTRx_TRAS_3           (0x8UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000800 */

+

+#define FMC_SDTRx_TRC_Pos          (12U)

+#define FMC_SDTRx_TRC_Msk          (0xFUL << FMC_SDTRx_TRC_Pos)                /*!< 0x0000F000 */

+#define FMC_SDTRx_TRC              FMC_SDTRx_TRC_Msk                           /*!<TRC[2:0] bits (Row cycle delay) */

+#define FMC_SDTRx_TRC_0            (0x1UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00001000 */

+#define FMC_SDTRx_TRC_1            (0x2UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00002000 */

+#define FMC_SDTRx_TRC_2            (0x4UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00004000 */

+

+#define FMC_SDTRx_TWR_Pos          (16U)

+#define FMC_SDTRx_TWR_Msk          (0xFUL << FMC_SDTRx_TWR_Pos)                /*!< 0x000F0000 */

+#define FMC_SDTRx_TWR              FMC_SDTRx_TWR_Msk                           /*!<TRC[2:0] bits (Write recovery delay) */

+#define FMC_SDTRx_TWR_0            (0x1UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00010000 */

+#define FMC_SDTRx_TWR_1            (0x2UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00020000 */

+#define FMC_SDTRx_TWR_2            (0x4UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00040000 */

+

+#define FMC_SDTRx_TRP_Pos          (20U)

+#define FMC_SDTRx_TRP_Msk          (0xFUL << FMC_SDTRx_TRP_Pos)                /*!< 0x00F00000 */

+#define FMC_SDTRx_TRP              FMC_SDTRx_TRP_Msk                           /*!<TRP[2:0] bits (Row precharge delay) */

+#define FMC_SDTRx_TRP_0            (0x1UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00100000 */

+#define FMC_SDTRx_TRP_1            (0x2UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00200000 */

+#define FMC_SDTRx_TRP_2            (0x4UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00400000 */

+

+#define FMC_SDTRx_TRCD_Pos         (24U)

+#define FMC_SDTRx_TRCD_Msk         (0xFUL << FMC_SDTRx_TRCD_Pos)               /*!< 0x0F000000 */

+#define FMC_SDTRx_TRCD             FMC_SDTRx_TRCD_Msk                          /*!<TRP[2:0] bits (Row to column delay) */

+#define FMC_SDTRx_TRCD_0           (0x1UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x01000000 */

+#define FMC_SDTRx_TRCD_1           (0x2UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x02000000 */

+#define FMC_SDTRx_TRCD_2           (0x4UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x04000000 */

+

+/******************  Bit definition for FMC_SDCMR register  ******************/

+#define FMC_SDCMR_MODE_Pos         (0U)

+#define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */

+#define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */

+#define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */

+#define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */

+#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */

+

+#define FMC_SDCMR_CTB2_Pos         (3U)

+#define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */

+#define FMC_SDCMR_CTB2             FMC_SDCMR_CTB2_Msk                          /*!<Command target 2 */

+

+#define FMC_SDCMR_CTB1_Pos         (4U)

+#define FMC_SDCMR_CTB1_Msk         (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */

+#define FMC_SDCMR_CTB1             FMC_SDCMR_CTB1_Msk                          /*!<Command target 1 */

+

+#define FMC_SDCMR_NRFS_Pos         (5U)

+#define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */

+#define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!<NRFS[3:0] bits (Number of auto-refresh) */

+#define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000020 */

+#define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000040 */

+#define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000080 */

+#define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000100 */

+

+#define FMC_SDCMR_MRD_Pos          (9U)

+#define FMC_SDCMR_MRD_Msk          (0x1FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */

+#define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!<MRD[12:0] bits (Mode register definition) */

+

+/******************  Bit definition for FMC_SDRTR register  ******************/

+#define FMC_SDRTR_CRE_Pos          (0U)

+#define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */

+#define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!<Clear refresh error flag */

+

+#define FMC_SDRTR_COUNT_Pos        (1U)

+#define FMC_SDRTR_COUNT_Msk        (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */

+#define FMC_SDRTR_COUNT            FMC_SDRTR_COUNT_Msk                         /*!<COUNT[12:0] bits (Refresh timer count) */

+

+#define FMC_SDRTR_REIE_Pos         (14U)

+#define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */

+#define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!<RES interupt enable */

+

+/******************  Bit definition for FMC_SDSR register  ******************/

+#define FMC_SDSR_RE_Pos            (0U)

+#define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */

+#define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!<Refresh error flag */

+

+#define FMC_SDSR_MODES1_Pos        (1U)

+#define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */

+#define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!<MODES1[1:0]bits (Status mode for bank 1) */

+#define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000002 */

+#define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000004 */

+

+#define FMC_SDSR_MODES2_Pos        (3U)

+#define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */

+#define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!<MODES2[1:0]bits (Status mode for bank 2) */

+#define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000008 */

+#define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000010 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                       Graphic MMU (GFXMMU)                                 */

+/*                                                                            */

+/******************************************************************************/

+/****************** Bits definition for GFXMMU_CR register ********************/

+#define GFXMMU_CR_B0OIE_Pos                (0U)

+#define GFXMMU_CR_B0OIE_Msk                (0x1UL << GFXMMU_CR_B0OIE_Pos)       /*!< 0x00000001 */

+#define GFXMMU_CR_B0OIE                    GFXMMU_CR_B0OIE_Msk                 /*!< Buffer 0 overflow interrupt enable */

+#define GFXMMU_CR_B1OIE_Pos                (1U)

+#define GFXMMU_CR_B1OIE_Msk                (0x1UL << GFXMMU_CR_B1OIE_Pos)       /*!< 0x00000002 */

+#define GFXMMU_CR_B1OIE                    GFXMMU_CR_B1OIE_Msk                 /*!< Buffer 1 overflow interrupt enable */

+#define GFXMMU_CR_B2OIE_Pos                (2U)

+#define GFXMMU_CR_B2OIE_Msk                (0x1UL << GFXMMU_CR_B2OIE_Pos)       /*!< 0x00000004 */

+#define GFXMMU_CR_B2OIE                    GFXMMU_CR_B2OIE_Msk                 /*!< Buffer 2 overflow interrupt enable */

+#define GFXMMU_CR_B3OIE_Pos                (3U)

+#define GFXMMU_CR_B3OIE_Msk                (0x1UL << GFXMMU_CR_B3OIE_Pos)       /*!< 0x00000008 */

+#define GFXMMU_CR_B3OIE                    GFXMMU_CR_B3OIE_Msk                 /*!< Buffer 3 overflow interrupt enable */

+#define GFXMMU_CR_AMEIE_Pos                (4U)

+#define GFXMMU_CR_AMEIE_Msk                (0x1UL << GFXMMU_CR_AMEIE_Pos)       /*!< 0x00000010 */

+#define GFXMMU_CR_AMEIE                    GFXMMU_CR_AMEIE_Msk                 /*!< AHB master error interrupt enable */

+#define GFXMMU_CR_192BM_Pos                (6U)

+#define GFXMMU_CR_192BM_Msk                (0x1UL << GFXMMU_CR_192BM_Pos)       /*!< 0x00000040 */

+#define GFXMMU_CR_192BM                    GFXMMU_CR_192BM_Msk                 /*!< 192 block mode */

+#define GFXMMU_CR_CE_Pos                   (7U)

+#define GFXMMU_CR_CE_Msk                   (0x1UL << GFXMMU_CR_CE_Pos)          /*!< 0x00000080 */

+#define GFXMMU_CR_CE                       GFXMMU_CR_CE_Msk                    /*!< Cache Enable */

+#define GFXMMU_CR_CL_Pos                   (8U)

+#define GFXMMU_CR_CL_Msk                   (0x1UL << GFXMMU_CR_CL_Pos)          /*!< 0x00000100 */

+#define GFXMMU_CR_CL                       GFXMMU_CR_CL_Msk                    /*!< Cache Lock */

+#define GFXMMU_CR_CLB_Pos                  (9U)

+#define GFXMMU_CR_CLB_Msk                  (0x3UL << GFXMMU_CR_CLB_Pos)         /*!< 0x00000600 */

+#define GFXMMU_CR_CLB                      GFXMMU_CR_CLB_Msk                   /*!< CLB[1:0]: Cache Lock Buffer */

+#define GFXMMU_CR_CLB_0                    (0x1UL << GFXMMU_CR_CLB_Pos)         /*!< Cache locked on buffer 1 */

+#define GFXMMU_CR_CLB_1                    (0x2UL << GFXMMU_CR_CLB_Pos)         /*!< Cache locked on buffer 2 */

+#define GFXMMU_CR_FC_Pos                   (11U)

+#define GFXMMU_CR_FC_Msk                   (0x1UL << GFXMMU_CR_FC_Pos)          /*!< 0x00000800 */

+#define GFXMMU_CR_FC                       GFXMMU_CR_FC_Msk                    /*!< Force Caching */

+#define GFXMMU_CR_PD_Pos                   (12U)

+#define GFXMMU_CR_PD_Msk                   (0x1UL << GFXMMU_CR_PD_Pos)          /*!< 0x00001000 */

+#define GFXMMU_CR_PD                       GFXMMU_CR_PD_Msk                    /*!< Prefetch Disable */

+#define GFXMMU_CR_OC_Pos                   (16U)

+#define GFXMMU_CR_OC_Msk                   (0x1UL << GFXMMU_CR_OC_Pos)          /*!< 0x00002000 */

+#define GFXMMU_CR_OC                       GFXMMU_CR_OC_Msk                    /*!< Outter Cachability */

+#define GFXMMU_CR_OB_Pos                   (17U)

+#define GFXMMU_CR_OB_Msk                   (0x1UL << GFXMMU_CR_OB_Pos)          /*!< 0x00002000 */

+#define GFXMMU_CR_OB                       GFXMMU_CR_OB_Msk                    /*!< Outter Bufferability */

+

+/****************** Bits definition for GFXMMU_SR register ********************/

+#define GFXMMU_SR_B0OF_Pos                 (0U)

+#define GFXMMU_SR_B0OF_Msk                 (0x1UL << GFXMMU_SR_B0OF_Pos)        /*!< 0x00000001 */

+#define GFXMMU_SR_B0OF                     GFXMMU_SR_B0OF_Msk                  /*!< Buffer 0 overflow flag */

+#define GFXMMU_SR_B1OF_Pos                 (1U)

+#define GFXMMU_SR_B1OF_Msk                 (0x1UL << GFXMMU_SR_B1OF_Pos)        /*!< 0x00000002 */

+#define GFXMMU_SR_B1OF                     GFXMMU_SR_B1OF_Msk                  /*!< Buffer 1 overflow flag */

+#define GFXMMU_SR_B2OF_Pos                 (2U)

+#define GFXMMU_SR_B2OF_Msk                 (0x1UL << GFXMMU_SR_B2OF_Pos)        /*!< 0x00000004 */

+#define GFXMMU_SR_B2OF                     GFXMMU_SR_B2OF_Msk                  /*!< Buffer 2 overflow flag */

+#define GFXMMU_SR_B3OF_Pos                 (3U)

+#define GFXMMU_SR_B3OF_Msk                 (0x1UL << GFXMMU_SR_B3OF_Pos)        /*!< 0x00000008 */

+#define GFXMMU_SR_B3OF                     GFXMMU_SR_B3OF_Msk                  /*!< Buffer 3 overflow flag */

+#define GFXMMU_SR_AMEF_Pos                 (4U)

+#define GFXMMU_SR_AMEF_Msk                 (0x1UL << GFXMMU_SR_AMEF_Pos)        /*!< 0x00000010 */

+#define GFXMMU_SR_AMEF                     GFXMMU_SR_AMEF_Msk                  /*!< AHB master error flag */

+

+/****************** Bits definition for GFXMMU_FCR register *******************/

+#define GFXMMU_FCR_CB0OF_Pos               (0U)

+#define GFXMMU_FCR_CB0OF_Msk               (0x1UL << GFXMMU_FCR_CB0OF_Pos)      /*!< 0x00000001 */

+#define GFXMMU_FCR_CB0OF                   GFXMMU_FCR_CB0OF_Msk                /*!< Clear buffer 0 overflow flag */

+#define GFXMMU_FCR_CB1OF_Pos               (1U)

+#define GFXMMU_FCR_CB1OF_Msk               (0x1UL << GFXMMU_FCR_CB1OF_Pos)      /*!< 0x00000002 */

+#define GFXMMU_FCR_CB1OF                   GFXMMU_FCR_CB1OF_Msk                /*!< Clear buffer 1 overflow flag */

+#define GFXMMU_FCR_CB2OF_Pos               (2U)

+#define GFXMMU_FCR_CB2OF_Msk               (0x1UL << GFXMMU_FCR_CB2OF_Pos)      /*!< 0x00000004 */

+#define GFXMMU_FCR_CB2OF                   GFXMMU_FCR_CB2OF_Msk                /*!< Clear buffer 2 overflow flag */

+#define GFXMMU_FCR_CB3OF_Pos               (3U)

+#define GFXMMU_FCR_CB3OF_Msk               (0x1UL << GFXMMU_FCR_CB3OF_Pos)      /*!< 0x00000008 */

+#define GFXMMU_FCR_CB3OF                   GFXMMU_FCR_CB3OF_Msk                /*!< Clear buffer 3 overflow flag */

+#define GFXMMU_FCR_CAMEF_Pos               (4U)

+#define GFXMMU_FCR_CAMEF_Msk               (0x1UL << GFXMMU_FCR_CAMEF_Pos)      /*!< 0x00000010 */

+#define GFXMMU_FCR_CAMEF                   GFXMMU_FCR_CAMEF_Msk                /*!< Clear AHB master error flag */

+

+/****************** Bits definition for GFXMMU_CCR register *******************/

+#define GFXMMU_CCR_FF_Pos                  (0U)

+#define GFXMMU_CCR_FF_Msk                  (0x1UL << GFXMMU_CCR_FF_Pos)         /*!< 0x00000001 */

+#define GFXMMU_CCR_FF                      GFXMMU_CCR_FF_Msk                   /*!< Clear buffer 0 overflow flag */

+#define GFXMMU_CCR_FI_Pos                  (1U)

+#define GFXMMU_CCR_FI_Msk                  (0x1UL << GFXMMU_CCR_FI_Pos)         /*!< 0x00000002 */

+#define GFXMMU_CCR_FI                      GFXMMU_CCR_FI_Msk                   /*!< Clear buffer 1 overflow flag */

+

+/****************** Bits definition for GFXMMU_DVR register *******************/

+#define GFXMMU_DVR_DV_Pos                  (0U)

+#define GFXMMU_DVR_DV_Msk                  (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos)  /*!< 0xFFFFFFFF */

+#define GFXMMU_DVR_DV                      GFXMMU_DVR_DV_Msk                   /*!< DV[31:0] bits (Default value) */

+

+/****************** Bits definition for GFXMMU_B0CR register ******************/

+#define GFXMMU_B0CR_PBO_Pos                (4U)

+#define GFXMMU_B0CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B0CR_PBO_Pos)   /*!< 0x007FFFF0 */

+#define GFXMMU_B0CR_PBO                    GFXMMU_B0CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */

+#define GFXMMU_B0CR_PBBA_Pos               (23U)

+#define GFXMMU_B0CR_PBBA_Msk               (0x1FFUL << GFXMMU_B0CR_PBBA_Pos)    /*!< 0xFF800000 */

+#define GFXMMU_B0CR_PBBA                   GFXMMU_B0CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */

+

+/****************** Bits definition for GFXMMU_B1CR register ******************/

+#define GFXMMU_B1CR_PBO_Pos                (4U)

+#define GFXMMU_B1CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos)   /*!< 0x007FFFF0 */

+#define GFXMMU_B1CR_PBO                    GFXMMU_B1CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */

+#define GFXMMU_B1CR_PBBA_Pos               (23U)

+#define GFXMMU_B1CR_PBBA_Msk               (0x1FFUL << GFXMMU_B1CR_PBBA_Pos)    /*!< 0xFF800000 */

+#define GFXMMU_B1CR_PBBA                   GFXMMU_B1CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */

+

+/****************** Bits definition for GFXMMU_B2CR register ******************/

+#define GFXMMU_B2CR_PBO_Pos                (4U)

+#define GFXMMU_B2CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B2CR_PBO_Pos)   /*!< 0x007FFFF0 */

+#define GFXMMU_B2CR_PBO                    GFXMMU_B2CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */

+#define GFXMMU_B2CR_PBBA_Pos               (23U)

+#define GFXMMU_B2CR_PBBA_Msk               (0x1FFUL << GFXMMU_B2CR_PBBA_Pos)    /*!< 0xFF800000 */

+#define GFXMMU_B2CR_PBBA                   GFXMMU_B2CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */

+

+/****************** Bits definition for GFXMMU_B3CR register ******************/

+#define GFXMMU_B3CR_PBO_Pos                (4U)

+#define GFXMMU_B3CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B3CR_PBO_Pos)   /*!< 0x007FFFF0 */

+#define GFXMMU_B3CR_PBO                    GFXMMU_B3CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */

+#define GFXMMU_B3CR_PBBA_Pos               (23U)

+#define GFXMMU_B3CR_PBBA_Msk               (0x1FFUL << GFXMMU_B3CR_PBBA_Pos)    /*!< 0xFF800000 */

+#define GFXMMU_B3CR_PBBA                   GFXMMU_B3CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */

+

+/****************** Bits definition for GFXMMU_LUTxL register *****************/

+#define GFXMMU_LUTxL_EN_Pos                (0U)

+#define GFXMMU_LUTxL_EN_Msk                (0x1UL << GFXMMU_LUTxL_EN_Pos)       /*!< 0x00000001 */

+#define GFXMMU_LUTxL_EN                    GFXMMU_LUTxL_EN_Msk                 /*!< Enable */

+#define GFXMMU_LUTxL_FVB_Pos               (8U)

+#define GFXMMU_LUTxL_FVB_Msk               (0xFFUL << GFXMMU_LUTxL_FVB_Pos)     /*!< 0x0000FF00 */

+#define GFXMMU_LUTxL_FVB                   GFXMMU_LUTxL_FVB_Msk                /*!< FVB[7:0] bits (First visible block) */

+#define GFXMMU_LUTxL_LVB_Pos               (16U)

+#define GFXMMU_LUTxL_LVB_Msk               (0xFFUL << GFXMMU_LUTxL_LVB_Pos)     /*!< 0x00FF0000 */

+#define GFXMMU_LUTxL_LVB                   GFXMMU_LUTxL_LVB_Msk                /*!< LVB[7:0] bits (Last visible block) */

+

+/****************** Bits definition for GFXMMU_LUTxH register *****************/

+#define GFXMMU_LUTxH_LO_Pos                (4U)

+#define GFXMMU_LUTxH_LO_Msk                (0x3FFFFUL << GFXMMU_LUTxH_LO_Pos)   /*!< 0x003FFFF0 */

+#define GFXMMU_LUTxH_LO                    GFXMMU_LUTxH_LO_Msk                 /*!< LO[21:4] bits (Line offset) */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            General Purpose I/O                             */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bits definition for GPIO_MODER register  *****************/

+#define GPIO_MODER_MODE0_Pos           (0U)

+#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */

+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk

+#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */

+#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */

+

+#define GPIO_MODER_MODE1_Pos           (2U)

+#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */

+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk

+#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */

+#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */

+

+#define GPIO_MODER_MODE2_Pos           (4U)

+#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */

+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk

+#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */

+#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */

+

+#define GPIO_MODER_MODE3_Pos           (6U)

+#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */

+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk

+#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */

+#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */

+

+#define GPIO_MODER_MODE4_Pos           (8U)

+#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */

+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk

+#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */

+#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */

+

+#define GPIO_MODER_MODE5_Pos           (10U)

+#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */

+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk

+#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */

+#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */

+

+#define GPIO_MODER_MODE6_Pos           (12U)

+#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */

+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk

+#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */

+#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */

+

+#define GPIO_MODER_MODE7_Pos           (14U)

+#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */

+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk

+#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */

+#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */

+

+#define GPIO_MODER_MODE8_Pos           (16U)

+#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */

+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk

+#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */

+#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */

+

+#define GPIO_MODER_MODE9_Pos           (18U)

+#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */

+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk

+#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */

+#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */

+

+#define GPIO_MODER_MODE10_Pos          (20U)

+#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */

+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk

+#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */

+#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */

+

+#define GPIO_MODER_MODE11_Pos          (22U)

+#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */

+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk

+#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */

+#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */

+

+#define GPIO_MODER_MODE12_Pos          (24U)

+#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */

+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk

+#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */

+#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */

+

+#define GPIO_MODER_MODE13_Pos          (26U)

+#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */

+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk

+#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */

+#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */

+

+#define GPIO_MODER_MODE14_Pos          (28U)

+#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */

+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk

+#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */

+#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */

+

+#define GPIO_MODER_MODE15_Pos          (30U)

+#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */

+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk

+#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */

+#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_OTYPER register  ****************/

+#define GPIO_OTYPER_OT0_Pos            (0U)

+#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */

+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk

+#define GPIO_OTYPER_OT1_Pos            (1U)

+#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */

+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk

+#define GPIO_OTYPER_OT2_Pos            (2U)

+#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */

+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk

+#define GPIO_OTYPER_OT3_Pos            (3U)

+#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */

+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk

+#define GPIO_OTYPER_OT4_Pos            (4U)

+#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */

+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk

+#define GPIO_OTYPER_OT5_Pos            (5U)

+#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */

+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk

+#define GPIO_OTYPER_OT6_Pos            (6U)

+#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */

+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk

+#define GPIO_OTYPER_OT7_Pos            (7U)

+#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */

+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk

+#define GPIO_OTYPER_OT8_Pos            (8U)

+#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */

+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk

+#define GPIO_OTYPER_OT9_Pos            (9U)

+#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */

+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk

+#define GPIO_OTYPER_OT10_Pos           (10U)

+#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */

+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk

+#define GPIO_OTYPER_OT11_Pos           (11U)

+#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */

+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk

+#define GPIO_OTYPER_OT12_Pos           (12U)

+#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */

+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk

+#define GPIO_OTYPER_OT13_Pos           (13U)

+#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */

+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk

+#define GPIO_OTYPER_OT14_Pos           (14U)

+#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */

+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk

+#define GPIO_OTYPER_OT15_Pos           (15U)

+#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */

+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk

+

+/******************  Bits definition for GPIO_OSPEEDR register  ***************/

+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)

+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */

+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk

+#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */

+#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */

+

+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)

+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */

+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk

+#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */

+#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */

+

+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)

+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */

+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk

+#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */

+#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */

+

+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)

+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */

+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk

+#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */

+#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */

+

+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)

+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */

+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk

+#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */

+#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */

+

+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)

+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */

+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk

+#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */

+#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */

+

+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)

+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */

+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk

+#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */

+#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */

+

+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)

+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */

+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk

+#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */

+#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */

+

+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)

+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */

+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk

+#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */

+#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */

+

+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)

+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */

+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk

+#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */

+#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */

+

+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)

+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */

+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk

+#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */

+#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */

+

+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)

+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */

+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk

+#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */

+#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */

+

+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)

+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */

+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk

+#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */

+#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */

+

+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)

+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */

+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk

+#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */

+#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */

+

+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)

+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */

+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk

+#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */

+#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */

+

+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)

+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */

+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk

+#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */

+#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_PUPDR register  *****************/

+#define GPIO_PUPDR_PUPD0_Pos           (0U)

+#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */

+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk

+#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */

+#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */

+

+#define GPIO_PUPDR_PUPD1_Pos           (2U)

+#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */

+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk

+#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */

+#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */

+

+#define GPIO_PUPDR_PUPD2_Pos           (4U)

+#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */

+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk

+#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */

+#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */

+

+#define GPIO_PUPDR_PUPD3_Pos           (6U)

+#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */

+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk

+#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */

+#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */

+

+#define GPIO_PUPDR_PUPD4_Pos           (8U)

+#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */

+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk

+#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */

+#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */

+

+#define GPIO_PUPDR_PUPD5_Pos           (10U)

+#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */

+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk

+#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */

+#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */

+

+#define GPIO_PUPDR_PUPD6_Pos           (12U)

+#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */

+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk

+#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */

+#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */

+

+#define GPIO_PUPDR_PUPD7_Pos           (14U)

+#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */

+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk

+#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */

+#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */

+

+#define GPIO_PUPDR_PUPD8_Pos           (16U)

+#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */

+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk

+#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */

+#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */

+

+#define GPIO_PUPDR_PUPD9_Pos           (18U)

+#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */

+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk

+#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */

+#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */

+

+#define GPIO_PUPDR_PUPD10_Pos          (20U)

+#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */

+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk

+#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */

+#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */

+

+#define GPIO_PUPDR_PUPD11_Pos          (22U)

+#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */

+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk

+#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */

+#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */

+

+#define GPIO_PUPDR_PUPD12_Pos          (24U)

+#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */

+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk

+#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */

+#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */

+

+#define GPIO_PUPDR_PUPD13_Pos          (26U)

+#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */

+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk

+#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */

+#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */

+

+#define GPIO_PUPDR_PUPD14_Pos          (28U)

+#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */

+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk

+#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */

+#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */

+

+#define GPIO_PUPDR_PUPD15_Pos          (30U)

+#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */

+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk

+#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */

+#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_IDR register  *******************/

+#define GPIO_IDR_ID0_Pos               (0U)

+#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */

+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk

+#define GPIO_IDR_ID1_Pos               (1U)

+#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */

+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk

+#define GPIO_IDR_ID2_Pos               (2U)

+#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */

+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk

+#define GPIO_IDR_ID3_Pos               (3U)

+#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */

+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk

+#define GPIO_IDR_ID4_Pos               (4U)

+#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */

+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk

+#define GPIO_IDR_ID5_Pos               (5U)

+#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */

+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk

+#define GPIO_IDR_ID6_Pos               (6U)

+#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */

+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk

+#define GPIO_IDR_ID7_Pos               (7U)

+#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */

+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk

+#define GPIO_IDR_ID8_Pos               (8U)

+#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */

+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk

+#define GPIO_IDR_ID9_Pos               (9U)

+#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */

+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk

+#define GPIO_IDR_ID10_Pos              (10U)

+#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */

+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk

+#define GPIO_IDR_ID11_Pos              (11U)

+#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */

+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk

+#define GPIO_IDR_ID12_Pos              (12U)

+#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */

+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk

+#define GPIO_IDR_ID13_Pos              (13U)

+#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */

+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk

+#define GPIO_IDR_ID14_Pos              (14U)

+#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */

+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk

+#define GPIO_IDR_ID15_Pos              (15U)

+#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */

+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk

+

+/******************  Bits definition for GPIO_ODR register  *******************/

+#define GPIO_ODR_OD0_Pos               (0U)

+#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */

+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk

+#define GPIO_ODR_OD1_Pos               (1U)

+#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */

+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk

+#define GPIO_ODR_OD2_Pos               (2U)

+#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */

+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk

+#define GPIO_ODR_OD3_Pos               (3U)

+#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */

+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk

+#define GPIO_ODR_OD4_Pos               (4U)

+#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */

+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk

+#define GPIO_ODR_OD5_Pos               (5U)

+#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */

+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk

+#define GPIO_ODR_OD6_Pos               (6U)

+#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */

+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk

+#define GPIO_ODR_OD7_Pos               (7U)

+#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */

+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk

+#define GPIO_ODR_OD8_Pos               (8U)

+#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */

+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk

+#define GPIO_ODR_OD9_Pos               (9U)

+#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */

+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk

+#define GPIO_ODR_OD10_Pos              (10U)

+#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */

+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk

+#define GPIO_ODR_OD11_Pos              (11U)

+#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */

+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk

+#define GPIO_ODR_OD12_Pos              (12U)

+#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */

+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk

+#define GPIO_ODR_OD13_Pos              (13U)

+#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */

+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk

+#define GPIO_ODR_OD14_Pos              (14U)

+#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */

+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk

+#define GPIO_ODR_OD15_Pos              (15U)

+#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */

+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk

+

+/******************  Bits definition for GPIO_BSRR register  ******************/

+#define GPIO_BSRR_BS0_Pos              (0U)

+#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */

+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk

+#define GPIO_BSRR_BS1_Pos              (1U)

+#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */

+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk

+#define GPIO_BSRR_BS2_Pos              (2U)

+#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */

+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk

+#define GPIO_BSRR_BS3_Pos              (3U)

+#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */

+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk

+#define GPIO_BSRR_BS4_Pos              (4U)

+#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */

+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk

+#define GPIO_BSRR_BS5_Pos              (5U)

+#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */

+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk

+#define GPIO_BSRR_BS6_Pos              (6U)

+#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */

+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk

+#define GPIO_BSRR_BS7_Pos              (7U)

+#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */

+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk

+#define GPIO_BSRR_BS8_Pos              (8U)

+#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */

+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk

+#define GPIO_BSRR_BS9_Pos              (9U)

+#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */

+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk

+#define GPIO_BSRR_BS10_Pos             (10U)

+#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */

+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk

+#define GPIO_BSRR_BS11_Pos             (11U)

+#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */

+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk

+#define GPIO_BSRR_BS12_Pos             (12U)

+#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */

+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk

+#define GPIO_BSRR_BS13_Pos             (13U)

+#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */

+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk

+#define GPIO_BSRR_BS14_Pos             (14U)

+#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */

+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk

+#define GPIO_BSRR_BS15_Pos             (15U)

+#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */

+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk

+#define GPIO_BSRR_BR0_Pos              (16U)

+#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */

+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk

+#define GPIO_BSRR_BR1_Pos              (17U)

+#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */

+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk

+#define GPIO_BSRR_BR2_Pos              (18U)

+#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */

+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk

+#define GPIO_BSRR_BR3_Pos              (19U)

+#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */

+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk

+#define GPIO_BSRR_BR4_Pos              (20U)

+#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */

+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk

+#define GPIO_BSRR_BR5_Pos              (21U)

+#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */

+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk

+#define GPIO_BSRR_BR6_Pos              (22U)

+#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */

+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk

+#define GPIO_BSRR_BR7_Pos              (23U)

+#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */

+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk

+#define GPIO_BSRR_BR8_Pos              (24U)

+#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */

+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk

+#define GPIO_BSRR_BR9_Pos              (25U)

+#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */

+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk

+#define GPIO_BSRR_BR10_Pos             (26U)

+#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */

+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk

+#define GPIO_BSRR_BR11_Pos             (27U)

+#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */

+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk

+#define GPIO_BSRR_BR12_Pos             (28U)

+#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */

+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk

+#define GPIO_BSRR_BR13_Pos             (29U)

+#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */

+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk

+#define GPIO_BSRR_BR14_Pos             (30U)

+#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */

+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk

+#define GPIO_BSRR_BR15_Pos             (31U)

+#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */

+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk

+

+/****************** Bit definition for GPIO_LCKR register *********************/

+#define GPIO_LCKR_LCK0_Pos             (0U)

+#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */

+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk

+#define GPIO_LCKR_LCK1_Pos             (1U)

+#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */

+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk

+#define GPIO_LCKR_LCK2_Pos             (2U)

+#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */

+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk

+#define GPIO_LCKR_LCK3_Pos             (3U)

+#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */

+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk

+#define GPIO_LCKR_LCK4_Pos             (4U)

+#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */

+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk

+#define GPIO_LCKR_LCK5_Pos             (5U)

+#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */

+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk

+#define GPIO_LCKR_LCK6_Pos             (6U)

+#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */

+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk

+#define GPIO_LCKR_LCK7_Pos             (7U)

+#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */

+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk

+#define GPIO_LCKR_LCK8_Pos             (8U)

+#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */

+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk

+#define GPIO_LCKR_LCK9_Pos             (9U)

+#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */

+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk

+#define GPIO_LCKR_LCK10_Pos            (10U)

+#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */

+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk

+#define GPIO_LCKR_LCK11_Pos            (11U)

+#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */

+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk

+#define GPIO_LCKR_LCK12_Pos            (12U)

+#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */

+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk

+#define GPIO_LCKR_LCK13_Pos            (13U)

+#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */

+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk

+#define GPIO_LCKR_LCK14_Pos            (14U)

+#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */

+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk

+#define GPIO_LCKR_LCK15_Pos            (15U)

+#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */

+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk

+#define GPIO_LCKR_LCKK_Pos             (16U)

+#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */

+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk

+

+/****************** Bit definition for GPIO_AFRL register  ********************/

+#define GPIO_AFRL_AFSEL0_Pos           (0U)

+#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */

+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk

+#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */

+#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */

+#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */

+#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */

+#define GPIO_AFRL_AFSEL1_Pos           (4U)

+#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */

+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk

+#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */

+#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */

+#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */

+#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */

+#define GPIO_AFRL_AFSEL2_Pos           (8U)

+#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */

+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk

+#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */

+#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */

+#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */

+#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */

+#define GPIO_AFRL_AFSEL3_Pos           (12U)

+#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */

+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk

+#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */

+#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */

+#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */

+#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */

+#define GPIO_AFRL_AFSEL4_Pos           (16U)

+#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */

+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk

+#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */

+#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */

+#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */

+#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */

+#define GPIO_AFRL_AFSEL5_Pos           (20U)

+#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */

+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk

+#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */

+#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */

+#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */

+#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */

+#define GPIO_AFRL_AFSEL6_Pos           (24U)

+#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */

+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk

+#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */

+#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */

+#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */

+#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */

+#define GPIO_AFRL_AFSEL7_Pos           (28U)

+#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */

+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk

+#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */

+#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */

+#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */

+#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */

+

+/* Legacy defines */

+#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0

+#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1

+#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2

+#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3

+#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4

+#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5

+#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6

+#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7

+

+/****************** Bit definition for GPIO_AFRH register  ********************/

+#define GPIO_AFRH_AFSEL8_Pos           (0U)

+#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */

+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk

+#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */

+#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */

+#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */

+#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */

+#define GPIO_AFRH_AFSEL9_Pos           (4U)

+#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */

+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk

+#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */

+#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */

+#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */

+#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */

+#define GPIO_AFRH_AFSEL10_Pos          (8U)

+#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */

+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk

+#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */

+#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */

+#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */

+#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */

+#define GPIO_AFRH_AFSEL11_Pos          (12U)

+#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */

+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk

+#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */

+#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */

+#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */

+#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */

+#define GPIO_AFRH_AFSEL12_Pos          (16U)

+#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */

+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk

+#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */

+#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */

+#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */

+#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */

+#define GPIO_AFRH_AFSEL13_Pos          (20U)

+#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */

+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk

+#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */

+#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */

+#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */

+#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */

+#define GPIO_AFRH_AFSEL14_Pos          (24U)

+#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */

+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk

+#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */

+#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */

+#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */

+#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */

+#define GPIO_AFRH_AFSEL15_Pos          (28U)

+#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */

+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk

+#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */

+#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */

+#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */

+#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */

+

+/* Legacy defines */

+#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8

+#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9

+#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10

+#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11

+#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12

+#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13

+#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14

+#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15

+

+/******************************************************************************/

+/*                                                                            */

+/*                        HSEM HW Semaphore                                   */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for HSEM_R register  ********************/

+#define HSEM_R_PROCID_Pos         (0U)

+#define HSEM_R_PROCID_Msk         (0xFFUL << HSEM_R_PROCID_Pos)                /*!< 0x000000FF */

+#define HSEM_R_PROCID             HSEM_R_PROCID_Msk                            /*!<Semaphore ProcessID */

+#define HSEM_R_COREID_Pos         (8U)

+#define HSEM_R_COREID_Msk         (0xFFUL << HSEM_R_COREID_Pos)                /*!< 0x0000FF00 */

+#define HSEM_R_COREID             HSEM_R_COREID_Msk                            /*!<Semaphore CoreID.   */

+#define HSEM_R_LOCK_Pos           (31U)

+#define HSEM_R_LOCK_Msk           (0x1UL << HSEM_R_LOCK_Pos)                   /*!< 0x80000000 */

+#define HSEM_R_LOCK               HSEM_R_LOCK_Msk                              /*!<Lock indication.    */

+

+/********************  Bit definition for HSEM_RLR register  ******************/

+#define HSEM_RLR_PROCID_Pos       (0U)

+#define HSEM_RLR_PROCID_Msk       (0xFFUL << HSEM_RLR_PROCID_Pos)              /*!< 0x000000FF */

+#define HSEM_RLR_PROCID           HSEM_RLR_PROCID_Msk                          /*!<Semaphore ProcessID */

+#define HSEM_RLR_COREID_Pos       (8U)

+#define HSEM_RLR_COREID_Msk       (0xFFUL << HSEM_RLR_COREID_Pos)              /*!< 0x0000FF00 */

+#define HSEM_RLR_COREID           HSEM_RLR_COREID_Msk                          /*!<Semaphore CoreID.   */

+#define HSEM_RLR_LOCK_Pos         (31U)

+#define HSEM_RLR_LOCK_Msk         (0x1UL << HSEM_RLR_LOCK_Pos)                 /*!< 0x80000000 */

+#define HSEM_RLR_LOCK             HSEM_RLR_LOCK_Msk                            /*!<Lock indication.    */

+

+/********************  Bit definition for HSEM_C1IER register  *****************/

+#define HSEM_C1IER_ISE0_Pos       (0U)

+#define HSEM_C1IER_ISE0_Msk       (0x1UL << HSEM_C1IER_ISE0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1IER_ISE0           HSEM_C1IER_ISE0_Msk                          /*!<semaphore 0 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE1_Pos       (1U)

+#define HSEM_C1IER_ISE1_Msk       (0x1UL << HSEM_C1IER_ISE1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1IER_ISE1           HSEM_C1IER_ISE1_Msk                          /*!<semaphore 1 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE2_Pos       (2U)

+#define HSEM_C1IER_ISE2_Msk       (0x1UL << HSEM_C1IER_ISE2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1IER_ISE2           HSEM_C1IER_ISE2_Msk                          /*!<semaphore 2 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE3_Pos       (3U)

+#define HSEM_C1IER_ISE3_Msk       (0x1UL << HSEM_C1IER_ISE3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1IER_ISE3           HSEM_C1IER_ISE3_Msk                          /*!<semaphore 3 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE4_Pos       (4U)

+#define HSEM_C1IER_ISE4_Msk       (0x1UL << HSEM_C1IER_ISE4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1IER_ISE4           HSEM_C1IER_ISE4_Msk                          /*!<semaphore 4 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE5_Pos       (5U)

+#define HSEM_C1IER_ISE5_Msk       (0x1UL << HSEM_C1IER_ISE5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1IER_ISE5           HSEM_C1IER_ISE5_Msk                          /*!<semaphore 5 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE6_Pos       (6U)

+#define HSEM_C1IER_ISE6_Msk       (0x1UL << HSEM_C1IER_ISE6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1IER_ISE6           HSEM_C1IER_ISE6_Msk                          /*!<semaphore 6 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE7_Pos       (7U)

+#define HSEM_C1IER_ISE7_Msk       (0x1UL << HSEM_C1IER_ISE7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1IER_ISE7           HSEM_C1IER_ISE7_Msk                          /*!<semaphore 7 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE8_Pos       (8U)

+#define HSEM_C1IER_ISE8_Msk       (0x1UL << HSEM_C1IER_ISE8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1IER_ISE8           HSEM_C1IER_ISE8_Msk                          /*!<semaphore 8 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE9_Pos       (9U)

+#define HSEM_C1IER_ISE9_Msk       (0x1UL << HSEM_C1IER_ISE9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1IER_ISE9           HSEM_C1IER_ISE9_Msk                          /*!<semaphore 9 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE10_Pos      (10U)

+#define HSEM_C1IER_ISE10_Msk      (0x1UL << HSEM_C1IER_ISE10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1IER_ISE10          HSEM_C1IER_ISE10_Msk                         /*!<semaphore 10 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE11_Pos      (11U)

+#define HSEM_C1IER_ISE11_Msk      (0x1UL << HSEM_C1IER_ISE11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1IER_ISE11          HSEM_C1IER_ISE11_Msk                         /*!<semaphore 11 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE12_Pos      (12U)

+#define HSEM_C1IER_ISE12_Msk      (0x1UL << HSEM_C1IER_ISE12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1IER_ISE12          HSEM_C1IER_ISE12_Msk                         /*!<semaphore 12 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE13_Pos      (13U)

+#define HSEM_C1IER_ISE13_Msk      (0x1UL << HSEM_C1IER_ISE13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1IER_ISE13          HSEM_C1IER_ISE13_Msk                         /*!<semaphore 13 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE14_Pos      (14U)

+#define HSEM_C1IER_ISE14_Msk      (0x1UL << HSEM_C1IER_ISE14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1IER_ISE14          HSEM_C1IER_ISE14_Msk                         /*!<semaphore 14 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE15_Pos      (15U)

+#define HSEM_C1IER_ISE15_Msk      (0x1UL << HSEM_C1IER_ISE15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1IER_ISE15          HSEM_C1IER_ISE15_Msk                         /*!<semaphore 15 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE16_Pos      (16U)

+#define HSEM_C1IER_ISE16_Msk      (0x1UL << HSEM_C1IER_ISE16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1IER_ISE16          HSEM_C1IER_ISE16_Msk                         /*!<semaphore 16 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE17_Pos      (17U)

+#define HSEM_C1IER_ISE17_Msk      (0x1UL << HSEM_C1IER_ISE17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1IER_ISE17          HSEM_C1IER_ISE17_Msk                         /*!<semaphore 17 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE18_Pos      (18U)

+#define HSEM_C1IER_ISE18_Msk      (0x1UL << HSEM_C1IER_ISE18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1IER_ISE18          HSEM_C1IER_ISE18_Msk                         /*!<semaphore 18 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE19_Pos      (19U)

+#define HSEM_C1IER_ISE19_Msk      (0x1UL << HSEM_C1IER_ISE19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1IER_ISE19          HSEM_C1IER_ISE19_Msk                         /*!<semaphore 19 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE20_Pos      (20U)

+#define HSEM_C1IER_ISE20_Msk      (0x1UL << HSEM_C1IER_ISE20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1IER_ISE20          HSEM_C1IER_ISE20_Msk                         /*!<semaphore 20 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE21_Pos      (21U)

+#define HSEM_C1IER_ISE21_Msk      (0x1UL << HSEM_C1IER_ISE21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1IER_ISE21          HSEM_C1IER_ISE21_Msk                         /*!<semaphore 21 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE22_Pos      (22U)

+#define HSEM_C1IER_ISE22_Msk      (0x1UL << HSEM_C1IER_ISE22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1IER_ISE22          HSEM_C1IER_ISE22_Msk                         /*!<semaphore 22 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE23_Pos      (23U)

+#define HSEM_C1IER_ISE23_Msk      (0x1UL << HSEM_C1IER_ISE23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1IER_ISE23          HSEM_C1IER_ISE23_Msk                         /*!<semaphore 23 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE24_Pos      (24U)

+#define HSEM_C1IER_ISE24_Msk      (0x1UL << HSEM_C1IER_ISE24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1IER_ISE24          HSEM_C1IER_ISE24_Msk                         /*!<semaphore 24 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE25_Pos      (25U)

+#define HSEM_C1IER_ISE25_Msk      (0x1UL << HSEM_C1IER_ISE25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1IER_ISE25          HSEM_C1IER_ISE25_Msk                         /*!<semaphore 25 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE26_Pos      (26U)

+#define HSEM_C1IER_ISE26_Msk      (0x1UL << HSEM_C1IER_ISE26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1IER_ISE26          HSEM_C1IER_ISE26_Msk                         /*!<semaphore 26 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE27_Pos      (27U)

+#define HSEM_C1IER_ISE27_Msk      (0x1UL << HSEM_C1IER_ISE27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1IER_ISE27          HSEM_C1IER_ISE27_Msk                         /*!<semaphore 27 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE28_Pos      (28U)

+#define HSEM_C1IER_ISE28_Msk      (0x1UL << HSEM_C1IER_ISE28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1IER_ISE28          HSEM_C1IER_ISE28_Msk                         /*!<semaphore 28 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE29_Pos      (29U)

+#define HSEM_C1IER_ISE29_Msk      (0x1UL << HSEM_C1IER_ISE29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1IER_ISE29          HSEM_C1IER_ISE29_Msk                         /*!<semaphore 29 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE30_Pos      (30U)

+#define HSEM_C1IER_ISE30_Msk      (0x1UL << HSEM_C1IER_ISE30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1IER_ISE30          HSEM_C1IER_ISE30_Msk                         /*!<semaphore 30 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE31_Pos      (31U)

+#define HSEM_C1IER_ISE31_Msk      (0x1UL << HSEM_C1IER_ISE31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1IER_ISE31          HSEM_C1IER_ISE31_Msk                         /*!<semaphore 31 interrupt 0 enable bit. */

+

+/********************  Bit definition for HSEM_C1ICR register  *****************/

+#define HSEM_C1ICR_ISC0_Pos       (0U)

+#define HSEM_C1ICR_ISC0_Msk       (0x1UL << HSEM_C1ICR_ISC0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1ICR_ISC0           HSEM_C1ICR_ISC0_Msk                          /*!<semaphore 0 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC1_Pos       (1U)

+#define HSEM_C1ICR_ISC1_Msk       (0x1UL << HSEM_C1ICR_ISC1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1ICR_ISC1           HSEM_C1ICR_ISC1_Msk                          /*!<semaphore 1 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC2_Pos       (2U)

+#define HSEM_C1ICR_ISC2_Msk       (0x1UL << HSEM_C1ICR_ISC2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1ICR_ISC2           HSEM_C1ICR_ISC2_Msk                          /*!<semaphore 2 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC3_Pos       (3U)

+#define HSEM_C1ICR_ISC3_Msk       (0x1UL << HSEM_C1ICR_ISC3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1ICR_ISC3           HSEM_C1ICR_ISC3_Msk                          /*!<semaphore 3 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC4_Pos       (4U)

+#define HSEM_C1ICR_ISC4_Msk       (0x1UL << HSEM_C1ICR_ISC4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1ICR_ISC4           HSEM_C1ICR_ISC4_Msk                          /*!<semaphore 4 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC5_Pos       (5U)

+#define HSEM_C1ICR_ISC5_Msk       (0x1UL << HSEM_C1ICR_ISC5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1ICR_ISC5           HSEM_C1ICR_ISC5_Msk                          /*!<semaphore 5 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC6_Pos       (6U)

+#define HSEM_C1ICR_ISC6_Msk       (0x1UL << HSEM_C1ICR_ISC6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1ICR_ISC6           HSEM_C1ICR_ISC6_Msk                          /*!<semaphore 6 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC7_Pos       (7U)

+#define HSEM_C1ICR_ISC7_Msk       (0x1UL << HSEM_C1ICR_ISC7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1ICR_ISC7           HSEM_C1ICR_ISC7_Msk                          /*!<semaphore 7 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC8_Pos       (8U)

+#define HSEM_C1ICR_ISC8_Msk       (0x1UL << HSEM_C1ICR_ISC8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1ICR_ISC8           HSEM_C1ICR_ISC8_Msk                          /*!<semaphore 8 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC9_Pos       (9U)

+#define HSEM_C1ICR_ISC9_Msk       (0x1UL << HSEM_C1ICR_ISC9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1ICR_ISC9           HSEM_C1ICR_ISC9_Msk                          /*!<semaphore 9 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC10_Pos      (10U)

+#define HSEM_C1ICR_ISC10_Msk      (0x1UL << HSEM_C1ICR_ISC10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1ICR_ISC10          HSEM_C1ICR_ISC10_Msk                         /*!<semaphore 10 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC11_Pos      (11U)

+#define HSEM_C1ICR_ISC11_Msk      (0x1UL << HSEM_C1ICR_ISC11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1ICR_ISC11          HSEM_C1ICR_ISC11_Msk                         /*!<semaphore 11 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC12_Pos      (12U)

+#define HSEM_C1ICR_ISC12_Msk      (0x1UL << HSEM_C1ICR_ISC12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1ICR_ISC12          HSEM_C1ICR_ISC12_Msk                         /*!<semaphore 12 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC13_Pos      (13U)

+#define HSEM_C1ICR_ISC13_Msk      (0x1UL << HSEM_C1ICR_ISC13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1ICR_ISC13          HSEM_C1ICR_ISC13_Msk                         /*!<semaphore 13 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC14_Pos      (14U)

+#define HSEM_C1ICR_ISC14_Msk      (0x1UL << HSEM_C1ICR_ISC14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1ICR_ISC14          HSEM_C1ICR_ISC14_Msk                         /*!<semaphore 14 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC15_Pos      (15U)

+#define HSEM_C1ICR_ISC15_Msk      (0x1UL << HSEM_C1ICR_ISC15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1ICR_ISC15          HSEM_C1ICR_ISC15_Msk                         /*!<semaphore 15 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC16_Pos      (16U)

+#define HSEM_C1ICR_ISC16_Msk      (0x1UL << HSEM_C1ICR_ISC16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1ICR_ISC16          HSEM_C1ICR_ISC16_Msk                         /*!<semaphore 16 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC17_Pos      (17U)

+#define HSEM_C1ICR_ISC17_Msk      (0x1UL << HSEM_C1ICR_ISC17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1ICR_ISC17          HSEM_C1ICR_ISC17_Msk                         /*!<semaphore 17 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC18_Pos      (18U)

+#define HSEM_C1ICR_ISC18_Msk      (0x1UL << HSEM_C1ICR_ISC18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1ICR_ISC18          HSEM_C1ICR_ISC18_Msk                         /*!<semaphore 18 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC19_Pos      (19U)

+#define HSEM_C1ICR_ISC19_Msk      (0x1UL << HSEM_C1ICR_ISC19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1ICR_ISC19          HSEM_C1ICR_ISC19_Msk                         /*!<semaphore 19 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC20_Pos      (20U)

+#define HSEM_C1ICR_ISC20_Msk      (0x1UL << HSEM_C1ICR_ISC20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1ICR_ISC20          HSEM_C1ICR_ISC20_Msk                         /*!<semaphore 20 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC21_Pos      (21U)

+#define HSEM_C1ICR_ISC21_Msk      (0x1UL << HSEM_C1ICR_ISC21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1ICR_ISC21          HSEM_C1ICR_ISC21_Msk                         /*!<semaphore 21 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC22_Pos      (22U)

+#define HSEM_C1ICR_ISC22_Msk      (0x1UL << HSEM_C1ICR_ISC22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1ICR_ISC22          HSEM_C1ICR_ISC22_Msk                         /*!<semaphore 22 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC23_Pos      (23U)

+#define HSEM_C1ICR_ISC23_Msk      (0x1UL << HSEM_C1ICR_ISC23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1ICR_ISC23          HSEM_C1ICR_ISC23_Msk                         /*!<semaphore 23 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC24_Pos      (24U)

+#define HSEM_C1ICR_ISC24_Msk      (0x1UL << HSEM_C1ICR_ISC24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1ICR_ISC24          HSEM_C1ICR_ISC24_Msk                         /*!<semaphore 24 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC25_Pos      (25U)

+#define HSEM_C1ICR_ISC25_Msk      (0x1UL << HSEM_C1ICR_ISC25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1ICR_ISC25          HSEM_C1ICR_ISC25_Msk                         /*!<semaphore 25 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC26_Pos      (26U)

+#define HSEM_C1ICR_ISC26_Msk      (0x1UL << HSEM_C1ICR_ISC26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1ICR_ISC26          HSEM_C1ICR_ISC26_Msk                         /*!<semaphore 26 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC27_Pos      (27U)

+#define HSEM_C1ICR_ISC27_Msk      (0x1UL << HSEM_C1ICR_ISC27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1ICR_ISC27          HSEM_C1ICR_ISC27_Msk                         /*!<semaphore 27 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC28_Pos      (28U)

+#define HSEM_C1ICR_ISC28_Msk      (0x1UL << HSEM_C1ICR_ISC28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1ICR_ISC28          HSEM_C1ICR_ISC28_Msk                         /*!<semaphore 28 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC29_Pos      (29U)

+#define HSEM_C1ICR_ISC29_Msk      (0x1UL << HSEM_C1ICR_ISC29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1ICR_ISC29          HSEM_C1ICR_ISC29_Msk                         /*!<semaphore 29 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC30_Pos      (30U)

+#define HSEM_C1ICR_ISC30_Msk      (0x1UL << HSEM_C1ICR_ISC30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1ICR_ISC30          HSEM_C1ICR_ISC30_Msk                         /*!<semaphore 30 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC31_Pos      (31U)

+#define HSEM_C1ICR_ISC31_Msk      (0x1UL << HSEM_C1ICR_ISC31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1ICR_ISC31          HSEM_C1ICR_ISC31_Msk                         /*!<semaphore 31 interrupt 0 clear bit. */

+

+/********************  Bit definition for HSEM_C1ISR register  *****************/

+#define HSEM_C1ISR_ISF0_Pos       (0U)

+#define HSEM_C1ISR_ISF0_Msk       (0x1UL << HSEM_C1ISR_ISF0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1ISR_ISF0           HSEM_C1ISR_ISF0_Msk                          /*!<semaphore 0 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF1_Pos       (1U)

+#define HSEM_C1ISR_ISF1_Msk       (0x1UL << HSEM_C1ISR_ISF1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1ISR_ISF1           HSEM_C1ISR_ISF1_Msk                          /*!<semaphore 1 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF2_Pos       (2U)

+#define HSEM_C1ISR_ISF2_Msk       (0x1UL << HSEM_C1ISR_ISF2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1ISR_ISF2           HSEM_C1ISR_ISF2_Msk                          /*!<semaphore 2 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF3_Pos       (3U)

+#define HSEM_C1ISR_ISF3_Msk       (0x1UL << HSEM_C1ISR_ISF3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1ISR_ISF3           HSEM_C1ISR_ISF3_Msk                          /*!<semaphore 3 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF4_Pos       (4U)

+#define HSEM_C1ISR_ISF4_Msk       (0x1UL << HSEM_C1ISR_ISF4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1ISR_ISF4           HSEM_C1ISR_ISF4_Msk                          /*!<semaphore 4 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF5_Pos       (5U)

+#define HSEM_C1ISR_ISF5_Msk       (0x1UL << HSEM_C1ISR_ISF5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1ISR_ISF5           HSEM_C1ISR_ISF5_Msk                          /*!<semaphore 5 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF6_Pos       (6U)

+#define HSEM_C1ISR_ISF6_Msk       (0x1UL << HSEM_C1ISR_ISF6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1ISR_ISF6           HSEM_C1ISR_ISF6_Msk                          /*!<semaphore 6 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF7_Pos       (7U)

+#define HSEM_C1ISR_ISF7_Msk       (0x1UL << HSEM_C1ISR_ISF7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1ISR_ISF7           HSEM_C1ISR_ISF7_Msk                          /*!<semaphore 7 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF8_Pos       (8U)

+#define HSEM_C1ISR_ISF8_Msk       (0x1UL << HSEM_C1ISR_ISF8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1ISR_ISF8           HSEM_C1ISR_ISF8_Msk                          /*!<semaphore 8 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF9_Pos       (9U)

+#define HSEM_C1ISR_ISF9_Msk       (0x1UL << HSEM_C1ISR_ISF9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1ISR_ISF9           HSEM_C1ISR_ISF9_Msk                          /*!<semaphore 9 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF10_Pos      (10U)

+#define HSEM_C1ISR_ISF10_Msk      (0x1UL << HSEM_C1ISR_ISF10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1ISR_ISF10          HSEM_C1ISR_ISF10_Msk                         /*!<semaphore 10 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF11_Pos      (11U)

+#define HSEM_C1ISR_ISF11_Msk      (0x1UL << HSEM_C1ISR_ISF11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1ISR_ISF11          HSEM_C1ISR_ISF11_Msk                         /*!<semaphore 11 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF12_Pos      (12U)

+#define HSEM_C1ISR_ISF12_Msk      (0x1UL << HSEM_C1ISR_ISF12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1ISR_ISF12          HSEM_C1ISR_ISF12_Msk                         /*!<semaphore 12 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF13_Pos      (13U)

+#define HSEM_C1ISR_ISF13_Msk      (0x1UL << HSEM_C1ISR_ISF13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1ISR_ISF13          HSEM_C1ISR_ISF13_Msk                         /*!<semaphore 13 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF14_Pos      (14U)

+#define HSEM_C1ISR_ISF14_Msk      (0x1UL << HSEM_C1ISR_ISF14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1ISR_ISF14          HSEM_C1ISR_ISF14_Msk                         /*!<semaphore 14 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF15_Pos      (15U)

+#define HSEM_C1ISR_ISF15_Msk      (0x1UL << HSEM_C1ISR_ISF15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1ISR_ISF15          HSEM_C1ISR_ISF15_Msk                         /*!<semaphore 15 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF16_Pos      (16U)

+#define HSEM_C1ISR_ISF16_Msk      (0x1UL << HSEM_C1ISR_ISF16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1ISR_ISF16          HSEM_C1ISR_ISF16_Msk                         /*!<semaphore 16 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF17_Pos      (17U)

+#define HSEM_C1ISR_ISF17_Msk      (0x1UL << HSEM_C1ISR_ISF17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1ISR_ISF17          HSEM_C1ISR_ISF17_Msk                         /*!<semaphore 17 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF18_Pos      (18U)

+#define HSEM_C1ISR_ISF18_Msk      (0x1UL << HSEM_C1ISR_ISF18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1ISR_ISF18          HSEM_C1ISR_ISF18_Msk                         /*!<semaphore 18 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF19_Pos      (19U)

+#define HSEM_C1ISR_ISF19_Msk      (0x1UL << HSEM_C1ISR_ISF19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1ISR_ISF19          HSEM_C1ISR_ISF19_Msk                         /*!<semaphore 19 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF20_Pos      (20U)

+#define HSEM_C1ISR_ISF20_Msk      (0x1UL << HSEM_C1ISR_ISF20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1ISR_ISF20          HSEM_C1ISR_ISF20_Msk                         /*!<semaphore 20 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF21_Pos      (21U)

+#define HSEM_C1ISR_ISF21_Msk      (0x1UL << HSEM_C1ISR_ISF21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1ISR_ISF21          HSEM_C1ISR_ISF21_Msk                         /*!<semaphore 21 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF22_Pos      (22U)

+#define HSEM_C1ISR_ISF22_Msk      (0x1UL << HSEM_C1ISR_ISF22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1ISR_ISF22          HSEM_C1ISR_ISF22_Msk                         /*!<semaphore 22 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF23_Pos      (23U)

+#define HSEM_C1ISR_ISF23_Msk      (0x1UL << HSEM_C1ISR_ISF23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1ISR_ISF23          HSEM_C1ISR_ISF23_Msk                         /*!<semaphore 23 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF24_Pos      (24U)

+#define HSEM_C1ISR_ISF24_Msk      (0x1UL << HSEM_C1ISR_ISF24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1ISR_ISF24          HSEM_C1ISR_ISF24_Msk                         /*!<semaphore 24 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF25_Pos      (25U)

+#define HSEM_C1ISR_ISF25_Msk      (0x1UL << HSEM_C1ISR_ISF25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1ISR_ISF25          HSEM_C1ISR_ISF25_Msk                         /*!<semaphore 25 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF26_Pos      (26U)

+#define HSEM_C1ISR_ISF26_Msk      (0x1UL << HSEM_C1ISR_ISF26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1ISR_ISF26          HSEM_C1ISR_ISF26_Msk                         /*!<semaphore 26 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF27_Pos      (27U)

+#define HSEM_C1ISR_ISF27_Msk      (0x1UL << HSEM_C1ISR_ISF27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1ISR_ISF27          HSEM_C1ISR_ISF27_Msk                         /*!<semaphore 27 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF28_Pos      (28U)

+#define HSEM_C1ISR_ISF28_Msk      (0x1UL << HSEM_C1ISR_ISF28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1ISR_ISF28          HSEM_C1ISR_ISF28_Msk                         /*!<semaphore 28 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF29_Pos      (29U)

+#define HSEM_C1ISR_ISF29_Msk      (0x1UL << HSEM_C1ISR_ISF29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1ISR_ISF29          HSEM_C1ISR_ISF29_Msk                         /*!<semaphore 29 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF30_Pos      (30U)

+#define HSEM_C1ISR_ISF30_Msk      (0x1UL << HSEM_C1ISR_ISF30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1ISR_ISF30          HSEM_C1ISR_ISF30_Msk                         /*!<semaphore 30 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF31_Pos      (31U)

+#define HSEM_C1ISR_ISF31_Msk      (0x1UL << HSEM_C1ISR_ISF31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1ISR_ISF31          HSEM_C1ISR_ISF31_Msk                         /*!<semaphore 31 interrupt 0 status bit. */

+

+/********************  Bit definition for HSEM_C1MISR register  *****************/

+#define HSEM_C1MISR_MISF0_Pos     (0U)

+#define HSEM_C1MISR_MISF0_Msk     (0x1UL << HSEM_C1MISR_MISF0_Pos)             /*!< 0x00000001 */

+#define HSEM_C1MISR_MISF0         HSEM_C1MISR_MISF0_Msk                        /*!<semaphore 0 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF1_Pos     (1U)

+#define HSEM_C1MISR_MISF1_Msk     (0x1UL << HSEM_C1MISR_MISF1_Pos)             /*!< 0x00000002 */

+#define HSEM_C1MISR_MISF1         HSEM_C1MISR_MISF1_Msk                        /*!<semaphore 1 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF2_Pos     (2U)

+#define HSEM_C1MISR_MISF2_Msk     (0x1UL << HSEM_C1MISR_MISF2_Pos)             /*!< 0x00000004 */

+#define HSEM_C1MISR_MISF2         HSEM_C1MISR_MISF2_Msk                        /*!<semaphore 2 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF3_Pos     (3U)

+#define HSEM_C1MISR_MISF3_Msk     (0x1UL << HSEM_C1MISR_MISF3_Pos)             /*!< 0x00000008 */

+#define HSEM_C1MISR_MISF3         HSEM_C1MISR_MISF3_Msk                        /*!<semaphore 3 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF4_Pos     (4U)

+#define HSEM_C1MISR_MISF4_Msk     (0x1UL << HSEM_C1MISR_MISF4_Pos)             /*!< 0x00000010 */

+#define HSEM_C1MISR_MISF4         HSEM_C1MISR_MISF4_Msk                        /*!<semaphore 4 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF5_Pos     (5U)

+#define HSEM_C1MISR_MISF5_Msk     (0x1UL << HSEM_C1MISR_MISF5_Pos)             /*!< 0x00000020 */

+#define HSEM_C1MISR_MISF5         HSEM_C1MISR_MISF5_Msk                        /*!<semaphore 5 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF6_Pos     (6U)

+#define HSEM_C1MISR_MISF6_Msk     (0x1UL << HSEM_C1MISR_MISF6_Pos)             /*!< 0x00000040 */

+#define HSEM_C1MISR_MISF6         HSEM_C1MISR_MISF6_Msk                        /*!<semaphore 6 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF7_Pos     (7U)

+#define HSEM_C1MISR_MISF7_Msk     (0x1UL << HSEM_C1MISR_MISF7_Pos)             /*!< 0x00000080 */

+#define HSEM_C1MISR_MISF7         HSEM_C1MISR_MISF7_Msk                        /*!<semaphore 7 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF8_Pos     (8U)

+#define HSEM_C1MISR_MISF8_Msk     (0x1UL << HSEM_C1MISR_MISF8_Pos)             /*!< 0x00000100 */

+#define HSEM_C1MISR_MISF8         HSEM_C1MISR_MISF8_Msk                        /*!<semaphore 8 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF9_Pos     (9U)

+#define HSEM_C1MISR_MISF9_Msk     (0x1UL << HSEM_C1MISR_MISF9_Pos)             /*!< 0x00000200 */

+#define HSEM_C1MISR_MISF9         HSEM_C1MISR_MISF9_Msk                        /*!<semaphore 9 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF10_Pos    (10U)

+#define HSEM_C1MISR_MISF10_Msk    (0x1UL << HSEM_C1MISR_MISF10_Pos)            /*!< 0x00000400 */

+#define HSEM_C1MISR_MISF10        HSEM_C1MISR_MISF10_Msk                       /*!<semaphore 10 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF11_Pos    (11U)

+#define HSEM_C1MISR_MISF11_Msk    (0x1UL << HSEM_C1MISR_MISF11_Pos)            /*!< 0x00000800 */

+#define HSEM_C1MISR_MISF11        HSEM_C1MISR_MISF11_Msk                       /*!<semaphore 11 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF12_Pos    (12U)

+#define HSEM_C1MISR_MISF12_Msk    (0x1UL << HSEM_C1MISR_MISF12_Pos)            /*!< 0x00001000 */

+#define HSEM_C1MISR_MISF12        HSEM_C1MISR_MISF12_Msk                       /*!<semaphore 12 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF13_Pos    (13U)

+#define HSEM_C1MISR_MISF13_Msk    (0x1UL << HSEM_C1MISR_MISF13_Pos)            /*!< 0x00002000 */

+#define HSEM_C1MISR_MISF13        HSEM_C1MISR_MISF13_Msk                       /*!<semaphore 13 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF14_Pos    (14U)

+#define HSEM_C1MISR_MISF14_Msk    (0x1UL << HSEM_C1MISR_MISF14_Pos)            /*!< 0x00004000 */

+#define HSEM_C1MISR_MISF14        HSEM_C1MISR_MISF14_Msk                       /*!<semaphore 14 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF15_Pos    (15U)

+#define HSEM_C1MISR_MISF15_Msk    (0x1UL << HSEM_C1MISR_MISF15_Pos)            /*!< 0x00008000 */

+#define HSEM_C1MISR_MISF15        HSEM_C1MISR_MISF15_Msk                       /*!<semaphore 15 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF16_Pos    (16U)

+#define HSEM_C1MISR_MISF16_Msk    (0x1UL << HSEM_C1MISR_MISF16_Pos)            /*!< 0x00010000 */

+#define HSEM_C1MISR_MISF16        HSEM_C1MISR_MISF16_Msk                       /*!<semaphore 16 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF17_Pos    (17U)

+#define HSEM_C1MISR_MISF17_Msk    (0x1UL << HSEM_C1MISR_MISF17_Pos)            /*!< 0x00020000 */

+#define HSEM_C1MISR_MISF17        HSEM_C1MISR_MISF17_Msk                       /*!<semaphore 17 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF18_Pos    (18U)

+#define HSEM_C1MISR_MISF18_Msk    (0x1UL << HSEM_C1MISR_MISF18_Pos)            /*!< 0x00040000 */

+#define HSEM_C1MISR_MISF18        HSEM_C1MISR_MISF18_Msk                       /*!<semaphore 18 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF19_Pos    (19U)

+#define HSEM_C1MISR_MISF19_Msk    (0x1UL << HSEM_C1MISR_MISF19_Pos)            /*!< 0x00080000 */

+#define HSEM_C1MISR_MISF19        HSEM_C1MISR_MISF19_Msk                       /*!<semaphore 19 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF20_Pos    (20U)

+#define HSEM_C1MISR_MISF20_Msk    (0x1UL << HSEM_C1MISR_MISF20_Pos)            /*!< 0x00100000 */

+#define HSEM_C1MISR_MISF20        HSEM_C1MISR_MISF20_Msk                       /*!<semaphore 20 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF21_Pos    (21U)

+#define HSEM_C1MISR_MISF21_Msk    (0x1UL << HSEM_C1MISR_MISF21_Pos)            /*!< 0x00200000 */

+#define HSEM_C1MISR_MISF21        HSEM_C1MISR_MISF21_Msk                       /*!<semaphore 21 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF22_Pos    (22U)

+#define HSEM_C1MISR_MISF22_Msk    (0x1UL << HSEM_C1MISR_MISF22_Pos)            /*!< 0x00400000 */

+#define HSEM_C1MISR_MISF22        HSEM_C1MISR_MISF22_Msk                       /*!<semaphore 22 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF23_Pos    (23U)

+#define HSEM_C1MISR_MISF23_Msk    (0x1UL << HSEM_C1MISR_MISF23_Pos)            /*!< 0x00800000 */

+#define HSEM_C1MISR_MISF23        HSEM_C1MISR_MISF23_Msk                       /*!<semaphore 23 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF24_Pos    (24U)

+#define HSEM_C1MISR_MISF24_Msk    (0x1UL << HSEM_C1MISR_MISF24_Pos)            /*!< 0x01000000 */

+#define HSEM_C1MISR_MISF24        HSEM_C1MISR_MISF24_Msk                       /*!<semaphore 24 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF25_Pos    (25U)

+#define HSEM_C1MISR_MISF25_Msk    (0x1UL << HSEM_C1MISR_MISF25_Pos)            /*!< 0x02000000 */

+#define HSEM_C1MISR_MISF25        HSEM_C1MISR_MISF25_Msk                       /*!<semaphore 25 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF26_Pos    (26U)

+#define HSEM_C1MISR_MISF26_Msk    (0x1UL << HSEM_C1MISR_MISF26_Pos)            /*!< 0x04000000 */

+#define HSEM_C1MISR_MISF26        HSEM_C1MISR_MISF26_Msk                       /*!<semaphore 26 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF27_Pos    (27U)

+#define HSEM_C1MISR_MISF27_Msk    (0x1UL << HSEM_C1MISR_MISF27_Pos)            /*!< 0x08000000 */

+#define HSEM_C1MISR_MISF27        HSEM_C1MISR_MISF27_Msk                       /*!<semaphore 27 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF28_Pos    (28U)

+#define HSEM_C1MISR_MISF28_Msk    (0x1UL << HSEM_C1MISR_MISF28_Pos)            /*!< 0x10000000 */

+#define HSEM_C1MISR_MISF28        HSEM_C1MISR_MISF28_Msk                       /*!<semaphore 28 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF29_Pos    (29U)

+#define HSEM_C1MISR_MISF29_Msk    (0x1UL << HSEM_C1MISR_MISF29_Pos)            /*!< 0x20000000 */

+#define HSEM_C1MISR_MISF29        HSEM_C1MISR_MISF29_Msk                       /*!<semaphore 29 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF30_Pos    (30U)

+#define HSEM_C1MISR_MISF30_Msk    (0x1UL << HSEM_C1MISR_MISF30_Pos)            /*!< 0x40000000 */

+#define HSEM_C1MISR_MISF30        HSEM_C1MISR_MISF30_Msk                       /*!<semaphore 30 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF31_Pos    (31U)

+#define HSEM_C1MISR_MISF31_Msk    (0x1UL << HSEM_C1MISR_MISF31_Pos)            /*!< 0x80000000 */

+#define HSEM_C1MISR_MISF31        HSEM_C1MISR_MISF31_Msk                       /*!<semaphore 31 interrupt 0 masked status bit. */

+

+/********************  Bit definition for HSEM_CR register  *****************/

+#define HSEM_CR_COREID_Pos        (8U)

+#define HSEM_CR_COREID_Msk        (0xFFUL << HSEM_CR_COREID_Pos)               /*!< 0x0000FF00 */

+#define HSEM_CR_COREID            HSEM_CR_COREID_Msk                           /*!<CoreID of semaphores to be cleared. */

+#define HSEM_CR_KEY_Pos           (16U)

+#define HSEM_CR_KEY_Msk           (0xFFFFUL << HSEM_CR_KEY_Pos)                /*!< 0xFFFF0000 */

+#define HSEM_CR_KEY               HSEM_CR_KEY_Msk                              /*!<semaphores clear key. */

+

+/********************  Bit definition for HSEM_KEYR register  *****************/

+#define HSEM_KEYR_KEY_Pos         (16U)

+#define HSEM_KEYR_KEY_Msk         (0xFFFFUL << HSEM_KEYR_KEY_Pos)              /*!< 0xFFFF0000 */

+#define HSEM_KEYR_KEY             HSEM_KEYR_KEY_Msk                            /*!<semaphores clear key. */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    HASH                                    */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bits definition for HASH_CR register  ********************/

+#define HASH_CR_INIT_Pos          (2U)

+#define HASH_CR_INIT_Msk          (0x1UL << HASH_CR_INIT_Pos)                  /*!< 0x00000004 */

+#define HASH_CR_INIT              HASH_CR_INIT_Msk

+#define HASH_CR_DMAE_Pos          (3U)

+#define HASH_CR_DMAE_Msk          (0x1UL << HASH_CR_DMAE_Pos)                  /*!< 0x00000008 */

+#define HASH_CR_DMAE              HASH_CR_DMAE_Msk

+#define HASH_CR_DATATYPE_Pos      (4U)

+#define HASH_CR_DATATYPE_Msk      (0x3UL << HASH_CR_DATATYPE_Pos)              /*!< 0x00000030 */

+#define HASH_CR_DATATYPE          HASH_CR_DATATYPE_Msk

+#define HASH_CR_DATATYPE_0        (0x1UL << HASH_CR_DATATYPE_Pos)               /*!< 0x00000010 */

+#define HASH_CR_DATATYPE_1        (0x2UL << HASH_CR_DATATYPE_Pos)               /*!< 0x00000020 */

+#define HASH_CR_MODE_Pos          (6U)

+#define HASH_CR_MODE_Msk          (0x1UL << HASH_CR_MODE_Pos)                  /*!< 0x00000040 */

+#define HASH_CR_MODE              HASH_CR_MODE_Msk

+#define HASH_CR_ALGO_Pos          (7U)

+#define HASH_CR_ALGO_Msk          (0x801UL << HASH_CR_ALGO_Pos)                /*!< 0x00040080 */

+#define HASH_CR_ALGO              HASH_CR_ALGO_Msk

+#define HASH_CR_ALGO_0            (0x001UL << HASH_CR_ALGO_Pos)                 /*!< 0x00000080 */

+#define HASH_CR_ALGO_1            (0x800UL << HASH_CR_ALGO_Pos)                 /*!< 0x00040000 */

+#define HASH_CR_NBW_Pos           (8U)

+#define HASH_CR_NBW_Msk           (0xFUL << HASH_CR_NBW_Pos)                   /*!< 0x00000F00 */

+#define HASH_CR_NBW               HASH_CR_NBW_Msk

+#define HASH_CR_NBW_0             (0x1UL << HASH_CR_NBW_Pos)                    /*!< 0x00000100 */

+#define HASH_CR_NBW_1             (0x2UL << HASH_CR_NBW_Pos)                    /*!< 0x00000200 */

+#define HASH_CR_NBW_2             (0x4UL << HASH_CR_NBW_Pos)                    /*!< 0x00000400 */

+#define HASH_CR_NBW_3             (0x8UL << HASH_CR_NBW_Pos)                    /*!< 0x00000800 */

+#define HASH_CR_DINNE_Pos         (12U)

+#define HASH_CR_DINNE_Msk         (0x1UL << HASH_CR_DINNE_Pos)                 /*!< 0x00001000 */

+#define HASH_CR_DINNE             HASH_CR_DINNE_Msk

+#define HASH_CR_MDMAT_Pos         (13U)

+#define HASH_CR_MDMAT_Msk         (0x1UL << HASH_CR_MDMAT_Pos)                 /*!< 0x00002000 */

+#define HASH_CR_MDMAT             HASH_CR_MDMAT_Msk

+#define HASH_CR_LKEY_Pos          (16U)

+#define HASH_CR_LKEY_Msk          (0x1UL << HASH_CR_LKEY_Pos)                  /*!< 0x00010000 */

+#define HASH_CR_LKEY              HASH_CR_LKEY_Msk

+

+/******************  Bits definition for HASH_STR register  *******************/

+#define HASH_STR_NBLW_Pos         (0U)

+#define HASH_STR_NBLW_Msk         (0x1FUL << HASH_STR_NBLW_Pos)                /*!< 0x0000001F */

+#define HASH_STR_NBLW             HASH_STR_NBLW_Msk

+#define HASH_STR_NBLW_0           (0x01UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000001 */

+#define HASH_STR_NBLW_1           (0x02UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000002 */

+#define HASH_STR_NBLW_2           (0x04UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000004 */

+#define HASH_STR_NBLW_3           (0x08UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000008 */

+#define HASH_STR_NBLW_4           (0x10UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000010 */

+#define HASH_STR_DCAL_Pos         (8U)

+#define HASH_STR_DCAL_Msk         (0x1UL << HASH_STR_DCAL_Pos)                 /*!< 0x00000100 */

+#define HASH_STR_DCAL             HASH_STR_DCAL_Msk

+

+/******************  Bits definition for HASH_IMR register  *******************/

+#define HASH_IMR_DINIE_Pos        (0U)

+#define HASH_IMR_DINIE_Msk        (0x1UL << HASH_IMR_DINIE_Pos)                /*!< 0x00000001 */

+#define HASH_IMR_DINIE            HASH_IMR_DINIE_Msk

+#define HASH_IMR_DCIE_Pos         (1U)

+#define HASH_IMR_DCIE_Msk         (0x1UL << HASH_IMR_DCIE_Pos)                 /*!< 0x00000002 */

+#define HASH_IMR_DCIE             HASH_IMR_DCIE_Msk

+

+/******************  Bits definition for HASH_SR register  ********************/

+#define HASH_SR_DINIS_Pos         (0U)

+#define HASH_SR_DINIS_Msk         (0x1UL << HASH_SR_DINIS_Pos)                 /*!< 0x00000001 */

+#define HASH_SR_DINIS             HASH_SR_DINIS_Msk

+#define HASH_SR_DCIS_Pos          (1U)

+#define HASH_SR_DCIS_Msk          (0x1UL << HASH_SR_DCIS_Pos)                  /*!< 0x00000002 */

+#define HASH_SR_DCIS              HASH_SR_DCIS_Msk

+#define HASH_SR_DMAS_Pos          (2U)

+#define HASH_SR_DMAS_Msk          (0x1UL << HASH_SR_DMAS_Pos)                  /*!< 0x00000004 */

+#define HASH_SR_DMAS              HASH_SR_DMAS_Msk

+#define HASH_SR_BUSY_Pos          (3U)

+#define HASH_SR_BUSY_Msk          (0x1UL << HASH_SR_BUSY_Pos)                  /*!< 0x00000008 */

+#define HASH_SR_BUSY              HASH_SR_BUSY_Msk

+/******************************************************************************/

+/*                                                                            */

+/*                      Inter-integrated Circuit Interface (I2C)              */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for I2C_CR1 register  *******************/

+#define I2C_CR1_PE_Pos               (0U)

+#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */

+#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */

+#define I2C_CR1_TXIE_Pos             (1U)

+#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */

+#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */

+#define I2C_CR1_RXIE_Pos             (2U)

+#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */

+#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */

+#define I2C_CR1_ADDRIE_Pos           (3U)

+#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */

+#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */

+#define I2C_CR1_NACKIE_Pos           (4U)

+#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */

+#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */

+#define I2C_CR1_STOPIE_Pos           (5U)

+#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */

+#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */

+#define I2C_CR1_TCIE_Pos             (6U)

+#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */

+#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */

+#define I2C_CR1_ERRIE_Pos            (7U)

+#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */

+#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */

+#define I2C_CR1_DNF_Pos              (8U)

+#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */

+#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */

+#define I2C_CR1_ANFOFF_Pos           (12U)

+#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */

+#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */

+#define I2C_CR1_TXDMAEN_Pos          (14U)

+#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */

+#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */

+#define I2C_CR1_RXDMAEN_Pos          (15U)

+#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */

+#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */

+#define I2C_CR1_SBC_Pos              (16U)

+#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */

+#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */

+#define I2C_CR1_NOSTRETCH_Pos        (17U)

+#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */

+#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */

+#define I2C_CR1_WUPEN_Pos            (18U)

+#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */

+#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */

+#define I2C_CR1_GCEN_Pos             (19U)

+#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */

+#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */

+#define I2C_CR1_SMBHEN_Pos           (20U)

+#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */

+#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */

+#define I2C_CR1_SMBDEN_Pos           (21U)

+#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */

+#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */

+#define I2C_CR1_ALERTEN_Pos          (22U)

+#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */

+#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */

+#define I2C_CR1_PECEN_Pos            (23U)

+#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */

+#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */

+

+/******************  Bit definition for I2C_CR2 register  ********************/

+#define I2C_CR2_SADD_Pos             (0U)

+#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */

+#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */

+#define I2C_CR2_RD_WRN_Pos           (10U)

+#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */

+#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */

+#define I2C_CR2_ADD10_Pos            (11U)

+#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */

+#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */

+#define I2C_CR2_HEAD10R_Pos          (12U)

+#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */

+#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */

+#define I2C_CR2_START_Pos            (13U)

+#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */

+#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */

+#define I2C_CR2_STOP_Pos             (14U)

+#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */

+#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */

+#define I2C_CR2_NACK_Pos             (15U)

+#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */

+#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */

+#define I2C_CR2_NBYTES_Pos           (16U)

+#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */

+#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */

+#define I2C_CR2_RELOAD_Pos           (24U)

+#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */

+#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */

+#define I2C_CR2_AUTOEND_Pos          (25U)

+#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */

+#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */

+#define I2C_CR2_PECBYTE_Pos          (26U)

+#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */

+#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */

+

+/*******************  Bit definition for I2C_OAR1 register  ******************/

+#define I2C_OAR1_OA1_Pos             (0U)

+#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */

+#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */

+#define I2C_OAR1_OA1MODE_Pos         (10U)

+#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */

+#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */

+#define I2C_OAR1_OA1EN_Pos           (15U)

+#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */

+#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */

+

+/*******************  Bit definition for I2C_OAR2 register  ******************/

+#define I2C_OAR2_OA2_Pos             (1U)

+#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */

+#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */

+#define I2C_OAR2_OA2MSK_Pos          (8U)

+#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */

+#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */

+#define I2C_OAR2_OA2NOMASK           0x00000000UL                              /*!< No mask */

+#define I2C_OAR2_OA2MASK01_Pos       (8U)

+#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */

+#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared */

+#define I2C_OAR2_OA2MASK02_Pos       (9U)

+#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */

+#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */

+#define I2C_OAR2_OA2MASK03_Pos       (8U)

+#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */

+#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */

+#define I2C_OAR2_OA2MASK04_Pos       (10U)

+#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */

+#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */

+#define I2C_OAR2_OA2MASK05_Pos       (8U)

+#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */

+#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */

+#define I2C_OAR2_OA2MASK06_Pos       (9U)

+#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */

+#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared */

+#define I2C_OAR2_OA2MASK07_Pos       (8U)

+#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */

+#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done */

+#define I2C_OAR2_OA2EN_Pos           (15U)

+#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */

+#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */

+

+/*******************  Bit definition for I2C_TIMINGR register *******************/

+#define I2C_TIMINGR_SCLL_Pos         (0U)

+#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */

+#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */

+#define I2C_TIMINGR_SCLH_Pos         (8U)

+#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */

+#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */

+#define I2C_TIMINGR_SDADEL_Pos       (16U)

+#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */

+#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */

+#define I2C_TIMINGR_SCLDEL_Pos       (20U)

+#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */

+#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */

+#define I2C_TIMINGR_PRESC_Pos        (28U)

+#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */

+#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */

+

+/******************* Bit definition for I2C_TIMEOUTR register *******************/

+#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)

+#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */

+#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */

+#define I2C_TIMEOUTR_TIDLE_Pos       (12U)

+#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */

+#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */

+#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)

+#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */

+#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */

+#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)

+#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */

+#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/

+#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)

+#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */

+#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */

+

+/******************  Bit definition for I2C_ISR register  *********************/

+#define I2C_ISR_TXE_Pos              (0U)

+#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */

+#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */

+#define I2C_ISR_TXIS_Pos             (1U)

+#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */

+#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */

+#define I2C_ISR_RXNE_Pos             (2U)

+#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */

+#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */

+#define I2C_ISR_ADDR_Pos             (3U)

+#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */

+#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/

+#define I2C_ISR_NACKF_Pos            (4U)

+#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */

+#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */

+#define I2C_ISR_STOPF_Pos            (5U)

+#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */

+#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */

+#define I2C_ISR_TC_Pos               (6U)

+#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */

+#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */

+#define I2C_ISR_TCR_Pos              (7U)

+#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */

+#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */

+#define I2C_ISR_BERR_Pos             (8U)

+#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */

+#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */

+#define I2C_ISR_ARLO_Pos             (9U)

+#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */

+#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */

+#define I2C_ISR_OVR_Pos              (10U)

+#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */

+#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */

+#define I2C_ISR_PECERR_Pos           (11U)

+#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */

+#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */

+#define I2C_ISR_TIMEOUT_Pos          (12U)

+#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */

+#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */

+#define I2C_ISR_ALERT_Pos            (13U)

+#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */

+#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */

+#define I2C_ISR_BUSY_Pos             (15U)

+#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */

+#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */

+#define I2C_ISR_DIR_Pos              (16U)

+#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */

+#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */

+#define I2C_ISR_ADDCODE_Pos          (17U)

+#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */

+#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */

+

+/******************  Bit definition for I2C_ICR register  *********************/

+#define I2C_ICR_ADDRCF_Pos           (3U)

+#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */

+#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */

+#define I2C_ICR_NACKCF_Pos           (4U)

+#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */

+#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */

+#define I2C_ICR_STOPCF_Pos           (5U)

+#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */

+#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */

+#define I2C_ICR_BERRCF_Pos           (8U)

+#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */

+#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */

+#define I2C_ICR_ARLOCF_Pos           (9U)

+#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */

+#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */

+#define I2C_ICR_OVRCF_Pos            (10U)

+#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */

+#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */

+#define I2C_ICR_PECCF_Pos            (11U)

+#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */

+#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */

+#define I2C_ICR_TIMOUTCF_Pos         (12U)

+#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */

+#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */

+#define I2C_ICR_ALERTCF_Pos          (13U)

+#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */

+#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */

+

+/******************  Bit definition for I2C_PECR register  *********************/

+#define I2C_PECR_PEC_Pos             (0U)

+#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */

+#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */

+

+/******************  Bit definition for I2C_RXDR register  *********************/

+#define I2C_RXDR_RXDATA_Pos          (0U)

+#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */

+#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */

+

+/******************  Bit definition for I2C_TXDR register  *********************/

+#define I2C_TXDR_TXDATA_Pos          (0U)

+#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */

+#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           Independent WATCHDOG                             */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for IWDG_KR register  ********************/

+#define IWDG_KR_KEY_Pos      (0U)

+#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */

+#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */

+

+/*******************  Bit definition for IWDG_PR register  ********************/

+#define IWDG_PR_PR_Pos       (0U)

+#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */

+#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */

+#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */

+#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */

+#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */

+

+/*******************  Bit definition for IWDG_RLR register  *******************/

+#define IWDG_RLR_RL_Pos      (0U)

+#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */

+#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */

+

+/*******************  Bit definition for IWDG_SR register  ********************/

+#define IWDG_SR_PVU_Pos      (0U)

+#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */

+#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */

+#define IWDG_SR_RVU_Pos      (1U)

+#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */

+#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */

+#define IWDG_SR_WVU_Pos      (2U)

+#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */

+#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */

+

+/*******************  Bit definition for IWDG_KR register  ********************/

+#define IWDG_WINR_WIN_Pos    (0U)

+#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */

+#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */

+

+/******************************************************************************/

+/*                                                                            */

+/*                        JPEG Encoder/Decoder                                */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for CONFR0 register  ********************/

+#define JPEG_CONFR0_START_Pos           (0U)

+#define JPEG_CONFR0_START_Msk           (0x1UL << JPEG_CONFR0_START_Pos)       /*!< 0x00000001 */

+#define JPEG_CONFR0_START               JPEG_CONFR0_START_Msk                  /*!<Start/Stop bit */

+

+/********************  Bit definition for CONFR1 register  ********************/

+#define JPEG_CONFR1_NF_Pos              (0U)

+#define JPEG_CONFR1_NF_Msk              (0x3UL << JPEG_CONFR1_NF_Pos)          /*!< 0x00000003 */

+#define JPEG_CONFR1_NF                  JPEG_CONFR1_NF_Msk                     /*!<Number of color components */

+#define JPEG_CONFR1_NF_0                (0x1UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000001 */

+#define JPEG_CONFR1_NF_1                (0x2UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000002 */

+#define JPEG_CONFR1_DE_Pos              (3U)

+#define JPEG_CONFR1_DE_Msk              (0x1UL << JPEG_CONFR1_DE_Pos)          /*!< 0x00000008 */

+#define JPEG_CONFR1_DE                  JPEG_CONFR1_DE_Msk                     /*!<Decoding Enable */

+#define JPEG_CONFR1_COLORSPACE_Pos      (4U)

+#define JPEG_CONFR1_COLORSPACE_Msk      (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)  /*!< 0x00000030 */

+#define JPEG_CONFR1_COLORSPACE          JPEG_CONFR1_COLORSPACE_Msk             /*!<Color Space */

+#define JPEG_CONFR1_COLORSPACE_0        (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000010 */

+#define JPEG_CONFR1_COLORSPACE_1        (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000020 */

+#define JPEG_CONFR1_NS_Pos              (6U)

+#define JPEG_CONFR1_NS_Msk              (0x3UL << JPEG_CONFR1_NS_Pos)          /*!< 0x000000C0 */

+#define JPEG_CONFR1_NS                  JPEG_CONFR1_NS_Msk                     /*!<Number of components for Scan */

+#define JPEG_CONFR1_NS_0                (0x1UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR1_NS_1                (0x2UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR1_HDR_Pos             (8U)

+#define JPEG_CONFR1_HDR_Msk             (0x1UL << JPEG_CONFR1_HDR_Pos)         /*!< 0x00000100 */

+#define JPEG_CONFR1_HDR                 JPEG_CONFR1_HDR_Msk                    /*!<Header Processing On/Off */

+#define JPEG_CONFR1_YSIZE_Pos           (16U)

+#define JPEG_CONFR1_YSIZE_Msk           (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)    /*!< 0xFFFF0000 */

+#define JPEG_CONFR1_YSIZE               JPEG_CONFR1_YSIZE_Msk                  /*!<Number of lines in source image */

+

+/********************  Bit definition for CONFR2 register  ********************/

+#define JPEG_CONFR2_NMCU_Pos            (0U)

+#define JPEG_CONFR2_NMCU_Msk            (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)  /*!< 0x03FFFFFF */

+#define JPEG_CONFR2_NMCU                JPEG_CONFR2_NMCU_Msk                   /*!<Number of MCU units minus 1 to encode */

+

+/********************  Bit definition for CONFR3 register  ********************/

+#define JPEG_CONFR3_XSIZE_Pos           (16U)

+#define JPEG_CONFR3_XSIZE_Msk           (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)    /*!< 0xFFFF0000 */

+#define JPEG_CONFR3_XSIZE               JPEG_CONFR3_XSIZE_Msk                  /*!<Number of pixels per line */

+

+/********************  Bit definition for CONFR4 register  ********************/

+#define JPEG_CONFR4_HD_Pos              (0U)

+#define JPEG_CONFR4_HD_Msk              (0x1UL << JPEG_CONFR4_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR4_HD                  JPEG_CONFR4_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR4_HA_Pos              (1U)

+#define JPEG_CONFR4_HA_Msk              (0x1UL << JPEG_CONFR4_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR4_HA                  JPEG_CONFR4_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR4_QT_Pos              (2U)

+#define JPEG_CONFR4_QT_Msk              (0x3UL << JPEG_CONFR4_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR4_QT                  JPEG_CONFR4_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR4_QT_0                (0x1UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR4_QT_1                (0x2UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR4_NB_Pos              (4U)

+#define JPEG_CONFR4_NB_Msk              (0xFUL << JPEG_CONFR4_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR4_NB                  JPEG_CONFR4_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR4_NB_0                (0x1UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR4_NB_1                (0x2UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR4_NB_2                (0x4UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR4_NB_3                (0x8UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR4_VSF_Pos             (8U)

+#define JPEG_CONFR4_VSF_Msk             (0xFUL << JPEG_CONFR4_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR4_VSF                 JPEG_CONFR4_VSF_Msk                    /*!<Vertical sampling factor for component 1 */

+#define JPEG_CONFR4_VSF_0               (0x1UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR4_VSF_1               (0x2UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR4_VSF_2               (0x4UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR4_VSF_3               (0x8UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR4_HSF_Pos             (12U)

+#define JPEG_CONFR4_HSF_Msk             (0xFUL << JPEG_CONFR4_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR4_HSF                 JPEG_CONFR4_HSF_Msk                    /*!<Horizontal sampling factor for component 1 */

+#define JPEG_CONFR4_HSF_0               (0x1UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR4_HSF_1               (0x2UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR4_HSF_2               (0x4UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR4_HSF_3               (0x8UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR5 register  ********************/

+#define JPEG_CONFR5_HD_Pos              (0U)

+#define JPEG_CONFR5_HD_Msk              (0x1UL << JPEG_CONFR5_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR5_HD                  JPEG_CONFR5_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR5_HA_Pos              (1U)

+#define JPEG_CONFR5_HA_Msk              (0x1UL << JPEG_CONFR5_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR5_HA                  JPEG_CONFR5_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR5_QT_Pos              (2U)

+#define JPEG_CONFR5_QT_Msk              (0x3UL << JPEG_CONFR5_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR5_QT                  JPEG_CONFR5_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR5_QT_0                (0x1UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR5_QT_1                (0x2UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR5_NB_Pos              (4U)

+#define JPEG_CONFR5_NB_Msk              (0xFUL << JPEG_CONFR5_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR5_NB                  JPEG_CONFR5_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR5_NB_0                (0x1UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR5_NB_1                (0x2UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR5_NB_2                (0x4UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR5_NB_3                (0x8UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR5_VSF_Pos             (8U)

+#define JPEG_CONFR5_VSF_Msk             (0xFUL << JPEG_CONFR5_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR5_VSF                 JPEG_CONFR5_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR5_VSF_0               (0x1UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR5_VSF_1               (0x2UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR5_VSF_2               (0x4UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR5_VSF_3               (0x8UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR5_HSF_Pos             (12U)

+#define JPEG_CONFR5_HSF_Msk             (0xFUL << JPEG_CONFR5_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR5_HSF                 JPEG_CONFR5_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR5_HSF_0               (0x1UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR5_HSF_1               (0x2UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR5_HSF_2               (0x4UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR5_HSF_3               (0x8UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR6 register  ********************/

+#define JPEG_CONFR6_HD_Pos              (0U)

+#define JPEG_CONFR6_HD_Msk              (0x1UL << JPEG_CONFR6_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR6_HD                  JPEG_CONFR6_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR6_HA_Pos              (1U)

+#define JPEG_CONFR6_HA_Msk              (0x1UL << JPEG_CONFR6_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR6_HA                  JPEG_CONFR6_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR6_QT_Pos              (2U)

+#define JPEG_CONFR6_QT_Msk              (0x3UL << JPEG_CONFR6_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR6_QT                  JPEG_CONFR6_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR6_QT_0                (0x1UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR6_QT_1                (0x2UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR6_NB_Pos              (4U)

+#define JPEG_CONFR6_NB_Msk              (0xFUL << JPEG_CONFR6_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR6_NB                  JPEG_CONFR6_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR6_NB_0                (0x1UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR6_NB_1                (0x2UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR6_NB_2                (0x4UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR6_NB_3                (0x8UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR6_VSF_Pos             (8U)

+#define JPEG_CONFR6_VSF_Msk             (0xFUL << JPEG_CONFR6_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR6_VSF                 JPEG_CONFR6_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR6_VSF_0               (0x1UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR6_VSF_1               (0x2UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR6_VSF_2               (0x4UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR6_VSF_3               (0x8UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR6_HSF_Pos             (12U)

+#define JPEG_CONFR6_HSF_Msk             (0xFUL << JPEG_CONFR6_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR6_HSF                 JPEG_CONFR6_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR6_HSF_0               (0x1UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR6_HSF_1               (0x2UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR6_HSF_2               (0x4UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR6_HSF_3               (0x8UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR7 register  ********************/

+#define JPEG_CONFR7_HD_Pos              (0U)

+#define JPEG_CONFR7_HD_Msk              (0x1UL << JPEG_CONFR7_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR7_HD                  JPEG_CONFR7_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR7_HA_Pos              (1U)

+#define JPEG_CONFR7_HA_Msk              (0x1UL << JPEG_CONFR7_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR7_HA                  JPEG_CONFR7_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR7_QT_Pos              (2U)

+#define JPEG_CONFR7_QT_Msk              (0x3UL << JPEG_CONFR7_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR7_QT                  JPEG_CONFR7_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR7_QT_0                (0x1UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR7_QT_1                (0x2UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR7_NB_Pos              (4U)

+#define JPEG_CONFR7_NB_Msk              (0xFUL << JPEG_CONFR7_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR7_NB                  JPEG_CONFR7_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR7_NB_0                (0x1UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR7_NB_1                (0x2UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR7_NB_2                (0x4UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR7_NB_3                (0x8UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR7_VSF_Pos             (8U)

+#define JPEG_CONFR7_VSF_Msk             (0xFUL << JPEG_CONFR7_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR7_VSF                 JPEG_CONFR7_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR7_VSF_0               (0x1UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR7_VSF_1               (0x2UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR7_VSF_2               (0x4UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR7_VSF_3               (0x8UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR7_HSF_Pos             (12U)

+#define JPEG_CONFR7_HSF_Msk             (0xFUL << JPEG_CONFR7_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR7_HSF                 JPEG_CONFR7_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR7_HSF_0               (0x1UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR7_HSF_1               (0x2UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR7_HSF_2               (0x4UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR7_HSF_3               (0x8UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CR register  ********************/

+#define JPEG_CR_JCEN_Pos                (0U)

+#define JPEG_CR_JCEN_Msk                (0x1UL << JPEG_CR_JCEN_Pos)            /*!< 0x00000001 */

+#define JPEG_CR_JCEN                    JPEG_CR_JCEN_Msk                       /*!<Enable the JPEG Codec Core */

+#define JPEG_CR_IFTIE_Pos               (1U)

+#define JPEG_CR_IFTIE_Msk               (0x1UL << JPEG_CR_IFTIE_Pos)           /*!< 0x00000002 */

+#define JPEG_CR_IFTIE                   JPEG_CR_IFTIE_Msk                      /*!<Input FIFO Threshold Interrupt Enable */

+#define JPEG_CR_IFNFIE_Pos              (2U)

+#define JPEG_CR_IFNFIE_Msk              (0x1UL << JPEG_CR_IFNFIE_Pos)          /*!< 0x00000004 */

+#define JPEG_CR_IFNFIE                  JPEG_CR_IFNFIE_Msk                     /*!<Input FIFO Not Full Interrupt Enable */

+#define JPEG_CR_OFTIE_Pos               (3U)

+#define JPEG_CR_OFTIE_Msk               (0x1UL << JPEG_CR_OFTIE_Pos)           /*!< 0x00000008 */

+#define JPEG_CR_OFTIE                   JPEG_CR_OFTIE_Msk                      /*!<Output FIFO Threshold Interrupt Enable */

+#define JPEG_CR_OFNEIE_Pos              (4U)

+#define JPEG_CR_OFNEIE_Msk              (0x1UL << JPEG_CR_OFNEIE_Pos)          /*!< 0x00000010 */

+#define JPEG_CR_OFNEIE                  JPEG_CR_OFNEIE_Msk                     /*!<Output FIFO Not Empty Interrupt Enable */

+#define JPEG_CR_EOCIE_Pos               (5U)

+#define JPEG_CR_EOCIE_Msk               (0x1UL << JPEG_CR_EOCIE_Pos)           /*!< 0x00000020 */

+#define JPEG_CR_EOCIE                   JPEG_CR_EOCIE_Msk                      /*!<End of Conversion Interrupt Enable */

+#define JPEG_CR_HPDIE_Pos               (6U)

+#define JPEG_CR_HPDIE_Msk               (0x1UL << JPEG_CR_HPDIE_Pos)           /*!< 0x00000040 */

+#define JPEG_CR_HPDIE                   JPEG_CR_HPDIE_Msk                      /*!<Header Parsing Done Interrupt Enable */

+#define JPEG_CR_IFF_Pos                 (13U)

+#define JPEG_CR_IFF_Msk                 (0x1UL << JPEG_CR_IFF_Pos)             /*!< 0x00002000 */

+#define JPEG_CR_IFF                     JPEG_CR_IFF_Msk                        /*!<Flush the input FIFO */

+#define JPEG_CR_OFF_Pos                 (14U)

+#define JPEG_CR_OFF_Msk                 (0x1UL << JPEG_CR_OFF_Pos)             /*!< 0x00004000 */

+#define JPEG_CR_OFF                     JPEG_CR_OFF_Msk                        /*!<Flush the output FIFO */

+

+/********************  Bit definition for SR register  ********************/

+#define JPEG_SR_IFTF_Pos                (1U)

+#define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */

+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is bellow its threshold flag */

+#define JPEG_SR_IFNFF_Pos               (2U)

+#define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */

+#define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */

+#define JPEG_SR_OFTF_Pos                (3U)

+#define JPEG_SR_OFTF_Msk                (0x1UL << JPEG_SR_OFTF_Pos)            /*!< 0x00000008 */

+#define JPEG_SR_OFTF                    JPEG_SR_OFTF_Msk                       /*!<Output FIFO is not empty and has reach its threshold */

+#define JPEG_SR_OFNEF_Pos               (4U)

+#define JPEG_SR_OFNEF_Msk               (0x1UL << JPEG_SR_OFNEF_Pos)           /*!< 0x00000010 */

+#define JPEG_SR_OFNEF                   JPEG_SR_OFNEF_Msk                      /*!<Output FIFO is not empty, a data is available */

+#define JPEG_SR_EOCF_Pos                (5U)

+#define JPEG_SR_EOCF_Msk                (0x1UL << JPEG_SR_EOCF_Pos)            /*!< 0x00000020 */

+#define JPEG_SR_EOCF                    JPEG_SR_EOCF_Msk                       /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */

+#define JPEG_SR_HPDF_Pos                (6U)

+#define JPEG_SR_HPDF_Msk                (0x1UL << JPEG_SR_HPDF_Pos)            /*!< 0x00000040 */

+#define JPEG_SR_HPDF                    JPEG_SR_HPDF_Msk                       /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */

+#define JPEG_SR_COF_Pos                 (7U)

+#define JPEG_SR_COF_Msk                 (0x1UL << JPEG_SR_COF_Pos)             /*!< 0x00000080 */

+#define JPEG_SR_COF                     JPEG_SR_COF_Msk                        /*!<JPEG Codec operation on going flag */

+

+/********************  Bit definition for CFR register  ********************/

+#define JPEG_CFR_CEOCF_Pos              (4U)

+#define JPEG_CFR_CEOCF_Msk              (0x1UL << JPEG_CFR_CEOCF_Pos)          /*!< 0x00000010 */

+#define JPEG_CFR_CEOCF                  JPEG_CFR_CEOCF_Msk                     /*!<Clear End of Conversion Flag */

+#define JPEG_CFR_CHPDF_Pos              (5U)

+#define JPEG_CFR_CHPDF_Msk              (0x1UL << JPEG_CFR_CHPDF_Pos)          /*!< 0x00000020 */

+#define JPEG_CFR_CHPDF                  JPEG_CFR_CHPDF_Msk                     /*!<Clear Header Parsing Done Flag */

+

+/********************  Bit definition for DIR register  ********************/

+#define JPEG_DIR_DATAIN_Pos             (0U)

+#define JPEG_DIR_DATAIN_Msk             (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)  /*!< 0xFFFFFFFF */

+#define JPEG_DIR_DATAIN                 JPEG_DIR_DATAIN_Msk                    /*!<Data Input FIFO */

+

+/********************  Bit definition for DOR register  ********************/

+#define JPEG_DOR_DATAOUT_Pos            (0U)

+#define JPEG_DOR_DATAOUT_Msk            (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */

+#define JPEG_DOR_DATAOUT                JPEG_DOR_DATAOUT_Msk                   /*!<Data Output FIFO */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      LCD-TFT Display Controller (LTDC)                     */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for LTDC_SSCR register  *****************/

+

+#define LTDC_SSCR_VSH_Pos            (0U)

+#define LTDC_SSCR_VSH_Msk            (0x7FFUL << LTDC_SSCR_VSH_Pos)            /*!< 0x000007FF */

+#define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height  */

+#define LTDC_SSCR_HSW_Pos            (16U)

+#define LTDC_SSCR_HSW_Msk            (0xFFFUL << LTDC_SSCR_HSW_Pos)            /*!< 0x0FFF0000 */

+#define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */

+

+/********************  Bit definition for LTDC_BPCR register  *****************/

+

+#define LTDC_BPCR_AVBP_Pos           (0U)

+#define LTDC_BPCR_AVBP_Msk           (0x7FFUL << LTDC_BPCR_AVBP_Pos)           /*!< 0x000007FF */

+#define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch   */

+#define LTDC_BPCR_AHBP_Pos           (16U)

+#define LTDC_BPCR_AHBP_Msk           (0xFFFUL << LTDC_BPCR_AHBP_Pos)           /*!< 0x0FFF0000 */

+#define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */

+

+/********************  Bit definition for LTDC_AWCR register  *****************/

+

+#define LTDC_AWCR_AAH_Pos            (0U)

+#define LTDC_AWCR_AAH_Msk            (0x7FFUL << LTDC_AWCR_AAH_Pos)            /*!< 0x000007FF */

+#define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active heigh */

+#define LTDC_AWCR_AAW_Pos            (16U)

+#define LTDC_AWCR_AAW_Msk            (0xFFFUL << LTDC_AWCR_AAW_Pos)            /*!< 0x0FFF0000 */

+#define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */

+

+/********************  Bit definition for LTDC_TWCR register  *****************/

+

+#define LTDC_TWCR_TOTALH_Pos         (0U)

+#define LTDC_TWCR_TOTALH_Msk         (0x7FFUL << LTDC_TWCR_TOTALH_Pos)         /*!< 0x000007FF */

+#define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total Heigh */

+#define LTDC_TWCR_TOTALW_Pos         (16U)

+#define LTDC_TWCR_TOTALW_Msk         (0xFFFUL << LTDC_TWCR_TOTALW_Pos)         /*!< 0x0FFF0000 */

+#define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */

+

+/********************  Bit definition for LTDC_GCR register  ******************/

+

+#define LTDC_GCR_LTDCEN_Pos          (0U)

+#define LTDC_GCR_LTDCEN_Msk          (0x1UL << LTDC_GCR_LTDCEN_Pos)            /*!< 0x00000001 */

+#define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit       */

+#define LTDC_GCR_DBW_Pos             (4U)

+#define LTDC_GCR_DBW_Msk             (0x7UL << LTDC_GCR_DBW_Pos)               /*!< 0x00000070 */

+#define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width                   */

+#define LTDC_GCR_DGW_Pos             (8U)

+#define LTDC_GCR_DGW_Msk             (0x7UL << LTDC_GCR_DGW_Pos)               /*!< 0x00000700 */

+#define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width                  */

+#define LTDC_GCR_DRW_Pos             (12U)

+#define LTDC_GCR_DRW_Msk             (0x7UL << LTDC_GCR_DRW_Pos)               /*!< 0x00007000 */

+#define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width                    */

+#define LTDC_GCR_DEN_Pos             (16U)

+#define LTDC_GCR_DEN_Msk             (0x1UL << LTDC_GCR_DEN_Pos)               /*!< 0x00010000 */

+#define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable                       */

+#define LTDC_GCR_PCPOL_Pos           (28U)

+#define LTDC_GCR_PCPOL_Msk           (0x1UL << LTDC_GCR_PCPOL_Pos)             /*!< 0x10000000 */

+#define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity                */

+#define LTDC_GCR_DEPOL_Pos           (29U)

+#define LTDC_GCR_DEPOL_Msk           (0x1UL << LTDC_GCR_DEPOL_Pos)             /*!< 0x20000000 */

+#define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity                */

+#define LTDC_GCR_VSPOL_Pos           (30U)

+#define LTDC_GCR_VSPOL_Msk           (0x1UL << LTDC_GCR_VSPOL_Pos)             /*!< 0x40000000 */

+#define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity   */

+#define LTDC_GCR_HSPOL_Pos           (31U)

+#define LTDC_GCR_HSPOL_Msk           (0x1UL << LTDC_GCR_HSPOL_Pos)             /*!< 0x80000000 */

+#define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */

+

+

+/********************  Bit definition for LTDC_SRCR register  *****************/

+

+#define LTDC_SRCR_IMR_Pos            (0U)

+#define LTDC_SRCR_IMR_Msk            (0x1UL << LTDC_SRCR_IMR_Pos)              /*!< 0x00000001 */

+#define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload         */

+#define LTDC_SRCR_VBR_Pos            (1U)

+#define LTDC_SRCR_VBR_Msk            (0x1UL << LTDC_SRCR_VBR_Pos)              /*!< 0x00000002 */

+#define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */

+

+/********************  Bit definition for LTDC_BCCR register  *****************/

+

+#define LTDC_BCCR_BCBLUE_Pos         (0U)

+#define LTDC_BCCR_BCBLUE_Msk         (0xFFUL << LTDC_BCCR_BCBLUE_Pos)          /*!< 0x000000FF */

+#define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value  */

+#define LTDC_BCCR_BCGREEN_Pos        (8U)

+#define LTDC_BCCR_BCGREEN_Msk        (0xFFUL << LTDC_BCCR_BCGREEN_Pos)         /*!< 0x0000FF00 */

+#define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */

+#define LTDC_BCCR_BCRED_Pos          (16U)

+#define LTDC_BCCR_BCRED_Msk          (0xFFUL << LTDC_BCCR_BCRED_Pos)           /*!< 0x00FF0000 */

+#define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value   */

+

+/********************  Bit definition for LTDC_IER register  ******************/

+

+#define LTDC_IER_LIE_Pos             (0U)

+#define LTDC_IER_LIE_Msk             (0x1UL << LTDC_IER_LIE_Pos)               /*!< 0x00000001 */

+#define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable            */

+#define LTDC_IER_FUIE_Pos            (1U)

+#define LTDC_IER_FUIE_Msk            (0x1UL << LTDC_IER_FUIE_Pos)              /*!< 0x00000002 */

+#define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable   */

+#define LTDC_IER_TERRIE_Pos          (2U)

+#define LTDC_IER_TERRIE_Msk          (0x1UL << LTDC_IER_TERRIE_Pos)            /*!< 0x00000004 */

+#define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable  */

+#define LTDC_IER_RRIE_Pos            (3U)

+#define LTDC_IER_RRIE_Msk            (0x1UL << LTDC_IER_RRIE_Pos)              /*!< 0x00000008 */

+#define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */

+

+/********************  Bit definition for LTDC_ISR register  ******************/

+

+#define LTDC_ISR_LIF_Pos             (0U)

+#define LTDC_ISR_LIF_Msk             (0x1UL << LTDC_ISR_LIF_Pos)               /*!< 0x00000001 */

+#define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */

+#define LTDC_ISR_FUIF_Pos            (1U)

+#define LTDC_ISR_FUIF_Msk            (0x1UL << LTDC_ISR_FUIF_Pos)              /*!< 0x00000002 */

+#define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */

+#define LTDC_ISR_TERRIF_Pos          (2U)

+#define LTDC_ISR_TERRIF_Msk          (0x1UL << LTDC_ISR_TERRIF_Pos)            /*!< 0x00000004 */

+#define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */

+#define LTDC_ISR_RRIF_Pos            (3U)

+#define LTDC_ISR_RRIF_Msk            (0x1UL << LTDC_ISR_RRIF_Pos)              /*!< 0x00000008 */

+#define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */

+

+/********************  Bit definition for LTDC_ICR register  ******************/

+

+#define LTDC_ICR_CLIF_Pos            (0U)

+#define LTDC_ICR_CLIF_Msk            (0x1UL << LTDC_ICR_CLIF_Pos)              /*!< 0x00000001 */

+#define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */

+#define LTDC_ICR_CFUIF_Pos           (1U)

+#define LTDC_ICR_CFUIF_Msk           (0x1UL << LTDC_ICR_CFUIF_Pos)             /*!< 0x00000002 */

+#define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */

+#define LTDC_ICR_CTERRIF_Pos         (2U)

+#define LTDC_ICR_CTERRIF_Msk         (0x1UL << LTDC_ICR_CTERRIF_Pos)           /*!< 0x00000004 */

+#define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */

+#define LTDC_ICR_CRRIF_Pos           (3U)

+#define LTDC_ICR_CRRIF_Msk           (0x1UL << LTDC_ICR_CRRIF_Pos)             /*!< 0x00000008 */

+#define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */

+

+/********************  Bit definition for LTDC_LIPCR register  ****************/

+

+#define LTDC_LIPCR_LIPOS_Pos         (0U)

+#define LTDC_LIPCR_LIPOS_Msk         (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)         /*!< 0x000007FF */

+#define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */

+

+/********************  Bit definition for LTDC_CPSR register  *****************/

+

+#define LTDC_CPSR_CYPOS_Pos          (0U)

+#define LTDC_CPSR_CYPOS_Msk          (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)         /*!< 0x0000FFFF */

+#define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */

+#define LTDC_CPSR_CXPOS_Pos          (16U)

+#define LTDC_CPSR_CXPOS_Msk          (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)         /*!< 0xFFFF0000 */

+#define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */

+

+/********************  Bit definition for LTDC_CDSR register  *****************/

+

+#define LTDC_CDSR_VDES_Pos           (0U)

+#define LTDC_CDSR_VDES_Msk           (0x1UL << LTDC_CDSR_VDES_Pos)             /*!< 0x00000001 */

+#define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status       */

+#define LTDC_CDSR_HDES_Pos           (1U)

+#define LTDC_CDSR_HDES_Msk           (0x1UL << LTDC_CDSR_HDES_Pos)             /*!< 0x00000002 */

+#define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status     */

+#define LTDC_CDSR_VSYNCS_Pos         (2U)

+#define LTDC_CDSR_VSYNCS_Msk         (0x1UL << LTDC_CDSR_VSYNCS_Pos)           /*!< 0x00000004 */

+#define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status   */

+#define LTDC_CDSR_HSYNCS_Pos         (3U)

+#define LTDC_CDSR_HSYNCS_Msk         (0x1UL << LTDC_CDSR_HSYNCS_Pos)           /*!< 0x00000008 */

+#define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */

+

+/********************  Bit definition for LTDC_LxCR register  *****************/

+

+#define LTDC_LxCR_LEN_Pos            (0U)

+#define LTDC_LxCR_LEN_Msk            (0x1UL << LTDC_LxCR_LEN_Pos)              /*!< 0x00000001 */

+#define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable              */

+#define LTDC_LxCR_COLKEN_Pos         (1U)

+#define LTDC_LxCR_COLKEN_Msk         (0x1UL << LTDC_LxCR_COLKEN_Pos)           /*!< 0x00000002 */

+#define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable       */

+#define LTDC_LxCR_CLUTEN_Pos         (4U)

+#define LTDC_LxCR_CLUTEN_Msk         (0x1UL << LTDC_LxCR_CLUTEN_Pos)           /*!< 0x00000010 */

+#define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */

+

+/********************  Bit definition for LTDC_LxWHPCR register  **************/

+

+#define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)

+#define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)     /*!< 0x00000FFF */

+#define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */

+#define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)

+#define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)    /*!< 0xFFFF0000 */

+#define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position  */

+

+/********************  Bit definition for LTDC_LxWVPCR register  **************/

+

+#define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)

+#define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)     /*!< 0x00000FFF */

+#define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */

+#define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)

+#define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)    /*!< 0xFFFF0000 */

+#define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position  */

+

+/********************  Bit definition for LTDC_LxCKCR register  ***************/

+

+#define LTDC_LxCKCR_CKBLUE_Pos       (0U)

+#define LTDC_LxCKCR_CKBLUE_Msk       (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value  */

+#define LTDC_LxCKCR_CKGREEN_Pos      (8U)

+#define LTDC_LxCKCR_CKGREEN_Msk      (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */

+#define LTDC_LxCKCR_CKRED_Pos        (16U)

+#define LTDC_LxCKCR_CKRED_Msk        (0xFFUL << LTDC_LxCKCR_CKRED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value   */

+

+/********************  Bit definition for LTDC_LxPFCR register  ***************/

+

+#define LTDC_LxPFCR_PF_Pos           (0U)

+#define LTDC_LxPFCR_PF_Msk           (0x7UL << LTDC_LxPFCR_PF_Pos)             /*!< 0x00000007 */

+#define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */

+

+/********************  Bit definition for LTDC_LxCACR register  ***************/

+

+#define LTDC_LxCACR_CONSTA_Pos       (0U)

+#define LTDC_LxCACR_CONSTA_Msk       (0xFFUL << LTDC_LxCACR_CONSTA_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */

+

+/********************  Bit definition for LTDC_LxDCCR register  ***************/

+

+#define LTDC_LxDCCR_DCBLUE_Pos       (0U)

+#define LTDC_LxDCCR_DCBLUE_Msk       (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue  */

+#define LTDC_LxDCCR_DCGREEN_Pos      (8U)

+#define LTDC_LxDCCR_DCGREEN_Msk      (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */

+#define LTDC_LxDCCR_DCRED_Pos        (16U)

+#define LTDC_LxDCCR_DCRED_Msk        (0xFFUL << LTDC_LxDCCR_DCRED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red   */

+#define LTDC_LxDCCR_DCALPHA_Pos      (24U)

+#define LTDC_LxDCCR_DCALPHA_Msk      (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)       /*!< 0xFF000000 */

+#define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */

+

+/********************  Bit definition for LTDC_LxBFCR register  ***************/

+

+#define LTDC_LxBFCR_BF2_Pos          (0U)

+#define LTDC_LxBFCR_BF2_Msk          (0x7UL << LTDC_LxBFCR_BF2_Pos)            /*!< 0x00000007 */

+#define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */

+#define LTDC_LxBFCR_BF1_Pos          (8U)

+#define LTDC_LxBFCR_BF1_Msk          (0x7UL << LTDC_LxBFCR_BF1_Pos)            /*!< 0x00000700 */

+#define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */

+

+/********************  Bit definition for LTDC_LxCFBAR register  **************/

+

+#define LTDC_LxCFBAR_CFBADD_Pos      (0U)

+#define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */

+#define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */

+

+/********************  Bit definition for LTDC_LxCFBLR register  **************/

+

+#define LTDC_LxCFBLR_CFBLL_Pos       (0U)

+#define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)      /*!< 0x00001FFF */

+#define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length    */

+#define LTDC_LxCFBLR_CFBP_Pos        (16U)

+#define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)       /*!< 0x1FFF0000 */

+#define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */

+

+/********************  Bit definition for LTDC_LxCFBLNR register  *************/

+

+#define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)

+#define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)    /*!< 0x000007FF */

+#define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */

+

+/********************  Bit definition for LTDC_LxCLUTWR register  *************/

+

+#define LTDC_LxCLUTWR_BLUE_Pos       (0U)

+#define LTDC_LxCLUTWR_BLUE_Msk       (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value   */

+#define LTDC_LxCLUTWR_GREEN_Pos      (8U)

+#define LTDC_LxCLUTWR_GREEN_Msk      (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value  */

+#define LTDC_LxCLUTWR_RED_Pos        (16U)

+#define LTDC_LxCLUTWR_RED_Msk        (0xFFUL << LTDC_LxCLUTWR_RED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value    */

+#define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)

+#define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)     /*!< 0xFF000000 */

+#define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                     MDMA                                   */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for MDMA_GISR0 register  ****************/

+#define MDMA_GISR0_GIF0_Pos       (0U)

+#define MDMA_GISR0_GIF0_Msk       (0x1UL << MDMA_GISR0_GIF0_Pos)               /*!< 0x00000001 */

+#define MDMA_GISR0_GIF0           MDMA_GISR0_GIF0_Msk                          /*!< Channel 0 global interrupt flag */

+#define MDMA_GISR0_GIF1_Pos       (1U)

+#define MDMA_GISR0_GIF1_Msk       (0x1UL << MDMA_GISR0_GIF1_Pos)               /*!< 0x00000002 */

+#define MDMA_GISR0_GIF1           MDMA_GISR0_GIF1_Msk                          /*!< Channel 1 global interrupt flag */

+#define MDMA_GISR0_GIF2_Pos       (2U)

+#define MDMA_GISR0_GIF2_Msk       (0x1UL << MDMA_GISR0_GIF2_Pos)               /*!< 0x00000004 */

+#define MDMA_GISR0_GIF2           MDMA_GISR0_GIF2_Msk                          /*!< Channel 2 global interrupt flag */

+#define MDMA_GISR0_GIF3_Pos       (3U)

+#define MDMA_GISR0_GIF3_Msk       (0x1UL << MDMA_GISR0_GIF3_Pos)               /*!< 0x00000008 */

+#define MDMA_GISR0_GIF3           MDMA_GISR0_GIF3_Msk                          /*!< Channel 3 global interrupt flag */

+#define MDMA_GISR0_GIF4_Pos       (4U)

+#define MDMA_GISR0_GIF4_Msk       (0x1UL << MDMA_GISR0_GIF4_Pos)               /*!< 0x00000010 */

+#define MDMA_GISR0_GIF4           MDMA_GISR0_GIF4_Msk                          /*!< Channel 4 global interrupt flag */

+#define MDMA_GISR0_GIF5_Pos       (5U)

+#define MDMA_GISR0_GIF5_Msk       (0x1UL << MDMA_GISR0_GIF5_Pos)               /*!< 0x00000020 */

+#define MDMA_GISR0_GIF5           MDMA_GISR0_GIF5_Msk                          /*!< Channel 5 global interrupt flag */

+#define MDMA_GISR0_GIF6_Pos       (6U)

+#define MDMA_GISR0_GIF6_Msk       (0x1UL << MDMA_GISR0_GIF6_Pos)               /*!< 0x00000040 */

+#define MDMA_GISR0_GIF6           MDMA_GISR0_GIF6_Msk                          /*!< Channel 6 global interrupt flag */

+#define MDMA_GISR0_GIF7_Pos       (7U)

+#define MDMA_GISR0_GIF7_Msk       (0x1UL << MDMA_GISR0_GIF7_Pos)               /*!< 0x00000080 */

+#define MDMA_GISR0_GIF7           MDMA_GISR0_GIF7_Msk                          /*!< Channel 7 global interrupt flag */

+#define MDMA_GISR0_GIF8_Pos       (8U)

+#define MDMA_GISR0_GIF8_Msk       (0x1UL << MDMA_GISR0_GIF8_Pos)               /*!< 0x00000100 */

+#define MDMA_GISR0_GIF8           MDMA_GISR0_GIF8_Msk                          /*!< Channel 8 global interrupt flag */

+#define MDMA_GISR0_GIF9_Pos       (9U)

+#define MDMA_GISR0_GIF9_Msk       (0x1UL << MDMA_GISR0_GIF9_Pos)               /*!< 0x00000200 */

+#define MDMA_GISR0_GIF9           MDMA_GISR0_GIF9_Msk                          /*!< Channel 9 global interrupt flag */

+#define MDMA_GISR0_GIF10_Pos      (10U)

+#define MDMA_GISR0_GIF10_Msk      (0x1UL << MDMA_GISR0_GIF10_Pos)              /*!< 0x00000400 */

+#define MDMA_GISR0_GIF10          MDMA_GISR0_GIF10_Msk                         /*!< Channel 10 global interrupt flag */

+#define MDMA_GISR0_GIF11_Pos      (11U)

+#define MDMA_GISR0_GIF11_Msk      (0x1UL << MDMA_GISR0_GIF11_Pos)              /*!< 0x00000800 */

+#define MDMA_GISR0_GIF11          MDMA_GISR0_GIF11_Msk                         /*!< Channel 11 global interrupt flag */

+#define MDMA_GISR0_GIF12_Pos      (12U)

+#define MDMA_GISR0_GIF12_Msk      (0x1UL << MDMA_GISR0_GIF12_Pos)              /*!< 0x00001000 */

+#define MDMA_GISR0_GIF12          MDMA_GISR0_GIF12_Msk                         /*!< Channel 12 global interrupt flag */

+#define MDMA_GISR0_GIF13_Pos      (13U)

+#define MDMA_GISR0_GIF13_Msk      (0x1UL << MDMA_GISR0_GIF13_Pos)              /*!< 0x00002000 */

+#define MDMA_GISR0_GIF13          MDMA_GISR0_GIF13_Msk                         /*!< Channel 13 global interrupt flag */

+#define MDMA_GISR0_GIF14_Pos      (14U)

+#define MDMA_GISR0_GIF14_Msk      (0x1UL << MDMA_GISR0_GIF14_Pos)              /*!< 0x00004000 */

+#define MDMA_GISR0_GIF14          MDMA_GISR0_GIF14_Msk                         /*!< Channel 14 global interrupt flag */

+#define MDMA_GISR0_GIF15_Pos      (15U)

+#define MDMA_GISR0_GIF15_Msk      (0x1UL << MDMA_GISR0_GIF15_Pos)              /*!< 0x00008000 */

+#define MDMA_GISR0_GIF15          MDMA_GISR0_GIF15_Msk                         /*!< Channel 15 global interrupt flag */

+

+/********************  Bit definition for MDMA_CxISR register  ****************/

+#define MDMA_CISR_TEIF_Pos        (0U)

+#define MDMA_CISR_TEIF_Msk        (0x1UL << MDMA_CISR_TEIF_Pos)                /*!< 0x00000001 */

+#define MDMA_CISR_TEIF            MDMA_CISR_TEIF_Msk                           /*!< Channel x transfer error interrupt flag */

+#define MDMA_CISR_CTCIF_Pos       (1U)

+#define MDMA_CISR_CTCIF_Msk       (0x1UL << MDMA_CISR_CTCIF_Pos)               /*!< 0x00000002 */

+#define MDMA_CISR_CTCIF           MDMA_CISR_CTCIF_Msk                          /*!< Channel x Channel Transfer Complete interrupt flag */

+#define MDMA_CISR_BRTIF_Pos       (2U)

+#define MDMA_CISR_BRTIF_Msk       (0x1UL << MDMA_CISR_BRTIF_Pos)               /*!< 0x00000004 */

+#define MDMA_CISR_BRTIF           MDMA_CISR_BRTIF_Msk                          /*!< Channel x block repeat transfer complete interrupt flag */

+#define MDMA_CISR_BTIF_Pos        (3U)

+#define MDMA_CISR_BTIF_Msk        (0x1UL << MDMA_CISR_BTIF_Pos)                /*!< 0x00000008 */

+#define MDMA_CISR_BTIF            MDMA_CISR_BTIF_Msk                           /*!< Channel x block transfer complete interrupt flag */

+#define MDMA_CISR_TCIF_Pos        (4U)

+#define MDMA_CISR_TCIF_Msk        (0x1UL << MDMA_CISR_TCIF_Pos)                /*!< 0x00000010 */

+#define MDMA_CISR_TCIF            MDMA_CISR_TCIF_Msk                           /*!< Channel x buffer transfer complete interrupt flag */

+#define MDMA_CISR_CRQA_Pos        (16U)

+#define MDMA_CISR_CRQA_Msk        (0x1UL << MDMA_CISR_CRQA_Pos)                /*!< 0x00010000 */

+#define MDMA_CISR_CRQA            MDMA_CISR_CRQA_Msk                           /*!< Channel x ReQest Active flag */

+

+/********************  Bit definition for MDMA_CxIFCR register  ****************/

+#define MDMA_CIFCR_CTEIF_Pos      (0U)

+#define MDMA_CIFCR_CTEIF_Msk      (0x1UL << MDMA_CIFCR_CTEIF_Pos)              /*!< 0x00000001 */

+#define MDMA_CIFCR_CTEIF          MDMA_CIFCR_CTEIF_Msk                         /*!< Channel x clear transfer error interrupt flag */

+#define MDMA_CIFCR_CCTCIF_Pos     (1U)

+#define MDMA_CIFCR_CCTCIF_Msk     (0x1UL << MDMA_CIFCR_CCTCIF_Pos)             /*!< 0x00000002 */

+#define MDMA_CIFCR_CCTCIF         MDMA_CIFCR_CCTCIF_Msk                        /*!< Clear Channel transfer complete interrupt flag for channel x */

+#define MDMA_CIFCR_CBRTIF_Pos     (2U)

+#define MDMA_CIFCR_CBRTIF_Msk     (0x1UL << MDMA_CIFCR_CBRTIF_Pos)             /*!< 0x00000004 */

+#define MDMA_CIFCR_CBRTIF         MDMA_CIFCR_CBRTIF_Msk                        /*!< Channel x clear block repeat transfer complete interrupt flag */

+#define MDMA_CIFCR_CBTIF_Pos      (3U)

+#define MDMA_CIFCR_CBTIF_Msk      (0x1UL << MDMA_CIFCR_CBTIF_Pos)              /*!< 0x00000008 */

+#define MDMA_CIFCR_CBTIF          MDMA_CIFCR_CBTIF_Msk                         /*!< Channel x Clear block transfer complete interrupt flag */

+#define MDMA_CIFCR_CLTCIF_Pos     (4U)

+#define MDMA_CIFCR_CLTCIF_Msk     (0x1UL << MDMA_CIFCR_CLTCIF_Pos)             /*!< 0x00000010 */

+#define MDMA_CIFCR_CLTCIF         MDMA_CIFCR_CLTCIF_Msk                        /*!< CLear Transfer buffer Complete Interrupt Flag for channel */

+

+/********************  Bit definition for MDMA_CxESR register  ****************/

+#define MDMA_CESR_TEA_Pos         (0U)

+#define MDMA_CESR_TEA_Msk         (0x7FUL << MDMA_CESR_TEA_Pos)                /*!< 0x0000007F */

+#define MDMA_CESR_TEA             MDMA_CESR_TEA_Msk                            /*!< Transfer Error Address */

+#define MDMA_CESR_TED_Pos         (7U)

+#define MDMA_CESR_TED_Msk         (0x1UL << MDMA_CESR_TED_Pos)                 /*!< 0x00000080 */

+#define MDMA_CESR_TED             MDMA_CESR_TED_Msk                            /*!< Transfer Error Direction */

+#define MDMA_CESR_TELD_Pos        (8U)

+#define MDMA_CESR_TELD_Msk        (0x1UL << MDMA_CESR_TELD_Pos)                /*!< 0x00000100 */

+#define MDMA_CESR_TELD            MDMA_CESR_TELD_Msk                           /*!< Transfer Error Link Data */

+#define MDMA_CESR_TEMD_Pos        (9U)

+#define MDMA_CESR_TEMD_Msk        (0x1UL << MDMA_CESR_TEMD_Pos)                /*!< 0x00000200 */

+#define MDMA_CESR_TEMD            MDMA_CESR_TEMD_Msk                           /*!< Transfer Error Mask Data */

+#define MDMA_CESR_ASE_Pos         (10U)

+#define MDMA_CESR_ASE_Msk         (0x1UL << MDMA_CESR_ASE_Pos)                 /*!< 0x00000400 */

+#define MDMA_CESR_ASE             MDMA_CESR_ASE_Msk                            /*!< Address/Size Error       */

+#define MDMA_CESR_BSE_Pos         (11U)

+#define MDMA_CESR_BSE_Msk         (0x1UL << MDMA_CESR_BSE_Pos)                 /*!< 0x00000800 */

+#define MDMA_CESR_BSE             MDMA_CESR_BSE_Msk                            /*!< Block Size Error         */

+

+/********************  Bit definition for MDMA_CxCR register  ****************/

+#define MDMA_CCR_EN_Pos           (0U)

+#define MDMA_CCR_EN_Msk           (0x1UL << MDMA_CCR_EN_Pos)                   /*!< 0x00000001 */

+#define MDMA_CCR_EN               MDMA_CCR_EN_Msk                              /*!< Channel enable / flag channel ready when read low */

+#define MDMA_CCR_TEIE_Pos         (1U)

+#define MDMA_CCR_TEIE_Msk         (0x1UL << MDMA_CCR_TEIE_Pos)                 /*!< 0x00000002 */

+#define MDMA_CCR_TEIE             MDMA_CCR_TEIE_Msk                            /*!< Transfer error interrupt enable */

+#define MDMA_CCR_CTCIE_Pos        (2U)

+#define MDMA_CCR_CTCIE_Msk        (0x1UL << MDMA_CCR_CTCIE_Pos)                /*!< 0x00000004 */

+#define MDMA_CCR_CTCIE            MDMA_CCR_CTCIE_Msk                           /*!< Channel Transfer Complete interrupt enable */

+#define MDMA_CCR_BRTIE_Pos        (3U)

+#define MDMA_CCR_BRTIE_Msk        (0x1UL << MDMA_CCR_BRTIE_Pos)                /*!< 0x00000008 */

+#define MDMA_CCR_BRTIE            MDMA_CCR_BRTIE_Msk                           /*!< Block Repeat transfer interrupt enable */

+#define MDMA_CCR_BTIE_Pos         (4U)

+#define MDMA_CCR_BTIE_Msk         (0x1UL << MDMA_CCR_BTIE_Pos)                 /*!< 0x00000010 */

+#define MDMA_CCR_BTIE             MDMA_CCR_BTIE_Msk                            /*!< Block Transfer interrupt enable */

+#define MDMA_CCR_TCIE_Pos         (5U)

+#define MDMA_CCR_TCIE_Msk         (0x1UL << MDMA_CCR_TCIE_Pos)                 /*!< 0x00000020 */

+#define MDMA_CCR_TCIE             MDMA_CCR_TCIE_Msk                            /*!< buffer Transfer Complete interrupt enable */

+#define MDMA_CCR_PL_Pos           (6U)

+#define MDMA_CCR_PL_Msk           (0x3UL << MDMA_CCR_PL_Pos)                   /*!< 0x000000C0 */

+#define MDMA_CCR_PL               MDMA_CCR_PL_Msk                              /*!< Priority level */

+#define MDMA_CCR_PL_0             (0x1UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000040 */

+#define MDMA_CCR_PL_1             (0x2UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000080 */

+#define MDMA_CCR_BEX_Pos          (12U)

+#define MDMA_CCR_BEX_Msk          (0x1UL << MDMA_CCR_BEX_Pos)                  /*!< 0x00001000 */

+#define MDMA_CCR_BEX              MDMA_CCR_BEX_Msk                             /*!< Byte Endianess eXchange */

+#define MDMA_CCR_HEX_Pos          (13U)

+#define MDMA_CCR_HEX_Msk          (0x1UL << MDMA_CCR_HEX_Pos)                  /*!< 0x00002000 */

+#define MDMA_CCR_HEX              MDMA_CCR_HEX_Msk                             /*!< Half word Endianess eXchange */

+#define MDMA_CCR_WEX_Pos          (14U)

+#define MDMA_CCR_WEX_Msk          (0x1UL << MDMA_CCR_WEX_Pos)                  /*!< 0x00004000 */

+#define MDMA_CCR_WEX              MDMA_CCR_WEX_Msk                             /*!< Word Endianess eXchange */

+#define MDMA_CCR_SWRQ_Pos         (16U)

+#define MDMA_CCR_SWRQ_Msk         (0x1UL << MDMA_CCR_SWRQ_Pos)                 /*!< 0x00010000 */

+#define MDMA_CCR_SWRQ             MDMA_CCR_SWRQ_Msk                            /*!< SW ReQuest */

+

+/********************  Bit definition for MDMA_CxTCR register  ****************/

+#define MDMA_CTCR_SINC_Pos        (0U)

+#define MDMA_CTCR_SINC_Msk        (0x3UL << MDMA_CTCR_SINC_Pos)                /*!< 0x00000003 */

+#define MDMA_CTCR_SINC            MDMA_CTCR_SINC_Msk                           /*!< Source increment mode */

+#define MDMA_CTCR_SINC_0          (0x1UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000001 */

+#define MDMA_CTCR_SINC_1          (0x2UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000002 */

+#define MDMA_CTCR_DINC_Pos        (2U)

+#define MDMA_CTCR_DINC_Msk        (0x3UL << MDMA_CTCR_DINC_Pos)                /*!< 0x0000000C */

+#define MDMA_CTCR_DINC            MDMA_CTCR_DINC_Msk                           /*!< Source increment mode */

+#define MDMA_CTCR_DINC_0          (0x1UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000004 */

+#define MDMA_CTCR_DINC_1          (0x2UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000008 */

+#define MDMA_CTCR_SSIZE_Pos       (4U)

+#define MDMA_CTCR_SSIZE_Msk       (0x3UL << MDMA_CTCR_SSIZE_Pos)               /*!< 0x00000030 */

+#define MDMA_CTCR_SSIZE           MDMA_CTCR_SSIZE_Msk                          /*!< Source data size */

+#define MDMA_CTCR_SSIZE_0         (0x1UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000010 */

+#define MDMA_CTCR_SSIZE_1         (0x2UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000020 */

+#define MDMA_CTCR_DSIZE_Pos       (6U)

+#define MDMA_CTCR_DSIZE_Msk       (0x3UL << MDMA_CTCR_DSIZE_Pos)               /*!< 0x000000C0 */

+#define MDMA_CTCR_DSIZE           MDMA_CTCR_DSIZE_Msk                          /*!< Destination data size */

+#define MDMA_CTCR_DSIZE_0         (0x1UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000040 */

+#define MDMA_CTCR_DSIZE_1         (0x2UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000080 */

+#define MDMA_CTCR_SINCOS_Pos      (8U)

+#define MDMA_CTCR_SINCOS_Msk      (0x3UL << MDMA_CTCR_SINCOS_Pos)              /*!< 0x00000300 */

+#define MDMA_CTCR_SINCOS          MDMA_CTCR_SINCOS_Msk                         /*!< Source increment offset size */

+#define MDMA_CTCR_SINCOS_0        (0x1UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000100 */

+#define MDMA_CTCR_SINCOS_1        (0x2UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000200 */

+#define MDMA_CTCR_DINCOS_Pos      (10U)

+#define MDMA_CTCR_DINCOS_Msk      (0x3UL << MDMA_CTCR_DINCOS_Pos)              /*!< 0x00000C00 */

+#define MDMA_CTCR_DINCOS          MDMA_CTCR_DINCOS_Msk                         /*!< Destination increment offset size */

+#define MDMA_CTCR_DINCOS_0        (0x1UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000400 */

+#define MDMA_CTCR_DINCOS_1        (0x2UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000800 */

+#define MDMA_CTCR_SBURST_Pos      (12U)

+#define MDMA_CTCR_SBURST_Msk      (0x7UL << MDMA_CTCR_SBURST_Pos)              /*!< 0x00007000 */

+#define MDMA_CTCR_SBURST          MDMA_CTCR_SBURST_Msk                         /*!< Source burst transfer configuration */

+#define MDMA_CTCR_SBURST_0        (0x1UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00001000 */

+#define MDMA_CTCR_SBURST_1        (0x2UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00002000 */

+#define MDMA_CTCR_SBURST_2        (0x4UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00004000 */

+#define MDMA_CTCR_DBURST_Pos      (15U)

+#define MDMA_CTCR_DBURST_Msk      (0x7UL << MDMA_CTCR_DBURST_Pos)              /*!< 0x00038000 */

+#define MDMA_CTCR_DBURST          MDMA_CTCR_DBURST_Msk                         /*!< Destination burst transfer configuration */

+#define MDMA_CTCR_DBURST_0        (0x1UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00008000 */

+#define MDMA_CTCR_DBURST_1        (0x2UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00010000 */

+#define MDMA_CTCR_DBURST_2        (0x4UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00020000 */

+#define MDMA_CTCR_TLEN_Pos        (18U)

+#define MDMA_CTCR_TLEN_Msk        (0x7FUL << MDMA_CTCR_TLEN_Pos)               /*!< 0x01FC0000 */

+#define MDMA_CTCR_TLEN            MDMA_CTCR_TLEN_Msk                           /*!< buffer Transfer Length (number of bytes - 1) */

+#define MDMA_CTCR_PKE_Pos         (25U)

+#define MDMA_CTCR_PKE_Msk         (0x1UL << MDMA_CTCR_PKE_Pos)                 /*!< 0x02000000 */

+#define MDMA_CTCR_PKE             MDMA_CTCR_PKE_Msk                            /*!< PacK Enable */

+#define MDMA_CTCR_PAM_Pos         (26U)

+#define MDMA_CTCR_PAM_Msk         (0x3UL << MDMA_CTCR_PAM_Pos)                 /*!< 0x0C000000 */

+#define MDMA_CTCR_PAM             MDMA_CTCR_PAM_Msk                            /*!< Padding/Alignement Mode */

+#define MDMA_CTCR_PAM_0           (0x1UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x4000000 */

+#define MDMA_CTCR_PAM_1           (0x2UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x8000000 */

+#define MDMA_CTCR_TRGM_Pos        (28U)

+#define MDMA_CTCR_TRGM_Msk        (0x3UL << MDMA_CTCR_TRGM_Pos)                /*!< 0x30000000 */

+#define MDMA_CTCR_TRGM            MDMA_CTCR_TRGM_Msk                           /*!< Trigger Mode */

+#define MDMA_CTCR_TRGM_0          (0x1UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x10000000 */

+#define MDMA_CTCR_TRGM_1          (0x2UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x20000000 */

+#define MDMA_CTCR_SWRM_Pos        (30U)

+#define MDMA_CTCR_SWRM_Msk        (0x1UL << MDMA_CTCR_SWRM_Pos)                /*!< 0x40000000 */

+#define MDMA_CTCR_SWRM            MDMA_CTCR_SWRM_Msk                           /*!< SW Request Mode */

+#define MDMA_CTCR_BWM_Pos         (31U)

+#define MDMA_CTCR_BWM_Msk         (0x1UL << MDMA_CTCR_BWM_Pos)                 /*!< 0x80000000 */

+#define MDMA_CTCR_BWM             MDMA_CTCR_BWM_Msk                            /*!< Bufferable Write Mode */

+

+/********************  Bit definition for MDMA_CxBNDTR register  ****************/

+#define MDMA_CBNDTR_BNDT_Pos      (0U)

+#define MDMA_CBNDTR_BNDT_Msk      (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos)          /*!< 0x0001FFFF */

+#define MDMA_CBNDTR_BNDT          MDMA_CBNDTR_BNDT_Msk                         /*!< Block Number of data bytes to transfer */

+#define MDMA_CBNDTR_BRSUM_Pos     (18U)

+#define MDMA_CBNDTR_BRSUM_Msk     (0x1UL << MDMA_CBNDTR_BRSUM_Pos)             /*!< 0x00040000 */

+#define MDMA_CBNDTR_BRSUM         MDMA_CBNDTR_BRSUM_Msk                        /*!< Block Repeat Source address Update Mode */

+#define MDMA_CBNDTR_BRDUM_Pos     (19U)

+#define MDMA_CBNDTR_BRDUM_Msk     (0x1UL << MDMA_CBNDTR_BRDUM_Pos)             /*!< 0x00080000 */

+#define MDMA_CBNDTR_BRDUM         MDMA_CBNDTR_BRDUM_Msk                        /*!< Block Repeat Destination address Update Mode */

+#define MDMA_CBNDTR_BRC_Pos       (20U)

+#define MDMA_CBNDTR_BRC_Msk       (0xFFFUL << MDMA_CBNDTR_BRC_Pos)             /*!< 0xFFF00000 */

+#define MDMA_CBNDTR_BRC           MDMA_CBNDTR_BRC_Msk                          /*!< Block Repeat Count */

+

+/********************  Bit definition for MDMA_CxSAR register  ****************/

+#define MDMA_CSAR_SAR_Pos         (0U)

+#define MDMA_CSAR_SAR_Msk         (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CSAR_SAR             MDMA_CSAR_SAR_Msk                            /*!< Source address */

+

+/********************  Bit definition for MDMA_CxDAR register  ****************/

+#define MDMA_CDAR_DAR_Pos         (0U)

+#define MDMA_CDAR_DAR_Msk         (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CDAR_DAR             MDMA_CDAR_DAR_Msk                            /*!< Destination address */

+

+/********************  Bit definition for MDMA_CxBRUR  ************************/

+#define MDMA_CBRUR_SUV_Pos        (0U)

+#define MDMA_CBRUR_SUV_Msk        (0xFFFFUL << MDMA_CBRUR_SUV_Pos)             /*!< 0x0000FFFF */

+#define MDMA_CBRUR_SUV            MDMA_CBRUR_SUV_Msk                           /*!< Source address Update Value */

+#define MDMA_CBRUR_DUV_Pos        (16U)

+#define MDMA_CBRUR_DUV_Msk        (0xFFFFUL << MDMA_CBRUR_DUV_Pos)             /*!< 0xFFFF0000 */

+#define MDMA_CBRUR_DUV            MDMA_CBRUR_DUV_Msk                           /*!< Destination address Update Value */

+

+/********************  Bit definition for MDMA_CxLAR  *************************/

+#define MDMA_CLAR_LAR_Pos         (0U)

+#define MDMA_CLAR_LAR_Msk         (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CLAR_LAR             MDMA_CLAR_LAR_Msk                            /*!< Link Address Register */

+

+/********************  Bit definition for MDMA_CxTBR)  ************************/

+#define MDMA_CTBR_TSEL_Pos        (0U)

+#define MDMA_CTBR_TSEL_Msk        (0xFFUL << MDMA_CTBR_TSEL_Pos)               /*!< 0x000000FF */

+#define MDMA_CTBR_TSEL            MDMA_CTBR_TSEL_Msk                           /*!< Trigger SELection */

+#define MDMA_CTBR_SBUS_Pos        (16U)

+#define MDMA_CTBR_SBUS_Msk        (0x1UL << MDMA_CTBR_SBUS_Pos)                /*!< 0x00010000 */

+#define MDMA_CTBR_SBUS            MDMA_CTBR_SBUS_Msk                           /*!< Source BUS select */

+#define MDMA_CTBR_DBUS_Pos        (17U)

+#define MDMA_CTBR_DBUS_Msk        (0x1UL << MDMA_CTBR_DBUS_Pos)                /*!< 0x00020000 */

+#define MDMA_CTBR_DBUS            MDMA_CTBR_DBUS_Msk                           /*!< Destination BUS select */

+

+/********************  Bit definition for MDMA_CxMAR)  ************************/

+#define MDMA_CMAR_MAR_Pos         (0U)

+#define MDMA_CMAR_MAR_Msk         (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CMAR_MAR             MDMA_CMAR_MAR_Msk                            /*!< Mask address */

+

+/********************  Bit definition for MDMA_CxMDR)  ************************/

+#define MDMA_CMDR_MDR_Pos         (0U)

+#define MDMA_CMDR_MDR_Msk         (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CMDR_MDR             MDMA_CMDR_MDR_Msk                            /*!< Mask Data */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Operational Amplifier (OPAMP)                      */

+/*                                                                            */

+/******************************************************************************/

+/*********************  Bit definition for OPAMPx_CSR register  ***************/

+#define OPAMP_CSR_OPAMPxEN_Pos           (0U)

+#define OPAMP_CSR_OPAMPxEN_Msk           (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)     /*!< 0x00000001 */

+#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */

+#define OPAMP_CSR_FORCEVP_Pos            (1U)

+#define OPAMP_CSR_FORCEVP_Msk            (0x1UL << OPAMP_CSR_FORCEVP_Pos)      /*!< 0x00000002 */

+#define OPAMP_CSR_FORCEVP                OPAMP_CSR_FORCEVP_Msk                 /*!< Force internal reference on VP */

+

+#define OPAMP_CSR_VPSEL_Pos              (2U)

+#define OPAMP_CSR_VPSEL_Msk              (0x3UL << OPAMP_CSR_VPSEL_Pos)        /*!< 0x0000000C */

+#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */

+#define OPAMP_CSR_VPSEL_0                (0x1UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000004 */

+#define OPAMP_CSR_VPSEL_1                (0x2UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000008 */

+

+#define OPAMP_CSR_VMSEL_Pos              (5U)

+#define OPAMP_CSR_VMSEL_Msk              (0x3UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000060 */

+#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */

+#define OPAMP_CSR_VMSEL_0                (0x1UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000020 */

+#define OPAMP_CSR_VMSEL_1                (0x2UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000040 */

+

+#define OPAMP_CSR_OPAHSM_Pos             (8U)

+#define OPAMP_CSR_OPAHSM_Msk             (0x1UL << OPAMP_CSR_OPAHSM_Pos)       /*!< 0x00000100 */

+#define OPAMP_CSR_OPAHSM                 OPAMP_CSR_OPAHSM_Msk                  /*!< Operational amplifier high speed mode */

+#define OPAMP_CSR_CALON_Pos              (11U)

+#define OPAMP_CSR_CALON_Msk              (0x1UL << OPAMP_CSR_CALON_Pos)        /*!< 0x00000800 */

+#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */

+

+#define OPAMP_CSR_CALSEL_Pos             (12U)

+#define OPAMP_CSR_CALSEL_Msk             (0x3UL << OPAMP_CSR_CALSEL_Pos)       /*!< 0x00003000 */

+#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */

+#define OPAMP_CSR_CALSEL_0               (0x1UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00001000 */

+#define OPAMP_CSR_CALSEL_1               (0x2UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */

+

+#define OPAMP_CSR_PGGAIN_Pos             (14U)

+#define OPAMP_CSR_PGGAIN_Msk             (0xFUL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x0003C000 */

+#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */

+#define OPAMP_CSR_PGGAIN_0               (0x1UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00004000 */

+#define OPAMP_CSR_PGGAIN_1               (0x2UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00008000 */

+#define OPAMP_CSR_PGGAIN_2               (0x4UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00010000 */

+#define OPAMP_CSR_PGGAIN_3               (0x8UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00020000 */

+

+#define OPAMP_CSR_USERTRIM_Pos           (18U)

+#define OPAMP_CSR_USERTRIM_Msk           (0x1UL << OPAMP_CSR_USERTRIM_Pos)     /*!< 0x00040000 */

+#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */

+#define OPAMP_CSR_TSTREF_Pos             (29U)

+#define OPAMP_CSR_TSTREF_Msk             (0x1UL << OPAMP_CSR_TSTREF_Pos)       /*!< 0x20000000 */

+#define OPAMP_CSR_TSTREF                 OPAMP_CSR_TSTREF_Msk                  /*!< OpAmp calibration reference voltage output control */

+#define OPAMP_CSR_CALOUT_Pos             (30U)

+#define OPAMP_CSR_CALOUT_Msk             (0x1UL << OPAMP_CSR_CALOUT_Pos)       /*!< 0x40000000 */

+#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier calibration output */

+

+/*********************  Bit definition for OPAMP1_CSR register  ***************/

+#define OPAMP1_CSR_OPAEN_Pos              (0U)

+#define OPAMP1_CSR_OPAEN_Msk              (0x1UL << OPAMP1_CSR_OPAEN_Pos)      /*!< 0x00000001 */

+#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */

+#define OPAMP1_CSR_FORCEVP_Pos            (1U)

+#define OPAMP1_CSR_FORCEVP_Msk            (0x1UL << OPAMP1_CSR_FORCEVP_Pos)    /*!< 0x00000002 */

+#define OPAMP1_CSR_FORCEVP                OPAMP1_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */

+

+#define OPAMP1_CSR_VPSEL_Pos              (2U)

+#define OPAMP1_CSR_VPSEL_Msk              (0x3UL << OPAMP1_CSR_VPSEL_Pos)      /*!< 0x0000000C */

+#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */

+#define OPAMP1_CSR_VPSEL_0                (0x1UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000004 */

+#define OPAMP1_CSR_VPSEL_1                (0x2UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000008 */

+

+#define OPAMP1_CSR_VMSEL_Pos              (5U)

+#define OPAMP1_CSR_VMSEL_Msk              (0x3UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000060 */

+#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */

+#define OPAMP1_CSR_VMSEL_0                (0x1UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000020 */

+#define OPAMP1_CSR_VMSEL_1                (0x2UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000040 */

+

+#define OPAMP1_CSR_OPAHSM_Pos             (8U)

+#define OPAMP1_CSR_OPAHSM_Msk             (0x1UL << OPAMP1_CSR_OPAHSM_Pos)     /*!< 0x00000100 */

+#define OPAMP1_CSR_OPAHSM                 OPAMP1_CSR_OPAHSM_Msk                /*!< Operational amplifier1 high speed mode */

+#define OPAMP1_CSR_CALON_Pos              (11U)

+#define OPAMP1_CSR_CALON_Msk              (0x1UL << OPAMP1_CSR_CALON_Pos)      /*!< 0x00000800 */

+#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */

+

+#define OPAMP1_CSR_CALSEL_Pos             (12U)

+#define OPAMP1_CSR_CALSEL_Msk             (0x3UL << OPAMP1_CSR_CALSEL_Pos)     /*!< 0x00003000 */

+#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */

+#define OPAMP1_CSR_CALSEL_0               (0x1UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00001000 */

+#define OPAMP1_CSR_CALSEL_1               (0x2UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */

+

+#define OPAMP1_CSR_PGGAIN_Pos             (14U)

+#define OPAMP1_CSR_PGGAIN_Msk             (0xFUL << OPAMP1_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */

+#define OPAMP1_CSR_PGGAIN                 OPAMP1_CSR_PGGAIN_Msk                /*!< Operational amplifier1 Programmable amplifier gain value */

+#define OPAMP1_CSR_PGGAIN_0               (0x1UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00004000 */

+#define OPAMP1_CSR_PGGAIN_1               (0x2UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00008000 */

+#define OPAMP1_CSR_PGGAIN_2               (0x4UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00010000 */

+#define OPAMP1_CSR_PGGAIN_3               (0x8UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00020000 */

+

+#define OPAMP1_CSR_USERTRIM_Pos           (18U)

+#define OPAMP1_CSR_USERTRIM_Msk           (0x1UL << OPAMP1_CSR_USERTRIM_Pos)   /*!< 0x00040000 */

+#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */

+#define OPAMP1_CSR_TSTREF_Pos             (29U)

+#define OPAMP1_CSR_TSTREF_Msk             (0x1UL << OPAMP1_CSR_TSTREF_Pos)     /*!< 0x20000000 */

+#define OPAMP1_CSR_TSTREF                 OPAMP1_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */

+#define OPAMP1_CSR_CALOUT_Pos             (30U)

+#define OPAMP1_CSR_CALOUT_Msk             (0x1UL << OPAMP1_CSR_CALOUT_Pos)     /*!< 0x40000000 */

+#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */

+

+/*********************  Bit definition for OPAMP2_CSR register  ***************/

+#define OPAMP2_CSR_OPAEN_Pos              (0U)

+#define OPAMP2_CSR_OPAEN_Msk              (0x1UL << OPAMP2_CSR_OPAEN_Pos)      /*!< 0x00000001 */

+#define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */

+#define OPAMP2_CSR_FORCEVP_Pos            (1U)

+#define OPAMP2_CSR_FORCEVP_Msk            (0x1UL << OPAMP2_CSR_FORCEVP_Pos)    /*!< 0x00000002 */

+#define OPAMP2_CSR_FORCEVP                OPAMP2_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */

+

+#define OPAMP2_CSR_VPSEL_Pos              (2U)

+#define OPAMP2_CSR_VPSEL_Msk              (0x3UL << OPAMP2_CSR_VPSEL_Pos)      /*!< 0x0000000C */

+#define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */

+#define OPAMP2_CSR_VPSEL_0                (0x1UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000004 */

+#define OPAMP2_CSR_VPSEL_1                (0x2UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000008 */

+

+#define OPAMP2_CSR_VMSEL_Pos              (5U)

+#define OPAMP2_CSR_VMSEL_Msk              (0x3UL << OPAMP2_CSR_VMSEL_Pos)      /*!< 0x00000060 */

+#define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */

+#define OPAMP2_CSR_VMSEL_0                (0x1UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000020 */

+#define OPAMP2_CSR_VMSEL_1                (0x2UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000040 */

+

+#define OPAMP2_CSR_OPAHSM_Pos             (8U)

+#define OPAMP2_CSR_OPAHSM_Msk             (0x1UL << OPAMP2_CSR_OPAHSM_Pos)     /*!< 0x00000100 */

+#define OPAMP2_CSR_OPAHSM                 OPAMP2_CSR_OPAHSM_Msk                /*!< Operational amplifier2 high speed mode */

+#define OPAMP2_CSR_CALON_Pos              (11U)

+#define OPAMP2_CSR_CALON_Msk              (0x1UL << OPAMP2_CSR_CALON_Pos)      /*!< 0x00000800 */

+#define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */

+

+#define OPAMP2_CSR_CALSEL_Pos             (12U)

+#define OPAMP2_CSR_CALSEL_Msk             (0x3UL << OPAMP2_CSR_CALSEL_Pos)     /*!< 0x00003000 */

+#define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */

+#define OPAMP2_CSR_CALSEL_0               (0x1UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00001000 */

+#define OPAMP2_CSR_CALSEL_1               (0x2UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */

+

+#define OPAMP2_CSR_PGGAIN_Pos             (14U)

+#define OPAMP2_CSR_PGGAIN_Msk             (0xFUL << OPAMP2_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */

+#define OPAMP2_CSR_PGGAIN                 OPAMP2_CSR_PGGAIN_Msk                /*!< Operational amplifier2 Programmable amplifier gain value */

+#define OPAMP2_CSR_PGGAIN_0               (0x1UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00004000 */

+#define OPAMP2_CSR_PGGAIN_1               (0x2UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00008000 */

+#define OPAMP2_CSR_PGGAIN_2               (0x4UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00010000 */

+#define OPAMP2_CSR_PGGAIN_3               (0x8UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00020000 */

+

+#define OPAMP2_CSR_USERTRIM_Pos           (18U)

+#define OPAMP2_CSR_USERTRIM_Msk           (0x1UL << OPAMP2_CSR_USERTRIM_Pos)   /*!< 0x00040000 */

+#define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */

+#define OPAMP2_CSR_TSTREF_Pos             (29U)

+#define OPAMP2_CSR_TSTREF_Msk             (0x1UL << OPAMP2_CSR_TSTREF_Pos)     /*!< 0x20000000 */

+#define OPAMP2_CSR_TSTREF                 OPAMP2_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */

+#define OPAMP2_CSR_CALOUT_Pos             (30U)

+#define OPAMP2_CSR_CALOUT_Msk             (0x1UL << OPAMP2_CSR_CALOUT_Pos)     /*!< 0x40000000 */

+#define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */

+

+/*******************  Bit definition for OPAMP_OTR register  ******************/

+#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */

+#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP1_OTR register  ******************/

+#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */

+#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP2_OTR register  ******************/

+#define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */

+#define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP_HSOTR register  ****************/

+#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP_HSOTR_TRIMHSOFFSETN        OPAMP_HSOTR_TRIMHSOFFSETN_Msk         /*!< Trim for NMOS differential pairs */

+#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP_HSOTR_TRIMHSOFFSETP        OPAMP_HSOTR_TRIMHSOFFSETP_Msk         /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP1_HSOTR register  ****************/

+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP1_HSOTR_TRIMHSOFFSETN        OPAMP1_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */

+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP1_HSOTR_TRIMHSOFFSETP        OPAMP1_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP2_HSOTR register  ****************/

+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP2_HSOTR_TRIMHSOFFSETN        OPAMP2_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */

+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP2_HSOTR_TRIMHSOFFSETP        OPAMP2_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */

+

+/******************************************************************************/

+/*                                                                            */

+/*                Parallel Synchronous Slave Interface (PSSI )                */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for PSSI_CR register  *******************/

+#define PSSI_CR_OUTEN_Pos               (31U)

+#define PSSI_CR_OUTEN_Msk               (0x1UL << PSSI_CR_OUTEN_Pos)           /*!< 0x80000000 */

+#define PSSI_CR_OUTEN                   PSSI_CR_OUTEN_Msk                      /*!< Data direction selection */

+#define PSSI_CR_DMAEN_Pos               (30U)

+#define PSSI_CR_DMAEN_Msk               (0x1UL << PSSI_CR_DMAEN_Pos)           /*!< 0x40000000 */

+#define PSSI_CR_DMAEN                   PSSI_CR_DMAEN_Msk                      /*!< DMA enable */

+#define PSSI_CR_DERDYCFG_Pos            (18U)

+#define PSSI_CR_DERDYCFG_Msk            (0x7UL << PSSI_CR_DERDYCFG_Pos)        /*!< 0x001C0000 */

+#define PSSI_CR_DERDYCFG                PSSI_CR_DERDYCFG_Msk                   /*!< Data enable and ready configuration */

+#define PSSI_CR_ENABLE_Pos              (14U)

+#define PSSI_CR_ENABLE_Msk              (0x1UL << PSSI_CR_ENABLE_Pos)          /*!< 0x00004000 */

+#define PSSI_CR_ENABLE                  PSSI_CR_ENABLE_Msk                     /*!< PSSI enable */

+#define PSSI_CR_EDM_Pos                 (10U)

+#define PSSI_CR_EDM_Msk                 (0x3UL << PSSI_CR_EDM_Pos)             /*!< 0x00000C00 */

+#define PSSI_CR_EDM                     PSSI_CR_EDM_Msk                        /*!< Extended data mode */

+#define PSSI_CR_RDYPOL_Pos              (8U)

+#define PSSI_CR_RDYPOL_Msk              (0x1UL << PSSI_CR_RDYPOL_Pos)          /*!< 0x00000C00 */

+#define PSSI_CR_RDYPOL                  PSSI_CR_RDYPOL_Msk                     /*!< Ready polarity */

+#define PSSI_CR_DEPOL_Pos               (6U)

+#define PSSI_CR_DEPOL_Msk               (0x1UL << PSSI_CR_DEPOL_Pos)           /*!< 0x00000C00 */

+#define PSSI_CR_DEPOL                   PSSI_CR_DEPOL_Msk                      /*!<  Data enable polarity */

+#define PSSI_CR_CKPOL_Pos               (5U)

+#define PSSI_CR_CKPOL_Msk               (0x1UL << PSSI_CR_CKPOL_Pos)           /*!< 0x00000C00 */

+#define PSSI_CR_CKPOL                   PSSI_CR_CKPOL_Msk                      /*!< Parallel data clock polarity */

+/********************  Bit definition for PSSI_SR register  *******************/

+#define PSSI_SR_RTT1B_Pos               (3U)

+#define PSSI_SR_RTT1B_Msk               (0x1UL << PSSI_SR_RTT1B_Pos)           /*!< 0x00000008 */

+#define PSSI_SR_RTT1B                   PSSI_SR_RTT1B_Msk                      /*!< Ready to transfer one byte */

+#define PSSI_SR_RTT4B_Pos               (2U)

+#define PSSI_SR_RTT4B_Msk               (0x1UL << PSSI_SR_RTT4B_Pos)           /*!< 0x00000004 */

+#define PSSI_SR_RTT4B                   PSSI_SR_RTT4B_Msk                      /*!< Ready to transfer four bytes */

+/********************  Bit definition for PSSI_RIS register  *******************/

+#define PSSI_RIS_OVR_RIS_Pos            (1U)

+#define PSSI_RIS_OVR_RIS_Msk            (0x1UL << PSSI_RIS_OVR_RIS_Pos)        /*!< 0x00000002 */

+#define PSSI_RIS_OVR_RIS                PSSI_RIS_OVR_RIS_Msk                   /*!< Data buffer overrun/underrun raw interrupt status */

+/********************  Bit definition for PSSI_IER register  *******************/

+#define PSSI_IER_OVR_IE_Pos             (1U)

+#define PSSI_IER_OVR_IE_Msk             (0x1UL << PSSI_IER_OVR_IE_Pos)         /*!< 0x00000002 */

+#define PSSI_IER_OVR_IE                 PSSI_IER_OVR_IE_Msk                    /*!< Data buffer overrun/underrun interrupt enable */

+/********************  Bit definition for PSSI_MIS register  *******************/

+#define PSSI_MIS_OVR_MIS_Pos            (1U)

+#define PSSI_MIS_OVR_MIS_Msk            (0x1UL << PSSI_MIS_OVR_MIS_Pos)        /*!< 0x00000002 */

+#define PSSI_MIS_OVR_MIS                PSSI_MIS_OVR_MIS_Msk                   /*!< Data buffer overrun/underrun masked interrupt status */

+/********************  Bit definition for PSSI_ICR register  *******************/

+#define PSSI_ICR_OVR_ISC_Pos            (1U)

+#define PSSI_ICR_OVR_ISC_Msk            (0x1UL << PSSI_ICR_OVR_ISC_Pos)        /*!< 0x00000002 */

+#define PSSI_ICR_OVR_ISC                PSSI_ICR_OVR_ISC_Msk                   /*!< Data buffer overrun/underrun interrupt status clear */

+/********************  Bit definition for PSSI_DR register  *******************/

+#define PSSI_DR_DR_Pos                  (0U)

+#define PSSI_DR_DR_Msk                  (0xFFFFFFFFUL << PSSI_DR_DR_Pos)       /*!< 0xFFFFFFF */

+#define PSSI_DR_DR                      PSSI_DR_DR_Msk                         /*!< Data register  */

+

+/******************************************************************************/

+/*                                                                            */

+/*                              On The Fly Decryption                         */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for OTFDEC_CR register  ******************/

+#define OTFDEC_CR_ENC_Pos                      (0U)

+#define OTFDEC_CR_ENC_Msk                      (0x1UL << OTFDEC_CR_ENC_Pos)                  /*!< 0x00000001 */

+#define OTFDEC_CR_ENC                          OTFDEC_CR_ENC_Msk                             /*!< Encryption mode bit */

+

+/******************  Bit definition for OTFDEC_PRIVCFGR register  ************/

+#define OTFDEC_PRIVCFGR_PRIV_Pos               (0U)

+#define OTFDEC_PRIVCFGR_PRIV_Msk               (0x1UL << OTFDEC_PRIVCFGR_PRIV_Pos)           /*!< 0x00000001 */

+#define OTFDEC_PRIVCFGR_PRIV                   OTFDEC_PRIVCFGR_PRIV_Msk                      /*!< Privileged access protection */

+

+/******************  Bit definition for OTFDEC_REG_CONFIGR register  *********/

+#define OTFDEC_REG_CONFIGR_REG_EN_Pos          (0U)

+#define OTFDEC_REG_CONFIGR_REG_EN_Msk          (0x1UL << OTFDEC_REG_CONFIGR_REG_EN_Pos)      /*!< 0x00000001 */

+#define OTFDEC_REG_CONFIGR_REG_EN              OTFDEC_REG_CONFIGR_REG_EN_Msk                 /*!< Region on-the-fly decryption enable */

+

+#define OTFDEC_REG_CONFIGR_CONFIGLOCK_Pos      (1U)

+#define OTFDEC_REG_CONFIGR_CONFIGLOCK_Msk      (0x1UL << OTFDEC_REG_CONFIGR_CONFIGLOCK_Pos)  /*!< 0x00000002 */

+#define OTFDEC_REG_CONFIGR_CONFIGLOCK          OTFDEC_REG_CONFIGR_CONFIGLOCK_Msk             /*!< Region config lock */

+

+#define OTFDEC_REG_CONFIGR_KEYLOCK_Pos         (2U)

+#define OTFDEC_REG_CONFIGR_KEYLOCK_Msk         (0x1UL << OTFDEC_REG_CONFIGR_KEYLOCK_Pos)     /*!< 0x00000004 */

+#define OTFDEC_REG_CONFIGR_KEYLOCK             OTFDEC_REG_CONFIGR_KEYLOCK_Msk                /*!< Region key lock */

+

+#define OTFDEC_REG_CONFIGR_MODE_Pos            (4U)

+#define OTFDEC_REG_CONFIGR_MODE_Msk            (0x3UL << OTFDEC_REG_CONFIGR_MODE_Pos)        /*!< 0x00000030 */

+#define OTFDEC_REG_CONFIGR_MODE                OTFDEC_REG_CONFIGR_MODE_Msk                   /*!< Region operating mode */

+#define OTFDEC_REG_CONFIGR_MODE_0              (0x1UL << OTFDEC_REG_CONFIGR_MODE_Pos)        /*!< 0x00000010 */

+#define OTFDEC_REG_CONFIGR_MODE_1              (0x2UL << OTFDEC_REG_CONFIGR_MODE_Pos)        /*!< 0x00000020 */

+

+#define OTFDEC_REG_CONFIGR_KEYCRC_Pos          (8U)

+#define OTFDEC_REG_CONFIGR_KEYCRC_Msk          (0xFFUL << OTFDEC_REG_CONFIGR_KEYCRC_Pos)     /*!< 0x0000FF00 */

+#define OTFDEC_REG_CONFIGR_KEYCRC              OTFDEC_REG_CONFIGR_KEYCRC_Msk                 /*!< Region key 8-bit CRC */

+

+#define OTFDEC_REG_CONFIGR_VERSION_Pos         (16U)

+#define OTFDEC_REG_CONFIGR_VERSION_Msk         (0xFFFFUL << OTFDEC_REG_CONFIGR_VERSION_Pos)  /*!< 0xFFFF0000 */

+#define OTFDEC_REG_CONFIGR_VERSION             OTFDEC_REG_CONFIGR_VERSION_Msk                /*!< Region firmware version */

+

+/******************  Bit definition for OTFDEC_REG_START_ADDR register  ******/

+#define OTFDEC_REG_START_ADDR_Pos              (0U)

+#define OTFDEC_REG_START_ADDR_Msk              (0xFFFFFFFFUL << OTFDEC_REG_START_ADDR_Pos)   /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_START_ADDR                  OTFDEC_REG_START_ADDR_Msk                     /*!< Region AHB start address */

+

+/******************  Bit definition for OTFDEC_REG_END_ADDR register  ********/

+#define OTFDEC_REG_END_ADDR_Pos                (0U)

+#define OTFDEC_REG_END_ADDR_Msk                (0xFFFFFFFFUL << OTFDEC_REG_END_ADDR_Pos)     /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_END_ADDR                    OTFDEC_REG_END_ADDR_Msk                       /*!< Region AHB end address */

+

+/******************  Bit definition for OTFDEC_REG_NONCER0 register  *********/

+#define OTFDEC_REG_NONCER0_Pos                 (0U)

+#define OTFDEC_REG_NONCER0_Msk                 (0xFFFFFFFFUL << OTFDEC_REG_NONCER0_Pos)      /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_NONCER0                     OTFDEC_REG_NONCER0_Msk                        /*!< Region Nonce Register (LSB nonce[31:0]) */

+

+/******************  Bit definition for OTFDEC_REG_NONCER1 register  *********/

+#define OTFDEC_REG_NONCER1_Pos                 (0U)

+#define OTFDEC_REG_NONCER1_Msk                 (0xFFFFFFFFUL << OTFDEC_REG_NONCER1_Pos)      /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_NONCER1                     OTFDEC_REG_NONCER1_Msk                        /*!< Region Nonce Register (MSB nonce[63:32]) */

+

+/******************  Bit definition for OTFDEC_REG_KEYR0 register  ***********/

+#define OTFDEC_REG_KEYR0_Pos                   (0U)

+#define OTFDEC_REG_KEYR0_Msk                   (0xFFFFFFFFUL << OTFDEC_REG_KEYR0_Pos)        /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_KEYR0                       OTFDEC_REG_KEYR0_Msk                          /*!< Region Key Register (LSB key[31:0]) */

+

+/******************  Bit definition for OTFDEC_REG_KEYR1 register  ***********/

+#define OTFDEC_REG_KEYR1_Pos                   (0U)

+#define OTFDEC_REG_KEYR1_Msk                   (0xFFFFFFFFUL << OTFDEC_REG_KEYR1_Pos)        /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_KEYR1                       OTFDEC_REG_KEYR1_Msk                          /*!< Region Key Register (key[63:32]) */

+

+/******************  Bit definition for OTFDEC_REG_KEYR2 register  ***********/

+#define OTFDEC_REG_KEYR2_Pos                   (0U)

+#define OTFDEC_REG_KEYR2_Msk                   (0xFFFFFFFFUL << OTFDEC_REG_KEYR2_Pos)        /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_KEYR2                       OTFDEC_REG_KEYR2_Msk                          /*!< Region Key Register (key[95:64]) */

+

+/******************  Bit definition for OTFDEC_REG_KEYR3 register  ***********/

+#define OTFDEC_REG_KEYR3_Pos                   (0U)

+#define OTFDEC_REG_KEYR3_Msk                   (0xFFFFFFFFUL << OTFDEC_REG_KEYR3_Pos)        /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_KEYR3                       OTFDEC_REG_KEYR3_Msk                          /*!< Region Key Register (key[127:96]) */

+

+/******************  Bit definition for OTFDEC_ISR register  *****************/

+#define OTFDEC_ISR_SEIF_Pos                    (0U)

+#define OTFDEC_ISR_SEIF_Msk                    (0x1UL << OTFDEC_ISR_SEIF_Pos)                /*!< 0x00000001 */

+#define OTFDEC_ISR_SEIF                        OTFDEC_ISR_SEIF_Msk                           /*!< Security Error Interrupt Flag status bit before enable (mask) */

+

+#define OTFDEC_ISR_XONEIF_Pos                  (1U)

+#define OTFDEC_ISR_XONEIF_Msk                  (0x1UL << OTFDEC_ISR_XONEIF_Pos)              /*!< 0x00000002 */

+#define OTFDEC_ISR_XONEIF                      OTFDEC_ISR_XONEIF_Msk                         /*!< Execute-only Error Interrupt Flag status bit before enable (mask) */

+

+#define OTFDEC_ISR_KEIF_Pos                    (2U)

+#define OTFDEC_ISR_KEIF_Msk                    (0x1UL << OTFDEC_ISR_KEIF_Pos)                /*!< 0x00000004 */

+#define OTFDEC_ISR_KEIF                        OTFDEC_ISR_KEIF_Msk                           /*!< Key Error Interrupt Flag status bit before enable (mask) */

+

+/******************  Bit definition  for OTFDEC_ICR register  *****************/

+#define OTFDEC_ICR_SEIF_Pos                    (0U)

+#define OTFDEC_ICR_SEIF_Msk                    (0x1UL << OTFDEC_ICR_SEIF_Pos)                /*!< 0x00000001 */

+#define OTFDEC_ICR_SEIF                        OTFDEC_ICR_SEIF_Msk                           /*!< Security Error Interrupt Flag clear bit */

+

+#define OTFDEC_ICR_XONEIF_Pos                  (1U)

+#define OTFDEC_ICR_XONEIF_Msk                  (0x1UL << OTFDEC_ICR_XONEIF_Pos)              /*!< 0x00000002 */

+#define OTFDEC_ICR_XONEIF                      OTFDEC_ICR_XONEIF_Msk                         /*!< Execute-only Error Interrupt Flag clear bit */

+

+#define OTFDEC_ICR_KEIF_Pos                    (2U)

+#define OTFDEC_ICR_KEIF_Msk                    (0x1UL << OTFDEC_ICR_KEIF_Pos)                /*!< 0x00000004 */

+#define OTFDEC_ICR_KEIF                        OTFDEC_ICR_KEIF_Msk                           /*!< Key Error Interrupt Flag clear bit */

+

+/******************  Bit definition for OTFDEC_IER register  *****************/

+#define OTFDEC_IER_SEIE_Pos                    (0U)

+#define OTFDEC_IER_SEIE_Msk                    (0x1UL << OTFDEC_IER_SEIE_Pos)                /*!< 0x00000001 */

+#define OTFDEC_IER_SEIE                        OTFDEC_IER_SEIE_Msk                           /*!< Security Error Interrupt Enable bit */

+

+#define OTFDEC_IER_XONEIE_Pos                  (1U)

+#define OTFDEC_IER_XONEIE_Msk                  (0x1UL << OTFDEC_IER_XONEIE_Pos)              /*!< 0x00000002 */

+#define OTFDEC_IER_XONEIE                      OTFDEC_IER_XONEIE_Msk                         /*!< Execute-only Error Interrupt Enable bit */

+

+#define OTFDEC_IER_KEIE_Pos                    (2U)

+#define OTFDEC_IER_KEIE_Msk                    (0x1UL << OTFDEC_IER_KEIE_Pos)                /*!< 0x00000004 */

+#define OTFDEC_IER_KEIE                        OTFDEC_IER_KEIE_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                             Power Control                                  */

+/*                                                                            */

+/******************************************************************************/

+/*************************  NUMBER OF POWER DOMAINS  **************************/

+#define POWER_DOMAINS_NUMBER           2U                                      /*!< 2 Domains */

+

+/********************  Bit definition for PWR_CR1 register  *******************/

+#define PWR_CR1_SRDRAMSO_Pos           (27U)

+#define PWR_CR1_SRDRAMSO_Msk           (0x1UL << PWR_CR1_SRDRAMSO_Pos)         /*!< 0x08000000 */

+#define PWR_CR1_SRDRAMSO               PWR_CR1_SRDRAMSO_Msk                    /*!< SmartRun Domain AHB Memory Shut-Off in DStop/DStop2 Low-Power Mode */

+#define PWR_CR1_HSITFSO_Pos            (26U)

+#define PWR_CR1_HSITFSO_Msk            (0x1UL << PWR_CR1_HSITFSO_Pos)          /*!< 0x04000000 */

+#define PWR_CR1_HSITFSO                PWR_CR1_HSITFSO_Msk                     /*!< High-Speed Interfaces USB and FDCAN Memories Shut-off in DStop/DStop2 Mode */

+#define PWR_CR1_GFXSO_Pos              (25U)

+#define PWR_CR1_GFXSO_Msk              (0x1UL << PWR_CR1_GFXSO_Pos)            /*!< 0x02000000 */

+#define PWR_CR1_GFXSO                  PWR_CR1_GFXSO_Msk                       /*!< GFXMMU and JPEG Memories Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_ITCMSO_Pos             (24U)

+#define PWR_CR1_ITCMSO_Msk             (0x1UL << PWR_CR1_ITCMSO_Pos)           /*!< 0x01000000 */

+#define PWR_CR1_ITCMSO                 PWR_CR1_ITCMSO_Msk                      /*!< Instruction TCM and ETM Memories Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_AHBRAM2SO_Pos          (23U)

+#define PWR_CR1_AHBRAM2SO_Msk          (0x1UL << PWR_CR1_AHBRAM2SO_Pos)        /*!< 0x00800000 */

+#define PWR_CR1_AHBRAM2SO              PWR_CR1_AHBRAM2SO_Msk                   /*!< AHB RAM2 Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_AHBRAM1SO_Pos          (22U)

+#define PWR_CR1_AHBRAM1SO_Msk          (0x1UL << PWR_CR1_AHBRAM1SO_Pos)        /*!< 0x00400000 */

+#define PWR_CR1_AHBRAM1SO              PWR_CR1_AHBRAM1SO_Msk                   /*!< AHB RAM1 Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_AXIRAM3SO_Pos          (21U)

+#define PWR_CR1_AXIRAM3SO_Msk          (0x1UL << PWR_CR1_AXIRAM3SO_Pos)        /*!< 0x00200000 */

+#define PWR_CR1_AXIRAM3SO              PWR_CR1_AXIRAM3SO_Msk                   /*!< AXI RAM3 Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_AXIRAM2SO_Pos          (20U)

+#define PWR_CR1_AXIRAM2SO_Msk          (0x1UL << PWR_CR1_AXIRAM2SO_Pos)        /*!< 0x00100000 */

+#define PWR_CR1_AXIRAM2SO              PWR_CR1_AXIRAM2SO_Msk                   /*!< AXI RAM2 Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_AXIRAM1SO_Pos          (19U)

+#define PWR_CR1_AXIRAM1SO_Msk          (0x1UL << PWR_CR1_AXIRAM1SO_Pos)        /*!< 0x00080000 */

+#define PWR_CR1_AXIRAM1SO              PWR_CR1_AXIRAM1SO_Msk                   /*!< AXI RAM1 Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_ALS_Pos                (17U)

+#define PWR_CR1_ALS_Msk                (0x3UL << PWR_CR1_ALS_Pos)              /*!< 0x00060000 */

+#define PWR_CR1_ALS                    PWR_CR1_ALS_Msk                         /*!< Analog Voltage Detector level selection */

+#define PWR_CR1_ALS_0                  (0x1UL << PWR_CR1_ALS_Pos)              /*!< 0x00020000 */

+#define PWR_CR1_ALS_1                  (0x2UL << PWR_CR1_ALS_Pos)              /*!< 0x00040000 */

+#define PWR_CR1_AVDEN_Pos              (16U)

+#define PWR_CR1_AVDEN_Msk              (0x1UL << PWR_CR1_AVDEN_Pos)            /*!< 0x00010000 */

+#define PWR_CR1_AVDEN                  PWR_CR1_AVDEN_Msk                       /*!< Analog Voltage Detector Enable */

+#define PWR_CR1_SVOS_Pos               (14U)

+#define PWR_CR1_SVOS_Msk               (0x3UL << PWR_CR1_SVOS_Pos)             /*!< 0x0000C000 */

+#define PWR_CR1_SVOS                   PWR_CR1_SVOS_Msk                        /*!< System STOP mode Voltage Scaling selection */

+#define PWR_CR1_SVOS_0                 (0x1UL << PWR_CR1_SVOS_Pos)             /*!< 0x00004000 */

+#define PWR_CR1_SVOS_1                 (0x2UL << PWR_CR1_SVOS_Pos)             /*!< 0x00008000 */

+#define PWR_CR1_AVD_READY_Pos          (13U)

+#define PWR_CR1_AVD_READY_Msk          (0x1UL << PWR_CR1_AVD_READY_Pos)        /*!< 0x00002000 */

+#define PWR_CR1_AVD_READY              PWR_CR1_AVD_READY_Msk                   /*!< Analog Voltage Ready. */

+#define PWR_CR1_BOOSTE_Pos             (12U)

+#define PWR_CR1_BOOSTE_Msk             (0x1UL << PWR_CR1_BOOSTE_Pos)           /*!< 0x00001000 */

+#define PWR_CR1_BOOSTE                 PWR_CR1_BOOSTE_Msk                      /*!< Analog Switch VBoost control */

+#define PWR_CR1_FLPS_Pos               (9U)

+#define PWR_CR1_FLPS_Msk               (0x1UL << PWR_CR1_FLPS_Pos)             /*!< 0x00000200 */

+#define PWR_CR1_FLPS                   PWR_CR1_FLPS_Msk                        /*!< Flash low power mode in DSTOP */

+#define PWR_CR1_DBP_Pos                (8U)

+#define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */

+#define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable Back-up domain Protection */

+#define PWR_CR1_PLS_Pos                (5U)

+#define PWR_CR1_PLS_Msk                (0x7UL << PWR_CR1_PLS_Pos)              /*!< 0x000000E0 */

+#define PWR_CR1_PLS                    PWR_CR1_PLS_Msk                         /*!< Programmable Voltage Detector level selection */

+#define PWR_CR1_PLS_0                  (0x1UL << PWR_CR1_PLS_Pos)              /*!< 0x00000020 */

+#define PWR_CR1_PLS_1                  (0x2UL << PWR_CR1_PLS_Pos)              /*!< 0x00000040 */

+#define PWR_CR1_PLS_2                  (0x4UL << PWR_CR1_PLS_Pos)              /*!< 0x00000080 */

+#define PWR_CR1_PVDEN_Pos              (4U)

+#define PWR_CR1_PVDEN_Msk              (0x1UL << PWR_CR1_PVDEN_Pos)            /*!< 0x00000010 */

+#define PWR_CR1_PVDEN                  PWR_CR1_PVDEN_Msk                       /*!< Programmable Voltage detector enable */

+#define PWR_CR1_LPDS_Pos               (0U)

+#define PWR_CR1_LPDS_Msk               (0x1UL << PWR_CR1_LPDS_Pos)             /*!< 0x00000001 */

+#define PWR_CR1_LPDS                   PWR_CR1_LPDS_Msk                        /*!< Low Power Deepsleep with SVOS3 */

+

+/*!< PVD level configuration */

+#define PWR_CR1_PLS_LEV0               (0UL)                                   /*!< PVD level 0 */

+#define PWR_CR1_PLS_LEV1_Pos           (5U)

+#define PWR_CR1_PLS_LEV1_Msk           (0x1UL << PWR_CR1_PLS_LEV1_Pos)         /*!< 0x00000020 */

+#define PWR_CR1_PLS_LEV1               PWR_CR1_PLS_LEV1_Msk                    /*!< PVD level 1 */

+#define PWR_CR1_PLS_LEV2_Pos           (6U)

+#define PWR_CR1_PLS_LEV2_Msk           (0x1UL << PWR_CR1_PLS_LEV2_Pos)         /*!< 0x00000040 */

+#define PWR_CR1_PLS_LEV2               PWR_CR1_PLS_LEV2_Msk                    /*!< PVD level 2 */

+#define PWR_CR1_PLS_LEV3_Pos           (5U)

+#define PWR_CR1_PLS_LEV3_Msk           (0x3UL << PWR_CR1_PLS_LEV3_Pos)         /*!< 0x00000060 */

+#define PWR_CR1_PLS_LEV3               PWR_CR1_PLS_LEV3_Msk                    /*!< PVD level 3 */

+#define PWR_CR1_PLS_LEV4_Pos           (7U)

+#define PWR_CR1_PLS_LEV4_Msk           (0x1UL << PWR_CR1_PLS_LEV4_Pos)         /*!< 0x00000080 */

+#define PWR_CR1_PLS_LEV4               PWR_CR1_PLS_LEV4_Msk                    /*!< PVD level 4 */

+#define PWR_CR1_PLS_LEV5_Pos           (5U)

+#define PWR_CR1_PLS_LEV5_Msk           (0x5UL << PWR_CR1_PLS_LEV5_Pos)         /*!< 0x000000A0 */

+#define PWR_CR1_PLS_LEV5               PWR_CR1_PLS_LEV5_Msk                    /*!< PVD level 5 */

+#define PWR_CR1_PLS_LEV6_Pos           (6U)

+#define PWR_CR1_PLS_LEV6_Msk           (0x3UL << PWR_CR1_PLS_LEV6_Pos)         /*!< 0x000000C0 */

+#define PWR_CR1_PLS_LEV6               PWR_CR1_PLS_LEV6_Msk                    /*!< PVD level 6 */

+#define PWR_CR1_PLS_LEV7_Pos           (5U)

+#define PWR_CR1_PLS_LEV7_Msk           (0x7UL << PWR_CR1_PLS_LEV7_Pos)         /*!< 0x000000E0 */

+#define PWR_CR1_PLS_LEV7               PWR_CR1_PLS_LEV7_Msk                    /*!< PVD level 7 */

+

+/*!< AVD level configuration */

+#define PWR_CR1_ALS_LEV0               (0UL)                                   /*!< AVD level 0 */

+#define PWR_CR1_ALS_LEV1_Pos           (17U)

+#define PWR_CR1_ALS_LEV1_Msk           (0x1UL << PWR_CR1_ALS_LEV1_Pos)         /*!< 0x00020000 */

+#define PWR_CR1_ALS_LEV1               PWR_CR1_ALS_LEV1_Msk                    /*!< AVD level 1 */

+#define PWR_CR1_ALS_LEV2_Pos           (18U)

+#define PWR_CR1_ALS_LEV2_Msk           (0x1UL << PWR_CR1_ALS_LEV2_Pos)         /*!< 0x00040000 */

+#define PWR_CR1_ALS_LEV2               PWR_CR1_ALS_LEV2_Msk                    /*!< AVD level 2 */

+#define PWR_CR1_ALS_LEV3_Pos           (17U)

+#define PWR_CR1_ALS_LEV3_Msk           (0x3UL << PWR_CR1_ALS_LEV3_Pos)         /*!< 0x00060000 */

+#define PWR_CR1_ALS_LEV3               PWR_CR1_ALS_LEV3_Msk                    /*!< AVD level 3 */

+

+/********************  Bit definition for PWR_CSR1 register  ******************/

+#define PWR_CSR1_MMCVDO_Pos            (17U)

+#define PWR_CSR1_MMCVDO_Msk            (0x1UL << PWR_CSR1_MMCVDO_Pos)          /*!< 0x00020000                        */

+#define PWR_CSR1_MMCVDO                PWR_CSR1_MMCVDO_Msk                     /*!< voltage detector output on VDDMMC */

+#define PWR_CSR1_AVDO_Pos              (16U)

+#define PWR_CSR1_AVDO_Msk              (0x1UL << PWR_CSR1_AVDO_Pos)            /*!< 0x00010000 */

+#define PWR_CSR1_AVDO                  PWR_CSR1_AVDO_Msk                       /*!< Analog Voltage Detect Output */

+#define PWR_CSR1_ACTVOS_Pos            (14U)

+#define PWR_CSR1_ACTVOS_Msk            (0x3UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x0000C000 */

+#define PWR_CSR1_ACTVOS                PWR_CSR1_ACTVOS_Msk                     /*!< Current actual used VOS for VDD11 Voltage Scaling */

+#define PWR_CSR1_ACTVOS_0              (0x1UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00004000 */

+#define PWR_CSR1_ACTVOS_1              (0x2UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00008000 */

+#define PWR_CSR1_ACTVOSRDY_Pos         (13U)

+#define PWR_CSR1_ACTVOSRDY_Msk         (0x1UL << PWR_CSR1_ACTVOSRDY_Pos)       /*!< 0x00002000 */

+#define PWR_CSR1_ACTVOSRDY             PWR_CSR1_ACTVOSRDY_Msk                  /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling  */

+#define PWR_CSR1_PVDO_Pos              (4U)

+#define PWR_CSR1_PVDO_Msk              (0x1UL << PWR_CSR1_PVDO_Pos)            /*!< 0x00000010 */

+#define PWR_CSR1_PVDO                  PWR_CSR1_PVDO_Msk                       /*!< Programmable Voltage Detect Output */

+

+/********************  Bit definition for PWR_CR2 register  *******************/

+#define PWR_CR2_TEMPH_Pos              (23U)

+#define PWR_CR2_TEMPH_Msk              (0x1UL << PWR_CR2_TEMPH_Pos)            /*!< 0x00800000 */

+#define PWR_CR2_TEMPH                  PWR_CR2_TEMPH_Msk                       /*!< Monitored temperature level above high threshold */

+#define PWR_CR2_TEMPL_Pos              (22U)

+#define PWR_CR2_TEMPL_Msk              (0x1UL << PWR_CR2_TEMPL_Pos)            /*!< 0x00400000 */

+#define PWR_CR2_TEMPL                  PWR_CR2_TEMPL_Msk                       /*!< Monitored temperature level above low threshold */

+#define PWR_CR2_VBATH_Pos              (21U)

+#define PWR_CR2_VBATH_Msk              (0x1UL << PWR_CR2_VBATH_Pos)            /*!< 0x00200000 */

+#define PWR_CR2_VBATH                  PWR_CR2_VBATH_Msk                       /*!< Monitored VBAT level above high threshold */

+#define PWR_CR2_VBATL_Pos              (20U)

+#define PWR_CR2_VBATL_Msk              (0x1UL << PWR_CR2_VBATL_Pos)            /*!< 0x00100000 */

+#define PWR_CR2_VBATL                  PWR_CR2_VBATL_Msk                       /*!< Monitored VBAT level above low threshold */

+#define PWR_CR2_BRRDY_Pos              (16U)

+#define PWR_CR2_BRRDY_Msk              (0x1UL << PWR_CR2_BRRDY_Pos)            /*!< 0x00010000 */

+#define PWR_CR2_BRRDY                  PWR_CR2_BRRDY_Msk                       /*!< Backup regulator ready */

+#define PWR_CR2_MONEN_Pos              (4U)

+#define PWR_CR2_MONEN_Msk              (0x1UL << PWR_CR2_MONEN_Pos)            /*!< 0x00000010 */

+#define PWR_CR2_MONEN                  PWR_CR2_MONEN_Msk                       /*!< VBAT and temperature monitoring enable */

+#define PWR_CR2_BREN_Pos               (0U)

+#define PWR_CR2_BREN_Msk               (0x1UL << PWR_CR2_BREN_Pos)             /*!< 0x00000001 */

+#define PWR_CR2_BREN                   PWR_CR2_BREN_Msk                        /*!< Backup regulator enable */

+

+/********************  Bit definition for PWR_CR3 register  *******************/

+#define PWR_CR3_USB33RDY_Pos           (26U)

+#define PWR_CR3_USB33RDY_Msk           (0x1UL << PWR_CR3_USB33RDY_Pos)         /*!< 0x04000000 */

+#define PWR_CR3_USB33RDY               PWR_CR3_USB33RDY_Msk                    /*!< USB supply ready */

+#define PWR_CR3_USBREGEN_Pos           (25U)

+#define PWR_CR3_USBREGEN_Msk           (0x1UL << PWR_CR3_USBREGEN_Pos)         /*!< 0x02000000 */

+#define PWR_CR3_USBREGEN               PWR_CR3_USBREGEN_Msk                    /*!< USB regulator enable */

+#define PWR_CR3_USB33DEN_Pos           (24U)

+#define PWR_CR3_USB33DEN_Msk           (0x1UL << PWR_CR3_USB33DEN_Pos)         /*!< 0x01000000 */

+#define PWR_CR3_USB33DEN               PWR_CR3_USB33DEN_Msk                    /*!< VDD33_USB voltage level detector enable */

+#define PWR_CR3_VBRS_Pos               (9U)

+#define PWR_CR3_VBRS_Msk               (0x1UL << PWR_CR3_VBRS_Pos)             /*!< 0x00000200 */

+#define PWR_CR3_VBRS                   PWR_CR3_VBRS_Msk                        /*!< VBAT charging resistor selection */

+#define PWR_CR3_VBE_Pos                (8U)

+#define PWR_CR3_VBE_Msk                (0x1UL << PWR_CR3_VBE_Pos)              /*!< 0x00000100 */

+#define PWR_CR3_VBE                    PWR_CR3_VBE_Msk                         /*!< VBAT charging enable */

+#define PWR_CR3_SCUEN_Pos              (2U)

+#define PWR_CR3_SCUEN_Msk              (0x1UL << PWR_CR3_SCUEN_Pos)            /*!< 0x00000004 */

+#define PWR_CR3_SCUEN                  PWR_CR3_SCUEN_Msk                       /*!< Supply configuration update enable */

+#define PWR_CR3_LDOEN_Pos              (1U)

+#define PWR_CR3_LDOEN_Msk              (0x1UL << PWR_CR3_LDOEN_Pos)            /*!< 0x00000002 */

+#define PWR_CR3_LDOEN                  PWR_CR3_LDOEN_Msk                       /*!< Low Drop Output regulator enable */

+#define PWR_CR3_BYPASS_Pos             (0U)

+#define PWR_CR3_BYPASS_Msk             (0x1UL << PWR_CR3_BYPASS_Pos)           /*!< 0x00000001 */

+#define PWR_CR3_BYPASS                 PWR_CR3_BYPASS_Msk                      /*!< Power Management Unit bypass */

+

+/********************  Bit definition for PWR_CPUCR register  *****************/

+#define PWR_CPUCR_RUN_SRD_Pos          (11U)

+#define PWR_CPUCR_RUN_SRD_Msk          (0x1UL << PWR_CPUCR_RUN_SRD_Pos)        /*!< 0x00000800 */

+#define PWR_CPUCR_RUN_SRD              PWR_CPUCR_RUN_SRD_Msk                   /*!< Keep system SRD domain in RUN mode regardless of the CPU sub-systems modes */

+#define PWR_CPUCR_CSSF_Pos             (9U)

+#define PWR_CPUCR_CSSF_Msk             (0x1UL << PWR_CPUCR_CSSF_Pos)           /*!< 0x00000200 */

+#define PWR_CPUCR_CSSF                 PWR_CPUCR_CSSF_Msk                      /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */

+#define PWR_CPUCR_SBF_Pos              (6U)

+#define PWR_CPUCR_SBF_Msk              (0x1UL << PWR_CPUCR_SBF_Pos)            /*!< 0x00000040 */

+#define PWR_CPUCR_SBF                  PWR_CPUCR_SBF_Msk                       /*!< System STANDBY Flag */

+#define PWR_CPUCR_STOPF_Pos            (5U)

+#define PWR_CPUCR_STOPF_Msk            (0x1UL << PWR_CPUCR_STOPF_Pos)          /*!< 0x00000020 */

+#define PWR_CPUCR_STOPF                PWR_CPUCR_STOPF_Msk                     /*!< STOP Flag */

+#define PWR_CPUCR_PDDS_SRD_Pos         (2U)

+#define PWR_CPUCR_PDDS_SRD_Msk         (0x1UL << PWR_CPUCR_PDDS_SRD_Pos)       /*!< 0x00000004 */

+#define PWR_CPUCR_PDDS_SRD             PWR_CPUCR_PDDS_SRD_Msk                  /*!< System SRD domain Power Down Deepsleep */

+#define PWR_CPUCR_RETDS_CD_Pos         (0U)

+#define PWR_CPUCR_RETDS_CD_Msk         (0x1UL << PWR_CPUCR_RETDS_CD_Pos)       /*!< 0x00000001 */

+#define PWR_CPUCR_RETDS_CD             PWR_CPUCR_RETDS_CD_Msk                  /*!< CD domain Power Down Deepsleep selection */

+/********************  Bit definition for PWR_SRDCR register  *****************/

+#define PWR_SRDCR_VOS_Pos              (14U)

+#define PWR_SRDCR_VOS_Msk              (0x3UL << PWR_SRDCR_VOS_Pos)             /*!< 0x0000C000 */

+#define PWR_SRDCR_VOS                  PWR_SRDCR_VOS_Msk                        /*!< Voltage Scaling selection according performance */

+#define PWR_SRDCR_VOS_0                (0x1UL << PWR_SRDCR_VOS_Pos)             /*!< 0x00004000 */

+#define PWR_SRDCR_VOS_1                (0x2UL << PWR_SRDCR_VOS_Pos)             /*!< 0x00008000 */

+#define PWR_SRDCR_VOSRDY_Pos           (13U)

+#define PWR_SRDCR_VOSRDY_Msk           (0x1UL << PWR_SRDCR_VOSRDY_Pos)          /*!< 0x00002000 */

+#define PWR_SRDCR_VOSRDY               PWR_SRDCR_VOSRDY_Msk                     /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */

+/******************  Bit definition for PWR_WKUPCR register  ******************/

+#define PWR_WKUPCR_WKUPC6_Pos          (5U)

+#define PWR_WKUPCR_WKUPC6_Msk          (0x1UL << PWR_WKUPCR_WKUPC6_Pos)        /*!< 0x00000020 */

+#define PWR_WKUPCR_WKUPC6              PWR_WKUPCR_WKUPC6_Msk                   /*!< Clear Wakeup Pin Flag 6 */

+#define PWR_WKUPCR_WKUPC5_Pos          (4U)

+#define PWR_WKUPCR_WKUPC5_Msk          (0x1UL << PWR_WKUPCR_WKUPC5_Pos)        /*!< 0x00000010 */

+#define PWR_WKUPCR_WKUPC5              PWR_WKUPCR_WKUPC5_Msk                   /*!< Clear Wakeup Pin Flag 5 */

+#define PWR_WKUPCR_WKUPC4_Pos          (3U)

+#define PWR_WKUPCR_WKUPC4_Msk          (0x1UL << PWR_WKUPCR_WKUPC4_Pos)        /*!< 0x00000008 */

+#define PWR_WKUPCR_WKUPC4              PWR_WKUPCR_WKUPC4_Msk                   /*!< Clear Wakeup Pin Flag 4 */

+#define PWR_WKUPCR_WKUPC3_Pos          (2U)

+#define PWR_WKUPCR_WKUPC3_Msk          (0x1UL << PWR_WKUPCR_WKUPC3_Pos)        /*!< 0x00000004 */

+#define PWR_WKUPCR_WKUPC3              PWR_WKUPCR_WKUPC3_Msk                   /*!< Clear Wakeup Pin Flag 3 */

+#define PWR_WKUPCR_WKUPC2_Pos          (1U)

+#define PWR_WKUPCR_WKUPC2_Msk          (0x1UL << PWR_WKUPCR_WKUPC2_Pos)        /*!< 0x00000002 */

+#define PWR_WKUPCR_WKUPC2              PWR_WKUPCR_WKUPC2_Msk                   /*!< Clear Wakeup Pin Flag 2 */

+#define PWR_WKUPCR_WKUPC1_Pos          (0U)

+#define PWR_WKUPCR_WKUPC1_Msk          (0x1UL << PWR_WKUPCR_WKUPC1_Pos)        /*!< 0x00000001 */

+#define PWR_WKUPCR_WKUPC1              PWR_WKUPCR_WKUPC1_Msk                   /*!< Clear Wakeup Pin Flag 1 */

+

+/********************  Bit definition for PWR_WKUPFR register  ****************/

+#define PWR_WKUPFR_WKUPF6_Pos          (5U)

+#define PWR_WKUPFR_WKUPF6_Msk          (0x1UL << PWR_WKUPFR_WKUPF6_Pos)        /*!< 0x00000020 */

+#define PWR_WKUPFR_WKUPF6              PWR_WKUPFR_WKUPF6_Msk                   /*!< Wakeup Pin Flag 6 */

+#define PWR_WKUPFR_WKUPF5_Pos          (4U)

+#define PWR_WKUPFR_WKUPF5_Msk          (0x1UL << PWR_WKUPFR_WKUPF5_Pos)        /*!< 0x00000010 */

+#define PWR_WKUPFR_WKUPF5              PWR_WKUPFR_WKUPF5_Msk                   /*!< Wakeup Pin Flag 5 */

+#define PWR_WKUPFR_WKUPF4_Pos          (3U)

+#define PWR_WKUPFR_WKUPF4_Msk          (0x1UL << PWR_WKUPFR_WKUPF4_Pos)        /*!< 0x00000008 */

+#define PWR_WKUPFR_WKUPF4              PWR_WKUPFR_WKUPF4_Msk                   /*!< Wakeup Pin Flag 4 */

+#define PWR_WKUPFR_WKUPF3_Pos          (2U)

+#define PWR_WKUPFR_WKUPF3_Msk          (0x1UL << PWR_WKUPFR_WKUPF3_Pos)        /*!< 0x00000004 */

+#define PWR_WKUPFR_WKUPF3              PWR_WKUPFR_WKUPF3_Msk                   /*!< Wakeup Pin Flag 3 */

+#define PWR_WKUPFR_WKUPF2_Pos          (1U)

+#define PWR_WKUPFR_WKUPF2_Msk          (0x1UL << PWR_WKUPFR_WKUPF2_Pos)        /*!< 0x00000002 */

+#define PWR_WKUPFR_WKUPF2              PWR_WKUPFR_WKUPF2_Msk                   /*!< Wakeup Pin Flag 2 */

+#define PWR_WKUPFR_WKUPF1_Pos          (0U)

+#define PWR_WKUPFR_WKUPF1_Msk          (0x1UL << PWR_WKUPFR_WKUPF1_Pos)        /*!< 0x00000001 */

+#define PWR_WKUPFR_WKUPF1              PWR_WKUPFR_WKUPF1_Msk                   /*!< Wakeup Pin Flag 1 */

+

+/******************  Bit definition for PWR_WKUPEPR register  *****************/

+#define PWR_WKUPEPR_WKUPPUPD6_Pos      (26U)

+#define PWR_WKUPEPR_WKUPPUPD6_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x0C000000 */

+#define PWR_WKUPEPR_WKUPPUPD6          PWR_WKUPEPR_WKUPPUPD6_Msk               /*!< Wakeup Pin pull configuration for WKUP6 */

+#define PWR_WKUPEPR_WKUPPUPD6_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x04000000 */

+#define PWR_WKUPEPR_WKUPPUPD6_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x08000000 */

+#define PWR_WKUPEPR_WKUPPUPD5_Pos      (24U)

+#define PWR_WKUPEPR_WKUPPUPD5_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x03000000 */

+#define PWR_WKUPEPR_WKUPPUPD5          PWR_WKUPEPR_WKUPPUPD5_Msk               /*!< Wakeup Pin pull configuration for WKUP5 */

+#define PWR_WKUPEPR_WKUPPUPD5_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x01000000 */

+#define PWR_WKUPEPR_WKUPPUPD5_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x02000000 */

+#define PWR_WKUPEPR_WKUPPUPD4_Pos      (22U)

+#define PWR_WKUPEPR_WKUPPUPD4_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00C00000 */

+#define PWR_WKUPEPR_WKUPPUPD4          PWR_WKUPEPR_WKUPPUPD4_Msk               /*!< Wakeup Pin pull configuration for WKUP4 */

+#define PWR_WKUPEPR_WKUPPUPD4_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00400000 */

+#define PWR_WKUPEPR_WKUPPUPD4_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00800000 */

+#define PWR_WKUPEPR_WKUPPUPD3_Pos      (20U)

+#define PWR_WKUPEPR_WKUPPUPD3_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00300000 */

+#define PWR_WKUPEPR_WKUPPUPD3          PWR_WKUPEPR_WKUPPUPD3_Msk               /*!< Wakeup Pin pull configuration for WKUP3 */

+#define PWR_WKUPEPR_WKUPPUPD3_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00100000 */

+#define PWR_WKUPEPR_WKUPPUPD3_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00200000 */

+#define PWR_WKUPEPR_WKUPPUPD2_Pos      (18U)

+#define PWR_WKUPEPR_WKUPPUPD2_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x000C0000 */

+#define PWR_WKUPEPR_WKUPPUPD2          PWR_WKUPEPR_WKUPPUPD2_Msk               /*!< Wakeup Pin pull configuration for WKUP2 */

+#define PWR_WKUPEPR_WKUPPUPD2_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00040000 */

+#define PWR_WKUPEPR_WKUPPUPD2_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00080000 */

+#define PWR_WKUPEPR_WKUPPUPD1_Pos      (16U)

+#define PWR_WKUPEPR_WKUPPUPD1_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00030000 */

+#define PWR_WKUPEPR_WKUPPUPD1          PWR_WKUPEPR_WKUPPUPD1_Msk               /*!< Wakeup Pin pull configuration for WKUP1 */

+#define PWR_WKUPEPR_WKUPPUPD1_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00010000 */

+#define PWR_WKUPEPR_WKUPPUPD1_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00020000 */

+#define PWR_WKUPEPR_WKUPP6_Pos         (13U)

+#define PWR_WKUPEPR_WKUPP6_Msk         (0x1UL << PWR_WKUPEPR_WKUPP6_Pos)       /*!< 0x00002000 */

+#define PWR_WKUPEPR_WKUPP6             PWR_WKUPEPR_WKUPP6_Msk                  /*!< Wakeup Pin Polarity for WKUP6 */

+#define PWR_WKUPEPR_WKUPP5_Pos         (12U)

+#define PWR_WKUPEPR_WKUPP5_Msk         (0x1UL << PWR_WKUPEPR_WKUPP5_Pos)       /*!< 0x00001000 */

+#define PWR_WKUPEPR_WKUPP5             PWR_WKUPEPR_WKUPP5_Msk                  /*!< Wakeup Pin Polarity for WKUP5 */

+#define PWR_WKUPEPR_WKUPP4_Pos         (11U)

+#define PWR_WKUPEPR_WKUPP4_Msk         (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)       /*!< 0x00000800 */

+#define PWR_WKUPEPR_WKUPP4             PWR_WKUPEPR_WKUPP4_Msk                  /*!< Wakeup Pin Polarity for WKUP4 */

+#define PWR_WKUPEPR_WKUPP3_Pos         (10U)

+#define PWR_WKUPEPR_WKUPP3_Msk         (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)       /*!< 0x00000400 */

+#define PWR_WKUPEPR_WKUPP3             PWR_WKUPEPR_WKUPP3_Msk                  /*!< Wakeup Pin Polarity for WKUP3 */

+#define PWR_WKUPEPR_WKUPP2_Pos         (9U)

+#define PWR_WKUPEPR_WKUPP2_Msk         (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)       /*!< 0x00000200 */

+#define PWR_WKUPEPR_WKUPP2             PWR_WKUPEPR_WKUPP2_Msk                  /*!< Wakeup Pin Polarity for WKUP2 */

+#define PWR_WKUPEPR_WKUPP1_Pos         (8U)

+#define PWR_WKUPEPR_WKUPP1_Msk         (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)       /*!< 0x00000100 */

+#define PWR_WKUPEPR_WKUPP1             PWR_WKUPEPR_WKUPP1_Msk                  /*!< Wakeup Pin Polarity for WKUP1 */

+#define PWR_WKUPEPR_WKUPEN6_Pos        (5U)

+#define PWR_WKUPEPR_WKUPEN6_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos)      /*!< 0x00000020 */

+#define PWR_WKUPEPR_WKUPEN6            PWR_WKUPEPR_WKUPEN6_Msk                 /*!< Enable Wakeup Pin WKUP6 */

+#define PWR_WKUPEPR_WKUPEN5_Pos        (4U)

+#define PWR_WKUPEPR_WKUPEN5_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos)      /*!< 0x00000010 */

+#define PWR_WKUPEPR_WKUPEN5            PWR_WKUPEPR_WKUPEN5_Msk                 /*!< Enable Wakeup Pin WKUP5 */

+#define PWR_WKUPEPR_WKUPEN4_Pos        (3U)

+#define PWR_WKUPEPR_WKUPEN4_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)      /*!< 0x00000008 */

+#define PWR_WKUPEPR_WKUPEN4            PWR_WKUPEPR_WKUPEN4_Msk                 /*!< Enable Wakeup Pin WKUP4 */

+#define PWR_WKUPEPR_WKUPEN3_Pos        (2U)

+#define PWR_WKUPEPR_WKUPEN3_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)      /*!< 0x00000004 */

+#define PWR_WKUPEPR_WKUPEN3            PWR_WKUPEPR_WKUPEN3_Msk                 /*!< Enable Wakeup Pin WKUP3 */

+#define PWR_WKUPEPR_WKUPEN2_Pos        (1U)

+#define PWR_WKUPEPR_WKUPEN2_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)      /*!< 0x00000002 */

+#define PWR_WKUPEPR_WKUPEN2            PWR_WKUPEPR_WKUPEN2_Msk                 /*!< Enable Wakeup Pin WKUP2 */

+#define PWR_WKUPEPR_WKUPEN1_Pos        (0U)

+#define PWR_WKUPEPR_WKUPEN1_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)      /*!< 0x00000001 */

+#define PWR_WKUPEPR_WKUPEN1            PWR_WKUPEPR_WKUPEN1_Msk                 /*!< Enable Wakeup Pin WKUP1 */

+#define PWR_WKUPEPR_WKUPEN_Pos         (0U)

+#define PWR_WKUPEPR_WKUPEN_Msk         (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos)      /*!< 0x0000003F */

+#define PWR_WKUPEPR_WKUPEN             PWR_WKUPEPR_WKUPEN_Msk                  /*!< Enable all Wakeup Pin */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Reset and Clock Control                            */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  RCC VERSION  ********************************/

+#define RCC_VER_2_0

+

+/********************  Bit definition for RCC_CR register  ********************/

+#define RCC_CR_HSION_Pos                       (0U)

+#define RCC_CR_HSION_Msk                       (0x1UL << RCC_CR_HSION_Pos)     /*!< 0x00000001 */

+#define RCC_CR_HSION                           RCC_CR_HSION_Msk                /*!< Internal High Speed clock enable */

+#define RCC_CR_HSIKERON_Pos                    (1U)

+#define RCC_CR_HSIKERON_Msk                    (0x1UL << RCC_CR_HSIKERON_Pos)  /*!< 0x00000002 */

+#define RCC_CR_HSIKERON                        RCC_CR_HSIKERON_Msk             /*!< Internal High Speed clock enable for some IPs Kernel */

+#define RCC_CR_HSIRDY_Pos                      (2U)

+#define RCC_CR_HSIRDY_Msk                      (0x1UL << RCC_CR_HSIRDY_Pos)    /*!< 0x00000004 */

+#define RCC_CR_HSIRDY                          RCC_CR_HSIRDY_Msk               /*!< Internal High Speed clock ready flag */

+#define RCC_CR_HSIDIV_Pos                      (3U)

+#define RCC_CR_HSIDIV_Msk                      (0x3UL << RCC_CR_HSIDIV_Pos)    /*!< 0x00000018 */

+#define RCC_CR_HSIDIV                          RCC_CR_HSIDIV_Msk               /*!< Internal High Speed clock divider selection */

+#define RCC_CR_HSIDIV_1                        (0x0UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000000 */

+#define RCC_CR_HSIDIV_2                        (0x1UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000008 */

+#define RCC_CR_HSIDIV_4                        (0x2UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000010 */

+#define RCC_CR_HSIDIV_8                        (0x3UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000018 */

+

+#define RCC_CR_HSIDIVF_Pos                     (5U)

+#define RCC_CR_HSIDIVF_Msk                     (0x1UL << RCC_CR_HSIDIVF_Pos)   /*!< 0x00000020 */

+#define RCC_CR_HSIDIVF                         RCC_CR_HSIDIVF_Msk              /*!< HSI Divider flag */

+#define RCC_CR_CSION_Pos                       (7U)

+#define RCC_CR_CSION_Msk                       (0x1UL << RCC_CR_CSION_Pos)     /*!< 0x00000080 */

+#define RCC_CR_CSION                           RCC_CR_CSION_Msk                /*!< The Internal RC 4MHz oscillator clock enable */

+#define RCC_CR_CSIRDY_Pos                      (8U)

+#define RCC_CR_CSIRDY_Msk                      (0x1UL << RCC_CR_CSIRDY_Pos)    /*!< 0x00000100 */

+#define RCC_CR_CSIRDY                          RCC_CR_CSIRDY_Msk               /*!< The Internal RC 4MHz oscillator clock ready */

+#define RCC_CR_CSIKERON_Pos                    (9U)

+#define RCC_CR_CSIKERON_Msk                    (0x1UL << RCC_CR_CSIKERON_Pos)  /*!< 0x00000200 */

+#define RCC_CR_CSIKERON                        RCC_CR_CSIKERON_Msk             /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */

+#define RCC_CR_HSI48ON_Pos                     (12U)

+#define RCC_CR_HSI48ON_Msk                     (0x1UL << RCC_CR_HSI48ON_Pos)   /*!< 0x00001000 */

+#define RCC_CR_HSI48ON                         RCC_CR_HSI48ON_Msk              /*!< HSI48 clock enable clock enable  */

+#define RCC_CR_HSI48RDY_Pos                    (13U)

+#define RCC_CR_HSI48RDY_Msk                    (0x1UL << RCC_CR_HSI48RDY_Pos)  /*!< 0x00002000 */

+#define RCC_CR_HSI48RDY                        RCC_CR_HSI48RDY_Msk             /*!< HSI48 clock ready */

+

+#define RCC_CR_CPUCKRDY_Pos                     (14U)

+#define RCC_CR_CPUCKRDY_Msk                     (0x1UL << RCC_CR_CPUCKRDY_Pos)   /*!< 0x00004000 */

+#define RCC_CR_CPUCKRDY                         RCC_CR_CPUCKRDY_Msk              /*!< CPU domain clocks ready flag  */

+#define RCC_CR_CDCKRDY_Pos                     (15U)

+#define RCC_CR_CDCKRDY_Msk                     (0x1UL << RCC_CR_CDCKRDY_Pos)   /*!< 0x00008000 */

+#define RCC_CR_CDCKRDY                         RCC_CR_CDCKRDY_Msk              /*!< CD domain clocks ready flag */

+

+#define RCC_CR_HSEON_Pos                       (16U)

+#define RCC_CR_HSEON_Msk                       (0x1UL << RCC_CR_HSEON_Pos)     /*!< 0x00010000 */

+#define RCC_CR_HSEON                           RCC_CR_HSEON_Msk                /*!< External High Speed clock enable */

+#define RCC_CR_HSERDY_Pos                      (17U)

+#define RCC_CR_HSERDY_Msk                      (0x1UL << RCC_CR_HSERDY_Pos)    /*!< 0x00020000 */

+#define RCC_CR_HSERDY                          RCC_CR_HSERDY_Msk               /*!< External High Speed clock ready */

+#define RCC_CR_HSEBYP_Pos                      (18U)

+#define RCC_CR_HSEBYP_Msk                      (0x1UL << RCC_CR_HSEBYP_Pos)    /*!< 0x00040000 */

+#define RCC_CR_HSEBYP                          RCC_CR_HSEBYP_Msk               /*!< External High Speed clock Bypass */

+#define RCC_CR_CSSHSEON_Pos                    (19U)

+#define RCC_CR_CSSHSEON_Msk                    (0x1UL << RCC_CR_CSSHSEON_Pos)  /*!< 0x00080000 */

+#define RCC_CR_CSSHSEON                        RCC_CR_CSSHSEON_Msk             /*!< HSE Clock security System enable */

+

+#define RCC_CR_HSEEXT_Pos                    (20U)

+#define RCC_CR_HSEEXT_Msk                    (0x1UL << RCC_CR_HSEEXT_Pos)  /*!< 0x00080000 */

+#define RCC_CR_HSEEXT                        RCC_CR_HSEEXT_Msk             /*!< HSE Clock security System enable */

+

+#define RCC_CR_PLL1ON_Pos                      (24U)

+#define RCC_CR_PLL1ON_Msk                      (0x1UL << RCC_CR_PLL1ON_Pos)    /*!< 0x01000000 */

+#define RCC_CR_PLL1ON                          RCC_CR_PLL1ON_Msk               /*!< System PLL1 clock enable */

+#define RCC_CR_PLL1RDY_Pos                     (25U)

+#define RCC_CR_PLL1RDY_Msk                     (0x1UL << RCC_CR_PLL1RDY_Pos)   /*!< 0x02000000 */

+#define RCC_CR_PLL1RDY                         RCC_CR_PLL1RDY_Msk              /*!< System PLL1 clock ready */

+#define RCC_CR_PLL2ON_Pos                      (26U)

+#define RCC_CR_PLL2ON_Msk                      (0x1UL << RCC_CR_PLL2ON_Pos)    /*!< 0x04000000 */

+#define RCC_CR_PLL2ON                          RCC_CR_PLL2ON_Msk               /*!< System PLL2 clock enable */

+#define RCC_CR_PLL2RDY_Pos                     (27U)

+#define RCC_CR_PLL2RDY_Msk                     (0x1UL << RCC_CR_PLL2RDY_Pos)   /*!< 0x08000000 */

+#define RCC_CR_PLL2RDY                         RCC_CR_PLL2RDY_Msk              /*!< System PLL2 clock ready */

+#define RCC_CR_PLL3ON_Pos                      (28U)

+#define RCC_CR_PLL3ON_Msk                      (0x1UL << RCC_CR_PLL3ON_Pos)    /*!< 0x10000000 */

+#define RCC_CR_PLL3ON                          RCC_CR_PLL3ON_Msk               /*!< System PLL3 clock enable */

+#define RCC_CR_PLL3RDY_Pos                     (29U)

+#define RCC_CR_PLL3RDY_Msk                     (0x1UL << RCC_CR_PLL3RDY_Pos)   /*!< 0x20000000 */

+#define RCC_CR_PLL3RDY                         RCC_CR_PLL3RDY_Msk              /*!< System PLL3 clock ready */

+

+/*Legacy */

+#define RCC_CR_PLLON_Pos                       (24U)

+#define RCC_CR_PLLON_Msk                       (0x1UL << RCC_CR_PLLON_Pos)     /*!< 0x01000000 */

+#define RCC_CR_PLLON                           RCC_CR_PLLON_Msk                /*!< System PLL clock enable */

+#define RCC_CR_PLLRDY_Pos                      (25U)

+#define RCC_CR_PLLRDY_Msk                      (0x1UL << RCC_CR_PLLRDY_Pos)    /*!< 0x02000000 */

+#define RCC_CR_PLLRDY                          RCC_CR_PLLRDY_Msk               /*!< System PLL clock ready */

+

+/********************  Bit definition for RCC_HSICFGR register  ***************/

+/*!< HSICAL configuration */

+#define RCC_HSICFGR_HSICAL_Pos                 (0U)

+#define RCC_HSICFGR_HSICAL_Msk                 (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */

+#define RCC_HSICFGR_HSICAL                     RCC_HSICFGR_HSICAL_Msk          /*!< HSICAL[11:0] bits */

+#define RCC_HSICFGR_HSICAL_0                   (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */

+#define RCC_HSICFGR_HSICAL_1                   (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */

+#define RCC_HSICFGR_HSICAL_2                   (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */

+#define RCC_HSICFGR_HSICAL_3                   (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */

+#define RCC_HSICFGR_HSICAL_4                   (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */

+#define RCC_HSICFGR_HSICAL_5                   (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */

+#define RCC_HSICFGR_HSICAL_6                   (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */

+#define RCC_HSICFGR_HSICAL_7                   (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */

+#define RCC_HSICFGR_HSICAL_8                   (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */

+#define RCC_HSICFGR_HSICAL_9                   (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */

+#define RCC_HSICFGR_HSICAL_10                  (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */

+#define RCC_HSICFGR_HSICAL_11                  (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */

+

+/*!< HSITRIM configuration */

+#define RCC_HSICFGR_HSITRIM_Pos                (24U)

+#define RCC_HSICFGR_HSITRIM_Msk                (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */

+#define RCC_HSICFGR_HSITRIM                    RCC_HSICFGR_HSITRIM_Msk         /*!< HSITRIM[6:0] bits */

+#define RCC_HSICFGR_HSITRIM_0                  (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */

+#define RCC_HSICFGR_HSITRIM_1                  (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */

+#define RCC_HSICFGR_HSITRIM_2                  (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */

+#define RCC_HSICFGR_HSITRIM_3                  (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */

+#define RCC_HSICFGR_HSITRIM_4                  (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */

+#define RCC_HSICFGR_HSITRIM_5                  (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */

+#define RCC_HSICFGR_HSITRIM_6                  (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */

+

+

+/********************  Bit definition for RCC_CRRCR register  *****************/

+

+/*!< HSI48CAL configuration */

+#define RCC_CRRCR_HSI48CAL_Pos                 (0U)

+#define RCC_CRRCR_HSI48CAL_Msk                 (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */

+#define RCC_CRRCR_HSI48CAL                     RCC_CRRCR_HSI48CAL_Msk          /*!< HSI48CAL[9:0] bits */

+#define RCC_CRRCR_HSI48CAL_0                   (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */

+#define RCC_CRRCR_HSI48CAL_1                   (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */

+#define RCC_CRRCR_HSI48CAL_2                   (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */

+#define RCC_CRRCR_HSI48CAL_3                   (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */

+#define RCC_CRRCR_HSI48CAL_4                   (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */

+#define RCC_CRRCR_HSI48CAL_5                   (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */

+#define RCC_CRRCR_HSI48CAL_6                   (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */

+#define RCC_CRRCR_HSI48CAL_7                   (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */

+#define RCC_CRRCR_HSI48CAL_8                   (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */

+#define RCC_CRRCR_HSI48CAL_9                   (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */

+

+

+/********************  Bit definition for RCC_CSICFGR register  *****************/

+/*!< CSICAL configuration */

+#define RCC_CSICFGR_CSICAL_Pos                 (0U)

+#define RCC_CSICFGR_CSICAL_Msk                 (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */

+#define RCC_CSICFGR_CSICAL                     RCC_CSICFGR_CSICAL_Msk          /*!< CSICAL[7:0] bits */

+#define RCC_CSICFGR_CSICAL_0                   (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */

+#define RCC_CSICFGR_CSICAL_1                   (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */

+#define RCC_CSICFGR_CSICAL_2                   (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */

+#define RCC_CSICFGR_CSICAL_3                   (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */

+#define RCC_CSICFGR_CSICAL_4                   (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */

+#define RCC_CSICFGR_CSICAL_5                   (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */

+#define RCC_CSICFGR_CSICAL_6                   (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */

+#define RCC_CSICFGR_CSICAL_7                   (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */

+

+/*!< CSITRIM configuration */

+#define RCC_CSICFGR_CSITRIM_Pos                (24U)

+#define RCC_CSICFGR_CSITRIM_Msk                (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */

+#define RCC_CSICFGR_CSITRIM                    RCC_CSICFGR_CSITRIM_Msk         /*!< CSITRIM[5:0] bits */

+#define RCC_CSICFGR_CSITRIM_0                  (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */

+#define RCC_CSICFGR_CSITRIM_1                  (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */

+#define RCC_CSICFGR_CSITRIM_2                  (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */

+#define RCC_CSICFGR_CSITRIM_3                  (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */

+#define RCC_CSICFGR_CSITRIM_4                  (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */

+#define RCC_CSICFGR_CSITRIM_5                  (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */

+

+/********************  Bit definition for RCC_CFGR register  ******************/

+/*!< SW configuration */

+#define RCC_CFGR_SW_Pos                        (0U)

+#define RCC_CFGR_SW_Msk                        (0x7UL << RCC_CFGR_SW_Pos)           /*!< 0x00000007 */

+#define RCC_CFGR_SW                            RCC_CFGR_SW_Msk                     /*!< SW[2:0] bits (System clock Switch) */

+#define RCC_CFGR_SW_0                          (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */

+#define RCC_CFGR_SW_1                          (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */

+#define RCC_CFGR_SW_2                          (0x4UL << RCC_CFGR_SW_Pos)           /*!< 0x00000004 */

+

+#define RCC_CFGR_SW_HSI                        (0x00000000UL)                       /*!< HSI selection as system clock */

+#define RCC_CFGR_SW_CSI                        (0x00000001UL)                       /*!< CSI selection as system clock */

+#define RCC_CFGR_SW_HSE                        (0x00000002UL)                       /*!< HSE selection as system clock */

+#define RCC_CFGR_SW_PLL1                       (0x00000003UL)                       /*!< PLL1 selection as system clock */

+

+/*!< SWS configuration */

+#define RCC_CFGR_SWS_Pos                       (3U)

+#define RCC_CFGR_SWS_Msk                       (0x7UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000038 */

+#define RCC_CFGR_SWS                           RCC_CFGR_SWS_Msk                    /*!< SWS[2:0] bits (System Clock Switch Status) */

+#define RCC_CFGR_SWS_0                         (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */

+#define RCC_CFGR_SWS_1                         (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000010 */

+#define RCC_CFGR_SWS_2                         (0x4UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000020 */

+

+#define RCC_CFGR_SWS_HSI                       (0x00000000UL)                       /*!< HSI used as system clock */

+#define RCC_CFGR_SWS_CSI                       (0x00000008UL)                       /*!< CSI used as system clock */

+#define RCC_CFGR_SWS_HSE                       (0x00000010UL)                       /*!< HSE used as system clock */

+#define RCC_CFGR_SWS_PLL1                      (0x00000018UL)                       /*!< PLL1 used as system clock */

+

+#define RCC_CFGR_STOPWUCK_Pos                  (6U)

+#define RCC_CFGR_STOPWUCK_Msk                  (0x1UL << RCC_CFGR_STOPWUCK_Pos)     /*!< 0x00000040 */

+#define RCC_CFGR_STOPWUCK                      RCC_CFGR_STOPWUCK_Msk                /*!< Wake Up from stop and CSS backup clock selection */

+

+#define RCC_CFGR_STOPKERWUCK_Pos               (7U)

+#define RCC_CFGR_STOPKERWUCK_Msk               (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)  /*!< 0x00000080 */

+#define RCC_CFGR_STOPKERWUCK                   RCC_CFGR_STOPKERWUCK_Msk             /*!< Kernel Clock Selection after a Wake Up from STOP */

+

+/*!< RTCPRE configuration */

+#define RCC_CFGR_RTCPRE_Pos                    (8U)

+#define RCC_CFGR_RTCPRE_Msk                    (0x3FUL << RCC_CFGR_RTCPRE_Pos)

+#define RCC_CFGR_RTCPRE                        RCC_CFGR_RTCPRE_Msk                  /*!< 0x00003F00 */

+#define RCC_CFGR_RTCPRE_0                      (0x1UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000100 */

+#define RCC_CFGR_RTCPRE_1                      (0x2UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000200 */

+#define RCC_CFGR_RTCPRE_2                      (0x4UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000400 */

+#define RCC_CFGR_RTCPRE_3                      (0x8UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000800 */

+#define RCC_CFGR_RTCPRE_4                      (0x10UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00001000 */

+#define RCC_CFGR_RTCPRE_5                      (0x20UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00002000 */

+

+

+/*!< TIMPRE configuration */

+#define RCC_CFGR_TIMPRE_Pos                    (15U)

+#define RCC_CFGR_TIMPRE_Msk                    (0x1UL << RCC_CFGR_TIMPRE_Pos)

+#define RCC_CFGR_TIMPRE                        RCC_CFGR_TIMPRE_Msk                  /*!< 0x00008000 */

+

+/*!< MCO1 configuration */

+#define RCC_CFGR_MCO1_Pos                      (22U)

+#define RCC_CFGR_MCO1_Msk                      (0x7UL << RCC_CFGR_MCO1_Pos)

+#define RCC_CFGR_MCO1                          RCC_CFGR_MCO1_Msk                       /*!< 0x01C00000 */

+#define RCC_CFGR_MCO1_0                        (0x1UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00400000 */

+#define RCC_CFGR_MCO1_1                        (0x2UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00800000 */

+#define RCC_CFGR_MCO1_2                        (0x4UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x01000000 */

+

+#define RCC_CFGR_MCO1PRE_Pos                   (18U)

+#define RCC_CFGR_MCO1PRE_Msk                   (0xFUL << RCC_CFGR_MCO1PRE_Pos)

+#define RCC_CFGR_MCO1PRE                       RCC_CFGR_MCO1PRE_Msk                    /*!< 0x003C0000 */

+#define RCC_CFGR_MCO1PRE_0                     (0x1UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00040000 */

+#define RCC_CFGR_MCO1PRE_1                     (0x2UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00080000 */

+#define RCC_CFGR_MCO1PRE_2                     (0x4UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00100000 */

+#define RCC_CFGR_MCO1PRE_3                     (0x8UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00200000 */

+

+#define RCC_CFGR_MCO2PRE_Pos                   (25U)

+#define RCC_CFGR_MCO2PRE_Msk                   (0xFUL << RCC_CFGR_MCO2PRE_Pos)

+#define RCC_CFGR_MCO2PRE                       RCC_CFGR_MCO2PRE_Msk                    /*!< 0x1E000000 */

+#define RCC_CFGR_MCO2PRE_0                     (0x1UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x02000000 */

+#define RCC_CFGR_MCO2PRE_1                     (0x2UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x04000000 */

+#define RCC_CFGR_MCO2PRE_2                     (0x4UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x08000000 */

+#define RCC_CFGR_MCO2PRE_3                     (0x8UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x10000000 */

+

+#define RCC_CFGR_MCO2_Pos                      (29U)

+#define RCC_CFGR_MCO2_Msk                      (0x7UL << RCC_CFGR_MCO2_Pos)

+#define RCC_CFGR_MCO2                          RCC_CFGR_MCO2_Msk                       /*!< 0xE0000000 */

+#define RCC_CFGR_MCO2_0                        (0x1UL << RCC_CFGR_MCO2_Pos)             /*!< 0x20000000 */

+#define RCC_CFGR_MCO2_1                        (0x2UL << RCC_CFGR_MCO2_Pos)             /*!< 0x40000000 */

+#define RCC_CFGR_MCO2_2                        (0x4UL << RCC_CFGR_MCO2_Pos)             /*!< 0x80000000 */

+

+/********************  Bit definition for RCC_D1CFGR register  ******************/

+/*!< D1HPRE configuration */

+#define RCC_CDCFGR1_HPRE_Pos                    (0U)

+#define RCC_CDCFGR1_HPRE_Msk                    (0xFUL << RCC_CDCFGR1_HPRE_Pos)  /*!< 0x0000000F */

+#define RCC_CDCFGR1_HPRE                        RCC_CDCFGR1_HPRE_Msk             /*!< HPRE[3:0] bits (AHB3 prescaler) */

+#define RCC_CDCFGR1_HPRE_0                      (0x1UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000001 */

+#define RCC_CDCFGR1_HPRE_1                      (0x2UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000002 */

+#define RCC_CDCFGR1_HPRE_2                      (0x4UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000004 */

+#define RCC_CDCFGR1_HPRE_3                      (0x8UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000008 */

+

+#define RCC_CDCFGR1_HPRE_DIV1                   ((uint32_t)0x00000000)                 /*!< AHB3 Clock not divided */

+#define RCC_CDCFGR1_HPRE_DIV2_Pos               (3U)

+#define RCC_CDCFGR1_HPRE_DIV2_Msk               (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos)   /*!< 0x00000008 */

+#define RCC_CDCFGR1_HPRE_DIV2                   RCC_CDCFGR1_HPRE_DIV2_Msk              /*!< AHB3 Clock divided by 2 */

+#define RCC_CDCFGR1_HPRE_DIV4_Pos               (0U)

+#define RCC_CDCFGR1_HPRE_DIV4_Msk               (0x9UL << RCC_CDCFGR1_HPRE_DIV4_Pos)   /*!< 0x00000009 */

+#define RCC_CDCFGR1_HPRE_DIV4                   RCC_CDCFGR1_HPRE_DIV4_Msk              /*!< AHB3 Clock divided by 4 */

+#define RCC_CDCFGR1_HPRE_DIV8_Pos               (1U)

+#define RCC_CDCFGR1_HPRE_DIV8_Msk               (0x5UL << RCC_CDCFGR1_HPRE_DIV8_Pos)   /*!< 0x0000000A */

+#define RCC_CDCFGR1_HPRE_DIV8                   RCC_CDCFGR1_HPRE_DIV8_Msk              /*!< AHB3 Clock divided by 8 */

+#define RCC_CDCFGR1_HPRE_DIV16_Pos              (0U)

+#define RCC_CDCFGR1_HPRE_DIV16_Msk              (0xBUL << RCC_CDCFGR1_HPRE_DIV16_Pos)  /*!< 0x0000000B */

+#define RCC_CDCFGR1_HPRE_DIV16                  RCC_CDCFGR1_HPRE_DIV16_Msk             /*!< AHB3 Clock divided by 16 */

+#define RCC_CDCFGR1_HPRE_DIV64_Pos              (2U)

+#define RCC_CDCFGR1_HPRE_DIV64_Msk              (0x3UL << RCC_CDCFGR1_HPRE_DIV64_Pos)  /*!< 0x0000000C */

+#define RCC_CDCFGR1_HPRE_DIV64                  RCC_CDCFGR1_HPRE_DIV64_Msk             /*!< AHB3 Clock divided by 64 */

+#define RCC_CDCFGR1_HPRE_DIV128_Pos             (0U)

+#define RCC_CDCFGR1_HPRE_DIV128_Msk             (0xDUL << RCC_CDCFGR1_HPRE_DIV128_Pos) /*!< 0x0000000D */

+#define RCC_CDCFGR1_HPRE_DIV128                 RCC_CDCFGR1_HPRE_DIV128_Msk            /*!< AHB3 Clock divided by 128 */

+#define RCC_CDCFGR1_HPRE_DIV256_Pos             (1U)

+#define RCC_CDCFGR1_HPRE_DIV256_Msk             (0x7UL << RCC_CDCFGR1_HPRE_DIV256_Pos) /*!< 0x0000000E */

+#define RCC_CDCFGR1_HPRE_DIV256                 RCC_CDCFGR1_HPRE_DIV256_Msk            /*!< AHB3 Clock divided by 256 */

+#define RCC_CDCFGR1_HPRE_DIV512_Pos             (0U)

+#define RCC_CDCFGR1_HPRE_DIV512_Msk             (0xFUL << RCC_CDCFGR1_HPRE_DIV512_Pos) /*!< 0x0000000F */

+#define RCC_CDCFGR1_HPRE_DIV512                 RCC_CDCFGR1_HPRE_DIV512_Msk            /*!< AHB3 Clock divided by 512 */

+

+/*!< D1PPRE configuration */

+#define RCC_CDCFGR1_CDPPRE_Pos                  (4U)

+#define RCC_CDCFGR1_CDPPRE_Msk                  (0x7UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000070 */

+#define RCC_CDCFGR1_CDPPRE                      RCC_CDCFGR1_CDPPRE_Msk                 /*!< CDPRE[2:0] bits (APB3 prescaler) */

+#define RCC_CDCFGR1_CDPPRE_0                    (0x1UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000010 */

+#define RCC_CDCFGR1_CDPPRE_1                    (0x2UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000020 */

+#define RCC_CDCFGR1_CDPPRE_2                    (0x4UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000040 */

+

+#define RCC_CDCFGR1_CDPPRE_DIV1                 ((uint32_t)0x00000000)                 /*!< APB3 clock not divided */

+#define RCC_CDCFGR1_CDPPRE_DIV2_Pos             (6U)

+#define RCC_CDCFGR1_CDPPRE_DIV2_Msk             (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_CDCFGR1_CDPPRE_DIV2                 RCC_CDCFGR1_CDPPRE_DIV2_Msk            /*!< APB3 clock divided by 2 */

+#define RCC_CDCFGR1_CDPPRE_DIV4_Pos             (4U)

+#define RCC_CDCFGR1_CDPPRE_DIV4_Msk             (0x5UL << RCC_CDCFGR1_CDPPRE_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_CDCFGR1_CDPPRE_DIV4                 RCC_CDCFGR1_CDPPRE_DIV4_Msk            /*!< APB3 clock divided by 4 */

+#define RCC_CDCFGR1_CDPPRE_DIV8_Pos             (5U)

+#define RCC_CDCFGR1_CDPPRE_DIV8_Msk             (0x3UL << RCC_CDCFGR1_CDPPRE_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_CDCFGR1_CDPPRE_DIV8                 RCC_CDCFGR1_CDPPRE_DIV8_Msk            /*!< APB3 clock divided by 8 */

+#define RCC_CDCFGR1_CDPPRE_DIV16_Pos            (4U)

+#define RCC_CDCFGR1_CDPPRE_DIV16_Msk            (0x7UL << RCC_CDCFGR1_CDPPRE_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_CDCFGR1_CDPPRE_DIV16                RCC_CDCFGR1_CDPPRE_DIV16_Msk            /*!< APB3 clock divided by 16 */

+

+#define RCC_CDCFGR1_CDCPRE_Pos                  (8U)

+#define RCC_CDCFGR1_CDCPRE_Msk                  (0xFUL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000F00 */

+#define RCC_CDCFGR1_CDCPRE                      RCC_CDCFGR1_CDCPRE_Msk                  /*!< CDCPRE[2:0] bits (Domain 1 Core prescaler) */

+#define RCC_CDCFGR1_CDCPRE_0                    (0x1UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000100 */

+#define RCC_CDCFGR1_CDCPRE_1                    (0x2UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000200 */

+#define RCC_CDCFGR1_CDCPRE_2                    (0x4UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000400 */

+#define RCC_CDCFGR1_CDCPRE_3                    (0x8UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000800 */

+

+#define RCC_CDCFGR1_CDCPRE_DIV1                 ((uint32_t)0x00000000)                  /*!< Domain 1 Core clock not divided */

+#define RCC_CDCFGR1_CDCPRE_DIV2_Pos             (11U)

+#define RCC_CDCFGR1_CDCPRE_DIV2_Msk             (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos)  /*!< 0x00000800 */

+#define RCC_CDCFGR1_CDCPRE_DIV2                 RCC_CDCFGR1_CDCPRE_DIV2_Msk             /*!< Domain 1 Core clock divided by 2 */

+#define RCC_CDCFGR1_CDCPRE_DIV4_Pos             (8U)

+#define RCC_CDCFGR1_CDCPRE_DIV4_Msk             (0x9UL << RCC_CDCFGR1_CDCPRE_DIV4_Pos)  /*!< 0x00000900 */

+#define RCC_CDCFGR1_CDCPRE_DIV4                 RCC_CDCFGR1_CDCPRE_DIV4_Msk             /*!< Domain 1 Core clock divided by 4 */

+#define RCC_CDCFGR1_CDCPRE_DIV8_Pos             (9U)

+#define RCC_CDCFGR1_CDCPRE_DIV8_Msk             (0x5UL << RCC_CDCFGR1_CDCPRE_DIV8_Pos)  /*!< 0x00000A00 */

+#define RCC_CDCFGR1_CDCPRE_DIV8                 RCC_CDCFGR1_CDCPRE_DIV8_Msk             /*!< Domain 1 Core clock divided by 8 */

+#define RCC_CDCFGR1_CDCPRE_DIV16_Pos            (8U)

+#define RCC_CDCFGR1_CDCPRE_DIV16_Msk            (0xBUL << RCC_CDCFGR1_CDCPRE_DIV16_Pos) /*!< 0x00000B00 */

+#define RCC_CDCFGR1_CDCPRE_DIV16                RCC_CDCFGR1_CDCPRE_DIV16_Msk            /*!< Domain 1 Core clock divided by 16 */

+#define RCC_CDCFGR1_CDCPRE_DIV64_Pos            (10U)

+#define RCC_CDCFGR1_CDCPRE_DIV64_Msk            (0x3UL << RCC_CDCFGR1_CDCPRE_DIV64_Pos) /*!< 0x00000C00 */

+#define RCC_CDCFGR1_CDCPRE_DIV64                RCC_CDCFGR1_CDCPRE_DIV64_Msk            /*!< Domain 1 Core clock divided by 64 */

+#define RCC_CDCFGR1_CDCPRE_DIV128_Pos           (8U)

+#define RCC_CDCFGR1_CDCPRE_DIV128_Msk           (0xDUL << RCC_CDCFGR1_CDCPRE_DIV128_Pos)/*!< 0x00000D00 */

+#define RCC_CDCFGR1_CDCPRE_DIV128               RCC_CDCFGR1_CDCPRE_DIV128_Msk           /*!< Domain 1 Core clock divided by 128 */

+#define RCC_CDCFGR1_CDCPRE_DIV256_Pos           (9U)

+#define RCC_CDCFGR1_CDCPRE_DIV256_Msk           (0x7UL << RCC_CDCFGR1_CDCPRE_DIV256_Pos)/*!< 0x00000E00 */

+#define RCC_CDCFGR1_CDCPRE_DIV256               RCC_CDCFGR1_CDCPRE_DIV256_Msk           /*!< Domain 1 Core clock divided by 256 */

+#define RCC_CDCFGR1_CDCPRE_DIV512_Pos           (8U)

+#define RCC_CDCFGR1_CDCPRE_DIV512_Msk           (0xFUL << RCC_CDCFGR1_CDCPRE_DIV512_Pos)/*!< 0x00000F00 */

+#define RCC_CDCFGR1_CDCPRE_DIV512               RCC_CDCFGR1_CDCPRE_DIV512_Msk           /*!< Domain 1 Core clock divided by 512 */

+

+/********************  Bit definition for RCC_CDCFGR2 register  ******************/

+/*!< CDPPRE1 configuration */

+#define RCC_CDCFGR2_CDPPRE1_Pos                 (4U)

+#define RCC_CDCFGR2_CDPPRE1_Msk                 (0x7UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000070 */

+#define RCC_CDCFGR2_CDPPRE1                     RCC_CDCFGR2_CDPPRE1_Msk          /*!< D1PPRE1[2:0] bits (APB1 prescaler) */

+#define RCC_CDCFGR2_CDPPRE1_0                   (0x1UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000010 */

+#define RCC_CDCFGR2_CDPPRE1_1                   (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */

+#define RCC_CDCFGR2_CDPPRE1_2                   (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */

+

+#define RCC_CDCFGR2_CDPPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */

+#define RCC_CDCFGR2_CDPPRE1_DIV2_Pos            (6U)

+#define RCC_CDCFGR2_CDPPRE1_DIV2_Msk            (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_CDCFGR2_CDPPRE1_DIV2                RCC_CDCFGR2_CDPPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */

+#define RCC_CDCFGR2_CDPPRE1_DIV4_Pos            (4U)

+#define RCC_CDCFGR2_CDPPRE1_DIV4_Msk            (0x5UL << RCC_CDCFGR2_CDPPRE1_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_CDCFGR2_CDPPRE1_DIV4                RCC_CDCFGR2_CDPPRE1_DIV4_Msk     /*!< APB1 clock divided by 4 */

+#define RCC_CDCFGR2_CDPPRE1_DIV8_Pos            (5U)

+#define RCC_CDCFGR2_CDPPRE1_DIV8_Msk            (0x3UL << RCC_CDCFGR2_CDPPRE1_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_CDCFGR2_CDPPRE1_DIV8                RCC_CDCFGR2_CDPPRE1_DIV8_Msk     /*!< APB1 clock divided by 8 */

+#define RCC_CDCFGR2_CDPPRE1_DIV16_Pos           (4U)

+#define RCC_CDCFGR2_CDPPRE1_DIV16_Msk           (0x7UL << RCC_CDCFGR2_CDPPRE1_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_CDCFGR2_CDPPRE1_DIV16               RCC_CDCFGR2_CDPPRE1_DIV16_Msk    /*!< APB1 clock divided by 16 */

+

+/*!< CDPPRE2 configuration */

+#define RCC_CDCFGR2_CDPPRE2_Pos                 (8U)

+#define RCC_CDCFGR2_CDPPRE2_Msk                 (0x7UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000700 */

+#define RCC_CDCFGR2_CDPPRE2                     RCC_CDCFGR2_CDPPRE2_Msk          /*!< CDPPRE2[2:0] bits (APB2 prescaler) */

+#define RCC_CDCFGR2_CDPPRE2_0                   (0x1UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000100 */

+#define RCC_CDCFGR2_CDPPRE2_1                   (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */

+#define RCC_CDCFGR2_CDPPRE2_2                   (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */

+

+#define RCC_CDCFGR2_CDPPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */

+#define RCC_CDCFGR2_CDPPRE2_DIV2_Pos            (10U)

+#define RCC_CDCFGR2_CDPPRE2_DIV2_Msk            (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */

+#define RCC_CDCFGR2_CDPPRE2_DIV2                RCC_CDCFGR2_CDPPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */

+#define RCC_CDCFGR2_CDPPRE2_DIV4_Pos            (8U)

+#define RCC_CDCFGR2_CDPPRE2_DIV4_Msk            (0x5UL << RCC_CDCFGR2_CDPPRE2_DIV4_Pos) /*!< 0x00000500 */

+#define RCC_CDCFGR2_CDPPRE2_DIV4                RCC_CDCFGR2_CDPPRE2_DIV4_Msk     /*!< APB2 clock divided by 4 */

+#define RCC_CDCFGR2_CDPPRE2_DIV8_Pos            (9U)

+#define RCC_CDCFGR2_CDPPRE2_DIV8_Msk            (0x3UL << RCC_CDCFGR2_CDPPRE2_DIV8_Pos) /*!< 0x00000600 */

+#define RCC_CDCFGR2_CDPPRE2_DIV8                RCC_CDCFGR2_CDPPRE2_DIV8_Msk     /*!< APB2 clock divided by 8 */

+#define RCC_CDCFGR2_CDPPRE2_DIV16_Pos           (8U)

+#define RCC_CDCFGR2_CDPPRE2_DIV16_Msk           (0x7UL << RCC_CDCFGR2_CDPPRE2_DIV16_Pos) /*!< 0x00000700 */

+#define RCC_CDCFGR2_CDPPRE2_DIV16               RCC_CDCFGR2_CDPPRE2_DIV16_Msk    /*!< APB2 clock divided by 16 */

+

+/********************  Bit definition for RCC_SRDCFGR register  ******************/

+/*!< SRDPPRE configuration */

+#define RCC_SRDCFGR_SRDPPRE_Pos                  (4U)

+#define RCC_SRDCFGR_SRDPPRE_Msk                  (0x7UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000070 */

+#define RCC_SRDCFGR_SRDPPRE                      RCC_SRDCFGR_SRDPPRE_Msk           /*!< SRDPPRE1[2:0] bits (APB4 prescaler) */

+#define RCC_SRDCFGR_SRDPPRE_0                    (0x1UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000010 */

+#define RCC_SRDCFGR_SRDPPRE_1                    (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */

+#define RCC_SRDCFGR_SRDPPRE_2                    (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */

+

+#define RCC_SRDCFGR_SRDPPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */

+#define RCC_SRDCFGR_SRDPPRE_DIV2_Pos             (6U)

+#define RCC_SRDCFGR_SRDPPRE_DIV2_Msk             (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_SRDCFGR_SRDPPRE_DIV2                 RCC_SRDCFGR_SRDPPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */

+#define RCC_SRDCFGR_SRDPPRE_DIV4_Pos             (4U)

+#define RCC_SRDCFGR_SRDPPRE_DIV4_Msk             (0x5UL << RCC_SRDCFGR_SRDPPRE_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_SRDCFGR_SRDPPRE_DIV4                 RCC_SRDCFGR_SRDPPRE_DIV4_Msk      /*!< APB4 clock divided by 4 */

+#define RCC_SRDCFGR_SRDPPRE_DIV8_Pos             (5U)

+#define RCC_SRDCFGR_SRDPPRE_DIV8_Msk             (0x3UL << RCC_SRDCFGR_SRDPPRE_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_SRDCFGR_SRDPPRE_DIV8                 RCC_SRDCFGR_SRDPPRE_DIV8_Msk      /*!< APB4 clock divided by 8 */

+#define RCC_SRDCFGR_SRDPPRE_DIV16_Pos            (4U)

+#define RCC_SRDCFGR_SRDPPRE_DIV16_Msk            (0x7UL << RCC_SRDCFGR_SRDPPRE_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_SRDCFGR_SRDPPRE_DIV16                RCC_SRDCFGR_SRDPPRE_DIV16_Msk     /*!< APB4 clock divided by 16 */

+

+/********************  Bit definition for RCC_PLLCKSELR register  *************/

+

+#define RCC_PLLCKSELR_PLLSRC_Pos               (0U)

+#define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */

+#define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk

+

+#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)

+#define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */

+#define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_HSE_Pos           (1U)

+#define RCC_PLLCKSELR_PLLSRC_HSE_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */

+#define RCC_PLLCKSELR_PLLSRC_HSE               RCC_PLLCKSELR_PLLSRC_HSE_Msk    /*!< HSE source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_NONE_Pos          (0U)

+#define RCC_PLLCKSELR_PLLSRC_NONE_Msk          (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */

+#define RCC_PLLCKSELR_PLLSRC_NONE              RCC_PLLCKSELR_PLLSRC_NONE_Msk   /*!< No source clock selected  */

+

+#define RCC_PLLCKSELR_DIVM1_Pos                (4U)

+#define RCC_PLLCKSELR_DIVM1_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */

+#define RCC_PLLCKSELR_DIVM1                    RCC_PLLCKSELR_DIVM1_Msk

+#define RCC_PLLCKSELR_DIVM1_0                  (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */

+#define RCC_PLLCKSELR_DIVM1_1                  (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */

+#define RCC_PLLCKSELR_DIVM1_2                  (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */

+#define RCC_PLLCKSELR_DIVM1_3                  (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */

+#define RCC_PLLCKSELR_DIVM1_4                  (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */

+#define RCC_PLLCKSELR_DIVM1_5                  (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */

+

+#define RCC_PLLCKSELR_DIVM2_Pos                (12U)

+#define RCC_PLLCKSELR_DIVM2_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */

+#define RCC_PLLCKSELR_DIVM2                    RCC_PLLCKSELR_DIVM2_Msk

+#define RCC_PLLCKSELR_DIVM2_0                  (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */

+#define RCC_PLLCKSELR_DIVM2_1                  (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */

+#define RCC_PLLCKSELR_DIVM2_2                  (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */

+#define RCC_PLLCKSELR_DIVM2_3                  (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */

+#define RCC_PLLCKSELR_DIVM2_4                  (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */

+#define RCC_PLLCKSELR_DIVM2_5                  (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */

+

+#define RCC_PLLCKSELR_DIVM3_Pos                (20U)

+#define RCC_PLLCKSELR_DIVM3_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */

+#define RCC_PLLCKSELR_DIVM3                    RCC_PLLCKSELR_DIVM3_Msk

+#define RCC_PLLCKSELR_DIVM3_0                  (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */

+#define RCC_PLLCKSELR_DIVM3_1                  (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */

+#define RCC_PLLCKSELR_DIVM3_2                  (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */

+#define RCC_PLLCKSELR_DIVM3_3                  (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */

+#define RCC_PLLCKSELR_DIVM3_4                  (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */

+#define RCC_PLLCKSELR_DIVM3_5                  (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */

+

+/********************  Bit definition for RCC_PLLCFGR register  ***************/

+

+#define RCC_PLLCFGR_PLL1FRACEN_Pos             (0U)

+#define RCC_PLLCFGR_PLL1FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */

+#define RCC_PLLCFGR_PLL1FRACEN                 RCC_PLLCFGR_PLL1FRACEN_Msk

+#define RCC_PLLCFGR_PLL1VCOSEL_Pos             (1U)

+#define RCC_PLLCFGR_PLL1VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */

+#define RCC_PLLCFGR_PLL1VCOSEL                 RCC_PLLCFGR_PLL1VCOSEL_Msk

+#define RCC_PLLCFGR_PLL1RGE_Pos                (2U)

+#define RCC_PLLCFGR_PLL1RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */

+#define RCC_PLLCFGR_PLL1RGE                    RCC_PLLCFGR_PLL1RGE_Msk

+#define RCC_PLLCFGR_PLL1RGE_0                  (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL1RGE_1                  (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */

+#define RCC_PLLCFGR_PLL1RGE_2                  (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */

+#define RCC_PLLCFGR_PLL1RGE_3                  (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */

+

+#define RCC_PLLCFGR_PLL2FRACEN_Pos             (4U)

+#define RCC_PLLCFGR_PLL2FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */

+#define RCC_PLLCFGR_PLL2FRACEN                 RCC_PLLCFGR_PLL2FRACEN_Msk

+#define RCC_PLLCFGR_PLL2VCOSEL_Pos             (5U)

+#define RCC_PLLCFGR_PLL2VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */

+#define RCC_PLLCFGR_PLL2VCOSEL                 RCC_PLLCFGR_PLL2VCOSEL_Msk

+#define RCC_PLLCFGR_PLL2RGE_Pos                (6U)

+#define RCC_PLLCFGR_PLL2RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */

+#define RCC_PLLCFGR_PLL2RGE                    RCC_PLLCFGR_PLL2RGE_Msk

+#define RCC_PLLCFGR_PLL2RGE_0                  (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL2RGE_1                  (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */

+#define RCC_PLLCFGR_PLL2RGE_2                  (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */

+#define RCC_PLLCFGR_PLL2RGE_3                  (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */

+

+#define RCC_PLLCFGR_PLL3FRACEN_Pos             (8U)

+#define RCC_PLLCFGR_PLL3FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */

+#define RCC_PLLCFGR_PLL3FRACEN                 RCC_PLLCFGR_PLL3FRACEN_Msk

+#define RCC_PLLCFGR_PLL3VCOSEL_Pos             (9U)

+#define RCC_PLLCFGR_PLL3VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */

+#define RCC_PLLCFGR_PLL3VCOSEL                 RCC_PLLCFGR_PLL3VCOSEL_Msk

+#define RCC_PLLCFGR_PLL3RGE_Pos                (10U)

+#define RCC_PLLCFGR_PLL3RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */

+#define RCC_PLLCFGR_PLL3RGE                    RCC_PLLCFGR_PLL3RGE_Msk

+#define RCC_PLLCFGR_PLL3RGE_0                  (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL3RGE_1                  (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */

+#define RCC_PLLCFGR_PLL3RGE_2                  (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */

+#define RCC_PLLCFGR_PLL3RGE_3                  (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */

+

+#define RCC_PLLCFGR_DIVP1EN_Pos                (16U)

+#define RCC_PLLCFGR_DIVP1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */

+#define RCC_PLLCFGR_DIVP1EN                    RCC_PLLCFGR_DIVP1EN_Msk

+#define RCC_PLLCFGR_DIVQ1EN_Pos                (17U)

+#define RCC_PLLCFGR_DIVQ1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */

+#define RCC_PLLCFGR_DIVQ1EN                    RCC_PLLCFGR_DIVQ1EN_Msk

+#define RCC_PLLCFGR_DIVR1EN_Pos                (18U)

+#define RCC_PLLCFGR_DIVR1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */

+#define RCC_PLLCFGR_DIVR1EN                    RCC_PLLCFGR_DIVR1EN_Msk

+

+#define RCC_PLLCFGR_DIVP2EN_Pos                (19U)

+#define RCC_PLLCFGR_DIVP2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */

+#define RCC_PLLCFGR_DIVP2EN                    RCC_PLLCFGR_DIVP2EN_Msk

+#define RCC_PLLCFGR_DIVQ2EN_Pos                (20U)

+#define RCC_PLLCFGR_DIVQ2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */

+#define RCC_PLLCFGR_DIVQ2EN                    RCC_PLLCFGR_DIVQ2EN_Msk

+#define RCC_PLLCFGR_DIVR2EN_Pos                (21U)

+#define RCC_PLLCFGR_DIVR2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */

+#define RCC_PLLCFGR_DIVR2EN                    RCC_PLLCFGR_DIVR2EN_Msk

+

+#define RCC_PLLCFGR_DIVP3EN_Pos                (22U)

+#define RCC_PLLCFGR_DIVP3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */

+#define RCC_PLLCFGR_DIVP3EN                    RCC_PLLCFGR_DIVP3EN_Msk

+#define RCC_PLLCFGR_DIVQ3EN_Pos                (23U)

+#define RCC_PLLCFGR_DIVQ3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */

+#define RCC_PLLCFGR_DIVQ3EN                    RCC_PLLCFGR_DIVQ3EN_Msk

+#define RCC_PLLCFGR_DIVR3EN_Pos                (24U)

+#define RCC_PLLCFGR_DIVR3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */

+#define RCC_PLLCFGR_DIVR3EN                    RCC_PLLCFGR_DIVR3EN_Msk

+

+

+/********************  Bit definition for RCC_PLL1DIVR register  ***************/

+#define RCC_PLL1DIVR_N1_Pos                    (0U)

+#define RCC_PLL1DIVR_N1_Msk                    (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */

+#define RCC_PLL1DIVR_N1                        RCC_PLL1DIVR_N1_Msk

+#define RCC_PLL1DIVR_P1_Pos                    (9U)

+#define RCC_PLL1DIVR_P1_Msk                    (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL1DIVR_P1                        RCC_PLL1DIVR_P1_Msk

+#define RCC_PLL1DIVR_Q1_Pos                    (16U)

+#define RCC_PLL1DIVR_Q1_Msk                    (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */

+#define RCC_PLL1DIVR_Q1                        RCC_PLL1DIVR_Q1_Msk

+#define RCC_PLL1DIVR_R1_Pos                    (24U)

+#define RCC_PLL1DIVR_R1_Msk                    (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */

+#define RCC_PLL1DIVR_R1                        RCC_PLL1DIVR_R1_Msk

+

+/********************  Bit definition for RCC_PLL1FRACR register  ***************/

+#define RCC_PLL1FRACR_FRACN1_Pos               (3U)

+#define RCC_PLL1FRACR_FRACN1_Msk               (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL1FRACR_FRACN1                   RCC_PLL1FRACR_FRACN1_Msk

+

+/********************  Bit definition for RCC_PLL2DIVR register  ***************/

+#define RCC_PLL2DIVR_N2_Pos                    (0U)

+#define RCC_PLL2DIVR_N2_Msk                    (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */

+#define RCC_PLL2DIVR_N2                        RCC_PLL2DIVR_N2_Msk

+#define RCC_PLL2DIVR_P2_Pos                    (9U)

+#define RCC_PLL2DIVR_P2_Msk                    (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL2DIVR_P2                        RCC_PLL2DIVR_P2_Msk

+#define RCC_PLL2DIVR_Q2_Pos                    (16U)

+#define RCC_PLL2DIVR_Q2_Msk                    (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */

+#define RCC_PLL2DIVR_Q2                        RCC_PLL2DIVR_Q2_Msk

+#define RCC_PLL2DIVR_R2_Pos                    (24U)

+#define RCC_PLL2DIVR_R2_Msk                    (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */

+#define RCC_PLL2DIVR_R2                        RCC_PLL2DIVR_R2_Msk

+

+/********************  Bit definition for RCC_PLL2FRACR register  ***************/

+#define RCC_PLL2FRACR_FRACN2_Pos               (3U)

+#define RCC_PLL2FRACR_FRACN2_Msk               (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL2FRACR_FRACN2                   RCC_PLL2FRACR_FRACN2_Msk

+

+/********************  Bit definition for RCC_PLL3DIVR register  ***************/

+#define RCC_PLL3DIVR_N3_Pos                    (0U)

+#define RCC_PLL3DIVR_N3_Msk                    (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */

+#define RCC_PLL3DIVR_N3                        RCC_PLL3DIVR_N3_Msk

+#define RCC_PLL3DIVR_P3_Pos                    (9U)

+#define RCC_PLL3DIVR_P3_Msk                    (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL3DIVR_P3                        RCC_PLL3DIVR_P3_Msk

+#define RCC_PLL3DIVR_Q3_Pos                    (16U)

+#define RCC_PLL3DIVR_Q3_Msk                    (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */

+#define RCC_PLL3DIVR_Q3                        RCC_PLL3DIVR_Q3_Msk

+#define RCC_PLL3DIVR_R3_Pos                    (24U)

+#define RCC_PLL3DIVR_R3_Msk                    (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */

+#define RCC_PLL3DIVR_R3                        RCC_PLL3DIVR_R3_Msk

+

+/********************  Bit definition for RCC_PLL3FRACR register  ***************/

+#define RCC_PLL3FRACR_FRACN3_Pos               (3U)

+#define RCC_PLL3FRACR_FRACN3_Msk               (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL3FRACR_FRACN3                   RCC_PLL3FRACR_FRACN3_Msk

+

+/********************  Bit definition for RCC_CDCCIPR register  ***************/

+#define RCC_CDCCIPR_FMCSEL_Pos                 (0U)

+#define RCC_CDCCIPR_FMCSEL_Msk                 (0x3UL << RCC_CDCCIPR_FMCSEL_Pos)     /*!< 0x00000003 */

+#define RCC_CDCCIPR_FMCSEL                     RCC_CDCCIPR_FMCSEL_Msk

+#define RCC_CDCCIPR_FMCSEL_0                   (0x1UL << RCC_CDCCIPR_FMCSEL_Pos)     /*!< 0x00000001 */

+#define RCC_CDCCIPR_FMCSEL_1                   (0x2UL << RCC_CDCCIPR_FMCSEL_Pos)     /*!< 0x00000002 */

+#define RCC_CDCCIPR_OCTOSPISEL_Pos             (4U)

+#define RCC_CDCCIPR_OCTOSPISEL_Msk             (0x3UL << RCC_CDCCIPR_OCTOSPISEL_Pos) /*!< 0x00000030 */

+#define RCC_CDCCIPR_OCTOSPISEL                 RCC_CDCCIPR_OCTOSPISEL_Msk

+#define RCC_CDCCIPR_OCTOSPISEL_0               (0x1UL << RCC_CDCCIPR_OCTOSPISEL_Pos) /*!< 0x00000010 */

+#define RCC_CDCCIPR_OCTOSPISEL_1               (0x2UL << RCC_CDCCIPR_OCTOSPISEL_Pos) /*!< 0x00000020 */

+#define RCC_CDCCIPR_SDMMCSEL_Pos               (16U)

+#define RCC_CDCCIPR_SDMMCSEL_Msk               (0x1UL << RCC_CDCCIPR_SDMMCSEL_Pos)   /*!< 0x00010000 */

+#define RCC_CDCCIPR_SDMMCSEL                   RCC_CDCCIPR_SDMMCSEL_Msk

+#define RCC_CDCCIPR_CKPERSEL_Pos               (28U)

+#define RCC_CDCCIPR_CKPERSEL_Msk               (0x3UL << RCC_CDCCIPR_CKPERSEL_Pos)   /*!< 0x30000000 */

+#define RCC_CDCCIPR_CKPERSEL                   RCC_CDCCIPR_CKPERSEL_Msk

+#define RCC_CDCCIPR_CKPERSEL_0                 (0x1UL << RCC_CDCCIPR_CKPERSEL_Pos)   /*!< 0x10000000 */

+#define RCC_CDCCIPR_CKPERSEL_1                 (0x2UL << RCC_CDCCIPR_CKPERSEL_Pos)   /*!< 0x20000000 */

+

+/********************  Bit definition for RCC_CDCCIP1R register  ***************/

+#define RCC_CDCCIP1R_SAI1SEL_Pos               (0U)

+#define RCC_CDCCIP1R_SAI1SEL_Msk               (0x7UL << RCC_CDCCIP1R_SAI1SEL_Pos)   /*!< 0x00000007 */

+#define RCC_CDCCIP1R_SAI1SEL                   RCC_CDCCIP1R_SAI1SEL_Msk

+#define RCC_CDCCIP1R_SAI1SEL_0                 (0x1UL << RCC_CDCCIP1R_SAI1SEL_Pos)   /*!< 0x00000001 */

+#define RCC_CDCCIP1R_SAI1SEL_1                 (0x2UL << RCC_CDCCIP1R_SAI1SEL_Pos)   /*!< 0x00000002 */

+#define RCC_CDCCIP1R_SAI1SEL_2                 (0x4UL << RCC_CDCCIP1R_SAI1SEL_Pos)   /*!< 0x00000004 */

+

+#define RCC_CDCCIP1R_SAI2ASEL_Pos              (6U)

+#define RCC_CDCCIP1R_SAI2ASEL_Msk              (0x7UL << RCC_CDCCIP1R_SAI2ASEL_Pos)  /*!< 0x000001C0 */

+#define RCC_CDCCIP1R_SAI2ASEL                  RCC_CDCCIP1R_SAI2ASEL_Msk

+#define RCC_CDCCIP1R_SAI2ASEL_0                (0x1UL << RCC_CDCCIP1R_SAI2ASEL_Pos)  /*!< 0x00000040 */

+#define RCC_CDCCIP1R_SAI2ASEL_1                (0x2UL << RCC_CDCCIP1R_SAI2ASEL_Pos)  /*!< 0x00000080 */

+#define RCC_CDCCIP1R_SAI2ASEL_2                (0x4UL << RCC_CDCCIP1R_SAI2ASEL_Pos)  /*!< 0x00000100 */

+

+#define RCC_CDCCIP1R_SAI2BSEL_Pos              (9U)

+#define RCC_CDCCIP1R_SAI2BSEL_Msk              (0x7UL << RCC_CDCCIP1R_SAI2BSEL_Pos)  /*!< 0x00000E00 */

+#define RCC_CDCCIP1R_SAI2BSEL                  RCC_CDCCIP1R_SAI2BSEL_Msk

+#define RCC_CDCCIP1R_SAI2BSEL_0                (0x1UL << RCC_CDCCIP1R_SAI2BSEL_Pos)  /*!< 0x00000200 */

+#define RCC_CDCCIP1R_SAI2BSEL_1                (0x2UL << RCC_CDCCIP1R_SAI2BSEL_Pos)  /*!< 0x00000400 */

+#define RCC_CDCCIP1R_SAI2BSEL_2                (0x4UL << RCC_CDCCIP1R_SAI2BSEL_Pos)  /*!< 0x00000800 */

+

+#define RCC_CDCCIP1R_SPI123SEL_Pos             (12U)

+#define RCC_CDCCIP1R_SPI123SEL_Msk             (0x7UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */

+#define RCC_CDCCIP1R_SPI123SEL                 RCC_CDCCIP1R_SPI123SEL_Msk

+#define RCC_CDCCIP1R_SPI123SEL_0               (0x1UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */

+#define RCC_CDCCIP1R_SPI123SEL_1               (0x2UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */

+#define RCC_CDCCIP1R_SPI123SEL_2               (0x4UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */

+

+#define RCC_CDCCIP1R_SPI45SEL_Pos              (16U)

+#define RCC_CDCCIP1R_SPI45SEL_Msk              (0x7UL << RCC_CDCCIP1R_SPI45SEL_Pos)  /*!< 0x00070000 */

+#define RCC_CDCCIP1R_SPI45SEL                  RCC_CDCCIP1R_SPI45SEL_Msk

+#define RCC_CDCCIP1R_SPI45SEL_0                (0x1UL << RCC_CDCCIP1R_SPI45SEL_Pos)  /*!< 0x00010000 */

+#define RCC_CDCCIP1R_SPI45SEL_1                (0x2UL << RCC_CDCCIP1R_SPI45SEL_Pos)  /*!< 0x00020000 */

+#define RCC_CDCCIP1R_SPI45SEL_2                (0x4UL << RCC_CDCCIP1R_SPI45SEL_Pos)  /*!< 0x00040000 */

+

+#define RCC_CDCCIP1R_SPDIFSEL_Pos              (20U)

+#define RCC_CDCCIP1R_SPDIFSEL_Msk              (0x3UL << RCC_CDCCIP1R_SPDIFSEL_Pos)  /*!< 0x00300000 */

+#define RCC_CDCCIP1R_SPDIFSEL                  RCC_CDCCIP1R_SPDIFSEL_Msk

+#define RCC_CDCCIP1R_SPDIFSEL_0                (0x1UL << RCC_CDCCIP1R_SPDIFSEL_Pos)  /*!< 0x00100000 */

+#define RCC_CDCCIP1R_SPDIFSEL_1                (0x2UL << RCC_CDCCIP1R_SPDIFSEL_Pos)  /*!< 0x00200000 */

+

+#define RCC_CDCCIP1R_DFSDM1SEL_Pos             (24U)

+#define RCC_CDCCIP1R_DFSDM1SEL_Msk             (0x1UL << RCC_CDCCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */

+#define RCC_CDCCIP1R_DFSDM1SEL                 RCC_CDCCIP1R_DFSDM1SEL_Msk

+

+#define RCC_CDCCIP1R_FDCANSEL_Pos              (28U)

+#define RCC_CDCCIP1R_FDCANSEL_Msk              (0x3UL << RCC_CDCCIP1R_FDCANSEL_Pos)  /*!< 0x30000000 */

+#define RCC_CDCCIP1R_FDCANSEL                  RCC_CDCCIP1R_FDCANSEL_Msk

+#define RCC_CDCCIP1R_FDCANSEL_0                (0x1UL << RCC_CDCCIP1R_FDCANSEL_Pos)  /*!< 0x10000000 */

+#define RCC_CDCCIP1R_FDCANSEL_1                (0x2UL << RCC_CDCCIP1R_FDCANSEL_Pos)  /*!< 0x20000000 */

+

+#define RCC_CDCCIP1R_SWPSEL_Pos                (31U)

+#define RCC_CDCCIP1R_SWPSEL_Msk                (0x1UL << RCC_CDCCIP1R_SWPSEL_Pos)    /*!< 0x80000000 */

+#define RCC_CDCCIP1R_SWPSEL                    RCC_CDCCIP1R_SWPSEL_Msk

+

+/********************  Bit definition for RCC_CDCCIP2R register  ***************/

+#define RCC_CDCCIP2R_USART234578SEL_Pos        (0U)

+#define RCC_CDCCIP2R_USART234578SEL_Msk        (0x7UL << RCC_CDCCIP2R_USART234578SEL_Pos)   /*!< 0x00000007 */

+#define RCC_CDCCIP2R_USART234578SEL            RCC_CDCCIP2R_USART234578SEL_Msk

+#define RCC_CDCCIP2R_USART234578SEL_0          (0x1UL << RCC_CDCCIP2R_USART234578SEL_Pos)   /*!< 0x00000001 */

+#define RCC_CDCCIP2R_USART234578SEL_1          (0x2UL << RCC_CDCCIP2R_USART234578SEL_Pos)   /*!< 0x00000002 */

+#define RCC_CDCCIP2R_USART234578SEL_2          (0x4UL << RCC_CDCCIP2R_USART234578SEL_Pos)   /*!< 0x00000004 */

+

+#define RCC_CDCCIP2R_USART16910SEL_Pos         (3U)

+#define RCC_CDCCIP2R_USART16910SEL_Msk         (0x7UL << RCC_CDCCIP2R_USART16910SEL_Pos)    /*!< 0x00000038 */

+#define RCC_CDCCIP2R_USART16910SEL             RCC_CDCCIP2R_USART16910SEL_Msk

+#define RCC_CDCCIP2R_USART16910SEL_0           (0x1UL << RCC_CDCCIP2R_USART16910SEL_Pos)    /*!< 0x00000008 */

+#define RCC_CDCCIP2R_USART16910SEL_1           (0x2UL << RCC_CDCCIP2R_USART16910SEL_Pos)    /*!< 0x00000010 */

+#define RCC_CDCCIP2R_USART16910SEL_2           (0x4UL << RCC_CDCCIP2R_USART16910SEL_Pos)    /*!< 0x00000020 */

+

+#define RCC_CDCCIP2R_RNGSEL_Pos                (8U)

+#define RCC_CDCCIP2R_RNGSEL_Msk                (0x3UL << RCC_CDCCIP2R_RNGSEL_Pos)           /*!< 0x00000300 */

+#define RCC_CDCCIP2R_RNGSEL                    RCC_CDCCIP2R_RNGSEL_Msk

+#define RCC_CDCCIP2R_RNGSEL_0                  (0x1UL << RCC_CDCCIP2R_RNGSEL_Pos)           /*!< 0x00000100 */

+#define RCC_CDCCIP2R_RNGSEL_1                  (0x2UL << RCC_CDCCIP2R_RNGSEL_Pos)           /*!< 0x00000200 */

+

+#define RCC_CDCCIP2R_I2C123SEL_Pos             (12U)

+#define RCC_CDCCIP2R_I2C123SEL_Msk             (0x3UL << RCC_CDCCIP2R_I2C123SEL_Pos)        /*!< 0x00003000 */

+#define RCC_CDCCIP2R_I2C123SEL                 RCC_CDCCIP2R_I2C123SEL_Msk

+#define RCC_CDCCIP2R_I2C123SEL_0               (0x1UL << RCC_CDCCIP2R_I2C123SEL_Pos)        /*!< 0x00001000 */

+#define RCC_CDCCIP2R_I2C123SEL_1               (0x2UL << RCC_CDCCIP2R_I2C123SEL_Pos)        /*!< 0x00002000 */

+

+#define RCC_CDCCIP2R_USBSEL_Pos                (20U)

+#define RCC_CDCCIP2R_USBSEL_Msk                (0x3UL << RCC_CDCCIP2R_USBSEL_Pos)           /*!< 0x00300000 */

+#define RCC_CDCCIP2R_USBSEL                    RCC_CDCCIP2R_USBSEL_Msk

+#define RCC_CDCCIP2R_USBSEL_0                  (0x1UL << RCC_CDCCIP2R_USBSEL_Pos)           /*!< 0x00100000 */

+#define RCC_CDCCIP2R_USBSEL_1                  (0x2UL << RCC_CDCCIP2R_USBSEL_Pos)           /*!< 0x00200000 */

+

+#define RCC_CDCCIP2R_CECSEL_Pos                (22U)

+#define RCC_CDCCIP2R_CECSEL_Msk                (0x3UL << RCC_CDCCIP2R_CECSEL_Pos)           /*!< 0x00C00000 */

+#define RCC_CDCCIP2R_CECSEL                    RCC_CDCCIP2R_CECSEL_Msk

+#define RCC_CDCCIP2R_CECSEL_0                  (0x1UL << RCC_CDCCIP2R_CECSEL_Pos)           /*!< 0x00400000 */

+#define RCC_CDCCIP2R_CECSEL_1                  (0x2UL << RCC_CDCCIP2R_CECSEL_Pos)           /*!< 0x00800000 */

+

+#define RCC_CDCCIP2R_LPTIM1SEL_Pos             (28U)

+#define RCC_CDCCIP2R_LPTIM1SEL_Msk             (0x7UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)        /*!< 0x70000000 */

+#define RCC_CDCCIP2R_LPTIM1SEL                 RCC_CDCCIP2R_LPTIM1SEL_Msk

+#define RCC_CDCCIP2R_LPTIM1SEL_0               (0x1UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)        /*!< 0x10000000 */

+#define RCC_CDCCIP2R_LPTIM1SEL_1               (0x2UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)        /*!< 0x20000000 */

+#define RCC_CDCCIP2R_LPTIM1SEL_2               (0x4UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)        /*!< 0x40000000 */

+

+/********************  Bit definition for RCC_SRDCCIPR register  ***************/

+#define RCC_SRDCCIPR_LPUART1SEL_Pos             (0U)

+#define RCC_SRDCCIPR_LPUART1SEL_Msk             (0x7UL << RCC_SRDCCIPR_LPUART1SEL_Pos)      /*!< 0x00000007 */

+#define RCC_SRDCCIPR_LPUART1SEL                 RCC_SRDCCIPR_LPUART1SEL_Msk

+#define RCC_SRDCCIPR_LPUART1SEL_0               (0x1UL << RCC_SRDCCIPR_LPUART1SEL_Pos)      /*!< 0x00000001 */

+#define RCC_SRDCCIPR_LPUART1SEL_1               (0x2UL << RCC_SRDCCIPR_LPUART1SEL_Pos)      /*!< 0x00000002 */

+#define RCC_SRDCCIPR_LPUART1SEL_2               (0x4UL << RCC_SRDCCIPR_LPUART1SEL_Pos)      /*!< 0x00000004 */

+

+#define RCC_SRDCCIPR_I2C4SEL_Pos                (8U)

+#define RCC_SRDCCIPR_I2C4SEL_Msk                (0x3UL << RCC_SRDCCIPR_I2C4SEL_Pos)         /*!< 0x00000300 */

+#define RCC_SRDCCIPR_I2C4SEL                    RCC_SRDCCIPR_I2C4SEL_Msk

+#define RCC_SRDCCIPR_I2C4SEL_0                  (0x1UL << RCC_SRDCCIPR_I2C4SEL_Pos)         /*!< 0x00000100 */

+#define RCC_SRDCCIPR_I2C4SEL_1                  (0x2UL << RCC_SRDCCIPR_I2C4SEL_Pos)         /*!< 0x00000200 */

+

+#define RCC_SRDCCIPR_LPTIM2SEL_Pos              (10U)

+#define RCC_SRDCCIPR_LPTIM2SEL_Msk              (0x7UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)       /*!< 0x00001C00 */

+#define RCC_SRDCCIPR_LPTIM2SEL                  RCC_SRDCCIPR_LPTIM2SEL_Msk

+#define RCC_SRDCCIPR_LPTIM2SEL_0                (0x1UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)       /*!< 0x00000400 */

+#define RCC_SRDCCIPR_LPTIM2SEL_1                (0x2UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)       /*!< 0x00000800 */

+#define RCC_SRDCCIPR_LPTIM2SEL_2                (0x4UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)       /*!< 0x00001000 */

+

+#define RCC_SRDCCIPR_LPTIM3SEL_Pos            (13U)

+#define RCC_SRDCCIPR_LPTIM3SEL_Msk            (0x7UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)         /*!< 0x0000E000 */

+#define RCC_SRDCCIPR_LPTIM3SEL                RCC_SRDCCIPR_LPTIM3SEL_Msk

+#define RCC_SRDCCIPR_LPTIM3SEL_0              (0x1UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)         /*!< 0x00002000 */

+#define RCC_SRDCCIPR_LPTIM3SEL_1              (0x2UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)         /*!< 0x00004000 */

+#define RCC_SRDCCIPR_LPTIM3SEL_2              (0x4UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)         /*!< 0x00008000 */

+

+#define RCC_SRDCCIPR_ADCSEL_Pos                 (16U)

+#define RCC_SRDCCIPR_ADCSEL_Msk                 (0x3UL << RCC_SRDCCIPR_ADCSEL_Pos)          /*!< 0x00030000 */

+#define RCC_SRDCCIPR_ADCSEL                     RCC_SRDCCIPR_ADCSEL_Msk

+#define RCC_SRDCCIPR_ADCSEL_0                   (0x1UL << RCC_SRDCCIPR_ADCSEL_Pos)          /*!< 0x00010000 */

+#define RCC_SRDCCIPR_ADCSEL_1                   (0x2UL << RCC_SRDCCIPR_ADCSEL_Pos)          /*!< 0x00020000 */

+

+#define RCC_SRDCCIPR_DFSDM2SEL_Pos              (27U)

+#define RCC_SRDCCIPR_DFSDM2SEL_Msk              (0x1UL << RCC_SRDCCIPR_DFSDM2SEL_Pos)       /*!< 0x08000000 */

+#define RCC_SRDCCIPR_DFSDM2SEL                   RCC_SRDCCIPR_DFSDM2SEL_Msk

+

+#define RCC_SRDCCIPR_SPI6SEL_Pos                (28U)

+#define RCC_SRDCCIPR_SPI6SEL_Msk                (0x7UL << RCC_SRDCCIPR_SPI6SEL_Pos)         /*!< 0x70000000 */

+#define RCC_SRDCCIPR_SPI6SEL                    RCC_SRDCCIPR_SPI6SEL_Msk

+#define RCC_SRDCCIPR_SPI6SEL_0                  (0x1UL << RCC_SRDCCIPR_SPI6SEL_Pos)         /*!< 0x10000000 */

+#define RCC_SRDCCIPR_SPI6SEL_1                  (0x2UL << RCC_SRDCCIPR_SPI6SEL_Pos)         /*!< 0x20000000 */

+#define RCC_SRDCCIPR_SPI6SEL_2                  (0x4UL << RCC_SRDCCIPR_SPI6SEL_Pos)         /*!< 0x40000000 */

+

+/********************  Bit definition for RCC_CIER register  ******************/

+#define RCC_CIER_LSIRDYIE_Pos                  (0U)

+#define RCC_CIER_LSIRDYIE_Msk                  (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */

+#define RCC_CIER_LSIRDYIE                      RCC_CIER_LSIRDYIE_Msk

+#define RCC_CIER_LSERDYIE_Pos                  (1U)

+#define RCC_CIER_LSERDYIE_Msk                  (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */

+#define RCC_CIER_LSERDYIE                      RCC_CIER_LSERDYIE_Msk

+#define RCC_CIER_HSIRDYIE_Pos                  (2U)

+#define RCC_CIER_HSIRDYIE_Msk                  (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */

+#define RCC_CIER_HSIRDYIE                      RCC_CIER_HSIRDYIE_Msk

+#define RCC_CIER_HSERDYIE_Pos                  (3U)

+#define RCC_CIER_HSERDYIE_Msk                  (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */

+#define RCC_CIER_HSERDYIE                      RCC_CIER_HSERDYIE_Msk

+#define RCC_CIER_CSIRDYIE_Pos                  (4U)

+#define RCC_CIER_CSIRDYIE_Msk                  (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */

+#define RCC_CIER_CSIRDYIE                      RCC_CIER_CSIRDYIE_Msk

+#define RCC_CIER_HSI48RDYIE_Pos                (5U)

+#define RCC_CIER_HSI48RDYIE_Msk                (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */

+#define RCC_CIER_HSI48RDYIE                    RCC_CIER_HSI48RDYIE_Msk

+#define RCC_CIER_PLL1RDYIE_Pos                 (6U)

+#define RCC_CIER_PLL1RDYIE_Msk                 (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */

+#define RCC_CIER_PLL1RDYIE                     RCC_CIER_PLL1RDYIE_Msk

+#define RCC_CIER_PLL2RDYIE_Pos                 (7U)

+#define RCC_CIER_PLL2RDYIE_Msk                 (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */

+#define RCC_CIER_PLL2RDYIE                     RCC_CIER_PLL2RDYIE_Msk

+#define RCC_CIER_PLL3RDYIE_Pos                 (8U)

+#define RCC_CIER_PLL3RDYIE_Msk                 (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */

+#define RCC_CIER_PLL3RDYIE                     RCC_CIER_PLL3RDYIE_Msk

+#define RCC_CIER_LSECSSIE_Pos                  (9U)

+#define RCC_CIER_LSECSSIE_Msk                  (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */

+#define RCC_CIER_LSECSSIE                      RCC_CIER_LSECSSIE_Msk

+

+/********************  Bit definition for RCC_CIFR register  ******************/

+#define RCC_CIFR_LSIRDYF_Pos                   (0U)

+#define RCC_CIFR_LSIRDYF_Msk                   (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */

+#define RCC_CIFR_LSIRDYF                       RCC_CIFR_LSIRDYF_Msk

+#define RCC_CIFR_LSERDYF_Pos                   (1U)

+#define RCC_CIFR_LSERDYF_Msk                   (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */

+#define RCC_CIFR_LSERDYF                       RCC_CIFR_LSERDYF_Msk

+#define RCC_CIFR_HSIRDYF_Pos                   (2U)

+#define RCC_CIFR_HSIRDYF_Msk                   (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */

+#define RCC_CIFR_HSIRDYF                       RCC_CIFR_HSIRDYF_Msk

+#define RCC_CIFR_HSERDYF_Pos                   (3U)

+#define RCC_CIFR_HSERDYF_Msk                   (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */

+#define RCC_CIFR_HSERDYF                       RCC_CIFR_HSERDYF_Msk

+#define RCC_CIFR_CSIRDYF_Pos                   (4U)

+#define RCC_CIFR_CSIRDYF_Msk                   (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */

+#define RCC_CIFR_CSIRDYF                       RCC_CIFR_CSIRDYF_Msk

+#define RCC_CIFR_HSI48RDYF_Pos                 (5U)

+#define RCC_CIFR_HSI48RDYF_Msk                 (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */

+#define RCC_CIFR_HSI48RDYF                     RCC_CIFR_HSI48RDYF_Msk

+#define RCC_CIFR_PLLRDYF_Pos                   (6U)

+#define RCC_CIFR_PLLRDYF_Msk                   (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */

+#define RCC_CIFR_PLLRDYF                       RCC_CIFR_PLLRDYF_Msk

+#define RCC_CIFR_PLL2RDYF_Pos                  (7U)

+#define RCC_CIFR_PLL2RDYF_Msk                  (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */

+#define RCC_CIFR_PLL2RDYF                      RCC_CIFR_PLL2RDYF_Msk

+#define RCC_CIFR_PLL3RDYF_Pos                  (8U)

+#define RCC_CIFR_PLL3RDYF_Msk                  (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */

+#define RCC_CIFR_PLL3RDYF                      RCC_CIFR_PLL3RDYF_Msk

+#define RCC_CIFR_LSECSSF_Pos                   (9U)

+#define RCC_CIFR_LSECSSF_Msk                   (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */

+#define RCC_CIFR_LSECSSF                       RCC_CIFR_LSECSSF_Msk

+#define RCC_CIFR_HSECSSF_Pos                   (10U)

+#define RCC_CIFR_HSECSSF_Msk                   (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */

+#define RCC_CIFR_HSECSSF                       RCC_CIFR_HSECSSF_Msk

+

+/********************  Bit definition for RCC_CICR register  ******************/

+#define RCC_CICR_LSIRDYC_Pos                   (0U)

+#define RCC_CICR_LSIRDYC_Msk                   (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */

+#define RCC_CICR_LSIRDYC                       RCC_CICR_LSIRDYC_Msk

+#define RCC_CICR_LSERDYC_Pos                   (1U)

+#define RCC_CICR_LSERDYC_Msk                   (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */

+#define RCC_CICR_LSERDYC                       RCC_CICR_LSERDYC_Msk

+#define RCC_CICR_HSIRDYC_Pos                   (2U)

+#define RCC_CICR_HSIRDYC_Msk                   (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */

+#define RCC_CICR_HSIRDYC                       RCC_CICR_HSIRDYC_Msk

+#define RCC_CICR_HSERDYC_Pos                   (3U)

+#define RCC_CICR_HSERDYC_Msk                   (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */

+#define RCC_CICR_HSERDYC                       RCC_CICR_HSERDYC_Msk

+#define RCC_CICR_CSIRDYC_Pos                   (4U)

+#define RCC_CICR_CSIRDYC_Msk                   (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */

+#define RCC_CICR_CSIRDYC                       RCC_CICR_CSIRDYC_Msk

+#define RCC_CICR_HSI48RDYC_Pos                 (5U)

+#define RCC_CICR_HSI48RDYC_Msk                 (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */

+#define RCC_CICR_HSI48RDYC                     RCC_CICR_HSI48RDYC_Msk

+#define RCC_CICR_PLLRDYC_Pos                   (6U)

+#define RCC_CICR_PLLRDYC_Msk                   (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */

+#define RCC_CICR_PLLRDYC                       RCC_CICR_PLLRDYC_Msk

+#define RCC_CICR_PLL2RDYC_Pos                  (7U)

+#define RCC_CICR_PLL2RDYC_Msk                  (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */

+#define RCC_CICR_PLL2RDYC                      RCC_CICR_PLL2RDYC_Msk

+#define RCC_CICR_PLL3RDYC_Pos                  (8U)

+#define RCC_CICR_PLL3RDYC_Msk                  (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */

+#define RCC_CICR_PLL3RDYC                      RCC_CICR_PLL3RDYC_Msk

+#define RCC_CICR_LSECSSC_Pos                   (9U)

+#define RCC_CICR_LSECSSC_Msk                   (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */

+#define RCC_CICR_LSECSSC                       RCC_CICR_LSECSSC_Msk

+#define RCC_CICR_HSECSSC_Pos                   (10U)

+#define RCC_CICR_HSECSSC_Msk                   (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */

+#define RCC_CICR_HSECSSC                       RCC_CICR_HSECSSC_Msk

+

+/********************  Bit definition for RCC_BDCR register  ******************/

+#define RCC_BDCR_LSEON_Pos                     (0U)

+#define RCC_BDCR_LSEON_Msk                     (0x1UL << RCC_BDCR_LSEON_Pos)   /*!< 0x00000001 */

+#define RCC_BDCR_LSEON                         RCC_BDCR_LSEON_Msk

+#define RCC_BDCR_LSERDY_Pos                    (1U)

+#define RCC_BDCR_LSERDY_Msk                    (0x1UL << RCC_BDCR_LSERDY_Pos)  /*!< 0x00000002 */

+#define RCC_BDCR_LSERDY                        RCC_BDCR_LSERDY_Msk

+#define RCC_BDCR_LSEBYP_Pos                    (2U)

+#define RCC_BDCR_LSEBYP_Msk                    (0x1UL << RCC_BDCR_LSEBYP_Pos)  /*!< 0x00000004 */

+#define RCC_BDCR_LSEBYP                        RCC_BDCR_LSEBYP_Msk

+

+#define RCC_BDCR_LSEDRV_Pos                    (3U)

+#define RCC_BDCR_LSEDRV_Msk                    (0x3UL << RCC_BDCR_LSEDRV_Pos)  /*!< 0x00000018 */

+#define RCC_BDCR_LSEDRV                        RCC_BDCR_LSEDRV_Msk

+#define RCC_BDCR_LSEDRV_0                      (0x1UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000008 */

+#define RCC_BDCR_LSEDRV_1                      (0x2UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000010 */

+

+#define RCC_BDCR_LSECSSON_Pos                  (5U)

+#define RCC_BDCR_LSECSSON_Msk                  (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */

+#define RCC_BDCR_LSECSSON                      RCC_BDCR_LSECSSON_Msk

+#define RCC_BDCR_LSECSSD_Pos                   (6U)

+#define RCC_BDCR_LSECSSD_Msk                   (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */

+#define RCC_BDCR_LSECSSD                       RCC_BDCR_LSECSSD_Msk

+#define RCC_BDCR_LSEEXT_Pos                    (7U)

+#define RCC_BDCR_LSEEXT_Msk                    (0x1UL << RCC_BDCR_LSEEXT_Pos)  /*!< 0x00000080 */

+#define RCC_BDCR_LSEEXT                        RCC_BDCR_LSEEXT_Msk

+

+#define RCC_BDCR_RTCSEL_Pos                    (8U)

+#define RCC_BDCR_RTCSEL_Msk                    (0x3UL << RCC_BDCR_RTCSEL_Pos)  /*!< 0x00000300 */

+#define RCC_BDCR_RTCSEL                        RCC_BDCR_RTCSEL_Msk

+#define RCC_BDCR_RTCSEL_0                      (0x1UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000100 */

+#define RCC_BDCR_RTCSEL_1                      (0x2UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000200 */

+

+#define RCC_BDCR_RTCEN_Pos                     (15U)

+#define RCC_BDCR_RTCEN_Msk                     (0x1UL << RCC_BDCR_RTCEN_Pos)   /*!< 0x00008000 */

+#define RCC_BDCR_RTCEN                         RCC_BDCR_RTCEN_Msk

+#define RCC_BDCR_VSWRST_Pos                    (16U)

+#define RCC_BDCR_VSWRST_Msk                    (0x1UL << RCC_BDCR_VSWRST_Pos)   /*!< 0x00010000 */

+#define RCC_BDCR_VSWRST                        RCC_BDCR_VSWRST_Msk

+/* Legacy define */

+#define RCC_BDCR_BDRST_Pos                     RCC_BDCR_VSWRST_Pos

+#define RCC_BDCR_BDRST_Msk                     RCC_BDCR_VSWRST_Msk

+#define RCC_BDCR_BDRST                         RCC_BDCR_VSWRST

+/********************  Bit definition for RCC_CSR register  *******************/

+#define RCC_CSR_LSION_Pos                      (0U)

+#define RCC_CSR_LSION_Msk                      (0x1UL << RCC_CSR_LSION_Pos)    /*!< 0x00000001 */

+#define RCC_CSR_LSION                          RCC_CSR_LSION_Msk

+#define RCC_CSR_LSIRDY_Pos                     (1U)

+#define RCC_CSR_LSIRDY_Msk                     (0x1UL << RCC_CSR_LSIRDY_Pos)   /*!< 0x00000002 */

+#define RCC_CSR_LSIRDY                         RCC_CSR_LSIRDY_Msk

+

+

+/********************  Bit definition for RCC_AHB3ENR register  **************/

+#define RCC_AHB3ENR_MDMAEN_Pos                 (0U)

+#define RCC_AHB3ENR_MDMAEN_Msk                 (0x1UL << RCC_AHB3ENR_MDMAEN_Pos)       /*!< 0x00000001 */

+#define RCC_AHB3ENR_MDMAEN                     RCC_AHB3ENR_MDMAEN_Msk

+#define RCC_AHB3ENR_DMA2DEN_Pos                (4U)

+#define RCC_AHB3ENR_DMA2DEN_Msk                (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos)      /*!< 0x00000010 */

+#define RCC_AHB3ENR_DMA2DEN                    RCC_AHB3ENR_DMA2DEN_Msk

+#define RCC_AHB3ENR_JPGDECEN_Pos               (5U)

+#define RCC_AHB3ENR_JPGDECEN_Msk               (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos)     /*!< 0x00000020 */

+#define RCC_AHB3ENR_JPGDECEN                   RCC_AHB3ENR_JPGDECEN_Msk

+#define RCC_AHB3ENR_FMCEN_Pos                  (12U)

+#define RCC_AHB3ENR_FMCEN_Msk                  (0x1UL << RCC_AHB3ENR_FMCEN_Pos)        /*!< 0x00001000 */

+#define RCC_AHB3ENR_FMCEN                      RCC_AHB3ENR_FMCEN_Msk

+#define RCC_AHB3ENR_OSPI1EN_Pos                (14U)

+#define RCC_AHB3ENR_OSPI1EN_Msk                (0x1UL << RCC_AHB3ENR_OSPI1EN_Pos)      /*!< 0x00004000 */

+#define RCC_AHB3ENR_OSPI1EN                    RCC_AHB3ENR_OSPI1EN_Msk

+#define RCC_AHB3ENR_SDMMC1EN_Pos               (16U)

+#define RCC_AHB3ENR_SDMMC1EN_Msk               (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos)     /*!< 0x00010000 */

+#define RCC_AHB3ENR_SDMMC1EN                   RCC_AHB3ENR_SDMMC1EN_Msk

+#define RCC_AHB3ENR_OSPI2EN_Pos                (19U)

+#define RCC_AHB3ENR_OSPI2EN_Msk                (0x1UL << RCC_AHB3ENR_OSPI2EN_Pos)      /*!< 0x00040000 */

+#define RCC_AHB3ENR_OSPI2EN                    RCC_AHB3ENR_OSPI2EN_Msk

+#define RCC_AHB3ENR_IOMNGREN_Pos               (21U)

+#define RCC_AHB3ENR_IOMNGREN_Msk               (0x1UL << RCC_AHB3ENR_IOMNGREN_Pos)     /*!< 0x00100000 */

+#define RCC_AHB3ENR_IOMNGREN                   RCC_AHB3ENR_IOMNGREN_Msk

+#define RCC_AHB3ENR_OTFDEC1EN_Pos              (22U)

+#define RCC_AHB3ENR_OTFDEC1EN_Msk              (0x1UL << RCC_AHB3ENR_OTFDEC1EN_Pos)    /*!< 0x00200000 */

+#define RCC_AHB3ENR_OTFDEC1EN                  RCC_AHB3ENR_OTFDEC1EN_Msk

+#define RCC_AHB3ENR_OTFDEC2EN_Pos              (23U)

+#define RCC_AHB3ENR_OTFDEC2EN_Msk              (0x1UL << RCC_AHB3ENR_OTFDEC2EN_Pos)    /*!< 0x00400000 */

+#define RCC_AHB3ENR_OTFDEC2EN                  RCC_AHB3ENR_OTFDEC2EN_Msk

+#define RCC_AHB3ENR_GFXMMUEN_Pos               (24U)

+#define RCC_AHB3ENR_GFXMMUEN_Msk               (0x1UL << RCC_AHB3ENR_GFXMMUEN_Pos)     /*!< 0x00800000 */

+#define RCC_AHB3ENR_GFXMMUEN                   RCC_AHB3ENR_GFXMMUEN_Msk

+

+/********************  Bit definition for RCC_AHB1ENR register  ***************/

+#define RCC_AHB1ENR_DMA1EN_Pos                 (0U)

+#define RCC_AHB1ENR_DMA1EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)          /*!< 0x00000001 */

+#define RCC_AHB1ENR_DMA1EN                     RCC_AHB1ENR_DMA1EN_Msk

+#define RCC_AHB1ENR_DMA2EN_Pos                 (1U)

+#define RCC_AHB1ENR_DMA2EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)          /*!< 0x00000002 */

+#define RCC_AHB1ENR_DMA2EN                     RCC_AHB1ENR_DMA2EN_Msk

+#define RCC_AHB1ENR_ADC12EN_Pos                (5U)

+#define RCC_AHB1ENR_ADC12EN_Msk                (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)         /*!< 0x00000020 */

+#define RCC_AHB1ENR_ADC12EN                    RCC_AHB1ENR_ADC12EN_Msk

+#define RCC_AHB1ENR_CRCEN_Pos                  (9U)

+#define RCC_AHB1ENR_CRCEN_Msk                  (0x1UL << RCC_AHB1ENR_CRCEN_Pos)           /*!< 0x00000200 */

+#define RCC_AHB1ENR_CRCEN                      RCC_AHB1ENR_CRCEN_Msk

+#define RCC_AHB1ENR_USB1OTGHSEN_Pos            (25U)

+#define RCC_AHB1ENR_USB1OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos)     /*!< 0x02000000 */

+#define RCC_AHB1ENR_USB1OTGHSEN                RCC_AHB1ENR_USB1OTGHSEN_Msk

+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos        (26U)

+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */

+#define RCC_AHB1ENR_USB1OTGHSULPIEN            RCC_AHB1ENR_USB1OTGHSULPIEN_Msk

+

+/********************  Bit definition for RCC_AHB2ENR register  ***************/

+#define RCC_AHB2ENR_DCMI_PSSIEN_Pos            (0U)

+#define RCC_AHB2ENR_DCMI_PSSIEN_Msk            (0x1UL << RCC_AHB2ENR_DCMI_PSSIEN_Pos)     /*!< 0x00000001 */

+#define RCC_AHB2ENR_DCMI_PSSIEN                RCC_AHB2ENR_DCMI_PSSIEN_Msk

+#define RCC_AHB2ENR_HSEMEN_Pos                 (2U)

+#define RCC_AHB2ENR_HSEMEN_Msk                 (0x1UL << RCC_AHB2ENR_HSEMEN_Pos)          /*!< 0x00000004 */

+#define RCC_AHB2ENR_HSEMEN                     RCC_AHB2ENR_HSEMEN_Msk

+#define RCC_AHB2ENR_CRYPEN_Pos                 (4U)

+#define RCC_AHB2ENR_CRYPEN_Msk                 (0x1UL << RCC_AHB2ENR_CRYPEN_Pos)          /*!< 0x00000010 */

+#define RCC_AHB2ENR_CRYPEN                     RCC_AHB2ENR_CRYPEN_Msk

+#define RCC_AHB2ENR_HASHEN_Pos                 (5U)

+#define RCC_AHB2ENR_HASHEN_Msk                 (0x1UL << RCC_AHB2ENR_HASHEN_Pos)          /*!< 0x00000020 */

+#define RCC_AHB2ENR_HASHEN                     RCC_AHB2ENR_HASHEN_Msk

+#define RCC_AHB2ENR_RNGEN_Pos                  (6U)

+#define RCC_AHB2ENR_RNGEN_Msk                  (0x1UL << RCC_AHB2ENR_RNGEN_Pos)           /*!< 0x00000040 */

+#define RCC_AHB2ENR_RNGEN                      RCC_AHB2ENR_RNGEN_Msk

+#define RCC_AHB2ENR_SDMMC2EN_Pos               (9U)

+#define RCC_AHB2ENR_SDMMC2EN_Msk               (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)        /*!< 0x00000200 */

+#define RCC_AHB2ENR_SDMMC2EN                   RCC_AHB2ENR_SDMMC2EN_Msk

+#define RCC_AHB2ENR_BDMA1EN_Pos                (11U)

+#define RCC_AHB2ENR_BDMA1EN_Msk                (0x1UL << RCC_AHB2ENR_BDMA1EN_Pos)         /*!< 0x00000800 */

+#define RCC_AHB2ENR_BDMA1EN                    RCC_AHB2ENR_BDMA1EN_Msk

+#define RCC_AHB2ENR_AHBSRAM1EN_Pos             (29U)

+#define RCC_AHB2ENR_AHBSRAM1EN_Msk             (0x1UL << RCC_AHB2ENR_AHBSRAM1EN_Pos)       /*!< 0x20000000 */

+#define RCC_AHB2ENR_AHBSRAM1EN                 RCC_AHB2ENR_AHBSRAM1EN_Msk

+#define RCC_AHB2ENR_AHBSRAM2EN_Pos             (30U)

+#define RCC_AHB2ENR_AHBSRAM2EN_Msk             (0x1UL << RCC_AHB2ENR_AHBSRAM2EN_Pos)       /*!< 0x40000000 */

+#define RCC_AHB2ENR_AHBSRAM2EN                 RCC_AHB2ENR_AHBSRAM2EN_Msk

+

+/* Legacy define */

+#define RCC_AHB2ENR_DCMIEN_Pos                 RCC_AHB2ENR_DCMI_PSSIEN_Pos

+#define RCC_AHB2ENR_DCMIEN_Msk                 RCC_AHB2ENR_DCMI_PSSIEN_Msk

+#define RCC_AHB2ENR_DCMIEN                     RCC_AHB2ENR_DCMI_PSSIEN

+

+/********************  Bit definition for RCC_AHB4ENR register  ******************/

+#define RCC_AHB4ENR_GPIOAEN_Pos                (0U)

+#define RCC_AHB4ENR_GPIOAEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)         /*!< 0x00000001 */

+#define RCC_AHB4ENR_GPIOAEN                    RCC_AHB4ENR_GPIOAEN_Msk

+#define RCC_AHB4ENR_GPIOBEN_Pos                (1U)

+#define RCC_AHB4ENR_GPIOBEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)         /*!< 0x00000002 */

+#define RCC_AHB4ENR_GPIOBEN                    RCC_AHB4ENR_GPIOBEN_Msk

+#define RCC_AHB4ENR_GPIOCEN_Pos                (2U)

+#define RCC_AHB4ENR_GPIOCEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)         /*!< 0x00000004 */

+#define RCC_AHB4ENR_GPIOCEN                    RCC_AHB4ENR_GPIOCEN_Msk

+#define RCC_AHB4ENR_GPIODEN_Pos                (3U)

+#define RCC_AHB4ENR_GPIODEN_Msk                (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)         /*!< 0x00000008 */

+#define RCC_AHB4ENR_GPIODEN                    RCC_AHB4ENR_GPIODEN_Msk

+#define RCC_AHB4ENR_GPIOEEN_Pos                (4U)

+#define RCC_AHB4ENR_GPIOEEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)         /*!< 0x00000010 */

+#define RCC_AHB4ENR_GPIOEEN                    RCC_AHB4ENR_GPIOEEN_Msk

+#define RCC_AHB4ENR_GPIOFEN_Pos                (5U)

+#define RCC_AHB4ENR_GPIOFEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)         /*!< 0x00000020 */

+#define RCC_AHB4ENR_GPIOFEN                    RCC_AHB4ENR_GPIOFEN_Msk

+#define RCC_AHB4ENR_GPIOGEN_Pos                (6U)

+#define RCC_AHB4ENR_GPIOGEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)         /*!< 0x00000040 */

+#define RCC_AHB4ENR_GPIOGEN                    RCC_AHB4ENR_GPIOGEN_Msk

+#define RCC_AHB4ENR_GPIOHEN_Pos                (7U)

+#define RCC_AHB4ENR_GPIOHEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)         /*!< 0x00000080 */

+#define RCC_AHB4ENR_GPIOHEN                    RCC_AHB4ENR_GPIOHEN_Msk

+#define RCC_AHB4ENR_GPIOIEN_Pos                (8U)

+#define RCC_AHB4ENR_GPIOIEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos)         /*!< 0x00000100 */

+#define RCC_AHB4ENR_GPIOIEN                    RCC_AHB4ENR_GPIOIEN_Msk

+#define RCC_AHB4ENR_GPIOJEN_Pos                (9U)

+#define RCC_AHB4ENR_GPIOJEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos)         /*!< 0x00000200 */

+#define RCC_AHB4ENR_GPIOJEN                    RCC_AHB4ENR_GPIOJEN_Msk

+#define RCC_AHB4ENR_GPIOKEN_Pos                (10U)

+#define RCC_AHB4ENR_GPIOKEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos)         /*!< 0x00000400 */

+#define RCC_AHB4ENR_GPIOKEN                    RCC_AHB4ENR_GPIOKEN_Msk

+#define RCC_AHB4ENR_BDMA2EN_Pos                (21U)

+#define RCC_AHB4ENR_BDMA2EN_Msk                (0x1UL << RCC_AHB4ENR_BDMA2EN_Pos)         /*!< 0x00080000 */

+#define RCC_AHB4ENR_BDMA2EN                    RCC_AHB4ENR_BDMA2EN_Msk

+#define RCC_AHB4ENR_BKPRAMEN_Pos               (28U)

+#define RCC_AHB4ENR_BKPRAMEN_Msk               (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)        /*!< 0x10000000 */

+#define RCC_AHB4ENR_BKPRAMEN                   RCC_AHB4ENR_BKPRAMEN_Msk

+#define RCC_AHB4ENR_SRDSRAMEN_Pos              (29U)

+#define RCC_AHB4ENR_SRDSRAMEN_Msk              (0x1UL << RCC_AHB4ENR_SRDSRAMEN_Pos)       /*!< 0x20000000 */

+#define RCC_AHB4ENR_SRDSRAMEN                  RCC_AHB4ENR_SRDSRAMEN_Msk

+

+/********************  Bit definition for RCC_APB3ENR register  ******************/

+#define RCC_APB3ENR_LTDCEN_Pos                 (3U)

+#define RCC_APB3ENR_LTDCEN_Msk                 (0x1UL << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */

+#define RCC_APB3ENR_LTDCEN                     RCC_APB3ENR_LTDCEN_Msk

+#define RCC_APB3ENR_WWDGEN_Pos                 (6U)

+#define RCC_APB3ENR_WWDGEN_Msk                 (0x1UL << RCC_APB3ENR_WWDGEN_Pos) /*!< 0x00000040 */

+#define RCC_APB3ENR_WWDGEN                     RCC_APB3ENR_WWDGEN_Msk

+

+/* Legacy define */

+#define RCC_APB3ENR_WWDG1EN_Pos                 RCC_APB3ENR_WWDGEN_Pos

+#define RCC_APB3ENR_WWDG1EN_Msk                 RCC_APB3ENR_WWDGEN_Msk

+#define RCC_APB3ENR_WWDG1EN                     RCC_APB3ENR_WWDGEN

+/********************  Bit definition for RCC_APB1LENR register  ******************/

+

+#define RCC_APB1LENR_TIM2EN_Pos                (0U)

+#define RCC_APB1LENR_TIM2EN_Msk                (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */

+#define RCC_APB1LENR_TIM2EN                    RCC_APB1LENR_TIM2EN_Msk

+#define RCC_APB1LENR_TIM3EN_Pos                (1U)

+#define RCC_APB1LENR_TIM3EN_Msk                (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */

+#define RCC_APB1LENR_TIM3EN                    RCC_APB1LENR_TIM3EN_Msk

+#define RCC_APB1LENR_TIM4EN_Pos                (2U)

+#define RCC_APB1LENR_TIM4EN_Msk                (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */

+#define RCC_APB1LENR_TIM4EN                    RCC_APB1LENR_TIM4EN_Msk

+#define RCC_APB1LENR_TIM5EN_Pos                (3U)

+#define RCC_APB1LENR_TIM5EN_Msk                (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */

+#define RCC_APB1LENR_TIM5EN                    RCC_APB1LENR_TIM5EN_Msk

+#define RCC_APB1LENR_TIM6EN_Pos                (4U)

+#define RCC_APB1LENR_TIM6EN_Msk                (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */

+#define RCC_APB1LENR_TIM6EN                    RCC_APB1LENR_TIM6EN_Msk

+#define RCC_APB1LENR_TIM7EN_Pos                (5U)

+#define RCC_APB1LENR_TIM7EN_Msk                (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */

+#define RCC_APB1LENR_TIM7EN                    RCC_APB1LENR_TIM7EN_Msk

+#define RCC_APB1LENR_TIM12EN_Pos               (6U)

+#define RCC_APB1LENR_TIM12EN_Msk               (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */

+#define RCC_APB1LENR_TIM12EN                   RCC_APB1LENR_TIM12EN_Msk

+#define RCC_APB1LENR_TIM13EN_Pos               (7U)

+#define RCC_APB1LENR_TIM13EN_Msk               (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */

+#define RCC_APB1LENR_TIM13EN                   RCC_APB1LENR_TIM13EN_Msk

+#define RCC_APB1LENR_TIM14EN_Pos               (8U)

+#define RCC_APB1LENR_TIM14EN_Msk               (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */

+#define RCC_APB1LENR_TIM14EN                   RCC_APB1LENR_TIM14EN_Msk

+#define RCC_APB1LENR_LPTIM1EN_Pos              (9U)

+#define RCC_APB1LENR_LPTIM1EN_Msk              (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */

+#define RCC_APB1LENR_LPTIM1EN                  RCC_APB1LENR_LPTIM1EN_Msk

+

+

+#define RCC_APB1LENR_SPI2EN_Pos                (14U)

+#define RCC_APB1LENR_SPI2EN_Msk                (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */

+#define RCC_APB1LENR_SPI2EN                    RCC_APB1LENR_SPI2EN_Msk

+#define RCC_APB1LENR_SPI3EN_Pos                (15U)

+#define RCC_APB1LENR_SPI3EN_Msk                (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */

+#define RCC_APB1LENR_SPI3EN                    RCC_APB1LENR_SPI3EN_Msk

+#define RCC_APB1LENR_SPDIFRXEN_Pos             (16U)

+#define RCC_APB1LENR_SPDIFRXEN_Msk             (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */

+#define RCC_APB1LENR_SPDIFRXEN                 RCC_APB1LENR_SPDIFRXEN_Msk

+#define RCC_APB1LENR_USART2EN_Pos              (17U)

+#define RCC_APB1LENR_USART2EN_Msk              (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */

+#define RCC_APB1LENR_USART2EN                  RCC_APB1LENR_USART2EN_Msk

+#define RCC_APB1LENR_USART3EN_Pos              (18U)

+#define RCC_APB1LENR_USART3EN_Msk              (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */

+#define RCC_APB1LENR_USART3EN                  RCC_APB1LENR_USART3EN_Msk

+#define RCC_APB1LENR_UART4EN_Pos               (19U)

+#define RCC_APB1LENR_UART4EN_Msk               (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */

+#define RCC_APB1LENR_UART4EN                   RCC_APB1LENR_UART4EN_Msk

+#define RCC_APB1LENR_UART5EN_Pos               (20U)

+#define RCC_APB1LENR_UART5EN_Msk               (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */

+#define RCC_APB1LENR_UART5EN                   RCC_APB1LENR_UART5EN_Msk

+#define RCC_APB1LENR_I2C1EN_Pos                (21U)

+#define RCC_APB1LENR_I2C1EN_Msk                (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */

+#define RCC_APB1LENR_I2C1EN                    RCC_APB1LENR_I2C1EN_Msk

+#define RCC_APB1LENR_I2C2EN_Pos                (22U)

+#define RCC_APB1LENR_I2C2EN_Msk                (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */

+#define RCC_APB1LENR_I2C2EN                    RCC_APB1LENR_I2C2EN_Msk

+#define RCC_APB1LENR_I2C3EN_Pos                (23U)

+#define RCC_APB1LENR_I2C3EN_Msk                (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */

+#define RCC_APB1LENR_I2C3EN                    RCC_APB1LENR_I2C3EN_Msk

+#define RCC_APB1LENR_CECEN_Pos                 (27U)

+#define RCC_APB1LENR_CECEN_Msk                 (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */

+#define RCC_APB1LENR_CECEN                     RCC_APB1LENR_CECEN_Msk

+#define RCC_APB1LENR_DAC12EN_Pos               (29U)

+#define RCC_APB1LENR_DAC12EN_Msk               (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */

+#define RCC_APB1LENR_DAC12EN                   RCC_APB1LENR_DAC12EN_Msk

+#define RCC_APB1LENR_UART7EN_Pos               (30U)

+#define RCC_APB1LENR_UART7EN_Msk               (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */

+#define RCC_APB1LENR_UART7EN                   RCC_APB1LENR_UART7EN_Msk

+#define RCC_APB1LENR_UART8EN_Pos               (31U)

+#define RCC_APB1LENR_UART8EN_Msk               (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */

+#define RCC_APB1LENR_UART8EN                   RCC_APB1LENR_UART8EN_Msk

+

+/* Legacy define */

+#define RCC_APB1LENR_HDMICECEN_Pos             RCC_APB1LENR_CECEN_Pos

+#define RCC_APB1LENR_HDMICECEN_Msk             RCC_APB1LENR_CECEN_Msk

+#define RCC_APB1LENR_HDMICECEN                 RCC_APB1LENR_CECEN

+/********************  Bit definition for RCC_APB1HENR register  ******************/

+#define RCC_APB1HENR_CRSEN_Pos                 (1U)

+#define RCC_APB1HENR_CRSEN_Msk                 (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1HENR_CRSEN                     RCC_APB1HENR_CRSEN_Msk

+#define RCC_APB1HENR_SWPMIEN_Pos               (2U)

+#define RCC_APB1HENR_SWPMIEN_Msk               (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1HENR_SWPMIEN                   RCC_APB1HENR_SWPMIEN_Msk

+#define RCC_APB1HENR_OPAMPEN_Pos               (4U)

+#define RCC_APB1HENR_OPAMPEN_Msk               (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1HENR_OPAMPEN                   RCC_APB1HENR_OPAMPEN_Msk

+#define RCC_APB1HENR_MDIOSEN_Pos               (5U)

+#define RCC_APB1HENR_MDIOSEN_Msk               (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1HENR_MDIOSEN                   RCC_APB1HENR_MDIOSEN_Msk

+#define RCC_APB1HENR_FDCANEN_Pos               (8U)

+#define RCC_APB1HENR_FDCANEN_Msk               (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1HENR_FDCANEN                   RCC_APB1HENR_FDCANEN_Msk

+

+/********************  Bit definition for RCC_APB2ENR register  ******************/

+#define RCC_APB2ENR_TIM1EN_Pos                 (0U)

+#define RCC_APB2ENR_TIM1EN_Msk                 (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */

+#define RCC_APB2ENR_TIM1EN                     RCC_APB2ENR_TIM1EN_Msk

+#define RCC_APB2ENR_TIM8EN_Pos                 (1U)

+#define RCC_APB2ENR_TIM8EN_Msk                 (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */

+#define RCC_APB2ENR_TIM8EN                     RCC_APB2ENR_TIM8EN_Msk

+#define RCC_APB2ENR_USART1EN_Pos               (4U)

+#define RCC_APB2ENR_USART1EN_Msk               (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */

+#define RCC_APB2ENR_USART1EN                   RCC_APB2ENR_USART1EN_Msk

+#define RCC_APB2ENR_USART6EN_Pos               (5U)

+#define RCC_APB2ENR_USART6EN_Msk               (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */

+#define RCC_APB2ENR_USART6EN                   RCC_APB2ENR_USART6EN_Msk

+#define RCC_APB2ENR_UART9EN_Pos                (6U)

+#define RCC_APB2ENR_UART9EN_Msk                (0x1UL << RCC_APB2ENR_UART9EN_Pos) /*!< 0x00000040 */

+#define RCC_APB2ENR_UART9EN                    RCC_APB2ENR_UART9EN_Msk

+#define RCC_APB2ENR_USART10EN_Pos              (7U)

+#define RCC_APB2ENR_USART10EN_Msk              (0x1UL << RCC_APB2ENR_USART10EN_Pos) /*!< 0x00000080 */

+#define RCC_APB2ENR_USART10EN                   RCC_APB2ENR_USART10EN_Msk

+#define RCC_APB2ENR_SPI1EN_Pos                 (12U)

+#define RCC_APB2ENR_SPI1EN_Msk                 (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */

+#define RCC_APB2ENR_SPI1EN                     RCC_APB2ENR_SPI1EN_Msk

+#define RCC_APB2ENR_SPI4EN_Pos                 (13U)

+#define RCC_APB2ENR_SPI4EN_Msk                 (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */

+#define RCC_APB2ENR_SPI4EN                     RCC_APB2ENR_SPI4EN_Msk

+#define RCC_APB2ENR_TIM15EN_Pos                (16U)

+#define RCC_APB2ENR_TIM15EN_Msk                (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */

+#define RCC_APB2ENR_TIM15EN                    RCC_APB2ENR_TIM15EN_Msk

+#define RCC_APB2ENR_TIM16EN_Pos                (17U)

+#define RCC_APB2ENR_TIM16EN_Msk                (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */

+#define RCC_APB2ENR_TIM16EN                    RCC_APB2ENR_TIM16EN_Msk

+#define RCC_APB2ENR_TIM17EN_Pos                (18U)

+#define RCC_APB2ENR_TIM17EN_Msk                (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */

+#define RCC_APB2ENR_TIM17EN                    RCC_APB2ENR_TIM17EN_Msk

+#define RCC_APB2ENR_SPI5EN_Pos                 (20U)

+#define RCC_APB2ENR_SPI5EN_Msk                 (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */

+#define RCC_APB2ENR_SPI5EN                     RCC_APB2ENR_SPI5EN_Msk

+#define RCC_APB2ENR_SAI1EN_Pos                 (22U)

+#define RCC_APB2ENR_SAI1EN_Msk                 (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */

+#define RCC_APB2ENR_SAI1EN                     RCC_APB2ENR_SAI1EN_Msk

+#define RCC_APB2ENR_SAI2EN_Pos                 (23U)

+#define RCC_APB2ENR_SAI2EN_Msk                 (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */

+#define RCC_APB2ENR_SAI2EN                     RCC_APB2ENR_SAI2EN_Msk

+#define RCC_APB2ENR_DFSDM1EN_Pos               (30U)

+#define RCC_APB2ENR_DFSDM1EN_Msk               (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x40000000 */

+#define RCC_APB2ENR_DFSDM1EN                   RCC_APB2ENR_DFSDM1EN_Msk

+

+/********************  Bit definition for RCC_APB4ENR register  ******************/

+#define RCC_APB4ENR_SYSCFGEN_Pos               (1U)

+#define RCC_APB4ENR_SYSCFGEN_Msk               (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */

+#define RCC_APB4ENR_SYSCFGEN                   RCC_APB4ENR_SYSCFGEN_Msk

+#define RCC_APB4ENR_LPUART1EN_Pos              (3U)

+#define RCC_APB4ENR_LPUART1EN_Msk              (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */

+#define RCC_APB4ENR_LPUART1EN                  RCC_APB4ENR_LPUART1EN_Msk

+#define RCC_APB4ENR_SPI6EN_Pos                 (5U)

+#define RCC_APB4ENR_SPI6EN_Msk                 (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */

+#define RCC_APB4ENR_SPI6EN                     RCC_APB4ENR_SPI6EN_Msk

+#define RCC_APB4ENR_I2C4EN_Pos                 (7U)

+#define RCC_APB4ENR_I2C4EN_Msk                 (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */

+#define RCC_APB4ENR_I2C4EN                     RCC_APB4ENR_I2C4EN_Msk

+#define RCC_APB4ENR_LPTIM2EN_Pos               (9U)

+#define RCC_APB4ENR_LPTIM2EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */

+#define RCC_APB4ENR_LPTIM2EN                   RCC_APB4ENR_LPTIM2EN_Msk

+#define RCC_APB4ENR_LPTIM3EN_Pos               (10U)

+#define RCC_APB4ENR_LPTIM3EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */

+#define RCC_APB4ENR_LPTIM3EN                   RCC_APB4ENR_LPTIM3EN_Msk

+#define RCC_APB4ENR_DAC2EN_Pos                 (13U)

+#define RCC_APB4ENR_DAC2EN_Msk                 (0x1UL << RCC_APB4ENR_DAC2EN_Pos) /*!< 0x00002000 */

+#define RCC_APB4ENR_DAC2EN                     RCC_APB4ENR_DAC2EN_Msk

+#define RCC_APB4ENR_COMP12EN_Pos               (14U)

+#define RCC_APB4ENR_COMP12EN_Msk               (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */

+#define RCC_APB4ENR_COMP12EN                   RCC_APB4ENR_COMP12EN_Msk

+#define RCC_APB4ENR_VREFEN_Pos                 (15U)

+#define RCC_APB4ENR_VREFEN_Msk                 (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */

+#define RCC_APB4ENR_VREFEN                     RCC_APB4ENR_VREFEN_Msk

+#define RCC_APB4ENR_RTCAPBEN_Pos               (16U)

+#define RCC_APB4ENR_RTCAPBEN_Msk               (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */

+#define RCC_APB4ENR_RTCAPBEN                   RCC_APB4ENR_RTCAPBEN_Msk

+

+#define RCC_APB4ENR_DTSEN_Pos                  (26U)

+#define RCC_APB4ENR_DTSEN_Msk                  (0x1UL << RCC_APB4ENR_DTSEN_Pos) /*!< 0x04000000 */

+#define RCC_APB4ENR_DTSEN                      RCC_APB4ENR_DTSEN_Msk

+#define RCC_APB4ENR_DFSDM2EN_Pos               (27U)

+#define RCC_APB4ENR_DFSDM2EN_Msk               (0x1UL << RCC_APB4ENR_DFSDM2EN_Pos) /*!< 0x08000000 */

+#define RCC_APB4ENR_DFSDM2EN                   RCC_APB4ENR_DFSDM2EN_Msk

+

+/********************  Bit definition for RCC_AHB3RSTR register  ***************/

+#define RCC_AHB3RSTR_MDMARST_Pos               (0U)

+#define RCC_AHB3RSTR_MDMARST_Msk               (0x1UL << RCC_AHB3RSTR_MDMARST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB3RSTR_MDMARST                   RCC_AHB3RSTR_MDMARST_Msk

+#define RCC_AHB3RSTR_DMA2DRST_Pos              (4U)

+#define RCC_AHB3RSTR_DMA2DRST_Msk              (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos)     /*!< 0x00000010 */

+#define RCC_AHB3RSTR_DMA2DRST                  RCC_AHB3RSTR_DMA2DRST_Msk

+#define RCC_AHB3RSTR_JPGDECRST_Pos             (5U)

+#define RCC_AHB3RSTR_JPGDECRST_Msk             (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos)    /*!< 0x00000020 */

+#define RCC_AHB3RSTR_JPGDECRST                 RCC_AHB3RSTR_JPGDECRST_Msk

+#define RCC_AHB3RSTR_FMCRST_Pos                (12U)

+#define RCC_AHB3RSTR_FMCRST_Msk                (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)      /*!< 0x00001000 */

+#define RCC_AHB3RSTR_FMCRST                    RCC_AHB3RSTR_FMCRST_Msk

+#define RCC_AHB3RSTR_OSPI1RST_Pos              (14U)

+#define RCC_AHB3RSTR_OSPI1RST_Msk              (0x1UL << RCC_AHB3RSTR_OSPI1RST_Pos)    /*!< 0x00004000 */

+#define RCC_AHB3RSTR_OSPI1RST                   RCC_AHB3RSTR_OSPI1RST_Msk

+#define RCC_AHB3RSTR_SDMMC1RST_Pos             (16U)

+#define RCC_AHB3RSTR_SDMMC1RST_Msk             (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos)   /*!< 0x00010000 */

+#define RCC_AHB3RSTR_SDMMC1RST                 RCC_AHB3RSTR_SDMMC1RST_Msk

+#define RCC_AHB3RSTR_OSPI2RST_Pos              (19U)

+#define RCC_AHB3RSTR_OSPI2RST_Msk              (0x1UL << RCC_AHB3RSTR_OSPI2RST_Pos)    /*!< 0x00008000 */

+#define RCC_AHB3RSTR_OSPI2RST                  RCC_AHB3RSTR_OSPI2RST_Msk

+#define RCC_AHB3RSTR_IOMNGRRST_Pos             (21U)

+#define RCC_AHB3RSTR_IOMNGRRST_Msk             (0x1UL << RCC_AHB3RSTR_IOMNGRRST_Pos)   /*!< 0x00020000 */

+#define RCC_AHB3RSTR_IOMNGRRST                 RCC_AHB3RSTR_IOMNGRRST_Msk

+#define RCC_AHB3RSTR_OTFDEC1RST_Pos            (22U)

+#define RCC_AHB3RSTR_OTFDEC1RST_Msk            (0x1UL << RCC_AHB3RSTR_OTFDEC1RST_Pos)  /*!< 0x00040000 */

+#define RCC_AHB3RSTR_OTFDEC1RST                RCC_AHB3RSTR_OTFDEC1RST_Msk

+#define RCC_AHB3RSTR_OTFDEC2RST_Pos            (23U)

+#define RCC_AHB3RSTR_OTFDEC2RST_Msk            (0x1UL << RCC_AHB3RSTR_OTFDEC2RST_Pos)  /*!< 0x00080000 */

+#define RCC_AHB3RSTR_OTFDEC2RST                RCC_AHB3RSTR_OTFDEC2RST_Msk

+#define RCC_AHB3RSTR_GFXMMURST_Pos             (24U)

+#define RCC_AHB3RSTR_GFXMMURST_Msk             (0x1UL << RCC_AHB3RSTR_GFXMMURST_Pos)   /*!< 0x00100000 */

+#define RCC_AHB3RSTR_GFXMMURST                 RCC_AHB3RSTR_GFXMMURST_Msk

+

+

+/********************  Bit definition for RCC_AHB1RSTR register  ***************/

+#define RCC_AHB1RSTR_DMA1RST_Pos               (0U)

+#define RCC_AHB1RSTR_DMA1RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB1RSTR_DMA1RST                   RCC_AHB1RSTR_DMA1RST_Msk

+#define RCC_AHB1RSTR_DMA2RST_Pos               (1U)

+#define RCC_AHB1RSTR_DMA2RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)      /*!< 0x00000002 */

+#define RCC_AHB1RSTR_DMA2RST                   RCC_AHB1RSTR_DMA2RST_Msk

+#define RCC_AHB1RSTR_ADC12RST_Pos              (5U)

+#define RCC_AHB1RSTR_ADC12RST_Msk              (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)     /*!< 0x00000020 */

+#define RCC_AHB1RSTR_ADC12RST                  RCC_AHB1RSTR_ADC12RST_Msk

+#define RCC_AHB1RSTR_CRCRST_Pos                (9U)

+#define RCC_AHB1RSTR_CRCRST_Msk                (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)       /*!< 0x00000200 */

+#define RCC_AHB1RSTR_CRCRST                    RCC_AHB1RSTR_CRCRST_Msk

+#define RCC_AHB1RSTR_USB1OTGHSRST_Pos          (25U)

+#define RCC_AHB1RSTR_USB1OTGHSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */

+#define RCC_AHB1RSTR_USB1OTGHSRST              RCC_AHB1RSTR_USB1OTGHSRST_Msk

+

+/********************  Bit definition for RCC_AHB2RSTR register  ***************/

+#define RCC_AHB2RSTR_DCMI_PSSIRST_Pos          (0U)

+#define RCC_AHB2RSTR_DCMI_PSSIRST_Msk          (0x1UL << RCC_AHB2RSTR_DCMI_PSSIRST_Pos)  /*!< 0x00000001 */

+#define RCC_AHB2RSTR_DCMI_PSSIRST              RCC_AHB2RSTR_DCMI_PSSIRST_Msk

+#define RCC_AHB2RSTR_HSEMRST_Pos               (2U)

+#define RCC_AHB2RSTR_HSEMRST_Msk               (0x1UL << RCC_AHB2RSTR_HSEMRST_Pos)       /*!< 0x00000004 */

+#define RCC_AHB2RSTR_HSEMRST                   RCC_AHB2RSTR_HSEMRST_Msk

+#define RCC_AHB2RSTR_CRYPRST_Pos               (4U)

+#define RCC_AHB2RSTR_CRYPRST_Msk               (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos)       /*!< 0x00000010 */

+#define RCC_AHB2RSTR_CRYPRST                   RCC_AHB2RSTR_CRYPRST_Msk

+#define RCC_AHB2RSTR_HASHRST_Pos               (5U)

+#define RCC_AHB2RSTR_HASHRST_Msk               (0x1UL << RCC_AHB2RSTR_HASHRST_Pos)       /*!< 0x00000020 */

+#define RCC_AHB2RSTR_HASHRST                   RCC_AHB2RSTR_HASHRST_Msk

+#define RCC_AHB2RSTR_RNGRST_Pos                (6U)

+#define RCC_AHB2RSTR_RNGRST_Msk                (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)        /*!< 0x00000040 */

+#define RCC_AHB2RSTR_RNGRST                    RCC_AHB2RSTR_RNGRST_Msk

+#define RCC_AHB2RSTR_SDMMC2RST_Pos             (9U)

+#define RCC_AHB2RSTR_SDMMC2RST_Msk             (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)     /*!< 0x00000200 */

+#define RCC_AHB2RSTR_SDMMC2RST                 RCC_AHB2RSTR_SDMMC2RST_Msk

+#define RCC_AHB2RSTR_BDMA1RST_Pos              (11U)

+#define RCC_AHB2RSTR_BDMA1RST_Msk              (0x1UL << RCC_AHB2RSTR_BDMA1RST_Pos)      /*!< 0x00000200 */

+#define RCC_AHB2RSTR_BDMA1RST                  RCC_AHB2RSTR_BDMA1RST_Msk

+

+/* Legacy define */

+#define RCC_AHB2RSTR_DCMIRST_Pos               RCC_AHB2RSTR_DCMI_PSSIRST_Pos

+#define RCC_AHB2RSTR_DCMIRST_Msk               RCC_AHB2RSTR_DCMI_PSSIRST_Msk

+#define RCC_AHB2RSTR_DCMIRST                   RCC_AHB2RSTR_DCMI_PSSIRST

+/********************  Bit definition for RCC_AHB4RSTR register  ******************/

+#define RCC_AHB4RSTR_GPIOARST_Pos              (0U)

+#define RCC_AHB4RSTR_GPIOARST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB4RSTR_GPIOARST                  RCC_AHB4RSTR_GPIOARST_Msk

+#define RCC_AHB4RSTR_GPIOBRST_Pos              (1U)

+#define RCC_AHB4RSTR_GPIOBRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)      /*!< 0x00000002 */

+#define RCC_AHB4RSTR_GPIOBRST                  RCC_AHB4RSTR_GPIOBRST_Msk

+#define RCC_AHB4RSTR_GPIOCRST_Pos              (2U)

+#define RCC_AHB4RSTR_GPIOCRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)      /*!< 0x00000004 */

+#define RCC_AHB4RSTR_GPIOCRST                  RCC_AHB4RSTR_GPIOCRST_Msk

+#define RCC_AHB4RSTR_GPIODRST_Pos              (3U)

+#define RCC_AHB4RSTR_GPIODRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)      /*!< 0x00000008 */

+#define RCC_AHB4RSTR_GPIODRST                  RCC_AHB4RSTR_GPIODRST_Msk

+#define RCC_AHB4RSTR_GPIOERST_Pos              (4U)

+#define RCC_AHB4RSTR_GPIOERST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)      /*!< 0x00000010 */

+#define RCC_AHB4RSTR_GPIOERST                  RCC_AHB4RSTR_GPIOERST_Msk

+#define RCC_AHB4RSTR_GPIOFRST_Pos              (5U)

+#define RCC_AHB4RSTR_GPIOFRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)       /*!< 0x00000020 */

+#define RCC_AHB4RSTR_GPIOFRST                  RCC_AHB4RSTR_GPIOFRST_Msk

+#define RCC_AHB4RSTR_GPIOGRST_Pos              (6U)

+#define RCC_AHB4RSTR_GPIOGRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)       /*!< 0x00000040 */

+#define RCC_AHB4RSTR_GPIOGRST                  RCC_AHB4RSTR_GPIOGRST_Msk

+#define RCC_AHB4RSTR_GPIOHRST_Pos              (7U)

+#define RCC_AHB4RSTR_GPIOHRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)       /*!< 0x00000080 */

+#define RCC_AHB4RSTR_GPIOHRST                  RCC_AHB4RSTR_GPIOHRST_Msk

+#define RCC_AHB4RSTR_GPIOIRST_Pos              (8U)

+#define RCC_AHB4RSTR_GPIOIRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos)       /*!< 0x00000100 */

+#define RCC_AHB4RSTR_GPIOIRST                  RCC_AHB4RSTR_GPIOIRST_Msk

+#define RCC_AHB4RSTR_GPIOJRST_Pos              (9U)

+#define RCC_AHB4RSTR_GPIOJRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos)       /*!< 0x00000200 */

+#define RCC_AHB4RSTR_GPIOJRST                  RCC_AHB4RSTR_GPIOJRST_Msk

+#define RCC_AHB4RSTR_GPIOKRST_Pos              (10U)

+#define RCC_AHB4RSTR_GPIOKRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos)       /*!< 0x00000400 */

+#define RCC_AHB4RSTR_GPIOKRST                  RCC_AHB4RSTR_GPIOKRST_Msk

+#define RCC_AHB4RSTR_BDMA2RST_Pos              (21U)

+#define RCC_AHB4RSTR_BDMA2RST_Msk              (0x1UL << RCC_AHB4RSTR_BDMA2RST_Pos)       /*!< 0x00200000 */

+#define RCC_AHB4RSTR_BDMA2RST                   RCC_AHB4RSTR_BDMA2RST_Msk

+

+

+/********************  Bit definition for RCC_APB3RSTR register  ******************/

+#define RCC_APB3RSTR_LTDCRST_Pos               (3U)

+#define RCC_APB3RSTR_LTDCRST_Msk               (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */

+#define RCC_APB3RSTR_LTDCRST                   RCC_APB3RSTR_LTDCRST_Msk

+

+/********************  Bit definition for RCC_APB1LRSTR register  ******************/

+

+#define RCC_APB1LRSTR_TIM2RST_Pos              (0U)

+#define RCC_APB1LRSTR_TIM2RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */

+#define RCC_APB1LRSTR_TIM2RST                  RCC_APB1LRSTR_TIM2RST_Msk

+#define RCC_APB1LRSTR_TIM3RST_Pos              (1U)

+#define RCC_APB1LRSTR_TIM3RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */

+#define RCC_APB1LRSTR_TIM3RST                  RCC_APB1LRSTR_TIM3RST_Msk

+#define RCC_APB1LRSTR_TIM4RST_Pos              (2U)

+#define RCC_APB1LRSTR_TIM4RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */

+#define RCC_APB1LRSTR_TIM4RST                  RCC_APB1LRSTR_TIM4RST_Msk

+#define RCC_APB1LRSTR_TIM5RST_Pos              (3U)

+#define RCC_APB1LRSTR_TIM5RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */

+#define RCC_APB1LRSTR_TIM5RST                  RCC_APB1LRSTR_TIM5RST_Msk

+#define RCC_APB1LRSTR_TIM6RST_Pos              (4U)

+#define RCC_APB1LRSTR_TIM6RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */

+#define RCC_APB1LRSTR_TIM6RST                  RCC_APB1LRSTR_TIM6RST_Msk

+#define RCC_APB1LRSTR_TIM7RST_Pos              (5U)

+#define RCC_APB1LRSTR_TIM7RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */

+#define RCC_APB1LRSTR_TIM7RST                  RCC_APB1LRSTR_TIM7RST_Msk

+#define RCC_APB1LRSTR_TIM12RST_Pos             (6U)

+#define RCC_APB1LRSTR_TIM12RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */

+#define RCC_APB1LRSTR_TIM12RST                 RCC_APB1LRSTR_TIM12RST_Msk

+#define RCC_APB1LRSTR_TIM13RST_Pos             (7U)

+#define RCC_APB1LRSTR_TIM13RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */

+#define RCC_APB1LRSTR_TIM13RST                 RCC_APB1LRSTR_TIM13RST_Msk

+#define RCC_APB1LRSTR_TIM14RST_Pos             (8U)

+#define RCC_APB1LRSTR_TIM14RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */

+#define RCC_APB1LRSTR_TIM14RST                 RCC_APB1LRSTR_TIM14RST_Msk

+#define RCC_APB1LRSTR_LPTIM1RST_Pos            (9U)

+#define RCC_APB1LRSTR_LPTIM1RST_Msk            (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */

+#define RCC_APB1LRSTR_LPTIM1RST                RCC_APB1LRSTR_LPTIM1RST_Msk

+#define RCC_APB1LRSTR_SPI2RST_Pos              (14U)

+#define RCC_APB1LRSTR_SPI2RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */

+#define RCC_APB1LRSTR_SPI2RST                  RCC_APB1LRSTR_SPI2RST_Msk

+#define RCC_APB1LRSTR_SPI3RST_Pos              (15U)

+#define RCC_APB1LRSTR_SPI3RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */

+#define RCC_APB1LRSTR_SPI3RST                  RCC_APB1LRSTR_SPI3RST_Msk

+#define RCC_APB1LRSTR_SPDIFRXRST_Pos           (16U)

+#define RCC_APB1LRSTR_SPDIFRXRST_Msk           (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */

+#define RCC_APB1LRSTR_SPDIFRXRST               RCC_APB1LRSTR_SPDIFRXRST_Msk

+#define RCC_APB1LRSTR_USART2RST_Pos            (17U)

+#define RCC_APB1LRSTR_USART2RST_Msk            (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */

+#define RCC_APB1LRSTR_USART2RST                RCC_APB1LRSTR_USART2RST_Msk

+#define RCC_APB1LRSTR_USART3RST_Pos            (18U)

+#define RCC_APB1LRSTR_USART3RST_Msk            (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */

+#define RCC_APB1LRSTR_USART3RST                RCC_APB1LRSTR_USART3RST_Msk

+#define RCC_APB1LRSTR_UART4RST_Pos             (19U)

+#define RCC_APB1LRSTR_UART4RST_Msk             (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */

+#define RCC_APB1LRSTR_UART4RST                 RCC_APB1LRSTR_UART4RST_Msk

+#define RCC_APB1LRSTR_UART5RST_Pos             (20U)

+#define RCC_APB1LRSTR_UART5RST_Msk             (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */

+#define RCC_APB1LRSTR_UART5RST                 RCC_APB1LRSTR_UART5RST_Msk

+#define RCC_APB1LRSTR_I2C1RST_Pos              (21U)

+#define RCC_APB1LRSTR_I2C1RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */

+#define RCC_APB1LRSTR_I2C1RST                  RCC_APB1LRSTR_I2C1RST_Msk

+#define RCC_APB1LRSTR_I2C2RST_Pos              (22U)

+#define RCC_APB1LRSTR_I2C2RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */

+#define RCC_APB1LRSTR_I2C2RST                  RCC_APB1LRSTR_I2C2RST_Msk

+#define RCC_APB1LRSTR_I2C3RST_Pos              (23U)

+#define RCC_APB1LRSTR_I2C3RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */

+#define RCC_APB1LRSTR_I2C3RST                  RCC_APB1LRSTR_I2C3RST_Msk

+#define RCC_APB1LRSTR_CECRST_Pos               (27U)

+#define RCC_APB1LRSTR_CECRST_Msk               (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */

+#define RCC_APB1LRSTR_CECRST                   RCC_APB1LRSTR_CECRST_Msk

+#define RCC_APB1LRSTR_DAC12RST_Pos             (29U)

+#define RCC_APB1LRSTR_DAC12RST_Msk             (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */

+#define RCC_APB1LRSTR_DAC12RST                 RCC_APB1LRSTR_DAC12RST_Msk

+#define RCC_APB1LRSTR_UART7RST_Pos             (30U)

+#define RCC_APB1LRSTR_UART7RST_Msk             (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */

+#define RCC_APB1LRSTR_UART7RST                 RCC_APB1LRSTR_UART7RST_Msk

+#define RCC_APB1LRSTR_UART8RST_Pos             (31U)

+#define RCC_APB1LRSTR_UART8RST_Msk             (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */

+#define RCC_APB1LRSTR_UART8RST                 RCC_APB1LRSTR_UART8RST_Msk

+

+/* Legacy define */

+#define RCC_APB1LRSTR_HDMICECRST_Pos           RCC_APB1LRSTR_CECRST_Pos

+#define RCC_APB1LRSTR_HDMICECRST_Msk           RCC_APB1LRSTR_CECRST_Msk

+#define RCC_APB1LRSTR_HDMICECRST               RCC_APB1LRSTR_CECRST

+/********************  Bit definition for RCC_APB1HRSTR register  ******************/

+#define RCC_APB1HRSTR_CRSRST_Pos               (1U)

+#define RCC_APB1HRSTR_CRSRST_Msk               (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */

+#define RCC_APB1HRSTR_CRSRST                   RCC_APB1HRSTR_CRSRST_Msk

+#define RCC_APB1HRSTR_SWPMIRST_Pos             (2U)

+#define RCC_APB1HRSTR_SWPMIRST_Msk             (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */

+#define RCC_APB1HRSTR_SWPMIRST                 RCC_APB1HRSTR_SWPMIRST_Msk

+#define RCC_APB1HRSTR_OPAMPRST_Pos             (4U)

+#define RCC_APB1HRSTR_OPAMPRST_Msk             (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */

+#define RCC_APB1HRSTR_OPAMPRST                 RCC_APB1HRSTR_OPAMPRST_Msk

+#define RCC_APB1HRSTR_MDIOSRST_Pos             (5U)

+#define RCC_APB1HRSTR_MDIOSRST_Msk             (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */

+#define RCC_APB1HRSTR_MDIOSRST                 RCC_APB1HRSTR_MDIOSRST_Msk

+#define RCC_APB1HRSTR_FDCANRST_Pos             (8U)

+#define RCC_APB1HRSTR_FDCANRST_Msk             (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */

+#define RCC_APB1HRSTR_FDCANRST                 RCC_APB1HRSTR_FDCANRST_Msk

+

+/********************  Bit definition for RCC_APB2RSTR register  ******************/

+#define RCC_APB2RSTR_TIM1RST_Pos               (0U)

+#define RCC_APB2RSTR_TIM1RST_Msk               (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */

+#define RCC_APB2RSTR_TIM1RST                   RCC_APB2RSTR_TIM1RST_Msk

+#define RCC_APB2RSTR_TIM8RST_Pos               (1U)

+#define RCC_APB2RSTR_TIM8RST_Msk               (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */

+#define RCC_APB2RSTR_TIM8RST                   RCC_APB2RSTR_TIM8RST_Msk

+#define RCC_APB2RSTR_USART1RST_Pos             (4U)

+#define RCC_APB2RSTR_USART1RST_Msk             (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */

+#define RCC_APB2RSTR_USART1RST                 RCC_APB2RSTR_USART1RST_Msk

+#define RCC_APB2RSTR_USART6RST_Pos             (5U)

+#define RCC_APB2RSTR_USART6RST_Msk             (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */

+#define RCC_APB2RSTR_USART6RST                 RCC_APB2RSTR_USART6RST_Msk

+#define RCC_APB2RSTR_UART9RST_Pos              (6U)

+#define RCC_APB2RSTR_UART9RST_Msk              (0x1UL << RCC_APB2RSTR_UART9RST_Pos) /*!< 0x00000040 */

+#define RCC_APB2RSTR_UART9RST                  RCC_APB2RSTR_UART9RST_Msk

+#define RCC_APB2RSTR_USART10RST_Pos            (7U)

+#define RCC_APB2RSTR_USART10RST_Msk            (0x1UL << RCC_APB2RSTR_USART10RST_Pos) /*!< 0x00000080 */

+#define RCC_APB2RSTR_USART10RST                RCC_APB2RSTR_USART10RST_Msk

+#define RCC_APB2RSTR_SPI1RST_Pos               (12U)

+#define RCC_APB2RSTR_SPI1RST_Msk               (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */

+#define RCC_APB2RSTR_SPI1RST                   RCC_APB2RSTR_SPI1RST_Msk

+#define RCC_APB2RSTR_SPI4RST_Pos               (13U)

+#define RCC_APB2RSTR_SPI4RST_Msk               (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */

+#define RCC_APB2RSTR_SPI4RST                   RCC_APB2RSTR_SPI4RST_Msk

+#define RCC_APB2RSTR_TIM15RST_Pos              (16U)

+#define RCC_APB2RSTR_TIM15RST_Msk              (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */

+#define RCC_APB2RSTR_TIM15RST                  RCC_APB2RSTR_TIM15RST_Msk

+#define RCC_APB2RSTR_TIM16RST_Pos              (17U)

+#define RCC_APB2RSTR_TIM16RST_Msk              (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */

+#define RCC_APB2RSTR_TIM16RST                  RCC_APB2RSTR_TIM16RST_Msk

+#define RCC_APB2RSTR_TIM17RST_Pos              (18U)

+#define RCC_APB2RSTR_TIM17RST_Msk              (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */

+#define RCC_APB2RSTR_TIM17RST                  RCC_APB2RSTR_TIM17RST_Msk

+#define RCC_APB2RSTR_SPI5RST_Pos               (20U)

+#define RCC_APB2RSTR_SPI5RST_Msk               (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */

+#define RCC_APB2RSTR_SPI5RST                   RCC_APB2RSTR_SPI5RST_Msk

+#define RCC_APB2RSTR_SAI1RST_Pos               (22U)

+#define RCC_APB2RSTR_SAI1RST_Msk               (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */

+#define RCC_APB2RSTR_SAI1RST                   RCC_APB2RSTR_SAI1RST_Msk

+#define RCC_APB2RSTR_SAI2RST_Pos               (23U)

+#define RCC_APB2RSTR_SAI2RST_Msk               (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */

+#define RCC_APB2RSTR_SAI2RST                   RCC_APB2RSTR_SAI2RST_Msk

+#define RCC_APB2RSTR_DFSDM1RST_Pos             (30U)

+#define RCC_APB2RSTR_DFSDM1RST_Msk             (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */

+#define RCC_APB2RSTR_DFSDM1RST                 RCC_APB2RSTR_DFSDM1RST_Msk

+

+/********************  Bit definition for RCC_APB4RSTR register  ******************/

+#define RCC_APB4RSTR_SYSCFGRST_Pos             (1U)

+#define RCC_APB4RSTR_SYSCFGRST_Msk             (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */

+#define RCC_APB4RSTR_SYSCFGRST                 RCC_APB4RSTR_SYSCFGRST_Msk

+#define RCC_APB4RSTR_LPUART1RST_Pos            (3U)

+#define RCC_APB4RSTR_LPUART1RST_Msk            (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */

+#define RCC_APB4RSTR_LPUART1RST                RCC_APB4RSTR_LPUART1RST_Msk

+#define RCC_APB4RSTR_SPI6RST_Pos               (5U)

+#define RCC_APB4RSTR_SPI6RST_Msk               (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */

+#define RCC_APB4RSTR_SPI6RST                   RCC_APB4RSTR_SPI6RST_Msk

+#define RCC_APB4RSTR_I2C4RST_Pos               (7U)

+#define RCC_APB4RSTR_I2C4RST_Msk               (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */

+#define RCC_APB4RSTR_I2C4RST                   RCC_APB4RSTR_I2C4RST_Msk

+#define RCC_APB4RSTR_LPTIM2RST_Pos             (9U)

+#define RCC_APB4RSTR_LPTIM2RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */

+#define RCC_APB4RSTR_LPTIM2RST                 RCC_APB4RSTR_LPTIM2RST_Msk

+#define RCC_APB4RSTR_LPTIM3RST_Pos             (10U)

+#define RCC_APB4RSTR_LPTIM3RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */

+#define RCC_APB4RSTR_LPTIM3RST                 RCC_APB4RSTR_LPTIM3RST_Msk

+#define RCC_APB4RSTR_DAC2RST_Pos               (13U)

+#define RCC_APB4RSTR_DAC2RST_Msk               (0x1UL << RCC_APB4RSTR_DAC2RST_Pos) /*!< 0x00001000 */

+#define RCC_APB4RSTR_DAC2RST                    RCC_APB4RSTR_DAC2RST_Msk

+#define RCC_APB4RSTR_COMP12RST_Pos             (14U)

+#define RCC_APB4RSTR_COMP12RST_Msk             (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */

+#define RCC_APB4RSTR_COMP12RST                 RCC_APB4RSTR_COMP12RST_Msk

+#define RCC_APB4RSTR_VREFRST_Pos               (15U)

+#define RCC_APB4RSTR_VREFRST_Msk               (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */

+#define RCC_APB4RSTR_VREFRST                   RCC_APB4RSTR_VREFRST_Msk

+

+#define RCC_APB4RSTR_DTSRST_Pos                (26U)

+#define RCC_APB4RSTR_DTSRST_Msk                (0x1UL << RCC_APB4RSTR_DTSRST_Pos) /*!< 0x04000000 */

+#define RCC_APB4RSTR_DTSRST                    RCC_APB4RSTR_DTSRST_Msk

+#define RCC_APB4RSTR_DFSDM2RST_Pos             (27U)

+#define RCC_APB4RSTR_DFSDM2RST_Msk             (0x1UL << RCC_APB4RSTR_DFSDM2RST_Pos) /*!< 0x08000000 */

+#define RCC_APB4RSTR_DFSDM2RST                 RCC_APB4RSTR_DFSDM2RST_Msk

+

+

+/********************  Bit definition for RCC_SRDAMR register  ********************/

+#define RCC_SRDAMR_BDMA2AMEN_Pos               (0U)

+#define RCC_SRDAMR_BDMA2AMEN_Msk               (0x1UL << RCC_SRDAMR_BDMA2AMEN_Pos) /*!< 0x00000001 */

+#define RCC_SRDAMR_BDMA2AMEN                   RCC_SRDAMR_BDMA2AMEN_Msk

+#define RCC_SRDAMR_GPIOAMEN_Pos                (1U)

+#define RCC_SRDAMR_GPIOAMEN_Msk                (0x1UL << RCC_SRDAMR_GPIOAMEN_Pos) /*!< 0x00000001 */

+#define RCC_SRDAMR_GPIOAMEN                    RCC_SRDAMR_GPIOAMEN_Msk

+#define RCC_SRDAMR_LPUART1AMEN_Pos             (3U)

+#define RCC_SRDAMR_LPUART1AMEN_Msk             (0x1UL << RCC_SRDAMR_LPUART1AMEN_Pos) /*!< 0x00000008 */

+#define RCC_SRDAMR_LPUART1AMEN                 RCC_SRDAMR_LPUART1AMEN_Msk

+#define RCC_SRDAMR_SPI6AMEN_Pos                (5U)

+#define RCC_SRDAMR_SPI6AMEN_Msk                (0x1UL << RCC_SRDAMR_SPI6AMEN_Pos) /*!< 0x00000020 */

+#define RCC_SRDAMR_SPI6AMEN                    RCC_SRDAMR_SPI6AMEN_Msk

+#define RCC_SRDAMR_I2C4AMEN_Pos                (7U)

+#define RCC_SRDAMR_I2C4AMEN_Msk                (0x1UL << RCC_SRDAMR_I2C4AMEN_Pos) /*!< 0x00000080 */

+#define RCC_SRDAMR_I2C4AMEN                    RCC_SRDAMR_I2C4AMEN_Msk

+#define RCC_SRDAMR_LPTIM2AMEN_Pos              (9U)

+#define RCC_SRDAMR_LPTIM2AMEN_Msk              (0x1UL << RCC_SRDAMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */

+#define RCC_SRDAMR_LPTIM2AMEN                  RCC_SRDAMR_LPTIM2AMEN_Msk

+#define RCC_SRDAMR_LPTIM3AMEN_Pos              (10U)

+#define RCC_SRDAMR_LPTIM3AMEN_Msk              (0x1UL << RCC_SRDAMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */

+#define RCC_SRDAMR_LPTIM3AMEN                  RCC_SRDAMR_LPTIM3AMEN_Msk

+#define RCC_SRDAMR_DAC2AMEN_Pos                (13U)

+#define RCC_SRDAMR_DAC2AMEN_Msk                (0x1UL << RCC_SRDAMR_DAC2AMEN_Pos) /*!< 0x00004000 */

+#define RCC_SRDAMR_DAC2AMEN                    RCC_SRDAMR_DAC2AMEN_Msk

+#define RCC_SRDAMR_COMP12AMEN_Pos              (14U)

+#define RCC_SRDAMR_COMP12AMEN_Msk              (0x1UL << RCC_SRDAMR_COMP12AMEN_Pos) /*!< 0x00004000 */

+#define RCC_SRDAMR_COMP12AMEN                  RCC_SRDAMR_COMP12AMEN_Msk

+#define RCC_SRDAMR_VREFAMEN_Pos                (15U)

+#define RCC_SRDAMR_VREFAMEN_Msk                (0x1UL << RCC_SRDAMR_VREFAMEN_Pos) /*!< 0x00008000 */

+#define RCC_SRDAMR_VREFAMEN                     RCC_SRDAMR_VREFAMEN_Msk

+#define RCC_SRDAMR_RTCAMEN_Pos                 (16U)

+#define RCC_SRDAMR_RTCAMEN_Msk                 (0x1UL << RCC_SRDAMR_RTCAMEN_Pos) /*!< 0x00010000 */

+#define RCC_SRDAMR_RTCAMEN                     RCC_SRDAMR_RTCAMEN_Msk

+#define RCC_SRDAMR_DTSAMEN_Pos                 (26U)

+#define RCC_SRDAMR_DTSAMEN_Msk                 (0x1UL << RCC_SRDAMR_DTSAMEN_Pos) /*!< 0x04000000 */

+#define RCC_SRDAMR_DTSAMEN                     RCC_SRDAMR_DTSAMEN_Msk

+#define RCC_SRDAMR_DFSDM2AMEN_Pos              (27U)

+#define RCC_SRDAMR_DFSDM2AMEN_Msk              (0x1UL << RCC_SRDAMR_DFSDM2AMEN_Pos) /*!< 0x20000000 */

+#define RCC_SRDAMR_DFSDM2AMEN                   RCC_SRDAMR_DFSDM2AMEN_Msk

+#define RCC_SRDAMR_BKPRAMAMEN_Pos              (28U)

+#define RCC_SRDAMR_BKPRAMAMEN_Msk              (0x1UL << RCC_SRDAMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */

+#define RCC_SRDAMR_BKPRAMAMEN                  RCC_SRDAMR_BKPRAMAMEN_Msk

+#define RCC_SRDAMR_SRDSRAMAMEN_Pos             (29U)

+#define RCC_SRDAMR_SRDSRAMAMEN_Msk             (0x1UL << RCC_SRDAMR_SRDSRAMAMEN_Pos) /*!< 0x20000000 */

+#define RCC_SRDAMR_SRDSRAMAMEN                  RCC_SRDAMR_SRDSRAMAMEN_Msk

+/********************  Bit definition for RCC_CKGAENR register  ********************/

+#define RCC_CKGAENR_AXICKG_Pos                 (0U)

+#define RCC_CKGAENR_AXICKG_Msk                 (0x1UL << RCC_CKGAENR_AXICKG_Pos) /*!< 0x00000001 */

+#define RCC_CKGAENR_AXICKG                      RCC_CKGAENR_AXICKG_Msk

+#define RCC_CKGAENR_AHBCKG_Pos                 (1U)

+#define RCC_CKGAENR_AHBCKG_Msk                 (0x1UL << RCC_CKGAENR_AHBCKG_Pos) /*!< 0x00000002 */

+#define RCC_CKGAENR_AHBCKG                     RCC_CKGAENR_AHBCKG_Msk

+#define RCC_CKGAENR_CPUCKG_Pos                 (2U)

+#define RCC_CKGAENR_CPUCKG_Msk                 (0x1UL << RCC_CKGAENR_CPUCKG_Pos) /*!< 0x00000004 */

+#define RCC_CKGAENR_CPUCKG                     RCC_CKGAENR_CPUCKG_Msk

+#define RCC_CKGAENR_SDMMCCKG_Pos               (3U)

+#define RCC_CKGAENR_SDMMCCKG_Msk               (0x1UL << RCC_CKGAENR_SDMMCCKG_Pos) /*!< 0x00000008 */

+#define RCC_CKGAENR_SDMMCCKG                    RCC_CKGAENR_SDMMCCKG_Msk

+#define RCC_CKGAENR_MDMACKG_Pos                (4U)

+#define RCC_CKGAENR_MDMACKG_Msk                (0x1UL << RCC_CKGAENR_MDMACKG_Pos) /*!< 0x00000010 */

+#define RCC_CKGAENR_MDMACKG                    RCC_CKGAENR_MDMACKG_Msk

+#define RCC_CKGAENR_DMA2DCKG_Pos               (5U)

+#define RCC_CKGAENR_DMA2DCKG_Msk               (0x1UL << RCC_CKGAENR_DMA2DCKG_Pos) /*!< 0x00000020 */

+#define RCC_CKGAENR_DMA2DCKG                    RCC_CKGAENR_DMA2DCKG_Msk

+#define RCC_CKGAENR_LTDCCKG_Pos                (6U)

+#define RCC_CKGAENR_LTDCCKG_Msk                (0x1UL << RCC_CKGAENR_LTDCCKG_Pos) /*!< 0x00000040 */

+#define RCC_CKGAENR_LTDCCKG                    RCC_CKGAENR_LTDCCKG_Msk

+#define RCC_CKGAENR_GFXMMUMCKG_Pos             (7U)

+#define RCC_CKGAENR_GFXMMUMCKG_Msk             (0x1UL << RCC_CKGAENR_GFXMMUMCKG_Pos) /*!< 0x00000080 */

+#define RCC_CKGAENR_GFXMMUMCKG                 RCC_CKGAENR_GFXMMUMCKG_Msk

+#define RCC_CKGAENR_AHB12CKG_Pos               (8U)

+#define RCC_CKGAENR_AHB12CKG_Msk               (0x1UL << RCC_CKGAENR_AHB12CKG_Pos) /*!< 0x00000100 */

+#define RCC_CKGAENR_AHB12CKG                   RCC_CKGAENR_AHB12CKG_Msk

+#define RCC_CKGAENR_AHB34CKG_Pos               (9U)

+#define RCC_CKGAENR_AHB34CKG_Msk               (0x1UL << RCC_CKGAENR_AHB34CKG_Pos) /*!< 0x00000200 */

+#define RCC_CKGAENR_AHB34CKG                   RCC_CKGAENR_AHB34CKG_Msk

+#define RCC_CKGAENR_FLIFTCKG_Pos               (10U)

+#define RCC_CKGAENR_FLIFTCKG_Msk               (0x1UL << RCC_CKGAENR_FLIFTCKG_Pos) /*!< 0x00000400 */

+#define RCC_CKGAENR_FLIFTCKG                   RCC_CKGAENR_FLIFTCKG_Msk

+#define RCC_CKGAENR_OCTOSPI2CKG_Pos            (11U)

+#define RCC_CKGAENR_OCTOSPI2CKG_Msk            (0x1UL << RCC_CKGAENR_OCTOSPI2CKG_Pos) /*!< 0x00000800 */

+#define RCC_CKGAENR_OCTOSPI2CKG                RCC_CKGAENR_OCTOSPI2CKG_Msk

+#define RCC_CKGAENR_FMCCKG_Pos                 (12U)

+#define RCC_CKGAENR_FMCCKG_Msk                 (0x1UL << RCC_CKGAENR_FMCCKG_Pos) /*!< 0x00001000 */

+#define RCC_CKGAENR_FMCCKG                     RCC_CKGAENR_FMCCKG_Msk

+#define RCC_CKGAENR_OCTOSPI1CKG_Pos            (13U)

+#define RCC_CKGAENR_OCTOSPI1CKG_Msk            (0x1UL << RCC_CKGAENR_OCTOSPI1CKG_Pos) /*!< 0x00002000 */

+#define RCC_CKGAENR_OCTOSPI1CKG                RCC_CKGAENR_OCTOSPI1CKG_Msk

+#define RCC_CKGAENR_AXIRAM1CKG_Pos             (14U)

+#define RCC_CKGAENR_AXIRAM1CKG_Msk             (0x1UL << RCC_CKGAENR_AXIRAM1CKG_Pos) /*!< 0x00004000 */

+#define RCC_CKGAENR_AXIRAM1CKG                 RCC_CKGAENR_AXIRAM1CKG_Msk

+#define RCC_CKGAENR_AXIRAM2CKG_Pos             (15U)

+#define RCC_CKGAENR_AXIRAM2CKG_Msk             (0x1UL << RCC_CKGAENR_AXIRAM2CKG_Pos) /*!< 0x00008000 */

+#define RCC_CKGAENR_AXIRAM2CKG                 RCC_CKGAENR_AXIRAM2CKG_Msk

+#define RCC_CKGAENR_AXIRAM3CKG_Pos             (16U)

+#define RCC_CKGAENR_AXIRAM3CKG_Msk             (0x1UL << RCC_CKGAENR_AXIRAM3CKG_Pos) /*!< 0x00010000 */

+#define RCC_CKGAENR_AXIRAM3CKG                 RCC_CKGAENR_AXIRAM3CKG_Msk

+#define RCC_CKGAENR_GFXMMUSCKG_Pos             (17U)

+#define RCC_CKGAENR_GFXMMUSCKG_Msk             (0x1UL << RCC_CKGAENR_GFXMMUSCKG_Pos) /*!< 0x00020000 */

+#define RCC_CKGAENR_GFXMMUSCKG                 RCC_CKGAENR_GFXMMUSCKG_Msk

+#define RCC_CKGAENR_ECCRAMCKG_Pos              (29U)

+#define RCC_CKGAENR_ECCRAMCKG_Msk              (0x1UL << RCC_CKGAENR_ECCRAMCKG_Pos) /*!< 0x20000000 */

+#define RCC_CKGAENR_ECCRAMCKG                  RCC_CKGAENR_ECCRAMCKG_Msk

+#define RCC_CKGAENR_EXTICKG_Pos                (30U)

+#define RCC_CKGAENR_EXTICKG_Msk                (0x1UL << RCC_CKGAENR_EXTICKG_Pos) /*!< 0x40000000 */

+#define RCC_CKGAENR_EXTICKG                    RCC_CKGAENR_EXTICKG_Msk

+#define RCC_CKGAENR_JTAGCKG_Pos                (31U)

+#define RCC_CKGAENR_JTAGCKG_Msk                (0x1UL << RCC_CKGAENR_JTAGCKG_Pos) /*!< 0x80000008 */

+#define RCC_CKGAENR_JTAGCKG                    RCC_CKGAENR_JTAGCKG_Msk

+/********************  Bit definition for RCC_AHB3LPENR register  **************/

+#define RCC_AHB3LPENR_MDMALPEN_Pos             (0U)

+#define RCC_AHB3LPENR_MDMALPEN_Msk             (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos)         /*!< 0x00000001 */

+#define RCC_AHB3LPENR_MDMALPEN                 RCC_AHB3LPENR_MDMALPEN_Msk

+#define RCC_AHB3LPENR_DMA2DLPEN_Pos            (4U)

+#define RCC_AHB3LPENR_DMA2DLPEN_Msk            (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos)        /*!< 0x00000010 */

+#define RCC_AHB3LPENR_DMA2DLPEN                RCC_AHB3LPENR_DMA2DLPEN_Msk

+#define RCC_AHB3LPENR_JPGDECLPEN_Pos           (5U)

+#define RCC_AHB3LPENR_JPGDECLPEN_Msk           (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos)       /*!< 0x00000020 */

+#define RCC_AHB3LPENR_JPGDECLPEN               RCC_AHB3LPENR_JPGDECLPEN_Msk

+#define RCC_AHB3LPENR_FLASHLPEN_Pos            (8U)

+#define RCC_AHB3LPENR_FLASHLPEN_Msk            (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos)        /*!< 0x00000100 */

+#define RCC_AHB3LPENR_FLASHLPEN                RCC_AHB3LPENR_FLASHLPEN_Msk

+#define RCC_AHB3LPENR_FMCLPEN_Pos              (12U)

+#define RCC_AHB3LPENR_FMCLPEN_Msk              (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)          /*!< 0x00001000 */

+#define RCC_AHB3LPENR_FMCLPEN                  RCC_AHB3LPENR_FMCLPEN_Msk

+#define RCC_AHB3LPENR_OSPI1LPEN_Pos            (14U)

+#define RCC_AHB3LPENR_OSPI1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_OSPI1LPEN_Pos)        /*!< 0x00004000 */

+#define RCC_AHB3LPENR_OSPI1LPEN                RCC_AHB3LPENR_OSPI1LPEN_Msk

+#define RCC_AHB3LPENR_SDMMC1LPEN_Pos           (16U)

+#define RCC_AHB3LPENR_SDMMC1LPEN_Msk           (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos)       /*!< 0x00010000 */

+#define RCC_AHB3LPENR_SDMMC1LPEN               RCC_AHB3LPENR_SDMMC1LPEN_Msk

+#define RCC_AHB3LPENR_OSPI2LPEN_Pos            (19U)

+#define RCC_AHB3LPENR_OSPI2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_OSPI2LPEN_Pos)        /*!< 0x00080000 */

+#define RCC_AHB3LPENR_OSPI2LPEN                RCC_AHB3LPENR_OSPI2LPEN_Msk

+#define RCC_AHB3LPENR_IOMNGRLPEN_Pos           (21U)

+#define RCC_AHB3LPENR_IOMNGRLPEN_Msk           (0x1UL << RCC_AHB3LPENR_IOMNGRLPEN_Pos)       /*!< 0x00200000 */

+#define RCC_AHB3LPENR_IOMNGRLPEN               RCC_AHB3LPENR_IOMNGRLPEN_Msk

+#define RCC_AHB3LPENR_OTFDEC1LPEN_Pos          (22U)

+#define RCC_AHB3LPENR_OTFDEC1LPEN_Msk          (0x1UL << RCC_AHB3LPENR_OTFDEC1LPEN_Pos)      /*!< 0x00400000 */

+#define RCC_AHB3LPENR_OTFDEC1LPEN              RCC_AHB3LPENR_OTFDEC1LPEN_Msk

+#define RCC_AHB3LPENR_OTFDEC2LPEN_Pos          (23U)

+#define RCC_AHB3LPENR_OTFDEC2LPEN_Msk          (0x1UL << RCC_AHB3LPENR_OTFDEC2LPEN_Pos)      /*!< 0x00800000 */

+#define RCC_AHB3LPENR_OTFDEC2LPEN              RCC_AHB3LPENR_OTFDEC2LPEN_Msk

+#define RCC_AHB3LPENR_GFXMMULPEN_Pos           (24U)

+#define RCC_AHB3LPENR_GFXMMULPEN_Msk           (0x1UL << RCC_AHB3LPENR_GFXMMULPEN_Pos)       /*!< 0x01000000 */

+#define RCC_AHB3LPENR_GFXMMULPEN               RCC_AHB3LPENR_GFXMMULPEN_Msk

+#define RCC_AHB3LPENR_AXISRAM2LPEN_Pos         (26U)

+#define RCC_AHB3LPENR_AXISRAM2LPEN_Msk         (0x1UL << RCC_AHB3LPENR_AXISRAM2LPEN_Pos)     /*!< 0x02000000 */

+#define RCC_AHB3LPENR_AXISRAM2LPEN             RCC_AHB3LPENR_AXISRAM2LPEN_Msk

+#define RCC_AHB3LPENR_AXISRAM3LPEN_Pos         (27U)

+#define RCC_AHB3LPENR_AXISRAM3LPEN_Msk         (0x1UL << RCC_AHB3LPENR_AXISRAM3LPEN_Pos)     /*!< 0x04000000 */

+#define RCC_AHB3LPENR_AXISRAM3LPEN             RCC_AHB3LPENR_AXISRAM3LPEN_Msk

+#define RCC_AHB3LPENR_DTCM1LPEN_Pos            (28U)

+#define RCC_AHB3LPENR_DTCM1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos)        /*!< 0x10000000 */

+#define RCC_AHB3LPENR_DTCM1LPEN                RCC_AHB3LPENR_DTCM1LPEN_Msk

+#define RCC_AHB3LPENR_DTCM2LPEN_Pos            (29U)

+#define RCC_AHB3LPENR_DTCM2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos)        /*!< 0x20000000 */

+#define RCC_AHB3LPENR_DTCM2LPEN                RCC_AHB3LPENR_DTCM2LPEN_Msk

+#define RCC_AHB3LPENR_ITCMLPEN_Pos             (30U)

+#define RCC_AHB3LPENR_ITCMLPEN_Msk             (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos)         /*!< 0x40000000 */

+#define RCC_AHB3LPENR_ITCMLPEN                 RCC_AHB3LPENR_ITCMLPEN_Msk

+#define RCC_AHB3LPENR_AXISRAM1LPEN_Pos         (31U)

+#define RCC_AHB3LPENR_AXISRAM1LPEN_Msk         (0x1UL << RCC_AHB3LPENR_AXISRAM1LPEN_Pos)      /*!< 0x80000000 */

+#define RCC_AHB3LPENR_AXISRAM1LPEN             RCC_AHB3LPENR_AXISRAM1LPEN_Msk

+

+

+/* Legacy define */

+#define RCC_AHB3LPENR_AXISRAMLPEN_Pos          RCC_AHB3LPENR_AXISRAM1LPEN_Pos

+#define RCC_AHB3LPENR_AXISRAMLPEN_Msk          RCC_AHB3LPENR_AXISRAM1LPEN_Msk

+#define RCC_AHB3LPENR_AXISRAMLPEN              RCC_AHB3LPENR_AXISRAM1LPEN

+/********************  Bit definition for RCC_AHB1LPENR register  ***************/

+#define RCC_AHB1LPENR_DMA1LPEN_Pos             (0U)

+#define RCC_AHB1LPENR_DMA1LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB1LPENR_DMA1LPEN                 RCC_AHB1LPENR_DMA1LPEN_Msk

+#define RCC_AHB1LPENR_DMA2LPEN_Pos             (1U)

+#define RCC_AHB1LPENR_DMA2LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */

+#define RCC_AHB1LPENR_DMA2LPEN                 RCC_AHB1LPENR_DMA2LPEN_Msk

+#define RCC_AHB1LPENR_ADC12LPEN_Pos            (5U)

+#define RCC_AHB1LPENR_ADC12LPEN_Msk            (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB1LPENR_ADC12LPEN                RCC_AHB1LPENR_ADC12LPEN_Msk

+#define RCC_AHB1LPENR_CRCLPEN_Pos              (9U)

+#define RCC_AHB1LPENR_CRCLPEN_Msk              (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00008000 */

+#define RCC_AHB1LPENR_CRCLPEN                   RCC_AHB1LPENR_CRCLPEN_Msk

+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos        (25U)

+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */

+#define RCC_AHB1LPENR_USB1OTGHSLPEN            RCC_AHB1LPENR_USB1OTGHSLPEN_Msk

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos    (26U)

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN        RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk

+

+/********************  Bit definition for RCC_AHB2LPENR register  ***************/

+#define RCC_AHB2LPENR_DCMI_PSSILPEN_Pos        (0U)

+#define RCC_AHB2LPENR_DCMI_PSSILPEN_Msk        (0x1UL << RCC_AHB2LPENR_DCMI_PSSILPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB2LPENR_DCMI_PSSILPEN            RCC_AHB2LPENR_DCMI_PSSILPEN_Msk

+#define RCC_AHB2LPENR_CRYPLPEN_Pos             (4U)

+#define RCC_AHB2LPENR_CRYPLPEN_Msk             (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */

+#define RCC_AHB2LPENR_CRYPLPEN                 RCC_AHB2LPENR_CRYPLPEN_Msk

+#define RCC_AHB2LPENR_HASHLPEN_Pos             (5U)

+#define RCC_AHB2LPENR_HASHLPEN_Msk             (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB2LPENR_HASHLPEN                 RCC_AHB2LPENR_HASHLPEN_Msk

+#define RCC_AHB2LPENR_RNGLPEN_Pos              (6U)

+#define RCC_AHB2LPENR_RNGLPEN_Msk              (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */

+#define RCC_AHB2LPENR_RNGLPEN                  RCC_AHB2LPENR_RNGLPEN_Msk

+#define RCC_AHB2LPENR_SDMMC2LPEN_Pos           (9U)

+#define RCC_AHB2LPENR_SDMMC2LPEN_Msk           (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */

+#define RCC_AHB2LPENR_SDMMC2LPEN               RCC_AHB2LPENR_SDMMC2LPEN_Msk

+#define RCC_AHB2LPENR_BDMA1LPEN_Pos            (11U)

+#define RCC_AHB2LPENR_BDMA1LPEN_Msk            (0x1UL << RCC_AHB2LPENR_BDMA1LPEN_Pos)   /*!< 0x00000800 */

+#define RCC_AHB2LPENR_BDMA1LPEN                RCC_AHB2LPENR_BDMA1LPEN_Msk

+#define RCC_AHB2LPENR_AHBSRAM1LPEN_Pos         (29U)

+#define RCC_AHB2LPENR_AHBSRAM1LPEN_Msk         (0x1UL << RCC_AHB2LPENR_AHBSRAM1LPEN_Pos) /*!< 0x20000000 */

+#define RCC_AHB2LPENR_AHBSRAM1LPEN             RCC_AHB2LPENR_AHBSRAM1LPEN_Msk

+#define RCC_AHB2LPENR_AHBSRAM2LPEN_Pos         (30U)

+#define RCC_AHB2LPENR_AHBSRAM2LPEN_Msk         (0x1UL << RCC_AHB2LPENR_AHBSRAM2LPEN_Pos) /*!< 0x40000000 */

+#define RCC_AHB2LPENR_AHBSRAM2LPEN             RCC_AHB2LPENR_AHBSRAM2LPEN_Msk

+

+/* Legacy define */

+#define RCC_AHB2LPENR_DFSDMDMALPEN_Pos         RCC_AHB2LPENR_BDMA1LPEN_Pos

+#define RCC_AHB2LPENR_DFSDMDMALPEN_Msk         RCC_AHB2LPENR_BDMA1LPEN_Msk

+#define RCC_AHB2LPENR_DFSDMDMALPEN             RCC_AHB2LPENR_BDMA1LPEN

+#define RCC_AHB2LPENR_DCMILPEN_Pos             RCC_AHB2LPENR_DCMI_PSSILPEN_Pos

+#define RCC_AHB2LPENR_DCMILPEN_Msk             RCC_AHB2LPENR_DCMI_PSSILPEN_Msk

+#define RCC_AHB2LPENR_DCMILPEN                 RCC_AHB2LPENR_DCMI_PSSILPEN

+

+/********************  Bit definition for RCC_AHB4LPENR register  ******************/

+#define RCC_AHB4LPENR_GPIOALPEN_Pos            (0U)

+#define RCC_AHB4LPENR_GPIOALPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB4LPENR_GPIOALPEN                RCC_AHB4LPENR_GPIOALPEN_Msk

+#define RCC_AHB4LPENR_GPIOBLPEN_Pos            (1U)

+#define RCC_AHB4LPENR_GPIOBLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */

+#define RCC_AHB4LPENR_GPIOBLPEN                RCC_AHB4LPENR_GPIOBLPEN_Msk

+#define RCC_AHB4LPENR_GPIOCLPEN_Pos            (2U)

+#define RCC_AHB4LPENR_GPIOCLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */

+#define RCC_AHB4LPENR_GPIOCLPEN                RCC_AHB4LPENR_GPIOCLPEN_Msk

+#define RCC_AHB4LPENR_GPIODLPEN_Pos            (3U)

+#define RCC_AHB4LPENR_GPIODLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */

+#define RCC_AHB4LPENR_GPIODLPEN                RCC_AHB4LPENR_GPIODLPEN_Msk

+#define RCC_AHB4LPENR_GPIOELPEN_Pos            (4U)

+#define RCC_AHB4LPENR_GPIOELPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */

+#define RCC_AHB4LPENR_GPIOELPEN                RCC_AHB4LPENR_GPIOELPEN_Msk

+#define RCC_AHB4LPENR_GPIOFLPEN_Pos            (5U)

+#define RCC_AHB4LPENR_GPIOFLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB4LPENR_GPIOFLPEN                RCC_AHB4LPENR_GPIOFLPEN_Msk

+#define RCC_AHB4LPENR_GPIOGLPEN_Pos            (6U)

+#define RCC_AHB4LPENR_GPIOGLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */

+#define RCC_AHB4LPENR_GPIOGLPEN                RCC_AHB4LPENR_GPIOGLPEN_Msk

+#define RCC_AHB4LPENR_GPIOHLPEN_Pos            (7U)

+#define RCC_AHB4LPENR_GPIOHLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */

+#define RCC_AHB4LPENR_GPIOHLPEN                RCC_AHB4LPENR_GPIOHLPEN_Msk

+#define RCC_AHB4LPENR_GPIOILPEN_Pos            (8U)

+#define RCC_AHB4LPENR_GPIOILPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */

+#define RCC_AHB4LPENR_GPIOILPEN                RCC_AHB4LPENR_GPIOILPEN_Msk

+#define RCC_AHB4LPENR_GPIOJLPEN_Pos            (9U)

+#define RCC_AHB4LPENR_GPIOJLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */

+#define RCC_AHB4LPENR_GPIOJLPEN                RCC_AHB4LPENR_GPIOJLPEN_Msk

+#define RCC_AHB4LPENR_GPIOKLPEN_Pos            (10U)

+#define RCC_AHB4LPENR_GPIOKLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */

+#define RCC_AHB4LPENR_GPIOKLPEN                RCC_AHB4LPENR_GPIOKLPEN_Msk

+#define RCC_AHB4LPENR_BDMA2LPEN_Pos             (21U)

+#define RCC_AHB4LPENR_BDMA2LPEN_Msk             (0x1UL << RCC_AHB4LPENR_BDMA2LPEN_Pos) /*!< 0x00200000 */

+#define RCC_AHB4LPENR_BDMA2LPEN                 RCC_AHB4LPENR_BDMA2LPEN_Msk

+#define RCC_AHB4LPENR_BKPRAMLPEN_Pos           (28U)

+#define RCC_AHB4LPENR_BKPRAMLPEN_Msk           (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */

+#define RCC_AHB4LPENR_BKPRAMLPEN               RCC_AHB4LPENR_BKPRAMLPEN_Msk

+#define RCC_AHB4LPENR_SRDSRAMLPEN_Pos          (29U)

+#define RCC_AHB4LPENR_SRDSRAMLPEN_Msk          (0x1UL << RCC_AHB4LPENR_SRDSRAMLPEN_Pos) /*!< 0x20000000 */

+#define RCC_AHB4LPENR_SRDSRAMLPEN              RCC_AHB4LPENR_SRDSRAMLPEN_Msk

+

+/********************  Bit definition for RCC_APB3LPENR register  ******************/

+#define RCC_APB3LPENR_LTDCLPEN_Pos             (3U)

+#define RCC_APB3LPENR_LTDCLPEN_Msk             (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB3LPENR_LTDCLPEN                 RCC_APB3LPENR_LTDCLPEN_Msk

+#define RCC_APB3LPENR_WWDGLPEN_Pos             (6U)

+#define RCC_APB3LPENR_WWDGLPEN_Msk             (0x1UL << RCC_APB3LPENR_WWDGLPEN_Pos)  /*!< 0x00000040 */

+#define RCC_APB3LPENR_WWDGLPEN                 RCC_APB3LPENR_WWDGLPEN_Msk

+

+/* Legacy define */

+#define RCC_APB3LPENR_WWDG1LPEN_Pos            RCC_APB3LPENR_WWDGLPEN_Pos

+#define RCC_APB3LPENR_WWDG1LPEN_Msk            RCC_APB3LPENR_WWDGLPEN_Msk

+#define RCC_APB3LPENR_WWDG1LPEN                RCC_APB3LPENR_WWDGLPEN

+/********************  Bit definition for RCC_APB1LLPENR register  ******************/

+

+#define RCC_APB1LLPENR_TIM2LPEN_Pos            (0U)

+#define RCC_APB1LLPENR_TIM2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */

+#define RCC_APB1LLPENR_TIM2LPEN                RCC_APB1LLPENR_TIM2LPEN_Msk

+#define RCC_APB1LLPENR_TIM3LPEN_Pos            (1U)

+#define RCC_APB1LLPENR_TIM3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1LLPENR_TIM3LPEN                RCC_APB1LLPENR_TIM3LPEN_Msk

+#define RCC_APB1LLPENR_TIM4LPEN_Pos            (2U)

+#define RCC_APB1LLPENR_TIM4LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1LLPENR_TIM4LPEN                RCC_APB1LLPENR_TIM4LPEN_Msk

+#define RCC_APB1LLPENR_TIM5LPEN_Pos            (3U)

+#define RCC_APB1LLPENR_TIM5LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB1LLPENR_TIM5LPEN                RCC_APB1LLPENR_TIM5LPEN_Msk

+#define RCC_APB1LLPENR_TIM6LPEN_Pos            (4U)

+#define RCC_APB1LLPENR_TIM6LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1LLPENR_TIM6LPEN                RCC_APB1LLPENR_TIM6LPEN_Msk

+#define RCC_APB1LLPENR_TIM7LPEN_Pos            (5U)

+#define RCC_APB1LLPENR_TIM7LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1LLPENR_TIM7LPEN                RCC_APB1LLPENR_TIM7LPEN_Msk

+#define RCC_APB1LLPENR_TIM12LPEN_Pos           (6U)

+#define RCC_APB1LLPENR_TIM12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */

+#define RCC_APB1LLPENR_TIM12LPEN               RCC_APB1LLPENR_TIM12LPEN_Msk

+#define RCC_APB1LLPENR_TIM13LPEN_Pos           (7U)

+#define RCC_APB1LLPENR_TIM13LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB1LLPENR_TIM13LPEN               RCC_APB1LLPENR_TIM13LPEN_Msk

+#define RCC_APB1LLPENR_TIM14LPEN_Pos           (8U)

+#define RCC_APB1LLPENR_TIM14LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1LLPENR_TIM14LPEN               RCC_APB1LLPENR_TIM14LPEN_Msk

+#define RCC_APB1LLPENR_LPTIM1LPEN_Pos          (9U)

+#define RCC_APB1LLPENR_LPTIM1LPEN_Msk          (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */

+#define RCC_APB1LLPENR_LPTIM1LPEN              RCC_APB1LLPENR_LPTIM1LPEN_Msk

+

+

+#define RCC_APB1LLPENR_SPI2LPEN_Pos            (14U)

+#define RCC_APB1LLPENR_SPI2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */

+#define RCC_APB1LLPENR_SPI2LPEN                RCC_APB1LLPENR_SPI2LPEN_Msk

+#define RCC_APB1LLPENR_SPI3LPEN_Pos            (15U)

+#define RCC_APB1LLPENR_SPI3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */

+#define RCC_APB1LLPENR_SPI3LPEN                RCC_APB1LLPENR_SPI3LPEN_Msk

+#define RCC_APB1LLPENR_SPDIFRXLPEN_Pos         (16U)

+#define RCC_APB1LLPENR_SPDIFRXLPEN_Msk         (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB1LLPENR_SPDIFRXLPEN             RCC_APB1LLPENR_SPDIFRXLPEN_Msk

+#define RCC_APB1LLPENR_USART2LPEN_Pos          (17U)

+#define RCC_APB1LLPENR_USART2LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */

+#define RCC_APB1LLPENR_USART2LPEN              RCC_APB1LLPENR_USART2LPEN_Msk

+#define RCC_APB1LLPENR_USART3LPEN_Pos          (18U)

+#define RCC_APB1LLPENR_USART3LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */

+#define RCC_APB1LLPENR_USART3LPEN              RCC_APB1LLPENR_USART3LPEN_Msk

+#define RCC_APB1LLPENR_UART4LPEN_Pos           (19U)

+#define RCC_APB1LLPENR_UART4LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */

+#define RCC_APB1LLPENR_UART4LPEN               RCC_APB1LLPENR_UART4LPEN_Msk

+#define RCC_APB1LLPENR_UART5LPEN_Pos           (20U)

+#define RCC_APB1LLPENR_UART5LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */

+#define RCC_APB1LLPENR_UART5LPEN               RCC_APB1LLPENR_UART5LPEN_Msk

+#define RCC_APB1LLPENR_I2C1LPEN_Pos            (21U)

+#define RCC_APB1LLPENR_I2C1LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */

+#define RCC_APB1LLPENR_I2C1LPEN                RCC_APB1LLPENR_I2C1LPEN_Msk

+#define RCC_APB1LLPENR_I2C2LPEN_Pos            (22U)

+#define RCC_APB1LLPENR_I2C2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */

+#define RCC_APB1LLPENR_I2C2LPEN                RCC_APB1LLPENR_I2C2LPEN_Msk

+#define RCC_APB1LLPENR_I2C3LPEN_Pos            (23U)

+#define RCC_APB1LLPENR_I2C3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */

+#define RCC_APB1LLPENR_I2C3LPEN                RCC_APB1LLPENR_I2C3LPEN_Msk

+#define RCC_APB1LLPENR_CECLPEN_Pos             (27U)

+#define RCC_APB1LLPENR_CECLPEN_Msk             (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */

+#define RCC_APB1LLPENR_CECLPEN                 RCC_APB1LLPENR_CECLPEN_Msk

+#define RCC_APB1LLPENR_DAC12LPEN_Pos           (29U)

+#define RCC_APB1LLPENR_DAC12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */

+#define RCC_APB1LLPENR_DAC12LPEN               RCC_APB1LLPENR_DAC12LPEN_Msk

+#define RCC_APB1LLPENR_UART7LPEN_Pos           (30U)

+#define RCC_APB1LLPENR_UART7LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */

+#define RCC_APB1LLPENR_UART7LPEN               RCC_APB1LLPENR_UART7LPEN_Msk

+#define RCC_APB1LLPENR_UART8LPEN_Pos           (31U)

+#define RCC_APB1LLPENR_UART8LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */

+#define RCC_APB1LLPENR_UART8LPEN               RCC_APB1LLPENR_UART8LPEN_Msk

+

+/* Legacy define */

+#define RCC_APB1LLPENR_HDMICECEN_Pos           RCC_APB1LLPENR_CECLPEN_Pos

+#define RCC_APB1LLPENR_HDMICECEN_Msk           RCC_APB1LLPENR_CECLPEN_Msk

+#define RCC_APB1LLPENR_HDMICECEN               RCC_APB1LLPENR_CECLPEN

+/********************  Bit definition for RCC_APB1HLPENR register  ******************/

+#define RCC_APB1HLPENR_CRSLPEN_Pos             (1U)

+#define RCC_APB1HLPENR_CRSLPEN_Msk             (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1HLPENR_CRSLPEN                 RCC_APB1HLPENR_CRSLPEN_Msk

+#define RCC_APB1HLPENR_SWPMILPEN_Pos           (2U)

+#define RCC_APB1HLPENR_SWPMILPEN_Msk           (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1HLPENR_SWPMILPEN               RCC_APB1HLPENR_SWPMILPEN_Msk

+#define RCC_APB1HLPENR_OPAMPLPEN_Pos           (4U)

+#define RCC_APB1HLPENR_OPAMPLPEN_Msk           (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1HLPENR_OPAMPLPEN               RCC_APB1HLPENR_OPAMPLPEN_Msk

+#define RCC_APB1HLPENR_MDIOSLPEN_Pos           (5U)

+#define RCC_APB1HLPENR_MDIOSLPEN_Msk           (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1HLPENR_MDIOSLPEN               RCC_APB1HLPENR_MDIOSLPEN_Msk

+#define RCC_APB1HLPENR_FDCANLPEN_Pos           (8U)

+#define RCC_APB1HLPENR_FDCANLPEN_Msk           (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1HLPENR_FDCANLPEN               RCC_APB1HLPENR_FDCANLPEN_Msk

+

+/********************  Bit definition for RCC_APB2LPENR register  ******************/

+#define RCC_APB2LPENR_TIM1LPEN_Pos             (0U)

+#define RCC_APB2LPENR_TIM1LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */

+#define RCC_APB2LPENR_TIM1LPEN                 RCC_APB2LPENR_TIM1LPEN_Msk

+#define RCC_APB2LPENR_TIM8LPEN_Pos             (1U)

+#define RCC_APB2LPENR_TIM8LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB2LPENR_TIM8LPEN                 RCC_APB2LPENR_TIM8LPEN_Msk

+#define RCC_APB2LPENR_USART1LPEN_Pos           (4U)

+#define RCC_APB2LPENR_USART1LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB2LPENR_USART1LPEN               RCC_APB2LPENR_USART1LPEN_Msk

+#define RCC_APB2LPENR_USART6LPEN_Pos           (5U)

+#define RCC_APB2LPENR_USART6LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB2LPENR_USART6LPEN               RCC_APB2LPENR_USART6LPEN_Msk

+#define RCC_APB2LPENR_UART9LPEN_Pos            (6U)

+#define RCC_APB2LPENR_UART9LPEN_Msk            (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos) /*!< 0x00000040 */

+#define RCC_APB2LPENR_UART9LPEN                 RCC_APB2LPENR_UART9LPEN_Msk

+#define RCC_APB2LPENR_USART10LPEN_Pos          (7U)

+#define RCC_APB2LPENR_USART10LPEN_Msk          (0x1UL << RCC_APB2LPENR_USART10LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB2LPENR_USART10LPEN               RCC_APB2LPENR_USART10LPEN_Msk

+#define RCC_APB2LPENR_SPI1LPEN_Pos             (12U)

+#define RCC_APB2LPENR_SPI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */

+#define RCC_APB2LPENR_SPI1LPEN                 RCC_APB2LPENR_SPI1LPEN_Msk

+#define RCC_APB2LPENR_SPI4LPEN_Pos             (13U)

+#define RCC_APB2LPENR_SPI4LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */

+#define RCC_APB2LPENR_SPI4LPEN                 RCC_APB2LPENR_SPI4LPEN_Msk

+#define RCC_APB2LPENR_TIM15LPEN_Pos            (16U)

+#define RCC_APB2LPENR_TIM15LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB2LPENR_TIM15LPEN                RCC_APB2LPENR_TIM15LPEN_Msk

+#define RCC_APB2LPENR_TIM16LPEN_Pos            (17U)

+#define RCC_APB2LPENR_TIM16LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */

+#define RCC_APB2LPENR_TIM16LPEN                RCC_APB2LPENR_TIM16LPEN_Msk

+#define RCC_APB2LPENR_TIM17LPEN_Pos            (18U)

+#define RCC_APB2LPENR_TIM17LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */

+#define RCC_APB2LPENR_TIM17LPEN                RCC_APB2LPENR_TIM17LPEN_Msk

+#define RCC_APB2LPENR_SPI5LPEN_Pos             (20U)

+#define RCC_APB2LPENR_SPI5LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */

+#define RCC_APB2LPENR_SPI5LPEN                 RCC_APB2LPENR_SPI5LPEN_Msk

+#define RCC_APB2LPENR_SAI1LPEN_Pos             (22U)

+#define RCC_APB2LPENR_SAI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */

+#define RCC_APB2LPENR_SAI1LPEN                 RCC_APB2LPENR_SAI1LPEN_Msk

+#define RCC_APB2LPENR_SAI2LPEN_Pos             (23U)

+#define RCC_APB2LPENR_SAI2LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */

+#define RCC_APB2LPENR_SAI2LPEN                 RCC_APB2LPENR_SAI2LPEN_Msk

+#define RCC_APB2LPENR_DFSDM1LPEN_Pos           (30U)

+#define RCC_APB2LPENR_DFSDM1LPEN_Msk           (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x40000000 */

+#define RCC_APB2LPENR_DFSDM1LPEN               RCC_APB2LPENR_DFSDM1LPEN_Msk

+

+/********************  Bit definition for RCC_APB4LPENR register  ******************/

+#define RCC_APB4LPENR_SYSCFGLPEN_Pos           (1U)

+#define RCC_APB4LPENR_SYSCFGLPEN_Msk           (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB4LPENR_SYSCFGLPEN               RCC_APB4LPENR_SYSCFGLPEN_Msk

+#define RCC_APB4LPENR_LPUART1LPEN_Pos          (3U)

+#define RCC_APB4LPENR_LPUART1LPEN_Msk          (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB4LPENR_LPUART1LPEN              RCC_APB4LPENR_LPUART1LPEN_Msk

+#define RCC_APB4LPENR_SPI6LPEN_Pos             (5U)

+#define RCC_APB4LPENR_SPI6LPEN_Msk             (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB4LPENR_SPI6LPEN                 RCC_APB4LPENR_SPI6LPEN_Msk

+#define RCC_APB4LPENR_I2C4LPEN_Pos             (7U)

+#define RCC_APB4LPENR_I2C4LPEN_Msk             (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB4LPENR_I2C4LPEN                 RCC_APB4LPENR_I2C4LPEN_Msk

+#define RCC_APB4LPENR_LPTIM2LPEN_Pos           (9U)

+#define RCC_APB4LPENR_LPTIM2LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */

+#define RCC_APB4LPENR_LPTIM2LPEN               RCC_APB4LPENR_LPTIM2LPEN_Msk

+#define RCC_APB4LPENR_LPTIM3LPEN_Pos           (10U)

+#define RCC_APB4LPENR_LPTIM3LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */

+#define RCC_APB4LPENR_LPTIM3LPEN               RCC_APB4LPENR_LPTIM3LPEN_Msk

+#define RCC_APB4LPENR_DAC2LPEN_Pos             (13U)

+#define RCC_APB4LPENR_DAC2LPEN_Msk             (0x1UL << RCC_APB4LPENR_DAC2LPEN_Pos) /*!< 0x00002000 */

+#define RCC_APB4LPENR_DAC2LPEN                 RCC_APB4LPENR_DAC2LPEN_Msk

+#define RCC_APB4LPENR_COMP12LPEN_Pos           (14U)

+#define RCC_APB4LPENR_COMP12LPEN_Msk           (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */

+#define RCC_APB4LPENR_COMP12LPEN               RCC_APB4LPENR_COMP12LPEN_Msk

+#define RCC_APB4LPENR_VREFLPEN_Pos             (15U)

+#define RCC_APB4LPENR_VREFLPEN_Msk             (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */

+#define RCC_APB4LPENR_VREFLPEN                 RCC_APB4LPENR_VREFLPEN_Msk

+#define RCC_APB4LPENR_RTCAPBLPEN_Pos           (16U)

+#define RCC_APB4LPENR_RTCAPBLPEN_Msk           (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB4LPENR_RTCAPBLPEN               RCC_APB4LPENR_RTCAPBLPEN_Msk

+

+#define RCC_APB4LPENR_DTSLPEN_Pos              (26U)

+#define RCC_APB4LPENR_DTSLPEN_Msk              (0x1UL << RCC_APB4LPENR_DTSLPEN_Pos) /*!< 0x04000000 */

+#define RCC_APB4LPENR_DTSLPEN                  RCC_APB4LPENR_DTSLPEN_Msk

+#define RCC_APB4LPENR_DFSDM2LPEN_Pos           (27U)

+#define RCC_APB4LPENR_DFSDM2LPEN_Msk           (0x1UL << RCC_APB4LPENR_DFSDM2LPEN_Pos) /*!< 0x08000000 */

+#define RCC_APB4LPENR_DFSDM2LPEN                RCC_APB4LPENR_DFSDM2LPEN_Msk

+

+/********************  Bit definition for RCC_RSR register  *******************/

+#define RCC_RSR_RMVF_Pos                       (16U)

+#define RCC_RSR_RMVF_Msk                       (0x1UL << RCC_RSR_RMVF_Pos)     /*!< 0x00010000 */

+#define RCC_RSR_RMVF                           RCC_RSR_RMVF_Msk

+#define RCC_RSR_CDRSTF_Pos                     (19U)

+#define RCC_RSR_CDRSTF_Msk                     (0x1UL << RCC_RSR_CDRSTF_Pos)   /*!< 0x00080000 */

+#define RCC_RSR_CDRSTF                         RCC_RSR_CDRSTF_Msk

+#define RCC_RSR_BORRSTF_Pos                    (21U)

+#define RCC_RSR_BORRSTF_Msk                    (0x1UL << RCC_RSR_BORRSTF_Pos)  /*!< 0x00200000 */

+#define RCC_RSR_BORRSTF                        RCC_RSR_BORRSTF_Msk

+#define RCC_RSR_PINRSTF_Pos                    (22U)

+#define RCC_RSR_PINRSTF_Msk                    (0x1UL << RCC_RSR_PINRSTF_Pos)  /*!< 0x00400000 */

+#define RCC_RSR_PINRSTF                        RCC_RSR_PINRSTF_Msk

+#define RCC_RSR_PORRSTF_Pos                    (23U)

+#define RCC_RSR_PORRSTF_Msk                    (0x1UL << RCC_RSR_PORRSTF_Pos)  /*!< 0x00800000 */

+#define RCC_RSR_PORRSTF                        RCC_RSR_PORRSTF_Msk

+#define RCC_RSR_SFTRSTF_Pos                    (24U)

+#define RCC_RSR_SFTRSTF_Msk                    (0x1UL << RCC_RSR_SFTRSTF_Pos)  /*!< 0x01000000 */

+#define RCC_RSR_SFTRSTF                        RCC_RSR_SFTRSTF_Msk

+#define RCC_RSR_IWDGRSTF_Pos                   (26U)

+#define RCC_RSR_IWDGRSTF_Msk                   (0x1UL << RCC_RSR_IWDGRSTF_Pos) /*!< 0x04000000 */

+#define RCC_RSR_IWDGRSTF                       RCC_RSR_IWDGRSTF_Msk

+#define RCC_RSR_WWDGRSTF_Pos                   (28U)

+#define RCC_RSR_WWDGRSTF_Msk                   (0x1UL << RCC_RSR_WWDGRSTF_Pos) /*!< 0x10000000 */

+#define RCC_RSR_WWDGRSTF                       RCC_RSR_WWDGRSTF_Msk

+

+#define RCC_RSR_LPWRRSTF_Pos                   (30U)

+#define RCC_RSR_LPWRRSTF_Msk                   (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */

+#define RCC_RSR_LPWRRSTF                       RCC_RSR_LPWRRSTF_Msk

+

+

+/* Legacy define */

+#define RCC_RSR_IWDG1RSTF_Pos                  RCC_RSR_IWDGRSTF_Pos

+#define RCC_RSR_IWDG1RSTF_Msk                  RCC_RSR_IWDGRSTF_Msk

+#define RCC_RSR_IWDG1RSTF                      RCC_RSR_IWDGRSTF

+#define RCC_RSR_WWDG1RSTF_Pos                  RCC_RSR_WWDGRSTF_Pos

+#define RCC_RSR_WWDG1RSTF_Msk                  RCC_RSR_WWDGRSTF_Msk

+#define RCC_RSR_WWDG1RSTF                      RCC_RSR_WWDGRSTF

+/******************************************************************************/

+/*                                                                            */

+/*                                    RNG                                     */

+/*                                                                            */

+/******************************************************************************/

+/***************************    RNG VER  **************************************/

+#define RNG_VER_3_1

+/********************  Bits definition for RNG_CR register  *******************/

+#define RNG_CR_RNGEN_Pos    (2U)

+#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */

+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk

+#define RNG_CR_IE_Pos       (3U)

+#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */

+#define RNG_CR_IE           RNG_CR_IE_Msk

+#define RNG_CR_CED_Pos      (5U)

+#define RNG_CR_CED_Msk      (0x1UL << RNG_CR_CED_Pos)                          /*!< 0x00000020 */

+#define RNG_CR_CED          RNG_CR_CED_Msk

+#define RNG_CR_RNG_CONFIG3_Pos      (8U)

+#define RNG_CR_RNG_CONFIG3_Msk      (0xFUL << RNG_CR_RNG_CONFIG3_Pos)          /*!< 0x00000F00 */

+#define RNG_CR_RNG_CONFIG3          RNG_CR_RNG_CONFIG3_Msk

+#define RNG_CR_NISTC_Pos            (12U)

+#define RNG_CR_NISTC_Msk            (0x1UL << RNG_CR_NISTC_Pos)                /*!< 0x00001000 */

+#define RNG_CR_NISTC                RNG_CR_NISTC_Msk

+#define RNG_CR_RNG_CONFIG2_Pos      (13U)

+#define RNG_CR_RNG_CONFIG2_Msk      (0x7UL << RNG_CR_RNG_CONFIG2_Pos)          /*!< 0x0000E000 */

+#define RNG_CR_RNG_CONFIG2          RNG_CR_RNG_CONFIG2_Msk

+#define RNG_CR_CLKDIV_Pos           (16U)

+#define RNG_CR_CLKDIV_Msk           (0xFUL << RNG_CR_CLKDIV_Pos)               /*!< 0x000F0000 */

+#define RNG_CR_CLKDIV               RNG_CR_CLKDIV_Msk

+#define RNG_CR_CLKDIV_0             (0x1U << RNG_CR_CLKDIV_Pos)                /*!< 0x00010000 */

+#define RNG_CR_CLKDIV_1             (0x2U << RNG_CR_CLKDIV_Pos)                /*!< 0x00020000 */

+#define RNG_CR_CLKDIV_2             (0x4U << RNG_CR_CLKDIV_Pos)                /*!< 0x00040000 */

+#define RNG_CR_CLKDIV_3             (0x8U << RNG_CR_CLKDIV_Pos)                /*!< 0x00080000 */

+#define RNG_CR_RNG_CONFIG1_Pos      (20U)

+#define RNG_CR_RNG_CONFIG1_Msk      (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)         /*!< 0x03F00000 */

+#define RNG_CR_RNG_CONFIG1          RNG_CR_RNG_CONFIG1_Msk

+#define RNG_CR_CONDRST_Pos         (30U)

+#define RNG_CR_CONDRST_Msk         (0x1UL << RNG_CR_CONDRST_Pos)                  /*!< 0x40000000 */

+#define RNG_CR_CONDRST             RNG_CR_CONDRST_Msk

+#define RNG_CR_CONFIGLOCK_Pos      (31U)

+#define RNG_CR_CONFIGLOCK_Msk      (0x1UL << RNG_CR_CONFIGLOCK_Pos)            /*!< 0x80000000 */

+#define RNG_CR_CONFIGLOCK          RNG_CR_CONFIGLOCK_Msk

+

+/********************  Bits definition for RNG_SR register  *******************/

+#define RNG_SR_DRDY_Pos     (0U)

+#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */

+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk

+#define RNG_SR_CECS_Pos     (1U)

+#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */

+#define RNG_SR_CECS         RNG_SR_CECS_Msk

+#define RNG_SR_SECS_Pos     (2U)

+#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */

+#define RNG_SR_SECS         RNG_SR_SECS_Msk

+#define RNG_SR_CEIS_Pos     (5U)

+#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */

+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk

+#define RNG_SR_SEIS_Pos     (6U)

+#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */

+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                           Real-Time Clock (RTC)                            */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for RTC_TR register  *******************/

+#define RTC_TR_PM_Pos                  (22U)

+#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */

+#define RTC_TR_PM                      RTC_TR_PM_Msk

+#define RTC_TR_HT_Pos                  (20U)

+#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */

+#define RTC_TR_HT                      RTC_TR_HT_Msk

+#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */

+#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */

+#define RTC_TR_HU_Pos                  (16U)

+#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */

+#define RTC_TR_HU                      RTC_TR_HU_Msk

+#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */

+#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */

+#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */

+#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */

+#define RTC_TR_MNT_Pos                 (12U)

+#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */

+#define RTC_TR_MNT                     RTC_TR_MNT_Msk

+#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */

+#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */

+#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */

+#define RTC_TR_MNU_Pos                 (8U)

+#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */

+#define RTC_TR_MNU                     RTC_TR_MNU_Msk

+#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */

+#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */

+#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */

+#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */

+#define RTC_TR_ST_Pos                  (4U)

+#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */

+#define RTC_TR_ST                      RTC_TR_ST_Msk

+#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */

+#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */

+#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */

+#define RTC_TR_SU_Pos                  (0U)

+#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */

+#define RTC_TR_SU                      RTC_TR_SU_Msk

+#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */

+#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */

+#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */

+#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_DR register  *******************/

+#define RTC_DR_YT_Pos                  (20U)

+#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */

+#define RTC_DR_YT                      RTC_DR_YT_Msk

+#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */

+#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */

+#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */

+#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */

+#define RTC_DR_YU_Pos                  (16U)

+#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */

+#define RTC_DR_YU                      RTC_DR_YU_Msk

+#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */

+#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */

+#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */

+#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */

+#define RTC_DR_WDU_Pos                 (13U)

+#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */

+#define RTC_DR_WDU                     RTC_DR_WDU_Msk

+#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */

+#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */

+#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */

+#define RTC_DR_MT_Pos                  (12U)

+#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */

+#define RTC_DR_MT                      RTC_DR_MT_Msk

+#define RTC_DR_MU_Pos                  (8U)

+#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */

+#define RTC_DR_MU                      RTC_DR_MU_Msk

+#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */

+#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */

+#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */

+#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */

+#define RTC_DR_DT_Pos                  (4U)

+#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */

+#define RTC_DR_DT                      RTC_DR_DT_Msk

+#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */

+#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */

+#define RTC_DR_DU_Pos                  (0U)

+#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */

+#define RTC_DR_DU                      RTC_DR_DU_Msk

+#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */

+#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */

+#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */

+#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_CR register  *******************/

+#define RTC_CR_OUT2EN_Pos            (31U)

+#define RTC_CR_OUT2EN_Msk            (0x1UL << RTC_CR_OUT2EN_Pos)              /*!< 0x80000000 */

+#define RTC_CR_OUT2EN                RTC_CR_OUT2EN_Msk                         /*!<RTC_OUT2 output enable */

+#define RTC_CR_TAMPALRM_TYPE_Pos     (30U)

+#define RTC_CR_TAMPALRM_TYPE_Msk     (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)       /*!< 0x40000000 */

+#define RTC_CR_TAMPALRM_TYPE         RTC_CR_TAMPALRM_TYPE_Msk                  /*!<TAMPALARM output type  */

+#define RTC_CR_TAMPALRM_PU_Pos       (29U)

+#define RTC_CR_TAMPALRM_PU_Msk       (0x1UL << RTC_CR_TAMPALRM_PU_Pos)         /*!< 0x20000000 */

+#define RTC_CR_TAMPALRM_PU           RTC_CR_TAMPALRM_PU_Msk                    /*!<TAMPALARM output pull-up config */

+#define RTC_CR_TAMPOE_Pos            (26U)

+#define RTC_CR_TAMPOE_Msk            (0x1UL << RTC_CR_TAMPOE_Pos)              /*!< 0x04000000 */

+#define RTC_CR_TAMPOE                RTC_CR_TAMPOE_Msk                         /*!<Tamper detection output enable on TAMPALARM  */

+#define RTC_CR_TAMPTS_Pos            (25U)

+#define RTC_CR_TAMPTS_Msk            (0x1UL << RTC_CR_TAMPTS_Pos)              /*!< 0x02000000 */

+#define RTC_CR_TAMPTS                RTC_CR_TAMPTS_Msk                         /*!<Activate timestamp on tamper detection event  */

+#define RTC_CR_ITSE_Pos                (24U)

+#define RTC_CR_ITSE_Msk                (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */

+#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk

+#define RTC_CR_COE_Pos                 (23U)

+#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */

+#define RTC_CR_COE                     RTC_CR_COE_Msk

+#define RTC_CR_OSEL_Pos                (21U)

+#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */

+#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk

+#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */

+#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */

+#define RTC_CR_POL_Pos                 (20U)

+#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */

+#define RTC_CR_POL                     RTC_CR_POL_Msk

+#define RTC_CR_COSEL_Pos               (19U)

+#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */

+#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk

+#define RTC_CR_BKP_Pos                 (18U)

+#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */

+#define RTC_CR_BKP                     RTC_CR_BKP_Msk

+#define RTC_CR_SUB1H_Pos               (17U)

+#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */

+#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk

+#define RTC_CR_ADD1H_Pos               (16U)

+#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */

+#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk

+#define RTC_CR_TSIE_Pos                (15U)

+#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */

+#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk

+#define RTC_CR_WUTIE_Pos               (14U)

+#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */

+#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk

+#define RTC_CR_ALRBIE_Pos              (13U)

+#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */

+#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk

+#define RTC_CR_ALRAIE_Pos              (12U)

+#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */

+#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk

+#define RTC_CR_TSE_Pos                 (11U)

+#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */

+#define RTC_CR_TSE                     RTC_CR_TSE_Msk

+#define RTC_CR_WUTE_Pos                (10U)

+#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */

+#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk

+#define RTC_CR_ALRBE_Pos               (9U)

+#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */

+#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk

+#define RTC_CR_ALRAE_Pos               (8U)

+#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */

+#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk

+#define RTC_CR_FMT_Pos                 (6U)

+#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */

+#define RTC_CR_FMT                     RTC_CR_FMT_Msk

+#define RTC_CR_BYPSHAD_Pos             (5U)

+#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */

+#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk

+#define RTC_CR_REFCKON_Pos             (4U)

+#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */

+#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk

+#define RTC_CR_TSEDGE_Pos              (3U)

+#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */

+#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk

+#define RTC_CR_WUCKSEL_Pos             (0U)

+#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */

+#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk

+#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */

+#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */

+#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */

+

+/********************  Bits definition for RTC_ICSR register  ******************/

+#define RTC_ICSR_RECALPF_Pos         (16U)

+#define RTC_ICSR_RECALPF_Msk         (0x1UL << RTC_ICSR_RECALPF_Pos)           /*!< 0x00010000 */

+#define RTC_ICSR_RECALPF             RTC_ICSR_RECALPF_Msk

+#define RTC_ICSR_INIT_Pos            (7U)

+#define RTC_ICSR_INIT_Msk            (0x1UL << RTC_ICSR_INIT_Pos)              /*!< 0x00000080 */

+#define RTC_ICSR_INIT                RTC_ICSR_INIT_Msk

+#define RTC_ICSR_INITF_Pos           (6U)

+#define RTC_ICSR_INITF_Msk           (0x1UL << RTC_ICSR_INITF_Pos)             /*!< 0x00000040 */

+#define RTC_ICSR_INITF               RTC_ICSR_INITF_Msk

+#define RTC_ICSR_RSF_Pos             (5U)

+#define RTC_ICSR_RSF_Msk             (0x1UL << RTC_ICSR_RSF_Pos)               /*!< 0x00000020 */

+#define RTC_ICSR_RSF                 RTC_ICSR_RSF_Msk

+#define RTC_ICSR_INITS_Pos           (4U)

+#define RTC_ICSR_INITS_Msk           (0x1UL << RTC_ICSR_INITS_Pos)             /*!< 0x00000010 */

+#define RTC_ICSR_INITS               RTC_ICSR_INITS_Msk

+#define RTC_ICSR_SHPF_Pos            (3U)

+#define RTC_ICSR_SHPF_Msk            (0x1UL << RTC_ICSR_SHPF_Pos)              /*!< 0x00000008 */

+#define RTC_ICSR_SHPF                RTC_ICSR_SHPF_Msk

+#define RTC_ICSR_WUTWF_Pos           (2U)

+#define RTC_ICSR_WUTWF_Msk           (0x1UL << RTC_ICSR_WUTWF_Pos)             /*!< 0x00000004 */

+#define RTC_ICSR_WUTWF               RTC_ICSR_WUTWF_Msk

+#define RTC_ICSR_ALRBWF_Pos          (1U)

+#define RTC_ICSR_ALRBWF_Msk          (0x1UL << RTC_ICSR_ALRBWF_Pos)            /*!< 0x00000002 */

+#define RTC_ICSR_ALRBWF              RTC_ICSR_ALRBWF_Msk

+#define RTC_ICSR_ALRAWF_Pos          (0U)

+#define RTC_ICSR_ALRAWF_Msk          (0x1UL << RTC_ICSR_ALRAWF_Pos)            /*!< 0x00000001 */

+#define RTC_ICSR_ALRAWF              RTC_ICSR_ALRAWF_Msk

+

+/********************  Bits definition for RTC_PRER register  *****************/

+#define RTC_PRER_PREDIV_A_Pos          (16U)

+#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */

+#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk

+#define RTC_PRER_PREDIV_S_Pos          (0U)

+#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */

+#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk

+

+/********************  Bits definition for RTC_WUTR register  *****************/

+#define RTC_WUTR_WUT_Pos               (0U)

+#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */

+#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk

+

+/********************  Bits definition for RTC_ALRMAR register  ***************/

+#define RTC_ALRMAR_MSK4_Pos            (31U)

+#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */

+#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk

+#define RTC_ALRMAR_WDSEL_Pos           (30U)

+#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */

+#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk

+#define RTC_ALRMAR_DT_Pos              (28U)

+#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */

+#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk

+#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */

+#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */

+#define RTC_ALRMAR_DU_Pos              (24U)

+#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */

+#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk

+#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */

+#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */

+#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */

+#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */

+#define RTC_ALRMAR_MSK3_Pos            (23U)

+#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */

+#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk

+#define RTC_ALRMAR_PM_Pos              (22U)

+#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */

+#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk

+#define RTC_ALRMAR_HT_Pos              (20U)

+#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */

+#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk

+#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */

+#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */

+#define RTC_ALRMAR_HU_Pos              (16U)

+#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */

+#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk

+#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */

+#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */

+#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */

+#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */

+#define RTC_ALRMAR_MSK2_Pos            (15U)

+#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */

+#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk

+#define RTC_ALRMAR_MNT_Pos             (12U)

+#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */

+#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk

+#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */

+#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */

+#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */

+#define RTC_ALRMAR_MNU_Pos             (8U)

+#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */

+#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk

+#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */

+#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */

+#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */

+#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */

+#define RTC_ALRMAR_MSK1_Pos            (7U)

+#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */

+#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk

+#define RTC_ALRMAR_ST_Pos              (4U)

+#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */

+#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk

+#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */

+#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */

+#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */

+#define RTC_ALRMAR_SU_Pos              (0U)

+#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */

+#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk

+#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */

+#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */

+#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */

+#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_ALRMBR register  ***************/

+#define RTC_ALRMBR_MSK4_Pos            (31U)

+#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */

+#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk

+#define RTC_ALRMBR_WDSEL_Pos           (30U)

+#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */

+#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk

+#define RTC_ALRMBR_DT_Pos              (28U)

+#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */

+#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk

+#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */

+#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */

+#define RTC_ALRMBR_DU_Pos              (24U)

+#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */

+#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk

+#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */

+#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */

+#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */

+#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */

+#define RTC_ALRMBR_MSK3_Pos            (23U)

+#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */

+#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk

+#define RTC_ALRMBR_PM_Pos              (22U)

+#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */

+#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk

+#define RTC_ALRMBR_HT_Pos              (20U)

+#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */

+#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk

+#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */

+#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */

+#define RTC_ALRMBR_HU_Pos              (16U)

+#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */

+#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk

+#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */

+#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */

+#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */

+#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */

+#define RTC_ALRMBR_MSK2_Pos            (15U)

+#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */

+#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk

+#define RTC_ALRMBR_MNT_Pos             (12U)

+#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */

+#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk

+#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */

+#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */

+#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */

+#define RTC_ALRMBR_MNU_Pos             (8U)

+#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */

+#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk

+#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */

+#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */

+#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */

+#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */

+#define RTC_ALRMBR_MSK1_Pos            (7U)

+#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */

+#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk

+#define RTC_ALRMBR_ST_Pos              (4U)

+#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */

+#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk

+#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */

+#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */

+#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */

+#define RTC_ALRMBR_SU_Pos              (0U)

+#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */

+#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk

+#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */

+#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */

+#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */

+#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_WPR register  ******************/

+#define RTC_WPR_KEY_Pos                (0U)

+#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */

+#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk

+

+/********************  Bits definition for RTC_SSR register  ******************/

+#define RTC_SSR_SS_Pos                 (0U)

+#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)            /*!< 0x0000FFFF */

+#define RTC_SSR_SS                     RTC_SSR_SS_Msk

+

+/********************  Bits definition for RTC_SHIFTR register  ***************/

+#define RTC_SHIFTR_SUBFS_Pos           (0U)

+#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */

+#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk

+#define RTC_SHIFTR_ADD1S_Pos           (31U)

+#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */

+#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk

+

+/********************  Bits definition for RTC_TSTR register  *****************/

+#define RTC_TSTR_PM_Pos                (22U)

+#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */

+#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk

+#define RTC_TSTR_HT_Pos                (20U)

+#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */

+#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk

+#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */

+#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */

+#define RTC_TSTR_HU_Pos                (16U)

+#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */

+#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk

+#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */

+#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */

+#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */

+#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */

+#define RTC_TSTR_MNT_Pos               (12U)

+#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */

+#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk

+#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */

+#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */

+#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */

+#define RTC_TSTR_MNU_Pos               (8U)

+#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */

+#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk

+#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */

+#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */

+#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */

+#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */

+#define RTC_TSTR_ST_Pos                (4U)

+#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */

+#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk

+#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */

+#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */

+#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */

+#define RTC_TSTR_SU_Pos                (0U)

+#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */

+#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk

+#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */

+#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */

+#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */

+#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_TSDR register  *****************/

+#define RTC_TSDR_WDU_Pos               (13U)

+#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */

+#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk

+#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */

+#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */

+#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */

+#define RTC_TSDR_MT_Pos                (12U)

+#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */

+#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk

+#define RTC_TSDR_MU_Pos                (8U)

+#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */

+#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk

+#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */

+#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */

+#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */

+#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */

+#define RTC_TSDR_DT_Pos                (4U)

+#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */

+#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk

+#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */

+#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */

+#define RTC_TSDR_DU_Pos                (0U)

+#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */

+#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk

+#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */

+#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */

+#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */

+#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_TSSSR register  ****************/

+#define RTC_TSSSR_SS_Pos               (0U)

+#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)          /*!< 0x0000FFFF */

+#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk

+

+/********************  Bits definition for RTC_CALR register  *****************/

+#define RTC_CALR_CALP_Pos              (15U)

+#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */

+#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk

+#define RTC_CALR_CALW8_Pos             (14U)

+#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */

+#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk

+#define RTC_CALR_CALW16_Pos            (13U)

+#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */

+#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk

+#define RTC_CALR_CALM_Pos              (0U)

+#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */

+#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk

+#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */

+#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */

+#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */

+#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */

+#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */

+#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */

+#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */

+#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */

+#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */

+

+

+/********************  Bits definition for RTC_ALRMASSR register  *************/

+#define RTC_ALRMASSR_MASKSS_Pos        (24U)

+#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x0F000000 */

+#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk

+#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */

+#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */

+#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */

+#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */

+#define RTC_ALRMASSR_SS_Pos            (0U)

+#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */

+#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk

+

+/********************  Bits definition for RTC_ALRMBSSR register  *************/

+#define RTC_ALRMBSSR_MASKSS_Pos        (24U)

+#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x0F000000 */

+#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk

+#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */

+#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */

+#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */

+#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */

+#define RTC_ALRMBSSR_SS_Pos            (0U)

+#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */

+#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk

+

+

+/********************  Bits definition for RTC_SR register  *******************/

+#define RTC_SR_ITSF_Pos              (5U)

+#define RTC_SR_ITSF_Msk              (0x1UL << RTC_SR_ITSF_Pos)                 /*!< 0x00000020 */

+#define RTC_SR_ITSF                  RTC_SR_ITSF_Msk

+#define RTC_SR_TSOVF_Pos             (4U)

+#define RTC_SR_TSOVF_Msk             (0x1UL << RTC_SR_TSOVF_Pos)                /*!< 0x00000010 */

+#define RTC_SR_TSOVF                 RTC_SR_TSOVF_Msk

+#define RTC_SR_TSF_Pos               (3U)

+#define RTC_SR_TSF_Msk               (0x1UL << RTC_SR_TSF_Pos)                  /*!< 0x00000008 */

+#define RTC_SR_TSF                   RTC_SR_TSF_Msk

+#define RTC_SR_WUTF_Pos              (2U)

+#define RTC_SR_WUTF_Msk              (0x1UL << RTC_SR_WUTF_Pos)                 /*!< 0x00000004 */

+#define RTC_SR_WUTF                  RTC_SR_WUTF_Msk

+#define RTC_SR_ALRBF_Pos             (1U)

+#define RTC_SR_ALRBF_Msk             (0x1UL << RTC_SR_ALRBF_Pos)                /*!< 0x00000002 */

+#define RTC_SR_ALRBF                 RTC_SR_ALRBF_Msk

+#define RTC_SR_ALRAF_Pos             (0U)

+#define RTC_SR_ALRAF_Msk             (0x1UL << RTC_SR_ALRAF_Pos)                /*!< 0x00000001 */

+#define RTC_SR_ALRAF                 RTC_SR_ALRAF_Msk

+

+/********************  Bits definition for RTC_MISR register  *****************/

+#define RTC_MISR_ITSMF_Pos           (5U)

+#define RTC_MISR_ITSMF_Msk           (0x1UL << RTC_MISR_ITSMF_Pos)              /*!< 0x00000020 */

+#define RTC_MISR_ITSMF               RTC_MISR_ITSMF_Msk

+#define RTC_MISR_TSOVMF_Pos          (4U)

+#define RTC_MISR_TSOVMF_Msk          (0x1UL << RTC_MISR_TSOVMF_Pos)             /*!< 0x00000010 */

+#define RTC_MISR_TSOVMF              RTC_MISR_TSOVMF_Msk

+#define RTC_MISR_TSMF_Pos            (3U)

+#define RTC_MISR_TSMF_Msk            (0x1UL << RTC_MISR_TSMF_Pos)               /*!< 0x00000008 */

+#define RTC_MISR_TSMF                RTC_MISR_TSMF_Msk

+#define RTC_MISR_WUTMF_Pos           (2U)

+#define RTC_MISR_WUTMF_Msk           (0x1UL << RTC_MISR_WUTMF_Pos)              /*!< 0x00000004 */

+#define RTC_MISR_WUTMF               RTC_MISR_WUTMF_Msk

+#define RTC_MISR_ALRBMF_Pos          (1U)

+#define RTC_MISR_ALRBMF_Msk          (0x1UL << RTC_MISR_ALRBMF_Pos)             /*!< 0x00000002 */

+#define RTC_MISR_ALRBMF              RTC_MISR_ALRBMF_Msk

+#define RTC_MISR_ALRAMF_Pos          (0U)

+#define RTC_MISR_ALRAMF_Msk          (0x1UL << RTC_MISR_ALRAMF_Pos)             /*!< 0x00000001 */

+#define RTC_MISR_ALRAMF              RTC_MISR_ALRAMF_Msk

+

+/********************  Bits definition for RTC_SCR register  ******************/

+#define RTC_SCR_CITSF_Pos            (5U)

+#define RTC_SCR_CITSF_Msk            (0x1UL << RTC_SCR_CITSF_Pos)               /*!< 0x00000020 */

+#define RTC_SCR_CITSF                RTC_SCR_CITSF_Msk

+#define RTC_SCR_CTSOVF_Pos           (4U)

+#define RTC_SCR_CTSOVF_Msk           (0x1UL << RTC_SCR_CTSOVF_Pos)              /*!< 0x00000010 */

+#define RTC_SCR_CTSOVF               RTC_SCR_CTSOVF_Msk

+#define RTC_SCR_CTSF_Pos             (3U)

+#define RTC_SCR_CTSF_Msk             (0x1UL << RTC_SCR_CTSF_Pos)                /*!< 0x00000008 */

+#define RTC_SCR_CTSF                 RTC_SCR_CTSF_Msk

+#define RTC_SCR_CWUTF_Pos            (2U)

+#define RTC_SCR_CWUTF_Msk            (0x1UL << RTC_SCR_CWUTF_Pos)               /*!< 0x00000004 */

+#define RTC_SCR_CWUTF                RTC_SCR_CWUTF_Msk

+#define RTC_SCR_CALRBF_Pos           (1U)

+#define RTC_SCR_CALRBF_Msk           (0x1UL << RTC_SCR_CALRBF_Pos)              /*!< 0x00000002 */

+#define RTC_SCR_CALRBF               RTC_SCR_CALRBF_Msk

+#define RTC_SCR_CALRAF_Pos           (0U)

+#define RTC_SCR_CALRAF_Msk           (0x1UL << RTC_SCR_CALRAF_Pos)              /*!< 0x00000001 */

+#define RTC_SCR_CALRAF               RTC_SCR_CALRAF_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                     Tamper and backup register (TAMP)                      */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for TAMP_CR1 register  *****************/

+#define TAMP_CR1_TAMP1E_Pos          (0U)

+#define TAMP_CR1_TAMP1E_Msk          (0x1UL << TAMP_CR1_TAMP1E_Pos)            /*!< 0x00000001 */

+#define TAMP_CR1_TAMP1E              TAMP_CR1_TAMP1E_Msk

+#define TAMP_CR1_TAMP2E_Pos          (1U)

+#define TAMP_CR1_TAMP2E_Msk          (0x1UL << TAMP_CR1_TAMP2E_Pos)            /*!< 0x00000002 */

+#define TAMP_CR1_TAMP2E              TAMP_CR1_TAMP2E_Msk

+#define TAMP_CR1_TAMP3E_Pos          (2U)

+#define TAMP_CR1_TAMP3E_Msk          (0x1UL << TAMP_CR1_TAMP3E_Pos)            /*!< 0x00000004 */

+#define TAMP_CR1_TAMP3E              TAMP_CR1_TAMP3E_Msk

+#define TAMP_CR1_ITAMP1E_Pos         (16U)

+#define TAMP_CR1_ITAMP1E_Msk         (0x1UL << TAMP_CR1_ITAMP1E_Pos)           /*!< 0x00010000 */

+#define TAMP_CR1_ITAMP1E             TAMP_CR1_ITAMP1E_Msk

+#define TAMP_CR1_ITAMP2E_Pos         (17U)

+#define TAMP_CR1_ITAMP2E_Msk         (0x1UL << TAMP_CR1_ITAMP2E_Pos)           /*!< 0x00020000 */

+#define TAMP_CR1_ITAMP2E             TAMP_CR1_ITAMP2E_Msk

+#define TAMP_CR1_ITAMP3E_Pos         (18U)

+#define TAMP_CR1_ITAMP3E_Msk         (0x1UL << TAMP_CR1_ITAMP3E_Pos)           /*!< 0x00040000 */

+#define TAMP_CR1_ITAMP3E             TAMP_CR1_ITAMP3E_Msk

+#define TAMP_CR1_ITAMP4E_Pos         (19U)

+#define TAMP_CR1_ITAMP4E_Msk         (0x1UL << TAMP_CR1_ITAMP4E_Pos)           /*!< 0x00080000 */

+#define TAMP_CR1_ITAMP4E             TAMP_CR1_ITAMP4E_Msk

+#define TAMP_CR1_ITAMP5E_Pos         (20U)

+#define TAMP_CR1_ITAMP5E_Msk         (0x1UL << TAMP_CR1_ITAMP5E_Pos)           /*!< 0x00100000 */

+#define TAMP_CR1_ITAMP5E             TAMP_CR1_ITAMP5E_Msk

+#define TAMP_CR1_ITAMP6E_Pos         (21U)

+#define TAMP_CR1_ITAMP6E_Msk         (0x1UL << TAMP_CR1_ITAMP6E_Pos)           /*!< 0x00200000 */

+#define TAMP_CR1_ITAMP6E             TAMP_CR1_ITAMP6E_Msk

+#define TAMP_CR1_ITAMP8E_Pos         (23U)

+#define TAMP_CR1_ITAMP8E_Msk         (0x1UL << TAMP_CR1_ITAMP8E_Pos)           /*!< 0x00800000 */

+#define TAMP_CR1_ITAMP8E             TAMP_CR1_ITAMP8E_Msk

+

+/********************  Bits definition for TAMP_CR2 register  *****************/

+#define TAMP_CR2_TAMP1NOERASE_Pos    (0U)

+#define TAMP_CR2_TAMP1NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)      /*!< 0x00000001 */

+#define TAMP_CR2_TAMP1NOERASE        TAMP_CR2_TAMP1NOERASE_Msk

+#define TAMP_CR2_TAMP2NOERASE_Pos    (1U)

+#define TAMP_CR2_TAMP2NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)      /*!< 0x00000002 */

+#define TAMP_CR2_TAMP2NOERASE        TAMP_CR2_TAMP2NOERASE_Msk

+#define TAMP_CR2_TAMP3NOERASE_Pos    (2U)

+#define TAMP_CR2_TAMP3NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos)      /*!< 0x00000004 */

+#define TAMP_CR2_TAMP3NOERASE        TAMP_CR2_TAMP3NOERASE_Msk

+#define TAMP_CR2_TAMP1MSK_Pos        (16U)

+#define TAMP_CR2_TAMP1MSK_Msk        (0x1UL << TAMP_CR2_TAMP1MSK_Pos)          /*!< 0x00010000 */

+#define TAMP_CR2_TAMP1MSK            TAMP_CR2_TAMP1MSK_Msk

+#define TAMP_CR2_TAMP2MSK_Pos        (17U)

+#define TAMP_CR2_TAMP2MSK_Msk        (0x1UL << TAMP_CR2_TAMP2MSK_Pos)          /*!< 0x00020000 */

+#define TAMP_CR2_TAMP2MSK            TAMP_CR2_TAMP2MSK_Msk

+#define TAMP_CR2_TAMP3MSK_Pos        (18U)

+#define TAMP_CR2_TAMP3MSK_Msk        (0x1UL << TAMP_CR2_TAMP3MSK_Pos)          /*!< 0x00040000 */

+#define TAMP_CR2_TAMP3MSK            TAMP_CR2_TAMP3MSK_Msk

+#define TAMP_CR2_TAMP1TRG_Pos        (24U)

+#define TAMP_CR2_TAMP1TRG_Msk        (0x1UL << TAMP_CR2_TAMP1TRG_Pos)          /*!< 0x01000000 */

+#define TAMP_CR2_TAMP1TRG            TAMP_CR2_TAMP1TRG_Msk

+#define TAMP_CR2_TAMP2TRG_Pos        (25U)

+#define TAMP_CR2_TAMP2TRG_Msk        (0x1UL << TAMP_CR2_TAMP2TRG_Pos)          /*!< 0x02000000 */

+#define TAMP_CR2_TAMP2TRG            TAMP_CR2_TAMP2TRG_Msk

+#define TAMP_CR2_TAMP3TRG_Pos        (26U)

+#define TAMP_CR2_TAMP3TRG_Msk        (0x1UL << TAMP_CR2_TAMP3TRG_Pos)          /*!< 0x04000000 */

+#define TAMP_CR2_TAMP3TRG            TAMP_CR2_TAMP3TRG_Msk

+

+/********************  Bits definition for TAMP_FLTCR register  ***************/

+#define TAMP_FLTCR_TAMPFREQ_Pos      (0U)

+#define TAMP_FLTCR_TAMPFREQ_Msk      (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000007 */

+#define TAMP_FLTCR_TAMPFREQ          TAMP_FLTCR_TAMPFREQ_Msk

+#define TAMP_FLTCR_TAMPFREQ_0        (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000001 */

+#define TAMP_FLTCR_TAMPFREQ_1        (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000002 */

+#define TAMP_FLTCR_TAMPFREQ_2        (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000004 */

+#define TAMP_FLTCR_TAMPFLT_Pos       (3U)

+#define TAMP_FLTCR_TAMPFLT_Msk       (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000018 */

+#define TAMP_FLTCR_TAMPFLT           TAMP_FLTCR_TAMPFLT_Msk

+#define TAMP_FLTCR_TAMPFLT_0         (0x1UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000008 */

+#define TAMP_FLTCR_TAMPFLT_1         (0x2UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000010 */

+#define TAMP_FLTCR_TAMPPRCH_Pos      (5U)

+#define TAMP_FLTCR_TAMPPRCH_Msk      (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000060 */

+#define TAMP_FLTCR_TAMPPRCH          TAMP_FLTCR_TAMPPRCH_Msk

+#define TAMP_FLTCR_TAMPPRCH_0        (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000020 */

+#define TAMP_FLTCR_TAMPPRCH_1        (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000040 */

+#define TAMP_FLTCR_TAMPPUDIS_Pos     (7U)

+#define TAMP_FLTCR_TAMPPUDIS_Msk     (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)        /*!< 0x00000080 */

+#define TAMP_FLTCR_TAMPPUDIS         TAMP_FLTCR_TAMPPUDIS_Msk

+

+/*******************  Bits definition for TAMP_ATCR1 register  ****************/

+#define TAMP_ATCR1_TAMP1AM_Pos       (0U)

+#define TAMP_ATCR1_TAMP1AM_Msk       (0x1UL << TAMP_ATCR1_TAMP1AM_Pos)         /*!< 0x00000001 */

+#define TAMP_ATCR1_TAMP1AM           TAMP_ATCR1_TAMP1AM_Msk

+#define TAMP_ATCR1_TAMP2AM_Pos       (1U)

+#define TAMP_ATCR1_TAMP2AM_Msk       (0x1UL << TAMP_ATCR1_TAMP2AM_Pos)         /*!< 0x00000002 */

+#define TAMP_ATCR1_TAMP2AM           TAMP_ATCR1_TAMP2AM_Msk

+#define TAMP_ATCR1_TAMP3AM_Pos       (2U)

+#define TAMP_ATCR1_TAMP3AM_Msk       (0x1UL << TAMP_ATCR1_TAMP3AM_Pos)         /*!< 0x00000004 */

+#define TAMP_ATCR1_TAMP3AM           TAMP_ATCR1_TAMP3AM_Msk

+#define TAMP_ATCR1_ATOSEL1_Pos       (8U)

+#define TAMP_ATCR1_ATOSEL1_Msk       (0x3UL << TAMP_ATCR1_ATOSEL1_Pos)          /*!< 0x00000300 */

+#define TAMP_ATCR1_ATOSEL1            TAMP_ATCR1_ATOSEL1_Msk

+#define TAMP_ATCR1_ATOSEL1_0         (0x1UL << TAMP_ATCR1_ATOSEL1_Pos)         /*!< 0x00000100 */

+#define TAMP_ATCR1_ATOSEL1_1         (0x2UL << TAMP_ATCR1_ATOSEL1_Pos)         /*!< 0x00000200 */

+#define TAMP_ATCR1_ATOSEL2_Pos       (10U)

+#define TAMP_ATCR1_ATOSEL2_Msk       (0x3UL << TAMP_ATCR1_ATOSEL2_Pos)          /*!< 0x00000C00 */

+#define TAMP_ATCR1_ATOSEL2            TAMP_ATCR1_ATOSEL2_Msk

+#define TAMP_ATCR1_ATOSEL2_0         (0x1UL << TAMP_ATCR1_ATOSEL2_Pos)         /*!< 0x00000400 */

+#define TAMP_ATCR1_ATOSEL2_1         (0x2UL << TAMP_ATCR1_ATOSEL2_Pos)         /*!< 0x00000800 */

+#define TAMP_ATCR1_ATOSEL3_Pos       (12U)

+#define TAMP_ATCR1_ATOSEL3_Msk       (0x3UL << TAMP_ATCR1_ATOSEL3_Pos)          /*!< 0x00003000 */

+#define TAMP_ATCR1_ATOSEL3            TAMP_ATCR1_ATOSEL3_Msk

+#define TAMP_ATCR1_ATOSEL3_0         (0x1UL << TAMP_ATCR1_ATOSEL3_Pos)         /*!< 0x00001000 */

+#define TAMP_ATCR1_ATOSEL3_1         (0x2UL << TAMP_ATCR1_ATOSEL3_Pos)         /*!< 0x00002000 */

+#define TAMP_ATCR1_ATOSEL4_Pos       (14U)

+#define TAMP_ATCR1_ATOSEL4_Msk       (0x3UL << TAMP_ATCR1_ATOSEL4_Pos)          /*!< 0x0000C000 */

+#define TAMP_ATCR1_ATOSEL4            TAMP_ATCR1_ATOSEL4_Msk

+#define TAMP_ATCR1_ATOSEL4_0         (0x1UL << TAMP_ATCR1_ATOSEL4_Pos)         /*!< 0x00004000 */

+#define TAMP_ATCR1_ATOSEL4_1         (0x2UL << TAMP_ATCR1_ATOSEL4_Pos)         /*!< 0x00008000 */

+#define TAMP_ATCR1_ATCKSEL_Pos       (16U)

+#define TAMP_ATCR1_ATCKSEL_Msk       (0x7UL << TAMP_ATCR1_ATCKSEL_Pos)          /*!< 0x00070000 */

+#define TAMP_ATCR1_ATCKSEL            TAMP_ATCR1_ATCKSEL_Msk

+#define TAMP_ATCR1_ATCKSEL_0         (0x1UL << TAMP_ATCR1_ATCKSEL_Pos)         /*!< 0x00010000 */

+#define TAMP_ATCR1_ATCKSEL_1         (0x2UL << TAMP_ATCR1_ATCKSEL_Pos)         /*!< 0x00020000 */

+#define TAMP_ATCR1_ATCKSEL_2         (0x4UL << TAMP_ATCR1_ATCKSEL_Pos)         /*!< 0x00040000 */

+#define TAMP_ATCR1_ATPER_Pos         (24U)

+#define TAMP_ATCR1_ATPER_Msk         (0x7UL << TAMP_ATCR1_ATPER_Pos)           /*!< 0x07000000 */

+#define TAMP_ATCR1_ATPER             TAMP_ATCR1_ATPER_Msk

+#define TAMP_ATCR1_ATOSHARE_Pos      (30U)

+#define TAMP_ATCR1_ATOSHARE_Msk      (0x1UL << TAMP_ATCR1_ATOSHARE_Pos)        /*!< 0x40000000 */

+#define TAMP_ATCR1_ATOSHARE          TAMP_ATCR1_ATOSHARE_Msk

+#define TAMP_ATCR1_FLTEN_Pos         (31U)

+#define TAMP_ATCR1_FLTEN_Msk         (0x1UL << TAMP_ATCR1_FLTEN_Pos)           /*!< 0x80000000 */

+#define TAMP_ATCR1_FLTEN             TAMP_ATCR1_FLTEN_Msk

+

+/********************  Bits definition for TAMP_ATSEEDR register  *************/

+#define TAMP_ATSEEDR_SEED_Pos        (0U)

+#define TAMP_ATSEEDR_SEED_Msk        (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos)   /*!< 0xFFFFFFFF */

+#define TAMP_ATSEEDR_SEED            TAMP_ATSEEDR_SEED_Msk

+

+/********************  Bits definition for TAMP_ATOR register  ****************/

+#define TAMP_ATOR_PRNG_Pos           (0U)

+#define TAMP_ATOR_PRNG_Msk           (0x000000FFUL << TAMP_ATOR_PRNG_Pos)      /*!< 0x000000FF */

+#define TAMP_ATOR_PRNG               TAMP_ATOR_PRNG_Msk

+#define TAMP_ATOR_SEEDF_Pos          (14U)

+#define TAMP_ATOR_SEEDF_Msk          (0x01UL << TAMP_ATOR_SEEDF_Pos)           /*!< 0x00004000 */

+#define TAMP_ATOR_SEEDF              TAMP_ATOR_SEEDF_Msk

+#define TAMP_ATOR_INITS_Pos          (15U)

+#define TAMP_ATOR_INITS_Msk          (0x01UL << TAMP_ATOR_INITS_Pos)           /*!< 0x00008000 */

+#define TAMP_ATOR_INITS              TAMP_ATOR_INITS_Msk

+

+/********************  Bits definition for TAMP_IER register  *****************/

+#define TAMP_IER_TAMP1IE_Pos         (0U)

+#define TAMP_IER_TAMP1IE_Msk         (0x1UL << TAMP_IER_TAMP1IE_Pos)           /*!< 0x00000001 */

+#define TAMP_IER_TAMP1IE             TAMP_IER_TAMP1IE_Msk

+#define TAMP_IER_TAMP2IE_Pos         (1U)

+#define TAMP_IER_TAMP2IE_Msk         (0x1UL << TAMP_IER_TAMP2IE_Pos)           /*!< 0x00000002 */

+#define TAMP_IER_TAMP2IE             TAMP_IER_TAMP2IE_Msk

+#define TAMP_IER_TAMP3IE_Pos         (2U)

+#define TAMP_IER_TAMP3IE_Msk         (0x1UL << TAMP_IER_TAMP3IE_Pos)           /*!< 0x00000004 */

+#define TAMP_IER_TAMP3IE             TAMP_IER_TAMP3IE_Msk

+#define TAMP_IER_ITAMP1IE_Pos        (16U)

+#define TAMP_IER_ITAMP1IE_Msk        (0x1UL << TAMP_IER_ITAMP1IE_Pos)          /*!< 0x00010000 */

+#define TAMP_IER_ITAMP1IE            TAMP_IER_ITAMP1IE_Msk

+#define TAMP_IER_ITAMP2IE_Pos        (17U)

+#define TAMP_IER_ITAMP2IE_Msk        (0x1UL << TAMP_IER_ITAMP2IE_Pos)          /*!< 0x00020000 */

+#define TAMP_IER_ITAMP2IE            TAMP_IER_ITAMP2IE_Msk

+#define TAMP_IER_ITAMP3IE_Pos        (18U)

+#define TAMP_IER_ITAMP3IE_Msk        (0x1UL << TAMP_IER_ITAMP3IE_Pos)          /*!< 0x00040000 */

+#define TAMP_IER_ITAMP3IE            TAMP_IER_ITAMP3IE_Msk

+#define TAMP_IER_ITAMP4IE_Pos        (19U)

+#define TAMP_IER_ITAMP4IE_Msk        (0x1UL << TAMP_IER_ITAMP4IE_Pos)          /*!< 0x00080000 */

+#define TAMP_IER_ITAMP4IE            TAMP_IER_ITAMP4IE_Msk

+#define TAMP_IER_ITAMP5IE_Pos        (20U)

+#define TAMP_IER_ITAMP5IE_Msk        (0x1UL << TAMP_IER_ITAMP5IE_Pos)          /*!< 0x00100000 */

+#define TAMP_IER_ITAMP5IE            TAMP_IER_ITAMP5IE_Msk

+#define TAMP_IER_ITAMP6IE_Pos        (21U)

+#define TAMP_IER_ITAMP6IE_Msk        (0x1UL << TAMP_IER_ITAMP6IE_Pos)          /*!< 0x00200000 */

+#define TAMP_IER_ITAMP6IE            TAMP_IER_ITAMP6IE_Msk

+#define TAMP_IER_ITAMP8IE_Pos        (23U)

+#define TAMP_IER_ITAMP8IE_Msk        (0x1UL << TAMP_IER_ITAMP8IE_Pos)          /*!< 0x00800000 */

+#define TAMP_IER_ITAMP8IE            TAMP_IER_ITAMP8IE_Msk

+

+/********************  Bits definition for TAMP_SR register  *****************/

+#define TAMP_SR_TAMP1F_Pos           (0U)

+#define TAMP_SR_TAMP1F_Msk           (0x1UL << TAMP_SR_TAMP1F_Pos)             /*!< 0x00000001 */

+#define TAMP_SR_TAMP1F               TAMP_SR_TAMP1F_Msk

+#define TAMP_SR_TAMP2F_Pos           (1U)

+#define TAMP_SR_TAMP2F_Msk           (0x1UL << TAMP_SR_TAMP2F_Pos)             /*!< 0x00000002 */

+#define TAMP_SR_TAMP2F               TAMP_SR_TAMP2F_Msk

+#define TAMP_SR_TAMP3F_Pos           (2U)

+#define TAMP_SR_TAMP3F_Msk           (0x1UL << TAMP_SR_TAMP3F_Pos)             /*!< 0x00000004 */

+#define TAMP_SR_TAMP3F               TAMP_SR_TAMP3F_Msk

+#define TAMP_SR_ITAMP1F_Pos          (16U)

+#define TAMP_SR_ITAMP1F_Msk          (0x1UL << TAMP_SR_ITAMP1F_Pos)            /*!< 0x00010000 */

+#define TAMP_SR_ITAMP1F              TAMP_SR_ITAMP1F_Msk

+#define TAMP_SR_ITAMP2F_Pos          (17U)

+#define TAMP_SR_ITAMP2F_Msk          (0x1UL << TAMP_SR_ITAMP2F_Pos)            /*!< 0x00020000 */

+#define TAMP_SR_ITAMP2F              TAMP_SR_ITAMP2F_Msk

+#define TAMP_SR_ITAMP3F_Pos          (18U)

+#define TAMP_SR_ITAMP3F_Msk          (0x1UL << TAMP_SR_ITAMP3F_Pos)            /*!< 0x00040000 */

+#define TAMP_SR_ITAMP3F              TAMP_SR_ITAMP3F_Msk

+#define TAMP_SR_ITAMP4F_Pos          (19U)

+#define TAMP_SR_ITAMP4F_Msk          (0x1UL << TAMP_SR_ITAMP4F_Pos)            /*!< 0x00080000 */

+#define TAMP_SR_ITAMP4F              TAMP_SR_ITAMP4F_Msk

+#define TAMP_SR_ITAMP5F_Pos          (20U)

+#define TAMP_SR_ITAMP5F_Msk          (0x1UL << TAMP_SR_ITAMP5F_Pos)            /*!< 0x00100000 */

+#define TAMP_SR_ITAMP5F              TAMP_SR_ITAMP5F_Msk

+#define TAMP_SR_ITAMP6F_Pos          (21U)

+#define TAMP_SR_ITAMP6F_Msk          (0x1UL << TAMP_SR_ITAMP6F_Pos)            /*!< 0x00200000 */

+#define TAMP_SR_ITAMP6F              TAMP_SR_ITAMP6F_Msk

+#define TAMP_SR_ITAMP8F_Pos          (23U)

+#define TAMP_SR_ITAMP8F_Msk          (0x1UL << TAMP_SR_ITAMP8F_Pos)            /*!< 0x00800000 */

+#define TAMP_SR_ITAMP8F              TAMP_SR_ITAMP8F_Msk

+

+/********************  Bits definition for TAMP_MISR register  ************ *****/

+#define TAMP_MISR_TAMP1MF_Pos        (0U)

+#define TAMP_MISR_TAMP1MF_Msk        (0x1UL << TAMP_MISR_TAMP1MF_Pos)           /*!< 0x00000001 */

+#define TAMP_MISR_TAMP1MF            TAMP_MISR_TAMP1MF_Msk

+#define TAMP_MISR_TAMP2MF_Pos        (1U)

+#define TAMP_MISR_TAMP2MF_Msk        (0x1UL << TAMP_MISR_TAMP2MF_Pos)           /*!< 0x00000002 */

+#define TAMP_MISR_TAMP2MF            TAMP_MISR_TAMP2MF_Msk

+#define TAMP_MISR_TAMP3MF_Pos        (2U)

+#define TAMP_MISR_TAMP3MF_Msk        (0x1UL << TAMP_MISR_TAMP3MF_Pos)          /*!< 0x00000004 */

+#define TAMP_MISR_TAMP3MF            TAMP_MISR_TAMP3MF_Msk

+#define TAMP_MISR_ITAMP1MF_Pos       (16U)

+#define TAMP_MISR_ITAMP1MF_Msk       (0x1UL << TAMP_MISR_ITAMP1MF_Pos)         /*!< 0x00010000 */

+#define TAMP_MISR_ITAMP1MF           TAMP_MISR_ITAMP1MF_Msk

+#define TAMP_MISR_ITAMP2MF_Pos       (17U)

+#define TAMP_MISR_ITAMP2MF_Msk       (0x1UL << TAMP_MISR_ITAMP2MF_Pos)         /*!< 0x00020000 */

+#define TAMP_MISR_ITAMP2MF           TAMP_MISR_ITAMP2MF_Msk

+#define TAMP_MISR_ITAMP3MF_Pos       (18U)

+#define TAMP_MISR_ITAMP3MF_Msk       (0x1UL << TAMP_MISR_ITAMP3MF_Pos)         /*!< 0x00040000 */

+#define TAMP_MISR_ITAMP3MF           TAMP_MISR_ITAMP3MF_Msk

+#define TAMP_MISR_ITAMP4MF_Pos       (19U)

+#define TAMP_MISR_ITAMP4MF_Msk       (0x1UL << TAMP_MISR_ITAMP4MF_Pos)         /*!< 0x00080000 */

+#define TAMP_MISR_ITAMP4MF           TAMP_MISR_ITAMP4MF_Msk

+#define TAMP_MISR_ITAMP5MF_Pos       (20U)

+#define TAMP_MISR_ITAMP5MF_Msk       (0x1UL << TAMP_MISR_ITAMP5MF_Pos)         /*!< 0x00100000 */

+#define TAMP_MISR_ITAMP5MF           TAMP_MISR_ITAMP5MF_Msk

+#define TAMP_MISR_ITAMP6MF_Pos       (21U)

+#define TAMP_MISR_ITAMP6MF_Msk       (0x1UL << TAMP_MISR_ITAMP6MF_Pos)         /*!< 0x00200000 */

+#define TAMP_MISR_ITAMP6MF           TAMP_MISR_ITAMP6MF_Msk

+#define TAMP_MISR_ITAMP8MF_Pos       (23U)

+#define TAMP_MISR_ITAMP8MF_Msk       (0x1UL << TAMP_MISR_ITAMP8MF_Pos)         /*!< 0x00800000 */

+#define TAMP_MISR_ITAMP8MF           TAMP_MISR_ITAMP8MF_Msk

+

+/********************  Bits definition for TAMP_SCR register  *****************/

+#define TAMP_SCR_CTAMP1F_Pos         (0U)

+#define TAMP_SCR_CTAMP1F_Msk         (0x1UL << TAMP_SCR_CTAMP1F_Pos)            /*!< 0x00000001 */

+#define TAMP_SCR_CTAMP1F             TAMP_SCR_CTAMP1F_Msk

+#define TAMP_SCR_CTAMP2F_Pos         (1U)

+#define TAMP_SCR_CTAMP2F_Msk         (0x1UL << TAMP_SCR_CTAMP2F_Pos)            /*!< 0x00000002 */

+#define TAMP_SCR_CTAMP2F             TAMP_SCR_CTAMP2F_Msk

+#define TAMP_SCR_CTAMP3F_Pos         (2U)

+#define TAMP_SCR_CTAMP3F_Msk         (0x1UL << TAMP_SCR_CTAMP3F_Pos)           /*!< 0x00000004 */

+#define TAMP_SCR_CTAMP3F             TAMP_SCR_CTAMP3F_Msk

+#define TAMP_SCR_CITAMP1F_Pos        (16U)

+#define TAMP_SCR_CITAMP1F_Msk        (0x1UL << TAMP_SCR_CITAMP1F_Pos)          /*!< 0x00010000 */

+#define TAMP_SCR_CITAMP1F            TAMP_SCR_CITAMP1F_Msk

+#define TAMP_SCR_CITAMP2F_Pos        (17U)

+#define TAMP_SCR_CITAMP2F_Msk        (0x1UL << TAMP_SCR_CITAMP2F_Pos)          /*!< 0x00020000 */

+#define TAMP_SCR_CITAMP2F            TAMP_SCR_CITAMP2F_Msk

+#define TAMP_SCR_CITAMP3F_Pos        (18U)

+#define TAMP_SCR_CITAMP3F_Msk        (0x1UL << TAMP_SCR_CITAMP3F_Pos)          /*!< 0x00040000 */

+#define TAMP_SCR_CITAMP3F            TAMP_SCR_CITAMP3F_Msk

+#define TAMP_SCR_CITAMP4F_Pos        (19U)

+#define TAMP_SCR_CITAMP4F_Msk        (0x1UL << TAMP_SCR_CITAMP4F_Pos)          /*!< 0x00080000 */

+#define TAMP_SCR_CITAMP4F            TAMP_SCR_CITAMP4F_Msk

+#define TAMP_SCR_CITAMP5F_Pos        (20U)

+#define TAMP_SCR_CITAMP5F_Msk        (0x1UL << TAMP_SCR_CITAMP5F_Pos)          /*!< 0x00100000 */

+#define TAMP_SCR_CITAMP5F            TAMP_SCR_CITAMP5F_Msk

+#define TAMP_SCR_CITAMP6F_Pos        (21U)

+#define TAMP_SCR_CITAMP6F_Msk        (0x1UL << TAMP_SCR_CITAMP6F_Pos)          /*!< 0x00200000 */

+#define TAMP_SCR_CITAMP6F            TAMP_SCR_CITAMP6F_Msk

+#define TAMP_SCR_CITAMP8F_Pos        (23U)

+#define TAMP_SCR_CITAMP8F_Msk        (0x1UL << TAMP_SCR_CITAMP8F_Pos)          /*!< 0x00800000 */

+#define TAMP_SCR_CITAMP8F            TAMP_SCR_CITAMP8F_Msk

+

+/********************  Bits definition for TAMP_COUNTR register  **************/

+#define TAMP_COUNTR_Pos              (16U)

+#define TAMP_COUNTR_Msk              (0xFFFFUL << TAMP_COUNTR_Pos)             /*!< 0xFFFF0000 */

+#define TAMP_COUNTR                  TAMP_COUNTR_Msk

+

+/********************  Bits definition for TAMP_OR register  ******************/

+#define TAMP_OR_OUT3_RMP_Pos         (0U)

+#define TAMP_OR_OUT3_RMP_Msk         (0x1UL << TAMP_OR_OUT3_RMP_Pos)           /*!< 0x00000001 */

+#define TAMP_OR_OUT3_RMP             TAMP_OR_OUT3_RMP_Msk

+

+/********************  Bits definition for TAMP_BKP0R register  ***************/

+#define TAMP_BKP0R_Pos               (0U)

+#define TAMP_BKP0R_Msk               (0xFFFFFFFFUL << TAMP_BKP0R_Pos)           /*!< 0xFFFFFFFF */

+#define TAMP_BKP0R                   TAMP_BKP0R_Msk

+

+/********************  Bits definition for TAMP_BKP1R register  ****************/

+#define TAMP_BKP1R_Pos               (0U)

+#define TAMP_BKP1R_Msk               (0xFFFFFFFFUL << TAMP_BKP1R_Pos)           /*!< 0xFFFFFFFF */

+#define TAMP_BKP1R                   TAMP_BKP1R_Msk

+

+/********************  Bits definition for TAMP_BKP2R register  ****************/

+#define TAMP_BKP2R_Pos               (0U)

+#define TAMP_BKP2R_Msk               (0xFFFFFFFFUL << TAMP_BKP2R_Pos)           /*!< 0xFFFFFFFF */

+#define TAMP_BKP2R                   TAMP_BKP2R_Msk

+

+/********************  Bits definition for TAMP_BKP3R register  ****************/

+#define TAMP_BKP3R_Pos               (0U)

+#define TAMP_BKP3R_Msk               (0xFFFFFFFFUL << TAMP_BKP3R_Pos)           /*!< 0xFFFFFFFF */

+#define TAMP_BKP3R                   TAMP_BKP3R_Msk

+

+/********************  Bits definition for TAMP_BKP4R register  ****************/

+#define TAMP_BKP4R_Pos               (0U)

+#define TAMP_BKP4R_Msk               (0xFFFFFFFFUL << TAMP_BKP4R_Pos)           /*!< 0xFFFFFFFF */

+#define TAMP_BKP4R                   TAMP_BKP4R_Msk

+

+/********************  Bits definition for TAMP_BKP5R register  ****************/

+#define TAMP_BKP5R_Pos               (0U)

+#define TAMP_BKP5R_Msk               (0xFFFFFFFFUL << TAMP_BKP5R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP5R                   TAMP_BKP5R_Msk

+

+/********************  Bits definition for TAMP_BKP6R register  ****************/

+#define TAMP_BKP6R_Pos               (0U)

+#define TAMP_BKP6R_Msk               (0xFFFFFFFFUL << TAMP_BKP6R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP6R                   TAMP_BKP6R_Msk

+

+/********************  Bits definition for TAMP_BKP7R register  ****************/

+#define TAMP_BKP7R_Pos               (0U)

+#define TAMP_BKP7R_Msk               (0xFFFFFFFFUL << TAMP_BKP7R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP7R                   TAMP_BKP7R_Msk

+

+/********************  Bits definition for TAMP_BKP8R register  ****************/

+#define TAMP_BKP8R_Pos               (0U)

+#define TAMP_BKP8R_Msk               (0xFFFFFFFFUL << TAMP_BKP8R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP8R                   TAMP_BKP8R_Msk

+

+/********************  Bits definition for TAMP_BKP9R register  ****************/

+#define TAMP_BKP9R_Pos               (0U)

+#define TAMP_BKP9R_Msk               (0xFFFFFFFFUL << TAMP_BKP9R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP9R                   TAMP_BKP9R_Msk

+

+/********************  Bits definition for TAMP_BKP10R register  ***************/

+#define TAMP_BKP10R_Pos              (0U)

+#define TAMP_BKP10R_Msk              (0xFFFFFFFFUL << TAMP_BKP10R_Pos)         /*!< 0xFFFFFFFF */

+#define TAMP_BKP10R                  TAMP_BKP10R_Msk

+

+/********************  Bits definition for TAMP_BKP11R register  ***************/

+#define TAMP_BKP11R_Pos              (0U)

+#define TAMP_BKP11R_Msk              (0xFFFFFFFFUL << TAMP_BKP11R_Pos)         /*!< 0xFFFFFFFF */

+#define TAMP_BKP11R                  TAMP_BKP11R_Msk

+

+/********************  Bits definition for TAMP_BKP12R register  ***************/

+#define TAMP_BKP12R_Pos              (0U)

+#define TAMP_BKP12R_Msk              (0xFFFFFFFFUL << TAMP_BKP12R_Pos)         /*!< 0xFFFFFFFF */

+#define TAMP_BKP12R                  TAMP_BKP12R_Msk

+

+/********************  Bits definition for TAMP_BKP13R register  ***************/

+#define TAMP_BKP13R_Pos              (0U)

+#define TAMP_BKP13R_Msk              (0xFFFFFFFFUL << TAMP_BKP13R_Pos)         /*!< 0xFFFFFFFF */

+#define TAMP_BKP13R                  TAMP_BKP13R_Msk

+

+/********************  Bits definition for TAMP_BKP14R register  ***************/

+#define TAMP_BKP14R_Pos              (0U)

+#define TAMP_BKP14R_Msk              (0xFFFFFFFFUL << TAMP_BKP14R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP14R                  TAMP_BKP14R_Msk

+

+/********************  Bits definition for TAMP_BKP15R register  ***************/

+#define TAMP_BKP15R_Pos              (0U)

+#define TAMP_BKP15R_Msk              (0xFFFFFFFFUL << TAMP_BKP15R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP15R                  TAMP_BKP15R_Msk

+

+/********************  Bits definition for TAMP_BKP16R register  ***************/

+#define TAMP_BKP16R_Pos              (0U)

+#define TAMP_BKP16R_Msk              (0xFFFFFFFFUL << TAMP_BKP16R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP16R                  TAMP_BKP16R_Msk

+

+/********************  Bits definition for TAMP_BKP17R register  ***************/

+#define TAMP_BKP17R_Pos              (0U)

+#define TAMP_BKP17R_Msk              (0xFFFFFFFFUL << TAMP_BKP17R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP17R                  TAMP_BKP17R_Msk

+

+/********************  Bits definition for TAMP_BKP18R register  ***************/

+#define TAMP_BKP18R_Pos              (0U)

+#define TAMP_BKP18R_Msk              (0xFFFFFFFFUL << TAMP_BKP18R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP18R                  TAMP_BKP18R_Msk

+

+/********************  Bits definition for TAMP_BKP19R register  ***************/

+#define TAMP_BKP19R_Pos              (0U)

+#define TAMP_BKP19R_Msk              (0xFFFFFFFFUL << TAMP_BKP19R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP19R                  TAMP_BKP19R_Msk

+

+/********************  Bits definition for TAMP_BKP20R register  ***************/

+#define TAMP_BKP20R_Pos              (0U)

+#define TAMP_BKP20R_Msk              (0xFFFFFFFFUL << TAMP_BKP20R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP20R                  TAMP_BKP20R_Msk

+

+/********************  Bits definition for TAMP_BKP21R register  ***************/

+#define TAMP_BKP21R_Pos              (0U)

+#define TAMP_BKP21R_Msk              (0xFFFFFFFFUL << TAMP_BKP21R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP21R                  TAMP_BKP21R_Msk

+

+/********************  Bits definition for TAMP_BKP22R register  ***************/

+#define TAMP_BKP22R_Pos              (0U)

+#define TAMP_BKP22R_Msk              (0xFFFFFFFFUL << TAMP_BKP22R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP22R                  TAMP_BKP22R_Msk

+

+/********************  Bits definition for TAMP_BKP23R register  ***************/

+#define TAMP_BKP23R_Pos              (0U)

+#define TAMP_BKP23R_Msk              (0xFFFFFFFFUL << TAMP_BKP23R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP23R                  TAMP_BKP23R_Msk

+

+/********************  Bits definition for TAMP_BKP24R register  ***************/

+#define TAMP_BKP24R_Pos              (0U)

+#define TAMP_BKP24R_Msk              (0xFFFFFFFFUL << TAMP_BKP24R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP24R                  TAMP_BKP24R_Msk

+

+/********************  Bits definition for TAMP_BKP25R register  ***************/

+#define TAMP_BKP25R_Pos              (0U)

+#define TAMP_BKP25R_Msk              (0xFFFFFFFFUL << TAMP_BKP25R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP25R                  TAMP_BKP25R_Msk

+

+/********************  Bits definition for TAMP_BKP26R register  ***************/

+#define TAMP_BKP26R_Pos              (0U)

+#define TAMP_BKP26R_Msk              (0xFFFFFFFFUL << TAMP_BKP26R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP26R                  TAMP_BKP26R_Msk

+

+/********************  Bits definition for TAMP_BKP27R register  ***************/

+#define TAMP_BKP27R_Pos              (0U)

+#define TAMP_BKP27R_Msk              (0xFFFFFFFFUL << TAMP_BKP27R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP27R                  TAMP_BKP27R_Msk

+

+/********************  Bits definition for TAMP_BKP28R register  ***************/

+#define TAMP_BKP28R_Pos              (0U)

+#define TAMP_BKP28R_Msk              (0xFFFFFFFFUL << TAMP_BKP28R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP28R                  TAMP_BKP28R_Msk

+

+/********************  Bits definition for TAMP_BKP29R register  ***************/

+#define TAMP_BKP29R_Pos              (0U)

+#define TAMP_BKP29R_Msk              (0xFFFFFFFFUL << TAMP_BKP29R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP29R                  TAMP_BKP29R_Msk

+

+/********************  Bits definition for TAMP_BKP30R register  ***************/

+#define TAMP_BKP30R_Pos              (0U)

+#define TAMP_BKP30R_Msk              (0xFFFFFFFFUL << TAMP_BKP30R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP30R                  TAMP_BKP30R_Msk

+

+/********************  Bits definition for TAMP_BKP31R register  ***************/

+#define TAMP_BKP31R_Pos              (0U)

+#define TAMP_BKP31R_Msk              (0xFFFFFFFFUL << TAMP_BKP31R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP31R                  TAMP_BKP31R_Msk

+

+/******************** Number of backup registers ******************************/

+#define TAMP_BKP_NUMBER_Pos             (5U)

+#define TAMP_BKP_NUMBER_Msk             (0x1UL << TAMP_BKP_NUMBER_Pos)         /*!< 0x00000080 */

+#define TAMP_BKP_NUMBER                 TAMP_BKP_NUMBER_Msk                    /*!< 32 BKPREG  */

+

+/******************************************************************************/

+/*                                                                            */

+/*                              SPDIF-RX Interface                            */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for SPDIF_CR register  ******************/

+#define SPDIFRX_CR_SPDIFEN_Pos      (0U)

+#define SPDIFRX_CR_SPDIFEN_Msk      (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)          /*!< 0x00000003 */

+#define SPDIFRX_CR_SPDIFEN          SPDIFRX_CR_SPDIFEN_Msk                     /*!<Peripheral Block Enable                      */

+#define SPDIFRX_CR_RXDMAEN_Pos      (2U)

+#define SPDIFRX_CR_RXDMAEN_Msk      (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)          /*!< 0x00000004 */

+#define SPDIFRX_CR_RXDMAEN          SPDIFRX_CR_RXDMAEN_Msk                     /*!<Receiver DMA Enable for data flow            */

+#define SPDIFRX_CR_RXSTEO_Pos       (3U)

+#define SPDIFRX_CR_RXSTEO_Msk       (0x1UL << SPDIFRX_CR_RXSTEO_Pos)           /*!< 0x00000008 */

+#define SPDIFRX_CR_RXSTEO           SPDIFRX_CR_RXSTEO_Msk                      /*!<Stereo Mode                                  */

+#define SPDIFRX_CR_DRFMT_Pos        (4U)

+#define SPDIFRX_CR_DRFMT_Msk        (0x3UL << SPDIFRX_CR_DRFMT_Pos)            /*!< 0x00000030 */

+#define SPDIFRX_CR_DRFMT            SPDIFRX_CR_DRFMT_Msk                       /*!<RX Data format                               */

+#define SPDIFRX_CR_PMSK_Pos         (6U)

+#define SPDIFRX_CR_PMSK_Msk         (0x1UL << SPDIFRX_CR_PMSK_Pos)             /*!< 0x00000040 */

+#define SPDIFRX_CR_PMSK             SPDIFRX_CR_PMSK_Msk                        /*!<Mask Parity error bit                        */

+#define SPDIFRX_CR_VMSK_Pos         (7U)

+#define SPDIFRX_CR_VMSK_Msk         (0x1UL << SPDIFRX_CR_VMSK_Pos)             /*!< 0x00000080 */

+#define SPDIFRX_CR_VMSK             SPDIFRX_CR_VMSK_Msk                        /*!<Mask of Validity bit                         */

+#define SPDIFRX_CR_CUMSK_Pos        (8U)

+#define SPDIFRX_CR_CUMSK_Msk        (0x1UL << SPDIFRX_CR_CUMSK_Pos)            /*!< 0x00000100 */

+#define SPDIFRX_CR_CUMSK            SPDIFRX_CR_CUMSK_Msk                       /*!<Mask of channel status and user bits         */

+#define SPDIFRX_CR_PTMSK_Pos        (9U)

+#define SPDIFRX_CR_PTMSK_Msk        (0x1UL << SPDIFRX_CR_PTMSK_Pos)            /*!< 0x00000200 */

+#define SPDIFRX_CR_PTMSK            SPDIFRX_CR_PTMSK_Msk                       /*!<Mask of Preamble Type bits                   */

+#define SPDIFRX_CR_CBDMAEN_Pos      (10U)

+#define SPDIFRX_CR_CBDMAEN_Msk      (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)          /*!< 0x00000400 */

+#define SPDIFRX_CR_CBDMAEN          SPDIFRX_CR_CBDMAEN_Msk                     /*!<Control Buffer DMA ENable for control flow   */

+#define SPDIFRX_CR_CHSEL_Pos        (11U)

+#define SPDIFRX_CR_CHSEL_Msk        (0x1UL << SPDIFRX_CR_CHSEL_Pos)            /*!< 0x00000800 */

+#define SPDIFRX_CR_CHSEL            SPDIFRX_CR_CHSEL_Msk                       /*!<Channel Selection                            */

+#define SPDIFRX_CR_NBTR_Pos         (12U)

+#define SPDIFRX_CR_NBTR_Msk         (0x3UL << SPDIFRX_CR_NBTR_Pos)             /*!< 0x00003000 */

+#define SPDIFRX_CR_NBTR             SPDIFRX_CR_NBTR_Msk                        /*!<Maximum allowed re-tries during synchronization phase */

+#define SPDIFRX_CR_WFA_Pos          (14U)

+#define SPDIFRX_CR_WFA_Msk          (0x1UL << SPDIFRX_CR_WFA_Pos)              /*!< 0x00004000 */

+#define SPDIFRX_CR_WFA              SPDIFRX_CR_WFA_Msk                         /*!<Wait For Activity     */

+#define SPDIFRX_CR_INSEL_Pos        (16U)

+#define SPDIFRX_CR_INSEL_Msk        (0x7UL << SPDIFRX_CR_INSEL_Pos)            /*!< 0x00070000 */

+#define SPDIFRX_CR_INSEL            SPDIFRX_CR_INSEL_Msk                       /*!<SPDIF input selection */

+#define SPDIFRX_CR_CKSEN_Pos        (20U)

+#define SPDIFRX_CR_CKSEN_Msk        (0x1UL << SPDIFRX_CR_CKSEN_Pos)            /*!< 0x00100000 */

+#define SPDIFRX_CR_CKSEN            SPDIFRX_CR_CKSEN_Msk                       /*!<Symbol Clock Enable */

+#define SPDIFRX_CR_CKSBKPEN_Pos     (21U)

+#define SPDIFRX_CR_CKSBKPEN_Msk     (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)         /*!< 0x00200000 */

+#define SPDIFRX_CR_CKSBKPEN         SPDIFRX_CR_CKSBKPEN_Msk                    /*!<Backup Symbol Clock Enable */

+

+/*******************  Bit definition for SPDIFRX_IMR register  *******************/

+#define SPDIFRX_IMR_RXNEIE_Pos      (0U)

+#define SPDIFRX_IMR_RXNEIE_Msk      (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)          /*!< 0x00000001 */

+#define SPDIFRX_IMR_RXNEIE          SPDIFRX_IMR_RXNEIE_Msk                     /*!<RXNE interrupt enable                              */

+#define SPDIFRX_IMR_CSRNEIE_Pos     (1U)

+#define SPDIFRX_IMR_CSRNEIE_Msk     (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)         /*!< 0x00000002 */

+#define SPDIFRX_IMR_CSRNEIE         SPDIFRX_IMR_CSRNEIE_Msk                    /*!<Control Buffer Ready Interrupt Enable              */

+#define SPDIFRX_IMR_PERRIE_Pos      (2U)

+#define SPDIFRX_IMR_PERRIE_Msk      (0x1UL << SPDIFRX_IMR_PERRIE_Pos)          /*!< 0x00000004 */

+#define SPDIFRX_IMR_PERRIE          SPDIFRX_IMR_PERRIE_Msk                     /*!<Parity error interrupt enable                      */

+#define SPDIFRX_IMR_OVRIE_Pos       (3U)

+#define SPDIFRX_IMR_OVRIE_Msk       (0x1UL << SPDIFRX_IMR_OVRIE_Pos)           /*!< 0x00000008 */

+#define SPDIFRX_IMR_OVRIE           SPDIFRX_IMR_OVRIE_Msk                      /*!<Overrun error Interrupt Enable                     */

+#define SPDIFRX_IMR_SBLKIE_Pos      (4U)

+#define SPDIFRX_IMR_SBLKIE_Msk      (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)          /*!< 0x00000010 */

+#define SPDIFRX_IMR_SBLKIE          SPDIFRX_IMR_SBLKIE_Msk                     /*!<Synchronization Block Detected Interrupt Enable    */

+#define SPDIFRX_IMR_SYNCDIE_Pos     (5U)

+#define SPDIFRX_IMR_SYNCDIE_Msk     (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)         /*!< 0x00000020 */

+#define SPDIFRX_IMR_SYNCDIE         SPDIFRX_IMR_SYNCDIE_Msk                    /*!<Synchronization Done                               */

+#define SPDIFRX_IMR_IFEIE_Pos       (6U)

+#define SPDIFRX_IMR_IFEIE_Msk       (0x1UL << SPDIFRX_IMR_IFEIE_Pos)           /*!< 0x00000040 */

+#define SPDIFRX_IMR_IFEIE           SPDIFRX_IMR_IFEIE_Msk                      /*!<Serial Interface Error Interrupt Enable            */

+

+/*******************  Bit definition for SPDIFRX_SR register  *******************/

+#define SPDIFRX_SR_RXNE_Pos         (0U)

+#define SPDIFRX_SR_RXNE_Msk         (0x1UL << SPDIFRX_SR_RXNE_Pos)             /*!< 0x00000001 */

+#define SPDIFRX_SR_RXNE             SPDIFRX_SR_RXNE_Msk                        /*!<Read data register not empty                          */

+#define SPDIFRX_SR_CSRNE_Pos        (1U)

+#define SPDIFRX_SR_CSRNE_Msk        (0x1UL << SPDIFRX_SR_CSRNE_Pos)            /*!< 0x00000002 */

+#define SPDIFRX_SR_CSRNE            SPDIFRX_SR_CSRNE_Msk                       /*!<The Control Buffer register is not empty              */

+#define SPDIFRX_SR_PERR_Pos         (2U)

+#define SPDIFRX_SR_PERR_Msk         (0x1UL << SPDIFRX_SR_PERR_Pos)             /*!< 0x00000004 */

+#define SPDIFRX_SR_PERR             SPDIFRX_SR_PERR_Msk                        /*!<Parity error                                          */

+#define SPDIFRX_SR_OVR_Pos          (3U)

+#define SPDIFRX_SR_OVR_Msk          (0x1UL << SPDIFRX_SR_OVR_Pos)              /*!< 0x00000008 */

+#define SPDIFRX_SR_OVR              SPDIFRX_SR_OVR_Msk                         /*!<Overrun error                                         */

+#define SPDIFRX_SR_SBD_Pos          (4U)

+#define SPDIFRX_SR_SBD_Msk          (0x1UL << SPDIFRX_SR_SBD_Pos)              /*!< 0x00000010 */

+#define SPDIFRX_SR_SBD              SPDIFRX_SR_SBD_Msk                         /*!<Synchronization Block Detected                        */

+#define SPDIFRX_SR_SYNCD_Pos        (5U)

+#define SPDIFRX_SR_SYNCD_Msk        (0x1UL << SPDIFRX_SR_SYNCD_Pos)            /*!< 0x00000020 */

+#define SPDIFRX_SR_SYNCD            SPDIFRX_SR_SYNCD_Msk                       /*!<Synchronization Done                                  */

+#define SPDIFRX_SR_FERR_Pos         (6U)

+#define SPDIFRX_SR_FERR_Msk         (0x1UL << SPDIFRX_SR_FERR_Pos)             /*!< 0x00000040 */

+#define SPDIFRX_SR_FERR             SPDIFRX_SR_FERR_Msk                        /*!<Framing error                                         */

+#define SPDIFRX_SR_SERR_Pos         (7U)

+#define SPDIFRX_SR_SERR_Msk         (0x1UL << SPDIFRX_SR_SERR_Pos)             /*!< 0x00000080 */

+#define SPDIFRX_SR_SERR             SPDIFRX_SR_SERR_Msk                        /*!<Synchronization error                                 */

+#define SPDIFRX_SR_TERR_Pos         (8U)

+#define SPDIFRX_SR_TERR_Msk         (0x1UL << SPDIFRX_SR_TERR_Pos)             /*!< 0x00000100 */

+#define SPDIFRX_SR_TERR             SPDIFRX_SR_TERR_Msk                        /*!<Time-out error                                        */

+#define SPDIFRX_SR_WIDTH5_Pos       (16U)

+#define SPDIFRX_SR_WIDTH5_Msk       (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)        /*!< 0x7FFF0000 */

+#define SPDIFRX_SR_WIDTH5           SPDIFRX_SR_WIDTH5_Msk                      /*!<Duration of 5 symbols counted with spdif_clk          */

+

+/*******************  Bit definition for SPDIFRX_IFCR register  *******************/

+#define SPDIFRX_IFCR_PERRCF_Pos     (2U)

+#define SPDIFRX_IFCR_PERRCF_Msk     (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)         /*!< 0x00000004 */

+#define SPDIFRX_IFCR_PERRCF         SPDIFRX_IFCR_PERRCF_Msk                    /*!<Clears the Parity error flag                         */

+#define SPDIFRX_IFCR_OVRCF_Pos      (3U)

+#define SPDIFRX_IFCR_OVRCF_Msk      (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)          /*!< 0x00000008 */

+#define SPDIFRX_IFCR_OVRCF          SPDIFRX_IFCR_OVRCF_Msk                     /*!<Clears the Overrun error flag                        */

+#define SPDIFRX_IFCR_SBDCF_Pos      (4U)

+#define SPDIFRX_IFCR_SBDCF_Msk      (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)          /*!< 0x00000010 */

+#define SPDIFRX_IFCR_SBDCF          SPDIFRX_IFCR_SBDCF_Msk                     /*!<Clears the Synchronization Block Detected flag       */

+#define SPDIFRX_IFCR_SYNCDCF_Pos    (5U)

+#define SPDIFRX_IFCR_SYNCDCF_Msk    (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)        /*!< 0x00000020 */

+#define SPDIFRX_IFCR_SYNCDCF        SPDIFRX_IFCR_SYNCDCF_Msk                   /*!<Clears the Synchronization Done flag                 */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/

+#define SPDIFRX_DR0_DR_Pos          (0U)

+#define SPDIFRX_DR0_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)         /*!< 0x00FFFFFF */

+#define SPDIFRX_DR0_DR              SPDIFRX_DR0_DR_Msk                         /*!<Data value            */

+#define SPDIFRX_DR0_PE_Pos          (24U)

+#define SPDIFRX_DR0_PE_Msk          (0x1UL << SPDIFRX_DR0_PE_Pos)              /*!< 0x01000000 */

+#define SPDIFRX_DR0_PE              SPDIFRX_DR0_PE_Msk                         /*!<Parity Error bit      */

+#define SPDIFRX_DR0_V_Pos           (25U)

+#define SPDIFRX_DR0_V_Msk           (0x1UL << SPDIFRX_DR0_V_Pos)               /*!< 0x02000000 */

+#define SPDIFRX_DR0_V               SPDIFRX_DR0_V_Msk                          /*!<Validity bit          */

+#define SPDIFRX_DR0_U_Pos           (26U)

+#define SPDIFRX_DR0_U_Msk           (0x1UL << SPDIFRX_DR0_U_Pos)               /*!< 0x04000000 */

+#define SPDIFRX_DR0_U               SPDIFRX_DR0_U_Msk                          /*!<User bit              */

+#define SPDIFRX_DR0_C_Pos           (27U)

+#define SPDIFRX_DR0_C_Msk           (0x1UL << SPDIFRX_DR0_C_Pos)               /*!< 0x08000000 */

+#define SPDIFRX_DR0_C               SPDIFRX_DR0_C_Msk                          /*!<Channel Status bit    */

+#define SPDIFRX_DR0_PT_Pos          (28U)

+#define SPDIFRX_DR0_PT_Msk          (0x3UL << SPDIFRX_DR0_PT_Pos)              /*!< 0x30000000 */

+#define SPDIFRX_DR0_PT              SPDIFRX_DR0_PT_Msk                         /*!<Preamble Type         */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/

+#define SPDIFRX_DR1_DR_Pos          (8U)

+#define SPDIFRX_DR1_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)         /*!< 0xFFFFFF00 */

+#define SPDIFRX_DR1_DR              SPDIFRX_DR1_DR_Msk                         /*!<Data value            */

+#define SPDIFRX_DR1_PT_Pos          (4U)

+#define SPDIFRX_DR1_PT_Msk          (0x3UL << SPDIFRX_DR1_PT_Pos)              /*!< 0x00000030 */

+#define SPDIFRX_DR1_PT              SPDIFRX_DR1_PT_Msk                         /*!<Preamble Type         */

+#define SPDIFRX_DR1_C_Pos           (3U)

+#define SPDIFRX_DR1_C_Msk           (0x1UL << SPDIFRX_DR1_C_Pos)               /*!< 0x00000008 */

+#define SPDIFRX_DR1_C               SPDIFRX_DR1_C_Msk                          /*!<Channel Status bit    */

+#define SPDIFRX_DR1_U_Pos           (2U)

+#define SPDIFRX_DR1_U_Msk           (0x1UL << SPDIFRX_DR1_U_Pos)               /*!< 0x00000004 */

+#define SPDIFRX_DR1_U               SPDIFRX_DR1_U_Msk                          /*!<User bit              */

+#define SPDIFRX_DR1_V_Pos           (1U)

+#define SPDIFRX_DR1_V_Msk           (0x1UL << SPDIFRX_DR1_V_Pos)               /*!< 0x00000002 */

+#define SPDIFRX_DR1_V               SPDIFRX_DR1_V_Msk                          /*!<Validity bit          */

+#define SPDIFRX_DR1_PE_Pos          (0U)

+#define SPDIFRX_DR1_PE_Msk          (0x1UL << SPDIFRX_DR1_PE_Pos)              /*!< 0x00000001 */

+#define SPDIFRX_DR1_PE              SPDIFRX_DR1_PE_Msk                         /*!<Parity Error bit      */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/

+#define SPDIFRX_DR1_DRNL1_Pos       (16U)

+#define SPDIFRX_DR1_DRNL1_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)        /*!< 0xFFFF0000 */

+#define SPDIFRX_DR1_DRNL1           SPDIFRX_DR1_DRNL1_Msk                      /*!<Data value Channel B      */

+#define SPDIFRX_DR1_DRNL2_Pos       (0U)

+#define SPDIFRX_DR1_DRNL2_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)        /*!< 0x0000FFFF */

+#define SPDIFRX_DR1_DRNL2           SPDIFRX_DR1_DRNL2_Msk                      /*!<Data value Channel A      */

+

+/*******************  Bit definition for SPDIFRX_CSR register   *******************/

+#define SPDIFRX_CSR_USR_Pos         (0U)

+#define SPDIFRX_CSR_USR_Msk         (0xFFFFUL << SPDIFRX_CSR_USR_Pos)          /*!< 0x0000FFFF */

+#define SPDIFRX_CSR_USR             SPDIFRX_CSR_USR_Msk                        /*!<User data information           */

+#define SPDIFRX_CSR_CS_Pos          (16U)

+#define SPDIFRX_CSR_CS_Msk          (0xFFUL << SPDIFRX_CSR_CS_Pos)             /*!< 0x00FF0000 */

+#define SPDIFRX_CSR_CS              SPDIFRX_CSR_CS_Msk                         /*!<Channel A status information    */

+#define SPDIFRX_CSR_SOB_Pos         (24U)

+#define SPDIFRX_CSR_SOB_Msk         (0x1UL << SPDIFRX_CSR_SOB_Pos)             /*!< 0x01000000 */

+#define SPDIFRX_CSR_SOB             SPDIFRX_CSR_SOB_Msk                        /*!<Start Of Block                  */

+

+/*******************  Bit definition for SPDIFRX_DIR register    *******************/

+#define SPDIFRX_DIR_THI_Pos         (0U)

+#define SPDIFRX_DIR_THI_Msk         (0x1FFFUL << SPDIFRX_DIR_THI_Pos)          /*!< 0x00001FFF */

+#define SPDIFRX_DIR_THI             SPDIFRX_DIR_THI_Msk                        /*!<Threshold LOW      */

+#define SPDIFRX_DIR_TLO_Pos         (16U)

+#define SPDIFRX_DIR_TLO_Msk         (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)          /*!< 0x1FFF0000 */

+#define SPDIFRX_DIR_TLO             SPDIFRX_DIR_TLO_Msk                        /*!<Threshold HIGH     */

+

+/*******************  Bit definition for SPDIFRX_VERR register    *******************/

+#define SPDIFRX_VERR_MINREV_Pos     (0U)

+#define SPDIFRX_VERR_MINREV_Msk     (0xFUL << SPDIFRX_VERR_MINREV_Pos)         /*!< 0x0000000F */

+#define SPDIFRX_VERR_MINREV         SPDIFRX_VERR_MINREV_Msk                    /*!<SPDIFRX Minor revision     */

+#define SPDIFRX_VERR_MAJREV_Pos     (4U)

+#define SPDIFRX_VERR_MAJREV_Msk     (0xFUL << SPDIFRX_VERR_MAJREV_Pos)         /*!< 0x000000F0 */

+#define SPDIFRX_VERR_MAJREV         SPDIFRX_VERR_MAJREV_Msk                    /*!<SPDIFRX Major revision     */

+

+/*******************  Bit definition for SPDIFRX_IDR register    *******************/

+#define SPDIFRX_IDR_ID_Pos          (0U)

+#define SPDIFRX_IDR_ID_Msk          (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos)       /*!< 0xFFFFFFFF */

+#define SPDIFRX_IDR_ID              SPDIFRX_IDR_ID_Msk                         /*!<SPDIFRX identifier     */

+

+/*******************  Bit definition for SPDIFRX_SIDR register    *******************/

+#define SPDIFRX_SIDR_SID_Pos        (0U)

+#define SPDIFRX_SIDR_SID_Msk        (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos)     /*!< 0xFFFFFFFF */

+#define SPDIFRX_SIDR_SID            SPDIFRX_SIDR_SID_Msk                       /*!<Size of the memory region allocated to SPDIFRX registers */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          Serial Audio Interface                            */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  SAI VERSION  ********************************/

+#define SAI_VER_V2_1

+

+/********************  Bit definition for SAI_GCR register  *******************/

+#define SAI_GCR_SYNCIN_Pos         (0U)

+#define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000003 */

+#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */

+#define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */

+#define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */

+

+#define SAI_GCR_SYNCOUT_Pos        (4U)

+#define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000030 */

+#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */

+#define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */

+#define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */

+

+/*******************  Bit definition for SAI_xCR1 register  *******************/

+#define SAI_xCR1_MODE_Pos          (0U)

+#define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */

+#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */

+#define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */

+#define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */

+

+#define SAI_xCR1_PRTCFG_Pos        (2U)

+#define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */

+#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */

+#define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */

+#define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */

+

+#define SAI_xCR1_DS_Pos            (5U)

+#define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */

+#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */

+#define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */

+#define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */

+#define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */

+

+#define SAI_xCR1_LSBFIRST_Pos      (8U)

+#define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */

+#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */

+#define SAI_xCR1_CKSTR_Pos         (9U)

+#define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */

+#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */

+

+#define SAI_xCR1_SYNCEN_Pos        (10U)

+#define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */

+#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */

+#define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */

+#define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */

+

+#define SAI_xCR1_MONO_Pos          (12U)

+#define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */

+#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */

+#define SAI_xCR1_OUTDRIV_Pos       (13U)

+#define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */

+#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */

+#define SAI_xCR1_SAIEN_Pos         (16U)

+#define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */

+#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */

+#define SAI_xCR1_DMAEN_Pos         (17U)

+#define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */

+#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */

+#define SAI_xCR1_NODIV_Pos         (19U)

+#define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */

+#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */

+

+#define SAI_xCR1_MCKDIV_Pos        (20U)

+#define SAI_xCR1_MCKDIV_Msk        (0x3FUL << SAI_xCR1_MCKDIV_Pos)             /*!< 0x03F00000 */

+#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[5:0] (Master ClocK Divider)  */

+#define SAI_xCR1_MCKDIV_0          (0x01UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00100000 */

+#define SAI_xCR1_MCKDIV_1          (0x02UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00200000 */

+#define SAI_xCR1_MCKDIV_2          (0x04UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00400000 */

+#define SAI_xCR1_MCKDIV_3          (0x08UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00800000 */

+#define SAI_xCR1_MCKDIV_4          (0x10UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x01000000 */

+#define SAI_xCR1_MCKDIV_5          (0x20UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x02000000 */

+

+#define SAI_xCR1_MCKEN_Pos         (27U)

+#define SAI_xCR1_MCKEN_Msk         (0x1UL << SAI_xCR1_MCKEN_Pos)               /*!< 0x08000000 */

+#define SAI_xCR1_MCKEN             SAI_xCR1_MCKEN_Msk                          /*!<Master ClocK enable */

+

+#define SAI_xCR1_OSR_Pos           (26U)

+#define SAI_xCR1_OSR_Msk           (0x1UL << SAI_xCR1_OSR_Pos)                 /*!< 0x04000000 */

+#define SAI_xCR1_OSR               SAI_xCR1_OSR_Msk                            /*!<OverSampling Ratio for master clock  */

+

+/* Legacy define */

+#define  SAI_xCR1_NOMCK               SAI_xCR1_NODIV

+

+/*******************  Bit definition for SAI_xCR2 register  *******************/

+#define SAI_xCR2_FTH_Pos           (0U)

+#define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */

+#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */

+#define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */

+#define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */

+#define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */

+

+#define SAI_xCR2_FFLUSH_Pos        (3U)

+#define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */

+#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */

+#define SAI_xCR2_TRIS_Pos          (4U)

+#define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */

+#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */

+#define SAI_xCR2_MUTE_Pos          (5U)

+#define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */

+#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */

+#define SAI_xCR2_MUTEVAL_Pos       (6U)

+#define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */

+#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */

+

+#define SAI_xCR2_MUTECNT_Pos       (7U)

+#define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */

+#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */

+#define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */

+#define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */

+#define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */

+#define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */

+#define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */

+#define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */

+

+#define SAI_xCR2_CPL_Pos           (13U)

+#define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */

+#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */

+

+#define SAI_xCR2_COMP_Pos          (14U)

+#define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */

+#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */

+#define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */

+#define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */

+

+/******************  Bit definition for SAI_xFRCR register  *******************/

+#define SAI_xFRCR_FRL_Pos          (0U)

+#define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */

+#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](FRame Length)  */

+#define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */

+#define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */

+#define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */

+#define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */

+#define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */

+#define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */

+#define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */

+#define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */

+

+#define SAI_xFRCR_FSALL_Pos        (8U)

+#define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */

+#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FSALL[6:0] (Frame Synchronization Active Level Length)  */

+#define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */

+#define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */

+#define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */

+#define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */

+#define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */

+#define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */

+#define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */

+

+#define SAI_xFRCR_FSDEF_Pos        (16U)

+#define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */

+#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!<Frame Synchronization Definition  */

+#define SAI_xFRCR_FSPOL_Pos        (17U)

+#define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */

+#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */

+#define SAI_xFRCR_FSOFF_Pos        (18U)

+#define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */

+#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */

+

+/* Legacy define */

+#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL

+

+/******************  Bit definition for SAI_xSLOTR register  *******************/

+#define SAI_xSLOTR_FBOFF_Pos       (0U)

+#define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */

+#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FBOFF[4:0](First Bit Offset)  */

+#define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */

+#define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */

+#define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */

+#define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */

+#define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */

+

+#define SAI_xSLOTR_SLOTSZ_Pos      (6U)

+#define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */

+#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */

+#define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */

+#define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */

+

+#define SAI_xSLOTR_NBSLOT_Pos      (8U)

+#define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */

+#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */

+#define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */

+#define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */

+#define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */

+#define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */

+

+#define SAI_xSLOTR_SLOTEN_Pos      (16U)

+#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */

+#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */

+

+/*******************  Bit definition for SAI_xIMR register  *******************/

+#define SAI_xIMR_OVRUDRIE_Pos      (0U)

+#define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */

+#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */

+#define SAI_xIMR_MUTEDETIE_Pos     (1U)

+#define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */

+#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */

+#define SAI_xIMR_WCKCFGIE_Pos      (2U)

+#define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */

+#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */

+#define SAI_xIMR_FREQIE_Pos        (3U)

+#define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */

+#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */

+#define SAI_xIMR_CNRDYIE_Pos       (4U)

+#define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */

+#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */

+#define SAI_xIMR_AFSDETIE_Pos      (5U)

+#define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */

+#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */

+#define SAI_xIMR_LFSDETIE_Pos      (6U)

+#define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */

+#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */

+

+/********************  Bit definition for SAI_xSR register  *******************/

+#define SAI_xSR_OVRUDR_Pos         (0U)

+#define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */

+#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */

+#define SAI_xSR_MUTEDET_Pos        (1U)

+#define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */

+#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */

+#define SAI_xSR_WCKCFG_Pos         (2U)

+#define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */

+#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */

+#define SAI_xSR_FREQ_Pos           (3U)

+#define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */

+#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */

+#define SAI_xSR_CNRDY_Pos          (4U)

+#define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */

+#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */

+#define SAI_xSR_AFSDET_Pos         (5U)

+#define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */

+#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */

+#define SAI_xSR_LFSDET_Pos         (6U)

+#define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */

+#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */

+

+#define SAI_xSR_FLVL_Pos           (16U)

+#define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */

+#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */

+#define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */

+#define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */

+#define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */

+

+/******************  Bit definition for SAI_xCLRFR register  ******************/

+#define SAI_xCLRFR_COVRUDR_Pos     (0U)

+#define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */

+#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */

+#define SAI_xCLRFR_CMUTEDET_Pos    (1U)

+#define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */

+#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */

+#define SAI_xCLRFR_CWCKCFG_Pos     (2U)

+#define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */

+#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */

+#define SAI_xCLRFR_CFREQ_Pos       (3U)

+#define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */

+#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */

+#define SAI_xCLRFR_CCNRDY_Pos      (4U)

+#define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */

+#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */

+#define SAI_xCLRFR_CAFSDET_Pos     (5U)

+#define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */

+#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */

+#define SAI_xCLRFR_CLFSDET_Pos     (6U)

+#define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */

+#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */

+

+/******************  Bit definition for SAI_xDR register  *********************/

+#define SAI_xDR_DATA_Pos           (0U)

+#define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */

+#define SAI_xDR_DATA               SAI_xDR_DATA_Msk

+

+/*******************  Bit definition for SAI_PDMCR register  ******************/

+#define SAI_PDMCR_PDMEN_Pos        (0U)

+#define SAI_PDMCR_PDMEN_Msk        (0x1UL << SAI_PDMCR_PDMEN_Pos)              /*!< 0x00000001 */

+#define SAI_PDMCR_PDMEN            SAI_PDMCR_PDMEN_Msk                         /*!<PDM Enable                                          */

+

+#define SAI_PDMCR_MICNBR_Pos       (4U)

+#define SAI_PDMCR_MICNBR_Msk       (0x3UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000030 */

+#define SAI_PDMCR_MICNBR           SAI_PDMCR_MICNBR_Msk                        /*!<Number of microphones                               */

+#define SAI_PDMCR_MICNBR_0         (0x1UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000010 */

+#define SAI_PDMCR_MICNBR_1         (0x2UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000020 */

+

+#define SAI_PDMCR_CKEN1_Pos        (8U)

+#define SAI_PDMCR_CKEN1_Msk        (0x1UL << SAI_PDMCR_CKEN1_Pos)              /*!< 0x00000100 */

+#define SAI_PDMCR_CKEN1            SAI_PDMCR_CKEN1_Msk                         /*!<Clock enable of bitstream clock number 1            */

+#define SAI_PDMCR_CKEN2_Pos        (9U)

+#define SAI_PDMCR_CKEN2_Msk        (0x1UL << SAI_PDMCR_CKEN2_Pos)              /*!< 0x00000200 */

+#define SAI_PDMCR_CKEN2            SAI_PDMCR_CKEN2_Msk                         /*!<Clock enable of bitstream clock number 2            */

+#define SAI_PDMCR_CKEN3_Pos        (10U)

+#define SAI_PDMCR_CKEN3_Msk        (0x1UL << SAI_PDMCR_CKEN3_Pos)              /*!< 0x00000400 */

+#define SAI_PDMCR_CKEN3            SAI_PDMCR_CKEN3_Msk                         /*!<Clock enable of bitstream clock number 3            */

+#define SAI_PDMCR_CKEN4_Pos        (11U)

+#define SAI_PDMCR_CKEN4_Msk        (0x1UL << SAI_PDMCR_CKEN4_Pos)              /*!< 0x00000800 */

+#define SAI_PDMCR_CKEN4            SAI_PDMCR_CKEN4_Msk                         /*!<Clock enable of bitstream clock number 4            */

+

+/******************  Bit definition for SAI_PDMDLY register  ******************/

+#define SAI_PDMDLY_DLYM1L_Pos      (0U)

+#define SAI_PDMDLY_DLYM1L_Msk      (0x7UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000007 */

+#define SAI_PDMDLY_DLYM1L          SAI_PDMDLY_DLYM1L_Msk                       /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */

+#define SAI_PDMDLY_DLYM1L_0        (0x1UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000001 */

+#define SAI_PDMDLY_DLYM1L_1        (0x2UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000002 */

+#define SAI_PDMDLY_DLYM1L_2        (0x4UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000004 */

+

+#define SAI_PDMDLY_DLYM1R_Pos      (4U)

+#define SAI_PDMDLY_DLYM1R_Msk      (0x7UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000070 */

+#define SAI_PDMDLY_DLYM1R          SAI_PDMDLY_DLYM1R_Msk                       /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */

+#define SAI_PDMDLY_DLYM1R_0        (0x1UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000010 */

+#define SAI_PDMDLY_DLYM1R_1        (0x2UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000020 */

+#define SAI_PDMDLY_DLYM1R_2        (0x4UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000040 */

+

+#define SAI_PDMDLY_DLYM2L_Pos      (8U)

+#define SAI_PDMDLY_DLYM2L_Msk      (0x7UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000700 */

+#define SAI_PDMDLY_DLYM2L          SAI_PDMDLY_DLYM2L_Msk                       /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */

+#define SAI_PDMDLY_DLYM2L_0        (0x1UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000100 */

+#define SAI_PDMDLY_DLYM2L_1        (0x2UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000200 */

+#define SAI_PDMDLY_DLYM2L_2        (0x4UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000400 */

+

+#define SAI_PDMDLY_DLYM2R_Pos      (12U)

+#define SAI_PDMDLY_DLYM2R_Msk      (0x7UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00007000 */

+#define SAI_PDMDLY_DLYM2R          SAI_PDMDLY_DLYM2R_Msk                       /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/

+#define SAI_PDMDLY_DLYM2R_0        (0x1UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00001000 */

+#define SAI_PDMDLY_DLYM2R_1        (0x2UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00002000 */

+#define SAI_PDMDLY_DLYM2R_2        (0x4UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00004000 */

+

+#define SAI_PDMDLY_DLYM3L_Pos      (16U)

+#define SAI_PDMDLY_DLYM3L_Msk      (0x7UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00070000 */

+#define SAI_PDMDLY_DLYM3L          SAI_PDMDLY_DLYM3L_Msk                       /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/

+#define SAI_PDMDLY_DLYM3L_0        (0x1UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00010000 */

+#define SAI_PDMDLY_DLYM3L_1        (0x2UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00020000 */

+#define SAI_PDMDLY_DLYM3L_2        (0x4UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00040000 */

+

+#define SAI_PDMDLY_DLYM3R_Pos      (20U)

+#define SAI_PDMDLY_DLYM3R_Msk      (0x7UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00700000 */

+#define SAI_PDMDLY_DLYM3R          SAI_PDMDLY_DLYM3R_Msk                       /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/

+#define SAI_PDMDLY_DLYM3R_0        (0x1UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00100000 */

+#define SAI_PDMDLY_DLYM3R_1        (0x2UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00200000 */

+#define SAI_PDMDLY_DLYM3R_2        (0x4UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00400000 */

+

+#define SAI_PDMDLY_DLYM4L_Pos      (24U)

+#define SAI_PDMDLY_DLYM4L_Msk      (0x7UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x07000000 */

+#define SAI_PDMDLY_DLYM4L          SAI_PDMDLY_DLYM4L_Msk                       /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/

+#define SAI_PDMDLY_DLYM4L_0        (0x1UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x01000000 */

+#define SAI_PDMDLY_DLYM4L_1        (0x2UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x02000000 */

+#define SAI_PDMDLY_DLYM4L_2        (0x4UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x04000000 */

+

+#define SAI_PDMDLY_DLYM4R_Pos      (28U)

+#define SAI_PDMDLY_DLYM4R_Msk      (0x7UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x70000000 */

+#define SAI_PDMDLY_DLYM4R          SAI_PDMDLY_DLYM4R_Msk                       /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/

+#define SAI_PDMDLY_DLYM4R_0        (0x1UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x10000000 */

+#define SAI_PDMDLY_DLYM4R_1        (0x2UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x20000000 */

+#define SAI_PDMDLY_DLYM4R_2        (0x4UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x40000000 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           SDMMC Interface                                  */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for SDMMC_POWER register  ******************/

+#define SDMMC_POWER_PWRCTRL_Pos          (0U)

+#define SDMMC_POWER_PWRCTRL_Msk          (0x3UL << SDMMC_POWER_PWRCTRL_Pos)    /*!< 0x00000003 */

+#define SDMMC_POWER_PWRCTRL              SDMMC_POWER_PWRCTRL_Msk               /*!<PWRCTRL[1:0] bits (Power supply control bits) */

+#define SDMMC_POWER_PWRCTRL_0            (0x1UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000001 */

+#define SDMMC_POWER_PWRCTRL_1            (0x2UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000002 */

+#define SDMMC_POWER_VSWITCH_Pos          (2U)

+#define SDMMC_POWER_VSWITCH_Msk          (0x1UL << SDMMC_POWER_VSWITCH_Pos)    /*!< 0x00000004 */

+#define SDMMC_POWER_VSWITCH              SDMMC_POWER_VSWITCH_Msk               /*!<Voltage switch sequence start */

+#define SDMMC_POWER_VSWITCHEN_Pos        (3U)

+#define SDMMC_POWER_VSWITCHEN_Msk        (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)  /*!< 0x00000008 */

+#define SDMMC_POWER_VSWITCHEN            SDMMC_POWER_VSWITCHEN_Msk             /*!<Voltage switch procedure enable */

+#define SDMMC_POWER_DIRPOL_Pos           (4U)

+#define SDMMC_POWER_DIRPOL_Msk           (0x1UL << SDMMC_POWER_DIRPOL_Pos)     /*!< 0x00000010 */

+#define SDMMC_POWER_DIRPOL               SDMMC_POWER_DIRPOL_Msk                /*!<Data and Command direction signals polarity selection */

+

+/******************  Bit definition for SDMMC_CLKCR register  ******************/

+#define SDMMC_CLKCR_CLKDIV_Pos           (0U)

+#define SDMMC_CLKCR_CLKDIV_Msk           (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)   /*!< 0x000003FF */

+#define SDMMC_CLKCR_CLKDIV               SDMMC_CLKCR_CLKDIV_Msk                /*!<Clock divide factor             */

+#define SDMMC_CLKCR_PWRSAV_Pos           (12U)

+#define SDMMC_CLKCR_PWRSAV_Msk           (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)     /*!< 0x00001000 */

+#define SDMMC_CLKCR_PWRSAV               SDMMC_CLKCR_PWRSAV_Msk                /*!<Power saving configuration bit  */

+

+#define SDMMC_CLKCR_WIDBUS_Pos           (14U)

+#define SDMMC_CLKCR_WIDBUS_Msk           (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)     /*!< 0x0000C000 */

+#define SDMMC_CLKCR_WIDBUS               SDMMC_CLKCR_WIDBUS_Msk                /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */

+#define SDMMC_CLKCR_WIDBUS_0             (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00004000 */

+#define SDMMC_CLKCR_WIDBUS_1             (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00008000 */

+

+#define SDMMC_CLKCR_NEGEDGE_Pos          (16U)

+#define SDMMC_CLKCR_NEGEDGE_Msk          (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)    /*!< 0x00010000 */

+#define SDMMC_CLKCR_NEGEDGE              SDMMC_CLKCR_NEGEDGE_Msk               /*!<SDMMC_CK dephasing selection bit */

+#define SDMMC_CLKCR_HWFC_EN_Pos          (17U)

+#define SDMMC_CLKCR_HWFC_EN_Msk          (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)    /*!< 0x00020000 */

+#define SDMMC_CLKCR_HWFC_EN              SDMMC_CLKCR_HWFC_EN_Msk               /*!<HW Flow Control enable           */

+#define SDMMC_CLKCR_DDR_Pos              (18U)

+#define SDMMC_CLKCR_DDR_Msk              (0x1UL << SDMMC_CLKCR_DDR_Pos)        /*!< 0x00040000 */

+#define SDMMC_CLKCR_DDR                  SDMMC_CLKCR_DDR_Msk                   /*!<Data rate signaling selection    */

+#define SDMMC_CLKCR_BUSSPEED_Pos         (19U)

+#define SDMMC_CLKCR_BUSSPEED_Msk         (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)   /*!< 0x00080000 */

+#define SDMMC_CLKCR_BUSSPEED             SDMMC_CLKCR_BUSSPEED_Msk              /*!<Bus speed mode selection         */

+#define SDMMC_CLKCR_SELCLKRX_Pos         (20U)

+#define SDMMC_CLKCR_SELCLKRX_Msk         (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)   /*!< 0x00300000 */

+#define SDMMC_CLKCR_SELCLKRX             SDMMC_CLKCR_SELCLKRX_Msk              /*!<SELCLKRX[1:0] bits (Receive clock selection) */

+#define SDMMC_CLKCR_SELCLKRX_0           (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00100000 */

+#define SDMMC_CLKCR_SELCLKRX_1           (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00200000 */

+

+/*******************  Bit definition for SDMMC_ARG register  *******************/

+#define SDMMC_ARG_CMDARG_Pos             (0U)

+#define SDMMC_ARG_CMDARG_Msk             (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_ARG_CMDARG                 SDMMC_ARG_CMDARG_Msk                  /*!<Command argument */

+

+/*******************  Bit definition for SDMMC_CMD register  *******************/

+#define SDMMC_CMD_CMDINDEX_Pos           (0U)

+#define SDMMC_CMD_CMDINDEX_Msk           (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)    /*!< 0x0000003F */

+#define SDMMC_CMD_CMDINDEX               SDMMC_CMD_CMDINDEX_Msk                /*!<Command Index                               */

+#define SDMMC_CMD_CMDTRANS_Pos           (6U)

+#define SDMMC_CMD_CMDTRANS_Msk           (0x1UL << SDMMC_CMD_CMDTRANS_Pos)     /*!< 0x00000040 */

+#define SDMMC_CMD_CMDTRANS               SDMMC_CMD_CMDTRANS_Msk                /*!<CPSM Treats command as a Data Transfer      */

+#define SDMMC_CMD_CMDSTOP_Pos            (7U)

+#define SDMMC_CMD_CMDSTOP_Msk            (0x1UL << SDMMC_CMD_CMDSTOP_Pos)      /*!< 0x00000080 */

+#define SDMMC_CMD_CMDSTOP                SDMMC_CMD_CMDSTOP_Msk                 /*!<CPSM Treats command as a Stop               */

+

+#define SDMMC_CMD_WAITRESP_Pos           (8U)

+#define SDMMC_CMD_WAITRESP_Msk           (0x3UL << SDMMC_CMD_WAITRESP_Pos)     /*!< 0x00000300 */

+#define SDMMC_CMD_WAITRESP               SDMMC_CMD_WAITRESP_Msk                /*!<WAITRESP[1:0] bits (Wait for response bits) */

+#define SDMMC_CMD_WAITRESP_0             (0x1UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000100 */

+#define SDMMC_CMD_WAITRESP_1             (0x2UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000200 */

+

+#define SDMMC_CMD_WAITINT_Pos            (10U)

+#define SDMMC_CMD_WAITINT_Msk            (0x1UL << SDMMC_CMD_WAITINT_Pos)      /*!< 0x00000400 */

+#define SDMMC_CMD_WAITINT                SDMMC_CMD_WAITINT_Msk                 /*!<CPSM Waits for Interrupt Request                               */

+#define SDMMC_CMD_WAITPEND_Pos           (11U)

+#define SDMMC_CMD_WAITPEND_Msk           (0x1UL << SDMMC_CMD_WAITPEND_Pos)     /*!< 0x00000800 */

+#define SDMMC_CMD_WAITPEND               SDMMC_CMD_WAITPEND_Msk                /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */

+#define SDMMC_CMD_CPSMEN_Pos             (12U)

+#define SDMMC_CMD_CPSMEN_Msk             (0x1UL << SDMMC_CMD_CPSMEN_Pos)       /*!< 0x00001000 */

+#define SDMMC_CMD_CPSMEN                 SDMMC_CMD_CPSMEN_Msk                  /*!<Command path state machine (CPSM) Enable bit                   */

+#define SDMMC_CMD_DTHOLD_Pos             (13U)

+#define SDMMC_CMD_DTHOLD_Msk             (0x1UL << SDMMC_CMD_DTHOLD_Pos)       /*!< 0x00002000 */

+#define SDMMC_CMD_DTHOLD                 SDMMC_CMD_DTHOLD_Msk                  /*!<Hold new data block transmission and reception in the DPSM     */

+#define SDMMC_CMD_BOOTMODE_Pos           (14U)

+#define SDMMC_CMD_BOOTMODE_Msk           (0x1UL << SDMMC_CMD_BOOTMODE_Pos)     /*!< 0x00004000 */

+#define SDMMC_CMD_BOOTMODE               SDMMC_CMD_BOOTMODE_Msk                /*!<Boot mode                                                      */

+#define SDMMC_CMD_BOOTEN_Pos             (15U)

+#define SDMMC_CMD_BOOTEN_Msk             (0x1UL << SDMMC_CMD_BOOTEN_Pos)       /*!< 0x00008000 */

+#define SDMMC_CMD_BOOTEN                 SDMMC_CMD_BOOTEN_Msk                  /*!<Enable Boot mode procedure                                     */

+#define SDMMC_CMD_CMDSUSPEND_Pos         (16U)

+#define SDMMC_CMD_CMDSUSPEND_Msk         (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)   /*!< 0x00010000 */

+#define SDMMC_CMD_CMDSUSPEND             SDMMC_CMD_CMDSUSPEND_Msk              /*!<CPSM Treats command as a Suspend or Resume command             */

+

+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/

+#define SDMMC_RESPCMD_RESPCMD_Pos        (0U)

+#define SDMMC_RESPCMD_RESPCMD_Msk        (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */

+#define SDMMC_RESPCMD_RESPCMD            SDMMC_RESPCMD_RESPCMD_Msk             /*!<Response command index */

+

+/******************  Bit definition for SDMMC_RESP0 register  ******************/

+#define SDMMC_RESP0_CARDSTATUS0_Pos      (0U)

+#define SDMMC_RESP0_CARDSTATUS0_Msk      (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP0_CARDSTATUS0          SDMMC_RESP0_CARDSTATUS0_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP1 register  ******************/

+#define SDMMC_RESP1_CARDSTATUS1_Pos      (0U)

+#define SDMMC_RESP1_CARDSTATUS1_Msk      (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP1_CARDSTATUS1          SDMMC_RESP1_CARDSTATUS1_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP2 register  ******************/

+#define SDMMC_RESP2_CARDSTATUS2_Pos      (0U)

+#define SDMMC_RESP2_CARDSTATUS2_Msk      (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP2_CARDSTATUS2          SDMMC_RESP2_CARDSTATUS2_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP3 register  ******************/

+#define SDMMC_RESP3_CARDSTATUS3_Pos      (0U)

+#define SDMMC_RESP3_CARDSTATUS3_Msk      (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP3_CARDSTATUS3          SDMMC_RESP3_CARDSTATUS3_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP4 register  ******************/

+#define SDMMC_RESP4_CARDSTATUS4_Pos      (0U)

+#define SDMMC_RESP4_CARDSTATUS4_Msk      (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP4_CARDSTATUS4          SDMMC_RESP4_CARDSTATUS4_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_DTIMER register  *****************/

+#define SDMMC_DTIMER_DATATIME_Pos        (0U)

+#define SDMMC_DTIMER_DATATIME_Msk        (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_DTIMER_DATATIME            SDMMC_DTIMER_DATATIME_Msk             /*!<Data timeout period. */

+

+/******************  Bit definition for SDMMC_DLEN register  *******************/

+#define SDMMC_DLEN_DATALENGTH_Pos        (0U)

+#define SDMMC_DLEN_DATALENGTH_Msk        (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_DLEN_DATALENGTH            SDMMC_DLEN_DATALENGTH_Msk             /*!<Data length value    */

+

+/******************  Bit definition for SDMMC_DCTRL register  ******************/

+#define SDMMC_DCTRL_DTEN_Pos             (0U)

+#define SDMMC_DCTRL_DTEN_Msk             (0x1UL << SDMMC_DCTRL_DTEN_Pos)       /*!< 0x00000001 */

+#define SDMMC_DCTRL_DTEN                 SDMMC_DCTRL_DTEN_Msk                  /*!<Data transfer enabled bit                */

+#define SDMMC_DCTRL_DTDIR_Pos            (1U)

+#define SDMMC_DCTRL_DTDIR_Msk            (0x1UL << SDMMC_DCTRL_DTDIR_Pos)      /*!< 0x00000002 */

+#define SDMMC_DCTRL_DTDIR                SDMMC_DCTRL_DTDIR_Msk                 /*!<Data transfer direction selection        */

+#define SDMMC_DCTRL_DTMODE_Pos           (2U)

+#define SDMMC_DCTRL_DTMODE_Msk           (0x3UL << SDMMC_DCTRL_DTMODE_Pos)     /*!< 0x0000000C */

+#define SDMMC_DCTRL_DTMODE               SDMMC_DCTRL_DTMODE_Msk                /*!<DTMODE[1:0] Data transfer mode selection */

+#define SDMMC_DCTRL_DTMODE_0             (0x1UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000004 */

+#define SDMMC_DCTRL_DTMODE_1             (0x2UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000008 */

+

+#define SDMMC_DCTRL_DBLOCKSIZE_Pos       (4U)

+#define SDMMC_DCTRL_DBLOCKSIZE_Msk       (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */

+#define SDMMC_DCTRL_DBLOCKSIZE           SDMMC_DCTRL_DBLOCKSIZE_Msk            /*!<DBLOCKSIZE[3:0] bits (Data block size) */

+#define SDMMC_DCTRL_DBLOCKSIZE_0         (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000010 */

+#define SDMMC_DCTRL_DBLOCKSIZE_1         (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000020 */

+#define SDMMC_DCTRL_DBLOCKSIZE_2         (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000040 */

+#define SDMMC_DCTRL_DBLOCKSIZE_3         (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000080 */

+

+#define SDMMC_DCTRL_RWSTART_Pos          (8U)

+#define SDMMC_DCTRL_RWSTART_Msk          (0x1UL << SDMMC_DCTRL_RWSTART_Pos)    /*!< 0x00000100 */

+#define SDMMC_DCTRL_RWSTART              SDMMC_DCTRL_RWSTART_Msk               /*!<Read wait start                                 */

+#define SDMMC_DCTRL_RWSTOP_Pos           (9U)

+#define SDMMC_DCTRL_RWSTOP_Msk           (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)     /*!< 0x00000200 */

+#define SDMMC_DCTRL_RWSTOP               SDMMC_DCTRL_RWSTOP_Msk                /*!<Read wait stop                                  */

+#define SDMMC_DCTRL_RWMOD_Pos            (10U)

+#define SDMMC_DCTRL_RWMOD_Msk            (0x1UL << SDMMC_DCTRL_RWMOD_Pos)      /*!< 0x00000400 */

+#define SDMMC_DCTRL_RWMOD                SDMMC_DCTRL_RWMOD_Msk                 /*!<Read wait mode                                  */

+#define SDMMC_DCTRL_SDIOEN_Pos           (11U)

+#define SDMMC_DCTRL_SDIOEN_Msk           (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)     /*!< 0x00000800 */

+#define SDMMC_DCTRL_SDIOEN               SDMMC_DCTRL_SDIOEN_Msk                /*!<SD I/O enable functions                         */

+#define SDMMC_DCTRL_BOOTACKEN_Pos        (12U)

+#define SDMMC_DCTRL_BOOTACKEN_Msk        (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)  /*!< 0x00001000 */

+#define SDMMC_DCTRL_BOOTACKEN            SDMMC_DCTRL_BOOTACKEN_Msk             /*!<Enable the reception of the Boot Acknowledgment */

+#define SDMMC_DCTRL_FIFORST_Pos          (13U)

+#define SDMMC_DCTRL_FIFORST_Msk          (0x1UL << SDMMC_DCTRL_FIFORST_Pos)    /*!< 0x00002000 */

+#define SDMMC_DCTRL_FIFORST              SDMMC_DCTRL_FIFORST_Msk               /*!<FIFO reset                                      */

+

+/******************  Bit definition for SDMMC_DCOUNT register  *****************/

+#define SDMMC_DCOUNT_DATACOUNT_Pos       (0U)

+#define SDMMC_DCOUNT_DATACOUNT_Msk       (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_DCOUNT_DATACOUNT           SDMMC_DCOUNT_DATACOUNT_Msk            /*!<Data count value */

+

+/******************  Bit definition for SDMMC_STA register  ********************/

+#define SDMMC_STA_CCRCFAIL_Pos           (0U)

+#define SDMMC_STA_CCRCFAIL_Msk           (0x1UL << SDMMC_STA_CCRCFAIL_Pos)     /*!< 0x00000001 */

+#define SDMMC_STA_CCRCFAIL               SDMMC_STA_CCRCFAIL_Msk                /*!<Command response received (CRC check failed)  */

+#define SDMMC_STA_DCRCFAIL_Pos           (1U)

+#define SDMMC_STA_DCRCFAIL_Msk           (0x1UL << SDMMC_STA_DCRCFAIL_Pos)     /*!< 0x00000002 */

+#define SDMMC_STA_DCRCFAIL               SDMMC_STA_DCRCFAIL_Msk                /*!<Data block sent/received (CRC check failed)   */

+#define SDMMC_STA_CTIMEOUT_Pos           (2U)

+#define SDMMC_STA_CTIMEOUT_Msk           (0x1UL << SDMMC_STA_CTIMEOUT_Pos)     /*!< 0x00000004 */

+#define SDMMC_STA_CTIMEOUT               SDMMC_STA_CTIMEOUT_Msk                /*!<Command response timeout                      */

+#define SDMMC_STA_DTIMEOUT_Pos           (3U)

+#define SDMMC_STA_DTIMEOUT_Msk           (0x1UL << SDMMC_STA_DTIMEOUT_Pos)     /*!< 0x00000008 */

+#define SDMMC_STA_DTIMEOUT               SDMMC_STA_DTIMEOUT_Msk                /*!<Data timeout                                  */

+#define SDMMC_STA_TXUNDERR_Pos           (4U)

+#define SDMMC_STA_TXUNDERR_Msk           (0x1UL << SDMMC_STA_TXUNDERR_Pos)     /*!< 0x00000010 */

+#define SDMMC_STA_TXUNDERR               SDMMC_STA_TXUNDERR_Msk                /*!<Transmit FIFO underrun error                  */

+#define SDMMC_STA_RXOVERR_Pos            (5U)

+#define SDMMC_STA_RXOVERR_Msk            (0x1UL << SDMMC_STA_RXOVERR_Pos)      /*!< 0x00000020 */

+#define SDMMC_STA_RXOVERR                SDMMC_STA_RXOVERR_Msk                 /*!<Received FIFO overrun error                   */

+#define SDMMC_STA_CMDREND_Pos            (6U)

+#define SDMMC_STA_CMDREND_Msk            (0x1UL << SDMMC_STA_CMDREND_Pos)      /*!< 0x00000040 */

+#define SDMMC_STA_CMDREND                SDMMC_STA_CMDREND_Msk                 /*!<Command response received (CRC check passed)  */

+#define SDMMC_STA_CMDSENT_Pos            (7U)

+#define SDMMC_STA_CMDSENT_Msk            (0x1UL << SDMMC_STA_CMDSENT_Pos)      /*!< 0x00000080 */

+#define SDMMC_STA_CMDSENT                SDMMC_STA_CMDSENT_Msk                 /*!<Command sent (no response required)           */

+#define SDMMC_STA_DATAEND_Pos            (8U)

+#define SDMMC_STA_DATAEND_Msk            (0x1UL << SDMMC_STA_DATAEND_Pos)      /*!< 0x00000100 */

+#define SDMMC_STA_DATAEND                SDMMC_STA_DATAEND_Msk                 /*!<Data end (data counter, SDIDCOUNT, is zero)   */

+#define SDMMC_STA_DHOLD_Pos              (9U)

+#define SDMMC_STA_DHOLD_Msk              (0x1UL << SDMMC_STA_DHOLD_Pos)        /*!< 0x00000200 */

+#define SDMMC_STA_DHOLD                  SDMMC_STA_DHOLD_Msk                   /*!<Data transfer Hold                                                      */

+#define SDMMC_STA_DBCKEND_Pos            (10U)

+#define SDMMC_STA_DBCKEND_Msk            (0x1UL << SDMMC_STA_DBCKEND_Pos)      /*!< 0x00000400 */

+#define SDMMC_STA_DBCKEND                SDMMC_STA_DBCKEND_Msk                 /*!<Data block sent/received (CRC check passed)   */

+#define SDMMC_STA_DABORT_Pos             (11U)

+#define SDMMC_STA_DABORT_Msk             (0x1UL << SDMMC_STA_DABORT_Pos)       /*!< 0x00000800 */

+#define SDMMC_STA_DABORT                 SDMMC_STA_DABORT_Msk                  /*!<Data transfer aborted by CMD12                                          */

+#define SDMMC_STA_DPSMACT_Pos            (12U)

+#define SDMMC_STA_DPSMACT_Msk            (0x1UL << SDMMC_STA_DPSMACT_Pos)      /*!< 0x00001000 */

+#define SDMMC_STA_DPSMACT                SDMMC_STA_DPSMACT_Msk                 /*!<Data path state machine active                                       */

+#define SDMMC_STA_CPSMACT_Pos            (13U)

+#define SDMMC_STA_CPSMACT_Msk            (0x1UL << SDMMC_STA_CPSMACT_Pos)      /*!< 0x00002000 */

+#define SDMMC_STA_CPSMACT                SDMMC_STA_CPSMACT_Msk                 /*!<Command path state machine active                                          */

+#define SDMMC_STA_TXFIFOHE_Pos           (14U)

+#define SDMMC_STA_TXFIFOHE_Msk           (0x1UL << SDMMC_STA_TXFIFOHE_Pos)     /*!< 0x00004000 */

+#define SDMMC_STA_TXFIFOHE               SDMMC_STA_TXFIFOHE_Msk                /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */

+#define SDMMC_STA_RXFIFOHF_Pos           (15U)

+#define SDMMC_STA_RXFIFOHF_Msk           (0x1UL << SDMMC_STA_RXFIFOHF_Pos)     /*!< 0x00008000 */

+#define SDMMC_STA_RXFIFOHF               SDMMC_STA_RXFIFOHF_Msk                /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */

+#define SDMMC_STA_TXFIFOF_Pos            (16U)

+#define SDMMC_STA_TXFIFOF_Msk            (0x1UL << SDMMC_STA_TXFIFOF_Pos)      /*!< 0x00010000 */

+#define SDMMC_STA_TXFIFOF                SDMMC_STA_TXFIFOF_Msk                 /*!<Transmit FIFO full                            */

+#define SDMMC_STA_RXFIFOF_Pos            (17U)

+#define SDMMC_STA_RXFIFOF_Msk            (0x1UL << SDMMC_STA_RXFIFOF_Pos)      /*!< 0x00020000 */

+#define SDMMC_STA_RXFIFOF                SDMMC_STA_RXFIFOF_Msk                 /*!<Receive FIFO full                             */

+#define SDMMC_STA_TXFIFOE_Pos            (18U)

+#define SDMMC_STA_TXFIFOE_Msk            (0x1UL << SDMMC_STA_TXFIFOE_Pos)      /*!< 0x00040000 */

+#define SDMMC_STA_TXFIFOE                SDMMC_STA_TXFIFOE_Msk                 /*!<Transmit FIFO empty                           */

+#define SDMMC_STA_RXFIFOE_Pos            (19U)

+#define SDMMC_STA_RXFIFOE_Msk            (0x1UL << SDMMC_STA_RXFIFOE_Pos)      /*!< 0x00080000 */

+#define SDMMC_STA_RXFIFOE                SDMMC_STA_RXFIFOE_Msk                 /*!<Receive FIFO empty                            */

+#define SDMMC_STA_BUSYD0_Pos             (20U)

+#define SDMMC_STA_BUSYD0_Msk             (0x1UL << SDMMC_STA_BUSYD0_Pos)       /*!< 0x00100000 */

+#define SDMMC_STA_BUSYD0                 SDMMC_STA_BUSYD0_Msk                  /*!<Inverted value of SDMMC_D0 line (Busy)                                  */

+#define SDMMC_STA_BUSYD0END_Pos          (21U)

+#define SDMMC_STA_BUSYD0END_Msk          (0x1UL << SDMMC_STA_BUSYD0END_Pos)    /*!< 0x00200000 */

+#define SDMMC_STA_BUSYD0END              SDMMC_STA_BUSYD0END_Msk               /*!<End of SDMMC_D0 Busy following a CMD response detected                  */

+#define SDMMC_STA_SDIOIT_Pos             (22U)

+#define SDMMC_STA_SDIOIT_Msk             (0x1UL << SDMMC_STA_SDIOIT_Pos)       /*!< 0x00400000 */

+#define SDMMC_STA_SDIOIT                 SDMMC_STA_SDIOIT_Msk                  /*!<SDIO interrupt received                                                 */

+#define SDMMC_STA_ACKFAIL_Pos            (23U)

+#define SDMMC_STA_ACKFAIL_Msk            (0x1UL << SDMMC_STA_ACKFAIL_Pos)      /*!< 0x00800000 */

+#define SDMMC_STA_ACKFAIL                SDMMC_STA_ACKFAIL_Msk                 /*!<Boot Acknowledgment received (BootAck check fail)                       */

+#define SDMMC_STA_ACKTIMEOUT_Pos         (24U)

+#define SDMMC_STA_ACKTIMEOUT_Msk         (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)   /*!< 0x01000000 */

+#define SDMMC_STA_ACKTIMEOUT             SDMMC_STA_ACKTIMEOUT_Msk              /*!<Boot Acknowledgment timeout                                             */

+#define SDMMC_STA_VSWEND_Pos             (25U)

+#define SDMMC_STA_VSWEND_Msk             (0x1UL << SDMMC_STA_VSWEND_Pos)       /*!< 0x02000000 */

+#define SDMMC_STA_VSWEND                 SDMMC_STA_VSWEND_Msk                  /*!<Voltage switch critical timing section completion                       */

+#define SDMMC_STA_CKSTOP_Pos             (26U)

+#define SDMMC_STA_CKSTOP_Msk             (0x1UL << SDMMC_STA_CKSTOP_Pos)       /*!< 0x04000000 */

+#define SDMMC_STA_CKSTOP                 SDMMC_STA_CKSTOP_Msk                  /*!<SDMMC_CK stopped in Voltage switch procedure                            */

+#define SDMMC_STA_IDMATE_Pos             (27U)

+#define SDMMC_STA_IDMATE_Msk             (0x1UL << SDMMC_STA_IDMATE_Pos)       /*!< 0x08000000 */

+#define SDMMC_STA_IDMATE                 SDMMC_STA_IDMATE_Msk                  /*!<IDMA transfer error                                                     */

+#define SDMMC_STA_IDMABTC_Pos            (28U)

+#define SDMMC_STA_IDMABTC_Msk            (0x1UL << SDMMC_STA_IDMABTC_Pos)      /*!< 0x10000000 */

+#define SDMMC_STA_IDMABTC                SDMMC_STA_IDMABTC_Msk                 /*!<IDMA buffer transfer complete                                           */

+

+/*******************  Bit definition for SDMMC_ICR register  *******************/

+#define SDMMC_ICR_CCRCFAILC_Pos          (0U)

+#define SDMMC_ICR_CCRCFAILC_Msk          (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)    /*!< 0x00000001 */

+#define SDMMC_ICR_CCRCFAILC              SDMMC_ICR_CCRCFAILC_Msk               /*!<CCRCFAIL flag clear bit */

+#define SDMMC_ICR_DCRCFAILC_Pos          (1U)

+#define SDMMC_ICR_DCRCFAILC_Msk          (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)    /*!< 0x00000002 */

+#define SDMMC_ICR_DCRCFAILC              SDMMC_ICR_DCRCFAILC_Msk               /*!<DCRCFAIL flag clear bit */

+#define SDMMC_ICR_CTIMEOUTC_Pos          (2U)

+#define SDMMC_ICR_CTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)    /*!< 0x00000004 */

+#define SDMMC_ICR_CTIMEOUTC              SDMMC_ICR_CTIMEOUTC_Msk               /*!<CTIMEOUT flag clear bit */

+#define SDMMC_ICR_DTIMEOUTC_Pos          (3U)

+#define SDMMC_ICR_DTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)    /*!< 0x00000008 */

+#define SDMMC_ICR_DTIMEOUTC              SDMMC_ICR_DTIMEOUTC_Msk               /*!<DTIMEOUT flag clear bit */

+#define SDMMC_ICR_TXUNDERRC_Pos          (4U)

+#define SDMMC_ICR_TXUNDERRC_Msk          (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)    /*!< 0x00000010 */

+#define SDMMC_ICR_TXUNDERRC              SDMMC_ICR_TXUNDERRC_Msk               /*!<TXUNDERR flag clear bit */

+#define SDMMC_ICR_RXOVERRC_Pos           (5U)

+#define SDMMC_ICR_RXOVERRC_Msk           (0x1UL << SDMMC_ICR_RXOVERRC_Pos)     /*!< 0x00000020 */

+#define SDMMC_ICR_RXOVERRC               SDMMC_ICR_RXOVERRC_Msk                /*!<RXOVERR flag clear bit  */

+#define SDMMC_ICR_CMDRENDC_Pos           (6U)

+#define SDMMC_ICR_CMDRENDC_Msk           (0x1UL << SDMMC_ICR_CMDRENDC_Pos)     /*!< 0x00000040 */

+#define SDMMC_ICR_CMDRENDC               SDMMC_ICR_CMDRENDC_Msk                /*!<CMDREND flag clear bit  */

+#define SDMMC_ICR_CMDSENTC_Pos           (7U)

+#define SDMMC_ICR_CMDSENTC_Msk           (0x1UL << SDMMC_ICR_CMDSENTC_Pos)     /*!< 0x00000080 */

+#define SDMMC_ICR_CMDSENTC               SDMMC_ICR_CMDSENTC_Msk                /*!<CMDSENT flag clear bit  */

+#define SDMMC_ICR_DATAENDC_Pos           (8U)

+#define SDMMC_ICR_DATAENDC_Msk           (0x1UL << SDMMC_ICR_DATAENDC_Pos)     /*!< 0x00000100 */

+#define SDMMC_ICR_DATAENDC               SDMMC_ICR_DATAENDC_Msk                /*!<DATAEND flag clear bit  */

+#define SDMMC_ICR_DHOLDC_Pos             (9U)

+#define SDMMC_ICR_DHOLDC_Msk             (0x1UL << SDMMC_ICR_DHOLDC_Pos)       /*!< 0x00000200 */

+#define SDMMC_ICR_DHOLDC                 SDMMC_ICR_DHOLDC_Msk                  /*!<DHOLD flag clear bit       */

+#define SDMMC_ICR_DBCKENDC_Pos           (10U)

+#define SDMMC_ICR_DBCKENDC_Msk           (0x1UL << SDMMC_ICR_DBCKENDC_Pos)     /*!< 0x00000400 */

+#define SDMMC_ICR_DBCKENDC               SDMMC_ICR_DBCKENDC_Msk                /*!<DBCKEND flag clear bit  */

+#define SDMMC_ICR_DABORTC_Pos            (11U)

+#define SDMMC_ICR_DABORTC_Msk            (0x1UL << SDMMC_ICR_DABORTC_Pos)      /*!< 0x00000800 */

+#define SDMMC_ICR_DABORTC                SDMMC_ICR_DABORTC_Msk                 /*!<DABORTC flag clear bit     */

+#define SDMMC_ICR_BUSYD0ENDC_Pos         (21U)

+#define SDMMC_ICR_BUSYD0ENDC_Msk         (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)   /*!< 0x00200000 */

+#define SDMMC_ICR_BUSYD0ENDC             SDMMC_ICR_BUSYD0ENDC_Msk              /*!<BUSYD0ENDC flag clear bit  */

+#define SDMMC_ICR_SDIOITC_Pos            (22U)

+#define SDMMC_ICR_SDIOITC_Msk            (0x1UL << SDMMC_ICR_SDIOITC_Pos)      /*!< 0x00400000 */

+#define SDMMC_ICR_SDIOITC                SDMMC_ICR_SDIOITC_Msk                 /*!<SDIOIT flag clear bit      */

+#define SDMMC_ICR_ACKFAILC_Pos           (23U)

+#define SDMMC_ICR_ACKFAILC_Msk           (0x1UL << SDMMC_ICR_ACKFAILC_Pos)     /*!< 0x00800000 */

+#define SDMMC_ICR_ACKFAILC               SDMMC_ICR_ACKFAILC_Msk                /*!<ACKFAILC flag clear bit    */

+#define SDMMC_ICR_ACKTIMEOUTC_Pos        (24U)

+#define SDMMC_ICR_ACKTIMEOUTC_Msk        (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)  /*!< 0x01000000 */

+#define SDMMC_ICR_ACKTIMEOUTC            SDMMC_ICR_ACKTIMEOUTC_Msk             /*!<ACKTIMEOUTC flag clear bit */

+#define SDMMC_ICR_VSWENDC_Pos            (25U)

+#define SDMMC_ICR_VSWENDC_Msk            (0x1UL << SDMMC_ICR_VSWENDC_Pos)      /*!< 0x02000000 */

+#define SDMMC_ICR_VSWENDC                SDMMC_ICR_VSWENDC_Msk                 /*!<VSWENDC flag clear bit     */

+#define SDMMC_ICR_CKSTOPC_Pos            (26U)

+#define SDMMC_ICR_CKSTOPC_Msk            (0x1UL << SDMMC_ICR_CKSTOPC_Pos)      /*!< 0x04000000 */

+#define SDMMC_ICR_CKSTOPC                SDMMC_ICR_CKSTOPC_Msk                 /*!<CKSTOPC flag clear bit     */

+#define SDMMC_ICR_IDMATEC_Pos            (27U)

+#define SDMMC_ICR_IDMATEC_Msk            (0x1UL << SDMMC_ICR_IDMATEC_Pos)      /*!< 0x08000000 */

+#define SDMMC_ICR_IDMATEC                SDMMC_ICR_IDMATEC_Msk                 /*!<IDMATEC flag clear bit     */

+#define SDMMC_ICR_IDMABTCC_Pos           (28U)

+#define SDMMC_ICR_IDMABTCC_Msk           (0x1UL << SDMMC_ICR_IDMABTCC_Pos)     /*!< 0x10000000 */

+#define SDMMC_ICR_IDMABTCC               SDMMC_ICR_IDMABTCC_Msk                /*!<IDMABTCC flag clear bit    */

+

+/******************  Bit definition for SDMMC_MASK register  *******************/

+#define SDMMC_MASK_CCRCFAILIE_Pos        (0U)

+#define SDMMC_MASK_CCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)  /*!< 0x00000001 */

+#define SDMMC_MASK_CCRCFAILIE            SDMMC_MASK_CCRCFAILIE_Msk             /*!<Command CRC Fail Interrupt Enable          */

+#define SDMMC_MASK_DCRCFAILIE_Pos        (1U)

+#define SDMMC_MASK_DCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)  /*!< 0x00000002 */

+#define SDMMC_MASK_DCRCFAILIE            SDMMC_MASK_DCRCFAILIE_Msk             /*!<Data CRC Fail Interrupt Enable             */

+#define SDMMC_MASK_CTIMEOUTIE_Pos        (2U)

+#define SDMMC_MASK_CTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)  /*!< 0x00000004 */

+#define SDMMC_MASK_CTIMEOUTIE            SDMMC_MASK_CTIMEOUTIE_Msk             /*!<Command TimeOut Interrupt Enable           */

+#define SDMMC_MASK_DTIMEOUTIE_Pos        (3U)

+#define SDMMC_MASK_DTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)  /*!< 0x00000008 */

+#define SDMMC_MASK_DTIMEOUTIE            SDMMC_MASK_DTIMEOUTIE_Msk             /*!<Data TimeOut Interrupt Enable              */

+#define SDMMC_MASK_TXUNDERRIE_Pos        (4U)

+#define SDMMC_MASK_TXUNDERRIE_Msk        (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)  /*!< 0x00000010 */

+#define SDMMC_MASK_TXUNDERRIE            SDMMC_MASK_TXUNDERRIE_Msk             /*!<Tx FIFO UnderRun Error Interrupt Enable    */

+#define SDMMC_MASK_RXOVERRIE_Pos         (5U)

+#define SDMMC_MASK_RXOVERRIE_Msk         (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)   /*!< 0x00000020 */

+#define SDMMC_MASK_RXOVERRIE             SDMMC_MASK_RXOVERRIE_Msk              /*!<Rx FIFO OverRun Error Interrupt Enable     */

+#define SDMMC_MASK_CMDRENDIE_Pos         (6U)

+#define SDMMC_MASK_CMDRENDIE_Msk         (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)   /*!< 0x00000040 */

+#define SDMMC_MASK_CMDRENDIE             SDMMC_MASK_CMDRENDIE_Msk              /*!<Command Response Received Interrupt Enable */

+#define SDMMC_MASK_CMDSENTIE_Pos         (7U)

+#define SDMMC_MASK_CMDSENTIE_Msk         (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)   /*!< 0x00000080 */

+#define SDMMC_MASK_CMDSENTIE             SDMMC_MASK_CMDSENTIE_Msk              /*!<Command Sent Interrupt Enable              */

+#define SDMMC_MASK_DATAENDIE_Pos         (8U)

+#define SDMMC_MASK_DATAENDIE_Msk         (0x1UL << SDMMC_MASK_DATAENDIE_Pos)   /*!< 0x00000100 */

+#define SDMMC_MASK_DATAENDIE             SDMMC_MASK_DATAENDIE_Msk              /*!<Data End Interrupt Enable                  */

+#define SDMMC_MASK_DHOLDIE_Pos           (9U)

+#define SDMMC_MASK_DHOLDIE_Msk           (0x1UL << SDMMC_MASK_DHOLDIE_Pos)     /*!< 0x00000200 */

+#define SDMMC_MASK_DHOLDIE               SDMMC_MASK_DHOLDIE_Msk                /*!<Data Hold Interrupt Enable                 */

+#define SDMMC_MASK_DBCKENDIE_Pos         (10U)

+#define SDMMC_MASK_DBCKENDIE_Msk         (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)   /*!< 0x00000400 */

+#define SDMMC_MASK_DBCKENDIE             SDMMC_MASK_DBCKENDIE_Msk              /*!<Data Block End Interrupt Enable            */

+#define SDMMC_MASK_DABORTIE_Pos          (11U)

+#define SDMMC_MASK_DABORTIE_Msk          (0x1UL << SDMMC_MASK_DABORTIE_Pos)    /*!< 0x00000800 */

+#define SDMMC_MASK_DABORTIE              SDMMC_MASK_DABORTIE_Msk               /*!<Data transfer aborted interrupt enable     */

+

+#define SDMMC_MASK_TXFIFOHEIE_Pos        (14U)

+#define SDMMC_MASK_TXFIFOHEIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)  /*!< 0x00004000 */

+#define SDMMC_MASK_TXFIFOHEIE            SDMMC_MASK_TXFIFOHEIE_Msk             /*!<Tx FIFO Half Empty interrupt Enable        */

+#define SDMMC_MASK_RXFIFOHFIE_Pos        (15U)

+#define SDMMC_MASK_RXFIFOHFIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)  /*!< 0x00008000 */

+#define SDMMC_MASK_RXFIFOHFIE            SDMMC_MASK_RXFIFOHFIE_Msk             /*!<Rx FIFO Half Full interrupt Enable         */

+

+#define SDMMC_MASK_RXFIFOFIE_Pos         (17U)

+#define SDMMC_MASK_RXFIFOFIE_Msk         (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)   /*!< 0x00020000 */

+#define SDMMC_MASK_RXFIFOFIE             SDMMC_MASK_RXFIFOFIE_Msk              /*!<Rx FIFO Full interrupt Enable              */

+#define SDMMC_MASK_TXFIFOEIE_Pos         (18U)

+#define SDMMC_MASK_TXFIFOEIE_Msk         (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)   /*!< 0x00040000 */

+#define SDMMC_MASK_TXFIFOEIE             SDMMC_MASK_TXFIFOEIE_Msk              /*!<Tx FIFO Empty interrupt Enable             */

+

+#define SDMMC_MASK_BUSYD0ENDIE_Pos       (21U)

+#define SDMMC_MASK_BUSYD0ENDIE_Msk       (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */

+#define SDMMC_MASK_BUSYD0ENDIE           SDMMC_MASK_BUSYD0ENDIE_Msk            /*!<BUSYD0ENDIE interrupt Enable */

+#define SDMMC_MASK_SDIOITIE_Pos           (22U)

+#define SDMMC_MASK_SDIOITIE_Msk           (0x1UL << SDMMC_MASK_SDIOITIE_Pos)     /*!< 0x00400000 */

+#define SDMMC_MASK_SDIOITIE               SDMMC_MASK_SDIOITIE_Msk                /*!<SDMMC Mode Interrupt Received interrupt Enable */

+#define SDMMC_MASK_ACKFAILIE_Pos         (23U)

+#define SDMMC_MASK_ACKFAILIE_Msk         (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)   /*!< 0x00800000 */

+#define SDMMC_MASK_ACKFAILIE             SDMMC_MASK_ACKFAILIE_Msk              /*!<Acknowledgment Fail Interrupt Enable */

+#define SDMMC_MASK_ACKTIMEOUTIE_Pos      (24U)

+#define SDMMC_MASK_ACKTIMEOUTIE_Msk      (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */

+#define SDMMC_MASK_ACKTIMEOUTIE          SDMMC_MASK_ACKTIMEOUTIE_Msk           /*!<Acknowledgment timeout Interrupt Enable */

+#define SDMMC_MASK_VSWENDIE_Pos          (25U)

+#define SDMMC_MASK_VSWENDIE_Msk          (0x1UL << SDMMC_MASK_VSWENDIE_Pos)    /*!< 0x02000000 */

+#define SDMMC_MASK_VSWENDIE              SDMMC_MASK_VSWENDIE_Msk               /*!<Voltage switch critical timing section completion Interrupt Enable */

+#define SDMMC_MASK_CKSTOPIE_Pos          (26U)

+#define SDMMC_MASK_CKSTOPIE_Msk          (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)    /*!< 0x04000000 */

+#define SDMMC_MASK_CKSTOPIE              SDMMC_MASK_CKSTOPIE_Msk               /*!<Voltage Switch clock stopped Interrupt Enable */

+#define SDMMC_MASK_IDMABTCIE_Pos         (28U)

+#define SDMMC_MASK_IDMABTCIE_Msk         (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)   /*!< 0x10000000 */

+#define SDMMC_MASK_IDMABTCIE             SDMMC_MASK_IDMABTCIE_Msk              /*!<IDMA buffer transfer complete Interrupt Enable */

+

+/*****************  Bit definition for SDMMC_ACKTIME register  *****************/

+#define SDMMC_ACKTIME_ACKTIME_Pos        (0U)

+#define SDMMC_ACKTIME_ACKTIME_Msk        (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_ACKTIME_ACKTIME            SDMMC_ACKTIME_ACKTIME_Msk             /*!<Boot acknowledgment timeout period */

+

+/******************  Bit definition for SDMMC_FIFO register  *******************/

+#define SDMMC_FIFO_FIFODATA_Pos          (0U)

+#define SDMMC_FIFO_FIFODATA_Msk          (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_FIFO_FIFODATA              SDMMC_FIFO_FIFODATA_Msk               /*!<Receive and transmit FIFO data */

+

+/******************  Bit definition for SDMMC_IDMACTRL register ****************/

+#define SDMMC_IDMA_IDMAEN_Pos            (0U)

+#define SDMMC_IDMA_IDMAEN_Msk            (0x1UL << SDMMC_IDMA_IDMAEN_Pos)      /*!< 0x00000001 */

+#define SDMMC_IDMA_IDMAEN                SDMMC_IDMA_IDMAEN_Msk                 /*!< Enable the internal DMA of the SDMMC peripheral */

+#define SDMMC_IDMA_IDMABMODE_Pos         (1U)

+#define SDMMC_IDMA_IDMABMODE_Msk         (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)   /*!< 0x00000002 */

+#define SDMMC_IDMA_IDMABMODE             SDMMC_IDMA_IDMABMODE_Msk              /*!< Enable double buffer mode for IDMA */

+#define SDMMC_IDMA_IDMABACT_Pos          (2U)

+#define SDMMC_IDMA_IDMABACT_Msk          (0x1UL << SDMMC_IDMA_IDMABACT_Pos)    /*!< 0x00000004 */

+#define SDMMC_IDMA_IDMABACT              SDMMC_IDMA_IDMABACT_Msk               /*!< Uses buffer 1 when double buffer mode is selected */

+

+/*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/

+#define SDMMC_IDMABSIZE_IDMABNDT_Pos     (5U)

+#define SDMMC_IDMABSIZE_IDMABNDT_Msk     (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */

+#define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */

+

+/*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/

+#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */

+

+/*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/

+#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                        Delay Block Interface (DLYB)                        */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for DLYB_CR register  ********************/

+#define DLYB_CR_DEN_Pos         (0U)

+#define DLYB_CR_DEN_Msk         (0x1UL << DLYB_CR_DEN_Pos)                     /*!< 0x00000001 */

+#define DLYB_CR_DEN             DLYB_CR_DEN_Msk                                /*!<Delay Block enable */

+#define DLYB_CR_SEN_Pos         (1U)

+#define DLYB_CR_SEN_Msk         (0x1UL << DLYB_CR_SEN_Pos)                     /*!< 0x00000002 */

+#define DLYB_CR_SEN             DLYB_CR_SEN_Msk                                /*!<Sampler length enable */

+

+

+/*******************  Bit definition for DLYB_CFGR register  ********************/

+#define DLYB_CFGR_SEL_Pos       (0U)

+#define DLYB_CFGR_SEL_Msk       (0xFUL << DLYB_CFGR_SEL_Pos)                   /*!< 0x0000000F */

+#define DLYB_CFGR_SEL           DLYB_CFGR_SEL_Msk                              /*!<Select the phase for the Output clock[3:0] */

+#define DLYB_CFGR_SEL_0         (0x1UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000001 */

+#define DLYB_CFGR_SEL_1         (0x2UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000002 */

+#define DLYB_CFGR_SEL_2         (0x3UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000003 */

+#define DLYB_CFGR_SEL_3         (0x8UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000008 */

+

+#define DLYB_CFGR_UNIT_Pos      (8U)

+#define DLYB_CFGR_UNIT_Msk      (0x7FUL << DLYB_CFGR_UNIT_Pos)                 /*!< 0x00007F00 */

+#define DLYB_CFGR_UNIT          DLYB_CFGR_UNIT_Msk                             /*!<Delay Defines the delay of a Unit delay cell[6:0] */

+#define DLYB_CFGR_UNIT_0        (0x01UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000100 */

+#define DLYB_CFGR_UNIT_1        (0x02UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000200 */

+#define DLYB_CFGR_UNIT_2        (0x04UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000400 */

+#define DLYB_CFGR_UNIT_3        (0x08UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000800 */

+#define DLYB_CFGR_UNIT_4        (0x10UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00001000 */

+#define DLYB_CFGR_UNIT_5        (0x20UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00002000 */

+#define DLYB_CFGR_UNIT_6        (0x40UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00004000 */

+

+#define DLYB_CFGR_LNG_Pos       (16U)

+#define DLYB_CFGR_LNG_Msk       (0xFFFUL << DLYB_CFGR_LNG_Pos)                 /*!< 0x0FFF0000 */

+#define DLYB_CFGR_LNG           DLYB_CFGR_LNG_Msk                              /*!<Delay line length value[11:0] */

+#define DLYB_CFGR_LNG_0         (0x001UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00010000 */

+#define DLYB_CFGR_LNG_1         (0x002UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00020000 */

+#define DLYB_CFGR_LNG_2         (0x004UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00040000 */

+#define DLYB_CFGR_LNG_3         (0x008UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00080000 */

+#define DLYB_CFGR_LNG_4         (0x010UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00100000 */

+#define DLYB_CFGR_LNG_5         (0x020UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00200000 */

+#define DLYB_CFGR_LNG_6         (0x040UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00400000 */

+#define DLYB_CFGR_LNG_7         (0x080UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00800000 */

+#define DLYB_CFGR_LNG_8         (0x100UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x01000000 */

+#define DLYB_CFGR_LNG_9         (0x200UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x02000000 */

+#define DLYB_CFGR_LNG_10        (0x400UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x04000000 */

+#define DLYB_CFGR_LNG_11        (0x800UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x08000000 */

+

+#define DLYB_CFGR_LNGF_Pos      (31U)

+#define DLYB_CFGR_LNGF_Msk      (0x1UL << DLYB_CFGR_LNGF_Pos)                  /*!< 0x80000000 */

+#define DLYB_CFGR_LNGF          DLYB_CFGR_LNGF_Msk                             /*!<Length valid flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                   Serial Peripheral Interface (SPI/I2S)                    */

+/*                                                                            */

+/******************************************************************************/

+#define SPI_SPI6I2S_SUPPORT       /*!<SPI6 I2S support feature */

+/*******************  Bit definition for SPI_CR1 register  ********************/

+#define SPI_CR1_SPE_Pos             (0U)

+#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000001 */

+#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<Serial Peripheral Enable                         */

+#define SPI_CR1_MASRX_Pos           (8U)

+#define SPI_CR1_MASRX_Msk           (0x1UL << SPI_CR1_MASRX_Pos)               /*!< 0x00000100 */

+#define SPI_CR1_MASRX               SPI_CR1_MASRX_Msk                          /*!<Master automatic SUSP in Receive mode            */

+#define SPI_CR1_CSTART_Pos          (9U)

+#define SPI_CR1_CSTART_Msk          (0x1UL << SPI_CR1_CSTART_Pos)              /*!< 0x00000200 */

+#define SPI_CR1_CSTART              SPI_CR1_CSTART_Msk                         /*!<Master transfer start                            */

+#define SPI_CR1_CSUSP_Pos           (10U)

+#define SPI_CR1_CSUSP_Msk           (0x1UL << SPI_CR1_CSUSP_Pos)               /*!< 0x00000400 */

+#define SPI_CR1_CSUSP               SPI_CR1_CSUSP_Msk                          /*!<Master SUSPend request                           */

+#define SPI_CR1_HDDIR_Pos           (11U)

+#define SPI_CR1_HDDIR_Msk           (0x1UL << SPI_CR1_HDDIR_Pos)               /*!< 0x00000800 */

+#define SPI_CR1_HDDIR               SPI_CR1_HDDIR_Msk                          /*!<Rx/Tx direction at Half-duplex mode              */

+#define SPI_CR1_SSI_Pos             (12U)

+#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00001000 */

+#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal SS signal input level                   */

+#define SPI_CR1_CRC33_17_Pos        (13U)

+#define SPI_CR1_CRC33_17_Msk        (0x1UL << SPI_CR1_CRC33_17_Pos)            /*!< 0x00002000 */

+#define SPI_CR1_CRC33_17             SPI_CR1_CRC33_17_Msk                      /*!<32-bit CRC polynomial configuration              */

+#define SPI_CR1_RCRCINI_Pos         (14U)

+#define SPI_CR1_RCRCINI_Msk         (0x1UL << SPI_CR1_RCRCINI_Pos)             /*!< 0x00004000 */

+#define SPI_CR1_RCRCINI             SPI_CR1_RCRCINI_Msk                        /*!<CRC init pattern control for receiver            */

+#define SPI_CR1_TCRCINI_Pos         (15U)

+#define SPI_CR1_TCRCINI_Msk         (0x1UL << SPI_CR1_TCRCINI_Pos)             /*!< 0x00008000 */

+#define SPI_CR1_TCRCINI             SPI_CR1_TCRCINI_Msk                        /*!<CRC init pattern control for transmitter         */

+#define SPI_CR1_IOLOCK_Pos          (16U)

+#define SPI_CR1_IOLOCK_Msk          (0x1UL << SPI_CR1_IOLOCK_Pos)              /*!< 0x00010000 */

+#define SPI_CR1_IOLOCK              SPI_CR1_IOLOCK_Msk                         /*!<Locking the AF configuration of associated IOs   */

+

+/*******************  Bit definition for SPI_CR2 register  ********************/

+#define SPI_CR2_TSER_Pos            (16U)

+#define SPI_CR2_TSER_Msk            (0xFFFFUL << SPI_CR2_TSER_Pos)             /*!< 0xFFFF0000 */

+#define SPI_CR2_TSER                SPI_CR2_TSER_Msk                           /*!<Number of data transfer extension                */

+#define SPI_CR2_TSIZE_Pos           (0U)

+#define SPI_CR2_TSIZE_Msk           (0xFFFFUL << SPI_CR2_TSIZE_Pos)            /*!< 0x0000FFFF */

+#define SPI_CR2_TSIZE               SPI_CR2_TSIZE_Msk                          /*!<Number of data at current transfer               */

+

+/*******************  Bit definition for SPI_CFG1 register  ********************/

+#define SPI_CFG1_DSIZE_Pos          (0U)

+#define SPI_CFG1_DSIZE_Msk          (0x1FUL << SPI_CFG1_DSIZE_Pos)             /*!< 0x0000001F */

+#define SPI_CFG1_DSIZE              SPI_CFG1_DSIZE_Msk                         /*!<DSIZE[4:0]: Bits number in single SPI data frame */

+#define SPI_CFG1_DSIZE_0            (0x01UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000001 */

+#define SPI_CFG1_DSIZE_1            (0x02UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000002 */

+#define SPI_CFG1_DSIZE_2            (0x04UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000004 */

+#define SPI_CFG1_DSIZE_3            (0x08UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000008 */

+#define SPI_CFG1_DSIZE_4            (0x10UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000010 */

+

+#define SPI_CFG1_FTHLV_Pos          (5U)

+#define SPI_CFG1_FTHLV_Msk          (0xFUL << SPI_CFG1_FTHLV_Pos)              /*!< 0x000001E0 */

+#define SPI_CFG1_FTHLV              SPI_CFG1_FTHLV_Msk                         /*!<FTHVL [3:0]: FIFO threshold level*/

+#define SPI_CFG1_FTHLV_0            (0x1UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000020 */

+#define SPI_CFG1_FTHLV_1            (0x2UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000040 */

+#define SPI_CFG1_FTHLV_2            (0x4UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000080 */

+#define SPI_CFG1_FTHLV_3            (0x8UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000100 */

+

+#define SPI_CFG1_UDRCFG_Pos         (9U)

+#define SPI_CFG1_UDRCFG_Msk         (0x3UL << SPI_CFG1_UDRCFG_Pos)             /*!< 0x00000600 */

+#define SPI_CFG1_UDRCFG             SPI_CFG1_UDRCFG_Msk                        /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */

+#define SPI_CFG1_UDRCFG_0           (0x1UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000200 */

+#define SPI_CFG1_UDRCFG_1           (0x2UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000400 */

+

+

+#define SPI_CFG1_UDRDET_Pos         (11U)

+#define SPI_CFG1_UDRDET_Msk         (0x3UL << SPI_CFG1_UDRDET_Pos)             /*!< 0x00001800 */

+#define SPI_CFG1_UDRDET             SPI_CFG1_UDRDET_Msk                        /*!<UDRDET[1:0]: Detection of underrun condition     */

+#define SPI_CFG1_UDRDET_0           (0x1UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00000800 */

+#define SPI_CFG1_UDRDET_1           (0x2UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00001000 */

+

+#define SPI_CFG1_RXDMAEN_Pos        (14U)

+#define SPI_CFG1_RXDMAEN_Msk        (0x1UL << SPI_CFG1_RXDMAEN_Pos)            /*!< 0x00004000 */

+#define SPI_CFG1_RXDMAEN            SPI_CFG1_RXDMAEN_Msk                       /*!<Rx DMA stream enable                */

+#define SPI_CFG1_TXDMAEN_Pos        (15U)

+#define SPI_CFG1_TXDMAEN_Msk        (0x1UL << SPI_CFG1_TXDMAEN_Pos)            /*!< 0x00008000 */

+#define SPI_CFG1_TXDMAEN            SPI_CFG1_TXDMAEN_Msk                       /*!<Tx DMA stream enable                */

+

+#define SPI_CFG1_CRCSIZE_Pos        (16U)

+#define SPI_CFG1_CRCSIZE_Msk        (0x1FUL << SPI_CFG1_CRCSIZE_Pos)           /*!< 0x001F0000 */

+#define SPI_CFG1_CRCSIZE            SPI_CFG1_CRCSIZE_Msk                       /*!<CRCSIZE [4:0]: Length of CRC frame*/

+#define SPI_CFG1_CRCSIZE_0          (0x01UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00010000 */

+#define SPI_CFG1_CRCSIZE_1          (0x02UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00020000 */

+#define SPI_CFG1_CRCSIZE_2          (0x04UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00040000 */

+#define SPI_CFG1_CRCSIZE_3          (0x08UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00080000 */

+#define SPI_CFG1_CRCSIZE_4          (0x10UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00100000 */

+

+#define SPI_CFG1_CRCEN_Pos          (22U)

+#define SPI_CFG1_CRCEN_Msk          (0x1UL << SPI_CFG1_CRCEN_Pos)              /*!< 0x00400000 */

+#define SPI_CFG1_CRCEN              SPI_CFG1_CRCEN_Msk                         /*!<Hardware CRC computation enable */

+

+#define SPI_CFG1_MBR_Pos            (28U)

+#define SPI_CFG1_MBR_Msk            (0x7UL << SPI_CFG1_MBR_Pos)                /*!< 0x70000000 */

+#define SPI_CFG1_MBR                SPI_CFG1_MBR_Msk                           /*!<Master baud rate                */

+#define SPI_CFG1_MBR_0              (0x1UL << SPI_CFG1_MBR_Pos)                 /*!< 0x10000000 */

+#define SPI_CFG1_MBR_1              (0x2UL << SPI_CFG1_MBR_Pos)                 /*!< 0x20000000 */

+#define SPI_CFG1_MBR_2              (0x4UL << SPI_CFG1_MBR_Pos)                 /*!< 0x40000000 */

+

+/*******************  Bit definition for SPI_CFG2 register  ********************/

+#define SPI_CFG2_MSSI_Pos           (0U)

+#define SPI_CFG2_MSSI_Msk           (0xFUL << SPI_CFG2_MSSI_Pos)               /*!< 0x0000000F */

+#define SPI_CFG2_MSSI               SPI_CFG2_MSSI_Msk                          /*!<Master SS Idleness */

+#define SPI_CFG2_MSSI_0             (0x1UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000001 */

+#define SPI_CFG2_MSSI_1             (0x2UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000002 */

+#define SPI_CFG2_MSSI_2             (0x4UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000004 */

+#define SPI_CFG2_MSSI_3             (0x8UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000008 */

+

+#define SPI_CFG2_MIDI_Pos           (4U)

+#define SPI_CFG2_MIDI_Msk           (0xFUL << SPI_CFG2_MIDI_Pos)               /*!< 0x000000F0 */

+#define SPI_CFG2_MIDI               SPI_CFG2_MIDI_Msk                          /*!<Master Inter-Data Idleness */

+#define SPI_CFG2_MIDI_0             (0x1UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000010 */

+#define SPI_CFG2_MIDI_1             (0x2UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000020 */

+#define SPI_CFG2_MIDI_2             (0x4UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000040 */

+#define SPI_CFG2_MIDI_3             (0x8UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000080 */

+

+#define SPI_CFG2_IOSWP_Pos          (15U)

+#define SPI_CFG2_IOSWP_Msk          (0x1UL << SPI_CFG2_IOSWP_Pos)              /*!< 0x00008000 */

+#define SPI_CFG2_IOSWP              SPI_CFG2_IOSWP_Msk                         /*!<Swap functionality of MISO and MOSI pins */

+

+#define SPI_CFG2_COMM_Pos           (17U)

+#define SPI_CFG2_COMM_Msk           (0x3UL << SPI_CFG2_COMM_Pos)               /*!< 0x00060000 */

+#define SPI_CFG2_COMM               SPI_CFG2_COMM_Msk                          /*!<COMM [1:0]: SPI Communication Mode*/

+#define SPI_CFG2_COMM_0             (0x1UL << SPI_CFG2_COMM_Pos)                /*!< 0x00020000 */

+#define SPI_CFG2_COMM_1             (0x2UL << SPI_CFG2_COMM_Pos)                /*!< 0x00040000 */

+

+#define SPI_CFG2_SP_Pos             (19U)

+#define SPI_CFG2_SP_Msk             (0x7UL << SPI_CFG2_SP_Pos)                 /*!< 0x00380000 */

+#define SPI_CFG2_SP                 SPI_CFG2_SP_Msk                            /*!<SP[2:0]: Serial Protocol */

+#define SPI_CFG2_SP_0               (0x1UL << SPI_CFG2_SP_Pos)                  /*!< 0x00080000 */

+#define SPI_CFG2_SP_1               (0x2UL << SPI_CFG2_SP_Pos)                  /*!< 0x00100000 */

+#define SPI_CFG2_SP_2               (0x4UL << SPI_CFG2_SP_Pos)                  /*!< 0x00200000 */

+

+#define SPI_CFG2_MASTER_Pos         (22U)

+#define SPI_CFG2_MASTER_Msk         (0x1UL << SPI_CFG2_MASTER_Pos)             /*!< 0x00400000 */

+#define SPI_CFG2_MASTER             SPI_CFG2_MASTER_Msk                        /*!<SPI Master           */

+#define SPI_CFG2_LSBFRST_Pos        (23U)

+#define SPI_CFG2_LSBFRST_Msk        (0x1UL << SPI_CFG2_LSBFRST_Pos)            /*!< 0x00800000 */

+#define SPI_CFG2_LSBFRST            SPI_CFG2_LSBFRST_Msk                       /*!<Data frame format               */

+#define SPI_CFG2_CPHA_Pos           (24U)

+#define SPI_CFG2_CPHA_Msk           (0x1UL << SPI_CFG2_CPHA_Pos)               /*!< 0x01000000 */

+#define SPI_CFG2_CPHA               SPI_CFG2_CPHA_Msk                          /*!<Clock Phase      */

+#define SPI_CFG2_CPOL_Pos           (25U)

+#define SPI_CFG2_CPOL_Msk           (0x1UL << SPI_CFG2_CPOL_Pos)               /*!< 0x02000000 */

+#define SPI_CFG2_CPOL               SPI_CFG2_CPOL_Msk                          /*!<Clock Polarity   */

+#define SPI_CFG2_SSM_Pos            (26U)

+#define SPI_CFG2_SSM_Msk            (0x1UL << SPI_CFG2_SSM_Pos)                /*!< 0x04000000 */

+#define SPI_CFG2_SSM                SPI_CFG2_SSM_Msk                           /*!<Software slave management */

+

+#define SPI_CFG2_SSIOP_Pos          (28U)

+#define SPI_CFG2_SSIOP_Msk          (0x1UL << SPI_CFG2_SSIOP_Pos)              /*!< 0x10000000 */

+#define SPI_CFG2_SSIOP              SPI_CFG2_SSIOP_Msk                         /*!<SS input/output polarity */

+#define SPI_CFG2_SSOE_Pos           (29U)

+#define SPI_CFG2_SSOE_Msk           (0x1UL << SPI_CFG2_SSOE_Pos)               /*!< 0x20000000 */

+#define SPI_CFG2_SSOE               SPI_CFG2_SSOE_Msk                          /*!<SS output enable */

+#define SPI_CFG2_SSOM_Pos           (30U)

+#define SPI_CFG2_SSOM_Msk           (0x1UL << SPI_CFG2_SSOM_Pos)               /*!< 0x40000000 */

+#define SPI_CFG2_SSOM               SPI_CFG2_SSOM_Msk                          /*!<SS output management in master mode */

+

+#define SPI_CFG2_AFCNTR_Pos         (31U)

+#define SPI_CFG2_AFCNTR_Msk         (0x1UL << SPI_CFG2_AFCNTR_Pos)             /*!< 0x80000000 */

+#define SPI_CFG2_AFCNTR             SPI_CFG2_AFCNTR_Msk                        /*!<Alternate function GPIOs control */

+

+/*******************  Bit definition for SPI_IER register  ********************/

+#define SPI_IER_RXPIE_Pos           (0U)

+#define SPI_IER_RXPIE_Msk           (0x1UL << SPI_IER_RXPIE_Pos)               /*!< 0x00000001 */

+#define SPI_IER_RXPIE               SPI_IER_RXPIE_Msk                          /*!<RXP Interrupt Enable            */

+#define SPI_IER_TXPIE_Pos           (1U)

+#define SPI_IER_TXPIE_Msk           (0x1UL << SPI_IER_TXPIE_Pos)               /*!< 0x00000002 */

+#define SPI_IER_TXPIE               SPI_IER_TXPIE_Msk                          /*!<TXP interrupt enable            */

+#define SPI_IER_DXPIE_Pos           (2U)

+#define SPI_IER_DXPIE_Msk           (0x1UL << SPI_IER_DXPIE_Pos)               /*!< 0x00000004 */

+#define SPI_IER_DXPIE               SPI_IER_DXPIE_Msk                          /*!<DXP interrupt enable            */

+#define SPI_IER_EOTIE_Pos           (3U)

+#define SPI_IER_EOTIE_Msk           (0x1UL << SPI_IER_EOTIE_Pos)               /*!< 0x00000008 */

+#define SPI_IER_EOTIE               SPI_IER_EOTIE_Msk                          /*!<EOT/SUSP/TXC interrupt enable   */

+#define SPI_IER_TXTFIE_Pos          (4U)

+#define SPI_IER_TXTFIE_Msk          (0x1UL << SPI_IER_TXTFIE_Pos)              /*!< 0x00000010 */

+#define SPI_IER_TXTFIE              SPI_IER_TXTFIE_Msk                         /*!<TXTF interrupt enable           */

+#define SPI_IER_UDRIE_Pos           (5U)

+#define SPI_IER_UDRIE_Msk           (0x1UL << SPI_IER_UDRIE_Pos)               /*!< 0x00000020 */

+#define SPI_IER_UDRIE               SPI_IER_UDRIE_Msk                          /*!<UDR interrupt enable            */

+#define SPI_IER_OVRIE_Pos           (6U)

+#define SPI_IER_OVRIE_Msk           (0x1UL << SPI_IER_OVRIE_Pos)               /*!< 0x00000040 */

+#define SPI_IER_OVRIE               SPI_IER_OVRIE_Msk                          /*!<OVR interrupt enable            */

+#define SPI_IER_CRCEIE_Pos          (7U)

+#define SPI_IER_CRCEIE_Msk          (0x1UL << SPI_IER_CRCEIE_Pos)               /*!< 0x00000080 */

+#define SPI_IER_CRCEIE              SPI_IER_CRCEIE_Msk                          /*!<CRCE interrupt enable           */

+#define SPI_IER_TIFREIE_Pos         (8U)

+#define SPI_IER_TIFREIE_Msk         (0x1UL << SPI_IER_TIFREIE_Pos)             /*!< 0x00000100 */

+#define SPI_IER_TIFREIE             SPI_IER_TIFREIE_Msk                        /*!<TI Frame Error interrupt enable */

+#define SPI_IER_MODFIE_Pos          (9U)

+#define SPI_IER_MODFIE_Msk          (0x1UL << SPI_IER_MODFIE_Pos)              /*!< 0x00000200 */

+#define SPI_IER_MODFIE              SPI_IER_MODFIE_Msk                         /*!<MODF interrupt enable           */

+#define SPI_IER_TSERFIE_Pos         (10U)

+#define SPI_IER_TSERFIE_Msk         (0x1UL << SPI_IER_TSERFIE_Pos)              /*!< 0x00000400 */

+#define SPI_IER_TSERFIE             SPI_IER_TSERFIE_Msk                        /*!<TSERF interrupt enable          */

+

+/*******************  Bit definition for SPI_SR register  ********************/

+#define SPI_SR_RXP_Pos              (0U)

+#define SPI_SR_RXP_Msk              (0x1UL << SPI_SR_RXP_Pos)                  /*!< 0x00000001 */

+#define SPI_SR_RXP                  SPI_SR_RXP_Msk                             /*!<Rx-Packet available             */

+#define SPI_SR_TXP_Pos              (1U)

+#define SPI_SR_TXP_Msk              (0x1UL << SPI_SR_TXP_Pos)                  /*!< 0x00000002 */

+#define SPI_SR_TXP                  SPI_SR_TXP_Msk                             /*!<Tx-Packet space available       */

+#define SPI_SR_DXP_Pos              (2U)

+#define SPI_SR_DXP_Msk              (0x1UL << SPI_SR_DXP_Pos)                  /*!< 0x00000004 */

+#define SPI_SR_DXP                  SPI_SR_DXP_Msk                             /*!<Duplex Packet available         */

+#define SPI_SR_EOT_Pos              (3U)

+#define SPI_SR_EOT_Msk              (0x1UL << SPI_SR_EOT_Pos)                  /*!< 0x00000008 */

+#define SPI_SR_EOT                  SPI_SR_EOT_Msk                             /*!<Duplex Packet available         */

+#define SPI_SR_TXTF_Pos             (4U)

+#define SPI_SR_TXTF_Msk             (0x1UL << SPI_SR_TXTF_Pos)                 /*!< 0x00000010 */

+#define SPI_SR_TXTF                 SPI_SR_TXTF_Msk                            /*!<Transmission Transfer Filled    */

+#define SPI_SR_UDR_Pos              (5U)

+#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000020 */

+#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<UDR at Slave transmission       */

+#define SPI_SR_OVR_Pos              (6U)

+#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */

+#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Rx-Packet available             */

+#define SPI_SR_CRCE_Pos             (7U)

+#define SPI_SR_CRCE_Msk             (0x1UL << SPI_SR_CRCE_Pos)                 /*!< 0x00000080 */

+#define SPI_SR_CRCE                 SPI_SR_CRCE_Msk                            /*!<CRC Error Detected              */

+#define SPI_SR_TIFRE_Pos            (8U)

+#define SPI_SR_TIFRE_Msk            (0x1UL << SPI_SR_TIFRE_Pos)                /*!< 0x00000100 */

+#define SPI_SR_TIFRE                SPI_SR_TIFRE_Msk                           /*!<TI frame format error Detected  */

+#define SPI_SR_MODF_Pos             (9U)

+#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000200 */

+#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode Fault Detected             */

+#define SPI_SR_TSERF_Pos            (10U)

+#define SPI_SR_TSERF_Msk            (0x1UL << SPI_SR_TSERF_Pos)                /*!< 0x00000400 */

+#define SPI_SR_TSERF                SPI_SR_TSERF_Msk                           /*!<Number of SPI data to be transacted reloaded     */

+#define SPI_SR_SUSP_Pos             (11U)

+#define SPI_SR_SUSP_Msk             (0x1UL << SPI_SR_SUSP_Pos)                 /*!< 0x00000800 */

+#define SPI_SR_SUSP                 SPI_SR_SUSP_Msk                            /*!<SUSP is set by hardware  */

+#define SPI_SR_TXC_Pos              (12U)

+#define SPI_SR_TXC_Msk              (0x1UL << SPI_SR_TXC_Pos)                  /*!< 0x00001000 */

+#define SPI_SR_TXC                  SPI_SR_TXC_Msk                             /*!<TxFIFO transmission complete */

+#define SPI_SR_RXPLVL_Pos           (13U)

+#define SPI_SR_RXPLVL_Msk           (0x3UL << SPI_SR_RXPLVL_Pos)               /*!< 0x00006000 */

+#define SPI_SR_RXPLVL               SPI_SR_RXPLVL_Msk                          /*!<RxFIFO Packing Level                             */

+#define SPI_SR_RXPLVL_0             (0x1UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00002000 */

+#define SPI_SR_RXPLVL_1             (0x2UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00004000 */

+#define SPI_SR_RXWNE_Pos            (15U)

+#define SPI_SR_RXWNE_Msk            (0x1UL << SPI_SR_RXWNE_Pos)                /*!< 0x00008000 */

+#define SPI_SR_RXWNE                SPI_SR_RXWNE_Msk                           /*!<Rx FIFO Word Not Empty                           */

+#define SPI_SR_CTSIZE_Pos           (16U)

+#define SPI_SR_CTSIZE_Msk           (0xFFFFUL << SPI_SR_CTSIZE_Pos)            /*!< 0xFFFF0000 */

+#define SPI_SR_CTSIZE               SPI_SR_CTSIZE_Msk                          /*!<Number of data frames remaining in TSIZE         */

+

+/*******************  Bit definition for SPI_IFCR register  ********************/

+#define SPI_IFCR_EOTC_Pos           (3U)

+#define SPI_IFCR_EOTC_Msk           (0x1UL << SPI_IFCR_EOTC_Pos)               /*!< 0x00000008 */

+#define SPI_IFCR_EOTC               SPI_IFCR_EOTC_Msk                          /*!<End Of Transfer flag clear              */

+#define SPI_IFCR_TXTFC_Pos          (4U)

+#define SPI_IFCR_TXTFC_Msk          (0x1UL << SPI_IFCR_TXTFC_Pos)              /*!< 0x00000010 */

+#define SPI_IFCR_TXTFC              SPI_IFCR_TXTFC_Msk                         /*!<Transmission Transfer Filled flag clear */

+#define SPI_IFCR_UDRC_Pos           (5U)

+#define SPI_IFCR_UDRC_Msk           (0x1UL << SPI_IFCR_UDRC_Pos)               /*!< 0x00000020 */

+#define SPI_IFCR_UDRC               SPI_IFCR_UDRC_Msk                          /*!<Underrun flag clear                     */

+#define SPI_IFCR_OVRC_Pos           (6U)

+#define SPI_IFCR_OVRC_Msk           (0x1UL << SPI_IFCR_OVRC_Pos)               /*!< 0x00000040 */

+#define SPI_IFCR_OVRC               SPI_IFCR_OVRC_Msk                          /*!<Overrun flag clear                      */

+#define SPI_IFCR_CRCEC_Pos          (7U)

+#define SPI_IFCR_CRCEC_Msk          (0x1UL << SPI_IFCR_CRCEC_Pos)              /*!< 0x00000080 */

+#define SPI_IFCR_CRCEC              SPI_IFCR_CRCEC_Msk                         /*!<CRC Error flag clear                    */

+#define SPI_IFCR_TIFREC_Pos         (8U)

+#define SPI_IFCR_TIFREC_Msk         (0x1UL << SPI_IFCR_TIFREC_Pos)             /*!< 0x00000100 */

+#define SPI_IFCR_TIFREC             SPI_IFCR_TIFREC_Msk                        /*!<TI frame format error flag clear        */

+#define SPI_IFCR_MODFC_Pos          (9U)

+#define SPI_IFCR_MODFC_Msk          (0x1UL << SPI_IFCR_MODFC_Pos)              /*!< 0x00000200 */

+#define SPI_IFCR_MODFC              SPI_IFCR_MODFC_Msk                         /*!<Mode Fault flag clear                   */

+#define SPI_IFCR_TSERFC_Pos         (10U)

+#define SPI_IFCR_TSERFC_Msk         (0x1UL << SPI_IFCR_TSERFC_Pos)             /*!< 0x00000400 */

+#define SPI_IFCR_TSERFC             SPI_IFCR_TSERFC_Msk                        /*!<TSERFC flag clear                       */

+#define SPI_IFCR_SUSPC_Pos          (11U)

+#define SPI_IFCR_SUSPC_Msk          (0x1UL << SPI_IFCR_SUSPC_Pos)              /*!< 0x00000800 */

+#define SPI_IFCR_SUSPC              SPI_IFCR_SUSPC_Msk                         /*!<SUSPend flag clear                      */

+

+/*******************  Bit definition for SPI_TXDR register  ********************/

+#define SPI_TXDR_TXDR_Pos           (0U)

+#define SPI_TXDR_TXDR_Msk           (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)        /*!< 0xFFFFFFFF */

+#define SPI_TXDR_TXDR               SPI_TXDR_TXDR_Msk                          /* Transmit Data Register */

+

+/*******************  Bit definition for SPI_RXDR register  ********************/

+#define SPI_RXDR_RXDR_Pos           (0U)

+#define SPI_RXDR_RXDR_Msk           (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)        /*!< 0xFFFFFFFF */

+#define SPI_RXDR_RXDR               SPI_RXDR_RXDR_Msk                          /* Receive Data Register  */

+

+/*******************  Bit definition for SPI_CRCPOLY register  ********************/

+#define SPI_CRCPOLY_CRCPOLY_Pos     (0U)

+#define SPI_CRCPOLY_CRCPOLY_Msk     (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)  /*!< 0xFFFFFFFF */

+#define SPI_CRCPOLY_CRCPOLY         SPI_CRCPOLY_CRCPOLY_Msk                    /* CRC Polynomial register  */

+

+/*******************  Bit definition for SPI_TXCRC register  ********************/

+#define SPI_TXCRC_TXCRC_Pos         (0U)

+#define SPI_TXCRC_TXCRC_Msk         (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_TXCRC_TXCRC             SPI_TXCRC_TXCRC_Msk                        /* CRCRegister for transmitter */

+

+/*******************  Bit definition for SPI_RXCRC register  ********************/

+#define SPI_RXCRC_RXCRC_Pos         (0U)

+#define SPI_RXCRC_RXCRC_Msk         (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_RXCRC_RXCRC             SPI_RXCRC_RXCRC_Msk                        /* CRCRegister for receiver */

+

+/*******************  Bit definition for SPI_UDRDR register  ********************/

+#define SPI_UDRDR_UDRDR_Pos         (0U)

+#define SPI_UDRDR_UDRDR_Msk         (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_UDRDR_UDRDR             SPI_UDRDR_UDRDR_Msk                        /* Data at slave underrun condition */

+

+/******************  Bit definition for SPI_I2SCFGR register  *****************/

+#define SPI_I2SCFGR_I2SMOD_Pos      (0U)

+#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000001 */

+#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */

+#define SPI_I2SCFGR_I2SCFG_Pos      (1U)

+#define SPI_I2SCFGR_I2SCFG_Msk      (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x0000000E */

+#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[2:0] I2S configuration mode                */

+#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000002 */

+#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000004 */

+#define SPI_I2SCFGR_I2SCFG_2        (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000008 */

+#define SPI_I2SCFGR_I2SSTD_Pos      (4U)

+#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */

+#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] I2S standard selection                */

+#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */

+#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */

+#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)

+#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */

+#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                         */

+#define SPI_I2SCFGR_DATLEN_Pos      (8U)

+#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000300 */

+#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] Data length to be transferred         */

+#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000100 */

+#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000200 */

+#define SPI_I2SCFGR_CHLEN_Pos       (10U)

+#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000400 */

+#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */

+#define SPI_I2SCFGR_CKPOL_Pos       (11U)

+#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000800 */

+#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<Steady state clock polarity                       */

+#define SPI_I2SCFGR_FIXCH_Pos       (12U)

+#define SPI_I2SCFGR_FIXCH_Msk       (0x1UL << SPI_I2SCFGR_FIXCH_Pos)           /*!< 0x00001000 */

+#define SPI_I2SCFGR_FIXCH           SPI_I2SCFGR_FIXCH_Msk                      /*!<Fixed channel length in SLAVE                     */

+#define SPI_I2SCFGR_WSINV_Pos       (13U)

+#define SPI_I2SCFGR_WSINV_Msk       (0x1UL << SPI_I2SCFGR_WSINV_Pos)           /*!< 0x00002000 */

+#define SPI_I2SCFGR_WSINV           SPI_I2SCFGR_WSINV_Msk                      /*!<Word select inversion                             */

+#define SPI_I2SCFGR_DATFMT_Pos      (14U)

+#define SPI_I2SCFGR_DATFMT_Msk      (0x1UL << SPI_I2SCFGR_DATFMT_Pos)          /*!< 0x00004000 */

+#define SPI_I2SCFGR_DATFMT          SPI_I2SCFGR_DATFMT_Msk                     /*!<Data format                                       */

+#define SPI_I2SCFGR_I2SDIV_Pos      (16U)

+#define SPI_I2SCFGR_I2SDIV_Msk      (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)         /*!< 0x00FF0000 */

+#define SPI_I2SCFGR_I2SDIV          SPI_I2SCFGR_I2SDIV_Msk                     /*!<I2S Linear prescaler */

+#define SPI_I2SCFGR_ODD_Pos         (24U)

+#define SPI_I2SCFGR_ODD_Msk         (0x1UL << SPI_I2SCFGR_ODD_Pos)             /*!< 0x01000000 */

+#define SPI_I2SCFGR_ODD             SPI_I2SCFGR_ODD_Msk                        /*!<Odd factor for the prescaler */

+#define SPI_I2SCFGR_MCKOE_Pos       (25U)

+#define SPI_I2SCFGR_MCKOE_Msk       (0x1UL << SPI_I2SCFGR_MCKOE_Pos)           /*!< 0x02000000 */

+#define SPI_I2SCFGR_MCKOE           SPI_I2SCFGR_MCKOE_Msk                      /*!<Master Clock Output Enable */

+

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                 SYSCFG                                     */

+/*                                                                            */

+/******************************************************************************/

+

+/******************  Bit definition for SYSCFG_PMCR register  ******************/

+#define SYSCFG_PMCR_I2C1_FMP_Pos        (0U)

+#define SYSCFG_PMCR_I2C1_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos)    /*!< 0x00000001 */

+#define SYSCFG_PMCR_I2C1_FMP            SYSCFG_PMCR_I2C1_FMP_Msk               /*!< I2C1 Fast mode plus */

+#define SYSCFG_PMCR_I2C2_FMP_Pos        (1U)

+#define SYSCFG_PMCR_I2C2_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos)    /*!< 0x00000002 */

+#define SYSCFG_PMCR_I2C2_FMP            SYSCFG_PMCR_I2C2_FMP_Msk               /*!< I2C2 Fast mode plus */

+#define SYSCFG_PMCR_I2C3_FMP_Pos        (2U)

+#define SYSCFG_PMCR_I2C3_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos)    /*!< 0x00000004 */

+#define SYSCFG_PMCR_I2C3_FMP            SYSCFG_PMCR_I2C3_FMP_Msk               /*!< I2C3 Fast mode plus */

+#define SYSCFG_PMCR_I2C4_FMP_Pos        (3U)

+#define SYSCFG_PMCR_I2C4_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos)    /*!< 0x00000008 */

+#define SYSCFG_PMCR_I2C4_FMP            SYSCFG_PMCR_I2C4_FMP_Msk               /*!< I2C4 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB6_FMP_Pos     (4U)

+#define SYSCFG_PMCR_I2C_PB6_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */

+#define SYSCFG_PMCR_I2C_PB6_FMP         SYSCFG_PMCR_I2C_PB6_FMP_Msk            /*!< I2C PB6 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB7_FMP_Pos     (5U)

+#define SYSCFG_PMCR_I2C_PB7_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */

+#define SYSCFG_PMCR_I2C_PB7_FMP         SYSCFG_PMCR_I2C_PB7_FMP_Msk            /*!< I2C PB7 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB8_FMP_Pos     (6U)

+#define SYSCFG_PMCR_I2C_PB8_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */

+#define SYSCFG_PMCR_I2C_PB8_FMP         SYSCFG_PMCR_I2C_PB8_FMP_Msk            /*!< I2C PB8 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB9_FMP_Pos     (7U)

+#define SYSCFG_PMCR_I2C_PB9_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */

+#define SYSCFG_PMCR_I2C_PB9_FMP         SYSCFG_PMCR_I2C_PB9_FMP_Msk            /*!< I2C PB9 Fast mode plus */

+#define SYSCFG_PMCR_PA0SO_Pos           (24U)

+#define SYSCFG_PMCR_PA0SO_Msk           (0x1UL << SYSCFG_PMCR_PA0SO_Pos)       /*!< 0x01000000 */

+#define SYSCFG_PMCR_PA0SO               SYSCFG_PMCR_PA0SO_Msk                  /*!< PA0 Switch Open */

+#define SYSCFG_PMCR_PA1SO_Pos           (25U)

+#define SYSCFG_PMCR_PA1SO_Msk           (0x1UL << SYSCFG_PMCR_PA1SO_Pos)       /*!< 0x02000000 */

+#define SYSCFG_PMCR_PA1SO               SYSCFG_PMCR_PA1SO_Msk                  /*!< PA1 Switch Open */

+#define SYSCFG_PMCR_PC2SO_Pos           (26U)

+#define SYSCFG_PMCR_PC2SO_Msk           (0x1UL << SYSCFG_PMCR_PC2SO_Pos)       /*!< 0x04000000 */

+#define SYSCFG_PMCR_PC2SO               SYSCFG_PMCR_PC2SO_Msk                  /*!< PC2 Switch Open */

+#define SYSCFG_PMCR_PC3SO_Pos           (27U)

+#define SYSCFG_PMCR_PC3SO_Msk           (0x1UL << SYSCFG_PMCR_PC3SO_Pos)       /*!< 0x08000000 */

+#define SYSCFG_PMCR_PC3SO               SYSCFG_PMCR_PC3SO_Msk                  /*!< PC3 Switch Open */

+

+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/

+#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)

+#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */

+#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)

+#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */

+#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)

+#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000F00 */

+#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */

+#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)

+#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x0000F000 */

+#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */

+/**

+  * @brief   EXTI0 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */

+

+/**

+  * @brief   EXTI1 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */

+/**

+  * @brief   EXTI2 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */

+

+/**

+  * @brief   EXTI3 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/

+#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)

+#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */

+#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)

+#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */

+#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)

+#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000F00 */

+#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */

+#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)

+#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x0000F000 */

+#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */

+/**

+  * @brief   EXTI4 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */

+/**

+  * @brief   EXTI5 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */

+/**

+  * @brief   EXTI6 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */

+

+/**

+  * @brief   EXTI7 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/

+#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)

+#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */

+#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)

+#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */

+#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)

+#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000F00 */

+#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */

+#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)

+#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x0000F000 */

+#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */

+

+/**

+  * @brief   EXTI8 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */

+

+/**

+  * @brief   EXTI9 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */

+

+/**

+  * @brief   EXTI10 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */

+

+/**

+  * @brief   EXTI11 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/

+#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)

+#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x0000000F */

+#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */

+#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)

+#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x000000F0 */

+#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */

+#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)

+#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000F00 */

+#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */

+#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)

+#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x0000F000 */

+#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */

+/**

+  * @brief   EXTI12 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */

+/**

+  * @brief   EXTI13 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */

+/**

+  * @brief   EXTI14 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */

+/**

+  * @brief   EXTI15 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */

+

+/******************  Bit definition for SYSCFG_CFGR register  ******************/

+#define SYSCFG_CFGR_PVDL_Pos            (2U)

+#define SYSCFG_CFGR_PVDL_Msk            (0x1UL << SYSCFG_CFGR_PVDL_Pos)        /*!< 0x00000004 */

+#define SYSCFG_CFGR_PVDL                SYSCFG_CFGR_PVDL_Msk                   /*!<PVD lock enable bit */

+#define SYSCFG_CFGR_FLASHL_Pos          (3U)

+#define SYSCFG_CFGR_FLASHL_Msk          (0x1UL << SYSCFG_CFGR_FLASHL_Pos)      /*!< 0x00000008 */

+#define SYSCFG_CFGR_FLASHL              SYSCFG_CFGR_FLASHL_Msk                 /*!<FLASH double ECC error lock bit */

+#define SYSCFG_CFGR_CM7L_Pos            (6U)

+#define SYSCFG_CFGR_CM7L_Msk            (0x1UL << SYSCFG_CFGR_CM7L_Pos)        /*!< 0x00000040 */

+#define SYSCFG_CFGR_CM7L                SYSCFG_CFGR_CM7L_Msk                   /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */

+#define SYSCFG_CFGR_DTCML_Pos           (13U)

+#define SYSCFG_CFGR_DTCML_Msk           (0x1UL << SYSCFG_CFGR_DTCML_Pos)       /*!< 0x00002000 */

+#define SYSCFG_CFGR_DTCML               SYSCFG_CFGR_DTCML_Msk                  /*!<DTCM double ECC error lock bit */

+#define SYSCFG_CFGR_ITCML_Pos           (14U)

+#define SYSCFG_CFGR_ITCML_Msk           (0x1UL << SYSCFG_CFGR_ITCML_Pos)       /*!< 0x00004000 */

+#define SYSCFG_CFGR_ITCML               SYSCFG_CFGR_ITCML_Msk                  /*!<ITCM double ECC error lock bit */

+/******************  Bit definition for SYSCFG_CCCSR register  ******************/

+#define SYSCFG_CCCSR_EN_Pos             (0U)

+#define SYSCFG_CCCSR_EN_Msk             (0x1UL << SYSCFG_CCCSR_EN_Pos)         /*!< 0x00000001 */

+#define SYSCFG_CCCSR_EN                 SYSCFG_CCCSR_EN_Msk                    /*!< I/O compensation cell enable */

+#define SYSCFG_CCCSR_CS_Pos             (1U)

+#define SYSCFG_CCCSR_CS_Msk             (0x1UL << SYSCFG_CCCSR_CS_Pos)         /*!< 0x00000002 */

+#define SYSCFG_CCCSR_CS                 SYSCFG_CCCSR_CS_Msk                    /*!< I/O compensation cell code selection */

+#define SYSCFG_CCCSR_CS_MMC_Pos         (3U)

+#define SYSCFG_CCCSR_CS_MMC_Msk         (0x1UL << SYSCFG_CCCSR_CS_MMC_Pos)         /*!< 0x00000004 */

+#define SYSCFG_CCCSR_CS_MMC             SYSCFG_CCCSR_CS_MMC_Msk                    /*!< I/O compensation cell code selection */

+#define SYSCFG_CCCSR_READY_Pos          (8U)

+#define SYSCFG_CCCSR_READY_Msk          (0x1UL << SYSCFG_CCCSR_READY_Pos)      /*!< 0x00000100 */

+#define SYSCFG_CCCSR_READY              SYSCFG_CCCSR_READY_Msk                 /*!< I/O compensation cell ready flag */

+#define SYSCFG_CCCSR_HSLV0_Pos           (16U)

+#define SYSCFG_CCCSR_HSLV0_Msk           (0x1UL << SYSCFG_CCCSR_HSLV0_Pos)       /*!< 0x00010000 */

+#define SYSCFG_CCCSR_HSLV0               SYSCFG_CCCSR_HSLV0_Msk                  /*!< High-speed at low-voltage */

+#define SYSCFG_CCCSR_HSLV1_Pos           (17U)

+#define SYSCFG_CCCSR_HSLV1_Msk           (0x1UL << SYSCFG_CCCSR_HSLV1_Pos)       /*!< 0x00020000 */

+#define SYSCFG_CCCSR_HSLV1               SYSCFG_CCCSR_HSLV1_Msk                  /*!< High-speed at low-voltage */

+#define SYSCFG_CCCSR_HSLV2_Pos           (18U)

+#define SYSCFG_CCCSR_HSLV2_Msk           (0x1UL << SYSCFG_CCCSR_HSLV2_Pos)       /*!< 0x00040000 */

+#define SYSCFG_CCCSR_HSLV2               SYSCFG_CCCSR_HSLV2_Msk                  /*!< High-speed at low-voltage */

+#define SYSCFG_CCCSR_HSLV3_Pos           (19U)

+#define SYSCFG_CCCSR_HSLV3_Msk           (0x1UL << SYSCFG_CCCSR_HSLV3_Pos)       /*!< 0x00080000 */

+#define SYSCFG_CCCSR_HSLV3               SYSCFG_CCCSR_HSLV3_Msk                  /*!< High-speed at low-voltage */

+/******************  Bit definition for SYSCFG_CCVR register  *******************/

+#define SYSCFG_CCVR_NCV_Pos             (0U)

+#define SYSCFG_CCVR_NCV_Msk             (0xFUL << SYSCFG_CCVR_NCV_Pos)         /*!< 0x0000000F */

+#define SYSCFG_CCVR_NCV                 SYSCFG_CCVR_NCV_Msk                    /*!< NMOS compensation value */

+#define SYSCFG_CCVR_PCV_Pos             (4U)

+#define SYSCFG_CCVR_PCV_Msk             (0xFUL << SYSCFG_CCVR_PCV_Pos)         /*!< 0x000000F0 */

+#define SYSCFG_CCVR_PCV                 SYSCFG_CCVR_PCV_Msk                    /*!< PMOS compensation value */

+

+/******************  Bit definition for SYSCFG_CCCR register  *******************/

+#define SYSCFG_CCCR_NCC_Pos             (0U)

+#define SYSCFG_CCCR_NCC_Msk             (0xFUL << SYSCFG_CCCR_NCC_Pos)         /*!< 0x0000000F */

+#define SYSCFG_CCCR_NCC                 SYSCFG_CCCR_NCC_Msk                    /*!< NMOS compensation code */

+#define SYSCFG_CCCR_PCC_Pos             (4U)

+#define SYSCFG_CCCR_PCC_Msk             (0xFUL << SYSCFG_CCCR_PCC_Pos)         /*!< 0x000000F0 */

+#define SYSCFG_CCCR_PCC                 SYSCFG_CCCR_PCC_Msk                    /*!< PMOS compensation code */

+#define SYSCFG_CCCR_NCC_MMC_Pos         (8U)

+#define SYSCFG_CCCR_NCC_MMC_Msk         (0xFUL << SYSCFG_CCCR_NCC_MMC_Pos)     /*!< 0x00000F00 */

+#define SYSCFG_CCCR_NCC_MMC             SYSCFG_CCCR_NCC_MMC_Msk                /*!< NMOS compensation code */

+#define SYSCFG_CCCR_PCC_MMC_Pos         (12U)

+#define SYSCFG_CCCR_PCC_MMC_Msk         (0xFUL << SYSCFG_CCCR_PCC_MMC_Pos)     /*!< 0x0000F000 */

+#define SYSCFG_CCCR_PCC_MMC             SYSCFG_CCCR_PCC_MMC_Msk                /*!< PMOS compensation code */

+/******************************************************************************/

+/*                                                                            */

+/*                    Digital Temperature Sensor (DTS)                        */

+/*                                                                            */

+/******************************************************************************/

+

+/******************  Bit definition for DTS_CFGR1 register  ******************/

+#define DTS_CFGR1_TS1_EN_Pos               (0U)

+#define DTS_CFGR1_TS1_EN_Msk               (0x1UL << DTS_CFGR1_TS1_EN_Pos) /*!< 0x00000001 */

+#define DTS_CFGR1_TS1_EN                   DTS_CFGR1_TS1_EN_Msk        /*!< DTS Enable */

+#define DTS_CFGR1_TS1_START_Pos            (4U)

+#define DTS_CFGR1_TS1_START_Msk            (0x1UL << DTS_CFGR1_TS1_START_Pos) /*!< 0x00000010 */

+#define DTS_CFGR1_TS1_START                DTS_CFGR1_TS1_START_Msk     /*!< Proceed to a frequency measurement on DTS */

+#define DTS_CFGR1_TS1_INTRIG_SEL_Pos       (8U)

+#define DTS_CFGR1_TS1_INTRIG_SEL_Msk       (0xFUL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000F00 */

+#define DTS_CFGR1_TS1_INTRIG_SEL           DTS_CFGR1_TS1_INTRIG_SEL_Msk /*!< Input triggers selection bits [3:0] for DTS */

+#define DTS_CFGR1_TS1_INTRIG_SEL_0         (0x1UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000100 */

+#define DTS_CFGR1_TS1_INTRIG_SEL_1         (0x2UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000200 */

+#define DTS_CFGR1_TS1_INTRIG_SEL_2         (0x4UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000400 */

+#define DTS_CFGR1_TS1_INTRIG_SEL_3         (0x8UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000800 */

+#define DTS_CFGR1_TS1_SMP_TIME_Pos         (16U)

+#define DTS_CFGR1_TS1_SMP_TIME_Msk         (0xFUL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x000F0000 */

+#define DTS_CFGR1_TS1_SMP_TIME             DTS_CFGR1_TS1_SMP_TIME_Msk  /*!< Sample time [3:0] for DTS */

+#define DTS_CFGR1_TS1_SMP_TIME_0           (0x1UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00010000 */

+#define DTS_CFGR1_TS1_SMP_TIME_1           (0x2UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00020000 */

+#define DTS_CFGR1_TS1_SMP_TIME_2           (0x4UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00040000 */

+#define DTS_CFGR1_TS1_SMP_TIME_3           (0x8UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00080000 */

+#define DTS_CFGR1_REFCLK_SEL_Pos           (20U)

+#define DTS_CFGR1_REFCLK_SEL_Msk           (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */

+#define DTS_CFGR1_REFCLK_SEL               DTS_CFGR1_REFCLK_SEL_Msk    /*!< Reference Clock Selection */

+#define DTS_CFGR1_Q_MEAS_OPT_Pos           (21U)

+#define DTS_CFGR1_Q_MEAS_OPT_Msk           (0x1UL << DTS_CFGR1_Q_MEAS_OPT_Pos) /*!< 0x00200000 */

+#define DTS_CFGR1_Q_MEAS_OPT               DTS_CFGR1_Q_MEAS_OPT_Msk    /*!< Quick measure option bit  */

+#define DTS_CFGR1_HSREF_CLK_DIV_Pos        (24U)

+#define DTS_CFGR1_HSREF_CLK_DIV_Msk        (0x7FUL << DTS_CFGR1_HSREF_CLK_DIV_Pos) /*!< 0x7F000000 */

+#define DTS_CFGR1_HSREF_CLK_DIV            DTS_CFGR1_HSREF_CLK_DIV_Msk /*!< High Speed Clock Divider Ratio [6:0]*/

+

+/******************  Bit definition for DTS_T0VALR1 register  ******************/

+#define DTS_T0VALR1_TS1_FMT0_Pos           (0U)

+#define DTS_T0VALR1_TS1_FMT0_Msk           (0xFFFFUL << DTS_T0VALR1_TS1_FMT0_Pos) /*!< 0x0000FFFF */

+#define DTS_T0VALR1_TS1_FMT0               DTS_T0VALR1_TS1_FMT0_Msk    /*!< Engineering value of the measured frequency at T0 for DTS */

+#define DTS_T0VALR1_TS1_T0_Pos             (16U)

+#define DTS_T0VALR1_TS1_T0_Msk             (0x3UL << DTS_T0VALR1_TS1_T0_Pos) /*!< 0x00030000 */

+#define DTS_T0VALR1_TS1_T0                 DTS_T0VALR1_TS1_T0_Msk      /*!< Engineering value of the DTSerature T0 for DTS */

+

+/******************  Bit definition for DTS_RAMPVALR register  ******************/

+#define DTS_RAMPVALR_TS1_RAMP_COEFF_Pos    (0U)

+#define DTS_RAMPVALR_TS1_RAMP_COEFF_Msk    (0xFFFFUL << DTS_RAMPVALR_TS1_RAMP_COEFF_Pos) /*!< 0x0000FFFF */

+#define DTS_RAMPVALR_TS1_RAMP_COEFF        DTS_RAMPVALR_TS1_RAMP_COEFF_Msk /*!< Engineering value of the ramp coefficient for DTS */

+

+/******************  Bit definition for DTS_ITR1 register      ******************/

+#define DTS_ITR1_TS1_LITTHD_Pos            (0U)

+#define DTS_ITR1_TS1_LITTHD_Msk            (0xFFFFUL << DTS_ITR1_TS1_LITTHD_Pos) /*!< 0x0000FFFF */

+#define DTS_ITR1_TS1_LITTHD                DTS_ITR1_TS1_LITTHD_Msk     /*!< Low interrupt threshold[15:0] for DTS */

+#define DTS_ITR1_TS1_HITTHD_Pos            (16U)

+#define DTS_ITR1_TS1_HITTHD_Msk            (0xFFFFUL << DTS_ITR1_TS1_HITTHD_Pos) /*!< 0xFFFF0000 */

+#define DTS_ITR1_TS1_HITTHD                DTS_ITR1_TS1_HITTHD_Msk     /*!< High interrupt threshold[15:0] for DTS */

+

+/******************  Bit definition for DTS_DR register        ******************/

+#define DTS_DR_TS1_MFREQ_Pos               (0U)

+#define DTS_DR_TS1_MFREQ_Msk               (0xFFFFUL << DTS_DR_TS1_MFREQ_Pos) /*!< 0x0000FFFF */

+#define DTS_DR_TS1_MFREQ                   DTS_DR_TS1_MFREQ_Msk        /*!< Measured Frequency[15:0] for DTS */

+

+/******************  Bit definition for DTS_SR register        ******************/

+#define DTS_SR_TS1_ITEF_Pos                (0U)

+#define DTS_SR_TS1_ITEF_Msk                (0x1UL << DTS_SR_TS1_ITEF_Pos) /*!< 0x00000001 */

+#define DTS_SR_TS1_ITEF                    DTS_SR_TS1_ITEF_Msk         /*!< Interrupt flag for end of measure for DTS */

+#define DTS_SR_TS1_ITLF_Pos                (1U)

+#define DTS_SR_TS1_ITLF_Msk                (0x1UL << DTS_SR_TS1_ITLF_Pos) /*!< 0x00000002 */

+#define DTS_SR_TS1_ITLF                    DTS_SR_TS1_ITLF_Msk         /*!< Interrupt flag for low threshold for DTS  */

+#define DTS_SR_TS1_ITHF_Pos                (2U)

+#define DTS_SR_TS1_ITHF_Msk                (0x1UL << DTS_SR_TS1_ITHF_Pos) /*!< 0x00000004 */

+#define DTS_SR_TS1_ITHF                    DTS_SR_TS1_ITHF_Msk         /*!< Interrupt flag for high threshold for DTS */

+#define DTS_SR_TS1_AITEF_Pos               (4U)

+#define DTS_SR_TS1_AITEF_Msk               (0x1UL << DTS_SR_TS1_AITEF_Pos) /*!< 0x00000010 */

+#define DTS_SR_TS1_AITEF                   DTS_SR_TS1_AITEF_Msk        /*!< Asynchronous interrupt flag for end of measure for DTS */

+#define DTS_SR_TS1_AITLF_Pos               (5U)

+#define DTS_SR_TS1_AITLF_Msk               (0x1UL << DTS_SR_TS1_AITLF_Pos) /*!< 0x00000020 */

+#define DTS_SR_TS1_AITLF                   DTS_SR_TS1_AITLF_Msk        /*!< Asynchronous interrupt flag for low threshold for DTS  */

+#define DTS_SR_TS1_AITHF_Pos               (6U)

+#define DTS_SR_TS1_AITHF_Msk               (0x1UL << DTS_SR_TS1_AITHF_Pos) /*!< 0x00000040 */

+#define DTS_SR_TS1_AITHF                   DTS_SR_TS1_AITHF_Msk        /*!< Asynchronous interrupt flag for high threshold for DTS */

+#define DTS_SR_TS1_RDY_Pos                 (15U)

+#define DTS_SR_TS1_RDY_Msk                 (0x1UL << DTS_SR_TS1_RDY_Pos) /*!< 0x00008000 */

+#define DTS_SR_TS1_RDY                     DTS_SR_TS1_RDY_Msk          /*!< DTS ready flag */

+

+/******************  Bit definition for DTS_ITENR register      ******************/

+#define DTS_ITENR_TS1_ITEEN_Pos            (0U)

+#define DTS_ITENR_TS1_ITEEN_Msk            (0x1UL << DTS_ITENR_TS1_ITEEN_Pos) /*!< 0x00000001 */

+#define DTS_ITENR_TS1_ITEEN                DTS_ITENR_TS1_ITEEN_Msk     /*!< Enable interrupt flag for end of measure for DTS */

+#define DTS_ITENR_TS1_ITLEN_Pos            (1U)

+#define DTS_ITENR_TS1_ITLEN_Msk            (0x1UL << DTS_ITENR_TS1_ITLEN_Pos) /*!< 0x00000002 */

+#define DTS_ITENR_TS1_ITLEN                DTS_ITENR_TS1_ITLEN_Msk     /*!< Enable interrupt flag for low threshold for DTS  */

+#define DTS_ITENR_TS1_ITHEN_Pos            (2U)

+#define DTS_ITENR_TS1_ITHEN_Msk            (0x1UL << DTS_ITENR_TS1_ITHEN_Pos) /*!< 0x00000004 */

+#define DTS_ITENR_TS1_ITHEN                DTS_ITENR_TS1_ITHEN_Msk     /*!< Enable interrupt flag for high threshold for DTS */

+#define DTS_ITENR_TS1_AITEEN_Pos           (4U)

+#define DTS_ITENR_TS1_AITEEN_Msk           (0x1UL << DTS_ITENR_TS1_AITEEN_Pos) /*!< 0x00000010 */

+#define DTS_ITENR_TS1_AITEEN               DTS_ITENR_TS1_AITEEN_Msk    /*!< Enable asynchronous interrupt flag for end of measure for DTS */

+#define DTS_ITENR_TS1_AITLEN_Pos           (5U)

+#define DTS_ITENR_TS1_AITLEN_Msk           (0x1UL << DTS_ITENR_TS1_AITLEN_Pos) /*!< 0x00000020 */

+#define DTS_ITENR_TS1_AITLEN               DTS_ITENR_TS1_AITLEN_Msk    /*!< Enable Asynchronous interrupt flag for low threshold for DTS  */

+#define DTS_ITENR_TS1_AITHEN_Pos           (6U)

+#define DTS_ITENR_TS1_AITHEN_Msk           (0x1UL << DTS_ITENR_TS1_AITHEN_Pos) /*!< 0x00000040 */

+#define DTS_ITENR_TS1_AITHEN               DTS_ITENR_TS1_AITHEN_Msk    /*!< Enable asynchronous interrupt flag for high threshold for DTS */

+

+/******************  Bit definition for DTS_ICIFR register      ******************/

+#define DTS_ICIFR_TS1_CITEF_Pos            (0U)

+#define DTS_ICIFR_TS1_CITEF_Msk            (0x1UL << DTS_ICIFR_TS1_CITEF_Pos) /*!< 0x00000001 */

+#define DTS_ICIFR_TS1_CITEF                DTS_ICIFR_TS1_CITEF_Msk     /*!< Clear the IT flag for End Of Measure for DTS */

+#define DTS_ICIFR_TS1_CITLF_Pos            (1U)

+#define DTS_ICIFR_TS1_CITLF_Msk            (0x1UL << DTS_ICIFR_TS1_CITLF_Pos) /*!< 0x00000002 */

+#define DTS_ICIFR_TS1_CITLF                DTS_ICIFR_TS1_CITLF_Msk     /*!< Clear the IT flag for low threshold for DTS  */

+#define DTS_ICIFR_TS1_CITHF_Pos            (2U)

+#define DTS_ICIFR_TS1_CITHF_Msk            (0x1UL << DTS_ICIFR_TS1_CITHF_Pos) /*!< 0x00000004 */

+#define DTS_ICIFR_TS1_CITHF                DTS_ICIFR_TS1_CITHF_Msk     /*!< Clear the IT flag for high threshold on DTS  */

+#define DTS_ICIFR_TS1_CAITEF_Pos           (4U)

+#define DTS_ICIFR_TS1_CAITEF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITEF_Pos) /*!< 0x00000010 */

+#define DTS_ICIFR_TS1_CAITEF               DTS_ICIFR_TS1_CAITEF_Msk    /*!< Clear the asynchronous IT flag for End Of Measure for DTS */

+#define DTS_ICIFR_TS1_CAITLF_Pos           (5U)

+#define DTS_ICIFR_TS1_CAITLF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITLF_Pos) /*!< 0x00000020 */

+#define DTS_ICIFR_TS1_CAITLF               DTS_ICIFR_TS1_CAITLF_Msk    /*!< Clear the asynchronous IT flag for low threshold for DTS  */

+#define DTS_ICIFR_TS1_CAITHF_Pos           (6U)

+#define DTS_ICIFR_TS1_CAITHF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITHF_Pos) /*!< 0x00000040 */

+#define DTS_ICIFR_TS1_CAITHF               DTS_ICIFR_TS1_CAITHF_Msk    /*!< Clear the asynchronous IT flag for high threshold on DTS  */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    TIM                                     */

+/*                                                                            */

+/******************************************************************************/

+#define TIM_BREAK_INPUT_SUPPORT             /*!<TIM Break input feature */

+

+/*******************  Bit definition for TIM_CR1 register  ********************/

+#define TIM_CR1_CEN_Pos           (0U)

+#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */

+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */

+#define TIM_CR1_UDIS_Pos          (1U)

+#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */

+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */

+#define TIM_CR1_URS_Pos           (2U)

+#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */

+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */

+#define TIM_CR1_OPM_Pos           (3U)

+#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */

+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */

+#define TIM_CR1_DIR_Pos           (4U)

+#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */

+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */

+

+#define TIM_CR1_CMS_Pos           (5U)

+#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */

+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */

+#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */

+#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */

+

+#define TIM_CR1_ARPE_Pos          (7U)

+#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */

+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */

+

+#define TIM_CR1_CKD_Pos           (8U)

+#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */

+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */

+#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */

+#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */

+

+#define TIM_CR1_UIFREMAP_Pos      (11U)

+#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */

+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */

+

+/*******************  Bit definition for TIM_CR2 register  ********************/

+#define TIM_CR2_CCPC_Pos          (0U)

+#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */

+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */

+#define TIM_CR2_CCUS_Pos          (2U)

+#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */

+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */

+#define TIM_CR2_CCDS_Pos          (3U)

+#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */

+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */

+

+#define TIM_CR2_MMS_Pos           (4U)

+#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */

+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */

+#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */

+#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */

+#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */

+

+#define TIM_CR2_TI1S_Pos          (7U)

+#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */

+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */

+#define TIM_CR2_OIS1_Pos          (8U)

+#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */

+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */

+#define TIM_CR2_OIS1N_Pos         (9U)

+#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */

+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */

+#define TIM_CR2_OIS2_Pos          (10U)

+#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */

+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */

+#define TIM_CR2_OIS2N_Pos         (11U)

+#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */

+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */

+#define TIM_CR2_OIS3_Pos          (12U)

+#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */

+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */

+#define TIM_CR2_OIS3N_Pos         (13U)

+#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */

+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */

+#define TIM_CR2_OIS4_Pos          (14U)

+#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */

+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */

+#define TIM_CR2_OIS5_Pos          (16U)

+#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */

+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */

+#define TIM_CR2_OIS6_Pos          (17U)

+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */

+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */

+

+#define TIM_CR2_MMS2_Pos          (20U)

+#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */

+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */

+#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */

+#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */

+#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */

+#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */

+

+/*******************  Bit definition for TIM_SMCR register  *******************/

+#define TIM_SMCR_SMS_Pos          (0U)

+#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */

+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */

+#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */

+#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */

+#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */

+#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */

+

+#define TIM_SMCR_TS_Pos           (4U)

+#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */

+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[4:0] bits (Trigger selection) */

+#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)                /*!< 0x00000010 */

+#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)                /*!< 0x00000020 */

+#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)                /*!< 0x00000040 */

+#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)                /*!< 0x00100000 */

+#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)                /*!< 0x00200000 */

+

+#define TIM_SMCR_MSM_Pos          (7U)

+#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */

+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */

+

+#define TIM_SMCR_ETF_Pos          (8U)

+#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */

+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */

+#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */

+#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */

+#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */

+#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */

+

+#define TIM_SMCR_ETPS_Pos         (12U)

+#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */

+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */

+#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */

+#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */

+

+#define TIM_SMCR_ECE_Pos          (14U)

+#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */

+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */

+#define TIM_SMCR_ETP_Pos          (15U)

+#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */

+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */

+

+/*******************  Bit definition for TIM_DIER register  *******************/

+#define TIM_DIER_UIE_Pos          (0U)

+#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */

+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */

+#define TIM_DIER_CC1IE_Pos        (1U)

+#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */

+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */

+#define TIM_DIER_CC2IE_Pos        (2U)

+#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */

+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */

+#define TIM_DIER_CC3IE_Pos        (3U)

+#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */

+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */

+#define TIM_DIER_CC4IE_Pos        (4U)

+#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */

+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */

+#define TIM_DIER_COMIE_Pos        (5U)

+#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */

+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */

+#define TIM_DIER_TIE_Pos          (6U)

+#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */

+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */

+#define TIM_DIER_BIE_Pos          (7U)

+#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */

+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */

+#define TIM_DIER_UDE_Pos          (8U)

+#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */

+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */

+#define TIM_DIER_CC1DE_Pos        (9U)

+#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */

+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */

+#define TIM_DIER_CC2DE_Pos        (10U)

+#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */

+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */

+#define TIM_DIER_CC3DE_Pos        (11U)

+#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */

+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */

+#define TIM_DIER_CC4DE_Pos        (12U)

+#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */

+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */

+#define TIM_DIER_COMDE_Pos        (13U)

+#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */

+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */

+#define TIM_DIER_TDE_Pos          (14U)

+#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */

+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */

+

+/********************  Bit definition for TIM_SR register  ********************/

+#define TIM_SR_UIF_Pos            (0U)

+#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */

+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */

+#define TIM_SR_CC1IF_Pos          (1U)

+#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */

+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */

+#define TIM_SR_CC2IF_Pos          (2U)

+#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */

+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */

+#define TIM_SR_CC3IF_Pos          (3U)

+#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */

+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */

+#define TIM_SR_CC4IF_Pos          (4U)

+#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */

+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */

+#define TIM_SR_COMIF_Pos          (5U)

+#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */

+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */

+#define TIM_SR_TIF_Pos            (6U)

+#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */

+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */

+#define TIM_SR_BIF_Pos            (7U)

+#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */

+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */

+#define TIM_SR_B2IF_Pos           (8U)

+#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */

+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break2 interrupt Flag */

+#define TIM_SR_CC1OF_Pos          (9U)

+#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */

+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */

+#define TIM_SR_CC2OF_Pos          (10U)

+#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */

+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */

+#define TIM_SR_CC3OF_Pos          (11U)

+#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */

+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */

+#define TIM_SR_CC4OF_Pos          (12U)

+#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */

+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */

+#define TIM_SR_CC5IF_Pos          (16U)

+#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */

+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */

+#define TIM_SR_CC6IF_Pos          (17U)

+#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */

+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */

+#define TIM_SR_SBIF_Pos           (13U)

+#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */

+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!< System Break Flag */

+

+/*******************  Bit definition for TIM_EGR register  ********************/

+#define TIM_EGR_UG_Pos            (0U)

+#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */

+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */

+#define TIM_EGR_CC1G_Pos          (1U)

+#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */

+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */

+#define TIM_EGR_CC2G_Pos          (2U)

+#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */

+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */

+#define TIM_EGR_CC3G_Pos          (3U)

+#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */

+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */

+#define TIM_EGR_CC4G_Pos          (4U)

+#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */

+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */

+#define TIM_EGR_COMG_Pos          (5U)

+#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */

+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */

+#define TIM_EGR_TG_Pos            (6U)

+#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */

+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */

+#define TIM_EGR_BG_Pos            (7U)

+#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */

+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */

+#define TIM_EGR_B2G_Pos           (8U)

+#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */

+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break Generation */

+

+

+/******************  Bit definition for TIM_CCMR1 register  *******************/

+#define TIM_CCMR1_CC1S_Pos        (0U)

+#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */

+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */

+#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */

+#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */

+

+#define TIM_CCMR1_OC1FE_Pos       (2U)

+#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */

+#define TIM_CCMR1_OC1PE_Pos       (3U)

+#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */

+

+#define TIM_CCMR1_OC1M_Pos        (4U)

+#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */

+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */

+#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */

+#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */

+#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */

+#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR1_OC1CE_Pos       (7U)

+#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */

+

+#define TIM_CCMR1_CC2S_Pos        (8U)

+#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */

+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */

+#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */

+#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */

+

+#define TIM_CCMR1_OC2FE_Pos       (10U)

+#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */

+#define TIM_CCMR1_OC2PE_Pos       (11U)

+#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */

+

+#define TIM_CCMR1_OC2M_Pos        (12U)

+#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */

+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */

+#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */

+#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */

+#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */

+#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */

+

+#define TIM_CCMR1_OC2CE_Pos       (15U)

+#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */

+

+/*----------------------------------------------------------------------------*/

+

+#define TIM_CCMR1_IC1PSC_Pos      (2U)

+#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */

+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */

+#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */

+

+#define TIM_CCMR1_IC1F_Pos        (4U)

+#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */

+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */

+#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */

+

+#define TIM_CCMR1_IC2PSC_Pos      (10U)

+#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */

+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */

+#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */

+

+#define TIM_CCMR1_IC2F_Pos        (12U)

+#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */

+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */

+#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */

+

+/******************  Bit definition for TIM_CCMR2 register  *******************/

+#define TIM_CCMR2_CC3S_Pos        (0U)

+#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */

+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */

+#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */

+#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */

+

+#define TIM_CCMR2_OC3FE_Pos       (2U)

+#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */

+#define TIM_CCMR2_OC3PE_Pos       (3U)

+#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */

+

+#define TIM_CCMR2_OC3M_Pos        (4U)

+#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */

+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */

+#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR2_OC3CE_Pos       (7U)

+#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */

+

+#define TIM_CCMR2_CC4S_Pos        (8U)

+#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */

+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */

+#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */

+#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */

+

+#define TIM_CCMR2_OC4FE_Pos       (10U)

+#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */

+#define TIM_CCMR2_OC4PE_Pos       (11U)

+#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */

+

+#define TIM_CCMR2_OC4M_Pos        (12U)

+#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */

+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */

+#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */

+

+#define TIM_CCMR2_OC4CE_Pos       (15U)

+#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */

+

+/*----------------------------------------------------------------------------*/

+

+#define TIM_CCMR2_IC3PSC_Pos      (2U)

+#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */

+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */

+#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */

+

+#define TIM_CCMR2_IC3F_Pos        (4U)

+#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */

+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */

+#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */

+

+#define TIM_CCMR2_IC4PSC_Pos      (10U)

+#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */

+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */

+#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */

+

+#define TIM_CCMR2_IC4F_Pos        (12U)

+#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */

+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */

+#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */

+

+/*******************  Bit definition for TIM_CCER register  *******************/

+#define TIM_CCER_CC1E_Pos         (0U)

+#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */

+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */

+#define TIM_CCER_CC1P_Pos         (1U)

+#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */

+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */

+#define TIM_CCER_CC1NE_Pos        (2U)

+#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */

+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */

+#define TIM_CCER_CC1NP_Pos        (3U)

+#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */

+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */

+#define TIM_CCER_CC2E_Pos         (4U)

+#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */

+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */

+#define TIM_CCER_CC2P_Pos         (5U)

+#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */

+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */

+#define TIM_CCER_CC2NE_Pos        (6U)

+#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */

+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */

+#define TIM_CCER_CC2NP_Pos        (7U)

+#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */

+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */

+#define TIM_CCER_CC3E_Pos         (8U)

+#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */

+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */

+#define TIM_CCER_CC3P_Pos         (9U)

+#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */

+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */

+#define TIM_CCER_CC3NE_Pos        (10U)

+#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */

+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */

+#define TIM_CCER_CC3NP_Pos        (11U)

+#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */

+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */

+#define TIM_CCER_CC4E_Pos         (12U)

+#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */

+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */

+#define TIM_CCER_CC4P_Pos         (13U)

+#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */

+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */

+#define TIM_CCER_CC4NP_Pos        (15U)

+#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */

+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */

+#define TIM_CCER_CC5E_Pos         (16U)

+#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */

+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */

+#define TIM_CCER_CC5P_Pos         (17U)

+#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */

+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */

+#define TIM_CCER_CC6E_Pos         (20U)

+#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */

+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */

+#define TIM_CCER_CC6P_Pos         (21U)

+#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */

+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */

+/*******************  Bit definition for TIM_CNT register  ********************/

+#define TIM_CNT_CNT_Pos           (0U)

+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */

+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */

+#define TIM_CNT_UIFCPY_Pos        (31U)

+#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */

+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy */

+/*******************  Bit definition for TIM_PSC register  ********************/

+#define TIM_PSC_PSC_Pos           (0U)

+#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */

+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */

+

+/*******************  Bit definition for TIM_ARR register  ********************/

+#define TIM_ARR_ARR_Pos           (0U)

+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */

+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */

+

+/*******************  Bit definition for TIM_RCR register  ********************/

+#define TIM_RCR_REP_Pos           (0U)

+#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                  /*!< 0x000000FF */

+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */

+

+/*******************  Bit definition for TIM_CCR1 register  *******************/

+#define TIM_CCR1_CCR1_Pos         (0U)

+#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */

+

+/*******************  Bit definition for TIM_CCR2 register  *******************/

+#define TIM_CCR2_CCR2_Pos         (0U)

+#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */

+

+/*******************  Bit definition for TIM_CCR3 register  *******************/

+#define TIM_CCR3_CCR3_Pos         (0U)

+#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */

+

+/*******************  Bit definition for TIM_CCR4 register  *******************/

+#define TIM_CCR4_CCR4_Pos         (0U)

+#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */

+

+/*******************  Bit definition for TIM_CCR5 register  *******************/

+#define TIM_CCR5_CCR5_Pos         (0U)

+#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */

+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */

+#define TIM_CCR5_GC5C1_Pos        (29U)

+#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */

+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */

+#define TIM_CCR5_GC5C2_Pos        (30U)

+#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */

+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */

+#define TIM_CCR5_GC5C3_Pos        (31U)

+#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */

+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */

+

+/*******************  Bit definition for TIM_CCR6 register  *******************/

+#define TIM_CCR6_CCR6_Pos         (0U)

+#define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */

+

+/*******************  Bit definition for TIM_BDTR register  *******************/

+#define TIM_BDTR_DTG_Pos          (0U)

+#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */

+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */

+#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */

+#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */

+#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */

+#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */

+#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */

+#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */

+#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */

+#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */

+

+#define TIM_BDTR_LOCK_Pos         (8U)

+#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */

+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */

+#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */

+#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */

+

+#define TIM_BDTR_OSSI_Pos         (10U)

+#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */

+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */

+#define TIM_BDTR_OSSR_Pos         (11U)

+#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */

+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */

+#define TIM_BDTR_BKE_Pos          (12U)

+#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */

+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break1 */

+#define TIM_BDTR_BKP_Pos          (13U)

+#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */

+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break1 */

+#define TIM_BDTR_AOE_Pos          (14U)

+#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */

+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */

+#define TIM_BDTR_MOE_Pos          (15U)

+#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */

+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */

+

+#define TIM_BDTR_BKF_Pos          (16U)

+#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */

+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break1 */

+#define TIM_BDTR_BK2F_Pos         (20U)

+#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */

+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break2 */

+

+#define TIM_BDTR_BK2E_Pos         (24U)

+#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */

+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break2 */

+#define TIM_BDTR_BK2P_Pos         (25U)

+#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */

+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */

+

+/*******************  Bit definition for TIM_DCR register  ********************/

+#define TIM_DCR_DBA_Pos           (0U)

+#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */

+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */

+#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */

+#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */

+#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */

+#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */

+#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */

+

+#define TIM_DCR_DBL_Pos           (8U)

+#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */

+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */

+#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */

+#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */

+#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */

+#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */

+#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */

+

+/*******************  Bit definition for TIM_DMAR register  *******************/

+#define TIM_DMAR_DMAB_Pos         (0U)

+#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */

+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */

+

+/******************  Bit definition for TIM_CCMR3 register  *******************/

+#define TIM_CCMR3_OC5FE_Pos       (2U)

+#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */

+#define TIM_CCMR3_OC5PE_Pos       (3U)

+#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */

+

+#define TIM_CCMR3_OC5M_Pos        (4U)

+#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */

+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */

+#define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR3_OC5CE_Pos       (7U)

+#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */

+

+#define TIM_CCMR3_OC6FE_Pos       (10U)

+#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 4 Fast enable */

+#define TIM_CCMR3_OC6PE_Pos       (11U)

+#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */

+

+#define TIM_CCMR3_OC6M_Pos        (12U)

+#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */

+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */

+#define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */

+

+#define TIM_CCMR3_OC6CE_Pos       (15U)

+#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 4 Clear Enable */

+/*******************  Bit definition for TIM1_AF1 register  *********************/

+#define TIM1_AF1_BKINE_Pos        (0U)

+#define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */

+#define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */

+#define TIM1_AF1_BKCMP1E_Pos      (1U)

+#define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */

+#define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM1_AF1_BKCMP2E_Pos      (2U)

+#define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */

+#define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit */

+#define TIM1_AF1_BKDF1BK0E_Pos    (8U)

+#define TIM1_AF1_BKDF1BK0E_Msk    (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)            /*!< 0x00000100 */

+#define TIM1_AF1_BKDF1BK0E        TIM1_AF1_BKDF1BK0E_Msk                       /*!<BKDF1BK0E Break input DFSDM Break 0 */

+#define TIM1_AF1_BKINP_Pos        (9U)

+#define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */

+#define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */

+#define TIM1_AF1_BKCMP1P_Pos      (10U)

+#define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */

+#define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM1_AF1_BKCMP2P_Pos      (11U)

+#define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */

+#define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */

+

+#define TIM1_AF1_ETRSEL_Pos       (14U)

+#define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */

+#define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */

+#define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00004000 */

+#define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00008000 */

+#define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00010000 */

+#define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM1_AF2 register  *********************/

+#define TIM1_AF2_BK2INE_Pos       (0U)

+#define TIM1_AF2_BK2INE_Msk       (0x1UL << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */

+#define TIM1_AF2_BK2INE           TIM1_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */

+#define TIM1_AF2_BK2CMP1E_Pos     (1U)

+#define TIM1_AF2_BK2CMP1E_Msk     (0x1UL << TIM1_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */

+#define TIM1_AF2_BK2CMP1E         TIM1_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */

+#define TIM1_AF2_BK2CMP2E_Pos     (2U)

+#define TIM1_AF2_BK2CMP2E_Msk     (0x1UL << TIM1_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */

+#define TIM1_AF2_BK2CMP2E         TIM1_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */

+#define TIM1_AF2_BK2DFBK1E_Pos    (8U)

+#define TIM1_AF2_BK2DFBK1E_Msk    (0x1UL << TIM1_AF2_BK2DFBK1E_Pos)            /*!< 0x00000100 */

+#define TIM1_AF2_BK2DFBK1E        TIM1_AF2_BK2DFBK1E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 1 */

+#define TIM1_AF2_BK2INP_Pos       (9U)

+#define TIM1_AF2_BK2INP_Msk       (0x1UL << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */

+#define TIM1_AF2_BK2INP           TIM1_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */

+#define TIM1_AF2_BK2CMP1P_Pos     (10U)

+#define TIM1_AF2_BK2CMP1P_Msk     (0x1UL << TIM1_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */

+#define TIM1_AF2_BK2CMP1P         TIM1_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */

+#define TIM1_AF2_BK2CMP2P_Pos     (11U)

+#define TIM1_AF2_BK2CMP2P_Msk     (0x1UL << TIM1_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */

+#define TIM1_AF2_BK2CMP2P         TIM1_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */

+

+/*******************  Bit definition for TIM_TISEL register  *********************/

+#define TIM_TISEL_TI1SEL_Pos      (0U)

+#define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */

+#define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/

+#define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000001 */

+#define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000002 */

+#define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000004 */

+#define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000008 */

+

+#define TIM_TISEL_TI2SEL_Pos      (8U)

+#define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */

+#define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/

+#define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000100 */

+#define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000200 */

+#define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000400 */

+#define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000800 */

+

+#define TIM_TISEL_TI3SEL_Pos      (16U)

+#define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */

+#define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/

+#define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00010000 */

+#define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00020000 */

+#define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00040000 */

+#define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00080000 */

+

+#define TIM_TISEL_TI4SEL_Pos      (24U)

+#define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */

+#define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/

+#define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x01000000 */

+#define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x02000000 */

+#define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x04000000 */

+#define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x08000000 */

+

+/*******************  Bit definition for TIM8_AF1 register  *********************/

+#define TIM8_AF1_BKINE_Pos        (0U)

+#define TIM8_AF1_BKINE_Msk        (0x1UL << TIM8_AF1_BKINE_Pos)                /*!< 0x00000001 */

+#define TIM8_AF1_BKINE            TIM8_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */

+#define TIM8_AF1_BKCMP1E_Pos      (1U)

+#define TIM8_AF1_BKCMP1E_Msk      (0x1UL << TIM8_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */

+#define TIM8_AF1_BKCMP1E          TIM8_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM8_AF1_BKCMP2E_Pos      (2U)

+#define TIM8_AF1_BKCMP2E_Msk      (0x1UL << TIM8_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */

+#define TIM8_AF1_BKCMP2E          TIM8_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM8_AF1_BKDFBK2E_Pos     (8U)

+#define TIM8_AF1_BKDFBK2E_Msk     (0x1UL << TIM8_AF1_BKDFBK2E_Pos)             /*!< 0x00000100 */

+#define TIM8_AF1_BKDFBK2E         TIM8_AF1_BKDFBK2E_Msk                        /*!<BKDFBK2E Break input DFSDM Break 2 */

+#define TIM8_AF1_BKINP_Pos        (9U)

+#define TIM8_AF1_BKINP_Msk        (0x1UL << TIM8_AF1_BKINP_Pos)                /*!< 0x00000200 */

+#define TIM8_AF1_BKINP            TIM8_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */

+#define TIM8_AF1_BKCMP1P_Pos      (10U)

+#define TIM8_AF1_BKCMP1P_Msk      (0x1UL << TIM8_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */

+#define TIM8_AF1_BKCMP1P          TIM8_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM8_AF1_BKCMP2P_Pos      (11U)

+#define TIM8_AF1_BKCMP2P_Msk      (0x1UL << TIM8_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */

+#define TIM8_AF1_BKCMP2P          TIM8_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */

+

+#define TIM8_AF1_ETRSEL_Pos       (14U)

+#define TIM8_AF1_ETRSEL_Msk       (0xFUL << TIM8_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */

+#define TIM8_AF1_ETRSEL           TIM8_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */

+#define TIM8_AF1_ETRSEL_0         (0x1UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00004000 */

+#define TIM8_AF1_ETRSEL_1         (0x2UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00008000 */

+#define TIM8_AF1_ETRSEL_2         (0x4UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00010000 */

+#define TIM8_AF1_ETRSEL_3         (0x8UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00020000 */

+/*******************  Bit definition for TIM8_AF2 register  *********************/

+#define TIM8_AF2_BK2INE_Pos       (0U)

+#define TIM8_AF2_BK2INE_Msk       (0x1UL << TIM8_AF2_BK2INE_Pos)               /*!< 0x00000001 */

+#define TIM8_AF2_BK2INE           TIM8_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */

+#define TIM8_AF2_BK2CMP1E_Pos     (1U)

+#define TIM8_AF2_BK2CMP1E_Msk     (0x1UL << TIM8_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */

+#define TIM8_AF2_BK2CMP1E         TIM8_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */

+#define TIM8_AF2_BK2CMP2E_Pos     (2U)

+#define TIM8_AF2_BK2CMP2E_Msk     (0x1UL << TIM8_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */

+#define TIM8_AF2_BK2CMP2E         TIM8_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */

+#define TIM8_AF2_BK2DFBK3E_Pos    (8U)

+#define TIM8_AF2_BK2DFBK3E_Msk    (0x1UL << TIM8_AF2_BK2DFBK3E_Pos)            /*!< 0x00000100 */

+#define TIM8_AF2_BK2DFBK3E        TIM8_AF2_BK2DFBK3E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 3 */

+#define TIM8_AF2_BK2INP_Pos       (9U)

+#define TIM8_AF2_BK2INP_Msk       (0x1UL << TIM8_AF2_BK2INP_Pos)               /*!< 0x00000200 */

+#define TIM8_AF2_BK2INP           TIM8_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */

+#define TIM8_AF2_BK2CMP1P_Pos     (10U)

+#define TIM8_AF2_BK2CMP1P_Msk     (0x1UL << TIM8_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */

+#define TIM8_AF2_BK2CMP1P         TIM8_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */

+#define TIM8_AF2_BK2CMP2P_Pos     (11U)

+#define TIM8_AF2_BK2CMP2P_Msk     (0x1UL << TIM8_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */

+#define TIM8_AF2_BK2CMP2P         TIM8_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */

+

+/*******************  Bit definition for TIM2_AF1 register  *********************/

+#define TIM2_AF1_ETRSEL_Pos      (14U)

+#define TIM2_AF1_ETRSEL_Msk      (0xFUL << TIM2_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM2_AF1_ETRSEL          TIM2_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */

+#define TIM2_AF1_ETRSEL_0        (0x1UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM2_AF1_ETRSEL_1        (0x2UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM2_AF1_ETRSEL_2        (0x4UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM2_AF1_ETRSEL_3        (0x8UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM3_AF1 register  *********************/

+#define TIM3_AF1_ETRSEL_Pos      (14U)

+#define TIM3_AF1_ETRSEL_Msk      (0xFUL << TIM3_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM3_AF1_ETRSEL          TIM3_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */

+#define TIM3_AF1_ETRSEL_0        (0x1UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM3_AF1_ETRSEL_1        (0x2UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM3_AF1_ETRSEL_2        (0x4UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM3_AF1_ETRSEL_3        (0x8UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM5_AF1 register  *********************/

+#define TIM5_AF1_ETRSEL_Pos      (14U)

+#define TIM5_AF1_ETRSEL_Msk      (0xFUL << TIM5_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM5_AF1_ETRSEL          TIM5_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */

+#define TIM5_AF1_ETRSEL_0        (0x1UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM5_AF1_ETRSEL_1        (0x2UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM5_AF1_ETRSEL_2        (0x4UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM5_AF1_ETRSEL_3        (0x8UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM15_AF1 register  *********************/

+#define TIM15_AF1_BKINE_Pos        (0U)

+#define TIM15_AF1_BKINE_Msk        (0x1UL << TIM15_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM15_AF1_BKINE            TIM15_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM15_AF1_BKCMP1E_Pos      (1U)

+#define TIM15_AF1_BKCMP1E_Msk      (0x1UL << TIM15_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM15_AF1_BKCMP1E          TIM15_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM15_AF1_BKCMP2E_Pos      (2U)

+#define TIM15_AF1_BKCMP2E_Msk      (0x1UL << TIM15_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM15_AF1_BKCMP2E          TIM15_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM15_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM15_AF1_BKDF1BK2E_Msk    (0x1UL << TIM15_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM15_AF1_BKDF1BK2E        TIM15_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[0] enable */

+#define TIM15_AF1_BKINP_Pos        (9U)

+#define TIM15_AF1_BKINP_Msk        (0x1UL << TIM15_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM15_AF1_BKINP            TIM15_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM15_AF1_BKCMP1P_Pos      (10U)

+#define TIM15_AF1_BKCMP1P_Msk      (0x1UL << TIM15_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM15_AF1_BKCMP1P          TIM15_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM15_AF1_BKCMP2P_Pos      (11U)

+#define TIM15_AF1_BKCMP2P_Msk      (0x1UL << TIM15_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM15_AF1_BKCMP2P          TIM15_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/*******************  Bit definition for TIM16_ register  *********************/

+#define TIM16_AF1_BKINE_Pos        (0U)

+#define TIM16_AF1_BKINE_Msk        (0x1UL << TIM16_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM16_AF1_BKINE            TIM16_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM16_AF1_BKCMP1E_Pos      (1U)

+#define TIM16_AF1_BKCMP1E_Msk      (0x1UL << TIM16_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM16_AF1_BKCMP1E          TIM16_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM16_AF1_BKCMP2E_Pos      (2U)

+#define TIM16_AF1_BKCMP2E_Msk      (0x1UL << TIM16_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM16_AF1_BKCMP2E          TIM16_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM16_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM16_AF1_BKDF1BK2E_Msk    (0x1UL << TIM16_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM16_AF1_BKDF1BK2E        TIM16_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[1] enable */

+#define TIM16_AF1_BKINP_Pos        (9U)

+#define TIM16_AF1_BKINP_Msk        (0x1UL << TIM16_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM16_AF1_BKINP            TIM16_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM16_AF1_BKCMP1P_Pos      (10U)

+#define TIM16_AF1_BKCMP1P_Msk      (0x1UL << TIM16_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM16_AF1_BKCMP1P          TIM16_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM16_AF1_BKCMP2P_Pos      (11U)

+#define TIM16_AF1_BKCMP2P_Msk      (0x1UL << TIM16_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM16_AF1_BKCMP2P          TIM16_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/*******************  Bit definition for TIM17_AF1 register  *********************/

+#define TIM17_AF1_BKINE_Pos        (0U)

+#define TIM17_AF1_BKINE_Msk        (0x1UL << TIM17_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM17_AF1_BKINE            TIM17_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM17_AF1_BKCMP1E_Pos      (1U)

+#define TIM17_AF1_BKCMP1E_Msk      (0x1UL << TIM17_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM17_AF1_BKCMP1E          TIM17_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM17_AF1_BKCMP2E_Pos      (2U)

+#define TIM17_AF1_BKCMP2E_Msk      (0x1UL << TIM17_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM17_AF1_BKCMP2E          TIM17_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM17_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM17_AF1_BKDF1BK2E_Msk    (0x1UL << TIM17_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM17_AF1_BKDF1BK2E        TIM17_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[2] enable */

+#define TIM17_AF1_BKINP_Pos        (9U)

+#define TIM17_AF1_BKINP_Msk        (0x1UL << TIM17_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM17_AF1_BKINP            TIM17_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM17_AF1_BKCMP1P_Pos      (10U)

+#define TIM17_AF1_BKCMP1P_Msk      (0x1UL << TIM17_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM17_AF1_BKCMP1P          TIM17_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM17_AF1_BKCMP2P_Pos      (11U)

+#define TIM17_AF1_BKCMP2P_Msk      (0x1UL << TIM17_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM17_AF1_BKCMP2P          TIM17_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Low Power Timer (LPTTIM)                           */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for LPTIM_ISR register  *******************/

+#define LPTIM_ISR_CMPM_Pos          (0U)

+#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */

+#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */

+#define LPTIM_ISR_ARRM_Pos          (1U)

+#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */

+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */

+#define LPTIM_ISR_EXTTRIG_Pos       (2U)

+#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */

+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */

+#define LPTIM_ISR_CMPOK_Pos         (3U)

+#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */

+#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */

+#define LPTIM_ISR_ARROK_Pos         (4U)

+#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */

+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */

+#define LPTIM_ISR_UP_Pos            (5U)

+#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */

+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */

+#define LPTIM_ISR_DOWN_Pos          (6U)

+#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */

+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */

+

+/******************  Bit definition for LPTIM_ICR register  *******************/

+#define LPTIM_ICR_CMPMCF_Pos        (0U)

+#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */

+#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */

+#define LPTIM_ICR_ARRMCF_Pos        (1U)

+#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */

+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */

+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)

+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */

+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */

+#define LPTIM_ICR_CMPOKCF_Pos       (3U)

+#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */

+#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */

+#define LPTIM_ICR_ARROKCF_Pos       (4U)

+#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */

+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */

+#define LPTIM_ICR_UPCF_Pos          (5U)

+#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */

+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */

+#define LPTIM_ICR_DOWNCF_Pos        (6U)

+#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */

+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */

+

+/******************  Bit definition for LPTIM_IER register ********************/

+#define LPTIM_IER_CMPMIE_Pos        (0U)

+#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */

+#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */

+#define LPTIM_IER_ARRMIE_Pos        (1U)

+#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */

+#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */

+#define LPTIM_IER_EXTTRIGIE_Pos     (2U)

+#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */

+#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */

+#define LPTIM_IER_CMPOKIE_Pos       (3U)

+#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */

+#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */

+#define LPTIM_IER_ARROKIE_Pos       (4U)

+#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */

+#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */

+#define LPTIM_IER_UPIE_Pos          (5U)

+#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */

+#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */

+#define LPTIM_IER_DOWNIE_Pos        (6U)

+#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */

+#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */

+

+/******************  Bit definition for LPTIM_CFGR register *******************/

+#define LPTIM_CFGR_CKSEL_Pos        (0U)

+#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */

+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */

+

+#define LPTIM_CFGR_CKPOL_Pos        (1U)

+#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */

+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */

+#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */

+#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */

+

+#define LPTIM_CFGR_CKFLT_Pos        (3U)

+#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */

+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */

+#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */

+#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */

+

+#define LPTIM_CFGR_TRGFLT_Pos       (6U)

+#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */

+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */

+#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */

+#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */

+

+#define LPTIM_CFGR_PRESC_Pos        (9U)

+#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */

+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */

+#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */

+#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */

+#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */

+

+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)

+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */

+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */

+#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */

+#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */

+#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */

+

+#define LPTIM_CFGR_TRIGEN_Pos       (17U)

+#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */

+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */

+#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */

+#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */

+

+#define LPTIM_CFGR_TIMOUT_Pos       (19U)

+#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */

+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */

+#define LPTIM_CFGR_WAVE_Pos         (20U)

+#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */

+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */

+#define LPTIM_CFGR_WAVPOL_Pos       (21U)

+#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */

+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */

+#define LPTIM_CFGR_PRELOAD_Pos      (22U)

+#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */

+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */

+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)

+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */

+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */

+#define LPTIM_CFGR_ENC_Pos          (24U)

+#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */

+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */

+

+/******************  Bit definition for LPTIM_CR register  ********************/

+#define LPTIM_CR_ENABLE_Pos         (0U)

+#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */

+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */

+#define LPTIM_CR_SNGSTRT_Pos        (1U)

+#define LPTIM_CR_SNGSTRT_Msk        (0x40001UL << LPTIM_CR_SNGSTRT_Pos)        /*!< 0x00080002 */

+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */

+#define LPTIM_CR_CNTSTRT_Pos        (2U)

+#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */

+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */

+#define LPTIM_CR_COUNTRST_Pos       (3U)

+#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */

+#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Timer Counter reset in synchronous mode*/

+#define LPTIM_CR_RSTARE_Pos         (4U)

+#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */

+#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Timer Counter reset after read enable (asynchronously)*/

+

+

+/******************  Bit definition for LPTIM_CMP register  *******************/

+#define LPTIM_CMP_CMP_Pos           (0U)

+#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */

+

+/******************  Bit definition for LPTIM_ARR register  *******************/

+#define LPTIM_ARR_ARR_Pos           (0U)

+#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */

+

+/******************  Bit definition for LPTIM_CNT register  *******************/

+#define LPTIM_CNT_CNT_Pos           (0U)

+#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */

+

+/******************  Bit definition for LPTIM_CFGR2 register  *****************/

+#define LPTIM_CFGR2_IN1SEL_Pos      (0U)

+#define LPTIM_CFGR2_IN1SEL_Msk      (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000003 */

+#define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< IN1SEL[1:0] bits (Remap selection) */

+#define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000001 */

+#define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000002 */

+#define LPTIM_CFGR2_IN2SEL_Pos      (4U)

+#define LPTIM_CFGR2_IN2SEL_Msk      (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000030 */

+#define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< IN2SEL[5:4] bits (Remap selection) */

+#define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000010 */

+#define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000020 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    OCTOSPI                                 */

+/*                                                                            */

+/******************************************************************************/

+/*****************  Bit definition for OCTOSPI_CR register  *******************/

+#define OCTOSPI_CR_EN_Pos              (0U)

+#define OCTOSPI_CR_EN_Msk              (0x1UL << OCTOSPI_CR_EN_Pos)             /*!< 0x00000001 */

+#define OCTOSPI_CR_EN                  OCTOSPI_CR_EN_Msk                       /*!< Enable */

+#define OCTOSPI_CR_ABORT_Pos           (1U)

+#define OCTOSPI_CR_ABORT_Msk           (0x1UL << OCTOSPI_CR_ABORT_Pos)          /*!< 0x00000002 */

+#define OCTOSPI_CR_ABORT               OCTOSPI_CR_ABORT_Msk                    /*!< Abort request */

+#define OCTOSPI_CR_DMAEN_Pos           (2U)

+#define OCTOSPI_CR_DMAEN_Msk           (0x1UL << OCTOSPI_CR_DMAEN_Pos)          /*!< 0x00000004 */

+#define OCTOSPI_CR_DMAEN               OCTOSPI_CR_DMAEN_Msk                    /*!< DMA Enable */

+#define OCTOSPI_CR_TCEN_Pos            (3U)

+#define OCTOSPI_CR_TCEN_Msk            (0x1UL << OCTOSPI_CR_TCEN_Pos)           /*!< 0x00000008 */

+#define OCTOSPI_CR_TCEN                OCTOSPI_CR_TCEN_Msk                     /*!< Timeout Counter Enable */

+#define OCTOSPI_CR_DQM_Pos             (6U)

+#define OCTOSPI_CR_DQM_Msk             (0x1UL << OCTOSPI_CR_DQM_Pos)            /*!< 0x00000040 */

+#define OCTOSPI_CR_DQM                 OCTOSPI_CR_DQM_Msk                      /*!< Dual-Quad Mode */

+#define OCTOSPI_CR_FSEL_Pos            (7U)

+#define OCTOSPI_CR_FSEL_Msk            (0x1UL << OCTOSPI_CR_FSEL_Pos)           /*!< 0x00000080 */

+#define OCTOSPI_CR_FSEL                OCTOSPI_CR_FSEL_Msk                     /*!< Flash Select */

+#define OCTOSPI_CR_FTHRES_Pos          (8U)

+#define OCTOSPI_CR_FTHRES_Msk          (0x1FUL << OCTOSPI_CR_FTHRES_Pos)        /*!< 0x00001F00 */

+#define OCTOSPI_CR_FTHRES              OCTOSPI_CR_FTHRES_Msk                   /*!< FIFO Threshold Level */

+#define OCTOSPI_CR_TEIE_Pos            (16U)

+#define OCTOSPI_CR_TEIE_Msk            (0x1UL << OCTOSPI_CR_TEIE_Pos)           /*!< 0x00010000 */

+#define OCTOSPI_CR_TEIE                OCTOSPI_CR_TEIE_Msk                     /*!< Transfer Error Interrupt Enable */

+#define OCTOSPI_CR_TCIE_Pos            (17U)

+#define OCTOSPI_CR_TCIE_Msk            (0x1UL << OCTOSPI_CR_TCIE_Pos)           /*!< 0x00020000 */

+#define OCTOSPI_CR_TCIE                OCTOSPI_CR_TCIE_Msk                     /*!< Transfer Complete Interrupt Enable */

+#define OCTOSPI_CR_FTIE_Pos            (18U)

+#define OCTOSPI_CR_FTIE_Msk            (0x1UL << OCTOSPI_CR_FTIE_Pos)           /*!< 0x00040000 */

+#define OCTOSPI_CR_FTIE                OCTOSPI_CR_FTIE_Msk                     /*!< FIFO Threshold Interrupt Enable */

+#define OCTOSPI_CR_SMIE_Pos            (19U)

+#define OCTOSPI_CR_SMIE_Msk            (0x1UL << OCTOSPI_CR_SMIE_Pos)           /*!< 0x00080000 */

+#define OCTOSPI_CR_SMIE                OCTOSPI_CR_SMIE_Msk                     /*!< Status Match Interrupt Enable */

+#define OCTOSPI_CR_TOIE_Pos            (20U)

+#define OCTOSPI_CR_TOIE_Msk            (0x1UL << OCTOSPI_CR_TOIE_Pos)           /*!< 0x00100000 */

+#define OCTOSPI_CR_TOIE                OCTOSPI_CR_TOIE_Msk                     /*!< TimeOut Interrupt Enable */

+#define OCTOSPI_CR_APMS_Pos            (22U)

+#define OCTOSPI_CR_APMS_Msk            (0x1UL << OCTOSPI_CR_APMS_Pos)           /*!< 0x00400000 */

+#define OCTOSPI_CR_APMS                OCTOSPI_CR_APMS_Msk                     /*!< Automatic Poll Mode Stop */

+#define OCTOSPI_CR_PMM_Pos             (23U)

+#define OCTOSPI_CR_PMM_Msk             (0x1UL << OCTOSPI_CR_PMM_Pos)            /*!< 0x00800000 */

+#define OCTOSPI_CR_PMM                 OCTOSPI_CR_PMM_Msk                      /*!< Polling Match Mode */

+#define OCTOSPI_CR_FMODE_Pos           (28U)

+#define OCTOSPI_CR_FMODE_Msk           (0x3UL << OCTOSPI_CR_FMODE_Pos)          /*!< 0x30000000 */

+#define OCTOSPI_CR_FMODE               OCTOSPI_CR_FMODE_Msk                    /*!< Functional Mode */

+#define OCTOSPI_CR_FMODE_0             (0x1UL << OCTOSPI_CR_FMODE_Pos)          /*!< 0x10000000 */

+#define OCTOSPI_CR_FMODE_1             (0x2UL << OCTOSPI_CR_FMODE_Pos)          /*!< 0x20000000 */

+

+/****************  Bit definition for OCTOSPI_DCR1 register  ******************/

+#define OCTOSPI_DCR1_CKMODE_Pos        (0U)

+#define OCTOSPI_DCR1_CKMODE_Msk        (0x1UL << OCTOSPI_DCR1_CKMODE_Pos)       /*!< 0x00000001 */

+#define OCTOSPI_DCR1_CKMODE            OCTOSPI_DCR1_CKMODE_Msk                 /*!< Mode 0 / Mode 3 */

+#define OCTOSPI_DCR1_FRCK_Pos          (1U)

+#define OCTOSPI_DCR1_FRCK_Msk          (0x1UL << OCTOSPI_DCR1_FRCK_Pos)         /*!< 0x00000002 */

+#define OCTOSPI_DCR1_FRCK              OCTOSPI_DCR1_FRCK_Msk                   /*!< Free Running Clock */

+#define OCTOSPI_DCR1_DLYBYP_Pos        (3U)

+#define OCTOSPI_DCR1_DLYBYP_Msk        (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos)       /*!< 0x00000008 */

+#define OCTOSPI_DCR1_DLYBYP            OCTOSPI_DCR1_DLYBYP_Msk                 /*!< Delay Block */

+#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)

+#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */

+#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */

+#define OCTOSPI_DCR1_CSHT_Pos          (8U)

+#define OCTOSPI_DCR1_CSHT_Msk          (0x7UL << OCTOSPI_DCR1_CSHT_Pos)         /*!< 0x00000700 */

+#define OCTOSPI_DCR1_CSHT              OCTOSPI_DCR1_CSHT_Msk                   /*!< Chip Select High Time */

+#define OCTOSPI_DCR1_DEVSIZE_Pos       (16U)

+#define OCTOSPI_DCR1_DEVSIZE_Msk       (0x1FUL << OCTOSPI_DCR1_DEVSIZE_Pos)     /*!< 0x001F0000 */

+#define OCTOSPI_DCR1_DEVSIZE           OCTOSPI_DCR1_DEVSIZE_Msk                /*!< Device Size */

+#define OCTOSPI_DCR1_MTYP_Pos          (24U)

+#define OCTOSPI_DCR1_MTYP_Msk          (0x7UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x07000000 */

+#define OCTOSPI_DCR1_MTYP              OCTOSPI_DCR1_MTYP_Msk                   /*!< Memory Type */

+#define OCTOSPI_DCR1_MTYP_0            (0x1UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x01000000 */

+#define OCTOSPI_DCR1_MTYP_1            (0x2UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x02000000 */

+#define OCTOSPI_DCR1_MTYP_2            (0x4UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x04000000 */

+

+/****************  Bit definition for OCTOSPI_DCR2 register  ******************/

+#define OCTOSPI_DCR2_PRESCALER_Pos     (0U)

+#define OCTOSPI_DCR2_PRESCALER_Msk     (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos)   /*!< 0x000000FF */

+#define OCTOSPI_DCR2_PRESCALER         OCTOSPI_DCR2_PRESCALER_Msk              /*!< Clock prescaler */

+#define OCTOSPI_DCR2_WRAPSIZE_Pos      (16U)

+#define OCTOSPI_DCR2_WRAPSIZE_Msk      (0x7UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00070000 */

+#define OCTOSPI_DCR2_WRAPSIZE          OCTOSPI_DCR2_WRAPSIZE_Msk               /*!< Wrap Size */

+#define OCTOSPI_DCR2_WRAPSIZE_0        (0x1UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00010000 */

+#define OCTOSPI_DCR2_WRAPSIZE_1        (0x2UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00020000 */

+#define OCTOSPI_DCR2_WRAPSIZE_2        (0x4UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00040000 */

+

+/****************  Bit definition for OCTOSPI_DCR3 register  ******************/

+#define OCTOSPI_DCR3_MAXTRAN_Pos       (0U)

+#define OCTOSPI_DCR3_MAXTRAN_Msk       (0xFFUL << OCTOSPI_DCR3_MAXTRAN_Pos)     /*!< 0x000000FF */

+#define OCTOSPI_DCR3_MAXTRAN           OCTOSPI_DCR3_MAXTRAN_Msk                /*!< Maximum Transfer */

+#define OCTOSPI_DCR3_CSBOUND_Pos       (16U)

+#define OCTOSPI_DCR3_CSBOUND_Msk       (0x1FUL << OCTOSPI_DCR3_CSBOUND_Pos)     /*!< 0x001F0000 */

+#define OCTOSPI_DCR3_CSBOUND           OCTOSPI_DCR3_CSBOUND_Msk                /*!< CS Boundary */

+

+/****************  Bit definition for OCTOSPI_DCR4 register  ******************/

+#define OCTOSPI_DCR4_REFRESH_Pos       (0U)

+#define OCTOSPI_DCR4_REFRESH_Msk       (0xFFFFFFFFUL << OCTOSPI_DCR4_REFRESH_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_DCR4_REFRESH           OCTOSPI_DCR4_REFRESH_Msk                /*!< Refresh rate */

+

+/*****************  Bit definition for OCTOSPI_SR register  *******************/

+#define OCTOSPI_SR_TEF_Pos             (0U)

+#define OCTOSPI_SR_TEF_Msk             (0x1UL << OCTOSPI_SR_TEF_Pos)            /*!< 0x00000001 */

+#define OCTOSPI_SR_TEF                 OCTOSPI_SR_TEF_Msk                      /*!< Transfer Error Flag */

+#define OCTOSPI_SR_TCF_Pos             (1U)

+#define OCTOSPI_SR_TCF_Msk             (0x1UL << OCTOSPI_SR_TCF_Pos)            /*!< 0x00000002 */

+#define OCTOSPI_SR_TCF                 OCTOSPI_SR_TCF_Msk                      /*!< Transfer Complete Flag */

+#define OCTOSPI_SR_FTF_Pos             (2U)

+#define OCTOSPI_SR_FTF_Msk             (0x1UL << OCTOSPI_SR_FTF_Pos)            /*!< 0x00000004 */

+#define OCTOSPI_SR_FTF                 OCTOSPI_SR_FTF_Msk                      /*!< FIFO Threshold Flag */

+#define OCTOSPI_SR_SMF_Pos             (3U)

+#define OCTOSPI_SR_SMF_Msk             (0x1UL << OCTOSPI_SR_SMF_Pos)            /*!< 0x00000008 */

+#define OCTOSPI_SR_SMF                 OCTOSPI_SR_SMF_Msk                      /*!< Status Match Flag */

+#define OCTOSPI_SR_TOF_Pos             (4U)

+#define OCTOSPI_SR_TOF_Msk             (0x1UL << OCTOSPI_SR_TOF_Pos)            /*!< 0x00000010 */

+#define OCTOSPI_SR_TOF                 OCTOSPI_SR_TOF_Msk                      /*!< Timeout Flag */

+#define OCTOSPI_SR_BUSY_Pos            (5U)

+#define OCTOSPI_SR_BUSY_Msk            (0x1UL << OCTOSPI_SR_BUSY_Pos)           /*!< 0x00000020 */

+#define OCTOSPI_SR_BUSY                OCTOSPI_SR_BUSY_Msk                     /*!< Busy */

+#define OCTOSPI_SR_FLEVEL_Pos          (8U)

+#define OCTOSPI_SR_FLEVEL_Msk          (0x3FUL << OCTOSPI_SR_FLEVEL_Pos)        /*!< 0x00003F00 */

+#define OCTOSPI_SR_FLEVEL              OCTOSPI_SR_FLEVEL_Msk                   /*!< FIFO Level */

+

+/****************  Bit definition for OCTOSPI_FCR register  *******************/

+#define OCTOSPI_FCR_CTEF_Pos           (0U)

+#define OCTOSPI_FCR_CTEF_Msk           (0x1UL << OCTOSPI_FCR_CTEF_Pos)          /*!< 0x00000001 */

+#define OCTOSPI_FCR_CTEF               OCTOSPI_FCR_CTEF_Msk                    /*!< Clear Transfer Error Flag */

+#define OCTOSPI_FCR_CTCF_Pos           (1U)

+#define OCTOSPI_FCR_CTCF_Msk           (0x1UL << OCTOSPI_FCR_CTCF_Pos)          /*!< 0x00000002 */

+#define OCTOSPI_FCR_CTCF               OCTOSPI_FCR_CTCF_Msk                    /*!< Clear Transfer Complete Flag */

+#define OCTOSPI_FCR_CSMF_Pos           (3U)

+#define OCTOSPI_FCR_CSMF_Msk           (0x1UL << OCTOSPI_FCR_CSMF_Pos)          /*!< 0x00000008 */

+#define OCTOSPI_FCR_CSMF               OCTOSPI_FCR_CSMF_Msk                    /*!< Clear Status Match Flag */

+#define OCTOSPI_FCR_CTOF_Pos           (4U)

+#define OCTOSPI_FCR_CTOF_Msk           (0x1UL << OCTOSPI_FCR_CTOF_Pos)          /*!< 0x00000010 */

+#define OCTOSPI_FCR_CTOF               OCTOSPI_FCR_CTOF_Msk                    /*!< Clear Timeout Flag */

+

+/****************  Bit definition for OCTOSPI_DLR register  *******************/

+#define OCTOSPI_DLR_DL_Pos             (0U)

+#define OCTOSPI_DLR_DL_Msk             (0xFFFFFFFFUL << OCTOSPI_DLR_DL_Pos)     /*!< 0xFFFFFFFF */

+#define OCTOSPI_DLR_DL                 OCTOSPI_DLR_DL_Msk                      /*!< Data Length */

+

+/*****************  Bit definition for OCTOSPI_AR register  *******************/

+#define OCTOSPI_AR_ADDRESS_Pos         (0U)

+#define OCTOSPI_AR_ADDRESS_Msk         (0xFFFFFFFFUL << OCTOSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_AR_ADDRESS             OCTOSPI_AR_ADDRESS_Msk                  /*!< Address */

+

+/*****************  Bit definition for OCTOSPI_DR register  *******************/

+#define OCTOSPI_DR_DATA_Pos            (0U)

+#define OCTOSPI_DR_DATA_Msk            (0xFFFFFFFFUL << OCTOSPI_DR_DATA_Pos)    /*!< 0xFFFFFFFF */

+#define OCTOSPI_DR_DATA                OCTOSPI_DR_DATA_Msk                     /*!< Data */

+

+/***************  Bit definition for OCTOSPI_PSMKR register  ******************/

+#define OCTOSPI_PSMKR_MASK_Pos         (0U)

+#define OCTOSPI_PSMKR_MASK_Msk         (0xFFFFFFFFUL << OCTOSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_PSMKR_MASK             OCTOSPI_PSMKR_MASK_Msk                  /*!< Status mask */

+

+/***************  Bit definition for OCTOSPI_PSMAR register  ******************/

+#define OCTOSPI_PSMAR_MATCH_Pos        (0U)

+#define OCTOSPI_PSMAR_MATCH_Msk        (0xFFFFFFFFUL << OCTOSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_PSMAR_MATCH            OCTOSPI_PSMAR_MATCH_Msk                 /*!< Status match */

+

+/****************  Bit definition for OCTOSPI_PIR register  *******************/

+#define OCTOSPI_PIR_INTERVAL_Pos       (0U)

+#define OCTOSPI_PIR_INTERVAL_Msk       (0xFFFFUL << OCTOSPI_PIR_INTERVAL_Pos)   /*!< 0x0000FFFF */

+#define OCTOSPI_PIR_INTERVAL           OCTOSPI_PIR_INTERVAL_Msk                /*!< Polling Interval */

+

+/****************  Bit definition for OCTOSPI_CCR register  *******************/

+#define OCTOSPI_CCR_IMODE_Pos          (0U)

+#define OCTOSPI_CCR_IMODE_Msk          (0x7UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000007 */

+#define OCTOSPI_CCR_IMODE              OCTOSPI_CCR_IMODE_Msk                   /*!< Instruction Mode */

+#define OCTOSPI_CCR_IMODE_0            (0x1UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000001 */

+#define OCTOSPI_CCR_IMODE_1            (0x2UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000002 */

+#define OCTOSPI_CCR_IMODE_2            (0x4UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000004 */

+#define OCTOSPI_CCR_IDTR_Pos           (3U)

+#define OCTOSPI_CCR_IDTR_Msk           (0x1UL << OCTOSPI_CCR_IDTR_Pos)          /*!< 0x00000008 */

+#define OCTOSPI_CCR_IDTR               OCTOSPI_CCR_IDTR_Msk                    /*!< Instruction Double Transfer Rate */

+#define OCTOSPI_CCR_ISIZE_Pos          (4U)

+#define OCTOSPI_CCR_ISIZE_Msk          (0x3UL << OCTOSPI_CCR_ISIZE_Pos)         /*!< 0x00000030 */

+#define OCTOSPI_CCR_ISIZE              OCTOSPI_CCR_ISIZE_Msk                   /*!< Instruction Size */

+#define OCTOSPI_CCR_ISIZE_0            (0x1UL << OCTOSPI_CCR_ISIZE_Pos)         /*!< 0x00000010 */

+#define OCTOSPI_CCR_ISIZE_1            (0x2UL << OCTOSPI_CCR_ISIZE_Pos)         /*!< 0x00000020 */

+#define OCTOSPI_CCR_ADMODE_Pos         (8U)

+#define OCTOSPI_CCR_ADMODE_Msk         (0x7UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000700 */

+#define OCTOSPI_CCR_ADMODE             OCTOSPI_CCR_ADMODE_Msk                  /*!< Address Mode */

+#define OCTOSPI_CCR_ADMODE_0           (0x1UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000100 */

+#define OCTOSPI_CCR_ADMODE_1           (0x2UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000200 */

+#define OCTOSPI_CCR_ADMODE_2           (0x4UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000400 */

+#define OCTOSPI_CCR_ADDTR_Pos          (11U)

+#define OCTOSPI_CCR_ADDTR_Msk          (0x1UL << OCTOSPI_CCR_ADDTR_Pos)         /*!< 0x00000800 */

+#define OCTOSPI_CCR_ADDTR              OCTOSPI_CCR_ADDTR_Msk                   /*!< Address Double Transfer Rate */

+#define OCTOSPI_CCR_ADSIZE_Pos         (12U)

+#define OCTOSPI_CCR_ADSIZE_Msk         (0x3UL << OCTOSPI_CCR_ADSIZE_Pos)        /*!< 0x00003000 */

+#define OCTOSPI_CCR_ADSIZE             OCTOSPI_CCR_ADSIZE_Msk                  /*!< Address Size */

+#define OCTOSPI_CCR_ADSIZE_0           (0x1UL << OCTOSPI_CCR_ADSIZE_Pos)        /*!< 0x00001000 */

+#define OCTOSPI_CCR_ADSIZE_1           (0x2UL << OCTOSPI_CCR_ADSIZE_Pos)        /*!< 0x00002000 */

+#define OCTOSPI_CCR_ABMODE_Pos         (16U)

+#define OCTOSPI_CCR_ABMODE_Msk         (0x7UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00070000 */

+#define OCTOSPI_CCR_ABMODE             OCTOSPI_CCR_ABMODE_Msk                  /*!< Alternate Bytes Mode */

+#define OCTOSPI_CCR_ABMODE_0           (0x1UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00010000 */

+#define OCTOSPI_CCR_ABMODE_1           (0x2UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00020000 */

+#define OCTOSPI_CCR_ABMODE_2           (0x4UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00040000 */

+#define OCTOSPI_CCR_ABDTR_Pos          (19U)

+#define OCTOSPI_CCR_ABDTR_Msk          (0x1UL << OCTOSPI_CCR_ABDTR_Pos)         /*!< 0x00080000 */

+#define OCTOSPI_CCR_ABDTR              OCTOSPI_CCR_ABDTR_Msk                   /*!< Alternate Bytes Double Transfer Rate */

+#define OCTOSPI_CCR_ABSIZE_Pos         (20U)

+#define OCTOSPI_CCR_ABSIZE_Msk         (0x3UL << OCTOSPI_CCR_ABSIZE_Pos)        /*!< 0x00300000 */

+#define OCTOSPI_CCR_ABSIZE             OCTOSPI_CCR_ABSIZE_Msk                  /*!< Alternate Bytes Size */

+#define OCTOSPI_CCR_ABSIZE_0           (0x1UL << OCTOSPI_CCR_ABSIZE_Pos)        /*!< 0x00100000 */

+#define OCTOSPI_CCR_ABSIZE_1           (0x2UL << OCTOSPI_CCR_ABSIZE_Pos)        /*!< 0x00200000 */

+#define OCTOSPI_CCR_DMODE_Pos          (24U)

+#define OCTOSPI_CCR_DMODE_Msk          (0x7UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x07000000 */

+#define OCTOSPI_CCR_DMODE              OCTOSPI_CCR_DMODE_Msk                   /*!< Data Mode */

+#define OCTOSPI_CCR_DMODE_0            (0x1UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x01000000 */

+#define OCTOSPI_CCR_DMODE_1            (0x2UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x02000000 */

+#define OCTOSPI_CCR_DMODE_2            (0x4UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x04000000 */

+#define OCTOSPI_CCR_DDTR_Pos           (27U)

+#define OCTOSPI_CCR_DDTR_Msk           (0x1UL << OCTOSPI_CCR_DDTR_Pos)          /*!< 0x08000000 */

+#define OCTOSPI_CCR_DDTR               OCTOSPI_CCR_DDTR_Msk                    /*!< Data Double Transfer Rate */

+#define OCTOSPI_CCR_DQSE_Pos           (29U)

+#define OCTOSPI_CCR_DQSE_Msk           (0x1UL << OCTOSPI_CCR_DQSE_Pos)          /*!< 0x20000000 */

+#define OCTOSPI_CCR_DQSE               OCTOSPI_CCR_DQSE_Msk                    /*!< DQS Enable */

+#define OCTOSPI_CCR_SIOO_Pos           (31U)

+#define OCTOSPI_CCR_SIOO_Msk           (0x1UL << OCTOSPI_CCR_SIOO_Pos)          /*!< 0x80000000 */

+#define OCTOSPI_CCR_SIOO               OCTOSPI_CCR_SIOO_Msk                    /*!< Send Instruction Only Once Mode */

+

+/****************  Bit definition for OCTOSPI_TCR register  *******************/

+#define OCTOSPI_TCR_DCYC_Pos           (0U)

+#define OCTOSPI_TCR_DCYC_Msk           (0x1FUL << OCTOSPI_TCR_DCYC_Pos)         /*!< 0x0000001F */

+#define OCTOSPI_TCR_DCYC               OCTOSPI_TCR_DCYC_Msk                    /*!< Number of Dummy Cycles */

+#define OCTOSPI_TCR_DHQC_Pos           (28U)

+#define OCTOSPI_TCR_DHQC_Msk           (0x1UL << OCTOSPI_TCR_DHQC_Pos)          /*!< 0x10000000 */

+#define OCTOSPI_TCR_DHQC               OCTOSPI_TCR_DHQC_Msk                    /*!< Delay Hold Quarter Cycle */

+#define OCTOSPI_TCR_SSHIFT_Pos         (30U)

+#define OCTOSPI_TCR_SSHIFT_Msk         (0x1UL << OCTOSPI_TCR_SSHIFT_Pos)        /*!< 0x40000000 */

+#define OCTOSPI_TCR_SSHIFT             OCTOSPI_TCR_SSHIFT_Msk                  /*!< Sample Shift */

+

+/*****************  Bit definition for OCTOSPI_IR register  *******************/

+#define OCTOSPI_IR_INSTRUCTION_Pos     (0U)

+#define OCTOSPI_IR_INSTRUCTION_Msk     (0xFFFFFFFFUL << OCTOSPI_IR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_IR_INSTRUCTION         OCTOSPI_IR_INSTRUCTION_Msk              /*!< Instruction */

+

+/****************  Bit definition for OCTOSPI_ABR register  *******************/

+#define OCTOSPI_ABR_ALTERNATE_Pos      (0U)

+#define OCTOSPI_ABR_ALTERNATE_Msk      (0xFFFFFFFFUL << OCTOSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_ABR_ALTERNATE          OCTOSPI_ABR_ALTERNATE_Msk               /*!< Alternate Bytes */

+

+/****************  Bit definition for OCTOSPI_LPTR register  ******************/

+#define OCTOSPI_LPTR_TIMEOUT_Pos       (0U)

+#define OCTOSPI_LPTR_TIMEOUT_Msk       (0xFFFFUL << OCTOSPI_LPTR_TIMEOUT_Pos)   /*!< 0x0000FFFF */

+#define OCTOSPI_LPTR_TIMEOUT           OCTOSPI_LPTR_TIMEOUT_Msk                /*!< Timeout period */

+

+/****************  Bit definition for OCTOSPI_WPCCR register  *******************/

+#define OCTOSPI_WPCCR_IMODE_Pos        (0U)

+#define OCTOSPI_WPCCR_IMODE_Msk        (0x7UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000007 */

+#define OCTOSPI_WPCCR_IMODE            OCTOSPI_WPCCR_IMODE_Msk                 /*!< Instruction Mode */

+#define OCTOSPI_WPCCR_IMODE_0          (0x1UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000001 */

+#define OCTOSPI_WPCCR_IMODE_1          (0x2UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000002 */

+#define OCTOSPI_WPCCR_IMODE_2          (0x4UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000004 */

+#define OCTOSPI_WPCCR_IDTR_Pos         (3U)

+#define OCTOSPI_WPCCR_IDTR_Msk         (0x1UL << OCTOSPI_WPCCR_IDTR_Pos)        /*!< 0x00000008 */

+#define OCTOSPI_WPCCR_IDTR             OCTOSPI_WPCCR_IDTR_Msk                  /*!< Instruction Double Transfer Rate */

+#define OCTOSPI_WPCCR_ISIZE_Pos        (4U)

+#define OCTOSPI_WPCCR_ISIZE_Msk        (0x3UL << OCTOSPI_WPCCR_ISIZE_Pos)       /*!< 0x00000030 */

+#define OCTOSPI_WPCCR_ISIZE            OCTOSPI_WPCCR_ISIZE_Msk                 /*!< Instruction Size */

+#define OCTOSPI_WPCCR_ISIZE_0          (0x1UL << OCTOSPI_WPCCR_ISIZE_Pos)       /*!< 0x00000010 */

+#define OCTOSPI_WPCCR_ISIZE_1          (0x2UL << OCTOSPI_WPCCR_ISIZE_Pos)       /*!< 0x00000020 */

+#define OCTOSPI_WPCCR_ADMODE_Pos       (8U)

+#define OCTOSPI_WPCCR_ADMODE_Msk       (0x7UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000700 */

+#define OCTOSPI_WPCCR_ADMODE           OCTOSPI_WPCCR_ADMODE_Msk                /*!< Address Mode */

+#define OCTOSPI_WPCCR_ADMODE_0         (0x1UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000100 */

+#define OCTOSPI_WPCCR_ADMODE_1         (0x2UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000200 */

+#define OCTOSPI_WPCCR_ADMODE_2         (0x4UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000400 */

+#define OCTOSPI_WPCCR_ADDTR_Pos        (11U)

+#define OCTOSPI_WPCCR_ADDTR_Msk        (0x1UL << OCTOSPI_WPCCR_ADDTR_Pos)       /*!< 0x00000800 */

+#define OCTOSPI_WPCCR_ADDTR            OCTOSPI_WPCCR_ADDTR_Msk                 /*!< Address Double Transfer Rate */

+#define OCTOSPI_WPCCR_ADSIZE_Pos       (12U)

+#define OCTOSPI_WPCCR_ADSIZE_Msk       (0x3UL << OCTOSPI_WPCCR_ADSIZE_Pos)      /*!< 0x00003000 */

+#define OCTOSPI_WPCCR_ADSIZE           OCTOSPI_WPCCR_ADSIZE_Msk                /*!< Address Size */

+#define OCTOSPI_WPCCR_ADSIZE_0         (0x1UL << OCTOSPI_WPCCR_ADSIZE_Pos)      /*!< 0x00001000 */

+#define OCTOSPI_WPCCR_ADSIZE_1         (0x2UL << OCTOSPI_WPCCR_ADSIZE_Pos)      /*!< 0x00002000 */

+#define OCTOSPI_WPCCR_ABMODE_Pos       (16U)

+#define OCTOSPI_WPCCR_ABMODE_Msk       (0x7UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00070000 */

+#define OCTOSPI_WPCCR_ABMODE           OCTOSPI_WPCCR_ABMODE_Msk                /*!< Alternate Bytes Mode */

+#define OCTOSPI_WPCCR_ABMODE_0         (0x1UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00010000 */

+#define OCTOSPI_WPCCR_ABMODE_1         (0x2UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00020000 */

+#define OCTOSPI_WPCCR_ABMODE_2         (0x4UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00040000 */

+#define OCTOSPI_WPCCR_ABDTR_Pos        (19U)

+#define OCTOSPI_WPCCR_ABDTR_Msk        (0x1UL << OCTOSPI_WPCCR_ABDTR_Pos)       /*!< 0x00080000 */

+#define OCTOSPI_WPCCR_ABDTR            OCTOSPI_WPCCR_ABDTR_Msk                 /*!< Alternate Bytes Double Transfer Rate */

+#define OCTOSPI_WPCCR_ABSIZE_Pos       (20U)

+#define OCTOSPI_WPCCR_ABSIZE_Msk       (0x3UL << OCTOSPI_WPCCR_ABSIZE_Pos)      /*!< 0x00300000 */

+#define OCTOSPI_WPCCR_ABSIZE           OCTOSPI_WPCCR_ABSIZE_Msk                /*!< Alternate Bytes Size */

+#define OCTOSPI_WPCCR_ABSIZE_0         (0x1UL << OCTOSPI_WPCCR_ABSIZE_Pos)      /*!< 0x00100000 */

+#define OCTOSPI_WPCCR_ABSIZE_1         (0x2UL << OCTOSPI_WPCCR_ABSIZE_Pos)      /*!< 0x00200000 */

+#define OCTOSPI_WPCCR_DMODE_Pos        (24U)

+#define OCTOSPI_WPCCR_DMODE_Msk        (0x7UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x07000000 */

+#define OCTOSPI_WPCCR_DMODE            OCTOSPI_WPCCR_DMODE_Msk                 /*!< Data Mode */

+#define OCTOSPI_WPCCR_DMODE_0          (0x1UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x01000000 */

+#define OCTOSPI_WPCCR_DMODE_1          (0x2UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x02000000 */

+#define OCTOSPI_WPCCR_DMODE_2          (0x4UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x04000000 */

+#define OCTOSPI_WPCCR_DDTR_Pos         (27U)

+#define OCTOSPI_WPCCR_DDTR_Msk         (0x1UL << OCTOSPI_WPCCR_DDTR_Pos)        /*!< 0x08000000 */

+#define OCTOSPI_WPCCR_DDTR             OCTOSPI_WPCCR_DDTR_Msk                  /*!< Data Double Transfer Rate */

+#define OCTOSPI_WPCCR_DQSE_Pos         (29U)

+#define OCTOSPI_WPCCR_DQSE_Msk         (0x1UL << OCTOSPI_WPCCR_DQSE_Pos)        /*!< 0x20000000 */

+#define OCTOSPI_WPCCR_DQSE             OCTOSPI_WPCCR_DQSE_Msk                  /*!< DQS Enable */

+#define OCTOSPI_WPCCR_SIOO_Pos         (31U)

+#define OCTOSPI_WPCCR_SIOO_Msk         (0x1UL << OCTOSPI_WPCCR_SIOO_Pos)        /*!< 0x80000000 */

+#define OCTOSPI_WPCCR_SIOO             OCTOSPI_WPCCR_SIOO_Msk                  /*!< Send Instruction Only Once Mode */

+

+/****************  Bit definition for OCTOSPI_WPTCR register  *******************/

+#define OCTOSPI_WPTCR_DCYC_Pos         (0U)

+#define OCTOSPI_WPTCR_DCYC_Msk         (0x1FUL << OCTOSPI_WPTCR_DCYC_Pos)       /*!< 0x0000001F */

+#define OCTOSPI_WPTCR_DCYC             OCTOSPI_WPTCR_DCYC_Msk                  /*!< Number of Dummy Cycles */

+#define OCTOSPI_WPTCR_DHQC_Pos         (28U)

+#define OCTOSPI_WPTCR_DHQC_Msk         (0x1UL << OCTOSPI_WPTCR_DHQC_Pos)        /*!< 0x10000000 */

+#define OCTOSPI_WPTCR_DHQC             OCTOSPI_WPTCR_DHQC_Msk                  /*!< Delay Hold Quarter Cycle */

+#define OCTOSPI_WPTCR_SSHIFT_Pos       (30U)

+#define OCTOSPI_WPTCR_SSHIFT_Msk       (0x1UL << OCTOSPI_WPTCR_SSHIFT_Pos)      /*!< 0x40000000 */

+#define OCTOSPI_WPTCR_SSHIFT           OCTOSPI_WPTCR_SSHIFT_Msk                /*!< Sample Shift */

+

+/*****************  Bit definition for OCTOSPI_WPIR register  *******************/

+#define OCTOSPI_WPIR_INSTRUCTION_Pos   (0U)

+#define OCTOSPI_WPIR_INSTRUCTION_Msk   (0xFFFFFFFFUL << OCTOSPI_WPIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_WPIR_INSTRUCTION       OCTOSPI_WPIR_INSTRUCTION_Msk            /*!< Instruction */

+

+/****************  Bit definition for OCTOSPI_WPABR register  *******************/

+#define OCTOSPI_WPABR_ALTERNATE_Pos    (0U)

+#define OCTOSPI_WPABR_ALTERNATE_Msk    (0xFFFFFFFFUL << OCTOSPI_WPABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_WPABR_ALTERNATE        OCTOSPI_WPABR_ALTERNATE_Msk             /*!< Alternate Bytes */

+

+/****************  Bit definition for OCTOSPI_WCCR register  ******************/

+#define OCTOSPI_WCCR_IMODE_Pos         (0U)

+#define OCTOSPI_WCCR_IMODE_Msk         (0x7UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000007 */

+#define OCTOSPI_WCCR_IMODE             OCTOSPI_WCCR_IMODE_Msk                  /*!< Instruction Mode */

+#define OCTOSPI_WCCR_IMODE_0           (0x1UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000001 */

+#define OCTOSPI_WCCR_IMODE_1           (0x2UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000002 */

+#define OCTOSPI_WCCR_IMODE_2           (0x4UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000004 */

+#define OCTOSPI_WCCR_IDTR_Pos          (3U)

+#define OCTOSPI_WCCR_IDTR_Msk          (0x1UL << OCTOSPI_WCCR_IDTR_Pos)         /*!< 0x00000008 */

+#define OCTOSPI_WCCR_IDTR              OCTOSPI_WCCR_IDTR_Msk                   /*!< Instruction Double Transfer Rate */

+#define OCTOSPI_WCCR_ISIZE_Pos         (4U)

+#define OCTOSPI_WCCR_ISIZE_Msk         (0x3UL << OCTOSPI_WCCR_ISIZE_Pos)        /*!< 0x00000030 */

+#define OCTOSPI_WCCR_ISIZE             OCTOSPI_WCCR_ISIZE_Msk                  /*!< Instruction Size */

+#define OCTOSPI_WCCR_ISIZE_0           (0x1UL << OCTOSPI_WCCR_ISIZE_Pos)        /*!< 0x00000010 */

+#define OCTOSPI_WCCR_ISIZE_1           (0x2UL << OCTOSPI_WCCR_ISIZE_Pos)        /*!< 0x00000020 */

+#define OCTOSPI_WCCR_ADMODE_Pos        (8U)

+#define OCTOSPI_WCCR_ADMODE_Msk        (0x7UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000700 */

+#define OCTOSPI_WCCR_ADMODE            OCTOSPI_WCCR_ADMODE_Msk                 /*!< Address Mode */

+#define OCTOSPI_WCCR_ADMODE_0          (0x1UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000100 */

+#define OCTOSPI_WCCR_ADMODE_1          (0x2UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000200 */

+#define OCTOSPI_WCCR_ADMODE_2          (0x4UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000400 */

+#define OCTOSPI_WCCR_ADDTR_Pos         (11U)

+#define OCTOSPI_WCCR_ADDTR_Msk         (0x1UL << OCTOSPI_WCCR_ADDTR_Pos)        /*!< 0x00000800 */

+#define OCTOSPI_WCCR_ADDTR             OCTOSPI_WCCR_ADDTR_Msk                  /*!< Address Double Transfer Rate */

+#define OCTOSPI_WCCR_ADSIZE_Pos        (12U)

+#define OCTOSPI_WCCR_ADSIZE_Msk        (0x3UL << OCTOSPI_WCCR_ADSIZE_Pos)       /*!< 0x00003000 */

+#define OCTOSPI_WCCR_ADSIZE            OCTOSPI_WCCR_ADSIZE_Msk                 /*!< Address Size */

+#define OCTOSPI_WCCR_ADSIZE_0          (0x1UL << OCTOSPI_WCCR_ADSIZE_Pos)       /*!< 0x00001000 */

+#define OCTOSPI_WCCR_ADSIZE_1          (0x2UL << OCTOSPI_WCCR_ADSIZE_Pos)       /*!< 0x00002000 */

+#define OCTOSPI_WCCR_ABMODE_Pos        (16U)

+#define OCTOSPI_WCCR_ABMODE_Msk        (0x7UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00070000 */

+#define OCTOSPI_WCCR_ABMODE            OCTOSPI_WCCR_ABMODE_Msk                 /*!< Alternate Bytes Mode */

+#define OCTOSPI_WCCR_ABMODE_0          (0x1UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00010000 */

+#define OCTOSPI_WCCR_ABMODE_1          (0x2UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00020000 */

+#define OCTOSPI_WCCR_ABMODE_2          (0x4UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00040000 */

+#define OCTOSPI_WCCR_ABDTR_Pos         (19U)

+#define OCTOSPI_WCCR_ABDTR_Msk         (0x1UL << OCTOSPI_WCCR_ABDTR_Pos)        /*!< 0x00080000 */

+#define OCTOSPI_WCCR_ABDTR             OCTOSPI_WCCR_ABDTR_Msk                  /*!< Alternate Bytes Double Transfer Rate */

+#define OCTOSPI_WCCR_ABSIZE_Pos        (20U)

+#define OCTOSPI_WCCR_ABSIZE_Msk        (0x3UL << OCTOSPI_WCCR_ABSIZE_Pos)       /*!< 0x00300000 */

+#define OCTOSPI_WCCR_ABSIZE            OCTOSPI_WCCR_ABSIZE_Msk                 /*!< Alternate Bytes Size */

+#define OCTOSPI_WCCR_ABSIZE_0          (0x1UL << OCTOSPI_WCCR_ABSIZE_Pos)       /*!< 0x00100000 */

+#define OCTOSPI_WCCR_ABSIZE_1          (0x2UL << OCTOSPI_WCCR_ABSIZE_Pos)       /*!< 0x00200000 */

+#define OCTOSPI_WCCR_DMODE_Pos         (24U)

+#define OCTOSPI_WCCR_DMODE_Msk         (0x7UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x07000000 */

+#define OCTOSPI_WCCR_DMODE             OCTOSPI_WCCR_DMODE_Msk                  /*!< Data Mode */

+#define OCTOSPI_WCCR_DMODE_0           (0x1UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x01000000 */

+#define OCTOSPI_WCCR_DMODE_1           (0x2UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x02000000 */

+#define OCTOSPI_WCCR_DMODE_2           (0x4UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x04000000 */

+#define OCTOSPI_WCCR_DDTR_Pos          (27U)

+#define OCTOSPI_WCCR_DDTR_Msk          (0x1UL << OCTOSPI_WCCR_DDTR_Pos)         /*!< 0x08000000 */

+#define OCTOSPI_WCCR_DDTR              OCTOSPI_WCCR_DDTR_Msk                   /*!< Data Double Transfer Rate */

+#define OCTOSPI_WCCR_DQSE_Pos          (29U)

+#define OCTOSPI_WCCR_DQSE_Msk          (0x1UL << OCTOSPI_WCCR_DQSE_Pos)         /*!< 0x20000000 */

+#define OCTOSPI_WCCR_DQSE              OCTOSPI_WCCR_DQSE_Msk                   /*!< DQS Enable */

+#define OCTOSPI_WCCR_SIOO_Pos          (31U)

+#define OCTOSPI_WCCR_SIOO_Msk          (0x1UL << OCTOSPI_WCCR_SIOO_Pos)         /*!< 0x80000000 */

+#define OCTOSPI_WCCR_SIOO              OCTOSPI_WCCR_SIOO_Msk                   /*!< Send Instruction Only Once Mode */

+

+/****************  Bit definition for OCTOSPI_WTCR register  ******************/

+#define OCTOSPI_WTCR_DCYC_Pos          (0U)

+#define OCTOSPI_WTCR_DCYC_Msk          (0x1FUL << OCTOSPI_WTCR_DCYC_Pos)        /*!< 0x0000001F */

+#define OCTOSPI_WTCR_DCYC              OCTOSPI_WTCR_DCYC_Msk                   /*!< Number of Dummy Cycles */

+

+/****************  Bit definition for OCTOSPI_WIR register  *******************/

+#define OCTOSPI_WIR_INSTRUCTION_Pos    (0U)

+#define OCTOSPI_WIR_INSTRUCTION_Msk    (0xFFFFFFFFUL << OCTOSPI_WIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_WIR_INSTRUCTION        OCTOSPI_WIR_INSTRUCTION_Msk             /*!< Instruction */

+

+/****************  Bit definition for OCTOSPI_WABR register  ******************/

+#define OCTOSPI_WABR_ALTERNATE_Pos     (0U)

+#define OCTOSPI_WABR_ALTERNATE_Msk     (0xFFFFFFFFUL << OCTOSPI_WABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_WABR_ALTERNATE         OCTOSPI_WABR_ALTERNATE_Msk              /*!< Alternate Bytes */

+

+/****************  Bit definition for OCTOSPI_HLCR register  ******************/

+#define OCTOSPI_HLCR_LM_Pos            (0U)

+#define OCTOSPI_HLCR_LM_Msk            (0x1UL << OCTOSPI_HLCR_LM_Pos)           /*!< 0x00000001 */

+#define OCTOSPI_HLCR_LM                OCTOSPI_HLCR_LM_Msk                     /*!< Latency Mode */

+#define OCTOSPI_HLCR_WZL_Pos           (1U)

+#define OCTOSPI_HLCR_WZL_Msk           (0x1UL << OCTOSPI_HLCR_WZL_Pos)          /*!< 0x00000002 */

+#define OCTOSPI_HLCR_WZL               OCTOSPI_HLCR_WZL_Msk                    /*!< Write Zero Latency */

+#define OCTOSPI_HLCR_TACC_Pos          (8U)

+#define OCTOSPI_HLCR_TACC_Msk          (0xFFUL << OCTOSPI_HLCR_TACC_Pos)        /*!< 0x0000FF00 */

+#define OCTOSPI_HLCR_TACC              OCTOSPI_HLCR_TACC_Msk                   /*!< Access Time */

+#define OCTOSPI_HLCR_TRWR_Pos          (16U)

+#define OCTOSPI_HLCR_TRWR_Msk          (0xFFUL << OCTOSPI_HLCR_TRWR_Pos)        /*!< 0x00FF0000 */

+#define OCTOSPI_HLCR_TRWR              OCTOSPI_HLCR_TRWR_Msk                   /*!< Read Write Recovery Time */

+

+/****************  Bit definition for OCTOSPI_VER register  *******************/

+#define OCTOSPI_VER_VER_Pos            (0U)

+#define OCTOSPI_VER_VER_Msk            (0xFFUL << OCTOSPI_VER_VER_Pos)          /*!< 0x000000FF */

+#define OCTOSPI_VER_VER                OCTOSPI_VER_VER_Msk                     /*!< Version */

+

+/*****************  Bit definition for OCTOSPI_ID register  *******************/

+#define OCTOSPI_ID_ID_Pos              (0U)

+#define OCTOSPI_ID_ID_Msk              (0xFFFFFFFFUL << OCTOSPI_ID_ID_Pos)      /*!< 0xFFFFFFFF */

+#define OCTOSPI_ID_ID                  OCTOSPI_ID_ID_Msk                       /*!< Identification */

+

+/****************  Bit definition for OCTOSPI_MID register  *******************/

+#define OCTOSPI_MID_MID_Pos            (0U)

+#define OCTOSPI_MID_MID_Msk            (0xFFFFFFFFUL << OCTOSPI_MID_MID_Pos)    /*!< 0xFFFFFFFF */

+#define OCTOSPI_MID_MID                OCTOSPI_MID_MID_Msk                     /*!< Magic ID */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                  OCTOSPIM                                  */

+/*                                                                            */

+/******************************************************************************/

+

+/***************  Bit definition for OCTOSPIM_CR register  ********************/

+#define OCTOSPIM_CR_MUXEN_Pos          (0U)

+#define OCTOSPIM_CR_MUXEN_Msk          (0x1UL << OCTOSPIM_CR_MUXEN_Pos)        /*!< 0x00000001 */

+#define OCTOSPIM_CR_MUXEN              OCTOSPIM_CR_MUXEN_Msk                   /*!< Multiplexed mode enable */

+#define OCTOSPIM_CR_REQ2ACK_TIME_Pos   (16U)

+#define OCTOSPIM_CR_REQ2ACK_TIME_Msk   (0xFFUL << OCTOSPIM_CR_REQ2ACK_TIME_Pos)/*!< 0x00FF0000 */

+#define OCTOSPIM_CR_REQ2ACK_TIME       OCTOSPIM_CR_REQ2ACK_TIME_Msk            /*!< REQ to ACK time */

+

+/***************  Bit definition for OCTOSPIM_PCR register  *******************/

+#define OCTOSPIM_PCR_CLKEN_Pos         (0U)

+#define OCTOSPIM_PCR_CLKEN_Msk         (0x1UL << OCTOSPIM_PCR_CLKEN_Pos)        /*!< 0x00000001 */

+#define OCTOSPIM_PCR_CLKEN             OCTOSPIM_PCR_CLKEN_Msk                   /*!< CLK/CLKn Enable for Port n */

+#define OCTOSPIM_PCR_CLKSRC_Pos        (1U)

+#define OCTOSPIM_PCR_CLKSRC_Msk        (0x1UL << OCTOSPIM_PCR_CLKSRC_Pos)       /*!< 0x00000002 */

+#define OCTOSPIM_PCR_CLKSRC            OCTOSPIM_PCR_CLKSRC_Msk                  /*!< CLK/CLKn Source for Port n */

+#define OCTOSPIM_PCR_DQSEN_Pos         (4U)

+#define OCTOSPIM_PCR_DQSEN_Msk         (0x1UL << OCTOSPIM_PCR_DQSEN_Pos)        /*!< 0x00000010 */

+#define OCTOSPIM_PCR_DQSEN             OCTOSPIM_PCR_DQSEN_Msk                   /*!< DQS Enable for Port n */

+#define OCTOSPIM_PCR_DQSSRC_Pos        (5U)

+#define OCTOSPIM_PCR_DQSSRC_Msk        (0x1UL << OCTOSPIM_PCR_DQSSRC_Pos)       /*!< 0x00000020 */

+#define OCTOSPIM_PCR_DQSSRC            OCTOSPIM_PCR_DQSSRC_Msk                  /*!< DQS Source for Port n */

+#define OCTOSPIM_PCR_NCSEN_Pos         (8U)

+#define OCTOSPIM_PCR_NCSEN_Msk         (0x1UL << OCTOSPIM_PCR_NCSEN_Pos)        /*!< 0x00000100 */

+#define OCTOSPIM_PCR_NCSEN             OCTOSPIM_PCR_NCSEN_Msk                   /*!< nCS Enable for Port n */

+#define OCTOSPIM_PCR_NCSSRC_Pos        (9U)

+#define OCTOSPIM_PCR_NCSSRC_Msk        (0x1UL << OCTOSPIM_PCR_NCSSRC_Pos)       /*!< 0x00000200 */

+#define OCTOSPIM_PCR_NCSSRC            OCTOSPIM_PCR_NCSSRC_Msk                  /*!< nCS Source for Port n */

+#define OCTOSPIM_PCR_IOLEN_Pos         (16U)

+#define OCTOSPIM_PCR_IOLEN_Msk         (0x1UL << OCTOSPIM_PCR_IOLEN_Pos)        /*!< 0x00010000 */

+#define OCTOSPIM_PCR_IOLEN             OCTOSPIM_PCR_IOLEN_Msk                   /*!< IO[3:0] Enable for Port n */

+#define OCTOSPIM_PCR_IOLSRC_Pos        (17U)

+#define OCTOSPIM_PCR_IOLSRC_Msk        (0x3UL << OCTOSPIM_PCR_IOLSRC_Pos)       /*!< 0x00060000 */

+#define OCTOSPIM_PCR_IOLSRC            OCTOSPIM_PCR_IOLSRC_Msk                  /*!< IO[3:0] Source for Port n */

+#define OCTOSPIM_PCR_IOLSRC_0          (0x1UL << OCTOSPIM_PCR_IOLSRC_Pos)       /*!< 0x00020000 */

+#define OCTOSPIM_PCR_IOLSRC_1          (0x2UL << OCTOSPIM_PCR_IOLSRC_Pos)       /*!< 0x00040000 */

+#define OCTOSPIM_PCR_IOHEN_Pos         (24U)

+#define OCTOSPIM_PCR_IOHEN_Msk         (0x1UL << OCTOSPIM_PCR_IOHEN_Pos)        /*!< 0x01000000 */

+#define OCTOSPIM_PCR_IOHEN             OCTOSPIM_PCR_IOHEN_Msk                   /*!< IO[7:4] Enable for Port n */

+#define OCTOSPIM_PCR_IOHSRC_Pos        (25U)

+#define OCTOSPIM_PCR_IOHSRC_Msk        (0x3UL << OCTOSPIM_PCR_IOHSRC_Pos)       /*!< 0x06000000 */

+#define OCTOSPIM_PCR_IOHSRC            OCTOSPIM_PCR_IOHSRC_Msk                  /*!< IO[7:4] Source for Port n */

+#define OCTOSPIM_PCR_IOHSRC_0          (0x1UL << OCTOSPIM_PCR_IOHSRC_Pos)       /*!< 0x02000000 */

+#define OCTOSPIM_PCR_IOHSRC_1          (0x2UL << OCTOSPIM_PCR_IOHSRC_Pos)       /*!< 0x04000000 */

+/******************************************************************************/

+/*                                                                            */

+/*                      Analog Comparators (COMP)                             */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for COMP_SR register  ********************/

+#define COMP_SR_C1VAL_Pos            (0U)

+#define COMP_SR_C1VAL_Msk            (0x1UL << COMP_SR_C1VAL_Pos)              /*!< 0x00000001 */

+#define COMP_SR_C1VAL                COMP_SR_C1VAL_Msk

+#define COMP_SR_C2VAL_Pos            (1U)

+#define COMP_SR_C2VAL_Msk            (0x1UL << COMP_SR_C2VAL_Pos)              /*!< 0x00000002 */

+#define COMP_SR_C2VAL                COMP_SR_C2VAL_Msk

+#define COMP_SR_C1IF_Pos             (16U)

+#define COMP_SR_C1IF_Msk             (0x1UL << COMP_SR_C1IF_Pos)               /*!< 0x00010000 */

+#define COMP_SR_C1IF                 COMP_SR_C1IF_Msk

+#define COMP_SR_C2IF_Pos             (17U)

+#define COMP_SR_C2IF_Msk             (0x1UL << COMP_SR_C2IF_Pos)               /*!< 0x00020000 */

+#define COMP_SR_C2IF                 COMP_SR_C2IF_Msk

+/*******************  Bit definition for COMP_ICFR register  ********************/

+#define COMP_ICFR_C1IF_Pos           (16U)

+#define COMP_ICFR_C1IF_Msk           (0x1UL << COMP_ICFR_C1IF_Pos)             /*!< 0x00010000 */

+#define COMP_ICFR_C1IF               COMP_ICFR_C1IF_Msk

+#define COMP_ICFR_C2IF_Pos           (17U)

+#define COMP_ICFR_C2IF_Msk           (0x1UL << COMP_ICFR_C2IF_Pos)             /*!< 0x00020000 */

+#define COMP_ICFR_C2IF               COMP_ICFR_C2IF_Msk

+/*******************  Bit definition for COMP_OR register  ********************/

+#define COMP_OR_AFOPA6_Pos           (0U)

+#define COMP_OR_AFOPA6_Msk           (0x1UL << COMP_OR_AFOPA6_Pos)             /*!< 0x00000001 */

+#define COMP_OR_AFOPA6               COMP_OR_AFOPA6_Msk

+#define COMP_OR_AFOPA8_Pos           (1U)

+#define COMP_OR_AFOPA8_Msk           (0x1UL << COMP_OR_AFOPA8_Pos)             /*!< 0x00000002 */

+#define COMP_OR_AFOPA8               COMP_OR_AFOPA8_Msk

+#define COMP_OR_AFOPB12_Pos          (2U)

+#define COMP_OR_AFOPB12_Msk          (0x1UL << COMP_OR_AFOPB12_Pos)            /*!< 0x00000004 */

+#define COMP_OR_AFOPB12              COMP_OR_AFOPB12_Msk

+#define COMP_OR_AFOPE6_Pos           (3U)

+#define COMP_OR_AFOPE6_Msk           (0x1UL << COMP_OR_AFOPE6_Pos)             /*!< 0x00000008 */

+#define COMP_OR_AFOPE6               COMP_OR_AFOPE6_Msk

+#define COMP_OR_AFOPE15_Pos          (4U)

+#define COMP_OR_AFOPE15_Msk          (0x1UL << COMP_OR_AFOPE15_Pos)            /*!< 0x00000010 */

+#define COMP_OR_AFOPE15              COMP_OR_AFOPE15_Msk

+#define COMP_OR_AFOPG2_Pos           (5U)

+#define COMP_OR_AFOPG2_Msk           (0x1UL << COMP_OR_AFOPG2_Pos)             /*!< 0x00000020 */

+#define COMP_OR_AFOPG2               COMP_OR_AFOPG2_Msk

+#define COMP_OR_AFOPG3_Pos           (6U)

+#define COMP_OR_AFOPG3_Msk           (0x1UL << COMP_OR_AFOPG3_Pos)             /*!< 0x00000040 */

+#define COMP_OR_AFOPG3               COMP_OR_AFOPG3_Msk

+#define COMP_OR_AFOPG4_Pos           (7U)

+#define COMP_OR_AFOPG4_Msk           (0x1UL << COMP_OR_AFOPG4_Pos)             /*!< 0x00000080 */

+#define COMP_OR_AFOPG4               COMP_OR_AFOPG4_Msk

+#define COMP_OR_AFOPI1_Pos           (8U)

+#define COMP_OR_AFOPI1_Msk           (0x1UL << COMP_OR_AFOPI1_Pos)             /*!< 0x00000100 */

+#define COMP_OR_AFOPI1               COMP_OR_AFOPI1_Msk

+#define COMP_OR_AFOPI4_Pos           (9U)

+#define COMP_OR_AFOPI4_Msk           (0x1UL << COMP_OR_AFOPI4_Pos)             /*!< 0x00000200 */

+#define COMP_OR_AFOPI4               COMP_OR_AFOPI4_Msk

+#define COMP_OR_AFOPK2_Pos           (10U)

+#define COMP_OR_AFOPK2_Msk           (0x1UL << COMP_OR_AFOPK2_Pos)             /*!< 0x00000400 */

+#define COMP_OR_AFOPK2               COMP_OR_AFOPK2_Msk

+

+/*!< ******************  Bit definition for COMP_CFGRx register  ********************/

+#define COMP_CFGRx_EN_Pos            (0U)

+#define COMP_CFGRx_EN_Msk            (0x1UL << COMP_CFGRx_EN_Pos)              /*!< 0x00000001 */

+#define COMP_CFGRx_EN                COMP_CFGRx_EN_Msk                         /*!< COMPx enable bit                     */

+#define COMP_CFGRx_BRGEN_Pos         (1U)

+#define COMP_CFGRx_BRGEN_Msk         (0x1UL << COMP_CFGRx_BRGEN_Pos)           /*!< 0x00000002 */

+#define COMP_CFGRx_BRGEN             COMP_CFGRx_BRGEN_Msk                      /*!< COMPx Scaler bridge enable           */

+#define COMP_CFGRx_SCALEN_Pos        (2U)

+#define COMP_CFGRx_SCALEN_Msk        (0x1UL << COMP_CFGRx_SCALEN_Pos)          /*!< 0x00000004 */

+#define COMP_CFGRx_SCALEN            COMP_CFGRx_SCALEN_Msk                     /*!< COMPx Voltage scaler enable bit      */

+#define COMP_CFGRx_POLARITY_Pos      (3U)

+#define COMP_CFGRx_POLARITY_Msk      (0x1UL << COMP_CFGRx_POLARITY_Pos)        /*!< 0x00000008 */

+#define COMP_CFGRx_POLARITY          COMP_CFGRx_POLARITY_Msk                   /*!< COMPx  polarity selection bit        */

+#define COMP_CFGRx_WINMODE_Pos       (4U)

+#define COMP_CFGRx_WINMODE_Msk       (0x1UL << COMP_CFGRx_WINMODE_Pos)         /*!< 0x00000010 */

+#define COMP_CFGRx_WINMODE           COMP_CFGRx_WINMODE_Msk                    /*!< COMPx Windows mode selection bit     */

+#define COMP_CFGRx_ITEN_Pos          (6U)

+#define COMP_CFGRx_ITEN_Msk          (0x1UL << COMP_CFGRx_ITEN_Pos)            /*!< 0x00000040 */

+#define COMP_CFGRx_ITEN              COMP_CFGRx_ITEN_Msk                       /*!< COMPx  interrupt enable              */

+#define COMP_CFGRx_HYST_Pos          (8U)

+#define COMP_CFGRx_HYST_Msk          (0x3UL << COMP_CFGRx_HYST_Pos)            /*!< 0x00000300 */

+#define COMP_CFGRx_HYST              COMP_CFGRx_HYST_Msk                       /*!< COMPx  hysteresis selection bits     */

+#define COMP_CFGRx_HYST_0            (0x1UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000100 */

+#define COMP_CFGRx_HYST_1            (0x2UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000200 */

+#define COMP_CFGRx_PWRMODE_Pos       (12U)

+#define COMP_CFGRx_PWRMODE_Msk       (0x3UL << COMP_CFGRx_PWRMODE_Pos)         /*!< 0x00003000 */

+#define COMP_CFGRx_PWRMODE           COMP_CFGRx_PWRMODE_Msk                    /*!< COMPx Power Mode of the comparator   */

+#define COMP_CFGRx_PWRMODE_0         (0x1UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00001000 */

+#define COMP_CFGRx_PWRMODE_1         (0x2UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00002000 */

+#define COMP_CFGRx_INMSEL_Pos        (16U)

+#define COMP_CFGRx_INMSEL_Msk        (0xFUL << COMP_CFGRx_INMSEL_Pos)          /*!< 0x000F0000 */

+#define COMP_CFGRx_INMSEL            COMP_CFGRx_INMSEL_Msk                     /*!< COMPx  input minus selection bit  */

+#define COMP_CFGRx_INMSEL_0          (0x1UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00010000 */

+#define COMP_CFGRx_INMSEL_1          (0x2UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00020000 */

+#define COMP_CFGRx_INMSEL_2          (0x4UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00040000 */

+#define COMP_CFGRx_INMSEL_3          (0x8UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00080000 */

+#define COMP_CFGRx_INPSEL_Pos        (20U)

+#define COMP_CFGRx_INPSEL_Msk        (0x1UL << COMP_CFGRx_INPSEL_Pos)          /*!< 0x00100000 */

+#define COMP_CFGRx_INPSEL            COMP_CFGRx_INPSEL_Msk                     /*!< COMPx  input plus selection bit       */

+#define COMP_CFGRx_INP2SEL_Pos        (22U)

+#define COMP_CFGRx_INP2SEL_Msk        (0x1UL << COMP_CFGRx_INP2SEL_Pos)        /*!< 0x00400000 */

+#define COMP_CFGRx_INP2SEL            COMP_CFGRx_INP2SEL_Msk                   /*!< COMPx  input plus 2 selection bit     */

+#define COMP_CFGRx_BLANKING_Pos      (24U)

+#define COMP_CFGRx_BLANKING_Msk      (0xFUL << COMP_CFGRx_BLANKING_Pos)        /*!< 0x0F000000 */

+#define COMP_CFGRx_BLANKING          COMP_CFGRx_BLANKING_Msk                   /*!< COMPx  blanking source selection bits */

+#define COMP_CFGRx_BLANKING_0        (0x1UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x01000000 */

+#define COMP_CFGRx_BLANKING_1        (0x2UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x02000000 */

+#define COMP_CFGRx_BLANKING_2        (0x4UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x04000000 */

+#define COMP_CFGRx_LOCK_Pos          (31U)

+#define COMP_CFGRx_LOCK_Msk          (0x1UL << COMP_CFGRx_LOCK_Pos)            /*!< 0x80000000 */

+#define COMP_CFGRx_LOCK              COMP_CFGRx_LOCK_Msk                       /*!< COMPx Lock Bit                        */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for USART_CR1 register  *******************/

+#define USART_CR1_UE_Pos                (0U)

+#define USART_CR1_UE_Msk                (0x1UL << USART_CR1_UE_Pos)            /*!< 0x00000001 */

+#define USART_CR1_UE                    USART_CR1_UE_Msk                       /*!< USART Enable */

+#define USART_CR1_UESM_Pos              (1U)

+#define USART_CR1_UESM_Msk              (0x1UL << USART_CR1_UESM_Pos)          /*!< 0x00000002 */

+#define USART_CR1_UESM                  USART_CR1_UESM_Msk                     /*!< USART Enable in STOP Mode */

+#define USART_CR1_RE_Pos                (2U)

+#define USART_CR1_RE_Msk                (0x1UL << USART_CR1_RE_Pos)            /*!< 0x00000004 */

+#define USART_CR1_RE                    USART_CR1_RE_Msk                       /*!< Receiver Enable */

+#define USART_CR1_TE_Pos                (3U)

+#define USART_CR1_TE_Msk                (0x1UL << USART_CR1_TE_Pos)            /*!< 0x00000008 */

+#define USART_CR1_TE                    USART_CR1_TE_Msk                       /*!< Transmitter Enable */

+#define USART_CR1_IDLEIE_Pos            (4U)

+#define USART_CR1_IDLEIE_Msk            (0x1UL << USART_CR1_IDLEIE_Pos)        /*!< 0x00000010 */

+#define USART_CR1_IDLEIE                USART_CR1_IDLEIE_Msk                   /*!< IDLE Interrupt Enable */

+#define USART_CR1_RXNEIE_RXFNEIE_Pos    (5U)

+#define USART_CR1_RXNEIE_RXFNEIE_Msk    (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */

+#define USART_CR1_RXNEIE_RXFNEIE        USART_CR1_RXNEIE_RXFNEIE_Msk           /*!< RXNE and RX FIFO Not Empty Interrupt Enable */

+#define USART_CR1_TCIE_Pos              (6U)

+#define USART_CR1_TCIE_Msk              (0x1UL << USART_CR1_TCIE_Pos)          /*!< 0x00000040 */

+#define USART_CR1_TCIE                  USART_CR1_TCIE_Msk                     /*!< Transmission Complete Interrupt Enable */

+#define USART_CR1_TXEIE_TXFNFIE_Pos     (7U)

+#define USART_CR1_TXEIE_TXFNFIE_Msk     (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */

+#define USART_CR1_TXEIE_TXFNFIE         USART_CR1_TXEIE_TXFNFIE_Msk            /*!< TXE and TX FIFO Not Full Interrupt Enable */

+#define USART_CR1_PEIE_Pos              (8U)

+#define USART_CR1_PEIE_Msk              (0x1UL << USART_CR1_PEIE_Pos)          /*!< 0x00000100 */

+#define USART_CR1_PEIE                  USART_CR1_PEIE_Msk                     /*!< PE Interrupt Enable */

+#define USART_CR1_PS_Pos                (9U)

+#define USART_CR1_PS_Msk                (0x1UL << USART_CR1_PS_Pos)            /*!< 0x00000200 */

+#define USART_CR1_PS                    USART_CR1_PS_Msk                       /*!< Parity Selection */

+#define USART_CR1_PCE_Pos               (10U)

+#define USART_CR1_PCE_Msk               (0x1UL << USART_CR1_PCE_Pos)           /*!< 0x00000400 */

+#define USART_CR1_PCE                   USART_CR1_PCE_Msk                      /*!< Parity Control Enable */

+#define USART_CR1_WAKE_Pos              (11U)

+#define USART_CR1_WAKE_Msk              (0x1UL << USART_CR1_WAKE_Pos)          /*!< 0x00000800 */

+#define USART_CR1_WAKE                  USART_CR1_WAKE_Msk                     /*!< Receiver Wakeup method */

+#define USART_CR1_M_Pos                 (12U)

+#define USART_CR1_M_Msk                 (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */

+#define USART_CR1_M                     USART_CR1_M_Msk                        /*!< Word length */

+#define USART_CR1_M0_Pos                (12U)

+#define USART_CR1_M0_Msk                (0x1UL << USART_CR1_M0_Pos)            /*!< 0x00001000 */

+#define USART_CR1_M0                    USART_CR1_M0_Msk                       /*!< Word length - Bit 0 */

+#define USART_CR1_MME_Pos               (13U)

+#define USART_CR1_MME_Msk               (0x1UL << USART_CR1_MME_Pos)           /*!< 0x00002000 */

+#define USART_CR1_MME                   USART_CR1_MME_Msk                      /*!< Mute Mode Enable */

+#define USART_CR1_CMIE_Pos              (14U)

+#define USART_CR1_CMIE_Msk              (0x1UL << USART_CR1_CMIE_Pos)          /*!< 0x00004000 */

+#define USART_CR1_CMIE                  USART_CR1_CMIE_Msk                     /*!< Character match interrupt enable */

+#define USART_CR1_OVER8_Pos             (15U)

+#define USART_CR1_OVER8_Msk             (0x1UL << USART_CR1_OVER8_Pos)         /*!< 0x00008000 */

+#define USART_CR1_OVER8                 USART_CR1_OVER8_Msk                    /*!< Oversampling by 8-bit or 16-bit mode */

+#define USART_CR1_DEDT_Pos              (16U)

+#define USART_CR1_DEDT_Msk              (0x1FUL << USART_CR1_DEDT_Pos)         /*!< 0x001F0000 */

+#define USART_CR1_DEDT                  USART_CR1_DEDT_Msk                     /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */

+#define USART_CR1_DEDT_0                (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */

+#define USART_CR1_DEDT_1                (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */

+#define USART_CR1_DEDT_2                (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */

+#define USART_CR1_DEDT_3                (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */

+#define USART_CR1_DEDT_4                (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */

+#define USART_CR1_DEAT_Pos              (21U)

+#define USART_CR1_DEAT_Msk              (0x1FUL << USART_CR1_DEAT_Pos)         /*!< 0x03E00000 */

+#define USART_CR1_DEAT                  USART_CR1_DEAT_Msk                     /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */

+#define USART_CR1_DEAT_0                (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */

+#define USART_CR1_DEAT_1                (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */

+#define USART_CR1_DEAT_2                (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */

+#define USART_CR1_DEAT_3                (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */

+#define USART_CR1_DEAT_4                (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */

+#define USART_CR1_RTOIE_Pos             (26U)

+#define USART_CR1_RTOIE_Msk             (0x1UL << USART_CR1_RTOIE_Pos)         /*!< 0x04000000 */

+#define USART_CR1_RTOIE                 USART_CR1_RTOIE_Msk                    /*!< Receive Time Out interrupt enable */

+#define USART_CR1_EOBIE_Pos             (27U)

+#define USART_CR1_EOBIE_Msk             (0x1UL << USART_CR1_EOBIE_Pos)         /*!< 0x08000000 */

+#define USART_CR1_EOBIE                 USART_CR1_EOBIE_Msk                    /*!< End of Block interrupt enable */

+#define USART_CR1_M1_Pos                (28U)

+#define USART_CR1_M1_Msk                (0x1UL << USART_CR1_M1_Pos)            /*!< 0x10000000 */

+#define USART_CR1_M1                    USART_CR1_M1_Msk                       /*!< Word length - Bit 1 */

+#define USART_CR1_FIFOEN_Pos            (29U)

+#define USART_CR1_FIFOEN_Msk            (0x1UL << USART_CR1_FIFOEN_Pos)        /*!< 0x20000000 */

+#define USART_CR1_FIFOEN                USART_CR1_FIFOEN_Msk                   /*!< FIFO mode enable */

+#define USART_CR1_TXFEIE_Pos            (30U)

+#define USART_CR1_TXFEIE_Msk            (0x1UL << USART_CR1_TXFEIE_Pos)        /*!< 0x40000000 */

+#define USART_CR1_TXFEIE                USART_CR1_TXFEIE_Msk                   /*!< TXFIFO empty interrupt enable */

+#define USART_CR1_RXFFIE_Pos            (31U)

+#define USART_CR1_RXFFIE_Msk            (0x1UL << USART_CR1_RXFFIE_Pos)        /*!< 0x80000000 */

+#define USART_CR1_RXFFIE                USART_CR1_RXFFIE_Msk                   /*!< RXFIFO Full interrupt enable */

+

+/* Legacy define */

+#define  USART_CR1_RXNEIE  USART_CR1_RXNEIE_RXFNEIE

+#define  USART_CR1_TXEIE   USART_CR1_TXEIE_TXFNFIE

+

+/******************  Bit definition for USART_CR2 register  *******************/

+#define USART_CR2_SLVEN_Pos             (0U)

+#define USART_CR2_SLVEN_Msk             (0x1UL << USART_CR2_SLVEN_Pos)         /*!< 0x00000001 */

+#define USART_CR2_SLVEN                 USART_CR2_SLVEN_Msk                    /*!< Synchronous Slave mode Enable */

+#define USART_CR2_DIS_NSS_Pos           (3U)

+#define USART_CR2_DIS_NSS_Msk           (0x1UL << USART_CR2_DIS_NSS_Pos)       /*!< 0x00000008 */

+#define USART_CR2_DIS_NSS               USART_CR2_DIS_NSS_Msk                  /*!< Negative Slave Select (NSS) pin management */

+#define USART_CR2_ADDM7_Pos             (4U)

+#define USART_CR2_ADDM7_Msk             (0x1UL << USART_CR2_ADDM7_Pos)         /*!< 0x00000010 */

+#define USART_CR2_ADDM7                 USART_CR2_ADDM7_Msk                    /*!< 7-bit or 4-bit Address Detection */

+#define USART_CR2_LBDL_Pos              (5U)

+#define USART_CR2_LBDL_Msk              (0x1UL << USART_CR2_LBDL_Pos)          /*!< 0x00000020 */

+#define USART_CR2_LBDL                  USART_CR2_LBDL_Msk                     /*!< LIN Break Detection Length */

+#define USART_CR2_LBDIE_Pos             (6U)

+#define USART_CR2_LBDIE_Msk             (0x1UL << USART_CR2_LBDIE_Pos)         /*!< 0x00000040 */

+#define USART_CR2_LBDIE                 USART_CR2_LBDIE_Msk                    /*!< LIN Break Detection Interrupt Enable */

+#define USART_CR2_LBCL_Pos              (8U)

+#define USART_CR2_LBCL_Msk              (0x1UL << USART_CR2_LBCL_Pos)          /*!< 0x00000100 */

+#define USART_CR2_LBCL                  USART_CR2_LBCL_Msk                     /*!< Last Bit Clock pulse */

+#define USART_CR2_CPHA_Pos              (9U)

+#define USART_CR2_CPHA_Msk              (0x1UL << USART_CR2_CPHA_Pos)          /*!< 0x00000200 */

+#define USART_CR2_CPHA                  USART_CR2_CPHA_Msk                     /*!< Clock Phase */

+#define USART_CR2_CPOL_Pos              (10U)

+#define USART_CR2_CPOL_Msk              (0x1UL << USART_CR2_CPOL_Pos)          /*!< 0x00000400 */

+#define USART_CR2_CPOL                  USART_CR2_CPOL_Msk                     /*!< Clock Polarity */

+#define USART_CR2_CLKEN_Pos             (11U)

+#define USART_CR2_CLKEN_Msk             (0x1UL << USART_CR2_CLKEN_Pos)         /*!< 0x00000800 */

+#define USART_CR2_CLKEN                 USART_CR2_CLKEN_Msk                    /*!< Clock Enable */

+#define USART_CR2_STOP_Pos              (12U)

+#define USART_CR2_STOP_Msk              (0x3UL << USART_CR2_STOP_Pos)          /*!< 0x00003000 */

+#define USART_CR2_STOP                  USART_CR2_STOP_Msk                     /*!< STOP[1:0] bits (STOP bits) */

+#define USART_CR2_STOP_0                (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */

+#define USART_CR2_STOP_1                (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */

+#define USART_CR2_LINEN_Pos             (14U)

+#define USART_CR2_LINEN_Msk             (0x1UL << USART_CR2_LINEN_Pos)         /*!< 0x00004000 */

+#define USART_CR2_LINEN                 USART_CR2_LINEN_Msk                    /*!< LIN mode enable */

+#define USART_CR2_SWAP_Pos              (15U)

+#define USART_CR2_SWAP_Msk              (0x1UL << USART_CR2_SWAP_Pos)          /*!< 0x00008000 */

+#define USART_CR2_SWAP                  USART_CR2_SWAP_Msk                     /*!< SWAP TX/RX pins */

+#define USART_CR2_RXINV_Pos             (16U)

+#define USART_CR2_RXINV_Msk             (0x1UL << USART_CR2_RXINV_Pos)         /*!< 0x00010000 */

+#define USART_CR2_RXINV                 USART_CR2_RXINV_Msk                    /*!< RX pin active level inversion */

+#define USART_CR2_TXINV_Pos             (17U)

+#define USART_CR2_TXINV_Msk             (0x1UL << USART_CR2_TXINV_Pos)         /*!< 0x00020000 */

+#define USART_CR2_TXINV                 USART_CR2_TXINV_Msk                    /*!< TX pin active level inversion */

+#define USART_CR2_DATAINV_Pos           (18U)

+#define USART_CR2_DATAINV_Msk           (0x1UL << USART_CR2_DATAINV_Pos)       /*!< 0x00040000 */

+#define USART_CR2_DATAINV               USART_CR2_DATAINV_Msk                  /*!< Binary data inversion */

+#define USART_CR2_MSBFIRST_Pos          (19U)

+#define USART_CR2_MSBFIRST_Msk          (0x1UL << USART_CR2_MSBFIRST_Pos)      /*!< 0x00080000 */

+#define USART_CR2_MSBFIRST              USART_CR2_MSBFIRST_Msk                 /*!< Most Significant Bit First */

+#define USART_CR2_ABREN_Pos             (20U)

+#define USART_CR2_ABREN_Msk             (0x1UL << USART_CR2_ABREN_Pos)         /*!< 0x00100000 */

+#define USART_CR2_ABREN                 USART_CR2_ABREN_Msk                    /*!< Auto Baud-Rate Enable*/

+#define USART_CR2_ABRMODE_Pos           (21U)

+#define USART_CR2_ABRMODE_Msk           (0x3UL << USART_CR2_ABRMODE_Pos)       /*!< 0x00600000 */

+#define USART_CR2_ABRMODE               USART_CR2_ABRMODE_Msk                  /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */

+#define USART_CR2_ABRMODE_0             (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */

+#define USART_CR2_ABRMODE_1             (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */

+#define USART_CR2_RTOEN_Pos             (23U)

+#define USART_CR2_RTOEN_Msk             (0x1UL << USART_CR2_RTOEN_Pos)         /*!< 0x00800000 */

+#define USART_CR2_RTOEN                 USART_CR2_RTOEN_Msk                    /*!< Receiver Time-Out enable */

+#define USART_CR2_ADD_Pos               (24U)

+#define USART_CR2_ADD_Msk               (0xFFUL << USART_CR2_ADD_Pos)          /*!< 0xFF000000 */

+#define USART_CR2_ADD                   USART_CR2_ADD_Msk                      /*!< Address of the USART node */

+

+/******************  Bit definition for USART_CR3 register  *******************/

+#define USART_CR3_EIE_Pos               (0U)

+#define USART_CR3_EIE_Msk               (0x1UL << USART_CR3_EIE_Pos)           /*!< 0x00000001 */

+#define USART_CR3_EIE                   USART_CR3_EIE_Msk                      /*!< Error Interrupt Enable */

+#define USART_CR3_IREN_Pos              (1U)

+#define USART_CR3_IREN_Msk              (0x1UL << USART_CR3_IREN_Pos)          /*!< 0x00000002 */

+#define USART_CR3_IREN                  USART_CR3_IREN_Msk                     /*!< IrDA mode Enable */

+#define USART_CR3_IRLP_Pos              (2U)

+#define USART_CR3_IRLP_Msk              (0x1UL << USART_CR3_IRLP_Pos)          /*!< 0x00000004 */

+#define USART_CR3_IRLP                  USART_CR3_IRLP_Msk                     /*!< IrDA Low-Power */

+#define USART_CR3_HDSEL_Pos             (3U)

+#define USART_CR3_HDSEL_Msk             (0x1UL << USART_CR3_HDSEL_Pos)         /*!< 0x00000008 */

+#define USART_CR3_HDSEL                 USART_CR3_HDSEL_Msk                    /*!< Half-Duplex Selection */

+#define USART_CR3_NACK_Pos              (4U)

+#define USART_CR3_NACK_Msk              (0x1UL << USART_CR3_NACK_Pos)          /*!< 0x00000010 */

+#define USART_CR3_NACK                  USART_CR3_NACK_Msk                     /*!< SmartCard NACK enable */

+#define USART_CR3_SCEN_Pos              (5U)

+#define USART_CR3_SCEN_Msk              (0x1UL << USART_CR3_SCEN_Pos)          /*!< 0x00000020 */

+#define USART_CR3_SCEN                  USART_CR3_SCEN_Msk                     /*!< SmartCard mode enable */

+#define USART_CR3_DMAR_Pos              (6U)

+#define USART_CR3_DMAR_Msk              (0x1UL << USART_CR3_DMAR_Pos)          /*!< 0x00000040 */

+#define USART_CR3_DMAR                  USART_CR3_DMAR_Msk                     /*!< DMA Enable Receiver */

+#define USART_CR3_DMAT_Pos              (7U)

+#define USART_CR3_DMAT_Msk              (0x1UL << USART_CR3_DMAT_Pos)          /*!< 0x00000080 */

+#define USART_CR3_DMAT                  USART_CR3_DMAT_Msk                     /*!< DMA Enable Transmitter */

+#define USART_CR3_RTSE_Pos              (8U)

+#define USART_CR3_RTSE_Msk              (0x1UL << USART_CR3_RTSE_Pos)          /*!< 0x00000100 */

+#define USART_CR3_RTSE                  USART_CR3_RTSE_Msk                     /*!< RTS Enable */

+#define USART_CR3_CTSE_Pos              (9U)

+#define USART_CR3_CTSE_Msk              (0x1UL << USART_CR3_CTSE_Pos)          /*!< 0x00000200 */

+#define USART_CR3_CTSE                  USART_CR3_CTSE_Msk                     /*!< CTS Enable */

+#define USART_CR3_CTSIE_Pos             (10U)

+#define USART_CR3_CTSIE_Msk             (0x1UL << USART_CR3_CTSIE_Pos)         /*!< 0x00000400 */

+#define USART_CR3_CTSIE                 USART_CR3_CTSIE_Msk                    /*!< CTS Interrupt Enable */

+#define USART_CR3_ONEBIT_Pos            (11U)

+#define USART_CR3_ONEBIT_Msk            (0x1UL << USART_CR3_ONEBIT_Pos)        /*!< 0x00000800 */

+#define USART_CR3_ONEBIT                USART_CR3_ONEBIT_Msk                   /*!< One sample bit method enable */

+#define USART_CR3_OVRDIS_Pos            (12U)

+#define USART_CR3_OVRDIS_Msk            (0x1UL << USART_CR3_OVRDIS_Pos)        /*!< 0x00001000 */

+#define USART_CR3_OVRDIS                USART_CR3_OVRDIS_Msk                   /*!< Overrun Disable */

+#define USART_CR3_DDRE_Pos              (13U)

+#define USART_CR3_DDRE_Msk              (0x1UL << USART_CR3_DDRE_Pos)          /*!< 0x00002000 */

+#define USART_CR3_DDRE                  USART_CR3_DDRE_Msk                     /*!< DMA Disable on Reception Error */

+#define USART_CR3_DEM_Pos               (14U)

+#define USART_CR3_DEM_Msk               (0x1UL << USART_CR3_DEM_Pos)           /*!< 0x00004000 */

+#define USART_CR3_DEM                   USART_CR3_DEM_Msk                      /*!< Driver Enable Mode */

+#define USART_CR3_DEP_Pos               (15U)

+#define USART_CR3_DEP_Msk               (0x1UL << USART_CR3_DEP_Pos)           /*!< 0x00008000 */

+#define USART_CR3_DEP                   USART_CR3_DEP_Msk                      /*!< Driver Enable Polarity Selection */

+#define USART_CR3_SCARCNT_Pos           (17U)

+#define USART_CR3_SCARCNT_Msk           (0x7UL << USART_CR3_SCARCNT_Pos)       /*!< 0x000E0000 */

+#define USART_CR3_SCARCNT               USART_CR3_SCARCNT_Msk                  /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */

+#define USART_CR3_SCARCNT_0             (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */

+#define USART_CR3_SCARCNT_1             (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */

+#define USART_CR3_SCARCNT_2             (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */

+#define USART_CR3_WUS_Pos               (20U)

+#define USART_CR3_WUS_Msk               (0x3UL << USART_CR3_WUS_Pos)           /*!< 0x00300000 */

+#define USART_CR3_WUS                   USART_CR3_WUS_Msk                      /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */

+#define USART_CR3_WUS_0                 (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */

+#define USART_CR3_WUS_1                 (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */

+#define USART_CR3_WUFIE_Pos             (22U)

+#define USART_CR3_WUFIE_Msk             (0x1UL << USART_CR3_WUFIE_Pos)         /*!< 0x00400000 */

+#define USART_CR3_WUFIE                 USART_CR3_WUFIE_Msk                    /*!< Wake Up Interrupt Enable */

+#define USART_CR3_TXFTIE_Pos            (23U)

+#define USART_CR3_TXFTIE_Msk            (0x1UL << USART_CR3_TXFTIE_Pos)        /*!< 0x00800000 */

+#define USART_CR3_TXFTIE                USART_CR3_TXFTIE_Msk                   /*!< TXFIFO threshold interrupt enable */

+#define USART_CR3_TCBGTIE_Pos           (24U)

+#define USART_CR3_TCBGTIE_Msk           (0x1UL << USART_CR3_TCBGTIE_Pos)       /*!< 0x01000000 */

+#define USART_CR3_TCBGTIE               USART_CR3_TCBGTIE_Msk                  /*!< Transmission Complete before guard time, interrupt enable */

+#define USART_CR3_RXFTCFG_Pos           (25U)

+#define USART_CR3_RXFTCFG_Msk           (0x7UL << USART_CR3_RXFTCFG_Pos)       /*!< 0x0E000000 */

+#define USART_CR3_RXFTCFG               USART_CR3_RXFTCFG_Msk                  /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */

+#define USART_CR3_RXFTCFG_0             (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */

+#define USART_CR3_RXFTCFG_1             (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */

+#define USART_CR3_RXFTCFG_2             (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */

+#define USART_CR3_RXFTIE_Pos            (28U)

+#define USART_CR3_RXFTIE_Msk            (0x1UL << USART_CR3_RXFTIE_Pos)        /*!< 0x10000000 */

+#define USART_CR3_RXFTIE                USART_CR3_RXFTIE_Msk                   /*!< RXFIFO threshold interrupt enable */

+#define USART_CR3_TXFTCFG_Pos           (29U)

+#define USART_CR3_TXFTCFG_Msk           (0x7UL << USART_CR3_TXFTCFG_Pos)       /*!< 0xE0000000 */

+#define USART_CR3_TXFTCFG               USART_CR3_TXFTCFG_Msk                  /*!< TXFIFO [2:0] threshold configuration */

+#define USART_CR3_TXFTCFG_0             (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */

+#define USART_CR3_TXFTCFG_1             (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */

+#define USART_CR3_TXFTCFG_2             (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */

+

+/******************  Bit definition for USART_BRR register  *******************/

+#define USART_BRR_DIV_FRACTION_Pos      (0U)

+#define USART_BRR_DIV_FRACTION_Msk      (0xFUL << USART_BRR_DIV_FRACTION_Pos)  /*!< 0x0000000F */

+#define USART_BRR_DIV_FRACTION          USART_BRR_DIV_FRACTION_Msk             /*!< Fraction of USARTDIV */

+#define USART_BRR_DIV_MANTISSA_Pos      (4U)

+#define USART_BRR_DIV_MANTISSA_Msk      (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */

+#define USART_BRR_DIV_MANTISSA          USART_BRR_DIV_MANTISSA_Msk             /*!< Mantissa of USARTDIV */

+

+/******************  Bit definition for USART_GTPR register  ******************/

+#define USART_GTPR_PSC_Pos              (0U)

+#define USART_GTPR_PSC_Msk              (0xFFUL << USART_GTPR_PSC_Pos)         /*!< 0x000000FF */

+#define USART_GTPR_PSC                  USART_GTPR_PSC_Msk                     /*!< PSC[7:0] bits (Prescaler value) */

+#define USART_GTPR_GT_Pos               (8U)

+#define USART_GTPR_GT_Msk               (0xFFUL << USART_GTPR_GT_Pos)          /*!< 0x0000FF00 */

+#define USART_GTPR_GT                   USART_GTPR_GT_Msk                      /*!< GT[7:0] bits (Guard time value) */

+

+/*******************  Bit definition for USART_RTOR register  *****************/

+#define USART_RTOR_RTO_Pos              (0U)

+#define USART_RTOR_RTO_Msk              (0xFFFFFFUL << USART_RTOR_RTO_Pos)     /*!< 0x00FFFFFF */

+#define USART_RTOR_RTO                  USART_RTOR_RTO_Msk                     /*!< Receiver Time Out Value */

+#define USART_RTOR_BLEN_Pos             (24U)

+#define USART_RTOR_BLEN_Msk             (0xFFUL << USART_RTOR_BLEN_Pos)        /*!< 0xFF000000 */

+#define USART_RTOR_BLEN                 USART_RTOR_BLEN_Msk                    /*!< Block Length */

+

+/*******************  Bit definition for USART_RQR register  ******************/

+#define USART_RQR_ABRRQ_Pos             (0U)

+#define USART_RQR_ABRRQ_Msk             (0x1UL << USART_RQR_ABRRQ_Pos)         /*!< 0x00000001 */

+#define USART_RQR_ABRRQ                 USART_RQR_ABRRQ_Msk                    /*!< Auto-Baud Rate Request */

+#define USART_RQR_SBKRQ_Pos             (1U)

+#define USART_RQR_SBKRQ_Msk             (0x1UL << USART_RQR_SBKRQ_Pos)         /*!< 0x00000002 */

+#define USART_RQR_SBKRQ                 USART_RQR_SBKRQ_Msk                    /*!< Send Break Request */

+#define USART_RQR_MMRQ_Pos              (2U)

+#define USART_RQR_MMRQ_Msk              (0x1UL << USART_RQR_MMRQ_Pos)          /*!< 0x00000004 */

+#define USART_RQR_MMRQ                  USART_RQR_MMRQ_Msk                     /*!< Mute Mode Request */

+#define USART_RQR_RXFRQ_Pos             (3U)

+#define USART_RQR_RXFRQ_Msk             (0x1UL << USART_RQR_RXFRQ_Pos)         /*!< 0x00000008 */

+#define USART_RQR_RXFRQ                 USART_RQR_RXFRQ_Msk                    /*!< Receive Data flush Request */

+#define USART_RQR_TXFRQ_Pos             (4U)

+#define USART_RQR_TXFRQ_Msk             (0x1UL << USART_RQR_TXFRQ_Pos)         /*!< 0x00000010 */

+#define USART_RQR_TXFRQ                 USART_RQR_TXFRQ_Msk                    /*!< Transmit data flush Request */

+

+/*******************  Bit definition for USART_ISR register  ******************/

+#define USART_ISR_PE_Pos                (0U)

+#define USART_ISR_PE_Msk                (0x1UL << USART_ISR_PE_Pos)            /*!< 0x00000001 */

+#define USART_ISR_PE                    USART_ISR_PE_Msk                       /*!< Parity Error */

+#define USART_ISR_FE_Pos                (1U)

+#define USART_ISR_FE_Msk                (0x1UL << USART_ISR_FE_Pos)            /*!< 0x00000002 */

+#define USART_ISR_FE                    USART_ISR_FE_Msk                       /*!< Framing Error */

+#define USART_ISR_NE_Pos                (2U)

+#define USART_ISR_NE_Msk                (0x1UL << USART_ISR_NE_Pos)            /*!< 0x00000004 */

+#define USART_ISR_NE                    USART_ISR_NE_Msk                       /*!< Noise detected Flag */

+#define USART_ISR_ORE_Pos               (3U)

+#define USART_ISR_ORE_Msk               (0x1UL << USART_ISR_ORE_Pos)           /*!< 0x00000008 */

+#define USART_ISR_ORE                   USART_ISR_ORE_Msk                      /*!< OverRun Error */

+#define USART_ISR_IDLE_Pos              (4U)

+#define USART_ISR_IDLE_Msk              (0x1UL << USART_ISR_IDLE_Pos)          /*!< 0x00000010 */

+#define USART_ISR_IDLE                  USART_ISR_IDLE_Msk                     /*!< IDLE line detected */

+#define USART_ISR_RXNE_RXFNE_Pos        (5U)

+#define USART_ISR_RXNE_RXFNE_Msk        (0x1UL << USART_ISR_RXNE_RXFNE_Pos)    /*!< 0x00000020 */

+#define USART_ISR_RXNE_RXFNE            USART_ISR_RXNE_RXFNE_Msk               /*!< Read Data Register or RX FIFO Not Empty */

+#define USART_ISR_TC_Pos                (6U)

+#define USART_ISR_TC_Msk                (0x1UL << USART_ISR_TC_Pos)            /*!< 0x00000040 */

+#define USART_ISR_TC                    USART_ISR_TC_Msk                       /*!< Transmission Complete */

+#define USART_ISR_TXE_TXFNF_Pos         (7U)

+#define USART_ISR_TXE_TXFNF_Msk         (0x1UL << USART_ISR_TXE_TXFNF_Pos)     /*!< 0x00000080 */

+#define USART_ISR_TXE_TXFNF             USART_ISR_TXE_TXFNF_Msk                /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */

+#define USART_ISR_LBDF_Pos              (8U)

+#define USART_ISR_LBDF_Msk              (0x1UL << USART_ISR_LBDF_Pos)          /*!< 0x00000100 */

+#define USART_ISR_LBDF                  USART_ISR_LBDF_Msk                     /*!< LIN Break Detection Flag */

+#define USART_ISR_CTSIF_Pos             (9U)

+#define USART_ISR_CTSIF_Msk             (0x1UL << USART_ISR_CTSIF_Pos)         /*!< 0x00000200 */

+#define USART_ISR_CTSIF                 USART_ISR_CTSIF_Msk                    /*!< CTS interrupt flag */

+#define USART_ISR_CTS_Pos               (10U)

+#define USART_ISR_CTS_Msk               (0x1UL << USART_ISR_CTS_Pos)           /*!< 0x00000400 */

+#define USART_ISR_CTS                   USART_ISR_CTS_Msk                      /*!< CTS flag */

+#define USART_ISR_RTOF_Pos              (11U)

+#define USART_ISR_RTOF_Msk              (0x1UL << USART_ISR_RTOF_Pos)          /*!< 0x00000800 */

+#define USART_ISR_RTOF                  USART_ISR_RTOF_Msk                     /*!< Receiver Time Out */

+#define USART_ISR_EOBF_Pos              (12U)

+#define USART_ISR_EOBF_Msk              (0x1UL << USART_ISR_EOBF_Pos)          /*!< 0x00001000 */

+#define USART_ISR_EOBF                  USART_ISR_EOBF_Msk                     /*!< End Of Block Flag */

+#define USART_ISR_UDR_Pos               (13U)

+#define USART_ISR_UDR_Msk               (0x1UL << USART_ISR_UDR_Pos)           /*!< 0x00002000 */

+#define USART_ISR_UDR                   USART_ISR_UDR_Msk                      /*!< SPI slave underrun error flag */

+#define USART_ISR_ABRE_Pos              (14U)

+#define USART_ISR_ABRE_Msk              (0x1UL << USART_ISR_ABRE_Pos)          /*!< 0x00004000 */

+#define USART_ISR_ABRE                  USART_ISR_ABRE_Msk                     /*!< Auto-Baud Rate Error */

+#define USART_ISR_ABRF_Pos              (15U)

+#define USART_ISR_ABRF_Msk              (0x1UL << USART_ISR_ABRF_Pos)          /*!< 0x00008000 */

+#define USART_ISR_ABRF                  USART_ISR_ABRF_Msk                     /*!< Auto-Baud Rate Flag */

+#define USART_ISR_BUSY_Pos              (16U)

+#define USART_ISR_BUSY_Msk              (0x1UL << USART_ISR_BUSY_Pos)          /*!< 0x00010000 */

+#define USART_ISR_BUSY                  USART_ISR_BUSY_Msk                     /*!< Busy Flag */

+#define USART_ISR_CMF_Pos               (17U)

+#define USART_ISR_CMF_Msk               (0x1UL << USART_ISR_CMF_Pos)           /*!< 0x00020000 */

+#define USART_ISR_CMF                   USART_ISR_CMF_Msk                      /*!< Character Match Flag */

+#define USART_ISR_SBKF_Pos              (18U)

+#define USART_ISR_SBKF_Msk              (0x1UL << USART_ISR_SBKF_Pos)          /*!< 0x00040000 */

+#define USART_ISR_SBKF                  USART_ISR_SBKF_Msk                     /*!< Send Break Flag */

+#define USART_ISR_RWU_Pos               (19U)

+#define USART_ISR_RWU_Msk               (0x1UL << USART_ISR_RWU_Pos)           /*!< 0x00080000 */

+#define USART_ISR_RWU                   USART_ISR_RWU_Msk                      /*!< Receive Wake Up from mute mode Flag */

+#define USART_ISR_WUF_Pos               (20U)

+#define USART_ISR_WUF_Msk               (0x1UL << USART_ISR_WUF_Pos)           /*!< 0x00100000 */

+#define USART_ISR_WUF                   USART_ISR_WUF_Msk                      /*!< Wake Up from stop mode Flag */

+#define USART_ISR_TEACK_Pos             (21U)

+#define USART_ISR_TEACK_Msk             (0x1UL << USART_ISR_TEACK_Pos)         /*!< 0x00200000 */

+#define USART_ISR_TEACK                 USART_ISR_TEACK_Msk                    /*!< Transmit Enable Acknowledge Flag */

+#define USART_ISR_REACK_Pos             (22U)

+#define USART_ISR_REACK_Msk             (0x1UL << USART_ISR_REACK_Pos)         /*!< 0x00400000 */

+#define USART_ISR_REACK                 USART_ISR_REACK_Msk                    /*!< Receive Enable Acknowledge Flag */

+#define USART_ISR_TXFE_Pos              (23U)

+#define USART_ISR_TXFE_Msk              (0x1UL << USART_ISR_TXFE_Pos)          /*!< 0x00800000 */

+#define USART_ISR_TXFE                  USART_ISR_TXFE_Msk                     /*!< TXFIFO Empty */

+#define USART_ISR_RXFF_Pos              (24U)

+#define USART_ISR_RXFF_Msk              (0x1UL << USART_ISR_RXFF_Pos)          /*!< 0x01000000 */

+#define USART_ISR_RXFF                  USART_ISR_RXFF_Msk                     /*!< RXFIFO Full Flag */

+#define USART_ISR_TCBGT_Pos             (25U)

+#define USART_ISR_TCBGT_Msk             (0x1UL << USART_ISR_TCBGT_Pos)         /*!< 0x02000000 */

+#define USART_ISR_TCBGT                 USART_ISR_TCBGT_Msk                    /*!< Transmission complete before guard time Flag */

+#define USART_ISR_RXFT_Pos              (26U)

+#define USART_ISR_RXFT_Msk              (0x1UL << USART_ISR_RXFT_Pos)          /*!< 0x04000000 */

+#define USART_ISR_RXFT                  USART_ISR_RXFT_Msk                     /*!< RXFIFO threshold Flag */

+#define USART_ISR_TXFT_Pos              (27U)

+#define USART_ISR_TXFT_Msk              (0x1UL << USART_ISR_TXFT_Pos)          /*!< 0x08000000 */

+#define USART_ISR_TXFT                  USART_ISR_TXFT_Msk                     /*!< TXFIFO threshold Flag */

+

+/*******************  Bit definition for USART_ICR register  ******************/

+#define USART_ICR_PECF_Pos              (0U)

+#define USART_ICR_PECF_Msk              (0x1UL << USART_ICR_PECF_Pos)          /*!< 0x00000001 */

+#define USART_ICR_PECF                  USART_ICR_PECF_Msk                     /*!< Parity Error Clear Flag */

+#define USART_ICR_FECF_Pos              (1U)

+#define USART_ICR_FECF_Msk              (0x1UL << USART_ICR_FECF_Pos)          /*!< 0x00000002 */

+#define USART_ICR_FECF                  USART_ICR_FECF_Msk                     /*!< Framing Error Clear Flag */

+#define USART_ICR_NECF_Pos              (2U)

+#define USART_ICR_NECF_Msk              (0x1UL << USART_ICR_NECF_Pos)          /*!< 0x00000004 */

+#define USART_ICR_NECF                  USART_ICR_NECF_Msk                     /*!< Noise detected Clear Flag */

+#define USART_ICR_ORECF_Pos             (3U)

+#define USART_ICR_ORECF_Msk             (0x1UL << USART_ICR_ORECF_Pos)         /*!< 0x00000008 */

+#define USART_ICR_ORECF                 USART_ICR_ORECF_Msk                    /*!< OverRun Error Clear Flag */

+#define USART_ICR_IDLECF_Pos            (4U)

+#define USART_ICR_IDLECF_Msk            (0x1UL << USART_ICR_IDLECF_Pos)        /*!< 0x00000010 */

+#define USART_ICR_IDLECF                USART_ICR_IDLECF_Msk                   /*!< IDLE line detected Clear Flag */

+#define USART_ICR_TXFECF_Pos            (5U)

+#define USART_ICR_TXFECF_Msk            (0x1UL << USART_ICR_TXFECF_Pos)        /*!< 0x00000020 */

+#define USART_ICR_TXFECF                USART_ICR_TXFECF_Msk                   /*!< TXFIFO empty clear flag */

+#define USART_ICR_TCCF_Pos              (6U)

+#define USART_ICR_TCCF_Msk              (0x1UL << USART_ICR_TCCF_Pos)          /*!< 0x00000040 */

+#define USART_ICR_TCCF                  USART_ICR_TCCF_Msk                     /*!< Transmission Complete Clear Flag */

+#define USART_ICR_TCBGTCF_Pos           (7U)

+#define USART_ICR_TCBGTCF_Msk           (0x1UL << USART_ICR_TCBGTCF_Pos)       /*!< 0x00000080 */

+#define USART_ICR_TCBGTCF               USART_ICR_TCBGTCF_Msk                  /*!< Transmission complete before guard time Clear Flag */

+#define USART_ICR_LBDCF_Pos             (8U)

+#define USART_ICR_LBDCF_Msk             (0x1UL << USART_ICR_LBDCF_Pos)         /*!< 0x00000100 */

+#define USART_ICR_LBDCF                 USART_ICR_LBDCF_Msk                    /*!< LIN Break Detection Clear Flag */

+#define USART_ICR_CTSCF_Pos             (9U)

+#define USART_ICR_CTSCF_Msk             (0x1UL << USART_ICR_CTSCF_Pos)         /*!< 0x00000200 */

+#define USART_ICR_CTSCF                 USART_ICR_CTSCF_Msk                    /*!< CTS Interrupt Clear Flag */

+#define USART_ICR_RTOCF_Pos             (11U)

+#define USART_ICR_RTOCF_Msk             (0x1UL << USART_ICR_RTOCF_Pos)         /*!< 0x00000800 */

+#define USART_ICR_RTOCF                 USART_ICR_RTOCF_Msk                    /*!< Receiver Time Out Clear Flag */

+#define USART_ICR_EOBCF_Pos             (12U)

+#define USART_ICR_EOBCF_Msk             (0x1UL << USART_ICR_EOBCF_Pos)         /*!< 0x00001000 */

+#define USART_ICR_EOBCF                 USART_ICR_EOBCF_Msk                    /*!< End Of Block Clear Flag */

+#define USART_ICR_UDRCF_Pos             (13U)

+#define USART_ICR_UDRCF_Msk             (0x1UL << USART_ICR_UDRCF_Pos)         /*!< 0x00002000 */

+#define USART_ICR_UDRCF                 USART_ICR_UDRCF_Msk                    /*!< SPI slave underrun clear flag */

+#define USART_ICR_CMCF_Pos              (17U)

+#define USART_ICR_CMCF_Msk              (0x1UL << USART_ICR_CMCF_Pos)          /*!< 0x00020000 */

+#define USART_ICR_CMCF                  USART_ICR_CMCF_Msk                     /*!< Character Match Clear Flag */

+#define USART_ICR_WUCF_Pos              (20U)

+#define USART_ICR_WUCF_Msk              (0x1UL << USART_ICR_WUCF_Pos)          /*!< 0x00100000 */

+#define USART_ICR_WUCF                  USART_ICR_WUCF_Msk                     /*!< Wake Up from stop mode Clear Flag */

+

+/*******************  Bit definition for USART_RDR register  ******************/

+#define USART_RDR_RDR_Pos               (0U)

+#define USART_RDR_RDR_Msk               (0x1FFUL << USART_RDR_RDR_Pos)         /*!< 0x000001FF */

+#define USART_RDR_RDR                   USART_RDR_RDR_Msk                      /*!< RDR[8:0] bits (Receive Data value) */

+

+/*******************  Bit definition for USART_TDR register  ******************/

+#define USART_TDR_TDR_Pos               (0U)

+#define USART_TDR_TDR_Msk               (0x1FFUL << USART_TDR_TDR_Pos)         /*!< 0x000001FF */

+#define USART_TDR_TDR                   USART_TDR_TDR_Msk                      /*!< TDR[8:0] bits (Transmit Data value) */

+

+/*******************  Bit definition for USART_PRESC register  ******************/

+#define USART_PRESC_PRESCALER_Pos       (0U)

+#define USART_PRESC_PRESCALER_Msk       (0xFUL << USART_PRESC_PRESCALER_Pos)   /*!< 0x0000000F */

+#define USART_PRESC_PRESCALER           USART_PRESC_PRESCALER_Msk              /*!< PRESCALER[3:0] bits (Clock prescaler) */

+#define USART_PRESC_PRESCALER_0         (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */

+#define USART_PRESC_PRESCALER_1         (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */

+#define USART_PRESC_PRESCALER_2         (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */

+#define USART_PRESC_PRESCALER_3         (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */

+

+/******************************************************************************/

+/*                                                                            */

+/*           Single Wire Protocol Master Interface (SWPMI)                    */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for SWPMI_CR register   ********************/

+#define SWPMI_CR_RXDMA_Pos       (0U)

+#define SWPMI_CR_RXDMA_Msk       (0x1UL << SWPMI_CR_RXDMA_Pos)                 /*!< 0x00000001 */

+#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */

+#define SWPMI_CR_TXDMA_Pos       (1U)

+#define SWPMI_CR_TXDMA_Msk       (0x1UL << SWPMI_CR_TXDMA_Pos)                 /*!< 0x00000002 */

+#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */

+#define SWPMI_CR_RXMODE_Pos      (2U)

+#define SWPMI_CR_RXMODE_Msk      (0x1UL << SWPMI_CR_RXMODE_Pos)                /*!< 0x00000004 */

+#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */

+#define SWPMI_CR_TXMODE_Pos      (3U)

+#define SWPMI_CR_TXMODE_Msk      (0x1UL << SWPMI_CR_TXMODE_Pos)                /*!< 0x00000008 */

+#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */

+#define SWPMI_CR_LPBK_Pos        (4U)

+#define SWPMI_CR_LPBK_Msk        (0x1UL << SWPMI_CR_LPBK_Pos)                  /*!< 0x00000010 */

+#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */

+#define SWPMI_CR_SWPACT_Pos      (5U)

+#define SWPMI_CR_SWPACT_Msk      (0x1UL << SWPMI_CR_SWPACT_Pos)                /*!< 0x00000020 */

+#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */

+#define SWPMI_CR_DEACT_Pos       (10U)

+#define SWPMI_CR_DEACT_Msk       (0x1UL << SWPMI_CR_DEACT_Pos)                 /*!< 0x00000400 */

+#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */

+#define SWPMI_CR_SWPEN_Pos       (11U)

+#define SWPMI_CR_SWPEN_Msk       (0x1UL << SWPMI_CR_SWPEN_Pos)                 /*!< 0x00000800 */

+#define SWPMI_CR_SWPEN           SWPMI_CR_SWPEN_Msk                            /*!<Single wire protocol master transceiver enable       */

+

+/*******************  Bit definition for SWPMI_BRR register  ********************/

+#define SWPMI_BRR_BR_Pos         (0U)

+#define SWPMI_BRR_BR_Msk         (0xFFUL << SWPMI_BRR_BR_Pos)                  /*!< 0x000000FF */

+#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[7:0] bits (Bitrate prescaler) */

+

+/*******************  Bit definition for SWPMI_ISR register  ********************/

+#define SWPMI_ISR_RXBFF_Pos      (0U)

+#define SWPMI_ISR_RXBFF_Msk      (0x1UL << SWPMI_ISR_RXBFF_Pos)                /*!< 0x00000001 */

+#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */

+#define SWPMI_ISR_TXBEF_Pos      (1U)

+#define SWPMI_ISR_TXBEF_Msk      (0x1UL << SWPMI_ISR_TXBEF_Pos)                /*!< 0x00000002 */

+#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */

+#define SWPMI_ISR_RXBERF_Pos     (2U)

+#define SWPMI_ISR_RXBERF_Msk     (0x1UL << SWPMI_ISR_RXBERF_Pos)               /*!< 0x00000004 */

+#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */

+#define SWPMI_ISR_RXOVRF_Pos     (3U)

+#define SWPMI_ISR_RXOVRF_Msk     (0x1UL << SWPMI_ISR_RXOVRF_Pos)               /*!< 0x00000008 */

+#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */

+#define SWPMI_ISR_TXUNRF_Pos     (4U)

+#define SWPMI_ISR_TXUNRF_Msk     (0x1UL << SWPMI_ISR_TXUNRF_Pos)               /*!< 0x00000010 */

+#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */

+#define SWPMI_ISR_RXNE_Pos       (5U)

+#define SWPMI_ISR_RXNE_Msk       (0x1UL << SWPMI_ISR_RXNE_Pos)                 /*!< 0x00000020 */

+#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */

+#define SWPMI_ISR_TXE_Pos        (6U)

+#define SWPMI_ISR_TXE_Msk        (0x1UL << SWPMI_ISR_TXE_Pos)                  /*!< 0x00000040 */

+#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */

+#define SWPMI_ISR_TCF_Pos        (7U)

+#define SWPMI_ISR_TCF_Msk        (0x1UL << SWPMI_ISR_TCF_Pos)                  /*!< 0x00000080 */

+#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */

+#define SWPMI_ISR_SRF_Pos        (8U)

+#define SWPMI_ISR_SRF_Msk        (0x1UL << SWPMI_ISR_SRF_Pos)                  /*!< 0x00000100 */

+#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */

+#define SWPMI_ISR_SUSP_Pos       (9U)

+#define SWPMI_ISR_SUSP_Msk       (0x1UL << SWPMI_ISR_SUSP_Pos)                 /*!< 0x00000200 */

+#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */

+#define SWPMI_ISR_DEACTF_Pos     (10U)

+#define SWPMI_ISR_DEACTF_Msk     (0x1UL << SWPMI_ISR_DEACTF_Pos)               /*!< 0x00000400 */

+#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */

+#define SWPMI_ISR_RDYF_Pos       (11U)

+#define SWPMI_ISR_RDYF_Msk       (0x1UL << SWPMI_ISR_RDYF_Pos)                 /*!< 0x00000800 */

+#define SWPMI_ISR_RDYF           SWPMI_ISR_RDYF_Msk                            /*!<Transceiver ready flag          */

+

+/*******************  Bit definition for SWPMI_ICR register  ********************/

+#define SWPMI_ICR_CRXBFF_Pos     (0U)

+#define SWPMI_ICR_CRXBFF_Msk     (0x1UL << SWPMI_ICR_CRXBFF_Pos)               /*!< 0x00000001 */

+#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */

+#define SWPMI_ICR_CTXBEF_Pos     (1U)

+#define SWPMI_ICR_CTXBEF_Msk     (0x1UL << SWPMI_ICR_CTXBEF_Pos)               /*!< 0x00000002 */

+#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */

+#define SWPMI_ICR_CRXBERF_Pos    (2U)

+#define SWPMI_ICR_CRXBERF_Msk    (0x1UL << SWPMI_ICR_CRXBERF_Pos)              /*!< 0x00000004 */

+#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */

+#define SWPMI_ICR_CRXOVRF_Pos    (3U)

+#define SWPMI_ICR_CRXOVRF_Msk    (0x1UL << SWPMI_ICR_CRXOVRF_Pos)              /*!< 0x00000008 */

+#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */

+#define SWPMI_ICR_CTXUNRF_Pos    (4U)

+#define SWPMI_ICR_CTXUNRF_Msk    (0x1UL << SWPMI_ICR_CTXUNRF_Pos)              /*!< 0x00000010 */

+#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */

+#define SWPMI_ICR_CTCF_Pos       (7U)

+#define SWPMI_ICR_CTCF_Msk       (0x1UL << SWPMI_ICR_CTCF_Pos)                 /*!< 0x00000080 */

+#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */

+#define SWPMI_ICR_CSRF_Pos       (8U)

+#define SWPMI_ICR_CSRF_Msk       (0x1UL << SWPMI_ICR_CSRF_Pos)                 /*!< 0x00000100 */

+#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */

+#define SWPMI_ICR_CRDYF_Pos      (11U)

+#define SWPMI_ICR_CRDYF_Msk      (0x1UL << SWPMI_ICR_CRDYF_Pos)                /*!< 0x00000800 */

+#define SWPMI_ICR_CRDYF          SWPMI_ICR_CRDYF_Msk                           /*!<Clear transceiver ready flag         */

+

+/*******************  Bit definition for SWPMI_IER register  ********************/

+#define SWPMI_IER_RXBFIE_Pos     (0U)

+#define SWPMI_IER_RXBFIE_Msk     (0x1UL << SWPMI_IER_RXBFIE_Pos)               /*!< 0x00000001 */

+#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */

+#define SWPMI_IER_TXBEIE_Pos     (1U)

+#define SWPMI_IER_TXBEIE_Msk     (0x1UL << SWPMI_IER_TXBEIE_Pos)               /*!< 0x00000002 */

+#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */

+#define SWPMI_IER_RXBERIE_Pos    (2U)

+#define SWPMI_IER_RXBERIE_Msk    (0x1UL << SWPMI_IER_RXBERIE_Pos)              /*!< 0x00000004 */

+#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */

+#define SWPMI_IER_RXOVRIE_Pos    (3U)

+#define SWPMI_IER_RXOVRIE_Msk    (0x1UL << SWPMI_IER_RXOVRIE_Pos)              /*!< 0x00000008 */

+#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */

+#define SWPMI_IER_TXUNRIE_Pos    (4U)

+#define SWPMI_IER_TXUNRIE_Msk    (0x1UL << SWPMI_IER_TXUNRIE_Pos)              /*!< 0x00000010 */

+#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */

+#define SWPMI_IER_RIE_Pos        (5U)

+#define SWPMI_IER_RIE_Msk        (0x1UL << SWPMI_IER_RIE_Pos)                  /*!< 0x00000020 */

+#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */

+#define SWPMI_IER_TIE_Pos        (6U)

+#define SWPMI_IER_TIE_Msk        (0x1UL << SWPMI_IER_TIE_Pos)                  /*!< 0x00000040 */

+#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */

+#define SWPMI_IER_TCIE_Pos       (7U)

+#define SWPMI_IER_TCIE_Msk       (0x1UL << SWPMI_IER_TCIE_Pos)                 /*!< 0x00000080 */

+#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */

+#define SWPMI_IER_SRIE_Pos       (8U)

+#define SWPMI_IER_SRIE_Msk       (0x1UL << SWPMI_IER_SRIE_Pos)                 /*!< 0x00000100 */

+#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */

+#define SWPMI_IER_RDYIE_Pos      (11U)

+#define SWPMI_IER_RDYIE_Msk      (0x1UL << SWPMI_IER_RDYIE_Pos)                /*!< 0x00000800 */

+#define SWPMI_IER_RDYIE          SWPMI_IER_RDYIE_Msk                           /*!<Transceiver ready interrupt enable          */

+

+/*******************  Bit definition for SWPMI_RFL register  ********************/

+#define SWPMI_RFL_RFL_Pos        (0U)

+#define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */

+#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */

+#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */

+

+/*******************  Bit definition for SWPMI_TDR register  ********************/

+#define SWPMI_TDR_TD_Pos         (0U)

+#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)            /*!< 0xFFFFFFFF */

+#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */

+

+/*******************  Bit definition for SWPMI_RDR register  ********************/

+#define SWPMI_RDR_RD_Pos         (0U)

+#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)            /*!< 0xFFFFFFFF */

+#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Recive Data Register           */

+

+

+/*******************  Bit definition for SWPMI_OR register  ********************/

+#define SWPMI_OR_TBYP_Pos        (0U)

+#define SWPMI_OR_TBYP_Msk        (0x1UL << SWPMI_OR_TBYP_Pos)                  /*!< 0x00000001 */

+#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */

+#define SWPMI_OR_CLASS_Pos       (1U)

+#define SWPMI_OR_CLASS_Msk       (0x1UL << SWPMI_OR_CLASS_Pos)                 /*!< 0x00000002 */

+#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP CLASS selection */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            Window WATCHDOG                                 */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for WWDG_CR register  ********************/

+#define WWDG_CR_T_Pos           (0U)

+#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */

+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */

+#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */

+#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */

+#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */

+#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */

+#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */

+#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */

+#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */

+

+#define WWDG_CR_WDGA_Pos        (7U)

+#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */

+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */

+

+/*******************  Bit definition for WWDG_CFR register  *******************/

+#define WWDG_CFR_W_Pos          (0U)

+#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */

+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */

+#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */

+#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */

+#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */

+#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */

+#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */

+#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */

+#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */

+

+#define WWDG_CFR_EWI_Pos        (9U)

+#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */

+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */

+

+#define WWDG_CFR_WDGTB_Pos      (11U)

+#define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */

+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */

+#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000800 */

+#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00001000 */

+#define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00002000 */

+

+/*******************  Bit definition for WWDG_SR register  ********************/

+#define WWDG_SR_EWIF_Pos        (0U)

+#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */

+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                DBG                                         */

+/*                                                                            */

+/******************************************************************************/

+/*********************************  DEVICE ID  ********************************/

+#define STM32H7_DEV_ID           0x480UL

+

+/********************  Bit definition for DBGMCU_IDCODE register  *************/

+#define DBGMCU_IDCODE_DEV_ID_Pos          (0U)

+#define DBGMCU_IDCODE_DEV_ID_Msk          (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */

+#define DBGMCU_IDCODE_DEV_ID              DBGMCU_IDCODE_DEV_ID_Msk

+#define DBGMCU_IDCODE_REV_ID_Pos          (16U)

+#define DBGMCU_IDCODE_REV_ID_Msk          (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */

+#define DBGMCU_IDCODE_REV_ID              DBGMCU_IDCODE_REV_ID_Msk

+

+/********************  Bit definition for DBGMCU_CR register  *****************/

+#define DBGMCU_CR_DBG_SLEEPCD_Pos         (0U)

+#define DBGMCU_CR_DBG_SLEEPCD_Msk         (0x1UL << DBGMCU_CR_DBG_SLEEPCD_Pos) /*!< 0x00000001 */

+#define DBGMCU_CR_DBG_SLEEPCD             DBGMCU_CR_DBG_SLEEPCD_Msk

+#define DBGMCU_CR_DBG_STOPCD_Pos          (1U)

+#define DBGMCU_CR_DBG_STOPCD_Msk          (0x1UL << DBGMCU_CR_DBG_STOPCD_Pos)  /*!< 0x00000002 */

+#define DBGMCU_CR_DBG_STOPCD              DBGMCU_CR_DBG_STOPCD_Msk

+#define DBGMCU_CR_DBG_STANDBYCD_Pos       (2U)

+#define DBGMCU_CR_DBG_STANDBYCD_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYCD_Pos) /*!< 0x00000004 */

+#define DBGMCU_CR_DBG_STANDBYCD           DBGMCU_CR_DBG_STANDBYCD_Msk

+

+/* Legacy defines */

+#define DBGMCU_CR_DBG_SLEEPD1_Pos         DBGMCU_CR_DBG_SLEEPCD_Pos

+#define DBGMCU_CR_DBG_SLEEPD1_Msk         DBGMCU_CR_DBG_SLEEPCD_Msk

+#define DBGMCU_CR_DBG_SLEEPD1             DBGMCU_CR_DBG_SLEEPCD

+#define DBGMCU_CR_DBG_STOPD1_Pos          DBGMCU_CR_DBG_STOPCD_Pos

+#define DBGMCU_CR_DBG_STOPD1_Msk          DBGMCU_CR_DBG_STOPCD_Msk

+#define DBGMCU_CR_DBG_STOPD1              DBGMCU_CR_DBG_STOPCD

+#define DBGMCU_CR_DBG_STANDBYD1_Pos       DBGMCU_CR_DBG_STANDBYCD_Pos

+#define DBGMCU_CR_DBG_STANDBYD1_Msk       DBGMCU_CR_DBG_STANDBYCD_Msk

+#define DBGMCU_CR_DBG_STANDBYD1           DBGMCU_CR_DBG_STANDBYCD

+#define DBGMCU_CR_DBG_STOPSRD_Pos          (7U)

+#define DBGMCU_CR_DBG_STOPSRD_Msk          (0x1UL << DBGMCU_CR_DBG_STOPSRD_Pos)  /*!< 0x00000080 */

+#define DBGMCU_CR_DBG_STOPSRD              DBGMCU_CR_DBG_STOPSRD_Msk

+#define DBGMCU_CR_DBG_STANDBYSRD_Pos       (8U)

+#define DBGMCU_CR_DBG_STANDBYSRD_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYSRD_Pos) /*!< 0x00000100 */

+#define DBGMCU_CR_DBG_STANDBYSRD           DBGMCU_CR_DBG_STANDBYSRD_Msk

+

+/* Legacy defines */

+#define DBGMCU_CR_DBG_STOPD3_Pos          DBGMCU_CR_DBG_STOPSRD_Pos

+#define DBGMCU_CR_DBG_STOPD3_Msk          DBGMCU_CR_DBG_STOPSRD_Msk

+#define DBGMCU_CR_DBG_STOPD3              DBGMCU_CR_DBG_STOPSRD

+#define DBGMCU_CR_DBG_STANDBYD3_Pos       DBGMCU_CR_DBG_STANDBYSRD_Pos

+#define DBGMCU_CR_DBG_STANDBYD3_Msk       DBGMCU_CR_DBG_STANDBYSRD_Msk

+#define DBGMCU_CR_DBG_STANDBYD3           DBGMCU_CR_DBG_STANDBYSRD

+

+#define DBGMCU_CR_DBG_TRACECKEN_Pos       (20U)

+#define DBGMCU_CR_DBG_TRACECKEN_Msk       (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */

+#define DBGMCU_CR_DBG_TRACECKEN           DBGMCU_CR_DBG_TRACECKEN_Msk

+#define DBGMCU_CR_DBG_CKCDEN_Pos          (21U)

+#define DBGMCU_CR_DBG_CKCDEN_Msk          (0x1UL << DBGMCU_CR_DBG_CKCDEN_Pos)  /*!< 0x00200000 */

+#define DBGMCU_CR_DBG_CKCDEN              DBGMCU_CR_DBG_CKCDEN_Msk

+#define DBGMCU_CR_DBG_CKSRDEN_Pos          (22U)

+#define DBGMCU_CR_DBG_CKSRDEN_Msk          (0x1UL << DBGMCU_CR_DBG_CKSRDEN_Pos)  /*!< 0x00400000 */

+#define DBGMCU_CR_DBG_CKSRDEN              DBGMCU_CR_DBG_CKSRDEN_Msk

+

+/* Legacy defines */

+#define DBGMCU_CR_DBG_CKD1EN_Pos          DBGMCU_CR_DBG_CKCDEN_Pos

+#define DBGMCU_CR_DBG_CKD1EN_Msk          DBGMCU_CR_DBG_CKCDEN_Msk

+#define DBGMCU_CR_DBG_CKD1EN              DBGMCU_CR_DBG_CKCDEN

+#define DBGMCU_CR_DBG_CKD3EN_Pos          DBGMCU_CR_DBG_CKSRDEN_Pos

+#define DBGMCU_CR_DBG_CKD3EN_Msk          DBGMCU_CR_DBG_CKSRDEN_Msk

+#define DBGMCU_CR_DBG_CKD3EN              DBGMCU_CR_DBG_CKSRDEN

+

+#define DBGMCU_CR_DBG_TRGOEN_Pos          (28U)

+#define DBGMCU_CR_DBG_TRGOEN_Msk          (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)  /*!< 0x10000000 */

+#define DBGMCU_CR_DBG_TRGOEN              DBGMCU_CR_DBG_TRGOEN_Msk

+

+/********************  Bit definition for APB3FZ1 register  ************/

+#define DBGMCU_APB3FZ1_DBG_WWDG1_Pos      (6U)

+#define DBGMCU_APB3FZ1_DBG_WWDG1_Msk      (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB3FZ1_DBG_WWDG1          DBGMCU_APB3FZ1_DBG_WWDG1_Msk

+/********************  Bit definition for APB1LFZ1 register  ************/

+#define DBGMCU_APB1LFZ1_DBG_TIM2_Pos      (0U)

+#define DBGMCU_APB1LFZ1_DBG_TIM2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB1LFZ1_DBG_TIM2          DBGMCU_APB1LFZ1_DBG_TIM2_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM3_Pos      (1U)

+#define DBGMCU_APB1LFZ1_DBG_TIM3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB1LFZ1_DBG_TIM3          DBGMCU_APB1LFZ1_DBG_TIM3_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM4_Pos      (2U)

+#define DBGMCU_APB1LFZ1_DBG_TIM4_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */

+#define DBGMCU_APB1LFZ1_DBG_TIM4          DBGMCU_APB1LFZ1_DBG_TIM4_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM5_Pos      (3U)

+#define DBGMCU_APB1LFZ1_DBG_TIM5_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */

+#define DBGMCU_APB1LFZ1_DBG_TIM5          DBGMCU_APB1LFZ1_DBG_TIM5_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM6_Pos      (4U)

+#define DBGMCU_APB1LFZ1_DBG_TIM6_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */

+#define DBGMCU_APB1LFZ1_DBG_TIM6          DBGMCU_APB1LFZ1_DBG_TIM6_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM7_Pos      (5U)

+#define DBGMCU_APB1LFZ1_DBG_TIM7_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */

+#define DBGMCU_APB1LFZ1_DBG_TIM7          DBGMCU_APB1LFZ1_DBG_TIM7_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM12_Pos     (6U)

+#define DBGMCU_APB1LFZ1_DBG_TIM12_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB1LFZ1_DBG_TIM12         DBGMCU_APB1LFZ1_DBG_TIM12_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM13_Pos     (7U)

+#define DBGMCU_APB1LFZ1_DBG_TIM13_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB1LFZ1_DBG_TIM13         DBGMCU_APB1LFZ1_DBG_TIM13_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM14_Pos     (8U)

+#define DBGMCU_APB1LFZ1_DBG_TIM14_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */

+#define DBGMCU_APB1LFZ1_DBG_TIM14         DBGMCU_APB1LFZ1_DBG_TIM14_Msk

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos    (9U)

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1        DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C1_Pos      (21U)

+#define DBGMCU_APB1LFZ1_DBG_I2C1_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C1          DBGMCU_APB1LFZ1_DBG_I2C1_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C2_Pos      (22U)

+#define DBGMCU_APB1LFZ1_DBG_I2C2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C2          DBGMCU_APB1LFZ1_DBG_I2C2_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C3_Pos      (23U)

+#define DBGMCU_APB1LFZ1_DBG_I2C3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C3          DBGMCU_APB1LFZ1_DBG_I2C3_Msk

+

+/********************  Bit definition for APB2FZ1 register  ************/

+#define DBGMCU_APB2FZ1_DBG_TIM1_Pos       (0U)

+#define DBGMCU_APB2FZ1_DBG_TIM1_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB2FZ1_DBG_TIM1           DBGMCU_APB2FZ1_DBG_TIM1_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM8_Pos       (1U)

+#define DBGMCU_APB2FZ1_DBG_TIM8_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB2FZ1_DBG_TIM8           DBGMCU_APB2FZ1_DBG_TIM8_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM15_Pos      (16U)

+#define DBGMCU_APB2FZ1_DBG_TIM15_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB2FZ1_DBG_TIM15          DBGMCU_APB2FZ1_DBG_TIM15_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM16_Pos      (17U)

+#define DBGMCU_APB2FZ1_DBG_TIM16_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */

+#define DBGMCU_APB2FZ1_DBG_TIM16          DBGMCU_APB2FZ1_DBG_TIM16_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM17_Pos      (18U)

+#define DBGMCU_APB2FZ1_DBG_TIM17_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB2FZ1_DBG_TIM17          DBGMCU_APB2FZ1_DBG_TIM17_Msk

+/********************  Bit definition for APB4FZ1 register  ************/

+#define DBGMCU_APB4FZ1_DBG_I2C4_Pos       (7U)

+#define DBGMCU_APB4FZ1_DBG_I2C4_Msk       (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB4FZ1_DBG_I2C4           DBGMCU_APB4FZ1_DBG_I2C4_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos     (9U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM2         DBGMCU_APB4FZ1_DBG_LPTIM2_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos     (10U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM3         DBGMCU_APB4FZ1_DBG_LPTIM3_Msk

+#define DBGMCU_APB4FZ1_DBG_RTC_Pos        (16U)

+#define DBGMCU_APB4FZ1_DBG_RTC_Msk        (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB4FZ1_DBG_RTC            DBGMCU_APB4FZ1_DBG_RTC_Msk

+#define DBGMCU_APB4FZ1_DBG_IWDG1_Pos      (18U)

+#define DBGMCU_APB4FZ1_DBG_IWDG1_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB4FZ1_DBG_IWDG1          DBGMCU_APB4FZ1_DBG_IWDG1_Msk

+/******************************************************************************/

+/*                                                                            */

+/*                             RAM ECC monitoring                             */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for RAMECC_IER register  ******************/

+#define RAMECC_IER_GECCDEBWIE_Pos         (3U)

+#define RAMECC_IER_GECCDEBWIE_Msk         (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)  /*!< 0x00000008 */

+#define RAMECC_IER_GECCDEBWIE             RAMECC_IER_GECCDEBWIE_Msk             /*!< Global ECC double error on byte write (BW) interrupt enable */

+#define RAMECC_IER_GECCDEIE_Pos           (2U)

+#define RAMECC_IER_GECCDEIE_Msk           (0x1UL << RAMECC_IER_GECCDEIE_Pos)    /*!< 0x00000004 */

+#define RAMECC_IER_GECCDEIE               RAMECC_IER_GECCDEIE_Msk               /*!< Global ECC double error interrupt enable */

+#define RAMECC_IER_GECCSEIE_Pos           (1U)

+#define RAMECC_IER_GECCSEIE_Msk           (0x1UL << RAMECC_IER_GECCSEIE_Pos)    /*!< 0x00000002 */

+#define RAMECC_IER_GECCSEIE               RAMECC_IER_GECCSEIE_Msk               /*!< Global ECC single error interrupt enable */

+#define RAMECC_IER_GIE_Pos                (0U)

+#define RAMECC_IER_GIE_Msk                (0x1UL << RAMECC_IER_GIE_Pos)         /*!< 0x00000001 */

+#define RAMECC_IER_GIE                    RAMECC_IER_GIE_Msk                    /*!< Global interrupt enable */

+

+/*******************  Bit definition for RAMECC_CR register  ******************/

+#define RAMECC_CR_ECCELEN_Pos             (5U)

+#define RAMECC_CR_ECCELEN_Msk             (0x1UL << RAMECC_CR_ECCELEN_Pos)      /*!< 0x00000020 */

+#define RAMECC_CR_ECCELEN                 RAMECC_CR_ECCELEN_Msk                 /*!< ECC error latching enable */

+#define RAMECC_CR_ECCDEBWIE_Pos           (4U)

+#define RAMECC_CR_ECCDEBWIE_Msk           (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)    /*!< 0x00000010 */

+#define RAMECC_CR_ECCDEBWIE               RAMECC_CR_ECCDEBWIE_Msk               /*!< ECC double error on byte write (BW) interrupt enable */

+#define RAMECC_CR_ECCDEIE_Pos             (3U)

+#define RAMECC_CR_ECCDEIE_Msk             (0x1UL << RAMECC_CR_ECCDEIE_Pos)      /*!< 0x00000008 */

+#define RAMECC_CR_ECCDEIE                 RAMECC_CR_ECCDEIE_Msk                 /*!< ECC double error interrupt enable */

+#define RAMECC_CR_ECCSEIE_Pos             (2U)

+#define RAMECC_CR_ECCSEIE_Msk             (0x1UL << RAMECC_CR_ECCSEIE_Pos)      /*!< 0x00000004 */

+#define RAMECC_CR_ECCSEIE                 RAMECC_CR_ECCSEIE_Msk                 /*!< ECC single error interrupt enable */

+

+/*******************  Bit definition for RAMECC_SR register  ******************/

+#define RAMECC_SR_DEBWDF_Pos             (2U)

+#define RAMECC_SR_DEBWDF_Msk             (0x1UL << RAMECC_SR_DEBWDF_Pos)        /*!< 0x00000004 */

+#define RAMECC_SR_DEBWDF                 RAMECC_SR_DEBWDF_Msk                   /*!< ECC double error on byte write (BW) detected flag */

+#define RAMECC_SR_DEDF_Pos               (1U)

+#define RAMECC_SR_DEDF_Msk               (0x1UL << RAMECC_SR_DEDF_Pos)          /*!< 0x00000002 */

+#define RAMECC_SR_DEDF                   RAMECC_SR_DEDF_Msk                     /*!< ECC double error detected flag */

+#define RAMECC_SR_SEDCF_Pos              (0U)

+#define RAMECC_SR_SEDCF_Msk              (0x1UL << RAMECC_SR_SEDCF_Pos)         /*!< 0x00000001 */

+#define RAMECC_SR_SEDCF                  RAMECC_SR_SEDCF_Msk                    /*!< ECC single error detected and corrected flag */

+

+/******************  Bit definition for RAMECC_FAR register  ******************/

+#define RAMECC_FAR_FADD_Pos              (0U)

+#define RAMECC_FAR_FADD_Msk              (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)  /*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FADD                  RAMECC_FAR_FADD_Msk                    /*!< ECC error failing address */

+

+/******************  Bit definition for RAMECC_FDRL register  *****************/

+#define RAMECC_FAR_FDATAL_Pos            (0U)

+#define RAMECC_FAR_FDATAL_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FDATAL                RAMECC_FAR_FDATAL_Msk                  /*!< ECC error failing address */

+

+/******************  Bit definition for RAMECC_FDRH register  *****************/

+#define RAMECC_FAR_FDATAH_Pos            (0U)

+#define RAMECC_FAR_FDATAH_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FDATAH                RAMECC_FAR_FDATAH_Msk                  /* Failing data high (64-bit memory) */

+

+/*****************  Bit definition for RAMECC_FECR register  ******************/

+#define RAMECC_FECR_FEC_Pos              (0U)

+#define RAMECC_FECR_FEC_Msk              (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)  /*!< 0xFFFFFFFF */

+#define RAMECC_FECR_FEC                  RAMECC_FECR_FEC_Msk                    /*!< Failing error code */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                MDIOS                                        */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for MDIOS_CR register  *******************/

+#define MDIOS_CR_EN_Pos                (0U)

+#define MDIOS_CR_EN_Msk                (0x1UL << MDIOS_CR_EN_Pos)              /*!< 0x00000001 */

+#define MDIOS_CR_EN                    MDIOS_CR_EN_Msk                         /*!<  MDIOS slave peripheral enable */

+#define MDIOS_CR_WRIE_Pos              (1U)

+#define MDIOS_CR_WRIE_Msk              (0x1UL << MDIOS_CR_WRIE_Pos)            /*!< 0x00000002 */

+#define MDIOS_CR_WRIE                  MDIOS_CR_WRIE_Msk                       /*!<  MDIOS slave register write interrupt enable. */

+#define MDIOS_CR_RDIE_Pos              (2U)

+#define MDIOS_CR_RDIE_Msk              (0x1UL << MDIOS_CR_RDIE_Pos)            /*!< 0x00000004 */

+#define MDIOS_CR_RDIE                  MDIOS_CR_RDIE_Msk                       /*!<  MDIOS slave register read interrupt enable. */

+#define MDIOS_CR_EIE_Pos               (3U)

+#define MDIOS_CR_EIE_Msk               (0x1UL << MDIOS_CR_EIE_Pos)             /*!< 0x00000008 */

+#define MDIOS_CR_EIE                   MDIOS_CR_EIE_Msk                        /*!<  MDIOS slave register error interrupt enable. */

+#define MDIOS_CR_DPC_Pos               (7U)

+#define MDIOS_CR_DPC_Msk               (0x1UL << MDIOS_CR_DPC_Pos)             /*!< 0x00000080 */

+#define MDIOS_CR_DPC                   MDIOS_CR_DPC_Msk                        /*!<  MDIOS slave disable preamble check. */

+#define MDIOS_CR_PORT_ADDRESS_Pos      (8U)

+#define MDIOS_CR_PORT_ADDRESS_Msk      (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)   /*!< 0x00001F00 */

+#define MDIOS_CR_PORT_ADDRESS          MDIOS_CR_PORT_ADDRESS_Msk               /*!<  MDIOS slave port address mask. */

+#define MDIOS_CR_PORT_ADDRESS_0        (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000100 */

+#define MDIOS_CR_PORT_ADDRESS_1        (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000200 */

+#define MDIOS_CR_PORT_ADDRESS_2        (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000400 */

+#define MDIOS_CR_PORT_ADDRESS_3        (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000800 */

+#define MDIOS_CR_PORT_ADDRESS_4        (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001000 */

+

+/********************  Bit definition for MDIOS_SR register  *******************/

+#define MDIOS_SR_PERF_Pos              (0U)

+#define MDIOS_SR_PERF_Msk              (0x1UL << MDIOS_SR_PERF_Pos)            /*!< 0x00000001 */

+#define MDIOS_SR_PERF                  MDIOS_SR_PERF_Msk                       /*!<  MDIOS slave turnaround error flag*/

+#define MDIOS_SR_SERF_Pos              (1U)

+#define MDIOS_SR_SERF_Msk              (0x1UL << MDIOS_SR_SERF_Pos)            /*!< 0x00000002 */

+#define MDIOS_SR_SERF                  MDIOS_SR_SERF_Msk                       /*!<  MDIOS slave start error flag */

+#define MDIOS_SR_TERF_Pos              (2U)

+#define MDIOS_SR_TERF_Msk              (0x1UL << MDIOS_SR_TERF_Pos)            /*!< 0x00000004 */

+#define MDIOS_SR_TERF                  MDIOS_SR_TERF_Msk                       /*!<  MDIOS slave preamble error flag */

+

+/********************  Bit definition for MDIOS_CLRFR register  *******************/

+#define MDIOS_SR_CPERF_Pos             (0U)

+#define MDIOS_SR_CPERF_Msk             (0x1UL << MDIOS_SR_CPERF_Pos)           /*!< 0x00000001 */

+#define MDIOS_SR_CPERF                 MDIOS_SR_CPERF_Msk                      /*!<  MDIOS slave Clear the turnaround error flag */

+#define MDIOS_SR_CSERF_Pos             (1U)

+#define MDIOS_SR_CSERF_Msk             (0x1UL << MDIOS_SR_CSERF_Pos)           /*!< 0x00000002 */

+#define MDIOS_SR_CSERF                 MDIOS_SR_CSERF_Msk                      /*!<  MDIOS slave Clear the start error flag */

+#define MDIOS_SR_CTERF_Pos             (2U)

+#define MDIOS_SR_CTERF_Msk             (0x1UL << MDIOS_SR_CTERF_Pos)           /*!< 0x00000004 */

+#define MDIOS_SR_CTERF                 MDIOS_SR_CTERF_Msk                      /*!<  MDIOS slave Clear the preamble error flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                       USB_OTG                              */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/

+#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)

+#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */

+#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */

+#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)

+#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */

+#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */

+#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)

+#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */

+#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */

+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)

+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */

+#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */

+#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)

+#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */

+#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */

+#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)

+#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */

+#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */

+#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)

+#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */

+#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */

+#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)

+#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */

+#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */

+#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)

+#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */

+#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */

+#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)

+#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */

+#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */

+#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)

+#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */

+#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */

+#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)

+#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */

+#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */

+#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)

+#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */

+#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */

+#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)

+#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */

+#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */

+#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)

+#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */

+#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */

+#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)

+#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */

+#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */

+#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)

+#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */

+#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */

+#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)

+#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */

+#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */

+

+/********************  Bit definition forUSB_OTG_HCFG register  ********************/

+

+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)

+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */

+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */

+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)

+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */

+

+/********************  Bit definition forUSB_OTG_DCFG register  ********************/

+

+#define USB_OTG_DCFG_DSPD_Pos                    (0U)

+#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */

+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */

+#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */

+#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)

+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */

+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */

+

+#define USB_OTG_DCFG_DAD_Pos                     (4U)

+#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */

+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */

+#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */

+#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */

+#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */

+#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */

+#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */

+#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */

+#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */

+

+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)

+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */

+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */

+#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */

+#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */

+

+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)

+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */

+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */

+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */

+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */

+

+/********************  Bit definition forUSB_OTG_PCGCR register  ********************/

+#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)

+#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */

+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */

+#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)

+#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */

+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */

+#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)

+#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */

+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */

+

+/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/

+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)

+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */

+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */

+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)

+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */

+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */

+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)

+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */

+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */

+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)

+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */

+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */

+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)

+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */

+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */

+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)

+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */

+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */

+

+/********************  Bit definition forUSB_OTG_DCTL register  ********************/

+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)

+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */

+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */

+#define USB_OTG_DCTL_SDIS_Pos                    (1U)

+#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */

+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */

+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)

+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */

+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */

+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)

+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */

+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */

+

+#define USB_OTG_DCTL_TCTL_Pos                    (4U)

+#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */

+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */

+#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */

+#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */

+#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */

+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)

+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */

+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */

+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)

+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */

+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */

+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)

+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */

+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */

+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)

+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */

+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */

+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)

+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */

+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */

+

+/********************  Bit definition forUSB_OTG_HFIR register  ********************/

+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)

+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */

+

+/********************  Bit definition forUSB_OTG_HFNUM register  ********************/

+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)

+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */

+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)

+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */

+

+/********************  Bit definition forUSB_OTG_DSTS register  ********************/

+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)

+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */

+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */

+

+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)

+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */

+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */

+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */

+#define USB_OTG_DSTS_EERR_Pos                    (3U)

+#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */

+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */

+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)

+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */

+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */

+

+/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/

+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)

+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */

+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */

+

+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)

+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */

+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */

+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */

+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */

+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */

+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */

+#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */

+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)

+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */

+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */

+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)

+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */

+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */

+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)

+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */

+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */

+

+/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/

+

+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)

+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */

+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */

+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */

+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */

+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */

+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)

+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */

+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */

+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)

+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */

+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */

+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)

+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */

+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */

+

+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)

+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */

+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */

+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */

+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */

+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */

+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */

+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)

+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */

+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */

+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)

+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */

+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */

+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)

+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */

+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */

+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)

+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */

+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */

+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)

+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */

+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */

+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)

+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */

+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */

+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)

+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */

+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */

+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)

+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */

+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */

+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)

+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */

+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */

+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)

+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */

+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */

+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)

+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */

+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */

+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)

+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */

+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */

+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)

+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */

+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */

+

+/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/

+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)

+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */

+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */

+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)

+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */

+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */

+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)

+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */

+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */

+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)

+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */

+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */

+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)

+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */

+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */

+

+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)

+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */

+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */

+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */

+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */

+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */

+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */

+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */

+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)

+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */

+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */

+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)

+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */

+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */

+

+/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/

+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)

+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */

+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)

+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */

+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)

+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */

+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)

+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */

+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)

+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */

+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)

+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */

+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)

+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */

+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)

+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */

+

+/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/

+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)

+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */

+

+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)

+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */

+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */

+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */

+

+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)

+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */

+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */

+

+/********************  Bit definition forUSB_OTG_HAINT register  ********************/

+#define USB_OTG_HAINT_HAINT_Pos                  (0U)

+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */

+

+/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/

+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)

+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */

+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)

+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */

+#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)

+#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */

+#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask               */

+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)

+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */

+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)

+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */

+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)

+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */

+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)

+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */

+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)

+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */

+#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)

+#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */

+#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)

+#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask               */

+#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)

+#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask               */

+#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)

+#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                */

+

+/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/

+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)

+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */

+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */

+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)

+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */

+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */

+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)

+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */

+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */

+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)

+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */

+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */

+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)

+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */

+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */

+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)

+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */

+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */

+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)

+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */

+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */

+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)

+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */

+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */

+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)

+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */

+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */

+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)

+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */

+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */

+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)

+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */

+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */

+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)

+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */

+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */

+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)

+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */

+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */

+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)

+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */

+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */

+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)

+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */

+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */

+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)

+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */

+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */

+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)

+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */

+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */

+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)

+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */

+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */

+#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)

+#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */

+#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */

+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)

+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */

+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */

+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)

+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */

+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */

+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)

+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */

+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */

+#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)

+#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */

+#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */

+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)

+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */

+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */

+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)

+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */

+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */

+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)

+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */

+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */

+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)

+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */

+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */

+

+/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/

+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)

+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */

+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */

+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)

+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */

+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */

+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)

+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */

+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */

+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)

+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */

+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */

+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)

+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */

+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */

+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)

+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */

+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */

+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)

+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */

+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */

+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)

+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */

+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */

+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)

+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */

+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */

+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)

+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */

+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */

+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)

+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */

+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */

+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)

+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */

+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */

+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)

+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */

+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */

+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)

+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */

+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */

+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)

+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */

+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */

+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)

+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */

+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */

+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)

+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */

+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */

+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)

+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */

+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */

+#define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)

+#define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */

+#define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */

+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)

+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */

+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */

+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)

+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */

+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */

+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)

+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */

+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */

+#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)

+#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */

+#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */

+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)

+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */

+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */

+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)

+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */

+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */

+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)

+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */

+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */

+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)

+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */

+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */

+

+/********************  Bit definition forUSB_OTG_DAINT register  ********************/

+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)

+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */

+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)

+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */

+

+/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/

+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)

+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */

+

+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/

+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)

+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */

+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */

+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)

+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */

+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */

+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)

+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */

+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */

+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)

+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */

+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */

+

+/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/

+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)

+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */

+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)

+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */

+

+/********************  Bit definition for OTG register  ********************/

+

+#define USB_OTG_CHNUM_Pos                        (0U)

+#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)  /*!< 0x0000000F */

+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */

+#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */

+#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */

+#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */

+#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */

+#define USB_OTG_BCNT_Pos                         (4U)

+#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */

+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */

+

+#define USB_OTG_DPID_Pos                         (15U)

+#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)   /*!< 0x00018000 */

+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */

+#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */

+#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */

+

+#define USB_OTG_PKTSTS_Pos                       (17U)

+#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */

+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */

+#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */

+#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */

+#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */

+#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */

+

+#define USB_OTG_EPNUM_Pos                        (0U)

+#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)  /*!< 0x0000000F */

+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */

+#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */

+#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */

+#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */

+#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */

+

+#define USB_OTG_FRMNUM_Pos                       (21U)

+#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */

+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */

+#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */

+#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */

+#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */

+#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */

+

+/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/

+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)

+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/

+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)

+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */

+

+/********************  Bit definition for OTG register  ********************/

+#define USB_OTG_NPTXFSA_Pos                      (0U)

+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */

+#define USB_OTG_NPTXFD_Pos                       (16U)

+#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */

+#define USB_OTG_TX0FSA_Pos                       (0U)

+#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */

+#define USB_OTG_TX0FD_Pos                        (16U)

+#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */

+

+/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/

+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)

+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */

+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */

+

+/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/

+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)

+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */

+

+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)

+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */

+

+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)

+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/

+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)

+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */

+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */

+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)

+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */

+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */

+

+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)

+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */

+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */

+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */

+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)

+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */

+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */

+

+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)

+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */

+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */

+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)

+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */

+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */

+

+/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */

+

+/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/

+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)

+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */

+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */

+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)

+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */

+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */

+

+/********************  Bit definition forUSB_OTG_GCCFG register  ********************/

+#define USB_OTG_GCCFG_DCDET_Pos                  (0U)

+#define USB_OTG_GCCFG_DCDET_Msk                  (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */

+#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */

+#define USB_OTG_GCCFG_PDET_Pos                   (1U)

+#define USB_OTG_GCCFG_PDET_Msk                   (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */

+#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */

+#define USB_OTG_GCCFG_SDET_Pos                   (2U)

+#define USB_OTG_GCCFG_SDET_Msk                   (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */

+#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */

+#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)

+#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */

+#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */

+#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)

+#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */

+#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */

+#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)

+#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */

+#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */

+#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)

+#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */

+#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/

+#define USB_OTG_GCCFG_PDEN_Pos                   (19U)

+#define USB_OTG_GCCFG_PDEN_Msk                   (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */

+#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/

+#define USB_OTG_GCCFG_SDEN_Pos                   (20U)

+#define USB_OTG_GCCFG_SDEN_Msk                   (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */

+#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */

+#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)

+#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */

+#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */

+

+/********************  Bit definition forUSB_OTG_GPWRDN) register  ********************/

+#define USB_OTG_GPWRDN_ADPMEN_Pos                (0U)

+#define USB_OTG_GPWRDN_ADPMEN_Msk                (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */

+#define USB_OTG_GPWRDN_ADPMEN                    USB_OTG_GPWRDN_ADPMEN_Msk     /*!< ADP module enable */

+#define USB_OTG_GPWRDN_ADPIF_Pos                 (23U)

+#define USB_OTG_GPWRDN_ADPIF_Msk                 (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */

+#define USB_OTG_GPWRDN_ADPIF                     USB_OTG_GPWRDN_ADPIF_Msk      /*!< ADP Interrupt flag */

+

+/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/

+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)

+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */

+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)

+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */

+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */

+

+/********************  Bit definition forUSB_OTG_CID register  ********************/

+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)

+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */

+

+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/

+#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)

+#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */

+#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */

+#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)

+#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */

+#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */

+#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)

+#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */

+#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */

+#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)

+#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */

+#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */

+#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)

+#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */

+#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */

+#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)

+#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */

+#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */

+#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)

+#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */

+#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */

+#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)

+#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */

+#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */

+#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)

+#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */

+#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */

+#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)

+#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */

+#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */

+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)

+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */

+#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */

+#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)

+#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */

+#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */

+#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)

+#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */

+#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */

+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)

+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */

+#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */

+#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)

+#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */

+#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */

+

+/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/

+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)

+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */

+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)

+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */

+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)

+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */

+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)

+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */

+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)

+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */

+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)

+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */

+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)

+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */

+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)

+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */

+

+/********************  Bit definition forUSB_OTG_HPRT register  ********************/

+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)

+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */

+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */

+#define USB_OTG_HPRT_PCDET_Pos                   (1U)

+#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */

+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */

+#define USB_OTG_HPRT_PENA_Pos                    (2U)

+#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */

+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */

+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)

+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */

+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */

+#define USB_OTG_HPRT_POCA_Pos                    (4U)

+#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */

+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */

+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)

+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */

+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */

+#define USB_OTG_HPRT_PRES_Pos                    (6U)

+#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */

+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume   */

+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)

+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */

+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend  */

+#define USB_OTG_HPRT_PRST_Pos                    (8U)

+#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */

+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset    */

+

+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)

+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */

+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */

+#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */

+#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */

+#define USB_OTG_HPRT_PPWR_Pos                    (12U)

+#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */

+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */

+

+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)

+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */

+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */

+#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */

+#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */

+#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */

+#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */

+

+#define USB_OTG_HPRT_PSPD_Pos                    (17U)

+#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */

+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */

+#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */

+#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */

+

+/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/

+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)

+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)

+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)

+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */

+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)

+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */

+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)

+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */

+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)

+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */

+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)

+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)

+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)

+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)

+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */

+

+/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/

+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)

+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */

+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)

+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/

+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)

+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */

+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)

+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */

+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */

+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)

+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */

+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */

+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)

+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */

+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */

+

+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)

+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */

+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */

+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)

+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */

+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */

+

+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)

+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */

+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */

+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */

+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */

+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */

+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */

+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)

+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */

+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */

+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)

+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */

+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */

+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)

+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */

+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)

+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */

+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)

+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */

+

+/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/

+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)

+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */

+

+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)

+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */

+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */

+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */

+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */

+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */

+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */

+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)

+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */

+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */

+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)

+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */

+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */

+

+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)

+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */

+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */

+

+#define USB_OTG_HCCHAR_MC_Pos                    (20U)

+#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */

+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */

+#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */

+#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */

+

+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)

+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */

+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */

+#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */

+#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */

+#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */

+#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */

+#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */

+#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */

+#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */

+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)

+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */

+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)

+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */

+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)

+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */

+

+/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/

+

+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)

+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */

+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */

+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */

+

+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)

+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */

+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */

+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */

+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */

+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */

+

+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)

+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */

+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */

+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */

+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */

+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)

+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */

+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */

+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)

+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */

+

+/********************  Bit definition forUSB_OTG_HCINT register  ********************/

+#define USB_OTG_HCINT_XFRC_Pos                   (0U)

+#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */

+#define USB_OTG_HCINT_CHH_Pos                    (1U)

+#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */

+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)

+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */

+#define USB_OTG_HCINT_STALL_Pos                  (3U)

+#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */

+#define USB_OTG_HCINT_NAK_Pos                    (4U)

+#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */

+#define USB_OTG_HCINT_ACK_Pos                    (5U)

+#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */

+#define USB_OTG_HCINT_NYET_Pos                   (6U)

+#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */

+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */

+#define USB_OTG_HCINT_TXERR_Pos                  (7U)

+#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */

+#define USB_OTG_HCINT_BBERR_Pos                  (8U)

+#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */

+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)

+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */

+#define USB_OTG_HCINT_DTERR_Pos                  (10U)

+#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */

+

+/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/

+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)

+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */

+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)

+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */

+#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)

+#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */

+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)

+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */

+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)

+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */

+#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)

+#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */

+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)

+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */

+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)

+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */

+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */

+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)

+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */

+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)

+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */

+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)

+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */

+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */

+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)

+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */

+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */

+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)

+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */

+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */

+

+/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/

+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)

+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */

+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)

+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */

+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)

+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */

+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)

+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */

+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)

+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */

+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)

+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */

+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)

+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */

+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */

+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)

+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */

+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)

+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */

+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)

+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */

+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)

+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */

+

+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/

+

+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)

+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */

+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)

+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */

+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)

+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */

+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */

+/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/

+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)

+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */

+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)

+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */

+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)

+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */

+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)

+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */

+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */

+#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */

+#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/

+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)

+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */

+

+/********************  Bit definition forUSB_OTG_HCDMA register  ********************/

+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)

+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */

+

+/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/

+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)

+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */

+

+/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/

+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)

+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */

+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)

+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/

+

+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)

+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */

+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)

+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */

+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */

+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)

+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */

+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */

+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)

+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */

+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)

+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */

+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */

+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)

+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */

+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */

+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)

+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */

+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */

+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)

+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */

+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */

+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)

+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */

+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */

+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)

+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */

+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)

+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */

+

+/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/

+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)

+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */

+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)

+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */

+#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)

+#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */

+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)

+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */

+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)

+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */

+#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)

+#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< OUT Status Phase Received interrupt */

+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)

+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */

+#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)

+#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */

+#define USB_OTG_DOEPINT_BNA_Pos                  (9U)

+#define USB_OTG_DOEPINT_BNA_Msk                  (0x1UL << USB_OTG_DOEPINT_BNA_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPINT_BNA                      USB_OTG_DOEPINT_BNA_Msk   /*!< Buffer not available interrupt */

+#define USB_OTG_DOEPINT_BERR_Pos                 (12U)

+#define USB_OTG_DOEPINT_BERR_Msk                 (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPINT_BERR                      USB_OTG_DOEPINT_BERR_Msk   /*!< Babble error interrupt */

+#define USB_OTG_DOEPINT_NAK_Pos                  (13U)

+#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */

+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)

+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */

+#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)

+#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */

+#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */

+

+/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/

+

+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)

+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */

+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)

+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */

+

+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)

+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */

+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */

+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */

+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition for PCGCCTL register  ********************/

+#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)

+#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */

+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */

+#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)

+#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */

+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */

+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)

+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */

+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/** @addtogroup Exported_macros

+  * @{

+  */

+

+/******************************* ADC Instances ********************************/

+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \

+                                       ((INSTANCE) == ADC2))

+

+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)

+

+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)

+

+/******************************** COMP Instances ******************************/

+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \

+                                       ((INSTANCE) == COMP2))

+

+#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)

+/******************** COMP Instances with window mode capability **************/

+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)

+

+/******************************** DTS Instances ******************************/

+#define IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS)

+

+/******************************* CRC Instances ********************************/

+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

+

+/******************************* DAC Instances ********************************/

+#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1)|| \

+                                       ((INSTANCE) == DAC2))

+/******************************* DCMI Instances *******************************/

+#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)

+

+/******************************* DELAYBLOCK Instances *******************************/

+#define IS_DLYB_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DLYB_SDMMC1) || \

+                                         ((INSTANCE) == DLYB_SDMMC2) || \

+                                         ((INSTANCE) == DLYB_OCTOSPI1) || \

+                                         ((INSTANCE) == DLYB_OCTOSPI2) )

+/****************************** DFSDM Instances *******************************/

+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \

+                                         ((INSTANCE) == DFSDM1_Filter1) || \

+                                         ((INSTANCE) == DFSDM1_Filter2) || \

+                                         ((INSTANCE) == DFSDM1_Filter3) || \

+                                         ((INSTANCE) == DFSDM1_Filter4) || \

+                                         ((INSTANCE) == DFSDM1_Filter5) || \

+                                         ((INSTANCE) == DFSDM1_Filter6) || \

+                                         ((INSTANCE) == DFSDM1_Filter7) || \

+                                         ((INSTANCE) == DFSDM2_Filter0))

+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \

+                                                 ((INSTANCE) == DFSDM1_Channel1) || \

+                                                 ((INSTANCE) == DFSDM1_Channel2) || \

+                                                 ((INSTANCE) == DFSDM1_Channel3) || \

+                                                 ((INSTANCE) == DFSDM1_Channel4) || \

+                                                 ((INSTANCE) == DFSDM1_Channel5) || \

+                                                 ((INSTANCE) == DFSDM1_Channel6) || \

+                                                 ((INSTANCE) == DFSDM1_Channel7) || \

+                                                 ((INSTANCE) == DFSDM2_Channel0) || \

+                                                 ((INSTANCE) == DFSDM2_Channel1))

+/****************************** RAMECC Instances ******************************/

+#define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC_Monitor1)   || \

+                                                  ((INSTANCE) == RAMECC_Monitor2)   || \

+                                                  ((INSTANCE) == RAMECC_Monitor3))

+

+/******************************** DMA Instances *******************************/

+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \

+                                       ((INSTANCE) == DMA1_Stream1)   || \

+                                       ((INSTANCE) == DMA1_Stream2)   || \

+                                       ((INSTANCE) == DMA1_Stream3)   || \

+                                       ((INSTANCE) == DMA1_Stream4)   || \

+                                       ((INSTANCE) == DMA1_Stream5)   || \

+                                       ((INSTANCE) == DMA1_Stream6)   || \

+                                       ((INSTANCE) == DMA1_Stream7)   || \

+                                       ((INSTANCE) == DMA2_Stream0)   || \

+                                       ((INSTANCE) == DMA2_Stream1)   || \

+                                       ((INSTANCE) == DMA2_Stream2)   || \

+                                       ((INSTANCE) == DMA2_Stream3)   || \

+                                       ((INSTANCE) == DMA2_Stream4)   || \

+                                       ((INSTANCE) == DMA2_Stream5)   || \

+                                       ((INSTANCE) == DMA2_Stream6)   || \

+                                       ((INSTANCE) == DMA2_Stream7)   || \

+                                       ((INSTANCE) == BDMA1_Channel0) || \

+                                       ((INSTANCE) == BDMA1_Channel1) || \

+                                       ((INSTANCE) == BDMA1_Channel2) || \

+                                       ((INSTANCE) == BDMA1_Channel3) || \

+                                       ((INSTANCE) == BDMA1_Channel4) || \

+                                       ((INSTANCE) == BDMA1_Channel5) || \

+                                       ((INSTANCE) == BDMA1_Channel6) || \

+                                       ((INSTANCE) == BDMA1_Channel7) || \

+                                       ((INSTANCE) == BDMA2_Channel0) || \

+                                       ((INSTANCE) == BDMA2_Channel1) || \

+                                       ((INSTANCE) == BDMA2_Channel2) || \

+                                       ((INSTANCE) == BDMA2_Channel3) || \

+                                       ((INSTANCE) == BDMA2_Channel4) || \

+                                       ((INSTANCE) == BDMA2_Channel5) || \

+                                       ((INSTANCE) == BDMA2_Channel6) || \

+                                       ((INSTANCE) == BDMA2_Channel7))

+

+/****************************** BDMA CHANNEL Instances ***************************/

+#define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA1_Channel0) || \

+                                            ((INSTANCE) == BDMA1_Channel1) || \

+                                            ((INSTANCE) == BDMA1_Channel2) || \

+                                            ((INSTANCE) == BDMA1_Channel3) || \

+                                            ((INSTANCE) == BDMA1_Channel4) || \

+                                            ((INSTANCE) == BDMA1_Channel5) || \

+                                            ((INSTANCE) == BDMA1_Channel6) || \

+                                            ((INSTANCE) == BDMA1_Channel7) || \

+                                            ((INSTANCE) == BDMA2_Channel0) || \

+                                            ((INSTANCE) == BDMA2_Channel1) || \

+                                            ((INSTANCE) == BDMA2_Channel2) || \

+                                            ((INSTANCE) == BDMA2_Channel3) || \

+                                            ((INSTANCE) == BDMA2_Channel4) || \

+                                            ((INSTANCE) == BDMA2_Channel5) || \

+                                            ((INSTANCE) == BDMA2_Channel6) || \

+                                            ((INSTANCE) == BDMA2_Channel7))

+

+/****************************** DMA DMAMUX ALL Instances ***************************/

+#define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)    || \

+                                               ((INSTANCE) == DMA1_Stream1)    || \

+                                               ((INSTANCE) == DMA1_Stream2)    || \

+                                               ((INSTANCE) == DMA1_Stream3)    || \

+                                               ((INSTANCE) == DMA1_Stream4)    || \

+                                               ((INSTANCE) == DMA1_Stream5)    || \

+                                               ((INSTANCE) == DMA1_Stream6)    || \

+                                               ((INSTANCE) == DMA1_Stream7)    || \

+                                               ((INSTANCE) == DMA2_Stream0)    || \

+                                               ((INSTANCE) == DMA2_Stream1)    || \

+                                               ((INSTANCE) == DMA2_Stream2)    || \

+                                               ((INSTANCE) == DMA2_Stream3)    || \

+                                               ((INSTANCE) == DMA2_Stream4)    || \

+                                               ((INSTANCE) == DMA2_Stream5)    || \

+                                               ((INSTANCE) == DMA2_Stream6)    || \

+                                               ((INSTANCE) == DMA2_Stream7)    || \

+                                               ((INSTANCE) == BDMA2_Channel0)  || \

+                                               ((INSTANCE) == BDMA2_Channel1)  || \

+                                               ((INSTANCE) == BDMA2_Channel2)  || \

+                                               ((INSTANCE) == BDMA2_Channel3)  || \

+                                               ((INSTANCE) == BDMA2_Channel4)  || \

+                                               ((INSTANCE) == BDMA2_Channel5)  || \

+                                               ((INSTANCE) == BDMA2_Channel6)  || \

+                                               ((INSTANCE) == BDMA2_Channel7))

+

+/****************************** BDMA DMAMUX Instances ***************************/

+#define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == BDMA2_Channel0) || \

+                                                    ((INSTANCE) == BDMA2_Channel1) || \

+                                                    ((INSTANCE) == BDMA2_Channel2) || \

+                                                    ((INSTANCE) == BDMA2_Channel3) || \

+                                                    ((INSTANCE) == BDMA2_Channel4) || \

+                                                    ((INSTANCE) == BDMA2_Channel5) || \

+                                                    ((INSTANCE) == BDMA2_Channel6) || \

+                                                    ((INSTANCE) == BDMA2_Channel7))

+

+/****************************** DMA STREAM Instances ***************************/

+#define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \

+                                          ((INSTANCE) == DMA1_Stream1)   || \

+                                          ((INSTANCE) == DMA1_Stream2)   || \

+                                          ((INSTANCE) == DMA1_Stream3)   || \

+                                          ((INSTANCE) == DMA1_Stream4)   || \

+                                          ((INSTANCE) == DMA1_Stream5)   || \

+                                          ((INSTANCE) == DMA1_Stream6)   || \

+                                          ((INSTANCE) == DMA1_Stream7)   || \

+                                          ((INSTANCE) == DMA2_Stream0)   || \

+                                          ((INSTANCE) == DMA2_Stream1)   || \

+                                          ((INSTANCE) == DMA2_Stream2)   || \

+                                          ((INSTANCE) == DMA2_Stream3)   || \

+                                          ((INSTANCE) == DMA2_Stream4)   || \

+                                          ((INSTANCE) == DMA2_Stream5)   || \

+                                          ((INSTANCE) == DMA2_Stream6)   || \

+                                          ((INSTANCE) == DMA2_Stream7))

+

+/****************************** DMA DMAMUX Instances ***************************/

+#define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)   || \

+                                                  ((INSTANCE) == DMA1_Stream1)   || \

+                                                  ((INSTANCE) == DMA1_Stream2)   || \

+                                                  ((INSTANCE) == DMA1_Stream3)   || \

+                                                  ((INSTANCE) == DMA1_Stream4)   || \

+                                                  ((INSTANCE) == DMA1_Stream5)   || \

+                                                  ((INSTANCE) == DMA1_Stream6)   || \

+                                                  ((INSTANCE) == DMA1_Stream7)   || \

+                                                  ((INSTANCE) == DMA2_Stream0)   || \

+                                                  ((INSTANCE) == DMA2_Stream1)   || \

+                                                  ((INSTANCE) == DMA2_Stream2)   || \

+                                                  ((INSTANCE) == DMA2_Stream3)   || \

+                                                  ((INSTANCE) == DMA2_Stream4)   || \

+                                                  ((INSTANCE) == DMA2_Stream5)   || \

+                                                  ((INSTANCE) == DMA2_Stream6)   || \

+                                                  ((INSTANCE) == DMA2_Stream7))

+

+/******************************** DMA Request Generator Instances **************/

+#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator1) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator2) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator3) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator4) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator5) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator6) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator7) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator0) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator1) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator2) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator3) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator4) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator5) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator6) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator7))

+

+/******************************* DMA2D Instances *******************************/

+#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)

+

+/******************************* OTFDEC Instances ******************************/

+#define IS_OTFDEC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == OTFDEC1) || \

+                                              ((__INSTANCE__) == OTFDEC2))

+

+/****************************** PSSI Instance *********************************/

+#define IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI)

+

+/******************************** MDMA Request Generator Instances **************/

+#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0)  || \

+                                               ((INSTANCE) == MDMA_Channel1)  || \

+                                               ((INSTANCE) == MDMA_Channel2)  || \

+                                               ((INSTANCE) == MDMA_Channel3)  || \

+                                               ((INSTANCE) == MDMA_Channel4)  || \

+                                               ((INSTANCE) == MDMA_Channel5)  || \

+                                               ((INSTANCE) == MDMA_Channel6)  || \

+                                               ((INSTANCE) == MDMA_Channel7)  || \

+                                               ((INSTANCE) == MDMA_Channel8)  || \

+                                               ((INSTANCE) == MDMA_Channel9)  || \

+                                               ((INSTANCE) == MDMA_Channel10) || \

+                                               ((INSTANCE) == MDMA_Channel11) || \

+                                               ((INSTANCE) == MDMA_Channel12) || \

+                                               ((INSTANCE) == MDMA_Channel13) || \

+                                               ((INSTANCE) == MDMA_Channel14) || \

+                                               ((INSTANCE) == MDMA_Channel15))

+

+

+/******************************* FDCAN Instances ******************************/

+#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \

+                                             ((__INSTANCE__) == FDCAN2))

+

+#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)

+

+/******************************* GFXMMU Instances *******************************/

+#define IS_GFXMMU_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GFXMMU)

+

+/******************************* GPIO Instances *******************************/

+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \

+                                        ((INSTANCE) == GPIOB) || \

+                                        ((INSTANCE) == GPIOC) || \

+                                        ((INSTANCE) == GPIOD) || \

+                                        ((INSTANCE) == GPIOE) || \

+                                        ((INSTANCE) == GPIOF) || \

+                                        ((INSTANCE) == GPIOG) || \

+                                        ((INSTANCE) == GPIOH) || \

+                                        ((INSTANCE) == GPIOI) || \

+                                        ((INSTANCE) == GPIOJ) || \

+                                        ((INSTANCE) == GPIOK))

+

+/******************************* GPIO AF Instances ****************************/

+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)

+

+/**************************** GPIO Lock Instances *****************************/

+/* On H7, all GPIO Bank support the Lock mechanism */

+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)

+

+/******************************** HSEM Instances *******************************/

+#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)

+#define HSEM_CPU1_COREID         (0x00000001U) /* Semaphore Core CM7 ID */

+#define HSEM_CR_COREID_CPU1      (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)

+#define HSEM_CR_COREID_CURRENT   (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)

+

+#define HSEM_SEMID_MIN     (0U)       /* HSEM ID Min*/

+#define HSEM_SEMID_MAX     (15U)      /* HSEM ID Max */

+

+#define HSEM_PROCESSID_MIN (0U)       /* HSEM Process ID Min */

+#define HSEM_PROCESSID_MAX (255U)     /* HSEM Process ID Max */

+

+#define HSEM_CLEAR_KEY_MIN (0U)       /* HSEM clear Key Min value */

+#define HSEM_CLEAR_KEY_MAX (0xFFFFU)  /* HSEM clear Key Max value */

+

+/******************************** I2C Instances *******************************/

+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

+                                       ((INSTANCE) == I2C2) || \

+                                       ((INSTANCE) == I2C3) || \

+                                       ((INSTANCE) == I2C4))

+/************** I2C Instances : wakeup capability from stop modes *************/

+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)

+

+/****************************** SMBUS Instances *******************************/

+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

+                                         ((INSTANCE) == I2C2) || \

+                                         ((INSTANCE) == I2C3) || \

+                                         ((INSTANCE) == I2C4))

+/******************************** I2S Instances *******************************/

+#define IS_I2S_ALL_INSTANCE(INSTANCE)   (((INSTANCE) == SPI1) || \

+                                         ((INSTANCE) == SPI2) || \

+                                         ((INSTANCE) == SPI3) || \

+                                         ((INSTANCE) == SPI6))

+

+/****************************** LTDC Instances ********************************/

+#define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)

+

+/******************************* RNG Instances ********************************/

+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)

+

+/****************************** RTC Instances *********************************/

+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)

+

+/****************************** SDMMC Instances *********************************/

+#define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \

+                                           ((_INSTANCE_) == SDMMC2))

+

+/******************************** SMBUS Instances *****************************/

+#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)

+

+/******************************** SPI Instances *******************************/

+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \

+                                       ((INSTANCE) == SPI2) || \

+                                       ((INSTANCE) == SPI3) || \

+                                       ((INSTANCE) == SPI4) || \

+                                       ((INSTANCE) == SPI5) || \

+                                       ((INSTANCE) == SPI6))

+

+#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \

+                                           ((INSTANCE) == SPI2) || \

+                                           ((INSTANCE) == SPI3))

+

+/******************************** SWPMI Instances *****************************/

+#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)

+

+/****************** LPTIM Instances : All supported instances *****************/

+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \

+                                         ((INSTANCE) == LPTIM2) || \

+                                         ((INSTANCE) == LPTIM3))

+

+/****************** LPTIM Instances : supporting encoder interface **************/

+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \

+                                                           ((INSTANCE) == LPTIM2))

+

+/****************** TIM Instances : All supported instances *******************/

+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM6)   || \

+                                         ((INSTANCE) == TIM7)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM13)  || \

+                                         ((INSTANCE) == TIM14)  || \

+                                         ((INSTANCE) == TIM15)  || \

+                                         ((INSTANCE) == TIM16)  || \

+                                         ((INSTANCE) == TIM17))

+

+/************* TIM Instances : at least 1 capture/compare channel *************/

+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM13)  || \

+                                         ((INSTANCE) == TIM14)  || \

+                                         ((INSTANCE) == TIM15)  || \

+                                         ((INSTANCE) == TIM16)  || \

+                                         ((INSTANCE) == TIM17))

+

+/************ TIM Instances : at least 2 capture/compare channels *************/

+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM15))

+

+/************ TIM Instances : at least 3 capture/compare channels *************/

+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8))

+

+/************ TIM Instances : at least 4 capture/compare channels *************/

+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8))

+

+/************ TIM Instances : at least 5 capture/compare channels *************/

+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM8))

+/************ TIM Instances : at least 6 capture/compare channels *************/

+#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM8))

+

+/******************** TIM Instances : Advanced-control timers *****************/

+#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \

+                                                ((__INSTANCE__) == TIM8))

+

+/******************** TIM Instances : Advanced-control timers *****************/

+

+/******************* TIM Instances : Timer input XOR function *****************/

+#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : DMA requests generation (UDE) *************/

+#define IS_TIM_DMA_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM6)   || \

+                                           ((INSTANCE) == TIM7)   || \

+                                           ((INSTANCE) == TIM8)   || \

+                                           ((INSTANCE) == TIM15)  || \

+                                           ((INSTANCE) == TIM16)  || \

+                                           ((INSTANCE) == TIM17))

+

+/************ TIM Instances : DMA requests generation (CCxDE) *****************/

+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15)  || \

+                                            ((INSTANCE) == TIM16)  || \

+                                            ((INSTANCE) == TIM17))

+

+/************ TIM Instances : DMA requests generation (COMDE) *****************/

+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15))

+

+/******************** TIM Instances : DMA burst feature ***********************/

+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8))

+

+/*************** TIM Instances : external trigger reamp input available *******/

+#define IS_TIM_ETR_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : remapping capability **********************/

+#define IS_TIM_REMAP_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \

+                                          ((INSTANCE) == TIM2)  || \

+                                          ((INSTANCE) == TIM3)  || \

+                                          ((INSTANCE) == TIM5)  || \

+                                          ((INSTANCE) == TIM8)  || \

+                                          ((INSTANCE) == TIM16) || \

+                                          ((INSTANCE) == TIM17))

+

+/*************** TIM Instances : external trigger reamp input available *******/

+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                              ((INSTANCE) == TIM2)   || \

+                                              ((INSTANCE) == TIM3)   || \

+                                              ((INSTANCE) == TIM5)   || \

+                                              ((INSTANCE) == TIM8))

+

+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/

+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM6)   || \

+                                            ((INSTANCE) == TIM7)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15))

+

+/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/

+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM8)   || \

+                                           ((INSTANCE) == TIM12))

+

+/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/

+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM8))

+

+/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/

+#define IS_TIM_TISEL_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)   || \

+                                          ((INSTANCE) == TIM2)   || \

+                                          ((INSTANCE) == TIM3)   || \

+                                          ((INSTANCE) == TIM4)   || \

+                                          ((INSTANCE) == TIM5)   || \

+                                          ((INSTANCE) == TIM8)   || \

+                                          ((INSTANCE) == TIM15)  || \

+                                          ((INSTANCE) == TIM16)  || \

+                                          ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting commutation event *************/

+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \

+                                                     ((INSTANCE) == TIM8)    || \

+                                                     ((INSTANCE) == TIM15)   || \

+                                                     ((INSTANCE) == TIM16)   || \

+                                                     ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting encoder interface **************/

+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1)  || \

+                                                      ((__INSTANCE__) == TIM2)      || \

+                                                      ((__INSTANCE__) == TIM3)      || \

+                                                      ((__INSTANCE__) == TIM4)      || \

+                                                      ((__INSTANCE__) == TIM5)      || \

+                                                      ((__INSTANCE__) == TIM8))

+

+/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/

+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                                       ((INSTANCE) == TIM8))

+/******************* TIM Instances : output(s) available **********************/

+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \

+    ((((INSTANCE) == TIM1) &&                  \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4) ||          \

+      ((CHANNEL) == TIM_CHANNEL_5) ||          \

+      ((CHANNEL) == TIM_CHANNEL_6)))           \

+     ||                                        \

+     (((INSTANCE) == TIM2) &&                  \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM3) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1)||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM4) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM5) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM8) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4) ||          \

+      ((CHANNEL) == TIM_CHANNEL_5) ||          \

+      ((CHANNEL) == TIM_CHANNEL_6)))           \

+  ||                                           \

+     (((INSTANCE) == TIM12) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2)))           \

+  ||                                           \

+     (((INSTANCE) == TIM13) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM14) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM15) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+     ((CHANNEL) == TIM_CHANNEL_2)))            \

+  ||                                           \

+     (((INSTANCE) == TIM16) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM17) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1))))

+

+/****************** TIM Instances : supporting the break function *************/

+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\

+      (((INSTANCE) == TIM1)    || \

+      ((INSTANCE) == TIM8)     || \

+       ((INSTANCE) == TIM15)   || \

+       ((INSTANCE) == TIM16)   || \

+       ((INSTANCE) == TIM17))

+

+/************** TIM Instances : supporting Break source selection *************/

+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \

+                                               ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting complementary output(s) ********/

+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \

+   ((((INSTANCE) == TIM1) &&                    \

+     (((CHANNEL) == TIM_CHANNEL_1) ||           \

+      ((CHANNEL) == TIM_CHANNEL_2) ||           \

+      ((CHANNEL) == TIM_CHANNEL_3)))            \

+ ||                                             \

+      (((INSTANCE) == TIM8) &&                  \

+      (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||           \

+      ((CHANNEL) == TIM_CHANNEL_3)))            \

+    ||                                          \

+    (((INSTANCE) == TIM15) &&                   \

+      ((CHANNEL) == TIM_CHANNEL_1))             \

+    ||                                          \

+    (((INSTANCE) == TIM16) &&                   \

+     ((CHANNEL) == TIM_CHANNEL_1))              \

+    ||                                          \

+    (((INSTANCE) == TIM17) &&                   \

+     ((CHANNEL) == TIM_CHANNEL_1)))

+

+/****************** TIM Instances : supporting counting mode selection ********/

+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting repetition counter *************/

+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15)   || \

+   ((INSTANCE) == TIM16)   || \

+   ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting synchronization ****************/

+#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\

+    (((__INSTANCE__) == TIM1)    || \

+     ((__INSTANCE__) == TIM2)    || \

+     ((__INSTANCE__) == TIM3)    || \

+     ((__INSTANCE__) == TIM4)    || \

+     ((__INSTANCE__) == TIM5)    || \

+     ((__INSTANCE__) == TIM6)    || \

+     ((__INSTANCE__) == TIM8)    || \

+     ((__INSTANCE__) == TIM12)   || \

+     ((__INSTANCE__) == TIM15))

+

+/****************** TIM Instances : supporting clock division *****************/

+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15)   || \

+   ((INSTANCE) == TIM16)   || \

+   ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting external clock mode 1 for ETRF input */

+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting external clock mode 2 **********/

+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\

+ (((INSTANCE) == TIM1)     || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/

+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/

+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : supporting OCxREF clear *******************/

+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3))

+

+/****************** TIM Instances : TIM_32B_COUNTER ***************************/

+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM5))

+

+/****************** TIM Instances : TIM_BKIN2 ***************************/

+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting Hall sensor interface **********/

+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)  || \

+                                                             ((__INSTANCE__) == TIM2)  || \

+                                                             ((__INSTANCE__) == TIM3)  || \

+                                                             ((__INSTANCE__) == TIM4)  || \

+                                                             ((__INSTANCE__) == TIM5)  || \

+                                                             ((__INSTANCE__) == TIM15) || \

+                                                             ((__INSTANCE__) == TIM8))

+

+/******************** USART Instances : Synchronous mode **********************/

+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                     ((INSTANCE) == USART2) || \

+                                     ((INSTANCE) == USART3) || \

+                                     ((INSTANCE) == USART6) || \

+                                     ((INSTANCE) == USART10))

+

+/******************** USART Instances : SPI slave mode ************************/

+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                              ((INSTANCE) == USART2) || \

+                                              ((INSTANCE) == USART3) || \

+                                              ((INSTANCE) == USART6) || \

+                                              ((INSTANCE) == USART10))

+

+/******************** UART Instances : Asynchronous mode **********************/

+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                    ((INSTANCE) == USART2) || \

+                                    ((INSTANCE) == USART3) || \

+                                    ((INSTANCE) == UART4)  || \

+                                    ((INSTANCE) == UART5)  || \

+                                    ((INSTANCE) == USART6) || \

+                                    ((INSTANCE) == UART7)  || \

+                                    ((INSTANCE) == UART8)  || \

+                                    ((INSTANCE) == UART9)  || \

+                                    ((INSTANCE) == USART10))

+

+/******************** UART Instances : FIFO mode.******************************/

+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                         ((INSTANCE) == USART2) || \

+                                         ((INSTANCE) == USART3) || \

+                                         ((INSTANCE) == UART4)  || \

+                                         ((INSTANCE) == UART5)  || \

+                                         ((INSTANCE) == USART6) || \

+                                         ((INSTANCE) == UART7)  || \

+                                         ((INSTANCE) == UART8)  || \

+                                         ((INSTANCE) == UART9)  || \

+                                         ((INSTANCE) == USART10)|| \

+                                         ((INSTANCE) == LPUART1))

+

+/****************** UART Instances : Auto Baud Rate detection *****************/

+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                            ((INSTANCE) == USART2) || \

+                                                            ((INSTANCE) == USART3) || \

+                                                            ((INSTANCE) == UART4)  || \

+                                                            ((INSTANCE) == UART5)  || \

+                                                            ((INSTANCE) == USART6) || \

+                                                            ((INSTANCE) == UART7)  || \

+                                                            ((INSTANCE) == UART8)  || \

+                                                            ((INSTANCE) == UART9)  || \

+                                                            ((INSTANCE) == USART10))

+

+/*********************** UART Instances : Driver Enable ***********************/

+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                  ((INSTANCE) == USART2) || \

+                                                  ((INSTANCE) == USART3) || \

+                                                  ((INSTANCE) == UART4)  || \

+                                                  ((INSTANCE) == UART5)  || \

+                                                  ((INSTANCE) == USART6) || \

+                                                  ((INSTANCE) == UART7)  || \

+                                                  ((INSTANCE) == UART8)  || \

+                                                  ((INSTANCE) == UART9)  || \

+                                                  ((INSTANCE) == USART10)|| \

+                                                  ((INSTANCE) == LPUART1))

+

+/********************* UART Instances : Half-Duplex mode **********************/

+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                               ((INSTANCE) == USART2) || \

+                                               ((INSTANCE) == USART3) || \

+                                               ((INSTANCE) == UART4)  || \

+                                               ((INSTANCE) == UART5)  || \

+                                               ((INSTANCE) == USART6) || \

+                                               ((INSTANCE) == UART7)  || \

+                                               ((INSTANCE) == UART8)  || \

+                                               ((INSTANCE) == UART9)  || \

+                                               ((INSTANCE) == USART10)|| \

+                                               ((INSTANCE) == LPUART1))

+

+/******************* UART Instances : Hardware Flow control *******************/

+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                           ((INSTANCE) == USART2) || \

+                                           ((INSTANCE) == USART3) || \

+                                           ((INSTANCE) == UART4)  || \

+                                           ((INSTANCE) == UART5)  || \

+                                           ((INSTANCE) == USART6) || \

+                                           ((INSTANCE) == UART7)  || \

+                                           ((INSTANCE) == UART8)  || \

+                                           ((INSTANCE) == UART9)  || \

+                                           ((INSTANCE) == USART10)|| \

+                                           ((INSTANCE) == LPUART1))

+

+/************************* UART Instances : LIN mode **************************/

+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                        ((INSTANCE) == USART2) || \

+                                        ((INSTANCE) == USART3) || \

+                                        ((INSTANCE) == UART4)  || \

+                                        ((INSTANCE) == UART5)  || \

+                                        ((INSTANCE) == USART6) || \

+                                        ((INSTANCE) == UART7)  || \

+                                        ((INSTANCE) == UART8)  || \

+                                        ((INSTANCE) == UART9)  || \

+                                        ((INSTANCE) == USART10))

+

+/****************** UART Instances : Wake-up from Stop mode *******************/

+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                    ((INSTANCE) == USART2) || \

+                                                    ((INSTANCE) == USART3) || \

+                                                    ((INSTANCE) == UART4)  || \

+                                                    ((INSTANCE) == UART5)  || \

+                                                    ((INSTANCE) == USART6) || \

+                                                    ((INSTANCE) == UART7)  || \

+                                                    ((INSTANCE) == UART8)  || \

+                                                    ((INSTANCE) == UART9)  || \

+                                                    ((INSTANCE) == USART10)|| \

+                                                    ((INSTANCE) == LPUART1))

+

+/************************* UART Instances : IRDA mode *************************/

+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                    ((INSTANCE) == USART2) || \

+                                    ((INSTANCE) == USART3) || \

+                                    ((INSTANCE) == UART4)  || \

+                                    ((INSTANCE) == UART5)  || \

+                                    ((INSTANCE) == USART6) || \

+                                    ((INSTANCE) == UART7)  || \

+                                    ((INSTANCE) == UART8)  || \

+                                    ((INSTANCE) == UART9)  || \

+                                    ((INSTANCE) == USART10))

+

+/********************* USART Instances : Smard card mode **********************/

+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                         ((INSTANCE) == USART2) || \

+                                         ((INSTANCE) == USART3) || \

+                                         ((INSTANCE) == USART6) ||\

+                                         ((INSTANCE) == USART10))

+

+/****************************** LPUART Instance *******************************/

+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)

+

+/****************************** IWDG Instances ********************************/

+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG1)

+/****************************** USB Instances ********************************/

+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)

+

+/****************************** WWDG Instances ********************************/

+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG1)

+/****************************** MDIOS Instances ********************************/

+#define IS_MDIOS_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == MDIOS)

+

+/****************************** CEC Instances *********************************/

+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)

+

+/****************************** SAI Instances ********************************/

+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \

+                                       ((INSTANCE) == SAI1_Block_B) || \

+                                       ((INSTANCE) == SAI2_Block_A) || \

+                                       ((INSTANCE) == SAI2_Block_B))

+

+/****************************** SPDIFRX Instances ********************************/

+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)

+

+/****************************** OPAMP Instances *******************************/

+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \

+                                         ((INSTANCE) == OPAMP2))

+

+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)

+

+/*********************** USB OTG PCD Instances ********************************/

+#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS)

+

+/*********************** USB OTG HCD Instances ********************************/

+#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS)

+

+/******************************************************************************/

+/*  For a painless codes migration between the STM32H7xx device product       */

+/*  lines, or with STM32F7xx devices the aliases defined below are put        */

+/*   in place to overcome the differences in the interrupt handlers and IRQn  */

+/*   definitions. No need to update developed interrupt code when moving      */

+/*  across product lines within the same STM32H7 Family                       */

+/******************************************************************************/

+

+/* Aliases for __IRQn */

+#define  RNG_IRQn                       HASH_RNG_IRQn

+#define  TIM1_BRK_TIM9_IRQn             TIM1_BRK_IRQn

+#define  TIM1_UP_TIM10_IRQn             TIM1_UP_IRQn

+#define  TIM1_TRG_COM_TIM11_IRQn        TIM1_TRG_COM_IRQn

+#define  PVD_IRQn                       PVD_AVD_IRQn

+

+/* Aliases for BDMA __IRQn */

+#define  BDMA_Channel0_IRQn             BDMA2_Channel0_IRQn

+#define  BDMA_Channel1_IRQn             BDMA2_Channel1_IRQn

+#define  BDMA_Channel2_IRQn             BDMA2_Channel2_IRQn

+#define  BDMA_Channel3_IRQn             BDMA2_Channel3_IRQn

+#define  BDMA_Channel4_IRQn             BDMA2_Channel4_IRQn

+#define  BDMA_Channel5_IRQn             BDMA2_Channel5_IRQn

+#define  BDMA_Channel6_IRQn             BDMA2_Channel6_IRQn

+#define  BDMA_Channel7_IRQn             BDMA2_Channel7_IRQn

+

+/* Aliases for PWR __IRQn */

+#define  PVD_AVD_IRQn                   PVD_PVM_IRQn

+

+/* Aliases for DCMI/PSSI __IRQn */

+#define  DCMI_IRQn                      DCMI_PSSI_IRQn

+

+/* Aliases for __IRQHandler */

+#define   RNG_IRQHandler               HASH_RNG_IRQHandler

+#define TIM1_BRK_TIM9_IRQHandler       TIM1_BRK_IRQHandler

+#define TIM1_UP_TIM9_IRQHandler        TIM1_UP_IRQHandler

+#define TIM1_TRG_COM_TIM11_IRQHandler  TIM1_TRG_COM_IRQHandler

+#define PVD_IRQHandler                 PVD_AVD_IRQHandler

+

+

+/* Aliases for BDMA __IRQHandler */

+#define  BDMA_Channel0_IRQHandler      BDMA2_Channel0_IRQHandler

+#define  BDMA_Channel1_IRQHandler      BDMA2_Channel1_IRQHandler

+#define  BDMA_Channel2_IRQHandler      BDMA2_Channel2_IRQHandler

+#define  BDMA_Channel3_IRQHandler      BDMA2_Channel3_IRQHandler

+#define  BDMA_Channel4_IRQHandler      BDMA2_Channel4_IRQHandler

+#define  BDMA_Channel5_IRQHandler      BDMA2_Channel5_IRQHandler

+#define  BDMA_Channel6_IRQHandler      BDMA2_Channel6_IRQHandler

+#define  BDMA_Channel7_IRQHandler      BDMA2_Channel7_IRQHandler

+

+/* Aliases for PWR __IRQHandler */

+#define  PVD_AVD_IRQHandler            PVD_PVM_IRQHandler

+

+/* Aliases for DCMI/PSSI __IRQHandler */

+#define  DCMI_IRQHandler               DCMI_PSSI_IRQHandler

+

+/* Alias for BDMA defines */

+#define BDMA_BASE              BDMA2_BASE

+#define BDMA_Channel0_BASE     BDMA2_Channel0_BASE

+#define BDMA_Channel1_BASE     BDMA2_Channel1_BASE

+#define BDMA_Channel2_BASE     BDMA2_Channel2_BASE

+#define BDMA_Channel3_BASE     BDMA2_Channel3_BASE

+#define BDMA_Channel4_BASE     BDMA2_Channel4_BASE

+#define BDMA_Channel5_BASE     BDMA2_Channel5_BASE

+#define BDMA_Channel6_BASE     BDMA2_Channel6_BASE

+#define BDMA_Channel7_BASE     BDMA2_Channel7_BASE

+

+#define BDMA                   BDMA2

+#define BDMA_Channel0          BDMA2_Channel0

+#define BDMA_Channel1          BDMA2_Channel1

+#define BDMA_Channel2          BDMA2_Channel2

+#define BDMA_Channel3          BDMA2_Channel3

+#define BDMA_Channel4          BDMA2_Channel4

+#define BDMA_Channel5          BDMA2_Channel5

+#define BDMA_Channel6          BDMA2_Channel6

+#define BDMA_Channel7          BDMA2_Channel7

+

+/* Alias for PWR defines */

+#define PWR_CPUCR_RUN_D3       PWR_CPUCR_RUN_SRD

+#define PWR_CPUCR_PDDS_D3      PWR_CPUCR_PDDS_SRD

+#define PWR_CPUCR_PDDS_D1      PWR_CPUCR_RETDS_CD

+

+#define PWR_D3CR_VOS           PWR_SRDCR_VOS

+

+#define PWR_D3CR_VOS_0         PWR_SRDCR_VOS_0

+#define PWR_D3CR_VOS_1         PWR_SRDCR_VOS_1

+#define PWR_D3CR_VOSRDY        PWR_SRDCR_VOSRDY

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif /* __cplusplus */

+

+#endif /* STM32H7B0xx_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7b0xxq.h b/bsps/arm/stm32h7/include/stm32h7b0xxq.h
new file mode 100644
index 0000000000..bccf541c15
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7b0xxq.h
@@ -0,0 +1,22906 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7b0xxQ.h

+  * @author  MCD Application Team

+  * @brief   CMSIS STM32H7B0xxQ Device Peripheral Access Layer Header File.

+  *

+  *          This file contains:

+  *           - Data structures and the address mapping for all peripherals

+  *           - Peripheral's registers declarations and bits definition

+  *           - Macros to access peripheral's registers hardware

+  *

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/** @addtogroup CMSIS_Device

+  * @{

+  */

+

+/** @addtogroup stm32h7b0xxQ

+  * @{

+  */

+

+#ifndef STM32H7B0xxQ_H

+#define STM32H7B0xxQ_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif /* __cplusplus */

+

+/** @addtogroup Peripheral_interrupt_number_definition

+  * @{

+  */

+

+/**

+ * @brief STM32H7XX Interrupt Number Definition, according to the selected device

+ *        in @ref Library_configuration_section

+ */

+typedef enum

+{

+/******  Cortex-M Processor Exceptions Numbers *****************************************************************/

+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */

+  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */

+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */

+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */

+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */

+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M SV Call Interrupt                                     */

+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M Debug Monitor Interrupt                               */

+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M Pend SV Interrupt                                     */

+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M System Tick Interrupt                                 */

+/******  STM32 specific Interrupt Numbers **********************************************************************/

+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)                   */

+  PVD_PVM_IRQn                = 1,      /*!< PVD/PVM through EXTI Line detection Interrupt                     */

+  RTC_TAMP_STAMP_CSS_LSE_IRQn = 2,      /*!< Tamper, TimeStamp, CSS and LSE interrupts through the EXTI line   */

+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */

+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */

+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */

+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */

+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */

+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */

+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */

+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */

+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */

+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */

+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */

+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */

+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */

+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */

+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */

+  ADC_IRQn                    = 18,     /*!< ADC1 and  ADC2 global Interrupts                                  */

+  FDCAN1_IT0_IRQn             = 19,     /*!< FDCAN1 Interrupt line 0                                           */

+  FDCAN2_IT0_IRQn             = 20,     /*!< FDCAN2 Interrupt line 0                                           */

+  FDCAN1_IT1_IRQn             = 21,     /*!< FDCAN1 Interrupt line 1                                           */

+  FDCAN2_IT1_IRQn             = 22,     /*!< FDCAN2 Interrupt line 1                                           */

+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */

+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                              */

+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                             */

+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt                            */

+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */

+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */

+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */

+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */

+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */

+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */

+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */

+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */

+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */

+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */

+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */

+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */

+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */

+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */

+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */

+  DFSDM2_IRQn                 = 42,     /*!< DFSDM2 global Interrupt                                           */

+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */

+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */

+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */

+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */

+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */

+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */

+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */

+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */

+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */

+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */

+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */

+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */

+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */

+  DMA2_Stream0_IRQn           = 56,     /*!<   DMA2 Stream 0 global Interrupt                                  */

+  DMA2_Stream1_IRQn           = 57,     /*!<   DMA2 Stream 1 global Interrupt                                  */

+  DMA2_Stream2_IRQn           = 58,     /*!<   DMA2 Stream 2 global Interrupt                                  */

+  DMA2_Stream3_IRQn           = 59,     /*!<   DMA2 Stream 3 global Interrupt                                  */

+  DMA2_Stream4_IRQn           = 60,     /*!<   DMA2 Stream 4 global Interrupt                                  */

+  FDCAN_CAL_IRQn              = 63,     /*!< FDCAN Calibration unit Interrupt                                  */

+  DFSDM1_FLT4_IRQn            = 64,     /*!< DFSDM Filter4 Interrupt                                           */

+  DFSDM1_FLT5_IRQn            = 65,     /*!< DFSDM Filter5 Interrupt                                           */

+  DFSDM1_FLT6_IRQn            = 66,     /*!< DFSDM Filter6 Interrupt                                           */

+  DFSDM1_FLT7_IRQn            = 67,     /*!< DFSDM Filter7 Interrupt                                           */

+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */

+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */

+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */

+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */

+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */

+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */

+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */

+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */

+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */

+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */

+  DCMI_PSSI_IRQn              = 78,     /*!< DCMI and PSSI global interrupt                                    */

+  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */

+  HASH_RNG_IRQn               = 80,     /*!< HASH and RNG global interrupt                                     */

+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */

+  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */

+  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */

+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */

+  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */

+  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */

+  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */

+  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */

+  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */

+  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */

+  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */

+  OCTOSPI1_IRQn               = 92,     /*!< OCTOSPI1 global interrupt                                         */

+  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */

+  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */

+  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */

+  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */

+  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */

+  DMAMUX1_OVR_IRQn            = 102,    /*!<DMAMUX1 Overrun interrupt                                          */

+  DFSDM1_FLT0_IRQn            = 110,    /*!<DFSDM Filter1 Interrupt                                            */

+  DFSDM1_FLT1_IRQn            = 111,    /*!<DFSDM Filter2 Interrupt                                            */

+  DFSDM1_FLT2_IRQn            = 112,    /*!<DFSDM Filter3 Interrupt                                            */

+  DFSDM1_FLT3_IRQn            = 113,    /*!<DFSDM Filter4 Interrupt                                            */

+  SWPMI1_IRQn                 = 115,    /*!< Serial Wire Interface 1 global interrupt                          */

+  TIM15_IRQn                  = 116,    /*!< TIM15 global Interrupt                                            */

+  TIM16_IRQn                  = 117,    /*!< TIM16 global Interrupt                                            */

+  TIM17_IRQn                  = 118,    /*!< TIM17 global Interrupt                                            */

+  MDIOS_WKUP_IRQn             = 119,    /*!< MDIOS Wakeup  Interrupt                                           */

+  MDIOS_IRQn                  = 120,    /*!< MDIOS global Interrupt                                            */

+  JPEG_IRQn                   = 121,    /*!< JPEG global Interrupt                                             */

+  MDMA_IRQn                   = 122,    /*!< MDMA global Interrupt                                             */

+  SDMMC2_IRQn                 = 124,    /*!< SDMMC2 global Interrupt                                           */

+  HSEM1_IRQn                  = 125,    /*!< HSEM1 global Interrupt                                            */

+  DAC2_IRQn                   = 127,    /*!< DAC2 global Interrupt                                             */

+  DMAMUX2_OVR_IRQn            = 128,    /*!<DMAMUX2 Overrun interrupt                                          */

+  BDMA2_Channel0_IRQn         = 129,    /*!< BDMA2 Channel 0 global Interrupt                                  */

+  BDMA2_Channel1_IRQn         = 130,    /*!< BDMA2 Channel 1 global Interrupt                                  */

+  BDMA2_Channel2_IRQn         = 131,    /*!< BDMA2 Channel 2 global Interrupt                                  */

+  BDMA2_Channel3_IRQn         = 132,    /*!< BDMA2 Channel 3 global Interrupt                                  */

+  BDMA2_Channel4_IRQn         = 133,    /*!< BDMA2 Channel 4 global Interrupt                                  */

+  BDMA2_Channel5_IRQn         = 134,    /*!< BDMA2 Channel 5 global Interrupt                                  */

+  BDMA2_Channel6_IRQn         = 135,    /*!< BDMA2 Channel 6 global Interrupt                                  */

+  BDMA2_Channel7_IRQn         = 136,    /*!< BDMA2 Channel 7 global Interrupt                                  */

+  COMP_IRQn                   = 137 ,   /*!< COMP global Interrupt                                             */

+  LPTIM2_IRQn                 = 138,    /*!< LP TIM2 global interrupt                                          */

+  LPTIM3_IRQn                 = 139,    /*!< LP TIM3 global interrupt                                          */

+  UART9_IRQn                  = 140,    /*!< UART9 global interrupt                                            */

+  USART10_IRQn                = 141,    /*!< USART10 global interrupt                                          */

+  LPUART1_IRQn                = 142,    /*!< LP UART1 interrupt                                                */

+  WWDG_RST_IRQn               = 143,    /*!<Window Watchdog Event interrupt                                    */

+  CRS_IRQn                    = 144,    /*!< Clock Recovery Global Interrupt                                   */

+  ECC_IRQn                    = 145,    /*!< ECC diagnostic Global Interrupt                                   */

+  DTS_IRQn                    = 147,    /*!< Digital Temperature Sensor Global Interrupt                       */

+  WAKEUP_PIN_IRQn             = 149,    /*!< Interrupt for all 6 wake-up pins                                  */

+  OCTOSPI2_IRQn               = 150,    /*!< OctoSPI2 global interrupt                                         */

+  OTFDEC1_IRQn                = 151,    /*!< OTFDEC1 global interrupt                                          */

+  OTFDEC2_IRQn                = 152,    /*!< OTFDEC2 global interrupt                                          */

+  GFXMMU_IRQn                 = 153,    /*!< GFXMMU global interrupt                                           */

+  BDMA1_IRQn                  = 154,    /*!< BDMA1 for DFSM global interrupt                                   */

+} IRQn_Type;

+

+/**

+  * @}

+  */

+

+/** @addtogroup Configuration_section_for_CMSIS

+  * @{

+  */

+

+#define SMPS       /*!< Switched mode power supply feature */

+

+

+

+/**

+  * @brief Configuration of the Cortex-M7 Processor and Core Peripherals

+   */

+#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */

+#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */

+#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */

+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */

+#define __FPU_PRESENT             1       /*!< FPU present                                   */

+#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */

+#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */

+#include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */

+

+/**

+  * @}

+  */

+

+

+

+

+#include "system_stm32h7xx.h"

+#include <stdint.h>

+

+/** @addtogroup Peripheral_registers_structures

+  * @{

+  */

+

+/**

+  * @brief Analog to Digital Converter

+  */

+

+typedef struct

+{

+  __IO uint32_t ISR;              /*!< ADC Interrupt and Status Register,                          Address offset: 0x00 */

+  __IO uint32_t IER;              /*!< ADC Interrupt Enable Register,                              Address offset: 0x04 */

+  __IO uint32_t CR;               /*!< ADC control register,                                       Address offset: 0x08 */

+  __IO uint32_t CFGR;             /*!< ADC Configuration register,                                 Address offset: 0x0C */

+  __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                               Address offset: 0x10 */

+  __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                                 Address offset: 0x14 */

+  __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                                 Address offset: 0x18 */

+  __IO uint32_t PCSEL;            /*!< ADC pre-channel selection,                                  Address offset: 0x1C */

+  __IO uint32_t LTR1;             /*!< ADC watchdog Lower threshold register 1,                    Address offset: 0x20 */

+  __IO uint32_t HTR1;             /*!< ADC watchdog higher threshold register 1,                   Address offset: 0x24 */

+  uint32_t      RESERVED1;        /*!< Reserved, 0x028                                                                  */

+  uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                                  */

+  __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                            Address offset: 0x30 */

+  __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                            Address offset: 0x34 */

+  __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                            Address offset: 0x38 */

+  __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                            Address offset: 0x3C */

+  __IO uint32_t DR;               /*!< ADC regular data register,                                  Address offset: 0x40 */

+  uint32_t      RESERVED3;        /*!< Reserved, 0x044                                                                  */

+  uint32_t      RESERVED4;        /*!< Reserved, 0x048                                                                  */

+  __IO uint32_t JSQR;             /*!< ADC injected sequence register,                             Address offset: 0x4C */

+  uint32_t      RESERVED5[4];     /*!< Reserved, 0x050 - 0x05C                                                          */

+  __IO uint32_t OFR1;             /*!< ADC offset register 1,                                      Address offset: 0x60 */

+  __IO uint32_t OFR2;             /*!< ADC offset register 2,                                      Address offset: 0x64 */

+  __IO uint32_t OFR3;             /*!< ADC offset register 3,                                      Address offset: 0x68 */

+  __IO uint32_t OFR4;             /*!< ADC offset register 4,                                      Address offset: 0x6C */

+  uint32_t      RESERVED6[4];     /*!< Reserved, 0x070 - 0x07C                                                          */

+  __IO uint32_t JDR1;             /*!< ADC injected data register 1,                               Address offset: 0x80 */

+  __IO uint32_t JDR2;             /*!< ADC injected data register 2,                               Address offset: 0x84 */

+  __IO uint32_t JDR3;             /*!< ADC injected data register 3,                               Address offset: 0x88 */

+  __IO uint32_t JDR4;             /*!< ADC injected data register 4,                               Address offset: 0x8C */

+  uint32_t      RESERVED7[4];     /*!< Reserved, 0x090 - 0x09C                                                          */

+  __IO uint32_t AWD2CR;           /*!< ADC  Analog Watchdog 2 Configuration Register,              Address offset: 0xA0 */

+  __IO uint32_t AWD3CR;           /*!< ADC  Analog Watchdog 3 Configuration Register,              Address offset: 0xA4 */

+  uint32_t      RESERVED8;        /*!< Reserved, 0x0A8                                                                  */

+  uint32_t      RESERVED9;        /*!< Reserved, 0x0AC                                                                  */

+  __IO uint32_t LTR2;             /*!< ADC watchdog Lower threshold register 2,                    Address offset: 0xB0 */

+  __IO uint32_t HTR2;             /*!< ADC watchdog Higher threshold register 2,                   Address offset: 0xB4 */

+  __IO uint32_t LTR3;             /*!< ADC watchdog Lower threshold register 3,                    Address offset: 0xB8 */

+  __IO uint32_t HTR3;             /*!< ADC watchdog Higher threshold register 3,                   Address offset: 0xBC */

+  __IO uint32_t DIFSEL;           /*!< ADC  Differential Mode Selection Register,                  Address offset: 0xC0 */

+  __IO uint32_t CALFACT;          /*!< ADC  Calibration Factors,                                   Address offset: 0xC4 */

+  __IO uint32_t CALFACT2;         /*!< ADC  Linearity Calibration Factors,                         Address offset: 0xC8 */

+} ADC_TypeDef;

+

+

+typedef struct

+{

+__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */

+uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */

+__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */

+__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */

+__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */

+

+} ADC_Common_TypeDef;

+

+

+/**

+  * @brief VREFBUF

+  */

+

+typedef struct

+{

+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */

+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */

+} VREFBUF_TypeDef;

+

+

+/**

+  * @brief FD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */

+  __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */

+  __IO uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */

+  __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */

+  __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */

+  __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */

+  __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */

+  __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */

+  __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */

+  __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */

+  __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */

+  __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */

+  __IO uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */

+  __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */

+  __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */

+  __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */

+  __IO uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */

+  __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */

+  __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */

+  __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */

+  __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */

+  __IO uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */

+  __IO uint32_t GFC;          /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */

+  __IO uint32_t SIDFC;        /*!< FDCAN Standard ID Filter Configuration register,                 Address offset: 0x084 */

+  __IO uint32_t XIDFC;        /*!< FDCAN Extended ID Filter Configuration register,                 Address offset: 0x088 */

+  __IO uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */

+  __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x090 */

+  __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x094 */

+  __IO uint32_t NDAT1;        /*!< FDCAN New Data 1 register,                                       Address offset: 0x098 */

+  __IO uint32_t NDAT2;        /*!< FDCAN New Data 2 register,                                       Address offset: 0x09C */

+  __IO uint32_t RXF0C;        /*!< FDCAN Rx FIFO 0 Configuration register,                          Address offset: 0x0A0 */

+  __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x0A4 */

+  __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x0A8 */

+  __IO uint32_t RXBC;         /*!< FDCAN Rx Buffer Configuration register,                          Address offset: 0x0AC */

+  __IO uint32_t RXF1C;        /*!< FDCAN Rx FIFO 1 Configuration register,                          Address offset: 0x0B0 */

+  __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x0B4 */

+  __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x0B8 */

+  __IO uint32_t RXESC;        /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register,        Address offset: 0x0BC */

+  __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */

+  __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */

+  __IO uint32_t TXESC;        /*!< FDCAN Tx Buffer Element Size Configuration register,             Address offset: 0x0C8 */

+  __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0CC */

+  __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0D0 */

+  __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D4 */

+  __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D8 */

+  __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0DC */

+  __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0E0 */

+  __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */

+  __IO uint32_t RESERVED6[2]; /*!< Reserved,                                                                0x0E8 - 0x0EC */

+  __IO uint32_t TXEFC;        /*!< FDCAN Tx Event FIFO Configuration register,                      Address offset: 0x0F0 */

+  __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0F4 */

+  __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0F8 */

+  __IO uint32_t RESERVED7;    /*!< Reserved,                                                                        0x0FC */

+} FDCAN_GlobalTypeDef;

+

+/**

+  * @brief TTFD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t TTTMC;          /*!< TT Trigger Memory Configuration register,    Address offset: 0x100 */

+  __IO uint32_t TTRMC;          /*!< TT Reference Message Configuration register, Address offset: 0x104 */

+  __IO uint32_t TTOCF;          /*!< TT Operation Configuration register,         Address offset: 0x108 */

+  __IO uint32_t TTMLM;          /*!< TT Matrix Limits register,                   Address offset: 0x10C */

+  __IO uint32_t TURCF;          /*!< TUR Configuration register,                  Address offset: 0x110 */

+  __IO uint32_t TTOCN;          /*!< TT Operation Control register,               Address offset: 0x114 */

+  __IO uint32_t TTGTP;          /*!< TT Global Time Preset register,              Address offset: 0x118 */

+  __IO uint32_t TTTMK;          /*!< TT Time Mark register,                       Address offset: 0x11C */

+  __IO uint32_t TTIR;           /*!< TT Interrupt register,                       Address offset: 0x120 */

+  __IO uint32_t TTIE;           /*!< TT Interrupt Enable register,                Address offset: 0x124 */

+  __IO uint32_t TTILS;          /*!< TT Interrupt Line Select register,           Address offset: 0x128 */

+  __IO uint32_t TTOST;          /*!< TT Operation Status register,                Address offset: 0x12C */

+  __IO uint32_t TURNA;          /*!< TT TUR Numerator Actual register,            Address offset: 0x130 */

+  __IO uint32_t TTLGT;          /*!< TT Local and Global Time register,           Address offset: 0x134 */

+  __IO uint32_t TTCTC;          /*!< TT Cycle Time and Count register,            Address offset: 0x138 */

+  __IO uint32_t TTCPT;          /*!< TT Capture Time register,                    Address offset: 0x13C */

+  __IO uint32_t TTCSM;          /*!< TT Cycle Sync Mark register,                 Address offset: 0x140 */

+  __IO uint32_t RESERVED1[111]; /*!< Reserved,                                            0x144 - 0x2FC */

+  __IO uint32_t TTTS;           /*!< TT Trigger Select register,                  Address offset: 0x300 */

+} TTCAN_TypeDef;

+

+/**

+  * @brief FD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t CREL;  /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */

+  __IO uint32_t CCFG;  /*!< Calibration Configuration register,           Address offset: 0x04 */

+  __IO uint32_t CSTAT; /*!< Calibration Status register,                  Address offset: 0x08 */

+  __IO uint32_t CWD;   /*!< Calibration Watchdog register,                Address offset: 0x0C */

+  __IO uint32_t IR;    /*!< CCU Interrupt register,                       Address offset: 0x10 */

+  __IO uint32_t IE;    /*!< CCU Interrupt Enable register,                Address offset: 0x14 */

+} FDCAN_ClockCalibrationUnit_TypeDef;

+

+

+/**

+  * @brief Consumer Electronics Control

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;           /*!< CEC control register,              Address offset:0x00 */

+  __IO uint32_t CFGR;         /*!< CEC configuration register,        Address offset:0x04 */

+  __IO uint32_t TXDR;         /*!< CEC Tx data register ,             Address offset:0x08 */

+  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,              Address offset:0x0C */

+  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register, Address offset:0x10 */

+  __IO uint32_t IER;          /*!< CEC interrupt enable register,     Address offset:0x14 */

+}CEC_TypeDef;

+

+/**

+  * @brief CRC calculation unit

+  */

+

+typedef struct

+{

+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */

+  __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */

+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */

+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */

+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */

+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */

+} CRC_TypeDef;

+

+

+/**

+  * @brief Clock Recovery System

+  */

+typedef struct

+{

+__IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */

+__IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */

+__IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */

+__IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */

+} CRS_TypeDef;

+

+

+/**

+  * @brief Digital to Analog Converter

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */

+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */

+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */

+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */

+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */

+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */

+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */

+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */

+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */

+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */

+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */

+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */

+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */

+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */

+  __IO uint32_t CCR;      /*!< DAC calibration control register,                        Address offset: 0x38 */

+  __IO uint32_t MCR;      /*!< DAC mode control register,                               Address offset: 0x3C */

+  __IO uint32_t SHSR1;    /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */

+  __IO uint32_t SHSR2;    /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */

+  __IO uint32_t SHHR;     /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */

+  __IO uint32_t SHRR;     /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */

+} DAC_TypeDef;

+

+/**

+  * @brief DFSDM module registers

+  */

+typedef struct

+{

+  __IO uint32_t FLTCR1;          /*!< DFSDM control register1,                          Address offset: 0x100 */

+  __IO uint32_t FLTCR2;          /*!< DFSDM control register2,                          Address offset: 0x104 */

+  __IO uint32_t FLTISR;          /*!< DFSDM interrupt and status register,              Address offset: 0x108 */

+  __IO uint32_t FLTICR;          /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */

+  __IO uint32_t FLTJCHGR;        /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */

+  __IO uint32_t FLTFCR;          /*!< DFSDM filter control register,                    Address offset: 0x114 */

+  __IO uint32_t FLTJDATAR;       /*!< DFSDM data register for injected group,           Address offset: 0x118 */

+  __IO uint32_t FLTRDATAR;       /*!< DFSDM data register for regular group,            Address offset: 0x11C */

+  __IO uint32_t FLTAWHTR;        /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */

+  __IO uint32_t FLTAWLTR;        /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */

+  __IO uint32_t FLTAWSR;         /*!< DFSDM analog watchdog status register             Address offset: 0x128 */

+  __IO uint32_t FLTAWCFR;        /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */

+  __IO uint32_t FLTEXMAX;        /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */

+  __IO uint32_t FLTEXMIN;        /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */

+  __IO uint32_t FLTCNVTIMR;      /*!< DFSDM conversion timer,                           Address offset: 0x138 */

+} DFSDM_Filter_TypeDef;

+

+/**

+  * @brief DFSDM channel configuration registers

+  */

+typedef struct

+{

+  __IO uint32_t CHCFGR1;      /*!< DFSDM channel configuration register1,            Address offset: 0x00 */

+  __IO uint32_t CHCFGR2;      /*!< DFSDM channel configuration register2,            Address offset: 0x04 */

+  __IO uint32_t CHAWSCDR;     /*!< DFSDM channel analog watchdog and

+                                   short circuit detector register,                  Address offset: 0x08 */

+  __IO uint32_t CHWDATAR;     /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */

+  __IO uint32_t CHDATINR;     /*!< DFSDM channel data input register,                Address offset: 0x10 */

+  __IO uint32_t CHDLYR;       /*!< DFSDM channel delay register,                     Address offset: 0x14 */

+} DFSDM_Channel_TypeDef;

+

+/**

+  * @brief Debug MCU

+  */

+typedef struct

+{

+  __IO uint32_t IDCODE;        /*!< MCU device ID code,                     Address offset: 0x00 */

+  __IO uint32_t CR;            /*!< Debug MCU configuration register,       Address offset: 0x04 */

+  uint32_t RESERVED4[11];      /*!< Reserved,                             Address offset: 0x08 */

+  __IO uint32_t APB3FZ1;     /*!< Debug MCU APB3FZ1 freeze register,    Address offset: 0x34 */

+  uint32_t RESERVED5;          /*!< Reserved,                             Address offset: 0x38 */

+  __IO uint32_t APB1LFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x3C */

+  uint32_t RESERVED6;          /*!< Reserved,                             Address offset: 0x40 */

+  __IO uint32_t APB1HFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x44 */

+  uint32_t RESERVED7;          /*!< Reserved,                             Address offset: 0x48 */

+  __IO uint32_t APB2FZ1;     /*!< Debug MCU APB2FZ1 freeze register,    Address offset: 0x4C */

+  uint32_t RESERVED8;          /*!< Reserved,                             Address offset: 0x50 */

+  __IO uint32_t APB4FZ1;     /*!< Debug MCU APB4FZ1 freeze register,    Address offset: 0x54 */

+}DBGMCU_TypeDef;

+/**

+  * @brief DCMI

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */

+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */

+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */

+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */

+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */

+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */

+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */

+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */

+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */

+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */

+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */

+} DCMI_TypeDef;

+

+/**

+  * @brief PSSI

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;             /*!< PSSI control register 1,               Address offset: 0x000 */

+  __IO uint32_t SR;             /*!< PSSI status register,                  Address offset: 0x004 */

+  __IO uint32_t RIS;            /*!< PSSI raw interrupt status register,    Address offset: 0x008 */

+  __IO uint32_t IER;            /*!< PSSI interrupt enable register,        Address offset: 0x00C */

+  __IO uint32_t MIS;            /*!< PSSI masked interrupt status register, Address offset: 0x010 */

+  __IO uint32_t ICR;            /*!< PSSI interrupt clear register,         Address offset: 0x014 */

+  __IO uint32_t RESERVED1[4];   /*!< Reserved,                                      0x018 - 0x024 */

+  __IO uint32_t DR;             /*!< PSSI data register,                    Address offset: 0x028 */

+  __IO uint32_t RESERVED2[241]; /*!< Reserved,                                      0x02C - 0x3EC */

+  __IO uint32_t HWCFGR;         /*!< PSSI IP HW configuration register,     Address offset: 0x3F0 */

+  __IO uint32_t VERR;           /*!< PSSI IP version register,              Address offset: 0x3F4 */

+  __IO uint32_t IPIDR;          /*!< PSSI IP ID register,                   Address offset: 0x3F8 */

+  __IO uint32_t SIDR;           /*!< PSSI SIZE ID register,                 Address offset: 0x3FC */

+} PSSI_TypeDef;

+

+/**

+  * @brief DMA Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */

+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */

+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */

+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */

+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */

+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */

+} DMA_Stream_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */

+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */

+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */

+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */

+} DMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CCR;          /*!< DMA channel x configuration register          */

+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register         */

+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register     */

+  __IO uint32_t CM0AR;        /*!< DMA channel x memory 0 address register       */

+  __IO uint32_t CM1AR;        /*!< DMA channel x memory 1 address register       */

+} BDMA_Channel_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */

+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */

+} BDMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CCR;        /*!< DMA Multiplexer Channel x Control Register   */

+}DMAMUX_Channel_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CSR;      /*!< DMA Channel Status Register     */

+  __IO uint32_t  CFR;      /*!< DMA Channel Clear Flag Register */

+}DMAMUX_ChannelStatus_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  RGCR;        /*!< DMA Request Generator x Control Register   */

+}DMAMUX_RequestGen_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  RGSR;        /*!< DMA Request Generator Status Register       */

+  __IO uint32_t  RGCFR;       /*!< DMA Request Generator Clear Flag Register   */

+}DMAMUX_RequestGenStatus_TypeDef;

+

+/**

+  * @brief MDMA Controller

+  */

+typedef struct

+{

+  __IO uint32_t  GISR0;   /*!< MDMA Global Interrupt/Status Register 0,          Address offset: 0x00 */

+}MDMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CISR;      /*!< MDMA channel x interrupt/status register,             Address offset: 0x40 */

+  __IO uint32_t  CIFCR;     /*!< MDMA channel x interrupt flag clear register,         Address offset: 0x44 */

+  __IO uint32_t  CESR;      /*!< MDMA Channel x error status register,                 Address offset: 0x48 */

+  __IO uint32_t  CCR;       /*!< MDMA channel x control register,                      Address offset: 0x4C */

+  __IO uint32_t  CTCR;      /*!< MDMA channel x Transfer Configuration register,       Address offset: 0x50 */

+  __IO uint32_t  CBNDTR;    /*!< MDMA Channel x block number of data register,         Address offset: 0x54 */

+  __IO uint32_t  CSAR;      /*!< MDMA channel x source address register,               Address offset: 0x58 */

+  __IO uint32_t  CDAR;      /*!< MDMA channel x destination address register,          Address offset: 0x5C */

+  __IO uint32_t  CBRUR;     /*!< MDMA channel x Block Repeat address Update register,  Address offset: 0x60 */

+  __IO uint32_t  CLAR;      /*!< MDMA channel x Link Address register,                 Address offset: 0x64 */

+  __IO uint32_t  CTBR;      /*!< MDMA channel x Trigger and Bus selection Register,    Address offset: 0x68 */

+  uint32_t       RESERVED0; /*!< Reserved, 0x68                                                             */

+  __IO uint32_t  CMAR;      /*!< MDMA channel x Mask address register,                 Address offset: 0x70 */

+  __IO uint32_t  CMDR;      /*!< MDMA channel x Mask Data register,                    Address offset: 0x74 */

+}MDMA_Channel_TypeDef;

+

+/**

+  * @brief DMA2D Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */

+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */

+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */

+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */

+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */

+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */

+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */

+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */

+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */

+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */

+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */

+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */

+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */

+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */

+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */

+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */

+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */

+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */

+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */

+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */

+  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */

+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */

+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */

+} DMA2D_TypeDef;

+

+

+/**

+  * @brief External Interrupt/Event Controller

+  */

+

+typedef struct

+{

+__IO uint32_t RTSR1;               /*!< EXTI Rising trigger selection register,          Address offset: 0x00 */

+__IO uint32_t FTSR1;               /*!< EXTI Falling trigger selection register,         Address offset: 0x04 */

+__IO uint32_t SWIER1;              /*!< EXTI Software interrupt event register,          Address offset: 0x08 */

+__IO uint32_t D3PMR1;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */

+__IO uint32_t D3PCR1L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L)     Address offset: 0x10 */

+__IO uint32_t D3PCR1H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H)   Address offset: 0x14 */

+uint32_t      RESERVED1[2];        /*!< Reserved,                                        0x18 to 0x1C         */

+__IO uint32_t RTSR2;               /*!< EXTI Rising trigger selection register,          Address offset: 0x20 */

+__IO uint32_t FTSR2;               /*!< EXTI Falling trigger selection register,         Address offset: 0x24 */

+__IO uint32_t SWIER2;              /*!< EXTI Software interrupt event register,          Address offset: 0x28 */

+__IO uint32_t D3PMR2;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */

+__IO uint32_t D3PCR2L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L)  Address offset: 0x30 */

+__IO uint32_t D3PCR2H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */

+uint32_t      RESERVED2[2];        /*!< Reserved,                                        0x38 to 0x3C         */

+__IO uint32_t RTSR3;               /*!< EXTI Rising trigger selection register,          Address offset: 0x40 */

+__IO uint32_t FTSR3;               /*!< EXTI Falling trigger selection register,         Address offset: 0x44 */

+__IO uint32_t SWIER3;              /*!< EXTI Software interrupt event register,          Address offset: 0x48 */

+__IO uint32_t D3PMR3;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */

+__IO uint32_t D3PCR3L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */

+__IO uint32_t D3PCR3H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */

+uint32_t      RESERVED3[10];       /*!< Reserved,                                        0x58 to 0x7C         */

+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                    Address offset: 0x80 */

+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                        Address offset: 0x84 */

+__IO uint32_t PR1;                 /*!< EXTI Pending register,                           Address offset: 0x88 */

+uint32_t      RESERVED4;           /*!< Reserved,                                        0x8C                 */

+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                    Address offset: 0x90 */

+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                        Address offset: 0x94 */

+__IO uint32_t PR2;                 /*!< EXTI Pending register,                           Address offset: 0x98 */

+uint32_t      RESERVED5;           /*!< Reserved,                                        0x9C                 */

+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                    Address offset: 0xA0 */

+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                        Address offset: 0xA4 */

+__IO uint32_t PR3;                 /*!< EXTI Pending register,                           Address offset: 0xA8 */

+}EXTI_TypeDef;

+

+typedef struct

+{

+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                Address offset: 0x00 */

+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                    Address offset: 0x04 */

+__IO uint32_t PR1;                 /*!< EXTI Pending register,                       Address offset: 0x08 */

+uint32_t      RESERVED1;           /*!< Reserved, 0x0C                                                    */

+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                Address offset: 0x10 */

+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                    Address offset: 0x14 */

+__IO uint32_t PR2;                 /*!< EXTI Pending register,                       Address offset: 0x18 */

+uint32_t      RESERVED2;           /*!< Reserved, 0x1C                                                    */

+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                Address offset: 0x20 */

+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                    Address offset: 0x24 */

+__IO uint32_t PR3;                 /*!< EXTI Pending register,                       Address offset: 0x28 */

+}EXTI_Core_TypeDef;

+

+

+/**

+  * @brief FLASH Registers

+  */

+

+typedef struct

+{

+  __IO uint32_t ACR;             /*!< FLASH access control register,                            Address offset: 0x00  */

+  __IO uint32_t KEYR1;           /*!< Flash Key Register for bank1,                             Address offset: 0x04  */

+  __IO uint32_t OPTKEYR;         /*!< Flash Option Key Register,                                Address offset: 0x08  */

+  __IO uint32_t CR1;             /*!< Flash Control Register for bank1,                         Address offset: 0x0C  */

+  __IO uint32_t SR1;             /*!< Flash Status Register for bank1,                          Address offset: 0x10  */

+  __IO uint32_t CCR1;            /*!< Flash Control Register for bank1,                         Address offset: 0x14  */

+  __IO uint32_t OPTCR;           /*!< Flash Option Control Register,                            Address offset: 0x18  */

+  __IO uint32_t OPTSR_CUR;       /*!< Flash Option Status Current Register,                     Address offset: 0x1C  */

+  __IO uint32_t OPTSR_PRG;       /*!< Flash Option Status to Program Register,                  Address offset: 0x20  */

+  __IO uint32_t OPTCCR;          /*!< Flash Option Clear Control Register,                      Address offset: 0x24  */

+  __IO uint32_t PRAR_CUR1;       /*!< Flash Current Protection Address Register for bank1,      Address offset: 0x28  */

+  __IO uint32_t PRAR_PRG1;       /*!< Flash Protection Address to Program Register for bank1,   Address offset: 0x2C  */

+  __IO uint32_t SCAR_CUR1;       /*!< Flash Current Secure Address Register for bank1,          Address offset: 0x30  */

+  __IO uint32_t SCAR_PRG1;       /*!< Flash Secure Address to Program Register for bank1,       Address offset: 0x34  */

+  __IO uint32_t WPSN_CUR1;       /*!< Flash Current Write Protection Register on bank1,         Address offset: 0x38  */

+  __IO uint32_t WPSN_PRG1;       /*!< Flash Write Protection to Program Register on bank1,      Address offset: 0x3C  */

+  __IO uint32_t BOOT_CUR;        /*!< Flash Current Boot Address for Pelican Core Register,     Address offset: 0x40  */

+  __IO uint32_t BOOT_PRG;        /*!< Flash Boot Address to Program for Pelican Core Register,  Address offset: 0x44  */

+  uint32_t      RESERVED0[2];    /*!< Reserved, 0x48 to 0x4C                                                          */

+  __IO uint32_t CRCCR1;          /*!< Flash CRC Control register For Bank1 Register ,           Address offset: 0x50  */

+  __IO uint32_t CRCSADD1;        /*!< Flash CRC Start Address Register for Bank1 ,              Address offset: 0x54  */

+  __IO uint32_t CRCEADD1;        /*!< Flash CRC End Address Register for Bank1 ,                Address offset: 0x58  */

+  __IO uint32_t CRCDATA;         /*!< Flash CRC Data Register for Bank1 ,                       Address offset: 0x5C  */

+  __IO uint32_t ECC_FA1;         /*!< Flash ECC Fail Address For Bank1 Register ,               Address offset: 0x60  */

+  uint32_t      RESERVED;        /*!< Reserved, 0x64                                                                  */

+  __IO uint32_t OTPBL_CUR;       /*!< Flash Current OTP Block Lock Register,                    Address offset: 0x68  */

+  __IO uint32_t OTPBL_PRG;       /*!< Flash OTP Block Lock to Program Register,                 Address offset: 0x6C  */

+  uint32_t      RESERVED1[37];   /*!< Reserved, 0x70 to 0x100                                                         */

+  __IO uint32_t KEYR2;           /*!< Flash Key Register for bank2,                             Address offset: 0x104 */

+  uint32_t      RESERVED2;       /*!< Reserved, 0x108                                                                 */

+  __IO uint32_t CR2;             /*!< Flash Control Register for bank2,                         Address offset: 0x10C */

+  __IO uint32_t SR2;             /*!< Flash Status Register for bank2,                          Address offset: 0x110 */

+  __IO uint32_t CCR2;            /*!< Flash Status Register for bank2,                          Address offset: 0x114 */

+  uint32_t      RESERVED3[4];    /*!< Reserved, 0x118 to 0x124                                                        */

+  __IO uint32_t PRAR_CUR2;       /*!< Flash Current Protection Address Register for bank2,      Address offset: 0x128 */

+  __IO uint32_t PRAR_PRG2;       /*!< Flash Protection Address to Program Register for bank2,   Address offset: 0x12C */

+  __IO uint32_t SCAR_CUR2;       /*!< Flash Current Secure Address Register for bank2,          Address offset: 0x130 */

+  __IO uint32_t SCAR_PRG2;       /*!< Flash Secure Address Register for bank2,                  Address offset: 0x134 */

+  __IO uint32_t WPSN_CUR2;       /*!< Flash Current Write Protection Register on bank2,         Address offset: 0x138 */

+  __IO uint32_t WPSN_PRG2;       /*!< Flash Write Protection to Program Register on bank2,      Address offset: 0x13C */

+  uint32_t      RESERVED4[4];    /*!< Reserved, 0x140 to 0x14C                                                        */

+  __IO uint32_t CRCCR2;          /*!< Flash CRC Control register For Bank2 Register ,           Address offset: 0x150 */

+  __IO uint32_t CRCSADD2;        /*!< Flash CRC Start Address Register for Bank2 ,              Address offset: 0x154 */

+  __IO uint32_t CRCEADD2;        /*!< Flash CRC End Address Register for Bank2 ,                Address offset: 0x158 */

+  __IO uint32_t CRCDATA2;        /*!< Flash CRC Data Register for Bank2 ,                       Address offset: 0x15C */

+  __IO uint32_t ECC_FA2;         /*!< Flash ECC Fail Address For Bank2 Register ,               Address offset: 0x160 */

+} FLASH_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */

+} FMC_Bank1_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank1E

+  */

+

+typedef struct

+{

+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */

+} FMC_Bank1E_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank2

+  */

+

+typedef struct

+{

+  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */

+  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */

+  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */

+  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */

+  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */

+  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */

+} FMC_Bank2_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank3

+  */

+

+typedef struct

+{

+  __IO uint32_t PCR;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */

+  __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */

+  __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */

+  __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */

+  uint32_t      RESERVED;  /*!< Reserved, 0x90                                                            */

+  __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */

+} FMC_Bank3_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank5 and 6

+  */

+

+

+typedef struct

+{

+  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */

+  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */

+  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */

+  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */

+  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */

+} FMC_Bank5_6_TypeDef;

+

+/**

+  * @brief GFXMMU registers

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;              /*!< GFXMMU configuration register,                     Address offset: 0x00 */

+  __IO uint32_t SR;              /*!< GFXMMU status register,                            Address offset: 0x04 */

+  __IO uint32_t FCR;             /*!< GFXMMU flag clear register,                        Address offset: 0x08 */

+  __IO uint32_t CCR;             /*!< GFXMMU Cache Control Register,                     Address offset: 0x0C */

+  __IO uint32_t DVR;             /*!< GFXMMU default value register,                     Address offset: 0x10 */

+       uint32_t RESERVED1[3];    /*!< Reserved1,                                         Address offset: 0x14 to 0x1C */

+  __IO uint32_t B0CR;            /*!< GFXMMU buffer 0 configuration register,            Address offset: 0x20 */

+  __IO uint32_t B1CR;            /*!< GFXMMU buffer 1 configuration register,            Address offset: 0x24 */

+  __IO uint32_t B2CR;            /*!< GFXMMU buffer 2 configuration register,            Address offset: 0x28 */

+  __IO uint32_t B3CR;            /*!< GFXMMU buffer 3 configuration register,            Address offset: 0x2C */

+       uint32_t RESERVED2[1012]; /*!< Reserved2,                                         Address offset: 0x30 to 0xFFC */

+  __IO uint32_t LUT[2048];       /*!< GFXMMU LUT registers,                              Address offset: 0x1000 to 0x2FFC

+                                      For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */

+} GFXMMU_TypeDef;

+/**

+  * @brief General Purpose I/O

+  */

+

+typedef struct

+{

+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */

+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */

+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */

+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */

+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */

+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */

+  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset,               Address offset: 0x18      */

+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */

+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */

+} GPIO_TypeDef;

+

+/**

+  * @brief Operational Amplifier (OPAMP)

+  */

+

+typedef struct

+{

+  __IO uint32_t CSR;          /*!< OPAMP control/status register,                      Address offset: 0x00 */

+  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,     Address offset: 0x04 */

+  __IO uint32_t HSOTR;        /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */

+} OPAMP_TypeDef;

+

+/**

+  * @brief System configuration controller

+  */

+

+typedef struct

+{

+ uint32_t RESERVED1;           /*!< Reserved,                                           Address offset: 0x00        */

+ __IO uint32_t PMCR;           /*!< SYSCFG peripheral mode configuration register,      Address offset: 0x04        */

+ __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration registers,  Address offset: 0x08-0x14   */

+ __IO uint32_t CFGR;           /*!< SYSCFG configuration registers,                     Address offset: 0x18        */

+ uint32_t RESERVED2;           /*!< Reserved,                                           Address offset: 0x1C        */

+ __IO uint32_t CCCSR;          /*!< SYSCFG compensation cell control/status register,   Address offset: 0x20        */

+ __IO uint32_t CCVR;           /*!< SYSCFG compensation cell value register,            Address offset: 0x24        */

+ __IO uint32_t CCCR;           /*!< SYSCFG compensation cell code register,             Address offset: 0x28        */

+

+} SYSCFG_TypeDef;

+

+/**

+  * @brief Inter-integrated Circuit Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */

+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */

+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */

+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */

+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */

+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */

+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */

+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */

+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */

+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */

+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */

+} I2C_TypeDef;

+

+/**

+  * @brief Independent WATCHDOG

+  */

+

+typedef struct

+{

+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */

+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */

+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */

+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */

+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */

+} IWDG_TypeDef;

+

+

+/**

+  * @brief JPEG Codec

+  */

+typedef struct

+{

+  __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */

+  __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */

+  __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */

+  __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */

+  __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */

+  __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */

+  __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */

+  __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */

+  uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */

+  __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */

+  __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */

+  __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */

+  uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */

+  __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */

+  __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */

+  uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */

+  __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */

+  __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */

+  __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */

+  __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */

+  __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */

+  __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */

+  __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */

+  __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */

+  uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */

+  __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0,                 Address offset: 500h-65Ch */

+  __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1,                 Address offset: 660h-7BCh */

+  __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encodor, DC Huffman table 0,                 Address offset: 7C0h-7DCh */

+  __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encodor, DC Huffman table 1,                 Address offset: 7E0h-7FCh */

+

+} JPEG_TypeDef;

+

+/**

+  * @brief LCD-TFT Display Controller

+  */

+

+typedef struct

+{

+  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04                                                       */

+  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */

+  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */

+  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */

+  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */

+  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */

+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20                                                       */

+  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */

+  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28                                                            */

+  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */

+  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30                                                            */

+  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */

+  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */

+  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */

+  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */

+  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */

+  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */

+} LTDC_TypeDef;

+

+/**

+  * @brief LCD-TFT Display layer x Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */

+  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */

+  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */

+  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */

+  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */

+  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */

+  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */

+  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */

+  uint32_t      RESERVED0[2];  /*!< Reserved */

+  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */

+  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */

+  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */

+  uint32_t      RESERVED1[3];  /*!< Reserved */

+  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */

+

+} LTDC_Layer_TypeDef;

+

+/**

+  * @brief Power Control

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;       /*!< PWR power control register 1,            Address offset: 0x00 */

+  __IO uint32_t CSR1;      /*!< PWR power control status register 1,     Address offset: 0x04 */

+  __IO uint32_t CR2;       /*!< PWR power control register 2,            Address offset: 0x08 */

+  __IO uint32_t CR3;       /*!< PWR power control register 3,            Address offset: 0x0C */

+  __IO uint32_t CPUCR;     /*!< PWR CPU control register,                Address offset: 0x10 */

+       uint32_t RESERVED0; /*!< Reserved,                                Address offset: 0x14 */

+  __IO uint32_t SRDCR;     /*!< PWR SRD domain control register,         Address offset: 0x18 */

+       uint32_t RESERVED1; /*!< Reserved,                                Address offset: 0x1C */

+  __IO uint32_t WKUPCR;    /*!< PWR wakeup clear register,               Address offset: 0x20 */

+  __IO uint32_t WKUPFR;    /*!< PWR wakeup flag register,                Address offset: 0x24 */

+  __IO uint32_t WKUPEPR;   /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */

+} PWR_TypeDef;

+

+/**

+  * @brief Reset and Clock Control

+  */

+

+typedef struct

+{

+ __IO uint32_t CR;             /*!< RCC clock control register,                                              Address offset: 0x00  */

+ __IO uint32_t HSICFGR;        /*!< HSI Clock Calibration Register,                                          Address offset: 0x04  */

+ __IO uint32_t CRRCR;          /*!< Clock Recovery RC  Register,                                             Address offset: 0x08  */

+ __IO uint32_t CSICFGR;        /*!< CSI Clock Calibration Register,                                          Address offset: 0x0C  */

+ __IO uint32_t CFGR;           /*!< RCC clock configuration register,                                        Address offset: 0x10  */

+ uint32_t     RESERVED1;       /*!< Reserved,                                                                Address offset: 0x14  */

+ __IO uint32_t CDCFGR1;         /*!< RCC Domain 1 configuration register,                                    Address offset: 0x18  */

+ __IO uint32_t CDCFGR2;         /*!< RCC Domain 2 configuration register,                                    Address offset: 0x1C  */

+ __IO uint32_t SRDCFGR;         /*!< RCC Domain 3 configuration register,                                    Address offset: 0x20  */

+ uint32_t     RESERVED2;       /*!< Reserved,                                                                Address offset: 0x24  */

+ __IO uint32_t PLLCKSELR;      /*!< RCC PLLs Clock Source Selection Register,                                Address offset: 0x28  */

+ __IO uint32_t PLLCFGR;        /*!< RCC PLLs  Configuration Register,                                        Address offset: 0x2C  */

+ __IO uint32_t PLL1DIVR;       /*!< RCC PLL1 Dividers Configuration Register,                                Address offset: 0x30  */

+ __IO uint32_t PLL1FRACR;      /*!< RCC PLL1 Fractional Divider Configuration Register,                      Address offset: 0x34  */

+ __IO uint32_t PLL2DIVR;       /*!< RCC PLL2 Dividers Configuration Register,                                Address offset: 0x38  */

+ __IO uint32_t PLL2FRACR;      /*!< RCC PLL2 Fractional Divider Configuration Register,                      Address offset: 0x3C  */

+ __IO uint32_t PLL3DIVR;       /*!< RCC PLL3 Dividers Configuration Register,                                Address offset: 0x40  */

+ __IO uint32_t PLL3FRACR;      /*!< RCC PLL3 Fractional Divider Configuration Register,                      Address offset: 0x44  */

+ uint32_t      RESERVED3;      /*!< Reserved,                                                                Address offset: 0x48  */

+ __IO uint32_t  CDCCIPR;       /*!< RCC Domain 1 Kernel Clock Configuration Register                         Address offset: 0x4C  */

+ __IO uint32_t  CDCCIP1R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x50  */

+ __IO uint32_t  CDCCIP2R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x54  */

+ __IO uint32_t  SRDCCIPR;       /*!< RCC Domain 3 Kernel Clock Configuration Register                         Address offset: 0x58  */

+ uint32_t      RESERVED4;      /*!< Reserved,                                                                Address offset: 0x5C  */

+ __IO uint32_t  CIER;          /*!< RCC Clock Source Interrupt Enable Register                               Address offset: 0x60  */

+ __IO uint32_t  CIFR;          /*!< RCC Clock Source Interrupt Flag Register                                 Address offset: 0x64  */

+ __IO uint32_t  CICR;          /*!< RCC Clock Source Interrupt Clear Register                                Address offset: 0x68  */

+ uint32_t     RESERVED5;       /*!< Reserved,                                                                Address offset: 0x6C  */

+ __IO uint32_t  BDCR;          /*!< RCC Vswitch Backup Domain Control Register,                              Address offset: 0x70  */

+ __IO uint32_t  CSR;           /*!< RCC clock control & status register,                                     Address offset: 0x74  */

+ uint32_t     RESERVED6;       /*!< Reserved,                                                                Address offset: 0x78  */

+ __IO uint32_t AHB3RSTR;       /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x7C  */

+ __IO uint32_t AHB1RSTR;       /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x80  */

+ __IO uint32_t AHB2RSTR;       /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x84  */

+ __IO uint32_t AHB4RSTR;       /*!< RCC AHB4 peripheral reset register,                                      Address offset: 0x88  */

+ __IO uint32_t APB3RSTR;       /*!< RCC APB3 peripheral reset register,                                      Address offset: 0x8C  */

+ __IO uint32_t APB1LRSTR;      /*!< RCC APB1 peripheral reset Low Word register,                             Address offset: 0x90  */

+ __IO uint32_t APB1HRSTR;      /*!< RCC APB1 peripheral reset High Word register,                            Address offset: 0x94  */

+ __IO uint32_t APB2RSTR;       /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x98  */

+ __IO uint32_t APB4RSTR;       /*!< RCC APB4 peripheral reset register,                                      Address offset: 0x9C  */

+ uint32_t     RESERVED7;       /*!< Reserved,                                                                Address offset: 0xA0  */

+ uint32_t     RESERVED8;       /*!< Reserved,                                                                Address offset: 0xA4  */

+ __IO uint32_t SRDAMR;         /*!< RCC Domain 3 Autonomous Mode Register,                                   Address offset: 0xA8  */

+  uint32_t     RESERVED9;      /*!< Reserved, 0xAC-0xAF                                                      Address offset: 0xAC  */

+ __IO uint32_t CKGAENR;        /*!< AXI Clocks Gating Enable Register,                                       Address offset: 0xB0  */

+  uint32_t     RESERVED10[31];   /*!< Reserved, 0xAC-0xAF                                                    Address offset: 0xAC  */

+ __IO uint32_t RSR;            /*!< RCC Reset status register,                                               Address offset: 0xD0  */

+ __IO uint32_t AHB3ENR;        /*!< RCC AHB3 peripheral clock  register,                                     Address offset: 0xD4  */

+ __IO uint32_t AHB1ENR;        /*!< RCC AHB1 peripheral clock  register,                                     Address offset: 0xD8  */

+ __IO uint32_t AHB2ENR;        /*!< RCC AHB2 peripheral clock  register,                                     Address offset: 0xDC  */

+ __IO uint32_t AHB4ENR;        /*!< RCC AHB4 peripheral clock  register,                                     Address offset: 0xE0  */

+ __IO uint32_t APB3ENR;        /*!< RCC APB3 peripheral clock  register,                                     Address offset: 0xE4  */

+ __IO uint32_t APB1LENR;       /*!< RCC APB1 peripheral clock  Low Word register,                            Address offset: 0xE8  */

+ __IO uint32_t APB1HENR;       /*!< RCC APB1 peripheral clock  High Word register,                           Address offset: 0xEC  */

+ __IO uint32_t APB2ENR;        /*!< RCC APB2 peripheral clock  register,                                     Address offset: 0xF0  */

+ __IO uint32_t APB4ENR;        /*!< RCC APB4 peripheral clock  register,                                     Address offset: 0xF4  */

+ uint32_t      RESERVED12;      /*!< Reserved,                                                                Address offset: 0xF8  */

+ __IO uint32_t AHB3LPENR;      /*!< RCC AHB3 peripheral sleep clock  register,                               Address offset: 0xFC  */

+ __IO uint32_t AHB1LPENR;      /*!< RCC AHB1 peripheral sleep clock  register,                               Address offset: 0x100 */

+ __IO uint32_t AHB2LPENR;      /*!< RCC AHB2 peripheral sleep clock  register,                               Address offset: 0x104 */

+ __IO uint32_t AHB4LPENR;      /*!< RCC AHB4 peripheral sleep clock  register,                               Address offset: 0x108 */

+ __IO uint32_t APB3LPENR;      /*!< RCC APB3 peripheral sleep clock  register,                               Address offset: 0x10C */

+ __IO uint32_t APB1LLPENR;     /*!< RCC APB1 peripheral sleep clock  Low Word register,                      Address offset: 0x110 */

+ __IO uint32_t APB1HLPENR;     /*!< RCC APB1 peripheral sleep clock  High Word register,                     Address offset: 0x114 */

+ __IO uint32_t APB2LPENR;      /*!< RCC APB2 peripheral sleep clock  register,                               Address offset: 0x118 */

+ __IO uint32_t APB4LPENR;      /*!< RCC APB4 peripheral sleep clock  register,                               Address offset: 0x11C */

+ uint32_t     RESERVED13[4];   /*!< Reserved, 0x120-0x12C                                                    Address offset: 0x120 */

+

+} RCC_TypeDef;

+

+

+/**

+  * @brief Real-Time Clock

+  */

+typedef struct

+{

+  __IO uint32_t TR;             /*!< RTC time register,                              Address offset: 0x00 */

+  __IO uint32_t DR;             /*!< RTC date register,                              Address offset: 0x04 */

+  __IO uint32_t SSR;            /*!< RTC sub second register,                        Address offset: 0x08 */

+  __IO uint32_t ICSR;           /*!< RTC initialization control and status register, Address offset: 0x0C */

+  __IO uint32_t PRER;           /*!< RTC prescaler register,                         Address offset: 0x10 */

+  __IO uint32_t WUTR;           /*!< RTC wakeup timer register,                      Address offset: 0x14 */

+  __IO uint32_t CR;             /*!< RTC control register,                           Address offset: 0x18 */

+       uint32_t RESERVED0;      /*!< Reserved,                                       Address offset: 0x1C */

+       uint32_t RESERVED1;      /*!< Reserved,                                       Address offset: 0x20 */

+  __IO uint32_t WPR;            /*!< RTC write protection register,                  Address offset: 0x24 */

+  __IO uint32_t CALR;           /*!< RTC calibration register,                       Address offset: 0x28 */

+  __IO uint32_t SHIFTR;         /*!< RTC shift control register,                     Address offset: 0x2C */

+  __IO uint32_t TSTR;           /*!< RTC time stamp time register,                   Address offset: 0x30 */

+  __IO uint32_t TSDR;           /*!< RTC time stamp date register,                   Address offset: 0x34 */

+  __IO uint32_t TSSSR;          /*!< RTC time-stamp sub second register,             Address offset: 0x38 */

+       uint32_t RESERVED2;      /*!< Reserved,                                       Address offset: 0x3C */

+  __IO uint32_t ALRMAR;         /*!< RTC alarm A register,                           Address offset: 0x40 */

+  __IO uint32_t ALRMASSR;       /*!< RTC alarm A sub second register,                Address offset: 0x44 */

+  __IO uint32_t ALRMBR;         /*!< RTC alarm B register,                           Address offset: 0x48 */

+  __IO uint32_t ALRMBSSR;       /*!< RTC alarm B sub second register,                Address offset: 0x4C */

+  __IO uint32_t SR;             /*!< RTC Status register,                            Address offset: 0x50 */

+  __IO uint32_t MISR;           /*!< RTC masked interrupt status register,           Address offset: 0x54 */

+       uint32_t RESERVED3;      /*!< Reserved,                                       Address offset: 0x58 */

+  __IO uint32_t SCR;            /*!< RTC status Clear register,                      Address offset: 0x5C */

+  __IO uint32_t CFGR;           /*!< RTC configuration register,                     Address offset: 0x60 */

+} RTC_TypeDef;

+

+/**

+  * @brief Tamper and backup registers

+  */

+typedef struct

+{

+  __IO uint32_t CR1;            /*!< TAMP configuration register 1,            Address offset: 0x00 */

+  __IO uint32_t CR2;            /*!< TAMP configuration register 2,            Address offset: 0x04 */

+       uint32_t RESERVED0;      /*!< Reserved,                                 Address offset: 0x08 */

+  __IO uint32_t FLTCR;          /*!< TAMP filter control register,             Address offset: 0x0C */

+  __IO uint32_t ATCR1;          /*!< TAMP active tamper control register,      Address offset: 0x10 */

+  __IO uint32_t ATSEEDR;        /*!< TAMP active tamper seed register,         Address offset: 0x14 */

+  __IO uint32_t ATOR;           /*!< TAMP active tamper output register,       Address offset: 0x18 */

+       uint32_t RESERVED1[4];   /*!< Reserved,                                 Address offset: 0x1C -- 0x28 */

+  __IO uint32_t IER;            /*!< TAMP interrupt enable register,           Address offset: 0x2C */

+  __IO uint32_t SR;             /*!< TAMP status register,                     Address offset: 0x30 */

+  __IO uint32_t MISR;           /*!< TAMP masked interrupt status register,    Address offset: 0x34 */

+       uint32_t RESERVED2;      /*!< Reserved,                                 Address offset: 0x38 */

+  __IO uint32_t SCR;            /*!< TAMP status clear register,               Address offset: 0x3C */

+  __IO uint32_t COUNTR;         /*!< TAMP monotonic counter register,          Address offset: 0x40 */

+       uint32_t RESERVED3[3];   /*!< Reserved,                                 Address offset: 0x44 -- 0x4C */

+  __IO uint32_t CFGR;           /*!< TAMP configuration register,              Address offset: 0x50 */

+       uint32_t RESERVED4[43];  /*!< Reserved,                                 Address offset: 0x54 -- 0xFC */

+  __IO uint32_t BKP0R;          /*!< TAMP backup register 0,                   Address offset: 0x100 */

+  __IO uint32_t BKP1R;          /*!< TAMP backup register 1,                   Address offset: 0x104 */

+  __IO uint32_t BKP2R;          /*!< TAMP backup register 2,                   Address offset: 0x108 */

+  __IO uint32_t BKP3R;          /*!< TAMP backup register 3,                   Address offset: 0x10C */

+  __IO uint32_t BKP4R;          /*!< TAMP backup register 4,                   Address offset: 0x110 */

+  __IO uint32_t BKP5R;          /*!< TAMP backup register 5,                   Address offset: 0x114 */

+  __IO uint32_t BKP6R;          /*!< TAMP backup register 6,                   Address offset: 0x118 */

+  __IO uint32_t BKP7R;          /*!< TAMP backup register 7,                   Address offset: 0x11C */

+  __IO uint32_t BKP8R;          /*!< TAMP backup register 8,                   Address offset: 0x120 */

+  __IO uint32_t BKP9R;          /*!< TAMP backup register 9,                   Address offset: 0x124 */

+  __IO uint32_t BKP10R;         /*!< TAMP backup register 10,                  Address offset: 0x128 */

+  __IO uint32_t BKP11R;         /*!< TAMP backup register 11,                  Address offset: 0x12C */

+  __IO uint32_t BKP12R;         /*!< TAMP backup register 12,                  Address offset: 0x130 */

+  __IO uint32_t BKP13R;         /*!< TAMP backup register 13,                  Address offset: 0x134 */

+  __IO uint32_t BKP14R;         /*!< TAMP backup register 14,                  Address offset: 0x138 */

+  __IO uint32_t BKP15R;         /*!< TAMP backup register 15,                  Address offset: 0x13C */

+  __IO uint32_t BKP16R;         /*!< TAMP backup register 16,                  Address offset: 0x140 */

+  __IO uint32_t BKP17R;         /*!< TAMP backup register 17,                  Address offset: 0x144 */

+  __IO uint32_t BKP18R;         /*!< TAMP backup register 18,                  Address offset: 0x148 */

+  __IO uint32_t BKP19R;         /*!< TAMP backup register 19,                  Address offset: 0x14C */

+  __IO uint32_t BKP20R;         /*!< TAMP backup register 20,                  Address offset: 0x150 */

+  __IO uint32_t BKP21R;         /*!< TAMP backup register 21,                  Address offset: 0x154 */

+  __IO uint32_t BKP22R;         /*!< TAMP backup register 22,                  Address offset: 0x158 */

+  __IO uint32_t BKP23R;         /*!< TAMP backup register 23,                  Address offset: 0x15C */

+  __IO uint32_t BKP24R;         /*!< TAMP backup register 24,                  Address offset: 0x160 */

+  __IO uint32_t BKP25R;         /*!< TAMP backup register 25,                  Address offset: 0x164 */

+  __IO uint32_t BKP26R;         /*!< TAMP backup register 26,                  Address offset: 0x168 */

+  __IO uint32_t BKP27R;         /*!< TAMP backup register 27,                  Address offset: 0x16C */

+  __IO uint32_t BKP28R;         /*!< TAMP backup register 28,                  Address offset: 0x170 */

+  __IO uint32_t BKP29R;         /*!< TAMP backup register 29,                  Address offset: 0x174 */

+  __IO uint32_t BKP30R;         /*!< TAMP backup register 30,                  Address offset: 0x178 */

+  __IO uint32_t BKP31R;         /*!< TAMP backup register 31,                  Address offset: 0x17C */

+} TAMP_TypeDef;

+

+/**

+  * @brief Serial Audio Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t GCR;           /*!< SAI global configuration register, Address offset: 0x00 */

+  uint32_t      RESERVED0[16]; /*!< Reserved, 0x04 - 0x43                                   */

+  __IO uint32_t PDMCR;         /*!< SAI PDM control register,          Address offset: 0x44 */

+  __IO uint32_t PDMDLY;        /*!< SAI PDM delay register,            Address offset: 0x48 */

+} SAI_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */

+  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */

+  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */

+  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */

+  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */

+  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */

+  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */

+  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */

+} SAI_Block_TypeDef;

+

+/**

+  * @brief SPDIF-RX Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */

+  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */

+  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */

+  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */

+  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */

+  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */

+  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */

+  uint32_t        RESERVED2;    /*!< Reserved,  0x1A                                          */

+} SPDIFRX_TypeDef;

+

+

+/**

+  * @brief Secure digital input/output Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t POWER;          /*!< SDMMC power control register,             Address offset: 0x00  */

+  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,             Address offset: 0x04  */

+  __IO uint32_t ARG;            /*!< SDMMC argument register,                  Address offset: 0x08  */

+  __IO uint32_t CMD;            /*!< SDMMC command register,                   Address offset: 0x0C  */

+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register,          Address offset: 0x10  */

+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                Address offset: 0x14  */

+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                Address offset: 0x18  */

+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                Address offset: 0x1C  */

+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                Address offset: 0x20  */

+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                Address offset: 0x24  */

+  __IO uint32_t DLEN;           /*!< SDMMC data length register,               Address offset: 0x28  */

+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,              Address offset: 0x2C  */

+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,              Address offset: 0x30  */

+  __I uint32_t  STA;            /*!< SDMMC status register,                    Address offset: 0x34  */

+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,           Address offset: 0x38  */

+  __IO uint32_t MASK;           /*!< SDMMC mask register,                      Address offset: 0x3C  */

+  __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,     Address offset: 0x40  */

+  uint32_t      RESERVED0[3];   /*!< Reserved, 0x44 - 0x4C - 0x4C                                    */

+  __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,               Address offset: 0x50  */

+  __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,           Address offset: 0x54  */

+  __IO uint32_t IDMABASE0;      /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58  */

+  __IO uint32_t IDMABASE1;      /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C  */

+  uint32_t      RESERVED1[8];   /*!< Reserved, 0x60-0x7C                                             */

+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,                 Address offset: 0x80  */

+  uint32_t      RESERVED2[222]; /*!< Reserved, 0x84-0x3F8                                            */

+  __IO uint32_t IPVR;           /*!< SDMMC data FIFO register,                 Address offset: 0x3FC */

+} SDMMC_TypeDef;

+

+

+/**

+  * @brief Delay Block DLYB

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;          /*!< DELAY BLOCK control register,  Address offset: 0x00 */

+  __IO uint32_t CFGR;        /*!< DELAY BLOCK configuration register,  Address offset: 0x04 */

+} DLYB_TypeDef;

+

+/**

+  * @brief HW Semaphore HSEM

+  */

+

+typedef struct

+{

+  __IO uint32_t R[32];      /*!< 2-step write lock and read back registers,     Address offset: 00h-7Ch  */

+  __IO uint32_t RLR[32];    /*!< 1-step read lock registers,                    Address offset: 80h-FCh  */

+  __IO uint32_t C1IER;      /*!< HSEM Interrupt enable register ,             Address offset: 100h     */

+  __IO uint32_t C1ICR;      /*!< HSEM Interrupt clear register ,              Address offset: 104h     */

+  __IO uint32_t C1ISR;      /*!< HSEM Interrupt Status register ,             Address offset: 108h     */

+  __IO uint32_t C1MISR;     /*!< HSEM Interrupt Masked Status register ,      Address offset: 10Ch     */

+  uint32_t  Reserved[12];   /* Reserved                                       Address offset: 110h-13Ch  */

+  __IO uint32_t CR;         /*!< HSEM Semaphore clear register ,                Address offset: 140h      */

+  __IO uint32_t KEYR;       /*!< HSEM Semaphore clear key register ,            Address offset: 144h      */

+

+} HSEM_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t IER;        /*!< HSEM interrupt enable register ,                Address offset:   0h     */

+  __IO uint32_t ICR;        /*!< HSEM interrupt clear register ,                 Address offset:   4h     */

+  __IO uint32_t ISR;        /*!< HSEM interrupt status register ,                Address offset:   8h     */

+  __IO uint32_t MISR;       /*!< HSEM masked interrupt status register ,         Address offset:   Ch     */

+} HSEM_Common_TypeDef;

+

+/**

+  * @brief Serial Peripheral Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */

+  __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */

+  __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */

+  __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */

+  __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */

+  __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */

+  __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */

+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */

+  __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */

+  uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */

+  __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */

+  uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */

+  __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */

+  __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */

+  __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */

+  __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */

+  __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */

+

+} SPI_TypeDef;

+

+/**

+  * @brief DTS

+  */

+typedef struct

+{

+  __IO uint32_t CFGR1;         /*!< DTS configuration register,                Address offset: 0x00 */

+  uint32_t RESERVED0;          /*!< Reserved,                                  Address offset: 0x04 */

+  __IO uint32_t T0VALR1;       /*!< DTS T0 Value register,                     Address offset: 0x08 */

+  uint32_t RESERVED1;          /*!< Reserved,                                  Address offset: 0x0C */

+  __IO uint32_t RAMPVALR;      /*!< DTS Ramp value register,                   Address offset: 0x10 */

+  __IO uint32_t ITR1;          /*!< DTS Interrupt threshold register,          Address offset: 0x14 */

+  uint32_t RESERVED2;          /*!< Reserved,                                  Address offset: 0x18 */

+  __IO uint32_t DR;            /*!< DTS data register,                         Address offset: 0x1C */

+  __IO uint32_t SR;            /*!< DTS status register                        Address offset: 0x20 */

+  __IO uint32_t ITENR;         /*!< DTS Interrupt enable register,             Address offset: 0x24 */

+  __IO uint32_t ICIFR;         /*!< DTS Clear Interrupt flag register,         Address offset: 0x28 */

+  __IO uint32_t OR;            /*!< DTS option register 1,                     Address offset: 0x2C */

+}

+DTS_TypeDef;

+

+/**

+  * @brief TIM

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */

+  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */

+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */

+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */

+  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */

+  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */

+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */

+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */

+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */

+  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */

+  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */

+  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */

+  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */

+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */

+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */

+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */

+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */

+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */

+  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */

+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */

+  uint32_t      RESERVED1;   /*!< Reserved, 0x50                                                 */

+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */

+  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */

+  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */

+  __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */

+  __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */

+  __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x68 */

+} TIM_TypeDef;

+

+/**

+  * @brief LPTIMIMER

+  */

+typedef struct

+{

+  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,         Address offset: 0x00 */

+  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,              Address offset: 0x04 */

+  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,             Address offset: 0x08 */

+  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                Address offset: 0x0C */

+  __IO uint32_t CR;       /*!< LPTIM Control register,                      Address offset: 0x10 */

+  __IO uint32_t CMP;      /*!< LPTIM Compare register,                      Address offset: 0x14 */

+  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                   Address offset: 0x18 */

+  __IO uint32_t CNT;      /*!< LPTIM Counter register,                      Address offset: 0x1C */

+  uint32_t  RESERVED1;    /*!< Reserved, 0x20                                                    */

+  __IO uint32_t CFGR2;    /*!< LPTIM Configuration register,                Address offset: 0x24 */

+} LPTIM_TypeDef;

+

+/**

+  * @brief Comparator

+  */

+typedef struct

+{

+  __IO uint32_t SR;        /*!< Comparator status register,                    Address offset: 0x00 */

+  __IO uint32_t ICFR;      /*!< Comparator interrupt clear flag register,       Address offset: 0x04 */

+  __IO uint32_t OR;        /*!< Comparator option register,                  Address offset: 0x08 */

+} COMPOPT_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CFGR;      /*!< Comparator configuration register  ,           Address offset: 0x00 */

+} COMP_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CFGR;       /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */

+} COMP_Common_TypeDef;

+/**

+  * @brief Universal Synchronous Asynchronous Receiver Transmitter

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */

+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */

+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */

+  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */

+  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */

+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */

+  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */

+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */

+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */

+  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */

+  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */

+  __IO uint32_t PRESC;  /*!< USART clock Prescaler register,           Address offset: 0x2C */

+} USART_TypeDef;

+

+/**

+  * @brief Single Wire Protocol Master Interface SPWMI

+  */

+typedef struct

+{

+  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */

+  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */

+    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */

+  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */

+  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */

+  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */

+  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */

+  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */

+  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */

+  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */

+} SWPMI_TypeDef;

+

+/**

+  * @brief Window WATCHDOG

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */

+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */

+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */

+} WWDG_TypeDef;

+

+

+/**

+  * @brief RAM_ECC_Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t CR;           /*!< RAMECC monitor configuration register          */

+  __IO uint32_t SR;           /*!< RAMECC monitor status register                 */

+  __IO uint32_t FAR;          /*!< RAMECC monitor failing address register        */

+  __IO uint32_t FDRL;         /*!< RAMECC monitor failing data low register       */

+  __IO uint32_t FDRH;         /*!< RAMECC monitor failing data high register      */

+  __IO uint32_t FECR;         /*!< RAMECC monitor failing ECC error code register */

+} RAMECC_MonitorTypeDef;

+

+typedef struct

+{

+  __IO uint32_t IER;          /*!< RAMECC interrupt enable register */

+} RAMECC_TypeDef;

+/**

+  * @}

+  */

+

+

+/**

+  * @brief Crypto Processor

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */

+  __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */

+  __IO uint32_t DIN;         /*!< CRYP data input register,                                Address offset: 0x08 */

+  __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */

+  __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */

+  __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */

+  __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */

+  __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */

+  __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */

+  __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */

+  __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */

+  __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */

+  __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */

+  __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */

+  __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */

+  __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */

+  __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */

+  __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */

+  __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */

+  __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */

+  __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */

+  __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */

+  __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */

+  __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */

+  __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */

+  __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */

+  __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */

+  __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */

+  __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */

+  __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */

+  __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */

+  __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */

+  __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */

+  __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */

+  __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */

+  __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */

+} CRYP_TypeDef;

+

+/**

+  * @brief HASH

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */

+  __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */

+  __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */

+  __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */

+  __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */

+  __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */

+       uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */

+  __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */

+} HASH_TypeDef;

+

+/**

+  * @brief HASH_DIGEST

+  */

+

+typedef struct

+{

+  __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */

+} HASH_DIGEST_TypeDef;

+

+

+/**

+  * @brief RNG

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */

+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */

+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */

+  uint32_t RESERVED;

+  __IO uint32_t HTCR;  /*!< RNG health test configuration register, Address offset: 0x10 */

+} RNG_TypeDef;

+

+/**

+  * @brief MDIOS

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;

+  __IO uint32_t WRFR;

+  __IO uint32_t CWRFR;

+  __IO uint32_t RDFR;

+  __IO uint32_t CRDFR;

+  __IO uint32_t SR;

+  __IO uint32_t CLRFR;

+  uint32_t RESERVED[57];

+  __IO uint32_t DINR0;

+  __IO uint32_t DINR1;

+  __IO uint32_t DINR2;

+  __IO uint32_t DINR3;

+  __IO uint32_t DINR4;

+  __IO uint32_t DINR5;

+  __IO uint32_t DINR6;

+  __IO uint32_t DINR7;

+  __IO uint32_t DINR8;

+  __IO uint32_t DINR9;

+  __IO uint32_t DINR10;

+  __IO uint32_t DINR11;

+  __IO uint32_t DINR12;

+  __IO uint32_t DINR13;

+  __IO uint32_t DINR14;

+  __IO uint32_t DINR15;

+  __IO uint32_t DINR16;

+  __IO uint32_t DINR17;

+  __IO uint32_t DINR18;

+  __IO uint32_t DINR19;

+  __IO uint32_t DINR20;

+  __IO uint32_t DINR21;

+  __IO uint32_t DINR22;

+  __IO uint32_t DINR23;

+  __IO uint32_t DINR24;

+  __IO uint32_t DINR25;

+  __IO uint32_t DINR26;

+  __IO uint32_t DINR27;

+  __IO uint32_t DINR28;

+  __IO uint32_t DINR29;

+  __IO uint32_t DINR30;

+  __IO uint32_t DINR31;

+  __IO uint32_t DOUTR0;

+  __IO uint32_t DOUTR1;

+  __IO uint32_t DOUTR2;

+  __IO uint32_t DOUTR3;

+  __IO uint32_t DOUTR4;

+  __IO uint32_t DOUTR5;

+  __IO uint32_t DOUTR6;

+  __IO uint32_t DOUTR7;

+  __IO uint32_t DOUTR8;

+  __IO uint32_t DOUTR9;

+  __IO uint32_t DOUTR10;

+  __IO uint32_t DOUTR11;

+  __IO uint32_t DOUTR12;

+  __IO uint32_t DOUTR13;

+  __IO uint32_t DOUTR14;

+  __IO uint32_t DOUTR15;

+  __IO uint32_t DOUTR16;

+  __IO uint32_t DOUTR17;

+  __IO uint32_t DOUTR18;

+  __IO uint32_t DOUTR19;

+  __IO uint32_t DOUTR20;

+  __IO uint32_t DOUTR21;

+  __IO uint32_t DOUTR22;

+  __IO uint32_t DOUTR23;

+  __IO uint32_t DOUTR24;

+  __IO uint32_t DOUTR25;

+  __IO uint32_t DOUTR26;

+  __IO uint32_t DOUTR27;

+  __IO uint32_t DOUTR28;

+  __IO uint32_t DOUTR29;

+  __IO uint32_t DOUTR30;

+  __IO uint32_t DOUTR31;

+} MDIOS_TypeDef;

+

+

+/**

+  * @brief USB_OTG_Core_Registers

+  */

+typedef struct

+{

+ __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */

+  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */

+  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */

+  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */

+  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */

+  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */

+  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */

+  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */

+  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */

+  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */

+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */

+  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */

+  uint32_t Reserved30[2];             /*!< Reserved                                     030h */

+  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */

+  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */

+  __IO uint32_t GSNPSID;              /* USB_OTG core ID                                040h*/

+  __IO uint32_t GHWCFG1;              /* User HW config1                                044h*/

+  __IO uint32_t GHWCFG2;              /* User HW config2                                048h*/

+  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */

+  uint32_t  Reserved6;                /*!< Reserved                                     050h */

+  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */

+  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */

+  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */

+   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */

+    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */

+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */

+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */

+} USB_OTG_GlobalTypeDef;

+

+

+/**

+  * @brief USB_OTG_device_Registers

+  */

+typedef struct

+{

+  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */

+  __IO uint32_t DCTL;            /*!< dev Control Register         804h */

+  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */

+  uint32_t Reserved0C;           /*!< Reserved                     80Ch */

+  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */

+  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */

+  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */

+  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */

+  uint32_t  Reserved20;          /*!< Reserved                     820h */

+  uint32_t Reserved9;            /*!< Reserved                     824h */

+  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */

+  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */

+  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */

+  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */

+  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */

+  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */

+  uint32_t Reserved40;           /*!< dedicated EP mask            840h */

+  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */

+  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */

+  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */

+} USB_OTG_DeviceTypeDef;

+

+

+/**

+  * @brief USB_OTG_IN_Endpoint-Specific_Register

+  */

+typedef struct

+{

+  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */

+  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */

+  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */

+  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */

+  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */

+  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */

+  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */

+  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */

+} USB_OTG_INEndpointTypeDef;

+

+

+/**

+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */

+  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */

+  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */

+  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */

+  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */

+  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */

+  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */

+} USB_OTG_OUTEndpointTypeDef;

+

+

+/**

+  * @brief USB_OTG_Host_Mode_Register_Structures

+  */

+typedef struct

+{

+  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */

+  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */

+  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */

+  uint32_t Reserved40C;           /*!< Reserved                             40Ch */

+  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */

+  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */

+  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */

+} USB_OTG_HostTypeDef;

+

+/**

+  * @brief USB_OTG_Host_Channel_Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */

+  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */

+  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */

+  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */

+  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */

+  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */

+  uint32_t Reserved[2];           /*!< Reserved                                      */

+} USB_OTG_HostChannelTypeDef;

+/**

+  * @}

+  */

+

+/**

+  * @brief OCTO Serial Peripheral Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;          /*!< OCTOSPI Control register,                           Address offset: 0x000 */

+  uint32_t RESERVED;         /*!< Reserved,                                           Address offset: 0x004 */

+  __IO uint32_t DCR1;        /*!< OCTOSPI Device Configuration register 1,            Address offset: 0x008 */

+  __IO uint32_t DCR2;        /*!< OCTOSPI Device Configuration register 2,            Address offset: 0x00C */

+  __IO uint32_t DCR3;        /*!< OCTOSPI Device Configuration register 3,            Address offset: 0x010 */

+  __IO uint32_t DCR4;        /*!< OCTOSPI Device Configuration register 4,            Address offset: 0x014 */

+  uint32_t RESERVED1[2];     /*!< Reserved,                                           Address offset: 0x018-0x01C */

+  __IO uint32_t SR;          /*!< OCTOSPI Status register,                            Address offset: 0x020 */

+  __IO uint32_t FCR;         /*!< OCTOSPI Flag Clear register,                        Address offset: 0x024 */

+  uint32_t RESERVED2[6];     /*!< Reserved,                                           Address offset: 0x028-0x03C */

+  __IO uint32_t DLR;         /*!< OCTOSPI Data Length register,                       Address offset: 0x040 */

+  uint32_t RESERVED3;        /*!< Reserved,                                           Address offset: 0x044 */

+  __IO uint32_t AR;          /*!< OCTOSPI Address register,                           Address offset: 0x048 */

+  uint32_t RESERVED4;        /*!< Reserved,                                           Address offset: 0x04C */

+  __IO uint32_t DR;          /*!< OCTOSPI Data register,                              Address offset: 0x050 */

+  uint32_t RESERVED5[11];    /*!< Reserved,                                           Address offset: 0x054-0x07C */

+  __IO uint32_t PSMKR;       /*!< OCTOSPI Polling Status Mask register,               Address offset: 0x080 */

+  uint32_t RESERVED6;        /*!< Reserved,                                           Address offset: 0x084 */

+  __IO uint32_t PSMAR;       /*!< OCTOSPI Polling Status Match register,              Address offset: 0x088 */

+  uint32_t RESERVED7;        /*!< Reserved,                                           Address offset: 0x08C */

+  __IO uint32_t PIR;         /*!< OCTOSPI Polling Interval register,                  Address offset: 0x090 */

+  uint32_t RESERVED8[27];    /*!< Reserved,                                           Address offset: 0x094-0x0FC */

+  __IO uint32_t CCR;         /*!< OCTOSPI Communication Configuration register,       Address offset: 0x100 */

+  uint32_t RESERVED9;        /*!< Reserved,                                           Address offset: 0x104 */

+  __IO uint32_t TCR;         /*!< OCTOSPI Timing Configuration register,              Address offset: 0x108 */

+  uint32_t RESERVED10;       /*!< Reserved,                                           Address offset: 0x10C */

+  __IO uint32_t IR;          /*!< OCTOSPI Instruction register,                       Address offset: 0x110 */

+  uint32_t RESERVED11[3];    /*!< Reserved,                                           Address offset: 0x114-0x11C */

+  __IO uint32_t ABR;         /*!< OCTOSPI Alternate Bytes register,                   Address offset: 0x120 */

+  uint32_t RESERVED12[3];    /*!< Reserved,                                           Address offset: 0x124-0x12C */

+  __IO uint32_t LPTR;        /*!< OCTOSPI Low Power Timeout register,                 Address offset: 0x130 */

+  uint32_t RESERVED13[3];    /*!< Reserved,                                           Address offset: 0x134-0x13C */

+  __IO uint32_t WPCCR;       /*!< OCTOSPI Wrap Communication Configuration register,  Address offset: 0x140 */

+  uint32_t RESERVED14;       /*!< Reserved,                                           Address offset: 0x144 */

+  __IO uint32_t WPTCR;       /*!< OCTOSPI Wrap Timing Configuration register,         Address offset: 0x148 */

+  uint32_t RESERVED15;       /*!< Reserved,                                           Address offset: 0x14C */

+  __IO uint32_t WPIR;        /*!< OCTOSPI Wrap Instruction register,                  Address offset: 0x150 */

+  uint32_t RESERVED16[3];    /*!< Reserved,                                           Address offset: 0x154-0x15C */

+  __IO uint32_t WPABR;       /*!< OCTOSPI Wrap Alternate Bytes register,              Address offset: 0x160 */

+  uint32_t RESERVED17[7];    /*!< Reserved,                                           Address offset: 0x164-0x17C */

+  __IO uint32_t WCCR;        /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */

+  uint32_t RESERVED18;       /*!< Reserved,                                           Address offset: 0x184 */

+  __IO uint32_t WTCR;        /*!< OCTOSPI Write Timing Configuration register,        Address offset: 0x188 */

+  uint32_t RESERVED19;       /*!< Reserved,                                           Address offset: 0x18C */

+  __IO uint32_t WIR;         /*!< OCTOSPI Write Instruction register,                 Address offset: 0x190 */

+  uint32_t RESERVED20[3];    /*!< Reserved,                                           Address offset: 0x194-0x19C */

+  __IO uint32_t WABR;        /*!< OCTOSPI Write Alternate Bytes register,             Address offset: 0x1A0 */

+  uint32_t RESERVED21[23];   /*!< Reserved,                                           Address offset: 0x1A4-0x1FC */

+  __IO uint32_t HLCR;        /*!< OCTOSPI Hyperbus Latency Configuration register,    Address offset: 0x200 */

+  uint32_t RESERVED22[122];  /*!< Reserved,                                           Address offset: 0x204-0x3EC */

+  __IO uint32_t HWCFGR;      /*!< OCTOSPI HW Configuration register,                  Address offset: 0x3F0 */

+  __IO uint32_t VER;         /*!< OCTOSPI Version register,                           Address offset: 0x3F4 */

+  __IO uint32_t ID;          /*!< OCTOSPI Identification register,                    Address offset: 0x3F8 */

+  __IO uint32_t MID;         /*!< OCTOPSI HW Magic ID register,                       Address offset: 0x3FC */

+} OCTOSPI_TypeDef;

+

+/**

+  * @}

+  */

+/**

+  * @brief OCTO Serial Peripheral Interface IO Manager

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;          /*!< OCTOSPI IO Manager Control register,                 Address offset: 0x00 */

+  __IO uint32_t PCR[3];      /*!< OCTOSPI IO Manager Port[1:3] Configuration register, Address offset: 0x04-0x20 */

+} OCTOSPIM_TypeDef;

+

+/**

+  * @}

+  */

+

+/**

+  * @brief OTFD register

+  */

+typedef struct

+{

+  __IO uint32_t REG_CONFIGR;

+  __IO uint32_t REG_START_ADDR;

+  __IO uint32_t REG_END_ADDR;

+  __IO uint32_t REG_NONCER0;

+  __IO uint32_t REG_NONCER1;

+  __IO uint32_t REG_KEYR0;

+  __IO uint32_t REG_KEYR1;

+  __IO uint32_t REG_KEYR2;

+  __IO uint32_t REG_KEYR3;

+} OTFDEC_Region_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CR;

+  uint32_t RESERVED1[191];

+  __IO uint32_t ISR;

+  __IO uint32_t ICR;

+  __IO uint32_t IER;

+  uint32_t RESERVED2[56];

+  __IO uint32_t HWCFGR2;

+  __IO uint32_t HWCFGR1;

+  __IO uint32_t VERR;

+  __IO uint32_t IPIDR;

+  __IO uint32_t SIDR;

+} OTFDEC_TypeDef;

+/**

+  * @}

+  */

+

+/** @addtogroup Peripheral_memory_map

+  * @{

+  */

+#define CD_ITCMRAM_BASE           (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM  */

+#define CD_DTCMRAM_BASE           (0x20000000UL) /*!< Base address of : 128KB (2x64KB) system data RAM accessible over DTCM                   */

+#define CD_AXIFLASH_BASE          (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI                */

+

+#define CD_AXISRAM1_BASE          (0x24000000UL) /*!< Base address of : (up to 256KB) system data RAM1 accessible over over AXI                */

+#define CD_AXISRAM2_BASE          (0x24040000UL) /*!< Base address of : (up to 384KB) system data RAM2 accessible over over AXI                */

+#define CD_AXISRAM3_BASE          (0x240A0000UL) /*!< Base address of : (up to 384KB) system data RAM3 accessible over over AXI                */

+#define CD_AHBSRAM1_BASE          (0x30000000UL) /*!< Base address of : (up to 64KB) system data RAM1 accessible over over AXI->AHB Bridge     */

+#define CD_AHBSRAM2_BASE          (0x30010000UL) /*!< Base address of : (up to 64KB) system data RAM2 accessible over over AXI->AHB Bridge     */

+

+#define SRD_BKPSRAM_BASE           (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge                                */

+#define SRD_SRAM_BASE              (0x38000000UL) /*!< Base address of : Backup SRAM(32 KB) over AXI->AHB Bridge                               */

+

+#define OCTOSPI1_BASE             (0x90000000UL) /*!< Base address of : OCTOSPI1 memories  accessible over AXI                                 */

+#define OCTOSPI2_BASE             (0x70000000UL) /*!< Base address of : OCTOSPI2 memories  accessible over AXI                                 */

+

+#define FLASH_BANK1_BASE          (0x08000000UL) /*!< Base address of : (up to 128 KB) Flash Bank1 accessible over AXI                         */

+#define FLASH_BANK2_BASE          (0x08100000UL) /*!< For legacy only , Flash bank 2 not available on STM32H7B0xx value line                   */

+#define FLASH_END                 (0x0801FFFFUL) /*!< FLASH end address                                                                        */

+

+/* Legacy define */

+#define FLASH_BASE                FLASH_BANK1_BASE

+#define D1_AXISRAM_BASE           CD_AXISRAM1_BASE

+

+#define FLASH_OTP_BASE            (0x08FFF000UL) /*!< Base address of : (up to 1KB) embedded FLASH Bank1 OTP Area                           */

+#define FLASH_OTP_END             (0x08FFF3FFUL) /*!< End address of : (up to 1KB) embedded FLASH Bank1 OTP Area                            */

+

+

+/*!< Device electronic signature memory map */

+#define UID_BASE                  (0x08FFF800UL)            /*!< Unique device ID register base address */

+#define FLASHSIZE_BASE            (0x08FFF80CUL)            /*!< FLASH Size register base address */

+#define PACKAGE_BASE              (0x08FFF80EUL)            /*!< Package Data register base address */

+

+#define PERIPH_BASE               (0x40000000UL) /*!< Base address of : AHB/ABP Peripherals                                                    */

+/*!< Peripheral memory map */

+#define CD_APB1PERIPH_BASE        PERIPH_BASE                   /*!<  D2_APB1PERIPH_BASE        PERIPH_BASE                                    */

+#define CD_APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)   /*!<  D2_APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)                    */

+#define CD_AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)   /*!<  D2_AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)                    */

+#define CD_AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)   /*!<  D2_AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)                    */

+

+#define CD_APB3PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)   /*!<  D1_APB1PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)                    */

+#define CD_AHB3PERIPH_BASE       (PERIPH_BASE + 0x12000000UL)   /*!<  D1_AHB1PERIPH_BASE       (PERIPH_BASE + 0x12000000UL)                    */

+

+#define SRD_APB4PERIPH_BASE      (PERIPH_BASE + 0x18000000UL)   /*!<  D3_APB1PERIPH_BASE       (PERIPH_BASE + 0x18000000UL)                    */

+#define SRD_AHB4PERIPH_BASE      (PERIPH_BASE + 0x18020000UL)   /*!<  D3_AHB1PERIPH_BASE       (PERIPH_BASE + 0x18020000UL)                    */

+

+/*!< Legacy Peripheral memory map */

+#define APB1PERIPH_BASE        PERIPH_BASE

+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)

+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)

+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)

+

+/*!< CD_AHB3PERIPH peripherals */

+#define MDMA_BASE             (CD_AHB3PERIPH_BASE + 0x0000UL)

+#define DMA2D_BASE            (CD_AHB3PERIPH_BASE + 0x1000UL)

+#define FLASH_R_BASE          (CD_AHB3PERIPH_BASE + 0x2000UL)

+#define JPGDEC_BASE           (CD_AHB3PERIPH_BASE + 0x3000UL)

+#define FMC_R_BASE            (CD_AHB3PERIPH_BASE + 0x4000UL)

+#define OCTOSPI1_R_BASE       (CD_AHB3PERIPH_BASE + 0x5000UL)

+#define DLYB_OCTOSPI1_BASE    (CD_AHB3PERIPH_BASE + 0x6000UL)

+#define SDMMC1_BASE           (CD_AHB3PERIPH_BASE + 0x7000UL)

+#define DLYB_SDMMC1_BASE      (CD_AHB3PERIPH_BASE + 0x8000UL)

+#define RAMECC_BASE           (CD_AHB3PERIPH_BASE + 0x9000UL)

+#define OCTOSPI2_R_BASE       (CD_AHB3PERIPH_BASE + 0xA000UL)

+#define DLYB_OCTOSPI2_BASE    (CD_AHB3PERIPH_BASE + 0xB000UL)

+#define OCTOSPIM_BASE         (CD_AHB3PERIPH_BASE + 0xB400UL)

+

+/*!< CD_AHB1PERIPH peripherals */

+

+#define DMA1_BASE               (CD_AHB1PERIPH_BASE + 0x0000UL)

+#define DMA2_BASE               (CD_AHB1PERIPH_BASE + 0x0400UL)

+#define DMAMUX1_BASE            (CD_AHB1PERIPH_BASE + 0x0800UL)

+#define ADC1_BASE               (CD_AHB1PERIPH_BASE + 0x2000UL)

+#define ADC2_BASE               (CD_AHB1PERIPH_BASE + 0x2100UL)

+#define ADC12_COMMON_BASE       (CD_AHB1PERIPH_BASE + 0x2300UL)

+#define CRC_BASE                (CD_AHB1PERIPH_BASE + 0x3000UL)

+

+/*!< USB registers base address */

+#define USB1_OTG_HS_PERIPH_BASE              (0x40040000UL)

+#define USB_OTG_GLOBAL_BASE                  (0x000UL)

+#define USB_OTG_DEVICE_BASE                  (0x800UL)

+#define USB_OTG_IN_ENDPOINT_BASE             (0x900UL)

+#define USB_OTG_OUT_ENDPOINT_BASE            (0xB00UL)

+#define USB_OTG_EP_REG_SIZE                  (0x20UL)

+#define USB_OTG_HOST_BASE                    (0x400UL)

+#define USB_OTG_HOST_PORT_BASE               (0x440UL)

+#define USB_OTG_HOST_CHANNEL_BASE            (0x500UL)

+#define USB_OTG_HOST_CHANNEL_SIZE            (0x20UL)

+#define USB_OTG_PCGCCTL_BASE                 (0xE00UL)

+#define USB_OTG_FIFO_BASE                    (0x1000UL)

+#define USB_OTG_FIFO_SIZE                    (0x1000UL)

+

+/*!< CD_AHB2PERIPH peripherals */

+

+#define DCMI_BASE              (CD_AHB2PERIPH_BASE + 0x0000UL)

+#define PSSI_BASE              (CD_AHB2PERIPH_BASE + 0x0400UL)

+#define HSEM_BASE              (CD_AHB2PERIPH_BASE + 0x0800UL)

+#define CRYP_BASE              (CD_AHB2PERIPH_BASE + 0x1000UL)

+#define HASH_BASE              (CD_AHB2PERIPH_BASE + 0x1400UL)

+#define HASH_DIGEST_BASE       (CD_AHB2PERIPH_BASE + 0x1710UL)

+#define RNG_BASE               (CD_AHB2PERIPH_BASE + 0x1800UL)

+#define SDMMC2_BASE            (CD_AHB2PERIPH_BASE + 0x2400UL)

+#define DLYB_SDMMC2_BASE       (CD_AHB2PERIPH_BASE + 0x2800UL)

+#define BDMA1_BASE             (CD_AHB2PERIPH_BASE + 0x2C00UL)

+

+/*!< SRD_AHB4PERIPH peripherals */

+#define GPIOA_BASE            (SRD_AHB4PERIPH_BASE + 0x0000UL)

+#define GPIOB_BASE            (SRD_AHB4PERIPH_BASE + 0x0400UL)

+#define GPIOC_BASE            (SRD_AHB4PERIPH_BASE + 0x0800UL)

+#define GPIOD_BASE            (SRD_AHB4PERIPH_BASE + 0x0C00UL)

+#define GPIOE_BASE            (SRD_AHB4PERIPH_BASE + 0x1000UL)

+#define GPIOF_BASE            (SRD_AHB4PERIPH_BASE + 0x1400UL)

+#define GPIOG_BASE            (SRD_AHB4PERIPH_BASE + 0x1800UL)

+#define GPIOH_BASE            (SRD_AHB4PERIPH_BASE + 0x1C00UL)

+#define GPIOI_BASE            (SRD_AHB4PERIPH_BASE + 0x2000UL)

+#define GPIOJ_BASE            (SRD_AHB4PERIPH_BASE + 0x2400UL)

+#define GPIOK_BASE            (SRD_AHB4PERIPH_BASE + 0x2800UL)

+#define RCC_BASE              (SRD_AHB4PERIPH_BASE + 0x4400UL)

+#define PWR_BASE              (SRD_AHB4PERIPH_BASE + 0x4800UL)

+#define BDMA2_BASE            (SRD_AHB4PERIPH_BASE + 0x5400UL)

+#define DMAMUX2_BASE          (SRD_AHB4PERIPH_BASE + 0x5800UL)

+

+/*!< CD_APB3PERIPH peripherals */

+#define LTDC_BASE             (CD_APB3PERIPH_BASE + 0x1000UL)

+#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84UL)

+#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104UL)

+#define WWDG1_BASE            (CD_APB3PERIPH_BASE + 0x3000UL)

+

+/*!< CD_APB1PERIPH peripherals */

+#define TIM2_BASE             (CD_APB1PERIPH_BASE + 0x0000UL)

+#define TIM3_BASE             (CD_APB1PERIPH_BASE + 0x0400UL)

+#define TIM4_BASE             (CD_APB1PERIPH_BASE + 0x0800UL)

+#define TIM5_BASE             (CD_APB1PERIPH_BASE + 0x0C00UL)

+#define TIM6_BASE             (CD_APB1PERIPH_BASE + 0x1000UL)

+#define TIM7_BASE             (CD_APB1PERIPH_BASE + 0x1400UL)

+#define TIM12_BASE            (CD_APB1PERIPH_BASE + 0x1800UL)

+#define TIM13_BASE            (CD_APB1PERIPH_BASE + 0x1C00UL)

+#define TIM14_BASE            (CD_APB1PERIPH_BASE + 0x2000UL)

+#define LPTIM1_BASE           (CD_APB1PERIPH_BASE + 0x2400UL)

+

+#define SPI2_BASE             (CD_APB1PERIPH_BASE + 0x3800UL)

+#define SPI3_BASE             (CD_APB1PERIPH_BASE + 0x3C00UL)

+#define SPDIFRX_BASE          (CD_APB1PERIPH_BASE + 0x4000UL)

+#define USART2_BASE           (CD_APB1PERIPH_BASE + 0x4400UL)

+#define USART3_BASE           (CD_APB1PERIPH_BASE + 0x4800UL)

+#define UART4_BASE            (CD_APB1PERIPH_BASE + 0x4C00UL)

+#define UART5_BASE            (CD_APB1PERIPH_BASE + 0x5000UL)

+#define I2C1_BASE             (CD_APB1PERIPH_BASE + 0x5400UL)

+#define I2C2_BASE             (CD_APB1PERIPH_BASE + 0x5800UL)

+#define I2C3_BASE             (CD_APB1PERIPH_BASE + 0x5C00UL)

+#define CEC_BASE              (CD_APB1PERIPH_BASE + 0x6C00UL)

+#define DAC1_BASE             (CD_APB1PERIPH_BASE + 0x7400UL)

+#define UART7_BASE            (CD_APB1PERIPH_BASE + 0x7800UL)

+#define UART8_BASE            (CD_APB1PERIPH_BASE + 0x7C00UL)

+#define CRS_BASE              (CD_APB1PERIPH_BASE + 0x8400UL)

+#define SWPMI1_BASE           (CD_APB1PERIPH_BASE + 0x8800UL)

+#define OPAMP_BASE            (CD_APB1PERIPH_BASE + 0x9000UL)

+#define OPAMP1_BASE           (CD_APB1PERIPH_BASE + 0x9000UL)

+#define OPAMP2_BASE           (CD_APB1PERIPH_BASE + 0x9010UL)

+#define MDIOS_BASE            (CD_APB1PERIPH_BASE + 0x9400UL)

+#define FDCAN1_BASE           (CD_APB1PERIPH_BASE + 0xA000UL)

+#define FDCAN2_BASE           (CD_APB1PERIPH_BASE + 0xA400UL)

+#define FDCAN_CCU_BASE        (CD_APB1PERIPH_BASE + 0xA800UL)

+#define SRAMCAN_BASE          (CD_APB1PERIPH_BASE + 0xAC00UL)

+

+/*!< CD_APB2PERIPH peripherals */

+

+#define TIM1_BASE             (CD_APB2PERIPH_BASE + 0x0000UL)

+#define TIM8_BASE             (CD_APB2PERIPH_BASE + 0x0400UL)

+#define USART1_BASE           (CD_APB2PERIPH_BASE + 0x1000UL)

+#define USART6_BASE           (CD_APB2PERIPH_BASE + 0x1400UL)

+#define UART9_BASE            (CD_APB2PERIPH_BASE + 0x1800UL)

+#define USART10_BASE          (CD_APB2PERIPH_BASE + 0x1C00UL)

+#define SPI1_BASE             (CD_APB2PERIPH_BASE + 0x3000UL)

+#define SPI4_BASE             (CD_APB2PERIPH_BASE + 0x3400UL)

+#define TIM15_BASE            (CD_APB2PERIPH_BASE + 0x4000UL)

+#define TIM16_BASE            (CD_APB2PERIPH_BASE + 0x4400UL)

+#define TIM17_BASE            (CD_APB2PERIPH_BASE + 0x4800UL)

+#define SPI5_BASE             (CD_APB2PERIPH_BASE + 0x5000UL)

+#define SAI1_BASE             (CD_APB2PERIPH_BASE + 0x5800UL)

+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)

+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)

+#define SAI2_BASE             (CD_APB2PERIPH_BASE + 0x5C00UL)

+#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004UL)

+#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024UL)

+#define DFSDM1_BASE           (CD_APB2PERIPH_BASE + 0x7800UL)

+#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00UL)

+#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20UL)

+#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40UL)

+#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60UL)

+#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80UL)

+#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0UL)

+#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0UL)

+#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0UL)

+#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)

+#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)

+#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)

+#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)

+#define DFSDM1_Filter4_BASE   (DFSDM1_BASE + 0x300UL)

+#define DFSDM1_Filter5_BASE   (DFSDM1_BASE + 0x380UL)

+#define DFSDM1_Filter6_BASE   (DFSDM1_BASE + 0x400UL)

+#define DFSDM1_Filter7_BASE   (DFSDM1_BASE + 0x480UL)

+/*!< SRD_APB4PERIPH peripherals */

+#define EXTI_BASE             (SRD_APB4PERIPH_BASE + 0x0000UL)

+#define EXTI_D1_BASE          (EXTI_BASE + 0x0080UL)

+#define SYSCFG_BASE           (SRD_APB4PERIPH_BASE + 0x0400UL)

+#define LPUART1_BASE          (SRD_APB4PERIPH_BASE + 0x0C00UL)

+#define SPI6_BASE             (SRD_APB4PERIPH_BASE + 0x1400UL)

+#define I2C4_BASE             (SRD_APB4PERIPH_BASE + 0x1C00UL)

+#define LPTIM2_BASE           (SRD_APB4PERIPH_BASE + 0x2400UL)

+#define LPTIM3_BASE           (SRD_APB4PERIPH_BASE + 0x2800UL)

+#define DAC2_BASE             (SRD_APB4PERIPH_BASE + 0x3400UL)

+#define COMP12_BASE           (SRD_APB4PERIPH_BASE + 0x3800UL)

+#define COMP1_BASE            (COMP12_BASE + 0x0CUL)

+#define COMP2_BASE            (COMP12_BASE + 0x10UL)

+#define VREFBUF_BASE          (SRD_APB4PERIPH_BASE + 0x3C00UL)

+#define RTC_BASE              (SRD_APB4PERIPH_BASE + 0x4000UL)

+#define TAMP_BASE             (SRD_APB4PERIPH_BASE + 0x4400UL)

+#define IWDG1_BASE            (SRD_APB4PERIPH_BASE + 0x4800UL)

+

+#define DTS_BASE              (SRD_APB4PERIPH_BASE + 0x6800UL)

+

+#define DFSDM2_BASE           (SRD_APB4PERIPH_BASE + 0x6C00UL)

+#define DFSDM2_Channel0_BASE  (DFSDM2_BASE + 0x00UL)

+#define DFSDM2_Channel1_BASE  (DFSDM2_BASE + 0x20UL)

+#define DFSDM2_FLT0_BASE      (DFSDM2_BASE + 0x100UL)

+

+/*!< CD_AHB3PERIPH peripherals */

+

+#define OTFDEC1_BASE          (CD_AHB3PERIPH_BASE + 0xB800UL)

+#define OTFDEC1_REGION1_BASE  (OTFDEC1_BASE + 0x20UL)

+#define OTFDEC1_REGION2_BASE  (OTFDEC1_BASE + 0x50UL)

+#define OTFDEC1_REGION3_BASE  (OTFDEC1_BASE + 0x80UL)

+#define OTFDEC1_REGION4_BASE  (OTFDEC1_BASE + 0xB0UL)

+#define OTFDEC2_BASE          (CD_AHB3PERIPH_BASE + 0xBC00UL)

+#define OTFDEC2_REGION1_BASE  (OTFDEC2_BASE + 0x20UL)

+#define OTFDEC2_REGION2_BASE  (OTFDEC2_BASE + 0x50UL)

+#define OTFDEC2_REGION3_BASE  (OTFDEC2_BASE + 0x80UL)

+#define OTFDEC2_REGION4_BASE  (OTFDEC2_BASE + 0xB0UL)

+#define GFXMMU_BASE           (CD_AHB3PERIPH_BASE + 0xC000UL)

+

+#define BDMA1_Channel0_BASE    (BDMA1_BASE + 0x0008UL)

+#define BDMA1_Channel1_BASE    (BDMA1_BASE + 0x001CUL)

+#define BDMA1_Channel2_BASE    (BDMA1_BASE + 0x0030UL)

+#define BDMA1_Channel3_BASE    (BDMA1_BASE + 0x0044UL)

+#define BDMA1_Channel4_BASE    (BDMA1_BASE + 0x0058UL)

+#define BDMA1_Channel5_BASE    (BDMA1_BASE + 0x006CUL)

+#define BDMA1_Channel6_BASE    (BDMA1_BASE + 0x0080UL)

+#define BDMA1_Channel7_BASE    (BDMA1_BASE + 0x0094UL)

+

+#define BDMA2_Channel0_BASE    (BDMA2_BASE + 0x0008UL)

+#define BDMA2_Channel1_BASE    (BDMA2_BASE + 0x001CUL)

+#define BDMA2_Channel2_BASE    (BDMA2_BASE + 0x0030UL)

+#define BDMA2_Channel3_BASE    (BDMA2_BASE + 0x0044UL)

+#define BDMA2_Channel4_BASE    (BDMA2_BASE + 0x0058UL)

+#define BDMA2_Channel5_BASE    (BDMA2_BASE + 0x006CUL)

+#define BDMA2_Channel6_BASE    (BDMA2_BASE + 0x0080UL)

+#define BDMA2_Channel7_BASE    (BDMA2_BASE + 0x0094UL)

+

+

+#define DMAMUX2_Channel0_BASE    (DMAMUX2_BASE)

+#define DMAMUX2_Channel1_BASE    (DMAMUX2_BASE + 0x0004UL)

+#define DMAMUX2_Channel2_BASE    (DMAMUX2_BASE + 0x0008UL)

+#define DMAMUX2_Channel3_BASE    (DMAMUX2_BASE + 0x000CUL)

+#define DMAMUX2_Channel4_BASE    (DMAMUX2_BASE + 0x0010UL)

+#define DMAMUX2_Channel5_BASE    (DMAMUX2_BASE + 0x0014UL)

+#define DMAMUX2_Channel6_BASE    (DMAMUX2_BASE + 0x0018UL)

+#define DMAMUX2_Channel7_BASE    (DMAMUX2_BASE + 0x001CUL)

+

+#define DMAMUX2_RequestGenerator0_BASE  (DMAMUX2_BASE + 0x0100UL)

+#define DMAMUX2_RequestGenerator1_BASE  (DMAMUX2_BASE + 0x0104UL)

+#define DMAMUX2_RequestGenerator2_BASE  (DMAMUX2_BASE + 0x0108UL)

+#define DMAMUX2_RequestGenerator3_BASE  (DMAMUX2_BASE + 0x010CUL)

+#define DMAMUX2_RequestGenerator4_BASE  (DMAMUX2_BASE + 0x0110UL)

+#define DMAMUX2_RequestGenerator5_BASE  (DMAMUX2_BASE + 0x0114UL)

+#define DMAMUX2_RequestGenerator6_BASE  (DMAMUX2_BASE + 0x0118UL)

+#define DMAMUX2_RequestGenerator7_BASE  (DMAMUX2_BASE + 0x011CUL)

+

+#define DMAMUX2_ChannelStatus_BASE      (DMAMUX2_BASE + 0x0080UL)

+#define DMAMUX2_RequestGenStatus_BASE   (DMAMUX2_BASE + 0x0140UL)

+

+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)

+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)

+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)

+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)

+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)

+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)

+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)

+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)

+

+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)

+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)

+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)

+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)

+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)

+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)

+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)

+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)

+

+

+#define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)

+#define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)

+#define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)

+#define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)

+#define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)

+#define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)

+#define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0018UL)

+#define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x001CUL)

+#define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0020UL)

+#define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x0024UL)

+#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)

+#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)

+#define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)

+#define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)

+#define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)

+#define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)

+

+#define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)

+#define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)

+#define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)

+#define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)

+#define DMAMUX1_RequestGenerator4_BASE  (DMAMUX1_BASE + 0x0110UL)

+#define DMAMUX1_RequestGenerator5_BASE  (DMAMUX1_BASE + 0x0114UL)

+#define DMAMUX1_RequestGenerator6_BASE  (DMAMUX1_BASE + 0x0118UL)

+#define DMAMUX1_RequestGenerator7_BASE  (DMAMUX1_BASE + 0x011CUL)

+

+#define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)

+#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)

+

+/*!< FMC Banks registers base  address */

+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)

+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)

+#define FMC_Bank2_R_BASE      (FMC_R_BASE + 0x0060UL)

+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)

+#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)

+

+/* Debug MCU registers base address */

+#define DBGMCU_BASE           (0x5C001000UL)

+

+#define MDMA_Channel0_BASE    (MDMA_BASE + 0x00000040UL)

+#define MDMA_Channel1_BASE    (MDMA_BASE + 0x00000080UL)

+#define MDMA_Channel2_BASE    (MDMA_BASE + 0x000000C0UL)

+#define MDMA_Channel3_BASE    (MDMA_BASE + 0x00000100UL)

+#define MDMA_Channel4_BASE    (MDMA_BASE + 0x00000140UL)

+#define MDMA_Channel5_BASE    (MDMA_BASE + 0x00000180UL)

+#define MDMA_Channel6_BASE    (MDMA_BASE + 0x000001C0UL)

+#define MDMA_Channel7_BASE    (MDMA_BASE + 0x00000200UL)

+#define MDMA_Channel8_BASE    (MDMA_BASE + 0x00000240UL)

+#define MDMA_Channel9_BASE    (MDMA_BASE + 0x00000280UL)

+#define MDMA_Channel10_BASE   (MDMA_BASE + 0x000002C0UL)

+#define MDMA_Channel11_BASE   (MDMA_BASE + 0x00000300UL)

+#define MDMA_Channel12_BASE   (MDMA_BASE + 0x00000340UL)

+#define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)

+#define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)

+#define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)

+#define MDMA_Channel16_BASE   (MDMA_BASE + 0x00000440UL)

+

+/* GFXMMU virtual buffers base address */

+#define GFXMMU_VIRTUAL_BUFFERS_BASE  (0x25000000UL)

+#define GFXMMU_VIRTUAL_BUFFER0_BASE  (GFXMMU_VIRTUAL_BUFFERS_BASE)

+#define GFXMMU_VIRTUAL_BUFFER1_BASE  (GFXMMU_VIRTUAL_BUFFERS_BASE + 0x400000UL)

+#define GFXMMU_VIRTUAL_BUFFER2_BASE  (GFXMMU_VIRTUAL_BUFFERS_BASE + 0x800000UL)

+#define GFXMMU_VIRTUAL_BUFFER3_BASE  (GFXMMU_VIRTUAL_BUFFERS_BASE + 0xC00000UL)

+

+#define RAMECC_Monitor1_BASE (RAMECC_BASE + 0x20UL)

+#define RAMECC_Monitor2_BASE (RAMECC_BASE + 0x40UL)

+#define RAMECC_Monitor3_BASE (RAMECC_BASE + 0x60UL)

+

+/**

+  * @}

+  */

+

+/** @addtogroup Peripheral_declaration

+  * @{

+  */

+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)

+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)

+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)

+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)

+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)

+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)

+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)

+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)

+#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)

+#define RTC                 ((RTC_TypeDef *) RTC_BASE)

+#define TAMP                ((TAMP_TypeDef *) TAMP_BASE)

+#define WWDG1               ((WWDG_TypeDef *) WWDG1_BASE)

+

+

+#define IWDG1               ((IWDG_TypeDef *) IWDG1_BASE)

+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)

+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)

+#define SPI4                ((SPI_TypeDef *) SPI4_BASE)

+#define SPI5                ((SPI_TypeDef *) SPI5_BASE)

+#define SPI6                ((SPI_TypeDef *) SPI6_BASE)

+#define USART2              ((USART_TypeDef *) USART2_BASE)

+#define USART3              ((USART_TypeDef *) USART3_BASE)

+#define USART6              ((USART_TypeDef *) USART6_BASE)

+#define USART10             ((USART_TypeDef *) USART10_BASE)

+#define UART7               ((USART_TypeDef *) UART7_BASE)

+#define UART8               ((USART_TypeDef *) UART8_BASE)

+#define UART9               ((USART_TypeDef *) UART9_BASE)

+#define CRS                 ((CRS_TypeDef *) CRS_BASE)

+#define UART4               ((USART_TypeDef *) UART4_BASE)

+#define UART5               ((USART_TypeDef *) UART5_BASE)

+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)

+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)

+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)

+#define I2C4                ((I2C_TypeDef *) I2C4_BASE)

+#define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

+#define FDCAN2              ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

+#define FDCAN_CCU           ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

+#define CEC                 ((CEC_TypeDef *) CEC_BASE)

+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)

+#define PWR                 ((PWR_TypeDef *) PWR_BASE)

+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)

+#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)

+#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)

+#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)

+#define LPTIM3              ((LPTIM_TypeDef *) LPTIM3_BASE)

+#define DTS                 ((DTS_TypeDef *) DTS_BASE)

+

+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)

+#define COMP12              ((COMPOPT_TypeDef *) COMP12_BASE)

+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)

+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)

+#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)

+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)

+#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)

+#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)

+

+

+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)

+#define EXTI_D1             ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)

+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)

+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)

+#define USART1              ((USART_TypeDef *) USART1_BASE)

+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)

+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)

+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)

+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)

+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)

+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

+#define SAI2                ((SAI_TypeDef *) SAI2_BASE)

+#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)

+#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)

+

+#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

+#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

+#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

+#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

+#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

+#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

+#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

+#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

+#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

+#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

+#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

+#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

+#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

+#define DFSDM1_Filter4      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter4_BASE)

+#define DFSDM1_Filter5      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter5_BASE)

+#define DFSDM1_Filter6      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter6_BASE)

+#define DFSDM1_Filter7      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter7_BASE)

+#define DFSDM2_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel0_BASE)

+#define DFSDM2_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel1_BASE)

+#define DFSDM2_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM2_FLT0_BASE)

+#define DMA2D               ((DMA2D_TypeDef *) DMA2D_BASE)

+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)

+#define PSSI                ((PSSI_TypeDef *) PSSI_BASE)

+#define RCC                 ((RCC_TypeDef *) RCC_BASE)

+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)

+#define CRC                 ((CRC_TypeDef *) CRC_BASE)

+

+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)

+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)

+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)

+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)

+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)

+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)

+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)

+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)

+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)

+#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)

+#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)

+

+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)

+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)

+#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

+

+#define CRYP                ((CRYP_TypeDef *) CRYP_BASE)

+#define HASH                ((HASH_TypeDef *) HASH_BASE)

+#define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)

+#define RNG                 ((RNG_TypeDef *) RNG_BASE)

+#define SDMMC2              ((SDMMC_TypeDef *) SDMMC2_BASE)

+#define DLYB_SDMMC2         ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

+

+#define BDMA1                ((BDMA_TypeDef *) BDMA1_BASE)

+#define BDMA1_Channel0       ((BDMA_Channel_TypeDef *) BDMA1_Channel0_BASE)

+#define BDMA1_Channel1       ((BDMA_Channel_TypeDef *) BDMA1_Channel1_BASE)

+#define BDMA1_Channel2       ((BDMA_Channel_TypeDef *) BDMA1_Channel2_BASE)

+#define BDMA1_Channel3       ((BDMA_Channel_TypeDef *) BDMA1_Channel3_BASE)

+#define BDMA1_Channel4       ((BDMA_Channel_TypeDef *) BDMA1_Channel4_BASE)

+#define BDMA1_Channel5       ((BDMA_Channel_TypeDef *) BDMA1_Channel5_BASE)

+#define BDMA1_Channel6       ((BDMA_Channel_TypeDef *) BDMA1_Channel6_BASE)

+#define BDMA1_Channel7       ((BDMA_Channel_TypeDef *) BDMA1_Channel7_BASE)

+

+#define BDMA2                ((BDMA_TypeDef *) BDMA2_BASE)

+#define BDMA2_Channel0       ((BDMA_Channel_TypeDef *) BDMA2_Channel0_BASE)

+#define BDMA2_Channel1       ((BDMA_Channel_TypeDef *) BDMA2_Channel1_BASE)

+#define BDMA2_Channel2       ((BDMA_Channel_TypeDef *) BDMA2_Channel2_BASE)

+#define BDMA2_Channel3       ((BDMA_Channel_TypeDef *) BDMA2_Channel3_BASE)

+#define BDMA2_Channel4       ((BDMA_Channel_TypeDef *) BDMA2_Channel4_BASE)

+#define BDMA2_Channel5       ((BDMA_Channel_TypeDef *) BDMA2_Channel5_BASE)

+#define BDMA2_Channel6       ((BDMA_Channel_TypeDef *) BDMA2_Channel6_BASE)

+#define BDMA2_Channel7       ((BDMA_Channel_TypeDef *) BDMA2_Channel7_BASE)

+

+#define RAMECC               ((RAMECC_TypeDef *)RAMECC_BASE)

+#define RAMECC_Monitor1      ((RAMECC_MonitorTypeDef *)RAMECC_Monitor1_BASE)

+#define RAMECC_Monitor2      ((RAMECC_MonitorTypeDef *)RAMECC_Monitor2_BASE)

+#define RAMECC_Monitor3      ((RAMECC_MonitorTypeDef *)RAMECC_Monitor3_BASE)

+

+#define DMAMUX2                ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

+#define DMAMUX2_Channel0       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

+#define DMAMUX2_Channel1       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

+#define DMAMUX2_Channel2       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

+#define DMAMUX2_Channel3       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

+#define DMAMUX2_Channel4       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

+#define DMAMUX2_Channel5       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

+#define DMAMUX2_Channel6       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

+#define DMAMUX2_Channel7       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

+

+

+#define DMAMUX2_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

+#define DMAMUX2_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

+#define DMAMUX2_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

+#define DMAMUX2_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

+#define DMAMUX2_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

+#define DMAMUX2_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

+#define DMAMUX2_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

+#define DMAMUX2_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

+

+#define DMAMUX2_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

+#define DMAMUX2_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

+

+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)

+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

+

+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)

+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

+

+

+#define DMAMUX1              ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

+#define DMAMUX1_Channel0     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

+#define DMAMUX1_Channel1     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

+#define DMAMUX1_Channel2     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

+#define DMAMUX1_Channel3     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

+#define DMAMUX1_Channel4     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

+#define DMAMUX1_Channel5     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

+#define DMAMUX1_Channel6     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

+#define DMAMUX1_Channel7     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

+#define DMAMUX1_Channel8     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

+#define DMAMUX1_Channel9     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

+#define DMAMUX1_Channel10    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

+#define DMAMUX1_Channel11    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

+#define DMAMUX1_Channel12    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

+#define DMAMUX1_Channel13    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

+#define DMAMUX1_Channel14    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

+#define DMAMUX1_Channel15    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

+

+#define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

+#define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

+#define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

+#define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

+#define DMAMUX1_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

+#define DMAMUX1_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

+#define DMAMUX1_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

+#define DMAMUX1_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

+

+#define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *)    DMAMUX1_ChannelStatus_BASE)

+#define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

+

+

+#define FMC_Bank1_R           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

+#define FMC_Bank1E_R          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

+#define FMC_Bank2_R           ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

+#define FMC_Bank3_R           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

+#define FMC_Bank5_6_R         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

+

+#define DAC2                ((DAC_TypeDef *) DAC2_BASE)

+#define OCTOSPI1            ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)

+#define DLYB_OCTOSPI1       ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE)

+#define OCTOSPI2            ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)

+#define DLYB_OCTOSPI2       ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE)

+#define OCTOSPIM            ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)

+

+#define OTFDEC1               ((OTFDEC_TypeDef *) OTFDEC1_BASE)

+#define OTFDEC1_REGION1       ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE)

+#define OTFDEC1_REGION2       ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE)

+#define OTFDEC1_REGION3       ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE)

+#define OTFDEC1_REGION4       ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE)

+

+#define OTFDEC2               ((OTFDEC_TypeDef *) OTFDEC2_BASE)

+#define OTFDEC2_REGION1       ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE)

+#define OTFDEC2_REGION2       ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE)

+#define OTFDEC2_REGION3       ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE)

+#define OTFDEC2_REGION4       ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE)

+#define GFXMMU              ((GFXMMU_TypeDef *) GFXMMU_BASE)

+

+#define SDMMC1                ((SDMMC_TypeDef *) SDMMC1_BASE)

+#define DLYB_SDMMC1           ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

+

+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)

+

+#define JPEG                ((JPEG_TypeDef *) JPGDEC_BASE)

+#define HSEM                ((HSEM_TypeDef *) HSEM_BASE)

+#define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

+

+#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)

+#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

+#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

+

+#define MDIOS               ((MDIOS_TypeDef *) MDIOS_BASE)

+

+#define MDMA                ((MDMA_TypeDef *)MDMA_BASE)

+#define MDMA_Channel0       ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

+#define MDMA_Channel1       ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

+#define MDMA_Channel2       ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

+#define MDMA_Channel3       ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

+#define MDMA_Channel4       ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

+#define MDMA_Channel5       ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

+#define MDMA_Channel6       ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

+#define MDMA_Channel7       ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

+#define MDMA_Channel8       ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

+#define MDMA_Channel9       ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

+#define MDMA_Channel10      ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

+#define MDMA_Channel11      ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

+#define MDMA_Channel12      ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

+#define MDMA_Channel13      ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

+#define MDMA_Channel14      ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

+#define MDMA_Channel15      ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

+

+

+#define USB1_OTG_HS         ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

+

+/* Legacy defines */

+#define USB_OTG_HS                   USB1_OTG_HS

+#define USB_OTG_HS_PERIPH_BASE       USB1_OTG_HS_PERIPH_BASE

+

+/**

+  * @}

+  */

+

+/** @addtogroup Exported_constants

+  * @{

+  */

+

+  /** @addtogroup Peripheral_Registers_Bits_Definition

+  * @{

+  */

+

+/******************************************************************************/

+/*                         Peripheral Registers_Bits_Definition               */

+/******************************************************************************/

+

+/******************************************************************************/

+/*                                                                            */

+/*                        Analog to Digital Converter                         */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  ADC VERSION  ********************************/

+#define ADC_VER_V5_3

+/********************  Bit definition for ADC_ISR register  ********************/

+#define ADC_ISR_ADRDY_Pos                 (0U)

+#define ADC_ISR_ADRDY_Msk                 (0x1UL << ADC_ISR_ADRDY_Pos)         /*!< 0x00000001 */

+#define ADC_ISR_ADRDY                     ADC_ISR_ADRDY_Msk                    /*!< ADC Ready (ADRDY) flag  */

+#define ADC_ISR_EOSMP_Pos                 (1U)

+#define ADC_ISR_EOSMP_Msk                 (0x1UL << ADC_ISR_EOSMP_Pos)         /*!< 0x00000002 */

+#define ADC_ISR_EOSMP                     ADC_ISR_EOSMP_Msk                    /*!< ADC End of Sampling flag */

+#define ADC_ISR_EOC_Pos                   (2U)

+#define ADC_ISR_EOC_Msk                   (0x1UL << ADC_ISR_EOC_Pos)           /*!< 0x00000004 */

+#define ADC_ISR_EOC                       ADC_ISR_EOC_Msk                      /*!< ADC End of Regular Conversion flag */

+#define ADC_ISR_EOS_Pos                   (3U)

+#define ADC_ISR_EOS_Msk                   (0x1UL << ADC_ISR_EOS_Pos)           /*!< 0x00000008 */

+#define ADC_ISR_EOS                       ADC_ISR_EOS_Msk                      /*!< ADC End of Regular sequence of Conversions flag */

+#define ADC_ISR_OVR_Pos                   (4U)

+#define ADC_ISR_OVR_Msk                   (0x1UL << ADC_ISR_OVR_Pos)           /*!< 0x00000010 */

+#define ADC_ISR_OVR                       ADC_ISR_OVR_Msk                      /*!< ADC overrun flag */

+#define ADC_ISR_JEOC_Pos                  (5U)

+#define ADC_ISR_JEOC_Msk                  (0x1UL << ADC_ISR_JEOC_Pos)          /*!< 0x00000020 */

+#define ADC_ISR_JEOC                      ADC_ISR_JEOC_Msk                     /*!< ADC End of Injected Conversion flag */

+#define ADC_ISR_JEOS_Pos                  (6U)

+#define ADC_ISR_JEOS_Msk                  (0x1UL << ADC_ISR_JEOS_Pos)          /*!< 0x00000040 */

+#define ADC_ISR_JEOS                      ADC_ISR_JEOS_Msk                     /*!< ADC End of Injected sequence of Conversions flag */

+#define ADC_ISR_AWD1_Pos                  (7U)

+#define ADC_ISR_AWD1_Msk                  (0x1UL << ADC_ISR_AWD1_Pos)          /*!< 0x00000080 */

+#define ADC_ISR_AWD1                      ADC_ISR_AWD1_Msk                     /*!< ADC Analog watchdog 1 flag */

+#define ADC_ISR_AWD2_Pos                  (8U)

+#define ADC_ISR_AWD2_Msk                  (0x1UL << ADC_ISR_AWD2_Pos)          /*!< 0x00000100 */

+#define ADC_ISR_AWD2                      ADC_ISR_AWD2_Msk                     /*!< ADC Analog watchdog 2 flag */

+#define ADC_ISR_AWD3_Pos                  (9U)

+#define ADC_ISR_AWD3_Msk                  (0x1UL << ADC_ISR_AWD3_Pos)          /*!< 0x00000200 */

+#define ADC_ISR_AWD3                      ADC_ISR_AWD3_Msk                     /*!< ADC Analog watchdog 3 flag */

+#define ADC_ISR_JQOVF_Pos                 (10U)

+#define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */

+#define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */

+

+/********************  Bit definition for ADC_IER register  ********************/

+#define ADC_IER_ADRDYIE_Pos               (0U)

+#define ADC_IER_ADRDYIE_Msk               (0x1UL << ADC_IER_ADRDYIE_Pos)       /*!< 0x00000001 */

+#define ADC_IER_ADRDYIE                   ADC_IER_ADRDYIE_Msk                  /*!< ADC Ready (ADRDY) interrupt source */

+#define ADC_IER_EOSMPIE_Pos               (1U)

+#define ADC_IER_EOSMPIE_Msk               (0x1UL << ADC_IER_EOSMPIE_Pos)       /*!< 0x00000002 */

+#define ADC_IER_EOSMPIE                   ADC_IER_EOSMPIE_Msk                  /*!< ADC End of Sampling interrupt source */

+#define ADC_IER_EOCIE_Pos                 (2U)

+#define ADC_IER_EOCIE_Msk                 (0x1UL << ADC_IER_EOCIE_Pos)         /*!< 0x00000004 */

+#define ADC_IER_EOCIE                     ADC_IER_EOCIE_Msk                    /*!< ADC End of Regular Conversion interrupt source */

+#define ADC_IER_EOSIE_Pos                 (3U)

+#define ADC_IER_EOSIE_Msk                 (0x1UL << ADC_IER_EOSIE_Pos)         /*!< 0x00000008 */

+#define ADC_IER_EOSIE                     ADC_IER_EOSIE_Msk                    /*!< ADC End of Regular sequence of Conversions interrupt source */

+#define ADC_IER_OVRIE_Pos                 (4U)

+#define ADC_IER_OVRIE_Msk                 (0x1UL << ADC_IER_OVRIE_Pos)         /*!< 0x00000010 */

+#define ADC_IER_OVRIE                     ADC_IER_OVRIE_Msk                    /*!< ADC overrun interrupt source */

+#define ADC_IER_JEOCIE_Pos                (5U)

+#define ADC_IER_JEOCIE_Msk                (0x1UL << ADC_IER_JEOCIE_Pos)        /*!< 0x00000020 */

+#define ADC_IER_JEOCIE                    ADC_IER_JEOCIE_Msk                   /*!< ADC End of Injected Conversion interrupt source */

+#define ADC_IER_JEOSIE_Pos                (6U)

+#define ADC_IER_JEOSIE_Msk                (0x1UL << ADC_IER_JEOSIE_Pos)        /*!< 0x00000040 */

+#define ADC_IER_JEOSIE                    ADC_IER_JEOSIE_Msk                   /*!< ADC End of Injected sequence of Conversions interrupt source */

+#define ADC_IER_AWD1IE_Pos                (7U)

+#define ADC_IER_AWD1IE_Msk                (0x1UL << ADC_IER_AWD1IE_Pos)        /*!< 0x00000080 */

+#define ADC_IER_AWD1IE                    ADC_IER_AWD1IE_Msk                   /*!< ADC Analog watchdog 1 interrupt source */

+#define ADC_IER_AWD2IE_Pos                (8U)

+#define ADC_IER_AWD2IE_Msk                (0x1UL << ADC_IER_AWD2IE_Pos)        /*!< 0x00000100 */

+#define ADC_IER_AWD2IE                    ADC_IER_AWD2IE_Msk                   /*!< ADC Analog watchdog 2 interrupt source */

+#define ADC_IER_AWD3IE_Pos                (9U)

+#define ADC_IER_AWD3IE_Msk                (0x1UL << ADC_IER_AWD3IE_Pos)        /*!< 0x00000200 */

+#define ADC_IER_AWD3IE                    ADC_IER_AWD3IE_Msk                   /*!< ADC Analog watchdog 3 interrupt source */

+#define ADC_IER_JQOVFIE_Pos               (10U)

+#define ADC_IER_JQOVFIE_Msk               (0x1UL << ADC_IER_JQOVFIE_Pos)       /*!< 0x00000400 */

+#define ADC_IER_JQOVFIE                   ADC_IER_JQOVFIE_Msk                  /*!< ADC Injected Context Queue Overflow interrupt source */

+

+/********************  Bit definition for ADC_CR register  ********************/

+#define ADC_CR_ADEN_Pos                   (0U)

+#define ADC_CR_ADEN_Msk                   (0x1UL << ADC_CR_ADEN_Pos)           /*!< 0x00000001 */

+#define ADC_CR_ADEN                       ADC_CR_ADEN_Msk                      /*!< ADC Enable control */

+#define ADC_CR_ADDIS_Pos                  (1U)

+#define ADC_CR_ADDIS_Msk                  (0x1UL << ADC_CR_ADDIS_Pos)          /*!< 0x00000002 */

+#define ADC_CR_ADDIS                      ADC_CR_ADDIS_Msk                     /*!< ADC Disable command */

+#define ADC_CR_ADSTART_Pos                (2U)

+#define ADC_CR_ADSTART_Msk                (0x1UL << ADC_CR_ADSTART_Pos)        /*!< 0x00000004 */

+#define ADC_CR_ADSTART                    ADC_CR_ADSTART_Msk                   /*!< ADC Start of Regular conversion */

+#define ADC_CR_JADSTART_Pos               (3U)

+#define ADC_CR_JADSTART_Msk               (0x1UL << ADC_CR_JADSTART_Pos)       /*!< 0x00000008 */

+#define ADC_CR_JADSTART                   ADC_CR_JADSTART_Msk                  /*!< ADC Start of injected conversion */

+#define ADC_CR_ADSTP_Pos                  (4U)

+#define ADC_CR_ADSTP_Msk                  (0x1UL << ADC_CR_ADSTP_Pos)          /*!< 0x00000010 */

+#define ADC_CR_ADSTP                      ADC_CR_ADSTP_Msk                     /*!< ADC Stop of Regular conversion */

+#define ADC_CR_JADSTP_Pos                 (5U)

+#define ADC_CR_JADSTP_Msk                 (0x1UL << ADC_CR_JADSTP_Pos)         /*!< 0x00000020 */

+#define ADC_CR_JADSTP                     ADC_CR_JADSTP_Msk                    /*!< ADC Stop of injected conversion */

+#define ADC_CR_BOOST_Pos                  (8U)

+#define ADC_CR_BOOST_Msk                  (0x3UL << ADC_CR_BOOST_Pos)          /*!< 0x00000300 */

+#define ADC_CR_BOOST                      ADC_CR_BOOST_Msk                     /*!< ADC Boost Mode configuration */

+#define ADC_CR_BOOST_0                    (0x1UL << ADC_CR_BOOST_Pos)           /*!< 0x00000100 */

+#define ADC_CR_BOOST_1                    (0x2UL << ADC_CR_BOOST_Pos)           /*!< 0x00000200 */

+#define ADC_CR_ADCALLIN_Pos               (16U)

+#define ADC_CR_ADCALLIN_Msk               (0x1UL << ADC_CR_ADCALLIN_Pos)       /*!< 0x00010000 */

+#define ADC_CR_ADCALLIN                   ADC_CR_ADCALLIN_Msk                  /*!< ADC Linearity calibration */

+#define ADC_CR_LINCALRDYW1_Pos            (22U)

+#define ADC_CR_LINCALRDYW1_Msk            (0x1UL << ADC_CR_LINCALRDYW1_Pos)    /*!< 0x00400000 */

+#define ADC_CR_LINCALRDYW1                ADC_CR_LINCALRDYW1_Msk               /*!< ADC Linearity calibration ready Word 1 */

+#define ADC_CR_LINCALRDYW2_Pos            (23U)

+#define ADC_CR_LINCALRDYW2_Msk            (0x1UL << ADC_CR_LINCALRDYW2_Pos)    /*!< 0x00800000 */

+#define ADC_CR_LINCALRDYW2                ADC_CR_LINCALRDYW2_Msk               /*!< ADC Linearity calibration ready Word 2 */

+#define ADC_CR_LINCALRDYW3_Pos            (24U)

+#define ADC_CR_LINCALRDYW3_Msk            (0x1UL << ADC_CR_LINCALRDYW3_Pos)    /*!< 0x01000000 */

+#define ADC_CR_LINCALRDYW3                ADC_CR_LINCALRDYW3_Msk               /*!< ADC Linearity calibration ready Word 3 */

+#define ADC_CR_LINCALRDYW4_Pos            (25U)

+#define ADC_CR_LINCALRDYW4_Msk            (0x1UL << ADC_CR_LINCALRDYW4_Pos)    /*!< 0x02000000 */

+#define ADC_CR_LINCALRDYW4                ADC_CR_LINCALRDYW4_Msk               /*!< ADC Linearity calibration ready Word 4 */

+#define ADC_CR_LINCALRDYW5_Pos            (26U)

+#define ADC_CR_LINCALRDYW5_Msk            (0x1UL << ADC_CR_LINCALRDYW5_Pos)    /*!< 0x04000000 */

+#define ADC_CR_LINCALRDYW5                ADC_CR_LINCALRDYW5_Msk               /*!< ADC Linearity calibration ready Word 5 */

+#define ADC_CR_LINCALRDYW6_Pos            (27U)

+#define ADC_CR_LINCALRDYW6_Msk            (0x1UL << ADC_CR_LINCALRDYW6_Pos)    /*!< 0x08000000 */

+#define ADC_CR_LINCALRDYW6                ADC_CR_LINCALRDYW6_Msk               /*!< ADC Linearity calibration ready Word 6 */

+#define ADC_CR_ADVREGEN_Pos               (28U)

+#define ADC_CR_ADVREGEN_Msk               (0x1UL << ADC_CR_ADVREGEN_Pos)       /*!< 0x10000000 */

+#define ADC_CR_ADVREGEN                   ADC_CR_ADVREGEN_Msk                  /*!< ADC Voltage regulator Enable */

+#define ADC_CR_DEEPPWD_Pos                (29U)

+#define ADC_CR_DEEPPWD_Msk                (0x1UL << ADC_CR_DEEPPWD_Pos)        /*!< 0x20000000 */

+#define ADC_CR_DEEPPWD                    ADC_CR_DEEPPWD_Msk                   /*!< ADC Deep power down Enable */

+#define ADC_CR_ADCALDIF_Pos               (30U)

+#define ADC_CR_ADCALDIF_Msk               (0x1UL << ADC_CR_ADCALDIF_Pos)       /*!< 0x40000000 */

+#define ADC_CR_ADCALDIF                   ADC_CR_ADCALDIF_Msk                  /*!< ADC Differential Mode for calibration */

+#define ADC_CR_ADCAL_Pos                  (31U)

+#define ADC_CR_ADCAL_Msk                  (0x1UL << ADC_CR_ADCAL_Pos)          /*!< 0x80000000 */

+#define ADC_CR_ADCAL                      ADC_CR_ADCAL_Msk                     /*!< ADC Calibration */

+

+/********************  Bit definition for ADC_CFGR register  ********************/

+#define ADC_CFGR_DMNGT_Pos                (0U)

+#define ADC_CFGR_DMNGT_Msk                (0x3UL << ADC_CFGR_DMNGT_Pos)        /*!< 0x00000003 */

+#define ADC_CFGR_DMNGT                    ADC_CFGR_DMNGT_Msk                   /*!< ADC Data Management configuration */

+#define ADC_CFGR_DMNGT_0                  (0x1UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000001 */

+#define ADC_CFGR_DMNGT_1                  (0x2UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000002 */

+

+#define ADC_CFGR_RES_Pos                  (2U)

+#define ADC_CFGR_RES_Msk                  (0x7UL << ADC_CFGR_RES_Pos)          /*!< 0x0000001C */

+#define ADC_CFGR_RES                      ADC_CFGR_RES_Msk                     /*!< ADC Data resolution */

+#define ADC_CFGR_RES_0                    (0x1UL << ADC_CFGR_RES_Pos)           /*!< 0x00000004 */

+#define ADC_CFGR_RES_1                    (0x2UL << ADC_CFGR_RES_Pos)           /*!< 0x00000008 */

+#define ADC_CFGR_RES_2                    (0x4UL << ADC_CFGR_RES_Pos)           /*!< 0x00000010 */

+

+#define ADC_CFGR_EXTSEL_Pos               (5U)

+#define ADC_CFGR_EXTSEL_Msk               (0x1FUL << ADC_CFGR_EXTSEL_Pos)      /*!< 0x000003E0 */

+#define ADC_CFGR_EXTSEL                   ADC_CFGR_EXTSEL_Msk                  /*!< ADC External trigger selection for regular group */

+#define ADC_CFGR_EXTSEL_0                 (0x01UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000020 */

+#define ADC_CFGR_EXTSEL_1                 (0x02UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000040 */

+#define ADC_CFGR_EXTSEL_2                 (0x04UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000080 */

+#define ADC_CFGR_EXTSEL_3                 (0x08UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000100 */

+#define ADC_CFGR_EXTSEL_4                 (0x10UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000200 */

+

+#define ADC_CFGR_EXTEN_Pos                (10U)

+#define ADC_CFGR_EXTEN_Msk                (0x3UL << ADC_CFGR_EXTEN_Pos)        /*!< 0x00000C00 */

+#define ADC_CFGR_EXTEN                    ADC_CFGR_EXTEN_Msk                   /*!< ADC External trigger enable and polarity selection for regular channels */

+#define ADC_CFGR_EXTEN_0                  (0x1UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000400 */

+#define ADC_CFGR_EXTEN_1                  (0x2UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000800 */

+

+#define ADC_CFGR_OVRMOD_Pos               (12U)

+#define ADC_CFGR_OVRMOD_Msk               (0x1UL << ADC_CFGR_OVRMOD_Pos)       /*!< 0x00001000 */

+#define ADC_CFGR_OVRMOD                   ADC_CFGR_OVRMOD_Msk                  /*!< ADC overrun mode */

+#define ADC_CFGR_CONT_Pos                 (13U)

+#define ADC_CFGR_CONT_Msk                 (0x1UL << ADC_CFGR_CONT_Pos)         /*!< 0x00002000 */

+#define ADC_CFGR_CONT                     ADC_CFGR_CONT_Msk                    /*!< ADC Single/continuous conversion mode for regular conversion */

+#define ADC_CFGR_AUTDLY_Pos               (14U)

+#define ADC_CFGR_AUTDLY_Msk               (0x1UL << ADC_CFGR_AUTDLY_Pos)       /*!< 0x00004000 */

+#define ADC_CFGR_AUTDLY                   ADC_CFGR_AUTDLY_Msk                  /*!< ADC Delayed conversion mode */

+

+#define ADC_CFGR_DISCEN_Pos               (16U)

+#define ADC_CFGR_DISCEN_Msk               (0x1UL << ADC_CFGR_DISCEN_Pos)       /*!< 0x00010000 */

+#define ADC_CFGR_DISCEN                   ADC_CFGR_DISCEN_Msk                  /*!< ADC Discontinuous mode for regular channels */

+

+#define ADC_CFGR_DISCNUM_Pos              (17U)

+#define ADC_CFGR_DISCNUM_Msk              (0x7UL << ADC_CFGR_DISCNUM_Pos)      /*!< 0x000E0000 */

+#define ADC_CFGR_DISCNUM                  ADC_CFGR_DISCNUM_Msk                 /*!< ADC Discontinuous mode channel count */

+#define ADC_CFGR_DISCNUM_0                (0x1UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00020000 */

+#define ADC_CFGR_DISCNUM_1                (0x2UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00040000 */

+#define ADC_CFGR_DISCNUM_2                (0x4UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00080000 */

+

+#define ADC_CFGR_JDISCEN_Pos              (20U)

+#define ADC_CFGR_JDISCEN_Msk              (0x1UL << ADC_CFGR_JDISCEN_Pos)      /*!< 0x00100000 */

+#define ADC_CFGR_JDISCEN                  ADC_CFGR_JDISCEN_Msk                 /*!< ADC Discontinuous mode on injected channels */

+#define ADC_CFGR_JQM_Pos                  (21U)

+#define ADC_CFGR_JQM_Msk                  (0x1UL << ADC_CFGR_JQM_Pos)          /*!< 0x00200000 */

+#define ADC_CFGR_JQM                      ADC_CFGR_JQM_Msk                     /*!< ADC JSQR Queue mode */

+#define ADC_CFGR_AWD1SGL_Pos              (22U)

+#define ADC_CFGR_AWD1SGL_Msk              (0x1UL << ADC_CFGR_AWD1SGL_Pos)      /*!< 0x00400000 */

+#define ADC_CFGR_AWD1SGL                  ADC_CFGR_AWD1SGL_Msk                 /*!< Enable the watchdog 1 on a single channel or on all channels */

+#define ADC_CFGR_AWD1EN_Pos               (23U)

+#define ADC_CFGR_AWD1EN_Msk               (0x1UL << ADC_CFGR_AWD1EN_Pos)       /*!< 0x00800000 */

+#define ADC_CFGR_AWD1EN                   ADC_CFGR_AWD1EN_Msk                  /*!< ADC Analog watchdog 1 enable on regular Channels */

+#define ADC_CFGR_JAWD1EN_Pos              (24U)

+#define ADC_CFGR_JAWD1EN_Msk              (0x1UL << ADC_CFGR_JAWD1EN_Pos)      /*!< 0x01000000 */

+#define ADC_CFGR_JAWD1EN                  ADC_CFGR_JAWD1EN_Msk                 /*!< ADC Analog watchdog 1 enable on injected Channels */

+#define ADC_CFGR_JAUTO_Pos                (25U)

+#define ADC_CFGR_JAUTO_Msk                (0x1UL << ADC_CFGR_JAUTO_Pos)        /*!< 0x02000000 */

+#define ADC_CFGR_JAUTO                    ADC_CFGR_JAUTO_Msk                   /*!< ADC Automatic injected group conversion */

+

+#define ADC_CFGR_AWD1CH_Pos               (26U)

+#define ADC_CFGR_AWD1CH_Msk               (0x1FUL << ADC_CFGR_AWD1CH_Pos)      /*!< 0x7C000000 */

+#define ADC_CFGR_AWD1CH                   ADC_CFGR_AWD1CH_Msk                  /*!< ADC Analog watchdog 1 Channel selection */

+#define ADC_CFGR_AWD1CH_0                 (0x01UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x04000000 */

+#define ADC_CFGR_AWD1CH_1                 (0x02UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x08000000 */

+#define ADC_CFGR_AWD1CH_2                 (0x04UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x10000000 */

+#define ADC_CFGR_AWD1CH_3                 (0x08UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x20000000 */

+#define ADC_CFGR_AWD1CH_4                 (0x10UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x40000000 */

+

+#define ADC_CFGR_JQDIS_Pos                (31U)

+#define ADC_CFGR_JQDIS_Msk                (0x1UL << ADC_CFGR_JQDIS_Pos)        /*!< 0x80000000 */

+#define ADC_CFGR_JQDIS                    ADC_CFGR_JQDIS_Msk                   /*!< ADC Injected queue disable */

+

+/********************  Bit definition for ADC_CFGR2 register  ********************/

+#define ADC_CFGR2_ROVSE_Pos               (0U)

+#define ADC_CFGR2_ROVSE_Msk               (0x1UL << ADC_CFGR2_ROVSE_Pos)       /*!< 0x00000001 */

+#define ADC_CFGR2_ROVSE                   ADC_CFGR2_ROVSE_Msk                  /*!< ADC Regular group oversampler enable */

+#define ADC_CFGR2_JOVSE_Pos               (1U)

+#define ADC_CFGR2_JOVSE_Msk               (0x1UL << ADC_CFGR2_JOVSE_Pos)       /*!< 0x00000002 */

+#define ADC_CFGR2_JOVSE                   ADC_CFGR2_JOVSE_Msk                  /*!< ADC Injected group oversampler enable */

+

+#define ADC_CFGR2_OVSS_Pos                (5U)

+#define ADC_CFGR2_OVSS_Msk                (0xFUL << ADC_CFGR2_OVSS_Pos)        /*!< 0x000001E0 */

+#define ADC_CFGR2_OVSS                    ADC_CFGR2_OVSS_Msk                   /*!< ADC Regular Oversampling shift */

+#define ADC_CFGR2_OVSS_0                  (0x1UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000020 */

+#define ADC_CFGR2_OVSS_1                  (0x2UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000040 */

+#define ADC_CFGR2_OVSS_2                  (0x4UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000080 */

+#define ADC_CFGR2_OVSS_3                  (0x8UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000100 */

+

+#define ADC_CFGR2_TROVS_Pos               (9U)

+#define ADC_CFGR2_TROVS_Msk               (0x1UL << ADC_CFGR2_TROVS_Pos)       /*!< 0x00000200 */

+#define ADC_CFGR2_TROVS                   ADC_CFGR2_TROVS_Msk                  /*!< ADC Triggered regular Oversampling */

+#define ADC_CFGR2_ROVSM_Pos               (10U)

+#define ADC_CFGR2_ROVSM_Msk               (0x1UL << ADC_CFGR2_ROVSM_Pos)       /*!< 0x00000400 */

+#define ADC_CFGR2_ROVSM                   ADC_CFGR2_ROVSM_Msk                  /*!< ADC Regular oversampling mode */

+

+#define ADC_CFGR2_RSHIFT1_Pos             (11U)

+#define ADC_CFGR2_RSHIFT1_Msk             (0x1UL << ADC_CFGR2_RSHIFT1_Pos)     /*!< 0x00000800 */

+#define ADC_CFGR2_RSHIFT1                 ADC_CFGR2_RSHIFT1_Msk                /*!< ADC Right-shift data after Offset 1 correction */

+#define ADC_CFGR2_RSHIFT2_Pos             (12U)

+#define ADC_CFGR2_RSHIFT2_Msk             (0x1UL << ADC_CFGR2_RSHIFT2_Pos)     /*!< 0x00001000 */

+#define ADC_CFGR2_RSHIFT2                 ADC_CFGR2_RSHIFT2_Msk                /*!< ADC Right-shift data after Offset 2 correction */

+#define ADC_CFGR2_RSHIFT3_Pos             (13U)

+#define ADC_CFGR2_RSHIFT3_Msk             (0x1UL << ADC_CFGR2_RSHIFT3_Pos)     /*!< 0x00002000 */

+#define ADC_CFGR2_RSHIFT3                 ADC_CFGR2_RSHIFT3_Msk                /*!< ADC Right-shift data after Offset 3 correction */

+#define ADC_CFGR2_RSHIFT4_Pos             (14U)

+#define ADC_CFGR2_RSHIFT4_Msk             (0x1UL << ADC_CFGR2_RSHIFT4_Pos)     /*!< 0x00004000 */

+#define ADC_CFGR2_RSHIFT4                 ADC_CFGR2_RSHIFT4_Msk                /*!< ADC Right-shift data after Offset 4 correction */

+

+#define ADC_CFGR2_OVSR_Pos                (16U)

+#define ADC_CFGR2_OVSR_Msk                (0x3FFUL << ADC_CFGR2_OVSR_Pos)      /*!< 0x03FF0000 */

+#define ADC_CFGR2_OVSR                    ADC_CFGR2_OVSR_Msk                   /*!< ADC oversampling Ratio */

+#define ADC_CFGR2_OVSR_0                  (0x001UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00010000 */

+#define ADC_CFGR2_OVSR_1                  (0x002UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00020000 */

+#define ADC_CFGR2_OVSR_2                  (0x004UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00040000 */

+#define ADC_CFGR2_OVSR_3                  (0x008UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00080000 */

+#define ADC_CFGR2_OVSR_4                  (0x010UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00100000 */

+#define ADC_CFGR2_OVSR_5                  (0x020UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00200000 */

+#define ADC_CFGR2_OVSR_6                  (0x040UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00400000 */

+#define ADC_CFGR2_OVSR_7                  (0x080UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00800000 */

+#define ADC_CFGR2_OVSR_8                  (0x100UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x01000000 */

+#define ADC_CFGR2_OVSR_9                  (0x200UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x02000000 */

+

+#define ADC_CFGR2_LSHIFT_Pos              (28U)

+#define ADC_CFGR2_LSHIFT_Msk              (0xFUL << ADC_CFGR2_LSHIFT_Pos)      /*!< 0xF0000000 */

+#define ADC_CFGR2_LSHIFT                  ADC_CFGR2_LSHIFT_Msk                 /*!< ADC Left shift factor */

+#define ADC_CFGR2_LSHIFT_0                (0x1UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x10000000 */

+#define ADC_CFGR2_LSHIFT_1                (0x2UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x20000000 */

+#define ADC_CFGR2_LSHIFT_2                (0x4UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x40000000 */

+#define ADC_CFGR2_LSHIFT_3                (0x8UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_SMPR1 register  ********************/

+#define ADC_SMPR1_SMP0_Pos                (0U)

+#define ADC_SMPR1_SMP0_Msk                (0x7UL << ADC_SMPR1_SMP0_Pos)        /*!< 0x00000007 */

+#define ADC_SMPR1_SMP0                    ADC_SMPR1_SMP0_Msk                   /*!< ADC Channel 0 Sampling time selection  */

+#define ADC_SMPR1_SMP0_0                  (0x1UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000001 */

+#define ADC_SMPR1_SMP0_1                  (0x2UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000002 */

+#define ADC_SMPR1_SMP0_2                  (0x4UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000004 */

+

+#define ADC_SMPR1_SMP1_Pos                (3U)

+#define ADC_SMPR1_SMP1_Msk                (0x7UL << ADC_SMPR1_SMP1_Pos)        /*!< 0x00000038 */

+#define ADC_SMPR1_SMP1                    ADC_SMPR1_SMP1_Msk                   /*!< ADC Channel 1 Sampling time selection  */

+#define ADC_SMPR1_SMP1_0                  (0x1UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000008 */

+#define ADC_SMPR1_SMP1_1                  (0x2UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000010 */

+#define ADC_SMPR1_SMP1_2                  (0x4UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000020 */

+

+#define ADC_SMPR1_SMP2_Pos                (6U)

+#define ADC_SMPR1_SMP2_Msk                (0x7UL << ADC_SMPR1_SMP2_Pos)        /*!< 0x000001C0 */

+#define ADC_SMPR1_SMP2                    ADC_SMPR1_SMP2_Msk                   /*!< ADC Channel 2 Sampling time selection  */

+#define ADC_SMPR1_SMP2_0                  (0x1UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000040 */

+#define ADC_SMPR1_SMP2_1                  (0x2UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000080 */

+#define ADC_SMPR1_SMP2_2                  (0x4UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000100 */

+

+#define ADC_SMPR1_SMP3_Pos                (9U)

+#define ADC_SMPR1_SMP3_Msk                (0x7UL << ADC_SMPR1_SMP3_Pos)        /*!< 0x00000E00 */

+#define ADC_SMPR1_SMP3                    ADC_SMPR1_SMP3_Msk                   /*!< ADC Channel 3 Sampling time selection  */

+#define ADC_SMPR1_SMP3_0                  (0x1UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000200 */

+#define ADC_SMPR1_SMP3_1                  (0x2UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000400 */

+#define ADC_SMPR1_SMP3_2                  (0x4UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000800 */

+

+#define ADC_SMPR1_SMP4_Pos                (12U)

+#define ADC_SMPR1_SMP4_Msk                (0x7UL << ADC_SMPR1_SMP4_Pos)        /*!< 0x00007000 */

+#define ADC_SMPR1_SMP4                    ADC_SMPR1_SMP4_Msk                   /*!< ADC Channel 4 Sampling time selection  */

+#define ADC_SMPR1_SMP4_0                  (0x1UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00001000 */

+#define ADC_SMPR1_SMP4_1                  (0x2UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00002000 */

+#define ADC_SMPR1_SMP4_2                  (0x4UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00004000 */

+

+#define ADC_SMPR1_SMP5_Pos                (15U)

+#define ADC_SMPR1_SMP5_Msk                (0x7UL << ADC_SMPR1_SMP5_Pos)        /*!< 0x00038000 */

+#define ADC_SMPR1_SMP5                    ADC_SMPR1_SMP5_Msk                   /*!< ADC Channel 5 Sampling time selection  */

+#define ADC_SMPR1_SMP5_0                  (0x1UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00008000 */

+#define ADC_SMPR1_SMP5_1                  (0x2UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00010000 */

+#define ADC_SMPR1_SMP5_2                  (0x4UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00020000 */

+

+#define ADC_SMPR1_SMP6_Pos                (18U)

+#define ADC_SMPR1_SMP6_Msk                (0x7UL << ADC_SMPR1_SMP6_Pos)        /*!< 0x001C0000 */

+#define ADC_SMPR1_SMP6                    ADC_SMPR1_SMP6_Msk                   /*!< ADC Channel 6 Sampling time selection  */

+#define ADC_SMPR1_SMP6_0                  (0x1UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00040000 */

+#define ADC_SMPR1_SMP6_1                  (0x2UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00080000 */

+#define ADC_SMPR1_SMP6_2                  (0x4UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00100000 */

+

+#define ADC_SMPR1_SMP7_Pos                (21U)

+#define ADC_SMPR1_SMP7_Msk                (0x7UL << ADC_SMPR1_SMP7_Pos)        /*!< 0x00E00000 */

+#define ADC_SMPR1_SMP7                    ADC_SMPR1_SMP7_Msk                   /*!< ADC Channel 7 Sampling time selection  */

+#define ADC_SMPR1_SMP7_0                  (0x1UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00200000 */

+#define ADC_SMPR1_SMP7_1                  (0x2UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00400000 */

+#define ADC_SMPR1_SMP7_2                  (0x4UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00800000 */

+

+#define ADC_SMPR1_SMP8_Pos                (24U)

+#define ADC_SMPR1_SMP8_Msk                (0x7UL << ADC_SMPR1_SMP8_Pos)        /*!< 0x07000000 */

+#define ADC_SMPR1_SMP8                    ADC_SMPR1_SMP8_Msk                   /*!< ADC Channel 8 Sampling time selection  */

+#define ADC_SMPR1_SMP8_0                  (0x1UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x01000000 */

+#define ADC_SMPR1_SMP8_1                  (0x2UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x02000000 */

+#define ADC_SMPR1_SMP8_2                  (0x4UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x04000000 */

+

+#define ADC_SMPR1_SMP9_Pos                (27U)

+#define ADC_SMPR1_SMP9_Msk                (0x7UL << ADC_SMPR1_SMP9_Pos)        /*!< 0x38000000 */

+#define ADC_SMPR1_SMP9                    ADC_SMPR1_SMP9_Msk                   /*!< ADC Channel 9 Sampling time selection  */

+#define ADC_SMPR1_SMP9_0                  (0x1UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x08000000 */

+#define ADC_SMPR1_SMP9_1                  (0x2UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x10000000 */

+#define ADC_SMPR1_SMP9_2                  (0x4UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x20000000 */

+

+/********************  Bit definition for ADC_SMPR2 register  ********************/

+#define ADC_SMPR2_SMP10_Pos               (0U)

+#define ADC_SMPR2_SMP10_Msk               (0x7UL << ADC_SMPR2_SMP10_Pos)       /*!< 0x00000007 */

+#define ADC_SMPR2_SMP10                   ADC_SMPR2_SMP10_Msk                  /*!< ADC Channel 10 Sampling time selection  */

+#define ADC_SMPR2_SMP10_0                 (0x1UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000001 */

+#define ADC_SMPR2_SMP10_1                 (0x2UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000002 */

+#define ADC_SMPR2_SMP10_2                 (0x4UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000004 */

+

+#define ADC_SMPR2_SMP11_Pos               (3U)

+#define ADC_SMPR2_SMP11_Msk               (0x7UL << ADC_SMPR2_SMP11_Pos)       /*!< 0x00000038 */

+#define ADC_SMPR2_SMP11                   ADC_SMPR2_SMP11_Msk                  /*!< ADC Channel 11 Sampling time selection  */

+#define ADC_SMPR2_SMP11_0                 (0x1UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000008 */

+#define ADC_SMPR2_SMP11_1                 (0x2UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000010 */

+#define ADC_SMPR2_SMP11_2                 (0x4UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000020 */

+

+#define ADC_SMPR2_SMP12_Pos               (6U)

+#define ADC_SMPR2_SMP12_Msk               (0x7UL << ADC_SMPR2_SMP12_Pos)       /*!< 0x000001C0 */

+#define ADC_SMPR2_SMP12                   ADC_SMPR2_SMP12_Msk                  /*!< ADC Channel 12 Sampling time selection  */

+#define ADC_SMPR2_SMP12_0                 (0x1UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000040 */

+#define ADC_SMPR2_SMP12_1                 (0x2UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000080 */

+#define ADC_SMPR2_SMP12_2                 (0x4UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000100 */

+

+#define ADC_SMPR2_SMP13_Pos               (9U)

+#define ADC_SMPR2_SMP13_Msk               (0x7UL << ADC_SMPR2_SMP13_Pos)       /*!< 0x00000E00 */

+#define ADC_SMPR2_SMP13                   ADC_SMPR2_SMP13_Msk                  /*!< ADC Channel 13 Sampling time selection  */

+#define ADC_SMPR2_SMP13_0                 (0x1UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000200 */

+#define ADC_SMPR2_SMP13_1                 (0x2UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000400 */

+#define ADC_SMPR2_SMP13_2                 (0x4UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000800 */

+

+#define ADC_SMPR2_SMP14_Pos               (12U)

+#define ADC_SMPR2_SMP14_Msk               (0x7UL << ADC_SMPR2_SMP14_Pos)       /*!< 0x00007000 */

+#define ADC_SMPR2_SMP14                   ADC_SMPR2_SMP14_Msk                  /*!< ADC Channel 14 Sampling time selection  */

+#define ADC_SMPR2_SMP14_0                 (0x1UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00001000 */

+#define ADC_SMPR2_SMP14_1                 (0x2UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00002000 */

+#define ADC_SMPR2_SMP14_2                 (0x4UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00004000 */

+

+#define ADC_SMPR2_SMP15_Pos               (15U)

+#define ADC_SMPR2_SMP15_Msk               (0x7UL << ADC_SMPR2_SMP15_Pos)       /*!< 0x00038000 */

+#define ADC_SMPR2_SMP15                   ADC_SMPR2_SMP15_Msk                  /*!< ADC Channel 15 Sampling time selection  */

+#define ADC_SMPR2_SMP15_0                 (0x1UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00008000 */

+#define ADC_SMPR2_SMP15_1                 (0x2UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00010000 */

+#define ADC_SMPR2_SMP15_2                 (0x4UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00020000 */

+

+#define ADC_SMPR2_SMP16_Pos               (18U)

+#define ADC_SMPR2_SMP16_Msk               (0x7UL << ADC_SMPR2_SMP16_Pos)       /*!< 0x001C0000 */

+#define ADC_SMPR2_SMP16                   ADC_SMPR2_SMP16_Msk                  /*!< ADC Channel 16 Sampling time selection  */

+#define ADC_SMPR2_SMP16_0                 (0x1UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00040000 */

+#define ADC_SMPR2_SMP16_1                 (0x2UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00080000 */

+#define ADC_SMPR2_SMP16_2                 (0x4UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00100000 */

+

+#define ADC_SMPR2_SMP17_Pos               (21U)

+#define ADC_SMPR2_SMP17_Msk               (0x7UL << ADC_SMPR2_SMP17_Pos)       /*!< 0x00E00000 */

+#define ADC_SMPR2_SMP17                   ADC_SMPR2_SMP17_Msk                  /*!< ADC Channel 17 Sampling time selection  */

+#define ADC_SMPR2_SMP17_0                 (0x1UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00200000 */

+#define ADC_SMPR2_SMP17_1                 (0x2UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00400000 */

+#define ADC_SMPR2_SMP17_2                 (0x4UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00800000 */

+

+#define ADC_SMPR2_SMP18_Pos               (24U)

+#define ADC_SMPR2_SMP18_Msk               (0x7UL << ADC_SMPR2_SMP18_Pos)       /*!< 0x07000000 */

+#define ADC_SMPR2_SMP18                   ADC_SMPR2_SMP18_Msk                  /*!< ADC Channel 18 Sampling time selection  */

+#define ADC_SMPR2_SMP18_0                 (0x1UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x01000000 */

+#define ADC_SMPR2_SMP18_1                 (0x2UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x02000000 */

+#define ADC_SMPR2_SMP18_2                 (0x4UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x04000000 */

+

+#define ADC_SMPR2_SMP19_Pos               (27U)

+#define ADC_SMPR2_SMP19_Msk               (0x7UL << ADC_SMPR2_SMP19_Pos)       /*!< 0x38000000 */

+#define ADC_SMPR2_SMP19                   ADC_SMPR2_SMP19_Msk                  /*!< ADC Channel 19 Sampling time selection  */

+#define ADC_SMPR2_SMP19_0                 (0x1UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x08000000 */

+#define ADC_SMPR2_SMP19_1                 (0x2UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x10000000 */

+#define ADC_SMPR2_SMP19_2                 (0x4UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x20000000 */

+

+/********************  Bit definition for ADC_PCSEL register  ********************/

+#define ADC_PCSEL_PCSEL_Pos               (0U)

+#define ADC_PCSEL_PCSEL_Msk               (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)   /*!< 0x000FFFFF */

+#define ADC_PCSEL_PCSEL                   ADC_PCSEL_PCSEL_Msk                  /*!< ADC pre channel selection */

+#define ADC_PCSEL_PCSEL_0                 (0x00001UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */

+#define ADC_PCSEL_PCSEL_1                 (0x00002UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */

+#define ADC_PCSEL_PCSEL_2                 (0x00004UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */

+#define ADC_PCSEL_PCSEL_3                 (0x00008UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */

+#define ADC_PCSEL_PCSEL_4                 (0x00010UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */

+#define ADC_PCSEL_PCSEL_5                 (0x00020UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */

+#define ADC_PCSEL_PCSEL_6                 (0x00040UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */

+#define ADC_PCSEL_PCSEL_7                 (0x00080UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */

+#define ADC_PCSEL_PCSEL_8                 (0x00100UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */

+#define ADC_PCSEL_PCSEL_9                 (0x00200UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */

+#define ADC_PCSEL_PCSEL_10                (0x00400UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */

+#define ADC_PCSEL_PCSEL_11                (0x00800UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */

+#define ADC_PCSEL_PCSEL_12                (0x01000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */

+#define ADC_PCSEL_PCSEL_13                (0x02000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */

+#define ADC_PCSEL_PCSEL_14                (0x04000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */

+#define ADC_PCSEL_PCSEL_15                (0x08000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */

+#define ADC_PCSEL_PCSEL_16                (0x10000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */

+#define ADC_PCSEL_PCSEL_17                (0x20000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */

+#define ADC_PCSEL_PCSEL_18                (0x40000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */

+#define ADC_PCSEL_PCSEL_19                (0x80000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00080000 */

+

+/*****************  Bit definition for ADC_LTR1, 2, 3 registers *****************/

+#define ADC_LTR_LT_Pos                    (0U)

+#define ADC_LTR_LT_Msk                    (0x3FFFFFFUL << ADC_LTR_LT_Pos)      /*!< 0x03FFFFFF */

+#define ADC_LTR_LT                        ADC_LTR_LT_Msk                       /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */

+

+/*****************  Bit definition for ADC_HTR1, 2, 3 registers  ****************/

+#define ADC_HTR_HT_Pos                    (0U)

+#define ADC_HTR_HT_Msk                    (0x3FFFFFFUL << ADC_HTR_HT_Pos)      /*!< 0x03FFFFFF */

+#define ADC_HTR_HT                        ADC_HTR_HT_Msk                       /*!< ADC Analog watchdog 1,2 and 3 higher threshold */

+

+

+/********************  Bit definition for ADC_SQR1 register  ********************/

+#define ADC_SQR1_L_Pos                    (0U)

+#define ADC_SQR1_L_Msk                    (0xFUL << ADC_SQR1_L_Pos)            /*!< 0x0000000F */

+#define ADC_SQR1_L                        ADC_SQR1_L_Msk                       /*!< ADC regular channel sequence lenght */

+#define ADC_SQR1_L_0                      (0x1UL << ADC_SQR1_L_Pos)             /*!< 0x00000001 */

+#define ADC_SQR1_L_1                      (0x2UL << ADC_SQR1_L_Pos)             /*!< 0x00000002 */

+#define ADC_SQR1_L_2                      (0x4UL << ADC_SQR1_L_Pos)             /*!< 0x00000004 */

+#define ADC_SQR1_L_3                      (0x8UL << ADC_SQR1_L_Pos)             /*!< 0x00000008 */

+

+#define ADC_SQR1_SQ1_Pos                  (6U)

+#define ADC_SQR1_SQ1_Msk                  (0x1FUL << ADC_SQR1_SQ1_Pos)         /*!< 0x000007C0 */

+#define ADC_SQR1_SQ1                      ADC_SQR1_SQ1_Msk                     /*!< ADC 1st conversion in regular sequence */

+#define ADC_SQR1_SQ1_0                    (0x01UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000040 */

+#define ADC_SQR1_SQ1_1                    (0x02UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000080 */

+#define ADC_SQR1_SQ1_2                    (0x04UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000100 */

+#define ADC_SQR1_SQ1_3                    (0x08UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000200 */

+#define ADC_SQR1_SQ1_4                    (0x10UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000400 */

+

+#define ADC_SQR1_SQ2_Pos                  (12U)

+#define ADC_SQR1_SQ2_Msk                  (0x1FUL << ADC_SQR1_SQ2_Pos)         /*!< 0x0001F000 */

+#define ADC_SQR1_SQ2                      ADC_SQR1_SQ2_Msk                     /*!< ADC 2nd conversion in regular sequence */

+#define ADC_SQR1_SQ2_0                    (0x01UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00001000 */

+#define ADC_SQR1_SQ2_1                    (0x02UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00002000 */

+#define ADC_SQR1_SQ2_2                    (0x04UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00004000 */

+#define ADC_SQR1_SQ2_3                    (0x08UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00008000 */

+#define ADC_SQR1_SQ2_4                    (0x10UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00010000 */

+

+#define ADC_SQR1_SQ3_Pos                  (18U)

+#define ADC_SQR1_SQ3_Msk                  (0x1FUL << ADC_SQR1_SQ3_Pos)         /*!< 0x007C0000 */

+#define ADC_SQR1_SQ3                      ADC_SQR1_SQ3_Msk                     /*!< ADC 3rd conversion in regular sequence */

+#define ADC_SQR1_SQ3_0                    (0x01UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00040000 */

+#define ADC_SQR1_SQ3_1                    (0x02UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00080000 */

+#define ADC_SQR1_SQ3_2                    (0x04UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00100000 */

+#define ADC_SQR1_SQ3_3                    (0x08UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00200000 */

+#define ADC_SQR1_SQ3_4                    (0x10UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00400000 */

+

+#define ADC_SQR1_SQ4_Pos                  (24U)

+#define ADC_SQR1_SQ4_Msk                  (0x1FUL << ADC_SQR1_SQ4_Pos)         /*!< 0x1F000000 */

+#define ADC_SQR1_SQ4                      ADC_SQR1_SQ4_Msk                     /*!< ADC 4th conversion in regular sequence */

+#define ADC_SQR1_SQ4_0                    (0x01UL << ADC_SQR1_SQ4_Pos)          /*!< 0x01000000 */

+#define ADC_SQR1_SQ4_1                    (0x02UL << ADC_SQR1_SQ4_Pos)          /*!< 0x02000000 */

+#define ADC_SQR1_SQ4_2                    (0x04UL << ADC_SQR1_SQ4_Pos)          /*!< 0x04000000 */

+#define ADC_SQR1_SQ4_3                    (0x08UL << ADC_SQR1_SQ4_Pos)          /*!< 0x08000000 */

+#define ADC_SQR1_SQ4_4                    (0x10UL << ADC_SQR1_SQ4_Pos)          /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR2 register  ********************/

+#define ADC_SQR2_SQ5_Pos                  (0U)

+#define ADC_SQR2_SQ5_Msk                  (0x1FUL << ADC_SQR2_SQ5_Pos)         /*!< 0x0000001F */

+#define ADC_SQR2_SQ5                      ADC_SQR2_SQ5_Msk                     /*!< ADC 5th conversion in regular sequence */

+#define ADC_SQR2_SQ5_0                    (0x01UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000001 */

+#define ADC_SQR2_SQ5_1                    (0x02UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000002 */

+#define ADC_SQR2_SQ5_2                    (0x04UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000004 */

+#define ADC_SQR2_SQ5_3                    (0x08UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000008 */

+#define ADC_SQR2_SQ5_4                    (0x10UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000010 */

+

+#define ADC_SQR2_SQ6_Pos                  (6U)

+#define ADC_SQR2_SQ6_Msk                  (0x1FUL << ADC_SQR2_SQ6_Pos)         /*!< 0x000007C0 */

+#define ADC_SQR2_SQ6                      ADC_SQR2_SQ6_Msk                     /*!< ADC 6th conversion in regular sequence */

+#define ADC_SQR2_SQ6_0                    (0x01UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000040 */

+#define ADC_SQR2_SQ6_1                    (0x02UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000080 */

+#define ADC_SQR2_SQ6_2                    (0x04UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000100 */

+#define ADC_SQR2_SQ6_3                    (0x08UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000200 */

+#define ADC_SQR2_SQ6_4                    (0x10UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000400 */

+

+#define ADC_SQR2_SQ7_Pos                  (12U)

+#define ADC_SQR2_SQ7_Msk                  (0x1FUL << ADC_SQR2_SQ7_Pos)         /*!< 0x0001F000 */

+#define ADC_SQR2_SQ7                      ADC_SQR2_SQ7_Msk                     /*!< ADC 7th conversion in regular sequence */

+#define ADC_SQR2_SQ7_0                    (0x01UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00001000 */

+#define ADC_SQR2_SQ7_1                    (0x02UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00002000 */

+#define ADC_SQR2_SQ7_2                    (0x04UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00004000 */

+#define ADC_SQR2_SQ7_3                    (0x08UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00008000 */

+#define ADC_SQR2_SQ7_4                    (0x10UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00010000 */

+

+#define ADC_SQR2_SQ8_Pos                  (18U)

+#define ADC_SQR2_SQ8_Msk                  (0x1FUL << ADC_SQR2_SQ8_Pos)         /*!< 0x007C0000 */

+#define ADC_SQR2_SQ8                      ADC_SQR2_SQ8_Msk                     /*!< ADC 8th conversion in regular sequence */

+#define ADC_SQR2_SQ8_0                    (0x01UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00040000 */

+#define ADC_SQR2_SQ8_1                    (0x02UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00080000 */

+#define ADC_SQR2_SQ8_2                    (0x04UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00100000 */

+#define ADC_SQR2_SQ8_3                    (0x08UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00200000 */

+#define ADC_SQR2_SQ8_4                    (0x10UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00400000 */

+

+#define ADC_SQR2_SQ9_Pos                  (24U)

+#define ADC_SQR2_SQ9_Msk                  (0x1FUL << ADC_SQR2_SQ9_Pos)         /*!< 0x1F000000 */

+#define ADC_SQR2_SQ9                      ADC_SQR2_SQ9_Msk                     /*!< ADC 9th conversion in regular sequence */

+#define ADC_SQR2_SQ9_0                    (0x01UL << ADC_SQR2_SQ9_Pos)          /*!< 0x01000000 */

+#define ADC_SQR2_SQ9_1                    (0x02UL << ADC_SQR2_SQ9_Pos)          /*!< 0x02000000 */

+#define ADC_SQR2_SQ9_2                    (0x04UL << ADC_SQR2_SQ9_Pos)          /*!< 0x04000000 */

+#define ADC_SQR2_SQ9_3                    (0x08UL << ADC_SQR2_SQ9_Pos)          /*!< 0x08000000 */

+#define ADC_SQR2_SQ9_4                    (0x10UL << ADC_SQR2_SQ9_Pos)          /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR3 register  ********************/

+#define ADC_SQR3_SQ10_Pos                 (0U)

+#define ADC_SQR3_SQ10_Msk                 (0x1FUL << ADC_SQR3_SQ10_Pos)        /*!< 0x0000001F */

+#define ADC_SQR3_SQ10                     ADC_SQR3_SQ10_Msk                    /*!< ADC 10th conversion in regular sequence */

+#define ADC_SQR3_SQ10_0                   (0x01UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000001 */

+#define ADC_SQR3_SQ10_1                   (0x02UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000002 */

+#define ADC_SQR3_SQ10_2                   (0x04UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000004 */

+#define ADC_SQR3_SQ10_3                   (0x08UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000008 */

+#define ADC_SQR3_SQ10_4                   (0x10UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000010 */

+

+#define ADC_SQR3_SQ11_Pos                 (6U)

+#define ADC_SQR3_SQ11_Msk                 (0x1FUL << ADC_SQR3_SQ11_Pos)        /*!< 0x000007C0 */

+#define ADC_SQR3_SQ11                     ADC_SQR3_SQ11_Msk                    /*!< ADC 11th conversion in regular sequence */

+#define ADC_SQR3_SQ11_0                   (0x01UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000040 */

+#define ADC_SQR3_SQ11_1                   (0x02UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000080 */

+#define ADC_SQR3_SQ11_2                   (0x04UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000100 */

+#define ADC_SQR3_SQ11_3                   (0x08UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000200 */

+#define ADC_SQR3_SQ11_4                   (0x10UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000400 */

+

+#define ADC_SQR3_SQ12_Pos                 (12U)

+#define ADC_SQR3_SQ12_Msk                 (0x1FUL << ADC_SQR3_SQ12_Pos)        /*!< 0x0001F000 */

+#define ADC_SQR3_SQ12                     ADC_SQR3_SQ12_Msk                    /*!< ADC 12th conversion in regular sequence */

+#define ADC_SQR3_SQ12_0                   (0x01UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00001000 */

+#define ADC_SQR3_SQ12_1                   (0x02UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00002000 */

+#define ADC_SQR3_SQ12_2                   (0x04UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00004000 */

+#define ADC_SQR3_SQ12_3                   (0x08UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00008000 */

+#define ADC_SQR3_SQ12_4                   (0x10UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00010000 */

+

+#define ADC_SQR3_SQ13_Pos                 (18U)

+#define ADC_SQR3_SQ13_Msk                 (0x1FUL << ADC_SQR3_SQ13_Pos)        /*!< 0x007C0000 */

+#define ADC_SQR3_SQ13                     ADC_SQR3_SQ13_Msk                    /*!< ADC 13th conversion in regular sequence */

+#define ADC_SQR3_SQ13_0                   (0x01UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00040000 */

+#define ADC_SQR3_SQ13_1                   (0x02UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00080000 */

+#define ADC_SQR3_SQ13_2                   (0x04UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00100000 */

+#define ADC_SQR3_SQ13_3                   (0x08UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00200000 */

+#define ADC_SQR3_SQ13_4                   (0x10UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00400000 */

+

+#define ADC_SQR3_SQ14_Pos                 (24U)

+#define ADC_SQR3_SQ14_Msk                 (0x1FUL << ADC_SQR3_SQ14_Pos)        /*!< 0x1F000000 */

+#define ADC_SQR3_SQ14                     ADC_SQR3_SQ14_Msk                    /*!< ADC 14th conversion in regular sequence */

+#define ADC_SQR3_SQ14_0                   (0x01UL << ADC_SQR3_SQ14_Pos)         /*!< 0x01000000 */

+#define ADC_SQR3_SQ14_1                   (0x02UL << ADC_SQR3_SQ14_Pos)         /*!< 0x02000000 */

+#define ADC_SQR3_SQ14_2                   (0x04UL << ADC_SQR3_SQ14_Pos)         /*!< 0x04000000 */

+#define ADC_SQR3_SQ14_3                   (0x08UL << ADC_SQR3_SQ14_Pos)         /*!< 0x08000000 */

+#define ADC_SQR3_SQ14_4                   (0x10UL << ADC_SQR3_SQ14_Pos)         /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR4 register  ********************/

+#define ADC_SQR4_SQ15_Pos                 (0U)

+#define ADC_SQR4_SQ15_Msk                 (0x1FUL << ADC_SQR4_SQ15_Pos)        /*!< 0x0000001F */

+#define ADC_SQR4_SQ15                     ADC_SQR4_SQ15_Msk                    /*!< ADC 15th conversion in regular sequence */

+#define ADC_SQR4_SQ15_0                   (0x01UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000001 */

+#define ADC_SQR4_SQ15_1                   (0x02UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000002 */

+#define ADC_SQR4_SQ15_2                   (0x04UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000004 */

+#define ADC_SQR4_SQ15_3                   (0x08UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000008 */

+#define ADC_SQR4_SQ15_4                   (0x10UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000010 */

+

+#define ADC_SQR4_SQ16_Pos                 (6U)

+#define ADC_SQR4_SQ16_Msk                 (0x1FUL << ADC_SQR4_SQ16_Pos)        /*!< 0x000007C0 */

+#define ADC_SQR4_SQ16                     ADC_SQR4_SQ16_Msk                    /*!< ADC 16th conversion in regular sequence */

+#define ADC_SQR4_SQ16_0                   (0x01UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000040 */

+#define ADC_SQR4_SQ16_1                   (0x02UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000080 */

+#define ADC_SQR4_SQ16_2                   (0x04UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000100 */

+#define ADC_SQR4_SQ16_3                   (0x08UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000200 */

+#define ADC_SQR4_SQ16_4                   (0x10UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000400 */

+/********************  Bit definition for ADC_DR register  ********************/

+#define ADC_DR_RDATA_Pos                  (0U)

+#define ADC_DR_RDATA_Msk                  (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)   /*!< 0xFFFFFFFF */

+#define ADC_DR_RDATA                      ADC_DR_RDATA_Msk                     /*!< ADC regular Data converted */

+

+/********************  Bit definition for ADC_JSQR register  ********************/

+#define ADC_JSQR_JL_Pos                   (0U)

+#define ADC_JSQR_JL_Msk                   (0x3UL << ADC_JSQR_JL_Pos)           /*!< 0x00000003 */

+#define ADC_JSQR_JL                       ADC_JSQR_JL_Msk                      /*!< ADC injected channel sequence length */

+#define ADC_JSQR_JL_0                     (0x1UL << ADC_JSQR_JL_Pos)           /*!< 0x00000001 */

+#define ADC_JSQR_JL_1                     (0x2UL << ADC_JSQR_JL_Pos)           /*!< 0x00000002 */

+

+#define ADC_JSQR_JEXTSEL_Pos              (2U)

+#define ADC_JSQR_JEXTSEL_Msk              (0x1FUL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x0000007C */

+#define ADC_JSQR_JEXTSEL                  ADC_JSQR_JEXTSEL_Msk                 /*!< ADC external trigger selection for injected group */

+#define ADC_JSQR_JEXTSEL_0                (0x01UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000004 */

+#define ADC_JSQR_JEXTSEL_1                (0x02UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000008 */

+#define ADC_JSQR_JEXTSEL_2                (0x04UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000010 */

+#define ADC_JSQR_JEXTSEL_3                (0x08UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000020 */

+#define ADC_JSQR_JEXTSEL_4                (0x10UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000040 */

+

+#define ADC_JSQR_JEXTEN_Pos               (7U)

+#define ADC_JSQR_JEXTEN_Msk               (0x3UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000180 */

+#define ADC_JSQR_JEXTEN                   ADC_JSQR_JEXTEN_Msk                  /*!< ADC external trigger enable and polarity selection for injected channels */

+#define ADC_JSQR_JEXTEN_0                 (0x1UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000080 */

+#define ADC_JSQR_JEXTEN_1                 (0x2UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000100 */

+

+#define ADC_JSQR_JSQ1_Pos                 (9U)

+#define ADC_JSQR_JSQ1_Msk                 (0x1FUL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00003E00 */

+#define ADC_JSQR_JSQ1                     ADC_JSQR_JSQ1_Msk                    /*!< ADC 1st conversion in injected sequence */

+#define ADC_JSQR_JSQ1_0                   (0x01UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000200 */

+#define ADC_JSQR_JSQ1_1                   (0x02UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000400 */

+#define ADC_JSQR_JSQ1_2                   (0x04UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000800 */

+#define ADC_JSQR_JSQ1_3                   (0x08UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00001000 */

+#define ADC_JSQR_JSQ1_4                   (0x10UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00002000 */

+

+#define ADC_JSQR_JSQ2_Pos                 (15U)

+#define ADC_JSQR_JSQ2_Msk                 (0x1FUL << ADC_JSQR_JSQ2_Pos)        /*!< 0x000F8000 */

+#define ADC_JSQR_JSQ2                     ADC_JSQR_JSQ2_Msk                    /*!< ADC 2nd conversion in injected sequence */

+#define ADC_JSQR_JSQ2_0                   (0x01UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00008000 */

+#define ADC_JSQR_JSQ2_1                   (0x02UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00010000 */

+#define ADC_JSQR_JSQ2_2                   (0x04UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00020000 */

+#define ADC_JSQR_JSQ2_3                   (0x08UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00040000 */

+#define ADC_JSQR_JSQ2_4                   (0x10UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00080000 */

+

+#define ADC_JSQR_JSQ3_Pos                 (21U)

+#define ADC_JSQR_JSQ3_Msk                 (0x1FUL << ADC_JSQR_JSQ3_Pos)        /*!< 0x03E00000 */

+#define ADC_JSQR_JSQ3                     ADC_JSQR_JSQ3_Msk                    /*!< ADC 3rd conversion in injected sequence */

+#define ADC_JSQR_JSQ3_0                   (0x01UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00200000 */

+#define ADC_JSQR_JSQ3_1                   (0x02UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00400000 */

+#define ADC_JSQR_JSQ3_2                   (0x04UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00800000 */

+#define ADC_JSQR_JSQ3_3                   (0x08UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x01000000 */

+#define ADC_JSQR_JSQ3_4                   (0x10UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x02000000 */

+

+#define ADC_JSQR_JSQ4_Pos                 (27U)

+#define ADC_JSQR_JSQ4_Msk                 (0x1FUL << ADC_JSQR_JSQ4_Pos)        /*!< 0xF8000000 */

+#define ADC_JSQR_JSQ4                     ADC_JSQR_JSQ4_Msk                    /*!< ADC 4th conversion in injected sequence */

+#define ADC_JSQR_JSQ4_0                   (0x01UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x08000000 */

+#define ADC_JSQR_JSQ4_1                   (0x02UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x10000000 */

+#define ADC_JSQR_JSQ4_2                   (0x04UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x20000000 */

+#define ADC_JSQR_JSQ4_3                   (0x08UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x40000000 */

+#define ADC_JSQR_JSQ4_4                   (0x10UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_OFR1 register  ********************/

+#define ADC_OFR1_OFFSET1_Pos              (0U)

+#define ADC_OFR1_OFFSET1_Msk              (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR1_OFFSET1                  ADC_OFR1_OFFSET1_Msk                  /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */

+#define ADC_OFR1_OFFSET1_0                (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */

+#define ADC_OFR1_OFFSET1_1                (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */

+#define ADC_OFR1_OFFSET1_2                (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */

+#define ADC_OFR1_OFFSET1_3                (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */

+#define ADC_OFR1_OFFSET1_4                (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */

+#define ADC_OFR1_OFFSET1_5                (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */

+#define ADC_OFR1_OFFSET1_6                (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */

+#define ADC_OFR1_OFFSET1_7                (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */

+#define ADC_OFR1_OFFSET1_8                (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */

+#define ADC_OFR1_OFFSET1_9                (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */

+#define ADC_OFR1_OFFSET1_10               (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */

+#define ADC_OFR1_OFFSET1_11               (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */

+#define ADC_OFR1_OFFSET1_12               (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */

+#define ADC_OFR1_OFFSET1_13               (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */

+#define ADC_OFR1_OFFSET1_14               (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */

+#define ADC_OFR1_OFFSET1_15               (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */

+#define ADC_OFR1_OFFSET1_16               (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */

+#define ADC_OFR1_OFFSET1_17               (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */

+#define ADC_OFR1_OFFSET1_18               (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */

+#define ADC_OFR1_OFFSET1_19               (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */

+#define ADC_OFR1_OFFSET1_20               (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */

+#define ADC_OFR1_OFFSET1_21               (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */

+#define ADC_OFR1_OFFSET1_22               (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */

+#define ADC_OFR1_OFFSET1_23               (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */

+#define ADC_OFR1_OFFSET1_24               (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */

+#define ADC_OFR1_OFFSET1_25               (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR1_OFFSET1_CH_Pos           (26U)

+#define ADC_OFR1_OFFSET1_CH_Msk           (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR1_OFFSET1_CH               ADC_OFR1_OFFSET1_CH_Msk               /*!< ADC Channel selection for the data offset 1 */

+#define ADC_OFR1_OFFSET1_CH_0             (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR1_OFFSET1_CH_1             (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR1_OFFSET1_CH_2             (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR1_OFFSET1_CH_3             (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR1_OFFSET1_CH_4             (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR1_SSATE_Pos                (31U)

+#define ADC_OFR1_SSATE_Msk                (0x1UL << ADC_OFR1_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR1_SSATE                    ADC_OFR1_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR2 register  ********************/

+#define ADC_OFR2_OFFSET2_Pos              (0U)

+#define ADC_OFR2_OFFSET2_Msk              (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR2_OFFSET2                  ADC_OFR2_OFFSET2_Msk                  /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */

+#define ADC_OFR2_OFFSET2_0                (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */

+#define ADC_OFR2_OFFSET2_1                (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */

+#define ADC_OFR2_OFFSET2_2                (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */

+#define ADC_OFR2_OFFSET2_3                (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */

+#define ADC_OFR2_OFFSET2_4                (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */

+#define ADC_OFR2_OFFSET2_5                (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */

+#define ADC_OFR2_OFFSET2_6                (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */

+#define ADC_OFR2_OFFSET2_7                (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */

+#define ADC_OFR2_OFFSET2_8                (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */

+#define ADC_OFR2_OFFSET2_9                (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */

+#define ADC_OFR2_OFFSET2_10               (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */

+#define ADC_OFR2_OFFSET2_11               (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */

+#define ADC_OFR2_OFFSET2_12               (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */

+#define ADC_OFR2_OFFSET2_13               (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */

+#define ADC_OFR2_OFFSET2_14               (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */

+#define ADC_OFR2_OFFSET2_15               (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */

+#define ADC_OFR2_OFFSET2_16               (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */

+#define ADC_OFR2_OFFSET2_17               (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */

+#define ADC_OFR2_OFFSET2_18               (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */

+#define ADC_OFR2_OFFSET2_19               (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */

+#define ADC_OFR2_OFFSET2_20               (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */

+#define ADC_OFR2_OFFSET2_21               (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */

+#define ADC_OFR2_OFFSET2_22               (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */

+#define ADC_OFR2_OFFSET2_23               (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */

+#define ADC_OFR2_OFFSET2_24               (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */

+#define ADC_OFR2_OFFSET2_25               (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR2_OFFSET2_CH_Pos           (26U)

+#define ADC_OFR2_OFFSET2_CH_Msk           (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR2_OFFSET2_CH               ADC_OFR2_OFFSET2_CH_Msk               /*!< ADC Channel selection for the data offset 2 */

+#define ADC_OFR2_OFFSET2_CH_0             (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR2_OFFSET2_CH_1             (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR2_OFFSET2_CH_2             (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR2_OFFSET2_CH_3             (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR2_OFFSET2_CH_4             (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR2_SSATE_Pos                (31U)

+#define ADC_OFR2_SSATE_Msk                (0x1UL << ADC_OFR2_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR2_SSATE                    ADC_OFR2_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR3 register  ********************/

+#define ADC_OFR3_OFFSET3_Pos              (0U)

+#define ADC_OFR3_OFFSET3_Msk              (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR3_OFFSET3                  ADC_OFR3_OFFSET3_Msk                  /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */

+#define ADC_OFR3_OFFSET3_0                (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */

+#define ADC_OFR3_OFFSET3_1                (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */

+#define ADC_OFR3_OFFSET3_2                (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */

+#define ADC_OFR3_OFFSET3_3                (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */

+#define ADC_OFR3_OFFSET3_4                (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */

+#define ADC_OFR3_OFFSET3_5                (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */

+#define ADC_OFR3_OFFSET3_6                (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */

+#define ADC_OFR3_OFFSET3_7                (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */

+#define ADC_OFR3_OFFSET3_8                (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */

+#define ADC_OFR3_OFFSET3_9                (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */

+#define ADC_OFR3_OFFSET3_10               (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */

+#define ADC_OFR3_OFFSET3_11               (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */

+#define ADC_OFR3_OFFSET3_12               (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */

+#define ADC_OFR3_OFFSET3_13               (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */

+#define ADC_OFR3_OFFSET3_14               (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */

+#define ADC_OFR3_OFFSET3_15               (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */

+#define ADC_OFR3_OFFSET3_16               (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */

+#define ADC_OFR3_OFFSET3_17               (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */

+#define ADC_OFR3_OFFSET3_18               (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */

+#define ADC_OFR3_OFFSET3_19               (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */

+#define ADC_OFR3_OFFSET3_20               (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */

+#define ADC_OFR3_OFFSET3_21               (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */

+#define ADC_OFR3_OFFSET3_22               (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */

+#define ADC_OFR3_OFFSET3_23               (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */

+#define ADC_OFR3_OFFSET3_24               (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */

+#define ADC_OFR3_OFFSET3_25               (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR3_OFFSET3_CH_Pos           (26U)

+#define ADC_OFR3_OFFSET3_CH_Msk           (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR3_OFFSET3_CH               ADC_OFR3_OFFSET3_CH_Msk               /*!< ADC Channel selection for the data offset 3 */

+#define ADC_OFR3_OFFSET3_CH_0             (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR3_OFFSET3_CH_1             (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR3_OFFSET3_CH_2             (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR3_OFFSET3_CH_3             (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR3_OFFSET3_CH_4             (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR3_SSATE_Pos                (31U)

+#define ADC_OFR3_SSATE_Msk                (0x1UL << ADC_OFR3_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR3_SSATE                    ADC_OFR3_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR4 register  ********************/

+#define ADC_OFR4_OFFSET4_Pos              (0U)

+#define ADC_OFR4_OFFSET4_Msk              (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR4_OFFSET4                  ADC_OFR4_OFFSET4_Msk                  /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */

+#define ADC_OFR4_OFFSET4_0                (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */

+#define ADC_OFR4_OFFSET4_1                (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */

+#define ADC_OFR4_OFFSET4_2                (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */

+#define ADC_OFR4_OFFSET4_3                (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */

+#define ADC_OFR4_OFFSET4_4                (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */

+#define ADC_OFR4_OFFSET4_5                (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */

+#define ADC_OFR4_OFFSET4_6                (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */

+#define ADC_OFR4_OFFSET4_7                (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */

+#define ADC_OFR4_OFFSET4_8                (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */

+#define ADC_OFR4_OFFSET4_9                (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */

+#define ADC_OFR4_OFFSET4_10               (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */

+#define ADC_OFR4_OFFSET4_11               (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */

+#define ADC_OFR4_OFFSET4_12               (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */

+#define ADC_OFR4_OFFSET4_13               (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */

+#define ADC_OFR4_OFFSET4_14               (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */

+#define ADC_OFR4_OFFSET4_15               (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */

+#define ADC_OFR4_OFFSET4_16               (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */

+#define ADC_OFR4_OFFSET4_17               (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */

+#define ADC_OFR4_OFFSET4_18               (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */

+#define ADC_OFR4_OFFSET4_19               (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */

+#define ADC_OFR4_OFFSET4_20               (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */

+#define ADC_OFR4_OFFSET4_21               (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */

+#define ADC_OFR4_OFFSET4_22               (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */

+#define ADC_OFR4_OFFSET4_23               (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */

+#define ADC_OFR4_OFFSET4_24               (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */

+#define ADC_OFR4_OFFSET4_25               (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR4_OFFSET4_CH_Pos           (26U)

+#define ADC_OFR4_OFFSET4_CH_Msk           (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR4_OFFSET4_CH               ADC_OFR4_OFFSET4_CH_Msk               /*!< ADC Channel selection for the data offset 4 */

+#define ADC_OFR4_OFFSET4_CH_0             (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR4_OFFSET4_CH_1             (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR4_OFFSET4_CH_2             (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR4_OFFSET4_CH_3             (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR4_OFFSET4_CH_4             (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR4_SSATE_Pos                (31U)

+#define ADC_OFR4_SSATE_Msk                (0x1UL << ADC_OFR4_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR4_SSATE                    ADC_OFR4_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_JDR1 register  ********************/

+#define ADC_JDR1_JDATA_Pos                (0U)

+#define ADC_JDR1_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR1_JDATA                    ADC_JDR1_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR1_JDATA_0                  (0x00000001UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR1_JDATA_1                  (0x00000002UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR1_JDATA_2                  (0x00000004UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR1_JDATA_3                  (0x00000008UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR1_JDATA_4                  (0x00000010UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR1_JDATA_5                  (0x00000020UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR1_JDATA_6                  (0x00000040UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR1_JDATA_7                  (0x00000080UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR1_JDATA_8                  (0x00000100UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR1_JDATA_9                  (0x00000200UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR1_JDATA_10                 (0x00000400UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR1_JDATA_11                 (0x00000800UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR1_JDATA_12                 (0x00001000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR1_JDATA_13                 (0x00002000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR1_JDATA_14                 (0x00004000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR1_JDATA_15                 (0x00008000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR1_JDATA_16                 (0x00010000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR1_JDATA_17                 (0x00020000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR1_JDATA_18                 (0x00040000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR1_JDATA_19                 (0x00080000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR1_JDATA_20                 (0x00100000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR1_JDATA_21                 (0x00200000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR1_JDATA_22                 (0x00400000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR1_JDATA_23                 (0x00800000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR1_JDATA_24                 (0x01000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR1_JDATA_25                 (0x02000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR1_JDATA_26                 (0x04000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR1_JDATA_27                 (0x08000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR1_JDATA_28                 (0x10000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR1_JDATA_29                 (0x20000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR1_JDATA_30                 (0x40000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR1_JDATA_31                 (0x80000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR2 register  ********************/

+#define ADC_JDR2_JDATA_Pos                (0U)

+#define ADC_JDR2_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR2_JDATA                    ADC_JDR2_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR2_JDATA_0                  (0x00000001UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR2_JDATA_1                  (0x00000002UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR2_JDATA_2                  (0x00000004UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR2_JDATA_3                  (0x00000008UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR2_JDATA_4                  (0x00000010UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR2_JDATA_5                  (0x00000020UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR2_JDATA_6                  (0x00000040UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR2_JDATA_7                  (0x00000080UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR2_JDATA_8                  (0x00000100UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR2_JDATA_9                  (0x00000200UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR2_JDATA_10                 (0x00000400UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR2_JDATA_11                 (0x00000800UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR2_JDATA_12                 (0x00001000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR2_JDATA_13                 (0x00002000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR2_JDATA_14                 (0x00004000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR2_JDATA_15                 (0x00008000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR2_JDATA_16                 (0x00010000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR2_JDATA_17                 (0x00020000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR2_JDATA_18                 (0x00040000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR2_JDATA_19                 (0x00080000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR2_JDATA_20                 (0x00100000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR2_JDATA_21                 (0x00200000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR2_JDATA_22                 (0x00400000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR2_JDATA_23                 (0x00800000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR2_JDATA_24                 (0x01000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR2_JDATA_25                 (0x02000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR2_JDATA_26                 (0x04000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR2_JDATA_27                 (0x08000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR2_JDATA_28                 (0x10000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR2_JDATA_29                 (0x20000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR2_JDATA_30                 (0x40000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR2_JDATA_31                 (0x80000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR3 register  ********************/

+#define ADC_JDR3_JDATA_Pos                (0U)

+#define ADC_JDR3_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR3_JDATA                    ADC_JDR3_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR3_JDATA_0                  (0x00000001UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR3_JDATA_1                  (0x00000002UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR3_JDATA_2                  (0x00000004UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR3_JDATA_3                  (0x00000008UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR3_JDATA_4                  (0x00000010UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR3_JDATA_5                  (0x00000020UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR3_JDATA_6                  (0x00000040UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR3_JDATA_7                  (0x00000080UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR3_JDATA_8                  (0x00000100UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR3_JDATA_9                  (0x00000200UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR3_JDATA_10                 (0x00000400UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR3_JDATA_11                 (0x00000800UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR3_JDATA_12                 (0x00001000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR3_JDATA_13                 (0x00002000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR3_JDATA_14                 (0x00004000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR3_JDATA_15                 (0x00008000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR3_JDATA_16                 (0x00010000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR3_JDATA_17                 (0x00020000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR3_JDATA_18                 (0x00040000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR3_JDATA_19                 (0x00080000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR3_JDATA_20                 (0x00100000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR3_JDATA_21                 (0x00200000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR3_JDATA_22                 (0x00400000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR3_JDATA_23                 (0x00800000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR3_JDATA_24                 (0x01000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR3_JDATA_25                 (0x02000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR3_JDATA_26                 (0x04000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR3_JDATA_27                 (0x08000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR3_JDATA_28                 (0x10000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR3_JDATA_29                 (0x20000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR3_JDATA_30                 (0x40000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR3_JDATA_31                 (0x80000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR4 register  ********************/

+#define ADC_JDR4_JDATA_Pos                (0U)

+#define ADC_JDR4_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR4_JDATA                    ADC_JDR4_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR4_JDATA_0                  (0x00000001UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR4_JDATA_1                  (0x00000002UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR4_JDATA_2                  (0x00000004UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR4_JDATA_3                  (0x00000008UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR4_JDATA_4                  (0x00000010UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR4_JDATA_5                  (0x00000020UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR4_JDATA_6                  (0x00000040UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR4_JDATA_7                  (0x00000080UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR4_JDATA_8                  (0x00000100UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR4_JDATA_9                  (0x00000200UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR4_JDATA_10                 (0x00000400UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR4_JDATA_11                 (0x00000800UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR4_JDATA_12                 (0x00001000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR4_JDATA_13                 (0x00002000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR4_JDATA_14                 (0x00004000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR4_JDATA_15                 (0x00008000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR4_JDATA_16                 (0x00010000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR4_JDATA_17                 (0x00020000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR4_JDATA_18                 (0x00040000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR4_JDATA_19                 (0x00080000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR4_JDATA_20                 (0x00100000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR4_JDATA_21                 (0x00200000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR4_JDATA_22                 (0x00400000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR4_JDATA_23                 (0x00800000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR4_JDATA_24                 (0x01000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR4_JDATA_25                 (0x02000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR4_JDATA_26                 (0x04000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR4_JDATA_27                 (0x08000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR4_JDATA_28                 (0x10000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR4_JDATA_29                 (0x20000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR4_JDATA_30                 (0x40000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR4_JDATA_31                 (0x80000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_AWD2CR register  ********************/

+#define ADC_AWD2CR_AWD2CH_Pos             (0U)

+#define ADC_AWD2CR_AWD2CH_Msk             (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x000FFFFF */

+#define ADC_AWD2CR_AWD2CH                 ADC_AWD2CR_AWD2CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */

+#define ADC_AWD2CR_AWD2CH_0               (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000001 */

+#define ADC_AWD2CR_AWD2CH_1               (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000002 */

+#define ADC_AWD2CR_AWD2CH_2               (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000004 */

+#define ADC_AWD2CR_AWD2CH_3               (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000008 */

+#define ADC_AWD2CR_AWD2CH_4               (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000010 */

+#define ADC_AWD2CR_AWD2CH_5               (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000020 */

+#define ADC_AWD2CR_AWD2CH_6               (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000040 */

+#define ADC_AWD2CR_AWD2CH_7               (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000080 */

+#define ADC_AWD2CR_AWD2CH_8               (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000100 */

+#define ADC_AWD2CR_AWD2CH_9               (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000200 */

+#define ADC_AWD2CR_AWD2CH_10              (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000400 */

+#define ADC_AWD2CR_AWD2CH_11              (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000800 */

+#define ADC_AWD2CR_AWD2CH_12              (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00001000 */

+#define ADC_AWD2CR_AWD2CH_13              (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00002000 */

+#define ADC_AWD2CR_AWD2CH_14              (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00004000 */

+#define ADC_AWD2CR_AWD2CH_15              (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00008000 */

+#define ADC_AWD2CR_AWD2CH_16              (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00010000 */

+#define ADC_AWD2CR_AWD2CH_17              (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00020000 */

+#define ADC_AWD2CR_AWD2CH_18              (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */

+#define ADC_AWD2CR_AWD2CH_19              (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_AWD3CR register  ********************/

+#define ADC_AWD3CR_AWD3CH_Pos             (0U)

+#define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x000FFFFF */

+#define ADC_AWD3CR_AWD3CH                 ADC_AWD3CR_AWD3CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */

+#define ADC_AWD3CR_AWD3CH_0               (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000001 */

+#define ADC_AWD3CR_AWD3CH_1               (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000002 */

+#define ADC_AWD3CR_AWD3CH_2               (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000004 */

+#define ADC_AWD3CR_AWD3CH_3               (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000008 */

+#define ADC_AWD3CR_AWD3CH_4               (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000010 */

+#define ADC_AWD3CR_AWD3CH_5               (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000020 */

+#define ADC_AWD3CR_AWD3CH_6               (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000040 */

+#define ADC_AWD3CR_AWD3CH_7               (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000080 */

+#define ADC_AWD3CR_AWD3CH_8               (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000100 */

+#define ADC_AWD3CR_AWD3CH_9               (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000200 */

+#define ADC_AWD3CR_AWD3CH_10              (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000400 */

+#define ADC_AWD3CR_AWD3CH_11              (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000800 */

+#define ADC_AWD3CR_AWD3CH_12              (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00001000 */

+#define ADC_AWD3CR_AWD3CH_13              (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00002000 */

+#define ADC_AWD3CR_AWD3CH_14              (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00004000 */

+#define ADC_AWD3CR_AWD3CH_15              (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00008000 */

+#define ADC_AWD3CR_AWD3CH_16              (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00010000 */

+#define ADC_AWD3CR_AWD3CH_17              (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00020000 */

+#define ADC_AWD3CR_AWD3CH_18              (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */

+#define ADC_AWD3CR_AWD3CH_19              (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_DIFSEL register  ********************/

+#define ADC_DIFSEL_DIFSEL_Pos             (0U)

+#define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */

+#define ADC_DIFSEL_DIFSEL                 ADC_DIFSEL_DIFSEL_Msk                 /*!< ADC differential modes for channels 1 to 18 */

+#define ADC_DIFSEL_DIFSEL_0               (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000001 */

+#define ADC_DIFSEL_DIFSEL_1               (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000002 */

+#define ADC_DIFSEL_DIFSEL_2               (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000004 */

+#define ADC_DIFSEL_DIFSEL_3               (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000008 */

+#define ADC_DIFSEL_DIFSEL_4               (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000010 */

+#define ADC_DIFSEL_DIFSEL_5               (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000020 */

+#define ADC_DIFSEL_DIFSEL_6               (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000040 */

+#define ADC_DIFSEL_DIFSEL_7               (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000080 */

+#define ADC_DIFSEL_DIFSEL_8               (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000100 */

+#define ADC_DIFSEL_DIFSEL_9               (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000200 */

+#define ADC_DIFSEL_DIFSEL_10              (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000400 */

+#define ADC_DIFSEL_DIFSEL_11              (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000800 */

+#define ADC_DIFSEL_DIFSEL_12              (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00001000 */

+#define ADC_DIFSEL_DIFSEL_13              (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00002000 */

+#define ADC_DIFSEL_DIFSEL_14              (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00004000 */

+#define ADC_DIFSEL_DIFSEL_15              (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00008000 */

+#define ADC_DIFSEL_DIFSEL_16              (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00010000 */

+#define ADC_DIFSEL_DIFSEL_17              (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00020000 */

+#define ADC_DIFSEL_DIFSEL_18              (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00040000 */

+#define ADC_DIFSEL_DIFSEL_19              (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_CALFACT register  ********************/

+#define ADC_CALFACT_CALFACT_S_Pos         (0U)

+#define ADC_CALFACT_CALFACT_S_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */

+#define ADC_CALFACT_CALFACT_S             ADC_CALFACT_CALFACT_S_Msk              /*!< ADC calibration factors in single-ended mode */

+#define ADC_CALFACT_CALFACT_S_0           (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */

+#define ADC_CALFACT_CALFACT_S_1           (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */

+#define ADC_CALFACT_CALFACT_S_2           (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */

+#define ADC_CALFACT_CALFACT_S_3           (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */

+#define ADC_CALFACT_CALFACT_S_4           (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */

+#define ADC_CALFACT_CALFACT_S_5           (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */

+#define ADC_CALFACT_CALFACT_S_6           (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */

+#define ADC_CALFACT_CALFACT_S_7           (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */

+#define ADC_CALFACT_CALFACT_S_8           (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */

+#define ADC_CALFACT_CALFACT_S_9           (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */

+#define ADC_CALFACT_CALFACT_S_10          (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */

+#define ADC_CALFACT_CALFACT_D_Pos         (16U)

+#define ADC_CALFACT_CALFACT_D_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */

+#define ADC_CALFACT_CALFACT_D             ADC_CALFACT_CALFACT_D_Msk              /*!< ADC calibration factors in differential mode */

+#define ADC_CALFACT_CALFACT_D_0           (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */

+#define ADC_CALFACT_CALFACT_D_1           (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */

+#define ADC_CALFACT_CALFACT_D_2           (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */

+#define ADC_CALFACT_CALFACT_D_3           (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */

+#define ADC_CALFACT_CALFACT_D_4           (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */

+#define ADC_CALFACT_CALFACT_D_5           (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */

+#define ADC_CALFACT_CALFACT_D_6           (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */

+#define ADC_CALFACT_CALFACT_D_7           (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */

+#define ADC_CALFACT_CALFACT_D_8           (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */

+#define ADC_CALFACT_CALFACT_D_9           (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */

+#define ADC_CALFACT_CALFACT_D_10          (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */

+

+/********************  Bit definition for ADC_CALFACT2 register  ********************/

+#define ADC_CALFACT2_LINCALFACT_Pos       (0U)

+#define ADC_CALFACT2_LINCALFACT_Msk       (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */

+#define ADC_CALFACT2_LINCALFACT           ADC_CALFACT2_LINCALFACT_Msk                   /*!< ADC Linearity calibration factors */

+#define ADC_CALFACT2_LINCALFACT_0         (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */

+#define ADC_CALFACT2_LINCALFACT_1         (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */

+#define ADC_CALFACT2_LINCALFACT_2         (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */

+#define ADC_CALFACT2_LINCALFACT_3         (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */

+#define ADC_CALFACT2_LINCALFACT_4         (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */

+#define ADC_CALFACT2_LINCALFACT_5         (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */

+#define ADC_CALFACT2_LINCALFACT_6         (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */

+#define ADC_CALFACT2_LINCALFACT_7         (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */

+#define ADC_CALFACT2_LINCALFACT_8         (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */

+#define ADC_CALFACT2_LINCALFACT_9         (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */

+#define ADC_CALFACT2_LINCALFACT_10        (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */

+#define ADC_CALFACT2_LINCALFACT_11        (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */

+#define ADC_CALFACT2_LINCALFACT_12        (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */

+#define ADC_CALFACT2_LINCALFACT_13        (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */

+#define ADC_CALFACT2_LINCALFACT_14        (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */

+#define ADC_CALFACT2_LINCALFACT_15        (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */

+#define ADC_CALFACT2_LINCALFACT_16        (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */

+#define ADC_CALFACT2_LINCALFACT_17        (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */

+#define ADC_CALFACT2_LINCALFACT_18        (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */

+#define ADC_CALFACT2_LINCALFACT_19        (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */

+#define ADC_CALFACT2_LINCALFACT_20        (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */

+#define ADC_CALFACT2_LINCALFACT_21        (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */

+#define ADC_CALFACT2_LINCALFACT_22        (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */

+#define ADC_CALFACT2_LINCALFACT_23        (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */

+#define ADC_CALFACT2_LINCALFACT_24        (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */

+#define ADC_CALFACT2_LINCALFACT_25        (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */

+#define ADC_CALFACT2_LINCALFACT_26        (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */

+#define ADC_CALFACT2_LINCALFACT_27        (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */

+#define ADC_CALFACT2_LINCALFACT_28        (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */

+#define ADC_CALFACT2_LINCALFACT_29        (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */

+

+/*************************  ADC Common registers  *****************************/

+/********************  Bit definition for ADC_CSR register  ********************/

+#define ADC_CSR_ADRDY_MST_Pos             (0U)

+#define ADC_CSR_ADRDY_MST_Msk             (0x1UL << ADC_CSR_ADRDY_MST_Pos)     /*!< 0x00000001 */

+#define ADC_CSR_ADRDY_MST                 ADC_CSR_ADRDY_MST_Msk                /*!< Master ADC ready */

+#define ADC_CSR_EOSMP_MST_Pos             (1U)

+#define ADC_CSR_EOSMP_MST_Msk             (0x1UL << ADC_CSR_EOSMP_MST_Pos)     /*!< 0x00000002 */

+#define ADC_CSR_EOSMP_MST                 ADC_CSR_EOSMP_MST_Msk                /*!< End of sampling phase flag of the master ADC */

+#define ADC_CSR_EOC_MST_Pos               (2U)

+#define ADC_CSR_EOC_MST_Msk               (0x1UL << ADC_CSR_EOC_MST_Pos)       /*!< 0x00000004 */

+#define ADC_CSR_EOC_MST                   ADC_CSR_EOC_MST_Msk                  /*!< End of regular conversion of the master ADC */

+#define ADC_CSR_EOS_MST_Pos               (3U)

+#define ADC_CSR_EOS_MST_Msk               (0x1UL << ADC_CSR_EOS_MST_Pos)       /*!< 0x00000008 */

+#define ADC_CSR_EOS_MST                   ADC_CSR_EOS_MST_Msk                  /*!< End of regular sequence flag of the master ADC */

+#define ADC_CSR_OVR_MST_Pos               (4U)

+#define ADC_CSR_OVR_MST_Msk               (0x1UL << ADC_CSR_OVR_MST_Pos)       /*!< 0x00000010 */

+#define ADC_CSR_OVR_MST                   ADC_CSR_OVR_MST_Msk                  /*!< Overrun flag of the master ADC */

+#define ADC_CSR_JEOC_MST_Pos              (5U)

+#define ADC_CSR_JEOC_MST_Msk              (0x1UL << ADC_CSR_JEOC_MST_Pos)      /*!< 0x00000020 */

+#define ADC_CSR_JEOC_MST                  ADC_CSR_JEOC_MST_Msk                 /*!< End of injected conversion of the master ADC */

+#define ADC_CSR_JEOS_MST_Pos              (6U)

+#define ADC_CSR_JEOS_MST_Msk              (0x1UL << ADC_CSR_JEOS_MST_Pos)      /*!< 0x00000040 */

+#define ADC_CSR_JEOS_MST                  ADC_CSR_JEOS_MST_Msk                 /*!< End of injected sequence flag of the master ADC */

+#define ADC_CSR_AWD1_MST_Pos              (7U)

+#define ADC_CSR_AWD1_MST_Msk              (0x1UL << ADC_CSR_AWD1_MST_Pos)      /*!< 0x00000080 */

+#define ADC_CSR_AWD1_MST                  ADC_CSR_AWD1_MST_Msk                 /*!< Analog watchdog 1 flag of the master ADC */

+#define ADC_CSR_AWD2_MST_Pos              (8U)

+#define ADC_CSR_AWD2_MST_Msk              (0x1UL << ADC_CSR_AWD2_MST_Pos)      /*!< 0x00000100 */

+#define ADC_CSR_AWD2_MST                  ADC_CSR_AWD2_MST_Msk                 /*!< Analog watchdog 2 flag of the master ADC */

+#define ADC_CSR_AWD3_MST_Pos              (9U)

+#define ADC_CSR_AWD3_MST_Msk              (0x1UL << ADC_CSR_AWD3_MST_Pos)      /*!< 0x00000200 */

+#define ADC_CSR_AWD3_MST                  ADC_CSR_AWD3_MST_Msk                 /*!< Analog watchdog 3 flag of the master ADC */

+#define ADC_CSR_JQOVF_MST_Pos             (10U)

+#define ADC_CSR_JQOVF_MST_Msk             (0x1UL << ADC_CSR_JQOVF_MST_Pos)     /*!< 0x00000400 */

+#define ADC_CSR_JQOVF_MST                 ADC_CSR_JQOVF_MST_Msk                /*!< Injected context queue overflow flag of the master ADC */

+#define ADC_CSR_ADRDY_SLV_Pos             (16U)

+#define ADC_CSR_ADRDY_SLV_Msk             (0x1UL << ADC_CSR_ADRDY_SLV_Pos)     /*!< 0x00010000 */

+#define ADC_CSR_ADRDY_SLV                 ADC_CSR_ADRDY_SLV_Msk                /*!< Slave ADC ready */

+#define ADC_CSR_EOSMP_SLV_Pos             (17U)

+#define ADC_CSR_EOSMP_SLV_Msk             (0x1UL << ADC_CSR_EOSMP_SLV_Pos)     /*!< 0x00020000 */

+#define ADC_CSR_EOSMP_SLV                 ADC_CSR_EOSMP_SLV_Msk                /*!< End of sampling phase flag of the slave ADC */

+#define ADC_CSR_EOC_SLV_Pos               (18U)

+#define ADC_CSR_EOC_SLV_Msk               (0x1UL << ADC_CSR_EOC_SLV_Pos)       /*!< 0x00040000 */

+#define ADC_CSR_EOC_SLV                   ADC_CSR_EOC_SLV_Msk                  /*!< End of regular conversion of the slave ADC */

+#define ADC_CSR_EOS_SLV_Pos               (19U)

+#define ADC_CSR_EOS_SLV_Msk               (0x1UL << ADC_CSR_EOS_SLV_Pos)       /*!< 0x00080000 */

+#define ADC_CSR_EOS_SLV                   ADC_CSR_EOS_SLV_Msk                  /*!< End of regular sequence flag of the slave ADC */

+#define ADC_CSR_OVR_SLV_Pos               (20U)

+#define ADC_CSR_OVR_SLV_Msk               (0x1UL << ADC_CSR_OVR_SLV_Pos)       /*!< 0x00100000 */

+#define ADC_CSR_OVR_SLV                   ADC_CSR_OVR_SLV_Msk                  /*!< Overrun flag of the slave ADC */

+#define ADC_CSR_JEOC_SLV_Pos              (21U)

+#define ADC_CSR_JEOC_SLV_Msk              (0x1UL << ADC_CSR_JEOC_SLV_Pos)      /*!< 0x00200000 */

+#define ADC_CSR_JEOC_SLV                  ADC_CSR_JEOC_SLV_Msk                 /*!< End of injected conversion of the slave ADC */

+#define ADC_CSR_JEOS_SLV_Pos              (22U)

+#define ADC_CSR_JEOS_SLV_Msk              (0x1UL << ADC_CSR_JEOS_SLV_Pos)      /*!< 0x00400000 */

+#define ADC_CSR_JEOS_SLV                  ADC_CSR_JEOS_SLV_Msk                 /*!< End of injected sequence flag of the slave ADC */

+#define ADC_CSR_AWD1_SLV_Pos              (23U)

+#define ADC_CSR_AWD1_SLV_Msk              (0x1UL << ADC_CSR_AWD1_SLV_Pos)      /*!< 0x00800000 */

+#define ADC_CSR_AWD1_SLV                  ADC_CSR_AWD1_SLV_Msk                 /*!< Analog watchdog 1 flag of the slave ADC */

+#define ADC_CSR_AWD2_SLV_Pos              (24U)

+#define ADC_CSR_AWD2_SLV_Msk              (0x1UL << ADC_CSR_AWD2_SLV_Pos)      /*!< 0x01000000 */

+#define ADC_CSR_AWD2_SLV                  ADC_CSR_AWD2_SLV_Msk                 /*!< Analog watchdog 2 flag of the slave ADC */

+#define ADC_CSR_AWD3_SLV_Pos              (25U)

+#define ADC_CSR_AWD3_SLV_Msk              (0x1UL << ADC_CSR_AWD3_SLV_Pos)      /*!< 0x02000000 */

+#define ADC_CSR_AWD3_SLV                  ADC_CSR_AWD3_SLV_Msk                 /*!< Analog watchdog 3 flag of the slave ADC */

+#define ADC_CSR_JQOVF_SLV_Pos             (26U)

+#define ADC_CSR_JQOVF_SLV_Msk             (0x1UL << ADC_CSR_JQOVF_SLV_Pos)     /*!< 0x04000000 */

+#define ADC_CSR_JQOVF_SLV                 ADC_CSR_JQOVF_SLV_Msk                /*!< Injected context queue overflow flag of the slave ADC */

+

+/********************  Bit definition for ADC_CCR register  ********************/

+#define ADC_CCR_DUAL_Pos                  (0U)

+#define ADC_CCR_DUAL_Msk                  (0x1FUL << ADC_CCR_DUAL_Pos)          /*!< 0x0000001F */

+#define ADC_CCR_DUAL                      ADC_CCR_DUAL_Msk                      /*!< Dual ADC mode selection */

+#define ADC_CCR_DUAL_0                    (0x01UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000001 */

+#define ADC_CCR_DUAL_1                    (0x02UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000002 */

+#define ADC_CCR_DUAL_2                    (0x04UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000004 */

+#define ADC_CCR_DUAL_3                    (0x08UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000008 */

+#define ADC_CCR_DUAL_4                    (0x10UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000010 */

+

+#define ADC_CCR_DELAY_Pos                 (8U)

+#define ADC_CCR_DELAY_Msk                 (0xFUL << ADC_CCR_DELAY_Pos)          /*!< 0x00000F00 */

+#define ADC_CCR_DELAY                     ADC_CCR_DELAY_Msk                     /*!< Delay between 2 sampling phases */

+#define ADC_CCR_DELAY_0                   (0x1UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000100 */

+#define ADC_CCR_DELAY_1                   (0x2UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000200 */

+#define ADC_CCR_DELAY_2                   (0x4UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000400 */

+#define ADC_CCR_DELAY_3                   (0x8UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000800 */

+

+

+#define ADC_CCR_DAMDF_Pos                 (14U)

+#define ADC_CCR_DAMDF_Msk                 (0x3UL << ADC_CCR_DAMDF_Pos)          /*!< 0x0000C000 */

+#define ADC_CCR_DAMDF                     ADC_CCR_DAMDF_Msk                     /*!< Dual ADC mode Data format */

+#define ADC_CCR_DAMDF_0                   (0x1UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00004000 */

+#define ADC_CCR_DAMDF_1                   (0x2UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00008000 */

+

+#define ADC_CCR_CKMODE_Pos                (16U)

+#define ADC_CCR_CKMODE_Msk                (0x3UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00030000 */

+#define ADC_CCR_CKMODE                    ADC_CCR_CKMODE_Msk                    /*!< ADC clock mode */

+#define ADC_CCR_CKMODE_0                  (0x1UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00010000 */

+#define ADC_CCR_CKMODE_1                  (0x2UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00020000 */

+

+#define ADC_CCR_PRESC_Pos                 (18U)

+#define ADC_CCR_PRESC_Msk                 (0xFUL << ADC_CCR_PRESC_Pos)          /*!< 0x003C0000 */

+#define ADC_CCR_PRESC                     ADC_CCR_PRESC_Msk                     /*!< ADC prescaler */

+#define ADC_CCR_PRESC_0                   (0x1UL << ADC_CCR_PRESC_Pos)          /*!< 0x00040000 */

+#define ADC_CCR_PRESC_1                   (0x2UL << ADC_CCR_PRESC_Pos)          /*!< 0x00080000 */

+#define ADC_CCR_PRESC_2                   (0x4UL << ADC_CCR_PRESC_Pos)          /*!< 0x00100000 */

+#define ADC_CCR_PRESC_3                   (0x8UL << ADC_CCR_PRESC_Pos)          /*!< 0x00200000 */

+

+#define ADC_CCR_VREFEN_Pos                (22U)

+#define ADC_CCR_VREFEN_Msk                (0x1UL << ADC_CCR_VREFEN_Pos)         /*!< 0x00400000 */

+#define ADC_CCR_VREFEN                    ADC_CCR_VREFEN_Msk                    /*!< VREFINT enable */

+#define ADC_CCR_TSEN_Pos                  (23U)

+#define ADC_CCR_TSEN_Msk                  (0x1UL << ADC_CCR_TSEN_Pos)           /*!< 0x00800000 */

+#define ADC_CCR_TSEN                      ADC_CCR_TSEN_Msk                      /*!< Temperature sensor enable */

+#define ADC_CCR_VBATEN_Pos                (24U)

+#define ADC_CCR_VBATEN_Msk                (0x1UL << ADC_CCR_VBATEN_Pos)         /*!< 0x01000000 */

+#define ADC_CCR_VBATEN                    ADC_CCR_VBATEN_Msk                    /*!< VBAT enable */

+

+/********************  Bit definition for ADC_CDR register  *******************/

+#define ADC_CDR_RDATA_MST_Pos             (0U)

+#define ADC_CDR_RDATA_MST_Msk             (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)   /*!< 0x0000FFFF */

+#define ADC_CDR_RDATA_MST                 ADC_CDR_RDATA_MST_Msk                 /*!< ADC multimode master group regular conversion data */

+

+#define ADC_CDR_RDATA_SLV_Pos             (16U)

+#define ADC_CDR_RDATA_SLV_Msk             (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)   /*!< 0xFFFF0000 */

+#define ADC_CDR_RDATA_SLV                 ADC_CDR_RDATA_SLV_Msk                 /*!< ADC multimode slave group regular conversion data */

+

+/********************  Bit definition for ADC_CDR2 register  ******************/

+#define ADC_CDR2_RDATA_ALT_Pos            (0U)

+#define ADC_CDR2_RDATA_ALT_Msk            (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */

+#define ADC_CDR2_RDATA_ALT                ADC_CDR2_RDATA_ALT_Msk                   /*!< Regular data of the master/slave alternated ADCs */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                   VREFBUF                                  */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for VREFBUF_CSR register  ****************/

+#define VREFBUF_CSR_ENVR_Pos        (0U)

+#define VREFBUF_CSR_ENVR_Msk        (0x1UL << VREFBUF_CSR_ENVR_Pos)            /*!< 0x00000001 */

+#define VREFBUF_CSR_ENVR            VREFBUF_CSR_ENVR_Msk                       /*!<Voltage reference buffer enable */

+#define VREFBUF_CSR_HIZ_Pos         (1U)

+#define VREFBUF_CSR_HIZ_Msk         (0x1UL << VREFBUF_CSR_HIZ_Pos)             /*!< 0x00000002 */

+#define VREFBUF_CSR_HIZ             VREFBUF_CSR_HIZ_Msk                        /*!<High impedance mode             */

+#define VREFBUF_CSR_VRR_Pos         (3U)

+#define VREFBUF_CSR_VRR_Msk         (0x1UL << VREFBUF_CSR_VRR_Pos)             /*!< 0x00000008 */

+#define VREFBUF_CSR_VRR             VREFBUF_CSR_VRR_Msk                        /*!<Voltage reference buffer ready  */

+#define VREFBUF_CSR_VRS_Pos         (4U)

+#define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */

+#define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */

+

+#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */

+#define VREFBUF_CSR_VRS_OUT2_Pos    (4U)

+#define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */

+#define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */

+#define VREFBUF_CSR_VRS_OUT3_Pos    (5U)

+#define VREFBUF_CSR_VRS_OUT3_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)        /*!< 0x00000020 */

+#define VREFBUF_CSR_VRS_OUT3        VREFBUF_CSR_VRS_OUT3_Msk                   /*!<Voltage reference VREF_OUT3     */

+#define VREFBUF_CSR_VRS_OUT4_Pos    (4U)

+#define VREFBUF_CSR_VRS_OUT4_Msk    (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)        /*!< 0x00000030 */

+#define VREFBUF_CSR_VRS_OUT4        VREFBUF_CSR_VRS_OUT4_Msk                   /*!<Voltage reference VREF_OUT4     */

+

+/*******************  Bit definition for VREFBUF_CCR register  ****************/

+#define VREFBUF_CCR_TRIM_Pos        (0U)

+#define VREFBUF_CCR_TRIM_Msk        (0x3FUL << VREFBUF_CCR_TRIM_Pos)           /*!< 0x0000003F */

+#define VREFBUF_CCR_TRIM            VREFBUF_CCR_TRIM_Msk                       /*!<TRIM[5:0] bits (Trimming code)  */

+

+/******************************************************************************/

+/*                                                                            */

+/*                 Flexible Datarate Controller Area Network                  */

+/*                                                                            */

+/******************************************************************************/

+/*!<FDCAN control and status registers */

+/*****************  Bit definition for FDCAN_CREL register  *******************/

+#define FDCAN_CREL_DAY_Pos        (0U)

+#define FDCAN_CREL_DAY_Msk        (0xFFUL << FDCAN_CREL_DAY_Pos)               /*!< 0x000000FF */

+#define FDCAN_CREL_DAY            FDCAN_CREL_DAY_Msk                           /*!<Timestamp Day                           */

+#define FDCAN_CREL_MON_Pos        (8U)

+#define FDCAN_CREL_MON_Msk        (0xFFUL << FDCAN_CREL_MON_Pos)               /*!< 0x0000FF00 */

+#define FDCAN_CREL_MON            FDCAN_CREL_MON_Msk                           /*!<Timestamp Month                         */

+#define FDCAN_CREL_YEAR_Pos       (16U)

+#define FDCAN_CREL_YEAR_Msk       (0xFUL << FDCAN_CREL_YEAR_Pos)               /*!< 0x000F0000 */

+#define FDCAN_CREL_YEAR           FDCAN_CREL_YEAR_Msk                          /*!<Timestamp Year                          */

+#define FDCAN_CREL_SUBSTEP_Pos    (20U)

+#define FDCAN_CREL_SUBSTEP_Msk    (0xFUL << FDCAN_CREL_SUBSTEP_Pos)            /*!< 0x00F00000 */

+#define FDCAN_CREL_SUBSTEP        FDCAN_CREL_SUBSTEP_Msk                       /*!<Sub-step of Core release                */

+#define FDCAN_CREL_STEP_Pos       (24U)

+#define FDCAN_CREL_STEP_Msk       (0xFUL << FDCAN_CREL_STEP_Pos)               /*!< 0x0F000000 */

+#define FDCAN_CREL_STEP           FDCAN_CREL_STEP_Msk                          /*!<Step of Core release                    */

+#define FDCAN_CREL_REL_Pos        (28U)

+#define FDCAN_CREL_REL_Msk        (0xFUL << FDCAN_CREL_REL_Pos)                /*!< 0xF0000000 */

+#define FDCAN_CREL_REL            FDCAN_CREL_REL_Msk                           /*!<Core release                            */

+

+/*****************  Bit definition for FDCAN_ENDN register  *******************/

+#define FDCAN_ENDN_ETV_Pos        (0U)

+#define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endiannes Test Value                    */

+

+/*****************  Bit definition for FDCAN_DBTP register  *******************/

+#define FDCAN_DBTP_DSJW_Pos       (0U)

+#define FDCAN_DBTP_DSJW_Msk       (0xFUL << FDCAN_DBTP_DSJW_Pos)               /*!< 0x0000000F */

+#define FDCAN_DBTP_DSJW           FDCAN_DBTP_DSJW_Msk                          /*!<Synchronization Jump Width              */

+#define FDCAN_DBTP_DTSEG2_Pos     (4U)

+#define FDCAN_DBTP_DTSEG2_Msk     (0xFUL << FDCAN_DBTP_DTSEG2_Pos)             /*!< 0x000000F0 */

+#define FDCAN_DBTP_DTSEG2         FDCAN_DBTP_DTSEG2_Msk                        /*!<Data time segment after sample point    */

+#define FDCAN_DBTP_DTSEG1_Pos     (8U)

+#define FDCAN_DBTP_DTSEG1_Msk     (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)            /*!< 0x00001F00 */

+#define FDCAN_DBTP_DTSEG1         FDCAN_DBTP_DTSEG1_Msk                        /*!<Data time segment before sample point   */

+#define FDCAN_DBTP_DBRP_Pos       (16U)

+#define FDCAN_DBTP_DBRP_Msk       (0x1FUL << FDCAN_DBTP_DBRP_Pos)              /*!< 0x001F0000 */

+#define FDCAN_DBTP_DBRP           FDCAN_DBTP_DBRP_Msk                          /*!<Data BIt Rate Prescaler                 */

+#define FDCAN_DBTP_TDC_Pos        (23U)

+#define FDCAN_DBTP_TDC_Msk        (0x1UL << FDCAN_DBTP_TDC_Pos)                /*!< 0x00800000 */

+#define FDCAN_DBTP_TDC            FDCAN_DBTP_TDC_Msk                           /*!<Transceiver Delay Compensation          */

+

+/*****************  Bit definition for FDCAN_TEST register  *******************/

+#define FDCAN_TEST_LBCK_Pos       (4U)

+#define FDCAN_TEST_LBCK_Msk       (0x1UL << FDCAN_TEST_LBCK_Pos)               /*!< 0x00000010 */

+#define FDCAN_TEST_LBCK           FDCAN_TEST_LBCK_Msk                          /*!<Loop Back mode                           */

+#define FDCAN_TEST_TX_Pos         (5U)

+#define FDCAN_TEST_TX_Msk         (0x3UL << FDCAN_TEST_TX_Pos)                 /*!< 0x00000060 */

+#define FDCAN_TEST_TX             FDCAN_TEST_TX_Msk                            /*!<Control of Transmit Pin                  */

+#define FDCAN_TEST_RX_Pos         (7U)

+#define FDCAN_TEST_RX_Msk         (0x1UL << FDCAN_TEST_RX_Pos)                 /*!< 0x00000080 */

+#define FDCAN_TEST_RX             FDCAN_TEST_RX_Msk                            /*!<Receive Pin                              */

+

+/*****************  Bit definition for FDCAN_RWD register  ********************/

+#define FDCAN_RWD_WDC_Pos         (0U)

+#define FDCAN_RWD_WDC_Msk         (0xFFUL << FDCAN_RWD_WDC_Pos)                /*!< 0x000000FF */

+#define FDCAN_RWD_WDC             FDCAN_RWD_WDC_Msk                            /*!<Watchdog configuration                   */

+#define FDCAN_RWD_WDV_Pos         (8U)

+#define FDCAN_RWD_WDV_Msk         (0xFFUL << FDCAN_RWD_WDV_Pos)                /*!< 0x0000FF00 */

+#define FDCAN_RWD_WDV             FDCAN_RWD_WDV_Msk                            /*!<Watchdog value                           */

+

+/*****************  Bit definition for FDCAN_CCCR register  ********************/

+#define FDCAN_CCCR_INIT_Pos       (0U)

+#define FDCAN_CCCR_INIT_Msk       (0x1UL << FDCAN_CCCR_INIT_Pos)               /*!< 0x00000001 */

+#define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!<Initialization                           */

+#define FDCAN_CCCR_CCE_Pos        (1U)

+#define FDCAN_CCCR_CCE_Msk        (0x1UL << FDCAN_CCCR_CCE_Pos)                /*!< 0x00000002 */

+#define FDCAN_CCCR_CCE            FDCAN_CCCR_CCE_Msk                           /*!<Configuration Change Enable              */

+#define FDCAN_CCCR_ASM_Pos        (2U)

+#define FDCAN_CCCR_ASM_Msk        (0x1UL << FDCAN_CCCR_ASM_Pos)                /*!< 0x00000004 */

+#define FDCAN_CCCR_ASM            FDCAN_CCCR_ASM_Msk                           /*!<ASM Restricted Operation Mode            */

+#define FDCAN_CCCR_CSA_Pos        (3U)

+#define FDCAN_CCCR_CSA_Msk        (0x1UL << FDCAN_CCCR_CSA_Pos)                /*!< 0x00000008 */

+#define FDCAN_CCCR_CSA            FDCAN_CCCR_CSA_Msk                           /*!<Clock Stop Acknowledge                   */

+#define FDCAN_CCCR_CSR_Pos        (4U)

+#define FDCAN_CCCR_CSR_Msk        (0x1UL << FDCAN_CCCR_CSR_Pos)                /*!< 0x00000010 */

+#define FDCAN_CCCR_CSR            FDCAN_CCCR_CSR_Msk                           /*!<Clock Stop Request                       */

+#define FDCAN_CCCR_MON_Pos        (5U)

+#define FDCAN_CCCR_MON_Msk        (0x1UL << FDCAN_CCCR_MON_Pos)                /*!< 0x00000020 */

+#define FDCAN_CCCR_MON            FDCAN_CCCR_MON_Msk                           /*!<Bus Monitoring Mode                      */

+#define FDCAN_CCCR_DAR_Pos        (6U)

+#define FDCAN_CCCR_DAR_Msk        (0x1UL << FDCAN_CCCR_DAR_Pos)                /*!< 0x00000040 */

+#define FDCAN_CCCR_DAR            FDCAN_CCCR_DAR_Msk                           /*!<Disable Automatic Retransmission         */

+#define FDCAN_CCCR_TEST_Pos       (7U)

+#define FDCAN_CCCR_TEST_Msk       (0x1UL << FDCAN_CCCR_TEST_Pos)               /*!< 0x00000080 */

+#define FDCAN_CCCR_TEST           FDCAN_CCCR_TEST_Msk                          /*!<Test Mode Enable                         */

+#define FDCAN_CCCR_FDOE_Pos       (8U)

+#define FDCAN_CCCR_FDOE_Msk       (0x1UL << FDCAN_CCCR_FDOE_Pos)               /*!< 0x00000100 */

+#define FDCAN_CCCR_FDOE           FDCAN_CCCR_FDOE_Msk                          /*!<FD Operation Enable                      */

+#define FDCAN_CCCR_BRSE_Pos       (9U)

+#define FDCAN_CCCR_BRSE_Msk       (0x1UL << FDCAN_CCCR_BRSE_Pos)               /*!< 0x00000200 */

+#define FDCAN_CCCR_BRSE           FDCAN_CCCR_BRSE_Msk                          /*!<FDCAN Bit Rate Switching                 */

+#define FDCAN_CCCR_PXHD_Pos       (12U)

+#define FDCAN_CCCR_PXHD_Msk       (0x1UL << FDCAN_CCCR_PXHD_Pos)               /*!< 0x00001000 */

+#define FDCAN_CCCR_PXHD           FDCAN_CCCR_PXHD_Msk                          /*!<Protocol Exception Handling Disable      */

+#define FDCAN_CCCR_EFBI_Pos       (13U)

+#define FDCAN_CCCR_EFBI_Msk       (0x1UL << FDCAN_CCCR_EFBI_Pos)               /*!< 0x00002000 */

+#define FDCAN_CCCR_EFBI           FDCAN_CCCR_EFBI_Msk                          /*!<Edge Filtering during Bus Integration    */

+#define FDCAN_CCCR_TXP_Pos        (14U)

+#define FDCAN_CCCR_TXP_Msk        (0x1UL << FDCAN_CCCR_TXP_Pos)                /*!< 0x00004000 */

+#define FDCAN_CCCR_TXP            FDCAN_CCCR_TXP_Msk                           /*!<Two CAN bit times Pause                  */

+#define FDCAN_CCCR_NISO_Pos       (15U)

+#define FDCAN_CCCR_NISO_Msk       (0x1UL << FDCAN_CCCR_NISO_Pos)               /*!< 0x00008000 */

+#define FDCAN_CCCR_NISO           FDCAN_CCCR_NISO_Msk                          /*!<Non ISO Operation                        */

+

+/*****************  Bit definition for FDCAN_NBTP register  ********************/

+#define FDCAN_NBTP_NTSEG2_Pos     (0U)

+#define FDCAN_NBTP_NTSEG2_Msk     (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)            /*!< 0x0000007F */

+#define FDCAN_NBTP_NTSEG2         FDCAN_NBTP_NTSEG2_Msk                        /*!<Nominal Time segment after sample point  */

+#define FDCAN_NBTP_NTSEG1_Pos     (8U)

+#define FDCAN_NBTP_NTSEG1_Msk     (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)            /*!< 0x0000FF00 */

+#define FDCAN_NBTP_NTSEG1         FDCAN_NBTP_NTSEG1_Msk                        /*!<Nominal Time segment before sample point */

+#define FDCAN_NBTP_NBRP_Pos       (16U)

+#define FDCAN_NBTP_NBRP_Msk       (0x1FFUL << FDCAN_NBTP_NBRP_Pos)             /*!< 0x01FF0000 */

+#define FDCAN_NBTP_NBRP           FDCAN_NBTP_NBRP_Msk                          /*!<Bit Rate Prescaler                       */

+#define FDCAN_NBTP_NSJW_Pos       (25U)

+#define FDCAN_NBTP_NSJW_Msk       (0x7FUL << FDCAN_NBTP_NSJW_Pos)              /*!< 0xFE000000 */

+#define FDCAN_NBTP_NSJW           FDCAN_NBTP_NSJW_Msk                          /*!<Nominal (Re)Synchronization Jump Width   */

+

+/*****************  Bit definition for FDCAN_TSCC register  ********************/

+#define FDCAN_TSCC_TSS_Pos        (0U)

+#define FDCAN_TSCC_TSS_Msk        (0x3UL << FDCAN_TSCC_TSS_Pos)                /*!< 0x00000003 */

+#define FDCAN_TSCC_TSS            FDCAN_TSCC_TSS_Msk                           /*!<Timestamp Select                         */

+#define FDCAN_TSCC_TCP_Pos        (16U)

+#define FDCAN_TSCC_TCP_Msk        (0xFUL << FDCAN_TSCC_TCP_Pos)                /*!< 0x000F0000 */

+#define FDCAN_TSCC_TCP            FDCAN_TSCC_TCP_Msk                           /*!<Timestamp Counter Prescaler              */

+

+/*****************  Bit definition for FDCAN_TSCV register  ********************/

+#define FDCAN_TSCV_TSC_Pos        (0U)

+#define FDCAN_TSCV_TSC_Msk        (0xFFFFUL << FDCAN_TSCV_TSC_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TSCV_TSC            FDCAN_TSCV_TSC_Msk                           /*!<Timestamp Counter                        */

+

+/*****************  Bit definition for FDCAN_TOCC register  ********************/

+#define FDCAN_TOCC_ETOC_Pos       (0U)

+#define FDCAN_TOCC_ETOC_Msk       (0x1UL << FDCAN_TOCC_ETOC_Pos)               /*!< 0x00000001 */

+#define FDCAN_TOCC_ETOC           FDCAN_TOCC_ETOC_Msk                          /*!<Enable Timeout Counter                   */

+#define FDCAN_TOCC_TOS_Pos        (1U)

+#define FDCAN_TOCC_TOS_Msk        (0x3UL << FDCAN_TOCC_TOS_Pos)                /*!< 0x00000006 */

+#define FDCAN_TOCC_TOS            FDCAN_TOCC_TOS_Msk                           /*!<Timeout Select                           */

+#define FDCAN_TOCC_TOP_Pos        (16U)

+#define FDCAN_TOCC_TOP_Msk        (0xFFFFUL << FDCAN_TOCC_TOP_Pos)             /*!< 0xFFFF0000 */

+#define FDCAN_TOCC_TOP            FDCAN_TOCC_TOP_Msk                           /*!<Timeout Period                           */

+

+/*****************  Bit definition for FDCAN_TOCV register  ********************/

+#define FDCAN_TOCV_TOC_Pos        (0U)

+#define FDCAN_TOCV_TOC_Msk        (0xFFFFUL << FDCAN_TOCV_TOC_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TOCV_TOC            FDCAN_TOCV_TOC_Msk                           /*!<Timeout Counter                          */

+

+/*****************  Bit definition for FDCAN_ECR register  *********************/

+#define FDCAN_ECR_TEC_Pos         (0U)

+#define FDCAN_ECR_TEC_Msk         (0xFUL << FDCAN_ECR_TEC_Pos)                 /*!< 0x0000000F */

+#define FDCAN_ECR_TEC             FDCAN_ECR_TEC_Msk                            /*!<Transmit Error Counter                   */

+#define FDCAN_ECR_REC_Pos         (8U)

+#define FDCAN_ECR_REC_Msk         (0x7FUL << FDCAN_ECR_REC_Pos)                /*!< 0x00007F00 */

+#define FDCAN_ECR_REC             FDCAN_ECR_REC_Msk                            /*!<Receive Error Counter                    */

+#define FDCAN_ECR_RP_Pos          (15U)

+#define FDCAN_ECR_RP_Msk          (0x1UL << FDCAN_ECR_RP_Pos)                  /*!< 0x00008000 */

+#define FDCAN_ECR_RP              FDCAN_ECR_RP_Msk                             /*!<Receive Error Passive                    */

+#define FDCAN_ECR_CEL_Pos         (16U)

+#define FDCAN_ECR_CEL_Msk         (0xFFUL << FDCAN_ECR_CEL_Pos)                /*!< 0x00FF0000 */

+#define FDCAN_ECR_CEL             FDCAN_ECR_CEL_Msk                            /*!<CAN Error Logging                        */

+

+/*****************  Bit definition for FDCAN_PSR register  *********************/

+#define FDCAN_PSR_LEC_Pos         (0U)

+#define FDCAN_PSR_LEC_Msk         (0x7UL << FDCAN_PSR_LEC_Pos)                 /*!< 0x00000007 */

+#define FDCAN_PSR_LEC             FDCAN_PSR_LEC_Msk                            /*!<Last Error Code                          */

+#define FDCAN_PSR_ACT_Pos         (3U)

+#define FDCAN_PSR_ACT_Msk         (0x3UL << FDCAN_PSR_ACT_Pos)                 /*!< 0x00000018 */

+#define FDCAN_PSR_ACT             FDCAN_PSR_ACT_Msk                            /*!<Activity                                 */

+#define FDCAN_PSR_EP_Pos          (5U)

+#define FDCAN_PSR_EP_Msk          (0x1UL << FDCAN_PSR_EP_Pos)                  /*!< 0x00000020 */

+#define FDCAN_PSR_EP              FDCAN_PSR_EP_Msk                             /*!<Error Passive                            */

+#define FDCAN_PSR_EW_Pos          (6U)

+#define FDCAN_PSR_EW_Msk          (0x1UL << FDCAN_PSR_EW_Pos)                  /*!< 0x00000040 */

+#define FDCAN_PSR_EW              FDCAN_PSR_EW_Msk                             /*!<Warning Status                           */

+#define FDCAN_PSR_BO_Pos          (7U)

+#define FDCAN_PSR_BO_Msk          (0x1UL << FDCAN_PSR_BO_Pos)                  /*!< 0x00000080 */

+#define FDCAN_PSR_BO              FDCAN_PSR_BO_Msk                             /*!<Bus_Off Status                           */

+#define FDCAN_PSR_DLEC_Pos        (8U)

+#define FDCAN_PSR_DLEC_Msk        (0x7UL << FDCAN_PSR_DLEC_Pos)                /*!< 0x00000700 */

+#define FDCAN_PSR_DLEC            FDCAN_PSR_DLEC_Msk                           /*!<Data Last Error Code                     */

+#define FDCAN_PSR_RESI_Pos        (11U)

+#define FDCAN_PSR_RESI_Msk        (0x1UL << FDCAN_PSR_RESI_Pos)                /*!< 0x00000800 */

+#define FDCAN_PSR_RESI            FDCAN_PSR_RESI_Msk                           /*!<ESI flag of last received FDCAN Message  */

+#define FDCAN_PSR_RBRS_Pos        (12U)

+#define FDCAN_PSR_RBRS_Msk        (0x1UL << FDCAN_PSR_RBRS_Pos)                /*!< 0x00001000 */

+#define FDCAN_PSR_RBRS            FDCAN_PSR_RBRS_Msk                           /*!<BRS flag of last received FDCAN Message  */

+#define FDCAN_PSR_REDL_Pos        (13U)

+#define FDCAN_PSR_REDL_Msk        (0x1UL << FDCAN_PSR_REDL_Pos)                /*!< 0x00002000 */

+#define FDCAN_PSR_REDL            FDCAN_PSR_REDL_Msk                           /*!<Received FDCAN Message                   */

+#define FDCAN_PSR_PXE_Pos         (14U)

+#define FDCAN_PSR_PXE_Msk         (0x1UL << FDCAN_PSR_PXE_Pos)                 /*!< 0x00004000 */

+#define FDCAN_PSR_PXE             FDCAN_PSR_PXE_Msk                            /*!<Protocol Exception Event                 */

+#define FDCAN_PSR_TDCV_Pos        (16U)

+#define FDCAN_PSR_TDCV_Msk        (0x7FUL << FDCAN_PSR_TDCV_Pos)               /*!< 0x007F0000 */

+#define FDCAN_PSR_TDCV            FDCAN_PSR_TDCV_Msk                           /*!<Transmitter Delay Compensation Value     */

+

+/*****************  Bit definition for FDCAN_TDCR register  ********************/

+#define FDCAN_TDCR_TDCF_Pos       (0U)

+#define FDCAN_TDCR_TDCF_Msk       (0x7FUL << FDCAN_TDCR_TDCF_Pos)              /*!< 0x0000007F */

+#define FDCAN_TDCR_TDCF           FDCAN_TDCR_TDCF_Msk                          /*!<Transmitter Delay Compensation Filter    */

+#define FDCAN_TDCR_TDCO_Pos       (8U)

+#define FDCAN_TDCR_TDCO_Msk       (0x7FUL << FDCAN_TDCR_TDCO_Pos)              /*!< 0x00007F00 */

+#define FDCAN_TDCR_TDCO           FDCAN_TDCR_TDCO_Msk                          /*!<Transmitter Delay Compensation Offset    */

+

+/*****************  Bit definition for FDCAN_IR register  **********************/

+#define FDCAN_IR_RF0N_Pos         (0U)

+#define FDCAN_IR_RF0N_Msk         (0x1UL << FDCAN_IR_RF0N_Pos)                 /*!< 0x00000001 */

+#define FDCAN_IR_RF0N             FDCAN_IR_RF0N_Msk                            /*!<Rx FIFO 0 New Message                    */

+#define FDCAN_IR_RF0W_Pos         (1U)

+#define FDCAN_IR_RF0W_Msk         (0x1UL << FDCAN_IR_RF0W_Pos)                 /*!< 0x00000002 */

+#define FDCAN_IR_RF0W             FDCAN_IR_RF0W_Msk                            /*!<Rx FIFO 0 Watermark Reached              */

+#define FDCAN_IR_RF0F_Pos         (2U)

+#define FDCAN_IR_RF0F_Msk         (0x1UL << FDCAN_IR_RF0F_Pos)                 /*!< 0x00000004 */

+#define FDCAN_IR_RF0F             FDCAN_IR_RF0F_Msk                            /*!<Rx FIFO 0 Full                           */

+#define FDCAN_IR_RF0L_Pos         (3U)

+#define FDCAN_IR_RF0L_Msk         (0x1UL << FDCAN_IR_RF0L_Pos)                 /*!< 0x00000008 */

+#define FDCAN_IR_RF0L             FDCAN_IR_RF0L_Msk                            /*!<Rx FIFO 0 Message Lost                   */

+#define FDCAN_IR_RF1N_Pos         (4U)

+#define FDCAN_IR_RF1N_Msk         (0x1UL << FDCAN_IR_RF1N_Pos)                 /*!< 0x00000010 */

+#define FDCAN_IR_RF1N             FDCAN_IR_RF1N_Msk                            /*!<Rx FIFO 1 New Message                    */

+#define FDCAN_IR_RF1W_Pos         (5U)

+#define FDCAN_IR_RF1W_Msk         (0x1UL << FDCAN_IR_RF1W_Pos)                 /*!< 0x00000020 */

+#define FDCAN_IR_RF1W             FDCAN_IR_RF1W_Msk                            /*!<Rx FIFO 1 Watermark Reached              */

+#define FDCAN_IR_RF1F_Pos         (6U)

+#define FDCAN_IR_RF1F_Msk         (0x1UL << FDCAN_IR_RF1F_Pos)                 /*!< 0x00000040 */

+#define FDCAN_IR_RF1F             FDCAN_IR_RF1F_Msk                            /*!<Rx FIFO 1 Full                           */

+#define FDCAN_IR_RF1L_Pos         (7U)

+#define FDCAN_IR_RF1L_Msk         (0x1UL << FDCAN_IR_RF1L_Pos)                 /*!< 0x00000080 */

+#define FDCAN_IR_RF1L             FDCAN_IR_RF1L_Msk                            /*!<Rx FIFO 1 Message Lost                   */

+#define FDCAN_IR_HPM_Pos          (8U)

+#define FDCAN_IR_HPM_Msk          (0x1UL << FDCAN_IR_HPM_Pos)                  /*!< 0x00000100 */

+#define FDCAN_IR_HPM              FDCAN_IR_HPM_Msk                             /*!<High Priority Message                    */

+#define FDCAN_IR_TC_Pos           (9U)

+#define FDCAN_IR_TC_Msk           (0x1UL << FDCAN_IR_TC_Pos)                   /*!< 0x00000200 */

+#define FDCAN_IR_TC               FDCAN_IR_TC_Msk                              /*!<Transmission Completed                   */

+#define FDCAN_IR_TCF_Pos          (10U)

+#define FDCAN_IR_TCF_Msk          (0x1UL << FDCAN_IR_TCF_Pos)                  /*!< 0x00000400 */

+#define FDCAN_IR_TCF              FDCAN_IR_TCF_Msk                             /*!<Transmission Cancellation Finished       */

+#define FDCAN_IR_TFE_Pos          (11U)

+#define FDCAN_IR_TFE_Msk          (0x1UL << FDCAN_IR_TFE_Pos)                  /*!< 0x00000800 */

+#define FDCAN_IR_TFE              FDCAN_IR_TFE_Msk                             /*!<Tx FIFO Empty                            */

+#define FDCAN_IR_TEFN_Pos         (12U)

+#define FDCAN_IR_TEFN_Msk         (0x1UL << FDCAN_IR_TEFN_Pos)                 /*!< 0x00001000 */

+#define FDCAN_IR_TEFN             FDCAN_IR_TEFN_Msk                            /*!<Tx Event FIFO New Entry                  */

+#define FDCAN_IR_TEFW_Pos         (13U)

+#define FDCAN_IR_TEFW_Msk         (0x1UL << FDCAN_IR_TEFW_Pos)                 /*!< 0x00002000 */

+#define FDCAN_IR_TEFW             FDCAN_IR_TEFW_Msk                            /*!<Tx Event FIFO Watermark Reached          */

+#define FDCAN_IR_TEFF_Pos         (14U)

+#define FDCAN_IR_TEFF_Msk         (0x1UL << FDCAN_IR_TEFF_Pos)                 /*!< 0x00004000 */

+#define FDCAN_IR_TEFF             FDCAN_IR_TEFF_Msk                            /*!<Tx Event FIFO Full                       */

+#define FDCAN_IR_TEFL_Pos         (15U)

+#define FDCAN_IR_TEFL_Msk         (0x1UL << FDCAN_IR_TEFL_Pos)                 /*!< 0x00008000 */

+#define FDCAN_IR_TEFL             FDCAN_IR_TEFL_Msk                            /*!<Tx Event FIFO Element Lost               */

+#define FDCAN_IR_TSW_Pos          (16U)

+#define FDCAN_IR_TSW_Msk          (0x1UL << FDCAN_IR_TSW_Pos)                  /*!< 0x00010000 */

+#define FDCAN_IR_TSW              FDCAN_IR_TSW_Msk                             /*!<Timestamp Wraparound                     */

+#define FDCAN_IR_MRAF_Pos         (17U)

+#define FDCAN_IR_MRAF_Msk         (0x1UL << FDCAN_IR_MRAF_Pos)                 /*!< 0x00020000 */

+#define FDCAN_IR_MRAF             FDCAN_IR_MRAF_Msk                            /*!<Message RAM Access Failure               */

+#define FDCAN_IR_TOO_Pos          (18U)

+#define FDCAN_IR_TOO_Msk          (0x1UL << FDCAN_IR_TOO_Pos)                  /*!< 0x00040000 */

+#define FDCAN_IR_TOO              FDCAN_IR_TOO_Msk                             /*!<Timeout Occurred                         */

+#define FDCAN_IR_DRX_Pos          (19U)

+#define FDCAN_IR_DRX_Msk          (0x1UL << FDCAN_IR_DRX_Pos)                  /*!< 0x00080000 */

+#define FDCAN_IR_DRX              FDCAN_IR_DRX_Msk                             /*!<Message stored to Dedicated Rx Buffer    */

+#define FDCAN_IR_ELO_Pos          (22U)

+#define FDCAN_IR_ELO_Msk          (0x1UL << FDCAN_IR_ELO_Pos)                  /*!< 0x00400000 */

+#define FDCAN_IR_ELO              FDCAN_IR_ELO_Msk                             /*!<Error Logging Overflow                   */

+#define FDCAN_IR_EP_Pos           (23U)

+#define FDCAN_IR_EP_Msk           (0x1UL << FDCAN_IR_EP_Pos)                   /*!< 0x00800000 */

+#define FDCAN_IR_EP               FDCAN_IR_EP_Msk                              /*!<Error Passive                            */

+#define FDCAN_IR_EW_Pos           (24U)

+#define FDCAN_IR_EW_Msk           (0x1UL << FDCAN_IR_EW_Pos)                   /*!< 0x01000000 */

+#define FDCAN_IR_EW               FDCAN_IR_EW_Msk                              /*!<Warning Status                           */

+#define FDCAN_IR_BO_Pos           (25U)

+#define FDCAN_IR_BO_Msk           (0x1UL << FDCAN_IR_BO_Pos)                   /*!< 0x02000000 */

+#define FDCAN_IR_BO               FDCAN_IR_BO_Msk                              /*!<Bus_Off Status                           */

+#define FDCAN_IR_WDI_Pos          (26U)

+#define FDCAN_IR_WDI_Msk          (0x1UL << FDCAN_IR_WDI_Pos)                  /*!< 0x04000000 */

+#define FDCAN_IR_WDI              FDCAN_IR_WDI_Msk                             /*!<Watchdog Interrupt                       */

+#define FDCAN_IR_PEA_Pos          (27U)

+#define FDCAN_IR_PEA_Msk          (0x1UL << FDCAN_IR_PEA_Pos)                  /*!< 0x08000000 */

+#define FDCAN_IR_PEA              FDCAN_IR_PEA_Msk                             /*!<Protocol Error in Arbitration Phase      */

+#define FDCAN_IR_PED_Pos          (28U)

+#define FDCAN_IR_PED_Msk          (0x1UL << FDCAN_IR_PED_Pos)                  /*!< 0x10000000 */

+#define FDCAN_IR_PED              FDCAN_IR_PED_Msk                             /*!<Protocol Error in Data Phase             */

+#define FDCAN_IR_ARA_Pos          (29U)

+#define FDCAN_IR_ARA_Msk          (0x1UL << FDCAN_IR_ARA_Pos)                  /*!< 0x20000000 */

+#define FDCAN_IR_ARA              FDCAN_IR_ARA_Msk                             /*!<Access to Reserved Address               */

+

+/*****************  Bit definition for FDCAN_IE register  **********************/

+#define FDCAN_IE_RF0NE_Pos        (0U)

+#define FDCAN_IE_RF0NE_Msk        (0x1UL << FDCAN_IE_RF0NE_Pos)                /*!< 0x00000001 */

+#define FDCAN_IE_RF0NE            FDCAN_IE_RF0NE_Msk                           /*!<Rx FIFO 0 New Message Enable                 */

+#define FDCAN_IE_RF0WE_Pos        (1U)

+#define FDCAN_IE_RF0WE_Msk        (0x1UL << FDCAN_IE_RF0WE_Pos)                /*!< 0x00000002 */

+#define FDCAN_IE_RF0WE            FDCAN_IE_RF0WE_Msk                           /*!<Rx FIFO 0 Watermark Reached Enable           */

+#define FDCAN_IE_RF0FE_Pos        (2U)

+#define FDCAN_IE_RF0FE_Msk        (0x1UL << FDCAN_IE_RF0FE_Pos)                /*!< 0x00000004 */

+#define FDCAN_IE_RF0FE            FDCAN_IE_RF0FE_Msk                           /*!<Rx FIFO 0 Full Enable                        */

+#define FDCAN_IE_RF0LE_Pos        (3U)

+#define FDCAN_IE_RF0LE_Msk        (0x1UL << FDCAN_IE_RF0LE_Pos)                /*!< 0x00000008 */

+#define FDCAN_IE_RF0LE            FDCAN_IE_RF0LE_Msk                           /*!<Rx FIFO 0 Message Lost Enable                */

+#define FDCAN_IE_RF1NE_Pos        (4U)

+#define FDCAN_IE_RF1NE_Msk        (0x1UL << FDCAN_IE_RF1NE_Pos)                /*!< 0x00000010 */

+#define FDCAN_IE_RF1NE            FDCAN_IE_RF1NE_Msk                           /*!<Rx FIFO 1 New Message Enable                 */

+#define FDCAN_IE_RF1WE_Pos        (5U)

+#define FDCAN_IE_RF1WE_Msk        (0x1UL << FDCAN_IE_RF1WE_Pos)                /*!< 0x00000020 */

+#define FDCAN_IE_RF1WE            FDCAN_IE_RF1WE_Msk                           /*!<Rx FIFO 1 Watermark Reached Enable           */

+#define FDCAN_IE_RF1FE_Pos        (6U)

+#define FDCAN_IE_RF1FE_Msk        (0x1UL << FDCAN_IE_RF1FE_Pos)                /*!< 0x00000040 */

+#define FDCAN_IE_RF1FE            FDCAN_IE_RF1FE_Msk                           /*!<Rx FIFO 1 Full Enable                        */

+#define FDCAN_IE_RF1LE_Pos        (7U)

+#define FDCAN_IE_RF1LE_Msk        (0x1UL << FDCAN_IE_RF1LE_Pos)                /*!< 0x00000080 */

+#define FDCAN_IE_RF1LE            FDCAN_IE_RF1LE_Msk                           /*!<Rx FIFO 1 Message Lost Enable                */

+#define FDCAN_IE_HPME_Pos         (8U)

+#define FDCAN_IE_HPME_Msk         (0x1UL << FDCAN_IE_HPME_Pos)                 /*!< 0x00000100 */

+#define FDCAN_IE_HPME             FDCAN_IE_HPME_Msk                            /*!<High Priority Message Enable                 */

+#define FDCAN_IE_TCE_Pos          (9U)

+#define FDCAN_IE_TCE_Msk          (0x1UL << FDCAN_IE_TCE_Pos)                  /*!< 0x00000200 */

+#define FDCAN_IE_TCE              FDCAN_IE_TCE_Msk                             /*!<Transmission Completed Enable                */

+#define FDCAN_IE_TCFE_Pos         (10U)

+#define FDCAN_IE_TCFE_Msk         (0x1UL << FDCAN_IE_TCFE_Pos)                 /*!< 0x00000400 */

+#define FDCAN_IE_TCFE             FDCAN_IE_TCFE_Msk                            /*!<Transmission Cancellation Finished Enable    */

+#define FDCAN_IE_TFEE_Pos         (11U)

+#define FDCAN_IE_TFEE_Msk         (0x1UL << FDCAN_IE_TFEE_Pos)                 /*!< 0x00000800 */

+#define FDCAN_IE_TFEE             FDCAN_IE_TFEE_Msk                            /*!<Tx FIFO Empty Enable                         */

+#define FDCAN_IE_TEFNE_Pos        (12U)

+#define FDCAN_IE_TEFNE_Msk        (0x1UL << FDCAN_IE_TEFNE_Pos)                /*!< 0x00001000 */

+#define FDCAN_IE_TEFNE            FDCAN_IE_TEFNE_Msk                           /*!<Tx Event FIFO New Entry Enable               */

+#define FDCAN_IE_TEFWE_Pos        (13U)

+#define FDCAN_IE_TEFWE_Msk        (0x1UL << FDCAN_IE_TEFWE_Pos)                /*!< 0x00002000 */

+#define FDCAN_IE_TEFWE            FDCAN_IE_TEFWE_Msk                           /*!<Tx Event FIFO Watermark Reached Enable       */

+#define FDCAN_IE_TEFFE_Pos        (14U)

+#define FDCAN_IE_TEFFE_Msk        (0x1UL << FDCAN_IE_TEFFE_Pos)                /*!< 0x00004000 */

+#define FDCAN_IE_TEFFE            FDCAN_IE_TEFFE_Msk                           /*!<Tx Event FIFO Full Enable                    */

+#define FDCAN_IE_TEFLE_Pos        (15U)

+#define FDCAN_IE_TEFLE_Msk        (0x1UL << FDCAN_IE_TEFLE_Pos)                /*!< 0x00008000 */

+#define FDCAN_IE_TEFLE            FDCAN_IE_TEFLE_Msk                           /*!<Tx Event FIFO Element Lost Enable            */

+#define FDCAN_IE_TSWE_Pos         (16U)

+#define FDCAN_IE_TSWE_Msk         (0x1UL << FDCAN_IE_TSWE_Pos)                 /*!< 0x00010000 */

+#define FDCAN_IE_TSWE             FDCAN_IE_TSWE_Msk                            /*!<Timestamp Wraparound Enable                  */

+#define FDCAN_IE_MRAFE_Pos        (17U)

+#define FDCAN_IE_MRAFE_Msk        (0x1UL << FDCAN_IE_MRAFE_Pos)                /*!< 0x00020000 */

+#define FDCAN_IE_MRAFE            FDCAN_IE_MRAFE_Msk                           /*!<Message RAM Access Failure Enable            */

+#define FDCAN_IE_TOOE_Pos         (18U)

+#define FDCAN_IE_TOOE_Msk         (0x1UL << FDCAN_IE_TOOE_Pos)                 /*!< 0x00040000 */

+#define FDCAN_IE_TOOE             FDCAN_IE_TOOE_Msk                            /*!<Timeout Occurred Enable                      */

+#define FDCAN_IE_DRXE_Pos         (19U)

+#define FDCAN_IE_DRXE_Msk         (0x1UL << FDCAN_IE_DRXE_Pos)                 /*!< 0x00080000 */

+#define FDCAN_IE_DRXE             FDCAN_IE_DRXE_Msk                            /*!<Message stored to Dedicated Rx Buffer Enable */

+#define FDCAN_IE_BECE_Pos         (20U)

+#define FDCAN_IE_BECE_Msk         (0x1UL << FDCAN_IE_BECE_Pos)                 /*!< 0x00100000 */

+#define FDCAN_IE_BECE             FDCAN_IE_BECE_Msk                            /*!<Bit Error Corrected Interrupt Enable         */

+#define FDCAN_IE_BEUE_Pos         (21U)

+#define FDCAN_IE_BEUE_Msk         (0x1UL << FDCAN_IE_BEUE_Pos)                 /*!< 0x00200000 */

+#define FDCAN_IE_BEUE             FDCAN_IE_BEUE_Msk                            /*!<Bit Error Uncorrected Interrupt Enable       */

+#define FDCAN_IE_ELOE_Pos         (22U)

+#define FDCAN_IE_ELOE_Msk         (0x1UL << FDCAN_IE_ELOE_Pos)                 /*!< 0x00400000 */

+#define FDCAN_IE_ELOE             FDCAN_IE_ELOE_Msk                            /*!<Error Logging Overflow Enable                */

+#define FDCAN_IE_EPE_Pos          (23U)

+#define FDCAN_IE_EPE_Msk          (0x1UL << FDCAN_IE_EPE_Pos)                  /*!< 0x00800000 */

+#define FDCAN_IE_EPE              FDCAN_IE_EPE_Msk                             /*!<Error Passive Enable                         */

+#define FDCAN_IE_EWE_Pos          (24U)

+#define FDCAN_IE_EWE_Msk          (0x1UL << FDCAN_IE_EWE_Pos)                  /*!< 0x01000000 */

+#define FDCAN_IE_EWE              FDCAN_IE_EWE_Msk                             /*!<Warning Status Enable                        */

+#define FDCAN_IE_BOE_Pos          (25U)

+#define FDCAN_IE_BOE_Msk          (0x1UL << FDCAN_IE_BOE_Pos)                  /*!< 0x02000000 */

+#define FDCAN_IE_BOE              FDCAN_IE_BOE_Msk                             /*!<Bus_Off Status Enable                        */

+#define FDCAN_IE_WDIE_Pos         (26U)

+#define FDCAN_IE_WDIE_Msk         (0x1UL << FDCAN_IE_WDIE_Pos)                 /*!< 0x04000000 */

+#define FDCAN_IE_WDIE             FDCAN_IE_WDIE_Msk                            /*!<Watchdog Interrupt Enable                    */

+#define FDCAN_IE_PEAE_Pos         (27U)

+#define FDCAN_IE_PEAE_Msk         (0x1UL << FDCAN_IE_PEAE_Pos)                 /*!< 0x08000000 */

+#define FDCAN_IE_PEAE             FDCAN_IE_PEAE_Msk                            /*!<Protocol Error in Arbitration Phase Enable   */

+#define FDCAN_IE_PEDE_Pos         (28U)

+#define FDCAN_IE_PEDE_Msk         (0x1UL << FDCAN_IE_PEDE_Pos)                 /*!< 0x10000000 */

+#define FDCAN_IE_PEDE             FDCAN_IE_PEDE_Msk                            /*!<Protocol Error in Data Phase Enable          */

+#define FDCAN_IE_ARAE_Pos         (29U)

+#define FDCAN_IE_ARAE_Msk         (0x1UL << FDCAN_IE_ARAE_Pos)                 /*!< 0x20000000 */

+#define FDCAN_IE_ARAE             FDCAN_IE_ARAE_Msk                            /*!<Access to Reserved Address Enable            */

+

+/*****************  Bit definition for FDCAN_ILS register  **********************/

+#define FDCAN_ILS_RF0NL_Pos       (0U)

+#define FDCAN_ILS_RF0NL_Msk       (0x1UL << FDCAN_ILS_RF0NL_Pos)               /*!< 0x00000001 */

+#define FDCAN_ILS_RF0NL           FDCAN_ILS_RF0NL_Msk                          /*!<Rx FIFO 0 New Message Line                  */

+#define FDCAN_ILS_RF0WL_Pos       (1U)

+#define FDCAN_ILS_RF0WL_Msk       (0x1UL << FDCAN_ILS_RF0WL_Pos)               /*!< 0x00000002 */

+#define FDCAN_ILS_RF0WL           FDCAN_ILS_RF0WL_Msk                          /*!<Rx FIFO 0 Watermark Reached Line            */

+#define FDCAN_ILS_RF0FL_Pos       (2U)

+#define FDCAN_ILS_RF0FL_Msk       (0x1UL << FDCAN_ILS_RF0FL_Pos)               /*!< 0x00000004 */

+#define FDCAN_ILS_RF0FL           FDCAN_ILS_RF0FL_Msk                          /*!<Rx FIFO 0 Full Line                         */

+#define FDCAN_ILS_RF0LL_Pos       (3U)

+#define FDCAN_ILS_RF0LL_Msk       (0x1UL << FDCAN_ILS_RF0LL_Pos)               /*!< 0x00000008 */

+#define FDCAN_ILS_RF0LL           FDCAN_ILS_RF0LL_Msk                          /*!<Rx FIFO 0 Message Lost Line                 */

+#define FDCAN_ILS_RF1NL_Pos       (4U)

+#define FDCAN_ILS_RF1NL_Msk       (0x1UL << FDCAN_ILS_RF1NL_Pos)               /*!< 0x00000010 */

+#define FDCAN_ILS_RF1NL           FDCAN_ILS_RF1NL_Msk                          /*!<Rx FIFO 1 New Message Line                  */

+#define FDCAN_ILS_RF1WL_Pos       (5U)

+#define FDCAN_ILS_RF1WL_Msk       (0x1UL << FDCAN_ILS_RF1WL_Pos)               /*!< 0x00000020 */

+#define FDCAN_ILS_RF1WL           FDCAN_ILS_RF1WL_Msk                          /*!<Rx FIFO 1 Watermark Reached Line            */

+#define FDCAN_ILS_RF1FL_Pos       (6U)

+#define FDCAN_ILS_RF1FL_Msk       (0x1UL << FDCAN_ILS_RF1FL_Pos)               /*!< 0x00000040 */

+#define FDCAN_ILS_RF1FL           FDCAN_ILS_RF1FL_Msk                          /*!<Rx FIFO 1 Full Line                         */

+#define FDCAN_ILS_RF1LL_Pos       (7U)

+#define FDCAN_ILS_RF1LL_Msk       (0x1UL << FDCAN_ILS_RF1LL_Pos)               /*!< 0x00000080 */

+#define FDCAN_ILS_RF1LL           FDCAN_ILS_RF1LL_Msk                          /*!<Rx FIFO 1 Message Lost Line                 */

+#define FDCAN_ILS_HPML_Pos        (8U)

+#define FDCAN_ILS_HPML_Msk        (0x1UL << FDCAN_ILS_HPML_Pos)                /*!< 0x00000100 */

+#define FDCAN_ILS_HPML            FDCAN_ILS_HPML_Msk                           /*!<High Priority Message Line                  */

+#define FDCAN_ILS_TCL_Pos         (9U)

+#define FDCAN_ILS_TCL_Msk         (0x1UL << FDCAN_ILS_TCL_Pos)                 /*!< 0x00000200 */

+#define FDCAN_ILS_TCL             FDCAN_ILS_TCL_Msk                            /*!<Transmission Completed Line                 */

+#define FDCAN_ILS_TCFL_Pos        (10U)

+#define FDCAN_ILS_TCFL_Msk        (0x1UL << FDCAN_ILS_TCFL_Pos)                /*!< 0x00000400 */

+#define FDCAN_ILS_TCFL            FDCAN_ILS_TCFL_Msk                           /*!<Transmission Cancellation Finished Line     */

+#define FDCAN_ILS_TFEL_Pos        (11U)

+#define FDCAN_ILS_TFEL_Msk        (0x1UL << FDCAN_ILS_TFEL_Pos)                /*!< 0x00000800 */

+#define FDCAN_ILS_TFEL            FDCAN_ILS_TFEL_Msk                           /*!<Tx FIFO Empty Line                          */

+#define FDCAN_ILS_TEFNL_Pos       (12U)

+#define FDCAN_ILS_TEFNL_Msk       (0x1UL << FDCAN_ILS_TEFNL_Pos)               /*!< 0x00001000 */

+#define FDCAN_ILS_TEFNL           FDCAN_ILS_TEFNL_Msk                          /*!<Tx Event FIFO New Entry Line                */

+#define FDCAN_ILS_TEFWL_Pos       (13U)

+#define FDCAN_ILS_TEFWL_Msk       (0x1UL << FDCAN_ILS_TEFWL_Pos)               /*!< 0x00002000 */

+#define FDCAN_ILS_TEFWL           FDCAN_ILS_TEFWL_Msk                          /*!<Tx Event FIFO Watermark Reached Line        */

+#define FDCAN_ILS_TEFFL_Pos       (14U)

+#define FDCAN_ILS_TEFFL_Msk       (0x1UL << FDCAN_ILS_TEFFL_Pos)               /*!< 0x00004000 */

+#define FDCAN_ILS_TEFFL           FDCAN_ILS_TEFFL_Msk                          /*!<Tx Event FIFO Full Line                     */

+#define FDCAN_ILS_TEFLL_Pos       (15U)

+#define FDCAN_ILS_TEFLL_Msk       (0x1UL << FDCAN_ILS_TEFLL_Pos)               /*!< 0x00008000 */

+#define FDCAN_ILS_TEFLL           FDCAN_ILS_TEFLL_Msk                          /*!<Tx Event FIFO Element Lost Line             */

+#define FDCAN_ILS_TSWL_Pos        (16U)

+#define FDCAN_ILS_TSWL_Msk        (0x1UL << FDCAN_ILS_TSWL_Pos)                /*!< 0x00010000 */

+#define FDCAN_ILS_TSWL            FDCAN_ILS_TSWL_Msk                           /*!<Timestamp Wraparound Line                   */

+#define FDCAN_ILS_MRAFE_Pos       (17U)

+#define FDCAN_ILS_MRAFE_Msk       (0x1UL << FDCAN_ILS_MRAFE_Pos)               /*!< 0x00020000 */

+#define FDCAN_ILS_MRAFE           FDCAN_ILS_MRAFE_Msk                          /*!<Message RAM Access Failure Line             */

+#define FDCAN_ILS_TOOE_Pos        (18U)

+#define FDCAN_ILS_TOOE_Msk        (0x1UL << FDCAN_ILS_TOOE_Pos)                /*!< 0x00040000 */

+#define FDCAN_ILS_TOOE            FDCAN_ILS_TOOE_Msk                           /*!<Timeout Occurred Line                       */

+#define FDCAN_ILS_DRXE_Pos        (19U)

+#define FDCAN_ILS_DRXE_Msk        (0x1UL << FDCAN_ILS_DRXE_Pos)                /*!< 0x00080000 */

+#define FDCAN_ILS_DRXE            FDCAN_ILS_DRXE_Msk                           /*!<Message stored to Dedicated Rx Buffer Line  */

+#define FDCAN_ILS_BECE_Pos        (20U)

+#define FDCAN_ILS_BECE_Msk        (0x1UL << FDCAN_ILS_BECE_Pos)                /*!< 0x00100000 */

+#define FDCAN_ILS_BECE            FDCAN_ILS_BECE_Msk                           /*!<Bit Error Corrected Interrupt Line          */

+#define FDCAN_ILS_BEUE_Pos        (21U)

+#define FDCAN_ILS_BEUE_Msk        (0x1UL << FDCAN_ILS_BEUE_Pos)                /*!< 0x00200000 */

+#define FDCAN_ILS_BEUE            FDCAN_ILS_BEUE_Msk                           /*!<Bit Error Uncorrected Interrupt Line        */

+#define FDCAN_ILS_ELOE_Pos        (22U)

+#define FDCAN_ILS_ELOE_Msk        (0x1UL << FDCAN_ILS_ELOE_Pos)                /*!< 0x00400000 */

+#define FDCAN_ILS_ELOE            FDCAN_ILS_ELOE_Msk                           /*!<Error Logging Overflow Line                 */

+#define FDCAN_ILS_EPE_Pos         (23U)

+#define FDCAN_ILS_EPE_Msk         (0x1UL << FDCAN_ILS_EPE_Pos)                 /*!< 0x00800000 */

+#define FDCAN_ILS_EPE             FDCAN_ILS_EPE_Msk                            /*!<Error Passive Line                          */

+#define FDCAN_ILS_EWE_Pos         (24U)

+#define FDCAN_ILS_EWE_Msk         (0x1UL << FDCAN_ILS_EWE_Pos)                 /*!< 0x01000000 */

+#define FDCAN_ILS_EWE             FDCAN_ILS_EWE_Msk                            /*!<Warning Status Line                         */

+#define FDCAN_ILS_BOE_Pos         (25U)

+#define FDCAN_ILS_BOE_Msk         (0x1UL << FDCAN_ILS_BOE_Pos)                 /*!< 0x02000000 */

+#define FDCAN_ILS_BOE             FDCAN_ILS_BOE_Msk                            /*!<Bus_Off Status Line                         */

+#define FDCAN_ILS_WDIE_Pos        (26U)

+#define FDCAN_ILS_WDIE_Msk        (0x1UL << FDCAN_ILS_WDIE_Pos)                /*!< 0x04000000 */

+#define FDCAN_ILS_WDIE            FDCAN_ILS_WDIE_Msk                           /*!<Watchdog Interrupt Line                     */

+#define FDCAN_ILS_PEAE_Pos        (27U)

+#define FDCAN_ILS_PEAE_Msk        (0x1UL << FDCAN_ILS_PEAE_Pos)                /*!< 0x08000000 */

+#define FDCAN_ILS_PEAE            FDCAN_ILS_PEAE_Msk                           /*!<Protocol Error in Arbitration Phase Line    */

+#define FDCAN_ILS_PEDE_Pos        (28U)

+#define FDCAN_ILS_PEDE_Msk        (0x1UL << FDCAN_ILS_PEDE_Pos)                /*!< 0x10000000 */

+#define FDCAN_ILS_PEDE            FDCAN_ILS_PEDE_Msk                           /*!<Protocol Error in Data Phase Line           */

+#define FDCAN_ILS_ARAE_Pos        (29U)

+#define FDCAN_ILS_ARAE_Msk        (0x1UL << FDCAN_ILS_ARAE_Pos)                /*!< 0x20000000 */

+#define FDCAN_ILS_ARAE            FDCAN_ILS_ARAE_Msk                           /*!<Access to Reserved Address Line             */

+

+/*****************  Bit definition for FDCAN_ILE register  **********************/

+#define FDCAN_ILE_EINT0_Pos       (0U)

+#define FDCAN_ILE_EINT0_Msk       (0x1UL << FDCAN_ILE_EINT0_Pos)               /*!< 0x00000001 */

+#define FDCAN_ILE_EINT0           FDCAN_ILE_EINT0_Msk                          /*!<Enable Interrupt Line 0                   */

+#define FDCAN_ILE_EINT1_Pos       (1U)

+#define FDCAN_ILE_EINT1_Msk       (0x1UL << FDCAN_ILE_EINT1_Pos)               /*!< 0x00000002 */

+#define FDCAN_ILE_EINT1           FDCAN_ILE_EINT1_Msk                          /*!<Enable Interrupt Line 1                   */

+

+/*****************  Bit definition for FDCAN_GFC register  **********************/

+#define FDCAN_GFC_RRFE_Pos        (0U)

+#define FDCAN_GFC_RRFE_Msk        (0x1UL << FDCAN_GFC_RRFE_Pos)                /*!< 0x00000001 */

+#define FDCAN_GFC_RRFE            FDCAN_GFC_RRFE_Msk                           /*!<Reject Remote Frames Extended             */

+#define FDCAN_GFC_RRFS_Pos        (1U)

+#define FDCAN_GFC_RRFS_Msk        (0x1UL << FDCAN_GFC_RRFS_Pos)                /*!< 0x00000002 */

+#define FDCAN_GFC_RRFS            FDCAN_GFC_RRFS_Msk                           /*!<Reject Remote Frames Standard             */

+#define FDCAN_GFC_ANFE_Pos        (2U)

+#define FDCAN_GFC_ANFE_Msk        (0x3UL << FDCAN_GFC_ANFE_Pos)                /*!< 0x0000000C */

+#define FDCAN_GFC_ANFE            FDCAN_GFC_ANFE_Msk                           /*!<Accept Non-matching Frames Extended       */

+#define FDCAN_GFC_ANFS_Pos        (4U)

+#define FDCAN_GFC_ANFS_Msk        (0x3UL << FDCAN_GFC_ANFS_Pos)                /*!< 0x00000030 */

+#define FDCAN_GFC_ANFS            FDCAN_GFC_ANFS_Msk                           /*!<Accept Non-matching Frames Standard       */

+

+/*****************  Bit definition for FDCAN_SIDFC register  ********************/

+#define FDCAN_SIDFC_FLSSA_Pos     (2U)

+#define FDCAN_SIDFC_FLSSA_Msk     (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)          /*!< 0x0000FFFC */

+#define FDCAN_SIDFC_FLSSA         FDCAN_SIDFC_FLSSA_Msk                        /*!<Filter List Standard Start Address        */

+#define FDCAN_SIDFC_LSS_Pos       (16U)

+#define FDCAN_SIDFC_LSS_Msk       (0xFFUL << FDCAN_SIDFC_LSS_Pos)              /*!< 0x00FF0000 */

+#define FDCAN_SIDFC_LSS           FDCAN_SIDFC_LSS_Msk                          /*!<List Size Standard                        */

+

+/*****************  Bit definition for FDCAN_XIDFC register  ********************/

+#define FDCAN_XIDFC_FLESA_Pos     (2U)

+#define FDCAN_XIDFC_FLESA_Msk     (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)          /*!< 0x0000FFFC */

+#define FDCAN_XIDFC_FLESA         FDCAN_XIDFC_FLESA_Msk                        /*!<Filter List Standard Start Address        */

+#define FDCAN_XIDFC_LSE_Pos       (16U)

+#define FDCAN_XIDFC_LSE_Msk       (0x7FUL << FDCAN_XIDFC_LSE_Pos)              /*!< 0x007F0000 */

+#define FDCAN_XIDFC_LSE           FDCAN_XIDFC_LSE_Msk                          /*!<List Size Extended                        */

+

+/*****************  Bit definition for FDCAN_XIDAM register  ********************/

+#define FDCAN_XIDAM_EIDM_Pos      (0U)

+#define FDCAN_XIDAM_EIDM_Msk      (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)       /*!< 0x1FFFFFFF */

+#define FDCAN_XIDAM_EIDM          FDCAN_XIDAM_EIDM_Msk                         /*!<Extended ID Mask                          */

+

+/*****************  Bit definition for FDCAN_HPMS register  *********************/

+#define FDCAN_HPMS_BIDX_Pos       (0U)

+#define FDCAN_HPMS_BIDX_Msk       (0x3FUL << FDCAN_HPMS_BIDX_Pos)              /*!< 0x0000003F */

+#define FDCAN_HPMS_BIDX           FDCAN_HPMS_BIDX_Msk                          /*!<Buffer Index                              */

+#define FDCAN_HPMS_MSI_Pos        (6U)

+#define FDCAN_HPMS_MSI_Msk        (0x3UL << FDCAN_HPMS_MSI_Pos)                /*!< 0x000000C0 */

+#define FDCAN_HPMS_MSI            FDCAN_HPMS_MSI_Msk                           /*!<Message Storage Indicator                 */

+#define FDCAN_HPMS_FIDX_Pos       (8U)

+#define FDCAN_HPMS_FIDX_Msk       (0x7FUL << FDCAN_HPMS_FIDX_Pos)              /*!< 0x00007F00 */

+#define FDCAN_HPMS_FIDX           FDCAN_HPMS_FIDX_Msk                          /*!<Filter Index                              */

+#define FDCAN_HPMS_FLST_Pos       (15U)

+#define FDCAN_HPMS_FLST_Msk       (0x1UL << FDCAN_HPMS_FLST_Pos)               /*!< 0x00008000 */

+#define FDCAN_HPMS_FLST           FDCAN_HPMS_FLST_Msk                          /*!<Filter List                               */

+

+/*****************  Bit definition for FDCAN_NDAT1 register  ********************/

+#define FDCAN_NDAT1_ND0_Pos       (0U)

+#define FDCAN_NDAT1_ND0_Msk       (0x1UL << FDCAN_NDAT1_ND0_Pos)               /*!< 0x00000001 */

+#define FDCAN_NDAT1_ND0           FDCAN_NDAT1_ND0_Msk                          /*!<New Data flag of Rx Buffer 0              */

+#define FDCAN_NDAT1_ND1_Pos       (1U)

+#define FDCAN_NDAT1_ND1_Msk       (0x1UL << FDCAN_NDAT1_ND1_Pos)               /*!< 0x00000002 */

+#define FDCAN_NDAT1_ND1           FDCAN_NDAT1_ND1_Msk                          /*!<New Data flag of Rx Buffer 1              */

+#define FDCAN_NDAT1_ND2_Pos       (2U)

+#define FDCAN_NDAT1_ND2_Msk       (0x1UL << FDCAN_NDAT1_ND2_Pos)               /*!< 0x00000004 */

+#define FDCAN_NDAT1_ND2           FDCAN_NDAT1_ND2_Msk                          /*!<New Data flag of Rx Buffer 2              */

+#define FDCAN_NDAT1_ND3_Pos       (3U)

+#define FDCAN_NDAT1_ND3_Msk       (0x1UL << FDCAN_NDAT1_ND3_Pos)               /*!< 0x00000008 */

+#define FDCAN_NDAT1_ND3           FDCAN_NDAT1_ND3_Msk                          /*!<New Data flag of Rx Buffer 3              */

+#define FDCAN_NDAT1_ND4_Pos       (4U)

+#define FDCAN_NDAT1_ND4_Msk       (0x1UL << FDCAN_NDAT1_ND4_Pos)               /*!< 0x00000010 */

+#define FDCAN_NDAT1_ND4           FDCAN_NDAT1_ND4_Msk                          /*!<New Data flag of Rx Buffer 4              */

+#define FDCAN_NDAT1_ND5_Pos       (5U)

+#define FDCAN_NDAT1_ND5_Msk       (0x1UL << FDCAN_NDAT1_ND5_Pos)               /*!< 0x00000020 */

+#define FDCAN_NDAT1_ND5           FDCAN_NDAT1_ND5_Msk                          /*!<New Data flag of Rx Buffer 5              */

+#define FDCAN_NDAT1_ND6_Pos       (6U)

+#define FDCAN_NDAT1_ND6_Msk       (0x1UL << FDCAN_NDAT1_ND6_Pos)               /*!< 0x00000040 */

+#define FDCAN_NDAT1_ND6           FDCAN_NDAT1_ND6_Msk                          /*!<New Data flag of Rx Buffer 6              */

+#define FDCAN_NDAT1_ND7_Pos       (7U)

+#define FDCAN_NDAT1_ND7_Msk       (0x1UL << FDCAN_NDAT1_ND7_Pos)               /*!< 0x00000080 */

+#define FDCAN_NDAT1_ND7           FDCAN_NDAT1_ND7_Msk                          /*!<New Data flag of Rx Buffer 7              */

+#define FDCAN_NDAT1_ND8_Pos       (8U)

+#define FDCAN_NDAT1_ND8_Msk       (0x1UL << FDCAN_NDAT1_ND8_Pos)               /*!< 0x00000100 */

+#define FDCAN_NDAT1_ND8           FDCAN_NDAT1_ND8_Msk                          /*!<New Data flag of Rx Buffer 8              */

+#define FDCAN_NDAT1_ND9_Pos       (9U)

+#define FDCAN_NDAT1_ND9_Msk       (0x1UL << FDCAN_NDAT1_ND9_Pos)               /*!< 0x00000200 */

+#define FDCAN_NDAT1_ND9           FDCAN_NDAT1_ND9_Msk                          /*!<New Data flag of Rx Buffer 9              */

+#define FDCAN_NDAT1_ND10_Pos      (10U)

+#define FDCAN_NDAT1_ND10_Msk      (0x1UL << FDCAN_NDAT1_ND10_Pos)              /*!< 0x00000400 */

+#define FDCAN_NDAT1_ND10          FDCAN_NDAT1_ND10_Msk                         /*!<New Data flag of Rx Buffer 10             */

+#define FDCAN_NDAT1_ND11_Pos      (11U)

+#define FDCAN_NDAT1_ND11_Msk      (0x1UL << FDCAN_NDAT1_ND11_Pos)              /*!< 0x00000800 */

+#define FDCAN_NDAT1_ND11          FDCAN_NDAT1_ND11_Msk                         /*!<New Data flag of Rx Buffer 11             */

+#define FDCAN_NDAT1_ND12_Pos      (12U)

+#define FDCAN_NDAT1_ND12_Msk      (0x1UL << FDCAN_NDAT1_ND12_Pos)              /*!< 0x00001000 */

+#define FDCAN_NDAT1_ND12          FDCAN_NDAT1_ND12_Msk                         /*!<New Data flag of Rx Buffer 12             */

+#define FDCAN_NDAT1_ND13_Pos      (13U)

+#define FDCAN_NDAT1_ND13_Msk      (0x1UL << FDCAN_NDAT1_ND13_Pos)              /*!< 0x00002000 */

+#define FDCAN_NDAT1_ND13          FDCAN_NDAT1_ND13_Msk                         /*!<New Data flag of Rx Buffer 13             */

+#define FDCAN_NDAT1_ND14_Pos      (14U)

+#define FDCAN_NDAT1_ND14_Msk      (0x1UL << FDCAN_NDAT1_ND14_Pos)              /*!< 0x00004000 */

+#define FDCAN_NDAT1_ND14          FDCAN_NDAT1_ND14_Msk                         /*!<New Data flag of Rx Buffer 14             */

+#define FDCAN_NDAT1_ND15_Pos      (15U)

+#define FDCAN_NDAT1_ND15_Msk      (0x1UL << FDCAN_NDAT1_ND15_Pos)              /*!< 0x00008000 */

+#define FDCAN_NDAT1_ND15          FDCAN_NDAT1_ND15_Msk                         /*!<New Data flag of Rx Buffer 15             */

+#define FDCAN_NDAT1_ND16_Pos      (16U)

+#define FDCAN_NDAT1_ND16_Msk      (0x1UL << FDCAN_NDAT1_ND16_Pos)              /*!< 0x00010000 */

+#define FDCAN_NDAT1_ND16          FDCAN_NDAT1_ND16_Msk                         /*!<New Data flag of Rx Buffer 16             */

+#define FDCAN_NDAT1_ND17_Pos      (17U)

+#define FDCAN_NDAT1_ND17_Msk      (0x1UL << FDCAN_NDAT1_ND17_Pos)              /*!< 0x00020000 */

+#define FDCAN_NDAT1_ND17          FDCAN_NDAT1_ND17_Msk                         /*!<New Data flag of Rx Buffer 17             */

+#define FDCAN_NDAT1_ND18_Pos      (18U)

+#define FDCAN_NDAT1_ND18_Msk      (0x1UL << FDCAN_NDAT1_ND18_Pos)              /*!< 0x00040000 */

+#define FDCAN_NDAT1_ND18          FDCAN_NDAT1_ND18_Msk                         /*!<New Data flag of Rx Buffer 18             */

+#define FDCAN_NDAT1_ND19_Pos      (19U)

+#define FDCAN_NDAT1_ND19_Msk      (0x1UL << FDCAN_NDAT1_ND19_Pos)              /*!< 0x00080000 */

+#define FDCAN_NDAT1_ND19          FDCAN_NDAT1_ND19_Msk                         /*!<New Data flag of Rx Buffer 19             */

+#define FDCAN_NDAT1_ND20_Pos      (20U)

+#define FDCAN_NDAT1_ND20_Msk      (0x1UL << FDCAN_NDAT1_ND20_Pos)              /*!< 0x00100000 */

+#define FDCAN_NDAT1_ND20          FDCAN_NDAT1_ND20_Msk                         /*!<New Data flag of Rx Buffer 20             */

+#define FDCAN_NDAT1_ND21_Pos      (21U)

+#define FDCAN_NDAT1_ND21_Msk      (0x1UL << FDCAN_NDAT1_ND21_Pos)              /*!< 0x00200000 */

+#define FDCAN_NDAT1_ND21          FDCAN_NDAT1_ND21_Msk                         /*!<New Data flag of Rx Buffer 21             */

+#define FDCAN_NDAT1_ND22_Pos      (22U)

+#define FDCAN_NDAT1_ND22_Msk      (0x1UL << FDCAN_NDAT1_ND22_Pos)              /*!< 0x00400000 */

+#define FDCAN_NDAT1_ND22          FDCAN_NDAT1_ND22_Msk                         /*!<New Data flag of Rx Buffer 22             */

+#define FDCAN_NDAT1_ND23_Pos      (23U)

+#define FDCAN_NDAT1_ND23_Msk      (0x1UL << FDCAN_NDAT1_ND23_Pos)              /*!< 0x00800000 */

+#define FDCAN_NDAT1_ND23          FDCAN_NDAT1_ND23_Msk                         /*!<New Data flag of Rx Buffer 23             */

+#define FDCAN_NDAT1_ND24_Pos      (24U)

+#define FDCAN_NDAT1_ND24_Msk      (0x1UL << FDCAN_NDAT1_ND24_Pos)              /*!< 0x01000000 */

+#define FDCAN_NDAT1_ND24          FDCAN_NDAT1_ND24_Msk                         /*!<New Data flag of Rx Buffer 24             */

+#define FDCAN_NDAT1_ND25_Pos      (25U)

+#define FDCAN_NDAT1_ND25_Msk      (0x1UL << FDCAN_NDAT1_ND25_Pos)              /*!< 0x02000000 */

+#define FDCAN_NDAT1_ND25          FDCAN_NDAT1_ND25_Msk                         /*!<New Data flag of Rx Buffer 25             */

+#define FDCAN_NDAT1_ND26_Pos      (26U)

+#define FDCAN_NDAT1_ND26_Msk      (0x1UL << FDCAN_NDAT1_ND26_Pos)              /*!< 0x04000000 */

+#define FDCAN_NDAT1_ND26          FDCAN_NDAT1_ND26_Msk                         /*!<New Data flag of Rx Buffer 26             */

+#define FDCAN_NDAT1_ND27_Pos      (27U)

+#define FDCAN_NDAT1_ND27_Msk      (0x1UL << FDCAN_NDAT1_ND27_Pos)              /*!< 0x08000000 */

+#define FDCAN_NDAT1_ND27          FDCAN_NDAT1_ND27_Msk                         /*!<New Data flag of Rx Buffer 27             */

+#define FDCAN_NDAT1_ND28_Pos      (28U)

+#define FDCAN_NDAT1_ND28_Msk      (0x1UL << FDCAN_NDAT1_ND28_Pos)              /*!< 0x10000000 */

+#define FDCAN_NDAT1_ND28          FDCAN_NDAT1_ND28_Msk                         /*!<New Data flag of Rx Buffer 28             */

+#define FDCAN_NDAT1_ND29_Pos      (29U)

+#define FDCAN_NDAT1_ND29_Msk      (0x1UL << FDCAN_NDAT1_ND29_Pos)              /*!< 0x20000000 */

+#define FDCAN_NDAT1_ND29          FDCAN_NDAT1_ND29_Msk                         /*!<New Data flag of Rx Buffer 29             */

+#define FDCAN_NDAT1_ND30_Pos      (30U)

+#define FDCAN_NDAT1_ND30_Msk      (0x1UL << FDCAN_NDAT1_ND30_Pos)              /*!< 0x40000000 */

+#define FDCAN_NDAT1_ND30          FDCAN_NDAT1_ND30_Msk                         /*!<New Data flag of Rx Buffer 30             */

+#define FDCAN_NDAT1_ND31_Pos      (31U)

+#define FDCAN_NDAT1_ND31_Msk      (0x1UL << FDCAN_NDAT1_ND31_Pos)              /*!< 0x80000000 */

+#define FDCAN_NDAT1_ND31          FDCAN_NDAT1_ND31_Msk                         /*!<New Data flag of Rx Buffer 31             */

+

+/*****************  Bit definition for FDCAN_NDAT2 register  ********************/

+#define FDCAN_NDAT2_ND32_Pos      (0U)

+#define FDCAN_NDAT2_ND32_Msk      (0x1UL << FDCAN_NDAT2_ND32_Pos)              /*!< 0x00000001 */

+#define FDCAN_NDAT2_ND32          FDCAN_NDAT2_ND32_Msk                         /*!<New Data flag of Rx Buffer 32             */

+#define FDCAN_NDAT2_ND33_Pos      (1U)

+#define FDCAN_NDAT2_ND33_Msk      (0x1UL << FDCAN_NDAT2_ND33_Pos)              /*!< 0x00000002 */

+#define FDCAN_NDAT2_ND33          FDCAN_NDAT2_ND33_Msk                         /*!<New Data flag of Rx Buffer 33             */

+#define FDCAN_NDAT2_ND34_Pos      (2U)

+#define FDCAN_NDAT2_ND34_Msk      (0x1UL << FDCAN_NDAT2_ND34_Pos)              /*!< 0x00000004 */

+#define FDCAN_NDAT2_ND34          FDCAN_NDAT2_ND34_Msk                         /*!<New Data flag of Rx Buffer 34             */

+#define FDCAN_NDAT2_ND35_Pos      (3U)

+#define FDCAN_NDAT2_ND35_Msk      (0x1UL << FDCAN_NDAT2_ND35_Pos)              /*!< 0x00000008 */

+#define FDCAN_NDAT2_ND35          FDCAN_NDAT2_ND35_Msk                         /*!<New Data flag of Rx Buffer 35             */

+#define FDCAN_NDAT2_ND36_Pos      (4U)

+#define FDCAN_NDAT2_ND36_Msk      (0x1UL << FDCAN_NDAT2_ND36_Pos)              /*!< 0x00000010 */

+#define FDCAN_NDAT2_ND36          FDCAN_NDAT2_ND36_Msk                         /*!<New Data flag of Rx Buffer 36             */

+#define FDCAN_NDAT2_ND37_Pos      (5U)

+#define FDCAN_NDAT2_ND37_Msk      (0x1UL << FDCAN_NDAT2_ND37_Pos)              /*!< 0x00000020 */

+#define FDCAN_NDAT2_ND37          FDCAN_NDAT2_ND37_Msk                         /*!<New Data flag of Rx Buffer 37             */

+#define FDCAN_NDAT2_ND38_Pos      (6U)

+#define FDCAN_NDAT2_ND38_Msk      (0x1UL << FDCAN_NDAT2_ND38_Pos)              /*!< 0x00000040 */

+#define FDCAN_NDAT2_ND38          FDCAN_NDAT2_ND38_Msk                         /*!<New Data flag of Rx Buffer 38             */

+#define FDCAN_NDAT2_ND39_Pos      (7U)

+#define FDCAN_NDAT2_ND39_Msk      (0x1UL << FDCAN_NDAT2_ND39_Pos)              /*!< 0x00000080 */

+#define FDCAN_NDAT2_ND39          FDCAN_NDAT2_ND39_Msk                         /*!<New Data flag of Rx Buffer 39             */

+#define FDCAN_NDAT2_ND40_Pos      (8U)

+#define FDCAN_NDAT2_ND40_Msk      (0x1UL << FDCAN_NDAT2_ND40_Pos)              /*!< 0x00000100 */

+#define FDCAN_NDAT2_ND40          FDCAN_NDAT2_ND40_Msk                         /*!<New Data flag of Rx Buffer 40             */

+#define FDCAN_NDAT2_ND41_Pos      (9U)

+#define FDCAN_NDAT2_ND41_Msk      (0x1UL << FDCAN_NDAT2_ND41_Pos)              /*!< 0x00000200 */

+#define FDCAN_NDAT2_ND41          FDCAN_NDAT2_ND41_Msk                         /*!<New Data flag of Rx Buffer 41             */

+#define FDCAN_NDAT2_ND42_Pos      (10U)

+#define FDCAN_NDAT2_ND42_Msk      (0x1UL << FDCAN_NDAT2_ND42_Pos)              /*!< 0x00000400 */

+#define FDCAN_NDAT2_ND42          FDCAN_NDAT2_ND42_Msk                         /*!<New Data flag of Rx Buffer 42             */

+#define FDCAN_NDAT2_ND43_Pos      (11U)

+#define FDCAN_NDAT2_ND43_Msk      (0x1UL << FDCAN_NDAT2_ND43_Pos)              /*!< 0x00000800 */

+#define FDCAN_NDAT2_ND43          FDCAN_NDAT2_ND43_Msk                         /*!<New Data flag of Rx Buffer 43             */

+#define FDCAN_NDAT2_ND44_Pos      (12U)

+#define FDCAN_NDAT2_ND44_Msk      (0x1UL << FDCAN_NDAT2_ND44_Pos)              /*!< 0x00001000 */

+#define FDCAN_NDAT2_ND44          FDCAN_NDAT2_ND44_Msk                         /*!<New Data flag of Rx Buffer 44             */

+#define FDCAN_NDAT2_ND45_Pos      (13U)

+#define FDCAN_NDAT2_ND45_Msk      (0x1UL << FDCAN_NDAT2_ND45_Pos)              /*!< 0x00002000 */

+#define FDCAN_NDAT2_ND45          FDCAN_NDAT2_ND45_Msk                         /*!<New Data flag of Rx Buffer 45             */

+#define FDCAN_NDAT2_ND46_Pos      (14U)

+#define FDCAN_NDAT2_ND46_Msk      (0x1UL << FDCAN_NDAT2_ND46_Pos)              /*!< 0x00004000 */

+#define FDCAN_NDAT2_ND46          FDCAN_NDAT2_ND46_Msk                         /*!<New Data flag of Rx Buffer 46             */

+#define FDCAN_NDAT2_ND47_Pos      (15U)

+#define FDCAN_NDAT2_ND47_Msk      (0x1UL << FDCAN_NDAT2_ND47_Pos)              /*!< 0x00008000 */

+#define FDCAN_NDAT2_ND47          FDCAN_NDAT2_ND47_Msk                         /*!<New Data flag of Rx Buffer 47             */

+#define FDCAN_NDAT2_ND48_Pos      (16U)

+#define FDCAN_NDAT2_ND48_Msk      (0x1UL << FDCAN_NDAT2_ND48_Pos)              /*!< 0x00010000 */

+#define FDCAN_NDAT2_ND48          FDCAN_NDAT2_ND48_Msk                         /*!<New Data flag of Rx Buffer 48             */

+#define FDCAN_NDAT2_ND49_Pos      (17U)

+#define FDCAN_NDAT2_ND49_Msk      (0x1UL << FDCAN_NDAT2_ND49_Pos)              /*!< 0x00020000 */

+#define FDCAN_NDAT2_ND49          FDCAN_NDAT2_ND49_Msk                         /*!<New Data flag of Rx Buffer 49             */

+#define FDCAN_NDAT2_ND50_Pos      (18U)

+#define FDCAN_NDAT2_ND50_Msk      (0x1UL << FDCAN_NDAT2_ND50_Pos)              /*!< 0x00040000 */

+#define FDCAN_NDAT2_ND50          FDCAN_NDAT2_ND50_Msk                         /*!<New Data flag of Rx Buffer 50             */

+#define FDCAN_NDAT2_ND51_Pos      (19U)

+#define FDCAN_NDAT2_ND51_Msk      (0x1UL << FDCAN_NDAT2_ND51_Pos)              /*!< 0x00080000 */

+#define FDCAN_NDAT2_ND51          FDCAN_NDAT2_ND51_Msk                         /*!<New Data flag of Rx Buffer 51             */

+#define FDCAN_NDAT2_ND52_Pos      (20U)

+#define FDCAN_NDAT2_ND52_Msk      (0x1UL << FDCAN_NDAT2_ND52_Pos)              /*!< 0x00100000 */

+#define FDCAN_NDAT2_ND52          FDCAN_NDAT2_ND52_Msk                         /*!<New Data flag of Rx Buffer 52             */

+#define FDCAN_NDAT2_ND53_Pos      (21U)

+#define FDCAN_NDAT2_ND53_Msk      (0x1UL << FDCAN_NDAT2_ND53_Pos)              /*!< 0x00200000 */

+#define FDCAN_NDAT2_ND53          FDCAN_NDAT2_ND53_Msk                         /*!<New Data flag of Rx Buffer 53             */

+#define FDCAN_NDAT2_ND54_Pos      (22U)

+#define FDCAN_NDAT2_ND54_Msk      (0x1UL << FDCAN_NDAT2_ND54_Pos)              /*!< 0x00400000 */

+#define FDCAN_NDAT2_ND54          FDCAN_NDAT2_ND54_Msk                         /*!<New Data flag of Rx Buffer 54             */

+#define FDCAN_NDAT2_ND55_Pos      (23U)

+#define FDCAN_NDAT2_ND55_Msk      (0x1UL << FDCAN_NDAT2_ND55_Pos)              /*!< 0x00800000 */

+#define FDCAN_NDAT2_ND55          FDCAN_NDAT2_ND55_Msk                         /*!<New Data flag of Rx Buffer 55             */

+#define FDCAN_NDAT2_ND56_Pos      (24U)

+#define FDCAN_NDAT2_ND56_Msk      (0x1UL << FDCAN_NDAT2_ND56_Pos)              /*!< 0x01000000 */

+#define FDCAN_NDAT2_ND56          FDCAN_NDAT2_ND56_Msk                         /*!<New Data flag of Rx Buffer 56             */

+#define FDCAN_NDAT2_ND57_Pos      (25U)

+#define FDCAN_NDAT2_ND57_Msk      (0x1UL << FDCAN_NDAT2_ND57_Pos)              /*!< 0x02000000 */

+#define FDCAN_NDAT2_ND57          FDCAN_NDAT2_ND57_Msk                         /*!<New Data flag of Rx Buffer 57             */

+#define FDCAN_NDAT2_ND58_Pos      (26U)

+#define FDCAN_NDAT2_ND58_Msk      (0x1UL << FDCAN_NDAT2_ND58_Pos)              /*!< 0x04000000 */

+#define FDCAN_NDAT2_ND58          FDCAN_NDAT2_ND58_Msk                         /*!<New Data flag of Rx Buffer 58             */

+#define FDCAN_NDAT2_ND59_Pos      (27U)

+#define FDCAN_NDAT2_ND59_Msk      (0x1UL << FDCAN_NDAT2_ND59_Pos)              /*!< 0x08000000 */

+#define FDCAN_NDAT2_ND59          FDCAN_NDAT2_ND59_Msk                         /*!<New Data flag of Rx Buffer 59             */

+#define FDCAN_NDAT2_ND60_Pos      (28U)

+#define FDCAN_NDAT2_ND60_Msk      (0x1UL << FDCAN_NDAT2_ND60_Pos)              /*!< 0x10000000 */

+#define FDCAN_NDAT2_ND60          FDCAN_NDAT2_ND60_Msk                         /*!<New Data flag of Rx Buffer 60             */

+#define FDCAN_NDAT2_ND61_Pos      (29U)

+#define FDCAN_NDAT2_ND61_Msk      (0x1UL << FDCAN_NDAT2_ND61_Pos)              /*!< 0x20000000 */

+#define FDCAN_NDAT2_ND61          FDCAN_NDAT2_ND61_Msk                         /*!<New Data flag of Rx Buffer 61             */

+#define FDCAN_NDAT2_ND62_Pos      (30U)

+#define FDCAN_NDAT2_ND62_Msk      (0x1UL << FDCAN_NDAT2_ND62_Pos)              /*!< 0x40000000 */

+#define FDCAN_NDAT2_ND62          FDCAN_NDAT2_ND62_Msk                         /*!<New Data flag of Rx Buffer 62             */

+#define FDCAN_NDAT2_ND63_Pos      (31U)

+#define FDCAN_NDAT2_ND63_Msk      (0x1UL << FDCAN_NDAT2_ND63_Pos)              /*!< 0x80000000 */

+#define FDCAN_NDAT2_ND63          FDCAN_NDAT2_ND63_Msk                         /*!<New Data flag of Rx Buffer 63             */

+

+/*****************  Bit definition for FDCAN_RXF0C register  ********************/

+#define FDCAN_RXF0C_F0SA_Pos      (2U)

+#define FDCAN_RXF0C_F0SA_Msk      (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_RXF0C_F0SA          FDCAN_RXF0C_F0SA_Msk                         /*!<Rx FIFO 0 Start Address                   */

+#define FDCAN_RXF0C_F0S_Pos       (16U)

+#define FDCAN_RXF0C_F0S_Msk       (0x7FUL << FDCAN_RXF0C_F0S_Pos)              /*!< 0x007F0000 */

+#define FDCAN_RXF0C_F0S           FDCAN_RXF0C_F0S_Msk                          /*!<Number of Rx FIFO 0 elements              */

+#define FDCAN_RXF0C_F0WM_Pos      (24U)

+#define FDCAN_RXF0C_F0WM_Msk      (0x7FUL << FDCAN_RXF0C_F0WM_Pos)             /*!< 0x7F000000 */

+#define FDCAN_RXF0C_F0WM          FDCAN_RXF0C_F0WM_Msk                         /*!<FIFO 0 Watermark                          */

+#define FDCAN_RXF0C_F0OM_Pos      (31U)

+#define FDCAN_RXF0C_F0OM_Msk      (0x1UL << FDCAN_RXF0C_F0OM_Pos)              /*!< 0x80000000 */

+#define FDCAN_RXF0C_F0OM          FDCAN_RXF0C_F0OM_Msk                         /*!<FIFO 0 Operation Mode                     */

+

+/*****************  Bit definition for FDCAN_RXF0S register  ********************/

+#define FDCAN_RXF0S_F0FL_Pos      (0U)

+#define FDCAN_RXF0S_F0FL_Msk      (0x7FUL << FDCAN_RXF0S_F0FL_Pos)             /*!< 0x0000007F */

+#define FDCAN_RXF0S_F0FL          FDCAN_RXF0S_F0FL_Msk                         /*!<Rx FIFO 0 Fill Level                      */

+#define FDCAN_RXF0S_F0GI_Pos      (8U)

+#define FDCAN_RXF0S_F0GI_Msk      (0x3FUL << FDCAN_RXF0S_F0GI_Pos)             /*!< 0x00003F00 */

+#define FDCAN_RXF0S_F0GI          FDCAN_RXF0S_F0GI_Msk                         /*!<Rx FIFO 0 Get Index                       */

+#define FDCAN_RXF0S_F0PI_Pos      (16U)

+#define FDCAN_RXF0S_F0PI_Msk      (0x3FUL << FDCAN_RXF0S_F0PI_Pos)             /*!< 0x003F0000 */

+#define FDCAN_RXF0S_F0PI          FDCAN_RXF0S_F0PI_Msk                         /*!<Rx FIFO 0 Put Index                       */

+#define FDCAN_RXF0S_F0F_Pos       (24U)

+#define FDCAN_RXF0S_F0F_Msk       (0x1UL << FDCAN_RXF0S_F0F_Pos)               /*!< 0x01000000 */

+#define FDCAN_RXF0S_F0F           FDCAN_RXF0S_F0F_Msk                          /*!<Rx FIFO 0 Full                            */

+#define FDCAN_RXF0S_RF0L_Pos      (25U)

+#define FDCAN_RXF0S_RF0L_Msk      (0x1UL << FDCAN_RXF0S_RF0L_Pos)              /*!< 0x02000000 */

+#define FDCAN_RXF0S_RF0L          FDCAN_RXF0S_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                    */

+

+/*****************  Bit definition for FDCAN_RXF0A register  ********************/

+#define FDCAN_RXF0A_F0AI_Pos      (0U)

+#define FDCAN_RXF0A_F0AI_Msk      (0x3FUL << FDCAN_RXF0A_F0AI_Pos)             /*!< 0x0000003F */

+#define FDCAN_RXF0A_F0AI          FDCAN_RXF0A_F0AI_Msk                         /*!<Rx FIFO 0 Acknowledge Index               */

+

+/*****************  Bit definition for FDCAN_RXBC register  ********************/

+#define FDCAN_RXBC_RBSA_Pos       (2U)

+#define FDCAN_RXBC_RBSA_Msk       (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)            /*!< 0x0000FFFC */

+#define FDCAN_RXBC_RBSA           FDCAN_RXBC_RBSA_Msk                          /*!<Rx Buffer Start Address                   */

+

+/*****************  Bit definition for FDCAN_RXF1C register  ********************/

+#define FDCAN_RXF1C_F1SA_Pos      (2U)

+#define FDCAN_RXF1C_F1SA_Msk      (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_RXF1C_F1SA          FDCAN_RXF1C_F1SA_Msk                         /*!<Rx FIFO 1 Start Address                   */

+#define FDCAN_RXF1C_F1S_Pos       (16U)

+#define FDCAN_RXF1C_F1S_Msk       (0x7FUL << FDCAN_RXF1C_F1S_Pos)              /*!< 0x007F0000 */

+#define FDCAN_RXF1C_F1S           FDCAN_RXF1C_F1S_Msk                          /*!<Number of Rx FIFO 1 elements              */

+#define FDCAN_RXF1C_F1WM_Pos      (24U)

+#define FDCAN_RXF1C_F1WM_Msk      (0x7FUL << FDCAN_RXF1C_F1WM_Pos)             /*!< 0x7F000000 */

+#define FDCAN_RXF1C_F1WM          FDCAN_RXF1C_F1WM_Msk                         /*!<Rx FIFO 1 Watermark                       */

+#define FDCAN_RXF1C_F1OM_Pos      (31U)

+#define FDCAN_RXF1C_F1OM_Msk      (0x1UL << FDCAN_RXF1C_F1OM_Pos)              /*!< 0x80000000 */

+#define FDCAN_RXF1C_F1OM          FDCAN_RXF1C_F1OM_Msk                         /*!<FIFO 1 Operation Mode                     */

+

+/*****************  Bit definition for FDCAN_RXF1S register  ********************/

+#define FDCAN_RXF1S_F1FL_Pos      (0U)

+#define FDCAN_RXF1S_F1FL_Msk      (0x7FUL << FDCAN_RXF1S_F1FL_Pos)             /*!< 0x0000007F */

+#define FDCAN_RXF1S_F1FL          FDCAN_RXF1S_F1FL_Msk                         /*!<Rx FIFO 1 Fill Level                      */

+#define FDCAN_RXF1S_F1GI_Pos      (8U)

+#define FDCAN_RXF1S_F1GI_Msk      (0x3FUL << FDCAN_RXF1S_F1GI_Pos)             /*!< 0x00003F00 */

+#define FDCAN_RXF1S_F1GI          FDCAN_RXF1S_F1GI_Msk                         /*!<Rx FIFO 1 Get Index                       */

+#define FDCAN_RXF1S_F1PI_Pos      (16U)

+#define FDCAN_RXF1S_F1PI_Msk      (0x3FUL << FDCAN_RXF1S_F1PI_Pos)             /*!< 0x003F0000 */

+#define FDCAN_RXF1S_F1PI          FDCAN_RXF1S_F1PI_Msk                         /*!<Rx FIFO 1 Put Index                       */

+#define FDCAN_RXF1S_F1F_Pos       (24U)

+#define FDCAN_RXF1S_F1F_Msk       (0x1UL << FDCAN_RXF1S_F1F_Pos)               /*!< 0x01000000 */

+#define FDCAN_RXF1S_F1F           FDCAN_RXF1S_F1F_Msk                          /*!<Rx FIFO 1 Full                            */

+#define FDCAN_RXF1S_RF1L_Pos      (25U)

+#define FDCAN_RXF1S_RF1L_Msk      (0x1UL << FDCAN_RXF1S_RF1L_Pos)              /*!< 0x02000000 */

+#define FDCAN_RXF1S_RF1L          FDCAN_RXF1S_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                    */

+

+/*****************  Bit definition for FDCAN_RXF1A register  ********************/

+#define FDCAN_RXF1A_F1AI_Pos      (0U)

+#define FDCAN_RXF1A_F1AI_Msk      (0x3FUL << FDCAN_RXF1A_F1AI_Pos)             /*!< 0x0000003F */

+#define FDCAN_RXF1A_F1AI          FDCAN_RXF1A_F1AI_Msk                         /*!<Rx FIFO 1 Acknowledge Index               */

+

+/*****************  Bit definition for FDCAN_RXESC register  ********************/

+#define FDCAN_RXESC_F0DS_Pos      (0U)

+#define FDCAN_RXESC_F0DS_Msk      (0x7UL << FDCAN_RXESC_F0DS_Pos)              /*!< 0x00000007 */

+#define FDCAN_RXESC_F0DS          FDCAN_RXESC_F0DS_Msk                         /*!<Rx FIFO 1 Data Field Size                 */

+#define FDCAN_RXESC_F1DS_Pos      (4U)

+#define FDCAN_RXESC_F1DS_Msk      (0x7UL << FDCAN_RXESC_F1DS_Pos)              /*!< 0x00000070 */

+#define FDCAN_RXESC_F1DS          FDCAN_RXESC_F1DS_Msk                         /*!<Rx FIFO 0 Data Field Size                 */

+#define FDCAN_RXESC_RBDS_Pos      (8U)

+#define FDCAN_RXESC_RBDS_Msk      (0x7UL << FDCAN_RXESC_RBDS_Pos)              /*!< 0x00000700 */

+#define FDCAN_RXESC_RBDS          FDCAN_RXESC_RBDS_Msk                         /*!<Rx Buffer Data Field Size                 */

+

+/*****************  Bit definition for FDCAN_TXBC register  *********************/

+#define FDCAN_TXBC_TBSA_Pos       (2U)

+#define FDCAN_TXBC_TBSA_Msk       (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)            /*!< 0x0000FFFC */

+#define FDCAN_TXBC_TBSA           FDCAN_TXBC_TBSA_Msk                          /*!<Tx Buffers Start Address                  */

+#define FDCAN_TXBC_NDTB_Pos       (16U)

+#define FDCAN_TXBC_NDTB_Msk       (0x3FUL << FDCAN_TXBC_NDTB_Pos)              /*!< 0x003F0000 */

+#define FDCAN_TXBC_NDTB           FDCAN_TXBC_NDTB_Msk                          /*!<Number of Dedicated Transmit Buffers      */

+#define FDCAN_TXBC_TFQS_Pos       (24U)

+#define FDCAN_TXBC_TFQS_Msk       (0x3FUL << FDCAN_TXBC_TFQS_Pos)              /*!< 0x3F000000 */

+#define FDCAN_TXBC_TFQS           FDCAN_TXBC_TFQS_Msk                          /*!<Transmit FIFO/Queue Size                  */

+#define FDCAN_TXBC_TFQM_Pos       (30U)

+#define FDCAN_TXBC_TFQM_Msk       (0x1UL << FDCAN_TXBC_TFQM_Pos)               /*!< 0x40000000 */

+#define FDCAN_TXBC_TFQM           FDCAN_TXBC_TFQM_Msk                          /*!<Tx FIFO/Queue Mode                        */

+

+/*****************  Bit definition for FDCAN_TXFQS register  *********************/

+#define FDCAN_TXFQS_TFFL_Pos      (0U)

+#define FDCAN_TXFQS_TFFL_Msk      (0x3FUL << FDCAN_TXFQS_TFFL_Pos)             /*!< 0x0000003F */

+#define FDCAN_TXFQS_TFFL          FDCAN_TXFQS_TFFL_Msk                         /*!<Tx FIFO Free Level                        */

+#define FDCAN_TXFQS_TFGI_Pos      (8U)

+#define FDCAN_TXFQS_TFGI_Msk      (0x1FUL << FDCAN_TXFQS_TFGI_Pos)             /*!< 0x00001F00 */

+#define FDCAN_TXFQS_TFGI          FDCAN_TXFQS_TFGI_Msk                         /*!<Tx FIFO Get Index                         */

+#define FDCAN_TXFQS_TFQPI_Pos     (16U)

+#define FDCAN_TXFQS_TFQPI_Msk     (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)            /*!< 0x001F0000 */

+#define FDCAN_TXFQS_TFQPI         FDCAN_TXFQS_TFQPI_Msk                        /*!<Tx FIFO/Queue Put Index                   */

+#define FDCAN_TXFQS_TFQF_Pos      (21U)

+#define FDCAN_TXFQS_TFQF_Msk      (0x1UL << FDCAN_TXFQS_TFQF_Pos)              /*!< 0x00200000 */

+#define FDCAN_TXFQS_TFQF          FDCAN_TXFQS_TFQF_Msk                         /*!<Tx FIFO/Queue Full                        */

+

+/*****************  Bit definition for FDCAN_TXESC register  *********************/

+#define FDCAN_TXESC_TBDS_Pos      (0U)

+#define FDCAN_TXESC_TBDS_Msk      (0x7UL << FDCAN_TXESC_TBDS_Pos)              /*!< 0x00000007 */

+#define FDCAN_TXESC_TBDS          FDCAN_TXESC_TBDS_Msk                         /*!<Tx Buffer Data Field Size                 */

+

+/*****************  Bit definition for FDCAN_TXBRP register  *********************/

+#define FDCAN_TXBRP_TRP_Pos       (0U)

+#define FDCAN_TXBRP_TRP_Msk       (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)        /*!< 0xFFFFFFFF */

+#define FDCAN_TXBRP_TRP           FDCAN_TXBRP_TRP_Msk                          /*!<Transmission Request Pending              */

+

+/*****************  Bit definition for FDCAN_TXBAR register  *********************/

+#define FDCAN_TXBAR_AR_Pos        (0U)

+#define FDCAN_TXBAR_AR_Msk        (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBAR_AR            FDCAN_TXBAR_AR_Msk                           /*!<Add Request                               */

+

+/*****************  Bit definition for FDCAN_TXBCR register  *********************/

+#define FDCAN_TXBCR_CR_Pos        (0U)

+#define FDCAN_TXBCR_CR_Msk        (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCR_CR            FDCAN_TXBCR_CR_Msk                           /*!<Cancellation Request                      */

+

+/*****************  Bit definition for FDCAN_TXBTO register  *********************/

+#define FDCAN_TXBTO_TO_Pos        (0U)

+#define FDCAN_TXBTO_TO_Msk        (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBTO_TO            FDCAN_TXBTO_TO_Msk                           /*!<Transmission Occurred                     */

+

+/*****************  Bit definition for FDCAN_TXBCF register  *********************/

+#define FDCAN_TXBCF_CF_Pos        (0U)

+#define FDCAN_TXBCF_CF_Msk        (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCF_CF            FDCAN_TXBCF_CF_Msk                           /*!<Cancellation Finished                     */

+

+/*****************  Bit definition for FDCAN_TXBTIE register  ********************/

+#define FDCAN_TXBTIE_TIE_Pos      (0U)

+#define FDCAN_TXBTIE_TIE_Msk      (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)       /*!< 0xFFFFFFFF */

+#define FDCAN_TXBTIE_TIE          FDCAN_TXBTIE_TIE_Msk                         /*!<Transmission Interrupt Enable             */

+

+/*****************  Bit definition for FDCAN_ TXBCIE register  *******************/

+#define FDCAN_TXBCIE_CFIE_Pos     (0U)

+#define FDCAN_TXBCIE_CFIE_Msk     (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)      /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCIE_CFIE         FDCAN_TXBCIE_CFIE_Msk                        /*!<Cancellation Finished Interrupt Enable    */

+

+/*****************  Bit definition for FDCAN_TXEFC register  *********************/

+#define FDCAN_TXEFC_EFSA_Pos      (2U)

+#define FDCAN_TXEFC_EFSA_Msk      (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_TXEFC_EFSA          FDCAN_TXEFC_EFSA_Msk                         /*!<Event FIFO Start Address                  */

+#define FDCAN_TXEFC_EFS_Pos       (16U)

+#define FDCAN_TXEFC_EFS_Msk       (0x3FUL << FDCAN_TXEFC_EFS_Pos)              /*!< 0x003F0000 */

+#define FDCAN_TXEFC_EFS           FDCAN_TXEFC_EFS_Msk                          /*!<Event FIFO Size                           */

+#define FDCAN_TXEFC_EFWM_Pos      (24U)

+#define FDCAN_TXEFC_EFWM_Msk      (0x3FUL << FDCAN_TXEFC_EFWM_Pos)             /*!< 0x3F000000 */

+#define FDCAN_TXEFC_EFWM          FDCAN_TXEFC_EFWM_Msk                         /*!<Event FIFO Watermark                      */

+

+/*****************  Bit definition for FDCAN_TXEFS register  *********************/

+#define FDCAN_TXEFS_EFFL_Pos      (0U)

+#define FDCAN_TXEFS_EFFL_Msk      (0x3FUL << FDCAN_TXEFS_EFFL_Pos)             /*!< 0x0000003F */

+#define FDCAN_TXEFS_EFFL          FDCAN_TXEFS_EFFL_Msk                         /*!<Event FIFO Fill Level                     */

+#define FDCAN_TXEFS_EFGI_Pos      (8U)

+#define FDCAN_TXEFS_EFGI_Msk      (0x1FUL << FDCAN_TXEFS_EFGI_Pos)             /*!< 0x00001F00 */

+#define FDCAN_TXEFS_EFGI          FDCAN_TXEFS_EFGI_Msk                         /*!<Event FIFO Get Index                      */

+#define FDCAN_TXEFS_EFPI_Pos      (16U)

+#define FDCAN_TXEFS_EFPI_Msk      (0x1FUL << FDCAN_TXEFS_EFPI_Pos)             /*!< 0x001F0000 */

+#define FDCAN_TXEFS_EFPI          FDCAN_TXEFS_EFPI_Msk                         /*!<Event FIFO Put Index                      */

+#define FDCAN_TXEFS_EFF_Pos       (24U)

+#define FDCAN_TXEFS_EFF_Msk       (0x1UL << FDCAN_TXEFS_EFF_Pos)               /*!< 0x01000000 */

+#define FDCAN_TXEFS_EFF           FDCAN_TXEFS_EFF_Msk                          /*!<Event FIFO Full                           */

+#define FDCAN_TXEFS_TEFL_Pos      (25U)

+#define FDCAN_TXEFS_TEFL_Msk      (0x1UL << FDCAN_TXEFS_TEFL_Pos)              /*!< 0x02000000 */

+#define FDCAN_TXEFS_TEFL          FDCAN_TXEFS_TEFL_Msk                         /*!<Tx Event FIFO Element Lost                */

+

+/*****************  Bit definition for FDCAN_TXEFA register  *********************/

+#define FDCAN_TXEFA_EFAI_Pos      (0U)

+#define FDCAN_TXEFA_EFAI_Msk      (0x1FUL << FDCAN_TXEFA_EFAI_Pos)             /*!< 0x0000001F */

+#define FDCAN_TXEFA_EFAI          FDCAN_TXEFA_EFAI_Msk                         /*!<Event FIFO Acknowledge Index              */

+

+/*****************  Bit definition for FDCAN_TTTMC register  *********************/

+#define FDCAN_TTTMC_TMSA_Pos      (2U)

+#define FDCAN_TTTMC_TMSA_Msk      (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_TTTMC_TMSA          FDCAN_TTTMC_TMSA_Msk                         /*!<Trigger Memory Start Address              */

+#define FDCAN_TTTMC_TME_Pos       (16U)

+#define FDCAN_TTTMC_TME_Msk       (0x7FUL << FDCAN_TTTMC_TME_Pos)              /*!< 0x007F0000 */

+#define FDCAN_TTTMC_TME           FDCAN_TTTMC_TME_Msk                          /*!<Trigger Memory Elements                   */

+

+/*****************  Bit definition for FDCAN_TTRMC register  *********************/

+#define FDCAN_TTRMC_RID_Pos       (0U)

+#define FDCAN_TTRMC_RID_Msk       (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)        /*!< 0x1FFFFFFF */

+#define FDCAN_TTRMC_RID           FDCAN_TTRMC_RID_Msk                          /*!<Reference Identifier                      */

+#define FDCAN_TTRMC_XTD_Pos       (30U)

+#define FDCAN_TTRMC_XTD_Msk       (0x1UL << FDCAN_TTRMC_XTD_Pos)               /*!< 0x40000000 */

+#define FDCAN_TTRMC_XTD           FDCAN_TTRMC_XTD_Msk                          /*!< Extended Identifier                      */

+#define FDCAN_TTRMC_RMPS_Pos      (31U)

+#define FDCAN_TTRMC_RMPS_Msk      (0x1UL << FDCAN_TTRMC_RMPS_Pos)              /*!< 0x80000000 */

+#define FDCAN_TTRMC_RMPS          FDCAN_TTRMC_RMPS_Msk                         /*!<Reference Message Payload Select          */

+

+/*****************  Bit definition for FDCAN_TTOCF register  *********************/

+#define FDCAN_TTOCF_OM_Pos        (0U)

+#define FDCAN_TTOCF_OM_Msk        (0x3UL << FDCAN_TTOCF_OM_Pos)                /*!< 0x00000003 */

+#define FDCAN_TTOCF_OM            FDCAN_TTOCF_OM_Msk                           /*!<Operation Mode                            */

+#define FDCAN_TTOCF_GEN_Pos       (3U)

+#define FDCAN_TTOCF_GEN_Msk       (0x1UL << FDCAN_TTOCF_GEN_Pos)               /*!< 0x00000008 */

+#define FDCAN_TTOCF_GEN           FDCAN_TTOCF_GEN_Msk                          /*!<Gap Enable                                */

+#define FDCAN_TTOCF_TM_Pos        (4U)

+#define FDCAN_TTOCF_TM_Msk        (0x1UL << FDCAN_TTOCF_TM_Pos)                /*!< 0x00000010 */

+#define FDCAN_TTOCF_TM            FDCAN_TTOCF_TM_Msk                           /*!<Time Master                               */

+#define FDCAN_TTOCF_LDSDL_Pos     (5U)

+#define FDCAN_TTOCF_LDSDL_Msk     (0x7UL << FDCAN_TTOCF_LDSDL_Pos)             /*!< 0x000000E0 */

+#define FDCAN_TTOCF_LDSDL         FDCAN_TTOCF_LDSDL_Msk                        /*!<LD of Synchronization Deviation Limit     */

+#define FDCAN_TTOCF_IRTO_Pos      (8U)

+#define FDCAN_TTOCF_IRTO_Msk      (0x7FUL << FDCAN_TTOCF_IRTO_Pos)             /*!< 0x00007F00 */

+#define FDCAN_TTOCF_IRTO          FDCAN_TTOCF_IRTO_Msk                         /*!<Initial Reference Trigger Offset          */

+#define FDCAN_TTOCF_EECS_Pos      (15U)

+#define FDCAN_TTOCF_EECS_Msk      (0x1UL << FDCAN_TTOCF_EECS_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTOCF_EECS          FDCAN_TTOCF_EECS_Msk                         /*!<Enable External Clock Synchronization     */

+#define FDCAN_TTOCF_AWL_Pos       (16U)

+#define FDCAN_TTOCF_AWL_Msk       (0xFFUL << FDCAN_TTOCF_AWL_Pos)              /*!< 0x00FF0000 */

+#define FDCAN_TTOCF_AWL           FDCAN_TTOCF_AWL_Msk                          /*!<Application Watchdog Limit                */

+#define FDCAN_TTOCF_EGTF_Pos      (24U)

+#define FDCAN_TTOCF_EGTF_Msk      (0x1UL << FDCAN_TTOCF_EGTF_Pos)              /*!< 0x01000000 */

+#define FDCAN_TTOCF_EGTF          FDCAN_TTOCF_EGTF_Msk                         /*!<Enable Global Time Filtering              */

+#define FDCAN_TTOCF_ECC_Pos       (25U)

+#define FDCAN_TTOCF_ECC_Msk       (0x1UL << FDCAN_TTOCF_ECC_Pos)               /*!< 0x02000000 */

+#define FDCAN_TTOCF_ECC           FDCAN_TTOCF_ECC_Msk                          /*!<Enable Clock Calibration                  */

+#define FDCAN_TTOCF_EVTP_Pos      (26U)

+#define FDCAN_TTOCF_EVTP_Msk      (0x1UL << FDCAN_TTOCF_EVTP_Pos)              /*!< 0x04000000 */

+#define FDCAN_TTOCF_EVTP          FDCAN_TTOCF_EVTP_Msk                         /*!<Event Trigger Polarity                    */

+

+/*****************  Bit definition for FDCAN_TTMLM register  *********************/

+#define FDCAN_TTMLM_CCM_Pos       (0U)

+#define FDCAN_TTMLM_CCM_Msk       (0x3FUL << FDCAN_TTMLM_CCM_Pos)              /*!< 0x0000003F */

+#define FDCAN_TTMLM_CCM           FDCAN_TTMLM_CCM_Msk                          /*!<Cycle Count Max                           */

+#define FDCAN_TTMLM_CSS_Pos       (6U)

+#define FDCAN_TTMLM_CSS_Msk       (0x3UL << FDCAN_TTMLM_CSS_Pos)               /*!< 0x000000C0 */

+#define FDCAN_TTMLM_CSS           FDCAN_TTMLM_CSS_Msk                          /*!<Cycle Start Synchronization               */

+#define FDCAN_TTMLM_TXEW_Pos      (8U)

+#define FDCAN_TTMLM_TXEW_Msk      (0xFUL << FDCAN_TTMLM_TXEW_Pos)              /*!< 0x00000F00 */

+#define FDCAN_TTMLM_TXEW          FDCAN_TTMLM_TXEW_Msk                         /*!<Tx Enable Window                          */

+#define FDCAN_TTMLM_ENTT_Pos      (16U)

+#define FDCAN_TTMLM_ENTT_Msk      (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)            /*!< 0x0FFF0000 */

+#define FDCAN_TTMLM_ENTT          FDCAN_TTMLM_ENTT_Msk                         /*!<Expected Number of Tx Triggers            */

+

+/*****************  Bit definition for FDCAN_TURCF register  *********************/

+#define FDCAN_TURCF_NCL_Pos       (0U)

+#define FDCAN_TURCF_NCL_Msk       (0xFFFFUL << FDCAN_TURCF_NCL_Pos)            /*!< 0x0000FFFF */

+#define FDCAN_TURCF_NCL           FDCAN_TURCF_NCL_Msk                          /*!<Numerator Configuration Low               */

+#define FDCAN_TURCF_DC_Pos        (16U)

+#define FDCAN_TURCF_DC_Msk        (0x3FFFUL << FDCAN_TURCF_DC_Pos)             /*!< 0x3FFF0000 */

+#define FDCAN_TURCF_DC            FDCAN_TURCF_DC_Msk                           /*!<Denominator Configuration                 */

+#define FDCAN_TURCF_ELT_Pos       (31U)

+#define FDCAN_TURCF_ELT_Msk       (0x1UL << FDCAN_TURCF_ELT_Pos)               /*!< 0x80000000 */

+#define FDCAN_TURCF_ELT           FDCAN_TURCF_ELT_Msk                          /*!<Enable Local Time                         */

+

+/*****************  Bit definition for FDCAN_TTOCN register  ********************/

+#define FDCAN_TTOCN_SGT_Pos       (0U)

+#define FDCAN_TTOCN_SGT_Msk       (0x1UL << FDCAN_TTOCN_SGT_Pos)               /*!< 0x00000001 */

+#define FDCAN_TTOCN_SGT           FDCAN_TTOCN_SGT_Msk                          /*!<Set Global time                           */

+#define FDCAN_TTOCN_ECS_Pos       (1U)

+#define FDCAN_TTOCN_ECS_Msk       (0x1UL << FDCAN_TTOCN_ECS_Pos)               /*!< 0x00000002 */

+#define FDCAN_TTOCN_ECS           FDCAN_TTOCN_ECS_Msk                          /*!<External Clock Synchronization            */

+#define FDCAN_TTOCN_SWP_Pos       (2U)

+#define FDCAN_TTOCN_SWP_Msk       (0x1UL << FDCAN_TTOCN_SWP_Pos)               /*!< 0x00000004 */

+#define FDCAN_TTOCN_SWP           FDCAN_TTOCN_SWP_Msk                          /*!<Stop Watch Polarity                       */

+#define FDCAN_TTOCN_SWS_Pos       (3U)

+#define FDCAN_TTOCN_SWS_Msk       (0x3UL << FDCAN_TTOCN_SWS_Pos)               /*!< 0x00000018 */

+#define FDCAN_TTOCN_SWS           FDCAN_TTOCN_SWS_Msk                          /*!<Stop Watch Source                         */

+#define FDCAN_TTOCN_RTIE_Pos      (5U)

+#define FDCAN_TTOCN_RTIE_Msk      (0x1UL << FDCAN_TTOCN_RTIE_Pos)              /*!< 0x00000020 */

+#define FDCAN_TTOCN_RTIE          FDCAN_TTOCN_RTIE_Msk                         /*!<Register Time Mark Interrupt Pulse Enable */

+#define FDCAN_TTOCN_TMC_Pos       (6U)

+#define FDCAN_TTOCN_TMC_Msk       (0x3UL << FDCAN_TTOCN_TMC_Pos)               /*!< 0x000000C0 */

+#define FDCAN_TTOCN_TMC           FDCAN_TTOCN_TMC_Msk                          /*!<Register Time Mark Compare                */

+#define FDCAN_TTOCN_TTIE_Pos      (8U)

+#define FDCAN_TTOCN_TTIE_Msk      (0x1UL << FDCAN_TTOCN_TTIE_Pos)              /*!< 0x00000100 */

+#define FDCAN_TTOCN_TTIE          FDCAN_TTOCN_TTIE_Msk                         /*!<Trigger Time Mark Interrupt Pulse Enable  */

+#define FDCAN_TTOCN_GCS_Pos       (9U)

+#define FDCAN_TTOCN_GCS_Msk       (0x1UL << FDCAN_TTOCN_GCS_Pos)               /*!< 0x00000200 */

+#define FDCAN_TTOCN_GCS           FDCAN_TTOCN_GCS_Msk                          /*!<Gap Control Select                        */

+#define FDCAN_TTOCN_FGP_Pos       (10U)

+#define FDCAN_TTOCN_FGP_Msk       (0x1UL << FDCAN_TTOCN_FGP_Pos)               /*!< 0x00000400 */

+#define FDCAN_TTOCN_FGP           FDCAN_TTOCN_FGP_Msk                          /*!<Finish Gap                                */

+#define FDCAN_TTOCN_TMG_Pos       (11U)

+#define FDCAN_TTOCN_TMG_Msk       (0x1UL << FDCAN_TTOCN_TMG_Pos)               /*!< 0x00000800 */

+#define FDCAN_TTOCN_TMG           FDCAN_TTOCN_TMG_Msk                          /*!<Time Mark Gap                             */

+#define FDCAN_TTOCN_NIG_Pos       (12U)

+#define FDCAN_TTOCN_NIG_Msk       (0x1UL << FDCAN_TTOCN_NIG_Pos)               /*!< 0x00001000 */

+#define FDCAN_TTOCN_NIG           FDCAN_TTOCN_NIG_Msk                          /*!<Next is Gap                               */

+#define FDCAN_TTOCN_ESCN_Pos      (13U)

+#define FDCAN_TTOCN_ESCN_Msk      (0x1UL << FDCAN_TTOCN_ESCN_Pos)              /*!< 0x00002000 */

+#define FDCAN_TTOCN_ESCN          FDCAN_TTOCN_ESCN_Msk                         /*!<External Synchronization Control          */

+#define FDCAN_TTOCN_LCKC_Pos      (15U)

+#define FDCAN_TTOCN_LCKC_Msk      (0x1UL << FDCAN_TTOCN_LCKC_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTOCN_LCKC          FDCAN_TTOCN_LCKC_Msk                         /*!<TT Operation Control Register Locked      */

+

+/*****************  Bit definition for FDCAN_TTGTP register  ********************/

+#define FDCAN_TTGTP_TP_Pos        (0U)

+#define FDCAN_TTGTP_TP_Msk        (0xFFFFUL << FDCAN_TTGTP_TP_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTGTP_TP            FDCAN_TTGTP_TP_Msk                           /*!<Time Preset                               */

+#define FDCAN_TTGTP_CTP_Pos       (16U)

+#define FDCAN_TTGTP_CTP_Msk       (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)            /*!< 0xFFFF0000 */

+#define FDCAN_TTGTP_CTP           FDCAN_TTGTP_CTP_Msk                          /*!<Cycle Time Target Phase                   */

+

+/*****************  Bit definition for FDCAN_TTTMK register  ********************/

+#define FDCAN_TTTMK_TM_Pos        (0U)

+#define FDCAN_TTTMK_TM_Msk        (0xFFFFUL << FDCAN_TTTMK_TM_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTTMK_TM            FDCAN_TTTMK_TM_Msk                           /*!<Time Mark                                 */

+#define FDCAN_TTTMK_TICC_Pos      (16U)

+#define FDCAN_TTTMK_TICC_Msk      (0x7FUL << FDCAN_TTTMK_TICC_Pos)             /*!< 0x007F0000 */

+#define FDCAN_TTTMK_TICC          FDCAN_TTTMK_TICC_Msk                         /*!<Time Mark Cycle Code                      */

+#define FDCAN_TTTMK_LCKM_Pos      (31U)

+#define FDCAN_TTTMK_LCKM_Msk      (0x1UL << FDCAN_TTTMK_LCKM_Pos)              /*!< 0x80000000 */

+#define FDCAN_TTTMK_LCKM          FDCAN_TTTMK_LCKM_Msk                         /*!<TT Time Mark Register Locked              */

+

+/*****************  Bit definition for FDCAN_TTIR register  ********************/

+#define FDCAN_TTIR_SBC_Pos        (0U)

+#define FDCAN_TTIR_SBC_Msk        (0x1UL << FDCAN_TTIR_SBC_Pos)                /*!< 0x00000001 */

+#define FDCAN_TTIR_SBC            FDCAN_TTIR_SBC_Msk                           /*!<Start of Basic Cycle                      */

+#define FDCAN_TTIR_SMC_Pos        (1U)

+#define FDCAN_TTIR_SMC_Msk        (0x1UL << FDCAN_TTIR_SMC_Pos)                /*!< 0x00000002 */

+#define FDCAN_TTIR_SMC            FDCAN_TTIR_SMC_Msk                           /*!<Start of Matrix Cycle                     */

+#define FDCAN_TTIR_CSM_Pos        (2U)

+#define FDCAN_TTIR_CSM_Msk        (0x1UL << FDCAN_TTIR_CSM_Pos)                /*!< 0x00000004 */

+#define FDCAN_TTIR_CSM            FDCAN_TTIR_CSM_Msk                           /*!<Change of Synchronization Mode            */

+#define FDCAN_TTIR_SOG_Pos        (3U)

+#define FDCAN_TTIR_SOG_Msk        (0x1UL << FDCAN_TTIR_SOG_Pos)                /*!< 0x00000008 */

+#define FDCAN_TTIR_SOG            FDCAN_TTIR_SOG_Msk                           /*!<Start of Gap                              */

+#define FDCAN_TTIR_RTMI_Pos       (4U)

+#define FDCAN_TTIR_RTMI_Msk       (0x1UL << FDCAN_TTIR_RTMI_Pos)               /*!< 0x00000010 */

+#define FDCAN_TTIR_RTMI           FDCAN_TTIR_RTMI_Msk                          /*!<Register Time Mark Interrupt              */

+#define FDCAN_TTIR_TTMI_Pos       (5U)

+#define FDCAN_TTIR_TTMI_Msk       (0x1UL << FDCAN_TTIR_TTMI_Pos)               /*!< 0x00000020 */

+#define FDCAN_TTIR_TTMI           FDCAN_TTIR_TTMI_Msk                          /*!<Trigger Time Mark Event Internal          */

+#define FDCAN_TTIR_SWE_Pos        (6U)

+#define FDCAN_TTIR_SWE_Msk        (0x1UL << FDCAN_TTIR_SWE_Pos)                /*!< 0x00000040 */

+#define FDCAN_TTIR_SWE            FDCAN_TTIR_SWE_Msk                           /*!<Stop Watch Event                          */

+#define FDCAN_TTIR_GTW_Pos        (7U)

+#define FDCAN_TTIR_GTW_Msk        (0x1UL << FDCAN_TTIR_GTW_Pos)                /*!< 0x00000080 */

+#define FDCAN_TTIR_GTW            FDCAN_TTIR_GTW_Msk                           /*!<Global Time Wrap                          */

+#define FDCAN_TTIR_GTD_Pos        (8U)

+#define FDCAN_TTIR_GTD_Msk        (0x1UL << FDCAN_TTIR_GTD_Pos)                /*!< 0x00000100 */

+#define FDCAN_TTIR_GTD            FDCAN_TTIR_GTD_Msk                           /*!<Global Time Discontinuity                 */

+#define FDCAN_TTIR_GTE_Pos        (9U)

+#define FDCAN_TTIR_GTE_Msk        (0x1UL << FDCAN_TTIR_GTE_Pos)                /*!< 0x00000200 */

+#define FDCAN_TTIR_GTE            FDCAN_TTIR_GTE_Msk                           /*!<Global Time Error                         */

+#define FDCAN_TTIR_TXU_Pos        (10U)

+#define FDCAN_TTIR_TXU_Msk        (0x1UL << FDCAN_TTIR_TXU_Pos)                /*!< 0x00000400 */

+#define FDCAN_TTIR_TXU            FDCAN_TTIR_TXU_Msk                           /*!<Tx Count Underflow                        */

+#define FDCAN_TTIR_TXO_Pos        (11U)

+#define FDCAN_TTIR_TXO_Msk        (0x1UL << FDCAN_TTIR_TXO_Pos)                /*!< 0x00000800 */

+#define FDCAN_TTIR_TXO            FDCAN_TTIR_TXO_Msk                           /*!<Tx Count Overflow                         */

+#define FDCAN_TTIR_SE1_Pos        (12U)

+#define FDCAN_TTIR_SE1_Msk        (0x1UL << FDCAN_TTIR_SE1_Pos)                /*!< 0x00001000 */

+#define FDCAN_TTIR_SE1            FDCAN_TTIR_SE1_Msk                           /*!<Scheduling Error 1                        */

+#define FDCAN_TTIR_SE2_Pos        (13U)

+#define FDCAN_TTIR_SE2_Msk        (0x1UL << FDCAN_TTIR_SE2_Pos)                /*!< 0x00002000 */

+#define FDCAN_TTIR_SE2            FDCAN_TTIR_SE2_Msk                           /*!<Scheduling Error 2                        */

+#define FDCAN_TTIR_ELC_Pos        (14U)

+#define FDCAN_TTIR_ELC_Msk        (0x1UL << FDCAN_TTIR_ELC_Pos)                /*!< 0x00004000 */

+#define FDCAN_TTIR_ELC            FDCAN_TTIR_ELC_Msk                           /*!<Error Level Changed                       */

+#define FDCAN_TTIR_IWT_Pos        (15U)

+#define FDCAN_TTIR_IWT_Msk        (0x1UL << FDCAN_TTIR_IWT_Pos)                /*!< 0x00008000 */

+#define FDCAN_TTIR_IWT            FDCAN_TTIR_IWT_Msk                           /*!<Initialization Watch Trigger              */

+#define FDCAN_TTIR_WT_Pos         (16U)

+#define FDCAN_TTIR_WT_Msk         (0x1UL << FDCAN_TTIR_WT_Pos)                 /*!< 0x00010000 */

+#define FDCAN_TTIR_WT             FDCAN_TTIR_WT_Msk                            /*!<Watch Trigger                             */

+#define FDCAN_TTIR_AW_Pos         (17U)

+#define FDCAN_TTIR_AW_Msk         (0x1UL << FDCAN_TTIR_AW_Pos)                 /*!< 0x00020000 */

+#define FDCAN_TTIR_AW             FDCAN_TTIR_AW_Msk                            /*!<Application Watchdog                      */

+#define FDCAN_TTIR_CER_Pos        (18U)

+#define FDCAN_TTIR_CER_Msk        (0x1UL << FDCAN_TTIR_CER_Pos)                /*!< 0x00040000 */

+#define FDCAN_TTIR_CER            FDCAN_TTIR_CER_Msk                           /*!<Configuration Error                       */

+

+/*****************  Bit definition for FDCAN_TTIE register  ********************/

+#define FDCAN_TTIE_SBCE_Pos       (0U)

+#define FDCAN_TTIE_SBCE_Msk       (0x1UL << FDCAN_TTIE_SBCE_Pos)               /*!< 0x00000001 */

+#define FDCAN_TTIE_SBCE           FDCAN_TTIE_SBCE_Msk                          /*!<Start of Basic Cycle Interrupt Enable             */

+#define FDCAN_TTIE_SMCE_Pos       (1U)

+#define FDCAN_TTIE_SMCE_Msk       (0x1UL << FDCAN_TTIE_SMCE_Pos)               /*!< 0x00000002 */

+#define FDCAN_TTIE_SMCE           FDCAN_TTIE_SMCE_Msk                          /*!<Start of Matrix Cycle Interrupt Enable            */

+#define FDCAN_TTIE_CSME_Pos       (2U)

+#define FDCAN_TTIE_CSME_Msk       (0x1UL << FDCAN_TTIE_CSME_Pos)               /*!< 0x00000004 */

+#define FDCAN_TTIE_CSME           FDCAN_TTIE_CSME_Msk                          /*!<Change of Synchronization Mode Interrupt Enable   */

+#define FDCAN_TTIE_SOGE_Pos       (3U)

+#define FDCAN_TTIE_SOGE_Msk       (0x1UL << FDCAN_TTIE_SOGE_Pos)               /*!< 0x00000008 */

+#define FDCAN_TTIE_SOGE           FDCAN_TTIE_SOGE_Msk                          /*!<Start of Gap Interrupt Enable                     */

+#define FDCAN_TTIE_RTMIE_Pos      (4U)

+#define FDCAN_TTIE_RTMIE_Msk      (0x1UL << FDCAN_TTIE_RTMIE_Pos)              /*!< 0x00000010 */

+#define FDCAN_TTIE_RTMIE          FDCAN_TTIE_RTMIE_Msk                         /*!<Register Time Mark Interrupt Interrupt Enable     */

+#define FDCAN_TTIE_TTMIE_Pos      (5U)

+#define FDCAN_TTIE_TTMIE_Msk      (0x1UL << FDCAN_TTIE_TTMIE_Pos)              /*!< 0x00000020 */

+#define FDCAN_TTIE_TTMIE          FDCAN_TTIE_TTMIE_Msk                         /*!<Trigger Time Mark Event Internal Interrupt Enable */

+#define FDCAN_TTIE_SWEE_Pos       (6U)

+#define FDCAN_TTIE_SWEE_Msk       (0x1UL << FDCAN_TTIE_SWEE_Pos)               /*!< 0x00000040 */

+#define FDCAN_TTIE_SWEE           FDCAN_TTIE_SWEE_Msk                          /*!<Stop Watch Event Interrupt Enable                 */

+#define FDCAN_TTIE_GTWE_Pos       (7U)

+#define FDCAN_TTIE_GTWE_Msk       (0x1UL << FDCAN_TTIE_GTWE_Pos)               /*!< 0x00000080 */

+#define FDCAN_TTIE_GTWE           FDCAN_TTIE_GTWE_Msk                          /*!<Global Time Wrap Interrupt Enable                 */

+#define FDCAN_TTIE_GTDE_Pos       (8U)

+#define FDCAN_TTIE_GTDE_Msk       (0x1UL << FDCAN_TTIE_GTDE_Pos)               /*!< 0x00000100 */

+#define FDCAN_TTIE_GTDE           FDCAN_TTIE_GTDE_Msk                          /*!<Global Time Discontinuity Interrupt Enable        */

+#define FDCAN_TTIE_GTEE_Pos       (9U)

+#define FDCAN_TTIE_GTEE_Msk       (0x1UL << FDCAN_TTIE_GTEE_Pos)               /*!< 0x00000200 */

+#define FDCAN_TTIE_GTEE           FDCAN_TTIE_GTEE_Msk                          /*!<Global Time Error Interrupt Enable                */

+#define FDCAN_TTIE_TXUE_Pos       (10U)

+#define FDCAN_TTIE_TXUE_Msk       (0x1UL << FDCAN_TTIE_TXUE_Pos)               /*!< 0x00000400 */

+#define FDCAN_TTIE_TXUE           FDCAN_TTIE_TXUE_Msk                          /*!<Tx Count Underflow Interrupt Enable               */

+#define FDCAN_TTIE_TXOE_Pos       (11U)

+#define FDCAN_TTIE_TXOE_Msk       (0x1UL << FDCAN_TTIE_TXOE_Pos)               /*!< 0x00000800 */

+#define FDCAN_TTIE_TXOE           FDCAN_TTIE_TXOE_Msk                          /*!<Tx Count Overflow Interrupt Enable                */

+#define FDCAN_TTIE_SE1E_Pos       (12U)

+#define FDCAN_TTIE_SE1E_Msk       (0x1UL << FDCAN_TTIE_SE1E_Pos)               /*!< 0x00001000 */

+#define FDCAN_TTIE_SE1E           FDCAN_TTIE_SE1E_Msk                          /*!<Scheduling Error 1 Interrupt Enable               */

+#define FDCAN_TTIE_SE2E_Pos       (13U)

+#define FDCAN_TTIE_SE2E_Msk       (0x1UL << FDCAN_TTIE_SE2E_Pos)               /*!< 0x00002000 */

+#define FDCAN_TTIE_SE2E           FDCAN_TTIE_SE2E_Msk                          /*!<Scheduling Error 2 Interrupt Enable               */

+#define FDCAN_TTIE_ELCE_Pos       (14U)

+#define FDCAN_TTIE_ELCE_Msk       (0x1UL << FDCAN_TTIE_ELCE_Pos)               /*!< 0x00004000 */

+#define FDCAN_TTIE_ELCE           FDCAN_TTIE_ELCE_Msk                          /*!<Error Level Changed Interrupt Enable              */

+#define FDCAN_TTIE_IWTE_Pos       (15U)

+#define FDCAN_TTIE_IWTE_Msk       (0x1UL << FDCAN_TTIE_IWTE_Pos)               /*!< 0x00008000 */

+#define FDCAN_TTIE_IWTE           FDCAN_TTIE_IWTE_Msk                          /*!<Initialization Watch Trigger Interrupt Enable     */

+#define FDCAN_TTIE_WTE_Pos        (16U)

+#define FDCAN_TTIE_WTE_Msk        (0x1UL << FDCAN_TTIE_WTE_Pos)                /*!< 0x00010000 */

+#define FDCAN_TTIE_WTE            FDCAN_TTIE_WTE_Msk                           /*!<Watch Trigger Interrupt Enable                    */

+#define FDCAN_TTIE_AWE_Pos        (17U)

+#define FDCAN_TTIE_AWE_Msk        (0x1UL << FDCAN_TTIE_AWE_Pos)                /*!< 0x00020000 */

+#define FDCAN_TTIE_AWE            FDCAN_TTIE_AWE_Msk                           /*!<Application Watchdog Interrupt Enable             */

+#define FDCAN_TTIE_CERE_Pos       (18U)

+#define FDCAN_TTIE_CERE_Msk       (0x1UL << FDCAN_TTIE_CERE_Pos)               /*!< 0x00040000 */

+#define FDCAN_TTIE_CERE           FDCAN_TTIE_CERE_Msk                          /*!<Configuration Error Interrupt Enable              */

+

+/*****************  Bit definition for FDCAN_TTILS register  ********************/

+#define FDCAN_TTILS_SBCS_Pos      (0U)

+#define FDCAN_TTILS_SBCS_Msk      (0x1UL << FDCAN_TTILS_SBCS_Pos)              /*!< 0x00000001 */

+#define FDCAN_TTILS_SBCS          FDCAN_TTILS_SBCS_Msk                         /*!<Start of Basic Cycle Interrupt Line               */

+#define FDCAN_TTILS_SMCS_Pos      (1U)

+#define FDCAN_TTILS_SMCS_Msk      (0x1UL << FDCAN_TTILS_SMCS_Pos)              /*!< 0x00000002 */

+#define FDCAN_TTILS_SMCS          FDCAN_TTILS_SMCS_Msk                         /*!<Start of Matrix Cycle Interrupt Line              */

+#define FDCAN_TTILS_CSMS_Pos      (2U)

+#define FDCAN_TTILS_CSMS_Msk      (0x1UL << FDCAN_TTILS_CSMS_Pos)              /*!< 0x00000004 */

+#define FDCAN_TTILS_CSMS          FDCAN_TTILS_CSMS_Msk                         /*!<Change of Synchronization Mode Interrupt Line     */

+#define FDCAN_TTILS_SOGS_Pos      (3U)

+#define FDCAN_TTILS_SOGS_Msk      (0x1UL << FDCAN_TTILS_SOGS_Pos)              /*!< 0x00000008 */

+#define FDCAN_TTILS_SOGS          FDCAN_TTILS_SOGS_Msk                         /*!<Start of Gap Interrupt Line                       */

+#define FDCAN_TTILS_RTMIS_Pos     (4U)

+#define FDCAN_TTILS_RTMIS_Msk     (0x1UL << FDCAN_TTILS_RTMIS_Pos)             /*!< 0x00000010 */

+#define FDCAN_TTILS_RTMIS         FDCAN_TTILS_RTMIS_Msk                        /*!<Register Time Mark Interrupt Interrupt Line       */

+#define FDCAN_TTILS_TTMIS_Pos     (5U)

+#define FDCAN_TTILS_TTMIS_Msk     (0x1UL << FDCAN_TTILS_TTMIS_Pos)             /*!< 0x00000020 */

+#define FDCAN_TTILS_TTMIS         FDCAN_TTILS_TTMIS_Msk                        /*!<Trigger Time Mark Event Internal Interrupt Line   */

+#define FDCAN_TTILS_SWES_Pos      (6U)

+#define FDCAN_TTILS_SWES_Msk      (0x1UL << FDCAN_TTILS_SWES_Pos)              /*!< 0x00000040 */

+#define FDCAN_TTILS_SWES          FDCAN_TTILS_SWES_Msk                         /*!<Stop Watch Event Interrupt Line                   */

+#define FDCAN_TTILS_GTWS_Pos      (7U)

+#define FDCAN_TTILS_GTWS_Msk      (0x1UL << FDCAN_TTILS_GTWS_Pos)              /*!< 0x00000080 */

+#define FDCAN_TTILS_GTWS          FDCAN_TTILS_GTWS_Msk                         /*!<Global Time Wrap Interrupt Line                   */

+#define FDCAN_TTILS_GTDS_Pos      (8U)

+#define FDCAN_TTILS_GTDS_Msk      (0x1UL << FDCAN_TTILS_GTDS_Pos)              /*!< 0x00000100 */

+#define FDCAN_TTILS_GTDS          FDCAN_TTILS_GTDS_Msk                         /*!<Global Time Discontinuity Interrupt Line          */

+#define FDCAN_TTILS_GTES_Pos      (9U)

+#define FDCAN_TTILS_GTES_Msk      (0x1UL << FDCAN_TTILS_GTES_Pos)              /*!< 0x00000200 */

+#define FDCAN_TTILS_GTES          FDCAN_TTILS_GTES_Msk                         /*!<Global Time Error Interrupt Line                  */

+#define FDCAN_TTILS_TXUS_Pos      (10U)

+#define FDCAN_TTILS_TXUS_Msk      (0x1UL << FDCAN_TTILS_TXUS_Pos)              /*!< 0x00000400 */

+#define FDCAN_TTILS_TXUS          FDCAN_TTILS_TXUS_Msk                         /*!<Tx Count Underflow Interrupt Line                 */

+#define FDCAN_TTILS_TXOS_Pos      (11U)

+#define FDCAN_TTILS_TXOS_Msk      (0x1UL << FDCAN_TTILS_TXOS_Pos)              /*!< 0x00000800 */

+#define FDCAN_TTILS_TXOS          FDCAN_TTILS_TXOS_Msk                         /*!<Tx Count Overflow Interrupt Line                  */

+#define FDCAN_TTILS_SE1S_Pos      (12U)

+#define FDCAN_TTILS_SE1S_Msk      (0x1UL << FDCAN_TTILS_SE1S_Pos)              /*!< 0x00001000 */

+#define FDCAN_TTILS_SE1S          FDCAN_TTILS_SE1S_Msk                         /*!<Scheduling Error 1 Interrupt Line                 */

+#define FDCAN_TTILS_SE2S_Pos      (13U)

+#define FDCAN_TTILS_SE2S_Msk      (0x1UL << FDCAN_TTILS_SE2S_Pos)              /*!< 0x00002000 */

+#define FDCAN_TTILS_SE2S          FDCAN_TTILS_SE2S_Msk                         /*!<Scheduling Error 2 Interrupt Line                 */

+#define FDCAN_TTILS_ELCS_Pos      (14U)

+#define FDCAN_TTILS_ELCS_Msk      (0x1UL << FDCAN_TTILS_ELCS_Pos)              /*!< 0x00004000 */

+#define FDCAN_TTILS_ELCS          FDCAN_TTILS_ELCS_Msk                         /*!<Error Level Changed Interrupt Line                */

+#define FDCAN_TTILS_IWTS_Pos      (15U)

+#define FDCAN_TTILS_IWTS_Msk      (0x1UL << FDCAN_TTILS_IWTS_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTILS_IWTS          FDCAN_TTILS_IWTS_Msk                         /*!<Initialization Watch Trigger Interrupt Line       */

+#define FDCAN_TTILS_WTS_Pos       (16U)

+#define FDCAN_TTILS_WTS_Msk       (0x1UL << FDCAN_TTILS_WTS_Pos)               /*!< 0x00010000 */

+#define FDCAN_TTILS_WTS           FDCAN_TTILS_WTS_Msk                          /*!<Watch Trigger Interrupt Line                      */

+#define FDCAN_TTILS_AWS_Pos       (17U)

+#define FDCAN_TTILS_AWS_Msk       (0x1UL << FDCAN_TTILS_AWS_Pos)               /*!< 0x00020000 */

+#define FDCAN_TTILS_AWS           FDCAN_TTILS_AWS_Msk                          /*!<Application Watchdog Interrupt Line               */

+#define FDCAN_TTILS_CERS_Pos      (18U)

+#define FDCAN_TTILS_CERS_Msk      (0x1UL << FDCAN_TTILS_CERS_Pos)              /*!< 0x00040000 */

+#define FDCAN_TTILS_CERS          FDCAN_TTILS_CERS_Msk                         /*!<Configuration Error Interrupt Line                */

+

+/*****************  Bit definition for FDCAN_TTOST register  ********************/

+#define FDCAN_TTOST_EL_Pos        (0U)

+#define FDCAN_TTOST_EL_Msk        (0x3UL << FDCAN_TTOST_EL_Pos)                /*!< 0x00000003 */

+#define FDCAN_TTOST_EL            FDCAN_TTOST_EL_Msk                           /*!<Error Level                              */

+#define FDCAN_TTOST_MS_Pos        (2U)

+#define FDCAN_TTOST_MS_Msk        (0x3UL << FDCAN_TTOST_MS_Pos)                /*!< 0x0000000C */

+#define FDCAN_TTOST_MS            FDCAN_TTOST_MS_Msk                           /*!<Master State                             */

+#define FDCAN_TTOST_SYS_Pos       (4U)

+#define FDCAN_TTOST_SYS_Msk       (0x3UL << FDCAN_TTOST_SYS_Pos)               /*!< 0x00000030 */

+#define FDCAN_TTOST_SYS           FDCAN_TTOST_SYS_Msk                          /*!<Synchronization State                    */

+#define FDCAN_TTOST_QGTP_Pos      (6U)

+#define FDCAN_TTOST_QGTP_Msk      (0x1UL << FDCAN_TTOST_QGTP_Pos)              /*!< 0x00000040 */

+#define FDCAN_TTOST_QGTP          FDCAN_TTOST_QGTP_Msk                         /*!<Quality of Global Time Phase             */

+#define FDCAN_TTOST_QCS_Pos       (7U)

+#define FDCAN_TTOST_QCS_Msk       (0x1UL << FDCAN_TTOST_QCS_Pos)               /*!< 0x00000080 */

+#define FDCAN_TTOST_QCS           FDCAN_TTOST_QCS_Msk                          /*!<Quality of Clock Speed                   */

+#define FDCAN_TTOST_RTO_Pos       (8U)

+#define FDCAN_TTOST_RTO_Msk       (0xFFUL << FDCAN_TTOST_RTO_Pos)              /*!< 0x0000FF00 */

+#define FDCAN_TTOST_RTO           FDCAN_TTOST_RTO_Msk                          /*!<Reference Trigger Offset                 */

+#define FDCAN_TTOST_WGTD_Pos      (22U)

+#define FDCAN_TTOST_WGTD_Msk      (0x1UL << FDCAN_TTOST_WGTD_Pos)              /*!< 0x00400000 */

+#define FDCAN_TTOST_WGTD          FDCAN_TTOST_WGTD_Msk                         /*!<Wait for Global Time Discontinuity       */

+#define FDCAN_TTOST_GFI_Pos       (23U)

+#define FDCAN_TTOST_GFI_Msk       (0x1UL << FDCAN_TTOST_GFI_Pos)               /*!< 0x00800000 */

+#define FDCAN_TTOST_GFI           FDCAN_TTOST_GFI_Msk                          /*!<Gap Finished Indicator                   */

+#define FDCAN_TTOST_TMP_Pos       (24U)

+#define FDCAN_TTOST_TMP_Msk       (0x7UL << FDCAN_TTOST_TMP_Pos)               /*!< 0x07000000 */

+#define FDCAN_TTOST_TMP           FDCAN_TTOST_TMP_Msk                          /*!<Time Master Priority                     */

+#define FDCAN_TTOST_GSI_Pos       (27U)

+#define FDCAN_TTOST_GSI_Msk       (0x1UL << FDCAN_TTOST_GSI_Pos)               /*!< 0x08000000 */

+#define FDCAN_TTOST_GSI           FDCAN_TTOST_GSI_Msk                          /*!<Gap Started Indicator                    */

+#define FDCAN_TTOST_WFE_Pos       (28U)

+#define FDCAN_TTOST_WFE_Msk       (0x1UL << FDCAN_TTOST_WFE_Pos)               /*!< 0x10000000 */

+#define FDCAN_TTOST_WFE           FDCAN_TTOST_WFE_Msk                          /*!<Wait for Event                           */

+#define FDCAN_TTOST_AWE_Pos       (29U)

+#define FDCAN_TTOST_AWE_Msk       (0x1UL << FDCAN_TTOST_AWE_Pos)               /*!< 0x20000000 */

+#define FDCAN_TTOST_AWE           FDCAN_TTOST_AWE_Msk                          /*!<Application Watchdog Event               */

+#define FDCAN_TTOST_WECS_Pos      (30U)

+#define FDCAN_TTOST_WECS_Msk      (0x1UL << FDCAN_TTOST_WECS_Pos)              /*!< 0x40000000 */

+#define FDCAN_TTOST_WECS          FDCAN_TTOST_WECS_Msk                         /*!<Wait for External Clock Synchronization  */

+#define FDCAN_TTOST_SPL_Pos       (31U)

+#define FDCAN_TTOST_SPL_Msk       (0x1UL << FDCAN_TTOST_SPL_Pos)               /*!< 0x80000000 */

+#define FDCAN_TTOST_SPL           FDCAN_TTOST_SPL_Msk                          /*!<Schedule Phase Lock                      */

+

+/*****************  Bit definition for FDCAN_TURNA register  ********************/

+#define FDCAN_TURNA_NAV_Pos       (0U)

+#define FDCAN_TURNA_NAV_Msk       (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)           /*!< 0x0003FFFF */

+#define FDCAN_TURNA_NAV           FDCAN_TURNA_NAV_Msk                          /*!<Numerator Actual Value                   */

+

+/*****************  Bit definition for FDCAN_TTLGT register  ********************/

+#define FDCAN_TTLGT_LT_Pos        (0U)

+#define FDCAN_TTLGT_LT_Msk        (0xFFFFUL << FDCAN_TTLGT_LT_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTLGT_LT            FDCAN_TTLGT_LT_Msk                           /*!<Local Time                               */

+#define FDCAN_TTLGT_GT_Pos        (16U)

+#define FDCAN_TTLGT_GT_Msk        (0xFFFFUL << FDCAN_TTLGT_GT_Pos)             /*!< 0xFFFF0000 */

+#define FDCAN_TTLGT_GT            FDCAN_TTLGT_GT_Msk                           /*!<Global Time                              */

+

+/*****************  Bit definition for FDCAN_TTCTC register  ********************/

+#define FDCAN_TTCTC_CT_Pos        (0U)

+#define FDCAN_TTCTC_CT_Msk        (0xFFFFUL << FDCAN_TTCTC_CT_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTCTC_CT            FDCAN_TTCTC_CT_Msk                           /*!<Cycle Time                               */

+#define FDCAN_TTCTC_CC_Pos        (16U)

+#define FDCAN_TTCTC_CC_Msk        (0x3FUL << FDCAN_TTCTC_CC_Pos)               /*!< 0x003F0000 */

+#define FDCAN_TTCTC_CC            FDCAN_TTCTC_CC_Msk                           /*!<Cycle Count                              */

+

+/*****************  Bit definition for FDCAN_TTCPT register  ********************/

+#define FDCAN_TTCPT_CCV_Pos       (0U)

+#define FDCAN_TTCPT_CCV_Msk       (0x3FUL << FDCAN_TTCPT_CCV_Pos)              /*!< 0x0000003F */

+#define FDCAN_TTCPT_CCV           FDCAN_TTCPT_CCV_Msk                          /*!<Cycle Count Value                        */

+#define FDCAN_TTCPT_SWV_Pos       (16U)

+#define FDCAN_TTCPT_SWV_Msk       (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)            /*!< 0xFFFF0000 */

+#define FDCAN_TTCPT_SWV           FDCAN_TTCPT_SWV_Msk                          /*!<Stop Watch Value                         */

+

+/*****************  Bit definition for FDCAN_TTCSM register  ********************/

+#define FDCAN_TTCSM_CSM_Pos       (0U)

+#define FDCAN_TTCSM_CSM_Msk       (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)            /*!< 0x0000FFFF */

+#define FDCAN_TTCSM_CSM           FDCAN_TTCSM_CSM_Msk                          /*!<Cycle Sync Mark                          */

+

+/*****************  Bit definition for FDCAN_TTTS register  *********************/

+#define FDCAN_TTTS_SWTSEL_Pos     (0U)

+#define FDCAN_TTTS_SWTSEL_Msk     (0x3UL << FDCAN_TTTS_SWTSEL_Pos)             /*!< 0x00000003 */

+#define FDCAN_TTTS_SWTSEL         FDCAN_TTTS_SWTSEL_Msk                        /*!<Stop watch trigger input selection       */

+#define FDCAN_TTTS_EVTSEL_Pos     (4U)

+#define FDCAN_TTTS_EVTSEL_Msk     (0x3UL << FDCAN_TTTS_EVTSEL_Pos)             /*!< 0x00000030 */

+#define FDCAN_TTTS_EVTSEL         FDCAN_TTTS_EVTSEL_Msk                        /*!<Event trigger input selection            */

+

+/********************************************************************************/

+/*                                                                              */

+/*                      FDCANCCU (Clock Calibration unit)                       */

+/*                                                                              */

+/********************************************************************************/

+

+/*****************  Bit definition for FDCANCCU_CREL register  ******************/

+#define FDCANCCU_CREL_DAY_Pos        (0U)

+#define FDCANCCU_CREL_DAY_Msk        (0xFFUL << FDCANCCU_CREL_DAY_Pos)         /*!< 0x000000FF */

+#define FDCANCCU_CREL_DAY            FDCANCCU_CREL_DAY_Msk                     /*!<Timestamp Day                           */

+#define FDCANCCU_CREL_MON_Pos        (8U)

+#define FDCANCCU_CREL_MON_Msk        (0xFFUL << FDCANCCU_CREL_MON_Pos)         /*!< 0x0000FF00 */

+#define FDCANCCU_CREL_MON            FDCANCCU_CREL_MON_Msk                     /*!<Timestamp Month                         */

+#define FDCANCCU_CREL_YEAR_Pos       (16U)

+#define FDCANCCU_CREL_YEAR_Msk       (0xFUL << FDCANCCU_CREL_YEAR_Pos)         /*!< 0x000F0000 */

+#define FDCANCCU_CREL_YEAR           FDCANCCU_CREL_YEAR_Msk                    /*!<Timestamp Year                          */

+#define FDCANCCU_CREL_SUBSTEP_Pos    (20U)

+#define FDCANCCU_CREL_SUBSTEP_Msk    (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)      /*!< 0x00F00000 */

+#define FDCANCCU_CREL_SUBSTEP        FDCANCCU_CREL_SUBSTEP_Msk                 /*!<Sub-step of Core release                */

+#define FDCANCCU_CREL_STEP_Pos       (24U)

+#define FDCANCCU_CREL_STEP_Msk       (0xFUL << FDCANCCU_CREL_STEP_Pos)         /*!< 0x0F000000 */

+#define FDCANCCU_CREL_STEP           FDCANCCU_CREL_STEP_Msk                    /*!<Step of Core release                    */

+#define FDCANCCU_CREL_REL_Pos        (28U)

+#define FDCANCCU_CREL_REL_Msk        (0xFUL << FDCANCCU_CREL_REL_Pos)          /*!< 0xF0000000 */

+#define FDCANCCU_CREL_REL            FDCANCCU_CREL_REL_Msk                     /*!<Core release                            */

+

+/*****************  Bit definition for FDCANCCU_CCFG register  ******************/

+#define FDCANCCU_CCFG_TQBT_Pos       (0U)

+#define FDCANCCU_CCFG_TQBT_Msk       (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)        /*!< 0x0000001F */

+#define FDCANCCU_CCFG_TQBT           FDCANCCU_CCFG_TQBT_Msk                    /*!<Time Quanta per Bit Time                */

+#define FDCANCCU_CCFG_BCC_Pos        (6U)

+#define FDCANCCU_CCFG_BCC_Msk        (0x1UL << FDCANCCU_CCFG_BCC_Pos)          /*!< 0x00000040 */

+#define FDCANCCU_CCFG_BCC            FDCANCCU_CCFG_BCC_Msk                     /*!<Bypass Clock Calibration                */

+#define FDCANCCU_CCFG_CFL_Pos        (7U)

+#define FDCANCCU_CCFG_CFL_Msk        (0x1UL << FDCANCCU_CCFG_CFL_Pos)          /*!< 0x00000080 */

+#define FDCANCCU_CCFG_CFL            FDCANCCU_CCFG_CFL_Msk                     /*!<Calibration Field Length                */

+#define FDCANCCU_CCFG_OCPM_Pos       (8U)

+#define FDCANCCU_CCFG_OCPM_Msk       (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)        /*!< 0x0000FF00 */

+#define FDCANCCU_CCFG_OCPM           FDCANCCU_CCFG_OCPM_Msk                    /*!<Oscillator Clock Periods Minimum        */

+#define FDCANCCU_CCFG_CDIV_Pos       (16U)

+#define FDCANCCU_CCFG_CDIV_Msk       (0xFUL << FDCANCCU_CCFG_CDIV_Pos)         /*!< 0x000F0000 */

+#define FDCANCCU_CCFG_CDIV           FDCANCCU_CCFG_CDIV_Msk                    /*!<Clock Divider                           */

+#define FDCANCCU_CCFG_SWR_Pos        (31U)

+#define FDCANCCU_CCFG_SWR_Msk        (0x1UL << FDCANCCU_CCFG_SWR_Pos)          /*!< 0x80000000 */

+#define FDCANCCU_CCFG_SWR            FDCANCCU_CCFG_SWR_Msk                     /*!<Software Reset                          */

+

+/*****************  Bit definition for FDCANCCU_CSTAT register  *****************/

+#define FDCANCCU_CSTAT_OCPC_Pos      (0U)

+#define FDCANCCU_CSTAT_OCPC_Msk      (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)    /*!< 0x0003FFFF */

+#define FDCANCCU_CSTAT_OCPC          FDCANCCU_CSTAT_OCPC_Msk                   /*!<Oscillator Clock Period Counter        */

+#define FDCANCCU_CSTAT_TQC_Pos       (18U)

+#define FDCANCCU_CSTAT_TQC_Msk       (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)       /*!< 0x1FFC0000 */

+#define FDCANCCU_CSTAT_TQC           FDCANCCU_CSTAT_TQC_Msk                    /*!<Time Quanta Counter                    */

+#define FDCANCCU_CSTAT_CALS_Pos      (30U)

+#define FDCANCCU_CSTAT_CALS_Msk      (0x3UL << FDCANCCU_CSTAT_CALS_Pos)        /*!< 0xC0000000 */

+#define FDCANCCU_CSTAT_CALS          FDCANCCU_CSTAT_CALS_Msk                   /*!<Calibration State                      */

+

+/******************  Bit definition for FDCANCCU_CWD register  ******************/

+#define FDCANCCU_CWD_WDC_Pos         (0U)

+#define FDCANCCU_CWD_WDC_Msk         (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)        /*!< 0x0000FFFF */

+#define FDCANCCU_CWD_WDC             FDCANCCU_CWD_WDC_Msk                      /*!<Watchdog Configuration                 */

+#define FDCANCCU_CWD_WDV_Pos         (16U)

+#define FDCANCCU_CWD_WDV_Msk         (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)        /*!< 0xFFFF0000 */

+#define FDCANCCU_CWD_WDV             FDCANCCU_CWD_WDV_Msk                      /*!<Watchdog Value                         */

+

+/******************  Bit definition for FDCANCCU_IR register  *******************/

+#define FDCANCCU_IR_CWE_Pos          (0U)

+#define FDCANCCU_IR_CWE_Msk          (0x1UL << FDCANCCU_IR_CWE_Pos)            /*!< 0x00000001 */

+#define FDCANCCU_IR_CWE              FDCANCCU_IR_CWE_Msk                       /*!<Calibration Watchdog Event             */

+#define FDCANCCU_IR_CSC_Pos          (1U)

+#define FDCANCCU_IR_CSC_Msk          (0x1UL << FDCANCCU_IR_CSC_Pos)            /*!< 0x00000002 */

+#define FDCANCCU_IR_CSC              FDCANCCU_IR_CSC_Msk                       /*!<Calibration State Changed              */

+

+/******************  Bit definition for FDCANCCU_IE register  *******************/

+#define FDCANCCU_IE_CWEE_Pos         (0U)

+#define FDCANCCU_IE_CWEE_Msk         (0x1UL << FDCANCCU_IE_CWEE_Pos)           /*!< 0x00000001 */

+#define FDCANCCU_IE_CWEE             FDCANCCU_IE_CWEE_Msk                      /*!<Calibration Watchdog Event Enable      */

+#define FDCANCCU_IE_CSCE_Pos         (1U)

+#define FDCANCCU_IE_CSCE_Msk         (0x1UL << FDCANCCU_IE_CSCE_Pos)           /*!< 0x00000002 */

+#define FDCANCCU_IE_CSCE             FDCANCCU_IE_CSCE_Msk                      /*!<Calibration State Changed Enable       */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          HDMI-CEC (CEC)                                    */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for CEC_CR register  *********************/

+#define CEC_CR_CECEN_Pos         (0U)

+#define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                   /*!< 0x00000001 */

+#define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                                */

+#define CEC_CR_TXSOM_Pos         (1U)

+#define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                   /*!< 0x00000002 */

+#define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message                   */

+#define CEC_CR_TXEOM_Pos         (2U)

+#define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                   /*!< 0x00000004 */

+#define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message                     */

+

+/*******************  Bit definition for CEC_CFGR register  *******************/

+#define CEC_CFGR_SFT_Pos         (0U)

+#define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                   /*!< 0x00000007 */

+#define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time                      */

+#define CEC_CFGR_RXTOL_Pos       (3U)

+#define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                 /*!< 0x00000008 */

+#define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                             */

+#define CEC_CFGR_BRESTP_Pos      (4U)

+#define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                /*!< 0x00000010 */

+#define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                               */

+#define CEC_CFGR_BREGEN_Pos      (5U)

+#define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                /*!< 0x00000020 */

+#define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation           */

+#define CEC_CFGR_LBPEGEN_Pos     (6U)

+#define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)               /*!< 0x00000040 */

+#define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error generation      */

+#define CEC_CFGR_SFTOPT_Pos      (8U)

+#define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                /*!< 0x00000100 */

+#define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional             */

+#define CEC_CFGR_BRDNOGEN_Pos    (7U)

+#define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)              /*!< 0x00000080 */

+#define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No error generation         */

+#define CEC_CFGR_OAR_Pos         (16U)

+#define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                /*!< 0x7FFF0000 */

+#define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                           */

+#define CEC_CFGR_LSTN_Pos        (31U)

+#define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                  /*!< 0x80000000 */

+#define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                           */

+

+/*******************  Bit definition for CEC_TXDR register  *******************/

+#define CEC_TXDR_TXD_Pos         (0U)

+#define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                  /*!< 0x000000FF */

+#define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                               */

+

+/*******************  Bit definition for CEC_RXDR register  *******************/

+#define CEC_RXDR_RXD_Pos         (0U)

+#define CEC_RXDR_RXD_Msk         (0xFFUL << CEC_RXDR_RXD_Pos)                  /*!< 0x000000FF */

+#define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                              /*!< CEC Rx Data                               */

+

+/*******************  Bit definition for CEC_ISR register  ********************/

+#define CEC_ISR_RXBR_Pos         (0U)

+#define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                   /*!< 0x00000001 */

+#define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                      */

+#define CEC_ISR_RXEND_Pos        (1U)

+#define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                  /*!< 0x00000002 */

+#define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                      */

+#define CEC_ISR_RXOVR_Pos        (2U)

+#define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                  /*!< 0x00000004 */

+#define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                            */

+#define CEC_ISR_BRE_Pos          (3U)

+#define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                    /*!< 0x00000008 */

+#define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                   */

+#define CEC_ISR_SBPE_Pos         (4U)

+#define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                   /*!< 0x00000010 */

+#define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error             */

+#define CEC_ISR_LBPE_Pos         (5U)

+#define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                   /*!< 0x00000020 */

+#define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error              */

+#define CEC_ISR_RXACKE_Pos       (6U)

+#define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                 /*!< 0x00000040 */

+#define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge                */

+#define CEC_ISR_ARBLST_Pos       (7U)

+#define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                 /*!< 0x00000080 */

+#define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                      */

+#define CEC_ISR_TXBR_Pos         (8U)

+#define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                   /*!< 0x00000100 */

+#define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                       */

+#define CEC_ISR_TXEND_Pos        (9U)

+#define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                  /*!< 0x00000200 */

+#define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                   */

+#define CEC_ISR_TXUDR_Pos        (10U)

+#define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                  /*!< 0x00000400 */

+#define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                    */

+#define CEC_ISR_TXERR_Pos        (11U)

+#define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                  /*!< 0x00000800 */

+#define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                              */

+#define CEC_ISR_TXACKE_Pos       (12U)

+#define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                 /*!< 0x00001000 */

+#define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge                */

+

+/*******************  Bit definition for CEC_IER register  ********************/

+#define CEC_IER_RXBRIE_Pos       (0U)

+#define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                 /*!< 0x00000001 */

+#define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable            */

+#define CEC_IER_RXENDIE_Pos      (1U)

+#define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                /*!< 0x00000002 */

+#define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable            */

+#define CEC_IER_RXOVRIE_Pos      (2U)

+#define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                /*!< 0x00000004 */

+#define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable                  */

+#define CEC_IER_BREIE_Pos        (3U)

+#define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                  /*!< 0x00000008 */

+#define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable         */

+#define CEC_IER_SBPEIE_Pos       (4U)

+#define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                 /*!< 0x00000010 */

+#define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable   */

+#define CEC_IER_LBPEIE_Pos       (5U)

+#define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                 /*!< 0x00000020 */

+#define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable    */

+#define CEC_IER_RXACKEIE_Pos     (6U)

+#define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)               /*!< 0x00000040 */

+#define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable      */

+#define CEC_IER_ARBLSTIE_Pos     (7U)

+#define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)               /*!< 0x00000080 */

+#define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable            */

+#define CEC_IER_TXBRIE_Pos       (8U)

+#define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                 /*!< 0x00000100 */

+#define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable            */

+#define CEC_IER_TXENDIE_Pos      (9U)

+#define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                /*!< 0x00000200 */

+#define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable         */

+#define CEC_IER_TXUDRIE_Pos      (10U)

+#define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                /*!< 0x00000400 */

+#define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable          */

+#define CEC_IER_TXERRIE_Pos      (11U)

+#define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                /*!< 0x00000800 */

+#define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                    */

+#define CEC_IER_TXACKEIE_Pos     (12U)

+#define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)               /*!< 0x00001000 */

+#define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable      */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          CRC calculation unit                              */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for CRC_DR register  *********************/

+#define CRC_DR_DR_Pos            (0U)

+#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */

+#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */

+

+/*******************  Bit definition for CRC_IDR register  ********************/

+#define CRC_IDR_IDR_Pos          (0U)

+#define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */

+#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */

+

+/********************  Bit definition for CRC_CR register  ********************/

+#define CRC_CR_RESET_Pos         (0U)

+#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */

+#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */

+#define CRC_CR_POLYSIZE_Pos      (3U)

+#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */

+#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */

+#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */

+#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */

+#define CRC_CR_REV_IN_Pos        (5U)

+#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */

+#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */

+#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */

+#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */

+#define CRC_CR_REV_OUT_Pos       (7U)

+#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */

+#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */

+

+/*******************  Bit definition for CRC_INIT register  *******************/

+#define CRC_INIT_INIT_Pos        (0U)

+#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */

+#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */

+

+/*******************  Bit definition for CRC_POL register  ********************/

+#define CRC_POL_POL_Pos          (0U)

+#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */

+#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          CRS Clock Recovery System                         */

+/******************************************************************************/

+

+/*******************  Bit definition for CRS_CR register  *********************/

+#define CRS_CR_SYNCOKIE_Pos       (0U)

+#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */

+#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */

+#define CRS_CR_SYNCWARNIE_Pos     (1U)

+#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */

+#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */

+#define CRS_CR_ERRIE_Pos          (2U)

+#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */

+#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */

+#define CRS_CR_ESYNCIE_Pos        (3U)

+#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */

+#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */

+#define CRS_CR_CEN_Pos            (5U)

+#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */

+#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */

+#define CRS_CR_AUTOTRIMEN_Pos     (6U)

+#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */

+#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */

+#define CRS_CR_SWSYNC_Pos         (7U)

+#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */

+#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */

+#define CRS_CR_TRIM_Pos           (8U)

+#define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00003F00 */

+#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */

+

+/*******************  Bit definition for CRS_CFGR register  *********************/

+#define CRS_CFGR_RELOAD_Pos       (0U)

+#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */

+#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */

+#define CRS_CFGR_FELIM_Pos        (16U)

+#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */

+#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */

+

+#define CRS_CFGR_SYNCDIV_Pos      (24U)

+#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */

+#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */

+#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */

+#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */

+#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */

+

+#define CRS_CFGR_SYNCSRC_Pos      (28U)

+#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */

+#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */

+#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */

+#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */

+

+#define CRS_CFGR_SYNCPOL_Pos      (31U)

+#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */

+#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */

+

+/*******************  Bit definition for CRS_ISR register  *********************/

+#define CRS_ISR_SYNCOKF_Pos       (0U)

+#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */

+#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */

+#define CRS_ISR_SYNCWARNF_Pos     (1U)

+#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */

+#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */

+#define CRS_ISR_ERRF_Pos          (2U)

+#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */

+#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */

+#define CRS_ISR_ESYNCF_Pos        (3U)

+#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */

+#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */

+#define CRS_ISR_SYNCERR_Pos       (8U)

+#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */

+#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */

+#define CRS_ISR_SYNCMISS_Pos      (9U)

+#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */

+#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */

+#define CRS_ISR_TRIMOVF_Pos       (10U)

+#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */

+#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */

+#define CRS_ISR_FEDIR_Pos         (15U)

+#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */

+#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */

+#define CRS_ISR_FECAP_Pos         (16U)

+#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */

+#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */

+

+/*******************  Bit definition for CRS_ICR register  *********************/

+#define CRS_ICR_SYNCOKC_Pos       (0U)

+#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */

+#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */

+#define CRS_ICR_SYNCWARNC_Pos     (1U)

+#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */

+#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */

+#define CRS_ICR_ERRC_Pos          (2U)

+#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */

+#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */

+#define CRS_ICR_ESYNCC_Pos        (3U)

+#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */

+#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            Crypto Processor                                */

+/*                                                                            */

+/******************************************************************************/

+/********************************  CRYP VER  **********************************/

+#define  CRYP_VER_2_2

+/******************* Bits definition for CRYP_CR register  ********************/

+#define CRYP_CR_ALGODIR_Pos              (2U)

+#define CRYP_CR_ALGODIR_Msk              (0x1UL << CRYP_CR_ALGODIR_Pos)        /*!< 0x00000004 */

+#define CRYP_CR_ALGODIR                  CRYP_CR_ALGODIR_Msk

+

+#define CRYP_CR_ALGOMODE_Pos             (3U)

+#define CRYP_CR_ALGOMODE_Msk             (0x10007UL << CRYP_CR_ALGOMODE_Pos)   /*!< 0x00080038 */

+#define CRYP_CR_ALGOMODE                 CRYP_CR_ALGOMODE_Msk

+#define CRYP_CR_ALGOMODE_0               (0x00001UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000008 */

+#define CRYP_CR_ALGOMODE_1               (0x00002UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000010 */

+#define CRYP_CR_ALGOMODE_2               (0x00004UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000020 */

+#define CRYP_CR_ALGOMODE_TDES_ECB        ((uint32_t)0x00000000)

+#define CRYP_CR_ALGOMODE_TDES_CBC_Pos    (3U)

+#define CRYP_CR_ALGOMODE_TDES_CBC_Msk    (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */

+#define CRYP_CR_ALGOMODE_TDES_CBC        CRYP_CR_ALGOMODE_TDES_CBC_Msk

+#define CRYP_CR_ALGOMODE_DES_ECB_Pos     (4U)

+#define CRYP_CR_ALGOMODE_DES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_DES_ECB_Pos) /*!< 0x00000010 */

+#define CRYP_CR_ALGOMODE_DES_ECB         CRYP_CR_ALGOMODE_DES_ECB_Msk

+#define CRYP_CR_ALGOMODE_DES_CBC_Pos     (3U)

+#define CRYP_CR_ALGOMODE_DES_CBC_Msk     (0x3UL << CRYP_CR_ALGOMODE_DES_CBC_Pos) /*!< 0x00000018 */

+#define CRYP_CR_ALGOMODE_DES_CBC         CRYP_CR_ALGOMODE_DES_CBC_Msk

+#define CRYP_CR_ALGOMODE_AES_ECB_Pos     (5U)

+#define CRYP_CR_ALGOMODE_AES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */

+#define CRYP_CR_ALGOMODE_AES_ECB         CRYP_CR_ALGOMODE_AES_ECB_Msk

+#define CRYP_CR_ALGOMODE_AES_CBC_Pos     (3U)

+#define CRYP_CR_ALGOMODE_AES_CBC_Msk     (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */

+#define CRYP_CR_ALGOMODE_AES_CBC         CRYP_CR_ALGOMODE_AES_CBC_Msk

+#define CRYP_CR_ALGOMODE_AES_CTR_Pos     (4U)

+#define CRYP_CR_ALGOMODE_AES_CTR_Msk     (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */

+#define CRYP_CR_ALGOMODE_AES_CTR         CRYP_CR_ALGOMODE_AES_CTR_Msk

+#define CRYP_CR_ALGOMODE_AES_KEY_Pos     (3U)

+#define CRYP_CR_ALGOMODE_AES_KEY_Msk     (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */

+#define CRYP_CR_ALGOMODE_AES_KEY         CRYP_CR_ALGOMODE_AES_KEY_Msk

+#define CRYP_CR_ALGOMODE_AES_GCM_Pos     (19U)

+#define CRYP_CR_ALGOMODE_AES_GCM_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_GCM_Pos) /*!< 0x00080000 */

+#define CRYP_CR_ALGOMODE_AES_GCM         CRYP_CR_ALGOMODE_AES_GCM_Msk

+#define CRYP_CR_ALGOMODE_AES_CCM_Pos     (3U)

+#define CRYP_CR_ALGOMODE_AES_CCM_Msk     (0x10001UL << CRYP_CR_ALGOMODE_AES_CCM_Pos) /*!< 0x00080008 */

+#define CRYP_CR_ALGOMODE_AES_CCM         CRYP_CR_ALGOMODE_AES_CCM_Msk

+

+#define CRYP_CR_DATATYPE_Pos             (6U)

+#define CRYP_CR_DATATYPE_Msk             (0x3UL << CRYP_CR_DATATYPE_Pos)       /*!< 0x000000C0 */

+#define CRYP_CR_DATATYPE                 CRYP_CR_DATATYPE_Msk

+#define CRYP_CR_DATATYPE_0               (0x1UL << CRYP_CR_DATATYPE_Pos)        /*!< 0x00000040 */

+#define CRYP_CR_DATATYPE_1               (0x2UL << CRYP_CR_DATATYPE_Pos)        /*!< 0x00000080 */

+#define CRYP_CR_KEYSIZE_Pos              (8U)

+#define CRYP_CR_KEYSIZE_Msk              (0x3UL << CRYP_CR_KEYSIZE_Pos)        /*!< 0x00000300 */

+#define CRYP_CR_KEYSIZE                  CRYP_CR_KEYSIZE_Msk

+#define CRYP_CR_KEYSIZE_0                (0x1UL << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000100 */

+#define CRYP_CR_KEYSIZE_1                (0x2UL << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000200 */

+#define CRYP_CR_FFLUSH_Pos               (14U)

+#define CRYP_CR_FFLUSH_Msk               (0x1UL << CRYP_CR_FFLUSH_Pos)         /*!< 0x00004000 */

+#define CRYP_CR_FFLUSH                   CRYP_CR_FFLUSH_Msk

+#define CRYP_CR_CRYPEN_Pos               (15U)

+#define CRYP_CR_CRYPEN_Msk               (0x1UL << CRYP_CR_CRYPEN_Pos)         /*!< 0x00008000 */

+#define CRYP_CR_CRYPEN                   CRYP_CR_CRYPEN_Msk

+

+#define CRYP_CR_GCM_CCMPH_Pos            (16U)

+#define CRYP_CR_GCM_CCMPH_Msk            (0x3UL << CRYP_CR_GCM_CCMPH_Pos)      /*!< 0x00030000 */

+#define CRYP_CR_GCM_CCMPH                CRYP_CR_GCM_CCMPH_Msk

+#define CRYP_CR_GCM_CCMPH_0              (0x1UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00010000 */

+#define CRYP_CR_GCM_CCMPH_1              (0x2UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00020000 */

+#define CRYP_CR_ALGOMODE_3               ((uint32_t)0x00080000)

+#define CRYP_CR_NPBLB_Pos                (20U)

+#define CRYP_CR_NPBLB_Msk                (0xFUL << CRYP_CR_NPBLB_Pos)          /*!< 0x00F00000 */

+#define CRYP_CR_NPBLB                    CRYP_CR_NPBLB_Msk

+

+/****************** Bits definition for CRYP_SR register  *********************/

+#define CRYP_SR_IFEM_Pos                 (0U)

+#define CRYP_SR_IFEM_Msk                 (0x1UL << CRYP_SR_IFEM_Pos)           /*!< 0x00000001 */

+#define CRYP_SR_IFEM                     CRYP_SR_IFEM_Msk

+#define CRYP_SR_IFNF_Pos                 (1U)

+#define CRYP_SR_IFNF_Msk                 (0x1UL << CRYP_SR_IFNF_Pos)           /*!< 0x00000002 */

+#define CRYP_SR_IFNF                     CRYP_SR_IFNF_Msk

+#define CRYP_SR_OFNE_Pos                 (2U)

+#define CRYP_SR_OFNE_Msk                 (0x1UL << CRYP_SR_OFNE_Pos)           /*!< 0x00000004 */

+#define CRYP_SR_OFNE                     CRYP_SR_OFNE_Msk

+#define CRYP_SR_OFFU_Pos                 (3U)

+#define CRYP_SR_OFFU_Msk                 (0x1UL << CRYP_SR_OFFU_Pos)           /*!< 0x00000008 */

+#define CRYP_SR_OFFU                     CRYP_SR_OFFU_Msk

+#define CRYP_SR_BUSY_Pos                 (4U)

+#define CRYP_SR_BUSY_Msk                 (0x1UL << CRYP_SR_BUSY_Pos)           /*!< 0x00000010 */

+#define CRYP_SR_BUSY                     CRYP_SR_BUSY_Msk

+/****************** Bits definition for CRYP_DMACR register  ******************/

+#define CRYP_DMACR_DIEN_Pos              (0U)

+#define CRYP_DMACR_DIEN_Msk              (0x1UL << CRYP_DMACR_DIEN_Pos)        /*!< 0x00000001 */

+#define CRYP_DMACR_DIEN                  CRYP_DMACR_DIEN_Msk

+#define CRYP_DMACR_DOEN_Pos              (1U)

+#define CRYP_DMACR_DOEN_Msk              (0x1UL << CRYP_DMACR_DOEN_Pos)        /*!< 0x00000002 */

+#define CRYP_DMACR_DOEN                  CRYP_DMACR_DOEN_Msk

+/*****************  Bits definition for CRYP_IMSCR register  ******************/

+#define CRYP_IMSCR_INIM_Pos              (0U)

+#define CRYP_IMSCR_INIM_Msk              (0x1UL << CRYP_IMSCR_INIM_Pos)        /*!< 0x00000001 */

+#define CRYP_IMSCR_INIM                  CRYP_IMSCR_INIM_Msk

+#define CRYP_IMSCR_OUTIM_Pos             (1U)

+#define CRYP_IMSCR_OUTIM_Msk             (0x1UL << CRYP_IMSCR_OUTIM_Pos)       /*!< 0x00000002 */

+#define CRYP_IMSCR_OUTIM                 CRYP_IMSCR_OUTIM_Msk

+/****************** Bits definition for CRYP_RISR register  *******************/

+#define CRYP_RISR_INRIS_Pos              (0U)

+#define CRYP_RISR_INRIS_Msk              (0x1UL << CRYP_RISR_INRIS_Pos)        /*!< 0x00000001 */

+#define CRYP_RISR_INRIS                  CRYP_RISR_INRIS_Msk

+#define CRYP_RISR_OUTRIS_Pos             (1U)

+#define CRYP_RISR_OUTRIS_Msk             (0x1UL << CRYP_RISR_OUTRIS_Pos)       /*!< 0x00000002 */

+#define CRYP_RISR_OUTRIS                 CRYP_RISR_OUTRIS_Msk

+/****************** Bits definition for CRYP_MISR register  *******************/

+#define CRYP_MISR_INMIS_Pos              (0U)

+#define CRYP_MISR_INMIS_Msk              (0x1UL << CRYP_MISR_INMIS_Pos)        /*!< 0x00000001 */

+#define CRYP_MISR_INMIS                  CRYP_MISR_INMIS_Msk

+#define CRYP_MISR_OUTMIS_Pos             (1U)

+#define CRYP_MISR_OUTMIS_Msk             (0x1UL << CRYP_MISR_OUTMIS_Pos)       /*!< 0x00000002 */

+#define CRYP_MISR_OUTMIS                 CRYP_MISR_OUTMIS_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                      Digital to Analog Converter                           */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for DAC_CR register  ********************/

+#define DAC_CR_EN1_Pos              (0U)

+#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */

+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */

+#define DAC_CR_TEN1_Pos             (1U)

+#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */

+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */

+

+#define DAC_CR_TSEL1_Pos            (2U)

+#define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */

+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */

+#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000004 */

+#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */

+#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */

+#define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */

+

+

+#define DAC_CR_WAVE1_Pos            (6U)

+#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */

+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */

+#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */

+#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */

+

+#define DAC_CR_MAMP1_Pos            (8U)

+#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */

+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */

+#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */

+#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */

+#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */

+#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */

+

+#define DAC_CR_DMAEN1_Pos           (12U)

+#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */

+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */

+#define DAC_CR_DMAUDRIE1_Pos        (13U)

+#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */

+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/

+#define DAC_CR_CEN1_Pos             (14U)

+#define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */

+#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/

+

+#define DAC_CR_EN2_Pos              (16U)

+#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */

+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */

+#define DAC_CR_TEN2_Pos             (17U)

+#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */

+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */

+

+#define DAC_CR_TSEL2_Pos            (18U)

+#define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */

+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */

+#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00040000 */

+#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */

+#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */

+#define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */

+

+

+#define DAC_CR_WAVE2_Pos            (22U)

+#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */

+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */

+#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */

+#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */

+

+#define DAC_CR_MAMP2_Pos            (24U)

+#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */

+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */

+#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */

+#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */

+#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */

+#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */

+

+#define DAC_CR_DMAEN2_Pos           (28U)

+#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */

+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */

+#define DAC_CR_DMAUDRIE2_Pos        (29U)

+#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */

+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/

+#define DAC_CR_CEN2_Pos             (30U)

+#define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */

+#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/

+

+/*****************  Bit definition for DAC_SWTRIGR register  ******************/

+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)

+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */

+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */

+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)

+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */

+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */

+

+/*****************  Bit definition for DAC_DHR12R1 register  ******************/

+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)

+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12L1 register  ******************/

+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)

+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8R1 register  ******************/

+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)

+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12R2 register  ******************/

+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)

+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12L2 register  ******************/

+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)

+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8R2 register  ******************/

+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)

+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12RD register  ******************/

+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)

+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */

+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)

+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */

+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12LD register  ******************/

+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)

+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */

+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)

+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */

+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8RD register  ******************/

+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)

+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */

+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)

+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */

+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */

+

+/*******************  Bit definition for DAC_DOR1 register  *******************/

+#define DAC_DOR1_DACC1DOR_Pos       (0U)

+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */

+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */

+

+/*******************  Bit definition for DAC_DOR2 register  *******************/

+#define DAC_DOR2_DACC2DOR_Pos       (0U)

+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */

+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */

+

+/********************  Bit definition for DAC_SR register  ********************/

+#define DAC_SR_DMAUDR1_Pos          (13U)

+#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */

+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */

+#define DAC_SR_CAL_FLAG1_Pos        (14U)

+#define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */

+#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */

+#define DAC_SR_BWST1_Pos            (15U)

+#define DAC_SR_BWST1_Msk            (0x4001UL << DAC_SR_BWST1_Pos)             /*!< 0x20008000 */

+#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */

+

+#define DAC_SR_DMAUDR2_Pos          (29U)

+#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */

+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */

+#define DAC_SR_CAL_FLAG2_Pos        (30U)

+#define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */

+#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */

+#define DAC_SR_BWST2_Pos            (31U)

+#define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */

+#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */

+

+/*******************  Bit definition for DAC_CCR register  ********************/

+#define DAC_CCR_OTRIM1_Pos          (0U)

+#define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */

+#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */

+#define DAC_CCR_OTRIM2_Pos          (16U)

+#define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */

+#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */

+

+/*******************  Bit definition for DAC_MCR register  *******************/

+#define DAC_MCR_MODE1_Pos           (0U)

+#define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */

+#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */

+#define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */

+#define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */

+#define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */

+

+#define DAC_MCR_MODE2_Pos           (16U)

+#define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */

+#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */

+#define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */

+#define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */

+#define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */

+

+/******************  Bit definition for DAC_SHSR1 register  ******************/

+#define DAC_SHSR1_TSAMPLE1_Pos      (0U)

+#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */

+#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */

+

+/******************  Bit definition for DAC_SHSR2 register  ******************/

+#define DAC_SHSR2_TSAMPLE2_Pos      (0U)

+#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */

+#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */

+

+/******************  Bit definition for DAC_SHHR register  ******************/

+#define DAC_SHHR_THOLD1_Pos         (0U)

+#define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */

+#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */

+#define DAC_SHHR_THOLD2_Pos         (16U)

+#define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */

+#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */

+

+/******************  Bit definition for DAC_SHRR register  ******************/

+#define DAC_SHRR_TREFRESH1_Pos      (0U)

+#define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */

+#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */

+#define DAC_SHRR_TREFRESH2_Pos      (16U)

+#define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */

+#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    DCMI                                    */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DCMI_CR register  ******************/

+#define DCMI_CR_CAPTURE_Pos        (0U)

+#define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)              /*!< 0x00000001 */

+#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk

+#define DCMI_CR_CM_Pos             (1U)

+#define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                   /*!< 0x00000002 */

+#define DCMI_CR_CM                 DCMI_CR_CM_Msk

+#define DCMI_CR_CROP_Pos           (2U)

+#define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                 /*!< 0x00000004 */

+#define DCMI_CR_CROP               DCMI_CR_CROP_Msk

+#define DCMI_CR_JPEG_Pos           (3U)

+#define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                 /*!< 0x00000008 */

+#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk

+#define DCMI_CR_ESS_Pos            (4U)

+#define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                  /*!< 0x00000010 */

+#define DCMI_CR_ESS                DCMI_CR_ESS_Msk

+#define DCMI_CR_PCKPOL_Pos         (5U)

+#define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)               /*!< 0x00000020 */

+#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk

+#define DCMI_CR_HSPOL_Pos          (6U)

+#define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                /*!< 0x00000040 */

+#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk

+#define DCMI_CR_VSPOL_Pos          (7U)

+#define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */

+#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk

+#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)

+#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)

+#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)

+#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)

+#define DCMI_CR_CRE_Pos            (12U)

+#define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */

+#define DCMI_CR_CRE                DCMI_CR_CRE_Msk

+#define DCMI_CR_ENABLE_Pos         (14U)

+#define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)               /*!< 0x00004000 */

+#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk

+#define DCMI_CR_BSM_Pos            (16U)

+#define DCMI_CR_BSM_Msk            (0x3UL << DCMI_CR_BSM_Pos)                  /*!< 0x00030000 */

+#define DCMI_CR_BSM                DCMI_CR_BSM_Msk

+#define DCMI_CR_BSM_0              (0x1UL << DCMI_CR_BSM_Pos)                   /*!< 0x00010000 */

+#define DCMI_CR_BSM_1              (0x2UL << DCMI_CR_BSM_Pos)                   /*!< 0x00020000 */

+#define DCMI_CR_OEBS_Pos           (18U)

+#define DCMI_CR_OEBS_Msk           (0x1UL << DCMI_CR_OEBS_Pos)                 /*!< 0x00040000 */

+#define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk

+#define DCMI_CR_LSM_Pos            (19U)

+#define DCMI_CR_LSM_Msk            (0x1UL << DCMI_CR_LSM_Pos)                  /*!< 0x00080000 */

+#define DCMI_CR_LSM                DCMI_CR_LSM_Msk

+#define DCMI_CR_OELS_Pos           (20U)

+#define DCMI_CR_OELS_Msk           (0x1UL << DCMI_CR_OELS_Pos)                 /*!< 0x00100000 */

+#define DCMI_CR_OELS               DCMI_CR_OELS_Msk

+

+/********************  Bits definition for DCMI_SR register  ******************/

+#define DCMI_SR_HSYNC_Pos          (0U)

+#define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                /*!< 0x00000001 */

+#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk

+#define DCMI_SR_VSYNC_Pos          (1U)

+#define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                /*!< 0x00000002 */

+#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk

+#define DCMI_SR_FNE_Pos            (2U)

+#define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                  /*!< 0x00000004 */

+#define DCMI_SR_FNE                DCMI_SR_FNE_Msk

+

+/********************  Bits definition for DCMI_RIS register   ****************/

+#define DCMI_RIS_FRAME_RIS_Pos     (0U)

+#define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)           /*!< 0x00000001 */

+#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk

+#define DCMI_RIS_OVR_RIS_Pos       (1U)

+#define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)             /*!< 0x00000002 */

+#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk

+#define DCMI_RIS_ERR_RIS_Pos       (2U)

+#define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)             /*!< 0x00000004 */

+#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk

+#define DCMI_RIS_VSYNC_RIS_Pos     (3U)

+#define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)           /*!< 0x00000008 */

+#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk

+#define DCMI_RIS_LINE_RIS_Pos      (4U)

+#define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)            /*!< 0x00000010 */

+#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk

+

+/********************  Bits definition for DCMI_IER register  *****************/

+#define DCMI_IER_FRAME_IE_Pos      (0U)

+#define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)            /*!< 0x00000001 */

+#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk

+#define DCMI_IER_OVR_IE_Pos        (1U)

+#define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)              /*!< 0x00000002 */

+#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk

+#define DCMI_IER_ERR_IE_Pos        (2U)

+#define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)              /*!< 0x00000004 */

+#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk

+#define DCMI_IER_VSYNC_IE_Pos      (3U)

+#define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)            /*!< 0x00000008 */

+#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk

+#define DCMI_IER_LINE_IE_Pos       (4U)

+#define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)             /*!< 0x00000010 */

+#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk

+

+

+/********************  Bits definition for DCMI_MIS register  *****************/

+#define DCMI_MIS_FRAME_MIS_Pos     (0U)

+#define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)           /*!< 0x00000001 */

+#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk

+#define DCMI_MIS_OVR_MIS_Pos       (1U)

+#define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)             /*!< 0x00000002 */

+#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk

+#define DCMI_MIS_ERR_MIS_Pos       (2U)

+#define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)             /*!< 0x00000004 */

+#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk

+#define DCMI_MIS_VSYNC_MIS_Pos     (3U)

+#define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)           /*!< 0x00000008 */

+#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk

+#define DCMI_MIS_LINE_MIS_Pos      (4U)

+#define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)            /*!< 0x00000010 */

+#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk

+

+

+/********************  Bits definition for DCMI_ICR register  *****************/

+#define DCMI_ICR_FRAME_ISC_Pos     (0U)

+#define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)           /*!< 0x00000001 */

+#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk

+#define DCMI_ICR_OVR_ISC_Pos       (1U)

+#define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)             /*!< 0x00000002 */

+#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk

+#define DCMI_ICR_ERR_ISC_Pos       (2U)

+#define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)             /*!< 0x00000004 */

+#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk

+#define DCMI_ICR_VSYNC_ISC_Pos     (3U)

+#define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)           /*!< 0x00000008 */

+#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk

+#define DCMI_ICR_LINE_ISC_Pos      (4U)

+#define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)            /*!< 0x00000010 */

+#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk

+

+

+/********************  Bits definition for DCMI_ESCR register  ******************/

+#define DCMI_ESCR_FSC_Pos          (0U)

+#define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)               /*!< 0x000000FF */

+#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk

+#define DCMI_ESCR_LSC_Pos          (8U)

+#define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)               /*!< 0x0000FF00 */

+#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk

+#define DCMI_ESCR_LEC_Pos          (16U)

+#define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)               /*!< 0x00FF0000 */

+#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk

+#define DCMI_ESCR_FEC_Pos          (24U)

+#define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)               /*!< 0xFF000000 */

+#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk

+

+/********************  Bits definition for DCMI_ESUR register  ******************/

+#define DCMI_ESUR_FSU_Pos          (0U)

+#define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)               /*!< 0x000000FF */

+#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk

+#define DCMI_ESUR_LSU_Pos          (8U)

+#define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)               /*!< 0x0000FF00 */

+#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk

+#define DCMI_ESUR_LEU_Pos          (16U)

+#define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)               /*!< 0x00FF0000 */

+#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk

+#define DCMI_ESUR_FEU_Pos          (24U)

+#define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)               /*!< 0xFF000000 */

+#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk

+

+/********************  Bits definition for DCMI_CWSTRT register  ******************/

+#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)

+#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)       /*!< 0x00003FFF */

+#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk

+#define DCMI_CWSTRT_VST_Pos        (16U)

+#define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)           /*!< 0x1FFF0000 */

+#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk

+

+/********************  Bits definition for DCMI_CWSIZE register  ******************/

+#define DCMI_CWSIZE_CAPCNT_Pos     (0U)

+#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)        /*!< 0x00003FFF */

+#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk

+#define DCMI_CWSIZE_VLINE_Pos      (16U)

+#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)         /*!< 0x3FFF0000 */

+#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk

+

+/********************  Bits definition for DCMI_DR register  ******************/

+#define DCMI_DR_BYTE0_Pos          (0U)

+#define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)               /*!< 0x000000FF */

+#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk

+#define DCMI_DR_BYTE1_Pos          (8U)

+#define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)               /*!< 0x0000FF00 */

+#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk

+#define DCMI_DR_BYTE2_Pos          (16U)

+#define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)               /*!< 0x00FF0000 */

+#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk

+#define DCMI_DR_BYTE3_Pos          (24U)

+#define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)               /*!< 0xFF000000 */

+#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                 Digital Filter for Sigma Delta Modulators                  */

+/*                                                                            */

+/******************************************************************************/

+

+/****************   DFSDM channel configuration registers  ********************/

+

+/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/

+#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)

+#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)   /*!< 0x80000000 */

+#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */

+#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)

+#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)  /*!< 0x40000000 */

+#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */

+#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)

+#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */

+#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */

+#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)

+#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x0000C000 */

+#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */

+#define DFSDM_CHCFGR1_DATPACK_1         (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */

+#define DFSDM_CHCFGR1_DATPACK_0         (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */

+#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)

+#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00003000 */

+#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */

+#define DFSDM_CHCFGR1_DATMPX_1          (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */

+#define DFSDM_CHCFGR1_DATMPX_0          (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */

+#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)

+#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)   /*!< 0x00000100 */

+#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */

+#define DFSDM_CHCFGR1_CHEN_Pos          (7U)

+#define DFSDM_CHCFGR1_CHEN_Msk          (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)      /*!< 0x00000080 */

+#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */

+#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)

+#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)    /*!< 0x00000040 */

+#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */

+#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)

+#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)     /*!< 0x00000020 */

+#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */

+#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)

+#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x0000000C */

+#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */

+#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */

+#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */

+#define DFSDM_CHCFGR1_SITP_Pos          (0U)

+#define DFSDM_CHCFGR1_SITP_Msk          (0x3UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000003 */

+#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */

+#define DFSDM_CHCFGR1_SITP_1            (0x2UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */

+#define DFSDM_CHCFGR1_SITP_0            (0x1UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */

+

+/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/

+#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)

+#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */

+#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)

+#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)    /*!< 0x000000F8 */

+#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */

+

+/******************  Bit definition for DFSDM_CHAWSCDR register *****************/

+#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)

+#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00C00000 */

+#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */

+#define DFSDM_CHAWSCDR_AWFORD_1         (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */

+#define DFSDM_CHAWSCDR_AWFORD_0         (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */

+#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)

+#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)  /*!< 0x001F0000 */

+#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */

+#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)

+#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)    /*!< 0x0000F000 */

+#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */

+#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)

+#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)    /*!< 0x000000FF */

+#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */

+

+/****************  Bit definition for DFSDM_CHWDATR register *******************/

+#define DFSDM_CHWDATR_WDATA_Pos         (0U)

+#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)  /*!< 0x0000FFFF */

+#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */

+

+/****************  Bit definition for DFSDM_CHDATINR register *****************/

+#define DFSDM_CHDATINR_INDAT0_Pos       (0U)

+#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */

+#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */

+#define DFSDM_CHDATINR_INDAT1_Pos       (16U)

+#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */

+#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */

+

+/****************  Bit definition for DFSDM_CHDLYR register *****************/

+#define DFSDM_CHDLYR_PLSSKP_Pos         (0U)

+#define DFSDM_CHDLYR_PLSSKP_Msk         (0x3FUL << DFSDM_CHDLYR_PLSSKP_Pos)    /*!< 0x0000003F*/

+#define DFSDM_CHDLYR_PLSSKP             DFSDM_CHDLYR_PLSSKP_Msk

+/************************   DFSDM module registers  ****************************/

+

+/********************  Bit definition for DFSDM_FLTCR1 register *******************/

+#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)

+#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)     /*!< 0x40000000 */

+#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */

+#define DFSDM_FLTCR1_FAST_Pos           (29U)

+#define DFSDM_FLTCR1_FAST_Msk           (0x1UL << DFSDM_FLTCR1_FAST_Pos)       /*!< 0x20000000 */

+#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */

+#define DFSDM_FLTCR1_RCH_Pos            (24U)

+#define DFSDM_FLTCR1_RCH_Msk            (0x7UL << DFSDM_FLTCR1_RCH_Pos)        /*!< 0x07000000 */

+#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */

+#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)

+#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)     /*!< 0x00200000 */

+#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */

+#define DFSDM_FLTCR1_RSYNC_Pos          (19U)

+#define DFSDM_FLTCR1_RSYNC_Msk          (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)      /*!< 0x00080000 */

+#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */

+#define DFSDM_FLTCR1_RCONT_Pos          (18U)

+#define DFSDM_FLTCR1_RCONT_Msk          (0x1UL << DFSDM_FLTCR1_RCONT_Pos)      /*!< 0x00040000 */

+#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */

+#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)

+#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)   /*!< 0x00020000 */

+#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */

+#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)

+#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00006000 */

+#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */

+#define DFSDM_FLTCR1_JEXTEN_1           (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */

+#define DFSDM_FLTCR1_JEXTEN_0           (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */

+#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)

+#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)   /*!< 0x00001F00 */

+#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */

+#define DFSDM_FLTCR1_JEXTSEL_0          (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000100 */

+#define DFSDM_FLTCR1_JEXTSEL_1          (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000200 */

+#define DFSDM_FLTCR1_JEXTSEL_2          (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000400 */

+#define DFSDM_FLTCR1_JEXTSEL_3          (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000800 */

+#define DFSDM_FLTCR1_JEXTSEL_4          (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00001000 */

+

+#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)

+#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)     /*!< 0x00000020 */

+#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */

+#define DFSDM_FLTCR1_JSCAN_Pos          (4U)

+#define DFSDM_FLTCR1_JSCAN_Msk          (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)      /*!< 0x00000010 */

+#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */

+#define DFSDM_FLTCR1_JSYNC_Pos          (3U)

+#define DFSDM_FLTCR1_JSYNC_Msk          (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)      /*!< 0x00000008 */

+#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */

+#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)

+#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)   /*!< 0x00000002 */

+#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */

+#define DFSDM_FLTCR1_DFEN_Pos           (0U)

+#define DFSDM_FLTCR1_DFEN_Msk           (0x1UL << DFSDM_FLTCR1_DFEN_Pos)       /*!< 0x00000001 */

+#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */

+

+/********************  Bit definition for DFSDM_FLTCR2 register *******************/

+#define DFSDM_FLTCR2_AWDCH_Pos          (16U)

+#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)     /*!< 0x00FF0000 */

+#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */

+#define DFSDM_FLTCR2_EXCH_Pos           (8U)

+#define DFSDM_FLTCR2_EXCH_Msk           (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)      /*!< 0x0000FF00 */

+#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */

+#define DFSDM_FLTCR2_CKABIE_Pos         (6U)

+#define DFSDM_FLTCR2_CKABIE_Msk         (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)     /*!< 0x00000040 */

+#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */

+#define DFSDM_FLTCR2_SCDIE_Pos          (5U)

+#define DFSDM_FLTCR2_SCDIE_Msk          (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)      /*!< 0x00000020 */

+#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */

+#define DFSDM_FLTCR2_AWDIE_Pos          (4U)

+#define DFSDM_FLTCR2_AWDIE_Msk          (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)      /*!< 0x00000010 */

+#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */

+#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)

+#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)     /*!< 0x00000008 */

+#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */

+#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)

+#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)     /*!< 0x00000004 */

+#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */

+#define DFSDM_FLTCR2_REOCIE_Pos         (1U)

+#define DFSDM_FLTCR2_REOCIE_Msk         (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)     /*!< 0x00000002 */

+#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */

+#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)

+#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)     /*!< 0x00000001 */

+#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */

+

+/********************  Bit definition for DFSDM_FLTISR register *******************/

+#define DFSDM_FLTISR_SCDF_Pos           (24U)

+#define DFSDM_FLTISR_SCDF_Msk           (0xFFUL << DFSDM_FLTISR_SCDF_Pos)      /*!< 0xFF000000 */

+#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */

+#define DFSDM_FLTISR_CKABF_Pos          (16U)

+#define DFSDM_FLTISR_CKABF_Msk          (0xFFUL << DFSDM_FLTISR_CKABF_Pos)     /*!< 0x00FF0000 */

+#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */

+#define DFSDM_FLTISR_RCIP_Pos           (14U)

+#define DFSDM_FLTISR_RCIP_Msk           (0x1UL << DFSDM_FLTISR_RCIP_Pos)       /*!< 0x00004000 */

+#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */

+#define DFSDM_FLTISR_JCIP_Pos           (13U)

+#define DFSDM_FLTISR_JCIP_Msk           (0x1UL << DFSDM_FLTISR_JCIP_Pos)       /*!< 0x00002000 */

+#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */

+#define DFSDM_FLTISR_AWDF_Pos           (4U)

+#define DFSDM_FLTISR_AWDF_Msk           (0x1UL << DFSDM_FLTISR_AWDF_Pos)       /*!< 0x00000010 */

+#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */

+#define DFSDM_FLTISR_ROVRF_Pos          (3U)

+#define DFSDM_FLTISR_ROVRF_Msk          (0x1UL << DFSDM_FLTISR_ROVRF_Pos)      /*!< 0x00000008 */

+#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */

+#define DFSDM_FLTISR_JOVRF_Pos          (2U)

+#define DFSDM_FLTISR_JOVRF_Msk          (0x1UL << DFSDM_FLTISR_JOVRF_Pos)      /*!< 0x00000004 */

+#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */

+#define DFSDM_FLTISR_REOCF_Pos          (1U)

+#define DFSDM_FLTISR_REOCF_Msk          (0x1UL << DFSDM_FLTISR_REOCF_Pos)      /*!< 0x00000002 */

+#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */

+#define DFSDM_FLTISR_JEOCF_Pos          (0U)

+#define DFSDM_FLTISR_JEOCF_Msk          (0x1UL << DFSDM_FLTISR_JEOCF_Pos)      /*!< 0x00000001 */

+#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */

+

+/********************  Bit definition for DFSDM_FLTICR register *******************/

+#define DFSDM_FLTICR_CLRSCDF_Pos        (24U)

+#define DFSDM_FLTICR_CLRSCDF_Msk        (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)   /*!< 0xFF000000 */

+#define DFSDM_FLTICR_CLRSCDF            DFSDM_FLTICR_CLRSCDF_Msk               /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */

+#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)

+#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)  /*!< 0x00FF0000 */

+#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */

+#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)

+#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)   /*!< 0x00000008 */

+#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */

+#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)

+#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)   /*!< 0x00000004 */

+#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */

+

+/*******************  Bit definition for DFSDM_FLTJCHGR register ******************/

+#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)

+#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)    /*!< 0x000000FF */

+#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */

+

+/********************  Bit definition for DFSDM_FLTFCR register *******************/

+#define DFSDM_FLTFCR_FORD_Pos           (29U)

+#define DFSDM_FLTFCR_FORD_Msk           (0x7UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0xE0000000 */

+#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */

+#define DFSDM_FLTFCR_FORD_2             (0x4UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */

+#define DFSDM_FLTFCR_FORD_1             (0x2UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */

+#define DFSDM_FLTFCR_FORD_0             (0x1UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */

+#define DFSDM_FLTFCR_FOSR_Pos           (16U)

+#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)     /*!< 0x03FF0000 */

+#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */

+#define DFSDM_FLTFCR_IOSR_Pos           (0U)

+#define DFSDM_FLTFCR_IOSR_Msk           (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)      /*!< 0x000000FF */

+#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */

+

+/******************  Bit definition for DFSDM_FLTJDATAR register *****************/

+#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)

+#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */

+#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)

+#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */

+#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */

+

+/******************  Bit definition for DFSDM_FLTRDATAR register *****************/

+#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)

+#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */

+#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)

+#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)   /*!< 0x00000010 */

+#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */

+#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)

+#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */

+#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */

+

+/******************  Bit definition for DFSDM_FLTAWHTR register ******************/

+#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)

+#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */

+#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)

+#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)    /*!< 0x0000000F */

+#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */

+

+/******************  Bit definition for DFSDM_FLTAWLTR register ******************/

+#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)

+#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWHT[23:0] Analog watchdog low threshold */

+#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)

+#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)    /*!< 0x0000000F */

+#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */

+

+/******************  Bit definition for DFSDM_FLTAWSR register ******************/

+#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)

+#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)    /*!< 0x0000FF00 */

+#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */

+#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)

+#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)    /*!< 0x000000FF */

+#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */

+

+/******************  Bit definition for DFSDM_FLTAWCFR) register *****************/

+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)

+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */

+#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */

+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)

+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */

+#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */

+

+/******************  Bit definition for DFSDM_FLTEXMAX register ******************/

+#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)

+#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */

+#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)

+#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)  /*!< 0x00000007 */

+#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */

+

+/******************  Bit definition for DFSDM_FLTEXMIN register ******************/

+#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)

+#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */

+#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)

+#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)  /*!< 0x00000007 */

+#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */

+

+/******************  Bit definition for DFSDM_FLTCNVTIMR register ******************/

+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)

+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */

+#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           BDMA Controller                                  */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for BDMA_ISR register  ********************/

+#define BDMA_ISR_GIF0_Pos       (0U)

+#define BDMA_ISR_GIF0_Msk       (0x1UL << BDMA_ISR_GIF0_Pos)                   /*!< 0x00000001 */

+#define BDMA_ISR_GIF0           BDMA_ISR_GIF0_Msk                              /*!< Channel 0 Global interrupt flag */

+#define BDMA_ISR_TCIF0_Pos      (1U)

+#define BDMA_ISR_TCIF0_Msk      (0x1UL << BDMA_ISR_TCIF0_Pos)                  /*!< 0x00000002 */

+#define BDMA_ISR_TCIF0          BDMA_ISR_TCIF0_Msk                             /*!< Channel 0 Transfer Complete flag */

+#define BDMA_ISR_HTIF0_Pos      (2U)

+#define BDMA_ISR_HTIF0_Msk      (0x1UL << BDMA_ISR_HTIF0_Pos)                  /*!< 0x00000004 */

+#define BDMA_ISR_HTIF0          BDMA_ISR_HTIF0_Msk                             /*!< Channel 0 Half Transfer flag */

+#define BDMA_ISR_TEIF0_Pos      (3U)

+#define BDMA_ISR_TEIF0_Msk      (0x1UL << BDMA_ISR_TEIF0_Pos)                  /*!< 0x00000008 */

+#define BDMA_ISR_TEIF0          BDMA_ISR_TEIF0_Msk                             /*!< Channel 0 Transfer Error flag */

+#define BDMA_ISR_GIF1_Pos       (4U)

+#define BDMA_ISR_GIF1_Msk       (0x1UL << BDMA_ISR_GIF1_Pos)                   /*!< 0x00000010 */

+#define BDMA_ISR_GIF1           BDMA_ISR_GIF1_Msk                              /*!< Channel 1 Global interrupt flag */

+#define BDMA_ISR_TCIF1_Pos      (5U)

+#define BDMA_ISR_TCIF1_Msk      (0x1UL << BDMA_ISR_TCIF1_Pos)                  /*!< 0x00000020 */

+#define BDMA_ISR_TCIF1          BDMA_ISR_TCIF1_Msk                             /*!< Channel 1 Transfer Complete flag */

+#define BDMA_ISR_HTIF1_Pos      (6U)

+#define BDMA_ISR_HTIF1_Msk      (0x1UL << BDMA_ISR_HTIF1_Pos)                  /*!< 0x00000040 */

+#define BDMA_ISR_HTIF1          BDMA_ISR_HTIF1_Msk                             /*!< Channel 1 Half Transfer flag */

+#define BDMA_ISR_TEIF1_Pos      (7U)

+#define BDMA_ISR_TEIF1_Msk      (0x1UL << BDMA_ISR_TEIF1_Pos)                  /*!< 0x00000080 */

+#define BDMA_ISR_TEIF1          BDMA_ISR_TEIF1_Msk                             /*!< Channel 1 Transfer Error flag */

+#define BDMA_ISR_GIF2_Pos       (8U)

+#define BDMA_ISR_GIF2_Msk       (0x1UL << BDMA_ISR_GIF2_Pos)                   /*!< 0x00000100 */

+#define BDMA_ISR_GIF2           BDMA_ISR_GIF2_Msk                              /*!< Channel 2 Global interrupt flag */

+#define BDMA_ISR_TCIF2_Pos      (9U)

+#define BDMA_ISR_TCIF2_Msk      (0x1UL << BDMA_ISR_TCIF2_Pos)                  /*!< 0x00000200 */

+#define BDMA_ISR_TCIF2          BDMA_ISR_TCIF2_Msk                             /*!< Channel 2 Transfer Complete flag */

+#define BDMA_ISR_HTIF2_Pos      (10U)

+#define BDMA_ISR_HTIF2_Msk      (0x1UL << BDMA_ISR_HTIF2_Pos)                  /*!< 0x00000400 */

+#define BDMA_ISR_HTIF2          BDMA_ISR_HTIF2_Msk                             /*!< Channel 2 Half Transfer flag */

+#define BDMA_ISR_TEIF2_Pos      (11U)

+#define BDMA_ISR_TEIF2_Msk      (0x1UL << BDMA_ISR_TEIF2_Pos)                  /*!< 0x00000800 */

+#define BDMA_ISR_TEIF2          BDMA_ISR_TEIF2_Msk                             /*!< Channel 2 Transfer Error flag */

+#define BDMA_ISR_GIF3_Pos       (12U)

+#define BDMA_ISR_GIF3_Msk       (0x1UL << BDMA_ISR_GIF3_Pos)                   /*!< 0x00001000 */

+#define BDMA_ISR_GIF3           BDMA_ISR_GIF3_Msk                              /*!< Channel 3 Global interrupt flag */

+#define BDMA_ISR_TCIF3_Pos      (13U)

+#define BDMA_ISR_TCIF3_Msk      (0x1UL << BDMA_ISR_TCIF3_Pos)                  /*!< 0x00002000 */

+#define BDMA_ISR_TCIF3          BDMA_ISR_TCIF3_Msk                             /*!< Channel 3 Transfer Complete flag */

+#define BDMA_ISR_HTIF3_Pos      (14U)

+#define BDMA_ISR_HTIF3_Msk      (0x1UL << BDMA_ISR_HTIF3_Pos)                  /*!< 0x00004000 */

+#define BDMA_ISR_HTIF3          BDMA_ISR_HTIF3_Msk                             /*!< Channel 3 Half Transfer flag */

+#define BDMA_ISR_TEIF3_Pos      (15U)

+#define BDMA_ISR_TEIF3_Msk      (0x1UL << BDMA_ISR_TEIF3_Pos)                  /*!< 0x00008000 */

+#define BDMA_ISR_TEIF3          BDMA_ISR_TEIF3_Msk                             /*!< Channel 3 Transfer Error flag */

+#define BDMA_ISR_GIF4_Pos       (16U)

+#define BDMA_ISR_GIF4_Msk       (0x1UL << BDMA_ISR_GIF4_Pos)                   /*!< 0x00010000 */

+#define BDMA_ISR_GIF4           BDMA_ISR_GIF4_Msk                              /*!< Channel 4 Global interrupt flag */

+#define BDMA_ISR_TCIF4_Pos      (17U)

+#define BDMA_ISR_TCIF4_Msk      (0x1UL << BDMA_ISR_TCIF4_Pos)                  /*!< 0x00020000 */

+#define BDMA_ISR_TCIF4          BDMA_ISR_TCIF4_Msk                             /*!< Channel 4 Transfer Complete flag */

+#define BDMA_ISR_HTIF4_Pos      (18U)

+#define BDMA_ISR_HTIF4_Msk      (0x1UL << BDMA_ISR_HTIF4_Pos)                  /*!< 0x00040000 */

+#define BDMA_ISR_HTIF4          BDMA_ISR_HTIF4_Msk                             /*!< Channel 4 Half Transfer flag */

+#define BDMA_ISR_TEIF4_Pos      (19U)

+#define BDMA_ISR_TEIF4_Msk      (0x1UL << BDMA_ISR_TEIF4_Pos)                  /*!< 0x00080000 */

+#define BDMA_ISR_TEIF4          BDMA_ISR_TEIF4_Msk                             /*!< Channel 4 Transfer Error flag */

+#define BDMA_ISR_GIF5_Pos       (20U)

+#define BDMA_ISR_GIF5_Msk       (0x1UL << BDMA_ISR_GIF5_Pos)                   /*!< 0x00100000 */

+#define BDMA_ISR_GIF5           BDMA_ISR_GIF5_Msk                              /*!< Channel 5 Global interrupt flag */

+#define BDMA_ISR_TCIF5_Pos      (21U)

+#define BDMA_ISR_TCIF5_Msk      (0x1UL << BDMA_ISR_TCIF5_Pos)                  /*!< 0x00200000 */

+#define BDMA_ISR_TCIF5          BDMA_ISR_TCIF5_Msk                             /*!< Channel 5 Transfer Complete flag */

+#define BDMA_ISR_HTIF5_Pos      (22U)

+#define BDMA_ISR_HTIF5_Msk      (0x1UL << BDMA_ISR_HTIF5_Pos)                  /*!< 0x00400000 */

+#define BDMA_ISR_HTIF5          BDMA_ISR_HTIF5_Msk                             /*!< Channel 5 Half Transfer flag */

+#define BDMA_ISR_TEIF5_Pos      (23U)

+#define BDMA_ISR_TEIF5_Msk      (0x1UL << BDMA_ISR_TEIF5_Pos)                  /*!< 0x00800000 */

+#define BDMA_ISR_TEIF5          BDMA_ISR_TEIF5_Msk                             /*!< Channel 5 Transfer Error flag */

+#define BDMA_ISR_GIF6_Pos       (24U)

+#define BDMA_ISR_GIF6_Msk       (0x1UL << BDMA_ISR_GIF6_Pos)                   /*!< 0x01000000 */

+#define BDMA_ISR_GIF6           BDMA_ISR_GIF6_Msk                              /*!< Channel 6 Global interrupt flag */

+#define BDMA_ISR_TCIF6_Pos      (25U)

+#define BDMA_ISR_TCIF6_Msk      (0x1UL << BDMA_ISR_TCIF6_Pos)                  /*!< 0x02000000 */

+#define BDMA_ISR_TCIF6          BDMA_ISR_TCIF6_Msk                             /*!< Channel 6 Transfer Complete flag */

+#define BDMA_ISR_HTIF6_Pos      (26U)

+#define BDMA_ISR_HTIF6_Msk      (0x1UL << BDMA_ISR_HTIF6_Pos)                  /*!< 0x04000000 */

+#define BDMA_ISR_HTIF6          BDMA_ISR_HTIF6_Msk                             /*!< Channel 6 Half Transfer flag */

+#define BDMA_ISR_TEIF6_Pos      (27U)

+#define BDMA_ISR_TEIF6_Msk      (0x1UL << BDMA_ISR_TEIF6_Pos)                  /*!< 0x08000000 */

+#define BDMA_ISR_TEIF6          BDMA_ISR_TEIF6_Msk                             /*!< Channel 6 Transfer Error flag */

+#define BDMA_ISR_GIF7_Pos       (28U)

+#define BDMA_ISR_GIF7_Msk       (0x1UL << BDMA_ISR_GIF7_Pos)                   /*!< 0x10000000 */

+#define BDMA_ISR_GIF7           BDMA_ISR_GIF7_Msk                              /*!< Channel 7 Global interrupt flag */

+#define BDMA_ISR_TCIF7_Pos      (29U)

+#define BDMA_ISR_TCIF7_Msk      (0x1UL << BDMA_ISR_TCIF7_Pos)                  /*!< 0x20000000 */

+#define BDMA_ISR_TCIF7          BDMA_ISR_TCIF7_Msk                             /*!< Channel 7 Transfer Complete flag */

+#define BDMA_ISR_HTIF7_Pos      (30U)

+#define BDMA_ISR_HTIF7_Msk      (0x1UL << BDMA_ISR_HTIF7_Pos)                  /*!< 0x40000000 */

+#define BDMA_ISR_HTIF7          BDMA_ISR_HTIF7_Msk                             /*!< Channel 7 Half Transfer flag */

+#define BDMA_ISR_TEIF7_Pos      (31U)

+#define BDMA_ISR_TEIF7_Msk      (0x1UL << BDMA_ISR_TEIF7_Pos)                  /*!< 0x80000000 */

+#define BDMA_ISR_TEIF7          BDMA_ISR_TEIF7_Msk                             /*!< Channel 7 Transfer Error flag */

+

+/*******************  Bit definition for BDMA_IFCR register  *******************/

+#define BDMA_IFCR_CGIF0_Pos     (0U)

+#define BDMA_IFCR_CGIF0_Msk     (0x1UL << BDMA_IFCR_CGIF0_Pos)                 /*!< 0x00000001 */

+#define BDMA_IFCR_CGIF0         BDMA_IFCR_CGIF0_Msk                            /*!< Channel 0 Global interrupt clearr */

+#define BDMA_IFCR_CTCIF0_Pos    (1U)

+#define BDMA_IFCR_CTCIF0_Msk    (0x1UL << BDMA_IFCR_CTCIF0_Pos)                /*!< 0x00000002 */

+#define BDMA_IFCR_CTCIF0        BDMA_IFCR_CTCIF0_Msk                           /*!< Channel 0 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF0_Pos    (2U)

+#define BDMA_IFCR_CHTIF0_Msk    (0x1UL << BDMA_IFCR_CHTIF0_Pos)                /*!< 0x00000004 */

+#define BDMA_IFCR_CHTIF0        BDMA_IFCR_CHTIF0_Msk                           /*!< Channel 0 Half Transfer clear */

+#define BDMA_IFCR_CTEIF0_Pos    (3U)

+#define BDMA_IFCR_CTEIF0_Msk    (0x1UL << BDMA_IFCR_CTEIF0_Pos)                /*!< 0x00000008 */

+#define BDMA_IFCR_CTEIF0        BDMA_IFCR_CTEIF0_Msk                           /*!< Channel 0 Transfer Error clear */

+#define BDMA_IFCR_CGIF1_Pos     (4U)

+#define BDMA_IFCR_CGIF1_Msk     (0x1UL << BDMA_IFCR_CGIF1_Pos)                 /*!< 0x00000010 */

+#define BDMA_IFCR_CGIF1         BDMA_IFCR_CGIF1_Msk                            /*!< Channel 1 Global interrupt clear */

+#define BDMA_IFCR_CTCIF1_Pos    (5U)

+#define BDMA_IFCR_CTCIF1_Msk    (0x1UL << BDMA_IFCR_CTCIF1_Pos)                /*!< 0x00000020 */

+#define BDMA_IFCR_CTCIF1        BDMA_IFCR_CTCIF1_Msk                           /*!< Channel 1 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF1_Pos    (6U)

+#define BDMA_IFCR_CHTIF1_Msk    (0x1UL << BDMA_IFCR_CHTIF1_Pos)                /*!< 0x00000040 */

+#define BDMA_IFCR_CHTIF1        BDMA_IFCR_CHTIF1_Msk                           /*!< Channel 1 Half Transfer clear */

+#define BDMA_IFCR_CTEIF1_Pos    (7U)

+#define BDMA_IFCR_CTEIF1_Msk    (0x1UL << BDMA_IFCR_CTEIF1_Pos)                /*!< 0x00000080 */

+#define BDMA_IFCR_CTEIF1        BDMA_IFCR_CTEIF1_Msk                           /*!< Channel 1 Transfer Error clear */

+#define BDMA_IFCR_CGIF2_Pos     (8U)

+#define BDMA_IFCR_CGIF2_Msk     (0x1UL << BDMA_IFCR_CGIF2_Pos)                 /*!< 0x00000100 */

+#define BDMA_IFCR_CGIF2         BDMA_IFCR_CGIF2_Msk                            /*!< Channel 2 Global interrupt clear */

+#define BDMA_IFCR_CTCIF2_Pos    (9U)

+#define BDMA_IFCR_CTCIF2_Msk    (0x1UL << BDMA_IFCR_CTCIF2_Pos)                /*!< 0x00000200 */

+#define BDMA_IFCR_CTCIF2        BDMA_IFCR_CTCIF2_Msk                           /*!< Channel 2 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF2_Pos    (10U)

+#define BDMA_IFCR_CHTIF2_Msk    (0x1UL << BDMA_IFCR_CHTIF2_Pos)                /*!< 0x00000400 */

+#define BDMA_IFCR_CHTIF2        BDMA_IFCR_CHTIF2_Msk                           /*!< Channel 2 Half Transfer clear */

+#define BDMA_IFCR_CTEIF2_Pos    (11U)

+#define BDMA_IFCR_CTEIF2_Msk    (0x1UL << BDMA_IFCR_CTEIF2_Pos)                /*!< 0x00000800 */

+#define BDMA_IFCR_CTEIF2        BDMA_IFCR_CTEIF2_Msk                           /*!< Channel 2 Transfer Error clear */

+#define BDMA_IFCR_CGIF3_Pos     (12U)

+#define BDMA_IFCR_CGIF3_Msk     (0x1UL << BDMA_IFCR_CGIF3_Pos)                 /*!< 0x00001000 */

+#define BDMA_IFCR_CGIF3         BDMA_IFCR_CGIF3_Msk                            /*!< Channel 3 Global interrupt clear */

+#define BDMA_IFCR_CTCIF3_Pos    (13U)

+#define BDMA_IFCR_CTCIF3_Msk    (0x1UL << BDMA_IFCR_CTCIF3_Pos)                /*!< 0x00002000 */

+#define BDMA_IFCR_CTCIF3        BDMA_IFCR_CTCIF3_Msk                           /*!< Channel 3 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF3_Pos    (14U)

+#define BDMA_IFCR_CHTIF3_Msk    (0x1UL << BDMA_IFCR_CHTIF3_Pos)                /*!< 0x00004000 */

+#define BDMA_IFCR_CHTIF3        BDMA_IFCR_CHTIF3_Msk                           /*!< Channel 3 Half Transfer clear */

+#define BDMA_IFCR_CTEIF3_Pos    (15U)

+#define BDMA_IFCR_CTEIF3_Msk    (0x1UL << BDMA_IFCR_CTEIF3_Pos)                /*!< 0x00008000 */

+#define BDMA_IFCR_CTEIF3        BDMA_IFCR_CTEIF3_Msk                           /*!< Channel 3 Transfer Error clear */

+#define BDMA_IFCR_CGIF4_Pos     (16U)

+#define BDMA_IFCR_CGIF4_Msk     (0x1UL << BDMA_IFCR_CGIF4_Pos)                 /*!< 0x00010000 */

+#define BDMA_IFCR_CGIF4         BDMA_IFCR_CGIF4_Msk                            /*!< Channel 4 Global interrupt clear */

+#define BDMA_IFCR_CTCIF4_Pos    (17U)

+#define BDMA_IFCR_CTCIF4_Msk    (0x1UL << BDMA_IFCR_CTCIF4_Pos)                /*!< 0x00020000 */

+#define BDMA_IFCR_CTCIF4        BDMA_IFCR_CTCIF4_Msk                           /*!< Channel 4 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF4_Pos    (18U)

+#define BDMA_IFCR_CHTIF4_Msk    (0x1UL << BDMA_IFCR_CHTIF4_Pos)                /*!< 0x00040000 */

+#define BDMA_IFCR_CHTIF4        BDMA_IFCR_CHTIF4_Msk                           /*!< Channel 4 Half Transfer clear */

+#define BDMA_IFCR_CTEIF4_Pos    (19U)

+#define BDMA_IFCR_CTEIF4_Msk    (0x1UL << BDMA_IFCR_CTEIF4_Pos)                /*!< 0x00080000 */

+#define BDMA_IFCR_CTEIF4        BDMA_IFCR_CTEIF4_Msk                           /*!< Channel 4 Transfer Error clear */

+#define BDMA_IFCR_CGIF5_Pos     (20U)

+#define BDMA_IFCR_CGIF5_Msk     (0x1UL << BDMA_IFCR_CGIF5_Pos)                 /*!< 0x00100000 */

+#define BDMA_IFCR_CGIF5         BDMA_IFCR_CGIF5_Msk                            /*!< Channel 5 Global interrupt clear */

+#define BDMA_IFCR_CTCIF5_Pos    (21U)

+#define BDMA_IFCR_CTCIF5_Msk    (0x1UL << BDMA_IFCR_CTCIF5_Pos)                /*!< 0x00200000 */

+#define BDMA_IFCR_CTCIF5        BDMA_IFCR_CTCIF5_Msk                           /*!< Channel 5 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF5_Pos    (22U)

+#define BDMA_IFCR_CHTIF5_Msk    (0x1UL << BDMA_IFCR_CHTIF5_Pos)                /*!< 0x00400000 */

+#define BDMA_IFCR_CHTIF5        BDMA_IFCR_CHTIF5_Msk                           /*!< Channel 5 Half Transfer clear */

+#define BDMA_IFCR_CTEIF5_Pos    (23U)

+#define BDMA_IFCR_CTEIF5_Msk    (0x1UL << BDMA_IFCR_CTEIF5_Pos)                /*!< 0x00800000 */

+#define BDMA_IFCR_CTEIF5        BDMA_IFCR_CTEIF5_Msk                           /*!< Channel 5 Transfer Error clear */

+#define BDMA_IFCR_CGIF6_Pos     (24U)

+#define BDMA_IFCR_CGIF6_Msk     (0x1UL << BDMA_IFCR_CGIF6_Pos)                 /*!< 0x01000000 */

+#define BDMA_IFCR_CGIF6         BDMA_IFCR_CGIF6_Msk                            /*!< Channel 6 Global interrupt clear */

+#define BDMA_IFCR_CTCIF6_Pos    (25U)

+#define BDMA_IFCR_CTCIF6_Msk    (0x1UL << BDMA_IFCR_CTCIF6_Pos)                /*!< 0x02000000 */

+#define BDMA_IFCR_CTCIF6        BDMA_IFCR_CTCIF6_Msk                           /*!< Channel 6 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF6_Pos    (26U)

+#define BDMA_IFCR_CHTIF6_Msk    (0x1UL << BDMA_IFCR_CHTIF6_Pos)                /*!< 0x04000000 */

+#define BDMA_IFCR_CHTIF6        BDMA_IFCR_CHTIF6_Msk                           /*!< Channel 6 Half Transfer clear */

+#define BDMA_IFCR_CTEIF6_Pos    (27U)

+#define BDMA_IFCR_CTEIF6_Msk    (0x1UL << BDMA_IFCR_CTEIF6_Pos)                /*!< 0x08000000 */

+#define BDMA_IFCR_CTEIF6        BDMA_IFCR_CTEIF6_Msk                           /*!< Channel 6 Transfer Error clear */

+#define BDMA_IFCR_CGIF7_Pos     (28U)

+#define BDMA_IFCR_CGIF7_Msk     (0x1UL << BDMA_IFCR_CGIF7_Pos)                 /*!< 0x10000000 */

+#define BDMA_IFCR_CGIF7         BDMA_IFCR_CGIF7_Msk                            /*!< Channel 7 Global interrupt clear */

+#define BDMA_IFCR_CTCIF7_Pos    (29U)

+#define BDMA_IFCR_CTCIF7_Msk    (0x1UL << BDMA_IFCR_CTCIF7_Pos)                /*!< 0x20000000 */

+#define BDMA_IFCR_CTCIF7        BDMA_IFCR_CTCIF7_Msk                           /*!< Channel 7 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF7_Pos    (30U)

+#define BDMA_IFCR_CHTIF7_Msk    (0x1UL << BDMA_IFCR_CHTIF7_Pos)                /*!< 0x40000000 */

+#define BDMA_IFCR_CHTIF7        BDMA_IFCR_CHTIF7_Msk                           /*!< Channel 7 Half Transfer clear */

+#define BDMA_IFCR_CTEIF7_Pos    (31U)

+#define BDMA_IFCR_CTEIF7_Msk    (0x1UL << BDMA_IFCR_CTEIF7_Pos)                /*!< 0x80000000 */

+#define BDMA_IFCR_CTEIF7        BDMA_IFCR_CTEIF7_Msk                           /*!< Channel 7 Transfer Error clear */

+

+/*******************  Bit definition for BDMA_CCR register  ********************/

+#define BDMA_CCR_EN_Pos         (0U)

+#define BDMA_CCR_EN_Msk         (0x1UL << BDMA_CCR_EN_Pos)                     /*!< 0x00000001 */

+#define BDMA_CCR_EN             BDMA_CCR_EN_Msk                                /*!< Channel enable                      */

+#define BDMA_CCR_TCIE_Pos       (1U)

+#define BDMA_CCR_TCIE_Msk       (0x1UL << BDMA_CCR_TCIE_Pos)                   /*!< 0x00000002 */

+#define BDMA_CCR_TCIE           BDMA_CCR_TCIE_Msk                              /*!< Transfer complete interrupt enable  */

+#define BDMA_CCR_HTIE_Pos       (2U)

+#define BDMA_CCR_HTIE_Msk       (0x1UL << BDMA_CCR_HTIE_Pos)                   /*!< 0x00000004 */

+#define BDMA_CCR_HTIE           BDMA_CCR_HTIE_Msk                              /*!< Half Transfer interrupt enable      */

+#define BDMA_CCR_TEIE_Pos       (3U)

+#define BDMA_CCR_TEIE_Msk       (0x1UL << BDMA_CCR_TEIE_Pos)                   /*!< 0x00000008 */

+#define BDMA_CCR_TEIE           BDMA_CCR_TEIE_Msk                              /*!< Transfer error interrupt enable     */

+#define BDMA_CCR_DIR_Pos        (4U)

+#define BDMA_CCR_DIR_Msk        (0x1UL << BDMA_CCR_DIR_Pos)                    /*!< 0x00000010 */

+#define BDMA_CCR_DIR            BDMA_CCR_DIR_Msk                               /*!< Data transfer direction             */

+#define BDMA_CCR_CIRC_Pos       (5U)

+#define BDMA_CCR_CIRC_Msk       (0x1UL << BDMA_CCR_CIRC_Pos)                   /*!< 0x00000020 */

+#define BDMA_CCR_CIRC           BDMA_CCR_CIRC_Msk                              /*!< Circular mode                       */

+#define BDMA_CCR_PINC_Pos       (6U)

+#define BDMA_CCR_PINC_Msk       (0x1UL << BDMA_CCR_PINC_Pos)                   /*!< 0x00000040 */

+#define BDMA_CCR_PINC           BDMA_CCR_PINC_Msk                              /*!< Peripheral increment mode           */

+#define BDMA_CCR_MINC_Pos       (7U)

+#define BDMA_CCR_MINC_Msk       (0x1UL << BDMA_CCR_MINC_Pos)                   /*!< 0x00000080 */

+#define BDMA_CCR_MINC           BDMA_CCR_MINC_Msk                              /*!< Memory increment mode               */

+

+#define BDMA_CCR_PSIZE_Pos      (8U)

+#define BDMA_CCR_PSIZE_Msk      (0x3UL << BDMA_CCR_PSIZE_Pos)                  /*!< 0x00000300 */

+#define BDMA_CCR_PSIZE          BDMA_CCR_PSIZE_Msk                             /*!< PSIZE[1:0] bits (Peripheral size)   */

+#define BDMA_CCR_PSIZE_0        (0x1UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000100 */

+#define BDMA_CCR_PSIZE_1        (0x2UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000200 */

+

+#define BDMA_CCR_MSIZE_Pos      (10U)

+#define BDMA_CCR_MSIZE_Msk      (0x3UL << BDMA_CCR_MSIZE_Pos)                  /*!< 0x00000C00 */

+#define BDMA_CCR_MSIZE          BDMA_CCR_MSIZE_Msk                             /*!< MSIZE[1:0] bits (Memory size)       */

+#define BDMA_CCR_MSIZE_0        (0x1UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000400 */

+#define BDMA_CCR_MSIZE_1        (0x2UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000800 */

+

+#define BDMA_CCR_PL_Pos         (12U)

+#define BDMA_CCR_PL_Msk         (0x3UL << BDMA_CCR_PL_Pos)                     /*!< 0x00003000 */

+#define BDMA_CCR_PL             BDMA_CCR_PL_Msk                                /*!< PL[1:0] bits(Channel Priority level)*/

+#define BDMA_CCR_PL_0           (0x1UL << BDMA_CCR_PL_Pos)                      /*!< 0x00001000 */

+#define BDMA_CCR_PL_1           (0x2UL << BDMA_CCR_PL_Pos)                      /*!< 0x00002000 */

+

+#define BDMA_CCR_MEM2MEM_Pos    (14U)

+#define BDMA_CCR_MEM2MEM_Msk    (0x1UL << BDMA_CCR_MEM2MEM_Pos)                /*!< 0x00004000 */

+#define BDMA_CCR_MEM2MEM        BDMA_CCR_MEM2MEM_Msk                           /*!< Memory to memory mode               */

+#define BDMA_CCR_DBM_Pos        (15U)

+#define BDMA_CCR_DBM_Msk        (0x1UL << BDMA_CCR_DBM_Pos)                    /*!< 0x0000A000 */

+#define BDMA_CCR_DBM            BDMA_CCR_DBM_Msk                               /*!< Memory to memory mode               */

+#define BDMA_CCR_CT_Pos         (16U)

+#define BDMA_CCR_CT_Msk         (0x1UL << BDMA_CCR_CT_Pos)                     /*!< 0x00010000 */

+#define BDMA_CCR_CT             BDMA_CCR_CT_Msk                                /*!< Memory to memory mode               */

+

+/******************  Bit definition for BDMA_CNDTR register  *******************/

+#define BDMA_CNDTR_NDT_Pos      (0U)

+#define BDMA_CNDTR_NDT_Msk      (0xFFFFUL << BDMA_CNDTR_NDT_Pos)               /*!< 0x0000FFFF */

+#define BDMA_CNDTR_NDT          BDMA_CNDTR_NDT_Msk                             /*!< Number of data to Transfer          */

+

+/******************  Bit definition for BDMA_CPAR register  ********************/

+#define BDMA_CPAR_PA_Pos        (0U)

+#define BDMA_CPAR_PA_Msk        (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CPAR_PA            BDMA_CPAR_PA_Msk                               /*!< Peripheral Address                  */

+

+/******************  Bit definition for BDMA_CM0AR register  ********************/

+#define BDMA_CM0AR_MA_Pos        (0U)

+#define BDMA_CM0AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CM0AR_MA            BDMA_CM0AR_MA_Msk                               /*!< Memory Address                      */

+

+/******************  Bit definition for BDMA_CM1AR register  ********************/

+#define BDMA_CM1AR_MA_Pos        (0U)

+#define BDMA_CM1AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CM1AR_MA            BDMA_CM1AR_MA_Msk                               /*!< Memory Address                      */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             DMA Controller                                 */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DMA_SxCR register  *****************/

+#define DMA_SxCR_MBURST_Pos      (23U)

+#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                /*!< 0x01800000 */

+#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk                           /*!< Memory burst transfer configuration */

+#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */

+#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */

+#define DMA_SxCR_PBURST_Pos      (21U)

+#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                /*!< 0x00600000 */

+#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk                           /*!< Peripheral burst transfer configuration */

+#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */

+#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */

+#define DMA_SxCR_TRBUFF_Pos      (20U)

+#define DMA_SxCR_TRBUFF_Msk      (0x1UL << DMA_SxCR_TRBUFF_Pos)                 /*!< 0x00100000 */

+#define DMA_SxCR_TRBUFF          DMA_SxCR_TRBUFF_Msk                            /*!< bufferable transfers enabled/disable */

+#define DMA_SxCR_CT_Pos          (19U)

+#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                    /*!< 0x00080000 */

+#define DMA_SxCR_CT              DMA_SxCR_CT_Msk                               /*!< Current target (only in double buffer mode) */

+#define DMA_SxCR_DBM_Pos         (18U)

+#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                   /*!< 0x00040000 */

+#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk                              /*!< Double buffer mode */

+#define DMA_SxCR_PL_Pos          (16U)

+#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                    /*!< 0x00030000 */

+#define DMA_SxCR_PL              DMA_SxCR_PL_Msk                               /*!< Priority level */

+#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */

+#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */

+#define DMA_SxCR_PINCOS_Pos      (15U)

+#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                /*!< 0x00008000 */

+#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk                           /*!< Peripheral increment offset size */

+#define DMA_SxCR_MSIZE_Pos       (13U)

+#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                 /*!< 0x00006000 */

+#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk                            /*!< Memory data size */

+#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */

+#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */

+#define DMA_SxCR_PSIZE_Pos       (11U)

+#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                 /*!< 0x00001800 */

+#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk                            /*< Peripheral data size */

+#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */

+#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */

+#define DMA_SxCR_MINC_Pos        (10U)

+#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                  /*!< 0x00000400 */

+#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk                             /*!< Memory increment mode */

+#define DMA_SxCR_PINC_Pos        (9U)

+#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                  /*!< 0x00000200 */

+#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk                             /*!< Peripheral increment mode */

+#define DMA_SxCR_CIRC_Pos        (8U)

+#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                  /*!< 0x00000100 */

+#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk                             /*!< Circular mode */

+#define DMA_SxCR_DIR_Pos         (6U)

+#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                   /*!< 0x000000C0 */

+#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk                              /*!< Data transfer direction */

+#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */

+#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */

+#define DMA_SxCR_PFCTRL_Pos      (5U)

+#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                /*!< 0x00000020 */

+#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk                           /*!< Peripheral flow controller */

+#define DMA_SxCR_TCIE_Pos        (4U)

+#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                  /*!< 0x00000010 */

+#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk                             /*!< Transfer complete interrupt enable */

+#define DMA_SxCR_HTIE_Pos        (3U)

+#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                  /*!< 0x00000008 */

+#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk                             /*!< Half transfer interrupt enable */

+#define DMA_SxCR_TEIE_Pos        (2U)

+#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                  /*!< 0x00000004 */

+#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk                             /*!< Transfer error interrupt enable */

+#define DMA_SxCR_DMEIE_Pos       (1U)

+#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                 /*!< 0x00000002 */

+#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk                            /*!< Direct mode error interrupt enable */

+#define DMA_SxCR_EN_Pos          (0U)

+#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                    /*!< 0x00000001 */

+#define DMA_SxCR_EN              DMA_SxCR_EN_Msk                               /*!< Stream enable / flag stream ready when read low */

+

+/********************  Bits definition for DMA_SxCNDTR register  **************/

+#define DMA_SxNDT_Pos            (0U)

+#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                   /*!< 0x0000FFFF */

+#define DMA_SxNDT                DMA_SxNDT_Msk                                 /*!< Number of data items to transfer */

+#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */

+#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */

+#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */

+#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */

+#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */

+#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */

+#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */

+#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */

+#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */

+#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */

+#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */

+#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */

+#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */

+#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */

+#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */

+#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */

+

+/********************  Bits definition for DMA_SxFCR register  ****************/

+#define DMA_SxFCR_FEIE_Pos       (7U)

+#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                 /*!< 0x00000080 */

+#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk                            /*!< FIFO error interrupt enable */

+#define DMA_SxFCR_FS_Pos         (3U)

+#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                   /*!< 0x00000038 */

+#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk                              /*!< FIFO status */

+#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */

+#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */

+#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */

+#define DMA_SxFCR_DMDIS_Pos      (2U)

+#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                /*!< 0x00000004 */

+#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk                           /*!< Direct mode disable */

+#define DMA_SxFCR_FTH_Pos        (0U)

+#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                  /*!< 0x00000003 */

+#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk                             /*!< FIFO threshold selection */

+#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */

+#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */

+

+/********************  Bits definition for DMA_LISR register  *****************/

+#define DMA_LISR_TCIF3_Pos       (27U)

+#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                 /*!< 0x08000000 */

+#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk                            /*!<  Stream 3 transfer complete interrupt flag */

+#define DMA_LISR_HTIF3_Pos       (26U)

+#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                 /*!< 0x04000000 */

+#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk                            /*!<  Stream 3 half transfer interrupt flag */

+#define DMA_LISR_TEIF3_Pos       (25U)

+#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                 /*!< 0x02000000 */

+#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk                            /*!<  Stream 3 transfer error interrupt flag */

+#define DMA_LISR_DMEIF3_Pos      (24U)

+#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                /*!< 0x01000000 */

+#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk                           /*!<  Stream 3 direct mode error interrupt flag */

+#define DMA_LISR_FEIF3_Pos       (22U)

+#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                 /*!< 0x00400000 */

+#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk                            /*!<  Stream 3 FIFO error interrupt flag */

+#define DMA_LISR_TCIF2_Pos       (21U)

+#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                 /*!< 0x00200000 */

+#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk                            /*!<  Stream 2 transfer complete interrupt flag */

+#define DMA_LISR_HTIF2_Pos       (20U)

+#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                 /*!< 0x00100000 */

+#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk                            /*!<  Stream 2 half transfer interrupt flag */

+#define DMA_LISR_TEIF2_Pos       (19U)

+#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                 /*!< 0x00080000 */

+#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk                            /*!<  Stream 2 transfer error interrupt flag */

+#define DMA_LISR_DMEIF2_Pos      (18U)

+#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                /*!< 0x00040000 */

+#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk                           /*!<  Stream 2 direct mode error interrupt flag */

+#define DMA_LISR_FEIF2_Pos       (16U)

+#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                 /*!< 0x00010000 */

+#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk                            /*!<  Stream 2 FIFO error interrupt flag */

+#define DMA_LISR_TCIF1_Pos       (11U)

+#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                 /*!< 0x00000800 */

+#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk                            /*!<  Stream 1 transfer complete interrupt flag */

+#define DMA_LISR_HTIF1_Pos       (10U)

+#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                 /*!< 0x00000400 */

+#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk                            /*!<  Stream 1 half transfer interrupt flag */

+#define DMA_LISR_TEIF1_Pos       (9U)

+#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                 /*!< 0x00000200 */

+#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk                            /*!<  Stream 1 transfer error interrupt flag */

+#define DMA_LISR_DMEIF1_Pos      (8U)

+#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                /*!< 0x00000100 */

+#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk                           /*!<  Stream 1 direct mode error interrupt flag */

+#define DMA_LISR_FEIF1_Pos       (6U)

+#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                 /*!< 0x00000040 */

+#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk                            /*!<  Stream 1 FIFO error interrupt flag */

+#define DMA_LISR_TCIF0_Pos       (5U)

+#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                 /*!< 0x00000020 */

+#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk                            /*!<  Stream 0 transfer complete interrupt flag */

+#define DMA_LISR_HTIF0_Pos       (4U)

+#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                 /*!< 0x00000010 */

+#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk                            /*!<  Stream 0 half transfer interrupt flag */

+#define DMA_LISR_TEIF0_Pos       (3U)

+#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                 /*!< 0x00000008 */

+#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk                            /*!<  Stream 0 transfer error interrupt flag */

+#define DMA_LISR_DMEIF0_Pos      (2U)

+#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                /*!< 0x00000004 */

+#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk                           /*!<  Stream 0 direct mode error interrupt flag */

+#define DMA_LISR_FEIF0_Pos       (0U)

+#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                 /*!< 0x00000001 */

+#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk                            /*!<  Stream 0 FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_HISR register  *****************/

+#define DMA_HISR_TCIF7_Pos       (27U)

+#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                 /*!< 0x08000000 */

+#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk                            /*!<  Stream 7 transfer complete interrupt flag */

+#define DMA_HISR_HTIF7_Pos       (26U)

+#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                 /*!< 0x04000000 */

+#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk                            /*!<  Stream 7 half transfer interrupt flag */

+#define DMA_HISR_TEIF7_Pos       (25U)

+#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                 /*!< 0x02000000 */

+#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk                            /*!<  Stream 7 transfer error interrupt flag */

+#define DMA_HISR_DMEIF7_Pos      (24U)

+#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                /*!< 0x01000000 */

+#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk                           /*!<  Stream 7 direct mode error interrupt flag */

+#define DMA_HISR_FEIF7_Pos       (22U)

+#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                 /*!< 0x00400000 */

+#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk                            /*!<  Stream 7 FIFO error interrupt flag */

+#define DMA_HISR_TCIF6_Pos       (21U)

+#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                 /*!< 0x00200000 */

+#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk                            /*!<  Stream 6 transfer complete interrupt flag */

+#define DMA_HISR_HTIF6_Pos       (20U)

+#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                 /*!< 0x00100000 */

+#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk                            /*!<  Stream 6 half transfer interrupt flag */

+#define DMA_HISR_TEIF6_Pos       (19U)

+#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                 /*!< 0x00080000 */

+#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk                            /*!<  Stream 6 transfer error interrupt flag */

+#define DMA_HISR_DMEIF6_Pos      (18U)

+#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                /*!< 0x00040000 */

+#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk                           /*!<  Stream 6 direct mode error interrupt flag */

+#define DMA_HISR_FEIF6_Pos       (16U)

+#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                 /*!< 0x00010000 */

+#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk                            /*!<  Stream 6 FIFO error interrupt flag */

+#define DMA_HISR_TCIF5_Pos       (11U)

+#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                 /*!< 0x00000800 */

+#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk                            /*!<  Stream 5 transfer complete interrupt flag */

+#define DMA_HISR_HTIF5_Pos       (10U)

+#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                 /*!< 0x00000400 */

+#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk                            /*!<  Stream 5 half transfer interrupt flag */

+#define DMA_HISR_TEIF5_Pos       (9U)

+#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                 /*!< 0x00000200 */

+#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk                            /*!<  Stream 5 transfer error interrupt flag */

+#define DMA_HISR_DMEIF5_Pos      (8U)

+#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                /*!< 0x00000100 */

+#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk                           /*!<  Stream 5 direct mode error interrupt flag */

+#define DMA_HISR_FEIF5_Pos       (6U)

+#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                 /*!< 0x00000040 */

+#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk                            /*!<  Stream 5 FIFO error interrupt flag */

+#define DMA_HISR_TCIF4_Pos       (5U)

+#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                 /*!< 0x00000020 */

+#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk                            /*!<  Stream 4 transfer complete interrupt flag */

+#define DMA_HISR_HTIF4_Pos       (4U)

+#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                 /*!< 0x00000010 */

+#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk                            /*!<  Stream 4 half transfer interrupt flag */

+#define DMA_HISR_TEIF4_Pos       (3U)

+#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                 /*!< 0x00000008 */

+#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk                            /*!<  Stream 4 transfer error interrupt flag */

+#define DMA_HISR_DMEIF4_Pos      (2U)

+#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                /*!< 0x00000004 */

+#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk                           /*!<  Stream 4 direct mode error interrupt flag */

+#define DMA_HISR_FEIF4_Pos       (0U)

+#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                 /*!< 0x00000001 */

+#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk                            /*!<  Stream 4 FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_LIFCR register  ****************/

+#define DMA_LIFCR_CTCIF3_Pos     (27U)

+#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)               /*!< 0x08000000 */

+#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk                          /*!<  Stream 3 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF3_Pos     (26U)

+#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)               /*!< 0x04000000 */

+#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk                          /*!<  Stream 3 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF3_Pos     (25U)

+#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)               /*!< 0x02000000 */

+#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk                          /*!<  Stream 3 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF3_Pos    (24U)

+#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)              /*!< 0x01000000 */

+#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk                         /*!<  Stream 3 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF3_Pos     (22U)

+#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)               /*!< 0x00400000 */

+#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk                          /*!<  Stream 3 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF2_Pos     (21U)

+#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)               /*!< 0x00200000 */

+#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk                          /*!<  Stream 2 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF2_Pos     (20U)

+#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)               /*!< 0x00100000 */

+#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk                          /*!<  Stream 2 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF2_Pos     (19U)

+#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)               /*!< 0x00080000 */

+#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk                          /*!<  Stream 2 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF2_Pos    (18U)

+#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)              /*!< 0x00040000 */

+#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk                         /*!<  Stream 2 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF2_Pos     (16U)

+#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)               /*!< 0x00010000 */

+#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk                          /*!<  Stream 2 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF1_Pos     (11U)

+#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)               /*!< 0x00000800 */

+#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk                          /*!<  Stream 1 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF1_Pos     (10U)

+#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)               /*!< 0x00000400 */

+#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk                          /*!<  Stream 1 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF1_Pos     (9U)

+#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)               /*!< 0x00000200 */

+#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk                          /*!<  Stream 1 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF1_Pos    (8U)

+#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)              /*!< 0x00000100 */

+#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk                         /*!<  Stream 1 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF1_Pos     (6U)

+#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)               /*!< 0x00000040 */

+#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk                          /*!<  Stream 1 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF0_Pos     (5U)

+#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)               /*!< 0x00000020 */

+#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk                          /*!<  Stream 0 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF0_Pos     (4U)

+#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)               /*!< 0x00000010 */

+#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk                          /*!<  Stream 0 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF0_Pos     (3U)

+#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)               /*!< 0x00000008 */

+#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk                          /*!<  Stream 0 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF0_Pos    (2U)

+#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)              /*!< 0x00000004 */

+#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk                         /*!<  Stream 0 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF0_Pos     (0U)

+#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)               /*!< 0x00000001 */

+#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk                          /*!<  Stream 0 clear FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_HIFCR  register  ****************/

+#define DMA_HIFCR_CTCIF7_Pos     (27U)

+#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)               /*!< 0x08000000 */

+#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk                          /*!<  Stream 7 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF7_Pos     (26U)

+#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)               /*!< 0x04000000 */

+#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk                          /*!<  Stream 7 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF7_Pos     (25U)

+#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)               /*!< 0x02000000 */

+#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk                          /*!<  Stream 7 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF7_Pos    (24U)

+#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)              /*!< 0x01000000 */

+#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk                         /*!<  Stream 7 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF7_Pos     (22U)

+#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)               /*!< 0x00400000 */

+#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk                          /*!<  Stream 7 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF6_Pos     (21U)

+#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)               /*!< 0x00200000 */

+#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk                          /*!<  Stream 6 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF6_Pos     (20U)

+#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)               /*!< 0x00100000 */

+#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk                          /*!<  Stream 6 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF6_Pos     (19U)

+#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)               /*!< 0x00080000 */

+#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk                          /*!<  Stream 6 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF6_Pos    (18U)

+#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)              /*!< 0x00040000 */

+#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk                         /*!<  Stream 6 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF6_Pos     (16U)

+#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)               /*!< 0x00010000 */

+#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk                          /*!<  Stream 6 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF5_Pos     (11U)

+#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)               /*!< 0x00000800 */

+#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk                          /*!<  Stream 5 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF5_Pos     (10U)

+#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)               /*!< 0x00000400 */

+#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk                          /*!<  Stream 5 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF5_Pos     (9U)

+#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)               /*!< 0x00000200 */

+#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk                          /*!<  Stream 5 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF5_Pos    (8U)

+#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)              /*!< 0x00000100 */

+#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk                         /*!<  Stream 5 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF5_Pos     (6U)

+#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)               /*!< 0x00000040 */

+#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk                          /*!<  Stream 5 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF4_Pos     (5U)

+#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)               /*!< 0x00000020 */

+#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk                          /*!<  Stream 4 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF4_Pos     (4U)

+#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)               /*!< 0x00000010 */

+#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk                          /*!<  Stream 4 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF4_Pos     (3U)

+#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)               /*!< 0x00000008 */

+#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk                          /*!<  Stream 4 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF4_Pos    (2U)

+#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)              /*!< 0x00000004 */

+#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk                         /*!<  Stream 4 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF4_Pos     (0U)

+#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)               /*!< 0x00000001 */

+#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk                          /*!<  Stream 4 clear FIFO error interrupt flag */

+

+/******************  Bit definition for DMA_SxPAR register  ********************/

+#define DMA_SxPAR_PA_Pos         (0U)

+#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)            /*!< 0xFFFFFFFF */

+#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */

+

+/******************  Bit definition for DMA_SxM0AR register  ********************/

+#define DMA_SxM0AR_M0A_Pos       (0U)

+#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)          /*!< 0xFFFFFFFF */

+#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory 0 Address */

+

+/******************  Bit definition for DMA_SxM1AR register  ********************/

+#define DMA_SxM1AR_M1A_Pos       (0U)

+#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)          /*!< 0xFFFFFFFF */

+#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory 1 Address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             DMAMUX Controller                              */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DMAMUX_CxCR register  **************/

+#define DMAMUX_CxCR_DMAREQ_ID_Pos      (0U)

+#define DMAMUX_CxCR_DMAREQ_ID_Msk      (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)   /*!< 0x000000FF */

+#define DMAMUX_CxCR_DMAREQ_ID          DMAMUX_CxCR_DMAREQ_ID_Msk               /*!<  DMA request identification */

+#define DMAMUX_CxCR_DMAREQ_ID_0        (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000001 */

+#define DMAMUX_CxCR_DMAREQ_ID_1        (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000002 */

+#define DMAMUX_CxCR_DMAREQ_ID_2        (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000004 */

+#define DMAMUX_CxCR_DMAREQ_ID_3        (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000008 */

+#define DMAMUX_CxCR_DMAREQ_ID_4        (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000010 */

+#define DMAMUX_CxCR_DMAREQ_ID_5        (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000020 */

+#define DMAMUX_CxCR_DMAREQ_ID_6        (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000040 */

+#define DMAMUX_CxCR_DMAREQ_ID_7        (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000080 */

+#define DMAMUX_CxCR_SOIE_Pos           (8U)

+#define DMAMUX_CxCR_SOIE_Msk           (0x1UL << DMAMUX_CxCR_SOIE_Pos)         /*!< 0x00000100 */

+#define DMAMUX_CxCR_SOIE               DMAMUX_CxCR_SOIE_Msk                    /*!<  Synchronization overrun interrupt enable */

+#define DMAMUX_CxCR_EGE_Pos            (9U)

+#define DMAMUX_CxCR_EGE_Msk            (0x1UL << DMAMUX_CxCR_EGE_Pos)          /*!< 0x00000200 */

+#define DMAMUX_CxCR_EGE                DMAMUX_CxCR_EGE_Msk                     /*!<  Event generation enable */

+#define DMAMUX_CxCR_SE_Pos             (16U)

+#define DMAMUX_CxCR_SE_Msk             (0x1UL << DMAMUX_CxCR_SE_Pos)           /*!< 0x00010000 */

+#define DMAMUX_CxCR_SE                 DMAMUX_CxCR_SE_Msk                      /*!<  Synchronization enable */

+#define DMAMUX_CxCR_SPOL_Pos           (17U)

+#define DMAMUX_CxCR_SPOL_Msk           (0x3UL << DMAMUX_CxCR_SPOL_Pos)         /*!< 0x00060000 */

+#define DMAMUX_CxCR_SPOL               DMAMUX_CxCR_SPOL_Msk                    /*!<  Synchronization polarity */

+#define DMAMUX_CxCR_SPOL_0             (0x1UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00020000 */

+#define DMAMUX_CxCR_SPOL_1             (0x2UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00040000 */

+#define DMAMUX_CxCR_NBREQ_Pos          (19U)

+#define DMAMUX_CxCR_NBREQ_Msk          (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)       /*!< 0x00F80000 */

+#define DMAMUX_CxCR_NBREQ              DMAMUX_CxCR_NBREQ_Msk                   /*!<  Number of DMA requests minus 1 to forward */

+#define DMAMUX_CxCR_NBREQ_0            (0x01UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00080000 */

+#define DMAMUX_CxCR_NBREQ_1            (0x02UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00100000 */

+#define DMAMUX_CxCR_NBREQ_2            (0x04UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00200000 */

+#define DMAMUX_CxCR_NBREQ_3            (0x08UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00400000 */

+#define DMAMUX_CxCR_NBREQ_4            (0x10UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00800000 */

+#define DMAMUX_CxCR_SYNC_ID_Pos        (24U)

+#define DMAMUX_CxCR_SYNC_ID_Msk        (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)     /*!< 0x1F000000 */

+#define DMAMUX_CxCR_SYNC_ID            DMAMUX_CxCR_SYNC_ID_Msk                 /*!<  Synchronization identification */

+#define DMAMUX_CxCR_SYNC_ID_0          (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x01000000 */

+#define DMAMUX_CxCR_SYNC_ID_1          (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x02000000 */

+#define DMAMUX_CxCR_SYNC_ID_2          (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x04000000 */

+#define DMAMUX_CxCR_SYNC_ID_3          (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x08000000 */

+#define DMAMUX_CxCR_SYNC_ID_4          (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x10000000 */

+

+/********************  Bits definition for DMAMUX_CSR register  **************/

+#define DMAMUX_CSR_SOF0_Pos            (0U)

+#define DMAMUX_CSR_SOF0_Msk            (0x1UL << DMAMUX_CSR_SOF0_Pos)          /*!< 0x00000001 */

+#define DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0_Msk                     /*!< Channel 0 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF1_Pos            (1U)

+#define DMAMUX_CSR_SOF1_Msk            (0x1UL << DMAMUX_CSR_SOF1_Pos)          /*!< 0x00000002 */

+#define DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1_Msk                     /*!< Channel 1 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF2_Pos            (2U)

+#define DMAMUX_CSR_SOF2_Msk            (0x1UL << DMAMUX_CSR_SOF2_Pos)          /*!< 0x00000004 */

+#define DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2_Msk                     /*!< Channel 2 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF3_Pos            (3U)

+#define DMAMUX_CSR_SOF3_Msk            (0x1UL << DMAMUX_CSR_SOF3_Pos)          /*!< 0x00000008 */

+#define DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3_Msk                     /*!< Channel 3 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF4_Pos            (4U)

+#define DMAMUX_CSR_SOF4_Msk            (0x1UL << DMAMUX_CSR_SOF4_Pos)          /*!< 0x00000010 */

+#define DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4_Msk                     /*!< Channel 4 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF5_Pos            (5U)

+#define DMAMUX_CSR_SOF5_Msk            (0x1UL << DMAMUX_CSR_SOF5_Pos)          /*!< 0x00000020 */

+#define DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5_Msk                     /*!< Channel 5 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF6_Pos            (6U)

+#define DMAMUX_CSR_SOF6_Msk            (0x1UL << DMAMUX_CSR_SOF6_Pos)          /*!< 0x00000040 */

+#define DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6_Msk                     /*!< Channel 6 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF7_Pos            (7U)

+#define DMAMUX_CSR_SOF7_Msk            (0x1UL << DMAMUX_CSR_SOF7_Pos)          /*!< 0x00000080 */

+#define DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7_Msk                     /*!< Channel 7 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF8_Pos            (8U)

+#define DMAMUX_CSR_SOF8_Msk            (0x1UL << DMAMUX_CSR_SOF8_Pos)          /*!< 0x00000100 */

+#define DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8_Msk                     /*!< Channel 8 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF9_Pos            (9U)

+#define DMAMUX_CSR_SOF9_Msk            (0x1UL << DMAMUX_CSR_SOF9_Pos)          /*!< 0x00000200 */

+#define DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9_Msk                     /*!< Channel 9 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF10_Pos           (10U)

+#define DMAMUX_CSR_SOF10_Msk           (0x1UL << DMAMUX_CSR_SOF10_Pos)         /*!< 0x00000400 */

+#define DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10_Msk                    /*!< Channel 10 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF11_Pos           (11U)

+#define DMAMUX_CSR_SOF11_Msk           (0x1UL << DMAMUX_CSR_SOF11_Pos)         /*!< 0x00000800 */

+#define DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11_Msk                    /*!< Channel 11 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF12_Pos           (12U)

+#define DMAMUX_CSR_SOF12_Msk           (0x1UL << DMAMUX_CSR_SOF12_Pos)         /*!< 0x00001000 */

+#define DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12_Msk                    /*!< Channel 12 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF13_Pos           (13U)

+#define DMAMUX_CSR_SOF13_Msk           (0x1UL << DMAMUX_CSR_SOF13_Pos)         /*!< 0x00002000 */

+#define DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13_Msk                    /*!< Channel 13 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF14_Pos           (14U)

+#define DMAMUX_CSR_SOF14_Msk           (0x1UL << DMAMUX_CSR_SOF14_Pos)         /*!< 0x00004000 */

+#define DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14_Msk                    /*!< Channel 14 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF15_Pos           (15U)

+#define DMAMUX_CSR_SOF15_Msk           (0x1UL << DMAMUX_CSR_SOF15_Pos)         /*!< 0x00008000 */

+#define DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15_Msk                    /*!< Channel 15 Synchronization overrun event flag */

+

+/********************  Bits definition for DMAMUX_CFR register  **************/

+#define DMAMUX_CFR_CSOF0_Pos           (0U)

+#define DMAMUX_CFR_CSOF0_Msk           (0x1UL << DMAMUX_CFR_CSOF0_Pos)         /*!< 0x00000001 */

+#define DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0_Msk                    /*!< Channel 0 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF1_Pos           (1U)

+#define DMAMUX_CFR_CSOF1_Msk           (0x1UL << DMAMUX_CFR_CSOF1_Pos)         /*!< 0x00000002 */

+#define DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1_Msk                    /*!< Channel 1 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF2_Pos           (2U)

+#define DMAMUX_CFR_CSOF2_Msk           (0x1UL << DMAMUX_CFR_CSOF2_Pos)         /*!< 0x00000004 */

+#define DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2_Msk                    /*!< Channel 2 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF3_Pos           (3U)

+#define DMAMUX_CFR_CSOF3_Msk           (0x1UL << DMAMUX_CFR_CSOF3_Pos)         /*!< 0x00000008 */

+#define DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3_Msk                    /*!< Channel 3 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF4_Pos           (4U)

+#define DMAMUX_CFR_CSOF4_Msk           (0x1UL << DMAMUX_CFR_CSOF4_Pos)         /*!< 0x00000010 */

+#define DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4_Msk                    /*!< Channel 4 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF5_Pos           (5U)

+#define DMAMUX_CFR_CSOF5_Msk           (0x1UL << DMAMUX_CFR_CSOF5_Pos)         /*!< 0x00000020 */

+#define DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5_Msk                    /*!< Channel 5 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF6_Pos           (6U)

+#define DMAMUX_CFR_CSOF6_Msk           (0x1UL << DMAMUX_CFR_CSOF6_Pos)         /*!< 0x00000040 */

+#define DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6_Msk                    /*!< Channel 6 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF7_Pos           (7U)

+#define DMAMUX_CFR_CSOF7_Msk           (0x1UL << DMAMUX_CFR_CSOF7_Pos)         /*!< 0x00000080 */

+#define DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7_Msk                    /*!< Channel 7 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF8_Pos           (8U)

+#define DMAMUX_CFR_CSOF8_Msk           (0x1UL << DMAMUX_CFR_CSOF8_Pos)         /*!< 0x00000100 */

+#define DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8_Msk                    /*!< Channel 8 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF9_Pos           (9U)

+#define DMAMUX_CFR_CSOF9_Msk           (0x1UL << DMAMUX_CFR_CSOF9_Pos)         /*!< 0x00000200 */

+#define DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9_Msk                    /*!< Channel 9 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF10_Pos          (10U)

+#define DMAMUX_CFR_CSOF10_Msk          (0x1UL << DMAMUX_CFR_CSOF10_Pos)        /*!< 0x00000400 */

+#define DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10_Msk                   /*!< Channel 10 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF11_Pos          (11U)

+#define DMAMUX_CFR_CSOF11_Msk          (0x1UL << DMAMUX_CFR_CSOF11_Pos)        /*!< 0x00000800 */

+#define DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11_Msk                   /*!< Channel 11 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF12_Pos          (12U)

+#define DMAMUX_CFR_CSOF12_Msk          (0x1UL << DMAMUX_CFR_CSOF12_Pos)        /*!< 0x00001000 */

+#define DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12_Msk                   /*!< Channel 12 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF13_Pos          (13U)

+#define DMAMUX_CFR_CSOF13_Msk          (0x1UL << DMAMUX_CFR_CSOF13_Pos)        /*!< 0x00002000 */

+#define DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13_Msk                   /*!< Channel 13 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF14_Pos          (14U)

+#define DMAMUX_CFR_CSOF14_Msk          (0x1UL << DMAMUX_CFR_CSOF14_Pos)        /*!< 0x00004000 */

+#define DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14_Msk                   /*!< Channel 14 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF15_Pos          (15U)

+#define DMAMUX_CFR_CSOF15_Msk          (0x1UL << DMAMUX_CFR_CSOF15_Pos)        /*!< 0x00008000 */

+#define DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15_Msk                   /*!< Channel 15 Clear synchronization overrun event flag */

+

+/********************  Bits definition for DMAMUX_RGxCR register  ************/

+#define DMAMUX_RGxCR_SIG_ID_Pos        (0U)

+#define DMAMUX_RGxCR_SIG_ID_Msk        (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)     /*!< 0x0000001F */

+#define DMAMUX_RGxCR_SIG_ID            DMAMUX_RGxCR_SIG_ID_Msk                 /*!< Signal identification */

+#define DMAMUX_RGxCR_SIG_ID_0          (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000001 */

+#define DMAMUX_RGxCR_SIG_ID_1          (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000002 */

+#define DMAMUX_RGxCR_SIG_ID_2          (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000004 */

+#define DMAMUX_RGxCR_SIG_ID_3          (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000008 */

+#define DMAMUX_RGxCR_SIG_ID_4          (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000010 */

+#define DMAMUX_RGxCR_OIE_Pos           (8U)

+#define DMAMUX_RGxCR_OIE_Msk           (0x1UL << DMAMUX_RGxCR_OIE_Pos)         /*!< 0x00000100 */

+#define DMAMUX_RGxCR_OIE               DMAMUX_RGxCR_OIE_Msk                    /*!< Trigger overrun interrupt enable */

+#define DMAMUX_RGxCR_GE_Pos            (16U)

+#define DMAMUX_RGxCR_GE_Msk            (0x1UL << DMAMUX_RGxCR_GE_Pos)          /*!< 0x00010000 */

+#define DMAMUX_RGxCR_GE                DMAMUX_RGxCR_GE_Msk                     /*!< DMA request generator enable */

+#define DMAMUX_RGxCR_GPOL_Pos          (17U)

+#define DMAMUX_RGxCR_GPOL_Msk          (0x3UL << DMAMUX_RGxCR_GPOL_Pos)        /*!< 0x00060000 */

+#define DMAMUX_RGxCR_GPOL              DMAMUX_RGxCR_GPOL_Msk                   /*!< DMA request generator trigger polarity */

+#define DMAMUX_RGxCR_GPOL_0            (0x1UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00020000 */

+#define DMAMUX_RGxCR_GPOL_1            (0x2UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00040000 */

+#define DMAMUX_RGxCR_GNBREQ_Pos        (19U)

+#define DMAMUX_RGxCR_GNBREQ_Msk        (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)     /*!< 0x00F80000 */

+#define DMAMUX_RGxCR_GNBREQ            DMAMUX_RGxCR_GNBREQ_Msk                 /*!< Number of DMA requests to be generated */

+#define DMAMUX_RGxCR_GNBREQ_0          (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00080000 */

+#define DMAMUX_RGxCR_GNBREQ_1          (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00100000 */

+#define DMAMUX_RGxCR_GNBREQ_2          (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00200000 */

+#define DMAMUX_RGxCR_GNBREQ_3          (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00400000 */

+#define DMAMUX_RGxCR_GNBREQ_4          (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00800000 */

+

+/********************  Bits definition for DMAMUX_RGSR register  **************/

+#define DMAMUX_RGSR_OF0_Pos            (0U)

+#define DMAMUX_RGSR_OF0_Msk            (0x1UL << DMAMUX_RGSR_OF0_Pos)          /*!< 0x00000001 */

+#define DMAMUX_RGSR_OF0                DMAMUX_RGSR_OF0_Msk                     /*!< Request generator channel 0 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF1_Pos            (1U)

+#define DMAMUX_RGSR_OF1_Msk            (0x1UL << DMAMUX_RGSR_OF1_Pos)          /*!< 0x00000002 */

+#define DMAMUX_RGSR_OF1                DMAMUX_RGSR_OF1_Msk                     /*!< Request generator channel 1 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF2_Pos            (2U)

+#define DMAMUX_RGSR_OF2_Msk            (0x1UL << DMAMUX_RGSR_OF2_Pos)          /*!< 0x00000004 */

+#define DMAMUX_RGSR_OF2                DMAMUX_RGSR_OF2_Msk                     /*!< Request generator channel 2 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF3_Pos            (3U)

+#define DMAMUX_RGSR_OF3_Msk            (0x1UL << DMAMUX_RGSR_OF3_Pos)          /*!< 0x00000008 */

+#define DMAMUX_RGSR_OF3                DMAMUX_RGSR_OF3_Msk                     /*!< Request generator channel 3 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF4_Pos            (4U)

+#define DMAMUX_RGSR_OF4_Msk            (0x1UL << DMAMUX_RGSR_OF4_Pos)          /*!< 0x00000010 */

+#define DMAMUX_RGSR_OF4                DMAMUX_RGSR_OF4_Msk                     /*!< Request generator channel 4 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF5_Pos            (5U)

+#define DMAMUX_RGSR_OF5_Msk            (0x1UL << DMAMUX_RGSR_OF5_Pos)          /*!< 0x00000020 */

+#define DMAMUX_RGSR_OF5                DMAMUX_RGSR_OF5_Msk                     /*!< Request generator channel 5 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF6_Pos            (6U)

+#define DMAMUX_RGSR_OF6_Msk            (0x1UL << DMAMUX_RGSR_OF6_Pos)          /*!< 0x00000040 */

+#define DMAMUX_RGSR_OF6                DMAMUX_RGSR_OF6_Msk                     /*!< Request generator channel 6 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF7_Pos            (7U)

+#define DMAMUX_RGSR_OF7_Msk            (0x1UL << DMAMUX_RGSR_OF7_Pos)          /*!< 0x00000080 */

+#define DMAMUX_RGSR_OF7                DMAMUX_RGSR_OF7_Msk                     /*!< Request generator channel 7 Trigger overrun event flag */

+

+/********************  Bits definition for DMAMUX_RGCFR register  **************/

+#define DMAMUX_RGCFR_COF0_Pos          (0U)

+#define DMAMUX_RGCFR_COF0_Msk          (0x1UL << DMAMUX_RGCFR_COF0_Pos)        /*!< 0x00000001 */

+#define DMAMUX_RGCFR_COF0              DMAMUX_RGCFR_COF0_Msk                   /*!< Request generator channel 0 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF1_Pos          (1U)

+#define DMAMUX_RGCFR_COF1_Msk          (0x1UL << DMAMUX_RGCFR_COF1_Pos)        /*!< 0x00000002 */

+#define DMAMUX_RGCFR_COF1              DMAMUX_RGCFR_COF1_Msk                   /*!< Request generator channel 1 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF2_Pos          (2U)

+#define DMAMUX_RGCFR_COF2_Msk          (0x1UL << DMAMUX_RGCFR_COF2_Pos)        /*!< 0x00000004 */

+#define DMAMUX_RGCFR_COF2              DMAMUX_RGCFR_COF2_Msk                   /*!< Request generator channel 2 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF3_Pos          (3U)

+#define DMAMUX_RGCFR_COF3_Msk          (0x1UL << DMAMUX_RGCFR_COF3_Pos)        /*!< 0x00000008 */

+#define DMAMUX_RGCFR_COF3              DMAMUX_RGCFR_COF3_Msk                   /*!< Request generator channel 3 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF4_Pos          (4U)

+#define DMAMUX_RGCFR_COF4_Msk          (0x1UL << DMAMUX_RGCFR_COF4_Pos)        /*!< 0x00000010 */

+#define DMAMUX_RGCFR_COF4              DMAMUX_RGCFR_COF4_Msk                   /*!< Request generator channel 4 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF5_Pos          (5U)

+#define DMAMUX_RGCFR_COF5_Msk          (0x1UL << DMAMUX_RGCFR_COF5_Pos)        /*!< 0x00000020 */

+#define DMAMUX_RGCFR_COF5              DMAMUX_RGCFR_COF5_Msk                   /*!< Request generator channel 5 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF6_Pos          (6U)

+#define DMAMUX_RGCFR_COF6_Msk          (0x1UL << DMAMUX_RGCFR_COF6_Pos)        /*!< 0x00000040 */

+#define DMAMUX_RGCFR_COF6              DMAMUX_RGCFR_COF6_Msk                   /*!< Request generator channel 6 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF7_Pos          (7U)

+#define DMAMUX_RGCFR_COF7_Msk          (0x1UL << DMAMUX_RGCFR_COF7_Pos)        /*!< 0x00000080 */

+#define DMAMUX_RGCFR_COF7              DMAMUX_RGCFR_COF7_Msk                   /*!< Request generator channel 7 Clear trigger overrun event flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         AHB Master DMA2D Controller (DMA2D)                */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for DMA2D_CR register  ******************/

+

+#define DMA2D_CR_START_Pos         (0U)

+#define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)               /*!< 0x00000001 */

+#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer                          */

+#define DMA2D_CR_SUSP_Pos          (1U)

+#define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                /*!< 0x00000002 */

+#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer                        */

+#define DMA2D_CR_ABORT_Pos         (2U)

+#define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)               /*!< 0x00000004 */

+#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer                          */

+#define DMA2D_CR_LOM_Pos           (6U)

+#define DMA2D_CR_LOM_Msk           (0x1UL << DMA2D_CR_LOM_Pos)                 /*!< 0x00000040 */

+#define DMA2D_CR_LOM               DMA2D_CR_LOM_Msk                            /*!< Line Offset Mode                         */

+#define DMA2D_CR_TEIE_Pos          (8U)

+#define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                /*!< 0x00000100 */

+#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable         */

+#define DMA2D_CR_TCIE_Pos          (9U)

+#define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                /*!< 0x00000200 */

+#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable      */

+#define DMA2D_CR_TWIE_Pos          (10U)

+#define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                /*!< 0x00000400 */

+#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable     */

+#define DMA2D_CR_CAEIE_Pos         (11U)

+#define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)               /*!< 0x00000800 */

+#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable      */

+#define DMA2D_CR_CTCIE_Pos         (12U)

+#define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)               /*!< 0x00001000 */

+#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */

+#define DMA2D_CR_CEIE_Pos          (13U)

+#define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                /*!< 0x00002000 */

+#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable    */

+#define DMA2D_CR_MODE_Pos          (16U)

+#define DMA2D_CR_MODE_Msk          (0x7UL << DMA2D_CR_MODE_Pos)                /*!< 0x00070000 */

+#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[2:0]                         */

+#define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */

+#define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */

+#define DMA2D_CR_MODE_2            (0x4UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00040000 */

+

+/********************  Bit definition for DMA2D_ISR register  *****************/

+

+#define DMA2D_ISR_TEIF_Pos         (0U)

+#define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)               /*!< 0x00000001 */

+#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag         */

+#define DMA2D_ISR_TCIF_Pos         (1U)

+#define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)               /*!< 0x00000002 */

+#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag      */

+#define DMA2D_ISR_TWIF_Pos         (2U)

+#define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)               /*!< 0x00000004 */

+#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag     */

+#define DMA2D_ISR_CAEIF_Pos        (3U)

+#define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)              /*!< 0x00000008 */

+#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag      */

+#define DMA2D_ISR_CTCIF_Pos        (4U)

+#define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)              /*!< 0x00000010 */

+#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */

+#define DMA2D_ISR_CEIF_Pos         (5U)

+#define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)               /*!< 0x00000020 */

+#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag    */

+

+/********************  Bit definition for DMA2D_IFCR register  ****************/

+

+#define DMA2D_IFCR_CTEIF_Pos       (0U)

+#define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)             /*!< 0x00000001 */

+#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */

+#define DMA2D_IFCR_CTCIF_Pos       (1U)

+#define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)             /*!< 0x00000002 */

+#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */

+#define DMA2D_IFCR_CTWIF_Pos       (2U)

+#define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)             /*!< 0x00000004 */

+#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */

+#define DMA2D_IFCR_CAECIF_Pos      (3U)

+#define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)            /*!< 0x00000008 */

+#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */

+#define DMA2D_IFCR_CCTCIF_Pos      (4U)

+#define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)            /*!< 0x00000010 */

+#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */

+#define DMA2D_IFCR_CCEIF_Pos       (5U)

+#define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)             /*!< 0x00000020 */

+#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */

+

+/********************  Bit definition for DMA2D_FGMAR register  ***************/

+

+#define DMA2D_FGMAR_MA_Pos         (0U)

+#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)        /*!< 0xFFFFFFFF */

+#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Foreground Memory Address */

+

+/********************  Bit definition for DMA2D_FGOR register  ****************/

+

+#define DMA2D_FGOR_LO_Pos          (0U)

+#define DMA2D_FGOR_LO_Msk          (0xFFFFUL << DMA2D_FGOR_LO_Pos)             /*!< 0x0000FFFF */

+#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */

+

+/********************  Bit definition for DMA2D_BGMAR register  ***************/

+

+#define DMA2D_BGMAR_MA_Pos         (0U)

+#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)        /*!< 0xFFFFFFFF */

+#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Background Memory Address */

+

+/********************  Bit definition for DMA2D_BGOR register  ****************/

+

+#define DMA2D_BGOR_LO_Pos          (0U)

+#define DMA2D_BGOR_LO_Msk          (0xFFFFUL << DMA2D_BGOR_LO_Pos)             /*!< 0x0000FFFF */

+#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */

+

+/********************  Bit definition for DMA2D_FGPFCCR register  *************/

+

+#define DMA2D_FGPFCCR_CM_Pos       (0U)

+#define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x0000000F */

+#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */

+#define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */

+#define DMA2D_FGPFCCR_CCM_Pos      (4U)

+#define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)            /*!< 0x00000010 */

+#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */

+#define DMA2D_FGPFCCR_START_Pos    (5U)

+#define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)          /*!< 0x00000020 */

+#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */

+#define DMA2D_FGPFCCR_CS_Pos       (8U)

+#define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)            /*!< 0x0000FF00 */

+#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */

+#define DMA2D_FGPFCCR_AM_Pos       (16U)

+#define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00030000 */

+#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */

+#define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */

+#define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */

+#define DMA2D_FGPFCCR_CSS_Pos      (18U)

+#define DMA2D_FGPFCCR_CSS_Msk      (0x3UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x000C0000 */

+#define DMA2D_FGPFCCR_CSS          DMA2D_FGPFCCR_CSS_Msk                       /* !< Chroma Sub-Sampling */

+#define DMA2D_FGPFCCR_CSS_0        (0x1UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00040000 */

+#define DMA2D_FGPFCCR_CSS_1        (0x2UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00080000 */

+#define DMA2D_FGPFCCR_AI_Pos       (20U)

+#define DMA2D_FGPFCCR_AI_Msk       (0x1UL << DMA2D_FGPFCCR_AI_Pos)             /*!< 0x00100000 */

+#define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Foreground Input Alpha Inverted */

+#define DMA2D_FGPFCCR_RBS_Pos      (21U)

+#define DMA2D_FGPFCCR_RBS_Msk      (0x1UL << DMA2D_FGPFCCR_RBS_Pos)            /*!< 0x00200000 */

+#define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Foreground Input Red Blue Swap */

+#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)

+#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */

+#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */

+

+/********************  Bit definition for DMA2D_FGCOLR register  **************/

+

+#define DMA2D_FGCOLR_BLUE_Pos      (0U)

+#define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)           /*!< 0x000000FF */

+#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Foreground Blue Value */

+#define DMA2D_FGCOLR_GREEN_Pos     (8U)

+#define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */

+#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Foreground Green Value */

+#define DMA2D_FGCOLR_RED_Pos       (16U)

+#define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)            /*!< 0x00FF0000 */

+#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Foreground Red Value */

+

+/********************  Bit definition for DMA2D_BGPFCCR register  *************/

+

+#define DMA2D_BGPFCCR_CM_Pos       (0U)

+#define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x0000000F */

+#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */

+#define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_BGPFCCR_CM_3         (0x8UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000008 */

+#define DMA2D_BGPFCCR_CCM_Pos      (4U)

+#define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)            /*!< 0x00000010 */

+#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */

+#define DMA2D_BGPFCCR_START_Pos    (5U)

+#define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)          /*!< 0x00000020 */

+#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */

+#define DMA2D_BGPFCCR_CS_Pos       (8U)

+#define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)            /*!< 0x0000FF00 */

+#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */

+#define DMA2D_BGPFCCR_AM_Pos       (16U)

+#define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00030000 */

+#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */

+#define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */

+#define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */

+#define DMA2D_BGPFCCR_AI_Pos       (20U)

+#define DMA2D_BGPFCCR_AI_Msk       (0x1UL << DMA2D_BGPFCCR_AI_Pos)             /*!< 0x00100000 */

+#define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< background Input Alpha Inverted */

+#define DMA2D_BGPFCCR_RBS_Pos      (21U)

+#define DMA2D_BGPFCCR_RBS_Msk      (0x1UL << DMA2D_BGPFCCR_RBS_Pos)            /*!< 0x00200000 */

+#define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Background Input Red Blue Swap */

+#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)

+#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */

+#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */

+

+/********************  Bit definition for DMA2D_BGCOLR register  **************/

+

+#define DMA2D_BGCOLR_BLUE_Pos      (0U)

+#define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)           /*!< 0x000000FF */

+#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Background Blue Value */

+#define DMA2D_BGCOLR_GREEN_Pos     (8U)

+#define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */

+#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Background Green Value */

+#define DMA2D_BGCOLR_RED_Pos       (16U)

+#define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)            /*!< 0x00FF0000 */

+#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Background Red Value */

+

+/********************  Bit definition for DMA2D_FGCMAR register  **************/

+

+#define DMA2D_FGCMAR_MA_Pos        (0U)

+#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */

+#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Foreground CLUT Memory Address */

+

+/********************  Bit definition for DMA2D_BGCMAR register  **************/

+

+#define DMA2D_BGCMAR_MA_Pos        (0U)

+#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */

+#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Background CLUT Memory Address */

+

+/********************  Bit definition for DMA2D_OPFCCR register  **************/

+

+#define DMA2D_OPFCCR_CM_Pos        (0U)

+#define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000007 */

+#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Output Color mode CM[2:0] */

+#define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_OPFCCR_SB_Pos        (8U)

+#define DMA2D_OPFCCR_SB_Msk        (0x1UL << DMA2D_OPFCCR_SB_Pos)              /*!< 0x00000100 */

+#define DMA2D_OPFCCR_SB            DMA2D_OPFCCR_SB_Msk                         /*!< Swap Bytes */

+#define DMA2D_OPFCCR_AI_Pos        (20U)

+#define DMA2D_OPFCCR_AI_Msk        (0x1UL << DMA2D_OPFCCR_AI_Pos)              /*!< 0x00100000 */

+#define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Output Alpha Inverted */

+#define DMA2D_OPFCCR_RBS_Pos       (21U)

+#define DMA2D_OPFCCR_RBS_Msk       (0x1UL << DMA2D_OPFCCR_RBS_Pos)             /*!< 0x00200000 */

+#define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Output Red Blue Swap */

+

+/********************  Bit definition for DMA2D_OCOLR register  ***************/

+

+/*!<Mode_ARGB8888/RGB888 */

+

+#define DMA2D_OCOLR_BLUE_1_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_1_Msk     (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos)            /*0x000000FFU*/

+#define DMA2D_OCOLR_BLUE_1         DMA2D_OCOLR_BLUE_1_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_1_Pos    (8U)

+#define DMA2D_OCOLR_GREEN_1_Msk    (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos)            /*0x0000FF00U)*/

+#define DMA2D_OCOLR_GREEN_1        DMA2D_OCOLR_GREEN_1_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_1_Pos      (16U)

+#define DMA2D_OCOLR_RED_1_Msk      (0xFFUL << DMA2D_OCOLR_RED_1_Pos)            /*0x00FF0000U */

+#define DMA2D_OCOLR_RED_1          DMA2D_OCOLR_RED_1_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_1_Pos    (24U)

+#define DMA2D_OCOLR_ALPHA_1_Msk    (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos)          /*0xFF000000U*/

+#define DMA2D_OCOLR_ALPHA_1        DMA2D_OCOLR_ALPHA_1_Msk                     /*!< Output Alpha Channel Value */

+

+/*!<Mode_RGB565 */

+#define DMA2D_OCOLR_BLUE_2_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_2_Msk     (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos)            /*0x0000001FU*/

+#define DMA2D_OCOLR_BLUE_2         DMA2D_OCOLR_BLUE_2_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_2_Pos    (5U)

+#define DMA2D_OCOLR_GREEN_2_Msk    (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos)          /* 0x000007E0U */

+#define DMA2D_OCOLR_GREEN_2        DMA2D_OCOLR_GREEN_2_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_2_Pos      (11U)

+#define DMA2D_OCOLR_RED_2_Msk      (0xF8UL<<DMA2D_OCOLR_RED_2_Pos)              /*0x0000F800U*/

+#define DMA2D_OCOLR_RED_2          DMA2D_OCOLR_RED_2_Msk                       /*!< Output Red Value */

+

+/*!<Mode_ARGB1555 */

+#define DMA2D_OCOLR_BLUE_3_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_3_Msk     (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos)           /*0x0000001FU*/

+#define DMA2D_OCOLR_BLUE_3         DMA2D_OCOLR_BLUE_3_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_3_Pos    (5U)

+#define DMA2D_OCOLR_GREEN_3_Msk    (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos)          /*0x000003E0U*/

+#define DMA2D_OCOLR_GREEN_3        DMA2D_OCOLR_GREEN_3_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_3_Pos      (10U)

+#define DMA2D_OCOLR_RED_3_Msk      (0x7CUL << DMA2D_OCOLR_RED_3_Pos)            /* 0x00007C00U*/

+#define DMA2D_OCOLR_RED_3          DMA2D_OCOLR_RED_3_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_3_Pos    (15U)

+#define DMA2D_OCOLR_ALPHA_3_Msk    (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos)           /*0x00008000U*/

+#define DMA2D_OCOLR_ALPHA_3        DMA2D_OCOLR_ALPHA_3_Msk                     /*!< Output Alpha Channel Value */

+

+/*!<Mode_ARGB4444 */

+#define DMA2D_OCOLR_BLUE_4_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_4_Msk     (0xFUL << DMA2D_OCOLR_BLUE_4_Pos)            /*0x0000000FU*/

+#define DMA2D_OCOLR_BLUE_4         DMA2D_OCOLR_BLUE_4_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_4_Pos    (4U)

+#define DMA2D_OCOLR_GREEN_4_Msk    (0xFUL << DMA2D_OCOLR_GREEN_4_Pos)           /*0x000000F0U*/

+#define DMA2D_OCOLR_GREEN_4        DMA2D_OCOLR_GREEN_4_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_4_Pos      (8U)

+#define DMA2D_OCOLR_RED_4_Msk      (0xFUL << DMA2D_OCOLR_RED_4_Pos)             /*0x00000F00U*/

+#define DMA2D_OCOLR_RED_4          DMA2D_OCOLR_RED_4_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_4_Pos    (12U)

+#define DMA2D_OCOLR_ALPHA_4_Msk    (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos)            /*0x0000F000U*/

+#define DMA2D_OCOLR_ALPHA_4        DMA2D_OCOLR_ALPHA_4_Msk                     /*!< Output Alpha Channel Value */

+

+/********************  Bit definition for DMA2D_OMAR register  ****************/

+

+#define DMA2D_OMAR_MA_Pos          (0U)

+#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)         /*!< 0xFFFFFFFF */

+#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Output Memory Address */

+

+/********************  Bit definition for DMA2D_OOR register  *****************/

+

+#define DMA2D_OOR_LO_Pos           (0U)

+#define DMA2D_OOR_LO_Msk           (0xFFFFUL << DMA2D_OOR_LO_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Output Line Offset */

+

+/********************  Bit definition for DMA2D_NLR register  *****************/

+

+#define DMA2D_NLR_NL_Pos           (0U)

+#define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */

+#define DMA2D_NLR_PL_Pos           (16U)

+#define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)              /*!< 0x3FFF0000 */

+#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */

+

+/********************  Bit definition for DMA2D_LWR register  *****************/

+

+#define DMA2D_LWR_LW_Pos           (0U)

+#define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */

+

+/********************  Bit definition for DMA2D_AMTCR register  ***************/

+

+#define DMA2D_AMTCR_EN_Pos         (0U)

+#define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)               /*!< 0x00000001 */

+#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */

+#define DMA2D_AMTCR_DT_Pos         (8U)

+#define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)              /*!< 0x0000FF00 */

+#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */

+

+

+/********************  Bit definition for DMA2D_FGCLUT register  **************/

+

+/********************  Bit definition for DMA2D_BGCLUT register  **************/

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                    External Interrupt/Event Controller                     */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for EXTI_RTSR1 register  *******************/

+#define EXTI_RTSR1_TR_Pos          (0U)

+#define EXTI_RTSR1_TR_Msk          (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)           /*!< 0x003FFFFF */

+#define EXTI_RTSR1_TR              EXTI_RTSR1_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR1_TR0_Pos         (0U)

+#define EXTI_RTSR1_TR0_Msk         (0x1UL << EXTI_RTSR1_TR0_Pos)               /*!< 0x00000001 */

+#define EXTI_RTSR1_TR0             EXTI_RTSR1_TR0_Msk                          /*!< Rising trigger event configuration bit of line 0 */

+#define EXTI_RTSR1_TR1_Pos         (1U)

+#define EXTI_RTSR1_TR1_Msk         (0x1UL << EXTI_RTSR1_TR1_Pos)               /*!< 0x00000002 */

+#define EXTI_RTSR1_TR1             EXTI_RTSR1_TR1_Msk                          /*!< Rising trigger event configuration bit of line 1 */

+#define EXTI_RTSR1_TR2_Pos         (2U)

+#define EXTI_RTSR1_TR2_Msk         (0x1UL << EXTI_RTSR1_TR2_Pos)               /*!< 0x00000004 */

+#define EXTI_RTSR1_TR2             EXTI_RTSR1_TR2_Msk                          /*!< Rising trigger event configuration bit of line 2 */

+#define EXTI_RTSR1_TR3_Pos         (3U)

+#define EXTI_RTSR1_TR3_Msk         (0x1UL << EXTI_RTSR1_TR3_Pos)               /*!< 0x00000008 */

+#define EXTI_RTSR1_TR3             EXTI_RTSR1_TR3_Msk                          /*!< Rising trigger event configuration bit of line 3 */

+#define EXTI_RTSR1_TR4_Pos         (4U)

+#define EXTI_RTSR1_TR4_Msk         (0x1UL << EXTI_RTSR1_TR4_Pos)               /*!< 0x00000010 */

+#define EXTI_RTSR1_TR4             EXTI_RTSR1_TR4_Msk                          /*!< Rising trigger event configuration bit of line 4 */

+#define EXTI_RTSR1_TR5_Pos         (5U)

+#define EXTI_RTSR1_TR5_Msk         (0x1UL << EXTI_RTSR1_TR5_Pos)               /*!< 0x00000020 */

+#define EXTI_RTSR1_TR5             EXTI_RTSR1_TR5_Msk                          /*!< Rising trigger event configuration bit of line 5 */

+#define EXTI_RTSR1_TR6_Pos         (6U)

+#define EXTI_RTSR1_TR6_Msk         (0x1UL << EXTI_RTSR1_TR6_Pos)               /*!< 0x00000040 */

+#define EXTI_RTSR1_TR6             EXTI_RTSR1_TR6_Msk                          /*!< Rising trigger event configuration bit of line 6 */

+#define EXTI_RTSR1_TR7_Pos         (7U)

+#define EXTI_RTSR1_TR7_Msk         (0x1UL << EXTI_RTSR1_TR7_Pos)               /*!< 0x00000080 */

+#define EXTI_RTSR1_TR7             EXTI_RTSR1_TR7_Msk                          /*!< Rising trigger event configuration bit of line 7 */

+#define EXTI_RTSR1_TR8_Pos         (8U)

+#define EXTI_RTSR1_TR8_Msk         (0x1UL << EXTI_RTSR1_TR8_Pos)               /*!< 0x00000100 */

+#define EXTI_RTSR1_TR8             EXTI_RTSR1_TR8_Msk                          /*!< Rising trigger event configuration bit of line 8 */

+#define EXTI_RTSR1_TR9_Pos         (9U)

+#define EXTI_RTSR1_TR9_Msk         (0x1UL << EXTI_RTSR1_TR9_Pos)               /*!< 0x00000200 */

+#define EXTI_RTSR1_TR9             EXTI_RTSR1_TR9_Msk                          /*!< Rising trigger event configuration bit of line 9 */

+#define EXTI_RTSR1_TR10_Pos        (10U)

+#define EXTI_RTSR1_TR10_Msk        (0x1UL << EXTI_RTSR1_TR10_Pos)              /*!< 0x00000400 */

+#define EXTI_RTSR1_TR10            EXTI_RTSR1_TR10_Msk                         /*!< Rising trigger event configuration bit of line 10 */

+#define EXTI_RTSR1_TR11_Pos        (11U)

+#define EXTI_RTSR1_TR11_Msk        (0x1UL << EXTI_RTSR1_TR11_Pos)              /*!< 0x00000800 */

+#define EXTI_RTSR1_TR11            EXTI_RTSR1_TR11_Msk                         /*!< Rising trigger event configuration bit of line 11 */

+#define EXTI_RTSR1_TR12_Pos        (12U)

+#define EXTI_RTSR1_TR12_Msk        (0x1UL << EXTI_RTSR1_TR12_Pos)              /*!< 0x00001000 */

+#define EXTI_RTSR1_TR12            EXTI_RTSR1_TR12_Msk                         /*!< Rising trigger event configuration bit of line 12 */

+#define EXTI_RTSR1_TR13_Pos        (13U)

+#define EXTI_RTSR1_TR13_Msk        (0x1UL << EXTI_RTSR1_TR13_Pos)              /*!< 0x00002000 */

+#define EXTI_RTSR1_TR13            EXTI_RTSR1_TR13_Msk                         /*!< Rising trigger event configuration bit of line 13 */

+#define EXTI_RTSR1_TR14_Pos        (14U)

+#define EXTI_RTSR1_TR14_Msk        (0x1UL << EXTI_RTSR1_TR14_Pos)              /*!< 0x00004000 */

+#define EXTI_RTSR1_TR14            EXTI_RTSR1_TR14_Msk                         /*!< Rising trigger event configuration bit of line 14 */

+#define EXTI_RTSR1_TR15_Pos        (15U)

+#define EXTI_RTSR1_TR15_Msk        (0x1UL << EXTI_RTSR1_TR15_Pos)              /*!< 0x00008000 */

+#define EXTI_RTSR1_TR15            EXTI_RTSR1_TR15_Msk                         /*!< Rising trigger event configuration bit of line 15 */

+#define EXTI_RTSR1_TR16_Pos        (16U)

+#define EXTI_RTSR1_TR16_Msk        (0x1UL << EXTI_RTSR1_TR16_Pos)              /*!< 0x00010000 */

+#define EXTI_RTSR1_TR16            EXTI_RTSR1_TR16_Msk                         /*!< Rising trigger event configuration bit of line 16 */

+#define EXTI_RTSR1_TR17_Pos        (17U)

+#define EXTI_RTSR1_TR17_Msk        (0x1UL << EXTI_RTSR1_TR17_Pos)              /*!< 0x00020000 */

+#define EXTI_RTSR1_TR17            EXTI_RTSR1_TR17_Msk                         /*!< Rising trigger event configuration bit of line 17 */

+#define EXTI_RTSR1_TR18_Pos        (18U)

+#define EXTI_RTSR1_TR18_Msk        (0x1UL << EXTI_RTSR1_TR18_Pos)              /*!< 0x00040000 */

+#define EXTI_RTSR1_TR18            EXTI_RTSR1_TR18_Msk                         /*!< Rising trigger event configuration bit of line 18 */

+#define EXTI_RTSR1_TR19_Pos        (19U)

+#define EXTI_RTSR1_TR19_Msk        (0x1UL << EXTI_RTSR1_TR19_Pos)              /*!< 0x00080000 */

+#define EXTI_RTSR1_TR19            EXTI_RTSR1_TR19_Msk                         /*!< Rising trigger event configuration bit of line 19 */

+#define EXTI_RTSR1_TR20_Pos        (20U)

+#define EXTI_RTSR1_TR20_Msk        (0x1UL << EXTI_RTSR1_TR20_Pos)              /*!< 0x00100000 */

+#define EXTI_RTSR1_TR20            EXTI_RTSR1_TR20_Msk                         /*!< Rising trigger event configuration bit of line 20 */

+#define EXTI_RTSR1_TR21_Pos        (21U)

+#define EXTI_RTSR1_TR21_Msk        (0x1UL << EXTI_RTSR1_TR21_Pos)              /*!< 0x00200000 */

+#define EXTI_RTSR1_TR21            EXTI_RTSR1_TR21_Msk                         /*!< Rising trigger event configuration bit of line 21 */

+

+/******************  Bit definition for EXTI_FTSR1 register  *******************/

+#define EXTI_FTSR1_TR_Pos          (0U)

+#define EXTI_FTSR1_TR_Msk          (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)           /*!< 0x003FFFFF */

+#define EXTI_FTSR1_TR              EXTI_FTSR1_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR1_TR0_Pos         (0U)

+#define EXTI_FTSR1_TR0_Msk         (0x1UL << EXTI_FTSR1_TR0_Pos)               /*!< 0x00000001 */

+#define EXTI_FTSR1_TR0             EXTI_FTSR1_TR0_Msk                          /*!< Falling trigger event configuration bit of line 0 */

+#define EXTI_FTSR1_TR1_Pos         (1U)

+#define EXTI_FTSR1_TR1_Msk         (0x1UL << EXTI_FTSR1_TR1_Pos)               /*!< 0x00000002 */

+#define EXTI_FTSR1_TR1             EXTI_FTSR1_TR1_Msk                          /*!< Falling trigger event configuration bit of line 1 */

+#define EXTI_FTSR1_TR2_Pos         (2U)

+#define EXTI_FTSR1_TR2_Msk         (0x1UL << EXTI_FTSR1_TR2_Pos)               /*!< 0x00000004 */

+#define EXTI_FTSR1_TR2             EXTI_FTSR1_TR2_Msk                          /*!< Falling trigger event configuration bit of line 2 */

+#define EXTI_FTSR1_TR3_Pos         (3U)

+#define EXTI_FTSR1_TR3_Msk         (0x1UL << EXTI_FTSR1_TR3_Pos)               /*!< 0x00000008 */

+#define EXTI_FTSR1_TR3             EXTI_FTSR1_TR3_Msk                          /*!< Falling trigger event configuration bit of line 3 */

+#define EXTI_FTSR1_TR4_Pos         (4U)

+#define EXTI_FTSR1_TR4_Msk         (0x1UL << EXTI_FTSR1_TR4_Pos)               /*!< 0x00000010 */

+#define EXTI_FTSR1_TR4             EXTI_FTSR1_TR4_Msk                          /*!< Falling trigger event configuration bit of line 4 */

+#define EXTI_FTSR1_TR5_Pos         (5U)

+#define EXTI_FTSR1_TR5_Msk         (0x1UL << EXTI_FTSR1_TR5_Pos)               /*!< 0x00000020 */

+#define EXTI_FTSR1_TR5             EXTI_FTSR1_TR5_Msk                          /*!< Falling trigger event configuration bit of line 5 */

+#define EXTI_FTSR1_TR6_Pos         (6U)

+#define EXTI_FTSR1_TR6_Msk         (0x1UL << EXTI_FTSR1_TR6_Pos)               /*!< 0x00000040 */

+#define EXTI_FTSR1_TR6             EXTI_FTSR1_TR6_Msk                          /*!< Falling trigger event configuration bit of line 6 */

+#define EXTI_FTSR1_TR7_Pos         (7U)

+#define EXTI_FTSR1_TR7_Msk         (0x1UL << EXTI_FTSR1_TR7_Pos)               /*!< 0x00000080 */

+#define EXTI_FTSR1_TR7             EXTI_FTSR1_TR7_Msk                          /*!< Falling trigger event configuration bit of line 7 */

+#define EXTI_FTSR1_TR8_Pos         (8U)

+#define EXTI_FTSR1_TR8_Msk         (0x1UL << EXTI_FTSR1_TR8_Pos)               /*!< 0x00000100 */

+#define EXTI_FTSR1_TR8             EXTI_FTSR1_TR8_Msk                          /*!< Falling trigger event configuration bit of line 8 */

+#define EXTI_FTSR1_TR9_Pos         (9U)

+#define EXTI_FTSR1_TR9_Msk         (0x1UL << EXTI_FTSR1_TR9_Pos)               /*!< 0x00000200 */

+#define EXTI_FTSR1_TR9             EXTI_FTSR1_TR9_Msk                          /*!< Falling trigger event configuration bit of line 9 */

+#define EXTI_FTSR1_TR10_Pos        (10U)

+#define EXTI_FTSR1_TR10_Msk        (0x1UL << EXTI_FTSR1_TR10_Pos)              /*!< 0x00000400 */

+#define EXTI_FTSR1_TR10            EXTI_FTSR1_TR10_Msk                         /*!< Falling trigger event configuration bit of line 10 */

+#define EXTI_FTSR1_TR11_Pos        (11U)

+#define EXTI_FTSR1_TR11_Msk        (0x1UL << EXTI_FTSR1_TR11_Pos)              /*!< 0x00000800 */

+#define EXTI_FTSR1_TR11            EXTI_FTSR1_TR11_Msk                         /*!< Falling trigger event configuration bit of line 11 */

+#define EXTI_FTSR1_TR12_Pos        (12U)

+#define EXTI_FTSR1_TR12_Msk        (0x1UL << EXTI_FTSR1_TR12_Pos)              /*!< 0x00001000 */

+#define EXTI_FTSR1_TR12            EXTI_FTSR1_TR12_Msk                         /*!< Falling trigger event configuration bit of line 12 */

+#define EXTI_FTSR1_TR13_Pos        (13U)

+#define EXTI_FTSR1_TR13_Msk        (0x1UL << EXTI_FTSR1_TR13_Pos)              /*!< 0x00002000 */

+#define EXTI_FTSR1_TR13            EXTI_FTSR1_TR13_Msk                         /*!< Falling trigger event configuration bit of line 13 */

+#define EXTI_FTSR1_TR14_Pos        (14U)

+#define EXTI_FTSR1_TR14_Msk        (0x1UL << EXTI_FTSR1_TR14_Pos)              /*!< 0x00004000 */

+#define EXTI_FTSR1_TR14            EXTI_FTSR1_TR14_Msk                         /*!< Falling trigger event configuration bit of line 14 */

+#define EXTI_FTSR1_TR15_Pos        (15U)

+#define EXTI_FTSR1_TR15_Msk        (0x1UL << EXTI_FTSR1_TR15_Pos)              /*!< 0x00008000 */

+#define EXTI_FTSR1_TR15            EXTI_FTSR1_TR15_Msk                         /*!< Falling trigger event configuration bit of line 15 */

+#define EXTI_FTSR1_TR16_Pos        (16U)

+#define EXTI_FTSR1_TR16_Msk        (0x1UL << EXTI_FTSR1_TR16_Pos)              /*!< 0x00010000 */

+#define EXTI_FTSR1_TR16            EXTI_FTSR1_TR16_Msk                         /*!< Falling trigger event configuration bit of line 16 */

+#define EXTI_FTSR1_TR17_Pos        (17U)

+#define EXTI_FTSR1_TR17_Msk        (0x1UL << EXTI_FTSR1_TR17_Pos)              /*!< 0x00020000 */

+#define EXTI_FTSR1_TR17            EXTI_FTSR1_TR17_Msk                         /*!< Falling trigger event configuration bit of line 17 */

+#define EXTI_FTSR1_TR18_Pos        (18U)

+#define EXTI_FTSR1_TR18_Msk        (0x1UL << EXTI_FTSR1_TR18_Pos)              /*!< 0x00040000 */

+#define EXTI_FTSR1_TR18            EXTI_FTSR1_TR18_Msk                         /*!< Falling trigger event configuration bit of line 18 */

+#define EXTI_FTSR1_TR19_Pos        (19U)

+#define EXTI_FTSR1_TR19_Msk        (0x1UL << EXTI_FTSR1_TR19_Pos)              /*!< 0x00080000 */

+#define EXTI_FTSR1_TR19            EXTI_FTSR1_TR19_Msk                         /*!< Falling trigger event configuration bit of line 19 */

+#define EXTI_FTSR1_TR20_Pos        (20U)

+#define EXTI_FTSR1_TR20_Msk        (0x1UL << EXTI_FTSR1_TR20_Pos)              /*!< 0x00100000 */

+#define EXTI_FTSR1_TR20            EXTI_FTSR1_TR20_Msk                         /*!< Falling trigger event configuration bit of line 20 */

+#define EXTI_FTSR1_TR21_Pos        (21U)

+#define EXTI_FTSR1_TR21_Msk        (0x1UL << EXTI_FTSR1_TR21_Pos)              /*!< 0x00200000 */

+#define EXTI_FTSR1_TR21            EXTI_FTSR1_TR21_Msk                         /*!< Falling trigger event configuration bit of line 21 */

+

+/******************  Bit definition for EXTI_SWIER1 register  ******************/

+#define EXTI_SWIER1_SWIER0_Pos     (0U)

+#define EXTI_SWIER1_SWIER0_Msk     (0x1UL << EXTI_SWIER1_SWIER0_Pos)           /*!< 0x00000001 */

+#define EXTI_SWIER1_SWIER0         EXTI_SWIER1_SWIER0_Msk                      /*!< Software Interrupt on line 0 */

+#define EXTI_SWIER1_SWIER1_Pos     (1U)

+#define EXTI_SWIER1_SWIER1_Msk     (0x1UL << EXTI_SWIER1_SWIER1_Pos)           /*!< 0x00000002 */

+#define EXTI_SWIER1_SWIER1         EXTI_SWIER1_SWIER1_Msk                      /*!< Software Interrupt on line 1 */

+#define EXTI_SWIER1_SWIER2_Pos     (2U)

+#define EXTI_SWIER1_SWIER2_Msk     (0x1UL << EXTI_SWIER1_SWIER2_Pos)           /*!< 0x00000004 */

+#define EXTI_SWIER1_SWIER2         EXTI_SWIER1_SWIER2_Msk                      /*!< Software Interrupt on line 2 */

+#define EXTI_SWIER1_SWIER3_Pos     (3U)

+#define EXTI_SWIER1_SWIER3_Msk     (0x1UL << EXTI_SWIER1_SWIER3_Pos)           /*!< 0x00000008 */

+#define EXTI_SWIER1_SWIER3         EXTI_SWIER1_SWIER3_Msk                      /*!< Software Interrupt on line 3 */

+#define EXTI_SWIER1_SWIER4_Pos     (4U)

+#define EXTI_SWIER1_SWIER4_Msk     (0x1UL << EXTI_SWIER1_SWIER4_Pos)           /*!< 0x00000010 */

+#define EXTI_SWIER1_SWIER4         EXTI_SWIER1_SWIER4_Msk                      /*!< Software Interrupt on line 4 */

+#define EXTI_SWIER1_SWIER5_Pos     (5U)

+#define EXTI_SWIER1_SWIER5_Msk     (0x1UL << EXTI_SWIER1_SWIER5_Pos)           /*!< 0x00000020 */

+#define EXTI_SWIER1_SWIER5         EXTI_SWIER1_SWIER5_Msk                      /*!< Software Interrupt on line 5 */

+#define EXTI_SWIER1_SWIER6_Pos     (6U)

+#define EXTI_SWIER1_SWIER6_Msk     (0x1UL << EXTI_SWIER1_SWIER6_Pos)           /*!< 0x00000040 */

+#define EXTI_SWIER1_SWIER6         EXTI_SWIER1_SWIER6_Msk                      /*!< Software Interrupt on line 6 */

+#define EXTI_SWIER1_SWIER7_Pos     (7U)

+#define EXTI_SWIER1_SWIER7_Msk     (0x1UL << EXTI_SWIER1_SWIER7_Pos)           /*!< 0x00000080 */

+#define EXTI_SWIER1_SWIER7         EXTI_SWIER1_SWIER7_Msk                      /*!< Software Interrupt on line 7 */

+#define EXTI_SWIER1_SWIER8_Pos     (8U)

+#define EXTI_SWIER1_SWIER8_Msk     (0x1UL << EXTI_SWIER1_SWIER8_Pos)           /*!< 0x00000100 */

+#define EXTI_SWIER1_SWIER8         EXTI_SWIER1_SWIER8_Msk                      /*!< Software Interrupt on line 8 */

+#define EXTI_SWIER1_SWIER9_Pos     (9U)

+#define EXTI_SWIER1_SWIER9_Msk     (0x1UL << EXTI_SWIER1_SWIER9_Pos)           /*!< 0x00000200 */

+#define EXTI_SWIER1_SWIER9         EXTI_SWIER1_SWIER9_Msk                      /*!< Software Interrupt on line 9 */

+#define EXTI_SWIER1_SWIER10_Pos    (10U)

+#define EXTI_SWIER1_SWIER10_Msk    (0x1UL << EXTI_SWIER1_SWIER10_Pos)          /*!< 0x00000400 */

+#define EXTI_SWIER1_SWIER10        EXTI_SWIER1_SWIER10_Msk                     /*!< Software Interrupt on line 10 */

+#define EXTI_SWIER1_SWIER11_Pos    (11U)

+#define EXTI_SWIER1_SWIER11_Msk    (0x1UL << EXTI_SWIER1_SWIER11_Pos)          /*!< 0x00000800 */

+#define EXTI_SWIER1_SWIER11        EXTI_SWIER1_SWIER11_Msk                     /*!< Software Interrupt on line 11 */

+#define EXTI_SWIER1_SWIER12_Pos    (12U)

+#define EXTI_SWIER1_SWIER12_Msk    (0x1UL << EXTI_SWIER1_SWIER12_Pos)          /*!< 0x00001000 */

+#define EXTI_SWIER1_SWIER12        EXTI_SWIER1_SWIER12_Msk                     /*!< Software Interrupt on line 12 */

+#define EXTI_SWIER1_SWIER13_Pos    (13U)

+#define EXTI_SWIER1_SWIER13_Msk    (0x1UL << EXTI_SWIER1_SWIER13_Pos)          /*!< 0x00002000 */

+#define EXTI_SWIER1_SWIER13        EXTI_SWIER1_SWIER13_Msk                     /*!< Software Interrupt on line 13 */

+#define EXTI_SWIER1_SWIER14_Pos    (14U)

+#define EXTI_SWIER1_SWIER14_Msk    (0x1UL << EXTI_SWIER1_SWIER14_Pos)          /*!< 0x00004000 */

+#define EXTI_SWIER1_SWIER14        EXTI_SWIER1_SWIER14_Msk                     /*!< Software Interrupt on line 14 */

+#define EXTI_SWIER1_SWIER15_Pos    (15U)

+#define EXTI_SWIER1_SWIER15_Msk    (0x1UL << EXTI_SWIER1_SWIER15_Pos)          /*!< 0x00008000 */

+#define EXTI_SWIER1_SWIER15        EXTI_SWIER1_SWIER15_Msk                     /*!< Software Interrupt on line 15 */

+#define EXTI_SWIER1_SWIER16_Pos    (16U)

+#define EXTI_SWIER1_SWIER16_Msk    (0x1UL << EXTI_SWIER1_SWIER16_Pos)          /*!< 0x00010000 */

+#define EXTI_SWIER1_SWIER16        EXTI_SWIER1_SWIER16_Msk                     /*!< Software Interrupt on line 16 */

+#define EXTI_SWIER1_SWIER17_Pos    (17U)

+#define EXTI_SWIER1_SWIER17_Msk    (0x1UL << EXTI_SWIER1_SWIER17_Pos)          /*!< 0x00020000 */

+#define EXTI_SWIER1_SWIER17        EXTI_SWIER1_SWIER17_Msk                     /*!< Software Interrupt on line 17 */

+#define EXTI_SWIER1_SWIER18_Pos    (18U)

+#define EXTI_SWIER1_SWIER18_Msk    (0x1UL << EXTI_SWIER1_SWIER18_Pos)          /*!< 0x00040000 */

+#define EXTI_SWIER1_SWIER18        EXTI_SWIER1_SWIER18_Msk                     /*!< Software Interrupt on line 18 */

+#define EXTI_SWIER1_SWIER19_Pos    (19U)

+#define EXTI_SWIER1_SWIER19_Msk    (0x1UL << EXTI_SWIER1_SWIER19_Pos)          /*!< 0x00080000 */

+#define EXTI_SWIER1_SWIER19        EXTI_SWIER1_SWIER19_Msk                     /*!< Software Interrupt on line 19 */

+#define EXTI_SWIER1_SWIER20_Pos    (20U)

+#define EXTI_SWIER1_SWIER20_Msk    (0x1UL << EXTI_SWIER1_SWIER20_Pos)          /*!< 0x00100000 */

+#define EXTI_SWIER1_SWIER20        EXTI_SWIER1_SWIER20_Msk                     /*!< Software Interrupt on line 20 */

+#define EXTI_SWIER1_SWIER21_Pos    (21U)

+#define EXTI_SWIER1_SWIER21_Msk    (0x1UL << EXTI_SWIER1_SWIER21_Pos)          /*!< 0x00200000 */

+#define EXTI_SWIER1_SWIER21        EXTI_SWIER1_SWIER21_Msk                     /*!< Software Interrupt on line 21 */

+

+/******************  Bit definition for EXTI_D3PMR1 register  ******************/

+#define EXTI_D3PMR1_MR0_Pos        (0U)

+#define EXTI_D3PMR1_MR0_Msk        (0x1UL << EXTI_D3PMR1_MR0_Pos)              /*!< 0x00000001 */

+#define EXTI_D3PMR1_MR0            EXTI_D3PMR1_MR0_Msk                         /*!< Pending Mask Event for line 0  */

+#define EXTI_D3PMR1_MR1_Pos        (1U)

+#define EXTI_D3PMR1_MR1_Msk        (0x1UL << EXTI_D3PMR1_MR1_Pos)              /*!< 0x00000002 */

+#define EXTI_D3PMR1_MR1            EXTI_D3PMR1_MR1_Msk                         /*!< Pending Mask Event for line 1  */

+#define EXTI_D3PMR1_MR2_Pos        (2U)

+#define EXTI_D3PMR1_MR2_Msk        (0x1UL << EXTI_D3PMR1_MR2_Pos)              /*!< 0x00000004 */

+#define EXTI_D3PMR1_MR2            EXTI_D3PMR1_MR2_Msk                         /*!< Pending Mask Event for line 2  */

+#define EXTI_D3PMR1_MR3_Pos        (3U)

+#define EXTI_D3PMR1_MR3_Msk        (0x1UL << EXTI_D3PMR1_MR3_Pos)              /*!< 0x00000008 */

+#define EXTI_D3PMR1_MR3            EXTI_D3PMR1_MR3_Msk                         /*!< Pending Mask Event for line 3  */

+#define EXTI_D3PMR1_MR4_Pos        (4U)

+#define EXTI_D3PMR1_MR4_Msk        (0x1UL << EXTI_D3PMR1_MR4_Pos)              /*!< 0x00000010 */

+#define EXTI_D3PMR1_MR4            EXTI_D3PMR1_MR4_Msk                         /*!< Pending Mask Event for line 4  */

+#define EXTI_D3PMR1_MR5_Pos        (5U)

+#define EXTI_D3PMR1_MR5_Msk        (0x1UL << EXTI_D3PMR1_MR5_Pos)              /*!< 0x00000020 */

+#define EXTI_D3PMR1_MR5            EXTI_D3PMR1_MR5_Msk                         /*!< Pending Mask Event for line 5  */

+#define EXTI_D3PMR1_MR6_Pos        (6U)

+#define EXTI_D3PMR1_MR6_Msk        (0x1UL << EXTI_D3PMR1_MR6_Pos)              /*!< 0x00000040 */

+#define EXTI_D3PMR1_MR6            EXTI_D3PMR1_MR6_Msk                         /*!< Pending Mask Event for line 6  */

+#define EXTI_D3PMR1_MR7_Pos        (7U)

+#define EXTI_D3PMR1_MR7_Msk        (0x1UL << EXTI_D3PMR1_MR7_Pos)              /*!< 0x00000080 */

+#define EXTI_D3PMR1_MR7            EXTI_D3PMR1_MR7_Msk                         /*!< Pending Mask Event for line 7  */

+#define EXTI_D3PMR1_MR8_Pos        (8U)

+#define EXTI_D3PMR1_MR8_Msk        (0x1UL << EXTI_D3PMR1_MR8_Pos)              /*!< 0x00000100 */

+#define EXTI_D3PMR1_MR8            EXTI_D3PMR1_MR8_Msk                         /*!< Pending Mask Event for line 8  */

+#define EXTI_D3PMR1_MR9_Pos        (9U)

+#define EXTI_D3PMR1_MR9_Msk        (0x1UL << EXTI_D3PMR1_MR9_Pos)              /*!< 0x00000200 */

+#define EXTI_D3PMR1_MR9            EXTI_D3PMR1_MR9_Msk                         /*!< Pending Mask Event for line 9  */

+#define EXTI_D3PMR1_MR10_Pos       (10U)

+#define EXTI_D3PMR1_MR10_Msk       (0x1UL << EXTI_D3PMR1_MR10_Pos)             /*!< 0x00000400 */

+#define EXTI_D3PMR1_MR10           EXTI_D3PMR1_MR10_Msk                        /*!< Pending Mask Event for line 10 */

+#define EXTI_D3PMR1_MR11_Pos       (11U)

+#define EXTI_D3PMR1_MR11_Msk       (0x1UL << EXTI_D3PMR1_MR11_Pos)             /*!< 0x00000800 */

+#define EXTI_D3PMR1_MR11           EXTI_D3PMR1_MR11_Msk                        /*!< Pending Mask Event for line 11 */

+#define EXTI_D3PMR1_MR12_Pos       (12U)

+#define EXTI_D3PMR1_MR12_Msk       (0x1UL << EXTI_D3PMR1_MR12_Pos)             /*!< 0x00001000 */

+#define EXTI_D3PMR1_MR12           EXTI_D3PMR1_MR12_Msk                        /*!< Pending Mask Event for line 12 */

+#define EXTI_D3PMR1_MR13_Pos       (13U)

+#define EXTI_D3PMR1_MR13_Msk       (0x1UL << EXTI_D3PMR1_MR13_Pos)             /*!< 0x00002000 */

+#define EXTI_D3PMR1_MR13           EXTI_D3PMR1_MR13_Msk                        /*!< Pending Mask Event for line 13 */

+#define EXTI_D3PMR1_MR14_Pos       (14U)

+#define EXTI_D3PMR1_MR14_Msk       (0x1UL << EXTI_D3PMR1_MR14_Pos)             /*!< 0x00004000 */

+#define EXTI_D3PMR1_MR14           EXTI_D3PMR1_MR14_Msk                        /*!< Pending Mask Event for line 14 */

+#define EXTI_D3PMR1_MR15_Pos       (15U)

+#define EXTI_D3PMR1_MR15_Msk       (0x1UL << EXTI_D3PMR1_MR15_Pos)             /*!< 0x00008000 */

+#define EXTI_D3PMR1_MR15           EXTI_D3PMR1_MR15_Msk                        /*!< Pending Mask Event for line 15 */

+#define EXTI_D3PMR1_MR19_Pos       (19U)

+#define EXTI_D3PMR1_MR19_Msk       (0x1UL << EXTI_D3PMR1_MR19_Pos)             /*!< 0x00080000 */

+#define EXTI_D3PMR1_MR19           EXTI_D3PMR1_MR19_Msk                        /*!< Pending Mask Event for line 19 */

+#define EXTI_D3PMR1_MR20_Pos       (20U)

+#define EXTI_D3PMR1_MR20_Msk       (0x1UL << EXTI_D3PMR1_MR20_Pos)             /*!< 0x00100000 */

+#define EXTI_D3PMR1_MR20           EXTI_D3PMR1_MR20_Msk                        /*!< Pending Mask Event for line 20 */

+#define EXTI_D3PMR1_MR21_Pos       (21U)

+#define EXTI_D3PMR1_MR21_Msk       (0x1UL << EXTI_D3PMR1_MR21_Pos)             /*!< 0x00200000 */

+#define EXTI_D3PMR1_MR21           EXTI_D3PMR1_MR21_Msk                        /*!< Pending Mask Event for line 21 */

+#define EXTI_D3PMR1_MR25_Pos       (24U)

+#define EXTI_D3PMR1_MR25_Msk       (0x1UL << EXTI_D3PMR1_MR25_Pos)             /*!< 0x01000000 */

+#define EXTI_D3PMR1_MR25           EXTI_D3PMR1_MR25_Msk                        /*!< Pending Mask Event for line 25 */

+

+/*******************  Bit definition for EXTI_D3PCR1L register  ****************/

+#define EXTI_D3PCR1L_PCS0_Pos       (0U)

+#define EXTI_D3PCR1L_PCS0_Msk       (0x3UL << EXTI_D3PCR1L_PCS0_Pos)           /*!< 0x00000003 */

+#define EXTI_D3PCR1L_PCS0           EXTI_D3PCR1L_PCS0_Msk                      /*!< D3 Pending request clear input signal selection on line 0 */

+#define EXTI_D3PCR1L_PCS1_Pos       (2U)

+#define EXTI_D3PCR1L_PCS1_Msk       (0x3UL << EXTI_D3PCR1L_PCS1_Pos)           /*!< 0x000000C0 */

+#define EXTI_D3PCR1L_PCS1           EXTI_D3PCR1L_PCS1_Msk                      /*!< D3 Pending request clear input signal selection on line 1 */

+#define EXTI_D3PCR1L_PCS2_Pos       (4U)

+#define EXTI_D3PCR1L_PCS2_Msk       (0x3UL << EXTI_D3PCR1L_PCS2_Pos)           /*!< 0x00000030 */

+#define EXTI_D3PCR1L_PCS2           EXTI_D3PCR1L_PCS2_Msk                      /*!< D3 Pending request clear input signal selection on line 2 */

+#define EXTI_D3PCR1L_PCS3_Pos       (6U)

+#define EXTI_D3PCR1L_PCS3_Msk       (0x3UL << EXTI_D3PCR1L_PCS3_Pos)           /*!< 0x000000C0 */

+#define EXTI_D3PCR1L_PCS3           EXTI_D3PCR1L_PCS3_Msk                      /*!< D3 Pending request clear input signal selection on line 3 */

+#define EXTI_D3PCR1L_PCS4_Pos       (8U)

+#define EXTI_D3PCR1L_PCS4_Msk       (0x3UL << EXTI_D3PCR1L_PCS4_Pos)           /*!< 0x00000300 */

+#define EXTI_D3PCR1L_PCS4           EXTI_D3PCR1L_PCS4_Msk                      /*!< D3 Pending request clear input signal selection on line 4 */

+#define EXTI_D3PCR1L_PCS5_Pos       (10U)

+#define EXTI_D3PCR1L_PCS5_Msk       (0x3UL << EXTI_D3PCR1L_PCS5_Pos)           /*!< 0x00000C00 */

+#define EXTI_D3PCR1L_PCS5           EXTI_D3PCR1L_PCS5_Msk                      /*!< D3 Pending request clear input signal selection on line 5 */

+#define EXTI_D3PCR1L_PCS6_Pos       (12U)

+#define EXTI_D3PCR1L_PCS6_Msk       (0x3UL << EXTI_D3PCR1L_PCS6_Pos)           /*!< 0x00003000 */

+#define EXTI_D3PCR1L_PCS6           EXTI_D3PCR1L_PCS6_Msk                      /*!< D3 Pending request clear input signal selection on line 6 */

+#define EXTI_D3PCR1L_PCS7_Pos       (14U)

+#define EXTI_D3PCR1L_PCS7_Msk       (0x3UL << EXTI_D3PCR1L_PCS7_Pos)           /*!< 0x0000C000 */

+#define EXTI_D3PCR1L_PCS7           EXTI_D3PCR1L_PCS7_Msk                      /*!< D3 Pending request clear input signal selection on line 7 */

+#define EXTI_D3PCR1L_PCS8_Pos       (16U)

+#define EXTI_D3PCR1L_PCS8_Msk       (0x3UL << EXTI_D3PCR1L_PCS8_Pos)           /*!< 0x00030000 */

+#define EXTI_D3PCR1L_PCS8           EXTI_D3PCR1L_PCS8_Msk                      /*!< D3 Pending request clear input signal selection on line 8 */

+#define EXTI_D3PCR1L_PCS9_Pos       (18U)

+#define EXTI_D3PCR1L_PCS9_Msk       (0x3UL << EXTI_D3PCR1L_PCS9_Pos)           /*!< 0x000C0000 */

+#define EXTI_D3PCR1L_PCS9           EXTI_D3PCR1L_PCS9_Msk                      /*!< D3 Pending request clear input signal selection on line 9 */

+#define EXTI_D3PCR1L_PCS10_Pos      (20U)

+#define EXTI_D3PCR1L_PCS10_Msk      (0x3UL << EXTI_D3PCR1L_PCS10_Pos)          /*!< 0x00300000 */

+#define EXTI_D3PCR1L_PCS10          EXTI_D3PCR1L_PCS10_Msk                     /*!< D3 Pending request clear input signal selection on line 10*/

+#define EXTI_D3PCR1L_PCS11_Pos      (22U)

+#define EXTI_D3PCR1L_PCS11_Msk      (0x3UL << EXTI_D3PCR1L_PCS11_Pos)          /*!< 0x00C00000 */

+#define EXTI_D3PCR1L_PCS11          EXTI_D3PCR1L_PCS11_Msk                     /*!< D3 Pending request clear input signal selection on line 11*/

+#define EXTI_D3PCR1L_PCS12_Pos      (24U)

+#define EXTI_D3PCR1L_PCS12_Msk      (0x3UL << EXTI_D3PCR1L_PCS12_Pos)          /*!< 0x03000000 */

+#define EXTI_D3PCR1L_PCS12          EXTI_D3PCR1L_PCS12_Msk                     /*!< D3 Pending request clear input signal selection on line 12*/

+#define EXTI_D3PCR1L_PCS13_Pos      (26U)

+#define EXTI_D3PCR1L_PCS13_Msk      (0x3UL << EXTI_D3PCR1L_PCS13_Pos)          /*!< 0x0C000000 */

+#define EXTI_D3PCR1L_PCS13          EXTI_D3PCR1L_PCS13_Msk                     /*!< D3 Pending request clear input signal selection on line 13*/

+#define EXTI_D3PCR1L_PCS14_Pos      (28U)

+#define EXTI_D3PCR1L_PCS14_Msk      (0x3UL << EXTI_D3PCR1L_PCS14_Pos)          /*!< 0x30000000 */

+#define EXTI_D3PCR1L_PCS14          EXTI_D3PCR1L_PCS14_Msk                     /*!< D3 Pending request clear input signal selection on line 14*/

+#define EXTI_D3PCR1L_PCS15_Pos      (30U)

+#define EXTI_D3PCR1L_PCS15_Msk      (0x3UL << EXTI_D3PCR1L_PCS15_Pos)          /*!< 0xC0000000 */

+#define EXTI_D3PCR1L_PCS15          EXTI_D3PCR1L_PCS15_Msk                     /*!< D3 Pending request clear input signal selection on line 15*/

+

+/*******************  Bit definition for EXTI_D3PCR1H register  ****************/

+#define EXTI_D3PCR1H_PCS19_Pos       (6U)

+#define EXTI_D3PCR1H_PCS19_Msk       (0x3UL << EXTI_D3PCR1H_PCS19_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR1H_PCS19           EXTI_D3PCR1H_PCS19_Msk                    /*!< D3 Pending request clear input signal selection on line 19 */

+#define EXTI_D3PCR1H_PCS20_Pos       (8U)

+#define EXTI_D3PCR1H_PCS20_Msk       (0x3UL << EXTI_D3PCR1H_PCS20_Pos)         /*!< 0x00000300 */

+#define EXTI_D3PCR1H_PCS20           EXTI_D3PCR1H_PCS20_Msk                    /*!< D3 Pending request clear input signal selection on line 20 */

+#define EXTI_D3PCR1H_PCS21_Pos       (10U)

+#define EXTI_D3PCR1H_PCS21_Msk       (0x3UL << EXTI_D3PCR1H_PCS21_Pos)         /*!< 0x00000C00 */

+#define EXTI_D3PCR1H_PCS21           EXTI_D3PCR1H_PCS21_Msk                    /*!< D3 Pending request clear input signal selection on line 21 */

+#define EXTI_D3PCR1H_PCS25_Pos       (18U)

+#define EXTI_D3PCR1H_PCS25_Msk       (0x3UL << EXTI_D3PCR1H_PCS25_Pos)         /*!< 0x000C0000 */

+#define EXTI_D3PCR1H_PCS25           EXTI_D3PCR1H_PCS25_Msk                    /*!< D3 Pending request clear input signal selection on line 25 */

+

+/******************  Bit definition for EXTI_RTSR2 register  *******************/

+#define EXTI_RTSR2_TR_Pos          (17U)

+#define EXTI_RTSR2_TR_Msk          (0x5UL << EXTI_RTSR2_TR_Pos)                /*!< 0x000A0000 */

+#define EXTI_RTSR2_TR              EXTI_RTSR2_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR2_TR49_Pos        (17U)

+#define EXTI_RTSR2_TR49_Msk        (0x1UL << EXTI_RTSR2_TR49_Pos)              /*!< 0x00020000 */

+#define EXTI_RTSR2_TR49            EXTI_RTSR2_TR49_Msk                         /*!< Rising trigger event configuration bit of line 49 */

+#define EXTI_RTSR2_TR51_Pos        (19U)

+#define EXTI_RTSR2_TR51_Msk        (0x1UL << EXTI_RTSR2_TR51_Pos)              /*!< 0x00080000 */

+#define EXTI_RTSR2_TR51            EXTI_RTSR2_TR51_Msk                         /*!< Rising trigger event configuration bit of line 51 */

+

+/******************  Bit definition for EXTI_FTSR2 register  *******************/

+#define EXTI_FTSR2_TR_Pos          (17U)

+#define EXTI_FTSR2_TR_Msk          (0x5UL << EXTI_FTSR2_TR_Pos)                /*!< 0x000A0000 */

+#define EXTI_FTSR2_TR              EXTI_FTSR2_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR2_TR49_Pos        (17U)

+#define EXTI_FTSR2_TR49_Msk        (0x1UL << EXTI_FTSR2_TR49_Pos)              /*!< 0x00020000 */

+#define EXTI_FTSR2_TR49            EXTI_FTSR2_TR49_Msk                         /*!< Falling trigger event configuration bit of line 49 */

+#define EXTI_FTSR2_TR51_Pos        (19U)

+#define EXTI_FTSR2_TR51_Msk        (0x1UL << EXTI_FTSR2_TR51_Pos)              /*!< 0x00080000 */

+#define EXTI_FTSR2_TR51            EXTI_FTSR2_TR51_Msk                         /*!< Falling trigger event configuration bit of line 51 */

+

+/******************  Bit definition for EXTI_SWIER2 register  ******************/

+#define EXTI_SWIER2_SWIER49_Pos    (17U)

+#define EXTI_SWIER2_SWIER49_Msk    (0x1UL << EXTI_SWIER2_SWIER49_Pos)          /*!< 0x00020000 */

+#define EXTI_SWIER2_SWIER49        EXTI_SWIER2_SWIER49_Msk                     /*!< Software Interrupt on line 49 */

+#define EXTI_SWIER2_SWIER51_Pos    (19U)

+#define EXTI_SWIER2_SWIER51_Msk    (0x1UL << EXTI_SWIER2_SWIER51_Pos)          /*!< 0x00080000 */

+#define EXTI_SWIER2_SWIER51        EXTI_SWIER2_SWIER51_Msk                     /*!< Software Interrupt on line 51 */

+

+/******************  Bit definition for EXTI_D3PMR2 register  ******************/

+#define EXTI_D3PMR2_MR34_Pos       (2U)

+#define EXTI_D3PMR2_MR34_Msk       (0x1UL << EXTI_D3PMR2_MR34_Pos)             /*!< 0x00000004 */

+#define EXTI_D3PMR2_MR34           EXTI_D3PMR2_MR34_Msk                        /*!< Pending Mask Event for line 34  */

+#define EXTI_D3PMR2_MR35_Pos       (3U)

+#define EXTI_D3PMR2_MR35_Msk       (0x1UL << EXTI_D3PMR2_MR35_Pos)             /*!< 0x00000008 */

+#define EXTI_D3PMR2_MR35           EXTI_D3PMR2_MR35_Msk                        /*!< Pending Mask Event for line 35  */

+#define EXTI_D3PMR2_MR41_Pos       (9U)

+#define EXTI_D3PMR2_MR41_Msk       (0x1UL << EXTI_D3PMR2_MR41_Pos)             /*!< 0x00000200 */

+#define EXTI_D3PMR2_MR41           EXTI_D3PMR2_MR41_Msk                        /*!< Pending Mask Event for line 41  */

+#define EXTI_D3PMR2_MR48_Pos       (16U)

+#define EXTI_D3PMR2_MR48_Msk       (0x1UL << EXTI_D3PMR2_MR48_Pos)             /*!< 0x00010000 */

+#define EXTI_D3PMR2_MR48           EXTI_D3PMR2_MR48_Msk                        /*!< Pending Mask Event for line 48  */

+#define EXTI_D3PMR2_MR49_Pos       (17U)

+#define EXTI_D3PMR2_MR49_Msk       (0x1UL << EXTI_D3PMR2_MR49_Pos)             /*!< 0x00020000 */

+#define EXTI_D3PMR2_MR49           EXTI_D3PMR2_MR49_Msk                        /*!< Pending Mask Event for line 49  */

+#define EXTI_D3PMR2_MR50_Pos       (18U)

+#define EXTI_D3PMR2_MR50_Msk       (0x1UL << EXTI_D3PMR2_MR50_Pos)             /*!< 0x00040000 */

+#define EXTI_D3PMR2_MR50           EXTI_D3PMR2_MR50_Msk                        /*!< Pending Mask Event for line 50  */

+#define EXTI_D3PMR2_MR51_Pos       (19U)

+#define EXTI_D3PMR2_MR51_Msk       (0x1UL << EXTI_D3PMR2_MR51_Pos)             /*!< 0x00080000 */

+#define EXTI_D3PMR2_MR51           EXTI_D3PMR2_MR51_Msk                        /*!< Pending Mask Event for line 51  */

+/*******************  Bit definition for EXTI_D3PCR2L register  ****************/

+#define EXTI_D3PCR2L_PCS34_Pos       (4U)

+#define EXTI_D3PCR2L_PCS34_Msk       (0x3UL << EXTI_D3PCR2L_PCS34_Pos)         /*!< 0x00000030 */

+#define EXTI_D3PCR2L_PCS34           EXTI_D3PCR2L_PCS34_Msk                    /*!< D3 Pending request clear input signal selection on line 34 */

+#define EXTI_D3PCR2L_PCS35_Pos       (6U)

+#define EXTI_D3PCR2L_PCS35_Msk       (0x3UL << EXTI_D3PCR2L_PCS35_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR2L_PCS35           EXTI_D3PCR2L_PCS35_Msk                    /*!< D3 Pending request clear input signal selection on line 35 */

+#define EXTI_D3PCR2L_PCS41_Pos       (18U)

+#define EXTI_D3PCR2L_PCS41_Msk       (0x3UL << EXTI_D3PCR2L_PCS41_Pos)         /*!< 0x000C0000 */

+#define EXTI_D3PCR2L_PCS41           EXTI_D3PCR2L_PCS41_Msk                    /*!< D3 Pending request clear input signal selection on line 41 */

+

+

+/*******************  Bit definition for EXTI_D3PCR2H register  ****************/

+#define EXTI_D3PCR2H_PCS48_Pos       (0U)

+#define EXTI_D3PCR2H_PCS48_Msk       (0x3UL << EXTI_D3PCR2H_PCS48_Pos)         /*!< 0x00000003 */

+#define EXTI_D3PCR2H_PCS48           EXTI_D3PCR2H_PCS48_Msk                    /*!< D3 Pending request clear input signal selection on line 48 */

+#define EXTI_D3PCR2H_PCS49_Pos       (2U)

+#define EXTI_D3PCR2H_PCS49_Msk       (0x3UL << EXTI_D3PCR2H_PCS49_Pos)         /*!< 0x0000000C */

+#define EXTI_D3PCR2H_PCS49           EXTI_D3PCR2H_PCS49_Msk                    /*!< D3 Pending request clear input signal selection on line 49 */

+#define EXTI_D3PCR2H_PCS50_Pos       (4U)

+#define EXTI_D3PCR2H_PCS50_Msk       (0x3UL << EXTI_D3PCR2H_PCS50_Pos)         /*!< 0x00000030 */

+#define EXTI_D3PCR2H_PCS50           EXTI_D3PCR2H_PCS50_Msk                    /*!< D3 Pending request clear input signal selection on line 50 */

+#define EXTI_D3PCR2H_PCS51_Pos       (6U)

+#define EXTI_D3PCR2H_PCS51_Msk       (0x3UL << EXTI_D3PCR2H_PCS51_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR2H_PCS51           EXTI_D3PCR2H_PCS51_Msk                    /*!< D3 Pending request clear input signal selection on line 51 */

+/******************  Bit definition for EXTI_RTSR3 register  *******************/

+#define EXTI_RTSR3_TR_Pos          (18U)

+#define EXTI_RTSR3_TR_Msk          (0x9UL << EXTI_RTSR3_TR_Pos)                /*!< 0x00240000 */

+#define EXTI_RTSR3_TR              EXTI_RTSR3_TR_Msk                           /*!< Rising trigger event configuration bit            */

+#define EXTI_RTSR3_TR82_Pos        (18U)

+#define EXTI_RTSR3_TR82_Msk        (0x1UL << EXTI_RTSR3_TR82_Pos)              /*!< 0x00040000 */

+#define EXTI_RTSR3_TR82            EXTI_RTSR3_TR82_Msk                         /*!< Rising trigger event configuration bit of line 82 */

+#define EXTI_RTSR3_TR85_Pos        (21U)

+#define EXTI_RTSR3_TR85_Msk        (0x1UL << EXTI_RTSR3_TR85_Pos)              /*!< 0x00200000 */

+#define EXTI_RTSR3_TR85            EXTI_RTSR3_TR85_Msk                         /*!< Rising trigger event configuration bit of line 85 */

+

+/******************  Bit definition for EXTI_FTSR3 register  *******************/

+#define EXTI_FTSR3_TR_Pos          (18U)

+#define EXTI_FTSR3_TR_Msk          (0x9UL << EXTI_FTSR3_TR_Pos)                /*!< 0x00240000 */

+#define EXTI_FTSR3_TR              EXTI_FTSR3_TR_Msk                           /*!< Falling trigger event configuration bit            */

+#define EXTI_FTSR3_TR82_Pos        (18U)

+#define EXTI_FTSR3_TR82_Msk        (0x1UL << EXTI_FTSR3_TR82_Pos)              /*!< 0x00040000 */

+#define EXTI_FTSR3_TR82            EXTI_FTSR3_TR82_Msk                         /*!< Falling trigger event configuration bit of line 82 */

+#define EXTI_FTSR3_TR85_Pos        (21U)

+#define EXTI_FTSR3_TR85_Msk        (0x1UL << EXTI_FTSR3_TR85_Pos)              /*!< 0x00200000 */

+#define EXTI_FTSR3_TR85            EXTI_FTSR3_TR85_Msk                         /*!< Falling trigger event configuration bit of line 85 */

+

+/******************  Bit definition for EXTI_SWIER3 register  ******************/

+#define EXTI_SWIER3_SWI_Pos        (18U)

+#define EXTI_SWIER3_SWI_Msk        (0x9UL << EXTI_SWIER3_SWI_Pos)              /*!< 0x00240000 */

+#define EXTI_SWIER3_SWI            EXTI_SWIER3_SWI_Msk                         /*!< Software Interrupt event bit */

+#define EXTI_SWIER3_SWIER82_Pos    (18U)

+#define EXTI_SWIER3_SWIER82_Msk    (0x1UL << EXTI_SWIER3_SWIER82_Pos)          /*!< 0x00040000 */

+#define EXTI_SWIER3_SWIER82        EXTI_SWIER3_SWIER82_Msk                     /*!< Software Interrupt on line 82 */

+#define EXTI_SWIER3_SWIER85_Pos    (21U)

+#define EXTI_SWIER3_SWIER85_Msk    (0x1UL << EXTI_SWIER3_SWIER85_Pos)          /*!< 0x00200000 */

+#define EXTI_SWIER3_SWIER85        EXTI_SWIER3_SWIER85_Msk                     /*!< Software Interrupt on line 85 */

+

+/******************  Bit definition for EXTI_D3PMR3 register  ******************/

+#define EXTI_D3PMR3_MR88_Pos       (24U)

+#define EXTI_D3PMR3_MR88_Msk       (0x1UL << EXTI_D3PMR3_MR88_Pos)             /*!< 0x01000000 */

+#define EXTI_D3PMR3_MR88           EXTI_D3PMR3_MR88_Msk                        /*!< Pending Mask Event for line 88  */

+

+/*******************  Bit definition for EXTI_D3PCR3H register  ****************/

+#define EXTI_D3PCR3H_PCS88_Pos       (16U)

+#define EXTI_D3PCR3H_PCS88_Msk       (0x3UL << EXTI_D3PCR3H_PCS88_Pos)         /*!< 0x00030000 */

+#define EXTI_D3PCR3H_PCS88           EXTI_D3PCR3H_PCS88_Msk                    /*!< D3 Pending request clear input signal selection on line 88 */

+

+/*******************  Bit definition for EXTI_IMR1 register  *******************/

+#define EXTI_IMR1_IM_Pos           (0U)

+#define EXTI_IMR1_IM_Msk           (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)          /*!< 0xFFFFFFFF */

+#define EXTI_IMR1_IM               EXTI_IMR1_IM_Msk                            /*!< Interrupt Mask */

+#define EXTI_IMR1_IM0_Pos          (0U)

+#define EXTI_IMR1_IM0_Msk          (0x1UL << EXTI_IMR1_IM0_Pos)                /*!< 0x00000001 */

+#define EXTI_IMR1_IM0              EXTI_IMR1_IM0_Msk                           /*!< Interrupt Mask on line 0 */

+#define EXTI_IMR1_IM1_Pos          (1U)

+#define EXTI_IMR1_IM1_Msk          (0x1UL << EXTI_IMR1_IM1_Pos)                /*!< 0x00000002 */

+#define EXTI_IMR1_IM1              EXTI_IMR1_IM1_Msk                           /*!< Interrupt Mask on line 1 */

+#define EXTI_IMR1_IM2_Pos          (2U)

+#define EXTI_IMR1_IM2_Msk          (0x1UL << EXTI_IMR1_IM2_Pos)                /*!< 0x00000004 */

+#define EXTI_IMR1_IM2              EXTI_IMR1_IM2_Msk                           /*!< Interrupt Mask on line 2 */

+#define EXTI_IMR1_IM3_Pos          (3U)

+#define EXTI_IMR1_IM3_Msk          (0x1UL << EXTI_IMR1_IM3_Pos)                /*!< 0x00000008 */

+#define EXTI_IMR1_IM3              EXTI_IMR1_IM3_Msk                           /*!< Interrupt Mask on line 3 */

+#define EXTI_IMR1_IM4_Pos          (4U)

+#define EXTI_IMR1_IM4_Msk          (0x1UL << EXTI_IMR1_IM4_Pos)                /*!< 0x00000010 */

+#define EXTI_IMR1_IM4              EXTI_IMR1_IM4_Msk                           /*!< Interrupt Mask on line 4 */

+#define EXTI_IMR1_IM5_Pos          (5U)

+#define EXTI_IMR1_IM5_Msk          (0x1UL << EXTI_IMR1_IM5_Pos)                /*!< 0x00000020 */

+#define EXTI_IMR1_IM5              EXTI_IMR1_IM5_Msk                           /*!< Interrupt Mask on line 5 */

+#define EXTI_IMR1_IM6_Pos          (6U)

+#define EXTI_IMR1_IM6_Msk          (0x1UL << EXTI_IMR1_IM6_Pos)                /*!< 0x00000040 */

+#define EXTI_IMR1_IM6              EXTI_IMR1_IM6_Msk                           /*!< Interrupt Mask on line 6 */

+#define EXTI_IMR1_IM7_Pos          (7U)

+#define EXTI_IMR1_IM7_Msk          (0x1UL << EXTI_IMR1_IM7_Pos)                /*!< 0x00000080 */

+#define EXTI_IMR1_IM7              EXTI_IMR1_IM7_Msk                           /*!< Interrupt Mask on line 7 */

+#define EXTI_IMR1_IM8_Pos          (8U)

+#define EXTI_IMR1_IM8_Msk          (0x1UL << EXTI_IMR1_IM8_Pos)                /*!< 0x00000100 */

+#define EXTI_IMR1_IM8              EXTI_IMR1_IM8_Msk                           /*!< Interrupt Mask on line 8 */

+#define EXTI_IMR1_IM9_Pos          (9U)

+#define EXTI_IMR1_IM9_Msk          (0x1UL << EXTI_IMR1_IM9_Pos)                /*!< 0x00000200 */

+#define EXTI_IMR1_IM9              EXTI_IMR1_IM9_Msk                           /*!< Interrupt Mask on line 9 */

+#define EXTI_IMR1_IM10_Pos         (10U)

+#define EXTI_IMR1_IM10_Msk         (0x1UL << EXTI_IMR1_IM10_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR1_IM10             EXTI_IMR1_IM10_Msk                          /*!< Interrupt Mask on line 10 */

+#define EXTI_IMR1_IM11_Pos         (11U)

+#define EXTI_IMR1_IM11_Msk         (0x1UL << EXTI_IMR1_IM11_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR1_IM11             EXTI_IMR1_IM11_Msk                          /*!< Interrupt Mask on line 11 */

+#define EXTI_IMR1_IM12_Pos         (12U)

+#define EXTI_IMR1_IM12_Msk         (0x1UL << EXTI_IMR1_IM12_Pos)               /*!< 0x00001000 */

+#define EXTI_IMR1_IM12             EXTI_IMR1_IM12_Msk                          /*!< Interrupt Mask on line 12 */

+#define EXTI_IMR1_IM13_Pos         (13U)

+#define EXTI_IMR1_IM13_Msk         (0x1UL << EXTI_IMR1_IM13_Pos)               /*!< 0x00002000 */

+#define EXTI_IMR1_IM13             EXTI_IMR1_IM13_Msk                          /*!< Interrupt Mask on line 13 */

+#define EXTI_IMR1_IM14_Pos         (14U)

+#define EXTI_IMR1_IM14_Msk         (0x1UL << EXTI_IMR1_IM14_Pos)               /*!< 0x00004000 */

+#define EXTI_IMR1_IM14             EXTI_IMR1_IM14_Msk                          /*!< Interrupt Mask on line 14 */

+#define EXTI_IMR1_IM15_Pos         (15U)

+#define EXTI_IMR1_IM15_Msk         (0x1UL << EXTI_IMR1_IM15_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR1_IM15             EXTI_IMR1_IM15_Msk                          /*!< Interrupt Mask on line 15 */

+#define EXTI_IMR1_IM16_Pos         (16U)

+#define EXTI_IMR1_IM16_Msk         (0x1UL << EXTI_IMR1_IM16_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR1_IM16             EXTI_IMR1_IM16_Msk                          /*!< Interrupt Mask on line 16 */

+#define EXTI_IMR1_IM17_Pos         (17U)

+#define EXTI_IMR1_IM17_Msk         (0x1UL << EXTI_IMR1_IM17_Pos)               /*!< 0x00020000 */

+#define EXTI_IMR1_IM17             EXTI_IMR1_IM17_Msk                          /*!< Interrupt Mask on line 17 */

+#define EXTI_IMR1_IM18_Pos         (18U)

+#define EXTI_IMR1_IM18_Msk         (0x1UL << EXTI_IMR1_IM18_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR1_IM18             EXTI_IMR1_IM18_Msk                          /*!< Interrupt Mask on line 18 */

+#define EXTI_IMR1_IM19_Pos         (19U)

+#define EXTI_IMR1_IM19_Msk         (0x1UL << EXTI_IMR1_IM19_Pos)               /*!< 0x00080000 */

+#define EXTI_IMR1_IM19             EXTI_IMR1_IM19_Msk                          /*!< Interrupt Mask on line 19 */

+#define EXTI_IMR1_IM20_Pos         (20U)

+#define EXTI_IMR1_IM20_Msk         (0x1UL << EXTI_IMR1_IM20_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR1_IM20             EXTI_IMR1_IM20_Msk                          /*!< Interrupt Mask on line 20 */

+#define EXTI_IMR1_IM21_Pos         (21U)

+#define EXTI_IMR1_IM21_Msk         (0x1UL << EXTI_IMR1_IM21_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR1_IM21             EXTI_IMR1_IM21_Msk                          /*!< Interrupt Mask on line 21 */

+#define EXTI_IMR1_IM22_Pos         (22U)

+#define EXTI_IMR1_IM22_Msk         (0x1UL << EXTI_IMR1_IM22_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR1_IM22             EXTI_IMR1_IM22_Msk                          /*!< Interrupt Mask on line 22 */

+#define EXTI_IMR1_IM23_Pos         (23U)

+#define EXTI_IMR1_IM23_Msk         (0x1UL << EXTI_IMR1_IM23_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR1_IM23             EXTI_IMR1_IM23_Msk                          /*!< Interrupt Mask on line 23 */

+#define EXTI_IMR1_IM24_Pos         (24U)

+#define EXTI_IMR1_IM24_Msk         (0x1UL << EXTI_IMR1_IM24_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR1_IM24             EXTI_IMR1_IM24_Msk                          /*!< Interrupt Mask on line 24 */

+#define EXTI_IMR1_IM25_Pos         (25U)

+#define EXTI_IMR1_IM25_Msk         (0x1UL << EXTI_IMR1_IM25_Pos)               /*!< 0x02000000 */

+#define EXTI_IMR1_IM25             EXTI_IMR1_IM25_Msk                          /*!< Interrupt Mask on line 25 */

+#define EXTI_IMR1_IM26_Pos         (26U)

+#define EXTI_IMR1_IM26_Msk         (0x1UL << EXTI_IMR1_IM26_Pos)               /*!< 0x04000000 */

+#define EXTI_IMR1_IM26             EXTI_IMR1_IM26_Msk                          /*!< Interrupt Mask on line 26 */

+#define EXTI_IMR1_IM27_Pos         (27U)

+#define EXTI_IMR1_IM27_Msk         (0x1UL << EXTI_IMR1_IM27_Pos)               /*!< 0x08000000 */

+#define EXTI_IMR1_IM27             EXTI_IMR1_IM27_Msk                          /*!< Interrupt Mask on line 27 */

+#define EXTI_IMR1_IM28_Pos         (28U)

+#define EXTI_IMR1_IM28_Msk         (0x1UL << EXTI_IMR1_IM28_Pos)               /*!< 0x10000000 */

+#define EXTI_IMR1_IM28             EXTI_IMR1_IM28_Msk                          /*!< Interrupt Mask on line 28 */

+#define EXTI_IMR1_IM29_Pos         (29U)

+#define EXTI_IMR1_IM29_Msk         (0x1UL << EXTI_IMR1_IM29_Pos)               /*!< 0x20000000 */

+#define EXTI_IMR1_IM29             EXTI_IMR1_IM29_Msk                          /*!< Interrupt Mask on line 29 */

+#define EXTI_IMR1_IM30_Pos         (30U)

+#define EXTI_IMR1_IM30_Msk         (0x1UL << EXTI_IMR1_IM30_Pos)               /*!< 0x40000000 */

+#define EXTI_IMR1_IM30             EXTI_IMR1_IM30_Msk                          /*!< Interrupt Mask on line 30 */

+#define EXTI_IMR1_IM31_Pos         (31U)

+#define EXTI_IMR1_IM31_Msk         (0x1UL << EXTI_IMR1_IM31_Pos)               /*!< 0x80000000 */

+#define EXTI_IMR1_IM31             EXTI_IMR1_IM31_Msk                          /*!< Interrupt Mask on line 31 */

+

+/*******************  Bit definition for EXTI_EMR1 register  *******************/

+#define EXTI_EMR1_EM_Pos           (0U)

+#define EXTI_EMR1_EM_Msk           (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)          /*!< 0xFFFFFFFF */

+#define EXTI_EMR1_EM               EXTI_EMR1_EM_Msk                            /*!< Event Mask */

+#define EXTI_EMR1_EM0_Pos          (0U)

+#define EXTI_EMR1_EM0_Msk          (0x1UL << EXTI_EMR1_EM0_Pos)                /*!< 0x00000001 */

+#define EXTI_EMR1_EM0              EXTI_EMR1_EM0_Msk                           /*!< Event Mask on line 0 */

+#define EXTI_EMR1_EM1_Pos          (1U)

+#define EXTI_EMR1_EM1_Msk          (0x1UL << EXTI_EMR1_EM1_Pos)                /*!< 0x00000002 */

+#define EXTI_EMR1_EM1              EXTI_EMR1_EM1_Msk                           /*!< Event Mask on line 1 */

+#define EXTI_EMR1_EM2_Pos          (2U)

+#define EXTI_EMR1_EM2_Msk          (0x1UL << EXTI_EMR1_EM2_Pos)                /*!< 0x00000004 */

+#define EXTI_EMR1_EM2              EXTI_EMR1_EM2_Msk                           /*!< Event Mask on line 2 */

+#define EXTI_EMR1_EM3_Pos          (3U)

+#define EXTI_EMR1_EM3_Msk          (0x1UL << EXTI_EMR1_EM3_Pos)                /*!< 0x00000008 */

+#define EXTI_EMR1_EM3              EXTI_EMR1_EM3_Msk                           /*!< Event Mask on line 3 */

+#define EXTI_EMR1_EM4_Pos          (4U)

+#define EXTI_EMR1_EM4_Msk          (0x1UL << EXTI_EMR1_EM4_Pos)                /*!< 0x00000010 */

+#define EXTI_EMR1_EM4              EXTI_EMR1_EM4_Msk                           /*!< Event Mask on line 4 */

+#define EXTI_EMR1_EM5_Pos          (5U)

+#define EXTI_EMR1_EM5_Msk          (0x1UL << EXTI_EMR1_EM5_Pos)                /*!< 0x00000020 */

+#define EXTI_EMR1_EM5              EXTI_EMR1_EM5_Msk                           /*!< Event Mask on line 5 */

+#define EXTI_EMR1_EM6_Pos          (6U)

+#define EXTI_EMR1_EM6_Msk          (0x1UL << EXTI_EMR1_EM6_Pos)                /*!< 0x00000040 */

+#define EXTI_EMR1_EM6              EXTI_EMR1_EM6_Msk                           /*!< Event Mask on line 6 */

+#define EXTI_EMR1_EM7_Pos          (7U)

+#define EXTI_EMR1_EM7_Msk          (0x1UL << EXTI_EMR1_EM7_Pos)                /*!< 0x00000080 */

+#define EXTI_EMR1_EM7              EXTI_EMR1_EM7_Msk                           /*!< Event Mask on line 7 */

+#define EXTI_EMR1_EM8_Pos          (8U)

+#define EXTI_EMR1_EM8_Msk          (0x1UL << EXTI_EMR1_EM8_Pos)                /*!< 0x00000100 */

+#define EXTI_EMR1_EM8              EXTI_EMR1_EM8_Msk                           /*!< Event Mask on line 8 */

+#define EXTI_EMR1_EM9_Pos          (9U)

+#define EXTI_EMR1_EM9_Msk          (0x1UL << EXTI_EMR1_EM9_Pos)                /*!< 0x00000200 */

+#define EXTI_EMR1_EM9              EXTI_EMR1_EM9_Msk                           /*!< Event Mask on line 9 */

+#define EXTI_EMR1_EM10_Pos         (10U)

+#define EXTI_EMR1_EM10_Msk         (0x1UL << EXTI_EMR1_EM10_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR1_EM10             EXTI_EMR1_EM10_Msk                          /*!< Event Mask on line 10 */

+#define EXTI_EMR1_EM11_Pos         (11U)

+#define EXTI_EMR1_EM11_Msk         (0x1UL << EXTI_EMR1_EM11_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR1_EM11             EXTI_EMR1_EM11_Msk                          /*!< Event Mask on line 11 */

+#define EXTI_EMR1_EM12_Pos         (12U)

+#define EXTI_EMR1_EM12_Msk         (0x1UL << EXTI_EMR1_EM12_Pos)               /*!< 0x00001000 */

+#define EXTI_EMR1_EM12             EXTI_EMR1_EM12_Msk                          /*!< Event Mask on line 12 */

+#define EXTI_EMR1_EM13_Pos         (13U)

+#define EXTI_EMR1_EM13_Msk         (0x1UL << EXTI_EMR1_EM13_Pos)               /*!< 0x00002000 */

+#define EXTI_EMR1_EM13             EXTI_EMR1_EM13_Msk                          /*!< Event Mask on line 13 */

+#define EXTI_EMR1_EM14_Pos         (14U)

+#define EXTI_EMR1_EM14_Msk         (0x1UL << EXTI_EMR1_EM14_Pos)               /*!< 0x00004000 */

+#define EXTI_EMR1_EM14             EXTI_EMR1_EM14_Msk                          /*!< Event Mask on line 14 */

+#define EXTI_EMR1_EM15_Pos         (15U)

+#define EXTI_EMR1_EM15_Msk         (0x1UL << EXTI_EMR1_EM15_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR1_EM15             EXTI_EMR1_EM15_Msk                          /*!< Event Mask on line 15 */

+#define EXTI_EMR1_EM16_Pos         (16U)

+#define EXTI_EMR1_EM16_Msk         (0x1UL << EXTI_EMR1_EM16_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR1_EM16             EXTI_EMR1_EM16_Msk                          /*!< Event Mask on line 16 */

+#define EXTI_EMR1_EM17_Pos         (17U)

+#define EXTI_EMR1_EM17_Msk         (0x1UL << EXTI_EMR1_EM17_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR1_EM17             EXTI_EMR1_EM17_Msk                          /*!< Event Mask on line 17 */

+#define EXTI_EMR1_EM18_Pos         (18U)

+#define EXTI_EMR1_EM18_Msk         (0x1UL << EXTI_EMR1_EM18_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR1_EM18             EXTI_EMR1_EM18_Msk                          /*!< Event Mask on line 18 */

+#define EXTI_EMR1_EM20_Pos         (20U)

+#define EXTI_EMR1_EM20_Msk         (0x1UL << EXTI_EMR1_EM20_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR1_EM20             EXTI_EMR1_EM20_Msk                          /*!< Event Mask on line 20 */

+#define EXTI_EMR1_EM21_Pos         (21U)

+#define EXTI_EMR1_EM21_Msk         (0x1UL << EXTI_EMR1_EM21_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR1_EM21             EXTI_EMR1_EM21_Msk                          /*!< Event Mask on line 21 */

+#define EXTI_EMR1_EM22_Pos         (22U)

+#define EXTI_EMR1_EM22_Msk         (0x1UL << EXTI_EMR1_EM22_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR1_EM22             EXTI_EMR1_EM22_Msk                          /*!< Event Mask on line 22 */

+#define EXTI_EMR1_EM23_Pos         (23U)

+#define EXTI_EMR1_EM23_Msk         (0x1UL << EXTI_EMR1_EM23_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR1_EM23             EXTI_EMR1_EM23_Msk                          /*!< Event Mask on line 23 */

+#define EXTI_EMR1_EM24_Pos         (24U)

+#define EXTI_EMR1_EM24_Msk         (0x1UL << EXTI_EMR1_EM24_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR1_EM24             EXTI_EMR1_EM24_Msk                          /*!< Event Mask on line 24 */

+#define EXTI_EMR1_EM25_Pos         (25U)

+#define EXTI_EMR1_EM25_Msk         (0x1UL << EXTI_EMR1_EM25_Pos)               /*!< 0x02000000 */

+#define EXTI_EMR1_EM25             EXTI_EMR1_EM25_Msk                          /*!< Event Mask on line 25 */

+#define EXTI_EMR1_EM26_Pos         (26U)

+#define EXTI_EMR1_EM26_Msk         (0x1UL << EXTI_EMR1_EM26_Pos)               /*!< 0x04000000 */

+#define EXTI_EMR1_EM26             EXTI_EMR1_EM26_Msk                          /*!< Event Mask on line 26 */

+#define EXTI_EMR1_EM27_Pos         (27U)

+#define EXTI_EMR1_EM27_Msk         (0x1UL << EXTI_EMR1_EM27_Pos)               /*!< 0x08000000 */

+#define EXTI_EMR1_EM27             EXTI_EMR1_EM27_Msk                          /*!< Event Mask on line 27 */

+#define EXTI_EMR1_EM28_Pos         (28U)

+#define EXTI_EMR1_EM28_Msk         (0x1UL << EXTI_EMR1_EM28_Pos)               /*!< 0x10000000 */

+#define EXTI_EMR1_EM28             EXTI_EMR1_EM28_Msk                          /*!< Event Mask on line 28 */

+#define EXTI_EMR1_EM29_Pos         (29U)

+#define EXTI_EMR1_EM29_Msk         (0x1UL << EXTI_EMR1_EM29_Pos)               /*!< 0x20000000 */

+#define EXTI_EMR1_EM29             EXTI_EMR1_EM29_Msk                          /*!< Event Mask on line 29 */

+#define EXTI_EMR1_EM30_Pos         (30U)

+#define EXTI_EMR1_EM30_Msk         (0x1UL << EXTI_EMR1_EM30_Pos)               /*!< 0x40000000 */

+#define EXTI_EMR1_EM30             EXTI_EMR1_EM30_Msk                          /*!< Event Mask on line 30 */

+#define EXTI_EMR1_EM31_Pos         (31U)

+#define EXTI_EMR1_EM31_Msk         (0x1UL << EXTI_EMR1_EM31_Pos)               /*!< 0x80000000 */

+#define EXTI_EMR1_EM31             EXTI_EMR1_EM31_Msk                          /*!< Event Mask on line 31 */

+

+/*******************  Bit definition for EXTI_PR1 register  ********************/

+#define EXTI_PR1_PR_Pos            (0U)

+#define EXTI_PR1_PR_Msk            (0x3FFFFFUL << EXTI_PR1_PR_Pos)             /*!< 0x003FFFFF */

+#define EXTI_PR1_PR                EXTI_PR1_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR1_PR0_Pos           (0U)

+#define EXTI_PR1_PR0_Msk           (0x1UL << EXTI_PR1_PR0_Pos)                 /*!< 0x00000001 */

+#define EXTI_PR1_PR0               EXTI_PR1_PR0_Msk                            /*!< Pending bit for line 0 */

+#define EXTI_PR1_PR1_Pos           (1U)

+#define EXTI_PR1_PR1_Msk           (0x1UL << EXTI_PR1_PR1_Pos)                 /*!< 0x00000002 */

+#define EXTI_PR1_PR1               EXTI_PR1_PR1_Msk                            /*!< Pending bit for line 1 */

+#define EXTI_PR1_PR2_Pos           (2U)

+#define EXTI_PR1_PR2_Msk           (0x1UL << EXTI_PR1_PR2_Pos)                 /*!< 0x00000004 */

+#define EXTI_PR1_PR2               EXTI_PR1_PR2_Msk                            /*!< Pending bit for line 2 */

+#define EXTI_PR1_PR3_Pos           (3U)

+#define EXTI_PR1_PR3_Msk           (0x1UL << EXTI_PR1_PR3_Pos)                 /*!< 0x00000008 */

+#define EXTI_PR1_PR3               EXTI_PR1_PR3_Msk                            /*!< Pending bit for line 3 */

+#define EXTI_PR1_PR4_Pos           (4U)

+#define EXTI_PR1_PR4_Msk           (0x1UL << EXTI_PR1_PR4_Pos)                 /*!< 0x00000010 */

+#define EXTI_PR1_PR4               EXTI_PR1_PR4_Msk                            /*!< Pending bit for line 4 */

+#define EXTI_PR1_PR5_Pos           (5U)

+#define EXTI_PR1_PR5_Msk           (0x1UL << EXTI_PR1_PR5_Pos)                 /*!< 0x00000020 */

+#define EXTI_PR1_PR5               EXTI_PR1_PR5_Msk                            /*!< Pending bit for line 5 */

+#define EXTI_PR1_PR6_Pos           (6U)

+#define EXTI_PR1_PR6_Msk           (0x1UL << EXTI_PR1_PR6_Pos)                 /*!< 0x00000040 */

+#define EXTI_PR1_PR6               EXTI_PR1_PR6_Msk                            /*!< Pending bit for line 6 */

+#define EXTI_PR1_PR7_Pos           (7U)

+#define EXTI_PR1_PR7_Msk           (0x1UL << EXTI_PR1_PR7_Pos)                 /*!< 0x00000080 */

+#define EXTI_PR1_PR7               EXTI_PR1_PR7_Msk                            /*!< Pending bit for line 7 */

+#define EXTI_PR1_PR8_Pos           (8U)

+#define EXTI_PR1_PR8_Msk           (0x1UL << EXTI_PR1_PR8_Pos)                 /*!< 0x00000100 */

+#define EXTI_PR1_PR8               EXTI_PR1_PR8_Msk                            /*!< Pending bit for line 8 */

+#define EXTI_PR1_PR9_Pos           (9U)

+#define EXTI_PR1_PR9_Msk           (0x1UL << EXTI_PR1_PR9_Pos)                 /*!< 0x00000200 */

+#define EXTI_PR1_PR9               EXTI_PR1_PR9_Msk                            /*!< Pending bit for line 9 */

+#define EXTI_PR1_PR10_Pos          (10U)

+#define EXTI_PR1_PR10_Msk          (0x1UL << EXTI_PR1_PR10_Pos)                /*!< 0x00000400 */

+#define EXTI_PR1_PR10              EXTI_PR1_PR10_Msk                           /*!< Pending bit for line 10 */

+#define EXTI_PR1_PR11_Pos          (11U)

+#define EXTI_PR1_PR11_Msk          (0x1UL << EXTI_PR1_PR11_Pos)                /*!< 0x00000800 */

+#define EXTI_PR1_PR11              EXTI_PR1_PR11_Msk                           /*!< Pending bit for line 11 */

+#define EXTI_PR1_PR12_Pos          (12U)

+#define EXTI_PR1_PR12_Msk          (0x1UL << EXTI_PR1_PR12_Pos)                /*!< 0x00001000 */

+#define EXTI_PR1_PR12              EXTI_PR1_PR12_Msk                           /*!< Pending bit for line 12 */

+#define EXTI_PR1_PR13_Pos          (13U)

+#define EXTI_PR1_PR13_Msk          (0x1UL << EXTI_PR1_PR13_Pos)                /*!< 0x00002000 */

+#define EXTI_PR1_PR13              EXTI_PR1_PR13_Msk                           /*!< Pending bit for line 13 */

+#define EXTI_PR1_PR14_Pos          (14U)

+#define EXTI_PR1_PR14_Msk          (0x1UL << EXTI_PR1_PR14_Pos)                /*!< 0x00004000 */

+#define EXTI_PR1_PR14              EXTI_PR1_PR14_Msk                           /*!< Pending bit for line 14 */

+#define EXTI_PR1_PR15_Pos          (15U)

+#define EXTI_PR1_PR15_Msk          (0x1UL << EXTI_PR1_PR15_Pos)                /*!< 0x00008000 */

+#define EXTI_PR1_PR15              EXTI_PR1_PR15_Msk                           /*!< Pending bit for line 15 */

+#define EXTI_PR1_PR16_Pos          (16U)

+#define EXTI_PR1_PR16_Msk          (0x1UL << EXTI_PR1_PR16_Pos)                /*!< 0x00010000 */

+#define EXTI_PR1_PR16              EXTI_PR1_PR16_Msk                           /*!< Pending bit for line 16 */

+#define EXTI_PR1_PR17_Pos          (17U)

+#define EXTI_PR1_PR17_Msk          (0x1UL << EXTI_PR1_PR17_Pos)                /*!< 0x00020000 */

+#define EXTI_PR1_PR17              EXTI_PR1_PR17_Msk                           /*!< Pending bit for line 17 */

+#define EXTI_PR1_PR18_Pos          (18U)

+#define EXTI_PR1_PR18_Msk          (0x1UL << EXTI_PR1_PR18_Pos)                /*!< 0x00040000 */

+#define EXTI_PR1_PR18              EXTI_PR1_PR18_Msk                           /*!< Pending bit for line 18 */

+#define EXTI_PR1_PR19_Pos          (19U)

+#define EXTI_PR1_PR19_Msk          (0x1UL << EXTI_PR1_PR19_Pos)                /*!< 0x00080000 */

+#define EXTI_PR1_PR19              EXTI_PR1_PR19_Msk                           /*!< Pending bit for line 19 */

+#define EXTI_PR1_PR20_Pos          (20U)

+#define EXTI_PR1_PR20_Msk          (0x1UL << EXTI_PR1_PR20_Pos)                /*!< 0x00100000 */

+#define EXTI_PR1_PR20              EXTI_PR1_PR20_Msk                           /*!< Pending bit for line 20 */

+#define EXTI_PR1_PR21_Pos          (21U)

+#define EXTI_PR1_PR21_Msk          (0x1UL << EXTI_PR1_PR21_Pos)                /*!< 0x00200000 */

+#define EXTI_PR1_PR21              EXTI_PR1_PR21_Msk                           /*!< Pending bit for line 21 */

+

+/*******************  Bit definition for EXTI_IMR2 register  *******************/

+#define EXTI_IMR2_IM_Pos           (0U)

+#define EXTI_IMR2_IM_Msk           (0xFFFF8FFFUL << EXTI_IMR2_IM_Pos)          /*!< 0xFFFF8FFF */

+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            /*!< Interrupt Mask            */

+#define EXTI_IMR2_IM32_Pos         (0U)

+#define EXTI_IMR2_IM32_Msk         (0x1UL << EXTI_IMR2_IM32_Pos)               /*!< 0x00000001 */

+#define EXTI_IMR2_IM32             EXTI_IMR2_IM32_Msk                          /*!< Interrupt Mask on line 32 */

+#define EXTI_IMR2_IM33_Pos         (1U)

+#define EXTI_IMR2_IM33_Msk         (0x1UL << EXTI_IMR2_IM33_Pos)               /*!< 0x00000002 */

+#define EXTI_IMR2_IM33             EXTI_IMR2_IM33_Msk                          /*!< Interrupt Mask on line 33 */

+#define EXTI_IMR2_IM34_Pos         (2U)

+#define EXTI_IMR2_IM34_Msk         (0x1UL << EXTI_IMR2_IM34_Pos)               /*!< 0x00000004 */

+#define EXTI_IMR2_IM34             EXTI_IMR2_IM34_Msk                          /*!< Interrupt Mask on line 34 */

+#define EXTI_IMR2_IM35_Pos         (3U)

+#define EXTI_IMR2_IM35_Msk         (0x1UL << EXTI_IMR2_IM35_Pos)               /*!< 0x00000008 */

+#define EXTI_IMR2_IM35             EXTI_IMR2_IM35_Msk                          /*!< Interrupt Mask on line 35 */

+#define EXTI_IMR2_IM36_Pos         (4U)

+#define EXTI_IMR2_IM36_Msk         (0x1UL << EXTI_IMR2_IM36_Pos)               /*!< 0x00000010 */

+#define EXTI_IMR2_IM36             EXTI_IMR2_IM36_Msk                          /*!< Interrupt Mask on line 36 */

+#define EXTI_IMR2_IM37_Pos         (5U)

+#define EXTI_IMR2_IM37_Msk         (0x1UL << EXTI_IMR2_IM37_Pos)               /*!< 0x00000020 */

+#define EXTI_IMR2_IM37             EXTI_IMR2_IM37_Msk                          /*!< Interrupt Mask on line 37 */

+#define EXTI_IMR2_IM38_Pos         (6U)

+#define EXTI_IMR2_IM38_Msk         (0x1UL << EXTI_IMR2_IM38_Pos)               /*!< 0x00000040 */

+#define EXTI_IMR2_IM38             EXTI_IMR2_IM38_Msk                          /*!< Interrupt Mask on line 38 */

+#define EXTI_IMR2_IM39_Pos         (7U)

+#define EXTI_IMR2_IM39_Msk         (0x1UL << EXTI_IMR2_IM39_Pos)               /*!< 0x00000080 */

+#define EXTI_IMR2_IM39             EXTI_IMR2_IM39_Msk                          /*!< Interrupt Mask on line 39 */

+#define EXTI_IMR2_IM40_Pos         (8U)

+#define EXTI_IMR2_IM40_Msk         (0x1UL << EXTI_IMR2_IM40_Pos)               /*!< 0x00000100 */

+#define EXTI_IMR2_IM40             EXTI_IMR2_IM40_Msk                          /*!< Interrupt Mask on line 40 */

+#define EXTI_IMR2_IM41_Pos         (9U)

+#define EXTI_IMR2_IM41_Msk         (0x1UL << EXTI_IMR2_IM41_Pos)               /*!< 0x00000200 */

+#define EXTI_IMR2_IM41             EXTI_IMR2_IM41_Msk                          /*!< Interrupt Mask on line 41 */

+#define EXTI_IMR2_IM42_Pos         (10U)

+#define EXTI_IMR2_IM42_Msk         (0x1UL << EXTI_IMR2_IM42_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR2_IM42             EXTI_IMR2_IM42_Msk                          /*!< Interrupt Mask on line 42 */

+#define EXTI_IMR2_IM43_Pos         (11U)

+#define EXTI_IMR2_IM43_Msk         (0x1UL << EXTI_IMR2_IM43_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR2_IM43             EXTI_IMR2_IM43_Msk                          /*!< Interrupt Mask on line 43 */

+#define EXTI_IMR2_IM47_Pos         (15U)

+#define EXTI_IMR2_IM47_Msk         (0x1UL << EXTI_IMR2_IM47_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR2_IM47             EXTI_IMR2_IM47_Msk                          /*!< Interrupt Mask on line 47 */

+#define EXTI_IMR2_IM48_Pos         (16U)

+#define EXTI_IMR2_IM48_Msk         (0x1UL << EXTI_IMR2_IM48_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR2_IM48             EXTI_IMR2_IM48_Msk                          /*!< Interrupt Mask on line 48 */

+#define EXTI_IMR2_IM49_Pos         (17U)

+#define EXTI_IMR2_IM49_Msk         (0x1UL << EXTI_IMR2_IM49_Pos)               /*!< 0x00020000 */

+#define EXTI_IMR2_IM49             EXTI_IMR2_IM49_Msk                          /*!< Interrupt Mask on line 49 */

+#define EXTI_IMR2_IM50_Pos         (18U)

+#define EXTI_IMR2_IM50_Msk         (0x1UL << EXTI_IMR2_IM50_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR2_IM50             EXTI_IMR2_IM50_Msk                          /*!< Interrupt Mask on line 50 */

+#define EXTI_IMR2_IM51_Pos         (19U)

+#define EXTI_IMR2_IM51_Msk         (0x1UL << EXTI_IMR2_IM51_Pos)               /*!< 0x00080000 */

+#define EXTI_IMR2_IM51             EXTI_IMR2_IM51_Msk                          /*!< Interrupt Mask on line 51 */

+#define EXTI_IMR2_IM52_Pos         (20U)

+#define EXTI_IMR2_IM52_Msk         (0x1UL << EXTI_IMR2_IM52_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR2_IM52             EXTI_IMR2_IM52_Msk                          /*!< Interrupt Mask on line 52 */

+#define EXTI_IMR2_IM53_Pos         (21U)

+#define EXTI_IMR2_IM53_Msk         (0x1UL << EXTI_IMR2_IM53_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR2_IM53             EXTI_IMR2_IM53_Msk                          /*!< Interrupt Mask on line 53 */

+#define EXTI_IMR2_IM54_Pos         (22U)

+#define EXTI_IMR2_IM54_Msk         (0x1UL << EXTI_IMR2_IM54_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR2_IM54             EXTI_IMR2_IM54_Msk                          /*!< Interrupt Mask on line 54 */

+#define EXTI_IMR2_IM55_Pos         (23U)

+#define EXTI_IMR2_IM55_Msk         (0x1UL << EXTI_IMR2_IM55_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR2_IM55             EXTI_IMR2_IM55_Msk                          /*!< Interrupt Mask on line 55 */

+#define EXTI_IMR2_IM56_Pos         (24U)

+#define EXTI_IMR2_IM56_Msk         (0x1UL << EXTI_IMR2_IM56_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR2_IM56             EXTI_IMR2_IM56_Msk                          /*!< Interrupt Mask on line 56 */

+#define EXTI_IMR2_IM57_Pos         (25U)

+#define EXTI_IMR2_IM57_Msk         (0x1UL << EXTI_IMR2_IM57_Pos)               /*!< 0x02000000 */

+#define EXTI_IMR2_IM57             EXTI_IMR2_IM57_Msk                          /*!< Interrupt Mask on line 57 */

+#define EXTI_IMR2_IM58_Pos         (26U)

+#define EXTI_IMR2_IM58_Msk         (0x1UL << EXTI_IMR2_IM58_Pos)               /*!< 0x04000000 */

+#define EXTI_IMR2_IM58             EXTI_IMR2_IM58_Msk                          /*!< Interrupt Mask on line 58 */

+#define EXTI_IMR2_IM59_Pos         (27U)

+#define EXTI_IMR2_IM59_Msk         (0x1UL << EXTI_IMR2_IM59_Pos)               /*!< 0x08000000 */

+#define EXTI_IMR2_IM59             EXTI_IMR2_IM59_Msk                          /*!< Interrupt Mask on line 59 */

+#define EXTI_IMR2_IM60_Pos         (28U)

+#define EXTI_IMR2_IM60_Msk         (0x1UL << EXTI_IMR2_IM60_Pos)               /*!< 0x10000000 */

+#define EXTI_IMR2_IM60             EXTI_IMR2_IM60_Msk                          /*!< Interrupt Mask on line 60 */

+#define EXTI_IMR2_IM61_Pos         (29U)

+#define EXTI_IMR2_IM61_Msk         (0x1UL << EXTI_IMR2_IM61_Pos)               /*!< 0x20000000 */

+#define EXTI_IMR2_IM61             EXTI_IMR2_IM61_Msk                          /*!< Interrupt Mask on line 61 */

+#define EXTI_IMR2_IM62_Pos         (30U)

+#define EXTI_IMR2_IM62_Msk         (0x1UL << EXTI_IMR2_IM62_Pos)               /*!< 0x40000000 */

+#define EXTI_IMR2_IM62             EXTI_IMR2_IM62_Msk                          /*!< Interrupt Mask on line 62 */

+#define EXTI_IMR2_IM63_Pos         (31U)

+#define EXTI_IMR2_IM63_Msk         (0x1UL << EXTI_IMR2_IM63_Pos)               /*!< 0x80000000 */

+#define EXTI_IMR2_IM63             EXTI_IMR2_IM63_Msk                          /*!< Interrupt Mask on line 63 */

+

+/*******************  Bit definition for EXTI_EMR2 register  *******************/

+#define EXTI_EMR2_EM_Pos           (0U)

+#define EXTI_EMR2_EM_Msk           (0xFFFF8FFFUL << EXTI_EMR2_EM_Pos)          /*!< 0xFFFF8FFF */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            /*!< Event Mask           */

+#define EXTI_EMR2_EM32_Pos         (0U)

+#define EXTI_EMR2_EM32_Msk         (0x1UL << EXTI_EMR2_EM32_Pos)               /*!< 0x00000001 */

+#define EXTI_EMR2_EM32             EXTI_EMR2_EM32_Msk                          /*!< Event Mask on line 32*/

+#define EXTI_EMR2_EM33_Pos         (1U)

+#define EXTI_EMR2_EM33_Msk         (0x1UL << EXTI_EMR2_EM33_Pos)               /*!< 0x00000002 */

+#define EXTI_EMR2_EM33             EXTI_EMR2_EM33_Msk                          /*!< Event Mask on line 33*/

+#define EXTI_EMR2_EM34_Pos         (2U)

+#define EXTI_EMR2_EM34_Msk         (0x1UL << EXTI_EMR2_EM34_Pos)               /*!< 0x00000004 */

+#define EXTI_EMR2_EM34             EXTI_EMR2_EM34_Msk                          /*!< Event Mask on line 34*/

+#define EXTI_EMR2_EM35_Pos         (3U)

+#define EXTI_EMR2_EM35_Msk         (0x1UL << EXTI_EMR2_EM35_Pos)               /*!< 0x00000008 */

+#define EXTI_EMR2_EM35             EXTI_EMR2_EM35_Msk                          /*!< Event Mask on line 35*/

+#define EXTI_EMR2_EM36_Pos         (4U)

+#define EXTI_EMR2_EM36_Msk         (0x1UL << EXTI_EMR2_EM36_Pos)               /*!< 0x00000010 */

+#define EXTI_EMR2_EM36             EXTI_EMR2_EM36_Msk                          /*!< Event Mask on line 36*/

+#define EXTI_EMR2_EM37_Pos         (5U)

+#define EXTI_EMR2_EM37_Msk         (0x1UL << EXTI_EMR2_EM37_Pos)               /*!< 0x00000020 */

+#define EXTI_EMR2_EM37             EXTI_EMR2_EM37_Msk                          /*!< Event Mask on line 37*/

+#define EXTI_EMR2_EM38_Pos         (6U)

+#define EXTI_EMR2_EM38_Msk         (0x1UL << EXTI_EMR2_EM38_Pos)               /*!< 0x00000040 */

+#define EXTI_EMR2_EM38             EXTI_EMR2_EM38_Msk                          /*!< Event Mask on line 38*/

+#define EXTI_EMR2_EM39_Pos         (7U)

+#define EXTI_EMR2_EM39_Msk         (0x1UL << EXTI_EMR2_EM39_Pos)               /*!< 0x00000080 */

+#define EXTI_EMR2_EM39             EXTI_EMR2_EM39_Msk                          /*!< Event Mask on line 39*/

+#define EXTI_EMR2_EM40_Pos         (8U)

+#define EXTI_EMR2_EM40_Msk         (0x1UL << EXTI_EMR2_EM40_Pos)               /*!< 0x00000100 */

+#define EXTI_EMR2_EM40             EXTI_EMR2_EM40_Msk                          /*!< Event Mask on line 40*/

+#define EXTI_EMR2_EM41_Pos         (9U)

+#define EXTI_EMR2_EM41_Msk         (0x1UL << EXTI_EMR2_EM41_Pos)               /*!< 0x00000200 */

+#define EXTI_EMR2_EM41             EXTI_EMR2_EM41_Msk                          /*!< Event Mask on line 41*/

+#define EXTI_EMR2_EM42_Pos         (10U)

+#define EXTI_EMR2_EM42_Msk         (0x1UL << EXTI_EMR2_EM42_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR2_EM42             EXTI_EMR2_EM42_Msk                          /*!< Event Mask on line 42 */

+#define EXTI_EMR2_EM43_Pos         (11U)

+#define EXTI_EMR2_EM43_Msk         (0x1UL << EXTI_EMR2_EM43_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR2_EM43             EXTI_EMR2_EM43_Msk                          /*!< Event Mask on line 43 */

+#define EXTI_EMR2_EM47_Pos         (15U)

+#define EXTI_EMR2_EM47_Msk         (0x1UL << EXTI_EMR2_EM47_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR2_EM47             EXTI_EMR2_EM47_Msk                          /*!< Event Mask on line 47 */

+#define EXTI_EMR2_EM48_Pos         (16U)

+#define EXTI_EMR2_EM48_Msk         (0x1UL << EXTI_EMR2_EM48_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR2_EM48             EXTI_EMR2_EM48_Msk                          /*!< Event Mask on line 48 */

+#define EXTI_EMR2_EM49_Pos         (17U)

+#define EXTI_EMR2_EM49_Msk         (0x1UL << EXTI_EMR2_EM49_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR2_EM49             EXTI_EMR2_EM49_Msk                          /*!< Event Mask on line 49 */

+#define EXTI_EMR2_EM50_Pos         (18U)

+#define EXTI_EMR2_EM50_Msk         (0x1UL << EXTI_EMR2_EM50_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR2_EM50             EXTI_EMR2_EM50_Msk                          /*!< Event Mask on line 50 */

+#define EXTI_EMR2_EM51_Pos         (19U)

+#define EXTI_EMR2_EM51_Msk         (0x1UL << EXTI_EMR2_EM51_Pos)               /*!< 0x00080000 */

+#define EXTI_EMR2_EM51             EXTI_EMR2_EM51_Msk                          /*!< Event Mask on line 51 */

+#define EXTI_EMR2_EM52_Pos         (20U)

+#define EXTI_EMR2_EM52_Msk         (0x1UL << EXTI_EMR2_EM52_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR2_EM52             EXTI_EMR2_EM52_Msk                          /*!< Event Mask on line 52 */

+#define EXTI_EMR2_EM53_Pos         (21U)

+#define EXTI_EMR2_EM53_Msk         (0x1UL << EXTI_EMR2_EM53_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR2_EM53             EXTI_EMR2_EM53_Msk                          /*!< Event Mask on line 53 */

+#define EXTI_EMR2_EM54_Pos         (22U)

+#define EXTI_EMR2_EM54_Msk         (0x1UL << EXTI_EMR2_EM54_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR2_EM54             EXTI_EMR2_EM54_Msk                          /*!< Event Mask on line 54 */

+#define EXTI_EMR2_EM55_Pos         (23U)

+#define EXTI_EMR2_EM55_Msk         (0x1UL << EXTI_EMR2_EM55_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR2_EM55             EXTI_EMR2_EM55_Msk                          /*!< Event Mask on line 55 */

+#define EXTI_EMR2_EM56_Pos         (24U)

+#define EXTI_EMR2_EM56_Msk         (0x1UL << EXTI_EMR2_EM56_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR2_EM56             EXTI_EMR2_EM56_Msk                          /*!< Event Mask on line 56 */

+#define EXTI_EMR2_EM57_Pos         (25U)

+#define EXTI_EMR2_EM57_Msk         (0x1UL << EXTI_EMR2_EM57_Pos)               /*!< 0x02000000 */

+#define EXTI_EMR2_EM57             EXTI_EMR2_EM57_Msk                          /*!< Event Mask on line 57 */

+#define EXTI_EMR2_EM58_Pos         (26U)

+#define EXTI_EMR2_EM58_Msk         (0x1UL << EXTI_EMR2_EM58_Pos)               /*!< 0x04000000 */

+#define EXTI_EMR2_EM58             EXTI_EMR2_EM58_Msk                          /*!< Event Mask on line 58 */

+#define EXTI_EMR2_EM59_Pos         (27U)

+#define EXTI_EMR2_EM59_Msk         (0x1UL << EXTI_EMR2_EM59_Pos)               /*!< 0x08000000 */

+#define EXTI_EMR2_EM59             EXTI_EMR2_EM59_Msk                          /*!< Event Mask on line 59 */

+#define EXTI_EMR2_EM60_Pos         (28U)

+#define EXTI_EMR2_EM60_Msk         (0x1UL << EXTI_EMR2_EM60_Pos)               /*!< 0x10000000 */

+#define EXTI_EMR2_EM60             EXTI_EMR2_EM60_Msk                          /*!< Event Mask on line 60 */

+#define EXTI_EMR2_EM61_Pos         (29U)

+#define EXTI_EMR2_EM61_Msk         (0x1UL << EXTI_EMR2_EM61_Pos)               /*!< 0x20000000 */

+#define EXTI_EMR2_EM61             EXTI_EMR2_EM61_Msk                          /*!< Event Mask on line 61 */

+#define EXTI_EMR2_EM62_Pos         (30U)

+#define EXTI_EMR2_EM62_Msk         (0x1UL << EXTI_EMR2_EM62_Pos)               /*!< 0x40000000 */

+#define EXTI_EMR2_EM62             EXTI_EMR2_EM62_Msk                          /*!< Event Mask on line 62 */

+#define EXTI_EMR2_EM63_Pos         (31U)

+#define EXTI_EMR2_EM63_Msk         (0x1UL << EXTI_EMR2_EM63_Pos)               /*!< 0x80000000 */

+#define EXTI_EMR2_EM63             EXTI_EMR2_EM63_Msk                          /*!< Event Mask on line 63 */

+

+/*******************  Bit definition for EXTI_PR2 register  ********************/

+#define EXTI_PR2_PR_Pos            (17U)

+#define EXTI_PR2_PR_Msk            (0x5UL << EXTI_PR2_PR_Pos)                  /*!< 0x000A0000 */

+#define EXTI_PR2_PR                EXTI_PR2_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR2_PR49_Pos          (17U)

+#define EXTI_PR2_PR49_Msk          (0x1UL << EXTI_PR2_PR49_Pos)                /*!< 0x00020000 */

+#define EXTI_PR2_PR49              EXTI_PR2_PR49_Msk                           /*!< Pending bit for line 49 */

+#define EXTI_PR2_PR51_Pos          (19U)

+#define EXTI_PR2_PR51_Msk          (0x1UL << EXTI_PR2_PR51_Pos)                /*!< 0x00080000 */

+#define EXTI_PR2_PR51              EXTI_PR2_PR51_Msk                           /*!< Pending bit for line 51 */

+

+/*******************  Bit definition for EXTI_IMR3 register  *******************/

+#define EXTI_IMR3_IM_Pos           (0U)

+#define EXTI_IMR3_IM_Msk           (0x001A527FFUL << EXTI_IMR3_IM_Pos)         /*!< 0x001A527FF */

+#define EXTI_IMR3_IM               EXTI_IMR3_IM_Msk                            /*!< Interrupt Mask            */

+#define EXTI_IMR3_IM64_Pos         (0U)

+#define EXTI_IMR3_IM64_Msk         (0x1UL << EXTI_IMR3_IM64_Pos)               /*!< 0x00000001 */

+#define EXTI_IMR3_IM64             EXTI_IMR3_IM64_Msk                          /*!< Interrupt Mask on line 64 */

+#define EXTI_IMR3_IM65_Pos         (1U)

+#define EXTI_IMR3_IM65_Msk         (0x1UL << EXTI_IMR3_IM65_Pos)               /*!< 0x00000002 */

+#define EXTI_IMR3_IM65             EXTI_IMR3_IM65_Msk                          /*!< Interrupt Mask on line 65 */

+#define EXTI_IMR3_IM66_Pos         (2U)

+#define EXTI_IMR3_IM66_Msk         (0x1UL << EXTI_IMR3_IM66_Pos)               /*!< 0x00000004 */

+#define EXTI_IMR3_IM66             EXTI_IMR3_IM66_Msk                          /*!< Interrupt Mask on line 66 */

+#define EXTI_IMR3_IM67_Pos         (3U)

+#define EXTI_IMR3_IM67_Msk         (0x1UL << EXTI_IMR3_IM67_Pos)               /*!< 0x00000008 */

+#define EXTI_IMR3_IM67             EXTI_IMR3_IM67_Msk                          /*!< Interrupt Mask on line 67 */

+#define EXTI_IMR3_IM68_Pos         (4U)

+#define EXTI_IMR3_IM68_Msk         (0x1UL << EXTI_IMR3_IM68_Pos)               /*!< 0x00000010 */

+#define EXTI_IMR3_IM68             EXTI_IMR3_IM68_Msk                          /*!< Interrupt Mask on line 68 */

+#define EXTI_IMR3_IM69_Pos         (5U)

+#define EXTI_IMR3_IM69_Msk         (0x1UL << EXTI_IMR3_IM69_Pos)               /*!< 0x00000020 */

+#define EXTI_IMR3_IM69             EXTI_IMR3_IM69_Msk                          /*!< Interrupt Mask on line 69 */

+#define EXTI_IMR3_IM70_Pos         (6U)

+#define EXTI_IMR3_IM70_Msk         (0x1UL << EXTI_IMR3_IM70_Pos)               /*!< 0x00000040 */

+#define EXTI_IMR3_IM70             EXTI_IMR3_IM70_Msk                          /*!< Interrupt Mask on line 70 */

+#define EXTI_IMR3_IM71_Pos         (7U)

+#define EXTI_IMR3_IM71_Msk         (0x1UL << EXTI_IMR3_IM71_Pos)               /*!< 0x00000080 */

+#define EXTI_IMR3_IM71             EXTI_IMR3_IM71_Msk                          /*!< Interrupt Mask on line 71 */

+#define EXTI_IMR3_IM72_Pos         (8U)

+#define EXTI_IMR3_IM72_Msk         (0x1UL << EXTI_IMR3_IM72_Pos)               /*!< 0x00000100 */

+#define EXTI_IMR3_IM72             EXTI_IMR3_IM72_Msk                          /*!< Interrupt Mask on line 72 */

+#define EXTI_IMR3_IM73_Pos         (9U)

+#define EXTI_IMR3_IM73_Msk         (0x1UL << EXTI_IMR3_IM73_Pos)               /*!< 0x00000200 */

+#define EXTI_IMR3_IM73             EXTI_IMR3_IM73_Msk                          /*!< Interrupt Mask on line 73 */

+#define EXTI_IMR3_IM74_Pos         (10U)

+#define EXTI_IMR3_IM74_Msk         (0x1UL << EXTI_IMR3_IM74_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR3_IM74             EXTI_IMR3_IM74_Msk                          /*!< Interrupt Mask on line 74 */

+#define EXTI_IMR3_IM77_Pos         (13U)

+#define EXTI_IMR3_IM77_Msk         (0x1UL << EXTI_IMR3_IM77_Pos)               /*!< 0x00002000 */

+#define EXTI_IMR3_IM77             EXTI_IMR3_IM77_Msk                          /*!< Interrupt Mask on line 77 */

+#define EXTI_IMR3_IM80_Pos         (16U)

+#define EXTI_IMR3_IM80_Msk         (0x1UL << EXTI_IMR3_IM80_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR3_IM80             EXTI_IMR3_IM80_Msk                          /*!< Interrupt Mask on line 80 */

+#define EXTI_IMR3_IM82_Pos         (18U)

+#define EXTI_IMR3_IM82_Msk         (0x1UL << EXTI_IMR3_IM82_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR3_IM82             EXTI_IMR3_IM82_Msk                          /*!< Interrupt Mask on line 82 */

+#define EXTI_IMR3_IM85_Pos         (21U)

+#define EXTI_IMR3_IM85_Msk         (0x1UL << EXTI_IMR3_IM85_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR3_IM85             EXTI_IMR3_IM85_Msk                          /*!< Interrupt Mask on line 85 */

+#define EXTI_IMR3_IM87_Pos         (23U)

+#define EXTI_IMR3_IM87_Msk         (0x1UL << EXTI_IMR3_IM87_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR3_IM87             EXTI_IMR3_IM87_Msk                          /*!< Interrupt Mask on line 87 */

+

+

+#define EXTI_IMR3_IM88_Pos         (24U)

+#define EXTI_IMR3_IM88_Msk         (0x1UL << EXTI_IMR3_IM88_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR3_IM88             EXTI_IMR3_IM88_Msk                          /*!< Interrupt Mask on line 88 */

+

+/*******************  Bit definition for EXTI_EMR3 register  *******************/

+#define EXTI_EMR3_EM_Pos           (0U)

+#define EXTI_EMR3_EM_Msk           (0x01A527FFUL << EXTI_EMR3_EM_Pos)          /*!< 0x01A527FF */

+#define EXTI_EMR3_EM               EXTI_EMR3_EM_Msk                            /*!< Event Mask           */

+#define EXTI_EMR3_EM64_Pos         (0U)

+#define EXTI_EMR3_EM64_Msk         (0x1UL << EXTI_EMR3_EM64_Pos)               /*!< 0x00000001 */

+#define EXTI_EMR3_EM64             EXTI_EMR3_EM64_Msk                          /*!< Event Mask on line 64*/

+#define EXTI_EMR3_EM65_Pos         (1U)

+#define EXTI_EMR3_EM65_Msk         (0x1UL << EXTI_EMR3_EM65_Pos)               /*!< 0x00000002 */

+#define EXTI_EMR3_EM65             EXTI_EMR3_EM65_Msk                          /*!< Event Mask on line 65*/

+#define EXTI_EMR3_EM66_Pos         (2U)

+#define EXTI_EMR3_EM66_Msk         (0x1UL << EXTI_EMR3_EM66_Pos)               /*!< 0x00000004 */

+#define EXTI_EMR3_EM66             EXTI_EMR3_EM66_Msk                          /*!< Event Mask on line 66*/

+#define EXTI_EMR3_EM67_Pos         (3U)

+#define EXTI_EMR3_EM67_Msk         (0x1UL << EXTI_EMR3_EM67_Pos)               /*!< 0x00000008 */

+#define EXTI_EMR3_EM67             EXTI_EMR3_EM67_Msk                          /*!< Event Mask on line 67*/

+#define EXTI_EMR3_EM68_Pos         (4U)

+#define EXTI_EMR3_EM68_Msk         (0x1UL << EXTI_EMR3_EM68_Pos)               /*!< 0x00000010 */

+#define EXTI_EMR3_EM68             EXTI_EMR3_EM68_Msk                          /*!< Event Mask on line 68*/

+#define EXTI_EMR3_EM69_Pos         (5U)

+#define EXTI_EMR3_EM69_Msk         (0x1UL << EXTI_EMR3_EM69_Pos)               /*!< 0x00000020 */

+#define EXTI_EMR3_EM69             EXTI_EMR3_EM69_Msk                          /*!< Event Mask on line 69*/

+#define EXTI_EMR3_EM70_Pos         (6U)

+#define EXTI_EMR3_EM70_Msk         (0x1UL << EXTI_EMR3_EM70_Pos)               /*!< 0x00000040 */

+#define EXTI_EMR3_EM70             EXTI_EMR3_EM70_Msk                          /*!< Event Mask on line 70*/

+#define EXTI_EMR3_EM71_Pos         (7U)

+#define EXTI_EMR3_EM71_Msk         (0x1UL << EXTI_EMR3_EM71_Pos)               /*!< 0x00000080 */

+#define EXTI_EMR3_EM71             EXTI_EMR3_EM71_Msk                          /*!< Event Mask on line 71*/

+#define EXTI_EMR3_EM72_Pos         (8U)

+#define EXTI_EMR3_EM72_Msk         (0x1UL << EXTI_EMR3_EM72_Pos)               /*!< 0x00000100 */

+#define EXTI_EMR3_EM72             EXTI_EMR3_EM72_Msk                          /*!< Event Mask on line 72*/

+#define EXTI_EMR3_EM73_Pos         (9U)

+#define EXTI_EMR3_EM73_Msk         (0x1UL << EXTI_EMR3_EM73_Pos)               /*!< 0x00000200 */

+#define EXTI_EMR3_EM73             EXTI_EMR3_EM73_Msk                          /*!< Event Mask on line 73*/

+#define EXTI_EMR3_EM74_Pos         (10U)

+#define EXTI_EMR3_EM74_Msk         (0x1UL << EXTI_EMR3_EM74_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR3_EM74             EXTI_EMR3_EM74_Msk                          /*!< Event Mask on line 74 */

+#define EXTI_EMR3_EM77_Pos         (13U)

+#define EXTI_EMR3_EM77_Msk         (0x1UL << EXTI_EMR3_EM77_Pos)               /*!< 0x00002000 */

+#define EXTI_EMR3_EM77             EXTI_EMR3_EM77_Msk                          /*!< Event Mask on line 77 */

+#define EXTI_EMR3_EM80_Pos         (16U)

+#define EXTI_EMR3_EM80_Msk         (0x1UL << EXTI_EMR3_EM80_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR3_EM80             EXTI_EMR3_EM80_Msk                          /*!< Event Mask on line 80 */

+#define EXTI_EMR3_EM81_Pos         (17U)

+#define EXTI_EMR3_EM81_Msk         (0x1UL << EXTI_EMR3_EM81_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR3_EM81             EXTI_EMR3_EM81_Msk                          /*!< Event Mask on line 81 */

+#define EXTI_EMR3_EM82_Pos         (18U)

+#define EXTI_EMR3_EM82_Msk         (0x1UL << EXTI_EMR3_EM82_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR3_EM82             EXTI_EMR3_EM82_Msk                          /*!< Event Mask on line 82 */

+#define EXTI_EMR3_EM85_Pos         (21U)

+#define EXTI_EMR3_EM85_Msk         (0x1UL << EXTI_EMR3_EM85_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR3_EM85             EXTI_EMR3_EM85_Msk                          /*!< Event Mask on line 85 */

+#define EXTI_EMR3_EM87_Pos         (23U)

+#define EXTI_EMR3_EM87_Msk         (0x1UL << EXTI_EMR3_EM87_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR3_EM87             EXTI_EMR3_EM87_Msk                          /*!< Event Mask on line 87 */

+

+#define EXTI_EMR3_EM88_Pos         (24U)

+#define EXTI_EMR3_EM88_Msk         (0x1UL << EXTI_EMR3_EM88_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR3_EM88             EXTI_EMR3_EM88_Msk                          /*!< Event Mask on line 88 */

+

+/*******************  Bit definition for EXTI_PR3 register  ********************/

+#define EXTI_PR3_PR_Pos            (18U)

+#define EXTI_PR3_PR_Msk            (0x9UL << EXTI_PR3_PR_Pos)                  /*!< 0x00240000 */

+#define EXTI_PR3_PR                EXTI_PR3_PR_Msk                             /*!< Pending bit             */

+#define EXTI_PR3_PR82_Pos          (18U)

+#define EXTI_PR3_PR82_Msk          (0x1UL << EXTI_PR3_PR82_Pos)                /*!< 0x00040000 */

+#define EXTI_PR3_PR82              EXTI_PR3_PR82_Msk                           /*!< Pending bit for line 82 */

+#define EXTI_PR3_PR85_Pos          (21U)

+#define EXTI_PR3_PR85_Msk          (0x1UL << EXTI_PR3_PR85_Pos)                /*!< 0x00200000 */

+#define EXTI_PR3_PR85              EXTI_PR3_PR85_Msk                           /*!< Pending bit for line 85 */

+/******************************************************************************/

+/*                                                                            */

+/*                                    FLASH                                   */

+/*                                                                            */

+/******************************************************************************/

+/*

+* @brief FLASH Global Defines

+*/

+#define FLASH_SECTOR_TOTAL                   16U                   /* 16 sectors */

+#define FLASH_SECTOR_SIZE                    0x00002000UL          /* 8 KB       */

+#define FLASH_SIZE                           0x00020000UL          /* 128 KB     */

+#define FLASH_BANK_SIZE                      FLASH_SIZE            /* 128 KB     */

+#define FLASH_LATENCY_DEFAULT                FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycles */

+#define FLASH_NB_32BITWORD_IN_FLASHWORD      4U                    /* 128 bits */

+

+/*******************  Bits definition for FLASH_ACR register  **********************/

+#define FLASH_ACR_LATENCY_Pos                (0U)

+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */

+#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */

+#define FLASH_ACR_LATENCY_0WS                (0x00000000UL)

+#define FLASH_ACR_LATENCY_1WS                (0x00000001UL)

+#define FLASH_ACR_LATENCY_2WS                (0x00000002UL)

+#define FLASH_ACR_LATENCY_3WS                (0x00000003UL)

+#define FLASH_ACR_LATENCY_4WS                (0x00000004UL)

+#define FLASH_ACR_LATENCY_5WS                (0x00000005UL)

+#define FLASH_ACR_LATENCY_6WS                (0x00000006UL)

+#define FLASH_ACR_LATENCY_7WS                (0x00000007UL)

+#define FLASH_ACR_LATENCY_8WS                (0x00000008UL)

+#define FLASH_ACR_LATENCY_9WS                (0x00000009UL)

+#define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)

+#define FLASH_ACR_LATENCY_11WS               (0x0000000BUL)

+#define FLASH_ACR_LATENCY_12WS               (0x0000000CUL)

+#define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)

+#define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)

+#define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)

+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)

+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */

+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */

+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */

+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */

+

+/*******************  Bits definition for FLASH_CR register  ***********************/

+#define FLASH_CR_LOCK_Pos                    (0U)

+#define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */

+#define FLASH_CR_LOCK                        FLASH_CR_LOCK_Msk                 /*!< Configuration lock bit */

+#define FLASH_CR_PG_Pos                      (1U)

+#define FLASH_CR_PG_Msk                      (0x1UL << FLASH_CR_PG_Pos)        /*!< 0x00000002 */

+#define FLASH_CR_PG                          FLASH_CR_PG_Msk                   /*!< Internal buffer control bit */

+#define FLASH_CR_SER_Pos                     (2U)

+#define FLASH_CR_SER_Msk                     (0x1UL << FLASH_CR_SER_Pos)       /*!< 0x00000004 */

+#define FLASH_CR_SER                         FLASH_CR_SER_Msk                  /*!< Sector erase request */

+#define FLASH_CR_BER_Pos                     (3U)

+#define FLASH_CR_BER_Msk                     (0x1UL << FLASH_CR_BER_Pos)       /*!< 0x00000008 */

+#define FLASH_CR_BER                         FLASH_CR_BER_Msk                  /*!< Bank erase request */

+#define FLASH_CR_FW_Pos                      (4U)

+#define FLASH_CR_FW_Msk                      (0x1UL << FLASH_CR_FW_Pos)        /*!< 0x00000010 */

+#define FLASH_CR_FW                          FLASH_CR_FW_Msk                   /*!< Write forcing control bit */

+#define FLASH_CR_START_Pos                   (5U)

+#define FLASH_CR_START_Msk                   (0x1UL << FLASH_CR_START_Pos)     /*!< 0x00000020 */

+#define FLASH_CR_START                       FLASH_CR_START_Msk                /*!< Erase start control bit */

+#define FLASH_CR_SNB_Pos                     (6U)

+#define FLASH_CR_SNB_Msk                     (0x7FUL << FLASH_CR_SNB_Pos)      /*!< 0x00001FC0 */

+#define FLASH_CR_SNB                         FLASH_CR_SNB_Msk                  /*!< Sector erase selection number */

+#define FLASH_CR_SNB_0                       (0x01UL << FLASH_CR_SNB_Pos)      /*!< 0x00000040 */

+#define FLASH_CR_SNB_1                       (0x02UL << FLASH_CR_SNB_Pos)      /*!< 0x00000080 */

+#define FLASH_CR_SNB_2                       (0x04UL << FLASH_CR_SNB_Pos)      /*!< 0x00000100 */

+#define FLASH_CR_SNB_3                       (0x08UL << FLASH_CR_SNB_Pos)      /*!< 0x00000200 */

+#define FLASH_CR_SNB_4                       (0x10UL << FLASH_CR_SNB_Pos)      /*!< 0x00000400 */

+#define FLASH_CR_SNB_5                       (0x20UL << FLASH_CR_SNB_Pos)      /*!< 0x00000800 */

+#define FLASH_CR_SNB_6                       (0x40UL << FLASH_CR_SNB_Pos)      /*!< 0x00001000 */

+#define FLASH_CR_CRC_EN_Pos                  (15U)

+#define FLASH_CR_CRC_EN_Msk                  (0x1UL << FLASH_CR_CRC_EN_Pos)    /*!< 0x00008000 */

+#define FLASH_CR_CRC_EN                      FLASH_CR_CRC_EN_Msk               /*!< CRC control bit */

+#define FLASH_CR_EOPIE_Pos                   (16U)

+#define FLASH_CR_EOPIE_Msk                   (0x1UL << FLASH_CR_EOPIE_Pos)     /*!< 0x00010000 */

+#define FLASH_CR_EOPIE                       FLASH_CR_EOPIE_Msk                /*!< End-of-program interrupt control bit */

+#define FLASH_CR_WRPERRIE_Pos                (17U)

+#define FLASH_CR_WRPERRIE_Msk                (0x1UL << FLASH_CR_WRPERRIE_Pos)  /*!< 0x00020000 */

+#define FLASH_CR_WRPERRIE                    FLASH_CR_WRPERRIE_Msk             /*!< Write protection error interrupt enable bit */

+#define FLASH_CR_PGSERRIE_Pos                (18U)

+#define FLASH_CR_PGSERRIE_Msk                (0x1UL << FLASH_CR_PGSERRIE_Pos)  /*!< 0x00040000 */

+#define FLASH_CR_PGSERRIE                    FLASH_CR_PGSERRIE_Msk             /*!< Programming sequence error interrupt enable bit */

+#define FLASH_CR_STRBERRIE_Pos               (19U)

+#define FLASH_CR_STRBERRIE_Msk               (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */

+#define FLASH_CR_STRBERRIE                   FLASH_CR_STRBERRIE_Msk            /*!< Strobe error interrupt enable bit */

+#define FLASH_CR_INCERRIE_Pos                (21U)

+#define FLASH_CR_INCERRIE_Msk                (0x1UL << FLASH_CR_INCERRIE_Pos)  /*!< 0x00200000 */

+#define FLASH_CR_INCERRIE                    FLASH_CR_INCERRIE_Msk             /*!< Inconsistency error interrupt enable bit */

+#define FLASH_CR_RDPERRIE_Pos                (23U)

+#define FLASH_CR_RDPERRIE_Msk                (0x1UL << FLASH_CR_RDPERRIE_Pos)  /*!< 0x00800000 */

+#define FLASH_CR_RDPERRIE                    FLASH_CR_RDPERRIE_Msk             /*!< Read protection error interrupt enable bit */

+#define FLASH_CR_RDSERRIE_Pos                (24U)

+#define FLASH_CR_RDSERRIE_Msk                (0x1UL << FLASH_CR_RDSERRIE_Pos)  /*!< 0x01000000 */

+#define FLASH_CR_RDSERRIE                    FLASH_CR_RDSERRIE_Msk             /*!< Secure error interrupt enable bit */

+#define FLASH_CR_SNECCERRIE_Pos              (25U)

+#define FLASH_CR_SNECCERRIE_Msk              (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */

+#define FLASH_CR_SNECCERRIE                  FLASH_CR_SNECCERRIE_Msk            /*!< ECC single correction error interrupt enable bit */

+#define FLASH_CR_DBECCERRIE_Pos              (26U)

+#define FLASH_CR_DBECCERRIE_Msk              (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */

+#define FLASH_CR_DBECCERRIE                  FLASH_CR_DBECCERRIE_Msk            /*!< ECC double detection error interrupt enable bit */

+#define FLASH_CR_CRCENDIE_Pos                (27U)

+#define FLASH_CR_CRCENDIE_Msk                (0x1UL << FLASH_CR_CRCENDIE_Pos)  /*!< 0x08000000 */

+#define FLASH_CR_CRCENDIE                    FLASH_CR_CRCENDIE_Msk             /*!< CRC end of calculation interrupt enable bit */

+#define FLASH_CR_CRCRDERRIE_Pos              (28U)

+#define FLASH_CR_CRCRDERRIE_Msk              (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */

+#define FLASH_CR_CRCRDERRIE                  FLASH_CR_CRCRDERRIE_Msk            /*!< CRC read error interrupt enable bit */

+

+/*******************  Bits definition for FLASH_SR register  ***********************/

+#define FLASH_SR_BSY_Pos                     (0U)

+#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)       /*!< 0x00000001 */

+#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy flag */

+#define FLASH_SR_WBNE_Pos                    (1U)

+#define FLASH_SR_WBNE_Msk                    (0x1UL << FLASH_SR_WBNE_Pos)      /*!< 0x00000002 */

+#define FLASH_SR_WBNE                        FLASH_SR_WBNE_Msk                 /*!< Write buffer not empty flag */

+#define FLASH_SR_QW_Pos                      (2U)

+#define FLASH_SR_QW_Msk                      (0x1UL << FLASH_SR_QW_Pos)        /*!< 0x00000004 */

+#define FLASH_SR_QW                          FLASH_SR_QW_Msk                   /*!< Wait queue flag */

+#define FLASH_SR_CRC_BUSY_Pos                (3U)

+#define FLASH_SR_CRC_BUSY_Msk                (0x1UL << FLASH_SR_CRC_BUSY_Pos)  /*!< 0x00000008 */

+#define FLASH_SR_CRC_BUSY                    FLASH_SR_CRC_BUSY_Msk             /*!< CRC busy flag */

+#define FLASH_SR_EOP_Pos                     (16U)

+#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)       /*!< 0x00010000 */

+#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End-of-program flag */

+#define FLASH_SR_WRPERR_Pos                  (17U)

+#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)    /*!< 0x00020000 */

+#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protection error flag */

+#define FLASH_SR_PGSERR_Pos                  (18U)

+#define FLASH_SR_PGSERR_Msk                  (0x1UL << FLASH_SR_PGSERR_Pos)    /*!< 0x00040000 */

+#define FLASH_SR_PGSERR                      FLASH_SR_PGSERR_Msk               /*!< Programming sequence error flag */

+#define FLASH_SR_STRBERR_Pos                 (19U)

+#define FLASH_SR_STRBERR_Msk                 (0x1UL << FLASH_SR_STRBERR_Pos)   /*!< 0x00080000 */

+#define FLASH_SR_STRBERR                     FLASH_SR_STRBERR_Msk              /*!< Strobe error flag */

+#define FLASH_SR_INCERR_Pos                  (21U)

+#define FLASH_SR_INCERR_Msk                  (0x1UL << FLASH_SR_INCERR_Pos)    /*!< 0x00200000 */

+#define FLASH_SR_INCERR                      FLASH_SR_INCERR_Msk               /*!< Inconsistency error flag */

+#define FLASH_SR_RDPERR_Pos                  (23U)

+#define FLASH_SR_RDPERR_Msk                  (0x1UL << FLASH_SR_RDPERR_Pos)    /*!< 0x00800000 */

+#define FLASH_SR_RDPERR                      FLASH_SR_RDPERR_Msk               /*!< Read protection error flag */

+#define FLASH_SR_RDSERR_Pos                  (24U)

+#define FLASH_SR_RDSERR_Msk                  (0x1UL << FLASH_SR_RDSERR_Pos)    /*!< 0x01000000 */

+#define FLASH_SR_RDSERR                      FLASH_SR_RDSERR_Msk               /*!< Secure error flag */

+#define FLASH_SR_SNECCERR_Pos                (25U)

+#define FLASH_SR_SNECCERR_Msk                (0x1UL << FLASH_SR_SNECCERR_Pos)  /*!< 0x02000000 */

+#define FLASH_SR_SNECCERR                    FLASH_SR_SNECCERR_Msk             /*!< Single correction error flag */

+#define FLASH_SR_DBECCERR_Pos                (26U)

+#define FLASH_SR_DBECCERR_Msk                (0x1UL << FLASH_SR_DBECCERR_Pos)  /*!< 0x04000000 */

+#define FLASH_SR_DBECCERR                    FLASH_SR_DBECCERR_Msk             /*!< ECC double detection error flag */

+#define FLASH_SR_CRCEND_Pos                  (27U)

+#define FLASH_SR_CRCEND_Msk                  (0x1UL << FLASH_SR_CRCEND_Pos)    /*!< 0x08000000 */

+#define FLASH_SR_CRCEND                      FLASH_SR_CRCEND_Msk               /*!< CRC end of calculation flag */

+#define FLASH_SR_CRCRDERR_Pos                (28U)

+#define FLASH_SR_CRCRDERR_Msk                (0x1UL << FLASH_SR_CRCRDERR_Pos)  /*!< 0x10000000 */

+#define FLASH_SR_CRCRDERR                    FLASH_SR_CRCRDERR_Msk             /*!< CRC read error flag */

+

+/*******************  Bits definition for FLASH_CCR register  *******************/

+#define FLASH_CCR_CLR_EOP_Pos                (16U)

+#define FLASH_CCR_CLR_EOP_Msk                (0x1UL << FLASH_CCR_CLR_EOP_Pos)  /*!< 0x00010000 */

+#define FLASH_CCR_CLR_EOP                    FLASH_CCR_CLR_EOP_Msk             /*!< EOP flag clear bit */

+#define FLASH_CCR_CLR_WRPERR_Pos             (17U)

+#define FLASH_CCR_CLR_WRPERR_Msk             (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */

+#define FLASH_CCR_CLR_WRPERR                 FLASH_CCR_CLR_WRPERR_Msk            /*!< WRPERR flag clear bit */

+#define FLASH_CCR_CLR_PGSERR_Pos             (18U)

+#define FLASH_CCR_CLR_PGSERR_Msk             (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */

+#define FLASH_CCR_CLR_PGSERR                 FLASH_CCR_CLR_PGSERR_Msk            /*!< PGSERR flag clear bit */

+#define FLASH_CCR_CLR_STRBERR_Pos            (19U)

+#define FLASH_CCR_CLR_STRBERR_Msk            (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */

+#define FLASH_CCR_CLR_STRBERR                FLASH_CCR_CLR_STRBERR_Msk            /*!< STRBERR flag clear bit */

+#define FLASH_CCR_CLR_INCERR_Pos             (21U)

+#define FLASH_CCR_CLR_INCERR_Msk             (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */

+#define FLASH_CCR_CLR_INCERR                 FLASH_CCR_CLR_INCERR_Msk            /*!< INCERR flag clear bit */

+#define FLASH_CCR_CLR_RDPERR_Pos             (23U)

+#define FLASH_CCR_CLR_RDPERR_Msk             (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */

+#define FLASH_CCR_CLR_RDPERR                 FLASH_CCR_CLR_RDPERR_Msk            /*!< RDPERR flag clear bit */

+#define FLASH_CCR_CLR_RDSERR_Pos             (24U)

+#define FLASH_CCR_CLR_RDSERR_Msk             (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */

+#define FLASH_CCR_CLR_RDSERR                 FLASH_CCR_CLR_RDSERR_Msk            /*!< RDSERR flag clear bit */

+#define FLASH_CCR_CLR_SNECCERR_Pos           (25U)

+#define FLASH_CCR_CLR_SNECCERR_Msk           (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */

+#define FLASH_CCR_CLR_SNECCERR               FLASH_CCR_CLR_SNECCERR_Msk            /*!< SNECCERR flag clear bit */

+#define FLASH_CCR_CLR_DBECCERR_Pos           (26U)

+#define FLASH_CCR_CLR_DBECCERR_Msk           (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */

+#define FLASH_CCR_CLR_DBECCERR               FLASH_CCR_CLR_DBECCERR_Msk            /*!< DBECCERR flag clear bit */

+#define FLASH_CCR_CLR_CRCEND_Pos             (27U)

+#define FLASH_CCR_CLR_CRCEND_Msk             (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */

+#define FLASH_CCR_CLR_CRCEND                 FLASH_CCR_CLR_CRCEND_Msk            /*!< CRCEND flag clear bit */

+#define FLASH_CCR_CLR_CRCRDERR_Pos           (28U)

+#define FLASH_CCR_CLR_CRCRDERR_Msk           (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */

+#define FLASH_CCR_CLR_CRCRDERR               FLASH_CCR_CLR_CRCRDERR_Msk            /*!< CRCRDERR flag clear bit */

+

+/*******************  Bits definition for FLASH_OPTCR register  *******************/

+#define FLASH_OPTCR_OPTLOCK_Pos              (0U)

+#define FLASH_OPTCR_OPTLOCK_Msk              (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)  /*!< 0x00000001 */

+#define FLASH_OPTCR_OPTLOCK                  FLASH_OPTCR_OPTLOCK_Msk             /*!< FLASH_OPTCR lock option configuration bit */

+#define FLASH_OPTCR_OPTSTART_Pos             (1U)

+#define FLASH_OPTCR_OPTSTART_Msk             (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */

+#define FLASH_OPTCR_OPTSTART                 FLASH_OPTCR_OPTSTART_Msk            /*!< Option byte start change option configuration bit */

+#define FLASH_OPTCR_MER_Pos                  (4U)

+#define FLASH_OPTCR_MER_Msk                  (0x1UL << FLASH_OPTCR_MER_Pos)      /*!< 0x00000010 */

+#define FLASH_OPTCR_MER                      FLASH_OPTCR_MER_Msk                 /*!< Mass erase request */

+#define FLASH_OPTCR_PG_OTP_Pos               (5U)

+#define FLASH_OPTCR_PG_OTP_Msk               (0x1UL << FLASH_OPTCR_PG_OTP_Pos)   /*!< 0x00000020 */

+#define FLASH_OPTCR_PG_OTP                   FLASH_OPTCR_PG_OTP_Msk              /*!< OTP program control bit */

+#define FLASH_OPTCR_OPTCHANGEERRIE_Pos       (30U)

+#define FLASH_OPTCR_OPTCHANGEERRIE_Msk       (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */

+#define FLASH_OPTCR_OPTCHANGEERRIE           FLASH_OPTCR_OPTCHANGEERRIE_Msk            /*!< Option byte change error interrupt enable bit */

+#define FLASH_OPTCR_SWAP_BANK_Pos            (31U)

+#define FLASH_OPTCR_SWAP_BANK_Msk            (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */

+#define FLASH_OPTCR_SWAP_BANK                FLASH_OPTCR_SWAP_BANK_Msk            /*!< Bank swapping option configuration bit */

+

+/*******************  Bits definition for FLASH_OPTSR register  ***************/

+#define FLASH_OPTSR_OPT_BUSY_Pos             (0U)

+#define FLASH_OPTSR_OPT_BUSY_Msk             (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */

+#define FLASH_OPTSR_OPT_BUSY                 FLASH_OPTSR_OPT_BUSY_Msk            /*!< Option byte change ongoing flag */

+#define FLASH_OPTSR_BOR_LEV_Pos              (2U)

+#define FLASH_OPTSR_BOR_LEV_Msk              (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */

+#define FLASH_OPTSR_BOR_LEV                  FLASH_OPTSR_BOR_LEV_Msk            /*!< Brownout level option status bit */

+#define FLASH_OPTSR_BOR_LEV_0                (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */

+#define FLASH_OPTSR_BOR_LEV_1                (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */

+#define FLASH_OPTSR_IWDG1_SW_Pos             (4U)

+#define FLASH_OPTSR_IWDG1_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */

+#define FLASH_OPTSR_IWDG1_SW                 FLASH_OPTSR_IWDG1_SW_Msk            /*!< IWDG1 control mode option status bit */

+#define FLASH_OPTSR_NRST_STOP_D1_Pos         (6U)

+#define FLASH_OPTSR_NRST_STOP_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */

+#define FLASH_OPTSR_NRST_STOP_D1             FLASH_OPTSR_NRST_STOP_D1_Msk            /*!< D1 domain DStop entry reset option status bit */

+#define FLASH_OPTSR_NRST_STBY_D1_Pos         (7U)

+#define FLASH_OPTSR_NRST_STBY_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */

+#define FLASH_OPTSR_NRST_STBY_D1             FLASH_OPTSR_NRST_STBY_D1_Msk            /*!< D1 domain DStandby entry reset option status bit */

+#define FLASH_OPTSR_RDP_Pos                  (8U)

+#define FLASH_OPTSR_RDP_Msk                  (0xFFUL << FLASH_OPTSR_RDP_Pos)   /*!< 0x0000FF00 */

+#define FLASH_OPTSR_RDP                      FLASH_OPTSR_RDP_Msk               /*!< Readout protection level option status byte */

+#define FLASH_OPTSR_VDDMMC_HSLV_Pos          (16U)

+#define FLASH_OPTSR_VDDMMC_HSLV_Msk          (0x1UL << FLASH_OPTSR_VDDMMC_HSLV_Pos) /*!< 0x00010000 */

+#define FLASH_OPTSR_VDDMMC_HSLV              FLASH_OPTSR_VDDMMC_HSLV_Msk            /*!< VDDMMC I/O high-speed at low-voltage status bit (below 2.5V) */

+#define FLASH_OPTSR_FZ_IWDG_STOP_Pos         (17U)

+#define FLASH_OPTSR_FZ_IWDG_STOP_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */

+#define FLASH_OPTSR_FZ_IWDG_STOP             FLASH_OPTSR_FZ_IWDG_STOP_Msk            /*!< IWDG Stop mode freeze option status bit */

+#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos         (18U)

+#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */

+#define FLASH_OPTSR_FZ_IWDG_SDBY             FLASH_OPTSR_FZ_IWDG_SDBY_Msk            /*!< IWDG Standby mode freeze option status bit */

+#define FLASH_OPTSR_ST_RAM_SIZE_Pos          (19U)

+#define FLASH_OPTSR_ST_RAM_SIZE_Msk          (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */

+#define FLASH_OPTSR_ST_RAM_SIZE              FLASH_OPTSR_ST_RAM_SIZE_Msk            /*!< ST RAM size option status */

+#define FLASH_OPTSR_ST_RAM_SIZE_0            (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */

+#define FLASH_OPTSR_ST_RAM_SIZE_1            (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */

+#define FLASH_OPTSR_SECURITY_Pos             (21U)

+#define FLASH_OPTSR_SECURITY_Msk             (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */

+#define FLASH_OPTSR_SECURITY                 FLASH_OPTSR_SECURITY_Msk            /*!< Security enable option status bit */

+#define FLASH_OPTSR_IO_HSLV_Pos              (29U)

+#define FLASH_OPTSR_IO_HSLV_Msk              (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */

+#define FLASH_OPTSR_IO_HSLV                  FLASH_OPTSR_IO_HSLV_Msk            /*!< I/O high-speed at low-voltage status bit */

+#define FLASH_OPTSR_OPTCHANGEERR_Pos         (30U)

+#define FLASH_OPTSR_OPTCHANGEERR_Msk         (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */

+#define FLASH_OPTSR_OPTCHANGEERR             FLASH_OPTSR_OPTCHANGEERR_Msk            /*!< Option byte change error flag */

+#define FLASH_OPTSR_SWAP_BANK_OPT_Pos        (31U)

+#define FLASH_OPTSR_SWAP_BANK_OPT_Msk        (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */

+#define FLASH_OPTSR_SWAP_BANK_OPT            FLASH_OPTSR_SWAP_BANK_OPT_Msk            /*!< Bank swapping option status bit */

+

+/*******************  Bits definition for FLASH_OPTCCR register  *******************/

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos    (30U)

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk    (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR        FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk            /*!< OPTCHANGEERR reset bit */

+

+/*******************  Bits definition for FLASH_PRAR register  *********************/

+#define FLASH_PRAR_PROT_AREA_START_Pos       (0U)

+#define FLASH_PRAR_PROT_AREA_START_Msk       (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */

+#define FLASH_PRAR_PROT_AREA_START           FLASH_PRAR_PROT_AREA_START_Msk              /*!< PCROP area start status bits */

+#define FLASH_PRAR_PROT_AREA_END_Pos         (16U)

+#define FLASH_PRAR_PROT_AREA_END_Msk         (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */

+#define FLASH_PRAR_PROT_AREA_END             FLASH_PRAR_PROT_AREA_END_Msk              /*!< PCROP area end status bits */

+#define FLASH_PRAR_DMEP_Pos                  (31U)

+#define FLASH_PRAR_DMEP_Msk                  (0x1UL << FLASH_PRAR_DMEP_Pos)    /*!< 0x80000000 */

+#define FLASH_PRAR_DMEP                      FLASH_PRAR_DMEP_Msk               /*!< PCROP protected erase enable option status bit */

+

+/*******************  Bits definition for FLASH_SCAR register  *********************/

+#define FLASH_SCAR_SEC_AREA_START_Pos        (0U)

+#define FLASH_SCAR_SEC_AREA_START_Msk        (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */

+#define FLASH_SCAR_SEC_AREA_START            FLASH_SCAR_SEC_AREA_START_Msk              /*!< Secure-only area start status bits */

+#define FLASH_SCAR_SEC_AREA_END_Pos          (16U)

+#define FLASH_SCAR_SEC_AREA_END_Msk          (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */

+#define FLASH_SCAR_SEC_AREA_END              FLASH_SCAR_SEC_AREA_END_Msk              /*!< Secure-only area end status bits */

+#define FLASH_SCAR_DMES_Pos                  (31U)

+#define FLASH_SCAR_DMES_Msk                  (0x1UL << FLASH_SCAR_DMES_Pos)    /*!< 0x80000000 */

+#define FLASH_SCAR_DMES                      FLASH_SCAR_DMES_Msk               /*!< Secure access protected erase enable option status bit */

+

+/*******************  Bits definition for FLASH_WPSN register  *********************/

+#define FLASH_WPSN_WRPSN_Pos                 (0U)

+#define FLASH_WPSN_WRPSN_Msk                 (0xFFFFFFFFUL << FLASH_WPSN_WRPSN_Pos)  /*!< 0xFFFFFFFF */

+#define FLASH_WPSN_WRPSN                     FLASH_WPSN_WRPSN_Msk              /*!< Sector write protection option status byte */

+

+/*******************  Bits definition for FLASH_BOOT_CUR register  ****************/

+#define FLASH_BOOT_ADD0_Pos                  (0U)

+#define FLASH_BOOT_ADD0_Msk                  (0xFFFFUL << FLASH_BOOT_ADD0_Pos) /*!< 0x0000FFFF */

+#define FLASH_BOOT_ADD0                      FLASH_BOOT_ADD0_Msk               /*!< Arm Cortex-M7 boot address 0 */

+#define FLASH_BOOT_ADD1_Pos                  (16U)

+#define FLASH_BOOT_ADD1_Msk                  (0xFFFFUL << FLASH_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */

+#define FLASH_BOOT_ADD1                      FLASH_BOOT_ADD1_Msk               /*!< Arm Cortex-M7 boot address 1 */

+

+

+/*******************  Bits definition for FLASH_CRCCR register  ********************/

+#define FLASH_CRCCR_CRC_SECT_Pos             (0U)

+#define FLASH_CRCCR_CRC_SECT_Msk             (0x3FUL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x0000003F */

+#define FLASH_CRCCR_CRC_SECT                 FLASH_CRCCR_CRC_SECT_Msk             /*!< CRC sector number */

+#define FLASH_CRCCR_CRC_BY_SECT_Pos          (8U)

+#define FLASH_CRCCR_CRC_BY_SECT_Msk          (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */

+#define FLASH_CRCCR_CRC_BY_SECT              FLASH_CRCCR_CRC_BY_SECT_Msk            /*!< CRC sector mode select bit */

+#define FLASH_CRCCR_ADD_SECT_Pos             (9U)

+#define FLASH_CRCCR_ADD_SECT_Msk             (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */

+#define FLASH_CRCCR_ADD_SECT                 FLASH_CRCCR_ADD_SECT_Msk            /*!< CRC sector select bit */

+#define FLASH_CRCCR_CLEAN_SECT_Pos           (10U)

+#define FLASH_CRCCR_CLEAN_SECT_Msk           (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */

+#define FLASH_CRCCR_CLEAN_SECT               FLASH_CRCCR_CLEAN_SECT_Msk            /*!< CRC sector list clear bit */

+#define FLASH_CRCCR_START_CRC_Pos            (16U)

+#define FLASH_CRCCR_START_CRC_Msk            (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */

+#define FLASH_CRCCR_START_CRC                FLASH_CRCCR_START_CRC_Msk            /*!< CRC start bit */

+#define FLASH_CRCCR_CLEAN_CRC_Pos            (17U)

+#define FLASH_CRCCR_CLEAN_CRC_Msk            (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */

+#define FLASH_CRCCR_CLEAN_CRC                FLASH_CRCCR_CLEAN_CRC_Msk            /*!< CRC clear bit */

+#define FLASH_CRCCR_CRC_BURST_Pos            (20U)

+#define FLASH_CRCCR_CRC_BURST_Msk            (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */

+#define FLASH_CRCCR_CRC_BURST                FLASH_CRCCR_CRC_BURST_Msk            /*!< CRC burst size */

+#define FLASH_CRCCR_CRC_BURST_0              (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */

+#define FLASH_CRCCR_CRC_BURST_1              (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */

+#define FLASH_CRCCR_ALL_BANK_Pos             (22U)

+#define FLASH_CRCCR_ALL_BANK_Msk             (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */

+#define FLASH_CRCCR_ALL_BANK                 FLASH_CRCCR_ALL_BANK_Msk            /*!< CRC select bit */

+

+/*******************  Bits definition for FLASH_CRCSADD register  ****************/

+#define FLASH_CRCSADD_CRC_START_ADDR_Pos     (0U)

+#define FLASH_CRCSADD_CRC_START_ADDR_Msk     (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCSADD_CRC_START_ADDR         FLASH_CRCSADD_CRC_START_ADDR_Msk                   /*!< CRC start address */

+

+/*******************  Bits definition for FLASH_CRCEADD register  ****************/

+#define FLASH_CRCEADD_CRC_END_ADDR_Pos       (0U)

+#define FLASH_CRCEADD_CRC_END_ADDR_Msk       (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCEADD_CRC_END_ADDR           FLASH_CRCEADD_CRC_END_ADDR_Msk                   /*!< CRC end address */

+

+/*******************  Bits definition for FLASH_CRCDATA register  ***************/

+#define FLASH_CRCDATA_CRC_DATA_Pos           (0U)

+#define FLASH_CRCDATA_CRC_DATA_Msk           (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCDATA_CRC_DATA               FLASH_CRCDATA_CRC_DATA_Msk                   /*!< CRC result */

+

+/*******************  Bits definition for FLASH_ECC_FA register  *******************/

+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos       (0U)

+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk       (0xFFFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x0000FFFF */

+#define FLASH_ECC_FA_FAIL_ECC_ADDR           FLASH_ECC_FA_FAIL_ECC_ADDR_Msk               /*!< ECC error address */

+#define FLASH_ECC_FA_OTP_FAIL_ECC_Pos        (31U)

+#define FLASH_ECC_FA_OTP_FAIL_ECC_Msk        (0x1UL << FLASH_ECC_FA_OTP_FAIL_ECC_Pos) /*!< 0x80000000 */

+#define FLASH_ECC_FA_OTP_FAIL_ECC            FLASH_ECC_FA_OTP_FAIL_ECC_Msk            /*!< OTP ECC error bit */

+

+/*******************  Bits definition for FLASH_OTPBL register  *******************/

+#define FLASH_OTPBL_LOCKBL_Pos               (0U)

+#define FLASH_OTPBL_LOCKBL_Msk               (0xFFFFUL << FLASH_OTPBL_LOCKBL_Pos) /*!< 0x0000FFFF */

+#define FLASH_OTPBL_LOCKBL                   FLASH_OTPBL_LOCKBL_Msk               /*!< OTP Block Lock */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          Flexible Memory Controller                        */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for FMC_BCR1 register  *******************/

+#define FMC_BCR1_CCLKEN_Pos        (20U)

+#define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */

+#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continous clock enable     */

+#define FMC_BCR1_WFDIS_Pos         (21U)

+#define FMC_BCR1_WFDIS_Msk         (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */

+#define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */

+

+#define FMC_BCR1_BMAP_Pos          (24U)

+#define FMC_BCR1_BMAP_Msk          (0x3UL << FMC_BCR1_BMAP_Pos)                /*!< 0x03000000 */

+#define FMC_BCR1_BMAP              FMC_BCR1_BMAP_Msk                           /*!<BMAP[1:0] FMC bank mapping */

+#define FMC_BCR1_BMAP_0            (0x1UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x01000000 */

+#define FMC_BCR1_BMAP_1            (0x2UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x02000000 */

+

+#define FMC_BCR1_FMCEN_Pos         (31U)

+#define FMC_BCR1_FMCEN_Msk         (0x1UL << FMC_BCR1_FMCEN_Pos)               /*!< 0x80000000 */

+#define FMC_BCR1_FMCEN             FMC_BCR1_FMCEN_Msk                          /*!<FMC controller Enable */

+/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/

+#define FMC_BCRx_MBKEN_Pos         (0U)

+#define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */

+#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */

+#define FMC_BCRx_MUXEN_Pos         (1U)

+#define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */

+#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */

+

+#define FMC_BCRx_MTYP_Pos          (2U)

+#define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */

+#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */

+#define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000004 */

+#define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000008 */

+

+#define FMC_BCRx_MWID_Pos          (4U)

+#define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */

+#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */

+#define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000010 */

+#define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000020 */

+

+#define FMC_BCRx_FACCEN_Pos        (6U)

+#define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */

+#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */

+#define FMC_BCRx_BURSTEN_Pos       (8U)

+#define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */

+#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */

+#define FMC_BCRx_WAITPOL_Pos       (9U)

+#define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */

+#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */

+#define FMC_BCRx_WAITCFG_Pos       (11U)

+#define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */

+#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */

+#define FMC_BCRx_WREN_Pos          (12U)

+#define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */

+#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */

+#define FMC_BCRx_WAITEN_Pos        (13U)

+#define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */

+#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */

+#define FMC_BCRx_EXTMOD_Pos        (14U)

+#define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */

+#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */

+#define FMC_BCRx_ASYNCWAIT_Pos     (15U)

+#define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */

+#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */

+

+#define FMC_BCRx_CPSIZE_Pos        (16U)

+#define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */

+#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<PSIZE[2:0] bits CRAM Page Size */

+#define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00010000 */

+#define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00020000 */

+#define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00040000 */

+

+#define FMC_BCRx_CBURSTRW_Pos      (19U)

+#define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */

+#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */

+

+/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/

+#define FMC_BTRx_ADDSET_Pos        (0U)

+#define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */

+#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */

+#define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000001 */

+#define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000002 */

+#define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000004 */

+#define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000008 */

+

+#define FMC_BTRx_ADDHLD_Pos        (4U)

+#define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */

+#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */

+#define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000010 */

+#define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000020 */

+#define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000040 */

+#define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000080 */

+

+#define FMC_BTRx_DATAST_Pos        (8U)

+#define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */

+#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */

+#define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000100 */

+#define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000200 */

+#define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000400 */

+#define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000800 */

+#define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00001000 */

+#define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00002000 */

+#define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00004000 */

+#define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00008000 */

+

+#define FMC_BTRx_BUSTURN_Pos       (16U)

+#define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */

+#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */

+#define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00010000 */

+#define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00020000 */

+#define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00040000 */

+#define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00080000 */

+

+#define FMC_BTRx_CLKDIV_Pos        (20U)

+#define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */

+#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */

+#define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00100000 */

+#define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00200000 */

+#define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00400000 */

+#define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00800000 */

+

+#define FMC_BTRx_DATLAT_Pos        (24U)

+#define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */

+#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */

+#define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x01000000 */

+#define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x02000000 */

+#define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x04000000 */

+#define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x08000000 */

+

+#define FMC_BTRx_ACCMOD_Pos        (28U)

+#define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */

+#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */

+#define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x10000000 */

+#define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x20000000 */

+

+/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/

+#define FMC_BWTRx_ADDSET_Pos       (0U)

+#define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */

+#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */

+#define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000001 */

+#define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000002 */

+#define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000004 */

+#define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000008 */

+

+#define FMC_BWTRx_ADDHLD_Pos       (4U)

+#define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */

+#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */

+#define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000010 */

+#define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000020 */

+#define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000040 */

+#define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000080 */

+

+#define FMC_BWTRx_DATAST_Pos       (8U)

+#define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */

+#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */

+#define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000100 */

+#define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000200 */

+#define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000400 */

+#define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000800 */

+#define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00001000 */

+#define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00002000 */

+#define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00004000 */

+#define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00008000 */

+

+#define FMC_BWTRx_BUSTURN_Pos      (16U)

+#define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */

+#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */

+#define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00010000 */

+#define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00020000 */

+#define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00040000 */

+#define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00080000 */

+

+#define FMC_BWTRx_ACCMOD_Pos       (28U)

+#define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */

+#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */

+#define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x10000000 */

+#define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x20000000 */

+

+/******************  Bit definition for FMC_PCR register  *******************/

+#define FMC_PCR_PWAITEN_Pos        (1U)

+#define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */

+#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */

+#define FMC_PCR_PBKEN_Pos          (2U)

+#define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */

+#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */

+

+#define FMC_PCR_PWID_Pos           (4U)

+#define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */

+#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */

+#define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */

+#define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */

+

+#define FMC_PCR_ECCEN_Pos          (6U)

+#define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */

+#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */

+

+#define FMC_PCR_TCLR_Pos           (9U)

+#define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */

+#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */

+#define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */

+#define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */

+#define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */

+#define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */

+

+#define FMC_PCR_TAR_Pos            (13U)

+#define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */

+#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */

+#define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */

+#define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */

+#define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */

+#define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */

+

+#define FMC_PCR_ECCPS_Pos          (17U)

+#define FMC_PCR_ECCPS_Msk          (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */

+#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */

+#define FMC_PCR_ECCPS_0            (0x1UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */

+#define FMC_PCR_ECCPS_1            (0x2UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */

+#define FMC_PCR_ECCPS_2            (0x4UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */

+

+/*******************  Bit definition for FMC_SR register  *******************/

+#define FMC_SR_IRS_Pos             (0U)

+#define FMC_SR_IRS_Msk             (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */

+#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */

+#define FMC_SR_ILS_Pos             (1U)

+#define FMC_SR_ILS_Msk             (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */

+#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */

+#define FMC_SR_IFS_Pos             (2U)

+#define FMC_SR_IFS_Msk             (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */

+#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */

+#define FMC_SR_IREN_Pos            (3U)

+#define FMC_SR_IREN_Msk            (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */

+#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */

+#define FMC_SR_ILEN_Pos            (4U)

+#define FMC_SR_ILEN_Msk            (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */

+#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */

+#define FMC_SR_IFEN_Pos            (5U)

+#define FMC_SR_IFEN_Msk            (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */

+#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */

+#define FMC_SR_FEMPT_Pos           (6U)

+#define FMC_SR_FEMPT_Msk           (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */

+#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */

+

+/******************  Bit definition for FMC_PMEM register  ******************/

+#define FMC_PMEM_MEMSET_Pos       (0U)

+#define FMC_PMEM_MEMSET_Msk       (0xFFUL << FMC_PMEM_MEMSET_Pos)            /*!< 0x000000FF */

+#define FMC_PMEM_MEMSET           FMC_PMEM_MEMSET_Msk                        /*!<MEMSET[7:0] bits (Common memory setup time) */

+#define FMC_PMEM_MEMSET_0         (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */

+#define FMC_PMEM_MEMSET_1         (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */

+#define FMC_PMEM_MEMSET_2         (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */

+#define FMC_PMEM_MEMSET_3         (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */

+#define FMC_PMEM_MEMSET_4         (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */

+#define FMC_PMEM_MEMSET_5         (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */

+#define FMC_PMEM_MEMSET_6         (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */

+#define FMC_PMEM_MEMSET_7         (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */

+

+#define FMC_PMEM_MEMWAIT_Pos      (8U)

+#define FMC_PMEM_MEMWAIT_Msk      (0xFFUL << FMC_PMEM_MEMWAIT_Pos)           /*!< 0x0000FF00 */

+#define FMC_PMEM_MEMWAIT          FMC_PMEM_MEMWAIT_Msk                       /*!<MEMWAIT[7:0] bits (Common memory wait time) */

+#define FMC_PMEM_MEMWAIT_0        (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */

+#define FMC_PMEM_MEMWAIT_1        (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */

+#define FMC_PMEM_MEMWAIT_2        (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */

+#define FMC_PMEM_MEMWAIT_3        (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */

+#define FMC_PMEM_MEMWAIT_4        (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */

+#define FMC_PMEM_MEMWAIT_5        (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */

+#define FMC_PMEM_MEMWAIT_6        (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */

+#define FMC_PMEM_MEMWAIT_7        (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */

+

+#define FMC_PMEM_MEMHOLD_Pos      (16U)

+#define FMC_PMEM_MEMHOLD_Msk      (0xFFUL << FMC_PMEM_MEMHOLD_Pos)           /*!< 0x00FF0000 */

+#define FMC_PMEM_MEMHOLD          FMC_PMEM_MEMHOLD_Msk                       /*!<MEMHOLD[7:0] bits (Common memory hold time) */

+#define FMC_PMEM_MEMHOLD_0        (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */

+#define FMC_PMEM_MEMHOLD_1        (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */

+#define FMC_PMEM_MEMHOLD_2        (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */

+#define FMC_PMEM_MEMHOLD_3        (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */

+#define FMC_PMEM_MEMHOLD_4        (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */

+#define FMC_PMEM_MEMHOLD_5        (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */

+#define FMC_PMEM_MEMHOLD_6        (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */

+#define FMC_PMEM_MEMHOLD_7        (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */

+

+#define FMC_PMEM_MEMHIZ_Pos       (24U)

+#define FMC_PMEM_MEMHIZ_Msk       (0xFFUL << FMC_PMEM_MEMHIZ_Pos)            /*!< 0xFF000000 */

+#define FMC_PMEM_MEMHIZ           FMC_PMEM_MEMHIZ_Msk                        /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */

+#define FMC_PMEM_MEMHIZ_0         (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */

+#define FMC_PMEM_MEMHIZ_1         (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */

+#define FMC_PMEM_MEMHIZ_2         (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */

+#define FMC_PMEM_MEMHIZ_3         (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */

+#define FMC_PMEM_MEMHIZ_4         (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */

+#define FMC_PMEM_MEMHIZ_5         (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */

+#define FMC_PMEM_MEMHIZ_6         (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */

+#define FMC_PMEM_MEMHIZ_7         (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */

+

+/******************  Bit definition for FMC_PATT register  ******************/

+#define FMC_PATT_ATTSET_Pos       (0U)

+#define FMC_PATT_ATTSET_Msk       (0xFFUL << FMC_PATT_ATTSET_Pos)            /*!< 0x000000FF */

+#define FMC_PATT_ATTSET           FMC_PATT_ATTSET_Msk                        /*!<ATTSET[7:0] bits (Attribute memory setup time) */

+#define FMC_PATT_ATTSET_0         (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */

+#define FMC_PATT_ATTSET_1         (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */

+#define FMC_PATT_ATTSET_2         (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */

+#define FMC_PATT_ATTSET_3         (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */

+#define FMC_PATT_ATTSET_4         (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */

+#define FMC_PATT_ATTSET_5         (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */

+#define FMC_PATT_ATTSET_6         (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */

+#define FMC_PATT_ATTSET_7         (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */

+

+#define FMC_PATT_ATTWAIT_Pos      (8U)

+#define FMC_PATT_ATTWAIT_Msk      (0xFFUL << FMC_PATT_ATTWAIT_Pos)           /*!< 0x0000FF00 */

+#define FMC_PATT_ATTWAIT          FMC_PATT_ATTWAIT_Msk                       /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */

+#define FMC_PATT_ATTWAIT_0        (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */

+#define FMC_PATT_ATTWAIT_1        (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */

+#define FMC_PATT_ATTWAIT_2        (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */

+#define FMC_PATT_ATTWAIT_3        (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */

+#define FMC_PATT_ATTWAIT_4        (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */

+#define FMC_PATT_ATTWAIT_5        (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */

+#define FMC_PATT_ATTWAIT_6        (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */

+#define FMC_PATT_ATTWAIT_7        (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */

+

+#define FMC_PATT_ATTHOLD_Pos      (16U)

+#define FMC_PATT_ATTHOLD_Msk      (0xFFUL << FMC_PATT_ATTHOLD_Pos)           /*!< 0x00FF0000 */

+#define FMC_PATT_ATTHOLD          FMC_PATT_ATTHOLD_Msk                       /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */

+#define FMC_PATT_ATTHOLD_0        (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */

+#define FMC_PATT_ATTHOLD_1        (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */

+#define FMC_PATT_ATTHOLD_2        (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */

+#define FMC_PATT_ATTHOLD_3        (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */

+#define FMC_PATT_ATTHOLD_4        (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */

+#define FMC_PATT_ATTHOLD_5        (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */

+#define FMC_PATT_ATTHOLD_6        (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */

+#define FMC_PATT_ATTHOLD_7        (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */

+

+#define FMC_PATT_ATTHIZ_Pos       (24U)

+#define FMC_PATT_ATTHIZ_Msk       (0xFFUL << FMC_PATT_ATTHIZ_Pos)            /*!< 0xFF000000 */

+#define FMC_PATT_ATTHIZ           FMC_PATT_ATTHIZ_Msk                        /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */

+#define FMC_PATT_ATTHIZ_0         (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */

+#define FMC_PATT_ATTHIZ_1         (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */

+#define FMC_PATT_ATTHIZ_2         (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */

+#define FMC_PATT_ATTHIZ_3         (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */

+#define FMC_PATT_ATTHIZ_4         (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */

+#define FMC_PATT_ATTHIZ_5         (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */

+#define FMC_PATT_ATTHIZ_6         (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */

+#define FMC_PATT_ATTHIZ_7         (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */

+

+/******************  Bit definition for FMC_ECCR3 register  ******************/

+#define FMC_ECCR3_ECC3_Pos         (0U)

+#define FMC_ECCR3_ECC3_Msk         (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)        /*!< 0xFFFFFFFF */

+#define FMC_ECCR3_ECC3             FMC_ECCR3_ECC3_Msk                          /*!<ECC result */

+

+/******************  Bit definition for FMC_SDCRx registers (x=1..4)  *********/

+#define FMC_SDCRx_NC_Pos           (0U)

+#define FMC_SDCRx_NC_Msk           (0x3UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000003 */

+#define FMC_SDCRx_NC               FMC_SDCRx_NC_Msk                            /*!<NC[1:0] bits (Number of column bits) */

+#define FMC_SDCRx_NC_0             (0x1UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000001 */

+#define FMC_SDCRx_NC_1             (0x2UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000002 */

+

+#define FMC_SDCRx_NR_Pos           (2U)

+#define FMC_SDCRx_NR_Msk           (0x3UL << FMC_SDCRx_NR_Pos)                 /*!< 0x0000000C */

+#define FMC_SDCRx_NR               FMC_SDCRx_NR_Msk                            /*!<NR[1:0] bits (Number of row bits) */

+#define FMC_SDCRx_NR_0             (0x1UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000004 */

+#define FMC_SDCRx_NR_1             (0x2UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000008 */

+

+#define FMC_SDCRx_MWID_Pos         (4U)

+#define FMC_SDCRx_MWID_Msk         (0x3UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000030 */

+#define FMC_SDCRx_MWID             FMC_SDCRx_MWID_Msk                          /*!<NR[1:0] bits (Number of row bits) */

+#define FMC_SDCRx_MWID_0           (0x1UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000010 */

+#define FMC_SDCRx_MWID_1           (0x2UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000020 */

+

+#define FMC_SDCRx_NB_Pos           (6U)

+#define FMC_SDCRx_NB_Msk           (0x1UL << FMC_SDCRx_NB_Pos)                 /*!< 0x00000040 */

+#define FMC_SDCRx_NB               FMC_SDCRx_NB_Msk                            /*!<Number of internal bank */

+

+#define FMC_SDCRx_CAS_Pos          (7U)

+#define FMC_SDCRx_CAS_Msk          (0x3UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000180 */

+#define FMC_SDCRx_CAS              FMC_SDCRx_CAS_Msk                           /*!<CAS[1:0] bits (CAS latency) */

+#define FMC_SDCRx_CAS_0            (0x1UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000080 */

+#define FMC_SDCRx_CAS_1            (0x2UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000100 */

+

+#define FMC_SDCRx_WP_Pos           (9U)

+#define FMC_SDCRx_WP_Msk           (0x1UL << FMC_SDCRx_WP_Pos)                 /*!< 0x00000200 */

+#define FMC_SDCRx_WP               FMC_SDCRx_WP_Msk                            /*!<Write protection */

+

+#define FMC_SDCRx_SDCLK_Pos        (10U)

+#define FMC_SDCRx_SDCLK_Msk        (0x3UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000C00 */

+#define FMC_SDCRx_SDCLK            FMC_SDCRx_SDCLK_Msk                         /*!<SDRAM clock configuration */

+#define FMC_SDCRx_SDCLK_0          (0x1UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000400 */

+#define FMC_SDCRx_SDCLK_1          (0x2UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000800 */

+

+#define FMC_SDCRx_RBURST_Pos       (12U)

+#define FMC_SDCRx_RBURST_Msk       (0x1UL << FMC_SDCRx_RBURST_Pos)             /*!< 0x00001000 */

+#define FMC_SDCRx_RBURST           FMC_SDCRx_RBURST_Msk                        /*!<Read burst */

+

+#define FMC_SDCRx_RPIPE_Pos        (13U)

+#define FMC_SDCRx_RPIPE_Msk        (0x3UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00006000 */

+#define FMC_SDCRx_RPIPE            FMC_SDCRx_RPIPE_Msk                         /*!<Write protection */

+#define FMC_SDCRx_RPIPE_0          (0x1UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00002000 */

+#define FMC_SDCRx_RPIPE_1          (0x2UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00004000 */

+

+/******************  Bit definition for FMC_SDTRx(1,2) register  ******************/

+#define FMC_SDTRx_TMRD_Pos         (0U)

+#define FMC_SDTRx_TMRD_Msk         (0xFUL << FMC_SDTRx_TMRD_Pos)               /*!< 0x0000000F */

+#define FMC_SDTRx_TMRD             FMC_SDTRx_TMRD_Msk                          /*!<TMRD[3:0] bits (Load mode register to active) */

+#define FMC_SDTRx_TMRD_0           (0x1UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000001 */

+#define FMC_SDTRx_TMRD_1           (0x2UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000002 */

+#define FMC_SDTRx_TMRD_2           (0x4UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000004 */

+#define FMC_SDTRx_TMRD_3           (0x8UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000008 */

+

+#define FMC_SDTRx_TXSR_Pos         (4U)

+#define FMC_SDTRx_TXSR_Msk         (0xFUL << FMC_SDTRx_TXSR_Pos)               /*!< 0x000000F0 */

+#define FMC_SDTRx_TXSR             FMC_SDTRx_TXSR_Msk                          /*!<TXSR[3:0] bits (Exit self refresh) */

+#define FMC_SDTRx_TXSR_0           (0x1UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000010 */

+#define FMC_SDTRx_TXSR_1           (0x2UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000020 */

+#define FMC_SDTRx_TXSR_2           (0x4UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000040 */

+#define FMC_SDTRx_TXSR_3           (0x8UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000080 */

+

+#define FMC_SDTRx_TRAS_Pos         (8U)

+#define FMC_SDTRx_TRAS_Msk         (0xFUL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000F00 */

+#define FMC_SDTRx_TRAS             FMC_SDTRx_TRAS_Msk                          /*!<TRAS[3:0] bits (Self refresh time) */

+#define FMC_SDTRx_TRAS_0           (0x1UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000100 */

+#define FMC_SDTRx_TRAS_1           (0x2UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000200 */

+#define FMC_SDTRx_TRAS_2           (0x4UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000400 */

+#define FMC_SDTRx_TRAS_3           (0x8UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000800 */

+

+#define FMC_SDTRx_TRC_Pos          (12U)

+#define FMC_SDTRx_TRC_Msk          (0xFUL << FMC_SDTRx_TRC_Pos)                /*!< 0x0000F000 */

+#define FMC_SDTRx_TRC              FMC_SDTRx_TRC_Msk                           /*!<TRC[2:0] bits (Row cycle delay) */

+#define FMC_SDTRx_TRC_0            (0x1UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00001000 */

+#define FMC_SDTRx_TRC_1            (0x2UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00002000 */

+#define FMC_SDTRx_TRC_2            (0x4UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00004000 */

+

+#define FMC_SDTRx_TWR_Pos          (16U)

+#define FMC_SDTRx_TWR_Msk          (0xFUL << FMC_SDTRx_TWR_Pos)                /*!< 0x000F0000 */

+#define FMC_SDTRx_TWR              FMC_SDTRx_TWR_Msk                           /*!<TRC[2:0] bits (Write recovery delay) */

+#define FMC_SDTRx_TWR_0            (0x1UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00010000 */

+#define FMC_SDTRx_TWR_1            (0x2UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00020000 */

+#define FMC_SDTRx_TWR_2            (0x4UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00040000 */

+

+#define FMC_SDTRx_TRP_Pos          (20U)

+#define FMC_SDTRx_TRP_Msk          (0xFUL << FMC_SDTRx_TRP_Pos)                /*!< 0x00F00000 */

+#define FMC_SDTRx_TRP              FMC_SDTRx_TRP_Msk                           /*!<TRP[2:0] bits (Row precharge delay) */

+#define FMC_SDTRx_TRP_0            (0x1UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00100000 */

+#define FMC_SDTRx_TRP_1            (0x2UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00200000 */

+#define FMC_SDTRx_TRP_2            (0x4UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00400000 */

+

+#define FMC_SDTRx_TRCD_Pos         (24U)

+#define FMC_SDTRx_TRCD_Msk         (0xFUL << FMC_SDTRx_TRCD_Pos)               /*!< 0x0F000000 */

+#define FMC_SDTRx_TRCD             FMC_SDTRx_TRCD_Msk                          /*!<TRP[2:0] bits (Row to column delay) */

+#define FMC_SDTRx_TRCD_0           (0x1UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x01000000 */

+#define FMC_SDTRx_TRCD_1           (0x2UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x02000000 */

+#define FMC_SDTRx_TRCD_2           (0x4UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x04000000 */

+

+/******************  Bit definition for FMC_SDCMR register  ******************/

+#define FMC_SDCMR_MODE_Pos         (0U)

+#define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */

+#define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */

+#define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */

+#define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */

+#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */

+

+#define FMC_SDCMR_CTB2_Pos         (3U)

+#define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */

+#define FMC_SDCMR_CTB2             FMC_SDCMR_CTB2_Msk                          /*!<Command target 2 */

+

+#define FMC_SDCMR_CTB1_Pos         (4U)

+#define FMC_SDCMR_CTB1_Msk         (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */

+#define FMC_SDCMR_CTB1             FMC_SDCMR_CTB1_Msk                          /*!<Command target 1 */

+

+#define FMC_SDCMR_NRFS_Pos         (5U)

+#define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */

+#define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!<NRFS[3:0] bits (Number of auto-refresh) */

+#define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000020 */

+#define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000040 */

+#define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000080 */

+#define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000100 */

+

+#define FMC_SDCMR_MRD_Pos          (9U)

+#define FMC_SDCMR_MRD_Msk          (0x1FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */

+#define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!<MRD[12:0] bits (Mode register definition) */

+

+/******************  Bit definition for FMC_SDRTR register  ******************/

+#define FMC_SDRTR_CRE_Pos          (0U)

+#define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */

+#define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!<Clear refresh error flag */

+

+#define FMC_SDRTR_COUNT_Pos        (1U)

+#define FMC_SDRTR_COUNT_Msk        (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */

+#define FMC_SDRTR_COUNT            FMC_SDRTR_COUNT_Msk                         /*!<COUNT[12:0] bits (Refresh timer count) */

+

+#define FMC_SDRTR_REIE_Pos         (14U)

+#define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */

+#define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!<RES interupt enable */

+

+/******************  Bit definition for FMC_SDSR register  ******************/

+#define FMC_SDSR_RE_Pos            (0U)

+#define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */

+#define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!<Refresh error flag */

+

+#define FMC_SDSR_MODES1_Pos        (1U)

+#define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */

+#define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!<MODES1[1:0]bits (Status mode for bank 1) */

+#define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000002 */

+#define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000004 */

+

+#define FMC_SDSR_MODES2_Pos        (3U)

+#define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */

+#define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!<MODES2[1:0]bits (Status mode for bank 2) */

+#define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000008 */

+#define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000010 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                       Graphic MMU (GFXMMU)                                 */

+/*                                                                            */

+/******************************************************************************/

+/****************** Bits definition for GFXMMU_CR register ********************/

+#define GFXMMU_CR_B0OIE_Pos                (0U)

+#define GFXMMU_CR_B0OIE_Msk                (0x1UL << GFXMMU_CR_B0OIE_Pos)       /*!< 0x00000001 */

+#define GFXMMU_CR_B0OIE                    GFXMMU_CR_B0OIE_Msk                 /*!< Buffer 0 overflow interrupt enable */

+#define GFXMMU_CR_B1OIE_Pos                (1U)

+#define GFXMMU_CR_B1OIE_Msk                (0x1UL << GFXMMU_CR_B1OIE_Pos)       /*!< 0x00000002 */

+#define GFXMMU_CR_B1OIE                    GFXMMU_CR_B1OIE_Msk                 /*!< Buffer 1 overflow interrupt enable */

+#define GFXMMU_CR_B2OIE_Pos                (2U)

+#define GFXMMU_CR_B2OIE_Msk                (0x1UL << GFXMMU_CR_B2OIE_Pos)       /*!< 0x00000004 */

+#define GFXMMU_CR_B2OIE                    GFXMMU_CR_B2OIE_Msk                 /*!< Buffer 2 overflow interrupt enable */

+#define GFXMMU_CR_B3OIE_Pos                (3U)

+#define GFXMMU_CR_B3OIE_Msk                (0x1UL << GFXMMU_CR_B3OIE_Pos)       /*!< 0x00000008 */

+#define GFXMMU_CR_B3OIE                    GFXMMU_CR_B3OIE_Msk                 /*!< Buffer 3 overflow interrupt enable */

+#define GFXMMU_CR_AMEIE_Pos                (4U)

+#define GFXMMU_CR_AMEIE_Msk                (0x1UL << GFXMMU_CR_AMEIE_Pos)       /*!< 0x00000010 */

+#define GFXMMU_CR_AMEIE                    GFXMMU_CR_AMEIE_Msk                 /*!< AHB master error interrupt enable */

+#define GFXMMU_CR_192BM_Pos                (6U)

+#define GFXMMU_CR_192BM_Msk                (0x1UL << GFXMMU_CR_192BM_Pos)       /*!< 0x00000040 */

+#define GFXMMU_CR_192BM                    GFXMMU_CR_192BM_Msk                 /*!< 192 block mode */

+#define GFXMMU_CR_CE_Pos                   (7U)

+#define GFXMMU_CR_CE_Msk                   (0x1UL << GFXMMU_CR_CE_Pos)          /*!< 0x00000080 */

+#define GFXMMU_CR_CE                       GFXMMU_CR_CE_Msk                    /*!< Cache Enable */

+#define GFXMMU_CR_CL_Pos                   (8U)

+#define GFXMMU_CR_CL_Msk                   (0x1UL << GFXMMU_CR_CL_Pos)          /*!< 0x00000100 */

+#define GFXMMU_CR_CL                       GFXMMU_CR_CL_Msk                    /*!< Cache Lock */

+#define GFXMMU_CR_CLB_Pos                  (9U)

+#define GFXMMU_CR_CLB_Msk                  (0x3UL << GFXMMU_CR_CLB_Pos)         /*!< 0x00000600 */

+#define GFXMMU_CR_CLB                      GFXMMU_CR_CLB_Msk                   /*!< CLB[1:0]: Cache Lock Buffer */

+#define GFXMMU_CR_CLB_0                    (0x1UL << GFXMMU_CR_CLB_Pos)         /*!< Cache locked on buffer 1 */

+#define GFXMMU_CR_CLB_1                    (0x2UL << GFXMMU_CR_CLB_Pos)         /*!< Cache locked on buffer 2 */

+#define GFXMMU_CR_FC_Pos                   (11U)

+#define GFXMMU_CR_FC_Msk                   (0x1UL << GFXMMU_CR_FC_Pos)          /*!< 0x00000800 */

+#define GFXMMU_CR_FC                       GFXMMU_CR_FC_Msk                    /*!< Force Caching */

+#define GFXMMU_CR_PD_Pos                   (12U)

+#define GFXMMU_CR_PD_Msk                   (0x1UL << GFXMMU_CR_PD_Pos)          /*!< 0x00001000 */

+#define GFXMMU_CR_PD                       GFXMMU_CR_PD_Msk                    /*!< Prefetch Disable */

+#define GFXMMU_CR_OC_Pos                   (16U)

+#define GFXMMU_CR_OC_Msk                   (0x1UL << GFXMMU_CR_OC_Pos)          /*!< 0x00002000 */

+#define GFXMMU_CR_OC                       GFXMMU_CR_OC_Msk                    /*!< Outter Cachability */

+#define GFXMMU_CR_OB_Pos                   (17U)

+#define GFXMMU_CR_OB_Msk                   (0x1UL << GFXMMU_CR_OB_Pos)          /*!< 0x00002000 */

+#define GFXMMU_CR_OB                       GFXMMU_CR_OB_Msk                    /*!< Outter Bufferability */

+

+/****************** Bits definition for GFXMMU_SR register ********************/

+#define GFXMMU_SR_B0OF_Pos                 (0U)

+#define GFXMMU_SR_B0OF_Msk                 (0x1UL << GFXMMU_SR_B0OF_Pos)        /*!< 0x00000001 */

+#define GFXMMU_SR_B0OF                     GFXMMU_SR_B0OF_Msk                  /*!< Buffer 0 overflow flag */

+#define GFXMMU_SR_B1OF_Pos                 (1U)

+#define GFXMMU_SR_B1OF_Msk                 (0x1UL << GFXMMU_SR_B1OF_Pos)        /*!< 0x00000002 */

+#define GFXMMU_SR_B1OF                     GFXMMU_SR_B1OF_Msk                  /*!< Buffer 1 overflow flag */

+#define GFXMMU_SR_B2OF_Pos                 (2U)

+#define GFXMMU_SR_B2OF_Msk                 (0x1UL << GFXMMU_SR_B2OF_Pos)        /*!< 0x00000004 */

+#define GFXMMU_SR_B2OF                     GFXMMU_SR_B2OF_Msk                  /*!< Buffer 2 overflow flag */

+#define GFXMMU_SR_B3OF_Pos                 (3U)

+#define GFXMMU_SR_B3OF_Msk                 (0x1UL << GFXMMU_SR_B3OF_Pos)        /*!< 0x00000008 */

+#define GFXMMU_SR_B3OF                     GFXMMU_SR_B3OF_Msk                  /*!< Buffer 3 overflow flag */

+#define GFXMMU_SR_AMEF_Pos                 (4U)

+#define GFXMMU_SR_AMEF_Msk                 (0x1UL << GFXMMU_SR_AMEF_Pos)        /*!< 0x00000010 */

+#define GFXMMU_SR_AMEF                     GFXMMU_SR_AMEF_Msk                  /*!< AHB master error flag */

+

+/****************** Bits definition for GFXMMU_FCR register *******************/

+#define GFXMMU_FCR_CB0OF_Pos               (0U)

+#define GFXMMU_FCR_CB0OF_Msk               (0x1UL << GFXMMU_FCR_CB0OF_Pos)      /*!< 0x00000001 */

+#define GFXMMU_FCR_CB0OF                   GFXMMU_FCR_CB0OF_Msk                /*!< Clear buffer 0 overflow flag */

+#define GFXMMU_FCR_CB1OF_Pos               (1U)

+#define GFXMMU_FCR_CB1OF_Msk               (0x1UL << GFXMMU_FCR_CB1OF_Pos)      /*!< 0x00000002 */

+#define GFXMMU_FCR_CB1OF                   GFXMMU_FCR_CB1OF_Msk                /*!< Clear buffer 1 overflow flag */

+#define GFXMMU_FCR_CB2OF_Pos               (2U)

+#define GFXMMU_FCR_CB2OF_Msk               (0x1UL << GFXMMU_FCR_CB2OF_Pos)      /*!< 0x00000004 */

+#define GFXMMU_FCR_CB2OF                   GFXMMU_FCR_CB2OF_Msk                /*!< Clear buffer 2 overflow flag */

+#define GFXMMU_FCR_CB3OF_Pos               (3U)

+#define GFXMMU_FCR_CB3OF_Msk               (0x1UL << GFXMMU_FCR_CB3OF_Pos)      /*!< 0x00000008 */

+#define GFXMMU_FCR_CB3OF                   GFXMMU_FCR_CB3OF_Msk                /*!< Clear buffer 3 overflow flag */

+#define GFXMMU_FCR_CAMEF_Pos               (4U)

+#define GFXMMU_FCR_CAMEF_Msk               (0x1UL << GFXMMU_FCR_CAMEF_Pos)      /*!< 0x00000010 */

+#define GFXMMU_FCR_CAMEF                   GFXMMU_FCR_CAMEF_Msk                /*!< Clear AHB master error flag */

+

+/****************** Bits definition for GFXMMU_CCR register *******************/

+#define GFXMMU_CCR_FF_Pos                  (0U)

+#define GFXMMU_CCR_FF_Msk                  (0x1UL << GFXMMU_CCR_FF_Pos)         /*!< 0x00000001 */

+#define GFXMMU_CCR_FF                      GFXMMU_CCR_FF_Msk                   /*!< Clear buffer 0 overflow flag */

+#define GFXMMU_CCR_FI_Pos                  (1U)

+#define GFXMMU_CCR_FI_Msk                  (0x1UL << GFXMMU_CCR_FI_Pos)         /*!< 0x00000002 */

+#define GFXMMU_CCR_FI                      GFXMMU_CCR_FI_Msk                   /*!< Clear buffer 1 overflow flag */

+

+/****************** Bits definition for GFXMMU_DVR register *******************/

+#define GFXMMU_DVR_DV_Pos                  (0U)

+#define GFXMMU_DVR_DV_Msk                  (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos)  /*!< 0xFFFFFFFF */

+#define GFXMMU_DVR_DV                      GFXMMU_DVR_DV_Msk                   /*!< DV[31:0] bits (Default value) */

+

+/****************** Bits definition for GFXMMU_B0CR register ******************/

+#define GFXMMU_B0CR_PBO_Pos                (4U)

+#define GFXMMU_B0CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B0CR_PBO_Pos)   /*!< 0x007FFFF0 */

+#define GFXMMU_B0CR_PBO                    GFXMMU_B0CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */

+#define GFXMMU_B0CR_PBBA_Pos               (23U)

+#define GFXMMU_B0CR_PBBA_Msk               (0x1FFUL << GFXMMU_B0CR_PBBA_Pos)    /*!< 0xFF800000 */

+#define GFXMMU_B0CR_PBBA                   GFXMMU_B0CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */

+

+/****************** Bits definition for GFXMMU_B1CR register ******************/

+#define GFXMMU_B1CR_PBO_Pos                (4U)

+#define GFXMMU_B1CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos)   /*!< 0x007FFFF0 */

+#define GFXMMU_B1CR_PBO                    GFXMMU_B1CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */

+#define GFXMMU_B1CR_PBBA_Pos               (23U)

+#define GFXMMU_B1CR_PBBA_Msk               (0x1FFUL << GFXMMU_B1CR_PBBA_Pos)    /*!< 0xFF800000 */

+#define GFXMMU_B1CR_PBBA                   GFXMMU_B1CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */

+

+/****************** Bits definition for GFXMMU_B2CR register ******************/

+#define GFXMMU_B2CR_PBO_Pos                (4U)

+#define GFXMMU_B2CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B2CR_PBO_Pos)   /*!< 0x007FFFF0 */

+#define GFXMMU_B2CR_PBO                    GFXMMU_B2CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */

+#define GFXMMU_B2CR_PBBA_Pos               (23U)

+#define GFXMMU_B2CR_PBBA_Msk               (0x1FFUL << GFXMMU_B2CR_PBBA_Pos)    /*!< 0xFF800000 */

+#define GFXMMU_B2CR_PBBA                   GFXMMU_B2CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */

+

+/****************** Bits definition for GFXMMU_B3CR register ******************/

+#define GFXMMU_B3CR_PBO_Pos                (4U)

+#define GFXMMU_B3CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B3CR_PBO_Pos)   /*!< 0x007FFFF0 */

+#define GFXMMU_B3CR_PBO                    GFXMMU_B3CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */

+#define GFXMMU_B3CR_PBBA_Pos               (23U)

+#define GFXMMU_B3CR_PBBA_Msk               (0x1FFUL << GFXMMU_B3CR_PBBA_Pos)    /*!< 0xFF800000 */

+#define GFXMMU_B3CR_PBBA                   GFXMMU_B3CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */

+

+/****************** Bits definition for GFXMMU_LUTxL register *****************/

+#define GFXMMU_LUTxL_EN_Pos                (0U)

+#define GFXMMU_LUTxL_EN_Msk                (0x1UL << GFXMMU_LUTxL_EN_Pos)       /*!< 0x00000001 */

+#define GFXMMU_LUTxL_EN                    GFXMMU_LUTxL_EN_Msk                 /*!< Enable */

+#define GFXMMU_LUTxL_FVB_Pos               (8U)

+#define GFXMMU_LUTxL_FVB_Msk               (0xFFUL << GFXMMU_LUTxL_FVB_Pos)     /*!< 0x0000FF00 */

+#define GFXMMU_LUTxL_FVB                   GFXMMU_LUTxL_FVB_Msk                /*!< FVB[7:0] bits (First visible block) */

+#define GFXMMU_LUTxL_LVB_Pos               (16U)

+#define GFXMMU_LUTxL_LVB_Msk               (0xFFUL << GFXMMU_LUTxL_LVB_Pos)     /*!< 0x00FF0000 */

+#define GFXMMU_LUTxL_LVB                   GFXMMU_LUTxL_LVB_Msk                /*!< LVB[7:0] bits (Last visible block) */

+

+/****************** Bits definition for GFXMMU_LUTxH register *****************/

+#define GFXMMU_LUTxH_LO_Pos                (4U)

+#define GFXMMU_LUTxH_LO_Msk                (0x3FFFFUL << GFXMMU_LUTxH_LO_Pos)   /*!< 0x003FFFF0 */

+#define GFXMMU_LUTxH_LO                    GFXMMU_LUTxH_LO_Msk                 /*!< LO[21:4] bits (Line offset) */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            General Purpose I/O                             */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bits definition for GPIO_MODER register  *****************/

+#define GPIO_MODER_MODE0_Pos           (0U)

+#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */

+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk

+#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */

+#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */

+

+#define GPIO_MODER_MODE1_Pos           (2U)

+#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */

+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk

+#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */

+#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */

+

+#define GPIO_MODER_MODE2_Pos           (4U)

+#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */

+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk

+#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */

+#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */

+

+#define GPIO_MODER_MODE3_Pos           (6U)

+#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */

+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk

+#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */

+#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */

+

+#define GPIO_MODER_MODE4_Pos           (8U)

+#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */

+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk

+#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */

+#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */

+

+#define GPIO_MODER_MODE5_Pos           (10U)

+#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */

+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk

+#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */

+#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */

+

+#define GPIO_MODER_MODE6_Pos           (12U)

+#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */

+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk

+#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */

+#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */

+

+#define GPIO_MODER_MODE7_Pos           (14U)

+#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */

+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk

+#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */

+#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */

+

+#define GPIO_MODER_MODE8_Pos           (16U)

+#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */

+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk

+#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */

+#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */

+

+#define GPIO_MODER_MODE9_Pos           (18U)

+#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */

+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk

+#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */

+#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */

+

+#define GPIO_MODER_MODE10_Pos          (20U)

+#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */

+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk

+#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */

+#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */

+

+#define GPIO_MODER_MODE11_Pos          (22U)

+#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */

+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk

+#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */

+#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */

+

+#define GPIO_MODER_MODE12_Pos          (24U)

+#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */

+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk

+#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */

+#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */

+

+#define GPIO_MODER_MODE13_Pos          (26U)

+#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */

+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk

+#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */

+#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */

+

+#define GPIO_MODER_MODE14_Pos          (28U)

+#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */

+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk

+#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */

+#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */

+

+#define GPIO_MODER_MODE15_Pos          (30U)

+#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */

+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk

+#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */

+#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_OTYPER register  ****************/

+#define GPIO_OTYPER_OT0_Pos            (0U)

+#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */

+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk

+#define GPIO_OTYPER_OT1_Pos            (1U)

+#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */

+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk

+#define GPIO_OTYPER_OT2_Pos            (2U)

+#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */

+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk

+#define GPIO_OTYPER_OT3_Pos            (3U)

+#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */

+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk

+#define GPIO_OTYPER_OT4_Pos            (4U)

+#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */

+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk

+#define GPIO_OTYPER_OT5_Pos            (5U)

+#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */

+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk

+#define GPIO_OTYPER_OT6_Pos            (6U)

+#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */

+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk

+#define GPIO_OTYPER_OT7_Pos            (7U)

+#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */

+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk

+#define GPIO_OTYPER_OT8_Pos            (8U)

+#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */

+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk

+#define GPIO_OTYPER_OT9_Pos            (9U)

+#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */

+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk

+#define GPIO_OTYPER_OT10_Pos           (10U)

+#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */

+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk

+#define GPIO_OTYPER_OT11_Pos           (11U)

+#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */

+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk

+#define GPIO_OTYPER_OT12_Pos           (12U)

+#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */

+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk

+#define GPIO_OTYPER_OT13_Pos           (13U)

+#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */

+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk

+#define GPIO_OTYPER_OT14_Pos           (14U)

+#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */

+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk

+#define GPIO_OTYPER_OT15_Pos           (15U)

+#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */

+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk

+

+/******************  Bits definition for GPIO_OSPEEDR register  ***************/

+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)

+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */

+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk

+#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */

+#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */

+

+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)

+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */

+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk

+#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */

+#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */

+

+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)

+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */

+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk

+#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */

+#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */

+

+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)

+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */

+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk

+#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */

+#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */

+

+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)

+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */

+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk

+#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */

+#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */

+

+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)

+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */

+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk

+#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */

+#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */

+

+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)

+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */

+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk

+#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */

+#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */

+

+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)

+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */

+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk

+#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */

+#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */

+

+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)

+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */

+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk

+#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */

+#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */

+

+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)

+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */

+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk

+#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */

+#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */

+

+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)

+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */

+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk

+#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */

+#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */

+

+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)

+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */

+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk

+#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */

+#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */

+

+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)

+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */

+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk

+#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */

+#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */

+

+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)

+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */

+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk

+#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */

+#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */

+

+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)

+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */

+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk

+#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */

+#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */

+

+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)

+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */

+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk

+#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */

+#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_PUPDR register  *****************/

+#define GPIO_PUPDR_PUPD0_Pos           (0U)

+#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */

+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk

+#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */

+#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */

+

+#define GPIO_PUPDR_PUPD1_Pos           (2U)

+#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */

+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk

+#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */

+#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */

+

+#define GPIO_PUPDR_PUPD2_Pos           (4U)

+#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */

+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk

+#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */

+#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */

+

+#define GPIO_PUPDR_PUPD3_Pos           (6U)

+#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */

+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk

+#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */

+#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */

+

+#define GPIO_PUPDR_PUPD4_Pos           (8U)

+#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */

+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk

+#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */

+#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */

+

+#define GPIO_PUPDR_PUPD5_Pos           (10U)

+#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */

+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk

+#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */

+#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */

+

+#define GPIO_PUPDR_PUPD6_Pos           (12U)

+#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */

+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk

+#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */

+#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */

+

+#define GPIO_PUPDR_PUPD7_Pos           (14U)

+#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */

+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk

+#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */

+#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */

+

+#define GPIO_PUPDR_PUPD8_Pos           (16U)

+#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */

+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk

+#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */

+#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */

+

+#define GPIO_PUPDR_PUPD9_Pos           (18U)

+#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */

+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk

+#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */

+#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */

+

+#define GPIO_PUPDR_PUPD10_Pos          (20U)

+#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */

+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk

+#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */

+#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */

+

+#define GPIO_PUPDR_PUPD11_Pos          (22U)

+#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */

+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk

+#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */

+#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */

+

+#define GPIO_PUPDR_PUPD12_Pos          (24U)

+#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */

+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk

+#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */

+#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */

+

+#define GPIO_PUPDR_PUPD13_Pos          (26U)

+#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */

+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk

+#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */

+#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */

+

+#define GPIO_PUPDR_PUPD14_Pos          (28U)

+#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */

+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk

+#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */

+#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */

+

+#define GPIO_PUPDR_PUPD15_Pos          (30U)

+#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */

+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk

+#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */

+#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_IDR register  *******************/

+#define GPIO_IDR_ID0_Pos               (0U)

+#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */

+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk

+#define GPIO_IDR_ID1_Pos               (1U)

+#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */

+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk

+#define GPIO_IDR_ID2_Pos               (2U)

+#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */

+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk

+#define GPIO_IDR_ID3_Pos               (3U)

+#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */

+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk

+#define GPIO_IDR_ID4_Pos               (4U)

+#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */

+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk

+#define GPIO_IDR_ID5_Pos               (5U)

+#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */

+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk

+#define GPIO_IDR_ID6_Pos               (6U)

+#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */

+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk

+#define GPIO_IDR_ID7_Pos               (7U)

+#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */

+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk

+#define GPIO_IDR_ID8_Pos               (8U)

+#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */

+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk

+#define GPIO_IDR_ID9_Pos               (9U)

+#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */

+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk

+#define GPIO_IDR_ID10_Pos              (10U)

+#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */

+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk

+#define GPIO_IDR_ID11_Pos              (11U)

+#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */

+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk

+#define GPIO_IDR_ID12_Pos              (12U)

+#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */

+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk

+#define GPIO_IDR_ID13_Pos              (13U)

+#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */

+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk

+#define GPIO_IDR_ID14_Pos              (14U)

+#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */

+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk

+#define GPIO_IDR_ID15_Pos              (15U)

+#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */

+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk

+

+/******************  Bits definition for GPIO_ODR register  *******************/

+#define GPIO_ODR_OD0_Pos               (0U)

+#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */

+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk

+#define GPIO_ODR_OD1_Pos               (1U)

+#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */

+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk

+#define GPIO_ODR_OD2_Pos               (2U)

+#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */

+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk

+#define GPIO_ODR_OD3_Pos               (3U)

+#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */

+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk

+#define GPIO_ODR_OD4_Pos               (4U)

+#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */

+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk

+#define GPIO_ODR_OD5_Pos               (5U)

+#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */

+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk

+#define GPIO_ODR_OD6_Pos               (6U)

+#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */

+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk

+#define GPIO_ODR_OD7_Pos               (7U)

+#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */

+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk

+#define GPIO_ODR_OD8_Pos               (8U)

+#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */

+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk

+#define GPIO_ODR_OD9_Pos               (9U)

+#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */

+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk

+#define GPIO_ODR_OD10_Pos              (10U)

+#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */

+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk

+#define GPIO_ODR_OD11_Pos              (11U)

+#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */

+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk

+#define GPIO_ODR_OD12_Pos              (12U)

+#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */

+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk

+#define GPIO_ODR_OD13_Pos              (13U)

+#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */

+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk

+#define GPIO_ODR_OD14_Pos              (14U)

+#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */

+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk

+#define GPIO_ODR_OD15_Pos              (15U)

+#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */

+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk

+

+/******************  Bits definition for GPIO_BSRR register  ******************/

+#define GPIO_BSRR_BS0_Pos              (0U)

+#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */

+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk

+#define GPIO_BSRR_BS1_Pos              (1U)

+#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */

+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk

+#define GPIO_BSRR_BS2_Pos              (2U)

+#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */

+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk

+#define GPIO_BSRR_BS3_Pos              (3U)

+#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */

+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk

+#define GPIO_BSRR_BS4_Pos              (4U)

+#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */

+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk

+#define GPIO_BSRR_BS5_Pos              (5U)

+#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */

+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk

+#define GPIO_BSRR_BS6_Pos              (6U)

+#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */

+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk

+#define GPIO_BSRR_BS7_Pos              (7U)

+#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */

+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk

+#define GPIO_BSRR_BS8_Pos              (8U)

+#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */

+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk

+#define GPIO_BSRR_BS9_Pos              (9U)

+#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */

+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk

+#define GPIO_BSRR_BS10_Pos             (10U)

+#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */

+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk

+#define GPIO_BSRR_BS11_Pos             (11U)

+#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */

+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk

+#define GPIO_BSRR_BS12_Pos             (12U)

+#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */

+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk

+#define GPIO_BSRR_BS13_Pos             (13U)

+#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */

+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk

+#define GPIO_BSRR_BS14_Pos             (14U)

+#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */

+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk

+#define GPIO_BSRR_BS15_Pos             (15U)

+#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */

+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk

+#define GPIO_BSRR_BR0_Pos              (16U)

+#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */

+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk

+#define GPIO_BSRR_BR1_Pos              (17U)

+#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */

+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk

+#define GPIO_BSRR_BR2_Pos              (18U)

+#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */

+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk

+#define GPIO_BSRR_BR3_Pos              (19U)

+#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */

+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk

+#define GPIO_BSRR_BR4_Pos              (20U)

+#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */

+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk

+#define GPIO_BSRR_BR5_Pos              (21U)

+#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */

+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk

+#define GPIO_BSRR_BR6_Pos              (22U)

+#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */

+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk

+#define GPIO_BSRR_BR7_Pos              (23U)

+#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */

+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk

+#define GPIO_BSRR_BR8_Pos              (24U)

+#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */

+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk

+#define GPIO_BSRR_BR9_Pos              (25U)

+#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */

+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk

+#define GPIO_BSRR_BR10_Pos             (26U)

+#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */

+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk

+#define GPIO_BSRR_BR11_Pos             (27U)

+#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */

+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk

+#define GPIO_BSRR_BR12_Pos             (28U)

+#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */

+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk

+#define GPIO_BSRR_BR13_Pos             (29U)

+#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */

+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk

+#define GPIO_BSRR_BR14_Pos             (30U)

+#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */

+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk

+#define GPIO_BSRR_BR15_Pos             (31U)

+#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */

+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk

+

+/****************** Bit definition for GPIO_LCKR register *********************/

+#define GPIO_LCKR_LCK0_Pos             (0U)

+#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */

+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk

+#define GPIO_LCKR_LCK1_Pos             (1U)

+#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */

+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk

+#define GPIO_LCKR_LCK2_Pos             (2U)

+#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */

+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk

+#define GPIO_LCKR_LCK3_Pos             (3U)

+#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */

+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk

+#define GPIO_LCKR_LCK4_Pos             (4U)

+#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */

+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk

+#define GPIO_LCKR_LCK5_Pos             (5U)

+#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */

+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk

+#define GPIO_LCKR_LCK6_Pos             (6U)

+#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */

+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk

+#define GPIO_LCKR_LCK7_Pos             (7U)

+#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */

+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk

+#define GPIO_LCKR_LCK8_Pos             (8U)

+#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */

+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk

+#define GPIO_LCKR_LCK9_Pos             (9U)

+#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */

+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk

+#define GPIO_LCKR_LCK10_Pos            (10U)

+#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */

+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk

+#define GPIO_LCKR_LCK11_Pos            (11U)

+#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */

+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk

+#define GPIO_LCKR_LCK12_Pos            (12U)

+#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */

+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk

+#define GPIO_LCKR_LCK13_Pos            (13U)

+#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */

+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk

+#define GPIO_LCKR_LCK14_Pos            (14U)

+#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */

+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk

+#define GPIO_LCKR_LCK15_Pos            (15U)

+#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */

+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk

+#define GPIO_LCKR_LCKK_Pos             (16U)

+#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */

+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk

+

+/****************** Bit definition for GPIO_AFRL register  ********************/

+#define GPIO_AFRL_AFSEL0_Pos           (0U)

+#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */

+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk

+#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */

+#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */

+#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */

+#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */

+#define GPIO_AFRL_AFSEL1_Pos           (4U)

+#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */

+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk

+#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */

+#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */

+#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */

+#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */

+#define GPIO_AFRL_AFSEL2_Pos           (8U)

+#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */

+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk

+#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */

+#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */

+#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */

+#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */

+#define GPIO_AFRL_AFSEL3_Pos           (12U)

+#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */

+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk

+#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */

+#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */

+#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */

+#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */

+#define GPIO_AFRL_AFSEL4_Pos           (16U)

+#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */

+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk

+#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */

+#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */

+#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */

+#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */

+#define GPIO_AFRL_AFSEL5_Pos           (20U)

+#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */

+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk

+#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */

+#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */

+#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */

+#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */

+#define GPIO_AFRL_AFSEL6_Pos           (24U)

+#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */

+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk

+#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */

+#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */

+#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */

+#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */

+#define GPIO_AFRL_AFSEL7_Pos           (28U)

+#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */

+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk

+#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */

+#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */

+#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */

+#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */

+

+/* Legacy defines */

+#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0

+#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1

+#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2

+#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3

+#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4

+#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5

+#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6

+#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7

+

+/****************** Bit definition for GPIO_AFRH register  ********************/

+#define GPIO_AFRH_AFSEL8_Pos           (0U)

+#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */

+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk

+#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */

+#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */

+#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */

+#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */

+#define GPIO_AFRH_AFSEL9_Pos           (4U)

+#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */

+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk

+#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */

+#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */

+#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */

+#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */

+#define GPIO_AFRH_AFSEL10_Pos          (8U)

+#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */

+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk

+#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */

+#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */

+#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */

+#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */

+#define GPIO_AFRH_AFSEL11_Pos          (12U)

+#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */

+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk

+#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */

+#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */

+#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */

+#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */

+#define GPIO_AFRH_AFSEL12_Pos          (16U)

+#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */

+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk

+#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */

+#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */

+#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */

+#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */

+#define GPIO_AFRH_AFSEL13_Pos          (20U)

+#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */

+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk

+#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */

+#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */

+#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */

+#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */

+#define GPIO_AFRH_AFSEL14_Pos          (24U)

+#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */

+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk

+#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */

+#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */

+#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */

+#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */

+#define GPIO_AFRH_AFSEL15_Pos          (28U)

+#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */

+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk

+#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */

+#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */

+#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */

+#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */

+

+/* Legacy defines */

+#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8

+#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9

+#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10

+#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11

+#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12

+#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13

+#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14

+#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15

+

+/******************************************************************************/

+/*                                                                            */

+/*                        HSEM HW Semaphore                                   */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for HSEM_R register  ********************/

+#define HSEM_R_PROCID_Pos         (0U)

+#define HSEM_R_PROCID_Msk         (0xFFUL << HSEM_R_PROCID_Pos)                /*!< 0x000000FF */

+#define HSEM_R_PROCID             HSEM_R_PROCID_Msk                            /*!<Semaphore ProcessID */

+#define HSEM_R_COREID_Pos         (8U)

+#define HSEM_R_COREID_Msk         (0xFFUL << HSEM_R_COREID_Pos)                /*!< 0x0000FF00 */

+#define HSEM_R_COREID             HSEM_R_COREID_Msk                            /*!<Semaphore CoreID.   */

+#define HSEM_R_LOCK_Pos           (31U)

+#define HSEM_R_LOCK_Msk           (0x1UL << HSEM_R_LOCK_Pos)                   /*!< 0x80000000 */

+#define HSEM_R_LOCK               HSEM_R_LOCK_Msk                              /*!<Lock indication.    */

+

+/********************  Bit definition for HSEM_RLR register  ******************/

+#define HSEM_RLR_PROCID_Pos       (0U)

+#define HSEM_RLR_PROCID_Msk       (0xFFUL << HSEM_RLR_PROCID_Pos)              /*!< 0x000000FF */

+#define HSEM_RLR_PROCID           HSEM_RLR_PROCID_Msk                          /*!<Semaphore ProcessID */

+#define HSEM_RLR_COREID_Pos       (8U)

+#define HSEM_RLR_COREID_Msk       (0xFFUL << HSEM_RLR_COREID_Pos)              /*!< 0x0000FF00 */

+#define HSEM_RLR_COREID           HSEM_RLR_COREID_Msk                          /*!<Semaphore CoreID.   */

+#define HSEM_RLR_LOCK_Pos         (31U)

+#define HSEM_RLR_LOCK_Msk         (0x1UL << HSEM_RLR_LOCK_Pos)                 /*!< 0x80000000 */

+#define HSEM_RLR_LOCK             HSEM_RLR_LOCK_Msk                            /*!<Lock indication.    */

+

+/********************  Bit definition for HSEM_C1IER register  *****************/

+#define HSEM_C1IER_ISE0_Pos       (0U)

+#define HSEM_C1IER_ISE0_Msk       (0x1UL << HSEM_C1IER_ISE0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1IER_ISE0           HSEM_C1IER_ISE0_Msk                          /*!<semaphore 0 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE1_Pos       (1U)

+#define HSEM_C1IER_ISE1_Msk       (0x1UL << HSEM_C1IER_ISE1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1IER_ISE1           HSEM_C1IER_ISE1_Msk                          /*!<semaphore 1 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE2_Pos       (2U)

+#define HSEM_C1IER_ISE2_Msk       (0x1UL << HSEM_C1IER_ISE2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1IER_ISE2           HSEM_C1IER_ISE2_Msk                          /*!<semaphore 2 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE3_Pos       (3U)

+#define HSEM_C1IER_ISE3_Msk       (0x1UL << HSEM_C1IER_ISE3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1IER_ISE3           HSEM_C1IER_ISE3_Msk                          /*!<semaphore 3 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE4_Pos       (4U)

+#define HSEM_C1IER_ISE4_Msk       (0x1UL << HSEM_C1IER_ISE4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1IER_ISE4           HSEM_C1IER_ISE4_Msk                          /*!<semaphore 4 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE5_Pos       (5U)

+#define HSEM_C1IER_ISE5_Msk       (0x1UL << HSEM_C1IER_ISE5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1IER_ISE5           HSEM_C1IER_ISE5_Msk                          /*!<semaphore 5 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE6_Pos       (6U)

+#define HSEM_C1IER_ISE6_Msk       (0x1UL << HSEM_C1IER_ISE6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1IER_ISE6           HSEM_C1IER_ISE6_Msk                          /*!<semaphore 6 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE7_Pos       (7U)

+#define HSEM_C1IER_ISE7_Msk       (0x1UL << HSEM_C1IER_ISE7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1IER_ISE7           HSEM_C1IER_ISE7_Msk                          /*!<semaphore 7 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE8_Pos       (8U)

+#define HSEM_C1IER_ISE8_Msk       (0x1UL << HSEM_C1IER_ISE8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1IER_ISE8           HSEM_C1IER_ISE8_Msk                          /*!<semaphore 8 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE9_Pos       (9U)

+#define HSEM_C1IER_ISE9_Msk       (0x1UL << HSEM_C1IER_ISE9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1IER_ISE9           HSEM_C1IER_ISE9_Msk                          /*!<semaphore 9 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE10_Pos      (10U)

+#define HSEM_C1IER_ISE10_Msk      (0x1UL << HSEM_C1IER_ISE10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1IER_ISE10          HSEM_C1IER_ISE10_Msk                         /*!<semaphore 10 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE11_Pos      (11U)

+#define HSEM_C1IER_ISE11_Msk      (0x1UL << HSEM_C1IER_ISE11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1IER_ISE11          HSEM_C1IER_ISE11_Msk                         /*!<semaphore 11 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE12_Pos      (12U)

+#define HSEM_C1IER_ISE12_Msk      (0x1UL << HSEM_C1IER_ISE12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1IER_ISE12          HSEM_C1IER_ISE12_Msk                         /*!<semaphore 12 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE13_Pos      (13U)

+#define HSEM_C1IER_ISE13_Msk      (0x1UL << HSEM_C1IER_ISE13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1IER_ISE13          HSEM_C1IER_ISE13_Msk                         /*!<semaphore 13 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE14_Pos      (14U)

+#define HSEM_C1IER_ISE14_Msk      (0x1UL << HSEM_C1IER_ISE14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1IER_ISE14          HSEM_C1IER_ISE14_Msk                         /*!<semaphore 14 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE15_Pos      (15U)

+#define HSEM_C1IER_ISE15_Msk      (0x1UL << HSEM_C1IER_ISE15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1IER_ISE15          HSEM_C1IER_ISE15_Msk                         /*!<semaphore 15 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE16_Pos      (16U)

+#define HSEM_C1IER_ISE16_Msk      (0x1UL << HSEM_C1IER_ISE16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1IER_ISE16          HSEM_C1IER_ISE16_Msk                         /*!<semaphore 16 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE17_Pos      (17U)

+#define HSEM_C1IER_ISE17_Msk      (0x1UL << HSEM_C1IER_ISE17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1IER_ISE17          HSEM_C1IER_ISE17_Msk                         /*!<semaphore 17 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE18_Pos      (18U)

+#define HSEM_C1IER_ISE18_Msk      (0x1UL << HSEM_C1IER_ISE18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1IER_ISE18          HSEM_C1IER_ISE18_Msk                         /*!<semaphore 18 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE19_Pos      (19U)

+#define HSEM_C1IER_ISE19_Msk      (0x1UL << HSEM_C1IER_ISE19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1IER_ISE19          HSEM_C1IER_ISE19_Msk                         /*!<semaphore 19 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE20_Pos      (20U)

+#define HSEM_C1IER_ISE20_Msk      (0x1UL << HSEM_C1IER_ISE20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1IER_ISE20          HSEM_C1IER_ISE20_Msk                         /*!<semaphore 20 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE21_Pos      (21U)

+#define HSEM_C1IER_ISE21_Msk      (0x1UL << HSEM_C1IER_ISE21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1IER_ISE21          HSEM_C1IER_ISE21_Msk                         /*!<semaphore 21 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE22_Pos      (22U)

+#define HSEM_C1IER_ISE22_Msk      (0x1UL << HSEM_C1IER_ISE22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1IER_ISE22          HSEM_C1IER_ISE22_Msk                         /*!<semaphore 22 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE23_Pos      (23U)

+#define HSEM_C1IER_ISE23_Msk      (0x1UL << HSEM_C1IER_ISE23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1IER_ISE23          HSEM_C1IER_ISE23_Msk                         /*!<semaphore 23 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE24_Pos      (24U)

+#define HSEM_C1IER_ISE24_Msk      (0x1UL << HSEM_C1IER_ISE24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1IER_ISE24          HSEM_C1IER_ISE24_Msk                         /*!<semaphore 24 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE25_Pos      (25U)

+#define HSEM_C1IER_ISE25_Msk      (0x1UL << HSEM_C1IER_ISE25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1IER_ISE25          HSEM_C1IER_ISE25_Msk                         /*!<semaphore 25 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE26_Pos      (26U)

+#define HSEM_C1IER_ISE26_Msk      (0x1UL << HSEM_C1IER_ISE26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1IER_ISE26          HSEM_C1IER_ISE26_Msk                         /*!<semaphore 26 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE27_Pos      (27U)

+#define HSEM_C1IER_ISE27_Msk      (0x1UL << HSEM_C1IER_ISE27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1IER_ISE27          HSEM_C1IER_ISE27_Msk                         /*!<semaphore 27 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE28_Pos      (28U)

+#define HSEM_C1IER_ISE28_Msk      (0x1UL << HSEM_C1IER_ISE28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1IER_ISE28          HSEM_C1IER_ISE28_Msk                         /*!<semaphore 28 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE29_Pos      (29U)

+#define HSEM_C1IER_ISE29_Msk      (0x1UL << HSEM_C1IER_ISE29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1IER_ISE29          HSEM_C1IER_ISE29_Msk                         /*!<semaphore 29 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE30_Pos      (30U)

+#define HSEM_C1IER_ISE30_Msk      (0x1UL << HSEM_C1IER_ISE30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1IER_ISE30          HSEM_C1IER_ISE30_Msk                         /*!<semaphore 30 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE31_Pos      (31U)

+#define HSEM_C1IER_ISE31_Msk      (0x1UL << HSEM_C1IER_ISE31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1IER_ISE31          HSEM_C1IER_ISE31_Msk                         /*!<semaphore 31 interrupt 0 enable bit. */

+

+/********************  Bit definition for HSEM_C1ICR register  *****************/

+#define HSEM_C1ICR_ISC0_Pos       (0U)

+#define HSEM_C1ICR_ISC0_Msk       (0x1UL << HSEM_C1ICR_ISC0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1ICR_ISC0           HSEM_C1ICR_ISC0_Msk                          /*!<semaphore 0 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC1_Pos       (1U)

+#define HSEM_C1ICR_ISC1_Msk       (0x1UL << HSEM_C1ICR_ISC1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1ICR_ISC1           HSEM_C1ICR_ISC1_Msk                          /*!<semaphore 1 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC2_Pos       (2U)

+#define HSEM_C1ICR_ISC2_Msk       (0x1UL << HSEM_C1ICR_ISC2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1ICR_ISC2           HSEM_C1ICR_ISC2_Msk                          /*!<semaphore 2 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC3_Pos       (3U)

+#define HSEM_C1ICR_ISC3_Msk       (0x1UL << HSEM_C1ICR_ISC3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1ICR_ISC3           HSEM_C1ICR_ISC3_Msk                          /*!<semaphore 3 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC4_Pos       (4U)

+#define HSEM_C1ICR_ISC4_Msk       (0x1UL << HSEM_C1ICR_ISC4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1ICR_ISC4           HSEM_C1ICR_ISC4_Msk                          /*!<semaphore 4 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC5_Pos       (5U)

+#define HSEM_C1ICR_ISC5_Msk       (0x1UL << HSEM_C1ICR_ISC5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1ICR_ISC5           HSEM_C1ICR_ISC5_Msk                          /*!<semaphore 5 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC6_Pos       (6U)

+#define HSEM_C1ICR_ISC6_Msk       (0x1UL << HSEM_C1ICR_ISC6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1ICR_ISC6           HSEM_C1ICR_ISC6_Msk                          /*!<semaphore 6 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC7_Pos       (7U)

+#define HSEM_C1ICR_ISC7_Msk       (0x1UL << HSEM_C1ICR_ISC7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1ICR_ISC7           HSEM_C1ICR_ISC7_Msk                          /*!<semaphore 7 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC8_Pos       (8U)

+#define HSEM_C1ICR_ISC8_Msk       (0x1UL << HSEM_C1ICR_ISC8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1ICR_ISC8           HSEM_C1ICR_ISC8_Msk                          /*!<semaphore 8 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC9_Pos       (9U)

+#define HSEM_C1ICR_ISC9_Msk       (0x1UL << HSEM_C1ICR_ISC9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1ICR_ISC9           HSEM_C1ICR_ISC9_Msk                          /*!<semaphore 9 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC10_Pos      (10U)

+#define HSEM_C1ICR_ISC10_Msk      (0x1UL << HSEM_C1ICR_ISC10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1ICR_ISC10          HSEM_C1ICR_ISC10_Msk                         /*!<semaphore 10 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC11_Pos      (11U)

+#define HSEM_C1ICR_ISC11_Msk      (0x1UL << HSEM_C1ICR_ISC11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1ICR_ISC11          HSEM_C1ICR_ISC11_Msk                         /*!<semaphore 11 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC12_Pos      (12U)

+#define HSEM_C1ICR_ISC12_Msk      (0x1UL << HSEM_C1ICR_ISC12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1ICR_ISC12          HSEM_C1ICR_ISC12_Msk                         /*!<semaphore 12 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC13_Pos      (13U)

+#define HSEM_C1ICR_ISC13_Msk      (0x1UL << HSEM_C1ICR_ISC13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1ICR_ISC13          HSEM_C1ICR_ISC13_Msk                         /*!<semaphore 13 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC14_Pos      (14U)

+#define HSEM_C1ICR_ISC14_Msk      (0x1UL << HSEM_C1ICR_ISC14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1ICR_ISC14          HSEM_C1ICR_ISC14_Msk                         /*!<semaphore 14 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC15_Pos      (15U)

+#define HSEM_C1ICR_ISC15_Msk      (0x1UL << HSEM_C1ICR_ISC15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1ICR_ISC15          HSEM_C1ICR_ISC15_Msk                         /*!<semaphore 15 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC16_Pos      (16U)

+#define HSEM_C1ICR_ISC16_Msk      (0x1UL << HSEM_C1ICR_ISC16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1ICR_ISC16          HSEM_C1ICR_ISC16_Msk                         /*!<semaphore 16 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC17_Pos      (17U)

+#define HSEM_C1ICR_ISC17_Msk      (0x1UL << HSEM_C1ICR_ISC17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1ICR_ISC17          HSEM_C1ICR_ISC17_Msk                         /*!<semaphore 17 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC18_Pos      (18U)

+#define HSEM_C1ICR_ISC18_Msk      (0x1UL << HSEM_C1ICR_ISC18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1ICR_ISC18          HSEM_C1ICR_ISC18_Msk                         /*!<semaphore 18 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC19_Pos      (19U)

+#define HSEM_C1ICR_ISC19_Msk      (0x1UL << HSEM_C1ICR_ISC19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1ICR_ISC19          HSEM_C1ICR_ISC19_Msk                         /*!<semaphore 19 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC20_Pos      (20U)

+#define HSEM_C1ICR_ISC20_Msk      (0x1UL << HSEM_C1ICR_ISC20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1ICR_ISC20          HSEM_C1ICR_ISC20_Msk                         /*!<semaphore 20 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC21_Pos      (21U)

+#define HSEM_C1ICR_ISC21_Msk      (0x1UL << HSEM_C1ICR_ISC21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1ICR_ISC21          HSEM_C1ICR_ISC21_Msk                         /*!<semaphore 21 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC22_Pos      (22U)

+#define HSEM_C1ICR_ISC22_Msk      (0x1UL << HSEM_C1ICR_ISC22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1ICR_ISC22          HSEM_C1ICR_ISC22_Msk                         /*!<semaphore 22 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC23_Pos      (23U)

+#define HSEM_C1ICR_ISC23_Msk      (0x1UL << HSEM_C1ICR_ISC23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1ICR_ISC23          HSEM_C1ICR_ISC23_Msk                         /*!<semaphore 23 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC24_Pos      (24U)

+#define HSEM_C1ICR_ISC24_Msk      (0x1UL << HSEM_C1ICR_ISC24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1ICR_ISC24          HSEM_C1ICR_ISC24_Msk                         /*!<semaphore 24 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC25_Pos      (25U)

+#define HSEM_C1ICR_ISC25_Msk      (0x1UL << HSEM_C1ICR_ISC25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1ICR_ISC25          HSEM_C1ICR_ISC25_Msk                         /*!<semaphore 25 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC26_Pos      (26U)

+#define HSEM_C1ICR_ISC26_Msk      (0x1UL << HSEM_C1ICR_ISC26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1ICR_ISC26          HSEM_C1ICR_ISC26_Msk                         /*!<semaphore 26 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC27_Pos      (27U)

+#define HSEM_C1ICR_ISC27_Msk      (0x1UL << HSEM_C1ICR_ISC27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1ICR_ISC27          HSEM_C1ICR_ISC27_Msk                         /*!<semaphore 27 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC28_Pos      (28U)

+#define HSEM_C1ICR_ISC28_Msk      (0x1UL << HSEM_C1ICR_ISC28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1ICR_ISC28          HSEM_C1ICR_ISC28_Msk                         /*!<semaphore 28 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC29_Pos      (29U)

+#define HSEM_C1ICR_ISC29_Msk      (0x1UL << HSEM_C1ICR_ISC29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1ICR_ISC29          HSEM_C1ICR_ISC29_Msk                         /*!<semaphore 29 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC30_Pos      (30U)

+#define HSEM_C1ICR_ISC30_Msk      (0x1UL << HSEM_C1ICR_ISC30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1ICR_ISC30          HSEM_C1ICR_ISC30_Msk                         /*!<semaphore 30 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC31_Pos      (31U)

+#define HSEM_C1ICR_ISC31_Msk      (0x1UL << HSEM_C1ICR_ISC31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1ICR_ISC31          HSEM_C1ICR_ISC31_Msk                         /*!<semaphore 31 interrupt 0 clear bit. */

+

+/********************  Bit definition for HSEM_C1ISR register  *****************/

+#define HSEM_C1ISR_ISF0_Pos       (0U)

+#define HSEM_C1ISR_ISF0_Msk       (0x1UL << HSEM_C1ISR_ISF0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1ISR_ISF0           HSEM_C1ISR_ISF0_Msk                          /*!<semaphore 0 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF1_Pos       (1U)

+#define HSEM_C1ISR_ISF1_Msk       (0x1UL << HSEM_C1ISR_ISF1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1ISR_ISF1           HSEM_C1ISR_ISF1_Msk                          /*!<semaphore 1 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF2_Pos       (2U)

+#define HSEM_C1ISR_ISF2_Msk       (0x1UL << HSEM_C1ISR_ISF2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1ISR_ISF2           HSEM_C1ISR_ISF2_Msk                          /*!<semaphore 2 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF3_Pos       (3U)

+#define HSEM_C1ISR_ISF3_Msk       (0x1UL << HSEM_C1ISR_ISF3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1ISR_ISF3           HSEM_C1ISR_ISF3_Msk                          /*!<semaphore 3 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF4_Pos       (4U)

+#define HSEM_C1ISR_ISF4_Msk       (0x1UL << HSEM_C1ISR_ISF4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1ISR_ISF4           HSEM_C1ISR_ISF4_Msk                          /*!<semaphore 4 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF5_Pos       (5U)

+#define HSEM_C1ISR_ISF5_Msk       (0x1UL << HSEM_C1ISR_ISF5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1ISR_ISF5           HSEM_C1ISR_ISF5_Msk                          /*!<semaphore 5 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF6_Pos       (6U)

+#define HSEM_C1ISR_ISF6_Msk       (0x1UL << HSEM_C1ISR_ISF6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1ISR_ISF6           HSEM_C1ISR_ISF6_Msk                          /*!<semaphore 6 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF7_Pos       (7U)

+#define HSEM_C1ISR_ISF7_Msk       (0x1UL << HSEM_C1ISR_ISF7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1ISR_ISF7           HSEM_C1ISR_ISF7_Msk                          /*!<semaphore 7 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF8_Pos       (8U)

+#define HSEM_C1ISR_ISF8_Msk       (0x1UL << HSEM_C1ISR_ISF8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1ISR_ISF8           HSEM_C1ISR_ISF8_Msk                          /*!<semaphore 8 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF9_Pos       (9U)

+#define HSEM_C1ISR_ISF9_Msk       (0x1UL << HSEM_C1ISR_ISF9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1ISR_ISF9           HSEM_C1ISR_ISF9_Msk                          /*!<semaphore 9 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF10_Pos      (10U)

+#define HSEM_C1ISR_ISF10_Msk      (0x1UL << HSEM_C1ISR_ISF10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1ISR_ISF10          HSEM_C1ISR_ISF10_Msk                         /*!<semaphore 10 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF11_Pos      (11U)

+#define HSEM_C1ISR_ISF11_Msk      (0x1UL << HSEM_C1ISR_ISF11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1ISR_ISF11          HSEM_C1ISR_ISF11_Msk                         /*!<semaphore 11 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF12_Pos      (12U)

+#define HSEM_C1ISR_ISF12_Msk      (0x1UL << HSEM_C1ISR_ISF12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1ISR_ISF12          HSEM_C1ISR_ISF12_Msk                         /*!<semaphore 12 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF13_Pos      (13U)

+#define HSEM_C1ISR_ISF13_Msk      (0x1UL << HSEM_C1ISR_ISF13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1ISR_ISF13          HSEM_C1ISR_ISF13_Msk                         /*!<semaphore 13 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF14_Pos      (14U)

+#define HSEM_C1ISR_ISF14_Msk      (0x1UL << HSEM_C1ISR_ISF14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1ISR_ISF14          HSEM_C1ISR_ISF14_Msk                         /*!<semaphore 14 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF15_Pos      (15U)

+#define HSEM_C1ISR_ISF15_Msk      (0x1UL << HSEM_C1ISR_ISF15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1ISR_ISF15          HSEM_C1ISR_ISF15_Msk                         /*!<semaphore 15 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF16_Pos      (16U)

+#define HSEM_C1ISR_ISF16_Msk      (0x1UL << HSEM_C1ISR_ISF16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1ISR_ISF16          HSEM_C1ISR_ISF16_Msk                         /*!<semaphore 16 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF17_Pos      (17U)

+#define HSEM_C1ISR_ISF17_Msk      (0x1UL << HSEM_C1ISR_ISF17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1ISR_ISF17          HSEM_C1ISR_ISF17_Msk                         /*!<semaphore 17 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF18_Pos      (18U)

+#define HSEM_C1ISR_ISF18_Msk      (0x1UL << HSEM_C1ISR_ISF18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1ISR_ISF18          HSEM_C1ISR_ISF18_Msk                         /*!<semaphore 18 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF19_Pos      (19U)

+#define HSEM_C1ISR_ISF19_Msk      (0x1UL << HSEM_C1ISR_ISF19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1ISR_ISF19          HSEM_C1ISR_ISF19_Msk                         /*!<semaphore 19 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF20_Pos      (20U)

+#define HSEM_C1ISR_ISF20_Msk      (0x1UL << HSEM_C1ISR_ISF20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1ISR_ISF20          HSEM_C1ISR_ISF20_Msk                         /*!<semaphore 20 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF21_Pos      (21U)

+#define HSEM_C1ISR_ISF21_Msk      (0x1UL << HSEM_C1ISR_ISF21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1ISR_ISF21          HSEM_C1ISR_ISF21_Msk                         /*!<semaphore 21 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF22_Pos      (22U)

+#define HSEM_C1ISR_ISF22_Msk      (0x1UL << HSEM_C1ISR_ISF22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1ISR_ISF22          HSEM_C1ISR_ISF22_Msk                         /*!<semaphore 22 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF23_Pos      (23U)

+#define HSEM_C1ISR_ISF23_Msk      (0x1UL << HSEM_C1ISR_ISF23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1ISR_ISF23          HSEM_C1ISR_ISF23_Msk                         /*!<semaphore 23 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF24_Pos      (24U)

+#define HSEM_C1ISR_ISF24_Msk      (0x1UL << HSEM_C1ISR_ISF24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1ISR_ISF24          HSEM_C1ISR_ISF24_Msk                         /*!<semaphore 24 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF25_Pos      (25U)

+#define HSEM_C1ISR_ISF25_Msk      (0x1UL << HSEM_C1ISR_ISF25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1ISR_ISF25          HSEM_C1ISR_ISF25_Msk                         /*!<semaphore 25 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF26_Pos      (26U)

+#define HSEM_C1ISR_ISF26_Msk      (0x1UL << HSEM_C1ISR_ISF26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1ISR_ISF26          HSEM_C1ISR_ISF26_Msk                         /*!<semaphore 26 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF27_Pos      (27U)

+#define HSEM_C1ISR_ISF27_Msk      (0x1UL << HSEM_C1ISR_ISF27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1ISR_ISF27          HSEM_C1ISR_ISF27_Msk                         /*!<semaphore 27 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF28_Pos      (28U)

+#define HSEM_C1ISR_ISF28_Msk      (0x1UL << HSEM_C1ISR_ISF28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1ISR_ISF28          HSEM_C1ISR_ISF28_Msk                         /*!<semaphore 28 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF29_Pos      (29U)

+#define HSEM_C1ISR_ISF29_Msk      (0x1UL << HSEM_C1ISR_ISF29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1ISR_ISF29          HSEM_C1ISR_ISF29_Msk                         /*!<semaphore 29 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF30_Pos      (30U)

+#define HSEM_C1ISR_ISF30_Msk      (0x1UL << HSEM_C1ISR_ISF30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1ISR_ISF30          HSEM_C1ISR_ISF30_Msk                         /*!<semaphore 30 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF31_Pos      (31U)

+#define HSEM_C1ISR_ISF31_Msk      (0x1UL << HSEM_C1ISR_ISF31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1ISR_ISF31          HSEM_C1ISR_ISF31_Msk                         /*!<semaphore 31 interrupt 0 status bit. */

+

+/********************  Bit definition for HSEM_C1MISR register  *****************/

+#define HSEM_C1MISR_MISF0_Pos     (0U)

+#define HSEM_C1MISR_MISF0_Msk     (0x1UL << HSEM_C1MISR_MISF0_Pos)             /*!< 0x00000001 */

+#define HSEM_C1MISR_MISF0         HSEM_C1MISR_MISF0_Msk                        /*!<semaphore 0 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF1_Pos     (1U)

+#define HSEM_C1MISR_MISF1_Msk     (0x1UL << HSEM_C1MISR_MISF1_Pos)             /*!< 0x00000002 */

+#define HSEM_C1MISR_MISF1         HSEM_C1MISR_MISF1_Msk                        /*!<semaphore 1 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF2_Pos     (2U)

+#define HSEM_C1MISR_MISF2_Msk     (0x1UL << HSEM_C1MISR_MISF2_Pos)             /*!< 0x00000004 */

+#define HSEM_C1MISR_MISF2         HSEM_C1MISR_MISF2_Msk                        /*!<semaphore 2 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF3_Pos     (3U)

+#define HSEM_C1MISR_MISF3_Msk     (0x1UL << HSEM_C1MISR_MISF3_Pos)             /*!< 0x00000008 */

+#define HSEM_C1MISR_MISF3         HSEM_C1MISR_MISF3_Msk                        /*!<semaphore 3 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF4_Pos     (4U)

+#define HSEM_C1MISR_MISF4_Msk     (0x1UL << HSEM_C1MISR_MISF4_Pos)             /*!< 0x00000010 */

+#define HSEM_C1MISR_MISF4         HSEM_C1MISR_MISF4_Msk                        /*!<semaphore 4 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF5_Pos     (5U)

+#define HSEM_C1MISR_MISF5_Msk     (0x1UL << HSEM_C1MISR_MISF5_Pos)             /*!< 0x00000020 */

+#define HSEM_C1MISR_MISF5         HSEM_C1MISR_MISF5_Msk                        /*!<semaphore 5 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF6_Pos     (6U)

+#define HSEM_C1MISR_MISF6_Msk     (0x1UL << HSEM_C1MISR_MISF6_Pos)             /*!< 0x00000040 */

+#define HSEM_C1MISR_MISF6         HSEM_C1MISR_MISF6_Msk                        /*!<semaphore 6 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF7_Pos     (7U)

+#define HSEM_C1MISR_MISF7_Msk     (0x1UL << HSEM_C1MISR_MISF7_Pos)             /*!< 0x00000080 */

+#define HSEM_C1MISR_MISF7         HSEM_C1MISR_MISF7_Msk                        /*!<semaphore 7 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF8_Pos     (8U)

+#define HSEM_C1MISR_MISF8_Msk     (0x1UL << HSEM_C1MISR_MISF8_Pos)             /*!< 0x00000100 */

+#define HSEM_C1MISR_MISF8         HSEM_C1MISR_MISF8_Msk                        /*!<semaphore 8 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF9_Pos     (9U)

+#define HSEM_C1MISR_MISF9_Msk     (0x1UL << HSEM_C1MISR_MISF9_Pos)             /*!< 0x00000200 */

+#define HSEM_C1MISR_MISF9         HSEM_C1MISR_MISF9_Msk                        /*!<semaphore 9 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF10_Pos    (10U)

+#define HSEM_C1MISR_MISF10_Msk    (0x1UL << HSEM_C1MISR_MISF10_Pos)            /*!< 0x00000400 */

+#define HSEM_C1MISR_MISF10        HSEM_C1MISR_MISF10_Msk                       /*!<semaphore 10 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF11_Pos    (11U)

+#define HSEM_C1MISR_MISF11_Msk    (0x1UL << HSEM_C1MISR_MISF11_Pos)            /*!< 0x00000800 */

+#define HSEM_C1MISR_MISF11        HSEM_C1MISR_MISF11_Msk                       /*!<semaphore 11 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF12_Pos    (12U)

+#define HSEM_C1MISR_MISF12_Msk    (0x1UL << HSEM_C1MISR_MISF12_Pos)            /*!< 0x00001000 */

+#define HSEM_C1MISR_MISF12        HSEM_C1MISR_MISF12_Msk                       /*!<semaphore 12 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF13_Pos    (13U)

+#define HSEM_C1MISR_MISF13_Msk    (0x1UL << HSEM_C1MISR_MISF13_Pos)            /*!< 0x00002000 */

+#define HSEM_C1MISR_MISF13        HSEM_C1MISR_MISF13_Msk                       /*!<semaphore 13 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF14_Pos    (14U)

+#define HSEM_C1MISR_MISF14_Msk    (0x1UL << HSEM_C1MISR_MISF14_Pos)            /*!< 0x00004000 */

+#define HSEM_C1MISR_MISF14        HSEM_C1MISR_MISF14_Msk                       /*!<semaphore 14 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF15_Pos    (15U)

+#define HSEM_C1MISR_MISF15_Msk    (0x1UL << HSEM_C1MISR_MISF15_Pos)            /*!< 0x00008000 */

+#define HSEM_C1MISR_MISF15        HSEM_C1MISR_MISF15_Msk                       /*!<semaphore 15 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF16_Pos    (16U)

+#define HSEM_C1MISR_MISF16_Msk    (0x1UL << HSEM_C1MISR_MISF16_Pos)            /*!< 0x00010000 */

+#define HSEM_C1MISR_MISF16        HSEM_C1MISR_MISF16_Msk                       /*!<semaphore 16 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF17_Pos    (17U)

+#define HSEM_C1MISR_MISF17_Msk    (0x1UL << HSEM_C1MISR_MISF17_Pos)            /*!< 0x00020000 */

+#define HSEM_C1MISR_MISF17        HSEM_C1MISR_MISF17_Msk                       /*!<semaphore 17 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF18_Pos    (18U)

+#define HSEM_C1MISR_MISF18_Msk    (0x1UL << HSEM_C1MISR_MISF18_Pos)            /*!< 0x00040000 */

+#define HSEM_C1MISR_MISF18        HSEM_C1MISR_MISF18_Msk                       /*!<semaphore 18 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF19_Pos    (19U)

+#define HSEM_C1MISR_MISF19_Msk    (0x1UL << HSEM_C1MISR_MISF19_Pos)            /*!< 0x00080000 */

+#define HSEM_C1MISR_MISF19        HSEM_C1MISR_MISF19_Msk                       /*!<semaphore 19 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF20_Pos    (20U)

+#define HSEM_C1MISR_MISF20_Msk    (0x1UL << HSEM_C1MISR_MISF20_Pos)            /*!< 0x00100000 */

+#define HSEM_C1MISR_MISF20        HSEM_C1MISR_MISF20_Msk                       /*!<semaphore 20 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF21_Pos    (21U)

+#define HSEM_C1MISR_MISF21_Msk    (0x1UL << HSEM_C1MISR_MISF21_Pos)            /*!< 0x00200000 */

+#define HSEM_C1MISR_MISF21        HSEM_C1MISR_MISF21_Msk                       /*!<semaphore 21 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF22_Pos    (22U)

+#define HSEM_C1MISR_MISF22_Msk    (0x1UL << HSEM_C1MISR_MISF22_Pos)            /*!< 0x00400000 */

+#define HSEM_C1MISR_MISF22        HSEM_C1MISR_MISF22_Msk                       /*!<semaphore 22 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF23_Pos    (23U)

+#define HSEM_C1MISR_MISF23_Msk    (0x1UL << HSEM_C1MISR_MISF23_Pos)            /*!< 0x00800000 */

+#define HSEM_C1MISR_MISF23        HSEM_C1MISR_MISF23_Msk                       /*!<semaphore 23 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF24_Pos    (24U)

+#define HSEM_C1MISR_MISF24_Msk    (0x1UL << HSEM_C1MISR_MISF24_Pos)            /*!< 0x01000000 */

+#define HSEM_C1MISR_MISF24        HSEM_C1MISR_MISF24_Msk                       /*!<semaphore 24 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF25_Pos    (25U)

+#define HSEM_C1MISR_MISF25_Msk    (0x1UL << HSEM_C1MISR_MISF25_Pos)            /*!< 0x02000000 */

+#define HSEM_C1MISR_MISF25        HSEM_C1MISR_MISF25_Msk                       /*!<semaphore 25 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF26_Pos    (26U)

+#define HSEM_C1MISR_MISF26_Msk    (0x1UL << HSEM_C1MISR_MISF26_Pos)            /*!< 0x04000000 */

+#define HSEM_C1MISR_MISF26        HSEM_C1MISR_MISF26_Msk                       /*!<semaphore 26 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF27_Pos    (27U)

+#define HSEM_C1MISR_MISF27_Msk    (0x1UL << HSEM_C1MISR_MISF27_Pos)            /*!< 0x08000000 */

+#define HSEM_C1MISR_MISF27        HSEM_C1MISR_MISF27_Msk                       /*!<semaphore 27 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF28_Pos    (28U)

+#define HSEM_C1MISR_MISF28_Msk    (0x1UL << HSEM_C1MISR_MISF28_Pos)            /*!< 0x10000000 */

+#define HSEM_C1MISR_MISF28        HSEM_C1MISR_MISF28_Msk                       /*!<semaphore 28 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF29_Pos    (29U)

+#define HSEM_C1MISR_MISF29_Msk    (0x1UL << HSEM_C1MISR_MISF29_Pos)            /*!< 0x20000000 */

+#define HSEM_C1MISR_MISF29        HSEM_C1MISR_MISF29_Msk                       /*!<semaphore 29 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF30_Pos    (30U)

+#define HSEM_C1MISR_MISF30_Msk    (0x1UL << HSEM_C1MISR_MISF30_Pos)            /*!< 0x40000000 */

+#define HSEM_C1MISR_MISF30        HSEM_C1MISR_MISF30_Msk                       /*!<semaphore 30 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF31_Pos    (31U)

+#define HSEM_C1MISR_MISF31_Msk    (0x1UL << HSEM_C1MISR_MISF31_Pos)            /*!< 0x80000000 */

+#define HSEM_C1MISR_MISF31        HSEM_C1MISR_MISF31_Msk                       /*!<semaphore 31 interrupt 0 masked status bit. */

+

+/********************  Bit definition for HSEM_CR register  *****************/

+#define HSEM_CR_COREID_Pos        (8U)

+#define HSEM_CR_COREID_Msk        (0xFFUL << HSEM_CR_COREID_Pos)               /*!< 0x0000FF00 */

+#define HSEM_CR_COREID            HSEM_CR_COREID_Msk                           /*!<CoreID of semaphores to be cleared. */

+#define HSEM_CR_KEY_Pos           (16U)

+#define HSEM_CR_KEY_Msk           (0xFFFFUL << HSEM_CR_KEY_Pos)                /*!< 0xFFFF0000 */

+#define HSEM_CR_KEY               HSEM_CR_KEY_Msk                              /*!<semaphores clear key. */

+

+/********************  Bit definition for HSEM_KEYR register  *****************/

+#define HSEM_KEYR_KEY_Pos         (16U)

+#define HSEM_KEYR_KEY_Msk         (0xFFFFUL << HSEM_KEYR_KEY_Pos)              /*!< 0xFFFF0000 */

+#define HSEM_KEYR_KEY             HSEM_KEYR_KEY_Msk                            /*!<semaphores clear key. */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    HASH                                    */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bits definition for HASH_CR register  ********************/

+#define HASH_CR_INIT_Pos          (2U)

+#define HASH_CR_INIT_Msk          (0x1UL << HASH_CR_INIT_Pos)                  /*!< 0x00000004 */

+#define HASH_CR_INIT              HASH_CR_INIT_Msk

+#define HASH_CR_DMAE_Pos          (3U)

+#define HASH_CR_DMAE_Msk          (0x1UL << HASH_CR_DMAE_Pos)                  /*!< 0x00000008 */

+#define HASH_CR_DMAE              HASH_CR_DMAE_Msk

+#define HASH_CR_DATATYPE_Pos      (4U)

+#define HASH_CR_DATATYPE_Msk      (0x3UL << HASH_CR_DATATYPE_Pos)              /*!< 0x00000030 */

+#define HASH_CR_DATATYPE          HASH_CR_DATATYPE_Msk

+#define HASH_CR_DATATYPE_0        (0x1UL << HASH_CR_DATATYPE_Pos)               /*!< 0x00000010 */

+#define HASH_CR_DATATYPE_1        (0x2UL << HASH_CR_DATATYPE_Pos)               /*!< 0x00000020 */

+#define HASH_CR_MODE_Pos          (6U)

+#define HASH_CR_MODE_Msk          (0x1UL << HASH_CR_MODE_Pos)                  /*!< 0x00000040 */

+#define HASH_CR_MODE              HASH_CR_MODE_Msk

+#define HASH_CR_ALGO_Pos          (7U)

+#define HASH_CR_ALGO_Msk          (0x801UL << HASH_CR_ALGO_Pos)                /*!< 0x00040080 */

+#define HASH_CR_ALGO              HASH_CR_ALGO_Msk

+#define HASH_CR_ALGO_0            (0x001UL << HASH_CR_ALGO_Pos)                 /*!< 0x00000080 */

+#define HASH_CR_ALGO_1            (0x800UL << HASH_CR_ALGO_Pos)                 /*!< 0x00040000 */

+#define HASH_CR_NBW_Pos           (8U)

+#define HASH_CR_NBW_Msk           (0xFUL << HASH_CR_NBW_Pos)                   /*!< 0x00000F00 */

+#define HASH_CR_NBW               HASH_CR_NBW_Msk

+#define HASH_CR_NBW_0             (0x1UL << HASH_CR_NBW_Pos)                    /*!< 0x00000100 */

+#define HASH_CR_NBW_1             (0x2UL << HASH_CR_NBW_Pos)                    /*!< 0x00000200 */

+#define HASH_CR_NBW_2             (0x4UL << HASH_CR_NBW_Pos)                    /*!< 0x00000400 */

+#define HASH_CR_NBW_3             (0x8UL << HASH_CR_NBW_Pos)                    /*!< 0x00000800 */

+#define HASH_CR_DINNE_Pos         (12U)

+#define HASH_CR_DINNE_Msk         (0x1UL << HASH_CR_DINNE_Pos)                 /*!< 0x00001000 */

+#define HASH_CR_DINNE             HASH_CR_DINNE_Msk

+#define HASH_CR_MDMAT_Pos         (13U)

+#define HASH_CR_MDMAT_Msk         (0x1UL << HASH_CR_MDMAT_Pos)                 /*!< 0x00002000 */

+#define HASH_CR_MDMAT             HASH_CR_MDMAT_Msk

+#define HASH_CR_LKEY_Pos          (16U)

+#define HASH_CR_LKEY_Msk          (0x1UL << HASH_CR_LKEY_Pos)                  /*!< 0x00010000 */

+#define HASH_CR_LKEY              HASH_CR_LKEY_Msk

+

+/******************  Bits definition for HASH_STR register  *******************/

+#define HASH_STR_NBLW_Pos         (0U)

+#define HASH_STR_NBLW_Msk         (0x1FUL << HASH_STR_NBLW_Pos)                /*!< 0x0000001F */

+#define HASH_STR_NBLW             HASH_STR_NBLW_Msk

+#define HASH_STR_NBLW_0           (0x01UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000001 */

+#define HASH_STR_NBLW_1           (0x02UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000002 */

+#define HASH_STR_NBLW_2           (0x04UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000004 */

+#define HASH_STR_NBLW_3           (0x08UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000008 */

+#define HASH_STR_NBLW_4           (0x10UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000010 */

+#define HASH_STR_DCAL_Pos         (8U)

+#define HASH_STR_DCAL_Msk         (0x1UL << HASH_STR_DCAL_Pos)                 /*!< 0x00000100 */

+#define HASH_STR_DCAL             HASH_STR_DCAL_Msk

+

+/******************  Bits definition for HASH_IMR register  *******************/

+#define HASH_IMR_DINIE_Pos        (0U)

+#define HASH_IMR_DINIE_Msk        (0x1UL << HASH_IMR_DINIE_Pos)                /*!< 0x00000001 */

+#define HASH_IMR_DINIE            HASH_IMR_DINIE_Msk

+#define HASH_IMR_DCIE_Pos         (1U)

+#define HASH_IMR_DCIE_Msk         (0x1UL << HASH_IMR_DCIE_Pos)                 /*!< 0x00000002 */

+#define HASH_IMR_DCIE             HASH_IMR_DCIE_Msk

+

+/******************  Bits definition for HASH_SR register  ********************/

+#define HASH_SR_DINIS_Pos         (0U)

+#define HASH_SR_DINIS_Msk         (0x1UL << HASH_SR_DINIS_Pos)                 /*!< 0x00000001 */

+#define HASH_SR_DINIS             HASH_SR_DINIS_Msk

+#define HASH_SR_DCIS_Pos          (1U)

+#define HASH_SR_DCIS_Msk          (0x1UL << HASH_SR_DCIS_Pos)                  /*!< 0x00000002 */

+#define HASH_SR_DCIS              HASH_SR_DCIS_Msk

+#define HASH_SR_DMAS_Pos          (2U)

+#define HASH_SR_DMAS_Msk          (0x1UL << HASH_SR_DMAS_Pos)                  /*!< 0x00000004 */

+#define HASH_SR_DMAS              HASH_SR_DMAS_Msk

+#define HASH_SR_BUSY_Pos          (3U)

+#define HASH_SR_BUSY_Msk          (0x1UL << HASH_SR_BUSY_Pos)                  /*!< 0x00000008 */

+#define HASH_SR_BUSY              HASH_SR_BUSY_Msk

+/******************************************************************************/

+/*                                                                            */

+/*                      Inter-integrated Circuit Interface (I2C)              */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for I2C_CR1 register  *******************/

+#define I2C_CR1_PE_Pos               (0U)

+#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */

+#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */

+#define I2C_CR1_TXIE_Pos             (1U)

+#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */

+#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */

+#define I2C_CR1_RXIE_Pos             (2U)

+#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */

+#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */

+#define I2C_CR1_ADDRIE_Pos           (3U)

+#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */

+#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */

+#define I2C_CR1_NACKIE_Pos           (4U)

+#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */

+#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */

+#define I2C_CR1_STOPIE_Pos           (5U)

+#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */

+#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */

+#define I2C_CR1_TCIE_Pos             (6U)

+#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */

+#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */

+#define I2C_CR1_ERRIE_Pos            (7U)

+#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */

+#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */

+#define I2C_CR1_DNF_Pos              (8U)

+#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */

+#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */

+#define I2C_CR1_ANFOFF_Pos           (12U)

+#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */

+#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */

+#define I2C_CR1_TXDMAEN_Pos          (14U)

+#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */

+#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */

+#define I2C_CR1_RXDMAEN_Pos          (15U)

+#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */

+#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */

+#define I2C_CR1_SBC_Pos              (16U)

+#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */

+#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */

+#define I2C_CR1_NOSTRETCH_Pos        (17U)

+#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */

+#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */

+#define I2C_CR1_WUPEN_Pos            (18U)

+#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */

+#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */

+#define I2C_CR1_GCEN_Pos             (19U)

+#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */

+#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */

+#define I2C_CR1_SMBHEN_Pos           (20U)

+#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */

+#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */

+#define I2C_CR1_SMBDEN_Pos           (21U)

+#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */

+#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */

+#define I2C_CR1_ALERTEN_Pos          (22U)

+#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */

+#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */

+#define I2C_CR1_PECEN_Pos            (23U)

+#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */

+#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */

+

+/******************  Bit definition for I2C_CR2 register  ********************/

+#define I2C_CR2_SADD_Pos             (0U)

+#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */

+#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */

+#define I2C_CR2_RD_WRN_Pos           (10U)

+#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */

+#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */

+#define I2C_CR2_ADD10_Pos            (11U)

+#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */

+#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */

+#define I2C_CR2_HEAD10R_Pos          (12U)

+#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */

+#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */

+#define I2C_CR2_START_Pos            (13U)

+#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */

+#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */

+#define I2C_CR2_STOP_Pos             (14U)

+#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */

+#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */

+#define I2C_CR2_NACK_Pos             (15U)

+#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */

+#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */

+#define I2C_CR2_NBYTES_Pos           (16U)

+#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */

+#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */

+#define I2C_CR2_RELOAD_Pos           (24U)

+#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */

+#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */

+#define I2C_CR2_AUTOEND_Pos          (25U)

+#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */

+#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */

+#define I2C_CR2_PECBYTE_Pos          (26U)

+#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */

+#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */

+

+/*******************  Bit definition for I2C_OAR1 register  ******************/

+#define I2C_OAR1_OA1_Pos             (0U)

+#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */

+#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */

+#define I2C_OAR1_OA1MODE_Pos         (10U)

+#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */

+#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */

+#define I2C_OAR1_OA1EN_Pos           (15U)

+#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */

+#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */

+

+/*******************  Bit definition for I2C_OAR2 register  ******************/

+#define I2C_OAR2_OA2_Pos             (1U)

+#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */

+#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */

+#define I2C_OAR2_OA2MSK_Pos          (8U)

+#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */

+#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */

+#define I2C_OAR2_OA2NOMASK           0x00000000UL                              /*!< No mask */

+#define I2C_OAR2_OA2MASK01_Pos       (8U)

+#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */

+#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared */

+#define I2C_OAR2_OA2MASK02_Pos       (9U)

+#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */

+#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */

+#define I2C_OAR2_OA2MASK03_Pos       (8U)

+#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */

+#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */

+#define I2C_OAR2_OA2MASK04_Pos       (10U)

+#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */

+#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */

+#define I2C_OAR2_OA2MASK05_Pos       (8U)

+#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */

+#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */

+#define I2C_OAR2_OA2MASK06_Pos       (9U)

+#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */

+#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared */

+#define I2C_OAR2_OA2MASK07_Pos       (8U)

+#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */

+#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done */

+#define I2C_OAR2_OA2EN_Pos           (15U)

+#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */

+#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */

+

+/*******************  Bit definition for I2C_TIMINGR register *******************/

+#define I2C_TIMINGR_SCLL_Pos         (0U)

+#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */

+#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */

+#define I2C_TIMINGR_SCLH_Pos         (8U)

+#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */

+#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */

+#define I2C_TIMINGR_SDADEL_Pos       (16U)

+#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */

+#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */

+#define I2C_TIMINGR_SCLDEL_Pos       (20U)

+#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */

+#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */

+#define I2C_TIMINGR_PRESC_Pos        (28U)

+#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */

+#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */

+

+/******************* Bit definition for I2C_TIMEOUTR register *******************/

+#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)

+#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */

+#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */

+#define I2C_TIMEOUTR_TIDLE_Pos       (12U)

+#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */

+#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */

+#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)

+#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */

+#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */

+#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)

+#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */

+#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/

+#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)

+#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */

+#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */

+

+/******************  Bit definition for I2C_ISR register  *********************/

+#define I2C_ISR_TXE_Pos              (0U)

+#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */

+#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */

+#define I2C_ISR_TXIS_Pos             (1U)

+#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */

+#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */

+#define I2C_ISR_RXNE_Pos             (2U)

+#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */

+#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */

+#define I2C_ISR_ADDR_Pos             (3U)

+#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */

+#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/

+#define I2C_ISR_NACKF_Pos            (4U)

+#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */

+#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */

+#define I2C_ISR_STOPF_Pos            (5U)

+#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */

+#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */

+#define I2C_ISR_TC_Pos               (6U)

+#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */

+#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */

+#define I2C_ISR_TCR_Pos              (7U)

+#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */

+#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */

+#define I2C_ISR_BERR_Pos             (8U)

+#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */

+#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */

+#define I2C_ISR_ARLO_Pos             (9U)

+#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */

+#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */

+#define I2C_ISR_OVR_Pos              (10U)

+#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */

+#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */

+#define I2C_ISR_PECERR_Pos           (11U)

+#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */

+#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */

+#define I2C_ISR_TIMEOUT_Pos          (12U)

+#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */

+#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */

+#define I2C_ISR_ALERT_Pos            (13U)

+#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */

+#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */

+#define I2C_ISR_BUSY_Pos             (15U)

+#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */

+#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */

+#define I2C_ISR_DIR_Pos              (16U)

+#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */

+#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */

+#define I2C_ISR_ADDCODE_Pos          (17U)

+#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */

+#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */

+

+/******************  Bit definition for I2C_ICR register  *********************/

+#define I2C_ICR_ADDRCF_Pos           (3U)

+#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */

+#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */

+#define I2C_ICR_NACKCF_Pos           (4U)

+#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */

+#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */

+#define I2C_ICR_STOPCF_Pos           (5U)

+#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */

+#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */

+#define I2C_ICR_BERRCF_Pos           (8U)

+#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */

+#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */

+#define I2C_ICR_ARLOCF_Pos           (9U)

+#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */

+#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */

+#define I2C_ICR_OVRCF_Pos            (10U)

+#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */

+#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */

+#define I2C_ICR_PECCF_Pos            (11U)

+#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */

+#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */

+#define I2C_ICR_TIMOUTCF_Pos         (12U)

+#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */

+#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */

+#define I2C_ICR_ALERTCF_Pos          (13U)

+#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */

+#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */

+

+/******************  Bit definition for I2C_PECR register  *********************/

+#define I2C_PECR_PEC_Pos             (0U)

+#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */

+#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */

+

+/******************  Bit definition for I2C_RXDR register  *********************/

+#define I2C_RXDR_RXDATA_Pos          (0U)

+#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */

+#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */

+

+/******************  Bit definition for I2C_TXDR register  *********************/

+#define I2C_TXDR_TXDATA_Pos          (0U)

+#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */

+#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           Independent WATCHDOG                             */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for IWDG_KR register  ********************/

+#define IWDG_KR_KEY_Pos      (0U)

+#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */

+#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */

+

+/*******************  Bit definition for IWDG_PR register  ********************/

+#define IWDG_PR_PR_Pos       (0U)

+#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */

+#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */

+#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */

+#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */

+#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */

+

+/*******************  Bit definition for IWDG_RLR register  *******************/

+#define IWDG_RLR_RL_Pos      (0U)

+#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */

+#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */

+

+/*******************  Bit definition for IWDG_SR register  ********************/

+#define IWDG_SR_PVU_Pos      (0U)

+#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */

+#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */

+#define IWDG_SR_RVU_Pos      (1U)

+#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */

+#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */

+#define IWDG_SR_WVU_Pos      (2U)

+#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */

+#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */

+

+/*******************  Bit definition for IWDG_KR register  ********************/

+#define IWDG_WINR_WIN_Pos    (0U)

+#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */

+#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */

+

+/******************************************************************************/

+/*                                                                            */

+/*                        JPEG Encoder/Decoder                                */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for CONFR0 register  ********************/

+#define JPEG_CONFR0_START_Pos           (0U)

+#define JPEG_CONFR0_START_Msk           (0x1UL << JPEG_CONFR0_START_Pos)       /*!< 0x00000001 */

+#define JPEG_CONFR0_START               JPEG_CONFR0_START_Msk                  /*!<Start/Stop bit */

+

+/********************  Bit definition for CONFR1 register  ********************/

+#define JPEG_CONFR1_NF_Pos              (0U)

+#define JPEG_CONFR1_NF_Msk              (0x3UL << JPEG_CONFR1_NF_Pos)          /*!< 0x00000003 */

+#define JPEG_CONFR1_NF                  JPEG_CONFR1_NF_Msk                     /*!<Number of color components */

+#define JPEG_CONFR1_NF_0                (0x1UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000001 */

+#define JPEG_CONFR1_NF_1                (0x2UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000002 */

+#define JPEG_CONFR1_DE_Pos              (3U)

+#define JPEG_CONFR1_DE_Msk              (0x1UL << JPEG_CONFR1_DE_Pos)          /*!< 0x00000008 */

+#define JPEG_CONFR1_DE                  JPEG_CONFR1_DE_Msk                     /*!<Decoding Enable */

+#define JPEG_CONFR1_COLORSPACE_Pos      (4U)

+#define JPEG_CONFR1_COLORSPACE_Msk      (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)  /*!< 0x00000030 */

+#define JPEG_CONFR1_COLORSPACE          JPEG_CONFR1_COLORSPACE_Msk             /*!<Color Space */

+#define JPEG_CONFR1_COLORSPACE_0        (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000010 */

+#define JPEG_CONFR1_COLORSPACE_1        (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000020 */

+#define JPEG_CONFR1_NS_Pos              (6U)

+#define JPEG_CONFR1_NS_Msk              (0x3UL << JPEG_CONFR1_NS_Pos)          /*!< 0x000000C0 */

+#define JPEG_CONFR1_NS                  JPEG_CONFR1_NS_Msk                     /*!<Number of components for Scan */

+#define JPEG_CONFR1_NS_0                (0x1UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR1_NS_1                (0x2UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR1_HDR_Pos             (8U)

+#define JPEG_CONFR1_HDR_Msk             (0x1UL << JPEG_CONFR1_HDR_Pos)         /*!< 0x00000100 */

+#define JPEG_CONFR1_HDR                 JPEG_CONFR1_HDR_Msk                    /*!<Header Processing On/Off */

+#define JPEG_CONFR1_YSIZE_Pos           (16U)

+#define JPEG_CONFR1_YSIZE_Msk           (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)    /*!< 0xFFFF0000 */

+#define JPEG_CONFR1_YSIZE               JPEG_CONFR1_YSIZE_Msk                  /*!<Number of lines in source image */

+

+/********************  Bit definition for CONFR2 register  ********************/

+#define JPEG_CONFR2_NMCU_Pos            (0U)

+#define JPEG_CONFR2_NMCU_Msk            (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)  /*!< 0x03FFFFFF */

+#define JPEG_CONFR2_NMCU                JPEG_CONFR2_NMCU_Msk                   /*!<Number of MCU units minus 1 to encode */

+

+/********************  Bit definition for CONFR3 register  ********************/

+#define JPEG_CONFR3_XSIZE_Pos           (16U)

+#define JPEG_CONFR3_XSIZE_Msk           (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)    /*!< 0xFFFF0000 */

+#define JPEG_CONFR3_XSIZE               JPEG_CONFR3_XSIZE_Msk                  /*!<Number of pixels per line */

+

+/********************  Bit definition for CONFR4 register  ********************/

+#define JPEG_CONFR4_HD_Pos              (0U)

+#define JPEG_CONFR4_HD_Msk              (0x1UL << JPEG_CONFR4_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR4_HD                  JPEG_CONFR4_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR4_HA_Pos              (1U)

+#define JPEG_CONFR4_HA_Msk              (0x1UL << JPEG_CONFR4_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR4_HA                  JPEG_CONFR4_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR4_QT_Pos              (2U)

+#define JPEG_CONFR4_QT_Msk              (0x3UL << JPEG_CONFR4_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR4_QT                  JPEG_CONFR4_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR4_QT_0                (0x1UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR4_QT_1                (0x2UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR4_NB_Pos              (4U)

+#define JPEG_CONFR4_NB_Msk              (0xFUL << JPEG_CONFR4_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR4_NB                  JPEG_CONFR4_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR4_NB_0                (0x1UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR4_NB_1                (0x2UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR4_NB_2                (0x4UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR4_NB_3                (0x8UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR4_VSF_Pos             (8U)

+#define JPEG_CONFR4_VSF_Msk             (0xFUL << JPEG_CONFR4_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR4_VSF                 JPEG_CONFR4_VSF_Msk                    /*!<Vertical sampling factor for component 1 */

+#define JPEG_CONFR4_VSF_0               (0x1UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR4_VSF_1               (0x2UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR4_VSF_2               (0x4UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR4_VSF_3               (0x8UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR4_HSF_Pos             (12U)

+#define JPEG_CONFR4_HSF_Msk             (0xFUL << JPEG_CONFR4_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR4_HSF                 JPEG_CONFR4_HSF_Msk                    /*!<Horizontal sampling factor for component 1 */

+#define JPEG_CONFR4_HSF_0               (0x1UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR4_HSF_1               (0x2UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR4_HSF_2               (0x4UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR4_HSF_3               (0x8UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR5 register  ********************/

+#define JPEG_CONFR5_HD_Pos              (0U)

+#define JPEG_CONFR5_HD_Msk              (0x1UL << JPEG_CONFR5_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR5_HD                  JPEG_CONFR5_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR5_HA_Pos              (1U)

+#define JPEG_CONFR5_HA_Msk              (0x1UL << JPEG_CONFR5_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR5_HA                  JPEG_CONFR5_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR5_QT_Pos              (2U)

+#define JPEG_CONFR5_QT_Msk              (0x3UL << JPEG_CONFR5_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR5_QT                  JPEG_CONFR5_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR5_QT_0                (0x1UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR5_QT_1                (0x2UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR5_NB_Pos              (4U)

+#define JPEG_CONFR5_NB_Msk              (0xFUL << JPEG_CONFR5_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR5_NB                  JPEG_CONFR5_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR5_NB_0                (0x1UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR5_NB_1                (0x2UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR5_NB_2                (0x4UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR5_NB_3                (0x8UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR5_VSF_Pos             (8U)

+#define JPEG_CONFR5_VSF_Msk             (0xFUL << JPEG_CONFR5_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR5_VSF                 JPEG_CONFR5_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR5_VSF_0               (0x1UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR5_VSF_1               (0x2UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR5_VSF_2               (0x4UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR5_VSF_3               (0x8UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR5_HSF_Pos             (12U)

+#define JPEG_CONFR5_HSF_Msk             (0xFUL << JPEG_CONFR5_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR5_HSF                 JPEG_CONFR5_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR5_HSF_0               (0x1UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR5_HSF_1               (0x2UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR5_HSF_2               (0x4UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR5_HSF_3               (0x8UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR6 register  ********************/

+#define JPEG_CONFR6_HD_Pos              (0U)

+#define JPEG_CONFR6_HD_Msk              (0x1UL << JPEG_CONFR6_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR6_HD                  JPEG_CONFR6_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR6_HA_Pos              (1U)

+#define JPEG_CONFR6_HA_Msk              (0x1UL << JPEG_CONFR6_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR6_HA                  JPEG_CONFR6_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR6_QT_Pos              (2U)

+#define JPEG_CONFR6_QT_Msk              (0x3UL << JPEG_CONFR6_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR6_QT                  JPEG_CONFR6_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR6_QT_0                (0x1UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR6_QT_1                (0x2UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR6_NB_Pos              (4U)

+#define JPEG_CONFR6_NB_Msk              (0xFUL << JPEG_CONFR6_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR6_NB                  JPEG_CONFR6_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR6_NB_0                (0x1UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR6_NB_1                (0x2UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR6_NB_2                (0x4UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR6_NB_3                (0x8UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR6_VSF_Pos             (8U)

+#define JPEG_CONFR6_VSF_Msk             (0xFUL << JPEG_CONFR6_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR6_VSF                 JPEG_CONFR6_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR6_VSF_0               (0x1UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR6_VSF_1               (0x2UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR6_VSF_2               (0x4UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR6_VSF_3               (0x8UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR6_HSF_Pos             (12U)

+#define JPEG_CONFR6_HSF_Msk             (0xFUL << JPEG_CONFR6_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR6_HSF                 JPEG_CONFR6_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR6_HSF_0               (0x1UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR6_HSF_1               (0x2UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR6_HSF_2               (0x4UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR6_HSF_3               (0x8UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR7 register  ********************/

+#define JPEG_CONFR7_HD_Pos              (0U)

+#define JPEG_CONFR7_HD_Msk              (0x1UL << JPEG_CONFR7_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR7_HD                  JPEG_CONFR7_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR7_HA_Pos              (1U)

+#define JPEG_CONFR7_HA_Msk              (0x1UL << JPEG_CONFR7_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR7_HA                  JPEG_CONFR7_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR7_QT_Pos              (2U)

+#define JPEG_CONFR7_QT_Msk              (0x3UL << JPEG_CONFR7_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR7_QT                  JPEG_CONFR7_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR7_QT_0                (0x1UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR7_QT_1                (0x2UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR7_NB_Pos              (4U)

+#define JPEG_CONFR7_NB_Msk              (0xFUL << JPEG_CONFR7_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR7_NB                  JPEG_CONFR7_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR7_NB_0                (0x1UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR7_NB_1                (0x2UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR7_NB_2                (0x4UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR7_NB_3                (0x8UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR7_VSF_Pos             (8U)

+#define JPEG_CONFR7_VSF_Msk             (0xFUL << JPEG_CONFR7_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR7_VSF                 JPEG_CONFR7_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR7_VSF_0               (0x1UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR7_VSF_1               (0x2UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR7_VSF_2               (0x4UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR7_VSF_3               (0x8UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR7_HSF_Pos             (12U)

+#define JPEG_CONFR7_HSF_Msk             (0xFUL << JPEG_CONFR7_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR7_HSF                 JPEG_CONFR7_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR7_HSF_0               (0x1UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR7_HSF_1               (0x2UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR7_HSF_2               (0x4UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR7_HSF_3               (0x8UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CR register  ********************/

+#define JPEG_CR_JCEN_Pos                (0U)

+#define JPEG_CR_JCEN_Msk                (0x1UL << JPEG_CR_JCEN_Pos)            /*!< 0x00000001 */

+#define JPEG_CR_JCEN                    JPEG_CR_JCEN_Msk                       /*!<Enable the JPEG Codec Core */

+#define JPEG_CR_IFTIE_Pos               (1U)

+#define JPEG_CR_IFTIE_Msk               (0x1UL << JPEG_CR_IFTIE_Pos)           /*!< 0x00000002 */

+#define JPEG_CR_IFTIE                   JPEG_CR_IFTIE_Msk                      /*!<Input FIFO Threshold Interrupt Enable */

+#define JPEG_CR_IFNFIE_Pos              (2U)

+#define JPEG_CR_IFNFIE_Msk              (0x1UL << JPEG_CR_IFNFIE_Pos)          /*!< 0x00000004 */

+#define JPEG_CR_IFNFIE                  JPEG_CR_IFNFIE_Msk                     /*!<Input FIFO Not Full Interrupt Enable */

+#define JPEG_CR_OFTIE_Pos               (3U)

+#define JPEG_CR_OFTIE_Msk               (0x1UL << JPEG_CR_OFTIE_Pos)           /*!< 0x00000008 */

+#define JPEG_CR_OFTIE                   JPEG_CR_OFTIE_Msk                      /*!<Output FIFO Threshold Interrupt Enable */

+#define JPEG_CR_OFNEIE_Pos              (4U)

+#define JPEG_CR_OFNEIE_Msk              (0x1UL << JPEG_CR_OFNEIE_Pos)          /*!< 0x00000010 */

+#define JPEG_CR_OFNEIE                  JPEG_CR_OFNEIE_Msk                     /*!<Output FIFO Not Empty Interrupt Enable */

+#define JPEG_CR_EOCIE_Pos               (5U)

+#define JPEG_CR_EOCIE_Msk               (0x1UL << JPEG_CR_EOCIE_Pos)           /*!< 0x00000020 */

+#define JPEG_CR_EOCIE                   JPEG_CR_EOCIE_Msk                      /*!<End of Conversion Interrupt Enable */

+#define JPEG_CR_HPDIE_Pos               (6U)

+#define JPEG_CR_HPDIE_Msk               (0x1UL << JPEG_CR_HPDIE_Pos)           /*!< 0x00000040 */

+#define JPEG_CR_HPDIE                   JPEG_CR_HPDIE_Msk                      /*!<Header Parsing Done Interrupt Enable */

+#define JPEG_CR_IFF_Pos                 (13U)

+#define JPEG_CR_IFF_Msk                 (0x1UL << JPEG_CR_IFF_Pos)             /*!< 0x00002000 */

+#define JPEG_CR_IFF                     JPEG_CR_IFF_Msk                        /*!<Flush the input FIFO */

+#define JPEG_CR_OFF_Pos                 (14U)

+#define JPEG_CR_OFF_Msk                 (0x1UL << JPEG_CR_OFF_Pos)             /*!< 0x00004000 */

+#define JPEG_CR_OFF                     JPEG_CR_OFF_Msk                        /*!<Flush the output FIFO */

+

+/********************  Bit definition for SR register  ********************/

+#define JPEG_SR_IFTF_Pos                (1U)

+#define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */

+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is bellow its threshold flag */

+#define JPEG_SR_IFNFF_Pos               (2U)

+#define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */

+#define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */

+#define JPEG_SR_OFTF_Pos                (3U)

+#define JPEG_SR_OFTF_Msk                (0x1UL << JPEG_SR_OFTF_Pos)            /*!< 0x00000008 */

+#define JPEG_SR_OFTF                    JPEG_SR_OFTF_Msk                       /*!<Output FIFO is not empty and has reach its threshold */

+#define JPEG_SR_OFNEF_Pos               (4U)

+#define JPEG_SR_OFNEF_Msk               (0x1UL << JPEG_SR_OFNEF_Pos)           /*!< 0x00000010 */

+#define JPEG_SR_OFNEF                   JPEG_SR_OFNEF_Msk                      /*!<Output FIFO is not empty, a data is available */

+#define JPEG_SR_EOCF_Pos                (5U)

+#define JPEG_SR_EOCF_Msk                (0x1UL << JPEG_SR_EOCF_Pos)            /*!< 0x00000020 */

+#define JPEG_SR_EOCF                    JPEG_SR_EOCF_Msk                       /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */

+#define JPEG_SR_HPDF_Pos                (6U)

+#define JPEG_SR_HPDF_Msk                (0x1UL << JPEG_SR_HPDF_Pos)            /*!< 0x00000040 */

+#define JPEG_SR_HPDF                    JPEG_SR_HPDF_Msk                       /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */

+#define JPEG_SR_COF_Pos                 (7U)

+#define JPEG_SR_COF_Msk                 (0x1UL << JPEG_SR_COF_Pos)             /*!< 0x00000080 */

+#define JPEG_SR_COF                     JPEG_SR_COF_Msk                        /*!<JPEG Codec operation on going flag */

+

+/********************  Bit definition for CFR register  ********************/

+#define JPEG_CFR_CEOCF_Pos              (4U)

+#define JPEG_CFR_CEOCF_Msk              (0x1UL << JPEG_CFR_CEOCF_Pos)          /*!< 0x00000010 */

+#define JPEG_CFR_CEOCF                  JPEG_CFR_CEOCF_Msk                     /*!<Clear End of Conversion Flag */

+#define JPEG_CFR_CHPDF_Pos              (5U)

+#define JPEG_CFR_CHPDF_Msk              (0x1UL << JPEG_CFR_CHPDF_Pos)          /*!< 0x00000020 */

+#define JPEG_CFR_CHPDF                  JPEG_CFR_CHPDF_Msk                     /*!<Clear Header Parsing Done Flag */

+

+/********************  Bit definition for DIR register  ********************/

+#define JPEG_DIR_DATAIN_Pos             (0U)

+#define JPEG_DIR_DATAIN_Msk             (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)  /*!< 0xFFFFFFFF */

+#define JPEG_DIR_DATAIN                 JPEG_DIR_DATAIN_Msk                    /*!<Data Input FIFO */

+

+/********************  Bit definition for DOR register  ********************/

+#define JPEG_DOR_DATAOUT_Pos            (0U)

+#define JPEG_DOR_DATAOUT_Msk            (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */

+#define JPEG_DOR_DATAOUT                JPEG_DOR_DATAOUT_Msk                   /*!<Data Output FIFO */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      LCD-TFT Display Controller (LTDC)                     */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for LTDC_SSCR register  *****************/

+

+#define LTDC_SSCR_VSH_Pos            (0U)

+#define LTDC_SSCR_VSH_Msk            (0x7FFUL << LTDC_SSCR_VSH_Pos)            /*!< 0x000007FF */

+#define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height  */

+#define LTDC_SSCR_HSW_Pos            (16U)

+#define LTDC_SSCR_HSW_Msk            (0xFFFUL << LTDC_SSCR_HSW_Pos)            /*!< 0x0FFF0000 */

+#define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */

+

+/********************  Bit definition for LTDC_BPCR register  *****************/

+

+#define LTDC_BPCR_AVBP_Pos           (0U)

+#define LTDC_BPCR_AVBP_Msk           (0x7FFUL << LTDC_BPCR_AVBP_Pos)           /*!< 0x000007FF */

+#define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch   */

+#define LTDC_BPCR_AHBP_Pos           (16U)

+#define LTDC_BPCR_AHBP_Msk           (0xFFFUL << LTDC_BPCR_AHBP_Pos)           /*!< 0x0FFF0000 */

+#define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */

+

+/********************  Bit definition for LTDC_AWCR register  *****************/

+

+#define LTDC_AWCR_AAH_Pos            (0U)

+#define LTDC_AWCR_AAH_Msk            (0x7FFUL << LTDC_AWCR_AAH_Pos)            /*!< 0x000007FF */

+#define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active heigh */

+#define LTDC_AWCR_AAW_Pos            (16U)

+#define LTDC_AWCR_AAW_Msk            (0xFFFUL << LTDC_AWCR_AAW_Pos)            /*!< 0x0FFF0000 */

+#define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */

+

+/********************  Bit definition for LTDC_TWCR register  *****************/

+

+#define LTDC_TWCR_TOTALH_Pos         (0U)

+#define LTDC_TWCR_TOTALH_Msk         (0x7FFUL << LTDC_TWCR_TOTALH_Pos)         /*!< 0x000007FF */

+#define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total Heigh */

+#define LTDC_TWCR_TOTALW_Pos         (16U)

+#define LTDC_TWCR_TOTALW_Msk         (0xFFFUL << LTDC_TWCR_TOTALW_Pos)         /*!< 0x0FFF0000 */

+#define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */

+

+/********************  Bit definition for LTDC_GCR register  ******************/

+

+#define LTDC_GCR_LTDCEN_Pos          (0U)

+#define LTDC_GCR_LTDCEN_Msk          (0x1UL << LTDC_GCR_LTDCEN_Pos)            /*!< 0x00000001 */

+#define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit       */

+#define LTDC_GCR_DBW_Pos             (4U)

+#define LTDC_GCR_DBW_Msk             (0x7UL << LTDC_GCR_DBW_Pos)               /*!< 0x00000070 */

+#define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width                   */

+#define LTDC_GCR_DGW_Pos             (8U)

+#define LTDC_GCR_DGW_Msk             (0x7UL << LTDC_GCR_DGW_Pos)               /*!< 0x00000700 */

+#define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width                  */

+#define LTDC_GCR_DRW_Pos             (12U)

+#define LTDC_GCR_DRW_Msk             (0x7UL << LTDC_GCR_DRW_Pos)               /*!< 0x00007000 */

+#define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width                    */

+#define LTDC_GCR_DEN_Pos             (16U)

+#define LTDC_GCR_DEN_Msk             (0x1UL << LTDC_GCR_DEN_Pos)               /*!< 0x00010000 */

+#define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable                       */

+#define LTDC_GCR_PCPOL_Pos           (28U)

+#define LTDC_GCR_PCPOL_Msk           (0x1UL << LTDC_GCR_PCPOL_Pos)             /*!< 0x10000000 */

+#define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity                */

+#define LTDC_GCR_DEPOL_Pos           (29U)

+#define LTDC_GCR_DEPOL_Msk           (0x1UL << LTDC_GCR_DEPOL_Pos)             /*!< 0x20000000 */

+#define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity                */

+#define LTDC_GCR_VSPOL_Pos           (30U)

+#define LTDC_GCR_VSPOL_Msk           (0x1UL << LTDC_GCR_VSPOL_Pos)             /*!< 0x40000000 */

+#define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity   */

+#define LTDC_GCR_HSPOL_Pos           (31U)

+#define LTDC_GCR_HSPOL_Msk           (0x1UL << LTDC_GCR_HSPOL_Pos)             /*!< 0x80000000 */

+#define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */

+

+

+/********************  Bit definition for LTDC_SRCR register  *****************/

+

+#define LTDC_SRCR_IMR_Pos            (0U)

+#define LTDC_SRCR_IMR_Msk            (0x1UL << LTDC_SRCR_IMR_Pos)              /*!< 0x00000001 */

+#define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload         */

+#define LTDC_SRCR_VBR_Pos            (1U)

+#define LTDC_SRCR_VBR_Msk            (0x1UL << LTDC_SRCR_VBR_Pos)              /*!< 0x00000002 */

+#define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */

+

+/********************  Bit definition for LTDC_BCCR register  *****************/

+

+#define LTDC_BCCR_BCBLUE_Pos         (0U)

+#define LTDC_BCCR_BCBLUE_Msk         (0xFFUL << LTDC_BCCR_BCBLUE_Pos)          /*!< 0x000000FF */

+#define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value  */

+#define LTDC_BCCR_BCGREEN_Pos        (8U)

+#define LTDC_BCCR_BCGREEN_Msk        (0xFFUL << LTDC_BCCR_BCGREEN_Pos)         /*!< 0x0000FF00 */

+#define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */

+#define LTDC_BCCR_BCRED_Pos          (16U)

+#define LTDC_BCCR_BCRED_Msk          (0xFFUL << LTDC_BCCR_BCRED_Pos)           /*!< 0x00FF0000 */

+#define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value   */

+

+/********************  Bit definition for LTDC_IER register  ******************/

+

+#define LTDC_IER_LIE_Pos             (0U)

+#define LTDC_IER_LIE_Msk             (0x1UL << LTDC_IER_LIE_Pos)               /*!< 0x00000001 */

+#define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable            */

+#define LTDC_IER_FUIE_Pos            (1U)

+#define LTDC_IER_FUIE_Msk            (0x1UL << LTDC_IER_FUIE_Pos)              /*!< 0x00000002 */

+#define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable   */

+#define LTDC_IER_TERRIE_Pos          (2U)

+#define LTDC_IER_TERRIE_Msk          (0x1UL << LTDC_IER_TERRIE_Pos)            /*!< 0x00000004 */

+#define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable  */

+#define LTDC_IER_RRIE_Pos            (3U)

+#define LTDC_IER_RRIE_Msk            (0x1UL << LTDC_IER_RRIE_Pos)              /*!< 0x00000008 */

+#define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */

+

+/********************  Bit definition for LTDC_ISR register  ******************/

+

+#define LTDC_ISR_LIF_Pos             (0U)

+#define LTDC_ISR_LIF_Msk             (0x1UL << LTDC_ISR_LIF_Pos)               /*!< 0x00000001 */

+#define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */

+#define LTDC_ISR_FUIF_Pos            (1U)

+#define LTDC_ISR_FUIF_Msk            (0x1UL << LTDC_ISR_FUIF_Pos)              /*!< 0x00000002 */

+#define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */

+#define LTDC_ISR_TERRIF_Pos          (2U)

+#define LTDC_ISR_TERRIF_Msk          (0x1UL << LTDC_ISR_TERRIF_Pos)            /*!< 0x00000004 */

+#define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */

+#define LTDC_ISR_RRIF_Pos            (3U)

+#define LTDC_ISR_RRIF_Msk            (0x1UL << LTDC_ISR_RRIF_Pos)              /*!< 0x00000008 */

+#define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */

+

+/********************  Bit definition for LTDC_ICR register  ******************/

+

+#define LTDC_ICR_CLIF_Pos            (0U)

+#define LTDC_ICR_CLIF_Msk            (0x1UL << LTDC_ICR_CLIF_Pos)              /*!< 0x00000001 */

+#define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */

+#define LTDC_ICR_CFUIF_Pos           (1U)

+#define LTDC_ICR_CFUIF_Msk           (0x1UL << LTDC_ICR_CFUIF_Pos)             /*!< 0x00000002 */

+#define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */

+#define LTDC_ICR_CTERRIF_Pos         (2U)

+#define LTDC_ICR_CTERRIF_Msk         (0x1UL << LTDC_ICR_CTERRIF_Pos)           /*!< 0x00000004 */

+#define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */

+#define LTDC_ICR_CRRIF_Pos           (3U)

+#define LTDC_ICR_CRRIF_Msk           (0x1UL << LTDC_ICR_CRRIF_Pos)             /*!< 0x00000008 */

+#define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */

+

+/********************  Bit definition for LTDC_LIPCR register  ****************/

+

+#define LTDC_LIPCR_LIPOS_Pos         (0U)

+#define LTDC_LIPCR_LIPOS_Msk         (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)         /*!< 0x000007FF */

+#define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */

+

+/********************  Bit definition for LTDC_CPSR register  *****************/

+

+#define LTDC_CPSR_CYPOS_Pos          (0U)

+#define LTDC_CPSR_CYPOS_Msk          (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)         /*!< 0x0000FFFF */

+#define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */

+#define LTDC_CPSR_CXPOS_Pos          (16U)

+#define LTDC_CPSR_CXPOS_Msk          (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)         /*!< 0xFFFF0000 */

+#define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */

+

+/********************  Bit definition for LTDC_CDSR register  *****************/

+

+#define LTDC_CDSR_VDES_Pos           (0U)

+#define LTDC_CDSR_VDES_Msk           (0x1UL << LTDC_CDSR_VDES_Pos)             /*!< 0x00000001 */

+#define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status       */

+#define LTDC_CDSR_HDES_Pos           (1U)

+#define LTDC_CDSR_HDES_Msk           (0x1UL << LTDC_CDSR_HDES_Pos)             /*!< 0x00000002 */

+#define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status     */

+#define LTDC_CDSR_VSYNCS_Pos         (2U)

+#define LTDC_CDSR_VSYNCS_Msk         (0x1UL << LTDC_CDSR_VSYNCS_Pos)           /*!< 0x00000004 */

+#define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status   */

+#define LTDC_CDSR_HSYNCS_Pos         (3U)

+#define LTDC_CDSR_HSYNCS_Msk         (0x1UL << LTDC_CDSR_HSYNCS_Pos)           /*!< 0x00000008 */

+#define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */

+

+/********************  Bit definition for LTDC_LxCR register  *****************/

+

+#define LTDC_LxCR_LEN_Pos            (0U)

+#define LTDC_LxCR_LEN_Msk            (0x1UL << LTDC_LxCR_LEN_Pos)              /*!< 0x00000001 */

+#define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable              */

+#define LTDC_LxCR_COLKEN_Pos         (1U)

+#define LTDC_LxCR_COLKEN_Msk         (0x1UL << LTDC_LxCR_COLKEN_Pos)           /*!< 0x00000002 */

+#define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable       */

+#define LTDC_LxCR_CLUTEN_Pos         (4U)

+#define LTDC_LxCR_CLUTEN_Msk         (0x1UL << LTDC_LxCR_CLUTEN_Pos)           /*!< 0x00000010 */

+#define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */

+

+/********************  Bit definition for LTDC_LxWHPCR register  **************/

+

+#define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)

+#define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)     /*!< 0x00000FFF */

+#define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */

+#define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)

+#define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)    /*!< 0xFFFF0000 */

+#define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position  */

+

+/********************  Bit definition for LTDC_LxWVPCR register  **************/

+

+#define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)

+#define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)     /*!< 0x00000FFF */

+#define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */

+#define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)

+#define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)    /*!< 0xFFFF0000 */

+#define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position  */

+

+/********************  Bit definition for LTDC_LxCKCR register  ***************/

+

+#define LTDC_LxCKCR_CKBLUE_Pos       (0U)

+#define LTDC_LxCKCR_CKBLUE_Msk       (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value  */

+#define LTDC_LxCKCR_CKGREEN_Pos      (8U)

+#define LTDC_LxCKCR_CKGREEN_Msk      (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */

+#define LTDC_LxCKCR_CKRED_Pos        (16U)

+#define LTDC_LxCKCR_CKRED_Msk        (0xFFUL << LTDC_LxCKCR_CKRED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value   */

+

+/********************  Bit definition for LTDC_LxPFCR register  ***************/

+

+#define LTDC_LxPFCR_PF_Pos           (0U)

+#define LTDC_LxPFCR_PF_Msk           (0x7UL << LTDC_LxPFCR_PF_Pos)             /*!< 0x00000007 */

+#define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */

+

+/********************  Bit definition for LTDC_LxCACR register  ***************/

+

+#define LTDC_LxCACR_CONSTA_Pos       (0U)

+#define LTDC_LxCACR_CONSTA_Msk       (0xFFUL << LTDC_LxCACR_CONSTA_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */

+

+/********************  Bit definition for LTDC_LxDCCR register  ***************/

+

+#define LTDC_LxDCCR_DCBLUE_Pos       (0U)

+#define LTDC_LxDCCR_DCBLUE_Msk       (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue  */

+#define LTDC_LxDCCR_DCGREEN_Pos      (8U)

+#define LTDC_LxDCCR_DCGREEN_Msk      (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */

+#define LTDC_LxDCCR_DCRED_Pos        (16U)

+#define LTDC_LxDCCR_DCRED_Msk        (0xFFUL << LTDC_LxDCCR_DCRED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red   */

+#define LTDC_LxDCCR_DCALPHA_Pos      (24U)

+#define LTDC_LxDCCR_DCALPHA_Msk      (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)       /*!< 0xFF000000 */

+#define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */

+

+/********************  Bit definition for LTDC_LxBFCR register  ***************/

+

+#define LTDC_LxBFCR_BF2_Pos          (0U)

+#define LTDC_LxBFCR_BF2_Msk          (0x7UL << LTDC_LxBFCR_BF2_Pos)            /*!< 0x00000007 */

+#define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */

+#define LTDC_LxBFCR_BF1_Pos          (8U)

+#define LTDC_LxBFCR_BF1_Msk          (0x7UL << LTDC_LxBFCR_BF1_Pos)            /*!< 0x00000700 */

+#define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */

+

+/********************  Bit definition for LTDC_LxCFBAR register  **************/

+

+#define LTDC_LxCFBAR_CFBADD_Pos      (0U)

+#define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */

+#define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */

+

+/********************  Bit definition for LTDC_LxCFBLR register  **************/

+

+#define LTDC_LxCFBLR_CFBLL_Pos       (0U)

+#define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)      /*!< 0x00001FFF */

+#define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length    */

+#define LTDC_LxCFBLR_CFBP_Pos        (16U)

+#define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)       /*!< 0x1FFF0000 */

+#define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */

+

+/********************  Bit definition for LTDC_LxCFBLNR register  *************/

+

+#define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)

+#define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)    /*!< 0x000007FF */

+#define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */

+

+/********************  Bit definition for LTDC_LxCLUTWR register  *************/

+

+#define LTDC_LxCLUTWR_BLUE_Pos       (0U)

+#define LTDC_LxCLUTWR_BLUE_Msk       (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value   */

+#define LTDC_LxCLUTWR_GREEN_Pos      (8U)

+#define LTDC_LxCLUTWR_GREEN_Msk      (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value  */

+#define LTDC_LxCLUTWR_RED_Pos        (16U)

+#define LTDC_LxCLUTWR_RED_Msk        (0xFFUL << LTDC_LxCLUTWR_RED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value    */

+#define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)

+#define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)     /*!< 0xFF000000 */

+#define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                     MDMA                                   */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for MDMA_GISR0 register  ****************/

+#define MDMA_GISR0_GIF0_Pos       (0U)

+#define MDMA_GISR0_GIF0_Msk       (0x1UL << MDMA_GISR0_GIF0_Pos)               /*!< 0x00000001 */

+#define MDMA_GISR0_GIF0           MDMA_GISR0_GIF0_Msk                          /*!< Channel 0 global interrupt flag */

+#define MDMA_GISR0_GIF1_Pos       (1U)

+#define MDMA_GISR0_GIF1_Msk       (0x1UL << MDMA_GISR0_GIF1_Pos)               /*!< 0x00000002 */

+#define MDMA_GISR0_GIF1           MDMA_GISR0_GIF1_Msk                          /*!< Channel 1 global interrupt flag */

+#define MDMA_GISR0_GIF2_Pos       (2U)

+#define MDMA_GISR0_GIF2_Msk       (0x1UL << MDMA_GISR0_GIF2_Pos)               /*!< 0x00000004 */

+#define MDMA_GISR0_GIF2           MDMA_GISR0_GIF2_Msk                          /*!< Channel 2 global interrupt flag */

+#define MDMA_GISR0_GIF3_Pos       (3U)

+#define MDMA_GISR0_GIF3_Msk       (0x1UL << MDMA_GISR0_GIF3_Pos)               /*!< 0x00000008 */

+#define MDMA_GISR0_GIF3           MDMA_GISR0_GIF3_Msk                          /*!< Channel 3 global interrupt flag */

+#define MDMA_GISR0_GIF4_Pos       (4U)

+#define MDMA_GISR0_GIF4_Msk       (0x1UL << MDMA_GISR0_GIF4_Pos)               /*!< 0x00000010 */

+#define MDMA_GISR0_GIF4           MDMA_GISR0_GIF4_Msk                          /*!< Channel 4 global interrupt flag */

+#define MDMA_GISR0_GIF5_Pos       (5U)

+#define MDMA_GISR0_GIF5_Msk       (0x1UL << MDMA_GISR0_GIF5_Pos)               /*!< 0x00000020 */

+#define MDMA_GISR0_GIF5           MDMA_GISR0_GIF5_Msk                          /*!< Channel 5 global interrupt flag */

+#define MDMA_GISR0_GIF6_Pos       (6U)

+#define MDMA_GISR0_GIF6_Msk       (0x1UL << MDMA_GISR0_GIF6_Pos)               /*!< 0x00000040 */

+#define MDMA_GISR0_GIF6           MDMA_GISR0_GIF6_Msk                          /*!< Channel 6 global interrupt flag */

+#define MDMA_GISR0_GIF7_Pos       (7U)

+#define MDMA_GISR0_GIF7_Msk       (0x1UL << MDMA_GISR0_GIF7_Pos)               /*!< 0x00000080 */

+#define MDMA_GISR0_GIF7           MDMA_GISR0_GIF7_Msk                          /*!< Channel 7 global interrupt flag */

+#define MDMA_GISR0_GIF8_Pos       (8U)

+#define MDMA_GISR0_GIF8_Msk       (0x1UL << MDMA_GISR0_GIF8_Pos)               /*!< 0x00000100 */

+#define MDMA_GISR0_GIF8           MDMA_GISR0_GIF8_Msk                          /*!< Channel 8 global interrupt flag */

+#define MDMA_GISR0_GIF9_Pos       (9U)

+#define MDMA_GISR0_GIF9_Msk       (0x1UL << MDMA_GISR0_GIF9_Pos)               /*!< 0x00000200 */

+#define MDMA_GISR0_GIF9           MDMA_GISR0_GIF9_Msk                          /*!< Channel 9 global interrupt flag */

+#define MDMA_GISR0_GIF10_Pos      (10U)

+#define MDMA_GISR0_GIF10_Msk      (0x1UL << MDMA_GISR0_GIF10_Pos)              /*!< 0x00000400 */

+#define MDMA_GISR0_GIF10          MDMA_GISR0_GIF10_Msk                         /*!< Channel 10 global interrupt flag */

+#define MDMA_GISR0_GIF11_Pos      (11U)

+#define MDMA_GISR0_GIF11_Msk      (0x1UL << MDMA_GISR0_GIF11_Pos)              /*!< 0x00000800 */

+#define MDMA_GISR0_GIF11          MDMA_GISR0_GIF11_Msk                         /*!< Channel 11 global interrupt flag */

+#define MDMA_GISR0_GIF12_Pos      (12U)

+#define MDMA_GISR0_GIF12_Msk      (0x1UL << MDMA_GISR0_GIF12_Pos)              /*!< 0x00001000 */

+#define MDMA_GISR0_GIF12          MDMA_GISR0_GIF12_Msk                         /*!< Channel 12 global interrupt flag */

+#define MDMA_GISR0_GIF13_Pos      (13U)

+#define MDMA_GISR0_GIF13_Msk      (0x1UL << MDMA_GISR0_GIF13_Pos)              /*!< 0x00002000 */

+#define MDMA_GISR0_GIF13          MDMA_GISR0_GIF13_Msk                         /*!< Channel 13 global interrupt flag */

+#define MDMA_GISR0_GIF14_Pos      (14U)

+#define MDMA_GISR0_GIF14_Msk      (0x1UL << MDMA_GISR0_GIF14_Pos)              /*!< 0x00004000 */

+#define MDMA_GISR0_GIF14          MDMA_GISR0_GIF14_Msk                         /*!< Channel 14 global interrupt flag */

+#define MDMA_GISR0_GIF15_Pos      (15U)

+#define MDMA_GISR0_GIF15_Msk      (0x1UL << MDMA_GISR0_GIF15_Pos)              /*!< 0x00008000 */

+#define MDMA_GISR0_GIF15          MDMA_GISR0_GIF15_Msk                         /*!< Channel 15 global interrupt flag */

+

+/********************  Bit definition for MDMA_CxISR register  ****************/

+#define MDMA_CISR_TEIF_Pos        (0U)

+#define MDMA_CISR_TEIF_Msk        (0x1UL << MDMA_CISR_TEIF_Pos)                /*!< 0x00000001 */

+#define MDMA_CISR_TEIF            MDMA_CISR_TEIF_Msk                           /*!< Channel x transfer error interrupt flag */

+#define MDMA_CISR_CTCIF_Pos       (1U)

+#define MDMA_CISR_CTCIF_Msk       (0x1UL << MDMA_CISR_CTCIF_Pos)               /*!< 0x00000002 */

+#define MDMA_CISR_CTCIF           MDMA_CISR_CTCIF_Msk                          /*!< Channel x Channel Transfer Complete interrupt flag */

+#define MDMA_CISR_BRTIF_Pos       (2U)

+#define MDMA_CISR_BRTIF_Msk       (0x1UL << MDMA_CISR_BRTIF_Pos)               /*!< 0x00000004 */

+#define MDMA_CISR_BRTIF           MDMA_CISR_BRTIF_Msk                          /*!< Channel x block repeat transfer complete interrupt flag */

+#define MDMA_CISR_BTIF_Pos        (3U)

+#define MDMA_CISR_BTIF_Msk        (0x1UL << MDMA_CISR_BTIF_Pos)                /*!< 0x00000008 */

+#define MDMA_CISR_BTIF            MDMA_CISR_BTIF_Msk                           /*!< Channel x block transfer complete interrupt flag */

+#define MDMA_CISR_TCIF_Pos        (4U)

+#define MDMA_CISR_TCIF_Msk        (0x1UL << MDMA_CISR_TCIF_Pos)                /*!< 0x00000010 */

+#define MDMA_CISR_TCIF            MDMA_CISR_TCIF_Msk                           /*!< Channel x buffer transfer complete interrupt flag */

+#define MDMA_CISR_CRQA_Pos        (16U)

+#define MDMA_CISR_CRQA_Msk        (0x1UL << MDMA_CISR_CRQA_Pos)                /*!< 0x00010000 */

+#define MDMA_CISR_CRQA            MDMA_CISR_CRQA_Msk                           /*!< Channel x ReQest Active flag */

+

+/********************  Bit definition for MDMA_CxIFCR register  ****************/

+#define MDMA_CIFCR_CTEIF_Pos      (0U)

+#define MDMA_CIFCR_CTEIF_Msk      (0x1UL << MDMA_CIFCR_CTEIF_Pos)              /*!< 0x00000001 */

+#define MDMA_CIFCR_CTEIF          MDMA_CIFCR_CTEIF_Msk                         /*!< Channel x clear transfer error interrupt flag */

+#define MDMA_CIFCR_CCTCIF_Pos     (1U)

+#define MDMA_CIFCR_CCTCIF_Msk     (0x1UL << MDMA_CIFCR_CCTCIF_Pos)             /*!< 0x00000002 */

+#define MDMA_CIFCR_CCTCIF         MDMA_CIFCR_CCTCIF_Msk                        /*!< Clear Channel transfer complete interrupt flag for channel x */

+#define MDMA_CIFCR_CBRTIF_Pos     (2U)

+#define MDMA_CIFCR_CBRTIF_Msk     (0x1UL << MDMA_CIFCR_CBRTIF_Pos)             /*!< 0x00000004 */

+#define MDMA_CIFCR_CBRTIF         MDMA_CIFCR_CBRTIF_Msk                        /*!< Channel x clear block repeat transfer complete interrupt flag */

+#define MDMA_CIFCR_CBTIF_Pos      (3U)

+#define MDMA_CIFCR_CBTIF_Msk      (0x1UL << MDMA_CIFCR_CBTIF_Pos)              /*!< 0x00000008 */

+#define MDMA_CIFCR_CBTIF          MDMA_CIFCR_CBTIF_Msk                         /*!< Channel x Clear block transfer complete interrupt flag */

+#define MDMA_CIFCR_CLTCIF_Pos     (4U)

+#define MDMA_CIFCR_CLTCIF_Msk     (0x1UL << MDMA_CIFCR_CLTCIF_Pos)             /*!< 0x00000010 */

+#define MDMA_CIFCR_CLTCIF         MDMA_CIFCR_CLTCIF_Msk                        /*!< CLear Transfer buffer Complete Interrupt Flag for channel */

+

+/********************  Bit definition for MDMA_CxESR register  ****************/

+#define MDMA_CESR_TEA_Pos         (0U)

+#define MDMA_CESR_TEA_Msk         (0x7FUL << MDMA_CESR_TEA_Pos)                /*!< 0x0000007F */

+#define MDMA_CESR_TEA             MDMA_CESR_TEA_Msk                            /*!< Transfer Error Address */

+#define MDMA_CESR_TED_Pos         (7U)

+#define MDMA_CESR_TED_Msk         (0x1UL << MDMA_CESR_TED_Pos)                 /*!< 0x00000080 */

+#define MDMA_CESR_TED             MDMA_CESR_TED_Msk                            /*!< Transfer Error Direction */

+#define MDMA_CESR_TELD_Pos        (8U)

+#define MDMA_CESR_TELD_Msk        (0x1UL << MDMA_CESR_TELD_Pos)                /*!< 0x00000100 */

+#define MDMA_CESR_TELD            MDMA_CESR_TELD_Msk                           /*!< Transfer Error Link Data */

+#define MDMA_CESR_TEMD_Pos        (9U)

+#define MDMA_CESR_TEMD_Msk        (0x1UL << MDMA_CESR_TEMD_Pos)                /*!< 0x00000200 */

+#define MDMA_CESR_TEMD            MDMA_CESR_TEMD_Msk                           /*!< Transfer Error Mask Data */

+#define MDMA_CESR_ASE_Pos         (10U)

+#define MDMA_CESR_ASE_Msk         (0x1UL << MDMA_CESR_ASE_Pos)                 /*!< 0x00000400 */

+#define MDMA_CESR_ASE             MDMA_CESR_ASE_Msk                            /*!< Address/Size Error       */

+#define MDMA_CESR_BSE_Pos         (11U)

+#define MDMA_CESR_BSE_Msk         (0x1UL << MDMA_CESR_BSE_Pos)                 /*!< 0x00000800 */

+#define MDMA_CESR_BSE             MDMA_CESR_BSE_Msk                            /*!< Block Size Error         */

+

+/********************  Bit definition for MDMA_CxCR register  ****************/

+#define MDMA_CCR_EN_Pos           (0U)

+#define MDMA_CCR_EN_Msk           (0x1UL << MDMA_CCR_EN_Pos)                   /*!< 0x00000001 */

+#define MDMA_CCR_EN               MDMA_CCR_EN_Msk                              /*!< Channel enable / flag channel ready when read low */

+#define MDMA_CCR_TEIE_Pos         (1U)

+#define MDMA_CCR_TEIE_Msk         (0x1UL << MDMA_CCR_TEIE_Pos)                 /*!< 0x00000002 */

+#define MDMA_CCR_TEIE             MDMA_CCR_TEIE_Msk                            /*!< Transfer error interrupt enable */

+#define MDMA_CCR_CTCIE_Pos        (2U)

+#define MDMA_CCR_CTCIE_Msk        (0x1UL << MDMA_CCR_CTCIE_Pos)                /*!< 0x00000004 */

+#define MDMA_CCR_CTCIE            MDMA_CCR_CTCIE_Msk                           /*!< Channel Transfer Complete interrupt enable */

+#define MDMA_CCR_BRTIE_Pos        (3U)

+#define MDMA_CCR_BRTIE_Msk        (0x1UL << MDMA_CCR_BRTIE_Pos)                /*!< 0x00000008 */

+#define MDMA_CCR_BRTIE            MDMA_CCR_BRTIE_Msk                           /*!< Block Repeat transfer interrupt enable */

+#define MDMA_CCR_BTIE_Pos         (4U)

+#define MDMA_CCR_BTIE_Msk         (0x1UL << MDMA_CCR_BTIE_Pos)                 /*!< 0x00000010 */

+#define MDMA_CCR_BTIE             MDMA_CCR_BTIE_Msk                            /*!< Block Transfer interrupt enable */

+#define MDMA_CCR_TCIE_Pos         (5U)

+#define MDMA_CCR_TCIE_Msk         (0x1UL << MDMA_CCR_TCIE_Pos)                 /*!< 0x00000020 */

+#define MDMA_CCR_TCIE             MDMA_CCR_TCIE_Msk                            /*!< buffer Transfer Complete interrupt enable */

+#define MDMA_CCR_PL_Pos           (6U)

+#define MDMA_CCR_PL_Msk           (0x3UL << MDMA_CCR_PL_Pos)                   /*!< 0x000000C0 */

+#define MDMA_CCR_PL               MDMA_CCR_PL_Msk                              /*!< Priority level */

+#define MDMA_CCR_PL_0             (0x1UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000040 */

+#define MDMA_CCR_PL_1             (0x2UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000080 */

+#define MDMA_CCR_BEX_Pos          (12U)

+#define MDMA_CCR_BEX_Msk          (0x1UL << MDMA_CCR_BEX_Pos)                  /*!< 0x00001000 */

+#define MDMA_CCR_BEX              MDMA_CCR_BEX_Msk                             /*!< Byte Endianess eXchange */

+#define MDMA_CCR_HEX_Pos          (13U)

+#define MDMA_CCR_HEX_Msk          (0x1UL << MDMA_CCR_HEX_Pos)                  /*!< 0x00002000 */

+#define MDMA_CCR_HEX              MDMA_CCR_HEX_Msk                             /*!< Half word Endianess eXchange */

+#define MDMA_CCR_WEX_Pos          (14U)

+#define MDMA_CCR_WEX_Msk          (0x1UL << MDMA_CCR_WEX_Pos)                  /*!< 0x00004000 */

+#define MDMA_CCR_WEX              MDMA_CCR_WEX_Msk                             /*!< Word Endianess eXchange */

+#define MDMA_CCR_SWRQ_Pos         (16U)

+#define MDMA_CCR_SWRQ_Msk         (0x1UL << MDMA_CCR_SWRQ_Pos)                 /*!< 0x00010000 */

+#define MDMA_CCR_SWRQ             MDMA_CCR_SWRQ_Msk                            /*!< SW ReQuest */

+

+/********************  Bit definition for MDMA_CxTCR register  ****************/

+#define MDMA_CTCR_SINC_Pos        (0U)

+#define MDMA_CTCR_SINC_Msk        (0x3UL << MDMA_CTCR_SINC_Pos)                /*!< 0x00000003 */

+#define MDMA_CTCR_SINC            MDMA_CTCR_SINC_Msk                           /*!< Source increment mode */

+#define MDMA_CTCR_SINC_0          (0x1UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000001 */

+#define MDMA_CTCR_SINC_1          (0x2UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000002 */

+#define MDMA_CTCR_DINC_Pos        (2U)

+#define MDMA_CTCR_DINC_Msk        (0x3UL << MDMA_CTCR_DINC_Pos)                /*!< 0x0000000C */

+#define MDMA_CTCR_DINC            MDMA_CTCR_DINC_Msk                           /*!< Source increment mode */

+#define MDMA_CTCR_DINC_0          (0x1UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000004 */

+#define MDMA_CTCR_DINC_1          (0x2UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000008 */

+#define MDMA_CTCR_SSIZE_Pos       (4U)

+#define MDMA_CTCR_SSIZE_Msk       (0x3UL << MDMA_CTCR_SSIZE_Pos)               /*!< 0x00000030 */

+#define MDMA_CTCR_SSIZE           MDMA_CTCR_SSIZE_Msk                          /*!< Source data size */

+#define MDMA_CTCR_SSIZE_0         (0x1UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000010 */

+#define MDMA_CTCR_SSIZE_1         (0x2UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000020 */

+#define MDMA_CTCR_DSIZE_Pos       (6U)

+#define MDMA_CTCR_DSIZE_Msk       (0x3UL << MDMA_CTCR_DSIZE_Pos)               /*!< 0x000000C0 */

+#define MDMA_CTCR_DSIZE           MDMA_CTCR_DSIZE_Msk                          /*!< Destination data size */

+#define MDMA_CTCR_DSIZE_0         (0x1UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000040 */

+#define MDMA_CTCR_DSIZE_1         (0x2UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000080 */

+#define MDMA_CTCR_SINCOS_Pos      (8U)

+#define MDMA_CTCR_SINCOS_Msk      (0x3UL << MDMA_CTCR_SINCOS_Pos)              /*!< 0x00000300 */

+#define MDMA_CTCR_SINCOS          MDMA_CTCR_SINCOS_Msk                         /*!< Source increment offset size */

+#define MDMA_CTCR_SINCOS_0        (0x1UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000100 */

+#define MDMA_CTCR_SINCOS_1        (0x2UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000200 */

+#define MDMA_CTCR_DINCOS_Pos      (10U)

+#define MDMA_CTCR_DINCOS_Msk      (0x3UL << MDMA_CTCR_DINCOS_Pos)              /*!< 0x00000C00 */

+#define MDMA_CTCR_DINCOS          MDMA_CTCR_DINCOS_Msk                         /*!< Destination increment offset size */

+#define MDMA_CTCR_DINCOS_0        (0x1UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000400 */

+#define MDMA_CTCR_DINCOS_1        (0x2UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000800 */

+#define MDMA_CTCR_SBURST_Pos      (12U)

+#define MDMA_CTCR_SBURST_Msk      (0x7UL << MDMA_CTCR_SBURST_Pos)              /*!< 0x00007000 */

+#define MDMA_CTCR_SBURST          MDMA_CTCR_SBURST_Msk                         /*!< Source burst transfer configuration */

+#define MDMA_CTCR_SBURST_0        (0x1UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00001000 */

+#define MDMA_CTCR_SBURST_1        (0x2UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00002000 */

+#define MDMA_CTCR_SBURST_2        (0x4UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00004000 */

+#define MDMA_CTCR_DBURST_Pos      (15U)

+#define MDMA_CTCR_DBURST_Msk      (0x7UL << MDMA_CTCR_DBURST_Pos)              /*!< 0x00038000 */

+#define MDMA_CTCR_DBURST          MDMA_CTCR_DBURST_Msk                         /*!< Destination burst transfer configuration */

+#define MDMA_CTCR_DBURST_0        (0x1UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00008000 */

+#define MDMA_CTCR_DBURST_1        (0x2UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00010000 */

+#define MDMA_CTCR_DBURST_2        (0x4UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00020000 */

+#define MDMA_CTCR_TLEN_Pos        (18U)

+#define MDMA_CTCR_TLEN_Msk        (0x7FUL << MDMA_CTCR_TLEN_Pos)               /*!< 0x01FC0000 */

+#define MDMA_CTCR_TLEN            MDMA_CTCR_TLEN_Msk                           /*!< buffer Transfer Length (number of bytes - 1) */

+#define MDMA_CTCR_PKE_Pos         (25U)

+#define MDMA_CTCR_PKE_Msk         (0x1UL << MDMA_CTCR_PKE_Pos)                 /*!< 0x02000000 */

+#define MDMA_CTCR_PKE             MDMA_CTCR_PKE_Msk                            /*!< PacK Enable */

+#define MDMA_CTCR_PAM_Pos         (26U)

+#define MDMA_CTCR_PAM_Msk         (0x3UL << MDMA_CTCR_PAM_Pos)                 /*!< 0x0C000000 */

+#define MDMA_CTCR_PAM             MDMA_CTCR_PAM_Msk                            /*!< Padding/Alignement Mode */

+#define MDMA_CTCR_PAM_0           (0x1UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x4000000 */

+#define MDMA_CTCR_PAM_1           (0x2UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x8000000 */

+#define MDMA_CTCR_TRGM_Pos        (28U)

+#define MDMA_CTCR_TRGM_Msk        (0x3UL << MDMA_CTCR_TRGM_Pos)                /*!< 0x30000000 */

+#define MDMA_CTCR_TRGM            MDMA_CTCR_TRGM_Msk                           /*!< Trigger Mode */

+#define MDMA_CTCR_TRGM_0          (0x1UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x10000000 */

+#define MDMA_CTCR_TRGM_1          (0x2UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x20000000 */

+#define MDMA_CTCR_SWRM_Pos        (30U)

+#define MDMA_CTCR_SWRM_Msk        (0x1UL << MDMA_CTCR_SWRM_Pos)                /*!< 0x40000000 */

+#define MDMA_CTCR_SWRM            MDMA_CTCR_SWRM_Msk                           /*!< SW Request Mode */

+#define MDMA_CTCR_BWM_Pos         (31U)

+#define MDMA_CTCR_BWM_Msk         (0x1UL << MDMA_CTCR_BWM_Pos)                 /*!< 0x80000000 */

+#define MDMA_CTCR_BWM             MDMA_CTCR_BWM_Msk                            /*!< Bufferable Write Mode */

+

+/********************  Bit definition for MDMA_CxBNDTR register  ****************/

+#define MDMA_CBNDTR_BNDT_Pos      (0U)

+#define MDMA_CBNDTR_BNDT_Msk      (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos)          /*!< 0x0001FFFF */

+#define MDMA_CBNDTR_BNDT          MDMA_CBNDTR_BNDT_Msk                         /*!< Block Number of data bytes to transfer */

+#define MDMA_CBNDTR_BRSUM_Pos     (18U)

+#define MDMA_CBNDTR_BRSUM_Msk     (0x1UL << MDMA_CBNDTR_BRSUM_Pos)             /*!< 0x00040000 */

+#define MDMA_CBNDTR_BRSUM         MDMA_CBNDTR_BRSUM_Msk                        /*!< Block Repeat Source address Update Mode */

+#define MDMA_CBNDTR_BRDUM_Pos     (19U)

+#define MDMA_CBNDTR_BRDUM_Msk     (0x1UL << MDMA_CBNDTR_BRDUM_Pos)             /*!< 0x00080000 */

+#define MDMA_CBNDTR_BRDUM         MDMA_CBNDTR_BRDUM_Msk                        /*!< Block Repeat Destination address Update Mode */

+#define MDMA_CBNDTR_BRC_Pos       (20U)

+#define MDMA_CBNDTR_BRC_Msk       (0xFFFUL << MDMA_CBNDTR_BRC_Pos)             /*!< 0xFFF00000 */

+#define MDMA_CBNDTR_BRC           MDMA_CBNDTR_BRC_Msk                          /*!< Block Repeat Count */

+

+/********************  Bit definition for MDMA_CxSAR register  ****************/

+#define MDMA_CSAR_SAR_Pos         (0U)

+#define MDMA_CSAR_SAR_Msk         (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CSAR_SAR             MDMA_CSAR_SAR_Msk                            /*!< Source address */

+

+/********************  Bit definition for MDMA_CxDAR register  ****************/

+#define MDMA_CDAR_DAR_Pos         (0U)

+#define MDMA_CDAR_DAR_Msk         (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CDAR_DAR             MDMA_CDAR_DAR_Msk                            /*!< Destination address */

+

+/********************  Bit definition for MDMA_CxBRUR  ************************/

+#define MDMA_CBRUR_SUV_Pos        (0U)

+#define MDMA_CBRUR_SUV_Msk        (0xFFFFUL << MDMA_CBRUR_SUV_Pos)             /*!< 0x0000FFFF */

+#define MDMA_CBRUR_SUV            MDMA_CBRUR_SUV_Msk                           /*!< Source address Update Value */

+#define MDMA_CBRUR_DUV_Pos        (16U)

+#define MDMA_CBRUR_DUV_Msk        (0xFFFFUL << MDMA_CBRUR_DUV_Pos)             /*!< 0xFFFF0000 */

+#define MDMA_CBRUR_DUV            MDMA_CBRUR_DUV_Msk                           /*!< Destination address Update Value */

+

+/********************  Bit definition for MDMA_CxLAR  *************************/

+#define MDMA_CLAR_LAR_Pos         (0U)

+#define MDMA_CLAR_LAR_Msk         (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CLAR_LAR             MDMA_CLAR_LAR_Msk                            /*!< Link Address Register */

+

+/********************  Bit definition for MDMA_CxTBR)  ************************/

+#define MDMA_CTBR_TSEL_Pos        (0U)

+#define MDMA_CTBR_TSEL_Msk        (0xFFUL << MDMA_CTBR_TSEL_Pos)               /*!< 0x000000FF */

+#define MDMA_CTBR_TSEL            MDMA_CTBR_TSEL_Msk                           /*!< Trigger SELection */

+#define MDMA_CTBR_SBUS_Pos        (16U)

+#define MDMA_CTBR_SBUS_Msk        (0x1UL << MDMA_CTBR_SBUS_Pos)                /*!< 0x00010000 */

+#define MDMA_CTBR_SBUS            MDMA_CTBR_SBUS_Msk                           /*!< Source BUS select */

+#define MDMA_CTBR_DBUS_Pos        (17U)

+#define MDMA_CTBR_DBUS_Msk        (0x1UL << MDMA_CTBR_DBUS_Pos)                /*!< 0x00020000 */

+#define MDMA_CTBR_DBUS            MDMA_CTBR_DBUS_Msk                           /*!< Destination BUS select */

+

+/********************  Bit definition for MDMA_CxMAR)  ************************/

+#define MDMA_CMAR_MAR_Pos         (0U)

+#define MDMA_CMAR_MAR_Msk         (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CMAR_MAR             MDMA_CMAR_MAR_Msk                            /*!< Mask address */

+

+/********************  Bit definition for MDMA_CxMDR)  ************************/

+#define MDMA_CMDR_MDR_Pos         (0U)

+#define MDMA_CMDR_MDR_Msk         (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CMDR_MDR             MDMA_CMDR_MDR_Msk                            /*!< Mask Data */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Operational Amplifier (OPAMP)                      */

+/*                                                                            */

+/******************************************************************************/

+/*********************  Bit definition for OPAMPx_CSR register  ***************/

+#define OPAMP_CSR_OPAMPxEN_Pos           (0U)

+#define OPAMP_CSR_OPAMPxEN_Msk           (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)     /*!< 0x00000001 */

+#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */

+#define OPAMP_CSR_FORCEVP_Pos            (1U)

+#define OPAMP_CSR_FORCEVP_Msk            (0x1UL << OPAMP_CSR_FORCEVP_Pos)      /*!< 0x00000002 */

+#define OPAMP_CSR_FORCEVP                OPAMP_CSR_FORCEVP_Msk                 /*!< Force internal reference on VP */

+

+#define OPAMP_CSR_VPSEL_Pos              (2U)

+#define OPAMP_CSR_VPSEL_Msk              (0x3UL << OPAMP_CSR_VPSEL_Pos)        /*!< 0x0000000C */

+#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */

+#define OPAMP_CSR_VPSEL_0                (0x1UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000004 */

+#define OPAMP_CSR_VPSEL_1                (0x2UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000008 */

+

+#define OPAMP_CSR_VMSEL_Pos              (5U)

+#define OPAMP_CSR_VMSEL_Msk              (0x3UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000060 */

+#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */

+#define OPAMP_CSR_VMSEL_0                (0x1UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000020 */

+#define OPAMP_CSR_VMSEL_1                (0x2UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000040 */

+

+#define OPAMP_CSR_OPAHSM_Pos             (8U)

+#define OPAMP_CSR_OPAHSM_Msk             (0x1UL << OPAMP_CSR_OPAHSM_Pos)       /*!< 0x00000100 */

+#define OPAMP_CSR_OPAHSM                 OPAMP_CSR_OPAHSM_Msk                  /*!< Operational amplifier high speed mode */

+#define OPAMP_CSR_CALON_Pos              (11U)

+#define OPAMP_CSR_CALON_Msk              (0x1UL << OPAMP_CSR_CALON_Pos)        /*!< 0x00000800 */

+#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */

+

+#define OPAMP_CSR_CALSEL_Pos             (12U)

+#define OPAMP_CSR_CALSEL_Msk             (0x3UL << OPAMP_CSR_CALSEL_Pos)       /*!< 0x00003000 */

+#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */

+#define OPAMP_CSR_CALSEL_0               (0x1UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00001000 */

+#define OPAMP_CSR_CALSEL_1               (0x2UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */

+

+#define OPAMP_CSR_PGGAIN_Pos             (14U)

+#define OPAMP_CSR_PGGAIN_Msk             (0xFUL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x0003C000 */

+#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */

+#define OPAMP_CSR_PGGAIN_0               (0x1UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00004000 */

+#define OPAMP_CSR_PGGAIN_1               (0x2UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00008000 */

+#define OPAMP_CSR_PGGAIN_2               (0x4UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00010000 */

+#define OPAMP_CSR_PGGAIN_3               (0x8UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00020000 */

+

+#define OPAMP_CSR_USERTRIM_Pos           (18U)

+#define OPAMP_CSR_USERTRIM_Msk           (0x1UL << OPAMP_CSR_USERTRIM_Pos)     /*!< 0x00040000 */

+#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */

+#define OPAMP_CSR_TSTREF_Pos             (29U)

+#define OPAMP_CSR_TSTREF_Msk             (0x1UL << OPAMP_CSR_TSTREF_Pos)       /*!< 0x20000000 */

+#define OPAMP_CSR_TSTREF                 OPAMP_CSR_TSTREF_Msk                  /*!< OpAmp calibration reference voltage output control */

+#define OPAMP_CSR_CALOUT_Pos             (30U)

+#define OPAMP_CSR_CALOUT_Msk             (0x1UL << OPAMP_CSR_CALOUT_Pos)       /*!< 0x40000000 */

+#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier calibration output */

+

+/*********************  Bit definition for OPAMP1_CSR register  ***************/

+#define OPAMP1_CSR_OPAEN_Pos              (0U)

+#define OPAMP1_CSR_OPAEN_Msk              (0x1UL << OPAMP1_CSR_OPAEN_Pos)      /*!< 0x00000001 */

+#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */

+#define OPAMP1_CSR_FORCEVP_Pos            (1U)

+#define OPAMP1_CSR_FORCEVP_Msk            (0x1UL << OPAMP1_CSR_FORCEVP_Pos)    /*!< 0x00000002 */

+#define OPAMP1_CSR_FORCEVP                OPAMP1_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */

+

+#define OPAMP1_CSR_VPSEL_Pos              (2U)

+#define OPAMP1_CSR_VPSEL_Msk              (0x3UL << OPAMP1_CSR_VPSEL_Pos)      /*!< 0x0000000C */

+#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */

+#define OPAMP1_CSR_VPSEL_0                (0x1UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000004 */

+#define OPAMP1_CSR_VPSEL_1                (0x2UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000008 */

+

+#define OPAMP1_CSR_VMSEL_Pos              (5U)

+#define OPAMP1_CSR_VMSEL_Msk              (0x3UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000060 */

+#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */

+#define OPAMP1_CSR_VMSEL_0                (0x1UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000020 */

+#define OPAMP1_CSR_VMSEL_1                (0x2UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000040 */

+

+#define OPAMP1_CSR_OPAHSM_Pos             (8U)

+#define OPAMP1_CSR_OPAHSM_Msk             (0x1UL << OPAMP1_CSR_OPAHSM_Pos)     /*!< 0x00000100 */

+#define OPAMP1_CSR_OPAHSM                 OPAMP1_CSR_OPAHSM_Msk                /*!< Operational amplifier1 high speed mode */

+#define OPAMP1_CSR_CALON_Pos              (11U)

+#define OPAMP1_CSR_CALON_Msk              (0x1UL << OPAMP1_CSR_CALON_Pos)      /*!< 0x00000800 */

+#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */

+

+#define OPAMP1_CSR_CALSEL_Pos             (12U)

+#define OPAMP1_CSR_CALSEL_Msk             (0x3UL << OPAMP1_CSR_CALSEL_Pos)     /*!< 0x00003000 */

+#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */

+#define OPAMP1_CSR_CALSEL_0               (0x1UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00001000 */

+#define OPAMP1_CSR_CALSEL_1               (0x2UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */

+

+#define OPAMP1_CSR_PGGAIN_Pos             (14U)

+#define OPAMP1_CSR_PGGAIN_Msk             (0xFUL << OPAMP1_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */

+#define OPAMP1_CSR_PGGAIN                 OPAMP1_CSR_PGGAIN_Msk                /*!< Operational amplifier1 Programmable amplifier gain value */

+#define OPAMP1_CSR_PGGAIN_0               (0x1UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00004000 */

+#define OPAMP1_CSR_PGGAIN_1               (0x2UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00008000 */

+#define OPAMP1_CSR_PGGAIN_2               (0x4UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00010000 */

+#define OPAMP1_CSR_PGGAIN_3               (0x8UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00020000 */

+

+#define OPAMP1_CSR_USERTRIM_Pos           (18U)

+#define OPAMP1_CSR_USERTRIM_Msk           (0x1UL << OPAMP1_CSR_USERTRIM_Pos)   /*!< 0x00040000 */

+#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */

+#define OPAMP1_CSR_TSTREF_Pos             (29U)

+#define OPAMP1_CSR_TSTREF_Msk             (0x1UL << OPAMP1_CSR_TSTREF_Pos)     /*!< 0x20000000 */

+#define OPAMP1_CSR_TSTREF                 OPAMP1_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */

+#define OPAMP1_CSR_CALOUT_Pos             (30U)

+#define OPAMP1_CSR_CALOUT_Msk             (0x1UL << OPAMP1_CSR_CALOUT_Pos)     /*!< 0x40000000 */

+#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */

+

+/*********************  Bit definition for OPAMP2_CSR register  ***************/

+#define OPAMP2_CSR_OPAEN_Pos              (0U)

+#define OPAMP2_CSR_OPAEN_Msk              (0x1UL << OPAMP2_CSR_OPAEN_Pos)      /*!< 0x00000001 */

+#define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */

+#define OPAMP2_CSR_FORCEVP_Pos            (1U)

+#define OPAMP2_CSR_FORCEVP_Msk            (0x1UL << OPAMP2_CSR_FORCEVP_Pos)    /*!< 0x00000002 */

+#define OPAMP2_CSR_FORCEVP                OPAMP2_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */

+

+#define OPAMP2_CSR_VPSEL_Pos              (2U)

+#define OPAMP2_CSR_VPSEL_Msk              (0x3UL << OPAMP2_CSR_VPSEL_Pos)      /*!< 0x0000000C */

+#define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */

+#define OPAMP2_CSR_VPSEL_0                (0x1UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000004 */

+#define OPAMP2_CSR_VPSEL_1                (0x2UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000008 */

+

+#define OPAMP2_CSR_VMSEL_Pos              (5U)

+#define OPAMP2_CSR_VMSEL_Msk              (0x3UL << OPAMP2_CSR_VMSEL_Pos)      /*!< 0x00000060 */

+#define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */

+#define OPAMP2_CSR_VMSEL_0                (0x1UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000020 */

+#define OPAMP2_CSR_VMSEL_1                (0x2UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000040 */

+

+#define OPAMP2_CSR_OPAHSM_Pos             (8U)

+#define OPAMP2_CSR_OPAHSM_Msk             (0x1UL << OPAMP2_CSR_OPAHSM_Pos)     /*!< 0x00000100 */

+#define OPAMP2_CSR_OPAHSM                 OPAMP2_CSR_OPAHSM_Msk                /*!< Operational amplifier2 high speed mode */

+#define OPAMP2_CSR_CALON_Pos              (11U)

+#define OPAMP2_CSR_CALON_Msk              (0x1UL << OPAMP2_CSR_CALON_Pos)      /*!< 0x00000800 */

+#define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */

+

+#define OPAMP2_CSR_CALSEL_Pos             (12U)

+#define OPAMP2_CSR_CALSEL_Msk             (0x3UL << OPAMP2_CSR_CALSEL_Pos)     /*!< 0x00003000 */

+#define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */

+#define OPAMP2_CSR_CALSEL_0               (0x1UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00001000 */

+#define OPAMP2_CSR_CALSEL_1               (0x2UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */

+

+#define OPAMP2_CSR_PGGAIN_Pos             (14U)

+#define OPAMP2_CSR_PGGAIN_Msk             (0xFUL << OPAMP2_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */

+#define OPAMP2_CSR_PGGAIN                 OPAMP2_CSR_PGGAIN_Msk                /*!< Operational amplifier2 Programmable amplifier gain value */

+#define OPAMP2_CSR_PGGAIN_0               (0x1UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00004000 */

+#define OPAMP2_CSR_PGGAIN_1               (0x2UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00008000 */

+#define OPAMP2_CSR_PGGAIN_2               (0x4UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00010000 */

+#define OPAMP2_CSR_PGGAIN_3               (0x8UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00020000 */

+

+#define OPAMP2_CSR_USERTRIM_Pos           (18U)

+#define OPAMP2_CSR_USERTRIM_Msk           (0x1UL << OPAMP2_CSR_USERTRIM_Pos)   /*!< 0x00040000 */

+#define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */

+#define OPAMP2_CSR_TSTREF_Pos             (29U)

+#define OPAMP2_CSR_TSTREF_Msk             (0x1UL << OPAMP2_CSR_TSTREF_Pos)     /*!< 0x20000000 */

+#define OPAMP2_CSR_TSTREF                 OPAMP2_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */

+#define OPAMP2_CSR_CALOUT_Pos             (30U)

+#define OPAMP2_CSR_CALOUT_Msk             (0x1UL << OPAMP2_CSR_CALOUT_Pos)     /*!< 0x40000000 */

+#define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */

+

+/*******************  Bit definition for OPAMP_OTR register  ******************/

+#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */

+#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP1_OTR register  ******************/

+#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */

+#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP2_OTR register  ******************/

+#define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */

+#define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP_HSOTR register  ****************/

+#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP_HSOTR_TRIMHSOFFSETN        OPAMP_HSOTR_TRIMHSOFFSETN_Msk         /*!< Trim for NMOS differential pairs */

+#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP_HSOTR_TRIMHSOFFSETP        OPAMP_HSOTR_TRIMHSOFFSETP_Msk         /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP1_HSOTR register  ****************/

+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP1_HSOTR_TRIMHSOFFSETN        OPAMP1_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */

+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP1_HSOTR_TRIMHSOFFSETP        OPAMP1_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP2_HSOTR register  ****************/

+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP2_HSOTR_TRIMHSOFFSETN        OPAMP2_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */

+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP2_HSOTR_TRIMHSOFFSETP        OPAMP2_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */

+

+/******************************************************************************/

+/*                                                                            */

+/*                Parallel Synchronous Slave Interface (PSSI )                */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for PSSI_CR register  *******************/

+#define PSSI_CR_OUTEN_Pos               (31U)

+#define PSSI_CR_OUTEN_Msk               (0x1UL << PSSI_CR_OUTEN_Pos)           /*!< 0x80000000 */

+#define PSSI_CR_OUTEN                   PSSI_CR_OUTEN_Msk                      /*!< Data direction selection */

+#define PSSI_CR_DMAEN_Pos               (30U)

+#define PSSI_CR_DMAEN_Msk               (0x1UL << PSSI_CR_DMAEN_Pos)           /*!< 0x40000000 */

+#define PSSI_CR_DMAEN                   PSSI_CR_DMAEN_Msk                      /*!< DMA enable */

+#define PSSI_CR_DERDYCFG_Pos            (18U)

+#define PSSI_CR_DERDYCFG_Msk            (0x7UL << PSSI_CR_DERDYCFG_Pos)        /*!< 0x001C0000 */

+#define PSSI_CR_DERDYCFG                PSSI_CR_DERDYCFG_Msk                   /*!< Data enable and ready configuration */

+#define PSSI_CR_ENABLE_Pos              (14U)

+#define PSSI_CR_ENABLE_Msk              (0x1UL << PSSI_CR_ENABLE_Pos)          /*!< 0x00004000 */

+#define PSSI_CR_ENABLE                  PSSI_CR_ENABLE_Msk                     /*!< PSSI enable */

+#define PSSI_CR_EDM_Pos                 (10U)

+#define PSSI_CR_EDM_Msk                 (0x3UL << PSSI_CR_EDM_Pos)             /*!< 0x00000C00 */

+#define PSSI_CR_EDM                     PSSI_CR_EDM_Msk                        /*!< Extended data mode */

+#define PSSI_CR_RDYPOL_Pos              (8U)

+#define PSSI_CR_RDYPOL_Msk              (0x1UL << PSSI_CR_RDYPOL_Pos)          /*!< 0x00000C00 */

+#define PSSI_CR_RDYPOL                  PSSI_CR_RDYPOL_Msk                     /*!< Ready polarity */

+#define PSSI_CR_DEPOL_Pos               (6U)

+#define PSSI_CR_DEPOL_Msk               (0x1UL << PSSI_CR_DEPOL_Pos)           /*!< 0x00000C00 */

+#define PSSI_CR_DEPOL                   PSSI_CR_DEPOL_Msk                      /*!<  Data enable polarity */

+#define PSSI_CR_CKPOL_Pos               (5U)

+#define PSSI_CR_CKPOL_Msk               (0x1UL << PSSI_CR_CKPOL_Pos)           /*!< 0x00000C00 */

+#define PSSI_CR_CKPOL                   PSSI_CR_CKPOL_Msk                      /*!< Parallel data clock polarity */

+/********************  Bit definition for PSSI_SR register  *******************/

+#define PSSI_SR_RTT1B_Pos               (3U)

+#define PSSI_SR_RTT1B_Msk               (0x1UL << PSSI_SR_RTT1B_Pos)           /*!< 0x00000008 */

+#define PSSI_SR_RTT1B                   PSSI_SR_RTT1B_Msk                      /*!< Ready to transfer one byte */

+#define PSSI_SR_RTT4B_Pos               (2U)

+#define PSSI_SR_RTT4B_Msk               (0x1UL << PSSI_SR_RTT4B_Pos)           /*!< 0x00000004 */

+#define PSSI_SR_RTT4B                   PSSI_SR_RTT4B_Msk                      /*!< Ready to transfer four bytes */

+/********************  Bit definition for PSSI_RIS register  *******************/

+#define PSSI_RIS_OVR_RIS_Pos            (1U)

+#define PSSI_RIS_OVR_RIS_Msk            (0x1UL << PSSI_RIS_OVR_RIS_Pos)        /*!< 0x00000002 */

+#define PSSI_RIS_OVR_RIS                PSSI_RIS_OVR_RIS_Msk                   /*!< Data buffer overrun/underrun raw interrupt status */

+/********************  Bit definition for PSSI_IER register  *******************/

+#define PSSI_IER_OVR_IE_Pos             (1U)

+#define PSSI_IER_OVR_IE_Msk             (0x1UL << PSSI_IER_OVR_IE_Pos)         /*!< 0x00000002 */

+#define PSSI_IER_OVR_IE                 PSSI_IER_OVR_IE_Msk                    /*!< Data buffer overrun/underrun interrupt enable */

+/********************  Bit definition for PSSI_MIS register  *******************/

+#define PSSI_MIS_OVR_MIS_Pos            (1U)

+#define PSSI_MIS_OVR_MIS_Msk            (0x1UL << PSSI_MIS_OVR_MIS_Pos)        /*!< 0x00000002 */

+#define PSSI_MIS_OVR_MIS                PSSI_MIS_OVR_MIS_Msk                   /*!< Data buffer overrun/underrun masked interrupt status */

+/********************  Bit definition for PSSI_ICR register  *******************/

+#define PSSI_ICR_OVR_ISC_Pos            (1U)

+#define PSSI_ICR_OVR_ISC_Msk            (0x1UL << PSSI_ICR_OVR_ISC_Pos)        /*!< 0x00000002 */

+#define PSSI_ICR_OVR_ISC                PSSI_ICR_OVR_ISC_Msk                   /*!< Data buffer overrun/underrun interrupt status clear */

+/********************  Bit definition for PSSI_DR register  *******************/

+#define PSSI_DR_DR_Pos                  (0U)

+#define PSSI_DR_DR_Msk                  (0xFFFFFFFFUL << PSSI_DR_DR_Pos)       /*!< 0xFFFFFFF */

+#define PSSI_DR_DR                      PSSI_DR_DR_Msk                         /*!< Data register  */

+

+/******************************************************************************/

+/*                                                                            */

+/*                              On The Fly Decryption                         */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for OTFDEC_CR register  ******************/

+#define OTFDEC_CR_ENC_Pos                      (0U)

+#define OTFDEC_CR_ENC_Msk                      (0x1UL << OTFDEC_CR_ENC_Pos)                  /*!< 0x00000001 */

+#define OTFDEC_CR_ENC                          OTFDEC_CR_ENC_Msk                             /*!< Encryption mode bit */

+

+/******************  Bit definition for OTFDEC_PRIVCFGR register  ************/

+#define OTFDEC_PRIVCFGR_PRIV_Pos               (0U)

+#define OTFDEC_PRIVCFGR_PRIV_Msk               (0x1UL << OTFDEC_PRIVCFGR_PRIV_Pos)           /*!< 0x00000001 */

+#define OTFDEC_PRIVCFGR_PRIV                   OTFDEC_PRIVCFGR_PRIV_Msk                      /*!< Privileged access protection */

+

+/******************  Bit definition for OTFDEC_REG_CONFIGR register  *********/

+#define OTFDEC_REG_CONFIGR_REG_EN_Pos          (0U)

+#define OTFDEC_REG_CONFIGR_REG_EN_Msk          (0x1UL << OTFDEC_REG_CONFIGR_REG_EN_Pos)      /*!< 0x00000001 */

+#define OTFDEC_REG_CONFIGR_REG_EN              OTFDEC_REG_CONFIGR_REG_EN_Msk                 /*!< Region on-the-fly decryption enable */

+

+#define OTFDEC_REG_CONFIGR_CONFIGLOCK_Pos      (1U)

+#define OTFDEC_REG_CONFIGR_CONFIGLOCK_Msk      (0x1UL << OTFDEC_REG_CONFIGR_CONFIGLOCK_Pos)  /*!< 0x00000002 */

+#define OTFDEC_REG_CONFIGR_CONFIGLOCK          OTFDEC_REG_CONFIGR_CONFIGLOCK_Msk             /*!< Region config lock */

+

+#define OTFDEC_REG_CONFIGR_KEYLOCK_Pos         (2U)

+#define OTFDEC_REG_CONFIGR_KEYLOCK_Msk         (0x1UL << OTFDEC_REG_CONFIGR_KEYLOCK_Pos)     /*!< 0x00000004 */

+#define OTFDEC_REG_CONFIGR_KEYLOCK             OTFDEC_REG_CONFIGR_KEYLOCK_Msk                /*!< Region key lock */

+

+#define OTFDEC_REG_CONFIGR_MODE_Pos            (4U)

+#define OTFDEC_REG_CONFIGR_MODE_Msk            (0x3UL << OTFDEC_REG_CONFIGR_MODE_Pos)        /*!< 0x00000030 */

+#define OTFDEC_REG_CONFIGR_MODE                OTFDEC_REG_CONFIGR_MODE_Msk                   /*!< Region operating mode */

+#define OTFDEC_REG_CONFIGR_MODE_0              (0x1UL << OTFDEC_REG_CONFIGR_MODE_Pos)        /*!< 0x00000010 */

+#define OTFDEC_REG_CONFIGR_MODE_1              (0x2UL << OTFDEC_REG_CONFIGR_MODE_Pos)        /*!< 0x00000020 */

+

+#define OTFDEC_REG_CONFIGR_KEYCRC_Pos          (8U)

+#define OTFDEC_REG_CONFIGR_KEYCRC_Msk          (0xFFUL << OTFDEC_REG_CONFIGR_KEYCRC_Pos)     /*!< 0x0000FF00 */

+#define OTFDEC_REG_CONFIGR_KEYCRC              OTFDEC_REG_CONFIGR_KEYCRC_Msk                 /*!< Region key 8-bit CRC */

+

+#define OTFDEC_REG_CONFIGR_VERSION_Pos         (16U)

+#define OTFDEC_REG_CONFIGR_VERSION_Msk         (0xFFFFUL << OTFDEC_REG_CONFIGR_VERSION_Pos)  /*!< 0xFFFF0000 */

+#define OTFDEC_REG_CONFIGR_VERSION             OTFDEC_REG_CONFIGR_VERSION_Msk                /*!< Region firmware version */

+

+/******************  Bit definition for OTFDEC_REG_START_ADDR register  ******/

+#define OTFDEC_REG_START_ADDR_Pos              (0U)

+#define OTFDEC_REG_START_ADDR_Msk              (0xFFFFFFFFUL << OTFDEC_REG_START_ADDR_Pos)   /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_START_ADDR                  OTFDEC_REG_START_ADDR_Msk                     /*!< Region AHB start address */

+

+/******************  Bit definition for OTFDEC_REG_END_ADDR register  ********/

+#define OTFDEC_REG_END_ADDR_Pos                (0U)

+#define OTFDEC_REG_END_ADDR_Msk                (0xFFFFFFFFUL << OTFDEC_REG_END_ADDR_Pos)     /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_END_ADDR                    OTFDEC_REG_END_ADDR_Msk                       /*!< Region AHB end address */

+

+/******************  Bit definition for OTFDEC_REG_NONCER0 register  *********/

+#define OTFDEC_REG_NONCER0_Pos                 (0U)

+#define OTFDEC_REG_NONCER0_Msk                 (0xFFFFFFFFUL << OTFDEC_REG_NONCER0_Pos)      /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_NONCER0                     OTFDEC_REG_NONCER0_Msk                        /*!< Region Nonce Register (LSB nonce[31:0]) */

+

+/******************  Bit definition for OTFDEC_REG_NONCER1 register  *********/

+#define OTFDEC_REG_NONCER1_Pos                 (0U)

+#define OTFDEC_REG_NONCER1_Msk                 (0xFFFFFFFFUL << OTFDEC_REG_NONCER1_Pos)      /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_NONCER1                     OTFDEC_REG_NONCER1_Msk                        /*!< Region Nonce Register (MSB nonce[63:32]) */

+

+/******************  Bit definition for OTFDEC_REG_KEYR0 register  ***********/

+#define OTFDEC_REG_KEYR0_Pos                   (0U)

+#define OTFDEC_REG_KEYR0_Msk                   (0xFFFFFFFFUL << OTFDEC_REG_KEYR0_Pos)        /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_KEYR0                       OTFDEC_REG_KEYR0_Msk                          /*!< Region Key Register (LSB key[31:0]) */

+

+/******************  Bit definition for OTFDEC_REG_KEYR1 register  ***********/

+#define OTFDEC_REG_KEYR1_Pos                   (0U)

+#define OTFDEC_REG_KEYR1_Msk                   (0xFFFFFFFFUL << OTFDEC_REG_KEYR1_Pos)        /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_KEYR1                       OTFDEC_REG_KEYR1_Msk                          /*!< Region Key Register (key[63:32]) */

+

+/******************  Bit definition for OTFDEC_REG_KEYR2 register  ***********/

+#define OTFDEC_REG_KEYR2_Pos                   (0U)

+#define OTFDEC_REG_KEYR2_Msk                   (0xFFFFFFFFUL << OTFDEC_REG_KEYR2_Pos)        /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_KEYR2                       OTFDEC_REG_KEYR2_Msk                          /*!< Region Key Register (key[95:64]) */

+

+/******************  Bit definition for OTFDEC_REG_KEYR3 register  ***********/

+#define OTFDEC_REG_KEYR3_Pos                   (0U)

+#define OTFDEC_REG_KEYR3_Msk                   (0xFFFFFFFFUL << OTFDEC_REG_KEYR3_Pos)        /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_KEYR3                       OTFDEC_REG_KEYR3_Msk                          /*!< Region Key Register (key[127:96]) */

+

+/******************  Bit definition for OTFDEC_ISR register  *****************/

+#define OTFDEC_ISR_SEIF_Pos                    (0U)

+#define OTFDEC_ISR_SEIF_Msk                    (0x1UL << OTFDEC_ISR_SEIF_Pos)                /*!< 0x00000001 */

+#define OTFDEC_ISR_SEIF                        OTFDEC_ISR_SEIF_Msk                           /*!< Security Error Interrupt Flag status bit before enable (mask) */

+

+#define OTFDEC_ISR_XONEIF_Pos                  (1U)

+#define OTFDEC_ISR_XONEIF_Msk                  (0x1UL << OTFDEC_ISR_XONEIF_Pos)              /*!< 0x00000002 */

+#define OTFDEC_ISR_XONEIF                      OTFDEC_ISR_XONEIF_Msk                         /*!< Execute-only Error Interrupt Flag status bit before enable (mask) */

+

+#define OTFDEC_ISR_KEIF_Pos                    (2U)

+#define OTFDEC_ISR_KEIF_Msk                    (0x1UL << OTFDEC_ISR_KEIF_Pos)                /*!< 0x00000004 */

+#define OTFDEC_ISR_KEIF                        OTFDEC_ISR_KEIF_Msk                           /*!< Key Error Interrupt Flag status bit before enable (mask) */

+

+/******************  Bit definition  for OTFDEC_ICR register  *****************/

+#define OTFDEC_ICR_SEIF_Pos                    (0U)

+#define OTFDEC_ICR_SEIF_Msk                    (0x1UL << OTFDEC_ICR_SEIF_Pos)                /*!< 0x00000001 */

+#define OTFDEC_ICR_SEIF                        OTFDEC_ICR_SEIF_Msk                           /*!< Security Error Interrupt Flag clear bit */

+

+#define OTFDEC_ICR_XONEIF_Pos                  (1U)

+#define OTFDEC_ICR_XONEIF_Msk                  (0x1UL << OTFDEC_ICR_XONEIF_Pos)              /*!< 0x00000002 */

+#define OTFDEC_ICR_XONEIF                      OTFDEC_ICR_XONEIF_Msk                         /*!< Execute-only Error Interrupt Flag clear bit */

+

+#define OTFDEC_ICR_KEIF_Pos                    (2U)

+#define OTFDEC_ICR_KEIF_Msk                    (0x1UL << OTFDEC_ICR_KEIF_Pos)                /*!< 0x00000004 */

+#define OTFDEC_ICR_KEIF                        OTFDEC_ICR_KEIF_Msk                           /*!< Key Error Interrupt Flag clear bit */

+

+/******************  Bit definition for OTFDEC_IER register  *****************/

+#define OTFDEC_IER_SEIE_Pos                    (0U)

+#define OTFDEC_IER_SEIE_Msk                    (0x1UL << OTFDEC_IER_SEIE_Pos)                /*!< 0x00000001 */

+#define OTFDEC_IER_SEIE                        OTFDEC_IER_SEIE_Msk                           /*!< Security Error Interrupt Enable bit */

+

+#define OTFDEC_IER_XONEIE_Pos                  (1U)

+#define OTFDEC_IER_XONEIE_Msk                  (0x1UL << OTFDEC_IER_XONEIE_Pos)              /*!< 0x00000002 */

+#define OTFDEC_IER_XONEIE                      OTFDEC_IER_XONEIE_Msk                         /*!< Execute-only Error Interrupt Enable bit */

+

+#define OTFDEC_IER_KEIE_Pos                    (2U)

+#define OTFDEC_IER_KEIE_Msk                    (0x1UL << OTFDEC_IER_KEIE_Pos)                /*!< 0x00000004 */

+#define OTFDEC_IER_KEIE                        OTFDEC_IER_KEIE_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                             Power Control                                  */

+/*                                                                            */

+/******************************************************************************/

+/*************************  NUMBER OF POWER DOMAINS  **************************/

+#define POWER_DOMAINS_NUMBER           2U                                      /*!< 2 Domains */

+

+/********************  Bit definition for PWR_CR1 register  *******************/

+#define PWR_CR1_SRDRAMSO_Pos           (27U)

+#define PWR_CR1_SRDRAMSO_Msk           (0x1UL << PWR_CR1_SRDRAMSO_Pos)         /*!< 0x08000000 */

+#define PWR_CR1_SRDRAMSO               PWR_CR1_SRDRAMSO_Msk                    /*!< SmartRun Domain AHB Memory Shut-Off in DStop/DStop2 Low-Power Mode */

+#define PWR_CR1_HSITFSO_Pos            (26U)

+#define PWR_CR1_HSITFSO_Msk            (0x1UL << PWR_CR1_HSITFSO_Pos)          /*!< 0x04000000 */

+#define PWR_CR1_HSITFSO                PWR_CR1_HSITFSO_Msk                     /*!< High-Speed Interfaces USB and FDCAN Memories Shut-off in DStop/DStop2 Mode */

+#define PWR_CR1_GFXSO_Pos              (25U)

+#define PWR_CR1_GFXSO_Msk              (0x1UL << PWR_CR1_GFXSO_Pos)            /*!< 0x02000000 */

+#define PWR_CR1_GFXSO                  PWR_CR1_GFXSO_Msk                       /*!< GFXMMU and JPEG Memories Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_ITCMSO_Pos             (24U)

+#define PWR_CR1_ITCMSO_Msk             (0x1UL << PWR_CR1_ITCMSO_Pos)           /*!< 0x01000000 */

+#define PWR_CR1_ITCMSO                 PWR_CR1_ITCMSO_Msk                      /*!< Instruction TCM and ETM Memories Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_AHBRAM2SO_Pos          (23U)

+#define PWR_CR1_AHBRAM2SO_Msk          (0x1UL << PWR_CR1_AHBRAM2SO_Pos)        /*!< 0x00800000 */

+#define PWR_CR1_AHBRAM2SO              PWR_CR1_AHBRAM2SO_Msk                   /*!< AHB RAM2 Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_AHBRAM1SO_Pos          (22U)

+#define PWR_CR1_AHBRAM1SO_Msk          (0x1UL << PWR_CR1_AHBRAM1SO_Pos)        /*!< 0x00400000 */

+#define PWR_CR1_AHBRAM1SO              PWR_CR1_AHBRAM1SO_Msk                   /*!< AHB RAM1 Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_AXIRAM3SO_Pos          (21U)

+#define PWR_CR1_AXIRAM3SO_Msk          (0x1UL << PWR_CR1_AXIRAM3SO_Pos)        /*!< 0x00200000 */

+#define PWR_CR1_AXIRAM3SO              PWR_CR1_AXIRAM3SO_Msk                   /*!< AXI RAM3 Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_AXIRAM2SO_Pos          (20U)

+#define PWR_CR1_AXIRAM2SO_Msk          (0x1UL << PWR_CR1_AXIRAM2SO_Pos)        /*!< 0x00100000 */

+#define PWR_CR1_AXIRAM2SO              PWR_CR1_AXIRAM2SO_Msk                   /*!< AXI RAM2 Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_AXIRAM1SO_Pos          (19U)

+#define PWR_CR1_AXIRAM1SO_Msk          (0x1UL << PWR_CR1_AXIRAM1SO_Pos)        /*!< 0x00080000 */

+#define PWR_CR1_AXIRAM1SO              PWR_CR1_AXIRAM1SO_Msk                   /*!< AXI RAM1 Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_ALS_Pos                (17U)

+#define PWR_CR1_ALS_Msk                (0x3UL << PWR_CR1_ALS_Pos)              /*!< 0x00060000 */

+#define PWR_CR1_ALS                    PWR_CR1_ALS_Msk                         /*!< Analog Voltage Detector level selection */

+#define PWR_CR1_ALS_0                  (0x1UL << PWR_CR1_ALS_Pos)              /*!< 0x00020000 */

+#define PWR_CR1_ALS_1                  (0x2UL << PWR_CR1_ALS_Pos)              /*!< 0x00040000 */

+#define PWR_CR1_AVDEN_Pos              (16U)

+#define PWR_CR1_AVDEN_Msk              (0x1UL << PWR_CR1_AVDEN_Pos)            /*!< 0x00010000 */

+#define PWR_CR1_AVDEN                  PWR_CR1_AVDEN_Msk                       /*!< Analog Voltage Detector Enable */

+#define PWR_CR1_SVOS_Pos               (14U)

+#define PWR_CR1_SVOS_Msk               (0x3UL << PWR_CR1_SVOS_Pos)             /*!< 0x0000C000 */

+#define PWR_CR1_SVOS                   PWR_CR1_SVOS_Msk                        /*!< System STOP mode Voltage Scaling selection */

+#define PWR_CR1_SVOS_0                 (0x1UL << PWR_CR1_SVOS_Pos)             /*!< 0x00004000 */

+#define PWR_CR1_SVOS_1                 (0x2UL << PWR_CR1_SVOS_Pos)             /*!< 0x00008000 */

+#define PWR_CR1_AVD_READY_Pos          (13U)

+#define PWR_CR1_AVD_READY_Msk          (0x1UL << PWR_CR1_AVD_READY_Pos)        /*!< 0x00002000 */

+#define PWR_CR1_AVD_READY              PWR_CR1_AVD_READY_Msk                   /*!< Analog Voltage Ready. */

+#define PWR_CR1_BOOSTE_Pos             (12U)

+#define PWR_CR1_BOOSTE_Msk             (0x1UL << PWR_CR1_BOOSTE_Pos)           /*!< 0x00001000 */

+#define PWR_CR1_BOOSTE                 PWR_CR1_BOOSTE_Msk                      /*!< Analog Switch VBoost control */

+#define PWR_CR1_FLPS_Pos               (9U)

+#define PWR_CR1_FLPS_Msk               (0x1UL << PWR_CR1_FLPS_Pos)             /*!< 0x00000200 */

+#define PWR_CR1_FLPS                   PWR_CR1_FLPS_Msk                        /*!< Flash low power mode in DSTOP */

+#define PWR_CR1_DBP_Pos                (8U)

+#define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */

+#define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable Back-up domain Protection */

+#define PWR_CR1_PLS_Pos                (5U)

+#define PWR_CR1_PLS_Msk                (0x7UL << PWR_CR1_PLS_Pos)              /*!< 0x000000E0 */

+#define PWR_CR1_PLS                    PWR_CR1_PLS_Msk                         /*!< Programmable Voltage Detector level selection */

+#define PWR_CR1_PLS_0                  (0x1UL << PWR_CR1_PLS_Pos)              /*!< 0x00000020 */

+#define PWR_CR1_PLS_1                  (0x2UL << PWR_CR1_PLS_Pos)              /*!< 0x00000040 */

+#define PWR_CR1_PLS_2                  (0x4UL << PWR_CR1_PLS_Pos)              /*!< 0x00000080 */

+#define PWR_CR1_PVDEN_Pos              (4U)

+#define PWR_CR1_PVDEN_Msk              (0x1UL << PWR_CR1_PVDEN_Pos)            /*!< 0x00000010 */

+#define PWR_CR1_PVDEN                  PWR_CR1_PVDEN_Msk                       /*!< Programmable Voltage detector enable */

+#define PWR_CR1_LPDS_Pos               (0U)

+#define PWR_CR1_LPDS_Msk               (0x1UL << PWR_CR1_LPDS_Pos)             /*!< 0x00000001 */

+#define PWR_CR1_LPDS                   PWR_CR1_LPDS_Msk                        /*!< Low Power Deepsleep with SVOS3 */

+

+/*!< PVD level configuration */

+#define PWR_CR1_PLS_LEV0               (0UL)                                   /*!< PVD level 0 */

+#define PWR_CR1_PLS_LEV1_Pos           (5U)

+#define PWR_CR1_PLS_LEV1_Msk           (0x1UL << PWR_CR1_PLS_LEV1_Pos)         /*!< 0x00000020 */

+#define PWR_CR1_PLS_LEV1               PWR_CR1_PLS_LEV1_Msk                    /*!< PVD level 1 */

+#define PWR_CR1_PLS_LEV2_Pos           (6U)

+#define PWR_CR1_PLS_LEV2_Msk           (0x1UL << PWR_CR1_PLS_LEV2_Pos)         /*!< 0x00000040 */

+#define PWR_CR1_PLS_LEV2               PWR_CR1_PLS_LEV2_Msk                    /*!< PVD level 2 */

+#define PWR_CR1_PLS_LEV3_Pos           (5U)

+#define PWR_CR1_PLS_LEV3_Msk           (0x3UL << PWR_CR1_PLS_LEV3_Pos)         /*!< 0x00000060 */

+#define PWR_CR1_PLS_LEV3               PWR_CR1_PLS_LEV3_Msk                    /*!< PVD level 3 */

+#define PWR_CR1_PLS_LEV4_Pos           (7U)

+#define PWR_CR1_PLS_LEV4_Msk           (0x1UL << PWR_CR1_PLS_LEV4_Pos)         /*!< 0x00000080 */

+#define PWR_CR1_PLS_LEV4               PWR_CR1_PLS_LEV4_Msk                    /*!< PVD level 4 */

+#define PWR_CR1_PLS_LEV5_Pos           (5U)

+#define PWR_CR1_PLS_LEV5_Msk           (0x5UL << PWR_CR1_PLS_LEV5_Pos)         /*!< 0x000000A0 */

+#define PWR_CR1_PLS_LEV5               PWR_CR1_PLS_LEV5_Msk                    /*!< PVD level 5 */

+#define PWR_CR1_PLS_LEV6_Pos           (6U)

+#define PWR_CR1_PLS_LEV6_Msk           (0x3UL << PWR_CR1_PLS_LEV6_Pos)         /*!< 0x000000C0 */

+#define PWR_CR1_PLS_LEV6               PWR_CR1_PLS_LEV6_Msk                    /*!< PVD level 6 */

+#define PWR_CR1_PLS_LEV7_Pos           (5U)

+#define PWR_CR1_PLS_LEV7_Msk           (0x7UL << PWR_CR1_PLS_LEV7_Pos)         /*!< 0x000000E0 */

+#define PWR_CR1_PLS_LEV7               PWR_CR1_PLS_LEV7_Msk                    /*!< PVD level 7 */

+

+/*!< AVD level configuration */

+#define PWR_CR1_ALS_LEV0               (0UL)                                   /*!< AVD level 0 */

+#define PWR_CR1_ALS_LEV1_Pos           (17U)

+#define PWR_CR1_ALS_LEV1_Msk           (0x1UL << PWR_CR1_ALS_LEV1_Pos)         /*!< 0x00020000 */

+#define PWR_CR1_ALS_LEV1               PWR_CR1_ALS_LEV1_Msk                    /*!< AVD level 1 */

+#define PWR_CR1_ALS_LEV2_Pos           (18U)

+#define PWR_CR1_ALS_LEV2_Msk           (0x1UL << PWR_CR1_ALS_LEV2_Pos)         /*!< 0x00040000 */

+#define PWR_CR1_ALS_LEV2               PWR_CR1_ALS_LEV2_Msk                    /*!< AVD level 2 */

+#define PWR_CR1_ALS_LEV3_Pos           (17U)

+#define PWR_CR1_ALS_LEV3_Msk           (0x3UL << PWR_CR1_ALS_LEV3_Pos)         /*!< 0x00060000 */

+#define PWR_CR1_ALS_LEV3               PWR_CR1_ALS_LEV3_Msk                    /*!< AVD level 3 */

+

+/********************  Bit definition for PWR_CSR1 register  ******************/

+#define PWR_CSR1_MMCVDO_Pos            (17U)

+#define PWR_CSR1_MMCVDO_Msk            (0x1UL << PWR_CSR1_MMCVDO_Pos)          /*!< 0x00020000                        */

+#define PWR_CSR1_MMCVDO                PWR_CSR1_MMCVDO_Msk                     /*!< voltage detector output on VDDMMC */

+#define PWR_CSR1_AVDO_Pos              (16U)

+#define PWR_CSR1_AVDO_Msk              (0x1UL << PWR_CSR1_AVDO_Pos)            /*!< 0x00010000 */

+#define PWR_CSR1_AVDO                  PWR_CSR1_AVDO_Msk                       /*!< Analog Voltage Detect Output */

+#define PWR_CSR1_ACTVOS_Pos            (14U)

+#define PWR_CSR1_ACTVOS_Msk            (0x3UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x0000C000 */

+#define PWR_CSR1_ACTVOS                PWR_CSR1_ACTVOS_Msk                     /*!< Current actual used VOS for VDD11 Voltage Scaling */

+#define PWR_CSR1_ACTVOS_0              (0x1UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00004000 */

+#define PWR_CSR1_ACTVOS_1              (0x2UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00008000 */

+#define PWR_CSR1_ACTVOSRDY_Pos         (13U)

+#define PWR_CSR1_ACTVOSRDY_Msk         (0x1UL << PWR_CSR1_ACTVOSRDY_Pos)       /*!< 0x00002000 */

+#define PWR_CSR1_ACTVOSRDY             PWR_CSR1_ACTVOSRDY_Msk                  /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling  */

+#define PWR_CSR1_PVDO_Pos              (4U)

+#define PWR_CSR1_PVDO_Msk              (0x1UL << PWR_CSR1_PVDO_Pos)            /*!< 0x00000010 */

+#define PWR_CSR1_PVDO                  PWR_CSR1_PVDO_Msk                       /*!< Programmable Voltage Detect Output */

+

+/********************  Bit definition for PWR_CR2 register  *******************/

+#define PWR_CR2_TEMPH_Pos              (23U)

+#define PWR_CR2_TEMPH_Msk              (0x1UL << PWR_CR2_TEMPH_Pos)            /*!< 0x00800000 */

+#define PWR_CR2_TEMPH                  PWR_CR2_TEMPH_Msk                       /*!< Monitored temperature level above high threshold */

+#define PWR_CR2_TEMPL_Pos              (22U)

+#define PWR_CR2_TEMPL_Msk              (0x1UL << PWR_CR2_TEMPL_Pos)            /*!< 0x00400000 */

+#define PWR_CR2_TEMPL                  PWR_CR2_TEMPL_Msk                       /*!< Monitored temperature level above low threshold */

+#define PWR_CR2_VBATH_Pos              (21U)

+#define PWR_CR2_VBATH_Msk              (0x1UL << PWR_CR2_VBATH_Pos)            /*!< 0x00200000 */

+#define PWR_CR2_VBATH                  PWR_CR2_VBATH_Msk                       /*!< Monitored VBAT level above high threshold */

+#define PWR_CR2_VBATL_Pos              (20U)

+#define PWR_CR2_VBATL_Msk              (0x1UL << PWR_CR2_VBATL_Pos)            /*!< 0x00100000 */

+#define PWR_CR2_VBATL                  PWR_CR2_VBATL_Msk                       /*!< Monitored VBAT level above low threshold */

+#define PWR_CR2_BRRDY_Pos              (16U)

+#define PWR_CR2_BRRDY_Msk              (0x1UL << PWR_CR2_BRRDY_Pos)            /*!< 0x00010000 */

+#define PWR_CR2_BRRDY                  PWR_CR2_BRRDY_Msk                       /*!< Backup regulator ready */

+#define PWR_CR2_MONEN_Pos              (4U)

+#define PWR_CR2_MONEN_Msk              (0x1UL << PWR_CR2_MONEN_Pos)            /*!< 0x00000010 */

+#define PWR_CR2_MONEN                  PWR_CR2_MONEN_Msk                       /*!< VBAT and temperature monitoring enable */

+#define PWR_CR2_BREN_Pos               (0U)

+#define PWR_CR2_BREN_Msk               (0x1UL << PWR_CR2_BREN_Pos)             /*!< 0x00000001 */

+#define PWR_CR2_BREN                   PWR_CR2_BREN_Msk                        /*!< Backup regulator enable */

+

+/********************  Bit definition for PWR_CR3 register  *******************/

+#define PWR_CR3_USB33RDY_Pos           (26U)

+#define PWR_CR3_USB33RDY_Msk           (0x1UL << PWR_CR3_USB33RDY_Pos)         /*!< 0x04000000 */

+#define PWR_CR3_USB33RDY               PWR_CR3_USB33RDY_Msk                    /*!< USB supply ready */

+#define PWR_CR3_USBREGEN_Pos           (25U)

+#define PWR_CR3_USBREGEN_Msk           (0x1UL << PWR_CR3_USBREGEN_Pos)         /*!< 0x02000000 */

+#define PWR_CR3_USBREGEN               PWR_CR3_USBREGEN_Msk                    /*!< USB regulator enable */

+#define PWR_CR3_USB33DEN_Pos           (24U)

+#define PWR_CR3_USB33DEN_Msk           (0x1UL << PWR_CR3_USB33DEN_Pos)         /*!< 0x01000000 */

+#define PWR_CR3_USB33DEN               PWR_CR3_USB33DEN_Msk                    /*!< VDD33_USB voltage level detector enable */

+#define PWR_CR3_SMPSEXTRDY_Pos         (16U)

+#define PWR_CR3_SMPSEXTRDY_Msk         (0x1UL << PWR_CR3_SMPSEXTRDY_Pos)       /*!< 0x00010000 */

+#define PWR_CR3_SMPSEXTRDY             PWR_CR3_SMPSEXTRDY_Msk                  /*!< SMPS External supply ready */

+#define PWR_CR3_VBRS_Pos               (9U)

+#define PWR_CR3_VBRS_Msk               (0x1UL << PWR_CR3_VBRS_Pos)             /*!< 0x00000200 */

+#define PWR_CR3_VBRS                   PWR_CR3_VBRS_Msk                        /*!< VBAT charging resistor selection */

+#define PWR_CR3_VBE_Pos                (8U)

+#define PWR_CR3_VBE_Msk                (0x1UL << PWR_CR3_VBE_Pos)              /*!< 0x00000100 */

+#define PWR_CR3_VBE                    PWR_CR3_VBE_Msk                         /*!< VBAT charging enable */

+#define PWR_CR3_SMPSLEVEL_Pos          (4U)

+#define PWR_CR3_SMPSLEVEL_Msk          (0x3UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000030 */

+#define PWR_CR3_SMPSLEVEL              PWR_CR3_SMPSLEVEL_Msk                   /*!< SMPS output Voltage */

+#define PWR_CR3_SMPSLEVEL_0            (0x1UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000010 */

+#define PWR_CR3_SMPSLEVEL_1            (0x2UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000020 */

+#define PWR_CR3_SMPSEXTHP_Pos          (3U)

+#define PWR_CR3_SMPSEXTHP_Msk          (0x1UL << PWR_CR3_SMPSEXTHP_Pos)        /*!< 0x00000008 */

+#define PWR_CR3_SMPSEXTHP              PWR_CR3_SMPSEXTHP_Msk                   /*!< SMPS forced ON and in High Power MR mode */

+#define PWR_CR3_SMPSEN_Pos             (2U)

+#define PWR_CR3_SMPSEN_Msk             (0x1UL << PWR_CR3_SMPSEN_Pos)           /*!< 0x00000004 */

+#define PWR_CR3_SMPSEN                 PWR_CR3_SMPSEN_Msk                      /*!< SMPS Enable */

+#define PWR_CR3_LDOEN_Pos              (1U)

+#define PWR_CR3_LDOEN_Msk              (0x1UL << PWR_CR3_LDOEN_Pos)            /*!< 0x00000002 */

+#define PWR_CR3_LDOEN                  PWR_CR3_LDOEN_Msk                       /*!< Low Drop Output regulator enable */

+#define PWR_CR3_BYPASS_Pos             (0U)

+#define PWR_CR3_BYPASS_Msk             (0x1UL << PWR_CR3_BYPASS_Pos)           /*!< 0x00000001 */

+#define PWR_CR3_BYPASS                 PWR_CR3_BYPASS_Msk                      /*!< Power Management Unit bypass */

+

+/********************  Bit definition for PWR_CPUCR register  *****************/

+#define PWR_CPUCR_RUN_SRD_Pos          (11U)

+#define PWR_CPUCR_RUN_SRD_Msk          (0x1UL << PWR_CPUCR_RUN_SRD_Pos)        /*!< 0x00000800 */

+#define PWR_CPUCR_RUN_SRD              PWR_CPUCR_RUN_SRD_Msk                   /*!< Keep system SRD domain in RUN mode regardless of the CPU sub-systems modes */

+#define PWR_CPUCR_CSSF_Pos             (9U)

+#define PWR_CPUCR_CSSF_Msk             (0x1UL << PWR_CPUCR_CSSF_Pos)           /*!< 0x00000200 */

+#define PWR_CPUCR_CSSF                 PWR_CPUCR_CSSF_Msk                      /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */

+#define PWR_CPUCR_SBF_Pos              (6U)

+#define PWR_CPUCR_SBF_Msk              (0x1UL << PWR_CPUCR_SBF_Pos)            /*!< 0x00000040 */

+#define PWR_CPUCR_SBF                  PWR_CPUCR_SBF_Msk                       /*!< System STANDBY Flag */

+#define PWR_CPUCR_STOPF_Pos            (5U)

+#define PWR_CPUCR_STOPF_Msk            (0x1UL << PWR_CPUCR_STOPF_Pos)          /*!< 0x00000020 */

+#define PWR_CPUCR_STOPF                PWR_CPUCR_STOPF_Msk                     /*!< STOP Flag */

+#define PWR_CPUCR_PDDS_SRD_Pos         (2U)

+#define PWR_CPUCR_PDDS_SRD_Msk         (0x1UL << PWR_CPUCR_PDDS_SRD_Pos)       /*!< 0x00000004 */

+#define PWR_CPUCR_PDDS_SRD             PWR_CPUCR_PDDS_SRD_Msk                  /*!< System SRD domain Power Down Deepsleep */

+#define PWR_CPUCR_RETDS_CD_Pos         (0U)

+#define PWR_CPUCR_RETDS_CD_Msk         (0x1UL << PWR_CPUCR_RETDS_CD_Pos)       /*!< 0x00000001 */

+#define PWR_CPUCR_RETDS_CD             PWR_CPUCR_RETDS_CD_Msk                  /*!< CD domain Power Down Deepsleep selection */

+/********************  Bit definition for PWR_SRDCR register  *****************/

+#define PWR_SRDCR_VOS_Pos              (14U)

+#define PWR_SRDCR_VOS_Msk              (0x3UL << PWR_SRDCR_VOS_Pos)             /*!< 0x0000C000 */

+#define PWR_SRDCR_VOS                  PWR_SRDCR_VOS_Msk                        /*!< Voltage Scaling selection according performance */

+#define PWR_SRDCR_VOS_0                (0x1UL << PWR_SRDCR_VOS_Pos)             /*!< 0x00004000 */

+#define PWR_SRDCR_VOS_1                (0x2UL << PWR_SRDCR_VOS_Pos)             /*!< 0x00008000 */

+#define PWR_SRDCR_VOSRDY_Pos           (13U)

+#define PWR_SRDCR_VOSRDY_Msk           (0x1UL << PWR_SRDCR_VOSRDY_Pos)          /*!< 0x00002000 */

+#define PWR_SRDCR_VOSRDY               PWR_SRDCR_VOSRDY_Msk                     /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */

+/******************  Bit definition for PWR_WKUPCR register  ******************/

+#define PWR_WKUPCR_WKUPC6_Pos          (5U)

+#define PWR_WKUPCR_WKUPC6_Msk          (0x1UL << PWR_WKUPCR_WKUPC6_Pos)        /*!< 0x00000020 */

+#define PWR_WKUPCR_WKUPC6              PWR_WKUPCR_WKUPC6_Msk                   /*!< Clear Wakeup Pin Flag 6 */

+#define PWR_WKUPCR_WKUPC5_Pos          (4U)

+#define PWR_WKUPCR_WKUPC5_Msk          (0x1UL << PWR_WKUPCR_WKUPC5_Pos)        /*!< 0x00000010 */

+#define PWR_WKUPCR_WKUPC5              PWR_WKUPCR_WKUPC5_Msk                   /*!< Clear Wakeup Pin Flag 5 */

+#define PWR_WKUPCR_WKUPC4_Pos          (3U)

+#define PWR_WKUPCR_WKUPC4_Msk          (0x1UL << PWR_WKUPCR_WKUPC4_Pos)        /*!< 0x00000008 */

+#define PWR_WKUPCR_WKUPC4              PWR_WKUPCR_WKUPC4_Msk                   /*!< Clear Wakeup Pin Flag 4 */

+#define PWR_WKUPCR_WKUPC3_Pos          (2U)

+#define PWR_WKUPCR_WKUPC3_Msk          (0x1UL << PWR_WKUPCR_WKUPC3_Pos)        /*!< 0x00000004 */

+#define PWR_WKUPCR_WKUPC3              PWR_WKUPCR_WKUPC3_Msk                   /*!< Clear Wakeup Pin Flag 3 */

+#define PWR_WKUPCR_WKUPC2_Pos          (1U)

+#define PWR_WKUPCR_WKUPC2_Msk          (0x1UL << PWR_WKUPCR_WKUPC2_Pos)        /*!< 0x00000002 */

+#define PWR_WKUPCR_WKUPC2              PWR_WKUPCR_WKUPC2_Msk                   /*!< Clear Wakeup Pin Flag 2 */

+#define PWR_WKUPCR_WKUPC1_Pos          (0U)

+#define PWR_WKUPCR_WKUPC1_Msk          (0x1UL << PWR_WKUPCR_WKUPC1_Pos)        /*!< 0x00000001 */

+#define PWR_WKUPCR_WKUPC1              PWR_WKUPCR_WKUPC1_Msk                   /*!< Clear Wakeup Pin Flag 1 */

+

+/********************  Bit definition for PWR_WKUPFR register  ****************/

+#define PWR_WKUPFR_WKUPF6_Pos          (5U)

+#define PWR_WKUPFR_WKUPF6_Msk          (0x1UL << PWR_WKUPFR_WKUPF6_Pos)        /*!< 0x00000020 */

+#define PWR_WKUPFR_WKUPF6              PWR_WKUPFR_WKUPF6_Msk                   /*!< Wakeup Pin Flag 6 */

+#define PWR_WKUPFR_WKUPF5_Pos          (4U)

+#define PWR_WKUPFR_WKUPF5_Msk          (0x1UL << PWR_WKUPFR_WKUPF5_Pos)        /*!< 0x00000010 */

+#define PWR_WKUPFR_WKUPF5              PWR_WKUPFR_WKUPF5_Msk                   /*!< Wakeup Pin Flag 5 */

+#define PWR_WKUPFR_WKUPF4_Pos          (3U)

+#define PWR_WKUPFR_WKUPF4_Msk          (0x1UL << PWR_WKUPFR_WKUPF4_Pos)        /*!< 0x00000008 */

+#define PWR_WKUPFR_WKUPF4              PWR_WKUPFR_WKUPF4_Msk                   /*!< Wakeup Pin Flag 4 */

+#define PWR_WKUPFR_WKUPF3_Pos          (2U)

+#define PWR_WKUPFR_WKUPF3_Msk          (0x1UL << PWR_WKUPFR_WKUPF3_Pos)        /*!< 0x00000004 */

+#define PWR_WKUPFR_WKUPF3              PWR_WKUPFR_WKUPF3_Msk                   /*!< Wakeup Pin Flag 3 */

+#define PWR_WKUPFR_WKUPF2_Pos          (1U)

+#define PWR_WKUPFR_WKUPF2_Msk          (0x1UL << PWR_WKUPFR_WKUPF2_Pos)        /*!< 0x00000002 */

+#define PWR_WKUPFR_WKUPF2              PWR_WKUPFR_WKUPF2_Msk                   /*!< Wakeup Pin Flag 2 */

+#define PWR_WKUPFR_WKUPF1_Pos          (0U)

+#define PWR_WKUPFR_WKUPF1_Msk          (0x1UL << PWR_WKUPFR_WKUPF1_Pos)        /*!< 0x00000001 */

+#define PWR_WKUPFR_WKUPF1              PWR_WKUPFR_WKUPF1_Msk                   /*!< Wakeup Pin Flag 1 */

+

+/******************  Bit definition for PWR_WKUPEPR register  *****************/

+#define PWR_WKUPEPR_WKUPPUPD6_Pos      (26U)

+#define PWR_WKUPEPR_WKUPPUPD6_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x0C000000 */

+#define PWR_WKUPEPR_WKUPPUPD6          PWR_WKUPEPR_WKUPPUPD6_Msk               /*!< Wakeup Pin pull configuration for WKUP6 */

+#define PWR_WKUPEPR_WKUPPUPD6_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x04000000 */

+#define PWR_WKUPEPR_WKUPPUPD6_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x08000000 */

+#define PWR_WKUPEPR_WKUPPUPD5_Pos      (24U)

+#define PWR_WKUPEPR_WKUPPUPD5_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x03000000 */

+#define PWR_WKUPEPR_WKUPPUPD5          PWR_WKUPEPR_WKUPPUPD5_Msk               /*!< Wakeup Pin pull configuration for WKUP5 */

+#define PWR_WKUPEPR_WKUPPUPD5_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x01000000 */

+#define PWR_WKUPEPR_WKUPPUPD5_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x02000000 */

+#define PWR_WKUPEPR_WKUPPUPD4_Pos      (22U)

+#define PWR_WKUPEPR_WKUPPUPD4_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00C00000 */

+#define PWR_WKUPEPR_WKUPPUPD4          PWR_WKUPEPR_WKUPPUPD4_Msk               /*!< Wakeup Pin pull configuration for WKUP4 */

+#define PWR_WKUPEPR_WKUPPUPD4_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00400000 */

+#define PWR_WKUPEPR_WKUPPUPD4_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00800000 */

+#define PWR_WKUPEPR_WKUPPUPD3_Pos      (20U)

+#define PWR_WKUPEPR_WKUPPUPD3_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00300000 */

+#define PWR_WKUPEPR_WKUPPUPD3          PWR_WKUPEPR_WKUPPUPD3_Msk               /*!< Wakeup Pin pull configuration for WKUP3 */

+#define PWR_WKUPEPR_WKUPPUPD3_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00100000 */

+#define PWR_WKUPEPR_WKUPPUPD3_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00200000 */

+#define PWR_WKUPEPR_WKUPPUPD2_Pos      (18U)

+#define PWR_WKUPEPR_WKUPPUPD2_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x000C0000 */

+#define PWR_WKUPEPR_WKUPPUPD2          PWR_WKUPEPR_WKUPPUPD2_Msk               /*!< Wakeup Pin pull configuration for WKUP2 */

+#define PWR_WKUPEPR_WKUPPUPD2_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00040000 */

+#define PWR_WKUPEPR_WKUPPUPD2_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00080000 */

+#define PWR_WKUPEPR_WKUPPUPD1_Pos      (16U)

+#define PWR_WKUPEPR_WKUPPUPD1_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00030000 */

+#define PWR_WKUPEPR_WKUPPUPD1          PWR_WKUPEPR_WKUPPUPD1_Msk               /*!< Wakeup Pin pull configuration for WKUP1 */

+#define PWR_WKUPEPR_WKUPPUPD1_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00010000 */

+#define PWR_WKUPEPR_WKUPPUPD1_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00020000 */

+#define PWR_WKUPEPR_WKUPP6_Pos         (13U)

+#define PWR_WKUPEPR_WKUPP6_Msk         (0x1UL << PWR_WKUPEPR_WKUPP6_Pos)       /*!< 0x00002000 */

+#define PWR_WKUPEPR_WKUPP6             PWR_WKUPEPR_WKUPP6_Msk                  /*!< Wakeup Pin Polarity for WKUP6 */

+#define PWR_WKUPEPR_WKUPP5_Pos         (12U)

+#define PWR_WKUPEPR_WKUPP5_Msk         (0x1UL << PWR_WKUPEPR_WKUPP5_Pos)       /*!< 0x00001000 */

+#define PWR_WKUPEPR_WKUPP5             PWR_WKUPEPR_WKUPP5_Msk                  /*!< Wakeup Pin Polarity for WKUP5 */

+#define PWR_WKUPEPR_WKUPP4_Pos         (11U)

+#define PWR_WKUPEPR_WKUPP4_Msk         (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)       /*!< 0x00000800 */

+#define PWR_WKUPEPR_WKUPP4             PWR_WKUPEPR_WKUPP4_Msk                  /*!< Wakeup Pin Polarity for WKUP4 */

+#define PWR_WKUPEPR_WKUPP3_Pos         (10U)

+#define PWR_WKUPEPR_WKUPP3_Msk         (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)       /*!< 0x00000400 */

+#define PWR_WKUPEPR_WKUPP3             PWR_WKUPEPR_WKUPP3_Msk                  /*!< Wakeup Pin Polarity for WKUP3 */

+#define PWR_WKUPEPR_WKUPP2_Pos         (9U)

+#define PWR_WKUPEPR_WKUPP2_Msk         (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)       /*!< 0x00000200 */

+#define PWR_WKUPEPR_WKUPP2             PWR_WKUPEPR_WKUPP2_Msk                  /*!< Wakeup Pin Polarity for WKUP2 */

+#define PWR_WKUPEPR_WKUPP1_Pos         (8U)

+#define PWR_WKUPEPR_WKUPP1_Msk         (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)       /*!< 0x00000100 */

+#define PWR_WKUPEPR_WKUPP1             PWR_WKUPEPR_WKUPP1_Msk                  /*!< Wakeup Pin Polarity for WKUP1 */

+#define PWR_WKUPEPR_WKUPEN6_Pos        (5U)

+#define PWR_WKUPEPR_WKUPEN6_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos)      /*!< 0x00000020 */

+#define PWR_WKUPEPR_WKUPEN6            PWR_WKUPEPR_WKUPEN6_Msk                 /*!< Enable Wakeup Pin WKUP6 */

+#define PWR_WKUPEPR_WKUPEN5_Pos        (4U)

+#define PWR_WKUPEPR_WKUPEN5_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos)      /*!< 0x00000010 */

+#define PWR_WKUPEPR_WKUPEN5            PWR_WKUPEPR_WKUPEN5_Msk                 /*!< Enable Wakeup Pin WKUP5 */

+#define PWR_WKUPEPR_WKUPEN4_Pos        (3U)

+#define PWR_WKUPEPR_WKUPEN4_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)      /*!< 0x00000008 */

+#define PWR_WKUPEPR_WKUPEN4            PWR_WKUPEPR_WKUPEN4_Msk                 /*!< Enable Wakeup Pin WKUP4 */

+#define PWR_WKUPEPR_WKUPEN3_Pos        (2U)

+#define PWR_WKUPEPR_WKUPEN3_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)      /*!< 0x00000004 */

+#define PWR_WKUPEPR_WKUPEN3            PWR_WKUPEPR_WKUPEN3_Msk                 /*!< Enable Wakeup Pin WKUP3 */

+#define PWR_WKUPEPR_WKUPEN2_Pos        (1U)

+#define PWR_WKUPEPR_WKUPEN2_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)      /*!< 0x00000002 */

+#define PWR_WKUPEPR_WKUPEN2            PWR_WKUPEPR_WKUPEN2_Msk                 /*!< Enable Wakeup Pin WKUP2 */

+#define PWR_WKUPEPR_WKUPEN1_Pos        (0U)

+#define PWR_WKUPEPR_WKUPEN1_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)      /*!< 0x00000001 */

+#define PWR_WKUPEPR_WKUPEN1            PWR_WKUPEPR_WKUPEN1_Msk                 /*!< Enable Wakeup Pin WKUP1 */

+#define PWR_WKUPEPR_WKUPEN_Pos         (0U)

+#define PWR_WKUPEPR_WKUPEN_Msk         (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos)      /*!< 0x0000003F */

+#define PWR_WKUPEPR_WKUPEN             PWR_WKUPEPR_WKUPEN_Msk                  /*!< Enable all Wakeup Pin */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Reset and Clock Control                            */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  RCC VERSION  ********************************/

+#define RCC_VER_2_0

+

+/********************  Bit definition for RCC_CR register  ********************/

+#define RCC_CR_HSION_Pos                       (0U)

+#define RCC_CR_HSION_Msk                       (0x1UL << RCC_CR_HSION_Pos)     /*!< 0x00000001 */

+#define RCC_CR_HSION                           RCC_CR_HSION_Msk                /*!< Internal High Speed clock enable */

+#define RCC_CR_HSIKERON_Pos                    (1U)

+#define RCC_CR_HSIKERON_Msk                    (0x1UL << RCC_CR_HSIKERON_Pos)  /*!< 0x00000002 */

+#define RCC_CR_HSIKERON                        RCC_CR_HSIKERON_Msk             /*!< Internal High Speed clock enable for some IPs Kernel */

+#define RCC_CR_HSIRDY_Pos                      (2U)

+#define RCC_CR_HSIRDY_Msk                      (0x1UL << RCC_CR_HSIRDY_Pos)    /*!< 0x00000004 */

+#define RCC_CR_HSIRDY                          RCC_CR_HSIRDY_Msk               /*!< Internal High Speed clock ready flag */

+#define RCC_CR_HSIDIV_Pos                      (3U)

+#define RCC_CR_HSIDIV_Msk                      (0x3UL << RCC_CR_HSIDIV_Pos)    /*!< 0x00000018 */

+#define RCC_CR_HSIDIV                          RCC_CR_HSIDIV_Msk               /*!< Internal High Speed clock divider selection */

+#define RCC_CR_HSIDIV_1                        (0x0UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000000 */

+#define RCC_CR_HSIDIV_2                        (0x1UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000008 */

+#define RCC_CR_HSIDIV_4                        (0x2UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000010 */

+#define RCC_CR_HSIDIV_8                        (0x3UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000018 */

+

+#define RCC_CR_HSIDIVF_Pos                     (5U)

+#define RCC_CR_HSIDIVF_Msk                     (0x1UL << RCC_CR_HSIDIVF_Pos)   /*!< 0x00000020 */

+#define RCC_CR_HSIDIVF                         RCC_CR_HSIDIVF_Msk              /*!< HSI Divider flag */

+#define RCC_CR_CSION_Pos                       (7U)

+#define RCC_CR_CSION_Msk                       (0x1UL << RCC_CR_CSION_Pos)     /*!< 0x00000080 */

+#define RCC_CR_CSION                           RCC_CR_CSION_Msk                /*!< The Internal RC 4MHz oscillator clock enable */

+#define RCC_CR_CSIRDY_Pos                      (8U)

+#define RCC_CR_CSIRDY_Msk                      (0x1UL << RCC_CR_CSIRDY_Pos)    /*!< 0x00000100 */

+#define RCC_CR_CSIRDY                          RCC_CR_CSIRDY_Msk               /*!< The Internal RC 4MHz oscillator clock ready */

+#define RCC_CR_CSIKERON_Pos                    (9U)

+#define RCC_CR_CSIKERON_Msk                    (0x1UL << RCC_CR_CSIKERON_Pos)  /*!< 0x00000200 */

+#define RCC_CR_CSIKERON                        RCC_CR_CSIKERON_Msk             /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */

+#define RCC_CR_HSI48ON_Pos                     (12U)

+#define RCC_CR_HSI48ON_Msk                     (0x1UL << RCC_CR_HSI48ON_Pos)   /*!< 0x00001000 */

+#define RCC_CR_HSI48ON                         RCC_CR_HSI48ON_Msk              /*!< HSI48 clock enable clock enable  */

+#define RCC_CR_HSI48RDY_Pos                    (13U)

+#define RCC_CR_HSI48RDY_Msk                    (0x1UL << RCC_CR_HSI48RDY_Pos)  /*!< 0x00002000 */

+#define RCC_CR_HSI48RDY                        RCC_CR_HSI48RDY_Msk             /*!< HSI48 clock ready */

+

+#define RCC_CR_CPUCKRDY_Pos                     (14U)

+#define RCC_CR_CPUCKRDY_Msk                     (0x1UL << RCC_CR_CPUCKRDY_Pos)   /*!< 0x00004000 */

+#define RCC_CR_CPUCKRDY                         RCC_CR_CPUCKRDY_Msk              /*!< CPU domain clocks ready flag  */

+#define RCC_CR_CDCKRDY_Pos                     (15U)

+#define RCC_CR_CDCKRDY_Msk                     (0x1UL << RCC_CR_CDCKRDY_Pos)   /*!< 0x00008000 */

+#define RCC_CR_CDCKRDY                         RCC_CR_CDCKRDY_Msk              /*!< CD domain clocks ready flag */

+

+#define RCC_CR_HSEON_Pos                       (16U)

+#define RCC_CR_HSEON_Msk                       (0x1UL << RCC_CR_HSEON_Pos)     /*!< 0x00010000 */

+#define RCC_CR_HSEON                           RCC_CR_HSEON_Msk                /*!< External High Speed clock enable */

+#define RCC_CR_HSERDY_Pos                      (17U)

+#define RCC_CR_HSERDY_Msk                      (0x1UL << RCC_CR_HSERDY_Pos)    /*!< 0x00020000 */

+#define RCC_CR_HSERDY                          RCC_CR_HSERDY_Msk               /*!< External High Speed clock ready */

+#define RCC_CR_HSEBYP_Pos                      (18U)

+#define RCC_CR_HSEBYP_Msk                      (0x1UL << RCC_CR_HSEBYP_Pos)    /*!< 0x00040000 */

+#define RCC_CR_HSEBYP                          RCC_CR_HSEBYP_Msk               /*!< External High Speed clock Bypass */

+#define RCC_CR_CSSHSEON_Pos                    (19U)

+#define RCC_CR_CSSHSEON_Msk                    (0x1UL << RCC_CR_CSSHSEON_Pos)  /*!< 0x00080000 */

+#define RCC_CR_CSSHSEON                        RCC_CR_CSSHSEON_Msk             /*!< HSE Clock security System enable */

+

+#define RCC_CR_HSEEXT_Pos                    (20U)

+#define RCC_CR_HSEEXT_Msk                    (0x1UL << RCC_CR_HSEEXT_Pos)  /*!< 0x00080000 */

+#define RCC_CR_HSEEXT                        RCC_CR_HSEEXT_Msk             /*!< HSE Clock security System enable */

+

+#define RCC_CR_PLL1ON_Pos                      (24U)

+#define RCC_CR_PLL1ON_Msk                      (0x1UL << RCC_CR_PLL1ON_Pos)    /*!< 0x01000000 */

+#define RCC_CR_PLL1ON                          RCC_CR_PLL1ON_Msk               /*!< System PLL1 clock enable */

+#define RCC_CR_PLL1RDY_Pos                     (25U)

+#define RCC_CR_PLL1RDY_Msk                     (0x1UL << RCC_CR_PLL1RDY_Pos)   /*!< 0x02000000 */

+#define RCC_CR_PLL1RDY                         RCC_CR_PLL1RDY_Msk              /*!< System PLL1 clock ready */

+#define RCC_CR_PLL2ON_Pos                      (26U)

+#define RCC_CR_PLL2ON_Msk                      (0x1UL << RCC_CR_PLL2ON_Pos)    /*!< 0x04000000 */

+#define RCC_CR_PLL2ON                          RCC_CR_PLL2ON_Msk               /*!< System PLL2 clock enable */

+#define RCC_CR_PLL2RDY_Pos                     (27U)

+#define RCC_CR_PLL2RDY_Msk                     (0x1UL << RCC_CR_PLL2RDY_Pos)   /*!< 0x08000000 */

+#define RCC_CR_PLL2RDY                         RCC_CR_PLL2RDY_Msk              /*!< System PLL2 clock ready */

+#define RCC_CR_PLL3ON_Pos                      (28U)

+#define RCC_CR_PLL3ON_Msk                      (0x1UL << RCC_CR_PLL3ON_Pos)    /*!< 0x10000000 */

+#define RCC_CR_PLL3ON                          RCC_CR_PLL3ON_Msk               /*!< System PLL3 clock enable */

+#define RCC_CR_PLL3RDY_Pos                     (29U)

+#define RCC_CR_PLL3RDY_Msk                     (0x1UL << RCC_CR_PLL3RDY_Pos)   /*!< 0x20000000 */

+#define RCC_CR_PLL3RDY                         RCC_CR_PLL3RDY_Msk              /*!< System PLL3 clock ready */

+

+/*Legacy */

+#define RCC_CR_PLLON_Pos                       (24U)

+#define RCC_CR_PLLON_Msk                       (0x1UL << RCC_CR_PLLON_Pos)     /*!< 0x01000000 */

+#define RCC_CR_PLLON                           RCC_CR_PLLON_Msk                /*!< System PLL clock enable */

+#define RCC_CR_PLLRDY_Pos                      (25U)

+#define RCC_CR_PLLRDY_Msk                      (0x1UL << RCC_CR_PLLRDY_Pos)    /*!< 0x02000000 */

+#define RCC_CR_PLLRDY                          RCC_CR_PLLRDY_Msk               /*!< System PLL clock ready */

+

+/********************  Bit definition for RCC_HSICFGR register  ***************/

+/*!< HSICAL configuration */

+#define RCC_HSICFGR_HSICAL_Pos                 (0U)

+#define RCC_HSICFGR_HSICAL_Msk                 (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */

+#define RCC_HSICFGR_HSICAL                     RCC_HSICFGR_HSICAL_Msk          /*!< HSICAL[11:0] bits */

+#define RCC_HSICFGR_HSICAL_0                   (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */

+#define RCC_HSICFGR_HSICAL_1                   (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */

+#define RCC_HSICFGR_HSICAL_2                   (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */

+#define RCC_HSICFGR_HSICAL_3                   (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */

+#define RCC_HSICFGR_HSICAL_4                   (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */

+#define RCC_HSICFGR_HSICAL_5                   (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */

+#define RCC_HSICFGR_HSICAL_6                   (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */

+#define RCC_HSICFGR_HSICAL_7                   (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */

+#define RCC_HSICFGR_HSICAL_8                   (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */

+#define RCC_HSICFGR_HSICAL_9                   (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */

+#define RCC_HSICFGR_HSICAL_10                  (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */

+#define RCC_HSICFGR_HSICAL_11                  (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */

+

+/*!< HSITRIM configuration */

+#define RCC_HSICFGR_HSITRIM_Pos                (24U)

+#define RCC_HSICFGR_HSITRIM_Msk                (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */

+#define RCC_HSICFGR_HSITRIM                    RCC_HSICFGR_HSITRIM_Msk         /*!< HSITRIM[6:0] bits */

+#define RCC_HSICFGR_HSITRIM_0                  (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */

+#define RCC_HSICFGR_HSITRIM_1                  (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */

+#define RCC_HSICFGR_HSITRIM_2                  (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */

+#define RCC_HSICFGR_HSITRIM_3                  (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */

+#define RCC_HSICFGR_HSITRIM_4                  (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */

+#define RCC_HSICFGR_HSITRIM_5                  (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */

+#define RCC_HSICFGR_HSITRIM_6                  (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */

+

+

+/********************  Bit definition for RCC_CRRCR register  *****************/

+

+/*!< HSI48CAL configuration */

+#define RCC_CRRCR_HSI48CAL_Pos                 (0U)

+#define RCC_CRRCR_HSI48CAL_Msk                 (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */

+#define RCC_CRRCR_HSI48CAL                     RCC_CRRCR_HSI48CAL_Msk          /*!< HSI48CAL[9:0] bits */

+#define RCC_CRRCR_HSI48CAL_0                   (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */

+#define RCC_CRRCR_HSI48CAL_1                   (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */

+#define RCC_CRRCR_HSI48CAL_2                   (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */

+#define RCC_CRRCR_HSI48CAL_3                   (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */

+#define RCC_CRRCR_HSI48CAL_4                   (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */

+#define RCC_CRRCR_HSI48CAL_5                   (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */

+#define RCC_CRRCR_HSI48CAL_6                   (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */

+#define RCC_CRRCR_HSI48CAL_7                   (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */

+#define RCC_CRRCR_HSI48CAL_8                   (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */

+#define RCC_CRRCR_HSI48CAL_9                   (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */

+

+

+/********************  Bit definition for RCC_CSICFGR register  *****************/

+/*!< CSICAL configuration */

+#define RCC_CSICFGR_CSICAL_Pos                 (0U)

+#define RCC_CSICFGR_CSICAL_Msk                 (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */

+#define RCC_CSICFGR_CSICAL                     RCC_CSICFGR_CSICAL_Msk          /*!< CSICAL[7:0] bits */

+#define RCC_CSICFGR_CSICAL_0                   (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */

+#define RCC_CSICFGR_CSICAL_1                   (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */

+#define RCC_CSICFGR_CSICAL_2                   (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */

+#define RCC_CSICFGR_CSICAL_3                   (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */

+#define RCC_CSICFGR_CSICAL_4                   (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */

+#define RCC_CSICFGR_CSICAL_5                   (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */

+#define RCC_CSICFGR_CSICAL_6                   (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */

+#define RCC_CSICFGR_CSICAL_7                   (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */

+

+/*!< CSITRIM configuration */

+#define RCC_CSICFGR_CSITRIM_Pos                (24U)

+#define RCC_CSICFGR_CSITRIM_Msk                (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */

+#define RCC_CSICFGR_CSITRIM                    RCC_CSICFGR_CSITRIM_Msk         /*!< CSITRIM[5:0] bits */

+#define RCC_CSICFGR_CSITRIM_0                  (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */

+#define RCC_CSICFGR_CSITRIM_1                  (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */

+#define RCC_CSICFGR_CSITRIM_2                  (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */

+#define RCC_CSICFGR_CSITRIM_3                  (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */

+#define RCC_CSICFGR_CSITRIM_4                  (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */

+#define RCC_CSICFGR_CSITRIM_5                  (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */

+

+/********************  Bit definition for RCC_CFGR register  ******************/

+/*!< SW configuration */

+#define RCC_CFGR_SW_Pos                        (0U)

+#define RCC_CFGR_SW_Msk                        (0x7UL << RCC_CFGR_SW_Pos)           /*!< 0x00000007 */

+#define RCC_CFGR_SW                            RCC_CFGR_SW_Msk                     /*!< SW[2:0] bits (System clock Switch) */

+#define RCC_CFGR_SW_0                          (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */

+#define RCC_CFGR_SW_1                          (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */

+#define RCC_CFGR_SW_2                          (0x4UL << RCC_CFGR_SW_Pos)           /*!< 0x00000004 */

+

+#define RCC_CFGR_SW_HSI                        (0x00000000UL)                       /*!< HSI selection as system clock */

+#define RCC_CFGR_SW_CSI                        (0x00000001UL)                       /*!< CSI selection as system clock */

+#define RCC_CFGR_SW_HSE                        (0x00000002UL)                       /*!< HSE selection as system clock */

+#define RCC_CFGR_SW_PLL1                       (0x00000003UL)                       /*!< PLL1 selection as system clock */

+

+/*!< SWS configuration */

+#define RCC_CFGR_SWS_Pos                       (3U)

+#define RCC_CFGR_SWS_Msk                       (0x7UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000038 */

+#define RCC_CFGR_SWS                           RCC_CFGR_SWS_Msk                    /*!< SWS[2:0] bits (System Clock Switch Status) */

+#define RCC_CFGR_SWS_0                         (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */

+#define RCC_CFGR_SWS_1                         (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000010 */

+#define RCC_CFGR_SWS_2                         (0x4UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000020 */

+

+#define RCC_CFGR_SWS_HSI                       (0x00000000UL)                       /*!< HSI used as system clock */

+#define RCC_CFGR_SWS_CSI                       (0x00000008UL)                       /*!< CSI used as system clock */

+#define RCC_CFGR_SWS_HSE                       (0x00000010UL)                       /*!< HSE used as system clock */

+#define RCC_CFGR_SWS_PLL1                      (0x00000018UL)                       /*!< PLL1 used as system clock */

+

+#define RCC_CFGR_STOPWUCK_Pos                  (6U)

+#define RCC_CFGR_STOPWUCK_Msk                  (0x1UL << RCC_CFGR_STOPWUCK_Pos)     /*!< 0x00000040 */

+#define RCC_CFGR_STOPWUCK                      RCC_CFGR_STOPWUCK_Msk                /*!< Wake Up from stop and CSS backup clock selection */

+

+#define RCC_CFGR_STOPKERWUCK_Pos               (7U)

+#define RCC_CFGR_STOPKERWUCK_Msk               (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)  /*!< 0x00000080 */

+#define RCC_CFGR_STOPKERWUCK                   RCC_CFGR_STOPKERWUCK_Msk             /*!< Kernel Clock Selection after a Wake Up from STOP */

+

+/*!< RTCPRE configuration */

+#define RCC_CFGR_RTCPRE_Pos                    (8U)

+#define RCC_CFGR_RTCPRE_Msk                    (0x3FUL << RCC_CFGR_RTCPRE_Pos)

+#define RCC_CFGR_RTCPRE                        RCC_CFGR_RTCPRE_Msk                  /*!< 0x00003F00 */

+#define RCC_CFGR_RTCPRE_0                      (0x1UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000100 */

+#define RCC_CFGR_RTCPRE_1                      (0x2UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000200 */

+#define RCC_CFGR_RTCPRE_2                      (0x4UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000400 */

+#define RCC_CFGR_RTCPRE_3                      (0x8UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000800 */

+#define RCC_CFGR_RTCPRE_4                      (0x10UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00001000 */

+#define RCC_CFGR_RTCPRE_5                      (0x20UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00002000 */

+

+

+/*!< TIMPRE configuration */

+#define RCC_CFGR_TIMPRE_Pos                    (15U)

+#define RCC_CFGR_TIMPRE_Msk                    (0x1UL << RCC_CFGR_TIMPRE_Pos)

+#define RCC_CFGR_TIMPRE                        RCC_CFGR_TIMPRE_Msk                  /*!< 0x00008000 */

+

+/*!< MCO1 configuration */

+#define RCC_CFGR_MCO1_Pos                      (22U)

+#define RCC_CFGR_MCO1_Msk                      (0x7UL << RCC_CFGR_MCO1_Pos)

+#define RCC_CFGR_MCO1                          RCC_CFGR_MCO1_Msk                       /*!< 0x01C00000 */

+#define RCC_CFGR_MCO1_0                        (0x1UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00400000 */

+#define RCC_CFGR_MCO1_1                        (0x2UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00800000 */

+#define RCC_CFGR_MCO1_2                        (0x4UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x01000000 */

+

+#define RCC_CFGR_MCO1PRE_Pos                   (18U)

+#define RCC_CFGR_MCO1PRE_Msk                   (0xFUL << RCC_CFGR_MCO1PRE_Pos)

+#define RCC_CFGR_MCO1PRE                       RCC_CFGR_MCO1PRE_Msk                    /*!< 0x003C0000 */

+#define RCC_CFGR_MCO1PRE_0                     (0x1UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00040000 */

+#define RCC_CFGR_MCO1PRE_1                     (0x2UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00080000 */

+#define RCC_CFGR_MCO1PRE_2                     (0x4UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00100000 */

+#define RCC_CFGR_MCO1PRE_3                     (0x8UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00200000 */

+

+#define RCC_CFGR_MCO2PRE_Pos                   (25U)

+#define RCC_CFGR_MCO2PRE_Msk                   (0xFUL << RCC_CFGR_MCO2PRE_Pos)

+#define RCC_CFGR_MCO2PRE                       RCC_CFGR_MCO2PRE_Msk                    /*!< 0x1E000000 */

+#define RCC_CFGR_MCO2PRE_0                     (0x1UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x02000000 */

+#define RCC_CFGR_MCO2PRE_1                     (0x2UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x04000000 */

+#define RCC_CFGR_MCO2PRE_2                     (0x4UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x08000000 */

+#define RCC_CFGR_MCO2PRE_3                     (0x8UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x10000000 */

+

+#define RCC_CFGR_MCO2_Pos                      (29U)

+#define RCC_CFGR_MCO2_Msk                      (0x7UL << RCC_CFGR_MCO2_Pos)

+#define RCC_CFGR_MCO2                          RCC_CFGR_MCO2_Msk                       /*!< 0xE0000000 */

+#define RCC_CFGR_MCO2_0                        (0x1UL << RCC_CFGR_MCO2_Pos)             /*!< 0x20000000 */

+#define RCC_CFGR_MCO2_1                        (0x2UL << RCC_CFGR_MCO2_Pos)             /*!< 0x40000000 */

+#define RCC_CFGR_MCO2_2                        (0x4UL << RCC_CFGR_MCO2_Pos)             /*!< 0x80000000 */

+

+/********************  Bit definition for RCC_D1CFGR register  ******************/

+/*!< D1HPRE configuration */

+#define RCC_CDCFGR1_HPRE_Pos                    (0U)

+#define RCC_CDCFGR1_HPRE_Msk                    (0xFUL << RCC_CDCFGR1_HPRE_Pos)  /*!< 0x0000000F */

+#define RCC_CDCFGR1_HPRE                        RCC_CDCFGR1_HPRE_Msk             /*!< HPRE[3:0] bits (AHB3 prescaler) */

+#define RCC_CDCFGR1_HPRE_0                      (0x1UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000001 */

+#define RCC_CDCFGR1_HPRE_1                      (0x2UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000002 */

+#define RCC_CDCFGR1_HPRE_2                      (0x4UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000004 */

+#define RCC_CDCFGR1_HPRE_3                      (0x8UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000008 */

+

+#define RCC_CDCFGR1_HPRE_DIV1                   ((uint32_t)0x00000000)                 /*!< AHB3 Clock not divided */

+#define RCC_CDCFGR1_HPRE_DIV2_Pos               (3U)

+#define RCC_CDCFGR1_HPRE_DIV2_Msk               (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos)   /*!< 0x00000008 */

+#define RCC_CDCFGR1_HPRE_DIV2                   RCC_CDCFGR1_HPRE_DIV2_Msk              /*!< AHB3 Clock divided by 2 */

+#define RCC_CDCFGR1_HPRE_DIV4_Pos               (0U)

+#define RCC_CDCFGR1_HPRE_DIV4_Msk               (0x9UL << RCC_CDCFGR1_HPRE_DIV4_Pos)   /*!< 0x00000009 */

+#define RCC_CDCFGR1_HPRE_DIV4                   RCC_CDCFGR1_HPRE_DIV4_Msk              /*!< AHB3 Clock divided by 4 */

+#define RCC_CDCFGR1_HPRE_DIV8_Pos               (1U)

+#define RCC_CDCFGR1_HPRE_DIV8_Msk               (0x5UL << RCC_CDCFGR1_HPRE_DIV8_Pos)   /*!< 0x0000000A */

+#define RCC_CDCFGR1_HPRE_DIV8                   RCC_CDCFGR1_HPRE_DIV8_Msk              /*!< AHB3 Clock divided by 8 */

+#define RCC_CDCFGR1_HPRE_DIV16_Pos              (0U)

+#define RCC_CDCFGR1_HPRE_DIV16_Msk              (0xBUL << RCC_CDCFGR1_HPRE_DIV16_Pos)  /*!< 0x0000000B */

+#define RCC_CDCFGR1_HPRE_DIV16                  RCC_CDCFGR1_HPRE_DIV16_Msk             /*!< AHB3 Clock divided by 16 */

+#define RCC_CDCFGR1_HPRE_DIV64_Pos              (2U)

+#define RCC_CDCFGR1_HPRE_DIV64_Msk              (0x3UL << RCC_CDCFGR1_HPRE_DIV64_Pos)  /*!< 0x0000000C */

+#define RCC_CDCFGR1_HPRE_DIV64                  RCC_CDCFGR1_HPRE_DIV64_Msk             /*!< AHB3 Clock divided by 64 */

+#define RCC_CDCFGR1_HPRE_DIV128_Pos             (0U)

+#define RCC_CDCFGR1_HPRE_DIV128_Msk             (0xDUL << RCC_CDCFGR1_HPRE_DIV128_Pos) /*!< 0x0000000D */

+#define RCC_CDCFGR1_HPRE_DIV128                 RCC_CDCFGR1_HPRE_DIV128_Msk            /*!< AHB3 Clock divided by 128 */

+#define RCC_CDCFGR1_HPRE_DIV256_Pos             (1U)

+#define RCC_CDCFGR1_HPRE_DIV256_Msk             (0x7UL << RCC_CDCFGR1_HPRE_DIV256_Pos) /*!< 0x0000000E */

+#define RCC_CDCFGR1_HPRE_DIV256                 RCC_CDCFGR1_HPRE_DIV256_Msk            /*!< AHB3 Clock divided by 256 */

+#define RCC_CDCFGR1_HPRE_DIV512_Pos             (0U)

+#define RCC_CDCFGR1_HPRE_DIV512_Msk             (0xFUL << RCC_CDCFGR1_HPRE_DIV512_Pos) /*!< 0x0000000F */

+#define RCC_CDCFGR1_HPRE_DIV512                 RCC_CDCFGR1_HPRE_DIV512_Msk            /*!< AHB3 Clock divided by 512 */

+

+/*!< D1PPRE configuration */

+#define RCC_CDCFGR1_CDPPRE_Pos                  (4U)

+#define RCC_CDCFGR1_CDPPRE_Msk                  (0x7UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000070 */

+#define RCC_CDCFGR1_CDPPRE                      RCC_CDCFGR1_CDPPRE_Msk                 /*!< CDPRE[2:0] bits (APB3 prescaler) */

+#define RCC_CDCFGR1_CDPPRE_0                    (0x1UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000010 */

+#define RCC_CDCFGR1_CDPPRE_1                    (0x2UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000020 */

+#define RCC_CDCFGR1_CDPPRE_2                    (0x4UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000040 */

+

+#define RCC_CDCFGR1_CDPPRE_DIV1                 ((uint32_t)0x00000000)                 /*!< APB3 clock not divided */

+#define RCC_CDCFGR1_CDPPRE_DIV2_Pos             (6U)

+#define RCC_CDCFGR1_CDPPRE_DIV2_Msk             (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_CDCFGR1_CDPPRE_DIV2                 RCC_CDCFGR1_CDPPRE_DIV2_Msk            /*!< APB3 clock divided by 2 */

+#define RCC_CDCFGR1_CDPPRE_DIV4_Pos             (4U)

+#define RCC_CDCFGR1_CDPPRE_DIV4_Msk             (0x5UL << RCC_CDCFGR1_CDPPRE_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_CDCFGR1_CDPPRE_DIV4                 RCC_CDCFGR1_CDPPRE_DIV4_Msk            /*!< APB3 clock divided by 4 */

+#define RCC_CDCFGR1_CDPPRE_DIV8_Pos             (5U)

+#define RCC_CDCFGR1_CDPPRE_DIV8_Msk             (0x3UL << RCC_CDCFGR1_CDPPRE_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_CDCFGR1_CDPPRE_DIV8                 RCC_CDCFGR1_CDPPRE_DIV8_Msk            /*!< APB3 clock divided by 8 */

+#define RCC_CDCFGR1_CDPPRE_DIV16_Pos            (4U)

+#define RCC_CDCFGR1_CDPPRE_DIV16_Msk            (0x7UL << RCC_CDCFGR1_CDPPRE_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_CDCFGR1_CDPPRE_DIV16                RCC_CDCFGR1_CDPPRE_DIV16_Msk            /*!< APB3 clock divided by 16 */

+

+#define RCC_CDCFGR1_CDCPRE_Pos                  (8U)

+#define RCC_CDCFGR1_CDCPRE_Msk                  (0xFUL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000F00 */

+#define RCC_CDCFGR1_CDCPRE                      RCC_CDCFGR1_CDCPRE_Msk                  /*!< CDCPRE[2:0] bits (Domain 1 Core prescaler) */

+#define RCC_CDCFGR1_CDCPRE_0                    (0x1UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000100 */

+#define RCC_CDCFGR1_CDCPRE_1                    (0x2UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000200 */

+#define RCC_CDCFGR1_CDCPRE_2                    (0x4UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000400 */

+#define RCC_CDCFGR1_CDCPRE_3                    (0x8UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000800 */

+

+#define RCC_CDCFGR1_CDCPRE_DIV1                 ((uint32_t)0x00000000)                  /*!< Domain 1 Core clock not divided */

+#define RCC_CDCFGR1_CDCPRE_DIV2_Pos             (11U)

+#define RCC_CDCFGR1_CDCPRE_DIV2_Msk             (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos)  /*!< 0x00000800 */

+#define RCC_CDCFGR1_CDCPRE_DIV2                 RCC_CDCFGR1_CDCPRE_DIV2_Msk             /*!< Domain 1 Core clock divided by 2 */

+#define RCC_CDCFGR1_CDCPRE_DIV4_Pos             (8U)

+#define RCC_CDCFGR1_CDCPRE_DIV4_Msk             (0x9UL << RCC_CDCFGR1_CDCPRE_DIV4_Pos)  /*!< 0x00000900 */

+#define RCC_CDCFGR1_CDCPRE_DIV4                 RCC_CDCFGR1_CDCPRE_DIV4_Msk             /*!< Domain 1 Core clock divided by 4 */

+#define RCC_CDCFGR1_CDCPRE_DIV8_Pos             (9U)

+#define RCC_CDCFGR1_CDCPRE_DIV8_Msk             (0x5UL << RCC_CDCFGR1_CDCPRE_DIV8_Pos)  /*!< 0x00000A00 */

+#define RCC_CDCFGR1_CDCPRE_DIV8                 RCC_CDCFGR1_CDCPRE_DIV8_Msk             /*!< Domain 1 Core clock divided by 8 */

+#define RCC_CDCFGR1_CDCPRE_DIV16_Pos            (8U)

+#define RCC_CDCFGR1_CDCPRE_DIV16_Msk            (0xBUL << RCC_CDCFGR1_CDCPRE_DIV16_Pos) /*!< 0x00000B00 */

+#define RCC_CDCFGR1_CDCPRE_DIV16                RCC_CDCFGR1_CDCPRE_DIV16_Msk            /*!< Domain 1 Core clock divided by 16 */

+#define RCC_CDCFGR1_CDCPRE_DIV64_Pos            (10U)

+#define RCC_CDCFGR1_CDCPRE_DIV64_Msk            (0x3UL << RCC_CDCFGR1_CDCPRE_DIV64_Pos) /*!< 0x00000C00 */

+#define RCC_CDCFGR1_CDCPRE_DIV64                RCC_CDCFGR1_CDCPRE_DIV64_Msk            /*!< Domain 1 Core clock divided by 64 */

+#define RCC_CDCFGR1_CDCPRE_DIV128_Pos           (8U)

+#define RCC_CDCFGR1_CDCPRE_DIV128_Msk           (0xDUL << RCC_CDCFGR1_CDCPRE_DIV128_Pos)/*!< 0x00000D00 */

+#define RCC_CDCFGR1_CDCPRE_DIV128               RCC_CDCFGR1_CDCPRE_DIV128_Msk           /*!< Domain 1 Core clock divided by 128 */

+#define RCC_CDCFGR1_CDCPRE_DIV256_Pos           (9U)

+#define RCC_CDCFGR1_CDCPRE_DIV256_Msk           (0x7UL << RCC_CDCFGR1_CDCPRE_DIV256_Pos)/*!< 0x00000E00 */

+#define RCC_CDCFGR1_CDCPRE_DIV256               RCC_CDCFGR1_CDCPRE_DIV256_Msk           /*!< Domain 1 Core clock divided by 256 */

+#define RCC_CDCFGR1_CDCPRE_DIV512_Pos           (8U)

+#define RCC_CDCFGR1_CDCPRE_DIV512_Msk           (0xFUL << RCC_CDCFGR1_CDCPRE_DIV512_Pos)/*!< 0x00000F00 */

+#define RCC_CDCFGR1_CDCPRE_DIV512               RCC_CDCFGR1_CDCPRE_DIV512_Msk           /*!< Domain 1 Core clock divided by 512 */

+

+/********************  Bit definition for RCC_CDCFGR2 register  ******************/

+/*!< CDPPRE1 configuration */

+#define RCC_CDCFGR2_CDPPRE1_Pos                 (4U)

+#define RCC_CDCFGR2_CDPPRE1_Msk                 (0x7UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000070 */

+#define RCC_CDCFGR2_CDPPRE1                     RCC_CDCFGR2_CDPPRE1_Msk          /*!< D1PPRE1[2:0] bits (APB1 prescaler) */

+#define RCC_CDCFGR2_CDPPRE1_0                   (0x1UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000010 */

+#define RCC_CDCFGR2_CDPPRE1_1                   (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */

+#define RCC_CDCFGR2_CDPPRE1_2                   (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */

+

+#define RCC_CDCFGR2_CDPPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */

+#define RCC_CDCFGR2_CDPPRE1_DIV2_Pos            (6U)

+#define RCC_CDCFGR2_CDPPRE1_DIV2_Msk            (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_CDCFGR2_CDPPRE1_DIV2                RCC_CDCFGR2_CDPPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */

+#define RCC_CDCFGR2_CDPPRE1_DIV4_Pos            (4U)

+#define RCC_CDCFGR2_CDPPRE1_DIV4_Msk            (0x5UL << RCC_CDCFGR2_CDPPRE1_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_CDCFGR2_CDPPRE1_DIV4                RCC_CDCFGR2_CDPPRE1_DIV4_Msk     /*!< APB1 clock divided by 4 */

+#define RCC_CDCFGR2_CDPPRE1_DIV8_Pos            (5U)

+#define RCC_CDCFGR2_CDPPRE1_DIV8_Msk            (0x3UL << RCC_CDCFGR2_CDPPRE1_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_CDCFGR2_CDPPRE1_DIV8                RCC_CDCFGR2_CDPPRE1_DIV8_Msk     /*!< APB1 clock divided by 8 */

+#define RCC_CDCFGR2_CDPPRE1_DIV16_Pos           (4U)

+#define RCC_CDCFGR2_CDPPRE1_DIV16_Msk           (0x7UL << RCC_CDCFGR2_CDPPRE1_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_CDCFGR2_CDPPRE1_DIV16               RCC_CDCFGR2_CDPPRE1_DIV16_Msk    /*!< APB1 clock divided by 16 */

+

+/*!< CDPPRE2 configuration */

+#define RCC_CDCFGR2_CDPPRE2_Pos                 (8U)

+#define RCC_CDCFGR2_CDPPRE2_Msk                 (0x7UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000700 */

+#define RCC_CDCFGR2_CDPPRE2                     RCC_CDCFGR2_CDPPRE2_Msk          /*!< CDPPRE2[2:0] bits (APB2 prescaler) */

+#define RCC_CDCFGR2_CDPPRE2_0                   (0x1UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000100 */

+#define RCC_CDCFGR2_CDPPRE2_1                   (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */

+#define RCC_CDCFGR2_CDPPRE2_2                   (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */

+

+#define RCC_CDCFGR2_CDPPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */

+#define RCC_CDCFGR2_CDPPRE2_DIV2_Pos            (10U)

+#define RCC_CDCFGR2_CDPPRE2_DIV2_Msk            (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */

+#define RCC_CDCFGR2_CDPPRE2_DIV2                RCC_CDCFGR2_CDPPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */

+#define RCC_CDCFGR2_CDPPRE2_DIV4_Pos            (8U)

+#define RCC_CDCFGR2_CDPPRE2_DIV4_Msk            (0x5UL << RCC_CDCFGR2_CDPPRE2_DIV4_Pos) /*!< 0x00000500 */

+#define RCC_CDCFGR2_CDPPRE2_DIV4                RCC_CDCFGR2_CDPPRE2_DIV4_Msk     /*!< APB2 clock divided by 4 */

+#define RCC_CDCFGR2_CDPPRE2_DIV8_Pos            (9U)

+#define RCC_CDCFGR2_CDPPRE2_DIV8_Msk            (0x3UL << RCC_CDCFGR2_CDPPRE2_DIV8_Pos) /*!< 0x00000600 */

+#define RCC_CDCFGR2_CDPPRE2_DIV8                RCC_CDCFGR2_CDPPRE2_DIV8_Msk     /*!< APB2 clock divided by 8 */

+#define RCC_CDCFGR2_CDPPRE2_DIV16_Pos           (8U)

+#define RCC_CDCFGR2_CDPPRE2_DIV16_Msk           (0x7UL << RCC_CDCFGR2_CDPPRE2_DIV16_Pos) /*!< 0x00000700 */

+#define RCC_CDCFGR2_CDPPRE2_DIV16               RCC_CDCFGR2_CDPPRE2_DIV16_Msk    /*!< APB2 clock divided by 16 */

+

+/********************  Bit definition for RCC_SRDCFGR register  ******************/

+/*!< SRDPPRE configuration */

+#define RCC_SRDCFGR_SRDPPRE_Pos                  (4U)

+#define RCC_SRDCFGR_SRDPPRE_Msk                  (0x7UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000070 */

+#define RCC_SRDCFGR_SRDPPRE                      RCC_SRDCFGR_SRDPPRE_Msk           /*!< SRDPPRE1[2:0] bits (APB4 prescaler) */

+#define RCC_SRDCFGR_SRDPPRE_0                    (0x1UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000010 */

+#define RCC_SRDCFGR_SRDPPRE_1                    (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */

+#define RCC_SRDCFGR_SRDPPRE_2                    (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */

+

+#define RCC_SRDCFGR_SRDPPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */

+#define RCC_SRDCFGR_SRDPPRE_DIV2_Pos             (6U)

+#define RCC_SRDCFGR_SRDPPRE_DIV2_Msk             (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_SRDCFGR_SRDPPRE_DIV2                 RCC_SRDCFGR_SRDPPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */

+#define RCC_SRDCFGR_SRDPPRE_DIV4_Pos             (4U)

+#define RCC_SRDCFGR_SRDPPRE_DIV4_Msk             (0x5UL << RCC_SRDCFGR_SRDPPRE_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_SRDCFGR_SRDPPRE_DIV4                 RCC_SRDCFGR_SRDPPRE_DIV4_Msk      /*!< APB4 clock divided by 4 */

+#define RCC_SRDCFGR_SRDPPRE_DIV8_Pos             (5U)

+#define RCC_SRDCFGR_SRDPPRE_DIV8_Msk             (0x3UL << RCC_SRDCFGR_SRDPPRE_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_SRDCFGR_SRDPPRE_DIV8                 RCC_SRDCFGR_SRDPPRE_DIV8_Msk      /*!< APB4 clock divided by 8 */

+#define RCC_SRDCFGR_SRDPPRE_DIV16_Pos            (4U)

+#define RCC_SRDCFGR_SRDPPRE_DIV16_Msk            (0x7UL << RCC_SRDCFGR_SRDPPRE_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_SRDCFGR_SRDPPRE_DIV16                RCC_SRDCFGR_SRDPPRE_DIV16_Msk     /*!< APB4 clock divided by 16 */

+

+/********************  Bit definition for RCC_PLLCKSELR register  *************/

+

+#define RCC_PLLCKSELR_PLLSRC_Pos               (0U)

+#define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */

+#define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk

+

+#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)

+#define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */

+#define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_HSE_Pos           (1U)

+#define RCC_PLLCKSELR_PLLSRC_HSE_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */

+#define RCC_PLLCKSELR_PLLSRC_HSE               RCC_PLLCKSELR_PLLSRC_HSE_Msk    /*!< HSE source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_NONE_Pos          (0U)

+#define RCC_PLLCKSELR_PLLSRC_NONE_Msk          (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */

+#define RCC_PLLCKSELR_PLLSRC_NONE              RCC_PLLCKSELR_PLLSRC_NONE_Msk   /*!< No source clock selected  */

+

+#define RCC_PLLCKSELR_DIVM1_Pos                (4U)

+#define RCC_PLLCKSELR_DIVM1_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */

+#define RCC_PLLCKSELR_DIVM1                    RCC_PLLCKSELR_DIVM1_Msk

+#define RCC_PLLCKSELR_DIVM1_0                  (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */

+#define RCC_PLLCKSELR_DIVM1_1                  (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */

+#define RCC_PLLCKSELR_DIVM1_2                  (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */

+#define RCC_PLLCKSELR_DIVM1_3                  (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */

+#define RCC_PLLCKSELR_DIVM1_4                  (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */

+#define RCC_PLLCKSELR_DIVM1_5                  (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */

+

+#define RCC_PLLCKSELR_DIVM2_Pos                (12U)

+#define RCC_PLLCKSELR_DIVM2_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */

+#define RCC_PLLCKSELR_DIVM2                    RCC_PLLCKSELR_DIVM2_Msk

+#define RCC_PLLCKSELR_DIVM2_0                  (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */

+#define RCC_PLLCKSELR_DIVM2_1                  (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */

+#define RCC_PLLCKSELR_DIVM2_2                  (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */

+#define RCC_PLLCKSELR_DIVM2_3                  (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */

+#define RCC_PLLCKSELR_DIVM2_4                  (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */

+#define RCC_PLLCKSELR_DIVM2_5                  (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */

+

+#define RCC_PLLCKSELR_DIVM3_Pos                (20U)

+#define RCC_PLLCKSELR_DIVM3_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */

+#define RCC_PLLCKSELR_DIVM3                    RCC_PLLCKSELR_DIVM3_Msk

+#define RCC_PLLCKSELR_DIVM3_0                  (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */

+#define RCC_PLLCKSELR_DIVM3_1                  (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */

+#define RCC_PLLCKSELR_DIVM3_2                  (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */

+#define RCC_PLLCKSELR_DIVM3_3                  (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */

+#define RCC_PLLCKSELR_DIVM3_4                  (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */

+#define RCC_PLLCKSELR_DIVM3_5                  (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */

+

+/********************  Bit definition for RCC_PLLCFGR register  ***************/

+

+#define RCC_PLLCFGR_PLL1FRACEN_Pos             (0U)

+#define RCC_PLLCFGR_PLL1FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */

+#define RCC_PLLCFGR_PLL1FRACEN                 RCC_PLLCFGR_PLL1FRACEN_Msk

+#define RCC_PLLCFGR_PLL1VCOSEL_Pos             (1U)

+#define RCC_PLLCFGR_PLL1VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */

+#define RCC_PLLCFGR_PLL1VCOSEL                 RCC_PLLCFGR_PLL1VCOSEL_Msk

+#define RCC_PLLCFGR_PLL1RGE_Pos                (2U)

+#define RCC_PLLCFGR_PLL1RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */

+#define RCC_PLLCFGR_PLL1RGE                    RCC_PLLCFGR_PLL1RGE_Msk

+#define RCC_PLLCFGR_PLL1RGE_0                  (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL1RGE_1                  (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */

+#define RCC_PLLCFGR_PLL1RGE_2                  (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */

+#define RCC_PLLCFGR_PLL1RGE_3                  (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */

+

+#define RCC_PLLCFGR_PLL2FRACEN_Pos             (4U)

+#define RCC_PLLCFGR_PLL2FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */

+#define RCC_PLLCFGR_PLL2FRACEN                 RCC_PLLCFGR_PLL2FRACEN_Msk

+#define RCC_PLLCFGR_PLL2VCOSEL_Pos             (5U)

+#define RCC_PLLCFGR_PLL2VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */

+#define RCC_PLLCFGR_PLL2VCOSEL                 RCC_PLLCFGR_PLL2VCOSEL_Msk

+#define RCC_PLLCFGR_PLL2RGE_Pos                (6U)

+#define RCC_PLLCFGR_PLL2RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */

+#define RCC_PLLCFGR_PLL2RGE                    RCC_PLLCFGR_PLL2RGE_Msk

+#define RCC_PLLCFGR_PLL2RGE_0                  (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL2RGE_1                  (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */

+#define RCC_PLLCFGR_PLL2RGE_2                  (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */

+#define RCC_PLLCFGR_PLL2RGE_3                  (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */

+

+#define RCC_PLLCFGR_PLL3FRACEN_Pos             (8U)

+#define RCC_PLLCFGR_PLL3FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */

+#define RCC_PLLCFGR_PLL3FRACEN                 RCC_PLLCFGR_PLL3FRACEN_Msk

+#define RCC_PLLCFGR_PLL3VCOSEL_Pos             (9U)

+#define RCC_PLLCFGR_PLL3VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */

+#define RCC_PLLCFGR_PLL3VCOSEL                 RCC_PLLCFGR_PLL3VCOSEL_Msk

+#define RCC_PLLCFGR_PLL3RGE_Pos                (10U)

+#define RCC_PLLCFGR_PLL3RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */

+#define RCC_PLLCFGR_PLL3RGE                    RCC_PLLCFGR_PLL3RGE_Msk

+#define RCC_PLLCFGR_PLL3RGE_0                  (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL3RGE_1                  (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */

+#define RCC_PLLCFGR_PLL3RGE_2                  (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */

+#define RCC_PLLCFGR_PLL3RGE_3                  (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */

+

+#define RCC_PLLCFGR_DIVP1EN_Pos                (16U)

+#define RCC_PLLCFGR_DIVP1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */

+#define RCC_PLLCFGR_DIVP1EN                    RCC_PLLCFGR_DIVP1EN_Msk

+#define RCC_PLLCFGR_DIVQ1EN_Pos                (17U)

+#define RCC_PLLCFGR_DIVQ1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */

+#define RCC_PLLCFGR_DIVQ1EN                    RCC_PLLCFGR_DIVQ1EN_Msk

+#define RCC_PLLCFGR_DIVR1EN_Pos                (18U)

+#define RCC_PLLCFGR_DIVR1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */

+#define RCC_PLLCFGR_DIVR1EN                    RCC_PLLCFGR_DIVR1EN_Msk

+

+#define RCC_PLLCFGR_DIVP2EN_Pos                (19U)

+#define RCC_PLLCFGR_DIVP2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */

+#define RCC_PLLCFGR_DIVP2EN                    RCC_PLLCFGR_DIVP2EN_Msk

+#define RCC_PLLCFGR_DIVQ2EN_Pos                (20U)

+#define RCC_PLLCFGR_DIVQ2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */

+#define RCC_PLLCFGR_DIVQ2EN                    RCC_PLLCFGR_DIVQ2EN_Msk

+#define RCC_PLLCFGR_DIVR2EN_Pos                (21U)

+#define RCC_PLLCFGR_DIVR2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */

+#define RCC_PLLCFGR_DIVR2EN                    RCC_PLLCFGR_DIVR2EN_Msk

+

+#define RCC_PLLCFGR_DIVP3EN_Pos                (22U)

+#define RCC_PLLCFGR_DIVP3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */

+#define RCC_PLLCFGR_DIVP3EN                    RCC_PLLCFGR_DIVP3EN_Msk

+#define RCC_PLLCFGR_DIVQ3EN_Pos                (23U)

+#define RCC_PLLCFGR_DIVQ3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */

+#define RCC_PLLCFGR_DIVQ3EN                    RCC_PLLCFGR_DIVQ3EN_Msk

+#define RCC_PLLCFGR_DIVR3EN_Pos                (24U)

+#define RCC_PLLCFGR_DIVR3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */

+#define RCC_PLLCFGR_DIVR3EN                    RCC_PLLCFGR_DIVR3EN_Msk

+

+

+/********************  Bit definition for RCC_PLL1DIVR register  ***************/

+#define RCC_PLL1DIVR_N1_Pos                    (0U)

+#define RCC_PLL1DIVR_N1_Msk                    (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */

+#define RCC_PLL1DIVR_N1                        RCC_PLL1DIVR_N1_Msk

+#define RCC_PLL1DIVR_P1_Pos                    (9U)

+#define RCC_PLL1DIVR_P1_Msk                    (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL1DIVR_P1                        RCC_PLL1DIVR_P1_Msk

+#define RCC_PLL1DIVR_Q1_Pos                    (16U)

+#define RCC_PLL1DIVR_Q1_Msk                    (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */

+#define RCC_PLL1DIVR_Q1                        RCC_PLL1DIVR_Q1_Msk

+#define RCC_PLL1DIVR_R1_Pos                    (24U)

+#define RCC_PLL1DIVR_R1_Msk                    (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */

+#define RCC_PLL1DIVR_R1                        RCC_PLL1DIVR_R1_Msk

+

+/********************  Bit definition for RCC_PLL1FRACR register  ***************/

+#define RCC_PLL1FRACR_FRACN1_Pos               (3U)

+#define RCC_PLL1FRACR_FRACN1_Msk               (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL1FRACR_FRACN1                   RCC_PLL1FRACR_FRACN1_Msk

+

+/********************  Bit definition for RCC_PLL2DIVR register  ***************/

+#define RCC_PLL2DIVR_N2_Pos                    (0U)

+#define RCC_PLL2DIVR_N2_Msk                    (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */

+#define RCC_PLL2DIVR_N2                        RCC_PLL2DIVR_N2_Msk

+#define RCC_PLL2DIVR_P2_Pos                    (9U)

+#define RCC_PLL2DIVR_P2_Msk                    (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL2DIVR_P2                        RCC_PLL2DIVR_P2_Msk

+#define RCC_PLL2DIVR_Q2_Pos                    (16U)

+#define RCC_PLL2DIVR_Q2_Msk                    (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */

+#define RCC_PLL2DIVR_Q2                        RCC_PLL2DIVR_Q2_Msk

+#define RCC_PLL2DIVR_R2_Pos                    (24U)

+#define RCC_PLL2DIVR_R2_Msk                    (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */

+#define RCC_PLL2DIVR_R2                        RCC_PLL2DIVR_R2_Msk

+

+/********************  Bit definition for RCC_PLL2FRACR register  ***************/

+#define RCC_PLL2FRACR_FRACN2_Pos               (3U)

+#define RCC_PLL2FRACR_FRACN2_Msk               (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL2FRACR_FRACN2                   RCC_PLL2FRACR_FRACN2_Msk

+

+/********************  Bit definition for RCC_PLL3DIVR register  ***************/

+#define RCC_PLL3DIVR_N3_Pos                    (0U)

+#define RCC_PLL3DIVR_N3_Msk                    (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */

+#define RCC_PLL3DIVR_N3                        RCC_PLL3DIVR_N3_Msk

+#define RCC_PLL3DIVR_P3_Pos                    (9U)

+#define RCC_PLL3DIVR_P3_Msk                    (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL3DIVR_P3                        RCC_PLL3DIVR_P3_Msk

+#define RCC_PLL3DIVR_Q3_Pos                    (16U)

+#define RCC_PLL3DIVR_Q3_Msk                    (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */

+#define RCC_PLL3DIVR_Q3                        RCC_PLL3DIVR_Q3_Msk

+#define RCC_PLL3DIVR_R3_Pos                    (24U)

+#define RCC_PLL3DIVR_R3_Msk                    (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */

+#define RCC_PLL3DIVR_R3                        RCC_PLL3DIVR_R3_Msk

+

+/********************  Bit definition for RCC_PLL3FRACR register  ***************/

+#define RCC_PLL3FRACR_FRACN3_Pos               (3U)

+#define RCC_PLL3FRACR_FRACN3_Msk               (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL3FRACR_FRACN3                   RCC_PLL3FRACR_FRACN3_Msk

+

+/********************  Bit definition for RCC_CDCCIPR register  ***************/

+#define RCC_CDCCIPR_FMCSEL_Pos                 (0U)

+#define RCC_CDCCIPR_FMCSEL_Msk                 (0x3UL << RCC_CDCCIPR_FMCSEL_Pos)     /*!< 0x00000003 */

+#define RCC_CDCCIPR_FMCSEL                     RCC_CDCCIPR_FMCSEL_Msk

+#define RCC_CDCCIPR_FMCSEL_0                   (0x1UL << RCC_CDCCIPR_FMCSEL_Pos)     /*!< 0x00000001 */

+#define RCC_CDCCIPR_FMCSEL_1                   (0x2UL << RCC_CDCCIPR_FMCSEL_Pos)     /*!< 0x00000002 */

+#define RCC_CDCCIPR_OCTOSPISEL_Pos             (4U)

+#define RCC_CDCCIPR_OCTOSPISEL_Msk             (0x3UL << RCC_CDCCIPR_OCTOSPISEL_Pos) /*!< 0x00000030 */

+#define RCC_CDCCIPR_OCTOSPISEL                 RCC_CDCCIPR_OCTOSPISEL_Msk

+#define RCC_CDCCIPR_OCTOSPISEL_0               (0x1UL << RCC_CDCCIPR_OCTOSPISEL_Pos) /*!< 0x00000010 */

+#define RCC_CDCCIPR_OCTOSPISEL_1               (0x2UL << RCC_CDCCIPR_OCTOSPISEL_Pos) /*!< 0x00000020 */

+#define RCC_CDCCIPR_SDMMCSEL_Pos               (16U)

+#define RCC_CDCCIPR_SDMMCSEL_Msk               (0x1UL << RCC_CDCCIPR_SDMMCSEL_Pos)   /*!< 0x00010000 */

+#define RCC_CDCCIPR_SDMMCSEL                   RCC_CDCCIPR_SDMMCSEL_Msk

+#define RCC_CDCCIPR_CKPERSEL_Pos               (28U)

+#define RCC_CDCCIPR_CKPERSEL_Msk               (0x3UL << RCC_CDCCIPR_CKPERSEL_Pos)   /*!< 0x30000000 */

+#define RCC_CDCCIPR_CKPERSEL                   RCC_CDCCIPR_CKPERSEL_Msk

+#define RCC_CDCCIPR_CKPERSEL_0                 (0x1UL << RCC_CDCCIPR_CKPERSEL_Pos)   /*!< 0x10000000 */

+#define RCC_CDCCIPR_CKPERSEL_1                 (0x2UL << RCC_CDCCIPR_CKPERSEL_Pos)   /*!< 0x20000000 */

+

+/********************  Bit definition for RCC_CDCCIP1R register  ***************/

+#define RCC_CDCCIP1R_SAI1SEL_Pos               (0U)

+#define RCC_CDCCIP1R_SAI1SEL_Msk               (0x7UL << RCC_CDCCIP1R_SAI1SEL_Pos)   /*!< 0x00000007 */

+#define RCC_CDCCIP1R_SAI1SEL                   RCC_CDCCIP1R_SAI1SEL_Msk

+#define RCC_CDCCIP1R_SAI1SEL_0                 (0x1UL << RCC_CDCCIP1R_SAI1SEL_Pos)   /*!< 0x00000001 */

+#define RCC_CDCCIP1R_SAI1SEL_1                 (0x2UL << RCC_CDCCIP1R_SAI1SEL_Pos)   /*!< 0x00000002 */

+#define RCC_CDCCIP1R_SAI1SEL_2                 (0x4UL << RCC_CDCCIP1R_SAI1SEL_Pos)   /*!< 0x00000004 */

+

+#define RCC_CDCCIP1R_SAI2ASEL_Pos              (6U)

+#define RCC_CDCCIP1R_SAI2ASEL_Msk              (0x7UL << RCC_CDCCIP1R_SAI2ASEL_Pos)  /*!< 0x000001C0 */

+#define RCC_CDCCIP1R_SAI2ASEL                  RCC_CDCCIP1R_SAI2ASEL_Msk

+#define RCC_CDCCIP1R_SAI2ASEL_0                (0x1UL << RCC_CDCCIP1R_SAI2ASEL_Pos)  /*!< 0x00000040 */

+#define RCC_CDCCIP1R_SAI2ASEL_1                (0x2UL << RCC_CDCCIP1R_SAI2ASEL_Pos)  /*!< 0x00000080 */

+#define RCC_CDCCIP1R_SAI2ASEL_2                (0x4UL << RCC_CDCCIP1R_SAI2ASEL_Pos)  /*!< 0x00000100 */

+

+#define RCC_CDCCIP1R_SAI2BSEL_Pos              (9U)

+#define RCC_CDCCIP1R_SAI2BSEL_Msk              (0x7UL << RCC_CDCCIP1R_SAI2BSEL_Pos)  /*!< 0x00000E00 */

+#define RCC_CDCCIP1R_SAI2BSEL                  RCC_CDCCIP1R_SAI2BSEL_Msk

+#define RCC_CDCCIP1R_SAI2BSEL_0                (0x1UL << RCC_CDCCIP1R_SAI2BSEL_Pos)  /*!< 0x00000200 */

+#define RCC_CDCCIP1R_SAI2BSEL_1                (0x2UL << RCC_CDCCIP1R_SAI2BSEL_Pos)  /*!< 0x00000400 */

+#define RCC_CDCCIP1R_SAI2BSEL_2                (0x4UL << RCC_CDCCIP1R_SAI2BSEL_Pos)  /*!< 0x00000800 */

+

+#define RCC_CDCCIP1R_SPI123SEL_Pos             (12U)

+#define RCC_CDCCIP1R_SPI123SEL_Msk             (0x7UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */

+#define RCC_CDCCIP1R_SPI123SEL                 RCC_CDCCIP1R_SPI123SEL_Msk

+#define RCC_CDCCIP1R_SPI123SEL_0               (0x1UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */

+#define RCC_CDCCIP1R_SPI123SEL_1               (0x2UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */

+#define RCC_CDCCIP1R_SPI123SEL_2               (0x4UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */

+

+#define RCC_CDCCIP1R_SPI45SEL_Pos              (16U)

+#define RCC_CDCCIP1R_SPI45SEL_Msk              (0x7UL << RCC_CDCCIP1R_SPI45SEL_Pos)  /*!< 0x00070000 */

+#define RCC_CDCCIP1R_SPI45SEL                  RCC_CDCCIP1R_SPI45SEL_Msk

+#define RCC_CDCCIP1R_SPI45SEL_0                (0x1UL << RCC_CDCCIP1R_SPI45SEL_Pos)  /*!< 0x00010000 */

+#define RCC_CDCCIP1R_SPI45SEL_1                (0x2UL << RCC_CDCCIP1R_SPI45SEL_Pos)  /*!< 0x00020000 */

+#define RCC_CDCCIP1R_SPI45SEL_2                (0x4UL << RCC_CDCCIP1R_SPI45SEL_Pos)  /*!< 0x00040000 */

+

+#define RCC_CDCCIP1R_SPDIFSEL_Pos              (20U)

+#define RCC_CDCCIP1R_SPDIFSEL_Msk              (0x3UL << RCC_CDCCIP1R_SPDIFSEL_Pos)  /*!< 0x00300000 */

+#define RCC_CDCCIP1R_SPDIFSEL                  RCC_CDCCIP1R_SPDIFSEL_Msk

+#define RCC_CDCCIP1R_SPDIFSEL_0                (0x1UL << RCC_CDCCIP1R_SPDIFSEL_Pos)  /*!< 0x00100000 */

+#define RCC_CDCCIP1R_SPDIFSEL_1                (0x2UL << RCC_CDCCIP1R_SPDIFSEL_Pos)  /*!< 0x00200000 */

+

+#define RCC_CDCCIP1R_DFSDM1SEL_Pos             (24U)

+#define RCC_CDCCIP1R_DFSDM1SEL_Msk             (0x1UL << RCC_CDCCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */

+#define RCC_CDCCIP1R_DFSDM1SEL                 RCC_CDCCIP1R_DFSDM1SEL_Msk

+

+#define RCC_CDCCIP1R_FDCANSEL_Pos              (28U)

+#define RCC_CDCCIP1R_FDCANSEL_Msk              (0x3UL << RCC_CDCCIP1R_FDCANSEL_Pos)  /*!< 0x30000000 */

+#define RCC_CDCCIP1R_FDCANSEL                  RCC_CDCCIP1R_FDCANSEL_Msk

+#define RCC_CDCCIP1R_FDCANSEL_0                (0x1UL << RCC_CDCCIP1R_FDCANSEL_Pos)  /*!< 0x10000000 */

+#define RCC_CDCCIP1R_FDCANSEL_1                (0x2UL << RCC_CDCCIP1R_FDCANSEL_Pos)  /*!< 0x20000000 */

+

+#define RCC_CDCCIP1R_SWPSEL_Pos                (31U)

+#define RCC_CDCCIP1R_SWPSEL_Msk                (0x1UL << RCC_CDCCIP1R_SWPSEL_Pos)    /*!< 0x80000000 */

+#define RCC_CDCCIP1R_SWPSEL                    RCC_CDCCIP1R_SWPSEL_Msk

+

+/********************  Bit definition for RCC_CDCCIP2R register  ***************/

+#define RCC_CDCCIP2R_USART234578SEL_Pos        (0U)

+#define RCC_CDCCIP2R_USART234578SEL_Msk        (0x7UL << RCC_CDCCIP2R_USART234578SEL_Pos)   /*!< 0x00000007 */

+#define RCC_CDCCIP2R_USART234578SEL            RCC_CDCCIP2R_USART234578SEL_Msk

+#define RCC_CDCCIP2R_USART234578SEL_0          (0x1UL << RCC_CDCCIP2R_USART234578SEL_Pos)   /*!< 0x00000001 */

+#define RCC_CDCCIP2R_USART234578SEL_1          (0x2UL << RCC_CDCCIP2R_USART234578SEL_Pos)   /*!< 0x00000002 */

+#define RCC_CDCCIP2R_USART234578SEL_2          (0x4UL << RCC_CDCCIP2R_USART234578SEL_Pos)   /*!< 0x00000004 */

+

+#define RCC_CDCCIP2R_USART16910SEL_Pos         (3U)

+#define RCC_CDCCIP2R_USART16910SEL_Msk         (0x7UL << RCC_CDCCIP2R_USART16910SEL_Pos)    /*!< 0x00000038 */

+#define RCC_CDCCIP2R_USART16910SEL             RCC_CDCCIP2R_USART16910SEL_Msk

+#define RCC_CDCCIP2R_USART16910SEL_0           (0x1UL << RCC_CDCCIP2R_USART16910SEL_Pos)    /*!< 0x00000008 */

+#define RCC_CDCCIP2R_USART16910SEL_1           (0x2UL << RCC_CDCCIP2R_USART16910SEL_Pos)    /*!< 0x00000010 */

+#define RCC_CDCCIP2R_USART16910SEL_2           (0x4UL << RCC_CDCCIP2R_USART16910SEL_Pos)    /*!< 0x00000020 */

+

+#define RCC_CDCCIP2R_RNGSEL_Pos                (8U)

+#define RCC_CDCCIP2R_RNGSEL_Msk                (0x3UL << RCC_CDCCIP2R_RNGSEL_Pos)           /*!< 0x00000300 */

+#define RCC_CDCCIP2R_RNGSEL                    RCC_CDCCIP2R_RNGSEL_Msk

+#define RCC_CDCCIP2R_RNGSEL_0                  (0x1UL << RCC_CDCCIP2R_RNGSEL_Pos)           /*!< 0x00000100 */

+#define RCC_CDCCIP2R_RNGSEL_1                  (0x2UL << RCC_CDCCIP2R_RNGSEL_Pos)           /*!< 0x00000200 */

+

+#define RCC_CDCCIP2R_I2C123SEL_Pos             (12U)

+#define RCC_CDCCIP2R_I2C123SEL_Msk             (0x3UL << RCC_CDCCIP2R_I2C123SEL_Pos)        /*!< 0x00003000 */

+#define RCC_CDCCIP2R_I2C123SEL                 RCC_CDCCIP2R_I2C123SEL_Msk

+#define RCC_CDCCIP2R_I2C123SEL_0               (0x1UL << RCC_CDCCIP2R_I2C123SEL_Pos)        /*!< 0x00001000 */

+#define RCC_CDCCIP2R_I2C123SEL_1               (0x2UL << RCC_CDCCIP2R_I2C123SEL_Pos)        /*!< 0x00002000 */

+

+#define RCC_CDCCIP2R_USBSEL_Pos                (20U)

+#define RCC_CDCCIP2R_USBSEL_Msk                (0x3UL << RCC_CDCCIP2R_USBSEL_Pos)           /*!< 0x00300000 */

+#define RCC_CDCCIP2R_USBSEL                    RCC_CDCCIP2R_USBSEL_Msk

+#define RCC_CDCCIP2R_USBSEL_0                  (0x1UL << RCC_CDCCIP2R_USBSEL_Pos)           /*!< 0x00100000 */

+#define RCC_CDCCIP2R_USBSEL_1                  (0x2UL << RCC_CDCCIP2R_USBSEL_Pos)           /*!< 0x00200000 */

+

+#define RCC_CDCCIP2R_CECSEL_Pos                (22U)

+#define RCC_CDCCIP2R_CECSEL_Msk                (0x3UL << RCC_CDCCIP2R_CECSEL_Pos)           /*!< 0x00C00000 */

+#define RCC_CDCCIP2R_CECSEL                    RCC_CDCCIP2R_CECSEL_Msk

+#define RCC_CDCCIP2R_CECSEL_0                  (0x1UL << RCC_CDCCIP2R_CECSEL_Pos)           /*!< 0x00400000 */

+#define RCC_CDCCIP2R_CECSEL_1                  (0x2UL << RCC_CDCCIP2R_CECSEL_Pos)           /*!< 0x00800000 */

+

+#define RCC_CDCCIP2R_LPTIM1SEL_Pos             (28U)

+#define RCC_CDCCIP2R_LPTIM1SEL_Msk             (0x7UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)        /*!< 0x70000000 */

+#define RCC_CDCCIP2R_LPTIM1SEL                 RCC_CDCCIP2R_LPTIM1SEL_Msk

+#define RCC_CDCCIP2R_LPTIM1SEL_0               (0x1UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)        /*!< 0x10000000 */

+#define RCC_CDCCIP2R_LPTIM1SEL_1               (0x2UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)        /*!< 0x20000000 */

+#define RCC_CDCCIP2R_LPTIM1SEL_2               (0x4UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)        /*!< 0x40000000 */

+

+/********************  Bit definition for RCC_SRDCCIPR register  ***************/

+#define RCC_SRDCCIPR_LPUART1SEL_Pos             (0U)

+#define RCC_SRDCCIPR_LPUART1SEL_Msk             (0x7UL << RCC_SRDCCIPR_LPUART1SEL_Pos)      /*!< 0x00000007 */

+#define RCC_SRDCCIPR_LPUART1SEL                 RCC_SRDCCIPR_LPUART1SEL_Msk

+#define RCC_SRDCCIPR_LPUART1SEL_0               (0x1UL << RCC_SRDCCIPR_LPUART1SEL_Pos)      /*!< 0x00000001 */

+#define RCC_SRDCCIPR_LPUART1SEL_1               (0x2UL << RCC_SRDCCIPR_LPUART1SEL_Pos)      /*!< 0x00000002 */

+#define RCC_SRDCCIPR_LPUART1SEL_2               (0x4UL << RCC_SRDCCIPR_LPUART1SEL_Pos)      /*!< 0x00000004 */

+

+#define RCC_SRDCCIPR_I2C4SEL_Pos                (8U)

+#define RCC_SRDCCIPR_I2C4SEL_Msk                (0x3UL << RCC_SRDCCIPR_I2C4SEL_Pos)         /*!< 0x00000300 */

+#define RCC_SRDCCIPR_I2C4SEL                    RCC_SRDCCIPR_I2C4SEL_Msk

+#define RCC_SRDCCIPR_I2C4SEL_0                  (0x1UL << RCC_SRDCCIPR_I2C4SEL_Pos)         /*!< 0x00000100 */

+#define RCC_SRDCCIPR_I2C4SEL_1                  (0x2UL << RCC_SRDCCIPR_I2C4SEL_Pos)         /*!< 0x00000200 */

+

+#define RCC_SRDCCIPR_LPTIM2SEL_Pos              (10U)

+#define RCC_SRDCCIPR_LPTIM2SEL_Msk              (0x7UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)       /*!< 0x00001C00 */

+#define RCC_SRDCCIPR_LPTIM2SEL                  RCC_SRDCCIPR_LPTIM2SEL_Msk

+#define RCC_SRDCCIPR_LPTIM2SEL_0                (0x1UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)       /*!< 0x00000400 */

+#define RCC_SRDCCIPR_LPTIM2SEL_1                (0x2UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)       /*!< 0x00000800 */

+#define RCC_SRDCCIPR_LPTIM2SEL_2                (0x4UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)       /*!< 0x00001000 */

+

+#define RCC_SRDCCIPR_LPTIM3SEL_Pos            (13U)

+#define RCC_SRDCCIPR_LPTIM3SEL_Msk            (0x7UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)         /*!< 0x0000E000 */

+#define RCC_SRDCCIPR_LPTIM3SEL                RCC_SRDCCIPR_LPTIM3SEL_Msk

+#define RCC_SRDCCIPR_LPTIM3SEL_0              (0x1UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)         /*!< 0x00002000 */

+#define RCC_SRDCCIPR_LPTIM3SEL_1              (0x2UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)         /*!< 0x00004000 */

+#define RCC_SRDCCIPR_LPTIM3SEL_2              (0x4UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)         /*!< 0x00008000 */

+

+#define RCC_SRDCCIPR_ADCSEL_Pos                 (16U)

+#define RCC_SRDCCIPR_ADCSEL_Msk                 (0x3UL << RCC_SRDCCIPR_ADCSEL_Pos)          /*!< 0x00030000 */

+#define RCC_SRDCCIPR_ADCSEL                     RCC_SRDCCIPR_ADCSEL_Msk

+#define RCC_SRDCCIPR_ADCSEL_0                   (0x1UL << RCC_SRDCCIPR_ADCSEL_Pos)          /*!< 0x00010000 */

+#define RCC_SRDCCIPR_ADCSEL_1                   (0x2UL << RCC_SRDCCIPR_ADCSEL_Pos)          /*!< 0x00020000 */

+

+#define RCC_SRDCCIPR_DFSDM2SEL_Pos              (27U)

+#define RCC_SRDCCIPR_DFSDM2SEL_Msk              (0x1UL << RCC_SRDCCIPR_DFSDM2SEL_Pos)       /*!< 0x08000000 */

+#define RCC_SRDCCIPR_DFSDM2SEL                   RCC_SRDCCIPR_DFSDM2SEL_Msk

+

+#define RCC_SRDCCIPR_SPI6SEL_Pos                (28U)

+#define RCC_SRDCCIPR_SPI6SEL_Msk                (0x7UL << RCC_SRDCCIPR_SPI6SEL_Pos)         /*!< 0x70000000 */

+#define RCC_SRDCCIPR_SPI6SEL                    RCC_SRDCCIPR_SPI6SEL_Msk

+#define RCC_SRDCCIPR_SPI6SEL_0                  (0x1UL << RCC_SRDCCIPR_SPI6SEL_Pos)         /*!< 0x10000000 */

+#define RCC_SRDCCIPR_SPI6SEL_1                  (0x2UL << RCC_SRDCCIPR_SPI6SEL_Pos)         /*!< 0x20000000 */

+#define RCC_SRDCCIPR_SPI6SEL_2                  (0x4UL << RCC_SRDCCIPR_SPI6SEL_Pos)         /*!< 0x40000000 */

+

+/********************  Bit definition for RCC_CIER register  ******************/

+#define RCC_CIER_LSIRDYIE_Pos                  (0U)

+#define RCC_CIER_LSIRDYIE_Msk                  (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */

+#define RCC_CIER_LSIRDYIE                      RCC_CIER_LSIRDYIE_Msk

+#define RCC_CIER_LSERDYIE_Pos                  (1U)

+#define RCC_CIER_LSERDYIE_Msk                  (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */

+#define RCC_CIER_LSERDYIE                      RCC_CIER_LSERDYIE_Msk

+#define RCC_CIER_HSIRDYIE_Pos                  (2U)

+#define RCC_CIER_HSIRDYIE_Msk                  (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */

+#define RCC_CIER_HSIRDYIE                      RCC_CIER_HSIRDYIE_Msk

+#define RCC_CIER_HSERDYIE_Pos                  (3U)

+#define RCC_CIER_HSERDYIE_Msk                  (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */

+#define RCC_CIER_HSERDYIE                      RCC_CIER_HSERDYIE_Msk

+#define RCC_CIER_CSIRDYIE_Pos                  (4U)

+#define RCC_CIER_CSIRDYIE_Msk                  (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */

+#define RCC_CIER_CSIRDYIE                      RCC_CIER_CSIRDYIE_Msk

+#define RCC_CIER_HSI48RDYIE_Pos                (5U)

+#define RCC_CIER_HSI48RDYIE_Msk                (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */

+#define RCC_CIER_HSI48RDYIE                    RCC_CIER_HSI48RDYIE_Msk

+#define RCC_CIER_PLL1RDYIE_Pos                 (6U)

+#define RCC_CIER_PLL1RDYIE_Msk                 (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */

+#define RCC_CIER_PLL1RDYIE                     RCC_CIER_PLL1RDYIE_Msk

+#define RCC_CIER_PLL2RDYIE_Pos                 (7U)

+#define RCC_CIER_PLL2RDYIE_Msk                 (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */

+#define RCC_CIER_PLL2RDYIE                     RCC_CIER_PLL2RDYIE_Msk

+#define RCC_CIER_PLL3RDYIE_Pos                 (8U)

+#define RCC_CIER_PLL3RDYIE_Msk                 (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */

+#define RCC_CIER_PLL3RDYIE                     RCC_CIER_PLL3RDYIE_Msk

+#define RCC_CIER_LSECSSIE_Pos                  (9U)

+#define RCC_CIER_LSECSSIE_Msk                  (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */

+#define RCC_CIER_LSECSSIE                      RCC_CIER_LSECSSIE_Msk

+

+/********************  Bit definition for RCC_CIFR register  ******************/

+#define RCC_CIFR_LSIRDYF_Pos                   (0U)

+#define RCC_CIFR_LSIRDYF_Msk                   (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */

+#define RCC_CIFR_LSIRDYF                       RCC_CIFR_LSIRDYF_Msk

+#define RCC_CIFR_LSERDYF_Pos                   (1U)

+#define RCC_CIFR_LSERDYF_Msk                   (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */

+#define RCC_CIFR_LSERDYF                       RCC_CIFR_LSERDYF_Msk

+#define RCC_CIFR_HSIRDYF_Pos                   (2U)

+#define RCC_CIFR_HSIRDYF_Msk                   (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */

+#define RCC_CIFR_HSIRDYF                       RCC_CIFR_HSIRDYF_Msk

+#define RCC_CIFR_HSERDYF_Pos                   (3U)

+#define RCC_CIFR_HSERDYF_Msk                   (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */

+#define RCC_CIFR_HSERDYF                       RCC_CIFR_HSERDYF_Msk

+#define RCC_CIFR_CSIRDYF_Pos                   (4U)

+#define RCC_CIFR_CSIRDYF_Msk                   (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */

+#define RCC_CIFR_CSIRDYF                       RCC_CIFR_CSIRDYF_Msk

+#define RCC_CIFR_HSI48RDYF_Pos                 (5U)

+#define RCC_CIFR_HSI48RDYF_Msk                 (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */

+#define RCC_CIFR_HSI48RDYF                     RCC_CIFR_HSI48RDYF_Msk

+#define RCC_CIFR_PLLRDYF_Pos                   (6U)

+#define RCC_CIFR_PLLRDYF_Msk                   (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */

+#define RCC_CIFR_PLLRDYF                       RCC_CIFR_PLLRDYF_Msk

+#define RCC_CIFR_PLL2RDYF_Pos                  (7U)

+#define RCC_CIFR_PLL2RDYF_Msk                  (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */

+#define RCC_CIFR_PLL2RDYF                      RCC_CIFR_PLL2RDYF_Msk

+#define RCC_CIFR_PLL3RDYF_Pos                  (8U)

+#define RCC_CIFR_PLL3RDYF_Msk                  (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */

+#define RCC_CIFR_PLL3RDYF                      RCC_CIFR_PLL3RDYF_Msk

+#define RCC_CIFR_LSECSSF_Pos                   (9U)

+#define RCC_CIFR_LSECSSF_Msk                   (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */

+#define RCC_CIFR_LSECSSF                       RCC_CIFR_LSECSSF_Msk

+#define RCC_CIFR_HSECSSF_Pos                   (10U)

+#define RCC_CIFR_HSECSSF_Msk                   (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */

+#define RCC_CIFR_HSECSSF                       RCC_CIFR_HSECSSF_Msk

+

+/********************  Bit definition for RCC_CICR register  ******************/

+#define RCC_CICR_LSIRDYC_Pos                   (0U)

+#define RCC_CICR_LSIRDYC_Msk                   (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */

+#define RCC_CICR_LSIRDYC                       RCC_CICR_LSIRDYC_Msk

+#define RCC_CICR_LSERDYC_Pos                   (1U)

+#define RCC_CICR_LSERDYC_Msk                   (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */

+#define RCC_CICR_LSERDYC                       RCC_CICR_LSERDYC_Msk

+#define RCC_CICR_HSIRDYC_Pos                   (2U)

+#define RCC_CICR_HSIRDYC_Msk                   (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */

+#define RCC_CICR_HSIRDYC                       RCC_CICR_HSIRDYC_Msk

+#define RCC_CICR_HSERDYC_Pos                   (3U)

+#define RCC_CICR_HSERDYC_Msk                   (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */

+#define RCC_CICR_HSERDYC                       RCC_CICR_HSERDYC_Msk

+#define RCC_CICR_CSIRDYC_Pos                   (4U)

+#define RCC_CICR_CSIRDYC_Msk                   (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */

+#define RCC_CICR_CSIRDYC                       RCC_CICR_CSIRDYC_Msk

+#define RCC_CICR_HSI48RDYC_Pos                 (5U)

+#define RCC_CICR_HSI48RDYC_Msk                 (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */

+#define RCC_CICR_HSI48RDYC                     RCC_CICR_HSI48RDYC_Msk

+#define RCC_CICR_PLLRDYC_Pos                   (6U)

+#define RCC_CICR_PLLRDYC_Msk                   (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */

+#define RCC_CICR_PLLRDYC                       RCC_CICR_PLLRDYC_Msk

+#define RCC_CICR_PLL2RDYC_Pos                  (7U)

+#define RCC_CICR_PLL2RDYC_Msk                  (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */

+#define RCC_CICR_PLL2RDYC                      RCC_CICR_PLL2RDYC_Msk

+#define RCC_CICR_PLL3RDYC_Pos                  (8U)

+#define RCC_CICR_PLL3RDYC_Msk                  (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */

+#define RCC_CICR_PLL3RDYC                      RCC_CICR_PLL3RDYC_Msk

+#define RCC_CICR_LSECSSC_Pos                   (9U)

+#define RCC_CICR_LSECSSC_Msk                   (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */

+#define RCC_CICR_LSECSSC                       RCC_CICR_LSECSSC_Msk

+#define RCC_CICR_HSECSSC_Pos                   (10U)

+#define RCC_CICR_HSECSSC_Msk                   (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */

+#define RCC_CICR_HSECSSC                       RCC_CICR_HSECSSC_Msk

+

+/********************  Bit definition for RCC_BDCR register  ******************/

+#define RCC_BDCR_LSEON_Pos                     (0U)

+#define RCC_BDCR_LSEON_Msk                     (0x1UL << RCC_BDCR_LSEON_Pos)   /*!< 0x00000001 */

+#define RCC_BDCR_LSEON                         RCC_BDCR_LSEON_Msk

+#define RCC_BDCR_LSERDY_Pos                    (1U)

+#define RCC_BDCR_LSERDY_Msk                    (0x1UL << RCC_BDCR_LSERDY_Pos)  /*!< 0x00000002 */

+#define RCC_BDCR_LSERDY                        RCC_BDCR_LSERDY_Msk

+#define RCC_BDCR_LSEBYP_Pos                    (2U)

+#define RCC_BDCR_LSEBYP_Msk                    (0x1UL << RCC_BDCR_LSEBYP_Pos)  /*!< 0x00000004 */

+#define RCC_BDCR_LSEBYP                        RCC_BDCR_LSEBYP_Msk

+

+#define RCC_BDCR_LSEDRV_Pos                    (3U)

+#define RCC_BDCR_LSEDRV_Msk                    (0x3UL << RCC_BDCR_LSEDRV_Pos)  /*!< 0x00000018 */

+#define RCC_BDCR_LSEDRV                        RCC_BDCR_LSEDRV_Msk

+#define RCC_BDCR_LSEDRV_0                      (0x1UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000008 */

+#define RCC_BDCR_LSEDRV_1                      (0x2UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000010 */

+

+#define RCC_BDCR_LSECSSON_Pos                  (5U)

+#define RCC_BDCR_LSECSSON_Msk                  (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */

+#define RCC_BDCR_LSECSSON                      RCC_BDCR_LSECSSON_Msk

+#define RCC_BDCR_LSECSSD_Pos                   (6U)

+#define RCC_BDCR_LSECSSD_Msk                   (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */

+#define RCC_BDCR_LSECSSD                       RCC_BDCR_LSECSSD_Msk

+#define RCC_BDCR_LSEEXT_Pos                    (7U)

+#define RCC_BDCR_LSEEXT_Msk                    (0x1UL << RCC_BDCR_LSEEXT_Pos)  /*!< 0x00000080 */

+#define RCC_BDCR_LSEEXT                        RCC_BDCR_LSEEXT_Msk

+

+#define RCC_BDCR_RTCSEL_Pos                    (8U)

+#define RCC_BDCR_RTCSEL_Msk                    (0x3UL << RCC_BDCR_RTCSEL_Pos)  /*!< 0x00000300 */

+#define RCC_BDCR_RTCSEL                        RCC_BDCR_RTCSEL_Msk

+#define RCC_BDCR_RTCSEL_0                      (0x1UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000100 */

+#define RCC_BDCR_RTCSEL_1                      (0x2UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000200 */

+

+#define RCC_BDCR_RTCEN_Pos                     (15U)

+#define RCC_BDCR_RTCEN_Msk                     (0x1UL << RCC_BDCR_RTCEN_Pos)   /*!< 0x00008000 */

+#define RCC_BDCR_RTCEN                         RCC_BDCR_RTCEN_Msk

+#define RCC_BDCR_VSWRST_Pos                    (16U)

+#define RCC_BDCR_VSWRST_Msk                    (0x1UL << RCC_BDCR_VSWRST_Pos)   /*!< 0x00010000 */

+#define RCC_BDCR_VSWRST                        RCC_BDCR_VSWRST_Msk

+/* Legacy define */

+#define RCC_BDCR_BDRST_Pos                     RCC_BDCR_VSWRST_Pos

+#define RCC_BDCR_BDRST_Msk                     RCC_BDCR_VSWRST_Msk

+#define RCC_BDCR_BDRST                         RCC_BDCR_VSWRST

+/********************  Bit definition for RCC_CSR register  *******************/

+#define RCC_CSR_LSION_Pos                      (0U)

+#define RCC_CSR_LSION_Msk                      (0x1UL << RCC_CSR_LSION_Pos)    /*!< 0x00000001 */

+#define RCC_CSR_LSION                          RCC_CSR_LSION_Msk

+#define RCC_CSR_LSIRDY_Pos                     (1U)

+#define RCC_CSR_LSIRDY_Msk                     (0x1UL << RCC_CSR_LSIRDY_Pos)   /*!< 0x00000002 */

+#define RCC_CSR_LSIRDY                         RCC_CSR_LSIRDY_Msk

+

+

+/********************  Bit definition for RCC_AHB3ENR register  **************/

+#define RCC_AHB3ENR_MDMAEN_Pos                 (0U)

+#define RCC_AHB3ENR_MDMAEN_Msk                 (0x1UL << RCC_AHB3ENR_MDMAEN_Pos)       /*!< 0x00000001 */

+#define RCC_AHB3ENR_MDMAEN                     RCC_AHB3ENR_MDMAEN_Msk

+#define RCC_AHB3ENR_DMA2DEN_Pos                (4U)

+#define RCC_AHB3ENR_DMA2DEN_Msk                (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos)      /*!< 0x00000010 */

+#define RCC_AHB3ENR_DMA2DEN                    RCC_AHB3ENR_DMA2DEN_Msk

+#define RCC_AHB3ENR_JPGDECEN_Pos               (5U)

+#define RCC_AHB3ENR_JPGDECEN_Msk               (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos)     /*!< 0x00000020 */

+#define RCC_AHB3ENR_JPGDECEN                   RCC_AHB3ENR_JPGDECEN_Msk

+#define RCC_AHB3ENR_FMCEN_Pos                  (12U)

+#define RCC_AHB3ENR_FMCEN_Msk                  (0x1UL << RCC_AHB3ENR_FMCEN_Pos)        /*!< 0x00001000 */

+#define RCC_AHB3ENR_FMCEN                      RCC_AHB3ENR_FMCEN_Msk

+#define RCC_AHB3ENR_OSPI1EN_Pos                (14U)

+#define RCC_AHB3ENR_OSPI1EN_Msk                (0x1UL << RCC_AHB3ENR_OSPI1EN_Pos)      /*!< 0x00004000 */

+#define RCC_AHB3ENR_OSPI1EN                    RCC_AHB3ENR_OSPI1EN_Msk

+#define RCC_AHB3ENR_SDMMC1EN_Pos               (16U)

+#define RCC_AHB3ENR_SDMMC1EN_Msk               (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos)     /*!< 0x00010000 */

+#define RCC_AHB3ENR_SDMMC1EN                   RCC_AHB3ENR_SDMMC1EN_Msk

+#define RCC_AHB3ENR_OSPI2EN_Pos                (19U)

+#define RCC_AHB3ENR_OSPI2EN_Msk                (0x1UL << RCC_AHB3ENR_OSPI2EN_Pos)      /*!< 0x00040000 */

+#define RCC_AHB3ENR_OSPI2EN                    RCC_AHB3ENR_OSPI2EN_Msk

+#define RCC_AHB3ENR_IOMNGREN_Pos               (21U)

+#define RCC_AHB3ENR_IOMNGREN_Msk               (0x1UL << RCC_AHB3ENR_IOMNGREN_Pos)     /*!< 0x00100000 */

+#define RCC_AHB3ENR_IOMNGREN                   RCC_AHB3ENR_IOMNGREN_Msk

+#define RCC_AHB3ENR_OTFDEC1EN_Pos              (22U)

+#define RCC_AHB3ENR_OTFDEC1EN_Msk              (0x1UL << RCC_AHB3ENR_OTFDEC1EN_Pos)    /*!< 0x00200000 */

+#define RCC_AHB3ENR_OTFDEC1EN                  RCC_AHB3ENR_OTFDEC1EN_Msk

+#define RCC_AHB3ENR_OTFDEC2EN_Pos              (23U)

+#define RCC_AHB3ENR_OTFDEC2EN_Msk              (0x1UL << RCC_AHB3ENR_OTFDEC2EN_Pos)    /*!< 0x00400000 */

+#define RCC_AHB3ENR_OTFDEC2EN                  RCC_AHB3ENR_OTFDEC2EN_Msk

+#define RCC_AHB3ENR_GFXMMUEN_Pos               (24U)

+#define RCC_AHB3ENR_GFXMMUEN_Msk               (0x1UL << RCC_AHB3ENR_GFXMMUEN_Pos)     /*!< 0x00800000 */

+#define RCC_AHB3ENR_GFXMMUEN                   RCC_AHB3ENR_GFXMMUEN_Msk

+

+/********************  Bit definition for RCC_AHB1ENR register  ***************/

+#define RCC_AHB1ENR_DMA1EN_Pos                 (0U)

+#define RCC_AHB1ENR_DMA1EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)          /*!< 0x00000001 */

+#define RCC_AHB1ENR_DMA1EN                     RCC_AHB1ENR_DMA1EN_Msk

+#define RCC_AHB1ENR_DMA2EN_Pos                 (1U)

+#define RCC_AHB1ENR_DMA2EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)          /*!< 0x00000002 */

+#define RCC_AHB1ENR_DMA2EN                     RCC_AHB1ENR_DMA2EN_Msk

+#define RCC_AHB1ENR_ADC12EN_Pos                (5U)

+#define RCC_AHB1ENR_ADC12EN_Msk                (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)         /*!< 0x00000020 */

+#define RCC_AHB1ENR_ADC12EN                    RCC_AHB1ENR_ADC12EN_Msk

+#define RCC_AHB1ENR_CRCEN_Pos                  (9U)

+#define RCC_AHB1ENR_CRCEN_Msk                  (0x1UL << RCC_AHB1ENR_CRCEN_Pos)           /*!< 0x00000200 */

+#define RCC_AHB1ENR_CRCEN                      RCC_AHB1ENR_CRCEN_Msk

+#define RCC_AHB1ENR_USB1OTGHSEN_Pos            (25U)

+#define RCC_AHB1ENR_USB1OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos)     /*!< 0x02000000 */

+#define RCC_AHB1ENR_USB1OTGHSEN                RCC_AHB1ENR_USB1OTGHSEN_Msk

+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos        (26U)

+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */

+#define RCC_AHB1ENR_USB1OTGHSULPIEN            RCC_AHB1ENR_USB1OTGHSULPIEN_Msk

+

+/********************  Bit definition for RCC_AHB2ENR register  ***************/

+#define RCC_AHB2ENR_DCMI_PSSIEN_Pos            (0U)

+#define RCC_AHB2ENR_DCMI_PSSIEN_Msk            (0x1UL << RCC_AHB2ENR_DCMI_PSSIEN_Pos)     /*!< 0x00000001 */

+#define RCC_AHB2ENR_DCMI_PSSIEN                RCC_AHB2ENR_DCMI_PSSIEN_Msk

+#define RCC_AHB2ENR_HSEMEN_Pos                 (2U)

+#define RCC_AHB2ENR_HSEMEN_Msk                 (0x1UL << RCC_AHB2ENR_HSEMEN_Pos)          /*!< 0x00000004 */

+#define RCC_AHB2ENR_HSEMEN                     RCC_AHB2ENR_HSEMEN_Msk

+#define RCC_AHB2ENR_CRYPEN_Pos                 (4U)

+#define RCC_AHB2ENR_CRYPEN_Msk                 (0x1UL << RCC_AHB2ENR_CRYPEN_Pos)          /*!< 0x00000010 */

+#define RCC_AHB2ENR_CRYPEN                     RCC_AHB2ENR_CRYPEN_Msk

+#define RCC_AHB2ENR_HASHEN_Pos                 (5U)

+#define RCC_AHB2ENR_HASHEN_Msk                 (0x1UL << RCC_AHB2ENR_HASHEN_Pos)          /*!< 0x00000020 */

+#define RCC_AHB2ENR_HASHEN                     RCC_AHB2ENR_HASHEN_Msk

+#define RCC_AHB2ENR_RNGEN_Pos                  (6U)

+#define RCC_AHB2ENR_RNGEN_Msk                  (0x1UL << RCC_AHB2ENR_RNGEN_Pos)           /*!< 0x00000040 */

+#define RCC_AHB2ENR_RNGEN                      RCC_AHB2ENR_RNGEN_Msk

+#define RCC_AHB2ENR_SDMMC2EN_Pos               (9U)

+#define RCC_AHB2ENR_SDMMC2EN_Msk               (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)        /*!< 0x00000200 */

+#define RCC_AHB2ENR_SDMMC2EN                   RCC_AHB2ENR_SDMMC2EN_Msk

+#define RCC_AHB2ENR_BDMA1EN_Pos                (11U)

+#define RCC_AHB2ENR_BDMA1EN_Msk                (0x1UL << RCC_AHB2ENR_BDMA1EN_Pos)         /*!< 0x00000800 */

+#define RCC_AHB2ENR_BDMA1EN                    RCC_AHB2ENR_BDMA1EN_Msk

+#define RCC_AHB2ENR_AHBSRAM1EN_Pos             (29U)

+#define RCC_AHB2ENR_AHBSRAM1EN_Msk             (0x1UL << RCC_AHB2ENR_AHBSRAM1EN_Pos)       /*!< 0x20000000 */

+#define RCC_AHB2ENR_AHBSRAM1EN                 RCC_AHB2ENR_AHBSRAM1EN_Msk

+#define RCC_AHB2ENR_AHBSRAM2EN_Pos             (30U)

+#define RCC_AHB2ENR_AHBSRAM2EN_Msk             (0x1UL << RCC_AHB2ENR_AHBSRAM2EN_Pos)       /*!< 0x40000000 */

+#define RCC_AHB2ENR_AHBSRAM2EN                 RCC_AHB2ENR_AHBSRAM2EN_Msk

+

+/* Legacy define */

+#define RCC_AHB2ENR_DCMIEN_Pos                 RCC_AHB2ENR_DCMI_PSSIEN_Pos

+#define RCC_AHB2ENR_DCMIEN_Msk                 RCC_AHB2ENR_DCMI_PSSIEN_Msk

+#define RCC_AHB2ENR_DCMIEN                     RCC_AHB2ENR_DCMI_PSSIEN

+

+/********************  Bit definition for RCC_AHB4ENR register  ******************/

+#define RCC_AHB4ENR_GPIOAEN_Pos                (0U)

+#define RCC_AHB4ENR_GPIOAEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)         /*!< 0x00000001 */

+#define RCC_AHB4ENR_GPIOAEN                    RCC_AHB4ENR_GPIOAEN_Msk

+#define RCC_AHB4ENR_GPIOBEN_Pos                (1U)

+#define RCC_AHB4ENR_GPIOBEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)         /*!< 0x00000002 */

+#define RCC_AHB4ENR_GPIOBEN                    RCC_AHB4ENR_GPIOBEN_Msk

+#define RCC_AHB4ENR_GPIOCEN_Pos                (2U)

+#define RCC_AHB4ENR_GPIOCEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)         /*!< 0x00000004 */

+#define RCC_AHB4ENR_GPIOCEN                    RCC_AHB4ENR_GPIOCEN_Msk

+#define RCC_AHB4ENR_GPIODEN_Pos                (3U)

+#define RCC_AHB4ENR_GPIODEN_Msk                (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)         /*!< 0x00000008 */

+#define RCC_AHB4ENR_GPIODEN                    RCC_AHB4ENR_GPIODEN_Msk

+#define RCC_AHB4ENR_GPIOEEN_Pos                (4U)

+#define RCC_AHB4ENR_GPIOEEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)         /*!< 0x00000010 */

+#define RCC_AHB4ENR_GPIOEEN                    RCC_AHB4ENR_GPIOEEN_Msk

+#define RCC_AHB4ENR_GPIOFEN_Pos                (5U)

+#define RCC_AHB4ENR_GPIOFEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)         /*!< 0x00000020 */

+#define RCC_AHB4ENR_GPIOFEN                    RCC_AHB4ENR_GPIOFEN_Msk

+#define RCC_AHB4ENR_GPIOGEN_Pos                (6U)

+#define RCC_AHB4ENR_GPIOGEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)         /*!< 0x00000040 */

+#define RCC_AHB4ENR_GPIOGEN                    RCC_AHB4ENR_GPIOGEN_Msk

+#define RCC_AHB4ENR_GPIOHEN_Pos                (7U)

+#define RCC_AHB4ENR_GPIOHEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)         /*!< 0x00000080 */

+#define RCC_AHB4ENR_GPIOHEN                    RCC_AHB4ENR_GPIOHEN_Msk

+#define RCC_AHB4ENR_GPIOIEN_Pos                (8U)

+#define RCC_AHB4ENR_GPIOIEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos)         /*!< 0x00000100 */

+#define RCC_AHB4ENR_GPIOIEN                    RCC_AHB4ENR_GPIOIEN_Msk

+#define RCC_AHB4ENR_GPIOJEN_Pos                (9U)

+#define RCC_AHB4ENR_GPIOJEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos)         /*!< 0x00000200 */

+#define RCC_AHB4ENR_GPIOJEN                    RCC_AHB4ENR_GPIOJEN_Msk

+#define RCC_AHB4ENR_GPIOKEN_Pos                (10U)

+#define RCC_AHB4ENR_GPIOKEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos)         /*!< 0x00000400 */

+#define RCC_AHB4ENR_GPIOKEN                    RCC_AHB4ENR_GPIOKEN_Msk

+#define RCC_AHB4ENR_BDMA2EN_Pos                (21U)

+#define RCC_AHB4ENR_BDMA2EN_Msk                (0x1UL << RCC_AHB4ENR_BDMA2EN_Pos)         /*!< 0x00080000 */

+#define RCC_AHB4ENR_BDMA2EN                    RCC_AHB4ENR_BDMA2EN_Msk

+#define RCC_AHB4ENR_BKPRAMEN_Pos               (28U)

+#define RCC_AHB4ENR_BKPRAMEN_Msk               (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)        /*!< 0x10000000 */

+#define RCC_AHB4ENR_BKPRAMEN                   RCC_AHB4ENR_BKPRAMEN_Msk

+#define RCC_AHB4ENR_SRDSRAMEN_Pos              (29U)

+#define RCC_AHB4ENR_SRDSRAMEN_Msk              (0x1UL << RCC_AHB4ENR_SRDSRAMEN_Pos)       /*!< 0x20000000 */

+#define RCC_AHB4ENR_SRDSRAMEN                  RCC_AHB4ENR_SRDSRAMEN_Msk

+

+/********************  Bit definition for RCC_APB3ENR register  ******************/

+#define RCC_APB3ENR_LTDCEN_Pos                 (3U)

+#define RCC_APB3ENR_LTDCEN_Msk                 (0x1UL << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */

+#define RCC_APB3ENR_LTDCEN                     RCC_APB3ENR_LTDCEN_Msk

+#define RCC_APB3ENR_WWDGEN_Pos                 (6U)

+#define RCC_APB3ENR_WWDGEN_Msk                 (0x1UL << RCC_APB3ENR_WWDGEN_Pos) /*!< 0x00000040 */

+#define RCC_APB3ENR_WWDGEN                     RCC_APB3ENR_WWDGEN_Msk

+

+/* Legacy define */

+#define RCC_APB3ENR_WWDG1EN_Pos                 RCC_APB3ENR_WWDGEN_Pos

+#define RCC_APB3ENR_WWDG1EN_Msk                 RCC_APB3ENR_WWDGEN_Msk

+#define RCC_APB3ENR_WWDG1EN                     RCC_APB3ENR_WWDGEN

+/********************  Bit definition for RCC_APB1LENR register  ******************/

+

+#define RCC_APB1LENR_TIM2EN_Pos                (0U)

+#define RCC_APB1LENR_TIM2EN_Msk                (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */

+#define RCC_APB1LENR_TIM2EN                    RCC_APB1LENR_TIM2EN_Msk

+#define RCC_APB1LENR_TIM3EN_Pos                (1U)

+#define RCC_APB1LENR_TIM3EN_Msk                (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */

+#define RCC_APB1LENR_TIM3EN                    RCC_APB1LENR_TIM3EN_Msk

+#define RCC_APB1LENR_TIM4EN_Pos                (2U)

+#define RCC_APB1LENR_TIM4EN_Msk                (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */

+#define RCC_APB1LENR_TIM4EN                    RCC_APB1LENR_TIM4EN_Msk

+#define RCC_APB1LENR_TIM5EN_Pos                (3U)

+#define RCC_APB1LENR_TIM5EN_Msk                (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */

+#define RCC_APB1LENR_TIM5EN                    RCC_APB1LENR_TIM5EN_Msk

+#define RCC_APB1LENR_TIM6EN_Pos                (4U)

+#define RCC_APB1LENR_TIM6EN_Msk                (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */

+#define RCC_APB1LENR_TIM6EN                    RCC_APB1LENR_TIM6EN_Msk

+#define RCC_APB1LENR_TIM7EN_Pos                (5U)

+#define RCC_APB1LENR_TIM7EN_Msk                (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */

+#define RCC_APB1LENR_TIM7EN                    RCC_APB1LENR_TIM7EN_Msk

+#define RCC_APB1LENR_TIM12EN_Pos               (6U)

+#define RCC_APB1LENR_TIM12EN_Msk               (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */

+#define RCC_APB1LENR_TIM12EN                   RCC_APB1LENR_TIM12EN_Msk

+#define RCC_APB1LENR_TIM13EN_Pos               (7U)

+#define RCC_APB1LENR_TIM13EN_Msk               (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */

+#define RCC_APB1LENR_TIM13EN                   RCC_APB1LENR_TIM13EN_Msk

+#define RCC_APB1LENR_TIM14EN_Pos               (8U)

+#define RCC_APB1LENR_TIM14EN_Msk               (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */

+#define RCC_APB1LENR_TIM14EN                   RCC_APB1LENR_TIM14EN_Msk

+#define RCC_APB1LENR_LPTIM1EN_Pos              (9U)

+#define RCC_APB1LENR_LPTIM1EN_Msk              (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */

+#define RCC_APB1LENR_LPTIM1EN                  RCC_APB1LENR_LPTIM1EN_Msk

+

+

+#define RCC_APB1LENR_SPI2EN_Pos                (14U)

+#define RCC_APB1LENR_SPI2EN_Msk                (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */

+#define RCC_APB1LENR_SPI2EN                    RCC_APB1LENR_SPI2EN_Msk

+#define RCC_APB1LENR_SPI3EN_Pos                (15U)

+#define RCC_APB1LENR_SPI3EN_Msk                (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */

+#define RCC_APB1LENR_SPI3EN                    RCC_APB1LENR_SPI3EN_Msk

+#define RCC_APB1LENR_SPDIFRXEN_Pos             (16U)

+#define RCC_APB1LENR_SPDIFRXEN_Msk             (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */

+#define RCC_APB1LENR_SPDIFRXEN                 RCC_APB1LENR_SPDIFRXEN_Msk

+#define RCC_APB1LENR_USART2EN_Pos              (17U)

+#define RCC_APB1LENR_USART2EN_Msk              (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */

+#define RCC_APB1LENR_USART2EN                  RCC_APB1LENR_USART2EN_Msk

+#define RCC_APB1LENR_USART3EN_Pos              (18U)

+#define RCC_APB1LENR_USART3EN_Msk              (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */

+#define RCC_APB1LENR_USART3EN                  RCC_APB1LENR_USART3EN_Msk

+#define RCC_APB1LENR_UART4EN_Pos               (19U)

+#define RCC_APB1LENR_UART4EN_Msk               (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */

+#define RCC_APB1LENR_UART4EN                   RCC_APB1LENR_UART4EN_Msk

+#define RCC_APB1LENR_UART5EN_Pos               (20U)

+#define RCC_APB1LENR_UART5EN_Msk               (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */

+#define RCC_APB1LENR_UART5EN                   RCC_APB1LENR_UART5EN_Msk

+#define RCC_APB1LENR_I2C1EN_Pos                (21U)

+#define RCC_APB1LENR_I2C1EN_Msk                (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */

+#define RCC_APB1LENR_I2C1EN                    RCC_APB1LENR_I2C1EN_Msk

+#define RCC_APB1LENR_I2C2EN_Pos                (22U)

+#define RCC_APB1LENR_I2C2EN_Msk                (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */

+#define RCC_APB1LENR_I2C2EN                    RCC_APB1LENR_I2C2EN_Msk

+#define RCC_APB1LENR_I2C3EN_Pos                (23U)

+#define RCC_APB1LENR_I2C3EN_Msk                (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */

+#define RCC_APB1LENR_I2C3EN                    RCC_APB1LENR_I2C3EN_Msk

+#define RCC_APB1LENR_CECEN_Pos                 (27U)

+#define RCC_APB1LENR_CECEN_Msk                 (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */

+#define RCC_APB1LENR_CECEN                     RCC_APB1LENR_CECEN_Msk

+#define RCC_APB1LENR_DAC12EN_Pos               (29U)

+#define RCC_APB1LENR_DAC12EN_Msk               (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */

+#define RCC_APB1LENR_DAC12EN                   RCC_APB1LENR_DAC12EN_Msk

+#define RCC_APB1LENR_UART7EN_Pos               (30U)

+#define RCC_APB1LENR_UART7EN_Msk               (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */

+#define RCC_APB1LENR_UART7EN                   RCC_APB1LENR_UART7EN_Msk

+#define RCC_APB1LENR_UART8EN_Pos               (31U)

+#define RCC_APB1LENR_UART8EN_Msk               (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */

+#define RCC_APB1LENR_UART8EN                   RCC_APB1LENR_UART8EN_Msk

+

+/* Legacy define */

+#define RCC_APB1LENR_HDMICECEN_Pos             RCC_APB1LENR_CECEN_Pos

+#define RCC_APB1LENR_HDMICECEN_Msk             RCC_APB1LENR_CECEN_Msk

+#define RCC_APB1LENR_HDMICECEN                 RCC_APB1LENR_CECEN

+/********************  Bit definition for RCC_APB1HENR register  ******************/

+#define RCC_APB1HENR_CRSEN_Pos                 (1U)

+#define RCC_APB1HENR_CRSEN_Msk                 (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1HENR_CRSEN                     RCC_APB1HENR_CRSEN_Msk

+#define RCC_APB1HENR_SWPMIEN_Pos               (2U)

+#define RCC_APB1HENR_SWPMIEN_Msk               (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1HENR_SWPMIEN                   RCC_APB1HENR_SWPMIEN_Msk

+#define RCC_APB1HENR_OPAMPEN_Pos               (4U)

+#define RCC_APB1HENR_OPAMPEN_Msk               (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1HENR_OPAMPEN                   RCC_APB1HENR_OPAMPEN_Msk

+#define RCC_APB1HENR_MDIOSEN_Pos               (5U)

+#define RCC_APB1HENR_MDIOSEN_Msk               (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1HENR_MDIOSEN                   RCC_APB1HENR_MDIOSEN_Msk

+#define RCC_APB1HENR_FDCANEN_Pos               (8U)

+#define RCC_APB1HENR_FDCANEN_Msk               (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1HENR_FDCANEN                   RCC_APB1HENR_FDCANEN_Msk

+

+/********************  Bit definition for RCC_APB2ENR register  ******************/

+#define RCC_APB2ENR_TIM1EN_Pos                 (0U)

+#define RCC_APB2ENR_TIM1EN_Msk                 (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */

+#define RCC_APB2ENR_TIM1EN                     RCC_APB2ENR_TIM1EN_Msk

+#define RCC_APB2ENR_TIM8EN_Pos                 (1U)

+#define RCC_APB2ENR_TIM8EN_Msk                 (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */

+#define RCC_APB2ENR_TIM8EN                     RCC_APB2ENR_TIM8EN_Msk

+#define RCC_APB2ENR_USART1EN_Pos               (4U)

+#define RCC_APB2ENR_USART1EN_Msk               (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */

+#define RCC_APB2ENR_USART1EN                   RCC_APB2ENR_USART1EN_Msk

+#define RCC_APB2ENR_USART6EN_Pos               (5U)

+#define RCC_APB2ENR_USART6EN_Msk               (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */

+#define RCC_APB2ENR_USART6EN                   RCC_APB2ENR_USART6EN_Msk

+#define RCC_APB2ENR_UART9EN_Pos                (6U)

+#define RCC_APB2ENR_UART9EN_Msk                (0x1UL << RCC_APB2ENR_UART9EN_Pos) /*!< 0x00000040 */

+#define RCC_APB2ENR_UART9EN                    RCC_APB2ENR_UART9EN_Msk

+#define RCC_APB2ENR_USART10EN_Pos              (7U)

+#define RCC_APB2ENR_USART10EN_Msk              (0x1UL << RCC_APB2ENR_USART10EN_Pos) /*!< 0x00000080 */

+#define RCC_APB2ENR_USART10EN                   RCC_APB2ENR_USART10EN_Msk

+#define RCC_APB2ENR_SPI1EN_Pos                 (12U)

+#define RCC_APB2ENR_SPI1EN_Msk                 (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */

+#define RCC_APB2ENR_SPI1EN                     RCC_APB2ENR_SPI1EN_Msk

+#define RCC_APB2ENR_SPI4EN_Pos                 (13U)

+#define RCC_APB2ENR_SPI4EN_Msk                 (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */

+#define RCC_APB2ENR_SPI4EN                     RCC_APB2ENR_SPI4EN_Msk

+#define RCC_APB2ENR_TIM15EN_Pos                (16U)

+#define RCC_APB2ENR_TIM15EN_Msk                (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */

+#define RCC_APB2ENR_TIM15EN                    RCC_APB2ENR_TIM15EN_Msk

+#define RCC_APB2ENR_TIM16EN_Pos                (17U)

+#define RCC_APB2ENR_TIM16EN_Msk                (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */

+#define RCC_APB2ENR_TIM16EN                    RCC_APB2ENR_TIM16EN_Msk

+#define RCC_APB2ENR_TIM17EN_Pos                (18U)

+#define RCC_APB2ENR_TIM17EN_Msk                (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */

+#define RCC_APB2ENR_TIM17EN                    RCC_APB2ENR_TIM17EN_Msk

+#define RCC_APB2ENR_SPI5EN_Pos                 (20U)

+#define RCC_APB2ENR_SPI5EN_Msk                 (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */

+#define RCC_APB2ENR_SPI5EN                     RCC_APB2ENR_SPI5EN_Msk

+#define RCC_APB2ENR_SAI1EN_Pos                 (22U)

+#define RCC_APB2ENR_SAI1EN_Msk                 (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */

+#define RCC_APB2ENR_SAI1EN                     RCC_APB2ENR_SAI1EN_Msk

+#define RCC_APB2ENR_SAI2EN_Pos                 (23U)

+#define RCC_APB2ENR_SAI2EN_Msk                 (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */

+#define RCC_APB2ENR_SAI2EN                     RCC_APB2ENR_SAI2EN_Msk

+#define RCC_APB2ENR_DFSDM1EN_Pos               (30U)

+#define RCC_APB2ENR_DFSDM1EN_Msk               (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x40000000 */

+#define RCC_APB2ENR_DFSDM1EN                   RCC_APB2ENR_DFSDM1EN_Msk

+

+/********************  Bit definition for RCC_APB4ENR register  ******************/

+#define RCC_APB4ENR_SYSCFGEN_Pos               (1U)

+#define RCC_APB4ENR_SYSCFGEN_Msk               (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */

+#define RCC_APB4ENR_SYSCFGEN                   RCC_APB4ENR_SYSCFGEN_Msk

+#define RCC_APB4ENR_LPUART1EN_Pos              (3U)

+#define RCC_APB4ENR_LPUART1EN_Msk              (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */

+#define RCC_APB4ENR_LPUART1EN                  RCC_APB4ENR_LPUART1EN_Msk

+#define RCC_APB4ENR_SPI6EN_Pos                 (5U)

+#define RCC_APB4ENR_SPI6EN_Msk                 (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */

+#define RCC_APB4ENR_SPI6EN                     RCC_APB4ENR_SPI6EN_Msk

+#define RCC_APB4ENR_I2C4EN_Pos                 (7U)

+#define RCC_APB4ENR_I2C4EN_Msk                 (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */

+#define RCC_APB4ENR_I2C4EN                     RCC_APB4ENR_I2C4EN_Msk

+#define RCC_APB4ENR_LPTIM2EN_Pos               (9U)

+#define RCC_APB4ENR_LPTIM2EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */

+#define RCC_APB4ENR_LPTIM2EN                   RCC_APB4ENR_LPTIM2EN_Msk

+#define RCC_APB4ENR_LPTIM3EN_Pos               (10U)

+#define RCC_APB4ENR_LPTIM3EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */

+#define RCC_APB4ENR_LPTIM3EN                   RCC_APB4ENR_LPTIM3EN_Msk

+#define RCC_APB4ENR_DAC2EN_Pos                 (13U)

+#define RCC_APB4ENR_DAC2EN_Msk                 (0x1UL << RCC_APB4ENR_DAC2EN_Pos) /*!< 0x00002000 */

+#define RCC_APB4ENR_DAC2EN                     RCC_APB4ENR_DAC2EN_Msk

+#define RCC_APB4ENR_COMP12EN_Pos               (14U)

+#define RCC_APB4ENR_COMP12EN_Msk               (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */

+#define RCC_APB4ENR_COMP12EN                   RCC_APB4ENR_COMP12EN_Msk

+#define RCC_APB4ENR_VREFEN_Pos                 (15U)

+#define RCC_APB4ENR_VREFEN_Msk                 (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */

+#define RCC_APB4ENR_VREFEN                     RCC_APB4ENR_VREFEN_Msk

+#define RCC_APB4ENR_RTCAPBEN_Pos               (16U)

+#define RCC_APB4ENR_RTCAPBEN_Msk               (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */

+#define RCC_APB4ENR_RTCAPBEN                   RCC_APB4ENR_RTCAPBEN_Msk

+

+#define RCC_APB4ENR_DTSEN_Pos                  (26U)

+#define RCC_APB4ENR_DTSEN_Msk                  (0x1UL << RCC_APB4ENR_DTSEN_Pos) /*!< 0x04000000 */

+#define RCC_APB4ENR_DTSEN                      RCC_APB4ENR_DTSEN_Msk

+#define RCC_APB4ENR_DFSDM2EN_Pos               (27U)

+#define RCC_APB4ENR_DFSDM2EN_Msk               (0x1UL << RCC_APB4ENR_DFSDM2EN_Pos) /*!< 0x08000000 */

+#define RCC_APB4ENR_DFSDM2EN                   RCC_APB4ENR_DFSDM2EN_Msk

+

+/********************  Bit definition for RCC_AHB3RSTR register  ***************/

+#define RCC_AHB3RSTR_MDMARST_Pos               (0U)

+#define RCC_AHB3RSTR_MDMARST_Msk               (0x1UL << RCC_AHB3RSTR_MDMARST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB3RSTR_MDMARST                   RCC_AHB3RSTR_MDMARST_Msk

+#define RCC_AHB3RSTR_DMA2DRST_Pos              (4U)

+#define RCC_AHB3RSTR_DMA2DRST_Msk              (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos)     /*!< 0x00000010 */

+#define RCC_AHB3RSTR_DMA2DRST                  RCC_AHB3RSTR_DMA2DRST_Msk

+#define RCC_AHB3RSTR_JPGDECRST_Pos             (5U)

+#define RCC_AHB3RSTR_JPGDECRST_Msk             (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos)    /*!< 0x00000020 */

+#define RCC_AHB3RSTR_JPGDECRST                 RCC_AHB3RSTR_JPGDECRST_Msk

+#define RCC_AHB3RSTR_FMCRST_Pos                (12U)

+#define RCC_AHB3RSTR_FMCRST_Msk                (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)      /*!< 0x00001000 */

+#define RCC_AHB3RSTR_FMCRST                    RCC_AHB3RSTR_FMCRST_Msk

+#define RCC_AHB3RSTR_OSPI1RST_Pos              (14U)

+#define RCC_AHB3RSTR_OSPI1RST_Msk              (0x1UL << RCC_AHB3RSTR_OSPI1RST_Pos)    /*!< 0x00004000 */

+#define RCC_AHB3RSTR_OSPI1RST                   RCC_AHB3RSTR_OSPI1RST_Msk

+#define RCC_AHB3RSTR_SDMMC1RST_Pos             (16U)

+#define RCC_AHB3RSTR_SDMMC1RST_Msk             (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos)   /*!< 0x00010000 */

+#define RCC_AHB3RSTR_SDMMC1RST                 RCC_AHB3RSTR_SDMMC1RST_Msk

+#define RCC_AHB3RSTR_OSPI2RST_Pos              (19U)

+#define RCC_AHB3RSTR_OSPI2RST_Msk              (0x1UL << RCC_AHB3RSTR_OSPI2RST_Pos)    /*!< 0x00008000 */

+#define RCC_AHB3RSTR_OSPI2RST                  RCC_AHB3RSTR_OSPI2RST_Msk

+#define RCC_AHB3RSTR_IOMNGRRST_Pos             (21U)

+#define RCC_AHB3RSTR_IOMNGRRST_Msk             (0x1UL << RCC_AHB3RSTR_IOMNGRRST_Pos)   /*!< 0x00020000 */

+#define RCC_AHB3RSTR_IOMNGRRST                 RCC_AHB3RSTR_IOMNGRRST_Msk

+#define RCC_AHB3RSTR_OTFDEC1RST_Pos            (22U)

+#define RCC_AHB3RSTR_OTFDEC1RST_Msk            (0x1UL << RCC_AHB3RSTR_OTFDEC1RST_Pos)  /*!< 0x00040000 */

+#define RCC_AHB3RSTR_OTFDEC1RST                RCC_AHB3RSTR_OTFDEC1RST_Msk

+#define RCC_AHB3RSTR_OTFDEC2RST_Pos            (23U)

+#define RCC_AHB3RSTR_OTFDEC2RST_Msk            (0x1UL << RCC_AHB3RSTR_OTFDEC2RST_Pos)  /*!< 0x00080000 */

+#define RCC_AHB3RSTR_OTFDEC2RST                RCC_AHB3RSTR_OTFDEC2RST_Msk

+#define RCC_AHB3RSTR_GFXMMURST_Pos             (24U)

+#define RCC_AHB3RSTR_GFXMMURST_Msk             (0x1UL << RCC_AHB3RSTR_GFXMMURST_Pos)   /*!< 0x00100000 */

+#define RCC_AHB3RSTR_GFXMMURST                 RCC_AHB3RSTR_GFXMMURST_Msk

+

+

+/********************  Bit definition for RCC_AHB1RSTR register  ***************/

+#define RCC_AHB1RSTR_DMA1RST_Pos               (0U)

+#define RCC_AHB1RSTR_DMA1RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB1RSTR_DMA1RST                   RCC_AHB1RSTR_DMA1RST_Msk

+#define RCC_AHB1RSTR_DMA2RST_Pos               (1U)

+#define RCC_AHB1RSTR_DMA2RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)      /*!< 0x00000002 */

+#define RCC_AHB1RSTR_DMA2RST                   RCC_AHB1RSTR_DMA2RST_Msk

+#define RCC_AHB1RSTR_ADC12RST_Pos              (5U)

+#define RCC_AHB1RSTR_ADC12RST_Msk              (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)     /*!< 0x00000020 */

+#define RCC_AHB1RSTR_ADC12RST                  RCC_AHB1RSTR_ADC12RST_Msk

+#define RCC_AHB1RSTR_CRCRST_Pos                (9U)

+#define RCC_AHB1RSTR_CRCRST_Msk                (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)       /*!< 0x00000200 */

+#define RCC_AHB1RSTR_CRCRST                    RCC_AHB1RSTR_CRCRST_Msk

+#define RCC_AHB1RSTR_USB1OTGHSRST_Pos          (25U)

+#define RCC_AHB1RSTR_USB1OTGHSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */

+#define RCC_AHB1RSTR_USB1OTGHSRST              RCC_AHB1RSTR_USB1OTGHSRST_Msk

+

+/********************  Bit definition for RCC_AHB2RSTR register  ***************/

+#define RCC_AHB2RSTR_DCMI_PSSIRST_Pos          (0U)

+#define RCC_AHB2RSTR_DCMI_PSSIRST_Msk          (0x1UL << RCC_AHB2RSTR_DCMI_PSSIRST_Pos)  /*!< 0x00000001 */

+#define RCC_AHB2RSTR_DCMI_PSSIRST              RCC_AHB2RSTR_DCMI_PSSIRST_Msk

+#define RCC_AHB2RSTR_HSEMRST_Pos               (2U)

+#define RCC_AHB2RSTR_HSEMRST_Msk               (0x1UL << RCC_AHB2RSTR_HSEMRST_Pos)       /*!< 0x00000004 */

+#define RCC_AHB2RSTR_HSEMRST                   RCC_AHB2RSTR_HSEMRST_Msk

+#define RCC_AHB2RSTR_CRYPRST_Pos               (4U)

+#define RCC_AHB2RSTR_CRYPRST_Msk               (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos)       /*!< 0x00000010 */

+#define RCC_AHB2RSTR_CRYPRST                   RCC_AHB2RSTR_CRYPRST_Msk

+#define RCC_AHB2RSTR_HASHRST_Pos               (5U)

+#define RCC_AHB2RSTR_HASHRST_Msk               (0x1UL << RCC_AHB2RSTR_HASHRST_Pos)       /*!< 0x00000020 */

+#define RCC_AHB2RSTR_HASHRST                   RCC_AHB2RSTR_HASHRST_Msk

+#define RCC_AHB2RSTR_RNGRST_Pos                (6U)

+#define RCC_AHB2RSTR_RNGRST_Msk                (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)        /*!< 0x00000040 */

+#define RCC_AHB2RSTR_RNGRST                    RCC_AHB2RSTR_RNGRST_Msk

+#define RCC_AHB2RSTR_SDMMC2RST_Pos             (9U)

+#define RCC_AHB2RSTR_SDMMC2RST_Msk             (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)     /*!< 0x00000200 */

+#define RCC_AHB2RSTR_SDMMC2RST                 RCC_AHB2RSTR_SDMMC2RST_Msk

+#define RCC_AHB2RSTR_BDMA1RST_Pos              (11U)

+#define RCC_AHB2RSTR_BDMA1RST_Msk              (0x1UL << RCC_AHB2RSTR_BDMA1RST_Pos)      /*!< 0x00000200 */

+#define RCC_AHB2RSTR_BDMA1RST                  RCC_AHB2RSTR_BDMA1RST_Msk

+

+/* Legacy define */

+#define RCC_AHB2RSTR_DCMIRST_Pos               RCC_AHB2RSTR_DCMI_PSSIRST_Pos

+#define RCC_AHB2RSTR_DCMIRST_Msk               RCC_AHB2RSTR_DCMI_PSSIRST_Msk

+#define RCC_AHB2RSTR_DCMIRST                   RCC_AHB2RSTR_DCMI_PSSIRST

+/********************  Bit definition for RCC_AHB4RSTR register  ******************/

+#define RCC_AHB4RSTR_GPIOARST_Pos              (0U)

+#define RCC_AHB4RSTR_GPIOARST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB4RSTR_GPIOARST                  RCC_AHB4RSTR_GPIOARST_Msk

+#define RCC_AHB4RSTR_GPIOBRST_Pos              (1U)

+#define RCC_AHB4RSTR_GPIOBRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)      /*!< 0x00000002 */

+#define RCC_AHB4RSTR_GPIOBRST                  RCC_AHB4RSTR_GPIOBRST_Msk

+#define RCC_AHB4RSTR_GPIOCRST_Pos              (2U)

+#define RCC_AHB4RSTR_GPIOCRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)      /*!< 0x00000004 */

+#define RCC_AHB4RSTR_GPIOCRST                  RCC_AHB4RSTR_GPIOCRST_Msk

+#define RCC_AHB4RSTR_GPIODRST_Pos              (3U)

+#define RCC_AHB4RSTR_GPIODRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)      /*!< 0x00000008 */

+#define RCC_AHB4RSTR_GPIODRST                  RCC_AHB4RSTR_GPIODRST_Msk

+#define RCC_AHB4RSTR_GPIOERST_Pos              (4U)

+#define RCC_AHB4RSTR_GPIOERST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)      /*!< 0x00000010 */

+#define RCC_AHB4RSTR_GPIOERST                  RCC_AHB4RSTR_GPIOERST_Msk

+#define RCC_AHB4RSTR_GPIOFRST_Pos              (5U)

+#define RCC_AHB4RSTR_GPIOFRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)       /*!< 0x00000020 */

+#define RCC_AHB4RSTR_GPIOFRST                  RCC_AHB4RSTR_GPIOFRST_Msk

+#define RCC_AHB4RSTR_GPIOGRST_Pos              (6U)

+#define RCC_AHB4RSTR_GPIOGRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)       /*!< 0x00000040 */

+#define RCC_AHB4RSTR_GPIOGRST                  RCC_AHB4RSTR_GPIOGRST_Msk

+#define RCC_AHB4RSTR_GPIOHRST_Pos              (7U)

+#define RCC_AHB4RSTR_GPIOHRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)       /*!< 0x00000080 */

+#define RCC_AHB4RSTR_GPIOHRST                  RCC_AHB4RSTR_GPIOHRST_Msk

+#define RCC_AHB4RSTR_GPIOIRST_Pos              (8U)

+#define RCC_AHB4RSTR_GPIOIRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos)       /*!< 0x00000100 */

+#define RCC_AHB4RSTR_GPIOIRST                  RCC_AHB4RSTR_GPIOIRST_Msk

+#define RCC_AHB4RSTR_GPIOJRST_Pos              (9U)

+#define RCC_AHB4RSTR_GPIOJRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos)       /*!< 0x00000200 */

+#define RCC_AHB4RSTR_GPIOJRST                  RCC_AHB4RSTR_GPIOJRST_Msk

+#define RCC_AHB4RSTR_GPIOKRST_Pos              (10U)

+#define RCC_AHB4RSTR_GPIOKRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos)       /*!< 0x00000400 */

+#define RCC_AHB4RSTR_GPIOKRST                  RCC_AHB4RSTR_GPIOKRST_Msk

+#define RCC_AHB4RSTR_BDMA2RST_Pos              (21U)

+#define RCC_AHB4RSTR_BDMA2RST_Msk              (0x1UL << RCC_AHB4RSTR_BDMA2RST_Pos)       /*!< 0x00200000 */

+#define RCC_AHB4RSTR_BDMA2RST                   RCC_AHB4RSTR_BDMA2RST_Msk

+

+

+/********************  Bit definition for RCC_APB3RSTR register  ******************/

+#define RCC_APB3RSTR_LTDCRST_Pos               (3U)

+#define RCC_APB3RSTR_LTDCRST_Msk               (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */

+#define RCC_APB3RSTR_LTDCRST                   RCC_APB3RSTR_LTDCRST_Msk

+

+/********************  Bit definition for RCC_APB1LRSTR register  ******************/

+

+#define RCC_APB1LRSTR_TIM2RST_Pos              (0U)

+#define RCC_APB1LRSTR_TIM2RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */

+#define RCC_APB1LRSTR_TIM2RST                  RCC_APB1LRSTR_TIM2RST_Msk

+#define RCC_APB1LRSTR_TIM3RST_Pos              (1U)

+#define RCC_APB1LRSTR_TIM3RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */

+#define RCC_APB1LRSTR_TIM3RST                  RCC_APB1LRSTR_TIM3RST_Msk

+#define RCC_APB1LRSTR_TIM4RST_Pos              (2U)

+#define RCC_APB1LRSTR_TIM4RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */

+#define RCC_APB1LRSTR_TIM4RST                  RCC_APB1LRSTR_TIM4RST_Msk

+#define RCC_APB1LRSTR_TIM5RST_Pos              (3U)

+#define RCC_APB1LRSTR_TIM5RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */

+#define RCC_APB1LRSTR_TIM5RST                  RCC_APB1LRSTR_TIM5RST_Msk

+#define RCC_APB1LRSTR_TIM6RST_Pos              (4U)

+#define RCC_APB1LRSTR_TIM6RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */

+#define RCC_APB1LRSTR_TIM6RST                  RCC_APB1LRSTR_TIM6RST_Msk

+#define RCC_APB1LRSTR_TIM7RST_Pos              (5U)

+#define RCC_APB1LRSTR_TIM7RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */

+#define RCC_APB1LRSTR_TIM7RST                  RCC_APB1LRSTR_TIM7RST_Msk

+#define RCC_APB1LRSTR_TIM12RST_Pos             (6U)

+#define RCC_APB1LRSTR_TIM12RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */

+#define RCC_APB1LRSTR_TIM12RST                 RCC_APB1LRSTR_TIM12RST_Msk

+#define RCC_APB1LRSTR_TIM13RST_Pos             (7U)

+#define RCC_APB1LRSTR_TIM13RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */

+#define RCC_APB1LRSTR_TIM13RST                 RCC_APB1LRSTR_TIM13RST_Msk

+#define RCC_APB1LRSTR_TIM14RST_Pos             (8U)

+#define RCC_APB1LRSTR_TIM14RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */

+#define RCC_APB1LRSTR_TIM14RST                 RCC_APB1LRSTR_TIM14RST_Msk

+#define RCC_APB1LRSTR_LPTIM1RST_Pos            (9U)

+#define RCC_APB1LRSTR_LPTIM1RST_Msk            (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */

+#define RCC_APB1LRSTR_LPTIM1RST                RCC_APB1LRSTR_LPTIM1RST_Msk

+#define RCC_APB1LRSTR_SPI2RST_Pos              (14U)

+#define RCC_APB1LRSTR_SPI2RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */

+#define RCC_APB1LRSTR_SPI2RST                  RCC_APB1LRSTR_SPI2RST_Msk

+#define RCC_APB1LRSTR_SPI3RST_Pos              (15U)

+#define RCC_APB1LRSTR_SPI3RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */

+#define RCC_APB1LRSTR_SPI3RST                  RCC_APB1LRSTR_SPI3RST_Msk

+#define RCC_APB1LRSTR_SPDIFRXRST_Pos           (16U)

+#define RCC_APB1LRSTR_SPDIFRXRST_Msk           (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */

+#define RCC_APB1LRSTR_SPDIFRXRST               RCC_APB1LRSTR_SPDIFRXRST_Msk

+#define RCC_APB1LRSTR_USART2RST_Pos            (17U)

+#define RCC_APB1LRSTR_USART2RST_Msk            (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */

+#define RCC_APB1LRSTR_USART2RST                RCC_APB1LRSTR_USART2RST_Msk

+#define RCC_APB1LRSTR_USART3RST_Pos            (18U)

+#define RCC_APB1LRSTR_USART3RST_Msk            (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */

+#define RCC_APB1LRSTR_USART3RST                RCC_APB1LRSTR_USART3RST_Msk

+#define RCC_APB1LRSTR_UART4RST_Pos             (19U)

+#define RCC_APB1LRSTR_UART4RST_Msk             (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */

+#define RCC_APB1LRSTR_UART4RST                 RCC_APB1LRSTR_UART4RST_Msk

+#define RCC_APB1LRSTR_UART5RST_Pos             (20U)

+#define RCC_APB1LRSTR_UART5RST_Msk             (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */

+#define RCC_APB1LRSTR_UART5RST                 RCC_APB1LRSTR_UART5RST_Msk

+#define RCC_APB1LRSTR_I2C1RST_Pos              (21U)

+#define RCC_APB1LRSTR_I2C1RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */

+#define RCC_APB1LRSTR_I2C1RST                  RCC_APB1LRSTR_I2C1RST_Msk

+#define RCC_APB1LRSTR_I2C2RST_Pos              (22U)

+#define RCC_APB1LRSTR_I2C2RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */

+#define RCC_APB1LRSTR_I2C2RST                  RCC_APB1LRSTR_I2C2RST_Msk

+#define RCC_APB1LRSTR_I2C3RST_Pos              (23U)

+#define RCC_APB1LRSTR_I2C3RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */

+#define RCC_APB1LRSTR_I2C3RST                  RCC_APB1LRSTR_I2C3RST_Msk

+#define RCC_APB1LRSTR_CECRST_Pos               (27U)

+#define RCC_APB1LRSTR_CECRST_Msk               (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */

+#define RCC_APB1LRSTR_CECRST                   RCC_APB1LRSTR_CECRST_Msk

+#define RCC_APB1LRSTR_DAC12RST_Pos             (29U)

+#define RCC_APB1LRSTR_DAC12RST_Msk             (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */

+#define RCC_APB1LRSTR_DAC12RST                 RCC_APB1LRSTR_DAC12RST_Msk

+#define RCC_APB1LRSTR_UART7RST_Pos             (30U)

+#define RCC_APB1LRSTR_UART7RST_Msk             (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */

+#define RCC_APB1LRSTR_UART7RST                 RCC_APB1LRSTR_UART7RST_Msk

+#define RCC_APB1LRSTR_UART8RST_Pos             (31U)

+#define RCC_APB1LRSTR_UART8RST_Msk             (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */

+#define RCC_APB1LRSTR_UART8RST                 RCC_APB1LRSTR_UART8RST_Msk

+

+/* Legacy define */

+#define RCC_APB1LRSTR_HDMICECRST_Pos           RCC_APB1LRSTR_CECRST_Pos

+#define RCC_APB1LRSTR_HDMICECRST_Msk           RCC_APB1LRSTR_CECRST_Msk

+#define RCC_APB1LRSTR_HDMICECRST               RCC_APB1LRSTR_CECRST

+/********************  Bit definition for RCC_APB1HRSTR register  ******************/

+#define RCC_APB1HRSTR_CRSRST_Pos               (1U)

+#define RCC_APB1HRSTR_CRSRST_Msk               (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */

+#define RCC_APB1HRSTR_CRSRST                   RCC_APB1HRSTR_CRSRST_Msk

+#define RCC_APB1HRSTR_SWPMIRST_Pos             (2U)

+#define RCC_APB1HRSTR_SWPMIRST_Msk             (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */

+#define RCC_APB1HRSTR_SWPMIRST                 RCC_APB1HRSTR_SWPMIRST_Msk

+#define RCC_APB1HRSTR_OPAMPRST_Pos             (4U)

+#define RCC_APB1HRSTR_OPAMPRST_Msk             (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */

+#define RCC_APB1HRSTR_OPAMPRST                 RCC_APB1HRSTR_OPAMPRST_Msk

+#define RCC_APB1HRSTR_MDIOSRST_Pos             (5U)

+#define RCC_APB1HRSTR_MDIOSRST_Msk             (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */

+#define RCC_APB1HRSTR_MDIOSRST                 RCC_APB1HRSTR_MDIOSRST_Msk

+#define RCC_APB1HRSTR_FDCANRST_Pos             (8U)

+#define RCC_APB1HRSTR_FDCANRST_Msk             (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */

+#define RCC_APB1HRSTR_FDCANRST                 RCC_APB1HRSTR_FDCANRST_Msk

+

+/********************  Bit definition for RCC_APB2RSTR register  ******************/

+#define RCC_APB2RSTR_TIM1RST_Pos               (0U)

+#define RCC_APB2RSTR_TIM1RST_Msk               (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */

+#define RCC_APB2RSTR_TIM1RST                   RCC_APB2RSTR_TIM1RST_Msk

+#define RCC_APB2RSTR_TIM8RST_Pos               (1U)

+#define RCC_APB2RSTR_TIM8RST_Msk               (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */

+#define RCC_APB2RSTR_TIM8RST                   RCC_APB2RSTR_TIM8RST_Msk

+#define RCC_APB2RSTR_USART1RST_Pos             (4U)

+#define RCC_APB2RSTR_USART1RST_Msk             (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */

+#define RCC_APB2RSTR_USART1RST                 RCC_APB2RSTR_USART1RST_Msk

+#define RCC_APB2RSTR_USART6RST_Pos             (5U)

+#define RCC_APB2RSTR_USART6RST_Msk             (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */

+#define RCC_APB2RSTR_USART6RST                 RCC_APB2RSTR_USART6RST_Msk

+#define RCC_APB2RSTR_UART9RST_Pos              (6U)

+#define RCC_APB2RSTR_UART9RST_Msk              (0x1UL << RCC_APB2RSTR_UART9RST_Pos) /*!< 0x00000040 */

+#define RCC_APB2RSTR_UART9RST                  RCC_APB2RSTR_UART9RST_Msk

+#define RCC_APB2RSTR_USART10RST_Pos            (7U)

+#define RCC_APB2RSTR_USART10RST_Msk            (0x1UL << RCC_APB2RSTR_USART10RST_Pos) /*!< 0x00000080 */

+#define RCC_APB2RSTR_USART10RST                RCC_APB2RSTR_USART10RST_Msk

+#define RCC_APB2RSTR_SPI1RST_Pos               (12U)

+#define RCC_APB2RSTR_SPI1RST_Msk               (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */

+#define RCC_APB2RSTR_SPI1RST                   RCC_APB2RSTR_SPI1RST_Msk

+#define RCC_APB2RSTR_SPI4RST_Pos               (13U)

+#define RCC_APB2RSTR_SPI4RST_Msk               (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */

+#define RCC_APB2RSTR_SPI4RST                   RCC_APB2RSTR_SPI4RST_Msk

+#define RCC_APB2RSTR_TIM15RST_Pos              (16U)

+#define RCC_APB2RSTR_TIM15RST_Msk              (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */

+#define RCC_APB2RSTR_TIM15RST                  RCC_APB2RSTR_TIM15RST_Msk

+#define RCC_APB2RSTR_TIM16RST_Pos              (17U)

+#define RCC_APB2RSTR_TIM16RST_Msk              (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */

+#define RCC_APB2RSTR_TIM16RST                  RCC_APB2RSTR_TIM16RST_Msk

+#define RCC_APB2RSTR_TIM17RST_Pos              (18U)

+#define RCC_APB2RSTR_TIM17RST_Msk              (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */

+#define RCC_APB2RSTR_TIM17RST                  RCC_APB2RSTR_TIM17RST_Msk

+#define RCC_APB2RSTR_SPI5RST_Pos               (20U)

+#define RCC_APB2RSTR_SPI5RST_Msk               (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */

+#define RCC_APB2RSTR_SPI5RST                   RCC_APB2RSTR_SPI5RST_Msk

+#define RCC_APB2RSTR_SAI1RST_Pos               (22U)

+#define RCC_APB2RSTR_SAI1RST_Msk               (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */

+#define RCC_APB2RSTR_SAI1RST                   RCC_APB2RSTR_SAI1RST_Msk

+#define RCC_APB2RSTR_SAI2RST_Pos               (23U)

+#define RCC_APB2RSTR_SAI2RST_Msk               (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */

+#define RCC_APB2RSTR_SAI2RST                   RCC_APB2RSTR_SAI2RST_Msk

+#define RCC_APB2RSTR_DFSDM1RST_Pos             (30U)

+#define RCC_APB2RSTR_DFSDM1RST_Msk             (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */

+#define RCC_APB2RSTR_DFSDM1RST                 RCC_APB2RSTR_DFSDM1RST_Msk

+

+/********************  Bit definition for RCC_APB4RSTR register  ******************/

+#define RCC_APB4RSTR_SYSCFGRST_Pos             (1U)

+#define RCC_APB4RSTR_SYSCFGRST_Msk             (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */

+#define RCC_APB4RSTR_SYSCFGRST                 RCC_APB4RSTR_SYSCFGRST_Msk

+#define RCC_APB4RSTR_LPUART1RST_Pos            (3U)

+#define RCC_APB4RSTR_LPUART1RST_Msk            (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */

+#define RCC_APB4RSTR_LPUART1RST                RCC_APB4RSTR_LPUART1RST_Msk

+#define RCC_APB4RSTR_SPI6RST_Pos               (5U)

+#define RCC_APB4RSTR_SPI6RST_Msk               (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */

+#define RCC_APB4RSTR_SPI6RST                   RCC_APB4RSTR_SPI6RST_Msk

+#define RCC_APB4RSTR_I2C4RST_Pos               (7U)

+#define RCC_APB4RSTR_I2C4RST_Msk               (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */

+#define RCC_APB4RSTR_I2C4RST                   RCC_APB4RSTR_I2C4RST_Msk

+#define RCC_APB4RSTR_LPTIM2RST_Pos             (9U)

+#define RCC_APB4RSTR_LPTIM2RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */

+#define RCC_APB4RSTR_LPTIM2RST                 RCC_APB4RSTR_LPTIM2RST_Msk

+#define RCC_APB4RSTR_LPTIM3RST_Pos             (10U)

+#define RCC_APB4RSTR_LPTIM3RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */

+#define RCC_APB4RSTR_LPTIM3RST                 RCC_APB4RSTR_LPTIM3RST_Msk

+#define RCC_APB4RSTR_DAC2RST_Pos               (13U)

+#define RCC_APB4RSTR_DAC2RST_Msk               (0x1UL << RCC_APB4RSTR_DAC2RST_Pos) /*!< 0x00001000 */

+#define RCC_APB4RSTR_DAC2RST                    RCC_APB4RSTR_DAC2RST_Msk

+#define RCC_APB4RSTR_COMP12RST_Pos             (14U)

+#define RCC_APB4RSTR_COMP12RST_Msk             (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */

+#define RCC_APB4RSTR_COMP12RST                 RCC_APB4RSTR_COMP12RST_Msk

+#define RCC_APB4RSTR_VREFRST_Pos               (15U)

+#define RCC_APB4RSTR_VREFRST_Msk               (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */

+#define RCC_APB4RSTR_VREFRST                   RCC_APB4RSTR_VREFRST_Msk

+

+#define RCC_APB4RSTR_DTSRST_Pos                (26U)

+#define RCC_APB4RSTR_DTSRST_Msk                (0x1UL << RCC_APB4RSTR_DTSRST_Pos) /*!< 0x04000000 */

+#define RCC_APB4RSTR_DTSRST                    RCC_APB4RSTR_DTSRST_Msk

+#define RCC_APB4RSTR_DFSDM2RST_Pos             (27U)

+#define RCC_APB4RSTR_DFSDM2RST_Msk             (0x1UL << RCC_APB4RSTR_DFSDM2RST_Pos) /*!< 0x08000000 */

+#define RCC_APB4RSTR_DFSDM2RST                 RCC_APB4RSTR_DFSDM2RST_Msk

+

+

+/********************  Bit definition for RCC_SRDAMR register  ********************/

+#define RCC_SRDAMR_BDMA2AMEN_Pos               (0U)

+#define RCC_SRDAMR_BDMA2AMEN_Msk               (0x1UL << RCC_SRDAMR_BDMA2AMEN_Pos) /*!< 0x00000001 */

+#define RCC_SRDAMR_BDMA2AMEN                   RCC_SRDAMR_BDMA2AMEN_Msk

+#define RCC_SRDAMR_GPIOAMEN_Pos                (1U)

+#define RCC_SRDAMR_GPIOAMEN_Msk                (0x1UL << RCC_SRDAMR_GPIOAMEN_Pos) /*!< 0x00000001 */

+#define RCC_SRDAMR_GPIOAMEN                    RCC_SRDAMR_GPIOAMEN_Msk

+#define RCC_SRDAMR_LPUART1AMEN_Pos             (3U)

+#define RCC_SRDAMR_LPUART1AMEN_Msk             (0x1UL << RCC_SRDAMR_LPUART1AMEN_Pos) /*!< 0x00000008 */

+#define RCC_SRDAMR_LPUART1AMEN                 RCC_SRDAMR_LPUART1AMEN_Msk

+#define RCC_SRDAMR_SPI6AMEN_Pos                (5U)

+#define RCC_SRDAMR_SPI6AMEN_Msk                (0x1UL << RCC_SRDAMR_SPI6AMEN_Pos) /*!< 0x00000020 */

+#define RCC_SRDAMR_SPI6AMEN                    RCC_SRDAMR_SPI6AMEN_Msk

+#define RCC_SRDAMR_I2C4AMEN_Pos                (7U)

+#define RCC_SRDAMR_I2C4AMEN_Msk                (0x1UL << RCC_SRDAMR_I2C4AMEN_Pos) /*!< 0x00000080 */

+#define RCC_SRDAMR_I2C4AMEN                    RCC_SRDAMR_I2C4AMEN_Msk

+#define RCC_SRDAMR_LPTIM2AMEN_Pos              (9U)

+#define RCC_SRDAMR_LPTIM2AMEN_Msk              (0x1UL << RCC_SRDAMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */

+#define RCC_SRDAMR_LPTIM2AMEN                  RCC_SRDAMR_LPTIM2AMEN_Msk

+#define RCC_SRDAMR_LPTIM3AMEN_Pos              (10U)

+#define RCC_SRDAMR_LPTIM3AMEN_Msk              (0x1UL << RCC_SRDAMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */

+#define RCC_SRDAMR_LPTIM3AMEN                  RCC_SRDAMR_LPTIM3AMEN_Msk

+#define RCC_SRDAMR_DAC2AMEN_Pos                (13U)

+#define RCC_SRDAMR_DAC2AMEN_Msk                (0x1UL << RCC_SRDAMR_DAC2AMEN_Pos) /*!< 0x00004000 */

+#define RCC_SRDAMR_DAC2AMEN                    RCC_SRDAMR_DAC2AMEN_Msk

+#define RCC_SRDAMR_COMP12AMEN_Pos              (14U)

+#define RCC_SRDAMR_COMP12AMEN_Msk              (0x1UL << RCC_SRDAMR_COMP12AMEN_Pos) /*!< 0x00004000 */

+#define RCC_SRDAMR_COMP12AMEN                  RCC_SRDAMR_COMP12AMEN_Msk

+#define RCC_SRDAMR_VREFAMEN_Pos                (15U)

+#define RCC_SRDAMR_VREFAMEN_Msk                (0x1UL << RCC_SRDAMR_VREFAMEN_Pos) /*!< 0x00008000 */

+#define RCC_SRDAMR_VREFAMEN                     RCC_SRDAMR_VREFAMEN_Msk

+#define RCC_SRDAMR_RTCAMEN_Pos                 (16U)

+#define RCC_SRDAMR_RTCAMEN_Msk                 (0x1UL << RCC_SRDAMR_RTCAMEN_Pos) /*!< 0x00010000 */

+#define RCC_SRDAMR_RTCAMEN                     RCC_SRDAMR_RTCAMEN_Msk

+#define RCC_SRDAMR_DTSAMEN_Pos                 (26U)

+#define RCC_SRDAMR_DTSAMEN_Msk                 (0x1UL << RCC_SRDAMR_DTSAMEN_Pos) /*!< 0x04000000 */

+#define RCC_SRDAMR_DTSAMEN                     RCC_SRDAMR_DTSAMEN_Msk

+#define RCC_SRDAMR_DFSDM2AMEN_Pos              (27U)

+#define RCC_SRDAMR_DFSDM2AMEN_Msk              (0x1UL << RCC_SRDAMR_DFSDM2AMEN_Pos) /*!< 0x20000000 */

+#define RCC_SRDAMR_DFSDM2AMEN                   RCC_SRDAMR_DFSDM2AMEN_Msk

+#define RCC_SRDAMR_BKPRAMAMEN_Pos              (28U)

+#define RCC_SRDAMR_BKPRAMAMEN_Msk              (0x1UL << RCC_SRDAMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */

+#define RCC_SRDAMR_BKPRAMAMEN                  RCC_SRDAMR_BKPRAMAMEN_Msk

+#define RCC_SRDAMR_SRDSRAMAMEN_Pos             (29U)

+#define RCC_SRDAMR_SRDSRAMAMEN_Msk             (0x1UL << RCC_SRDAMR_SRDSRAMAMEN_Pos) /*!< 0x20000000 */

+#define RCC_SRDAMR_SRDSRAMAMEN                  RCC_SRDAMR_SRDSRAMAMEN_Msk

+/********************  Bit definition for RCC_CKGAENR register  ********************/

+#define RCC_CKGAENR_AXICKG_Pos                 (0U)

+#define RCC_CKGAENR_AXICKG_Msk                 (0x1UL << RCC_CKGAENR_AXICKG_Pos) /*!< 0x00000001 */

+#define RCC_CKGAENR_AXICKG                      RCC_CKGAENR_AXICKG_Msk

+#define RCC_CKGAENR_AHBCKG_Pos                 (1U)

+#define RCC_CKGAENR_AHBCKG_Msk                 (0x1UL << RCC_CKGAENR_AHBCKG_Pos) /*!< 0x00000002 */

+#define RCC_CKGAENR_AHBCKG                     RCC_CKGAENR_AHBCKG_Msk

+#define RCC_CKGAENR_CPUCKG_Pos                 (2U)

+#define RCC_CKGAENR_CPUCKG_Msk                 (0x1UL << RCC_CKGAENR_CPUCKG_Pos) /*!< 0x00000004 */

+#define RCC_CKGAENR_CPUCKG                     RCC_CKGAENR_CPUCKG_Msk

+#define RCC_CKGAENR_SDMMCCKG_Pos               (3U)

+#define RCC_CKGAENR_SDMMCCKG_Msk               (0x1UL << RCC_CKGAENR_SDMMCCKG_Pos) /*!< 0x00000008 */

+#define RCC_CKGAENR_SDMMCCKG                    RCC_CKGAENR_SDMMCCKG_Msk

+#define RCC_CKGAENR_MDMACKG_Pos                (4U)

+#define RCC_CKGAENR_MDMACKG_Msk                (0x1UL << RCC_CKGAENR_MDMACKG_Pos) /*!< 0x00000010 */

+#define RCC_CKGAENR_MDMACKG                    RCC_CKGAENR_MDMACKG_Msk

+#define RCC_CKGAENR_DMA2DCKG_Pos               (5U)

+#define RCC_CKGAENR_DMA2DCKG_Msk               (0x1UL << RCC_CKGAENR_DMA2DCKG_Pos) /*!< 0x00000020 */

+#define RCC_CKGAENR_DMA2DCKG                    RCC_CKGAENR_DMA2DCKG_Msk

+#define RCC_CKGAENR_LTDCCKG_Pos                (6U)

+#define RCC_CKGAENR_LTDCCKG_Msk                (0x1UL << RCC_CKGAENR_LTDCCKG_Pos) /*!< 0x00000040 */

+#define RCC_CKGAENR_LTDCCKG                    RCC_CKGAENR_LTDCCKG_Msk

+#define RCC_CKGAENR_GFXMMUMCKG_Pos             (7U)

+#define RCC_CKGAENR_GFXMMUMCKG_Msk             (0x1UL << RCC_CKGAENR_GFXMMUMCKG_Pos) /*!< 0x00000080 */

+#define RCC_CKGAENR_GFXMMUMCKG                 RCC_CKGAENR_GFXMMUMCKG_Msk

+#define RCC_CKGAENR_AHB12CKG_Pos               (8U)

+#define RCC_CKGAENR_AHB12CKG_Msk               (0x1UL << RCC_CKGAENR_AHB12CKG_Pos) /*!< 0x00000100 */

+#define RCC_CKGAENR_AHB12CKG                   RCC_CKGAENR_AHB12CKG_Msk

+#define RCC_CKGAENR_AHB34CKG_Pos               (9U)

+#define RCC_CKGAENR_AHB34CKG_Msk               (0x1UL << RCC_CKGAENR_AHB34CKG_Pos) /*!< 0x00000200 */

+#define RCC_CKGAENR_AHB34CKG                   RCC_CKGAENR_AHB34CKG_Msk

+#define RCC_CKGAENR_FLIFTCKG_Pos               (10U)

+#define RCC_CKGAENR_FLIFTCKG_Msk               (0x1UL << RCC_CKGAENR_FLIFTCKG_Pos) /*!< 0x00000400 */

+#define RCC_CKGAENR_FLIFTCKG                   RCC_CKGAENR_FLIFTCKG_Msk

+#define RCC_CKGAENR_OCTOSPI2CKG_Pos            (11U)

+#define RCC_CKGAENR_OCTOSPI2CKG_Msk            (0x1UL << RCC_CKGAENR_OCTOSPI2CKG_Pos) /*!< 0x00000800 */

+#define RCC_CKGAENR_OCTOSPI2CKG                RCC_CKGAENR_OCTOSPI2CKG_Msk

+#define RCC_CKGAENR_FMCCKG_Pos                 (12U)

+#define RCC_CKGAENR_FMCCKG_Msk                 (0x1UL << RCC_CKGAENR_FMCCKG_Pos) /*!< 0x00001000 */

+#define RCC_CKGAENR_FMCCKG                     RCC_CKGAENR_FMCCKG_Msk

+#define RCC_CKGAENR_OCTOSPI1CKG_Pos            (13U)

+#define RCC_CKGAENR_OCTOSPI1CKG_Msk            (0x1UL << RCC_CKGAENR_OCTOSPI1CKG_Pos) /*!< 0x00002000 */

+#define RCC_CKGAENR_OCTOSPI1CKG                RCC_CKGAENR_OCTOSPI1CKG_Msk

+#define RCC_CKGAENR_AXIRAM1CKG_Pos             (14U)

+#define RCC_CKGAENR_AXIRAM1CKG_Msk             (0x1UL << RCC_CKGAENR_AXIRAM1CKG_Pos) /*!< 0x00004000 */

+#define RCC_CKGAENR_AXIRAM1CKG                 RCC_CKGAENR_AXIRAM1CKG_Msk

+#define RCC_CKGAENR_AXIRAM2CKG_Pos             (15U)

+#define RCC_CKGAENR_AXIRAM2CKG_Msk             (0x1UL << RCC_CKGAENR_AXIRAM2CKG_Pos) /*!< 0x00008000 */

+#define RCC_CKGAENR_AXIRAM2CKG                 RCC_CKGAENR_AXIRAM2CKG_Msk

+#define RCC_CKGAENR_AXIRAM3CKG_Pos             (16U)

+#define RCC_CKGAENR_AXIRAM3CKG_Msk             (0x1UL << RCC_CKGAENR_AXIRAM3CKG_Pos) /*!< 0x00010000 */

+#define RCC_CKGAENR_AXIRAM3CKG                 RCC_CKGAENR_AXIRAM3CKG_Msk

+#define RCC_CKGAENR_GFXMMUSCKG_Pos             (17U)

+#define RCC_CKGAENR_GFXMMUSCKG_Msk             (0x1UL << RCC_CKGAENR_GFXMMUSCKG_Pos) /*!< 0x00020000 */

+#define RCC_CKGAENR_GFXMMUSCKG                 RCC_CKGAENR_GFXMMUSCKG_Msk

+#define RCC_CKGAENR_ECCRAMCKG_Pos              (29U)

+#define RCC_CKGAENR_ECCRAMCKG_Msk              (0x1UL << RCC_CKGAENR_ECCRAMCKG_Pos) /*!< 0x20000000 */

+#define RCC_CKGAENR_ECCRAMCKG                  RCC_CKGAENR_ECCRAMCKG_Msk

+#define RCC_CKGAENR_EXTICKG_Pos                (30U)

+#define RCC_CKGAENR_EXTICKG_Msk                (0x1UL << RCC_CKGAENR_EXTICKG_Pos) /*!< 0x40000000 */

+#define RCC_CKGAENR_EXTICKG                    RCC_CKGAENR_EXTICKG_Msk

+#define RCC_CKGAENR_JTAGCKG_Pos                (31U)

+#define RCC_CKGAENR_JTAGCKG_Msk                (0x1UL << RCC_CKGAENR_JTAGCKG_Pos) /*!< 0x80000008 */

+#define RCC_CKGAENR_JTAGCKG                    RCC_CKGAENR_JTAGCKG_Msk

+/********************  Bit definition for RCC_AHB3LPENR register  **************/

+#define RCC_AHB3LPENR_MDMALPEN_Pos             (0U)

+#define RCC_AHB3LPENR_MDMALPEN_Msk             (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos)         /*!< 0x00000001 */

+#define RCC_AHB3LPENR_MDMALPEN                 RCC_AHB3LPENR_MDMALPEN_Msk

+#define RCC_AHB3LPENR_DMA2DLPEN_Pos            (4U)

+#define RCC_AHB3LPENR_DMA2DLPEN_Msk            (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos)        /*!< 0x00000010 */

+#define RCC_AHB3LPENR_DMA2DLPEN                RCC_AHB3LPENR_DMA2DLPEN_Msk

+#define RCC_AHB3LPENR_JPGDECLPEN_Pos           (5U)

+#define RCC_AHB3LPENR_JPGDECLPEN_Msk           (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos)       /*!< 0x00000020 */

+#define RCC_AHB3LPENR_JPGDECLPEN               RCC_AHB3LPENR_JPGDECLPEN_Msk

+#define RCC_AHB3LPENR_FLASHLPEN_Pos            (8U)

+#define RCC_AHB3LPENR_FLASHLPEN_Msk            (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos)        /*!< 0x00000100 */

+#define RCC_AHB3LPENR_FLASHLPEN                RCC_AHB3LPENR_FLASHLPEN_Msk

+#define RCC_AHB3LPENR_FMCLPEN_Pos              (12U)

+#define RCC_AHB3LPENR_FMCLPEN_Msk              (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)          /*!< 0x00001000 */

+#define RCC_AHB3LPENR_FMCLPEN                  RCC_AHB3LPENR_FMCLPEN_Msk

+#define RCC_AHB3LPENR_OSPI1LPEN_Pos            (14U)

+#define RCC_AHB3LPENR_OSPI1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_OSPI1LPEN_Pos)        /*!< 0x00004000 */

+#define RCC_AHB3LPENR_OSPI1LPEN                RCC_AHB3LPENR_OSPI1LPEN_Msk

+#define RCC_AHB3LPENR_SDMMC1LPEN_Pos           (16U)

+#define RCC_AHB3LPENR_SDMMC1LPEN_Msk           (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos)       /*!< 0x00010000 */

+#define RCC_AHB3LPENR_SDMMC1LPEN               RCC_AHB3LPENR_SDMMC1LPEN_Msk

+#define RCC_AHB3LPENR_OSPI2LPEN_Pos            (19U)

+#define RCC_AHB3LPENR_OSPI2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_OSPI2LPEN_Pos)        /*!< 0x00080000 */

+#define RCC_AHB3LPENR_OSPI2LPEN                RCC_AHB3LPENR_OSPI2LPEN_Msk

+#define RCC_AHB3LPENR_IOMNGRLPEN_Pos           (21U)

+#define RCC_AHB3LPENR_IOMNGRLPEN_Msk           (0x1UL << RCC_AHB3LPENR_IOMNGRLPEN_Pos)       /*!< 0x00200000 */

+#define RCC_AHB3LPENR_IOMNGRLPEN               RCC_AHB3LPENR_IOMNGRLPEN_Msk

+#define RCC_AHB3LPENR_OTFDEC1LPEN_Pos          (22U)

+#define RCC_AHB3LPENR_OTFDEC1LPEN_Msk          (0x1UL << RCC_AHB3LPENR_OTFDEC1LPEN_Pos)      /*!< 0x00400000 */

+#define RCC_AHB3LPENR_OTFDEC1LPEN              RCC_AHB3LPENR_OTFDEC1LPEN_Msk

+#define RCC_AHB3LPENR_OTFDEC2LPEN_Pos          (23U)

+#define RCC_AHB3LPENR_OTFDEC2LPEN_Msk          (0x1UL << RCC_AHB3LPENR_OTFDEC2LPEN_Pos)      /*!< 0x00800000 */

+#define RCC_AHB3LPENR_OTFDEC2LPEN              RCC_AHB3LPENR_OTFDEC2LPEN_Msk

+#define RCC_AHB3LPENR_GFXMMULPEN_Pos           (24U)

+#define RCC_AHB3LPENR_GFXMMULPEN_Msk           (0x1UL << RCC_AHB3LPENR_GFXMMULPEN_Pos)       /*!< 0x01000000 */

+#define RCC_AHB3LPENR_GFXMMULPEN               RCC_AHB3LPENR_GFXMMULPEN_Msk

+#define RCC_AHB3LPENR_AXISRAM2LPEN_Pos         (26U)

+#define RCC_AHB3LPENR_AXISRAM2LPEN_Msk         (0x1UL << RCC_AHB3LPENR_AXISRAM2LPEN_Pos)     /*!< 0x02000000 */

+#define RCC_AHB3LPENR_AXISRAM2LPEN             RCC_AHB3LPENR_AXISRAM2LPEN_Msk

+#define RCC_AHB3LPENR_AXISRAM3LPEN_Pos         (27U)

+#define RCC_AHB3LPENR_AXISRAM3LPEN_Msk         (0x1UL << RCC_AHB3LPENR_AXISRAM3LPEN_Pos)     /*!< 0x04000000 */

+#define RCC_AHB3LPENR_AXISRAM3LPEN             RCC_AHB3LPENR_AXISRAM3LPEN_Msk

+#define RCC_AHB3LPENR_DTCM1LPEN_Pos            (28U)

+#define RCC_AHB3LPENR_DTCM1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos)        /*!< 0x10000000 */

+#define RCC_AHB3LPENR_DTCM1LPEN                RCC_AHB3LPENR_DTCM1LPEN_Msk

+#define RCC_AHB3LPENR_DTCM2LPEN_Pos            (29U)

+#define RCC_AHB3LPENR_DTCM2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos)        /*!< 0x20000000 */

+#define RCC_AHB3LPENR_DTCM2LPEN                RCC_AHB3LPENR_DTCM2LPEN_Msk

+#define RCC_AHB3LPENR_ITCMLPEN_Pos             (30U)

+#define RCC_AHB3LPENR_ITCMLPEN_Msk             (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos)         /*!< 0x40000000 */

+#define RCC_AHB3LPENR_ITCMLPEN                 RCC_AHB3LPENR_ITCMLPEN_Msk

+#define RCC_AHB3LPENR_AXISRAM1LPEN_Pos         (31U)

+#define RCC_AHB3LPENR_AXISRAM1LPEN_Msk         (0x1UL << RCC_AHB3LPENR_AXISRAM1LPEN_Pos)      /*!< 0x80000000 */

+#define RCC_AHB3LPENR_AXISRAM1LPEN             RCC_AHB3LPENR_AXISRAM1LPEN_Msk

+

+

+/* Legacy define */

+#define RCC_AHB3LPENR_AXISRAMLPEN_Pos          RCC_AHB3LPENR_AXISRAM1LPEN_Pos

+#define RCC_AHB3LPENR_AXISRAMLPEN_Msk          RCC_AHB3LPENR_AXISRAM1LPEN_Msk

+#define RCC_AHB3LPENR_AXISRAMLPEN              RCC_AHB3LPENR_AXISRAM1LPEN

+/********************  Bit definition for RCC_AHB1LPENR register  ***************/

+#define RCC_AHB1LPENR_DMA1LPEN_Pos             (0U)

+#define RCC_AHB1LPENR_DMA1LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB1LPENR_DMA1LPEN                 RCC_AHB1LPENR_DMA1LPEN_Msk

+#define RCC_AHB1LPENR_DMA2LPEN_Pos             (1U)

+#define RCC_AHB1LPENR_DMA2LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */

+#define RCC_AHB1LPENR_DMA2LPEN                 RCC_AHB1LPENR_DMA2LPEN_Msk

+#define RCC_AHB1LPENR_ADC12LPEN_Pos            (5U)

+#define RCC_AHB1LPENR_ADC12LPEN_Msk            (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB1LPENR_ADC12LPEN                RCC_AHB1LPENR_ADC12LPEN_Msk

+#define RCC_AHB1LPENR_CRCLPEN_Pos              (9U)

+#define RCC_AHB1LPENR_CRCLPEN_Msk              (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00008000 */

+#define RCC_AHB1LPENR_CRCLPEN                   RCC_AHB1LPENR_CRCLPEN_Msk

+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos        (25U)

+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */

+#define RCC_AHB1LPENR_USB1OTGHSLPEN            RCC_AHB1LPENR_USB1OTGHSLPEN_Msk

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos    (26U)

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN        RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk

+

+/********************  Bit definition for RCC_AHB2LPENR register  ***************/

+#define RCC_AHB2LPENR_DCMI_PSSILPEN_Pos        (0U)

+#define RCC_AHB2LPENR_DCMI_PSSILPEN_Msk        (0x1UL << RCC_AHB2LPENR_DCMI_PSSILPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB2LPENR_DCMI_PSSILPEN            RCC_AHB2LPENR_DCMI_PSSILPEN_Msk

+#define RCC_AHB2LPENR_CRYPLPEN_Pos             (4U)

+#define RCC_AHB2LPENR_CRYPLPEN_Msk             (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */

+#define RCC_AHB2LPENR_CRYPLPEN                 RCC_AHB2LPENR_CRYPLPEN_Msk

+#define RCC_AHB2LPENR_HASHLPEN_Pos             (5U)

+#define RCC_AHB2LPENR_HASHLPEN_Msk             (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB2LPENR_HASHLPEN                 RCC_AHB2LPENR_HASHLPEN_Msk

+#define RCC_AHB2LPENR_RNGLPEN_Pos              (6U)

+#define RCC_AHB2LPENR_RNGLPEN_Msk              (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */

+#define RCC_AHB2LPENR_RNGLPEN                  RCC_AHB2LPENR_RNGLPEN_Msk

+#define RCC_AHB2LPENR_SDMMC2LPEN_Pos           (9U)

+#define RCC_AHB2LPENR_SDMMC2LPEN_Msk           (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */

+#define RCC_AHB2LPENR_SDMMC2LPEN               RCC_AHB2LPENR_SDMMC2LPEN_Msk

+#define RCC_AHB2LPENR_BDMA1LPEN_Pos            (11U)

+#define RCC_AHB2LPENR_BDMA1LPEN_Msk            (0x1UL << RCC_AHB2LPENR_BDMA1LPEN_Pos)   /*!< 0x00000800 */

+#define RCC_AHB2LPENR_BDMA1LPEN                RCC_AHB2LPENR_BDMA1LPEN_Msk

+#define RCC_AHB2LPENR_AHBSRAM1LPEN_Pos         (29U)

+#define RCC_AHB2LPENR_AHBSRAM1LPEN_Msk         (0x1UL << RCC_AHB2LPENR_AHBSRAM1LPEN_Pos) /*!< 0x20000000 */

+#define RCC_AHB2LPENR_AHBSRAM1LPEN             RCC_AHB2LPENR_AHBSRAM1LPEN_Msk

+#define RCC_AHB2LPENR_AHBSRAM2LPEN_Pos         (30U)

+#define RCC_AHB2LPENR_AHBSRAM2LPEN_Msk         (0x1UL << RCC_AHB2LPENR_AHBSRAM2LPEN_Pos) /*!< 0x40000000 */

+#define RCC_AHB2LPENR_AHBSRAM2LPEN             RCC_AHB2LPENR_AHBSRAM2LPEN_Msk

+

+/* Legacy define */

+#define RCC_AHB2LPENR_DFSDMDMALPEN_Pos         RCC_AHB2LPENR_BDMA1LPEN_Pos

+#define RCC_AHB2LPENR_DFSDMDMALPEN_Msk         RCC_AHB2LPENR_BDMA1LPEN_Msk

+#define RCC_AHB2LPENR_DFSDMDMALPEN             RCC_AHB2LPENR_BDMA1LPEN

+#define RCC_AHB2LPENR_DCMILPEN_Pos             RCC_AHB2LPENR_DCMI_PSSILPEN_Pos

+#define RCC_AHB2LPENR_DCMILPEN_Msk             RCC_AHB2LPENR_DCMI_PSSILPEN_Msk

+#define RCC_AHB2LPENR_DCMILPEN                 RCC_AHB2LPENR_DCMI_PSSILPEN

+

+/********************  Bit definition for RCC_AHB4LPENR register  ******************/

+#define RCC_AHB4LPENR_GPIOALPEN_Pos            (0U)

+#define RCC_AHB4LPENR_GPIOALPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB4LPENR_GPIOALPEN                RCC_AHB4LPENR_GPIOALPEN_Msk

+#define RCC_AHB4LPENR_GPIOBLPEN_Pos            (1U)

+#define RCC_AHB4LPENR_GPIOBLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */

+#define RCC_AHB4LPENR_GPIOBLPEN                RCC_AHB4LPENR_GPIOBLPEN_Msk

+#define RCC_AHB4LPENR_GPIOCLPEN_Pos            (2U)

+#define RCC_AHB4LPENR_GPIOCLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */

+#define RCC_AHB4LPENR_GPIOCLPEN                RCC_AHB4LPENR_GPIOCLPEN_Msk

+#define RCC_AHB4LPENR_GPIODLPEN_Pos            (3U)

+#define RCC_AHB4LPENR_GPIODLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */

+#define RCC_AHB4LPENR_GPIODLPEN                RCC_AHB4LPENR_GPIODLPEN_Msk

+#define RCC_AHB4LPENR_GPIOELPEN_Pos            (4U)

+#define RCC_AHB4LPENR_GPIOELPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */

+#define RCC_AHB4LPENR_GPIOELPEN                RCC_AHB4LPENR_GPIOELPEN_Msk

+#define RCC_AHB4LPENR_GPIOFLPEN_Pos            (5U)

+#define RCC_AHB4LPENR_GPIOFLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB4LPENR_GPIOFLPEN                RCC_AHB4LPENR_GPIOFLPEN_Msk

+#define RCC_AHB4LPENR_GPIOGLPEN_Pos            (6U)

+#define RCC_AHB4LPENR_GPIOGLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */

+#define RCC_AHB4LPENR_GPIOGLPEN                RCC_AHB4LPENR_GPIOGLPEN_Msk

+#define RCC_AHB4LPENR_GPIOHLPEN_Pos            (7U)

+#define RCC_AHB4LPENR_GPIOHLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */

+#define RCC_AHB4LPENR_GPIOHLPEN                RCC_AHB4LPENR_GPIOHLPEN_Msk

+#define RCC_AHB4LPENR_GPIOILPEN_Pos            (8U)

+#define RCC_AHB4LPENR_GPIOILPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */

+#define RCC_AHB4LPENR_GPIOILPEN                RCC_AHB4LPENR_GPIOILPEN_Msk

+#define RCC_AHB4LPENR_GPIOJLPEN_Pos            (9U)

+#define RCC_AHB4LPENR_GPIOJLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */

+#define RCC_AHB4LPENR_GPIOJLPEN                RCC_AHB4LPENR_GPIOJLPEN_Msk

+#define RCC_AHB4LPENR_GPIOKLPEN_Pos            (10U)

+#define RCC_AHB4LPENR_GPIOKLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */

+#define RCC_AHB4LPENR_GPIOKLPEN                RCC_AHB4LPENR_GPIOKLPEN_Msk

+#define RCC_AHB4LPENR_BDMA2LPEN_Pos             (21U)

+#define RCC_AHB4LPENR_BDMA2LPEN_Msk             (0x1UL << RCC_AHB4LPENR_BDMA2LPEN_Pos) /*!< 0x00200000 */

+#define RCC_AHB4LPENR_BDMA2LPEN                 RCC_AHB4LPENR_BDMA2LPEN_Msk

+#define RCC_AHB4LPENR_BKPRAMLPEN_Pos           (28U)

+#define RCC_AHB4LPENR_BKPRAMLPEN_Msk           (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */

+#define RCC_AHB4LPENR_BKPRAMLPEN               RCC_AHB4LPENR_BKPRAMLPEN_Msk

+#define RCC_AHB4LPENR_SRDSRAMLPEN_Pos          (29U)

+#define RCC_AHB4LPENR_SRDSRAMLPEN_Msk          (0x1UL << RCC_AHB4LPENR_SRDSRAMLPEN_Pos) /*!< 0x20000000 */

+#define RCC_AHB4LPENR_SRDSRAMLPEN              RCC_AHB4LPENR_SRDSRAMLPEN_Msk

+

+/********************  Bit definition for RCC_APB3LPENR register  ******************/

+#define RCC_APB3LPENR_LTDCLPEN_Pos             (3U)

+#define RCC_APB3LPENR_LTDCLPEN_Msk             (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB3LPENR_LTDCLPEN                 RCC_APB3LPENR_LTDCLPEN_Msk

+#define RCC_APB3LPENR_WWDGLPEN_Pos             (6U)

+#define RCC_APB3LPENR_WWDGLPEN_Msk             (0x1UL << RCC_APB3LPENR_WWDGLPEN_Pos)  /*!< 0x00000040 */

+#define RCC_APB3LPENR_WWDGLPEN                 RCC_APB3LPENR_WWDGLPEN_Msk

+

+/* Legacy define */

+#define RCC_APB3LPENR_WWDG1LPEN_Pos            RCC_APB3LPENR_WWDGLPEN_Pos

+#define RCC_APB3LPENR_WWDG1LPEN_Msk            RCC_APB3LPENR_WWDGLPEN_Msk

+#define RCC_APB3LPENR_WWDG1LPEN                RCC_APB3LPENR_WWDGLPEN

+/********************  Bit definition for RCC_APB1LLPENR register  ******************/

+

+#define RCC_APB1LLPENR_TIM2LPEN_Pos            (0U)

+#define RCC_APB1LLPENR_TIM2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */

+#define RCC_APB1LLPENR_TIM2LPEN                RCC_APB1LLPENR_TIM2LPEN_Msk

+#define RCC_APB1LLPENR_TIM3LPEN_Pos            (1U)

+#define RCC_APB1LLPENR_TIM3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1LLPENR_TIM3LPEN                RCC_APB1LLPENR_TIM3LPEN_Msk

+#define RCC_APB1LLPENR_TIM4LPEN_Pos            (2U)

+#define RCC_APB1LLPENR_TIM4LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1LLPENR_TIM4LPEN                RCC_APB1LLPENR_TIM4LPEN_Msk

+#define RCC_APB1LLPENR_TIM5LPEN_Pos            (3U)

+#define RCC_APB1LLPENR_TIM5LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB1LLPENR_TIM5LPEN                RCC_APB1LLPENR_TIM5LPEN_Msk

+#define RCC_APB1LLPENR_TIM6LPEN_Pos            (4U)

+#define RCC_APB1LLPENR_TIM6LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1LLPENR_TIM6LPEN                RCC_APB1LLPENR_TIM6LPEN_Msk

+#define RCC_APB1LLPENR_TIM7LPEN_Pos            (5U)

+#define RCC_APB1LLPENR_TIM7LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1LLPENR_TIM7LPEN                RCC_APB1LLPENR_TIM7LPEN_Msk

+#define RCC_APB1LLPENR_TIM12LPEN_Pos           (6U)

+#define RCC_APB1LLPENR_TIM12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */

+#define RCC_APB1LLPENR_TIM12LPEN               RCC_APB1LLPENR_TIM12LPEN_Msk

+#define RCC_APB1LLPENR_TIM13LPEN_Pos           (7U)

+#define RCC_APB1LLPENR_TIM13LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB1LLPENR_TIM13LPEN               RCC_APB1LLPENR_TIM13LPEN_Msk

+#define RCC_APB1LLPENR_TIM14LPEN_Pos           (8U)

+#define RCC_APB1LLPENR_TIM14LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1LLPENR_TIM14LPEN               RCC_APB1LLPENR_TIM14LPEN_Msk

+#define RCC_APB1LLPENR_LPTIM1LPEN_Pos          (9U)

+#define RCC_APB1LLPENR_LPTIM1LPEN_Msk          (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */

+#define RCC_APB1LLPENR_LPTIM1LPEN              RCC_APB1LLPENR_LPTIM1LPEN_Msk

+

+

+#define RCC_APB1LLPENR_SPI2LPEN_Pos            (14U)

+#define RCC_APB1LLPENR_SPI2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */

+#define RCC_APB1LLPENR_SPI2LPEN                RCC_APB1LLPENR_SPI2LPEN_Msk

+#define RCC_APB1LLPENR_SPI3LPEN_Pos            (15U)

+#define RCC_APB1LLPENR_SPI3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */

+#define RCC_APB1LLPENR_SPI3LPEN                RCC_APB1LLPENR_SPI3LPEN_Msk

+#define RCC_APB1LLPENR_SPDIFRXLPEN_Pos         (16U)

+#define RCC_APB1LLPENR_SPDIFRXLPEN_Msk         (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB1LLPENR_SPDIFRXLPEN             RCC_APB1LLPENR_SPDIFRXLPEN_Msk

+#define RCC_APB1LLPENR_USART2LPEN_Pos          (17U)

+#define RCC_APB1LLPENR_USART2LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */

+#define RCC_APB1LLPENR_USART2LPEN              RCC_APB1LLPENR_USART2LPEN_Msk

+#define RCC_APB1LLPENR_USART3LPEN_Pos          (18U)

+#define RCC_APB1LLPENR_USART3LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */

+#define RCC_APB1LLPENR_USART3LPEN              RCC_APB1LLPENR_USART3LPEN_Msk

+#define RCC_APB1LLPENR_UART4LPEN_Pos           (19U)

+#define RCC_APB1LLPENR_UART4LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */

+#define RCC_APB1LLPENR_UART4LPEN               RCC_APB1LLPENR_UART4LPEN_Msk

+#define RCC_APB1LLPENR_UART5LPEN_Pos           (20U)

+#define RCC_APB1LLPENR_UART5LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */

+#define RCC_APB1LLPENR_UART5LPEN               RCC_APB1LLPENR_UART5LPEN_Msk

+#define RCC_APB1LLPENR_I2C1LPEN_Pos            (21U)

+#define RCC_APB1LLPENR_I2C1LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */

+#define RCC_APB1LLPENR_I2C1LPEN                RCC_APB1LLPENR_I2C1LPEN_Msk

+#define RCC_APB1LLPENR_I2C2LPEN_Pos            (22U)

+#define RCC_APB1LLPENR_I2C2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */

+#define RCC_APB1LLPENR_I2C2LPEN                RCC_APB1LLPENR_I2C2LPEN_Msk

+#define RCC_APB1LLPENR_I2C3LPEN_Pos            (23U)

+#define RCC_APB1LLPENR_I2C3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */

+#define RCC_APB1LLPENR_I2C3LPEN                RCC_APB1LLPENR_I2C3LPEN_Msk

+#define RCC_APB1LLPENR_CECLPEN_Pos             (27U)

+#define RCC_APB1LLPENR_CECLPEN_Msk             (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */

+#define RCC_APB1LLPENR_CECLPEN                 RCC_APB1LLPENR_CECLPEN_Msk

+#define RCC_APB1LLPENR_DAC12LPEN_Pos           (29U)

+#define RCC_APB1LLPENR_DAC12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */

+#define RCC_APB1LLPENR_DAC12LPEN               RCC_APB1LLPENR_DAC12LPEN_Msk

+#define RCC_APB1LLPENR_UART7LPEN_Pos           (30U)

+#define RCC_APB1LLPENR_UART7LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */

+#define RCC_APB1LLPENR_UART7LPEN               RCC_APB1LLPENR_UART7LPEN_Msk

+#define RCC_APB1LLPENR_UART8LPEN_Pos           (31U)

+#define RCC_APB1LLPENR_UART8LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */

+#define RCC_APB1LLPENR_UART8LPEN               RCC_APB1LLPENR_UART8LPEN_Msk

+

+/* Legacy define */

+#define RCC_APB1LLPENR_HDMICECEN_Pos           RCC_APB1LLPENR_CECLPEN_Pos

+#define RCC_APB1LLPENR_HDMICECEN_Msk           RCC_APB1LLPENR_CECLPEN_Msk

+#define RCC_APB1LLPENR_HDMICECEN               RCC_APB1LLPENR_CECLPEN

+/********************  Bit definition for RCC_APB1HLPENR register  ******************/

+#define RCC_APB1HLPENR_CRSLPEN_Pos             (1U)

+#define RCC_APB1HLPENR_CRSLPEN_Msk             (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1HLPENR_CRSLPEN                 RCC_APB1HLPENR_CRSLPEN_Msk

+#define RCC_APB1HLPENR_SWPMILPEN_Pos           (2U)

+#define RCC_APB1HLPENR_SWPMILPEN_Msk           (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1HLPENR_SWPMILPEN               RCC_APB1HLPENR_SWPMILPEN_Msk

+#define RCC_APB1HLPENR_OPAMPLPEN_Pos           (4U)

+#define RCC_APB1HLPENR_OPAMPLPEN_Msk           (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1HLPENR_OPAMPLPEN               RCC_APB1HLPENR_OPAMPLPEN_Msk

+#define RCC_APB1HLPENR_MDIOSLPEN_Pos           (5U)

+#define RCC_APB1HLPENR_MDIOSLPEN_Msk           (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1HLPENR_MDIOSLPEN               RCC_APB1HLPENR_MDIOSLPEN_Msk

+#define RCC_APB1HLPENR_FDCANLPEN_Pos           (8U)

+#define RCC_APB1HLPENR_FDCANLPEN_Msk           (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1HLPENR_FDCANLPEN               RCC_APB1HLPENR_FDCANLPEN_Msk

+

+/********************  Bit definition for RCC_APB2LPENR register  ******************/

+#define RCC_APB2LPENR_TIM1LPEN_Pos             (0U)

+#define RCC_APB2LPENR_TIM1LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */

+#define RCC_APB2LPENR_TIM1LPEN                 RCC_APB2LPENR_TIM1LPEN_Msk

+#define RCC_APB2LPENR_TIM8LPEN_Pos             (1U)

+#define RCC_APB2LPENR_TIM8LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB2LPENR_TIM8LPEN                 RCC_APB2LPENR_TIM8LPEN_Msk

+#define RCC_APB2LPENR_USART1LPEN_Pos           (4U)

+#define RCC_APB2LPENR_USART1LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB2LPENR_USART1LPEN               RCC_APB2LPENR_USART1LPEN_Msk

+#define RCC_APB2LPENR_USART6LPEN_Pos           (5U)

+#define RCC_APB2LPENR_USART6LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB2LPENR_USART6LPEN               RCC_APB2LPENR_USART6LPEN_Msk

+#define RCC_APB2LPENR_UART9LPEN_Pos            (6U)

+#define RCC_APB2LPENR_UART9LPEN_Msk            (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos) /*!< 0x00000040 */

+#define RCC_APB2LPENR_UART9LPEN                 RCC_APB2LPENR_UART9LPEN_Msk

+#define RCC_APB2LPENR_USART10LPEN_Pos          (7U)

+#define RCC_APB2LPENR_USART10LPEN_Msk          (0x1UL << RCC_APB2LPENR_USART10LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB2LPENR_USART10LPEN               RCC_APB2LPENR_USART10LPEN_Msk

+#define RCC_APB2LPENR_SPI1LPEN_Pos             (12U)

+#define RCC_APB2LPENR_SPI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */

+#define RCC_APB2LPENR_SPI1LPEN                 RCC_APB2LPENR_SPI1LPEN_Msk

+#define RCC_APB2LPENR_SPI4LPEN_Pos             (13U)

+#define RCC_APB2LPENR_SPI4LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */

+#define RCC_APB2LPENR_SPI4LPEN                 RCC_APB2LPENR_SPI4LPEN_Msk

+#define RCC_APB2LPENR_TIM15LPEN_Pos            (16U)

+#define RCC_APB2LPENR_TIM15LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB2LPENR_TIM15LPEN                RCC_APB2LPENR_TIM15LPEN_Msk

+#define RCC_APB2LPENR_TIM16LPEN_Pos            (17U)

+#define RCC_APB2LPENR_TIM16LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */

+#define RCC_APB2LPENR_TIM16LPEN                RCC_APB2LPENR_TIM16LPEN_Msk

+#define RCC_APB2LPENR_TIM17LPEN_Pos            (18U)

+#define RCC_APB2LPENR_TIM17LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */

+#define RCC_APB2LPENR_TIM17LPEN                RCC_APB2LPENR_TIM17LPEN_Msk

+#define RCC_APB2LPENR_SPI5LPEN_Pos             (20U)

+#define RCC_APB2LPENR_SPI5LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */

+#define RCC_APB2LPENR_SPI5LPEN                 RCC_APB2LPENR_SPI5LPEN_Msk

+#define RCC_APB2LPENR_SAI1LPEN_Pos             (22U)

+#define RCC_APB2LPENR_SAI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */

+#define RCC_APB2LPENR_SAI1LPEN                 RCC_APB2LPENR_SAI1LPEN_Msk

+#define RCC_APB2LPENR_SAI2LPEN_Pos             (23U)

+#define RCC_APB2LPENR_SAI2LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */

+#define RCC_APB2LPENR_SAI2LPEN                 RCC_APB2LPENR_SAI2LPEN_Msk

+#define RCC_APB2LPENR_DFSDM1LPEN_Pos           (30U)

+#define RCC_APB2LPENR_DFSDM1LPEN_Msk           (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x40000000 */

+#define RCC_APB2LPENR_DFSDM1LPEN               RCC_APB2LPENR_DFSDM1LPEN_Msk

+

+/********************  Bit definition for RCC_APB4LPENR register  ******************/

+#define RCC_APB4LPENR_SYSCFGLPEN_Pos           (1U)

+#define RCC_APB4LPENR_SYSCFGLPEN_Msk           (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB4LPENR_SYSCFGLPEN               RCC_APB4LPENR_SYSCFGLPEN_Msk

+#define RCC_APB4LPENR_LPUART1LPEN_Pos          (3U)

+#define RCC_APB4LPENR_LPUART1LPEN_Msk          (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB4LPENR_LPUART1LPEN              RCC_APB4LPENR_LPUART1LPEN_Msk

+#define RCC_APB4LPENR_SPI6LPEN_Pos             (5U)

+#define RCC_APB4LPENR_SPI6LPEN_Msk             (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB4LPENR_SPI6LPEN                 RCC_APB4LPENR_SPI6LPEN_Msk

+#define RCC_APB4LPENR_I2C4LPEN_Pos             (7U)

+#define RCC_APB4LPENR_I2C4LPEN_Msk             (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB4LPENR_I2C4LPEN                 RCC_APB4LPENR_I2C4LPEN_Msk

+#define RCC_APB4LPENR_LPTIM2LPEN_Pos           (9U)

+#define RCC_APB4LPENR_LPTIM2LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */

+#define RCC_APB4LPENR_LPTIM2LPEN               RCC_APB4LPENR_LPTIM2LPEN_Msk

+#define RCC_APB4LPENR_LPTIM3LPEN_Pos           (10U)

+#define RCC_APB4LPENR_LPTIM3LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */

+#define RCC_APB4LPENR_LPTIM3LPEN               RCC_APB4LPENR_LPTIM3LPEN_Msk

+#define RCC_APB4LPENR_DAC2LPEN_Pos             (13U)

+#define RCC_APB4LPENR_DAC2LPEN_Msk             (0x1UL << RCC_APB4LPENR_DAC2LPEN_Pos) /*!< 0x00002000 */

+#define RCC_APB4LPENR_DAC2LPEN                 RCC_APB4LPENR_DAC2LPEN_Msk

+#define RCC_APB4LPENR_COMP12LPEN_Pos           (14U)

+#define RCC_APB4LPENR_COMP12LPEN_Msk           (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */

+#define RCC_APB4LPENR_COMP12LPEN               RCC_APB4LPENR_COMP12LPEN_Msk

+#define RCC_APB4LPENR_VREFLPEN_Pos             (15U)

+#define RCC_APB4LPENR_VREFLPEN_Msk             (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */

+#define RCC_APB4LPENR_VREFLPEN                 RCC_APB4LPENR_VREFLPEN_Msk

+#define RCC_APB4LPENR_RTCAPBLPEN_Pos           (16U)

+#define RCC_APB4LPENR_RTCAPBLPEN_Msk           (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB4LPENR_RTCAPBLPEN               RCC_APB4LPENR_RTCAPBLPEN_Msk

+

+#define RCC_APB4LPENR_DTSLPEN_Pos              (26U)

+#define RCC_APB4LPENR_DTSLPEN_Msk              (0x1UL << RCC_APB4LPENR_DTSLPEN_Pos) /*!< 0x04000000 */

+#define RCC_APB4LPENR_DTSLPEN                  RCC_APB4LPENR_DTSLPEN_Msk

+#define RCC_APB4LPENR_DFSDM2LPEN_Pos           (27U)

+#define RCC_APB4LPENR_DFSDM2LPEN_Msk           (0x1UL << RCC_APB4LPENR_DFSDM2LPEN_Pos) /*!< 0x08000000 */

+#define RCC_APB4LPENR_DFSDM2LPEN                RCC_APB4LPENR_DFSDM2LPEN_Msk

+

+/********************  Bit definition for RCC_RSR register  *******************/

+#define RCC_RSR_RMVF_Pos                       (16U)

+#define RCC_RSR_RMVF_Msk                       (0x1UL << RCC_RSR_RMVF_Pos)     /*!< 0x00010000 */

+#define RCC_RSR_RMVF                           RCC_RSR_RMVF_Msk

+#define RCC_RSR_CDRSTF_Pos                     (19U)

+#define RCC_RSR_CDRSTF_Msk                     (0x1UL << RCC_RSR_CDRSTF_Pos)   /*!< 0x00080000 */

+#define RCC_RSR_CDRSTF                         RCC_RSR_CDRSTF_Msk

+#define RCC_RSR_BORRSTF_Pos                    (21U)

+#define RCC_RSR_BORRSTF_Msk                    (0x1UL << RCC_RSR_BORRSTF_Pos)  /*!< 0x00200000 */

+#define RCC_RSR_BORRSTF                        RCC_RSR_BORRSTF_Msk

+#define RCC_RSR_PINRSTF_Pos                    (22U)

+#define RCC_RSR_PINRSTF_Msk                    (0x1UL << RCC_RSR_PINRSTF_Pos)  /*!< 0x00400000 */

+#define RCC_RSR_PINRSTF                        RCC_RSR_PINRSTF_Msk

+#define RCC_RSR_PORRSTF_Pos                    (23U)

+#define RCC_RSR_PORRSTF_Msk                    (0x1UL << RCC_RSR_PORRSTF_Pos)  /*!< 0x00800000 */

+#define RCC_RSR_PORRSTF                        RCC_RSR_PORRSTF_Msk

+#define RCC_RSR_SFTRSTF_Pos                    (24U)

+#define RCC_RSR_SFTRSTF_Msk                    (0x1UL << RCC_RSR_SFTRSTF_Pos)  /*!< 0x01000000 */

+#define RCC_RSR_SFTRSTF                        RCC_RSR_SFTRSTF_Msk

+#define RCC_RSR_IWDGRSTF_Pos                   (26U)

+#define RCC_RSR_IWDGRSTF_Msk                   (0x1UL << RCC_RSR_IWDGRSTF_Pos) /*!< 0x04000000 */

+#define RCC_RSR_IWDGRSTF                       RCC_RSR_IWDGRSTF_Msk

+#define RCC_RSR_WWDGRSTF_Pos                   (28U)

+#define RCC_RSR_WWDGRSTF_Msk                   (0x1UL << RCC_RSR_WWDGRSTF_Pos) /*!< 0x10000000 */

+#define RCC_RSR_WWDGRSTF                       RCC_RSR_WWDGRSTF_Msk

+

+#define RCC_RSR_LPWRRSTF_Pos                   (30U)

+#define RCC_RSR_LPWRRSTF_Msk                   (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */

+#define RCC_RSR_LPWRRSTF                       RCC_RSR_LPWRRSTF_Msk

+

+

+/* Legacy define */

+#define RCC_RSR_IWDG1RSTF_Pos                  RCC_RSR_IWDGRSTF_Pos

+#define RCC_RSR_IWDG1RSTF_Msk                  RCC_RSR_IWDGRSTF_Msk

+#define RCC_RSR_IWDG1RSTF                      RCC_RSR_IWDGRSTF

+#define RCC_RSR_WWDG1RSTF_Pos                  RCC_RSR_WWDGRSTF_Pos

+#define RCC_RSR_WWDG1RSTF_Msk                  RCC_RSR_WWDGRSTF_Msk

+#define RCC_RSR_WWDG1RSTF                      RCC_RSR_WWDGRSTF

+/******************************************************************************/

+/*                                                                            */

+/*                                    RNG                                     */

+/*                                                                            */

+/******************************************************************************/

+/***************************    RNG VER  **************************************/

+#define RNG_VER_3_1

+/********************  Bits definition for RNG_CR register  *******************/

+#define RNG_CR_RNGEN_Pos    (2U)

+#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */

+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk

+#define RNG_CR_IE_Pos       (3U)

+#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */

+#define RNG_CR_IE           RNG_CR_IE_Msk

+#define RNG_CR_CED_Pos      (5U)

+#define RNG_CR_CED_Msk      (0x1UL << RNG_CR_CED_Pos)                          /*!< 0x00000020 */

+#define RNG_CR_CED          RNG_CR_CED_Msk

+#define RNG_CR_RNG_CONFIG3_Pos      (8U)

+#define RNG_CR_RNG_CONFIG3_Msk      (0xFUL << RNG_CR_RNG_CONFIG3_Pos)          /*!< 0x00000F00 */

+#define RNG_CR_RNG_CONFIG3          RNG_CR_RNG_CONFIG3_Msk

+#define RNG_CR_NISTC_Pos            (12U)

+#define RNG_CR_NISTC_Msk            (0x1UL << RNG_CR_NISTC_Pos)                /*!< 0x00001000 */

+#define RNG_CR_NISTC                RNG_CR_NISTC_Msk

+#define RNG_CR_RNG_CONFIG2_Pos      (13U)

+#define RNG_CR_RNG_CONFIG2_Msk      (0x7UL << RNG_CR_RNG_CONFIG2_Pos)          /*!< 0x0000E000 */

+#define RNG_CR_RNG_CONFIG2          RNG_CR_RNG_CONFIG2_Msk

+#define RNG_CR_CLKDIV_Pos           (16U)

+#define RNG_CR_CLKDIV_Msk           (0xFUL << RNG_CR_CLKDIV_Pos)               /*!< 0x000F0000 */

+#define RNG_CR_CLKDIV               RNG_CR_CLKDIV_Msk

+#define RNG_CR_CLKDIV_0             (0x1U << RNG_CR_CLKDIV_Pos)                /*!< 0x00010000 */

+#define RNG_CR_CLKDIV_1             (0x2U << RNG_CR_CLKDIV_Pos)                /*!< 0x00020000 */

+#define RNG_CR_CLKDIV_2             (0x4U << RNG_CR_CLKDIV_Pos)                /*!< 0x00040000 */

+#define RNG_CR_CLKDIV_3             (0x8U << RNG_CR_CLKDIV_Pos)                /*!< 0x00080000 */

+#define RNG_CR_RNG_CONFIG1_Pos      (20U)

+#define RNG_CR_RNG_CONFIG1_Msk      (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)         /*!< 0x03F00000 */

+#define RNG_CR_RNG_CONFIG1          RNG_CR_RNG_CONFIG1_Msk

+#define RNG_CR_CONDRST_Pos         (30U)

+#define RNG_CR_CONDRST_Msk         (0x1UL << RNG_CR_CONDRST_Pos)                  /*!< 0x40000000 */

+#define RNG_CR_CONDRST             RNG_CR_CONDRST_Msk

+#define RNG_CR_CONFIGLOCK_Pos      (31U)

+#define RNG_CR_CONFIGLOCK_Msk      (0x1UL << RNG_CR_CONFIGLOCK_Pos)            /*!< 0x80000000 */

+#define RNG_CR_CONFIGLOCK          RNG_CR_CONFIGLOCK_Msk

+

+/********************  Bits definition for RNG_SR register  *******************/

+#define RNG_SR_DRDY_Pos     (0U)

+#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */

+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk

+#define RNG_SR_CECS_Pos     (1U)

+#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */

+#define RNG_SR_CECS         RNG_SR_CECS_Msk

+#define RNG_SR_SECS_Pos     (2U)

+#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */

+#define RNG_SR_SECS         RNG_SR_SECS_Msk

+#define RNG_SR_CEIS_Pos     (5U)

+#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */

+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk

+#define RNG_SR_SEIS_Pos     (6U)

+#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */

+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                           Real-Time Clock (RTC)                            */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for RTC_TR register  *******************/

+#define RTC_TR_PM_Pos                  (22U)

+#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */

+#define RTC_TR_PM                      RTC_TR_PM_Msk

+#define RTC_TR_HT_Pos                  (20U)

+#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */

+#define RTC_TR_HT                      RTC_TR_HT_Msk

+#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */

+#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */

+#define RTC_TR_HU_Pos                  (16U)

+#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */

+#define RTC_TR_HU                      RTC_TR_HU_Msk

+#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */

+#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */

+#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */

+#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */

+#define RTC_TR_MNT_Pos                 (12U)

+#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */

+#define RTC_TR_MNT                     RTC_TR_MNT_Msk

+#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */

+#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */

+#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */

+#define RTC_TR_MNU_Pos                 (8U)

+#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */

+#define RTC_TR_MNU                     RTC_TR_MNU_Msk

+#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */

+#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */

+#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */

+#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */

+#define RTC_TR_ST_Pos                  (4U)

+#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */

+#define RTC_TR_ST                      RTC_TR_ST_Msk

+#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */

+#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */

+#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */

+#define RTC_TR_SU_Pos                  (0U)

+#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */

+#define RTC_TR_SU                      RTC_TR_SU_Msk

+#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */

+#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */

+#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */

+#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_DR register  *******************/

+#define RTC_DR_YT_Pos                  (20U)

+#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */

+#define RTC_DR_YT                      RTC_DR_YT_Msk

+#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */

+#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */

+#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */

+#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */

+#define RTC_DR_YU_Pos                  (16U)

+#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */

+#define RTC_DR_YU                      RTC_DR_YU_Msk

+#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */

+#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */

+#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */

+#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */

+#define RTC_DR_WDU_Pos                 (13U)

+#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */

+#define RTC_DR_WDU                     RTC_DR_WDU_Msk

+#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */

+#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */

+#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */

+#define RTC_DR_MT_Pos                  (12U)

+#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */

+#define RTC_DR_MT                      RTC_DR_MT_Msk

+#define RTC_DR_MU_Pos                  (8U)

+#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */

+#define RTC_DR_MU                      RTC_DR_MU_Msk

+#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */

+#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */

+#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */

+#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */

+#define RTC_DR_DT_Pos                  (4U)

+#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */

+#define RTC_DR_DT                      RTC_DR_DT_Msk

+#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */

+#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */

+#define RTC_DR_DU_Pos                  (0U)

+#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */

+#define RTC_DR_DU                      RTC_DR_DU_Msk

+#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */

+#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */

+#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */

+#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_CR register  *******************/

+#define RTC_CR_OUT2EN_Pos            (31U)

+#define RTC_CR_OUT2EN_Msk            (0x1UL << RTC_CR_OUT2EN_Pos)              /*!< 0x80000000 */

+#define RTC_CR_OUT2EN                RTC_CR_OUT2EN_Msk                         /*!<RTC_OUT2 output enable */

+#define RTC_CR_TAMPALRM_TYPE_Pos     (30U)

+#define RTC_CR_TAMPALRM_TYPE_Msk     (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)       /*!< 0x40000000 */

+#define RTC_CR_TAMPALRM_TYPE         RTC_CR_TAMPALRM_TYPE_Msk                  /*!<TAMPALARM output type  */

+#define RTC_CR_TAMPALRM_PU_Pos       (29U)

+#define RTC_CR_TAMPALRM_PU_Msk       (0x1UL << RTC_CR_TAMPALRM_PU_Pos)         /*!< 0x20000000 */

+#define RTC_CR_TAMPALRM_PU           RTC_CR_TAMPALRM_PU_Msk                    /*!<TAMPALARM output pull-up config */

+#define RTC_CR_TAMPOE_Pos            (26U)

+#define RTC_CR_TAMPOE_Msk            (0x1UL << RTC_CR_TAMPOE_Pos)              /*!< 0x04000000 */

+#define RTC_CR_TAMPOE                RTC_CR_TAMPOE_Msk                         /*!<Tamper detection output enable on TAMPALARM  */

+#define RTC_CR_TAMPTS_Pos            (25U)

+#define RTC_CR_TAMPTS_Msk            (0x1UL << RTC_CR_TAMPTS_Pos)              /*!< 0x02000000 */

+#define RTC_CR_TAMPTS                RTC_CR_TAMPTS_Msk                         /*!<Activate timestamp on tamper detection event  */

+#define RTC_CR_ITSE_Pos                (24U)

+#define RTC_CR_ITSE_Msk                (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */

+#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk

+#define RTC_CR_COE_Pos                 (23U)

+#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */

+#define RTC_CR_COE                     RTC_CR_COE_Msk

+#define RTC_CR_OSEL_Pos                (21U)

+#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */

+#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk

+#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */

+#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */

+#define RTC_CR_POL_Pos                 (20U)

+#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */

+#define RTC_CR_POL                     RTC_CR_POL_Msk

+#define RTC_CR_COSEL_Pos               (19U)

+#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */

+#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk

+#define RTC_CR_BKP_Pos                 (18U)

+#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */

+#define RTC_CR_BKP                     RTC_CR_BKP_Msk

+#define RTC_CR_SUB1H_Pos               (17U)

+#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */

+#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk

+#define RTC_CR_ADD1H_Pos               (16U)

+#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */

+#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk

+#define RTC_CR_TSIE_Pos                (15U)

+#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */

+#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk

+#define RTC_CR_WUTIE_Pos               (14U)

+#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */

+#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk

+#define RTC_CR_ALRBIE_Pos              (13U)

+#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */

+#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk

+#define RTC_CR_ALRAIE_Pos              (12U)

+#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */

+#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk

+#define RTC_CR_TSE_Pos                 (11U)

+#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */

+#define RTC_CR_TSE                     RTC_CR_TSE_Msk

+#define RTC_CR_WUTE_Pos                (10U)

+#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */

+#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk

+#define RTC_CR_ALRBE_Pos               (9U)

+#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */

+#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk

+#define RTC_CR_ALRAE_Pos               (8U)

+#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */

+#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk

+#define RTC_CR_FMT_Pos                 (6U)

+#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */

+#define RTC_CR_FMT                     RTC_CR_FMT_Msk

+#define RTC_CR_BYPSHAD_Pos             (5U)

+#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */

+#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk

+#define RTC_CR_REFCKON_Pos             (4U)

+#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */

+#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk

+#define RTC_CR_TSEDGE_Pos              (3U)

+#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */

+#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk

+#define RTC_CR_WUCKSEL_Pos             (0U)

+#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */

+#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk

+#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */

+#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */

+#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */

+

+/********************  Bits definition for RTC_ICSR register  ******************/

+#define RTC_ICSR_RECALPF_Pos         (16U)

+#define RTC_ICSR_RECALPF_Msk         (0x1UL << RTC_ICSR_RECALPF_Pos)           /*!< 0x00010000 */

+#define RTC_ICSR_RECALPF             RTC_ICSR_RECALPF_Msk

+#define RTC_ICSR_INIT_Pos            (7U)

+#define RTC_ICSR_INIT_Msk            (0x1UL << RTC_ICSR_INIT_Pos)              /*!< 0x00000080 */

+#define RTC_ICSR_INIT                RTC_ICSR_INIT_Msk

+#define RTC_ICSR_INITF_Pos           (6U)

+#define RTC_ICSR_INITF_Msk           (0x1UL << RTC_ICSR_INITF_Pos)             /*!< 0x00000040 */

+#define RTC_ICSR_INITF               RTC_ICSR_INITF_Msk

+#define RTC_ICSR_RSF_Pos             (5U)

+#define RTC_ICSR_RSF_Msk             (0x1UL << RTC_ICSR_RSF_Pos)               /*!< 0x00000020 */

+#define RTC_ICSR_RSF                 RTC_ICSR_RSF_Msk

+#define RTC_ICSR_INITS_Pos           (4U)

+#define RTC_ICSR_INITS_Msk           (0x1UL << RTC_ICSR_INITS_Pos)             /*!< 0x00000010 */

+#define RTC_ICSR_INITS               RTC_ICSR_INITS_Msk

+#define RTC_ICSR_SHPF_Pos            (3U)

+#define RTC_ICSR_SHPF_Msk            (0x1UL << RTC_ICSR_SHPF_Pos)              /*!< 0x00000008 */

+#define RTC_ICSR_SHPF                RTC_ICSR_SHPF_Msk

+#define RTC_ICSR_WUTWF_Pos           (2U)

+#define RTC_ICSR_WUTWF_Msk           (0x1UL << RTC_ICSR_WUTWF_Pos)             /*!< 0x00000004 */

+#define RTC_ICSR_WUTWF               RTC_ICSR_WUTWF_Msk

+#define RTC_ICSR_ALRBWF_Pos          (1U)

+#define RTC_ICSR_ALRBWF_Msk          (0x1UL << RTC_ICSR_ALRBWF_Pos)            /*!< 0x00000002 */

+#define RTC_ICSR_ALRBWF              RTC_ICSR_ALRBWF_Msk

+#define RTC_ICSR_ALRAWF_Pos          (0U)

+#define RTC_ICSR_ALRAWF_Msk          (0x1UL << RTC_ICSR_ALRAWF_Pos)            /*!< 0x00000001 */

+#define RTC_ICSR_ALRAWF              RTC_ICSR_ALRAWF_Msk

+

+/********************  Bits definition for RTC_PRER register  *****************/

+#define RTC_PRER_PREDIV_A_Pos          (16U)

+#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */

+#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk

+#define RTC_PRER_PREDIV_S_Pos          (0U)

+#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */

+#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk

+

+/********************  Bits definition for RTC_WUTR register  *****************/

+#define RTC_WUTR_WUT_Pos               (0U)

+#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */

+#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk

+

+/********************  Bits definition for RTC_ALRMAR register  ***************/

+#define RTC_ALRMAR_MSK4_Pos            (31U)

+#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */

+#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk

+#define RTC_ALRMAR_WDSEL_Pos           (30U)

+#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */

+#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk

+#define RTC_ALRMAR_DT_Pos              (28U)

+#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */

+#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk

+#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */

+#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */

+#define RTC_ALRMAR_DU_Pos              (24U)

+#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */

+#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk

+#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */

+#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */

+#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */

+#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */

+#define RTC_ALRMAR_MSK3_Pos            (23U)

+#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */

+#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk

+#define RTC_ALRMAR_PM_Pos              (22U)

+#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */

+#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk

+#define RTC_ALRMAR_HT_Pos              (20U)

+#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */

+#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk

+#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */

+#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */

+#define RTC_ALRMAR_HU_Pos              (16U)

+#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */

+#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk

+#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */

+#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */

+#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */

+#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */

+#define RTC_ALRMAR_MSK2_Pos            (15U)

+#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */

+#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk

+#define RTC_ALRMAR_MNT_Pos             (12U)

+#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */

+#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk

+#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */

+#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */

+#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */

+#define RTC_ALRMAR_MNU_Pos             (8U)

+#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */

+#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk

+#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */

+#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */

+#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */

+#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */

+#define RTC_ALRMAR_MSK1_Pos            (7U)

+#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */

+#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk

+#define RTC_ALRMAR_ST_Pos              (4U)

+#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */

+#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk

+#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */

+#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */

+#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */

+#define RTC_ALRMAR_SU_Pos              (0U)

+#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */

+#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk

+#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */

+#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */

+#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */

+#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_ALRMBR register  ***************/

+#define RTC_ALRMBR_MSK4_Pos            (31U)

+#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */

+#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk

+#define RTC_ALRMBR_WDSEL_Pos           (30U)

+#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */

+#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk

+#define RTC_ALRMBR_DT_Pos              (28U)

+#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */

+#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk

+#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */

+#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */

+#define RTC_ALRMBR_DU_Pos              (24U)

+#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */

+#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk

+#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */

+#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */

+#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */

+#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */

+#define RTC_ALRMBR_MSK3_Pos            (23U)

+#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */

+#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk

+#define RTC_ALRMBR_PM_Pos              (22U)

+#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */

+#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk

+#define RTC_ALRMBR_HT_Pos              (20U)

+#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */

+#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk

+#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */

+#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */

+#define RTC_ALRMBR_HU_Pos              (16U)

+#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */

+#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk

+#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */

+#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */

+#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */

+#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */

+#define RTC_ALRMBR_MSK2_Pos            (15U)

+#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */

+#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk

+#define RTC_ALRMBR_MNT_Pos             (12U)

+#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */

+#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk

+#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */

+#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */

+#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */

+#define RTC_ALRMBR_MNU_Pos             (8U)

+#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */

+#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk

+#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */

+#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */

+#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */

+#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */

+#define RTC_ALRMBR_MSK1_Pos            (7U)

+#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */

+#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk

+#define RTC_ALRMBR_ST_Pos              (4U)

+#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */

+#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk

+#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */

+#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */

+#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */

+#define RTC_ALRMBR_SU_Pos              (0U)

+#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */

+#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk

+#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */

+#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */

+#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */

+#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_WPR register  ******************/

+#define RTC_WPR_KEY_Pos                (0U)

+#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */

+#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk

+

+/********************  Bits definition for RTC_SSR register  ******************/

+#define RTC_SSR_SS_Pos                 (0U)

+#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)            /*!< 0x0000FFFF */

+#define RTC_SSR_SS                     RTC_SSR_SS_Msk

+

+/********************  Bits definition for RTC_SHIFTR register  ***************/

+#define RTC_SHIFTR_SUBFS_Pos           (0U)

+#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */

+#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk

+#define RTC_SHIFTR_ADD1S_Pos           (31U)

+#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */

+#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk

+

+/********************  Bits definition for RTC_TSTR register  *****************/

+#define RTC_TSTR_PM_Pos                (22U)

+#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */

+#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk

+#define RTC_TSTR_HT_Pos                (20U)

+#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */

+#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk

+#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */

+#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */

+#define RTC_TSTR_HU_Pos                (16U)

+#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */

+#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk

+#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */

+#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */

+#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */

+#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */

+#define RTC_TSTR_MNT_Pos               (12U)

+#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */

+#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk

+#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */

+#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */

+#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */

+#define RTC_TSTR_MNU_Pos               (8U)

+#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */

+#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk

+#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */

+#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */

+#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */

+#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */

+#define RTC_TSTR_ST_Pos                (4U)

+#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */

+#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk

+#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */

+#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */

+#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */

+#define RTC_TSTR_SU_Pos                (0U)

+#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */

+#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk

+#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */

+#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */

+#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */

+#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_TSDR register  *****************/

+#define RTC_TSDR_WDU_Pos               (13U)

+#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */

+#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk

+#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */

+#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */

+#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */

+#define RTC_TSDR_MT_Pos                (12U)

+#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */

+#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk

+#define RTC_TSDR_MU_Pos                (8U)

+#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */

+#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk

+#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */

+#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */

+#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */

+#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */

+#define RTC_TSDR_DT_Pos                (4U)

+#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */

+#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk

+#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */

+#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */

+#define RTC_TSDR_DU_Pos                (0U)

+#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */

+#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk

+#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */

+#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */

+#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */

+#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_TSSSR register  ****************/

+#define RTC_TSSSR_SS_Pos               (0U)

+#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)          /*!< 0x0000FFFF */

+#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk

+

+/********************  Bits definition for RTC_CALR register  *****************/

+#define RTC_CALR_CALP_Pos              (15U)

+#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */

+#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk

+#define RTC_CALR_CALW8_Pos             (14U)

+#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */

+#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk

+#define RTC_CALR_CALW16_Pos            (13U)

+#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */

+#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk

+#define RTC_CALR_CALM_Pos              (0U)

+#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */

+#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk

+#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */

+#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */

+#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */

+#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */

+#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */

+#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */

+#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */

+#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */

+#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */

+

+

+/********************  Bits definition for RTC_ALRMASSR register  *************/

+#define RTC_ALRMASSR_MASKSS_Pos        (24U)

+#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x0F000000 */

+#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk

+#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */

+#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */

+#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */

+#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */

+#define RTC_ALRMASSR_SS_Pos            (0U)

+#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */

+#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk

+

+/********************  Bits definition for RTC_ALRMBSSR register  *************/

+#define RTC_ALRMBSSR_MASKSS_Pos        (24U)

+#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x0F000000 */

+#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk

+#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */

+#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */

+#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */

+#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */

+#define RTC_ALRMBSSR_SS_Pos            (0U)

+#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */

+#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk

+

+

+/********************  Bits definition for RTC_SR register  *******************/

+#define RTC_SR_ITSF_Pos              (5U)

+#define RTC_SR_ITSF_Msk              (0x1UL << RTC_SR_ITSF_Pos)                 /*!< 0x00000020 */

+#define RTC_SR_ITSF                  RTC_SR_ITSF_Msk

+#define RTC_SR_TSOVF_Pos             (4U)

+#define RTC_SR_TSOVF_Msk             (0x1UL << RTC_SR_TSOVF_Pos)                /*!< 0x00000010 */

+#define RTC_SR_TSOVF                 RTC_SR_TSOVF_Msk

+#define RTC_SR_TSF_Pos               (3U)

+#define RTC_SR_TSF_Msk               (0x1UL << RTC_SR_TSF_Pos)                  /*!< 0x00000008 */

+#define RTC_SR_TSF                   RTC_SR_TSF_Msk

+#define RTC_SR_WUTF_Pos              (2U)

+#define RTC_SR_WUTF_Msk              (0x1UL << RTC_SR_WUTF_Pos)                 /*!< 0x00000004 */

+#define RTC_SR_WUTF                  RTC_SR_WUTF_Msk

+#define RTC_SR_ALRBF_Pos             (1U)

+#define RTC_SR_ALRBF_Msk             (0x1UL << RTC_SR_ALRBF_Pos)                /*!< 0x00000002 */

+#define RTC_SR_ALRBF                 RTC_SR_ALRBF_Msk

+#define RTC_SR_ALRAF_Pos             (0U)

+#define RTC_SR_ALRAF_Msk             (0x1UL << RTC_SR_ALRAF_Pos)                /*!< 0x00000001 */

+#define RTC_SR_ALRAF                 RTC_SR_ALRAF_Msk

+

+/********************  Bits definition for RTC_MISR register  *****************/

+#define RTC_MISR_ITSMF_Pos           (5U)

+#define RTC_MISR_ITSMF_Msk           (0x1UL << RTC_MISR_ITSMF_Pos)              /*!< 0x00000020 */

+#define RTC_MISR_ITSMF               RTC_MISR_ITSMF_Msk

+#define RTC_MISR_TSOVMF_Pos          (4U)

+#define RTC_MISR_TSOVMF_Msk          (0x1UL << RTC_MISR_TSOVMF_Pos)             /*!< 0x00000010 */

+#define RTC_MISR_TSOVMF              RTC_MISR_TSOVMF_Msk

+#define RTC_MISR_TSMF_Pos            (3U)

+#define RTC_MISR_TSMF_Msk            (0x1UL << RTC_MISR_TSMF_Pos)               /*!< 0x00000008 */

+#define RTC_MISR_TSMF                RTC_MISR_TSMF_Msk

+#define RTC_MISR_WUTMF_Pos           (2U)

+#define RTC_MISR_WUTMF_Msk           (0x1UL << RTC_MISR_WUTMF_Pos)              /*!< 0x00000004 */

+#define RTC_MISR_WUTMF               RTC_MISR_WUTMF_Msk

+#define RTC_MISR_ALRBMF_Pos          (1U)

+#define RTC_MISR_ALRBMF_Msk          (0x1UL << RTC_MISR_ALRBMF_Pos)             /*!< 0x00000002 */

+#define RTC_MISR_ALRBMF              RTC_MISR_ALRBMF_Msk

+#define RTC_MISR_ALRAMF_Pos          (0U)

+#define RTC_MISR_ALRAMF_Msk          (0x1UL << RTC_MISR_ALRAMF_Pos)             /*!< 0x00000001 */

+#define RTC_MISR_ALRAMF              RTC_MISR_ALRAMF_Msk

+

+/********************  Bits definition for RTC_SCR register  ******************/

+#define RTC_SCR_CITSF_Pos            (5U)

+#define RTC_SCR_CITSF_Msk            (0x1UL << RTC_SCR_CITSF_Pos)               /*!< 0x00000020 */

+#define RTC_SCR_CITSF                RTC_SCR_CITSF_Msk

+#define RTC_SCR_CTSOVF_Pos           (4U)

+#define RTC_SCR_CTSOVF_Msk           (0x1UL << RTC_SCR_CTSOVF_Pos)              /*!< 0x00000010 */

+#define RTC_SCR_CTSOVF               RTC_SCR_CTSOVF_Msk

+#define RTC_SCR_CTSF_Pos             (3U)

+#define RTC_SCR_CTSF_Msk             (0x1UL << RTC_SCR_CTSF_Pos)                /*!< 0x00000008 */

+#define RTC_SCR_CTSF                 RTC_SCR_CTSF_Msk

+#define RTC_SCR_CWUTF_Pos            (2U)

+#define RTC_SCR_CWUTF_Msk            (0x1UL << RTC_SCR_CWUTF_Pos)               /*!< 0x00000004 */

+#define RTC_SCR_CWUTF                RTC_SCR_CWUTF_Msk

+#define RTC_SCR_CALRBF_Pos           (1U)

+#define RTC_SCR_CALRBF_Msk           (0x1UL << RTC_SCR_CALRBF_Pos)              /*!< 0x00000002 */

+#define RTC_SCR_CALRBF               RTC_SCR_CALRBF_Msk

+#define RTC_SCR_CALRAF_Pos           (0U)

+#define RTC_SCR_CALRAF_Msk           (0x1UL << RTC_SCR_CALRAF_Pos)              /*!< 0x00000001 */

+#define RTC_SCR_CALRAF               RTC_SCR_CALRAF_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                     Tamper and backup register (TAMP)                      */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for TAMP_CR1 register  *****************/

+#define TAMP_CR1_TAMP1E_Pos          (0U)

+#define TAMP_CR1_TAMP1E_Msk          (0x1UL << TAMP_CR1_TAMP1E_Pos)            /*!< 0x00000001 */

+#define TAMP_CR1_TAMP1E              TAMP_CR1_TAMP1E_Msk

+#define TAMP_CR1_TAMP2E_Pos          (1U)

+#define TAMP_CR1_TAMP2E_Msk          (0x1UL << TAMP_CR1_TAMP2E_Pos)            /*!< 0x00000002 */

+#define TAMP_CR1_TAMP2E              TAMP_CR1_TAMP2E_Msk

+#define TAMP_CR1_TAMP3E_Pos          (2U)

+#define TAMP_CR1_TAMP3E_Msk          (0x1UL << TAMP_CR1_TAMP3E_Pos)            /*!< 0x00000004 */

+#define TAMP_CR1_TAMP3E              TAMP_CR1_TAMP3E_Msk

+#define TAMP_CR1_ITAMP1E_Pos         (16U)

+#define TAMP_CR1_ITAMP1E_Msk         (0x1UL << TAMP_CR1_ITAMP1E_Pos)           /*!< 0x00010000 */

+#define TAMP_CR1_ITAMP1E             TAMP_CR1_ITAMP1E_Msk

+#define TAMP_CR1_ITAMP2E_Pos         (17U)

+#define TAMP_CR1_ITAMP2E_Msk         (0x1UL << TAMP_CR1_ITAMP2E_Pos)           /*!< 0x00020000 */

+#define TAMP_CR1_ITAMP2E             TAMP_CR1_ITAMP2E_Msk

+#define TAMP_CR1_ITAMP3E_Pos         (18U)

+#define TAMP_CR1_ITAMP3E_Msk         (0x1UL << TAMP_CR1_ITAMP3E_Pos)           /*!< 0x00040000 */

+#define TAMP_CR1_ITAMP3E             TAMP_CR1_ITAMP3E_Msk

+#define TAMP_CR1_ITAMP4E_Pos         (19U)

+#define TAMP_CR1_ITAMP4E_Msk         (0x1UL << TAMP_CR1_ITAMP4E_Pos)           /*!< 0x00080000 */

+#define TAMP_CR1_ITAMP4E             TAMP_CR1_ITAMP4E_Msk

+#define TAMP_CR1_ITAMP5E_Pos         (20U)

+#define TAMP_CR1_ITAMP5E_Msk         (0x1UL << TAMP_CR1_ITAMP5E_Pos)           /*!< 0x00100000 */

+#define TAMP_CR1_ITAMP5E             TAMP_CR1_ITAMP5E_Msk

+#define TAMP_CR1_ITAMP6E_Pos         (21U)

+#define TAMP_CR1_ITAMP6E_Msk         (0x1UL << TAMP_CR1_ITAMP6E_Pos)           /*!< 0x00200000 */

+#define TAMP_CR1_ITAMP6E             TAMP_CR1_ITAMP6E_Msk

+#define TAMP_CR1_ITAMP8E_Pos         (23U)

+#define TAMP_CR1_ITAMP8E_Msk         (0x1UL << TAMP_CR1_ITAMP8E_Pos)           /*!< 0x00800000 */

+#define TAMP_CR1_ITAMP8E             TAMP_CR1_ITAMP8E_Msk

+

+/********************  Bits definition for TAMP_CR2 register  *****************/

+#define TAMP_CR2_TAMP1NOERASE_Pos    (0U)

+#define TAMP_CR2_TAMP1NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)      /*!< 0x00000001 */

+#define TAMP_CR2_TAMP1NOERASE        TAMP_CR2_TAMP1NOERASE_Msk

+#define TAMP_CR2_TAMP2NOERASE_Pos    (1U)

+#define TAMP_CR2_TAMP2NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)      /*!< 0x00000002 */

+#define TAMP_CR2_TAMP2NOERASE        TAMP_CR2_TAMP2NOERASE_Msk

+#define TAMP_CR2_TAMP3NOERASE_Pos    (2U)

+#define TAMP_CR2_TAMP3NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos)      /*!< 0x00000004 */

+#define TAMP_CR2_TAMP3NOERASE        TAMP_CR2_TAMP3NOERASE_Msk

+#define TAMP_CR2_TAMP1MSK_Pos        (16U)

+#define TAMP_CR2_TAMP1MSK_Msk        (0x1UL << TAMP_CR2_TAMP1MSK_Pos)          /*!< 0x00010000 */

+#define TAMP_CR2_TAMP1MSK            TAMP_CR2_TAMP1MSK_Msk

+#define TAMP_CR2_TAMP2MSK_Pos        (17U)

+#define TAMP_CR2_TAMP2MSK_Msk        (0x1UL << TAMP_CR2_TAMP2MSK_Pos)          /*!< 0x00020000 */

+#define TAMP_CR2_TAMP2MSK            TAMP_CR2_TAMP2MSK_Msk

+#define TAMP_CR2_TAMP3MSK_Pos        (18U)

+#define TAMP_CR2_TAMP3MSK_Msk        (0x1UL << TAMP_CR2_TAMP3MSK_Pos)          /*!< 0x00040000 */

+#define TAMP_CR2_TAMP3MSK            TAMP_CR2_TAMP3MSK_Msk

+#define TAMP_CR2_TAMP1TRG_Pos        (24U)

+#define TAMP_CR2_TAMP1TRG_Msk        (0x1UL << TAMP_CR2_TAMP1TRG_Pos)          /*!< 0x01000000 */

+#define TAMP_CR2_TAMP1TRG            TAMP_CR2_TAMP1TRG_Msk

+#define TAMP_CR2_TAMP2TRG_Pos        (25U)

+#define TAMP_CR2_TAMP2TRG_Msk        (0x1UL << TAMP_CR2_TAMP2TRG_Pos)          /*!< 0x02000000 */

+#define TAMP_CR2_TAMP2TRG            TAMP_CR2_TAMP2TRG_Msk

+#define TAMP_CR2_TAMP3TRG_Pos        (26U)

+#define TAMP_CR2_TAMP3TRG_Msk        (0x1UL << TAMP_CR2_TAMP3TRG_Pos)          /*!< 0x04000000 */

+#define TAMP_CR2_TAMP3TRG            TAMP_CR2_TAMP3TRG_Msk

+

+/********************  Bits definition for TAMP_FLTCR register  ***************/

+#define TAMP_FLTCR_TAMPFREQ_Pos      (0U)

+#define TAMP_FLTCR_TAMPFREQ_Msk      (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000007 */

+#define TAMP_FLTCR_TAMPFREQ          TAMP_FLTCR_TAMPFREQ_Msk

+#define TAMP_FLTCR_TAMPFREQ_0        (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000001 */

+#define TAMP_FLTCR_TAMPFREQ_1        (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000002 */

+#define TAMP_FLTCR_TAMPFREQ_2        (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000004 */

+#define TAMP_FLTCR_TAMPFLT_Pos       (3U)

+#define TAMP_FLTCR_TAMPFLT_Msk       (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000018 */

+#define TAMP_FLTCR_TAMPFLT           TAMP_FLTCR_TAMPFLT_Msk

+#define TAMP_FLTCR_TAMPFLT_0         (0x1UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000008 */

+#define TAMP_FLTCR_TAMPFLT_1         (0x2UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000010 */

+#define TAMP_FLTCR_TAMPPRCH_Pos      (5U)

+#define TAMP_FLTCR_TAMPPRCH_Msk      (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000060 */

+#define TAMP_FLTCR_TAMPPRCH          TAMP_FLTCR_TAMPPRCH_Msk

+#define TAMP_FLTCR_TAMPPRCH_0        (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000020 */

+#define TAMP_FLTCR_TAMPPRCH_1        (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000040 */

+#define TAMP_FLTCR_TAMPPUDIS_Pos     (7U)

+#define TAMP_FLTCR_TAMPPUDIS_Msk     (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)        /*!< 0x00000080 */

+#define TAMP_FLTCR_TAMPPUDIS         TAMP_FLTCR_TAMPPUDIS_Msk

+

+/*******************  Bits definition for TAMP_ATCR1 register  ****************/

+#define TAMP_ATCR1_TAMP1AM_Pos       (0U)

+#define TAMP_ATCR1_TAMP1AM_Msk       (0x1UL << TAMP_ATCR1_TAMP1AM_Pos)         /*!< 0x00000001 */

+#define TAMP_ATCR1_TAMP1AM           TAMP_ATCR1_TAMP1AM_Msk

+#define TAMP_ATCR1_TAMP2AM_Pos       (1U)

+#define TAMP_ATCR1_TAMP2AM_Msk       (0x1UL << TAMP_ATCR1_TAMP2AM_Pos)         /*!< 0x00000002 */

+#define TAMP_ATCR1_TAMP2AM           TAMP_ATCR1_TAMP2AM_Msk

+#define TAMP_ATCR1_TAMP3AM_Pos       (2U)

+#define TAMP_ATCR1_TAMP3AM_Msk       (0x1UL << TAMP_ATCR1_TAMP3AM_Pos)         /*!< 0x00000004 */

+#define TAMP_ATCR1_TAMP3AM           TAMP_ATCR1_TAMP3AM_Msk

+#define TAMP_ATCR1_ATOSEL1_Pos       (8U)

+#define TAMP_ATCR1_ATOSEL1_Msk       (0x3UL << TAMP_ATCR1_ATOSEL1_Pos)          /*!< 0x00000300 */

+#define TAMP_ATCR1_ATOSEL1            TAMP_ATCR1_ATOSEL1_Msk

+#define TAMP_ATCR1_ATOSEL1_0         (0x1UL << TAMP_ATCR1_ATOSEL1_Pos)         /*!< 0x00000100 */

+#define TAMP_ATCR1_ATOSEL1_1         (0x2UL << TAMP_ATCR1_ATOSEL1_Pos)         /*!< 0x00000200 */

+#define TAMP_ATCR1_ATOSEL2_Pos       (10U)

+#define TAMP_ATCR1_ATOSEL2_Msk       (0x3UL << TAMP_ATCR1_ATOSEL2_Pos)          /*!< 0x00000C00 */

+#define TAMP_ATCR1_ATOSEL2            TAMP_ATCR1_ATOSEL2_Msk

+#define TAMP_ATCR1_ATOSEL2_0         (0x1UL << TAMP_ATCR1_ATOSEL2_Pos)         /*!< 0x00000400 */

+#define TAMP_ATCR1_ATOSEL2_1         (0x2UL << TAMP_ATCR1_ATOSEL2_Pos)         /*!< 0x00000800 */

+#define TAMP_ATCR1_ATOSEL3_Pos       (12U)

+#define TAMP_ATCR1_ATOSEL3_Msk       (0x3UL << TAMP_ATCR1_ATOSEL3_Pos)          /*!< 0x00003000 */

+#define TAMP_ATCR1_ATOSEL3            TAMP_ATCR1_ATOSEL3_Msk

+#define TAMP_ATCR1_ATOSEL3_0         (0x1UL << TAMP_ATCR1_ATOSEL3_Pos)         /*!< 0x00001000 */

+#define TAMP_ATCR1_ATOSEL3_1         (0x2UL << TAMP_ATCR1_ATOSEL3_Pos)         /*!< 0x00002000 */

+#define TAMP_ATCR1_ATOSEL4_Pos       (14U)

+#define TAMP_ATCR1_ATOSEL4_Msk       (0x3UL << TAMP_ATCR1_ATOSEL4_Pos)          /*!< 0x0000C000 */

+#define TAMP_ATCR1_ATOSEL4            TAMP_ATCR1_ATOSEL4_Msk

+#define TAMP_ATCR1_ATOSEL4_0         (0x1UL << TAMP_ATCR1_ATOSEL4_Pos)         /*!< 0x00004000 */

+#define TAMP_ATCR1_ATOSEL4_1         (0x2UL << TAMP_ATCR1_ATOSEL4_Pos)         /*!< 0x00008000 */

+#define TAMP_ATCR1_ATCKSEL_Pos       (16U)

+#define TAMP_ATCR1_ATCKSEL_Msk       (0x7UL << TAMP_ATCR1_ATCKSEL_Pos)          /*!< 0x00070000 */

+#define TAMP_ATCR1_ATCKSEL            TAMP_ATCR1_ATCKSEL_Msk

+#define TAMP_ATCR1_ATCKSEL_0         (0x1UL << TAMP_ATCR1_ATCKSEL_Pos)         /*!< 0x00010000 */

+#define TAMP_ATCR1_ATCKSEL_1         (0x2UL << TAMP_ATCR1_ATCKSEL_Pos)         /*!< 0x00020000 */

+#define TAMP_ATCR1_ATCKSEL_2         (0x4UL << TAMP_ATCR1_ATCKSEL_Pos)         /*!< 0x00040000 */

+#define TAMP_ATCR1_ATPER_Pos         (24U)

+#define TAMP_ATCR1_ATPER_Msk         (0x7UL << TAMP_ATCR1_ATPER_Pos)           /*!< 0x07000000 */

+#define TAMP_ATCR1_ATPER             TAMP_ATCR1_ATPER_Msk

+#define TAMP_ATCR1_ATOSHARE_Pos      (30U)

+#define TAMP_ATCR1_ATOSHARE_Msk      (0x1UL << TAMP_ATCR1_ATOSHARE_Pos)        /*!< 0x40000000 */

+#define TAMP_ATCR1_ATOSHARE          TAMP_ATCR1_ATOSHARE_Msk

+#define TAMP_ATCR1_FLTEN_Pos         (31U)

+#define TAMP_ATCR1_FLTEN_Msk         (0x1UL << TAMP_ATCR1_FLTEN_Pos)           /*!< 0x80000000 */

+#define TAMP_ATCR1_FLTEN             TAMP_ATCR1_FLTEN_Msk

+

+/********************  Bits definition for TAMP_ATSEEDR register  *************/

+#define TAMP_ATSEEDR_SEED_Pos        (0U)

+#define TAMP_ATSEEDR_SEED_Msk        (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos)   /*!< 0xFFFFFFFF */

+#define TAMP_ATSEEDR_SEED            TAMP_ATSEEDR_SEED_Msk

+

+/********************  Bits definition for TAMP_ATOR register  ****************/

+#define TAMP_ATOR_PRNG_Pos           (0U)

+#define TAMP_ATOR_PRNG_Msk           (0x000000FFUL << TAMP_ATOR_PRNG_Pos)      /*!< 0x000000FF */

+#define TAMP_ATOR_PRNG               TAMP_ATOR_PRNG_Msk

+#define TAMP_ATOR_SEEDF_Pos          (14U)

+#define TAMP_ATOR_SEEDF_Msk          (0x01UL << TAMP_ATOR_SEEDF_Pos)           /*!< 0x00004000 */

+#define TAMP_ATOR_SEEDF              TAMP_ATOR_SEEDF_Msk

+#define TAMP_ATOR_INITS_Pos          (15U)

+#define TAMP_ATOR_INITS_Msk          (0x01UL << TAMP_ATOR_INITS_Pos)           /*!< 0x00008000 */

+#define TAMP_ATOR_INITS              TAMP_ATOR_INITS_Msk

+

+/********************  Bits definition for TAMP_IER register  *****************/

+#define TAMP_IER_TAMP1IE_Pos         (0U)

+#define TAMP_IER_TAMP1IE_Msk         (0x1UL << TAMP_IER_TAMP1IE_Pos)           /*!< 0x00000001 */

+#define TAMP_IER_TAMP1IE             TAMP_IER_TAMP1IE_Msk

+#define TAMP_IER_TAMP2IE_Pos         (1U)

+#define TAMP_IER_TAMP2IE_Msk         (0x1UL << TAMP_IER_TAMP2IE_Pos)           /*!< 0x00000002 */

+#define TAMP_IER_TAMP2IE             TAMP_IER_TAMP2IE_Msk

+#define TAMP_IER_TAMP3IE_Pos         (2U)

+#define TAMP_IER_TAMP3IE_Msk         (0x1UL << TAMP_IER_TAMP3IE_Pos)           /*!< 0x00000004 */

+#define TAMP_IER_TAMP3IE             TAMP_IER_TAMP3IE_Msk

+#define TAMP_IER_ITAMP1IE_Pos        (16U)

+#define TAMP_IER_ITAMP1IE_Msk        (0x1UL << TAMP_IER_ITAMP1IE_Pos)          /*!< 0x00010000 */

+#define TAMP_IER_ITAMP1IE            TAMP_IER_ITAMP1IE_Msk

+#define TAMP_IER_ITAMP2IE_Pos        (17U)

+#define TAMP_IER_ITAMP2IE_Msk        (0x1UL << TAMP_IER_ITAMP2IE_Pos)          /*!< 0x00020000 */

+#define TAMP_IER_ITAMP2IE            TAMP_IER_ITAMP2IE_Msk

+#define TAMP_IER_ITAMP3IE_Pos        (18U)

+#define TAMP_IER_ITAMP3IE_Msk        (0x1UL << TAMP_IER_ITAMP3IE_Pos)          /*!< 0x00040000 */

+#define TAMP_IER_ITAMP3IE            TAMP_IER_ITAMP3IE_Msk

+#define TAMP_IER_ITAMP4IE_Pos        (19U)

+#define TAMP_IER_ITAMP4IE_Msk        (0x1UL << TAMP_IER_ITAMP4IE_Pos)          /*!< 0x00080000 */

+#define TAMP_IER_ITAMP4IE            TAMP_IER_ITAMP4IE_Msk

+#define TAMP_IER_ITAMP5IE_Pos        (20U)

+#define TAMP_IER_ITAMP5IE_Msk        (0x1UL << TAMP_IER_ITAMP5IE_Pos)          /*!< 0x00100000 */

+#define TAMP_IER_ITAMP5IE            TAMP_IER_ITAMP5IE_Msk

+#define TAMP_IER_ITAMP6IE_Pos        (21U)

+#define TAMP_IER_ITAMP6IE_Msk        (0x1UL << TAMP_IER_ITAMP6IE_Pos)          /*!< 0x00200000 */

+#define TAMP_IER_ITAMP6IE            TAMP_IER_ITAMP6IE_Msk

+#define TAMP_IER_ITAMP8IE_Pos        (23U)

+#define TAMP_IER_ITAMP8IE_Msk        (0x1UL << TAMP_IER_ITAMP8IE_Pos)          /*!< 0x00800000 */

+#define TAMP_IER_ITAMP8IE            TAMP_IER_ITAMP8IE_Msk

+

+/********************  Bits definition for TAMP_SR register  *****************/

+#define TAMP_SR_TAMP1F_Pos           (0U)

+#define TAMP_SR_TAMP1F_Msk           (0x1UL << TAMP_SR_TAMP1F_Pos)             /*!< 0x00000001 */

+#define TAMP_SR_TAMP1F               TAMP_SR_TAMP1F_Msk

+#define TAMP_SR_TAMP2F_Pos           (1U)

+#define TAMP_SR_TAMP2F_Msk           (0x1UL << TAMP_SR_TAMP2F_Pos)             /*!< 0x00000002 */

+#define TAMP_SR_TAMP2F               TAMP_SR_TAMP2F_Msk

+#define TAMP_SR_TAMP3F_Pos           (2U)

+#define TAMP_SR_TAMP3F_Msk           (0x1UL << TAMP_SR_TAMP3F_Pos)             /*!< 0x00000004 */

+#define TAMP_SR_TAMP3F               TAMP_SR_TAMP3F_Msk

+#define TAMP_SR_ITAMP1F_Pos          (16U)

+#define TAMP_SR_ITAMP1F_Msk          (0x1UL << TAMP_SR_ITAMP1F_Pos)            /*!< 0x00010000 */

+#define TAMP_SR_ITAMP1F              TAMP_SR_ITAMP1F_Msk

+#define TAMP_SR_ITAMP2F_Pos          (17U)

+#define TAMP_SR_ITAMP2F_Msk          (0x1UL << TAMP_SR_ITAMP2F_Pos)            /*!< 0x00020000 */

+#define TAMP_SR_ITAMP2F              TAMP_SR_ITAMP2F_Msk

+#define TAMP_SR_ITAMP3F_Pos          (18U)

+#define TAMP_SR_ITAMP3F_Msk          (0x1UL << TAMP_SR_ITAMP3F_Pos)            /*!< 0x00040000 */

+#define TAMP_SR_ITAMP3F              TAMP_SR_ITAMP3F_Msk

+#define TAMP_SR_ITAMP4F_Pos          (19U)

+#define TAMP_SR_ITAMP4F_Msk          (0x1UL << TAMP_SR_ITAMP4F_Pos)            /*!< 0x00080000 */

+#define TAMP_SR_ITAMP4F              TAMP_SR_ITAMP4F_Msk

+#define TAMP_SR_ITAMP5F_Pos          (20U)

+#define TAMP_SR_ITAMP5F_Msk          (0x1UL << TAMP_SR_ITAMP5F_Pos)            /*!< 0x00100000 */

+#define TAMP_SR_ITAMP5F              TAMP_SR_ITAMP5F_Msk

+#define TAMP_SR_ITAMP6F_Pos          (21U)

+#define TAMP_SR_ITAMP6F_Msk          (0x1UL << TAMP_SR_ITAMP6F_Pos)            /*!< 0x00200000 */

+#define TAMP_SR_ITAMP6F              TAMP_SR_ITAMP6F_Msk

+#define TAMP_SR_ITAMP8F_Pos          (23U)

+#define TAMP_SR_ITAMP8F_Msk          (0x1UL << TAMP_SR_ITAMP8F_Pos)            /*!< 0x00800000 */

+#define TAMP_SR_ITAMP8F              TAMP_SR_ITAMP8F_Msk

+

+/********************  Bits definition for TAMP_MISR register  ************ *****/

+#define TAMP_MISR_TAMP1MF_Pos        (0U)

+#define TAMP_MISR_TAMP1MF_Msk        (0x1UL << TAMP_MISR_TAMP1MF_Pos)           /*!< 0x00000001 */

+#define TAMP_MISR_TAMP1MF            TAMP_MISR_TAMP1MF_Msk

+#define TAMP_MISR_TAMP2MF_Pos        (1U)

+#define TAMP_MISR_TAMP2MF_Msk        (0x1UL << TAMP_MISR_TAMP2MF_Pos)           /*!< 0x00000002 */

+#define TAMP_MISR_TAMP2MF            TAMP_MISR_TAMP2MF_Msk

+#define TAMP_MISR_TAMP3MF_Pos        (2U)

+#define TAMP_MISR_TAMP3MF_Msk        (0x1UL << TAMP_MISR_TAMP3MF_Pos)          /*!< 0x00000004 */

+#define TAMP_MISR_TAMP3MF            TAMP_MISR_TAMP3MF_Msk

+#define TAMP_MISR_ITAMP1MF_Pos       (16U)

+#define TAMP_MISR_ITAMP1MF_Msk       (0x1UL << TAMP_MISR_ITAMP1MF_Pos)         /*!< 0x00010000 */

+#define TAMP_MISR_ITAMP1MF           TAMP_MISR_ITAMP1MF_Msk

+#define TAMP_MISR_ITAMP2MF_Pos       (17U)

+#define TAMP_MISR_ITAMP2MF_Msk       (0x1UL << TAMP_MISR_ITAMP2MF_Pos)         /*!< 0x00020000 */

+#define TAMP_MISR_ITAMP2MF           TAMP_MISR_ITAMP2MF_Msk

+#define TAMP_MISR_ITAMP3MF_Pos       (18U)

+#define TAMP_MISR_ITAMP3MF_Msk       (0x1UL << TAMP_MISR_ITAMP3MF_Pos)         /*!< 0x00040000 */

+#define TAMP_MISR_ITAMP3MF           TAMP_MISR_ITAMP3MF_Msk

+#define TAMP_MISR_ITAMP4MF_Pos       (19U)

+#define TAMP_MISR_ITAMP4MF_Msk       (0x1UL << TAMP_MISR_ITAMP4MF_Pos)         /*!< 0x00080000 */

+#define TAMP_MISR_ITAMP4MF           TAMP_MISR_ITAMP4MF_Msk

+#define TAMP_MISR_ITAMP5MF_Pos       (20U)

+#define TAMP_MISR_ITAMP5MF_Msk       (0x1UL << TAMP_MISR_ITAMP5MF_Pos)         /*!< 0x00100000 */

+#define TAMP_MISR_ITAMP5MF           TAMP_MISR_ITAMP5MF_Msk

+#define TAMP_MISR_ITAMP6MF_Pos       (21U)

+#define TAMP_MISR_ITAMP6MF_Msk       (0x1UL << TAMP_MISR_ITAMP6MF_Pos)         /*!< 0x00200000 */

+#define TAMP_MISR_ITAMP6MF           TAMP_MISR_ITAMP6MF_Msk

+#define TAMP_MISR_ITAMP8MF_Pos       (23U)

+#define TAMP_MISR_ITAMP8MF_Msk       (0x1UL << TAMP_MISR_ITAMP8MF_Pos)         /*!< 0x00800000 */

+#define TAMP_MISR_ITAMP8MF           TAMP_MISR_ITAMP8MF_Msk

+

+/********************  Bits definition for TAMP_SCR register  *****************/

+#define TAMP_SCR_CTAMP1F_Pos         (0U)

+#define TAMP_SCR_CTAMP1F_Msk         (0x1UL << TAMP_SCR_CTAMP1F_Pos)            /*!< 0x00000001 */

+#define TAMP_SCR_CTAMP1F             TAMP_SCR_CTAMP1F_Msk

+#define TAMP_SCR_CTAMP2F_Pos         (1U)

+#define TAMP_SCR_CTAMP2F_Msk         (0x1UL << TAMP_SCR_CTAMP2F_Pos)            /*!< 0x00000002 */

+#define TAMP_SCR_CTAMP2F             TAMP_SCR_CTAMP2F_Msk

+#define TAMP_SCR_CTAMP3F_Pos         (2U)

+#define TAMP_SCR_CTAMP3F_Msk         (0x1UL << TAMP_SCR_CTAMP3F_Pos)           /*!< 0x00000004 */

+#define TAMP_SCR_CTAMP3F             TAMP_SCR_CTAMP3F_Msk

+#define TAMP_SCR_CITAMP1F_Pos        (16U)

+#define TAMP_SCR_CITAMP1F_Msk        (0x1UL << TAMP_SCR_CITAMP1F_Pos)          /*!< 0x00010000 */

+#define TAMP_SCR_CITAMP1F            TAMP_SCR_CITAMP1F_Msk

+#define TAMP_SCR_CITAMP2F_Pos        (17U)

+#define TAMP_SCR_CITAMP2F_Msk        (0x1UL << TAMP_SCR_CITAMP2F_Pos)          /*!< 0x00020000 */

+#define TAMP_SCR_CITAMP2F            TAMP_SCR_CITAMP2F_Msk

+#define TAMP_SCR_CITAMP3F_Pos        (18U)

+#define TAMP_SCR_CITAMP3F_Msk        (0x1UL << TAMP_SCR_CITAMP3F_Pos)          /*!< 0x00040000 */

+#define TAMP_SCR_CITAMP3F            TAMP_SCR_CITAMP3F_Msk

+#define TAMP_SCR_CITAMP4F_Pos        (19U)

+#define TAMP_SCR_CITAMP4F_Msk        (0x1UL << TAMP_SCR_CITAMP4F_Pos)          /*!< 0x00080000 */

+#define TAMP_SCR_CITAMP4F            TAMP_SCR_CITAMP4F_Msk

+#define TAMP_SCR_CITAMP5F_Pos        (20U)

+#define TAMP_SCR_CITAMP5F_Msk        (0x1UL << TAMP_SCR_CITAMP5F_Pos)          /*!< 0x00100000 */

+#define TAMP_SCR_CITAMP5F            TAMP_SCR_CITAMP5F_Msk

+#define TAMP_SCR_CITAMP6F_Pos        (21U)

+#define TAMP_SCR_CITAMP6F_Msk        (0x1UL << TAMP_SCR_CITAMP6F_Pos)          /*!< 0x00200000 */

+#define TAMP_SCR_CITAMP6F            TAMP_SCR_CITAMP6F_Msk

+#define TAMP_SCR_CITAMP8F_Pos        (23U)

+#define TAMP_SCR_CITAMP8F_Msk        (0x1UL << TAMP_SCR_CITAMP8F_Pos)          /*!< 0x00800000 */

+#define TAMP_SCR_CITAMP8F            TAMP_SCR_CITAMP8F_Msk

+

+/********************  Bits definition for TAMP_COUNTR register  **************/

+#define TAMP_COUNTR_Pos              (16U)

+#define TAMP_COUNTR_Msk              (0xFFFFUL << TAMP_COUNTR_Pos)             /*!< 0xFFFF0000 */

+#define TAMP_COUNTR                  TAMP_COUNTR_Msk

+

+/********************  Bits definition for TAMP_OR register  ******************/

+#define TAMP_OR_OUT3_RMP_Pos         (0U)

+#define TAMP_OR_OUT3_RMP_Msk         (0x1UL << TAMP_OR_OUT3_RMP_Pos)           /*!< 0x00000001 */

+#define TAMP_OR_OUT3_RMP             TAMP_OR_OUT3_RMP_Msk

+

+/********************  Bits definition for TAMP_BKP0R register  ***************/

+#define TAMP_BKP0R_Pos               (0U)

+#define TAMP_BKP0R_Msk               (0xFFFFFFFFUL << TAMP_BKP0R_Pos)           /*!< 0xFFFFFFFF */

+#define TAMP_BKP0R                   TAMP_BKP0R_Msk

+

+/********************  Bits definition for TAMP_BKP1R register  ****************/

+#define TAMP_BKP1R_Pos               (0U)

+#define TAMP_BKP1R_Msk               (0xFFFFFFFFUL << TAMP_BKP1R_Pos)           /*!< 0xFFFFFFFF */

+#define TAMP_BKP1R                   TAMP_BKP1R_Msk

+

+/********************  Bits definition for TAMP_BKP2R register  ****************/

+#define TAMP_BKP2R_Pos               (0U)

+#define TAMP_BKP2R_Msk               (0xFFFFFFFFUL << TAMP_BKP2R_Pos)           /*!< 0xFFFFFFFF */

+#define TAMP_BKP2R                   TAMP_BKP2R_Msk

+

+/********************  Bits definition for TAMP_BKP3R register  ****************/

+#define TAMP_BKP3R_Pos               (0U)

+#define TAMP_BKP3R_Msk               (0xFFFFFFFFUL << TAMP_BKP3R_Pos)           /*!< 0xFFFFFFFF */

+#define TAMP_BKP3R                   TAMP_BKP3R_Msk

+

+/********************  Bits definition for TAMP_BKP4R register  ****************/

+#define TAMP_BKP4R_Pos               (0U)

+#define TAMP_BKP4R_Msk               (0xFFFFFFFFUL << TAMP_BKP4R_Pos)           /*!< 0xFFFFFFFF */

+#define TAMP_BKP4R                   TAMP_BKP4R_Msk

+

+/********************  Bits definition for TAMP_BKP5R register  ****************/

+#define TAMP_BKP5R_Pos               (0U)

+#define TAMP_BKP5R_Msk               (0xFFFFFFFFUL << TAMP_BKP5R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP5R                   TAMP_BKP5R_Msk

+

+/********************  Bits definition for TAMP_BKP6R register  ****************/

+#define TAMP_BKP6R_Pos               (0U)

+#define TAMP_BKP6R_Msk               (0xFFFFFFFFUL << TAMP_BKP6R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP6R                   TAMP_BKP6R_Msk

+

+/********************  Bits definition for TAMP_BKP7R register  ****************/

+#define TAMP_BKP7R_Pos               (0U)

+#define TAMP_BKP7R_Msk               (0xFFFFFFFFUL << TAMP_BKP7R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP7R                   TAMP_BKP7R_Msk

+

+/********************  Bits definition for TAMP_BKP8R register  ****************/

+#define TAMP_BKP8R_Pos               (0U)

+#define TAMP_BKP8R_Msk               (0xFFFFFFFFUL << TAMP_BKP8R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP8R                   TAMP_BKP8R_Msk

+

+/********************  Bits definition for TAMP_BKP9R register  ****************/

+#define TAMP_BKP9R_Pos               (0U)

+#define TAMP_BKP9R_Msk               (0xFFFFFFFFUL << TAMP_BKP9R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP9R                   TAMP_BKP9R_Msk

+

+/********************  Bits definition for TAMP_BKP10R register  ***************/

+#define TAMP_BKP10R_Pos              (0U)

+#define TAMP_BKP10R_Msk              (0xFFFFFFFFUL << TAMP_BKP10R_Pos)         /*!< 0xFFFFFFFF */

+#define TAMP_BKP10R                  TAMP_BKP10R_Msk

+

+/********************  Bits definition for TAMP_BKP11R register  ***************/

+#define TAMP_BKP11R_Pos              (0U)

+#define TAMP_BKP11R_Msk              (0xFFFFFFFFUL << TAMP_BKP11R_Pos)         /*!< 0xFFFFFFFF */

+#define TAMP_BKP11R                  TAMP_BKP11R_Msk

+

+/********************  Bits definition for TAMP_BKP12R register  ***************/

+#define TAMP_BKP12R_Pos              (0U)

+#define TAMP_BKP12R_Msk              (0xFFFFFFFFUL << TAMP_BKP12R_Pos)         /*!< 0xFFFFFFFF */

+#define TAMP_BKP12R                  TAMP_BKP12R_Msk

+

+/********************  Bits definition for TAMP_BKP13R register  ***************/

+#define TAMP_BKP13R_Pos              (0U)

+#define TAMP_BKP13R_Msk              (0xFFFFFFFFUL << TAMP_BKP13R_Pos)         /*!< 0xFFFFFFFF */

+#define TAMP_BKP13R                  TAMP_BKP13R_Msk

+

+/********************  Bits definition for TAMP_BKP14R register  ***************/

+#define TAMP_BKP14R_Pos              (0U)

+#define TAMP_BKP14R_Msk              (0xFFFFFFFFUL << TAMP_BKP14R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP14R                  TAMP_BKP14R_Msk

+

+/********************  Bits definition for TAMP_BKP15R register  ***************/

+#define TAMP_BKP15R_Pos              (0U)

+#define TAMP_BKP15R_Msk              (0xFFFFFFFFUL << TAMP_BKP15R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP15R                  TAMP_BKP15R_Msk

+

+/********************  Bits definition for TAMP_BKP16R register  ***************/

+#define TAMP_BKP16R_Pos              (0U)

+#define TAMP_BKP16R_Msk              (0xFFFFFFFFUL << TAMP_BKP16R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP16R                  TAMP_BKP16R_Msk

+

+/********************  Bits definition for TAMP_BKP17R register  ***************/

+#define TAMP_BKP17R_Pos              (0U)

+#define TAMP_BKP17R_Msk              (0xFFFFFFFFUL << TAMP_BKP17R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP17R                  TAMP_BKP17R_Msk

+

+/********************  Bits definition for TAMP_BKP18R register  ***************/

+#define TAMP_BKP18R_Pos              (0U)

+#define TAMP_BKP18R_Msk              (0xFFFFFFFFUL << TAMP_BKP18R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP18R                  TAMP_BKP18R_Msk

+

+/********************  Bits definition for TAMP_BKP19R register  ***************/

+#define TAMP_BKP19R_Pos              (0U)

+#define TAMP_BKP19R_Msk              (0xFFFFFFFFUL << TAMP_BKP19R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP19R                  TAMP_BKP19R_Msk

+

+/********************  Bits definition for TAMP_BKP20R register  ***************/

+#define TAMP_BKP20R_Pos              (0U)

+#define TAMP_BKP20R_Msk              (0xFFFFFFFFUL << TAMP_BKP20R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP20R                  TAMP_BKP20R_Msk

+

+/********************  Bits definition for TAMP_BKP21R register  ***************/

+#define TAMP_BKP21R_Pos              (0U)

+#define TAMP_BKP21R_Msk              (0xFFFFFFFFUL << TAMP_BKP21R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP21R                  TAMP_BKP21R_Msk

+

+/********************  Bits definition for TAMP_BKP22R register  ***************/

+#define TAMP_BKP22R_Pos              (0U)

+#define TAMP_BKP22R_Msk              (0xFFFFFFFFUL << TAMP_BKP22R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP22R                  TAMP_BKP22R_Msk

+

+/********************  Bits definition for TAMP_BKP23R register  ***************/

+#define TAMP_BKP23R_Pos              (0U)

+#define TAMP_BKP23R_Msk              (0xFFFFFFFFUL << TAMP_BKP23R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP23R                  TAMP_BKP23R_Msk

+

+/********************  Bits definition for TAMP_BKP24R register  ***************/

+#define TAMP_BKP24R_Pos              (0U)

+#define TAMP_BKP24R_Msk              (0xFFFFFFFFUL << TAMP_BKP24R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP24R                  TAMP_BKP24R_Msk

+

+/********************  Bits definition for TAMP_BKP25R register  ***************/

+#define TAMP_BKP25R_Pos              (0U)

+#define TAMP_BKP25R_Msk              (0xFFFFFFFFUL << TAMP_BKP25R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP25R                  TAMP_BKP25R_Msk

+

+/********************  Bits definition for TAMP_BKP26R register  ***************/

+#define TAMP_BKP26R_Pos              (0U)

+#define TAMP_BKP26R_Msk              (0xFFFFFFFFUL << TAMP_BKP26R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP26R                  TAMP_BKP26R_Msk

+

+/********************  Bits definition for TAMP_BKP27R register  ***************/

+#define TAMP_BKP27R_Pos              (0U)

+#define TAMP_BKP27R_Msk              (0xFFFFFFFFUL << TAMP_BKP27R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP27R                  TAMP_BKP27R_Msk

+

+/********************  Bits definition for TAMP_BKP28R register  ***************/

+#define TAMP_BKP28R_Pos              (0U)

+#define TAMP_BKP28R_Msk              (0xFFFFFFFFUL << TAMP_BKP28R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP28R                  TAMP_BKP28R_Msk

+

+/********************  Bits definition for TAMP_BKP29R register  ***************/

+#define TAMP_BKP29R_Pos              (0U)

+#define TAMP_BKP29R_Msk              (0xFFFFFFFFUL << TAMP_BKP29R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP29R                  TAMP_BKP29R_Msk

+

+/********************  Bits definition for TAMP_BKP30R register  ***************/

+#define TAMP_BKP30R_Pos              (0U)

+#define TAMP_BKP30R_Msk              (0xFFFFFFFFUL << TAMP_BKP30R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP30R                  TAMP_BKP30R_Msk

+

+/********************  Bits definition for TAMP_BKP31R register  ***************/

+#define TAMP_BKP31R_Pos              (0U)

+#define TAMP_BKP31R_Msk              (0xFFFFFFFFUL << TAMP_BKP31R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP31R                  TAMP_BKP31R_Msk

+

+/******************** Number of backup registers ******************************/

+#define TAMP_BKP_NUMBER_Pos             (5U)

+#define TAMP_BKP_NUMBER_Msk             (0x1UL << TAMP_BKP_NUMBER_Pos)         /*!< 0x00000080 */

+#define TAMP_BKP_NUMBER                 TAMP_BKP_NUMBER_Msk                    /*!< 32 BKPREG  */

+

+/******************************************************************************/

+/*                                                                            */

+/*                              SPDIF-RX Interface                            */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for SPDIF_CR register  ******************/

+#define SPDIFRX_CR_SPDIFEN_Pos      (0U)

+#define SPDIFRX_CR_SPDIFEN_Msk      (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)          /*!< 0x00000003 */

+#define SPDIFRX_CR_SPDIFEN          SPDIFRX_CR_SPDIFEN_Msk                     /*!<Peripheral Block Enable                      */

+#define SPDIFRX_CR_RXDMAEN_Pos      (2U)

+#define SPDIFRX_CR_RXDMAEN_Msk      (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)          /*!< 0x00000004 */

+#define SPDIFRX_CR_RXDMAEN          SPDIFRX_CR_RXDMAEN_Msk                     /*!<Receiver DMA Enable for data flow            */

+#define SPDIFRX_CR_RXSTEO_Pos       (3U)

+#define SPDIFRX_CR_RXSTEO_Msk       (0x1UL << SPDIFRX_CR_RXSTEO_Pos)           /*!< 0x00000008 */

+#define SPDIFRX_CR_RXSTEO           SPDIFRX_CR_RXSTEO_Msk                      /*!<Stereo Mode                                  */

+#define SPDIFRX_CR_DRFMT_Pos        (4U)

+#define SPDIFRX_CR_DRFMT_Msk        (0x3UL << SPDIFRX_CR_DRFMT_Pos)            /*!< 0x00000030 */

+#define SPDIFRX_CR_DRFMT            SPDIFRX_CR_DRFMT_Msk                       /*!<RX Data format                               */

+#define SPDIFRX_CR_PMSK_Pos         (6U)

+#define SPDIFRX_CR_PMSK_Msk         (0x1UL << SPDIFRX_CR_PMSK_Pos)             /*!< 0x00000040 */

+#define SPDIFRX_CR_PMSK             SPDIFRX_CR_PMSK_Msk                        /*!<Mask Parity error bit                        */

+#define SPDIFRX_CR_VMSK_Pos         (7U)

+#define SPDIFRX_CR_VMSK_Msk         (0x1UL << SPDIFRX_CR_VMSK_Pos)             /*!< 0x00000080 */

+#define SPDIFRX_CR_VMSK             SPDIFRX_CR_VMSK_Msk                        /*!<Mask of Validity bit                         */

+#define SPDIFRX_CR_CUMSK_Pos        (8U)

+#define SPDIFRX_CR_CUMSK_Msk        (0x1UL << SPDIFRX_CR_CUMSK_Pos)            /*!< 0x00000100 */

+#define SPDIFRX_CR_CUMSK            SPDIFRX_CR_CUMSK_Msk                       /*!<Mask of channel status and user bits         */

+#define SPDIFRX_CR_PTMSK_Pos        (9U)

+#define SPDIFRX_CR_PTMSK_Msk        (0x1UL << SPDIFRX_CR_PTMSK_Pos)            /*!< 0x00000200 */

+#define SPDIFRX_CR_PTMSK            SPDIFRX_CR_PTMSK_Msk                       /*!<Mask of Preamble Type bits                   */

+#define SPDIFRX_CR_CBDMAEN_Pos      (10U)

+#define SPDIFRX_CR_CBDMAEN_Msk      (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)          /*!< 0x00000400 */

+#define SPDIFRX_CR_CBDMAEN          SPDIFRX_CR_CBDMAEN_Msk                     /*!<Control Buffer DMA ENable for control flow   */

+#define SPDIFRX_CR_CHSEL_Pos        (11U)

+#define SPDIFRX_CR_CHSEL_Msk        (0x1UL << SPDIFRX_CR_CHSEL_Pos)            /*!< 0x00000800 */

+#define SPDIFRX_CR_CHSEL            SPDIFRX_CR_CHSEL_Msk                       /*!<Channel Selection                            */

+#define SPDIFRX_CR_NBTR_Pos         (12U)

+#define SPDIFRX_CR_NBTR_Msk         (0x3UL << SPDIFRX_CR_NBTR_Pos)             /*!< 0x00003000 */

+#define SPDIFRX_CR_NBTR             SPDIFRX_CR_NBTR_Msk                        /*!<Maximum allowed re-tries during synchronization phase */

+#define SPDIFRX_CR_WFA_Pos          (14U)

+#define SPDIFRX_CR_WFA_Msk          (0x1UL << SPDIFRX_CR_WFA_Pos)              /*!< 0x00004000 */

+#define SPDIFRX_CR_WFA              SPDIFRX_CR_WFA_Msk                         /*!<Wait For Activity     */

+#define SPDIFRX_CR_INSEL_Pos        (16U)

+#define SPDIFRX_CR_INSEL_Msk        (0x7UL << SPDIFRX_CR_INSEL_Pos)            /*!< 0x00070000 */

+#define SPDIFRX_CR_INSEL            SPDIFRX_CR_INSEL_Msk                       /*!<SPDIF input selection */

+#define SPDIFRX_CR_CKSEN_Pos        (20U)

+#define SPDIFRX_CR_CKSEN_Msk        (0x1UL << SPDIFRX_CR_CKSEN_Pos)            /*!< 0x00100000 */

+#define SPDIFRX_CR_CKSEN            SPDIFRX_CR_CKSEN_Msk                       /*!<Symbol Clock Enable */

+#define SPDIFRX_CR_CKSBKPEN_Pos     (21U)

+#define SPDIFRX_CR_CKSBKPEN_Msk     (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)         /*!< 0x00200000 */

+#define SPDIFRX_CR_CKSBKPEN         SPDIFRX_CR_CKSBKPEN_Msk                    /*!<Backup Symbol Clock Enable */

+

+/*******************  Bit definition for SPDIFRX_IMR register  *******************/

+#define SPDIFRX_IMR_RXNEIE_Pos      (0U)

+#define SPDIFRX_IMR_RXNEIE_Msk      (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)          /*!< 0x00000001 */

+#define SPDIFRX_IMR_RXNEIE          SPDIFRX_IMR_RXNEIE_Msk                     /*!<RXNE interrupt enable                              */

+#define SPDIFRX_IMR_CSRNEIE_Pos     (1U)

+#define SPDIFRX_IMR_CSRNEIE_Msk     (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)         /*!< 0x00000002 */

+#define SPDIFRX_IMR_CSRNEIE         SPDIFRX_IMR_CSRNEIE_Msk                    /*!<Control Buffer Ready Interrupt Enable              */

+#define SPDIFRX_IMR_PERRIE_Pos      (2U)

+#define SPDIFRX_IMR_PERRIE_Msk      (0x1UL << SPDIFRX_IMR_PERRIE_Pos)          /*!< 0x00000004 */

+#define SPDIFRX_IMR_PERRIE          SPDIFRX_IMR_PERRIE_Msk                     /*!<Parity error interrupt enable                      */

+#define SPDIFRX_IMR_OVRIE_Pos       (3U)

+#define SPDIFRX_IMR_OVRIE_Msk       (0x1UL << SPDIFRX_IMR_OVRIE_Pos)           /*!< 0x00000008 */

+#define SPDIFRX_IMR_OVRIE           SPDIFRX_IMR_OVRIE_Msk                      /*!<Overrun error Interrupt Enable                     */

+#define SPDIFRX_IMR_SBLKIE_Pos      (4U)

+#define SPDIFRX_IMR_SBLKIE_Msk      (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)          /*!< 0x00000010 */

+#define SPDIFRX_IMR_SBLKIE          SPDIFRX_IMR_SBLKIE_Msk                     /*!<Synchronization Block Detected Interrupt Enable    */

+#define SPDIFRX_IMR_SYNCDIE_Pos     (5U)

+#define SPDIFRX_IMR_SYNCDIE_Msk     (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)         /*!< 0x00000020 */

+#define SPDIFRX_IMR_SYNCDIE         SPDIFRX_IMR_SYNCDIE_Msk                    /*!<Synchronization Done                               */

+#define SPDIFRX_IMR_IFEIE_Pos       (6U)

+#define SPDIFRX_IMR_IFEIE_Msk       (0x1UL << SPDIFRX_IMR_IFEIE_Pos)           /*!< 0x00000040 */

+#define SPDIFRX_IMR_IFEIE           SPDIFRX_IMR_IFEIE_Msk                      /*!<Serial Interface Error Interrupt Enable            */

+

+/*******************  Bit definition for SPDIFRX_SR register  *******************/

+#define SPDIFRX_SR_RXNE_Pos         (0U)

+#define SPDIFRX_SR_RXNE_Msk         (0x1UL << SPDIFRX_SR_RXNE_Pos)             /*!< 0x00000001 */

+#define SPDIFRX_SR_RXNE             SPDIFRX_SR_RXNE_Msk                        /*!<Read data register not empty                          */

+#define SPDIFRX_SR_CSRNE_Pos        (1U)

+#define SPDIFRX_SR_CSRNE_Msk        (0x1UL << SPDIFRX_SR_CSRNE_Pos)            /*!< 0x00000002 */

+#define SPDIFRX_SR_CSRNE            SPDIFRX_SR_CSRNE_Msk                       /*!<The Control Buffer register is not empty              */

+#define SPDIFRX_SR_PERR_Pos         (2U)

+#define SPDIFRX_SR_PERR_Msk         (0x1UL << SPDIFRX_SR_PERR_Pos)             /*!< 0x00000004 */

+#define SPDIFRX_SR_PERR             SPDIFRX_SR_PERR_Msk                        /*!<Parity error                                          */

+#define SPDIFRX_SR_OVR_Pos          (3U)

+#define SPDIFRX_SR_OVR_Msk          (0x1UL << SPDIFRX_SR_OVR_Pos)              /*!< 0x00000008 */

+#define SPDIFRX_SR_OVR              SPDIFRX_SR_OVR_Msk                         /*!<Overrun error                                         */

+#define SPDIFRX_SR_SBD_Pos          (4U)

+#define SPDIFRX_SR_SBD_Msk          (0x1UL << SPDIFRX_SR_SBD_Pos)              /*!< 0x00000010 */

+#define SPDIFRX_SR_SBD              SPDIFRX_SR_SBD_Msk                         /*!<Synchronization Block Detected                        */

+#define SPDIFRX_SR_SYNCD_Pos        (5U)

+#define SPDIFRX_SR_SYNCD_Msk        (0x1UL << SPDIFRX_SR_SYNCD_Pos)            /*!< 0x00000020 */

+#define SPDIFRX_SR_SYNCD            SPDIFRX_SR_SYNCD_Msk                       /*!<Synchronization Done                                  */

+#define SPDIFRX_SR_FERR_Pos         (6U)

+#define SPDIFRX_SR_FERR_Msk         (0x1UL << SPDIFRX_SR_FERR_Pos)             /*!< 0x00000040 */

+#define SPDIFRX_SR_FERR             SPDIFRX_SR_FERR_Msk                        /*!<Framing error                                         */

+#define SPDIFRX_SR_SERR_Pos         (7U)

+#define SPDIFRX_SR_SERR_Msk         (0x1UL << SPDIFRX_SR_SERR_Pos)             /*!< 0x00000080 */

+#define SPDIFRX_SR_SERR             SPDIFRX_SR_SERR_Msk                        /*!<Synchronization error                                 */

+#define SPDIFRX_SR_TERR_Pos         (8U)

+#define SPDIFRX_SR_TERR_Msk         (0x1UL << SPDIFRX_SR_TERR_Pos)             /*!< 0x00000100 */

+#define SPDIFRX_SR_TERR             SPDIFRX_SR_TERR_Msk                        /*!<Time-out error                                        */

+#define SPDIFRX_SR_WIDTH5_Pos       (16U)

+#define SPDIFRX_SR_WIDTH5_Msk       (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)        /*!< 0x7FFF0000 */

+#define SPDIFRX_SR_WIDTH5           SPDIFRX_SR_WIDTH5_Msk                      /*!<Duration of 5 symbols counted with spdif_clk          */

+

+/*******************  Bit definition for SPDIFRX_IFCR register  *******************/

+#define SPDIFRX_IFCR_PERRCF_Pos     (2U)

+#define SPDIFRX_IFCR_PERRCF_Msk     (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)         /*!< 0x00000004 */

+#define SPDIFRX_IFCR_PERRCF         SPDIFRX_IFCR_PERRCF_Msk                    /*!<Clears the Parity error flag                         */

+#define SPDIFRX_IFCR_OVRCF_Pos      (3U)

+#define SPDIFRX_IFCR_OVRCF_Msk      (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)          /*!< 0x00000008 */

+#define SPDIFRX_IFCR_OVRCF          SPDIFRX_IFCR_OVRCF_Msk                     /*!<Clears the Overrun error flag                        */

+#define SPDIFRX_IFCR_SBDCF_Pos      (4U)

+#define SPDIFRX_IFCR_SBDCF_Msk      (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)          /*!< 0x00000010 */

+#define SPDIFRX_IFCR_SBDCF          SPDIFRX_IFCR_SBDCF_Msk                     /*!<Clears the Synchronization Block Detected flag       */

+#define SPDIFRX_IFCR_SYNCDCF_Pos    (5U)

+#define SPDIFRX_IFCR_SYNCDCF_Msk    (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)        /*!< 0x00000020 */

+#define SPDIFRX_IFCR_SYNCDCF        SPDIFRX_IFCR_SYNCDCF_Msk                   /*!<Clears the Synchronization Done flag                 */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/

+#define SPDIFRX_DR0_DR_Pos          (0U)

+#define SPDIFRX_DR0_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)         /*!< 0x00FFFFFF */

+#define SPDIFRX_DR0_DR              SPDIFRX_DR0_DR_Msk                         /*!<Data value            */

+#define SPDIFRX_DR0_PE_Pos          (24U)

+#define SPDIFRX_DR0_PE_Msk          (0x1UL << SPDIFRX_DR0_PE_Pos)              /*!< 0x01000000 */

+#define SPDIFRX_DR0_PE              SPDIFRX_DR0_PE_Msk                         /*!<Parity Error bit      */

+#define SPDIFRX_DR0_V_Pos           (25U)

+#define SPDIFRX_DR0_V_Msk           (0x1UL << SPDIFRX_DR0_V_Pos)               /*!< 0x02000000 */

+#define SPDIFRX_DR0_V               SPDIFRX_DR0_V_Msk                          /*!<Validity bit          */

+#define SPDIFRX_DR0_U_Pos           (26U)

+#define SPDIFRX_DR0_U_Msk           (0x1UL << SPDIFRX_DR0_U_Pos)               /*!< 0x04000000 */

+#define SPDIFRX_DR0_U               SPDIFRX_DR0_U_Msk                          /*!<User bit              */

+#define SPDIFRX_DR0_C_Pos           (27U)

+#define SPDIFRX_DR0_C_Msk           (0x1UL << SPDIFRX_DR0_C_Pos)               /*!< 0x08000000 */

+#define SPDIFRX_DR0_C               SPDIFRX_DR0_C_Msk                          /*!<Channel Status bit    */

+#define SPDIFRX_DR0_PT_Pos          (28U)

+#define SPDIFRX_DR0_PT_Msk          (0x3UL << SPDIFRX_DR0_PT_Pos)              /*!< 0x30000000 */

+#define SPDIFRX_DR0_PT              SPDIFRX_DR0_PT_Msk                         /*!<Preamble Type         */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/

+#define SPDIFRX_DR1_DR_Pos          (8U)

+#define SPDIFRX_DR1_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)         /*!< 0xFFFFFF00 */

+#define SPDIFRX_DR1_DR              SPDIFRX_DR1_DR_Msk                         /*!<Data value            */

+#define SPDIFRX_DR1_PT_Pos          (4U)

+#define SPDIFRX_DR1_PT_Msk          (0x3UL << SPDIFRX_DR1_PT_Pos)              /*!< 0x00000030 */

+#define SPDIFRX_DR1_PT              SPDIFRX_DR1_PT_Msk                         /*!<Preamble Type         */

+#define SPDIFRX_DR1_C_Pos           (3U)

+#define SPDIFRX_DR1_C_Msk           (0x1UL << SPDIFRX_DR1_C_Pos)               /*!< 0x00000008 */

+#define SPDIFRX_DR1_C               SPDIFRX_DR1_C_Msk                          /*!<Channel Status bit    */

+#define SPDIFRX_DR1_U_Pos           (2U)

+#define SPDIFRX_DR1_U_Msk           (0x1UL << SPDIFRX_DR1_U_Pos)               /*!< 0x00000004 */

+#define SPDIFRX_DR1_U               SPDIFRX_DR1_U_Msk                          /*!<User bit              */

+#define SPDIFRX_DR1_V_Pos           (1U)

+#define SPDIFRX_DR1_V_Msk           (0x1UL << SPDIFRX_DR1_V_Pos)               /*!< 0x00000002 */

+#define SPDIFRX_DR1_V               SPDIFRX_DR1_V_Msk                          /*!<Validity bit          */

+#define SPDIFRX_DR1_PE_Pos          (0U)

+#define SPDIFRX_DR1_PE_Msk          (0x1UL << SPDIFRX_DR1_PE_Pos)              /*!< 0x00000001 */

+#define SPDIFRX_DR1_PE              SPDIFRX_DR1_PE_Msk                         /*!<Parity Error bit      */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/

+#define SPDIFRX_DR1_DRNL1_Pos       (16U)

+#define SPDIFRX_DR1_DRNL1_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)        /*!< 0xFFFF0000 */

+#define SPDIFRX_DR1_DRNL1           SPDIFRX_DR1_DRNL1_Msk                      /*!<Data value Channel B      */

+#define SPDIFRX_DR1_DRNL2_Pos       (0U)

+#define SPDIFRX_DR1_DRNL2_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)        /*!< 0x0000FFFF */

+#define SPDIFRX_DR1_DRNL2           SPDIFRX_DR1_DRNL2_Msk                      /*!<Data value Channel A      */

+

+/*******************  Bit definition for SPDIFRX_CSR register   *******************/

+#define SPDIFRX_CSR_USR_Pos         (0U)

+#define SPDIFRX_CSR_USR_Msk         (0xFFFFUL << SPDIFRX_CSR_USR_Pos)          /*!< 0x0000FFFF */

+#define SPDIFRX_CSR_USR             SPDIFRX_CSR_USR_Msk                        /*!<User data information           */

+#define SPDIFRX_CSR_CS_Pos          (16U)

+#define SPDIFRX_CSR_CS_Msk          (0xFFUL << SPDIFRX_CSR_CS_Pos)             /*!< 0x00FF0000 */

+#define SPDIFRX_CSR_CS              SPDIFRX_CSR_CS_Msk                         /*!<Channel A status information    */

+#define SPDIFRX_CSR_SOB_Pos         (24U)

+#define SPDIFRX_CSR_SOB_Msk         (0x1UL << SPDIFRX_CSR_SOB_Pos)             /*!< 0x01000000 */

+#define SPDIFRX_CSR_SOB             SPDIFRX_CSR_SOB_Msk                        /*!<Start Of Block                  */

+

+/*******************  Bit definition for SPDIFRX_DIR register    *******************/

+#define SPDIFRX_DIR_THI_Pos         (0U)

+#define SPDIFRX_DIR_THI_Msk         (0x1FFFUL << SPDIFRX_DIR_THI_Pos)          /*!< 0x00001FFF */

+#define SPDIFRX_DIR_THI             SPDIFRX_DIR_THI_Msk                        /*!<Threshold LOW      */

+#define SPDIFRX_DIR_TLO_Pos         (16U)

+#define SPDIFRX_DIR_TLO_Msk         (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)          /*!< 0x1FFF0000 */

+#define SPDIFRX_DIR_TLO             SPDIFRX_DIR_TLO_Msk                        /*!<Threshold HIGH     */

+

+/*******************  Bit definition for SPDIFRX_VERR register    *******************/

+#define SPDIFRX_VERR_MINREV_Pos     (0U)

+#define SPDIFRX_VERR_MINREV_Msk     (0xFUL << SPDIFRX_VERR_MINREV_Pos)         /*!< 0x0000000F */

+#define SPDIFRX_VERR_MINREV         SPDIFRX_VERR_MINREV_Msk                    /*!<SPDIFRX Minor revision     */

+#define SPDIFRX_VERR_MAJREV_Pos     (4U)

+#define SPDIFRX_VERR_MAJREV_Msk     (0xFUL << SPDIFRX_VERR_MAJREV_Pos)         /*!< 0x000000F0 */

+#define SPDIFRX_VERR_MAJREV         SPDIFRX_VERR_MAJREV_Msk                    /*!<SPDIFRX Major revision     */

+

+/*******************  Bit definition for SPDIFRX_IDR register    *******************/

+#define SPDIFRX_IDR_ID_Pos          (0U)

+#define SPDIFRX_IDR_ID_Msk          (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos)       /*!< 0xFFFFFFFF */

+#define SPDIFRX_IDR_ID              SPDIFRX_IDR_ID_Msk                         /*!<SPDIFRX identifier     */

+

+/*******************  Bit definition for SPDIFRX_SIDR register    *******************/

+#define SPDIFRX_SIDR_SID_Pos        (0U)

+#define SPDIFRX_SIDR_SID_Msk        (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos)     /*!< 0xFFFFFFFF */

+#define SPDIFRX_SIDR_SID            SPDIFRX_SIDR_SID_Msk                       /*!<Size of the memory region allocated to SPDIFRX registers */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          Serial Audio Interface                            */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  SAI VERSION  ********************************/

+#define SAI_VER_V2_1

+

+/********************  Bit definition for SAI_GCR register  *******************/

+#define SAI_GCR_SYNCIN_Pos         (0U)

+#define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000003 */

+#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */

+#define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */

+#define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */

+

+#define SAI_GCR_SYNCOUT_Pos        (4U)

+#define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000030 */

+#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */

+#define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */

+#define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */

+

+/*******************  Bit definition for SAI_xCR1 register  *******************/

+#define SAI_xCR1_MODE_Pos          (0U)

+#define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */

+#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */

+#define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */

+#define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */

+

+#define SAI_xCR1_PRTCFG_Pos        (2U)

+#define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */

+#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */

+#define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */

+#define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */

+

+#define SAI_xCR1_DS_Pos            (5U)

+#define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */

+#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */

+#define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */

+#define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */

+#define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */

+

+#define SAI_xCR1_LSBFIRST_Pos      (8U)

+#define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */

+#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */

+#define SAI_xCR1_CKSTR_Pos         (9U)

+#define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */

+#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */

+

+#define SAI_xCR1_SYNCEN_Pos        (10U)

+#define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */

+#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */

+#define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */

+#define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */

+

+#define SAI_xCR1_MONO_Pos          (12U)

+#define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */

+#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */

+#define SAI_xCR1_OUTDRIV_Pos       (13U)

+#define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */

+#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */

+#define SAI_xCR1_SAIEN_Pos         (16U)

+#define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */

+#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */

+#define SAI_xCR1_DMAEN_Pos         (17U)

+#define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */

+#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */

+#define SAI_xCR1_NODIV_Pos         (19U)

+#define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */

+#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */

+

+#define SAI_xCR1_MCKDIV_Pos        (20U)

+#define SAI_xCR1_MCKDIV_Msk        (0x3FUL << SAI_xCR1_MCKDIV_Pos)             /*!< 0x03F00000 */

+#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[5:0] (Master ClocK Divider)  */

+#define SAI_xCR1_MCKDIV_0          (0x01UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00100000 */

+#define SAI_xCR1_MCKDIV_1          (0x02UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00200000 */

+#define SAI_xCR1_MCKDIV_2          (0x04UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00400000 */

+#define SAI_xCR1_MCKDIV_3          (0x08UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00800000 */

+#define SAI_xCR1_MCKDIV_4          (0x10UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x01000000 */

+#define SAI_xCR1_MCKDIV_5          (0x20UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x02000000 */

+

+#define SAI_xCR1_MCKEN_Pos         (27U)

+#define SAI_xCR1_MCKEN_Msk         (0x1UL << SAI_xCR1_MCKEN_Pos)               /*!< 0x08000000 */

+#define SAI_xCR1_MCKEN             SAI_xCR1_MCKEN_Msk                          /*!<Master ClocK enable */

+

+#define SAI_xCR1_OSR_Pos           (26U)

+#define SAI_xCR1_OSR_Msk           (0x1UL << SAI_xCR1_OSR_Pos)                 /*!< 0x04000000 */

+#define SAI_xCR1_OSR               SAI_xCR1_OSR_Msk                            /*!<OverSampling Ratio for master clock  */

+

+/* Legacy define */

+#define  SAI_xCR1_NOMCK               SAI_xCR1_NODIV

+

+/*******************  Bit definition for SAI_xCR2 register  *******************/

+#define SAI_xCR2_FTH_Pos           (0U)

+#define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */

+#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */

+#define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */

+#define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */

+#define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */

+

+#define SAI_xCR2_FFLUSH_Pos        (3U)

+#define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */

+#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */

+#define SAI_xCR2_TRIS_Pos          (4U)

+#define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */

+#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */

+#define SAI_xCR2_MUTE_Pos          (5U)

+#define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */

+#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */

+#define SAI_xCR2_MUTEVAL_Pos       (6U)

+#define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */

+#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */

+

+#define SAI_xCR2_MUTECNT_Pos       (7U)

+#define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */

+#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */

+#define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */

+#define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */

+#define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */

+#define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */

+#define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */

+#define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */

+

+#define SAI_xCR2_CPL_Pos           (13U)

+#define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */

+#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */

+

+#define SAI_xCR2_COMP_Pos          (14U)

+#define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */

+#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */

+#define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */

+#define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */

+

+/******************  Bit definition for SAI_xFRCR register  *******************/

+#define SAI_xFRCR_FRL_Pos          (0U)

+#define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */

+#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](FRame Length)  */

+#define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */

+#define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */

+#define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */

+#define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */

+#define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */

+#define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */

+#define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */

+#define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */

+

+#define SAI_xFRCR_FSALL_Pos        (8U)

+#define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */

+#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FSALL[6:0] (Frame Synchronization Active Level Length)  */

+#define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */

+#define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */

+#define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */

+#define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */

+#define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */

+#define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */

+#define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */

+

+#define SAI_xFRCR_FSDEF_Pos        (16U)

+#define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */

+#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!<Frame Synchronization Definition  */

+#define SAI_xFRCR_FSPOL_Pos        (17U)

+#define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */

+#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */

+#define SAI_xFRCR_FSOFF_Pos        (18U)

+#define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */

+#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */

+

+/* Legacy define */

+#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL

+

+/******************  Bit definition for SAI_xSLOTR register  *******************/

+#define SAI_xSLOTR_FBOFF_Pos       (0U)

+#define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */

+#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FBOFF[4:0](First Bit Offset)  */

+#define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */

+#define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */

+#define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */

+#define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */

+#define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */

+

+#define SAI_xSLOTR_SLOTSZ_Pos      (6U)

+#define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */

+#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */

+#define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */

+#define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */

+

+#define SAI_xSLOTR_NBSLOT_Pos      (8U)

+#define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */

+#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */

+#define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */

+#define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */

+#define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */

+#define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */

+

+#define SAI_xSLOTR_SLOTEN_Pos      (16U)

+#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */

+#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */

+

+/*******************  Bit definition for SAI_xIMR register  *******************/

+#define SAI_xIMR_OVRUDRIE_Pos      (0U)

+#define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */

+#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */

+#define SAI_xIMR_MUTEDETIE_Pos     (1U)

+#define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */

+#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */

+#define SAI_xIMR_WCKCFGIE_Pos      (2U)

+#define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */

+#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */

+#define SAI_xIMR_FREQIE_Pos        (3U)

+#define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */

+#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */

+#define SAI_xIMR_CNRDYIE_Pos       (4U)

+#define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */

+#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */

+#define SAI_xIMR_AFSDETIE_Pos      (5U)

+#define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */

+#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */

+#define SAI_xIMR_LFSDETIE_Pos      (6U)

+#define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */

+#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */

+

+/********************  Bit definition for SAI_xSR register  *******************/

+#define SAI_xSR_OVRUDR_Pos         (0U)

+#define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */

+#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */

+#define SAI_xSR_MUTEDET_Pos        (1U)

+#define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */

+#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */

+#define SAI_xSR_WCKCFG_Pos         (2U)

+#define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */

+#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */

+#define SAI_xSR_FREQ_Pos           (3U)

+#define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */

+#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */

+#define SAI_xSR_CNRDY_Pos          (4U)

+#define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */

+#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */

+#define SAI_xSR_AFSDET_Pos         (5U)

+#define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */

+#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */

+#define SAI_xSR_LFSDET_Pos         (6U)

+#define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */

+#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */

+

+#define SAI_xSR_FLVL_Pos           (16U)

+#define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */

+#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */

+#define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */

+#define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */

+#define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */

+

+/******************  Bit definition for SAI_xCLRFR register  ******************/

+#define SAI_xCLRFR_COVRUDR_Pos     (0U)

+#define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */

+#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */

+#define SAI_xCLRFR_CMUTEDET_Pos    (1U)

+#define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */

+#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */

+#define SAI_xCLRFR_CWCKCFG_Pos     (2U)

+#define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */

+#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */

+#define SAI_xCLRFR_CFREQ_Pos       (3U)

+#define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */

+#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */

+#define SAI_xCLRFR_CCNRDY_Pos      (4U)

+#define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */

+#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */

+#define SAI_xCLRFR_CAFSDET_Pos     (5U)

+#define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */

+#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */

+#define SAI_xCLRFR_CLFSDET_Pos     (6U)

+#define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */

+#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */

+

+/******************  Bit definition for SAI_xDR register  *********************/

+#define SAI_xDR_DATA_Pos           (0U)

+#define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */

+#define SAI_xDR_DATA               SAI_xDR_DATA_Msk

+

+/*******************  Bit definition for SAI_PDMCR register  ******************/

+#define SAI_PDMCR_PDMEN_Pos        (0U)

+#define SAI_PDMCR_PDMEN_Msk        (0x1UL << SAI_PDMCR_PDMEN_Pos)              /*!< 0x00000001 */

+#define SAI_PDMCR_PDMEN            SAI_PDMCR_PDMEN_Msk                         /*!<PDM Enable                                          */

+

+#define SAI_PDMCR_MICNBR_Pos       (4U)

+#define SAI_PDMCR_MICNBR_Msk       (0x3UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000030 */

+#define SAI_PDMCR_MICNBR           SAI_PDMCR_MICNBR_Msk                        /*!<Number of microphones                               */

+#define SAI_PDMCR_MICNBR_0         (0x1UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000010 */

+#define SAI_PDMCR_MICNBR_1         (0x2UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000020 */

+

+#define SAI_PDMCR_CKEN1_Pos        (8U)

+#define SAI_PDMCR_CKEN1_Msk        (0x1UL << SAI_PDMCR_CKEN1_Pos)              /*!< 0x00000100 */

+#define SAI_PDMCR_CKEN1            SAI_PDMCR_CKEN1_Msk                         /*!<Clock enable of bitstream clock number 1            */

+#define SAI_PDMCR_CKEN2_Pos        (9U)

+#define SAI_PDMCR_CKEN2_Msk        (0x1UL << SAI_PDMCR_CKEN2_Pos)              /*!< 0x00000200 */

+#define SAI_PDMCR_CKEN2            SAI_PDMCR_CKEN2_Msk                         /*!<Clock enable of bitstream clock number 2            */

+#define SAI_PDMCR_CKEN3_Pos        (10U)

+#define SAI_PDMCR_CKEN3_Msk        (0x1UL << SAI_PDMCR_CKEN3_Pos)              /*!< 0x00000400 */

+#define SAI_PDMCR_CKEN3            SAI_PDMCR_CKEN3_Msk                         /*!<Clock enable of bitstream clock number 3            */

+#define SAI_PDMCR_CKEN4_Pos        (11U)

+#define SAI_PDMCR_CKEN4_Msk        (0x1UL << SAI_PDMCR_CKEN4_Pos)              /*!< 0x00000800 */

+#define SAI_PDMCR_CKEN4            SAI_PDMCR_CKEN4_Msk                         /*!<Clock enable of bitstream clock number 4            */

+

+/******************  Bit definition for SAI_PDMDLY register  ******************/

+#define SAI_PDMDLY_DLYM1L_Pos      (0U)

+#define SAI_PDMDLY_DLYM1L_Msk      (0x7UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000007 */

+#define SAI_PDMDLY_DLYM1L          SAI_PDMDLY_DLYM1L_Msk                       /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */

+#define SAI_PDMDLY_DLYM1L_0        (0x1UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000001 */

+#define SAI_PDMDLY_DLYM1L_1        (0x2UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000002 */

+#define SAI_PDMDLY_DLYM1L_2        (0x4UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000004 */

+

+#define SAI_PDMDLY_DLYM1R_Pos      (4U)

+#define SAI_PDMDLY_DLYM1R_Msk      (0x7UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000070 */

+#define SAI_PDMDLY_DLYM1R          SAI_PDMDLY_DLYM1R_Msk                       /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */

+#define SAI_PDMDLY_DLYM1R_0        (0x1UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000010 */

+#define SAI_PDMDLY_DLYM1R_1        (0x2UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000020 */

+#define SAI_PDMDLY_DLYM1R_2        (0x4UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000040 */

+

+#define SAI_PDMDLY_DLYM2L_Pos      (8U)

+#define SAI_PDMDLY_DLYM2L_Msk      (0x7UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000700 */

+#define SAI_PDMDLY_DLYM2L          SAI_PDMDLY_DLYM2L_Msk                       /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */

+#define SAI_PDMDLY_DLYM2L_0        (0x1UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000100 */

+#define SAI_PDMDLY_DLYM2L_1        (0x2UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000200 */

+#define SAI_PDMDLY_DLYM2L_2        (0x4UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000400 */

+

+#define SAI_PDMDLY_DLYM2R_Pos      (12U)

+#define SAI_PDMDLY_DLYM2R_Msk      (0x7UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00007000 */

+#define SAI_PDMDLY_DLYM2R          SAI_PDMDLY_DLYM2R_Msk                       /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/

+#define SAI_PDMDLY_DLYM2R_0        (0x1UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00001000 */

+#define SAI_PDMDLY_DLYM2R_1        (0x2UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00002000 */

+#define SAI_PDMDLY_DLYM2R_2        (0x4UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00004000 */

+

+#define SAI_PDMDLY_DLYM3L_Pos      (16U)

+#define SAI_PDMDLY_DLYM3L_Msk      (0x7UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00070000 */

+#define SAI_PDMDLY_DLYM3L          SAI_PDMDLY_DLYM3L_Msk                       /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/

+#define SAI_PDMDLY_DLYM3L_0        (0x1UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00010000 */

+#define SAI_PDMDLY_DLYM3L_1        (0x2UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00020000 */

+#define SAI_PDMDLY_DLYM3L_2        (0x4UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00040000 */

+

+#define SAI_PDMDLY_DLYM3R_Pos      (20U)

+#define SAI_PDMDLY_DLYM3R_Msk      (0x7UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00700000 */

+#define SAI_PDMDLY_DLYM3R          SAI_PDMDLY_DLYM3R_Msk                       /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/

+#define SAI_PDMDLY_DLYM3R_0        (0x1UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00100000 */

+#define SAI_PDMDLY_DLYM3R_1        (0x2UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00200000 */

+#define SAI_PDMDLY_DLYM3R_2        (0x4UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00400000 */

+

+#define SAI_PDMDLY_DLYM4L_Pos      (24U)

+#define SAI_PDMDLY_DLYM4L_Msk      (0x7UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x07000000 */

+#define SAI_PDMDLY_DLYM4L          SAI_PDMDLY_DLYM4L_Msk                       /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/

+#define SAI_PDMDLY_DLYM4L_0        (0x1UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x01000000 */

+#define SAI_PDMDLY_DLYM4L_1        (0x2UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x02000000 */

+#define SAI_PDMDLY_DLYM4L_2        (0x4UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x04000000 */

+

+#define SAI_PDMDLY_DLYM4R_Pos      (28U)

+#define SAI_PDMDLY_DLYM4R_Msk      (0x7UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x70000000 */

+#define SAI_PDMDLY_DLYM4R          SAI_PDMDLY_DLYM4R_Msk                       /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/

+#define SAI_PDMDLY_DLYM4R_0        (0x1UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x10000000 */

+#define SAI_PDMDLY_DLYM4R_1        (0x2UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x20000000 */

+#define SAI_PDMDLY_DLYM4R_2        (0x4UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x40000000 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           SDMMC Interface                                  */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for SDMMC_POWER register  ******************/

+#define SDMMC_POWER_PWRCTRL_Pos          (0U)

+#define SDMMC_POWER_PWRCTRL_Msk          (0x3UL << SDMMC_POWER_PWRCTRL_Pos)    /*!< 0x00000003 */

+#define SDMMC_POWER_PWRCTRL              SDMMC_POWER_PWRCTRL_Msk               /*!<PWRCTRL[1:0] bits (Power supply control bits) */

+#define SDMMC_POWER_PWRCTRL_0            (0x1UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000001 */

+#define SDMMC_POWER_PWRCTRL_1            (0x2UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000002 */

+#define SDMMC_POWER_VSWITCH_Pos          (2U)

+#define SDMMC_POWER_VSWITCH_Msk          (0x1UL << SDMMC_POWER_VSWITCH_Pos)    /*!< 0x00000004 */

+#define SDMMC_POWER_VSWITCH              SDMMC_POWER_VSWITCH_Msk               /*!<Voltage switch sequence start */

+#define SDMMC_POWER_VSWITCHEN_Pos        (3U)

+#define SDMMC_POWER_VSWITCHEN_Msk        (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)  /*!< 0x00000008 */

+#define SDMMC_POWER_VSWITCHEN            SDMMC_POWER_VSWITCHEN_Msk             /*!<Voltage switch procedure enable */

+#define SDMMC_POWER_DIRPOL_Pos           (4U)

+#define SDMMC_POWER_DIRPOL_Msk           (0x1UL << SDMMC_POWER_DIRPOL_Pos)     /*!< 0x00000010 */

+#define SDMMC_POWER_DIRPOL               SDMMC_POWER_DIRPOL_Msk                /*!<Data and Command direction signals polarity selection */

+

+/******************  Bit definition for SDMMC_CLKCR register  ******************/

+#define SDMMC_CLKCR_CLKDIV_Pos           (0U)

+#define SDMMC_CLKCR_CLKDIV_Msk           (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)   /*!< 0x000003FF */

+#define SDMMC_CLKCR_CLKDIV               SDMMC_CLKCR_CLKDIV_Msk                /*!<Clock divide factor             */

+#define SDMMC_CLKCR_PWRSAV_Pos           (12U)

+#define SDMMC_CLKCR_PWRSAV_Msk           (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)     /*!< 0x00001000 */

+#define SDMMC_CLKCR_PWRSAV               SDMMC_CLKCR_PWRSAV_Msk                /*!<Power saving configuration bit  */

+

+#define SDMMC_CLKCR_WIDBUS_Pos           (14U)

+#define SDMMC_CLKCR_WIDBUS_Msk           (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)     /*!< 0x0000C000 */

+#define SDMMC_CLKCR_WIDBUS               SDMMC_CLKCR_WIDBUS_Msk                /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */

+#define SDMMC_CLKCR_WIDBUS_0             (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00004000 */

+#define SDMMC_CLKCR_WIDBUS_1             (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00008000 */

+

+#define SDMMC_CLKCR_NEGEDGE_Pos          (16U)

+#define SDMMC_CLKCR_NEGEDGE_Msk          (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)    /*!< 0x00010000 */

+#define SDMMC_CLKCR_NEGEDGE              SDMMC_CLKCR_NEGEDGE_Msk               /*!<SDMMC_CK dephasing selection bit */

+#define SDMMC_CLKCR_HWFC_EN_Pos          (17U)

+#define SDMMC_CLKCR_HWFC_EN_Msk          (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)    /*!< 0x00020000 */

+#define SDMMC_CLKCR_HWFC_EN              SDMMC_CLKCR_HWFC_EN_Msk               /*!<HW Flow Control enable           */

+#define SDMMC_CLKCR_DDR_Pos              (18U)

+#define SDMMC_CLKCR_DDR_Msk              (0x1UL << SDMMC_CLKCR_DDR_Pos)        /*!< 0x00040000 */

+#define SDMMC_CLKCR_DDR                  SDMMC_CLKCR_DDR_Msk                   /*!<Data rate signaling selection    */

+#define SDMMC_CLKCR_BUSSPEED_Pos         (19U)

+#define SDMMC_CLKCR_BUSSPEED_Msk         (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)   /*!< 0x00080000 */

+#define SDMMC_CLKCR_BUSSPEED             SDMMC_CLKCR_BUSSPEED_Msk              /*!<Bus speed mode selection         */

+#define SDMMC_CLKCR_SELCLKRX_Pos         (20U)

+#define SDMMC_CLKCR_SELCLKRX_Msk         (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)   /*!< 0x00300000 */

+#define SDMMC_CLKCR_SELCLKRX             SDMMC_CLKCR_SELCLKRX_Msk              /*!<SELCLKRX[1:0] bits (Receive clock selection) */

+#define SDMMC_CLKCR_SELCLKRX_0           (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00100000 */

+#define SDMMC_CLKCR_SELCLKRX_1           (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00200000 */

+

+/*******************  Bit definition for SDMMC_ARG register  *******************/

+#define SDMMC_ARG_CMDARG_Pos             (0U)

+#define SDMMC_ARG_CMDARG_Msk             (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_ARG_CMDARG                 SDMMC_ARG_CMDARG_Msk                  /*!<Command argument */

+

+/*******************  Bit definition for SDMMC_CMD register  *******************/

+#define SDMMC_CMD_CMDINDEX_Pos           (0U)

+#define SDMMC_CMD_CMDINDEX_Msk           (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)    /*!< 0x0000003F */

+#define SDMMC_CMD_CMDINDEX               SDMMC_CMD_CMDINDEX_Msk                /*!<Command Index                               */

+#define SDMMC_CMD_CMDTRANS_Pos           (6U)

+#define SDMMC_CMD_CMDTRANS_Msk           (0x1UL << SDMMC_CMD_CMDTRANS_Pos)     /*!< 0x00000040 */

+#define SDMMC_CMD_CMDTRANS               SDMMC_CMD_CMDTRANS_Msk                /*!<CPSM Treats command as a Data Transfer      */

+#define SDMMC_CMD_CMDSTOP_Pos            (7U)

+#define SDMMC_CMD_CMDSTOP_Msk            (0x1UL << SDMMC_CMD_CMDSTOP_Pos)      /*!< 0x00000080 */

+#define SDMMC_CMD_CMDSTOP                SDMMC_CMD_CMDSTOP_Msk                 /*!<CPSM Treats command as a Stop               */

+

+#define SDMMC_CMD_WAITRESP_Pos           (8U)

+#define SDMMC_CMD_WAITRESP_Msk           (0x3UL << SDMMC_CMD_WAITRESP_Pos)     /*!< 0x00000300 */

+#define SDMMC_CMD_WAITRESP               SDMMC_CMD_WAITRESP_Msk                /*!<WAITRESP[1:0] bits (Wait for response bits) */

+#define SDMMC_CMD_WAITRESP_0             (0x1UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000100 */

+#define SDMMC_CMD_WAITRESP_1             (0x2UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000200 */

+

+#define SDMMC_CMD_WAITINT_Pos            (10U)

+#define SDMMC_CMD_WAITINT_Msk            (0x1UL << SDMMC_CMD_WAITINT_Pos)      /*!< 0x00000400 */

+#define SDMMC_CMD_WAITINT                SDMMC_CMD_WAITINT_Msk                 /*!<CPSM Waits for Interrupt Request                               */

+#define SDMMC_CMD_WAITPEND_Pos           (11U)

+#define SDMMC_CMD_WAITPEND_Msk           (0x1UL << SDMMC_CMD_WAITPEND_Pos)     /*!< 0x00000800 */

+#define SDMMC_CMD_WAITPEND               SDMMC_CMD_WAITPEND_Msk                /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */

+#define SDMMC_CMD_CPSMEN_Pos             (12U)

+#define SDMMC_CMD_CPSMEN_Msk             (0x1UL << SDMMC_CMD_CPSMEN_Pos)       /*!< 0x00001000 */

+#define SDMMC_CMD_CPSMEN                 SDMMC_CMD_CPSMEN_Msk                  /*!<Command path state machine (CPSM) Enable bit                   */

+#define SDMMC_CMD_DTHOLD_Pos             (13U)

+#define SDMMC_CMD_DTHOLD_Msk             (0x1UL << SDMMC_CMD_DTHOLD_Pos)       /*!< 0x00002000 */

+#define SDMMC_CMD_DTHOLD                 SDMMC_CMD_DTHOLD_Msk                  /*!<Hold new data block transmission and reception in the DPSM     */

+#define SDMMC_CMD_BOOTMODE_Pos           (14U)

+#define SDMMC_CMD_BOOTMODE_Msk           (0x1UL << SDMMC_CMD_BOOTMODE_Pos)     /*!< 0x00004000 */

+#define SDMMC_CMD_BOOTMODE               SDMMC_CMD_BOOTMODE_Msk                /*!<Boot mode                                                      */

+#define SDMMC_CMD_BOOTEN_Pos             (15U)

+#define SDMMC_CMD_BOOTEN_Msk             (0x1UL << SDMMC_CMD_BOOTEN_Pos)       /*!< 0x00008000 */

+#define SDMMC_CMD_BOOTEN                 SDMMC_CMD_BOOTEN_Msk                  /*!<Enable Boot mode procedure                                     */

+#define SDMMC_CMD_CMDSUSPEND_Pos         (16U)

+#define SDMMC_CMD_CMDSUSPEND_Msk         (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)   /*!< 0x00010000 */

+#define SDMMC_CMD_CMDSUSPEND             SDMMC_CMD_CMDSUSPEND_Msk              /*!<CPSM Treats command as a Suspend or Resume command             */

+

+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/

+#define SDMMC_RESPCMD_RESPCMD_Pos        (0U)

+#define SDMMC_RESPCMD_RESPCMD_Msk        (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */

+#define SDMMC_RESPCMD_RESPCMD            SDMMC_RESPCMD_RESPCMD_Msk             /*!<Response command index */

+

+/******************  Bit definition for SDMMC_RESP0 register  ******************/

+#define SDMMC_RESP0_CARDSTATUS0_Pos      (0U)

+#define SDMMC_RESP0_CARDSTATUS0_Msk      (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP0_CARDSTATUS0          SDMMC_RESP0_CARDSTATUS0_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP1 register  ******************/

+#define SDMMC_RESP1_CARDSTATUS1_Pos      (0U)

+#define SDMMC_RESP1_CARDSTATUS1_Msk      (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP1_CARDSTATUS1          SDMMC_RESP1_CARDSTATUS1_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP2 register  ******************/

+#define SDMMC_RESP2_CARDSTATUS2_Pos      (0U)

+#define SDMMC_RESP2_CARDSTATUS2_Msk      (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP2_CARDSTATUS2          SDMMC_RESP2_CARDSTATUS2_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP3 register  ******************/

+#define SDMMC_RESP3_CARDSTATUS3_Pos      (0U)

+#define SDMMC_RESP3_CARDSTATUS3_Msk      (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP3_CARDSTATUS3          SDMMC_RESP3_CARDSTATUS3_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP4 register  ******************/

+#define SDMMC_RESP4_CARDSTATUS4_Pos      (0U)

+#define SDMMC_RESP4_CARDSTATUS4_Msk      (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP4_CARDSTATUS4          SDMMC_RESP4_CARDSTATUS4_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_DTIMER register  *****************/

+#define SDMMC_DTIMER_DATATIME_Pos        (0U)

+#define SDMMC_DTIMER_DATATIME_Msk        (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_DTIMER_DATATIME            SDMMC_DTIMER_DATATIME_Msk             /*!<Data timeout period. */

+

+/******************  Bit definition for SDMMC_DLEN register  *******************/

+#define SDMMC_DLEN_DATALENGTH_Pos        (0U)

+#define SDMMC_DLEN_DATALENGTH_Msk        (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_DLEN_DATALENGTH            SDMMC_DLEN_DATALENGTH_Msk             /*!<Data length value    */

+

+/******************  Bit definition for SDMMC_DCTRL register  ******************/

+#define SDMMC_DCTRL_DTEN_Pos             (0U)

+#define SDMMC_DCTRL_DTEN_Msk             (0x1UL << SDMMC_DCTRL_DTEN_Pos)       /*!< 0x00000001 */

+#define SDMMC_DCTRL_DTEN                 SDMMC_DCTRL_DTEN_Msk                  /*!<Data transfer enabled bit                */

+#define SDMMC_DCTRL_DTDIR_Pos            (1U)

+#define SDMMC_DCTRL_DTDIR_Msk            (0x1UL << SDMMC_DCTRL_DTDIR_Pos)      /*!< 0x00000002 */

+#define SDMMC_DCTRL_DTDIR                SDMMC_DCTRL_DTDIR_Msk                 /*!<Data transfer direction selection        */

+#define SDMMC_DCTRL_DTMODE_Pos           (2U)

+#define SDMMC_DCTRL_DTMODE_Msk           (0x3UL << SDMMC_DCTRL_DTMODE_Pos)     /*!< 0x0000000C */

+#define SDMMC_DCTRL_DTMODE               SDMMC_DCTRL_DTMODE_Msk                /*!<DTMODE[1:0] Data transfer mode selection */

+#define SDMMC_DCTRL_DTMODE_0             (0x1UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000004 */

+#define SDMMC_DCTRL_DTMODE_1             (0x2UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000008 */

+

+#define SDMMC_DCTRL_DBLOCKSIZE_Pos       (4U)

+#define SDMMC_DCTRL_DBLOCKSIZE_Msk       (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */

+#define SDMMC_DCTRL_DBLOCKSIZE           SDMMC_DCTRL_DBLOCKSIZE_Msk            /*!<DBLOCKSIZE[3:0] bits (Data block size) */

+#define SDMMC_DCTRL_DBLOCKSIZE_0         (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000010 */

+#define SDMMC_DCTRL_DBLOCKSIZE_1         (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000020 */

+#define SDMMC_DCTRL_DBLOCKSIZE_2         (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000040 */

+#define SDMMC_DCTRL_DBLOCKSIZE_3         (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000080 */

+

+#define SDMMC_DCTRL_RWSTART_Pos          (8U)

+#define SDMMC_DCTRL_RWSTART_Msk          (0x1UL << SDMMC_DCTRL_RWSTART_Pos)    /*!< 0x00000100 */

+#define SDMMC_DCTRL_RWSTART              SDMMC_DCTRL_RWSTART_Msk               /*!<Read wait start                                 */

+#define SDMMC_DCTRL_RWSTOP_Pos           (9U)

+#define SDMMC_DCTRL_RWSTOP_Msk           (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)     /*!< 0x00000200 */

+#define SDMMC_DCTRL_RWSTOP               SDMMC_DCTRL_RWSTOP_Msk                /*!<Read wait stop                                  */

+#define SDMMC_DCTRL_RWMOD_Pos            (10U)

+#define SDMMC_DCTRL_RWMOD_Msk            (0x1UL << SDMMC_DCTRL_RWMOD_Pos)      /*!< 0x00000400 */

+#define SDMMC_DCTRL_RWMOD                SDMMC_DCTRL_RWMOD_Msk                 /*!<Read wait mode                                  */

+#define SDMMC_DCTRL_SDIOEN_Pos           (11U)

+#define SDMMC_DCTRL_SDIOEN_Msk           (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)     /*!< 0x00000800 */

+#define SDMMC_DCTRL_SDIOEN               SDMMC_DCTRL_SDIOEN_Msk                /*!<SD I/O enable functions                         */

+#define SDMMC_DCTRL_BOOTACKEN_Pos        (12U)

+#define SDMMC_DCTRL_BOOTACKEN_Msk        (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)  /*!< 0x00001000 */

+#define SDMMC_DCTRL_BOOTACKEN            SDMMC_DCTRL_BOOTACKEN_Msk             /*!<Enable the reception of the Boot Acknowledgment */

+#define SDMMC_DCTRL_FIFORST_Pos          (13U)

+#define SDMMC_DCTRL_FIFORST_Msk          (0x1UL << SDMMC_DCTRL_FIFORST_Pos)    /*!< 0x00002000 */

+#define SDMMC_DCTRL_FIFORST              SDMMC_DCTRL_FIFORST_Msk               /*!<FIFO reset                                      */

+

+/******************  Bit definition for SDMMC_DCOUNT register  *****************/

+#define SDMMC_DCOUNT_DATACOUNT_Pos       (0U)

+#define SDMMC_DCOUNT_DATACOUNT_Msk       (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_DCOUNT_DATACOUNT           SDMMC_DCOUNT_DATACOUNT_Msk            /*!<Data count value */

+

+/******************  Bit definition for SDMMC_STA register  ********************/

+#define SDMMC_STA_CCRCFAIL_Pos           (0U)

+#define SDMMC_STA_CCRCFAIL_Msk           (0x1UL << SDMMC_STA_CCRCFAIL_Pos)     /*!< 0x00000001 */

+#define SDMMC_STA_CCRCFAIL               SDMMC_STA_CCRCFAIL_Msk                /*!<Command response received (CRC check failed)  */

+#define SDMMC_STA_DCRCFAIL_Pos           (1U)

+#define SDMMC_STA_DCRCFAIL_Msk           (0x1UL << SDMMC_STA_DCRCFAIL_Pos)     /*!< 0x00000002 */

+#define SDMMC_STA_DCRCFAIL               SDMMC_STA_DCRCFAIL_Msk                /*!<Data block sent/received (CRC check failed)   */

+#define SDMMC_STA_CTIMEOUT_Pos           (2U)

+#define SDMMC_STA_CTIMEOUT_Msk           (0x1UL << SDMMC_STA_CTIMEOUT_Pos)     /*!< 0x00000004 */

+#define SDMMC_STA_CTIMEOUT               SDMMC_STA_CTIMEOUT_Msk                /*!<Command response timeout                      */

+#define SDMMC_STA_DTIMEOUT_Pos           (3U)

+#define SDMMC_STA_DTIMEOUT_Msk           (0x1UL << SDMMC_STA_DTIMEOUT_Pos)     /*!< 0x00000008 */

+#define SDMMC_STA_DTIMEOUT               SDMMC_STA_DTIMEOUT_Msk                /*!<Data timeout                                  */

+#define SDMMC_STA_TXUNDERR_Pos           (4U)

+#define SDMMC_STA_TXUNDERR_Msk           (0x1UL << SDMMC_STA_TXUNDERR_Pos)     /*!< 0x00000010 */

+#define SDMMC_STA_TXUNDERR               SDMMC_STA_TXUNDERR_Msk                /*!<Transmit FIFO underrun error                  */

+#define SDMMC_STA_RXOVERR_Pos            (5U)

+#define SDMMC_STA_RXOVERR_Msk            (0x1UL << SDMMC_STA_RXOVERR_Pos)      /*!< 0x00000020 */

+#define SDMMC_STA_RXOVERR                SDMMC_STA_RXOVERR_Msk                 /*!<Received FIFO overrun error                   */

+#define SDMMC_STA_CMDREND_Pos            (6U)

+#define SDMMC_STA_CMDREND_Msk            (0x1UL << SDMMC_STA_CMDREND_Pos)      /*!< 0x00000040 */

+#define SDMMC_STA_CMDREND                SDMMC_STA_CMDREND_Msk                 /*!<Command response received (CRC check passed)  */

+#define SDMMC_STA_CMDSENT_Pos            (7U)

+#define SDMMC_STA_CMDSENT_Msk            (0x1UL << SDMMC_STA_CMDSENT_Pos)      /*!< 0x00000080 */

+#define SDMMC_STA_CMDSENT                SDMMC_STA_CMDSENT_Msk                 /*!<Command sent (no response required)           */

+#define SDMMC_STA_DATAEND_Pos            (8U)

+#define SDMMC_STA_DATAEND_Msk            (0x1UL << SDMMC_STA_DATAEND_Pos)      /*!< 0x00000100 */

+#define SDMMC_STA_DATAEND                SDMMC_STA_DATAEND_Msk                 /*!<Data end (data counter, SDIDCOUNT, is zero)   */

+#define SDMMC_STA_DHOLD_Pos              (9U)

+#define SDMMC_STA_DHOLD_Msk              (0x1UL << SDMMC_STA_DHOLD_Pos)        /*!< 0x00000200 */

+#define SDMMC_STA_DHOLD                  SDMMC_STA_DHOLD_Msk                   /*!<Data transfer Hold                                                      */

+#define SDMMC_STA_DBCKEND_Pos            (10U)

+#define SDMMC_STA_DBCKEND_Msk            (0x1UL << SDMMC_STA_DBCKEND_Pos)      /*!< 0x00000400 */

+#define SDMMC_STA_DBCKEND                SDMMC_STA_DBCKEND_Msk                 /*!<Data block sent/received (CRC check passed)   */

+#define SDMMC_STA_DABORT_Pos             (11U)

+#define SDMMC_STA_DABORT_Msk             (0x1UL << SDMMC_STA_DABORT_Pos)       /*!< 0x00000800 */

+#define SDMMC_STA_DABORT                 SDMMC_STA_DABORT_Msk                  /*!<Data transfer aborted by CMD12                                          */

+#define SDMMC_STA_DPSMACT_Pos            (12U)

+#define SDMMC_STA_DPSMACT_Msk            (0x1UL << SDMMC_STA_DPSMACT_Pos)      /*!< 0x00001000 */

+#define SDMMC_STA_DPSMACT                SDMMC_STA_DPSMACT_Msk                 /*!<Data path state machine active                                       */

+#define SDMMC_STA_CPSMACT_Pos            (13U)

+#define SDMMC_STA_CPSMACT_Msk            (0x1UL << SDMMC_STA_CPSMACT_Pos)      /*!< 0x00002000 */

+#define SDMMC_STA_CPSMACT                SDMMC_STA_CPSMACT_Msk                 /*!<Command path state machine active                                          */

+#define SDMMC_STA_TXFIFOHE_Pos           (14U)

+#define SDMMC_STA_TXFIFOHE_Msk           (0x1UL << SDMMC_STA_TXFIFOHE_Pos)     /*!< 0x00004000 */

+#define SDMMC_STA_TXFIFOHE               SDMMC_STA_TXFIFOHE_Msk                /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */

+#define SDMMC_STA_RXFIFOHF_Pos           (15U)

+#define SDMMC_STA_RXFIFOHF_Msk           (0x1UL << SDMMC_STA_RXFIFOHF_Pos)     /*!< 0x00008000 */

+#define SDMMC_STA_RXFIFOHF               SDMMC_STA_RXFIFOHF_Msk                /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */

+#define SDMMC_STA_TXFIFOF_Pos            (16U)

+#define SDMMC_STA_TXFIFOF_Msk            (0x1UL << SDMMC_STA_TXFIFOF_Pos)      /*!< 0x00010000 */

+#define SDMMC_STA_TXFIFOF                SDMMC_STA_TXFIFOF_Msk                 /*!<Transmit FIFO full                            */

+#define SDMMC_STA_RXFIFOF_Pos            (17U)

+#define SDMMC_STA_RXFIFOF_Msk            (0x1UL << SDMMC_STA_RXFIFOF_Pos)      /*!< 0x00020000 */

+#define SDMMC_STA_RXFIFOF                SDMMC_STA_RXFIFOF_Msk                 /*!<Receive FIFO full                             */

+#define SDMMC_STA_TXFIFOE_Pos            (18U)

+#define SDMMC_STA_TXFIFOE_Msk            (0x1UL << SDMMC_STA_TXFIFOE_Pos)      /*!< 0x00040000 */

+#define SDMMC_STA_TXFIFOE                SDMMC_STA_TXFIFOE_Msk                 /*!<Transmit FIFO empty                           */

+#define SDMMC_STA_RXFIFOE_Pos            (19U)

+#define SDMMC_STA_RXFIFOE_Msk            (0x1UL << SDMMC_STA_RXFIFOE_Pos)      /*!< 0x00080000 */

+#define SDMMC_STA_RXFIFOE                SDMMC_STA_RXFIFOE_Msk                 /*!<Receive FIFO empty                            */

+#define SDMMC_STA_BUSYD0_Pos             (20U)

+#define SDMMC_STA_BUSYD0_Msk             (0x1UL << SDMMC_STA_BUSYD0_Pos)       /*!< 0x00100000 */

+#define SDMMC_STA_BUSYD0                 SDMMC_STA_BUSYD0_Msk                  /*!<Inverted value of SDMMC_D0 line (Busy)                                  */

+#define SDMMC_STA_BUSYD0END_Pos          (21U)

+#define SDMMC_STA_BUSYD0END_Msk          (0x1UL << SDMMC_STA_BUSYD0END_Pos)    /*!< 0x00200000 */

+#define SDMMC_STA_BUSYD0END              SDMMC_STA_BUSYD0END_Msk               /*!<End of SDMMC_D0 Busy following a CMD response detected                  */

+#define SDMMC_STA_SDIOIT_Pos             (22U)

+#define SDMMC_STA_SDIOIT_Msk             (0x1UL << SDMMC_STA_SDIOIT_Pos)       /*!< 0x00400000 */

+#define SDMMC_STA_SDIOIT                 SDMMC_STA_SDIOIT_Msk                  /*!<SDIO interrupt received                                                 */

+#define SDMMC_STA_ACKFAIL_Pos            (23U)

+#define SDMMC_STA_ACKFAIL_Msk            (0x1UL << SDMMC_STA_ACKFAIL_Pos)      /*!< 0x00800000 */

+#define SDMMC_STA_ACKFAIL                SDMMC_STA_ACKFAIL_Msk                 /*!<Boot Acknowledgment received (BootAck check fail)                       */

+#define SDMMC_STA_ACKTIMEOUT_Pos         (24U)

+#define SDMMC_STA_ACKTIMEOUT_Msk         (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)   /*!< 0x01000000 */

+#define SDMMC_STA_ACKTIMEOUT             SDMMC_STA_ACKTIMEOUT_Msk              /*!<Boot Acknowledgment timeout                                             */

+#define SDMMC_STA_VSWEND_Pos             (25U)

+#define SDMMC_STA_VSWEND_Msk             (0x1UL << SDMMC_STA_VSWEND_Pos)       /*!< 0x02000000 */

+#define SDMMC_STA_VSWEND                 SDMMC_STA_VSWEND_Msk                  /*!<Voltage switch critical timing section completion                       */

+#define SDMMC_STA_CKSTOP_Pos             (26U)

+#define SDMMC_STA_CKSTOP_Msk             (0x1UL << SDMMC_STA_CKSTOP_Pos)       /*!< 0x04000000 */

+#define SDMMC_STA_CKSTOP                 SDMMC_STA_CKSTOP_Msk                  /*!<SDMMC_CK stopped in Voltage switch procedure                            */

+#define SDMMC_STA_IDMATE_Pos             (27U)

+#define SDMMC_STA_IDMATE_Msk             (0x1UL << SDMMC_STA_IDMATE_Pos)       /*!< 0x08000000 */

+#define SDMMC_STA_IDMATE                 SDMMC_STA_IDMATE_Msk                  /*!<IDMA transfer error                                                     */

+#define SDMMC_STA_IDMABTC_Pos            (28U)

+#define SDMMC_STA_IDMABTC_Msk            (0x1UL << SDMMC_STA_IDMABTC_Pos)      /*!< 0x10000000 */

+#define SDMMC_STA_IDMABTC                SDMMC_STA_IDMABTC_Msk                 /*!<IDMA buffer transfer complete                                           */

+

+/*******************  Bit definition for SDMMC_ICR register  *******************/

+#define SDMMC_ICR_CCRCFAILC_Pos          (0U)

+#define SDMMC_ICR_CCRCFAILC_Msk          (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)    /*!< 0x00000001 */

+#define SDMMC_ICR_CCRCFAILC              SDMMC_ICR_CCRCFAILC_Msk               /*!<CCRCFAIL flag clear bit */

+#define SDMMC_ICR_DCRCFAILC_Pos          (1U)

+#define SDMMC_ICR_DCRCFAILC_Msk          (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)    /*!< 0x00000002 */

+#define SDMMC_ICR_DCRCFAILC              SDMMC_ICR_DCRCFAILC_Msk               /*!<DCRCFAIL flag clear bit */

+#define SDMMC_ICR_CTIMEOUTC_Pos          (2U)

+#define SDMMC_ICR_CTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)    /*!< 0x00000004 */

+#define SDMMC_ICR_CTIMEOUTC              SDMMC_ICR_CTIMEOUTC_Msk               /*!<CTIMEOUT flag clear bit */

+#define SDMMC_ICR_DTIMEOUTC_Pos          (3U)

+#define SDMMC_ICR_DTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)    /*!< 0x00000008 */

+#define SDMMC_ICR_DTIMEOUTC              SDMMC_ICR_DTIMEOUTC_Msk               /*!<DTIMEOUT flag clear bit */

+#define SDMMC_ICR_TXUNDERRC_Pos          (4U)

+#define SDMMC_ICR_TXUNDERRC_Msk          (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)    /*!< 0x00000010 */

+#define SDMMC_ICR_TXUNDERRC              SDMMC_ICR_TXUNDERRC_Msk               /*!<TXUNDERR flag clear bit */

+#define SDMMC_ICR_RXOVERRC_Pos           (5U)

+#define SDMMC_ICR_RXOVERRC_Msk           (0x1UL << SDMMC_ICR_RXOVERRC_Pos)     /*!< 0x00000020 */

+#define SDMMC_ICR_RXOVERRC               SDMMC_ICR_RXOVERRC_Msk                /*!<RXOVERR flag clear bit  */

+#define SDMMC_ICR_CMDRENDC_Pos           (6U)

+#define SDMMC_ICR_CMDRENDC_Msk           (0x1UL << SDMMC_ICR_CMDRENDC_Pos)     /*!< 0x00000040 */

+#define SDMMC_ICR_CMDRENDC               SDMMC_ICR_CMDRENDC_Msk                /*!<CMDREND flag clear bit  */

+#define SDMMC_ICR_CMDSENTC_Pos           (7U)

+#define SDMMC_ICR_CMDSENTC_Msk           (0x1UL << SDMMC_ICR_CMDSENTC_Pos)     /*!< 0x00000080 */

+#define SDMMC_ICR_CMDSENTC               SDMMC_ICR_CMDSENTC_Msk                /*!<CMDSENT flag clear bit  */

+#define SDMMC_ICR_DATAENDC_Pos           (8U)

+#define SDMMC_ICR_DATAENDC_Msk           (0x1UL << SDMMC_ICR_DATAENDC_Pos)     /*!< 0x00000100 */

+#define SDMMC_ICR_DATAENDC               SDMMC_ICR_DATAENDC_Msk                /*!<DATAEND flag clear bit  */

+#define SDMMC_ICR_DHOLDC_Pos             (9U)

+#define SDMMC_ICR_DHOLDC_Msk             (0x1UL << SDMMC_ICR_DHOLDC_Pos)       /*!< 0x00000200 */

+#define SDMMC_ICR_DHOLDC                 SDMMC_ICR_DHOLDC_Msk                  /*!<DHOLD flag clear bit       */

+#define SDMMC_ICR_DBCKENDC_Pos           (10U)

+#define SDMMC_ICR_DBCKENDC_Msk           (0x1UL << SDMMC_ICR_DBCKENDC_Pos)     /*!< 0x00000400 */

+#define SDMMC_ICR_DBCKENDC               SDMMC_ICR_DBCKENDC_Msk                /*!<DBCKEND flag clear bit  */

+#define SDMMC_ICR_DABORTC_Pos            (11U)

+#define SDMMC_ICR_DABORTC_Msk            (0x1UL << SDMMC_ICR_DABORTC_Pos)      /*!< 0x00000800 */

+#define SDMMC_ICR_DABORTC                SDMMC_ICR_DABORTC_Msk                 /*!<DABORTC flag clear bit     */

+#define SDMMC_ICR_BUSYD0ENDC_Pos         (21U)

+#define SDMMC_ICR_BUSYD0ENDC_Msk         (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)   /*!< 0x00200000 */

+#define SDMMC_ICR_BUSYD0ENDC             SDMMC_ICR_BUSYD0ENDC_Msk              /*!<BUSYD0ENDC flag clear bit  */

+#define SDMMC_ICR_SDIOITC_Pos            (22U)

+#define SDMMC_ICR_SDIOITC_Msk            (0x1UL << SDMMC_ICR_SDIOITC_Pos)      /*!< 0x00400000 */

+#define SDMMC_ICR_SDIOITC                SDMMC_ICR_SDIOITC_Msk                 /*!<SDIOIT flag clear bit      */

+#define SDMMC_ICR_ACKFAILC_Pos           (23U)

+#define SDMMC_ICR_ACKFAILC_Msk           (0x1UL << SDMMC_ICR_ACKFAILC_Pos)     /*!< 0x00800000 */

+#define SDMMC_ICR_ACKFAILC               SDMMC_ICR_ACKFAILC_Msk                /*!<ACKFAILC flag clear bit    */

+#define SDMMC_ICR_ACKTIMEOUTC_Pos        (24U)

+#define SDMMC_ICR_ACKTIMEOUTC_Msk        (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)  /*!< 0x01000000 */

+#define SDMMC_ICR_ACKTIMEOUTC            SDMMC_ICR_ACKTIMEOUTC_Msk             /*!<ACKTIMEOUTC flag clear bit */

+#define SDMMC_ICR_VSWENDC_Pos            (25U)

+#define SDMMC_ICR_VSWENDC_Msk            (0x1UL << SDMMC_ICR_VSWENDC_Pos)      /*!< 0x02000000 */

+#define SDMMC_ICR_VSWENDC                SDMMC_ICR_VSWENDC_Msk                 /*!<VSWENDC flag clear bit     */

+#define SDMMC_ICR_CKSTOPC_Pos            (26U)

+#define SDMMC_ICR_CKSTOPC_Msk            (0x1UL << SDMMC_ICR_CKSTOPC_Pos)      /*!< 0x04000000 */

+#define SDMMC_ICR_CKSTOPC                SDMMC_ICR_CKSTOPC_Msk                 /*!<CKSTOPC flag clear bit     */

+#define SDMMC_ICR_IDMATEC_Pos            (27U)

+#define SDMMC_ICR_IDMATEC_Msk            (0x1UL << SDMMC_ICR_IDMATEC_Pos)      /*!< 0x08000000 */

+#define SDMMC_ICR_IDMATEC                SDMMC_ICR_IDMATEC_Msk                 /*!<IDMATEC flag clear bit     */

+#define SDMMC_ICR_IDMABTCC_Pos           (28U)

+#define SDMMC_ICR_IDMABTCC_Msk           (0x1UL << SDMMC_ICR_IDMABTCC_Pos)     /*!< 0x10000000 */

+#define SDMMC_ICR_IDMABTCC               SDMMC_ICR_IDMABTCC_Msk                /*!<IDMABTCC flag clear bit    */

+

+/******************  Bit definition for SDMMC_MASK register  *******************/

+#define SDMMC_MASK_CCRCFAILIE_Pos        (0U)

+#define SDMMC_MASK_CCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)  /*!< 0x00000001 */

+#define SDMMC_MASK_CCRCFAILIE            SDMMC_MASK_CCRCFAILIE_Msk             /*!<Command CRC Fail Interrupt Enable          */

+#define SDMMC_MASK_DCRCFAILIE_Pos        (1U)

+#define SDMMC_MASK_DCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)  /*!< 0x00000002 */

+#define SDMMC_MASK_DCRCFAILIE            SDMMC_MASK_DCRCFAILIE_Msk             /*!<Data CRC Fail Interrupt Enable             */

+#define SDMMC_MASK_CTIMEOUTIE_Pos        (2U)

+#define SDMMC_MASK_CTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)  /*!< 0x00000004 */

+#define SDMMC_MASK_CTIMEOUTIE            SDMMC_MASK_CTIMEOUTIE_Msk             /*!<Command TimeOut Interrupt Enable           */

+#define SDMMC_MASK_DTIMEOUTIE_Pos        (3U)

+#define SDMMC_MASK_DTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)  /*!< 0x00000008 */

+#define SDMMC_MASK_DTIMEOUTIE            SDMMC_MASK_DTIMEOUTIE_Msk             /*!<Data TimeOut Interrupt Enable              */

+#define SDMMC_MASK_TXUNDERRIE_Pos        (4U)

+#define SDMMC_MASK_TXUNDERRIE_Msk        (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)  /*!< 0x00000010 */

+#define SDMMC_MASK_TXUNDERRIE            SDMMC_MASK_TXUNDERRIE_Msk             /*!<Tx FIFO UnderRun Error Interrupt Enable    */

+#define SDMMC_MASK_RXOVERRIE_Pos         (5U)

+#define SDMMC_MASK_RXOVERRIE_Msk         (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)   /*!< 0x00000020 */

+#define SDMMC_MASK_RXOVERRIE             SDMMC_MASK_RXOVERRIE_Msk              /*!<Rx FIFO OverRun Error Interrupt Enable     */

+#define SDMMC_MASK_CMDRENDIE_Pos         (6U)

+#define SDMMC_MASK_CMDRENDIE_Msk         (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)   /*!< 0x00000040 */

+#define SDMMC_MASK_CMDRENDIE             SDMMC_MASK_CMDRENDIE_Msk              /*!<Command Response Received Interrupt Enable */

+#define SDMMC_MASK_CMDSENTIE_Pos         (7U)

+#define SDMMC_MASK_CMDSENTIE_Msk         (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)   /*!< 0x00000080 */

+#define SDMMC_MASK_CMDSENTIE             SDMMC_MASK_CMDSENTIE_Msk              /*!<Command Sent Interrupt Enable              */

+#define SDMMC_MASK_DATAENDIE_Pos         (8U)

+#define SDMMC_MASK_DATAENDIE_Msk         (0x1UL << SDMMC_MASK_DATAENDIE_Pos)   /*!< 0x00000100 */

+#define SDMMC_MASK_DATAENDIE             SDMMC_MASK_DATAENDIE_Msk              /*!<Data End Interrupt Enable                  */

+#define SDMMC_MASK_DHOLDIE_Pos           (9U)

+#define SDMMC_MASK_DHOLDIE_Msk           (0x1UL << SDMMC_MASK_DHOLDIE_Pos)     /*!< 0x00000200 */

+#define SDMMC_MASK_DHOLDIE               SDMMC_MASK_DHOLDIE_Msk                /*!<Data Hold Interrupt Enable                 */

+#define SDMMC_MASK_DBCKENDIE_Pos         (10U)

+#define SDMMC_MASK_DBCKENDIE_Msk         (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)   /*!< 0x00000400 */

+#define SDMMC_MASK_DBCKENDIE             SDMMC_MASK_DBCKENDIE_Msk              /*!<Data Block End Interrupt Enable            */

+#define SDMMC_MASK_DABORTIE_Pos          (11U)

+#define SDMMC_MASK_DABORTIE_Msk          (0x1UL << SDMMC_MASK_DABORTIE_Pos)    /*!< 0x00000800 */

+#define SDMMC_MASK_DABORTIE              SDMMC_MASK_DABORTIE_Msk               /*!<Data transfer aborted interrupt enable     */

+

+#define SDMMC_MASK_TXFIFOHEIE_Pos        (14U)

+#define SDMMC_MASK_TXFIFOHEIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)  /*!< 0x00004000 */

+#define SDMMC_MASK_TXFIFOHEIE            SDMMC_MASK_TXFIFOHEIE_Msk             /*!<Tx FIFO Half Empty interrupt Enable        */

+#define SDMMC_MASK_RXFIFOHFIE_Pos        (15U)

+#define SDMMC_MASK_RXFIFOHFIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)  /*!< 0x00008000 */

+#define SDMMC_MASK_RXFIFOHFIE            SDMMC_MASK_RXFIFOHFIE_Msk             /*!<Rx FIFO Half Full interrupt Enable         */

+

+#define SDMMC_MASK_RXFIFOFIE_Pos         (17U)

+#define SDMMC_MASK_RXFIFOFIE_Msk         (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)   /*!< 0x00020000 */

+#define SDMMC_MASK_RXFIFOFIE             SDMMC_MASK_RXFIFOFIE_Msk              /*!<Rx FIFO Full interrupt Enable              */

+#define SDMMC_MASK_TXFIFOEIE_Pos         (18U)

+#define SDMMC_MASK_TXFIFOEIE_Msk         (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)   /*!< 0x00040000 */

+#define SDMMC_MASK_TXFIFOEIE             SDMMC_MASK_TXFIFOEIE_Msk              /*!<Tx FIFO Empty interrupt Enable             */

+

+#define SDMMC_MASK_BUSYD0ENDIE_Pos       (21U)

+#define SDMMC_MASK_BUSYD0ENDIE_Msk       (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */

+#define SDMMC_MASK_BUSYD0ENDIE           SDMMC_MASK_BUSYD0ENDIE_Msk            /*!<BUSYD0ENDIE interrupt Enable */

+#define SDMMC_MASK_SDIOITIE_Pos           (22U)

+#define SDMMC_MASK_SDIOITIE_Msk           (0x1UL << SDMMC_MASK_SDIOITIE_Pos)     /*!< 0x00400000 */

+#define SDMMC_MASK_SDIOITIE               SDMMC_MASK_SDIOITIE_Msk                /*!<SDMMC Mode Interrupt Received interrupt Enable */

+#define SDMMC_MASK_ACKFAILIE_Pos         (23U)

+#define SDMMC_MASK_ACKFAILIE_Msk         (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)   /*!< 0x00800000 */

+#define SDMMC_MASK_ACKFAILIE             SDMMC_MASK_ACKFAILIE_Msk              /*!<Acknowledgment Fail Interrupt Enable */

+#define SDMMC_MASK_ACKTIMEOUTIE_Pos      (24U)

+#define SDMMC_MASK_ACKTIMEOUTIE_Msk      (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */

+#define SDMMC_MASK_ACKTIMEOUTIE          SDMMC_MASK_ACKTIMEOUTIE_Msk           /*!<Acknowledgment timeout Interrupt Enable */

+#define SDMMC_MASK_VSWENDIE_Pos          (25U)

+#define SDMMC_MASK_VSWENDIE_Msk          (0x1UL << SDMMC_MASK_VSWENDIE_Pos)    /*!< 0x02000000 */

+#define SDMMC_MASK_VSWENDIE              SDMMC_MASK_VSWENDIE_Msk               /*!<Voltage switch critical timing section completion Interrupt Enable */

+#define SDMMC_MASK_CKSTOPIE_Pos          (26U)

+#define SDMMC_MASK_CKSTOPIE_Msk          (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)    /*!< 0x04000000 */

+#define SDMMC_MASK_CKSTOPIE              SDMMC_MASK_CKSTOPIE_Msk               /*!<Voltage Switch clock stopped Interrupt Enable */

+#define SDMMC_MASK_IDMABTCIE_Pos         (28U)

+#define SDMMC_MASK_IDMABTCIE_Msk         (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)   /*!< 0x10000000 */

+#define SDMMC_MASK_IDMABTCIE             SDMMC_MASK_IDMABTCIE_Msk              /*!<IDMA buffer transfer complete Interrupt Enable */

+

+/*****************  Bit definition for SDMMC_ACKTIME register  *****************/

+#define SDMMC_ACKTIME_ACKTIME_Pos        (0U)

+#define SDMMC_ACKTIME_ACKTIME_Msk        (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_ACKTIME_ACKTIME            SDMMC_ACKTIME_ACKTIME_Msk             /*!<Boot acknowledgment timeout period */

+

+/******************  Bit definition for SDMMC_FIFO register  *******************/

+#define SDMMC_FIFO_FIFODATA_Pos          (0U)

+#define SDMMC_FIFO_FIFODATA_Msk          (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_FIFO_FIFODATA              SDMMC_FIFO_FIFODATA_Msk               /*!<Receive and transmit FIFO data */

+

+/******************  Bit definition for SDMMC_IDMACTRL register ****************/

+#define SDMMC_IDMA_IDMAEN_Pos            (0U)

+#define SDMMC_IDMA_IDMAEN_Msk            (0x1UL << SDMMC_IDMA_IDMAEN_Pos)      /*!< 0x00000001 */

+#define SDMMC_IDMA_IDMAEN                SDMMC_IDMA_IDMAEN_Msk                 /*!< Enable the internal DMA of the SDMMC peripheral */

+#define SDMMC_IDMA_IDMABMODE_Pos         (1U)

+#define SDMMC_IDMA_IDMABMODE_Msk         (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)   /*!< 0x00000002 */

+#define SDMMC_IDMA_IDMABMODE             SDMMC_IDMA_IDMABMODE_Msk              /*!< Enable double buffer mode for IDMA */

+#define SDMMC_IDMA_IDMABACT_Pos          (2U)

+#define SDMMC_IDMA_IDMABACT_Msk          (0x1UL << SDMMC_IDMA_IDMABACT_Pos)    /*!< 0x00000004 */

+#define SDMMC_IDMA_IDMABACT              SDMMC_IDMA_IDMABACT_Msk               /*!< Uses buffer 1 when double buffer mode is selected */

+

+/*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/

+#define SDMMC_IDMABSIZE_IDMABNDT_Pos     (5U)

+#define SDMMC_IDMABSIZE_IDMABNDT_Msk     (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */

+#define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */

+

+/*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/

+#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */

+

+/*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/

+#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                        Delay Block Interface (DLYB)                        */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for DLYB_CR register  ********************/

+#define DLYB_CR_DEN_Pos         (0U)

+#define DLYB_CR_DEN_Msk         (0x1UL << DLYB_CR_DEN_Pos)                     /*!< 0x00000001 */

+#define DLYB_CR_DEN             DLYB_CR_DEN_Msk                                /*!<Delay Block enable */

+#define DLYB_CR_SEN_Pos         (1U)

+#define DLYB_CR_SEN_Msk         (0x1UL << DLYB_CR_SEN_Pos)                     /*!< 0x00000002 */

+#define DLYB_CR_SEN             DLYB_CR_SEN_Msk                                /*!<Sampler length enable */

+

+

+/*******************  Bit definition for DLYB_CFGR register  ********************/

+#define DLYB_CFGR_SEL_Pos       (0U)

+#define DLYB_CFGR_SEL_Msk       (0xFUL << DLYB_CFGR_SEL_Pos)                   /*!< 0x0000000F */

+#define DLYB_CFGR_SEL           DLYB_CFGR_SEL_Msk                              /*!<Select the phase for the Output clock[3:0] */

+#define DLYB_CFGR_SEL_0         (0x1UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000001 */

+#define DLYB_CFGR_SEL_1         (0x2UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000002 */

+#define DLYB_CFGR_SEL_2         (0x3UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000003 */

+#define DLYB_CFGR_SEL_3         (0x8UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000008 */

+

+#define DLYB_CFGR_UNIT_Pos      (8U)

+#define DLYB_CFGR_UNIT_Msk      (0x7FUL << DLYB_CFGR_UNIT_Pos)                 /*!< 0x00007F00 */

+#define DLYB_CFGR_UNIT          DLYB_CFGR_UNIT_Msk                             /*!<Delay Defines the delay of a Unit delay cell[6:0] */

+#define DLYB_CFGR_UNIT_0        (0x01UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000100 */

+#define DLYB_CFGR_UNIT_1        (0x02UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000200 */

+#define DLYB_CFGR_UNIT_2        (0x04UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000400 */

+#define DLYB_CFGR_UNIT_3        (0x08UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000800 */

+#define DLYB_CFGR_UNIT_4        (0x10UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00001000 */

+#define DLYB_CFGR_UNIT_5        (0x20UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00002000 */

+#define DLYB_CFGR_UNIT_6        (0x40UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00004000 */

+

+#define DLYB_CFGR_LNG_Pos       (16U)

+#define DLYB_CFGR_LNG_Msk       (0xFFFUL << DLYB_CFGR_LNG_Pos)                 /*!< 0x0FFF0000 */

+#define DLYB_CFGR_LNG           DLYB_CFGR_LNG_Msk                              /*!<Delay line length value[11:0] */

+#define DLYB_CFGR_LNG_0         (0x001UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00010000 */

+#define DLYB_CFGR_LNG_1         (0x002UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00020000 */

+#define DLYB_CFGR_LNG_2         (0x004UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00040000 */

+#define DLYB_CFGR_LNG_3         (0x008UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00080000 */

+#define DLYB_CFGR_LNG_4         (0x010UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00100000 */

+#define DLYB_CFGR_LNG_5         (0x020UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00200000 */

+#define DLYB_CFGR_LNG_6         (0x040UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00400000 */

+#define DLYB_CFGR_LNG_7         (0x080UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00800000 */

+#define DLYB_CFGR_LNG_8         (0x100UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x01000000 */

+#define DLYB_CFGR_LNG_9         (0x200UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x02000000 */

+#define DLYB_CFGR_LNG_10        (0x400UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x04000000 */

+#define DLYB_CFGR_LNG_11        (0x800UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x08000000 */

+

+#define DLYB_CFGR_LNGF_Pos      (31U)

+#define DLYB_CFGR_LNGF_Msk      (0x1UL << DLYB_CFGR_LNGF_Pos)                  /*!< 0x80000000 */

+#define DLYB_CFGR_LNGF          DLYB_CFGR_LNGF_Msk                             /*!<Length valid flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                   Serial Peripheral Interface (SPI/I2S)                    */

+/*                                                                            */

+/******************************************************************************/

+#define SPI_SPI6I2S_SUPPORT       /*!<SPI6 I2S support feature */

+/*******************  Bit definition for SPI_CR1 register  ********************/

+#define SPI_CR1_SPE_Pos             (0U)

+#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000001 */

+#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<Serial Peripheral Enable                         */

+#define SPI_CR1_MASRX_Pos           (8U)

+#define SPI_CR1_MASRX_Msk           (0x1UL << SPI_CR1_MASRX_Pos)               /*!< 0x00000100 */

+#define SPI_CR1_MASRX               SPI_CR1_MASRX_Msk                          /*!<Master automatic SUSP in Receive mode            */

+#define SPI_CR1_CSTART_Pos          (9U)

+#define SPI_CR1_CSTART_Msk          (0x1UL << SPI_CR1_CSTART_Pos)              /*!< 0x00000200 */

+#define SPI_CR1_CSTART              SPI_CR1_CSTART_Msk                         /*!<Master transfer start                            */

+#define SPI_CR1_CSUSP_Pos           (10U)

+#define SPI_CR1_CSUSP_Msk           (0x1UL << SPI_CR1_CSUSP_Pos)               /*!< 0x00000400 */

+#define SPI_CR1_CSUSP               SPI_CR1_CSUSP_Msk                          /*!<Master SUSPend request                           */

+#define SPI_CR1_HDDIR_Pos           (11U)

+#define SPI_CR1_HDDIR_Msk           (0x1UL << SPI_CR1_HDDIR_Pos)               /*!< 0x00000800 */

+#define SPI_CR1_HDDIR               SPI_CR1_HDDIR_Msk                          /*!<Rx/Tx direction at Half-duplex mode              */

+#define SPI_CR1_SSI_Pos             (12U)

+#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00001000 */

+#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal SS signal input level                   */

+#define SPI_CR1_CRC33_17_Pos        (13U)

+#define SPI_CR1_CRC33_17_Msk        (0x1UL << SPI_CR1_CRC33_17_Pos)            /*!< 0x00002000 */

+#define SPI_CR1_CRC33_17             SPI_CR1_CRC33_17_Msk                      /*!<32-bit CRC polynomial configuration              */

+#define SPI_CR1_RCRCINI_Pos         (14U)

+#define SPI_CR1_RCRCINI_Msk         (0x1UL << SPI_CR1_RCRCINI_Pos)             /*!< 0x00004000 */

+#define SPI_CR1_RCRCINI             SPI_CR1_RCRCINI_Msk                        /*!<CRC init pattern control for receiver            */

+#define SPI_CR1_TCRCINI_Pos         (15U)

+#define SPI_CR1_TCRCINI_Msk         (0x1UL << SPI_CR1_TCRCINI_Pos)             /*!< 0x00008000 */

+#define SPI_CR1_TCRCINI             SPI_CR1_TCRCINI_Msk                        /*!<CRC init pattern control for transmitter         */

+#define SPI_CR1_IOLOCK_Pos          (16U)

+#define SPI_CR1_IOLOCK_Msk          (0x1UL << SPI_CR1_IOLOCK_Pos)              /*!< 0x00010000 */

+#define SPI_CR1_IOLOCK              SPI_CR1_IOLOCK_Msk                         /*!<Locking the AF configuration of associated IOs   */

+

+/*******************  Bit definition for SPI_CR2 register  ********************/

+#define SPI_CR2_TSER_Pos            (16U)

+#define SPI_CR2_TSER_Msk            (0xFFFFUL << SPI_CR2_TSER_Pos)             /*!< 0xFFFF0000 */

+#define SPI_CR2_TSER                SPI_CR2_TSER_Msk                           /*!<Number of data transfer extension                */

+#define SPI_CR2_TSIZE_Pos           (0U)

+#define SPI_CR2_TSIZE_Msk           (0xFFFFUL << SPI_CR2_TSIZE_Pos)            /*!< 0x0000FFFF */

+#define SPI_CR2_TSIZE               SPI_CR2_TSIZE_Msk                          /*!<Number of data at current transfer               */

+

+/*******************  Bit definition for SPI_CFG1 register  ********************/

+#define SPI_CFG1_DSIZE_Pos          (0U)

+#define SPI_CFG1_DSIZE_Msk          (0x1FUL << SPI_CFG1_DSIZE_Pos)             /*!< 0x0000001F */

+#define SPI_CFG1_DSIZE              SPI_CFG1_DSIZE_Msk                         /*!<DSIZE[4:0]: Bits number in single SPI data frame */

+#define SPI_CFG1_DSIZE_0            (0x01UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000001 */

+#define SPI_CFG1_DSIZE_1            (0x02UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000002 */

+#define SPI_CFG1_DSIZE_2            (0x04UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000004 */

+#define SPI_CFG1_DSIZE_3            (0x08UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000008 */

+#define SPI_CFG1_DSIZE_4            (0x10UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000010 */

+

+#define SPI_CFG1_FTHLV_Pos          (5U)

+#define SPI_CFG1_FTHLV_Msk          (0xFUL << SPI_CFG1_FTHLV_Pos)              /*!< 0x000001E0 */

+#define SPI_CFG1_FTHLV              SPI_CFG1_FTHLV_Msk                         /*!<FTHVL [3:0]: FIFO threshold level*/

+#define SPI_CFG1_FTHLV_0            (0x1UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000020 */

+#define SPI_CFG1_FTHLV_1            (0x2UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000040 */

+#define SPI_CFG1_FTHLV_2            (0x4UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000080 */

+#define SPI_CFG1_FTHLV_3            (0x8UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000100 */

+

+#define SPI_CFG1_UDRCFG_Pos         (9U)

+#define SPI_CFG1_UDRCFG_Msk         (0x3UL << SPI_CFG1_UDRCFG_Pos)             /*!< 0x00000600 */

+#define SPI_CFG1_UDRCFG             SPI_CFG1_UDRCFG_Msk                        /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */

+#define SPI_CFG1_UDRCFG_0           (0x1UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000200 */

+#define SPI_CFG1_UDRCFG_1           (0x2UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000400 */

+

+

+#define SPI_CFG1_UDRDET_Pos         (11U)

+#define SPI_CFG1_UDRDET_Msk         (0x3UL << SPI_CFG1_UDRDET_Pos)             /*!< 0x00001800 */

+#define SPI_CFG1_UDRDET             SPI_CFG1_UDRDET_Msk                        /*!<UDRDET[1:0]: Detection of underrun condition     */

+#define SPI_CFG1_UDRDET_0           (0x1UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00000800 */

+#define SPI_CFG1_UDRDET_1           (0x2UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00001000 */

+

+#define SPI_CFG1_RXDMAEN_Pos        (14U)

+#define SPI_CFG1_RXDMAEN_Msk        (0x1UL << SPI_CFG1_RXDMAEN_Pos)            /*!< 0x00004000 */

+#define SPI_CFG1_RXDMAEN            SPI_CFG1_RXDMAEN_Msk                       /*!<Rx DMA stream enable                */

+#define SPI_CFG1_TXDMAEN_Pos        (15U)

+#define SPI_CFG1_TXDMAEN_Msk        (0x1UL << SPI_CFG1_TXDMAEN_Pos)            /*!< 0x00008000 */

+#define SPI_CFG1_TXDMAEN            SPI_CFG1_TXDMAEN_Msk                       /*!<Tx DMA stream enable                */

+

+#define SPI_CFG1_CRCSIZE_Pos        (16U)

+#define SPI_CFG1_CRCSIZE_Msk        (0x1FUL << SPI_CFG1_CRCSIZE_Pos)           /*!< 0x001F0000 */

+#define SPI_CFG1_CRCSIZE            SPI_CFG1_CRCSIZE_Msk                       /*!<CRCSIZE [4:0]: Length of CRC frame*/

+#define SPI_CFG1_CRCSIZE_0          (0x01UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00010000 */

+#define SPI_CFG1_CRCSIZE_1          (0x02UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00020000 */

+#define SPI_CFG1_CRCSIZE_2          (0x04UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00040000 */

+#define SPI_CFG1_CRCSIZE_3          (0x08UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00080000 */

+#define SPI_CFG1_CRCSIZE_4          (0x10UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00100000 */

+

+#define SPI_CFG1_CRCEN_Pos          (22U)

+#define SPI_CFG1_CRCEN_Msk          (0x1UL << SPI_CFG1_CRCEN_Pos)              /*!< 0x00400000 */

+#define SPI_CFG1_CRCEN              SPI_CFG1_CRCEN_Msk                         /*!<Hardware CRC computation enable */

+

+#define SPI_CFG1_MBR_Pos            (28U)

+#define SPI_CFG1_MBR_Msk            (0x7UL << SPI_CFG1_MBR_Pos)                /*!< 0x70000000 */

+#define SPI_CFG1_MBR                SPI_CFG1_MBR_Msk                           /*!<Master baud rate                */

+#define SPI_CFG1_MBR_0              (0x1UL << SPI_CFG1_MBR_Pos)                 /*!< 0x10000000 */

+#define SPI_CFG1_MBR_1              (0x2UL << SPI_CFG1_MBR_Pos)                 /*!< 0x20000000 */

+#define SPI_CFG1_MBR_2              (0x4UL << SPI_CFG1_MBR_Pos)                 /*!< 0x40000000 */

+

+/*******************  Bit definition for SPI_CFG2 register  ********************/

+#define SPI_CFG2_MSSI_Pos           (0U)

+#define SPI_CFG2_MSSI_Msk           (0xFUL << SPI_CFG2_MSSI_Pos)               /*!< 0x0000000F */

+#define SPI_CFG2_MSSI               SPI_CFG2_MSSI_Msk                          /*!<Master SS Idleness */

+#define SPI_CFG2_MSSI_0             (0x1UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000001 */

+#define SPI_CFG2_MSSI_1             (0x2UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000002 */

+#define SPI_CFG2_MSSI_2             (0x4UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000004 */

+#define SPI_CFG2_MSSI_3             (0x8UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000008 */

+

+#define SPI_CFG2_MIDI_Pos           (4U)

+#define SPI_CFG2_MIDI_Msk           (0xFUL << SPI_CFG2_MIDI_Pos)               /*!< 0x000000F0 */

+#define SPI_CFG2_MIDI               SPI_CFG2_MIDI_Msk                          /*!<Master Inter-Data Idleness */

+#define SPI_CFG2_MIDI_0             (0x1UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000010 */

+#define SPI_CFG2_MIDI_1             (0x2UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000020 */

+#define SPI_CFG2_MIDI_2             (0x4UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000040 */

+#define SPI_CFG2_MIDI_3             (0x8UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000080 */

+

+#define SPI_CFG2_IOSWP_Pos          (15U)

+#define SPI_CFG2_IOSWP_Msk          (0x1UL << SPI_CFG2_IOSWP_Pos)              /*!< 0x00008000 */

+#define SPI_CFG2_IOSWP              SPI_CFG2_IOSWP_Msk                         /*!<Swap functionality of MISO and MOSI pins */

+

+#define SPI_CFG2_COMM_Pos           (17U)

+#define SPI_CFG2_COMM_Msk           (0x3UL << SPI_CFG2_COMM_Pos)               /*!< 0x00060000 */

+#define SPI_CFG2_COMM               SPI_CFG2_COMM_Msk                          /*!<COMM [1:0]: SPI Communication Mode*/

+#define SPI_CFG2_COMM_0             (0x1UL << SPI_CFG2_COMM_Pos)                /*!< 0x00020000 */

+#define SPI_CFG2_COMM_1             (0x2UL << SPI_CFG2_COMM_Pos)                /*!< 0x00040000 */

+

+#define SPI_CFG2_SP_Pos             (19U)

+#define SPI_CFG2_SP_Msk             (0x7UL << SPI_CFG2_SP_Pos)                 /*!< 0x00380000 */

+#define SPI_CFG2_SP                 SPI_CFG2_SP_Msk                            /*!<SP[2:0]: Serial Protocol */

+#define SPI_CFG2_SP_0               (0x1UL << SPI_CFG2_SP_Pos)                  /*!< 0x00080000 */

+#define SPI_CFG2_SP_1               (0x2UL << SPI_CFG2_SP_Pos)                  /*!< 0x00100000 */

+#define SPI_CFG2_SP_2               (0x4UL << SPI_CFG2_SP_Pos)                  /*!< 0x00200000 */

+

+#define SPI_CFG2_MASTER_Pos         (22U)

+#define SPI_CFG2_MASTER_Msk         (0x1UL << SPI_CFG2_MASTER_Pos)             /*!< 0x00400000 */

+#define SPI_CFG2_MASTER             SPI_CFG2_MASTER_Msk                        /*!<SPI Master           */

+#define SPI_CFG2_LSBFRST_Pos        (23U)

+#define SPI_CFG2_LSBFRST_Msk        (0x1UL << SPI_CFG2_LSBFRST_Pos)            /*!< 0x00800000 */

+#define SPI_CFG2_LSBFRST            SPI_CFG2_LSBFRST_Msk                       /*!<Data frame format               */

+#define SPI_CFG2_CPHA_Pos           (24U)

+#define SPI_CFG2_CPHA_Msk           (0x1UL << SPI_CFG2_CPHA_Pos)               /*!< 0x01000000 */

+#define SPI_CFG2_CPHA               SPI_CFG2_CPHA_Msk                          /*!<Clock Phase      */

+#define SPI_CFG2_CPOL_Pos           (25U)

+#define SPI_CFG2_CPOL_Msk           (0x1UL << SPI_CFG2_CPOL_Pos)               /*!< 0x02000000 */

+#define SPI_CFG2_CPOL               SPI_CFG2_CPOL_Msk                          /*!<Clock Polarity   */

+#define SPI_CFG2_SSM_Pos            (26U)

+#define SPI_CFG2_SSM_Msk            (0x1UL << SPI_CFG2_SSM_Pos)                /*!< 0x04000000 */

+#define SPI_CFG2_SSM                SPI_CFG2_SSM_Msk                           /*!<Software slave management */

+

+#define SPI_CFG2_SSIOP_Pos          (28U)

+#define SPI_CFG2_SSIOP_Msk          (0x1UL << SPI_CFG2_SSIOP_Pos)              /*!< 0x10000000 */

+#define SPI_CFG2_SSIOP              SPI_CFG2_SSIOP_Msk                         /*!<SS input/output polarity */

+#define SPI_CFG2_SSOE_Pos           (29U)

+#define SPI_CFG2_SSOE_Msk           (0x1UL << SPI_CFG2_SSOE_Pos)               /*!< 0x20000000 */

+#define SPI_CFG2_SSOE               SPI_CFG2_SSOE_Msk                          /*!<SS output enable */

+#define SPI_CFG2_SSOM_Pos           (30U)

+#define SPI_CFG2_SSOM_Msk           (0x1UL << SPI_CFG2_SSOM_Pos)               /*!< 0x40000000 */

+#define SPI_CFG2_SSOM               SPI_CFG2_SSOM_Msk                          /*!<SS output management in master mode */

+

+#define SPI_CFG2_AFCNTR_Pos         (31U)

+#define SPI_CFG2_AFCNTR_Msk         (0x1UL << SPI_CFG2_AFCNTR_Pos)             /*!< 0x80000000 */

+#define SPI_CFG2_AFCNTR             SPI_CFG2_AFCNTR_Msk                        /*!<Alternate function GPIOs control */

+

+/*******************  Bit definition for SPI_IER register  ********************/

+#define SPI_IER_RXPIE_Pos           (0U)

+#define SPI_IER_RXPIE_Msk           (0x1UL << SPI_IER_RXPIE_Pos)               /*!< 0x00000001 */

+#define SPI_IER_RXPIE               SPI_IER_RXPIE_Msk                          /*!<RXP Interrupt Enable            */

+#define SPI_IER_TXPIE_Pos           (1U)

+#define SPI_IER_TXPIE_Msk           (0x1UL << SPI_IER_TXPIE_Pos)               /*!< 0x00000002 */

+#define SPI_IER_TXPIE               SPI_IER_TXPIE_Msk                          /*!<TXP interrupt enable            */

+#define SPI_IER_DXPIE_Pos           (2U)

+#define SPI_IER_DXPIE_Msk           (0x1UL << SPI_IER_DXPIE_Pos)               /*!< 0x00000004 */

+#define SPI_IER_DXPIE               SPI_IER_DXPIE_Msk                          /*!<DXP interrupt enable            */

+#define SPI_IER_EOTIE_Pos           (3U)

+#define SPI_IER_EOTIE_Msk           (0x1UL << SPI_IER_EOTIE_Pos)               /*!< 0x00000008 */

+#define SPI_IER_EOTIE               SPI_IER_EOTIE_Msk                          /*!<EOT/SUSP/TXC interrupt enable   */

+#define SPI_IER_TXTFIE_Pos          (4U)

+#define SPI_IER_TXTFIE_Msk          (0x1UL << SPI_IER_TXTFIE_Pos)              /*!< 0x00000010 */

+#define SPI_IER_TXTFIE              SPI_IER_TXTFIE_Msk                         /*!<TXTF interrupt enable           */

+#define SPI_IER_UDRIE_Pos           (5U)

+#define SPI_IER_UDRIE_Msk           (0x1UL << SPI_IER_UDRIE_Pos)               /*!< 0x00000020 */

+#define SPI_IER_UDRIE               SPI_IER_UDRIE_Msk                          /*!<UDR interrupt enable            */

+#define SPI_IER_OVRIE_Pos           (6U)

+#define SPI_IER_OVRIE_Msk           (0x1UL << SPI_IER_OVRIE_Pos)               /*!< 0x00000040 */

+#define SPI_IER_OVRIE               SPI_IER_OVRIE_Msk                          /*!<OVR interrupt enable            */

+#define SPI_IER_CRCEIE_Pos          (7U)

+#define SPI_IER_CRCEIE_Msk          (0x1UL << SPI_IER_CRCEIE_Pos)               /*!< 0x00000080 */

+#define SPI_IER_CRCEIE              SPI_IER_CRCEIE_Msk                          /*!<CRCE interrupt enable           */

+#define SPI_IER_TIFREIE_Pos         (8U)

+#define SPI_IER_TIFREIE_Msk         (0x1UL << SPI_IER_TIFREIE_Pos)             /*!< 0x00000100 */

+#define SPI_IER_TIFREIE             SPI_IER_TIFREIE_Msk                        /*!<TI Frame Error interrupt enable */

+#define SPI_IER_MODFIE_Pos          (9U)

+#define SPI_IER_MODFIE_Msk          (0x1UL << SPI_IER_MODFIE_Pos)              /*!< 0x00000200 */

+#define SPI_IER_MODFIE              SPI_IER_MODFIE_Msk                         /*!<MODF interrupt enable           */

+#define SPI_IER_TSERFIE_Pos         (10U)

+#define SPI_IER_TSERFIE_Msk         (0x1UL << SPI_IER_TSERFIE_Pos)              /*!< 0x00000400 */

+#define SPI_IER_TSERFIE             SPI_IER_TSERFIE_Msk                        /*!<TSERF interrupt enable          */

+

+/*******************  Bit definition for SPI_SR register  ********************/

+#define SPI_SR_RXP_Pos              (0U)

+#define SPI_SR_RXP_Msk              (0x1UL << SPI_SR_RXP_Pos)                  /*!< 0x00000001 */

+#define SPI_SR_RXP                  SPI_SR_RXP_Msk                             /*!<Rx-Packet available             */

+#define SPI_SR_TXP_Pos              (1U)

+#define SPI_SR_TXP_Msk              (0x1UL << SPI_SR_TXP_Pos)                  /*!< 0x00000002 */

+#define SPI_SR_TXP                  SPI_SR_TXP_Msk                             /*!<Tx-Packet space available       */

+#define SPI_SR_DXP_Pos              (2U)

+#define SPI_SR_DXP_Msk              (0x1UL << SPI_SR_DXP_Pos)                  /*!< 0x00000004 */

+#define SPI_SR_DXP                  SPI_SR_DXP_Msk                             /*!<Duplex Packet available         */

+#define SPI_SR_EOT_Pos              (3U)

+#define SPI_SR_EOT_Msk              (0x1UL << SPI_SR_EOT_Pos)                  /*!< 0x00000008 */

+#define SPI_SR_EOT                  SPI_SR_EOT_Msk                             /*!<Duplex Packet available         */

+#define SPI_SR_TXTF_Pos             (4U)

+#define SPI_SR_TXTF_Msk             (0x1UL << SPI_SR_TXTF_Pos)                 /*!< 0x00000010 */

+#define SPI_SR_TXTF                 SPI_SR_TXTF_Msk                            /*!<Transmission Transfer Filled    */

+#define SPI_SR_UDR_Pos              (5U)

+#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000020 */

+#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<UDR at Slave transmission       */

+#define SPI_SR_OVR_Pos              (6U)

+#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */

+#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Rx-Packet available             */

+#define SPI_SR_CRCE_Pos             (7U)

+#define SPI_SR_CRCE_Msk             (0x1UL << SPI_SR_CRCE_Pos)                 /*!< 0x00000080 */

+#define SPI_SR_CRCE                 SPI_SR_CRCE_Msk                            /*!<CRC Error Detected              */

+#define SPI_SR_TIFRE_Pos            (8U)

+#define SPI_SR_TIFRE_Msk            (0x1UL << SPI_SR_TIFRE_Pos)                /*!< 0x00000100 */

+#define SPI_SR_TIFRE                SPI_SR_TIFRE_Msk                           /*!<TI frame format error Detected  */

+#define SPI_SR_MODF_Pos             (9U)

+#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000200 */

+#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode Fault Detected             */

+#define SPI_SR_TSERF_Pos            (10U)

+#define SPI_SR_TSERF_Msk            (0x1UL << SPI_SR_TSERF_Pos)                /*!< 0x00000400 */

+#define SPI_SR_TSERF                SPI_SR_TSERF_Msk                           /*!<Number of SPI data to be transacted reloaded     */

+#define SPI_SR_SUSP_Pos             (11U)

+#define SPI_SR_SUSP_Msk             (0x1UL << SPI_SR_SUSP_Pos)                 /*!< 0x00000800 */

+#define SPI_SR_SUSP                 SPI_SR_SUSP_Msk                            /*!<SUSP is set by hardware  */

+#define SPI_SR_TXC_Pos              (12U)

+#define SPI_SR_TXC_Msk              (0x1UL << SPI_SR_TXC_Pos)                  /*!< 0x00001000 */

+#define SPI_SR_TXC                  SPI_SR_TXC_Msk                             /*!<TxFIFO transmission complete */

+#define SPI_SR_RXPLVL_Pos           (13U)

+#define SPI_SR_RXPLVL_Msk           (0x3UL << SPI_SR_RXPLVL_Pos)               /*!< 0x00006000 */

+#define SPI_SR_RXPLVL               SPI_SR_RXPLVL_Msk                          /*!<RxFIFO Packing Level                             */

+#define SPI_SR_RXPLVL_0             (0x1UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00002000 */

+#define SPI_SR_RXPLVL_1             (0x2UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00004000 */

+#define SPI_SR_RXWNE_Pos            (15U)

+#define SPI_SR_RXWNE_Msk            (0x1UL << SPI_SR_RXWNE_Pos)                /*!< 0x00008000 */

+#define SPI_SR_RXWNE                SPI_SR_RXWNE_Msk                           /*!<Rx FIFO Word Not Empty                           */

+#define SPI_SR_CTSIZE_Pos           (16U)

+#define SPI_SR_CTSIZE_Msk           (0xFFFFUL << SPI_SR_CTSIZE_Pos)            /*!< 0xFFFF0000 */

+#define SPI_SR_CTSIZE               SPI_SR_CTSIZE_Msk                          /*!<Number of data frames remaining in TSIZE         */

+

+/*******************  Bit definition for SPI_IFCR register  ********************/

+#define SPI_IFCR_EOTC_Pos           (3U)

+#define SPI_IFCR_EOTC_Msk           (0x1UL << SPI_IFCR_EOTC_Pos)               /*!< 0x00000008 */

+#define SPI_IFCR_EOTC               SPI_IFCR_EOTC_Msk                          /*!<End Of Transfer flag clear              */

+#define SPI_IFCR_TXTFC_Pos          (4U)

+#define SPI_IFCR_TXTFC_Msk          (0x1UL << SPI_IFCR_TXTFC_Pos)              /*!< 0x00000010 */

+#define SPI_IFCR_TXTFC              SPI_IFCR_TXTFC_Msk                         /*!<Transmission Transfer Filled flag clear */

+#define SPI_IFCR_UDRC_Pos           (5U)

+#define SPI_IFCR_UDRC_Msk           (0x1UL << SPI_IFCR_UDRC_Pos)               /*!< 0x00000020 */

+#define SPI_IFCR_UDRC               SPI_IFCR_UDRC_Msk                          /*!<Underrun flag clear                     */

+#define SPI_IFCR_OVRC_Pos           (6U)

+#define SPI_IFCR_OVRC_Msk           (0x1UL << SPI_IFCR_OVRC_Pos)               /*!< 0x00000040 */

+#define SPI_IFCR_OVRC               SPI_IFCR_OVRC_Msk                          /*!<Overrun flag clear                      */

+#define SPI_IFCR_CRCEC_Pos          (7U)

+#define SPI_IFCR_CRCEC_Msk          (0x1UL << SPI_IFCR_CRCEC_Pos)              /*!< 0x00000080 */

+#define SPI_IFCR_CRCEC              SPI_IFCR_CRCEC_Msk                         /*!<CRC Error flag clear                    */

+#define SPI_IFCR_TIFREC_Pos         (8U)

+#define SPI_IFCR_TIFREC_Msk         (0x1UL << SPI_IFCR_TIFREC_Pos)             /*!< 0x00000100 */

+#define SPI_IFCR_TIFREC             SPI_IFCR_TIFREC_Msk                        /*!<TI frame format error flag clear        */

+#define SPI_IFCR_MODFC_Pos          (9U)

+#define SPI_IFCR_MODFC_Msk          (0x1UL << SPI_IFCR_MODFC_Pos)              /*!< 0x00000200 */

+#define SPI_IFCR_MODFC              SPI_IFCR_MODFC_Msk                         /*!<Mode Fault flag clear                   */

+#define SPI_IFCR_TSERFC_Pos         (10U)

+#define SPI_IFCR_TSERFC_Msk         (0x1UL << SPI_IFCR_TSERFC_Pos)             /*!< 0x00000400 */

+#define SPI_IFCR_TSERFC             SPI_IFCR_TSERFC_Msk                        /*!<TSERFC flag clear                       */

+#define SPI_IFCR_SUSPC_Pos          (11U)

+#define SPI_IFCR_SUSPC_Msk          (0x1UL << SPI_IFCR_SUSPC_Pos)              /*!< 0x00000800 */

+#define SPI_IFCR_SUSPC              SPI_IFCR_SUSPC_Msk                         /*!<SUSPend flag clear                      */

+

+/*******************  Bit definition for SPI_TXDR register  ********************/

+#define SPI_TXDR_TXDR_Pos           (0U)

+#define SPI_TXDR_TXDR_Msk           (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)        /*!< 0xFFFFFFFF */

+#define SPI_TXDR_TXDR               SPI_TXDR_TXDR_Msk                          /* Transmit Data Register */

+

+/*******************  Bit definition for SPI_RXDR register  ********************/

+#define SPI_RXDR_RXDR_Pos           (0U)

+#define SPI_RXDR_RXDR_Msk           (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)        /*!< 0xFFFFFFFF */

+#define SPI_RXDR_RXDR               SPI_RXDR_RXDR_Msk                          /* Receive Data Register  */

+

+/*******************  Bit definition for SPI_CRCPOLY register  ********************/

+#define SPI_CRCPOLY_CRCPOLY_Pos     (0U)

+#define SPI_CRCPOLY_CRCPOLY_Msk     (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)  /*!< 0xFFFFFFFF */

+#define SPI_CRCPOLY_CRCPOLY         SPI_CRCPOLY_CRCPOLY_Msk                    /* CRC Polynomial register  */

+

+/*******************  Bit definition for SPI_TXCRC register  ********************/

+#define SPI_TXCRC_TXCRC_Pos         (0U)

+#define SPI_TXCRC_TXCRC_Msk         (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_TXCRC_TXCRC             SPI_TXCRC_TXCRC_Msk                        /* CRCRegister for transmitter */

+

+/*******************  Bit definition for SPI_RXCRC register  ********************/

+#define SPI_RXCRC_RXCRC_Pos         (0U)

+#define SPI_RXCRC_RXCRC_Msk         (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_RXCRC_RXCRC             SPI_RXCRC_RXCRC_Msk                        /* CRCRegister for receiver */

+

+/*******************  Bit definition for SPI_UDRDR register  ********************/

+#define SPI_UDRDR_UDRDR_Pos         (0U)

+#define SPI_UDRDR_UDRDR_Msk         (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_UDRDR_UDRDR             SPI_UDRDR_UDRDR_Msk                        /* Data at slave underrun condition */

+

+/******************  Bit definition for SPI_I2SCFGR register  *****************/

+#define SPI_I2SCFGR_I2SMOD_Pos      (0U)

+#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000001 */

+#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */

+#define SPI_I2SCFGR_I2SCFG_Pos      (1U)

+#define SPI_I2SCFGR_I2SCFG_Msk      (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x0000000E */

+#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[2:0] I2S configuration mode                */

+#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000002 */

+#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000004 */

+#define SPI_I2SCFGR_I2SCFG_2        (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000008 */

+#define SPI_I2SCFGR_I2SSTD_Pos      (4U)

+#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */

+#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] I2S standard selection                */

+#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */

+#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */

+#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)

+#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */

+#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                         */

+#define SPI_I2SCFGR_DATLEN_Pos      (8U)

+#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000300 */

+#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] Data length to be transferred         */

+#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000100 */

+#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000200 */

+#define SPI_I2SCFGR_CHLEN_Pos       (10U)

+#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000400 */

+#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */

+#define SPI_I2SCFGR_CKPOL_Pos       (11U)

+#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000800 */

+#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<Steady state clock polarity                       */

+#define SPI_I2SCFGR_FIXCH_Pos       (12U)

+#define SPI_I2SCFGR_FIXCH_Msk       (0x1UL << SPI_I2SCFGR_FIXCH_Pos)           /*!< 0x00001000 */

+#define SPI_I2SCFGR_FIXCH           SPI_I2SCFGR_FIXCH_Msk                      /*!<Fixed channel length in SLAVE                     */

+#define SPI_I2SCFGR_WSINV_Pos       (13U)

+#define SPI_I2SCFGR_WSINV_Msk       (0x1UL << SPI_I2SCFGR_WSINV_Pos)           /*!< 0x00002000 */

+#define SPI_I2SCFGR_WSINV           SPI_I2SCFGR_WSINV_Msk                      /*!<Word select inversion                             */

+#define SPI_I2SCFGR_DATFMT_Pos      (14U)

+#define SPI_I2SCFGR_DATFMT_Msk      (0x1UL << SPI_I2SCFGR_DATFMT_Pos)          /*!< 0x00004000 */

+#define SPI_I2SCFGR_DATFMT          SPI_I2SCFGR_DATFMT_Msk                     /*!<Data format                                       */

+#define SPI_I2SCFGR_I2SDIV_Pos      (16U)

+#define SPI_I2SCFGR_I2SDIV_Msk      (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)         /*!< 0x00FF0000 */

+#define SPI_I2SCFGR_I2SDIV          SPI_I2SCFGR_I2SDIV_Msk                     /*!<I2S Linear prescaler */

+#define SPI_I2SCFGR_ODD_Pos         (24U)

+#define SPI_I2SCFGR_ODD_Msk         (0x1UL << SPI_I2SCFGR_ODD_Pos)             /*!< 0x01000000 */

+#define SPI_I2SCFGR_ODD             SPI_I2SCFGR_ODD_Msk                        /*!<Odd factor for the prescaler */

+#define SPI_I2SCFGR_MCKOE_Pos       (25U)

+#define SPI_I2SCFGR_MCKOE_Msk       (0x1UL << SPI_I2SCFGR_MCKOE_Pos)           /*!< 0x02000000 */

+#define SPI_I2SCFGR_MCKOE           SPI_I2SCFGR_MCKOE_Msk                      /*!<Master Clock Output Enable */

+

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                 SYSCFG                                     */

+/*                                                                            */

+/******************************************************************************/

+

+/******************  Bit definition for SYSCFG_PMCR register  ******************/

+#define SYSCFG_PMCR_I2C1_FMP_Pos        (0U)

+#define SYSCFG_PMCR_I2C1_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos)    /*!< 0x00000001 */

+#define SYSCFG_PMCR_I2C1_FMP            SYSCFG_PMCR_I2C1_FMP_Msk               /*!< I2C1 Fast mode plus */

+#define SYSCFG_PMCR_I2C2_FMP_Pos        (1U)

+#define SYSCFG_PMCR_I2C2_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos)    /*!< 0x00000002 */

+#define SYSCFG_PMCR_I2C2_FMP            SYSCFG_PMCR_I2C2_FMP_Msk               /*!< I2C2 Fast mode plus */

+#define SYSCFG_PMCR_I2C3_FMP_Pos        (2U)

+#define SYSCFG_PMCR_I2C3_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos)    /*!< 0x00000004 */

+#define SYSCFG_PMCR_I2C3_FMP            SYSCFG_PMCR_I2C3_FMP_Msk               /*!< I2C3 Fast mode plus */

+#define SYSCFG_PMCR_I2C4_FMP_Pos        (3U)

+#define SYSCFG_PMCR_I2C4_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos)    /*!< 0x00000008 */

+#define SYSCFG_PMCR_I2C4_FMP            SYSCFG_PMCR_I2C4_FMP_Msk               /*!< I2C4 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB6_FMP_Pos     (4U)

+#define SYSCFG_PMCR_I2C_PB6_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */

+#define SYSCFG_PMCR_I2C_PB6_FMP         SYSCFG_PMCR_I2C_PB6_FMP_Msk            /*!< I2C PB6 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB7_FMP_Pos     (5U)

+#define SYSCFG_PMCR_I2C_PB7_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */

+#define SYSCFG_PMCR_I2C_PB7_FMP         SYSCFG_PMCR_I2C_PB7_FMP_Msk            /*!< I2C PB7 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB8_FMP_Pos     (6U)

+#define SYSCFG_PMCR_I2C_PB8_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */

+#define SYSCFG_PMCR_I2C_PB8_FMP         SYSCFG_PMCR_I2C_PB8_FMP_Msk            /*!< I2C PB8 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB9_FMP_Pos     (7U)

+#define SYSCFG_PMCR_I2C_PB9_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */

+#define SYSCFG_PMCR_I2C_PB9_FMP         SYSCFG_PMCR_I2C_PB9_FMP_Msk            /*!< I2C PB9 Fast mode plus */

+#define SYSCFG_PMCR_PA0SO_Pos           (24U)

+#define SYSCFG_PMCR_PA0SO_Msk           (0x1UL << SYSCFG_PMCR_PA0SO_Pos)       /*!< 0x01000000 */

+#define SYSCFG_PMCR_PA0SO               SYSCFG_PMCR_PA0SO_Msk                  /*!< PA0 Switch Open */

+#define SYSCFG_PMCR_PA1SO_Pos           (25U)

+#define SYSCFG_PMCR_PA1SO_Msk           (0x1UL << SYSCFG_PMCR_PA1SO_Pos)       /*!< 0x02000000 */

+#define SYSCFG_PMCR_PA1SO               SYSCFG_PMCR_PA1SO_Msk                  /*!< PA1 Switch Open */

+#define SYSCFG_PMCR_PC2SO_Pos           (26U)

+#define SYSCFG_PMCR_PC2SO_Msk           (0x1UL << SYSCFG_PMCR_PC2SO_Pos)       /*!< 0x04000000 */

+#define SYSCFG_PMCR_PC2SO               SYSCFG_PMCR_PC2SO_Msk                  /*!< PC2 Switch Open */

+#define SYSCFG_PMCR_PC3SO_Pos           (27U)

+#define SYSCFG_PMCR_PC3SO_Msk           (0x1UL << SYSCFG_PMCR_PC3SO_Pos)       /*!< 0x08000000 */

+#define SYSCFG_PMCR_PC3SO               SYSCFG_PMCR_PC3SO_Msk                  /*!< PC3 Switch Open */

+

+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/

+#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)

+#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */

+#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)

+#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */

+#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)

+#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000F00 */

+#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */

+#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)

+#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x0000F000 */

+#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */

+/**

+  * @brief   EXTI0 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */

+

+/**

+  * @brief   EXTI1 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */

+/**

+  * @brief   EXTI2 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */

+

+/**

+  * @brief   EXTI3 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/

+#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)

+#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */

+#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)

+#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */

+#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)

+#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000F00 */

+#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */

+#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)

+#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x0000F000 */

+#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */

+/**

+  * @brief   EXTI4 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */

+/**

+  * @brief   EXTI5 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */

+/**

+  * @brief   EXTI6 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */

+

+/**

+  * @brief   EXTI7 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/

+#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)

+#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */

+#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)

+#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */

+#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)

+#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000F00 */

+#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */

+#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)

+#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x0000F000 */

+#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */

+

+/**

+  * @brief   EXTI8 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */

+

+/**

+  * @brief   EXTI9 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */

+

+/**

+  * @brief   EXTI10 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */

+

+/**

+  * @brief   EXTI11 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/

+#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)

+#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x0000000F */

+#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */

+#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)

+#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x000000F0 */

+#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */

+#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)

+#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000F00 */

+#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */

+#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)

+#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x0000F000 */

+#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */

+/**

+  * @brief   EXTI12 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */

+/**

+  * @brief   EXTI13 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */

+/**

+  * @brief   EXTI14 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */

+/**

+  * @brief   EXTI15 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */

+

+/******************  Bit definition for SYSCFG_CFGR register  ******************/

+#define SYSCFG_CFGR_PVDL_Pos            (2U)

+#define SYSCFG_CFGR_PVDL_Msk            (0x1UL << SYSCFG_CFGR_PVDL_Pos)        /*!< 0x00000004 */

+#define SYSCFG_CFGR_PVDL                SYSCFG_CFGR_PVDL_Msk                   /*!<PVD lock enable bit */

+#define SYSCFG_CFGR_FLASHL_Pos          (3U)

+#define SYSCFG_CFGR_FLASHL_Msk          (0x1UL << SYSCFG_CFGR_FLASHL_Pos)      /*!< 0x00000008 */

+#define SYSCFG_CFGR_FLASHL              SYSCFG_CFGR_FLASHL_Msk                 /*!<FLASH double ECC error lock bit */

+#define SYSCFG_CFGR_CM7L_Pos            (6U)

+#define SYSCFG_CFGR_CM7L_Msk            (0x1UL << SYSCFG_CFGR_CM7L_Pos)        /*!< 0x00000040 */

+#define SYSCFG_CFGR_CM7L                SYSCFG_CFGR_CM7L_Msk                   /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */

+#define SYSCFG_CFGR_DTCML_Pos           (13U)

+#define SYSCFG_CFGR_DTCML_Msk           (0x1UL << SYSCFG_CFGR_DTCML_Pos)       /*!< 0x00002000 */

+#define SYSCFG_CFGR_DTCML               SYSCFG_CFGR_DTCML_Msk                  /*!<DTCM double ECC error lock bit */

+#define SYSCFG_CFGR_ITCML_Pos           (14U)

+#define SYSCFG_CFGR_ITCML_Msk           (0x1UL << SYSCFG_CFGR_ITCML_Pos)       /*!< 0x00004000 */

+#define SYSCFG_CFGR_ITCML               SYSCFG_CFGR_ITCML_Msk                  /*!<ITCM double ECC error lock bit */

+/******************  Bit definition for SYSCFG_CCCSR register  ******************/

+#define SYSCFG_CCCSR_EN_Pos             (0U)

+#define SYSCFG_CCCSR_EN_Msk             (0x1UL << SYSCFG_CCCSR_EN_Pos)         /*!< 0x00000001 */

+#define SYSCFG_CCCSR_EN                 SYSCFG_CCCSR_EN_Msk                    /*!< I/O compensation cell enable */

+#define SYSCFG_CCCSR_CS_Pos             (1U)

+#define SYSCFG_CCCSR_CS_Msk             (0x1UL << SYSCFG_CCCSR_CS_Pos)         /*!< 0x00000002 */

+#define SYSCFG_CCCSR_CS                 SYSCFG_CCCSR_CS_Msk                    /*!< I/O compensation cell code selection */

+#define SYSCFG_CCCSR_CS_MMC_Pos         (3U)

+#define SYSCFG_CCCSR_CS_MMC_Msk         (0x1UL << SYSCFG_CCCSR_CS_MMC_Pos)         /*!< 0x00000004 */

+#define SYSCFG_CCCSR_CS_MMC             SYSCFG_CCCSR_CS_MMC_Msk                    /*!< I/O compensation cell code selection */

+#define SYSCFG_CCCSR_READY_Pos          (8U)

+#define SYSCFG_CCCSR_READY_Msk          (0x1UL << SYSCFG_CCCSR_READY_Pos)      /*!< 0x00000100 */

+#define SYSCFG_CCCSR_READY              SYSCFG_CCCSR_READY_Msk                 /*!< I/O compensation cell ready flag */

+#define SYSCFG_CCCSR_HSLV0_Pos           (16U)

+#define SYSCFG_CCCSR_HSLV0_Msk           (0x1UL << SYSCFG_CCCSR_HSLV0_Pos)       /*!< 0x00010000 */

+#define SYSCFG_CCCSR_HSLV0               SYSCFG_CCCSR_HSLV0_Msk                  /*!< High-speed at low-voltage */

+#define SYSCFG_CCCSR_HSLV1_Pos           (17U)

+#define SYSCFG_CCCSR_HSLV1_Msk           (0x1UL << SYSCFG_CCCSR_HSLV1_Pos)       /*!< 0x00020000 */

+#define SYSCFG_CCCSR_HSLV1               SYSCFG_CCCSR_HSLV1_Msk                  /*!< High-speed at low-voltage */

+#define SYSCFG_CCCSR_HSLV2_Pos           (18U)

+#define SYSCFG_CCCSR_HSLV2_Msk           (0x1UL << SYSCFG_CCCSR_HSLV2_Pos)       /*!< 0x00040000 */

+#define SYSCFG_CCCSR_HSLV2               SYSCFG_CCCSR_HSLV2_Msk                  /*!< High-speed at low-voltage */

+#define SYSCFG_CCCSR_HSLV3_Pos           (19U)

+#define SYSCFG_CCCSR_HSLV3_Msk           (0x1UL << SYSCFG_CCCSR_HSLV3_Pos)       /*!< 0x00080000 */

+#define SYSCFG_CCCSR_HSLV3               SYSCFG_CCCSR_HSLV3_Msk                  /*!< High-speed at low-voltage */

+/******************  Bit definition for SYSCFG_CCVR register  *******************/

+#define SYSCFG_CCVR_NCV_Pos             (0U)

+#define SYSCFG_CCVR_NCV_Msk             (0xFUL << SYSCFG_CCVR_NCV_Pos)         /*!< 0x0000000F */

+#define SYSCFG_CCVR_NCV                 SYSCFG_CCVR_NCV_Msk                    /*!< NMOS compensation value */

+#define SYSCFG_CCVR_PCV_Pos             (4U)

+#define SYSCFG_CCVR_PCV_Msk             (0xFUL << SYSCFG_CCVR_PCV_Pos)         /*!< 0x000000F0 */

+#define SYSCFG_CCVR_PCV                 SYSCFG_CCVR_PCV_Msk                    /*!< PMOS compensation value */

+

+/******************  Bit definition for SYSCFG_CCCR register  *******************/

+#define SYSCFG_CCCR_NCC_Pos             (0U)

+#define SYSCFG_CCCR_NCC_Msk             (0xFUL << SYSCFG_CCCR_NCC_Pos)         /*!< 0x0000000F */

+#define SYSCFG_CCCR_NCC                 SYSCFG_CCCR_NCC_Msk                    /*!< NMOS compensation code */

+#define SYSCFG_CCCR_PCC_Pos             (4U)

+#define SYSCFG_CCCR_PCC_Msk             (0xFUL << SYSCFG_CCCR_PCC_Pos)         /*!< 0x000000F0 */

+#define SYSCFG_CCCR_PCC                 SYSCFG_CCCR_PCC_Msk                    /*!< PMOS compensation code */

+#define SYSCFG_CCCR_NCC_MMC_Pos         (8U)

+#define SYSCFG_CCCR_NCC_MMC_Msk         (0xFUL << SYSCFG_CCCR_NCC_MMC_Pos)     /*!< 0x00000F00 */

+#define SYSCFG_CCCR_NCC_MMC             SYSCFG_CCCR_NCC_MMC_Msk                /*!< NMOS compensation code */

+#define SYSCFG_CCCR_PCC_MMC_Pos         (12U)

+#define SYSCFG_CCCR_PCC_MMC_Msk         (0xFUL << SYSCFG_CCCR_PCC_MMC_Pos)     /*!< 0x0000F000 */

+#define SYSCFG_CCCR_PCC_MMC             SYSCFG_CCCR_PCC_MMC_Msk                /*!< PMOS compensation code */

+/******************************************************************************/

+/*                                                                            */

+/*                    Digital Temperature Sensor (DTS)                        */

+/*                                                                            */

+/******************************************************************************/

+

+/******************  Bit definition for DTS_CFGR1 register  ******************/

+#define DTS_CFGR1_TS1_EN_Pos               (0U)

+#define DTS_CFGR1_TS1_EN_Msk               (0x1UL << DTS_CFGR1_TS1_EN_Pos) /*!< 0x00000001 */

+#define DTS_CFGR1_TS1_EN                   DTS_CFGR1_TS1_EN_Msk        /*!< DTS Enable */

+#define DTS_CFGR1_TS1_START_Pos            (4U)

+#define DTS_CFGR1_TS1_START_Msk            (0x1UL << DTS_CFGR1_TS1_START_Pos) /*!< 0x00000010 */

+#define DTS_CFGR1_TS1_START                DTS_CFGR1_TS1_START_Msk     /*!< Proceed to a frequency measurement on DTS */

+#define DTS_CFGR1_TS1_INTRIG_SEL_Pos       (8U)

+#define DTS_CFGR1_TS1_INTRIG_SEL_Msk       (0xFUL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000F00 */

+#define DTS_CFGR1_TS1_INTRIG_SEL           DTS_CFGR1_TS1_INTRIG_SEL_Msk /*!< Input triggers selection bits [3:0] for DTS */

+#define DTS_CFGR1_TS1_INTRIG_SEL_0         (0x1UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000100 */

+#define DTS_CFGR1_TS1_INTRIG_SEL_1         (0x2UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000200 */

+#define DTS_CFGR1_TS1_INTRIG_SEL_2         (0x4UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000400 */

+#define DTS_CFGR1_TS1_INTRIG_SEL_3         (0x8UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000800 */

+#define DTS_CFGR1_TS1_SMP_TIME_Pos         (16U)

+#define DTS_CFGR1_TS1_SMP_TIME_Msk         (0xFUL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x000F0000 */

+#define DTS_CFGR1_TS1_SMP_TIME             DTS_CFGR1_TS1_SMP_TIME_Msk  /*!< Sample time [3:0] for DTS */

+#define DTS_CFGR1_TS1_SMP_TIME_0           (0x1UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00010000 */

+#define DTS_CFGR1_TS1_SMP_TIME_1           (0x2UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00020000 */

+#define DTS_CFGR1_TS1_SMP_TIME_2           (0x4UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00040000 */

+#define DTS_CFGR1_TS1_SMP_TIME_3           (0x8UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00080000 */

+#define DTS_CFGR1_REFCLK_SEL_Pos           (20U)

+#define DTS_CFGR1_REFCLK_SEL_Msk           (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */

+#define DTS_CFGR1_REFCLK_SEL               DTS_CFGR1_REFCLK_SEL_Msk    /*!< Reference Clock Selection */

+#define DTS_CFGR1_Q_MEAS_OPT_Pos           (21U)

+#define DTS_CFGR1_Q_MEAS_OPT_Msk           (0x1UL << DTS_CFGR1_Q_MEAS_OPT_Pos) /*!< 0x00200000 */

+#define DTS_CFGR1_Q_MEAS_OPT               DTS_CFGR1_Q_MEAS_OPT_Msk    /*!< Quick measure option bit  */

+#define DTS_CFGR1_HSREF_CLK_DIV_Pos        (24U)

+#define DTS_CFGR1_HSREF_CLK_DIV_Msk        (0x7FUL << DTS_CFGR1_HSREF_CLK_DIV_Pos) /*!< 0x7F000000 */

+#define DTS_CFGR1_HSREF_CLK_DIV            DTS_CFGR1_HSREF_CLK_DIV_Msk /*!< High Speed Clock Divider Ratio [6:0]*/

+

+/******************  Bit definition for DTS_T0VALR1 register  ******************/

+#define DTS_T0VALR1_TS1_FMT0_Pos           (0U)

+#define DTS_T0VALR1_TS1_FMT0_Msk           (0xFFFFUL << DTS_T0VALR1_TS1_FMT0_Pos) /*!< 0x0000FFFF */

+#define DTS_T0VALR1_TS1_FMT0               DTS_T0VALR1_TS1_FMT0_Msk    /*!< Engineering value of the measured frequency at T0 for DTS */

+#define DTS_T0VALR1_TS1_T0_Pos             (16U)

+#define DTS_T0VALR1_TS1_T0_Msk             (0x3UL << DTS_T0VALR1_TS1_T0_Pos) /*!< 0x00030000 */

+#define DTS_T0VALR1_TS1_T0                 DTS_T0VALR1_TS1_T0_Msk      /*!< Engineering value of the DTSerature T0 for DTS */

+

+/******************  Bit definition for DTS_RAMPVALR register  ******************/

+#define DTS_RAMPVALR_TS1_RAMP_COEFF_Pos    (0U)

+#define DTS_RAMPVALR_TS1_RAMP_COEFF_Msk    (0xFFFFUL << DTS_RAMPVALR_TS1_RAMP_COEFF_Pos) /*!< 0x0000FFFF */

+#define DTS_RAMPVALR_TS1_RAMP_COEFF        DTS_RAMPVALR_TS1_RAMP_COEFF_Msk /*!< Engineering value of the ramp coefficient for DTS */

+

+/******************  Bit definition for DTS_ITR1 register      ******************/

+#define DTS_ITR1_TS1_LITTHD_Pos            (0U)

+#define DTS_ITR1_TS1_LITTHD_Msk            (0xFFFFUL << DTS_ITR1_TS1_LITTHD_Pos) /*!< 0x0000FFFF */

+#define DTS_ITR1_TS1_LITTHD                DTS_ITR1_TS1_LITTHD_Msk     /*!< Low interrupt threshold[15:0] for DTS */

+#define DTS_ITR1_TS1_HITTHD_Pos            (16U)

+#define DTS_ITR1_TS1_HITTHD_Msk            (0xFFFFUL << DTS_ITR1_TS1_HITTHD_Pos) /*!< 0xFFFF0000 */

+#define DTS_ITR1_TS1_HITTHD                DTS_ITR1_TS1_HITTHD_Msk     /*!< High interrupt threshold[15:0] for DTS */

+

+/******************  Bit definition for DTS_DR register        ******************/

+#define DTS_DR_TS1_MFREQ_Pos               (0U)

+#define DTS_DR_TS1_MFREQ_Msk               (0xFFFFUL << DTS_DR_TS1_MFREQ_Pos) /*!< 0x0000FFFF */

+#define DTS_DR_TS1_MFREQ                   DTS_DR_TS1_MFREQ_Msk        /*!< Measured Frequency[15:0] for DTS */

+

+/******************  Bit definition for DTS_SR register        ******************/

+#define DTS_SR_TS1_ITEF_Pos                (0U)

+#define DTS_SR_TS1_ITEF_Msk                (0x1UL << DTS_SR_TS1_ITEF_Pos) /*!< 0x00000001 */

+#define DTS_SR_TS1_ITEF                    DTS_SR_TS1_ITEF_Msk         /*!< Interrupt flag for end of measure for DTS */

+#define DTS_SR_TS1_ITLF_Pos                (1U)

+#define DTS_SR_TS1_ITLF_Msk                (0x1UL << DTS_SR_TS1_ITLF_Pos) /*!< 0x00000002 */

+#define DTS_SR_TS1_ITLF                    DTS_SR_TS1_ITLF_Msk         /*!< Interrupt flag for low threshold for DTS  */

+#define DTS_SR_TS1_ITHF_Pos                (2U)

+#define DTS_SR_TS1_ITHF_Msk                (0x1UL << DTS_SR_TS1_ITHF_Pos) /*!< 0x00000004 */

+#define DTS_SR_TS1_ITHF                    DTS_SR_TS1_ITHF_Msk         /*!< Interrupt flag for high threshold for DTS */

+#define DTS_SR_TS1_AITEF_Pos               (4U)

+#define DTS_SR_TS1_AITEF_Msk               (0x1UL << DTS_SR_TS1_AITEF_Pos) /*!< 0x00000010 */

+#define DTS_SR_TS1_AITEF                   DTS_SR_TS1_AITEF_Msk        /*!< Asynchronous interrupt flag for end of measure for DTS */

+#define DTS_SR_TS1_AITLF_Pos               (5U)

+#define DTS_SR_TS1_AITLF_Msk               (0x1UL << DTS_SR_TS1_AITLF_Pos) /*!< 0x00000020 */

+#define DTS_SR_TS1_AITLF                   DTS_SR_TS1_AITLF_Msk        /*!< Asynchronous interrupt flag for low threshold for DTS  */

+#define DTS_SR_TS1_AITHF_Pos               (6U)

+#define DTS_SR_TS1_AITHF_Msk               (0x1UL << DTS_SR_TS1_AITHF_Pos) /*!< 0x00000040 */

+#define DTS_SR_TS1_AITHF                   DTS_SR_TS1_AITHF_Msk        /*!< Asynchronous interrupt flag for high threshold for DTS */

+#define DTS_SR_TS1_RDY_Pos                 (15U)

+#define DTS_SR_TS1_RDY_Msk                 (0x1UL << DTS_SR_TS1_RDY_Pos) /*!< 0x00008000 */

+#define DTS_SR_TS1_RDY                     DTS_SR_TS1_RDY_Msk          /*!< DTS ready flag */

+

+/******************  Bit definition for DTS_ITENR register      ******************/

+#define DTS_ITENR_TS1_ITEEN_Pos            (0U)

+#define DTS_ITENR_TS1_ITEEN_Msk            (0x1UL << DTS_ITENR_TS1_ITEEN_Pos) /*!< 0x00000001 */

+#define DTS_ITENR_TS1_ITEEN                DTS_ITENR_TS1_ITEEN_Msk     /*!< Enable interrupt flag for end of measure for DTS */

+#define DTS_ITENR_TS1_ITLEN_Pos            (1U)

+#define DTS_ITENR_TS1_ITLEN_Msk            (0x1UL << DTS_ITENR_TS1_ITLEN_Pos) /*!< 0x00000002 */

+#define DTS_ITENR_TS1_ITLEN                DTS_ITENR_TS1_ITLEN_Msk     /*!< Enable interrupt flag for low threshold for DTS  */

+#define DTS_ITENR_TS1_ITHEN_Pos            (2U)

+#define DTS_ITENR_TS1_ITHEN_Msk            (0x1UL << DTS_ITENR_TS1_ITHEN_Pos) /*!< 0x00000004 */

+#define DTS_ITENR_TS1_ITHEN                DTS_ITENR_TS1_ITHEN_Msk     /*!< Enable interrupt flag for high threshold for DTS */

+#define DTS_ITENR_TS1_AITEEN_Pos           (4U)

+#define DTS_ITENR_TS1_AITEEN_Msk           (0x1UL << DTS_ITENR_TS1_AITEEN_Pos) /*!< 0x00000010 */

+#define DTS_ITENR_TS1_AITEEN               DTS_ITENR_TS1_AITEEN_Msk    /*!< Enable asynchronous interrupt flag for end of measure for DTS */

+#define DTS_ITENR_TS1_AITLEN_Pos           (5U)

+#define DTS_ITENR_TS1_AITLEN_Msk           (0x1UL << DTS_ITENR_TS1_AITLEN_Pos) /*!< 0x00000020 */

+#define DTS_ITENR_TS1_AITLEN               DTS_ITENR_TS1_AITLEN_Msk    /*!< Enable Asynchronous interrupt flag for low threshold for DTS  */

+#define DTS_ITENR_TS1_AITHEN_Pos           (6U)

+#define DTS_ITENR_TS1_AITHEN_Msk           (0x1UL << DTS_ITENR_TS1_AITHEN_Pos) /*!< 0x00000040 */

+#define DTS_ITENR_TS1_AITHEN               DTS_ITENR_TS1_AITHEN_Msk    /*!< Enable asynchronous interrupt flag for high threshold for DTS */

+

+/******************  Bit definition for DTS_ICIFR register      ******************/

+#define DTS_ICIFR_TS1_CITEF_Pos            (0U)

+#define DTS_ICIFR_TS1_CITEF_Msk            (0x1UL << DTS_ICIFR_TS1_CITEF_Pos) /*!< 0x00000001 */

+#define DTS_ICIFR_TS1_CITEF                DTS_ICIFR_TS1_CITEF_Msk     /*!< Clear the IT flag for End Of Measure for DTS */

+#define DTS_ICIFR_TS1_CITLF_Pos            (1U)

+#define DTS_ICIFR_TS1_CITLF_Msk            (0x1UL << DTS_ICIFR_TS1_CITLF_Pos) /*!< 0x00000002 */

+#define DTS_ICIFR_TS1_CITLF                DTS_ICIFR_TS1_CITLF_Msk     /*!< Clear the IT flag for low threshold for DTS  */

+#define DTS_ICIFR_TS1_CITHF_Pos            (2U)

+#define DTS_ICIFR_TS1_CITHF_Msk            (0x1UL << DTS_ICIFR_TS1_CITHF_Pos) /*!< 0x00000004 */

+#define DTS_ICIFR_TS1_CITHF                DTS_ICIFR_TS1_CITHF_Msk     /*!< Clear the IT flag for high threshold on DTS  */

+#define DTS_ICIFR_TS1_CAITEF_Pos           (4U)

+#define DTS_ICIFR_TS1_CAITEF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITEF_Pos) /*!< 0x00000010 */

+#define DTS_ICIFR_TS1_CAITEF               DTS_ICIFR_TS1_CAITEF_Msk    /*!< Clear the asynchronous IT flag for End Of Measure for DTS */

+#define DTS_ICIFR_TS1_CAITLF_Pos           (5U)

+#define DTS_ICIFR_TS1_CAITLF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITLF_Pos) /*!< 0x00000020 */

+#define DTS_ICIFR_TS1_CAITLF               DTS_ICIFR_TS1_CAITLF_Msk    /*!< Clear the asynchronous IT flag for low threshold for DTS  */

+#define DTS_ICIFR_TS1_CAITHF_Pos           (6U)

+#define DTS_ICIFR_TS1_CAITHF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITHF_Pos) /*!< 0x00000040 */

+#define DTS_ICIFR_TS1_CAITHF               DTS_ICIFR_TS1_CAITHF_Msk    /*!< Clear the asynchronous IT flag for high threshold on DTS  */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    TIM                                     */

+/*                                                                            */

+/******************************************************************************/

+#define TIM_BREAK_INPUT_SUPPORT             /*!<TIM Break input feature */

+

+/*******************  Bit definition for TIM_CR1 register  ********************/

+#define TIM_CR1_CEN_Pos           (0U)

+#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */

+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */

+#define TIM_CR1_UDIS_Pos          (1U)

+#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */

+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */

+#define TIM_CR1_URS_Pos           (2U)

+#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */

+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */

+#define TIM_CR1_OPM_Pos           (3U)

+#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */

+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */

+#define TIM_CR1_DIR_Pos           (4U)

+#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */

+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */

+

+#define TIM_CR1_CMS_Pos           (5U)

+#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */

+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */

+#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */

+#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */

+

+#define TIM_CR1_ARPE_Pos          (7U)

+#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */

+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */

+

+#define TIM_CR1_CKD_Pos           (8U)

+#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */

+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */

+#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */

+#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */

+

+#define TIM_CR1_UIFREMAP_Pos      (11U)

+#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */

+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */

+

+/*******************  Bit definition for TIM_CR2 register  ********************/

+#define TIM_CR2_CCPC_Pos          (0U)

+#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */

+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */

+#define TIM_CR2_CCUS_Pos          (2U)

+#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */

+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */

+#define TIM_CR2_CCDS_Pos          (3U)

+#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */

+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */

+

+#define TIM_CR2_MMS_Pos           (4U)

+#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */

+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */

+#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */

+#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */

+#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */

+

+#define TIM_CR2_TI1S_Pos          (7U)

+#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */

+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */

+#define TIM_CR2_OIS1_Pos          (8U)

+#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */

+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */

+#define TIM_CR2_OIS1N_Pos         (9U)

+#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */

+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */

+#define TIM_CR2_OIS2_Pos          (10U)

+#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */

+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */

+#define TIM_CR2_OIS2N_Pos         (11U)

+#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */

+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */

+#define TIM_CR2_OIS3_Pos          (12U)

+#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */

+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */

+#define TIM_CR2_OIS3N_Pos         (13U)

+#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */

+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */

+#define TIM_CR2_OIS4_Pos          (14U)

+#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */

+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */

+#define TIM_CR2_OIS5_Pos          (16U)

+#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */

+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */

+#define TIM_CR2_OIS6_Pos          (17U)

+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */

+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */

+

+#define TIM_CR2_MMS2_Pos          (20U)

+#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */

+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */

+#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */

+#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */

+#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */

+#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */

+

+/*******************  Bit definition for TIM_SMCR register  *******************/

+#define TIM_SMCR_SMS_Pos          (0U)

+#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */

+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */

+#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */

+#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */

+#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */

+#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */

+

+#define TIM_SMCR_TS_Pos           (4U)

+#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */

+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[4:0] bits (Trigger selection) */

+#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)                /*!< 0x00000010 */

+#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)                /*!< 0x00000020 */

+#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)                /*!< 0x00000040 */

+#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)                /*!< 0x00100000 */

+#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)                /*!< 0x00200000 */

+

+#define TIM_SMCR_MSM_Pos          (7U)

+#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */

+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */

+

+#define TIM_SMCR_ETF_Pos          (8U)

+#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */

+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */

+#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */

+#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */

+#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */

+#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */

+

+#define TIM_SMCR_ETPS_Pos         (12U)

+#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */

+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */

+#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */

+#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */

+

+#define TIM_SMCR_ECE_Pos          (14U)

+#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */

+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */

+#define TIM_SMCR_ETP_Pos          (15U)

+#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */

+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */

+

+/*******************  Bit definition for TIM_DIER register  *******************/

+#define TIM_DIER_UIE_Pos          (0U)

+#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */

+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */

+#define TIM_DIER_CC1IE_Pos        (1U)

+#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */

+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */

+#define TIM_DIER_CC2IE_Pos        (2U)

+#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */

+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */

+#define TIM_DIER_CC3IE_Pos        (3U)

+#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */

+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */

+#define TIM_DIER_CC4IE_Pos        (4U)

+#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */

+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */

+#define TIM_DIER_COMIE_Pos        (5U)

+#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */

+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */

+#define TIM_DIER_TIE_Pos          (6U)

+#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */

+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */

+#define TIM_DIER_BIE_Pos          (7U)

+#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */

+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */

+#define TIM_DIER_UDE_Pos          (8U)

+#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */

+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */

+#define TIM_DIER_CC1DE_Pos        (9U)

+#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */

+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */

+#define TIM_DIER_CC2DE_Pos        (10U)

+#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */

+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */

+#define TIM_DIER_CC3DE_Pos        (11U)

+#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */

+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */

+#define TIM_DIER_CC4DE_Pos        (12U)

+#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */

+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */

+#define TIM_DIER_COMDE_Pos        (13U)

+#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */

+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */

+#define TIM_DIER_TDE_Pos          (14U)

+#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */

+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */

+

+/********************  Bit definition for TIM_SR register  ********************/

+#define TIM_SR_UIF_Pos            (0U)

+#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */

+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */

+#define TIM_SR_CC1IF_Pos          (1U)

+#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */

+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */

+#define TIM_SR_CC2IF_Pos          (2U)

+#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */

+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */

+#define TIM_SR_CC3IF_Pos          (3U)

+#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */

+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */

+#define TIM_SR_CC4IF_Pos          (4U)

+#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */

+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */

+#define TIM_SR_COMIF_Pos          (5U)

+#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */

+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */

+#define TIM_SR_TIF_Pos            (6U)

+#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */

+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */

+#define TIM_SR_BIF_Pos            (7U)

+#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */

+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */

+#define TIM_SR_B2IF_Pos           (8U)

+#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */

+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break2 interrupt Flag */

+#define TIM_SR_CC1OF_Pos          (9U)

+#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */

+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */

+#define TIM_SR_CC2OF_Pos          (10U)

+#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */

+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */

+#define TIM_SR_CC3OF_Pos          (11U)

+#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */

+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */

+#define TIM_SR_CC4OF_Pos          (12U)

+#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */

+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */

+#define TIM_SR_CC5IF_Pos          (16U)

+#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */

+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */

+#define TIM_SR_CC6IF_Pos          (17U)

+#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */

+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */

+#define TIM_SR_SBIF_Pos           (13U)

+#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */

+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!< System Break Flag */

+

+/*******************  Bit definition for TIM_EGR register  ********************/

+#define TIM_EGR_UG_Pos            (0U)

+#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */

+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */

+#define TIM_EGR_CC1G_Pos          (1U)

+#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */

+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */

+#define TIM_EGR_CC2G_Pos          (2U)

+#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */

+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */

+#define TIM_EGR_CC3G_Pos          (3U)

+#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */

+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */

+#define TIM_EGR_CC4G_Pos          (4U)

+#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */

+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */

+#define TIM_EGR_COMG_Pos          (5U)

+#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */

+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */

+#define TIM_EGR_TG_Pos            (6U)

+#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */

+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */

+#define TIM_EGR_BG_Pos            (7U)

+#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */

+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */

+#define TIM_EGR_B2G_Pos           (8U)

+#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */

+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break Generation */

+

+

+/******************  Bit definition for TIM_CCMR1 register  *******************/

+#define TIM_CCMR1_CC1S_Pos        (0U)

+#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */

+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */

+#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */

+#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */

+

+#define TIM_CCMR1_OC1FE_Pos       (2U)

+#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */

+#define TIM_CCMR1_OC1PE_Pos       (3U)

+#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */

+

+#define TIM_CCMR1_OC1M_Pos        (4U)

+#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */

+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */

+#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */

+#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */

+#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */

+#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR1_OC1CE_Pos       (7U)

+#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */

+

+#define TIM_CCMR1_CC2S_Pos        (8U)

+#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */

+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */

+#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */

+#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */

+

+#define TIM_CCMR1_OC2FE_Pos       (10U)

+#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */

+#define TIM_CCMR1_OC2PE_Pos       (11U)

+#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */

+

+#define TIM_CCMR1_OC2M_Pos        (12U)

+#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */

+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */

+#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */

+#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */

+#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */

+#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */

+

+#define TIM_CCMR1_OC2CE_Pos       (15U)

+#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */

+

+/*----------------------------------------------------------------------------*/

+

+#define TIM_CCMR1_IC1PSC_Pos      (2U)

+#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */

+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */

+#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */

+

+#define TIM_CCMR1_IC1F_Pos        (4U)

+#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */

+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */

+#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */

+

+#define TIM_CCMR1_IC2PSC_Pos      (10U)

+#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */

+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */

+#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */

+

+#define TIM_CCMR1_IC2F_Pos        (12U)

+#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */

+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */

+#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */

+

+/******************  Bit definition for TIM_CCMR2 register  *******************/

+#define TIM_CCMR2_CC3S_Pos        (0U)

+#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */

+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */

+#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */

+#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */

+

+#define TIM_CCMR2_OC3FE_Pos       (2U)

+#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */

+#define TIM_CCMR2_OC3PE_Pos       (3U)

+#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */

+

+#define TIM_CCMR2_OC3M_Pos        (4U)

+#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */

+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */

+#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR2_OC3CE_Pos       (7U)

+#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */

+

+#define TIM_CCMR2_CC4S_Pos        (8U)

+#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */

+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */

+#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */

+#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */

+

+#define TIM_CCMR2_OC4FE_Pos       (10U)

+#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */

+#define TIM_CCMR2_OC4PE_Pos       (11U)

+#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */

+

+#define TIM_CCMR2_OC4M_Pos        (12U)

+#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */

+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */

+#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */

+

+#define TIM_CCMR2_OC4CE_Pos       (15U)

+#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */

+

+/*----------------------------------------------------------------------------*/

+

+#define TIM_CCMR2_IC3PSC_Pos      (2U)

+#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */

+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */

+#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */

+

+#define TIM_CCMR2_IC3F_Pos        (4U)

+#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */

+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */

+#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */

+

+#define TIM_CCMR2_IC4PSC_Pos      (10U)

+#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */

+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */

+#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */

+

+#define TIM_CCMR2_IC4F_Pos        (12U)

+#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */

+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */

+#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */

+

+/*******************  Bit definition for TIM_CCER register  *******************/

+#define TIM_CCER_CC1E_Pos         (0U)

+#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */

+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */

+#define TIM_CCER_CC1P_Pos         (1U)

+#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */

+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */

+#define TIM_CCER_CC1NE_Pos        (2U)

+#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */

+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */

+#define TIM_CCER_CC1NP_Pos        (3U)

+#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */

+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */

+#define TIM_CCER_CC2E_Pos         (4U)

+#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */

+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */

+#define TIM_CCER_CC2P_Pos         (5U)

+#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */

+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */

+#define TIM_CCER_CC2NE_Pos        (6U)

+#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */

+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */

+#define TIM_CCER_CC2NP_Pos        (7U)

+#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */

+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */

+#define TIM_CCER_CC3E_Pos         (8U)

+#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */

+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */

+#define TIM_CCER_CC3P_Pos         (9U)

+#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */

+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */

+#define TIM_CCER_CC3NE_Pos        (10U)

+#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */

+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */

+#define TIM_CCER_CC3NP_Pos        (11U)

+#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */

+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */

+#define TIM_CCER_CC4E_Pos         (12U)

+#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */

+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */

+#define TIM_CCER_CC4P_Pos         (13U)

+#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */

+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */

+#define TIM_CCER_CC4NP_Pos        (15U)

+#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */

+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */

+#define TIM_CCER_CC5E_Pos         (16U)

+#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */

+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */

+#define TIM_CCER_CC5P_Pos         (17U)

+#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */

+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */

+#define TIM_CCER_CC6E_Pos         (20U)

+#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */

+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */

+#define TIM_CCER_CC6P_Pos         (21U)

+#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */

+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */

+/*******************  Bit definition for TIM_CNT register  ********************/

+#define TIM_CNT_CNT_Pos           (0U)

+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */

+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */

+#define TIM_CNT_UIFCPY_Pos        (31U)

+#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */

+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy */

+/*******************  Bit definition for TIM_PSC register  ********************/

+#define TIM_PSC_PSC_Pos           (0U)

+#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */

+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */

+

+/*******************  Bit definition for TIM_ARR register  ********************/

+#define TIM_ARR_ARR_Pos           (0U)

+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */

+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */

+

+/*******************  Bit definition for TIM_RCR register  ********************/

+#define TIM_RCR_REP_Pos           (0U)

+#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                  /*!< 0x000000FF */

+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */

+

+/*******************  Bit definition for TIM_CCR1 register  *******************/

+#define TIM_CCR1_CCR1_Pos         (0U)

+#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */

+

+/*******************  Bit definition for TIM_CCR2 register  *******************/

+#define TIM_CCR2_CCR2_Pos         (0U)

+#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */

+

+/*******************  Bit definition for TIM_CCR3 register  *******************/

+#define TIM_CCR3_CCR3_Pos         (0U)

+#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */

+

+/*******************  Bit definition for TIM_CCR4 register  *******************/

+#define TIM_CCR4_CCR4_Pos         (0U)

+#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */

+

+/*******************  Bit definition for TIM_CCR5 register  *******************/

+#define TIM_CCR5_CCR5_Pos         (0U)

+#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */

+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */

+#define TIM_CCR5_GC5C1_Pos        (29U)

+#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */

+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */

+#define TIM_CCR5_GC5C2_Pos        (30U)

+#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */

+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */

+#define TIM_CCR5_GC5C3_Pos        (31U)

+#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */

+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */

+

+/*******************  Bit definition for TIM_CCR6 register  *******************/

+#define TIM_CCR6_CCR6_Pos         (0U)

+#define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */

+

+/*******************  Bit definition for TIM_BDTR register  *******************/

+#define TIM_BDTR_DTG_Pos          (0U)

+#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */

+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */

+#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */

+#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */

+#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */

+#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */

+#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */

+#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */

+#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */

+#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */

+

+#define TIM_BDTR_LOCK_Pos         (8U)

+#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */

+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */

+#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */

+#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */

+

+#define TIM_BDTR_OSSI_Pos         (10U)

+#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */

+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */

+#define TIM_BDTR_OSSR_Pos         (11U)

+#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */

+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */

+#define TIM_BDTR_BKE_Pos          (12U)

+#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */

+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break1 */

+#define TIM_BDTR_BKP_Pos          (13U)

+#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */

+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break1 */

+#define TIM_BDTR_AOE_Pos          (14U)

+#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */

+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */

+#define TIM_BDTR_MOE_Pos          (15U)

+#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */

+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */

+

+#define TIM_BDTR_BKF_Pos          (16U)

+#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */

+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break1 */

+#define TIM_BDTR_BK2F_Pos         (20U)

+#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */

+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break2 */

+

+#define TIM_BDTR_BK2E_Pos         (24U)

+#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */

+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break2 */

+#define TIM_BDTR_BK2P_Pos         (25U)

+#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */

+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */

+

+/*******************  Bit definition for TIM_DCR register  ********************/

+#define TIM_DCR_DBA_Pos           (0U)

+#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */

+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */

+#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */

+#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */

+#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */

+#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */

+#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */

+

+#define TIM_DCR_DBL_Pos           (8U)

+#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */

+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */

+#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */

+#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */

+#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */

+#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */

+#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */

+

+/*******************  Bit definition for TIM_DMAR register  *******************/

+#define TIM_DMAR_DMAB_Pos         (0U)

+#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */

+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */

+

+/******************  Bit definition for TIM_CCMR3 register  *******************/

+#define TIM_CCMR3_OC5FE_Pos       (2U)

+#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */

+#define TIM_CCMR3_OC5PE_Pos       (3U)

+#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */

+

+#define TIM_CCMR3_OC5M_Pos        (4U)

+#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */

+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */

+#define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR3_OC5CE_Pos       (7U)

+#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */

+

+#define TIM_CCMR3_OC6FE_Pos       (10U)

+#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 4 Fast enable */

+#define TIM_CCMR3_OC6PE_Pos       (11U)

+#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */

+

+#define TIM_CCMR3_OC6M_Pos        (12U)

+#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */

+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */

+#define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */

+

+#define TIM_CCMR3_OC6CE_Pos       (15U)

+#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 4 Clear Enable */

+/*******************  Bit definition for TIM1_AF1 register  *********************/

+#define TIM1_AF1_BKINE_Pos        (0U)

+#define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */

+#define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */

+#define TIM1_AF1_BKCMP1E_Pos      (1U)

+#define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */

+#define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM1_AF1_BKCMP2E_Pos      (2U)

+#define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */

+#define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit */

+#define TIM1_AF1_BKDF1BK0E_Pos    (8U)

+#define TIM1_AF1_BKDF1BK0E_Msk    (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)            /*!< 0x00000100 */

+#define TIM1_AF1_BKDF1BK0E        TIM1_AF1_BKDF1BK0E_Msk                       /*!<BKDF1BK0E Break input DFSDM Break 0 */

+#define TIM1_AF1_BKINP_Pos        (9U)

+#define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */

+#define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */

+#define TIM1_AF1_BKCMP1P_Pos      (10U)

+#define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */

+#define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM1_AF1_BKCMP2P_Pos      (11U)

+#define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */

+#define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */

+

+#define TIM1_AF1_ETRSEL_Pos       (14U)

+#define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */

+#define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */

+#define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00004000 */

+#define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00008000 */

+#define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00010000 */

+#define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM1_AF2 register  *********************/

+#define TIM1_AF2_BK2INE_Pos       (0U)

+#define TIM1_AF2_BK2INE_Msk       (0x1UL << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */

+#define TIM1_AF2_BK2INE           TIM1_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */

+#define TIM1_AF2_BK2CMP1E_Pos     (1U)

+#define TIM1_AF2_BK2CMP1E_Msk     (0x1UL << TIM1_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */

+#define TIM1_AF2_BK2CMP1E         TIM1_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */

+#define TIM1_AF2_BK2CMP2E_Pos     (2U)

+#define TIM1_AF2_BK2CMP2E_Msk     (0x1UL << TIM1_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */

+#define TIM1_AF2_BK2CMP2E         TIM1_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */

+#define TIM1_AF2_BK2DFBK1E_Pos    (8U)

+#define TIM1_AF2_BK2DFBK1E_Msk    (0x1UL << TIM1_AF2_BK2DFBK1E_Pos)            /*!< 0x00000100 */

+#define TIM1_AF2_BK2DFBK1E        TIM1_AF2_BK2DFBK1E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 1 */

+#define TIM1_AF2_BK2INP_Pos       (9U)

+#define TIM1_AF2_BK2INP_Msk       (0x1UL << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */

+#define TIM1_AF2_BK2INP           TIM1_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */

+#define TIM1_AF2_BK2CMP1P_Pos     (10U)

+#define TIM1_AF2_BK2CMP1P_Msk     (0x1UL << TIM1_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */

+#define TIM1_AF2_BK2CMP1P         TIM1_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */

+#define TIM1_AF2_BK2CMP2P_Pos     (11U)

+#define TIM1_AF2_BK2CMP2P_Msk     (0x1UL << TIM1_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */

+#define TIM1_AF2_BK2CMP2P         TIM1_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */

+

+/*******************  Bit definition for TIM_TISEL register  *********************/

+#define TIM_TISEL_TI1SEL_Pos      (0U)

+#define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */

+#define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/

+#define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000001 */

+#define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000002 */

+#define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000004 */

+#define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000008 */

+

+#define TIM_TISEL_TI2SEL_Pos      (8U)

+#define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */

+#define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/

+#define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000100 */

+#define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000200 */

+#define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000400 */

+#define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000800 */

+

+#define TIM_TISEL_TI3SEL_Pos      (16U)

+#define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */

+#define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/

+#define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00010000 */

+#define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00020000 */

+#define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00040000 */

+#define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00080000 */

+

+#define TIM_TISEL_TI4SEL_Pos      (24U)

+#define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */

+#define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/

+#define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x01000000 */

+#define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x02000000 */

+#define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x04000000 */

+#define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x08000000 */

+

+/*******************  Bit definition for TIM8_AF1 register  *********************/

+#define TIM8_AF1_BKINE_Pos        (0U)

+#define TIM8_AF1_BKINE_Msk        (0x1UL << TIM8_AF1_BKINE_Pos)                /*!< 0x00000001 */

+#define TIM8_AF1_BKINE            TIM8_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */

+#define TIM8_AF1_BKCMP1E_Pos      (1U)

+#define TIM8_AF1_BKCMP1E_Msk      (0x1UL << TIM8_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */

+#define TIM8_AF1_BKCMP1E          TIM8_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM8_AF1_BKCMP2E_Pos      (2U)

+#define TIM8_AF1_BKCMP2E_Msk      (0x1UL << TIM8_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */

+#define TIM8_AF1_BKCMP2E          TIM8_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM8_AF1_BKDFBK2E_Pos     (8U)

+#define TIM8_AF1_BKDFBK2E_Msk     (0x1UL << TIM8_AF1_BKDFBK2E_Pos)             /*!< 0x00000100 */

+#define TIM8_AF1_BKDFBK2E         TIM8_AF1_BKDFBK2E_Msk                        /*!<BKDFBK2E Break input DFSDM Break 2 */

+#define TIM8_AF1_BKINP_Pos        (9U)

+#define TIM8_AF1_BKINP_Msk        (0x1UL << TIM8_AF1_BKINP_Pos)                /*!< 0x00000200 */

+#define TIM8_AF1_BKINP            TIM8_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */

+#define TIM8_AF1_BKCMP1P_Pos      (10U)

+#define TIM8_AF1_BKCMP1P_Msk      (0x1UL << TIM8_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */

+#define TIM8_AF1_BKCMP1P          TIM8_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM8_AF1_BKCMP2P_Pos      (11U)

+#define TIM8_AF1_BKCMP2P_Msk      (0x1UL << TIM8_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */

+#define TIM8_AF1_BKCMP2P          TIM8_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */

+

+#define TIM8_AF1_ETRSEL_Pos       (14U)

+#define TIM8_AF1_ETRSEL_Msk       (0xFUL << TIM8_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */

+#define TIM8_AF1_ETRSEL           TIM8_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */

+#define TIM8_AF1_ETRSEL_0         (0x1UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00004000 */

+#define TIM8_AF1_ETRSEL_1         (0x2UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00008000 */

+#define TIM8_AF1_ETRSEL_2         (0x4UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00010000 */

+#define TIM8_AF1_ETRSEL_3         (0x8UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00020000 */

+/*******************  Bit definition for TIM8_AF2 register  *********************/

+#define TIM8_AF2_BK2INE_Pos       (0U)

+#define TIM8_AF2_BK2INE_Msk       (0x1UL << TIM8_AF2_BK2INE_Pos)               /*!< 0x00000001 */

+#define TIM8_AF2_BK2INE           TIM8_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */

+#define TIM8_AF2_BK2CMP1E_Pos     (1U)

+#define TIM8_AF2_BK2CMP1E_Msk     (0x1UL << TIM8_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */

+#define TIM8_AF2_BK2CMP1E         TIM8_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */

+#define TIM8_AF2_BK2CMP2E_Pos     (2U)

+#define TIM8_AF2_BK2CMP2E_Msk     (0x1UL << TIM8_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */

+#define TIM8_AF2_BK2CMP2E         TIM8_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */

+#define TIM8_AF2_BK2DFBK3E_Pos    (8U)

+#define TIM8_AF2_BK2DFBK3E_Msk    (0x1UL << TIM8_AF2_BK2DFBK3E_Pos)            /*!< 0x00000100 */

+#define TIM8_AF2_BK2DFBK3E        TIM8_AF2_BK2DFBK3E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 3 */

+#define TIM8_AF2_BK2INP_Pos       (9U)

+#define TIM8_AF2_BK2INP_Msk       (0x1UL << TIM8_AF2_BK2INP_Pos)               /*!< 0x00000200 */

+#define TIM8_AF2_BK2INP           TIM8_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */

+#define TIM8_AF2_BK2CMP1P_Pos     (10U)

+#define TIM8_AF2_BK2CMP1P_Msk     (0x1UL << TIM8_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */

+#define TIM8_AF2_BK2CMP1P         TIM8_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */

+#define TIM8_AF2_BK2CMP2P_Pos     (11U)

+#define TIM8_AF2_BK2CMP2P_Msk     (0x1UL << TIM8_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */

+#define TIM8_AF2_BK2CMP2P         TIM8_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */

+

+/*******************  Bit definition for TIM2_AF1 register  *********************/

+#define TIM2_AF1_ETRSEL_Pos      (14U)

+#define TIM2_AF1_ETRSEL_Msk      (0xFUL << TIM2_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM2_AF1_ETRSEL          TIM2_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */

+#define TIM2_AF1_ETRSEL_0        (0x1UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM2_AF1_ETRSEL_1        (0x2UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM2_AF1_ETRSEL_2        (0x4UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM2_AF1_ETRSEL_3        (0x8UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM3_AF1 register  *********************/

+#define TIM3_AF1_ETRSEL_Pos      (14U)

+#define TIM3_AF1_ETRSEL_Msk      (0xFUL << TIM3_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM3_AF1_ETRSEL          TIM3_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */

+#define TIM3_AF1_ETRSEL_0        (0x1UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM3_AF1_ETRSEL_1        (0x2UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM3_AF1_ETRSEL_2        (0x4UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM3_AF1_ETRSEL_3        (0x8UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM5_AF1 register  *********************/

+#define TIM5_AF1_ETRSEL_Pos      (14U)

+#define TIM5_AF1_ETRSEL_Msk      (0xFUL << TIM5_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM5_AF1_ETRSEL          TIM5_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */

+#define TIM5_AF1_ETRSEL_0        (0x1UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM5_AF1_ETRSEL_1        (0x2UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM5_AF1_ETRSEL_2        (0x4UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM5_AF1_ETRSEL_3        (0x8UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM15_AF1 register  *********************/

+#define TIM15_AF1_BKINE_Pos        (0U)

+#define TIM15_AF1_BKINE_Msk        (0x1UL << TIM15_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM15_AF1_BKINE            TIM15_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM15_AF1_BKCMP1E_Pos      (1U)

+#define TIM15_AF1_BKCMP1E_Msk      (0x1UL << TIM15_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM15_AF1_BKCMP1E          TIM15_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM15_AF1_BKCMP2E_Pos      (2U)

+#define TIM15_AF1_BKCMP2E_Msk      (0x1UL << TIM15_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM15_AF1_BKCMP2E          TIM15_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM15_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM15_AF1_BKDF1BK2E_Msk    (0x1UL << TIM15_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM15_AF1_BKDF1BK2E        TIM15_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[0] enable */

+#define TIM15_AF1_BKINP_Pos        (9U)

+#define TIM15_AF1_BKINP_Msk        (0x1UL << TIM15_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM15_AF1_BKINP            TIM15_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM15_AF1_BKCMP1P_Pos      (10U)

+#define TIM15_AF1_BKCMP1P_Msk      (0x1UL << TIM15_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM15_AF1_BKCMP1P          TIM15_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM15_AF1_BKCMP2P_Pos      (11U)

+#define TIM15_AF1_BKCMP2P_Msk      (0x1UL << TIM15_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM15_AF1_BKCMP2P          TIM15_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/*******************  Bit definition for TIM16_ register  *********************/

+#define TIM16_AF1_BKINE_Pos        (0U)

+#define TIM16_AF1_BKINE_Msk        (0x1UL << TIM16_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM16_AF1_BKINE            TIM16_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM16_AF1_BKCMP1E_Pos      (1U)

+#define TIM16_AF1_BKCMP1E_Msk      (0x1UL << TIM16_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM16_AF1_BKCMP1E          TIM16_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM16_AF1_BKCMP2E_Pos      (2U)

+#define TIM16_AF1_BKCMP2E_Msk      (0x1UL << TIM16_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM16_AF1_BKCMP2E          TIM16_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM16_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM16_AF1_BKDF1BK2E_Msk    (0x1UL << TIM16_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM16_AF1_BKDF1BK2E        TIM16_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[1] enable */

+#define TIM16_AF1_BKINP_Pos        (9U)

+#define TIM16_AF1_BKINP_Msk        (0x1UL << TIM16_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM16_AF1_BKINP            TIM16_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM16_AF1_BKCMP1P_Pos      (10U)

+#define TIM16_AF1_BKCMP1P_Msk      (0x1UL << TIM16_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM16_AF1_BKCMP1P          TIM16_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM16_AF1_BKCMP2P_Pos      (11U)

+#define TIM16_AF1_BKCMP2P_Msk      (0x1UL << TIM16_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM16_AF1_BKCMP2P          TIM16_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/*******************  Bit definition for TIM17_AF1 register  *********************/

+#define TIM17_AF1_BKINE_Pos        (0U)

+#define TIM17_AF1_BKINE_Msk        (0x1UL << TIM17_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM17_AF1_BKINE            TIM17_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM17_AF1_BKCMP1E_Pos      (1U)

+#define TIM17_AF1_BKCMP1E_Msk      (0x1UL << TIM17_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM17_AF1_BKCMP1E          TIM17_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM17_AF1_BKCMP2E_Pos      (2U)

+#define TIM17_AF1_BKCMP2E_Msk      (0x1UL << TIM17_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM17_AF1_BKCMP2E          TIM17_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM17_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM17_AF1_BKDF1BK2E_Msk    (0x1UL << TIM17_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM17_AF1_BKDF1BK2E        TIM17_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[2] enable */

+#define TIM17_AF1_BKINP_Pos        (9U)

+#define TIM17_AF1_BKINP_Msk        (0x1UL << TIM17_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM17_AF1_BKINP            TIM17_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM17_AF1_BKCMP1P_Pos      (10U)

+#define TIM17_AF1_BKCMP1P_Msk      (0x1UL << TIM17_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM17_AF1_BKCMP1P          TIM17_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM17_AF1_BKCMP2P_Pos      (11U)

+#define TIM17_AF1_BKCMP2P_Msk      (0x1UL << TIM17_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM17_AF1_BKCMP2P          TIM17_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Low Power Timer (LPTTIM)                           */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for LPTIM_ISR register  *******************/

+#define LPTIM_ISR_CMPM_Pos          (0U)

+#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */

+#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */

+#define LPTIM_ISR_ARRM_Pos          (1U)

+#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */

+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */

+#define LPTIM_ISR_EXTTRIG_Pos       (2U)

+#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */

+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */

+#define LPTIM_ISR_CMPOK_Pos         (3U)

+#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */

+#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */

+#define LPTIM_ISR_ARROK_Pos         (4U)

+#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */

+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */

+#define LPTIM_ISR_UP_Pos            (5U)

+#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */

+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */

+#define LPTIM_ISR_DOWN_Pos          (6U)

+#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */

+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */

+

+/******************  Bit definition for LPTIM_ICR register  *******************/

+#define LPTIM_ICR_CMPMCF_Pos        (0U)

+#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */

+#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */

+#define LPTIM_ICR_ARRMCF_Pos        (1U)

+#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */

+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */

+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)

+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */

+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */

+#define LPTIM_ICR_CMPOKCF_Pos       (3U)

+#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */

+#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */

+#define LPTIM_ICR_ARROKCF_Pos       (4U)

+#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */

+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */

+#define LPTIM_ICR_UPCF_Pos          (5U)

+#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */

+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */

+#define LPTIM_ICR_DOWNCF_Pos        (6U)

+#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */

+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */

+

+/******************  Bit definition for LPTIM_IER register ********************/

+#define LPTIM_IER_CMPMIE_Pos        (0U)

+#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */

+#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */

+#define LPTIM_IER_ARRMIE_Pos        (1U)

+#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */

+#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */

+#define LPTIM_IER_EXTTRIGIE_Pos     (2U)

+#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */

+#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */

+#define LPTIM_IER_CMPOKIE_Pos       (3U)

+#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */

+#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */

+#define LPTIM_IER_ARROKIE_Pos       (4U)

+#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */

+#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */

+#define LPTIM_IER_UPIE_Pos          (5U)

+#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */

+#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */

+#define LPTIM_IER_DOWNIE_Pos        (6U)

+#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */

+#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */

+

+/******************  Bit definition for LPTIM_CFGR register *******************/

+#define LPTIM_CFGR_CKSEL_Pos        (0U)

+#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */

+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */

+

+#define LPTIM_CFGR_CKPOL_Pos        (1U)

+#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */

+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */

+#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */

+#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */

+

+#define LPTIM_CFGR_CKFLT_Pos        (3U)

+#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */

+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */

+#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */

+#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */

+

+#define LPTIM_CFGR_TRGFLT_Pos       (6U)

+#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */

+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */

+#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */

+#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */

+

+#define LPTIM_CFGR_PRESC_Pos        (9U)

+#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */

+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */

+#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */

+#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */

+#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */

+

+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)

+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */

+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */

+#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */

+#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */

+#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */

+

+#define LPTIM_CFGR_TRIGEN_Pos       (17U)

+#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */

+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */

+#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */

+#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */

+

+#define LPTIM_CFGR_TIMOUT_Pos       (19U)

+#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */

+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */

+#define LPTIM_CFGR_WAVE_Pos         (20U)

+#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */

+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */

+#define LPTIM_CFGR_WAVPOL_Pos       (21U)

+#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */

+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */

+#define LPTIM_CFGR_PRELOAD_Pos      (22U)

+#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */

+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */

+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)

+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */

+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */

+#define LPTIM_CFGR_ENC_Pos          (24U)

+#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */

+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */

+

+/******************  Bit definition for LPTIM_CR register  ********************/

+#define LPTIM_CR_ENABLE_Pos         (0U)

+#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */

+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */

+#define LPTIM_CR_SNGSTRT_Pos        (1U)

+#define LPTIM_CR_SNGSTRT_Msk        (0x40001UL << LPTIM_CR_SNGSTRT_Pos)        /*!< 0x00080002 */

+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */

+#define LPTIM_CR_CNTSTRT_Pos        (2U)

+#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */

+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */

+#define LPTIM_CR_COUNTRST_Pos       (3U)

+#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */

+#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Timer Counter reset in synchronous mode*/

+#define LPTIM_CR_RSTARE_Pos         (4U)

+#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */

+#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Timer Counter reset after read enable (asynchronously)*/

+

+

+/******************  Bit definition for LPTIM_CMP register  *******************/

+#define LPTIM_CMP_CMP_Pos           (0U)

+#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */

+

+/******************  Bit definition for LPTIM_ARR register  *******************/

+#define LPTIM_ARR_ARR_Pos           (0U)

+#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */

+

+/******************  Bit definition for LPTIM_CNT register  *******************/

+#define LPTIM_CNT_CNT_Pos           (0U)

+#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */

+

+/******************  Bit definition for LPTIM_CFGR2 register  *****************/

+#define LPTIM_CFGR2_IN1SEL_Pos      (0U)

+#define LPTIM_CFGR2_IN1SEL_Msk      (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000003 */

+#define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< IN1SEL[1:0] bits (Remap selection) */

+#define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000001 */

+#define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000002 */

+#define LPTIM_CFGR2_IN2SEL_Pos      (4U)

+#define LPTIM_CFGR2_IN2SEL_Msk      (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000030 */

+#define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< IN2SEL[5:4] bits (Remap selection) */

+#define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000010 */

+#define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000020 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    OCTOSPI                                 */

+/*                                                                            */

+/******************************************************************************/

+/*****************  Bit definition for OCTOSPI_CR register  *******************/

+#define OCTOSPI_CR_EN_Pos              (0U)

+#define OCTOSPI_CR_EN_Msk              (0x1UL << OCTOSPI_CR_EN_Pos)             /*!< 0x00000001 */

+#define OCTOSPI_CR_EN                  OCTOSPI_CR_EN_Msk                       /*!< Enable */

+#define OCTOSPI_CR_ABORT_Pos           (1U)

+#define OCTOSPI_CR_ABORT_Msk           (0x1UL << OCTOSPI_CR_ABORT_Pos)          /*!< 0x00000002 */

+#define OCTOSPI_CR_ABORT               OCTOSPI_CR_ABORT_Msk                    /*!< Abort request */

+#define OCTOSPI_CR_DMAEN_Pos           (2U)

+#define OCTOSPI_CR_DMAEN_Msk           (0x1UL << OCTOSPI_CR_DMAEN_Pos)          /*!< 0x00000004 */

+#define OCTOSPI_CR_DMAEN               OCTOSPI_CR_DMAEN_Msk                    /*!< DMA Enable */

+#define OCTOSPI_CR_TCEN_Pos            (3U)

+#define OCTOSPI_CR_TCEN_Msk            (0x1UL << OCTOSPI_CR_TCEN_Pos)           /*!< 0x00000008 */

+#define OCTOSPI_CR_TCEN                OCTOSPI_CR_TCEN_Msk                     /*!< Timeout Counter Enable */

+#define OCTOSPI_CR_DQM_Pos             (6U)

+#define OCTOSPI_CR_DQM_Msk             (0x1UL << OCTOSPI_CR_DQM_Pos)            /*!< 0x00000040 */

+#define OCTOSPI_CR_DQM                 OCTOSPI_CR_DQM_Msk                      /*!< Dual-Quad Mode */

+#define OCTOSPI_CR_FSEL_Pos            (7U)

+#define OCTOSPI_CR_FSEL_Msk            (0x1UL << OCTOSPI_CR_FSEL_Pos)           /*!< 0x00000080 */

+#define OCTOSPI_CR_FSEL                OCTOSPI_CR_FSEL_Msk                     /*!< Flash Select */

+#define OCTOSPI_CR_FTHRES_Pos          (8U)

+#define OCTOSPI_CR_FTHRES_Msk          (0x1FUL << OCTOSPI_CR_FTHRES_Pos)        /*!< 0x00001F00 */

+#define OCTOSPI_CR_FTHRES              OCTOSPI_CR_FTHRES_Msk                   /*!< FIFO Threshold Level */

+#define OCTOSPI_CR_TEIE_Pos            (16U)

+#define OCTOSPI_CR_TEIE_Msk            (0x1UL << OCTOSPI_CR_TEIE_Pos)           /*!< 0x00010000 */

+#define OCTOSPI_CR_TEIE                OCTOSPI_CR_TEIE_Msk                     /*!< Transfer Error Interrupt Enable */

+#define OCTOSPI_CR_TCIE_Pos            (17U)

+#define OCTOSPI_CR_TCIE_Msk            (0x1UL << OCTOSPI_CR_TCIE_Pos)           /*!< 0x00020000 */

+#define OCTOSPI_CR_TCIE                OCTOSPI_CR_TCIE_Msk                     /*!< Transfer Complete Interrupt Enable */

+#define OCTOSPI_CR_FTIE_Pos            (18U)

+#define OCTOSPI_CR_FTIE_Msk            (0x1UL << OCTOSPI_CR_FTIE_Pos)           /*!< 0x00040000 */

+#define OCTOSPI_CR_FTIE                OCTOSPI_CR_FTIE_Msk                     /*!< FIFO Threshold Interrupt Enable */

+#define OCTOSPI_CR_SMIE_Pos            (19U)

+#define OCTOSPI_CR_SMIE_Msk            (0x1UL << OCTOSPI_CR_SMIE_Pos)           /*!< 0x00080000 */

+#define OCTOSPI_CR_SMIE                OCTOSPI_CR_SMIE_Msk                     /*!< Status Match Interrupt Enable */

+#define OCTOSPI_CR_TOIE_Pos            (20U)

+#define OCTOSPI_CR_TOIE_Msk            (0x1UL << OCTOSPI_CR_TOIE_Pos)           /*!< 0x00100000 */

+#define OCTOSPI_CR_TOIE                OCTOSPI_CR_TOIE_Msk                     /*!< TimeOut Interrupt Enable */

+#define OCTOSPI_CR_APMS_Pos            (22U)

+#define OCTOSPI_CR_APMS_Msk            (0x1UL << OCTOSPI_CR_APMS_Pos)           /*!< 0x00400000 */

+#define OCTOSPI_CR_APMS                OCTOSPI_CR_APMS_Msk                     /*!< Automatic Poll Mode Stop */

+#define OCTOSPI_CR_PMM_Pos             (23U)

+#define OCTOSPI_CR_PMM_Msk             (0x1UL << OCTOSPI_CR_PMM_Pos)            /*!< 0x00800000 */

+#define OCTOSPI_CR_PMM                 OCTOSPI_CR_PMM_Msk                      /*!< Polling Match Mode */

+#define OCTOSPI_CR_FMODE_Pos           (28U)

+#define OCTOSPI_CR_FMODE_Msk           (0x3UL << OCTOSPI_CR_FMODE_Pos)          /*!< 0x30000000 */

+#define OCTOSPI_CR_FMODE               OCTOSPI_CR_FMODE_Msk                    /*!< Functional Mode */

+#define OCTOSPI_CR_FMODE_0             (0x1UL << OCTOSPI_CR_FMODE_Pos)          /*!< 0x10000000 */

+#define OCTOSPI_CR_FMODE_1             (0x2UL << OCTOSPI_CR_FMODE_Pos)          /*!< 0x20000000 */

+

+/****************  Bit definition for OCTOSPI_DCR1 register  ******************/

+#define OCTOSPI_DCR1_CKMODE_Pos        (0U)

+#define OCTOSPI_DCR1_CKMODE_Msk        (0x1UL << OCTOSPI_DCR1_CKMODE_Pos)       /*!< 0x00000001 */

+#define OCTOSPI_DCR1_CKMODE            OCTOSPI_DCR1_CKMODE_Msk                 /*!< Mode 0 / Mode 3 */

+#define OCTOSPI_DCR1_FRCK_Pos          (1U)

+#define OCTOSPI_DCR1_FRCK_Msk          (0x1UL << OCTOSPI_DCR1_FRCK_Pos)         /*!< 0x00000002 */

+#define OCTOSPI_DCR1_FRCK              OCTOSPI_DCR1_FRCK_Msk                   /*!< Free Running Clock */

+#define OCTOSPI_DCR1_DLYBYP_Pos        (3U)

+#define OCTOSPI_DCR1_DLYBYP_Msk        (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos)       /*!< 0x00000008 */

+#define OCTOSPI_DCR1_DLYBYP            OCTOSPI_DCR1_DLYBYP_Msk                 /*!< Delay Block */

+#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)

+#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */

+#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */

+#define OCTOSPI_DCR1_CSHT_Pos          (8U)

+#define OCTOSPI_DCR1_CSHT_Msk          (0x7UL << OCTOSPI_DCR1_CSHT_Pos)         /*!< 0x00000700 */

+#define OCTOSPI_DCR1_CSHT              OCTOSPI_DCR1_CSHT_Msk                   /*!< Chip Select High Time */

+#define OCTOSPI_DCR1_DEVSIZE_Pos       (16U)

+#define OCTOSPI_DCR1_DEVSIZE_Msk       (0x1FUL << OCTOSPI_DCR1_DEVSIZE_Pos)     /*!< 0x001F0000 */

+#define OCTOSPI_DCR1_DEVSIZE           OCTOSPI_DCR1_DEVSIZE_Msk                /*!< Device Size */

+#define OCTOSPI_DCR1_MTYP_Pos          (24U)

+#define OCTOSPI_DCR1_MTYP_Msk          (0x7UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x07000000 */

+#define OCTOSPI_DCR1_MTYP              OCTOSPI_DCR1_MTYP_Msk                   /*!< Memory Type */

+#define OCTOSPI_DCR1_MTYP_0            (0x1UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x01000000 */

+#define OCTOSPI_DCR1_MTYP_1            (0x2UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x02000000 */

+#define OCTOSPI_DCR1_MTYP_2            (0x4UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x04000000 */

+

+/****************  Bit definition for OCTOSPI_DCR2 register  ******************/

+#define OCTOSPI_DCR2_PRESCALER_Pos     (0U)

+#define OCTOSPI_DCR2_PRESCALER_Msk     (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos)   /*!< 0x000000FF */

+#define OCTOSPI_DCR2_PRESCALER         OCTOSPI_DCR2_PRESCALER_Msk              /*!< Clock prescaler */

+#define OCTOSPI_DCR2_WRAPSIZE_Pos      (16U)

+#define OCTOSPI_DCR2_WRAPSIZE_Msk      (0x7UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00070000 */

+#define OCTOSPI_DCR2_WRAPSIZE          OCTOSPI_DCR2_WRAPSIZE_Msk               /*!< Wrap Size */

+#define OCTOSPI_DCR2_WRAPSIZE_0        (0x1UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00010000 */

+#define OCTOSPI_DCR2_WRAPSIZE_1        (0x2UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00020000 */

+#define OCTOSPI_DCR2_WRAPSIZE_2        (0x4UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00040000 */

+

+/****************  Bit definition for OCTOSPI_DCR3 register  ******************/

+#define OCTOSPI_DCR3_MAXTRAN_Pos       (0U)

+#define OCTOSPI_DCR3_MAXTRAN_Msk       (0xFFUL << OCTOSPI_DCR3_MAXTRAN_Pos)     /*!< 0x000000FF */

+#define OCTOSPI_DCR3_MAXTRAN           OCTOSPI_DCR3_MAXTRAN_Msk                /*!< Maximum Transfer */

+#define OCTOSPI_DCR3_CSBOUND_Pos       (16U)

+#define OCTOSPI_DCR3_CSBOUND_Msk       (0x1FUL << OCTOSPI_DCR3_CSBOUND_Pos)     /*!< 0x001F0000 */

+#define OCTOSPI_DCR3_CSBOUND           OCTOSPI_DCR3_CSBOUND_Msk                /*!< CS Boundary */

+

+/****************  Bit definition for OCTOSPI_DCR4 register  ******************/

+#define OCTOSPI_DCR4_REFRESH_Pos       (0U)

+#define OCTOSPI_DCR4_REFRESH_Msk       (0xFFFFFFFFUL << OCTOSPI_DCR4_REFRESH_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_DCR4_REFRESH           OCTOSPI_DCR4_REFRESH_Msk                /*!< Refresh rate */

+

+/*****************  Bit definition for OCTOSPI_SR register  *******************/

+#define OCTOSPI_SR_TEF_Pos             (0U)

+#define OCTOSPI_SR_TEF_Msk             (0x1UL << OCTOSPI_SR_TEF_Pos)            /*!< 0x00000001 */

+#define OCTOSPI_SR_TEF                 OCTOSPI_SR_TEF_Msk                      /*!< Transfer Error Flag */

+#define OCTOSPI_SR_TCF_Pos             (1U)

+#define OCTOSPI_SR_TCF_Msk             (0x1UL << OCTOSPI_SR_TCF_Pos)            /*!< 0x00000002 */

+#define OCTOSPI_SR_TCF                 OCTOSPI_SR_TCF_Msk                      /*!< Transfer Complete Flag */

+#define OCTOSPI_SR_FTF_Pos             (2U)

+#define OCTOSPI_SR_FTF_Msk             (0x1UL << OCTOSPI_SR_FTF_Pos)            /*!< 0x00000004 */

+#define OCTOSPI_SR_FTF                 OCTOSPI_SR_FTF_Msk                      /*!< FIFO Threshold Flag */

+#define OCTOSPI_SR_SMF_Pos             (3U)

+#define OCTOSPI_SR_SMF_Msk             (0x1UL << OCTOSPI_SR_SMF_Pos)            /*!< 0x00000008 */

+#define OCTOSPI_SR_SMF                 OCTOSPI_SR_SMF_Msk                      /*!< Status Match Flag */

+#define OCTOSPI_SR_TOF_Pos             (4U)

+#define OCTOSPI_SR_TOF_Msk             (0x1UL << OCTOSPI_SR_TOF_Pos)            /*!< 0x00000010 */

+#define OCTOSPI_SR_TOF                 OCTOSPI_SR_TOF_Msk                      /*!< Timeout Flag */

+#define OCTOSPI_SR_BUSY_Pos            (5U)

+#define OCTOSPI_SR_BUSY_Msk            (0x1UL << OCTOSPI_SR_BUSY_Pos)           /*!< 0x00000020 */

+#define OCTOSPI_SR_BUSY                OCTOSPI_SR_BUSY_Msk                     /*!< Busy */

+#define OCTOSPI_SR_FLEVEL_Pos          (8U)

+#define OCTOSPI_SR_FLEVEL_Msk          (0x3FUL << OCTOSPI_SR_FLEVEL_Pos)        /*!< 0x00003F00 */

+#define OCTOSPI_SR_FLEVEL              OCTOSPI_SR_FLEVEL_Msk                   /*!< FIFO Level */

+

+/****************  Bit definition for OCTOSPI_FCR register  *******************/

+#define OCTOSPI_FCR_CTEF_Pos           (0U)

+#define OCTOSPI_FCR_CTEF_Msk           (0x1UL << OCTOSPI_FCR_CTEF_Pos)          /*!< 0x00000001 */

+#define OCTOSPI_FCR_CTEF               OCTOSPI_FCR_CTEF_Msk                    /*!< Clear Transfer Error Flag */

+#define OCTOSPI_FCR_CTCF_Pos           (1U)

+#define OCTOSPI_FCR_CTCF_Msk           (0x1UL << OCTOSPI_FCR_CTCF_Pos)          /*!< 0x00000002 */

+#define OCTOSPI_FCR_CTCF               OCTOSPI_FCR_CTCF_Msk                    /*!< Clear Transfer Complete Flag */

+#define OCTOSPI_FCR_CSMF_Pos           (3U)

+#define OCTOSPI_FCR_CSMF_Msk           (0x1UL << OCTOSPI_FCR_CSMF_Pos)          /*!< 0x00000008 */

+#define OCTOSPI_FCR_CSMF               OCTOSPI_FCR_CSMF_Msk                    /*!< Clear Status Match Flag */

+#define OCTOSPI_FCR_CTOF_Pos           (4U)

+#define OCTOSPI_FCR_CTOF_Msk           (0x1UL << OCTOSPI_FCR_CTOF_Pos)          /*!< 0x00000010 */

+#define OCTOSPI_FCR_CTOF               OCTOSPI_FCR_CTOF_Msk                    /*!< Clear Timeout Flag */

+

+/****************  Bit definition for OCTOSPI_DLR register  *******************/

+#define OCTOSPI_DLR_DL_Pos             (0U)

+#define OCTOSPI_DLR_DL_Msk             (0xFFFFFFFFUL << OCTOSPI_DLR_DL_Pos)     /*!< 0xFFFFFFFF */

+#define OCTOSPI_DLR_DL                 OCTOSPI_DLR_DL_Msk                      /*!< Data Length */

+

+/*****************  Bit definition for OCTOSPI_AR register  *******************/

+#define OCTOSPI_AR_ADDRESS_Pos         (0U)

+#define OCTOSPI_AR_ADDRESS_Msk         (0xFFFFFFFFUL << OCTOSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_AR_ADDRESS             OCTOSPI_AR_ADDRESS_Msk                  /*!< Address */

+

+/*****************  Bit definition for OCTOSPI_DR register  *******************/

+#define OCTOSPI_DR_DATA_Pos            (0U)

+#define OCTOSPI_DR_DATA_Msk            (0xFFFFFFFFUL << OCTOSPI_DR_DATA_Pos)    /*!< 0xFFFFFFFF */

+#define OCTOSPI_DR_DATA                OCTOSPI_DR_DATA_Msk                     /*!< Data */

+

+/***************  Bit definition for OCTOSPI_PSMKR register  ******************/

+#define OCTOSPI_PSMKR_MASK_Pos         (0U)

+#define OCTOSPI_PSMKR_MASK_Msk         (0xFFFFFFFFUL << OCTOSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_PSMKR_MASK             OCTOSPI_PSMKR_MASK_Msk                  /*!< Status mask */

+

+/***************  Bit definition for OCTOSPI_PSMAR register  ******************/

+#define OCTOSPI_PSMAR_MATCH_Pos        (0U)

+#define OCTOSPI_PSMAR_MATCH_Msk        (0xFFFFFFFFUL << OCTOSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_PSMAR_MATCH            OCTOSPI_PSMAR_MATCH_Msk                 /*!< Status match */

+

+/****************  Bit definition for OCTOSPI_PIR register  *******************/

+#define OCTOSPI_PIR_INTERVAL_Pos       (0U)

+#define OCTOSPI_PIR_INTERVAL_Msk       (0xFFFFUL << OCTOSPI_PIR_INTERVAL_Pos)   /*!< 0x0000FFFF */

+#define OCTOSPI_PIR_INTERVAL           OCTOSPI_PIR_INTERVAL_Msk                /*!< Polling Interval */

+

+/****************  Bit definition for OCTOSPI_CCR register  *******************/

+#define OCTOSPI_CCR_IMODE_Pos          (0U)

+#define OCTOSPI_CCR_IMODE_Msk          (0x7UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000007 */

+#define OCTOSPI_CCR_IMODE              OCTOSPI_CCR_IMODE_Msk                   /*!< Instruction Mode */

+#define OCTOSPI_CCR_IMODE_0            (0x1UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000001 */

+#define OCTOSPI_CCR_IMODE_1            (0x2UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000002 */

+#define OCTOSPI_CCR_IMODE_2            (0x4UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000004 */

+#define OCTOSPI_CCR_IDTR_Pos           (3U)

+#define OCTOSPI_CCR_IDTR_Msk           (0x1UL << OCTOSPI_CCR_IDTR_Pos)          /*!< 0x00000008 */

+#define OCTOSPI_CCR_IDTR               OCTOSPI_CCR_IDTR_Msk                    /*!< Instruction Double Transfer Rate */

+#define OCTOSPI_CCR_ISIZE_Pos          (4U)

+#define OCTOSPI_CCR_ISIZE_Msk          (0x3UL << OCTOSPI_CCR_ISIZE_Pos)         /*!< 0x00000030 */

+#define OCTOSPI_CCR_ISIZE              OCTOSPI_CCR_ISIZE_Msk                   /*!< Instruction Size */

+#define OCTOSPI_CCR_ISIZE_0            (0x1UL << OCTOSPI_CCR_ISIZE_Pos)         /*!< 0x00000010 */

+#define OCTOSPI_CCR_ISIZE_1            (0x2UL << OCTOSPI_CCR_ISIZE_Pos)         /*!< 0x00000020 */

+#define OCTOSPI_CCR_ADMODE_Pos         (8U)

+#define OCTOSPI_CCR_ADMODE_Msk         (0x7UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000700 */

+#define OCTOSPI_CCR_ADMODE             OCTOSPI_CCR_ADMODE_Msk                  /*!< Address Mode */

+#define OCTOSPI_CCR_ADMODE_0           (0x1UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000100 */

+#define OCTOSPI_CCR_ADMODE_1           (0x2UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000200 */

+#define OCTOSPI_CCR_ADMODE_2           (0x4UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000400 */

+#define OCTOSPI_CCR_ADDTR_Pos          (11U)

+#define OCTOSPI_CCR_ADDTR_Msk          (0x1UL << OCTOSPI_CCR_ADDTR_Pos)         /*!< 0x00000800 */

+#define OCTOSPI_CCR_ADDTR              OCTOSPI_CCR_ADDTR_Msk                   /*!< Address Double Transfer Rate */

+#define OCTOSPI_CCR_ADSIZE_Pos         (12U)

+#define OCTOSPI_CCR_ADSIZE_Msk         (0x3UL << OCTOSPI_CCR_ADSIZE_Pos)        /*!< 0x00003000 */

+#define OCTOSPI_CCR_ADSIZE             OCTOSPI_CCR_ADSIZE_Msk                  /*!< Address Size */

+#define OCTOSPI_CCR_ADSIZE_0           (0x1UL << OCTOSPI_CCR_ADSIZE_Pos)        /*!< 0x00001000 */

+#define OCTOSPI_CCR_ADSIZE_1           (0x2UL << OCTOSPI_CCR_ADSIZE_Pos)        /*!< 0x00002000 */

+#define OCTOSPI_CCR_ABMODE_Pos         (16U)

+#define OCTOSPI_CCR_ABMODE_Msk         (0x7UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00070000 */

+#define OCTOSPI_CCR_ABMODE             OCTOSPI_CCR_ABMODE_Msk                  /*!< Alternate Bytes Mode */

+#define OCTOSPI_CCR_ABMODE_0           (0x1UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00010000 */

+#define OCTOSPI_CCR_ABMODE_1           (0x2UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00020000 */

+#define OCTOSPI_CCR_ABMODE_2           (0x4UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00040000 */

+#define OCTOSPI_CCR_ABDTR_Pos          (19U)

+#define OCTOSPI_CCR_ABDTR_Msk          (0x1UL << OCTOSPI_CCR_ABDTR_Pos)         /*!< 0x00080000 */

+#define OCTOSPI_CCR_ABDTR              OCTOSPI_CCR_ABDTR_Msk                   /*!< Alternate Bytes Double Transfer Rate */

+#define OCTOSPI_CCR_ABSIZE_Pos         (20U)

+#define OCTOSPI_CCR_ABSIZE_Msk         (0x3UL << OCTOSPI_CCR_ABSIZE_Pos)        /*!< 0x00300000 */

+#define OCTOSPI_CCR_ABSIZE             OCTOSPI_CCR_ABSIZE_Msk                  /*!< Alternate Bytes Size */

+#define OCTOSPI_CCR_ABSIZE_0           (0x1UL << OCTOSPI_CCR_ABSIZE_Pos)        /*!< 0x00100000 */

+#define OCTOSPI_CCR_ABSIZE_1           (0x2UL << OCTOSPI_CCR_ABSIZE_Pos)        /*!< 0x00200000 */

+#define OCTOSPI_CCR_DMODE_Pos          (24U)

+#define OCTOSPI_CCR_DMODE_Msk          (0x7UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x07000000 */

+#define OCTOSPI_CCR_DMODE              OCTOSPI_CCR_DMODE_Msk                   /*!< Data Mode */

+#define OCTOSPI_CCR_DMODE_0            (0x1UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x01000000 */

+#define OCTOSPI_CCR_DMODE_1            (0x2UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x02000000 */

+#define OCTOSPI_CCR_DMODE_2            (0x4UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x04000000 */

+#define OCTOSPI_CCR_DDTR_Pos           (27U)

+#define OCTOSPI_CCR_DDTR_Msk           (0x1UL << OCTOSPI_CCR_DDTR_Pos)          /*!< 0x08000000 */

+#define OCTOSPI_CCR_DDTR               OCTOSPI_CCR_DDTR_Msk                    /*!< Data Double Transfer Rate */

+#define OCTOSPI_CCR_DQSE_Pos           (29U)

+#define OCTOSPI_CCR_DQSE_Msk           (0x1UL << OCTOSPI_CCR_DQSE_Pos)          /*!< 0x20000000 */

+#define OCTOSPI_CCR_DQSE               OCTOSPI_CCR_DQSE_Msk                    /*!< DQS Enable */

+#define OCTOSPI_CCR_SIOO_Pos           (31U)

+#define OCTOSPI_CCR_SIOO_Msk           (0x1UL << OCTOSPI_CCR_SIOO_Pos)          /*!< 0x80000000 */

+#define OCTOSPI_CCR_SIOO               OCTOSPI_CCR_SIOO_Msk                    /*!< Send Instruction Only Once Mode */

+

+/****************  Bit definition for OCTOSPI_TCR register  *******************/

+#define OCTOSPI_TCR_DCYC_Pos           (0U)

+#define OCTOSPI_TCR_DCYC_Msk           (0x1FUL << OCTOSPI_TCR_DCYC_Pos)         /*!< 0x0000001F */

+#define OCTOSPI_TCR_DCYC               OCTOSPI_TCR_DCYC_Msk                    /*!< Number of Dummy Cycles */

+#define OCTOSPI_TCR_DHQC_Pos           (28U)

+#define OCTOSPI_TCR_DHQC_Msk           (0x1UL << OCTOSPI_TCR_DHQC_Pos)          /*!< 0x10000000 */

+#define OCTOSPI_TCR_DHQC               OCTOSPI_TCR_DHQC_Msk                    /*!< Delay Hold Quarter Cycle */

+#define OCTOSPI_TCR_SSHIFT_Pos         (30U)

+#define OCTOSPI_TCR_SSHIFT_Msk         (0x1UL << OCTOSPI_TCR_SSHIFT_Pos)        /*!< 0x40000000 */

+#define OCTOSPI_TCR_SSHIFT             OCTOSPI_TCR_SSHIFT_Msk                  /*!< Sample Shift */

+

+/*****************  Bit definition for OCTOSPI_IR register  *******************/

+#define OCTOSPI_IR_INSTRUCTION_Pos     (0U)

+#define OCTOSPI_IR_INSTRUCTION_Msk     (0xFFFFFFFFUL << OCTOSPI_IR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_IR_INSTRUCTION         OCTOSPI_IR_INSTRUCTION_Msk              /*!< Instruction */

+

+/****************  Bit definition for OCTOSPI_ABR register  *******************/

+#define OCTOSPI_ABR_ALTERNATE_Pos      (0U)

+#define OCTOSPI_ABR_ALTERNATE_Msk      (0xFFFFFFFFUL << OCTOSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_ABR_ALTERNATE          OCTOSPI_ABR_ALTERNATE_Msk               /*!< Alternate Bytes */

+

+/****************  Bit definition for OCTOSPI_LPTR register  ******************/

+#define OCTOSPI_LPTR_TIMEOUT_Pos       (0U)

+#define OCTOSPI_LPTR_TIMEOUT_Msk       (0xFFFFUL << OCTOSPI_LPTR_TIMEOUT_Pos)   /*!< 0x0000FFFF */

+#define OCTOSPI_LPTR_TIMEOUT           OCTOSPI_LPTR_TIMEOUT_Msk                /*!< Timeout period */

+

+/****************  Bit definition for OCTOSPI_WPCCR register  *******************/

+#define OCTOSPI_WPCCR_IMODE_Pos        (0U)

+#define OCTOSPI_WPCCR_IMODE_Msk        (0x7UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000007 */

+#define OCTOSPI_WPCCR_IMODE            OCTOSPI_WPCCR_IMODE_Msk                 /*!< Instruction Mode */

+#define OCTOSPI_WPCCR_IMODE_0          (0x1UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000001 */

+#define OCTOSPI_WPCCR_IMODE_1          (0x2UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000002 */

+#define OCTOSPI_WPCCR_IMODE_2          (0x4UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000004 */

+#define OCTOSPI_WPCCR_IDTR_Pos         (3U)

+#define OCTOSPI_WPCCR_IDTR_Msk         (0x1UL << OCTOSPI_WPCCR_IDTR_Pos)        /*!< 0x00000008 */

+#define OCTOSPI_WPCCR_IDTR             OCTOSPI_WPCCR_IDTR_Msk                  /*!< Instruction Double Transfer Rate */

+#define OCTOSPI_WPCCR_ISIZE_Pos        (4U)

+#define OCTOSPI_WPCCR_ISIZE_Msk        (0x3UL << OCTOSPI_WPCCR_ISIZE_Pos)       /*!< 0x00000030 */

+#define OCTOSPI_WPCCR_ISIZE            OCTOSPI_WPCCR_ISIZE_Msk                 /*!< Instruction Size */

+#define OCTOSPI_WPCCR_ISIZE_0          (0x1UL << OCTOSPI_WPCCR_ISIZE_Pos)       /*!< 0x00000010 */

+#define OCTOSPI_WPCCR_ISIZE_1          (0x2UL << OCTOSPI_WPCCR_ISIZE_Pos)       /*!< 0x00000020 */

+#define OCTOSPI_WPCCR_ADMODE_Pos       (8U)

+#define OCTOSPI_WPCCR_ADMODE_Msk       (0x7UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000700 */

+#define OCTOSPI_WPCCR_ADMODE           OCTOSPI_WPCCR_ADMODE_Msk                /*!< Address Mode */

+#define OCTOSPI_WPCCR_ADMODE_0         (0x1UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000100 */

+#define OCTOSPI_WPCCR_ADMODE_1         (0x2UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000200 */

+#define OCTOSPI_WPCCR_ADMODE_2         (0x4UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000400 */

+#define OCTOSPI_WPCCR_ADDTR_Pos        (11U)

+#define OCTOSPI_WPCCR_ADDTR_Msk        (0x1UL << OCTOSPI_WPCCR_ADDTR_Pos)       /*!< 0x00000800 */

+#define OCTOSPI_WPCCR_ADDTR            OCTOSPI_WPCCR_ADDTR_Msk                 /*!< Address Double Transfer Rate */

+#define OCTOSPI_WPCCR_ADSIZE_Pos       (12U)

+#define OCTOSPI_WPCCR_ADSIZE_Msk       (0x3UL << OCTOSPI_WPCCR_ADSIZE_Pos)      /*!< 0x00003000 */

+#define OCTOSPI_WPCCR_ADSIZE           OCTOSPI_WPCCR_ADSIZE_Msk                /*!< Address Size */

+#define OCTOSPI_WPCCR_ADSIZE_0         (0x1UL << OCTOSPI_WPCCR_ADSIZE_Pos)      /*!< 0x00001000 */

+#define OCTOSPI_WPCCR_ADSIZE_1         (0x2UL << OCTOSPI_WPCCR_ADSIZE_Pos)      /*!< 0x00002000 */

+#define OCTOSPI_WPCCR_ABMODE_Pos       (16U)

+#define OCTOSPI_WPCCR_ABMODE_Msk       (0x7UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00070000 */

+#define OCTOSPI_WPCCR_ABMODE           OCTOSPI_WPCCR_ABMODE_Msk                /*!< Alternate Bytes Mode */

+#define OCTOSPI_WPCCR_ABMODE_0         (0x1UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00010000 */

+#define OCTOSPI_WPCCR_ABMODE_1         (0x2UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00020000 */

+#define OCTOSPI_WPCCR_ABMODE_2         (0x4UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00040000 */

+#define OCTOSPI_WPCCR_ABDTR_Pos        (19U)

+#define OCTOSPI_WPCCR_ABDTR_Msk        (0x1UL << OCTOSPI_WPCCR_ABDTR_Pos)       /*!< 0x00080000 */

+#define OCTOSPI_WPCCR_ABDTR            OCTOSPI_WPCCR_ABDTR_Msk                 /*!< Alternate Bytes Double Transfer Rate */

+#define OCTOSPI_WPCCR_ABSIZE_Pos       (20U)

+#define OCTOSPI_WPCCR_ABSIZE_Msk       (0x3UL << OCTOSPI_WPCCR_ABSIZE_Pos)      /*!< 0x00300000 */

+#define OCTOSPI_WPCCR_ABSIZE           OCTOSPI_WPCCR_ABSIZE_Msk                /*!< Alternate Bytes Size */

+#define OCTOSPI_WPCCR_ABSIZE_0         (0x1UL << OCTOSPI_WPCCR_ABSIZE_Pos)      /*!< 0x00100000 */

+#define OCTOSPI_WPCCR_ABSIZE_1         (0x2UL << OCTOSPI_WPCCR_ABSIZE_Pos)      /*!< 0x00200000 */

+#define OCTOSPI_WPCCR_DMODE_Pos        (24U)

+#define OCTOSPI_WPCCR_DMODE_Msk        (0x7UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x07000000 */

+#define OCTOSPI_WPCCR_DMODE            OCTOSPI_WPCCR_DMODE_Msk                 /*!< Data Mode */

+#define OCTOSPI_WPCCR_DMODE_0          (0x1UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x01000000 */

+#define OCTOSPI_WPCCR_DMODE_1          (0x2UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x02000000 */

+#define OCTOSPI_WPCCR_DMODE_2          (0x4UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x04000000 */

+#define OCTOSPI_WPCCR_DDTR_Pos         (27U)

+#define OCTOSPI_WPCCR_DDTR_Msk         (0x1UL << OCTOSPI_WPCCR_DDTR_Pos)        /*!< 0x08000000 */

+#define OCTOSPI_WPCCR_DDTR             OCTOSPI_WPCCR_DDTR_Msk                  /*!< Data Double Transfer Rate */

+#define OCTOSPI_WPCCR_DQSE_Pos         (29U)

+#define OCTOSPI_WPCCR_DQSE_Msk         (0x1UL << OCTOSPI_WPCCR_DQSE_Pos)        /*!< 0x20000000 */

+#define OCTOSPI_WPCCR_DQSE             OCTOSPI_WPCCR_DQSE_Msk                  /*!< DQS Enable */

+#define OCTOSPI_WPCCR_SIOO_Pos         (31U)

+#define OCTOSPI_WPCCR_SIOO_Msk         (0x1UL << OCTOSPI_WPCCR_SIOO_Pos)        /*!< 0x80000000 */

+#define OCTOSPI_WPCCR_SIOO             OCTOSPI_WPCCR_SIOO_Msk                  /*!< Send Instruction Only Once Mode */

+

+/****************  Bit definition for OCTOSPI_WPTCR register  *******************/

+#define OCTOSPI_WPTCR_DCYC_Pos         (0U)

+#define OCTOSPI_WPTCR_DCYC_Msk         (0x1FUL << OCTOSPI_WPTCR_DCYC_Pos)       /*!< 0x0000001F */

+#define OCTOSPI_WPTCR_DCYC             OCTOSPI_WPTCR_DCYC_Msk                  /*!< Number of Dummy Cycles */

+#define OCTOSPI_WPTCR_DHQC_Pos         (28U)

+#define OCTOSPI_WPTCR_DHQC_Msk         (0x1UL << OCTOSPI_WPTCR_DHQC_Pos)        /*!< 0x10000000 */

+#define OCTOSPI_WPTCR_DHQC             OCTOSPI_WPTCR_DHQC_Msk                  /*!< Delay Hold Quarter Cycle */

+#define OCTOSPI_WPTCR_SSHIFT_Pos       (30U)

+#define OCTOSPI_WPTCR_SSHIFT_Msk       (0x1UL << OCTOSPI_WPTCR_SSHIFT_Pos)      /*!< 0x40000000 */

+#define OCTOSPI_WPTCR_SSHIFT           OCTOSPI_WPTCR_SSHIFT_Msk                /*!< Sample Shift */

+

+/*****************  Bit definition for OCTOSPI_WPIR register  *******************/

+#define OCTOSPI_WPIR_INSTRUCTION_Pos   (0U)

+#define OCTOSPI_WPIR_INSTRUCTION_Msk   (0xFFFFFFFFUL << OCTOSPI_WPIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_WPIR_INSTRUCTION       OCTOSPI_WPIR_INSTRUCTION_Msk            /*!< Instruction */

+

+/****************  Bit definition for OCTOSPI_WPABR register  *******************/

+#define OCTOSPI_WPABR_ALTERNATE_Pos    (0U)

+#define OCTOSPI_WPABR_ALTERNATE_Msk    (0xFFFFFFFFUL << OCTOSPI_WPABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_WPABR_ALTERNATE        OCTOSPI_WPABR_ALTERNATE_Msk             /*!< Alternate Bytes */

+

+/****************  Bit definition for OCTOSPI_WCCR register  ******************/

+#define OCTOSPI_WCCR_IMODE_Pos         (0U)

+#define OCTOSPI_WCCR_IMODE_Msk         (0x7UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000007 */

+#define OCTOSPI_WCCR_IMODE             OCTOSPI_WCCR_IMODE_Msk                  /*!< Instruction Mode */

+#define OCTOSPI_WCCR_IMODE_0           (0x1UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000001 */

+#define OCTOSPI_WCCR_IMODE_1           (0x2UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000002 */

+#define OCTOSPI_WCCR_IMODE_2           (0x4UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000004 */

+#define OCTOSPI_WCCR_IDTR_Pos          (3U)

+#define OCTOSPI_WCCR_IDTR_Msk          (0x1UL << OCTOSPI_WCCR_IDTR_Pos)         /*!< 0x00000008 */

+#define OCTOSPI_WCCR_IDTR              OCTOSPI_WCCR_IDTR_Msk                   /*!< Instruction Double Transfer Rate */

+#define OCTOSPI_WCCR_ISIZE_Pos         (4U)

+#define OCTOSPI_WCCR_ISIZE_Msk         (0x3UL << OCTOSPI_WCCR_ISIZE_Pos)        /*!< 0x00000030 */

+#define OCTOSPI_WCCR_ISIZE             OCTOSPI_WCCR_ISIZE_Msk                  /*!< Instruction Size */

+#define OCTOSPI_WCCR_ISIZE_0           (0x1UL << OCTOSPI_WCCR_ISIZE_Pos)        /*!< 0x00000010 */

+#define OCTOSPI_WCCR_ISIZE_1           (0x2UL << OCTOSPI_WCCR_ISIZE_Pos)        /*!< 0x00000020 */

+#define OCTOSPI_WCCR_ADMODE_Pos        (8U)

+#define OCTOSPI_WCCR_ADMODE_Msk        (0x7UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000700 */

+#define OCTOSPI_WCCR_ADMODE            OCTOSPI_WCCR_ADMODE_Msk                 /*!< Address Mode */

+#define OCTOSPI_WCCR_ADMODE_0          (0x1UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000100 */

+#define OCTOSPI_WCCR_ADMODE_1          (0x2UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000200 */

+#define OCTOSPI_WCCR_ADMODE_2          (0x4UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000400 */

+#define OCTOSPI_WCCR_ADDTR_Pos         (11U)

+#define OCTOSPI_WCCR_ADDTR_Msk         (0x1UL << OCTOSPI_WCCR_ADDTR_Pos)        /*!< 0x00000800 */

+#define OCTOSPI_WCCR_ADDTR             OCTOSPI_WCCR_ADDTR_Msk                  /*!< Address Double Transfer Rate */

+#define OCTOSPI_WCCR_ADSIZE_Pos        (12U)

+#define OCTOSPI_WCCR_ADSIZE_Msk        (0x3UL << OCTOSPI_WCCR_ADSIZE_Pos)       /*!< 0x00003000 */

+#define OCTOSPI_WCCR_ADSIZE            OCTOSPI_WCCR_ADSIZE_Msk                 /*!< Address Size */

+#define OCTOSPI_WCCR_ADSIZE_0          (0x1UL << OCTOSPI_WCCR_ADSIZE_Pos)       /*!< 0x00001000 */

+#define OCTOSPI_WCCR_ADSIZE_1          (0x2UL << OCTOSPI_WCCR_ADSIZE_Pos)       /*!< 0x00002000 */

+#define OCTOSPI_WCCR_ABMODE_Pos        (16U)

+#define OCTOSPI_WCCR_ABMODE_Msk        (0x7UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00070000 */

+#define OCTOSPI_WCCR_ABMODE            OCTOSPI_WCCR_ABMODE_Msk                 /*!< Alternate Bytes Mode */

+#define OCTOSPI_WCCR_ABMODE_0          (0x1UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00010000 */

+#define OCTOSPI_WCCR_ABMODE_1          (0x2UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00020000 */

+#define OCTOSPI_WCCR_ABMODE_2          (0x4UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00040000 */

+#define OCTOSPI_WCCR_ABDTR_Pos         (19U)

+#define OCTOSPI_WCCR_ABDTR_Msk         (0x1UL << OCTOSPI_WCCR_ABDTR_Pos)        /*!< 0x00080000 */

+#define OCTOSPI_WCCR_ABDTR             OCTOSPI_WCCR_ABDTR_Msk                  /*!< Alternate Bytes Double Transfer Rate */

+#define OCTOSPI_WCCR_ABSIZE_Pos        (20U)

+#define OCTOSPI_WCCR_ABSIZE_Msk        (0x3UL << OCTOSPI_WCCR_ABSIZE_Pos)       /*!< 0x00300000 */

+#define OCTOSPI_WCCR_ABSIZE            OCTOSPI_WCCR_ABSIZE_Msk                 /*!< Alternate Bytes Size */

+#define OCTOSPI_WCCR_ABSIZE_0          (0x1UL << OCTOSPI_WCCR_ABSIZE_Pos)       /*!< 0x00100000 */

+#define OCTOSPI_WCCR_ABSIZE_1          (0x2UL << OCTOSPI_WCCR_ABSIZE_Pos)       /*!< 0x00200000 */

+#define OCTOSPI_WCCR_DMODE_Pos         (24U)

+#define OCTOSPI_WCCR_DMODE_Msk         (0x7UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x07000000 */

+#define OCTOSPI_WCCR_DMODE             OCTOSPI_WCCR_DMODE_Msk                  /*!< Data Mode */

+#define OCTOSPI_WCCR_DMODE_0           (0x1UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x01000000 */

+#define OCTOSPI_WCCR_DMODE_1           (0x2UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x02000000 */

+#define OCTOSPI_WCCR_DMODE_2           (0x4UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x04000000 */

+#define OCTOSPI_WCCR_DDTR_Pos          (27U)

+#define OCTOSPI_WCCR_DDTR_Msk          (0x1UL << OCTOSPI_WCCR_DDTR_Pos)         /*!< 0x08000000 */

+#define OCTOSPI_WCCR_DDTR              OCTOSPI_WCCR_DDTR_Msk                   /*!< Data Double Transfer Rate */

+#define OCTOSPI_WCCR_DQSE_Pos          (29U)

+#define OCTOSPI_WCCR_DQSE_Msk          (0x1UL << OCTOSPI_WCCR_DQSE_Pos)         /*!< 0x20000000 */

+#define OCTOSPI_WCCR_DQSE              OCTOSPI_WCCR_DQSE_Msk                   /*!< DQS Enable */

+#define OCTOSPI_WCCR_SIOO_Pos          (31U)

+#define OCTOSPI_WCCR_SIOO_Msk          (0x1UL << OCTOSPI_WCCR_SIOO_Pos)         /*!< 0x80000000 */

+#define OCTOSPI_WCCR_SIOO              OCTOSPI_WCCR_SIOO_Msk                   /*!< Send Instruction Only Once Mode */

+

+/****************  Bit definition for OCTOSPI_WTCR register  ******************/

+#define OCTOSPI_WTCR_DCYC_Pos          (0U)

+#define OCTOSPI_WTCR_DCYC_Msk          (0x1FUL << OCTOSPI_WTCR_DCYC_Pos)        /*!< 0x0000001F */

+#define OCTOSPI_WTCR_DCYC              OCTOSPI_WTCR_DCYC_Msk                   /*!< Number of Dummy Cycles */

+

+/****************  Bit definition for OCTOSPI_WIR register  *******************/

+#define OCTOSPI_WIR_INSTRUCTION_Pos    (0U)

+#define OCTOSPI_WIR_INSTRUCTION_Msk    (0xFFFFFFFFUL << OCTOSPI_WIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_WIR_INSTRUCTION        OCTOSPI_WIR_INSTRUCTION_Msk             /*!< Instruction */

+

+/****************  Bit definition for OCTOSPI_WABR register  ******************/

+#define OCTOSPI_WABR_ALTERNATE_Pos     (0U)

+#define OCTOSPI_WABR_ALTERNATE_Msk     (0xFFFFFFFFUL << OCTOSPI_WABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_WABR_ALTERNATE         OCTOSPI_WABR_ALTERNATE_Msk              /*!< Alternate Bytes */

+

+/****************  Bit definition for OCTOSPI_HLCR register  ******************/

+#define OCTOSPI_HLCR_LM_Pos            (0U)

+#define OCTOSPI_HLCR_LM_Msk            (0x1UL << OCTOSPI_HLCR_LM_Pos)           /*!< 0x00000001 */

+#define OCTOSPI_HLCR_LM                OCTOSPI_HLCR_LM_Msk                     /*!< Latency Mode */

+#define OCTOSPI_HLCR_WZL_Pos           (1U)

+#define OCTOSPI_HLCR_WZL_Msk           (0x1UL << OCTOSPI_HLCR_WZL_Pos)          /*!< 0x00000002 */

+#define OCTOSPI_HLCR_WZL               OCTOSPI_HLCR_WZL_Msk                    /*!< Write Zero Latency */

+#define OCTOSPI_HLCR_TACC_Pos          (8U)

+#define OCTOSPI_HLCR_TACC_Msk          (0xFFUL << OCTOSPI_HLCR_TACC_Pos)        /*!< 0x0000FF00 */

+#define OCTOSPI_HLCR_TACC              OCTOSPI_HLCR_TACC_Msk                   /*!< Access Time */

+#define OCTOSPI_HLCR_TRWR_Pos          (16U)

+#define OCTOSPI_HLCR_TRWR_Msk          (0xFFUL << OCTOSPI_HLCR_TRWR_Pos)        /*!< 0x00FF0000 */

+#define OCTOSPI_HLCR_TRWR              OCTOSPI_HLCR_TRWR_Msk                   /*!< Read Write Recovery Time */

+

+/****************  Bit definition for OCTOSPI_VER register  *******************/

+#define OCTOSPI_VER_VER_Pos            (0U)

+#define OCTOSPI_VER_VER_Msk            (0xFFUL << OCTOSPI_VER_VER_Pos)          /*!< 0x000000FF */

+#define OCTOSPI_VER_VER                OCTOSPI_VER_VER_Msk                     /*!< Version */

+

+/*****************  Bit definition for OCTOSPI_ID register  *******************/

+#define OCTOSPI_ID_ID_Pos              (0U)

+#define OCTOSPI_ID_ID_Msk              (0xFFFFFFFFUL << OCTOSPI_ID_ID_Pos)      /*!< 0xFFFFFFFF */

+#define OCTOSPI_ID_ID                  OCTOSPI_ID_ID_Msk                       /*!< Identification */

+

+/****************  Bit definition for OCTOSPI_MID register  *******************/

+#define OCTOSPI_MID_MID_Pos            (0U)

+#define OCTOSPI_MID_MID_Msk            (0xFFFFFFFFUL << OCTOSPI_MID_MID_Pos)    /*!< 0xFFFFFFFF */

+#define OCTOSPI_MID_MID                OCTOSPI_MID_MID_Msk                     /*!< Magic ID */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                  OCTOSPIM                                  */

+/*                                                                            */

+/******************************************************************************/

+

+/***************  Bit definition for OCTOSPIM_CR register  ********************/

+#define OCTOSPIM_CR_MUXEN_Pos          (0U)

+#define OCTOSPIM_CR_MUXEN_Msk          (0x1UL << OCTOSPIM_CR_MUXEN_Pos)        /*!< 0x00000001 */

+#define OCTOSPIM_CR_MUXEN              OCTOSPIM_CR_MUXEN_Msk                   /*!< Multiplexed mode enable */

+#define OCTOSPIM_CR_REQ2ACK_TIME_Pos   (16U)

+#define OCTOSPIM_CR_REQ2ACK_TIME_Msk   (0xFFUL << OCTOSPIM_CR_REQ2ACK_TIME_Pos)/*!< 0x00FF0000 */

+#define OCTOSPIM_CR_REQ2ACK_TIME       OCTOSPIM_CR_REQ2ACK_TIME_Msk            /*!< REQ to ACK time */

+

+/***************  Bit definition for OCTOSPIM_PCR register  *******************/

+#define OCTOSPIM_PCR_CLKEN_Pos         (0U)

+#define OCTOSPIM_PCR_CLKEN_Msk         (0x1UL << OCTOSPIM_PCR_CLKEN_Pos)        /*!< 0x00000001 */

+#define OCTOSPIM_PCR_CLKEN             OCTOSPIM_PCR_CLKEN_Msk                   /*!< CLK/CLKn Enable for Port n */

+#define OCTOSPIM_PCR_CLKSRC_Pos        (1U)

+#define OCTOSPIM_PCR_CLKSRC_Msk        (0x1UL << OCTOSPIM_PCR_CLKSRC_Pos)       /*!< 0x00000002 */

+#define OCTOSPIM_PCR_CLKSRC            OCTOSPIM_PCR_CLKSRC_Msk                  /*!< CLK/CLKn Source for Port n */

+#define OCTOSPIM_PCR_DQSEN_Pos         (4U)

+#define OCTOSPIM_PCR_DQSEN_Msk         (0x1UL << OCTOSPIM_PCR_DQSEN_Pos)        /*!< 0x00000010 */

+#define OCTOSPIM_PCR_DQSEN             OCTOSPIM_PCR_DQSEN_Msk                   /*!< DQS Enable for Port n */

+#define OCTOSPIM_PCR_DQSSRC_Pos        (5U)

+#define OCTOSPIM_PCR_DQSSRC_Msk        (0x1UL << OCTOSPIM_PCR_DQSSRC_Pos)       /*!< 0x00000020 */

+#define OCTOSPIM_PCR_DQSSRC            OCTOSPIM_PCR_DQSSRC_Msk                  /*!< DQS Source for Port n */

+#define OCTOSPIM_PCR_NCSEN_Pos         (8U)

+#define OCTOSPIM_PCR_NCSEN_Msk         (0x1UL << OCTOSPIM_PCR_NCSEN_Pos)        /*!< 0x00000100 */

+#define OCTOSPIM_PCR_NCSEN             OCTOSPIM_PCR_NCSEN_Msk                   /*!< nCS Enable for Port n */

+#define OCTOSPIM_PCR_NCSSRC_Pos        (9U)

+#define OCTOSPIM_PCR_NCSSRC_Msk        (0x1UL << OCTOSPIM_PCR_NCSSRC_Pos)       /*!< 0x00000200 */

+#define OCTOSPIM_PCR_NCSSRC            OCTOSPIM_PCR_NCSSRC_Msk                  /*!< nCS Source for Port n */

+#define OCTOSPIM_PCR_IOLEN_Pos         (16U)

+#define OCTOSPIM_PCR_IOLEN_Msk         (0x1UL << OCTOSPIM_PCR_IOLEN_Pos)        /*!< 0x00010000 */

+#define OCTOSPIM_PCR_IOLEN             OCTOSPIM_PCR_IOLEN_Msk                   /*!< IO[3:0] Enable for Port n */

+#define OCTOSPIM_PCR_IOLSRC_Pos        (17U)

+#define OCTOSPIM_PCR_IOLSRC_Msk        (0x3UL << OCTOSPIM_PCR_IOLSRC_Pos)       /*!< 0x00060000 */

+#define OCTOSPIM_PCR_IOLSRC            OCTOSPIM_PCR_IOLSRC_Msk                  /*!< IO[3:0] Source for Port n */

+#define OCTOSPIM_PCR_IOLSRC_0          (0x1UL << OCTOSPIM_PCR_IOLSRC_Pos)       /*!< 0x00020000 */

+#define OCTOSPIM_PCR_IOLSRC_1          (0x2UL << OCTOSPIM_PCR_IOLSRC_Pos)       /*!< 0x00040000 */

+#define OCTOSPIM_PCR_IOHEN_Pos         (24U)

+#define OCTOSPIM_PCR_IOHEN_Msk         (0x1UL << OCTOSPIM_PCR_IOHEN_Pos)        /*!< 0x01000000 */

+#define OCTOSPIM_PCR_IOHEN             OCTOSPIM_PCR_IOHEN_Msk                   /*!< IO[7:4] Enable for Port n */

+#define OCTOSPIM_PCR_IOHSRC_Pos        (25U)

+#define OCTOSPIM_PCR_IOHSRC_Msk        (0x3UL << OCTOSPIM_PCR_IOHSRC_Pos)       /*!< 0x06000000 */

+#define OCTOSPIM_PCR_IOHSRC            OCTOSPIM_PCR_IOHSRC_Msk                  /*!< IO[7:4] Source for Port n */

+#define OCTOSPIM_PCR_IOHSRC_0          (0x1UL << OCTOSPIM_PCR_IOHSRC_Pos)       /*!< 0x02000000 */

+#define OCTOSPIM_PCR_IOHSRC_1          (0x2UL << OCTOSPIM_PCR_IOHSRC_Pos)       /*!< 0x04000000 */

+/******************************************************************************/

+/*                                                                            */

+/*                      Analog Comparators (COMP)                             */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for COMP_SR register  ********************/

+#define COMP_SR_C1VAL_Pos            (0U)

+#define COMP_SR_C1VAL_Msk            (0x1UL << COMP_SR_C1VAL_Pos)              /*!< 0x00000001 */

+#define COMP_SR_C1VAL                COMP_SR_C1VAL_Msk

+#define COMP_SR_C2VAL_Pos            (1U)

+#define COMP_SR_C2VAL_Msk            (0x1UL << COMP_SR_C2VAL_Pos)              /*!< 0x00000002 */

+#define COMP_SR_C2VAL                COMP_SR_C2VAL_Msk

+#define COMP_SR_C1IF_Pos             (16U)

+#define COMP_SR_C1IF_Msk             (0x1UL << COMP_SR_C1IF_Pos)               /*!< 0x00010000 */

+#define COMP_SR_C1IF                 COMP_SR_C1IF_Msk

+#define COMP_SR_C2IF_Pos             (17U)

+#define COMP_SR_C2IF_Msk             (0x1UL << COMP_SR_C2IF_Pos)               /*!< 0x00020000 */

+#define COMP_SR_C2IF                 COMP_SR_C2IF_Msk

+/*******************  Bit definition for COMP_ICFR register  ********************/

+#define COMP_ICFR_C1IF_Pos           (16U)

+#define COMP_ICFR_C1IF_Msk           (0x1UL << COMP_ICFR_C1IF_Pos)             /*!< 0x00010000 */

+#define COMP_ICFR_C1IF               COMP_ICFR_C1IF_Msk

+#define COMP_ICFR_C2IF_Pos           (17U)

+#define COMP_ICFR_C2IF_Msk           (0x1UL << COMP_ICFR_C2IF_Pos)             /*!< 0x00020000 */

+#define COMP_ICFR_C2IF               COMP_ICFR_C2IF_Msk

+/*******************  Bit definition for COMP_OR register  ********************/

+#define COMP_OR_AFOPA6_Pos           (0U)

+#define COMP_OR_AFOPA6_Msk           (0x1UL << COMP_OR_AFOPA6_Pos)             /*!< 0x00000001 */

+#define COMP_OR_AFOPA6               COMP_OR_AFOPA6_Msk

+#define COMP_OR_AFOPA8_Pos           (1U)

+#define COMP_OR_AFOPA8_Msk           (0x1UL << COMP_OR_AFOPA8_Pos)             /*!< 0x00000002 */

+#define COMP_OR_AFOPA8               COMP_OR_AFOPA8_Msk

+#define COMP_OR_AFOPB12_Pos          (2U)

+#define COMP_OR_AFOPB12_Msk          (0x1UL << COMP_OR_AFOPB12_Pos)            /*!< 0x00000004 */

+#define COMP_OR_AFOPB12              COMP_OR_AFOPB12_Msk

+#define COMP_OR_AFOPE6_Pos           (3U)

+#define COMP_OR_AFOPE6_Msk           (0x1UL << COMP_OR_AFOPE6_Pos)             /*!< 0x00000008 */

+#define COMP_OR_AFOPE6               COMP_OR_AFOPE6_Msk

+#define COMP_OR_AFOPE15_Pos          (4U)

+#define COMP_OR_AFOPE15_Msk          (0x1UL << COMP_OR_AFOPE15_Pos)            /*!< 0x00000010 */

+#define COMP_OR_AFOPE15              COMP_OR_AFOPE15_Msk

+#define COMP_OR_AFOPG2_Pos           (5U)

+#define COMP_OR_AFOPG2_Msk           (0x1UL << COMP_OR_AFOPG2_Pos)             /*!< 0x00000020 */

+#define COMP_OR_AFOPG2               COMP_OR_AFOPG2_Msk

+#define COMP_OR_AFOPG3_Pos           (6U)

+#define COMP_OR_AFOPG3_Msk           (0x1UL << COMP_OR_AFOPG3_Pos)             /*!< 0x00000040 */

+#define COMP_OR_AFOPG3               COMP_OR_AFOPG3_Msk

+#define COMP_OR_AFOPG4_Pos           (7U)

+#define COMP_OR_AFOPG4_Msk           (0x1UL << COMP_OR_AFOPG4_Pos)             /*!< 0x00000080 */

+#define COMP_OR_AFOPG4               COMP_OR_AFOPG4_Msk

+#define COMP_OR_AFOPI1_Pos           (8U)

+#define COMP_OR_AFOPI1_Msk           (0x1UL << COMP_OR_AFOPI1_Pos)             /*!< 0x00000100 */

+#define COMP_OR_AFOPI1               COMP_OR_AFOPI1_Msk

+#define COMP_OR_AFOPI4_Pos           (9U)

+#define COMP_OR_AFOPI4_Msk           (0x1UL << COMP_OR_AFOPI4_Pos)             /*!< 0x00000200 */

+#define COMP_OR_AFOPI4               COMP_OR_AFOPI4_Msk

+#define COMP_OR_AFOPK2_Pos           (10U)

+#define COMP_OR_AFOPK2_Msk           (0x1UL << COMP_OR_AFOPK2_Pos)             /*!< 0x00000400 */

+#define COMP_OR_AFOPK2               COMP_OR_AFOPK2_Msk

+

+/*!< ******************  Bit definition for COMP_CFGRx register  ********************/

+#define COMP_CFGRx_EN_Pos            (0U)

+#define COMP_CFGRx_EN_Msk            (0x1UL << COMP_CFGRx_EN_Pos)              /*!< 0x00000001 */

+#define COMP_CFGRx_EN                COMP_CFGRx_EN_Msk                         /*!< COMPx enable bit                     */

+#define COMP_CFGRx_BRGEN_Pos         (1U)

+#define COMP_CFGRx_BRGEN_Msk         (0x1UL << COMP_CFGRx_BRGEN_Pos)           /*!< 0x00000002 */

+#define COMP_CFGRx_BRGEN             COMP_CFGRx_BRGEN_Msk                      /*!< COMPx Scaler bridge enable           */

+#define COMP_CFGRx_SCALEN_Pos        (2U)

+#define COMP_CFGRx_SCALEN_Msk        (0x1UL << COMP_CFGRx_SCALEN_Pos)          /*!< 0x00000004 */

+#define COMP_CFGRx_SCALEN            COMP_CFGRx_SCALEN_Msk                     /*!< COMPx Voltage scaler enable bit      */

+#define COMP_CFGRx_POLARITY_Pos      (3U)

+#define COMP_CFGRx_POLARITY_Msk      (0x1UL << COMP_CFGRx_POLARITY_Pos)        /*!< 0x00000008 */

+#define COMP_CFGRx_POLARITY          COMP_CFGRx_POLARITY_Msk                   /*!< COMPx  polarity selection bit        */

+#define COMP_CFGRx_WINMODE_Pos       (4U)

+#define COMP_CFGRx_WINMODE_Msk       (0x1UL << COMP_CFGRx_WINMODE_Pos)         /*!< 0x00000010 */

+#define COMP_CFGRx_WINMODE           COMP_CFGRx_WINMODE_Msk                    /*!< COMPx Windows mode selection bit     */

+#define COMP_CFGRx_ITEN_Pos          (6U)

+#define COMP_CFGRx_ITEN_Msk          (0x1UL << COMP_CFGRx_ITEN_Pos)            /*!< 0x00000040 */

+#define COMP_CFGRx_ITEN              COMP_CFGRx_ITEN_Msk                       /*!< COMPx  interrupt enable              */

+#define COMP_CFGRx_HYST_Pos          (8U)

+#define COMP_CFGRx_HYST_Msk          (0x3UL << COMP_CFGRx_HYST_Pos)            /*!< 0x00000300 */

+#define COMP_CFGRx_HYST              COMP_CFGRx_HYST_Msk                       /*!< COMPx  hysteresis selection bits     */

+#define COMP_CFGRx_HYST_0            (0x1UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000100 */

+#define COMP_CFGRx_HYST_1            (0x2UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000200 */

+#define COMP_CFGRx_PWRMODE_Pos       (12U)

+#define COMP_CFGRx_PWRMODE_Msk       (0x3UL << COMP_CFGRx_PWRMODE_Pos)         /*!< 0x00003000 */

+#define COMP_CFGRx_PWRMODE           COMP_CFGRx_PWRMODE_Msk                    /*!< COMPx Power Mode of the comparator   */

+#define COMP_CFGRx_PWRMODE_0         (0x1UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00001000 */

+#define COMP_CFGRx_PWRMODE_1         (0x2UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00002000 */

+#define COMP_CFGRx_INMSEL_Pos        (16U)

+#define COMP_CFGRx_INMSEL_Msk        (0xFUL << COMP_CFGRx_INMSEL_Pos)          /*!< 0x000F0000 */

+#define COMP_CFGRx_INMSEL            COMP_CFGRx_INMSEL_Msk                     /*!< COMPx  input minus selection bit  */

+#define COMP_CFGRx_INMSEL_0          (0x1UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00010000 */

+#define COMP_CFGRx_INMSEL_1          (0x2UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00020000 */

+#define COMP_CFGRx_INMSEL_2          (0x4UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00040000 */

+#define COMP_CFGRx_INMSEL_3          (0x8UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00080000 */

+#define COMP_CFGRx_INPSEL_Pos        (20U)

+#define COMP_CFGRx_INPSEL_Msk        (0x1UL << COMP_CFGRx_INPSEL_Pos)          /*!< 0x00100000 */

+#define COMP_CFGRx_INPSEL            COMP_CFGRx_INPSEL_Msk                     /*!< COMPx  input plus selection bit       */

+#define COMP_CFGRx_INP2SEL_Pos        (22U)

+#define COMP_CFGRx_INP2SEL_Msk        (0x1UL << COMP_CFGRx_INP2SEL_Pos)        /*!< 0x00400000 */

+#define COMP_CFGRx_INP2SEL            COMP_CFGRx_INP2SEL_Msk                   /*!< COMPx  input plus 2 selection bit     */

+#define COMP_CFGRx_BLANKING_Pos      (24U)

+#define COMP_CFGRx_BLANKING_Msk      (0xFUL << COMP_CFGRx_BLANKING_Pos)        /*!< 0x0F000000 */

+#define COMP_CFGRx_BLANKING          COMP_CFGRx_BLANKING_Msk                   /*!< COMPx  blanking source selection bits */

+#define COMP_CFGRx_BLANKING_0        (0x1UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x01000000 */

+#define COMP_CFGRx_BLANKING_1        (0x2UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x02000000 */

+#define COMP_CFGRx_BLANKING_2        (0x4UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x04000000 */

+#define COMP_CFGRx_LOCK_Pos          (31U)

+#define COMP_CFGRx_LOCK_Msk          (0x1UL << COMP_CFGRx_LOCK_Pos)            /*!< 0x80000000 */

+#define COMP_CFGRx_LOCK              COMP_CFGRx_LOCK_Msk                       /*!< COMPx Lock Bit                        */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for USART_CR1 register  *******************/

+#define USART_CR1_UE_Pos                (0U)

+#define USART_CR1_UE_Msk                (0x1UL << USART_CR1_UE_Pos)            /*!< 0x00000001 */

+#define USART_CR1_UE                    USART_CR1_UE_Msk                       /*!< USART Enable */

+#define USART_CR1_UESM_Pos              (1U)

+#define USART_CR1_UESM_Msk              (0x1UL << USART_CR1_UESM_Pos)          /*!< 0x00000002 */

+#define USART_CR1_UESM                  USART_CR1_UESM_Msk                     /*!< USART Enable in STOP Mode */

+#define USART_CR1_RE_Pos                (2U)

+#define USART_CR1_RE_Msk                (0x1UL << USART_CR1_RE_Pos)            /*!< 0x00000004 */

+#define USART_CR1_RE                    USART_CR1_RE_Msk                       /*!< Receiver Enable */

+#define USART_CR1_TE_Pos                (3U)

+#define USART_CR1_TE_Msk                (0x1UL << USART_CR1_TE_Pos)            /*!< 0x00000008 */

+#define USART_CR1_TE                    USART_CR1_TE_Msk                       /*!< Transmitter Enable */

+#define USART_CR1_IDLEIE_Pos            (4U)

+#define USART_CR1_IDLEIE_Msk            (0x1UL << USART_CR1_IDLEIE_Pos)        /*!< 0x00000010 */

+#define USART_CR1_IDLEIE                USART_CR1_IDLEIE_Msk                   /*!< IDLE Interrupt Enable */

+#define USART_CR1_RXNEIE_RXFNEIE_Pos    (5U)

+#define USART_CR1_RXNEIE_RXFNEIE_Msk    (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */

+#define USART_CR1_RXNEIE_RXFNEIE        USART_CR1_RXNEIE_RXFNEIE_Msk           /*!< RXNE and RX FIFO Not Empty Interrupt Enable */

+#define USART_CR1_TCIE_Pos              (6U)

+#define USART_CR1_TCIE_Msk              (0x1UL << USART_CR1_TCIE_Pos)          /*!< 0x00000040 */

+#define USART_CR1_TCIE                  USART_CR1_TCIE_Msk                     /*!< Transmission Complete Interrupt Enable */

+#define USART_CR1_TXEIE_TXFNFIE_Pos     (7U)

+#define USART_CR1_TXEIE_TXFNFIE_Msk     (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */

+#define USART_CR1_TXEIE_TXFNFIE         USART_CR1_TXEIE_TXFNFIE_Msk            /*!< TXE and TX FIFO Not Full Interrupt Enable */

+#define USART_CR1_PEIE_Pos              (8U)

+#define USART_CR1_PEIE_Msk              (0x1UL << USART_CR1_PEIE_Pos)          /*!< 0x00000100 */

+#define USART_CR1_PEIE                  USART_CR1_PEIE_Msk                     /*!< PE Interrupt Enable */

+#define USART_CR1_PS_Pos                (9U)

+#define USART_CR1_PS_Msk                (0x1UL << USART_CR1_PS_Pos)            /*!< 0x00000200 */

+#define USART_CR1_PS                    USART_CR1_PS_Msk                       /*!< Parity Selection */

+#define USART_CR1_PCE_Pos               (10U)

+#define USART_CR1_PCE_Msk               (0x1UL << USART_CR1_PCE_Pos)           /*!< 0x00000400 */

+#define USART_CR1_PCE                   USART_CR1_PCE_Msk                      /*!< Parity Control Enable */

+#define USART_CR1_WAKE_Pos              (11U)

+#define USART_CR1_WAKE_Msk              (0x1UL << USART_CR1_WAKE_Pos)          /*!< 0x00000800 */

+#define USART_CR1_WAKE                  USART_CR1_WAKE_Msk                     /*!< Receiver Wakeup method */

+#define USART_CR1_M_Pos                 (12U)

+#define USART_CR1_M_Msk                 (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */

+#define USART_CR1_M                     USART_CR1_M_Msk                        /*!< Word length */

+#define USART_CR1_M0_Pos                (12U)

+#define USART_CR1_M0_Msk                (0x1UL << USART_CR1_M0_Pos)            /*!< 0x00001000 */

+#define USART_CR1_M0                    USART_CR1_M0_Msk                       /*!< Word length - Bit 0 */

+#define USART_CR1_MME_Pos               (13U)

+#define USART_CR1_MME_Msk               (0x1UL << USART_CR1_MME_Pos)           /*!< 0x00002000 */

+#define USART_CR1_MME                   USART_CR1_MME_Msk                      /*!< Mute Mode Enable */

+#define USART_CR1_CMIE_Pos              (14U)

+#define USART_CR1_CMIE_Msk              (0x1UL << USART_CR1_CMIE_Pos)          /*!< 0x00004000 */

+#define USART_CR1_CMIE                  USART_CR1_CMIE_Msk                     /*!< Character match interrupt enable */

+#define USART_CR1_OVER8_Pos             (15U)

+#define USART_CR1_OVER8_Msk             (0x1UL << USART_CR1_OVER8_Pos)         /*!< 0x00008000 */

+#define USART_CR1_OVER8                 USART_CR1_OVER8_Msk                    /*!< Oversampling by 8-bit or 16-bit mode */

+#define USART_CR1_DEDT_Pos              (16U)

+#define USART_CR1_DEDT_Msk              (0x1FUL << USART_CR1_DEDT_Pos)         /*!< 0x001F0000 */

+#define USART_CR1_DEDT                  USART_CR1_DEDT_Msk                     /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */

+#define USART_CR1_DEDT_0                (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */

+#define USART_CR1_DEDT_1                (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */

+#define USART_CR1_DEDT_2                (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */

+#define USART_CR1_DEDT_3                (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */

+#define USART_CR1_DEDT_4                (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */

+#define USART_CR1_DEAT_Pos              (21U)

+#define USART_CR1_DEAT_Msk              (0x1FUL << USART_CR1_DEAT_Pos)         /*!< 0x03E00000 */

+#define USART_CR1_DEAT                  USART_CR1_DEAT_Msk                     /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */

+#define USART_CR1_DEAT_0                (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */

+#define USART_CR1_DEAT_1                (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */

+#define USART_CR1_DEAT_2                (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */

+#define USART_CR1_DEAT_3                (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */

+#define USART_CR1_DEAT_4                (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */

+#define USART_CR1_RTOIE_Pos             (26U)

+#define USART_CR1_RTOIE_Msk             (0x1UL << USART_CR1_RTOIE_Pos)         /*!< 0x04000000 */

+#define USART_CR1_RTOIE                 USART_CR1_RTOIE_Msk                    /*!< Receive Time Out interrupt enable */

+#define USART_CR1_EOBIE_Pos             (27U)

+#define USART_CR1_EOBIE_Msk             (0x1UL << USART_CR1_EOBIE_Pos)         /*!< 0x08000000 */

+#define USART_CR1_EOBIE                 USART_CR1_EOBIE_Msk                    /*!< End of Block interrupt enable */

+#define USART_CR1_M1_Pos                (28U)

+#define USART_CR1_M1_Msk                (0x1UL << USART_CR1_M1_Pos)            /*!< 0x10000000 */

+#define USART_CR1_M1                    USART_CR1_M1_Msk                       /*!< Word length - Bit 1 */

+#define USART_CR1_FIFOEN_Pos            (29U)

+#define USART_CR1_FIFOEN_Msk            (0x1UL << USART_CR1_FIFOEN_Pos)        /*!< 0x20000000 */

+#define USART_CR1_FIFOEN                USART_CR1_FIFOEN_Msk                   /*!< FIFO mode enable */

+#define USART_CR1_TXFEIE_Pos            (30U)

+#define USART_CR1_TXFEIE_Msk            (0x1UL << USART_CR1_TXFEIE_Pos)        /*!< 0x40000000 */

+#define USART_CR1_TXFEIE                USART_CR1_TXFEIE_Msk                   /*!< TXFIFO empty interrupt enable */

+#define USART_CR1_RXFFIE_Pos            (31U)

+#define USART_CR1_RXFFIE_Msk            (0x1UL << USART_CR1_RXFFIE_Pos)        /*!< 0x80000000 */

+#define USART_CR1_RXFFIE                USART_CR1_RXFFIE_Msk                   /*!< RXFIFO Full interrupt enable */

+

+/* Legacy define */

+#define  USART_CR1_RXNEIE  USART_CR1_RXNEIE_RXFNEIE

+#define  USART_CR1_TXEIE   USART_CR1_TXEIE_TXFNFIE

+

+/******************  Bit definition for USART_CR2 register  *******************/

+#define USART_CR2_SLVEN_Pos             (0U)

+#define USART_CR2_SLVEN_Msk             (0x1UL << USART_CR2_SLVEN_Pos)         /*!< 0x00000001 */

+#define USART_CR2_SLVEN                 USART_CR2_SLVEN_Msk                    /*!< Synchronous Slave mode Enable */

+#define USART_CR2_DIS_NSS_Pos           (3U)

+#define USART_CR2_DIS_NSS_Msk           (0x1UL << USART_CR2_DIS_NSS_Pos)       /*!< 0x00000008 */

+#define USART_CR2_DIS_NSS               USART_CR2_DIS_NSS_Msk                  /*!< Negative Slave Select (NSS) pin management */

+#define USART_CR2_ADDM7_Pos             (4U)

+#define USART_CR2_ADDM7_Msk             (0x1UL << USART_CR2_ADDM7_Pos)         /*!< 0x00000010 */

+#define USART_CR2_ADDM7                 USART_CR2_ADDM7_Msk                    /*!< 7-bit or 4-bit Address Detection */

+#define USART_CR2_LBDL_Pos              (5U)

+#define USART_CR2_LBDL_Msk              (0x1UL << USART_CR2_LBDL_Pos)          /*!< 0x00000020 */

+#define USART_CR2_LBDL                  USART_CR2_LBDL_Msk                     /*!< LIN Break Detection Length */

+#define USART_CR2_LBDIE_Pos             (6U)

+#define USART_CR2_LBDIE_Msk             (0x1UL << USART_CR2_LBDIE_Pos)         /*!< 0x00000040 */

+#define USART_CR2_LBDIE                 USART_CR2_LBDIE_Msk                    /*!< LIN Break Detection Interrupt Enable */

+#define USART_CR2_LBCL_Pos              (8U)

+#define USART_CR2_LBCL_Msk              (0x1UL << USART_CR2_LBCL_Pos)          /*!< 0x00000100 */

+#define USART_CR2_LBCL                  USART_CR2_LBCL_Msk                     /*!< Last Bit Clock pulse */

+#define USART_CR2_CPHA_Pos              (9U)

+#define USART_CR2_CPHA_Msk              (0x1UL << USART_CR2_CPHA_Pos)          /*!< 0x00000200 */

+#define USART_CR2_CPHA                  USART_CR2_CPHA_Msk                     /*!< Clock Phase */

+#define USART_CR2_CPOL_Pos              (10U)

+#define USART_CR2_CPOL_Msk              (0x1UL << USART_CR2_CPOL_Pos)          /*!< 0x00000400 */

+#define USART_CR2_CPOL                  USART_CR2_CPOL_Msk                     /*!< Clock Polarity */

+#define USART_CR2_CLKEN_Pos             (11U)

+#define USART_CR2_CLKEN_Msk             (0x1UL << USART_CR2_CLKEN_Pos)         /*!< 0x00000800 */

+#define USART_CR2_CLKEN                 USART_CR2_CLKEN_Msk                    /*!< Clock Enable */

+#define USART_CR2_STOP_Pos              (12U)

+#define USART_CR2_STOP_Msk              (0x3UL << USART_CR2_STOP_Pos)          /*!< 0x00003000 */

+#define USART_CR2_STOP                  USART_CR2_STOP_Msk                     /*!< STOP[1:0] bits (STOP bits) */

+#define USART_CR2_STOP_0                (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */

+#define USART_CR2_STOP_1                (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */

+#define USART_CR2_LINEN_Pos             (14U)

+#define USART_CR2_LINEN_Msk             (0x1UL << USART_CR2_LINEN_Pos)         /*!< 0x00004000 */

+#define USART_CR2_LINEN                 USART_CR2_LINEN_Msk                    /*!< LIN mode enable */

+#define USART_CR2_SWAP_Pos              (15U)

+#define USART_CR2_SWAP_Msk              (0x1UL << USART_CR2_SWAP_Pos)          /*!< 0x00008000 */

+#define USART_CR2_SWAP                  USART_CR2_SWAP_Msk                     /*!< SWAP TX/RX pins */

+#define USART_CR2_RXINV_Pos             (16U)

+#define USART_CR2_RXINV_Msk             (0x1UL << USART_CR2_RXINV_Pos)         /*!< 0x00010000 */

+#define USART_CR2_RXINV                 USART_CR2_RXINV_Msk                    /*!< RX pin active level inversion */

+#define USART_CR2_TXINV_Pos             (17U)

+#define USART_CR2_TXINV_Msk             (0x1UL << USART_CR2_TXINV_Pos)         /*!< 0x00020000 */

+#define USART_CR2_TXINV                 USART_CR2_TXINV_Msk                    /*!< TX pin active level inversion */

+#define USART_CR2_DATAINV_Pos           (18U)

+#define USART_CR2_DATAINV_Msk           (0x1UL << USART_CR2_DATAINV_Pos)       /*!< 0x00040000 */

+#define USART_CR2_DATAINV               USART_CR2_DATAINV_Msk                  /*!< Binary data inversion */

+#define USART_CR2_MSBFIRST_Pos          (19U)

+#define USART_CR2_MSBFIRST_Msk          (0x1UL << USART_CR2_MSBFIRST_Pos)      /*!< 0x00080000 */

+#define USART_CR2_MSBFIRST              USART_CR2_MSBFIRST_Msk                 /*!< Most Significant Bit First */

+#define USART_CR2_ABREN_Pos             (20U)

+#define USART_CR2_ABREN_Msk             (0x1UL << USART_CR2_ABREN_Pos)         /*!< 0x00100000 */

+#define USART_CR2_ABREN                 USART_CR2_ABREN_Msk                    /*!< Auto Baud-Rate Enable*/

+#define USART_CR2_ABRMODE_Pos           (21U)

+#define USART_CR2_ABRMODE_Msk           (0x3UL << USART_CR2_ABRMODE_Pos)       /*!< 0x00600000 */

+#define USART_CR2_ABRMODE               USART_CR2_ABRMODE_Msk                  /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */

+#define USART_CR2_ABRMODE_0             (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */

+#define USART_CR2_ABRMODE_1             (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */

+#define USART_CR2_RTOEN_Pos             (23U)

+#define USART_CR2_RTOEN_Msk             (0x1UL << USART_CR2_RTOEN_Pos)         /*!< 0x00800000 */

+#define USART_CR2_RTOEN                 USART_CR2_RTOEN_Msk                    /*!< Receiver Time-Out enable */

+#define USART_CR2_ADD_Pos               (24U)

+#define USART_CR2_ADD_Msk               (0xFFUL << USART_CR2_ADD_Pos)          /*!< 0xFF000000 */

+#define USART_CR2_ADD                   USART_CR2_ADD_Msk                      /*!< Address of the USART node */

+

+/******************  Bit definition for USART_CR3 register  *******************/

+#define USART_CR3_EIE_Pos               (0U)

+#define USART_CR3_EIE_Msk               (0x1UL << USART_CR3_EIE_Pos)           /*!< 0x00000001 */

+#define USART_CR3_EIE                   USART_CR3_EIE_Msk                      /*!< Error Interrupt Enable */

+#define USART_CR3_IREN_Pos              (1U)

+#define USART_CR3_IREN_Msk              (0x1UL << USART_CR3_IREN_Pos)          /*!< 0x00000002 */

+#define USART_CR3_IREN                  USART_CR3_IREN_Msk                     /*!< IrDA mode Enable */

+#define USART_CR3_IRLP_Pos              (2U)

+#define USART_CR3_IRLP_Msk              (0x1UL << USART_CR3_IRLP_Pos)          /*!< 0x00000004 */

+#define USART_CR3_IRLP                  USART_CR3_IRLP_Msk                     /*!< IrDA Low-Power */

+#define USART_CR3_HDSEL_Pos             (3U)

+#define USART_CR3_HDSEL_Msk             (0x1UL << USART_CR3_HDSEL_Pos)         /*!< 0x00000008 */

+#define USART_CR3_HDSEL                 USART_CR3_HDSEL_Msk                    /*!< Half-Duplex Selection */

+#define USART_CR3_NACK_Pos              (4U)

+#define USART_CR3_NACK_Msk              (0x1UL << USART_CR3_NACK_Pos)          /*!< 0x00000010 */

+#define USART_CR3_NACK                  USART_CR3_NACK_Msk                     /*!< SmartCard NACK enable */

+#define USART_CR3_SCEN_Pos              (5U)

+#define USART_CR3_SCEN_Msk              (0x1UL << USART_CR3_SCEN_Pos)          /*!< 0x00000020 */

+#define USART_CR3_SCEN                  USART_CR3_SCEN_Msk                     /*!< SmartCard mode enable */

+#define USART_CR3_DMAR_Pos              (6U)

+#define USART_CR3_DMAR_Msk              (0x1UL << USART_CR3_DMAR_Pos)          /*!< 0x00000040 */

+#define USART_CR3_DMAR                  USART_CR3_DMAR_Msk                     /*!< DMA Enable Receiver */

+#define USART_CR3_DMAT_Pos              (7U)

+#define USART_CR3_DMAT_Msk              (0x1UL << USART_CR3_DMAT_Pos)          /*!< 0x00000080 */

+#define USART_CR3_DMAT                  USART_CR3_DMAT_Msk                     /*!< DMA Enable Transmitter */

+#define USART_CR3_RTSE_Pos              (8U)

+#define USART_CR3_RTSE_Msk              (0x1UL << USART_CR3_RTSE_Pos)          /*!< 0x00000100 */

+#define USART_CR3_RTSE                  USART_CR3_RTSE_Msk                     /*!< RTS Enable */

+#define USART_CR3_CTSE_Pos              (9U)

+#define USART_CR3_CTSE_Msk              (0x1UL << USART_CR3_CTSE_Pos)          /*!< 0x00000200 */

+#define USART_CR3_CTSE                  USART_CR3_CTSE_Msk                     /*!< CTS Enable */

+#define USART_CR3_CTSIE_Pos             (10U)

+#define USART_CR3_CTSIE_Msk             (0x1UL << USART_CR3_CTSIE_Pos)         /*!< 0x00000400 */

+#define USART_CR3_CTSIE                 USART_CR3_CTSIE_Msk                    /*!< CTS Interrupt Enable */

+#define USART_CR3_ONEBIT_Pos            (11U)

+#define USART_CR3_ONEBIT_Msk            (0x1UL << USART_CR3_ONEBIT_Pos)        /*!< 0x00000800 */

+#define USART_CR3_ONEBIT                USART_CR3_ONEBIT_Msk                   /*!< One sample bit method enable */

+#define USART_CR3_OVRDIS_Pos            (12U)

+#define USART_CR3_OVRDIS_Msk            (0x1UL << USART_CR3_OVRDIS_Pos)        /*!< 0x00001000 */

+#define USART_CR3_OVRDIS                USART_CR3_OVRDIS_Msk                   /*!< Overrun Disable */

+#define USART_CR3_DDRE_Pos              (13U)

+#define USART_CR3_DDRE_Msk              (0x1UL << USART_CR3_DDRE_Pos)          /*!< 0x00002000 */

+#define USART_CR3_DDRE                  USART_CR3_DDRE_Msk                     /*!< DMA Disable on Reception Error */

+#define USART_CR3_DEM_Pos               (14U)

+#define USART_CR3_DEM_Msk               (0x1UL << USART_CR3_DEM_Pos)           /*!< 0x00004000 */

+#define USART_CR3_DEM                   USART_CR3_DEM_Msk                      /*!< Driver Enable Mode */

+#define USART_CR3_DEP_Pos               (15U)

+#define USART_CR3_DEP_Msk               (0x1UL << USART_CR3_DEP_Pos)           /*!< 0x00008000 */

+#define USART_CR3_DEP                   USART_CR3_DEP_Msk                      /*!< Driver Enable Polarity Selection */

+#define USART_CR3_SCARCNT_Pos           (17U)

+#define USART_CR3_SCARCNT_Msk           (0x7UL << USART_CR3_SCARCNT_Pos)       /*!< 0x000E0000 */

+#define USART_CR3_SCARCNT               USART_CR3_SCARCNT_Msk                  /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */

+#define USART_CR3_SCARCNT_0             (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */

+#define USART_CR3_SCARCNT_1             (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */

+#define USART_CR3_SCARCNT_2             (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */

+#define USART_CR3_WUS_Pos               (20U)

+#define USART_CR3_WUS_Msk               (0x3UL << USART_CR3_WUS_Pos)           /*!< 0x00300000 */

+#define USART_CR3_WUS                   USART_CR3_WUS_Msk                      /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */

+#define USART_CR3_WUS_0                 (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */

+#define USART_CR3_WUS_1                 (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */

+#define USART_CR3_WUFIE_Pos             (22U)

+#define USART_CR3_WUFIE_Msk             (0x1UL << USART_CR3_WUFIE_Pos)         /*!< 0x00400000 */

+#define USART_CR3_WUFIE                 USART_CR3_WUFIE_Msk                    /*!< Wake Up Interrupt Enable */

+#define USART_CR3_TXFTIE_Pos            (23U)

+#define USART_CR3_TXFTIE_Msk            (0x1UL << USART_CR3_TXFTIE_Pos)        /*!< 0x00800000 */

+#define USART_CR3_TXFTIE                USART_CR3_TXFTIE_Msk                   /*!< TXFIFO threshold interrupt enable */

+#define USART_CR3_TCBGTIE_Pos           (24U)

+#define USART_CR3_TCBGTIE_Msk           (0x1UL << USART_CR3_TCBGTIE_Pos)       /*!< 0x01000000 */

+#define USART_CR3_TCBGTIE               USART_CR3_TCBGTIE_Msk                  /*!< Transmission Complete before guard time, interrupt enable */

+#define USART_CR3_RXFTCFG_Pos           (25U)

+#define USART_CR3_RXFTCFG_Msk           (0x7UL << USART_CR3_RXFTCFG_Pos)       /*!< 0x0E000000 */

+#define USART_CR3_RXFTCFG               USART_CR3_RXFTCFG_Msk                  /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */

+#define USART_CR3_RXFTCFG_0             (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */

+#define USART_CR3_RXFTCFG_1             (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */

+#define USART_CR3_RXFTCFG_2             (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */

+#define USART_CR3_RXFTIE_Pos            (28U)

+#define USART_CR3_RXFTIE_Msk            (0x1UL << USART_CR3_RXFTIE_Pos)        /*!< 0x10000000 */

+#define USART_CR3_RXFTIE                USART_CR3_RXFTIE_Msk                   /*!< RXFIFO threshold interrupt enable */

+#define USART_CR3_TXFTCFG_Pos           (29U)

+#define USART_CR3_TXFTCFG_Msk           (0x7UL << USART_CR3_TXFTCFG_Pos)       /*!< 0xE0000000 */

+#define USART_CR3_TXFTCFG               USART_CR3_TXFTCFG_Msk                  /*!< TXFIFO [2:0] threshold configuration */

+#define USART_CR3_TXFTCFG_0             (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */

+#define USART_CR3_TXFTCFG_1             (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */

+#define USART_CR3_TXFTCFG_2             (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */

+

+/******************  Bit definition for USART_BRR register  *******************/

+#define USART_BRR_DIV_FRACTION_Pos      (0U)

+#define USART_BRR_DIV_FRACTION_Msk      (0xFUL << USART_BRR_DIV_FRACTION_Pos)  /*!< 0x0000000F */

+#define USART_BRR_DIV_FRACTION          USART_BRR_DIV_FRACTION_Msk             /*!< Fraction of USARTDIV */

+#define USART_BRR_DIV_MANTISSA_Pos      (4U)

+#define USART_BRR_DIV_MANTISSA_Msk      (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */

+#define USART_BRR_DIV_MANTISSA          USART_BRR_DIV_MANTISSA_Msk             /*!< Mantissa of USARTDIV */

+

+/******************  Bit definition for USART_GTPR register  ******************/

+#define USART_GTPR_PSC_Pos              (0U)

+#define USART_GTPR_PSC_Msk              (0xFFUL << USART_GTPR_PSC_Pos)         /*!< 0x000000FF */

+#define USART_GTPR_PSC                  USART_GTPR_PSC_Msk                     /*!< PSC[7:0] bits (Prescaler value) */

+#define USART_GTPR_GT_Pos               (8U)

+#define USART_GTPR_GT_Msk               (0xFFUL << USART_GTPR_GT_Pos)          /*!< 0x0000FF00 */

+#define USART_GTPR_GT                   USART_GTPR_GT_Msk                      /*!< GT[7:0] bits (Guard time value) */

+

+/*******************  Bit definition for USART_RTOR register  *****************/

+#define USART_RTOR_RTO_Pos              (0U)

+#define USART_RTOR_RTO_Msk              (0xFFFFFFUL << USART_RTOR_RTO_Pos)     /*!< 0x00FFFFFF */

+#define USART_RTOR_RTO                  USART_RTOR_RTO_Msk                     /*!< Receiver Time Out Value */

+#define USART_RTOR_BLEN_Pos             (24U)

+#define USART_RTOR_BLEN_Msk             (0xFFUL << USART_RTOR_BLEN_Pos)        /*!< 0xFF000000 */

+#define USART_RTOR_BLEN                 USART_RTOR_BLEN_Msk                    /*!< Block Length */

+

+/*******************  Bit definition for USART_RQR register  ******************/

+#define USART_RQR_ABRRQ_Pos             (0U)

+#define USART_RQR_ABRRQ_Msk             (0x1UL << USART_RQR_ABRRQ_Pos)         /*!< 0x00000001 */

+#define USART_RQR_ABRRQ                 USART_RQR_ABRRQ_Msk                    /*!< Auto-Baud Rate Request */

+#define USART_RQR_SBKRQ_Pos             (1U)

+#define USART_RQR_SBKRQ_Msk             (0x1UL << USART_RQR_SBKRQ_Pos)         /*!< 0x00000002 */

+#define USART_RQR_SBKRQ                 USART_RQR_SBKRQ_Msk                    /*!< Send Break Request */

+#define USART_RQR_MMRQ_Pos              (2U)

+#define USART_RQR_MMRQ_Msk              (0x1UL << USART_RQR_MMRQ_Pos)          /*!< 0x00000004 */

+#define USART_RQR_MMRQ                  USART_RQR_MMRQ_Msk                     /*!< Mute Mode Request */

+#define USART_RQR_RXFRQ_Pos             (3U)

+#define USART_RQR_RXFRQ_Msk             (0x1UL << USART_RQR_RXFRQ_Pos)         /*!< 0x00000008 */

+#define USART_RQR_RXFRQ                 USART_RQR_RXFRQ_Msk                    /*!< Receive Data flush Request */

+#define USART_RQR_TXFRQ_Pos             (4U)

+#define USART_RQR_TXFRQ_Msk             (0x1UL << USART_RQR_TXFRQ_Pos)         /*!< 0x00000010 */

+#define USART_RQR_TXFRQ                 USART_RQR_TXFRQ_Msk                    /*!< Transmit data flush Request */

+

+/*******************  Bit definition for USART_ISR register  ******************/

+#define USART_ISR_PE_Pos                (0U)

+#define USART_ISR_PE_Msk                (0x1UL << USART_ISR_PE_Pos)            /*!< 0x00000001 */

+#define USART_ISR_PE                    USART_ISR_PE_Msk                       /*!< Parity Error */

+#define USART_ISR_FE_Pos                (1U)

+#define USART_ISR_FE_Msk                (0x1UL << USART_ISR_FE_Pos)            /*!< 0x00000002 */

+#define USART_ISR_FE                    USART_ISR_FE_Msk                       /*!< Framing Error */

+#define USART_ISR_NE_Pos                (2U)

+#define USART_ISR_NE_Msk                (0x1UL << USART_ISR_NE_Pos)            /*!< 0x00000004 */

+#define USART_ISR_NE                    USART_ISR_NE_Msk                       /*!< Noise detected Flag */

+#define USART_ISR_ORE_Pos               (3U)

+#define USART_ISR_ORE_Msk               (0x1UL << USART_ISR_ORE_Pos)           /*!< 0x00000008 */

+#define USART_ISR_ORE                   USART_ISR_ORE_Msk                      /*!< OverRun Error */

+#define USART_ISR_IDLE_Pos              (4U)

+#define USART_ISR_IDLE_Msk              (0x1UL << USART_ISR_IDLE_Pos)          /*!< 0x00000010 */

+#define USART_ISR_IDLE                  USART_ISR_IDLE_Msk                     /*!< IDLE line detected */

+#define USART_ISR_RXNE_RXFNE_Pos        (5U)

+#define USART_ISR_RXNE_RXFNE_Msk        (0x1UL << USART_ISR_RXNE_RXFNE_Pos)    /*!< 0x00000020 */

+#define USART_ISR_RXNE_RXFNE            USART_ISR_RXNE_RXFNE_Msk               /*!< Read Data Register or RX FIFO Not Empty */

+#define USART_ISR_TC_Pos                (6U)

+#define USART_ISR_TC_Msk                (0x1UL << USART_ISR_TC_Pos)            /*!< 0x00000040 */

+#define USART_ISR_TC                    USART_ISR_TC_Msk                       /*!< Transmission Complete */

+#define USART_ISR_TXE_TXFNF_Pos         (7U)

+#define USART_ISR_TXE_TXFNF_Msk         (0x1UL << USART_ISR_TXE_TXFNF_Pos)     /*!< 0x00000080 */

+#define USART_ISR_TXE_TXFNF             USART_ISR_TXE_TXFNF_Msk                /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */

+#define USART_ISR_LBDF_Pos              (8U)

+#define USART_ISR_LBDF_Msk              (0x1UL << USART_ISR_LBDF_Pos)          /*!< 0x00000100 */

+#define USART_ISR_LBDF                  USART_ISR_LBDF_Msk                     /*!< LIN Break Detection Flag */

+#define USART_ISR_CTSIF_Pos             (9U)

+#define USART_ISR_CTSIF_Msk             (0x1UL << USART_ISR_CTSIF_Pos)         /*!< 0x00000200 */

+#define USART_ISR_CTSIF                 USART_ISR_CTSIF_Msk                    /*!< CTS interrupt flag */

+#define USART_ISR_CTS_Pos               (10U)

+#define USART_ISR_CTS_Msk               (0x1UL << USART_ISR_CTS_Pos)           /*!< 0x00000400 */

+#define USART_ISR_CTS                   USART_ISR_CTS_Msk                      /*!< CTS flag */

+#define USART_ISR_RTOF_Pos              (11U)

+#define USART_ISR_RTOF_Msk              (0x1UL << USART_ISR_RTOF_Pos)          /*!< 0x00000800 */

+#define USART_ISR_RTOF                  USART_ISR_RTOF_Msk                     /*!< Receiver Time Out */

+#define USART_ISR_EOBF_Pos              (12U)

+#define USART_ISR_EOBF_Msk              (0x1UL << USART_ISR_EOBF_Pos)          /*!< 0x00001000 */

+#define USART_ISR_EOBF                  USART_ISR_EOBF_Msk                     /*!< End Of Block Flag */

+#define USART_ISR_UDR_Pos               (13U)

+#define USART_ISR_UDR_Msk               (0x1UL << USART_ISR_UDR_Pos)           /*!< 0x00002000 */

+#define USART_ISR_UDR                   USART_ISR_UDR_Msk                      /*!< SPI slave underrun error flag */

+#define USART_ISR_ABRE_Pos              (14U)

+#define USART_ISR_ABRE_Msk              (0x1UL << USART_ISR_ABRE_Pos)          /*!< 0x00004000 */

+#define USART_ISR_ABRE                  USART_ISR_ABRE_Msk                     /*!< Auto-Baud Rate Error */

+#define USART_ISR_ABRF_Pos              (15U)

+#define USART_ISR_ABRF_Msk              (0x1UL << USART_ISR_ABRF_Pos)          /*!< 0x00008000 */

+#define USART_ISR_ABRF                  USART_ISR_ABRF_Msk                     /*!< Auto-Baud Rate Flag */

+#define USART_ISR_BUSY_Pos              (16U)

+#define USART_ISR_BUSY_Msk              (0x1UL << USART_ISR_BUSY_Pos)          /*!< 0x00010000 */

+#define USART_ISR_BUSY                  USART_ISR_BUSY_Msk                     /*!< Busy Flag */

+#define USART_ISR_CMF_Pos               (17U)

+#define USART_ISR_CMF_Msk               (0x1UL << USART_ISR_CMF_Pos)           /*!< 0x00020000 */

+#define USART_ISR_CMF                   USART_ISR_CMF_Msk                      /*!< Character Match Flag */

+#define USART_ISR_SBKF_Pos              (18U)

+#define USART_ISR_SBKF_Msk              (0x1UL << USART_ISR_SBKF_Pos)          /*!< 0x00040000 */

+#define USART_ISR_SBKF                  USART_ISR_SBKF_Msk                     /*!< Send Break Flag */

+#define USART_ISR_RWU_Pos               (19U)

+#define USART_ISR_RWU_Msk               (0x1UL << USART_ISR_RWU_Pos)           /*!< 0x00080000 */

+#define USART_ISR_RWU                   USART_ISR_RWU_Msk                      /*!< Receive Wake Up from mute mode Flag */

+#define USART_ISR_WUF_Pos               (20U)

+#define USART_ISR_WUF_Msk               (0x1UL << USART_ISR_WUF_Pos)           /*!< 0x00100000 */

+#define USART_ISR_WUF                   USART_ISR_WUF_Msk                      /*!< Wake Up from stop mode Flag */

+#define USART_ISR_TEACK_Pos             (21U)

+#define USART_ISR_TEACK_Msk             (0x1UL << USART_ISR_TEACK_Pos)         /*!< 0x00200000 */

+#define USART_ISR_TEACK                 USART_ISR_TEACK_Msk                    /*!< Transmit Enable Acknowledge Flag */

+#define USART_ISR_REACK_Pos             (22U)

+#define USART_ISR_REACK_Msk             (0x1UL << USART_ISR_REACK_Pos)         /*!< 0x00400000 */

+#define USART_ISR_REACK                 USART_ISR_REACK_Msk                    /*!< Receive Enable Acknowledge Flag */

+#define USART_ISR_TXFE_Pos              (23U)

+#define USART_ISR_TXFE_Msk              (0x1UL << USART_ISR_TXFE_Pos)          /*!< 0x00800000 */

+#define USART_ISR_TXFE                  USART_ISR_TXFE_Msk                     /*!< TXFIFO Empty */

+#define USART_ISR_RXFF_Pos              (24U)

+#define USART_ISR_RXFF_Msk              (0x1UL << USART_ISR_RXFF_Pos)          /*!< 0x01000000 */

+#define USART_ISR_RXFF                  USART_ISR_RXFF_Msk                     /*!< RXFIFO Full Flag */

+#define USART_ISR_TCBGT_Pos             (25U)

+#define USART_ISR_TCBGT_Msk             (0x1UL << USART_ISR_TCBGT_Pos)         /*!< 0x02000000 */

+#define USART_ISR_TCBGT                 USART_ISR_TCBGT_Msk                    /*!< Transmission complete before guard time Flag */

+#define USART_ISR_RXFT_Pos              (26U)

+#define USART_ISR_RXFT_Msk              (0x1UL << USART_ISR_RXFT_Pos)          /*!< 0x04000000 */

+#define USART_ISR_RXFT                  USART_ISR_RXFT_Msk                     /*!< RXFIFO threshold Flag */

+#define USART_ISR_TXFT_Pos              (27U)

+#define USART_ISR_TXFT_Msk              (0x1UL << USART_ISR_TXFT_Pos)          /*!< 0x08000000 */

+#define USART_ISR_TXFT                  USART_ISR_TXFT_Msk                     /*!< TXFIFO threshold Flag */

+

+/*******************  Bit definition for USART_ICR register  ******************/

+#define USART_ICR_PECF_Pos              (0U)

+#define USART_ICR_PECF_Msk              (0x1UL << USART_ICR_PECF_Pos)          /*!< 0x00000001 */

+#define USART_ICR_PECF                  USART_ICR_PECF_Msk                     /*!< Parity Error Clear Flag */

+#define USART_ICR_FECF_Pos              (1U)

+#define USART_ICR_FECF_Msk              (0x1UL << USART_ICR_FECF_Pos)          /*!< 0x00000002 */

+#define USART_ICR_FECF                  USART_ICR_FECF_Msk                     /*!< Framing Error Clear Flag */

+#define USART_ICR_NECF_Pos              (2U)

+#define USART_ICR_NECF_Msk              (0x1UL << USART_ICR_NECF_Pos)          /*!< 0x00000004 */

+#define USART_ICR_NECF                  USART_ICR_NECF_Msk                     /*!< Noise detected Clear Flag */

+#define USART_ICR_ORECF_Pos             (3U)

+#define USART_ICR_ORECF_Msk             (0x1UL << USART_ICR_ORECF_Pos)         /*!< 0x00000008 */

+#define USART_ICR_ORECF                 USART_ICR_ORECF_Msk                    /*!< OverRun Error Clear Flag */

+#define USART_ICR_IDLECF_Pos            (4U)

+#define USART_ICR_IDLECF_Msk            (0x1UL << USART_ICR_IDLECF_Pos)        /*!< 0x00000010 */

+#define USART_ICR_IDLECF                USART_ICR_IDLECF_Msk                   /*!< IDLE line detected Clear Flag */

+#define USART_ICR_TXFECF_Pos            (5U)

+#define USART_ICR_TXFECF_Msk            (0x1UL << USART_ICR_TXFECF_Pos)        /*!< 0x00000020 */

+#define USART_ICR_TXFECF                USART_ICR_TXFECF_Msk                   /*!< TXFIFO empty clear flag */

+#define USART_ICR_TCCF_Pos              (6U)

+#define USART_ICR_TCCF_Msk              (0x1UL << USART_ICR_TCCF_Pos)          /*!< 0x00000040 */

+#define USART_ICR_TCCF                  USART_ICR_TCCF_Msk                     /*!< Transmission Complete Clear Flag */

+#define USART_ICR_TCBGTCF_Pos           (7U)

+#define USART_ICR_TCBGTCF_Msk           (0x1UL << USART_ICR_TCBGTCF_Pos)       /*!< 0x00000080 */

+#define USART_ICR_TCBGTCF               USART_ICR_TCBGTCF_Msk                  /*!< Transmission complete before guard time Clear Flag */

+#define USART_ICR_LBDCF_Pos             (8U)

+#define USART_ICR_LBDCF_Msk             (0x1UL << USART_ICR_LBDCF_Pos)         /*!< 0x00000100 */

+#define USART_ICR_LBDCF                 USART_ICR_LBDCF_Msk                    /*!< LIN Break Detection Clear Flag */

+#define USART_ICR_CTSCF_Pos             (9U)

+#define USART_ICR_CTSCF_Msk             (0x1UL << USART_ICR_CTSCF_Pos)         /*!< 0x00000200 */

+#define USART_ICR_CTSCF                 USART_ICR_CTSCF_Msk                    /*!< CTS Interrupt Clear Flag */

+#define USART_ICR_RTOCF_Pos             (11U)

+#define USART_ICR_RTOCF_Msk             (0x1UL << USART_ICR_RTOCF_Pos)         /*!< 0x00000800 */

+#define USART_ICR_RTOCF                 USART_ICR_RTOCF_Msk                    /*!< Receiver Time Out Clear Flag */

+#define USART_ICR_EOBCF_Pos             (12U)

+#define USART_ICR_EOBCF_Msk             (0x1UL << USART_ICR_EOBCF_Pos)         /*!< 0x00001000 */

+#define USART_ICR_EOBCF                 USART_ICR_EOBCF_Msk                    /*!< End Of Block Clear Flag */

+#define USART_ICR_UDRCF_Pos             (13U)

+#define USART_ICR_UDRCF_Msk             (0x1UL << USART_ICR_UDRCF_Pos)         /*!< 0x00002000 */

+#define USART_ICR_UDRCF                 USART_ICR_UDRCF_Msk                    /*!< SPI slave underrun clear flag */

+#define USART_ICR_CMCF_Pos              (17U)

+#define USART_ICR_CMCF_Msk              (0x1UL << USART_ICR_CMCF_Pos)          /*!< 0x00020000 */

+#define USART_ICR_CMCF                  USART_ICR_CMCF_Msk                     /*!< Character Match Clear Flag */

+#define USART_ICR_WUCF_Pos              (20U)

+#define USART_ICR_WUCF_Msk              (0x1UL << USART_ICR_WUCF_Pos)          /*!< 0x00100000 */

+#define USART_ICR_WUCF                  USART_ICR_WUCF_Msk                     /*!< Wake Up from stop mode Clear Flag */

+

+/*******************  Bit definition for USART_RDR register  ******************/

+#define USART_RDR_RDR_Pos               (0U)

+#define USART_RDR_RDR_Msk               (0x1FFUL << USART_RDR_RDR_Pos)         /*!< 0x000001FF */

+#define USART_RDR_RDR                   USART_RDR_RDR_Msk                      /*!< RDR[8:0] bits (Receive Data value) */

+

+/*******************  Bit definition for USART_TDR register  ******************/

+#define USART_TDR_TDR_Pos               (0U)

+#define USART_TDR_TDR_Msk               (0x1FFUL << USART_TDR_TDR_Pos)         /*!< 0x000001FF */

+#define USART_TDR_TDR                   USART_TDR_TDR_Msk                      /*!< TDR[8:0] bits (Transmit Data value) */

+

+/*******************  Bit definition for USART_PRESC register  ******************/

+#define USART_PRESC_PRESCALER_Pos       (0U)

+#define USART_PRESC_PRESCALER_Msk       (0xFUL << USART_PRESC_PRESCALER_Pos)   /*!< 0x0000000F */

+#define USART_PRESC_PRESCALER           USART_PRESC_PRESCALER_Msk              /*!< PRESCALER[3:0] bits (Clock prescaler) */

+#define USART_PRESC_PRESCALER_0         (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */

+#define USART_PRESC_PRESCALER_1         (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */

+#define USART_PRESC_PRESCALER_2         (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */

+#define USART_PRESC_PRESCALER_3         (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */

+

+/******************************************************************************/

+/*                                                                            */

+/*           Single Wire Protocol Master Interface (SWPMI)                    */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for SWPMI_CR register   ********************/

+#define SWPMI_CR_RXDMA_Pos       (0U)

+#define SWPMI_CR_RXDMA_Msk       (0x1UL << SWPMI_CR_RXDMA_Pos)                 /*!< 0x00000001 */

+#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */

+#define SWPMI_CR_TXDMA_Pos       (1U)

+#define SWPMI_CR_TXDMA_Msk       (0x1UL << SWPMI_CR_TXDMA_Pos)                 /*!< 0x00000002 */

+#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */

+#define SWPMI_CR_RXMODE_Pos      (2U)

+#define SWPMI_CR_RXMODE_Msk      (0x1UL << SWPMI_CR_RXMODE_Pos)                /*!< 0x00000004 */

+#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */

+#define SWPMI_CR_TXMODE_Pos      (3U)

+#define SWPMI_CR_TXMODE_Msk      (0x1UL << SWPMI_CR_TXMODE_Pos)                /*!< 0x00000008 */

+#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */

+#define SWPMI_CR_LPBK_Pos        (4U)

+#define SWPMI_CR_LPBK_Msk        (0x1UL << SWPMI_CR_LPBK_Pos)                  /*!< 0x00000010 */

+#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */

+#define SWPMI_CR_SWPACT_Pos      (5U)

+#define SWPMI_CR_SWPACT_Msk      (0x1UL << SWPMI_CR_SWPACT_Pos)                /*!< 0x00000020 */

+#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */

+#define SWPMI_CR_DEACT_Pos       (10U)

+#define SWPMI_CR_DEACT_Msk       (0x1UL << SWPMI_CR_DEACT_Pos)                 /*!< 0x00000400 */

+#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */

+#define SWPMI_CR_SWPEN_Pos       (11U)

+#define SWPMI_CR_SWPEN_Msk       (0x1UL << SWPMI_CR_SWPEN_Pos)                 /*!< 0x00000800 */

+#define SWPMI_CR_SWPEN           SWPMI_CR_SWPEN_Msk                            /*!<Single wire protocol master transceiver enable       */

+

+/*******************  Bit definition for SWPMI_BRR register  ********************/

+#define SWPMI_BRR_BR_Pos         (0U)

+#define SWPMI_BRR_BR_Msk         (0xFFUL << SWPMI_BRR_BR_Pos)                  /*!< 0x000000FF */

+#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[7:0] bits (Bitrate prescaler) */

+

+/*******************  Bit definition for SWPMI_ISR register  ********************/

+#define SWPMI_ISR_RXBFF_Pos      (0U)

+#define SWPMI_ISR_RXBFF_Msk      (0x1UL << SWPMI_ISR_RXBFF_Pos)                /*!< 0x00000001 */

+#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */

+#define SWPMI_ISR_TXBEF_Pos      (1U)

+#define SWPMI_ISR_TXBEF_Msk      (0x1UL << SWPMI_ISR_TXBEF_Pos)                /*!< 0x00000002 */

+#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */

+#define SWPMI_ISR_RXBERF_Pos     (2U)

+#define SWPMI_ISR_RXBERF_Msk     (0x1UL << SWPMI_ISR_RXBERF_Pos)               /*!< 0x00000004 */

+#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */

+#define SWPMI_ISR_RXOVRF_Pos     (3U)

+#define SWPMI_ISR_RXOVRF_Msk     (0x1UL << SWPMI_ISR_RXOVRF_Pos)               /*!< 0x00000008 */

+#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */

+#define SWPMI_ISR_TXUNRF_Pos     (4U)

+#define SWPMI_ISR_TXUNRF_Msk     (0x1UL << SWPMI_ISR_TXUNRF_Pos)               /*!< 0x00000010 */

+#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */

+#define SWPMI_ISR_RXNE_Pos       (5U)

+#define SWPMI_ISR_RXNE_Msk       (0x1UL << SWPMI_ISR_RXNE_Pos)                 /*!< 0x00000020 */

+#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */

+#define SWPMI_ISR_TXE_Pos        (6U)

+#define SWPMI_ISR_TXE_Msk        (0x1UL << SWPMI_ISR_TXE_Pos)                  /*!< 0x00000040 */

+#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */

+#define SWPMI_ISR_TCF_Pos        (7U)

+#define SWPMI_ISR_TCF_Msk        (0x1UL << SWPMI_ISR_TCF_Pos)                  /*!< 0x00000080 */

+#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */

+#define SWPMI_ISR_SRF_Pos        (8U)

+#define SWPMI_ISR_SRF_Msk        (0x1UL << SWPMI_ISR_SRF_Pos)                  /*!< 0x00000100 */

+#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */

+#define SWPMI_ISR_SUSP_Pos       (9U)

+#define SWPMI_ISR_SUSP_Msk       (0x1UL << SWPMI_ISR_SUSP_Pos)                 /*!< 0x00000200 */

+#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */

+#define SWPMI_ISR_DEACTF_Pos     (10U)

+#define SWPMI_ISR_DEACTF_Msk     (0x1UL << SWPMI_ISR_DEACTF_Pos)               /*!< 0x00000400 */

+#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */

+#define SWPMI_ISR_RDYF_Pos       (11U)

+#define SWPMI_ISR_RDYF_Msk       (0x1UL << SWPMI_ISR_RDYF_Pos)                 /*!< 0x00000800 */

+#define SWPMI_ISR_RDYF           SWPMI_ISR_RDYF_Msk                            /*!<Transceiver ready flag          */

+

+/*******************  Bit definition for SWPMI_ICR register  ********************/

+#define SWPMI_ICR_CRXBFF_Pos     (0U)

+#define SWPMI_ICR_CRXBFF_Msk     (0x1UL << SWPMI_ICR_CRXBFF_Pos)               /*!< 0x00000001 */

+#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */

+#define SWPMI_ICR_CTXBEF_Pos     (1U)

+#define SWPMI_ICR_CTXBEF_Msk     (0x1UL << SWPMI_ICR_CTXBEF_Pos)               /*!< 0x00000002 */

+#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */

+#define SWPMI_ICR_CRXBERF_Pos    (2U)

+#define SWPMI_ICR_CRXBERF_Msk    (0x1UL << SWPMI_ICR_CRXBERF_Pos)              /*!< 0x00000004 */

+#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */

+#define SWPMI_ICR_CRXOVRF_Pos    (3U)

+#define SWPMI_ICR_CRXOVRF_Msk    (0x1UL << SWPMI_ICR_CRXOVRF_Pos)              /*!< 0x00000008 */

+#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */

+#define SWPMI_ICR_CTXUNRF_Pos    (4U)

+#define SWPMI_ICR_CTXUNRF_Msk    (0x1UL << SWPMI_ICR_CTXUNRF_Pos)              /*!< 0x00000010 */

+#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */

+#define SWPMI_ICR_CTCF_Pos       (7U)

+#define SWPMI_ICR_CTCF_Msk       (0x1UL << SWPMI_ICR_CTCF_Pos)                 /*!< 0x00000080 */

+#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */

+#define SWPMI_ICR_CSRF_Pos       (8U)

+#define SWPMI_ICR_CSRF_Msk       (0x1UL << SWPMI_ICR_CSRF_Pos)                 /*!< 0x00000100 */

+#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */

+#define SWPMI_ICR_CRDYF_Pos      (11U)

+#define SWPMI_ICR_CRDYF_Msk      (0x1UL << SWPMI_ICR_CRDYF_Pos)                /*!< 0x00000800 */

+#define SWPMI_ICR_CRDYF          SWPMI_ICR_CRDYF_Msk                           /*!<Clear transceiver ready flag         */

+

+/*******************  Bit definition for SWPMI_IER register  ********************/

+#define SWPMI_IER_RXBFIE_Pos     (0U)

+#define SWPMI_IER_RXBFIE_Msk     (0x1UL << SWPMI_IER_RXBFIE_Pos)               /*!< 0x00000001 */

+#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */

+#define SWPMI_IER_TXBEIE_Pos     (1U)

+#define SWPMI_IER_TXBEIE_Msk     (0x1UL << SWPMI_IER_TXBEIE_Pos)               /*!< 0x00000002 */

+#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */

+#define SWPMI_IER_RXBERIE_Pos    (2U)

+#define SWPMI_IER_RXBERIE_Msk    (0x1UL << SWPMI_IER_RXBERIE_Pos)              /*!< 0x00000004 */

+#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */

+#define SWPMI_IER_RXOVRIE_Pos    (3U)

+#define SWPMI_IER_RXOVRIE_Msk    (0x1UL << SWPMI_IER_RXOVRIE_Pos)              /*!< 0x00000008 */

+#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */

+#define SWPMI_IER_TXUNRIE_Pos    (4U)

+#define SWPMI_IER_TXUNRIE_Msk    (0x1UL << SWPMI_IER_TXUNRIE_Pos)              /*!< 0x00000010 */

+#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */

+#define SWPMI_IER_RIE_Pos        (5U)

+#define SWPMI_IER_RIE_Msk        (0x1UL << SWPMI_IER_RIE_Pos)                  /*!< 0x00000020 */

+#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */

+#define SWPMI_IER_TIE_Pos        (6U)

+#define SWPMI_IER_TIE_Msk        (0x1UL << SWPMI_IER_TIE_Pos)                  /*!< 0x00000040 */

+#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */

+#define SWPMI_IER_TCIE_Pos       (7U)

+#define SWPMI_IER_TCIE_Msk       (0x1UL << SWPMI_IER_TCIE_Pos)                 /*!< 0x00000080 */

+#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */

+#define SWPMI_IER_SRIE_Pos       (8U)

+#define SWPMI_IER_SRIE_Msk       (0x1UL << SWPMI_IER_SRIE_Pos)                 /*!< 0x00000100 */

+#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */

+#define SWPMI_IER_RDYIE_Pos      (11U)

+#define SWPMI_IER_RDYIE_Msk      (0x1UL << SWPMI_IER_RDYIE_Pos)                /*!< 0x00000800 */

+#define SWPMI_IER_RDYIE          SWPMI_IER_RDYIE_Msk                           /*!<Transceiver ready interrupt enable          */

+

+/*******************  Bit definition for SWPMI_RFL register  ********************/

+#define SWPMI_RFL_RFL_Pos        (0U)

+#define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */

+#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */

+#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */

+

+/*******************  Bit definition for SWPMI_TDR register  ********************/

+#define SWPMI_TDR_TD_Pos         (0U)

+#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)            /*!< 0xFFFFFFFF */

+#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */

+

+/*******************  Bit definition for SWPMI_RDR register  ********************/

+#define SWPMI_RDR_RD_Pos         (0U)

+#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)            /*!< 0xFFFFFFFF */

+#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Recive Data Register           */

+

+

+/*******************  Bit definition for SWPMI_OR register  ********************/

+#define SWPMI_OR_TBYP_Pos        (0U)

+#define SWPMI_OR_TBYP_Msk        (0x1UL << SWPMI_OR_TBYP_Pos)                  /*!< 0x00000001 */

+#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */

+#define SWPMI_OR_CLASS_Pos       (1U)

+#define SWPMI_OR_CLASS_Msk       (0x1UL << SWPMI_OR_CLASS_Pos)                 /*!< 0x00000002 */

+#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP CLASS selection */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            Window WATCHDOG                                 */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for WWDG_CR register  ********************/

+#define WWDG_CR_T_Pos           (0U)

+#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */

+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */

+#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */

+#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */

+#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */

+#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */

+#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */

+#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */

+#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */

+

+#define WWDG_CR_WDGA_Pos        (7U)

+#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */

+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */

+

+/*******************  Bit definition for WWDG_CFR register  *******************/

+#define WWDG_CFR_W_Pos          (0U)

+#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */

+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */

+#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */

+#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */

+#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */

+#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */

+#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */

+#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */

+#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */

+

+#define WWDG_CFR_EWI_Pos        (9U)

+#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */

+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */

+

+#define WWDG_CFR_WDGTB_Pos      (11U)

+#define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */

+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */

+#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000800 */

+#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00001000 */

+#define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00002000 */

+

+/*******************  Bit definition for WWDG_SR register  ********************/

+#define WWDG_SR_EWIF_Pos        (0U)

+#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */

+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                DBG                                         */

+/*                                                                            */

+/******************************************************************************/

+/*********************************  DEVICE ID  ********************************/

+#define STM32H7_DEV_ID           0x480UL

+

+/********************  Bit definition for DBGMCU_IDCODE register  *************/

+#define DBGMCU_IDCODE_DEV_ID_Pos          (0U)

+#define DBGMCU_IDCODE_DEV_ID_Msk          (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */

+#define DBGMCU_IDCODE_DEV_ID              DBGMCU_IDCODE_DEV_ID_Msk

+#define DBGMCU_IDCODE_REV_ID_Pos          (16U)

+#define DBGMCU_IDCODE_REV_ID_Msk          (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */

+#define DBGMCU_IDCODE_REV_ID              DBGMCU_IDCODE_REV_ID_Msk

+

+/********************  Bit definition for DBGMCU_CR register  *****************/

+#define DBGMCU_CR_DBG_SLEEPCD_Pos         (0U)

+#define DBGMCU_CR_DBG_SLEEPCD_Msk         (0x1UL << DBGMCU_CR_DBG_SLEEPCD_Pos) /*!< 0x00000001 */

+#define DBGMCU_CR_DBG_SLEEPCD             DBGMCU_CR_DBG_SLEEPCD_Msk

+#define DBGMCU_CR_DBG_STOPCD_Pos          (1U)

+#define DBGMCU_CR_DBG_STOPCD_Msk          (0x1UL << DBGMCU_CR_DBG_STOPCD_Pos)  /*!< 0x00000002 */

+#define DBGMCU_CR_DBG_STOPCD              DBGMCU_CR_DBG_STOPCD_Msk

+#define DBGMCU_CR_DBG_STANDBYCD_Pos       (2U)

+#define DBGMCU_CR_DBG_STANDBYCD_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYCD_Pos) /*!< 0x00000004 */

+#define DBGMCU_CR_DBG_STANDBYCD           DBGMCU_CR_DBG_STANDBYCD_Msk

+

+/* Legacy defines */

+#define DBGMCU_CR_DBG_SLEEPD1_Pos         DBGMCU_CR_DBG_SLEEPCD_Pos

+#define DBGMCU_CR_DBG_SLEEPD1_Msk         DBGMCU_CR_DBG_SLEEPCD_Msk

+#define DBGMCU_CR_DBG_SLEEPD1             DBGMCU_CR_DBG_SLEEPCD

+#define DBGMCU_CR_DBG_STOPD1_Pos          DBGMCU_CR_DBG_STOPCD_Pos

+#define DBGMCU_CR_DBG_STOPD1_Msk          DBGMCU_CR_DBG_STOPCD_Msk

+#define DBGMCU_CR_DBG_STOPD1              DBGMCU_CR_DBG_STOPCD

+#define DBGMCU_CR_DBG_STANDBYD1_Pos       DBGMCU_CR_DBG_STANDBYCD_Pos

+#define DBGMCU_CR_DBG_STANDBYD1_Msk       DBGMCU_CR_DBG_STANDBYCD_Msk

+#define DBGMCU_CR_DBG_STANDBYD1           DBGMCU_CR_DBG_STANDBYCD

+#define DBGMCU_CR_DBG_STOPSRD_Pos          (7U)

+#define DBGMCU_CR_DBG_STOPSRD_Msk          (0x1UL << DBGMCU_CR_DBG_STOPSRD_Pos)  /*!< 0x00000080 */

+#define DBGMCU_CR_DBG_STOPSRD              DBGMCU_CR_DBG_STOPSRD_Msk

+#define DBGMCU_CR_DBG_STANDBYSRD_Pos       (8U)

+#define DBGMCU_CR_DBG_STANDBYSRD_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYSRD_Pos) /*!< 0x00000100 */

+#define DBGMCU_CR_DBG_STANDBYSRD           DBGMCU_CR_DBG_STANDBYSRD_Msk

+

+/* Legacy defines */

+#define DBGMCU_CR_DBG_STOPD3_Pos          DBGMCU_CR_DBG_STOPSRD_Pos

+#define DBGMCU_CR_DBG_STOPD3_Msk          DBGMCU_CR_DBG_STOPSRD_Msk

+#define DBGMCU_CR_DBG_STOPD3              DBGMCU_CR_DBG_STOPSRD

+#define DBGMCU_CR_DBG_STANDBYD3_Pos       DBGMCU_CR_DBG_STANDBYSRD_Pos

+#define DBGMCU_CR_DBG_STANDBYD3_Msk       DBGMCU_CR_DBG_STANDBYSRD_Msk

+#define DBGMCU_CR_DBG_STANDBYD3           DBGMCU_CR_DBG_STANDBYSRD

+

+#define DBGMCU_CR_DBG_TRACECKEN_Pos       (20U)

+#define DBGMCU_CR_DBG_TRACECKEN_Msk       (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */

+#define DBGMCU_CR_DBG_TRACECKEN           DBGMCU_CR_DBG_TRACECKEN_Msk

+#define DBGMCU_CR_DBG_CKCDEN_Pos          (21U)

+#define DBGMCU_CR_DBG_CKCDEN_Msk          (0x1UL << DBGMCU_CR_DBG_CKCDEN_Pos)  /*!< 0x00200000 */

+#define DBGMCU_CR_DBG_CKCDEN              DBGMCU_CR_DBG_CKCDEN_Msk

+#define DBGMCU_CR_DBG_CKSRDEN_Pos          (22U)

+#define DBGMCU_CR_DBG_CKSRDEN_Msk          (0x1UL << DBGMCU_CR_DBG_CKSRDEN_Pos)  /*!< 0x00400000 */

+#define DBGMCU_CR_DBG_CKSRDEN              DBGMCU_CR_DBG_CKSRDEN_Msk

+

+/* Legacy defines */

+#define DBGMCU_CR_DBG_CKD1EN_Pos          DBGMCU_CR_DBG_CKCDEN_Pos

+#define DBGMCU_CR_DBG_CKD1EN_Msk          DBGMCU_CR_DBG_CKCDEN_Msk

+#define DBGMCU_CR_DBG_CKD1EN              DBGMCU_CR_DBG_CKCDEN

+#define DBGMCU_CR_DBG_CKD3EN_Pos          DBGMCU_CR_DBG_CKSRDEN_Pos

+#define DBGMCU_CR_DBG_CKD3EN_Msk          DBGMCU_CR_DBG_CKSRDEN_Msk

+#define DBGMCU_CR_DBG_CKD3EN              DBGMCU_CR_DBG_CKSRDEN

+

+#define DBGMCU_CR_DBG_TRGOEN_Pos          (28U)

+#define DBGMCU_CR_DBG_TRGOEN_Msk          (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)  /*!< 0x10000000 */

+#define DBGMCU_CR_DBG_TRGOEN              DBGMCU_CR_DBG_TRGOEN_Msk

+

+/********************  Bit definition for APB3FZ1 register  ************/

+#define DBGMCU_APB3FZ1_DBG_WWDG1_Pos      (6U)

+#define DBGMCU_APB3FZ1_DBG_WWDG1_Msk      (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB3FZ1_DBG_WWDG1          DBGMCU_APB3FZ1_DBG_WWDG1_Msk

+/********************  Bit definition for APB1LFZ1 register  ************/

+#define DBGMCU_APB1LFZ1_DBG_TIM2_Pos      (0U)

+#define DBGMCU_APB1LFZ1_DBG_TIM2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB1LFZ1_DBG_TIM2          DBGMCU_APB1LFZ1_DBG_TIM2_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM3_Pos      (1U)

+#define DBGMCU_APB1LFZ1_DBG_TIM3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB1LFZ1_DBG_TIM3          DBGMCU_APB1LFZ1_DBG_TIM3_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM4_Pos      (2U)

+#define DBGMCU_APB1LFZ1_DBG_TIM4_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */

+#define DBGMCU_APB1LFZ1_DBG_TIM4          DBGMCU_APB1LFZ1_DBG_TIM4_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM5_Pos      (3U)

+#define DBGMCU_APB1LFZ1_DBG_TIM5_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */

+#define DBGMCU_APB1LFZ1_DBG_TIM5          DBGMCU_APB1LFZ1_DBG_TIM5_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM6_Pos      (4U)

+#define DBGMCU_APB1LFZ1_DBG_TIM6_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */

+#define DBGMCU_APB1LFZ1_DBG_TIM6          DBGMCU_APB1LFZ1_DBG_TIM6_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM7_Pos      (5U)

+#define DBGMCU_APB1LFZ1_DBG_TIM7_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */

+#define DBGMCU_APB1LFZ1_DBG_TIM7          DBGMCU_APB1LFZ1_DBG_TIM7_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM12_Pos     (6U)

+#define DBGMCU_APB1LFZ1_DBG_TIM12_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB1LFZ1_DBG_TIM12         DBGMCU_APB1LFZ1_DBG_TIM12_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM13_Pos     (7U)

+#define DBGMCU_APB1LFZ1_DBG_TIM13_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB1LFZ1_DBG_TIM13         DBGMCU_APB1LFZ1_DBG_TIM13_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM14_Pos     (8U)

+#define DBGMCU_APB1LFZ1_DBG_TIM14_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */

+#define DBGMCU_APB1LFZ1_DBG_TIM14         DBGMCU_APB1LFZ1_DBG_TIM14_Msk

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos    (9U)

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1        DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C1_Pos      (21U)

+#define DBGMCU_APB1LFZ1_DBG_I2C1_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C1          DBGMCU_APB1LFZ1_DBG_I2C1_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C2_Pos      (22U)

+#define DBGMCU_APB1LFZ1_DBG_I2C2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C2          DBGMCU_APB1LFZ1_DBG_I2C2_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C3_Pos      (23U)

+#define DBGMCU_APB1LFZ1_DBG_I2C3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C3          DBGMCU_APB1LFZ1_DBG_I2C3_Msk

+

+/********************  Bit definition for APB2FZ1 register  ************/

+#define DBGMCU_APB2FZ1_DBG_TIM1_Pos       (0U)

+#define DBGMCU_APB2FZ1_DBG_TIM1_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB2FZ1_DBG_TIM1           DBGMCU_APB2FZ1_DBG_TIM1_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM8_Pos       (1U)

+#define DBGMCU_APB2FZ1_DBG_TIM8_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB2FZ1_DBG_TIM8           DBGMCU_APB2FZ1_DBG_TIM8_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM15_Pos      (16U)

+#define DBGMCU_APB2FZ1_DBG_TIM15_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB2FZ1_DBG_TIM15          DBGMCU_APB2FZ1_DBG_TIM15_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM16_Pos      (17U)

+#define DBGMCU_APB2FZ1_DBG_TIM16_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */

+#define DBGMCU_APB2FZ1_DBG_TIM16          DBGMCU_APB2FZ1_DBG_TIM16_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM17_Pos      (18U)

+#define DBGMCU_APB2FZ1_DBG_TIM17_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB2FZ1_DBG_TIM17          DBGMCU_APB2FZ1_DBG_TIM17_Msk

+/********************  Bit definition for APB4FZ1 register  ************/

+#define DBGMCU_APB4FZ1_DBG_I2C4_Pos       (7U)

+#define DBGMCU_APB4FZ1_DBG_I2C4_Msk       (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB4FZ1_DBG_I2C4           DBGMCU_APB4FZ1_DBG_I2C4_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos     (9U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM2         DBGMCU_APB4FZ1_DBG_LPTIM2_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos     (10U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM3         DBGMCU_APB4FZ1_DBG_LPTIM3_Msk

+#define DBGMCU_APB4FZ1_DBG_RTC_Pos        (16U)

+#define DBGMCU_APB4FZ1_DBG_RTC_Msk        (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB4FZ1_DBG_RTC            DBGMCU_APB4FZ1_DBG_RTC_Msk

+#define DBGMCU_APB4FZ1_DBG_IWDG1_Pos      (18U)

+#define DBGMCU_APB4FZ1_DBG_IWDG1_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB4FZ1_DBG_IWDG1          DBGMCU_APB4FZ1_DBG_IWDG1_Msk

+/******************************************************************************/

+/*                                                                            */

+/*                             RAM ECC monitoring                             */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for RAMECC_IER register  ******************/

+#define RAMECC_IER_GECCDEBWIE_Pos         (3U)

+#define RAMECC_IER_GECCDEBWIE_Msk         (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)  /*!< 0x00000008 */

+#define RAMECC_IER_GECCDEBWIE             RAMECC_IER_GECCDEBWIE_Msk             /*!< Global ECC double error on byte write (BW) interrupt enable */

+#define RAMECC_IER_GECCDEIE_Pos           (2U)

+#define RAMECC_IER_GECCDEIE_Msk           (0x1UL << RAMECC_IER_GECCDEIE_Pos)    /*!< 0x00000004 */

+#define RAMECC_IER_GECCDEIE               RAMECC_IER_GECCDEIE_Msk               /*!< Global ECC double error interrupt enable */

+#define RAMECC_IER_GECCSEIE_Pos           (1U)

+#define RAMECC_IER_GECCSEIE_Msk           (0x1UL << RAMECC_IER_GECCSEIE_Pos)    /*!< 0x00000002 */

+#define RAMECC_IER_GECCSEIE               RAMECC_IER_GECCSEIE_Msk               /*!< Global ECC single error interrupt enable */

+#define RAMECC_IER_GIE_Pos                (0U)

+#define RAMECC_IER_GIE_Msk                (0x1UL << RAMECC_IER_GIE_Pos)         /*!< 0x00000001 */

+#define RAMECC_IER_GIE                    RAMECC_IER_GIE_Msk                    /*!< Global interrupt enable */

+

+/*******************  Bit definition for RAMECC_CR register  ******************/

+#define RAMECC_CR_ECCELEN_Pos             (5U)

+#define RAMECC_CR_ECCELEN_Msk             (0x1UL << RAMECC_CR_ECCELEN_Pos)      /*!< 0x00000020 */

+#define RAMECC_CR_ECCELEN                 RAMECC_CR_ECCELEN_Msk                 /*!< ECC error latching enable */

+#define RAMECC_CR_ECCDEBWIE_Pos           (4U)

+#define RAMECC_CR_ECCDEBWIE_Msk           (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)    /*!< 0x00000010 */

+#define RAMECC_CR_ECCDEBWIE               RAMECC_CR_ECCDEBWIE_Msk               /*!< ECC double error on byte write (BW) interrupt enable */

+#define RAMECC_CR_ECCDEIE_Pos             (3U)

+#define RAMECC_CR_ECCDEIE_Msk             (0x1UL << RAMECC_CR_ECCDEIE_Pos)      /*!< 0x00000008 */

+#define RAMECC_CR_ECCDEIE                 RAMECC_CR_ECCDEIE_Msk                 /*!< ECC double error interrupt enable */

+#define RAMECC_CR_ECCSEIE_Pos             (2U)

+#define RAMECC_CR_ECCSEIE_Msk             (0x1UL << RAMECC_CR_ECCSEIE_Pos)      /*!< 0x00000004 */

+#define RAMECC_CR_ECCSEIE                 RAMECC_CR_ECCSEIE_Msk                 /*!< ECC single error interrupt enable */

+

+/*******************  Bit definition for RAMECC_SR register  ******************/

+#define RAMECC_SR_DEBWDF_Pos             (2U)

+#define RAMECC_SR_DEBWDF_Msk             (0x1UL << RAMECC_SR_DEBWDF_Pos)        /*!< 0x00000004 */

+#define RAMECC_SR_DEBWDF                 RAMECC_SR_DEBWDF_Msk                   /*!< ECC double error on byte write (BW) detected flag */

+#define RAMECC_SR_DEDF_Pos               (1U)

+#define RAMECC_SR_DEDF_Msk               (0x1UL << RAMECC_SR_DEDF_Pos)          /*!< 0x00000002 */

+#define RAMECC_SR_DEDF                   RAMECC_SR_DEDF_Msk                     /*!< ECC double error detected flag */

+#define RAMECC_SR_SEDCF_Pos              (0U)

+#define RAMECC_SR_SEDCF_Msk              (0x1UL << RAMECC_SR_SEDCF_Pos)         /*!< 0x00000001 */

+#define RAMECC_SR_SEDCF                  RAMECC_SR_SEDCF_Msk                    /*!< ECC single error detected and corrected flag */

+

+/******************  Bit definition for RAMECC_FAR register  ******************/

+#define RAMECC_FAR_FADD_Pos              (0U)

+#define RAMECC_FAR_FADD_Msk              (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)  /*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FADD                  RAMECC_FAR_FADD_Msk                    /*!< ECC error failing address */

+

+/******************  Bit definition for RAMECC_FDRL register  *****************/

+#define RAMECC_FAR_FDATAL_Pos            (0U)

+#define RAMECC_FAR_FDATAL_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FDATAL                RAMECC_FAR_FDATAL_Msk                  /*!< ECC error failing address */

+

+/******************  Bit definition for RAMECC_FDRH register  *****************/

+#define RAMECC_FAR_FDATAH_Pos            (0U)

+#define RAMECC_FAR_FDATAH_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FDATAH                RAMECC_FAR_FDATAH_Msk                  /* Failing data high (64-bit memory) */

+

+/*****************  Bit definition for RAMECC_FECR register  ******************/

+#define RAMECC_FECR_FEC_Pos              (0U)

+#define RAMECC_FECR_FEC_Msk              (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)  /*!< 0xFFFFFFFF */

+#define RAMECC_FECR_FEC                  RAMECC_FECR_FEC_Msk                    /*!< Failing error code */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                MDIOS                                        */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for MDIOS_CR register  *******************/

+#define MDIOS_CR_EN_Pos                (0U)

+#define MDIOS_CR_EN_Msk                (0x1UL << MDIOS_CR_EN_Pos)              /*!< 0x00000001 */

+#define MDIOS_CR_EN                    MDIOS_CR_EN_Msk                         /*!<  MDIOS slave peripheral enable */

+#define MDIOS_CR_WRIE_Pos              (1U)

+#define MDIOS_CR_WRIE_Msk              (0x1UL << MDIOS_CR_WRIE_Pos)            /*!< 0x00000002 */

+#define MDIOS_CR_WRIE                  MDIOS_CR_WRIE_Msk                       /*!<  MDIOS slave register write interrupt enable. */

+#define MDIOS_CR_RDIE_Pos              (2U)

+#define MDIOS_CR_RDIE_Msk              (0x1UL << MDIOS_CR_RDIE_Pos)            /*!< 0x00000004 */

+#define MDIOS_CR_RDIE                  MDIOS_CR_RDIE_Msk                       /*!<  MDIOS slave register read interrupt enable. */

+#define MDIOS_CR_EIE_Pos               (3U)

+#define MDIOS_CR_EIE_Msk               (0x1UL << MDIOS_CR_EIE_Pos)             /*!< 0x00000008 */

+#define MDIOS_CR_EIE                   MDIOS_CR_EIE_Msk                        /*!<  MDIOS slave register error interrupt enable. */

+#define MDIOS_CR_DPC_Pos               (7U)

+#define MDIOS_CR_DPC_Msk               (0x1UL << MDIOS_CR_DPC_Pos)             /*!< 0x00000080 */

+#define MDIOS_CR_DPC                   MDIOS_CR_DPC_Msk                        /*!<  MDIOS slave disable preamble check. */

+#define MDIOS_CR_PORT_ADDRESS_Pos      (8U)

+#define MDIOS_CR_PORT_ADDRESS_Msk      (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)   /*!< 0x00001F00 */

+#define MDIOS_CR_PORT_ADDRESS          MDIOS_CR_PORT_ADDRESS_Msk               /*!<  MDIOS slave port address mask. */

+#define MDIOS_CR_PORT_ADDRESS_0        (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000100 */

+#define MDIOS_CR_PORT_ADDRESS_1        (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000200 */

+#define MDIOS_CR_PORT_ADDRESS_2        (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000400 */

+#define MDIOS_CR_PORT_ADDRESS_3        (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000800 */

+#define MDIOS_CR_PORT_ADDRESS_4        (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001000 */

+

+/********************  Bit definition for MDIOS_SR register  *******************/

+#define MDIOS_SR_PERF_Pos              (0U)

+#define MDIOS_SR_PERF_Msk              (0x1UL << MDIOS_SR_PERF_Pos)            /*!< 0x00000001 */

+#define MDIOS_SR_PERF                  MDIOS_SR_PERF_Msk                       /*!<  MDIOS slave turnaround error flag*/

+#define MDIOS_SR_SERF_Pos              (1U)

+#define MDIOS_SR_SERF_Msk              (0x1UL << MDIOS_SR_SERF_Pos)            /*!< 0x00000002 */

+#define MDIOS_SR_SERF                  MDIOS_SR_SERF_Msk                       /*!<  MDIOS slave start error flag */

+#define MDIOS_SR_TERF_Pos              (2U)

+#define MDIOS_SR_TERF_Msk              (0x1UL << MDIOS_SR_TERF_Pos)            /*!< 0x00000004 */

+#define MDIOS_SR_TERF                  MDIOS_SR_TERF_Msk                       /*!<  MDIOS slave preamble error flag */

+

+/********************  Bit definition for MDIOS_CLRFR register  *******************/

+#define MDIOS_SR_CPERF_Pos             (0U)

+#define MDIOS_SR_CPERF_Msk             (0x1UL << MDIOS_SR_CPERF_Pos)           /*!< 0x00000001 */

+#define MDIOS_SR_CPERF                 MDIOS_SR_CPERF_Msk                      /*!<  MDIOS slave Clear the turnaround error flag */

+#define MDIOS_SR_CSERF_Pos             (1U)

+#define MDIOS_SR_CSERF_Msk             (0x1UL << MDIOS_SR_CSERF_Pos)           /*!< 0x00000002 */

+#define MDIOS_SR_CSERF                 MDIOS_SR_CSERF_Msk                      /*!<  MDIOS slave Clear the start error flag */

+#define MDIOS_SR_CTERF_Pos             (2U)

+#define MDIOS_SR_CTERF_Msk             (0x1UL << MDIOS_SR_CTERF_Pos)           /*!< 0x00000004 */

+#define MDIOS_SR_CTERF                 MDIOS_SR_CTERF_Msk                      /*!<  MDIOS slave Clear the preamble error flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                       USB_OTG                              */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/

+#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)

+#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */

+#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */

+#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)

+#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */

+#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */

+#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)

+#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */

+#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */

+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)

+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */

+#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */

+#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)

+#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */

+#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */

+#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)

+#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */

+#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */

+#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)

+#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */

+#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */

+#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)

+#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */

+#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */

+#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)

+#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */

+#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */

+#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)

+#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */

+#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */

+#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)

+#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */

+#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */

+#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)

+#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */

+#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */

+#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)

+#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */

+#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */

+#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)

+#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */

+#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */

+#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)

+#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */

+#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */

+#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)

+#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */

+#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */

+#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)

+#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */

+#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */

+#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)

+#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */

+#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */

+

+/********************  Bit definition forUSB_OTG_HCFG register  ********************/

+

+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)

+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */

+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */

+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)

+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */

+

+/********************  Bit definition forUSB_OTG_DCFG register  ********************/

+

+#define USB_OTG_DCFG_DSPD_Pos                    (0U)

+#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */

+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */

+#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */

+#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)

+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */

+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */

+

+#define USB_OTG_DCFG_DAD_Pos                     (4U)

+#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */

+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */

+#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */

+#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */

+#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */

+#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */

+#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */

+#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */

+#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */

+

+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)

+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */

+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */

+#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */

+#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */

+

+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)

+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */

+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */

+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */

+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */

+

+/********************  Bit definition forUSB_OTG_PCGCR register  ********************/

+#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)

+#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */

+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */

+#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)

+#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */

+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */

+#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)

+#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */

+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */

+

+/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/

+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)

+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */

+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */

+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)

+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */

+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */

+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)

+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */

+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */

+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)

+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */

+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */

+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)

+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */

+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */

+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)

+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */

+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */

+

+/********************  Bit definition forUSB_OTG_DCTL register  ********************/

+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)

+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */

+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */

+#define USB_OTG_DCTL_SDIS_Pos                    (1U)

+#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */

+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */

+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)

+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */

+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */

+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)

+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */

+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */

+

+#define USB_OTG_DCTL_TCTL_Pos                    (4U)

+#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */

+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */

+#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */

+#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */

+#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */

+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)

+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */

+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */

+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)

+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */

+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */

+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)

+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */

+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */

+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)

+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */

+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */

+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)

+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */

+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */

+

+/********************  Bit definition forUSB_OTG_HFIR register  ********************/

+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)

+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */

+

+/********************  Bit definition forUSB_OTG_HFNUM register  ********************/

+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)

+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */

+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)

+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */

+

+/********************  Bit definition forUSB_OTG_DSTS register  ********************/

+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)

+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */

+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */

+

+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)

+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */

+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */

+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */

+#define USB_OTG_DSTS_EERR_Pos                    (3U)

+#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */

+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */

+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)

+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */

+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */

+

+/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/

+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)

+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */

+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */

+

+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)

+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */

+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */

+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */

+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */

+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */

+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */

+#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */

+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)

+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */

+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */

+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)

+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */

+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */

+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)

+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */

+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */

+

+/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/

+

+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)

+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */

+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */

+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */

+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */

+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */

+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)

+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */

+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */

+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)

+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */

+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */

+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)

+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */

+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */

+

+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)

+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */

+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */

+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */

+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */

+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */

+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */

+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)

+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */

+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */

+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)

+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */

+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */

+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)

+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */

+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */

+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)

+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */

+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */

+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)

+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */

+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */

+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)

+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */

+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */

+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)

+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */

+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */

+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)

+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */

+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */

+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)

+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */

+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */

+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)

+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */

+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */

+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)

+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */

+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */

+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)

+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */

+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */

+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)

+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */

+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */

+

+/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/

+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)

+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */

+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */

+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)

+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */

+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */

+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)

+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */

+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */

+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)

+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */

+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */

+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)

+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */

+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */

+

+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)

+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */

+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */

+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */

+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */

+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */

+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */

+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */

+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)

+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */

+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */

+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)

+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */

+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */

+

+/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/

+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)

+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */

+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)

+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */

+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)

+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */

+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)

+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */

+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)

+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */

+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)

+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */

+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)

+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */

+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)

+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */

+

+/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/

+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)

+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */

+

+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)

+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */

+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */

+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */

+

+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)

+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */

+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */

+

+/********************  Bit definition forUSB_OTG_HAINT register  ********************/

+#define USB_OTG_HAINT_HAINT_Pos                  (0U)

+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */

+

+/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/

+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)

+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */

+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)

+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */

+#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)

+#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */

+#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask               */

+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)

+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */

+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)

+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */

+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)

+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */

+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)

+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */

+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)

+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */

+#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)

+#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */

+#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)

+#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask               */

+#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)

+#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask               */

+#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)

+#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                */

+

+/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/

+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)

+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */

+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */

+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)

+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */

+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */

+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)

+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */

+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */

+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)

+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */

+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */

+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)

+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */

+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */

+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)

+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */

+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */

+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)

+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */

+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */

+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)

+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */

+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */

+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)

+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */

+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */

+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)

+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */

+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */

+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)

+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */

+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */

+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)

+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */

+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */

+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)

+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */

+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */

+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)

+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */

+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */

+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)

+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */

+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */

+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)

+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */

+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */

+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)

+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */

+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */

+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)

+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */

+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */

+#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)

+#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */

+#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */

+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)

+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */

+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */

+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)

+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */

+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */

+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)

+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */

+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */

+#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)

+#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */

+#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */

+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)

+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */

+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */

+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)

+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */

+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */

+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)

+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */

+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */

+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)

+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */

+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */

+

+/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/

+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)

+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */

+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */

+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)

+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */

+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */

+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)

+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */

+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */

+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)

+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */

+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */

+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)

+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */

+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */

+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)

+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */

+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */

+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)

+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */

+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */

+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)

+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */

+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */

+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)

+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */

+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */

+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)

+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */

+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */

+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)

+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */

+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */

+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)

+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */

+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */

+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)

+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */

+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */

+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)

+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */

+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */

+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)

+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */

+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */

+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)

+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */

+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */

+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)

+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */

+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */

+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)

+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */

+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */

+#define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)

+#define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */

+#define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */

+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)

+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */

+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */

+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)

+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */

+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */

+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)

+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */

+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */

+#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)

+#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */

+#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */

+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)

+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */

+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */

+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)

+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */

+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */

+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)

+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */

+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */

+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)

+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */

+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */

+

+/********************  Bit definition forUSB_OTG_DAINT register  ********************/

+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)

+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */

+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)

+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */

+

+/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/

+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)

+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */

+

+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/

+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)

+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */

+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */

+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)

+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */

+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */

+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)

+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */

+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */

+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)

+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */

+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */

+

+/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/

+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)

+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */

+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)

+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */

+

+/********************  Bit definition for OTG register  ********************/

+

+#define USB_OTG_CHNUM_Pos                        (0U)

+#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)  /*!< 0x0000000F */

+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */

+#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */

+#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */

+#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */

+#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */

+#define USB_OTG_BCNT_Pos                         (4U)

+#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */

+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */

+

+#define USB_OTG_DPID_Pos                         (15U)

+#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)   /*!< 0x00018000 */

+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */

+#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */

+#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */

+

+#define USB_OTG_PKTSTS_Pos                       (17U)

+#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */

+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */

+#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */

+#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */

+#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */

+#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */

+

+#define USB_OTG_EPNUM_Pos                        (0U)

+#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)  /*!< 0x0000000F */

+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */

+#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */

+#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */

+#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */

+#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */

+

+#define USB_OTG_FRMNUM_Pos                       (21U)

+#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */

+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */

+#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */

+#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */

+#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */

+#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */

+

+/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/

+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)

+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/

+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)

+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */

+

+/********************  Bit definition for OTG register  ********************/

+#define USB_OTG_NPTXFSA_Pos                      (0U)

+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */

+#define USB_OTG_NPTXFD_Pos                       (16U)

+#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */

+#define USB_OTG_TX0FSA_Pos                       (0U)

+#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */

+#define USB_OTG_TX0FD_Pos                        (16U)

+#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */

+

+/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/

+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)

+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */

+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */

+

+/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/

+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)

+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */

+

+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)

+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */

+

+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)

+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/

+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)

+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */

+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */

+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)

+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */

+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */

+

+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)

+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */

+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */

+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */

+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)

+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */

+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */

+

+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)

+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */

+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */

+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)

+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */

+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */

+

+/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */

+

+/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/

+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)

+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */

+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */

+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)

+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */

+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */

+

+/********************  Bit definition forUSB_OTG_GCCFG register  ********************/

+#define USB_OTG_GCCFG_DCDET_Pos                  (0U)

+#define USB_OTG_GCCFG_DCDET_Msk                  (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */

+#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */

+#define USB_OTG_GCCFG_PDET_Pos                   (1U)

+#define USB_OTG_GCCFG_PDET_Msk                   (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */

+#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */

+#define USB_OTG_GCCFG_SDET_Pos                   (2U)

+#define USB_OTG_GCCFG_SDET_Msk                   (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */

+#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */

+#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)

+#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */

+#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */

+#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)

+#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */

+#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */

+#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)

+#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */

+#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */

+#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)

+#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */

+#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/

+#define USB_OTG_GCCFG_PDEN_Pos                   (19U)

+#define USB_OTG_GCCFG_PDEN_Msk                   (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */

+#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/

+#define USB_OTG_GCCFG_SDEN_Pos                   (20U)

+#define USB_OTG_GCCFG_SDEN_Msk                   (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */

+#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */

+#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)

+#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */

+#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */

+

+/********************  Bit definition forUSB_OTG_GPWRDN) register  ********************/

+#define USB_OTG_GPWRDN_ADPMEN_Pos                (0U)

+#define USB_OTG_GPWRDN_ADPMEN_Msk                (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */

+#define USB_OTG_GPWRDN_ADPMEN                    USB_OTG_GPWRDN_ADPMEN_Msk     /*!< ADP module enable */

+#define USB_OTG_GPWRDN_ADPIF_Pos                 (23U)

+#define USB_OTG_GPWRDN_ADPIF_Msk                 (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */

+#define USB_OTG_GPWRDN_ADPIF                     USB_OTG_GPWRDN_ADPIF_Msk      /*!< ADP Interrupt flag */

+

+/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/

+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)

+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */

+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)

+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */

+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */

+

+/********************  Bit definition forUSB_OTG_CID register  ********************/

+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)

+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */

+

+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/

+#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)

+#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */

+#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */

+#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)

+#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */

+#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */

+#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)

+#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */

+#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */

+#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)

+#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */

+#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */

+#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)

+#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */

+#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */

+#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)

+#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */

+#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */

+#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)

+#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */

+#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */

+#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)

+#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */

+#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */

+#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)

+#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */

+#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */

+#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)

+#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */

+#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */

+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)

+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */

+#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */

+#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)

+#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */

+#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */

+#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)

+#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */

+#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */

+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)

+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */

+#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */

+#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)

+#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */

+#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */

+

+/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/

+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)

+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */

+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)

+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */

+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)

+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */

+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)

+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */

+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)

+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */

+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)

+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */

+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)

+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */

+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)

+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */

+

+/********************  Bit definition forUSB_OTG_HPRT register  ********************/

+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)

+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */

+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */

+#define USB_OTG_HPRT_PCDET_Pos                   (1U)

+#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */

+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */

+#define USB_OTG_HPRT_PENA_Pos                    (2U)

+#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */

+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */

+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)

+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */

+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */

+#define USB_OTG_HPRT_POCA_Pos                    (4U)

+#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */

+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */

+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)

+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */

+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */

+#define USB_OTG_HPRT_PRES_Pos                    (6U)

+#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */

+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume   */

+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)

+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */

+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend  */

+#define USB_OTG_HPRT_PRST_Pos                    (8U)

+#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */

+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset    */

+

+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)

+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */

+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */

+#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */

+#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */

+#define USB_OTG_HPRT_PPWR_Pos                    (12U)

+#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */

+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */

+

+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)

+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */

+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */

+#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */

+#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */

+#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */

+#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */

+

+#define USB_OTG_HPRT_PSPD_Pos                    (17U)

+#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */

+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */

+#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */

+#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */

+

+/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/

+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)

+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)

+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)

+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */

+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)

+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */

+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)

+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */

+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)

+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */

+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)

+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)

+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)

+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)

+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */

+

+/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/

+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)

+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */

+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)

+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/

+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)

+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */

+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)

+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */

+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */

+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)

+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */

+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */

+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)

+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */

+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */

+

+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)

+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */

+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */

+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)

+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */

+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */

+

+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)

+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */

+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */

+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */

+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */

+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */

+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */

+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)

+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */

+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */

+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)

+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */

+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */

+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)

+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */

+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)

+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */

+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)

+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */

+

+/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/

+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)

+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */

+

+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)

+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */

+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */

+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */

+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */

+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */

+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */

+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)

+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */

+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */

+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)

+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */

+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */

+

+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)

+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */

+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */

+

+#define USB_OTG_HCCHAR_MC_Pos                    (20U)

+#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */

+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */

+#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */

+#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */

+

+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)

+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */

+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */

+#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */

+#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */

+#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */

+#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */

+#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */

+#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */

+#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */

+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)

+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */

+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)

+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */

+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)

+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */

+

+/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/

+

+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)

+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */

+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */

+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */

+

+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)

+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */

+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */

+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */

+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */

+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */

+

+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)

+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */

+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */

+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */

+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */

+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)

+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */

+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */

+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)

+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */

+

+/********************  Bit definition forUSB_OTG_HCINT register  ********************/

+#define USB_OTG_HCINT_XFRC_Pos                   (0U)

+#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */

+#define USB_OTG_HCINT_CHH_Pos                    (1U)

+#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */

+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)

+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */

+#define USB_OTG_HCINT_STALL_Pos                  (3U)

+#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */

+#define USB_OTG_HCINT_NAK_Pos                    (4U)

+#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */

+#define USB_OTG_HCINT_ACK_Pos                    (5U)

+#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */

+#define USB_OTG_HCINT_NYET_Pos                   (6U)

+#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */

+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */

+#define USB_OTG_HCINT_TXERR_Pos                  (7U)

+#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */

+#define USB_OTG_HCINT_BBERR_Pos                  (8U)

+#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */

+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)

+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */

+#define USB_OTG_HCINT_DTERR_Pos                  (10U)

+#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */

+

+/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/

+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)

+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */

+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)

+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */

+#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)

+#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */

+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)

+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */

+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)

+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */

+#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)

+#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */

+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)

+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */

+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)

+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */

+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */

+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)

+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */

+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)

+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */

+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)

+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */

+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */

+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)

+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */

+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */

+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)

+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */

+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */

+

+/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/

+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)

+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */

+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)

+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */

+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)

+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */

+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)

+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */

+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)

+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */

+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)

+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */

+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)

+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */

+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */

+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)

+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */

+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)

+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */

+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)

+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */

+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)

+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */

+

+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/

+

+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)

+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */

+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)

+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */

+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)

+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */

+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */

+/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/

+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)

+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */

+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)

+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */

+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)

+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */

+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)

+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */

+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */

+#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */

+#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/

+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)

+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */

+

+/********************  Bit definition forUSB_OTG_HCDMA register  ********************/

+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)

+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */

+

+/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/

+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)

+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */

+

+/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/

+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)

+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */

+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)

+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/

+

+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)

+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */

+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)

+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */

+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */

+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)

+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */

+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */

+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)

+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */

+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)

+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */

+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */

+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)

+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */

+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */

+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)

+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */

+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */

+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)

+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */

+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */

+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)

+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */

+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */

+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)

+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */

+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)

+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */

+

+/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/

+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)

+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */

+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)

+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */

+#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)

+#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */

+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)

+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */

+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)

+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */

+#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)

+#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< OUT Status Phase Received interrupt */

+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)

+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */

+#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)

+#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */

+#define USB_OTG_DOEPINT_BNA_Pos                  (9U)

+#define USB_OTG_DOEPINT_BNA_Msk                  (0x1UL << USB_OTG_DOEPINT_BNA_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPINT_BNA                      USB_OTG_DOEPINT_BNA_Msk   /*!< Buffer not available interrupt */

+#define USB_OTG_DOEPINT_BERR_Pos                 (12U)

+#define USB_OTG_DOEPINT_BERR_Msk                 (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPINT_BERR                      USB_OTG_DOEPINT_BERR_Msk   /*!< Babble error interrupt */

+#define USB_OTG_DOEPINT_NAK_Pos                  (13U)

+#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */

+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)

+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */

+#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)

+#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */

+#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */

+

+/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/

+

+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)

+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */

+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)

+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */

+

+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)

+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */

+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */

+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */

+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition for PCGCCTL register  ********************/

+#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)

+#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */

+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */

+#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)

+#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */

+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */

+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)

+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */

+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/** @addtogroup Exported_macros

+  * @{

+  */

+

+/******************************* ADC Instances ********************************/

+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \

+                                       ((INSTANCE) == ADC2))

+

+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)

+

+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)

+

+/******************************** COMP Instances ******************************/

+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \

+                                       ((INSTANCE) == COMP2))

+

+#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)

+/******************** COMP Instances with window mode capability **************/

+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)

+

+/******************************** DTS Instances ******************************/

+#define IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS)

+

+/******************************* CRC Instances ********************************/

+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

+

+/******************************* DAC Instances ********************************/

+#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1)|| \

+                                       ((INSTANCE) == DAC2))

+/******************************* DCMI Instances *******************************/

+#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)

+

+/******************************* DELAYBLOCK Instances *******************************/

+#define IS_DLYB_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DLYB_SDMMC1) || \

+                                         ((INSTANCE) == DLYB_SDMMC2) || \

+                                         ((INSTANCE) == DLYB_OCTOSPI1) || \

+                                         ((INSTANCE) == DLYB_OCTOSPI2) )

+/****************************** DFSDM Instances *******************************/

+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \

+                                         ((INSTANCE) == DFSDM1_Filter1) || \

+                                         ((INSTANCE) == DFSDM1_Filter2) || \

+                                         ((INSTANCE) == DFSDM1_Filter3) || \

+                                         ((INSTANCE) == DFSDM1_Filter4) || \

+                                         ((INSTANCE) == DFSDM1_Filter5) || \

+                                         ((INSTANCE) == DFSDM1_Filter6) || \

+                                         ((INSTANCE) == DFSDM1_Filter7) || \

+                                         ((INSTANCE) == DFSDM2_Filter0))

+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \

+                                                 ((INSTANCE) == DFSDM1_Channel1) || \

+                                                 ((INSTANCE) == DFSDM1_Channel2) || \

+                                                 ((INSTANCE) == DFSDM1_Channel3) || \

+                                                 ((INSTANCE) == DFSDM1_Channel4) || \

+                                                 ((INSTANCE) == DFSDM1_Channel5) || \

+                                                 ((INSTANCE) == DFSDM1_Channel6) || \

+                                                 ((INSTANCE) == DFSDM1_Channel7) || \

+                                                 ((INSTANCE) == DFSDM2_Channel0) || \

+                                                 ((INSTANCE) == DFSDM2_Channel1))

+/****************************** RAMECC Instances ******************************/

+#define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC_Monitor1)   || \

+                                                  ((INSTANCE) == RAMECC_Monitor2)   || \

+                                                  ((INSTANCE) == RAMECC_Monitor3))

+

+/******************************** DMA Instances *******************************/

+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \

+                                       ((INSTANCE) == DMA1_Stream1)   || \

+                                       ((INSTANCE) == DMA1_Stream2)   || \

+                                       ((INSTANCE) == DMA1_Stream3)   || \

+                                       ((INSTANCE) == DMA1_Stream4)   || \

+                                       ((INSTANCE) == DMA1_Stream5)   || \

+                                       ((INSTANCE) == DMA1_Stream6)   || \

+                                       ((INSTANCE) == DMA1_Stream7)   || \

+                                       ((INSTANCE) == DMA2_Stream0)   || \

+                                       ((INSTANCE) == DMA2_Stream1)   || \

+                                       ((INSTANCE) == DMA2_Stream2)   || \

+                                       ((INSTANCE) == DMA2_Stream3)   || \

+                                       ((INSTANCE) == DMA2_Stream4)   || \

+                                       ((INSTANCE) == DMA2_Stream5)   || \

+                                       ((INSTANCE) == DMA2_Stream6)   || \

+                                       ((INSTANCE) == DMA2_Stream7)   || \

+                                       ((INSTANCE) == BDMA1_Channel0) || \

+                                       ((INSTANCE) == BDMA1_Channel1) || \

+                                       ((INSTANCE) == BDMA1_Channel2) || \

+                                       ((INSTANCE) == BDMA1_Channel3) || \

+                                       ((INSTANCE) == BDMA1_Channel4) || \

+                                       ((INSTANCE) == BDMA1_Channel5) || \

+                                       ((INSTANCE) == BDMA1_Channel6) || \

+                                       ((INSTANCE) == BDMA1_Channel7) || \

+                                       ((INSTANCE) == BDMA2_Channel0) || \

+                                       ((INSTANCE) == BDMA2_Channel1) || \

+                                       ((INSTANCE) == BDMA2_Channel2) || \

+                                       ((INSTANCE) == BDMA2_Channel3) || \

+                                       ((INSTANCE) == BDMA2_Channel4) || \

+                                       ((INSTANCE) == BDMA2_Channel5) || \

+                                       ((INSTANCE) == BDMA2_Channel6) || \

+                                       ((INSTANCE) == BDMA2_Channel7))

+

+/****************************** BDMA CHANNEL Instances ***************************/

+#define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA1_Channel0) || \

+                                            ((INSTANCE) == BDMA1_Channel1) || \

+                                            ((INSTANCE) == BDMA1_Channel2) || \

+                                            ((INSTANCE) == BDMA1_Channel3) || \

+                                            ((INSTANCE) == BDMA1_Channel4) || \

+                                            ((INSTANCE) == BDMA1_Channel5) || \

+                                            ((INSTANCE) == BDMA1_Channel6) || \

+                                            ((INSTANCE) == BDMA1_Channel7) || \

+                                            ((INSTANCE) == BDMA2_Channel0) || \

+                                            ((INSTANCE) == BDMA2_Channel1) || \

+                                            ((INSTANCE) == BDMA2_Channel2) || \

+                                            ((INSTANCE) == BDMA2_Channel3) || \

+                                            ((INSTANCE) == BDMA2_Channel4) || \

+                                            ((INSTANCE) == BDMA2_Channel5) || \

+                                            ((INSTANCE) == BDMA2_Channel6) || \

+                                            ((INSTANCE) == BDMA2_Channel7))

+

+/****************************** DMA DMAMUX ALL Instances ***************************/

+#define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)    || \

+                                               ((INSTANCE) == DMA1_Stream1)    || \

+                                               ((INSTANCE) == DMA1_Stream2)    || \

+                                               ((INSTANCE) == DMA1_Stream3)    || \

+                                               ((INSTANCE) == DMA1_Stream4)    || \

+                                               ((INSTANCE) == DMA1_Stream5)    || \

+                                               ((INSTANCE) == DMA1_Stream6)    || \

+                                               ((INSTANCE) == DMA1_Stream7)    || \

+                                               ((INSTANCE) == DMA2_Stream0)    || \

+                                               ((INSTANCE) == DMA2_Stream1)    || \

+                                               ((INSTANCE) == DMA2_Stream2)    || \

+                                               ((INSTANCE) == DMA2_Stream3)    || \

+                                               ((INSTANCE) == DMA2_Stream4)    || \

+                                               ((INSTANCE) == DMA2_Stream5)    || \

+                                               ((INSTANCE) == DMA2_Stream6)    || \

+                                               ((INSTANCE) == DMA2_Stream7)    || \

+                                               ((INSTANCE) == BDMA2_Channel0)  || \

+                                               ((INSTANCE) == BDMA2_Channel1)  || \

+                                               ((INSTANCE) == BDMA2_Channel2)  || \

+                                               ((INSTANCE) == BDMA2_Channel3)  || \

+                                               ((INSTANCE) == BDMA2_Channel4)  || \

+                                               ((INSTANCE) == BDMA2_Channel5)  || \

+                                               ((INSTANCE) == BDMA2_Channel6)  || \

+                                               ((INSTANCE) == BDMA2_Channel7))

+

+/****************************** BDMA DMAMUX Instances ***************************/

+#define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == BDMA2_Channel0) || \

+                                                    ((INSTANCE) == BDMA2_Channel1) || \

+                                                    ((INSTANCE) == BDMA2_Channel2) || \

+                                                    ((INSTANCE) == BDMA2_Channel3) || \

+                                                    ((INSTANCE) == BDMA2_Channel4) || \

+                                                    ((INSTANCE) == BDMA2_Channel5) || \

+                                                    ((INSTANCE) == BDMA2_Channel6) || \

+                                                    ((INSTANCE) == BDMA2_Channel7))

+

+/****************************** DMA STREAM Instances ***************************/

+#define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \

+                                          ((INSTANCE) == DMA1_Stream1)   || \

+                                          ((INSTANCE) == DMA1_Stream2)   || \

+                                          ((INSTANCE) == DMA1_Stream3)   || \

+                                          ((INSTANCE) == DMA1_Stream4)   || \

+                                          ((INSTANCE) == DMA1_Stream5)   || \

+                                          ((INSTANCE) == DMA1_Stream6)   || \

+                                          ((INSTANCE) == DMA1_Stream7)   || \

+                                          ((INSTANCE) == DMA2_Stream0)   || \

+                                          ((INSTANCE) == DMA2_Stream1)   || \

+                                          ((INSTANCE) == DMA2_Stream2)   || \

+                                          ((INSTANCE) == DMA2_Stream3)   || \

+                                          ((INSTANCE) == DMA2_Stream4)   || \

+                                          ((INSTANCE) == DMA2_Stream5)   || \

+                                          ((INSTANCE) == DMA2_Stream6)   || \

+                                          ((INSTANCE) == DMA2_Stream7))

+

+/****************************** DMA DMAMUX Instances ***************************/

+#define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)   || \

+                                                  ((INSTANCE) == DMA1_Stream1)   || \

+                                                  ((INSTANCE) == DMA1_Stream2)   || \

+                                                  ((INSTANCE) == DMA1_Stream3)   || \

+                                                  ((INSTANCE) == DMA1_Stream4)   || \

+                                                  ((INSTANCE) == DMA1_Stream5)   || \

+                                                  ((INSTANCE) == DMA1_Stream6)   || \

+                                                  ((INSTANCE) == DMA1_Stream7)   || \

+                                                  ((INSTANCE) == DMA2_Stream0)   || \

+                                                  ((INSTANCE) == DMA2_Stream1)   || \

+                                                  ((INSTANCE) == DMA2_Stream2)   || \

+                                                  ((INSTANCE) == DMA2_Stream3)   || \

+                                                  ((INSTANCE) == DMA2_Stream4)   || \

+                                                  ((INSTANCE) == DMA2_Stream5)   || \

+                                                  ((INSTANCE) == DMA2_Stream6)   || \

+                                                  ((INSTANCE) == DMA2_Stream7))

+

+/******************************** DMA Request Generator Instances **************/

+#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator1) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator2) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator3) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator4) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator5) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator6) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator7) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator0) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator1) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator2) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator3) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator4) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator5) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator6) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator7))

+

+/******************************* DMA2D Instances *******************************/

+#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)

+

+/******************************* OTFDEC Instances ******************************/

+#define IS_OTFDEC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == OTFDEC1) || \

+                                              ((__INSTANCE__) == OTFDEC2))

+

+/****************************** PSSI Instance *********************************/

+#define IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI)

+

+/******************************** MDMA Request Generator Instances **************/

+#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0)  || \

+                                               ((INSTANCE) == MDMA_Channel1)  || \

+                                               ((INSTANCE) == MDMA_Channel2)  || \

+                                               ((INSTANCE) == MDMA_Channel3)  || \

+                                               ((INSTANCE) == MDMA_Channel4)  || \

+                                               ((INSTANCE) == MDMA_Channel5)  || \

+                                               ((INSTANCE) == MDMA_Channel6)  || \

+                                               ((INSTANCE) == MDMA_Channel7)  || \

+                                               ((INSTANCE) == MDMA_Channel8)  || \

+                                               ((INSTANCE) == MDMA_Channel9)  || \

+                                               ((INSTANCE) == MDMA_Channel10) || \

+                                               ((INSTANCE) == MDMA_Channel11) || \

+                                               ((INSTANCE) == MDMA_Channel12) || \

+                                               ((INSTANCE) == MDMA_Channel13) || \

+                                               ((INSTANCE) == MDMA_Channel14) || \

+                                               ((INSTANCE) == MDMA_Channel15))

+

+

+/******************************* FDCAN Instances ******************************/

+#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \

+                                             ((__INSTANCE__) == FDCAN2))

+

+#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)

+

+/******************************* GFXMMU Instances *******************************/

+#define IS_GFXMMU_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GFXMMU)

+

+/******************************* GPIO Instances *******************************/

+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \

+                                        ((INSTANCE) == GPIOB) || \

+                                        ((INSTANCE) == GPIOC) || \

+                                        ((INSTANCE) == GPIOD) || \

+                                        ((INSTANCE) == GPIOE) || \

+                                        ((INSTANCE) == GPIOF) || \

+                                        ((INSTANCE) == GPIOG) || \

+                                        ((INSTANCE) == GPIOH) || \

+                                        ((INSTANCE) == GPIOI) || \

+                                        ((INSTANCE) == GPIOJ) || \

+                                        ((INSTANCE) == GPIOK))

+

+/******************************* GPIO AF Instances ****************************/

+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)

+

+/**************************** GPIO Lock Instances *****************************/

+/* On H7, all GPIO Bank support the Lock mechanism */

+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)

+

+/******************************** HSEM Instances *******************************/

+#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)

+#define HSEM_CPU1_COREID         (0x00000001U) /* Semaphore Core CM7 ID */

+#define HSEM_CR_COREID_CPU1      (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)

+#define HSEM_CR_COREID_CURRENT   (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)

+

+#define HSEM_SEMID_MIN     (0U)       /* HSEM ID Min*/

+#define HSEM_SEMID_MAX     (15U)      /* HSEM ID Max */

+

+#define HSEM_PROCESSID_MIN (0U)       /* HSEM Process ID Min */

+#define HSEM_PROCESSID_MAX (255U)     /* HSEM Process ID Max */

+

+#define HSEM_CLEAR_KEY_MIN (0U)       /* HSEM clear Key Min value */

+#define HSEM_CLEAR_KEY_MAX (0xFFFFU)  /* HSEM clear Key Max value */

+

+/******************************** I2C Instances *******************************/

+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

+                                       ((INSTANCE) == I2C2) || \

+                                       ((INSTANCE) == I2C3) || \

+                                       ((INSTANCE) == I2C4))

+/************** I2C Instances : wakeup capability from stop modes *************/

+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)

+

+/****************************** SMBUS Instances *******************************/

+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

+                                         ((INSTANCE) == I2C2) || \

+                                         ((INSTANCE) == I2C3) || \

+                                         ((INSTANCE) == I2C4))

+/******************************** I2S Instances *******************************/

+#define IS_I2S_ALL_INSTANCE(INSTANCE)   (((INSTANCE) == SPI1) || \

+                                         ((INSTANCE) == SPI2) || \

+                                         ((INSTANCE) == SPI3) || \

+                                         ((INSTANCE) == SPI6))

+

+/****************************** LTDC Instances ********************************/

+#define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)

+

+/******************************* RNG Instances ********************************/

+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)

+

+/****************************** RTC Instances *********************************/

+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)

+

+/****************************** SDMMC Instances *********************************/

+#define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \

+                                           ((_INSTANCE_) == SDMMC2))

+

+/******************************** SMBUS Instances *****************************/

+#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)

+

+/******************************** SPI Instances *******************************/

+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \

+                                       ((INSTANCE) == SPI2) || \

+                                       ((INSTANCE) == SPI3) || \

+                                       ((INSTANCE) == SPI4) || \

+                                       ((INSTANCE) == SPI5) || \

+                                       ((INSTANCE) == SPI6))

+

+#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \

+                                           ((INSTANCE) == SPI2) || \

+                                           ((INSTANCE) == SPI3))

+

+/******************************** SWPMI Instances *****************************/

+#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)

+

+/****************** LPTIM Instances : All supported instances *****************/

+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \

+                                         ((INSTANCE) == LPTIM2) || \

+                                         ((INSTANCE) == LPTIM3))

+

+/****************** LPTIM Instances : supporting encoder interface **************/

+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \

+                                                           ((INSTANCE) == LPTIM2))

+

+/****************** TIM Instances : All supported instances *******************/

+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM6)   || \

+                                         ((INSTANCE) == TIM7)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM13)  || \

+                                         ((INSTANCE) == TIM14)  || \

+                                         ((INSTANCE) == TIM15)  || \

+                                         ((INSTANCE) == TIM16)  || \

+                                         ((INSTANCE) == TIM17))

+

+/************* TIM Instances : at least 1 capture/compare channel *************/

+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM13)  || \

+                                         ((INSTANCE) == TIM14)  || \

+                                         ((INSTANCE) == TIM15)  || \

+                                         ((INSTANCE) == TIM16)  || \

+                                         ((INSTANCE) == TIM17))

+

+/************ TIM Instances : at least 2 capture/compare channels *************/

+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM15))

+

+/************ TIM Instances : at least 3 capture/compare channels *************/

+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8))

+

+/************ TIM Instances : at least 4 capture/compare channels *************/

+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8))

+

+/************ TIM Instances : at least 5 capture/compare channels *************/

+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM8))

+/************ TIM Instances : at least 6 capture/compare channels *************/

+#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM8))

+

+/******************** TIM Instances : Advanced-control timers *****************/

+#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \

+                                                ((__INSTANCE__) == TIM8))

+

+/******************** TIM Instances : Advanced-control timers *****************/

+

+/******************* TIM Instances : Timer input XOR function *****************/

+#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : DMA requests generation (UDE) *************/

+#define IS_TIM_DMA_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM6)   || \

+                                           ((INSTANCE) == TIM7)   || \

+                                           ((INSTANCE) == TIM8)   || \

+                                           ((INSTANCE) == TIM15)  || \

+                                           ((INSTANCE) == TIM16)  || \

+                                           ((INSTANCE) == TIM17))

+

+/************ TIM Instances : DMA requests generation (CCxDE) *****************/

+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15)  || \

+                                            ((INSTANCE) == TIM16)  || \

+                                            ((INSTANCE) == TIM17))

+

+/************ TIM Instances : DMA requests generation (COMDE) *****************/

+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15))

+

+/******************** TIM Instances : DMA burst feature ***********************/

+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8))

+

+/*************** TIM Instances : external trigger reamp input available *******/

+#define IS_TIM_ETR_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : remapping capability **********************/

+#define IS_TIM_REMAP_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \

+                                          ((INSTANCE) == TIM2)  || \

+                                          ((INSTANCE) == TIM3)  || \

+                                          ((INSTANCE) == TIM5)  || \

+                                          ((INSTANCE) == TIM8)  || \

+                                          ((INSTANCE) == TIM16) || \

+                                          ((INSTANCE) == TIM17))

+

+/*************** TIM Instances : external trigger reamp input available *******/

+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                              ((INSTANCE) == TIM2)   || \

+                                              ((INSTANCE) == TIM3)   || \

+                                              ((INSTANCE) == TIM5)   || \

+                                              ((INSTANCE) == TIM8))

+

+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/

+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM6)   || \

+                                            ((INSTANCE) == TIM7)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15))

+

+/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/

+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM8)   || \

+                                           ((INSTANCE) == TIM12))

+

+/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/

+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM8))

+

+/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/

+#define IS_TIM_TISEL_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)   || \

+                                          ((INSTANCE) == TIM2)   || \

+                                          ((INSTANCE) == TIM3)   || \

+                                          ((INSTANCE) == TIM4)   || \

+                                          ((INSTANCE) == TIM5)   || \

+                                          ((INSTANCE) == TIM8)   || \

+                                          ((INSTANCE) == TIM15)  || \

+                                          ((INSTANCE) == TIM16)  || \

+                                          ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting commutation event *************/

+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \

+                                                     ((INSTANCE) == TIM8)    || \

+                                                     ((INSTANCE) == TIM15)   || \

+                                                     ((INSTANCE) == TIM16)   || \

+                                                     ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting encoder interface **************/

+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1)  || \

+                                                      ((__INSTANCE__) == TIM2)      || \

+                                                      ((__INSTANCE__) == TIM3)      || \

+                                                      ((__INSTANCE__) == TIM4)      || \

+                                                      ((__INSTANCE__) == TIM5)      || \

+                                                      ((__INSTANCE__) == TIM8))

+

+/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/

+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                                       ((INSTANCE) == TIM8))

+/******************* TIM Instances : output(s) available **********************/

+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \

+    ((((INSTANCE) == TIM1) &&                  \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4) ||          \

+      ((CHANNEL) == TIM_CHANNEL_5) ||          \

+      ((CHANNEL) == TIM_CHANNEL_6)))           \

+     ||                                        \

+     (((INSTANCE) == TIM2) &&                  \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM3) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1)||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM4) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM5) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM8) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4) ||          \

+      ((CHANNEL) == TIM_CHANNEL_5) ||          \

+      ((CHANNEL) == TIM_CHANNEL_6)))           \

+  ||                                           \

+     (((INSTANCE) == TIM12) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2)))           \

+  ||                                           \

+     (((INSTANCE) == TIM13) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM14) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM15) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+     ((CHANNEL) == TIM_CHANNEL_2)))            \

+  ||                                           \

+     (((INSTANCE) == TIM16) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM17) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1))))

+

+/****************** TIM Instances : supporting the break function *************/

+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\

+      (((INSTANCE) == TIM1)    || \

+      ((INSTANCE) == TIM8)     || \

+       ((INSTANCE) == TIM15)   || \

+       ((INSTANCE) == TIM16)   || \

+       ((INSTANCE) == TIM17))

+

+/************** TIM Instances : supporting Break source selection *************/

+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \

+                                               ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting complementary output(s) ********/

+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \

+   ((((INSTANCE) == TIM1) &&                    \

+     (((CHANNEL) == TIM_CHANNEL_1) ||           \

+      ((CHANNEL) == TIM_CHANNEL_2) ||           \

+      ((CHANNEL) == TIM_CHANNEL_3)))            \

+ ||                                             \

+      (((INSTANCE) == TIM8) &&                  \

+      (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||           \

+      ((CHANNEL) == TIM_CHANNEL_3)))            \

+    ||                                          \

+    (((INSTANCE) == TIM15) &&                   \

+      ((CHANNEL) == TIM_CHANNEL_1))             \

+    ||                                          \

+    (((INSTANCE) == TIM16) &&                   \

+     ((CHANNEL) == TIM_CHANNEL_1))              \

+    ||                                          \

+    (((INSTANCE) == TIM17) &&                   \

+     ((CHANNEL) == TIM_CHANNEL_1)))

+

+/****************** TIM Instances : supporting counting mode selection ********/

+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting repetition counter *************/

+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15)   || \

+   ((INSTANCE) == TIM16)   || \

+   ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting synchronization ****************/

+#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\

+    (((__INSTANCE__) == TIM1)    || \

+     ((__INSTANCE__) == TIM2)    || \

+     ((__INSTANCE__) == TIM3)    || \

+     ((__INSTANCE__) == TIM4)    || \

+     ((__INSTANCE__) == TIM5)    || \

+     ((__INSTANCE__) == TIM6)    || \

+     ((__INSTANCE__) == TIM8)    || \

+     ((__INSTANCE__) == TIM12)   || \

+     ((__INSTANCE__) == TIM15))

+

+/****************** TIM Instances : supporting clock division *****************/

+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15)   || \

+   ((INSTANCE) == TIM16)   || \

+   ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting external clock mode 1 for ETRF input */

+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting external clock mode 2 **********/

+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\

+ (((INSTANCE) == TIM1)     || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/

+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/

+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : supporting OCxREF clear *******************/

+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3))

+

+/****************** TIM Instances : TIM_32B_COUNTER ***************************/

+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM5))

+

+/****************** TIM Instances : TIM_BKIN2 ***************************/

+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting Hall sensor interface **********/

+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)  || \

+                                                             ((__INSTANCE__) == TIM2)  || \

+                                                             ((__INSTANCE__) == TIM3)  || \

+                                                             ((__INSTANCE__) == TIM4)  || \

+                                                             ((__INSTANCE__) == TIM5)  || \

+                                                             ((__INSTANCE__) == TIM15) || \

+                                                             ((__INSTANCE__) == TIM8))

+

+/******************** USART Instances : Synchronous mode **********************/

+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                     ((INSTANCE) == USART2) || \

+                                     ((INSTANCE) == USART3) || \

+                                     ((INSTANCE) == USART6) || \

+                                     ((INSTANCE) == USART10))

+

+/******************** USART Instances : SPI slave mode ************************/

+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                              ((INSTANCE) == USART2) || \

+                                              ((INSTANCE) == USART3) || \

+                                              ((INSTANCE) == USART6) || \

+                                              ((INSTANCE) == USART10))

+

+/******************** UART Instances : Asynchronous mode **********************/

+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                    ((INSTANCE) == USART2) || \

+                                    ((INSTANCE) == USART3) || \

+                                    ((INSTANCE) == UART4)  || \

+                                    ((INSTANCE) == UART5)  || \

+                                    ((INSTANCE) == USART6) || \

+                                    ((INSTANCE) == UART7)  || \

+                                    ((INSTANCE) == UART8)  || \

+                                    ((INSTANCE) == UART9)  || \

+                                    ((INSTANCE) == USART10))

+

+/******************** UART Instances : FIFO mode.******************************/

+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                         ((INSTANCE) == USART2) || \

+                                         ((INSTANCE) == USART3) || \

+                                         ((INSTANCE) == UART4)  || \

+                                         ((INSTANCE) == UART5)  || \

+                                         ((INSTANCE) == USART6) || \

+                                         ((INSTANCE) == UART7)  || \

+                                         ((INSTANCE) == UART8)  || \

+                                         ((INSTANCE) == UART9)  || \

+                                         ((INSTANCE) == USART10)|| \

+                                         ((INSTANCE) == LPUART1))

+

+/****************** UART Instances : Auto Baud Rate detection *****************/

+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                            ((INSTANCE) == USART2) || \

+                                                            ((INSTANCE) == USART3) || \

+                                                            ((INSTANCE) == UART4)  || \

+                                                            ((INSTANCE) == UART5)  || \

+                                                            ((INSTANCE) == USART6) || \

+                                                            ((INSTANCE) == UART7)  || \

+                                                            ((INSTANCE) == UART8)  || \

+                                                            ((INSTANCE) == UART9)  || \

+                                                            ((INSTANCE) == USART10))

+

+/*********************** UART Instances : Driver Enable ***********************/

+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                  ((INSTANCE) == USART2) || \

+                                                  ((INSTANCE) == USART3) || \

+                                                  ((INSTANCE) == UART4)  || \

+                                                  ((INSTANCE) == UART5)  || \

+                                                  ((INSTANCE) == USART6) || \

+                                                  ((INSTANCE) == UART7)  || \

+                                                  ((INSTANCE) == UART8)  || \

+                                                  ((INSTANCE) == UART9)  || \

+                                                  ((INSTANCE) == USART10)|| \

+                                                  ((INSTANCE) == LPUART1))

+

+/********************* UART Instances : Half-Duplex mode **********************/

+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                               ((INSTANCE) == USART2) || \

+                                               ((INSTANCE) == USART3) || \

+                                               ((INSTANCE) == UART4)  || \

+                                               ((INSTANCE) == UART5)  || \

+                                               ((INSTANCE) == USART6) || \

+                                               ((INSTANCE) == UART7)  || \

+                                               ((INSTANCE) == UART8)  || \

+                                               ((INSTANCE) == UART9)  || \

+                                               ((INSTANCE) == USART10)|| \

+                                               ((INSTANCE) == LPUART1))

+

+/******************* UART Instances : Hardware Flow control *******************/

+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                           ((INSTANCE) == USART2) || \

+                                           ((INSTANCE) == USART3) || \

+                                           ((INSTANCE) == UART4)  || \

+                                           ((INSTANCE) == UART5)  || \

+                                           ((INSTANCE) == USART6) || \

+                                           ((INSTANCE) == UART7)  || \

+                                           ((INSTANCE) == UART8)  || \

+                                           ((INSTANCE) == UART9)  || \

+                                           ((INSTANCE) == USART10)|| \

+                                           ((INSTANCE) == LPUART1))

+

+/************************* UART Instances : LIN mode **************************/

+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                        ((INSTANCE) == USART2) || \

+                                        ((INSTANCE) == USART3) || \

+                                        ((INSTANCE) == UART4)  || \

+                                        ((INSTANCE) == UART5)  || \

+                                        ((INSTANCE) == USART6) || \

+                                        ((INSTANCE) == UART7)  || \

+                                        ((INSTANCE) == UART8)  || \

+                                        ((INSTANCE) == UART9)  || \

+                                        ((INSTANCE) == USART10))

+

+/****************** UART Instances : Wake-up from Stop mode *******************/

+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                    ((INSTANCE) == USART2) || \

+                                                    ((INSTANCE) == USART3) || \

+                                                    ((INSTANCE) == UART4)  || \

+                                                    ((INSTANCE) == UART5)  || \

+                                                    ((INSTANCE) == USART6) || \

+                                                    ((INSTANCE) == UART7)  || \

+                                                    ((INSTANCE) == UART8)  || \

+                                                    ((INSTANCE) == UART9)  || \

+                                                    ((INSTANCE) == USART10)|| \

+                                                    ((INSTANCE) == LPUART1))

+

+/************************* UART Instances : IRDA mode *************************/

+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                    ((INSTANCE) == USART2) || \

+                                    ((INSTANCE) == USART3) || \

+                                    ((INSTANCE) == UART4)  || \

+                                    ((INSTANCE) == UART5)  || \

+                                    ((INSTANCE) == USART6) || \

+                                    ((INSTANCE) == UART7)  || \

+                                    ((INSTANCE) == UART8)  || \

+                                    ((INSTANCE) == UART9)  || \

+                                    ((INSTANCE) == USART10))

+

+/********************* USART Instances : Smard card mode **********************/

+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                         ((INSTANCE) == USART2) || \

+                                         ((INSTANCE) == USART3) || \

+                                         ((INSTANCE) == USART6) ||\

+                                         ((INSTANCE) == USART10))

+

+/****************************** LPUART Instance *******************************/

+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)

+

+/****************************** IWDG Instances ********************************/

+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG1)

+/****************************** USB Instances ********************************/

+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)

+

+/****************************** WWDG Instances ********************************/

+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG1)

+/****************************** MDIOS Instances ********************************/

+#define IS_MDIOS_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == MDIOS)

+

+/****************************** CEC Instances *********************************/

+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)

+

+/****************************** SAI Instances ********************************/

+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \

+                                       ((INSTANCE) == SAI1_Block_B) || \

+                                       ((INSTANCE) == SAI2_Block_A) || \

+                                       ((INSTANCE) == SAI2_Block_B))

+

+/****************************** SPDIFRX Instances ********************************/

+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)

+

+/****************************** OPAMP Instances *******************************/

+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \

+                                         ((INSTANCE) == OPAMP2))

+

+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)

+

+/*********************** USB OTG PCD Instances ********************************/

+#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS)

+

+/*********************** USB OTG HCD Instances ********************************/

+#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS)

+

+/******************************************************************************/

+/*  For a painless codes migration between the STM32H7xx device product       */

+/*  lines, or with STM32F7xx devices the aliases defined below are put        */

+/*   in place to overcome the differences in the interrupt handlers and IRQn  */

+/*   definitions. No need to update developed interrupt code when moving      */

+/*  across product lines within the same STM32H7 Family                       */

+/******************************************************************************/

+

+/* Aliases for __IRQn */

+#define  RNG_IRQn                       HASH_RNG_IRQn

+#define  TIM1_BRK_TIM9_IRQn             TIM1_BRK_IRQn

+#define  TIM1_UP_TIM10_IRQn             TIM1_UP_IRQn

+#define  TIM1_TRG_COM_TIM11_IRQn        TIM1_TRG_COM_IRQn

+#define  PVD_IRQn                       PVD_AVD_IRQn

+

+/* Aliases for BDMA __IRQn */

+#define  BDMA_Channel0_IRQn             BDMA2_Channel0_IRQn

+#define  BDMA_Channel1_IRQn             BDMA2_Channel1_IRQn

+#define  BDMA_Channel2_IRQn             BDMA2_Channel2_IRQn

+#define  BDMA_Channel3_IRQn             BDMA2_Channel3_IRQn

+#define  BDMA_Channel4_IRQn             BDMA2_Channel4_IRQn

+#define  BDMA_Channel5_IRQn             BDMA2_Channel5_IRQn

+#define  BDMA_Channel6_IRQn             BDMA2_Channel6_IRQn

+#define  BDMA_Channel7_IRQn             BDMA2_Channel7_IRQn

+

+/* Aliases for PWR __IRQn */

+#define  PVD_AVD_IRQn                   PVD_PVM_IRQn

+

+/* Aliases for DCMI/PSSI __IRQn */

+#define  DCMI_IRQn                      DCMI_PSSI_IRQn

+

+/* Aliases for __IRQHandler */

+#define   RNG_IRQHandler               HASH_RNG_IRQHandler

+#define TIM1_BRK_TIM9_IRQHandler       TIM1_BRK_IRQHandler

+#define TIM1_UP_TIM9_IRQHandler        TIM1_UP_IRQHandler

+#define TIM1_TRG_COM_TIM11_IRQHandler  TIM1_TRG_COM_IRQHandler

+#define PVD_IRQHandler                 PVD_AVD_IRQHandler

+

+

+/* Aliases for BDMA __IRQHandler */

+#define  BDMA_Channel0_IRQHandler      BDMA2_Channel0_IRQHandler

+#define  BDMA_Channel1_IRQHandler      BDMA2_Channel1_IRQHandler

+#define  BDMA_Channel2_IRQHandler      BDMA2_Channel2_IRQHandler

+#define  BDMA_Channel3_IRQHandler      BDMA2_Channel3_IRQHandler

+#define  BDMA_Channel4_IRQHandler      BDMA2_Channel4_IRQHandler

+#define  BDMA_Channel5_IRQHandler      BDMA2_Channel5_IRQHandler

+#define  BDMA_Channel6_IRQHandler      BDMA2_Channel6_IRQHandler

+#define  BDMA_Channel7_IRQHandler      BDMA2_Channel7_IRQHandler

+

+/* Aliases for PWR __IRQHandler */

+#define  PVD_AVD_IRQHandler            PVD_PVM_IRQHandler

+

+/* Aliases for DCMI/PSSI __IRQHandler */

+#define  DCMI_IRQHandler               DCMI_PSSI_IRQHandler

+

+/* Alias for BDMA defines */

+#define BDMA_BASE              BDMA2_BASE

+#define BDMA_Channel0_BASE     BDMA2_Channel0_BASE

+#define BDMA_Channel1_BASE     BDMA2_Channel1_BASE

+#define BDMA_Channel2_BASE     BDMA2_Channel2_BASE

+#define BDMA_Channel3_BASE     BDMA2_Channel3_BASE

+#define BDMA_Channel4_BASE     BDMA2_Channel4_BASE

+#define BDMA_Channel5_BASE     BDMA2_Channel5_BASE

+#define BDMA_Channel6_BASE     BDMA2_Channel6_BASE

+#define BDMA_Channel7_BASE     BDMA2_Channel7_BASE

+

+#define BDMA                   BDMA2

+#define BDMA_Channel0          BDMA2_Channel0

+#define BDMA_Channel1          BDMA2_Channel1

+#define BDMA_Channel2          BDMA2_Channel2

+#define BDMA_Channel3          BDMA2_Channel3

+#define BDMA_Channel4          BDMA2_Channel4

+#define BDMA_Channel5          BDMA2_Channel5

+#define BDMA_Channel6          BDMA2_Channel6

+#define BDMA_Channel7          BDMA2_Channel7

+

+/* Alias for PWR defines */

+#define PWR_CPUCR_RUN_D3       PWR_CPUCR_RUN_SRD

+#define PWR_CPUCR_PDDS_D3      PWR_CPUCR_PDDS_SRD

+#define PWR_CPUCR_PDDS_D1      PWR_CPUCR_RETDS_CD

+

+#define PWR_D3CR_VOS           PWR_SRDCR_VOS

+

+#define PWR_D3CR_VOS_0         PWR_SRDCR_VOS_0

+#define PWR_D3CR_VOS_1         PWR_SRDCR_VOS_1

+#define PWR_D3CR_VOSRDY        PWR_SRDCR_VOSRDY

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif /* __cplusplus */

+

+#endif /* STM32H7B0xxQ_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7b3xx.h b/bsps/arm/stm32h7/include/stm32h7b3xx.h
new file mode 100644
index 0000000000..9e1be9abc7
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7b3xx.h
@@ -0,0 +1,22895 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7b3xx.h

+  * @author  MCD Application Team

+  * @brief   CMSIS STM32H7B3xx Device Peripheral Access Layer Header File.

+  *

+  *          This file contains:

+  *           - Data structures and the address mapping for all peripherals

+  *           - Peripheral's registers declarations and bits definition

+  *           - Macros to access peripheral's registers hardware

+  *

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/** @addtogroup CMSIS_Device

+  * @{

+  */

+

+/** @addtogroup stm32h7b3xx

+  * @{

+  */

+

+#ifndef STM32H7B3xx_H

+#define STM32H7B3xx_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif /* __cplusplus */

+

+/** @addtogroup Peripheral_interrupt_number_definition

+  * @{

+  */

+

+/**

+ * @brief STM32H7XX Interrupt Number Definition, according to the selected device

+ *        in @ref Library_configuration_section

+ */

+typedef enum

+{

+/******  Cortex-M Processor Exceptions Numbers *****************************************************************/

+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */

+  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */

+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */

+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */

+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */

+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M SV Call Interrupt                                     */

+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M Debug Monitor Interrupt                               */

+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M Pend SV Interrupt                                     */

+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M System Tick Interrupt                                 */

+/******  STM32 specific Interrupt Numbers **********************************************************************/

+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)                   */

+  PVD_PVM_IRQn                = 1,      /*!< PVD/PVM through EXTI Line detection Interrupt                     */

+  RTC_TAMP_STAMP_CSS_LSE_IRQn = 2,      /*!< Tamper, TimeStamp, CSS and LSE interrupts through the EXTI line   */

+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */

+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */

+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */

+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */

+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */

+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */

+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */

+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */

+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */

+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */

+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */

+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */

+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */

+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */

+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */

+  ADC_IRQn                    = 18,     /*!< ADC1 and  ADC2 global Interrupts                                  */

+  FDCAN1_IT0_IRQn             = 19,     /*!< FDCAN1 Interrupt line 0                                           */

+  FDCAN2_IT0_IRQn             = 20,     /*!< FDCAN2 Interrupt line 0                                           */

+  FDCAN1_IT1_IRQn             = 21,     /*!< FDCAN1 Interrupt line 1                                           */

+  FDCAN2_IT1_IRQn             = 22,     /*!< FDCAN2 Interrupt line 1                                           */

+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */

+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                              */

+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                             */

+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt                            */

+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */

+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */

+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */

+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */

+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */

+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */

+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */

+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */

+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */

+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */

+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */

+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */

+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */

+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */

+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */

+  DFSDM2_IRQn                 = 42,     /*!< DFSDM2 global Interrupt                                           */

+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */

+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */

+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */

+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */

+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */

+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */

+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */

+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */

+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */

+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */

+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */

+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */

+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */

+  DMA2_Stream0_IRQn           = 56,     /*!<   DMA2 Stream 0 global Interrupt                                  */

+  DMA2_Stream1_IRQn           = 57,     /*!<   DMA2 Stream 1 global Interrupt                                  */

+  DMA2_Stream2_IRQn           = 58,     /*!<   DMA2 Stream 2 global Interrupt                                  */

+  DMA2_Stream3_IRQn           = 59,     /*!<   DMA2 Stream 3 global Interrupt                                  */

+  DMA2_Stream4_IRQn           = 60,     /*!<   DMA2 Stream 4 global Interrupt                                  */

+  FDCAN_CAL_IRQn              = 63,     /*!< FDCAN Calibration unit Interrupt                                  */

+  DFSDM1_FLT4_IRQn            = 64,     /*!< DFSDM Filter4 Interrupt                                           */

+  DFSDM1_FLT5_IRQn            = 65,     /*!< DFSDM Filter5 Interrupt                                           */

+  DFSDM1_FLT6_IRQn            = 66,     /*!< DFSDM Filter6 Interrupt                                           */

+  DFSDM1_FLT7_IRQn            = 67,     /*!< DFSDM Filter7 Interrupt                                           */

+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */

+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */

+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */

+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */

+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */

+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */

+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */

+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */

+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */

+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */

+  DCMI_PSSI_IRQn              = 78,     /*!< DCMI and PSSI global interrupt                                    */

+  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */

+  HASH_RNG_IRQn               = 80,     /*!< HASH and RNG global interrupt                                     */

+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */

+  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */

+  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */

+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */

+  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */

+  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */

+  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */

+  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */

+  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */

+  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */

+  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */

+  OCTOSPI1_IRQn               = 92,     /*!< OCTOSPI1 global interrupt                                         */

+  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */

+  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */

+  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */

+  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */

+  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */

+  DMAMUX1_OVR_IRQn            = 102,    /*!<DMAMUX1 Overrun interrupt                                          */

+  DFSDM1_FLT0_IRQn            = 110,    /*!<DFSDM Filter1 Interrupt                                            */

+  DFSDM1_FLT1_IRQn            = 111,    /*!<DFSDM Filter2 Interrupt                                            */

+  DFSDM1_FLT2_IRQn            = 112,    /*!<DFSDM Filter3 Interrupt                                            */

+  DFSDM1_FLT3_IRQn            = 113,    /*!<DFSDM Filter4 Interrupt                                            */

+  SWPMI1_IRQn                 = 115,    /*!< Serial Wire Interface 1 global interrupt                          */

+  TIM15_IRQn                  = 116,    /*!< TIM15 global Interrupt                                            */

+  TIM16_IRQn                  = 117,    /*!< TIM16 global Interrupt                                            */

+  TIM17_IRQn                  = 118,    /*!< TIM17 global Interrupt                                            */

+  MDIOS_WKUP_IRQn             = 119,    /*!< MDIOS Wakeup  Interrupt                                           */

+  MDIOS_IRQn                  = 120,    /*!< MDIOS global Interrupt                                            */

+  JPEG_IRQn                   = 121,    /*!< JPEG global Interrupt                                             */

+  MDMA_IRQn                   = 122,    /*!< MDMA global Interrupt                                             */

+  SDMMC2_IRQn                 = 124,    /*!< SDMMC2 global Interrupt                                           */

+  HSEM1_IRQn                  = 125,    /*!< HSEM1 global Interrupt                                            */

+  DAC2_IRQn                   = 127,    /*!< DAC2 global Interrupt                                             */

+  DMAMUX2_OVR_IRQn            = 128,    /*!<DMAMUX2 Overrun interrupt                                          */

+  BDMA2_Channel0_IRQn         = 129,    /*!< BDMA2 Channel 0 global Interrupt                                  */

+  BDMA2_Channel1_IRQn         = 130,    /*!< BDMA2 Channel 1 global Interrupt                                  */

+  BDMA2_Channel2_IRQn         = 131,    /*!< BDMA2 Channel 2 global Interrupt                                  */

+  BDMA2_Channel3_IRQn         = 132,    /*!< BDMA2 Channel 3 global Interrupt                                  */

+  BDMA2_Channel4_IRQn         = 133,    /*!< BDMA2 Channel 4 global Interrupt                                  */

+  BDMA2_Channel5_IRQn         = 134,    /*!< BDMA2 Channel 5 global Interrupt                                  */

+  BDMA2_Channel6_IRQn         = 135,    /*!< BDMA2 Channel 6 global Interrupt                                  */

+  BDMA2_Channel7_IRQn         = 136,    /*!< BDMA2 Channel 7 global Interrupt                                  */

+  COMP_IRQn                   = 137 ,   /*!< COMP global Interrupt                                             */

+  LPTIM2_IRQn                 = 138,    /*!< LP TIM2 global interrupt                                          */

+  LPTIM3_IRQn                 = 139,    /*!< LP TIM3 global interrupt                                          */

+  UART9_IRQn                  = 140,    /*!< UART9 global interrupt                                            */

+  USART10_IRQn                = 141,    /*!< USART10 global interrupt                                          */

+  LPUART1_IRQn                = 142,    /*!< LP UART1 interrupt                                                */

+  WWDG_RST_IRQn               = 143,    /*!<Window Watchdog Event interrupt                                    */

+  CRS_IRQn                    = 144,    /*!< Clock Recovery Global Interrupt                                   */

+  ECC_IRQn                    = 145,    /*!< ECC diagnostic Global Interrupt                                   */

+  DTS_IRQn                    = 147,    /*!< Digital Temperature Sensor Global Interrupt                       */

+  WAKEUP_PIN_IRQn             = 149,    /*!< Interrupt for all 6 wake-up pins                                  */

+  OCTOSPI2_IRQn               = 150,    /*!< OctoSPI2 global interrupt                                         */

+  OTFDEC1_IRQn                = 151,    /*!< OTFDEC1 global interrupt                                          */

+  OTFDEC2_IRQn                = 152,    /*!< OTFDEC2 global interrupt                                          */

+  GFXMMU_IRQn                 = 153,    /*!< GFXMMU global interrupt                                           */

+  BDMA1_IRQn                  = 154,    /*!< BDMA1 for DFSM global interrupt                                   */

+} IRQn_Type;

+

+/**

+  * @}

+  */

+

+/** @addtogroup Configuration_section_for_CMSIS

+  * @{

+  */

+

+

+

+

+/**

+  * @brief Configuration of the Cortex-M7 Processor and Core Peripherals

+   */

+#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */

+#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */

+#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */

+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */

+#define __FPU_PRESENT             1       /*!< FPU present                                   */

+#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */

+#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */

+#include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */

+

+/**

+  * @}

+  */

+

+

+

+

+#include "system_stm32h7xx.h"

+#include <stdint.h>

+

+/** @addtogroup Peripheral_registers_structures

+  * @{

+  */

+

+/**

+  * @brief Analog to Digital Converter

+  */

+

+typedef struct

+{

+  __IO uint32_t ISR;              /*!< ADC Interrupt and Status Register,                          Address offset: 0x00 */

+  __IO uint32_t IER;              /*!< ADC Interrupt Enable Register,                              Address offset: 0x04 */

+  __IO uint32_t CR;               /*!< ADC control register,                                       Address offset: 0x08 */

+  __IO uint32_t CFGR;             /*!< ADC Configuration register,                                 Address offset: 0x0C */

+  __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                               Address offset: 0x10 */

+  __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                                 Address offset: 0x14 */

+  __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                                 Address offset: 0x18 */

+  __IO uint32_t PCSEL;            /*!< ADC pre-channel selection,                                  Address offset: 0x1C */

+  __IO uint32_t LTR1;             /*!< ADC watchdog Lower threshold register 1,                    Address offset: 0x20 */

+  __IO uint32_t HTR1;             /*!< ADC watchdog higher threshold register 1,                   Address offset: 0x24 */

+  uint32_t      RESERVED1;        /*!< Reserved, 0x028                                                                  */

+  uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                                  */

+  __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                            Address offset: 0x30 */

+  __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                            Address offset: 0x34 */

+  __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                            Address offset: 0x38 */

+  __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                            Address offset: 0x3C */

+  __IO uint32_t DR;               /*!< ADC regular data register,                                  Address offset: 0x40 */

+  uint32_t      RESERVED3;        /*!< Reserved, 0x044                                                                  */

+  uint32_t      RESERVED4;        /*!< Reserved, 0x048                                                                  */

+  __IO uint32_t JSQR;             /*!< ADC injected sequence register,                             Address offset: 0x4C */

+  uint32_t      RESERVED5[4];     /*!< Reserved, 0x050 - 0x05C                                                          */

+  __IO uint32_t OFR1;             /*!< ADC offset register 1,                                      Address offset: 0x60 */

+  __IO uint32_t OFR2;             /*!< ADC offset register 2,                                      Address offset: 0x64 */

+  __IO uint32_t OFR3;             /*!< ADC offset register 3,                                      Address offset: 0x68 */

+  __IO uint32_t OFR4;             /*!< ADC offset register 4,                                      Address offset: 0x6C */

+  uint32_t      RESERVED6[4];     /*!< Reserved, 0x070 - 0x07C                                                          */

+  __IO uint32_t JDR1;             /*!< ADC injected data register 1,                               Address offset: 0x80 */

+  __IO uint32_t JDR2;             /*!< ADC injected data register 2,                               Address offset: 0x84 */

+  __IO uint32_t JDR3;             /*!< ADC injected data register 3,                               Address offset: 0x88 */

+  __IO uint32_t JDR4;             /*!< ADC injected data register 4,                               Address offset: 0x8C */

+  uint32_t      RESERVED7[4];     /*!< Reserved, 0x090 - 0x09C                                                          */

+  __IO uint32_t AWD2CR;           /*!< ADC  Analog Watchdog 2 Configuration Register,              Address offset: 0xA0 */

+  __IO uint32_t AWD3CR;           /*!< ADC  Analog Watchdog 3 Configuration Register,              Address offset: 0xA4 */

+  uint32_t      RESERVED8;        /*!< Reserved, 0x0A8                                                                  */

+  uint32_t      RESERVED9;        /*!< Reserved, 0x0AC                                                                  */

+  __IO uint32_t LTR2;             /*!< ADC watchdog Lower threshold register 2,                    Address offset: 0xB0 */

+  __IO uint32_t HTR2;             /*!< ADC watchdog Higher threshold register 2,                   Address offset: 0xB4 */

+  __IO uint32_t LTR3;             /*!< ADC watchdog Lower threshold register 3,                    Address offset: 0xB8 */

+  __IO uint32_t HTR3;             /*!< ADC watchdog Higher threshold register 3,                   Address offset: 0xBC */

+  __IO uint32_t DIFSEL;           /*!< ADC  Differential Mode Selection Register,                  Address offset: 0xC0 */

+  __IO uint32_t CALFACT;          /*!< ADC  Calibration Factors,                                   Address offset: 0xC4 */

+  __IO uint32_t CALFACT2;         /*!< ADC  Linearity Calibration Factors,                         Address offset: 0xC8 */

+} ADC_TypeDef;

+

+

+typedef struct

+{

+__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */

+uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */

+__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */

+__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */

+__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */

+

+} ADC_Common_TypeDef;

+

+

+/**

+  * @brief VREFBUF

+  */

+

+typedef struct

+{

+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */

+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */

+} VREFBUF_TypeDef;

+

+

+/**

+  * @brief FD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */

+  __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */

+  __IO uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */

+  __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */

+  __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */

+  __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */

+  __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */

+  __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */

+  __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */

+  __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */

+  __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */

+  __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */

+  __IO uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */

+  __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */

+  __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */

+  __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */

+  __IO uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */

+  __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */

+  __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */

+  __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */

+  __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */

+  __IO uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */

+  __IO uint32_t GFC;          /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */

+  __IO uint32_t SIDFC;        /*!< FDCAN Standard ID Filter Configuration register,                 Address offset: 0x084 */

+  __IO uint32_t XIDFC;        /*!< FDCAN Extended ID Filter Configuration register,                 Address offset: 0x088 */

+  __IO uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */

+  __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x090 */

+  __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x094 */

+  __IO uint32_t NDAT1;        /*!< FDCAN New Data 1 register,                                       Address offset: 0x098 */

+  __IO uint32_t NDAT2;        /*!< FDCAN New Data 2 register,                                       Address offset: 0x09C */

+  __IO uint32_t RXF0C;        /*!< FDCAN Rx FIFO 0 Configuration register,                          Address offset: 0x0A0 */

+  __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x0A4 */

+  __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x0A8 */

+  __IO uint32_t RXBC;         /*!< FDCAN Rx Buffer Configuration register,                          Address offset: 0x0AC */

+  __IO uint32_t RXF1C;        /*!< FDCAN Rx FIFO 1 Configuration register,                          Address offset: 0x0B0 */

+  __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x0B4 */

+  __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x0B8 */

+  __IO uint32_t RXESC;        /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register,        Address offset: 0x0BC */

+  __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */

+  __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */

+  __IO uint32_t TXESC;        /*!< FDCAN Tx Buffer Element Size Configuration register,             Address offset: 0x0C8 */

+  __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0CC */

+  __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0D0 */

+  __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D4 */

+  __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D8 */

+  __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0DC */

+  __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0E0 */

+  __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */

+  __IO uint32_t RESERVED6[2]; /*!< Reserved,                                                                0x0E8 - 0x0EC */

+  __IO uint32_t TXEFC;        /*!< FDCAN Tx Event FIFO Configuration register,                      Address offset: 0x0F0 */

+  __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0F4 */

+  __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0F8 */

+  __IO uint32_t RESERVED7;    /*!< Reserved,                                                                        0x0FC */

+} FDCAN_GlobalTypeDef;

+

+/**

+  * @brief TTFD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t TTTMC;          /*!< TT Trigger Memory Configuration register,    Address offset: 0x100 */

+  __IO uint32_t TTRMC;          /*!< TT Reference Message Configuration register, Address offset: 0x104 */

+  __IO uint32_t TTOCF;          /*!< TT Operation Configuration register,         Address offset: 0x108 */

+  __IO uint32_t TTMLM;          /*!< TT Matrix Limits register,                   Address offset: 0x10C */

+  __IO uint32_t TURCF;          /*!< TUR Configuration register,                  Address offset: 0x110 */

+  __IO uint32_t TTOCN;          /*!< TT Operation Control register,               Address offset: 0x114 */

+  __IO uint32_t TTGTP;          /*!< TT Global Time Preset register,              Address offset: 0x118 */

+  __IO uint32_t TTTMK;          /*!< TT Time Mark register,                       Address offset: 0x11C */

+  __IO uint32_t TTIR;           /*!< TT Interrupt register,                       Address offset: 0x120 */

+  __IO uint32_t TTIE;           /*!< TT Interrupt Enable register,                Address offset: 0x124 */

+  __IO uint32_t TTILS;          /*!< TT Interrupt Line Select register,           Address offset: 0x128 */

+  __IO uint32_t TTOST;          /*!< TT Operation Status register,                Address offset: 0x12C */

+  __IO uint32_t TURNA;          /*!< TT TUR Numerator Actual register,            Address offset: 0x130 */

+  __IO uint32_t TTLGT;          /*!< TT Local and Global Time register,           Address offset: 0x134 */

+  __IO uint32_t TTCTC;          /*!< TT Cycle Time and Count register,            Address offset: 0x138 */

+  __IO uint32_t TTCPT;          /*!< TT Capture Time register,                    Address offset: 0x13C */

+  __IO uint32_t TTCSM;          /*!< TT Cycle Sync Mark register,                 Address offset: 0x140 */

+  __IO uint32_t RESERVED1[111]; /*!< Reserved,                                            0x144 - 0x2FC */

+  __IO uint32_t TTTS;           /*!< TT Trigger Select register,                  Address offset: 0x300 */

+} TTCAN_TypeDef;

+

+/**

+  * @brief FD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t CREL;  /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */

+  __IO uint32_t CCFG;  /*!< Calibration Configuration register,           Address offset: 0x04 */

+  __IO uint32_t CSTAT; /*!< Calibration Status register,                  Address offset: 0x08 */

+  __IO uint32_t CWD;   /*!< Calibration Watchdog register,                Address offset: 0x0C */

+  __IO uint32_t IR;    /*!< CCU Interrupt register,                       Address offset: 0x10 */

+  __IO uint32_t IE;    /*!< CCU Interrupt Enable register,                Address offset: 0x14 */

+} FDCAN_ClockCalibrationUnit_TypeDef;

+

+

+/**

+  * @brief Consumer Electronics Control

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;           /*!< CEC control register,              Address offset:0x00 */

+  __IO uint32_t CFGR;         /*!< CEC configuration register,        Address offset:0x04 */

+  __IO uint32_t TXDR;         /*!< CEC Tx data register ,             Address offset:0x08 */

+  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,              Address offset:0x0C */

+  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register, Address offset:0x10 */

+  __IO uint32_t IER;          /*!< CEC interrupt enable register,     Address offset:0x14 */

+}CEC_TypeDef;

+

+/**

+  * @brief CRC calculation unit

+  */

+

+typedef struct

+{

+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */

+  __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */

+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */

+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */

+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */

+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */

+} CRC_TypeDef;

+

+

+/**

+  * @brief Clock Recovery System

+  */

+typedef struct

+{

+__IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */

+__IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */

+__IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */

+__IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */

+} CRS_TypeDef;

+

+

+/**

+  * @brief Digital to Analog Converter

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */

+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */

+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */

+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */

+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */

+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */

+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */

+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */

+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */

+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */

+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */

+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */

+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */

+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */

+  __IO uint32_t CCR;      /*!< DAC calibration control register,                        Address offset: 0x38 */

+  __IO uint32_t MCR;      /*!< DAC mode control register,                               Address offset: 0x3C */

+  __IO uint32_t SHSR1;    /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */

+  __IO uint32_t SHSR2;    /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */

+  __IO uint32_t SHHR;     /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */

+  __IO uint32_t SHRR;     /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */

+} DAC_TypeDef;

+

+/**

+  * @brief DFSDM module registers

+  */

+typedef struct

+{

+  __IO uint32_t FLTCR1;          /*!< DFSDM control register1,                          Address offset: 0x100 */

+  __IO uint32_t FLTCR2;          /*!< DFSDM control register2,                          Address offset: 0x104 */

+  __IO uint32_t FLTISR;          /*!< DFSDM interrupt and status register,              Address offset: 0x108 */

+  __IO uint32_t FLTICR;          /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */

+  __IO uint32_t FLTJCHGR;        /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */

+  __IO uint32_t FLTFCR;          /*!< DFSDM filter control register,                    Address offset: 0x114 */

+  __IO uint32_t FLTJDATAR;       /*!< DFSDM data register for injected group,           Address offset: 0x118 */

+  __IO uint32_t FLTRDATAR;       /*!< DFSDM data register for regular group,            Address offset: 0x11C */

+  __IO uint32_t FLTAWHTR;        /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */

+  __IO uint32_t FLTAWLTR;        /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */

+  __IO uint32_t FLTAWSR;         /*!< DFSDM analog watchdog status register             Address offset: 0x128 */

+  __IO uint32_t FLTAWCFR;        /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */

+  __IO uint32_t FLTEXMAX;        /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */

+  __IO uint32_t FLTEXMIN;        /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */

+  __IO uint32_t FLTCNVTIMR;      /*!< DFSDM conversion timer,                           Address offset: 0x138 */

+} DFSDM_Filter_TypeDef;

+

+/**

+  * @brief DFSDM channel configuration registers

+  */

+typedef struct

+{

+  __IO uint32_t CHCFGR1;      /*!< DFSDM channel configuration register1,            Address offset: 0x00 */

+  __IO uint32_t CHCFGR2;      /*!< DFSDM channel configuration register2,            Address offset: 0x04 */

+  __IO uint32_t CHAWSCDR;     /*!< DFSDM channel analog watchdog and

+                                   short circuit detector register,                  Address offset: 0x08 */

+  __IO uint32_t CHWDATAR;     /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */

+  __IO uint32_t CHDATINR;     /*!< DFSDM channel data input register,                Address offset: 0x10 */

+  __IO uint32_t CHDLYR;       /*!< DFSDM channel delay register,                     Address offset: 0x14 */

+} DFSDM_Channel_TypeDef;

+

+/**

+  * @brief Debug MCU

+  */

+typedef struct

+{

+  __IO uint32_t IDCODE;        /*!< MCU device ID code,                     Address offset: 0x00 */

+  __IO uint32_t CR;            /*!< Debug MCU configuration register,       Address offset: 0x04 */

+  uint32_t RESERVED4[11];      /*!< Reserved,                             Address offset: 0x08 */

+  __IO uint32_t APB3FZ1;     /*!< Debug MCU APB3FZ1 freeze register,    Address offset: 0x34 */

+  uint32_t RESERVED5;          /*!< Reserved,                             Address offset: 0x38 */

+  __IO uint32_t APB1LFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x3C */

+  uint32_t RESERVED6;          /*!< Reserved,                             Address offset: 0x40 */

+  __IO uint32_t APB1HFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x44 */

+  uint32_t RESERVED7;          /*!< Reserved,                             Address offset: 0x48 */

+  __IO uint32_t APB2FZ1;     /*!< Debug MCU APB2FZ1 freeze register,    Address offset: 0x4C */

+  uint32_t RESERVED8;          /*!< Reserved,                             Address offset: 0x50 */

+  __IO uint32_t APB4FZ1;     /*!< Debug MCU APB4FZ1 freeze register,    Address offset: 0x54 */

+}DBGMCU_TypeDef;

+/**

+  * @brief DCMI

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */

+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */

+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */

+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */

+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */

+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */

+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */

+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */

+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */

+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */

+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */

+} DCMI_TypeDef;

+

+/**

+  * @brief PSSI

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;             /*!< PSSI control register 1,               Address offset: 0x000 */

+  __IO uint32_t SR;             /*!< PSSI status register,                  Address offset: 0x004 */

+  __IO uint32_t RIS;            /*!< PSSI raw interrupt status register,    Address offset: 0x008 */

+  __IO uint32_t IER;            /*!< PSSI interrupt enable register,        Address offset: 0x00C */

+  __IO uint32_t MIS;            /*!< PSSI masked interrupt status register, Address offset: 0x010 */

+  __IO uint32_t ICR;            /*!< PSSI interrupt clear register,         Address offset: 0x014 */

+  __IO uint32_t RESERVED1[4];   /*!< Reserved,                                      0x018 - 0x024 */

+  __IO uint32_t DR;             /*!< PSSI data register,                    Address offset: 0x028 */

+  __IO uint32_t RESERVED2[241]; /*!< Reserved,                                      0x02C - 0x3EC */

+  __IO uint32_t HWCFGR;         /*!< PSSI IP HW configuration register,     Address offset: 0x3F0 */

+  __IO uint32_t VERR;           /*!< PSSI IP version register,              Address offset: 0x3F4 */

+  __IO uint32_t IPIDR;          /*!< PSSI IP ID register,                   Address offset: 0x3F8 */

+  __IO uint32_t SIDR;           /*!< PSSI SIZE ID register,                 Address offset: 0x3FC */

+} PSSI_TypeDef;

+

+/**

+  * @brief DMA Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */

+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */

+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */

+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */

+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */

+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */

+} DMA_Stream_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */

+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */

+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */

+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */

+} DMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CCR;          /*!< DMA channel x configuration register          */

+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register         */

+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register     */

+  __IO uint32_t CM0AR;        /*!< DMA channel x memory 0 address register       */

+  __IO uint32_t CM1AR;        /*!< DMA channel x memory 1 address register       */

+} BDMA_Channel_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */

+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */

+} BDMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CCR;        /*!< DMA Multiplexer Channel x Control Register   */

+}DMAMUX_Channel_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CSR;      /*!< DMA Channel Status Register     */

+  __IO uint32_t  CFR;      /*!< DMA Channel Clear Flag Register */

+}DMAMUX_ChannelStatus_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  RGCR;        /*!< DMA Request Generator x Control Register   */

+}DMAMUX_RequestGen_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  RGSR;        /*!< DMA Request Generator Status Register       */

+  __IO uint32_t  RGCFR;       /*!< DMA Request Generator Clear Flag Register   */

+}DMAMUX_RequestGenStatus_TypeDef;

+

+/**

+  * @brief MDMA Controller

+  */

+typedef struct

+{

+  __IO uint32_t  GISR0;   /*!< MDMA Global Interrupt/Status Register 0,          Address offset: 0x00 */

+}MDMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CISR;      /*!< MDMA channel x interrupt/status register,             Address offset: 0x40 */

+  __IO uint32_t  CIFCR;     /*!< MDMA channel x interrupt flag clear register,         Address offset: 0x44 */

+  __IO uint32_t  CESR;      /*!< MDMA Channel x error status register,                 Address offset: 0x48 */

+  __IO uint32_t  CCR;       /*!< MDMA channel x control register,                      Address offset: 0x4C */

+  __IO uint32_t  CTCR;      /*!< MDMA channel x Transfer Configuration register,       Address offset: 0x50 */

+  __IO uint32_t  CBNDTR;    /*!< MDMA Channel x block number of data register,         Address offset: 0x54 */

+  __IO uint32_t  CSAR;      /*!< MDMA channel x source address register,               Address offset: 0x58 */

+  __IO uint32_t  CDAR;      /*!< MDMA channel x destination address register,          Address offset: 0x5C */

+  __IO uint32_t  CBRUR;     /*!< MDMA channel x Block Repeat address Update register,  Address offset: 0x60 */

+  __IO uint32_t  CLAR;      /*!< MDMA channel x Link Address register,                 Address offset: 0x64 */

+  __IO uint32_t  CTBR;      /*!< MDMA channel x Trigger and Bus selection Register,    Address offset: 0x68 */

+  uint32_t       RESERVED0; /*!< Reserved, 0x68                                                             */

+  __IO uint32_t  CMAR;      /*!< MDMA channel x Mask address register,                 Address offset: 0x70 */

+  __IO uint32_t  CMDR;      /*!< MDMA channel x Mask Data register,                    Address offset: 0x74 */

+}MDMA_Channel_TypeDef;

+

+/**

+  * @brief DMA2D Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */

+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */

+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */

+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */

+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */

+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */

+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */

+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */

+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */

+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */

+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */

+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */

+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */

+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */

+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */

+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */

+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */

+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */

+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */

+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */

+  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */

+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */

+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */

+} DMA2D_TypeDef;

+

+

+/**

+  * @brief External Interrupt/Event Controller

+  */

+

+typedef struct

+{

+__IO uint32_t RTSR1;               /*!< EXTI Rising trigger selection register,          Address offset: 0x00 */

+__IO uint32_t FTSR1;               /*!< EXTI Falling trigger selection register,         Address offset: 0x04 */

+__IO uint32_t SWIER1;              /*!< EXTI Software interrupt event register,          Address offset: 0x08 */

+__IO uint32_t D3PMR1;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */

+__IO uint32_t D3PCR1L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L)     Address offset: 0x10 */

+__IO uint32_t D3PCR1H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H)   Address offset: 0x14 */

+uint32_t      RESERVED1[2];        /*!< Reserved,                                        0x18 to 0x1C         */

+__IO uint32_t RTSR2;               /*!< EXTI Rising trigger selection register,          Address offset: 0x20 */

+__IO uint32_t FTSR2;               /*!< EXTI Falling trigger selection register,         Address offset: 0x24 */

+__IO uint32_t SWIER2;              /*!< EXTI Software interrupt event register,          Address offset: 0x28 */

+__IO uint32_t D3PMR2;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */

+__IO uint32_t D3PCR2L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L)  Address offset: 0x30 */

+__IO uint32_t D3PCR2H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */

+uint32_t      RESERVED2[2];        /*!< Reserved,                                        0x38 to 0x3C         */

+__IO uint32_t RTSR3;               /*!< EXTI Rising trigger selection register,          Address offset: 0x40 */

+__IO uint32_t FTSR3;               /*!< EXTI Falling trigger selection register,         Address offset: 0x44 */

+__IO uint32_t SWIER3;              /*!< EXTI Software interrupt event register,          Address offset: 0x48 */

+__IO uint32_t D3PMR3;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */

+__IO uint32_t D3PCR3L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */

+__IO uint32_t D3PCR3H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */

+uint32_t      RESERVED3[10];       /*!< Reserved,                                        0x58 to 0x7C         */

+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                    Address offset: 0x80 */

+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                        Address offset: 0x84 */

+__IO uint32_t PR1;                 /*!< EXTI Pending register,                           Address offset: 0x88 */

+uint32_t      RESERVED4;           /*!< Reserved,                                        0x8C                 */

+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                    Address offset: 0x90 */

+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                        Address offset: 0x94 */

+__IO uint32_t PR2;                 /*!< EXTI Pending register,                           Address offset: 0x98 */

+uint32_t      RESERVED5;           /*!< Reserved,                                        0x9C                 */

+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                    Address offset: 0xA0 */

+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                        Address offset: 0xA4 */

+__IO uint32_t PR3;                 /*!< EXTI Pending register,                           Address offset: 0xA8 */

+}EXTI_TypeDef;

+

+typedef struct

+{

+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                Address offset: 0x00 */

+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                    Address offset: 0x04 */

+__IO uint32_t PR1;                 /*!< EXTI Pending register,                       Address offset: 0x08 */

+uint32_t      RESERVED1;           /*!< Reserved, 0x0C                                                    */

+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                Address offset: 0x10 */

+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                    Address offset: 0x14 */

+__IO uint32_t PR2;                 /*!< EXTI Pending register,                       Address offset: 0x18 */

+uint32_t      RESERVED2;           /*!< Reserved, 0x1C                                                    */

+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                Address offset: 0x20 */

+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                    Address offset: 0x24 */

+__IO uint32_t PR3;                 /*!< EXTI Pending register,                       Address offset: 0x28 */

+}EXTI_Core_TypeDef;

+

+

+/**

+  * @brief FLASH Registers

+  */

+

+typedef struct

+{

+  __IO uint32_t ACR;             /*!< FLASH access control register,                            Address offset: 0x00  */

+  __IO uint32_t KEYR1;           /*!< Flash Key Register for bank1,                             Address offset: 0x04  */

+  __IO uint32_t OPTKEYR;         /*!< Flash Option Key Register,                                Address offset: 0x08  */

+  __IO uint32_t CR1;             /*!< Flash Control Register for bank1,                         Address offset: 0x0C  */

+  __IO uint32_t SR1;             /*!< Flash Status Register for bank1,                          Address offset: 0x10  */

+  __IO uint32_t CCR1;            /*!< Flash Control Register for bank1,                         Address offset: 0x14  */

+  __IO uint32_t OPTCR;           /*!< Flash Option Control Register,                            Address offset: 0x18  */

+  __IO uint32_t OPTSR_CUR;       /*!< Flash Option Status Current Register,                     Address offset: 0x1C  */

+  __IO uint32_t OPTSR_PRG;       /*!< Flash Option Status to Program Register,                  Address offset: 0x20  */

+  __IO uint32_t OPTCCR;          /*!< Flash Option Clear Control Register,                      Address offset: 0x24  */

+  __IO uint32_t PRAR_CUR1;       /*!< Flash Current Protection Address Register for bank1,      Address offset: 0x28  */

+  __IO uint32_t PRAR_PRG1;       /*!< Flash Protection Address to Program Register for bank1,   Address offset: 0x2C  */

+  __IO uint32_t SCAR_CUR1;       /*!< Flash Current Secure Address Register for bank1,          Address offset: 0x30  */

+  __IO uint32_t SCAR_PRG1;       /*!< Flash Secure Address to Program Register for bank1,       Address offset: 0x34  */

+  __IO uint32_t WPSN_CUR1;       /*!< Flash Current Write Protection Register on bank1,         Address offset: 0x38  */

+  __IO uint32_t WPSN_PRG1;       /*!< Flash Write Protection to Program Register on bank1,      Address offset: 0x3C  */

+  __IO uint32_t BOOT_CUR;        /*!< Flash Current Boot Address for Pelican Core Register,     Address offset: 0x40  */

+  __IO uint32_t BOOT_PRG;        /*!< Flash Boot Address to Program for Pelican Core Register,  Address offset: 0x44  */

+  uint32_t      RESERVED0[2];    /*!< Reserved, 0x48 to 0x4C                                                          */

+  __IO uint32_t CRCCR1;          /*!< Flash CRC Control register For Bank1 Register ,           Address offset: 0x50  */

+  __IO uint32_t CRCSADD1;        /*!< Flash CRC Start Address Register for Bank1 ,              Address offset: 0x54  */

+  __IO uint32_t CRCEADD1;        /*!< Flash CRC End Address Register for Bank1 ,                Address offset: 0x58  */

+  __IO uint32_t CRCDATA;         /*!< Flash CRC Data Register for Bank1 ,                       Address offset: 0x5C  */

+  __IO uint32_t ECC_FA1;         /*!< Flash ECC Fail Address For Bank1 Register ,               Address offset: 0x60  */

+  uint32_t      RESERVED;        /*!< Reserved, 0x64                                                                  */

+  __IO uint32_t OTPBL_CUR;       /*!< Flash Current OTP Block Lock Register,                    Address offset: 0x68  */

+  __IO uint32_t OTPBL_PRG;       /*!< Flash OTP Block Lock to Program Register,                 Address offset: 0x6C  */

+  uint32_t      RESERVED1[37];   /*!< Reserved, 0x70 to 0x100                                                         */

+  __IO uint32_t KEYR2;           /*!< Flash Key Register for bank2,                             Address offset: 0x104 */

+  uint32_t      RESERVED2;       /*!< Reserved, 0x108                                                                 */

+  __IO uint32_t CR2;             /*!< Flash Control Register for bank2,                         Address offset: 0x10C */

+  __IO uint32_t SR2;             /*!< Flash Status Register for bank2,                          Address offset: 0x110 */

+  __IO uint32_t CCR2;            /*!< Flash Status Register for bank2,                          Address offset: 0x114 */

+  uint32_t      RESERVED3[4];    /*!< Reserved, 0x118 to 0x124                                                        */

+  __IO uint32_t PRAR_CUR2;       /*!< Flash Current Protection Address Register for bank2,      Address offset: 0x128 */

+  __IO uint32_t PRAR_PRG2;       /*!< Flash Protection Address to Program Register for bank2,   Address offset: 0x12C */

+  __IO uint32_t SCAR_CUR2;       /*!< Flash Current Secure Address Register for bank2,          Address offset: 0x130 */

+  __IO uint32_t SCAR_PRG2;       /*!< Flash Secure Address Register for bank2,                  Address offset: 0x134 */

+  __IO uint32_t WPSN_CUR2;       /*!< Flash Current Write Protection Register on bank2,         Address offset: 0x138 */

+  __IO uint32_t WPSN_PRG2;       /*!< Flash Write Protection to Program Register on bank2,      Address offset: 0x13C */

+  uint32_t      RESERVED4[4];    /*!< Reserved, 0x140 to 0x14C                                                        */

+  __IO uint32_t CRCCR2;          /*!< Flash CRC Control register For Bank2 Register ,           Address offset: 0x150 */

+  __IO uint32_t CRCSADD2;        /*!< Flash CRC Start Address Register for Bank2 ,              Address offset: 0x154 */

+  __IO uint32_t CRCEADD2;        /*!< Flash CRC End Address Register for Bank2 ,                Address offset: 0x158 */

+  __IO uint32_t CRCDATA2;        /*!< Flash CRC Data Register for Bank2 ,                       Address offset: 0x15C */

+  __IO uint32_t ECC_FA2;         /*!< Flash ECC Fail Address For Bank2 Register ,               Address offset: 0x160 */

+} FLASH_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */

+} FMC_Bank1_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank1E

+  */

+

+typedef struct

+{

+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */

+} FMC_Bank1E_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank2

+  */

+

+typedef struct

+{

+  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */

+  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */

+  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */

+  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */

+  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */

+  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */

+} FMC_Bank2_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank3

+  */

+

+typedef struct

+{

+  __IO uint32_t PCR;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */

+  __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */

+  __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */

+  __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */

+  uint32_t      RESERVED;  /*!< Reserved, 0x90                                                            */

+  __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */

+} FMC_Bank3_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank5 and 6

+  */

+

+

+typedef struct

+{

+  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */

+  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */

+  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */

+  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */

+  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */

+} FMC_Bank5_6_TypeDef;

+

+/**

+  * @brief GFXMMU registers

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;              /*!< GFXMMU configuration register,                     Address offset: 0x00 */

+  __IO uint32_t SR;              /*!< GFXMMU status register,                            Address offset: 0x04 */

+  __IO uint32_t FCR;             /*!< GFXMMU flag clear register,                        Address offset: 0x08 */

+  __IO uint32_t CCR;             /*!< GFXMMU Cache Control Register,                     Address offset: 0x0C */

+  __IO uint32_t DVR;             /*!< GFXMMU default value register,                     Address offset: 0x10 */

+       uint32_t RESERVED1[3];    /*!< Reserved1,                                         Address offset: 0x14 to 0x1C */

+  __IO uint32_t B0CR;            /*!< GFXMMU buffer 0 configuration register,            Address offset: 0x20 */

+  __IO uint32_t B1CR;            /*!< GFXMMU buffer 1 configuration register,            Address offset: 0x24 */

+  __IO uint32_t B2CR;            /*!< GFXMMU buffer 2 configuration register,            Address offset: 0x28 */

+  __IO uint32_t B3CR;            /*!< GFXMMU buffer 3 configuration register,            Address offset: 0x2C */

+       uint32_t RESERVED2[1012]; /*!< Reserved2,                                         Address offset: 0x30 to 0xFFC */

+  __IO uint32_t LUT[2048];       /*!< GFXMMU LUT registers,                              Address offset: 0x1000 to 0x2FFC

+                                      For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */

+} GFXMMU_TypeDef;

+/**

+  * @brief General Purpose I/O

+  */

+

+typedef struct

+{

+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */

+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */

+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */

+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */

+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */

+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */

+  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset,               Address offset: 0x18      */

+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */

+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */

+} GPIO_TypeDef;

+

+/**

+  * @brief Operational Amplifier (OPAMP)

+  */

+

+typedef struct

+{

+  __IO uint32_t CSR;          /*!< OPAMP control/status register,                      Address offset: 0x00 */

+  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,     Address offset: 0x04 */

+  __IO uint32_t HSOTR;        /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */

+} OPAMP_TypeDef;

+

+/**

+  * @brief System configuration controller

+  */

+

+typedef struct

+{

+ uint32_t RESERVED1;           /*!< Reserved,                                           Address offset: 0x00        */

+ __IO uint32_t PMCR;           /*!< SYSCFG peripheral mode configuration register,      Address offset: 0x04        */

+ __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration registers,  Address offset: 0x08-0x14   */

+ __IO uint32_t CFGR;           /*!< SYSCFG configuration registers,                     Address offset: 0x18        */

+ uint32_t RESERVED2;           /*!< Reserved,                                           Address offset: 0x1C        */

+ __IO uint32_t CCCSR;          /*!< SYSCFG compensation cell control/status register,   Address offset: 0x20        */

+ __IO uint32_t CCVR;           /*!< SYSCFG compensation cell value register,            Address offset: 0x24        */

+ __IO uint32_t CCCR;           /*!< SYSCFG compensation cell code register,             Address offset: 0x28        */

+

+} SYSCFG_TypeDef;

+

+/**

+  * @brief Inter-integrated Circuit Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */

+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */

+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */

+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */

+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */

+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */

+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */

+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */

+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */

+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */

+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */

+} I2C_TypeDef;

+

+/**

+  * @brief Independent WATCHDOG

+  */

+

+typedef struct

+{

+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */

+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */

+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */

+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */

+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */

+} IWDG_TypeDef;

+

+

+/**

+  * @brief JPEG Codec

+  */

+typedef struct

+{

+  __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */

+  __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */

+  __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */

+  __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */

+  __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */

+  __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */

+  __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */

+  __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */

+  uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */

+  __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */

+  __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */

+  __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */

+  uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */

+  __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */

+  __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */

+  uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */

+  __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */

+  __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */

+  __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */

+  __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */

+  __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */

+  __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */

+  __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */

+  __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */

+  uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */

+  __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0,                 Address offset: 500h-65Ch */

+  __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1,                 Address offset: 660h-7BCh */

+  __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encodor, DC Huffman table 0,                 Address offset: 7C0h-7DCh */

+  __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encodor, DC Huffman table 1,                 Address offset: 7E0h-7FCh */

+

+} JPEG_TypeDef;

+

+/**

+  * @brief LCD-TFT Display Controller

+  */

+

+typedef struct

+{

+  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04                                                       */

+  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */

+  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */

+  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */

+  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */

+  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */

+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20                                                       */

+  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */

+  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28                                                            */

+  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */

+  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30                                                            */

+  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */

+  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */

+  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */

+  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */

+  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */

+  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */

+} LTDC_TypeDef;

+

+/**

+  * @brief LCD-TFT Display layer x Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */

+  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */

+  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */

+  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */

+  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */

+  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */

+  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */

+  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */

+  uint32_t      RESERVED0[2];  /*!< Reserved */

+  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */

+  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */

+  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */

+  uint32_t      RESERVED1[3];  /*!< Reserved */

+  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */

+

+} LTDC_Layer_TypeDef;

+

+/**

+  * @brief Power Control

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;       /*!< PWR power control register 1,            Address offset: 0x00 */

+  __IO uint32_t CSR1;      /*!< PWR power control status register 1,     Address offset: 0x04 */

+  __IO uint32_t CR2;       /*!< PWR power control register 2,            Address offset: 0x08 */

+  __IO uint32_t CR3;       /*!< PWR power control register 3,            Address offset: 0x0C */

+  __IO uint32_t CPUCR;     /*!< PWR CPU control register,                Address offset: 0x10 */

+       uint32_t RESERVED0; /*!< Reserved,                                Address offset: 0x14 */

+  __IO uint32_t SRDCR;     /*!< PWR SRD domain control register,         Address offset: 0x18 */

+       uint32_t RESERVED1; /*!< Reserved,                                Address offset: 0x1C */

+  __IO uint32_t WKUPCR;    /*!< PWR wakeup clear register,               Address offset: 0x20 */

+  __IO uint32_t WKUPFR;    /*!< PWR wakeup flag register,                Address offset: 0x24 */

+  __IO uint32_t WKUPEPR;   /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */

+} PWR_TypeDef;

+

+/**

+  * @brief Reset and Clock Control

+  */

+

+typedef struct

+{

+ __IO uint32_t CR;             /*!< RCC clock control register,                                              Address offset: 0x00  */

+ __IO uint32_t HSICFGR;        /*!< HSI Clock Calibration Register,                                          Address offset: 0x04  */

+ __IO uint32_t CRRCR;          /*!< Clock Recovery RC  Register,                                             Address offset: 0x08  */

+ __IO uint32_t CSICFGR;        /*!< CSI Clock Calibration Register,                                          Address offset: 0x0C  */

+ __IO uint32_t CFGR;           /*!< RCC clock configuration register,                                        Address offset: 0x10  */

+ uint32_t     RESERVED1;       /*!< Reserved,                                                                Address offset: 0x14  */

+ __IO uint32_t CDCFGR1;         /*!< RCC Domain 1 configuration register,                                    Address offset: 0x18  */

+ __IO uint32_t CDCFGR2;         /*!< RCC Domain 2 configuration register,                                    Address offset: 0x1C  */

+ __IO uint32_t SRDCFGR;         /*!< RCC Domain 3 configuration register,                                    Address offset: 0x20  */

+ uint32_t     RESERVED2;       /*!< Reserved,                                                                Address offset: 0x24  */

+ __IO uint32_t PLLCKSELR;      /*!< RCC PLLs Clock Source Selection Register,                                Address offset: 0x28  */

+ __IO uint32_t PLLCFGR;        /*!< RCC PLLs  Configuration Register,                                        Address offset: 0x2C  */

+ __IO uint32_t PLL1DIVR;       /*!< RCC PLL1 Dividers Configuration Register,                                Address offset: 0x30  */

+ __IO uint32_t PLL1FRACR;      /*!< RCC PLL1 Fractional Divider Configuration Register,                      Address offset: 0x34  */

+ __IO uint32_t PLL2DIVR;       /*!< RCC PLL2 Dividers Configuration Register,                                Address offset: 0x38  */

+ __IO uint32_t PLL2FRACR;      /*!< RCC PLL2 Fractional Divider Configuration Register,                      Address offset: 0x3C  */

+ __IO uint32_t PLL3DIVR;       /*!< RCC PLL3 Dividers Configuration Register,                                Address offset: 0x40  */

+ __IO uint32_t PLL3FRACR;      /*!< RCC PLL3 Fractional Divider Configuration Register,                      Address offset: 0x44  */

+ uint32_t      RESERVED3;      /*!< Reserved,                                                                Address offset: 0x48  */

+ __IO uint32_t  CDCCIPR;       /*!< RCC Domain 1 Kernel Clock Configuration Register                         Address offset: 0x4C  */

+ __IO uint32_t  CDCCIP1R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x50  */

+ __IO uint32_t  CDCCIP2R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x54  */

+ __IO uint32_t  SRDCCIPR;       /*!< RCC Domain 3 Kernel Clock Configuration Register                         Address offset: 0x58  */

+ uint32_t      RESERVED4;      /*!< Reserved,                                                                Address offset: 0x5C  */

+ __IO uint32_t  CIER;          /*!< RCC Clock Source Interrupt Enable Register                               Address offset: 0x60  */

+ __IO uint32_t  CIFR;          /*!< RCC Clock Source Interrupt Flag Register                                 Address offset: 0x64  */

+ __IO uint32_t  CICR;          /*!< RCC Clock Source Interrupt Clear Register                                Address offset: 0x68  */

+ uint32_t     RESERVED5;       /*!< Reserved,                                                                Address offset: 0x6C  */

+ __IO uint32_t  BDCR;          /*!< RCC Vswitch Backup Domain Control Register,                              Address offset: 0x70  */

+ __IO uint32_t  CSR;           /*!< RCC clock control & status register,                                     Address offset: 0x74  */

+ uint32_t     RESERVED6;       /*!< Reserved,                                                                Address offset: 0x78  */

+ __IO uint32_t AHB3RSTR;       /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x7C  */

+ __IO uint32_t AHB1RSTR;       /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x80  */

+ __IO uint32_t AHB2RSTR;       /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x84  */

+ __IO uint32_t AHB4RSTR;       /*!< RCC AHB4 peripheral reset register,                                      Address offset: 0x88  */

+ __IO uint32_t APB3RSTR;       /*!< RCC APB3 peripheral reset register,                                      Address offset: 0x8C  */

+ __IO uint32_t APB1LRSTR;      /*!< RCC APB1 peripheral reset Low Word register,                             Address offset: 0x90  */

+ __IO uint32_t APB1HRSTR;      /*!< RCC APB1 peripheral reset High Word register,                            Address offset: 0x94  */

+ __IO uint32_t APB2RSTR;       /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x98  */

+ __IO uint32_t APB4RSTR;       /*!< RCC APB4 peripheral reset register,                                      Address offset: 0x9C  */

+ uint32_t     RESERVED7;       /*!< Reserved,                                                                Address offset: 0xA0  */

+ uint32_t     RESERVED8;       /*!< Reserved,                                                                Address offset: 0xA4  */

+ __IO uint32_t SRDAMR;         /*!< RCC Domain 3 Autonomous Mode Register,                                   Address offset: 0xA8  */

+  uint32_t     RESERVED9;      /*!< Reserved, 0xAC-0xAF                                                      Address offset: 0xAC  */

+ __IO uint32_t CKGAENR;        /*!< AXI Clocks Gating Enable Register,                                       Address offset: 0xB0  */

+  uint32_t     RESERVED10[31];   /*!< Reserved, 0xAC-0xAF                                                    Address offset: 0xAC  */

+ __IO uint32_t RSR;            /*!< RCC Reset status register,                                               Address offset: 0xD0  */

+ __IO uint32_t AHB3ENR;        /*!< RCC AHB3 peripheral clock  register,                                     Address offset: 0xD4  */

+ __IO uint32_t AHB1ENR;        /*!< RCC AHB1 peripheral clock  register,                                     Address offset: 0xD8  */

+ __IO uint32_t AHB2ENR;        /*!< RCC AHB2 peripheral clock  register,                                     Address offset: 0xDC  */

+ __IO uint32_t AHB4ENR;        /*!< RCC AHB4 peripheral clock  register,                                     Address offset: 0xE0  */

+ __IO uint32_t APB3ENR;        /*!< RCC APB3 peripheral clock  register,                                     Address offset: 0xE4  */

+ __IO uint32_t APB1LENR;       /*!< RCC APB1 peripheral clock  Low Word register,                            Address offset: 0xE8  */

+ __IO uint32_t APB1HENR;       /*!< RCC APB1 peripheral clock  High Word register,                           Address offset: 0xEC  */

+ __IO uint32_t APB2ENR;        /*!< RCC APB2 peripheral clock  register,                                     Address offset: 0xF0  */

+ __IO uint32_t APB4ENR;        /*!< RCC APB4 peripheral clock  register,                                     Address offset: 0xF4  */

+ uint32_t      RESERVED12;      /*!< Reserved,                                                                Address offset: 0xF8  */

+ __IO uint32_t AHB3LPENR;      /*!< RCC AHB3 peripheral sleep clock  register,                               Address offset: 0xFC  */

+ __IO uint32_t AHB1LPENR;      /*!< RCC AHB1 peripheral sleep clock  register,                               Address offset: 0x100 */

+ __IO uint32_t AHB2LPENR;      /*!< RCC AHB2 peripheral sleep clock  register,                               Address offset: 0x104 */

+ __IO uint32_t AHB4LPENR;      /*!< RCC AHB4 peripheral sleep clock  register,                               Address offset: 0x108 */

+ __IO uint32_t APB3LPENR;      /*!< RCC APB3 peripheral sleep clock  register,                               Address offset: 0x10C */

+ __IO uint32_t APB1LLPENR;     /*!< RCC APB1 peripheral sleep clock  Low Word register,                      Address offset: 0x110 */

+ __IO uint32_t APB1HLPENR;     /*!< RCC APB1 peripheral sleep clock  High Word register,                     Address offset: 0x114 */

+ __IO uint32_t APB2LPENR;      /*!< RCC APB2 peripheral sleep clock  register,                               Address offset: 0x118 */

+ __IO uint32_t APB4LPENR;      /*!< RCC APB4 peripheral sleep clock  register,                               Address offset: 0x11C */

+ uint32_t     RESERVED13[4];   /*!< Reserved, 0x120-0x12C                                                    Address offset: 0x120 */

+

+} RCC_TypeDef;

+

+

+/**

+  * @brief Real-Time Clock

+  */

+typedef struct

+{

+  __IO uint32_t TR;             /*!< RTC time register,                              Address offset: 0x00 */

+  __IO uint32_t DR;             /*!< RTC date register,                              Address offset: 0x04 */

+  __IO uint32_t SSR;            /*!< RTC sub second register,                        Address offset: 0x08 */

+  __IO uint32_t ICSR;           /*!< RTC initialization control and status register, Address offset: 0x0C */

+  __IO uint32_t PRER;           /*!< RTC prescaler register,                         Address offset: 0x10 */

+  __IO uint32_t WUTR;           /*!< RTC wakeup timer register,                      Address offset: 0x14 */

+  __IO uint32_t CR;             /*!< RTC control register,                           Address offset: 0x18 */

+       uint32_t RESERVED0;      /*!< Reserved,                                       Address offset: 0x1C */

+       uint32_t RESERVED1;      /*!< Reserved,                                       Address offset: 0x20 */

+  __IO uint32_t WPR;            /*!< RTC write protection register,                  Address offset: 0x24 */

+  __IO uint32_t CALR;           /*!< RTC calibration register,                       Address offset: 0x28 */

+  __IO uint32_t SHIFTR;         /*!< RTC shift control register,                     Address offset: 0x2C */

+  __IO uint32_t TSTR;           /*!< RTC time stamp time register,                   Address offset: 0x30 */

+  __IO uint32_t TSDR;           /*!< RTC time stamp date register,                   Address offset: 0x34 */

+  __IO uint32_t TSSSR;          /*!< RTC time-stamp sub second register,             Address offset: 0x38 */

+       uint32_t RESERVED2;      /*!< Reserved,                                       Address offset: 0x3C */

+  __IO uint32_t ALRMAR;         /*!< RTC alarm A register,                           Address offset: 0x40 */

+  __IO uint32_t ALRMASSR;       /*!< RTC alarm A sub second register,                Address offset: 0x44 */

+  __IO uint32_t ALRMBR;         /*!< RTC alarm B register,                           Address offset: 0x48 */

+  __IO uint32_t ALRMBSSR;       /*!< RTC alarm B sub second register,                Address offset: 0x4C */

+  __IO uint32_t SR;             /*!< RTC Status register,                            Address offset: 0x50 */

+  __IO uint32_t MISR;           /*!< RTC masked interrupt status register,           Address offset: 0x54 */

+       uint32_t RESERVED3;      /*!< Reserved,                                       Address offset: 0x58 */

+  __IO uint32_t SCR;            /*!< RTC status Clear register,                      Address offset: 0x5C */

+  __IO uint32_t CFGR;           /*!< RTC configuration register,                     Address offset: 0x60 */

+} RTC_TypeDef;

+

+/**

+  * @brief Tamper and backup registers

+  */

+typedef struct

+{

+  __IO uint32_t CR1;            /*!< TAMP configuration register 1,            Address offset: 0x00 */

+  __IO uint32_t CR2;            /*!< TAMP configuration register 2,            Address offset: 0x04 */

+       uint32_t RESERVED0;      /*!< Reserved,                                 Address offset: 0x08 */

+  __IO uint32_t FLTCR;          /*!< TAMP filter control register,             Address offset: 0x0C */

+  __IO uint32_t ATCR1;          /*!< TAMP active tamper control register,      Address offset: 0x10 */

+  __IO uint32_t ATSEEDR;        /*!< TAMP active tamper seed register,         Address offset: 0x14 */

+  __IO uint32_t ATOR;           /*!< TAMP active tamper output register,       Address offset: 0x18 */

+       uint32_t RESERVED1[4];   /*!< Reserved,                                 Address offset: 0x1C -- 0x28 */

+  __IO uint32_t IER;            /*!< TAMP interrupt enable register,           Address offset: 0x2C */

+  __IO uint32_t SR;             /*!< TAMP status register,                     Address offset: 0x30 */

+  __IO uint32_t MISR;           /*!< TAMP masked interrupt status register,    Address offset: 0x34 */

+       uint32_t RESERVED2;      /*!< Reserved,                                 Address offset: 0x38 */

+  __IO uint32_t SCR;            /*!< TAMP status clear register,               Address offset: 0x3C */

+  __IO uint32_t COUNTR;         /*!< TAMP monotonic counter register,          Address offset: 0x40 */

+       uint32_t RESERVED3[3];   /*!< Reserved,                                 Address offset: 0x44 -- 0x4C */

+  __IO uint32_t CFGR;           /*!< TAMP configuration register,              Address offset: 0x50 */

+       uint32_t RESERVED4[43];  /*!< Reserved,                                 Address offset: 0x54 -- 0xFC */

+  __IO uint32_t BKP0R;          /*!< TAMP backup register 0,                   Address offset: 0x100 */

+  __IO uint32_t BKP1R;          /*!< TAMP backup register 1,                   Address offset: 0x104 */

+  __IO uint32_t BKP2R;          /*!< TAMP backup register 2,                   Address offset: 0x108 */

+  __IO uint32_t BKP3R;          /*!< TAMP backup register 3,                   Address offset: 0x10C */

+  __IO uint32_t BKP4R;          /*!< TAMP backup register 4,                   Address offset: 0x110 */

+  __IO uint32_t BKP5R;          /*!< TAMP backup register 5,                   Address offset: 0x114 */

+  __IO uint32_t BKP6R;          /*!< TAMP backup register 6,                   Address offset: 0x118 */

+  __IO uint32_t BKP7R;          /*!< TAMP backup register 7,                   Address offset: 0x11C */

+  __IO uint32_t BKP8R;          /*!< TAMP backup register 8,                   Address offset: 0x120 */

+  __IO uint32_t BKP9R;          /*!< TAMP backup register 9,                   Address offset: 0x124 */

+  __IO uint32_t BKP10R;         /*!< TAMP backup register 10,                  Address offset: 0x128 */

+  __IO uint32_t BKP11R;         /*!< TAMP backup register 11,                  Address offset: 0x12C */

+  __IO uint32_t BKP12R;         /*!< TAMP backup register 12,                  Address offset: 0x130 */

+  __IO uint32_t BKP13R;         /*!< TAMP backup register 13,                  Address offset: 0x134 */

+  __IO uint32_t BKP14R;         /*!< TAMP backup register 14,                  Address offset: 0x138 */

+  __IO uint32_t BKP15R;         /*!< TAMP backup register 15,                  Address offset: 0x13C */

+  __IO uint32_t BKP16R;         /*!< TAMP backup register 16,                  Address offset: 0x140 */

+  __IO uint32_t BKP17R;         /*!< TAMP backup register 17,                  Address offset: 0x144 */

+  __IO uint32_t BKP18R;         /*!< TAMP backup register 18,                  Address offset: 0x148 */

+  __IO uint32_t BKP19R;         /*!< TAMP backup register 19,                  Address offset: 0x14C */

+  __IO uint32_t BKP20R;         /*!< TAMP backup register 20,                  Address offset: 0x150 */

+  __IO uint32_t BKP21R;         /*!< TAMP backup register 21,                  Address offset: 0x154 */

+  __IO uint32_t BKP22R;         /*!< TAMP backup register 22,                  Address offset: 0x158 */

+  __IO uint32_t BKP23R;         /*!< TAMP backup register 23,                  Address offset: 0x15C */

+  __IO uint32_t BKP24R;         /*!< TAMP backup register 24,                  Address offset: 0x160 */

+  __IO uint32_t BKP25R;         /*!< TAMP backup register 25,                  Address offset: 0x164 */

+  __IO uint32_t BKP26R;         /*!< TAMP backup register 26,                  Address offset: 0x168 */

+  __IO uint32_t BKP27R;         /*!< TAMP backup register 27,                  Address offset: 0x16C */

+  __IO uint32_t BKP28R;         /*!< TAMP backup register 28,                  Address offset: 0x170 */

+  __IO uint32_t BKP29R;         /*!< TAMP backup register 29,                  Address offset: 0x174 */

+  __IO uint32_t BKP30R;         /*!< TAMP backup register 30,                  Address offset: 0x178 */

+  __IO uint32_t BKP31R;         /*!< TAMP backup register 31,                  Address offset: 0x17C */

+} TAMP_TypeDef;

+

+/**

+  * @brief Serial Audio Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t GCR;           /*!< SAI global configuration register, Address offset: 0x00 */

+  uint32_t      RESERVED0[16]; /*!< Reserved, 0x04 - 0x43                                   */

+  __IO uint32_t PDMCR;         /*!< SAI PDM control register,          Address offset: 0x44 */

+  __IO uint32_t PDMDLY;        /*!< SAI PDM delay register,            Address offset: 0x48 */

+} SAI_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */

+  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */

+  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */

+  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */

+  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */

+  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */

+  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */

+  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */

+} SAI_Block_TypeDef;

+

+/**

+  * @brief SPDIF-RX Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */

+  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */

+  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */

+  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */

+  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */

+  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */

+  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */

+  uint32_t        RESERVED2;    /*!< Reserved,  0x1A                                          */

+} SPDIFRX_TypeDef;

+

+

+/**

+  * @brief Secure digital input/output Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t POWER;          /*!< SDMMC power control register,             Address offset: 0x00  */

+  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,             Address offset: 0x04  */

+  __IO uint32_t ARG;            /*!< SDMMC argument register,                  Address offset: 0x08  */

+  __IO uint32_t CMD;            /*!< SDMMC command register,                   Address offset: 0x0C  */

+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register,          Address offset: 0x10  */

+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                Address offset: 0x14  */

+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                Address offset: 0x18  */

+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                Address offset: 0x1C  */

+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                Address offset: 0x20  */

+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                Address offset: 0x24  */

+  __IO uint32_t DLEN;           /*!< SDMMC data length register,               Address offset: 0x28  */

+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,              Address offset: 0x2C  */

+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,              Address offset: 0x30  */

+  __I uint32_t  STA;            /*!< SDMMC status register,                    Address offset: 0x34  */

+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,           Address offset: 0x38  */

+  __IO uint32_t MASK;           /*!< SDMMC mask register,                      Address offset: 0x3C  */

+  __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,     Address offset: 0x40  */

+  uint32_t      RESERVED0[3];   /*!< Reserved, 0x44 - 0x4C - 0x4C                                    */

+  __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,               Address offset: 0x50  */

+  __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,           Address offset: 0x54  */

+  __IO uint32_t IDMABASE0;      /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58  */

+  __IO uint32_t IDMABASE1;      /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C  */

+  uint32_t      RESERVED1[8];   /*!< Reserved, 0x60-0x7C                                             */

+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,                 Address offset: 0x80  */

+  uint32_t      RESERVED2[222]; /*!< Reserved, 0x84-0x3F8                                            */

+  __IO uint32_t IPVR;           /*!< SDMMC data FIFO register,                 Address offset: 0x3FC */

+} SDMMC_TypeDef;

+

+

+/**

+  * @brief Delay Block DLYB

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;          /*!< DELAY BLOCK control register,  Address offset: 0x00 */

+  __IO uint32_t CFGR;        /*!< DELAY BLOCK configuration register,  Address offset: 0x04 */

+} DLYB_TypeDef;

+

+/**

+  * @brief HW Semaphore HSEM

+  */

+

+typedef struct

+{

+  __IO uint32_t R[32];      /*!< 2-step write lock and read back registers,     Address offset: 00h-7Ch  */

+  __IO uint32_t RLR[32];    /*!< 1-step read lock registers,                    Address offset: 80h-FCh  */

+  __IO uint32_t C1IER;      /*!< HSEM Interrupt enable register ,             Address offset: 100h     */

+  __IO uint32_t C1ICR;      /*!< HSEM Interrupt clear register ,              Address offset: 104h     */

+  __IO uint32_t C1ISR;      /*!< HSEM Interrupt Status register ,             Address offset: 108h     */

+  __IO uint32_t C1MISR;     /*!< HSEM Interrupt Masked Status register ,      Address offset: 10Ch     */

+  uint32_t  Reserved[12];   /* Reserved                                       Address offset: 110h-13Ch  */

+  __IO uint32_t CR;         /*!< HSEM Semaphore clear register ,                Address offset: 140h      */

+  __IO uint32_t KEYR;       /*!< HSEM Semaphore clear key register ,            Address offset: 144h      */

+

+} HSEM_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t IER;        /*!< HSEM interrupt enable register ,                Address offset:   0h     */

+  __IO uint32_t ICR;        /*!< HSEM interrupt clear register ,                 Address offset:   4h     */

+  __IO uint32_t ISR;        /*!< HSEM interrupt status register ,                Address offset:   8h     */

+  __IO uint32_t MISR;       /*!< HSEM masked interrupt status register ,         Address offset:   Ch     */

+} HSEM_Common_TypeDef;

+

+/**

+  * @brief Serial Peripheral Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */

+  __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */

+  __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */

+  __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */

+  __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */

+  __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */

+  __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */

+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */

+  __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */

+  uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */

+  __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */

+  uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */

+  __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */

+  __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */

+  __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */

+  __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */

+  __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */

+

+} SPI_TypeDef;

+

+/**

+  * @brief DTS

+  */

+typedef struct

+{

+  __IO uint32_t CFGR1;         /*!< DTS configuration register,                Address offset: 0x00 */

+  uint32_t RESERVED0;          /*!< Reserved,                                  Address offset: 0x04 */

+  __IO uint32_t T0VALR1;       /*!< DTS T0 Value register,                     Address offset: 0x08 */

+  uint32_t RESERVED1;          /*!< Reserved,                                  Address offset: 0x0C */

+  __IO uint32_t RAMPVALR;      /*!< DTS Ramp value register,                   Address offset: 0x10 */

+  __IO uint32_t ITR1;          /*!< DTS Interrupt threshold register,          Address offset: 0x14 */

+  uint32_t RESERVED2;          /*!< Reserved,                                  Address offset: 0x18 */

+  __IO uint32_t DR;            /*!< DTS data register,                         Address offset: 0x1C */

+  __IO uint32_t SR;            /*!< DTS status register                        Address offset: 0x20 */

+  __IO uint32_t ITENR;         /*!< DTS Interrupt enable register,             Address offset: 0x24 */

+  __IO uint32_t ICIFR;         /*!< DTS Clear Interrupt flag register,         Address offset: 0x28 */

+  __IO uint32_t OR;            /*!< DTS option register 1,                     Address offset: 0x2C */

+}

+DTS_TypeDef;

+

+/**

+  * @brief TIM

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */

+  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */

+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */

+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */

+  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */

+  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */

+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */

+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */

+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */

+  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */

+  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */

+  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */

+  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */

+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */

+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */

+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */

+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */

+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */

+  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */

+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */

+  uint32_t      RESERVED1;   /*!< Reserved, 0x50                                                 */

+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */

+  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */

+  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */

+  __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */

+  __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */

+  __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x68 */

+} TIM_TypeDef;

+

+/**

+  * @brief LPTIMIMER

+  */

+typedef struct

+{

+  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,         Address offset: 0x00 */

+  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,              Address offset: 0x04 */

+  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,             Address offset: 0x08 */

+  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                Address offset: 0x0C */

+  __IO uint32_t CR;       /*!< LPTIM Control register,                      Address offset: 0x10 */

+  __IO uint32_t CMP;      /*!< LPTIM Compare register,                      Address offset: 0x14 */

+  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                   Address offset: 0x18 */

+  __IO uint32_t CNT;      /*!< LPTIM Counter register,                      Address offset: 0x1C */

+  uint32_t  RESERVED1;    /*!< Reserved, 0x20                                                    */

+  __IO uint32_t CFGR2;    /*!< LPTIM Configuration register,                Address offset: 0x24 */

+} LPTIM_TypeDef;

+

+/**

+  * @brief Comparator

+  */

+typedef struct

+{

+  __IO uint32_t SR;        /*!< Comparator status register,                    Address offset: 0x00 */

+  __IO uint32_t ICFR;      /*!< Comparator interrupt clear flag register,       Address offset: 0x04 */

+  __IO uint32_t OR;        /*!< Comparator option register,                  Address offset: 0x08 */

+} COMPOPT_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CFGR;      /*!< Comparator configuration register  ,           Address offset: 0x00 */

+} COMP_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CFGR;       /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */

+} COMP_Common_TypeDef;

+/**

+  * @brief Universal Synchronous Asynchronous Receiver Transmitter

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */

+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */

+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */

+  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */

+  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */

+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */

+  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */

+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */

+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */

+  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */

+  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */

+  __IO uint32_t PRESC;  /*!< USART clock Prescaler register,           Address offset: 0x2C */

+} USART_TypeDef;

+

+/**

+  * @brief Single Wire Protocol Master Interface SPWMI

+  */

+typedef struct

+{

+  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */

+  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */

+    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */

+  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */

+  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */

+  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */

+  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */

+  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */

+  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */

+  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */

+} SWPMI_TypeDef;

+

+/**

+  * @brief Window WATCHDOG

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */

+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */

+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */

+} WWDG_TypeDef;

+

+

+/**

+  * @brief RAM_ECC_Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t CR;           /*!< RAMECC monitor configuration register          */

+  __IO uint32_t SR;           /*!< RAMECC monitor status register                 */

+  __IO uint32_t FAR;          /*!< RAMECC monitor failing address register        */

+  __IO uint32_t FDRL;         /*!< RAMECC monitor failing data low register       */

+  __IO uint32_t FDRH;         /*!< RAMECC monitor failing data high register      */

+  __IO uint32_t FECR;         /*!< RAMECC monitor failing ECC error code register */

+} RAMECC_MonitorTypeDef;

+

+typedef struct

+{

+  __IO uint32_t IER;          /*!< RAMECC interrupt enable register */

+} RAMECC_TypeDef;

+/**

+  * @}

+  */

+

+

+/**

+  * @brief Crypto Processor

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */

+  __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */

+  __IO uint32_t DIN;         /*!< CRYP data input register,                                Address offset: 0x08 */

+  __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */

+  __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */

+  __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */

+  __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */

+  __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */

+  __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */

+  __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */

+  __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */

+  __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */

+  __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */

+  __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */

+  __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */

+  __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */

+  __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */

+  __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */

+  __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */

+  __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */

+  __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */

+  __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */

+  __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */

+  __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */

+  __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */

+  __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */

+  __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */

+  __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */

+  __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */

+  __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */

+  __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */

+  __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */

+  __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */

+  __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */

+  __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */

+  __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */

+} CRYP_TypeDef;

+

+/**

+  * @brief HASH

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */

+  __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */

+  __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */

+  __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */

+  __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */

+  __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */

+       uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */

+  __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */

+} HASH_TypeDef;

+

+/**

+  * @brief HASH_DIGEST

+  */

+

+typedef struct

+{

+  __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */

+} HASH_DIGEST_TypeDef;

+

+

+/**

+  * @brief RNG

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */

+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */

+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */

+  uint32_t RESERVED;

+  __IO uint32_t HTCR;  /*!< RNG health test configuration register, Address offset: 0x10 */

+} RNG_TypeDef;

+

+/**

+  * @brief MDIOS

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;

+  __IO uint32_t WRFR;

+  __IO uint32_t CWRFR;

+  __IO uint32_t RDFR;

+  __IO uint32_t CRDFR;

+  __IO uint32_t SR;

+  __IO uint32_t CLRFR;

+  uint32_t RESERVED[57];

+  __IO uint32_t DINR0;

+  __IO uint32_t DINR1;

+  __IO uint32_t DINR2;

+  __IO uint32_t DINR3;

+  __IO uint32_t DINR4;

+  __IO uint32_t DINR5;

+  __IO uint32_t DINR6;

+  __IO uint32_t DINR7;

+  __IO uint32_t DINR8;

+  __IO uint32_t DINR9;

+  __IO uint32_t DINR10;

+  __IO uint32_t DINR11;

+  __IO uint32_t DINR12;

+  __IO uint32_t DINR13;

+  __IO uint32_t DINR14;

+  __IO uint32_t DINR15;

+  __IO uint32_t DINR16;

+  __IO uint32_t DINR17;

+  __IO uint32_t DINR18;

+  __IO uint32_t DINR19;

+  __IO uint32_t DINR20;

+  __IO uint32_t DINR21;

+  __IO uint32_t DINR22;

+  __IO uint32_t DINR23;

+  __IO uint32_t DINR24;

+  __IO uint32_t DINR25;

+  __IO uint32_t DINR26;

+  __IO uint32_t DINR27;

+  __IO uint32_t DINR28;

+  __IO uint32_t DINR29;

+  __IO uint32_t DINR30;

+  __IO uint32_t DINR31;

+  __IO uint32_t DOUTR0;

+  __IO uint32_t DOUTR1;

+  __IO uint32_t DOUTR2;

+  __IO uint32_t DOUTR3;

+  __IO uint32_t DOUTR4;

+  __IO uint32_t DOUTR5;

+  __IO uint32_t DOUTR6;

+  __IO uint32_t DOUTR7;

+  __IO uint32_t DOUTR8;

+  __IO uint32_t DOUTR9;

+  __IO uint32_t DOUTR10;

+  __IO uint32_t DOUTR11;

+  __IO uint32_t DOUTR12;

+  __IO uint32_t DOUTR13;

+  __IO uint32_t DOUTR14;

+  __IO uint32_t DOUTR15;

+  __IO uint32_t DOUTR16;

+  __IO uint32_t DOUTR17;

+  __IO uint32_t DOUTR18;

+  __IO uint32_t DOUTR19;

+  __IO uint32_t DOUTR20;

+  __IO uint32_t DOUTR21;

+  __IO uint32_t DOUTR22;

+  __IO uint32_t DOUTR23;

+  __IO uint32_t DOUTR24;

+  __IO uint32_t DOUTR25;

+  __IO uint32_t DOUTR26;

+  __IO uint32_t DOUTR27;

+  __IO uint32_t DOUTR28;

+  __IO uint32_t DOUTR29;

+  __IO uint32_t DOUTR30;

+  __IO uint32_t DOUTR31;

+} MDIOS_TypeDef;

+

+

+/**

+  * @brief USB_OTG_Core_Registers

+  */

+typedef struct

+{

+ __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */

+  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */

+  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */

+  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */

+  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */

+  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */

+  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */

+  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */

+  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */

+  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */

+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */

+  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */

+  uint32_t Reserved30[2];             /*!< Reserved                                     030h */

+  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */

+  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */

+  __IO uint32_t GSNPSID;              /* USB_OTG core ID                                040h*/

+  __IO uint32_t GHWCFG1;              /* User HW config1                                044h*/

+  __IO uint32_t GHWCFG2;              /* User HW config2                                048h*/

+  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */

+  uint32_t  Reserved6;                /*!< Reserved                                     050h */

+  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */

+  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */

+  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */

+   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */

+    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */

+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */

+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */

+} USB_OTG_GlobalTypeDef;

+

+

+/**

+  * @brief USB_OTG_device_Registers

+  */

+typedef struct

+{

+  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */

+  __IO uint32_t DCTL;            /*!< dev Control Register         804h */

+  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */

+  uint32_t Reserved0C;           /*!< Reserved                     80Ch */

+  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */

+  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */

+  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */

+  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */

+  uint32_t  Reserved20;          /*!< Reserved                     820h */

+  uint32_t Reserved9;            /*!< Reserved                     824h */

+  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */

+  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */

+  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */

+  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */

+  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */

+  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */

+  uint32_t Reserved40;           /*!< dedicated EP mask            840h */

+  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */

+  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */

+  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */

+} USB_OTG_DeviceTypeDef;

+

+

+/**

+  * @brief USB_OTG_IN_Endpoint-Specific_Register

+  */

+typedef struct

+{

+  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */

+  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */

+  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */

+  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */

+  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */

+  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */

+  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */

+  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */

+} USB_OTG_INEndpointTypeDef;

+

+

+/**

+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */

+  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */

+  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */

+  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */

+  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */

+  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */

+  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */

+} USB_OTG_OUTEndpointTypeDef;

+

+

+/**

+  * @brief USB_OTG_Host_Mode_Register_Structures

+  */

+typedef struct

+{

+  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */

+  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */

+  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */

+  uint32_t Reserved40C;           /*!< Reserved                             40Ch */

+  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */

+  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */

+  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */

+} USB_OTG_HostTypeDef;

+

+/**

+  * @brief USB_OTG_Host_Channel_Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */

+  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */

+  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */

+  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */

+  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */

+  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */

+  uint32_t Reserved[2];           /*!< Reserved                                      */

+} USB_OTG_HostChannelTypeDef;

+/**

+  * @}

+  */

+

+/**

+  * @brief OCTO Serial Peripheral Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;          /*!< OCTOSPI Control register,                           Address offset: 0x000 */

+  uint32_t RESERVED;         /*!< Reserved,                                           Address offset: 0x004 */

+  __IO uint32_t DCR1;        /*!< OCTOSPI Device Configuration register 1,            Address offset: 0x008 */

+  __IO uint32_t DCR2;        /*!< OCTOSPI Device Configuration register 2,            Address offset: 0x00C */

+  __IO uint32_t DCR3;        /*!< OCTOSPI Device Configuration register 3,            Address offset: 0x010 */

+  __IO uint32_t DCR4;        /*!< OCTOSPI Device Configuration register 4,            Address offset: 0x014 */

+  uint32_t RESERVED1[2];     /*!< Reserved,                                           Address offset: 0x018-0x01C */

+  __IO uint32_t SR;          /*!< OCTOSPI Status register,                            Address offset: 0x020 */

+  __IO uint32_t FCR;         /*!< OCTOSPI Flag Clear register,                        Address offset: 0x024 */

+  uint32_t RESERVED2[6];     /*!< Reserved,                                           Address offset: 0x028-0x03C */

+  __IO uint32_t DLR;         /*!< OCTOSPI Data Length register,                       Address offset: 0x040 */

+  uint32_t RESERVED3;        /*!< Reserved,                                           Address offset: 0x044 */

+  __IO uint32_t AR;          /*!< OCTOSPI Address register,                           Address offset: 0x048 */

+  uint32_t RESERVED4;        /*!< Reserved,                                           Address offset: 0x04C */

+  __IO uint32_t DR;          /*!< OCTOSPI Data register,                              Address offset: 0x050 */

+  uint32_t RESERVED5[11];    /*!< Reserved,                                           Address offset: 0x054-0x07C */

+  __IO uint32_t PSMKR;       /*!< OCTOSPI Polling Status Mask register,               Address offset: 0x080 */

+  uint32_t RESERVED6;        /*!< Reserved,                                           Address offset: 0x084 */

+  __IO uint32_t PSMAR;       /*!< OCTOSPI Polling Status Match register,              Address offset: 0x088 */

+  uint32_t RESERVED7;        /*!< Reserved,                                           Address offset: 0x08C */

+  __IO uint32_t PIR;         /*!< OCTOSPI Polling Interval register,                  Address offset: 0x090 */

+  uint32_t RESERVED8[27];    /*!< Reserved,                                           Address offset: 0x094-0x0FC */

+  __IO uint32_t CCR;         /*!< OCTOSPI Communication Configuration register,       Address offset: 0x100 */

+  uint32_t RESERVED9;        /*!< Reserved,                                           Address offset: 0x104 */

+  __IO uint32_t TCR;         /*!< OCTOSPI Timing Configuration register,              Address offset: 0x108 */

+  uint32_t RESERVED10;       /*!< Reserved,                                           Address offset: 0x10C */

+  __IO uint32_t IR;          /*!< OCTOSPI Instruction register,                       Address offset: 0x110 */

+  uint32_t RESERVED11[3];    /*!< Reserved,                                           Address offset: 0x114-0x11C */

+  __IO uint32_t ABR;         /*!< OCTOSPI Alternate Bytes register,                   Address offset: 0x120 */

+  uint32_t RESERVED12[3];    /*!< Reserved,                                           Address offset: 0x124-0x12C */

+  __IO uint32_t LPTR;        /*!< OCTOSPI Low Power Timeout register,                 Address offset: 0x130 */

+  uint32_t RESERVED13[3];    /*!< Reserved,                                           Address offset: 0x134-0x13C */

+  __IO uint32_t WPCCR;       /*!< OCTOSPI Wrap Communication Configuration register,  Address offset: 0x140 */

+  uint32_t RESERVED14;       /*!< Reserved,                                           Address offset: 0x144 */

+  __IO uint32_t WPTCR;       /*!< OCTOSPI Wrap Timing Configuration register,         Address offset: 0x148 */

+  uint32_t RESERVED15;       /*!< Reserved,                                           Address offset: 0x14C */

+  __IO uint32_t WPIR;        /*!< OCTOSPI Wrap Instruction register,                  Address offset: 0x150 */

+  uint32_t RESERVED16[3];    /*!< Reserved,                                           Address offset: 0x154-0x15C */

+  __IO uint32_t WPABR;       /*!< OCTOSPI Wrap Alternate Bytes register,              Address offset: 0x160 */

+  uint32_t RESERVED17[7];    /*!< Reserved,                                           Address offset: 0x164-0x17C */

+  __IO uint32_t WCCR;        /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */

+  uint32_t RESERVED18;       /*!< Reserved,                                           Address offset: 0x184 */

+  __IO uint32_t WTCR;        /*!< OCTOSPI Write Timing Configuration register,        Address offset: 0x188 */

+  uint32_t RESERVED19;       /*!< Reserved,                                           Address offset: 0x18C */

+  __IO uint32_t WIR;         /*!< OCTOSPI Write Instruction register,                 Address offset: 0x190 */

+  uint32_t RESERVED20[3];    /*!< Reserved,                                           Address offset: 0x194-0x19C */

+  __IO uint32_t WABR;        /*!< OCTOSPI Write Alternate Bytes register,             Address offset: 0x1A0 */

+  uint32_t RESERVED21[23];   /*!< Reserved,                                           Address offset: 0x1A4-0x1FC */

+  __IO uint32_t HLCR;        /*!< OCTOSPI Hyperbus Latency Configuration register,    Address offset: 0x200 */

+  uint32_t RESERVED22[122];  /*!< Reserved,                                           Address offset: 0x204-0x3EC */

+  __IO uint32_t HWCFGR;      /*!< OCTOSPI HW Configuration register,                  Address offset: 0x3F0 */

+  __IO uint32_t VER;         /*!< OCTOSPI Version register,                           Address offset: 0x3F4 */

+  __IO uint32_t ID;          /*!< OCTOSPI Identification register,                    Address offset: 0x3F8 */

+  __IO uint32_t MID;         /*!< OCTOPSI HW Magic ID register,                       Address offset: 0x3FC */

+} OCTOSPI_TypeDef;

+

+/**

+  * @}

+  */

+/**

+  * @brief OCTO Serial Peripheral Interface IO Manager

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;          /*!< OCTOSPI IO Manager Control register,                 Address offset: 0x00 */

+  __IO uint32_t PCR[3];      /*!< OCTOSPI IO Manager Port[1:3] Configuration register, Address offset: 0x04-0x20 */

+} OCTOSPIM_TypeDef;

+

+/**

+  * @}

+  */

+

+/**

+  * @brief OTFD register

+  */

+typedef struct

+{

+  __IO uint32_t REG_CONFIGR;

+  __IO uint32_t REG_START_ADDR;

+  __IO uint32_t REG_END_ADDR;

+  __IO uint32_t REG_NONCER0;

+  __IO uint32_t REG_NONCER1;

+  __IO uint32_t REG_KEYR0;

+  __IO uint32_t REG_KEYR1;

+  __IO uint32_t REG_KEYR2;

+  __IO uint32_t REG_KEYR3;

+} OTFDEC_Region_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CR;

+  uint32_t RESERVED1[191];

+  __IO uint32_t ISR;

+  __IO uint32_t ICR;

+  __IO uint32_t IER;

+  uint32_t RESERVED2[56];

+  __IO uint32_t HWCFGR2;

+  __IO uint32_t HWCFGR1;

+  __IO uint32_t VERR;

+  __IO uint32_t IPIDR;

+  __IO uint32_t SIDR;

+} OTFDEC_TypeDef;

+/**

+  * @}

+  */

+

+/** @addtogroup Peripheral_memory_map

+  * @{

+  */

+#define CD_ITCMRAM_BASE           (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM  */

+#define CD_DTCMRAM_BASE           (0x20000000UL) /*!< Base address of : 128KB (2x64KB) system data RAM accessible over DTCM                   */

+#define CD_AXIFLASH_BASE          (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI                */

+

+#define CD_AXISRAM1_BASE          (0x24000000UL) /*!< Base address of : (up to 256KB) system data RAM1 accessible over over AXI                */

+#define CD_AXISRAM2_BASE          (0x24040000UL) /*!< Base address of : (up to 384KB) system data RAM2 accessible over over AXI                */

+#define CD_AXISRAM3_BASE          (0x240A0000UL) /*!< Base address of : (up to 384KB) system data RAM3 accessible over over AXI                */

+#define CD_AHBSRAM1_BASE          (0x30000000UL) /*!< Base address of : (up to 64KB) system data RAM1 accessible over over AXI->AHB Bridge     */

+#define CD_AHBSRAM2_BASE          (0x30010000UL) /*!< Base address of : (up to 64KB) system data RAM2 accessible over over AXI->AHB Bridge     */

+

+#define SRD_BKPSRAM_BASE           (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge                                */

+#define SRD_SRAM_BASE              (0x38000000UL) /*!< Base address of : Backup SRAM(32 KB) over AXI->AHB Bridge                               */

+

+#define OCTOSPI1_BASE             (0x90000000UL) /*!< Base address of : OCTOSPI1 memories  accessible over AXI                                 */

+#define OCTOSPI2_BASE             (0x70000000UL) /*!< Base address of : OCTOSPI2 memories  accessible over AXI                                 */

+

+#define FLASH_BANK1_BASE          (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI                          */

+#define FLASH_BANK2_BASE          (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI                          */

+#define FLASH_END                 (0x081FFFFFUL) /*!< FLASH end address                                                                       */

+

+/* Legacy define */

+#define FLASH_BASE                FLASH_BANK1_BASE

+#define D1_AXISRAM_BASE           CD_AXISRAM1_BASE

+

+#define FLASH_OTP_BASE            (0x08FFF000UL) /*!< Base address of : (up to 1KB) embedded FLASH Bank1 OTP Area                           */

+#define FLASH_OTP_END             (0x08FFF3FFUL) /*!< End address of : (up to 1KB) embedded FLASH Bank1 OTP Area                            */

+

+

+/*!< Device electronic signature memory map */

+#define UID_BASE                  (0x08FFF800UL)            /*!< Unique device ID register base address */

+#define FLASHSIZE_BASE            (0x08FFF80CUL)            /*!< FLASH Size register base address */

+#define PACKAGE_BASE              (0x08FFF80EUL)            /*!< Package Data register base address */

+

+#define PERIPH_BASE               (0x40000000UL) /*!< Base address of : AHB/ABP Peripherals                                                    */

+/*!< Peripheral memory map */

+#define CD_APB1PERIPH_BASE        PERIPH_BASE                   /*!<  D2_APB1PERIPH_BASE        PERIPH_BASE                                    */

+#define CD_APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)   /*!<  D2_APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)                    */

+#define CD_AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)   /*!<  D2_AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)                    */

+#define CD_AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)   /*!<  D2_AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)                    */

+

+#define CD_APB3PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)   /*!<  D1_APB1PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)                    */

+#define CD_AHB3PERIPH_BASE       (PERIPH_BASE + 0x12000000UL)   /*!<  D1_AHB1PERIPH_BASE       (PERIPH_BASE + 0x12000000UL)                    */

+

+#define SRD_APB4PERIPH_BASE      (PERIPH_BASE + 0x18000000UL)   /*!<  D3_APB1PERIPH_BASE       (PERIPH_BASE + 0x18000000UL)                    */

+#define SRD_AHB4PERIPH_BASE      (PERIPH_BASE + 0x18020000UL)   /*!<  D3_AHB1PERIPH_BASE       (PERIPH_BASE + 0x18020000UL)                    */

+

+/*!< Legacy Peripheral memory map */

+#define APB1PERIPH_BASE        PERIPH_BASE

+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)

+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)

+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)

+

+/*!< CD_AHB3PERIPH peripherals */

+#define MDMA_BASE             (CD_AHB3PERIPH_BASE + 0x0000UL)

+#define DMA2D_BASE            (CD_AHB3PERIPH_BASE + 0x1000UL)

+#define FLASH_R_BASE          (CD_AHB3PERIPH_BASE + 0x2000UL)

+#define JPGDEC_BASE           (CD_AHB3PERIPH_BASE + 0x3000UL)

+#define FMC_R_BASE            (CD_AHB3PERIPH_BASE + 0x4000UL)

+#define OCTOSPI1_R_BASE       (CD_AHB3PERIPH_BASE + 0x5000UL)

+#define DLYB_OCTOSPI1_BASE    (CD_AHB3PERIPH_BASE + 0x6000UL)

+#define SDMMC1_BASE           (CD_AHB3PERIPH_BASE + 0x7000UL)

+#define DLYB_SDMMC1_BASE      (CD_AHB3PERIPH_BASE + 0x8000UL)

+#define RAMECC_BASE           (CD_AHB3PERIPH_BASE + 0x9000UL)

+#define OCTOSPI2_R_BASE       (CD_AHB3PERIPH_BASE + 0xA000UL)

+#define DLYB_OCTOSPI2_BASE    (CD_AHB3PERIPH_BASE + 0xB000UL)

+#define OCTOSPIM_BASE         (CD_AHB3PERIPH_BASE + 0xB400UL)

+

+/*!< CD_AHB1PERIPH peripherals */

+

+#define DMA1_BASE               (CD_AHB1PERIPH_BASE + 0x0000UL)

+#define DMA2_BASE               (CD_AHB1PERIPH_BASE + 0x0400UL)

+#define DMAMUX1_BASE            (CD_AHB1PERIPH_BASE + 0x0800UL)

+#define ADC1_BASE               (CD_AHB1PERIPH_BASE + 0x2000UL)

+#define ADC2_BASE               (CD_AHB1PERIPH_BASE + 0x2100UL)

+#define ADC12_COMMON_BASE       (CD_AHB1PERIPH_BASE + 0x2300UL)

+#define CRC_BASE                (CD_AHB1PERIPH_BASE + 0x3000UL)

+

+/*!< USB registers base address */

+#define USB1_OTG_HS_PERIPH_BASE              (0x40040000UL)

+#define USB_OTG_GLOBAL_BASE                  (0x000UL)

+#define USB_OTG_DEVICE_BASE                  (0x800UL)

+#define USB_OTG_IN_ENDPOINT_BASE             (0x900UL)

+#define USB_OTG_OUT_ENDPOINT_BASE            (0xB00UL)

+#define USB_OTG_EP_REG_SIZE                  (0x20UL)

+#define USB_OTG_HOST_BASE                    (0x400UL)

+#define USB_OTG_HOST_PORT_BASE               (0x440UL)

+#define USB_OTG_HOST_CHANNEL_BASE            (0x500UL)

+#define USB_OTG_HOST_CHANNEL_SIZE            (0x20UL)

+#define USB_OTG_PCGCCTL_BASE                 (0xE00UL)

+#define USB_OTG_FIFO_BASE                    (0x1000UL)

+#define USB_OTG_FIFO_SIZE                    (0x1000UL)

+

+/*!< CD_AHB2PERIPH peripherals */

+

+#define DCMI_BASE              (CD_AHB2PERIPH_BASE + 0x0000UL)

+#define PSSI_BASE              (CD_AHB2PERIPH_BASE + 0x0400UL)

+#define HSEM_BASE              (CD_AHB2PERIPH_BASE + 0x0800UL)

+#define CRYP_BASE              (CD_AHB2PERIPH_BASE + 0x1000UL)

+#define HASH_BASE              (CD_AHB2PERIPH_BASE + 0x1400UL)

+#define HASH_DIGEST_BASE       (CD_AHB2PERIPH_BASE + 0x1710UL)

+#define RNG_BASE               (CD_AHB2PERIPH_BASE + 0x1800UL)

+#define SDMMC2_BASE            (CD_AHB2PERIPH_BASE + 0x2400UL)

+#define DLYB_SDMMC2_BASE       (CD_AHB2PERIPH_BASE + 0x2800UL)

+#define BDMA1_BASE             (CD_AHB2PERIPH_BASE + 0x2C00UL)

+

+/*!< SRD_AHB4PERIPH peripherals */

+#define GPIOA_BASE            (SRD_AHB4PERIPH_BASE + 0x0000UL)

+#define GPIOB_BASE            (SRD_AHB4PERIPH_BASE + 0x0400UL)

+#define GPIOC_BASE            (SRD_AHB4PERIPH_BASE + 0x0800UL)

+#define GPIOD_BASE            (SRD_AHB4PERIPH_BASE + 0x0C00UL)

+#define GPIOE_BASE            (SRD_AHB4PERIPH_BASE + 0x1000UL)

+#define GPIOF_BASE            (SRD_AHB4PERIPH_BASE + 0x1400UL)

+#define GPIOG_BASE            (SRD_AHB4PERIPH_BASE + 0x1800UL)

+#define GPIOH_BASE            (SRD_AHB4PERIPH_BASE + 0x1C00UL)

+#define GPIOI_BASE            (SRD_AHB4PERIPH_BASE + 0x2000UL)

+#define GPIOJ_BASE            (SRD_AHB4PERIPH_BASE + 0x2400UL)

+#define GPIOK_BASE            (SRD_AHB4PERIPH_BASE + 0x2800UL)

+#define RCC_BASE              (SRD_AHB4PERIPH_BASE + 0x4400UL)

+#define PWR_BASE              (SRD_AHB4PERIPH_BASE + 0x4800UL)

+#define BDMA2_BASE            (SRD_AHB4PERIPH_BASE + 0x5400UL)

+#define DMAMUX2_BASE          (SRD_AHB4PERIPH_BASE + 0x5800UL)

+

+/*!< CD_APB3PERIPH peripherals */

+#define LTDC_BASE             (CD_APB3PERIPH_BASE + 0x1000UL)

+#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84UL)

+#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104UL)

+#define WWDG1_BASE            (CD_APB3PERIPH_BASE + 0x3000UL)

+

+/*!< CD_APB1PERIPH peripherals */

+#define TIM2_BASE             (CD_APB1PERIPH_BASE + 0x0000UL)

+#define TIM3_BASE             (CD_APB1PERIPH_BASE + 0x0400UL)

+#define TIM4_BASE             (CD_APB1PERIPH_BASE + 0x0800UL)

+#define TIM5_BASE             (CD_APB1PERIPH_BASE + 0x0C00UL)

+#define TIM6_BASE             (CD_APB1PERIPH_BASE + 0x1000UL)

+#define TIM7_BASE             (CD_APB1PERIPH_BASE + 0x1400UL)

+#define TIM12_BASE            (CD_APB1PERIPH_BASE + 0x1800UL)

+#define TIM13_BASE            (CD_APB1PERIPH_BASE + 0x1C00UL)

+#define TIM14_BASE            (CD_APB1PERIPH_BASE + 0x2000UL)

+#define LPTIM1_BASE           (CD_APB1PERIPH_BASE + 0x2400UL)

+

+#define SPI2_BASE             (CD_APB1PERIPH_BASE + 0x3800UL)

+#define SPI3_BASE             (CD_APB1PERIPH_BASE + 0x3C00UL)

+#define SPDIFRX_BASE          (CD_APB1PERIPH_BASE + 0x4000UL)

+#define USART2_BASE           (CD_APB1PERIPH_BASE + 0x4400UL)

+#define USART3_BASE           (CD_APB1PERIPH_BASE + 0x4800UL)

+#define UART4_BASE            (CD_APB1PERIPH_BASE + 0x4C00UL)

+#define UART5_BASE            (CD_APB1PERIPH_BASE + 0x5000UL)

+#define I2C1_BASE             (CD_APB1PERIPH_BASE + 0x5400UL)

+#define I2C2_BASE             (CD_APB1PERIPH_BASE + 0x5800UL)

+#define I2C3_BASE             (CD_APB1PERIPH_BASE + 0x5C00UL)

+#define CEC_BASE              (CD_APB1PERIPH_BASE + 0x6C00UL)

+#define DAC1_BASE             (CD_APB1PERIPH_BASE + 0x7400UL)

+#define UART7_BASE            (CD_APB1PERIPH_BASE + 0x7800UL)

+#define UART8_BASE            (CD_APB1PERIPH_BASE + 0x7C00UL)

+#define CRS_BASE              (CD_APB1PERIPH_BASE + 0x8400UL)

+#define SWPMI1_BASE           (CD_APB1PERIPH_BASE + 0x8800UL)

+#define OPAMP_BASE            (CD_APB1PERIPH_BASE + 0x9000UL)

+#define OPAMP1_BASE           (CD_APB1PERIPH_BASE + 0x9000UL)

+#define OPAMP2_BASE           (CD_APB1PERIPH_BASE + 0x9010UL)

+#define MDIOS_BASE            (CD_APB1PERIPH_BASE + 0x9400UL)

+#define FDCAN1_BASE           (CD_APB1PERIPH_BASE + 0xA000UL)

+#define FDCAN2_BASE           (CD_APB1PERIPH_BASE + 0xA400UL)

+#define FDCAN_CCU_BASE        (CD_APB1PERIPH_BASE + 0xA800UL)

+#define SRAMCAN_BASE          (CD_APB1PERIPH_BASE + 0xAC00UL)

+

+/*!< CD_APB2PERIPH peripherals */

+

+#define TIM1_BASE             (CD_APB2PERIPH_BASE + 0x0000UL)

+#define TIM8_BASE             (CD_APB2PERIPH_BASE + 0x0400UL)

+#define USART1_BASE           (CD_APB2PERIPH_BASE + 0x1000UL)

+#define USART6_BASE           (CD_APB2PERIPH_BASE + 0x1400UL)

+#define UART9_BASE            (CD_APB2PERIPH_BASE + 0x1800UL)

+#define USART10_BASE          (CD_APB2PERIPH_BASE + 0x1C00UL)

+#define SPI1_BASE             (CD_APB2PERIPH_BASE + 0x3000UL)

+#define SPI4_BASE             (CD_APB2PERIPH_BASE + 0x3400UL)

+#define TIM15_BASE            (CD_APB2PERIPH_BASE + 0x4000UL)

+#define TIM16_BASE            (CD_APB2PERIPH_BASE + 0x4400UL)

+#define TIM17_BASE            (CD_APB2PERIPH_BASE + 0x4800UL)

+#define SPI5_BASE             (CD_APB2PERIPH_BASE + 0x5000UL)

+#define SAI1_BASE             (CD_APB2PERIPH_BASE + 0x5800UL)

+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)

+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)

+#define SAI2_BASE             (CD_APB2PERIPH_BASE + 0x5C00UL)

+#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004UL)

+#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024UL)

+#define DFSDM1_BASE           (CD_APB2PERIPH_BASE + 0x7800UL)

+#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00UL)

+#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20UL)

+#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40UL)

+#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60UL)

+#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80UL)

+#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0UL)

+#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0UL)

+#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0UL)

+#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)

+#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)

+#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)

+#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)

+#define DFSDM1_Filter4_BASE   (DFSDM1_BASE + 0x300UL)

+#define DFSDM1_Filter5_BASE   (DFSDM1_BASE + 0x380UL)

+#define DFSDM1_Filter6_BASE   (DFSDM1_BASE + 0x400UL)

+#define DFSDM1_Filter7_BASE   (DFSDM1_BASE + 0x480UL)

+/*!< SRD_APB4PERIPH peripherals */

+#define EXTI_BASE             (SRD_APB4PERIPH_BASE + 0x0000UL)

+#define EXTI_D1_BASE          (EXTI_BASE + 0x0080UL)

+#define SYSCFG_BASE           (SRD_APB4PERIPH_BASE + 0x0400UL)

+#define LPUART1_BASE          (SRD_APB4PERIPH_BASE + 0x0C00UL)

+#define SPI6_BASE             (SRD_APB4PERIPH_BASE + 0x1400UL)

+#define I2C4_BASE             (SRD_APB4PERIPH_BASE + 0x1C00UL)

+#define LPTIM2_BASE           (SRD_APB4PERIPH_BASE + 0x2400UL)

+#define LPTIM3_BASE           (SRD_APB4PERIPH_BASE + 0x2800UL)

+#define DAC2_BASE             (SRD_APB4PERIPH_BASE + 0x3400UL)

+#define COMP12_BASE           (SRD_APB4PERIPH_BASE + 0x3800UL)

+#define COMP1_BASE            (COMP12_BASE + 0x0CUL)

+#define COMP2_BASE            (COMP12_BASE + 0x10UL)

+#define VREFBUF_BASE          (SRD_APB4PERIPH_BASE + 0x3C00UL)

+#define RTC_BASE              (SRD_APB4PERIPH_BASE + 0x4000UL)

+#define TAMP_BASE             (SRD_APB4PERIPH_BASE + 0x4400UL)

+#define IWDG1_BASE            (SRD_APB4PERIPH_BASE + 0x4800UL)

+

+#define DTS_BASE              (SRD_APB4PERIPH_BASE + 0x6800UL)

+

+#define DFSDM2_BASE           (SRD_APB4PERIPH_BASE + 0x6C00UL)

+#define DFSDM2_Channel0_BASE  (DFSDM2_BASE + 0x00UL)

+#define DFSDM2_Channel1_BASE  (DFSDM2_BASE + 0x20UL)

+#define DFSDM2_FLT0_BASE      (DFSDM2_BASE + 0x100UL)

+

+/*!< CD_AHB3PERIPH peripherals */

+

+#define OTFDEC1_BASE          (CD_AHB3PERIPH_BASE + 0xB800UL)

+#define OTFDEC1_REGION1_BASE  (OTFDEC1_BASE + 0x20UL)

+#define OTFDEC1_REGION2_BASE  (OTFDEC1_BASE + 0x50UL)

+#define OTFDEC1_REGION3_BASE  (OTFDEC1_BASE + 0x80UL)

+#define OTFDEC1_REGION4_BASE  (OTFDEC1_BASE + 0xB0UL)

+#define OTFDEC2_BASE          (CD_AHB3PERIPH_BASE + 0xBC00UL)

+#define OTFDEC2_REGION1_BASE  (OTFDEC2_BASE + 0x20UL)

+#define OTFDEC2_REGION2_BASE  (OTFDEC2_BASE + 0x50UL)

+#define OTFDEC2_REGION3_BASE  (OTFDEC2_BASE + 0x80UL)

+#define OTFDEC2_REGION4_BASE  (OTFDEC2_BASE + 0xB0UL)

+#define GFXMMU_BASE           (CD_AHB3PERIPH_BASE + 0xC000UL)

+

+#define BDMA1_Channel0_BASE    (BDMA1_BASE + 0x0008UL)

+#define BDMA1_Channel1_BASE    (BDMA1_BASE + 0x001CUL)

+#define BDMA1_Channel2_BASE    (BDMA1_BASE + 0x0030UL)

+#define BDMA1_Channel3_BASE    (BDMA1_BASE + 0x0044UL)

+#define BDMA1_Channel4_BASE    (BDMA1_BASE + 0x0058UL)

+#define BDMA1_Channel5_BASE    (BDMA1_BASE + 0x006CUL)

+#define BDMA1_Channel6_BASE    (BDMA1_BASE + 0x0080UL)

+#define BDMA1_Channel7_BASE    (BDMA1_BASE + 0x0094UL)

+

+#define BDMA2_Channel0_BASE    (BDMA2_BASE + 0x0008UL)

+#define BDMA2_Channel1_BASE    (BDMA2_BASE + 0x001CUL)

+#define BDMA2_Channel2_BASE    (BDMA2_BASE + 0x0030UL)

+#define BDMA2_Channel3_BASE    (BDMA2_BASE + 0x0044UL)

+#define BDMA2_Channel4_BASE    (BDMA2_BASE + 0x0058UL)

+#define BDMA2_Channel5_BASE    (BDMA2_BASE + 0x006CUL)

+#define BDMA2_Channel6_BASE    (BDMA2_BASE + 0x0080UL)

+#define BDMA2_Channel7_BASE    (BDMA2_BASE + 0x0094UL)

+

+

+#define DMAMUX2_Channel0_BASE    (DMAMUX2_BASE)

+#define DMAMUX2_Channel1_BASE    (DMAMUX2_BASE + 0x0004UL)

+#define DMAMUX2_Channel2_BASE    (DMAMUX2_BASE + 0x0008UL)

+#define DMAMUX2_Channel3_BASE    (DMAMUX2_BASE + 0x000CUL)

+#define DMAMUX2_Channel4_BASE    (DMAMUX2_BASE + 0x0010UL)

+#define DMAMUX2_Channel5_BASE    (DMAMUX2_BASE + 0x0014UL)

+#define DMAMUX2_Channel6_BASE    (DMAMUX2_BASE + 0x0018UL)

+#define DMAMUX2_Channel7_BASE    (DMAMUX2_BASE + 0x001CUL)

+

+#define DMAMUX2_RequestGenerator0_BASE  (DMAMUX2_BASE + 0x0100UL)

+#define DMAMUX2_RequestGenerator1_BASE  (DMAMUX2_BASE + 0x0104UL)

+#define DMAMUX2_RequestGenerator2_BASE  (DMAMUX2_BASE + 0x0108UL)

+#define DMAMUX2_RequestGenerator3_BASE  (DMAMUX2_BASE + 0x010CUL)

+#define DMAMUX2_RequestGenerator4_BASE  (DMAMUX2_BASE + 0x0110UL)

+#define DMAMUX2_RequestGenerator5_BASE  (DMAMUX2_BASE + 0x0114UL)

+#define DMAMUX2_RequestGenerator6_BASE  (DMAMUX2_BASE + 0x0118UL)

+#define DMAMUX2_RequestGenerator7_BASE  (DMAMUX2_BASE + 0x011CUL)

+

+#define DMAMUX2_ChannelStatus_BASE      (DMAMUX2_BASE + 0x0080UL)

+#define DMAMUX2_RequestGenStatus_BASE   (DMAMUX2_BASE + 0x0140UL)

+

+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)

+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)

+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)

+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)

+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)

+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)

+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)

+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)

+

+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)

+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)

+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)

+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)

+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)

+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)

+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)

+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)

+

+

+#define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)

+#define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)

+#define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)

+#define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)

+#define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)

+#define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)

+#define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0018UL)

+#define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x001CUL)

+#define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0020UL)

+#define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x0024UL)

+#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)

+#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)

+#define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)

+#define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)

+#define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)

+#define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)

+

+#define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)

+#define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)

+#define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)

+#define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)

+#define DMAMUX1_RequestGenerator4_BASE  (DMAMUX1_BASE + 0x0110UL)

+#define DMAMUX1_RequestGenerator5_BASE  (DMAMUX1_BASE + 0x0114UL)

+#define DMAMUX1_RequestGenerator6_BASE  (DMAMUX1_BASE + 0x0118UL)

+#define DMAMUX1_RequestGenerator7_BASE  (DMAMUX1_BASE + 0x011CUL)

+

+#define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)

+#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)

+

+/*!< FMC Banks registers base  address */

+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)

+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)

+#define FMC_Bank2_R_BASE      (FMC_R_BASE + 0x0060UL)

+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)

+#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)

+

+/* Debug MCU registers base address */

+#define DBGMCU_BASE           (0x5C001000UL)

+

+#define MDMA_Channel0_BASE    (MDMA_BASE + 0x00000040UL)

+#define MDMA_Channel1_BASE    (MDMA_BASE + 0x00000080UL)

+#define MDMA_Channel2_BASE    (MDMA_BASE + 0x000000C0UL)

+#define MDMA_Channel3_BASE    (MDMA_BASE + 0x00000100UL)

+#define MDMA_Channel4_BASE    (MDMA_BASE + 0x00000140UL)

+#define MDMA_Channel5_BASE    (MDMA_BASE + 0x00000180UL)

+#define MDMA_Channel6_BASE    (MDMA_BASE + 0x000001C0UL)

+#define MDMA_Channel7_BASE    (MDMA_BASE + 0x00000200UL)

+#define MDMA_Channel8_BASE    (MDMA_BASE + 0x00000240UL)

+#define MDMA_Channel9_BASE    (MDMA_BASE + 0x00000280UL)

+#define MDMA_Channel10_BASE   (MDMA_BASE + 0x000002C0UL)

+#define MDMA_Channel11_BASE   (MDMA_BASE + 0x00000300UL)

+#define MDMA_Channel12_BASE   (MDMA_BASE + 0x00000340UL)

+#define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)

+#define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)

+#define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)

+#define MDMA_Channel16_BASE   (MDMA_BASE + 0x00000440UL)

+

+/* GFXMMU virtual buffers base address */

+#define GFXMMU_VIRTUAL_BUFFERS_BASE  (0x25000000UL)

+#define GFXMMU_VIRTUAL_BUFFER0_BASE  (GFXMMU_VIRTUAL_BUFFERS_BASE)

+#define GFXMMU_VIRTUAL_BUFFER1_BASE  (GFXMMU_VIRTUAL_BUFFERS_BASE + 0x400000UL)

+#define GFXMMU_VIRTUAL_BUFFER2_BASE  (GFXMMU_VIRTUAL_BUFFERS_BASE + 0x800000UL)

+#define GFXMMU_VIRTUAL_BUFFER3_BASE  (GFXMMU_VIRTUAL_BUFFERS_BASE + 0xC00000UL)

+

+#define RAMECC_Monitor1_BASE (RAMECC_BASE + 0x20UL)

+#define RAMECC_Monitor2_BASE (RAMECC_BASE + 0x40UL)

+#define RAMECC_Monitor3_BASE (RAMECC_BASE + 0x60UL)

+

+/**

+  * @}

+  */

+

+/** @addtogroup Peripheral_declaration

+  * @{

+  */

+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)

+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)

+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)

+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)

+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)

+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)

+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)

+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)

+#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)

+#define RTC                 ((RTC_TypeDef *) RTC_BASE)

+#define TAMP                ((TAMP_TypeDef *) TAMP_BASE)

+#define WWDG1               ((WWDG_TypeDef *) WWDG1_BASE)

+

+

+#define IWDG1               ((IWDG_TypeDef *) IWDG1_BASE)

+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)

+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)

+#define SPI4                ((SPI_TypeDef *) SPI4_BASE)

+#define SPI5                ((SPI_TypeDef *) SPI5_BASE)

+#define SPI6                ((SPI_TypeDef *) SPI6_BASE)

+#define USART2              ((USART_TypeDef *) USART2_BASE)

+#define USART3              ((USART_TypeDef *) USART3_BASE)

+#define USART6              ((USART_TypeDef *) USART6_BASE)

+#define USART10             ((USART_TypeDef *) USART10_BASE)

+#define UART7               ((USART_TypeDef *) UART7_BASE)

+#define UART8               ((USART_TypeDef *) UART8_BASE)

+#define UART9               ((USART_TypeDef *) UART9_BASE)

+#define CRS                 ((CRS_TypeDef *) CRS_BASE)

+#define UART4               ((USART_TypeDef *) UART4_BASE)

+#define UART5               ((USART_TypeDef *) UART5_BASE)

+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)

+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)

+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)

+#define I2C4                ((I2C_TypeDef *) I2C4_BASE)

+#define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

+#define FDCAN2              ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

+#define FDCAN_CCU           ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

+#define CEC                 ((CEC_TypeDef *) CEC_BASE)

+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)

+#define PWR                 ((PWR_TypeDef *) PWR_BASE)

+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)

+#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)

+#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)

+#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)

+#define LPTIM3              ((LPTIM_TypeDef *) LPTIM3_BASE)

+#define DTS                 ((DTS_TypeDef *) DTS_BASE)

+

+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)

+#define COMP12              ((COMPOPT_TypeDef *) COMP12_BASE)

+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)

+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)

+#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)

+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)

+#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)

+#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)

+

+

+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)

+#define EXTI_D1             ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)

+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)

+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)

+#define USART1              ((USART_TypeDef *) USART1_BASE)

+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)

+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)

+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)

+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)

+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)

+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

+#define SAI2                ((SAI_TypeDef *) SAI2_BASE)

+#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)

+#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)

+

+#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

+#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

+#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

+#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

+#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

+#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

+#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

+#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

+#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

+#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

+#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

+#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

+#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

+#define DFSDM1_Filter4      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter4_BASE)

+#define DFSDM1_Filter5      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter5_BASE)

+#define DFSDM1_Filter6      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter6_BASE)

+#define DFSDM1_Filter7      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter7_BASE)

+#define DFSDM2_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel0_BASE)

+#define DFSDM2_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel1_BASE)

+#define DFSDM2_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM2_FLT0_BASE)

+#define DMA2D               ((DMA2D_TypeDef *) DMA2D_BASE)

+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)

+#define PSSI                ((PSSI_TypeDef *) PSSI_BASE)

+#define RCC                 ((RCC_TypeDef *) RCC_BASE)

+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)

+#define CRC                 ((CRC_TypeDef *) CRC_BASE)

+

+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)

+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)

+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)

+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)

+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)

+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)

+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)

+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)

+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)

+#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)

+#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)

+

+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)

+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)

+#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

+

+#define CRYP                ((CRYP_TypeDef *) CRYP_BASE)

+#define HASH                ((HASH_TypeDef *) HASH_BASE)

+#define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)

+#define RNG                 ((RNG_TypeDef *) RNG_BASE)

+#define SDMMC2              ((SDMMC_TypeDef *) SDMMC2_BASE)

+#define DLYB_SDMMC2         ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

+

+#define BDMA1                ((BDMA_TypeDef *) BDMA1_BASE)

+#define BDMA1_Channel0       ((BDMA_Channel_TypeDef *) BDMA1_Channel0_BASE)

+#define BDMA1_Channel1       ((BDMA_Channel_TypeDef *) BDMA1_Channel1_BASE)

+#define BDMA1_Channel2       ((BDMA_Channel_TypeDef *) BDMA1_Channel2_BASE)

+#define BDMA1_Channel3       ((BDMA_Channel_TypeDef *) BDMA1_Channel3_BASE)

+#define BDMA1_Channel4       ((BDMA_Channel_TypeDef *) BDMA1_Channel4_BASE)

+#define BDMA1_Channel5       ((BDMA_Channel_TypeDef *) BDMA1_Channel5_BASE)

+#define BDMA1_Channel6       ((BDMA_Channel_TypeDef *) BDMA1_Channel6_BASE)

+#define BDMA1_Channel7       ((BDMA_Channel_TypeDef *) BDMA1_Channel7_BASE)

+

+#define BDMA2                ((BDMA_TypeDef *) BDMA2_BASE)

+#define BDMA2_Channel0       ((BDMA_Channel_TypeDef *) BDMA2_Channel0_BASE)

+#define BDMA2_Channel1       ((BDMA_Channel_TypeDef *) BDMA2_Channel1_BASE)

+#define BDMA2_Channel2       ((BDMA_Channel_TypeDef *) BDMA2_Channel2_BASE)

+#define BDMA2_Channel3       ((BDMA_Channel_TypeDef *) BDMA2_Channel3_BASE)

+#define BDMA2_Channel4       ((BDMA_Channel_TypeDef *) BDMA2_Channel4_BASE)

+#define BDMA2_Channel5       ((BDMA_Channel_TypeDef *) BDMA2_Channel5_BASE)

+#define BDMA2_Channel6       ((BDMA_Channel_TypeDef *) BDMA2_Channel6_BASE)

+#define BDMA2_Channel7       ((BDMA_Channel_TypeDef *) BDMA2_Channel7_BASE)

+

+#define RAMECC               ((RAMECC_TypeDef *)RAMECC_BASE)

+#define RAMECC_Monitor1      ((RAMECC_MonitorTypeDef *)RAMECC_Monitor1_BASE)

+#define RAMECC_Monitor2      ((RAMECC_MonitorTypeDef *)RAMECC_Monitor2_BASE)

+#define RAMECC_Monitor3      ((RAMECC_MonitorTypeDef *)RAMECC_Monitor3_BASE)

+

+#define DMAMUX2                ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

+#define DMAMUX2_Channel0       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

+#define DMAMUX2_Channel1       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

+#define DMAMUX2_Channel2       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

+#define DMAMUX2_Channel3       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

+#define DMAMUX2_Channel4       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

+#define DMAMUX2_Channel5       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

+#define DMAMUX2_Channel6       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

+#define DMAMUX2_Channel7       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

+

+

+#define DMAMUX2_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

+#define DMAMUX2_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

+#define DMAMUX2_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

+#define DMAMUX2_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

+#define DMAMUX2_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

+#define DMAMUX2_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

+#define DMAMUX2_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

+#define DMAMUX2_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

+

+#define DMAMUX2_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

+#define DMAMUX2_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

+

+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)

+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

+

+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)

+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

+

+

+#define DMAMUX1              ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

+#define DMAMUX1_Channel0     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

+#define DMAMUX1_Channel1     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

+#define DMAMUX1_Channel2     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

+#define DMAMUX1_Channel3     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

+#define DMAMUX1_Channel4     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

+#define DMAMUX1_Channel5     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

+#define DMAMUX1_Channel6     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

+#define DMAMUX1_Channel7     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

+#define DMAMUX1_Channel8     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

+#define DMAMUX1_Channel9     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

+#define DMAMUX1_Channel10    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

+#define DMAMUX1_Channel11    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

+#define DMAMUX1_Channel12    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

+#define DMAMUX1_Channel13    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

+#define DMAMUX1_Channel14    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

+#define DMAMUX1_Channel15    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

+

+#define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

+#define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

+#define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

+#define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

+#define DMAMUX1_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

+#define DMAMUX1_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

+#define DMAMUX1_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

+#define DMAMUX1_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

+

+#define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *)    DMAMUX1_ChannelStatus_BASE)

+#define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

+

+

+#define FMC_Bank1_R           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

+#define FMC_Bank1E_R          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

+#define FMC_Bank2_R           ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

+#define FMC_Bank3_R           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

+#define FMC_Bank5_6_R         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

+

+#define DAC2                ((DAC_TypeDef *) DAC2_BASE)

+#define OCTOSPI1            ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)

+#define DLYB_OCTOSPI1       ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE)

+#define OCTOSPI2            ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)

+#define DLYB_OCTOSPI2       ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE)

+#define OCTOSPIM            ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)

+

+#define OTFDEC1               ((OTFDEC_TypeDef *) OTFDEC1_BASE)

+#define OTFDEC1_REGION1       ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE)

+#define OTFDEC1_REGION2       ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE)

+#define OTFDEC1_REGION3       ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE)

+#define OTFDEC1_REGION4       ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE)

+

+#define OTFDEC2               ((OTFDEC_TypeDef *) OTFDEC2_BASE)

+#define OTFDEC2_REGION1       ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE)

+#define OTFDEC2_REGION2       ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE)

+#define OTFDEC2_REGION3       ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE)

+#define OTFDEC2_REGION4       ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE)

+#define GFXMMU              ((GFXMMU_TypeDef *) GFXMMU_BASE)

+

+#define SDMMC1                ((SDMMC_TypeDef *) SDMMC1_BASE)

+#define DLYB_SDMMC1           ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

+

+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)

+

+#define JPEG                ((JPEG_TypeDef *) JPGDEC_BASE)

+#define HSEM                ((HSEM_TypeDef *) HSEM_BASE)

+#define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

+

+#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)

+#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

+#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

+

+#define MDIOS               ((MDIOS_TypeDef *) MDIOS_BASE)

+

+#define MDMA                ((MDMA_TypeDef *)MDMA_BASE)

+#define MDMA_Channel0       ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

+#define MDMA_Channel1       ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

+#define MDMA_Channel2       ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

+#define MDMA_Channel3       ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

+#define MDMA_Channel4       ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

+#define MDMA_Channel5       ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

+#define MDMA_Channel6       ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

+#define MDMA_Channel7       ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

+#define MDMA_Channel8       ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

+#define MDMA_Channel9       ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

+#define MDMA_Channel10      ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

+#define MDMA_Channel11      ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

+#define MDMA_Channel12      ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

+#define MDMA_Channel13      ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

+#define MDMA_Channel14      ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

+#define MDMA_Channel15      ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

+

+

+#define USB1_OTG_HS         ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

+

+/* Legacy defines */

+#define USB_OTG_HS                   USB1_OTG_HS

+#define USB_OTG_HS_PERIPH_BASE       USB1_OTG_HS_PERIPH_BASE

+

+/**

+  * @}

+  */

+

+/** @addtogroup Exported_constants

+  * @{

+  */

+

+  /** @addtogroup Peripheral_Registers_Bits_Definition

+  * @{

+  */

+

+/******************************************************************************/

+/*                         Peripheral Registers_Bits_Definition               */

+/******************************************************************************/

+

+/******************************************************************************/

+/*                                                                            */

+/*                        Analog to Digital Converter                         */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  ADC VERSION  ********************************/

+#define ADC_VER_V5_3

+/********************  Bit definition for ADC_ISR register  ********************/

+#define ADC_ISR_ADRDY_Pos                 (0U)

+#define ADC_ISR_ADRDY_Msk                 (0x1UL << ADC_ISR_ADRDY_Pos)         /*!< 0x00000001 */

+#define ADC_ISR_ADRDY                     ADC_ISR_ADRDY_Msk                    /*!< ADC Ready (ADRDY) flag  */

+#define ADC_ISR_EOSMP_Pos                 (1U)

+#define ADC_ISR_EOSMP_Msk                 (0x1UL << ADC_ISR_EOSMP_Pos)         /*!< 0x00000002 */

+#define ADC_ISR_EOSMP                     ADC_ISR_EOSMP_Msk                    /*!< ADC End of Sampling flag */

+#define ADC_ISR_EOC_Pos                   (2U)

+#define ADC_ISR_EOC_Msk                   (0x1UL << ADC_ISR_EOC_Pos)           /*!< 0x00000004 */

+#define ADC_ISR_EOC                       ADC_ISR_EOC_Msk                      /*!< ADC End of Regular Conversion flag */

+#define ADC_ISR_EOS_Pos                   (3U)

+#define ADC_ISR_EOS_Msk                   (0x1UL << ADC_ISR_EOS_Pos)           /*!< 0x00000008 */

+#define ADC_ISR_EOS                       ADC_ISR_EOS_Msk                      /*!< ADC End of Regular sequence of Conversions flag */

+#define ADC_ISR_OVR_Pos                   (4U)

+#define ADC_ISR_OVR_Msk                   (0x1UL << ADC_ISR_OVR_Pos)           /*!< 0x00000010 */

+#define ADC_ISR_OVR                       ADC_ISR_OVR_Msk                      /*!< ADC overrun flag */

+#define ADC_ISR_JEOC_Pos                  (5U)

+#define ADC_ISR_JEOC_Msk                  (0x1UL << ADC_ISR_JEOC_Pos)          /*!< 0x00000020 */

+#define ADC_ISR_JEOC                      ADC_ISR_JEOC_Msk                     /*!< ADC End of Injected Conversion flag */

+#define ADC_ISR_JEOS_Pos                  (6U)

+#define ADC_ISR_JEOS_Msk                  (0x1UL << ADC_ISR_JEOS_Pos)          /*!< 0x00000040 */

+#define ADC_ISR_JEOS                      ADC_ISR_JEOS_Msk                     /*!< ADC End of Injected sequence of Conversions flag */

+#define ADC_ISR_AWD1_Pos                  (7U)

+#define ADC_ISR_AWD1_Msk                  (0x1UL << ADC_ISR_AWD1_Pos)          /*!< 0x00000080 */

+#define ADC_ISR_AWD1                      ADC_ISR_AWD1_Msk                     /*!< ADC Analog watchdog 1 flag */

+#define ADC_ISR_AWD2_Pos                  (8U)

+#define ADC_ISR_AWD2_Msk                  (0x1UL << ADC_ISR_AWD2_Pos)          /*!< 0x00000100 */

+#define ADC_ISR_AWD2                      ADC_ISR_AWD2_Msk                     /*!< ADC Analog watchdog 2 flag */

+#define ADC_ISR_AWD3_Pos                  (9U)

+#define ADC_ISR_AWD3_Msk                  (0x1UL << ADC_ISR_AWD3_Pos)          /*!< 0x00000200 */

+#define ADC_ISR_AWD3                      ADC_ISR_AWD3_Msk                     /*!< ADC Analog watchdog 3 flag */

+#define ADC_ISR_JQOVF_Pos                 (10U)

+#define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */

+#define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */

+

+/********************  Bit definition for ADC_IER register  ********************/

+#define ADC_IER_ADRDYIE_Pos               (0U)

+#define ADC_IER_ADRDYIE_Msk               (0x1UL << ADC_IER_ADRDYIE_Pos)       /*!< 0x00000001 */

+#define ADC_IER_ADRDYIE                   ADC_IER_ADRDYIE_Msk                  /*!< ADC Ready (ADRDY) interrupt source */

+#define ADC_IER_EOSMPIE_Pos               (1U)

+#define ADC_IER_EOSMPIE_Msk               (0x1UL << ADC_IER_EOSMPIE_Pos)       /*!< 0x00000002 */

+#define ADC_IER_EOSMPIE                   ADC_IER_EOSMPIE_Msk                  /*!< ADC End of Sampling interrupt source */

+#define ADC_IER_EOCIE_Pos                 (2U)

+#define ADC_IER_EOCIE_Msk                 (0x1UL << ADC_IER_EOCIE_Pos)         /*!< 0x00000004 */

+#define ADC_IER_EOCIE                     ADC_IER_EOCIE_Msk                    /*!< ADC End of Regular Conversion interrupt source */

+#define ADC_IER_EOSIE_Pos                 (3U)

+#define ADC_IER_EOSIE_Msk                 (0x1UL << ADC_IER_EOSIE_Pos)         /*!< 0x00000008 */

+#define ADC_IER_EOSIE                     ADC_IER_EOSIE_Msk                    /*!< ADC End of Regular sequence of Conversions interrupt source */

+#define ADC_IER_OVRIE_Pos                 (4U)

+#define ADC_IER_OVRIE_Msk                 (0x1UL << ADC_IER_OVRIE_Pos)         /*!< 0x00000010 */

+#define ADC_IER_OVRIE                     ADC_IER_OVRIE_Msk                    /*!< ADC overrun interrupt source */

+#define ADC_IER_JEOCIE_Pos                (5U)

+#define ADC_IER_JEOCIE_Msk                (0x1UL << ADC_IER_JEOCIE_Pos)        /*!< 0x00000020 */

+#define ADC_IER_JEOCIE                    ADC_IER_JEOCIE_Msk                   /*!< ADC End of Injected Conversion interrupt source */

+#define ADC_IER_JEOSIE_Pos                (6U)

+#define ADC_IER_JEOSIE_Msk                (0x1UL << ADC_IER_JEOSIE_Pos)        /*!< 0x00000040 */

+#define ADC_IER_JEOSIE                    ADC_IER_JEOSIE_Msk                   /*!< ADC End of Injected sequence of Conversions interrupt source */

+#define ADC_IER_AWD1IE_Pos                (7U)

+#define ADC_IER_AWD1IE_Msk                (0x1UL << ADC_IER_AWD1IE_Pos)        /*!< 0x00000080 */

+#define ADC_IER_AWD1IE                    ADC_IER_AWD1IE_Msk                   /*!< ADC Analog watchdog 1 interrupt source */

+#define ADC_IER_AWD2IE_Pos                (8U)

+#define ADC_IER_AWD2IE_Msk                (0x1UL << ADC_IER_AWD2IE_Pos)        /*!< 0x00000100 */

+#define ADC_IER_AWD2IE                    ADC_IER_AWD2IE_Msk                   /*!< ADC Analog watchdog 2 interrupt source */

+#define ADC_IER_AWD3IE_Pos                (9U)

+#define ADC_IER_AWD3IE_Msk                (0x1UL << ADC_IER_AWD3IE_Pos)        /*!< 0x00000200 */

+#define ADC_IER_AWD3IE                    ADC_IER_AWD3IE_Msk                   /*!< ADC Analog watchdog 3 interrupt source */

+#define ADC_IER_JQOVFIE_Pos               (10U)

+#define ADC_IER_JQOVFIE_Msk               (0x1UL << ADC_IER_JQOVFIE_Pos)       /*!< 0x00000400 */

+#define ADC_IER_JQOVFIE                   ADC_IER_JQOVFIE_Msk                  /*!< ADC Injected Context Queue Overflow interrupt source */

+

+/********************  Bit definition for ADC_CR register  ********************/

+#define ADC_CR_ADEN_Pos                   (0U)

+#define ADC_CR_ADEN_Msk                   (0x1UL << ADC_CR_ADEN_Pos)           /*!< 0x00000001 */

+#define ADC_CR_ADEN                       ADC_CR_ADEN_Msk                      /*!< ADC Enable control */

+#define ADC_CR_ADDIS_Pos                  (1U)

+#define ADC_CR_ADDIS_Msk                  (0x1UL << ADC_CR_ADDIS_Pos)          /*!< 0x00000002 */

+#define ADC_CR_ADDIS                      ADC_CR_ADDIS_Msk                     /*!< ADC Disable command */

+#define ADC_CR_ADSTART_Pos                (2U)

+#define ADC_CR_ADSTART_Msk                (0x1UL << ADC_CR_ADSTART_Pos)        /*!< 0x00000004 */

+#define ADC_CR_ADSTART                    ADC_CR_ADSTART_Msk                   /*!< ADC Start of Regular conversion */

+#define ADC_CR_JADSTART_Pos               (3U)

+#define ADC_CR_JADSTART_Msk               (0x1UL << ADC_CR_JADSTART_Pos)       /*!< 0x00000008 */

+#define ADC_CR_JADSTART                   ADC_CR_JADSTART_Msk                  /*!< ADC Start of injected conversion */

+#define ADC_CR_ADSTP_Pos                  (4U)

+#define ADC_CR_ADSTP_Msk                  (0x1UL << ADC_CR_ADSTP_Pos)          /*!< 0x00000010 */

+#define ADC_CR_ADSTP                      ADC_CR_ADSTP_Msk                     /*!< ADC Stop of Regular conversion */

+#define ADC_CR_JADSTP_Pos                 (5U)

+#define ADC_CR_JADSTP_Msk                 (0x1UL << ADC_CR_JADSTP_Pos)         /*!< 0x00000020 */

+#define ADC_CR_JADSTP                     ADC_CR_JADSTP_Msk                    /*!< ADC Stop of injected conversion */

+#define ADC_CR_BOOST_Pos                  (8U)

+#define ADC_CR_BOOST_Msk                  (0x3UL << ADC_CR_BOOST_Pos)          /*!< 0x00000300 */

+#define ADC_CR_BOOST                      ADC_CR_BOOST_Msk                     /*!< ADC Boost Mode configuration */

+#define ADC_CR_BOOST_0                    (0x1UL << ADC_CR_BOOST_Pos)           /*!< 0x00000100 */

+#define ADC_CR_BOOST_1                    (0x2UL << ADC_CR_BOOST_Pos)           /*!< 0x00000200 */

+#define ADC_CR_ADCALLIN_Pos               (16U)

+#define ADC_CR_ADCALLIN_Msk               (0x1UL << ADC_CR_ADCALLIN_Pos)       /*!< 0x00010000 */

+#define ADC_CR_ADCALLIN                   ADC_CR_ADCALLIN_Msk                  /*!< ADC Linearity calibration */

+#define ADC_CR_LINCALRDYW1_Pos            (22U)

+#define ADC_CR_LINCALRDYW1_Msk            (0x1UL << ADC_CR_LINCALRDYW1_Pos)    /*!< 0x00400000 */

+#define ADC_CR_LINCALRDYW1                ADC_CR_LINCALRDYW1_Msk               /*!< ADC Linearity calibration ready Word 1 */

+#define ADC_CR_LINCALRDYW2_Pos            (23U)

+#define ADC_CR_LINCALRDYW2_Msk            (0x1UL << ADC_CR_LINCALRDYW2_Pos)    /*!< 0x00800000 */

+#define ADC_CR_LINCALRDYW2                ADC_CR_LINCALRDYW2_Msk               /*!< ADC Linearity calibration ready Word 2 */

+#define ADC_CR_LINCALRDYW3_Pos            (24U)

+#define ADC_CR_LINCALRDYW3_Msk            (0x1UL << ADC_CR_LINCALRDYW3_Pos)    /*!< 0x01000000 */

+#define ADC_CR_LINCALRDYW3                ADC_CR_LINCALRDYW3_Msk               /*!< ADC Linearity calibration ready Word 3 */

+#define ADC_CR_LINCALRDYW4_Pos            (25U)

+#define ADC_CR_LINCALRDYW4_Msk            (0x1UL << ADC_CR_LINCALRDYW4_Pos)    /*!< 0x02000000 */

+#define ADC_CR_LINCALRDYW4                ADC_CR_LINCALRDYW4_Msk               /*!< ADC Linearity calibration ready Word 4 */

+#define ADC_CR_LINCALRDYW5_Pos            (26U)

+#define ADC_CR_LINCALRDYW5_Msk            (0x1UL << ADC_CR_LINCALRDYW5_Pos)    /*!< 0x04000000 */

+#define ADC_CR_LINCALRDYW5                ADC_CR_LINCALRDYW5_Msk               /*!< ADC Linearity calibration ready Word 5 */

+#define ADC_CR_LINCALRDYW6_Pos            (27U)

+#define ADC_CR_LINCALRDYW6_Msk            (0x1UL << ADC_CR_LINCALRDYW6_Pos)    /*!< 0x08000000 */

+#define ADC_CR_LINCALRDYW6                ADC_CR_LINCALRDYW6_Msk               /*!< ADC Linearity calibration ready Word 6 */

+#define ADC_CR_ADVREGEN_Pos               (28U)

+#define ADC_CR_ADVREGEN_Msk               (0x1UL << ADC_CR_ADVREGEN_Pos)       /*!< 0x10000000 */

+#define ADC_CR_ADVREGEN                   ADC_CR_ADVREGEN_Msk                  /*!< ADC Voltage regulator Enable */

+#define ADC_CR_DEEPPWD_Pos                (29U)

+#define ADC_CR_DEEPPWD_Msk                (0x1UL << ADC_CR_DEEPPWD_Pos)        /*!< 0x20000000 */

+#define ADC_CR_DEEPPWD                    ADC_CR_DEEPPWD_Msk                   /*!< ADC Deep power down Enable */

+#define ADC_CR_ADCALDIF_Pos               (30U)

+#define ADC_CR_ADCALDIF_Msk               (0x1UL << ADC_CR_ADCALDIF_Pos)       /*!< 0x40000000 */

+#define ADC_CR_ADCALDIF                   ADC_CR_ADCALDIF_Msk                  /*!< ADC Differential Mode for calibration */

+#define ADC_CR_ADCAL_Pos                  (31U)

+#define ADC_CR_ADCAL_Msk                  (0x1UL << ADC_CR_ADCAL_Pos)          /*!< 0x80000000 */

+#define ADC_CR_ADCAL                      ADC_CR_ADCAL_Msk                     /*!< ADC Calibration */

+

+/********************  Bit definition for ADC_CFGR register  ********************/

+#define ADC_CFGR_DMNGT_Pos                (0U)

+#define ADC_CFGR_DMNGT_Msk                (0x3UL << ADC_CFGR_DMNGT_Pos)        /*!< 0x00000003 */

+#define ADC_CFGR_DMNGT                    ADC_CFGR_DMNGT_Msk                   /*!< ADC Data Management configuration */

+#define ADC_CFGR_DMNGT_0                  (0x1UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000001 */

+#define ADC_CFGR_DMNGT_1                  (0x2UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000002 */

+

+#define ADC_CFGR_RES_Pos                  (2U)

+#define ADC_CFGR_RES_Msk                  (0x7UL << ADC_CFGR_RES_Pos)          /*!< 0x0000001C */

+#define ADC_CFGR_RES                      ADC_CFGR_RES_Msk                     /*!< ADC Data resolution */

+#define ADC_CFGR_RES_0                    (0x1UL << ADC_CFGR_RES_Pos)           /*!< 0x00000004 */

+#define ADC_CFGR_RES_1                    (0x2UL << ADC_CFGR_RES_Pos)           /*!< 0x00000008 */

+#define ADC_CFGR_RES_2                    (0x4UL << ADC_CFGR_RES_Pos)           /*!< 0x00000010 */

+

+#define ADC_CFGR_EXTSEL_Pos               (5U)

+#define ADC_CFGR_EXTSEL_Msk               (0x1FUL << ADC_CFGR_EXTSEL_Pos)      /*!< 0x000003E0 */

+#define ADC_CFGR_EXTSEL                   ADC_CFGR_EXTSEL_Msk                  /*!< ADC External trigger selection for regular group */

+#define ADC_CFGR_EXTSEL_0                 (0x01UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000020 */

+#define ADC_CFGR_EXTSEL_1                 (0x02UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000040 */

+#define ADC_CFGR_EXTSEL_2                 (0x04UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000080 */

+#define ADC_CFGR_EXTSEL_3                 (0x08UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000100 */

+#define ADC_CFGR_EXTSEL_4                 (0x10UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000200 */

+

+#define ADC_CFGR_EXTEN_Pos                (10U)

+#define ADC_CFGR_EXTEN_Msk                (0x3UL << ADC_CFGR_EXTEN_Pos)        /*!< 0x00000C00 */

+#define ADC_CFGR_EXTEN                    ADC_CFGR_EXTEN_Msk                   /*!< ADC External trigger enable and polarity selection for regular channels */

+#define ADC_CFGR_EXTEN_0                  (0x1UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000400 */

+#define ADC_CFGR_EXTEN_1                  (0x2UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000800 */

+

+#define ADC_CFGR_OVRMOD_Pos               (12U)

+#define ADC_CFGR_OVRMOD_Msk               (0x1UL << ADC_CFGR_OVRMOD_Pos)       /*!< 0x00001000 */

+#define ADC_CFGR_OVRMOD                   ADC_CFGR_OVRMOD_Msk                  /*!< ADC overrun mode */

+#define ADC_CFGR_CONT_Pos                 (13U)

+#define ADC_CFGR_CONT_Msk                 (0x1UL << ADC_CFGR_CONT_Pos)         /*!< 0x00002000 */

+#define ADC_CFGR_CONT                     ADC_CFGR_CONT_Msk                    /*!< ADC Single/continuous conversion mode for regular conversion */

+#define ADC_CFGR_AUTDLY_Pos               (14U)

+#define ADC_CFGR_AUTDLY_Msk               (0x1UL << ADC_CFGR_AUTDLY_Pos)       /*!< 0x00004000 */

+#define ADC_CFGR_AUTDLY                   ADC_CFGR_AUTDLY_Msk                  /*!< ADC Delayed conversion mode */

+

+#define ADC_CFGR_DISCEN_Pos               (16U)

+#define ADC_CFGR_DISCEN_Msk               (0x1UL << ADC_CFGR_DISCEN_Pos)       /*!< 0x00010000 */

+#define ADC_CFGR_DISCEN                   ADC_CFGR_DISCEN_Msk                  /*!< ADC Discontinuous mode for regular channels */

+

+#define ADC_CFGR_DISCNUM_Pos              (17U)

+#define ADC_CFGR_DISCNUM_Msk              (0x7UL << ADC_CFGR_DISCNUM_Pos)      /*!< 0x000E0000 */

+#define ADC_CFGR_DISCNUM                  ADC_CFGR_DISCNUM_Msk                 /*!< ADC Discontinuous mode channel count */

+#define ADC_CFGR_DISCNUM_0                (0x1UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00020000 */

+#define ADC_CFGR_DISCNUM_1                (0x2UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00040000 */

+#define ADC_CFGR_DISCNUM_2                (0x4UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00080000 */

+

+#define ADC_CFGR_JDISCEN_Pos              (20U)

+#define ADC_CFGR_JDISCEN_Msk              (0x1UL << ADC_CFGR_JDISCEN_Pos)      /*!< 0x00100000 */

+#define ADC_CFGR_JDISCEN                  ADC_CFGR_JDISCEN_Msk                 /*!< ADC Discontinuous mode on injected channels */

+#define ADC_CFGR_JQM_Pos                  (21U)

+#define ADC_CFGR_JQM_Msk                  (0x1UL << ADC_CFGR_JQM_Pos)          /*!< 0x00200000 */

+#define ADC_CFGR_JQM                      ADC_CFGR_JQM_Msk                     /*!< ADC JSQR Queue mode */

+#define ADC_CFGR_AWD1SGL_Pos              (22U)

+#define ADC_CFGR_AWD1SGL_Msk              (0x1UL << ADC_CFGR_AWD1SGL_Pos)      /*!< 0x00400000 */

+#define ADC_CFGR_AWD1SGL                  ADC_CFGR_AWD1SGL_Msk                 /*!< Enable the watchdog 1 on a single channel or on all channels */

+#define ADC_CFGR_AWD1EN_Pos               (23U)

+#define ADC_CFGR_AWD1EN_Msk               (0x1UL << ADC_CFGR_AWD1EN_Pos)       /*!< 0x00800000 */

+#define ADC_CFGR_AWD1EN                   ADC_CFGR_AWD1EN_Msk                  /*!< ADC Analog watchdog 1 enable on regular Channels */

+#define ADC_CFGR_JAWD1EN_Pos              (24U)

+#define ADC_CFGR_JAWD1EN_Msk              (0x1UL << ADC_CFGR_JAWD1EN_Pos)      /*!< 0x01000000 */

+#define ADC_CFGR_JAWD1EN                  ADC_CFGR_JAWD1EN_Msk                 /*!< ADC Analog watchdog 1 enable on injected Channels */

+#define ADC_CFGR_JAUTO_Pos                (25U)

+#define ADC_CFGR_JAUTO_Msk                (0x1UL << ADC_CFGR_JAUTO_Pos)        /*!< 0x02000000 */

+#define ADC_CFGR_JAUTO                    ADC_CFGR_JAUTO_Msk                   /*!< ADC Automatic injected group conversion */

+

+#define ADC_CFGR_AWD1CH_Pos               (26U)

+#define ADC_CFGR_AWD1CH_Msk               (0x1FUL << ADC_CFGR_AWD1CH_Pos)      /*!< 0x7C000000 */

+#define ADC_CFGR_AWD1CH                   ADC_CFGR_AWD1CH_Msk                  /*!< ADC Analog watchdog 1 Channel selection */

+#define ADC_CFGR_AWD1CH_0                 (0x01UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x04000000 */

+#define ADC_CFGR_AWD1CH_1                 (0x02UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x08000000 */

+#define ADC_CFGR_AWD1CH_2                 (0x04UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x10000000 */

+#define ADC_CFGR_AWD1CH_3                 (0x08UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x20000000 */

+#define ADC_CFGR_AWD1CH_4                 (0x10UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x40000000 */

+

+#define ADC_CFGR_JQDIS_Pos                (31U)

+#define ADC_CFGR_JQDIS_Msk                (0x1UL << ADC_CFGR_JQDIS_Pos)        /*!< 0x80000000 */

+#define ADC_CFGR_JQDIS                    ADC_CFGR_JQDIS_Msk                   /*!< ADC Injected queue disable */

+

+/********************  Bit definition for ADC_CFGR2 register  ********************/

+#define ADC_CFGR2_ROVSE_Pos               (0U)

+#define ADC_CFGR2_ROVSE_Msk               (0x1UL << ADC_CFGR2_ROVSE_Pos)       /*!< 0x00000001 */

+#define ADC_CFGR2_ROVSE                   ADC_CFGR2_ROVSE_Msk                  /*!< ADC Regular group oversampler enable */

+#define ADC_CFGR2_JOVSE_Pos               (1U)

+#define ADC_CFGR2_JOVSE_Msk               (0x1UL << ADC_CFGR2_JOVSE_Pos)       /*!< 0x00000002 */

+#define ADC_CFGR2_JOVSE                   ADC_CFGR2_JOVSE_Msk                  /*!< ADC Injected group oversampler enable */

+

+#define ADC_CFGR2_OVSS_Pos                (5U)

+#define ADC_CFGR2_OVSS_Msk                (0xFUL << ADC_CFGR2_OVSS_Pos)        /*!< 0x000001E0 */

+#define ADC_CFGR2_OVSS                    ADC_CFGR2_OVSS_Msk                   /*!< ADC Regular Oversampling shift */

+#define ADC_CFGR2_OVSS_0                  (0x1UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000020 */

+#define ADC_CFGR2_OVSS_1                  (0x2UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000040 */

+#define ADC_CFGR2_OVSS_2                  (0x4UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000080 */

+#define ADC_CFGR2_OVSS_3                  (0x8UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000100 */

+

+#define ADC_CFGR2_TROVS_Pos               (9U)

+#define ADC_CFGR2_TROVS_Msk               (0x1UL << ADC_CFGR2_TROVS_Pos)       /*!< 0x00000200 */

+#define ADC_CFGR2_TROVS                   ADC_CFGR2_TROVS_Msk                  /*!< ADC Triggered regular Oversampling */

+#define ADC_CFGR2_ROVSM_Pos               (10U)

+#define ADC_CFGR2_ROVSM_Msk               (0x1UL << ADC_CFGR2_ROVSM_Pos)       /*!< 0x00000400 */

+#define ADC_CFGR2_ROVSM                   ADC_CFGR2_ROVSM_Msk                  /*!< ADC Regular oversampling mode */

+

+#define ADC_CFGR2_RSHIFT1_Pos             (11U)

+#define ADC_CFGR2_RSHIFT1_Msk             (0x1UL << ADC_CFGR2_RSHIFT1_Pos)     /*!< 0x00000800 */

+#define ADC_CFGR2_RSHIFT1                 ADC_CFGR2_RSHIFT1_Msk                /*!< ADC Right-shift data after Offset 1 correction */

+#define ADC_CFGR2_RSHIFT2_Pos             (12U)

+#define ADC_CFGR2_RSHIFT2_Msk             (0x1UL << ADC_CFGR2_RSHIFT2_Pos)     /*!< 0x00001000 */

+#define ADC_CFGR2_RSHIFT2                 ADC_CFGR2_RSHIFT2_Msk                /*!< ADC Right-shift data after Offset 2 correction */

+#define ADC_CFGR2_RSHIFT3_Pos             (13U)

+#define ADC_CFGR2_RSHIFT3_Msk             (0x1UL << ADC_CFGR2_RSHIFT3_Pos)     /*!< 0x00002000 */

+#define ADC_CFGR2_RSHIFT3                 ADC_CFGR2_RSHIFT3_Msk                /*!< ADC Right-shift data after Offset 3 correction */

+#define ADC_CFGR2_RSHIFT4_Pos             (14U)

+#define ADC_CFGR2_RSHIFT4_Msk             (0x1UL << ADC_CFGR2_RSHIFT4_Pos)     /*!< 0x00004000 */

+#define ADC_CFGR2_RSHIFT4                 ADC_CFGR2_RSHIFT4_Msk                /*!< ADC Right-shift data after Offset 4 correction */

+

+#define ADC_CFGR2_OVSR_Pos                (16U)

+#define ADC_CFGR2_OVSR_Msk                (0x3FFUL << ADC_CFGR2_OVSR_Pos)      /*!< 0x03FF0000 */

+#define ADC_CFGR2_OVSR                    ADC_CFGR2_OVSR_Msk                   /*!< ADC oversampling Ratio */

+#define ADC_CFGR2_OVSR_0                  (0x001UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00010000 */

+#define ADC_CFGR2_OVSR_1                  (0x002UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00020000 */

+#define ADC_CFGR2_OVSR_2                  (0x004UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00040000 */

+#define ADC_CFGR2_OVSR_3                  (0x008UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00080000 */

+#define ADC_CFGR2_OVSR_4                  (0x010UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00100000 */

+#define ADC_CFGR2_OVSR_5                  (0x020UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00200000 */

+#define ADC_CFGR2_OVSR_6                  (0x040UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00400000 */

+#define ADC_CFGR2_OVSR_7                  (0x080UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00800000 */

+#define ADC_CFGR2_OVSR_8                  (0x100UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x01000000 */

+#define ADC_CFGR2_OVSR_9                  (0x200UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x02000000 */

+

+#define ADC_CFGR2_LSHIFT_Pos              (28U)

+#define ADC_CFGR2_LSHIFT_Msk              (0xFUL << ADC_CFGR2_LSHIFT_Pos)      /*!< 0xF0000000 */

+#define ADC_CFGR2_LSHIFT                  ADC_CFGR2_LSHIFT_Msk                 /*!< ADC Left shift factor */

+#define ADC_CFGR2_LSHIFT_0                (0x1UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x10000000 */

+#define ADC_CFGR2_LSHIFT_1                (0x2UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x20000000 */

+#define ADC_CFGR2_LSHIFT_2                (0x4UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x40000000 */

+#define ADC_CFGR2_LSHIFT_3                (0x8UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_SMPR1 register  ********************/

+#define ADC_SMPR1_SMP0_Pos                (0U)

+#define ADC_SMPR1_SMP0_Msk                (0x7UL << ADC_SMPR1_SMP0_Pos)        /*!< 0x00000007 */

+#define ADC_SMPR1_SMP0                    ADC_SMPR1_SMP0_Msk                   /*!< ADC Channel 0 Sampling time selection  */

+#define ADC_SMPR1_SMP0_0                  (0x1UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000001 */

+#define ADC_SMPR1_SMP0_1                  (0x2UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000002 */

+#define ADC_SMPR1_SMP0_2                  (0x4UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000004 */

+

+#define ADC_SMPR1_SMP1_Pos                (3U)

+#define ADC_SMPR1_SMP1_Msk                (0x7UL << ADC_SMPR1_SMP1_Pos)        /*!< 0x00000038 */

+#define ADC_SMPR1_SMP1                    ADC_SMPR1_SMP1_Msk                   /*!< ADC Channel 1 Sampling time selection  */

+#define ADC_SMPR1_SMP1_0                  (0x1UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000008 */

+#define ADC_SMPR1_SMP1_1                  (0x2UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000010 */

+#define ADC_SMPR1_SMP1_2                  (0x4UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000020 */

+

+#define ADC_SMPR1_SMP2_Pos                (6U)

+#define ADC_SMPR1_SMP2_Msk                (0x7UL << ADC_SMPR1_SMP2_Pos)        /*!< 0x000001C0 */

+#define ADC_SMPR1_SMP2                    ADC_SMPR1_SMP2_Msk                   /*!< ADC Channel 2 Sampling time selection  */

+#define ADC_SMPR1_SMP2_0                  (0x1UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000040 */

+#define ADC_SMPR1_SMP2_1                  (0x2UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000080 */

+#define ADC_SMPR1_SMP2_2                  (0x4UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000100 */

+

+#define ADC_SMPR1_SMP3_Pos                (9U)

+#define ADC_SMPR1_SMP3_Msk                (0x7UL << ADC_SMPR1_SMP3_Pos)        /*!< 0x00000E00 */

+#define ADC_SMPR1_SMP3                    ADC_SMPR1_SMP3_Msk                   /*!< ADC Channel 3 Sampling time selection  */

+#define ADC_SMPR1_SMP3_0                  (0x1UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000200 */

+#define ADC_SMPR1_SMP3_1                  (0x2UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000400 */

+#define ADC_SMPR1_SMP3_2                  (0x4UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000800 */

+

+#define ADC_SMPR1_SMP4_Pos                (12U)

+#define ADC_SMPR1_SMP4_Msk                (0x7UL << ADC_SMPR1_SMP4_Pos)        /*!< 0x00007000 */

+#define ADC_SMPR1_SMP4                    ADC_SMPR1_SMP4_Msk                   /*!< ADC Channel 4 Sampling time selection  */

+#define ADC_SMPR1_SMP4_0                  (0x1UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00001000 */

+#define ADC_SMPR1_SMP4_1                  (0x2UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00002000 */

+#define ADC_SMPR1_SMP4_2                  (0x4UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00004000 */

+

+#define ADC_SMPR1_SMP5_Pos                (15U)

+#define ADC_SMPR1_SMP5_Msk                (0x7UL << ADC_SMPR1_SMP5_Pos)        /*!< 0x00038000 */

+#define ADC_SMPR1_SMP5                    ADC_SMPR1_SMP5_Msk                   /*!< ADC Channel 5 Sampling time selection  */

+#define ADC_SMPR1_SMP5_0                  (0x1UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00008000 */

+#define ADC_SMPR1_SMP5_1                  (0x2UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00010000 */

+#define ADC_SMPR1_SMP5_2                  (0x4UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00020000 */

+

+#define ADC_SMPR1_SMP6_Pos                (18U)

+#define ADC_SMPR1_SMP6_Msk                (0x7UL << ADC_SMPR1_SMP6_Pos)        /*!< 0x001C0000 */

+#define ADC_SMPR1_SMP6                    ADC_SMPR1_SMP6_Msk                   /*!< ADC Channel 6 Sampling time selection  */

+#define ADC_SMPR1_SMP6_0                  (0x1UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00040000 */

+#define ADC_SMPR1_SMP6_1                  (0x2UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00080000 */

+#define ADC_SMPR1_SMP6_2                  (0x4UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00100000 */

+

+#define ADC_SMPR1_SMP7_Pos                (21U)

+#define ADC_SMPR1_SMP7_Msk                (0x7UL << ADC_SMPR1_SMP7_Pos)        /*!< 0x00E00000 */

+#define ADC_SMPR1_SMP7                    ADC_SMPR1_SMP7_Msk                   /*!< ADC Channel 7 Sampling time selection  */

+#define ADC_SMPR1_SMP7_0                  (0x1UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00200000 */

+#define ADC_SMPR1_SMP7_1                  (0x2UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00400000 */

+#define ADC_SMPR1_SMP7_2                  (0x4UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00800000 */

+

+#define ADC_SMPR1_SMP8_Pos                (24U)

+#define ADC_SMPR1_SMP8_Msk                (0x7UL << ADC_SMPR1_SMP8_Pos)        /*!< 0x07000000 */

+#define ADC_SMPR1_SMP8                    ADC_SMPR1_SMP8_Msk                   /*!< ADC Channel 8 Sampling time selection  */

+#define ADC_SMPR1_SMP8_0                  (0x1UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x01000000 */

+#define ADC_SMPR1_SMP8_1                  (0x2UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x02000000 */

+#define ADC_SMPR1_SMP8_2                  (0x4UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x04000000 */

+

+#define ADC_SMPR1_SMP9_Pos                (27U)

+#define ADC_SMPR1_SMP9_Msk                (0x7UL << ADC_SMPR1_SMP9_Pos)        /*!< 0x38000000 */

+#define ADC_SMPR1_SMP9                    ADC_SMPR1_SMP9_Msk                   /*!< ADC Channel 9 Sampling time selection  */

+#define ADC_SMPR1_SMP9_0                  (0x1UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x08000000 */

+#define ADC_SMPR1_SMP9_1                  (0x2UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x10000000 */

+#define ADC_SMPR1_SMP9_2                  (0x4UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x20000000 */

+

+/********************  Bit definition for ADC_SMPR2 register  ********************/

+#define ADC_SMPR2_SMP10_Pos               (0U)

+#define ADC_SMPR2_SMP10_Msk               (0x7UL << ADC_SMPR2_SMP10_Pos)       /*!< 0x00000007 */

+#define ADC_SMPR2_SMP10                   ADC_SMPR2_SMP10_Msk                  /*!< ADC Channel 10 Sampling time selection  */

+#define ADC_SMPR2_SMP10_0                 (0x1UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000001 */

+#define ADC_SMPR2_SMP10_1                 (0x2UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000002 */

+#define ADC_SMPR2_SMP10_2                 (0x4UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000004 */

+

+#define ADC_SMPR2_SMP11_Pos               (3U)

+#define ADC_SMPR2_SMP11_Msk               (0x7UL << ADC_SMPR2_SMP11_Pos)       /*!< 0x00000038 */

+#define ADC_SMPR2_SMP11                   ADC_SMPR2_SMP11_Msk                  /*!< ADC Channel 11 Sampling time selection  */

+#define ADC_SMPR2_SMP11_0                 (0x1UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000008 */

+#define ADC_SMPR2_SMP11_1                 (0x2UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000010 */

+#define ADC_SMPR2_SMP11_2                 (0x4UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000020 */

+

+#define ADC_SMPR2_SMP12_Pos               (6U)

+#define ADC_SMPR2_SMP12_Msk               (0x7UL << ADC_SMPR2_SMP12_Pos)       /*!< 0x000001C0 */

+#define ADC_SMPR2_SMP12                   ADC_SMPR2_SMP12_Msk                  /*!< ADC Channel 12 Sampling time selection  */

+#define ADC_SMPR2_SMP12_0                 (0x1UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000040 */

+#define ADC_SMPR2_SMP12_1                 (0x2UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000080 */

+#define ADC_SMPR2_SMP12_2                 (0x4UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000100 */

+

+#define ADC_SMPR2_SMP13_Pos               (9U)

+#define ADC_SMPR2_SMP13_Msk               (0x7UL << ADC_SMPR2_SMP13_Pos)       /*!< 0x00000E00 */

+#define ADC_SMPR2_SMP13                   ADC_SMPR2_SMP13_Msk                  /*!< ADC Channel 13 Sampling time selection  */

+#define ADC_SMPR2_SMP13_0                 (0x1UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000200 */

+#define ADC_SMPR2_SMP13_1                 (0x2UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000400 */

+#define ADC_SMPR2_SMP13_2                 (0x4UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000800 */

+

+#define ADC_SMPR2_SMP14_Pos               (12U)

+#define ADC_SMPR2_SMP14_Msk               (0x7UL << ADC_SMPR2_SMP14_Pos)       /*!< 0x00007000 */

+#define ADC_SMPR2_SMP14                   ADC_SMPR2_SMP14_Msk                  /*!< ADC Channel 14 Sampling time selection  */

+#define ADC_SMPR2_SMP14_0                 (0x1UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00001000 */

+#define ADC_SMPR2_SMP14_1                 (0x2UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00002000 */

+#define ADC_SMPR2_SMP14_2                 (0x4UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00004000 */

+

+#define ADC_SMPR2_SMP15_Pos               (15U)

+#define ADC_SMPR2_SMP15_Msk               (0x7UL << ADC_SMPR2_SMP15_Pos)       /*!< 0x00038000 */

+#define ADC_SMPR2_SMP15                   ADC_SMPR2_SMP15_Msk                  /*!< ADC Channel 15 Sampling time selection  */

+#define ADC_SMPR2_SMP15_0                 (0x1UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00008000 */

+#define ADC_SMPR2_SMP15_1                 (0x2UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00010000 */

+#define ADC_SMPR2_SMP15_2                 (0x4UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00020000 */

+

+#define ADC_SMPR2_SMP16_Pos               (18U)

+#define ADC_SMPR2_SMP16_Msk               (0x7UL << ADC_SMPR2_SMP16_Pos)       /*!< 0x001C0000 */

+#define ADC_SMPR2_SMP16                   ADC_SMPR2_SMP16_Msk                  /*!< ADC Channel 16 Sampling time selection  */

+#define ADC_SMPR2_SMP16_0                 (0x1UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00040000 */

+#define ADC_SMPR2_SMP16_1                 (0x2UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00080000 */

+#define ADC_SMPR2_SMP16_2                 (0x4UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00100000 */

+

+#define ADC_SMPR2_SMP17_Pos               (21U)

+#define ADC_SMPR2_SMP17_Msk               (0x7UL << ADC_SMPR2_SMP17_Pos)       /*!< 0x00E00000 */

+#define ADC_SMPR2_SMP17                   ADC_SMPR2_SMP17_Msk                  /*!< ADC Channel 17 Sampling time selection  */

+#define ADC_SMPR2_SMP17_0                 (0x1UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00200000 */

+#define ADC_SMPR2_SMP17_1                 (0x2UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00400000 */

+#define ADC_SMPR2_SMP17_2                 (0x4UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00800000 */

+

+#define ADC_SMPR2_SMP18_Pos               (24U)

+#define ADC_SMPR2_SMP18_Msk               (0x7UL << ADC_SMPR2_SMP18_Pos)       /*!< 0x07000000 */

+#define ADC_SMPR2_SMP18                   ADC_SMPR2_SMP18_Msk                  /*!< ADC Channel 18 Sampling time selection  */

+#define ADC_SMPR2_SMP18_0                 (0x1UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x01000000 */

+#define ADC_SMPR2_SMP18_1                 (0x2UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x02000000 */

+#define ADC_SMPR2_SMP18_2                 (0x4UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x04000000 */

+

+#define ADC_SMPR2_SMP19_Pos               (27U)

+#define ADC_SMPR2_SMP19_Msk               (0x7UL << ADC_SMPR2_SMP19_Pos)       /*!< 0x38000000 */

+#define ADC_SMPR2_SMP19                   ADC_SMPR2_SMP19_Msk                  /*!< ADC Channel 19 Sampling time selection  */

+#define ADC_SMPR2_SMP19_0                 (0x1UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x08000000 */

+#define ADC_SMPR2_SMP19_1                 (0x2UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x10000000 */

+#define ADC_SMPR2_SMP19_2                 (0x4UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x20000000 */

+

+/********************  Bit definition for ADC_PCSEL register  ********************/

+#define ADC_PCSEL_PCSEL_Pos               (0U)

+#define ADC_PCSEL_PCSEL_Msk               (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)   /*!< 0x000FFFFF */

+#define ADC_PCSEL_PCSEL                   ADC_PCSEL_PCSEL_Msk                  /*!< ADC pre channel selection */

+#define ADC_PCSEL_PCSEL_0                 (0x00001UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */

+#define ADC_PCSEL_PCSEL_1                 (0x00002UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */

+#define ADC_PCSEL_PCSEL_2                 (0x00004UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */

+#define ADC_PCSEL_PCSEL_3                 (0x00008UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */

+#define ADC_PCSEL_PCSEL_4                 (0x00010UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */

+#define ADC_PCSEL_PCSEL_5                 (0x00020UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */

+#define ADC_PCSEL_PCSEL_6                 (0x00040UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */

+#define ADC_PCSEL_PCSEL_7                 (0x00080UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */

+#define ADC_PCSEL_PCSEL_8                 (0x00100UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */

+#define ADC_PCSEL_PCSEL_9                 (0x00200UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */

+#define ADC_PCSEL_PCSEL_10                (0x00400UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */

+#define ADC_PCSEL_PCSEL_11                (0x00800UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */

+#define ADC_PCSEL_PCSEL_12                (0x01000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */

+#define ADC_PCSEL_PCSEL_13                (0x02000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */

+#define ADC_PCSEL_PCSEL_14                (0x04000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */

+#define ADC_PCSEL_PCSEL_15                (0x08000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */

+#define ADC_PCSEL_PCSEL_16                (0x10000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */

+#define ADC_PCSEL_PCSEL_17                (0x20000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */

+#define ADC_PCSEL_PCSEL_18                (0x40000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */

+#define ADC_PCSEL_PCSEL_19                (0x80000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00080000 */

+

+/*****************  Bit definition for ADC_LTR1, 2, 3 registers *****************/

+#define ADC_LTR_LT_Pos                    (0U)

+#define ADC_LTR_LT_Msk                    (0x3FFFFFFUL << ADC_LTR_LT_Pos)      /*!< 0x03FFFFFF */

+#define ADC_LTR_LT                        ADC_LTR_LT_Msk                       /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */

+

+/*****************  Bit definition for ADC_HTR1, 2, 3 registers  ****************/

+#define ADC_HTR_HT_Pos                    (0U)

+#define ADC_HTR_HT_Msk                    (0x3FFFFFFUL << ADC_HTR_HT_Pos)      /*!< 0x03FFFFFF */

+#define ADC_HTR_HT                        ADC_HTR_HT_Msk                       /*!< ADC Analog watchdog 1,2 and 3 higher threshold */

+

+

+/********************  Bit definition for ADC_SQR1 register  ********************/

+#define ADC_SQR1_L_Pos                    (0U)

+#define ADC_SQR1_L_Msk                    (0xFUL << ADC_SQR1_L_Pos)            /*!< 0x0000000F */

+#define ADC_SQR1_L                        ADC_SQR1_L_Msk                       /*!< ADC regular channel sequence lenght */

+#define ADC_SQR1_L_0                      (0x1UL << ADC_SQR1_L_Pos)             /*!< 0x00000001 */

+#define ADC_SQR1_L_1                      (0x2UL << ADC_SQR1_L_Pos)             /*!< 0x00000002 */

+#define ADC_SQR1_L_2                      (0x4UL << ADC_SQR1_L_Pos)             /*!< 0x00000004 */

+#define ADC_SQR1_L_3                      (0x8UL << ADC_SQR1_L_Pos)             /*!< 0x00000008 */

+

+#define ADC_SQR1_SQ1_Pos                  (6U)

+#define ADC_SQR1_SQ1_Msk                  (0x1FUL << ADC_SQR1_SQ1_Pos)         /*!< 0x000007C0 */

+#define ADC_SQR1_SQ1                      ADC_SQR1_SQ1_Msk                     /*!< ADC 1st conversion in regular sequence */

+#define ADC_SQR1_SQ1_0                    (0x01UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000040 */

+#define ADC_SQR1_SQ1_1                    (0x02UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000080 */

+#define ADC_SQR1_SQ1_2                    (0x04UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000100 */

+#define ADC_SQR1_SQ1_3                    (0x08UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000200 */

+#define ADC_SQR1_SQ1_4                    (0x10UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000400 */

+

+#define ADC_SQR1_SQ2_Pos                  (12U)

+#define ADC_SQR1_SQ2_Msk                  (0x1FUL << ADC_SQR1_SQ2_Pos)         /*!< 0x0001F000 */

+#define ADC_SQR1_SQ2                      ADC_SQR1_SQ2_Msk                     /*!< ADC 2nd conversion in regular sequence */

+#define ADC_SQR1_SQ2_0                    (0x01UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00001000 */

+#define ADC_SQR1_SQ2_1                    (0x02UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00002000 */

+#define ADC_SQR1_SQ2_2                    (0x04UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00004000 */

+#define ADC_SQR1_SQ2_3                    (0x08UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00008000 */

+#define ADC_SQR1_SQ2_4                    (0x10UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00010000 */

+

+#define ADC_SQR1_SQ3_Pos                  (18U)

+#define ADC_SQR1_SQ3_Msk                  (0x1FUL << ADC_SQR1_SQ3_Pos)         /*!< 0x007C0000 */

+#define ADC_SQR1_SQ3                      ADC_SQR1_SQ3_Msk                     /*!< ADC 3rd conversion in regular sequence */

+#define ADC_SQR1_SQ3_0                    (0x01UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00040000 */

+#define ADC_SQR1_SQ3_1                    (0x02UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00080000 */

+#define ADC_SQR1_SQ3_2                    (0x04UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00100000 */

+#define ADC_SQR1_SQ3_3                    (0x08UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00200000 */

+#define ADC_SQR1_SQ3_4                    (0x10UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00400000 */

+

+#define ADC_SQR1_SQ4_Pos                  (24U)

+#define ADC_SQR1_SQ4_Msk                  (0x1FUL << ADC_SQR1_SQ4_Pos)         /*!< 0x1F000000 */

+#define ADC_SQR1_SQ4                      ADC_SQR1_SQ4_Msk                     /*!< ADC 4th conversion in regular sequence */

+#define ADC_SQR1_SQ4_0                    (0x01UL << ADC_SQR1_SQ4_Pos)          /*!< 0x01000000 */

+#define ADC_SQR1_SQ4_1                    (0x02UL << ADC_SQR1_SQ4_Pos)          /*!< 0x02000000 */

+#define ADC_SQR1_SQ4_2                    (0x04UL << ADC_SQR1_SQ4_Pos)          /*!< 0x04000000 */

+#define ADC_SQR1_SQ4_3                    (0x08UL << ADC_SQR1_SQ4_Pos)          /*!< 0x08000000 */

+#define ADC_SQR1_SQ4_4                    (0x10UL << ADC_SQR1_SQ4_Pos)          /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR2 register  ********************/

+#define ADC_SQR2_SQ5_Pos                  (0U)

+#define ADC_SQR2_SQ5_Msk                  (0x1FUL << ADC_SQR2_SQ5_Pos)         /*!< 0x0000001F */

+#define ADC_SQR2_SQ5                      ADC_SQR2_SQ5_Msk                     /*!< ADC 5th conversion in regular sequence */

+#define ADC_SQR2_SQ5_0                    (0x01UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000001 */

+#define ADC_SQR2_SQ5_1                    (0x02UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000002 */

+#define ADC_SQR2_SQ5_2                    (0x04UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000004 */

+#define ADC_SQR2_SQ5_3                    (0x08UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000008 */

+#define ADC_SQR2_SQ5_4                    (0x10UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000010 */

+

+#define ADC_SQR2_SQ6_Pos                  (6U)

+#define ADC_SQR2_SQ6_Msk                  (0x1FUL << ADC_SQR2_SQ6_Pos)         /*!< 0x000007C0 */

+#define ADC_SQR2_SQ6                      ADC_SQR2_SQ6_Msk                     /*!< ADC 6th conversion in regular sequence */

+#define ADC_SQR2_SQ6_0                    (0x01UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000040 */

+#define ADC_SQR2_SQ6_1                    (0x02UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000080 */

+#define ADC_SQR2_SQ6_2                    (0x04UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000100 */

+#define ADC_SQR2_SQ6_3                    (0x08UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000200 */

+#define ADC_SQR2_SQ6_4                    (0x10UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000400 */

+

+#define ADC_SQR2_SQ7_Pos                  (12U)

+#define ADC_SQR2_SQ7_Msk                  (0x1FUL << ADC_SQR2_SQ7_Pos)         /*!< 0x0001F000 */

+#define ADC_SQR2_SQ7                      ADC_SQR2_SQ7_Msk                     /*!< ADC 7th conversion in regular sequence */

+#define ADC_SQR2_SQ7_0                    (0x01UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00001000 */

+#define ADC_SQR2_SQ7_1                    (0x02UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00002000 */

+#define ADC_SQR2_SQ7_2                    (0x04UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00004000 */

+#define ADC_SQR2_SQ7_3                    (0x08UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00008000 */

+#define ADC_SQR2_SQ7_4                    (0x10UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00010000 */

+

+#define ADC_SQR2_SQ8_Pos                  (18U)

+#define ADC_SQR2_SQ8_Msk                  (0x1FUL << ADC_SQR2_SQ8_Pos)         /*!< 0x007C0000 */

+#define ADC_SQR2_SQ8                      ADC_SQR2_SQ8_Msk                     /*!< ADC 8th conversion in regular sequence */

+#define ADC_SQR2_SQ8_0                    (0x01UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00040000 */

+#define ADC_SQR2_SQ8_1                    (0x02UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00080000 */

+#define ADC_SQR2_SQ8_2                    (0x04UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00100000 */

+#define ADC_SQR2_SQ8_3                    (0x08UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00200000 */

+#define ADC_SQR2_SQ8_4                    (0x10UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00400000 */

+

+#define ADC_SQR2_SQ9_Pos                  (24U)

+#define ADC_SQR2_SQ9_Msk                  (0x1FUL << ADC_SQR2_SQ9_Pos)         /*!< 0x1F000000 */

+#define ADC_SQR2_SQ9                      ADC_SQR2_SQ9_Msk                     /*!< ADC 9th conversion in regular sequence */

+#define ADC_SQR2_SQ9_0                    (0x01UL << ADC_SQR2_SQ9_Pos)          /*!< 0x01000000 */

+#define ADC_SQR2_SQ9_1                    (0x02UL << ADC_SQR2_SQ9_Pos)          /*!< 0x02000000 */

+#define ADC_SQR2_SQ9_2                    (0x04UL << ADC_SQR2_SQ9_Pos)          /*!< 0x04000000 */

+#define ADC_SQR2_SQ9_3                    (0x08UL << ADC_SQR2_SQ9_Pos)          /*!< 0x08000000 */

+#define ADC_SQR2_SQ9_4                    (0x10UL << ADC_SQR2_SQ9_Pos)          /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR3 register  ********************/

+#define ADC_SQR3_SQ10_Pos                 (0U)

+#define ADC_SQR3_SQ10_Msk                 (0x1FUL << ADC_SQR3_SQ10_Pos)        /*!< 0x0000001F */

+#define ADC_SQR3_SQ10                     ADC_SQR3_SQ10_Msk                    /*!< ADC 10th conversion in regular sequence */

+#define ADC_SQR3_SQ10_0                   (0x01UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000001 */

+#define ADC_SQR3_SQ10_1                   (0x02UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000002 */

+#define ADC_SQR3_SQ10_2                   (0x04UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000004 */

+#define ADC_SQR3_SQ10_3                   (0x08UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000008 */

+#define ADC_SQR3_SQ10_4                   (0x10UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000010 */

+

+#define ADC_SQR3_SQ11_Pos                 (6U)

+#define ADC_SQR3_SQ11_Msk                 (0x1FUL << ADC_SQR3_SQ11_Pos)        /*!< 0x000007C0 */

+#define ADC_SQR3_SQ11                     ADC_SQR3_SQ11_Msk                    /*!< ADC 11th conversion in regular sequence */

+#define ADC_SQR3_SQ11_0                   (0x01UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000040 */

+#define ADC_SQR3_SQ11_1                   (0x02UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000080 */

+#define ADC_SQR3_SQ11_2                   (0x04UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000100 */

+#define ADC_SQR3_SQ11_3                   (0x08UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000200 */

+#define ADC_SQR3_SQ11_4                   (0x10UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000400 */

+

+#define ADC_SQR3_SQ12_Pos                 (12U)

+#define ADC_SQR3_SQ12_Msk                 (0x1FUL << ADC_SQR3_SQ12_Pos)        /*!< 0x0001F000 */

+#define ADC_SQR3_SQ12                     ADC_SQR3_SQ12_Msk                    /*!< ADC 12th conversion in regular sequence */

+#define ADC_SQR3_SQ12_0                   (0x01UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00001000 */

+#define ADC_SQR3_SQ12_1                   (0x02UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00002000 */

+#define ADC_SQR3_SQ12_2                   (0x04UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00004000 */

+#define ADC_SQR3_SQ12_3                   (0x08UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00008000 */

+#define ADC_SQR3_SQ12_4                   (0x10UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00010000 */

+

+#define ADC_SQR3_SQ13_Pos                 (18U)

+#define ADC_SQR3_SQ13_Msk                 (0x1FUL << ADC_SQR3_SQ13_Pos)        /*!< 0x007C0000 */

+#define ADC_SQR3_SQ13                     ADC_SQR3_SQ13_Msk                    /*!< ADC 13th conversion in regular sequence */

+#define ADC_SQR3_SQ13_0                   (0x01UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00040000 */

+#define ADC_SQR3_SQ13_1                   (0x02UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00080000 */

+#define ADC_SQR3_SQ13_2                   (0x04UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00100000 */

+#define ADC_SQR3_SQ13_3                   (0x08UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00200000 */

+#define ADC_SQR3_SQ13_4                   (0x10UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00400000 */

+

+#define ADC_SQR3_SQ14_Pos                 (24U)

+#define ADC_SQR3_SQ14_Msk                 (0x1FUL << ADC_SQR3_SQ14_Pos)        /*!< 0x1F000000 */

+#define ADC_SQR3_SQ14                     ADC_SQR3_SQ14_Msk                    /*!< ADC 14th conversion in regular sequence */

+#define ADC_SQR3_SQ14_0                   (0x01UL << ADC_SQR3_SQ14_Pos)         /*!< 0x01000000 */

+#define ADC_SQR3_SQ14_1                   (0x02UL << ADC_SQR3_SQ14_Pos)         /*!< 0x02000000 */

+#define ADC_SQR3_SQ14_2                   (0x04UL << ADC_SQR3_SQ14_Pos)         /*!< 0x04000000 */

+#define ADC_SQR3_SQ14_3                   (0x08UL << ADC_SQR3_SQ14_Pos)         /*!< 0x08000000 */

+#define ADC_SQR3_SQ14_4                   (0x10UL << ADC_SQR3_SQ14_Pos)         /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR4 register  ********************/

+#define ADC_SQR4_SQ15_Pos                 (0U)

+#define ADC_SQR4_SQ15_Msk                 (0x1FUL << ADC_SQR4_SQ15_Pos)        /*!< 0x0000001F */

+#define ADC_SQR4_SQ15                     ADC_SQR4_SQ15_Msk                    /*!< ADC 15th conversion in regular sequence */

+#define ADC_SQR4_SQ15_0                   (0x01UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000001 */

+#define ADC_SQR4_SQ15_1                   (0x02UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000002 */

+#define ADC_SQR4_SQ15_2                   (0x04UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000004 */

+#define ADC_SQR4_SQ15_3                   (0x08UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000008 */

+#define ADC_SQR4_SQ15_4                   (0x10UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000010 */

+

+#define ADC_SQR4_SQ16_Pos                 (6U)

+#define ADC_SQR4_SQ16_Msk                 (0x1FUL << ADC_SQR4_SQ16_Pos)        /*!< 0x000007C0 */

+#define ADC_SQR4_SQ16                     ADC_SQR4_SQ16_Msk                    /*!< ADC 16th conversion in regular sequence */

+#define ADC_SQR4_SQ16_0                   (0x01UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000040 */

+#define ADC_SQR4_SQ16_1                   (0x02UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000080 */

+#define ADC_SQR4_SQ16_2                   (0x04UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000100 */

+#define ADC_SQR4_SQ16_3                   (0x08UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000200 */

+#define ADC_SQR4_SQ16_4                   (0x10UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000400 */

+/********************  Bit definition for ADC_DR register  ********************/

+#define ADC_DR_RDATA_Pos                  (0U)

+#define ADC_DR_RDATA_Msk                  (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)   /*!< 0xFFFFFFFF */

+#define ADC_DR_RDATA                      ADC_DR_RDATA_Msk                     /*!< ADC regular Data converted */

+

+/********************  Bit definition for ADC_JSQR register  ********************/

+#define ADC_JSQR_JL_Pos                   (0U)

+#define ADC_JSQR_JL_Msk                   (0x3UL << ADC_JSQR_JL_Pos)           /*!< 0x00000003 */

+#define ADC_JSQR_JL                       ADC_JSQR_JL_Msk                      /*!< ADC injected channel sequence length */

+#define ADC_JSQR_JL_0                     (0x1UL << ADC_JSQR_JL_Pos)           /*!< 0x00000001 */

+#define ADC_JSQR_JL_1                     (0x2UL << ADC_JSQR_JL_Pos)           /*!< 0x00000002 */

+

+#define ADC_JSQR_JEXTSEL_Pos              (2U)

+#define ADC_JSQR_JEXTSEL_Msk              (0x1FUL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x0000007C */

+#define ADC_JSQR_JEXTSEL                  ADC_JSQR_JEXTSEL_Msk                 /*!< ADC external trigger selection for injected group */

+#define ADC_JSQR_JEXTSEL_0                (0x01UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000004 */

+#define ADC_JSQR_JEXTSEL_1                (0x02UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000008 */

+#define ADC_JSQR_JEXTSEL_2                (0x04UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000010 */

+#define ADC_JSQR_JEXTSEL_3                (0x08UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000020 */

+#define ADC_JSQR_JEXTSEL_4                (0x10UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000040 */

+

+#define ADC_JSQR_JEXTEN_Pos               (7U)

+#define ADC_JSQR_JEXTEN_Msk               (0x3UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000180 */

+#define ADC_JSQR_JEXTEN                   ADC_JSQR_JEXTEN_Msk                  /*!< ADC external trigger enable and polarity selection for injected channels */

+#define ADC_JSQR_JEXTEN_0                 (0x1UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000080 */

+#define ADC_JSQR_JEXTEN_1                 (0x2UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000100 */

+

+#define ADC_JSQR_JSQ1_Pos                 (9U)

+#define ADC_JSQR_JSQ1_Msk                 (0x1FUL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00003E00 */

+#define ADC_JSQR_JSQ1                     ADC_JSQR_JSQ1_Msk                    /*!< ADC 1st conversion in injected sequence */

+#define ADC_JSQR_JSQ1_0                   (0x01UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000200 */

+#define ADC_JSQR_JSQ1_1                   (0x02UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000400 */

+#define ADC_JSQR_JSQ1_2                   (0x04UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000800 */

+#define ADC_JSQR_JSQ1_3                   (0x08UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00001000 */

+#define ADC_JSQR_JSQ1_4                   (0x10UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00002000 */

+

+#define ADC_JSQR_JSQ2_Pos                 (15U)

+#define ADC_JSQR_JSQ2_Msk                 (0x1FUL << ADC_JSQR_JSQ2_Pos)        /*!< 0x000F8000 */

+#define ADC_JSQR_JSQ2                     ADC_JSQR_JSQ2_Msk                    /*!< ADC 2nd conversion in injected sequence */

+#define ADC_JSQR_JSQ2_0                   (0x01UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00008000 */

+#define ADC_JSQR_JSQ2_1                   (0x02UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00010000 */

+#define ADC_JSQR_JSQ2_2                   (0x04UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00020000 */

+#define ADC_JSQR_JSQ2_3                   (0x08UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00040000 */

+#define ADC_JSQR_JSQ2_4                   (0x10UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00080000 */

+

+#define ADC_JSQR_JSQ3_Pos                 (21U)

+#define ADC_JSQR_JSQ3_Msk                 (0x1FUL << ADC_JSQR_JSQ3_Pos)        /*!< 0x03E00000 */

+#define ADC_JSQR_JSQ3                     ADC_JSQR_JSQ3_Msk                    /*!< ADC 3rd conversion in injected sequence */

+#define ADC_JSQR_JSQ3_0                   (0x01UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00200000 */

+#define ADC_JSQR_JSQ3_1                   (0x02UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00400000 */

+#define ADC_JSQR_JSQ3_2                   (0x04UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00800000 */

+#define ADC_JSQR_JSQ3_3                   (0x08UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x01000000 */

+#define ADC_JSQR_JSQ3_4                   (0x10UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x02000000 */

+

+#define ADC_JSQR_JSQ4_Pos                 (27U)

+#define ADC_JSQR_JSQ4_Msk                 (0x1FUL << ADC_JSQR_JSQ4_Pos)        /*!< 0xF8000000 */

+#define ADC_JSQR_JSQ4                     ADC_JSQR_JSQ4_Msk                    /*!< ADC 4th conversion in injected sequence */

+#define ADC_JSQR_JSQ4_0                   (0x01UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x08000000 */

+#define ADC_JSQR_JSQ4_1                   (0x02UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x10000000 */

+#define ADC_JSQR_JSQ4_2                   (0x04UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x20000000 */

+#define ADC_JSQR_JSQ4_3                   (0x08UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x40000000 */

+#define ADC_JSQR_JSQ4_4                   (0x10UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_OFR1 register  ********************/

+#define ADC_OFR1_OFFSET1_Pos              (0U)

+#define ADC_OFR1_OFFSET1_Msk              (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR1_OFFSET1                  ADC_OFR1_OFFSET1_Msk                  /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */

+#define ADC_OFR1_OFFSET1_0                (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */

+#define ADC_OFR1_OFFSET1_1                (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */

+#define ADC_OFR1_OFFSET1_2                (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */

+#define ADC_OFR1_OFFSET1_3                (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */

+#define ADC_OFR1_OFFSET1_4                (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */

+#define ADC_OFR1_OFFSET1_5                (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */

+#define ADC_OFR1_OFFSET1_6                (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */

+#define ADC_OFR1_OFFSET1_7                (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */

+#define ADC_OFR1_OFFSET1_8                (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */

+#define ADC_OFR1_OFFSET1_9                (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */

+#define ADC_OFR1_OFFSET1_10               (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */

+#define ADC_OFR1_OFFSET1_11               (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */

+#define ADC_OFR1_OFFSET1_12               (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */

+#define ADC_OFR1_OFFSET1_13               (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */

+#define ADC_OFR1_OFFSET1_14               (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */

+#define ADC_OFR1_OFFSET1_15               (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */

+#define ADC_OFR1_OFFSET1_16               (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */

+#define ADC_OFR1_OFFSET1_17               (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */

+#define ADC_OFR1_OFFSET1_18               (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */

+#define ADC_OFR1_OFFSET1_19               (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */

+#define ADC_OFR1_OFFSET1_20               (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */

+#define ADC_OFR1_OFFSET1_21               (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */

+#define ADC_OFR1_OFFSET1_22               (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */

+#define ADC_OFR1_OFFSET1_23               (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */

+#define ADC_OFR1_OFFSET1_24               (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */

+#define ADC_OFR1_OFFSET1_25               (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR1_OFFSET1_CH_Pos           (26U)

+#define ADC_OFR1_OFFSET1_CH_Msk           (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR1_OFFSET1_CH               ADC_OFR1_OFFSET1_CH_Msk               /*!< ADC Channel selection for the data offset 1 */

+#define ADC_OFR1_OFFSET1_CH_0             (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR1_OFFSET1_CH_1             (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR1_OFFSET1_CH_2             (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR1_OFFSET1_CH_3             (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR1_OFFSET1_CH_4             (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR1_SSATE_Pos                (31U)

+#define ADC_OFR1_SSATE_Msk                (0x1UL << ADC_OFR1_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR1_SSATE                    ADC_OFR1_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR2 register  ********************/

+#define ADC_OFR2_OFFSET2_Pos              (0U)

+#define ADC_OFR2_OFFSET2_Msk              (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR2_OFFSET2                  ADC_OFR2_OFFSET2_Msk                  /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */

+#define ADC_OFR2_OFFSET2_0                (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */

+#define ADC_OFR2_OFFSET2_1                (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */

+#define ADC_OFR2_OFFSET2_2                (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */

+#define ADC_OFR2_OFFSET2_3                (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */

+#define ADC_OFR2_OFFSET2_4                (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */

+#define ADC_OFR2_OFFSET2_5                (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */

+#define ADC_OFR2_OFFSET2_6                (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */

+#define ADC_OFR2_OFFSET2_7                (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */

+#define ADC_OFR2_OFFSET2_8                (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */

+#define ADC_OFR2_OFFSET2_9                (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */

+#define ADC_OFR2_OFFSET2_10               (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */

+#define ADC_OFR2_OFFSET2_11               (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */

+#define ADC_OFR2_OFFSET2_12               (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */

+#define ADC_OFR2_OFFSET2_13               (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */

+#define ADC_OFR2_OFFSET2_14               (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */

+#define ADC_OFR2_OFFSET2_15               (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */

+#define ADC_OFR2_OFFSET2_16               (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */

+#define ADC_OFR2_OFFSET2_17               (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */

+#define ADC_OFR2_OFFSET2_18               (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */

+#define ADC_OFR2_OFFSET2_19               (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */

+#define ADC_OFR2_OFFSET2_20               (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */

+#define ADC_OFR2_OFFSET2_21               (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */

+#define ADC_OFR2_OFFSET2_22               (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */

+#define ADC_OFR2_OFFSET2_23               (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */

+#define ADC_OFR2_OFFSET2_24               (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */

+#define ADC_OFR2_OFFSET2_25               (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR2_OFFSET2_CH_Pos           (26U)

+#define ADC_OFR2_OFFSET2_CH_Msk           (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR2_OFFSET2_CH               ADC_OFR2_OFFSET2_CH_Msk               /*!< ADC Channel selection for the data offset 2 */

+#define ADC_OFR2_OFFSET2_CH_0             (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR2_OFFSET2_CH_1             (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR2_OFFSET2_CH_2             (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR2_OFFSET2_CH_3             (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR2_OFFSET2_CH_4             (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR2_SSATE_Pos                (31U)

+#define ADC_OFR2_SSATE_Msk                (0x1UL << ADC_OFR2_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR2_SSATE                    ADC_OFR2_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR3 register  ********************/

+#define ADC_OFR3_OFFSET3_Pos              (0U)

+#define ADC_OFR3_OFFSET3_Msk              (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR3_OFFSET3                  ADC_OFR3_OFFSET3_Msk                  /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */

+#define ADC_OFR3_OFFSET3_0                (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */

+#define ADC_OFR3_OFFSET3_1                (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */

+#define ADC_OFR3_OFFSET3_2                (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */

+#define ADC_OFR3_OFFSET3_3                (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */

+#define ADC_OFR3_OFFSET3_4                (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */

+#define ADC_OFR3_OFFSET3_5                (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */

+#define ADC_OFR3_OFFSET3_6                (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */

+#define ADC_OFR3_OFFSET3_7                (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */

+#define ADC_OFR3_OFFSET3_8                (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */

+#define ADC_OFR3_OFFSET3_9                (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */

+#define ADC_OFR3_OFFSET3_10               (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */

+#define ADC_OFR3_OFFSET3_11               (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */

+#define ADC_OFR3_OFFSET3_12               (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */

+#define ADC_OFR3_OFFSET3_13               (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */

+#define ADC_OFR3_OFFSET3_14               (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */

+#define ADC_OFR3_OFFSET3_15               (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */

+#define ADC_OFR3_OFFSET3_16               (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */

+#define ADC_OFR3_OFFSET3_17               (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */

+#define ADC_OFR3_OFFSET3_18               (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */

+#define ADC_OFR3_OFFSET3_19               (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */

+#define ADC_OFR3_OFFSET3_20               (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */

+#define ADC_OFR3_OFFSET3_21               (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */

+#define ADC_OFR3_OFFSET3_22               (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */

+#define ADC_OFR3_OFFSET3_23               (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */

+#define ADC_OFR3_OFFSET3_24               (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */

+#define ADC_OFR3_OFFSET3_25               (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR3_OFFSET3_CH_Pos           (26U)

+#define ADC_OFR3_OFFSET3_CH_Msk           (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR3_OFFSET3_CH               ADC_OFR3_OFFSET3_CH_Msk               /*!< ADC Channel selection for the data offset 3 */

+#define ADC_OFR3_OFFSET3_CH_0             (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR3_OFFSET3_CH_1             (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR3_OFFSET3_CH_2             (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR3_OFFSET3_CH_3             (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR3_OFFSET3_CH_4             (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR3_SSATE_Pos                (31U)

+#define ADC_OFR3_SSATE_Msk                (0x1UL << ADC_OFR3_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR3_SSATE                    ADC_OFR3_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR4 register  ********************/

+#define ADC_OFR4_OFFSET4_Pos              (0U)

+#define ADC_OFR4_OFFSET4_Msk              (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR4_OFFSET4                  ADC_OFR4_OFFSET4_Msk                  /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */

+#define ADC_OFR4_OFFSET4_0                (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */

+#define ADC_OFR4_OFFSET4_1                (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */

+#define ADC_OFR4_OFFSET4_2                (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */

+#define ADC_OFR4_OFFSET4_3                (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */

+#define ADC_OFR4_OFFSET4_4                (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */

+#define ADC_OFR4_OFFSET4_5                (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */

+#define ADC_OFR4_OFFSET4_6                (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */

+#define ADC_OFR4_OFFSET4_7                (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */

+#define ADC_OFR4_OFFSET4_8                (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */

+#define ADC_OFR4_OFFSET4_9                (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */

+#define ADC_OFR4_OFFSET4_10               (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */

+#define ADC_OFR4_OFFSET4_11               (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */

+#define ADC_OFR4_OFFSET4_12               (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */

+#define ADC_OFR4_OFFSET4_13               (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */

+#define ADC_OFR4_OFFSET4_14               (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */

+#define ADC_OFR4_OFFSET4_15               (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */

+#define ADC_OFR4_OFFSET4_16               (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */

+#define ADC_OFR4_OFFSET4_17               (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */

+#define ADC_OFR4_OFFSET4_18               (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */

+#define ADC_OFR4_OFFSET4_19               (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */

+#define ADC_OFR4_OFFSET4_20               (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */

+#define ADC_OFR4_OFFSET4_21               (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */

+#define ADC_OFR4_OFFSET4_22               (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */

+#define ADC_OFR4_OFFSET4_23               (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */

+#define ADC_OFR4_OFFSET4_24               (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */

+#define ADC_OFR4_OFFSET4_25               (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR4_OFFSET4_CH_Pos           (26U)

+#define ADC_OFR4_OFFSET4_CH_Msk           (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR4_OFFSET4_CH               ADC_OFR4_OFFSET4_CH_Msk               /*!< ADC Channel selection for the data offset 4 */

+#define ADC_OFR4_OFFSET4_CH_0             (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR4_OFFSET4_CH_1             (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR4_OFFSET4_CH_2             (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR4_OFFSET4_CH_3             (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR4_OFFSET4_CH_4             (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR4_SSATE_Pos                (31U)

+#define ADC_OFR4_SSATE_Msk                (0x1UL << ADC_OFR4_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR4_SSATE                    ADC_OFR4_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_JDR1 register  ********************/

+#define ADC_JDR1_JDATA_Pos                (0U)

+#define ADC_JDR1_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR1_JDATA                    ADC_JDR1_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR1_JDATA_0                  (0x00000001UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR1_JDATA_1                  (0x00000002UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR1_JDATA_2                  (0x00000004UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR1_JDATA_3                  (0x00000008UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR1_JDATA_4                  (0x00000010UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR1_JDATA_5                  (0x00000020UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR1_JDATA_6                  (0x00000040UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR1_JDATA_7                  (0x00000080UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR1_JDATA_8                  (0x00000100UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR1_JDATA_9                  (0x00000200UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR1_JDATA_10                 (0x00000400UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR1_JDATA_11                 (0x00000800UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR1_JDATA_12                 (0x00001000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR1_JDATA_13                 (0x00002000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR1_JDATA_14                 (0x00004000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR1_JDATA_15                 (0x00008000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR1_JDATA_16                 (0x00010000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR1_JDATA_17                 (0x00020000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR1_JDATA_18                 (0x00040000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR1_JDATA_19                 (0x00080000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR1_JDATA_20                 (0x00100000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR1_JDATA_21                 (0x00200000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR1_JDATA_22                 (0x00400000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR1_JDATA_23                 (0x00800000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR1_JDATA_24                 (0x01000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR1_JDATA_25                 (0x02000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR1_JDATA_26                 (0x04000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR1_JDATA_27                 (0x08000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR1_JDATA_28                 (0x10000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR1_JDATA_29                 (0x20000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR1_JDATA_30                 (0x40000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR1_JDATA_31                 (0x80000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR2 register  ********************/

+#define ADC_JDR2_JDATA_Pos                (0U)

+#define ADC_JDR2_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR2_JDATA                    ADC_JDR2_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR2_JDATA_0                  (0x00000001UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR2_JDATA_1                  (0x00000002UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR2_JDATA_2                  (0x00000004UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR2_JDATA_3                  (0x00000008UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR2_JDATA_4                  (0x00000010UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR2_JDATA_5                  (0x00000020UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR2_JDATA_6                  (0x00000040UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR2_JDATA_7                  (0x00000080UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR2_JDATA_8                  (0x00000100UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR2_JDATA_9                  (0x00000200UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR2_JDATA_10                 (0x00000400UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR2_JDATA_11                 (0x00000800UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR2_JDATA_12                 (0x00001000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR2_JDATA_13                 (0x00002000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR2_JDATA_14                 (0x00004000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR2_JDATA_15                 (0x00008000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR2_JDATA_16                 (0x00010000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR2_JDATA_17                 (0x00020000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR2_JDATA_18                 (0x00040000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR2_JDATA_19                 (0x00080000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR2_JDATA_20                 (0x00100000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR2_JDATA_21                 (0x00200000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR2_JDATA_22                 (0x00400000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR2_JDATA_23                 (0x00800000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR2_JDATA_24                 (0x01000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR2_JDATA_25                 (0x02000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR2_JDATA_26                 (0x04000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR2_JDATA_27                 (0x08000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR2_JDATA_28                 (0x10000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR2_JDATA_29                 (0x20000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR2_JDATA_30                 (0x40000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR2_JDATA_31                 (0x80000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR3 register  ********************/

+#define ADC_JDR3_JDATA_Pos                (0U)

+#define ADC_JDR3_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR3_JDATA                    ADC_JDR3_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR3_JDATA_0                  (0x00000001UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR3_JDATA_1                  (0x00000002UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR3_JDATA_2                  (0x00000004UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR3_JDATA_3                  (0x00000008UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR3_JDATA_4                  (0x00000010UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR3_JDATA_5                  (0x00000020UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR3_JDATA_6                  (0x00000040UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR3_JDATA_7                  (0x00000080UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR3_JDATA_8                  (0x00000100UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR3_JDATA_9                  (0x00000200UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR3_JDATA_10                 (0x00000400UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR3_JDATA_11                 (0x00000800UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR3_JDATA_12                 (0x00001000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR3_JDATA_13                 (0x00002000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR3_JDATA_14                 (0x00004000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR3_JDATA_15                 (0x00008000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR3_JDATA_16                 (0x00010000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR3_JDATA_17                 (0x00020000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR3_JDATA_18                 (0x00040000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR3_JDATA_19                 (0x00080000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR3_JDATA_20                 (0x00100000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR3_JDATA_21                 (0x00200000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR3_JDATA_22                 (0x00400000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR3_JDATA_23                 (0x00800000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR3_JDATA_24                 (0x01000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR3_JDATA_25                 (0x02000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR3_JDATA_26                 (0x04000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR3_JDATA_27                 (0x08000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR3_JDATA_28                 (0x10000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR3_JDATA_29                 (0x20000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR3_JDATA_30                 (0x40000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR3_JDATA_31                 (0x80000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR4 register  ********************/

+#define ADC_JDR4_JDATA_Pos                (0U)

+#define ADC_JDR4_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR4_JDATA                    ADC_JDR4_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR4_JDATA_0                  (0x00000001UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR4_JDATA_1                  (0x00000002UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR4_JDATA_2                  (0x00000004UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR4_JDATA_3                  (0x00000008UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR4_JDATA_4                  (0x00000010UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR4_JDATA_5                  (0x00000020UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR4_JDATA_6                  (0x00000040UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR4_JDATA_7                  (0x00000080UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR4_JDATA_8                  (0x00000100UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR4_JDATA_9                  (0x00000200UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR4_JDATA_10                 (0x00000400UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR4_JDATA_11                 (0x00000800UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR4_JDATA_12                 (0x00001000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR4_JDATA_13                 (0x00002000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR4_JDATA_14                 (0x00004000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR4_JDATA_15                 (0x00008000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR4_JDATA_16                 (0x00010000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR4_JDATA_17                 (0x00020000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR4_JDATA_18                 (0x00040000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR4_JDATA_19                 (0x00080000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR4_JDATA_20                 (0x00100000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR4_JDATA_21                 (0x00200000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR4_JDATA_22                 (0x00400000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR4_JDATA_23                 (0x00800000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR4_JDATA_24                 (0x01000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR4_JDATA_25                 (0x02000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR4_JDATA_26                 (0x04000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR4_JDATA_27                 (0x08000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR4_JDATA_28                 (0x10000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR4_JDATA_29                 (0x20000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR4_JDATA_30                 (0x40000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR4_JDATA_31                 (0x80000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_AWD2CR register  ********************/

+#define ADC_AWD2CR_AWD2CH_Pos             (0U)

+#define ADC_AWD2CR_AWD2CH_Msk             (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x000FFFFF */

+#define ADC_AWD2CR_AWD2CH                 ADC_AWD2CR_AWD2CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */

+#define ADC_AWD2CR_AWD2CH_0               (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000001 */

+#define ADC_AWD2CR_AWD2CH_1               (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000002 */

+#define ADC_AWD2CR_AWD2CH_2               (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000004 */

+#define ADC_AWD2CR_AWD2CH_3               (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000008 */

+#define ADC_AWD2CR_AWD2CH_4               (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000010 */

+#define ADC_AWD2CR_AWD2CH_5               (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000020 */

+#define ADC_AWD2CR_AWD2CH_6               (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000040 */

+#define ADC_AWD2CR_AWD2CH_7               (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000080 */

+#define ADC_AWD2CR_AWD2CH_8               (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000100 */

+#define ADC_AWD2CR_AWD2CH_9               (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000200 */

+#define ADC_AWD2CR_AWD2CH_10              (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000400 */

+#define ADC_AWD2CR_AWD2CH_11              (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000800 */

+#define ADC_AWD2CR_AWD2CH_12              (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00001000 */

+#define ADC_AWD2CR_AWD2CH_13              (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00002000 */

+#define ADC_AWD2CR_AWD2CH_14              (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00004000 */

+#define ADC_AWD2CR_AWD2CH_15              (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00008000 */

+#define ADC_AWD2CR_AWD2CH_16              (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00010000 */

+#define ADC_AWD2CR_AWD2CH_17              (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00020000 */

+#define ADC_AWD2CR_AWD2CH_18              (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */

+#define ADC_AWD2CR_AWD2CH_19              (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_AWD3CR register  ********************/

+#define ADC_AWD3CR_AWD3CH_Pos             (0U)

+#define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x000FFFFF */

+#define ADC_AWD3CR_AWD3CH                 ADC_AWD3CR_AWD3CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */

+#define ADC_AWD3CR_AWD3CH_0               (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000001 */

+#define ADC_AWD3CR_AWD3CH_1               (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000002 */

+#define ADC_AWD3CR_AWD3CH_2               (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000004 */

+#define ADC_AWD3CR_AWD3CH_3               (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000008 */

+#define ADC_AWD3CR_AWD3CH_4               (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000010 */

+#define ADC_AWD3CR_AWD3CH_5               (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000020 */

+#define ADC_AWD3CR_AWD3CH_6               (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000040 */

+#define ADC_AWD3CR_AWD3CH_7               (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000080 */

+#define ADC_AWD3CR_AWD3CH_8               (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000100 */

+#define ADC_AWD3CR_AWD3CH_9               (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000200 */

+#define ADC_AWD3CR_AWD3CH_10              (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000400 */

+#define ADC_AWD3CR_AWD3CH_11              (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000800 */

+#define ADC_AWD3CR_AWD3CH_12              (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00001000 */

+#define ADC_AWD3CR_AWD3CH_13              (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00002000 */

+#define ADC_AWD3CR_AWD3CH_14              (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00004000 */

+#define ADC_AWD3CR_AWD3CH_15              (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00008000 */

+#define ADC_AWD3CR_AWD3CH_16              (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00010000 */

+#define ADC_AWD3CR_AWD3CH_17              (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00020000 */

+#define ADC_AWD3CR_AWD3CH_18              (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */

+#define ADC_AWD3CR_AWD3CH_19              (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_DIFSEL register  ********************/

+#define ADC_DIFSEL_DIFSEL_Pos             (0U)

+#define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */

+#define ADC_DIFSEL_DIFSEL                 ADC_DIFSEL_DIFSEL_Msk                 /*!< ADC differential modes for channels 1 to 18 */

+#define ADC_DIFSEL_DIFSEL_0               (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000001 */

+#define ADC_DIFSEL_DIFSEL_1               (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000002 */

+#define ADC_DIFSEL_DIFSEL_2               (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000004 */

+#define ADC_DIFSEL_DIFSEL_3               (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000008 */

+#define ADC_DIFSEL_DIFSEL_4               (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000010 */

+#define ADC_DIFSEL_DIFSEL_5               (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000020 */

+#define ADC_DIFSEL_DIFSEL_6               (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000040 */

+#define ADC_DIFSEL_DIFSEL_7               (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000080 */

+#define ADC_DIFSEL_DIFSEL_8               (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000100 */

+#define ADC_DIFSEL_DIFSEL_9               (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000200 */

+#define ADC_DIFSEL_DIFSEL_10              (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000400 */

+#define ADC_DIFSEL_DIFSEL_11              (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000800 */

+#define ADC_DIFSEL_DIFSEL_12              (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00001000 */

+#define ADC_DIFSEL_DIFSEL_13              (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00002000 */

+#define ADC_DIFSEL_DIFSEL_14              (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00004000 */

+#define ADC_DIFSEL_DIFSEL_15              (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00008000 */

+#define ADC_DIFSEL_DIFSEL_16              (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00010000 */

+#define ADC_DIFSEL_DIFSEL_17              (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00020000 */

+#define ADC_DIFSEL_DIFSEL_18              (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00040000 */

+#define ADC_DIFSEL_DIFSEL_19              (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_CALFACT register  ********************/

+#define ADC_CALFACT_CALFACT_S_Pos         (0U)

+#define ADC_CALFACT_CALFACT_S_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */

+#define ADC_CALFACT_CALFACT_S             ADC_CALFACT_CALFACT_S_Msk              /*!< ADC calibration factors in single-ended mode */

+#define ADC_CALFACT_CALFACT_S_0           (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */

+#define ADC_CALFACT_CALFACT_S_1           (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */

+#define ADC_CALFACT_CALFACT_S_2           (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */

+#define ADC_CALFACT_CALFACT_S_3           (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */

+#define ADC_CALFACT_CALFACT_S_4           (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */

+#define ADC_CALFACT_CALFACT_S_5           (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */

+#define ADC_CALFACT_CALFACT_S_6           (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */

+#define ADC_CALFACT_CALFACT_S_7           (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */

+#define ADC_CALFACT_CALFACT_S_8           (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */

+#define ADC_CALFACT_CALFACT_S_9           (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */

+#define ADC_CALFACT_CALFACT_S_10          (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */

+#define ADC_CALFACT_CALFACT_D_Pos         (16U)

+#define ADC_CALFACT_CALFACT_D_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */

+#define ADC_CALFACT_CALFACT_D             ADC_CALFACT_CALFACT_D_Msk              /*!< ADC calibration factors in differential mode */

+#define ADC_CALFACT_CALFACT_D_0           (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */

+#define ADC_CALFACT_CALFACT_D_1           (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */

+#define ADC_CALFACT_CALFACT_D_2           (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */

+#define ADC_CALFACT_CALFACT_D_3           (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */

+#define ADC_CALFACT_CALFACT_D_4           (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */

+#define ADC_CALFACT_CALFACT_D_5           (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */

+#define ADC_CALFACT_CALFACT_D_6           (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */

+#define ADC_CALFACT_CALFACT_D_7           (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */

+#define ADC_CALFACT_CALFACT_D_8           (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */

+#define ADC_CALFACT_CALFACT_D_9           (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */

+#define ADC_CALFACT_CALFACT_D_10          (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */

+

+/********************  Bit definition for ADC_CALFACT2 register  ********************/

+#define ADC_CALFACT2_LINCALFACT_Pos       (0U)

+#define ADC_CALFACT2_LINCALFACT_Msk       (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */

+#define ADC_CALFACT2_LINCALFACT           ADC_CALFACT2_LINCALFACT_Msk                   /*!< ADC Linearity calibration factors */

+#define ADC_CALFACT2_LINCALFACT_0         (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */

+#define ADC_CALFACT2_LINCALFACT_1         (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */

+#define ADC_CALFACT2_LINCALFACT_2         (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */

+#define ADC_CALFACT2_LINCALFACT_3         (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */

+#define ADC_CALFACT2_LINCALFACT_4         (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */

+#define ADC_CALFACT2_LINCALFACT_5         (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */

+#define ADC_CALFACT2_LINCALFACT_6         (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */

+#define ADC_CALFACT2_LINCALFACT_7         (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */

+#define ADC_CALFACT2_LINCALFACT_8         (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */

+#define ADC_CALFACT2_LINCALFACT_9         (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */

+#define ADC_CALFACT2_LINCALFACT_10        (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */

+#define ADC_CALFACT2_LINCALFACT_11        (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */

+#define ADC_CALFACT2_LINCALFACT_12        (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */

+#define ADC_CALFACT2_LINCALFACT_13        (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */

+#define ADC_CALFACT2_LINCALFACT_14        (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */

+#define ADC_CALFACT2_LINCALFACT_15        (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */

+#define ADC_CALFACT2_LINCALFACT_16        (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */

+#define ADC_CALFACT2_LINCALFACT_17        (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */

+#define ADC_CALFACT2_LINCALFACT_18        (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */

+#define ADC_CALFACT2_LINCALFACT_19        (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */

+#define ADC_CALFACT2_LINCALFACT_20        (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */

+#define ADC_CALFACT2_LINCALFACT_21        (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */

+#define ADC_CALFACT2_LINCALFACT_22        (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */

+#define ADC_CALFACT2_LINCALFACT_23        (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */

+#define ADC_CALFACT2_LINCALFACT_24        (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */

+#define ADC_CALFACT2_LINCALFACT_25        (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */

+#define ADC_CALFACT2_LINCALFACT_26        (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */

+#define ADC_CALFACT2_LINCALFACT_27        (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */

+#define ADC_CALFACT2_LINCALFACT_28        (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */

+#define ADC_CALFACT2_LINCALFACT_29        (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */

+

+/*************************  ADC Common registers  *****************************/

+/********************  Bit definition for ADC_CSR register  ********************/

+#define ADC_CSR_ADRDY_MST_Pos             (0U)

+#define ADC_CSR_ADRDY_MST_Msk             (0x1UL << ADC_CSR_ADRDY_MST_Pos)     /*!< 0x00000001 */

+#define ADC_CSR_ADRDY_MST                 ADC_CSR_ADRDY_MST_Msk                /*!< Master ADC ready */

+#define ADC_CSR_EOSMP_MST_Pos             (1U)

+#define ADC_CSR_EOSMP_MST_Msk             (0x1UL << ADC_CSR_EOSMP_MST_Pos)     /*!< 0x00000002 */

+#define ADC_CSR_EOSMP_MST                 ADC_CSR_EOSMP_MST_Msk                /*!< End of sampling phase flag of the master ADC */

+#define ADC_CSR_EOC_MST_Pos               (2U)

+#define ADC_CSR_EOC_MST_Msk               (0x1UL << ADC_CSR_EOC_MST_Pos)       /*!< 0x00000004 */

+#define ADC_CSR_EOC_MST                   ADC_CSR_EOC_MST_Msk                  /*!< End of regular conversion of the master ADC */

+#define ADC_CSR_EOS_MST_Pos               (3U)

+#define ADC_CSR_EOS_MST_Msk               (0x1UL << ADC_CSR_EOS_MST_Pos)       /*!< 0x00000008 */

+#define ADC_CSR_EOS_MST                   ADC_CSR_EOS_MST_Msk                  /*!< End of regular sequence flag of the master ADC */

+#define ADC_CSR_OVR_MST_Pos               (4U)

+#define ADC_CSR_OVR_MST_Msk               (0x1UL << ADC_CSR_OVR_MST_Pos)       /*!< 0x00000010 */

+#define ADC_CSR_OVR_MST                   ADC_CSR_OVR_MST_Msk                  /*!< Overrun flag of the master ADC */

+#define ADC_CSR_JEOC_MST_Pos              (5U)

+#define ADC_CSR_JEOC_MST_Msk              (0x1UL << ADC_CSR_JEOC_MST_Pos)      /*!< 0x00000020 */

+#define ADC_CSR_JEOC_MST                  ADC_CSR_JEOC_MST_Msk                 /*!< End of injected conversion of the master ADC */

+#define ADC_CSR_JEOS_MST_Pos              (6U)

+#define ADC_CSR_JEOS_MST_Msk              (0x1UL << ADC_CSR_JEOS_MST_Pos)      /*!< 0x00000040 */

+#define ADC_CSR_JEOS_MST                  ADC_CSR_JEOS_MST_Msk                 /*!< End of injected sequence flag of the master ADC */

+#define ADC_CSR_AWD1_MST_Pos              (7U)

+#define ADC_CSR_AWD1_MST_Msk              (0x1UL << ADC_CSR_AWD1_MST_Pos)      /*!< 0x00000080 */

+#define ADC_CSR_AWD1_MST                  ADC_CSR_AWD1_MST_Msk                 /*!< Analog watchdog 1 flag of the master ADC */

+#define ADC_CSR_AWD2_MST_Pos              (8U)

+#define ADC_CSR_AWD2_MST_Msk              (0x1UL << ADC_CSR_AWD2_MST_Pos)      /*!< 0x00000100 */

+#define ADC_CSR_AWD2_MST                  ADC_CSR_AWD2_MST_Msk                 /*!< Analog watchdog 2 flag of the master ADC */

+#define ADC_CSR_AWD3_MST_Pos              (9U)

+#define ADC_CSR_AWD3_MST_Msk              (0x1UL << ADC_CSR_AWD3_MST_Pos)      /*!< 0x00000200 */

+#define ADC_CSR_AWD3_MST                  ADC_CSR_AWD3_MST_Msk                 /*!< Analog watchdog 3 flag of the master ADC */

+#define ADC_CSR_JQOVF_MST_Pos             (10U)

+#define ADC_CSR_JQOVF_MST_Msk             (0x1UL << ADC_CSR_JQOVF_MST_Pos)     /*!< 0x00000400 */

+#define ADC_CSR_JQOVF_MST                 ADC_CSR_JQOVF_MST_Msk                /*!< Injected context queue overflow flag of the master ADC */

+#define ADC_CSR_ADRDY_SLV_Pos             (16U)

+#define ADC_CSR_ADRDY_SLV_Msk             (0x1UL << ADC_CSR_ADRDY_SLV_Pos)     /*!< 0x00010000 */

+#define ADC_CSR_ADRDY_SLV                 ADC_CSR_ADRDY_SLV_Msk                /*!< Slave ADC ready */

+#define ADC_CSR_EOSMP_SLV_Pos             (17U)

+#define ADC_CSR_EOSMP_SLV_Msk             (0x1UL << ADC_CSR_EOSMP_SLV_Pos)     /*!< 0x00020000 */

+#define ADC_CSR_EOSMP_SLV                 ADC_CSR_EOSMP_SLV_Msk                /*!< End of sampling phase flag of the slave ADC */

+#define ADC_CSR_EOC_SLV_Pos               (18U)

+#define ADC_CSR_EOC_SLV_Msk               (0x1UL << ADC_CSR_EOC_SLV_Pos)       /*!< 0x00040000 */

+#define ADC_CSR_EOC_SLV                   ADC_CSR_EOC_SLV_Msk                  /*!< End of regular conversion of the slave ADC */

+#define ADC_CSR_EOS_SLV_Pos               (19U)

+#define ADC_CSR_EOS_SLV_Msk               (0x1UL << ADC_CSR_EOS_SLV_Pos)       /*!< 0x00080000 */

+#define ADC_CSR_EOS_SLV                   ADC_CSR_EOS_SLV_Msk                  /*!< End of regular sequence flag of the slave ADC */

+#define ADC_CSR_OVR_SLV_Pos               (20U)

+#define ADC_CSR_OVR_SLV_Msk               (0x1UL << ADC_CSR_OVR_SLV_Pos)       /*!< 0x00100000 */

+#define ADC_CSR_OVR_SLV                   ADC_CSR_OVR_SLV_Msk                  /*!< Overrun flag of the slave ADC */

+#define ADC_CSR_JEOC_SLV_Pos              (21U)

+#define ADC_CSR_JEOC_SLV_Msk              (0x1UL << ADC_CSR_JEOC_SLV_Pos)      /*!< 0x00200000 */

+#define ADC_CSR_JEOC_SLV                  ADC_CSR_JEOC_SLV_Msk                 /*!< End of injected conversion of the slave ADC */

+#define ADC_CSR_JEOS_SLV_Pos              (22U)

+#define ADC_CSR_JEOS_SLV_Msk              (0x1UL << ADC_CSR_JEOS_SLV_Pos)      /*!< 0x00400000 */

+#define ADC_CSR_JEOS_SLV                  ADC_CSR_JEOS_SLV_Msk                 /*!< End of injected sequence flag of the slave ADC */

+#define ADC_CSR_AWD1_SLV_Pos              (23U)

+#define ADC_CSR_AWD1_SLV_Msk              (0x1UL << ADC_CSR_AWD1_SLV_Pos)      /*!< 0x00800000 */

+#define ADC_CSR_AWD1_SLV                  ADC_CSR_AWD1_SLV_Msk                 /*!< Analog watchdog 1 flag of the slave ADC */

+#define ADC_CSR_AWD2_SLV_Pos              (24U)

+#define ADC_CSR_AWD2_SLV_Msk              (0x1UL << ADC_CSR_AWD2_SLV_Pos)      /*!< 0x01000000 */

+#define ADC_CSR_AWD2_SLV                  ADC_CSR_AWD2_SLV_Msk                 /*!< Analog watchdog 2 flag of the slave ADC */

+#define ADC_CSR_AWD3_SLV_Pos              (25U)

+#define ADC_CSR_AWD3_SLV_Msk              (0x1UL << ADC_CSR_AWD3_SLV_Pos)      /*!< 0x02000000 */

+#define ADC_CSR_AWD3_SLV                  ADC_CSR_AWD3_SLV_Msk                 /*!< Analog watchdog 3 flag of the slave ADC */

+#define ADC_CSR_JQOVF_SLV_Pos             (26U)

+#define ADC_CSR_JQOVF_SLV_Msk             (0x1UL << ADC_CSR_JQOVF_SLV_Pos)     /*!< 0x04000000 */

+#define ADC_CSR_JQOVF_SLV                 ADC_CSR_JQOVF_SLV_Msk                /*!< Injected context queue overflow flag of the slave ADC */

+

+/********************  Bit definition for ADC_CCR register  ********************/

+#define ADC_CCR_DUAL_Pos                  (0U)

+#define ADC_CCR_DUAL_Msk                  (0x1FUL << ADC_CCR_DUAL_Pos)          /*!< 0x0000001F */

+#define ADC_CCR_DUAL                      ADC_CCR_DUAL_Msk                      /*!< Dual ADC mode selection */

+#define ADC_CCR_DUAL_0                    (0x01UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000001 */

+#define ADC_CCR_DUAL_1                    (0x02UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000002 */

+#define ADC_CCR_DUAL_2                    (0x04UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000004 */

+#define ADC_CCR_DUAL_3                    (0x08UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000008 */

+#define ADC_CCR_DUAL_4                    (0x10UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000010 */

+

+#define ADC_CCR_DELAY_Pos                 (8U)

+#define ADC_CCR_DELAY_Msk                 (0xFUL << ADC_CCR_DELAY_Pos)          /*!< 0x00000F00 */

+#define ADC_CCR_DELAY                     ADC_CCR_DELAY_Msk                     /*!< Delay between 2 sampling phases */

+#define ADC_CCR_DELAY_0                   (0x1UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000100 */

+#define ADC_CCR_DELAY_1                   (0x2UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000200 */

+#define ADC_CCR_DELAY_2                   (0x4UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000400 */

+#define ADC_CCR_DELAY_3                   (0x8UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000800 */

+

+

+#define ADC_CCR_DAMDF_Pos                 (14U)

+#define ADC_CCR_DAMDF_Msk                 (0x3UL << ADC_CCR_DAMDF_Pos)          /*!< 0x0000C000 */

+#define ADC_CCR_DAMDF                     ADC_CCR_DAMDF_Msk                     /*!< Dual ADC mode Data format */

+#define ADC_CCR_DAMDF_0                   (0x1UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00004000 */

+#define ADC_CCR_DAMDF_1                   (0x2UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00008000 */

+

+#define ADC_CCR_CKMODE_Pos                (16U)

+#define ADC_CCR_CKMODE_Msk                (0x3UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00030000 */

+#define ADC_CCR_CKMODE                    ADC_CCR_CKMODE_Msk                    /*!< ADC clock mode */

+#define ADC_CCR_CKMODE_0                  (0x1UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00010000 */

+#define ADC_CCR_CKMODE_1                  (0x2UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00020000 */

+

+#define ADC_CCR_PRESC_Pos                 (18U)

+#define ADC_CCR_PRESC_Msk                 (0xFUL << ADC_CCR_PRESC_Pos)          /*!< 0x003C0000 */

+#define ADC_CCR_PRESC                     ADC_CCR_PRESC_Msk                     /*!< ADC prescaler */

+#define ADC_CCR_PRESC_0                   (0x1UL << ADC_CCR_PRESC_Pos)          /*!< 0x00040000 */

+#define ADC_CCR_PRESC_1                   (0x2UL << ADC_CCR_PRESC_Pos)          /*!< 0x00080000 */

+#define ADC_CCR_PRESC_2                   (0x4UL << ADC_CCR_PRESC_Pos)          /*!< 0x00100000 */

+#define ADC_CCR_PRESC_3                   (0x8UL << ADC_CCR_PRESC_Pos)          /*!< 0x00200000 */

+

+#define ADC_CCR_VREFEN_Pos                (22U)

+#define ADC_CCR_VREFEN_Msk                (0x1UL << ADC_CCR_VREFEN_Pos)         /*!< 0x00400000 */

+#define ADC_CCR_VREFEN                    ADC_CCR_VREFEN_Msk                    /*!< VREFINT enable */

+#define ADC_CCR_TSEN_Pos                  (23U)

+#define ADC_CCR_TSEN_Msk                  (0x1UL << ADC_CCR_TSEN_Pos)           /*!< 0x00800000 */

+#define ADC_CCR_TSEN                      ADC_CCR_TSEN_Msk                      /*!< Temperature sensor enable */

+#define ADC_CCR_VBATEN_Pos                (24U)

+#define ADC_CCR_VBATEN_Msk                (0x1UL << ADC_CCR_VBATEN_Pos)         /*!< 0x01000000 */

+#define ADC_CCR_VBATEN                    ADC_CCR_VBATEN_Msk                    /*!< VBAT enable */

+

+/********************  Bit definition for ADC_CDR register  *******************/

+#define ADC_CDR_RDATA_MST_Pos             (0U)

+#define ADC_CDR_RDATA_MST_Msk             (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)   /*!< 0x0000FFFF */

+#define ADC_CDR_RDATA_MST                 ADC_CDR_RDATA_MST_Msk                 /*!< ADC multimode master group regular conversion data */

+

+#define ADC_CDR_RDATA_SLV_Pos             (16U)

+#define ADC_CDR_RDATA_SLV_Msk             (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)   /*!< 0xFFFF0000 */

+#define ADC_CDR_RDATA_SLV                 ADC_CDR_RDATA_SLV_Msk                 /*!< ADC multimode slave group regular conversion data */

+

+/********************  Bit definition for ADC_CDR2 register  ******************/

+#define ADC_CDR2_RDATA_ALT_Pos            (0U)

+#define ADC_CDR2_RDATA_ALT_Msk            (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */

+#define ADC_CDR2_RDATA_ALT                ADC_CDR2_RDATA_ALT_Msk                   /*!< Regular data of the master/slave alternated ADCs */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                   VREFBUF                                  */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for VREFBUF_CSR register  ****************/

+#define VREFBUF_CSR_ENVR_Pos        (0U)

+#define VREFBUF_CSR_ENVR_Msk        (0x1UL << VREFBUF_CSR_ENVR_Pos)            /*!< 0x00000001 */

+#define VREFBUF_CSR_ENVR            VREFBUF_CSR_ENVR_Msk                       /*!<Voltage reference buffer enable */

+#define VREFBUF_CSR_HIZ_Pos         (1U)

+#define VREFBUF_CSR_HIZ_Msk         (0x1UL << VREFBUF_CSR_HIZ_Pos)             /*!< 0x00000002 */

+#define VREFBUF_CSR_HIZ             VREFBUF_CSR_HIZ_Msk                        /*!<High impedance mode             */

+#define VREFBUF_CSR_VRR_Pos         (3U)

+#define VREFBUF_CSR_VRR_Msk         (0x1UL << VREFBUF_CSR_VRR_Pos)             /*!< 0x00000008 */

+#define VREFBUF_CSR_VRR             VREFBUF_CSR_VRR_Msk                        /*!<Voltage reference buffer ready  */

+#define VREFBUF_CSR_VRS_Pos         (4U)

+#define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */

+#define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */

+

+#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */

+#define VREFBUF_CSR_VRS_OUT2_Pos    (4U)

+#define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */

+#define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */

+#define VREFBUF_CSR_VRS_OUT3_Pos    (5U)

+#define VREFBUF_CSR_VRS_OUT3_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)        /*!< 0x00000020 */

+#define VREFBUF_CSR_VRS_OUT3        VREFBUF_CSR_VRS_OUT3_Msk                   /*!<Voltage reference VREF_OUT3     */

+#define VREFBUF_CSR_VRS_OUT4_Pos    (4U)

+#define VREFBUF_CSR_VRS_OUT4_Msk    (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)        /*!< 0x00000030 */

+#define VREFBUF_CSR_VRS_OUT4        VREFBUF_CSR_VRS_OUT4_Msk                   /*!<Voltage reference VREF_OUT4     */

+

+/*******************  Bit definition for VREFBUF_CCR register  ****************/

+#define VREFBUF_CCR_TRIM_Pos        (0U)

+#define VREFBUF_CCR_TRIM_Msk        (0x3FUL << VREFBUF_CCR_TRIM_Pos)           /*!< 0x0000003F */

+#define VREFBUF_CCR_TRIM            VREFBUF_CCR_TRIM_Msk                       /*!<TRIM[5:0] bits (Trimming code)  */

+

+/******************************************************************************/

+/*                                                                            */

+/*                 Flexible Datarate Controller Area Network                  */

+/*                                                                            */

+/******************************************************************************/

+/*!<FDCAN control and status registers */

+/*****************  Bit definition for FDCAN_CREL register  *******************/

+#define FDCAN_CREL_DAY_Pos        (0U)

+#define FDCAN_CREL_DAY_Msk        (0xFFUL << FDCAN_CREL_DAY_Pos)               /*!< 0x000000FF */

+#define FDCAN_CREL_DAY            FDCAN_CREL_DAY_Msk                           /*!<Timestamp Day                           */

+#define FDCAN_CREL_MON_Pos        (8U)

+#define FDCAN_CREL_MON_Msk        (0xFFUL << FDCAN_CREL_MON_Pos)               /*!< 0x0000FF00 */

+#define FDCAN_CREL_MON            FDCAN_CREL_MON_Msk                           /*!<Timestamp Month                         */

+#define FDCAN_CREL_YEAR_Pos       (16U)

+#define FDCAN_CREL_YEAR_Msk       (0xFUL << FDCAN_CREL_YEAR_Pos)               /*!< 0x000F0000 */

+#define FDCAN_CREL_YEAR           FDCAN_CREL_YEAR_Msk                          /*!<Timestamp Year                          */

+#define FDCAN_CREL_SUBSTEP_Pos    (20U)

+#define FDCAN_CREL_SUBSTEP_Msk    (0xFUL << FDCAN_CREL_SUBSTEP_Pos)            /*!< 0x00F00000 */

+#define FDCAN_CREL_SUBSTEP        FDCAN_CREL_SUBSTEP_Msk                       /*!<Sub-step of Core release                */

+#define FDCAN_CREL_STEP_Pos       (24U)

+#define FDCAN_CREL_STEP_Msk       (0xFUL << FDCAN_CREL_STEP_Pos)               /*!< 0x0F000000 */

+#define FDCAN_CREL_STEP           FDCAN_CREL_STEP_Msk                          /*!<Step of Core release                    */

+#define FDCAN_CREL_REL_Pos        (28U)

+#define FDCAN_CREL_REL_Msk        (0xFUL << FDCAN_CREL_REL_Pos)                /*!< 0xF0000000 */

+#define FDCAN_CREL_REL            FDCAN_CREL_REL_Msk                           /*!<Core release                            */

+

+/*****************  Bit definition for FDCAN_ENDN register  *******************/

+#define FDCAN_ENDN_ETV_Pos        (0U)

+#define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endiannes Test Value                    */

+

+/*****************  Bit definition for FDCAN_DBTP register  *******************/

+#define FDCAN_DBTP_DSJW_Pos       (0U)

+#define FDCAN_DBTP_DSJW_Msk       (0xFUL << FDCAN_DBTP_DSJW_Pos)               /*!< 0x0000000F */

+#define FDCAN_DBTP_DSJW           FDCAN_DBTP_DSJW_Msk                          /*!<Synchronization Jump Width              */

+#define FDCAN_DBTP_DTSEG2_Pos     (4U)

+#define FDCAN_DBTP_DTSEG2_Msk     (0xFUL << FDCAN_DBTP_DTSEG2_Pos)             /*!< 0x000000F0 */

+#define FDCAN_DBTP_DTSEG2         FDCAN_DBTP_DTSEG2_Msk                        /*!<Data time segment after sample point    */

+#define FDCAN_DBTP_DTSEG1_Pos     (8U)

+#define FDCAN_DBTP_DTSEG1_Msk     (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)            /*!< 0x00001F00 */

+#define FDCAN_DBTP_DTSEG1         FDCAN_DBTP_DTSEG1_Msk                        /*!<Data time segment before sample point   */

+#define FDCAN_DBTP_DBRP_Pos       (16U)

+#define FDCAN_DBTP_DBRP_Msk       (0x1FUL << FDCAN_DBTP_DBRP_Pos)              /*!< 0x001F0000 */

+#define FDCAN_DBTP_DBRP           FDCAN_DBTP_DBRP_Msk                          /*!<Data BIt Rate Prescaler                 */

+#define FDCAN_DBTP_TDC_Pos        (23U)

+#define FDCAN_DBTP_TDC_Msk        (0x1UL << FDCAN_DBTP_TDC_Pos)                /*!< 0x00800000 */

+#define FDCAN_DBTP_TDC            FDCAN_DBTP_TDC_Msk                           /*!<Transceiver Delay Compensation          */

+

+/*****************  Bit definition for FDCAN_TEST register  *******************/

+#define FDCAN_TEST_LBCK_Pos       (4U)

+#define FDCAN_TEST_LBCK_Msk       (0x1UL << FDCAN_TEST_LBCK_Pos)               /*!< 0x00000010 */

+#define FDCAN_TEST_LBCK           FDCAN_TEST_LBCK_Msk                          /*!<Loop Back mode                           */

+#define FDCAN_TEST_TX_Pos         (5U)

+#define FDCAN_TEST_TX_Msk         (0x3UL << FDCAN_TEST_TX_Pos)                 /*!< 0x00000060 */

+#define FDCAN_TEST_TX             FDCAN_TEST_TX_Msk                            /*!<Control of Transmit Pin                  */

+#define FDCAN_TEST_RX_Pos         (7U)

+#define FDCAN_TEST_RX_Msk         (0x1UL << FDCAN_TEST_RX_Pos)                 /*!< 0x00000080 */

+#define FDCAN_TEST_RX             FDCAN_TEST_RX_Msk                            /*!<Receive Pin                              */

+

+/*****************  Bit definition for FDCAN_RWD register  ********************/

+#define FDCAN_RWD_WDC_Pos         (0U)

+#define FDCAN_RWD_WDC_Msk         (0xFFUL << FDCAN_RWD_WDC_Pos)                /*!< 0x000000FF */

+#define FDCAN_RWD_WDC             FDCAN_RWD_WDC_Msk                            /*!<Watchdog configuration                   */

+#define FDCAN_RWD_WDV_Pos         (8U)

+#define FDCAN_RWD_WDV_Msk         (0xFFUL << FDCAN_RWD_WDV_Pos)                /*!< 0x0000FF00 */

+#define FDCAN_RWD_WDV             FDCAN_RWD_WDV_Msk                            /*!<Watchdog value                           */

+

+/*****************  Bit definition for FDCAN_CCCR register  ********************/

+#define FDCAN_CCCR_INIT_Pos       (0U)

+#define FDCAN_CCCR_INIT_Msk       (0x1UL << FDCAN_CCCR_INIT_Pos)               /*!< 0x00000001 */

+#define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!<Initialization                           */

+#define FDCAN_CCCR_CCE_Pos        (1U)

+#define FDCAN_CCCR_CCE_Msk        (0x1UL << FDCAN_CCCR_CCE_Pos)                /*!< 0x00000002 */

+#define FDCAN_CCCR_CCE            FDCAN_CCCR_CCE_Msk                           /*!<Configuration Change Enable              */

+#define FDCAN_CCCR_ASM_Pos        (2U)

+#define FDCAN_CCCR_ASM_Msk        (0x1UL << FDCAN_CCCR_ASM_Pos)                /*!< 0x00000004 */

+#define FDCAN_CCCR_ASM            FDCAN_CCCR_ASM_Msk                           /*!<ASM Restricted Operation Mode            */

+#define FDCAN_CCCR_CSA_Pos        (3U)

+#define FDCAN_CCCR_CSA_Msk        (0x1UL << FDCAN_CCCR_CSA_Pos)                /*!< 0x00000008 */

+#define FDCAN_CCCR_CSA            FDCAN_CCCR_CSA_Msk                           /*!<Clock Stop Acknowledge                   */

+#define FDCAN_CCCR_CSR_Pos        (4U)

+#define FDCAN_CCCR_CSR_Msk        (0x1UL << FDCAN_CCCR_CSR_Pos)                /*!< 0x00000010 */

+#define FDCAN_CCCR_CSR            FDCAN_CCCR_CSR_Msk                           /*!<Clock Stop Request                       */

+#define FDCAN_CCCR_MON_Pos        (5U)

+#define FDCAN_CCCR_MON_Msk        (0x1UL << FDCAN_CCCR_MON_Pos)                /*!< 0x00000020 */

+#define FDCAN_CCCR_MON            FDCAN_CCCR_MON_Msk                           /*!<Bus Monitoring Mode                      */

+#define FDCAN_CCCR_DAR_Pos        (6U)

+#define FDCAN_CCCR_DAR_Msk        (0x1UL << FDCAN_CCCR_DAR_Pos)                /*!< 0x00000040 */

+#define FDCAN_CCCR_DAR            FDCAN_CCCR_DAR_Msk                           /*!<Disable Automatic Retransmission         */

+#define FDCAN_CCCR_TEST_Pos       (7U)

+#define FDCAN_CCCR_TEST_Msk       (0x1UL << FDCAN_CCCR_TEST_Pos)               /*!< 0x00000080 */

+#define FDCAN_CCCR_TEST           FDCAN_CCCR_TEST_Msk                          /*!<Test Mode Enable                         */

+#define FDCAN_CCCR_FDOE_Pos       (8U)

+#define FDCAN_CCCR_FDOE_Msk       (0x1UL << FDCAN_CCCR_FDOE_Pos)               /*!< 0x00000100 */

+#define FDCAN_CCCR_FDOE           FDCAN_CCCR_FDOE_Msk                          /*!<FD Operation Enable                      */

+#define FDCAN_CCCR_BRSE_Pos       (9U)

+#define FDCAN_CCCR_BRSE_Msk       (0x1UL << FDCAN_CCCR_BRSE_Pos)               /*!< 0x00000200 */

+#define FDCAN_CCCR_BRSE           FDCAN_CCCR_BRSE_Msk                          /*!<FDCAN Bit Rate Switching                 */

+#define FDCAN_CCCR_PXHD_Pos       (12U)

+#define FDCAN_CCCR_PXHD_Msk       (0x1UL << FDCAN_CCCR_PXHD_Pos)               /*!< 0x00001000 */

+#define FDCAN_CCCR_PXHD           FDCAN_CCCR_PXHD_Msk                          /*!<Protocol Exception Handling Disable      */

+#define FDCAN_CCCR_EFBI_Pos       (13U)

+#define FDCAN_CCCR_EFBI_Msk       (0x1UL << FDCAN_CCCR_EFBI_Pos)               /*!< 0x00002000 */

+#define FDCAN_CCCR_EFBI           FDCAN_CCCR_EFBI_Msk                          /*!<Edge Filtering during Bus Integration    */

+#define FDCAN_CCCR_TXP_Pos        (14U)

+#define FDCAN_CCCR_TXP_Msk        (0x1UL << FDCAN_CCCR_TXP_Pos)                /*!< 0x00004000 */

+#define FDCAN_CCCR_TXP            FDCAN_CCCR_TXP_Msk                           /*!<Two CAN bit times Pause                  */

+#define FDCAN_CCCR_NISO_Pos       (15U)

+#define FDCAN_CCCR_NISO_Msk       (0x1UL << FDCAN_CCCR_NISO_Pos)               /*!< 0x00008000 */

+#define FDCAN_CCCR_NISO           FDCAN_CCCR_NISO_Msk                          /*!<Non ISO Operation                        */

+

+/*****************  Bit definition for FDCAN_NBTP register  ********************/

+#define FDCAN_NBTP_NTSEG2_Pos     (0U)

+#define FDCAN_NBTP_NTSEG2_Msk     (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)            /*!< 0x0000007F */

+#define FDCAN_NBTP_NTSEG2         FDCAN_NBTP_NTSEG2_Msk                        /*!<Nominal Time segment after sample point  */

+#define FDCAN_NBTP_NTSEG1_Pos     (8U)

+#define FDCAN_NBTP_NTSEG1_Msk     (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)            /*!< 0x0000FF00 */

+#define FDCAN_NBTP_NTSEG1         FDCAN_NBTP_NTSEG1_Msk                        /*!<Nominal Time segment before sample point */

+#define FDCAN_NBTP_NBRP_Pos       (16U)

+#define FDCAN_NBTP_NBRP_Msk       (0x1FFUL << FDCAN_NBTP_NBRP_Pos)             /*!< 0x01FF0000 */

+#define FDCAN_NBTP_NBRP           FDCAN_NBTP_NBRP_Msk                          /*!<Bit Rate Prescaler                       */

+#define FDCAN_NBTP_NSJW_Pos       (25U)

+#define FDCAN_NBTP_NSJW_Msk       (0x7FUL << FDCAN_NBTP_NSJW_Pos)              /*!< 0xFE000000 */

+#define FDCAN_NBTP_NSJW           FDCAN_NBTP_NSJW_Msk                          /*!<Nominal (Re)Synchronization Jump Width   */

+

+/*****************  Bit definition for FDCAN_TSCC register  ********************/

+#define FDCAN_TSCC_TSS_Pos        (0U)

+#define FDCAN_TSCC_TSS_Msk        (0x3UL << FDCAN_TSCC_TSS_Pos)                /*!< 0x00000003 */

+#define FDCAN_TSCC_TSS            FDCAN_TSCC_TSS_Msk                           /*!<Timestamp Select                         */

+#define FDCAN_TSCC_TCP_Pos        (16U)

+#define FDCAN_TSCC_TCP_Msk        (0xFUL << FDCAN_TSCC_TCP_Pos)                /*!< 0x000F0000 */

+#define FDCAN_TSCC_TCP            FDCAN_TSCC_TCP_Msk                           /*!<Timestamp Counter Prescaler              */

+

+/*****************  Bit definition for FDCAN_TSCV register  ********************/

+#define FDCAN_TSCV_TSC_Pos        (0U)

+#define FDCAN_TSCV_TSC_Msk        (0xFFFFUL << FDCAN_TSCV_TSC_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TSCV_TSC            FDCAN_TSCV_TSC_Msk                           /*!<Timestamp Counter                        */

+

+/*****************  Bit definition for FDCAN_TOCC register  ********************/

+#define FDCAN_TOCC_ETOC_Pos       (0U)

+#define FDCAN_TOCC_ETOC_Msk       (0x1UL << FDCAN_TOCC_ETOC_Pos)               /*!< 0x00000001 */

+#define FDCAN_TOCC_ETOC           FDCAN_TOCC_ETOC_Msk                          /*!<Enable Timeout Counter                   */

+#define FDCAN_TOCC_TOS_Pos        (1U)

+#define FDCAN_TOCC_TOS_Msk        (0x3UL << FDCAN_TOCC_TOS_Pos)                /*!< 0x00000006 */

+#define FDCAN_TOCC_TOS            FDCAN_TOCC_TOS_Msk                           /*!<Timeout Select                           */

+#define FDCAN_TOCC_TOP_Pos        (16U)

+#define FDCAN_TOCC_TOP_Msk        (0xFFFFUL << FDCAN_TOCC_TOP_Pos)             /*!< 0xFFFF0000 */

+#define FDCAN_TOCC_TOP            FDCAN_TOCC_TOP_Msk                           /*!<Timeout Period                           */

+

+/*****************  Bit definition for FDCAN_TOCV register  ********************/

+#define FDCAN_TOCV_TOC_Pos        (0U)

+#define FDCAN_TOCV_TOC_Msk        (0xFFFFUL << FDCAN_TOCV_TOC_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TOCV_TOC            FDCAN_TOCV_TOC_Msk                           /*!<Timeout Counter                          */

+

+/*****************  Bit definition for FDCAN_ECR register  *********************/

+#define FDCAN_ECR_TEC_Pos         (0U)

+#define FDCAN_ECR_TEC_Msk         (0xFUL << FDCAN_ECR_TEC_Pos)                 /*!< 0x0000000F */

+#define FDCAN_ECR_TEC             FDCAN_ECR_TEC_Msk                            /*!<Transmit Error Counter                   */

+#define FDCAN_ECR_REC_Pos         (8U)

+#define FDCAN_ECR_REC_Msk         (0x7FUL << FDCAN_ECR_REC_Pos)                /*!< 0x00007F00 */

+#define FDCAN_ECR_REC             FDCAN_ECR_REC_Msk                            /*!<Receive Error Counter                    */

+#define FDCAN_ECR_RP_Pos          (15U)

+#define FDCAN_ECR_RP_Msk          (0x1UL << FDCAN_ECR_RP_Pos)                  /*!< 0x00008000 */

+#define FDCAN_ECR_RP              FDCAN_ECR_RP_Msk                             /*!<Receive Error Passive                    */

+#define FDCAN_ECR_CEL_Pos         (16U)

+#define FDCAN_ECR_CEL_Msk         (0xFFUL << FDCAN_ECR_CEL_Pos)                /*!< 0x00FF0000 */

+#define FDCAN_ECR_CEL             FDCAN_ECR_CEL_Msk                            /*!<CAN Error Logging                        */

+

+/*****************  Bit definition for FDCAN_PSR register  *********************/

+#define FDCAN_PSR_LEC_Pos         (0U)

+#define FDCAN_PSR_LEC_Msk         (0x7UL << FDCAN_PSR_LEC_Pos)                 /*!< 0x00000007 */

+#define FDCAN_PSR_LEC             FDCAN_PSR_LEC_Msk                            /*!<Last Error Code                          */

+#define FDCAN_PSR_ACT_Pos         (3U)

+#define FDCAN_PSR_ACT_Msk         (0x3UL << FDCAN_PSR_ACT_Pos)                 /*!< 0x00000018 */

+#define FDCAN_PSR_ACT             FDCAN_PSR_ACT_Msk                            /*!<Activity                                 */

+#define FDCAN_PSR_EP_Pos          (5U)

+#define FDCAN_PSR_EP_Msk          (0x1UL << FDCAN_PSR_EP_Pos)                  /*!< 0x00000020 */

+#define FDCAN_PSR_EP              FDCAN_PSR_EP_Msk                             /*!<Error Passive                            */

+#define FDCAN_PSR_EW_Pos          (6U)

+#define FDCAN_PSR_EW_Msk          (0x1UL << FDCAN_PSR_EW_Pos)                  /*!< 0x00000040 */

+#define FDCAN_PSR_EW              FDCAN_PSR_EW_Msk                             /*!<Warning Status                           */

+#define FDCAN_PSR_BO_Pos          (7U)

+#define FDCAN_PSR_BO_Msk          (0x1UL << FDCAN_PSR_BO_Pos)                  /*!< 0x00000080 */

+#define FDCAN_PSR_BO              FDCAN_PSR_BO_Msk                             /*!<Bus_Off Status                           */

+#define FDCAN_PSR_DLEC_Pos        (8U)

+#define FDCAN_PSR_DLEC_Msk        (0x7UL << FDCAN_PSR_DLEC_Pos)                /*!< 0x00000700 */

+#define FDCAN_PSR_DLEC            FDCAN_PSR_DLEC_Msk                           /*!<Data Last Error Code                     */

+#define FDCAN_PSR_RESI_Pos        (11U)

+#define FDCAN_PSR_RESI_Msk        (0x1UL << FDCAN_PSR_RESI_Pos)                /*!< 0x00000800 */

+#define FDCAN_PSR_RESI            FDCAN_PSR_RESI_Msk                           /*!<ESI flag of last received FDCAN Message  */

+#define FDCAN_PSR_RBRS_Pos        (12U)

+#define FDCAN_PSR_RBRS_Msk        (0x1UL << FDCAN_PSR_RBRS_Pos)                /*!< 0x00001000 */

+#define FDCAN_PSR_RBRS            FDCAN_PSR_RBRS_Msk                           /*!<BRS flag of last received FDCAN Message  */

+#define FDCAN_PSR_REDL_Pos        (13U)

+#define FDCAN_PSR_REDL_Msk        (0x1UL << FDCAN_PSR_REDL_Pos)                /*!< 0x00002000 */

+#define FDCAN_PSR_REDL            FDCAN_PSR_REDL_Msk                           /*!<Received FDCAN Message                   */

+#define FDCAN_PSR_PXE_Pos         (14U)

+#define FDCAN_PSR_PXE_Msk         (0x1UL << FDCAN_PSR_PXE_Pos)                 /*!< 0x00004000 */

+#define FDCAN_PSR_PXE             FDCAN_PSR_PXE_Msk                            /*!<Protocol Exception Event                 */

+#define FDCAN_PSR_TDCV_Pos        (16U)

+#define FDCAN_PSR_TDCV_Msk        (0x7FUL << FDCAN_PSR_TDCV_Pos)               /*!< 0x007F0000 */

+#define FDCAN_PSR_TDCV            FDCAN_PSR_TDCV_Msk                           /*!<Transmitter Delay Compensation Value     */

+

+/*****************  Bit definition for FDCAN_TDCR register  ********************/

+#define FDCAN_TDCR_TDCF_Pos       (0U)

+#define FDCAN_TDCR_TDCF_Msk       (0x7FUL << FDCAN_TDCR_TDCF_Pos)              /*!< 0x0000007F */

+#define FDCAN_TDCR_TDCF           FDCAN_TDCR_TDCF_Msk                          /*!<Transmitter Delay Compensation Filter    */

+#define FDCAN_TDCR_TDCO_Pos       (8U)

+#define FDCAN_TDCR_TDCO_Msk       (0x7FUL << FDCAN_TDCR_TDCO_Pos)              /*!< 0x00007F00 */

+#define FDCAN_TDCR_TDCO           FDCAN_TDCR_TDCO_Msk                          /*!<Transmitter Delay Compensation Offset    */

+

+/*****************  Bit definition for FDCAN_IR register  **********************/

+#define FDCAN_IR_RF0N_Pos         (0U)

+#define FDCAN_IR_RF0N_Msk         (0x1UL << FDCAN_IR_RF0N_Pos)                 /*!< 0x00000001 */

+#define FDCAN_IR_RF0N             FDCAN_IR_RF0N_Msk                            /*!<Rx FIFO 0 New Message                    */

+#define FDCAN_IR_RF0W_Pos         (1U)

+#define FDCAN_IR_RF0W_Msk         (0x1UL << FDCAN_IR_RF0W_Pos)                 /*!< 0x00000002 */

+#define FDCAN_IR_RF0W             FDCAN_IR_RF0W_Msk                            /*!<Rx FIFO 0 Watermark Reached              */

+#define FDCAN_IR_RF0F_Pos         (2U)

+#define FDCAN_IR_RF0F_Msk         (0x1UL << FDCAN_IR_RF0F_Pos)                 /*!< 0x00000004 */

+#define FDCAN_IR_RF0F             FDCAN_IR_RF0F_Msk                            /*!<Rx FIFO 0 Full                           */

+#define FDCAN_IR_RF0L_Pos         (3U)

+#define FDCAN_IR_RF0L_Msk         (0x1UL << FDCAN_IR_RF0L_Pos)                 /*!< 0x00000008 */

+#define FDCAN_IR_RF0L             FDCAN_IR_RF0L_Msk                            /*!<Rx FIFO 0 Message Lost                   */

+#define FDCAN_IR_RF1N_Pos         (4U)

+#define FDCAN_IR_RF1N_Msk         (0x1UL << FDCAN_IR_RF1N_Pos)                 /*!< 0x00000010 */

+#define FDCAN_IR_RF1N             FDCAN_IR_RF1N_Msk                            /*!<Rx FIFO 1 New Message                    */

+#define FDCAN_IR_RF1W_Pos         (5U)

+#define FDCAN_IR_RF1W_Msk         (0x1UL << FDCAN_IR_RF1W_Pos)                 /*!< 0x00000020 */

+#define FDCAN_IR_RF1W             FDCAN_IR_RF1W_Msk                            /*!<Rx FIFO 1 Watermark Reached              */

+#define FDCAN_IR_RF1F_Pos         (6U)

+#define FDCAN_IR_RF1F_Msk         (0x1UL << FDCAN_IR_RF1F_Pos)                 /*!< 0x00000040 */

+#define FDCAN_IR_RF1F             FDCAN_IR_RF1F_Msk                            /*!<Rx FIFO 1 Full                           */

+#define FDCAN_IR_RF1L_Pos         (7U)

+#define FDCAN_IR_RF1L_Msk         (0x1UL << FDCAN_IR_RF1L_Pos)                 /*!< 0x00000080 */

+#define FDCAN_IR_RF1L             FDCAN_IR_RF1L_Msk                            /*!<Rx FIFO 1 Message Lost                   */

+#define FDCAN_IR_HPM_Pos          (8U)

+#define FDCAN_IR_HPM_Msk          (0x1UL << FDCAN_IR_HPM_Pos)                  /*!< 0x00000100 */

+#define FDCAN_IR_HPM              FDCAN_IR_HPM_Msk                             /*!<High Priority Message                    */

+#define FDCAN_IR_TC_Pos           (9U)

+#define FDCAN_IR_TC_Msk           (0x1UL << FDCAN_IR_TC_Pos)                   /*!< 0x00000200 */

+#define FDCAN_IR_TC               FDCAN_IR_TC_Msk                              /*!<Transmission Completed                   */

+#define FDCAN_IR_TCF_Pos          (10U)

+#define FDCAN_IR_TCF_Msk          (0x1UL << FDCAN_IR_TCF_Pos)                  /*!< 0x00000400 */

+#define FDCAN_IR_TCF              FDCAN_IR_TCF_Msk                             /*!<Transmission Cancellation Finished       */

+#define FDCAN_IR_TFE_Pos          (11U)

+#define FDCAN_IR_TFE_Msk          (0x1UL << FDCAN_IR_TFE_Pos)                  /*!< 0x00000800 */

+#define FDCAN_IR_TFE              FDCAN_IR_TFE_Msk                             /*!<Tx FIFO Empty                            */

+#define FDCAN_IR_TEFN_Pos         (12U)

+#define FDCAN_IR_TEFN_Msk         (0x1UL << FDCAN_IR_TEFN_Pos)                 /*!< 0x00001000 */

+#define FDCAN_IR_TEFN             FDCAN_IR_TEFN_Msk                            /*!<Tx Event FIFO New Entry                  */

+#define FDCAN_IR_TEFW_Pos         (13U)

+#define FDCAN_IR_TEFW_Msk         (0x1UL << FDCAN_IR_TEFW_Pos)                 /*!< 0x00002000 */

+#define FDCAN_IR_TEFW             FDCAN_IR_TEFW_Msk                            /*!<Tx Event FIFO Watermark Reached          */

+#define FDCAN_IR_TEFF_Pos         (14U)

+#define FDCAN_IR_TEFF_Msk         (0x1UL << FDCAN_IR_TEFF_Pos)                 /*!< 0x00004000 */

+#define FDCAN_IR_TEFF             FDCAN_IR_TEFF_Msk                            /*!<Tx Event FIFO Full                       */

+#define FDCAN_IR_TEFL_Pos         (15U)

+#define FDCAN_IR_TEFL_Msk         (0x1UL << FDCAN_IR_TEFL_Pos)                 /*!< 0x00008000 */

+#define FDCAN_IR_TEFL             FDCAN_IR_TEFL_Msk                            /*!<Tx Event FIFO Element Lost               */

+#define FDCAN_IR_TSW_Pos          (16U)

+#define FDCAN_IR_TSW_Msk          (0x1UL << FDCAN_IR_TSW_Pos)                  /*!< 0x00010000 */

+#define FDCAN_IR_TSW              FDCAN_IR_TSW_Msk                             /*!<Timestamp Wraparound                     */

+#define FDCAN_IR_MRAF_Pos         (17U)

+#define FDCAN_IR_MRAF_Msk         (0x1UL << FDCAN_IR_MRAF_Pos)                 /*!< 0x00020000 */

+#define FDCAN_IR_MRAF             FDCAN_IR_MRAF_Msk                            /*!<Message RAM Access Failure               */

+#define FDCAN_IR_TOO_Pos          (18U)

+#define FDCAN_IR_TOO_Msk          (0x1UL << FDCAN_IR_TOO_Pos)                  /*!< 0x00040000 */

+#define FDCAN_IR_TOO              FDCAN_IR_TOO_Msk                             /*!<Timeout Occurred                         */

+#define FDCAN_IR_DRX_Pos          (19U)

+#define FDCAN_IR_DRX_Msk          (0x1UL << FDCAN_IR_DRX_Pos)                  /*!< 0x00080000 */

+#define FDCAN_IR_DRX              FDCAN_IR_DRX_Msk                             /*!<Message stored to Dedicated Rx Buffer    */

+#define FDCAN_IR_ELO_Pos          (22U)

+#define FDCAN_IR_ELO_Msk          (0x1UL << FDCAN_IR_ELO_Pos)                  /*!< 0x00400000 */

+#define FDCAN_IR_ELO              FDCAN_IR_ELO_Msk                             /*!<Error Logging Overflow                   */

+#define FDCAN_IR_EP_Pos           (23U)

+#define FDCAN_IR_EP_Msk           (0x1UL << FDCAN_IR_EP_Pos)                   /*!< 0x00800000 */

+#define FDCAN_IR_EP               FDCAN_IR_EP_Msk                              /*!<Error Passive                            */

+#define FDCAN_IR_EW_Pos           (24U)

+#define FDCAN_IR_EW_Msk           (0x1UL << FDCAN_IR_EW_Pos)                   /*!< 0x01000000 */

+#define FDCAN_IR_EW               FDCAN_IR_EW_Msk                              /*!<Warning Status                           */

+#define FDCAN_IR_BO_Pos           (25U)

+#define FDCAN_IR_BO_Msk           (0x1UL << FDCAN_IR_BO_Pos)                   /*!< 0x02000000 */

+#define FDCAN_IR_BO               FDCAN_IR_BO_Msk                              /*!<Bus_Off Status                           */

+#define FDCAN_IR_WDI_Pos          (26U)

+#define FDCAN_IR_WDI_Msk          (0x1UL << FDCAN_IR_WDI_Pos)                  /*!< 0x04000000 */

+#define FDCAN_IR_WDI              FDCAN_IR_WDI_Msk                             /*!<Watchdog Interrupt                       */

+#define FDCAN_IR_PEA_Pos          (27U)

+#define FDCAN_IR_PEA_Msk          (0x1UL << FDCAN_IR_PEA_Pos)                  /*!< 0x08000000 */

+#define FDCAN_IR_PEA              FDCAN_IR_PEA_Msk                             /*!<Protocol Error in Arbitration Phase      */

+#define FDCAN_IR_PED_Pos          (28U)

+#define FDCAN_IR_PED_Msk          (0x1UL << FDCAN_IR_PED_Pos)                  /*!< 0x10000000 */

+#define FDCAN_IR_PED              FDCAN_IR_PED_Msk                             /*!<Protocol Error in Data Phase             */

+#define FDCAN_IR_ARA_Pos          (29U)

+#define FDCAN_IR_ARA_Msk          (0x1UL << FDCAN_IR_ARA_Pos)                  /*!< 0x20000000 */

+#define FDCAN_IR_ARA              FDCAN_IR_ARA_Msk                             /*!<Access to Reserved Address               */

+

+/*****************  Bit definition for FDCAN_IE register  **********************/

+#define FDCAN_IE_RF0NE_Pos        (0U)

+#define FDCAN_IE_RF0NE_Msk        (0x1UL << FDCAN_IE_RF0NE_Pos)                /*!< 0x00000001 */

+#define FDCAN_IE_RF0NE            FDCAN_IE_RF0NE_Msk                           /*!<Rx FIFO 0 New Message Enable                 */

+#define FDCAN_IE_RF0WE_Pos        (1U)

+#define FDCAN_IE_RF0WE_Msk        (0x1UL << FDCAN_IE_RF0WE_Pos)                /*!< 0x00000002 */

+#define FDCAN_IE_RF0WE            FDCAN_IE_RF0WE_Msk                           /*!<Rx FIFO 0 Watermark Reached Enable           */

+#define FDCAN_IE_RF0FE_Pos        (2U)

+#define FDCAN_IE_RF0FE_Msk        (0x1UL << FDCAN_IE_RF0FE_Pos)                /*!< 0x00000004 */

+#define FDCAN_IE_RF0FE            FDCAN_IE_RF0FE_Msk                           /*!<Rx FIFO 0 Full Enable                        */

+#define FDCAN_IE_RF0LE_Pos        (3U)

+#define FDCAN_IE_RF0LE_Msk        (0x1UL << FDCAN_IE_RF0LE_Pos)                /*!< 0x00000008 */

+#define FDCAN_IE_RF0LE            FDCAN_IE_RF0LE_Msk                           /*!<Rx FIFO 0 Message Lost Enable                */

+#define FDCAN_IE_RF1NE_Pos        (4U)

+#define FDCAN_IE_RF1NE_Msk        (0x1UL << FDCAN_IE_RF1NE_Pos)                /*!< 0x00000010 */

+#define FDCAN_IE_RF1NE            FDCAN_IE_RF1NE_Msk                           /*!<Rx FIFO 1 New Message Enable                 */

+#define FDCAN_IE_RF1WE_Pos        (5U)

+#define FDCAN_IE_RF1WE_Msk        (0x1UL << FDCAN_IE_RF1WE_Pos)                /*!< 0x00000020 */

+#define FDCAN_IE_RF1WE            FDCAN_IE_RF1WE_Msk                           /*!<Rx FIFO 1 Watermark Reached Enable           */

+#define FDCAN_IE_RF1FE_Pos        (6U)

+#define FDCAN_IE_RF1FE_Msk        (0x1UL << FDCAN_IE_RF1FE_Pos)                /*!< 0x00000040 */

+#define FDCAN_IE_RF1FE            FDCAN_IE_RF1FE_Msk                           /*!<Rx FIFO 1 Full Enable                        */

+#define FDCAN_IE_RF1LE_Pos        (7U)

+#define FDCAN_IE_RF1LE_Msk        (0x1UL << FDCAN_IE_RF1LE_Pos)                /*!< 0x00000080 */

+#define FDCAN_IE_RF1LE            FDCAN_IE_RF1LE_Msk                           /*!<Rx FIFO 1 Message Lost Enable                */

+#define FDCAN_IE_HPME_Pos         (8U)

+#define FDCAN_IE_HPME_Msk         (0x1UL << FDCAN_IE_HPME_Pos)                 /*!< 0x00000100 */

+#define FDCAN_IE_HPME             FDCAN_IE_HPME_Msk                            /*!<High Priority Message Enable                 */

+#define FDCAN_IE_TCE_Pos          (9U)

+#define FDCAN_IE_TCE_Msk          (0x1UL << FDCAN_IE_TCE_Pos)                  /*!< 0x00000200 */

+#define FDCAN_IE_TCE              FDCAN_IE_TCE_Msk                             /*!<Transmission Completed Enable                */

+#define FDCAN_IE_TCFE_Pos         (10U)

+#define FDCAN_IE_TCFE_Msk         (0x1UL << FDCAN_IE_TCFE_Pos)                 /*!< 0x00000400 */

+#define FDCAN_IE_TCFE             FDCAN_IE_TCFE_Msk                            /*!<Transmission Cancellation Finished Enable    */

+#define FDCAN_IE_TFEE_Pos         (11U)

+#define FDCAN_IE_TFEE_Msk         (0x1UL << FDCAN_IE_TFEE_Pos)                 /*!< 0x00000800 */

+#define FDCAN_IE_TFEE             FDCAN_IE_TFEE_Msk                            /*!<Tx FIFO Empty Enable                         */

+#define FDCAN_IE_TEFNE_Pos        (12U)

+#define FDCAN_IE_TEFNE_Msk        (0x1UL << FDCAN_IE_TEFNE_Pos)                /*!< 0x00001000 */

+#define FDCAN_IE_TEFNE            FDCAN_IE_TEFNE_Msk                           /*!<Tx Event FIFO New Entry Enable               */

+#define FDCAN_IE_TEFWE_Pos        (13U)

+#define FDCAN_IE_TEFWE_Msk        (0x1UL << FDCAN_IE_TEFWE_Pos)                /*!< 0x00002000 */

+#define FDCAN_IE_TEFWE            FDCAN_IE_TEFWE_Msk                           /*!<Tx Event FIFO Watermark Reached Enable       */

+#define FDCAN_IE_TEFFE_Pos        (14U)

+#define FDCAN_IE_TEFFE_Msk        (0x1UL << FDCAN_IE_TEFFE_Pos)                /*!< 0x00004000 */

+#define FDCAN_IE_TEFFE            FDCAN_IE_TEFFE_Msk                           /*!<Tx Event FIFO Full Enable                    */

+#define FDCAN_IE_TEFLE_Pos        (15U)

+#define FDCAN_IE_TEFLE_Msk        (0x1UL << FDCAN_IE_TEFLE_Pos)                /*!< 0x00008000 */

+#define FDCAN_IE_TEFLE            FDCAN_IE_TEFLE_Msk                           /*!<Tx Event FIFO Element Lost Enable            */

+#define FDCAN_IE_TSWE_Pos         (16U)

+#define FDCAN_IE_TSWE_Msk         (0x1UL << FDCAN_IE_TSWE_Pos)                 /*!< 0x00010000 */

+#define FDCAN_IE_TSWE             FDCAN_IE_TSWE_Msk                            /*!<Timestamp Wraparound Enable                  */

+#define FDCAN_IE_MRAFE_Pos        (17U)

+#define FDCAN_IE_MRAFE_Msk        (0x1UL << FDCAN_IE_MRAFE_Pos)                /*!< 0x00020000 */

+#define FDCAN_IE_MRAFE            FDCAN_IE_MRAFE_Msk                           /*!<Message RAM Access Failure Enable            */

+#define FDCAN_IE_TOOE_Pos         (18U)

+#define FDCAN_IE_TOOE_Msk         (0x1UL << FDCAN_IE_TOOE_Pos)                 /*!< 0x00040000 */

+#define FDCAN_IE_TOOE             FDCAN_IE_TOOE_Msk                            /*!<Timeout Occurred Enable                      */

+#define FDCAN_IE_DRXE_Pos         (19U)

+#define FDCAN_IE_DRXE_Msk         (0x1UL << FDCAN_IE_DRXE_Pos)                 /*!< 0x00080000 */

+#define FDCAN_IE_DRXE             FDCAN_IE_DRXE_Msk                            /*!<Message stored to Dedicated Rx Buffer Enable */

+#define FDCAN_IE_BECE_Pos         (20U)

+#define FDCAN_IE_BECE_Msk         (0x1UL << FDCAN_IE_BECE_Pos)                 /*!< 0x00100000 */

+#define FDCAN_IE_BECE             FDCAN_IE_BECE_Msk                            /*!<Bit Error Corrected Interrupt Enable         */

+#define FDCAN_IE_BEUE_Pos         (21U)

+#define FDCAN_IE_BEUE_Msk         (0x1UL << FDCAN_IE_BEUE_Pos)                 /*!< 0x00200000 */

+#define FDCAN_IE_BEUE             FDCAN_IE_BEUE_Msk                            /*!<Bit Error Uncorrected Interrupt Enable       */

+#define FDCAN_IE_ELOE_Pos         (22U)

+#define FDCAN_IE_ELOE_Msk         (0x1UL << FDCAN_IE_ELOE_Pos)                 /*!< 0x00400000 */

+#define FDCAN_IE_ELOE             FDCAN_IE_ELOE_Msk                            /*!<Error Logging Overflow Enable                */

+#define FDCAN_IE_EPE_Pos          (23U)

+#define FDCAN_IE_EPE_Msk          (0x1UL << FDCAN_IE_EPE_Pos)                  /*!< 0x00800000 */

+#define FDCAN_IE_EPE              FDCAN_IE_EPE_Msk                             /*!<Error Passive Enable                         */

+#define FDCAN_IE_EWE_Pos          (24U)

+#define FDCAN_IE_EWE_Msk          (0x1UL << FDCAN_IE_EWE_Pos)                  /*!< 0x01000000 */

+#define FDCAN_IE_EWE              FDCAN_IE_EWE_Msk                             /*!<Warning Status Enable                        */

+#define FDCAN_IE_BOE_Pos          (25U)

+#define FDCAN_IE_BOE_Msk          (0x1UL << FDCAN_IE_BOE_Pos)                  /*!< 0x02000000 */

+#define FDCAN_IE_BOE              FDCAN_IE_BOE_Msk                             /*!<Bus_Off Status Enable                        */

+#define FDCAN_IE_WDIE_Pos         (26U)

+#define FDCAN_IE_WDIE_Msk         (0x1UL << FDCAN_IE_WDIE_Pos)                 /*!< 0x04000000 */

+#define FDCAN_IE_WDIE             FDCAN_IE_WDIE_Msk                            /*!<Watchdog Interrupt Enable                    */

+#define FDCAN_IE_PEAE_Pos         (27U)

+#define FDCAN_IE_PEAE_Msk         (0x1UL << FDCAN_IE_PEAE_Pos)                 /*!< 0x08000000 */

+#define FDCAN_IE_PEAE             FDCAN_IE_PEAE_Msk                            /*!<Protocol Error in Arbitration Phase Enable   */

+#define FDCAN_IE_PEDE_Pos         (28U)

+#define FDCAN_IE_PEDE_Msk         (0x1UL << FDCAN_IE_PEDE_Pos)                 /*!< 0x10000000 */

+#define FDCAN_IE_PEDE             FDCAN_IE_PEDE_Msk                            /*!<Protocol Error in Data Phase Enable          */

+#define FDCAN_IE_ARAE_Pos         (29U)

+#define FDCAN_IE_ARAE_Msk         (0x1UL << FDCAN_IE_ARAE_Pos)                 /*!< 0x20000000 */

+#define FDCAN_IE_ARAE             FDCAN_IE_ARAE_Msk                            /*!<Access to Reserved Address Enable            */

+

+/*****************  Bit definition for FDCAN_ILS register  **********************/

+#define FDCAN_ILS_RF0NL_Pos       (0U)

+#define FDCAN_ILS_RF0NL_Msk       (0x1UL << FDCAN_ILS_RF0NL_Pos)               /*!< 0x00000001 */

+#define FDCAN_ILS_RF0NL           FDCAN_ILS_RF0NL_Msk                          /*!<Rx FIFO 0 New Message Line                  */

+#define FDCAN_ILS_RF0WL_Pos       (1U)

+#define FDCAN_ILS_RF0WL_Msk       (0x1UL << FDCAN_ILS_RF0WL_Pos)               /*!< 0x00000002 */

+#define FDCAN_ILS_RF0WL           FDCAN_ILS_RF0WL_Msk                          /*!<Rx FIFO 0 Watermark Reached Line            */

+#define FDCAN_ILS_RF0FL_Pos       (2U)

+#define FDCAN_ILS_RF0FL_Msk       (0x1UL << FDCAN_ILS_RF0FL_Pos)               /*!< 0x00000004 */

+#define FDCAN_ILS_RF0FL           FDCAN_ILS_RF0FL_Msk                          /*!<Rx FIFO 0 Full Line                         */

+#define FDCAN_ILS_RF0LL_Pos       (3U)

+#define FDCAN_ILS_RF0LL_Msk       (0x1UL << FDCAN_ILS_RF0LL_Pos)               /*!< 0x00000008 */

+#define FDCAN_ILS_RF0LL           FDCAN_ILS_RF0LL_Msk                          /*!<Rx FIFO 0 Message Lost Line                 */

+#define FDCAN_ILS_RF1NL_Pos       (4U)

+#define FDCAN_ILS_RF1NL_Msk       (0x1UL << FDCAN_ILS_RF1NL_Pos)               /*!< 0x00000010 */

+#define FDCAN_ILS_RF1NL           FDCAN_ILS_RF1NL_Msk                          /*!<Rx FIFO 1 New Message Line                  */

+#define FDCAN_ILS_RF1WL_Pos       (5U)

+#define FDCAN_ILS_RF1WL_Msk       (0x1UL << FDCAN_ILS_RF1WL_Pos)               /*!< 0x00000020 */

+#define FDCAN_ILS_RF1WL           FDCAN_ILS_RF1WL_Msk                          /*!<Rx FIFO 1 Watermark Reached Line            */

+#define FDCAN_ILS_RF1FL_Pos       (6U)

+#define FDCAN_ILS_RF1FL_Msk       (0x1UL << FDCAN_ILS_RF1FL_Pos)               /*!< 0x00000040 */

+#define FDCAN_ILS_RF1FL           FDCAN_ILS_RF1FL_Msk                          /*!<Rx FIFO 1 Full Line                         */

+#define FDCAN_ILS_RF1LL_Pos       (7U)

+#define FDCAN_ILS_RF1LL_Msk       (0x1UL << FDCAN_ILS_RF1LL_Pos)               /*!< 0x00000080 */

+#define FDCAN_ILS_RF1LL           FDCAN_ILS_RF1LL_Msk                          /*!<Rx FIFO 1 Message Lost Line                 */

+#define FDCAN_ILS_HPML_Pos        (8U)

+#define FDCAN_ILS_HPML_Msk        (0x1UL << FDCAN_ILS_HPML_Pos)                /*!< 0x00000100 */

+#define FDCAN_ILS_HPML            FDCAN_ILS_HPML_Msk                           /*!<High Priority Message Line                  */

+#define FDCAN_ILS_TCL_Pos         (9U)

+#define FDCAN_ILS_TCL_Msk         (0x1UL << FDCAN_ILS_TCL_Pos)                 /*!< 0x00000200 */

+#define FDCAN_ILS_TCL             FDCAN_ILS_TCL_Msk                            /*!<Transmission Completed Line                 */

+#define FDCAN_ILS_TCFL_Pos        (10U)

+#define FDCAN_ILS_TCFL_Msk        (0x1UL << FDCAN_ILS_TCFL_Pos)                /*!< 0x00000400 */

+#define FDCAN_ILS_TCFL            FDCAN_ILS_TCFL_Msk                           /*!<Transmission Cancellation Finished Line     */

+#define FDCAN_ILS_TFEL_Pos        (11U)

+#define FDCAN_ILS_TFEL_Msk        (0x1UL << FDCAN_ILS_TFEL_Pos)                /*!< 0x00000800 */

+#define FDCAN_ILS_TFEL            FDCAN_ILS_TFEL_Msk                           /*!<Tx FIFO Empty Line                          */

+#define FDCAN_ILS_TEFNL_Pos       (12U)

+#define FDCAN_ILS_TEFNL_Msk       (0x1UL << FDCAN_ILS_TEFNL_Pos)               /*!< 0x00001000 */

+#define FDCAN_ILS_TEFNL           FDCAN_ILS_TEFNL_Msk                          /*!<Tx Event FIFO New Entry Line                */

+#define FDCAN_ILS_TEFWL_Pos       (13U)

+#define FDCAN_ILS_TEFWL_Msk       (0x1UL << FDCAN_ILS_TEFWL_Pos)               /*!< 0x00002000 */

+#define FDCAN_ILS_TEFWL           FDCAN_ILS_TEFWL_Msk                          /*!<Tx Event FIFO Watermark Reached Line        */

+#define FDCAN_ILS_TEFFL_Pos       (14U)

+#define FDCAN_ILS_TEFFL_Msk       (0x1UL << FDCAN_ILS_TEFFL_Pos)               /*!< 0x00004000 */

+#define FDCAN_ILS_TEFFL           FDCAN_ILS_TEFFL_Msk                          /*!<Tx Event FIFO Full Line                     */

+#define FDCAN_ILS_TEFLL_Pos       (15U)

+#define FDCAN_ILS_TEFLL_Msk       (0x1UL << FDCAN_ILS_TEFLL_Pos)               /*!< 0x00008000 */

+#define FDCAN_ILS_TEFLL           FDCAN_ILS_TEFLL_Msk                          /*!<Tx Event FIFO Element Lost Line             */

+#define FDCAN_ILS_TSWL_Pos        (16U)

+#define FDCAN_ILS_TSWL_Msk        (0x1UL << FDCAN_ILS_TSWL_Pos)                /*!< 0x00010000 */

+#define FDCAN_ILS_TSWL            FDCAN_ILS_TSWL_Msk                           /*!<Timestamp Wraparound Line                   */

+#define FDCAN_ILS_MRAFE_Pos       (17U)

+#define FDCAN_ILS_MRAFE_Msk       (0x1UL << FDCAN_ILS_MRAFE_Pos)               /*!< 0x00020000 */

+#define FDCAN_ILS_MRAFE           FDCAN_ILS_MRAFE_Msk                          /*!<Message RAM Access Failure Line             */

+#define FDCAN_ILS_TOOE_Pos        (18U)

+#define FDCAN_ILS_TOOE_Msk        (0x1UL << FDCAN_ILS_TOOE_Pos)                /*!< 0x00040000 */

+#define FDCAN_ILS_TOOE            FDCAN_ILS_TOOE_Msk                           /*!<Timeout Occurred Line                       */

+#define FDCAN_ILS_DRXE_Pos        (19U)

+#define FDCAN_ILS_DRXE_Msk        (0x1UL << FDCAN_ILS_DRXE_Pos)                /*!< 0x00080000 */

+#define FDCAN_ILS_DRXE            FDCAN_ILS_DRXE_Msk                           /*!<Message stored to Dedicated Rx Buffer Line  */

+#define FDCAN_ILS_BECE_Pos        (20U)

+#define FDCAN_ILS_BECE_Msk        (0x1UL << FDCAN_ILS_BECE_Pos)                /*!< 0x00100000 */

+#define FDCAN_ILS_BECE            FDCAN_ILS_BECE_Msk                           /*!<Bit Error Corrected Interrupt Line          */

+#define FDCAN_ILS_BEUE_Pos        (21U)

+#define FDCAN_ILS_BEUE_Msk        (0x1UL << FDCAN_ILS_BEUE_Pos)                /*!< 0x00200000 */

+#define FDCAN_ILS_BEUE            FDCAN_ILS_BEUE_Msk                           /*!<Bit Error Uncorrected Interrupt Line        */

+#define FDCAN_ILS_ELOE_Pos        (22U)

+#define FDCAN_ILS_ELOE_Msk        (0x1UL << FDCAN_ILS_ELOE_Pos)                /*!< 0x00400000 */

+#define FDCAN_ILS_ELOE            FDCAN_ILS_ELOE_Msk                           /*!<Error Logging Overflow Line                 */

+#define FDCAN_ILS_EPE_Pos         (23U)

+#define FDCAN_ILS_EPE_Msk         (0x1UL << FDCAN_ILS_EPE_Pos)                 /*!< 0x00800000 */

+#define FDCAN_ILS_EPE             FDCAN_ILS_EPE_Msk                            /*!<Error Passive Line                          */

+#define FDCAN_ILS_EWE_Pos         (24U)

+#define FDCAN_ILS_EWE_Msk         (0x1UL << FDCAN_ILS_EWE_Pos)                 /*!< 0x01000000 */

+#define FDCAN_ILS_EWE             FDCAN_ILS_EWE_Msk                            /*!<Warning Status Line                         */

+#define FDCAN_ILS_BOE_Pos         (25U)

+#define FDCAN_ILS_BOE_Msk         (0x1UL << FDCAN_ILS_BOE_Pos)                 /*!< 0x02000000 */

+#define FDCAN_ILS_BOE             FDCAN_ILS_BOE_Msk                            /*!<Bus_Off Status Line                         */

+#define FDCAN_ILS_WDIE_Pos        (26U)

+#define FDCAN_ILS_WDIE_Msk        (0x1UL << FDCAN_ILS_WDIE_Pos)                /*!< 0x04000000 */

+#define FDCAN_ILS_WDIE            FDCAN_ILS_WDIE_Msk                           /*!<Watchdog Interrupt Line                     */

+#define FDCAN_ILS_PEAE_Pos        (27U)

+#define FDCAN_ILS_PEAE_Msk        (0x1UL << FDCAN_ILS_PEAE_Pos)                /*!< 0x08000000 */

+#define FDCAN_ILS_PEAE            FDCAN_ILS_PEAE_Msk                           /*!<Protocol Error in Arbitration Phase Line    */

+#define FDCAN_ILS_PEDE_Pos        (28U)

+#define FDCAN_ILS_PEDE_Msk        (0x1UL << FDCAN_ILS_PEDE_Pos)                /*!< 0x10000000 */

+#define FDCAN_ILS_PEDE            FDCAN_ILS_PEDE_Msk                           /*!<Protocol Error in Data Phase Line           */

+#define FDCAN_ILS_ARAE_Pos        (29U)

+#define FDCAN_ILS_ARAE_Msk        (0x1UL << FDCAN_ILS_ARAE_Pos)                /*!< 0x20000000 */

+#define FDCAN_ILS_ARAE            FDCAN_ILS_ARAE_Msk                           /*!<Access to Reserved Address Line             */

+

+/*****************  Bit definition for FDCAN_ILE register  **********************/

+#define FDCAN_ILE_EINT0_Pos       (0U)

+#define FDCAN_ILE_EINT0_Msk       (0x1UL << FDCAN_ILE_EINT0_Pos)               /*!< 0x00000001 */

+#define FDCAN_ILE_EINT0           FDCAN_ILE_EINT0_Msk                          /*!<Enable Interrupt Line 0                   */

+#define FDCAN_ILE_EINT1_Pos       (1U)

+#define FDCAN_ILE_EINT1_Msk       (0x1UL << FDCAN_ILE_EINT1_Pos)               /*!< 0x00000002 */

+#define FDCAN_ILE_EINT1           FDCAN_ILE_EINT1_Msk                          /*!<Enable Interrupt Line 1                   */

+

+/*****************  Bit definition for FDCAN_GFC register  **********************/

+#define FDCAN_GFC_RRFE_Pos        (0U)

+#define FDCAN_GFC_RRFE_Msk        (0x1UL << FDCAN_GFC_RRFE_Pos)                /*!< 0x00000001 */

+#define FDCAN_GFC_RRFE            FDCAN_GFC_RRFE_Msk                           /*!<Reject Remote Frames Extended             */

+#define FDCAN_GFC_RRFS_Pos        (1U)

+#define FDCAN_GFC_RRFS_Msk        (0x1UL << FDCAN_GFC_RRFS_Pos)                /*!< 0x00000002 */

+#define FDCAN_GFC_RRFS            FDCAN_GFC_RRFS_Msk                           /*!<Reject Remote Frames Standard             */

+#define FDCAN_GFC_ANFE_Pos        (2U)

+#define FDCAN_GFC_ANFE_Msk        (0x3UL << FDCAN_GFC_ANFE_Pos)                /*!< 0x0000000C */

+#define FDCAN_GFC_ANFE            FDCAN_GFC_ANFE_Msk                           /*!<Accept Non-matching Frames Extended       */

+#define FDCAN_GFC_ANFS_Pos        (4U)

+#define FDCAN_GFC_ANFS_Msk        (0x3UL << FDCAN_GFC_ANFS_Pos)                /*!< 0x00000030 */

+#define FDCAN_GFC_ANFS            FDCAN_GFC_ANFS_Msk                           /*!<Accept Non-matching Frames Standard       */

+

+/*****************  Bit definition for FDCAN_SIDFC register  ********************/

+#define FDCAN_SIDFC_FLSSA_Pos     (2U)

+#define FDCAN_SIDFC_FLSSA_Msk     (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)          /*!< 0x0000FFFC */

+#define FDCAN_SIDFC_FLSSA         FDCAN_SIDFC_FLSSA_Msk                        /*!<Filter List Standard Start Address        */

+#define FDCAN_SIDFC_LSS_Pos       (16U)

+#define FDCAN_SIDFC_LSS_Msk       (0xFFUL << FDCAN_SIDFC_LSS_Pos)              /*!< 0x00FF0000 */

+#define FDCAN_SIDFC_LSS           FDCAN_SIDFC_LSS_Msk                          /*!<List Size Standard                        */

+

+/*****************  Bit definition for FDCAN_XIDFC register  ********************/

+#define FDCAN_XIDFC_FLESA_Pos     (2U)

+#define FDCAN_XIDFC_FLESA_Msk     (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)          /*!< 0x0000FFFC */

+#define FDCAN_XIDFC_FLESA         FDCAN_XIDFC_FLESA_Msk                        /*!<Filter List Standard Start Address        */

+#define FDCAN_XIDFC_LSE_Pos       (16U)

+#define FDCAN_XIDFC_LSE_Msk       (0x7FUL << FDCAN_XIDFC_LSE_Pos)              /*!< 0x007F0000 */

+#define FDCAN_XIDFC_LSE           FDCAN_XIDFC_LSE_Msk                          /*!<List Size Extended                        */

+

+/*****************  Bit definition for FDCAN_XIDAM register  ********************/

+#define FDCAN_XIDAM_EIDM_Pos      (0U)

+#define FDCAN_XIDAM_EIDM_Msk      (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)       /*!< 0x1FFFFFFF */

+#define FDCAN_XIDAM_EIDM          FDCAN_XIDAM_EIDM_Msk                         /*!<Extended ID Mask                          */

+

+/*****************  Bit definition for FDCAN_HPMS register  *********************/

+#define FDCAN_HPMS_BIDX_Pos       (0U)

+#define FDCAN_HPMS_BIDX_Msk       (0x3FUL << FDCAN_HPMS_BIDX_Pos)              /*!< 0x0000003F */

+#define FDCAN_HPMS_BIDX           FDCAN_HPMS_BIDX_Msk                          /*!<Buffer Index                              */

+#define FDCAN_HPMS_MSI_Pos        (6U)

+#define FDCAN_HPMS_MSI_Msk        (0x3UL << FDCAN_HPMS_MSI_Pos)                /*!< 0x000000C0 */

+#define FDCAN_HPMS_MSI            FDCAN_HPMS_MSI_Msk                           /*!<Message Storage Indicator                 */

+#define FDCAN_HPMS_FIDX_Pos       (8U)

+#define FDCAN_HPMS_FIDX_Msk       (0x7FUL << FDCAN_HPMS_FIDX_Pos)              /*!< 0x00007F00 */

+#define FDCAN_HPMS_FIDX           FDCAN_HPMS_FIDX_Msk                          /*!<Filter Index                              */

+#define FDCAN_HPMS_FLST_Pos       (15U)

+#define FDCAN_HPMS_FLST_Msk       (0x1UL << FDCAN_HPMS_FLST_Pos)               /*!< 0x00008000 */

+#define FDCAN_HPMS_FLST           FDCAN_HPMS_FLST_Msk                          /*!<Filter List                               */

+

+/*****************  Bit definition for FDCAN_NDAT1 register  ********************/

+#define FDCAN_NDAT1_ND0_Pos       (0U)

+#define FDCAN_NDAT1_ND0_Msk       (0x1UL << FDCAN_NDAT1_ND0_Pos)               /*!< 0x00000001 */

+#define FDCAN_NDAT1_ND0           FDCAN_NDAT1_ND0_Msk                          /*!<New Data flag of Rx Buffer 0              */

+#define FDCAN_NDAT1_ND1_Pos       (1U)

+#define FDCAN_NDAT1_ND1_Msk       (0x1UL << FDCAN_NDAT1_ND1_Pos)               /*!< 0x00000002 */

+#define FDCAN_NDAT1_ND1           FDCAN_NDAT1_ND1_Msk                          /*!<New Data flag of Rx Buffer 1              */

+#define FDCAN_NDAT1_ND2_Pos       (2U)

+#define FDCAN_NDAT1_ND2_Msk       (0x1UL << FDCAN_NDAT1_ND2_Pos)               /*!< 0x00000004 */

+#define FDCAN_NDAT1_ND2           FDCAN_NDAT1_ND2_Msk                          /*!<New Data flag of Rx Buffer 2              */

+#define FDCAN_NDAT1_ND3_Pos       (3U)

+#define FDCAN_NDAT1_ND3_Msk       (0x1UL << FDCAN_NDAT1_ND3_Pos)               /*!< 0x00000008 */

+#define FDCAN_NDAT1_ND3           FDCAN_NDAT1_ND3_Msk                          /*!<New Data flag of Rx Buffer 3              */

+#define FDCAN_NDAT1_ND4_Pos       (4U)

+#define FDCAN_NDAT1_ND4_Msk       (0x1UL << FDCAN_NDAT1_ND4_Pos)               /*!< 0x00000010 */

+#define FDCAN_NDAT1_ND4           FDCAN_NDAT1_ND4_Msk                          /*!<New Data flag of Rx Buffer 4              */

+#define FDCAN_NDAT1_ND5_Pos       (5U)

+#define FDCAN_NDAT1_ND5_Msk       (0x1UL << FDCAN_NDAT1_ND5_Pos)               /*!< 0x00000020 */

+#define FDCAN_NDAT1_ND5           FDCAN_NDAT1_ND5_Msk                          /*!<New Data flag of Rx Buffer 5              */

+#define FDCAN_NDAT1_ND6_Pos       (6U)

+#define FDCAN_NDAT1_ND6_Msk       (0x1UL << FDCAN_NDAT1_ND6_Pos)               /*!< 0x00000040 */

+#define FDCAN_NDAT1_ND6           FDCAN_NDAT1_ND6_Msk                          /*!<New Data flag of Rx Buffer 6              */

+#define FDCAN_NDAT1_ND7_Pos       (7U)

+#define FDCAN_NDAT1_ND7_Msk       (0x1UL << FDCAN_NDAT1_ND7_Pos)               /*!< 0x00000080 */

+#define FDCAN_NDAT1_ND7           FDCAN_NDAT1_ND7_Msk                          /*!<New Data flag of Rx Buffer 7              */

+#define FDCAN_NDAT1_ND8_Pos       (8U)

+#define FDCAN_NDAT1_ND8_Msk       (0x1UL << FDCAN_NDAT1_ND8_Pos)               /*!< 0x00000100 */

+#define FDCAN_NDAT1_ND8           FDCAN_NDAT1_ND8_Msk                          /*!<New Data flag of Rx Buffer 8              */

+#define FDCAN_NDAT1_ND9_Pos       (9U)

+#define FDCAN_NDAT1_ND9_Msk       (0x1UL << FDCAN_NDAT1_ND9_Pos)               /*!< 0x00000200 */

+#define FDCAN_NDAT1_ND9           FDCAN_NDAT1_ND9_Msk                          /*!<New Data flag of Rx Buffer 9              */

+#define FDCAN_NDAT1_ND10_Pos      (10U)

+#define FDCAN_NDAT1_ND10_Msk      (0x1UL << FDCAN_NDAT1_ND10_Pos)              /*!< 0x00000400 */

+#define FDCAN_NDAT1_ND10          FDCAN_NDAT1_ND10_Msk                         /*!<New Data flag of Rx Buffer 10             */

+#define FDCAN_NDAT1_ND11_Pos      (11U)

+#define FDCAN_NDAT1_ND11_Msk      (0x1UL << FDCAN_NDAT1_ND11_Pos)              /*!< 0x00000800 */

+#define FDCAN_NDAT1_ND11          FDCAN_NDAT1_ND11_Msk                         /*!<New Data flag of Rx Buffer 11             */

+#define FDCAN_NDAT1_ND12_Pos      (12U)

+#define FDCAN_NDAT1_ND12_Msk      (0x1UL << FDCAN_NDAT1_ND12_Pos)              /*!< 0x00001000 */

+#define FDCAN_NDAT1_ND12          FDCAN_NDAT1_ND12_Msk                         /*!<New Data flag of Rx Buffer 12             */

+#define FDCAN_NDAT1_ND13_Pos      (13U)

+#define FDCAN_NDAT1_ND13_Msk      (0x1UL << FDCAN_NDAT1_ND13_Pos)              /*!< 0x00002000 */

+#define FDCAN_NDAT1_ND13          FDCAN_NDAT1_ND13_Msk                         /*!<New Data flag of Rx Buffer 13             */

+#define FDCAN_NDAT1_ND14_Pos      (14U)

+#define FDCAN_NDAT1_ND14_Msk      (0x1UL << FDCAN_NDAT1_ND14_Pos)              /*!< 0x00004000 */

+#define FDCAN_NDAT1_ND14          FDCAN_NDAT1_ND14_Msk                         /*!<New Data flag of Rx Buffer 14             */

+#define FDCAN_NDAT1_ND15_Pos      (15U)

+#define FDCAN_NDAT1_ND15_Msk      (0x1UL << FDCAN_NDAT1_ND15_Pos)              /*!< 0x00008000 */

+#define FDCAN_NDAT1_ND15          FDCAN_NDAT1_ND15_Msk                         /*!<New Data flag of Rx Buffer 15             */

+#define FDCAN_NDAT1_ND16_Pos      (16U)

+#define FDCAN_NDAT1_ND16_Msk      (0x1UL << FDCAN_NDAT1_ND16_Pos)              /*!< 0x00010000 */

+#define FDCAN_NDAT1_ND16          FDCAN_NDAT1_ND16_Msk                         /*!<New Data flag of Rx Buffer 16             */

+#define FDCAN_NDAT1_ND17_Pos      (17U)

+#define FDCAN_NDAT1_ND17_Msk      (0x1UL << FDCAN_NDAT1_ND17_Pos)              /*!< 0x00020000 */

+#define FDCAN_NDAT1_ND17          FDCAN_NDAT1_ND17_Msk                         /*!<New Data flag of Rx Buffer 17             */

+#define FDCAN_NDAT1_ND18_Pos      (18U)

+#define FDCAN_NDAT1_ND18_Msk      (0x1UL << FDCAN_NDAT1_ND18_Pos)              /*!< 0x00040000 */

+#define FDCAN_NDAT1_ND18          FDCAN_NDAT1_ND18_Msk                         /*!<New Data flag of Rx Buffer 18             */

+#define FDCAN_NDAT1_ND19_Pos      (19U)

+#define FDCAN_NDAT1_ND19_Msk      (0x1UL << FDCAN_NDAT1_ND19_Pos)              /*!< 0x00080000 */

+#define FDCAN_NDAT1_ND19          FDCAN_NDAT1_ND19_Msk                         /*!<New Data flag of Rx Buffer 19             */

+#define FDCAN_NDAT1_ND20_Pos      (20U)

+#define FDCAN_NDAT1_ND20_Msk      (0x1UL << FDCAN_NDAT1_ND20_Pos)              /*!< 0x00100000 */

+#define FDCAN_NDAT1_ND20          FDCAN_NDAT1_ND20_Msk                         /*!<New Data flag of Rx Buffer 20             */

+#define FDCAN_NDAT1_ND21_Pos      (21U)

+#define FDCAN_NDAT1_ND21_Msk      (0x1UL << FDCAN_NDAT1_ND21_Pos)              /*!< 0x00200000 */

+#define FDCAN_NDAT1_ND21          FDCAN_NDAT1_ND21_Msk                         /*!<New Data flag of Rx Buffer 21             */

+#define FDCAN_NDAT1_ND22_Pos      (22U)

+#define FDCAN_NDAT1_ND22_Msk      (0x1UL << FDCAN_NDAT1_ND22_Pos)              /*!< 0x00400000 */

+#define FDCAN_NDAT1_ND22          FDCAN_NDAT1_ND22_Msk                         /*!<New Data flag of Rx Buffer 22             */

+#define FDCAN_NDAT1_ND23_Pos      (23U)

+#define FDCAN_NDAT1_ND23_Msk      (0x1UL << FDCAN_NDAT1_ND23_Pos)              /*!< 0x00800000 */

+#define FDCAN_NDAT1_ND23          FDCAN_NDAT1_ND23_Msk                         /*!<New Data flag of Rx Buffer 23             */

+#define FDCAN_NDAT1_ND24_Pos      (24U)

+#define FDCAN_NDAT1_ND24_Msk      (0x1UL << FDCAN_NDAT1_ND24_Pos)              /*!< 0x01000000 */

+#define FDCAN_NDAT1_ND24          FDCAN_NDAT1_ND24_Msk                         /*!<New Data flag of Rx Buffer 24             */

+#define FDCAN_NDAT1_ND25_Pos      (25U)

+#define FDCAN_NDAT1_ND25_Msk      (0x1UL << FDCAN_NDAT1_ND25_Pos)              /*!< 0x02000000 */

+#define FDCAN_NDAT1_ND25          FDCAN_NDAT1_ND25_Msk                         /*!<New Data flag of Rx Buffer 25             */

+#define FDCAN_NDAT1_ND26_Pos      (26U)

+#define FDCAN_NDAT1_ND26_Msk      (0x1UL << FDCAN_NDAT1_ND26_Pos)              /*!< 0x04000000 */

+#define FDCAN_NDAT1_ND26          FDCAN_NDAT1_ND26_Msk                         /*!<New Data flag of Rx Buffer 26             */

+#define FDCAN_NDAT1_ND27_Pos      (27U)

+#define FDCAN_NDAT1_ND27_Msk      (0x1UL << FDCAN_NDAT1_ND27_Pos)              /*!< 0x08000000 */

+#define FDCAN_NDAT1_ND27          FDCAN_NDAT1_ND27_Msk                         /*!<New Data flag of Rx Buffer 27             */

+#define FDCAN_NDAT1_ND28_Pos      (28U)

+#define FDCAN_NDAT1_ND28_Msk      (0x1UL << FDCAN_NDAT1_ND28_Pos)              /*!< 0x10000000 */

+#define FDCAN_NDAT1_ND28          FDCAN_NDAT1_ND28_Msk                         /*!<New Data flag of Rx Buffer 28             */

+#define FDCAN_NDAT1_ND29_Pos      (29U)

+#define FDCAN_NDAT1_ND29_Msk      (0x1UL << FDCAN_NDAT1_ND29_Pos)              /*!< 0x20000000 */

+#define FDCAN_NDAT1_ND29          FDCAN_NDAT1_ND29_Msk                         /*!<New Data flag of Rx Buffer 29             */

+#define FDCAN_NDAT1_ND30_Pos      (30U)

+#define FDCAN_NDAT1_ND30_Msk      (0x1UL << FDCAN_NDAT1_ND30_Pos)              /*!< 0x40000000 */

+#define FDCAN_NDAT1_ND30          FDCAN_NDAT1_ND30_Msk                         /*!<New Data flag of Rx Buffer 30             */

+#define FDCAN_NDAT1_ND31_Pos      (31U)

+#define FDCAN_NDAT1_ND31_Msk      (0x1UL << FDCAN_NDAT1_ND31_Pos)              /*!< 0x80000000 */

+#define FDCAN_NDAT1_ND31          FDCAN_NDAT1_ND31_Msk                         /*!<New Data flag of Rx Buffer 31             */

+

+/*****************  Bit definition for FDCAN_NDAT2 register  ********************/

+#define FDCAN_NDAT2_ND32_Pos      (0U)

+#define FDCAN_NDAT2_ND32_Msk      (0x1UL << FDCAN_NDAT2_ND32_Pos)              /*!< 0x00000001 */

+#define FDCAN_NDAT2_ND32          FDCAN_NDAT2_ND32_Msk                         /*!<New Data flag of Rx Buffer 32             */

+#define FDCAN_NDAT2_ND33_Pos      (1U)

+#define FDCAN_NDAT2_ND33_Msk      (0x1UL << FDCAN_NDAT2_ND33_Pos)              /*!< 0x00000002 */

+#define FDCAN_NDAT2_ND33          FDCAN_NDAT2_ND33_Msk                         /*!<New Data flag of Rx Buffer 33             */

+#define FDCAN_NDAT2_ND34_Pos      (2U)

+#define FDCAN_NDAT2_ND34_Msk      (0x1UL << FDCAN_NDAT2_ND34_Pos)              /*!< 0x00000004 */

+#define FDCAN_NDAT2_ND34          FDCAN_NDAT2_ND34_Msk                         /*!<New Data flag of Rx Buffer 34             */

+#define FDCAN_NDAT2_ND35_Pos      (3U)

+#define FDCAN_NDAT2_ND35_Msk      (0x1UL << FDCAN_NDAT2_ND35_Pos)              /*!< 0x00000008 */

+#define FDCAN_NDAT2_ND35          FDCAN_NDAT2_ND35_Msk                         /*!<New Data flag of Rx Buffer 35             */

+#define FDCAN_NDAT2_ND36_Pos      (4U)

+#define FDCAN_NDAT2_ND36_Msk      (0x1UL << FDCAN_NDAT2_ND36_Pos)              /*!< 0x00000010 */

+#define FDCAN_NDAT2_ND36          FDCAN_NDAT2_ND36_Msk                         /*!<New Data flag of Rx Buffer 36             */

+#define FDCAN_NDAT2_ND37_Pos      (5U)

+#define FDCAN_NDAT2_ND37_Msk      (0x1UL << FDCAN_NDAT2_ND37_Pos)              /*!< 0x00000020 */

+#define FDCAN_NDAT2_ND37          FDCAN_NDAT2_ND37_Msk                         /*!<New Data flag of Rx Buffer 37             */

+#define FDCAN_NDAT2_ND38_Pos      (6U)

+#define FDCAN_NDAT2_ND38_Msk      (0x1UL << FDCAN_NDAT2_ND38_Pos)              /*!< 0x00000040 */

+#define FDCAN_NDAT2_ND38          FDCAN_NDAT2_ND38_Msk                         /*!<New Data flag of Rx Buffer 38             */

+#define FDCAN_NDAT2_ND39_Pos      (7U)

+#define FDCAN_NDAT2_ND39_Msk      (0x1UL << FDCAN_NDAT2_ND39_Pos)              /*!< 0x00000080 */

+#define FDCAN_NDAT2_ND39          FDCAN_NDAT2_ND39_Msk                         /*!<New Data flag of Rx Buffer 39             */

+#define FDCAN_NDAT2_ND40_Pos      (8U)

+#define FDCAN_NDAT2_ND40_Msk      (0x1UL << FDCAN_NDAT2_ND40_Pos)              /*!< 0x00000100 */

+#define FDCAN_NDAT2_ND40          FDCAN_NDAT2_ND40_Msk                         /*!<New Data flag of Rx Buffer 40             */

+#define FDCAN_NDAT2_ND41_Pos      (9U)

+#define FDCAN_NDAT2_ND41_Msk      (0x1UL << FDCAN_NDAT2_ND41_Pos)              /*!< 0x00000200 */

+#define FDCAN_NDAT2_ND41          FDCAN_NDAT2_ND41_Msk                         /*!<New Data flag of Rx Buffer 41             */

+#define FDCAN_NDAT2_ND42_Pos      (10U)

+#define FDCAN_NDAT2_ND42_Msk      (0x1UL << FDCAN_NDAT2_ND42_Pos)              /*!< 0x00000400 */

+#define FDCAN_NDAT2_ND42          FDCAN_NDAT2_ND42_Msk                         /*!<New Data flag of Rx Buffer 42             */

+#define FDCAN_NDAT2_ND43_Pos      (11U)

+#define FDCAN_NDAT2_ND43_Msk      (0x1UL << FDCAN_NDAT2_ND43_Pos)              /*!< 0x00000800 */

+#define FDCAN_NDAT2_ND43          FDCAN_NDAT2_ND43_Msk                         /*!<New Data flag of Rx Buffer 43             */

+#define FDCAN_NDAT2_ND44_Pos      (12U)

+#define FDCAN_NDAT2_ND44_Msk      (0x1UL << FDCAN_NDAT2_ND44_Pos)              /*!< 0x00001000 */

+#define FDCAN_NDAT2_ND44          FDCAN_NDAT2_ND44_Msk                         /*!<New Data flag of Rx Buffer 44             */

+#define FDCAN_NDAT2_ND45_Pos      (13U)

+#define FDCAN_NDAT2_ND45_Msk      (0x1UL << FDCAN_NDAT2_ND45_Pos)              /*!< 0x00002000 */

+#define FDCAN_NDAT2_ND45          FDCAN_NDAT2_ND45_Msk                         /*!<New Data flag of Rx Buffer 45             */

+#define FDCAN_NDAT2_ND46_Pos      (14U)

+#define FDCAN_NDAT2_ND46_Msk      (0x1UL << FDCAN_NDAT2_ND46_Pos)              /*!< 0x00004000 */

+#define FDCAN_NDAT2_ND46          FDCAN_NDAT2_ND46_Msk                         /*!<New Data flag of Rx Buffer 46             */

+#define FDCAN_NDAT2_ND47_Pos      (15U)

+#define FDCAN_NDAT2_ND47_Msk      (0x1UL << FDCAN_NDAT2_ND47_Pos)              /*!< 0x00008000 */

+#define FDCAN_NDAT2_ND47          FDCAN_NDAT2_ND47_Msk                         /*!<New Data flag of Rx Buffer 47             */

+#define FDCAN_NDAT2_ND48_Pos      (16U)

+#define FDCAN_NDAT2_ND48_Msk      (0x1UL << FDCAN_NDAT2_ND48_Pos)              /*!< 0x00010000 */

+#define FDCAN_NDAT2_ND48          FDCAN_NDAT2_ND48_Msk                         /*!<New Data flag of Rx Buffer 48             */

+#define FDCAN_NDAT2_ND49_Pos      (17U)

+#define FDCAN_NDAT2_ND49_Msk      (0x1UL << FDCAN_NDAT2_ND49_Pos)              /*!< 0x00020000 */

+#define FDCAN_NDAT2_ND49          FDCAN_NDAT2_ND49_Msk                         /*!<New Data flag of Rx Buffer 49             */

+#define FDCAN_NDAT2_ND50_Pos      (18U)

+#define FDCAN_NDAT2_ND50_Msk      (0x1UL << FDCAN_NDAT2_ND50_Pos)              /*!< 0x00040000 */

+#define FDCAN_NDAT2_ND50          FDCAN_NDAT2_ND50_Msk                         /*!<New Data flag of Rx Buffer 50             */

+#define FDCAN_NDAT2_ND51_Pos      (19U)

+#define FDCAN_NDAT2_ND51_Msk      (0x1UL << FDCAN_NDAT2_ND51_Pos)              /*!< 0x00080000 */

+#define FDCAN_NDAT2_ND51          FDCAN_NDAT2_ND51_Msk                         /*!<New Data flag of Rx Buffer 51             */

+#define FDCAN_NDAT2_ND52_Pos      (20U)

+#define FDCAN_NDAT2_ND52_Msk      (0x1UL << FDCAN_NDAT2_ND52_Pos)              /*!< 0x00100000 */

+#define FDCAN_NDAT2_ND52          FDCAN_NDAT2_ND52_Msk                         /*!<New Data flag of Rx Buffer 52             */

+#define FDCAN_NDAT2_ND53_Pos      (21U)

+#define FDCAN_NDAT2_ND53_Msk      (0x1UL << FDCAN_NDAT2_ND53_Pos)              /*!< 0x00200000 */

+#define FDCAN_NDAT2_ND53          FDCAN_NDAT2_ND53_Msk                         /*!<New Data flag of Rx Buffer 53             */

+#define FDCAN_NDAT2_ND54_Pos      (22U)

+#define FDCAN_NDAT2_ND54_Msk      (0x1UL << FDCAN_NDAT2_ND54_Pos)              /*!< 0x00400000 */

+#define FDCAN_NDAT2_ND54          FDCAN_NDAT2_ND54_Msk                         /*!<New Data flag of Rx Buffer 54             */

+#define FDCAN_NDAT2_ND55_Pos      (23U)

+#define FDCAN_NDAT2_ND55_Msk      (0x1UL << FDCAN_NDAT2_ND55_Pos)              /*!< 0x00800000 */

+#define FDCAN_NDAT2_ND55          FDCAN_NDAT2_ND55_Msk                         /*!<New Data flag of Rx Buffer 55             */

+#define FDCAN_NDAT2_ND56_Pos      (24U)

+#define FDCAN_NDAT2_ND56_Msk      (0x1UL << FDCAN_NDAT2_ND56_Pos)              /*!< 0x01000000 */

+#define FDCAN_NDAT2_ND56          FDCAN_NDAT2_ND56_Msk                         /*!<New Data flag of Rx Buffer 56             */

+#define FDCAN_NDAT2_ND57_Pos      (25U)

+#define FDCAN_NDAT2_ND57_Msk      (0x1UL << FDCAN_NDAT2_ND57_Pos)              /*!< 0x02000000 */

+#define FDCAN_NDAT2_ND57          FDCAN_NDAT2_ND57_Msk                         /*!<New Data flag of Rx Buffer 57             */

+#define FDCAN_NDAT2_ND58_Pos      (26U)

+#define FDCAN_NDAT2_ND58_Msk      (0x1UL << FDCAN_NDAT2_ND58_Pos)              /*!< 0x04000000 */

+#define FDCAN_NDAT2_ND58          FDCAN_NDAT2_ND58_Msk                         /*!<New Data flag of Rx Buffer 58             */

+#define FDCAN_NDAT2_ND59_Pos      (27U)

+#define FDCAN_NDAT2_ND59_Msk      (0x1UL << FDCAN_NDAT2_ND59_Pos)              /*!< 0x08000000 */

+#define FDCAN_NDAT2_ND59          FDCAN_NDAT2_ND59_Msk                         /*!<New Data flag of Rx Buffer 59             */

+#define FDCAN_NDAT2_ND60_Pos      (28U)

+#define FDCAN_NDAT2_ND60_Msk      (0x1UL << FDCAN_NDAT2_ND60_Pos)              /*!< 0x10000000 */

+#define FDCAN_NDAT2_ND60          FDCAN_NDAT2_ND60_Msk                         /*!<New Data flag of Rx Buffer 60             */

+#define FDCAN_NDAT2_ND61_Pos      (29U)

+#define FDCAN_NDAT2_ND61_Msk      (0x1UL << FDCAN_NDAT2_ND61_Pos)              /*!< 0x20000000 */

+#define FDCAN_NDAT2_ND61          FDCAN_NDAT2_ND61_Msk                         /*!<New Data flag of Rx Buffer 61             */

+#define FDCAN_NDAT2_ND62_Pos      (30U)

+#define FDCAN_NDAT2_ND62_Msk      (0x1UL << FDCAN_NDAT2_ND62_Pos)              /*!< 0x40000000 */

+#define FDCAN_NDAT2_ND62          FDCAN_NDAT2_ND62_Msk                         /*!<New Data flag of Rx Buffer 62             */

+#define FDCAN_NDAT2_ND63_Pos      (31U)

+#define FDCAN_NDAT2_ND63_Msk      (0x1UL << FDCAN_NDAT2_ND63_Pos)              /*!< 0x80000000 */

+#define FDCAN_NDAT2_ND63          FDCAN_NDAT2_ND63_Msk                         /*!<New Data flag of Rx Buffer 63             */

+

+/*****************  Bit definition for FDCAN_RXF0C register  ********************/

+#define FDCAN_RXF0C_F0SA_Pos      (2U)

+#define FDCAN_RXF0C_F0SA_Msk      (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_RXF0C_F0SA          FDCAN_RXF0C_F0SA_Msk                         /*!<Rx FIFO 0 Start Address                   */

+#define FDCAN_RXF0C_F0S_Pos       (16U)

+#define FDCAN_RXF0C_F0S_Msk       (0x7FUL << FDCAN_RXF0C_F0S_Pos)              /*!< 0x007F0000 */

+#define FDCAN_RXF0C_F0S           FDCAN_RXF0C_F0S_Msk                          /*!<Number of Rx FIFO 0 elements              */

+#define FDCAN_RXF0C_F0WM_Pos      (24U)

+#define FDCAN_RXF0C_F0WM_Msk      (0x7FUL << FDCAN_RXF0C_F0WM_Pos)             /*!< 0x7F000000 */

+#define FDCAN_RXF0C_F0WM          FDCAN_RXF0C_F0WM_Msk                         /*!<FIFO 0 Watermark                          */

+#define FDCAN_RXF0C_F0OM_Pos      (31U)

+#define FDCAN_RXF0C_F0OM_Msk      (0x1UL << FDCAN_RXF0C_F0OM_Pos)              /*!< 0x80000000 */

+#define FDCAN_RXF0C_F0OM          FDCAN_RXF0C_F0OM_Msk                         /*!<FIFO 0 Operation Mode                     */

+

+/*****************  Bit definition for FDCAN_RXF0S register  ********************/

+#define FDCAN_RXF0S_F0FL_Pos      (0U)

+#define FDCAN_RXF0S_F0FL_Msk      (0x7FUL << FDCAN_RXF0S_F0FL_Pos)             /*!< 0x0000007F */

+#define FDCAN_RXF0S_F0FL          FDCAN_RXF0S_F0FL_Msk                         /*!<Rx FIFO 0 Fill Level                      */

+#define FDCAN_RXF0S_F0GI_Pos      (8U)

+#define FDCAN_RXF0S_F0GI_Msk      (0x3FUL << FDCAN_RXF0S_F0GI_Pos)             /*!< 0x00003F00 */

+#define FDCAN_RXF0S_F0GI          FDCAN_RXF0S_F0GI_Msk                         /*!<Rx FIFO 0 Get Index                       */

+#define FDCAN_RXF0S_F0PI_Pos      (16U)

+#define FDCAN_RXF0S_F0PI_Msk      (0x3FUL << FDCAN_RXF0S_F0PI_Pos)             /*!< 0x003F0000 */

+#define FDCAN_RXF0S_F0PI          FDCAN_RXF0S_F0PI_Msk                         /*!<Rx FIFO 0 Put Index                       */

+#define FDCAN_RXF0S_F0F_Pos       (24U)

+#define FDCAN_RXF0S_F0F_Msk       (0x1UL << FDCAN_RXF0S_F0F_Pos)               /*!< 0x01000000 */

+#define FDCAN_RXF0S_F0F           FDCAN_RXF0S_F0F_Msk                          /*!<Rx FIFO 0 Full                            */

+#define FDCAN_RXF0S_RF0L_Pos      (25U)

+#define FDCAN_RXF0S_RF0L_Msk      (0x1UL << FDCAN_RXF0S_RF0L_Pos)              /*!< 0x02000000 */

+#define FDCAN_RXF0S_RF0L          FDCAN_RXF0S_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                    */

+

+/*****************  Bit definition for FDCAN_RXF0A register  ********************/

+#define FDCAN_RXF0A_F0AI_Pos      (0U)

+#define FDCAN_RXF0A_F0AI_Msk      (0x3FUL << FDCAN_RXF0A_F0AI_Pos)             /*!< 0x0000003F */

+#define FDCAN_RXF0A_F0AI          FDCAN_RXF0A_F0AI_Msk                         /*!<Rx FIFO 0 Acknowledge Index               */

+

+/*****************  Bit definition for FDCAN_RXBC register  ********************/

+#define FDCAN_RXBC_RBSA_Pos       (2U)

+#define FDCAN_RXBC_RBSA_Msk       (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)            /*!< 0x0000FFFC */

+#define FDCAN_RXBC_RBSA           FDCAN_RXBC_RBSA_Msk                          /*!<Rx Buffer Start Address                   */

+

+/*****************  Bit definition for FDCAN_RXF1C register  ********************/

+#define FDCAN_RXF1C_F1SA_Pos      (2U)

+#define FDCAN_RXF1C_F1SA_Msk      (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_RXF1C_F1SA          FDCAN_RXF1C_F1SA_Msk                         /*!<Rx FIFO 1 Start Address                   */

+#define FDCAN_RXF1C_F1S_Pos       (16U)

+#define FDCAN_RXF1C_F1S_Msk       (0x7FUL << FDCAN_RXF1C_F1S_Pos)              /*!< 0x007F0000 */

+#define FDCAN_RXF1C_F1S           FDCAN_RXF1C_F1S_Msk                          /*!<Number of Rx FIFO 1 elements              */

+#define FDCAN_RXF1C_F1WM_Pos      (24U)

+#define FDCAN_RXF1C_F1WM_Msk      (0x7FUL << FDCAN_RXF1C_F1WM_Pos)             /*!< 0x7F000000 */

+#define FDCAN_RXF1C_F1WM          FDCAN_RXF1C_F1WM_Msk                         /*!<Rx FIFO 1 Watermark                       */

+#define FDCAN_RXF1C_F1OM_Pos      (31U)

+#define FDCAN_RXF1C_F1OM_Msk      (0x1UL << FDCAN_RXF1C_F1OM_Pos)              /*!< 0x80000000 */

+#define FDCAN_RXF1C_F1OM          FDCAN_RXF1C_F1OM_Msk                         /*!<FIFO 1 Operation Mode                     */

+

+/*****************  Bit definition for FDCAN_RXF1S register  ********************/

+#define FDCAN_RXF1S_F1FL_Pos      (0U)

+#define FDCAN_RXF1S_F1FL_Msk      (0x7FUL << FDCAN_RXF1S_F1FL_Pos)             /*!< 0x0000007F */

+#define FDCAN_RXF1S_F1FL          FDCAN_RXF1S_F1FL_Msk                         /*!<Rx FIFO 1 Fill Level                      */

+#define FDCAN_RXF1S_F1GI_Pos      (8U)

+#define FDCAN_RXF1S_F1GI_Msk      (0x3FUL << FDCAN_RXF1S_F1GI_Pos)             /*!< 0x00003F00 */

+#define FDCAN_RXF1S_F1GI          FDCAN_RXF1S_F1GI_Msk                         /*!<Rx FIFO 1 Get Index                       */

+#define FDCAN_RXF1S_F1PI_Pos      (16U)

+#define FDCAN_RXF1S_F1PI_Msk      (0x3FUL << FDCAN_RXF1S_F1PI_Pos)             /*!< 0x003F0000 */

+#define FDCAN_RXF1S_F1PI          FDCAN_RXF1S_F1PI_Msk                         /*!<Rx FIFO 1 Put Index                       */

+#define FDCAN_RXF1S_F1F_Pos       (24U)

+#define FDCAN_RXF1S_F1F_Msk       (0x1UL << FDCAN_RXF1S_F1F_Pos)               /*!< 0x01000000 */

+#define FDCAN_RXF1S_F1F           FDCAN_RXF1S_F1F_Msk                          /*!<Rx FIFO 1 Full                            */

+#define FDCAN_RXF1S_RF1L_Pos      (25U)

+#define FDCAN_RXF1S_RF1L_Msk      (0x1UL << FDCAN_RXF1S_RF1L_Pos)              /*!< 0x02000000 */

+#define FDCAN_RXF1S_RF1L          FDCAN_RXF1S_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                    */

+

+/*****************  Bit definition for FDCAN_RXF1A register  ********************/

+#define FDCAN_RXF1A_F1AI_Pos      (0U)

+#define FDCAN_RXF1A_F1AI_Msk      (0x3FUL << FDCAN_RXF1A_F1AI_Pos)             /*!< 0x0000003F */

+#define FDCAN_RXF1A_F1AI          FDCAN_RXF1A_F1AI_Msk                         /*!<Rx FIFO 1 Acknowledge Index               */

+

+/*****************  Bit definition for FDCAN_RXESC register  ********************/

+#define FDCAN_RXESC_F0DS_Pos      (0U)

+#define FDCAN_RXESC_F0DS_Msk      (0x7UL << FDCAN_RXESC_F0DS_Pos)              /*!< 0x00000007 */

+#define FDCAN_RXESC_F0DS          FDCAN_RXESC_F0DS_Msk                         /*!<Rx FIFO 1 Data Field Size                 */

+#define FDCAN_RXESC_F1DS_Pos      (4U)

+#define FDCAN_RXESC_F1DS_Msk      (0x7UL << FDCAN_RXESC_F1DS_Pos)              /*!< 0x00000070 */

+#define FDCAN_RXESC_F1DS          FDCAN_RXESC_F1DS_Msk                         /*!<Rx FIFO 0 Data Field Size                 */

+#define FDCAN_RXESC_RBDS_Pos      (8U)

+#define FDCAN_RXESC_RBDS_Msk      (0x7UL << FDCAN_RXESC_RBDS_Pos)              /*!< 0x00000700 */

+#define FDCAN_RXESC_RBDS          FDCAN_RXESC_RBDS_Msk                         /*!<Rx Buffer Data Field Size                 */

+

+/*****************  Bit definition for FDCAN_TXBC register  *********************/

+#define FDCAN_TXBC_TBSA_Pos       (2U)

+#define FDCAN_TXBC_TBSA_Msk       (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)            /*!< 0x0000FFFC */

+#define FDCAN_TXBC_TBSA           FDCAN_TXBC_TBSA_Msk                          /*!<Tx Buffers Start Address                  */

+#define FDCAN_TXBC_NDTB_Pos       (16U)

+#define FDCAN_TXBC_NDTB_Msk       (0x3FUL << FDCAN_TXBC_NDTB_Pos)              /*!< 0x003F0000 */

+#define FDCAN_TXBC_NDTB           FDCAN_TXBC_NDTB_Msk                          /*!<Number of Dedicated Transmit Buffers      */

+#define FDCAN_TXBC_TFQS_Pos       (24U)

+#define FDCAN_TXBC_TFQS_Msk       (0x3FUL << FDCAN_TXBC_TFQS_Pos)              /*!< 0x3F000000 */

+#define FDCAN_TXBC_TFQS           FDCAN_TXBC_TFQS_Msk                          /*!<Transmit FIFO/Queue Size                  */

+#define FDCAN_TXBC_TFQM_Pos       (30U)

+#define FDCAN_TXBC_TFQM_Msk       (0x1UL << FDCAN_TXBC_TFQM_Pos)               /*!< 0x40000000 */

+#define FDCAN_TXBC_TFQM           FDCAN_TXBC_TFQM_Msk                          /*!<Tx FIFO/Queue Mode                        */

+

+/*****************  Bit definition for FDCAN_TXFQS register  *********************/

+#define FDCAN_TXFQS_TFFL_Pos      (0U)

+#define FDCAN_TXFQS_TFFL_Msk      (0x3FUL << FDCAN_TXFQS_TFFL_Pos)             /*!< 0x0000003F */

+#define FDCAN_TXFQS_TFFL          FDCAN_TXFQS_TFFL_Msk                         /*!<Tx FIFO Free Level                        */

+#define FDCAN_TXFQS_TFGI_Pos      (8U)

+#define FDCAN_TXFQS_TFGI_Msk      (0x1FUL << FDCAN_TXFQS_TFGI_Pos)             /*!< 0x00001F00 */

+#define FDCAN_TXFQS_TFGI          FDCAN_TXFQS_TFGI_Msk                         /*!<Tx FIFO Get Index                         */

+#define FDCAN_TXFQS_TFQPI_Pos     (16U)

+#define FDCAN_TXFQS_TFQPI_Msk     (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)            /*!< 0x001F0000 */

+#define FDCAN_TXFQS_TFQPI         FDCAN_TXFQS_TFQPI_Msk                        /*!<Tx FIFO/Queue Put Index                   */

+#define FDCAN_TXFQS_TFQF_Pos      (21U)

+#define FDCAN_TXFQS_TFQF_Msk      (0x1UL << FDCAN_TXFQS_TFQF_Pos)              /*!< 0x00200000 */

+#define FDCAN_TXFQS_TFQF          FDCAN_TXFQS_TFQF_Msk                         /*!<Tx FIFO/Queue Full                        */

+

+/*****************  Bit definition for FDCAN_TXESC register  *********************/

+#define FDCAN_TXESC_TBDS_Pos      (0U)

+#define FDCAN_TXESC_TBDS_Msk      (0x7UL << FDCAN_TXESC_TBDS_Pos)              /*!< 0x00000007 */

+#define FDCAN_TXESC_TBDS          FDCAN_TXESC_TBDS_Msk                         /*!<Tx Buffer Data Field Size                 */

+

+/*****************  Bit definition for FDCAN_TXBRP register  *********************/

+#define FDCAN_TXBRP_TRP_Pos       (0U)

+#define FDCAN_TXBRP_TRP_Msk       (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)        /*!< 0xFFFFFFFF */

+#define FDCAN_TXBRP_TRP           FDCAN_TXBRP_TRP_Msk                          /*!<Transmission Request Pending              */

+

+/*****************  Bit definition for FDCAN_TXBAR register  *********************/

+#define FDCAN_TXBAR_AR_Pos        (0U)

+#define FDCAN_TXBAR_AR_Msk        (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBAR_AR            FDCAN_TXBAR_AR_Msk                           /*!<Add Request                               */

+

+/*****************  Bit definition for FDCAN_TXBCR register  *********************/

+#define FDCAN_TXBCR_CR_Pos        (0U)

+#define FDCAN_TXBCR_CR_Msk        (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCR_CR            FDCAN_TXBCR_CR_Msk                           /*!<Cancellation Request                      */

+

+/*****************  Bit definition for FDCAN_TXBTO register  *********************/

+#define FDCAN_TXBTO_TO_Pos        (0U)

+#define FDCAN_TXBTO_TO_Msk        (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBTO_TO            FDCAN_TXBTO_TO_Msk                           /*!<Transmission Occurred                     */

+

+/*****************  Bit definition for FDCAN_TXBCF register  *********************/

+#define FDCAN_TXBCF_CF_Pos        (0U)

+#define FDCAN_TXBCF_CF_Msk        (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCF_CF            FDCAN_TXBCF_CF_Msk                           /*!<Cancellation Finished                     */

+

+/*****************  Bit definition for FDCAN_TXBTIE register  ********************/

+#define FDCAN_TXBTIE_TIE_Pos      (0U)

+#define FDCAN_TXBTIE_TIE_Msk      (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)       /*!< 0xFFFFFFFF */

+#define FDCAN_TXBTIE_TIE          FDCAN_TXBTIE_TIE_Msk                         /*!<Transmission Interrupt Enable             */

+

+/*****************  Bit definition for FDCAN_ TXBCIE register  *******************/

+#define FDCAN_TXBCIE_CFIE_Pos     (0U)

+#define FDCAN_TXBCIE_CFIE_Msk     (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)      /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCIE_CFIE         FDCAN_TXBCIE_CFIE_Msk                        /*!<Cancellation Finished Interrupt Enable    */

+

+/*****************  Bit definition for FDCAN_TXEFC register  *********************/

+#define FDCAN_TXEFC_EFSA_Pos      (2U)

+#define FDCAN_TXEFC_EFSA_Msk      (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_TXEFC_EFSA          FDCAN_TXEFC_EFSA_Msk                         /*!<Event FIFO Start Address                  */

+#define FDCAN_TXEFC_EFS_Pos       (16U)

+#define FDCAN_TXEFC_EFS_Msk       (0x3FUL << FDCAN_TXEFC_EFS_Pos)              /*!< 0x003F0000 */

+#define FDCAN_TXEFC_EFS           FDCAN_TXEFC_EFS_Msk                          /*!<Event FIFO Size                           */

+#define FDCAN_TXEFC_EFWM_Pos      (24U)

+#define FDCAN_TXEFC_EFWM_Msk      (0x3FUL << FDCAN_TXEFC_EFWM_Pos)             /*!< 0x3F000000 */

+#define FDCAN_TXEFC_EFWM          FDCAN_TXEFC_EFWM_Msk                         /*!<Event FIFO Watermark                      */

+

+/*****************  Bit definition for FDCAN_TXEFS register  *********************/

+#define FDCAN_TXEFS_EFFL_Pos      (0U)

+#define FDCAN_TXEFS_EFFL_Msk      (0x3FUL << FDCAN_TXEFS_EFFL_Pos)             /*!< 0x0000003F */

+#define FDCAN_TXEFS_EFFL          FDCAN_TXEFS_EFFL_Msk                         /*!<Event FIFO Fill Level                     */

+#define FDCAN_TXEFS_EFGI_Pos      (8U)

+#define FDCAN_TXEFS_EFGI_Msk      (0x1FUL << FDCAN_TXEFS_EFGI_Pos)             /*!< 0x00001F00 */

+#define FDCAN_TXEFS_EFGI          FDCAN_TXEFS_EFGI_Msk                         /*!<Event FIFO Get Index                      */

+#define FDCAN_TXEFS_EFPI_Pos      (16U)

+#define FDCAN_TXEFS_EFPI_Msk      (0x1FUL << FDCAN_TXEFS_EFPI_Pos)             /*!< 0x001F0000 */

+#define FDCAN_TXEFS_EFPI          FDCAN_TXEFS_EFPI_Msk                         /*!<Event FIFO Put Index                      */

+#define FDCAN_TXEFS_EFF_Pos       (24U)

+#define FDCAN_TXEFS_EFF_Msk       (0x1UL << FDCAN_TXEFS_EFF_Pos)               /*!< 0x01000000 */

+#define FDCAN_TXEFS_EFF           FDCAN_TXEFS_EFF_Msk                          /*!<Event FIFO Full                           */

+#define FDCAN_TXEFS_TEFL_Pos      (25U)

+#define FDCAN_TXEFS_TEFL_Msk      (0x1UL << FDCAN_TXEFS_TEFL_Pos)              /*!< 0x02000000 */

+#define FDCAN_TXEFS_TEFL          FDCAN_TXEFS_TEFL_Msk                         /*!<Tx Event FIFO Element Lost                */

+

+/*****************  Bit definition for FDCAN_TXEFA register  *********************/

+#define FDCAN_TXEFA_EFAI_Pos      (0U)

+#define FDCAN_TXEFA_EFAI_Msk      (0x1FUL << FDCAN_TXEFA_EFAI_Pos)             /*!< 0x0000001F */

+#define FDCAN_TXEFA_EFAI          FDCAN_TXEFA_EFAI_Msk                         /*!<Event FIFO Acknowledge Index              */

+

+/*****************  Bit definition for FDCAN_TTTMC register  *********************/

+#define FDCAN_TTTMC_TMSA_Pos      (2U)

+#define FDCAN_TTTMC_TMSA_Msk      (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_TTTMC_TMSA          FDCAN_TTTMC_TMSA_Msk                         /*!<Trigger Memory Start Address              */

+#define FDCAN_TTTMC_TME_Pos       (16U)

+#define FDCAN_TTTMC_TME_Msk       (0x7FUL << FDCAN_TTTMC_TME_Pos)              /*!< 0x007F0000 */

+#define FDCAN_TTTMC_TME           FDCAN_TTTMC_TME_Msk                          /*!<Trigger Memory Elements                   */

+

+/*****************  Bit definition for FDCAN_TTRMC register  *********************/

+#define FDCAN_TTRMC_RID_Pos       (0U)

+#define FDCAN_TTRMC_RID_Msk       (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)        /*!< 0x1FFFFFFF */

+#define FDCAN_TTRMC_RID           FDCAN_TTRMC_RID_Msk                          /*!<Reference Identifier                      */

+#define FDCAN_TTRMC_XTD_Pos       (30U)

+#define FDCAN_TTRMC_XTD_Msk       (0x1UL << FDCAN_TTRMC_XTD_Pos)               /*!< 0x40000000 */

+#define FDCAN_TTRMC_XTD           FDCAN_TTRMC_XTD_Msk                          /*!< Extended Identifier                      */

+#define FDCAN_TTRMC_RMPS_Pos      (31U)

+#define FDCAN_TTRMC_RMPS_Msk      (0x1UL << FDCAN_TTRMC_RMPS_Pos)              /*!< 0x80000000 */

+#define FDCAN_TTRMC_RMPS          FDCAN_TTRMC_RMPS_Msk                         /*!<Reference Message Payload Select          */

+

+/*****************  Bit definition for FDCAN_TTOCF register  *********************/

+#define FDCAN_TTOCF_OM_Pos        (0U)

+#define FDCAN_TTOCF_OM_Msk        (0x3UL << FDCAN_TTOCF_OM_Pos)                /*!< 0x00000003 */

+#define FDCAN_TTOCF_OM            FDCAN_TTOCF_OM_Msk                           /*!<Operation Mode                            */

+#define FDCAN_TTOCF_GEN_Pos       (3U)

+#define FDCAN_TTOCF_GEN_Msk       (0x1UL << FDCAN_TTOCF_GEN_Pos)               /*!< 0x00000008 */

+#define FDCAN_TTOCF_GEN           FDCAN_TTOCF_GEN_Msk                          /*!<Gap Enable                                */

+#define FDCAN_TTOCF_TM_Pos        (4U)

+#define FDCAN_TTOCF_TM_Msk        (0x1UL << FDCAN_TTOCF_TM_Pos)                /*!< 0x00000010 */

+#define FDCAN_TTOCF_TM            FDCAN_TTOCF_TM_Msk                           /*!<Time Master                               */

+#define FDCAN_TTOCF_LDSDL_Pos     (5U)

+#define FDCAN_TTOCF_LDSDL_Msk     (0x7UL << FDCAN_TTOCF_LDSDL_Pos)             /*!< 0x000000E0 */

+#define FDCAN_TTOCF_LDSDL         FDCAN_TTOCF_LDSDL_Msk                        /*!<LD of Synchronization Deviation Limit     */

+#define FDCAN_TTOCF_IRTO_Pos      (8U)

+#define FDCAN_TTOCF_IRTO_Msk      (0x7FUL << FDCAN_TTOCF_IRTO_Pos)             /*!< 0x00007F00 */

+#define FDCAN_TTOCF_IRTO          FDCAN_TTOCF_IRTO_Msk                         /*!<Initial Reference Trigger Offset          */

+#define FDCAN_TTOCF_EECS_Pos      (15U)

+#define FDCAN_TTOCF_EECS_Msk      (0x1UL << FDCAN_TTOCF_EECS_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTOCF_EECS          FDCAN_TTOCF_EECS_Msk                         /*!<Enable External Clock Synchronization     */

+#define FDCAN_TTOCF_AWL_Pos       (16U)

+#define FDCAN_TTOCF_AWL_Msk       (0xFFUL << FDCAN_TTOCF_AWL_Pos)              /*!< 0x00FF0000 */

+#define FDCAN_TTOCF_AWL           FDCAN_TTOCF_AWL_Msk                          /*!<Application Watchdog Limit                */

+#define FDCAN_TTOCF_EGTF_Pos      (24U)

+#define FDCAN_TTOCF_EGTF_Msk      (0x1UL << FDCAN_TTOCF_EGTF_Pos)              /*!< 0x01000000 */

+#define FDCAN_TTOCF_EGTF          FDCAN_TTOCF_EGTF_Msk                         /*!<Enable Global Time Filtering              */

+#define FDCAN_TTOCF_ECC_Pos       (25U)

+#define FDCAN_TTOCF_ECC_Msk       (0x1UL << FDCAN_TTOCF_ECC_Pos)               /*!< 0x02000000 */

+#define FDCAN_TTOCF_ECC           FDCAN_TTOCF_ECC_Msk                          /*!<Enable Clock Calibration                  */

+#define FDCAN_TTOCF_EVTP_Pos      (26U)

+#define FDCAN_TTOCF_EVTP_Msk      (0x1UL << FDCAN_TTOCF_EVTP_Pos)              /*!< 0x04000000 */

+#define FDCAN_TTOCF_EVTP          FDCAN_TTOCF_EVTP_Msk                         /*!<Event Trigger Polarity                    */

+

+/*****************  Bit definition for FDCAN_TTMLM register  *********************/

+#define FDCAN_TTMLM_CCM_Pos       (0U)

+#define FDCAN_TTMLM_CCM_Msk       (0x3FUL << FDCAN_TTMLM_CCM_Pos)              /*!< 0x0000003F */

+#define FDCAN_TTMLM_CCM           FDCAN_TTMLM_CCM_Msk                          /*!<Cycle Count Max                           */

+#define FDCAN_TTMLM_CSS_Pos       (6U)

+#define FDCAN_TTMLM_CSS_Msk       (0x3UL << FDCAN_TTMLM_CSS_Pos)               /*!< 0x000000C0 */

+#define FDCAN_TTMLM_CSS           FDCAN_TTMLM_CSS_Msk                          /*!<Cycle Start Synchronization               */

+#define FDCAN_TTMLM_TXEW_Pos      (8U)

+#define FDCAN_TTMLM_TXEW_Msk      (0xFUL << FDCAN_TTMLM_TXEW_Pos)              /*!< 0x00000F00 */

+#define FDCAN_TTMLM_TXEW          FDCAN_TTMLM_TXEW_Msk                         /*!<Tx Enable Window                          */

+#define FDCAN_TTMLM_ENTT_Pos      (16U)

+#define FDCAN_TTMLM_ENTT_Msk      (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)            /*!< 0x0FFF0000 */

+#define FDCAN_TTMLM_ENTT          FDCAN_TTMLM_ENTT_Msk                         /*!<Expected Number of Tx Triggers            */

+

+/*****************  Bit definition for FDCAN_TURCF register  *********************/

+#define FDCAN_TURCF_NCL_Pos       (0U)

+#define FDCAN_TURCF_NCL_Msk       (0xFFFFUL << FDCAN_TURCF_NCL_Pos)            /*!< 0x0000FFFF */

+#define FDCAN_TURCF_NCL           FDCAN_TURCF_NCL_Msk                          /*!<Numerator Configuration Low               */

+#define FDCAN_TURCF_DC_Pos        (16U)

+#define FDCAN_TURCF_DC_Msk        (0x3FFFUL << FDCAN_TURCF_DC_Pos)             /*!< 0x3FFF0000 */

+#define FDCAN_TURCF_DC            FDCAN_TURCF_DC_Msk                           /*!<Denominator Configuration                 */

+#define FDCAN_TURCF_ELT_Pos       (31U)

+#define FDCAN_TURCF_ELT_Msk       (0x1UL << FDCAN_TURCF_ELT_Pos)               /*!< 0x80000000 */

+#define FDCAN_TURCF_ELT           FDCAN_TURCF_ELT_Msk                          /*!<Enable Local Time                         */

+

+/*****************  Bit definition for FDCAN_TTOCN register  ********************/

+#define FDCAN_TTOCN_SGT_Pos       (0U)

+#define FDCAN_TTOCN_SGT_Msk       (0x1UL << FDCAN_TTOCN_SGT_Pos)               /*!< 0x00000001 */

+#define FDCAN_TTOCN_SGT           FDCAN_TTOCN_SGT_Msk                          /*!<Set Global time                           */

+#define FDCAN_TTOCN_ECS_Pos       (1U)

+#define FDCAN_TTOCN_ECS_Msk       (0x1UL << FDCAN_TTOCN_ECS_Pos)               /*!< 0x00000002 */

+#define FDCAN_TTOCN_ECS           FDCAN_TTOCN_ECS_Msk                          /*!<External Clock Synchronization            */

+#define FDCAN_TTOCN_SWP_Pos       (2U)

+#define FDCAN_TTOCN_SWP_Msk       (0x1UL << FDCAN_TTOCN_SWP_Pos)               /*!< 0x00000004 */

+#define FDCAN_TTOCN_SWP           FDCAN_TTOCN_SWP_Msk                          /*!<Stop Watch Polarity                       */

+#define FDCAN_TTOCN_SWS_Pos       (3U)

+#define FDCAN_TTOCN_SWS_Msk       (0x3UL << FDCAN_TTOCN_SWS_Pos)               /*!< 0x00000018 */

+#define FDCAN_TTOCN_SWS           FDCAN_TTOCN_SWS_Msk                          /*!<Stop Watch Source                         */

+#define FDCAN_TTOCN_RTIE_Pos      (5U)

+#define FDCAN_TTOCN_RTIE_Msk      (0x1UL << FDCAN_TTOCN_RTIE_Pos)              /*!< 0x00000020 */

+#define FDCAN_TTOCN_RTIE          FDCAN_TTOCN_RTIE_Msk                         /*!<Register Time Mark Interrupt Pulse Enable */

+#define FDCAN_TTOCN_TMC_Pos       (6U)

+#define FDCAN_TTOCN_TMC_Msk       (0x3UL << FDCAN_TTOCN_TMC_Pos)               /*!< 0x000000C0 */

+#define FDCAN_TTOCN_TMC           FDCAN_TTOCN_TMC_Msk                          /*!<Register Time Mark Compare                */

+#define FDCAN_TTOCN_TTIE_Pos      (8U)

+#define FDCAN_TTOCN_TTIE_Msk      (0x1UL << FDCAN_TTOCN_TTIE_Pos)              /*!< 0x00000100 */

+#define FDCAN_TTOCN_TTIE          FDCAN_TTOCN_TTIE_Msk                         /*!<Trigger Time Mark Interrupt Pulse Enable  */

+#define FDCAN_TTOCN_GCS_Pos       (9U)

+#define FDCAN_TTOCN_GCS_Msk       (0x1UL << FDCAN_TTOCN_GCS_Pos)               /*!< 0x00000200 */

+#define FDCAN_TTOCN_GCS           FDCAN_TTOCN_GCS_Msk                          /*!<Gap Control Select                        */

+#define FDCAN_TTOCN_FGP_Pos       (10U)

+#define FDCAN_TTOCN_FGP_Msk       (0x1UL << FDCAN_TTOCN_FGP_Pos)               /*!< 0x00000400 */

+#define FDCAN_TTOCN_FGP           FDCAN_TTOCN_FGP_Msk                          /*!<Finish Gap                                */

+#define FDCAN_TTOCN_TMG_Pos       (11U)

+#define FDCAN_TTOCN_TMG_Msk       (0x1UL << FDCAN_TTOCN_TMG_Pos)               /*!< 0x00000800 */

+#define FDCAN_TTOCN_TMG           FDCAN_TTOCN_TMG_Msk                          /*!<Time Mark Gap                             */

+#define FDCAN_TTOCN_NIG_Pos       (12U)

+#define FDCAN_TTOCN_NIG_Msk       (0x1UL << FDCAN_TTOCN_NIG_Pos)               /*!< 0x00001000 */

+#define FDCAN_TTOCN_NIG           FDCAN_TTOCN_NIG_Msk                          /*!<Next is Gap                               */

+#define FDCAN_TTOCN_ESCN_Pos      (13U)

+#define FDCAN_TTOCN_ESCN_Msk      (0x1UL << FDCAN_TTOCN_ESCN_Pos)              /*!< 0x00002000 */

+#define FDCAN_TTOCN_ESCN          FDCAN_TTOCN_ESCN_Msk                         /*!<External Synchronization Control          */

+#define FDCAN_TTOCN_LCKC_Pos      (15U)

+#define FDCAN_TTOCN_LCKC_Msk      (0x1UL << FDCAN_TTOCN_LCKC_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTOCN_LCKC          FDCAN_TTOCN_LCKC_Msk                         /*!<TT Operation Control Register Locked      */

+

+/*****************  Bit definition for FDCAN_TTGTP register  ********************/

+#define FDCAN_TTGTP_TP_Pos        (0U)

+#define FDCAN_TTGTP_TP_Msk        (0xFFFFUL << FDCAN_TTGTP_TP_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTGTP_TP            FDCAN_TTGTP_TP_Msk                           /*!<Time Preset                               */

+#define FDCAN_TTGTP_CTP_Pos       (16U)

+#define FDCAN_TTGTP_CTP_Msk       (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)            /*!< 0xFFFF0000 */

+#define FDCAN_TTGTP_CTP           FDCAN_TTGTP_CTP_Msk                          /*!<Cycle Time Target Phase                   */

+

+/*****************  Bit definition for FDCAN_TTTMK register  ********************/

+#define FDCAN_TTTMK_TM_Pos        (0U)

+#define FDCAN_TTTMK_TM_Msk        (0xFFFFUL << FDCAN_TTTMK_TM_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTTMK_TM            FDCAN_TTTMK_TM_Msk                           /*!<Time Mark                                 */

+#define FDCAN_TTTMK_TICC_Pos      (16U)

+#define FDCAN_TTTMK_TICC_Msk      (0x7FUL << FDCAN_TTTMK_TICC_Pos)             /*!< 0x007F0000 */

+#define FDCAN_TTTMK_TICC          FDCAN_TTTMK_TICC_Msk                         /*!<Time Mark Cycle Code                      */

+#define FDCAN_TTTMK_LCKM_Pos      (31U)

+#define FDCAN_TTTMK_LCKM_Msk      (0x1UL << FDCAN_TTTMK_LCKM_Pos)              /*!< 0x80000000 */

+#define FDCAN_TTTMK_LCKM          FDCAN_TTTMK_LCKM_Msk                         /*!<TT Time Mark Register Locked              */

+

+/*****************  Bit definition for FDCAN_TTIR register  ********************/

+#define FDCAN_TTIR_SBC_Pos        (0U)

+#define FDCAN_TTIR_SBC_Msk        (0x1UL << FDCAN_TTIR_SBC_Pos)                /*!< 0x00000001 */

+#define FDCAN_TTIR_SBC            FDCAN_TTIR_SBC_Msk                           /*!<Start of Basic Cycle                      */

+#define FDCAN_TTIR_SMC_Pos        (1U)

+#define FDCAN_TTIR_SMC_Msk        (0x1UL << FDCAN_TTIR_SMC_Pos)                /*!< 0x00000002 */

+#define FDCAN_TTIR_SMC            FDCAN_TTIR_SMC_Msk                           /*!<Start of Matrix Cycle                     */

+#define FDCAN_TTIR_CSM_Pos        (2U)

+#define FDCAN_TTIR_CSM_Msk        (0x1UL << FDCAN_TTIR_CSM_Pos)                /*!< 0x00000004 */

+#define FDCAN_TTIR_CSM            FDCAN_TTIR_CSM_Msk                           /*!<Change of Synchronization Mode            */

+#define FDCAN_TTIR_SOG_Pos        (3U)

+#define FDCAN_TTIR_SOG_Msk        (0x1UL << FDCAN_TTIR_SOG_Pos)                /*!< 0x00000008 */

+#define FDCAN_TTIR_SOG            FDCAN_TTIR_SOG_Msk                           /*!<Start of Gap                              */

+#define FDCAN_TTIR_RTMI_Pos       (4U)

+#define FDCAN_TTIR_RTMI_Msk       (0x1UL << FDCAN_TTIR_RTMI_Pos)               /*!< 0x00000010 */

+#define FDCAN_TTIR_RTMI           FDCAN_TTIR_RTMI_Msk                          /*!<Register Time Mark Interrupt              */

+#define FDCAN_TTIR_TTMI_Pos       (5U)

+#define FDCAN_TTIR_TTMI_Msk       (0x1UL << FDCAN_TTIR_TTMI_Pos)               /*!< 0x00000020 */

+#define FDCAN_TTIR_TTMI           FDCAN_TTIR_TTMI_Msk                          /*!<Trigger Time Mark Event Internal          */

+#define FDCAN_TTIR_SWE_Pos        (6U)

+#define FDCAN_TTIR_SWE_Msk        (0x1UL << FDCAN_TTIR_SWE_Pos)                /*!< 0x00000040 */

+#define FDCAN_TTIR_SWE            FDCAN_TTIR_SWE_Msk                           /*!<Stop Watch Event                          */

+#define FDCAN_TTIR_GTW_Pos        (7U)

+#define FDCAN_TTIR_GTW_Msk        (0x1UL << FDCAN_TTIR_GTW_Pos)                /*!< 0x00000080 */

+#define FDCAN_TTIR_GTW            FDCAN_TTIR_GTW_Msk                           /*!<Global Time Wrap                          */

+#define FDCAN_TTIR_GTD_Pos        (8U)

+#define FDCAN_TTIR_GTD_Msk        (0x1UL << FDCAN_TTIR_GTD_Pos)                /*!< 0x00000100 */

+#define FDCAN_TTIR_GTD            FDCAN_TTIR_GTD_Msk                           /*!<Global Time Discontinuity                 */

+#define FDCAN_TTIR_GTE_Pos        (9U)

+#define FDCAN_TTIR_GTE_Msk        (0x1UL << FDCAN_TTIR_GTE_Pos)                /*!< 0x00000200 */

+#define FDCAN_TTIR_GTE            FDCAN_TTIR_GTE_Msk                           /*!<Global Time Error                         */

+#define FDCAN_TTIR_TXU_Pos        (10U)

+#define FDCAN_TTIR_TXU_Msk        (0x1UL << FDCAN_TTIR_TXU_Pos)                /*!< 0x00000400 */

+#define FDCAN_TTIR_TXU            FDCAN_TTIR_TXU_Msk                           /*!<Tx Count Underflow                        */

+#define FDCAN_TTIR_TXO_Pos        (11U)

+#define FDCAN_TTIR_TXO_Msk        (0x1UL << FDCAN_TTIR_TXO_Pos)                /*!< 0x00000800 */

+#define FDCAN_TTIR_TXO            FDCAN_TTIR_TXO_Msk                           /*!<Tx Count Overflow                         */

+#define FDCAN_TTIR_SE1_Pos        (12U)

+#define FDCAN_TTIR_SE1_Msk        (0x1UL << FDCAN_TTIR_SE1_Pos)                /*!< 0x00001000 */

+#define FDCAN_TTIR_SE1            FDCAN_TTIR_SE1_Msk                           /*!<Scheduling Error 1                        */

+#define FDCAN_TTIR_SE2_Pos        (13U)

+#define FDCAN_TTIR_SE2_Msk        (0x1UL << FDCAN_TTIR_SE2_Pos)                /*!< 0x00002000 */

+#define FDCAN_TTIR_SE2            FDCAN_TTIR_SE2_Msk                           /*!<Scheduling Error 2                        */

+#define FDCAN_TTIR_ELC_Pos        (14U)

+#define FDCAN_TTIR_ELC_Msk        (0x1UL << FDCAN_TTIR_ELC_Pos)                /*!< 0x00004000 */

+#define FDCAN_TTIR_ELC            FDCAN_TTIR_ELC_Msk                           /*!<Error Level Changed                       */

+#define FDCAN_TTIR_IWT_Pos        (15U)

+#define FDCAN_TTIR_IWT_Msk        (0x1UL << FDCAN_TTIR_IWT_Pos)                /*!< 0x00008000 */

+#define FDCAN_TTIR_IWT            FDCAN_TTIR_IWT_Msk                           /*!<Initialization Watch Trigger              */

+#define FDCAN_TTIR_WT_Pos         (16U)

+#define FDCAN_TTIR_WT_Msk         (0x1UL << FDCAN_TTIR_WT_Pos)                 /*!< 0x00010000 */

+#define FDCAN_TTIR_WT             FDCAN_TTIR_WT_Msk                            /*!<Watch Trigger                             */

+#define FDCAN_TTIR_AW_Pos         (17U)

+#define FDCAN_TTIR_AW_Msk         (0x1UL << FDCAN_TTIR_AW_Pos)                 /*!< 0x00020000 */

+#define FDCAN_TTIR_AW             FDCAN_TTIR_AW_Msk                            /*!<Application Watchdog                      */

+#define FDCAN_TTIR_CER_Pos        (18U)

+#define FDCAN_TTIR_CER_Msk        (0x1UL << FDCAN_TTIR_CER_Pos)                /*!< 0x00040000 */

+#define FDCAN_TTIR_CER            FDCAN_TTIR_CER_Msk                           /*!<Configuration Error                       */

+

+/*****************  Bit definition for FDCAN_TTIE register  ********************/

+#define FDCAN_TTIE_SBCE_Pos       (0U)

+#define FDCAN_TTIE_SBCE_Msk       (0x1UL << FDCAN_TTIE_SBCE_Pos)               /*!< 0x00000001 */

+#define FDCAN_TTIE_SBCE           FDCAN_TTIE_SBCE_Msk                          /*!<Start of Basic Cycle Interrupt Enable             */

+#define FDCAN_TTIE_SMCE_Pos       (1U)

+#define FDCAN_TTIE_SMCE_Msk       (0x1UL << FDCAN_TTIE_SMCE_Pos)               /*!< 0x00000002 */

+#define FDCAN_TTIE_SMCE           FDCAN_TTIE_SMCE_Msk                          /*!<Start of Matrix Cycle Interrupt Enable            */

+#define FDCAN_TTIE_CSME_Pos       (2U)

+#define FDCAN_TTIE_CSME_Msk       (0x1UL << FDCAN_TTIE_CSME_Pos)               /*!< 0x00000004 */

+#define FDCAN_TTIE_CSME           FDCAN_TTIE_CSME_Msk                          /*!<Change of Synchronization Mode Interrupt Enable   */

+#define FDCAN_TTIE_SOGE_Pos       (3U)

+#define FDCAN_TTIE_SOGE_Msk       (0x1UL << FDCAN_TTIE_SOGE_Pos)               /*!< 0x00000008 */

+#define FDCAN_TTIE_SOGE           FDCAN_TTIE_SOGE_Msk                          /*!<Start of Gap Interrupt Enable                     */

+#define FDCAN_TTIE_RTMIE_Pos      (4U)

+#define FDCAN_TTIE_RTMIE_Msk      (0x1UL << FDCAN_TTIE_RTMIE_Pos)              /*!< 0x00000010 */

+#define FDCAN_TTIE_RTMIE          FDCAN_TTIE_RTMIE_Msk                         /*!<Register Time Mark Interrupt Interrupt Enable     */

+#define FDCAN_TTIE_TTMIE_Pos      (5U)

+#define FDCAN_TTIE_TTMIE_Msk      (0x1UL << FDCAN_TTIE_TTMIE_Pos)              /*!< 0x00000020 */

+#define FDCAN_TTIE_TTMIE          FDCAN_TTIE_TTMIE_Msk                         /*!<Trigger Time Mark Event Internal Interrupt Enable */

+#define FDCAN_TTIE_SWEE_Pos       (6U)

+#define FDCAN_TTIE_SWEE_Msk       (0x1UL << FDCAN_TTIE_SWEE_Pos)               /*!< 0x00000040 */

+#define FDCAN_TTIE_SWEE           FDCAN_TTIE_SWEE_Msk                          /*!<Stop Watch Event Interrupt Enable                 */

+#define FDCAN_TTIE_GTWE_Pos       (7U)

+#define FDCAN_TTIE_GTWE_Msk       (0x1UL << FDCAN_TTIE_GTWE_Pos)               /*!< 0x00000080 */

+#define FDCAN_TTIE_GTWE           FDCAN_TTIE_GTWE_Msk                          /*!<Global Time Wrap Interrupt Enable                 */

+#define FDCAN_TTIE_GTDE_Pos       (8U)

+#define FDCAN_TTIE_GTDE_Msk       (0x1UL << FDCAN_TTIE_GTDE_Pos)               /*!< 0x00000100 */

+#define FDCAN_TTIE_GTDE           FDCAN_TTIE_GTDE_Msk                          /*!<Global Time Discontinuity Interrupt Enable        */

+#define FDCAN_TTIE_GTEE_Pos       (9U)

+#define FDCAN_TTIE_GTEE_Msk       (0x1UL << FDCAN_TTIE_GTEE_Pos)               /*!< 0x00000200 */

+#define FDCAN_TTIE_GTEE           FDCAN_TTIE_GTEE_Msk                          /*!<Global Time Error Interrupt Enable                */

+#define FDCAN_TTIE_TXUE_Pos       (10U)

+#define FDCAN_TTIE_TXUE_Msk       (0x1UL << FDCAN_TTIE_TXUE_Pos)               /*!< 0x00000400 */

+#define FDCAN_TTIE_TXUE           FDCAN_TTIE_TXUE_Msk                          /*!<Tx Count Underflow Interrupt Enable               */

+#define FDCAN_TTIE_TXOE_Pos       (11U)

+#define FDCAN_TTIE_TXOE_Msk       (0x1UL << FDCAN_TTIE_TXOE_Pos)               /*!< 0x00000800 */

+#define FDCAN_TTIE_TXOE           FDCAN_TTIE_TXOE_Msk                          /*!<Tx Count Overflow Interrupt Enable                */

+#define FDCAN_TTIE_SE1E_Pos       (12U)

+#define FDCAN_TTIE_SE1E_Msk       (0x1UL << FDCAN_TTIE_SE1E_Pos)               /*!< 0x00001000 */

+#define FDCAN_TTIE_SE1E           FDCAN_TTIE_SE1E_Msk                          /*!<Scheduling Error 1 Interrupt Enable               */

+#define FDCAN_TTIE_SE2E_Pos       (13U)

+#define FDCAN_TTIE_SE2E_Msk       (0x1UL << FDCAN_TTIE_SE2E_Pos)               /*!< 0x00002000 */

+#define FDCAN_TTIE_SE2E           FDCAN_TTIE_SE2E_Msk                          /*!<Scheduling Error 2 Interrupt Enable               */

+#define FDCAN_TTIE_ELCE_Pos       (14U)

+#define FDCAN_TTIE_ELCE_Msk       (0x1UL << FDCAN_TTIE_ELCE_Pos)               /*!< 0x00004000 */

+#define FDCAN_TTIE_ELCE           FDCAN_TTIE_ELCE_Msk                          /*!<Error Level Changed Interrupt Enable              */

+#define FDCAN_TTIE_IWTE_Pos       (15U)

+#define FDCAN_TTIE_IWTE_Msk       (0x1UL << FDCAN_TTIE_IWTE_Pos)               /*!< 0x00008000 */

+#define FDCAN_TTIE_IWTE           FDCAN_TTIE_IWTE_Msk                          /*!<Initialization Watch Trigger Interrupt Enable     */

+#define FDCAN_TTIE_WTE_Pos        (16U)

+#define FDCAN_TTIE_WTE_Msk        (0x1UL << FDCAN_TTIE_WTE_Pos)                /*!< 0x00010000 */

+#define FDCAN_TTIE_WTE            FDCAN_TTIE_WTE_Msk                           /*!<Watch Trigger Interrupt Enable                    */

+#define FDCAN_TTIE_AWE_Pos        (17U)

+#define FDCAN_TTIE_AWE_Msk        (0x1UL << FDCAN_TTIE_AWE_Pos)                /*!< 0x00020000 */

+#define FDCAN_TTIE_AWE            FDCAN_TTIE_AWE_Msk                           /*!<Application Watchdog Interrupt Enable             */

+#define FDCAN_TTIE_CERE_Pos       (18U)

+#define FDCAN_TTIE_CERE_Msk       (0x1UL << FDCAN_TTIE_CERE_Pos)               /*!< 0x00040000 */

+#define FDCAN_TTIE_CERE           FDCAN_TTIE_CERE_Msk                          /*!<Configuration Error Interrupt Enable              */

+

+/*****************  Bit definition for FDCAN_TTILS register  ********************/

+#define FDCAN_TTILS_SBCS_Pos      (0U)

+#define FDCAN_TTILS_SBCS_Msk      (0x1UL << FDCAN_TTILS_SBCS_Pos)              /*!< 0x00000001 */

+#define FDCAN_TTILS_SBCS          FDCAN_TTILS_SBCS_Msk                         /*!<Start of Basic Cycle Interrupt Line               */

+#define FDCAN_TTILS_SMCS_Pos      (1U)

+#define FDCAN_TTILS_SMCS_Msk      (0x1UL << FDCAN_TTILS_SMCS_Pos)              /*!< 0x00000002 */

+#define FDCAN_TTILS_SMCS          FDCAN_TTILS_SMCS_Msk                         /*!<Start of Matrix Cycle Interrupt Line              */

+#define FDCAN_TTILS_CSMS_Pos      (2U)

+#define FDCAN_TTILS_CSMS_Msk      (0x1UL << FDCAN_TTILS_CSMS_Pos)              /*!< 0x00000004 */

+#define FDCAN_TTILS_CSMS          FDCAN_TTILS_CSMS_Msk                         /*!<Change of Synchronization Mode Interrupt Line     */

+#define FDCAN_TTILS_SOGS_Pos      (3U)

+#define FDCAN_TTILS_SOGS_Msk      (0x1UL << FDCAN_TTILS_SOGS_Pos)              /*!< 0x00000008 */

+#define FDCAN_TTILS_SOGS          FDCAN_TTILS_SOGS_Msk                         /*!<Start of Gap Interrupt Line                       */

+#define FDCAN_TTILS_RTMIS_Pos     (4U)

+#define FDCAN_TTILS_RTMIS_Msk     (0x1UL << FDCAN_TTILS_RTMIS_Pos)             /*!< 0x00000010 */

+#define FDCAN_TTILS_RTMIS         FDCAN_TTILS_RTMIS_Msk                        /*!<Register Time Mark Interrupt Interrupt Line       */

+#define FDCAN_TTILS_TTMIS_Pos     (5U)

+#define FDCAN_TTILS_TTMIS_Msk     (0x1UL << FDCAN_TTILS_TTMIS_Pos)             /*!< 0x00000020 */

+#define FDCAN_TTILS_TTMIS         FDCAN_TTILS_TTMIS_Msk                        /*!<Trigger Time Mark Event Internal Interrupt Line   */

+#define FDCAN_TTILS_SWES_Pos      (6U)

+#define FDCAN_TTILS_SWES_Msk      (0x1UL << FDCAN_TTILS_SWES_Pos)              /*!< 0x00000040 */

+#define FDCAN_TTILS_SWES          FDCAN_TTILS_SWES_Msk                         /*!<Stop Watch Event Interrupt Line                   */

+#define FDCAN_TTILS_GTWS_Pos      (7U)

+#define FDCAN_TTILS_GTWS_Msk      (0x1UL << FDCAN_TTILS_GTWS_Pos)              /*!< 0x00000080 */

+#define FDCAN_TTILS_GTWS          FDCAN_TTILS_GTWS_Msk                         /*!<Global Time Wrap Interrupt Line                   */

+#define FDCAN_TTILS_GTDS_Pos      (8U)

+#define FDCAN_TTILS_GTDS_Msk      (0x1UL << FDCAN_TTILS_GTDS_Pos)              /*!< 0x00000100 */

+#define FDCAN_TTILS_GTDS          FDCAN_TTILS_GTDS_Msk                         /*!<Global Time Discontinuity Interrupt Line          */

+#define FDCAN_TTILS_GTES_Pos      (9U)

+#define FDCAN_TTILS_GTES_Msk      (0x1UL << FDCAN_TTILS_GTES_Pos)              /*!< 0x00000200 */

+#define FDCAN_TTILS_GTES          FDCAN_TTILS_GTES_Msk                         /*!<Global Time Error Interrupt Line                  */

+#define FDCAN_TTILS_TXUS_Pos      (10U)

+#define FDCAN_TTILS_TXUS_Msk      (0x1UL << FDCAN_TTILS_TXUS_Pos)              /*!< 0x00000400 */

+#define FDCAN_TTILS_TXUS          FDCAN_TTILS_TXUS_Msk                         /*!<Tx Count Underflow Interrupt Line                 */

+#define FDCAN_TTILS_TXOS_Pos      (11U)

+#define FDCAN_TTILS_TXOS_Msk      (0x1UL << FDCAN_TTILS_TXOS_Pos)              /*!< 0x00000800 */

+#define FDCAN_TTILS_TXOS          FDCAN_TTILS_TXOS_Msk                         /*!<Tx Count Overflow Interrupt Line                  */

+#define FDCAN_TTILS_SE1S_Pos      (12U)

+#define FDCAN_TTILS_SE1S_Msk      (0x1UL << FDCAN_TTILS_SE1S_Pos)              /*!< 0x00001000 */

+#define FDCAN_TTILS_SE1S          FDCAN_TTILS_SE1S_Msk                         /*!<Scheduling Error 1 Interrupt Line                 */

+#define FDCAN_TTILS_SE2S_Pos      (13U)

+#define FDCAN_TTILS_SE2S_Msk      (0x1UL << FDCAN_TTILS_SE2S_Pos)              /*!< 0x00002000 */

+#define FDCAN_TTILS_SE2S          FDCAN_TTILS_SE2S_Msk                         /*!<Scheduling Error 2 Interrupt Line                 */

+#define FDCAN_TTILS_ELCS_Pos      (14U)

+#define FDCAN_TTILS_ELCS_Msk      (0x1UL << FDCAN_TTILS_ELCS_Pos)              /*!< 0x00004000 */

+#define FDCAN_TTILS_ELCS          FDCAN_TTILS_ELCS_Msk                         /*!<Error Level Changed Interrupt Line                */

+#define FDCAN_TTILS_IWTS_Pos      (15U)

+#define FDCAN_TTILS_IWTS_Msk      (0x1UL << FDCAN_TTILS_IWTS_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTILS_IWTS          FDCAN_TTILS_IWTS_Msk                         /*!<Initialization Watch Trigger Interrupt Line       */

+#define FDCAN_TTILS_WTS_Pos       (16U)

+#define FDCAN_TTILS_WTS_Msk       (0x1UL << FDCAN_TTILS_WTS_Pos)               /*!< 0x00010000 */

+#define FDCAN_TTILS_WTS           FDCAN_TTILS_WTS_Msk                          /*!<Watch Trigger Interrupt Line                      */

+#define FDCAN_TTILS_AWS_Pos       (17U)

+#define FDCAN_TTILS_AWS_Msk       (0x1UL << FDCAN_TTILS_AWS_Pos)               /*!< 0x00020000 */

+#define FDCAN_TTILS_AWS           FDCAN_TTILS_AWS_Msk                          /*!<Application Watchdog Interrupt Line               */

+#define FDCAN_TTILS_CERS_Pos      (18U)

+#define FDCAN_TTILS_CERS_Msk      (0x1UL << FDCAN_TTILS_CERS_Pos)              /*!< 0x00040000 */

+#define FDCAN_TTILS_CERS          FDCAN_TTILS_CERS_Msk                         /*!<Configuration Error Interrupt Line                */

+

+/*****************  Bit definition for FDCAN_TTOST register  ********************/

+#define FDCAN_TTOST_EL_Pos        (0U)

+#define FDCAN_TTOST_EL_Msk        (0x3UL << FDCAN_TTOST_EL_Pos)                /*!< 0x00000003 */

+#define FDCAN_TTOST_EL            FDCAN_TTOST_EL_Msk                           /*!<Error Level                              */

+#define FDCAN_TTOST_MS_Pos        (2U)

+#define FDCAN_TTOST_MS_Msk        (0x3UL << FDCAN_TTOST_MS_Pos)                /*!< 0x0000000C */

+#define FDCAN_TTOST_MS            FDCAN_TTOST_MS_Msk                           /*!<Master State                             */

+#define FDCAN_TTOST_SYS_Pos       (4U)

+#define FDCAN_TTOST_SYS_Msk       (0x3UL << FDCAN_TTOST_SYS_Pos)               /*!< 0x00000030 */

+#define FDCAN_TTOST_SYS           FDCAN_TTOST_SYS_Msk                          /*!<Synchronization State                    */

+#define FDCAN_TTOST_QGTP_Pos      (6U)

+#define FDCAN_TTOST_QGTP_Msk      (0x1UL << FDCAN_TTOST_QGTP_Pos)              /*!< 0x00000040 */

+#define FDCAN_TTOST_QGTP          FDCAN_TTOST_QGTP_Msk                         /*!<Quality of Global Time Phase             */

+#define FDCAN_TTOST_QCS_Pos       (7U)

+#define FDCAN_TTOST_QCS_Msk       (0x1UL << FDCAN_TTOST_QCS_Pos)               /*!< 0x00000080 */

+#define FDCAN_TTOST_QCS           FDCAN_TTOST_QCS_Msk                          /*!<Quality of Clock Speed                   */

+#define FDCAN_TTOST_RTO_Pos       (8U)

+#define FDCAN_TTOST_RTO_Msk       (0xFFUL << FDCAN_TTOST_RTO_Pos)              /*!< 0x0000FF00 */

+#define FDCAN_TTOST_RTO           FDCAN_TTOST_RTO_Msk                          /*!<Reference Trigger Offset                 */

+#define FDCAN_TTOST_WGTD_Pos      (22U)

+#define FDCAN_TTOST_WGTD_Msk      (0x1UL << FDCAN_TTOST_WGTD_Pos)              /*!< 0x00400000 */

+#define FDCAN_TTOST_WGTD          FDCAN_TTOST_WGTD_Msk                         /*!<Wait for Global Time Discontinuity       */

+#define FDCAN_TTOST_GFI_Pos       (23U)

+#define FDCAN_TTOST_GFI_Msk       (0x1UL << FDCAN_TTOST_GFI_Pos)               /*!< 0x00800000 */

+#define FDCAN_TTOST_GFI           FDCAN_TTOST_GFI_Msk                          /*!<Gap Finished Indicator                   */

+#define FDCAN_TTOST_TMP_Pos       (24U)

+#define FDCAN_TTOST_TMP_Msk       (0x7UL << FDCAN_TTOST_TMP_Pos)               /*!< 0x07000000 */

+#define FDCAN_TTOST_TMP           FDCAN_TTOST_TMP_Msk                          /*!<Time Master Priority                     */

+#define FDCAN_TTOST_GSI_Pos       (27U)

+#define FDCAN_TTOST_GSI_Msk       (0x1UL << FDCAN_TTOST_GSI_Pos)               /*!< 0x08000000 */

+#define FDCAN_TTOST_GSI           FDCAN_TTOST_GSI_Msk                          /*!<Gap Started Indicator                    */

+#define FDCAN_TTOST_WFE_Pos       (28U)

+#define FDCAN_TTOST_WFE_Msk       (0x1UL << FDCAN_TTOST_WFE_Pos)               /*!< 0x10000000 */

+#define FDCAN_TTOST_WFE           FDCAN_TTOST_WFE_Msk                          /*!<Wait for Event                           */

+#define FDCAN_TTOST_AWE_Pos       (29U)

+#define FDCAN_TTOST_AWE_Msk       (0x1UL << FDCAN_TTOST_AWE_Pos)               /*!< 0x20000000 */

+#define FDCAN_TTOST_AWE           FDCAN_TTOST_AWE_Msk                          /*!<Application Watchdog Event               */

+#define FDCAN_TTOST_WECS_Pos      (30U)

+#define FDCAN_TTOST_WECS_Msk      (0x1UL << FDCAN_TTOST_WECS_Pos)              /*!< 0x40000000 */

+#define FDCAN_TTOST_WECS          FDCAN_TTOST_WECS_Msk                         /*!<Wait for External Clock Synchronization  */

+#define FDCAN_TTOST_SPL_Pos       (31U)

+#define FDCAN_TTOST_SPL_Msk       (0x1UL << FDCAN_TTOST_SPL_Pos)               /*!< 0x80000000 */

+#define FDCAN_TTOST_SPL           FDCAN_TTOST_SPL_Msk                          /*!<Schedule Phase Lock                      */

+

+/*****************  Bit definition for FDCAN_TURNA register  ********************/

+#define FDCAN_TURNA_NAV_Pos       (0U)

+#define FDCAN_TURNA_NAV_Msk       (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)           /*!< 0x0003FFFF */

+#define FDCAN_TURNA_NAV           FDCAN_TURNA_NAV_Msk                          /*!<Numerator Actual Value                   */

+

+/*****************  Bit definition for FDCAN_TTLGT register  ********************/

+#define FDCAN_TTLGT_LT_Pos        (0U)

+#define FDCAN_TTLGT_LT_Msk        (0xFFFFUL << FDCAN_TTLGT_LT_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTLGT_LT            FDCAN_TTLGT_LT_Msk                           /*!<Local Time                               */

+#define FDCAN_TTLGT_GT_Pos        (16U)

+#define FDCAN_TTLGT_GT_Msk        (0xFFFFUL << FDCAN_TTLGT_GT_Pos)             /*!< 0xFFFF0000 */

+#define FDCAN_TTLGT_GT            FDCAN_TTLGT_GT_Msk                           /*!<Global Time                              */

+

+/*****************  Bit definition for FDCAN_TTCTC register  ********************/

+#define FDCAN_TTCTC_CT_Pos        (0U)

+#define FDCAN_TTCTC_CT_Msk        (0xFFFFUL << FDCAN_TTCTC_CT_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTCTC_CT            FDCAN_TTCTC_CT_Msk                           /*!<Cycle Time                               */

+#define FDCAN_TTCTC_CC_Pos        (16U)

+#define FDCAN_TTCTC_CC_Msk        (0x3FUL << FDCAN_TTCTC_CC_Pos)               /*!< 0x003F0000 */

+#define FDCAN_TTCTC_CC            FDCAN_TTCTC_CC_Msk                           /*!<Cycle Count                              */

+

+/*****************  Bit definition for FDCAN_TTCPT register  ********************/

+#define FDCAN_TTCPT_CCV_Pos       (0U)

+#define FDCAN_TTCPT_CCV_Msk       (0x3FUL << FDCAN_TTCPT_CCV_Pos)              /*!< 0x0000003F */

+#define FDCAN_TTCPT_CCV           FDCAN_TTCPT_CCV_Msk                          /*!<Cycle Count Value                        */

+#define FDCAN_TTCPT_SWV_Pos       (16U)

+#define FDCAN_TTCPT_SWV_Msk       (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)            /*!< 0xFFFF0000 */

+#define FDCAN_TTCPT_SWV           FDCAN_TTCPT_SWV_Msk                          /*!<Stop Watch Value                         */

+

+/*****************  Bit definition for FDCAN_TTCSM register  ********************/

+#define FDCAN_TTCSM_CSM_Pos       (0U)

+#define FDCAN_TTCSM_CSM_Msk       (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)            /*!< 0x0000FFFF */

+#define FDCAN_TTCSM_CSM           FDCAN_TTCSM_CSM_Msk                          /*!<Cycle Sync Mark                          */

+

+/*****************  Bit definition for FDCAN_TTTS register  *********************/

+#define FDCAN_TTTS_SWTSEL_Pos     (0U)

+#define FDCAN_TTTS_SWTSEL_Msk     (0x3UL << FDCAN_TTTS_SWTSEL_Pos)             /*!< 0x00000003 */

+#define FDCAN_TTTS_SWTSEL         FDCAN_TTTS_SWTSEL_Msk                        /*!<Stop watch trigger input selection       */

+#define FDCAN_TTTS_EVTSEL_Pos     (4U)

+#define FDCAN_TTTS_EVTSEL_Msk     (0x3UL << FDCAN_TTTS_EVTSEL_Pos)             /*!< 0x00000030 */

+#define FDCAN_TTTS_EVTSEL         FDCAN_TTTS_EVTSEL_Msk                        /*!<Event trigger input selection            */

+

+/********************************************************************************/

+/*                                                                              */

+/*                      FDCANCCU (Clock Calibration unit)                       */

+/*                                                                              */

+/********************************************************************************/

+

+/*****************  Bit definition for FDCANCCU_CREL register  ******************/

+#define FDCANCCU_CREL_DAY_Pos        (0U)

+#define FDCANCCU_CREL_DAY_Msk        (0xFFUL << FDCANCCU_CREL_DAY_Pos)         /*!< 0x000000FF */

+#define FDCANCCU_CREL_DAY            FDCANCCU_CREL_DAY_Msk                     /*!<Timestamp Day                           */

+#define FDCANCCU_CREL_MON_Pos        (8U)

+#define FDCANCCU_CREL_MON_Msk        (0xFFUL << FDCANCCU_CREL_MON_Pos)         /*!< 0x0000FF00 */

+#define FDCANCCU_CREL_MON            FDCANCCU_CREL_MON_Msk                     /*!<Timestamp Month                         */

+#define FDCANCCU_CREL_YEAR_Pos       (16U)

+#define FDCANCCU_CREL_YEAR_Msk       (0xFUL << FDCANCCU_CREL_YEAR_Pos)         /*!< 0x000F0000 */

+#define FDCANCCU_CREL_YEAR           FDCANCCU_CREL_YEAR_Msk                    /*!<Timestamp Year                          */

+#define FDCANCCU_CREL_SUBSTEP_Pos    (20U)

+#define FDCANCCU_CREL_SUBSTEP_Msk    (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)      /*!< 0x00F00000 */

+#define FDCANCCU_CREL_SUBSTEP        FDCANCCU_CREL_SUBSTEP_Msk                 /*!<Sub-step of Core release                */

+#define FDCANCCU_CREL_STEP_Pos       (24U)

+#define FDCANCCU_CREL_STEP_Msk       (0xFUL << FDCANCCU_CREL_STEP_Pos)         /*!< 0x0F000000 */

+#define FDCANCCU_CREL_STEP           FDCANCCU_CREL_STEP_Msk                    /*!<Step of Core release                    */

+#define FDCANCCU_CREL_REL_Pos        (28U)

+#define FDCANCCU_CREL_REL_Msk        (0xFUL << FDCANCCU_CREL_REL_Pos)          /*!< 0xF0000000 */

+#define FDCANCCU_CREL_REL            FDCANCCU_CREL_REL_Msk                     /*!<Core release                            */

+

+/*****************  Bit definition for FDCANCCU_CCFG register  ******************/

+#define FDCANCCU_CCFG_TQBT_Pos       (0U)

+#define FDCANCCU_CCFG_TQBT_Msk       (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)        /*!< 0x0000001F */

+#define FDCANCCU_CCFG_TQBT           FDCANCCU_CCFG_TQBT_Msk                    /*!<Time Quanta per Bit Time                */

+#define FDCANCCU_CCFG_BCC_Pos        (6U)

+#define FDCANCCU_CCFG_BCC_Msk        (0x1UL << FDCANCCU_CCFG_BCC_Pos)          /*!< 0x00000040 */

+#define FDCANCCU_CCFG_BCC            FDCANCCU_CCFG_BCC_Msk                     /*!<Bypass Clock Calibration                */

+#define FDCANCCU_CCFG_CFL_Pos        (7U)

+#define FDCANCCU_CCFG_CFL_Msk        (0x1UL << FDCANCCU_CCFG_CFL_Pos)          /*!< 0x00000080 */

+#define FDCANCCU_CCFG_CFL            FDCANCCU_CCFG_CFL_Msk                     /*!<Calibration Field Length                */

+#define FDCANCCU_CCFG_OCPM_Pos       (8U)

+#define FDCANCCU_CCFG_OCPM_Msk       (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)        /*!< 0x0000FF00 */

+#define FDCANCCU_CCFG_OCPM           FDCANCCU_CCFG_OCPM_Msk                    /*!<Oscillator Clock Periods Minimum        */

+#define FDCANCCU_CCFG_CDIV_Pos       (16U)

+#define FDCANCCU_CCFG_CDIV_Msk       (0xFUL << FDCANCCU_CCFG_CDIV_Pos)         /*!< 0x000F0000 */

+#define FDCANCCU_CCFG_CDIV           FDCANCCU_CCFG_CDIV_Msk                    /*!<Clock Divider                           */

+#define FDCANCCU_CCFG_SWR_Pos        (31U)

+#define FDCANCCU_CCFG_SWR_Msk        (0x1UL << FDCANCCU_CCFG_SWR_Pos)          /*!< 0x80000000 */

+#define FDCANCCU_CCFG_SWR            FDCANCCU_CCFG_SWR_Msk                     /*!<Software Reset                          */

+

+/*****************  Bit definition for FDCANCCU_CSTAT register  *****************/

+#define FDCANCCU_CSTAT_OCPC_Pos      (0U)

+#define FDCANCCU_CSTAT_OCPC_Msk      (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)    /*!< 0x0003FFFF */

+#define FDCANCCU_CSTAT_OCPC          FDCANCCU_CSTAT_OCPC_Msk                   /*!<Oscillator Clock Period Counter        */

+#define FDCANCCU_CSTAT_TQC_Pos       (18U)

+#define FDCANCCU_CSTAT_TQC_Msk       (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)       /*!< 0x1FFC0000 */

+#define FDCANCCU_CSTAT_TQC           FDCANCCU_CSTAT_TQC_Msk                    /*!<Time Quanta Counter                    */

+#define FDCANCCU_CSTAT_CALS_Pos      (30U)

+#define FDCANCCU_CSTAT_CALS_Msk      (0x3UL << FDCANCCU_CSTAT_CALS_Pos)        /*!< 0xC0000000 */

+#define FDCANCCU_CSTAT_CALS          FDCANCCU_CSTAT_CALS_Msk                   /*!<Calibration State                      */

+

+/******************  Bit definition for FDCANCCU_CWD register  ******************/

+#define FDCANCCU_CWD_WDC_Pos         (0U)

+#define FDCANCCU_CWD_WDC_Msk         (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)        /*!< 0x0000FFFF */

+#define FDCANCCU_CWD_WDC             FDCANCCU_CWD_WDC_Msk                      /*!<Watchdog Configuration                 */

+#define FDCANCCU_CWD_WDV_Pos         (16U)

+#define FDCANCCU_CWD_WDV_Msk         (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)        /*!< 0xFFFF0000 */

+#define FDCANCCU_CWD_WDV             FDCANCCU_CWD_WDV_Msk                      /*!<Watchdog Value                         */

+

+/******************  Bit definition for FDCANCCU_IR register  *******************/

+#define FDCANCCU_IR_CWE_Pos          (0U)

+#define FDCANCCU_IR_CWE_Msk          (0x1UL << FDCANCCU_IR_CWE_Pos)            /*!< 0x00000001 */

+#define FDCANCCU_IR_CWE              FDCANCCU_IR_CWE_Msk                       /*!<Calibration Watchdog Event             */

+#define FDCANCCU_IR_CSC_Pos          (1U)

+#define FDCANCCU_IR_CSC_Msk          (0x1UL << FDCANCCU_IR_CSC_Pos)            /*!< 0x00000002 */

+#define FDCANCCU_IR_CSC              FDCANCCU_IR_CSC_Msk                       /*!<Calibration State Changed              */

+

+/******************  Bit definition for FDCANCCU_IE register  *******************/

+#define FDCANCCU_IE_CWEE_Pos         (0U)

+#define FDCANCCU_IE_CWEE_Msk         (0x1UL << FDCANCCU_IE_CWEE_Pos)           /*!< 0x00000001 */

+#define FDCANCCU_IE_CWEE             FDCANCCU_IE_CWEE_Msk                      /*!<Calibration Watchdog Event Enable      */

+#define FDCANCCU_IE_CSCE_Pos         (1U)

+#define FDCANCCU_IE_CSCE_Msk         (0x1UL << FDCANCCU_IE_CSCE_Pos)           /*!< 0x00000002 */

+#define FDCANCCU_IE_CSCE             FDCANCCU_IE_CSCE_Msk                      /*!<Calibration State Changed Enable       */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          HDMI-CEC (CEC)                                    */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for CEC_CR register  *********************/

+#define CEC_CR_CECEN_Pos         (0U)

+#define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                   /*!< 0x00000001 */

+#define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                                */

+#define CEC_CR_TXSOM_Pos         (1U)

+#define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                   /*!< 0x00000002 */

+#define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message                   */

+#define CEC_CR_TXEOM_Pos         (2U)

+#define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                   /*!< 0x00000004 */

+#define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message                     */

+

+/*******************  Bit definition for CEC_CFGR register  *******************/

+#define CEC_CFGR_SFT_Pos         (0U)

+#define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                   /*!< 0x00000007 */

+#define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time                      */

+#define CEC_CFGR_RXTOL_Pos       (3U)

+#define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                 /*!< 0x00000008 */

+#define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                             */

+#define CEC_CFGR_BRESTP_Pos      (4U)

+#define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                /*!< 0x00000010 */

+#define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                               */

+#define CEC_CFGR_BREGEN_Pos      (5U)

+#define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                /*!< 0x00000020 */

+#define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation           */

+#define CEC_CFGR_LBPEGEN_Pos     (6U)

+#define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)               /*!< 0x00000040 */

+#define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error generation      */

+#define CEC_CFGR_SFTOPT_Pos      (8U)

+#define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                /*!< 0x00000100 */

+#define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional             */

+#define CEC_CFGR_BRDNOGEN_Pos    (7U)

+#define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)              /*!< 0x00000080 */

+#define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No error generation         */

+#define CEC_CFGR_OAR_Pos         (16U)

+#define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                /*!< 0x7FFF0000 */

+#define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                           */

+#define CEC_CFGR_LSTN_Pos        (31U)

+#define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                  /*!< 0x80000000 */

+#define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                           */

+

+/*******************  Bit definition for CEC_TXDR register  *******************/

+#define CEC_TXDR_TXD_Pos         (0U)

+#define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                  /*!< 0x000000FF */

+#define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                               */

+

+/*******************  Bit definition for CEC_RXDR register  *******************/

+#define CEC_RXDR_RXD_Pos         (0U)

+#define CEC_RXDR_RXD_Msk         (0xFFUL << CEC_RXDR_RXD_Pos)                  /*!< 0x000000FF */

+#define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                              /*!< CEC Rx Data                               */

+

+/*******************  Bit definition for CEC_ISR register  ********************/

+#define CEC_ISR_RXBR_Pos         (0U)

+#define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                   /*!< 0x00000001 */

+#define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                      */

+#define CEC_ISR_RXEND_Pos        (1U)

+#define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                  /*!< 0x00000002 */

+#define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                      */

+#define CEC_ISR_RXOVR_Pos        (2U)

+#define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                  /*!< 0x00000004 */

+#define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                            */

+#define CEC_ISR_BRE_Pos          (3U)

+#define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                    /*!< 0x00000008 */

+#define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                   */

+#define CEC_ISR_SBPE_Pos         (4U)

+#define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                   /*!< 0x00000010 */

+#define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error             */

+#define CEC_ISR_LBPE_Pos         (5U)

+#define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                   /*!< 0x00000020 */

+#define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error              */

+#define CEC_ISR_RXACKE_Pos       (6U)

+#define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                 /*!< 0x00000040 */

+#define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge                */

+#define CEC_ISR_ARBLST_Pos       (7U)

+#define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                 /*!< 0x00000080 */

+#define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                      */

+#define CEC_ISR_TXBR_Pos         (8U)

+#define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                   /*!< 0x00000100 */

+#define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                       */

+#define CEC_ISR_TXEND_Pos        (9U)

+#define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                  /*!< 0x00000200 */

+#define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                   */

+#define CEC_ISR_TXUDR_Pos        (10U)

+#define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                  /*!< 0x00000400 */

+#define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                    */

+#define CEC_ISR_TXERR_Pos        (11U)

+#define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                  /*!< 0x00000800 */

+#define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                              */

+#define CEC_ISR_TXACKE_Pos       (12U)

+#define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                 /*!< 0x00001000 */

+#define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge                */

+

+/*******************  Bit definition for CEC_IER register  ********************/

+#define CEC_IER_RXBRIE_Pos       (0U)

+#define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                 /*!< 0x00000001 */

+#define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable            */

+#define CEC_IER_RXENDIE_Pos      (1U)

+#define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                /*!< 0x00000002 */

+#define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable            */

+#define CEC_IER_RXOVRIE_Pos      (2U)

+#define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                /*!< 0x00000004 */

+#define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable                  */

+#define CEC_IER_BREIE_Pos        (3U)

+#define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                  /*!< 0x00000008 */

+#define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable         */

+#define CEC_IER_SBPEIE_Pos       (4U)

+#define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                 /*!< 0x00000010 */

+#define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable   */

+#define CEC_IER_LBPEIE_Pos       (5U)

+#define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                 /*!< 0x00000020 */

+#define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable    */

+#define CEC_IER_RXACKEIE_Pos     (6U)

+#define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)               /*!< 0x00000040 */

+#define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable      */

+#define CEC_IER_ARBLSTIE_Pos     (7U)

+#define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)               /*!< 0x00000080 */

+#define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable            */

+#define CEC_IER_TXBRIE_Pos       (8U)

+#define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                 /*!< 0x00000100 */

+#define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable            */

+#define CEC_IER_TXENDIE_Pos      (9U)

+#define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                /*!< 0x00000200 */

+#define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable         */

+#define CEC_IER_TXUDRIE_Pos      (10U)

+#define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                /*!< 0x00000400 */

+#define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable          */

+#define CEC_IER_TXERRIE_Pos      (11U)

+#define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                /*!< 0x00000800 */

+#define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                    */

+#define CEC_IER_TXACKEIE_Pos     (12U)

+#define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)               /*!< 0x00001000 */

+#define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable      */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          CRC calculation unit                              */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for CRC_DR register  *********************/

+#define CRC_DR_DR_Pos            (0U)

+#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */

+#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */

+

+/*******************  Bit definition for CRC_IDR register  ********************/

+#define CRC_IDR_IDR_Pos          (0U)

+#define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */

+#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */

+

+/********************  Bit definition for CRC_CR register  ********************/

+#define CRC_CR_RESET_Pos         (0U)

+#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */

+#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */

+#define CRC_CR_POLYSIZE_Pos      (3U)

+#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */

+#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */

+#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */

+#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */

+#define CRC_CR_REV_IN_Pos        (5U)

+#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */

+#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */

+#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */

+#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */

+#define CRC_CR_REV_OUT_Pos       (7U)

+#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */

+#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */

+

+/*******************  Bit definition for CRC_INIT register  *******************/

+#define CRC_INIT_INIT_Pos        (0U)

+#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */

+#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */

+

+/*******************  Bit definition for CRC_POL register  ********************/

+#define CRC_POL_POL_Pos          (0U)

+#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */

+#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          CRS Clock Recovery System                         */

+/******************************************************************************/

+

+/*******************  Bit definition for CRS_CR register  *********************/

+#define CRS_CR_SYNCOKIE_Pos       (0U)

+#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */

+#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */

+#define CRS_CR_SYNCWARNIE_Pos     (1U)

+#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */

+#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */

+#define CRS_CR_ERRIE_Pos          (2U)

+#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */

+#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */

+#define CRS_CR_ESYNCIE_Pos        (3U)

+#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */

+#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */

+#define CRS_CR_CEN_Pos            (5U)

+#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */

+#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */

+#define CRS_CR_AUTOTRIMEN_Pos     (6U)

+#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */

+#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */

+#define CRS_CR_SWSYNC_Pos         (7U)

+#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */

+#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */

+#define CRS_CR_TRIM_Pos           (8U)

+#define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00003F00 */

+#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */

+

+/*******************  Bit definition for CRS_CFGR register  *********************/

+#define CRS_CFGR_RELOAD_Pos       (0U)

+#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */

+#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */

+#define CRS_CFGR_FELIM_Pos        (16U)

+#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */

+#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */

+

+#define CRS_CFGR_SYNCDIV_Pos      (24U)

+#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */

+#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */

+#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */

+#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */

+#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */

+

+#define CRS_CFGR_SYNCSRC_Pos      (28U)

+#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */

+#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */

+#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */

+#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */

+

+#define CRS_CFGR_SYNCPOL_Pos      (31U)

+#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */

+#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */

+

+/*******************  Bit definition for CRS_ISR register  *********************/

+#define CRS_ISR_SYNCOKF_Pos       (0U)

+#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */

+#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */

+#define CRS_ISR_SYNCWARNF_Pos     (1U)

+#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */

+#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */

+#define CRS_ISR_ERRF_Pos          (2U)

+#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */

+#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */

+#define CRS_ISR_ESYNCF_Pos        (3U)

+#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */

+#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */

+#define CRS_ISR_SYNCERR_Pos       (8U)

+#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */

+#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */

+#define CRS_ISR_SYNCMISS_Pos      (9U)

+#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */

+#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */

+#define CRS_ISR_TRIMOVF_Pos       (10U)

+#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */

+#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */

+#define CRS_ISR_FEDIR_Pos         (15U)

+#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */

+#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */

+#define CRS_ISR_FECAP_Pos         (16U)

+#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */

+#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */

+

+/*******************  Bit definition for CRS_ICR register  *********************/

+#define CRS_ICR_SYNCOKC_Pos       (0U)

+#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */

+#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */

+#define CRS_ICR_SYNCWARNC_Pos     (1U)

+#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */

+#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */

+#define CRS_ICR_ERRC_Pos          (2U)

+#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */

+#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */

+#define CRS_ICR_ESYNCC_Pos        (3U)

+#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */

+#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            Crypto Processor                                */

+/*                                                                            */

+/******************************************************************************/

+/********************************  CRYP VER  **********************************/

+#define  CRYP_VER_2_2

+/******************* Bits definition for CRYP_CR register  ********************/

+#define CRYP_CR_ALGODIR_Pos              (2U)

+#define CRYP_CR_ALGODIR_Msk              (0x1UL << CRYP_CR_ALGODIR_Pos)        /*!< 0x00000004 */

+#define CRYP_CR_ALGODIR                  CRYP_CR_ALGODIR_Msk

+

+#define CRYP_CR_ALGOMODE_Pos             (3U)

+#define CRYP_CR_ALGOMODE_Msk             (0x10007UL << CRYP_CR_ALGOMODE_Pos)   /*!< 0x00080038 */

+#define CRYP_CR_ALGOMODE                 CRYP_CR_ALGOMODE_Msk

+#define CRYP_CR_ALGOMODE_0               (0x00001UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000008 */

+#define CRYP_CR_ALGOMODE_1               (0x00002UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000010 */

+#define CRYP_CR_ALGOMODE_2               (0x00004UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000020 */

+#define CRYP_CR_ALGOMODE_TDES_ECB        ((uint32_t)0x00000000)

+#define CRYP_CR_ALGOMODE_TDES_CBC_Pos    (3U)

+#define CRYP_CR_ALGOMODE_TDES_CBC_Msk    (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */

+#define CRYP_CR_ALGOMODE_TDES_CBC        CRYP_CR_ALGOMODE_TDES_CBC_Msk

+#define CRYP_CR_ALGOMODE_DES_ECB_Pos     (4U)

+#define CRYP_CR_ALGOMODE_DES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_DES_ECB_Pos) /*!< 0x00000010 */

+#define CRYP_CR_ALGOMODE_DES_ECB         CRYP_CR_ALGOMODE_DES_ECB_Msk

+#define CRYP_CR_ALGOMODE_DES_CBC_Pos     (3U)

+#define CRYP_CR_ALGOMODE_DES_CBC_Msk     (0x3UL << CRYP_CR_ALGOMODE_DES_CBC_Pos) /*!< 0x00000018 */

+#define CRYP_CR_ALGOMODE_DES_CBC         CRYP_CR_ALGOMODE_DES_CBC_Msk

+#define CRYP_CR_ALGOMODE_AES_ECB_Pos     (5U)

+#define CRYP_CR_ALGOMODE_AES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */

+#define CRYP_CR_ALGOMODE_AES_ECB         CRYP_CR_ALGOMODE_AES_ECB_Msk

+#define CRYP_CR_ALGOMODE_AES_CBC_Pos     (3U)

+#define CRYP_CR_ALGOMODE_AES_CBC_Msk     (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */

+#define CRYP_CR_ALGOMODE_AES_CBC         CRYP_CR_ALGOMODE_AES_CBC_Msk

+#define CRYP_CR_ALGOMODE_AES_CTR_Pos     (4U)

+#define CRYP_CR_ALGOMODE_AES_CTR_Msk     (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */

+#define CRYP_CR_ALGOMODE_AES_CTR         CRYP_CR_ALGOMODE_AES_CTR_Msk

+#define CRYP_CR_ALGOMODE_AES_KEY_Pos     (3U)

+#define CRYP_CR_ALGOMODE_AES_KEY_Msk     (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */

+#define CRYP_CR_ALGOMODE_AES_KEY         CRYP_CR_ALGOMODE_AES_KEY_Msk

+#define CRYP_CR_ALGOMODE_AES_GCM_Pos     (19U)

+#define CRYP_CR_ALGOMODE_AES_GCM_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_GCM_Pos) /*!< 0x00080000 */

+#define CRYP_CR_ALGOMODE_AES_GCM         CRYP_CR_ALGOMODE_AES_GCM_Msk

+#define CRYP_CR_ALGOMODE_AES_CCM_Pos     (3U)

+#define CRYP_CR_ALGOMODE_AES_CCM_Msk     (0x10001UL << CRYP_CR_ALGOMODE_AES_CCM_Pos) /*!< 0x00080008 */

+#define CRYP_CR_ALGOMODE_AES_CCM         CRYP_CR_ALGOMODE_AES_CCM_Msk

+

+#define CRYP_CR_DATATYPE_Pos             (6U)

+#define CRYP_CR_DATATYPE_Msk             (0x3UL << CRYP_CR_DATATYPE_Pos)       /*!< 0x000000C0 */

+#define CRYP_CR_DATATYPE                 CRYP_CR_DATATYPE_Msk

+#define CRYP_CR_DATATYPE_0               (0x1UL << CRYP_CR_DATATYPE_Pos)        /*!< 0x00000040 */

+#define CRYP_CR_DATATYPE_1               (0x2UL << CRYP_CR_DATATYPE_Pos)        /*!< 0x00000080 */

+#define CRYP_CR_KEYSIZE_Pos              (8U)

+#define CRYP_CR_KEYSIZE_Msk              (0x3UL << CRYP_CR_KEYSIZE_Pos)        /*!< 0x00000300 */

+#define CRYP_CR_KEYSIZE                  CRYP_CR_KEYSIZE_Msk

+#define CRYP_CR_KEYSIZE_0                (0x1UL << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000100 */

+#define CRYP_CR_KEYSIZE_1                (0x2UL << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000200 */

+#define CRYP_CR_FFLUSH_Pos               (14U)

+#define CRYP_CR_FFLUSH_Msk               (0x1UL << CRYP_CR_FFLUSH_Pos)         /*!< 0x00004000 */

+#define CRYP_CR_FFLUSH                   CRYP_CR_FFLUSH_Msk

+#define CRYP_CR_CRYPEN_Pos               (15U)

+#define CRYP_CR_CRYPEN_Msk               (0x1UL << CRYP_CR_CRYPEN_Pos)         /*!< 0x00008000 */

+#define CRYP_CR_CRYPEN                   CRYP_CR_CRYPEN_Msk

+

+#define CRYP_CR_GCM_CCMPH_Pos            (16U)

+#define CRYP_CR_GCM_CCMPH_Msk            (0x3UL << CRYP_CR_GCM_CCMPH_Pos)      /*!< 0x00030000 */

+#define CRYP_CR_GCM_CCMPH                CRYP_CR_GCM_CCMPH_Msk

+#define CRYP_CR_GCM_CCMPH_0              (0x1UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00010000 */

+#define CRYP_CR_GCM_CCMPH_1              (0x2UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00020000 */

+#define CRYP_CR_ALGOMODE_3               ((uint32_t)0x00080000)

+#define CRYP_CR_NPBLB_Pos                (20U)

+#define CRYP_CR_NPBLB_Msk                (0xFUL << CRYP_CR_NPBLB_Pos)          /*!< 0x00F00000 */

+#define CRYP_CR_NPBLB                    CRYP_CR_NPBLB_Msk

+

+/****************** Bits definition for CRYP_SR register  *********************/

+#define CRYP_SR_IFEM_Pos                 (0U)

+#define CRYP_SR_IFEM_Msk                 (0x1UL << CRYP_SR_IFEM_Pos)           /*!< 0x00000001 */

+#define CRYP_SR_IFEM                     CRYP_SR_IFEM_Msk

+#define CRYP_SR_IFNF_Pos                 (1U)

+#define CRYP_SR_IFNF_Msk                 (0x1UL << CRYP_SR_IFNF_Pos)           /*!< 0x00000002 */

+#define CRYP_SR_IFNF                     CRYP_SR_IFNF_Msk

+#define CRYP_SR_OFNE_Pos                 (2U)

+#define CRYP_SR_OFNE_Msk                 (0x1UL << CRYP_SR_OFNE_Pos)           /*!< 0x00000004 */

+#define CRYP_SR_OFNE                     CRYP_SR_OFNE_Msk

+#define CRYP_SR_OFFU_Pos                 (3U)

+#define CRYP_SR_OFFU_Msk                 (0x1UL << CRYP_SR_OFFU_Pos)           /*!< 0x00000008 */

+#define CRYP_SR_OFFU                     CRYP_SR_OFFU_Msk

+#define CRYP_SR_BUSY_Pos                 (4U)

+#define CRYP_SR_BUSY_Msk                 (0x1UL << CRYP_SR_BUSY_Pos)           /*!< 0x00000010 */

+#define CRYP_SR_BUSY                     CRYP_SR_BUSY_Msk

+/****************** Bits definition for CRYP_DMACR register  ******************/

+#define CRYP_DMACR_DIEN_Pos              (0U)

+#define CRYP_DMACR_DIEN_Msk              (0x1UL << CRYP_DMACR_DIEN_Pos)        /*!< 0x00000001 */

+#define CRYP_DMACR_DIEN                  CRYP_DMACR_DIEN_Msk

+#define CRYP_DMACR_DOEN_Pos              (1U)

+#define CRYP_DMACR_DOEN_Msk              (0x1UL << CRYP_DMACR_DOEN_Pos)        /*!< 0x00000002 */

+#define CRYP_DMACR_DOEN                  CRYP_DMACR_DOEN_Msk

+/*****************  Bits definition for CRYP_IMSCR register  ******************/

+#define CRYP_IMSCR_INIM_Pos              (0U)

+#define CRYP_IMSCR_INIM_Msk              (0x1UL << CRYP_IMSCR_INIM_Pos)        /*!< 0x00000001 */

+#define CRYP_IMSCR_INIM                  CRYP_IMSCR_INIM_Msk

+#define CRYP_IMSCR_OUTIM_Pos             (1U)

+#define CRYP_IMSCR_OUTIM_Msk             (0x1UL << CRYP_IMSCR_OUTIM_Pos)       /*!< 0x00000002 */

+#define CRYP_IMSCR_OUTIM                 CRYP_IMSCR_OUTIM_Msk

+/****************** Bits definition for CRYP_RISR register  *******************/

+#define CRYP_RISR_INRIS_Pos              (0U)

+#define CRYP_RISR_INRIS_Msk              (0x1UL << CRYP_RISR_INRIS_Pos)        /*!< 0x00000001 */

+#define CRYP_RISR_INRIS                  CRYP_RISR_INRIS_Msk

+#define CRYP_RISR_OUTRIS_Pos             (1U)

+#define CRYP_RISR_OUTRIS_Msk             (0x1UL << CRYP_RISR_OUTRIS_Pos)       /*!< 0x00000002 */

+#define CRYP_RISR_OUTRIS                 CRYP_RISR_OUTRIS_Msk

+/****************** Bits definition for CRYP_MISR register  *******************/

+#define CRYP_MISR_INMIS_Pos              (0U)

+#define CRYP_MISR_INMIS_Msk              (0x1UL << CRYP_MISR_INMIS_Pos)        /*!< 0x00000001 */

+#define CRYP_MISR_INMIS                  CRYP_MISR_INMIS_Msk

+#define CRYP_MISR_OUTMIS_Pos             (1U)

+#define CRYP_MISR_OUTMIS_Msk             (0x1UL << CRYP_MISR_OUTMIS_Pos)       /*!< 0x00000002 */

+#define CRYP_MISR_OUTMIS                 CRYP_MISR_OUTMIS_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                      Digital to Analog Converter                           */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for DAC_CR register  ********************/

+#define DAC_CR_EN1_Pos              (0U)

+#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */

+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */

+#define DAC_CR_TEN1_Pos             (1U)

+#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */

+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */

+

+#define DAC_CR_TSEL1_Pos            (2U)

+#define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */

+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */

+#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000004 */

+#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */

+#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */

+#define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */

+

+

+#define DAC_CR_WAVE1_Pos            (6U)

+#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */

+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */

+#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */

+#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */

+

+#define DAC_CR_MAMP1_Pos            (8U)

+#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */

+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */

+#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */

+#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */

+#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */

+#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */

+

+#define DAC_CR_DMAEN1_Pos           (12U)

+#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */

+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */

+#define DAC_CR_DMAUDRIE1_Pos        (13U)

+#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */

+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/

+#define DAC_CR_CEN1_Pos             (14U)

+#define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */

+#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/

+

+#define DAC_CR_EN2_Pos              (16U)

+#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */

+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */

+#define DAC_CR_TEN2_Pos             (17U)

+#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */

+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */

+

+#define DAC_CR_TSEL2_Pos            (18U)

+#define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */

+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */

+#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00040000 */

+#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */

+#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */

+#define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */

+

+

+#define DAC_CR_WAVE2_Pos            (22U)

+#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */

+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */

+#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */

+#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */

+

+#define DAC_CR_MAMP2_Pos            (24U)

+#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */

+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */

+#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */

+#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */

+#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */

+#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */

+

+#define DAC_CR_DMAEN2_Pos           (28U)

+#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */

+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */

+#define DAC_CR_DMAUDRIE2_Pos        (29U)

+#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */

+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/

+#define DAC_CR_CEN2_Pos             (30U)

+#define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */

+#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/

+

+/*****************  Bit definition for DAC_SWTRIGR register  ******************/

+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)

+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */

+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */

+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)

+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */

+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */

+

+/*****************  Bit definition for DAC_DHR12R1 register  ******************/

+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)

+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12L1 register  ******************/

+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)

+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8R1 register  ******************/

+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)

+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12R2 register  ******************/

+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)

+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12L2 register  ******************/

+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)

+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8R2 register  ******************/

+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)

+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12RD register  ******************/

+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)

+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */

+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)

+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */

+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12LD register  ******************/

+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)

+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */

+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)

+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */

+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8RD register  ******************/

+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)

+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */

+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)

+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */

+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */

+

+/*******************  Bit definition for DAC_DOR1 register  *******************/

+#define DAC_DOR1_DACC1DOR_Pos       (0U)

+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */

+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */

+

+/*******************  Bit definition for DAC_DOR2 register  *******************/

+#define DAC_DOR2_DACC2DOR_Pos       (0U)

+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */

+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */

+

+/********************  Bit definition for DAC_SR register  ********************/

+#define DAC_SR_DMAUDR1_Pos          (13U)

+#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */

+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */

+#define DAC_SR_CAL_FLAG1_Pos        (14U)

+#define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */

+#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */

+#define DAC_SR_BWST1_Pos            (15U)

+#define DAC_SR_BWST1_Msk            (0x4001UL << DAC_SR_BWST1_Pos)             /*!< 0x20008000 */

+#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */

+

+#define DAC_SR_DMAUDR2_Pos          (29U)

+#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */

+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */

+#define DAC_SR_CAL_FLAG2_Pos        (30U)

+#define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */

+#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */

+#define DAC_SR_BWST2_Pos            (31U)

+#define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */

+#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */

+

+/*******************  Bit definition for DAC_CCR register  ********************/

+#define DAC_CCR_OTRIM1_Pos          (0U)

+#define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */

+#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */

+#define DAC_CCR_OTRIM2_Pos          (16U)

+#define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */

+#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */

+

+/*******************  Bit definition for DAC_MCR register  *******************/

+#define DAC_MCR_MODE1_Pos           (0U)

+#define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */

+#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */

+#define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */

+#define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */

+#define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */

+

+#define DAC_MCR_MODE2_Pos           (16U)

+#define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */

+#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */

+#define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */

+#define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */

+#define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */

+

+/******************  Bit definition for DAC_SHSR1 register  ******************/

+#define DAC_SHSR1_TSAMPLE1_Pos      (0U)

+#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */

+#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */

+

+/******************  Bit definition for DAC_SHSR2 register  ******************/

+#define DAC_SHSR2_TSAMPLE2_Pos      (0U)

+#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */

+#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */

+

+/******************  Bit definition for DAC_SHHR register  ******************/

+#define DAC_SHHR_THOLD1_Pos         (0U)

+#define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */

+#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */

+#define DAC_SHHR_THOLD2_Pos         (16U)

+#define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */

+#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */

+

+/******************  Bit definition for DAC_SHRR register  ******************/

+#define DAC_SHRR_TREFRESH1_Pos      (0U)

+#define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */

+#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */

+#define DAC_SHRR_TREFRESH2_Pos      (16U)

+#define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */

+#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    DCMI                                    */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DCMI_CR register  ******************/

+#define DCMI_CR_CAPTURE_Pos        (0U)

+#define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)              /*!< 0x00000001 */

+#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk

+#define DCMI_CR_CM_Pos             (1U)

+#define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                   /*!< 0x00000002 */

+#define DCMI_CR_CM                 DCMI_CR_CM_Msk

+#define DCMI_CR_CROP_Pos           (2U)

+#define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                 /*!< 0x00000004 */

+#define DCMI_CR_CROP               DCMI_CR_CROP_Msk

+#define DCMI_CR_JPEG_Pos           (3U)

+#define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                 /*!< 0x00000008 */

+#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk

+#define DCMI_CR_ESS_Pos            (4U)

+#define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                  /*!< 0x00000010 */

+#define DCMI_CR_ESS                DCMI_CR_ESS_Msk

+#define DCMI_CR_PCKPOL_Pos         (5U)

+#define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)               /*!< 0x00000020 */

+#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk

+#define DCMI_CR_HSPOL_Pos          (6U)

+#define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                /*!< 0x00000040 */

+#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk

+#define DCMI_CR_VSPOL_Pos          (7U)

+#define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */

+#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk

+#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)

+#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)

+#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)

+#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)

+#define DCMI_CR_CRE_Pos            (12U)

+#define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */

+#define DCMI_CR_CRE                DCMI_CR_CRE_Msk

+#define DCMI_CR_ENABLE_Pos         (14U)

+#define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)               /*!< 0x00004000 */

+#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk

+#define DCMI_CR_BSM_Pos            (16U)

+#define DCMI_CR_BSM_Msk            (0x3UL << DCMI_CR_BSM_Pos)                  /*!< 0x00030000 */

+#define DCMI_CR_BSM                DCMI_CR_BSM_Msk

+#define DCMI_CR_BSM_0              (0x1UL << DCMI_CR_BSM_Pos)                   /*!< 0x00010000 */

+#define DCMI_CR_BSM_1              (0x2UL << DCMI_CR_BSM_Pos)                   /*!< 0x00020000 */

+#define DCMI_CR_OEBS_Pos           (18U)

+#define DCMI_CR_OEBS_Msk           (0x1UL << DCMI_CR_OEBS_Pos)                 /*!< 0x00040000 */

+#define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk

+#define DCMI_CR_LSM_Pos            (19U)

+#define DCMI_CR_LSM_Msk            (0x1UL << DCMI_CR_LSM_Pos)                  /*!< 0x00080000 */

+#define DCMI_CR_LSM                DCMI_CR_LSM_Msk

+#define DCMI_CR_OELS_Pos           (20U)

+#define DCMI_CR_OELS_Msk           (0x1UL << DCMI_CR_OELS_Pos)                 /*!< 0x00100000 */

+#define DCMI_CR_OELS               DCMI_CR_OELS_Msk

+

+/********************  Bits definition for DCMI_SR register  ******************/

+#define DCMI_SR_HSYNC_Pos          (0U)

+#define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                /*!< 0x00000001 */

+#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk

+#define DCMI_SR_VSYNC_Pos          (1U)

+#define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                /*!< 0x00000002 */

+#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk

+#define DCMI_SR_FNE_Pos            (2U)

+#define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                  /*!< 0x00000004 */

+#define DCMI_SR_FNE                DCMI_SR_FNE_Msk

+

+/********************  Bits definition for DCMI_RIS register   ****************/

+#define DCMI_RIS_FRAME_RIS_Pos     (0U)

+#define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)           /*!< 0x00000001 */

+#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk

+#define DCMI_RIS_OVR_RIS_Pos       (1U)

+#define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)             /*!< 0x00000002 */

+#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk

+#define DCMI_RIS_ERR_RIS_Pos       (2U)

+#define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)             /*!< 0x00000004 */

+#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk

+#define DCMI_RIS_VSYNC_RIS_Pos     (3U)

+#define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)           /*!< 0x00000008 */

+#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk

+#define DCMI_RIS_LINE_RIS_Pos      (4U)

+#define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)            /*!< 0x00000010 */

+#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk

+

+/********************  Bits definition for DCMI_IER register  *****************/

+#define DCMI_IER_FRAME_IE_Pos      (0U)

+#define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)            /*!< 0x00000001 */

+#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk

+#define DCMI_IER_OVR_IE_Pos        (1U)

+#define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)              /*!< 0x00000002 */

+#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk

+#define DCMI_IER_ERR_IE_Pos        (2U)

+#define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)              /*!< 0x00000004 */

+#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk

+#define DCMI_IER_VSYNC_IE_Pos      (3U)

+#define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)            /*!< 0x00000008 */

+#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk

+#define DCMI_IER_LINE_IE_Pos       (4U)

+#define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)             /*!< 0x00000010 */

+#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk

+

+

+/********************  Bits definition for DCMI_MIS register  *****************/

+#define DCMI_MIS_FRAME_MIS_Pos     (0U)

+#define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)           /*!< 0x00000001 */

+#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk

+#define DCMI_MIS_OVR_MIS_Pos       (1U)

+#define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)             /*!< 0x00000002 */

+#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk

+#define DCMI_MIS_ERR_MIS_Pos       (2U)

+#define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)             /*!< 0x00000004 */

+#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk

+#define DCMI_MIS_VSYNC_MIS_Pos     (3U)

+#define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)           /*!< 0x00000008 */

+#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk

+#define DCMI_MIS_LINE_MIS_Pos      (4U)

+#define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)            /*!< 0x00000010 */

+#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk

+

+

+/********************  Bits definition for DCMI_ICR register  *****************/

+#define DCMI_ICR_FRAME_ISC_Pos     (0U)

+#define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)           /*!< 0x00000001 */

+#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk

+#define DCMI_ICR_OVR_ISC_Pos       (1U)

+#define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)             /*!< 0x00000002 */

+#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk

+#define DCMI_ICR_ERR_ISC_Pos       (2U)

+#define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)             /*!< 0x00000004 */

+#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk

+#define DCMI_ICR_VSYNC_ISC_Pos     (3U)

+#define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)           /*!< 0x00000008 */

+#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk

+#define DCMI_ICR_LINE_ISC_Pos      (4U)

+#define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)            /*!< 0x00000010 */

+#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk

+

+

+/********************  Bits definition for DCMI_ESCR register  ******************/

+#define DCMI_ESCR_FSC_Pos          (0U)

+#define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)               /*!< 0x000000FF */

+#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk

+#define DCMI_ESCR_LSC_Pos          (8U)

+#define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)               /*!< 0x0000FF00 */

+#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk

+#define DCMI_ESCR_LEC_Pos          (16U)

+#define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)               /*!< 0x00FF0000 */

+#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk

+#define DCMI_ESCR_FEC_Pos          (24U)

+#define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)               /*!< 0xFF000000 */

+#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk

+

+/********************  Bits definition for DCMI_ESUR register  ******************/

+#define DCMI_ESUR_FSU_Pos          (0U)

+#define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)               /*!< 0x000000FF */

+#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk

+#define DCMI_ESUR_LSU_Pos          (8U)

+#define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)               /*!< 0x0000FF00 */

+#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk

+#define DCMI_ESUR_LEU_Pos          (16U)

+#define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)               /*!< 0x00FF0000 */

+#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk

+#define DCMI_ESUR_FEU_Pos          (24U)

+#define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)               /*!< 0xFF000000 */

+#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk

+

+/********************  Bits definition for DCMI_CWSTRT register  ******************/

+#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)

+#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)       /*!< 0x00003FFF */

+#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk

+#define DCMI_CWSTRT_VST_Pos        (16U)

+#define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)           /*!< 0x1FFF0000 */

+#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk

+

+/********************  Bits definition for DCMI_CWSIZE register  ******************/

+#define DCMI_CWSIZE_CAPCNT_Pos     (0U)

+#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)        /*!< 0x00003FFF */

+#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk

+#define DCMI_CWSIZE_VLINE_Pos      (16U)

+#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)         /*!< 0x3FFF0000 */

+#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk

+

+/********************  Bits definition for DCMI_DR register  ******************/

+#define DCMI_DR_BYTE0_Pos          (0U)

+#define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)               /*!< 0x000000FF */

+#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk

+#define DCMI_DR_BYTE1_Pos          (8U)

+#define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)               /*!< 0x0000FF00 */

+#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk

+#define DCMI_DR_BYTE2_Pos          (16U)

+#define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)               /*!< 0x00FF0000 */

+#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk

+#define DCMI_DR_BYTE3_Pos          (24U)

+#define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)               /*!< 0xFF000000 */

+#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                 Digital Filter for Sigma Delta Modulators                  */

+/*                                                                            */

+/******************************************************************************/

+

+/****************   DFSDM channel configuration registers  ********************/

+

+/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/

+#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)

+#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)   /*!< 0x80000000 */

+#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */

+#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)

+#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)  /*!< 0x40000000 */

+#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */

+#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)

+#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */

+#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */

+#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)

+#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x0000C000 */

+#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */

+#define DFSDM_CHCFGR1_DATPACK_1         (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */

+#define DFSDM_CHCFGR1_DATPACK_0         (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */

+#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)

+#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00003000 */

+#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */

+#define DFSDM_CHCFGR1_DATMPX_1          (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */

+#define DFSDM_CHCFGR1_DATMPX_0          (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */

+#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)

+#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)   /*!< 0x00000100 */

+#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */

+#define DFSDM_CHCFGR1_CHEN_Pos          (7U)

+#define DFSDM_CHCFGR1_CHEN_Msk          (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)      /*!< 0x00000080 */

+#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */

+#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)

+#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)    /*!< 0x00000040 */

+#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */

+#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)

+#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)     /*!< 0x00000020 */

+#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */

+#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)

+#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x0000000C */

+#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */

+#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */

+#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */

+#define DFSDM_CHCFGR1_SITP_Pos          (0U)

+#define DFSDM_CHCFGR1_SITP_Msk          (0x3UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000003 */

+#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */

+#define DFSDM_CHCFGR1_SITP_1            (0x2UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */

+#define DFSDM_CHCFGR1_SITP_0            (0x1UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */

+

+/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/

+#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)

+#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */

+#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)

+#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)    /*!< 0x000000F8 */

+#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */

+

+/******************  Bit definition for DFSDM_CHAWSCDR register *****************/

+#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)

+#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00C00000 */

+#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */

+#define DFSDM_CHAWSCDR_AWFORD_1         (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */

+#define DFSDM_CHAWSCDR_AWFORD_0         (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */

+#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)

+#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)  /*!< 0x001F0000 */

+#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */

+#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)

+#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)    /*!< 0x0000F000 */

+#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */

+#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)

+#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)    /*!< 0x000000FF */

+#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */

+

+/****************  Bit definition for DFSDM_CHWDATR register *******************/

+#define DFSDM_CHWDATR_WDATA_Pos         (0U)

+#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)  /*!< 0x0000FFFF */

+#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */

+

+/****************  Bit definition for DFSDM_CHDATINR register *****************/

+#define DFSDM_CHDATINR_INDAT0_Pos       (0U)

+#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */

+#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */

+#define DFSDM_CHDATINR_INDAT1_Pos       (16U)

+#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */

+#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */

+

+/****************  Bit definition for DFSDM_CHDLYR register *****************/

+#define DFSDM_CHDLYR_PLSSKP_Pos         (0U)

+#define DFSDM_CHDLYR_PLSSKP_Msk         (0x3FUL << DFSDM_CHDLYR_PLSSKP_Pos)    /*!< 0x0000003F*/

+#define DFSDM_CHDLYR_PLSSKP             DFSDM_CHDLYR_PLSSKP_Msk

+/************************   DFSDM module registers  ****************************/

+

+/********************  Bit definition for DFSDM_FLTCR1 register *******************/

+#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)

+#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)     /*!< 0x40000000 */

+#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */

+#define DFSDM_FLTCR1_FAST_Pos           (29U)

+#define DFSDM_FLTCR1_FAST_Msk           (0x1UL << DFSDM_FLTCR1_FAST_Pos)       /*!< 0x20000000 */

+#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */

+#define DFSDM_FLTCR1_RCH_Pos            (24U)

+#define DFSDM_FLTCR1_RCH_Msk            (0x7UL << DFSDM_FLTCR1_RCH_Pos)        /*!< 0x07000000 */

+#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */

+#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)

+#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)     /*!< 0x00200000 */

+#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */

+#define DFSDM_FLTCR1_RSYNC_Pos          (19U)

+#define DFSDM_FLTCR1_RSYNC_Msk          (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)      /*!< 0x00080000 */

+#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */

+#define DFSDM_FLTCR1_RCONT_Pos          (18U)

+#define DFSDM_FLTCR1_RCONT_Msk          (0x1UL << DFSDM_FLTCR1_RCONT_Pos)      /*!< 0x00040000 */

+#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */

+#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)

+#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)   /*!< 0x00020000 */

+#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */

+#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)

+#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00006000 */

+#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */

+#define DFSDM_FLTCR1_JEXTEN_1           (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */

+#define DFSDM_FLTCR1_JEXTEN_0           (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */

+#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)

+#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)   /*!< 0x00001F00 */

+#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */

+#define DFSDM_FLTCR1_JEXTSEL_0          (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000100 */

+#define DFSDM_FLTCR1_JEXTSEL_1          (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000200 */

+#define DFSDM_FLTCR1_JEXTSEL_2          (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000400 */

+#define DFSDM_FLTCR1_JEXTSEL_3          (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000800 */

+#define DFSDM_FLTCR1_JEXTSEL_4          (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00001000 */

+

+#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)

+#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)     /*!< 0x00000020 */

+#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */

+#define DFSDM_FLTCR1_JSCAN_Pos          (4U)

+#define DFSDM_FLTCR1_JSCAN_Msk          (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)      /*!< 0x00000010 */

+#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */

+#define DFSDM_FLTCR1_JSYNC_Pos          (3U)

+#define DFSDM_FLTCR1_JSYNC_Msk          (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)      /*!< 0x00000008 */

+#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */

+#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)

+#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)   /*!< 0x00000002 */

+#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */

+#define DFSDM_FLTCR1_DFEN_Pos           (0U)

+#define DFSDM_FLTCR1_DFEN_Msk           (0x1UL << DFSDM_FLTCR1_DFEN_Pos)       /*!< 0x00000001 */

+#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */

+

+/********************  Bit definition for DFSDM_FLTCR2 register *******************/

+#define DFSDM_FLTCR2_AWDCH_Pos          (16U)

+#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)     /*!< 0x00FF0000 */

+#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */

+#define DFSDM_FLTCR2_EXCH_Pos           (8U)

+#define DFSDM_FLTCR2_EXCH_Msk           (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)      /*!< 0x0000FF00 */

+#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */

+#define DFSDM_FLTCR2_CKABIE_Pos         (6U)

+#define DFSDM_FLTCR2_CKABIE_Msk         (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)     /*!< 0x00000040 */

+#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */

+#define DFSDM_FLTCR2_SCDIE_Pos          (5U)

+#define DFSDM_FLTCR2_SCDIE_Msk          (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)      /*!< 0x00000020 */

+#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */

+#define DFSDM_FLTCR2_AWDIE_Pos          (4U)

+#define DFSDM_FLTCR2_AWDIE_Msk          (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)      /*!< 0x00000010 */

+#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */

+#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)

+#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)     /*!< 0x00000008 */

+#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */

+#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)

+#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)     /*!< 0x00000004 */

+#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */

+#define DFSDM_FLTCR2_REOCIE_Pos         (1U)

+#define DFSDM_FLTCR2_REOCIE_Msk         (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)     /*!< 0x00000002 */

+#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */

+#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)

+#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)     /*!< 0x00000001 */

+#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */

+

+/********************  Bit definition for DFSDM_FLTISR register *******************/

+#define DFSDM_FLTISR_SCDF_Pos           (24U)

+#define DFSDM_FLTISR_SCDF_Msk           (0xFFUL << DFSDM_FLTISR_SCDF_Pos)      /*!< 0xFF000000 */

+#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */

+#define DFSDM_FLTISR_CKABF_Pos          (16U)

+#define DFSDM_FLTISR_CKABF_Msk          (0xFFUL << DFSDM_FLTISR_CKABF_Pos)     /*!< 0x00FF0000 */

+#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */

+#define DFSDM_FLTISR_RCIP_Pos           (14U)

+#define DFSDM_FLTISR_RCIP_Msk           (0x1UL << DFSDM_FLTISR_RCIP_Pos)       /*!< 0x00004000 */

+#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */

+#define DFSDM_FLTISR_JCIP_Pos           (13U)

+#define DFSDM_FLTISR_JCIP_Msk           (0x1UL << DFSDM_FLTISR_JCIP_Pos)       /*!< 0x00002000 */

+#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */

+#define DFSDM_FLTISR_AWDF_Pos           (4U)

+#define DFSDM_FLTISR_AWDF_Msk           (0x1UL << DFSDM_FLTISR_AWDF_Pos)       /*!< 0x00000010 */

+#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */

+#define DFSDM_FLTISR_ROVRF_Pos          (3U)

+#define DFSDM_FLTISR_ROVRF_Msk          (0x1UL << DFSDM_FLTISR_ROVRF_Pos)      /*!< 0x00000008 */

+#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */

+#define DFSDM_FLTISR_JOVRF_Pos          (2U)

+#define DFSDM_FLTISR_JOVRF_Msk          (0x1UL << DFSDM_FLTISR_JOVRF_Pos)      /*!< 0x00000004 */

+#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */

+#define DFSDM_FLTISR_REOCF_Pos          (1U)

+#define DFSDM_FLTISR_REOCF_Msk          (0x1UL << DFSDM_FLTISR_REOCF_Pos)      /*!< 0x00000002 */

+#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */

+#define DFSDM_FLTISR_JEOCF_Pos          (0U)

+#define DFSDM_FLTISR_JEOCF_Msk          (0x1UL << DFSDM_FLTISR_JEOCF_Pos)      /*!< 0x00000001 */

+#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */

+

+/********************  Bit definition for DFSDM_FLTICR register *******************/

+#define DFSDM_FLTICR_CLRSCDF_Pos        (24U)

+#define DFSDM_FLTICR_CLRSCDF_Msk        (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)   /*!< 0xFF000000 */

+#define DFSDM_FLTICR_CLRSCDF            DFSDM_FLTICR_CLRSCDF_Msk               /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */

+#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)

+#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)  /*!< 0x00FF0000 */

+#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */

+#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)

+#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)   /*!< 0x00000008 */

+#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */

+#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)

+#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)   /*!< 0x00000004 */

+#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */

+

+/*******************  Bit definition for DFSDM_FLTJCHGR register ******************/

+#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)

+#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)    /*!< 0x000000FF */

+#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */

+

+/********************  Bit definition for DFSDM_FLTFCR register *******************/

+#define DFSDM_FLTFCR_FORD_Pos           (29U)

+#define DFSDM_FLTFCR_FORD_Msk           (0x7UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0xE0000000 */

+#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */

+#define DFSDM_FLTFCR_FORD_2             (0x4UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */

+#define DFSDM_FLTFCR_FORD_1             (0x2UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */

+#define DFSDM_FLTFCR_FORD_0             (0x1UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */

+#define DFSDM_FLTFCR_FOSR_Pos           (16U)

+#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)     /*!< 0x03FF0000 */

+#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */

+#define DFSDM_FLTFCR_IOSR_Pos           (0U)

+#define DFSDM_FLTFCR_IOSR_Msk           (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)      /*!< 0x000000FF */

+#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */

+

+/******************  Bit definition for DFSDM_FLTJDATAR register *****************/

+#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)

+#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */

+#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)

+#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */

+#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */

+

+/******************  Bit definition for DFSDM_FLTRDATAR register *****************/

+#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)

+#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */

+#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)

+#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)   /*!< 0x00000010 */

+#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */

+#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)

+#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */

+#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */

+

+/******************  Bit definition for DFSDM_FLTAWHTR register ******************/

+#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)

+#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */

+#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)

+#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)    /*!< 0x0000000F */

+#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */

+

+/******************  Bit definition for DFSDM_FLTAWLTR register ******************/

+#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)

+#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWHT[23:0] Analog watchdog low threshold */

+#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)

+#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)    /*!< 0x0000000F */

+#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */

+

+/******************  Bit definition for DFSDM_FLTAWSR register ******************/

+#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)

+#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)    /*!< 0x0000FF00 */

+#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */

+#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)

+#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)    /*!< 0x000000FF */

+#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */

+

+/******************  Bit definition for DFSDM_FLTAWCFR) register *****************/

+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)

+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */

+#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */

+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)

+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */

+#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */

+

+/******************  Bit definition for DFSDM_FLTEXMAX register ******************/

+#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)

+#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */

+#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)

+#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)  /*!< 0x00000007 */

+#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */

+

+/******************  Bit definition for DFSDM_FLTEXMIN register ******************/

+#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)

+#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */

+#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)

+#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)  /*!< 0x00000007 */

+#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */

+

+/******************  Bit definition for DFSDM_FLTCNVTIMR register ******************/

+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)

+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */

+#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           BDMA Controller                                  */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for BDMA_ISR register  ********************/

+#define BDMA_ISR_GIF0_Pos       (0U)

+#define BDMA_ISR_GIF0_Msk       (0x1UL << BDMA_ISR_GIF0_Pos)                   /*!< 0x00000001 */

+#define BDMA_ISR_GIF0           BDMA_ISR_GIF0_Msk                              /*!< Channel 0 Global interrupt flag */

+#define BDMA_ISR_TCIF0_Pos      (1U)

+#define BDMA_ISR_TCIF0_Msk      (0x1UL << BDMA_ISR_TCIF0_Pos)                  /*!< 0x00000002 */

+#define BDMA_ISR_TCIF0          BDMA_ISR_TCIF0_Msk                             /*!< Channel 0 Transfer Complete flag */

+#define BDMA_ISR_HTIF0_Pos      (2U)

+#define BDMA_ISR_HTIF0_Msk      (0x1UL << BDMA_ISR_HTIF0_Pos)                  /*!< 0x00000004 */

+#define BDMA_ISR_HTIF0          BDMA_ISR_HTIF0_Msk                             /*!< Channel 0 Half Transfer flag */

+#define BDMA_ISR_TEIF0_Pos      (3U)

+#define BDMA_ISR_TEIF0_Msk      (0x1UL << BDMA_ISR_TEIF0_Pos)                  /*!< 0x00000008 */

+#define BDMA_ISR_TEIF0          BDMA_ISR_TEIF0_Msk                             /*!< Channel 0 Transfer Error flag */

+#define BDMA_ISR_GIF1_Pos       (4U)

+#define BDMA_ISR_GIF1_Msk       (0x1UL << BDMA_ISR_GIF1_Pos)                   /*!< 0x00000010 */

+#define BDMA_ISR_GIF1           BDMA_ISR_GIF1_Msk                              /*!< Channel 1 Global interrupt flag */

+#define BDMA_ISR_TCIF1_Pos      (5U)

+#define BDMA_ISR_TCIF1_Msk      (0x1UL << BDMA_ISR_TCIF1_Pos)                  /*!< 0x00000020 */

+#define BDMA_ISR_TCIF1          BDMA_ISR_TCIF1_Msk                             /*!< Channel 1 Transfer Complete flag */

+#define BDMA_ISR_HTIF1_Pos      (6U)

+#define BDMA_ISR_HTIF1_Msk      (0x1UL << BDMA_ISR_HTIF1_Pos)                  /*!< 0x00000040 */

+#define BDMA_ISR_HTIF1          BDMA_ISR_HTIF1_Msk                             /*!< Channel 1 Half Transfer flag */

+#define BDMA_ISR_TEIF1_Pos      (7U)

+#define BDMA_ISR_TEIF1_Msk      (0x1UL << BDMA_ISR_TEIF1_Pos)                  /*!< 0x00000080 */

+#define BDMA_ISR_TEIF1          BDMA_ISR_TEIF1_Msk                             /*!< Channel 1 Transfer Error flag */

+#define BDMA_ISR_GIF2_Pos       (8U)

+#define BDMA_ISR_GIF2_Msk       (0x1UL << BDMA_ISR_GIF2_Pos)                   /*!< 0x00000100 */

+#define BDMA_ISR_GIF2           BDMA_ISR_GIF2_Msk                              /*!< Channel 2 Global interrupt flag */

+#define BDMA_ISR_TCIF2_Pos      (9U)

+#define BDMA_ISR_TCIF2_Msk      (0x1UL << BDMA_ISR_TCIF2_Pos)                  /*!< 0x00000200 */

+#define BDMA_ISR_TCIF2          BDMA_ISR_TCIF2_Msk                             /*!< Channel 2 Transfer Complete flag */

+#define BDMA_ISR_HTIF2_Pos      (10U)

+#define BDMA_ISR_HTIF2_Msk      (0x1UL << BDMA_ISR_HTIF2_Pos)                  /*!< 0x00000400 */

+#define BDMA_ISR_HTIF2          BDMA_ISR_HTIF2_Msk                             /*!< Channel 2 Half Transfer flag */

+#define BDMA_ISR_TEIF2_Pos      (11U)

+#define BDMA_ISR_TEIF2_Msk      (0x1UL << BDMA_ISR_TEIF2_Pos)                  /*!< 0x00000800 */

+#define BDMA_ISR_TEIF2          BDMA_ISR_TEIF2_Msk                             /*!< Channel 2 Transfer Error flag */

+#define BDMA_ISR_GIF3_Pos       (12U)

+#define BDMA_ISR_GIF3_Msk       (0x1UL << BDMA_ISR_GIF3_Pos)                   /*!< 0x00001000 */

+#define BDMA_ISR_GIF3           BDMA_ISR_GIF3_Msk                              /*!< Channel 3 Global interrupt flag */

+#define BDMA_ISR_TCIF3_Pos      (13U)

+#define BDMA_ISR_TCIF3_Msk      (0x1UL << BDMA_ISR_TCIF3_Pos)                  /*!< 0x00002000 */

+#define BDMA_ISR_TCIF3          BDMA_ISR_TCIF3_Msk                             /*!< Channel 3 Transfer Complete flag */

+#define BDMA_ISR_HTIF3_Pos      (14U)

+#define BDMA_ISR_HTIF3_Msk      (0x1UL << BDMA_ISR_HTIF3_Pos)                  /*!< 0x00004000 */

+#define BDMA_ISR_HTIF3          BDMA_ISR_HTIF3_Msk                             /*!< Channel 3 Half Transfer flag */

+#define BDMA_ISR_TEIF3_Pos      (15U)

+#define BDMA_ISR_TEIF3_Msk      (0x1UL << BDMA_ISR_TEIF3_Pos)                  /*!< 0x00008000 */

+#define BDMA_ISR_TEIF3          BDMA_ISR_TEIF3_Msk                             /*!< Channel 3 Transfer Error flag */

+#define BDMA_ISR_GIF4_Pos       (16U)

+#define BDMA_ISR_GIF4_Msk       (0x1UL << BDMA_ISR_GIF4_Pos)                   /*!< 0x00010000 */

+#define BDMA_ISR_GIF4           BDMA_ISR_GIF4_Msk                              /*!< Channel 4 Global interrupt flag */

+#define BDMA_ISR_TCIF4_Pos      (17U)

+#define BDMA_ISR_TCIF4_Msk      (0x1UL << BDMA_ISR_TCIF4_Pos)                  /*!< 0x00020000 */

+#define BDMA_ISR_TCIF4          BDMA_ISR_TCIF4_Msk                             /*!< Channel 4 Transfer Complete flag */

+#define BDMA_ISR_HTIF4_Pos      (18U)

+#define BDMA_ISR_HTIF4_Msk      (0x1UL << BDMA_ISR_HTIF4_Pos)                  /*!< 0x00040000 */

+#define BDMA_ISR_HTIF4          BDMA_ISR_HTIF4_Msk                             /*!< Channel 4 Half Transfer flag */

+#define BDMA_ISR_TEIF4_Pos      (19U)

+#define BDMA_ISR_TEIF4_Msk      (0x1UL << BDMA_ISR_TEIF4_Pos)                  /*!< 0x00080000 */

+#define BDMA_ISR_TEIF4          BDMA_ISR_TEIF4_Msk                             /*!< Channel 4 Transfer Error flag */

+#define BDMA_ISR_GIF5_Pos       (20U)

+#define BDMA_ISR_GIF5_Msk       (0x1UL << BDMA_ISR_GIF5_Pos)                   /*!< 0x00100000 */

+#define BDMA_ISR_GIF5           BDMA_ISR_GIF5_Msk                              /*!< Channel 5 Global interrupt flag */

+#define BDMA_ISR_TCIF5_Pos      (21U)

+#define BDMA_ISR_TCIF5_Msk      (0x1UL << BDMA_ISR_TCIF5_Pos)                  /*!< 0x00200000 */

+#define BDMA_ISR_TCIF5          BDMA_ISR_TCIF5_Msk                             /*!< Channel 5 Transfer Complete flag */

+#define BDMA_ISR_HTIF5_Pos      (22U)

+#define BDMA_ISR_HTIF5_Msk      (0x1UL << BDMA_ISR_HTIF5_Pos)                  /*!< 0x00400000 */

+#define BDMA_ISR_HTIF5          BDMA_ISR_HTIF5_Msk                             /*!< Channel 5 Half Transfer flag */

+#define BDMA_ISR_TEIF5_Pos      (23U)

+#define BDMA_ISR_TEIF5_Msk      (0x1UL << BDMA_ISR_TEIF5_Pos)                  /*!< 0x00800000 */

+#define BDMA_ISR_TEIF5          BDMA_ISR_TEIF5_Msk                             /*!< Channel 5 Transfer Error flag */

+#define BDMA_ISR_GIF6_Pos       (24U)

+#define BDMA_ISR_GIF6_Msk       (0x1UL << BDMA_ISR_GIF6_Pos)                   /*!< 0x01000000 */

+#define BDMA_ISR_GIF6           BDMA_ISR_GIF6_Msk                              /*!< Channel 6 Global interrupt flag */

+#define BDMA_ISR_TCIF6_Pos      (25U)

+#define BDMA_ISR_TCIF6_Msk      (0x1UL << BDMA_ISR_TCIF6_Pos)                  /*!< 0x02000000 */

+#define BDMA_ISR_TCIF6          BDMA_ISR_TCIF6_Msk                             /*!< Channel 6 Transfer Complete flag */

+#define BDMA_ISR_HTIF6_Pos      (26U)

+#define BDMA_ISR_HTIF6_Msk      (0x1UL << BDMA_ISR_HTIF6_Pos)                  /*!< 0x04000000 */

+#define BDMA_ISR_HTIF6          BDMA_ISR_HTIF6_Msk                             /*!< Channel 6 Half Transfer flag */

+#define BDMA_ISR_TEIF6_Pos      (27U)

+#define BDMA_ISR_TEIF6_Msk      (0x1UL << BDMA_ISR_TEIF6_Pos)                  /*!< 0x08000000 */

+#define BDMA_ISR_TEIF6          BDMA_ISR_TEIF6_Msk                             /*!< Channel 6 Transfer Error flag */

+#define BDMA_ISR_GIF7_Pos       (28U)

+#define BDMA_ISR_GIF7_Msk       (0x1UL << BDMA_ISR_GIF7_Pos)                   /*!< 0x10000000 */

+#define BDMA_ISR_GIF7           BDMA_ISR_GIF7_Msk                              /*!< Channel 7 Global interrupt flag */

+#define BDMA_ISR_TCIF7_Pos      (29U)

+#define BDMA_ISR_TCIF7_Msk      (0x1UL << BDMA_ISR_TCIF7_Pos)                  /*!< 0x20000000 */

+#define BDMA_ISR_TCIF7          BDMA_ISR_TCIF7_Msk                             /*!< Channel 7 Transfer Complete flag */

+#define BDMA_ISR_HTIF7_Pos      (30U)

+#define BDMA_ISR_HTIF7_Msk      (0x1UL << BDMA_ISR_HTIF7_Pos)                  /*!< 0x40000000 */

+#define BDMA_ISR_HTIF7          BDMA_ISR_HTIF7_Msk                             /*!< Channel 7 Half Transfer flag */

+#define BDMA_ISR_TEIF7_Pos      (31U)

+#define BDMA_ISR_TEIF7_Msk      (0x1UL << BDMA_ISR_TEIF7_Pos)                  /*!< 0x80000000 */

+#define BDMA_ISR_TEIF7          BDMA_ISR_TEIF7_Msk                             /*!< Channel 7 Transfer Error flag */

+

+/*******************  Bit definition for BDMA_IFCR register  *******************/

+#define BDMA_IFCR_CGIF0_Pos     (0U)

+#define BDMA_IFCR_CGIF0_Msk     (0x1UL << BDMA_IFCR_CGIF0_Pos)                 /*!< 0x00000001 */

+#define BDMA_IFCR_CGIF0         BDMA_IFCR_CGIF0_Msk                            /*!< Channel 0 Global interrupt clearr */

+#define BDMA_IFCR_CTCIF0_Pos    (1U)

+#define BDMA_IFCR_CTCIF0_Msk    (0x1UL << BDMA_IFCR_CTCIF0_Pos)                /*!< 0x00000002 */

+#define BDMA_IFCR_CTCIF0        BDMA_IFCR_CTCIF0_Msk                           /*!< Channel 0 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF0_Pos    (2U)

+#define BDMA_IFCR_CHTIF0_Msk    (0x1UL << BDMA_IFCR_CHTIF0_Pos)                /*!< 0x00000004 */

+#define BDMA_IFCR_CHTIF0        BDMA_IFCR_CHTIF0_Msk                           /*!< Channel 0 Half Transfer clear */

+#define BDMA_IFCR_CTEIF0_Pos    (3U)

+#define BDMA_IFCR_CTEIF0_Msk    (0x1UL << BDMA_IFCR_CTEIF0_Pos)                /*!< 0x00000008 */

+#define BDMA_IFCR_CTEIF0        BDMA_IFCR_CTEIF0_Msk                           /*!< Channel 0 Transfer Error clear */

+#define BDMA_IFCR_CGIF1_Pos     (4U)

+#define BDMA_IFCR_CGIF1_Msk     (0x1UL << BDMA_IFCR_CGIF1_Pos)                 /*!< 0x00000010 */

+#define BDMA_IFCR_CGIF1         BDMA_IFCR_CGIF1_Msk                            /*!< Channel 1 Global interrupt clear */

+#define BDMA_IFCR_CTCIF1_Pos    (5U)

+#define BDMA_IFCR_CTCIF1_Msk    (0x1UL << BDMA_IFCR_CTCIF1_Pos)                /*!< 0x00000020 */

+#define BDMA_IFCR_CTCIF1        BDMA_IFCR_CTCIF1_Msk                           /*!< Channel 1 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF1_Pos    (6U)

+#define BDMA_IFCR_CHTIF1_Msk    (0x1UL << BDMA_IFCR_CHTIF1_Pos)                /*!< 0x00000040 */

+#define BDMA_IFCR_CHTIF1        BDMA_IFCR_CHTIF1_Msk                           /*!< Channel 1 Half Transfer clear */

+#define BDMA_IFCR_CTEIF1_Pos    (7U)

+#define BDMA_IFCR_CTEIF1_Msk    (0x1UL << BDMA_IFCR_CTEIF1_Pos)                /*!< 0x00000080 */

+#define BDMA_IFCR_CTEIF1        BDMA_IFCR_CTEIF1_Msk                           /*!< Channel 1 Transfer Error clear */

+#define BDMA_IFCR_CGIF2_Pos     (8U)

+#define BDMA_IFCR_CGIF2_Msk     (0x1UL << BDMA_IFCR_CGIF2_Pos)                 /*!< 0x00000100 */

+#define BDMA_IFCR_CGIF2         BDMA_IFCR_CGIF2_Msk                            /*!< Channel 2 Global interrupt clear */

+#define BDMA_IFCR_CTCIF2_Pos    (9U)

+#define BDMA_IFCR_CTCIF2_Msk    (0x1UL << BDMA_IFCR_CTCIF2_Pos)                /*!< 0x00000200 */

+#define BDMA_IFCR_CTCIF2        BDMA_IFCR_CTCIF2_Msk                           /*!< Channel 2 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF2_Pos    (10U)

+#define BDMA_IFCR_CHTIF2_Msk    (0x1UL << BDMA_IFCR_CHTIF2_Pos)                /*!< 0x00000400 */

+#define BDMA_IFCR_CHTIF2        BDMA_IFCR_CHTIF2_Msk                           /*!< Channel 2 Half Transfer clear */

+#define BDMA_IFCR_CTEIF2_Pos    (11U)

+#define BDMA_IFCR_CTEIF2_Msk    (0x1UL << BDMA_IFCR_CTEIF2_Pos)                /*!< 0x00000800 */

+#define BDMA_IFCR_CTEIF2        BDMA_IFCR_CTEIF2_Msk                           /*!< Channel 2 Transfer Error clear */

+#define BDMA_IFCR_CGIF3_Pos     (12U)

+#define BDMA_IFCR_CGIF3_Msk     (0x1UL << BDMA_IFCR_CGIF3_Pos)                 /*!< 0x00001000 */

+#define BDMA_IFCR_CGIF3         BDMA_IFCR_CGIF3_Msk                            /*!< Channel 3 Global interrupt clear */

+#define BDMA_IFCR_CTCIF3_Pos    (13U)

+#define BDMA_IFCR_CTCIF3_Msk    (0x1UL << BDMA_IFCR_CTCIF3_Pos)                /*!< 0x00002000 */

+#define BDMA_IFCR_CTCIF3        BDMA_IFCR_CTCIF3_Msk                           /*!< Channel 3 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF3_Pos    (14U)

+#define BDMA_IFCR_CHTIF3_Msk    (0x1UL << BDMA_IFCR_CHTIF3_Pos)                /*!< 0x00004000 */

+#define BDMA_IFCR_CHTIF3        BDMA_IFCR_CHTIF3_Msk                           /*!< Channel 3 Half Transfer clear */

+#define BDMA_IFCR_CTEIF3_Pos    (15U)

+#define BDMA_IFCR_CTEIF3_Msk    (0x1UL << BDMA_IFCR_CTEIF3_Pos)                /*!< 0x00008000 */

+#define BDMA_IFCR_CTEIF3        BDMA_IFCR_CTEIF3_Msk                           /*!< Channel 3 Transfer Error clear */

+#define BDMA_IFCR_CGIF4_Pos     (16U)

+#define BDMA_IFCR_CGIF4_Msk     (0x1UL << BDMA_IFCR_CGIF4_Pos)                 /*!< 0x00010000 */

+#define BDMA_IFCR_CGIF4         BDMA_IFCR_CGIF4_Msk                            /*!< Channel 4 Global interrupt clear */

+#define BDMA_IFCR_CTCIF4_Pos    (17U)

+#define BDMA_IFCR_CTCIF4_Msk    (0x1UL << BDMA_IFCR_CTCIF4_Pos)                /*!< 0x00020000 */

+#define BDMA_IFCR_CTCIF4        BDMA_IFCR_CTCIF4_Msk                           /*!< Channel 4 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF4_Pos    (18U)

+#define BDMA_IFCR_CHTIF4_Msk    (0x1UL << BDMA_IFCR_CHTIF4_Pos)                /*!< 0x00040000 */

+#define BDMA_IFCR_CHTIF4        BDMA_IFCR_CHTIF4_Msk                           /*!< Channel 4 Half Transfer clear */

+#define BDMA_IFCR_CTEIF4_Pos    (19U)

+#define BDMA_IFCR_CTEIF4_Msk    (0x1UL << BDMA_IFCR_CTEIF4_Pos)                /*!< 0x00080000 */

+#define BDMA_IFCR_CTEIF4        BDMA_IFCR_CTEIF4_Msk                           /*!< Channel 4 Transfer Error clear */

+#define BDMA_IFCR_CGIF5_Pos     (20U)

+#define BDMA_IFCR_CGIF5_Msk     (0x1UL << BDMA_IFCR_CGIF5_Pos)                 /*!< 0x00100000 */

+#define BDMA_IFCR_CGIF5         BDMA_IFCR_CGIF5_Msk                            /*!< Channel 5 Global interrupt clear */

+#define BDMA_IFCR_CTCIF5_Pos    (21U)

+#define BDMA_IFCR_CTCIF5_Msk    (0x1UL << BDMA_IFCR_CTCIF5_Pos)                /*!< 0x00200000 */

+#define BDMA_IFCR_CTCIF5        BDMA_IFCR_CTCIF5_Msk                           /*!< Channel 5 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF5_Pos    (22U)

+#define BDMA_IFCR_CHTIF5_Msk    (0x1UL << BDMA_IFCR_CHTIF5_Pos)                /*!< 0x00400000 */

+#define BDMA_IFCR_CHTIF5        BDMA_IFCR_CHTIF5_Msk                           /*!< Channel 5 Half Transfer clear */

+#define BDMA_IFCR_CTEIF5_Pos    (23U)

+#define BDMA_IFCR_CTEIF5_Msk    (0x1UL << BDMA_IFCR_CTEIF5_Pos)                /*!< 0x00800000 */

+#define BDMA_IFCR_CTEIF5        BDMA_IFCR_CTEIF5_Msk                           /*!< Channel 5 Transfer Error clear */

+#define BDMA_IFCR_CGIF6_Pos     (24U)

+#define BDMA_IFCR_CGIF6_Msk     (0x1UL << BDMA_IFCR_CGIF6_Pos)                 /*!< 0x01000000 */

+#define BDMA_IFCR_CGIF6         BDMA_IFCR_CGIF6_Msk                            /*!< Channel 6 Global interrupt clear */

+#define BDMA_IFCR_CTCIF6_Pos    (25U)

+#define BDMA_IFCR_CTCIF6_Msk    (0x1UL << BDMA_IFCR_CTCIF6_Pos)                /*!< 0x02000000 */

+#define BDMA_IFCR_CTCIF6        BDMA_IFCR_CTCIF6_Msk                           /*!< Channel 6 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF6_Pos    (26U)

+#define BDMA_IFCR_CHTIF6_Msk    (0x1UL << BDMA_IFCR_CHTIF6_Pos)                /*!< 0x04000000 */

+#define BDMA_IFCR_CHTIF6        BDMA_IFCR_CHTIF6_Msk                           /*!< Channel 6 Half Transfer clear */

+#define BDMA_IFCR_CTEIF6_Pos    (27U)

+#define BDMA_IFCR_CTEIF6_Msk    (0x1UL << BDMA_IFCR_CTEIF6_Pos)                /*!< 0x08000000 */

+#define BDMA_IFCR_CTEIF6        BDMA_IFCR_CTEIF6_Msk                           /*!< Channel 6 Transfer Error clear */

+#define BDMA_IFCR_CGIF7_Pos     (28U)

+#define BDMA_IFCR_CGIF7_Msk     (0x1UL << BDMA_IFCR_CGIF7_Pos)                 /*!< 0x10000000 */

+#define BDMA_IFCR_CGIF7         BDMA_IFCR_CGIF7_Msk                            /*!< Channel 7 Global interrupt clear */

+#define BDMA_IFCR_CTCIF7_Pos    (29U)

+#define BDMA_IFCR_CTCIF7_Msk    (0x1UL << BDMA_IFCR_CTCIF7_Pos)                /*!< 0x20000000 */

+#define BDMA_IFCR_CTCIF7        BDMA_IFCR_CTCIF7_Msk                           /*!< Channel 7 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF7_Pos    (30U)

+#define BDMA_IFCR_CHTIF7_Msk    (0x1UL << BDMA_IFCR_CHTIF7_Pos)                /*!< 0x40000000 */

+#define BDMA_IFCR_CHTIF7        BDMA_IFCR_CHTIF7_Msk                           /*!< Channel 7 Half Transfer clear */

+#define BDMA_IFCR_CTEIF7_Pos    (31U)

+#define BDMA_IFCR_CTEIF7_Msk    (0x1UL << BDMA_IFCR_CTEIF7_Pos)                /*!< 0x80000000 */

+#define BDMA_IFCR_CTEIF7        BDMA_IFCR_CTEIF7_Msk                           /*!< Channel 7 Transfer Error clear */

+

+/*******************  Bit definition for BDMA_CCR register  ********************/

+#define BDMA_CCR_EN_Pos         (0U)

+#define BDMA_CCR_EN_Msk         (0x1UL << BDMA_CCR_EN_Pos)                     /*!< 0x00000001 */

+#define BDMA_CCR_EN             BDMA_CCR_EN_Msk                                /*!< Channel enable                      */

+#define BDMA_CCR_TCIE_Pos       (1U)

+#define BDMA_CCR_TCIE_Msk       (0x1UL << BDMA_CCR_TCIE_Pos)                   /*!< 0x00000002 */

+#define BDMA_CCR_TCIE           BDMA_CCR_TCIE_Msk                              /*!< Transfer complete interrupt enable  */

+#define BDMA_CCR_HTIE_Pos       (2U)

+#define BDMA_CCR_HTIE_Msk       (0x1UL << BDMA_CCR_HTIE_Pos)                   /*!< 0x00000004 */

+#define BDMA_CCR_HTIE           BDMA_CCR_HTIE_Msk                              /*!< Half Transfer interrupt enable      */

+#define BDMA_CCR_TEIE_Pos       (3U)

+#define BDMA_CCR_TEIE_Msk       (0x1UL << BDMA_CCR_TEIE_Pos)                   /*!< 0x00000008 */

+#define BDMA_CCR_TEIE           BDMA_CCR_TEIE_Msk                              /*!< Transfer error interrupt enable     */

+#define BDMA_CCR_DIR_Pos        (4U)

+#define BDMA_CCR_DIR_Msk        (0x1UL << BDMA_CCR_DIR_Pos)                    /*!< 0x00000010 */

+#define BDMA_CCR_DIR            BDMA_CCR_DIR_Msk                               /*!< Data transfer direction             */

+#define BDMA_CCR_CIRC_Pos       (5U)

+#define BDMA_CCR_CIRC_Msk       (0x1UL << BDMA_CCR_CIRC_Pos)                   /*!< 0x00000020 */

+#define BDMA_CCR_CIRC           BDMA_CCR_CIRC_Msk                              /*!< Circular mode                       */

+#define BDMA_CCR_PINC_Pos       (6U)

+#define BDMA_CCR_PINC_Msk       (0x1UL << BDMA_CCR_PINC_Pos)                   /*!< 0x00000040 */

+#define BDMA_CCR_PINC           BDMA_CCR_PINC_Msk                              /*!< Peripheral increment mode           */

+#define BDMA_CCR_MINC_Pos       (7U)

+#define BDMA_CCR_MINC_Msk       (0x1UL << BDMA_CCR_MINC_Pos)                   /*!< 0x00000080 */

+#define BDMA_CCR_MINC           BDMA_CCR_MINC_Msk                              /*!< Memory increment mode               */

+

+#define BDMA_CCR_PSIZE_Pos      (8U)

+#define BDMA_CCR_PSIZE_Msk      (0x3UL << BDMA_CCR_PSIZE_Pos)                  /*!< 0x00000300 */

+#define BDMA_CCR_PSIZE          BDMA_CCR_PSIZE_Msk                             /*!< PSIZE[1:0] bits (Peripheral size)   */

+#define BDMA_CCR_PSIZE_0        (0x1UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000100 */

+#define BDMA_CCR_PSIZE_1        (0x2UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000200 */

+

+#define BDMA_CCR_MSIZE_Pos      (10U)

+#define BDMA_CCR_MSIZE_Msk      (0x3UL << BDMA_CCR_MSIZE_Pos)                  /*!< 0x00000C00 */

+#define BDMA_CCR_MSIZE          BDMA_CCR_MSIZE_Msk                             /*!< MSIZE[1:0] bits (Memory size)       */

+#define BDMA_CCR_MSIZE_0        (0x1UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000400 */

+#define BDMA_CCR_MSIZE_1        (0x2UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000800 */

+

+#define BDMA_CCR_PL_Pos         (12U)

+#define BDMA_CCR_PL_Msk         (0x3UL << BDMA_CCR_PL_Pos)                     /*!< 0x00003000 */

+#define BDMA_CCR_PL             BDMA_CCR_PL_Msk                                /*!< PL[1:0] bits(Channel Priority level)*/

+#define BDMA_CCR_PL_0           (0x1UL << BDMA_CCR_PL_Pos)                      /*!< 0x00001000 */

+#define BDMA_CCR_PL_1           (0x2UL << BDMA_CCR_PL_Pos)                      /*!< 0x00002000 */

+

+#define BDMA_CCR_MEM2MEM_Pos    (14U)

+#define BDMA_CCR_MEM2MEM_Msk    (0x1UL << BDMA_CCR_MEM2MEM_Pos)                /*!< 0x00004000 */

+#define BDMA_CCR_MEM2MEM        BDMA_CCR_MEM2MEM_Msk                           /*!< Memory to memory mode               */

+#define BDMA_CCR_DBM_Pos        (15U)

+#define BDMA_CCR_DBM_Msk        (0x1UL << BDMA_CCR_DBM_Pos)                    /*!< 0x0000A000 */

+#define BDMA_CCR_DBM            BDMA_CCR_DBM_Msk                               /*!< Memory to memory mode               */

+#define BDMA_CCR_CT_Pos         (16U)

+#define BDMA_CCR_CT_Msk         (0x1UL << BDMA_CCR_CT_Pos)                     /*!< 0x00010000 */

+#define BDMA_CCR_CT             BDMA_CCR_CT_Msk                                /*!< Memory to memory mode               */

+

+/******************  Bit definition for BDMA_CNDTR register  *******************/

+#define BDMA_CNDTR_NDT_Pos      (0U)

+#define BDMA_CNDTR_NDT_Msk      (0xFFFFUL << BDMA_CNDTR_NDT_Pos)               /*!< 0x0000FFFF */

+#define BDMA_CNDTR_NDT          BDMA_CNDTR_NDT_Msk                             /*!< Number of data to Transfer          */

+

+/******************  Bit definition for BDMA_CPAR register  ********************/

+#define BDMA_CPAR_PA_Pos        (0U)

+#define BDMA_CPAR_PA_Msk        (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CPAR_PA            BDMA_CPAR_PA_Msk                               /*!< Peripheral Address                  */

+

+/******************  Bit definition for BDMA_CM0AR register  ********************/

+#define BDMA_CM0AR_MA_Pos        (0U)

+#define BDMA_CM0AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CM0AR_MA            BDMA_CM0AR_MA_Msk                               /*!< Memory Address                      */

+

+/******************  Bit definition for BDMA_CM1AR register  ********************/

+#define BDMA_CM1AR_MA_Pos        (0U)

+#define BDMA_CM1AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CM1AR_MA            BDMA_CM1AR_MA_Msk                               /*!< Memory Address                      */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             DMA Controller                                 */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DMA_SxCR register  *****************/

+#define DMA_SxCR_MBURST_Pos      (23U)

+#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                /*!< 0x01800000 */

+#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk                           /*!< Memory burst transfer configuration */

+#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */

+#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */

+#define DMA_SxCR_PBURST_Pos      (21U)

+#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                /*!< 0x00600000 */

+#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk                           /*!< Peripheral burst transfer configuration */

+#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */

+#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */

+#define DMA_SxCR_TRBUFF_Pos      (20U)

+#define DMA_SxCR_TRBUFF_Msk      (0x1UL << DMA_SxCR_TRBUFF_Pos)                 /*!< 0x00100000 */

+#define DMA_SxCR_TRBUFF          DMA_SxCR_TRBUFF_Msk                            /*!< bufferable transfers enabled/disable */

+#define DMA_SxCR_CT_Pos          (19U)

+#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                    /*!< 0x00080000 */

+#define DMA_SxCR_CT              DMA_SxCR_CT_Msk                               /*!< Current target (only in double buffer mode) */

+#define DMA_SxCR_DBM_Pos         (18U)

+#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                   /*!< 0x00040000 */

+#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk                              /*!< Double buffer mode */

+#define DMA_SxCR_PL_Pos          (16U)

+#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                    /*!< 0x00030000 */

+#define DMA_SxCR_PL              DMA_SxCR_PL_Msk                               /*!< Priority level */

+#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */

+#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */

+#define DMA_SxCR_PINCOS_Pos      (15U)

+#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                /*!< 0x00008000 */

+#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk                           /*!< Peripheral increment offset size */

+#define DMA_SxCR_MSIZE_Pos       (13U)

+#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                 /*!< 0x00006000 */

+#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk                            /*!< Memory data size */

+#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */

+#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */

+#define DMA_SxCR_PSIZE_Pos       (11U)

+#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                 /*!< 0x00001800 */

+#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk                            /*< Peripheral data size */

+#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */

+#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */

+#define DMA_SxCR_MINC_Pos        (10U)

+#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                  /*!< 0x00000400 */

+#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk                             /*!< Memory increment mode */

+#define DMA_SxCR_PINC_Pos        (9U)

+#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                  /*!< 0x00000200 */

+#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk                             /*!< Peripheral increment mode */

+#define DMA_SxCR_CIRC_Pos        (8U)

+#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                  /*!< 0x00000100 */

+#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk                             /*!< Circular mode */

+#define DMA_SxCR_DIR_Pos         (6U)

+#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                   /*!< 0x000000C0 */

+#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk                              /*!< Data transfer direction */

+#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */

+#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */

+#define DMA_SxCR_PFCTRL_Pos      (5U)

+#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                /*!< 0x00000020 */

+#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk                           /*!< Peripheral flow controller */

+#define DMA_SxCR_TCIE_Pos        (4U)

+#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                  /*!< 0x00000010 */

+#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk                             /*!< Transfer complete interrupt enable */

+#define DMA_SxCR_HTIE_Pos        (3U)

+#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                  /*!< 0x00000008 */

+#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk                             /*!< Half transfer interrupt enable */

+#define DMA_SxCR_TEIE_Pos        (2U)

+#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                  /*!< 0x00000004 */

+#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk                             /*!< Transfer error interrupt enable */

+#define DMA_SxCR_DMEIE_Pos       (1U)

+#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                 /*!< 0x00000002 */

+#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk                            /*!< Direct mode error interrupt enable */

+#define DMA_SxCR_EN_Pos          (0U)

+#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                    /*!< 0x00000001 */

+#define DMA_SxCR_EN              DMA_SxCR_EN_Msk                               /*!< Stream enable / flag stream ready when read low */

+

+/********************  Bits definition for DMA_SxCNDTR register  **************/

+#define DMA_SxNDT_Pos            (0U)

+#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                   /*!< 0x0000FFFF */

+#define DMA_SxNDT                DMA_SxNDT_Msk                                 /*!< Number of data items to transfer */

+#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */

+#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */

+#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */

+#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */

+#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */

+#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */

+#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */

+#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */

+#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */

+#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */

+#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */

+#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */

+#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */

+#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */

+#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */

+#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */

+

+/********************  Bits definition for DMA_SxFCR register  ****************/

+#define DMA_SxFCR_FEIE_Pos       (7U)

+#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                 /*!< 0x00000080 */

+#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk                            /*!< FIFO error interrupt enable */

+#define DMA_SxFCR_FS_Pos         (3U)

+#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                   /*!< 0x00000038 */

+#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk                              /*!< FIFO status */

+#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */

+#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */

+#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */

+#define DMA_SxFCR_DMDIS_Pos      (2U)

+#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                /*!< 0x00000004 */

+#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk                           /*!< Direct mode disable */

+#define DMA_SxFCR_FTH_Pos        (0U)

+#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                  /*!< 0x00000003 */

+#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk                             /*!< FIFO threshold selection */

+#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */

+#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */

+

+/********************  Bits definition for DMA_LISR register  *****************/

+#define DMA_LISR_TCIF3_Pos       (27U)

+#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                 /*!< 0x08000000 */

+#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk                            /*!<  Stream 3 transfer complete interrupt flag */

+#define DMA_LISR_HTIF3_Pos       (26U)

+#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                 /*!< 0x04000000 */

+#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk                            /*!<  Stream 3 half transfer interrupt flag */

+#define DMA_LISR_TEIF3_Pos       (25U)

+#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                 /*!< 0x02000000 */

+#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk                            /*!<  Stream 3 transfer error interrupt flag */

+#define DMA_LISR_DMEIF3_Pos      (24U)

+#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                /*!< 0x01000000 */

+#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk                           /*!<  Stream 3 direct mode error interrupt flag */

+#define DMA_LISR_FEIF3_Pos       (22U)

+#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                 /*!< 0x00400000 */

+#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk                            /*!<  Stream 3 FIFO error interrupt flag */

+#define DMA_LISR_TCIF2_Pos       (21U)

+#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                 /*!< 0x00200000 */

+#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk                            /*!<  Stream 2 transfer complete interrupt flag */

+#define DMA_LISR_HTIF2_Pos       (20U)

+#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                 /*!< 0x00100000 */

+#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk                            /*!<  Stream 2 half transfer interrupt flag */

+#define DMA_LISR_TEIF2_Pos       (19U)

+#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                 /*!< 0x00080000 */

+#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk                            /*!<  Stream 2 transfer error interrupt flag */

+#define DMA_LISR_DMEIF2_Pos      (18U)

+#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                /*!< 0x00040000 */

+#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk                           /*!<  Stream 2 direct mode error interrupt flag */

+#define DMA_LISR_FEIF2_Pos       (16U)

+#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                 /*!< 0x00010000 */

+#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk                            /*!<  Stream 2 FIFO error interrupt flag */

+#define DMA_LISR_TCIF1_Pos       (11U)

+#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                 /*!< 0x00000800 */

+#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk                            /*!<  Stream 1 transfer complete interrupt flag */

+#define DMA_LISR_HTIF1_Pos       (10U)

+#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                 /*!< 0x00000400 */

+#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk                            /*!<  Stream 1 half transfer interrupt flag */

+#define DMA_LISR_TEIF1_Pos       (9U)

+#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                 /*!< 0x00000200 */

+#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk                            /*!<  Stream 1 transfer error interrupt flag */

+#define DMA_LISR_DMEIF1_Pos      (8U)

+#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                /*!< 0x00000100 */

+#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk                           /*!<  Stream 1 direct mode error interrupt flag */

+#define DMA_LISR_FEIF1_Pos       (6U)

+#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                 /*!< 0x00000040 */

+#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk                            /*!<  Stream 1 FIFO error interrupt flag */

+#define DMA_LISR_TCIF0_Pos       (5U)

+#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                 /*!< 0x00000020 */

+#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk                            /*!<  Stream 0 transfer complete interrupt flag */

+#define DMA_LISR_HTIF0_Pos       (4U)

+#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                 /*!< 0x00000010 */

+#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk                            /*!<  Stream 0 half transfer interrupt flag */

+#define DMA_LISR_TEIF0_Pos       (3U)

+#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                 /*!< 0x00000008 */

+#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk                            /*!<  Stream 0 transfer error interrupt flag */

+#define DMA_LISR_DMEIF0_Pos      (2U)

+#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                /*!< 0x00000004 */

+#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk                           /*!<  Stream 0 direct mode error interrupt flag */

+#define DMA_LISR_FEIF0_Pos       (0U)

+#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                 /*!< 0x00000001 */

+#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk                            /*!<  Stream 0 FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_HISR register  *****************/

+#define DMA_HISR_TCIF7_Pos       (27U)

+#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                 /*!< 0x08000000 */

+#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk                            /*!<  Stream 7 transfer complete interrupt flag */

+#define DMA_HISR_HTIF7_Pos       (26U)

+#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                 /*!< 0x04000000 */

+#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk                            /*!<  Stream 7 half transfer interrupt flag */

+#define DMA_HISR_TEIF7_Pos       (25U)

+#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                 /*!< 0x02000000 */

+#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk                            /*!<  Stream 7 transfer error interrupt flag */

+#define DMA_HISR_DMEIF7_Pos      (24U)

+#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                /*!< 0x01000000 */

+#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk                           /*!<  Stream 7 direct mode error interrupt flag */

+#define DMA_HISR_FEIF7_Pos       (22U)

+#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                 /*!< 0x00400000 */

+#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk                            /*!<  Stream 7 FIFO error interrupt flag */

+#define DMA_HISR_TCIF6_Pos       (21U)

+#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                 /*!< 0x00200000 */

+#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk                            /*!<  Stream 6 transfer complete interrupt flag */

+#define DMA_HISR_HTIF6_Pos       (20U)

+#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                 /*!< 0x00100000 */

+#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk                            /*!<  Stream 6 half transfer interrupt flag */

+#define DMA_HISR_TEIF6_Pos       (19U)

+#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                 /*!< 0x00080000 */

+#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk                            /*!<  Stream 6 transfer error interrupt flag */

+#define DMA_HISR_DMEIF6_Pos      (18U)

+#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                /*!< 0x00040000 */

+#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk                           /*!<  Stream 6 direct mode error interrupt flag */

+#define DMA_HISR_FEIF6_Pos       (16U)

+#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                 /*!< 0x00010000 */

+#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk                            /*!<  Stream 6 FIFO error interrupt flag */

+#define DMA_HISR_TCIF5_Pos       (11U)

+#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                 /*!< 0x00000800 */

+#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk                            /*!<  Stream 5 transfer complete interrupt flag */

+#define DMA_HISR_HTIF5_Pos       (10U)

+#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                 /*!< 0x00000400 */

+#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk                            /*!<  Stream 5 half transfer interrupt flag */

+#define DMA_HISR_TEIF5_Pos       (9U)

+#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                 /*!< 0x00000200 */

+#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk                            /*!<  Stream 5 transfer error interrupt flag */

+#define DMA_HISR_DMEIF5_Pos      (8U)

+#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                /*!< 0x00000100 */

+#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk                           /*!<  Stream 5 direct mode error interrupt flag */

+#define DMA_HISR_FEIF5_Pos       (6U)

+#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                 /*!< 0x00000040 */

+#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk                            /*!<  Stream 5 FIFO error interrupt flag */

+#define DMA_HISR_TCIF4_Pos       (5U)

+#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                 /*!< 0x00000020 */

+#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk                            /*!<  Stream 4 transfer complete interrupt flag */

+#define DMA_HISR_HTIF4_Pos       (4U)

+#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                 /*!< 0x00000010 */

+#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk                            /*!<  Stream 4 half transfer interrupt flag */

+#define DMA_HISR_TEIF4_Pos       (3U)

+#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                 /*!< 0x00000008 */

+#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk                            /*!<  Stream 4 transfer error interrupt flag */

+#define DMA_HISR_DMEIF4_Pos      (2U)

+#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                /*!< 0x00000004 */

+#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk                           /*!<  Stream 4 direct mode error interrupt flag */

+#define DMA_HISR_FEIF4_Pos       (0U)

+#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                 /*!< 0x00000001 */

+#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk                            /*!<  Stream 4 FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_LIFCR register  ****************/

+#define DMA_LIFCR_CTCIF3_Pos     (27U)

+#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)               /*!< 0x08000000 */

+#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk                          /*!<  Stream 3 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF3_Pos     (26U)

+#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)               /*!< 0x04000000 */

+#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk                          /*!<  Stream 3 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF3_Pos     (25U)

+#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)               /*!< 0x02000000 */

+#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk                          /*!<  Stream 3 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF3_Pos    (24U)

+#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)              /*!< 0x01000000 */

+#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk                         /*!<  Stream 3 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF3_Pos     (22U)

+#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)               /*!< 0x00400000 */

+#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk                          /*!<  Stream 3 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF2_Pos     (21U)

+#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)               /*!< 0x00200000 */

+#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk                          /*!<  Stream 2 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF2_Pos     (20U)

+#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)               /*!< 0x00100000 */

+#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk                          /*!<  Stream 2 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF2_Pos     (19U)

+#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)               /*!< 0x00080000 */

+#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk                          /*!<  Stream 2 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF2_Pos    (18U)

+#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)              /*!< 0x00040000 */

+#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk                         /*!<  Stream 2 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF2_Pos     (16U)

+#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)               /*!< 0x00010000 */

+#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk                          /*!<  Stream 2 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF1_Pos     (11U)

+#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)               /*!< 0x00000800 */

+#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk                          /*!<  Stream 1 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF1_Pos     (10U)

+#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)               /*!< 0x00000400 */

+#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk                          /*!<  Stream 1 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF1_Pos     (9U)

+#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)               /*!< 0x00000200 */

+#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk                          /*!<  Stream 1 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF1_Pos    (8U)

+#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)              /*!< 0x00000100 */

+#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk                         /*!<  Stream 1 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF1_Pos     (6U)

+#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)               /*!< 0x00000040 */

+#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk                          /*!<  Stream 1 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF0_Pos     (5U)

+#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)               /*!< 0x00000020 */

+#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk                          /*!<  Stream 0 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF0_Pos     (4U)

+#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)               /*!< 0x00000010 */

+#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk                          /*!<  Stream 0 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF0_Pos     (3U)

+#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)               /*!< 0x00000008 */

+#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk                          /*!<  Stream 0 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF0_Pos    (2U)

+#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)              /*!< 0x00000004 */

+#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk                         /*!<  Stream 0 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF0_Pos     (0U)

+#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)               /*!< 0x00000001 */

+#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk                          /*!<  Stream 0 clear FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_HIFCR  register  ****************/

+#define DMA_HIFCR_CTCIF7_Pos     (27U)

+#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)               /*!< 0x08000000 */

+#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk                          /*!<  Stream 7 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF7_Pos     (26U)

+#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)               /*!< 0x04000000 */

+#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk                          /*!<  Stream 7 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF7_Pos     (25U)

+#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)               /*!< 0x02000000 */

+#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk                          /*!<  Stream 7 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF7_Pos    (24U)

+#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)              /*!< 0x01000000 */

+#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk                         /*!<  Stream 7 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF7_Pos     (22U)

+#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)               /*!< 0x00400000 */

+#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk                          /*!<  Stream 7 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF6_Pos     (21U)

+#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)               /*!< 0x00200000 */

+#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk                          /*!<  Stream 6 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF6_Pos     (20U)

+#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)               /*!< 0x00100000 */

+#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk                          /*!<  Stream 6 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF6_Pos     (19U)

+#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)               /*!< 0x00080000 */

+#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk                          /*!<  Stream 6 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF6_Pos    (18U)

+#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)              /*!< 0x00040000 */

+#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk                         /*!<  Stream 6 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF6_Pos     (16U)

+#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)               /*!< 0x00010000 */

+#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk                          /*!<  Stream 6 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF5_Pos     (11U)

+#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)               /*!< 0x00000800 */

+#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk                          /*!<  Stream 5 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF5_Pos     (10U)

+#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)               /*!< 0x00000400 */

+#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk                          /*!<  Stream 5 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF5_Pos     (9U)

+#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)               /*!< 0x00000200 */

+#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk                          /*!<  Stream 5 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF5_Pos    (8U)

+#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)              /*!< 0x00000100 */

+#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk                         /*!<  Stream 5 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF5_Pos     (6U)

+#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)               /*!< 0x00000040 */

+#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk                          /*!<  Stream 5 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF4_Pos     (5U)

+#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)               /*!< 0x00000020 */

+#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk                          /*!<  Stream 4 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF4_Pos     (4U)

+#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)               /*!< 0x00000010 */

+#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk                          /*!<  Stream 4 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF4_Pos     (3U)

+#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)               /*!< 0x00000008 */

+#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk                          /*!<  Stream 4 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF4_Pos    (2U)

+#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)              /*!< 0x00000004 */

+#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk                         /*!<  Stream 4 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF4_Pos     (0U)

+#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)               /*!< 0x00000001 */

+#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk                          /*!<  Stream 4 clear FIFO error interrupt flag */

+

+/******************  Bit definition for DMA_SxPAR register  ********************/

+#define DMA_SxPAR_PA_Pos         (0U)

+#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)            /*!< 0xFFFFFFFF */

+#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */

+

+/******************  Bit definition for DMA_SxM0AR register  ********************/

+#define DMA_SxM0AR_M0A_Pos       (0U)

+#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)          /*!< 0xFFFFFFFF */

+#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory 0 Address */

+

+/******************  Bit definition for DMA_SxM1AR register  ********************/

+#define DMA_SxM1AR_M1A_Pos       (0U)

+#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)          /*!< 0xFFFFFFFF */

+#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory 1 Address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             DMAMUX Controller                              */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DMAMUX_CxCR register  **************/

+#define DMAMUX_CxCR_DMAREQ_ID_Pos      (0U)

+#define DMAMUX_CxCR_DMAREQ_ID_Msk      (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)   /*!< 0x000000FF */

+#define DMAMUX_CxCR_DMAREQ_ID          DMAMUX_CxCR_DMAREQ_ID_Msk               /*!<  DMA request identification */

+#define DMAMUX_CxCR_DMAREQ_ID_0        (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000001 */

+#define DMAMUX_CxCR_DMAREQ_ID_1        (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000002 */

+#define DMAMUX_CxCR_DMAREQ_ID_2        (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000004 */

+#define DMAMUX_CxCR_DMAREQ_ID_3        (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000008 */

+#define DMAMUX_CxCR_DMAREQ_ID_4        (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000010 */

+#define DMAMUX_CxCR_DMAREQ_ID_5        (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000020 */

+#define DMAMUX_CxCR_DMAREQ_ID_6        (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000040 */

+#define DMAMUX_CxCR_DMAREQ_ID_7        (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000080 */

+#define DMAMUX_CxCR_SOIE_Pos           (8U)

+#define DMAMUX_CxCR_SOIE_Msk           (0x1UL << DMAMUX_CxCR_SOIE_Pos)         /*!< 0x00000100 */

+#define DMAMUX_CxCR_SOIE               DMAMUX_CxCR_SOIE_Msk                    /*!<  Synchronization overrun interrupt enable */

+#define DMAMUX_CxCR_EGE_Pos            (9U)

+#define DMAMUX_CxCR_EGE_Msk            (0x1UL << DMAMUX_CxCR_EGE_Pos)          /*!< 0x00000200 */

+#define DMAMUX_CxCR_EGE                DMAMUX_CxCR_EGE_Msk                     /*!<  Event generation enable */

+#define DMAMUX_CxCR_SE_Pos             (16U)

+#define DMAMUX_CxCR_SE_Msk             (0x1UL << DMAMUX_CxCR_SE_Pos)           /*!< 0x00010000 */

+#define DMAMUX_CxCR_SE                 DMAMUX_CxCR_SE_Msk                      /*!<  Synchronization enable */

+#define DMAMUX_CxCR_SPOL_Pos           (17U)

+#define DMAMUX_CxCR_SPOL_Msk           (0x3UL << DMAMUX_CxCR_SPOL_Pos)         /*!< 0x00060000 */

+#define DMAMUX_CxCR_SPOL               DMAMUX_CxCR_SPOL_Msk                    /*!<  Synchronization polarity */

+#define DMAMUX_CxCR_SPOL_0             (0x1UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00020000 */

+#define DMAMUX_CxCR_SPOL_1             (0x2UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00040000 */

+#define DMAMUX_CxCR_NBREQ_Pos          (19U)

+#define DMAMUX_CxCR_NBREQ_Msk          (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)       /*!< 0x00F80000 */

+#define DMAMUX_CxCR_NBREQ              DMAMUX_CxCR_NBREQ_Msk                   /*!<  Number of DMA requests minus 1 to forward */

+#define DMAMUX_CxCR_NBREQ_0            (0x01UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00080000 */

+#define DMAMUX_CxCR_NBREQ_1            (0x02UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00100000 */

+#define DMAMUX_CxCR_NBREQ_2            (0x04UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00200000 */

+#define DMAMUX_CxCR_NBREQ_3            (0x08UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00400000 */

+#define DMAMUX_CxCR_NBREQ_4            (0x10UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00800000 */

+#define DMAMUX_CxCR_SYNC_ID_Pos        (24U)

+#define DMAMUX_CxCR_SYNC_ID_Msk        (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)     /*!< 0x1F000000 */

+#define DMAMUX_CxCR_SYNC_ID            DMAMUX_CxCR_SYNC_ID_Msk                 /*!<  Synchronization identification */

+#define DMAMUX_CxCR_SYNC_ID_0          (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x01000000 */

+#define DMAMUX_CxCR_SYNC_ID_1          (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x02000000 */

+#define DMAMUX_CxCR_SYNC_ID_2          (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x04000000 */

+#define DMAMUX_CxCR_SYNC_ID_3          (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x08000000 */

+#define DMAMUX_CxCR_SYNC_ID_4          (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x10000000 */

+

+/********************  Bits definition for DMAMUX_CSR register  **************/

+#define DMAMUX_CSR_SOF0_Pos            (0U)

+#define DMAMUX_CSR_SOF0_Msk            (0x1UL << DMAMUX_CSR_SOF0_Pos)          /*!< 0x00000001 */

+#define DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0_Msk                     /*!< Channel 0 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF1_Pos            (1U)

+#define DMAMUX_CSR_SOF1_Msk            (0x1UL << DMAMUX_CSR_SOF1_Pos)          /*!< 0x00000002 */

+#define DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1_Msk                     /*!< Channel 1 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF2_Pos            (2U)

+#define DMAMUX_CSR_SOF2_Msk            (0x1UL << DMAMUX_CSR_SOF2_Pos)          /*!< 0x00000004 */

+#define DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2_Msk                     /*!< Channel 2 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF3_Pos            (3U)

+#define DMAMUX_CSR_SOF3_Msk            (0x1UL << DMAMUX_CSR_SOF3_Pos)          /*!< 0x00000008 */

+#define DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3_Msk                     /*!< Channel 3 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF4_Pos            (4U)

+#define DMAMUX_CSR_SOF4_Msk            (0x1UL << DMAMUX_CSR_SOF4_Pos)          /*!< 0x00000010 */

+#define DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4_Msk                     /*!< Channel 4 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF5_Pos            (5U)

+#define DMAMUX_CSR_SOF5_Msk            (0x1UL << DMAMUX_CSR_SOF5_Pos)          /*!< 0x00000020 */

+#define DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5_Msk                     /*!< Channel 5 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF6_Pos            (6U)

+#define DMAMUX_CSR_SOF6_Msk            (0x1UL << DMAMUX_CSR_SOF6_Pos)          /*!< 0x00000040 */

+#define DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6_Msk                     /*!< Channel 6 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF7_Pos            (7U)

+#define DMAMUX_CSR_SOF7_Msk            (0x1UL << DMAMUX_CSR_SOF7_Pos)          /*!< 0x00000080 */

+#define DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7_Msk                     /*!< Channel 7 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF8_Pos            (8U)

+#define DMAMUX_CSR_SOF8_Msk            (0x1UL << DMAMUX_CSR_SOF8_Pos)          /*!< 0x00000100 */

+#define DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8_Msk                     /*!< Channel 8 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF9_Pos            (9U)

+#define DMAMUX_CSR_SOF9_Msk            (0x1UL << DMAMUX_CSR_SOF9_Pos)          /*!< 0x00000200 */

+#define DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9_Msk                     /*!< Channel 9 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF10_Pos           (10U)

+#define DMAMUX_CSR_SOF10_Msk           (0x1UL << DMAMUX_CSR_SOF10_Pos)         /*!< 0x00000400 */

+#define DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10_Msk                    /*!< Channel 10 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF11_Pos           (11U)

+#define DMAMUX_CSR_SOF11_Msk           (0x1UL << DMAMUX_CSR_SOF11_Pos)         /*!< 0x00000800 */

+#define DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11_Msk                    /*!< Channel 11 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF12_Pos           (12U)

+#define DMAMUX_CSR_SOF12_Msk           (0x1UL << DMAMUX_CSR_SOF12_Pos)         /*!< 0x00001000 */

+#define DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12_Msk                    /*!< Channel 12 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF13_Pos           (13U)

+#define DMAMUX_CSR_SOF13_Msk           (0x1UL << DMAMUX_CSR_SOF13_Pos)         /*!< 0x00002000 */

+#define DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13_Msk                    /*!< Channel 13 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF14_Pos           (14U)

+#define DMAMUX_CSR_SOF14_Msk           (0x1UL << DMAMUX_CSR_SOF14_Pos)         /*!< 0x00004000 */

+#define DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14_Msk                    /*!< Channel 14 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF15_Pos           (15U)

+#define DMAMUX_CSR_SOF15_Msk           (0x1UL << DMAMUX_CSR_SOF15_Pos)         /*!< 0x00008000 */

+#define DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15_Msk                    /*!< Channel 15 Synchronization overrun event flag */

+

+/********************  Bits definition for DMAMUX_CFR register  **************/

+#define DMAMUX_CFR_CSOF0_Pos           (0U)

+#define DMAMUX_CFR_CSOF0_Msk           (0x1UL << DMAMUX_CFR_CSOF0_Pos)         /*!< 0x00000001 */

+#define DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0_Msk                    /*!< Channel 0 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF1_Pos           (1U)

+#define DMAMUX_CFR_CSOF1_Msk           (0x1UL << DMAMUX_CFR_CSOF1_Pos)         /*!< 0x00000002 */

+#define DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1_Msk                    /*!< Channel 1 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF2_Pos           (2U)

+#define DMAMUX_CFR_CSOF2_Msk           (0x1UL << DMAMUX_CFR_CSOF2_Pos)         /*!< 0x00000004 */

+#define DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2_Msk                    /*!< Channel 2 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF3_Pos           (3U)

+#define DMAMUX_CFR_CSOF3_Msk           (0x1UL << DMAMUX_CFR_CSOF3_Pos)         /*!< 0x00000008 */

+#define DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3_Msk                    /*!< Channel 3 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF4_Pos           (4U)

+#define DMAMUX_CFR_CSOF4_Msk           (0x1UL << DMAMUX_CFR_CSOF4_Pos)         /*!< 0x00000010 */

+#define DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4_Msk                    /*!< Channel 4 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF5_Pos           (5U)

+#define DMAMUX_CFR_CSOF5_Msk           (0x1UL << DMAMUX_CFR_CSOF5_Pos)         /*!< 0x00000020 */

+#define DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5_Msk                    /*!< Channel 5 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF6_Pos           (6U)

+#define DMAMUX_CFR_CSOF6_Msk           (0x1UL << DMAMUX_CFR_CSOF6_Pos)         /*!< 0x00000040 */

+#define DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6_Msk                    /*!< Channel 6 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF7_Pos           (7U)

+#define DMAMUX_CFR_CSOF7_Msk           (0x1UL << DMAMUX_CFR_CSOF7_Pos)         /*!< 0x00000080 */

+#define DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7_Msk                    /*!< Channel 7 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF8_Pos           (8U)

+#define DMAMUX_CFR_CSOF8_Msk           (0x1UL << DMAMUX_CFR_CSOF8_Pos)         /*!< 0x00000100 */

+#define DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8_Msk                    /*!< Channel 8 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF9_Pos           (9U)

+#define DMAMUX_CFR_CSOF9_Msk           (0x1UL << DMAMUX_CFR_CSOF9_Pos)         /*!< 0x00000200 */

+#define DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9_Msk                    /*!< Channel 9 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF10_Pos          (10U)

+#define DMAMUX_CFR_CSOF10_Msk          (0x1UL << DMAMUX_CFR_CSOF10_Pos)        /*!< 0x00000400 */

+#define DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10_Msk                   /*!< Channel 10 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF11_Pos          (11U)

+#define DMAMUX_CFR_CSOF11_Msk          (0x1UL << DMAMUX_CFR_CSOF11_Pos)        /*!< 0x00000800 */

+#define DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11_Msk                   /*!< Channel 11 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF12_Pos          (12U)

+#define DMAMUX_CFR_CSOF12_Msk          (0x1UL << DMAMUX_CFR_CSOF12_Pos)        /*!< 0x00001000 */

+#define DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12_Msk                   /*!< Channel 12 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF13_Pos          (13U)

+#define DMAMUX_CFR_CSOF13_Msk          (0x1UL << DMAMUX_CFR_CSOF13_Pos)        /*!< 0x00002000 */

+#define DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13_Msk                   /*!< Channel 13 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF14_Pos          (14U)

+#define DMAMUX_CFR_CSOF14_Msk          (0x1UL << DMAMUX_CFR_CSOF14_Pos)        /*!< 0x00004000 */

+#define DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14_Msk                   /*!< Channel 14 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF15_Pos          (15U)

+#define DMAMUX_CFR_CSOF15_Msk          (0x1UL << DMAMUX_CFR_CSOF15_Pos)        /*!< 0x00008000 */

+#define DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15_Msk                   /*!< Channel 15 Clear synchronization overrun event flag */

+

+/********************  Bits definition for DMAMUX_RGxCR register  ************/

+#define DMAMUX_RGxCR_SIG_ID_Pos        (0U)

+#define DMAMUX_RGxCR_SIG_ID_Msk        (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)     /*!< 0x0000001F */

+#define DMAMUX_RGxCR_SIG_ID            DMAMUX_RGxCR_SIG_ID_Msk                 /*!< Signal identification */

+#define DMAMUX_RGxCR_SIG_ID_0          (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000001 */

+#define DMAMUX_RGxCR_SIG_ID_1          (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000002 */

+#define DMAMUX_RGxCR_SIG_ID_2          (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000004 */

+#define DMAMUX_RGxCR_SIG_ID_3          (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000008 */

+#define DMAMUX_RGxCR_SIG_ID_4          (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000010 */

+#define DMAMUX_RGxCR_OIE_Pos           (8U)

+#define DMAMUX_RGxCR_OIE_Msk           (0x1UL << DMAMUX_RGxCR_OIE_Pos)         /*!< 0x00000100 */

+#define DMAMUX_RGxCR_OIE               DMAMUX_RGxCR_OIE_Msk                    /*!< Trigger overrun interrupt enable */

+#define DMAMUX_RGxCR_GE_Pos            (16U)

+#define DMAMUX_RGxCR_GE_Msk            (0x1UL << DMAMUX_RGxCR_GE_Pos)          /*!< 0x00010000 */

+#define DMAMUX_RGxCR_GE                DMAMUX_RGxCR_GE_Msk                     /*!< DMA request generator enable */

+#define DMAMUX_RGxCR_GPOL_Pos          (17U)

+#define DMAMUX_RGxCR_GPOL_Msk          (0x3UL << DMAMUX_RGxCR_GPOL_Pos)        /*!< 0x00060000 */

+#define DMAMUX_RGxCR_GPOL              DMAMUX_RGxCR_GPOL_Msk                   /*!< DMA request generator trigger polarity */

+#define DMAMUX_RGxCR_GPOL_0            (0x1UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00020000 */

+#define DMAMUX_RGxCR_GPOL_1            (0x2UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00040000 */

+#define DMAMUX_RGxCR_GNBREQ_Pos        (19U)

+#define DMAMUX_RGxCR_GNBREQ_Msk        (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)     /*!< 0x00F80000 */

+#define DMAMUX_RGxCR_GNBREQ            DMAMUX_RGxCR_GNBREQ_Msk                 /*!< Number of DMA requests to be generated */

+#define DMAMUX_RGxCR_GNBREQ_0          (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00080000 */

+#define DMAMUX_RGxCR_GNBREQ_1          (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00100000 */

+#define DMAMUX_RGxCR_GNBREQ_2          (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00200000 */

+#define DMAMUX_RGxCR_GNBREQ_3          (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00400000 */

+#define DMAMUX_RGxCR_GNBREQ_4          (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00800000 */

+

+/********************  Bits definition for DMAMUX_RGSR register  **************/

+#define DMAMUX_RGSR_OF0_Pos            (0U)

+#define DMAMUX_RGSR_OF0_Msk            (0x1UL << DMAMUX_RGSR_OF0_Pos)          /*!< 0x00000001 */

+#define DMAMUX_RGSR_OF0                DMAMUX_RGSR_OF0_Msk                     /*!< Request generator channel 0 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF1_Pos            (1U)

+#define DMAMUX_RGSR_OF1_Msk            (0x1UL << DMAMUX_RGSR_OF1_Pos)          /*!< 0x00000002 */

+#define DMAMUX_RGSR_OF1                DMAMUX_RGSR_OF1_Msk                     /*!< Request generator channel 1 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF2_Pos            (2U)

+#define DMAMUX_RGSR_OF2_Msk            (0x1UL << DMAMUX_RGSR_OF2_Pos)          /*!< 0x00000004 */

+#define DMAMUX_RGSR_OF2                DMAMUX_RGSR_OF2_Msk                     /*!< Request generator channel 2 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF3_Pos            (3U)

+#define DMAMUX_RGSR_OF3_Msk            (0x1UL << DMAMUX_RGSR_OF3_Pos)          /*!< 0x00000008 */

+#define DMAMUX_RGSR_OF3                DMAMUX_RGSR_OF3_Msk                     /*!< Request generator channel 3 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF4_Pos            (4U)

+#define DMAMUX_RGSR_OF4_Msk            (0x1UL << DMAMUX_RGSR_OF4_Pos)          /*!< 0x00000010 */

+#define DMAMUX_RGSR_OF4                DMAMUX_RGSR_OF4_Msk                     /*!< Request generator channel 4 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF5_Pos            (5U)

+#define DMAMUX_RGSR_OF5_Msk            (0x1UL << DMAMUX_RGSR_OF5_Pos)          /*!< 0x00000020 */

+#define DMAMUX_RGSR_OF5                DMAMUX_RGSR_OF5_Msk                     /*!< Request generator channel 5 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF6_Pos            (6U)

+#define DMAMUX_RGSR_OF6_Msk            (0x1UL << DMAMUX_RGSR_OF6_Pos)          /*!< 0x00000040 */

+#define DMAMUX_RGSR_OF6                DMAMUX_RGSR_OF6_Msk                     /*!< Request generator channel 6 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF7_Pos            (7U)

+#define DMAMUX_RGSR_OF7_Msk            (0x1UL << DMAMUX_RGSR_OF7_Pos)          /*!< 0x00000080 */

+#define DMAMUX_RGSR_OF7                DMAMUX_RGSR_OF7_Msk                     /*!< Request generator channel 7 Trigger overrun event flag */

+

+/********************  Bits definition for DMAMUX_RGCFR register  **************/

+#define DMAMUX_RGCFR_COF0_Pos          (0U)

+#define DMAMUX_RGCFR_COF0_Msk          (0x1UL << DMAMUX_RGCFR_COF0_Pos)        /*!< 0x00000001 */

+#define DMAMUX_RGCFR_COF0              DMAMUX_RGCFR_COF0_Msk                   /*!< Request generator channel 0 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF1_Pos          (1U)

+#define DMAMUX_RGCFR_COF1_Msk          (0x1UL << DMAMUX_RGCFR_COF1_Pos)        /*!< 0x00000002 */

+#define DMAMUX_RGCFR_COF1              DMAMUX_RGCFR_COF1_Msk                   /*!< Request generator channel 1 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF2_Pos          (2U)

+#define DMAMUX_RGCFR_COF2_Msk          (0x1UL << DMAMUX_RGCFR_COF2_Pos)        /*!< 0x00000004 */

+#define DMAMUX_RGCFR_COF2              DMAMUX_RGCFR_COF2_Msk                   /*!< Request generator channel 2 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF3_Pos          (3U)

+#define DMAMUX_RGCFR_COF3_Msk          (0x1UL << DMAMUX_RGCFR_COF3_Pos)        /*!< 0x00000008 */

+#define DMAMUX_RGCFR_COF3              DMAMUX_RGCFR_COF3_Msk                   /*!< Request generator channel 3 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF4_Pos          (4U)

+#define DMAMUX_RGCFR_COF4_Msk          (0x1UL << DMAMUX_RGCFR_COF4_Pos)        /*!< 0x00000010 */

+#define DMAMUX_RGCFR_COF4              DMAMUX_RGCFR_COF4_Msk                   /*!< Request generator channel 4 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF5_Pos          (5U)

+#define DMAMUX_RGCFR_COF5_Msk          (0x1UL << DMAMUX_RGCFR_COF5_Pos)        /*!< 0x00000020 */

+#define DMAMUX_RGCFR_COF5              DMAMUX_RGCFR_COF5_Msk                   /*!< Request generator channel 5 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF6_Pos          (6U)

+#define DMAMUX_RGCFR_COF6_Msk          (0x1UL << DMAMUX_RGCFR_COF6_Pos)        /*!< 0x00000040 */

+#define DMAMUX_RGCFR_COF6              DMAMUX_RGCFR_COF6_Msk                   /*!< Request generator channel 6 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF7_Pos          (7U)

+#define DMAMUX_RGCFR_COF7_Msk          (0x1UL << DMAMUX_RGCFR_COF7_Pos)        /*!< 0x00000080 */

+#define DMAMUX_RGCFR_COF7              DMAMUX_RGCFR_COF7_Msk                   /*!< Request generator channel 7 Clear trigger overrun event flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         AHB Master DMA2D Controller (DMA2D)                */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for DMA2D_CR register  ******************/

+

+#define DMA2D_CR_START_Pos         (0U)

+#define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)               /*!< 0x00000001 */

+#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer                          */

+#define DMA2D_CR_SUSP_Pos          (1U)

+#define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                /*!< 0x00000002 */

+#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer                        */

+#define DMA2D_CR_ABORT_Pos         (2U)

+#define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)               /*!< 0x00000004 */

+#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer                          */

+#define DMA2D_CR_LOM_Pos           (6U)

+#define DMA2D_CR_LOM_Msk           (0x1UL << DMA2D_CR_LOM_Pos)                 /*!< 0x00000040 */

+#define DMA2D_CR_LOM               DMA2D_CR_LOM_Msk                            /*!< Line Offset Mode                         */

+#define DMA2D_CR_TEIE_Pos          (8U)

+#define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                /*!< 0x00000100 */

+#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable         */

+#define DMA2D_CR_TCIE_Pos          (9U)

+#define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                /*!< 0x00000200 */

+#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable      */

+#define DMA2D_CR_TWIE_Pos          (10U)

+#define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                /*!< 0x00000400 */

+#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable     */

+#define DMA2D_CR_CAEIE_Pos         (11U)

+#define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)               /*!< 0x00000800 */

+#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable      */

+#define DMA2D_CR_CTCIE_Pos         (12U)

+#define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)               /*!< 0x00001000 */

+#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */

+#define DMA2D_CR_CEIE_Pos          (13U)

+#define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                /*!< 0x00002000 */

+#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable    */

+#define DMA2D_CR_MODE_Pos          (16U)

+#define DMA2D_CR_MODE_Msk          (0x7UL << DMA2D_CR_MODE_Pos)                /*!< 0x00070000 */

+#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[2:0]                         */

+#define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */

+#define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */

+#define DMA2D_CR_MODE_2            (0x4UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00040000 */

+

+/********************  Bit definition for DMA2D_ISR register  *****************/

+

+#define DMA2D_ISR_TEIF_Pos         (0U)

+#define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)               /*!< 0x00000001 */

+#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag         */

+#define DMA2D_ISR_TCIF_Pos         (1U)

+#define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)               /*!< 0x00000002 */

+#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag      */

+#define DMA2D_ISR_TWIF_Pos         (2U)

+#define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)               /*!< 0x00000004 */

+#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag     */

+#define DMA2D_ISR_CAEIF_Pos        (3U)

+#define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)              /*!< 0x00000008 */

+#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag      */

+#define DMA2D_ISR_CTCIF_Pos        (4U)

+#define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)              /*!< 0x00000010 */

+#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */

+#define DMA2D_ISR_CEIF_Pos         (5U)

+#define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)               /*!< 0x00000020 */

+#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag    */

+

+/********************  Bit definition for DMA2D_IFCR register  ****************/

+

+#define DMA2D_IFCR_CTEIF_Pos       (0U)

+#define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)             /*!< 0x00000001 */

+#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */

+#define DMA2D_IFCR_CTCIF_Pos       (1U)

+#define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)             /*!< 0x00000002 */

+#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */

+#define DMA2D_IFCR_CTWIF_Pos       (2U)

+#define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)             /*!< 0x00000004 */

+#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */

+#define DMA2D_IFCR_CAECIF_Pos      (3U)

+#define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)            /*!< 0x00000008 */

+#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */

+#define DMA2D_IFCR_CCTCIF_Pos      (4U)

+#define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)            /*!< 0x00000010 */

+#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */

+#define DMA2D_IFCR_CCEIF_Pos       (5U)

+#define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)             /*!< 0x00000020 */

+#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */

+

+/********************  Bit definition for DMA2D_FGMAR register  ***************/

+

+#define DMA2D_FGMAR_MA_Pos         (0U)

+#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)        /*!< 0xFFFFFFFF */

+#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Foreground Memory Address */

+

+/********************  Bit definition for DMA2D_FGOR register  ****************/

+

+#define DMA2D_FGOR_LO_Pos          (0U)

+#define DMA2D_FGOR_LO_Msk          (0xFFFFUL << DMA2D_FGOR_LO_Pos)             /*!< 0x0000FFFF */

+#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */

+

+/********************  Bit definition for DMA2D_BGMAR register  ***************/

+

+#define DMA2D_BGMAR_MA_Pos         (0U)

+#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)        /*!< 0xFFFFFFFF */

+#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Background Memory Address */

+

+/********************  Bit definition for DMA2D_BGOR register  ****************/

+

+#define DMA2D_BGOR_LO_Pos          (0U)

+#define DMA2D_BGOR_LO_Msk          (0xFFFFUL << DMA2D_BGOR_LO_Pos)             /*!< 0x0000FFFF */

+#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */

+

+/********************  Bit definition for DMA2D_FGPFCCR register  *************/

+

+#define DMA2D_FGPFCCR_CM_Pos       (0U)

+#define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x0000000F */

+#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */

+#define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */

+#define DMA2D_FGPFCCR_CCM_Pos      (4U)

+#define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)            /*!< 0x00000010 */

+#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */

+#define DMA2D_FGPFCCR_START_Pos    (5U)

+#define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)          /*!< 0x00000020 */

+#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */

+#define DMA2D_FGPFCCR_CS_Pos       (8U)

+#define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)            /*!< 0x0000FF00 */

+#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */

+#define DMA2D_FGPFCCR_AM_Pos       (16U)

+#define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00030000 */

+#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */

+#define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */

+#define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */

+#define DMA2D_FGPFCCR_CSS_Pos      (18U)

+#define DMA2D_FGPFCCR_CSS_Msk      (0x3UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x000C0000 */

+#define DMA2D_FGPFCCR_CSS          DMA2D_FGPFCCR_CSS_Msk                       /* !< Chroma Sub-Sampling */

+#define DMA2D_FGPFCCR_CSS_0        (0x1UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00040000 */

+#define DMA2D_FGPFCCR_CSS_1        (0x2UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00080000 */

+#define DMA2D_FGPFCCR_AI_Pos       (20U)

+#define DMA2D_FGPFCCR_AI_Msk       (0x1UL << DMA2D_FGPFCCR_AI_Pos)             /*!< 0x00100000 */

+#define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Foreground Input Alpha Inverted */

+#define DMA2D_FGPFCCR_RBS_Pos      (21U)

+#define DMA2D_FGPFCCR_RBS_Msk      (0x1UL << DMA2D_FGPFCCR_RBS_Pos)            /*!< 0x00200000 */

+#define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Foreground Input Red Blue Swap */

+#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)

+#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */

+#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */

+

+/********************  Bit definition for DMA2D_FGCOLR register  **************/

+

+#define DMA2D_FGCOLR_BLUE_Pos      (0U)

+#define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)           /*!< 0x000000FF */

+#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Foreground Blue Value */

+#define DMA2D_FGCOLR_GREEN_Pos     (8U)

+#define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */

+#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Foreground Green Value */

+#define DMA2D_FGCOLR_RED_Pos       (16U)

+#define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)            /*!< 0x00FF0000 */

+#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Foreground Red Value */

+

+/********************  Bit definition for DMA2D_BGPFCCR register  *************/

+

+#define DMA2D_BGPFCCR_CM_Pos       (0U)

+#define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x0000000F */

+#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */

+#define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_BGPFCCR_CM_3         (0x8UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000008 */

+#define DMA2D_BGPFCCR_CCM_Pos      (4U)

+#define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)            /*!< 0x00000010 */

+#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */

+#define DMA2D_BGPFCCR_START_Pos    (5U)

+#define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)          /*!< 0x00000020 */

+#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */

+#define DMA2D_BGPFCCR_CS_Pos       (8U)

+#define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)            /*!< 0x0000FF00 */

+#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */

+#define DMA2D_BGPFCCR_AM_Pos       (16U)

+#define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00030000 */

+#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */

+#define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */

+#define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */

+#define DMA2D_BGPFCCR_AI_Pos       (20U)

+#define DMA2D_BGPFCCR_AI_Msk       (0x1UL << DMA2D_BGPFCCR_AI_Pos)             /*!< 0x00100000 */

+#define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< background Input Alpha Inverted */

+#define DMA2D_BGPFCCR_RBS_Pos      (21U)

+#define DMA2D_BGPFCCR_RBS_Msk      (0x1UL << DMA2D_BGPFCCR_RBS_Pos)            /*!< 0x00200000 */

+#define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Background Input Red Blue Swap */

+#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)

+#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */

+#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */

+

+/********************  Bit definition for DMA2D_BGCOLR register  **************/

+

+#define DMA2D_BGCOLR_BLUE_Pos      (0U)

+#define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)           /*!< 0x000000FF */

+#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Background Blue Value */

+#define DMA2D_BGCOLR_GREEN_Pos     (8U)

+#define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */

+#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Background Green Value */

+#define DMA2D_BGCOLR_RED_Pos       (16U)

+#define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)            /*!< 0x00FF0000 */

+#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Background Red Value */

+

+/********************  Bit definition for DMA2D_FGCMAR register  **************/

+

+#define DMA2D_FGCMAR_MA_Pos        (0U)

+#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */

+#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Foreground CLUT Memory Address */

+

+/********************  Bit definition for DMA2D_BGCMAR register  **************/

+

+#define DMA2D_BGCMAR_MA_Pos        (0U)

+#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */

+#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Background CLUT Memory Address */

+

+/********************  Bit definition for DMA2D_OPFCCR register  **************/

+

+#define DMA2D_OPFCCR_CM_Pos        (0U)

+#define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000007 */

+#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Output Color mode CM[2:0] */

+#define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_OPFCCR_SB_Pos        (8U)

+#define DMA2D_OPFCCR_SB_Msk        (0x1UL << DMA2D_OPFCCR_SB_Pos)              /*!< 0x00000100 */

+#define DMA2D_OPFCCR_SB            DMA2D_OPFCCR_SB_Msk                         /*!< Swap Bytes */

+#define DMA2D_OPFCCR_AI_Pos        (20U)

+#define DMA2D_OPFCCR_AI_Msk        (0x1UL << DMA2D_OPFCCR_AI_Pos)              /*!< 0x00100000 */

+#define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Output Alpha Inverted */

+#define DMA2D_OPFCCR_RBS_Pos       (21U)

+#define DMA2D_OPFCCR_RBS_Msk       (0x1UL << DMA2D_OPFCCR_RBS_Pos)             /*!< 0x00200000 */

+#define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Output Red Blue Swap */

+

+/********************  Bit definition for DMA2D_OCOLR register  ***************/

+

+/*!<Mode_ARGB8888/RGB888 */

+

+#define DMA2D_OCOLR_BLUE_1_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_1_Msk     (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos)            /*0x000000FFU*/

+#define DMA2D_OCOLR_BLUE_1         DMA2D_OCOLR_BLUE_1_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_1_Pos    (8U)

+#define DMA2D_OCOLR_GREEN_1_Msk    (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos)            /*0x0000FF00U)*/

+#define DMA2D_OCOLR_GREEN_1        DMA2D_OCOLR_GREEN_1_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_1_Pos      (16U)

+#define DMA2D_OCOLR_RED_1_Msk      (0xFFUL << DMA2D_OCOLR_RED_1_Pos)            /*0x00FF0000U */

+#define DMA2D_OCOLR_RED_1          DMA2D_OCOLR_RED_1_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_1_Pos    (24U)

+#define DMA2D_OCOLR_ALPHA_1_Msk    (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos)          /*0xFF000000U*/

+#define DMA2D_OCOLR_ALPHA_1        DMA2D_OCOLR_ALPHA_1_Msk                     /*!< Output Alpha Channel Value */

+

+/*!<Mode_RGB565 */

+#define DMA2D_OCOLR_BLUE_2_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_2_Msk     (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos)            /*0x0000001FU*/

+#define DMA2D_OCOLR_BLUE_2         DMA2D_OCOLR_BLUE_2_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_2_Pos    (5U)

+#define DMA2D_OCOLR_GREEN_2_Msk    (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos)          /* 0x000007E0U */

+#define DMA2D_OCOLR_GREEN_2        DMA2D_OCOLR_GREEN_2_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_2_Pos      (11U)

+#define DMA2D_OCOLR_RED_2_Msk      (0xF8UL<<DMA2D_OCOLR_RED_2_Pos)              /*0x0000F800U*/

+#define DMA2D_OCOLR_RED_2          DMA2D_OCOLR_RED_2_Msk                       /*!< Output Red Value */

+

+/*!<Mode_ARGB1555 */

+#define DMA2D_OCOLR_BLUE_3_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_3_Msk     (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos)           /*0x0000001FU*/

+#define DMA2D_OCOLR_BLUE_3         DMA2D_OCOLR_BLUE_3_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_3_Pos    (5U)

+#define DMA2D_OCOLR_GREEN_3_Msk    (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos)          /*0x000003E0U*/

+#define DMA2D_OCOLR_GREEN_3        DMA2D_OCOLR_GREEN_3_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_3_Pos      (10U)

+#define DMA2D_OCOLR_RED_3_Msk      (0x7CUL << DMA2D_OCOLR_RED_3_Pos)            /* 0x00007C00U*/

+#define DMA2D_OCOLR_RED_3          DMA2D_OCOLR_RED_3_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_3_Pos    (15U)

+#define DMA2D_OCOLR_ALPHA_3_Msk    (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos)           /*0x00008000U*/

+#define DMA2D_OCOLR_ALPHA_3        DMA2D_OCOLR_ALPHA_3_Msk                     /*!< Output Alpha Channel Value */

+

+/*!<Mode_ARGB4444 */

+#define DMA2D_OCOLR_BLUE_4_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_4_Msk     (0xFUL << DMA2D_OCOLR_BLUE_4_Pos)            /*0x0000000FU*/

+#define DMA2D_OCOLR_BLUE_4         DMA2D_OCOLR_BLUE_4_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_4_Pos    (4U)

+#define DMA2D_OCOLR_GREEN_4_Msk    (0xFUL << DMA2D_OCOLR_GREEN_4_Pos)           /*0x000000F0U*/

+#define DMA2D_OCOLR_GREEN_4        DMA2D_OCOLR_GREEN_4_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_4_Pos      (8U)

+#define DMA2D_OCOLR_RED_4_Msk      (0xFUL << DMA2D_OCOLR_RED_4_Pos)             /*0x00000F00U*/

+#define DMA2D_OCOLR_RED_4          DMA2D_OCOLR_RED_4_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_4_Pos    (12U)

+#define DMA2D_OCOLR_ALPHA_4_Msk    (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos)            /*0x0000F000U*/

+#define DMA2D_OCOLR_ALPHA_4        DMA2D_OCOLR_ALPHA_4_Msk                     /*!< Output Alpha Channel Value */

+

+/********************  Bit definition for DMA2D_OMAR register  ****************/

+

+#define DMA2D_OMAR_MA_Pos          (0U)

+#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)         /*!< 0xFFFFFFFF */

+#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Output Memory Address */

+

+/********************  Bit definition for DMA2D_OOR register  *****************/

+

+#define DMA2D_OOR_LO_Pos           (0U)

+#define DMA2D_OOR_LO_Msk           (0xFFFFUL << DMA2D_OOR_LO_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Output Line Offset */

+

+/********************  Bit definition for DMA2D_NLR register  *****************/

+

+#define DMA2D_NLR_NL_Pos           (0U)

+#define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */

+#define DMA2D_NLR_PL_Pos           (16U)

+#define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)              /*!< 0x3FFF0000 */

+#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */

+

+/********************  Bit definition for DMA2D_LWR register  *****************/

+

+#define DMA2D_LWR_LW_Pos           (0U)

+#define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */

+

+/********************  Bit definition for DMA2D_AMTCR register  ***************/

+

+#define DMA2D_AMTCR_EN_Pos         (0U)

+#define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)               /*!< 0x00000001 */

+#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */

+#define DMA2D_AMTCR_DT_Pos         (8U)

+#define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)              /*!< 0x0000FF00 */

+#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */

+

+

+/********************  Bit definition for DMA2D_FGCLUT register  **************/

+

+/********************  Bit definition for DMA2D_BGCLUT register  **************/

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                    External Interrupt/Event Controller                     */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for EXTI_RTSR1 register  *******************/

+#define EXTI_RTSR1_TR_Pos          (0U)

+#define EXTI_RTSR1_TR_Msk          (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)           /*!< 0x003FFFFF */

+#define EXTI_RTSR1_TR              EXTI_RTSR1_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR1_TR0_Pos         (0U)

+#define EXTI_RTSR1_TR0_Msk         (0x1UL << EXTI_RTSR1_TR0_Pos)               /*!< 0x00000001 */

+#define EXTI_RTSR1_TR0             EXTI_RTSR1_TR0_Msk                          /*!< Rising trigger event configuration bit of line 0 */

+#define EXTI_RTSR1_TR1_Pos         (1U)

+#define EXTI_RTSR1_TR1_Msk         (0x1UL << EXTI_RTSR1_TR1_Pos)               /*!< 0x00000002 */

+#define EXTI_RTSR1_TR1             EXTI_RTSR1_TR1_Msk                          /*!< Rising trigger event configuration bit of line 1 */

+#define EXTI_RTSR1_TR2_Pos         (2U)

+#define EXTI_RTSR1_TR2_Msk         (0x1UL << EXTI_RTSR1_TR2_Pos)               /*!< 0x00000004 */

+#define EXTI_RTSR1_TR2             EXTI_RTSR1_TR2_Msk                          /*!< Rising trigger event configuration bit of line 2 */

+#define EXTI_RTSR1_TR3_Pos         (3U)

+#define EXTI_RTSR1_TR3_Msk         (0x1UL << EXTI_RTSR1_TR3_Pos)               /*!< 0x00000008 */

+#define EXTI_RTSR1_TR3             EXTI_RTSR1_TR3_Msk                          /*!< Rising trigger event configuration bit of line 3 */

+#define EXTI_RTSR1_TR4_Pos         (4U)

+#define EXTI_RTSR1_TR4_Msk         (0x1UL << EXTI_RTSR1_TR4_Pos)               /*!< 0x00000010 */

+#define EXTI_RTSR1_TR4             EXTI_RTSR1_TR4_Msk                          /*!< Rising trigger event configuration bit of line 4 */

+#define EXTI_RTSR1_TR5_Pos         (5U)

+#define EXTI_RTSR1_TR5_Msk         (0x1UL << EXTI_RTSR1_TR5_Pos)               /*!< 0x00000020 */

+#define EXTI_RTSR1_TR5             EXTI_RTSR1_TR5_Msk                          /*!< Rising trigger event configuration bit of line 5 */

+#define EXTI_RTSR1_TR6_Pos         (6U)

+#define EXTI_RTSR1_TR6_Msk         (0x1UL << EXTI_RTSR1_TR6_Pos)               /*!< 0x00000040 */

+#define EXTI_RTSR1_TR6             EXTI_RTSR1_TR6_Msk                          /*!< Rising trigger event configuration bit of line 6 */

+#define EXTI_RTSR1_TR7_Pos         (7U)

+#define EXTI_RTSR1_TR7_Msk         (0x1UL << EXTI_RTSR1_TR7_Pos)               /*!< 0x00000080 */

+#define EXTI_RTSR1_TR7             EXTI_RTSR1_TR7_Msk                          /*!< Rising trigger event configuration bit of line 7 */

+#define EXTI_RTSR1_TR8_Pos         (8U)

+#define EXTI_RTSR1_TR8_Msk         (0x1UL << EXTI_RTSR1_TR8_Pos)               /*!< 0x00000100 */

+#define EXTI_RTSR1_TR8             EXTI_RTSR1_TR8_Msk                          /*!< Rising trigger event configuration bit of line 8 */

+#define EXTI_RTSR1_TR9_Pos         (9U)

+#define EXTI_RTSR1_TR9_Msk         (0x1UL << EXTI_RTSR1_TR9_Pos)               /*!< 0x00000200 */

+#define EXTI_RTSR1_TR9             EXTI_RTSR1_TR9_Msk                          /*!< Rising trigger event configuration bit of line 9 */

+#define EXTI_RTSR1_TR10_Pos        (10U)

+#define EXTI_RTSR1_TR10_Msk        (0x1UL << EXTI_RTSR1_TR10_Pos)              /*!< 0x00000400 */

+#define EXTI_RTSR1_TR10            EXTI_RTSR1_TR10_Msk                         /*!< Rising trigger event configuration bit of line 10 */

+#define EXTI_RTSR1_TR11_Pos        (11U)

+#define EXTI_RTSR1_TR11_Msk        (0x1UL << EXTI_RTSR1_TR11_Pos)              /*!< 0x00000800 */

+#define EXTI_RTSR1_TR11            EXTI_RTSR1_TR11_Msk                         /*!< Rising trigger event configuration bit of line 11 */

+#define EXTI_RTSR1_TR12_Pos        (12U)

+#define EXTI_RTSR1_TR12_Msk        (0x1UL << EXTI_RTSR1_TR12_Pos)              /*!< 0x00001000 */

+#define EXTI_RTSR1_TR12            EXTI_RTSR1_TR12_Msk                         /*!< Rising trigger event configuration bit of line 12 */

+#define EXTI_RTSR1_TR13_Pos        (13U)

+#define EXTI_RTSR1_TR13_Msk        (0x1UL << EXTI_RTSR1_TR13_Pos)              /*!< 0x00002000 */

+#define EXTI_RTSR1_TR13            EXTI_RTSR1_TR13_Msk                         /*!< Rising trigger event configuration bit of line 13 */

+#define EXTI_RTSR1_TR14_Pos        (14U)

+#define EXTI_RTSR1_TR14_Msk        (0x1UL << EXTI_RTSR1_TR14_Pos)              /*!< 0x00004000 */

+#define EXTI_RTSR1_TR14            EXTI_RTSR1_TR14_Msk                         /*!< Rising trigger event configuration bit of line 14 */

+#define EXTI_RTSR1_TR15_Pos        (15U)

+#define EXTI_RTSR1_TR15_Msk        (0x1UL << EXTI_RTSR1_TR15_Pos)              /*!< 0x00008000 */

+#define EXTI_RTSR1_TR15            EXTI_RTSR1_TR15_Msk                         /*!< Rising trigger event configuration bit of line 15 */

+#define EXTI_RTSR1_TR16_Pos        (16U)

+#define EXTI_RTSR1_TR16_Msk        (0x1UL << EXTI_RTSR1_TR16_Pos)              /*!< 0x00010000 */

+#define EXTI_RTSR1_TR16            EXTI_RTSR1_TR16_Msk                         /*!< Rising trigger event configuration bit of line 16 */

+#define EXTI_RTSR1_TR17_Pos        (17U)

+#define EXTI_RTSR1_TR17_Msk        (0x1UL << EXTI_RTSR1_TR17_Pos)              /*!< 0x00020000 */

+#define EXTI_RTSR1_TR17            EXTI_RTSR1_TR17_Msk                         /*!< Rising trigger event configuration bit of line 17 */

+#define EXTI_RTSR1_TR18_Pos        (18U)

+#define EXTI_RTSR1_TR18_Msk        (0x1UL << EXTI_RTSR1_TR18_Pos)              /*!< 0x00040000 */

+#define EXTI_RTSR1_TR18            EXTI_RTSR1_TR18_Msk                         /*!< Rising trigger event configuration bit of line 18 */

+#define EXTI_RTSR1_TR19_Pos        (19U)

+#define EXTI_RTSR1_TR19_Msk        (0x1UL << EXTI_RTSR1_TR19_Pos)              /*!< 0x00080000 */

+#define EXTI_RTSR1_TR19            EXTI_RTSR1_TR19_Msk                         /*!< Rising trigger event configuration bit of line 19 */

+#define EXTI_RTSR1_TR20_Pos        (20U)

+#define EXTI_RTSR1_TR20_Msk        (0x1UL << EXTI_RTSR1_TR20_Pos)              /*!< 0x00100000 */

+#define EXTI_RTSR1_TR20            EXTI_RTSR1_TR20_Msk                         /*!< Rising trigger event configuration bit of line 20 */

+#define EXTI_RTSR1_TR21_Pos        (21U)

+#define EXTI_RTSR1_TR21_Msk        (0x1UL << EXTI_RTSR1_TR21_Pos)              /*!< 0x00200000 */

+#define EXTI_RTSR1_TR21            EXTI_RTSR1_TR21_Msk                         /*!< Rising trigger event configuration bit of line 21 */

+

+/******************  Bit definition for EXTI_FTSR1 register  *******************/

+#define EXTI_FTSR1_TR_Pos          (0U)

+#define EXTI_FTSR1_TR_Msk          (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)           /*!< 0x003FFFFF */

+#define EXTI_FTSR1_TR              EXTI_FTSR1_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR1_TR0_Pos         (0U)

+#define EXTI_FTSR1_TR0_Msk         (0x1UL << EXTI_FTSR1_TR0_Pos)               /*!< 0x00000001 */

+#define EXTI_FTSR1_TR0             EXTI_FTSR1_TR0_Msk                          /*!< Falling trigger event configuration bit of line 0 */

+#define EXTI_FTSR1_TR1_Pos         (1U)

+#define EXTI_FTSR1_TR1_Msk         (0x1UL << EXTI_FTSR1_TR1_Pos)               /*!< 0x00000002 */

+#define EXTI_FTSR1_TR1             EXTI_FTSR1_TR1_Msk                          /*!< Falling trigger event configuration bit of line 1 */

+#define EXTI_FTSR1_TR2_Pos         (2U)

+#define EXTI_FTSR1_TR2_Msk         (0x1UL << EXTI_FTSR1_TR2_Pos)               /*!< 0x00000004 */

+#define EXTI_FTSR1_TR2             EXTI_FTSR1_TR2_Msk                          /*!< Falling trigger event configuration bit of line 2 */

+#define EXTI_FTSR1_TR3_Pos         (3U)

+#define EXTI_FTSR1_TR3_Msk         (0x1UL << EXTI_FTSR1_TR3_Pos)               /*!< 0x00000008 */

+#define EXTI_FTSR1_TR3             EXTI_FTSR1_TR3_Msk                          /*!< Falling trigger event configuration bit of line 3 */

+#define EXTI_FTSR1_TR4_Pos         (4U)

+#define EXTI_FTSR1_TR4_Msk         (0x1UL << EXTI_FTSR1_TR4_Pos)               /*!< 0x00000010 */

+#define EXTI_FTSR1_TR4             EXTI_FTSR1_TR4_Msk                          /*!< Falling trigger event configuration bit of line 4 */

+#define EXTI_FTSR1_TR5_Pos         (5U)

+#define EXTI_FTSR1_TR5_Msk         (0x1UL << EXTI_FTSR1_TR5_Pos)               /*!< 0x00000020 */

+#define EXTI_FTSR1_TR5             EXTI_FTSR1_TR5_Msk                          /*!< Falling trigger event configuration bit of line 5 */

+#define EXTI_FTSR1_TR6_Pos         (6U)

+#define EXTI_FTSR1_TR6_Msk         (0x1UL << EXTI_FTSR1_TR6_Pos)               /*!< 0x00000040 */

+#define EXTI_FTSR1_TR6             EXTI_FTSR1_TR6_Msk                          /*!< Falling trigger event configuration bit of line 6 */

+#define EXTI_FTSR1_TR7_Pos         (7U)

+#define EXTI_FTSR1_TR7_Msk         (0x1UL << EXTI_FTSR1_TR7_Pos)               /*!< 0x00000080 */

+#define EXTI_FTSR1_TR7             EXTI_FTSR1_TR7_Msk                          /*!< Falling trigger event configuration bit of line 7 */

+#define EXTI_FTSR1_TR8_Pos         (8U)

+#define EXTI_FTSR1_TR8_Msk         (0x1UL << EXTI_FTSR1_TR8_Pos)               /*!< 0x00000100 */

+#define EXTI_FTSR1_TR8             EXTI_FTSR1_TR8_Msk                          /*!< Falling trigger event configuration bit of line 8 */

+#define EXTI_FTSR1_TR9_Pos         (9U)

+#define EXTI_FTSR1_TR9_Msk         (0x1UL << EXTI_FTSR1_TR9_Pos)               /*!< 0x00000200 */

+#define EXTI_FTSR1_TR9             EXTI_FTSR1_TR9_Msk                          /*!< Falling trigger event configuration bit of line 9 */

+#define EXTI_FTSR1_TR10_Pos        (10U)

+#define EXTI_FTSR1_TR10_Msk        (0x1UL << EXTI_FTSR1_TR10_Pos)              /*!< 0x00000400 */

+#define EXTI_FTSR1_TR10            EXTI_FTSR1_TR10_Msk                         /*!< Falling trigger event configuration bit of line 10 */

+#define EXTI_FTSR1_TR11_Pos        (11U)

+#define EXTI_FTSR1_TR11_Msk        (0x1UL << EXTI_FTSR1_TR11_Pos)              /*!< 0x00000800 */

+#define EXTI_FTSR1_TR11            EXTI_FTSR1_TR11_Msk                         /*!< Falling trigger event configuration bit of line 11 */

+#define EXTI_FTSR1_TR12_Pos        (12U)

+#define EXTI_FTSR1_TR12_Msk        (0x1UL << EXTI_FTSR1_TR12_Pos)              /*!< 0x00001000 */

+#define EXTI_FTSR1_TR12            EXTI_FTSR1_TR12_Msk                         /*!< Falling trigger event configuration bit of line 12 */

+#define EXTI_FTSR1_TR13_Pos        (13U)

+#define EXTI_FTSR1_TR13_Msk        (0x1UL << EXTI_FTSR1_TR13_Pos)              /*!< 0x00002000 */

+#define EXTI_FTSR1_TR13            EXTI_FTSR1_TR13_Msk                         /*!< Falling trigger event configuration bit of line 13 */

+#define EXTI_FTSR1_TR14_Pos        (14U)

+#define EXTI_FTSR1_TR14_Msk        (0x1UL << EXTI_FTSR1_TR14_Pos)              /*!< 0x00004000 */

+#define EXTI_FTSR1_TR14            EXTI_FTSR1_TR14_Msk                         /*!< Falling trigger event configuration bit of line 14 */

+#define EXTI_FTSR1_TR15_Pos        (15U)

+#define EXTI_FTSR1_TR15_Msk        (0x1UL << EXTI_FTSR1_TR15_Pos)              /*!< 0x00008000 */

+#define EXTI_FTSR1_TR15            EXTI_FTSR1_TR15_Msk                         /*!< Falling trigger event configuration bit of line 15 */

+#define EXTI_FTSR1_TR16_Pos        (16U)

+#define EXTI_FTSR1_TR16_Msk        (0x1UL << EXTI_FTSR1_TR16_Pos)              /*!< 0x00010000 */

+#define EXTI_FTSR1_TR16            EXTI_FTSR1_TR16_Msk                         /*!< Falling trigger event configuration bit of line 16 */

+#define EXTI_FTSR1_TR17_Pos        (17U)

+#define EXTI_FTSR1_TR17_Msk        (0x1UL << EXTI_FTSR1_TR17_Pos)              /*!< 0x00020000 */

+#define EXTI_FTSR1_TR17            EXTI_FTSR1_TR17_Msk                         /*!< Falling trigger event configuration bit of line 17 */

+#define EXTI_FTSR1_TR18_Pos        (18U)

+#define EXTI_FTSR1_TR18_Msk        (0x1UL << EXTI_FTSR1_TR18_Pos)              /*!< 0x00040000 */

+#define EXTI_FTSR1_TR18            EXTI_FTSR1_TR18_Msk                         /*!< Falling trigger event configuration bit of line 18 */

+#define EXTI_FTSR1_TR19_Pos        (19U)

+#define EXTI_FTSR1_TR19_Msk        (0x1UL << EXTI_FTSR1_TR19_Pos)              /*!< 0x00080000 */

+#define EXTI_FTSR1_TR19            EXTI_FTSR1_TR19_Msk                         /*!< Falling trigger event configuration bit of line 19 */

+#define EXTI_FTSR1_TR20_Pos        (20U)

+#define EXTI_FTSR1_TR20_Msk        (0x1UL << EXTI_FTSR1_TR20_Pos)              /*!< 0x00100000 */

+#define EXTI_FTSR1_TR20            EXTI_FTSR1_TR20_Msk                         /*!< Falling trigger event configuration bit of line 20 */

+#define EXTI_FTSR1_TR21_Pos        (21U)

+#define EXTI_FTSR1_TR21_Msk        (0x1UL << EXTI_FTSR1_TR21_Pos)              /*!< 0x00200000 */

+#define EXTI_FTSR1_TR21            EXTI_FTSR1_TR21_Msk                         /*!< Falling trigger event configuration bit of line 21 */

+

+/******************  Bit definition for EXTI_SWIER1 register  ******************/

+#define EXTI_SWIER1_SWIER0_Pos     (0U)

+#define EXTI_SWIER1_SWIER0_Msk     (0x1UL << EXTI_SWIER1_SWIER0_Pos)           /*!< 0x00000001 */

+#define EXTI_SWIER1_SWIER0         EXTI_SWIER1_SWIER0_Msk                      /*!< Software Interrupt on line 0 */

+#define EXTI_SWIER1_SWIER1_Pos     (1U)

+#define EXTI_SWIER1_SWIER1_Msk     (0x1UL << EXTI_SWIER1_SWIER1_Pos)           /*!< 0x00000002 */

+#define EXTI_SWIER1_SWIER1         EXTI_SWIER1_SWIER1_Msk                      /*!< Software Interrupt on line 1 */

+#define EXTI_SWIER1_SWIER2_Pos     (2U)

+#define EXTI_SWIER1_SWIER2_Msk     (0x1UL << EXTI_SWIER1_SWIER2_Pos)           /*!< 0x00000004 */

+#define EXTI_SWIER1_SWIER2         EXTI_SWIER1_SWIER2_Msk                      /*!< Software Interrupt on line 2 */

+#define EXTI_SWIER1_SWIER3_Pos     (3U)

+#define EXTI_SWIER1_SWIER3_Msk     (0x1UL << EXTI_SWIER1_SWIER3_Pos)           /*!< 0x00000008 */

+#define EXTI_SWIER1_SWIER3         EXTI_SWIER1_SWIER3_Msk                      /*!< Software Interrupt on line 3 */

+#define EXTI_SWIER1_SWIER4_Pos     (4U)

+#define EXTI_SWIER1_SWIER4_Msk     (0x1UL << EXTI_SWIER1_SWIER4_Pos)           /*!< 0x00000010 */

+#define EXTI_SWIER1_SWIER4         EXTI_SWIER1_SWIER4_Msk                      /*!< Software Interrupt on line 4 */

+#define EXTI_SWIER1_SWIER5_Pos     (5U)

+#define EXTI_SWIER1_SWIER5_Msk     (0x1UL << EXTI_SWIER1_SWIER5_Pos)           /*!< 0x00000020 */

+#define EXTI_SWIER1_SWIER5         EXTI_SWIER1_SWIER5_Msk                      /*!< Software Interrupt on line 5 */

+#define EXTI_SWIER1_SWIER6_Pos     (6U)

+#define EXTI_SWIER1_SWIER6_Msk     (0x1UL << EXTI_SWIER1_SWIER6_Pos)           /*!< 0x00000040 */

+#define EXTI_SWIER1_SWIER6         EXTI_SWIER1_SWIER6_Msk                      /*!< Software Interrupt on line 6 */

+#define EXTI_SWIER1_SWIER7_Pos     (7U)

+#define EXTI_SWIER1_SWIER7_Msk     (0x1UL << EXTI_SWIER1_SWIER7_Pos)           /*!< 0x00000080 */

+#define EXTI_SWIER1_SWIER7         EXTI_SWIER1_SWIER7_Msk                      /*!< Software Interrupt on line 7 */

+#define EXTI_SWIER1_SWIER8_Pos     (8U)

+#define EXTI_SWIER1_SWIER8_Msk     (0x1UL << EXTI_SWIER1_SWIER8_Pos)           /*!< 0x00000100 */

+#define EXTI_SWIER1_SWIER8         EXTI_SWIER1_SWIER8_Msk                      /*!< Software Interrupt on line 8 */

+#define EXTI_SWIER1_SWIER9_Pos     (9U)

+#define EXTI_SWIER1_SWIER9_Msk     (0x1UL << EXTI_SWIER1_SWIER9_Pos)           /*!< 0x00000200 */

+#define EXTI_SWIER1_SWIER9         EXTI_SWIER1_SWIER9_Msk                      /*!< Software Interrupt on line 9 */

+#define EXTI_SWIER1_SWIER10_Pos    (10U)

+#define EXTI_SWIER1_SWIER10_Msk    (0x1UL << EXTI_SWIER1_SWIER10_Pos)          /*!< 0x00000400 */

+#define EXTI_SWIER1_SWIER10        EXTI_SWIER1_SWIER10_Msk                     /*!< Software Interrupt on line 10 */

+#define EXTI_SWIER1_SWIER11_Pos    (11U)

+#define EXTI_SWIER1_SWIER11_Msk    (0x1UL << EXTI_SWIER1_SWIER11_Pos)          /*!< 0x00000800 */

+#define EXTI_SWIER1_SWIER11        EXTI_SWIER1_SWIER11_Msk                     /*!< Software Interrupt on line 11 */

+#define EXTI_SWIER1_SWIER12_Pos    (12U)

+#define EXTI_SWIER1_SWIER12_Msk    (0x1UL << EXTI_SWIER1_SWIER12_Pos)          /*!< 0x00001000 */

+#define EXTI_SWIER1_SWIER12        EXTI_SWIER1_SWIER12_Msk                     /*!< Software Interrupt on line 12 */

+#define EXTI_SWIER1_SWIER13_Pos    (13U)

+#define EXTI_SWIER1_SWIER13_Msk    (0x1UL << EXTI_SWIER1_SWIER13_Pos)          /*!< 0x00002000 */

+#define EXTI_SWIER1_SWIER13        EXTI_SWIER1_SWIER13_Msk                     /*!< Software Interrupt on line 13 */

+#define EXTI_SWIER1_SWIER14_Pos    (14U)

+#define EXTI_SWIER1_SWIER14_Msk    (0x1UL << EXTI_SWIER1_SWIER14_Pos)          /*!< 0x00004000 */

+#define EXTI_SWIER1_SWIER14        EXTI_SWIER1_SWIER14_Msk                     /*!< Software Interrupt on line 14 */

+#define EXTI_SWIER1_SWIER15_Pos    (15U)

+#define EXTI_SWIER1_SWIER15_Msk    (0x1UL << EXTI_SWIER1_SWIER15_Pos)          /*!< 0x00008000 */

+#define EXTI_SWIER1_SWIER15        EXTI_SWIER1_SWIER15_Msk                     /*!< Software Interrupt on line 15 */

+#define EXTI_SWIER1_SWIER16_Pos    (16U)

+#define EXTI_SWIER1_SWIER16_Msk    (0x1UL << EXTI_SWIER1_SWIER16_Pos)          /*!< 0x00010000 */

+#define EXTI_SWIER1_SWIER16        EXTI_SWIER1_SWIER16_Msk                     /*!< Software Interrupt on line 16 */

+#define EXTI_SWIER1_SWIER17_Pos    (17U)

+#define EXTI_SWIER1_SWIER17_Msk    (0x1UL << EXTI_SWIER1_SWIER17_Pos)          /*!< 0x00020000 */

+#define EXTI_SWIER1_SWIER17        EXTI_SWIER1_SWIER17_Msk                     /*!< Software Interrupt on line 17 */

+#define EXTI_SWIER1_SWIER18_Pos    (18U)

+#define EXTI_SWIER1_SWIER18_Msk    (0x1UL << EXTI_SWIER1_SWIER18_Pos)          /*!< 0x00040000 */

+#define EXTI_SWIER1_SWIER18        EXTI_SWIER1_SWIER18_Msk                     /*!< Software Interrupt on line 18 */

+#define EXTI_SWIER1_SWIER19_Pos    (19U)

+#define EXTI_SWIER1_SWIER19_Msk    (0x1UL << EXTI_SWIER1_SWIER19_Pos)          /*!< 0x00080000 */

+#define EXTI_SWIER1_SWIER19        EXTI_SWIER1_SWIER19_Msk                     /*!< Software Interrupt on line 19 */

+#define EXTI_SWIER1_SWIER20_Pos    (20U)

+#define EXTI_SWIER1_SWIER20_Msk    (0x1UL << EXTI_SWIER1_SWIER20_Pos)          /*!< 0x00100000 */

+#define EXTI_SWIER1_SWIER20        EXTI_SWIER1_SWIER20_Msk                     /*!< Software Interrupt on line 20 */

+#define EXTI_SWIER1_SWIER21_Pos    (21U)

+#define EXTI_SWIER1_SWIER21_Msk    (0x1UL << EXTI_SWIER1_SWIER21_Pos)          /*!< 0x00200000 */

+#define EXTI_SWIER1_SWIER21        EXTI_SWIER1_SWIER21_Msk                     /*!< Software Interrupt on line 21 */

+

+/******************  Bit definition for EXTI_D3PMR1 register  ******************/

+#define EXTI_D3PMR1_MR0_Pos        (0U)

+#define EXTI_D3PMR1_MR0_Msk        (0x1UL << EXTI_D3PMR1_MR0_Pos)              /*!< 0x00000001 */

+#define EXTI_D3PMR1_MR0            EXTI_D3PMR1_MR0_Msk                         /*!< Pending Mask Event for line 0  */

+#define EXTI_D3PMR1_MR1_Pos        (1U)

+#define EXTI_D3PMR1_MR1_Msk        (0x1UL << EXTI_D3PMR1_MR1_Pos)              /*!< 0x00000002 */

+#define EXTI_D3PMR1_MR1            EXTI_D3PMR1_MR1_Msk                         /*!< Pending Mask Event for line 1  */

+#define EXTI_D3PMR1_MR2_Pos        (2U)

+#define EXTI_D3PMR1_MR2_Msk        (0x1UL << EXTI_D3PMR1_MR2_Pos)              /*!< 0x00000004 */

+#define EXTI_D3PMR1_MR2            EXTI_D3PMR1_MR2_Msk                         /*!< Pending Mask Event for line 2  */

+#define EXTI_D3PMR1_MR3_Pos        (3U)

+#define EXTI_D3PMR1_MR3_Msk        (0x1UL << EXTI_D3PMR1_MR3_Pos)              /*!< 0x00000008 */

+#define EXTI_D3PMR1_MR3            EXTI_D3PMR1_MR3_Msk                         /*!< Pending Mask Event for line 3  */

+#define EXTI_D3PMR1_MR4_Pos        (4U)

+#define EXTI_D3PMR1_MR4_Msk        (0x1UL << EXTI_D3PMR1_MR4_Pos)              /*!< 0x00000010 */

+#define EXTI_D3PMR1_MR4            EXTI_D3PMR1_MR4_Msk                         /*!< Pending Mask Event for line 4  */

+#define EXTI_D3PMR1_MR5_Pos        (5U)

+#define EXTI_D3PMR1_MR5_Msk        (0x1UL << EXTI_D3PMR1_MR5_Pos)              /*!< 0x00000020 */

+#define EXTI_D3PMR1_MR5            EXTI_D3PMR1_MR5_Msk                         /*!< Pending Mask Event for line 5  */

+#define EXTI_D3PMR1_MR6_Pos        (6U)

+#define EXTI_D3PMR1_MR6_Msk        (0x1UL << EXTI_D3PMR1_MR6_Pos)              /*!< 0x00000040 */

+#define EXTI_D3PMR1_MR6            EXTI_D3PMR1_MR6_Msk                         /*!< Pending Mask Event for line 6  */

+#define EXTI_D3PMR1_MR7_Pos        (7U)

+#define EXTI_D3PMR1_MR7_Msk        (0x1UL << EXTI_D3PMR1_MR7_Pos)              /*!< 0x00000080 */

+#define EXTI_D3PMR1_MR7            EXTI_D3PMR1_MR7_Msk                         /*!< Pending Mask Event for line 7  */

+#define EXTI_D3PMR1_MR8_Pos        (8U)

+#define EXTI_D3PMR1_MR8_Msk        (0x1UL << EXTI_D3PMR1_MR8_Pos)              /*!< 0x00000100 */

+#define EXTI_D3PMR1_MR8            EXTI_D3PMR1_MR8_Msk                         /*!< Pending Mask Event for line 8  */

+#define EXTI_D3PMR1_MR9_Pos        (9U)

+#define EXTI_D3PMR1_MR9_Msk        (0x1UL << EXTI_D3PMR1_MR9_Pos)              /*!< 0x00000200 */

+#define EXTI_D3PMR1_MR9            EXTI_D3PMR1_MR9_Msk                         /*!< Pending Mask Event for line 9  */

+#define EXTI_D3PMR1_MR10_Pos       (10U)

+#define EXTI_D3PMR1_MR10_Msk       (0x1UL << EXTI_D3PMR1_MR10_Pos)             /*!< 0x00000400 */

+#define EXTI_D3PMR1_MR10           EXTI_D3PMR1_MR10_Msk                        /*!< Pending Mask Event for line 10 */

+#define EXTI_D3PMR1_MR11_Pos       (11U)

+#define EXTI_D3PMR1_MR11_Msk       (0x1UL << EXTI_D3PMR1_MR11_Pos)             /*!< 0x00000800 */

+#define EXTI_D3PMR1_MR11           EXTI_D3PMR1_MR11_Msk                        /*!< Pending Mask Event for line 11 */

+#define EXTI_D3PMR1_MR12_Pos       (12U)

+#define EXTI_D3PMR1_MR12_Msk       (0x1UL << EXTI_D3PMR1_MR12_Pos)             /*!< 0x00001000 */

+#define EXTI_D3PMR1_MR12           EXTI_D3PMR1_MR12_Msk                        /*!< Pending Mask Event for line 12 */

+#define EXTI_D3PMR1_MR13_Pos       (13U)

+#define EXTI_D3PMR1_MR13_Msk       (0x1UL << EXTI_D3PMR1_MR13_Pos)             /*!< 0x00002000 */

+#define EXTI_D3PMR1_MR13           EXTI_D3PMR1_MR13_Msk                        /*!< Pending Mask Event for line 13 */

+#define EXTI_D3PMR1_MR14_Pos       (14U)

+#define EXTI_D3PMR1_MR14_Msk       (0x1UL << EXTI_D3PMR1_MR14_Pos)             /*!< 0x00004000 */

+#define EXTI_D3PMR1_MR14           EXTI_D3PMR1_MR14_Msk                        /*!< Pending Mask Event for line 14 */

+#define EXTI_D3PMR1_MR15_Pos       (15U)

+#define EXTI_D3PMR1_MR15_Msk       (0x1UL << EXTI_D3PMR1_MR15_Pos)             /*!< 0x00008000 */

+#define EXTI_D3PMR1_MR15           EXTI_D3PMR1_MR15_Msk                        /*!< Pending Mask Event for line 15 */

+#define EXTI_D3PMR1_MR19_Pos       (19U)

+#define EXTI_D3PMR1_MR19_Msk       (0x1UL << EXTI_D3PMR1_MR19_Pos)             /*!< 0x00080000 */

+#define EXTI_D3PMR1_MR19           EXTI_D3PMR1_MR19_Msk                        /*!< Pending Mask Event for line 19 */

+#define EXTI_D3PMR1_MR20_Pos       (20U)

+#define EXTI_D3PMR1_MR20_Msk       (0x1UL << EXTI_D3PMR1_MR20_Pos)             /*!< 0x00100000 */

+#define EXTI_D3PMR1_MR20           EXTI_D3PMR1_MR20_Msk                        /*!< Pending Mask Event for line 20 */

+#define EXTI_D3PMR1_MR21_Pos       (21U)

+#define EXTI_D3PMR1_MR21_Msk       (0x1UL << EXTI_D3PMR1_MR21_Pos)             /*!< 0x00200000 */

+#define EXTI_D3PMR1_MR21           EXTI_D3PMR1_MR21_Msk                        /*!< Pending Mask Event for line 21 */

+#define EXTI_D3PMR1_MR25_Pos       (24U)

+#define EXTI_D3PMR1_MR25_Msk       (0x1UL << EXTI_D3PMR1_MR25_Pos)             /*!< 0x01000000 */

+#define EXTI_D3PMR1_MR25           EXTI_D3PMR1_MR25_Msk                        /*!< Pending Mask Event for line 25 */

+

+/*******************  Bit definition for EXTI_D3PCR1L register  ****************/

+#define EXTI_D3PCR1L_PCS0_Pos       (0U)

+#define EXTI_D3PCR1L_PCS0_Msk       (0x3UL << EXTI_D3PCR1L_PCS0_Pos)           /*!< 0x00000003 */

+#define EXTI_D3PCR1L_PCS0           EXTI_D3PCR1L_PCS0_Msk                      /*!< D3 Pending request clear input signal selection on line 0 */

+#define EXTI_D3PCR1L_PCS1_Pos       (2U)

+#define EXTI_D3PCR1L_PCS1_Msk       (0x3UL << EXTI_D3PCR1L_PCS1_Pos)           /*!< 0x000000C0 */

+#define EXTI_D3PCR1L_PCS1           EXTI_D3PCR1L_PCS1_Msk                      /*!< D3 Pending request clear input signal selection on line 1 */

+#define EXTI_D3PCR1L_PCS2_Pos       (4U)

+#define EXTI_D3PCR1L_PCS2_Msk       (0x3UL << EXTI_D3PCR1L_PCS2_Pos)           /*!< 0x00000030 */

+#define EXTI_D3PCR1L_PCS2           EXTI_D3PCR1L_PCS2_Msk                      /*!< D3 Pending request clear input signal selection on line 2 */

+#define EXTI_D3PCR1L_PCS3_Pos       (6U)

+#define EXTI_D3PCR1L_PCS3_Msk       (0x3UL << EXTI_D3PCR1L_PCS3_Pos)           /*!< 0x000000C0 */

+#define EXTI_D3PCR1L_PCS3           EXTI_D3PCR1L_PCS3_Msk                      /*!< D3 Pending request clear input signal selection on line 3 */

+#define EXTI_D3PCR1L_PCS4_Pos       (8U)

+#define EXTI_D3PCR1L_PCS4_Msk       (0x3UL << EXTI_D3PCR1L_PCS4_Pos)           /*!< 0x00000300 */

+#define EXTI_D3PCR1L_PCS4           EXTI_D3PCR1L_PCS4_Msk                      /*!< D3 Pending request clear input signal selection on line 4 */

+#define EXTI_D3PCR1L_PCS5_Pos       (10U)

+#define EXTI_D3PCR1L_PCS5_Msk       (0x3UL << EXTI_D3PCR1L_PCS5_Pos)           /*!< 0x00000C00 */

+#define EXTI_D3PCR1L_PCS5           EXTI_D3PCR1L_PCS5_Msk                      /*!< D3 Pending request clear input signal selection on line 5 */

+#define EXTI_D3PCR1L_PCS6_Pos       (12U)

+#define EXTI_D3PCR1L_PCS6_Msk       (0x3UL << EXTI_D3PCR1L_PCS6_Pos)           /*!< 0x00003000 */

+#define EXTI_D3PCR1L_PCS6           EXTI_D3PCR1L_PCS6_Msk                      /*!< D3 Pending request clear input signal selection on line 6 */

+#define EXTI_D3PCR1L_PCS7_Pos       (14U)

+#define EXTI_D3PCR1L_PCS7_Msk       (0x3UL << EXTI_D3PCR1L_PCS7_Pos)           /*!< 0x0000C000 */

+#define EXTI_D3PCR1L_PCS7           EXTI_D3PCR1L_PCS7_Msk                      /*!< D3 Pending request clear input signal selection on line 7 */

+#define EXTI_D3PCR1L_PCS8_Pos       (16U)

+#define EXTI_D3PCR1L_PCS8_Msk       (0x3UL << EXTI_D3PCR1L_PCS8_Pos)           /*!< 0x00030000 */

+#define EXTI_D3PCR1L_PCS8           EXTI_D3PCR1L_PCS8_Msk                      /*!< D3 Pending request clear input signal selection on line 8 */

+#define EXTI_D3PCR1L_PCS9_Pos       (18U)

+#define EXTI_D3PCR1L_PCS9_Msk       (0x3UL << EXTI_D3PCR1L_PCS9_Pos)           /*!< 0x000C0000 */

+#define EXTI_D3PCR1L_PCS9           EXTI_D3PCR1L_PCS9_Msk                      /*!< D3 Pending request clear input signal selection on line 9 */

+#define EXTI_D3PCR1L_PCS10_Pos      (20U)

+#define EXTI_D3PCR1L_PCS10_Msk      (0x3UL << EXTI_D3PCR1L_PCS10_Pos)          /*!< 0x00300000 */

+#define EXTI_D3PCR1L_PCS10          EXTI_D3PCR1L_PCS10_Msk                     /*!< D3 Pending request clear input signal selection on line 10*/

+#define EXTI_D3PCR1L_PCS11_Pos      (22U)

+#define EXTI_D3PCR1L_PCS11_Msk      (0x3UL << EXTI_D3PCR1L_PCS11_Pos)          /*!< 0x00C00000 */

+#define EXTI_D3PCR1L_PCS11          EXTI_D3PCR1L_PCS11_Msk                     /*!< D3 Pending request clear input signal selection on line 11*/

+#define EXTI_D3PCR1L_PCS12_Pos      (24U)

+#define EXTI_D3PCR1L_PCS12_Msk      (0x3UL << EXTI_D3PCR1L_PCS12_Pos)          /*!< 0x03000000 */

+#define EXTI_D3PCR1L_PCS12          EXTI_D3PCR1L_PCS12_Msk                     /*!< D3 Pending request clear input signal selection on line 12*/

+#define EXTI_D3PCR1L_PCS13_Pos      (26U)

+#define EXTI_D3PCR1L_PCS13_Msk      (0x3UL << EXTI_D3PCR1L_PCS13_Pos)          /*!< 0x0C000000 */

+#define EXTI_D3PCR1L_PCS13          EXTI_D3PCR1L_PCS13_Msk                     /*!< D3 Pending request clear input signal selection on line 13*/

+#define EXTI_D3PCR1L_PCS14_Pos      (28U)

+#define EXTI_D3PCR1L_PCS14_Msk      (0x3UL << EXTI_D3PCR1L_PCS14_Pos)          /*!< 0x30000000 */

+#define EXTI_D3PCR1L_PCS14          EXTI_D3PCR1L_PCS14_Msk                     /*!< D3 Pending request clear input signal selection on line 14*/

+#define EXTI_D3PCR1L_PCS15_Pos      (30U)

+#define EXTI_D3PCR1L_PCS15_Msk      (0x3UL << EXTI_D3PCR1L_PCS15_Pos)          /*!< 0xC0000000 */

+#define EXTI_D3PCR1L_PCS15          EXTI_D3PCR1L_PCS15_Msk                     /*!< D3 Pending request clear input signal selection on line 15*/

+

+/*******************  Bit definition for EXTI_D3PCR1H register  ****************/

+#define EXTI_D3PCR1H_PCS19_Pos       (6U)

+#define EXTI_D3PCR1H_PCS19_Msk       (0x3UL << EXTI_D3PCR1H_PCS19_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR1H_PCS19           EXTI_D3PCR1H_PCS19_Msk                    /*!< D3 Pending request clear input signal selection on line 19 */

+#define EXTI_D3PCR1H_PCS20_Pos       (8U)

+#define EXTI_D3PCR1H_PCS20_Msk       (0x3UL << EXTI_D3PCR1H_PCS20_Pos)         /*!< 0x00000300 */

+#define EXTI_D3PCR1H_PCS20           EXTI_D3PCR1H_PCS20_Msk                    /*!< D3 Pending request clear input signal selection on line 20 */

+#define EXTI_D3PCR1H_PCS21_Pos       (10U)

+#define EXTI_D3PCR1H_PCS21_Msk       (0x3UL << EXTI_D3PCR1H_PCS21_Pos)         /*!< 0x00000C00 */

+#define EXTI_D3PCR1H_PCS21           EXTI_D3PCR1H_PCS21_Msk                    /*!< D3 Pending request clear input signal selection on line 21 */

+#define EXTI_D3PCR1H_PCS25_Pos       (18U)

+#define EXTI_D3PCR1H_PCS25_Msk       (0x3UL << EXTI_D3PCR1H_PCS25_Pos)         /*!< 0x000C0000 */

+#define EXTI_D3PCR1H_PCS25           EXTI_D3PCR1H_PCS25_Msk                    /*!< D3 Pending request clear input signal selection on line 25 */

+

+/******************  Bit definition for EXTI_RTSR2 register  *******************/

+#define EXTI_RTSR2_TR_Pos          (17U)

+#define EXTI_RTSR2_TR_Msk          (0x5UL << EXTI_RTSR2_TR_Pos)                /*!< 0x000A0000 */

+#define EXTI_RTSR2_TR              EXTI_RTSR2_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR2_TR49_Pos        (17U)

+#define EXTI_RTSR2_TR49_Msk        (0x1UL << EXTI_RTSR2_TR49_Pos)              /*!< 0x00020000 */

+#define EXTI_RTSR2_TR49            EXTI_RTSR2_TR49_Msk                         /*!< Rising trigger event configuration bit of line 49 */

+#define EXTI_RTSR2_TR51_Pos        (19U)

+#define EXTI_RTSR2_TR51_Msk        (0x1UL << EXTI_RTSR2_TR51_Pos)              /*!< 0x00080000 */

+#define EXTI_RTSR2_TR51            EXTI_RTSR2_TR51_Msk                         /*!< Rising trigger event configuration bit of line 51 */

+

+/******************  Bit definition for EXTI_FTSR2 register  *******************/

+#define EXTI_FTSR2_TR_Pos          (17U)

+#define EXTI_FTSR2_TR_Msk          (0x5UL << EXTI_FTSR2_TR_Pos)                /*!< 0x000A0000 */

+#define EXTI_FTSR2_TR              EXTI_FTSR2_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR2_TR49_Pos        (17U)

+#define EXTI_FTSR2_TR49_Msk        (0x1UL << EXTI_FTSR2_TR49_Pos)              /*!< 0x00020000 */

+#define EXTI_FTSR2_TR49            EXTI_FTSR2_TR49_Msk                         /*!< Falling trigger event configuration bit of line 49 */

+#define EXTI_FTSR2_TR51_Pos        (19U)

+#define EXTI_FTSR2_TR51_Msk        (0x1UL << EXTI_FTSR2_TR51_Pos)              /*!< 0x00080000 */

+#define EXTI_FTSR2_TR51            EXTI_FTSR2_TR51_Msk                         /*!< Falling trigger event configuration bit of line 51 */

+

+/******************  Bit definition for EXTI_SWIER2 register  ******************/

+#define EXTI_SWIER2_SWIER49_Pos    (17U)

+#define EXTI_SWIER2_SWIER49_Msk    (0x1UL << EXTI_SWIER2_SWIER49_Pos)          /*!< 0x00020000 */

+#define EXTI_SWIER2_SWIER49        EXTI_SWIER2_SWIER49_Msk                     /*!< Software Interrupt on line 49 */

+#define EXTI_SWIER2_SWIER51_Pos    (19U)

+#define EXTI_SWIER2_SWIER51_Msk    (0x1UL << EXTI_SWIER2_SWIER51_Pos)          /*!< 0x00080000 */

+#define EXTI_SWIER2_SWIER51        EXTI_SWIER2_SWIER51_Msk                     /*!< Software Interrupt on line 51 */

+

+/******************  Bit definition for EXTI_D3PMR2 register  ******************/

+#define EXTI_D3PMR2_MR34_Pos       (2U)

+#define EXTI_D3PMR2_MR34_Msk       (0x1UL << EXTI_D3PMR2_MR34_Pos)             /*!< 0x00000004 */

+#define EXTI_D3PMR2_MR34           EXTI_D3PMR2_MR34_Msk                        /*!< Pending Mask Event for line 34  */

+#define EXTI_D3PMR2_MR35_Pos       (3U)

+#define EXTI_D3PMR2_MR35_Msk       (0x1UL << EXTI_D3PMR2_MR35_Pos)             /*!< 0x00000008 */

+#define EXTI_D3PMR2_MR35           EXTI_D3PMR2_MR35_Msk                        /*!< Pending Mask Event for line 35  */

+#define EXTI_D3PMR2_MR41_Pos       (9U)

+#define EXTI_D3PMR2_MR41_Msk       (0x1UL << EXTI_D3PMR2_MR41_Pos)             /*!< 0x00000200 */

+#define EXTI_D3PMR2_MR41           EXTI_D3PMR2_MR41_Msk                        /*!< Pending Mask Event for line 41  */

+#define EXTI_D3PMR2_MR48_Pos       (16U)

+#define EXTI_D3PMR2_MR48_Msk       (0x1UL << EXTI_D3PMR2_MR48_Pos)             /*!< 0x00010000 */

+#define EXTI_D3PMR2_MR48           EXTI_D3PMR2_MR48_Msk                        /*!< Pending Mask Event for line 48  */

+#define EXTI_D3PMR2_MR49_Pos       (17U)

+#define EXTI_D3PMR2_MR49_Msk       (0x1UL << EXTI_D3PMR2_MR49_Pos)             /*!< 0x00020000 */

+#define EXTI_D3PMR2_MR49           EXTI_D3PMR2_MR49_Msk                        /*!< Pending Mask Event for line 49  */

+#define EXTI_D3PMR2_MR50_Pos       (18U)

+#define EXTI_D3PMR2_MR50_Msk       (0x1UL << EXTI_D3PMR2_MR50_Pos)             /*!< 0x00040000 */

+#define EXTI_D3PMR2_MR50           EXTI_D3PMR2_MR50_Msk                        /*!< Pending Mask Event for line 50  */

+#define EXTI_D3PMR2_MR51_Pos       (19U)

+#define EXTI_D3PMR2_MR51_Msk       (0x1UL << EXTI_D3PMR2_MR51_Pos)             /*!< 0x00080000 */

+#define EXTI_D3PMR2_MR51           EXTI_D3PMR2_MR51_Msk                        /*!< Pending Mask Event for line 51  */

+/*******************  Bit definition for EXTI_D3PCR2L register  ****************/

+#define EXTI_D3PCR2L_PCS34_Pos       (4U)

+#define EXTI_D3PCR2L_PCS34_Msk       (0x3UL << EXTI_D3PCR2L_PCS34_Pos)         /*!< 0x00000030 */

+#define EXTI_D3PCR2L_PCS34           EXTI_D3PCR2L_PCS34_Msk                    /*!< D3 Pending request clear input signal selection on line 34 */

+#define EXTI_D3PCR2L_PCS35_Pos       (6U)

+#define EXTI_D3PCR2L_PCS35_Msk       (0x3UL << EXTI_D3PCR2L_PCS35_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR2L_PCS35           EXTI_D3PCR2L_PCS35_Msk                    /*!< D3 Pending request clear input signal selection on line 35 */

+#define EXTI_D3PCR2L_PCS41_Pos       (18U)

+#define EXTI_D3PCR2L_PCS41_Msk       (0x3UL << EXTI_D3PCR2L_PCS41_Pos)         /*!< 0x000C0000 */

+#define EXTI_D3PCR2L_PCS41           EXTI_D3PCR2L_PCS41_Msk                    /*!< D3 Pending request clear input signal selection on line 41 */

+

+

+/*******************  Bit definition for EXTI_D3PCR2H register  ****************/

+#define EXTI_D3PCR2H_PCS48_Pos       (0U)

+#define EXTI_D3PCR2H_PCS48_Msk       (0x3UL << EXTI_D3PCR2H_PCS48_Pos)         /*!< 0x00000003 */

+#define EXTI_D3PCR2H_PCS48           EXTI_D3PCR2H_PCS48_Msk                    /*!< D3 Pending request clear input signal selection on line 48 */

+#define EXTI_D3PCR2H_PCS49_Pos       (2U)

+#define EXTI_D3PCR2H_PCS49_Msk       (0x3UL << EXTI_D3PCR2H_PCS49_Pos)         /*!< 0x0000000C */

+#define EXTI_D3PCR2H_PCS49           EXTI_D3PCR2H_PCS49_Msk                    /*!< D3 Pending request clear input signal selection on line 49 */

+#define EXTI_D3PCR2H_PCS50_Pos       (4U)

+#define EXTI_D3PCR2H_PCS50_Msk       (0x3UL << EXTI_D3PCR2H_PCS50_Pos)         /*!< 0x00000030 */

+#define EXTI_D3PCR2H_PCS50           EXTI_D3PCR2H_PCS50_Msk                    /*!< D3 Pending request clear input signal selection on line 50 */

+#define EXTI_D3PCR2H_PCS51_Pos       (6U)

+#define EXTI_D3PCR2H_PCS51_Msk       (0x3UL << EXTI_D3PCR2H_PCS51_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR2H_PCS51           EXTI_D3PCR2H_PCS51_Msk                    /*!< D3 Pending request clear input signal selection on line 51 */

+/******************  Bit definition for EXTI_RTSR3 register  *******************/

+#define EXTI_RTSR3_TR_Pos          (18U)

+#define EXTI_RTSR3_TR_Msk          (0x9UL << EXTI_RTSR3_TR_Pos)                /*!< 0x00240000 */

+#define EXTI_RTSR3_TR              EXTI_RTSR3_TR_Msk                           /*!< Rising trigger event configuration bit            */

+#define EXTI_RTSR3_TR82_Pos        (18U)

+#define EXTI_RTSR3_TR82_Msk        (0x1UL << EXTI_RTSR3_TR82_Pos)              /*!< 0x00040000 */

+#define EXTI_RTSR3_TR82            EXTI_RTSR3_TR82_Msk                         /*!< Rising trigger event configuration bit of line 82 */

+#define EXTI_RTSR3_TR85_Pos        (21U)

+#define EXTI_RTSR3_TR85_Msk        (0x1UL << EXTI_RTSR3_TR85_Pos)              /*!< 0x00200000 */

+#define EXTI_RTSR3_TR85            EXTI_RTSR3_TR85_Msk                         /*!< Rising trigger event configuration bit of line 85 */

+

+/******************  Bit definition for EXTI_FTSR3 register  *******************/

+#define EXTI_FTSR3_TR_Pos          (18U)

+#define EXTI_FTSR3_TR_Msk          (0x9UL << EXTI_FTSR3_TR_Pos)                /*!< 0x00240000 */

+#define EXTI_FTSR3_TR              EXTI_FTSR3_TR_Msk                           /*!< Falling trigger event configuration bit            */

+#define EXTI_FTSR3_TR82_Pos        (18U)

+#define EXTI_FTSR3_TR82_Msk        (0x1UL << EXTI_FTSR3_TR82_Pos)              /*!< 0x00040000 */

+#define EXTI_FTSR3_TR82            EXTI_FTSR3_TR82_Msk                         /*!< Falling trigger event configuration bit of line 82 */

+#define EXTI_FTSR3_TR85_Pos        (21U)

+#define EXTI_FTSR3_TR85_Msk        (0x1UL << EXTI_FTSR3_TR85_Pos)              /*!< 0x00200000 */

+#define EXTI_FTSR3_TR85            EXTI_FTSR3_TR85_Msk                         /*!< Falling trigger event configuration bit of line 85 */

+

+/******************  Bit definition for EXTI_SWIER3 register  ******************/

+#define EXTI_SWIER3_SWI_Pos        (18U)

+#define EXTI_SWIER3_SWI_Msk        (0x9UL << EXTI_SWIER3_SWI_Pos)              /*!< 0x00240000 */

+#define EXTI_SWIER3_SWI            EXTI_SWIER3_SWI_Msk                         /*!< Software Interrupt event bit */

+#define EXTI_SWIER3_SWIER82_Pos    (18U)

+#define EXTI_SWIER3_SWIER82_Msk    (0x1UL << EXTI_SWIER3_SWIER82_Pos)          /*!< 0x00040000 */

+#define EXTI_SWIER3_SWIER82        EXTI_SWIER3_SWIER82_Msk                     /*!< Software Interrupt on line 82 */

+#define EXTI_SWIER3_SWIER85_Pos    (21U)

+#define EXTI_SWIER3_SWIER85_Msk    (0x1UL << EXTI_SWIER3_SWIER85_Pos)          /*!< 0x00200000 */

+#define EXTI_SWIER3_SWIER85        EXTI_SWIER3_SWIER85_Msk                     /*!< Software Interrupt on line 85 */

+

+/******************  Bit definition for EXTI_D3PMR3 register  ******************/

+#define EXTI_D3PMR3_MR88_Pos       (24U)

+#define EXTI_D3PMR3_MR88_Msk       (0x1UL << EXTI_D3PMR3_MR88_Pos)             /*!< 0x01000000 */

+#define EXTI_D3PMR3_MR88           EXTI_D3PMR3_MR88_Msk                        /*!< Pending Mask Event for line 88  */

+

+/*******************  Bit definition for EXTI_D3PCR3H register  ****************/

+#define EXTI_D3PCR3H_PCS88_Pos       (16U)

+#define EXTI_D3PCR3H_PCS88_Msk       (0x3UL << EXTI_D3PCR3H_PCS88_Pos)         /*!< 0x00030000 */

+#define EXTI_D3PCR3H_PCS88           EXTI_D3PCR3H_PCS88_Msk                    /*!< D3 Pending request clear input signal selection on line 88 */

+

+/*******************  Bit definition for EXTI_IMR1 register  *******************/

+#define EXTI_IMR1_IM_Pos           (0U)

+#define EXTI_IMR1_IM_Msk           (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)          /*!< 0xFFFFFFFF */

+#define EXTI_IMR1_IM               EXTI_IMR1_IM_Msk                            /*!< Interrupt Mask */

+#define EXTI_IMR1_IM0_Pos          (0U)

+#define EXTI_IMR1_IM0_Msk          (0x1UL << EXTI_IMR1_IM0_Pos)                /*!< 0x00000001 */

+#define EXTI_IMR1_IM0              EXTI_IMR1_IM0_Msk                           /*!< Interrupt Mask on line 0 */

+#define EXTI_IMR1_IM1_Pos          (1U)

+#define EXTI_IMR1_IM1_Msk          (0x1UL << EXTI_IMR1_IM1_Pos)                /*!< 0x00000002 */

+#define EXTI_IMR1_IM1              EXTI_IMR1_IM1_Msk                           /*!< Interrupt Mask on line 1 */

+#define EXTI_IMR1_IM2_Pos          (2U)

+#define EXTI_IMR1_IM2_Msk          (0x1UL << EXTI_IMR1_IM2_Pos)                /*!< 0x00000004 */

+#define EXTI_IMR1_IM2              EXTI_IMR1_IM2_Msk                           /*!< Interrupt Mask on line 2 */

+#define EXTI_IMR1_IM3_Pos          (3U)

+#define EXTI_IMR1_IM3_Msk          (0x1UL << EXTI_IMR1_IM3_Pos)                /*!< 0x00000008 */

+#define EXTI_IMR1_IM3              EXTI_IMR1_IM3_Msk                           /*!< Interrupt Mask on line 3 */

+#define EXTI_IMR1_IM4_Pos          (4U)

+#define EXTI_IMR1_IM4_Msk          (0x1UL << EXTI_IMR1_IM4_Pos)                /*!< 0x00000010 */

+#define EXTI_IMR1_IM4              EXTI_IMR1_IM4_Msk                           /*!< Interrupt Mask on line 4 */

+#define EXTI_IMR1_IM5_Pos          (5U)

+#define EXTI_IMR1_IM5_Msk          (0x1UL << EXTI_IMR1_IM5_Pos)                /*!< 0x00000020 */

+#define EXTI_IMR1_IM5              EXTI_IMR1_IM5_Msk                           /*!< Interrupt Mask on line 5 */

+#define EXTI_IMR1_IM6_Pos          (6U)

+#define EXTI_IMR1_IM6_Msk          (0x1UL << EXTI_IMR1_IM6_Pos)                /*!< 0x00000040 */

+#define EXTI_IMR1_IM6              EXTI_IMR1_IM6_Msk                           /*!< Interrupt Mask on line 6 */

+#define EXTI_IMR1_IM7_Pos          (7U)

+#define EXTI_IMR1_IM7_Msk          (0x1UL << EXTI_IMR1_IM7_Pos)                /*!< 0x00000080 */

+#define EXTI_IMR1_IM7              EXTI_IMR1_IM7_Msk                           /*!< Interrupt Mask on line 7 */

+#define EXTI_IMR1_IM8_Pos          (8U)

+#define EXTI_IMR1_IM8_Msk          (0x1UL << EXTI_IMR1_IM8_Pos)                /*!< 0x00000100 */

+#define EXTI_IMR1_IM8              EXTI_IMR1_IM8_Msk                           /*!< Interrupt Mask on line 8 */

+#define EXTI_IMR1_IM9_Pos          (9U)

+#define EXTI_IMR1_IM9_Msk          (0x1UL << EXTI_IMR1_IM9_Pos)                /*!< 0x00000200 */

+#define EXTI_IMR1_IM9              EXTI_IMR1_IM9_Msk                           /*!< Interrupt Mask on line 9 */

+#define EXTI_IMR1_IM10_Pos         (10U)

+#define EXTI_IMR1_IM10_Msk         (0x1UL << EXTI_IMR1_IM10_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR1_IM10             EXTI_IMR1_IM10_Msk                          /*!< Interrupt Mask on line 10 */

+#define EXTI_IMR1_IM11_Pos         (11U)

+#define EXTI_IMR1_IM11_Msk         (0x1UL << EXTI_IMR1_IM11_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR1_IM11             EXTI_IMR1_IM11_Msk                          /*!< Interrupt Mask on line 11 */

+#define EXTI_IMR1_IM12_Pos         (12U)

+#define EXTI_IMR1_IM12_Msk         (0x1UL << EXTI_IMR1_IM12_Pos)               /*!< 0x00001000 */

+#define EXTI_IMR1_IM12             EXTI_IMR1_IM12_Msk                          /*!< Interrupt Mask on line 12 */

+#define EXTI_IMR1_IM13_Pos         (13U)

+#define EXTI_IMR1_IM13_Msk         (0x1UL << EXTI_IMR1_IM13_Pos)               /*!< 0x00002000 */

+#define EXTI_IMR1_IM13             EXTI_IMR1_IM13_Msk                          /*!< Interrupt Mask on line 13 */

+#define EXTI_IMR1_IM14_Pos         (14U)

+#define EXTI_IMR1_IM14_Msk         (0x1UL << EXTI_IMR1_IM14_Pos)               /*!< 0x00004000 */

+#define EXTI_IMR1_IM14             EXTI_IMR1_IM14_Msk                          /*!< Interrupt Mask on line 14 */

+#define EXTI_IMR1_IM15_Pos         (15U)

+#define EXTI_IMR1_IM15_Msk         (0x1UL << EXTI_IMR1_IM15_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR1_IM15             EXTI_IMR1_IM15_Msk                          /*!< Interrupt Mask on line 15 */

+#define EXTI_IMR1_IM16_Pos         (16U)

+#define EXTI_IMR1_IM16_Msk         (0x1UL << EXTI_IMR1_IM16_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR1_IM16             EXTI_IMR1_IM16_Msk                          /*!< Interrupt Mask on line 16 */

+#define EXTI_IMR1_IM17_Pos         (17U)

+#define EXTI_IMR1_IM17_Msk         (0x1UL << EXTI_IMR1_IM17_Pos)               /*!< 0x00020000 */

+#define EXTI_IMR1_IM17             EXTI_IMR1_IM17_Msk                          /*!< Interrupt Mask on line 17 */

+#define EXTI_IMR1_IM18_Pos         (18U)

+#define EXTI_IMR1_IM18_Msk         (0x1UL << EXTI_IMR1_IM18_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR1_IM18             EXTI_IMR1_IM18_Msk                          /*!< Interrupt Mask on line 18 */

+#define EXTI_IMR1_IM19_Pos         (19U)

+#define EXTI_IMR1_IM19_Msk         (0x1UL << EXTI_IMR1_IM19_Pos)               /*!< 0x00080000 */

+#define EXTI_IMR1_IM19             EXTI_IMR1_IM19_Msk                          /*!< Interrupt Mask on line 19 */

+#define EXTI_IMR1_IM20_Pos         (20U)

+#define EXTI_IMR1_IM20_Msk         (0x1UL << EXTI_IMR1_IM20_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR1_IM20             EXTI_IMR1_IM20_Msk                          /*!< Interrupt Mask on line 20 */

+#define EXTI_IMR1_IM21_Pos         (21U)

+#define EXTI_IMR1_IM21_Msk         (0x1UL << EXTI_IMR1_IM21_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR1_IM21             EXTI_IMR1_IM21_Msk                          /*!< Interrupt Mask on line 21 */

+#define EXTI_IMR1_IM22_Pos         (22U)

+#define EXTI_IMR1_IM22_Msk         (0x1UL << EXTI_IMR1_IM22_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR1_IM22             EXTI_IMR1_IM22_Msk                          /*!< Interrupt Mask on line 22 */

+#define EXTI_IMR1_IM23_Pos         (23U)

+#define EXTI_IMR1_IM23_Msk         (0x1UL << EXTI_IMR1_IM23_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR1_IM23             EXTI_IMR1_IM23_Msk                          /*!< Interrupt Mask on line 23 */

+#define EXTI_IMR1_IM24_Pos         (24U)

+#define EXTI_IMR1_IM24_Msk         (0x1UL << EXTI_IMR1_IM24_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR1_IM24             EXTI_IMR1_IM24_Msk                          /*!< Interrupt Mask on line 24 */

+#define EXTI_IMR1_IM25_Pos         (25U)

+#define EXTI_IMR1_IM25_Msk         (0x1UL << EXTI_IMR1_IM25_Pos)               /*!< 0x02000000 */

+#define EXTI_IMR1_IM25             EXTI_IMR1_IM25_Msk                          /*!< Interrupt Mask on line 25 */

+#define EXTI_IMR1_IM26_Pos         (26U)

+#define EXTI_IMR1_IM26_Msk         (0x1UL << EXTI_IMR1_IM26_Pos)               /*!< 0x04000000 */

+#define EXTI_IMR1_IM26             EXTI_IMR1_IM26_Msk                          /*!< Interrupt Mask on line 26 */

+#define EXTI_IMR1_IM27_Pos         (27U)

+#define EXTI_IMR1_IM27_Msk         (0x1UL << EXTI_IMR1_IM27_Pos)               /*!< 0x08000000 */

+#define EXTI_IMR1_IM27             EXTI_IMR1_IM27_Msk                          /*!< Interrupt Mask on line 27 */

+#define EXTI_IMR1_IM28_Pos         (28U)

+#define EXTI_IMR1_IM28_Msk         (0x1UL << EXTI_IMR1_IM28_Pos)               /*!< 0x10000000 */

+#define EXTI_IMR1_IM28             EXTI_IMR1_IM28_Msk                          /*!< Interrupt Mask on line 28 */

+#define EXTI_IMR1_IM29_Pos         (29U)

+#define EXTI_IMR1_IM29_Msk         (0x1UL << EXTI_IMR1_IM29_Pos)               /*!< 0x20000000 */

+#define EXTI_IMR1_IM29             EXTI_IMR1_IM29_Msk                          /*!< Interrupt Mask on line 29 */

+#define EXTI_IMR1_IM30_Pos         (30U)

+#define EXTI_IMR1_IM30_Msk         (0x1UL << EXTI_IMR1_IM30_Pos)               /*!< 0x40000000 */

+#define EXTI_IMR1_IM30             EXTI_IMR1_IM30_Msk                          /*!< Interrupt Mask on line 30 */

+#define EXTI_IMR1_IM31_Pos         (31U)

+#define EXTI_IMR1_IM31_Msk         (0x1UL << EXTI_IMR1_IM31_Pos)               /*!< 0x80000000 */

+#define EXTI_IMR1_IM31             EXTI_IMR1_IM31_Msk                          /*!< Interrupt Mask on line 31 */

+

+/*******************  Bit definition for EXTI_EMR1 register  *******************/

+#define EXTI_EMR1_EM_Pos           (0U)

+#define EXTI_EMR1_EM_Msk           (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)          /*!< 0xFFFFFFFF */

+#define EXTI_EMR1_EM               EXTI_EMR1_EM_Msk                            /*!< Event Mask */

+#define EXTI_EMR1_EM0_Pos          (0U)

+#define EXTI_EMR1_EM0_Msk          (0x1UL << EXTI_EMR1_EM0_Pos)                /*!< 0x00000001 */

+#define EXTI_EMR1_EM0              EXTI_EMR1_EM0_Msk                           /*!< Event Mask on line 0 */

+#define EXTI_EMR1_EM1_Pos          (1U)

+#define EXTI_EMR1_EM1_Msk          (0x1UL << EXTI_EMR1_EM1_Pos)                /*!< 0x00000002 */

+#define EXTI_EMR1_EM1              EXTI_EMR1_EM1_Msk                           /*!< Event Mask on line 1 */

+#define EXTI_EMR1_EM2_Pos          (2U)

+#define EXTI_EMR1_EM2_Msk          (0x1UL << EXTI_EMR1_EM2_Pos)                /*!< 0x00000004 */

+#define EXTI_EMR1_EM2              EXTI_EMR1_EM2_Msk                           /*!< Event Mask on line 2 */

+#define EXTI_EMR1_EM3_Pos          (3U)

+#define EXTI_EMR1_EM3_Msk          (0x1UL << EXTI_EMR1_EM3_Pos)                /*!< 0x00000008 */

+#define EXTI_EMR1_EM3              EXTI_EMR1_EM3_Msk                           /*!< Event Mask on line 3 */

+#define EXTI_EMR1_EM4_Pos          (4U)

+#define EXTI_EMR1_EM4_Msk          (0x1UL << EXTI_EMR1_EM4_Pos)                /*!< 0x00000010 */

+#define EXTI_EMR1_EM4              EXTI_EMR1_EM4_Msk                           /*!< Event Mask on line 4 */

+#define EXTI_EMR1_EM5_Pos          (5U)

+#define EXTI_EMR1_EM5_Msk          (0x1UL << EXTI_EMR1_EM5_Pos)                /*!< 0x00000020 */

+#define EXTI_EMR1_EM5              EXTI_EMR1_EM5_Msk                           /*!< Event Mask on line 5 */

+#define EXTI_EMR1_EM6_Pos          (6U)

+#define EXTI_EMR1_EM6_Msk          (0x1UL << EXTI_EMR1_EM6_Pos)                /*!< 0x00000040 */

+#define EXTI_EMR1_EM6              EXTI_EMR1_EM6_Msk                           /*!< Event Mask on line 6 */

+#define EXTI_EMR1_EM7_Pos          (7U)

+#define EXTI_EMR1_EM7_Msk          (0x1UL << EXTI_EMR1_EM7_Pos)                /*!< 0x00000080 */

+#define EXTI_EMR1_EM7              EXTI_EMR1_EM7_Msk                           /*!< Event Mask on line 7 */

+#define EXTI_EMR1_EM8_Pos          (8U)

+#define EXTI_EMR1_EM8_Msk          (0x1UL << EXTI_EMR1_EM8_Pos)                /*!< 0x00000100 */

+#define EXTI_EMR1_EM8              EXTI_EMR1_EM8_Msk                           /*!< Event Mask on line 8 */

+#define EXTI_EMR1_EM9_Pos          (9U)

+#define EXTI_EMR1_EM9_Msk          (0x1UL << EXTI_EMR1_EM9_Pos)                /*!< 0x00000200 */

+#define EXTI_EMR1_EM9              EXTI_EMR1_EM9_Msk                           /*!< Event Mask on line 9 */

+#define EXTI_EMR1_EM10_Pos         (10U)

+#define EXTI_EMR1_EM10_Msk         (0x1UL << EXTI_EMR1_EM10_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR1_EM10             EXTI_EMR1_EM10_Msk                          /*!< Event Mask on line 10 */

+#define EXTI_EMR1_EM11_Pos         (11U)

+#define EXTI_EMR1_EM11_Msk         (0x1UL << EXTI_EMR1_EM11_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR1_EM11             EXTI_EMR1_EM11_Msk                          /*!< Event Mask on line 11 */

+#define EXTI_EMR1_EM12_Pos         (12U)

+#define EXTI_EMR1_EM12_Msk         (0x1UL << EXTI_EMR1_EM12_Pos)               /*!< 0x00001000 */

+#define EXTI_EMR1_EM12             EXTI_EMR1_EM12_Msk                          /*!< Event Mask on line 12 */

+#define EXTI_EMR1_EM13_Pos         (13U)

+#define EXTI_EMR1_EM13_Msk         (0x1UL << EXTI_EMR1_EM13_Pos)               /*!< 0x00002000 */

+#define EXTI_EMR1_EM13             EXTI_EMR1_EM13_Msk                          /*!< Event Mask on line 13 */

+#define EXTI_EMR1_EM14_Pos         (14U)

+#define EXTI_EMR1_EM14_Msk         (0x1UL << EXTI_EMR1_EM14_Pos)               /*!< 0x00004000 */

+#define EXTI_EMR1_EM14             EXTI_EMR1_EM14_Msk                          /*!< Event Mask on line 14 */

+#define EXTI_EMR1_EM15_Pos         (15U)

+#define EXTI_EMR1_EM15_Msk         (0x1UL << EXTI_EMR1_EM15_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR1_EM15             EXTI_EMR1_EM15_Msk                          /*!< Event Mask on line 15 */

+#define EXTI_EMR1_EM16_Pos         (16U)

+#define EXTI_EMR1_EM16_Msk         (0x1UL << EXTI_EMR1_EM16_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR1_EM16             EXTI_EMR1_EM16_Msk                          /*!< Event Mask on line 16 */

+#define EXTI_EMR1_EM17_Pos         (17U)

+#define EXTI_EMR1_EM17_Msk         (0x1UL << EXTI_EMR1_EM17_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR1_EM17             EXTI_EMR1_EM17_Msk                          /*!< Event Mask on line 17 */

+#define EXTI_EMR1_EM18_Pos         (18U)

+#define EXTI_EMR1_EM18_Msk         (0x1UL << EXTI_EMR1_EM18_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR1_EM18             EXTI_EMR1_EM18_Msk                          /*!< Event Mask on line 18 */

+#define EXTI_EMR1_EM20_Pos         (20U)

+#define EXTI_EMR1_EM20_Msk         (0x1UL << EXTI_EMR1_EM20_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR1_EM20             EXTI_EMR1_EM20_Msk                          /*!< Event Mask on line 20 */

+#define EXTI_EMR1_EM21_Pos         (21U)

+#define EXTI_EMR1_EM21_Msk         (0x1UL << EXTI_EMR1_EM21_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR1_EM21             EXTI_EMR1_EM21_Msk                          /*!< Event Mask on line 21 */

+#define EXTI_EMR1_EM22_Pos         (22U)

+#define EXTI_EMR1_EM22_Msk         (0x1UL << EXTI_EMR1_EM22_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR1_EM22             EXTI_EMR1_EM22_Msk                          /*!< Event Mask on line 22 */

+#define EXTI_EMR1_EM23_Pos         (23U)

+#define EXTI_EMR1_EM23_Msk         (0x1UL << EXTI_EMR1_EM23_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR1_EM23             EXTI_EMR1_EM23_Msk                          /*!< Event Mask on line 23 */

+#define EXTI_EMR1_EM24_Pos         (24U)

+#define EXTI_EMR1_EM24_Msk         (0x1UL << EXTI_EMR1_EM24_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR1_EM24             EXTI_EMR1_EM24_Msk                          /*!< Event Mask on line 24 */

+#define EXTI_EMR1_EM25_Pos         (25U)

+#define EXTI_EMR1_EM25_Msk         (0x1UL << EXTI_EMR1_EM25_Pos)               /*!< 0x02000000 */

+#define EXTI_EMR1_EM25             EXTI_EMR1_EM25_Msk                          /*!< Event Mask on line 25 */

+#define EXTI_EMR1_EM26_Pos         (26U)

+#define EXTI_EMR1_EM26_Msk         (0x1UL << EXTI_EMR1_EM26_Pos)               /*!< 0x04000000 */

+#define EXTI_EMR1_EM26             EXTI_EMR1_EM26_Msk                          /*!< Event Mask on line 26 */

+#define EXTI_EMR1_EM27_Pos         (27U)

+#define EXTI_EMR1_EM27_Msk         (0x1UL << EXTI_EMR1_EM27_Pos)               /*!< 0x08000000 */

+#define EXTI_EMR1_EM27             EXTI_EMR1_EM27_Msk                          /*!< Event Mask on line 27 */

+#define EXTI_EMR1_EM28_Pos         (28U)

+#define EXTI_EMR1_EM28_Msk         (0x1UL << EXTI_EMR1_EM28_Pos)               /*!< 0x10000000 */

+#define EXTI_EMR1_EM28             EXTI_EMR1_EM28_Msk                          /*!< Event Mask on line 28 */

+#define EXTI_EMR1_EM29_Pos         (29U)

+#define EXTI_EMR1_EM29_Msk         (0x1UL << EXTI_EMR1_EM29_Pos)               /*!< 0x20000000 */

+#define EXTI_EMR1_EM29             EXTI_EMR1_EM29_Msk                          /*!< Event Mask on line 29 */

+#define EXTI_EMR1_EM30_Pos         (30U)

+#define EXTI_EMR1_EM30_Msk         (0x1UL << EXTI_EMR1_EM30_Pos)               /*!< 0x40000000 */

+#define EXTI_EMR1_EM30             EXTI_EMR1_EM30_Msk                          /*!< Event Mask on line 30 */

+#define EXTI_EMR1_EM31_Pos         (31U)

+#define EXTI_EMR1_EM31_Msk         (0x1UL << EXTI_EMR1_EM31_Pos)               /*!< 0x80000000 */

+#define EXTI_EMR1_EM31             EXTI_EMR1_EM31_Msk                          /*!< Event Mask on line 31 */

+

+/*******************  Bit definition for EXTI_PR1 register  ********************/

+#define EXTI_PR1_PR_Pos            (0U)

+#define EXTI_PR1_PR_Msk            (0x3FFFFFUL << EXTI_PR1_PR_Pos)             /*!< 0x003FFFFF */

+#define EXTI_PR1_PR                EXTI_PR1_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR1_PR0_Pos           (0U)

+#define EXTI_PR1_PR0_Msk           (0x1UL << EXTI_PR1_PR0_Pos)                 /*!< 0x00000001 */

+#define EXTI_PR1_PR0               EXTI_PR1_PR0_Msk                            /*!< Pending bit for line 0 */

+#define EXTI_PR1_PR1_Pos           (1U)

+#define EXTI_PR1_PR1_Msk           (0x1UL << EXTI_PR1_PR1_Pos)                 /*!< 0x00000002 */

+#define EXTI_PR1_PR1               EXTI_PR1_PR1_Msk                            /*!< Pending bit for line 1 */

+#define EXTI_PR1_PR2_Pos           (2U)

+#define EXTI_PR1_PR2_Msk           (0x1UL << EXTI_PR1_PR2_Pos)                 /*!< 0x00000004 */

+#define EXTI_PR1_PR2               EXTI_PR1_PR2_Msk                            /*!< Pending bit for line 2 */

+#define EXTI_PR1_PR3_Pos           (3U)

+#define EXTI_PR1_PR3_Msk           (0x1UL << EXTI_PR1_PR3_Pos)                 /*!< 0x00000008 */

+#define EXTI_PR1_PR3               EXTI_PR1_PR3_Msk                            /*!< Pending bit for line 3 */

+#define EXTI_PR1_PR4_Pos           (4U)

+#define EXTI_PR1_PR4_Msk           (0x1UL << EXTI_PR1_PR4_Pos)                 /*!< 0x00000010 */

+#define EXTI_PR1_PR4               EXTI_PR1_PR4_Msk                            /*!< Pending bit for line 4 */

+#define EXTI_PR1_PR5_Pos           (5U)

+#define EXTI_PR1_PR5_Msk           (0x1UL << EXTI_PR1_PR5_Pos)                 /*!< 0x00000020 */

+#define EXTI_PR1_PR5               EXTI_PR1_PR5_Msk                            /*!< Pending bit for line 5 */

+#define EXTI_PR1_PR6_Pos           (6U)

+#define EXTI_PR1_PR6_Msk           (0x1UL << EXTI_PR1_PR6_Pos)                 /*!< 0x00000040 */

+#define EXTI_PR1_PR6               EXTI_PR1_PR6_Msk                            /*!< Pending bit for line 6 */

+#define EXTI_PR1_PR7_Pos           (7U)

+#define EXTI_PR1_PR7_Msk           (0x1UL << EXTI_PR1_PR7_Pos)                 /*!< 0x00000080 */

+#define EXTI_PR1_PR7               EXTI_PR1_PR7_Msk                            /*!< Pending bit for line 7 */

+#define EXTI_PR1_PR8_Pos           (8U)

+#define EXTI_PR1_PR8_Msk           (0x1UL << EXTI_PR1_PR8_Pos)                 /*!< 0x00000100 */

+#define EXTI_PR1_PR8               EXTI_PR1_PR8_Msk                            /*!< Pending bit for line 8 */

+#define EXTI_PR1_PR9_Pos           (9U)

+#define EXTI_PR1_PR9_Msk           (0x1UL << EXTI_PR1_PR9_Pos)                 /*!< 0x00000200 */

+#define EXTI_PR1_PR9               EXTI_PR1_PR9_Msk                            /*!< Pending bit for line 9 */

+#define EXTI_PR1_PR10_Pos          (10U)

+#define EXTI_PR1_PR10_Msk          (0x1UL << EXTI_PR1_PR10_Pos)                /*!< 0x00000400 */

+#define EXTI_PR1_PR10              EXTI_PR1_PR10_Msk                           /*!< Pending bit for line 10 */

+#define EXTI_PR1_PR11_Pos          (11U)

+#define EXTI_PR1_PR11_Msk          (0x1UL << EXTI_PR1_PR11_Pos)                /*!< 0x00000800 */

+#define EXTI_PR1_PR11              EXTI_PR1_PR11_Msk                           /*!< Pending bit for line 11 */

+#define EXTI_PR1_PR12_Pos          (12U)

+#define EXTI_PR1_PR12_Msk          (0x1UL << EXTI_PR1_PR12_Pos)                /*!< 0x00001000 */

+#define EXTI_PR1_PR12              EXTI_PR1_PR12_Msk                           /*!< Pending bit for line 12 */

+#define EXTI_PR1_PR13_Pos          (13U)

+#define EXTI_PR1_PR13_Msk          (0x1UL << EXTI_PR1_PR13_Pos)                /*!< 0x00002000 */

+#define EXTI_PR1_PR13              EXTI_PR1_PR13_Msk                           /*!< Pending bit for line 13 */

+#define EXTI_PR1_PR14_Pos          (14U)

+#define EXTI_PR1_PR14_Msk          (0x1UL << EXTI_PR1_PR14_Pos)                /*!< 0x00004000 */

+#define EXTI_PR1_PR14              EXTI_PR1_PR14_Msk                           /*!< Pending bit for line 14 */

+#define EXTI_PR1_PR15_Pos          (15U)

+#define EXTI_PR1_PR15_Msk          (0x1UL << EXTI_PR1_PR15_Pos)                /*!< 0x00008000 */

+#define EXTI_PR1_PR15              EXTI_PR1_PR15_Msk                           /*!< Pending bit for line 15 */

+#define EXTI_PR1_PR16_Pos          (16U)

+#define EXTI_PR1_PR16_Msk          (0x1UL << EXTI_PR1_PR16_Pos)                /*!< 0x00010000 */

+#define EXTI_PR1_PR16              EXTI_PR1_PR16_Msk                           /*!< Pending bit for line 16 */

+#define EXTI_PR1_PR17_Pos          (17U)

+#define EXTI_PR1_PR17_Msk          (0x1UL << EXTI_PR1_PR17_Pos)                /*!< 0x00020000 */

+#define EXTI_PR1_PR17              EXTI_PR1_PR17_Msk                           /*!< Pending bit for line 17 */

+#define EXTI_PR1_PR18_Pos          (18U)

+#define EXTI_PR1_PR18_Msk          (0x1UL << EXTI_PR1_PR18_Pos)                /*!< 0x00040000 */

+#define EXTI_PR1_PR18              EXTI_PR1_PR18_Msk                           /*!< Pending bit for line 18 */

+#define EXTI_PR1_PR19_Pos          (19U)

+#define EXTI_PR1_PR19_Msk          (0x1UL << EXTI_PR1_PR19_Pos)                /*!< 0x00080000 */

+#define EXTI_PR1_PR19              EXTI_PR1_PR19_Msk                           /*!< Pending bit for line 19 */

+#define EXTI_PR1_PR20_Pos          (20U)

+#define EXTI_PR1_PR20_Msk          (0x1UL << EXTI_PR1_PR20_Pos)                /*!< 0x00100000 */

+#define EXTI_PR1_PR20              EXTI_PR1_PR20_Msk                           /*!< Pending bit for line 20 */

+#define EXTI_PR1_PR21_Pos          (21U)

+#define EXTI_PR1_PR21_Msk          (0x1UL << EXTI_PR1_PR21_Pos)                /*!< 0x00200000 */

+#define EXTI_PR1_PR21              EXTI_PR1_PR21_Msk                           /*!< Pending bit for line 21 */

+

+/*******************  Bit definition for EXTI_IMR2 register  *******************/

+#define EXTI_IMR2_IM_Pos           (0U)

+#define EXTI_IMR2_IM_Msk           (0xFFFF8FFFUL << EXTI_IMR2_IM_Pos)          /*!< 0xFFFF8FFF */

+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            /*!< Interrupt Mask            */

+#define EXTI_IMR2_IM32_Pos         (0U)

+#define EXTI_IMR2_IM32_Msk         (0x1UL << EXTI_IMR2_IM32_Pos)               /*!< 0x00000001 */

+#define EXTI_IMR2_IM32             EXTI_IMR2_IM32_Msk                          /*!< Interrupt Mask on line 32 */

+#define EXTI_IMR2_IM33_Pos         (1U)

+#define EXTI_IMR2_IM33_Msk         (0x1UL << EXTI_IMR2_IM33_Pos)               /*!< 0x00000002 */

+#define EXTI_IMR2_IM33             EXTI_IMR2_IM33_Msk                          /*!< Interrupt Mask on line 33 */

+#define EXTI_IMR2_IM34_Pos         (2U)

+#define EXTI_IMR2_IM34_Msk         (0x1UL << EXTI_IMR2_IM34_Pos)               /*!< 0x00000004 */

+#define EXTI_IMR2_IM34             EXTI_IMR2_IM34_Msk                          /*!< Interrupt Mask on line 34 */

+#define EXTI_IMR2_IM35_Pos         (3U)

+#define EXTI_IMR2_IM35_Msk         (0x1UL << EXTI_IMR2_IM35_Pos)               /*!< 0x00000008 */

+#define EXTI_IMR2_IM35             EXTI_IMR2_IM35_Msk                          /*!< Interrupt Mask on line 35 */

+#define EXTI_IMR2_IM36_Pos         (4U)

+#define EXTI_IMR2_IM36_Msk         (0x1UL << EXTI_IMR2_IM36_Pos)               /*!< 0x00000010 */

+#define EXTI_IMR2_IM36             EXTI_IMR2_IM36_Msk                          /*!< Interrupt Mask on line 36 */

+#define EXTI_IMR2_IM37_Pos         (5U)

+#define EXTI_IMR2_IM37_Msk         (0x1UL << EXTI_IMR2_IM37_Pos)               /*!< 0x00000020 */

+#define EXTI_IMR2_IM37             EXTI_IMR2_IM37_Msk                          /*!< Interrupt Mask on line 37 */

+#define EXTI_IMR2_IM38_Pos         (6U)

+#define EXTI_IMR2_IM38_Msk         (0x1UL << EXTI_IMR2_IM38_Pos)               /*!< 0x00000040 */

+#define EXTI_IMR2_IM38             EXTI_IMR2_IM38_Msk                          /*!< Interrupt Mask on line 38 */

+#define EXTI_IMR2_IM39_Pos         (7U)

+#define EXTI_IMR2_IM39_Msk         (0x1UL << EXTI_IMR2_IM39_Pos)               /*!< 0x00000080 */

+#define EXTI_IMR2_IM39             EXTI_IMR2_IM39_Msk                          /*!< Interrupt Mask on line 39 */

+#define EXTI_IMR2_IM40_Pos         (8U)

+#define EXTI_IMR2_IM40_Msk         (0x1UL << EXTI_IMR2_IM40_Pos)               /*!< 0x00000100 */

+#define EXTI_IMR2_IM40             EXTI_IMR2_IM40_Msk                          /*!< Interrupt Mask on line 40 */

+#define EXTI_IMR2_IM41_Pos         (9U)

+#define EXTI_IMR2_IM41_Msk         (0x1UL << EXTI_IMR2_IM41_Pos)               /*!< 0x00000200 */

+#define EXTI_IMR2_IM41             EXTI_IMR2_IM41_Msk                          /*!< Interrupt Mask on line 41 */

+#define EXTI_IMR2_IM42_Pos         (10U)

+#define EXTI_IMR2_IM42_Msk         (0x1UL << EXTI_IMR2_IM42_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR2_IM42             EXTI_IMR2_IM42_Msk                          /*!< Interrupt Mask on line 42 */

+#define EXTI_IMR2_IM43_Pos         (11U)

+#define EXTI_IMR2_IM43_Msk         (0x1UL << EXTI_IMR2_IM43_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR2_IM43             EXTI_IMR2_IM43_Msk                          /*!< Interrupt Mask on line 43 */

+#define EXTI_IMR2_IM47_Pos         (15U)

+#define EXTI_IMR2_IM47_Msk         (0x1UL << EXTI_IMR2_IM47_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR2_IM47             EXTI_IMR2_IM47_Msk                          /*!< Interrupt Mask on line 47 */

+#define EXTI_IMR2_IM48_Pos         (16U)

+#define EXTI_IMR2_IM48_Msk         (0x1UL << EXTI_IMR2_IM48_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR2_IM48             EXTI_IMR2_IM48_Msk                          /*!< Interrupt Mask on line 48 */

+#define EXTI_IMR2_IM49_Pos         (17U)

+#define EXTI_IMR2_IM49_Msk         (0x1UL << EXTI_IMR2_IM49_Pos)               /*!< 0x00020000 */

+#define EXTI_IMR2_IM49             EXTI_IMR2_IM49_Msk                          /*!< Interrupt Mask on line 49 */

+#define EXTI_IMR2_IM50_Pos         (18U)

+#define EXTI_IMR2_IM50_Msk         (0x1UL << EXTI_IMR2_IM50_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR2_IM50             EXTI_IMR2_IM50_Msk                          /*!< Interrupt Mask on line 50 */

+#define EXTI_IMR2_IM51_Pos         (19U)

+#define EXTI_IMR2_IM51_Msk         (0x1UL << EXTI_IMR2_IM51_Pos)               /*!< 0x00080000 */

+#define EXTI_IMR2_IM51             EXTI_IMR2_IM51_Msk                          /*!< Interrupt Mask on line 51 */

+#define EXTI_IMR2_IM52_Pos         (20U)

+#define EXTI_IMR2_IM52_Msk         (0x1UL << EXTI_IMR2_IM52_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR2_IM52             EXTI_IMR2_IM52_Msk                          /*!< Interrupt Mask on line 52 */

+#define EXTI_IMR2_IM53_Pos         (21U)

+#define EXTI_IMR2_IM53_Msk         (0x1UL << EXTI_IMR2_IM53_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR2_IM53             EXTI_IMR2_IM53_Msk                          /*!< Interrupt Mask on line 53 */

+#define EXTI_IMR2_IM54_Pos         (22U)

+#define EXTI_IMR2_IM54_Msk         (0x1UL << EXTI_IMR2_IM54_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR2_IM54             EXTI_IMR2_IM54_Msk                          /*!< Interrupt Mask on line 54 */

+#define EXTI_IMR2_IM55_Pos         (23U)

+#define EXTI_IMR2_IM55_Msk         (0x1UL << EXTI_IMR2_IM55_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR2_IM55             EXTI_IMR2_IM55_Msk                          /*!< Interrupt Mask on line 55 */

+#define EXTI_IMR2_IM56_Pos         (24U)

+#define EXTI_IMR2_IM56_Msk         (0x1UL << EXTI_IMR2_IM56_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR2_IM56             EXTI_IMR2_IM56_Msk                          /*!< Interrupt Mask on line 56 */

+#define EXTI_IMR2_IM57_Pos         (25U)

+#define EXTI_IMR2_IM57_Msk         (0x1UL << EXTI_IMR2_IM57_Pos)               /*!< 0x02000000 */

+#define EXTI_IMR2_IM57             EXTI_IMR2_IM57_Msk                          /*!< Interrupt Mask on line 57 */

+#define EXTI_IMR2_IM58_Pos         (26U)

+#define EXTI_IMR2_IM58_Msk         (0x1UL << EXTI_IMR2_IM58_Pos)               /*!< 0x04000000 */

+#define EXTI_IMR2_IM58             EXTI_IMR2_IM58_Msk                          /*!< Interrupt Mask on line 58 */

+#define EXTI_IMR2_IM59_Pos         (27U)

+#define EXTI_IMR2_IM59_Msk         (0x1UL << EXTI_IMR2_IM59_Pos)               /*!< 0x08000000 */

+#define EXTI_IMR2_IM59             EXTI_IMR2_IM59_Msk                          /*!< Interrupt Mask on line 59 */

+#define EXTI_IMR2_IM60_Pos         (28U)

+#define EXTI_IMR2_IM60_Msk         (0x1UL << EXTI_IMR2_IM60_Pos)               /*!< 0x10000000 */

+#define EXTI_IMR2_IM60             EXTI_IMR2_IM60_Msk                          /*!< Interrupt Mask on line 60 */

+#define EXTI_IMR2_IM61_Pos         (29U)

+#define EXTI_IMR2_IM61_Msk         (0x1UL << EXTI_IMR2_IM61_Pos)               /*!< 0x20000000 */

+#define EXTI_IMR2_IM61             EXTI_IMR2_IM61_Msk                          /*!< Interrupt Mask on line 61 */

+#define EXTI_IMR2_IM62_Pos         (30U)

+#define EXTI_IMR2_IM62_Msk         (0x1UL << EXTI_IMR2_IM62_Pos)               /*!< 0x40000000 */

+#define EXTI_IMR2_IM62             EXTI_IMR2_IM62_Msk                          /*!< Interrupt Mask on line 62 */

+#define EXTI_IMR2_IM63_Pos         (31U)

+#define EXTI_IMR2_IM63_Msk         (0x1UL << EXTI_IMR2_IM63_Pos)               /*!< 0x80000000 */

+#define EXTI_IMR2_IM63             EXTI_IMR2_IM63_Msk                          /*!< Interrupt Mask on line 63 */

+

+/*******************  Bit definition for EXTI_EMR2 register  *******************/

+#define EXTI_EMR2_EM_Pos           (0U)

+#define EXTI_EMR2_EM_Msk           (0xFFFF8FFFUL << EXTI_EMR2_EM_Pos)          /*!< 0xFFFF8FFF */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            /*!< Event Mask           */

+#define EXTI_EMR2_EM32_Pos         (0U)

+#define EXTI_EMR2_EM32_Msk         (0x1UL << EXTI_EMR2_EM32_Pos)               /*!< 0x00000001 */

+#define EXTI_EMR2_EM32             EXTI_EMR2_EM32_Msk                          /*!< Event Mask on line 32*/

+#define EXTI_EMR2_EM33_Pos         (1U)

+#define EXTI_EMR2_EM33_Msk         (0x1UL << EXTI_EMR2_EM33_Pos)               /*!< 0x00000002 */

+#define EXTI_EMR2_EM33             EXTI_EMR2_EM33_Msk                          /*!< Event Mask on line 33*/

+#define EXTI_EMR2_EM34_Pos         (2U)

+#define EXTI_EMR2_EM34_Msk         (0x1UL << EXTI_EMR2_EM34_Pos)               /*!< 0x00000004 */

+#define EXTI_EMR2_EM34             EXTI_EMR2_EM34_Msk                          /*!< Event Mask on line 34*/

+#define EXTI_EMR2_EM35_Pos         (3U)

+#define EXTI_EMR2_EM35_Msk         (0x1UL << EXTI_EMR2_EM35_Pos)               /*!< 0x00000008 */

+#define EXTI_EMR2_EM35             EXTI_EMR2_EM35_Msk                          /*!< Event Mask on line 35*/

+#define EXTI_EMR2_EM36_Pos         (4U)

+#define EXTI_EMR2_EM36_Msk         (0x1UL << EXTI_EMR2_EM36_Pos)               /*!< 0x00000010 */

+#define EXTI_EMR2_EM36             EXTI_EMR2_EM36_Msk                          /*!< Event Mask on line 36*/

+#define EXTI_EMR2_EM37_Pos         (5U)

+#define EXTI_EMR2_EM37_Msk         (0x1UL << EXTI_EMR2_EM37_Pos)               /*!< 0x00000020 */

+#define EXTI_EMR2_EM37             EXTI_EMR2_EM37_Msk                          /*!< Event Mask on line 37*/

+#define EXTI_EMR2_EM38_Pos         (6U)

+#define EXTI_EMR2_EM38_Msk         (0x1UL << EXTI_EMR2_EM38_Pos)               /*!< 0x00000040 */

+#define EXTI_EMR2_EM38             EXTI_EMR2_EM38_Msk                          /*!< Event Mask on line 38*/

+#define EXTI_EMR2_EM39_Pos         (7U)

+#define EXTI_EMR2_EM39_Msk         (0x1UL << EXTI_EMR2_EM39_Pos)               /*!< 0x00000080 */

+#define EXTI_EMR2_EM39             EXTI_EMR2_EM39_Msk                          /*!< Event Mask on line 39*/

+#define EXTI_EMR2_EM40_Pos         (8U)

+#define EXTI_EMR2_EM40_Msk         (0x1UL << EXTI_EMR2_EM40_Pos)               /*!< 0x00000100 */

+#define EXTI_EMR2_EM40             EXTI_EMR2_EM40_Msk                          /*!< Event Mask on line 40*/

+#define EXTI_EMR2_EM41_Pos         (9U)

+#define EXTI_EMR2_EM41_Msk         (0x1UL << EXTI_EMR2_EM41_Pos)               /*!< 0x00000200 */

+#define EXTI_EMR2_EM41             EXTI_EMR2_EM41_Msk                          /*!< Event Mask on line 41*/

+#define EXTI_EMR2_EM42_Pos         (10U)

+#define EXTI_EMR2_EM42_Msk         (0x1UL << EXTI_EMR2_EM42_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR2_EM42             EXTI_EMR2_EM42_Msk                          /*!< Event Mask on line 42 */

+#define EXTI_EMR2_EM43_Pos         (11U)

+#define EXTI_EMR2_EM43_Msk         (0x1UL << EXTI_EMR2_EM43_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR2_EM43             EXTI_EMR2_EM43_Msk                          /*!< Event Mask on line 43 */

+#define EXTI_EMR2_EM47_Pos         (15U)

+#define EXTI_EMR2_EM47_Msk         (0x1UL << EXTI_EMR2_EM47_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR2_EM47             EXTI_EMR2_EM47_Msk                          /*!< Event Mask on line 47 */

+#define EXTI_EMR2_EM48_Pos         (16U)

+#define EXTI_EMR2_EM48_Msk         (0x1UL << EXTI_EMR2_EM48_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR2_EM48             EXTI_EMR2_EM48_Msk                          /*!< Event Mask on line 48 */

+#define EXTI_EMR2_EM49_Pos         (17U)

+#define EXTI_EMR2_EM49_Msk         (0x1UL << EXTI_EMR2_EM49_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR2_EM49             EXTI_EMR2_EM49_Msk                          /*!< Event Mask on line 49 */

+#define EXTI_EMR2_EM50_Pos         (18U)

+#define EXTI_EMR2_EM50_Msk         (0x1UL << EXTI_EMR2_EM50_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR2_EM50             EXTI_EMR2_EM50_Msk                          /*!< Event Mask on line 50 */

+#define EXTI_EMR2_EM51_Pos         (19U)

+#define EXTI_EMR2_EM51_Msk         (0x1UL << EXTI_EMR2_EM51_Pos)               /*!< 0x00080000 */

+#define EXTI_EMR2_EM51             EXTI_EMR2_EM51_Msk                          /*!< Event Mask on line 51 */

+#define EXTI_EMR2_EM52_Pos         (20U)

+#define EXTI_EMR2_EM52_Msk         (0x1UL << EXTI_EMR2_EM52_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR2_EM52             EXTI_EMR2_EM52_Msk                          /*!< Event Mask on line 52 */

+#define EXTI_EMR2_EM53_Pos         (21U)

+#define EXTI_EMR2_EM53_Msk         (0x1UL << EXTI_EMR2_EM53_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR2_EM53             EXTI_EMR2_EM53_Msk                          /*!< Event Mask on line 53 */

+#define EXTI_EMR2_EM54_Pos         (22U)

+#define EXTI_EMR2_EM54_Msk         (0x1UL << EXTI_EMR2_EM54_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR2_EM54             EXTI_EMR2_EM54_Msk                          /*!< Event Mask on line 54 */

+#define EXTI_EMR2_EM55_Pos         (23U)

+#define EXTI_EMR2_EM55_Msk         (0x1UL << EXTI_EMR2_EM55_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR2_EM55             EXTI_EMR2_EM55_Msk                          /*!< Event Mask on line 55 */

+#define EXTI_EMR2_EM56_Pos         (24U)

+#define EXTI_EMR2_EM56_Msk         (0x1UL << EXTI_EMR2_EM56_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR2_EM56             EXTI_EMR2_EM56_Msk                          /*!< Event Mask on line 56 */

+#define EXTI_EMR2_EM57_Pos         (25U)

+#define EXTI_EMR2_EM57_Msk         (0x1UL << EXTI_EMR2_EM57_Pos)               /*!< 0x02000000 */

+#define EXTI_EMR2_EM57             EXTI_EMR2_EM57_Msk                          /*!< Event Mask on line 57 */

+#define EXTI_EMR2_EM58_Pos         (26U)

+#define EXTI_EMR2_EM58_Msk         (0x1UL << EXTI_EMR2_EM58_Pos)               /*!< 0x04000000 */

+#define EXTI_EMR2_EM58             EXTI_EMR2_EM58_Msk                          /*!< Event Mask on line 58 */

+#define EXTI_EMR2_EM59_Pos         (27U)

+#define EXTI_EMR2_EM59_Msk         (0x1UL << EXTI_EMR2_EM59_Pos)               /*!< 0x08000000 */

+#define EXTI_EMR2_EM59             EXTI_EMR2_EM59_Msk                          /*!< Event Mask on line 59 */

+#define EXTI_EMR2_EM60_Pos         (28U)

+#define EXTI_EMR2_EM60_Msk         (0x1UL << EXTI_EMR2_EM60_Pos)               /*!< 0x10000000 */

+#define EXTI_EMR2_EM60             EXTI_EMR2_EM60_Msk                          /*!< Event Mask on line 60 */

+#define EXTI_EMR2_EM61_Pos         (29U)

+#define EXTI_EMR2_EM61_Msk         (0x1UL << EXTI_EMR2_EM61_Pos)               /*!< 0x20000000 */

+#define EXTI_EMR2_EM61             EXTI_EMR2_EM61_Msk                          /*!< Event Mask on line 61 */

+#define EXTI_EMR2_EM62_Pos         (30U)

+#define EXTI_EMR2_EM62_Msk         (0x1UL << EXTI_EMR2_EM62_Pos)               /*!< 0x40000000 */

+#define EXTI_EMR2_EM62             EXTI_EMR2_EM62_Msk                          /*!< Event Mask on line 62 */

+#define EXTI_EMR2_EM63_Pos         (31U)

+#define EXTI_EMR2_EM63_Msk         (0x1UL << EXTI_EMR2_EM63_Pos)               /*!< 0x80000000 */

+#define EXTI_EMR2_EM63             EXTI_EMR2_EM63_Msk                          /*!< Event Mask on line 63 */

+

+/*******************  Bit definition for EXTI_PR2 register  ********************/

+#define EXTI_PR2_PR_Pos            (17U)

+#define EXTI_PR2_PR_Msk            (0x5UL << EXTI_PR2_PR_Pos)                  /*!< 0x000A0000 */

+#define EXTI_PR2_PR                EXTI_PR2_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR2_PR49_Pos          (17U)

+#define EXTI_PR2_PR49_Msk          (0x1UL << EXTI_PR2_PR49_Pos)                /*!< 0x00020000 */

+#define EXTI_PR2_PR49              EXTI_PR2_PR49_Msk                           /*!< Pending bit for line 49 */

+#define EXTI_PR2_PR51_Pos          (19U)

+#define EXTI_PR2_PR51_Msk          (0x1UL << EXTI_PR2_PR51_Pos)                /*!< 0x00080000 */

+#define EXTI_PR2_PR51              EXTI_PR2_PR51_Msk                           /*!< Pending bit for line 51 */

+

+/*******************  Bit definition for EXTI_IMR3 register  *******************/

+#define EXTI_IMR3_IM_Pos           (0U)

+#define EXTI_IMR3_IM_Msk           (0x001A527FFUL << EXTI_IMR3_IM_Pos)         /*!< 0x001A527FF */

+#define EXTI_IMR3_IM               EXTI_IMR3_IM_Msk                            /*!< Interrupt Mask            */

+#define EXTI_IMR3_IM64_Pos         (0U)

+#define EXTI_IMR3_IM64_Msk         (0x1UL << EXTI_IMR3_IM64_Pos)               /*!< 0x00000001 */

+#define EXTI_IMR3_IM64             EXTI_IMR3_IM64_Msk                          /*!< Interrupt Mask on line 64 */

+#define EXTI_IMR3_IM65_Pos         (1U)

+#define EXTI_IMR3_IM65_Msk         (0x1UL << EXTI_IMR3_IM65_Pos)               /*!< 0x00000002 */

+#define EXTI_IMR3_IM65             EXTI_IMR3_IM65_Msk                          /*!< Interrupt Mask on line 65 */

+#define EXTI_IMR3_IM66_Pos         (2U)

+#define EXTI_IMR3_IM66_Msk         (0x1UL << EXTI_IMR3_IM66_Pos)               /*!< 0x00000004 */

+#define EXTI_IMR3_IM66             EXTI_IMR3_IM66_Msk                          /*!< Interrupt Mask on line 66 */

+#define EXTI_IMR3_IM67_Pos         (3U)

+#define EXTI_IMR3_IM67_Msk         (0x1UL << EXTI_IMR3_IM67_Pos)               /*!< 0x00000008 */

+#define EXTI_IMR3_IM67             EXTI_IMR3_IM67_Msk                          /*!< Interrupt Mask on line 67 */

+#define EXTI_IMR3_IM68_Pos         (4U)

+#define EXTI_IMR3_IM68_Msk         (0x1UL << EXTI_IMR3_IM68_Pos)               /*!< 0x00000010 */

+#define EXTI_IMR3_IM68             EXTI_IMR3_IM68_Msk                          /*!< Interrupt Mask on line 68 */

+#define EXTI_IMR3_IM69_Pos         (5U)

+#define EXTI_IMR3_IM69_Msk         (0x1UL << EXTI_IMR3_IM69_Pos)               /*!< 0x00000020 */

+#define EXTI_IMR3_IM69             EXTI_IMR3_IM69_Msk                          /*!< Interrupt Mask on line 69 */

+#define EXTI_IMR3_IM70_Pos         (6U)

+#define EXTI_IMR3_IM70_Msk         (0x1UL << EXTI_IMR3_IM70_Pos)               /*!< 0x00000040 */

+#define EXTI_IMR3_IM70             EXTI_IMR3_IM70_Msk                          /*!< Interrupt Mask on line 70 */

+#define EXTI_IMR3_IM71_Pos         (7U)

+#define EXTI_IMR3_IM71_Msk         (0x1UL << EXTI_IMR3_IM71_Pos)               /*!< 0x00000080 */

+#define EXTI_IMR3_IM71             EXTI_IMR3_IM71_Msk                          /*!< Interrupt Mask on line 71 */

+#define EXTI_IMR3_IM72_Pos         (8U)

+#define EXTI_IMR3_IM72_Msk         (0x1UL << EXTI_IMR3_IM72_Pos)               /*!< 0x00000100 */

+#define EXTI_IMR3_IM72             EXTI_IMR3_IM72_Msk                          /*!< Interrupt Mask on line 72 */

+#define EXTI_IMR3_IM73_Pos         (9U)

+#define EXTI_IMR3_IM73_Msk         (0x1UL << EXTI_IMR3_IM73_Pos)               /*!< 0x00000200 */

+#define EXTI_IMR3_IM73             EXTI_IMR3_IM73_Msk                          /*!< Interrupt Mask on line 73 */

+#define EXTI_IMR3_IM74_Pos         (10U)

+#define EXTI_IMR3_IM74_Msk         (0x1UL << EXTI_IMR3_IM74_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR3_IM74             EXTI_IMR3_IM74_Msk                          /*!< Interrupt Mask on line 74 */

+#define EXTI_IMR3_IM77_Pos         (13U)

+#define EXTI_IMR3_IM77_Msk         (0x1UL << EXTI_IMR3_IM77_Pos)               /*!< 0x00002000 */

+#define EXTI_IMR3_IM77             EXTI_IMR3_IM77_Msk                          /*!< Interrupt Mask on line 77 */

+#define EXTI_IMR3_IM80_Pos         (16U)

+#define EXTI_IMR3_IM80_Msk         (0x1UL << EXTI_IMR3_IM80_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR3_IM80             EXTI_IMR3_IM80_Msk                          /*!< Interrupt Mask on line 80 */

+#define EXTI_IMR3_IM82_Pos         (18U)

+#define EXTI_IMR3_IM82_Msk         (0x1UL << EXTI_IMR3_IM82_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR3_IM82             EXTI_IMR3_IM82_Msk                          /*!< Interrupt Mask on line 82 */

+#define EXTI_IMR3_IM85_Pos         (21U)

+#define EXTI_IMR3_IM85_Msk         (0x1UL << EXTI_IMR3_IM85_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR3_IM85             EXTI_IMR3_IM85_Msk                          /*!< Interrupt Mask on line 85 */

+#define EXTI_IMR3_IM87_Pos         (23U)

+#define EXTI_IMR3_IM87_Msk         (0x1UL << EXTI_IMR3_IM87_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR3_IM87             EXTI_IMR3_IM87_Msk                          /*!< Interrupt Mask on line 87 */

+

+

+#define EXTI_IMR3_IM88_Pos         (24U)

+#define EXTI_IMR3_IM88_Msk         (0x1UL << EXTI_IMR3_IM88_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR3_IM88             EXTI_IMR3_IM88_Msk                          /*!< Interrupt Mask on line 88 */

+

+/*******************  Bit definition for EXTI_EMR3 register  *******************/

+#define EXTI_EMR3_EM_Pos           (0U)

+#define EXTI_EMR3_EM_Msk           (0x01A527FFUL << EXTI_EMR3_EM_Pos)          /*!< 0x01A527FF */

+#define EXTI_EMR3_EM               EXTI_EMR3_EM_Msk                            /*!< Event Mask           */

+#define EXTI_EMR3_EM64_Pos         (0U)

+#define EXTI_EMR3_EM64_Msk         (0x1UL << EXTI_EMR3_EM64_Pos)               /*!< 0x00000001 */

+#define EXTI_EMR3_EM64             EXTI_EMR3_EM64_Msk                          /*!< Event Mask on line 64*/

+#define EXTI_EMR3_EM65_Pos         (1U)

+#define EXTI_EMR3_EM65_Msk         (0x1UL << EXTI_EMR3_EM65_Pos)               /*!< 0x00000002 */

+#define EXTI_EMR3_EM65             EXTI_EMR3_EM65_Msk                          /*!< Event Mask on line 65*/

+#define EXTI_EMR3_EM66_Pos         (2U)

+#define EXTI_EMR3_EM66_Msk         (0x1UL << EXTI_EMR3_EM66_Pos)               /*!< 0x00000004 */

+#define EXTI_EMR3_EM66             EXTI_EMR3_EM66_Msk                          /*!< Event Mask on line 66*/

+#define EXTI_EMR3_EM67_Pos         (3U)

+#define EXTI_EMR3_EM67_Msk         (0x1UL << EXTI_EMR3_EM67_Pos)               /*!< 0x00000008 */

+#define EXTI_EMR3_EM67             EXTI_EMR3_EM67_Msk                          /*!< Event Mask on line 67*/

+#define EXTI_EMR3_EM68_Pos         (4U)

+#define EXTI_EMR3_EM68_Msk         (0x1UL << EXTI_EMR3_EM68_Pos)               /*!< 0x00000010 */

+#define EXTI_EMR3_EM68             EXTI_EMR3_EM68_Msk                          /*!< Event Mask on line 68*/

+#define EXTI_EMR3_EM69_Pos         (5U)

+#define EXTI_EMR3_EM69_Msk         (0x1UL << EXTI_EMR3_EM69_Pos)               /*!< 0x00000020 */

+#define EXTI_EMR3_EM69             EXTI_EMR3_EM69_Msk                          /*!< Event Mask on line 69*/

+#define EXTI_EMR3_EM70_Pos         (6U)

+#define EXTI_EMR3_EM70_Msk         (0x1UL << EXTI_EMR3_EM70_Pos)               /*!< 0x00000040 */

+#define EXTI_EMR3_EM70             EXTI_EMR3_EM70_Msk                          /*!< Event Mask on line 70*/

+#define EXTI_EMR3_EM71_Pos         (7U)

+#define EXTI_EMR3_EM71_Msk         (0x1UL << EXTI_EMR3_EM71_Pos)               /*!< 0x00000080 */

+#define EXTI_EMR3_EM71             EXTI_EMR3_EM71_Msk                          /*!< Event Mask on line 71*/

+#define EXTI_EMR3_EM72_Pos         (8U)

+#define EXTI_EMR3_EM72_Msk         (0x1UL << EXTI_EMR3_EM72_Pos)               /*!< 0x00000100 */

+#define EXTI_EMR3_EM72             EXTI_EMR3_EM72_Msk                          /*!< Event Mask on line 72*/

+#define EXTI_EMR3_EM73_Pos         (9U)

+#define EXTI_EMR3_EM73_Msk         (0x1UL << EXTI_EMR3_EM73_Pos)               /*!< 0x00000200 */

+#define EXTI_EMR3_EM73             EXTI_EMR3_EM73_Msk                          /*!< Event Mask on line 73*/

+#define EXTI_EMR3_EM74_Pos         (10U)

+#define EXTI_EMR3_EM74_Msk         (0x1UL << EXTI_EMR3_EM74_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR3_EM74             EXTI_EMR3_EM74_Msk                          /*!< Event Mask on line 74 */

+#define EXTI_EMR3_EM77_Pos         (13U)

+#define EXTI_EMR3_EM77_Msk         (0x1UL << EXTI_EMR3_EM77_Pos)               /*!< 0x00002000 */

+#define EXTI_EMR3_EM77             EXTI_EMR3_EM77_Msk                          /*!< Event Mask on line 77 */

+#define EXTI_EMR3_EM80_Pos         (16U)

+#define EXTI_EMR3_EM80_Msk         (0x1UL << EXTI_EMR3_EM80_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR3_EM80             EXTI_EMR3_EM80_Msk                          /*!< Event Mask on line 80 */

+#define EXTI_EMR3_EM81_Pos         (17U)

+#define EXTI_EMR3_EM81_Msk         (0x1UL << EXTI_EMR3_EM81_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR3_EM81             EXTI_EMR3_EM81_Msk                          /*!< Event Mask on line 81 */

+#define EXTI_EMR3_EM82_Pos         (18U)

+#define EXTI_EMR3_EM82_Msk         (0x1UL << EXTI_EMR3_EM82_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR3_EM82             EXTI_EMR3_EM82_Msk                          /*!< Event Mask on line 82 */

+#define EXTI_EMR3_EM85_Pos         (21U)

+#define EXTI_EMR3_EM85_Msk         (0x1UL << EXTI_EMR3_EM85_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR3_EM85             EXTI_EMR3_EM85_Msk                          /*!< Event Mask on line 85 */

+#define EXTI_EMR3_EM87_Pos         (23U)

+#define EXTI_EMR3_EM87_Msk         (0x1UL << EXTI_EMR3_EM87_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR3_EM87             EXTI_EMR3_EM87_Msk                          /*!< Event Mask on line 87 */

+

+#define EXTI_EMR3_EM88_Pos         (24U)

+#define EXTI_EMR3_EM88_Msk         (0x1UL << EXTI_EMR3_EM88_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR3_EM88             EXTI_EMR3_EM88_Msk                          /*!< Event Mask on line 88 */

+

+/*******************  Bit definition for EXTI_PR3 register  ********************/

+#define EXTI_PR3_PR_Pos            (18U)

+#define EXTI_PR3_PR_Msk            (0x9UL << EXTI_PR3_PR_Pos)                  /*!< 0x00240000 */

+#define EXTI_PR3_PR                EXTI_PR3_PR_Msk                             /*!< Pending bit             */

+#define EXTI_PR3_PR82_Pos          (18U)

+#define EXTI_PR3_PR82_Msk          (0x1UL << EXTI_PR3_PR82_Pos)                /*!< 0x00040000 */

+#define EXTI_PR3_PR82              EXTI_PR3_PR82_Msk                           /*!< Pending bit for line 82 */

+#define EXTI_PR3_PR85_Pos          (21U)

+#define EXTI_PR3_PR85_Msk          (0x1UL << EXTI_PR3_PR85_Pos)                /*!< 0x00200000 */

+#define EXTI_PR3_PR85              EXTI_PR3_PR85_Msk                           /*!< Pending bit for line 85 */

+/******************************************************************************/

+/*                                                                            */

+/*                                    FLASH                                   */

+/*                                                                            */

+/******************************************************************************/

+/*

+* @brief FLASH Global Defines

+*/

+#define FLASH_SECTOR_TOTAL                   128U                  /* 128 sectors */

+#define FLASH_SIZE                           0x200000UL            /* 2 MB   */

+#define FLASH_BANK_SIZE                      (FLASH_SIZE >> 1)     /* 1 MB   */

+#define FLASH_SECTOR_SIZE                    0x00002000UL          /* 8 KB   */

+#define FLASH_LATENCY_DEFAULT                FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycles */

+#define FLASH_NB_32BITWORD_IN_FLASHWORD      4U                    /* 128 bits */

+#define DUAL_BANK                                                  /* Dual-bank Flash */

+

+/*******************  Bits definition for FLASH_ACR register  **********************/

+#define FLASH_ACR_LATENCY_Pos                (0U)

+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */

+#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */

+#define FLASH_ACR_LATENCY_0WS                (0x00000000UL)

+#define FLASH_ACR_LATENCY_1WS                (0x00000001UL)

+#define FLASH_ACR_LATENCY_2WS                (0x00000002UL)

+#define FLASH_ACR_LATENCY_3WS                (0x00000003UL)

+#define FLASH_ACR_LATENCY_4WS                (0x00000004UL)

+#define FLASH_ACR_LATENCY_5WS                (0x00000005UL)

+#define FLASH_ACR_LATENCY_6WS                (0x00000006UL)

+#define FLASH_ACR_LATENCY_7WS                (0x00000007UL)

+#define FLASH_ACR_LATENCY_8WS                (0x00000008UL)

+#define FLASH_ACR_LATENCY_9WS                (0x00000009UL)

+#define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)

+#define FLASH_ACR_LATENCY_11WS               (0x0000000BUL)

+#define FLASH_ACR_LATENCY_12WS               (0x0000000CUL)

+#define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)

+#define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)

+#define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)

+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)

+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */

+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */

+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */

+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */

+

+/*******************  Bits definition for FLASH_CR register  ***********************/

+#define FLASH_CR_LOCK_Pos                    (0U)

+#define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */

+#define FLASH_CR_LOCK                        FLASH_CR_LOCK_Msk                 /*!< Configuration lock bit */

+#define FLASH_CR_PG_Pos                      (1U)

+#define FLASH_CR_PG_Msk                      (0x1UL << FLASH_CR_PG_Pos)        /*!< 0x00000002 */

+#define FLASH_CR_PG                          FLASH_CR_PG_Msk                   /*!< Internal buffer control bit */

+#define FLASH_CR_SER_Pos                     (2U)

+#define FLASH_CR_SER_Msk                     (0x1UL << FLASH_CR_SER_Pos)       /*!< 0x00000004 */

+#define FLASH_CR_SER                         FLASH_CR_SER_Msk                  /*!< Sector erase request */

+#define FLASH_CR_BER_Pos                     (3U)

+#define FLASH_CR_BER_Msk                     (0x1UL << FLASH_CR_BER_Pos)       /*!< 0x00000008 */

+#define FLASH_CR_BER                         FLASH_CR_BER_Msk                  /*!< Bank erase request */

+#define FLASH_CR_FW_Pos                      (4U)

+#define FLASH_CR_FW_Msk                      (0x1UL << FLASH_CR_FW_Pos)        /*!< 0x00000010 */

+#define FLASH_CR_FW                          FLASH_CR_FW_Msk                   /*!< Write forcing control bit */

+#define FLASH_CR_START_Pos                   (5U)

+#define FLASH_CR_START_Msk                   (0x1UL << FLASH_CR_START_Pos)     /*!< 0x00000020 */

+#define FLASH_CR_START                       FLASH_CR_START_Msk                /*!< Erase start control bit */

+#define FLASH_CR_SNB_Pos                     (6U)

+#define FLASH_CR_SNB_Msk                     (0x7FUL << FLASH_CR_SNB_Pos)      /*!< 0x00001FC0 */

+#define FLASH_CR_SNB                         FLASH_CR_SNB_Msk                  /*!< Sector erase selection number */

+#define FLASH_CR_SNB_0                       (0x01UL << FLASH_CR_SNB_Pos)      /*!< 0x00000040 */

+#define FLASH_CR_SNB_1                       (0x02UL << FLASH_CR_SNB_Pos)      /*!< 0x00000080 */

+#define FLASH_CR_SNB_2                       (0x04UL << FLASH_CR_SNB_Pos)      /*!< 0x00000100 */

+#define FLASH_CR_SNB_3                       (0x08UL << FLASH_CR_SNB_Pos)      /*!< 0x00000200 */

+#define FLASH_CR_SNB_4                       (0x10UL << FLASH_CR_SNB_Pos)      /*!< 0x00000400 */

+#define FLASH_CR_SNB_5                       (0x20UL << FLASH_CR_SNB_Pos)      /*!< 0x00000800 */

+#define FLASH_CR_SNB_6                       (0x40UL << FLASH_CR_SNB_Pos)      /*!< 0x00001000 */

+#define FLASH_CR_CRC_EN_Pos                  (15U)

+#define FLASH_CR_CRC_EN_Msk                  (0x1UL << FLASH_CR_CRC_EN_Pos)    /*!< 0x00008000 */

+#define FLASH_CR_CRC_EN                      FLASH_CR_CRC_EN_Msk               /*!< CRC control bit */

+#define FLASH_CR_EOPIE_Pos                   (16U)

+#define FLASH_CR_EOPIE_Msk                   (0x1UL << FLASH_CR_EOPIE_Pos)     /*!< 0x00010000 */

+#define FLASH_CR_EOPIE                       FLASH_CR_EOPIE_Msk                /*!< End-of-program interrupt control bit */

+#define FLASH_CR_WRPERRIE_Pos                (17U)

+#define FLASH_CR_WRPERRIE_Msk                (0x1UL << FLASH_CR_WRPERRIE_Pos)  /*!< 0x00020000 */

+#define FLASH_CR_WRPERRIE                    FLASH_CR_WRPERRIE_Msk             /*!< Write protection error interrupt enable bit */

+#define FLASH_CR_PGSERRIE_Pos                (18U)

+#define FLASH_CR_PGSERRIE_Msk                (0x1UL << FLASH_CR_PGSERRIE_Pos)  /*!< 0x00040000 */

+#define FLASH_CR_PGSERRIE                    FLASH_CR_PGSERRIE_Msk             /*!< Programming sequence error interrupt enable bit */

+#define FLASH_CR_STRBERRIE_Pos               (19U)

+#define FLASH_CR_STRBERRIE_Msk               (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */

+#define FLASH_CR_STRBERRIE                   FLASH_CR_STRBERRIE_Msk            /*!< Strobe error interrupt enable bit */

+#define FLASH_CR_INCERRIE_Pos                (21U)

+#define FLASH_CR_INCERRIE_Msk                (0x1UL << FLASH_CR_INCERRIE_Pos)  /*!< 0x00200000 */

+#define FLASH_CR_INCERRIE                    FLASH_CR_INCERRIE_Msk             /*!< Inconsistency error interrupt enable bit */

+#define FLASH_CR_RDPERRIE_Pos                (23U)

+#define FLASH_CR_RDPERRIE_Msk                (0x1UL << FLASH_CR_RDPERRIE_Pos)  /*!< 0x00800000 */

+#define FLASH_CR_RDPERRIE                    FLASH_CR_RDPERRIE_Msk             /*!< Read protection error interrupt enable bit */

+#define FLASH_CR_RDSERRIE_Pos                (24U)

+#define FLASH_CR_RDSERRIE_Msk                (0x1UL << FLASH_CR_RDSERRIE_Pos)  /*!< 0x01000000 */

+#define FLASH_CR_RDSERRIE                    FLASH_CR_RDSERRIE_Msk             /*!< Secure error interrupt enable bit */

+#define FLASH_CR_SNECCERRIE_Pos              (25U)

+#define FLASH_CR_SNECCERRIE_Msk              (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */

+#define FLASH_CR_SNECCERRIE                  FLASH_CR_SNECCERRIE_Msk            /*!< ECC single correction error interrupt enable bit */

+#define FLASH_CR_DBECCERRIE_Pos              (26U)

+#define FLASH_CR_DBECCERRIE_Msk              (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */

+#define FLASH_CR_DBECCERRIE                  FLASH_CR_DBECCERRIE_Msk            /*!< ECC double detection error interrupt enable bit */

+#define FLASH_CR_CRCENDIE_Pos                (27U)

+#define FLASH_CR_CRCENDIE_Msk                (0x1UL << FLASH_CR_CRCENDIE_Pos)  /*!< 0x08000000 */

+#define FLASH_CR_CRCENDIE                    FLASH_CR_CRCENDIE_Msk             /*!< CRC end of calculation interrupt enable bit */

+#define FLASH_CR_CRCRDERRIE_Pos              (28U)

+#define FLASH_CR_CRCRDERRIE_Msk              (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */

+#define FLASH_CR_CRCRDERRIE                  FLASH_CR_CRCRDERRIE_Msk            /*!< CRC read error interrupt enable bit */

+

+/*******************  Bits definition for FLASH_SR register  ***********************/

+#define FLASH_SR_BSY_Pos                     (0U)

+#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)       /*!< 0x00000001 */

+#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy flag */

+#define FLASH_SR_WBNE_Pos                    (1U)

+#define FLASH_SR_WBNE_Msk                    (0x1UL << FLASH_SR_WBNE_Pos)      /*!< 0x00000002 */

+#define FLASH_SR_WBNE                        FLASH_SR_WBNE_Msk                 /*!< Write buffer not empty flag */

+#define FLASH_SR_QW_Pos                      (2U)

+#define FLASH_SR_QW_Msk                      (0x1UL << FLASH_SR_QW_Pos)        /*!< 0x00000004 */

+#define FLASH_SR_QW                          FLASH_SR_QW_Msk                   /*!< Wait queue flag */

+#define FLASH_SR_CRC_BUSY_Pos                (3U)

+#define FLASH_SR_CRC_BUSY_Msk                (0x1UL << FLASH_SR_CRC_BUSY_Pos)  /*!< 0x00000008 */

+#define FLASH_SR_CRC_BUSY                    FLASH_SR_CRC_BUSY_Msk             /*!< CRC busy flag */

+#define FLASH_SR_EOP_Pos                     (16U)

+#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)       /*!< 0x00010000 */

+#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End-of-program flag */

+#define FLASH_SR_WRPERR_Pos                  (17U)

+#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)    /*!< 0x00020000 */

+#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protection error flag */

+#define FLASH_SR_PGSERR_Pos                  (18U)

+#define FLASH_SR_PGSERR_Msk                  (0x1UL << FLASH_SR_PGSERR_Pos)    /*!< 0x00040000 */

+#define FLASH_SR_PGSERR                      FLASH_SR_PGSERR_Msk               /*!< Programming sequence error flag */

+#define FLASH_SR_STRBERR_Pos                 (19U)

+#define FLASH_SR_STRBERR_Msk                 (0x1UL << FLASH_SR_STRBERR_Pos)   /*!< 0x00080000 */

+#define FLASH_SR_STRBERR                     FLASH_SR_STRBERR_Msk              /*!< Strobe error flag */

+#define FLASH_SR_INCERR_Pos                  (21U)

+#define FLASH_SR_INCERR_Msk                  (0x1UL << FLASH_SR_INCERR_Pos)    /*!< 0x00200000 */

+#define FLASH_SR_INCERR                      FLASH_SR_INCERR_Msk               /*!< Inconsistency error flag */

+#define FLASH_SR_RDPERR_Pos                  (23U)

+#define FLASH_SR_RDPERR_Msk                  (0x1UL << FLASH_SR_RDPERR_Pos)    /*!< 0x00800000 */

+#define FLASH_SR_RDPERR                      FLASH_SR_RDPERR_Msk               /*!< Read protection error flag */

+#define FLASH_SR_RDSERR_Pos                  (24U)

+#define FLASH_SR_RDSERR_Msk                  (0x1UL << FLASH_SR_RDSERR_Pos)    /*!< 0x01000000 */

+#define FLASH_SR_RDSERR                      FLASH_SR_RDSERR_Msk               /*!< Secure error flag */

+#define FLASH_SR_SNECCERR_Pos                (25U)

+#define FLASH_SR_SNECCERR_Msk                (0x1UL << FLASH_SR_SNECCERR_Pos)  /*!< 0x02000000 */

+#define FLASH_SR_SNECCERR                    FLASH_SR_SNECCERR_Msk             /*!< Single correction error flag */

+#define FLASH_SR_DBECCERR_Pos                (26U)

+#define FLASH_SR_DBECCERR_Msk                (0x1UL << FLASH_SR_DBECCERR_Pos)  /*!< 0x04000000 */

+#define FLASH_SR_DBECCERR                    FLASH_SR_DBECCERR_Msk             /*!< ECC double detection error flag */

+#define FLASH_SR_CRCEND_Pos                  (27U)

+#define FLASH_SR_CRCEND_Msk                  (0x1UL << FLASH_SR_CRCEND_Pos)    /*!< 0x08000000 */

+#define FLASH_SR_CRCEND                      FLASH_SR_CRCEND_Msk               /*!< CRC end of calculation flag */

+#define FLASH_SR_CRCRDERR_Pos                (28U)

+#define FLASH_SR_CRCRDERR_Msk                (0x1UL << FLASH_SR_CRCRDERR_Pos)  /*!< 0x10000000 */

+#define FLASH_SR_CRCRDERR                    FLASH_SR_CRCRDERR_Msk             /*!< CRC read error flag */

+

+/*******************  Bits definition for FLASH_CCR register  *******************/

+#define FLASH_CCR_CLR_EOP_Pos                (16U)

+#define FLASH_CCR_CLR_EOP_Msk                (0x1UL << FLASH_CCR_CLR_EOP_Pos)  /*!< 0x00010000 */

+#define FLASH_CCR_CLR_EOP                    FLASH_CCR_CLR_EOP_Msk             /*!< EOP flag clear bit */

+#define FLASH_CCR_CLR_WRPERR_Pos             (17U)

+#define FLASH_CCR_CLR_WRPERR_Msk             (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */

+#define FLASH_CCR_CLR_WRPERR                 FLASH_CCR_CLR_WRPERR_Msk            /*!< WRPERR flag clear bit */

+#define FLASH_CCR_CLR_PGSERR_Pos             (18U)

+#define FLASH_CCR_CLR_PGSERR_Msk             (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */

+#define FLASH_CCR_CLR_PGSERR                 FLASH_CCR_CLR_PGSERR_Msk            /*!< PGSERR flag clear bit */

+#define FLASH_CCR_CLR_STRBERR_Pos            (19U)

+#define FLASH_CCR_CLR_STRBERR_Msk            (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */

+#define FLASH_CCR_CLR_STRBERR                FLASH_CCR_CLR_STRBERR_Msk            /*!< STRBERR flag clear bit */

+#define FLASH_CCR_CLR_INCERR_Pos             (21U)

+#define FLASH_CCR_CLR_INCERR_Msk             (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */

+#define FLASH_CCR_CLR_INCERR                 FLASH_CCR_CLR_INCERR_Msk            /*!< INCERR flag clear bit */

+#define FLASH_CCR_CLR_RDPERR_Pos             (23U)

+#define FLASH_CCR_CLR_RDPERR_Msk             (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */

+#define FLASH_CCR_CLR_RDPERR                 FLASH_CCR_CLR_RDPERR_Msk            /*!< RDPERR flag clear bit */

+#define FLASH_CCR_CLR_RDSERR_Pos             (24U)

+#define FLASH_CCR_CLR_RDSERR_Msk             (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */

+#define FLASH_CCR_CLR_RDSERR                 FLASH_CCR_CLR_RDSERR_Msk            /*!< RDSERR flag clear bit */

+#define FLASH_CCR_CLR_SNECCERR_Pos           (25U)

+#define FLASH_CCR_CLR_SNECCERR_Msk           (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */

+#define FLASH_CCR_CLR_SNECCERR               FLASH_CCR_CLR_SNECCERR_Msk            /*!< SNECCERR flag clear bit */

+#define FLASH_CCR_CLR_DBECCERR_Pos           (26U)

+#define FLASH_CCR_CLR_DBECCERR_Msk           (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */

+#define FLASH_CCR_CLR_DBECCERR               FLASH_CCR_CLR_DBECCERR_Msk            /*!< DBECCERR flag clear bit */

+#define FLASH_CCR_CLR_CRCEND_Pos             (27U)

+#define FLASH_CCR_CLR_CRCEND_Msk             (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */

+#define FLASH_CCR_CLR_CRCEND                 FLASH_CCR_CLR_CRCEND_Msk            /*!< CRCEND flag clear bit */

+#define FLASH_CCR_CLR_CRCRDERR_Pos           (28U)

+#define FLASH_CCR_CLR_CRCRDERR_Msk           (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */

+#define FLASH_CCR_CLR_CRCRDERR               FLASH_CCR_CLR_CRCRDERR_Msk            /*!< CRCRDERR flag clear bit */

+

+/*******************  Bits definition for FLASH_OPTCR register  *******************/

+#define FLASH_OPTCR_OPTLOCK_Pos              (0U)

+#define FLASH_OPTCR_OPTLOCK_Msk              (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)  /*!< 0x00000001 */

+#define FLASH_OPTCR_OPTLOCK                  FLASH_OPTCR_OPTLOCK_Msk             /*!< FLASH_OPTCR lock option configuration bit */

+#define FLASH_OPTCR_OPTSTART_Pos             (1U)

+#define FLASH_OPTCR_OPTSTART_Msk             (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */

+#define FLASH_OPTCR_OPTSTART                 FLASH_OPTCR_OPTSTART_Msk            /*!< Option byte start change option configuration bit */

+#define FLASH_OPTCR_MER_Pos                  (4U)

+#define FLASH_OPTCR_MER_Msk                  (0x1UL << FLASH_OPTCR_MER_Pos)      /*!< 0x00000010 */

+#define FLASH_OPTCR_MER                      FLASH_OPTCR_MER_Msk                 /*!< Mass erase request */

+#define FLASH_OPTCR_PG_OTP_Pos               (5U)

+#define FLASH_OPTCR_PG_OTP_Msk               (0x1UL << FLASH_OPTCR_PG_OTP_Pos)   /*!< 0x00000020 */

+#define FLASH_OPTCR_PG_OTP                   FLASH_OPTCR_PG_OTP_Msk              /*!< OTP program control bit */

+#define FLASH_OPTCR_OPTCHANGEERRIE_Pos       (30U)

+#define FLASH_OPTCR_OPTCHANGEERRIE_Msk       (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */

+#define FLASH_OPTCR_OPTCHANGEERRIE           FLASH_OPTCR_OPTCHANGEERRIE_Msk            /*!< Option byte change error interrupt enable bit */

+#define FLASH_OPTCR_SWAP_BANK_Pos            (31U)

+#define FLASH_OPTCR_SWAP_BANK_Msk            (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */

+#define FLASH_OPTCR_SWAP_BANK                FLASH_OPTCR_SWAP_BANK_Msk            /*!< Bank swapping option configuration bit */

+

+/*******************  Bits definition for FLASH_OPTSR register  ***************/

+#define FLASH_OPTSR_OPT_BUSY_Pos             (0U)

+#define FLASH_OPTSR_OPT_BUSY_Msk             (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */

+#define FLASH_OPTSR_OPT_BUSY                 FLASH_OPTSR_OPT_BUSY_Msk            /*!< Option byte change ongoing flag */

+#define FLASH_OPTSR_BOR_LEV_Pos              (2U)

+#define FLASH_OPTSR_BOR_LEV_Msk              (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */

+#define FLASH_OPTSR_BOR_LEV                  FLASH_OPTSR_BOR_LEV_Msk            /*!< Brownout level option status bit */

+#define FLASH_OPTSR_BOR_LEV_0                (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */

+#define FLASH_OPTSR_BOR_LEV_1                (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */

+#define FLASH_OPTSR_IWDG1_SW_Pos             (4U)

+#define FLASH_OPTSR_IWDG1_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */

+#define FLASH_OPTSR_IWDG1_SW                 FLASH_OPTSR_IWDG1_SW_Msk            /*!< IWDG1 control mode option status bit */

+#define FLASH_OPTSR_NRST_STOP_D1_Pos         (6U)

+#define FLASH_OPTSR_NRST_STOP_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */

+#define FLASH_OPTSR_NRST_STOP_D1             FLASH_OPTSR_NRST_STOP_D1_Msk            /*!< D1 domain DStop entry reset option status bit */

+#define FLASH_OPTSR_NRST_STBY_D1_Pos         (7U)

+#define FLASH_OPTSR_NRST_STBY_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */

+#define FLASH_OPTSR_NRST_STBY_D1             FLASH_OPTSR_NRST_STBY_D1_Msk            /*!< D1 domain DStandby entry reset option status bit */

+#define FLASH_OPTSR_RDP_Pos                  (8U)

+#define FLASH_OPTSR_RDP_Msk                  (0xFFUL << FLASH_OPTSR_RDP_Pos)   /*!< 0x0000FF00 */

+#define FLASH_OPTSR_RDP                      FLASH_OPTSR_RDP_Msk               /*!< Readout protection level option status byte */

+#define FLASH_OPTSR_VDDMMC_HSLV_Pos          (16U)

+#define FLASH_OPTSR_VDDMMC_HSLV_Msk          (0x1UL << FLASH_OPTSR_VDDMMC_HSLV_Pos) /*!< 0x00010000 */

+#define FLASH_OPTSR_VDDMMC_HSLV              FLASH_OPTSR_VDDMMC_HSLV_Msk            /*!< VDDMMC I/O high-speed at low-voltage status bit (below 2.5V) */

+#define FLASH_OPTSR_FZ_IWDG_STOP_Pos         (17U)

+#define FLASH_OPTSR_FZ_IWDG_STOP_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */

+#define FLASH_OPTSR_FZ_IWDG_STOP             FLASH_OPTSR_FZ_IWDG_STOP_Msk            /*!< IWDG Stop mode freeze option status bit */

+#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos         (18U)

+#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */

+#define FLASH_OPTSR_FZ_IWDG_SDBY             FLASH_OPTSR_FZ_IWDG_SDBY_Msk            /*!< IWDG Standby mode freeze option status bit */

+#define FLASH_OPTSR_ST_RAM_SIZE_Pos          (19U)

+#define FLASH_OPTSR_ST_RAM_SIZE_Msk          (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */

+#define FLASH_OPTSR_ST_RAM_SIZE              FLASH_OPTSR_ST_RAM_SIZE_Msk            /*!< ST RAM size option status */

+#define FLASH_OPTSR_ST_RAM_SIZE_0            (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */

+#define FLASH_OPTSR_ST_RAM_SIZE_1            (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */

+#define FLASH_OPTSR_SECURITY_Pos             (21U)

+#define FLASH_OPTSR_SECURITY_Msk             (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */

+#define FLASH_OPTSR_SECURITY                 FLASH_OPTSR_SECURITY_Msk            /*!< Security enable option status bit */

+#define FLASH_OPTSR_IO_HSLV_Pos              (29U)

+#define FLASH_OPTSR_IO_HSLV_Msk              (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */

+#define FLASH_OPTSR_IO_HSLV                  FLASH_OPTSR_IO_HSLV_Msk            /*!< I/O high-speed at low-voltage status bit */

+#define FLASH_OPTSR_OPTCHANGEERR_Pos         (30U)

+#define FLASH_OPTSR_OPTCHANGEERR_Msk         (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */

+#define FLASH_OPTSR_OPTCHANGEERR             FLASH_OPTSR_OPTCHANGEERR_Msk            /*!< Option byte change error flag */

+#define FLASH_OPTSR_SWAP_BANK_OPT_Pos        (31U)

+#define FLASH_OPTSR_SWAP_BANK_OPT_Msk        (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */

+#define FLASH_OPTSR_SWAP_BANK_OPT            FLASH_OPTSR_SWAP_BANK_OPT_Msk            /*!< Bank swapping option status bit */

+

+/*******************  Bits definition for FLASH_OPTCCR register  *******************/

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos    (30U)

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk    (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR        FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk            /*!< OPTCHANGEERR reset bit */

+

+/*******************  Bits definition for FLASH_PRAR register  *********************/

+#define FLASH_PRAR_PROT_AREA_START_Pos       (0U)

+#define FLASH_PRAR_PROT_AREA_START_Msk       (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */

+#define FLASH_PRAR_PROT_AREA_START           FLASH_PRAR_PROT_AREA_START_Msk              /*!< PCROP area start status bits */

+#define FLASH_PRAR_PROT_AREA_END_Pos         (16U)

+#define FLASH_PRAR_PROT_AREA_END_Msk         (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */

+#define FLASH_PRAR_PROT_AREA_END             FLASH_PRAR_PROT_AREA_END_Msk              /*!< PCROP area end status bits */

+#define FLASH_PRAR_DMEP_Pos                  (31U)

+#define FLASH_PRAR_DMEP_Msk                  (0x1UL << FLASH_PRAR_DMEP_Pos)    /*!< 0x80000000 */

+#define FLASH_PRAR_DMEP                      FLASH_PRAR_DMEP_Msk               /*!< PCROP protected erase enable option status bit */

+

+/*******************  Bits definition for FLASH_SCAR register  *********************/

+#define FLASH_SCAR_SEC_AREA_START_Pos        (0U)

+#define FLASH_SCAR_SEC_AREA_START_Msk        (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */

+#define FLASH_SCAR_SEC_AREA_START            FLASH_SCAR_SEC_AREA_START_Msk              /*!< Secure-only area start status bits */

+#define FLASH_SCAR_SEC_AREA_END_Pos          (16U)

+#define FLASH_SCAR_SEC_AREA_END_Msk          (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */

+#define FLASH_SCAR_SEC_AREA_END              FLASH_SCAR_SEC_AREA_END_Msk              /*!< Secure-only area end status bits */

+#define FLASH_SCAR_DMES_Pos                  (31U)

+#define FLASH_SCAR_DMES_Msk                  (0x1UL << FLASH_SCAR_DMES_Pos)    /*!< 0x80000000 */

+#define FLASH_SCAR_DMES                      FLASH_SCAR_DMES_Msk               /*!< Secure access protected erase enable option status bit */

+

+/*******************  Bits definition for FLASH_WPSN register  *********************/

+#define FLASH_WPSN_WRPSN_Pos                 (0U)

+#define FLASH_WPSN_WRPSN_Msk                 (0xFFFFFFFFUL << FLASH_WPSN_WRPSN_Pos)  /*!< 0xFFFFFFFF */

+#define FLASH_WPSN_WRPSN                     FLASH_WPSN_WRPSN_Msk              /*!< Sector write protection option status byte */

+

+/*******************  Bits definition for FLASH_BOOT_CUR register  ****************/

+#define FLASH_BOOT_ADD0_Pos                  (0U)

+#define FLASH_BOOT_ADD0_Msk                  (0xFFFFUL << FLASH_BOOT_ADD0_Pos) /*!< 0x0000FFFF */

+#define FLASH_BOOT_ADD0                      FLASH_BOOT_ADD0_Msk               /*!< Arm Cortex-M7 boot address 0 */

+#define FLASH_BOOT_ADD1_Pos                  (16U)

+#define FLASH_BOOT_ADD1_Msk                  (0xFFFFUL << FLASH_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */

+#define FLASH_BOOT_ADD1                      FLASH_BOOT_ADD1_Msk               /*!< Arm Cortex-M7 boot address 1 */

+

+

+/*******************  Bits definition for FLASH_CRCCR register  ********************/

+#define FLASH_CRCCR_CRC_SECT_Pos             (0U)

+#define FLASH_CRCCR_CRC_SECT_Msk             (0x3FUL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x0000003F */

+#define FLASH_CRCCR_CRC_SECT                 FLASH_CRCCR_CRC_SECT_Msk             /*!< CRC sector number */

+#define FLASH_CRCCR_CRC_BY_SECT_Pos          (8U)

+#define FLASH_CRCCR_CRC_BY_SECT_Msk          (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */

+#define FLASH_CRCCR_CRC_BY_SECT              FLASH_CRCCR_CRC_BY_SECT_Msk            /*!< CRC sector mode select bit */

+#define FLASH_CRCCR_ADD_SECT_Pos             (9U)

+#define FLASH_CRCCR_ADD_SECT_Msk             (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */

+#define FLASH_CRCCR_ADD_SECT                 FLASH_CRCCR_ADD_SECT_Msk            /*!< CRC sector select bit */

+#define FLASH_CRCCR_CLEAN_SECT_Pos           (10U)

+#define FLASH_CRCCR_CLEAN_SECT_Msk           (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */

+#define FLASH_CRCCR_CLEAN_SECT               FLASH_CRCCR_CLEAN_SECT_Msk            /*!< CRC sector list clear bit */

+#define FLASH_CRCCR_START_CRC_Pos            (16U)

+#define FLASH_CRCCR_START_CRC_Msk            (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */

+#define FLASH_CRCCR_START_CRC                FLASH_CRCCR_START_CRC_Msk            /*!< CRC start bit */

+#define FLASH_CRCCR_CLEAN_CRC_Pos            (17U)

+#define FLASH_CRCCR_CLEAN_CRC_Msk            (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */

+#define FLASH_CRCCR_CLEAN_CRC                FLASH_CRCCR_CLEAN_CRC_Msk            /*!< CRC clear bit */

+#define FLASH_CRCCR_CRC_BURST_Pos            (20U)

+#define FLASH_CRCCR_CRC_BURST_Msk            (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */

+#define FLASH_CRCCR_CRC_BURST                FLASH_CRCCR_CRC_BURST_Msk            /*!< CRC burst size */

+#define FLASH_CRCCR_CRC_BURST_0              (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */

+#define FLASH_CRCCR_CRC_BURST_1              (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */

+#define FLASH_CRCCR_ALL_BANK_Pos             (22U)

+#define FLASH_CRCCR_ALL_BANK_Msk             (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */

+#define FLASH_CRCCR_ALL_BANK                 FLASH_CRCCR_ALL_BANK_Msk            /*!< CRC select bit */

+

+/*******************  Bits definition for FLASH_CRCSADD register  ****************/

+#define FLASH_CRCSADD_CRC_START_ADDR_Pos     (0U)

+#define FLASH_CRCSADD_CRC_START_ADDR_Msk     (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCSADD_CRC_START_ADDR         FLASH_CRCSADD_CRC_START_ADDR_Msk                   /*!< CRC start address */

+

+/*******************  Bits definition for FLASH_CRCEADD register  ****************/

+#define FLASH_CRCEADD_CRC_END_ADDR_Pos       (0U)

+#define FLASH_CRCEADD_CRC_END_ADDR_Msk       (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCEADD_CRC_END_ADDR           FLASH_CRCEADD_CRC_END_ADDR_Msk                   /*!< CRC end address */

+

+/*******************  Bits definition for FLASH_CRCDATA register  ***************/

+#define FLASH_CRCDATA_CRC_DATA_Pos           (0U)

+#define FLASH_CRCDATA_CRC_DATA_Msk           (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCDATA_CRC_DATA               FLASH_CRCDATA_CRC_DATA_Msk                   /*!< CRC result */

+

+/*******************  Bits definition for FLASH_ECC_FA register  *******************/

+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos       (0U)

+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk       (0xFFFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x0000FFFF */

+#define FLASH_ECC_FA_FAIL_ECC_ADDR           FLASH_ECC_FA_FAIL_ECC_ADDR_Msk               /*!< ECC error address */

+#define FLASH_ECC_FA_OTP_FAIL_ECC_Pos        (31U)

+#define FLASH_ECC_FA_OTP_FAIL_ECC_Msk        (0x1UL << FLASH_ECC_FA_OTP_FAIL_ECC_Pos) /*!< 0x80000000 */

+#define FLASH_ECC_FA_OTP_FAIL_ECC            FLASH_ECC_FA_OTP_FAIL_ECC_Msk            /*!< OTP ECC error bit */

+

+/*******************  Bits definition for FLASH_OTPBL register  *******************/

+#define FLASH_OTPBL_LOCKBL_Pos               (0U)

+#define FLASH_OTPBL_LOCKBL_Msk               (0xFFFFUL << FLASH_OTPBL_LOCKBL_Pos) /*!< 0x0000FFFF */

+#define FLASH_OTPBL_LOCKBL                   FLASH_OTPBL_LOCKBL_Msk               /*!< OTP Block Lock */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          Flexible Memory Controller                        */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for FMC_BCR1 register  *******************/

+#define FMC_BCR1_CCLKEN_Pos        (20U)

+#define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */

+#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continous clock enable     */

+#define FMC_BCR1_WFDIS_Pos         (21U)

+#define FMC_BCR1_WFDIS_Msk         (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */

+#define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */

+

+#define FMC_BCR1_BMAP_Pos          (24U)

+#define FMC_BCR1_BMAP_Msk          (0x3UL << FMC_BCR1_BMAP_Pos)                /*!< 0x03000000 */

+#define FMC_BCR1_BMAP              FMC_BCR1_BMAP_Msk                           /*!<BMAP[1:0] FMC bank mapping */

+#define FMC_BCR1_BMAP_0            (0x1UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x01000000 */

+#define FMC_BCR1_BMAP_1            (0x2UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x02000000 */

+

+#define FMC_BCR1_FMCEN_Pos         (31U)

+#define FMC_BCR1_FMCEN_Msk         (0x1UL << FMC_BCR1_FMCEN_Pos)               /*!< 0x80000000 */

+#define FMC_BCR1_FMCEN             FMC_BCR1_FMCEN_Msk                          /*!<FMC controller Enable */

+/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/

+#define FMC_BCRx_MBKEN_Pos         (0U)

+#define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */

+#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */

+#define FMC_BCRx_MUXEN_Pos         (1U)

+#define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */

+#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */

+

+#define FMC_BCRx_MTYP_Pos          (2U)

+#define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */

+#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */

+#define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000004 */

+#define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000008 */

+

+#define FMC_BCRx_MWID_Pos          (4U)

+#define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */

+#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */

+#define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000010 */

+#define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000020 */

+

+#define FMC_BCRx_FACCEN_Pos        (6U)

+#define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */

+#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */

+#define FMC_BCRx_BURSTEN_Pos       (8U)

+#define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */

+#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */

+#define FMC_BCRx_WAITPOL_Pos       (9U)

+#define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */

+#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */

+#define FMC_BCRx_WAITCFG_Pos       (11U)

+#define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */

+#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */

+#define FMC_BCRx_WREN_Pos          (12U)

+#define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */

+#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */

+#define FMC_BCRx_WAITEN_Pos        (13U)

+#define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */

+#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */

+#define FMC_BCRx_EXTMOD_Pos        (14U)

+#define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */

+#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */

+#define FMC_BCRx_ASYNCWAIT_Pos     (15U)

+#define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */

+#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */

+

+#define FMC_BCRx_CPSIZE_Pos        (16U)

+#define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */

+#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<PSIZE[2:0] bits CRAM Page Size */

+#define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00010000 */

+#define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00020000 */

+#define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00040000 */

+

+#define FMC_BCRx_CBURSTRW_Pos      (19U)

+#define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */

+#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */

+

+/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/

+#define FMC_BTRx_ADDSET_Pos        (0U)

+#define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */

+#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */

+#define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000001 */

+#define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000002 */

+#define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000004 */

+#define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000008 */

+

+#define FMC_BTRx_ADDHLD_Pos        (4U)

+#define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */

+#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */

+#define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000010 */

+#define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000020 */

+#define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000040 */

+#define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000080 */

+

+#define FMC_BTRx_DATAST_Pos        (8U)

+#define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */

+#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */

+#define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000100 */

+#define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000200 */

+#define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000400 */

+#define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000800 */

+#define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00001000 */

+#define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00002000 */

+#define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00004000 */

+#define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00008000 */

+

+#define FMC_BTRx_BUSTURN_Pos       (16U)

+#define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */

+#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */

+#define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00010000 */

+#define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00020000 */

+#define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00040000 */

+#define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00080000 */

+

+#define FMC_BTRx_CLKDIV_Pos        (20U)

+#define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */

+#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */

+#define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00100000 */

+#define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00200000 */

+#define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00400000 */

+#define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00800000 */

+

+#define FMC_BTRx_DATLAT_Pos        (24U)

+#define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */

+#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */

+#define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x01000000 */

+#define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x02000000 */

+#define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x04000000 */

+#define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x08000000 */

+

+#define FMC_BTRx_ACCMOD_Pos        (28U)

+#define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */

+#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */

+#define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x10000000 */

+#define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x20000000 */

+

+/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/

+#define FMC_BWTRx_ADDSET_Pos       (0U)

+#define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */

+#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */

+#define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000001 */

+#define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000002 */

+#define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000004 */

+#define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000008 */

+

+#define FMC_BWTRx_ADDHLD_Pos       (4U)

+#define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */

+#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */

+#define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000010 */

+#define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000020 */

+#define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000040 */

+#define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000080 */

+

+#define FMC_BWTRx_DATAST_Pos       (8U)

+#define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */

+#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */

+#define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000100 */

+#define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000200 */

+#define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000400 */

+#define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000800 */

+#define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00001000 */

+#define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00002000 */

+#define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00004000 */

+#define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00008000 */

+

+#define FMC_BWTRx_BUSTURN_Pos      (16U)

+#define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */

+#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */

+#define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00010000 */

+#define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00020000 */

+#define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00040000 */

+#define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00080000 */

+

+#define FMC_BWTRx_ACCMOD_Pos       (28U)

+#define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */

+#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */

+#define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x10000000 */

+#define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x20000000 */

+

+/******************  Bit definition for FMC_PCR register  *******************/

+#define FMC_PCR_PWAITEN_Pos        (1U)

+#define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */

+#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */

+#define FMC_PCR_PBKEN_Pos          (2U)

+#define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */

+#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */

+

+#define FMC_PCR_PWID_Pos           (4U)

+#define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */

+#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */

+#define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */

+#define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */

+

+#define FMC_PCR_ECCEN_Pos          (6U)

+#define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */

+#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */

+

+#define FMC_PCR_TCLR_Pos           (9U)

+#define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */

+#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */

+#define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */

+#define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */

+#define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */

+#define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */

+

+#define FMC_PCR_TAR_Pos            (13U)

+#define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */

+#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */

+#define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */

+#define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */

+#define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */

+#define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */

+

+#define FMC_PCR_ECCPS_Pos          (17U)

+#define FMC_PCR_ECCPS_Msk          (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */

+#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */

+#define FMC_PCR_ECCPS_0            (0x1UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */

+#define FMC_PCR_ECCPS_1            (0x2UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */

+#define FMC_PCR_ECCPS_2            (0x4UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */

+

+/*******************  Bit definition for FMC_SR register  *******************/

+#define FMC_SR_IRS_Pos             (0U)

+#define FMC_SR_IRS_Msk             (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */

+#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */

+#define FMC_SR_ILS_Pos             (1U)

+#define FMC_SR_ILS_Msk             (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */

+#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */

+#define FMC_SR_IFS_Pos             (2U)

+#define FMC_SR_IFS_Msk             (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */

+#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */

+#define FMC_SR_IREN_Pos            (3U)

+#define FMC_SR_IREN_Msk            (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */

+#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */

+#define FMC_SR_ILEN_Pos            (4U)

+#define FMC_SR_ILEN_Msk            (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */

+#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */

+#define FMC_SR_IFEN_Pos            (5U)

+#define FMC_SR_IFEN_Msk            (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */

+#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */

+#define FMC_SR_FEMPT_Pos           (6U)

+#define FMC_SR_FEMPT_Msk           (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */

+#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */

+

+/******************  Bit definition for FMC_PMEM register  ******************/

+#define FMC_PMEM_MEMSET_Pos       (0U)

+#define FMC_PMEM_MEMSET_Msk       (0xFFUL << FMC_PMEM_MEMSET_Pos)            /*!< 0x000000FF */

+#define FMC_PMEM_MEMSET           FMC_PMEM_MEMSET_Msk                        /*!<MEMSET[7:0] bits (Common memory setup time) */

+#define FMC_PMEM_MEMSET_0         (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */

+#define FMC_PMEM_MEMSET_1         (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */

+#define FMC_PMEM_MEMSET_2         (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */

+#define FMC_PMEM_MEMSET_3         (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */

+#define FMC_PMEM_MEMSET_4         (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */

+#define FMC_PMEM_MEMSET_5         (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */

+#define FMC_PMEM_MEMSET_6         (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */

+#define FMC_PMEM_MEMSET_7         (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */

+

+#define FMC_PMEM_MEMWAIT_Pos      (8U)

+#define FMC_PMEM_MEMWAIT_Msk      (0xFFUL << FMC_PMEM_MEMWAIT_Pos)           /*!< 0x0000FF00 */

+#define FMC_PMEM_MEMWAIT          FMC_PMEM_MEMWAIT_Msk                       /*!<MEMWAIT[7:0] bits (Common memory wait time) */

+#define FMC_PMEM_MEMWAIT_0        (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */

+#define FMC_PMEM_MEMWAIT_1        (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */

+#define FMC_PMEM_MEMWAIT_2        (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */

+#define FMC_PMEM_MEMWAIT_3        (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */

+#define FMC_PMEM_MEMWAIT_4        (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */

+#define FMC_PMEM_MEMWAIT_5        (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */

+#define FMC_PMEM_MEMWAIT_6        (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */

+#define FMC_PMEM_MEMWAIT_7        (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */

+

+#define FMC_PMEM_MEMHOLD_Pos      (16U)

+#define FMC_PMEM_MEMHOLD_Msk      (0xFFUL << FMC_PMEM_MEMHOLD_Pos)           /*!< 0x00FF0000 */

+#define FMC_PMEM_MEMHOLD          FMC_PMEM_MEMHOLD_Msk                       /*!<MEMHOLD[7:0] bits (Common memory hold time) */

+#define FMC_PMEM_MEMHOLD_0        (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */

+#define FMC_PMEM_MEMHOLD_1        (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */

+#define FMC_PMEM_MEMHOLD_2        (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */

+#define FMC_PMEM_MEMHOLD_3        (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */

+#define FMC_PMEM_MEMHOLD_4        (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */

+#define FMC_PMEM_MEMHOLD_5        (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */

+#define FMC_PMEM_MEMHOLD_6        (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */

+#define FMC_PMEM_MEMHOLD_7        (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */

+

+#define FMC_PMEM_MEMHIZ_Pos       (24U)

+#define FMC_PMEM_MEMHIZ_Msk       (0xFFUL << FMC_PMEM_MEMHIZ_Pos)            /*!< 0xFF000000 */

+#define FMC_PMEM_MEMHIZ           FMC_PMEM_MEMHIZ_Msk                        /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */

+#define FMC_PMEM_MEMHIZ_0         (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */

+#define FMC_PMEM_MEMHIZ_1         (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */

+#define FMC_PMEM_MEMHIZ_2         (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */

+#define FMC_PMEM_MEMHIZ_3         (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */

+#define FMC_PMEM_MEMHIZ_4         (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */

+#define FMC_PMEM_MEMHIZ_5         (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */

+#define FMC_PMEM_MEMHIZ_6         (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */

+#define FMC_PMEM_MEMHIZ_7         (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */

+

+/******************  Bit definition for FMC_PATT register  ******************/

+#define FMC_PATT_ATTSET_Pos       (0U)

+#define FMC_PATT_ATTSET_Msk       (0xFFUL << FMC_PATT_ATTSET_Pos)            /*!< 0x000000FF */

+#define FMC_PATT_ATTSET           FMC_PATT_ATTSET_Msk                        /*!<ATTSET[7:0] bits (Attribute memory setup time) */

+#define FMC_PATT_ATTSET_0         (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */

+#define FMC_PATT_ATTSET_1         (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */

+#define FMC_PATT_ATTSET_2         (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */

+#define FMC_PATT_ATTSET_3         (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */

+#define FMC_PATT_ATTSET_4         (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */

+#define FMC_PATT_ATTSET_5         (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */

+#define FMC_PATT_ATTSET_6         (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */

+#define FMC_PATT_ATTSET_7         (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */

+

+#define FMC_PATT_ATTWAIT_Pos      (8U)

+#define FMC_PATT_ATTWAIT_Msk      (0xFFUL << FMC_PATT_ATTWAIT_Pos)           /*!< 0x0000FF00 */

+#define FMC_PATT_ATTWAIT          FMC_PATT_ATTWAIT_Msk                       /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */

+#define FMC_PATT_ATTWAIT_0        (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */

+#define FMC_PATT_ATTWAIT_1        (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */

+#define FMC_PATT_ATTWAIT_2        (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */

+#define FMC_PATT_ATTWAIT_3        (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */

+#define FMC_PATT_ATTWAIT_4        (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */

+#define FMC_PATT_ATTWAIT_5        (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */

+#define FMC_PATT_ATTWAIT_6        (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */

+#define FMC_PATT_ATTWAIT_7        (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */

+

+#define FMC_PATT_ATTHOLD_Pos      (16U)

+#define FMC_PATT_ATTHOLD_Msk      (0xFFUL << FMC_PATT_ATTHOLD_Pos)           /*!< 0x00FF0000 */

+#define FMC_PATT_ATTHOLD          FMC_PATT_ATTHOLD_Msk                       /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */

+#define FMC_PATT_ATTHOLD_0        (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */

+#define FMC_PATT_ATTHOLD_1        (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */

+#define FMC_PATT_ATTHOLD_2        (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */

+#define FMC_PATT_ATTHOLD_3        (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */

+#define FMC_PATT_ATTHOLD_4        (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */

+#define FMC_PATT_ATTHOLD_5        (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */

+#define FMC_PATT_ATTHOLD_6        (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */

+#define FMC_PATT_ATTHOLD_7        (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */

+

+#define FMC_PATT_ATTHIZ_Pos       (24U)

+#define FMC_PATT_ATTHIZ_Msk       (0xFFUL << FMC_PATT_ATTHIZ_Pos)            /*!< 0xFF000000 */

+#define FMC_PATT_ATTHIZ           FMC_PATT_ATTHIZ_Msk                        /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */

+#define FMC_PATT_ATTHIZ_0         (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */

+#define FMC_PATT_ATTHIZ_1         (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */

+#define FMC_PATT_ATTHIZ_2         (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */

+#define FMC_PATT_ATTHIZ_3         (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */

+#define FMC_PATT_ATTHIZ_4         (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */

+#define FMC_PATT_ATTHIZ_5         (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */

+#define FMC_PATT_ATTHIZ_6         (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */

+#define FMC_PATT_ATTHIZ_7         (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */

+

+/******************  Bit definition for FMC_ECCR3 register  ******************/

+#define FMC_ECCR3_ECC3_Pos         (0U)

+#define FMC_ECCR3_ECC3_Msk         (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)        /*!< 0xFFFFFFFF */

+#define FMC_ECCR3_ECC3             FMC_ECCR3_ECC3_Msk                          /*!<ECC result */

+

+/******************  Bit definition for FMC_SDCRx registers (x=1..4)  *********/

+#define FMC_SDCRx_NC_Pos           (0U)

+#define FMC_SDCRx_NC_Msk           (0x3UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000003 */

+#define FMC_SDCRx_NC               FMC_SDCRx_NC_Msk                            /*!<NC[1:0] bits (Number of column bits) */

+#define FMC_SDCRx_NC_0             (0x1UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000001 */

+#define FMC_SDCRx_NC_1             (0x2UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000002 */

+

+#define FMC_SDCRx_NR_Pos           (2U)

+#define FMC_SDCRx_NR_Msk           (0x3UL << FMC_SDCRx_NR_Pos)                 /*!< 0x0000000C */

+#define FMC_SDCRx_NR               FMC_SDCRx_NR_Msk                            /*!<NR[1:0] bits (Number of row bits) */

+#define FMC_SDCRx_NR_0             (0x1UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000004 */

+#define FMC_SDCRx_NR_1             (0x2UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000008 */

+

+#define FMC_SDCRx_MWID_Pos         (4U)

+#define FMC_SDCRx_MWID_Msk         (0x3UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000030 */

+#define FMC_SDCRx_MWID             FMC_SDCRx_MWID_Msk                          /*!<NR[1:0] bits (Number of row bits) */

+#define FMC_SDCRx_MWID_0           (0x1UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000010 */

+#define FMC_SDCRx_MWID_1           (0x2UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000020 */

+

+#define FMC_SDCRx_NB_Pos           (6U)

+#define FMC_SDCRx_NB_Msk           (0x1UL << FMC_SDCRx_NB_Pos)                 /*!< 0x00000040 */

+#define FMC_SDCRx_NB               FMC_SDCRx_NB_Msk                            /*!<Number of internal bank */

+

+#define FMC_SDCRx_CAS_Pos          (7U)

+#define FMC_SDCRx_CAS_Msk          (0x3UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000180 */

+#define FMC_SDCRx_CAS              FMC_SDCRx_CAS_Msk                           /*!<CAS[1:0] bits (CAS latency) */

+#define FMC_SDCRx_CAS_0            (0x1UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000080 */

+#define FMC_SDCRx_CAS_1            (0x2UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000100 */

+

+#define FMC_SDCRx_WP_Pos           (9U)

+#define FMC_SDCRx_WP_Msk           (0x1UL << FMC_SDCRx_WP_Pos)                 /*!< 0x00000200 */

+#define FMC_SDCRx_WP               FMC_SDCRx_WP_Msk                            /*!<Write protection */

+

+#define FMC_SDCRx_SDCLK_Pos        (10U)

+#define FMC_SDCRx_SDCLK_Msk        (0x3UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000C00 */

+#define FMC_SDCRx_SDCLK            FMC_SDCRx_SDCLK_Msk                         /*!<SDRAM clock configuration */

+#define FMC_SDCRx_SDCLK_0          (0x1UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000400 */

+#define FMC_SDCRx_SDCLK_1          (0x2UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000800 */

+

+#define FMC_SDCRx_RBURST_Pos       (12U)

+#define FMC_SDCRx_RBURST_Msk       (0x1UL << FMC_SDCRx_RBURST_Pos)             /*!< 0x00001000 */

+#define FMC_SDCRx_RBURST           FMC_SDCRx_RBURST_Msk                        /*!<Read burst */

+

+#define FMC_SDCRx_RPIPE_Pos        (13U)

+#define FMC_SDCRx_RPIPE_Msk        (0x3UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00006000 */

+#define FMC_SDCRx_RPIPE            FMC_SDCRx_RPIPE_Msk                         /*!<Write protection */

+#define FMC_SDCRx_RPIPE_0          (0x1UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00002000 */

+#define FMC_SDCRx_RPIPE_1          (0x2UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00004000 */

+

+/******************  Bit definition for FMC_SDTRx(1,2) register  ******************/

+#define FMC_SDTRx_TMRD_Pos         (0U)

+#define FMC_SDTRx_TMRD_Msk         (0xFUL << FMC_SDTRx_TMRD_Pos)               /*!< 0x0000000F */

+#define FMC_SDTRx_TMRD             FMC_SDTRx_TMRD_Msk                          /*!<TMRD[3:0] bits (Load mode register to active) */

+#define FMC_SDTRx_TMRD_0           (0x1UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000001 */

+#define FMC_SDTRx_TMRD_1           (0x2UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000002 */

+#define FMC_SDTRx_TMRD_2           (0x4UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000004 */

+#define FMC_SDTRx_TMRD_3           (0x8UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000008 */

+

+#define FMC_SDTRx_TXSR_Pos         (4U)

+#define FMC_SDTRx_TXSR_Msk         (0xFUL << FMC_SDTRx_TXSR_Pos)               /*!< 0x000000F0 */

+#define FMC_SDTRx_TXSR             FMC_SDTRx_TXSR_Msk                          /*!<TXSR[3:0] bits (Exit self refresh) */

+#define FMC_SDTRx_TXSR_0           (0x1UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000010 */

+#define FMC_SDTRx_TXSR_1           (0x2UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000020 */

+#define FMC_SDTRx_TXSR_2           (0x4UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000040 */

+#define FMC_SDTRx_TXSR_3           (0x8UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000080 */

+

+#define FMC_SDTRx_TRAS_Pos         (8U)

+#define FMC_SDTRx_TRAS_Msk         (0xFUL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000F00 */

+#define FMC_SDTRx_TRAS             FMC_SDTRx_TRAS_Msk                          /*!<TRAS[3:0] bits (Self refresh time) */

+#define FMC_SDTRx_TRAS_0           (0x1UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000100 */

+#define FMC_SDTRx_TRAS_1           (0x2UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000200 */

+#define FMC_SDTRx_TRAS_2           (0x4UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000400 */

+#define FMC_SDTRx_TRAS_3           (0x8UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000800 */

+

+#define FMC_SDTRx_TRC_Pos          (12U)

+#define FMC_SDTRx_TRC_Msk          (0xFUL << FMC_SDTRx_TRC_Pos)                /*!< 0x0000F000 */

+#define FMC_SDTRx_TRC              FMC_SDTRx_TRC_Msk                           /*!<TRC[2:0] bits (Row cycle delay) */

+#define FMC_SDTRx_TRC_0            (0x1UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00001000 */

+#define FMC_SDTRx_TRC_1            (0x2UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00002000 */

+#define FMC_SDTRx_TRC_2            (0x4UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00004000 */

+

+#define FMC_SDTRx_TWR_Pos          (16U)

+#define FMC_SDTRx_TWR_Msk          (0xFUL << FMC_SDTRx_TWR_Pos)                /*!< 0x000F0000 */

+#define FMC_SDTRx_TWR              FMC_SDTRx_TWR_Msk                           /*!<TRC[2:0] bits (Write recovery delay) */

+#define FMC_SDTRx_TWR_0            (0x1UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00010000 */

+#define FMC_SDTRx_TWR_1            (0x2UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00020000 */

+#define FMC_SDTRx_TWR_2            (0x4UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00040000 */

+

+#define FMC_SDTRx_TRP_Pos          (20U)

+#define FMC_SDTRx_TRP_Msk          (0xFUL << FMC_SDTRx_TRP_Pos)                /*!< 0x00F00000 */

+#define FMC_SDTRx_TRP              FMC_SDTRx_TRP_Msk                           /*!<TRP[2:0] bits (Row precharge delay) */

+#define FMC_SDTRx_TRP_0            (0x1UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00100000 */

+#define FMC_SDTRx_TRP_1            (0x2UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00200000 */

+#define FMC_SDTRx_TRP_2            (0x4UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00400000 */

+

+#define FMC_SDTRx_TRCD_Pos         (24U)

+#define FMC_SDTRx_TRCD_Msk         (0xFUL << FMC_SDTRx_TRCD_Pos)               /*!< 0x0F000000 */

+#define FMC_SDTRx_TRCD             FMC_SDTRx_TRCD_Msk                          /*!<TRP[2:0] bits (Row to column delay) */

+#define FMC_SDTRx_TRCD_0           (0x1UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x01000000 */

+#define FMC_SDTRx_TRCD_1           (0x2UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x02000000 */

+#define FMC_SDTRx_TRCD_2           (0x4UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x04000000 */

+

+/******************  Bit definition for FMC_SDCMR register  ******************/

+#define FMC_SDCMR_MODE_Pos         (0U)

+#define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */

+#define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */

+#define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */

+#define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */

+#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */

+

+#define FMC_SDCMR_CTB2_Pos         (3U)

+#define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */

+#define FMC_SDCMR_CTB2             FMC_SDCMR_CTB2_Msk                          /*!<Command target 2 */

+

+#define FMC_SDCMR_CTB1_Pos         (4U)

+#define FMC_SDCMR_CTB1_Msk         (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */

+#define FMC_SDCMR_CTB1             FMC_SDCMR_CTB1_Msk                          /*!<Command target 1 */

+

+#define FMC_SDCMR_NRFS_Pos         (5U)

+#define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */

+#define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!<NRFS[3:0] bits (Number of auto-refresh) */

+#define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000020 */

+#define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000040 */

+#define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000080 */

+#define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000100 */

+

+#define FMC_SDCMR_MRD_Pos          (9U)

+#define FMC_SDCMR_MRD_Msk          (0x1FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */

+#define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!<MRD[12:0] bits (Mode register definition) */

+

+/******************  Bit definition for FMC_SDRTR register  ******************/

+#define FMC_SDRTR_CRE_Pos          (0U)

+#define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */

+#define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!<Clear refresh error flag */

+

+#define FMC_SDRTR_COUNT_Pos        (1U)

+#define FMC_SDRTR_COUNT_Msk        (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */

+#define FMC_SDRTR_COUNT            FMC_SDRTR_COUNT_Msk                         /*!<COUNT[12:0] bits (Refresh timer count) */

+

+#define FMC_SDRTR_REIE_Pos         (14U)

+#define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */

+#define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!<RES interupt enable */

+

+/******************  Bit definition for FMC_SDSR register  ******************/

+#define FMC_SDSR_RE_Pos            (0U)

+#define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */

+#define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!<Refresh error flag */

+

+#define FMC_SDSR_MODES1_Pos        (1U)

+#define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */

+#define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!<MODES1[1:0]bits (Status mode for bank 1) */

+#define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000002 */

+#define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000004 */

+

+#define FMC_SDSR_MODES2_Pos        (3U)

+#define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */

+#define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!<MODES2[1:0]bits (Status mode for bank 2) */

+#define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000008 */

+#define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000010 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                       Graphic MMU (GFXMMU)                                 */

+/*                                                                            */

+/******************************************************************************/

+/****************** Bits definition for GFXMMU_CR register ********************/

+#define GFXMMU_CR_B0OIE_Pos                (0U)

+#define GFXMMU_CR_B0OIE_Msk                (0x1UL << GFXMMU_CR_B0OIE_Pos)       /*!< 0x00000001 */

+#define GFXMMU_CR_B0OIE                    GFXMMU_CR_B0OIE_Msk                 /*!< Buffer 0 overflow interrupt enable */

+#define GFXMMU_CR_B1OIE_Pos                (1U)

+#define GFXMMU_CR_B1OIE_Msk                (0x1UL << GFXMMU_CR_B1OIE_Pos)       /*!< 0x00000002 */

+#define GFXMMU_CR_B1OIE                    GFXMMU_CR_B1OIE_Msk                 /*!< Buffer 1 overflow interrupt enable */

+#define GFXMMU_CR_B2OIE_Pos                (2U)

+#define GFXMMU_CR_B2OIE_Msk                (0x1UL << GFXMMU_CR_B2OIE_Pos)       /*!< 0x00000004 */

+#define GFXMMU_CR_B2OIE                    GFXMMU_CR_B2OIE_Msk                 /*!< Buffer 2 overflow interrupt enable */

+#define GFXMMU_CR_B3OIE_Pos                (3U)

+#define GFXMMU_CR_B3OIE_Msk                (0x1UL << GFXMMU_CR_B3OIE_Pos)       /*!< 0x00000008 */

+#define GFXMMU_CR_B3OIE                    GFXMMU_CR_B3OIE_Msk                 /*!< Buffer 3 overflow interrupt enable */

+#define GFXMMU_CR_AMEIE_Pos                (4U)

+#define GFXMMU_CR_AMEIE_Msk                (0x1UL << GFXMMU_CR_AMEIE_Pos)       /*!< 0x00000010 */

+#define GFXMMU_CR_AMEIE                    GFXMMU_CR_AMEIE_Msk                 /*!< AHB master error interrupt enable */

+#define GFXMMU_CR_192BM_Pos                (6U)

+#define GFXMMU_CR_192BM_Msk                (0x1UL << GFXMMU_CR_192BM_Pos)       /*!< 0x00000040 */

+#define GFXMMU_CR_192BM                    GFXMMU_CR_192BM_Msk                 /*!< 192 block mode */

+#define GFXMMU_CR_CE_Pos                   (7U)

+#define GFXMMU_CR_CE_Msk                   (0x1UL << GFXMMU_CR_CE_Pos)          /*!< 0x00000080 */

+#define GFXMMU_CR_CE                       GFXMMU_CR_CE_Msk                    /*!< Cache Enable */

+#define GFXMMU_CR_CL_Pos                   (8U)

+#define GFXMMU_CR_CL_Msk                   (0x1UL << GFXMMU_CR_CL_Pos)          /*!< 0x00000100 */

+#define GFXMMU_CR_CL                       GFXMMU_CR_CL_Msk                    /*!< Cache Lock */

+#define GFXMMU_CR_CLB_Pos                  (9U)

+#define GFXMMU_CR_CLB_Msk                  (0x3UL << GFXMMU_CR_CLB_Pos)         /*!< 0x00000600 */

+#define GFXMMU_CR_CLB                      GFXMMU_CR_CLB_Msk                   /*!< CLB[1:0]: Cache Lock Buffer */

+#define GFXMMU_CR_CLB_0                    (0x1UL << GFXMMU_CR_CLB_Pos)         /*!< Cache locked on buffer 1 */

+#define GFXMMU_CR_CLB_1                    (0x2UL << GFXMMU_CR_CLB_Pos)         /*!< Cache locked on buffer 2 */

+#define GFXMMU_CR_FC_Pos                   (11U)

+#define GFXMMU_CR_FC_Msk                   (0x1UL << GFXMMU_CR_FC_Pos)          /*!< 0x00000800 */

+#define GFXMMU_CR_FC                       GFXMMU_CR_FC_Msk                    /*!< Force Caching */

+#define GFXMMU_CR_PD_Pos                   (12U)

+#define GFXMMU_CR_PD_Msk                   (0x1UL << GFXMMU_CR_PD_Pos)          /*!< 0x00001000 */

+#define GFXMMU_CR_PD                       GFXMMU_CR_PD_Msk                    /*!< Prefetch Disable */

+#define GFXMMU_CR_OC_Pos                   (16U)

+#define GFXMMU_CR_OC_Msk                   (0x1UL << GFXMMU_CR_OC_Pos)          /*!< 0x00002000 */

+#define GFXMMU_CR_OC                       GFXMMU_CR_OC_Msk                    /*!< Outter Cachability */

+#define GFXMMU_CR_OB_Pos                   (17U)

+#define GFXMMU_CR_OB_Msk                   (0x1UL << GFXMMU_CR_OB_Pos)          /*!< 0x00002000 */

+#define GFXMMU_CR_OB                       GFXMMU_CR_OB_Msk                    /*!< Outter Bufferability */

+

+/****************** Bits definition for GFXMMU_SR register ********************/

+#define GFXMMU_SR_B0OF_Pos                 (0U)

+#define GFXMMU_SR_B0OF_Msk                 (0x1UL << GFXMMU_SR_B0OF_Pos)        /*!< 0x00000001 */

+#define GFXMMU_SR_B0OF                     GFXMMU_SR_B0OF_Msk                  /*!< Buffer 0 overflow flag */

+#define GFXMMU_SR_B1OF_Pos                 (1U)

+#define GFXMMU_SR_B1OF_Msk                 (0x1UL << GFXMMU_SR_B1OF_Pos)        /*!< 0x00000002 */

+#define GFXMMU_SR_B1OF                     GFXMMU_SR_B1OF_Msk                  /*!< Buffer 1 overflow flag */

+#define GFXMMU_SR_B2OF_Pos                 (2U)

+#define GFXMMU_SR_B2OF_Msk                 (0x1UL << GFXMMU_SR_B2OF_Pos)        /*!< 0x00000004 */

+#define GFXMMU_SR_B2OF                     GFXMMU_SR_B2OF_Msk                  /*!< Buffer 2 overflow flag */

+#define GFXMMU_SR_B3OF_Pos                 (3U)

+#define GFXMMU_SR_B3OF_Msk                 (0x1UL << GFXMMU_SR_B3OF_Pos)        /*!< 0x00000008 */

+#define GFXMMU_SR_B3OF                     GFXMMU_SR_B3OF_Msk                  /*!< Buffer 3 overflow flag */

+#define GFXMMU_SR_AMEF_Pos                 (4U)

+#define GFXMMU_SR_AMEF_Msk                 (0x1UL << GFXMMU_SR_AMEF_Pos)        /*!< 0x00000010 */

+#define GFXMMU_SR_AMEF                     GFXMMU_SR_AMEF_Msk                  /*!< AHB master error flag */

+

+/****************** Bits definition for GFXMMU_FCR register *******************/

+#define GFXMMU_FCR_CB0OF_Pos               (0U)

+#define GFXMMU_FCR_CB0OF_Msk               (0x1UL << GFXMMU_FCR_CB0OF_Pos)      /*!< 0x00000001 */

+#define GFXMMU_FCR_CB0OF                   GFXMMU_FCR_CB0OF_Msk                /*!< Clear buffer 0 overflow flag */

+#define GFXMMU_FCR_CB1OF_Pos               (1U)

+#define GFXMMU_FCR_CB1OF_Msk               (0x1UL << GFXMMU_FCR_CB1OF_Pos)      /*!< 0x00000002 */

+#define GFXMMU_FCR_CB1OF                   GFXMMU_FCR_CB1OF_Msk                /*!< Clear buffer 1 overflow flag */

+#define GFXMMU_FCR_CB2OF_Pos               (2U)

+#define GFXMMU_FCR_CB2OF_Msk               (0x1UL << GFXMMU_FCR_CB2OF_Pos)      /*!< 0x00000004 */

+#define GFXMMU_FCR_CB2OF                   GFXMMU_FCR_CB2OF_Msk                /*!< Clear buffer 2 overflow flag */

+#define GFXMMU_FCR_CB3OF_Pos               (3U)

+#define GFXMMU_FCR_CB3OF_Msk               (0x1UL << GFXMMU_FCR_CB3OF_Pos)      /*!< 0x00000008 */

+#define GFXMMU_FCR_CB3OF                   GFXMMU_FCR_CB3OF_Msk                /*!< Clear buffer 3 overflow flag */

+#define GFXMMU_FCR_CAMEF_Pos               (4U)

+#define GFXMMU_FCR_CAMEF_Msk               (0x1UL << GFXMMU_FCR_CAMEF_Pos)      /*!< 0x00000010 */

+#define GFXMMU_FCR_CAMEF                   GFXMMU_FCR_CAMEF_Msk                /*!< Clear AHB master error flag */

+

+/****************** Bits definition for GFXMMU_CCR register *******************/

+#define GFXMMU_CCR_FF_Pos                  (0U)

+#define GFXMMU_CCR_FF_Msk                  (0x1UL << GFXMMU_CCR_FF_Pos)         /*!< 0x00000001 */

+#define GFXMMU_CCR_FF                      GFXMMU_CCR_FF_Msk                   /*!< Clear buffer 0 overflow flag */

+#define GFXMMU_CCR_FI_Pos                  (1U)

+#define GFXMMU_CCR_FI_Msk                  (0x1UL << GFXMMU_CCR_FI_Pos)         /*!< 0x00000002 */

+#define GFXMMU_CCR_FI                      GFXMMU_CCR_FI_Msk                   /*!< Clear buffer 1 overflow flag */

+

+/****************** Bits definition for GFXMMU_DVR register *******************/

+#define GFXMMU_DVR_DV_Pos                  (0U)

+#define GFXMMU_DVR_DV_Msk                  (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos)  /*!< 0xFFFFFFFF */

+#define GFXMMU_DVR_DV                      GFXMMU_DVR_DV_Msk                   /*!< DV[31:0] bits (Default value) */

+

+/****************** Bits definition for GFXMMU_B0CR register ******************/

+#define GFXMMU_B0CR_PBO_Pos                (4U)

+#define GFXMMU_B0CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B0CR_PBO_Pos)   /*!< 0x007FFFF0 */

+#define GFXMMU_B0CR_PBO                    GFXMMU_B0CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */

+#define GFXMMU_B0CR_PBBA_Pos               (23U)

+#define GFXMMU_B0CR_PBBA_Msk               (0x1FFUL << GFXMMU_B0CR_PBBA_Pos)    /*!< 0xFF800000 */

+#define GFXMMU_B0CR_PBBA                   GFXMMU_B0CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */

+

+/****************** Bits definition for GFXMMU_B1CR register ******************/

+#define GFXMMU_B1CR_PBO_Pos                (4U)

+#define GFXMMU_B1CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos)   /*!< 0x007FFFF0 */

+#define GFXMMU_B1CR_PBO                    GFXMMU_B1CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */

+#define GFXMMU_B1CR_PBBA_Pos               (23U)

+#define GFXMMU_B1CR_PBBA_Msk               (0x1FFUL << GFXMMU_B1CR_PBBA_Pos)    /*!< 0xFF800000 */

+#define GFXMMU_B1CR_PBBA                   GFXMMU_B1CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */

+

+/****************** Bits definition for GFXMMU_B2CR register ******************/

+#define GFXMMU_B2CR_PBO_Pos                (4U)

+#define GFXMMU_B2CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B2CR_PBO_Pos)   /*!< 0x007FFFF0 */

+#define GFXMMU_B2CR_PBO                    GFXMMU_B2CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */

+#define GFXMMU_B2CR_PBBA_Pos               (23U)

+#define GFXMMU_B2CR_PBBA_Msk               (0x1FFUL << GFXMMU_B2CR_PBBA_Pos)    /*!< 0xFF800000 */

+#define GFXMMU_B2CR_PBBA                   GFXMMU_B2CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */

+

+/****************** Bits definition for GFXMMU_B3CR register ******************/

+#define GFXMMU_B3CR_PBO_Pos                (4U)

+#define GFXMMU_B3CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B3CR_PBO_Pos)   /*!< 0x007FFFF0 */

+#define GFXMMU_B3CR_PBO                    GFXMMU_B3CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */

+#define GFXMMU_B3CR_PBBA_Pos               (23U)

+#define GFXMMU_B3CR_PBBA_Msk               (0x1FFUL << GFXMMU_B3CR_PBBA_Pos)    /*!< 0xFF800000 */

+#define GFXMMU_B3CR_PBBA                   GFXMMU_B3CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */

+

+/****************** Bits definition for GFXMMU_LUTxL register *****************/

+#define GFXMMU_LUTxL_EN_Pos                (0U)

+#define GFXMMU_LUTxL_EN_Msk                (0x1UL << GFXMMU_LUTxL_EN_Pos)       /*!< 0x00000001 */

+#define GFXMMU_LUTxL_EN                    GFXMMU_LUTxL_EN_Msk                 /*!< Enable */

+#define GFXMMU_LUTxL_FVB_Pos               (8U)

+#define GFXMMU_LUTxL_FVB_Msk               (0xFFUL << GFXMMU_LUTxL_FVB_Pos)     /*!< 0x0000FF00 */

+#define GFXMMU_LUTxL_FVB                   GFXMMU_LUTxL_FVB_Msk                /*!< FVB[7:0] bits (First visible block) */

+#define GFXMMU_LUTxL_LVB_Pos               (16U)

+#define GFXMMU_LUTxL_LVB_Msk               (0xFFUL << GFXMMU_LUTxL_LVB_Pos)     /*!< 0x00FF0000 */

+#define GFXMMU_LUTxL_LVB                   GFXMMU_LUTxL_LVB_Msk                /*!< LVB[7:0] bits (Last visible block) */

+

+/****************** Bits definition for GFXMMU_LUTxH register *****************/

+#define GFXMMU_LUTxH_LO_Pos                (4U)

+#define GFXMMU_LUTxH_LO_Msk                (0x3FFFFUL << GFXMMU_LUTxH_LO_Pos)   /*!< 0x003FFFF0 */

+#define GFXMMU_LUTxH_LO                    GFXMMU_LUTxH_LO_Msk                 /*!< LO[21:4] bits (Line offset) */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            General Purpose I/O                             */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bits definition for GPIO_MODER register  *****************/

+#define GPIO_MODER_MODE0_Pos           (0U)

+#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */

+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk

+#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */

+#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */

+

+#define GPIO_MODER_MODE1_Pos           (2U)

+#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */

+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk

+#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */

+#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */

+

+#define GPIO_MODER_MODE2_Pos           (4U)

+#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */

+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk

+#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */

+#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */

+

+#define GPIO_MODER_MODE3_Pos           (6U)

+#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */

+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk

+#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */

+#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */

+

+#define GPIO_MODER_MODE4_Pos           (8U)

+#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */

+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk

+#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */

+#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */

+

+#define GPIO_MODER_MODE5_Pos           (10U)

+#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */

+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk

+#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */

+#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */

+

+#define GPIO_MODER_MODE6_Pos           (12U)

+#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */

+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk

+#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */

+#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */

+

+#define GPIO_MODER_MODE7_Pos           (14U)

+#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */

+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk

+#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */

+#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */

+

+#define GPIO_MODER_MODE8_Pos           (16U)

+#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */

+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk

+#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */

+#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */

+

+#define GPIO_MODER_MODE9_Pos           (18U)

+#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */

+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk

+#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */

+#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */

+

+#define GPIO_MODER_MODE10_Pos          (20U)

+#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */

+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk

+#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */

+#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */

+

+#define GPIO_MODER_MODE11_Pos          (22U)

+#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */

+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk

+#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */

+#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */

+

+#define GPIO_MODER_MODE12_Pos          (24U)

+#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */

+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk

+#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */

+#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */

+

+#define GPIO_MODER_MODE13_Pos          (26U)

+#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */

+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk

+#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */

+#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */

+

+#define GPIO_MODER_MODE14_Pos          (28U)

+#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */

+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk

+#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */

+#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */

+

+#define GPIO_MODER_MODE15_Pos          (30U)

+#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */

+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk

+#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */

+#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_OTYPER register  ****************/

+#define GPIO_OTYPER_OT0_Pos            (0U)

+#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */

+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk

+#define GPIO_OTYPER_OT1_Pos            (1U)

+#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */

+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk

+#define GPIO_OTYPER_OT2_Pos            (2U)

+#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */

+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk

+#define GPIO_OTYPER_OT3_Pos            (3U)

+#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */

+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk

+#define GPIO_OTYPER_OT4_Pos            (4U)

+#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */

+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk

+#define GPIO_OTYPER_OT5_Pos            (5U)

+#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */

+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk

+#define GPIO_OTYPER_OT6_Pos            (6U)

+#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */

+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk

+#define GPIO_OTYPER_OT7_Pos            (7U)

+#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */

+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk

+#define GPIO_OTYPER_OT8_Pos            (8U)

+#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */

+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk

+#define GPIO_OTYPER_OT9_Pos            (9U)

+#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */

+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk

+#define GPIO_OTYPER_OT10_Pos           (10U)

+#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */

+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk

+#define GPIO_OTYPER_OT11_Pos           (11U)

+#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */

+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk

+#define GPIO_OTYPER_OT12_Pos           (12U)

+#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */

+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk

+#define GPIO_OTYPER_OT13_Pos           (13U)

+#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */

+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk

+#define GPIO_OTYPER_OT14_Pos           (14U)

+#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */

+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk

+#define GPIO_OTYPER_OT15_Pos           (15U)

+#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */

+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk

+

+/******************  Bits definition for GPIO_OSPEEDR register  ***************/

+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)

+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */

+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk

+#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */

+#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */

+

+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)

+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */

+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk

+#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */

+#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */

+

+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)

+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */

+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk

+#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */

+#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */

+

+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)

+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */

+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk

+#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */

+#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */

+

+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)

+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */

+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk

+#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */

+#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */

+

+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)

+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */

+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk

+#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */

+#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */

+

+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)

+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */

+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk

+#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */

+#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */

+

+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)

+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */

+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk

+#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */

+#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */

+

+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)

+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */

+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk

+#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */

+#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */

+

+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)

+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */

+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk

+#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */

+#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */

+

+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)

+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */

+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk

+#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */

+#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */

+

+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)

+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */

+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk

+#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */

+#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */

+

+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)

+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */

+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk

+#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */

+#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */

+

+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)

+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */

+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk

+#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */

+#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */

+

+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)

+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */

+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk

+#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */

+#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */

+

+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)

+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */

+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk

+#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */

+#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_PUPDR register  *****************/

+#define GPIO_PUPDR_PUPD0_Pos           (0U)

+#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */

+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk

+#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */

+#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */

+

+#define GPIO_PUPDR_PUPD1_Pos           (2U)

+#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */

+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk

+#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */

+#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */

+

+#define GPIO_PUPDR_PUPD2_Pos           (4U)

+#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */

+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk

+#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */

+#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */

+

+#define GPIO_PUPDR_PUPD3_Pos           (6U)

+#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */

+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk

+#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */

+#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */

+

+#define GPIO_PUPDR_PUPD4_Pos           (8U)

+#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */

+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk

+#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */

+#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */

+

+#define GPIO_PUPDR_PUPD5_Pos           (10U)

+#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */

+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk

+#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */

+#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */

+

+#define GPIO_PUPDR_PUPD6_Pos           (12U)

+#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */

+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk

+#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */

+#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */

+

+#define GPIO_PUPDR_PUPD7_Pos           (14U)

+#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */

+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk

+#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */

+#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */

+

+#define GPIO_PUPDR_PUPD8_Pos           (16U)

+#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */

+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk

+#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */

+#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */

+

+#define GPIO_PUPDR_PUPD9_Pos           (18U)

+#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */

+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk

+#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */

+#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */

+

+#define GPIO_PUPDR_PUPD10_Pos          (20U)

+#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */

+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk

+#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */

+#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */

+

+#define GPIO_PUPDR_PUPD11_Pos          (22U)

+#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */

+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk

+#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */

+#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */

+

+#define GPIO_PUPDR_PUPD12_Pos          (24U)

+#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */

+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk

+#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */

+#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */

+

+#define GPIO_PUPDR_PUPD13_Pos          (26U)

+#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */

+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk

+#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */

+#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */

+

+#define GPIO_PUPDR_PUPD14_Pos          (28U)

+#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */

+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk

+#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */

+#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */

+

+#define GPIO_PUPDR_PUPD15_Pos          (30U)

+#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */

+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk

+#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */

+#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_IDR register  *******************/

+#define GPIO_IDR_ID0_Pos               (0U)

+#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */

+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk

+#define GPIO_IDR_ID1_Pos               (1U)

+#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */

+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk

+#define GPIO_IDR_ID2_Pos               (2U)

+#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */

+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk

+#define GPIO_IDR_ID3_Pos               (3U)

+#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */

+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk

+#define GPIO_IDR_ID4_Pos               (4U)

+#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */

+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk

+#define GPIO_IDR_ID5_Pos               (5U)

+#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */

+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk

+#define GPIO_IDR_ID6_Pos               (6U)

+#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */

+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk

+#define GPIO_IDR_ID7_Pos               (7U)

+#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */

+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk

+#define GPIO_IDR_ID8_Pos               (8U)

+#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */

+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk

+#define GPIO_IDR_ID9_Pos               (9U)

+#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */

+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk

+#define GPIO_IDR_ID10_Pos              (10U)

+#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */

+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk

+#define GPIO_IDR_ID11_Pos              (11U)

+#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */

+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk

+#define GPIO_IDR_ID12_Pos              (12U)

+#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */

+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk

+#define GPIO_IDR_ID13_Pos              (13U)

+#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */

+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk

+#define GPIO_IDR_ID14_Pos              (14U)

+#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */

+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk

+#define GPIO_IDR_ID15_Pos              (15U)

+#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */

+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk

+

+/******************  Bits definition for GPIO_ODR register  *******************/

+#define GPIO_ODR_OD0_Pos               (0U)

+#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */

+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk

+#define GPIO_ODR_OD1_Pos               (1U)

+#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */

+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk

+#define GPIO_ODR_OD2_Pos               (2U)

+#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */

+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk

+#define GPIO_ODR_OD3_Pos               (3U)

+#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */

+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk

+#define GPIO_ODR_OD4_Pos               (4U)

+#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */

+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk

+#define GPIO_ODR_OD5_Pos               (5U)

+#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */

+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk

+#define GPIO_ODR_OD6_Pos               (6U)

+#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */

+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk

+#define GPIO_ODR_OD7_Pos               (7U)

+#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */

+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk

+#define GPIO_ODR_OD8_Pos               (8U)

+#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */

+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk

+#define GPIO_ODR_OD9_Pos               (9U)

+#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */

+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk

+#define GPIO_ODR_OD10_Pos              (10U)

+#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */

+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk

+#define GPIO_ODR_OD11_Pos              (11U)

+#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */

+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk

+#define GPIO_ODR_OD12_Pos              (12U)

+#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */

+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk

+#define GPIO_ODR_OD13_Pos              (13U)

+#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */

+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk

+#define GPIO_ODR_OD14_Pos              (14U)

+#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */

+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk

+#define GPIO_ODR_OD15_Pos              (15U)

+#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */

+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk

+

+/******************  Bits definition for GPIO_BSRR register  ******************/

+#define GPIO_BSRR_BS0_Pos              (0U)

+#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */

+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk

+#define GPIO_BSRR_BS1_Pos              (1U)

+#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */

+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk

+#define GPIO_BSRR_BS2_Pos              (2U)

+#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */

+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk

+#define GPIO_BSRR_BS3_Pos              (3U)

+#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */

+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk

+#define GPIO_BSRR_BS4_Pos              (4U)

+#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */

+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk

+#define GPIO_BSRR_BS5_Pos              (5U)

+#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */

+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk

+#define GPIO_BSRR_BS6_Pos              (6U)

+#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */

+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk

+#define GPIO_BSRR_BS7_Pos              (7U)

+#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */

+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk

+#define GPIO_BSRR_BS8_Pos              (8U)

+#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */

+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk

+#define GPIO_BSRR_BS9_Pos              (9U)

+#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */

+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk

+#define GPIO_BSRR_BS10_Pos             (10U)

+#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */

+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk

+#define GPIO_BSRR_BS11_Pos             (11U)

+#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */

+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk

+#define GPIO_BSRR_BS12_Pos             (12U)

+#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */

+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk

+#define GPIO_BSRR_BS13_Pos             (13U)

+#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */

+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk

+#define GPIO_BSRR_BS14_Pos             (14U)

+#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */

+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk

+#define GPIO_BSRR_BS15_Pos             (15U)

+#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */

+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk

+#define GPIO_BSRR_BR0_Pos              (16U)

+#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */

+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk

+#define GPIO_BSRR_BR1_Pos              (17U)

+#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */

+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk

+#define GPIO_BSRR_BR2_Pos              (18U)

+#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */

+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk

+#define GPIO_BSRR_BR3_Pos              (19U)

+#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */

+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk

+#define GPIO_BSRR_BR4_Pos              (20U)

+#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */

+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk

+#define GPIO_BSRR_BR5_Pos              (21U)

+#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */

+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk

+#define GPIO_BSRR_BR6_Pos              (22U)

+#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */

+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk

+#define GPIO_BSRR_BR7_Pos              (23U)

+#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */

+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk

+#define GPIO_BSRR_BR8_Pos              (24U)

+#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */

+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk

+#define GPIO_BSRR_BR9_Pos              (25U)

+#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */

+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk

+#define GPIO_BSRR_BR10_Pos             (26U)

+#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */

+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk

+#define GPIO_BSRR_BR11_Pos             (27U)

+#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */

+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk

+#define GPIO_BSRR_BR12_Pos             (28U)

+#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */

+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk

+#define GPIO_BSRR_BR13_Pos             (29U)

+#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */

+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk

+#define GPIO_BSRR_BR14_Pos             (30U)

+#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */

+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk

+#define GPIO_BSRR_BR15_Pos             (31U)

+#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */

+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk

+

+/****************** Bit definition for GPIO_LCKR register *********************/

+#define GPIO_LCKR_LCK0_Pos             (0U)

+#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */

+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk

+#define GPIO_LCKR_LCK1_Pos             (1U)

+#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */

+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk

+#define GPIO_LCKR_LCK2_Pos             (2U)

+#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */

+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk

+#define GPIO_LCKR_LCK3_Pos             (3U)

+#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */

+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk

+#define GPIO_LCKR_LCK4_Pos             (4U)

+#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */

+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk

+#define GPIO_LCKR_LCK5_Pos             (5U)

+#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */

+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk

+#define GPIO_LCKR_LCK6_Pos             (6U)

+#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */

+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk

+#define GPIO_LCKR_LCK7_Pos             (7U)

+#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */

+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk

+#define GPIO_LCKR_LCK8_Pos             (8U)

+#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */

+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk

+#define GPIO_LCKR_LCK9_Pos             (9U)

+#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */

+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk

+#define GPIO_LCKR_LCK10_Pos            (10U)

+#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */

+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk

+#define GPIO_LCKR_LCK11_Pos            (11U)

+#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */

+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk

+#define GPIO_LCKR_LCK12_Pos            (12U)

+#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */

+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk

+#define GPIO_LCKR_LCK13_Pos            (13U)

+#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */

+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk

+#define GPIO_LCKR_LCK14_Pos            (14U)

+#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */

+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk

+#define GPIO_LCKR_LCK15_Pos            (15U)

+#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */

+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk

+#define GPIO_LCKR_LCKK_Pos             (16U)

+#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */

+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk

+

+/****************** Bit definition for GPIO_AFRL register  ********************/

+#define GPIO_AFRL_AFSEL0_Pos           (0U)

+#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */

+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk

+#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */

+#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */

+#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */

+#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */

+#define GPIO_AFRL_AFSEL1_Pos           (4U)

+#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */

+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk

+#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */

+#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */

+#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */

+#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */

+#define GPIO_AFRL_AFSEL2_Pos           (8U)

+#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */

+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk

+#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */

+#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */

+#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */

+#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */

+#define GPIO_AFRL_AFSEL3_Pos           (12U)

+#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */

+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk

+#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */

+#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */

+#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */

+#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */

+#define GPIO_AFRL_AFSEL4_Pos           (16U)

+#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */

+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk

+#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */

+#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */

+#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */

+#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */

+#define GPIO_AFRL_AFSEL5_Pos           (20U)

+#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */

+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk

+#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */

+#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */

+#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */

+#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */

+#define GPIO_AFRL_AFSEL6_Pos           (24U)

+#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */

+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk

+#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */

+#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */

+#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */

+#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */

+#define GPIO_AFRL_AFSEL7_Pos           (28U)

+#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */

+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk

+#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */

+#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */

+#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */

+#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */

+

+/* Legacy defines */

+#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0

+#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1

+#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2

+#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3

+#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4

+#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5

+#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6

+#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7

+

+/****************** Bit definition for GPIO_AFRH register  ********************/

+#define GPIO_AFRH_AFSEL8_Pos           (0U)

+#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */

+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk

+#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */

+#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */

+#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */

+#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */

+#define GPIO_AFRH_AFSEL9_Pos           (4U)

+#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */

+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk

+#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */

+#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */

+#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */

+#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */

+#define GPIO_AFRH_AFSEL10_Pos          (8U)

+#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */

+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk

+#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */

+#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */

+#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */

+#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */

+#define GPIO_AFRH_AFSEL11_Pos          (12U)

+#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */

+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk

+#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */

+#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */

+#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */

+#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */

+#define GPIO_AFRH_AFSEL12_Pos          (16U)

+#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */

+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk

+#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */

+#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */

+#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */

+#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */

+#define GPIO_AFRH_AFSEL13_Pos          (20U)

+#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */

+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk

+#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */

+#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */

+#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */

+#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */

+#define GPIO_AFRH_AFSEL14_Pos          (24U)

+#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */

+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk

+#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */

+#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */

+#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */

+#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */

+#define GPIO_AFRH_AFSEL15_Pos          (28U)

+#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */

+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk

+#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */

+#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */

+#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */

+#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */

+

+/* Legacy defines */

+#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8

+#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9

+#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10

+#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11

+#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12

+#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13

+#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14

+#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15

+

+/******************************************************************************/

+/*                                                                            */

+/*                        HSEM HW Semaphore                                   */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for HSEM_R register  ********************/

+#define HSEM_R_PROCID_Pos         (0U)

+#define HSEM_R_PROCID_Msk         (0xFFUL << HSEM_R_PROCID_Pos)                /*!< 0x000000FF */

+#define HSEM_R_PROCID             HSEM_R_PROCID_Msk                            /*!<Semaphore ProcessID */

+#define HSEM_R_COREID_Pos         (8U)

+#define HSEM_R_COREID_Msk         (0xFFUL << HSEM_R_COREID_Pos)                /*!< 0x0000FF00 */

+#define HSEM_R_COREID             HSEM_R_COREID_Msk                            /*!<Semaphore CoreID.   */

+#define HSEM_R_LOCK_Pos           (31U)

+#define HSEM_R_LOCK_Msk           (0x1UL << HSEM_R_LOCK_Pos)                   /*!< 0x80000000 */

+#define HSEM_R_LOCK               HSEM_R_LOCK_Msk                              /*!<Lock indication.    */

+

+/********************  Bit definition for HSEM_RLR register  ******************/

+#define HSEM_RLR_PROCID_Pos       (0U)

+#define HSEM_RLR_PROCID_Msk       (0xFFUL << HSEM_RLR_PROCID_Pos)              /*!< 0x000000FF */

+#define HSEM_RLR_PROCID           HSEM_RLR_PROCID_Msk                          /*!<Semaphore ProcessID */

+#define HSEM_RLR_COREID_Pos       (8U)

+#define HSEM_RLR_COREID_Msk       (0xFFUL << HSEM_RLR_COREID_Pos)              /*!< 0x0000FF00 */

+#define HSEM_RLR_COREID           HSEM_RLR_COREID_Msk                          /*!<Semaphore CoreID.   */

+#define HSEM_RLR_LOCK_Pos         (31U)

+#define HSEM_RLR_LOCK_Msk         (0x1UL << HSEM_RLR_LOCK_Pos)                 /*!< 0x80000000 */

+#define HSEM_RLR_LOCK             HSEM_RLR_LOCK_Msk                            /*!<Lock indication.    */

+

+/********************  Bit definition for HSEM_C1IER register  *****************/

+#define HSEM_C1IER_ISE0_Pos       (0U)

+#define HSEM_C1IER_ISE0_Msk       (0x1UL << HSEM_C1IER_ISE0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1IER_ISE0           HSEM_C1IER_ISE0_Msk                          /*!<semaphore 0 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE1_Pos       (1U)

+#define HSEM_C1IER_ISE1_Msk       (0x1UL << HSEM_C1IER_ISE1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1IER_ISE1           HSEM_C1IER_ISE1_Msk                          /*!<semaphore 1 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE2_Pos       (2U)

+#define HSEM_C1IER_ISE2_Msk       (0x1UL << HSEM_C1IER_ISE2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1IER_ISE2           HSEM_C1IER_ISE2_Msk                          /*!<semaphore 2 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE3_Pos       (3U)

+#define HSEM_C1IER_ISE3_Msk       (0x1UL << HSEM_C1IER_ISE3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1IER_ISE3           HSEM_C1IER_ISE3_Msk                          /*!<semaphore 3 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE4_Pos       (4U)

+#define HSEM_C1IER_ISE4_Msk       (0x1UL << HSEM_C1IER_ISE4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1IER_ISE4           HSEM_C1IER_ISE4_Msk                          /*!<semaphore 4 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE5_Pos       (5U)

+#define HSEM_C1IER_ISE5_Msk       (0x1UL << HSEM_C1IER_ISE5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1IER_ISE5           HSEM_C1IER_ISE5_Msk                          /*!<semaphore 5 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE6_Pos       (6U)

+#define HSEM_C1IER_ISE6_Msk       (0x1UL << HSEM_C1IER_ISE6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1IER_ISE6           HSEM_C1IER_ISE6_Msk                          /*!<semaphore 6 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE7_Pos       (7U)

+#define HSEM_C1IER_ISE7_Msk       (0x1UL << HSEM_C1IER_ISE7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1IER_ISE7           HSEM_C1IER_ISE7_Msk                          /*!<semaphore 7 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE8_Pos       (8U)

+#define HSEM_C1IER_ISE8_Msk       (0x1UL << HSEM_C1IER_ISE8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1IER_ISE8           HSEM_C1IER_ISE8_Msk                          /*!<semaphore 8 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE9_Pos       (9U)

+#define HSEM_C1IER_ISE9_Msk       (0x1UL << HSEM_C1IER_ISE9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1IER_ISE9           HSEM_C1IER_ISE9_Msk                          /*!<semaphore 9 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE10_Pos      (10U)

+#define HSEM_C1IER_ISE10_Msk      (0x1UL << HSEM_C1IER_ISE10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1IER_ISE10          HSEM_C1IER_ISE10_Msk                         /*!<semaphore 10 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE11_Pos      (11U)

+#define HSEM_C1IER_ISE11_Msk      (0x1UL << HSEM_C1IER_ISE11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1IER_ISE11          HSEM_C1IER_ISE11_Msk                         /*!<semaphore 11 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE12_Pos      (12U)

+#define HSEM_C1IER_ISE12_Msk      (0x1UL << HSEM_C1IER_ISE12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1IER_ISE12          HSEM_C1IER_ISE12_Msk                         /*!<semaphore 12 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE13_Pos      (13U)

+#define HSEM_C1IER_ISE13_Msk      (0x1UL << HSEM_C1IER_ISE13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1IER_ISE13          HSEM_C1IER_ISE13_Msk                         /*!<semaphore 13 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE14_Pos      (14U)

+#define HSEM_C1IER_ISE14_Msk      (0x1UL << HSEM_C1IER_ISE14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1IER_ISE14          HSEM_C1IER_ISE14_Msk                         /*!<semaphore 14 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE15_Pos      (15U)

+#define HSEM_C1IER_ISE15_Msk      (0x1UL << HSEM_C1IER_ISE15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1IER_ISE15          HSEM_C1IER_ISE15_Msk                         /*!<semaphore 15 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE16_Pos      (16U)

+#define HSEM_C1IER_ISE16_Msk      (0x1UL << HSEM_C1IER_ISE16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1IER_ISE16          HSEM_C1IER_ISE16_Msk                         /*!<semaphore 16 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE17_Pos      (17U)

+#define HSEM_C1IER_ISE17_Msk      (0x1UL << HSEM_C1IER_ISE17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1IER_ISE17          HSEM_C1IER_ISE17_Msk                         /*!<semaphore 17 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE18_Pos      (18U)

+#define HSEM_C1IER_ISE18_Msk      (0x1UL << HSEM_C1IER_ISE18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1IER_ISE18          HSEM_C1IER_ISE18_Msk                         /*!<semaphore 18 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE19_Pos      (19U)

+#define HSEM_C1IER_ISE19_Msk      (0x1UL << HSEM_C1IER_ISE19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1IER_ISE19          HSEM_C1IER_ISE19_Msk                         /*!<semaphore 19 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE20_Pos      (20U)

+#define HSEM_C1IER_ISE20_Msk      (0x1UL << HSEM_C1IER_ISE20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1IER_ISE20          HSEM_C1IER_ISE20_Msk                         /*!<semaphore 20 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE21_Pos      (21U)

+#define HSEM_C1IER_ISE21_Msk      (0x1UL << HSEM_C1IER_ISE21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1IER_ISE21          HSEM_C1IER_ISE21_Msk                         /*!<semaphore 21 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE22_Pos      (22U)

+#define HSEM_C1IER_ISE22_Msk      (0x1UL << HSEM_C1IER_ISE22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1IER_ISE22          HSEM_C1IER_ISE22_Msk                         /*!<semaphore 22 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE23_Pos      (23U)

+#define HSEM_C1IER_ISE23_Msk      (0x1UL << HSEM_C1IER_ISE23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1IER_ISE23          HSEM_C1IER_ISE23_Msk                         /*!<semaphore 23 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE24_Pos      (24U)

+#define HSEM_C1IER_ISE24_Msk      (0x1UL << HSEM_C1IER_ISE24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1IER_ISE24          HSEM_C1IER_ISE24_Msk                         /*!<semaphore 24 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE25_Pos      (25U)

+#define HSEM_C1IER_ISE25_Msk      (0x1UL << HSEM_C1IER_ISE25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1IER_ISE25          HSEM_C1IER_ISE25_Msk                         /*!<semaphore 25 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE26_Pos      (26U)

+#define HSEM_C1IER_ISE26_Msk      (0x1UL << HSEM_C1IER_ISE26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1IER_ISE26          HSEM_C1IER_ISE26_Msk                         /*!<semaphore 26 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE27_Pos      (27U)

+#define HSEM_C1IER_ISE27_Msk      (0x1UL << HSEM_C1IER_ISE27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1IER_ISE27          HSEM_C1IER_ISE27_Msk                         /*!<semaphore 27 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE28_Pos      (28U)

+#define HSEM_C1IER_ISE28_Msk      (0x1UL << HSEM_C1IER_ISE28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1IER_ISE28          HSEM_C1IER_ISE28_Msk                         /*!<semaphore 28 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE29_Pos      (29U)

+#define HSEM_C1IER_ISE29_Msk      (0x1UL << HSEM_C1IER_ISE29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1IER_ISE29          HSEM_C1IER_ISE29_Msk                         /*!<semaphore 29 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE30_Pos      (30U)

+#define HSEM_C1IER_ISE30_Msk      (0x1UL << HSEM_C1IER_ISE30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1IER_ISE30          HSEM_C1IER_ISE30_Msk                         /*!<semaphore 30 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE31_Pos      (31U)

+#define HSEM_C1IER_ISE31_Msk      (0x1UL << HSEM_C1IER_ISE31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1IER_ISE31          HSEM_C1IER_ISE31_Msk                         /*!<semaphore 31 interrupt 0 enable bit. */

+

+/********************  Bit definition for HSEM_C1ICR register  *****************/

+#define HSEM_C1ICR_ISC0_Pos       (0U)

+#define HSEM_C1ICR_ISC0_Msk       (0x1UL << HSEM_C1ICR_ISC0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1ICR_ISC0           HSEM_C1ICR_ISC0_Msk                          /*!<semaphore 0 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC1_Pos       (1U)

+#define HSEM_C1ICR_ISC1_Msk       (0x1UL << HSEM_C1ICR_ISC1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1ICR_ISC1           HSEM_C1ICR_ISC1_Msk                          /*!<semaphore 1 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC2_Pos       (2U)

+#define HSEM_C1ICR_ISC2_Msk       (0x1UL << HSEM_C1ICR_ISC2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1ICR_ISC2           HSEM_C1ICR_ISC2_Msk                          /*!<semaphore 2 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC3_Pos       (3U)

+#define HSEM_C1ICR_ISC3_Msk       (0x1UL << HSEM_C1ICR_ISC3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1ICR_ISC3           HSEM_C1ICR_ISC3_Msk                          /*!<semaphore 3 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC4_Pos       (4U)

+#define HSEM_C1ICR_ISC4_Msk       (0x1UL << HSEM_C1ICR_ISC4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1ICR_ISC4           HSEM_C1ICR_ISC4_Msk                          /*!<semaphore 4 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC5_Pos       (5U)

+#define HSEM_C1ICR_ISC5_Msk       (0x1UL << HSEM_C1ICR_ISC5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1ICR_ISC5           HSEM_C1ICR_ISC5_Msk                          /*!<semaphore 5 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC6_Pos       (6U)

+#define HSEM_C1ICR_ISC6_Msk       (0x1UL << HSEM_C1ICR_ISC6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1ICR_ISC6           HSEM_C1ICR_ISC6_Msk                          /*!<semaphore 6 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC7_Pos       (7U)

+#define HSEM_C1ICR_ISC7_Msk       (0x1UL << HSEM_C1ICR_ISC7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1ICR_ISC7           HSEM_C1ICR_ISC7_Msk                          /*!<semaphore 7 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC8_Pos       (8U)

+#define HSEM_C1ICR_ISC8_Msk       (0x1UL << HSEM_C1ICR_ISC8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1ICR_ISC8           HSEM_C1ICR_ISC8_Msk                          /*!<semaphore 8 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC9_Pos       (9U)

+#define HSEM_C1ICR_ISC9_Msk       (0x1UL << HSEM_C1ICR_ISC9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1ICR_ISC9           HSEM_C1ICR_ISC9_Msk                          /*!<semaphore 9 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC10_Pos      (10U)

+#define HSEM_C1ICR_ISC10_Msk      (0x1UL << HSEM_C1ICR_ISC10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1ICR_ISC10          HSEM_C1ICR_ISC10_Msk                         /*!<semaphore 10 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC11_Pos      (11U)

+#define HSEM_C1ICR_ISC11_Msk      (0x1UL << HSEM_C1ICR_ISC11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1ICR_ISC11          HSEM_C1ICR_ISC11_Msk                         /*!<semaphore 11 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC12_Pos      (12U)

+#define HSEM_C1ICR_ISC12_Msk      (0x1UL << HSEM_C1ICR_ISC12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1ICR_ISC12          HSEM_C1ICR_ISC12_Msk                         /*!<semaphore 12 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC13_Pos      (13U)

+#define HSEM_C1ICR_ISC13_Msk      (0x1UL << HSEM_C1ICR_ISC13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1ICR_ISC13          HSEM_C1ICR_ISC13_Msk                         /*!<semaphore 13 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC14_Pos      (14U)

+#define HSEM_C1ICR_ISC14_Msk      (0x1UL << HSEM_C1ICR_ISC14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1ICR_ISC14          HSEM_C1ICR_ISC14_Msk                         /*!<semaphore 14 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC15_Pos      (15U)

+#define HSEM_C1ICR_ISC15_Msk      (0x1UL << HSEM_C1ICR_ISC15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1ICR_ISC15          HSEM_C1ICR_ISC15_Msk                         /*!<semaphore 15 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC16_Pos      (16U)

+#define HSEM_C1ICR_ISC16_Msk      (0x1UL << HSEM_C1ICR_ISC16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1ICR_ISC16          HSEM_C1ICR_ISC16_Msk                         /*!<semaphore 16 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC17_Pos      (17U)

+#define HSEM_C1ICR_ISC17_Msk      (0x1UL << HSEM_C1ICR_ISC17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1ICR_ISC17          HSEM_C1ICR_ISC17_Msk                         /*!<semaphore 17 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC18_Pos      (18U)

+#define HSEM_C1ICR_ISC18_Msk      (0x1UL << HSEM_C1ICR_ISC18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1ICR_ISC18          HSEM_C1ICR_ISC18_Msk                         /*!<semaphore 18 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC19_Pos      (19U)

+#define HSEM_C1ICR_ISC19_Msk      (0x1UL << HSEM_C1ICR_ISC19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1ICR_ISC19          HSEM_C1ICR_ISC19_Msk                         /*!<semaphore 19 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC20_Pos      (20U)

+#define HSEM_C1ICR_ISC20_Msk      (0x1UL << HSEM_C1ICR_ISC20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1ICR_ISC20          HSEM_C1ICR_ISC20_Msk                         /*!<semaphore 20 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC21_Pos      (21U)

+#define HSEM_C1ICR_ISC21_Msk      (0x1UL << HSEM_C1ICR_ISC21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1ICR_ISC21          HSEM_C1ICR_ISC21_Msk                         /*!<semaphore 21 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC22_Pos      (22U)

+#define HSEM_C1ICR_ISC22_Msk      (0x1UL << HSEM_C1ICR_ISC22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1ICR_ISC22          HSEM_C1ICR_ISC22_Msk                         /*!<semaphore 22 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC23_Pos      (23U)

+#define HSEM_C1ICR_ISC23_Msk      (0x1UL << HSEM_C1ICR_ISC23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1ICR_ISC23          HSEM_C1ICR_ISC23_Msk                         /*!<semaphore 23 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC24_Pos      (24U)

+#define HSEM_C1ICR_ISC24_Msk      (0x1UL << HSEM_C1ICR_ISC24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1ICR_ISC24          HSEM_C1ICR_ISC24_Msk                         /*!<semaphore 24 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC25_Pos      (25U)

+#define HSEM_C1ICR_ISC25_Msk      (0x1UL << HSEM_C1ICR_ISC25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1ICR_ISC25          HSEM_C1ICR_ISC25_Msk                         /*!<semaphore 25 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC26_Pos      (26U)

+#define HSEM_C1ICR_ISC26_Msk      (0x1UL << HSEM_C1ICR_ISC26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1ICR_ISC26          HSEM_C1ICR_ISC26_Msk                         /*!<semaphore 26 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC27_Pos      (27U)

+#define HSEM_C1ICR_ISC27_Msk      (0x1UL << HSEM_C1ICR_ISC27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1ICR_ISC27          HSEM_C1ICR_ISC27_Msk                         /*!<semaphore 27 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC28_Pos      (28U)

+#define HSEM_C1ICR_ISC28_Msk      (0x1UL << HSEM_C1ICR_ISC28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1ICR_ISC28          HSEM_C1ICR_ISC28_Msk                         /*!<semaphore 28 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC29_Pos      (29U)

+#define HSEM_C1ICR_ISC29_Msk      (0x1UL << HSEM_C1ICR_ISC29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1ICR_ISC29          HSEM_C1ICR_ISC29_Msk                         /*!<semaphore 29 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC30_Pos      (30U)

+#define HSEM_C1ICR_ISC30_Msk      (0x1UL << HSEM_C1ICR_ISC30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1ICR_ISC30          HSEM_C1ICR_ISC30_Msk                         /*!<semaphore 30 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC31_Pos      (31U)

+#define HSEM_C1ICR_ISC31_Msk      (0x1UL << HSEM_C1ICR_ISC31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1ICR_ISC31          HSEM_C1ICR_ISC31_Msk                         /*!<semaphore 31 interrupt 0 clear bit. */

+

+/********************  Bit definition for HSEM_C1ISR register  *****************/

+#define HSEM_C1ISR_ISF0_Pos       (0U)

+#define HSEM_C1ISR_ISF0_Msk       (0x1UL << HSEM_C1ISR_ISF0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1ISR_ISF0           HSEM_C1ISR_ISF0_Msk                          /*!<semaphore 0 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF1_Pos       (1U)

+#define HSEM_C1ISR_ISF1_Msk       (0x1UL << HSEM_C1ISR_ISF1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1ISR_ISF1           HSEM_C1ISR_ISF1_Msk                          /*!<semaphore 1 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF2_Pos       (2U)

+#define HSEM_C1ISR_ISF2_Msk       (0x1UL << HSEM_C1ISR_ISF2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1ISR_ISF2           HSEM_C1ISR_ISF2_Msk                          /*!<semaphore 2 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF3_Pos       (3U)

+#define HSEM_C1ISR_ISF3_Msk       (0x1UL << HSEM_C1ISR_ISF3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1ISR_ISF3           HSEM_C1ISR_ISF3_Msk                          /*!<semaphore 3 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF4_Pos       (4U)

+#define HSEM_C1ISR_ISF4_Msk       (0x1UL << HSEM_C1ISR_ISF4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1ISR_ISF4           HSEM_C1ISR_ISF4_Msk                          /*!<semaphore 4 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF5_Pos       (5U)

+#define HSEM_C1ISR_ISF5_Msk       (0x1UL << HSEM_C1ISR_ISF5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1ISR_ISF5           HSEM_C1ISR_ISF5_Msk                          /*!<semaphore 5 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF6_Pos       (6U)

+#define HSEM_C1ISR_ISF6_Msk       (0x1UL << HSEM_C1ISR_ISF6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1ISR_ISF6           HSEM_C1ISR_ISF6_Msk                          /*!<semaphore 6 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF7_Pos       (7U)

+#define HSEM_C1ISR_ISF7_Msk       (0x1UL << HSEM_C1ISR_ISF7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1ISR_ISF7           HSEM_C1ISR_ISF7_Msk                          /*!<semaphore 7 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF8_Pos       (8U)

+#define HSEM_C1ISR_ISF8_Msk       (0x1UL << HSEM_C1ISR_ISF8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1ISR_ISF8           HSEM_C1ISR_ISF8_Msk                          /*!<semaphore 8 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF9_Pos       (9U)

+#define HSEM_C1ISR_ISF9_Msk       (0x1UL << HSEM_C1ISR_ISF9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1ISR_ISF9           HSEM_C1ISR_ISF9_Msk                          /*!<semaphore 9 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF10_Pos      (10U)

+#define HSEM_C1ISR_ISF10_Msk      (0x1UL << HSEM_C1ISR_ISF10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1ISR_ISF10          HSEM_C1ISR_ISF10_Msk                         /*!<semaphore 10 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF11_Pos      (11U)

+#define HSEM_C1ISR_ISF11_Msk      (0x1UL << HSEM_C1ISR_ISF11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1ISR_ISF11          HSEM_C1ISR_ISF11_Msk                         /*!<semaphore 11 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF12_Pos      (12U)

+#define HSEM_C1ISR_ISF12_Msk      (0x1UL << HSEM_C1ISR_ISF12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1ISR_ISF12          HSEM_C1ISR_ISF12_Msk                         /*!<semaphore 12 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF13_Pos      (13U)

+#define HSEM_C1ISR_ISF13_Msk      (0x1UL << HSEM_C1ISR_ISF13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1ISR_ISF13          HSEM_C1ISR_ISF13_Msk                         /*!<semaphore 13 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF14_Pos      (14U)

+#define HSEM_C1ISR_ISF14_Msk      (0x1UL << HSEM_C1ISR_ISF14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1ISR_ISF14          HSEM_C1ISR_ISF14_Msk                         /*!<semaphore 14 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF15_Pos      (15U)

+#define HSEM_C1ISR_ISF15_Msk      (0x1UL << HSEM_C1ISR_ISF15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1ISR_ISF15          HSEM_C1ISR_ISF15_Msk                         /*!<semaphore 15 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF16_Pos      (16U)

+#define HSEM_C1ISR_ISF16_Msk      (0x1UL << HSEM_C1ISR_ISF16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1ISR_ISF16          HSEM_C1ISR_ISF16_Msk                         /*!<semaphore 16 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF17_Pos      (17U)

+#define HSEM_C1ISR_ISF17_Msk      (0x1UL << HSEM_C1ISR_ISF17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1ISR_ISF17          HSEM_C1ISR_ISF17_Msk                         /*!<semaphore 17 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF18_Pos      (18U)

+#define HSEM_C1ISR_ISF18_Msk      (0x1UL << HSEM_C1ISR_ISF18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1ISR_ISF18          HSEM_C1ISR_ISF18_Msk                         /*!<semaphore 18 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF19_Pos      (19U)

+#define HSEM_C1ISR_ISF19_Msk      (0x1UL << HSEM_C1ISR_ISF19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1ISR_ISF19          HSEM_C1ISR_ISF19_Msk                         /*!<semaphore 19 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF20_Pos      (20U)

+#define HSEM_C1ISR_ISF20_Msk      (0x1UL << HSEM_C1ISR_ISF20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1ISR_ISF20          HSEM_C1ISR_ISF20_Msk                         /*!<semaphore 20 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF21_Pos      (21U)

+#define HSEM_C1ISR_ISF21_Msk      (0x1UL << HSEM_C1ISR_ISF21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1ISR_ISF21          HSEM_C1ISR_ISF21_Msk                         /*!<semaphore 21 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF22_Pos      (22U)

+#define HSEM_C1ISR_ISF22_Msk      (0x1UL << HSEM_C1ISR_ISF22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1ISR_ISF22          HSEM_C1ISR_ISF22_Msk                         /*!<semaphore 22 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF23_Pos      (23U)

+#define HSEM_C1ISR_ISF23_Msk      (0x1UL << HSEM_C1ISR_ISF23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1ISR_ISF23          HSEM_C1ISR_ISF23_Msk                         /*!<semaphore 23 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF24_Pos      (24U)

+#define HSEM_C1ISR_ISF24_Msk      (0x1UL << HSEM_C1ISR_ISF24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1ISR_ISF24          HSEM_C1ISR_ISF24_Msk                         /*!<semaphore 24 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF25_Pos      (25U)

+#define HSEM_C1ISR_ISF25_Msk      (0x1UL << HSEM_C1ISR_ISF25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1ISR_ISF25          HSEM_C1ISR_ISF25_Msk                         /*!<semaphore 25 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF26_Pos      (26U)

+#define HSEM_C1ISR_ISF26_Msk      (0x1UL << HSEM_C1ISR_ISF26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1ISR_ISF26          HSEM_C1ISR_ISF26_Msk                         /*!<semaphore 26 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF27_Pos      (27U)

+#define HSEM_C1ISR_ISF27_Msk      (0x1UL << HSEM_C1ISR_ISF27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1ISR_ISF27          HSEM_C1ISR_ISF27_Msk                         /*!<semaphore 27 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF28_Pos      (28U)

+#define HSEM_C1ISR_ISF28_Msk      (0x1UL << HSEM_C1ISR_ISF28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1ISR_ISF28          HSEM_C1ISR_ISF28_Msk                         /*!<semaphore 28 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF29_Pos      (29U)

+#define HSEM_C1ISR_ISF29_Msk      (0x1UL << HSEM_C1ISR_ISF29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1ISR_ISF29          HSEM_C1ISR_ISF29_Msk                         /*!<semaphore 29 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF30_Pos      (30U)

+#define HSEM_C1ISR_ISF30_Msk      (0x1UL << HSEM_C1ISR_ISF30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1ISR_ISF30          HSEM_C1ISR_ISF30_Msk                         /*!<semaphore 30 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF31_Pos      (31U)

+#define HSEM_C1ISR_ISF31_Msk      (0x1UL << HSEM_C1ISR_ISF31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1ISR_ISF31          HSEM_C1ISR_ISF31_Msk                         /*!<semaphore 31 interrupt 0 status bit. */

+

+/********************  Bit definition for HSEM_C1MISR register  *****************/

+#define HSEM_C1MISR_MISF0_Pos     (0U)

+#define HSEM_C1MISR_MISF0_Msk     (0x1UL << HSEM_C1MISR_MISF0_Pos)             /*!< 0x00000001 */

+#define HSEM_C1MISR_MISF0         HSEM_C1MISR_MISF0_Msk                        /*!<semaphore 0 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF1_Pos     (1U)

+#define HSEM_C1MISR_MISF1_Msk     (0x1UL << HSEM_C1MISR_MISF1_Pos)             /*!< 0x00000002 */

+#define HSEM_C1MISR_MISF1         HSEM_C1MISR_MISF1_Msk                        /*!<semaphore 1 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF2_Pos     (2U)

+#define HSEM_C1MISR_MISF2_Msk     (0x1UL << HSEM_C1MISR_MISF2_Pos)             /*!< 0x00000004 */

+#define HSEM_C1MISR_MISF2         HSEM_C1MISR_MISF2_Msk                        /*!<semaphore 2 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF3_Pos     (3U)

+#define HSEM_C1MISR_MISF3_Msk     (0x1UL << HSEM_C1MISR_MISF3_Pos)             /*!< 0x00000008 */

+#define HSEM_C1MISR_MISF3         HSEM_C1MISR_MISF3_Msk                        /*!<semaphore 3 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF4_Pos     (4U)

+#define HSEM_C1MISR_MISF4_Msk     (0x1UL << HSEM_C1MISR_MISF4_Pos)             /*!< 0x00000010 */

+#define HSEM_C1MISR_MISF4         HSEM_C1MISR_MISF4_Msk                        /*!<semaphore 4 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF5_Pos     (5U)

+#define HSEM_C1MISR_MISF5_Msk     (0x1UL << HSEM_C1MISR_MISF5_Pos)             /*!< 0x00000020 */

+#define HSEM_C1MISR_MISF5         HSEM_C1MISR_MISF5_Msk                        /*!<semaphore 5 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF6_Pos     (6U)

+#define HSEM_C1MISR_MISF6_Msk     (0x1UL << HSEM_C1MISR_MISF6_Pos)             /*!< 0x00000040 */

+#define HSEM_C1MISR_MISF6         HSEM_C1MISR_MISF6_Msk                        /*!<semaphore 6 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF7_Pos     (7U)

+#define HSEM_C1MISR_MISF7_Msk     (0x1UL << HSEM_C1MISR_MISF7_Pos)             /*!< 0x00000080 */

+#define HSEM_C1MISR_MISF7         HSEM_C1MISR_MISF7_Msk                        /*!<semaphore 7 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF8_Pos     (8U)

+#define HSEM_C1MISR_MISF8_Msk     (0x1UL << HSEM_C1MISR_MISF8_Pos)             /*!< 0x00000100 */

+#define HSEM_C1MISR_MISF8         HSEM_C1MISR_MISF8_Msk                        /*!<semaphore 8 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF9_Pos     (9U)

+#define HSEM_C1MISR_MISF9_Msk     (0x1UL << HSEM_C1MISR_MISF9_Pos)             /*!< 0x00000200 */

+#define HSEM_C1MISR_MISF9         HSEM_C1MISR_MISF9_Msk                        /*!<semaphore 9 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF10_Pos    (10U)

+#define HSEM_C1MISR_MISF10_Msk    (0x1UL << HSEM_C1MISR_MISF10_Pos)            /*!< 0x00000400 */

+#define HSEM_C1MISR_MISF10        HSEM_C1MISR_MISF10_Msk                       /*!<semaphore 10 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF11_Pos    (11U)

+#define HSEM_C1MISR_MISF11_Msk    (0x1UL << HSEM_C1MISR_MISF11_Pos)            /*!< 0x00000800 */

+#define HSEM_C1MISR_MISF11        HSEM_C1MISR_MISF11_Msk                       /*!<semaphore 11 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF12_Pos    (12U)

+#define HSEM_C1MISR_MISF12_Msk    (0x1UL << HSEM_C1MISR_MISF12_Pos)            /*!< 0x00001000 */

+#define HSEM_C1MISR_MISF12        HSEM_C1MISR_MISF12_Msk                       /*!<semaphore 12 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF13_Pos    (13U)

+#define HSEM_C1MISR_MISF13_Msk    (0x1UL << HSEM_C1MISR_MISF13_Pos)            /*!< 0x00002000 */

+#define HSEM_C1MISR_MISF13        HSEM_C1MISR_MISF13_Msk                       /*!<semaphore 13 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF14_Pos    (14U)

+#define HSEM_C1MISR_MISF14_Msk    (0x1UL << HSEM_C1MISR_MISF14_Pos)            /*!< 0x00004000 */

+#define HSEM_C1MISR_MISF14        HSEM_C1MISR_MISF14_Msk                       /*!<semaphore 14 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF15_Pos    (15U)

+#define HSEM_C1MISR_MISF15_Msk    (0x1UL << HSEM_C1MISR_MISF15_Pos)            /*!< 0x00008000 */

+#define HSEM_C1MISR_MISF15        HSEM_C1MISR_MISF15_Msk                       /*!<semaphore 15 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF16_Pos    (16U)

+#define HSEM_C1MISR_MISF16_Msk    (0x1UL << HSEM_C1MISR_MISF16_Pos)            /*!< 0x00010000 */

+#define HSEM_C1MISR_MISF16        HSEM_C1MISR_MISF16_Msk                       /*!<semaphore 16 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF17_Pos    (17U)

+#define HSEM_C1MISR_MISF17_Msk    (0x1UL << HSEM_C1MISR_MISF17_Pos)            /*!< 0x00020000 */

+#define HSEM_C1MISR_MISF17        HSEM_C1MISR_MISF17_Msk                       /*!<semaphore 17 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF18_Pos    (18U)

+#define HSEM_C1MISR_MISF18_Msk    (0x1UL << HSEM_C1MISR_MISF18_Pos)            /*!< 0x00040000 */

+#define HSEM_C1MISR_MISF18        HSEM_C1MISR_MISF18_Msk                       /*!<semaphore 18 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF19_Pos    (19U)

+#define HSEM_C1MISR_MISF19_Msk    (0x1UL << HSEM_C1MISR_MISF19_Pos)            /*!< 0x00080000 */

+#define HSEM_C1MISR_MISF19        HSEM_C1MISR_MISF19_Msk                       /*!<semaphore 19 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF20_Pos    (20U)

+#define HSEM_C1MISR_MISF20_Msk    (0x1UL << HSEM_C1MISR_MISF20_Pos)            /*!< 0x00100000 */

+#define HSEM_C1MISR_MISF20        HSEM_C1MISR_MISF20_Msk                       /*!<semaphore 20 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF21_Pos    (21U)

+#define HSEM_C1MISR_MISF21_Msk    (0x1UL << HSEM_C1MISR_MISF21_Pos)            /*!< 0x00200000 */

+#define HSEM_C1MISR_MISF21        HSEM_C1MISR_MISF21_Msk                       /*!<semaphore 21 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF22_Pos    (22U)

+#define HSEM_C1MISR_MISF22_Msk    (0x1UL << HSEM_C1MISR_MISF22_Pos)            /*!< 0x00400000 */

+#define HSEM_C1MISR_MISF22        HSEM_C1MISR_MISF22_Msk                       /*!<semaphore 22 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF23_Pos    (23U)

+#define HSEM_C1MISR_MISF23_Msk    (0x1UL << HSEM_C1MISR_MISF23_Pos)            /*!< 0x00800000 */

+#define HSEM_C1MISR_MISF23        HSEM_C1MISR_MISF23_Msk                       /*!<semaphore 23 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF24_Pos    (24U)

+#define HSEM_C1MISR_MISF24_Msk    (0x1UL << HSEM_C1MISR_MISF24_Pos)            /*!< 0x01000000 */

+#define HSEM_C1MISR_MISF24        HSEM_C1MISR_MISF24_Msk                       /*!<semaphore 24 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF25_Pos    (25U)

+#define HSEM_C1MISR_MISF25_Msk    (0x1UL << HSEM_C1MISR_MISF25_Pos)            /*!< 0x02000000 */

+#define HSEM_C1MISR_MISF25        HSEM_C1MISR_MISF25_Msk                       /*!<semaphore 25 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF26_Pos    (26U)

+#define HSEM_C1MISR_MISF26_Msk    (0x1UL << HSEM_C1MISR_MISF26_Pos)            /*!< 0x04000000 */

+#define HSEM_C1MISR_MISF26        HSEM_C1MISR_MISF26_Msk                       /*!<semaphore 26 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF27_Pos    (27U)

+#define HSEM_C1MISR_MISF27_Msk    (0x1UL << HSEM_C1MISR_MISF27_Pos)            /*!< 0x08000000 */

+#define HSEM_C1MISR_MISF27        HSEM_C1MISR_MISF27_Msk                       /*!<semaphore 27 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF28_Pos    (28U)

+#define HSEM_C1MISR_MISF28_Msk    (0x1UL << HSEM_C1MISR_MISF28_Pos)            /*!< 0x10000000 */

+#define HSEM_C1MISR_MISF28        HSEM_C1MISR_MISF28_Msk                       /*!<semaphore 28 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF29_Pos    (29U)

+#define HSEM_C1MISR_MISF29_Msk    (0x1UL << HSEM_C1MISR_MISF29_Pos)            /*!< 0x20000000 */

+#define HSEM_C1MISR_MISF29        HSEM_C1MISR_MISF29_Msk                       /*!<semaphore 29 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF30_Pos    (30U)

+#define HSEM_C1MISR_MISF30_Msk    (0x1UL << HSEM_C1MISR_MISF30_Pos)            /*!< 0x40000000 */

+#define HSEM_C1MISR_MISF30        HSEM_C1MISR_MISF30_Msk                       /*!<semaphore 30 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF31_Pos    (31U)

+#define HSEM_C1MISR_MISF31_Msk    (0x1UL << HSEM_C1MISR_MISF31_Pos)            /*!< 0x80000000 */

+#define HSEM_C1MISR_MISF31        HSEM_C1MISR_MISF31_Msk                       /*!<semaphore 31 interrupt 0 masked status bit. */

+

+/********************  Bit definition for HSEM_CR register  *****************/

+#define HSEM_CR_COREID_Pos        (8U)

+#define HSEM_CR_COREID_Msk        (0xFFUL << HSEM_CR_COREID_Pos)               /*!< 0x0000FF00 */

+#define HSEM_CR_COREID            HSEM_CR_COREID_Msk                           /*!<CoreID of semaphores to be cleared. */

+#define HSEM_CR_KEY_Pos           (16U)

+#define HSEM_CR_KEY_Msk           (0xFFFFUL << HSEM_CR_KEY_Pos)                /*!< 0xFFFF0000 */

+#define HSEM_CR_KEY               HSEM_CR_KEY_Msk                              /*!<semaphores clear key. */

+

+/********************  Bit definition for HSEM_KEYR register  *****************/

+#define HSEM_KEYR_KEY_Pos         (16U)

+#define HSEM_KEYR_KEY_Msk         (0xFFFFUL << HSEM_KEYR_KEY_Pos)              /*!< 0xFFFF0000 */

+#define HSEM_KEYR_KEY             HSEM_KEYR_KEY_Msk                            /*!<semaphores clear key. */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    HASH                                    */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bits definition for HASH_CR register  ********************/

+#define HASH_CR_INIT_Pos          (2U)

+#define HASH_CR_INIT_Msk          (0x1UL << HASH_CR_INIT_Pos)                  /*!< 0x00000004 */

+#define HASH_CR_INIT              HASH_CR_INIT_Msk

+#define HASH_CR_DMAE_Pos          (3U)

+#define HASH_CR_DMAE_Msk          (0x1UL << HASH_CR_DMAE_Pos)                  /*!< 0x00000008 */

+#define HASH_CR_DMAE              HASH_CR_DMAE_Msk

+#define HASH_CR_DATATYPE_Pos      (4U)

+#define HASH_CR_DATATYPE_Msk      (0x3UL << HASH_CR_DATATYPE_Pos)              /*!< 0x00000030 */

+#define HASH_CR_DATATYPE          HASH_CR_DATATYPE_Msk

+#define HASH_CR_DATATYPE_0        (0x1UL << HASH_CR_DATATYPE_Pos)               /*!< 0x00000010 */

+#define HASH_CR_DATATYPE_1        (0x2UL << HASH_CR_DATATYPE_Pos)               /*!< 0x00000020 */

+#define HASH_CR_MODE_Pos          (6U)

+#define HASH_CR_MODE_Msk          (0x1UL << HASH_CR_MODE_Pos)                  /*!< 0x00000040 */

+#define HASH_CR_MODE              HASH_CR_MODE_Msk

+#define HASH_CR_ALGO_Pos          (7U)

+#define HASH_CR_ALGO_Msk          (0x801UL << HASH_CR_ALGO_Pos)                /*!< 0x00040080 */

+#define HASH_CR_ALGO              HASH_CR_ALGO_Msk

+#define HASH_CR_ALGO_0            (0x001UL << HASH_CR_ALGO_Pos)                 /*!< 0x00000080 */

+#define HASH_CR_ALGO_1            (0x800UL << HASH_CR_ALGO_Pos)                 /*!< 0x00040000 */

+#define HASH_CR_NBW_Pos           (8U)

+#define HASH_CR_NBW_Msk           (0xFUL << HASH_CR_NBW_Pos)                   /*!< 0x00000F00 */

+#define HASH_CR_NBW               HASH_CR_NBW_Msk

+#define HASH_CR_NBW_0             (0x1UL << HASH_CR_NBW_Pos)                    /*!< 0x00000100 */

+#define HASH_CR_NBW_1             (0x2UL << HASH_CR_NBW_Pos)                    /*!< 0x00000200 */

+#define HASH_CR_NBW_2             (0x4UL << HASH_CR_NBW_Pos)                    /*!< 0x00000400 */

+#define HASH_CR_NBW_3             (0x8UL << HASH_CR_NBW_Pos)                    /*!< 0x00000800 */

+#define HASH_CR_DINNE_Pos         (12U)

+#define HASH_CR_DINNE_Msk         (0x1UL << HASH_CR_DINNE_Pos)                 /*!< 0x00001000 */

+#define HASH_CR_DINNE             HASH_CR_DINNE_Msk

+#define HASH_CR_MDMAT_Pos         (13U)

+#define HASH_CR_MDMAT_Msk         (0x1UL << HASH_CR_MDMAT_Pos)                 /*!< 0x00002000 */

+#define HASH_CR_MDMAT             HASH_CR_MDMAT_Msk

+#define HASH_CR_LKEY_Pos          (16U)

+#define HASH_CR_LKEY_Msk          (0x1UL << HASH_CR_LKEY_Pos)                  /*!< 0x00010000 */

+#define HASH_CR_LKEY              HASH_CR_LKEY_Msk

+

+/******************  Bits definition for HASH_STR register  *******************/

+#define HASH_STR_NBLW_Pos         (0U)

+#define HASH_STR_NBLW_Msk         (0x1FUL << HASH_STR_NBLW_Pos)                /*!< 0x0000001F */

+#define HASH_STR_NBLW             HASH_STR_NBLW_Msk

+#define HASH_STR_NBLW_0           (0x01UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000001 */

+#define HASH_STR_NBLW_1           (0x02UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000002 */

+#define HASH_STR_NBLW_2           (0x04UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000004 */

+#define HASH_STR_NBLW_3           (0x08UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000008 */

+#define HASH_STR_NBLW_4           (0x10UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000010 */

+#define HASH_STR_DCAL_Pos         (8U)

+#define HASH_STR_DCAL_Msk         (0x1UL << HASH_STR_DCAL_Pos)                 /*!< 0x00000100 */

+#define HASH_STR_DCAL             HASH_STR_DCAL_Msk

+

+/******************  Bits definition for HASH_IMR register  *******************/

+#define HASH_IMR_DINIE_Pos        (0U)

+#define HASH_IMR_DINIE_Msk        (0x1UL << HASH_IMR_DINIE_Pos)                /*!< 0x00000001 */

+#define HASH_IMR_DINIE            HASH_IMR_DINIE_Msk

+#define HASH_IMR_DCIE_Pos         (1U)

+#define HASH_IMR_DCIE_Msk         (0x1UL << HASH_IMR_DCIE_Pos)                 /*!< 0x00000002 */

+#define HASH_IMR_DCIE             HASH_IMR_DCIE_Msk

+

+/******************  Bits definition for HASH_SR register  ********************/

+#define HASH_SR_DINIS_Pos         (0U)

+#define HASH_SR_DINIS_Msk         (0x1UL << HASH_SR_DINIS_Pos)                 /*!< 0x00000001 */

+#define HASH_SR_DINIS             HASH_SR_DINIS_Msk

+#define HASH_SR_DCIS_Pos          (1U)

+#define HASH_SR_DCIS_Msk          (0x1UL << HASH_SR_DCIS_Pos)                  /*!< 0x00000002 */

+#define HASH_SR_DCIS              HASH_SR_DCIS_Msk

+#define HASH_SR_DMAS_Pos          (2U)

+#define HASH_SR_DMAS_Msk          (0x1UL << HASH_SR_DMAS_Pos)                  /*!< 0x00000004 */

+#define HASH_SR_DMAS              HASH_SR_DMAS_Msk

+#define HASH_SR_BUSY_Pos          (3U)

+#define HASH_SR_BUSY_Msk          (0x1UL << HASH_SR_BUSY_Pos)                  /*!< 0x00000008 */

+#define HASH_SR_BUSY              HASH_SR_BUSY_Msk

+/******************************************************************************/

+/*                                                                            */

+/*                      Inter-integrated Circuit Interface (I2C)              */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for I2C_CR1 register  *******************/

+#define I2C_CR1_PE_Pos               (0U)

+#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */

+#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */

+#define I2C_CR1_TXIE_Pos             (1U)

+#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */

+#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */

+#define I2C_CR1_RXIE_Pos             (2U)

+#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */

+#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */

+#define I2C_CR1_ADDRIE_Pos           (3U)

+#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */

+#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */

+#define I2C_CR1_NACKIE_Pos           (4U)

+#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */

+#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */

+#define I2C_CR1_STOPIE_Pos           (5U)

+#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */

+#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */

+#define I2C_CR1_TCIE_Pos             (6U)

+#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */

+#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */

+#define I2C_CR1_ERRIE_Pos            (7U)

+#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */

+#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */

+#define I2C_CR1_DNF_Pos              (8U)

+#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */

+#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */

+#define I2C_CR1_ANFOFF_Pos           (12U)

+#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */

+#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */

+#define I2C_CR1_TXDMAEN_Pos          (14U)

+#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */

+#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */

+#define I2C_CR1_RXDMAEN_Pos          (15U)

+#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */

+#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */

+#define I2C_CR1_SBC_Pos              (16U)

+#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */

+#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */

+#define I2C_CR1_NOSTRETCH_Pos        (17U)

+#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */

+#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */

+#define I2C_CR1_WUPEN_Pos            (18U)

+#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */

+#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */

+#define I2C_CR1_GCEN_Pos             (19U)

+#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */

+#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */

+#define I2C_CR1_SMBHEN_Pos           (20U)

+#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */

+#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */

+#define I2C_CR1_SMBDEN_Pos           (21U)

+#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */

+#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */

+#define I2C_CR1_ALERTEN_Pos          (22U)

+#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */

+#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */

+#define I2C_CR1_PECEN_Pos            (23U)

+#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */

+#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */

+

+/******************  Bit definition for I2C_CR2 register  ********************/

+#define I2C_CR2_SADD_Pos             (0U)

+#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */

+#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */

+#define I2C_CR2_RD_WRN_Pos           (10U)

+#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */

+#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */

+#define I2C_CR2_ADD10_Pos            (11U)

+#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */

+#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */

+#define I2C_CR2_HEAD10R_Pos          (12U)

+#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */

+#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */

+#define I2C_CR2_START_Pos            (13U)

+#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */

+#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */

+#define I2C_CR2_STOP_Pos             (14U)

+#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */

+#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */

+#define I2C_CR2_NACK_Pos             (15U)

+#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */

+#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */

+#define I2C_CR2_NBYTES_Pos           (16U)

+#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */

+#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */

+#define I2C_CR2_RELOAD_Pos           (24U)

+#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */

+#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */

+#define I2C_CR2_AUTOEND_Pos          (25U)

+#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */

+#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */

+#define I2C_CR2_PECBYTE_Pos          (26U)

+#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */

+#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */

+

+/*******************  Bit definition for I2C_OAR1 register  ******************/

+#define I2C_OAR1_OA1_Pos             (0U)

+#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */

+#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */

+#define I2C_OAR1_OA1MODE_Pos         (10U)

+#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */

+#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */

+#define I2C_OAR1_OA1EN_Pos           (15U)

+#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */

+#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */

+

+/*******************  Bit definition for I2C_OAR2 register  ******************/

+#define I2C_OAR2_OA2_Pos             (1U)

+#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */

+#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */

+#define I2C_OAR2_OA2MSK_Pos          (8U)

+#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */

+#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */

+#define I2C_OAR2_OA2NOMASK           0x00000000UL                              /*!< No mask */

+#define I2C_OAR2_OA2MASK01_Pos       (8U)

+#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */

+#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared */

+#define I2C_OAR2_OA2MASK02_Pos       (9U)

+#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */

+#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */

+#define I2C_OAR2_OA2MASK03_Pos       (8U)

+#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */

+#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */

+#define I2C_OAR2_OA2MASK04_Pos       (10U)

+#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */

+#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */

+#define I2C_OAR2_OA2MASK05_Pos       (8U)

+#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */

+#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */

+#define I2C_OAR2_OA2MASK06_Pos       (9U)

+#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */

+#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared */

+#define I2C_OAR2_OA2MASK07_Pos       (8U)

+#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */

+#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done */

+#define I2C_OAR2_OA2EN_Pos           (15U)

+#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */

+#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */

+

+/*******************  Bit definition for I2C_TIMINGR register *******************/

+#define I2C_TIMINGR_SCLL_Pos         (0U)

+#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */

+#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */

+#define I2C_TIMINGR_SCLH_Pos         (8U)

+#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */

+#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */

+#define I2C_TIMINGR_SDADEL_Pos       (16U)

+#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */

+#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */

+#define I2C_TIMINGR_SCLDEL_Pos       (20U)

+#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */

+#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */

+#define I2C_TIMINGR_PRESC_Pos        (28U)

+#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */

+#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */

+

+/******************* Bit definition for I2C_TIMEOUTR register *******************/

+#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)

+#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */

+#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */

+#define I2C_TIMEOUTR_TIDLE_Pos       (12U)

+#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */

+#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */

+#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)

+#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */

+#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */

+#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)

+#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */

+#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/

+#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)

+#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */

+#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */

+

+/******************  Bit definition for I2C_ISR register  *********************/

+#define I2C_ISR_TXE_Pos              (0U)

+#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */

+#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */

+#define I2C_ISR_TXIS_Pos             (1U)

+#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */

+#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */

+#define I2C_ISR_RXNE_Pos             (2U)

+#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */

+#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */

+#define I2C_ISR_ADDR_Pos             (3U)

+#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */

+#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/

+#define I2C_ISR_NACKF_Pos            (4U)

+#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */

+#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */

+#define I2C_ISR_STOPF_Pos            (5U)

+#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */

+#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */

+#define I2C_ISR_TC_Pos               (6U)

+#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */

+#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */

+#define I2C_ISR_TCR_Pos              (7U)

+#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */

+#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */

+#define I2C_ISR_BERR_Pos             (8U)

+#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */

+#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */

+#define I2C_ISR_ARLO_Pos             (9U)

+#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */

+#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */

+#define I2C_ISR_OVR_Pos              (10U)

+#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */

+#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */

+#define I2C_ISR_PECERR_Pos           (11U)

+#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */

+#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */

+#define I2C_ISR_TIMEOUT_Pos          (12U)

+#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */

+#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */

+#define I2C_ISR_ALERT_Pos            (13U)

+#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */

+#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */

+#define I2C_ISR_BUSY_Pos             (15U)

+#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */

+#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */

+#define I2C_ISR_DIR_Pos              (16U)

+#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */

+#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */

+#define I2C_ISR_ADDCODE_Pos          (17U)

+#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */

+#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */

+

+/******************  Bit definition for I2C_ICR register  *********************/

+#define I2C_ICR_ADDRCF_Pos           (3U)

+#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */

+#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */

+#define I2C_ICR_NACKCF_Pos           (4U)

+#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */

+#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */

+#define I2C_ICR_STOPCF_Pos           (5U)

+#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */

+#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */

+#define I2C_ICR_BERRCF_Pos           (8U)

+#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */

+#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */

+#define I2C_ICR_ARLOCF_Pos           (9U)

+#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */

+#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */

+#define I2C_ICR_OVRCF_Pos            (10U)

+#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */

+#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */

+#define I2C_ICR_PECCF_Pos            (11U)

+#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */

+#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */

+#define I2C_ICR_TIMOUTCF_Pos         (12U)

+#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */

+#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */

+#define I2C_ICR_ALERTCF_Pos          (13U)

+#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */

+#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */

+

+/******************  Bit definition for I2C_PECR register  *********************/

+#define I2C_PECR_PEC_Pos             (0U)

+#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */

+#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */

+

+/******************  Bit definition for I2C_RXDR register  *********************/

+#define I2C_RXDR_RXDATA_Pos          (0U)

+#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */

+#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */

+

+/******************  Bit definition for I2C_TXDR register  *********************/

+#define I2C_TXDR_TXDATA_Pos          (0U)

+#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */

+#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           Independent WATCHDOG                             */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for IWDG_KR register  ********************/

+#define IWDG_KR_KEY_Pos      (0U)

+#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */

+#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */

+

+/*******************  Bit definition for IWDG_PR register  ********************/

+#define IWDG_PR_PR_Pos       (0U)

+#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */

+#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */

+#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */

+#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */

+#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */

+

+/*******************  Bit definition for IWDG_RLR register  *******************/

+#define IWDG_RLR_RL_Pos      (0U)

+#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */

+#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */

+

+/*******************  Bit definition for IWDG_SR register  ********************/

+#define IWDG_SR_PVU_Pos      (0U)

+#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */

+#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */

+#define IWDG_SR_RVU_Pos      (1U)

+#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */

+#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */

+#define IWDG_SR_WVU_Pos      (2U)

+#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */

+#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */

+

+/*******************  Bit definition for IWDG_KR register  ********************/

+#define IWDG_WINR_WIN_Pos    (0U)

+#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */

+#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */

+

+/******************************************************************************/

+/*                                                                            */

+/*                        JPEG Encoder/Decoder                                */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for CONFR0 register  ********************/

+#define JPEG_CONFR0_START_Pos           (0U)

+#define JPEG_CONFR0_START_Msk           (0x1UL << JPEG_CONFR0_START_Pos)       /*!< 0x00000001 */

+#define JPEG_CONFR0_START               JPEG_CONFR0_START_Msk                  /*!<Start/Stop bit */

+

+/********************  Bit definition for CONFR1 register  ********************/

+#define JPEG_CONFR1_NF_Pos              (0U)

+#define JPEG_CONFR1_NF_Msk              (0x3UL << JPEG_CONFR1_NF_Pos)          /*!< 0x00000003 */

+#define JPEG_CONFR1_NF                  JPEG_CONFR1_NF_Msk                     /*!<Number of color components */

+#define JPEG_CONFR1_NF_0                (0x1UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000001 */

+#define JPEG_CONFR1_NF_1                (0x2UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000002 */

+#define JPEG_CONFR1_DE_Pos              (3U)

+#define JPEG_CONFR1_DE_Msk              (0x1UL << JPEG_CONFR1_DE_Pos)          /*!< 0x00000008 */

+#define JPEG_CONFR1_DE                  JPEG_CONFR1_DE_Msk                     /*!<Decoding Enable */

+#define JPEG_CONFR1_COLORSPACE_Pos      (4U)

+#define JPEG_CONFR1_COLORSPACE_Msk      (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)  /*!< 0x00000030 */

+#define JPEG_CONFR1_COLORSPACE          JPEG_CONFR1_COLORSPACE_Msk             /*!<Color Space */

+#define JPEG_CONFR1_COLORSPACE_0        (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000010 */

+#define JPEG_CONFR1_COLORSPACE_1        (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000020 */

+#define JPEG_CONFR1_NS_Pos              (6U)

+#define JPEG_CONFR1_NS_Msk              (0x3UL << JPEG_CONFR1_NS_Pos)          /*!< 0x000000C0 */

+#define JPEG_CONFR1_NS                  JPEG_CONFR1_NS_Msk                     /*!<Number of components for Scan */

+#define JPEG_CONFR1_NS_0                (0x1UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR1_NS_1                (0x2UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR1_HDR_Pos             (8U)

+#define JPEG_CONFR1_HDR_Msk             (0x1UL << JPEG_CONFR1_HDR_Pos)         /*!< 0x00000100 */

+#define JPEG_CONFR1_HDR                 JPEG_CONFR1_HDR_Msk                    /*!<Header Processing On/Off */

+#define JPEG_CONFR1_YSIZE_Pos           (16U)

+#define JPEG_CONFR1_YSIZE_Msk           (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)    /*!< 0xFFFF0000 */

+#define JPEG_CONFR1_YSIZE               JPEG_CONFR1_YSIZE_Msk                  /*!<Number of lines in source image */

+

+/********************  Bit definition for CONFR2 register  ********************/

+#define JPEG_CONFR2_NMCU_Pos            (0U)

+#define JPEG_CONFR2_NMCU_Msk            (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)  /*!< 0x03FFFFFF */

+#define JPEG_CONFR2_NMCU                JPEG_CONFR2_NMCU_Msk                   /*!<Number of MCU units minus 1 to encode */

+

+/********************  Bit definition for CONFR3 register  ********************/

+#define JPEG_CONFR3_XSIZE_Pos           (16U)

+#define JPEG_CONFR3_XSIZE_Msk           (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)    /*!< 0xFFFF0000 */

+#define JPEG_CONFR3_XSIZE               JPEG_CONFR3_XSIZE_Msk                  /*!<Number of pixels per line */

+

+/********************  Bit definition for CONFR4 register  ********************/

+#define JPEG_CONFR4_HD_Pos              (0U)

+#define JPEG_CONFR4_HD_Msk              (0x1UL << JPEG_CONFR4_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR4_HD                  JPEG_CONFR4_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR4_HA_Pos              (1U)

+#define JPEG_CONFR4_HA_Msk              (0x1UL << JPEG_CONFR4_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR4_HA                  JPEG_CONFR4_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR4_QT_Pos              (2U)

+#define JPEG_CONFR4_QT_Msk              (0x3UL << JPEG_CONFR4_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR4_QT                  JPEG_CONFR4_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR4_QT_0                (0x1UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR4_QT_1                (0x2UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR4_NB_Pos              (4U)

+#define JPEG_CONFR4_NB_Msk              (0xFUL << JPEG_CONFR4_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR4_NB                  JPEG_CONFR4_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR4_NB_0                (0x1UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR4_NB_1                (0x2UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR4_NB_2                (0x4UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR4_NB_3                (0x8UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR4_VSF_Pos             (8U)

+#define JPEG_CONFR4_VSF_Msk             (0xFUL << JPEG_CONFR4_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR4_VSF                 JPEG_CONFR4_VSF_Msk                    /*!<Vertical sampling factor for component 1 */

+#define JPEG_CONFR4_VSF_0               (0x1UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR4_VSF_1               (0x2UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR4_VSF_2               (0x4UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR4_VSF_3               (0x8UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR4_HSF_Pos             (12U)

+#define JPEG_CONFR4_HSF_Msk             (0xFUL << JPEG_CONFR4_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR4_HSF                 JPEG_CONFR4_HSF_Msk                    /*!<Horizontal sampling factor for component 1 */

+#define JPEG_CONFR4_HSF_0               (0x1UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR4_HSF_1               (0x2UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR4_HSF_2               (0x4UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR4_HSF_3               (0x8UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR5 register  ********************/

+#define JPEG_CONFR5_HD_Pos              (0U)

+#define JPEG_CONFR5_HD_Msk              (0x1UL << JPEG_CONFR5_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR5_HD                  JPEG_CONFR5_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR5_HA_Pos              (1U)

+#define JPEG_CONFR5_HA_Msk              (0x1UL << JPEG_CONFR5_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR5_HA                  JPEG_CONFR5_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR5_QT_Pos              (2U)

+#define JPEG_CONFR5_QT_Msk              (0x3UL << JPEG_CONFR5_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR5_QT                  JPEG_CONFR5_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR5_QT_0                (0x1UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR5_QT_1                (0x2UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR5_NB_Pos              (4U)

+#define JPEG_CONFR5_NB_Msk              (0xFUL << JPEG_CONFR5_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR5_NB                  JPEG_CONFR5_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR5_NB_0                (0x1UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR5_NB_1                (0x2UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR5_NB_2                (0x4UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR5_NB_3                (0x8UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR5_VSF_Pos             (8U)

+#define JPEG_CONFR5_VSF_Msk             (0xFUL << JPEG_CONFR5_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR5_VSF                 JPEG_CONFR5_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR5_VSF_0               (0x1UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR5_VSF_1               (0x2UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR5_VSF_2               (0x4UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR5_VSF_3               (0x8UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR5_HSF_Pos             (12U)

+#define JPEG_CONFR5_HSF_Msk             (0xFUL << JPEG_CONFR5_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR5_HSF                 JPEG_CONFR5_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR5_HSF_0               (0x1UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR5_HSF_1               (0x2UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR5_HSF_2               (0x4UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR5_HSF_3               (0x8UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR6 register  ********************/

+#define JPEG_CONFR6_HD_Pos              (0U)

+#define JPEG_CONFR6_HD_Msk              (0x1UL << JPEG_CONFR6_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR6_HD                  JPEG_CONFR6_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR6_HA_Pos              (1U)

+#define JPEG_CONFR6_HA_Msk              (0x1UL << JPEG_CONFR6_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR6_HA                  JPEG_CONFR6_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR6_QT_Pos              (2U)

+#define JPEG_CONFR6_QT_Msk              (0x3UL << JPEG_CONFR6_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR6_QT                  JPEG_CONFR6_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR6_QT_0                (0x1UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR6_QT_1                (0x2UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR6_NB_Pos              (4U)

+#define JPEG_CONFR6_NB_Msk              (0xFUL << JPEG_CONFR6_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR6_NB                  JPEG_CONFR6_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR6_NB_0                (0x1UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR6_NB_1                (0x2UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR6_NB_2                (0x4UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR6_NB_3                (0x8UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR6_VSF_Pos             (8U)

+#define JPEG_CONFR6_VSF_Msk             (0xFUL << JPEG_CONFR6_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR6_VSF                 JPEG_CONFR6_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR6_VSF_0               (0x1UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR6_VSF_1               (0x2UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR6_VSF_2               (0x4UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR6_VSF_3               (0x8UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR6_HSF_Pos             (12U)

+#define JPEG_CONFR6_HSF_Msk             (0xFUL << JPEG_CONFR6_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR6_HSF                 JPEG_CONFR6_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR6_HSF_0               (0x1UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR6_HSF_1               (0x2UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR6_HSF_2               (0x4UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR6_HSF_3               (0x8UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR7 register  ********************/

+#define JPEG_CONFR7_HD_Pos              (0U)

+#define JPEG_CONFR7_HD_Msk              (0x1UL << JPEG_CONFR7_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR7_HD                  JPEG_CONFR7_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR7_HA_Pos              (1U)

+#define JPEG_CONFR7_HA_Msk              (0x1UL << JPEG_CONFR7_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR7_HA                  JPEG_CONFR7_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR7_QT_Pos              (2U)

+#define JPEG_CONFR7_QT_Msk              (0x3UL << JPEG_CONFR7_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR7_QT                  JPEG_CONFR7_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR7_QT_0                (0x1UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR7_QT_1                (0x2UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR7_NB_Pos              (4U)

+#define JPEG_CONFR7_NB_Msk              (0xFUL << JPEG_CONFR7_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR7_NB                  JPEG_CONFR7_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR7_NB_0                (0x1UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR7_NB_1                (0x2UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR7_NB_2                (0x4UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR7_NB_3                (0x8UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR7_VSF_Pos             (8U)

+#define JPEG_CONFR7_VSF_Msk             (0xFUL << JPEG_CONFR7_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR7_VSF                 JPEG_CONFR7_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR7_VSF_0               (0x1UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR7_VSF_1               (0x2UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR7_VSF_2               (0x4UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR7_VSF_3               (0x8UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR7_HSF_Pos             (12U)

+#define JPEG_CONFR7_HSF_Msk             (0xFUL << JPEG_CONFR7_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR7_HSF                 JPEG_CONFR7_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR7_HSF_0               (0x1UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR7_HSF_1               (0x2UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR7_HSF_2               (0x4UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR7_HSF_3               (0x8UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CR register  ********************/

+#define JPEG_CR_JCEN_Pos                (0U)

+#define JPEG_CR_JCEN_Msk                (0x1UL << JPEG_CR_JCEN_Pos)            /*!< 0x00000001 */

+#define JPEG_CR_JCEN                    JPEG_CR_JCEN_Msk                       /*!<Enable the JPEG Codec Core */

+#define JPEG_CR_IFTIE_Pos               (1U)

+#define JPEG_CR_IFTIE_Msk               (0x1UL << JPEG_CR_IFTIE_Pos)           /*!< 0x00000002 */

+#define JPEG_CR_IFTIE                   JPEG_CR_IFTIE_Msk                      /*!<Input FIFO Threshold Interrupt Enable */

+#define JPEG_CR_IFNFIE_Pos              (2U)

+#define JPEG_CR_IFNFIE_Msk              (0x1UL << JPEG_CR_IFNFIE_Pos)          /*!< 0x00000004 */

+#define JPEG_CR_IFNFIE                  JPEG_CR_IFNFIE_Msk                     /*!<Input FIFO Not Full Interrupt Enable */

+#define JPEG_CR_OFTIE_Pos               (3U)

+#define JPEG_CR_OFTIE_Msk               (0x1UL << JPEG_CR_OFTIE_Pos)           /*!< 0x00000008 */

+#define JPEG_CR_OFTIE                   JPEG_CR_OFTIE_Msk                      /*!<Output FIFO Threshold Interrupt Enable */

+#define JPEG_CR_OFNEIE_Pos              (4U)

+#define JPEG_CR_OFNEIE_Msk              (0x1UL << JPEG_CR_OFNEIE_Pos)          /*!< 0x00000010 */

+#define JPEG_CR_OFNEIE                  JPEG_CR_OFNEIE_Msk                     /*!<Output FIFO Not Empty Interrupt Enable */

+#define JPEG_CR_EOCIE_Pos               (5U)

+#define JPEG_CR_EOCIE_Msk               (0x1UL << JPEG_CR_EOCIE_Pos)           /*!< 0x00000020 */

+#define JPEG_CR_EOCIE                   JPEG_CR_EOCIE_Msk                      /*!<End of Conversion Interrupt Enable */

+#define JPEG_CR_HPDIE_Pos               (6U)

+#define JPEG_CR_HPDIE_Msk               (0x1UL << JPEG_CR_HPDIE_Pos)           /*!< 0x00000040 */

+#define JPEG_CR_HPDIE                   JPEG_CR_HPDIE_Msk                      /*!<Header Parsing Done Interrupt Enable */

+#define JPEG_CR_IFF_Pos                 (13U)

+#define JPEG_CR_IFF_Msk                 (0x1UL << JPEG_CR_IFF_Pos)             /*!< 0x00002000 */

+#define JPEG_CR_IFF                     JPEG_CR_IFF_Msk                        /*!<Flush the input FIFO */

+#define JPEG_CR_OFF_Pos                 (14U)

+#define JPEG_CR_OFF_Msk                 (0x1UL << JPEG_CR_OFF_Pos)             /*!< 0x00004000 */

+#define JPEG_CR_OFF                     JPEG_CR_OFF_Msk                        /*!<Flush the output FIFO */

+

+/********************  Bit definition for SR register  ********************/

+#define JPEG_SR_IFTF_Pos                (1U)

+#define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */

+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is bellow its threshold flag */

+#define JPEG_SR_IFNFF_Pos               (2U)

+#define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */

+#define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */

+#define JPEG_SR_OFTF_Pos                (3U)

+#define JPEG_SR_OFTF_Msk                (0x1UL << JPEG_SR_OFTF_Pos)            /*!< 0x00000008 */

+#define JPEG_SR_OFTF                    JPEG_SR_OFTF_Msk                       /*!<Output FIFO is not empty and has reach its threshold */

+#define JPEG_SR_OFNEF_Pos               (4U)

+#define JPEG_SR_OFNEF_Msk               (0x1UL << JPEG_SR_OFNEF_Pos)           /*!< 0x00000010 */

+#define JPEG_SR_OFNEF                   JPEG_SR_OFNEF_Msk                      /*!<Output FIFO is not empty, a data is available */

+#define JPEG_SR_EOCF_Pos                (5U)

+#define JPEG_SR_EOCF_Msk                (0x1UL << JPEG_SR_EOCF_Pos)            /*!< 0x00000020 */

+#define JPEG_SR_EOCF                    JPEG_SR_EOCF_Msk                       /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */

+#define JPEG_SR_HPDF_Pos                (6U)

+#define JPEG_SR_HPDF_Msk                (0x1UL << JPEG_SR_HPDF_Pos)            /*!< 0x00000040 */

+#define JPEG_SR_HPDF                    JPEG_SR_HPDF_Msk                       /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */

+#define JPEG_SR_COF_Pos                 (7U)

+#define JPEG_SR_COF_Msk                 (0x1UL << JPEG_SR_COF_Pos)             /*!< 0x00000080 */

+#define JPEG_SR_COF                     JPEG_SR_COF_Msk                        /*!<JPEG Codec operation on going flag */

+

+/********************  Bit definition for CFR register  ********************/

+#define JPEG_CFR_CEOCF_Pos              (4U)

+#define JPEG_CFR_CEOCF_Msk              (0x1UL << JPEG_CFR_CEOCF_Pos)          /*!< 0x00000010 */

+#define JPEG_CFR_CEOCF                  JPEG_CFR_CEOCF_Msk                     /*!<Clear End of Conversion Flag */

+#define JPEG_CFR_CHPDF_Pos              (5U)

+#define JPEG_CFR_CHPDF_Msk              (0x1UL << JPEG_CFR_CHPDF_Pos)          /*!< 0x00000020 */

+#define JPEG_CFR_CHPDF                  JPEG_CFR_CHPDF_Msk                     /*!<Clear Header Parsing Done Flag */

+

+/********************  Bit definition for DIR register  ********************/

+#define JPEG_DIR_DATAIN_Pos             (0U)

+#define JPEG_DIR_DATAIN_Msk             (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)  /*!< 0xFFFFFFFF */

+#define JPEG_DIR_DATAIN                 JPEG_DIR_DATAIN_Msk                    /*!<Data Input FIFO */

+

+/********************  Bit definition for DOR register  ********************/

+#define JPEG_DOR_DATAOUT_Pos            (0U)

+#define JPEG_DOR_DATAOUT_Msk            (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */

+#define JPEG_DOR_DATAOUT                JPEG_DOR_DATAOUT_Msk                   /*!<Data Output FIFO */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      LCD-TFT Display Controller (LTDC)                     */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for LTDC_SSCR register  *****************/

+

+#define LTDC_SSCR_VSH_Pos            (0U)

+#define LTDC_SSCR_VSH_Msk            (0x7FFUL << LTDC_SSCR_VSH_Pos)            /*!< 0x000007FF */

+#define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height  */

+#define LTDC_SSCR_HSW_Pos            (16U)

+#define LTDC_SSCR_HSW_Msk            (0xFFFUL << LTDC_SSCR_HSW_Pos)            /*!< 0x0FFF0000 */

+#define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */

+

+/********************  Bit definition for LTDC_BPCR register  *****************/

+

+#define LTDC_BPCR_AVBP_Pos           (0U)

+#define LTDC_BPCR_AVBP_Msk           (0x7FFUL << LTDC_BPCR_AVBP_Pos)           /*!< 0x000007FF */

+#define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch   */

+#define LTDC_BPCR_AHBP_Pos           (16U)

+#define LTDC_BPCR_AHBP_Msk           (0xFFFUL << LTDC_BPCR_AHBP_Pos)           /*!< 0x0FFF0000 */

+#define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */

+

+/********************  Bit definition for LTDC_AWCR register  *****************/

+

+#define LTDC_AWCR_AAH_Pos            (0U)

+#define LTDC_AWCR_AAH_Msk            (0x7FFUL << LTDC_AWCR_AAH_Pos)            /*!< 0x000007FF */

+#define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active heigh */

+#define LTDC_AWCR_AAW_Pos            (16U)

+#define LTDC_AWCR_AAW_Msk            (0xFFFUL << LTDC_AWCR_AAW_Pos)            /*!< 0x0FFF0000 */

+#define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */

+

+/********************  Bit definition for LTDC_TWCR register  *****************/

+

+#define LTDC_TWCR_TOTALH_Pos         (0U)

+#define LTDC_TWCR_TOTALH_Msk         (0x7FFUL << LTDC_TWCR_TOTALH_Pos)         /*!< 0x000007FF */

+#define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total Heigh */

+#define LTDC_TWCR_TOTALW_Pos         (16U)

+#define LTDC_TWCR_TOTALW_Msk         (0xFFFUL << LTDC_TWCR_TOTALW_Pos)         /*!< 0x0FFF0000 */

+#define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */

+

+/********************  Bit definition for LTDC_GCR register  ******************/

+

+#define LTDC_GCR_LTDCEN_Pos          (0U)

+#define LTDC_GCR_LTDCEN_Msk          (0x1UL << LTDC_GCR_LTDCEN_Pos)            /*!< 0x00000001 */

+#define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit       */

+#define LTDC_GCR_DBW_Pos             (4U)

+#define LTDC_GCR_DBW_Msk             (0x7UL << LTDC_GCR_DBW_Pos)               /*!< 0x00000070 */

+#define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width                   */

+#define LTDC_GCR_DGW_Pos             (8U)

+#define LTDC_GCR_DGW_Msk             (0x7UL << LTDC_GCR_DGW_Pos)               /*!< 0x00000700 */

+#define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width                  */

+#define LTDC_GCR_DRW_Pos             (12U)

+#define LTDC_GCR_DRW_Msk             (0x7UL << LTDC_GCR_DRW_Pos)               /*!< 0x00007000 */

+#define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width                    */

+#define LTDC_GCR_DEN_Pos             (16U)

+#define LTDC_GCR_DEN_Msk             (0x1UL << LTDC_GCR_DEN_Pos)               /*!< 0x00010000 */

+#define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable                       */

+#define LTDC_GCR_PCPOL_Pos           (28U)

+#define LTDC_GCR_PCPOL_Msk           (0x1UL << LTDC_GCR_PCPOL_Pos)             /*!< 0x10000000 */

+#define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity                */

+#define LTDC_GCR_DEPOL_Pos           (29U)

+#define LTDC_GCR_DEPOL_Msk           (0x1UL << LTDC_GCR_DEPOL_Pos)             /*!< 0x20000000 */

+#define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity                */

+#define LTDC_GCR_VSPOL_Pos           (30U)

+#define LTDC_GCR_VSPOL_Msk           (0x1UL << LTDC_GCR_VSPOL_Pos)             /*!< 0x40000000 */

+#define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity   */

+#define LTDC_GCR_HSPOL_Pos           (31U)

+#define LTDC_GCR_HSPOL_Msk           (0x1UL << LTDC_GCR_HSPOL_Pos)             /*!< 0x80000000 */

+#define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */

+

+

+/********************  Bit definition for LTDC_SRCR register  *****************/

+

+#define LTDC_SRCR_IMR_Pos            (0U)

+#define LTDC_SRCR_IMR_Msk            (0x1UL << LTDC_SRCR_IMR_Pos)              /*!< 0x00000001 */

+#define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload         */

+#define LTDC_SRCR_VBR_Pos            (1U)

+#define LTDC_SRCR_VBR_Msk            (0x1UL << LTDC_SRCR_VBR_Pos)              /*!< 0x00000002 */

+#define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */

+

+/********************  Bit definition for LTDC_BCCR register  *****************/

+

+#define LTDC_BCCR_BCBLUE_Pos         (0U)

+#define LTDC_BCCR_BCBLUE_Msk         (0xFFUL << LTDC_BCCR_BCBLUE_Pos)          /*!< 0x000000FF */

+#define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value  */

+#define LTDC_BCCR_BCGREEN_Pos        (8U)

+#define LTDC_BCCR_BCGREEN_Msk        (0xFFUL << LTDC_BCCR_BCGREEN_Pos)         /*!< 0x0000FF00 */

+#define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */

+#define LTDC_BCCR_BCRED_Pos          (16U)

+#define LTDC_BCCR_BCRED_Msk          (0xFFUL << LTDC_BCCR_BCRED_Pos)           /*!< 0x00FF0000 */

+#define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value   */

+

+/********************  Bit definition for LTDC_IER register  ******************/

+

+#define LTDC_IER_LIE_Pos             (0U)

+#define LTDC_IER_LIE_Msk             (0x1UL << LTDC_IER_LIE_Pos)               /*!< 0x00000001 */

+#define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable            */

+#define LTDC_IER_FUIE_Pos            (1U)

+#define LTDC_IER_FUIE_Msk            (0x1UL << LTDC_IER_FUIE_Pos)              /*!< 0x00000002 */

+#define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable   */

+#define LTDC_IER_TERRIE_Pos          (2U)

+#define LTDC_IER_TERRIE_Msk          (0x1UL << LTDC_IER_TERRIE_Pos)            /*!< 0x00000004 */

+#define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable  */

+#define LTDC_IER_RRIE_Pos            (3U)

+#define LTDC_IER_RRIE_Msk            (0x1UL << LTDC_IER_RRIE_Pos)              /*!< 0x00000008 */

+#define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */

+

+/********************  Bit definition for LTDC_ISR register  ******************/

+

+#define LTDC_ISR_LIF_Pos             (0U)

+#define LTDC_ISR_LIF_Msk             (0x1UL << LTDC_ISR_LIF_Pos)               /*!< 0x00000001 */

+#define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */

+#define LTDC_ISR_FUIF_Pos            (1U)

+#define LTDC_ISR_FUIF_Msk            (0x1UL << LTDC_ISR_FUIF_Pos)              /*!< 0x00000002 */

+#define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */

+#define LTDC_ISR_TERRIF_Pos          (2U)

+#define LTDC_ISR_TERRIF_Msk          (0x1UL << LTDC_ISR_TERRIF_Pos)            /*!< 0x00000004 */

+#define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */

+#define LTDC_ISR_RRIF_Pos            (3U)

+#define LTDC_ISR_RRIF_Msk            (0x1UL << LTDC_ISR_RRIF_Pos)              /*!< 0x00000008 */

+#define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */

+

+/********************  Bit definition for LTDC_ICR register  ******************/

+

+#define LTDC_ICR_CLIF_Pos            (0U)

+#define LTDC_ICR_CLIF_Msk            (0x1UL << LTDC_ICR_CLIF_Pos)              /*!< 0x00000001 */

+#define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */

+#define LTDC_ICR_CFUIF_Pos           (1U)

+#define LTDC_ICR_CFUIF_Msk           (0x1UL << LTDC_ICR_CFUIF_Pos)             /*!< 0x00000002 */

+#define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */

+#define LTDC_ICR_CTERRIF_Pos         (2U)

+#define LTDC_ICR_CTERRIF_Msk         (0x1UL << LTDC_ICR_CTERRIF_Pos)           /*!< 0x00000004 */

+#define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */

+#define LTDC_ICR_CRRIF_Pos           (3U)

+#define LTDC_ICR_CRRIF_Msk           (0x1UL << LTDC_ICR_CRRIF_Pos)             /*!< 0x00000008 */

+#define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */

+

+/********************  Bit definition for LTDC_LIPCR register  ****************/

+

+#define LTDC_LIPCR_LIPOS_Pos         (0U)

+#define LTDC_LIPCR_LIPOS_Msk         (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)         /*!< 0x000007FF */

+#define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */

+

+/********************  Bit definition for LTDC_CPSR register  *****************/

+

+#define LTDC_CPSR_CYPOS_Pos          (0U)

+#define LTDC_CPSR_CYPOS_Msk          (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)         /*!< 0x0000FFFF */

+#define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */

+#define LTDC_CPSR_CXPOS_Pos          (16U)

+#define LTDC_CPSR_CXPOS_Msk          (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)         /*!< 0xFFFF0000 */

+#define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */

+

+/********************  Bit definition for LTDC_CDSR register  *****************/

+

+#define LTDC_CDSR_VDES_Pos           (0U)

+#define LTDC_CDSR_VDES_Msk           (0x1UL << LTDC_CDSR_VDES_Pos)             /*!< 0x00000001 */

+#define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status       */

+#define LTDC_CDSR_HDES_Pos           (1U)

+#define LTDC_CDSR_HDES_Msk           (0x1UL << LTDC_CDSR_HDES_Pos)             /*!< 0x00000002 */

+#define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status     */

+#define LTDC_CDSR_VSYNCS_Pos         (2U)

+#define LTDC_CDSR_VSYNCS_Msk         (0x1UL << LTDC_CDSR_VSYNCS_Pos)           /*!< 0x00000004 */

+#define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status   */

+#define LTDC_CDSR_HSYNCS_Pos         (3U)

+#define LTDC_CDSR_HSYNCS_Msk         (0x1UL << LTDC_CDSR_HSYNCS_Pos)           /*!< 0x00000008 */

+#define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */

+

+/********************  Bit definition for LTDC_LxCR register  *****************/

+

+#define LTDC_LxCR_LEN_Pos            (0U)

+#define LTDC_LxCR_LEN_Msk            (0x1UL << LTDC_LxCR_LEN_Pos)              /*!< 0x00000001 */

+#define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable              */

+#define LTDC_LxCR_COLKEN_Pos         (1U)

+#define LTDC_LxCR_COLKEN_Msk         (0x1UL << LTDC_LxCR_COLKEN_Pos)           /*!< 0x00000002 */

+#define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable       */

+#define LTDC_LxCR_CLUTEN_Pos         (4U)

+#define LTDC_LxCR_CLUTEN_Msk         (0x1UL << LTDC_LxCR_CLUTEN_Pos)           /*!< 0x00000010 */

+#define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */

+

+/********************  Bit definition for LTDC_LxWHPCR register  **************/

+

+#define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)

+#define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)     /*!< 0x00000FFF */

+#define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */

+#define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)

+#define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)    /*!< 0xFFFF0000 */

+#define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position  */

+

+/********************  Bit definition for LTDC_LxWVPCR register  **************/

+

+#define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)

+#define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)     /*!< 0x00000FFF */

+#define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */

+#define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)

+#define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)    /*!< 0xFFFF0000 */

+#define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position  */

+

+/********************  Bit definition for LTDC_LxCKCR register  ***************/

+

+#define LTDC_LxCKCR_CKBLUE_Pos       (0U)

+#define LTDC_LxCKCR_CKBLUE_Msk       (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value  */

+#define LTDC_LxCKCR_CKGREEN_Pos      (8U)

+#define LTDC_LxCKCR_CKGREEN_Msk      (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */

+#define LTDC_LxCKCR_CKRED_Pos        (16U)

+#define LTDC_LxCKCR_CKRED_Msk        (0xFFUL << LTDC_LxCKCR_CKRED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value   */

+

+/********************  Bit definition for LTDC_LxPFCR register  ***************/

+

+#define LTDC_LxPFCR_PF_Pos           (0U)

+#define LTDC_LxPFCR_PF_Msk           (0x7UL << LTDC_LxPFCR_PF_Pos)             /*!< 0x00000007 */

+#define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */

+

+/********************  Bit definition for LTDC_LxCACR register  ***************/

+

+#define LTDC_LxCACR_CONSTA_Pos       (0U)

+#define LTDC_LxCACR_CONSTA_Msk       (0xFFUL << LTDC_LxCACR_CONSTA_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */

+

+/********************  Bit definition for LTDC_LxDCCR register  ***************/

+

+#define LTDC_LxDCCR_DCBLUE_Pos       (0U)

+#define LTDC_LxDCCR_DCBLUE_Msk       (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue  */

+#define LTDC_LxDCCR_DCGREEN_Pos      (8U)

+#define LTDC_LxDCCR_DCGREEN_Msk      (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */

+#define LTDC_LxDCCR_DCRED_Pos        (16U)

+#define LTDC_LxDCCR_DCRED_Msk        (0xFFUL << LTDC_LxDCCR_DCRED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red   */

+#define LTDC_LxDCCR_DCALPHA_Pos      (24U)

+#define LTDC_LxDCCR_DCALPHA_Msk      (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)       /*!< 0xFF000000 */

+#define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */

+

+/********************  Bit definition for LTDC_LxBFCR register  ***************/

+

+#define LTDC_LxBFCR_BF2_Pos          (0U)

+#define LTDC_LxBFCR_BF2_Msk          (0x7UL << LTDC_LxBFCR_BF2_Pos)            /*!< 0x00000007 */

+#define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */

+#define LTDC_LxBFCR_BF1_Pos          (8U)

+#define LTDC_LxBFCR_BF1_Msk          (0x7UL << LTDC_LxBFCR_BF1_Pos)            /*!< 0x00000700 */

+#define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */

+

+/********************  Bit definition for LTDC_LxCFBAR register  **************/

+

+#define LTDC_LxCFBAR_CFBADD_Pos      (0U)

+#define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */

+#define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */

+

+/********************  Bit definition for LTDC_LxCFBLR register  **************/

+

+#define LTDC_LxCFBLR_CFBLL_Pos       (0U)

+#define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)      /*!< 0x00001FFF */

+#define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length    */

+#define LTDC_LxCFBLR_CFBP_Pos        (16U)

+#define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)       /*!< 0x1FFF0000 */

+#define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */

+

+/********************  Bit definition for LTDC_LxCFBLNR register  *************/

+

+#define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)

+#define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)    /*!< 0x000007FF */

+#define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */

+

+/********************  Bit definition for LTDC_LxCLUTWR register  *************/

+

+#define LTDC_LxCLUTWR_BLUE_Pos       (0U)

+#define LTDC_LxCLUTWR_BLUE_Msk       (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value   */

+#define LTDC_LxCLUTWR_GREEN_Pos      (8U)

+#define LTDC_LxCLUTWR_GREEN_Msk      (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value  */

+#define LTDC_LxCLUTWR_RED_Pos        (16U)

+#define LTDC_LxCLUTWR_RED_Msk        (0xFFUL << LTDC_LxCLUTWR_RED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value    */

+#define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)

+#define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)     /*!< 0xFF000000 */

+#define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                     MDMA                                   */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for MDMA_GISR0 register  ****************/

+#define MDMA_GISR0_GIF0_Pos       (0U)

+#define MDMA_GISR0_GIF0_Msk       (0x1UL << MDMA_GISR0_GIF0_Pos)               /*!< 0x00000001 */

+#define MDMA_GISR0_GIF0           MDMA_GISR0_GIF0_Msk                          /*!< Channel 0 global interrupt flag */

+#define MDMA_GISR0_GIF1_Pos       (1U)

+#define MDMA_GISR0_GIF1_Msk       (0x1UL << MDMA_GISR0_GIF1_Pos)               /*!< 0x00000002 */

+#define MDMA_GISR0_GIF1           MDMA_GISR0_GIF1_Msk                          /*!< Channel 1 global interrupt flag */

+#define MDMA_GISR0_GIF2_Pos       (2U)

+#define MDMA_GISR0_GIF2_Msk       (0x1UL << MDMA_GISR0_GIF2_Pos)               /*!< 0x00000004 */

+#define MDMA_GISR0_GIF2           MDMA_GISR0_GIF2_Msk                          /*!< Channel 2 global interrupt flag */

+#define MDMA_GISR0_GIF3_Pos       (3U)

+#define MDMA_GISR0_GIF3_Msk       (0x1UL << MDMA_GISR0_GIF3_Pos)               /*!< 0x00000008 */

+#define MDMA_GISR0_GIF3           MDMA_GISR0_GIF3_Msk                          /*!< Channel 3 global interrupt flag */

+#define MDMA_GISR0_GIF4_Pos       (4U)

+#define MDMA_GISR0_GIF4_Msk       (0x1UL << MDMA_GISR0_GIF4_Pos)               /*!< 0x00000010 */

+#define MDMA_GISR0_GIF4           MDMA_GISR0_GIF4_Msk                          /*!< Channel 4 global interrupt flag */

+#define MDMA_GISR0_GIF5_Pos       (5U)

+#define MDMA_GISR0_GIF5_Msk       (0x1UL << MDMA_GISR0_GIF5_Pos)               /*!< 0x00000020 */

+#define MDMA_GISR0_GIF5           MDMA_GISR0_GIF5_Msk                          /*!< Channel 5 global interrupt flag */

+#define MDMA_GISR0_GIF6_Pos       (6U)

+#define MDMA_GISR0_GIF6_Msk       (0x1UL << MDMA_GISR0_GIF6_Pos)               /*!< 0x00000040 */

+#define MDMA_GISR0_GIF6           MDMA_GISR0_GIF6_Msk                          /*!< Channel 6 global interrupt flag */

+#define MDMA_GISR0_GIF7_Pos       (7U)

+#define MDMA_GISR0_GIF7_Msk       (0x1UL << MDMA_GISR0_GIF7_Pos)               /*!< 0x00000080 */

+#define MDMA_GISR0_GIF7           MDMA_GISR0_GIF7_Msk                          /*!< Channel 7 global interrupt flag */

+#define MDMA_GISR0_GIF8_Pos       (8U)

+#define MDMA_GISR0_GIF8_Msk       (0x1UL << MDMA_GISR0_GIF8_Pos)               /*!< 0x00000100 */

+#define MDMA_GISR0_GIF8           MDMA_GISR0_GIF8_Msk                          /*!< Channel 8 global interrupt flag */

+#define MDMA_GISR0_GIF9_Pos       (9U)

+#define MDMA_GISR0_GIF9_Msk       (0x1UL << MDMA_GISR0_GIF9_Pos)               /*!< 0x00000200 */

+#define MDMA_GISR0_GIF9           MDMA_GISR0_GIF9_Msk                          /*!< Channel 9 global interrupt flag */

+#define MDMA_GISR0_GIF10_Pos      (10U)

+#define MDMA_GISR0_GIF10_Msk      (0x1UL << MDMA_GISR0_GIF10_Pos)              /*!< 0x00000400 */

+#define MDMA_GISR0_GIF10          MDMA_GISR0_GIF10_Msk                         /*!< Channel 10 global interrupt flag */

+#define MDMA_GISR0_GIF11_Pos      (11U)

+#define MDMA_GISR0_GIF11_Msk      (0x1UL << MDMA_GISR0_GIF11_Pos)              /*!< 0x00000800 */

+#define MDMA_GISR0_GIF11          MDMA_GISR0_GIF11_Msk                         /*!< Channel 11 global interrupt flag */

+#define MDMA_GISR0_GIF12_Pos      (12U)

+#define MDMA_GISR0_GIF12_Msk      (0x1UL << MDMA_GISR0_GIF12_Pos)              /*!< 0x00001000 */

+#define MDMA_GISR0_GIF12          MDMA_GISR0_GIF12_Msk                         /*!< Channel 12 global interrupt flag */

+#define MDMA_GISR0_GIF13_Pos      (13U)

+#define MDMA_GISR0_GIF13_Msk      (0x1UL << MDMA_GISR0_GIF13_Pos)              /*!< 0x00002000 */

+#define MDMA_GISR0_GIF13          MDMA_GISR0_GIF13_Msk                         /*!< Channel 13 global interrupt flag */

+#define MDMA_GISR0_GIF14_Pos      (14U)

+#define MDMA_GISR0_GIF14_Msk      (0x1UL << MDMA_GISR0_GIF14_Pos)              /*!< 0x00004000 */

+#define MDMA_GISR0_GIF14          MDMA_GISR0_GIF14_Msk                         /*!< Channel 14 global interrupt flag */

+#define MDMA_GISR0_GIF15_Pos      (15U)

+#define MDMA_GISR0_GIF15_Msk      (0x1UL << MDMA_GISR0_GIF15_Pos)              /*!< 0x00008000 */

+#define MDMA_GISR0_GIF15          MDMA_GISR0_GIF15_Msk                         /*!< Channel 15 global interrupt flag */

+

+/********************  Bit definition for MDMA_CxISR register  ****************/

+#define MDMA_CISR_TEIF_Pos        (0U)

+#define MDMA_CISR_TEIF_Msk        (0x1UL << MDMA_CISR_TEIF_Pos)                /*!< 0x00000001 */

+#define MDMA_CISR_TEIF            MDMA_CISR_TEIF_Msk                           /*!< Channel x transfer error interrupt flag */

+#define MDMA_CISR_CTCIF_Pos       (1U)

+#define MDMA_CISR_CTCIF_Msk       (0x1UL << MDMA_CISR_CTCIF_Pos)               /*!< 0x00000002 */

+#define MDMA_CISR_CTCIF           MDMA_CISR_CTCIF_Msk                          /*!< Channel x Channel Transfer Complete interrupt flag */

+#define MDMA_CISR_BRTIF_Pos       (2U)

+#define MDMA_CISR_BRTIF_Msk       (0x1UL << MDMA_CISR_BRTIF_Pos)               /*!< 0x00000004 */

+#define MDMA_CISR_BRTIF           MDMA_CISR_BRTIF_Msk                          /*!< Channel x block repeat transfer complete interrupt flag */

+#define MDMA_CISR_BTIF_Pos        (3U)

+#define MDMA_CISR_BTIF_Msk        (0x1UL << MDMA_CISR_BTIF_Pos)                /*!< 0x00000008 */

+#define MDMA_CISR_BTIF            MDMA_CISR_BTIF_Msk                           /*!< Channel x block transfer complete interrupt flag */

+#define MDMA_CISR_TCIF_Pos        (4U)

+#define MDMA_CISR_TCIF_Msk        (0x1UL << MDMA_CISR_TCIF_Pos)                /*!< 0x00000010 */

+#define MDMA_CISR_TCIF            MDMA_CISR_TCIF_Msk                           /*!< Channel x buffer transfer complete interrupt flag */

+#define MDMA_CISR_CRQA_Pos        (16U)

+#define MDMA_CISR_CRQA_Msk        (0x1UL << MDMA_CISR_CRQA_Pos)                /*!< 0x00010000 */

+#define MDMA_CISR_CRQA            MDMA_CISR_CRQA_Msk                           /*!< Channel x ReQest Active flag */

+

+/********************  Bit definition for MDMA_CxIFCR register  ****************/

+#define MDMA_CIFCR_CTEIF_Pos      (0U)

+#define MDMA_CIFCR_CTEIF_Msk      (0x1UL << MDMA_CIFCR_CTEIF_Pos)              /*!< 0x00000001 */

+#define MDMA_CIFCR_CTEIF          MDMA_CIFCR_CTEIF_Msk                         /*!< Channel x clear transfer error interrupt flag */

+#define MDMA_CIFCR_CCTCIF_Pos     (1U)

+#define MDMA_CIFCR_CCTCIF_Msk     (0x1UL << MDMA_CIFCR_CCTCIF_Pos)             /*!< 0x00000002 */

+#define MDMA_CIFCR_CCTCIF         MDMA_CIFCR_CCTCIF_Msk                        /*!< Clear Channel transfer complete interrupt flag for channel x */

+#define MDMA_CIFCR_CBRTIF_Pos     (2U)

+#define MDMA_CIFCR_CBRTIF_Msk     (0x1UL << MDMA_CIFCR_CBRTIF_Pos)             /*!< 0x00000004 */

+#define MDMA_CIFCR_CBRTIF         MDMA_CIFCR_CBRTIF_Msk                        /*!< Channel x clear block repeat transfer complete interrupt flag */

+#define MDMA_CIFCR_CBTIF_Pos      (3U)

+#define MDMA_CIFCR_CBTIF_Msk      (0x1UL << MDMA_CIFCR_CBTIF_Pos)              /*!< 0x00000008 */

+#define MDMA_CIFCR_CBTIF          MDMA_CIFCR_CBTIF_Msk                         /*!< Channel x Clear block transfer complete interrupt flag */

+#define MDMA_CIFCR_CLTCIF_Pos     (4U)

+#define MDMA_CIFCR_CLTCIF_Msk     (0x1UL << MDMA_CIFCR_CLTCIF_Pos)             /*!< 0x00000010 */

+#define MDMA_CIFCR_CLTCIF         MDMA_CIFCR_CLTCIF_Msk                        /*!< CLear Transfer buffer Complete Interrupt Flag for channel */

+

+/********************  Bit definition for MDMA_CxESR register  ****************/

+#define MDMA_CESR_TEA_Pos         (0U)

+#define MDMA_CESR_TEA_Msk         (0x7FUL << MDMA_CESR_TEA_Pos)                /*!< 0x0000007F */

+#define MDMA_CESR_TEA             MDMA_CESR_TEA_Msk                            /*!< Transfer Error Address */

+#define MDMA_CESR_TED_Pos         (7U)

+#define MDMA_CESR_TED_Msk         (0x1UL << MDMA_CESR_TED_Pos)                 /*!< 0x00000080 */

+#define MDMA_CESR_TED             MDMA_CESR_TED_Msk                            /*!< Transfer Error Direction */

+#define MDMA_CESR_TELD_Pos        (8U)

+#define MDMA_CESR_TELD_Msk        (0x1UL << MDMA_CESR_TELD_Pos)                /*!< 0x00000100 */

+#define MDMA_CESR_TELD            MDMA_CESR_TELD_Msk                           /*!< Transfer Error Link Data */

+#define MDMA_CESR_TEMD_Pos        (9U)

+#define MDMA_CESR_TEMD_Msk        (0x1UL << MDMA_CESR_TEMD_Pos)                /*!< 0x00000200 */

+#define MDMA_CESR_TEMD            MDMA_CESR_TEMD_Msk                           /*!< Transfer Error Mask Data */

+#define MDMA_CESR_ASE_Pos         (10U)

+#define MDMA_CESR_ASE_Msk         (0x1UL << MDMA_CESR_ASE_Pos)                 /*!< 0x00000400 */

+#define MDMA_CESR_ASE             MDMA_CESR_ASE_Msk                            /*!< Address/Size Error       */

+#define MDMA_CESR_BSE_Pos         (11U)

+#define MDMA_CESR_BSE_Msk         (0x1UL << MDMA_CESR_BSE_Pos)                 /*!< 0x00000800 */

+#define MDMA_CESR_BSE             MDMA_CESR_BSE_Msk                            /*!< Block Size Error         */

+

+/********************  Bit definition for MDMA_CxCR register  ****************/

+#define MDMA_CCR_EN_Pos           (0U)

+#define MDMA_CCR_EN_Msk           (0x1UL << MDMA_CCR_EN_Pos)                   /*!< 0x00000001 */

+#define MDMA_CCR_EN               MDMA_CCR_EN_Msk                              /*!< Channel enable / flag channel ready when read low */

+#define MDMA_CCR_TEIE_Pos         (1U)

+#define MDMA_CCR_TEIE_Msk         (0x1UL << MDMA_CCR_TEIE_Pos)                 /*!< 0x00000002 */

+#define MDMA_CCR_TEIE             MDMA_CCR_TEIE_Msk                            /*!< Transfer error interrupt enable */

+#define MDMA_CCR_CTCIE_Pos        (2U)

+#define MDMA_CCR_CTCIE_Msk        (0x1UL << MDMA_CCR_CTCIE_Pos)                /*!< 0x00000004 */

+#define MDMA_CCR_CTCIE            MDMA_CCR_CTCIE_Msk                           /*!< Channel Transfer Complete interrupt enable */

+#define MDMA_CCR_BRTIE_Pos        (3U)

+#define MDMA_CCR_BRTIE_Msk        (0x1UL << MDMA_CCR_BRTIE_Pos)                /*!< 0x00000008 */

+#define MDMA_CCR_BRTIE            MDMA_CCR_BRTIE_Msk                           /*!< Block Repeat transfer interrupt enable */

+#define MDMA_CCR_BTIE_Pos         (4U)

+#define MDMA_CCR_BTIE_Msk         (0x1UL << MDMA_CCR_BTIE_Pos)                 /*!< 0x00000010 */

+#define MDMA_CCR_BTIE             MDMA_CCR_BTIE_Msk                            /*!< Block Transfer interrupt enable */

+#define MDMA_CCR_TCIE_Pos         (5U)

+#define MDMA_CCR_TCIE_Msk         (0x1UL << MDMA_CCR_TCIE_Pos)                 /*!< 0x00000020 */

+#define MDMA_CCR_TCIE             MDMA_CCR_TCIE_Msk                            /*!< buffer Transfer Complete interrupt enable */

+#define MDMA_CCR_PL_Pos           (6U)

+#define MDMA_CCR_PL_Msk           (0x3UL << MDMA_CCR_PL_Pos)                   /*!< 0x000000C0 */

+#define MDMA_CCR_PL               MDMA_CCR_PL_Msk                              /*!< Priority level */

+#define MDMA_CCR_PL_0             (0x1UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000040 */

+#define MDMA_CCR_PL_1             (0x2UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000080 */

+#define MDMA_CCR_BEX_Pos          (12U)

+#define MDMA_CCR_BEX_Msk          (0x1UL << MDMA_CCR_BEX_Pos)                  /*!< 0x00001000 */

+#define MDMA_CCR_BEX              MDMA_CCR_BEX_Msk                             /*!< Byte Endianess eXchange */

+#define MDMA_CCR_HEX_Pos          (13U)

+#define MDMA_CCR_HEX_Msk          (0x1UL << MDMA_CCR_HEX_Pos)                  /*!< 0x00002000 */

+#define MDMA_CCR_HEX              MDMA_CCR_HEX_Msk                             /*!< Half word Endianess eXchange */

+#define MDMA_CCR_WEX_Pos          (14U)

+#define MDMA_CCR_WEX_Msk          (0x1UL << MDMA_CCR_WEX_Pos)                  /*!< 0x00004000 */

+#define MDMA_CCR_WEX              MDMA_CCR_WEX_Msk                             /*!< Word Endianess eXchange */

+#define MDMA_CCR_SWRQ_Pos         (16U)

+#define MDMA_CCR_SWRQ_Msk         (0x1UL << MDMA_CCR_SWRQ_Pos)                 /*!< 0x00010000 */

+#define MDMA_CCR_SWRQ             MDMA_CCR_SWRQ_Msk                            /*!< SW ReQuest */

+

+/********************  Bit definition for MDMA_CxTCR register  ****************/

+#define MDMA_CTCR_SINC_Pos        (0U)

+#define MDMA_CTCR_SINC_Msk        (0x3UL << MDMA_CTCR_SINC_Pos)                /*!< 0x00000003 */

+#define MDMA_CTCR_SINC            MDMA_CTCR_SINC_Msk                           /*!< Source increment mode */

+#define MDMA_CTCR_SINC_0          (0x1UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000001 */

+#define MDMA_CTCR_SINC_1          (0x2UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000002 */

+#define MDMA_CTCR_DINC_Pos        (2U)

+#define MDMA_CTCR_DINC_Msk        (0x3UL << MDMA_CTCR_DINC_Pos)                /*!< 0x0000000C */

+#define MDMA_CTCR_DINC            MDMA_CTCR_DINC_Msk                           /*!< Source increment mode */

+#define MDMA_CTCR_DINC_0          (0x1UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000004 */

+#define MDMA_CTCR_DINC_1          (0x2UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000008 */

+#define MDMA_CTCR_SSIZE_Pos       (4U)

+#define MDMA_CTCR_SSIZE_Msk       (0x3UL << MDMA_CTCR_SSIZE_Pos)               /*!< 0x00000030 */

+#define MDMA_CTCR_SSIZE           MDMA_CTCR_SSIZE_Msk                          /*!< Source data size */

+#define MDMA_CTCR_SSIZE_0         (0x1UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000010 */

+#define MDMA_CTCR_SSIZE_1         (0x2UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000020 */

+#define MDMA_CTCR_DSIZE_Pos       (6U)

+#define MDMA_CTCR_DSIZE_Msk       (0x3UL << MDMA_CTCR_DSIZE_Pos)               /*!< 0x000000C0 */

+#define MDMA_CTCR_DSIZE           MDMA_CTCR_DSIZE_Msk                          /*!< Destination data size */

+#define MDMA_CTCR_DSIZE_0         (0x1UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000040 */

+#define MDMA_CTCR_DSIZE_1         (0x2UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000080 */

+#define MDMA_CTCR_SINCOS_Pos      (8U)

+#define MDMA_CTCR_SINCOS_Msk      (0x3UL << MDMA_CTCR_SINCOS_Pos)              /*!< 0x00000300 */

+#define MDMA_CTCR_SINCOS          MDMA_CTCR_SINCOS_Msk                         /*!< Source increment offset size */

+#define MDMA_CTCR_SINCOS_0        (0x1UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000100 */

+#define MDMA_CTCR_SINCOS_1        (0x2UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000200 */

+#define MDMA_CTCR_DINCOS_Pos      (10U)

+#define MDMA_CTCR_DINCOS_Msk      (0x3UL << MDMA_CTCR_DINCOS_Pos)              /*!< 0x00000C00 */

+#define MDMA_CTCR_DINCOS          MDMA_CTCR_DINCOS_Msk                         /*!< Destination increment offset size */

+#define MDMA_CTCR_DINCOS_0        (0x1UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000400 */

+#define MDMA_CTCR_DINCOS_1        (0x2UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000800 */

+#define MDMA_CTCR_SBURST_Pos      (12U)

+#define MDMA_CTCR_SBURST_Msk      (0x7UL << MDMA_CTCR_SBURST_Pos)              /*!< 0x00007000 */

+#define MDMA_CTCR_SBURST          MDMA_CTCR_SBURST_Msk                         /*!< Source burst transfer configuration */

+#define MDMA_CTCR_SBURST_0        (0x1UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00001000 */

+#define MDMA_CTCR_SBURST_1        (0x2UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00002000 */

+#define MDMA_CTCR_SBURST_2        (0x4UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00004000 */

+#define MDMA_CTCR_DBURST_Pos      (15U)

+#define MDMA_CTCR_DBURST_Msk      (0x7UL << MDMA_CTCR_DBURST_Pos)              /*!< 0x00038000 */

+#define MDMA_CTCR_DBURST          MDMA_CTCR_DBURST_Msk                         /*!< Destination burst transfer configuration */

+#define MDMA_CTCR_DBURST_0        (0x1UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00008000 */

+#define MDMA_CTCR_DBURST_1        (0x2UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00010000 */

+#define MDMA_CTCR_DBURST_2        (0x4UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00020000 */

+#define MDMA_CTCR_TLEN_Pos        (18U)

+#define MDMA_CTCR_TLEN_Msk        (0x7FUL << MDMA_CTCR_TLEN_Pos)               /*!< 0x01FC0000 */

+#define MDMA_CTCR_TLEN            MDMA_CTCR_TLEN_Msk                           /*!< buffer Transfer Length (number of bytes - 1) */

+#define MDMA_CTCR_PKE_Pos         (25U)

+#define MDMA_CTCR_PKE_Msk         (0x1UL << MDMA_CTCR_PKE_Pos)                 /*!< 0x02000000 */

+#define MDMA_CTCR_PKE             MDMA_CTCR_PKE_Msk                            /*!< PacK Enable */

+#define MDMA_CTCR_PAM_Pos         (26U)

+#define MDMA_CTCR_PAM_Msk         (0x3UL << MDMA_CTCR_PAM_Pos)                 /*!< 0x0C000000 */

+#define MDMA_CTCR_PAM             MDMA_CTCR_PAM_Msk                            /*!< Padding/Alignement Mode */

+#define MDMA_CTCR_PAM_0           (0x1UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x4000000 */

+#define MDMA_CTCR_PAM_1           (0x2UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x8000000 */

+#define MDMA_CTCR_TRGM_Pos        (28U)

+#define MDMA_CTCR_TRGM_Msk        (0x3UL << MDMA_CTCR_TRGM_Pos)                /*!< 0x30000000 */

+#define MDMA_CTCR_TRGM            MDMA_CTCR_TRGM_Msk                           /*!< Trigger Mode */

+#define MDMA_CTCR_TRGM_0          (0x1UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x10000000 */

+#define MDMA_CTCR_TRGM_1          (0x2UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x20000000 */

+#define MDMA_CTCR_SWRM_Pos        (30U)

+#define MDMA_CTCR_SWRM_Msk        (0x1UL << MDMA_CTCR_SWRM_Pos)                /*!< 0x40000000 */

+#define MDMA_CTCR_SWRM            MDMA_CTCR_SWRM_Msk                           /*!< SW Request Mode */

+#define MDMA_CTCR_BWM_Pos         (31U)

+#define MDMA_CTCR_BWM_Msk         (0x1UL << MDMA_CTCR_BWM_Pos)                 /*!< 0x80000000 */

+#define MDMA_CTCR_BWM             MDMA_CTCR_BWM_Msk                            /*!< Bufferable Write Mode */

+

+/********************  Bit definition for MDMA_CxBNDTR register  ****************/

+#define MDMA_CBNDTR_BNDT_Pos      (0U)

+#define MDMA_CBNDTR_BNDT_Msk      (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos)          /*!< 0x0001FFFF */

+#define MDMA_CBNDTR_BNDT          MDMA_CBNDTR_BNDT_Msk                         /*!< Block Number of data bytes to transfer */

+#define MDMA_CBNDTR_BRSUM_Pos     (18U)

+#define MDMA_CBNDTR_BRSUM_Msk     (0x1UL << MDMA_CBNDTR_BRSUM_Pos)             /*!< 0x00040000 */

+#define MDMA_CBNDTR_BRSUM         MDMA_CBNDTR_BRSUM_Msk                        /*!< Block Repeat Source address Update Mode */

+#define MDMA_CBNDTR_BRDUM_Pos     (19U)

+#define MDMA_CBNDTR_BRDUM_Msk     (0x1UL << MDMA_CBNDTR_BRDUM_Pos)             /*!< 0x00080000 */

+#define MDMA_CBNDTR_BRDUM         MDMA_CBNDTR_BRDUM_Msk                        /*!< Block Repeat Destination address Update Mode */

+#define MDMA_CBNDTR_BRC_Pos       (20U)

+#define MDMA_CBNDTR_BRC_Msk       (0xFFFUL << MDMA_CBNDTR_BRC_Pos)             /*!< 0xFFF00000 */

+#define MDMA_CBNDTR_BRC           MDMA_CBNDTR_BRC_Msk                          /*!< Block Repeat Count */

+

+/********************  Bit definition for MDMA_CxSAR register  ****************/

+#define MDMA_CSAR_SAR_Pos         (0U)

+#define MDMA_CSAR_SAR_Msk         (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CSAR_SAR             MDMA_CSAR_SAR_Msk                            /*!< Source address */

+

+/********************  Bit definition for MDMA_CxDAR register  ****************/

+#define MDMA_CDAR_DAR_Pos         (0U)

+#define MDMA_CDAR_DAR_Msk         (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CDAR_DAR             MDMA_CDAR_DAR_Msk                            /*!< Destination address */

+

+/********************  Bit definition for MDMA_CxBRUR  ************************/

+#define MDMA_CBRUR_SUV_Pos        (0U)

+#define MDMA_CBRUR_SUV_Msk        (0xFFFFUL << MDMA_CBRUR_SUV_Pos)             /*!< 0x0000FFFF */

+#define MDMA_CBRUR_SUV            MDMA_CBRUR_SUV_Msk                           /*!< Source address Update Value */

+#define MDMA_CBRUR_DUV_Pos        (16U)

+#define MDMA_CBRUR_DUV_Msk        (0xFFFFUL << MDMA_CBRUR_DUV_Pos)             /*!< 0xFFFF0000 */

+#define MDMA_CBRUR_DUV            MDMA_CBRUR_DUV_Msk                           /*!< Destination address Update Value */

+

+/********************  Bit definition for MDMA_CxLAR  *************************/

+#define MDMA_CLAR_LAR_Pos         (0U)

+#define MDMA_CLAR_LAR_Msk         (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CLAR_LAR             MDMA_CLAR_LAR_Msk                            /*!< Link Address Register */

+

+/********************  Bit definition for MDMA_CxTBR)  ************************/

+#define MDMA_CTBR_TSEL_Pos        (0U)

+#define MDMA_CTBR_TSEL_Msk        (0xFFUL << MDMA_CTBR_TSEL_Pos)               /*!< 0x000000FF */

+#define MDMA_CTBR_TSEL            MDMA_CTBR_TSEL_Msk                           /*!< Trigger SELection */

+#define MDMA_CTBR_SBUS_Pos        (16U)

+#define MDMA_CTBR_SBUS_Msk        (0x1UL << MDMA_CTBR_SBUS_Pos)                /*!< 0x00010000 */

+#define MDMA_CTBR_SBUS            MDMA_CTBR_SBUS_Msk                           /*!< Source BUS select */

+#define MDMA_CTBR_DBUS_Pos        (17U)

+#define MDMA_CTBR_DBUS_Msk        (0x1UL << MDMA_CTBR_DBUS_Pos)                /*!< 0x00020000 */

+#define MDMA_CTBR_DBUS            MDMA_CTBR_DBUS_Msk                           /*!< Destination BUS select */

+

+/********************  Bit definition for MDMA_CxMAR)  ************************/

+#define MDMA_CMAR_MAR_Pos         (0U)

+#define MDMA_CMAR_MAR_Msk         (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CMAR_MAR             MDMA_CMAR_MAR_Msk                            /*!< Mask address */

+

+/********************  Bit definition for MDMA_CxMDR)  ************************/

+#define MDMA_CMDR_MDR_Pos         (0U)

+#define MDMA_CMDR_MDR_Msk         (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CMDR_MDR             MDMA_CMDR_MDR_Msk                            /*!< Mask Data */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Operational Amplifier (OPAMP)                      */

+/*                                                                            */

+/******************************************************************************/

+/*********************  Bit definition for OPAMPx_CSR register  ***************/

+#define OPAMP_CSR_OPAMPxEN_Pos           (0U)

+#define OPAMP_CSR_OPAMPxEN_Msk           (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)     /*!< 0x00000001 */

+#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */

+#define OPAMP_CSR_FORCEVP_Pos            (1U)

+#define OPAMP_CSR_FORCEVP_Msk            (0x1UL << OPAMP_CSR_FORCEVP_Pos)      /*!< 0x00000002 */

+#define OPAMP_CSR_FORCEVP                OPAMP_CSR_FORCEVP_Msk                 /*!< Force internal reference on VP */

+

+#define OPAMP_CSR_VPSEL_Pos              (2U)

+#define OPAMP_CSR_VPSEL_Msk              (0x3UL << OPAMP_CSR_VPSEL_Pos)        /*!< 0x0000000C */

+#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */

+#define OPAMP_CSR_VPSEL_0                (0x1UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000004 */

+#define OPAMP_CSR_VPSEL_1                (0x2UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000008 */

+

+#define OPAMP_CSR_VMSEL_Pos              (5U)

+#define OPAMP_CSR_VMSEL_Msk              (0x3UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000060 */

+#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */

+#define OPAMP_CSR_VMSEL_0                (0x1UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000020 */

+#define OPAMP_CSR_VMSEL_1                (0x2UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000040 */

+

+#define OPAMP_CSR_OPAHSM_Pos             (8U)

+#define OPAMP_CSR_OPAHSM_Msk             (0x1UL << OPAMP_CSR_OPAHSM_Pos)       /*!< 0x00000100 */

+#define OPAMP_CSR_OPAHSM                 OPAMP_CSR_OPAHSM_Msk                  /*!< Operational amplifier high speed mode */

+#define OPAMP_CSR_CALON_Pos              (11U)

+#define OPAMP_CSR_CALON_Msk              (0x1UL << OPAMP_CSR_CALON_Pos)        /*!< 0x00000800 */

+#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */

+

+#define OPAMP_CSR_CALSEL_Pos             (12U)

+#define OPAMP_CSR_CALSEL_Msk             (0x3UL << OPAMP_CSR_CALSEL_Pos)       /*!< 0x00003000 */

+#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */

+#define OPAMP_CSR_CALSEL_0               (0x1UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00001000 */

+#define OPAMP_CSR_CALSEL_1               (0x2UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */

+

+#define OPAMP_CSR_PGGAIN_Pos             (14U)

+#define OPAMP_CSR_PGGAIN_Msk             (0xFUL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x0003C000 */

+#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */

+#define OPAMP_CSR_PGGAIN_0               (0x1UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00004000 */

+#define OPAMP_CSR_PGGAIN_1               (0x2UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00008000 */

+#define OPAMP_CSR_PGGAIN_2               (0x4UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00010000 */

+#define OPAMP_CSR_PGGAIN_3               (0x8UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00020000 */

+

+#define OPAMP_CSR_USERTRIM_Pos           (18U)

+#define OPAMP_CSR_USERTRIM_Msk           (0x1UL << OPAMP_CSR_USERTRIM_Pos)     /*!< 0x00040000 */

+#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */

+#define OPAMP_CSR_TSTREF_Pos             (29U)

+#define OPAMP_CSR_TSTREF_Msk             (0x1UL << OPAMP_CSR_TSTREF_Pos)       /*!< 0x20000000 */

+#define OPAMP_CSR_TSTREF                 OPAMP_CSR_TSTREF_Msk                  /*!< OpAmp calibration reference voltage output control */

+#define OPAMP_CSR_CALOUT_Pos             (30U)

+#define OPAMP_CSR_CALOUT_Msk             (0x1UL << OPAMP_CSR_CALOUT_Pos)       /*!< 0x40000000 */

+#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier calibration output */

+

+/*********************  Bit definition for OPAMP1_CSR register  ***************/

+#define OPAMP1_CSR_OPAEN_Pos              (0U)

+#define OPAMP1_CSR_OPAEN_Msk              (0x1UL << OPAMP1_CSR_OPAEN_Pos)      /*!< 0x00000001 */

+#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */

+#define OPAMP1_CSR_FORCEVP_Pos            (1U)

+#define OPAMP1_CSR_FORCEVP_Msk            (0x1UL << OPAMP1_CSR_FORCEVP_Pos)    /*!< 0x00000002 */

+#define OPAMP1_CSR_FORCEVP                OPAMP1_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */

+

+#define OPAMP1_CSR_VPSEL_Pos              (2U)

+#define OPAMP1_CSR_VPSEL_Msk              (0x3UL << OPAMP1_CSR_VPSEL_Pos)      /*!< 0x0000000C */

+#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */

+#define OPAMP1_CSR_VPSEL_0                (0x1UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000004 */

+#define OPAMP1_CSR_VPSEL_1                (0x2UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000008 */

+

+#define OPAMP1_CSR_VMSEL_Pos              (5U)

+#define OPAMP1_CSR_VMSEL_Msk              (0x3UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000060 */

+#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */

+#define OPAMP1_CSR_VMSEL_0                (0x1UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000020 */

+#define OPAMP1_CSR_VMSEL_1                (0x2UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000040 */

+

+#define OPAMP1_CSR_OPAHSM_Pos             (8U)

+#define OPAMP1_CSR_OPAHSM_Msk             (0x1UL << OPAMP1_CSR_OPAHSM_Pos)     /*!< 0x00000100 */

+#define OPAMP1_CSR_OPAHSM                 OPAMP1_CSR_OPAHSM_Msk                /*!< Operational amplifier1 high speed mode */

+#define OPAMP1_CSR_CALON_Pos              (11U)

+#define OPAMP1_CSR_CALON_Msk              (0x1UL << OPAMP1_CSR_CALON_Pos)      /*!< 0x00000800 */

+#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */

+

+#define OPAMP1_CSR_CALSEL_Pos             (12U)

+#define OPAMP1_CSR_CALSEL_Msk             (0x3UL << OPAMP1_CSR_CALSEL_Pos)     /*!< 0x00003000 */

+#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */

+#define OPAMP1_CSR_CALSEL_0               (0x1UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00001000 */

+#define OPAMP1_CSR_CALSEL_1               (0x2UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */

+

+#define OPAMP1_CSR_PGGAIN_Pos             (14U)

+#define OPAMP1_CSR_PGGAIN_Msk             (0xFUL << OPAMP1_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */

+#define OPAMP1_CSR_PGGAIN                 OPAMP1_CSR_PGGAIN_Msk                /*!< Operational amplifier1 Programmable amplifier gain value */

+#define OPAMP1_CSR_PGGAIN_0               (0x1UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00004000 */

+#define OPAMP1_CSR_PGGAIN_1               (0x2UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00008000 */

+#define OPAMP1_CSR_PGGAIN_2               (0x4UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00010000 */

+#define OPAMP1_CSR_PGGAIN_3               (0x8UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00020000 */

+

+#define OPAMP1_CSR_USERTRIM_Pos           (18U)

+#define OPAMP1_CSR_USERTRIM_Msk           (0x1UL << OPAMP1_CSR_USERTRIM_Pos)   /*!< 0x00040000 */

+#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */

+#define OPAMP1_CSR_TSTREF_Pos             (29U)

+#define OPAMP1_CSR_TSTREF_Msk             (0x1UL << OPAMP1_CSR_TSTREF_Pos)     /*!< 0x20000000 */

+#define OPAMP1_CSR_TSTREF                 OPAMP1_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */

+#define OPAMP1_CSR_CALOUT_Pos             (30U)

+#define OPAMP1_CSR_CALOUT_Msk             (0x1UL << OPAMP1_CSR_CALOUT_Pos)     /*!< 0x40000000 */

+#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */

+

+/*********************  Bit definition for OPAMP2_CSR register  ***************/

+#define OPAMP2_CSR_OPAEN_Pos              (0U)

+#define OPAMP2_CSR_OPAEN_Msk              (0x1UL << OPAMP2_CSR_OPAEN_Pos)      /*!< 0x00000001 */

+#define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */

+#define OPAMP2_CSR_FORCEVP_Pos            (1U)

+#define OPAMP2_CSR_FORCEVP_Msk            (0x1UL << OPAMP2_CSR_FORCEVP_Pos)    /*!< 0x00000002 */

+#define OPAMP2_CSR_FORCEVP                OPAMP2_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */

+

+#define OPAMP2_CSR_VPSEL_Pos              (2U)

+#define OPAMP2_CSR_VPSEL_Msk              (0x3UL << OPAMP2_CSR_VPSEL_Pos)      /*!< 0x0000000C */

+#define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */

+#define OPAMP2_CSR_VPSEL_0                (0x1UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000004 */

+#define OPAMP2_CSR_VPSEL_1                (0x2UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000008 */

+

+#define OPAMP2_CSR_VMSEL_Pos              (5U)

+#define OPAMP2_CSR_VMSEL_Msk              (0x3UL << OPAMP2_CSR_VMSEL_Pos)      /*!< 0x00000060 */

+#define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */

+#define OPAMP2_CSR_VMSEL_0                (0x1UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000020 */

+#define OPAMP2_CSR_VMSEL_1                (0x2UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000040 */

+

+#define OPAMP2_CSR_OPAHSM_Pos             (8U)

+#define OPAMP2_CSR_OPAHSM_Msk             (0x1UL << OPAMP2_CSR_OPAHSM_Pos)     /*!< 0x00000100 */

+#define OPAMP2_CSR_OPAHSM                 OPAMP2_CSR_OPAHSM_Msk                /*!< Operational amplifier2 high speed mode */

+#define OPAMP2_CSR_CALON_Pos              (11U)

+#define OPAMP2_CSR_CALON_Msk              (0x1UL << OPAMP2_CSR_CALON_Pos)      /*!< 0x00000800 */

+#define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */

+

+#define OPAMP2_CSR_CALSEL_Pos             (12U)

+#define OPAMP2_CSR_CALSEL_Msk             (0x3UL << OPAMP2_CSR_CALSEL_Pos)     /*!< 0x00003000 */

+#define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */

+#define OPAMP2_CSR_CALSEL_0               (0x1UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00001000 */

+#define OPAMP2_CSR_CALSEL_1               (0x2UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */

+

+#define OPAMP2_CSR_PGGAIN_Pos             (14U)

+#define OPAMP2_CSR_PGGAIN_Msk             (0xFUL << OPAMP2_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */

+#define OPAMP2_CSR_PGGAIN                 OPAMP2_CSR_PGGAIN_Msk                /*!< Operational amplifier2 Programmable amplifier gain value */

+#define OPAMP2_CSR_PGGAIN_0               (0x1UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00004000 */

+#define OPAMP2_CSR_PGGAIN_1               (0x2UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00008000 */

+#define OPAMP2_CSR_PGGAIN_2               (0x4UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00010000 */

+#define OPAMP2_CSR_PGGAIN_3               (0x8UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00020000 */

+

+#define OPAMP2_CSR_USERTRIM_Pos           (18U)

+#define OPAMP2_CSR_USERTRIM_Msk           (0x1UL << OPAMP2_CSR_USERTRIM_Pos)   /*!< 0x00040000 */

+#define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */

+#define OPAMP2_CSR_TSTREF_Pos             (29U)

+#define OPAMP2_CSR_TSTREF_Msk             (0x1UL << OPAMP2_CSR_TSTREF_Pos)     /*!< 0x20000000 */

+#define OPAMP2_CSR_TSTREF                 OPAMP2_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */

+#define OPAMP2_CSR_CALOUT_Pos             (30U)

+#define OPAMP2_CSR_CALOUT_Msk             (0x1UL << OPAMP2_CSR_CALOUT_Pos)     /*!< 0x40000000 */

+#define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */

+

+/*******************  Bit definition for OPAMP_OTR register  ******************/

+#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */

+#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP1_OTR register  ******************/

+#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */

+#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP2_OTR register  ******************/

+#define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */

+#define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP_HSOTR register  ****************/

+#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP_HSOTR_TRIMHSOFFSETN        OPAMP_HSOTR_TRIMHSOFFSETN_Msk         /*!< Trim for NMOS differential pairs */

+#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP_HSOTR_TRIMHSOFFSETP        OPAMP_HSOTR_TRIMHSOFFSETP_Msk         /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP1_HSOTR register  ****************/

+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP1_HSOTR_TRIMHSOFFSETN        OPAMP1_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */

+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP1_HSOTR_TRIMHSOFFSETP        OPAMP1_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP2_HSOTR register  ****************/

+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP2_HSOTR_TRIMHSOFFSETN        OPAMP2_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */

+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP2_HSOTR_TRIMHSOFFSETP        OPAMP2_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */

+

+/******************************************************************************/

+/*                                                                            */

+/*                Parallel Synchronous Slave Interface (PSSI )                */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for PSSI_CR register  *******************/

+#define PSSI_CR_OUTEN_Pos               (31U)

+#define PSSI_CR_OUTEN_Msk               (0x1UL << PSSI_CR_OUTEN_Pos)           /*!< 0x80000000 */

+#define PSSI_CR_OUTEN                   PSSI_CR_OUTEN_Msk                      /*!< Data direction selection */

+#define PSSI_CR_DMAEN_Pos               (30U)

+#define PSSI_CR_DMAEN_Msk               (0x1UL << PSSI_CR_DMAEN_Pos)           /*!< 0x40000000 */

+#define PSSI_CR_DMAEN                   PSSI_CR_DMAEN_Msk                      /*!< DMA enable */

+#define PSSI_CR_DERDYCFG_Pos            (18U)

+#define PSSI_CR_DERDYCFG_Msk            (0x7UL << PSSI_CR_DERDYCFG_Pos)        /*!< 0x001C0000 */

+#define PSSI_CR_DERDYCFG                PSSI_CR_DERDYCFG_Msk                   /*!< Data enable and ready configuration */

+#define PSSI_CR_ENABLE_Pos              (14U)

+#define PSSI_CR_ENABLE_Msk              (0x1UL << PSSI_CR_ENABLE_Pos)          /*!< 0x00004000 */

+#define PSSI_CR_ENABLE                  PSSI_CR_ENABLE_Msk                     /*!< PSSI enable */

+#define PSSI_CR_EDM_Pos                 (10U)

+#define PSSI_CR_EDM_Msk                 (0x3UL << PSSI_CR_EDM_Pos)             /*!< 0x00000C00 */

+#define PSSI_CR_EDM                     PSSI_CR_EDM_Msk                        /*!< Extended data mode */

+#define PSSI_CR_RDYPOL_Pos              (8U)

+#define PSSI_CR_RDYPOL_Msk              (0x1UL << PSSI_CR_RDYPOL_Pos)          /*!< 0x00000C00 */

+#define PSSI_CR_RDYPOL                  PSSI_CR_RDYPOL_Msk                     /*!< Ready polarity */

+#define PSSI_CR_DEPOL_Pos               (6U)

+#define PSSI_CR_DEPOL_Msk               (0x1UL << PSSI_CR_DEPOL_Pos)           /*!< 0x00000C00 */

+#define PSSI_CR_DEPOL                   PSSI_CR_DEPOL_Msk                      /*!<  Data enable polarity */

+#define PSSI_CR_CKPOL_Pos               (5U)

+#define PSSI_CR_CKPOL_Msk               (0x1UL << PSSI_CR_CKPOL_Pos)           /*!< 0x00000C00 */

+#define PSSI_CR_CKPOL                   PSSI_CR_CKPOL_Msk                      /*!< Parallel data clock polarity */

+/********************  Bit definition for PSSI_SR register  *******************/

+#define PSSI_SR_RTT1B_Pos               (3U)

+#define PSSI_SR_RTT1B_Msk               (0x1UL << PSSI_SR_RTT1B_Pos)           /*!< 0x00000008 */

+#define PSSI_SR_RTT1B                   PSSI_SR_RTT1B_Msk                      /*!< Ready to transfer one byte */

+#define PSSI_SR_RTT4B_Pos               (2U)

+#define PSSI_SR_RTT4B_Msk               (0x1UL << PSSI_SR_RTT4B_Pos)           /*!< 0x00000004 */

+#define PSSI_SR_RTT4B                   PSSI_SR_RTT4B_Msk                      /*!< Ready to transfer four bytes */

+/********************  Bit definition for PSSI_RIS register  *******************/

+#define PSSI_RIS_OVR_RIS_Pos            (1U)

+#define PSSI_RIS_OVR_RIS_Msk            (0x1UL << PSSI_RIS_OVR_RIS_Pos)        /*!< 0x00000002 */

+#define PSSI_RIS_OVR_RIS                PSSI_RIS_OVR_RIS_Msk                   /*!< Data buffer overrun/underrun raw interrupt status */

+/********************  Bit definition for PSSI_IER register  *******************/

+#define PSSI_IER_OVR_IE_Pos             (1U)

+#define PSSI_IER_OVR_IE_Msk             (0x1UL << PSSI_IER_OVR_IE_Pos)         /*!< 0x00000002 */

+#define PSSI_IER_OVR_IE                 PSSI_IER_OVR_IE_Msk                    /*!< Data buffer overrun/underrun interrupt enable */

+/********************  Bit definition for PSSI_MIS register  *******************/

+#define PSSI_MIS_OVR_MIS_Pos            (1U)

+#define PSSI_MIS_OVR_MIS_Msk            (0x1UL << PSSI_MIS_OVR_MIS_Pos)        /*!< 0x00000002 */

+#define PSSI_MIS_OVR_MIS                PSSI_MIS_OVR_MIS_Msk                   /*!< Data buffer overrun/underrun masked interrupt status */

+/********************  Bit definition for PSSI_ICR register  *******************/

+#define PSSI_ICR_OVR_ISC_Pos            (1U)

+#define PSSI_ICR_OVR_ISC_Msk            (0x1UL << PSSI_ICR_OVR_ISC_Pos)        /*!< 0x00000002 */

+#define PSSI_ICR_OVR_ISC                PSSI_ICR_OVR_ISC_Msk                   /*!< Data buffer overrun/underrun interrupt status clear */

+/********************  Bit definition for PSSI_DR register  *******************/

+#define PSSI_DR_DR_Pos                  (0U)

+#define PSSI_DR_DR_Msk                  (0xFFFFFFFFUL << PSSI_DR_DR_Pos)       /*!< 0xFFFFFFF */

+#define PSSI_DR_DR                      PSSI_DR_DR_Msk                         /*!< Data register  */

+

+/******************************************************************************/

+/*                                                                            */

+/*                              On The Fly Decryption                         */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for OTFDEC_CR register  ******************/

+#define OTFDEC_CR_ENC_Pos                      (0U)

+#define OTFDEC_CR_ENC_Msk                      (0x1UL << OTFDEC_CR_ENC_Pos)                  /*!< 0x00000001 */

+#define OTFDEC_CR_ENC                          OTFDEC_CR_ENC_Msk                             /*!< Encryption mode bit */

+

+/******************  Bit definition for OTFDEC_PRIVCFGR register  ************/

+#define OTFDEC_PRIVCFGR_PRIV_Pos               (0U)

+#define OTFDEC_PRIVCFGR_PRIV_Msk               (0x1UL << OTFDEC_PRIVCFGR_PRIV_Pos)           /*!< 0x00000001 */

+#define OTFDEC_PRIVCFGR_PRIV                   OTFDEC_PRIVCFGR_PRIV_Msk                      /*!< Privileged access protection */

+

+/******************  Bit definition for OTFDEC_REG_CONFIGR register  *********/

+#define OTFDEC_REG_CONFIGR_REG_EN_Pos          (0U)

+#define OTFDEC_REG_CONFIGR_REG_EN_Msk          (0x1UL << OTFDEC_REG_CONFIGR_REG_EN_Pos)      /*!< 0x00000001 */

+#define OTFDEC_REG_CONFIGR_REG_EN              OTFDEC_REG_CONFIGR_REG_EN_Msk                 /*!< Region on-the-fly decryption enable */

+

+#define OTFDEC_REG_CONFIGR_CONFIGLOCK_Pos      (1U)

+#define OTFDEC_REG_CONFIGR_CONFIGLOCK_Msk      (0x1UL << OTFDEC_REG_CONFIGR_CONFIGLOCK_Pos)  /*!< 0x00000002 */

+#define OTFDEC_REG_CONFIGR_CONFIGLOCK          OTFDEC_REG_CONFIGR_CONFIGLOCK_Msk             /*!< Region config lock */

+

+#define OTFDEC_REG_CONFIGR_KEYLOCK_Pos         (2U)

+#define OTFDEC_REG_CONFIGR_KEYLOCK_Msk         (0x1UL << OTFDEC_REG_CONFIGR_KEYLOCK_Pos)     /*!< 0x00000004 */

+#define OTFDEC_REG_CONFIGR_KEYLOCK             OTFDEC_REG_CONFIGR_KEYLOCK_Msk                /*!< Region key lock */

+

+#define OTFDEC_REG_CONFIGR_MODE_Pos            (4U)

+#define OTFDEC_REG_CONFIGR_MODE_Msk            (0x3UL << OTFDEC_REG_CONFIGR_MODE_Pos)        /*!< 0x00000030 */

+#define OTFDEC_REG_CONFIGR_MODE                OTFDEC_REG_CONFIGR_MODE_Msk                   /*!< Region operating mode */

+#define OTFDEC_REG_CONFIGR_MODE_0              (0x1UL << OTFDEC_REG_CONFIGR_MODE_Pos)        /*!< 0x00000010 */

+#define OTFDEC_REG_CONFIGR_MODE_1              (0x2UL << OTFDEC_REG_CONFIGR_MODE_Pos)        /*!< 0x00000020 */

+

+#define OTFDEC_REG_CONFIGR_KEYCRC_Pos          (8U)

+#define OTFDEC_REG_CONFIGR_KEYCRC_Msk          (0xFFUL << OTFDEC_REG_CONFIGR_KEYCRC_Pos)     /*!< 0x0000FF00 */

+#define OTFDEC_REG_CONFIGR_KEYCRC              OTFDEC_REG_CONFIGR_KEYCRC_Msk                 /*!< Region key 8-bit CRC */

+

+#define OTFDEC_REG_CONFIGR_VERSION_Pos         (16U)

+#define OTFDEC_REG_CONFIGR_VERSION_Msk         (0xFFFFUL << OTFDEC_REG_CONFIGR_VERSION_Pos)  /*!< 0xFFFF0000 */

+#define OTFDEC_REG_CONFIGR_VERSION             OTFDEC_REG_CONFIGR_VERSION_Msk                /*!< Region firmware version */

+

+/******************  Bit definition for OTFDEC_REG_START_ADDR register  ******/

+#define OTFDEC_REG_START_ADDR_Pos              (0U)

+#define OTFDEC_REG_START_ADDR_Msk              (0xFFFFFFFFUL << OTFDEC_REG_START_ADDR_Pos)   /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_START_ADDR                  OTFDEC_REG_START_ADDR_Msk                     /*!< Region AHB start address */

+

+/******************  Bit definition for OTFDEC_REG_END_ADDR register  ********/

+#define OTFDEC_REG_END_ADDR_Pos                (0U)

+#define OTFDEC_REG_END_ADDR_Msk                (0xFFFFFFFFUL << OTFDEC_REG_END_ADDR_Pos)     /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_END_ADDR                    OTFDEC_REG_END_ADDR_Msk                       /*!< Region AHB end address */

+

+/******************  Bit definition for OTFDEC_REG_NONCER0 register  *********/

+#define OTFDEC_REG_NONCER0_Pos                 (0U)

+#define OTFDEC_REG_NONCER0_Msk                 (0xFFFFFFFFUL << OTFDEC_REG_NONCER0_Pos)      /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_NONCER0                     OTFDEC_REG_NONCER0_Msk                        /*!< Region Nonce Register (LSB nonce[31:0]) */

+

+/******************  Bit definition for OTFDEC_REG_NONCER1 register  *********/

+#define OTFDEC_REG_NONCER1_Pos                 (0U)

+#define OTFDEC_REG_NONCER1_Msk                 (0xFFFFFFFFUL << OTFDEC_REG_NONCER1_Pos)      /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_NONCER1                     OTFDEC_REG_NONCER1_Msk                        /*!< Region Nonce Register (MSB nonce[63:32]) */

+

+/******************  Bit definition for OTFDEC_REG_KEYR0 register  ***********/

+#define OTFDEC_REG_KEYR0_Pos                   (0U)

+#define OTFDEC_REG_KEYR0_Msk                   (0xFFFFFFFFUL << OTFDEC_REG_KEYR0_Pos)        /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_KEYR0                       OTFDEC_REG_KEYR0_Msk                          /*!< Region Key Register (LSB key[31:0]) */

+

+/******************  Bit definition for OTFDEC_REG_KEYR1 register  ***********/

+#define OTFDEC_REG_KEYR1_Pos                   (0U)

+#define OTFDEC_REG_KEYR1_Msk                   (0xFFFFFFFFUL << OTFDEC_REG_KEYR1_Pos)        /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_KEYR1                       OTFDEC_REG_KEYR1_Msk                          /*!< Region Key Register (key[63:32]) */

+

+/******************  Bit definition for OTFDEC_REG_KEYR2 register  ***********/

+#define OTFDEC_REG_KEYR2_Pos                   (0U)

+#define OTFDEC_REG_KEYR2_Msk                   (0xFFFFFFFFUL << OTFDEC_REG_KEYR2_Pos)        /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_KEYR2                       OTFDEC_REG_KEYR2_Msk                          /*!< Region Key Register (key[95:64]) */

+

+/******************  Bit definition for OTFDEC_REG_KEYR3 register  ***********/

+#define OTFDEC_REG_KEYR3_Pos                   (0U)

+#define OTFDEC_REG_KEYR3_Msk                   (0xFFFFFFFFUL << OTFDEC_REG_KEYR3_Pos)        /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_KEYR3                       OTFDEC_REG_KEYR3_Msk                          /*!< Region Key Register (key[127:96]) */

+

+/******************  Bit definition for OTFDEC_ISR register  *****************/

+#define OTFDEC_ISR_SEIF_Pos                    (0U)

+#define OTFDEC_ISR_SEIF_Msk                    (0x1UL << OTFDEC_ISR_SEIF_Pos)                /*!< 0x00000001 */

+#define OTFDEC_ISR_SEIF                        OTFDEC_ISR_SEIF_Msk                           /*!< Security Error Interrupt Flag status bit before enable (mask) */

+

+#define OTFDEC_ISR_XONEIF_Pos                  (1U)

+#define OTFDEC_ISR_XONEIF_Msk                  (0x1UL << OTFDEC_ISR_XONEIF_Pos)              /*!< 0x00000002 */

+#define OTFDEC_ISR_XONEIF                      OTFDEC_ISR_XONEIF_Msk                         /*!< Execute-only Error Interrupt Flag status bit before enable (mask) */

+

+#define OTFDEC_ISR_KEIF_Pos                    (2U)

+#define OTFDEC_ISR_KEIF_Msk                    (0x1UL << OTFDEC_ISR_KEIF_Pos)                /*!< 0x00000004 */

+#define OTFDEC_ISR_KEIF                        OTFDEC_ISR_KEIF_Msk                           /*!< Key Error Interrupt Flag status bit before enable (mask) */

+

+/******************  Bit definition  for OTFDEC_ICR register  *****************/

+#define OTFDEC_ICR_SEIF_Pos                    (0U)

+#define OTFDEC_ICR_SEIF_Msk                    (0x1UL << OTFDEC_ICR_SEIF_Pos)                /*!< 0x00000001 */

+#define OTFDEC_ICR_SEIF                        OTFDEC_ICR_SEIF_Msk                           /*!< Security Error Interrupt Flag clear bit */

+

+#define OTFDEC_ICR_XONEIF_Pos                  (1U)

+#define OTFDEC_ICR_XONEIF_Msk                  (0x1UL << OTFDEC_ICR_XONEIF_Pos)              /*!< 0x00000002 */

+#define OTFDEC_ICR_XONEIF                      OTFDEC_ICR_XONEIF_Msk                         /*!< Execute-only Error Interrupt Flag clear bit */

+

+#define OTFDEC_ICR_KEIF_Pos                    (2U)

+#define OTFDEC_ICR_KEIF_Msk                    (0x1UL << OTFDEC_ICR_KEIF_Pos)                /*!< 0x00000004 */

+#define OTFDEC_ICR_KEIF                        OTFDEC_ICR_KEIF_Msk                           /*!< Key Error Interrupt Flag clear bit */

+

+/******************  Bit definition for OTFDEC_IER register  *****************/

+#define OTFDEC_IER_SEIE_Pos                    (0U)

+#define OTFDEC_IER_SEIE_Msk                    (0x1UL << OTFDEC_IER_SEIE_Pos)                /*!< 0x00000001 */

+#define OTFDEC_IER_SEIE                        OTFDEC_IER_SEIE_Msk                           /*!< Security Error Interrupt Enable bit */

+

+#define OTFDEC_IER_XONEIE_Pos                  (1U)

+#define OTFDEC_IER_XONEIE_Msk                  (0x1UL << OTFDEC_IER_XONEIE_Pos)              /*!< 0x00000002 */

+#define OTFDEC_IER_XONEIE                      OTFDEC_IER_XONEIE_Msk                         /*!< Execute-only Error Interrupt Enable bit */

+

+#define OTFDEC_IER_KEIE_Pos                    (2U)

+#define OTFDEC_IER_KEIE_Msk                    (0x1UL << OTFDEC_IER_KEIE_Pos)                /*!< 0x00000004 */

+#define OTFDEC_IER_KEIE                        OTFDEC_IER_KEIE_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                             Power Control                                  */

+/*                                                                            */

+/******************************************************************************/

+/*************************  NUMBER OF POWER DOMAINS  **************************/

+#define POWER_DOMAINS_NUMBER           2U                                      /*!< 2 Domains */

+

+/********************  Bit definition for PWR_CR1 register  *******************/

+#define PWR_CR1_SRDRAMSO_Pos           (27U)

+#define PWR_CR1_SRDRAMSO_Msk           (0x1UL << PWR_CR1_SRDRAMSO_Pos)         /*!< 0x08000000 */

+#define PWR_CR1_SRDRAMSO               PWR_CR1_SRDRAMSO_Msk                    /*!< SmartRun Domain AHB Memory Shut-Off in DStop/DStop2 Low-Power Mode */

+#define PWR_CR1_HSITFSO_Pos            (26U)

+#define PWR_CR1_HSITFSO_Msk            (0x1UL << PWR_CR1_HSITFSO_Pos)          /*!< 0x04000000 */

+#define PWR_CR1_HSITFSO                PWR_CR1_HSITFSO_Msk                     /*!< High-Speed Interfaces USB and FDCAN Memories Shut-off in DStop/DStop2 Mode */

+#define PWR_CR1_GFXSO_Pos              (25U)

+#define PWR_CR1_GFXSO_Msk              (0x1UL << PWR_CR1_GFXSO_Pos)            /*!< 0x02000000 */

+#define PWR_CR1_GFXSO                  PWR_CR1_GFXSO_Msk                       /*!< GFXMMU and JPEG Memories Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_ITCMSO_Pos             (24U)

+#define PWR_CR1_ITCMSO_Msk             (0x1UL << PWR_CR1_ITCMSO_Pos)           /*!< 0x01000000 */

+#define PWR_CR1_ITCMSO                 PWR_CR1_ITCMSO_Msk                      /*!< Instruction TCM and ETM Memories Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_AHBRAM2SO_Pos          (23U)

+#define PWR_CR1_AHBRAM2SO_Msk          (0x1UL << PWR_CR1_AHBRAM2SO_Pos)        /*!< 0x00800000 */

+#define PWR_CR1_AHBRAM2SO              PWR_CR1_AHBRAM2SO_Msk                   /*!< AHB RAM2 Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_AHBRAM1SO_Pos          (22U)

+#define PWR_CR1_AHBRAM1SO_Msk          (0x1UL << PWR_CR1_AHBRAM1SO_Pos)        /*!< 0x00400000 */

+#define PWR_CR1_AHBRAM1SO              PWR_CR1_AHBRAM1SO_Msk                   /*!< AHB RAM1 Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_AXIRAM3SO_Pos          (21U)

+#define PWR_CR1_AXIRAM3SO_Msk          (0x1UL << PWR_CR1_AXIRAM3SO_Pos)        /*!< 0x00200000 */

+#define PWR_CR1_AXIRAM3SO              PWR_CR1_AXIRAM3SO_Msk                   /*!< AXI RAM3 Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_AXIRAM2SO_Pos          (20U)

+#define PWR_CR1_AXIRAM2SO_Msk          (0x1UL << PWR_CR1_AXIRAM2SO_Pos)        /*!< 0x00100000 */

+#define PWR_CR1_AXIRAM2SO              PWR_CR1_AXIRAM2SO_Msk                   /*!< AXI RAM2 Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_AXIRAM1SO_Pos          (19U)

+#define PWR_CR1_AXIRAM1SO_Msk          (0x1UL << PWR_CR1_AXIRAM1SO_Pos)        /*!< 0x00080000 */

+#define PWR_CR1_AXIRAM1SO              PWR_CR1_AXIRAM1SO_Msk                   /*!< AXI RAM1 Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_ALS_Pos                (17U)

+#define PWR_CR1_ALS_Msk                (0x3UL << PWR_CR1_ALS_Pos)              /*!< 0x00060000 */

+#define PWR_CR1_ALS                    PWR_CR1_ALS_Msk                         /*!< Analog Voltage Detector level selection */

+#define PWR_CR1_ALS_0                  (0x1UL << PWR_CR1_ALS_Pos)              /*!< 0x00020000 */

+#define PWR_CR1_ALS_1                  (0x2UL << PWR_CR1_ALS_Pos)              /*!< 0x00040000 */

+#define PWR_CR1_AVDEN_Pos              (16U)

+#define PWR_CR1_AVDEN_Msk              (0x1UL << PWR_CR1_AVDEN_Pos)            /*!< 0x00010000 */

+#define PWR_CR1_AVDEN                  PWR_CR1_AVDEN_Msk                       /*!< Analog Voltage Detector Enable */

+#define PWR_CR1_SVOS_Pos               (14U)

+#define PWR_CR1_SVOS_Msk               (0x3UL << PWR_CR1_SVOS_Pos)             /*!< 0x0000C000 */

+#define PWR_CR1_SVOS                   PWR_CR1_SVOS_Msk                        /*!< System STOP mode Voltage Scaling selection */

+#define PWR_CR1_SVOS_0                 (0x1UL << PWR_CR1_SVOS_Pos)             /*!< 0x00004000 */

+#define PWR_CR1_SVOS_1                 (0x2UL << PWR_CR1_SVOS_Pos)             /*!< 0x00008000 */

+#define PWR_CR1_AVD_READY_Pos          (13U)

+#define PWR_CR1_AVD_READY_Msk          (0x1UL << PWR_CR1_AVD_READY_Pos)        /*!< 0x00002000 */

+#define PWR_CR1_AVD_READY              PWR_CR1_AVD_READY_Msk                   /*!< Analog Voltage Ready. */

+#define PWR_CR1_BOOSTE_Pos             (12U)

+#define PWR_CR1_BOOSTE_Msk             (0x1UL << PWR_CR1_BOOSTE_Pos)           /*!< 0x00001000 */

+#define PWR_CR1_BOOSTE                 PWR_CR1_BOOSTE_Msk                      /*!< Analog Switch VBoost control */

+#define PWR_CR1_FLPS_Pos               (9U)

+#define PWR_CR1_FLPS_Msk               (0x1UL << PWR_CR1_FLPS_Pos)             /*!< 0x00000200 */

+#define PWR_CR1_FLPS                   PWR_CR1_FLPS_Msk                        /*!< Flash low power mode in DSTOP */

+#define PWR_CR1_DBP_Pos                (8U)

+#define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */

+#define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable Back-up domain Protection */

+#define PWR_CR1_PLS_Pos                (5U)

+#define PWR_CR1_PLS_Msk                (0x7UL << PWR_CR1_PLS_Pos)              /*!< 0x000000E0 */

+#define PWR_CR1_PLS                    PWR_CR1_PLS_Msk                         /*!< Programmable Voltage Detector level selection */

+#define PWR_CR1_PLS_0                  (0x1UL << PWR_CR1_PLS_Pos)              /*!< 0x00000020 */

+#define PWR_CR1_PLS_1                  (0x2UL << PWR_CR1_PLS_Pos)              /*!< 0x00000040 */

+#define PWR_CR1_PLS_2                  (0x4UL << PWR_CR1_PLS_Pos)              /*!< 0x00000080 */

+#define PWR_CR1_PVDEN_Pos              (4U)

+#define PWR_CR1_PVDEN_Msk              (0x1UL << PWR_CR1_PVDEN_Pos)            /*!< 0x00000010 */

+#define PWR_CR1_PVDEN                  PWR_CR1_PVDEN_Msk                       /*!< Programmable Voltage detector enable */

+#define PWR_CR1_LPDS_Pos               (0U)

+#define PWR_CR1_LPDS_Msk               (0x1UL << PWR_CR1_LPDS_Pos)             /*!< 0x00000001 */

+#define PWR_CR1_LPDS                   PWR_CR1_LPDS_Msk                        /*!< Low Power Deepsleep with SVOS3 */

+

+/*!< PVD level configuration */

+#define PWR_CR1_PLS_LEV0               (0UL)                                   /*!< PVD level 0 */

+#define PWR_CR1_PLS_LEV1_Pos           (5U)

+#define PWR_CR1_PLS_LEV1_Msk           (0x1UL << PWR_CR1_PLS_LEV1_Pos)         /*!< 0x00000020 */

+#define PWR_CR1_PLS_LEV1               PWR_CR1_PLS_LEV1_Msk                    /*!< PVD level 1 */

+#define PWR_CR1_PLS_LEV2_Pos           (6U)

+#define PWR_CR1_PLS_LEV2_Msk           (0x1UL << PWR_CR1_PLS_LEV2_Pos)         /*!< 0x00000040 */

+#define PWR_CR1_PLS_LEV2               PWR_CR1_PLS_LEV2_Msk                    /*!< PVD level 2 */

+#define PWR_CR1_PLS_LEV3_Pos           (5U)

+#define PWR_CR1_PLS_LEV3_Msk           (0x3UL << PWR_CR1_PLS_LEV3_Pos)         /*!< 0x00000060 */

+#define PWR_CR1_PLS_LEV3               PWR_CR1_PLS_LEV3_Msk                    /*!< PVD level 3 */

+#define PWR_CR1_PLS_LEV4_Pos           (7U)

+#define PWR_CR1_PLS_LEV4_Msk           (0x1UL << PWR_CR1_PLS_LEV4_Pos)         /*!< 0x00000080 */

+#define PWR_CR1_PLS_LEV4               PWR_CR1_PLS_LEV4_Msk                    /*!< PVD level 4 */

+#define PWR_CR1_PLS_LEV5_Pos           (5U)

+#define PWR_CR1_PLS_LEV5_Msk           (0x5UL << PWR_CR1_PLS_LEV5_Pos)         /*!< 0x000000A0 */

+#define PWR_CR1_PLS_LEV5               PWR_CR1_PLS_LEV5_Msk                    /*!< PVD level 5 */

+#define PWR_CR1_PLS_LEV6_Pos           (6U)

+#define PWR_CR1_PLS_LEV6_Msk           (0x3UL << PWR_CR1_PLS_LEV6_Pos)         /*!< 0x000000C0 */

+#define PWR_CR1_PLS_LEV6               PWR_CR1_PLS_LEV6_Msk                    /*!< PVD level 6 */

+#define PWR_CR1_PLS_LEV7_Pos           (5U)

+#define PWR_CR1_PLS_LEV7_Msk           (0x7UL << PWR_CR1_PLS_LEV7_Pos)         /*!< 0x000000E0 */

+#define PWR_CR1_PLS_LEV7               PWR_CR1_PLS_LEV7_Msk                    /*!< PVD level 7 */

+

+/*!< AVD level configuration */

+#define PWR_CR1_ALS_LEV0               (0UL)                                   /*!< AVD level 0 */

+#define PWR_CR1_ALS_LEV1_Pos           (17U)

+#define PWR_CR1_ALS_LEV1_Msk           (0x1UL << PWR_CR1_ALS_LEV1_Pos)         /*!< 0x00020000 */

+#define PWR_CR1_ALS_LEV1               PWR_CR1_ALS_LEV1_Msk                    /*!< AVD level 1 */

+#define PWR_CR1_ALS_LEV2_Pos           (18U)

+#define PWR_CR1_ALS_LEV2_Msk           (0x1UL << PWR_CR1_ALS_LEV2_Pos)         /*!< 0x00040000 */

+#define PWR_CR1_ALS_LEV2               PWR_CR1_ALS_LEV2_Msk                    /*!< AVD level 2 */

+#define PWR_CR1_ALS_LEV3_Pos           (17U)

+#define PWR_CR1_ALS_LEV3_Msk           (0x3UL << PWR_CR1_ALS_LEV3_Pos)         /*!< 0x00060000 */

+#define PWR_CR1_ALS_LEV3               PWR_CR1_ALS_LEV3_Msk                    /*!< AVD level 3 */

+

+/********************  Bit definition for PWR_CSR1 register  ******************/

+#define PWR_CSR1_MMCVDO_Pos            (17U)

+#define PWR_CSR1_MMCVDO_Msk            (0x1UL << PWR_CSR1_MMCVDO_Pos)          /*!< 0x00020000                        */

+#define PWR_CSR1_MMCVDO                PWR_CSR1_MMCVDO_Msk                     /*!< voltage detector output on VDDMMC */

+#define PWR_CSR1_AVDO_Pos              (16U)

+#define PWR_CSR1_AVDO_Msk              (0x1UL << PWR_CSR1_AVDO_Pos)            /*!< 0x00010000 */

+#define PWR_CSR1_AVDO                  PWR_CSR1_AVDO_Msk                       /*!< Analog Voltage Detect Output */

+#define PWR_CSR1_ACTVOS_Pos            (14U)

+#define PWR_CSR1_ACTVOS_Msk            (0x3UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x0000C000 */

+#define PWR_CSR1_ACTVOS                PWR_CSR1_ACTVOS_Msk                     /*!< Current actual used VOS for VDD11 Voltage Scaling */

+#define PWR_CSR1_ACTVOS_0              (0x1UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00004000 */

+#define PWR_CSR1_ACTVOS_1              (0x2UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00008000 */

+#define PWR_CSR1_ACTVOSRDY_Pos         (13U)

+#define PWR_CSR1_ACTVOSRDY_Msk         (0x1UL << PWR_CSR1_ACTVOSRDY_Pos)       /*!< 0x00002000 */

+#define PWR_CSR1_ACTVOSRDY             PWR_CSR1_ACTVOSRDY_Msk                  /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling  */

+#define PWR_CSR1_PVDO_Pos              (4U)

+#define PWR_CSR1_PVDO_Msk              (0x1UL << PWR_CSR1_PVDO_Pos)            /*!< 0x00000010 */

+#define PWR_CSR1_PVDO                  PWR_CSR1_PVDO_Msk                       /*!< Programmable Voltage Detect Output */

+

+/********************  Bit definition for PWR_CR2 register  *******************/

+#define PWR_CR2_TEMPH_Pos              (23U)

+#define PWR_CR2_TEMPH_Msk              (0x1UL << PWR_CR2_TEMPH_Pos)            /*!< 0x00800000 */

+#define PWR_CR2_TEMPH                  PWR_CR2_TEMPH_Msk                       /*!< Monitored temperature level above high threshold */

+#define PWR_CR2_TEMPL_Pos              (22U)

+#define PWR_CR2_TEMPL_Msk              (0x1UL << PWR_CR2_TEMPL_Pos)            /*!< 0x00400000 */

+#define PWR_CR2_TEMPL                  PWR_CR2_TEMPL_Msk                       /*!< Monitored temperature level above low threshold */

+#define PWR_CR2_VBATH_Pos              (21U)

+#define PWR_CR2_VBATH_Msk              (0x1UL << PWR_CR2_VBATH_Pos)            /*!< 0x00200000 */

+#define PWR_CR2_VBATH                  PWR_CR2_VBATH_Msk                       /*!< Monitored VBAT level above high threshold */

+#define PWR_CR2_VBATL_Pos              (20U)

+#define PWR_CR2_VBATL_Msk              (0x1UL << PWR_CR2_VBATL_Pos)            /*!< 0x00100000 */

+#define PWR_CR2_VBATL                  PWR_CR2_VBATL_Msk                       /*!< Monitored VBAT level above low threshold */

+#define PWR_CR2_BRRDY_Pos              (16U)

+#define PWR_CR2_BRRDY_Msk              (0x1UL << PWR_CR2_BRRDY_Pos)            /*!< 0x00010000 */

+#define PWR_CR2_BRRDY                  PWR_CR2_BRRDY_Msk                       /*!< Backup regulator ready */

+#define PWR_CR2_MONEN_Pos              (4U)

+#define PWR_CR2_MONEN_Msk              (0x1UL << PWR_CR2_MONEN_Pos)            /*!< 0x00000010 */

+#define PWR_CR2_MONEN                  PWR_CR2_MONEN_Msk                       /*!< VBAT and temperature monitoring enable */

+#define PWR_CR2_BREN_Pos               (0U)

+#define PWR_CR2_BREN_Msk               (0x1UL << PWR_CR2_BREN_Pos)             /*!< 0x00000001 */

+#define PWR_CR2_BREN                   PWR_CR2_BREN_Msk                        /*!< Backup regulator enable */

+

+/********************  Bit definition for PWR_CR3 register  *******************/

+#define PWR_CR3_USB33RDY_Pos           (26U)

+#define PWR_CR3_USB33RDY_Msk           (0x1UL << PWR_CR3_USB33RDY_Pos)         /*!< 0x04000000 */

+#define PWR_CR3_USB33RDY               PWR_CR3_USB33RDY_Msk                    /*!< USB supply ready */

+#define PWR_CR3_USBREGEN_Pos           (25U)

+#define PWR_CR3_USBREGEN_Msk           (0x1UL << PWR_CR3_USBREGEN_Pos)         /*!< 0x02000000 */

+#define PWR_CR3_USBREGEN               PWR_CR3_USBREGEN_Msk                    /*!< USB regulator enable */

+#define PWR_CR3_USB33DEN_Pos           (24U)

+#define PWR_CR3_USB33DEN_Msk           (0x1UL << PWR_CR3_USB33DEN_Pos)         /*!< 0x01000000 */

+#define PWR_CR3_USB33DEN               PWR_CR3_USB33DEN_Msk                    /*!< VDD33_USB voltage level detector enable */

+#define PWR_CR3_VBRS_Pos               (9U)

+#define PWR_CR3_VBRS_Msk               (0x1UL << PWR_CR3_VBRS_Pos)             /*!< 0x00000200 */

+#define PWR_CR3_VBRS                   PWR_CR3_VBRS_Msk                        /*!< VBAT charging resistor selection */

+#define PWR_CR3_VBE_Pos                (8U)

+#define PWR_CR3_VBE_Msk                (0x1UL << PWR_CR3_VBE_Pos)              /*!< 0x00000100 */

+#define PWR_CR3_VBE                    PWR_CR3_VBE_Msk                         /*!< VBAT charging enable */

+#define PWR_CR3_SCUEN_Pos              (2U)

+#define PWR_CR3_SCUEN_Msk              (0x1UL << PWR_CR3_SCUEN_Pos)            /*!< 0x00000004 */

+#define PWR_CR3_SCUEN                  PWR_CR3_SCUEN_Msk                       /*!< Supply configuration update enable */

+#define PWR_CR3_LDOEN_Pos              (1U)

+#define PWR_CR3_LDOEN_Msk              (0x1UL << PWR_CR3_LDOEN_Pos)            /*!< 0x00000002 */

+#define PWR_CR3_LDOEN                  PWR_CR3_LDOEN_Msk                       /*!< Low Drop Output regulator enable */

+#define PWR_CR3_BYPASS_Pos             (0U)

+#define PWR_CR3_BYPASS_Msk             (0x1UL << PWR_CR3_BYPASS_Pos)           /*!< 0x00000001 */

+#define PWR_CR3_BYPASS                 PWR_CR3_BYPASS_Msk                      /*!< Power Management Unit bypass */

+

+/********************  Bit definition for PWR_CPUCR register  *****************/

+#define PWR_CPUCR_RUN_SRD_Pos          (11U)

+#define PWR_CPUCR_RUN_SRD_Msk          (0x1UL << PWR_CPUCR_RUN_SRD_Pos)        /*!< 0x00000800 */

+#define PWR_CPUCR_RUN_SRD              PWR_CPUCR_RUN_SRD_Msk                   /*!< Keep system SRD domain in RUN mode regardless of the CPU sub-systems modes */

+#define PWR_CPUCR_CSSF_Pos             (9U)

+#define PWR_CPUCR_CSSF_Msk             (0x1UL << PWR_CPUCR_CSSF_Pos)           /*!< 0x00000200 */

+#define PWR_CPUCR_CSSF                 PWR_CPUCR_CSSF_Msk                      /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */

+#define PWR_CPUCR_SBF_Pos              (6U)

+#define PWR_CPUCR_SBF_Msk              (0x1UL << PWR_CPUCR_SBF_Pos)            /*!< 0x00000040 */

+#define PWR_CPUCR_SBF                  PWR_CPUCR_SBF_Msk                       /*!< System STANDBY Flag */

+#define PWR_CPUCR_STOPF_Pos            (5U)

+#define PWR_CPUCR_STOPF_Msk            (0x1UL << PWR_CPUCR_STOPF_Pos)          /*!< 0x00000020 */

+#define PWR_CPUCR_STOPF                PWR_CPUCR_STOPF_Msk                     /*!< STOP Flag */

+#define PWR_CPUCR_PDDS_SRD_Pos         (2U)

+#define PWR_CPUCR_PDDS_SRD_Msk         (0x1UL << PWR_CPUCR_PDDS_SRD_Pos)       /*!< 0x00000004 */

+#define PWR_CPUCR_PDDS_SRD             PWR_CPUCR_PDDS_SRD_Msk                  /*!< System SRD domain Power Down Deepsleep */

+#define PWR_CPUCR_RETDS_CD_Pos         (0U)

+#define PWR_CPUCR_RETDS_CD_Msk         (0x1UL << PWR_CPUCR_RETDS_CD_Pos)       /*!< 0x00000001 */

+#define PWR_CPUCR_RETDS_CD             PWR_CPUCR_RETDS_CD_Msk                  /*!< CD domain Power Down Deepsleep selection */

+/********************  Bit definition for PWR_SRDCR register  *****************/

+#define PWR_SRDCR_VOS_Pos              (14U)

+#define PWR_SRDCR_VOS_Msk              (0x3UL << PWR_SRDCR_VOS_Pos)             /*!< 0x0000C000 */

+#define PWR_SRDCR_VOS                  PWR_SRDCR_VOS_Msk                        /*!< Voltage Scaling selection according performance */

+#define PWR_SRDCR_VOS_0                (0x1UL << PWR_SRDCR_VOS_Pos)             /*!< 0x00004000 */

+#define PWR_SRDCR_VOS_1                (0x2UL << PWR_SRDCR_VOS_Pos)             /*!< 0x00008000 */

+#define PWR_SRDCR_VOSRDY_Pos           (13U)

+#define PWR_SRDCR_VOSRDY_Msk           (0x1UL << PWR_SRDCR_VOSRDY_Pos)          /*!< 0x00002000 */

+#define PWR_SRDCR_VOSRDY               PWR_SRDCR_VOSRDY_Msk                     /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */

+/******************  Bit definition for PWR_WKUPCR register  ******************/

+#define PWR_WKUPCR_WKUPC6_Pos          (5U)

+#define PWR_WKUPCR_WKUPC6_Msk          (0x1UL << PWR_WKUPCR_WKUPC6_Pos)        /*!< 0x00000020 */

+#define PWR_WKUPCR_WKUPC6              PWR_WKUPCR_WKUPC6_Msk                   /*!< Clear Wakeup Pin Flag 6 */

+#define PWR_WKUPCR_WKUPC5_Pos          (4U)

+#define PWR_WKUPCR_WKUPC5_Msk          (0x1UL << PWR_WKUPCR_WKUPC5_Pos)        /*!< 0x00000010 */

+#define PWR_WKUPCR_WKUPC5              PWR_WKUPCR_WKUPC5_Msk                   /*!< Clear Wakeup Pin Flag 5 */

+#define PWR_WKUPCR_WKUPC4_Pos          (3U)

+#define PWR_WKUPCR_WKUPC4_Msk          (0x1UL << PWR_WKUPCR_WKUPC4_Pos)        /*!< 0x00000008 */

+#define PWR_WKUPCR_WKUPC4              PWR_WKUPCR_WKUPC4_Msk                   /*!< Clear Wakeup Pin Flag 4 */

+#define PWR_WKUPCR_WKUPC3_Pos          (2U)

+#define PWR_WKUPCR_WKUPC3_Msk          (0x1UL << PWR_WKUPCR_WKUPC3_Pos)        /*!< 0x00000004 */

+#define PWR_WKUPCR_WKUPC3              PWR_WKUPCR_WKUPC3_Msk                   /*!< Clear Wakeup Pin Flag 3 */

+#define PWR_WKUPCR_WKUPC2_Pos          (1U)

+#define PWR_WKUPCR_WKUPC2_Msk          (0x1UL << PWR_WKUPCR_WKUPC2_Pos)        /*!< 0x00000002 */

+#define PWR_WKUPCR_WKUPC2              PWR_WKUPCR_WKUPC2_Msk                   /*!< Clear Wakeup Pin Flag 2 */

+#define PWR_WKUPCR_WKUPC1_Pos          (0U)

+#define PWR_WKUPCR_WKUPC1_Msk          (0x1UL << PWR_WKUPCR_WKUPC1_Pos)        /*!< 0x00000001 */

+#define PWR_WKUPCR_WKUPC1              PWR_WKUPCR_WKUPC1_Msk                   /*!< Clear Wakeup Pin Flag 1 */

+

+/********************  Bit definition for PWR_WKUPFR register  ****************/

+#define PWR_WKUPFR_WKUPF6_Pos          (5U)

+#define PWR_WKUPFR_WKUPF6_Msk          (0x1UL << PWR_WKUPFR_WKUPF6_Pos)        /*!< 0x00000020 */

+#define PWR_WKUPFR_WKUPF6              PWR_WKUPFR_WKUPF6_Msk                   /*!< Wakeup Pin Flag 6 */

+#define PWR_WKUPFR_WKUPF5_Pos          (4U)

+#define PWR_WKUPFR_WKUPF5_Msk          (0x1UL << PWR_WKUPFR_WKUPF5_Pos)        /*!< 0x00000010 */

+#define PWR_WKUPFR_WKUPF5              PWR_WKUPFR_WKUPF5_Msk                   /*!< Wakeup Pin Flag 5 */

+#define PWR_WKUPFR_WKUPF4_Pos          (3U)

+#define PWR_WKUPFR_WKUPF4_Msk          (0x1UL << PWR_WKUPFR_WKUPF4_Pos)        /*!< 0x00000008 */

+#define PWR_WKUPFR_WKUPF4              PWR_WKUPFR_WKUPF4_Msk                   /*!< Wakeup Pin Flag 4 */

+#define PWR_WKUPFR_WKUPF3_Pos          (2U)

+#define PWR_WKUPFR_WKUPF3_Msk          (0x1UL << PWR_WKUPFR_WKUPF3_Pos)        /*!< 0x00000004 */

+#define PWR_WKUPFR_WKUPF3              PWR_WKUPFR_WKUPF3_Msk                   /*!< Wakeup Pin Flag 3 */

+#define PWR_WKUPFR_WKUPF2_Pos          (1U)

+#define PWR_WKUPFR_WKUPF2_Msk          (0x1UL << PWR_WKUPFR_WKUPF2_Pos)        /*!< 0x00000002 */

+#define PWR_WKUPFR_WKUPF2              PWR_WKUPFR_WKUPF2_Msk                   /*!< Wakeup Pin Flag 2 */

+#define PWR_WKUPFR_WKUPF1_Pos          (0U)

+#define PWR_WKUPFR_WKUPF1_Msk          (0x1UL << PWR_WKUPFR_WKUPF1_Pos)        /*!< 0x00000001 */

+#define PWR_WKUPFR_WKUPF1              PWR_WKUPFR_WKUPF1_Msk                   /*!< Wakeup Pin Flag 1 */

+

+/******************  Bit definition for PWR_WKUPEPR register  *****************/

+#define PWR_WKUPEPR_WKUPPUPD6_Pos      (26U)

+#define PWR_WKUPEPR_WKUPPUPD6_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x0C000000 */

+#define PWR_WKUPEPR_WKUPPUPD6          PWR_WKUPEPR_WKUPPUPD6_Msk               /*!< Wakeup Pin pull configuration for WKUP6 */

+#define PWR_WKUPEPR_WKUPPUPD6_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x04000000 */

+#define PWR_WKUPEPR_WKUPPUPD6_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x08000000 */

+#define PWR_WKUPEPR_WKUPPUPD5_Pos      (24U)

+#define PWR_WKUPEPR_WKUPPUPD5_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x03000000 */

+#define PWR_WKUPEPR_WKUPPUPD5          PWR_WKUPEPR_WKUPPUPD5_Msk               /*!< Wakeup Pin pull configuration for WKUP5 */

+#define PWR_WKUPEPR_WKUPPUPD5_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x01000000 */

+#define PWR_WKUPEPR_WKUPPUPD5_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x02000000 */

+#define PWR_WKUPEPR_WKUPPUPD4_Pos      (22U)

+#define PWR_WKUPEPR_WKUPPUPD4_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00C00000 */

+#define PWR_WKUPEPR_WKUPPUPD4          PWR_WKUPEPR_WKUPPUPD4_Msk               /*!< Wakeup Pin pull configuration for WKUP4 */

+#define PWR_WKUPEPR_WKUPPUPD4_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00400000 */

+#define PWR_WKUPEPR_WKUPPUPD4_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00800000 */

+#define PWR_WKUPEPR_WKUPPUPD3_Pos      (20U)

+#define PWR_WKUPEPR_WKUPPUPD3_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00300000 */

+#define PWR_WKUPEPR_WKUPPUPD3          PWR_WKUPEPR_WKUPPUPD3_Msk               /*!< Wakeup Pin pull configuration for WKUP3 */

+#define PWR_WKUPEPR_WKUPPUPD3_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00100000 */

+#define PWR_WKUPEPR_WKUPPUPD3_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00200000 */

+#define PWR_WKUPEPR_WKUPPUPD2_Pos      (18U)

+#define PWR_WKUPEPR_WKUPPUPD2_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x000C0000 */

+#define PWR_WKUPEPR_WKUPPUPD2          PWR_WKUPEPR_WKUPPUPD2_Msk               /*!< Wakeup Pin pull configuration for WKUP2 */

+#define PWR_WKUPEPR_WKUPPUPD2_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00040000 */

+#define PWR_WKUPEPR_WKUPPUPD2_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00080000 */

+#define PWR_WKUPEPR_WKUPPUPD1_Pos      (16U)

+#define PWR_WKUPEPR_WKUPPUPD1_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00030000 */

+#define PWR_WKUPEPR_WKUPPUPD1          PWR_WKUPEPR_WKUPPUPD1_Msk               /*!< Wakeup Pin pull configuration for WKUP1 */

+#define PWR_WKUPEPR_WKUPPUPD1_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00010000 */

+#define PWR_WKUPEPR_WKUPPUPD1_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00020000 */

+#define PWR_WKUPEPR_WKUPP6_Pos         (13U)

+#define PWR_WKUPEPR_WKUPP6_Msk         (0x1UL << PWR_WKUPEPR_WKUPP6_Pos)       /*!< 0x00002000 */

+#define PWR_WKUPEPR_WKUPP6             PWR_WKUPEPR_WKUPP6_Msk                  /*!< Wakeup Pin Polarity for WKUP6 */

+#define PWR_WKUPEPR_WKUPP5_Pos         (12U)

+#define PWR_WKUPEPR_WKUPP5_Msk         (0x1UL << PWR_WKUPEPR_WKUPP5_Pos)       /*!< 0x00001000 */

+#define PWR_WKUPEPR_WKUPP5             PWR_WKUPEPR_WKUPP5_Msk                  /*!< Wakeup Pin Polarity for WKUP5 */

+#define PWR_WKUPEPR_WKUPP4_Pos         (11U)

+#define PWR_WKUPEPR_WKUPP4_Msk         (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)       /*!< 0x00000800 */

+#define PWR_WKUPEPR_WKUPP4             PWR_WKUPEPR_WKUPP4_Msk                  /*!< Wakeup Pin Polarity for WKUP4 */

+#define PWR_WKUPEPR_WKUPP3_Pos         (10U)

+#define PWR_WKUPEPR_WKUPP3_Msk         (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)       /*!< 0x00000400 */

+#define PWR_WKUPEPR_WKUPP3             PWR_WKUPEPR_WKUPP3_Msk                  /*!< Wakeup Pin Polarity for WKUP3 */

+#define PWR_WKUPEPR_WKUPP2_Pos         (9U)

+#define PWR_WKUPEPR_WKUPP2_Msk         (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)       /*!< 0x00000200 */

+#define PWR_WKUPEPR_WKUPP2             PWR_WKUPEPR_WKUPP2_Msk                  /*!< Wakeup Pin Polarity for WKUP2 */

+#define PWR_WKUPEPR_WKUPP1_Pos         (8U)

+#define PWR_WKUPEPR_WKUPP1_Msk         (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)       /*!< 0x00000100 */

+#define PWR_WKUPEPR_WKUPP1             PWR_WKUPEPR_WKUPP1_Msk                  /*!< Wakeup Pin Polarity for WKUP1 */

+#define PWR_WKUPEPR_WKUPEN6_Pos        (5U)

+#define PWR_WKUPEPR_WKUPEN6_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos)      /*!< 0x00000020 */

+#define PWR_WKUPEPR_WKUPEN6            PWR_WKUPEPR_WKUPEN6_Msk                 /*!< Enable Wakeup Pin WKUP6 */

+#define PWR_WKUPEPR_WKUPEN5_Pos        (4U)

+#define PWR_WKUPEPR_WKUPEN5_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos)      /*!< 0x00000010 */

+#define PWR_WKUPEPR_WKUPEN5            PWR_WKUPEPR_WKUPEN5_Msk                 /*!< Enable Wakeup Pin WKUP5 */

+#define PWR_WKUPEPR_WKUPEN4_Pos        (3U)

+#define PWR_WKUPEPR_WKUPEN4_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)      /*!< 0x00000008 */

+#define PWR_WKUPEPR_WKUPEN4            PWR_WKUPEPR_WKUPEN4_Msk                 /*!< Enable Wakeup Pin WKUP4 */

+#define PWR_WKUPEPR_WKUPEN3_Pos        (2U)

+#define PWR_WKUPEPR_WKUPEN3_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)      /*!< 0x00000004 */

+#define PWR_WKUPEPR_WKUPEN3            PWR_WKUPEPR_WKUPEN3_Msk                 /*!< Enable Wakeup Pin WKUP3 */

+#define PWR_WKUPEPR_WKUPEN2_Pos        (1U)

+#define PWR_WKUPEPR_WKUPEN2_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)      /*!< 0x00000002 */

+#define PWR_WKUPEPR_WKUPEN2            PWR_WKUPEPR_WKUPEN2_Msk                 /*!< Enable Wakeup Pin WKUP2 */

+#define PWR_WKUPEPR_WKUPEN1_Pos        (0U)

+#define PWR_WKUPEPR_WKUPEN1_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)      /*!< 0x00000001 */

+#define PWR_WKUPEPR_WKUPEN1            PWR_WKUPEPR_WKUPEN1_Msk                 /*!< Enable Wakeup Pin WKUP1 */

+#define PWR_WKUPEPR_WKUPEN_Pos         (0U)

+#define PWR_WKUPEPR_WKUPEN_Msk         (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos)      /*!< 0x0000003F */

+#define PWR_WKUPEPR_WKUPEN             PWR_WKUPEPR_WKUPEN_Msk                  /*!< Enable all Wakeup Pin */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Reset and Clock Control                            */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  RCC VERSION  ********************************/

+#define RCC_VER_2_0

+

+/********************  Bit definition for RCC_CR register  ********************/

+#define RCC_CR_HSION_Pos                       (0U)

+#define RCC_CR_HSION_Msk                       (0x1UL << RCC_CR_HSION_Pos)     /*!< 0x00000001 */

+#define RCC_CR_HSION                           RCC_CR_HSION_Msk                /*!< Internal High Speed clock enable */

+#define RCC_CR_HSIKERON_Pos                    (1U)

+#define RCC_CR_HSIKERON_Msk                    (0x1UL << RCC_CR_HSIKERON_Pos)  /*!< 0x00000002 */

+#define RCC_CR_HSIKERON                        RCC_CR_HSIKERON_Msk             /*!< Internal High Speed clock enable for some IPs Kernel */

+#define RCC_CR_HSIRDY_Pos                      (2U)

+#define RCC_CR_HSIRDY_Msk                      (0x1UL << RCC_CR_HSIRDY_Pos)    /*!< 0x00000004 */

+#define RCC_CR_HSIRDY                          RCC_CR_HSIRDY_Msk               /*!< Internal High Speed clock ready flag */

+#define RCC_CR_HSIDIV_Pos                      (3U)

+#define RCC_CR_HSIDIV_Msk                      (0x3UL << RCC_CR_HSIDIV_Pos)    /*!< 0x00000018 */

+#define RCC_CR_HSIDIV                          RCC_CR_HSIDIV_Msk               /*!< Internal High Speed clock divider selection */

+#define RCC_CR_HSIDIV_1                        (0x0UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000000 */

+#define RCC_CR_HSIDIV_2                        (0x1UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000008 */

+#define RCC_CR_HSIDIV_4                        (0x2UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000010 */

+#define RCC_CR_HSIDIV_8                        (0x3UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000018 */

+

+#define RCC_CR_HSIDIVF_Pos                     (5U)

+#define RCC_CR_HSIDIVF_Msk                     (0x1UL << RCC_CR_HSIDIVF_Pos)   /*!< 0x00000020 */

+#define RCC_CR_HSIDIVF                         RCC_CR_HSIDIVF_Msk              /*!< HSI Divider flag */

+#define RCC_CR_CSION_Pos                       (7U)

+#define RCC_CR_CSION_Msk                       (0x1UL << RCC_CR_CSION_Pos)     /*!< 0x00000080 */

+#define RCC_CR_CSION                           RCC_CR_CSION_Msk                /*!< The Internal RC 4MHz oscillator clock enable */

+#define RCC_CR_CSIRDY_Pos                      (8U)

+#define RCC_CR_CSIRDY_Msk                      (0x1UL << RCC_CR_CSIRDY_Pos)    /*!< 0x00000100 */

+#define RCC_CR_CSIRDY                          RCC_CR_CSIRDY_Msk               /*!< The Internal RC 4MHz oscillator clock ready */

+#define RCC_CR_CSIKERON_Pos                    (9U)

+#define RCC_CR_CSIKERON_Msk                    (0x1UL << RCC_CR_CSIKERON_Pos)  /*!< 0x00000200 */

+#define RCC_CR_CSIKERON                        RCC_CR_CSIKERON_Msk             /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */

+#define RCC_CR_HSI48ON_Pos                     (12U)

+#define RCC_CR_HSI48ON_Msk                     (0x1UL << RCC_CR_HSI48ON_Pos)   /*!< 0x00001000 */

+#define RCC_CR_HSI48ON                         RCC_CR_HSI48ON_Msk              /*!< HSI48 clock enable clock enable  */

+#define RCC_CR_HSI48RDY_Pos                    (13U)

+#define RCC_CR_HSI48RDY_Msk                    (0x1UL << RCC_CR_HSI48RDY_Pos)  /*!< 0x00002000 */

+#define RCC_CR_HSI48RDY                        RCC_CR_HSI48RDY_Msk             /*!< HSI48 clock ready */

+

+#define RCC_CR_CPUCKRDY_Pos                     (14U)

+#define RCC_CR_CPUCKRDY_Msk                     (0x1UL << RCC_CR_CPUCKRDY_Pos)   /*!< 0x00004000 */

+#define RCC_CR_CPUCKRDY                         RCC_CR_CPUCKRDY_Msk              /*!< CPU domain clocks ready flag  */

+#define RCC_CR_CDCKRDY_Pos                     (15U)

+#define RCC_CR_CDCKRDY_Msk                     (0x1UL << RCC_CR_CDCKRDY_Pos)   /*!< 0x00008000 */

+#define RCC_CR_CDCKRDY                         RCC_CR_CDCKRDY_Msk              /*!< CD domain clocks ready flag */

+

+#define RCC_CR_HSEON_Pos                       (16U)

+#define RCC_CR_HSEON_Msk                       (0x1UL << RCC_CR_HSEON_Pos)     /*!< 0x00010000 */

+#define RCC_CR_HSEON                           RCC_CR_HSEON_Msk                /*!< External High Speed clock enable */

+#define RCC_CR_HSERDY_Pos                      (17U)

+#define RCC_CR_HSERDY_Msk                      (0x1UL << RCC_CR_HSERDY_Pos)    /*!< 0x00020000 */

+#define RCC_CR_HSERDY                          RCC_CR_HSERDY_Msk               /*!< External High Speed clock ready */

+#define RCC_CR_HSEBYP_Pos                      (18U)

+#define RCC_CR_HSEBYP_Msk                      (0x1UL << RCC_CR_HSEBYP_Pos)    /*!< 0x00040000 */

+#define RCC_CR_HSEBYP                          RCC_CR_HSEBYP_Msk               /*!< External High Speed clock Bypass */

+#define RCC_CR_CSSHSEON_Pos                    (19U)

+#define RCC_CR_CSSHSEON_Msk                    (0x1UL << RCC_CR_CSSHSEON_Pos)  /*!< 0x00080000 */

+#define RCC_CR_CSSHSEON                        RCC_CR_CSSHSEON_Msk             /*!< HSE Clock security System enable */

+

+#define RCC_CR_HSEEXT_Pos                    (20U)

+#define RCC_CR_HSEEXT_Msk                    (0x1UL << RCC_CR_HSEEXT_Pos)  /*!< 0x00080000 */

+#define RCC_CR_HSEEXT                        RCC_CR_HSEEXT_Msk             /*!< HSE Clock security System enable */

+

+#define RCC_CR_PLL1ON_Pos                      (24U)

+#define RCC_CR_PLL1ON_Msk                      (0x1UL << RCC_CR_PLL1ON_Pos)    /*!< 0x01000000 */

+#define RCC_CR_PLL1ON                          RCC_CR_PLL1ON_Msk               /*!< System PLL1 clock enable */

+#define RCC_CR_PLL1RDY_Pos                     (25U)

+#define RCC_CR_PLL1RDY_Msk                     (0x1UL << RCC_CR_PLL1RDY_Pos)   /*!< 0x02000000 */

+#define RCC_CR_PLL1RDY                         RCC_CR_PLL1RDY_Msk              /*!< System PLL1 clock ready */

+#define RCC_CR_PLL2ON_Pos                      (26U)

+#define RCC_CR_PLL2ON_Msk                      (0x1UL << RCC_CR_PLL2ON_Pos)    /*!< 0x04000000 */

+#define RCC_CR_PLL2ON                          RCC_CR_PLL2ON_Msk               /*!< System PLL2 clock enable */

+#define RCC_CR_PLL2RDY_Pos                     (27U)

+#define RCC_CR_PLL2RDY_Msk                     (0x1UL << RCC_CR_PLL2RDY_Pos)   /*!< 0x08000000 */

+#define RCC_CR_PLL2RDY                         RCC_CR_PLL2RDY_Msk              /*!< System PLL2 clock ready */

+#define RCC_CR_PLL3ON_Pos                      (28U)

+#define RCC_CR_PLL3ON_Msk                      (0x1UL << RCC_CR_PLL3ON_Pos)    /*!< 0x10000000 */

+#define RCC_CR_PLL3ON                          RCC_CR_PLL3ON_Msk               /*!< System PLL3 clock enable */

+#define RCC_CR_PLL3RDY_Pos                     (29U)

+#define RCC_CR_PLL3RDY_Msk                     (0x1UL << RCC_CR_PLL3RDY_Pos)   /*!< 0x20000000 */

+#define RCC_CR_PLL3RDY                         RCC_CR_PLL3RDY_Msk              /*!< System PLL3 clock ready */

+

+/*Legacy */

+#define RCC_CR_PLLON_Pos                       (24U)

+#define RCC_CR_PLLON_Msk                       (0x1UL << RCC_CR_PLLON_Pos)     /*!< 0x01000000 */

+#define RCC_CR_PLLON                           RCC_CR_PLLON_Msk                /*!< System PLL clock enable */

+#define RCC_CR_PLLRDY_Pos                      (25U)

+#define RCC_CR_PLLRDY_Msk                      (0x1UL << RCC_CR_PLLRDY_Pos)    /*!< 0x02000000 */

+#define RCC_CR_PLLRDY                          RCC_CR_PLLRDY_Msk               /*!< System PLL clock ready */

+

+/********************  Bit definition for RCC_HSICFGR register  ***************/

+/*!< HSICAL configuration */

+#define RCC_HSICFGR_HSICAL_Pos                 (0U)

+#define RCC_HSICFGR_HSICAL_Msk                 (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */

+#define RCC_HSICFGR_HSICAL                     RCC_HSICFGR_HSICAL_Msk          /*!< HSICAL[11:0] bits */

+#define RCC_HSICFGR_HSICAL_0                   (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */

+#define RCC_HSICFGR_HSICAL_1                   (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */

+#define RCC_HSICFGR_HSICAL_2                   (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */

+#define RCC_HSICFGR_HSICAL_3                   (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */

+#define RCC_HSICFGR_HSICAL_4                   (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */

+#define RCC_HSICFGR_HSICAL_5                   (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */

+#define RCC_HSICFGR_HSICAL_6                   (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */

+#define RCC_HSICFGR_HSICAL_7                   (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */

+#define RCC_HSICFGR_HSICAL_8                   (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */

+#define RCC_HSICFGR_HSICAL_9                   (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */

+#define RCC_HSICFGR_HSICAL_10                  (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */

+#define RCC_HSICFGR_HSICAL_11                  (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */

+

+/*!< HSITRIM configuration */

+#define RCC_HSICFGR_HSITRIM_Pos                (24U)

+#define RCC_HSICFGR_HSITRIM_Msk                (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */

+#define RCC_HSICFGR_HSITRIM                    RCC_HSICFGR_HSITRIM_Msk         /*!< HSITRIM[6:0] bits */

+#define RCC_HSICFGR_HSITRIM_0                  (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */

+#define RCC_HSICFGR_HSITRIM_1                  (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */

+#define RCC_HSICFGR_HSITRIM_2                  (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */

+#define RCC_HSICFGR_HSITRIM_3                  (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */

+#define RCC_HSICFGR_HSITRIM_4                  (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */

+#define RCC_HSICFGR_HSITRIM_5                  (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */

+#define RCC_HSICFGR_HSITRIM_6                  (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */

+

+

+/********************  Bit definition for RCC_CRRCR register  *****************/

+

+/*!< HSI48CAL configuration */

+#define RCC_CRRCR_HSI48CAL_Pos                 (0U)

+#define RCC_CRRCR_HSI48CAL_Msk                 (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */

+#define RCC_CRRCR_HSI48CAL                     RCC_CRRCR_HSI48CAL_Msk          /*!< HSI48CAL[9:0] bits */

+#define RCC_CRRCR_HSI48CAL_0                   (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */

+#define RCC_CRRCR_HSI48CAL_1                   (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */

+#define RCC_CRRCR_HSI48CAL_2                   (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */

+#define RCC_CRRCR_HSI48CAL_3                   (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */

+#define RCC_CRRCR_HSI48CAL_4                   (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */

+#define RCC_CRRCR_HSI48CAL_5                   (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */

+#define RCC_CRRCR_HSI48CAL_6                   (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */

+#define RCC_CRRCR_HSI48CAL_7                   (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */

+#define RCC_CRRCR_HSI48CAL_8                   (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */

+#define RCC_CRRCR_HSI48CAL_9                   (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */

+

+

+/********************  Bit definition for RCC_CSICFGR register  *****************/

+/*!< CSICAL configuration */

+#define RCC_CSICFGR_CSICAL_Pos                 (0U)

+#define RCC_CSICFGR_CSICAL_Msk                 (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */

+#define RCC_CSICFGR_CSICAL                     RCC_CSICFGR_CSICAL_Msk          /*!< CSICAL[7:0] bits */

+#define RCC_CSICFGR_CSICAL_0                   (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */

+#define RCC_CSICFGR_CSICAL_1                   (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */

+#define RCC_CSICFGR_CSICAL_2                   (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */

+#define RCC_CSICFGR_CSICAL_3                   (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */

+#define RCC_CSICFGR_CSICAL_4                   (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */

+#define RCC_CSICFGR_CSICAL_5                   (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */

+#define RCC_CSICFGR_CSICAL_6                   (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */

+#define RCC_CSICFGR_CSICAL_7                   (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */

+

+/*!< CSITRIM configuration */

+#define RCC_CSICFGR_CSITRIM_Pos                (24U)

+#define RCC_CSICFGR_CSITRIM_Msk                (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */

+#define RCC_CSICFGR_CSITRIM                    RCC_CSICFGR_CSITRIM_Msk         /*!< CSITRIM[5:0] bits */

+#define RCC_CSICFGR_CSITRIM_0                  (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */

+#define RCC_CSICFGR_CSITRIM_1                  (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */

+#define RCC_CSICFGR_CSITRIM_2                  (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */

+#define RCC_CSICFGR_CSITRIM_3                  (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */

+#define RCC_CSICFGR_CSITRIM_4                  (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */

+#define RCC_CSICFGR_CSITRIM_5                  (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */

+

+/********************  Bit definition for RCC_CFGR register  ******************/

+/*!< SW configuration */

+#define RCC_CFGR_SW_Pos                        (0U)

+#define RCC_CFGR_SW_Msk                        (0x7UL << RCC_CFGR_SW_Pos)           /*!< 0x00000007 */

+#define RCC_CFGR_SW                            RCC_CFGR_SW_Msk                     /*!< SW[2:0] bits (System clock Switch) */

+#define RCC_CFGR_SW_0                          (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */

+#define RCC_CFGR_SW_1                          (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */

+#define RCC_CFGR_SW_2                          (0x4UL << RCC_CFGR_SW_Pos)           /*!< 0x00000004 */

+

+#define RCC_CFGR_SW_HSI                        (0x00000000UL)                       /*!< HSI selection as system clock */

+#define RCC_CFGR_SW_CSI                        (0x00000001UL)                       /*!< CSI selection as system clock */

+#define RCC_CFGR_SW_HSE                        (0x00000002UL)                       /*!< HSE selection as system clock */

+#define RCC_CFGR_SW_PLL1                       (0x00000003UL)                       /*!< PLL1 selection as system clock */

+

+/*!< SWS configuration */

+#define RCC_CFGR_SWS_Pos                       (3U)

+#define RCC_CFGR_SWS_Msk                       (0x7UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000038 */

+#define RCC_CFGR_SWS                           RCC_CFGR_SWS_Msk                    /*!< SWS[2:0] bits (System Clock Switch Status) */

+#define RCC_CFGR_SWS_0                         (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */

+#define RCC_CFGR_SWS_1                         (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000010 */

+#define RCC_CFGR_SWS_2                         (0x4UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000020 */

+

+#define RCC_CFGR_SWS_HSI                       (0x00000000UL)                       /*!< HSI used as system clock */

+#define RCC_CFGR_SWS_CSI                       (0x00000008UL)                       /*!< CSI used as system clock */

+#define RCC_CFGR_SWS_HSE                       (0x00000010UL)                       /*!< HSE used as system clock */

+#define RCC_CFGR_SWS_PLL1                      (0x00000018UL)                       /*!< PLL1 used as system clock */

+

+#define RCC_CFGR_STOPWUCK_Pos                  (6U)

+#define RCC_CFGR_STOPWUCK_Msk                  (0x1UL << RCC_CFGR_STOPWUCK_Pos)     /*!< 0x00000040 */

+#define RCC_CFGR_STOPWUCK                      RCC_CFGR_STOPWUCK_Msk                /*!< Wake Up from stop and CSS backup clock selection */

+

+#define RCC_CFGR_STOPKERWUCK_Pos               (7U)

+#define RCC_CFGR_STOPKERWUCK_Msk               (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)  /*!< 0x00000080 */

+#define RCC_CFGR_STOPKERWUCK                   RCC_CFGR_STOPKERWUCK_Msk             /*!< Kernel Clock Selection after a Wake Up from STOP */

+

+/*!< RTCPRE configuration */

+#define RCC_CFGR_RTCPRE_Pos                    (8U)

+#define RCC_CFGR_RTCPRE_Msk                    (0x3FUL << RCC_CFGR_RTCPRE_Pos)

+#define RCC_CFGR_RTCPRE                        RCC_CFGR_RTCPRE_Msk                  /*!< 0x00003F00 */

+#define RCC_CFGR_RTCPRE_0                      (0x1UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000100 */

+#define RCC_CFGR_RTCPRE_1                      (0x2UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000200 */

+#define RCC_CFGR_RTCPRE_2                      (0x4UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000400 */

+#define RCC_CFGR_RTCPRE_3                      (0x8UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000800 */

+#define RCC_CFGR_RTCPRE_4                      (0x10UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00001000 */

+#define RCC_CFGR_RTCPRE_5                      (0x20UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00002000 */

+

+

+/*!< TIMPRE configuration */

+#define RCC_CFGR_TIMPRE_Pos                    (15U)

+#define RCC_CFGR_TIMPRE_Msk                    (0x1UL << RCC_CFGR_TIMPRE_Pos)

+#define RCC_CFGR_TIMPRE                        RCC_CFGR_TIMPRE_Msk                  /*!< 0x00008000 */

+

+/*!< MCO1 configuration */

+#define RCC_CFGR_MCO1_Pos                      (22U)

+#define RCC_CFGR_MCO1_Msk                      (0x7UL << RCC_CFGR_MCO1_Pos)

+#define RCC_CFGR_MCO1                          RCC_CFGR_MCO1_Msk                       /*!< 0x01C00000 */

+#define RCC_CFGR_MCO1_0                        (0x1UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00400000 */

+#define RCC_CFGR_MCO1_1                        (0x2UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00800000 */

+#define RCC_CFGR_MCO1_2                        (0x4UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x01000000 */

+

+#define RCC_CFGR_MCO1PRE_Pos                   (18U)

+#define RCC_CFGR_MCO1PRE_Msk                   (0xFUL << RCC_CFGR_MCO1PRE_Pos)

+#define RCC_CFGR_MCO1PRE                       RCC_CFGR_MCO1PRE_Msk                    /*!< 0x003C0000 */

+#define RCC_CFGR_MCO1PRE_0                     (0x1UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00040000 */

+#define RCC_CFGR_MCO1PRE_1                     (0x2UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00080000 */

+#define RCC_CFGR_MCO1PRE_2                     (0x4UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00100000 */

+#define RCC_CFGR_MCO1PRE_3                     (0x8UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00200000 */

+

+#define RCC_CFGR_MCO2PRE_Pos                   (25U)

+#define RCC_CFGR_MCO2PRE_Msk                   (0xFUL << RCC_CFGR_MCO2PRE_Pos)

+#define RCC_CFGR_MCO2PRE                       RCC_CFGR_MCO2PRE_Msk                    /*!< 0x1E000000 */

+#define RCC_CFGR_MCO2PRE_0                     (0x1UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x02000000 */

+#define RCC_CFGR_MCO2PRE_1                     (0x2UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x04000000 */

+#define RCC_CFGR_MCO2PRE_2                     (0x4UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x08000000 */

+#define RCC_CFGR_MCO2PRE_3                     (0x8UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x10000000 */

+

+#define RCC_CFGR_MCO2_Pos                      (29U)

+#define RCC_CFGR_MCO2_Msk                      (0x7UL << RCC_CFGR_MCO2_Pos)

+#define RCC_CFGR_MCO2                          RCC_CFGR_MCO2_Msk                       /*!< 0xE0000000 */

+#define RCC_CFGR_MCO2_0                        (0x1UL << RCC_CFGR_MCO2_Pos)             /*!< 0x20000000 */

+#define RCC_CFGR_MCO2_1                        (0x2UL << RCC_CFGR_MCO2_Pos)             /*!< 0x40000000 */

+#define RCC_CFGR_MCO2_2                        (0x4UL << RCC_CFGR_MCO2_Pos)             /*!< 0x80000000 */

+

+/********************  Bit definition for RCC_D1CFGR register  ******************/

+/*!< D1HPRE configuration */

+#define RCC_CDCFGR1_HPRE_Pos                    (0U)

+#define RCC_CDCFGR1_HPRE_Msk                    (0xFUL << RCC_CDCFGR1_HPRE_Pos)  /*!< 0x0000000F */

+#define RCC_CDCFGR1_HPRE                        RCC_CDCFGR1_HPRE_Msk             /*!< HPRE[3:0] bits (AHB3 prescaler) */

+#define RCC_CDCFGR1_HPRE_0                      (0x1UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000001 */

+#define RCC_CDCFGR1_HPRE_1                      (0x2UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000002 */

+#define RCC_CDCFGR1_HPRE_2                      (0x4UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000004 */

+#define RCC_CDCFGR1_HPRE_3                      (0x8UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000008 */

+

+#define RCC_CDCFGR1_HPRE_DIV1                   ((uint32_t)0x00000000)                 /*!< AHB3 Clock not divided */

+#define RCC_CDCFGR1_HPRE_DIV2_Pos               (3U)

+#define RCC_CDCFGR1_HPRE_DIV2_Msk               (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos)   /*!< 0x00000008 */

+#define RCC_CDCFGR1_HPRE_DIV2                   RCC_CDCFGR1_HPRE_DIV2_Msk              /*!< AHB3 Clock divided by 2 */

+#define RCC_CDCFGR1_HPRE_DIV4_Pos               (0U)

+#define RCC_CDCFGR1_HPRE_DIV4_Msk               (0x9UL << RCC_CDCFGR1_HPRE_DIV4_Pos)   /*!< 0x00000009 */

+#define RCC_CDCFGR1_HPRE_DIV4                   RCC_CDCFGR1_HPRE_DIV4_Msk              /*!< AHB3 Clock divided by 4 */

+#define RCC_CDCFGR1_HPRE_DIV8_Pos               (1U)

+#define RCC_CDCFGR1_HPRE_DIV8_Msk               (0x5UL << RCC_CDCFGR1_HPRE_DIV8_Pos)   /*!< 0x0000000A */

+#define RCC_CDCFGR1_HPRE_DIV8                   RCC_CDCFGR1_HPRE_DIV8_Msk              /*!< AHB3 Clock divided by 8 */

+#define RCC_CDCFGR1_HPRE_DIV16_Pos              (0U)

+#define RCC_CDCFGR1_HPRE_DIV16_Msk              (0xBUL << RCC_CDCFGR1_HPRE_DIV16_Pos)  /*!< 0x0000000B */

+#define RCC_CDCFGR1_HPRE_DIV16                  RCC_CDCFGR1_HPRE_DIV16_Msk             /*!< AHB3 Clock divided by 16 */

+#define RCC_CDCFGR1_HPRE_DIV64_Pos              (2U)

+#define RCC_CDCFGR1_HPRE_DIV64_Msk              (0x3UL << RCC_CDCFGR1_HPRE_DIV64_Pos)  /*!< 0x0000000C */

+#define RCC_CDCFGR1_HPRE_DIV64                  RCC_CDCFGR1_HPRE_DIV64_Msk             /*!< AHB3 Clock divided by 64 */

+#define RCC_CDCFGR1_HPRE_DIV128_Pos             (0U)

+#define RCC_CDCFGR1_HPRE_DIV128_Msk             (0xDUL << RCC_CDCFGR1_HPRE_DIV128_Pos) /*!< 0x0000000D */

+#define RCC_CDCFGR1_HPRE_DIV128                 RCC_CDCFGR1_HPRE_DIV128_Msk            /*!< AHB3 Clock divided by 128 */

+#define RCC_CDCFGR1_HPRE_DIV256_Pos             (1U)

+#define RCC_CDCFGR1_HPRE_DIV256_Msk             (0x7UL << RCC_CDCFGR1_HPRE_DIV256_Pos) /*!< 0x0000000E */

+#define RCC_CDCFGR1_HPRE_DIV256                 RCC_CDCFGR1_HPRE_DIV256_Msk            /*!< AHB3 Clock divided by 256 */

+#define RCC_CDCFGR1_HPRE_DIV512_Pos             (0U)

+#define RCC_CDCFGR1_HPRE_DIV512_Msk             (0xFUL << RCC_CDCFGR1_HPRE_DIV512_Pos) /*!< 0x0000000F */

+#define RCC_CDCFGR1_HPRE_DIV512                 RCC_CDCFGR1_HPRE_DIV512_Msk            /*!< AHB3 Clock divided by 512 */

+

+/*!< D1PPRE configuration */

+#define RCC_CDCFGR1_CDPPRE_Pos                  (4U)

+#define RCC_CDCFGR1_CDPPRE_Msk                  (0x7UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000070 */

+#define RCC_CDCFGR1_CDPPRE                      RCC_CDCFGR1_CDPPRE_Msk                 /*!< CDPRE[2:0] bits (APB3 prescaler) */

+#define RCC_CDCFGR1_CDPPRE_0                    (0x1UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000010 */

+#define RCC_CDCFGR1_CDPPRE_1                    (0x2UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000020 */

+#define RCC_CDCFGR1_CDPPRE_2                    (0x4UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000040 */

+

+#define RCC_CDCFGR1_CDPPRE_DIV1                 ((uint32_t)0x00000000)                 /*!< APB3 clock not divided */

+#define RCC_CDCFGR1_CDPPRE_DIV2_Pos             (6U)

+#define RCC_CDCFGR1_CDPPRE_DIV2_Msk             (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_CDCFGR1_CDPPRE_DIV2                 RCC_CDCFGR1_CDPPRE_DIV2_Msk            /*!< APB3 clock divided by 2 */

+#define RCC_CDCFGR1_CDPPRE_DIV4_Pos             (4U)

+#define RCC_CDCFGR1_CDPPRE_DIV4_Msk             (0x5UL << RCC_CDCFGR1_CDPPRE_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_CDCFGR1_CDPPRE_DIV4                 RCC_CDCFGR1_CDPPRE_DIV4_Msk            /*!< APB3 clock divided by 4 */

+#define RCC_CDCFGR1_CDPPRE_DIV8_Pos             (5U)

+#define RCC_CDCFGR1_CDPPRE_DIV8_Msk             (0x3UL << RCC_CDCFGR1_CDPPRE_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_CDCFGR1_CDPPRE_DIV8                 RCC_CDCFGR1_CDPPRE_DIV8_Msk            /*!< APB3 clock divided by 8 */

+#define RCC_CDCFGR1_CDPPRE_DIV16_Pos            (4U)

+#define RCC_CDCFGR1_CDPPRE_DIV16_Msk            (0x7UL << RCC_CDCFGR1_CDPPRE_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_CDCFGR1_CDPPRE_DIV16                RCC_CDCFGR1_CDPPRE_DIV16_Msk            /*!< APB3 clock divided by 16 */

+

+#define RCC_CDCFGR1_CDCPRE_Pos                  (8U)

+#define RCC_CDCFGR1_CDCPRE_Msk                  (0xFUL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000F00 */

+#define RCC_CDCFGR1_CDCPRE                      RCC_CDCFGR1_CDCPRE_Msk                  /*!< CDCPRE[2:0] bits (Domain 1 Core prescaler) */

+#define RCC_CDCFGR1_CDCPRE_0                    (0x1UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000100 */

+#define RCC_CDCFGR1_CDCPRE_1                    (0x2UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000200 */

+#define RCC_CDCFGR1_CDCPRE_2                    (0x4UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000400 */

+#define RCC_CDCFGR1_CDCPRE_3                    (0x8UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000800 */

+

+#define RCC_CDCFGR1_CDCPRE_DIV1                 ((uint32_t)0x00000000)                  /*!< Domain 1 Core clock not divided */

+#define RCC_CDCFGR1_CDCPRE_DIV2_Pos             (11U)

+#define RCC_CDCFGR1_CDCPRE_DIV2_Msk             (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos)  /*!< 0x00000800 */

+#define RCC_CDCFGR1_CDCPRE_DIV2                 RCC_CDCFGR1_CDCPRE_DIV2_Msk             /*!< Domain 1 Core clock divided by 2 */

+#define RCC_CDCFGR1_CDCPRE_DIV4_Pos             (8U)

+#define RCC_CDCFGR1_CDCPRE_DIV4_Msk             (0x9UL << RCC_CDCFGR1_CDCPRE_DIV4_Pos)  /*!< 0x00000900 */

+#define RCC_CDCFGR1_CDCPRE_DIV4                 RCC_CDCFGR1_CDCPRE_DIV4_Msk             /*!< Domain 1 Core clock divided by 4 */

+#define RCC_CDCFGR1_CDCPRE_DIV8_Pos             (9U)

+#define RCC_CDCFGR1_CDCPRE_DIV8_Msk             (0x5UL << RCC_CDCFGR1_CDCPRE_DIV8_Pos)  /*!< 0x00000A00 */

+#define RCC_CDCFGR1_CDCPRE_DIV8                 RCC_CDCFGR1_CDCPRE_DIV8_Msk             /*!< Domain 1 Core clock divided by 8 */

+#define RCC_CDCFGR1_CDCPRE_DIV16_Pos            (8U)

+#define RCC_CDCFGR1_CDCPRE_DIV16_Msk            (0xBUL << RCC_CDCFGR1_CDCPRE_DIV16_Pos) /*!< 0x00000B00 */

+#define RCC_CDCFGR1_CDCPRE_DIV16                RCC_CDCFGR1_CDCPRE_DIV16_Msk            /*!< Domain 1 Core clock divided by 16 */

+#define RCC_CDCFGR1_CDCPRE_DIV64_Pos            (10U)

+#define RCC_CDCFGR1_CDCPRE_DIV64_Msk            (0x3UL << RCC_CDCFGR1_CDCPRE_DIV64_Pos) /*!< 0x00000C00 */

+#define RCC_CDCFGR1_CDCPRE_DIV64                RCC_CDCFGR1_CDCPRE_DIV64_Msk            /*!< Domain 1 Core clock divided by 64 */

+#define RCC_CDCFGR1_CDCPRE_DIV128_Pos           (8U)

+#define RCC_CDCFGR1_CDCPRE_DIV128_Msk           (0xDUL << RCC_CDCFGR1_CDCPRE_DIV128_Pos)/*!< 0x00000D00 */

+#define RCC_CDCFGR1_CDCPRE_DIV128               RCC_CDCFGR1_CDCPRE_DIV128_Msk           /*!< Domain 1 Core clock divided by 128 */

+#define RCC_CDCFGR1_CDCPRE_DIV256_Pos           (9U)

+#define RCC_CDCFGR1_CDCPRE_DIV256_Msk           (0x7UL << RCC_CDCFGR1_CDCPRE_DIV256_Pos)/*!< 0x00000E00 */

+#define RCC_CDCFGR1_CDCPRE_DIV256               RCC_CDCFGR1_CDCPRE_DIV256_Msk           /*!< Domain 1 Core clock divided by 256 */

+#define RCC_CDCFGR1_CDCPRE_DIV512_Pos           (8U)

+#define RCC_CDCFGR1_CDCPRE_DIV512_Msk           (0xFUL << RCC_CDCFGR1_CDCPRE_DIV512_Pos)/*!< 0x00000F00 */

+#define RCC_CDCFGR1_CDCPRE_DIV512               RCC_CDCFGR1_CDCPRE_DIV512_Msk           /*!< Domain 1 Core clock divided by 512 */

+

+/********************  Bit definition for RCC_CDCFGR2 register  ******************/

+/*!< CDPPRE1 configuration */

+#define RCC_CDCFGR2_CDPPRE1_Pos                 (4U)

+#define RCC_CDCFGR2_CDPPRE1_Msk                 (0x7UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000070 */

+#define RCC_CDCFGR2_CDPPRE1                     RCC_CDCFGR2_CDPPRE1_Msk          /*!< D1PPRE1[2:0] bits (APB1 prescaler) */

+#define RCC_CDCFGR2_CDPPRE1_0                   (0x1UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000010 */

+#define RCC_CDCFGR2_CDPPRE1_1                   (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */

+#define RCC_CDCFGR2_CDPPRE1_2                   (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */

+

+#define RCC_CDCFGR2_CDPPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */

+#define RCC_CDCFGR2_CDPPRE1_DIV2_Pos            (6U)

+#define RCC_CDCFGR2_CDPPRE1_DIV2_Msk            (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_CDCFGR2_CDPPRE1_DIV2                RCC_CDCFGR2_CDPPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */

+#define RCC_CDCFGR2_CDPPRE1_DIV4_Pos            (4U)

+#define RCC_CDCFGR2_CDPPRE1_DIV4_Msk            (0x5UL << RCC_CDCFGR2_CDPPRE1_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_CDCFGR2_CDPPRE1_DIV4                RCC_CDCFGR2_CDPPRE1_DIV4_Msk     /*!< APB1 clock divided by 4 */

+#define RCC_CDCFGR2_CDPPRE1_DIV8_Pos            (5U)

+#define RCC_CDCFGR2_CDPPRE1_DIV8_Msk            (0x3UL << RCC_CDCFGR2_CDPPRE1_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_CDCFGR2_CDPPRE1_DIV8                RCC_CDCFGR2_CDPPRE1_DIV8_Msk     /*!< APB1 clock divided by 8 */

+#define RCC_CDCFGR2_CDPPRE1_DIV16_Pos           (4U)

+#define RCC_CDCFGR2_CDPPRE1_DIV16_Msk           (0x7UL << RCC_CDCFGR2_CDPPRE1_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_CDCFGR2_CDPPRE1_DIV16               RCC_CDCFGR2_CDPPRE1_DIV16_Msk    /*!< APB1 clock divided by 16 */

+

+/*!< CDPPRE2 configuration */

+#define RCC_CDCFGR2_CDPPRE2_Pos                 (8U)

+#define RCC_CDCFGR2_CDPPRE2_Msk                 (0x7UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000700 */

+#define RCC_CDCFGR2_CDPPRE2                     RCC_CDCFGR2_CDPPRE2_Msk          /*!< CDPPRE2[2:0] bits (APB2 prescaler) */

+#define RCC_CDCFGR2_CDPPRE2_0                   (0x1UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000100 */

+#define RCC_CDCFGR2_CDPPRE2_1                   (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */

+#define RCC_CDCFGR2_CDPPRE2_2                   (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */

+

+#define RCC_CDCFGR2_CDPPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */

+#define RCC_CDCFGR2_CDPPRE2_DIV2_Pos            (10U)

+#define RCC_CDCFGR2_CDPPRE2_DIV2_Msk            (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */

+#define RCC_CDCFGR2_CDPPRE2_DIV2                RCC_CDCFGR2_CDPPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */

+#define RCC_CDCFGR2_CDPPRE2_DIV4_Pos            (8U)

+#define RCC_CDCFGR2_CDPPRE2_DIV4_Msk            (0x5UL << RCC_CDCFGR2_CDPPRE2_DIV4_Pos) /*!< 0x00000500 */

+#define RCC_CDCFGR2_CDPPRE2_DIV4                RCC_CDCFGR2_CDPPRE2_DIV4_Msk     /*!< APB2 clock divided by 4 */

+#define RCC_CDCFGR2_CDPPRE2_DIV8_Pos            (9U)

+#define RCC_CDCFGR2_CDPPRE2_DIV8_Msk            (0x3UL << RCC_CDCFGR2_CDPPRE2_DIV8_Pos) /*!< 0x00000600 */

+#define RCC_CDCFGR2_CDPPRE2_DIV8                RCC_CDCFGR2_CDPPRE2_DIV8_Msk     /*!< APB2 clock divided by 8 */

+#define RCC_CDCFGR2_CDPPRE2_DIV16_Pos           (8U)

+#define RCC_CDCFGR2_CDPPRE2_DIV16_Msk           (0x7UL << RCC_CDCFGR2_CDPPRE2_DIV16_Pos) /*!< 0x00000700 */

+#define RCC_CDCFGR2_CDPPRE2_DIV16               RCC_CDCFGR2_CDPPRE2_DIV16_Msk    /*!< APB2 clock divided by 16 */

+

+/********************  Bit definition for RCC_SRDCFGR register  ******************/

+/*!< SRDPPRE configuration */

+#define RCC_SRDCFGR_SRDPPRE_Pos                  (4U)

+#define RCC_SRDCFGR_SRDPPRE_Msk                  (0x7UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000070 */

+#define RCC_SRDCFGR_SRDPPRE                      RCC_SRDCFGR_SRDPPRE_Msk           /*!< SRDPPRE1[2:0] bits (APB4 prescaler) */

+#define RCC_SRDCFGR_SRDPPRE_0                    (0x1UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000010 */

+#define RCC_SRDCFGR_SRDPPRE_1                    (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */

+#define RCC_SRDCFGR_SRDPPRE_2                    (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */

+

+#define RCC_SRDCFGR_SRDPPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */

+#define RCC_SRDCFGR_SRDPPRE_DIV2_Pos             (6U)

+#define RCC_SRDCFGR_SRDPPRE_DIV2_Msk             (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_SRDCFGR_SRDPPRE_DIV2                 RCC_SRDCFGR_SRDPPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */

+#define RCC_SRDCFGR_SRDPPRE_DIV4_Pos             (4U)

+#define RCC_SRDCFGR_SRDPPRE_DIV4_Msk             (0x5UL << RCC_SRDCFGR_SRDPPRE_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_SRDCFGR_SRDPPRE_DIV4                 RCC_SRDCFGR_SRDPPRE_DIV4_Msk      /*!< APB4 clock divided by 4 */

+#define RCC_SRDCFGR_SRDPPRE_DIV8_Pos             (5U)

+#define RCC_SRDCFGR_SRDPPRE_DIV8_Msk             (0x3UL << RCC_SRDCFGR_SRDPPRE_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_SRDCFGR_SRDPPRE_DIV8                 RCC_SRDCFGR_SRDPPRE_DIV8_Msk      /*!< APB4 clock divided by 8 */

+#define RCC_SRDCFGR_SRDPPRE_DIV16_Pos            (4U)

+#define RCC_SRDCFGR_SRDPPRE_DIV16_Msk            (0x7UL << RCC_SRDCFGR_SRDPPRE_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_SRDCFGR_SRDPPRE_DIV16                RCC_SRDCFGR_SRDPPRE_DIV16_Msk     /*!< APB4 clock divided by 16 */

+

+/********************  Bit definition for RCC_PLLCKSELR register  *************/

+

+#define RCC_PLLCKSELR_PLLSRC_Pos               (0U)

+#define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */

+#define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk

+

+#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)

+#define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */

+#define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_HSE_Pos           (1U)

+#define RCC_PLLCKSELR_PLLSRC_HSE_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */

+#define RCC_PLLCKSELR_PLLSRC_HSE               RCC_PLLCKSELR_PLLSRC_HSE_Msk    /*!< HSE source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_NONE_Pos          (0U)

+#define RCC_PLLCKSELR_PLLSRC_NONE_Msk          (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */

+#define RCC_PLLCKSELR_PLLSRC_NONE              RCC_PLLCKSELR_PLLSRC_NONE_Msk   /*!< No source clock selected  */

+

+#define RCC_PLLCKSELR_DIVM1_Pos                (4U)

+#define RCC_PLLCKSELR_DIVM1_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */

+#define RCC_PLLCKSELR_DIVM1                    RCC_PLLCKSELR_DIVM1_Msk

+#define RCC_PLLCKSELR_DIVM1_0                  (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */

+#define RCC_PLLCKSELR_DIVM1_1                  (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */

+#define RCC_PLLCKSELR_DIVM1_2                  (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */

+#define RCC_PLLCKSELR_DIVM1_3                  (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */

+#define RCC_PLLCKSELR_DIVM1_4                  (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */

+#define RCC_PLLCKSELR_DIVM1_5                  (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */

+

+#define RCC_PLLCKSELR_DIVM2_Pos                (12U)

+#define RCC_PLLCKSELR_DIVM2_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */

+#define RCC_PLLCKSELR_DIVM2                    RCC_PLLCKSELR_DIVM2_Msk

+#define RCC_PLLCKSELR_DIVM2_0                  (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */

+#define RCC_PLLCKSELR_DIVM2_1                  (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */

+#define RCC_PLLCKSELR_DIVM2_2                  (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */

+#define RCC_PLLCKSELR_DIVM2_3                  (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */

+#define RCC_PLLCKSELR_DIVM2_4                  (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */

+#define RCC_PLLCKSELR_DIVM2_5                  (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */

+

+#define RCC_PLLCKSELR_DIVM3_Pos                (20U)

+#define RCC_PLLCKSELR_DIVM3_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */

+#define RCC_PLLCKSELR_DIVM3                    RCC_PLLCKSELR_DIVM3_Msk

+#define RCC_PLLCKSELR_DIVM3_0                  (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */

+#define RCC_PLLCKSELR_DIVM3_1                  (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */

+#define RCC_PLLCKSELR_DIVM3_2                  (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */

+#define RCC_PLLCKSELR_DIVM3_3                  (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */

+#define RCC_PLLCKSELR_DIVM3_4                  (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */

+#define RCC_PLLCKSELR_DIVM3_5                  (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */

+

+/********************  Bit definition for RCC_PLLCFGR register  ***************/

+

+#define RCC_PLLCFGR_PLL1FRACEN_Pos             (0U)

+#define RCC_PLLCFGR_PLL1FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */

+#define RCC_PLLCFGR_PLL1FRACEN                 RCC_PLLCFGR_PLL1FRACEN_Msk

+#define RCC_PLLCFGR_PLL1VCOSEL_Pos             (1U)

+#define RCC_PLLCFGR_PLL1VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */

+#define RCC_PLLCFGR_PLL1VCOSEL                 RCC_PLLCFGR_PLL1VCOSEL_Msk

+#define RCC_PLLCFGR_PLL1RGE_Pos                (2U)

+#define RCC_PLLCFGR_PLL1RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */

+#define RCC_PLLCFGR_PLL1RGE                    RCC_PLLCFGR_PLL1RGE_Msk

+#define RCC_PLLCFGR_PLL1RGE_0                  (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL1RGE_1                  (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */

+#define RCC_PLLCFGR_PLL1RGE_2                  (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */

+#define RCC_PLLCFGR_PLL1RGE_3                  (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */

+

+#define RCC_PLLCFGR_PLL2FRACEN_Pos             (4U)

+#define RCC_PLLCFGR_PLL2FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */

+#define RCC_PLLCFGR_PLL2FRACEN                 RCC_PLLCFGR_PLL2FRACEN_Msk

+#define RCC_PLLCFGR_PLL2VCOSEL_Pos             (5U)

+#define RCC_PLLCFGR_PLL2VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */

+#define RCC_PLLCFGR_PLL2VCOSEL                 RCC_PLLCFGR_PLL2VCOSEL_Msk

+#define RCC_PLLCFGR_PLL2RGE_Pos                (6U)

+#define RCC_PLLCFGR_PLL2RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */

+#define RCC_PLLCFGR_PLL2RGE                    RCC_PLLCFGR_PLL2RGE_Msk

+#define RCC_PLLCFGR_PLL2RGE_0                  (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL2RGE_1                  (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */

+#define RCC_PLLCFGR_PLL2RGE_2                  (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */

+#define RCC_PLLCFGR_PLL2RGE_3                  (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */

+

+#define RCC_PLLCFGR_PLL3FRACEN_Pos             (8U)

+#define RCC_PLLCFGR_PLL3FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */

+#define RCC_PLLCFGR_PLL3FRACEN                 RCC_PLLCFGR_PLL3FRACEN_Msk

+#define RCC_PLLCFGR_PLL3VCOSEL_Pos             (9U)

+#define RCC_PLLCFGR_PLL3VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */

+#define RCC_PLLCFGR_PLL3VCOSEL                 RCC_PLLCFGR_PLL3VCOSEL_Msk

+#define RCC_PLLCFGR_PLL3RGE_Pos                (10U)

+#define RCC_PLLCFGR_PLL3RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */

+#define RCC_PLLCFGR_PLL3RGE                    RCC_PLLCFGR_PLL3RGE_Msk

+#define RCC_PLLCFGR_PLL3RGE_0                  (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL3RGE_1                  (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */

+#define RCC_PLLCFGR_PLL3RGE_2                  (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */

+#define RCC_PLLCFGR_PLL3RGE_3                  (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */

+

+#define RCC_PLLCFGR_DIVP1EN_Pos                (16U)

+#define RCC_PLLCFGR_DIVP1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */

+#define RCC_PLLCFGR_DIVP1EN                    RCC_PLLCFGR_DIVP1EN_Msk

+#define RCC_PLLCFGR_DIVQ1EN_Pos                (17U)

+#define RCC_PLLCFGR_DIVQ1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */

+#define RCC_PLLCFGR_DIVQ1EN                    RCC_PLLCFGR_DIVQ1EN_Msk

+#define RCC_PLLCFGR_DIVR1EN_Pos                (18U)

+#define RCC_PLLCFGR_DIVR1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */

+#define RCC_PLLCFGR_DIVR1EN                    RCC_PLLCFGR_DIVR1EN_Msk

+

+#define RCC_PLLCFGR_DIVP2EN_Pos                (19U)

+#define RCC_PLLCFGR_DIVP2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */

+#define RCC_PLLCFGR_DIVP2EN                    RCC_PLLCFGR_DIVP2EN_Msk

+#define RCC_PLLCFGR_DIVQ2EN_Pos                (20U)

+#define RCC_PLLCFGR_DIVQ2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */

+#define RCC_PLLCFGR_DIVQ2EN                    RCC_PLLCFGR_DIVQ2EN_Msk

+#define RCC_PLLCFGR_DIVR2EN_Pos                (21U)

+#define RCC_PLLCFGR_DIVR2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */

+#define RCC_PLLCFGR_DIVR2EN                    RCC_PLLCFGR_DIVR2EN_Msk

+

+#define RCC_PLLCFGR_DIVP3EN_Pos                (22U)

+#define RCC_PLLCFGR_DIVP3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */

+#define RCC_PLLCFGR_DIVP3EN                    RCC_PLLCFGR_DIVP3EN_Msk

+#define RCC_PLLCFGR_DIVQ3EN_Pos                (23U)

+#define RCC_PLLCFGR_DIVQ3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */

+#define RCC_PLLCFGR_DIVQ3EN                    RCC_PLLCFGR_DIVQ3EN_Msk

+#define RCC_PLLCFGR_DIVR3EN_Pos                (24U)

+#define RCC_PLLCFGR_DIVR3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */

+#define RCC_PLLCFGR_DIVR3EN                    RCC_PLLCFGR_DIVR3EN_Msk

+

+

+/********************  Bit definition for RCC_PLL1DIVR register  ***************/

+#define RCC_PLL1DIVR_N1_Pos                    (0U)

+#define RCC_PLL1DIVR_N1_Msk                    (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */

+#define RCC_PLL1DIVR_N1                        RCC_PLL1DIVR_N1_Msk

+#define RCC_PLL1DIVR_P1_Pos                    (9U)

+#define RCC_PLL1DIVR_P1_Msk                    (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL1DIVR_P1                        RCC_PLL1DIVR_P1_Msk

+#define RCC_PLL1DIVR_Q1_Pos                    (16U)

+#define RCC_PLL1DIVR_Q1_Msk                    (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */

+#define RCC_PLL1DIVR_Q1                        RCC_PLL1DIVR_Q1_Msk

+#define RCC_PLL1DIVR_R1_Pos                    (24U)

+#define RCC_PLL1DIVR_R1_Msk                    (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */

+#define RCC_PLL1DIVR_R1                        RCC_PLL1DIVR_R1_Msk

+

+/********************  Bit definition for RCC_PLL1FRACR register  ***************/

+#define RCC_PLL1FRACR_FRACN1_Pos               (3U)

+#define RCC_PLL1FRACR_FRACN1_Msk               (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL1FRACR_FRACN1                   RCC_PLL1FRACR_FRACN1_Msk

+

+/********************  Bit definition for RCC_PLL2DIVR register  ***************/

+#define RCC_PLL2DIVR_N2_Pos                    (0U)

+#define RCC_PLL2DIVR_N2_Msk                    (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */

+#define RCC_PLL2DIVR_N2                        RCC_PLL2DIVR_N2_Msk

+#define RCC_PLL2DIVR_P2_Pos                    (9U)

+#define RCC_PLL2DIVR_P2_Msk                    (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL2DIVR_P2                        RCC_PLL2DIVR_P2_Msk

+#define RCC_PLL2DIVR_Q2_Pos                    (16U)

+#define RCC_PLL2DIVR_Q2_Msk                    (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */

+#define RCC_PLL2DIVR_Q2                        RCC_PLL2DIVR_Q2_Msk

+#define RCC_PLL2DIVR_R2_Pos                    (24U)

+#define RCC_PLL2DIVR_R2_Msk                    (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */

+#define RCC_PLL2DIVR_R2                        RCC_PLL2DIVR_R2_Msk

+

+/********************  Bit definition for RCC_PLL2FRACR register  ***************/

+#define RCC_PLL2FRACR_FRACN2_Pos               (3U)

+#define RCC_PLL2FRACR_FRACN2_Msk               (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL2FRACR_FRACN2                   RCC_PLL2FRACR_FRACN2_Msk

+

+/********************  Bit definition for RCC_PLL3DIVR register  ***************/

+#define RCC_PLL3DIVR_N3_Pos                    (0U)

+#define RCC_PLL3DIVR_N3_Msk                    (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */

+#define RCC_PLL3DIVR_N3                        RCC_PLL3DIVR_N3_Msk

+#define RCC_PLL3DIVR_P3_Pos                    (9U)

+#define RCC_PLL3DIVR_P3_Msk                    (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL3DIVR_P3                        RCC_PLL3DIVR_P3_Msk

+#define RCC_PLL3DIVR_Q3_Pos                    (16U)

+#define RCC_PLL3DIVR_Q3_Msk                    (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */

+#define RCC_PLL3DIVR_Q3                        RCC_PLL3DIVR_Q3_Msk

+#define RCC_PLL3DIVR_R3_Pos                    (24U)

+#define RCC_PLL3DIVR_R3_Msk                    (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */

+#define RCC_PLL3DIVR_R3                        RCC_PLL3DIVR_R3_Msk

+

+/********************  Bit definition for RCC_PLL3FRACR register  ***************/

+#define RCC_PLL3FRACR_FRACN3_Pos               (3U)

+#define RCC_PLL3FRACR_FRACN3_Msk               (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL3FRACR_FRACN3                   RCC_PLL3FRACR_FRACN3_Msk

+

+/********************  Bit definition for RCC_CDCCIPR register  ***************/

+#define RCC_CDCCIPR_FMCSEL_Pos                 (0U)

+#define RCC_CDCCIPR_FMCSEL_Msk                 (0x3UL << RCC_CDCCIPR_FMCSEL_Pos)     /*!< 0x00000003 */

+#define RCC_CDCCIPR_FMCSEL                     RCC_CDCCIPR_FMCSEL_Msk

+#define RCC_CDCCIPR_FMCSEL_0                   (0x1UL << RCC_CDCCIPR_FMCSEL_Pos)     /*!< 0x00000001 */

+#define RCC_CDCCIPR_FMCSEL_1                   (0x2UL << RCC_CDCCIPR_FMCSEL_Pos)     /*!< 0x00000002 */

+#define RCC_CDCCIPR_OCTOSPISEL_Pos             (4U)

+#define RCC_CDCCIPR_OCTOSPISEL_Msk             (0x3UL << RCC_CDCCIPR_OCTOSPISEL_Pos) /*!< 0x00000030 */

+#define RCC_CDCCIPR_OCTOSPISEL                 RCC_CDCCIPR_OCTOSPISEL_Msk

+#define RCC_CDCCIPR_OCTOSPISEL_0               (0x1UL << RCC_CDCCIPR_OCTOSPISEL_Pos) /*!< 0x00000010 */

+#define RCC_CDCCIPR_OCTOSPISEL_1               (0x2UL << RCC_CDCCIPR_OCTOSPISEL_Pos) /*!< 0x00000020 */

+#define RCC_CDCCIPR_SDMMCSEL_Pos               (16U)

+#define RCC_CDCCIPR_SDMMCSEL_Msk               (0x1UL << RCC_CDCCIPR_SDMMCSEL_Pos)   /*!< 0x00010000 */

+#define RCC_CDCCIPR_SDMMCSEL                   RCC_CDCCIPR_SDMMCSEL_Msk

+#define RCC_CDCCIPR_CKPERSEL_Pos               (28U)

+#define RCC_CDCCIPR_CKPERSEL_Msk               (0x3UL << RCC_CDCCIPR_CKPERSEL_Pos)   /*!< 0x30000000 */

+#define RCC_CDCCIPR_CKPERSEL                   RCC_CDCCIPR_CKPERSEL_Msk

+#define RCC_CDCCIPR_CKPERSEL_0                 (0x1UL << RCC_CDCCIPR_CKPERSEL_Pos)   /*!< 0x10000000 */

+#define RCC_CDCCIPR_CKPERSEL_1                 (0x2UL << RCC_CDCCIPR_CKPERSEL_Pos)   /*!< 0x20000000 */

+

+/********************  Bit definition for RCC_CDCCIP1R register  ***************/

+#define RCC_CDCCIP1R_SAI1SEL_Pos               (0U)

+#define RCC_CDCCIP1R_SAI1SEL_Msk               (0x7UL << RCC_CDCCIP1R_SAI1SEL_Pos)   /*!< 0x00000007 */

+#define RCC_CDCCIP1R_SAI1SEL                   RCC_CDCCIP1R_SAI1SEL_Msk

+#define RCC_CDCCIP1R_SAI1SEL_0                 (0x1UL << RCC_CDCCIP1R_SAI1SEL_Pos)   /*!< 0x00000001 */

+#define RCC_CDCCIP1R_SAI1SEL_1                 (0x2UL << RCC_CDCCIP1R_SAI1SEL_Pos)   /*!< 0x00000002 */

+#define RCC_CDCCIP1R_SAI1SEL_2                 (0x4UL << RCC_CDCCIP1R_SAI1SEL_Pos)   /*!< 0x00000004 */

+

+#define RCC_CDCCIP1R_SAI2ASEL_Pos              (6U)

+#define RCC_CDCCIP1R_SAI2ASEL_Msk              (0x7UL << RCC_CDCCIP1R_SAI2ASEL_Pos)  /*!< 0x000001C0 */

+#define RCC_CDCCIP1R_SAI2ASEL                  RCC_CDCCIP1R_SAI2ASEL_Msk

+#define RCC_CDCCIP1R_SAI2ASEL_0                (0x1UL << RCC_CDCCIP1R_SAI2ASEL_Pos)  /*!< 0x00000040 */

+#define RCC_CDCCIP1R_SAI2ASEL_1                (0x2UL << RCC_CDCCIP1R_SAI2ASEL_Pos)  /*!< 0x00000080 */

+#define RCC_CDCCIP1R_SAI2ASEL_2                (0x4UL << RCC_CDCCIP1R_SAI2ASEL_Pos)  /*!< 0x00000100 */

+

+#define RCC_CDCCIP1R_SAI2BSEL_Pos              (9U)

+#define RCC_CDCCIP1R_SAI2BSEL_Msk              (0x7UL << RCC_CDCCIP1R_SAI2BSEL_Pos)  /*!< 0x00000E00 */

+#define RCC_CDCCIP1R_SAI2BSEL                  RCC_CDCCIP1R_SAI2BSEL_Msk

+#define RCC_CDCCIP1R_SAI2BSEL_0                (0x1UL << RCC_CDCCIP1R_SAI2BSEL_Pos)  /*!< 0x00000200 */

+#define RCC_CDCCIP1R_SAI2BSEL_1                (0x2UL << RCC_CDCCIP1R_SAI2BSEL_Pos)  /*!< 0x00000400 */

+#define RCC_CDCCIP1R_SAI2BSEL_2                (0x4UL << RCC_CDCCIP1R_SAI2BSEL_Pos)  /*!< 0x00000800 */

+

+#define RCC_CDCCIP1R_SPI123SEL_Pos             (12U)

+#define RCC_CDCCIP1R_SPI123SEL_Msk             (0x7UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */

+#define RCC_CDCCIP1R_SPI123SEL                 RCC_CDCCIP1R_SPI123SEL_Msk

+#define RCC_CDCCIP1R_SPI123SEL_0               (0x1UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */

+#define RCC_CDCCIP1R_SPI123SEL_1               (0x2UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */

+#define RCC_CDCCIP1R_SPI123SEL_2               (0x4UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */

+

+#define RCC_CDCCIP1R_SPI45SEL_Pos              (16U)

+#define RCC_CDCCIP1R_SPI45SEL_Msk              (0x7UL << RCC_CDCCIP1R_SPI45SEL_Pos)  /*!< 0x00070000 */

+#define RCC_CDCCIP1R_SPI45SEL                  RCC_CDCCIP1R_SPI45SEL_Msk

+#define RCC_CDCCIP1R_SPI45SEL_0                (0x1UL << RCC_CDCCIP1R_SPI45SEL_Pos)  /*!< 0x00010000 */

+#define RCC_CDCCIP1R_SPI45SEL_1                (0x2UL << RCC_CDCCIP1R_SPI45SEL_Pos)  /*!< 0x00020000 */

+#define RCC_CDCCIP1R_SPI45SEL_2                (0x4UL << RCC_CDCCIP1R_SPI45SEL_Pos)  /*!< 0x00040000 */

+

+#define RCC_CDCCIP1R_SPDIFSEL_Pos              (20U)

+#define RCC_CDCCIP1R_SPDIFSEL_Msk              (0x3UL << RCC_CDCCIP1R_SPDIFSEL_Pos)  /*!< 0x00300000 */

+#define RCC_CDCCIP1R_SPDIFSEL                  RCC_CDCCIP1R_SPDIFSEL_Msk

+#define RCC_CDCCIP1R_SPDIFSEL_0                (0x1UL << RCC_CDCCIP1R_SPDIFSEL_Pos)  /*!< 0x00100000 */

+#define RCC_CDCCIP1R_SPDIFSEL_1                (0x2UL << RCC_CDCCIP1R_SPDIFSEL_Pos)  /*!< 0x00200000 */

+

+#define RCC_CDCCIP1R_DFSDM1SEL_Pos             (24U)

+#define RCC_CDCCIP1R_DFSDM1SEL_Msk             (0x1UL << RCC_CDCCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */

+#define RCC_CDCCIP1R_DFSDM1SEL                 RCC_CDCCIP1R_DFSDM1SEL_Msk

+

+#define RCC_CDCCIP1R_FDCANSEL_Pos              (28U)

+#define RCC_CDCCIP1R_FDCANSEL_Msk              (0x3UL << RCC_CDCCIP1R_FDCANSEL_Pos)  /*!< 0x30000000 */

+#define RCC_CDCCIP1R_FDCANSEL                  RCC_CDCCIP1R_FDCANSEL_Msk

+#define RCC_CDCCIP1R_FDCANSEL_0                (0x1UL << RCC_CDCCIP1R_FDCANSEL_Pos)  /*!< 0x10000000 */

+#define RCC_CDCCIP1R_FDCANSEL_1                (0x2UL << RCC_CDCCIP1R_FDCANSEL_Pos)  /*!< 0x20000000 */

+

+#define RCC_CDCCIP1R_SWPSEL_Pos                (31U)

+#define RCC_CDCCIP1R_SWPSEL_Msk                (0x1UL << RCC_CDCCIP1R_SWPSEL_Pos)    /*!< 0x80000000 */

+#define RCC_CDCCIP1R_SWPSEL                    RCC_CDCCIP1R_SWPSEL_Msk

+

+/********************  Bit definition for RCC_CDCCIP2R register  ***************/

+#define RCC_CDCCIP2R_USART234578SEL_Pos        (0U)

+#define RCC_CDCCIP2R_USART234578SEL_Msk        (0x7UL << RCC_CDCCIP2R_USART234578SEL_Pos)   /*!< 0x00000007 */

+#define RCC_CDCCIP2R_USART234578SEL            RCC_CDCCIP2R_USART234578SEL_Msk

+#define RCC_CDCCIP2R_USART234578SEL_0          (0x1UL << RCC_CDCCIP2R_USART234578SEL_Pos)   /*!< 0x00000001 */

+#define RCC_CDCCIP2R_USART234578SEL_1          (0x2UL << RCC_CDCCIP2R_USART234578SEL_Pos)   /*!< 0x00000002 */

+#define RCC_CDCCIP2R_USART234578SEL_2          (0x4UL << RCC_CDCCIP2R_USART234578SEL_Pos)   /*!< 0x00000004 */

+

+#define RCC_CDCCIP2R_USART16910SEL_Pos         (3U)

+#define RCC_CDCCIP2R_USART16910SEL_Msk         (0x7UL << RCC_CDCCIP2R_USART16910SEL_Pos)    /*!< 0x00000038 */

+#define RCC_CDCCIP2R_USART16910SEL             RCC_CDCCIP2R_USART16910SEL_Msk

+#define RCC_CDCCIP2R_USART16910SEL_0           (0x1UL << RCC_CDCCIP2R_USART16910SEL_Pos)    /*!< 0x00000008 */

+#define RCC_CDCCIP2R_USART16910SEL_1           (0x2UL << RCC_CDCCIP2R_USART16910SEL_Pos)    /*!< 0x00000010 */

+#define RCC_CDCCIP2R_USART16910SEL_2           (0x4UL << RCC_CDCCIP2R_USART16910SEL_Pos)    /*!< 0x00000020 */

+

+#define RCC_CDCCIP2R_RNGSEL_Pos                (8U)

+#define RCC_CDCCIP2R_RNGSEL_Msk                (0x3UL << RCC_CDCCIP2R_RNGSEL_Pos)           /*!< 0x00000300 */

+#define RCC_CDCCIP2R_RNGSEL                    RCC_CDCCIP2R_RNGSEL_Msk

+#define RCC_CDCCIP2R_RNGSEL_0                  (0x1UL << RCC_CDCCIP2R_RNGSEL_Pos)           /*!< 0x00000100 */

+#define RCC_CDCCIP2R_RNGSEL_1                  (0x2UL << RCC_CDCCIP2R_RNGSEL_Pos)           /*!< 0x00000200 */

+

+#define RCC_CDCCIP2R_I2C123SEL_Pos             (12U)

+#define RCC_CDCCIP2R_I2C123SEL_Msk             (0x3UL << RCC_CDCCIP2R_I2C123SEL_Pos)        /*!< 0x00003000 */

+#define RCC_CDCCIP2R_I2C123SEL                 RCC_CDCCIP2R_I2C123SEL_Msk

+#define RCC_CDCCIP2R_I2C123SEL_0               (0x1UL << RCC_CDCCIP2R_I2C123SEL_Pos)        /*!< 0x00001000 */

+#define RCC_CDCCIP2R_I2C123SEL_1               (0x2UL << RCC_CDCCIP2R_I2C123SEL_Pos)        /*!< 0x00002000 */

+

+#define RCC_CDCCIP2R_USBSEL_Pos                (20U)

+#define RCC_CDCCIP2R_USBSEL_Msk                (0x3UL << RCC_CDCCIP2R_USBSEL_Pos)           /*!< 0x00300000 */

+#define RCC_CDCCIP2R_USBSEL                    RCC_CDCCIP2R_USBSEL_Msk

+#define RCC_CDCCIP2R_USBSEL_0                  (0x1UL << RCC_CDCCIP2R_USBSEL_Pos)           /*!< 0x00100000 */

+#define RCC_CDCCIP2R_USBSEL_1                  (0x2UL << RCC_CDCCIP2R_USBSEL_Pos)           /*!< 0x00200000 */

+

+#define RCC_CDCCIP2R_CECSEL_Pos                (22U)

+#define RCC_CDCCIP2R_CECSEL_Msk                (0x3UL << RCC_CDCCIP2R_CECSEL_Pos)           /*!< 0x00C00000 */

+#define RCC_CDCCIP2R_CECSEL                    RCC_CDCCIP2R_CECSEL_Msk

+#define RCC_CDCCIP2R_CECSEL_0                  (0x1UL << RCC_CDCCIP2R_CECSEL_Pos)           /*!< 0x00400000 */

+#define RCC_CDCCIP2R_CECSEL_1                  (0x2UL << RCC_CDCCIP2R_CECSEL_Pos)           /*!< 0x00800000 */

+

+#define RCC_CDCCIP2R_LPTIM1SEL_Pos             (28U)

+#define RCC_CDCCIP2R_LPTIM1SEL_Msk             (0x7UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)        /*!< 0x70000000 */

+#define RCC_CDCCIP2R_LPTIM1SEL                 RCC_CDCCIP2R_LPTIM1SEL_Msk

+#define RCC_CDCCIP2R_LPTIM1SEL_0               (0x1UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)        /*!< 0x10000000 */

+#define RCC_CDCCIP2R_LPTIM1SEL_1               (0x2UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)        /*!< 0x20000000 */

+#define RCC_CDCCIP2R_LPTIM1SEL_2               (0x4UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)        /*!< 0x40000000 */

+

+/********************  Bit definition for RCC_SRDCCIPR register  ***************/

+#define RCC_SRDCCIPR_LPUART1SEL_Pos             (0U)

+#define RCC_SRDCCIPR_LPUART1SEL_Msk             (0x7UL << RCC_SRDCCIPR_LPUART1SEL_Pos)      /*!< 0x00000007 */

+#define RCC_SRDCCIPR_LPUART1SEL                 RCC_SRDCCIPR_LPUART1SEL_Msk

+#define RCC_SRDCCIPR_LPUART1SEL_0               (0x1UL << RCC_SRDCCIPR_LPUART1SEL_Pos)      /*!< 0x00000001 */

+#define RCC_SRDCCIPR_LPUART1SEL_1               (0x2UL << RCC_SRDCCIPR_LPUART1SEL_Pos)      /*!< 0x00000002 */

+#define RCC_SRDCCIPR_LPUART1SEL_2               (0x4UL << RCC_SRDCCIPR_LPUART1SEL_Pos)      /*!< 0x00000004 */

+

+#define RCC_SRDCCIPR_I2C4SEL_Pos                (8U)

+#define RCC_SRDCCIPR_I2C4SEL_Msk                (0x3UL << RCC_SRDCCIPR_I2C4SEL_Pos)         /*!< 0x00000300 */

+#define RCC_SRDCCIPR_I2C4SEL                    RCC_SRDCCIPR_I2C4SEL_Msk

+#define RCC_SRDCCIPR_I2C4SEL_0                  (0x1UL << RCC_SRDCCIPR_I2C4SEL_Pos)         /*!< 0x00000100 */

+#define RCC_SRDCCIPR_I2C4SEL_1                  (0x2UL << RCC_SRDCCIPR_I2C4SEL_Pos)         /*!< 0x00000200 */

+

+#define RCC_SRDCCIPR_LPTIM2SEL_Pos              (10U)

+#define RCC_SRDCCIPR_LPTIM2SEL_Msk              (0x7UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)       /*!< 0x00001C00 */

+#define RCC_SRDCCIPR_LPTIM2SEL                  RCC_SRDCCIPR_LPTIM2SEL_Msk

+#define RCC_SRDCCIPR_LPTIM2SEL_0                (0x1UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)       /*!< 0x00000400 */

+#define RCC_SRDCCIPR_LPTIM2SEL_1                (0x2UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)       /*!< 0x00000800 */

+#define RCC_SRDCCIPR_LPTIM2SEL_2                (0x4UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)       /*!< 0x00001000 */

+

+#define RCC_SRDCCIPR_LPTIM3SEL_Pos            (13U)

+#define RCC_SRDCCIPR_LPTIM3SEL_Msk            (0x7UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)         /*!< 0x0000E000 */

+#define RCC_SRDCCIPR_LPTIM3SEL                RCC_SRDCCIPR_LPTIM3SEL_Msk

+#define RCC_SRDCCIPR_LPTIM3SEL_0              (0x1UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)         /*!< 0x00002000 */

+#define RCC_SRDCCIPR_LPTIM3SEL_1              (0x2UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)         /*!< 0x00004000 */

+#define RCC_SRDCCIPR_LPTIM3SEL_2              (0x4UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)         /*!< 0x00008000 */

+

+#define RCC_SRDCCIPR_ADCSEL_Pos                 (16U)

+#define RCC_SRDCCIPR_ADCSEL_Msk                 (0x3UL << RCC_SRDCCIPR_ADCSEL_Pos)          /*!< 0x00030000 */

+#define RCC_SRDCCIPR_ADCSEL                     RCC_SRDCCIPR_ADCSEL_Msk

+#define RCC_SRDCCIPR_ADCSEL_0                   (0x1UL << RCC_SRDCCIPR_ADCSEL_Pos)          /*!< 0x00010000 */

+#define RCC_SRDCCIPR_ADCSEL_1                   (0x2UL << RCC_SRDCCIPR_ADCSEL_Pos)          /*!< 0x00020000 */

+

+#define RCC_SRDCCIPR_DFSDM2SEL_Pos              (27U)

+#define RCC_SRDCCIPR_DFSDM2SEL_Msk              (0x1UL << RCC_SRDCCIPR_DFSDM2SEL_Pos)       /*!< 0x08000000 */

+#define RCC_SRDCCIPR_DFSDM2SEL                   RCC_SRDCCIPR_DFSDM2SEL_Msk

+

+#define RCC_SRDCCIPR_SPI6SEL_Pos                (28U)

+#define RCC_SRDCCIPR_SPI6SEL_Msk                (0x7UL << RCC_SRDCCIPR_SPI6SEL_Pos)         /*!< 0x70000000 */

+#define RCC_SRDCCIPR_SPI6SEL                    RCC_SRDCCIPR_SPI6SEL_Msk

+#define RCC_SRDCCIPR_SPI6SEL_0                  (0x1UL << RCC_SRDCCIPR_SPI6SEL_Pos)         /*!< 0x10000000 */

+#define RCC_SRDCCIPR_SPI6SEL_1                  (0x2UL << RCC_SRDCCIPR_SPI6SEL_Pos)         /*!< 0x20000000 */

+#define RCC_SRDCCIPR_SPI6SEL_2                  (0x4UL << RCC_SRDCCIPR_SPI6SEL_Pos)         /*!< 0x40000000 */

+

+/********************  Bit definition for RCC_CIER register  ******************/

+#define RCC_CIER_LSIRDYIE_Pos                  (0U)

+#define RCC_CIER_LSIRDYIE_Msk                  (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */

+#define RCC_CIER_LSIRDYIE                      RCC_CIER_LSIRDYIE_Msk

+#define RCC_CIER_LSERDYIE_Pos                  (1U)

+#define RCC_CIER_LSERDYIE_Msk                  (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */

+#define RCC_CIER_LSERDYIE                      RCC_CIER_LSERDYIE_Msk

+#define RCC_CIER_HSIRDYIE_Pos                  (2U)

+#define RCC_CIER_HSIRDYIE_Msk                  (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */

+#define RCC_CIER_HSIRDYIE                      RCC_CIER_HSIRDYIE_Msk

+#define RCC_CIER_HSERDYIE_Pos                  (3U)

+#define RCC_CIER_HSERDYIE_Msk                  (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */

+#define RCC_CIER_HSERDYIE                      RCC_CIER_HSERDYIE_Msk

+#define RCC_CIER_CSIRDYIE_Pos                  (4U)

+#define RCC_CIER_CSIRDYIE_Msk                  (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */

+#define RCC_CIER_CSIRDYIE                      RCC_CIER_CSIRDYIE_Msk

+#define RCC_CIER_HSI48RDYIE_Pos                (5U)

+#define RCC_CIER_HSI48RDYIE_Msk                (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */

+#define RCC_CIER_HSI48RDYIE                    RCC_CIER_HSI48RDYIE_Msk

+#define RCC_CIER_PLL1RDYIE_Pos                 (6U)

+#define RCC_CIER_PLL1RDYIE_Msk                 (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */

+#define RCC_CIER_PLL1RDYIE                     RCC_CIER_PLL1RDYIE_Msk

+#define RCC_CIER_PLL2RDYIE_Pos                 (7U)

+#define RCC_CIER_PLL2RDYIE_Msk                 (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */

+#define RCC_CIER_PLL2RDYIE                     RCC_CIER_PLL2RDYIE_Msk

+#define RCC_CIER_PLL3RDYIE_Pos                 (8U)

+#define RCC_CIER_PLL3RDYIE_Msk                 (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */

+#define RCC_CIER_PLL3RDYIE                     RCC_CIER_PLL3RDYIE_Msk

+#define RCC_CIER_LSECSSIE_Pos                  (9U)

+#define RCC_CIER_LSECSSIE_Msk                  (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */

+#define RCC_CIER_LSECSSIE                      RCC_CIER_LSECSSIE_Msk

+

+/********************  Bit definition for RCC_CIFR register  ******************/

+#define RCC_CIFR_LSIRDYF_Pos                   (0U)

+#define RCC_CIFR_LSIRDYF_Msk                   (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */

+#define RCC_CIFR_LSIRDYF                       RCC_CIFR_LSIRDYF_Msk

+#define RCC_CIFR_LSERDYF_Pos                   (1U)

+#define RCC_CIFR_LSERDYF_Msk                   (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */

+#define RCC_CIFR_LSERDYF                       RCC_CIFR_LSERDYF_Msk

+#define RCC_CIFR_HSIRDYF_Pos                   (2U)

+#define RCC_CIFR_HSIRDYF_Msk                   (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */

+#define RCC_CIFR_HSIRDYF                       RCC_CIFR_HSIRDYF_Msk

+#define RCC_CIFR_HSERDYF_Pos                   (3U)

+#define RCC_CIFR_HSERDYF_Msk                   (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */

+#define RCC_CIFR_HSERDYF                       RCC_CIFR_HSERDYF_Msk

+#define RCC_CIFR_CSIRDYF_Pos                   (4U)

+#define RCC_CIFR_CSIRDYF_Msk                   (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */

+#define RCC_CIFR_CSIRDYF                       RCC_CIFR_CSIRDYF_Msk

+#define RCC_CIFR_HSI48RDYF_Pos                 (5U)

+#define RCC_CIFR_HSI48RDYF_Msk                 (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */

+#define RCC_CIFR_HSI48RDYF                     RCC_CIFR_HSI48RDYF_Msk

+#define RCC_CIFR_PLLRDYF_Pos                   (6U)

+#define RCC_CIFR_PLLRDYF_Msk                   (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */

+#define RCC_CIFR_PLLRDYF                       RCC_CIFR_PLLRDYF_Msk

+#define RCC_CIFR_PLL2RDYF_Pos                  (7U)

+#define RCC_CIFR_PLL2RDYF_Msk                  (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */

+#define RCC_CIFR_PLL2RDYF                      RCC_CIFR_PLL2RDYF_Msk

+#define RCC_CIFR_PLL3RDYF_Pos                  (8U)

+#define RCC_CIFR_PLL3RDYF_Msk                  (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */

+#define RCC_CIFR_PLL3RDYF                      RCC_CIFR_PLL3RDYF_Msk

+#define RCC_CIFR_LSECSSF_Pos                   (9U)

+#define RCC_CIFR_LSECSSF_Msk                   (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */

+#define RCC_CIFR_LSECSSF                       RCC_CIFR_LSECSSF_Msk

+#define RCC_CIFR_HSECSSF_Pos                   (10U)

+#define RCC_CIFR_HSECSSF_Msk                   (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */

+#define RCC_CIFR_HSECSSF                       RCC_CIFR_HSECSSF_Msk

+

+/********************  Bit definition for RCC_CICR register  ******************/

+#define RCC_CICR_LSIRDYC_Pos                   (0U)

+#define RCC_CICR_LSIRDYC_Msk                   (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */

+#define RCC_CICR_LSIRDYC                       RCC_CICR_LSIRDYC_Msk

+#define RCC_CICR_LSERDYC_Pos                   (1U)

+#define RCC_CICR_LSERDYC_Msk                   (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */

+#define RCC_CICR_LSERDYC                       RCC_CICR_LSERDYC_Msk

+#define RCC_CICR_HSIRDYC_Pos                   (2U)

+#define RCC_CICR_HSIRDYC_Msk                   (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */

+#define RCC_CICR_HSIRDYC                       RCC_CICR_HSIRDYC_Msk

+#define RCC_CICR_HSERDYC_Pos                   (3U)

+#define RCC_CICR_HSERDYC_Msk                   (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */

+#define RCC_CICR_HSERDYC                       RCC_CICR_HSERDYC_Msk

+#define RCC_CICR_CSIRDYC_Pos                   (4U)

+#define RCC_CICR_CSIRDYC_Msk                   (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */

+#define RCC_CICR_CSIRDYC                       RCC_CICR_CSIRDYC_Msk

+#define RCC_CICR_HSI48RDYC_Pos                 (5U)

+#define RCC_CICR_HSI48RDYC_Msk                 (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */

+#define RCC_CICR_HSI48RDYC                     RCC_CICR_HSI48RDYC_Msk

+#define RCC_CICR_PLLRDYC_Pos                   (6U)

+#define RCC_CICR_PLLRDYC_Msk                   (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */

+#define RCC_CICR_PLLRDYC                       RCC_CICR_PLLRDYC_Msk

+#define RCC_CICR_PLL2RDYC_Pos                  (7U)

+#define RCC_CICR_PLL2RDYC_Msk                  (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */

+#define RCC_CICR_PLL2RDYC                      RCC_CICR_PLL2RDYC_Msk

+#define RCC_CICR_PLL3RDYC_Pos                  (8U)

+#define RCC_CICR_PLL3RDYC_Msk                  (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */

+#define RCC_CICR_PLL3RDYC                      RCC_CICR_PLL3RDYC_Msk

+#define RCC_CICR_LSECSSC_Pos                   (9U)

+#define RCC_CICR_LSECSSC_Msk                   (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */

+#define RCC_CICR_LSECSSC                       RCC_CICR_LSECSSC_Msk

+#define RCC_CICR_HSECSSC_Pos                   (10U)

+#define RCC_CICR_HSECSSC_Msk                   (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */

+#define RCC_CICR_HSECSSC                       RCC_CICR_HSECSSC_Msk

+

+/********************  Bit definition for RCC_BDCR register  ******************/

+#define RCC_BDCR_LSEON_Pos                     (0U)

+#define RCC_BDCR_LSEON_Msk                     (0x1UL << RCC_BDCR_LSEON_Pos)   /*!< 0x00000001 */

+#define RCC_BDCR_LSEON                         RCC_BDCR_LSEON_Msk

+#define RCC_BDCR_LSERDY_Pos                    (1U)

+#define RCC_BDCR_LSERDY_Msk                    (0x1UL << RCC_BDCR_LSERDY_Pos)  /*!< 0x00000002 */

+#define RCC_BDCR_LSERDY                        RCC_BDCR_LSERDY_Msk

+#define RCC_BDCR_LSEBYP_Pos                    (2U)

+#define RCC_BDCR_LSEBYP_Msk                    (0x1UL << RCC_BDCR_LSEBYP_Pos)  /*!< 0x00000004 */

+#define RCC_BDCR_LSEBYP                        RCC_BDCR_LSEBYP_Msk

+

+#define RCC_BDCR_LSEDRV_Pos                    (3U)

+#define RCC_BDCR_LSEDRV_Msk                    (0x3UL << RCC_BDCR_LSEDRV_Pos)  /*!< 0x00000018 */

+#define RCC_BDCR_LSEDRV                        RCC_BDCR_LSEDRV_Msk

+#define RCC_BDCR_LSEDRV_0                      (0x1UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000008 */

+#define RCC_BDCR_LSEDRV_1                      (0x2UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000010 */

+

+#define RCC_BDCR_LSECSSON_Pos                  (5U)

+#define RCC_BDCR_LSECSSON_Msk                  (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */

+#define RCC_BDCR_LSECSSON                      RCC_BDCR_LSECSSON_Msk

+#define RCC_BDCR_LSECSSD_Pos                   (6U)

+#define RCC_BDCR_LSECSSD_Msk                   (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */

+#define RCC_BDCR_LSECSSD                       RCC_BDCR_LSECSSD_Msk

+#define RCC_BDCR_LSEEXT_Pos                    (7U)

+#define RCC_BDCR_LSEEXT_Msk                    (0x1UL << RCC_BDCR_LSEEXT_Pos)  /*!< 0x00000080 */

+#define RCC_BDCR_LSEEXT                        RCC_BDCR_LSEEXT_Msk

+

+#define RCC_BDCR_RTCSEL_Pos                    (8U)

+#define RCC_BDCR_RTCSEL_Msk                    (0x3UL << RCC_BDCR_RTCSEL_Pos)  /*!< 0x00000300 */

+#define RCC_BDCR_RTCSEL                        RCC_BDCR_RTCSEL_Msk

+#define RCC_BDCR_RTCSEL_0                      (0x1UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000100 */

+#define RCC_BDCR_RTCSEL_1                      (0x2UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000200 */

+

+#define RCC_BDCR_RTCEN_Pos                     (15U)

+#define RCC_BDCR_RTCEN_Msk                     (0x1UL << RCC_BDCR_RTCEN_Pos)   /*!< 0x00008000 */

+#define RCC_BDCR_RTCEN                         RCC_BDCR_RTCEN_Msk

+#define RCC_BDCR_VSWRST_Pos                    (16U)

+#define RCC_BDCR_VSWRST_Msk                    (0x1UL << RCC_BDCR_VSWRST_Pos)   /*!< 0x00010000 */

+#define RCC_BDCR_VSWRST                        RCC_BDCR_VSWRST_Msk

+/* Legacy define */

+#define RCC_BDCR_BDRST_Pos                     RCC_BDCR_VSWRST_Pos

+#define RCC_BDCR_BDRST_Msk                     RCC_BDCR_VSWRST_Msk

+#define RCC_BDCR_BDRST                         RCC_BDCR_VSWRST

+/********************  Bit definition for RCC_CSR register  *******************/

+#define RCC_CSR_LSION_Pos                      (0U)

+#define RCC_CSR_LSION_Msk                      (0x1UL << RCC_CSR_LSION_Pos)    /*!< 0x00000001 */

+#define RCC_CSR_LSION                          RCC_CSR_LSION_Msk

+#define RCC_CSR_LSIRDY_Pos                     (1U)

+#define RCC_CSR_LSIRDY_Msk                     (0x1UL << RCC_CSR_LSIRDY_Pos)   /*!< 0x00000002 */

+#define RCC_CSR_LSIRDY                         RCC_CSR_LSIRDY_Msk

+

+

+/********************  Bit definition for RCC_AHB3ENR register  **************/

+#define RCC_AHB3ENR_MDMAEN_Pos                 (0U)

+#define RCC_AHB3ENR_MDMAEN_Msk                 (0x1UL << RCC_AHB3ENR_MDMAEN_Pos)       /*!< 0x00000001 */

+#define RCC_AHB3ENR_MDMAEN                     RCC_AHB3ENR_MDMAEN_Msk

+#define RCC_AHB3ENR_DMA2DEN_Pos                (4U)

+#define RCC_AHB3ENR_DMA2DEN_Msk                (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos)      /*!< 0x00000010 */

+#define RCC_AHB3ENR_DMA2DEN                    RCC_AHB3ENR_DMA2DEN_Msk

+#define RCC_AHB3ENR_JPGDECEN_Pos               (5U)

+#define RCC_AHB3ENR_JPGDECEN_Msk               (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos)     /*!< 0x00000020 */

+#define RCC_AHB3ENR_JPGDECEN                   RCC_AHB3ENR_JPGDECEN_Msk

+#define RCC_AHB3ENR_FMCEN_Pos                  (12U)

+#define RCC_AHB3ENR_FMCEN_Msk                  (0x1UL << RCC_AHB3ENR_FMCEN_Pos)        /*!< 0x00001000 */

+#define RCC_AHB3ENR_FMCEN                      RCC_AHB3ENR_FMCEN_Msk

+#define RCC_AHB3ENR_OSPI1EN_Pos                (14U)

+#define RCC_AHB3ENR_OSPI1EN_Msk                (0x1UL << RCC_AHB3ENR_OSPI1EN_Pos)      /*!< 0x00004000 */

+#define RCC_AHB3ENR_OSPI1EN                    RCC_AHB3ENR_OSPI1EN_Msk

+#define RCC_AHB3ENR_SDMMC1EN_Pos               (16U)

+#define RCC_AHB3ENR_SDMMC1EN_Msk               (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos)     /*!< 0x00010000 */

+#define RCC_AHB3ENR_SDMMC1EN                   RCC_AHB3ENR_SDMMC1EN_Msk

+#define RCC_AHB3ENR_OSPI2EN_Pos                (19U)

+#define RCC_AHB3ENR_OSPI2EN_Msk                (0x1UL << RCC_AHB3ENR_OSPI2EN_Pos)      /*!< 0x00040000 */

+#define RCC_AHB3ENR_OSPI2EN                    RCC_AHB3ENR_OSPI2EN_Msk

+#define RCC_AHB3ENR_IOMNGREN_Pos               (21U)

+#define RCC_AHB3ENR_IOMNGREN_Msk               (0x1UL << RCC_AHB3ENR_IOMNGREN_Pos)     /*!< 0x00100000 */

+#define RCC_AHB3ENR_IOMNGREN                   RCC_AHB3ENR_IOMNGREN_Msk

+#define RCC_AHB3ENR_OTFDEC1EN_Pos              (22U)

+#define RCC_AHB3ENR_OTFDEC1EN_Msk              (0x1UL << RCC_AHB3ENR_OTFDEC1EN_Pos)    /*!< 0x00200000 */

+#define RCC_AHB3ENR_OTFDEC1EN                  RCC_AHB3ENR_OTFDEC1EN_Msk

+#define RCC_AHB3ENR_OTFDEC2EN_Pos              (23U)

+#define RCC_AHB3ENR_OTFDEC2EN_Msk              (0x1UL << RCC_AHB3ENR_OTFDEC2EN_Pos)    /*!< 0x00400000 */

+#define RCC_AHB3ENR_OTFDEC2EN                  RCC_AHB3ENR_OTFDEC2EN_Msk

+#define RCC_AHB3ENR_GFXMMUEN_Pos               (24U)

+#define RCC_AHB3ENR_GFXMMUEN_Msk               (0x1UL << RCC_AHB3ENR_GFXMMUEN_Pos)     /*!< 0x00800000 */

+#define RCC_AHB3ENR_GFXMMUEN                   RCC_AHB3ENR_GFXMMUEN_Msk

+

+/********************  Bit definition for RCC_AHB1ENR register  ***************/

+#define RCC_AHB1ENR_DMA1EN_Pos                 (0U)

+#define RCC_AHB1ENR_DMA1EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)          /*!< 0x00000001 */

+#define RCC_AHB1ENR_DMA1EN                     RCC_AHB1ENR_DMA1EN_Msk

+#define RCC_AHB1ENR_DMA2EN_Pos                 (1U)

+#define RCC_AHB1ENR_DMA2EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)          /*!< 0x00000002 */

+#define RCC_AHB1ENR_DMA2EN                     RCC_AHB1ENR_DMA2EN_Msk

+#define RCC_AHB1ENR_ADC12EN_Pos                (5U)

+#define RCC_AHB1ENR_ADC12EN_Msk                (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)         /*!< 0x00000020 */

+#define RCC_AHB1ENR_ADC12EN                    RCC_AHB1ENR_ADC12EN_Msk

+#define RCC_AHB1ENR_CRCEN_Pos                  (9U)

+#define RCC_AHB1ENR_CRCEN_Msk                  (0x1UL << RCC_AHB1ENR_CRCEN_Pos)           /*!< 0x00000200 */

+#define RCC_AHB1ENR_CRCEN                      RCC_AHB1ENR_CRCEN_Msk

+#define RCC_AHB1ENR_USB1OTGHSEN_Pos            (25U)

+#define RCC_AHB1ENR_USB1OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos)     /*!< 0x02000000 */

+#define RCC_AHB1ENR_USB1OTGHSEN                RCC_AHB1ENR_USB1OTGHSEN_Msk

+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos        (26U)

+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */

+#define RCC_AHB1ENR_USB1OTGHSULPIEN            RCC_AHB1ENR_USB1OTGHSULPIEN_Msk

+

+/********************  Bit definition for RCC_AHB2ENR register  ***************/

+#define RCC_AHB2ENR_DCMI_PSSIEN_Pos            (0U)

+#define RCC_AHB2ENR_DCMI_PSSIEN_Msk            (0x1UL << RCC_AHB2ENR_DCMI_PSSIEN_Pos)     /*!< 0x00000001 */

+#define RCC_AHB2ENR_DCMI_PSSIEN                RCC_AHB2ENR_DCMI_PSSIEN_Msk

+#define RCC_AHB2ENR_HSEMEN_Pos                 (2U)

+#define RCC_AHB2ENR_HSEMEN_Msk                 (0x1UL << RCC_AHB2ENR_HSEMEN_Pos)          /*!< 0x00000004 */

+#define RCC_AHB2ENR_HSEMEN                     RCC_AHB2ENR_HSEMEN_Msk

+#define RCC_AHB2ENR_CRYPEN_Pos                 (4U)

+#define RCC_AHB2ENR_CRYPEN_Msk                 (0x1UL << RCC_AHB2ENR_CRYPEN_Pos)          /*!< 0x00000010 */

+#define RCC_AHB2ENR_CRYPEN                     RCC_AHB2ENR_CRYPEN_Msk

+#define RCC_AHB2ENR_HASHEN_Pos                 (5U)

+#define RCC_AHB2ENR_HASHEN_Msk                 (0x1UL << RCC_AHB2ENR_HASHEN_Pos)          /*!< 0x00000020 */

+#define RCC_AHB2ENR_HASHEN                     RCC_AHB2ENR_HASHEN_Msk

+#define RCC_AHB2ENR_RNGEN_Pos                  (6U)

+#define RCC_AHB2ENR_RNGEN_Msk                  (0x1UL << RCC_AHB2ENR_RNGEN_Pos)           /*!< 0x00000040 */

+#define RCC_AHB2ENR_RNGEN                      RCC_AHB2ENR_RNGEN_Msk

+#define RCC_AHB2ENR_SDMMC2EN_Pos               (9U)

+#define RCC_AHB2ENR_SDMMC2EN_Msk               (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)        /*!< 0x00000200 */

+#define RCC_AHB2ENR_SDMMC2EN                   RCC_AHB2ENR_SDMMC2EN_Msk

+#define RCC_AHB2ENR_BDMA1EN_Pos                (11U)

+#define RCC_AHB2ENR_BDMA1EN_Msk                (0x1UL << RCC_AHB2ENR_BDMA1EN_Pos)         /*!< 0x00000800 */

+#define RCC_AHB2ENR_BDMA1EN                    RCC_AHB2ENR_BDMA1EN_Msk

+#define RCC_AHB2ENR_AHBSRAM1EN_Pos             (29U)

+#define RCC_AHB2ENR_AHBSRAM1EN_Msk             (0x1UL << RCC_AHB2ENR_AHBSRAM1EN_Pos)       /*!< 0x20000000 */

+#define RCC_AHB2ENR_AHBSRAM1EN                 RCC_AHB2ENR_AHBSRAM1EN_Msk

+#define RCC_AHB2ENR_AHBSRAM2EN_Pos             (30U)

+#define RCC_AHB2ENR_AHBSRAM2EN_Msk             (0x1UL << RCC_AHB2ENR_AHBSRAM2EN_Pos)       /*!< 0x40000000 */

+#define RCC_AHB2ENR_AHBSRAM2EN                 RCC_AHB2ENR_AHBSRAM2EN_Msk

+

+/* Legacy define */

+#define RCC_AHB2ENR_DCMIEN_Pos                 RCC_AHB2ENR_DCMI_PSSIEN_Pos

+#define RCC_AHB2ENR_DCMIEN_Msk                 RCC_AHB2ENR_DCMI_PSSIEN_Msk

+#define RCC_AHB2ENR_DCMIEN                     RCC_AHB2ENR_DCMI_PSSIEN

+

+/********************  Bit definition for RCC_AHB4ENR register  ******************/

+#define RCC_AHB4ENR_GPIOAEN_Pos                (0U)

+#define RCC_AHB4ENR_GPIOAEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)         /*!< 0x00000001 */

+#define RCC_AHB4ENR_GPIOAEN                    RCC_AHB4ENR_GPIOAEN_Msk

+#define RCC_AHB4ENR_GPIOBEN_Pos                (1U)

+#define RCC_AHB4ENR_GPIOBEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)         /*!< 0x00000002 */

+#define RCC_AHB4ENR_GPIOBEN                    RCC_AHB4ENR_GPIOBEN_Msk

+#define RCC_AHB4ENR_GPIOCEN_Pos                (2U)

+#define RCC_AHB4ENR_GPIOCEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)         /*!< 0x00000004 */

+#define RCC_AHB4ENR_GPIOCEN                    RCC_AHB4ENR_GPIOCEN_Msk

+#define RCC_AHB4ENR_GPIODEN_Pos                (3U)

+#define RCC_AHB4ENR_GPIODEN_Msk                (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)         /*!< 0x00000008 */

+#define RCC_AHB4ENR_GPIODEN                    RCC_AHB4ENR_GPIODEN_Msk

+#define RCC_AHB4ENR_GPIOEEN_Pos                (4U)

+#define RCC_AHB4ENR_GPIOEEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)         /*!< 0x00000010 */

+#define RCC_AHB4ENR_GPIOEEN                    RCC_AHB4ENR_GPIOEEN_Msk

+#define RCC_AHB4ENR_GPIOFEN_Pos                (5U)

+#define RCC_AHB4ENR_GPIOFEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)         /*!< 0x00000020 */

+#define RCC_AHB4ENR_GPIOFEN                    RCC_AHB4ENR_GPIOFEN_Msk

+#define RCC_AHB4ENR_GPIOGEN_Pos                (6U)

+#define RCC_AHB4ENR_GPIOGEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)         /*!< 0x00000040 */

+#define RCC_AHB4ENR_GPIOGEN                    RCC_AHB4ENR_GPIOGEN_Msk

+#define RCC_AHB4ENR_GPIOHEN_Pos                (7U)

+#define RCC_AHB4ENR_GPIOHEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)         /*!< 0x00000080 */

+#define RCC_AHB4ENR_GPIOHEN                    RCC_AHB4ENR_GPIOHEN_Msk

+#define RCC_AHB4ENR_GPIOIEN_Pos                (8U)

+#define RCC_AHB4ENR_GPIOIEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos)         /*!< 0x00000100 */

+#define RCC_AHB4ENR_GPIOIEN                    RCC_AHB4ENR_GPIOIEN_Msk

+#define RCC_AHB4ENR_GPIOJEN_Pos                (9U)

+#define RCC_AHB4ENR_GPIOJEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos)         /*!< 0x00000200 */

+#define RCC_AHB4ENR_GPIOJEN                    RCC_AHB4ENR_GPIOJEN_Msk

+#define RCC_AHB4ENR_GPIOKEN_Pos                (10U)

+#define RCC_AHB4ENR_GPIOKEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos)         /*!< 0x00000400 */

+#define RCC_AHB4ENR_GPIOKEN                    RCC_AHB4ENR_GPIOKEN_Msk

+#define RCC_AHB4ENR_BDMA2EN_Pos                (21U)

+#define RCC_AHB4ENR_BDMA2EN_Msk                (0x1UL << RCC_AHB4ENR_BDMA2EN_Pos)         /*!< 0x00080000 */

+#define RCC_AHB4ENR_BDMA2EN                    RCC_AHB4ENR_BDMA2EN_Msk

+#define RCC_AHB4ENR_BKPRAMEN_Pos               (28U)

+#define RCC_AHB4ENR_BKPRAMEN_Msk               (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)        /*!< 0x10000000 */

+#define RCC_AHB4ENR_BKPRAMEN                   RCC_AHB4ENR_BKPRAMEN_Msk

+#define RCC_AHB4ENR_SRDSRAMEN_Pos              (29U)

+#define RCC_AHB4ENR_SRDSRAMEN_Msk              (0x1UL << RCC_AHB4ENR_SRDSRAMEN_Pos)       /*!< 0x20000000 */

+#define RCC_AHB4ENR_SRDSRAMEN                  RCC_AHB4ENR_SRDSRAMEN_Msk

+

+/********************  Bit definition for RCC_APB3ENR register  ******************/

+#define RCC_APB3ENR_LTDCEN_Pos                 (3U)

+#define RCC_APB3ENR_LTDCEN_Msk                 (0x1UL << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */

+#define RCC_APB3ENR_LTDCEN                     RCC_APB3ENR_LTDCEN_Msk

+#define RCC_APB3ENR_WWDGEN_Pos                 (6U)

+#define RCC_APB3ENR_WWDGEN_Msk                 (0x1UL << RCC_APB3ENR_WWDGEN_Pos) /*!< 0x00000040 */

+#define RCC_APB3ENR_WWDGEN                     RCC_APB3ENR_WWDGEN_Msk

+

+/* Legacy define */

+#define RCC_APB3ENR_WWDG1EN_Pos                 RCC_APB3ENR_WWDGEN_Pos

+#define RCC_APB3ENR_WWDG1EN_Msk                 RCC_APB3ENR_WWDGEN_Msk

+#define RCC_APB3ENR_WWDG1EN                     RCC_APB3ENR_WWDGEN

+/********************  Bit definition for RCC_APB1LENR register  ******************/

+

+#define RCC_APB1LENR_TIM2EN_Pos                (0U)

+#define RCC_APB1LENR_TIM2EN_Msk                (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */

+#define RCC_APB1LENR_TIM2EN                    RCC_APB1LENR_TIM2EN_Msk

+#define RCC_APB1LENR_TIM3EN_Pos                (1U)

+#define RCC_APB1LENR_TIM3EN_Msk                (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */

+#define RCC_APB1LENR_TIM3EN                    RCC_APB1LENR_TIM3EN_Msk

+#define RCC_APB1LENR_TIM4EN_Pos                (2U)

+#define RCC_APB1LENR_TIM4EN_Msk                (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */

+#define RCC_APB1LENR_TIM4EN                    RCC_APB1LENR_TIM4EN_Msk

+#define RCC_APB1LENR_TIM5EN_Pos                (3U)

+#define RCC_APB1LENR_TIM5EN_Msk                (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */

+#define RCC_APB1LENR_TIM5EN                    RCC_APB1LENR_TIM5EN_Msk

+#define RCC_APB1LENR_TIM6EN_Pos                (4U)

+#define RCC_APB1LENR_TIM6EN_Msk                (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */

+#define RCC_APB1LENR_TIM6EN                    RCC_APB1LENR_TIM6EN_Msk

+#define RCC_APB1LENR_TIM7EN_Pos                (5U)

+#define RCC_APB1LENR_TIM7EN_Msk                (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */

+#define RCC_APB1LENR_TIM7EN                    RCC_APB1LENR_TIM7EN_Msk

+#define RCC_APB1LENR_TIM12EN_Pos               (6U)

+#define RCC_APB1LENR_TIM12EN_Msk               (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */

+#define RCC_APB1LENR_TIM12EN                   RCC_APB1LENR_TIM12EN_Msk

+#define RCC_APB1LENR_TIM13EN_Pos               (7U)

+#define RCC_APB1LENR_TIM13EN_Msk               (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */

+#define RCC_APB1LENR_TIM13EN                   RCC_APB1LENR_TIM13EN_Msk

+#define RCC_APB1LENR_TIM14EN_Pos               (8U)

+#define RCC_APB1LENR_TIM14EN_Msk               (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */

+#define RCC_APB1LENR_TIM14EN                   RCC_APB1LENR_TIM14EN_Msk

+#define RCC_APB1LENR_LPTIM1EN_Pos              (9U)

+#define RCC_APB1LENR_LPTIM1EN_Msk              (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */

+#define RCC_APB1LENR_LPTIM1EN                  RCC_APB1LENR_LPTIM1EN_Msk

+

+

+#define RCC_APB1LENR_SPI2EN_Pos                (14U)

+#define RCC_APB1LENR_SPI2EN_Msk                (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */

+#define RCC_APB1LENR_SPI2EN                    RCC_APB1LENR_SPI2EN_Msk

+#define RCC_APB1LENR_SPI3EN_Pos                (15U)

+#define RCC_APB1LENR_SPI3EN_Msk                (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */

+#define RCC_APB1LENR_SPI3EN                    RCC_APB1LENR_SPI3EN_Msk

+#define RCC_APB1LENR_SPDIFRXEN_Pos             (16U)

+#define RCC_APB1LENR_SPDIFRXEN_Msk             (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */

+#define RCC_APB1LENR_SPDIFRXEN                 RCC_APB1LENR_SPDIFRXEN_Msk

+#define RCC_APB1LENR_USART2EN_Pos              (17U)

+#define RCC_APB1LENR_USART2EN_Msk              (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */

+#define RCC_APB1LENR_USART2EN                  RCC_APB1LENR_USART2EN_Msk

+#define RCC_APB1LENR_USART3EN_Pos              (18U)

+#define RCC_APB1LENR_USART3EN_Msk              (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */

+#define RCC_APB1LENR_USART3EN                  RCC_APB1LENR_USART3EN_Msk

+#define RCC_APB1LENR_UART4EN_Pos               (19U)

+#define RCC_APB1LENR_UART4EN_Msk               (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */

+#define RCC_APB1LENR_UART4EN                   RCC_APB1LENR_UART4EN_Msk

+#define RCC_APB1LENR_UART5EN_Pos               (20U)

+#define RCC_APB1LENR_UART5EN_Msk               (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */

+#define RCC_APB1LENR_UART5EN                   RCC_APB1LENR_UART5EN_Msk

+#define RCC_APB1LENR_I2C1EN_Pos                (21U)

+#define RCC_APB1LENR_I2C1EN_Msk                (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */

+#define RCC_APB1LENR_I2C1EN                    RCC_APB1LENR_I2C1EN_Msk

+#define RCC_APB1LENR_I2C2EN_Pos                (22U)

+#define RCC_APB1LENR_I2C2EN_Msk                (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */

+#define RCC_APB1LENR_I2C2EN                    RCC_APB1LENR_I2C2EN_Msk

+#define RCC_APB1LENR_I2C3EN_Pos                (23U)

+#define RCC_APB1LENR_I2C3EN_Msk                (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */

+#define RCC_APB1LENR_I2C3EN                    RCC_APB1LENR_I2C3EN_Msk

+#define RCC_APB1LENR_CECEN_Pos                 (27U)

+#define RCC_APB1LENR_CECEN_Msk                 (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */

+#define RCC_APB1LENR_CECEN                     RCC_APB1LENR_CECEN_Msk

+#define RCC_APB1LENR_DAC12EN_Pos               (29U)

+#define RCC_APB1LENR_DAC12EN_Msk               (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */

+#define RCC_APB1LENR_DAC12EN                   RCC_APB1LENR_DAC12EN_Msk

+#define RCC_APB1LENR_UART7EN_Pos               (30U)

+#define RCC_APB1LENR_UART7EN_Msk               (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */

+#define RCC_APB1LENR_UART7EN                   RCC_APB1LENR_UART7EN_Msk

+#define RCC_APB1LENR_UART8EN_Pos               (31U)

+#define RCC_APB1LENR_UART8EN_Msk               (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */

+#define RCC_APB1LENR_UART8EN                   RCC_APB1LENR_UART8EN_Msk

+

+/* Legacy define */

+#define RCC_APB1LENR_HDMICECEN_Pos             RCC_APB1LENR_CECEN_Pos

+#define RCC_APB1LENR_HDMICECEN_Msk             RCC_APB1LENR_CECEN_Msk

+#define RCC_APB1LENR_HDMICECEN                 RCC_APB1LENR_CECEN

+/********************  Bit definition for RCC_APB1HENR register  ******************/

+#define RCC_APB1HENR_CRSEN_Pos                 (1U)

+#define RCC_APB1HENR_CRSEN_Msk                 (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1HENR_CRSEN                     RCC_APB1HENR_CRSEN_Msk

+#define RCC_APB1HENR_SWPMIEN_Pos               (2U)

+#define RCC_APB1HENR_SWPMIEN_Msk               (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1HENR_SWPMIEN                   RCC_APB1HENR_SWPMIEN_Msk

+#define RCC_APB1HENR_OPAMPEN_Pos               (4U)

+#define RCC_APB1HENR_OPAMPEN_Msk               (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1HENR_OPAMPEN                   RCC_APB1HENR_OPAMPEN_Msk

+#define RCC_APB1HENR_MDIOSEN_Pos               (5U)

+#define RCC_APB1HENR_MDIOSEN_Msk               (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1HENR_MDIOSEN                   RCC_APB1HENR_MDIOSEN_Msk

+#define RCC_APB1HENR_FDCANEN_Pos               (8U)

+#define RCC_APB1HENR_FDCANEN_Msk               (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1HENR_FDCANEN                   RCC_APB1HENR_FDCANEN_Msk

+

+/********************  Bit definition for RCC_APB2ENR register  ******************/

+#define RCC_APB2ENR_TIM1EN_Pos                 (0U)

+#define RCC_APB2ENR_TIM1EN_Msk                 (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */

+#define RCC_APB2ENR_TIM1EN                     RCC_APB2ENR_TIM1EN_Msk

+#define RCC_APB2ENR_TIM8EN_Pos                 (1U)

+#define RCC_APB2ENR_TIM8EN_Msk                 (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */

+#define RCC_APB2ENR_TIM8EN                     RCC_APB2ENR_TIM8EN_Msk

+#define RCC_APB2ENR_USART1EN_Pos               (4U)

+#define RCC_APB2ENR_USART1EN_Msk               (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */

+#define RCC_APB2ENR_USART1EN                   RCC_APB2ENR_USART1EN_Msk

+#define RCC_APB2ENR_USART6EN_Pos               (5U)

+#define RCC_APB2ENR_USART6EN_Msk               (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */

+#define RCC_APB2ENR_USART6EN                   RCC_APB2ENR_USART6EN_Msk

+#define RCC_APB2ENR_UART9EN_Pos                (6U)

+#define RCC_APB2ENR_UART9EN_Msk                (0x1UL << RCC_APB2ENR_UART9EN_Pos) /*!< 0x00000040 */

+#define RCC_APB2ENR_UART9EN                    RCC_APB2ENR_UART9EN_Msk

+#define RCC_APB2ENR_USART10EN_Pos              (7U)

+#define RCC_APB2ENR_USART10EN_Msk              (0x1UL << RCC_APB2ENR_USART10EN_Pos) /*!< 0x00000080 */

+#define RCC_APB2ENR_USART10EN                   RCC_APB2ENR_USART10EN_Msk

+#define RCC_APB2ENR_SPI1EN_Pos                 (12U)

+#define RCC_APB2ENR_SPI1EN_Msk                 (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */

+#define RCC_APB2ENR_SPI1EN                     RCC_APB2ENR_SPI1EN_Msk

+#define RCC_APB2ENR_SPI4EN_Pos                 (13U)

+#define RCC_APB2ENR_SPI4EN_Msk                 (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */

+#define RCC_APB2ENR_SPI4EN                     RCC_APB2ENR_SPI4EN_Msk

+#define RCC_APB2ENR_TIM15EN_Pos                (16U)

+#define RCC_APB2ENR_TIM15EN_Msk                (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */

+#define RCC_APB2ENR_TIM15EN                    RCC_APB2ENR_TIM15EN_Msk

+#define RCC_APB2ENR_TIM16EN_Pos                (17U)

+#define RCC_APB2ENR_TIM16EN_Msk                (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */

+#define RCC_APB2ENR_TIM16EN                    RCC_APB2ENR_TIM16EN_Msk

+#define RCC_APB2ENR_TIM17EN_Pos                (18U)

+#define RCC_APB2ENR_TIM17EN_Msk                (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */

+#define RCC_APB2ENR_TIM17EN                    RCC_APB2ENR_TIM17EN_Msk

+#define RCC_APB2ENR_SPI5EN_Pos                 (20U)

+#define RCC_APB2ENR_SPI5EN_Msk                 (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */

+#define RCC_APB2ENR_SPI5EN                     RCC_APB2ENR_SPI5EN_Msk

+#define RCC_APB2ENR_SAI1EN_Pos                 (22U)

+#define RCC_APB2ENR_SAI1EN_Msk                 (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */

+#define RCC_APB2ENR_SAI1EN                     RCC_APB2ENR_SAI1EN_Msk

+#define RCC_APB2ENR_SAI2EN_Pos                 (23U)

+#define RCC_APB2ENR_SAI2EN_Msk                 (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */

+#define RCC_APB2ENR_SAI2EN                     RCC_APB2ENR_SAI2EN_Msk

+#define RCC_APB2ENR_DFSDM1EN_Pos               (30U)

+#define RCC_APB2ENR_DFSDM1EN_Msk               (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x40000000 */

+#define RCC_APB2ENR_DFSDM1EN                   RCC_APB2ENR_DFSDM1EN_Msk

+

+/********************  Bit definition for RCC_APB4ENR register  ******************/

+#define RCC_APB4ENR_SYSCFGEN_Pos               (1U)

+#define RCC_APB4ENR_SYSCFGEN_Msk               (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */

+#define RCC_APB4ENR_SYSCFGEN                   RCC_APB4ENR_SYSCFGEN_Msk

+#define RCC_APB4ENR_LPUART1EN_Pos              (3U)

+#define RCC_APB4ENR_LPUART1EN_Msk              (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */

+#define RCC_APB4ENR_LPUART1EN                  RCC_APB4ENR_LPUART1EN_Msk

+#define RCC_APB4ENR_SPI6EN_Pos                 (5U)

+#define RCC_APB4ENR_SPI6EN_Msk                 (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */

+#define RCC_APB4ENR_SPI6EN                     RCC_APB4ENR_SPI6EN_Msk

+#define RCC_APB4ENR_I2C4EN_Pos                 (7U)

+#define RCC_APB4ENR_I2C4EN_Msk                 (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */

+#define RCC_APB4ENR_I2C4EN                     RCC_APB4ENR_I2C4EN_Msk

+#define RCC_APB4ENR_LPTIM2EN_Pos               (9U)

+#define RCC_APB4ENR_LPTIM2EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */

+#define RCC_APB4ENR_LPTIM2EN                   RCC_APB4ENR_LPTIM2EN_Msk

+#define RCC_APB4ENR_LPTIM3EN_Pos               (10U)

+#define RCC_APB4ENR_LPTIM3EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */

+#define RCC_APB4ENR_LPTIM3EN                   RCC_APB4ENR_LPTIM3EN_Msk

+#define RCC_APB4ENR_DAC2EN_Pos                 (13U)

+#define RCC_APB4ENR_DAC2EN_Msk                 (0x1UL << RCC_APB4ENR_DAC2EN_Pos) /*!< 0x00002000 */

+#define RCC_APB4ENR_DAC2EN                     RCC_APB4ENR_DAC2EN_Msk

+#define RCC_APB4ENR_COMP12EN_Pos               (14U)

+#define RCC_APB4ENR_COMP12EN_Msk               (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */

+#define RCC_APB4ENR_COMP12EN                   RCC_APB4ENR_COMP12EN_Msk

+#define RCC_APB4ENR_VREFEN_Pos                 (15U)

+#define RCC_APB4ENR_VREFEN_Msk                 (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */

+#define RCC_APB4ENR_VREFEN                     RCC_APB4ENR_VREFEN_Msk

+#define RCC_APB4ENR_RTCAPBEN_Pos               (16U)

+#define RCC_APB4ENR_RTCAPBEN_Msk               (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */

+#define RCC_APB4ENR_RTCAPBEN                   RCC_APB4ENR_RTCAPBEN_Msk

+

+#define RCC_APB4ENR_DTSEN_Pos                  (26U)

+#define RCC_APB4ENR_DTSEN_Msk                  (0x1UL << RCC_APB4ENR_DTSEN_Pos) /*!< 0x04000000 */

+#define RCC_APB4ENR_DTSEN                      RCC_APB4ENR_DTSEN_Msk

+#define RCC_APB4ENR_DFSDM2EN_Pos               (27U)

+#define RCC_APB4ENR_DFSDM2EN_Msk               (0x1UL << RCC_APB4ENR_DFSDM2EN_Pos) /*!< 0x08000000 */

+#define RCC_APB4ENR_DFSDM2EN                   RCC_APB4ENR_DFSDM2EN_Msk

+

+/********************  Bit definition for RCC_AHB3RSTR register  ***************/

+#define RCC_AHB3RSTR_MDMARST_Pos               (0U)

+#define RCC_AHB3RSTR_MDMARST_Msk               (0x1UL << RCC_AHB3RSTR_MDMARST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB3RSTR_MDMARST                   RCC_AHB3RSTR_MDMARST_Msk

+#define RCC_AHB3RSTR_DMA2DRST_Pos              (4U)

+#define RCC_AHB3RSTR_DMA2DRST_Msk              (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos)     /*!< 0x00000010 */

+#define RCC_AHB3RSTR_DMA2DRST                  RCC_AHB3RSTR_DMA2DRST_Msk

+#define RCC_AHB3RSTR_JPGDECRST_Pos             (5U)

+#define RCC_AHB3RSTR_JPGDECRST_Msk             (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos)    /*!< 0x00000020 */

+#define RCC_AHB3RSTR_JPGDECRST                 RCC_AHB3RSTR_JPGDECRST_Msk

+#define RCC_AHB3RSTR_FMCRST_Pos                (12U)

+#define RCC_AHB3RSTR_FMCRST_Msk                (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)      /*!< 0x00001000 */

+#define RCC_AHB3RSTR_FMCRST                    RCC_AHB3RSTR_FMCRST_Msk

+#define RCC_AHB3RSTR_OSPI1RST_Pos              (14U)

+#define RCC_AHB3RSTR_OSPI1RST_Msk              (0x1UL << RCC_AHB3RSTR_OSPI1RST_Pos)    /*!< 0x00004000 */

+#define RCC_AHB3RSTR_OSPI1RST                   RCC_AHB3RSTR_OSPI1RST_Msk

+#define RCC_AHB3RSTR_SDMMC1RST_Pos             (16U)

+#define RCC_AHB3RSTR_SDMMC1RST_Msk             (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos)   /*!< 0x00010000 */

+#define RCC_AHB3RSTR_SDMMC1RST                 RCC_AHB3RSTR_SDMMC1RST_Msk

+#define RCC_AHB3RSTR_OSPI2RST_Pos              (19U)

+#define RCC_AHB3RSTR_OSPI2RST_Msk              (0x1UL << RCC_AHB3RSTR_OSPI2RST_Pos)    /*!< 0x00008000 */

+#define RCC_AHB3RSTR_OSPI2RST                  RCC_AHB3RSTR_OSPI2RST_Msk

+#define RCC_AHB3RSTR_IOMNGRRST_Pos             (21U)

+#define RCC_AHB3RSTR_IOMNGRRST_Msk             (0x1UL << RCC_AHB3RSTR_IOMNGRRST_Pos)   /*!< 0x00020000 */

+#define RCC_AHB3RSTR_IOMNGRRST                 RCC_AHB3RSTR_IOMNGRRST_Msk

+#define RCC_AHB3RSTR_OTFDEC1RST_Pos            (22U)

+#define RCC_AHB3RSTR_OTFDEC1RST_Msk            (0x1UL << RCC_AHB3RSTR_OTFDEC1RST_Pos)  /*!< 0x00040000 */

+#define RCC_AHB3RSTR_OTFDEC1RST                RCC_AHB3RSTR_OTFDEC1RST_Msk

+#define RCC_AHB3RSTR_OTFDEC2RST_Pos            (23U)

+#define RCC_AHB3RSTR_OTFDEC2RST_Msk            (0x1UL << RCC_AHB3RSTR_OTFDEC2RST_Pos)  /*!< 0x00080000 */

+#define RCC_AHB3RSTR_OTFDEC2RST                RCC_AHB3RSTR_OTFDEC2RST_Msk

+#define RCC_AHB3RSTR_GFXMMURST_Pos             (24U)

+#define RCC_AHB3RSTR_GFXMMURST_Msk             (0x1UL << RCC_AHB3RSTR_GFXMMURST_Pos)   /*!< 0x00100000 */

+#define RCC_AHB3RSTR_GFXMMURST                 RCC_AHB3RSTR_GFXMMURST_Msk

+

+

+/********************  Bit definition for RCC_AHB1RSTR register  ***************/

+#define RCC_AHB1RSTR_DMA1RST_Pos               (0U)

+#define RCC_AHB1RSTR_DMA1RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB1RSTR_DMA1RST                   RCC_AHB1RSTR_DMA1RST_Msk

+#define RCC_AHB1RSTR_DMA2RST_Pos               (1U)

+#define RCC_AHB1RSTR_DMA2RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)      /*!< 0x00000002 */

+#define RCC_AHB1RSTR_DMA2RST                   RCC_AHB1RSTR_DMA2RST_Msk

+#define RCC_AHB1RSTR_ADC12RST_Pos              (5U)

+#define RCC_AHB1RSTR_ADC12RST_Msk              (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)     /*!< 0x00000020 */

+#define RCC_AHB1RSTR_ADC12RST                  RCC_AHB1RSTR_ADC12RST_Msk

+#define RCC_AHB1RSTR_CRCRST_Pos                (9U)

+#define RCC_AHB1RSTR_CRCRST_Msk                (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)       /*!< 0x00000200 */

+#define RCC_AHB1RSTR_CRCRST                    RCC_AHB1RSTR_CRCRST_Msk

+#define RCC_AHB1RSTR_USB1OTGHSRST_Pos          (25U)

+#define RCC_AHB1RSTR_USB1OTGHSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */

+#define RCC_AHB1RSTR_USB1OTGHSRST              RCC_AHB1RSTR_USB1OTGHSRST_Msk

+

+/********************  Bit definition for RCC_AHB2RSTR register  ***************/

+#define RCC_AHB2RSTR_DCMI_PSSIRST_Pos          (0U)

+#define RCC_AHB2RSTR_DCMI_PSSIRST_Msk          (0x1UL << RCC_AHB2RSTR_DCMI_PSSIRST_Pos)  /*!< 0x00000001 */

+#define RCC_AHB2RSTR_DCMI_PSSIRST              RCC_AHB2RSTR_DCMI_PSSIRST_Msk

+#define RCC_AHB2RSTR_HSEMRST_Pos               (2U)

+#define RCC_AHB2RSTR_HSEMRST_Msk               (0x1UL << RCC_AHB2RSTR_HSEMRST_Pos)       /*!< 0x00000004 */

+#define RCC_AHB2RSTR_HSEMRST                   RCC_AHB2RSTR_HSEMRST_Msk

+#define RCC_AHB2RSTR_CRYPRST_Pos               (4U)

+#define RCC_AHB2RSTR_CRYPRST_Msk               (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos)       /*!< 0x00000010 */

+#define RCC_AHB2RSTR_CRYPRST                   RCC_AHB2RSTR_CRYPRST_Msk

+#define RCC_AHB2RSTR_HASHRST_Pos               (5U)

+#define RCC_AHB2RSTR_HASHRST_Msk               (0x1UL << RCC_AHB2RSTR_HASHRST_Pos)       /*!< 0x00000020 */

+#define RCC_AHB2RSTR_HASHRST                   RCC_AHB2RSTR_HASHRST_Msk

+#define RCC_AHB2RSTR_RNGRST_Pos                (6U)

+#define RCC_AHB2RSTR_RNGRST_Msk                (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)        /*!< 0x00000040 */

+#define RCC_AHB2RSTR_RNGRST                    RCC_AHB2RSTR_RNGRST_Msk

+#define RCC_AHB2RSTR_SDMMC2RST_Pos             (9U)

+#define RCC_AHB2RSTR_SDMMC2RST_Msk             (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)     /*!< 0x00000200 */

+#define RCC_AHB2RSTR_SDMMC2RST                 RCC_AHB2RSTR_SDMMC2RST_Msk

+#define RCC_AHB2RSTR_BDMA1RST_Pos              (11U)

+#define RCC_AHB2RSTR_BDMA1RST_Msk              (0x1UL << RCC_AHB2RSTR_BDMA1RST_Pos)      /*!< 0x00000200 */

+#define RCC_AHB2RSTR_BDMA1RST                  RCC_AHB2RSTR_BDMA1RST_Msk

+

+/* Legacy define */

+#define RCC_AHB2RSTR_DCMIRST_Pos               RCC_AHB2RSTR_DCMI_PSSIRST_Pos

+#define RCC_AHB2RSTR_DCMIRST_Msk               RCC_AHB2RSTR_DCMI_PSSIRST_Msk

+#define RCC_AHB2RSTR_DCMIRST                   RCC_AHB2RSTR_DCMI_PSSIRST

+/********************  Bit definition for RCC_AHB4RSTR register  ******************/

+#define RCC_AHB4RSTR_GPIOARST_Pos              (0U)

+#define RCC_AHB4RSTR_GPIOARST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB4RSTR_GPIOARST                  RCC_AHB4RSTR_GPIOARST_Msk

+#define RCC_AHB4RSTR_GPIOBRST_Pos              (1U)

+#define RCC_AHB4RSTR_GPIOBRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)      /*!< 0x00000002 */

+#define RCC_AHB4RSTR_GPIOBRST                  RCC_AHB4RSTR_GPIOBRST_Msk

+#define RCC_AHB4RSTR_GPIOCRST_Pos              (2U)

+#define RCC_AHB4RSTR_GPIOCRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)      /*!< 0x00000004 */

+#define RCC_AHB4RSTR_GPIOCRST                  RCC_AHB4RSTR_GPIOCRST_Msk

+#define RCC_AHB4RSTR_GPIODRST_Pos              (3U)

+#define RCC_AHB4RSTR_GPIODRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)      /*!< 0x00000008 */

+#define RCC_AHB4RSTR_GPIODRST                  RCC_AHB4RSTR_GPIODRST_Msk

+#define RCC_AHB4RSTR_GPIOERST_Pos              (4U)

+#define RCC_AHB4RSTR_GPIOERST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)      /*!< 0x00000010 */

+#define RCC_AHB4RSTR_GPIOERST                  RCC_AHB4RSTR_GPIOERST_Msk

+#define RCC_AHB4RSTR_GPIOFRST_Pos              (5U)

+#define RCC_AHB4RSTR_GPIOFRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)       /*!< 0x00000020 */

+#define RCC_AHB4RSTR_GPIOFRST                  RCC_AHB4RSTR_GPIOFRST_Msk

+#define RCC_AHB4RSTR_GPIOGRST_Pos              (6U)

+#define RCC_AHB4RSTR_GPIOGRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)       /*!< 0x00000040 */

+#define RCC_AHB4RSTR_GPIOGRST                  RCC_AHB4RSTR_GPIOGRST_Msk

+#define RCC_AHB4RSTR_GPIOHRST_Pos              (7U)

+#define RCC_AHB4RSTR_GPIOHRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)       /*!< 0x00000080 */

+#define RCC_AHB4RSTR_GPIOHRST                  RCC_AHB4RSTR_GPIOHRST_Msk

+#define RCC_AHB4RSTR_GPIOIRST_Pos              (8U)

+#define RCC_AHB4RSTR_GPIOIRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos)       /*!< 0x00000100 */

+#define RCC_AHB4RSTR_GPIOIRST                  RCC_AHB4RSTR_GPIOIRST_Msk

+#define RCC_AHB4RSTR_GPIOJRST_Pos              (9U)

+#define RCC_AHB4RSTR_GPIOJRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos)       /*!< 0x00000200 */

+#define RCC_AHB4RSTR_GPIOJRST                  RCC_AHB4RSTR_GPIOJRST_Msk

+#define RCC_AHB4RSTR_GPIOKRST_Pos              (10U)

+#define RCC_AHB4RSTR_GPIOKRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos)       /*!< 0x00000400 */

+#define RCC_AHB4RSTR_GPIOKRST                  RCC_AHB4RSTR_GPIOKRST_Msk

+#define RCC_AHB4RSTR_BDMA2RST_Pos              (21U)

+#define RCC_AHB4RSTR_BDMA2RST_Msk              (0x1UL << RCC_AHB4RSTR_BDMA2RST_Pos)       /*!< 0x00200000 */

+#define RCC_AHB4RSTR_BDMA2RST                   RCC_AHB4RSTR_BDMA2RST_Msk

+

+

+/********************  Bit definition for RCC_APB3RSTR register  ******************/

+#define RCC_APB3RSTR_LTDCRST_Pos               (3U)

+#define RCC_APB3RSTR_LTDCRST_Msk               (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */

+#define RCC_APB3RSTR_LTDCRST                   RCC_APB3RSTR_LTDCRST_Msk

+

+/********************  Bit definition for RCC_APB1LRSTR register  ******************/

+

+#define RCC_APB1LRSTR_TIM2RST_Pos              (0U)

+#define RCC_APB1LRSTR_TIM2RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */

+#define RCC_APB1LRSTR_TIM2RST                  RCC_APB1LRSTR_TIM2RST_Msk

+#define RCC_APB1LRSTR_TIM3RST_Pos              (1U)

+#define RCC_APB1LRSTR_TIM3RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */

+#define RCC_APB1LRSTR_TIM3RST                  RCC_APB1LRSTR_TIM3RST_Msk

+#define RCC_APB1LRSTR_TIM4RST_Pos              (2U)

+#define RCC_APB1LRSTR_TIM4RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */

+#define RCC_APB1LRSTR_TIM4RST                  RCC_APB1LRSTR_TIM4RST_Msk

+#define RCC_APB1LRSTR_TIM5RST_Pos              (3U)

+#define RCC_APB1LRSTR_TIM5RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */

+#define RCC_APB1LRSTR_TIM5RST                  RCC_APB1LRSTR_TIM5RST_Msk

+#define RCC_APB1LRSTR_TIM6RST_Pos              (4U)

+#define RCC_APB1LRSTR_TIM6RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */

+#define RCC_APB1LRSTR_TIM6RST                  RCC_APB1LRSTR_TIM6RST_Msk

+#define RCC_APB1LRSTR_TIM7RST_Pos              (5U)

+#define RCC_APB1LRSTR_TIM7RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */

+#define RCC_APB1LRSTR_TIM7RST                  RCC_APB1LRSTR_TIM7RST_Msk

+#define RCC_APB1LRSTR_TIM12RST_Pos             (6U)

+#define RCC_APB1LRSTR_TIM12RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */

+#define RCC_APB1LRSTR_TIM12RST                 RCC_APB1LRSTR_TIM12RST_Msk

+#define RCC_APB1LRSTR_TIM13RST_Pos             (7U)

+#define RCC_APB1LRSTR_TIM13RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */

+#define RCC_APB1LRSTR_TIM13RST                 RCC_APB1LRSTR_TIM13RST_Msk

+#define RCC_APB1LRSTR_TIM14RST_Pos             (8U)

+#define RCC_APB1LRSTR_TIM14RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */

+#define RCC_APB1LRSTR_TIM14RST                 RCC_APB1LRSTR_TIM14RST_Msk

+#define RCC_APB1LRSTR_LPTIM1RST_Pos            (9U)

+#define RCC_APB1LRSTR_LPTIM1RST_Msk            (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */

+#define RCC_APB1LRSTR_LPTIM1RST                RCC_APB1LRSTR_LPTIM1RST_Msk

+#define RCC_APB1LRSTR_SPI2RST_Pos              (14U)

+#define RCC_APB1LRSTR_SPI2RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */

+#define RCC_APB1LRSTR_SPI2RST                  RCC_APB1LRSTR_SPI2RST_Msk

+#define RCC_APB1LRSTR_SPI3RST_Pos              (15U)

+#define RCC_APB1LRSTR_SPI3RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */

+#define RCC_APB1LRSTR_SPI3RST                  RCC_APB1LRSTR_SPI3RST_Msk

+#define RCC_APB1LRSTR_SPDIFRXRST_Pos           (16U)

+#define RCC_APB1LRSTR_SPDIFRXRST_Msk           (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */

+#define RCC_APB1LRSTR_SPDIFRXRST               RCC_APB1LRSTR_SPDIFRXRST_Msk

+#define RCC_APB1LRSTR_USART2RST_Pos            (17U)

+#define RCC_APB1LRSTR_USART2RST_Msk            (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */

+#define RCC_APB1LRSTR_USART2RST                RCC_APB1LRSTR_USART2RST_Msk

+#define RCC_APB1LRSTR_USART3RST_Pos            (18U)

+#define RCC_APB1LRSTR_USART3RST_Msk            (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */

+#define RCC_APB1LRSTR_USART3RST                RCC_APB1LRSTR_USART3RST_Msk

+#define RCC_APB1LRSTR_UART4RST_Pos             (19U)

+#define RCC_APB1LRSTR_UART4RST_Msk             (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */

+#define RCC_APB1LRSTR_UART4RST                 RCC_APB1LRSTR_UART4RST_Msk

+#define RCC_APB1LRSTR_UART5RST_Pos             (20U)

+#define RCC_APB1LRSTR_UART5RST_Msk             (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */

+#define RCC_APB1LRSTR_UART5RST                 RCC_APB1LRSTR_UART5RST_Msk

+#define RCC_APB1LRSTR_I2C1RST_Pos              (21U)

+#define RCC_APB1LRSTR_I2C1RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */

+#define RCC_APB1LRSTR_I2C1RST                  RCC_APB1LRSTR_I2C1RST_Msk

+#define RCC_APB1LRSTR_I2C2RST_Pos              (22U)

+#define RCC_APB1LRSTR_I2C2RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */

+#define RCC_APB1LRSTR_I2C2RST                  RCC_APB1LRSTR_I2C2RST_Msk

+#define RCC_APB1LRSTR_I2C3RST_Pos              (23U)

+#define RCC_APB1LRSTR_I2C3RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */

+#define RCC_APB1LRSTR_I2C3RST                  RCC_APB1LRSTR_I2C3RST_Msk

+#define RCC_APB1LRSTR_CECRST_Pos               (27U)

+#define RCC_APB1LRSTR_CECRST_Msk               (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */

+#define RCC_APB1LRSTR_CECRST                   RCC_APB1LRSTR_CECRST_Msk

+#define RCC_APB1LRSTR_DAC12RST_Pos             (29U)

+#define RCC_APB1LRSTR_DAC12RST_Msk             (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */

+#define RCC_APB1LRSTR_DAC12RST                 RCC_APB1LRSTR_DAC12RST_Msk

+#define RCC_APB1LRSTR_UART7RST_Pos             (30U)

+#define RCC_APB1LRSTR_UART7RST_Msk             (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */

+#define RCC_APB1LRSTR_UART7RST                 RCC_APB1LRSTR_UART7RST_Msk

+#define RCC_APB1LRSTR_UART8RST_Pos             (31U)

+#define RCC_APB1LRSTR_UART8RST_Msk             (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */

+#define RCC_APB1LRSTR_UART8RST                 RCC_APB1LRSTR_UART8RST_Msk

+

+/* Legacy define */

+#define RCC_APB1LRSTR_HDMICECRST_Pos           RCC_APB1LRSTR_CECRST_Pos

+#define RCC_APB1LRSTR_HDMICECRST_Msk           RCC_APB1LRSTR_CECRST_Msk

+#define RCC_APB1LRSTR_HDMICECRST               RCC_APB1LRSTR_CECRST

+/********************  Bit definition for RCC_APB1HRSTR register  ******************/

+#define RCC_APB1HRSTR_CRSRST_Pos               (1U)

+#define RCC_APB1HRSTR_CRSRST_Msk               (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */

+#define RCC_APB1HRSTR_CRSRST                   RCC_APB1HRSTR_CRSRST_Msk

+#define RCC_APB1HRSTR_SWPMIRST_Pos             (2U)

+#define RCC_APB1HRSTR_SWPMIRST_Msk             (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */

+#define RCC_APB1HRSTR_SWPMIRST                 RCC_APB1HRSTR_SWPMIRST_Msk

+#define RCC_APB1HRSTR_OPAMPRST_Pos             (4U)

+#define RCC_APB1HRSTR_OPAMPRST_Msk             (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */

+#define RCC_APB1HRSTR_OPAMPRST                 RCC_APB1HRSTR_OPAMPRST_Msk

+#define RCC_APB1HRSTR_MDIOSRST_Pos             (5U)

+#define RCC_APB1HRSTR_MDIOSRST_Msk             (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */

+#define RCC_APB1HRSTR_MDIOSRST                 RCC_APB1HRSTR_MDIOSRST_Msk

+#define RCC_APB1HRSTR_FDCANRST_Pos             (8U)

+#define RCC_APB1HRSTR_FDCANRST_Msk             (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */

+#define RCC_APB1HRSTR_FDCANRST                 RCC_APB1HRSTR_FDCANRST_Msk

+

+/********************  Bit definition for RCC_APB2RSTR register  ******************/

+#define RCC_APB2RSTR_TIM1RST_Pos               (0U)

+#define RCC_APB2RSTR_TIM1RST_Msk               (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */

+#define RCC_APB2RSTR_TIM1RST                   RCC_APB2RSTR_TIM1RST_Msk

+#define RCC_APB2RSTR_TIM8RST_Pos               (1U)

+#define RCC_APB2RSTR_TIM8RST_Msk               (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */

+#define RCC_APB2RSTR_TIM8RST                   RCC_APB2RSTR_TIM8RST_Msk

+#define RCC_APB2RSTR_USART1RST_Pos             (4U)

+#define RCC_APB2RSTR_USART1RST_Msk             (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */

+#define RCC_APB2RSTR_USART1RST                 RCC_APB2RSTR_USART1RST_Msk

+#define RCC_APB2RSTR_USART6RST_Pos             (5U)

+#define RCC_APB2RSTR_USART6RST_Msk             (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */

+#define RCC_APB2RSTR_USART6RST                 RCC_APB2RSTR_USART6RST_Msk

+#define RCC_APB2RSTR_UART9RST_Pos              (6U)

+#define RCC_APB2RSTR_UART9RST_Msk              (0x1UL << RCC_APB2RSTR_UART9RST_Pos) /*!< 0x00000040 */

+#define RCC_APB2RSTR_UART9RST                  RCC_APB2RSTR_UART9RST_Msk

+#define RCC_APB2RSTR_USART10RST_Pos            (7U)

+#define RCC_APB2RSTR_USART10RST_Msk            (0x1UL << RCC_APB2RSTR_USART10RST_Pos) /*!< 0x00000080 */

+#define RCC_APB2RSTR_USART10RST                RCC_APB2RSTR_USART10RST_Msk

+#define RCC_APB2RSTR_SPI1RST_Pos               (12U)

+#define RCC_APB2RSTR_SPI1RST_Msk               (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */

+#define RCC_APB2RSTR_SPI1RST                   RCC_APB2RSTR_SPI1RST_Msk

+#define RCC_APB2RSTR_SPI4RST_Pos               (13U)

+#define RCC_APB2RSTR_SPI4RST_Msk               (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */

+#define RCC_APB2RSTR_SPI4RST                   RCC_APB2RSTR_SPI4RST_Msk

+#define RCC_APB2RSTR_TIM15RST_Pos              (16U)

+#define RCC_APB2RSTR_TIM15RST_Msk              (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */

+#define RCC_APB2RSTR_TIM15RST                  RCC_APB2RSTR_TIM15RST_Msk

+#define RCC_APB2RSTR_TIM16RST_Pos              (17U)

+#define RCC_APB2RSTR_TIM16RST_Msk              (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */

+#define RCC_APB2RSTR_TIM16RST                  RCC_APB2RSTR_TIM16RST_Msk

+#define RCC_APB2RSTR_TIM17RST_Pos              (18U)

+#define RCC_APB2RSTR_TIM17RST_Msk              (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */

+#define RCC_APB2RSTR_TIM17RST                  RCC_APB2RSTR_TIM17RST_Msk

+#define RCC_APB2RSTR_SPI5RST_Pos               (20U)

+#define RCC_APB2RSTR_SPI5RST_Msk               (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */

+#define RCC_APB2RSTR_SPI5RST                   RCC_APB2RSTR_SPI5RST_Msk

+#define RCC_APB2RSTR_SAI1RST_Pos               (22U)

+#define RCC_APB2RSTR_SAI1RST_Msk               (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */

+#define RCC_APB2RSTR_SAI1RST                   RCC_APB2RSTR_SAI1RST_Msk

+#define RCC_APB2RSTR_SAI2RST_Pos               (23U)

+#define RCC_APB2RSTR_SAI2RST_Msk               (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */

+#define RCC_APB2RSTR_SAI2RST                   RCC_APB2RSTR_SAI2RST_Msk

+#define RCC_APB2RSTR_DFSDM1RST_Pos             (30U)

+#define RCC_APB2RSTR_DFSDM1RST_Msk             (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */

+#define RCC_APB2RSTR_DFSDM1RST                 RCC_APB2RSTR_DFSDM1RST_Msk

+

+/********************  Bit definition for RCC_APB4RSTR register  ******************/

+#define RCC_APB4RSTR_SYSCFGRST_Pos             (1U)

+#define RCC_APB4RSTR_SYSCFGRST_Msk             (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */

+#define RCC_APB4RSTR_SYSCFGRST                 RCC_APB4RSTR_SYSCFGRST_Msk

+#define RCC_APB4RSTR_LPUART1RST_Pos            (3U)

+#define RCC_APB4RSTR_LPUART1RST_Msk            (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */

+#define RCC_APB4RSTR_LPUART1RST                RCC_APB4RSTR_LPUART1RST_Msk

+#define RCC_APB4RSTR_SPI6RST_Pos               (5U)

+#define RCC_APB4RSTR_SPI6RST_Msk               (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */

+#define RCC_APB4RSTR_SPI6RST                   RCC_APB4RSTR_SPI6RST_Msk

+#define RCC_APB4RSTR_I2C4RST_Pos               (7U)

+#define RCC_APB4RSTR_I2C4RST_Msk               (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */

+#define RCC_APB4RSTR_I2C4RST                   RCC_APB4RSTR_I2C4RST_Msk

+#define RCC_APB4RSTR_LPTIM2RST_Pos             (9U)

+#define RCC_APB4RSTR_LPTIM2RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */

+#define RCC_APB4RSTR_LPTIM2RST                 RCC_APB4RSTR_LPTIM2RST_Msk

+#define RCC_APB4RSTR_LPTIM3RST_Pos             (10U)

+#define RCC_APB4RSTR_LPTIM3RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */

+#define RCC_APB4RSTR_LPTIM3RST                 RCC_APB4RSTR_LPTIM3RST_Msk

+#define RCC_APB4RSTR_DAC2RST_Pos               (13U)

+#define RCC_APB4RSTR_DAC2RST_Msk               (0x1UL << RCC_APB4RSTR_DAC2RST_Pos) /*!< 0x00001000 */

+#define RCC_APB4RSTR_DAC2RST                    RCC_APB4RSTR_DAC2RST_Msk

+#define RCC_APB4RSTR_COMP12RST_Pos             (14U)

+#define RCC_APB4RSTR_COMP12RST_Msk             (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */

+#define RCC_APB4RSTR_COMP12RST                 RCC_APB4RSTR_COMP12RST_Msk

+#define RCC_APB4RSTR_VREFRST_Pos               (15U)

+#define RCC_APB4RSTR_VREFRST_Msk               (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */

+#define RCC_APB4RSTR_VREFRST                   RCC_APB4RSTR_VREFRST_Msk

+

+#define RCC_APB4RSTR_DTSRST_Pos                (26U)

+#define RCC_APB4RSTR_DTSRST_Msk                (0x1UL << RCC_APB4RSTR_DTSRST_Pos) /*!< 0x04000000 */

+#define RCC_APB4RSTR_DTSRST                    RCC_APB4RSTR_DTSRST_Msk

+#define RCC_APB4RSTR_DFSDM2RST_Pos             (27U)

+#define RCC_APB4RSTR_DFSDM2RST_Msk             (0x1UL << RCC_APB4RSTR_DFSDM2RST_Pos) /*!< 0x08000000 */

+#define RCC_APB4RSTR_DFSDM2RST                 RCC_APB4RSTR_DFSDM2RST_Msk

+

+

+/********************  Bit definition for RCC_SRDAMR register  ********************/

+#define RCC_SRDAMR_BDMA2AMEN_Pos               (0U)

+#define RCC_SRDAMR_BDMA2AMEN_Msk               (0x1UL << RCC_SRDAMR_BDMA2AMEN_Pos) /*!< 0x00000001 */

+#define RCC_SRDAMR_BDMA2AMEN                   RCC_SRDAMR_BDMA2AMEN_Msk

+#define RCC_SRDAMR_GPIOAMEN_Pos                (1U)

+#define RCC_SRDAMR_GPIOAMEN_Msk                (0x1UL << RCC_SRDAMR_GPIOAMEN_Pos) /*!< 0x00000001 */

+#define RCC_SRDAMR_GPIOAMEN                    RCC_SRDAMR_GPIOAMEN_Msk

+#define RCC_SRDAMR_LPUART1AMEN_Pos             (3U)

+#define RCC_SRDAMR_LPUART1AMEN_Msk             (0x1UL << RCC_SRDAMR_LPUART1AMEN_Pos) /*!< 0x00000008 */

+#define RCC_SRDAMR_LPUART1AMEN                 RCC_SRDAMR_LPUART1AMEN_Msk

+#define RCC_SRDAMR_SPI6AMEN_Pos                (5U)

+#define RCC_SRDAMR_SPI6AMEN_Msk                (0x1UL << RCC_SRDAMR_SPI6AMEN_Pos) /*!< 0x00000020 */

+#define RCC_SRDAMR_SPI6AMEN                    RCC_SRDAMR_SPI6AMEN_Msk

+#define RCC_SRDAMR_I2C4AMEN_Pos                (7U)

+#define RCC_SRDAMR_I2C4AMEN_Msk                (0x1UL << RCC_SRDAMR_I2C4AMEN_Pos) /*!< 0x00000080 */

+#define RCC_SRDAMR_I2C4AMEN                    RCC_SRDAMR_I2C4AMEN_Msk

+#define RCC_SRDAMR_LPTIM2AMEN_Pos              (9U)

+#define RCC_SRDAMR_LPTIM2AMEN_Msk              (0x1UL << RCC_SRDAMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */

+#define RCC_SRDAMR_LPTIM2AMEN                  RCC_SRDAMR_LPTIM2AMEN_Msk

+#define RCC_SRDAMR_LPTIM3AMEN_Pos              (10U)

+#define RCC_SRDAMR_LPTIM3AMEN_Msk              (0x1UL << RCC_SRDAMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */

+#define RCC_SRDAMR_LPTIM3AMEN                  RCC_SRDAMR_LPTIM3AMEN_Msk

+#define RCC_SRDAMR_DAC2AMEN_Pos                (13U)

+#define RCC_SRDAMR_DAC2AMEN_Msk                (0x1UL << RCC_SRDAMR_DAC2AMEN_Pos) /*!< 0x00004000 */

+#define RCC_SRDAMR_DAC2AMEN                    RCC_SRDAMR_DAC2AMEN_Msk

+#define RCC_SRDAMR_COMP12AMEN_Pos              (14U)

+#define RCC_SRDAMR_COMP12AMEN_Msk              (0x1UL << RCC_SRDAMR_COMP12AMEN_Pos) /*!< 0x00004000 */

+#define RCC_SRDAMR_COMP12AMEN                  RCC_SRDAMR_COMP12AMEN_Msk

+#define RCC_SRDAMR_VREFAMEN_Pos                (15U)

+#define RCC_SRDAMR_VREFAMEN_Msk                (0x1UL << RCC_SRDAMR_VREFAMEN_Pos) /*!< 0x00008000 */

+#define RCC_SRDAMR_VREFAMEN                     RCC_SRDAMR_VREFAMEN_Msk

+#define RCC_SRDAMR_RTCAMEN_Pos                 (16U)

+#define RCC_SRDAMR_RTCAMEN_Msk                 (0x1UL << RCC_SRDAMR_RTCAMEN_Pos) /*!< 0x00010000 */

+#define RCC_SRDAMR_RTCAMEN                     RCC_SRDAMR_RTCAMEN_Msk

+#define RCC_SRDAMR_DTSAMEN_Pos                 (26U)

+#define RCC_SRDAMR_DTSAMEN_Msk                 (0x1UL << RCC_SRDAMR_DTSAMEN_Pos) /*!< 0x04000000 */

+#define RCC_SRDAMR_DTSAMEN                     RCC_SRDAMR_DTSAMEN_Msk

+#define RCC_SRDAMR_DFSDM2AMEN_Pos              (27U)

+#define RCC_SRDAMR_DFSDM2AMEN_Msk              (0x1UL << RCC_SRDAMR_DFSDM2AMEN_Pos) /*!< 0x20000000 */

+#define RCC_SRDAMR_DFSDM2AMEN                   RCC_SRDAMR_DFSDM2AMEN_Msk

+#define RCC_SRDAMR_BKPRAMAMEN_Pos              (28U)

+#define RCC_SRDAMR_BKPRAMAMEN_Msk              (0x1UL << RCC_SRDAMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */

+#define RCC_SRDAMR_BKPRAMAMEN                  RCC_SRDAMR_BKPRAMAMEN_Msk

+#define RCC_SRDAMR_SRDSRAMAMEN_Pos             (29U)

+#define RCC_SRDAMR_SRDSRAMAMEN_Msk             (0x1UL << RCC_SRDAMR_SRDSRAMAMEN_Pos) /*!< 0x20000000 */

+#define RCC_SRDAMR_SRDSRAMAMEN                  RCC_SRDAMR_SRDSRAMAMEN_Msk

+/********************  Bit definition for RCC_CKGAENR register  ********************/

+#define RCC_CKGAENR_AXICKG_Pos                 (0U)

+#define RCC_CKGAENR_AXICKG_Msk                 (0x1UL << RCC_CKGAENR_AXICKG_Pos) /*!< 0x00000001 */

+#define RCC_CKGAENR_AXICKG                      RCC_CKGAENR_AXICKG_Msk

+#define RCC_CKGAENR_AHBCKG_Pos                 (1U)

+#define RCC_CKGAENR_AHBCKG_Msk                 (0x1UL << RCC_CKGAENR_AHBCKG_Pos) /*!< 0x00000002 */

+#define RCC_CKGAENR_AHBCKG                     RCC_CKGAENR_AHBCKG_Msk

+#define RCC_CKGAENR_CPUCKG_Pos                 (2U)

+#define RCC_CKGAENR_CPUCKG_Msk                 (0x1UL << RCC_CKGAENR_CPUCKG_Pos) /*!< 0x00000004 */

+#define RCC_CKGAENR_CPUCKG                     RCC_CKGAENR_CPUCKG_Msk

+#define RCC_CKGAENR_SDMMCCKG_Pos               (3U)

+#define RCC_CKGAENR_SDMMCCKG_Msk               (0x1UL << RCC_CKGAENR_SDMMCCKG_Pos) /*!< 0x00000008 */

+#define RCC_CKGAENR_SDMMCCKG                    RCC_CKGAENR_SDMMCCKG_Msk

+#define RCC_CKGAENR_MDMACKG_Pos                (4U)

+#define RCC_CKGAENR_MDMACKG_Msk                (0x1UL << RCC_CKGAENR_MDMACKG_Pos) /*!< 0x00000010 */

+#define RCC_CKGAENR_MDMACKG                    RCC_CKGAENR_MDMACKG_Msk

+#define RCC_CKGAENR_DMA2DCKG_Pos               (5U)

+#define RCC_CKGAENR_DMA2DCKG_Msk               (0x1UL << RCC_CKGAENR_DMA2DCKG_Pos) /*!< 0x00000020 */

+#define RCC_CKGAENR_DMA2DCKG                    RCC_CKGAENR_DMA2DCKG_Msk

+#define RCC_CKGAENR_LTDCCKG_Pos                (6U)

+#define RCC_CKGAENR_LTDCCKG_Msk                (0x1UL << RCC_CKGAENR_LTDCCKG_Pos) /*!< 0x00000040 */

+#define RCC_CKGAENR_LTDCCKG                    RCC_CKGAENR_LTDCCKG_Msk

+#define RCC_CKGAENR_GFXMMUMCKG_Pos             (7U)

+#define RCC_CKGAENR_GFXMMUMCKG_Msk             (0x1UL << RCC_CKGAENR_GFXMMUMCKG_Pos) /*!< 0x00000080 */

+#define RCC_CKGAENR_GFXMMUMCKG                 RCC_CKGAENR_GFXMMUMCKG_Msk

+#define RCC_CKGAENR_AHB12CKG_Pos               (8U)

+#define RCC_CKGAENR_AHB12CKG_Msk               (0x1UL << RCC_CKGAENR_AHB12CKG_Pos) /*!< 0x00000100 */

+#define RCC_CKGAENR_AHB12CKG                   RCC_CKGAENR_AHB12CKG_Msk

+#define RCC_CKGAENR_AHB34CKG_Pos               (9U)

+#define RCC_CKGAENR_AHB34CKG_Msk               (0x1UL << RCC_CKGAENR_AHB34CKG_Pos) /*!< 0x00000200 */

+#define RCC_CKGAENR_AHB34CKG                   RCC_CKGAENR_AHB34CKG_Msk

+#define RCC_CKGAENR_FLIFTCKG_Pos               (10U)

+#define RCC_CKGAENR_FLIFTCKG_Msk               (0x1UL << RCC_CKGAENR_FLIFTCKG_Pos) /*!< 0x00000400 */

+#define RCC_CKGAENR_FLIFTCKG                   RCC_CKGAENR_FLIFTCKG_Msk

+#define RCC_CKGAENR_OCTOSPI2CKG_Pos            (11U)

+#define RCC_CKGAENR_OCTOSPI2CKG_Msk            (0x1UL << RCC_CKGAENR_OCTOSPI2CKG_Pos) /*!< 0x00000800 */

+#define RCC_CKGAENR_OCTOSPI2CKG                RCC_CKGAENR_OCTOSPI2CKG_Msk

+#define RCC_CKGAENR_FMCCKG_Pos                 (12U)

+#define RCC_CKGAENR_FMCCKG_Msk                 (0x1UL << RCC_CKGAENR_FMCCKG_Pos) /*!< 0x00001000 */

+#define RCC_CKGAENR_FMCCKG                     RCC_CKGAENR_FMCCKG_Msk

+#define RCC_CKGAENR_OCTOSPI1CKG_Pos            (13U)

+#define RCC_CKGAENR_OCTOSPI1CKG_Msk            (0x1UL << RCC_CKGAENR_OCTOSPI1CKG_Pos) /*!< 0x00002000 */

+#define RCC_CKGAENR_OCTOSPI1CKG                RCC_CKGAENR_OCTOSPI1CKG_Msk

+#define RCC_CKGAENR_AXIRAM1CKG_Pos             (14U)

+#define RCC_CKGAENR_AXIRAM1CKG_Msk             (0x1UL << RCC_CKGAENR_AXIRAM1CKG_Pos) /*!< 0x00004000 */

+#define RCC_CKGAENR_AXIRAM1CKG                 RCC_CKGAENR_AXIRAM1CKG_Msk

+#define RCC_CKGAENR_AXIRAM2CKG_Pos             (15U)

+#define RCC_CKGAENR_AXIRAM2CKG_Msk             (0x1UL << RCC_CKGAENR_AXIRAM2CKG_Pos) /*!< 0x00008000 */

+#define RCC_CKGAENR_AXIRAM2CKG                 RCC_CKGAENR_AXIRAM2CKG_Msk

+#define RCC_CKGAENR_AXIRAM3CKG_Pos             (16U)

+#define RCC_CKGAENR_AXIRAM3CKG_Msk             (0x1UL << RCC_CKGAENR_AXIRAM3CKG_Pos) /*!< 0x00010000 */

+#define RCC_CKGAENR_AXIRAM3CKG                 RCC_CKGAENR_AXIRAM3CKG_Msk

+#define RCC_CKGAENR_GFXMMUSCKG_Pos             (17U)

+#define RCC_CKGAENR_GFXMMUSCKG_Msk             (0x1UL << RCC_CKGAENR_GFXMMUSCKG_Pos) /*!< 0x00020000 */

+#define RCC_CKGAENR_GFXMMUSCKG                 RCC_CKGAENR_GFXMMUSCKG_Msk

+#define RCC_CKGAENR_ECCRAMCKG_Pos              (29U)

+#define RCC_CKGAENR_ECCRAMCKG_Msk              (0x1UL << RCC_CKGAENR_ECCRAMCKG_Pos) /*!< 0x20000000 */

+#define RCC_CKGAENR_ECCRAMCKG                  RCC_CKGAENR_ECCRAMCKG_Msk

+#define RCC_CKGAENR_EXTICKG_Pos                (30U)

+#define RCC_CKGAENR_EXTICKG_Msk                (0x1UL << RCC_CKGAENR_EXTICKG_Pos) /*!< 0x40000000 */

+#define RCC_CKGAENR_EXTICKG                    RCC_CKGAENR_EXTICKG_Msk

+#define RCC_CKGAENR_JTAGCKG_Pos                (31U)

+#define RCC_CKGAENR_JTAGCKG_Msk                (0x1UL << RCC_CKGAENR_JTAGCKG_Pos) /*!< 0x80000008 */

+#define RCC_CKGAENR_JTAGCKG                    RCC_CKGAENR_JTAGCKG_Msk

+/********************  Bit definition for RCC_AHB3LPENR register  **************/

+#define RCC_AHB3LPENR_MDMALPEN_Pos             (0U)

+#define RCC_AHB3LPENR_MDMALPEN_Msk             (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos)         /*!< 0x00000001 */

+#define RCC_AHB3LPENR_MDMALPEN                 RCC_AHB3LPENR_MDMALPEN_Msk

+#define RCC_AHB3LPENR_DMA2DLPEN_Pos            (4U)

+#define RCC_AHB3LPENR_DMA2DLPEN_Msk            (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos)        /*!< 0x00000010 */

+#define RCC_AHB3LPENR_DMA2DLPEN                RCC_AHB3LPENR_DMA2DLPEN_Msk

+#define RCC_AHB3LPENR_JPGDECLPEN_Pos           (5U)

+#define RCC_AHB3LPENR_JPGDECLPEN_Msk           (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos)       /*!< 0x00000020 */

+#define RCC_AHB3LPENR_JPGDECLPEN               RCC_AHB3LPENR_JPGDECLPEN_Msk

+#define RCC_AHB3LPENR_FLASHLPEN_Pos            (8U)

+#define RCC_AHB3LPENR_FLASHLPEN_Msk            (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos)        /*!< 0x00000100 */

+#define RCC_AHB3LPENR_FLASHLPEN                RCC_AHB3LPENR_FLASHLPEN_Msk

+#define RCC_AHB3LPENR_FMCLPEN_Pos              (12U)

+#define RCC_AHB3LPENR_FMCLPEN_Msk              (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)          /*!< 0x00001000 */

+#define RCC_AHB3LPENR_FMCLPEN                  RCC_AHB3LPENR_FMCLPEN_Msk

+#define RCC_AHB3LPENR_OSPI1LPEN_Pos            (14U)

+#define RCC_AHB3LPENR_OSPI1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_OSPI1LPEN_Pos)        /*!< 0x00004000 */

+#define RCC_AHB3LPENR_OSPI1LPEN                RCC_AHB3LPENR_OSPI1LPEN_Msk

+#define RCC_AHB3LPENR_SDMMC1LPEN_Pos           (16U)

+#define RCC_AHB3LPENR_SDMMC1LPEN_Msk           (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos)       /*!< 0x00010000 */

+#define RCC_AHB3LPENR_SDMMC1LPEN               RCC_AHB3LPENR_SDMMC1LPEN_Msk

+#define RCC_AHB3LPENR_OSPI2LPEN_Pos            (19U)

+#define RCC_AHB3LPENR_OSPI2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_OSPI2LPEN_Pos)        /*!< 0x00080000 */

+#define RCC_AHB3LPENR_OSPI2LPEN                RCC_AHB3LPENR_OSPI2LPEN_Msk

+#define RCC_AHB3LPENR_IOMNGRLPEN_Pos           (21U)

+#define RCC_AHB3LPENR_IOMNGRLPEN_Msk           (0x1UL << RCC_AHB3LPENR_IOMNGRLPEN_Pos)       /*!< 0x00200000 */

+#define RCC_AHB3LPENR_IOMNGRLPEN               RCC_AHB3LPENR_IOMNGRLPEN_Msk

+#define RCC_AHB3LPENR_OTFDEC1LPEN_Pos          (22U)

+#define RCC_AHB3LPENR_OTFDEC1LPEN_Msk          (0x1UL << RCC_AHB3LPENR_OTFDEC1LPEN_Pos)      /*!< 0x00400000 */

+#define RCC_AHB3LPENR_OTFDEC1LPEN              RCC_AHB3LPENR_OTFDEC1LPEN_Msk

+#define RCC_AHB3LPENR_OTFDEC2LPEN_Pos          (23U)

+#define RCC_AHB3LPENR_OTFDEC2LPEN_Msk          (0x1UL << RCC_AHB3LPENR_OTFDEC2LPEN_Pos)      /*!< 0x00800000 */

+#define RCC_AHB3LPENR_OTFDEC2LPEN              RCC_AHB3LPENR_OTFDEC2LPEN_Msk

+#define RCC_AHB3LPENR_GFXMMULPEN_Pos           (24U)

+#define RCC_AHB3LPENR_GFXMMULPEN_Msk           (0x1UL << RCC_AHB3LPENR_GFXMMULPEN_Pos)       /*!< 0x01000000 */

+#define RCC_AHB3LPENR_GFXMMULPEN               RCC_AHB3LPENR_GFXMMULPEN_Msk

+#define RCC_AHB3LPENR_AXISRAM2LPEN_Pos         (26U)

+#define RCC_AHB3LPENR_AXISRAM2LPEN_Msk         (0x1UL << RCC_AHB3LPENR_AXISRAM2LPEN_Pos)     /*!< 0x02000000 */

+#define RCC_AHB3LPENR_AXISRAM2LPEN             RCC_AHB3LPENR_AXISRAM2LPEN_Msk

+#define RCC_AHB3LPENR_AXISRAM3LPEN_Pos         (27U)

+#define RCC_AHB3LPENR_AXISRAM3LPEN_Msk         (0x1UL << RCC_AHB3LPENR_AXISRAM3LPEN_Pos)     /*!< 0x04000000 */

+#define RCC_AHB3LPENR_AXISRAM3LPEN             RCC_AHB3LPENR_AXISRAM3LPEN_Msk

+#define RCC_AHB3LPENR_DTCM1LPEN_Pos            (28U)

+#define RCC_AHB3LPENR_DTCM1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos)        /*!< 0x10000000 */

+#define RCC_AHB3LPENR_DTCM1LPEN                RCC_AHB3LPENR_DTCM1LPEN_Msk

+#define RCC_AHB3LPENR_DTCM2LPEN_Pos            (29U)

+#define RCC_AHB3LPENR_DTCM2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos)        /*!< 0x20000000 */

+#define RCC_AHB3LPENR_DTCM2LPEN                RCC_AHB3LPENR_DTCM2LPEN_Msk

+#define RCC_AHB3LPENR_ITCMLPEN_Pos             (30U)

+#define RCC_AHB3LPENR_ITCMLPEN_Msk             (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos)         /*!< 0x40000000 */

+#define RCC_AHB3LPENR_ITCMLPEN                 RCC_AHB3LPENR_ITCMLPEN_Msk

+#define RCC_AHB3LPENR_AXISRAM1LPEN_Pos         (31U)

+#define RCC_AHB3LPENR_AXISRAM1LPEN_Msk         (0x1UL << RCC_AHB3LPENR_AXISRAM1LPEN_Pos)      /*!< 0x80000000 */

+#define RCC_AHB3LPENR_AXISRAM1LPEN             RCC_AHB3LPENR_AXISRAM1LPEN_Msk

+

+

+/* Legacy define */

+#define RCC_AHB3LPENR_AXISRAMLPEN_Pos          RCC_AHB3LPENR_AXISRAM1LPEN_Pos

+#define RCC_AHB3LPENR_AXISRAMLPEN_Msk          RCC_AHB3LPENR_AXISRAM1LPEN_Msk

+#define RCC_AHB3LPENR_AXISRAMLPEN              RCC_AHB3LPENR_AXISRAM1LPEN

+/********************  Bit definition for RCC_AHB1LPENR register  ***************/

+#define RCC_AHB1LPENR_DMA1LPEN_Pos             (0U)

+#define RCC_AHB1LPENR_DMA1LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB1LPENR_DMA1LPEN                 RCC_AHB1LPENR_DMA1LPEN_Msk

+#define RCC_AHB1LPENR_DMA2LPEN_Pos             (1U)

+#define RCC_AHB1LPENR_DMA2LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */

+#define RCC_AHB1LPENR_DMA2LPEN                 RCC_AHB1LPENR_DMA2LPEN_Msk

+#define RCC_AHB1LPENR_ADC12LPEN_Pos            (5U)

+#define RCC_AHB1LPENR_ADC12LPEN_Msk            (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB1LPENR_ADC12LPEN                RCC_AHB1LPENR_ADC12LPEN_Msk

+#define RCC_AHB1LPENR_CRCLPEN_Pos              (9U)

+#define RCC_AHB1LPENR_CRCLPEN_Msk              (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00008000 */

+#define RCC_AHB1LPENR_CRCLPEN                   RCC_AHB1LPENR_CRCLPEN_Msk

+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos        (25U)

+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */

+#define RCC_AHB1LPENR_USB1OTGHSLPEN            RCC_AHB1LPENR_USB1OTGHSLPEN_Msk

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos    (26U)

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN        RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk

+

+/********************  Bit definition for RCC_AHB2LPENR register  ***************/

+#define RCC_AHB2LPENR_DCMI_PSSILPEN_Pos        (0U)

+#define RCC_AHB2LPENR_DCMI_PSSILPEN_Msk        (0x1UL << RCC_AHB2LPENR_DCMI_PSSILPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB2LPENR_DCMI_PSSILPEN            RCC_AHB2LPENR_DCMI_PSSILPEN_Msk

+#define RCC_AHB2LPENR_CRYPLPEN_Pos             (4U)

+#define RCC_AHB2LPENR_CRYPLPEN_Msk             (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */

+#define RCC_AHB2LPENR_CRYPLPEN                 RCC_AHB2LPENR_CRYPLPEN_Msk

+#define RCC_AHB2LPENR_HASHLPEN_Pos             (5U)

+#define RCC_AHB2LPENR_HASHLPEN_Msk             (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB2LPENR_HASHLPEN                 RCC_AHB2LPENR_HASHLPEN_Msk

+#define RCC_AHB2LPENR_RNGLPEN_Pos              (6U)

+#define RCC_AHB2LPENR_RNGLPEN_Msk              (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */

+#define RCC_AHB2LPENR_RNGLPEN                  RCC_AHB2LPENR_RNGLPEN_Msk

+#define RCC_AHB2LPENR_SDMMC2LPEN_Pos           (9U)

+#define RCC_AHB2LPENR_SDMMC2LPEN_Msk           (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */

+#define RCC_AHB2LPENR_SDMMC2LPEN               RCC_AHB2LPENR_SDMMC2LPEN_Msk

+#define RCC_AHB2LPENR_BDMA1LPEN_Pos            (11U)

+#define RCC_AHB2LPENR_BDMA1LPEN_Msk            (0x1UL << RCC_AHB2LPENR_BDMA1LPEN_Pos)   /*!< 0x00000800 */

+#define RCC_AHB2LPENR_BDMA1LPEN                RCC_AHB2LPENR_BDMA1LPEN_Msk

+#define RCC_AHB2LPENR_AHBSRAM1LPEN_Pos         (29U)

+#define RCC_AHB2LPENR_AHBSRAM1LPEN_Msk         (0x1UL << RCC_AHB2LPENR_AHBSRAM1LPEN_Pos) /*!< 0x20000000 */

+#define RCC_AHB2LPENR_AHBSRAM1LPEN             RCC_AHB2LPENR_AHBSRAM1LPEN_Msk

+#define RCC_AHB2LPENR_AHBSRAM2LPEN_Pos         (30U)

+#define RCC_AHB2LPENR_AHBSRAM2LPEN_Msk         (0x1UL << RCC_AHB2LPENR_AHBSRAM2LPEN_Pos) /*!< 0x40000000 */

+#define RCC_AHB2LPENR_AHBSRAM2LPEN             RCC_AHB2LPENR_AHBSRAM2LPEN_Msk

+

+/* Legacy define */

+#define RCC_AHB2LPENR_DFSDMDMALPEN_Pos         RCC_AHB2LPENR_BDMA1LPEN_Pos

+#define RCC_AHB2LPENR_DFSDMDMALPEN_Msk         RCC_AHB2LPENR_BDMA1LPEN_Msk

+#define RCC_AHB2LPENR_DFSDMDMALPEN             RCC_AHB2LPENR_BDMA1LPEN

+#define RCC_AHB2LPENR_DCMILPEN_Pos             RCC_AHB2LPENR_DCMI_PSSILPEN_Pos

+#define RCC_AHB2LPENR_DCMILPEN_Msk             RCC_AHB2LPENR_DCMI_PSSILPEN_Msk

+#define RCC_AHB2LPENR_DCMILPEN                 RCC_AHB2LPENR_DCMI_PSSILPEN

+

+/********************  Bit definition for RCC_AHB4LPENR register  ******************/

+#define RCC_AHB4LPENR_GPIOALPEN_Pos            (0U)

+#define RCC_AHB4LPENR_GPIOALPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB4LPENR_GPIOALPEN                RCC_AHB4LPENR_GPIOALPEN_Msk

+#define RCC_AHB4LPENR_GPIOBLPEN_Pos            (1U)

+#define RCC_AHB4LPENR_GPIOBLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */

+#define RCC_AHB4LPENR_GPIOBLPEN                RCC_AHB4LPENR_GPIOBLPEN_Msk

+#define RCC_AHB4LPENR_GPIOCLPEN_Pos            (2U)

+#define RCC_AHB4LPENR_GPIOCLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */

+#define RCC_AHB4LPENR_GPIOCLPEN                RCC_AHB4LPENR_GPIOCLPEN_Msk

+#define RCC_AHB4LPENR_GPIODLPEN_Pos            (3U)

+#define RCC_AHB4LPENR_GPIODLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */

+#define RCC_AHB4LPENR_GPIODLPEN                RCC_AHB4LPENR_GPIODLPEN_Msk

+#define RCC_AHB4LPENR_GPIOELPEN_Pos            (4U)

+#define RCC_AHB4LPENR_GPIOELPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */

+#define RCC_AHB4LPENR_GPIOELPEN                RCC_AHB4LPENR_GPIOELPEN_Msk

+#define RCC_AHB4LPENR_GPIOFLPEN_Pos            (5U)

+#define RCC_AHB4LPENR_GPIOFLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB4LPENR_GPIOFLPEN                RCC_AHB4LPENR_GPIOFLPEN_Msk

+#define RCC_AHB4LPENR_GPIOGLPEN_Pos            (6U)

+#define RCC_AHB4LPENR_GPIOGLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */

+#define RCC_AHB4LPENR_GPIOGLPEN                RCC_AHB4LPENR_GPIOGLPEN_Msk

+#define RCC_AHB4LPENR_GPIOHLPEN_Pos            (7U)

+#define RCC_AHB4LPENR_GPIOHLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */

+#define RCC_AHB4LPENR_GPIOHLPEN                RCC_AHB4LPENR_GPIOHLPEN_Msk

+#define RCC_AHB4LPENR_GPIOILPEN_Pos            (8U)

+#define RCC_AHB4LPENR_GPIOILPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */

+#define RCC_AHB4LPENR_GPIOILPEN                RCC_AHB4LPENR_GPIOILPEN_Msk

+#define RCC_AHB4LPENR_GPIOJLPEN_Pos            (9U)

+#define RCC_AHB4LPENR_GPIOJLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */

+#define RCC_AHB4LPENR_GPIOJLPEN                RCC_AHB4LPENR_GPIOJLPEN_Msk

+#define RCC_AHB4LPENR_GPIOKLPEN_Pos            (10U)

+#define RCC_AHB4LPENR_GPIOKLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */

+#define RCC_AHB4LPENR_GPIOKLPEN                RCC_AHB4LPENR_GPIOKLPEN_Msk

+#define RCC_AHB4LPENR_BDMA2LPEN_Pos             (21U)

+#define RCC_AHB4LPENR_BDMA2LPEN_Msk             (0x1UL << RCC_AHB4LPENR_BDMA2LPEN_Pos) /*!< 0x00200000 */

+#define RCC_AHB4LPENR_BDMA2LPEN                 RCC_AHB4LPENR_BDMA2LPEN_Msk

+#define RCC_AHB4LPENR_BKPRAMLPEN_Pos           (28U)

+#define RCC_AHB4LPENR_BKPRAMLPEN_Msk           (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */

+#define RCC_AHB4LPENR_BKPRAMLPEN               RCC_AHB4LPENR_BKPRAMLPEN_Msk

+#define RCC_AHB4LPENR_SRDSRAMLPEN_Pos          (29U)

+#define RCC_AHB4LPENR_SRDSRAMLPEN_Msk          (0x1UL << RCC_AHB4LPENR_SRDSRAMLPEN_Pos) /*!< 0x20000000 */

+#define RCC_AHB4LPENR_SRDSRAMLPEN              RCC_AHB4LPENR_SRDSRAMLPEN_Msk

+

+/********************  Bit definition for RCC_APB3LPENR register  ******************/

+#define RCC_APB3LPENR_LTDCLPEN_Pos             (3U)

+#define RCC_APB3LPENR_LTDCLPEN_Msk             (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB3LPENR_LTDCLPEN                 RCC_APB3LPENR_LTDCLPEN_Msk

+#define RCC_APB3LPENR_WWDGLPEN_Pos             (6U)

+#define RCC_APB3LPENR_WWDGLPEN_Msk             (0x1UL << RCC_APB3LPENR_WWDGLPEN_Pos)  /*!< 0x00000040 */

+#define RCC_APB3LPENR_WWDGLPEN                 RCC_APB3LPENR_WWDGLPEN_Msk

+

+/* Legacy define */

+#define RCC_APB3LPENR_WWDG1LPEN_Pos            RCC_APB3LPENR_WWDGLPEN_Pos

+#define RCC_APB3LPENR_WWDG1LPEN_Msk            RCC_APB3LPENR_WWDGLPEN_Msk

+#define RCC_APB3LPENR_WWDG1LPEN                RCC_APB3LPENR_WWDGLPEN

+/********************  Bit definition for RCC_APB1LLPENR register  ******************/

+

+#define RCC_APB1LLPENR_TIM2LPEN_Pos            (0U)

+#define RCC_APB1LLPENR_TIM2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */

+#define RCC_APB1LLPENR_TIM2LPEN                RCC_APB1LLPENR_TIM2LPEN_Msk

+#define RCC_APB1LLPENR_TIM3LPEN_Pos            (1U)

+#define RCC_APB1LLPENR_TIM3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1LLPENR_TIM3LPEN                RCC_APB1LLPENR_TIM3LPEN_Msk

+#define RCC_APB1LLPENR_TIM4LPEN_Pos            (2U)

+#define RCC_APB1LLPENR_TIM4LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1LLPENR_TIM4LPEN                RCC_APB1LLPENR_TIM4LPEN_Msk

+#define RCC_APB1LLPENR_TIM5LPEN_Pos            (3U)

+#define RCC_APB1LLPENR_TIM5LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB1LLPENR_TIM5LPEN                RCC_APB1LLPENR_TIM5LPEN_Msk

+#define RCC_APB1LLPENR_TIM6LPEN_Pos            (4U)

+#define RCC_APB1LLPENR_TIM6LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1LLPENR_TIM6LPEN                RCC_APB1LLPENR_TIM6LPEN_Msk

+#define RCC_APB1LLPENR_TIM7LPEN_Pos            (5U)

+#define RCC_APB1LLPENR_TIM7LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1LLPENR_TIM7LPEN                RCC_APB1LLPENR_TIM7LPEN_Msk

+#define RCC_APB1LLPENR_TIM12LPEN_Pos           (6U)

+#define RCC_APB1LLPENR_TIM12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */

+#define RCC_APB1LLPENR_TIM12LPEN               RCC_APB1LLPENR_TIM12LPEN_Msk

+#define RCC_APB1LLPENR_TIM13LPEN_Pos           (7U)

+#define RCC_APB1LLPENR_TIM13LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB1LLPENR_TIM13LPEN               RCC_APB1LLPENR_TIM13LPEN_Msk

+#define RCC_APB1LLPENR_TIM14LPEN_Pos           (8U)

+#define RCC_APB1LLPENR_TIM14LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1LLPENR_TIM14LPEN               RCC_APB1LLPENR_TIM14LPEN_Msk

+#define RCC_APB1LLPENR_LPTIM1LPEN_Pos          (9U)

+#define RCC_APB1LLPENR_LPTIM1LPEN_Msk          (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */

+#define RCC_APB1LLPENR_LPTIM1LPEN              RCC_APB1LLPENR_LPTIM1LPEN_Msk

+

+

+#define RCC_APB1LLPENR_SPI2LPEN_Pos            (14U)

+#define RCC_APB1LLPENR_SPI2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */

+#define RCC_APB1LLPENR_SPI2LPEN                RCC_APB1LLPENR_SPI2LPEN_Msk

+#define RCC_APB1LLPENR_SPI3LPEN_Pos            (15U)

+#define RCC_APB1LLPENR_SPI3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */

+#define RCC_APB1LLPENR_SPI3LPEN                RCC_APB1LLPENR_SPI3LPEN_Msk

+#define RCC_APB1LLPENR_SPDIFRXLPEN_Pos         (16U)

+#define RCC_APB1LLPENR_SPDIFRXLPEN_Msk         (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB1LLPENR_SPDIFRXLPEN             RCC_APB1LLPENR_SPDIFRXLPEN_Msk

+#define RCC_APB1LLPENR_USART2LPEN_Pos          (17U)

+#define RCC_APB1LLPENR_USART2LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */

+#define RCC_APB1LLPENR_USART2LPEN              RCC_APB1LLPENR_USART2LPEN_Msk

+#define RCC_APB1LLPENR_USART3LPEN_Pos          (18U)

+#define RCC_APB1LLPENR_USART3LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */

+#define RCC_APB1LLPENR_USART3LPEN              RCC_APB1LLPENR_USART3LPEN_Msk

+#define RCC_APB1LLPENR_UART4LPEN_Pos           (19U)

+#define RCC_APB1LLPENR_UART4LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */

+#define RCC_APB1LLPENR_UART4LPEN               RCC_APB1LLPENR_UART4LPEN_Msk

+#define RCC_APB1LLPENR_UART5LPEN_Pos           (20U)

+#define RCC_APB1LLPENR_UART5LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */

+#define RCC_APB1LLPENR_UART5LPEN               RCC_APB1LLPENR_UART5LPEN_Msk

+#define RCC_APB1LLPENR_I2C1LPEN_Pos            (21U)

+#define RCC_APB1LLPENR_I2C1LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */

+#define RCC_APB1LLPENR_I2C1LPEN                RCC_APB1LLPENR_I2C1LPEN_Msk

+#define RCC_APB1LLPENR_I2C2LPEN_Pos            (22U)

+#define RCC_APB1LLPENR_I2C2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */

+#define RCC_APB1LLPENR_I2C2LPEN                RCC_APB1LLPENR_I2C2LPEN_Msk

+#define RCC_APB1LLPENR_I2C3LPEN_Pos            (23U)

+#define RCC_APB1LLPENR_I2C3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */

+#define RCC_APB1LLPENR_I2C3LPEN                RCC_APB1LLPENR_I2C3LPEN_Msk

+#define RCC_APB1LLPENR_CECLPEN_Pos             (27U)

+#define RCC_APB1LLPENR_CECLPEN_Msk             (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */

+#define RCC_APB1LLPENR_CECLPEN                 RCC_APB1LLPENR_CECLPEN_Msk

+#define RCC_APB1LLPENR_DAC12LPEN_Pos           (29U)

+#define RCC_APB1LLPENR_DAC12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */

+#define RCC_APB1LLPENR_DAC12LPEN               RCC_APB1LLPENR_DAC12LPEN_Msk

+#define RCC_APB1LLPENR_UART7LPEN_Pos           (30U)

+#define RCC_APB1LLPENR_UART7LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */

+#define RCC_APB1LLPENR_UART7LPEN               RCC_APB1LLPENR_UART7LPEN_Msk

+#define RCC_APB1LLPENR_UART8LPEN_Pos           (31U)

+#define RCC_APB1LLPENR_UART8LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */

+#define RCC_APB1LLPENR_UART8LPEN               RCC_APB1LLPENR_UART8LPEN_Msk

+

+/* Legacy define */

+#define RCC_APB1LLPENR_HDMICECEN_Pos           RCC_APB1LLPENR_CECLPEN_Pos

+#define RCC_APB1LLPENR_HDMICECEN_Msk           RCC_APB1LLPENR_CECLPEN_Msk

+#define RCC_APB1LLPENR_HDMICECEN               RCC_APB1LLPENR_CECLPEN

+/********************  Bit definition for RCC_APB1HLPENR register  ******************/

+#define RCC_APB1HLPENR_CRSLPEN_Pos             (1U)

+#define RCC_APB1HLPENR_CRSLPEN_Msk             (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1HLPENR_CRSLPEN                 RCC_APB1HLPENR_CRSLPEN_Msk

+#define RCC_APB1HLPENR_SWPMILPEN_Pos           (2U)

+#define RCC_APB1HLPENR_SWPMILPEN_Msk           (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1HLPENR_SWPMILPEN               RCC_APB1HLPENR_SWPMILPEN_Msk

+#define RCC_APB1HLPENR_OPAMPLPEN_Pos           (4U)

+#define RCC_APB1HLPENR_OPAMPLPEN_Msk           (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1HLPENR_OPAMPLPEN               RCC_APB1HLPENR_OPAMPLPEN_Msk

+#define RCC_APB1HLPENR_MDIOSLPEN_Pos           (5U)

+#define RCC_APB1HLPENR_MDIOSLPEN_Msk           (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1HLPENR_MDIOSLPEN               RCC_APB1HLPENR_MDIOSLPEN_Msk

+#define RCC_APB1HLPENR_FDCANLPEN_Pos           (8U)

+#define RCC_APB1HLPENR_FDCANLPEN_Msk           (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1HLPENR_FDCANLPEN               RCC_APB1HLPENR_FDCANLPEN_Msk

+

+/********************  Bit definition for RCC_APB2LPENR register  ******************/

+#define RCC_APB2LPENR_TIM1LPEN_Pos             (0U)

+#define RCC_APB2LPENR_TIM1LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */

+#define RCC_APB2LPENR_TIM1LPEN                 RCC_APB2LPENR_TIM1LPEN_Msk

+#define RCC_APB2LPENR_TIM8LPEN_Pos             (1U)

+#define RCC_APB2LPENR_TIM8LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB2LPENR_TIM8LPEN                 RCC_APB2LPENR_TIM8LPEN_Msk

+#define RCC_APB2LPENR_USART1LPEN_Pos           (4U)

+#define RCC_APB2LPENR_USART1LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB2LPENR_USART1LPEN               RCC_APB2LPENR_USART1LPEN_Msk

+#define RCC_APB2LPENR_USART6LPEN_Pos           (5U)

+#define RCC_APB2LPENR_USART6LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB2LPENR_USART6LPEN               RCC_APB2LPENR_USART6LPEN_Msk

+#define RCC_APB2LPENR_UART9LPEN_Pos            (6U)

+#define RCC_APB2LPENR_UART9LPEN_Msk            (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos) /*!< 0x00000040 */

+#define RCC_APB2LPENR_UART9LPEN                 RCC_APB2LPENR_UART9LPEN_Msk

+#define RCC_APB2LPENR_USART10LPEN_Pos          (7U)

+#define RCC_APB2LPENR_USART10LPEN_Msk          (0x1UL << RCC_APB2LPENR_USART10LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB2LPENR_USART10LPEN               RCC_APB2LPENR_USART10LPEN_Msk

+#define RCC_APB2LPENR_SPI1LPEN_Pos             (12U)

+#define RCC_APB2LPENR_SPI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */

+#define RCC_APB2LPENR_SPI1LPEN                 RCC_APB2LPENR_SPI1LPEN_Msk

+#define RCC_APB2LPENR_SPI4LPEN_Pos             (13U)

+#define RCC_APB2LPENR_SPI4LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */

+#define RCC_APB2LPENR_SPI4LPEN                 RCC_APB2LPENR_SPI4LPEN_Msk

+#define RCC_APB2LPENR_TIM15LPEN_Pos            (16U)

+#define RCC_APB2LPENR_TIM15LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB2LPENR_TIM15LPEN                RCC_APB2LPENR_TIM15LPEN_Msk

+#define RCC_APB2LPENR_TIM16LPEN_Pos            (17U)

+#define RCC_APB2LPENR_TIM16LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */

+#define RCC_APB2LPENR_TIM16LPEN                RCC_APB2LPENR_TIM16LPEN_Msk

+#define RCC_APB2LPENR_TIM17LPEN_Pos            (18U)

+#define RCC_APB2LPENR_TIM17LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */

+#define RCC_APB2LPENR_TIM17LPEN                RCC_APB2LPENR_TIM17LPEN_Msk

+#define RCC_APB2LPENR_SPI5LPEN_Pos             (20U)

+#define RCC_APB2LPENR_SPI5LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */

+#define RCC_APB2LPENR_SPI5LPEN                 RCC_APB2LPENR_SPI5LPEN_Msk

+#define RCC_APB2LPENR_SAI1LPEN_Pos             (22U)

+#define RCC_APB2LPENR_SAI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */

+#define RCC_APB2LPENR_SAI1LPEN                 RCC_APB2LPENR_SAI1LPEN_Msk

+#define RCC_APB2LPENR_SAI2LPEN_Pos             (23U)

+#define RCC_APB2LPENR_SAI2LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */

+#define RCC_APB2LPENR_SAI2LPEN                 RCC_APB2LPENR_SAI2LPEN_Msk

+#define RCC_APB2LPENR_DFSDM1LPEN_Pos           (30U)

+#define RCC_APB2LPENR_DFSDM1LPEN_Msk           (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x40000000 */

+#define RCC_APB2LPENR_DFSDM1LPEN               RCC_APB2LPENR_DFSDM1LPEN_Msk

+

+/********************  Bit definition for RCC_APB4LPENR register  ******************/

+#define RCC_APB4LPENR_SYSCFGLPEN_Pos           (1U)

+#define RCC_APB4LPENR_SYSCFGLPEN_Msk           (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB4LPENR_SYSCFGLPEN               RCC_APB4LPENR_SYSCFGLPEN_Msk

+#define RCC_APB4LPENR_LPUART1LPEN_Pos          (3U)

+#define RCC_APB4LPENR_LPUART1LPEN_Msk          (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB4LPENR_LPUART1LPEN              RCC_APB4LPENR_LPUART1LPEN_Msk

+#define RCC_APB4LPENR_SPI6LPEN_Pos             (5U)

+#define RCC_APB4LPENR_SPI6LPEN_Msk             (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB4LPENR_SPI6LPEN                 RCC_APB4LPENR_SPI6LPEN_Msk

+#define RCC_APB4LPENR_I2C4LPEN_Pos             (7U)

+#define RCC_APB4LPENR_I2C4LPEN_Msk             (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB4LPENR_I2C4LPEN                 RCC_APB4LPENR_I2C4LPEN_Msk

+#define RCC_APB4LPENR_LPTIM2LPEN_Pos           (9U)

+#define RCC_APB4LPENR_LPTIM2LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */

+#define RCC_APB4LPENR_LPTIM2LPEN               RCC_APB4LPENR_LPTIM2LPEN_Msk

+#define RCC_APB4LPENR_LPTIM3LPEN_Pos           (10U)

+#define RCC_APB4LPENR_LPTIM3LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */

+#define RCC_APB4LPENR_LPTIM3LPEN               RCC_APB4LPENR_LPTIM3LPEN_Msk

+#define RCC_APB4LPENR_DAC2LPEN_Pos             (13U)

+#define RCC_APB4LPENR_DAC2LPEN_Msk             (0x1UL << RCC_APB4LPENR_DAC2LPEN_Pos) /*!< 0x00002000 */

+#define RCC_APB4LPENR_DAC2LPEN                 RCC_APB4LPENR_DAC2LPEN_Msk

+#define RCC_APB4LPENR_COMP12LPEN_Pos           (14U)

+#define RCC_APB4LPENR_COMP12LPEN_Msk           (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */

+#define RCC_APB4LPENR_COMP12LPEN               RCC_APB4LPENR_COMP12LPEN_Msk

+#define RCC_APB4LPENR_VREFLPEN_Pos             (15U)

+#define RCC_APB4LPENR_VREFLPEN_Msk             (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */

+#define RCC_APB4LPENR_VREFLPEN                 RCC_APB4LPENR_VREFLPEN_Msk

+#define RCC_APB4LPENR_RTCAPBLPEN_Pos           (16U)

+#define RCC_APB4LPENR_RTCAPBLPEN_Msk           (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB4LPENR_RTCAPBLPEN               RCC_APB4LPENR_RTCAPBLPEN_Msk

+

+#define RCC_APB4LPENR_DTSLPEN_Pos              (26U)

+#define RCC_APB4LPENR_DTSLPEN_Msk              (0x1UL << RCC_APB4LPENR_DTSLPEN_Pos) /*!< 0x04000000 */

+#define RCC_APB4LPENR_DTSLPEN                  RCC_APB4LPENR_DTSLPEN_Msk

+#define RCC_APB4LPENR_DFSDM2LPEN_Pos           (27U)

+#define RCC_APB4LPENR_DFSDM2LPEN_Msk           (0x1UL << RCC_APB4LPENR_DFSDM2LPEN_Pos) /*!< 0x08000000 */

+#define RCC_APB4LPENR_DFSDM2LPEN                RCC_APB4LPENR_DFSDM2LPEN_Msk

+

+/********************  Bit definition for RCC_RSR register  *******************/

+#define RCC_RSR_RMVF_Pos                       (16U)

+#define RCC_RSR_RMVF_Msk                       (0x1UL << RCC_RSR_RMVF_Pos)     /*!< 0x00010000 */

+#define RCC_RSR_RMVF                           RCC_RSR_RMVF_Msk

+#define RCC_RSR_CDRSTF_Pos                     (19U)

+#define RCC_RSR_CDRSTF_Msk                     (0x1UL << RCC_RSR_CDRSTF_Pos)   /*!< 0x00080000 */

+#define RCC_RSR_CDRSTF                         RCC_RSR_CDRSTF_Msk

+#define RCC_RSR_BORRSTF_Pos                    (21U)

+#define RCC_RSR_BORRSTF_Msk                    (0x1UL << RCC_RSR_BORRSTF_Pos)  /*!< 0x00200000 */

+#define RCC_RSR_BORRSTF                        RCC_RSR_BORRSTF_Msk

+#define RCC_RSR_PINRSTF_Pos                    (22U)

+#define RCC_RSR_PINRSTF_Msk                    (0x1UL << RCC_RSR_PINRSTF_Pos)  /*!< 0x00400000 */

+#define RCC_RSR_PINRSTF                        RCC_RSR_PINRSTF_Msk

+#define RCC_RSR_PORRSTF_Pos                    (23U)

+#define RCC_RSR_PORRSTF_Msk                    (0x1UL << RCC_RSR_PORRSTF_Pos)  /*!< 0x00800000 */

+#define RCC_RSR_PORRSTF                        RCC_RSR_PORRSTF_Msk

+#define RCC_RSR_SFTRSTF_Pos                    (24U)

+#define RCC_RSR_SFTRSTF_Msk                    (0x1UL << RCC_RSR_SFTRSTF_Pos)  /*!< 0x01000000 */

+#define RCC_RSR_SFTRSTF                        RCC_RSR_SFTRSTF_Msk

+#define RCC_RSR_IWDGRSTF_Pos                   (26U)

+#define RCC_RSR_IWDGRSTF_Msk                   (0x1UL << RCC_RSR_IWDGRSTF_Pos) /*!< 0x04000000 */

+#define RCC_RSR_IWDGRSTF                       RCC_RSR_IWDGRSTF_Msk

+#define RCC_RSR_WWDGRSTF_Pos                   (28U)

+#define RCC_RSR_WWDGRSTF_Msk                   (0x1UL << RCC_RSR_WWDGRSTF_Pos) /*!< 0x10000000 */

+#define RCC_RSR_WWDGRSTF                       RCC_RSR_WWDGRSTF_Msk

+

+#define RCC_RSR_LPWRRSTF_Pos                   (30U)

+#define RCC_RSR_LPWRRSTF_Msk                   (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */

+#define RCC_RSR_LPWRRSTF                       RCC_RSR_LPWRRSTF_Msk

+

+

+/* Legacy define */

+#define RCC_RSR_IWDG1RSTF_Pos                  RCC_RSR_IWDGRSTF_Pos

+#define RCC_RSR_IWDG1RSTF_Msk                  RCC_RSR_IWDGRSTF_Msk

+#define RCC_RSR_IWDG1RSTF                      RCC_RSR_IWDGRSTF

+#define RCC_RSR_WWDG1RSTF_Pos                  RCC_RSR_WWDGRSTF_Pos

+#define RCC_RSR_WWDG1RSTF_Msk                  RCC_RSR_WWDGRSTF_Msk

+#define RCC_RSR_WWDG1RSTF                      RCC_RSR_WWDGRSTF

+/******************************************************************************/

+/*                                                                            */

+/*                                    RNG                                     */

+/*                                                                            */

+/******************************************************************************/

+/***************************    RNG VER  **************************************/

+#define RNG_VER_3_1

+/********************  Bits definition for RNG_CR register  *******************/

+#define RNG_CR_RNGEN_Pos    (2U)

+#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */

+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk

+#define RNG_CR_IE_Pos       (3U)

+#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */

+#define RNG_CR_IE           RNG_CR_IE_Msk

+#define RNG_CR_CED_Pos      (5U)

+#define RNG_CR_CED_Msk      (0x1UL << RNG_CR_CED_Pos)                          /*!< 0x00000020 */

+#define RNG_CR_CED          RNG_CR_CED_Msk

+#define RNG_CR_RNG_CONFIG3_Pos      (8U)

+#define RNG_CR_RNG_CONFIG3_Msk      (0xFUL << RNG_CR_RNG_CONFIG3_Pos)          /*!< 0x00000F00 */

+#define RNG_CR_RNG_CONFIG3          RNG_CR_RNG_CONFIG3_Msk

+#define RNG_CR_NISTC_Pos            (12U)

+#define RNG_CR_NISTC_Msk            (0x1UL << RNG_CR_NISTC_Pos)                /*!< 0x00001000 */

+#define RNG_CR_NISTC                RNG_CR_NISTC_Msk

+#define RNG_CR_RNG_CONFIG2_Pos      (13U)

+#define RNG_CR_RNG_CONFIG2_Msk      (0x7UL << RNG_CR_RNG_CONFIG2_Pos)          /*!< 0x0000E000 */

+#define RNG_CR_RNG_CONFIG2          RNG_CR_RNG_CONFIG2_Msk

+#define RNG_CR_CLKDIV_Pos           (16U)

+#define RNG_CR_CLKDIV_Msk           (0xFUL << RNG_CR_CLKDIV_Pos)               /*!< 0x000F0000 */

+#define RNG_CR_CLKDIV               RNG_CR_CLKDIV_Msk

+#define RNG_CR_CLKDIV_0             (0x1U << RNG_CR_CLKDIV_Pos)                /*!< 0x00010000 */

+#define RNG_CR_CLKDIV_1             (0x2U << RNG_CR_CLKDIV_Pos)                /*!< 0x00020000 */

+#define RNG_CR_CLKDIV_2             (0x4U << RNG_CR_CLKDIV_Pos)                /*!< 0x00040000 */

+#define RNG_CR_CLKDIV_3             (0x8U << RNG_CR_CLKDIV_Pos)                /*!< 0x00080000 */

+#define RNG_CR_RNG_CONFIG1_Pos      (20U)

+#define RNG_CR_RNG_CONFIG1_Msk      (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)         /*!< 0x03F00000 */

+#define RNG_CR_RNG_CONFIG1          RNG_CR_RNG_CONFIG1_Msk

+#define RNG_CR_CONDRST_Pos         (30U)

+#define RNG_CR_CONDRST_Msk         (0x1UL << RNG_CR_CONDRST_Pos)                  /*!< 0x40000000 */

+#define RNG_CR_CONDRST             RNG_CR_CONDRST_Msk

+#define RNG_CR_CONFIGLOCK_Pos      (31U)

+#define RNG_CR_CONFIGLOCK_Msk      (0x1UL << RNG_CR_CONFIGLOCK_Pos)            /*!< 0x80000000 */

+#define RNG_CR_CONFIGLOCK          RNG_CR_CONFIGLOCK_Msk

+

+/********************  Bits definition for RNG_SR register  *******************/

+#define RNG_SR_DRDY_Pos     (0U)

+#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */

+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk

+#define RNG_SR_CECS_Pos     (1U)

+#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */

+#define RNG_SR_CECS         RNG_SR_CECS_Msk

+#define RNG_SR_SECS_Pos     (2U)

+#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */

+#define RNG_SR_SECS         RNG_SR_SECS_Msk

+#define RNG_SR_CEIS_Pos     (5U)

+#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */

+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk

+#define RNG_SR_SEIS_Pos     (6U)

+#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */

+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                           Real-Time Clock (RTC)                            */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for RTC_TR register  *******************/

+#define RTC_TR_PM_Pos                  (22U)

+#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */

+#define RTC_TR_PM                      RTC_TR_PM_Msk

+#define RTC_TR_HT_Pos                  (20U)

+#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */

+#define RTC_TR_HT                      RTC_TR_HT_Msk

+#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */

+#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */

+#define RTC_TR_HU_Pos                  (16U)

+#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */

+#define RTC_TR_HU                      RTC_TR_HU_Msk

+#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */

+#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */

+#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */

+#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */

+#define RTC_TR_MNT_Pos                 (12U)

+#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */

+#define RTC_TR_MNT                     RTC_TR_MNT_Msk

+#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */

+#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */

+#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */

+#define RTC_TR_MNU_Pos                 (8U)

+#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */

+#define RTC_TR_MNU                     RTC_TR_MNU_Msk

+#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */

+#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */

+#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */

+#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */

+#define RTC_TR_ST_Pos                  (4U)

+#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */

+#define RTC_TR_ST                      RTC_TR_ST_Msk

+#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */

+#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */

+#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */

+#define RTC_TR_SU_Pos                  (0U)

+#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */

+#define RTC_TR_SU                      RTC_TR_SU_Msk

+#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */

+#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */

+#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */

+#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_DR register  *******************/

+#define RTC_DR_YT_Pos                  (20U)

+#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */

+#define RTC_DR_YT                      RTC_DR_YT_Msk

+#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */

+#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */

+#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */

+#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */

+#define RTC_DR_YU_Pos                  (16U)

+#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */

+#define RTC_DR_YU                      RTC_DR_YU_Msk

+#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */

+#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */

+#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */

+#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */

+#define RTC_DR_WDU_Pos                 (13U)

+#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */

+#define RTC_DR_WDU                     RTC_DR_WDU_Msk

+#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */

+#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */

+#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */

+#define RTC_DR_MT_Pos                  (12U)

+#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */

+#define RTC_DR_MT                      RTC_DR_MT_Msk

+#define RTC_DR_MU_Pos                  (8U)

+#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */

+#define RTC_DR_MU                      RTC_DR_MU_Msk

+#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */

+#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */

+#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */

+#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */

+#define RTC_DR_DT_Pos                  (4U)

+#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */

+#define RTC_DR_DT                      RTC_DR_DT_Msk

+#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */

+#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */

+#define RTC_DR_DU_Pos                  (0U)

+#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */

+#define RTC_DR_DU                      RTC_DR_DU_Msk

+#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */

+#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */

+#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */

+#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_CR register  *******************/

+#define RTC_CR_OUT2EN_Pos            (31U)

+#define RTC_CR_OUT2EN_Msk            (0x1UL << RTC_CR_OUT2EN_Pos)              /*!< 0x80000000 */

+#define RTC_CR_OUT2EN                RTC_CR_OUT2EN_Msk                         /*!<RTC_OUT2 output enable */

+#define RTC_CR_TAMPALRM_TYPE_Pos     (30U)

+#define RTC_CR_TAMPALRM_TYPE_Msk     (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)       /*!< 0x40000000 */

+#define RTC_CR_TAMPALRM_TYPE         RTC_CR_TAMPALRM_TYPE_Msk                  /*!<TAMPALARM output type  */

+#define RTC_CR_TAMPALRM_PU_Pos       (29U)

+#define RTC_CR_TAMPALRM_PU_Msk       (0x1UL << RTC_CR_TAMPALRM_PU_Pos)         /*!< 0x20000000 */

+#define RTC_CR_TAMPALRM_PU           RTC_CR_TAMPALRM_PU_Msk                    /*!<TAMPALARM output pull-up config */

+#define RTC_CR_TAMPOE_Pos            (26U)

+#define RTC_CR_TAMPOE_Msk            (0x1UL << RTC_CR_TAMPOE_Pos)              /*!< 0x04000000 */

+#define RTC_CR_TAMPOE                RTC_CR_TAMPOE_Msk                         /*!<Tamper detection output enable on TAMPALARM  */

+#define RTC_CR_TAMPTS_Pos            (25U)

+#define RTC_CR_TAMPTS_Msk            (0x1UL << RTC_CR_TAMPTS_Pos)              /*!< 0x02000000 */

+#define RTC_CR_TAMPTS                RTC_CR_TAMPTS_Msk                         /*!<Activate timestamp on tamper detection event  */

+#define RTC_CR_ITSE_Pos                (24U)

+#define RTC_CR_ITSE_Msk                (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */

+#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk

+#define RTC_CR_COE_Pos                 (23U)

+#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */

+#define RTC_CR_COE                     RTC_CR_COE_Msk

+#define RTC_CR_OSEL_Pos                (21U)

+#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */

+#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk

+#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */

+#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */

+#define RTC_CR_POL_Pos                 (20U)

+#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */

+#define RTC_CR_POL                     RTC_CR_POL_Msk

+#define RTC_CR_COSEL_Pos               (19U)

+#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */

+#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk

+#define RTC_CR_BKP_Pos                 (18U)

+#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */

+#define RTC_CR_BKP                     RTC_CR_BKP_Msk

+#define RTC_CR_SUB1H_Pos               (17U)

+#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */

+#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk

+#define RTC_CR_ADD1H_Pos               (16U)

+#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */

+#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk

+#define RTC_CR_TSIE_Pos                (15U)

+#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */

+#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk

+#define RTC_CR_WUTIE_Pos               (14U)

+#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */

+#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk

+#define RTC_CR_ALRBIE_Pos              (13U)

+#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */

+#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk

+#define RTC_CR_ALRAIE_Pos              (12U)

+#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */

+#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk

+#define RTC_CR_TSE_Pos                 (11U)

+#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */

+#define RTC_CR_TSE                     RTC_CR_TSE_Msk

+#define RTC_CR_WUTE_Pos                (10U)

+#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */

+#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk

+#define RTC_CR_ALRBE_Pos               (9U)

+#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */

+#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk

+#define RTC_CR_ALRAE_Pos               (8U)

+#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */

+#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk

+#define RTC_CR_FMT_Pos                 (6U)

+#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */

+#define RTC_CR_FMT                     RTC_CR_FMT_Msk

+#define RTC_CR_BYPSHAD_Pos             (5U)

+#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */

+#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk

+#define RTC_CR_REFCKON_Pos             (4U)

+#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */

+#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk

+#define RTC_CR_TSEDGE_Pos              (3U)

+#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */

+#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk

+#define RTC_CR_WUCKSEL_Pos             (0U)

+#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */

+#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk

+#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */

+#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */

+#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */

+

+/********************  Bits definition for RTC_ICSR register  ******************/

+#define RTC_ICSR_RECALPF_Pos         (16U)

+#define RTC_ICSR_RECALPF_Msk         (0x1UL << RTC_ICSR_RECALPF_Pos)           /*!< 0x00010000 */

+#define RTC_ICSR_RECALPF             RTC_ICSR_RECALPF_Msk

+#define RTC_ICSR_INIT_Pos            (7U)

+#define RTC_ICSR_INIT_Msk            (0x1UL << RTC_ICSR_INIT_Pos)              /*!< 0x00000080 */

+#define RTC_ICSR_INIT                RTC_ICSR_INIT_Msk

+#define RTC_ICSR_INITF_Pos           (6U)

+#define RTC_ICSR_INITF_Msk           (0x1UL << RTC_ICSR_INITF_Pos)             /*!< 0x00000040 */

+#define RTC_ICSR_INITF               RTC_ICSR_INITF_Msk

+#define RTC_ICSR_RSF_Pos             (5U)

+#define RTC_ICSR_RSF_Msk             (0x1UL << RTC_ICSR_RSF_Pos)               /*!< 0x00000020 */

+#define RTC_ICSR_RSF                 RTC_ICSR_RSF_Msk

+#define RTC_ICSR_INITS_Pos           (4U)

+#define RTC_ICSR_INITS_Msk           (0x1UL << RTC_ICSR_INITS_Pos)             /*!< 0x00000010 */

+#define RTC_ICSR_INITS               RTC_ICSR_INITS_Msk

+#define RTC_ICSR_SHPF_Pos            (3U)

+#define RTC_ICSR_SHPF_Msk            (0x1UL << RTC_ICSR_SHPF_Pos)              /*!< 0x00000008 */

+#define RTC_ICSR_SHPF                RTC_ICSR_SHPF_Msk

+#define RTC_ICSR_WUTWF_Pos           (2U)

+#define RTC_ICSR_WUTWF_Msk           (0x1UL << RTC_ICSR_WUTWF_Pos)             /*!< 0x00000004 */

+#define RTC_ICSR_WUTWF               RTC_ICSR_WUTWF_Msk

+#define RTC_ICSR_ALRBWF_Pos          (1U)

+#define RTC_ICSR_ALRBWF_Msk          (0x1UL << RTC_ICSR_ALRBWF_Pos)            /*!< 0x00000002 */

+#define RTC_ICSR_ALRBWF              RTC_ICSR_ALRBWF_Msk

+#define RTC_ICSR_ALRAWF_Pos          (0U)

+#define RTC_ICSR_ALRAWF_Msk          (0x1UL << RTC_ICSR_ALRAWF_Pos)            /*!< 0x00000001 */

+#define RTC_ICSR_ALRAWF              RTC_ICSR_ALRAWF_Msk

+

+/********************  Bits definition for RTC_PRER register  *****************/

+#define RTC_PRER_PREDIV_A_Pos          (16U)

+#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */

+#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk

+#define RTC_PRER_PREDIV_S_Pos          (0U)

+#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */

+#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk

+

+/********************  Bits definition for RTC_WUTR register  *****************/

+#define RTC_WUTR_WUT_Pos               (0U)

+#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */

+#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk

+

+/********************  Bits definition for RTC_ALRMAR register  ***************/

+#define RTC_ALRMAR_MSK4_Pos            (31U)

+#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */

+#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk

+#define RTC_ALRMAR_WDSEL_Pos           (30U)

+#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */

+#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk

+#define RTC_ALRMAR_DT_Pos              (28U)

+#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */

+#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk

+#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */

+#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */

+#define RTC_ALRMAR_DU_Pos              (24U)

+#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */

+#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk

+#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */

+#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */

+#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */

+#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */

+#define RTC_ALRMAR_MSK3_Pos            (23U)

+#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */

+#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk

+#define RTC_ALRMAR_PM_Pos              (22U)

+#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */

+#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk

+#define RTC_ALRMAR_HT_Pos              (20U)

+#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */

+#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk

+#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */

+#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */

+#define RTC_ALRMAR_HU_Pos              (16U)

+#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */

+#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk

+#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */

+#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */

+#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */

+#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */

+#define RTC_ALRMAR_MSK2_Pos            (15U)

+#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */

+#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk

+#define RTC_ALRMAR_MNT_Pos             (12U)

+#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */

+#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk

+#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */

+#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */

+#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */

+#define RTC_ALRMAR_MNU_Pos             (8U)

+#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */

+#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk

+#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */

+#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */

+#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */

+#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */

+#define RTC_ALRMAR_MSK1_Pos            (7U)

+#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */

+#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk

+#define RTC_ALRMAR_ST_Pos              (4U)

+#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */

+#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk

+#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */

+#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */

+#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */

+#define RTC_ALRMAR_SU_Pos              (0U)

+#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */

+#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk

+#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */

+#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */

+#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */

+#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_ALRMBR register  ***************/

+#define RTC_ALRMBR_MSK4_Pos            (31U)

+#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */

+#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk

+#define RTC_ALRMBR_WDSEL_Pos           (30U)

+#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */

+#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk

+#define RTC_ALRMBR_DT_Pos              (28U)

+#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */

+#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk

+#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */

+#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */

+#define RTC_ALRMBR_DU_Pos              (24U)

+#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */

+#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk

+#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */

+#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */

+#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */

+#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */

+#define RTC_ALRMBR_MSK3_Pos            (23U)

+#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */

+#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk

+#define RTC_ALRMBR_PM_Pos              (22U)

+#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */

+#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk

+#define RTC_ALRMBR_HT_Pos              (20U)

+#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */

+#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk

+#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */

+#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */

+#define RTC_ALRMBR_HU_Pos              (16U)

+#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */

+#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk

+#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */

+#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */

+#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */

+#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */

+#define RTC_ALRMBR_MSK2_Pos            (15U)

+#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */

+#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk

+#define RTC_ALRMBR_MNT_Pos             (12U)

+#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */

+#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk

+#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */

+#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */

+#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */

+#define RTC_ALRMBR_MNU_Pos             (8U)

+#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */

+#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk

+#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */

+#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */

+#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */

+#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */

+#define RTC_ALRMBR_MSK1_Pos            (7U)

+#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */

+#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk

+#define RTC_ALRMBR_ST_Pos              (4U)

+#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */

+#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk

+#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */

+#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */

+#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */

+#define RTC_ALRMBR_SU_Pos              (0U)

+#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */

+#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk

+#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */

+#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */

+#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */

+#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_WPR register  ******************/

+#define RTC_WPR_KEY_Pos                (0U)

+#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */

+#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk

+

+/********************  Bits definition for RTC_SSR register  ******************/

+#define RTC_SSR_SS_Pos                 (0U)

+#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)            /*!< 0x0000FFFF */

+#define RTC_SSR_SS                     RTC_SSR_SS_Msk

+

+/********************  Bits definition for RTC_SHIFTR register  ***************/

+#define RTC_SHIFTR_SUBFS_Pos           (0U)

+#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */

+#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk

+#define RTC_SHIFTR_ADD1S_Pos           (31U)

+#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */

+#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk

+

+/********************  Bits definition for RTC_TSTR register  *****************/

+#define RTC_TSTR_PM_Pos                (22U)

+#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */

+#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk

+#define RTC_TSTR_HT_Pos                (20U)

+#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */

+#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk

+#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */

+#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */

+#define RTC_TSTR_HU_Pos                (16U)

+#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */

+#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk

+#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */

+#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */

+#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */

+#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */

+#define RTC_TSTR_MNT_Pos               (12U)

+#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */

+#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk

+#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */

+#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */

+#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */

+#define RTC_TSTR_MNU_Pos               (8U)

+#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */

+#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk

+#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */

+#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */

+#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */

+#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */

+#define RTC_TSTR_ST_Pos                (4U)

+#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */

+#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk

+#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */

+#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */

+#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */

+#define RTC_TSTR_SU_Pos                (0U)

+#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */

+#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk

+#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */

+#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */

+#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */

+#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_TSDR register  *****************/

+#define RTC_TSDR_WDU_Pos               (13U)

+#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */

+#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk

+#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */

+#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */

+#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */

+#define RTC_TSDR_MT_Pos                (12U)

+#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */

+#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk

+#define RTC_TSDR_MU_Pos                (8U)

+#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */

+#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk

+#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */

+#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */

+#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */

+#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */

+#define RTC_TSDR_DT_Pos                (4U)

+#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */

+#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk

+#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */

+#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */

+#define RTC_TSDR_DU_Pos                (0U)

+#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */

+#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk

+#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */

+#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */

+#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */

+#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_TSSSR register  ****************/

+#define RTC_TSSSR_SS_Pos               (0U)

+#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)          /*!< 0x0000FFFF */

+#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk

+

+/********************  Bits definition for RTC_CALR register  *****************/

+#define RTC_CALR_CALP_Pos              (15U)

+#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */

+#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk

+#define RTC_CALR_CALW8_Pos             (14U)

+#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */

+#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk

+#define RTC_CALR_CALW16_Pos            (13U)

+#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */

+#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk

+#define RTC_CALR_CALM_Pos              (0U)

+#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */

+#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk

+#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */

+#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */

+#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */

+#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */

+#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */

+#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */

+#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */

+#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */

+#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */

+

+

+/********************  Bits definition for RTC_ALRMASSR register  *************/

+#define RTC_ALRMASSR_MASKSS_Pos        (24U)

+#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x0F000000 */

+#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk

+#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */

+#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */

+#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */

+#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */

+#define RTC_ALRMASSR_SS_Pos            (0U)

+#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */

+#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk

+

+/********************  Bits definition for RTC_ALRMBSSR register  *************/

+#define RTC_ALRMBSSR_MASKSS_Pos        (24U)

+#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x0F000000 */

+#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk

+#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */

+#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */

+#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */

+#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */

+#define RTC_ALRMBSSR_SS_Pos            (0U)

+#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */

+#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk

+

+

+/********************  Bits definition for RTC_SR register  *******************/

+#define RTC_SR_ITSF_Pos              (5U)

+#define RTC_SR_ITSF_Msk              (0x1UL << RTC_SR_ITSF_Pos)                 /*!< 0x00000020 */

+#define RTC_SR_ITSF                  RTC_SR_ITSF_Msk

+#define RTC_SR_TSOVF_Pos             (4U)

+#define RTC_SR_TSOVF_Msk             (0x1UL << RTC_SR_TSOVF_Pos)                /*!< 0x00000010 */

+#define RTC_SR_TSOVF                 RTC_SR_TSOVF_Msk

+#define RTC_SR_TSF_Pos               (3U)

+#define RTC_SR_TSF_Msk               (0x1UL << RTC_SR_TSF_Pos)                  /*!< 0x00000008 */

+#define RTC_SR_TSF                   RTC_SR_TSF_Msk

+#define RTC_SR_WUTF_Pos              (2U)

+#define RTC_SR_WUTF_Msk              (0x1UL << RTC_SR_WUTF_Pos)                 /*!< 0x00000004 */

+#define RTC_SR_WUTF                  RTC_SR_WUTF_Msk

+#define RTC_SR_ALRBF_Pos             (1U)

+#define RTC_SR_ALRBF_Msk             (0x1UL << RTC_SR_ALRBF_Pos)                /*!< 0x00000002 */

+#define RTC_SR_ALRBF                 RTC_SR_ALRBF_Msk

+#define RTC_SR_ALRAF_Pos             (0U)

+#define RTC_SR_ALRAF_Msk             (0x1UL << RTC_SR_ALRAF_Pos)                /*!< 0x00000001 */

+#define RTC_SR_ALRAF                 RTC_SR_ALRAF_Msk

+

+/********************  Bits definition for RTC_MISR register  *****************/

+#define RTC_MISR_ITSMF_Pos           (5U)

+#define RTC_MISR_ITSMF_Msk           (0x1UL << RTC_MISR_ITSMF_Pos)              /*!< 0x00000020 */

+#define RTC_MISR_ITSMF               RTC_MISR_ITSMF_Msk

+#define RTC_MISR_TSOVMF_Pos          (4U)

+#define RTC_MISR_TSOVMF_Msk          (0x1UL << RTC_MISR_TSOVMF_Pos)             /*!< 0x00000010 */

+#define RTC_MISR_TSOVMF              RTC_MISR_TSOVMF_Msk

+#define RTC_MISR_TSMF_Pos            (3U)

+#define RTC_MISR_TSMF_Msk            (0x1UL << RTC_MISR_TSMF_Pos)               /*!< 0x00000008 */

+#define RTC_MISR_TSMF                RTC_MISR_TSMF_Msk

+#define RTC_MISR_WUTMF_Pos           (2U)

+#define RTC_MISR_WUTMF_Msk           (0x1UL << RTC_MISR_WUTMF_Pos)              /*!< 0x00000004 */

+#define RTC_MISR_WUTMF               RTC_MISR_WUTMF_Msk

+#define RTC_MISR_ALRBMF_Pos          (1U)

+#define RTC_MISR_ALRBMF_Msk          (0x1UL << RTC_MISR_ALRBMF_Pos)             /*!< 0x00000002 */

+#define RTC_MISR_ALRBMF              RTC_MISR_ALRBMF_Msk

+#define RTC_MISR_ALRAMF_Pos          (0U)

+#define RTC_MISR_ALRAMF_Msk          (0x1UL << RTC_MISR_ALRAMF_Pos)             /*!< 0x00000001 */

+#define RTC_MISR_ALRAMF              RTC_MISR_ALRAMF_Msk

+

+/********************  Bits definition for RTC_SCR register  ******************/

+#define RTC_SCR_CITSF_Pos            (5U)

+#define RTC_SCR_CITSF_Msk            (0x1UL << RTC_SCR_CITSF_Pos)               /*!< 0x00000020 */

+#define RTC_SCR_CITSF                RTC_SCR_CITSF_Msk

+#define RTC_SCR_CTSOVF_Pos           (4U)

+#define RTC_SCR_CTSOVF_Msk           (0x1UL << RTC_SCR_CTSOVF_Pos)              /*!< 0x00000010 */

+#define RTC_SCR_CTSOVF               RTC_SCR_CTSOVF_Msk

+#define RTC_SCR_CTSF_Pos             (3U)

+#define RTC_SCR_CTSF_Msk             (0x1UL << RTC_SCR_CTSF_Pos)                /*!< 0x00000008 */

+#define RTC_SCR_CTSF                 RTC_SCR_CTSF_Msk

+#define RTC_SCR_CWUTF_Pos            (2U)

+#define RTC_SCR_CWUTF_Msk            (0x1UL << RTC_SCR_CWUTF_Pos)               /*!< 0x00000004 */

+#define RTC_SCR_CWUTF                RTC_SCR_CWUTF_Msk

+#define RTC_SCR_CALRBF_Pos           (1U)

+#define RTC_SCR_CALRBF_Msk           (0x1UL << RTC_SCR_CALRBF_Pos)              /*!< 0x00000002 */

+#define RTC_SCR_CALRBF               RTC_SCR_CALRBF_Msk

+#define RTC_SCR_CALRAF_Pos           (0U)

+#define RTC_SCR_CALRAF_Msk           (0x1UL << RTC_SCR_CALRAF_Pos)              /*!< 0x00000001 */

+#define RTC_SCR_CALRAF               RTC_SCR_CALRAF_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                     Tamper and backup register (TAMP)                      */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for TAMP_CR1 register  *****************/

+#define TAMP_CR1_TAMP1E_Pos          (0U)

+#define TAMP_CR1_TAMP1E_Msk          (0x1UL << TAMP_CR1_TAMP1E_Pos)            /*!< 0x00000001 */

+#define TAMP_CR1_TAMP1E              TAMP_CR1_TAMP1E_Msk

+#define TAMP_CR1_TAMP2E_Pos          (1U)

+#define TAMP_CR1_TAMP2E_Msk          (0x1UL << TAMP_CR1_TAMP2E_Pos)            /*!< 0x00000002 */

+#define TAMP_CR1_TAMP2E              TAMP_CR1_TAMP2E_Msk

+#define TAMP_CR1_TAMP3E_Pos          (2U)

+#define TAMP_CR1_TAMP3E_Msk          (0x1UL << TAMP_CR1_TAMP3E_Pos)            /*!< 0x00000004 */

+#define TAMP_CR1_TAMP3E              TAMP_CR1_TAMP3E_Msk

+#define TAMP_CR1_ITAMP1E_Pos         (16U)

+#define TAMP_CR1_ITAMP1E_Msk         (0x1UL << TAMP_CR1_ITAMP1E_Pos)           /*!< 0x00010000 */

+#define TAMP_CR1_ITAMP1E             TAMP_CR1_ITAMP1E_Msk

+#define TAMP_CR1_ITAMP2E_Pos         (17U)

+#define TAMP_CR1_ITAMP2E_Msk         (0x1UL << TAMP_CR1_ITAMP2E_Pos)           /*!< 0x00020000 */

+#define TAMP_CR1_ITAMP2E             TAMP_CR1_ITAMP2E_Msk

+#define TAMP_CR1_ITAMP3E_Pos         (18U)

+#define TAMP_CR1_ITAMP3E_Msk         (0x1UL << TAMP_CR1_ITAMP3E_Pos)           /*!< 0x00040000 */

+#define TAMP_CR1_ITAMP3E             TAMP_CR1_ITAMP3E_Msk

+#define TAMP_CR1_ITAMP4E_Pos         (19U)

+#define TAMP_CR1_ITAMP4E_Msk         (0x1UL << TAMP_CR1_ITAMP4E_Pos)           /*!< 0x00080000 */

+#define TAMP_CR1_ITAMP4E             TAMP_CR1_ITAMP4E_Msk

+#define TAMP_CR1_ITAMP5E_Pos         (20U)

+#define TAMP_CR1_ITAMP5E_Msk         (0x1UL << TAMP_CR1_ITAMP5E_Pos)           /*!< 0x00100000 */

+#define TAMP_CR1_ITAMP5E             TAMP_CR1_ITAMP5E_Msk

+#define TAMP_CR1_ITAMP6E_Pos         (21U)

+#define TAMP_CR1_ITAMP6E_Msk         (0x1UL << TAMP_CR1_ITAMP6E_Pos)           /*!< 0x00200000 */

+#define TAMP_CR1_ITAMP6E             TAMP_CR1_ITAMP6E_Msk

+#define TAMP_CR1_ITAMP8E_Pos         (23U)

+#define TAMP_CR1_ITAMP8E_Msk         (0x1UL << TAMP_CR1_ITAMP8E_Pos)           /*!< 0x00800000 */

+#define TAMP_CR1_ITAMP8E             TAMP_CR1_ITAMP8E_Msk

+

+/********************  Bits definition for TAMP_CR2 register  *****************/

+#define TAMP_CR2_TAMP1NOERASE_Pos    (0U)

+#define TAMP_CR2_TAMP1NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)      /*!< 0x00000001 */

+#define TAMP_CR2_TAMP1NOERASE        TAMP_CR2_TAMP1NOERASE_Msk

+#define TAMP_CR2_TAMP2NOERASE_Pos    (1U)

+#define TAMP_CR2_TAMP2NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)      /*!< 0x00000002 */

+#define TAMP_CR2_TAMP2NOERASE        TAMP_CR2_TAMP2NOERASE_Msk

+#define TAMP_CR2_TAMP3NOERASE_Pos    (2U)

+#define TAMP_CR2_TAMP3NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos)      /*!< 0x00000004 */

+#define TAMP_CR2_TAMP3NOERASE        TAMP_CR2_TAMP3NOERASE_Msk

+#define TAMP_CR2_TAMP1MSK_Pos        (16U)

+#define TAMP_CR2_TAMP1MSK_Msk        (0x1UL << TAMP_CR2_TAMP1MSK_Pos)          /*!< 0x00010000 */

+#define TAMP_CR2_TAMP1MSK            TAMP_CR2_TAMP1MSK_Msk

+#define TAMP_CR2_TAMP2MSK_Pos        (17U)

+#define TAMP_CR2_TAMP2MSK_Msk        (0x1UL << TAMP_CR2_TAMP2MSK_Pos)          /*!< 0x00020000 */

+#define TAMP_CR2_TAMP2MSK            TAMP_CR2_TAMP2MSK_Msk

+#define TAMP_CR2_TAMP3MSK_Pos        (18U)

+#define TAMP_CR2_TAMP3MSK_Msk        (0x1UL << TAMP_CR2_TAMP3MSK_Pos)          /*!< 0x00040000 */

+#define TAMP_CR2_TAMP3MSK            TAMP_CR2_TAMP3MSK_Msk

+#define TAMP_CR2_TAMP1TRG_Pos        (24U)

+#define TAMP_CR2_TAMP1TRG_Msk        (0x1UL << TAMP_CR2_TAMP1TRG_Pos)          /*!< 0x01000000 */

+#define TAMP_CR2_TAMP1TRG            TAMP_CR2_TAMP1TRG_Msk

+#define TAMP_CR2_TAMP2TRG_Pos        (25U)

+#define TAMP_CR2_TAMP2TRG_Msk        (0x1UL << TAMP_CR2_TAMP2TRG_Pos)          /*!< 0x02000000 */

+#define TAMP_CR2_TAMP2TRG            TAMP_CR2_TAMP2TRG_Msk

+#define TAMP_CR2_TAMP3TRG_Pos        (26U)

+#define TAMP_CR2_TAMP3TRG_Msk        (0x1UL << TAMP_CR2_TAMP3TRG_Pos)          /*!< 0x04000000 */

+#define TAMP_CR2_TAMP3TRG            TAMP_CR2_TAMP3TRG_Msk

+

+/********************  Bits definition for TAMP_FLTCR register  ***************/

+#define TAMP_FLTCR_TAMPFREQ_Pos      (0U)

+#define TAMP_FLTCR_TAMPFREQ_Msk      (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000007 */

+#define TAMP_FLTCR_TAMPFREQ          TAMP_FLTCR_TAMPFREQ_Msk

+#define TAMP_FLTCR_TAMPFREQ_0        (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000001 */

+#define TAMP_FLTCR_TAMPFREQ_1        (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000002 */

+#define TAMP_FLTCR_TAMPFREQ_2        (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000004 */

+#define TAMP_FLTCR_TAMPFLT_Pos       (3U)

+#define TAMP_FLTCR_TAMPFLT_Msk       (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000018 */

+#define TAMP_FLTCR_TAMPFLT           TAMP_FLTCR_TAMPFLT_Msk

+#define TAMP_FLTCR_TAMPFLT_0         (0x1UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000008 */

+#define TAMP_FLTCR_TAMPFLT_1         (0x2UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000010 */

+#define TAMP_FLTCR_TAMPPRCH_Pos      (5U)

+#define TAMP_FLTCR_TAMPPRCH_Msk      (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000060 */

+#define TAMP_FLTCR_TAMPPRCH          TAMP_FLTCR_TAMPPRCH_Msk

+#define TAMP_FLTCR_TAMPPRCH_0        (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000020 */

+#define TAMP_FLTCR_TAMPPRCH_1        (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000040 */

+#define TAMP_FLTCR_TAMPPUDIS_Pos     (7U)

+#define TAMP_FLTCR_TAMPPUDIS_Msk     (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)        /*!< 0x00000080 */

+#define TAMP_FLTCR_TAMPPUDIS         TAMP_FLTCR_TAMPPUDIS_Msk

+

+/*******************  Bits definition for TAMP_ATCR1 register  ****************/

+#define TAMP_ATCR1_TAMP1AM_Pos       (0U)

+#define TAMP_ATCR1_TAMP1AM_Msk       (0x1UL << TAMP_ATCR1_TAMP1AM_Pos)         /*!< 0x00000001 */

+#define TAMP_ATCR1_TAMP1AM           TAMP_ATCR1_TAMP1AM_Msk

+#define TAMP_ATCR1_TAMP2AM_Pos       (1U)

+#define TAMP_ATCR1_TAMP2AM_Msk       (0x1UL << TAMP_ATCR1_TAMP2AM_Pos)         /*!< 0x00000002 */

+#define TAMP_ATCR1_TAMP2AM           TAMP_ATCR1_TAMP2AM_Msk

+#define TAMP_ATCR1_TAMP3AM_Pos       (2U)

+#define TAMP_ATCR1_TAMP3AM_Msk       (0x1UL << TAMP_ATCR1_TAMP3AM_Pos)         /*!< 0x00000004 */

+#define TAMP_ATCR1_TAMP3AM           TAMP_ATCR1_TAMP3AM_Msk

+#define TAMP_ATCR1_ATOSEL1_Pos       (8U)

+#define TAMP_ATCR1_ATOSEL1_Msk       (0x3UL << TAMP_ATCR1_ATOSEL1_Pos)          /*!< 0x00000300 */

+#define TAMP_ATCR1_ATOSEL1            TAMP_ATCR1_ATOSEL1_Msk

+#define TAMP_ATCR1_ATOSEL1_0         (0x1UL << TAMP_ATCR1_ATOSEL1_Pos)         /*!< 0x00000100 */

+#define TAMP_ATCR1_ATOSEL1_1         (0x2UL << TAMP_ATCR1_ATOSEL1_Pos)         /*!< 0x00000200 */

+#define TAMP_ATCR1_ATOSEL2_Pos       (10U)

+#define TAMP_ATCR1_ATOSEL2_Msk       (0x3UL << TAMP_ATCR1_ATOSEL2_Pos)          /*!< 0x00000C00 */

+#define TAMP_ATCR1_ATOSEL2            TAMP_ATCR1_ATOSEL2_Msk

+#define TAMP_ATCR1_ATOSEL2_0         (0x1UL << TAMP_ATCR1_ATOSEL2_Pos)         /*!< 0x00000400 */

+#define TAMP_ATCR1_ATOSEL2_1         (0x2UL << TAMP_ATCR1_ATOSEL2_Pos)         /*!< 0x00000800 */

+#define TAMP_ATCR1_ATOSEL3_Pos       (12U)

+#define TAMP_ATCR1_ATOSEL3_Msk       (0x3UL << TAMP_ATCR1_ATOSEL3_Pos)          /*!< 0x00003000 */

+#define TAMP_ATCR1_ATOSEL3            TAMP_ATCR1_ATOSEL3_Msk

+#define TAMP_ATCR1_ATOSEL3_0         (0x1UL << TAMP_ATCR1_ATOSEL3_Pos)         /*!< 0x00001000 */

+#define TAMP_ATCR1_ATOSEL3_1         (0x2UL << TAMP_ATCR1_ATOSEL3_Pos)         /*!< 0x00002000 */

+#define TAMP_ATCR1_ATOSEL4_Pos       (14U)

+#define TAMP_ATCR1_ATOSEL4_Msk       (0x3UL << TAMP_ATCR1_ATOSEL4_Pos)          /*!< 0x0000C000 */

+#define TAMP_ATCR1_ATOSEL4            TAMP_ATCR1_ATOSEL4_Msk

+#define TAMP_ATCR1_ATOSEL4_0         (0x1UL << TAMP_ATCR1_ATOSEL4_Pos)         /*!< 0x00004000 */

+#define TAMP_ATCR1_ATOSEL4_1         (0x2UL << TAMP_ATCR1_ATOSEL4_Pos)         /*!< 0x00008000 */

+#define TAMP_ATCR1_ATCKSEL_Pos       (16U)

+#define TAMP_ATCR1_ATCKSEL_Msk       (0x7UL << TAMP_ATCR1_ATCKSEL_Pos)          /*!< 0x00070000 */

+#define TAMP_ATCR1_ATCKSEL            TAMP_ATCR1_ATCKSEL_Msk

+#define TAMP_ATCR1_ATCKSEL_0         (0x1UL << TAMP_ATCR1_ATCKSEL_Pos)         /*!< 0x00010000 */

+#define TAMP_ATCR1_ATCKSEL_1         (0x2UL << TAMP_ATCR1_ATCKSEL_Pos)         /*!< 0x00020000 */

+#define TAMP_ATCR1_ATCKSEL_2         (0x4UL << TAMP_ATCR1_ATCKSEL_Pos)         /*!< 0x00040000 */

+#define TAMP_ATCR1_ATPER_Pos         (24U)

+#define TAMP_ATCR1_ATPER_Msk         (0x7UL << TAMP_ATCR1_ATPER_Pos)           /*!< 0x07000000 */

+#define TAMP_ATCR1_ATPER             TAMP_ATCR1_ATPER_Msk

+#define TAMP_ATCR1_ATOSHARE_Pos      (30U)

+#define TAMP_ATCR1_ATOSHARE_Msk      (0x1UL << TAMP_ATCR1_ATOSHARE_Pos)        /*!< 0x40000000 */

+#define TAMP_ATCR1_ATOSHARE          TAMP_ATCR1_ATOSHARE_Msk

+#define TAMP_ATCR1_FLTEN_Pos         (31U)

+#define TAMP_ATCR1_FLTEN_Msk         (0x1UL << TAMP_ATCR1_FLTEN_Pos)           /*!< 0x80000000 */

+#define TAMP_ATCR1_FLTEN             TAMP_ATCR1_FLTEN_Msk

+

+/********************  Bits definition for TAMP_ATSEEDR register  *************/

+#define TAMP_ATSEEDR_SEED_Pos        (0U)

+#define TAMP_ATSEEDR_SEED_Msk        (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos)   /*!< 0xFFFFFFFF */

+#define TAMP_ATSEEDR_SEED            TAMP_ATSEEDR_SEED_Msk

+

+/********************  Bits definition for TAMP_ATOR register  ****************/

+#define TAMP_ATOR_PRNG_Pos           (0U)

+#define TAMP_ATOR_PRNG_Msk           (0x000000FFUL << TAMP_ATOR_PRNG_Pos)      /*!< 0x000000FF */

+#define TAMP_ATOR_PRNG               TAMP_ATOR_PRNG_Msk

+#define TAMP_ATOR_SEEDF_Pos          (14U)

+#define TAMP_ATOR_SEEDF_Msk          (0x01UL << TAMP_ATOR_SEEDF_Pos)           /*!< 0x00004000 */

+#define TAMP_ATOR_SEEDF              TAMP_ATOR_SEEDF_Msk

+#define TAMP_ATOR_INITS_Pos          (15U)

+#define TAMP_ATOR_INITS_Msk          (0x01UL << TAMP_ATOR_INITS_Pos)           /*!< 0x00008000 */

+#define TAMP_ATOR_INITS              TAMP_ATOR_INITS_Msk

+

+/********************  Bits definition for TAMP_IER register  *****************/

+#define TAMP_IER_TAMP1IE_Pos         (0U)

+#define TAMP_IER_TAMP1IE_Msk         (0x1UL << TAMP_IER_TAMP1IE_Pos)           /*!< 0x00000001 */

+#define TAMP_IER_TAMP1IE             TAMP_IER_TAMP1IE_Msk

+#define TAMP_IER_TAMP2IE_Pos         (1U)

+#define TAMP_IER_TAMP2IE_Msk         (0x1UL << TAMP_IER_TAMP2IE_Pos)           /*!< 0x00000002 */

+#define TAMP_IER_TAMP2IE             TAMP_IER_TAMP2IE_Msk

+#define TAMP_IER_TAMP3IE_Pos         (2U)

+#define TAMP_IER_TAMP3IE_Msk         (0x1UL << TAMP_IER_TAMP3IE_Pos)           /*!< 0x00000004 */

+#define TAMP_IER_TAMP3IE             TAMP_IER_TAMP3IE_Msk

+#define TAMP_IER_ITAMP1IE_Pos        (16U)

+#define TAMP_IER_ITAMP1IE_Msk        (0x1UL << TAMP_IER_ITAMP1IE_Pos)          /*!< 0x00010000 */

+#define TAMP_IER_ITAMP1IE            TAMP_IER_ITAMP1IE_Msk

+#define TAMP_IER_ITAMP2IE_Pos        (17U)

+#define TAMP_IER_ITAMP2IE_Msk        (0x1UL << TAMP_IER_ITAMP2IE_Pos)          /*!< 0x00020000 */

+#define TAMP_IER_ITAMP2IE            TAMP_IER_ITAMP2IE_Msk

+#define TAMP_IER_ITAMP3IE_Pos        (18U)

+#define TAMP_IER_ITAMP3IE_Msk        (0x1UL << TAMP_IER_ITAMP3IE_Pos)          /*!< 0x00040000 */

+#define TAMP_IER_ITAMP3IE            TAMP_IER_ITAMP3IE_Msk

+#define TAMP_IER_ITAMP4IE_Pos        (19U)

+#define TAMP_IER_ITAMP4IE_Msk        (0x1UL << TAMP_IER_ITAMP4IE_Pos)          /*!< 0x00080000 */

+#define TAMP_IER_ITAMP4IE            TAMP_IER_ITAMP4IE_Msk

+#define TAMP_IER_ITAMP5IE_Pos        (20U)

+#define TAMP_IER_ITAMP5IE_Msk        (0x1UL << TAMP_IER_ITAMP5IE_Pos)          /*!< 0x00100000 */

+#define TAMP_IER_ITAMP5IE            TAMP_IER_ITAMP5IE_Msk

+#define TAMP_IER_ITAMP6IE_Pos        (21U)

+#define TAMP_IER_ITAMP6IE_Msk        (0x1UL << TAMP_IER_ITAMP6IE_Pos)          /*!< 0x00200000 */

+#define TAMP_IER_ITAMP6IE            TAMP_IER_ITAMP6IE_Msk

+#define TAMP_IER_ITAMP8IE_Pos        (23U)

+#define TAMP_IER_ITAMP8IE_Msk        (0x1UL << TAMP_IER_ITAMP8IE_Pos)          /*!< 0x00800000 */

+#define TAMP_IER_ITAMP8IE            TAMP_IER_ITAMP8IE_Msk

+

+/********************  Bits definition for TAMP_SR register  *****************/

+#define TAMP_SR_TAMP1F_Pos           (0U)

+#define TAMP_SR_TAMP1F_Msk           (0x1UL << TAMP_SR_TAMP1F_Pos)             /*!< 0x00000001 */

+#define TAMP_SR_TAMP1F               TAMP_SR_TAMP1F_Msk

+#define TAMP_SR_TAMP2F_Pos           (1U)

+#define TAMP_SR_TAMP2F_Msk           (0x1UL << TAMP_SR_TAMP2F_Pos)             /*!< 0x00000002 */

+#define TAMP_SR_TAMP2F               TAMP_SR_TAMP2F_Msk

+#define TAMP_SR_TAMP3F_Pos           (2U)

+#define TAMP_SR_TAMP3F_Msk           (0x1UL << TAMP_SR_TAMP3F_Pos)             /*!< 0x00000004 */

+#define TAMP_SR_TAMP3F               TAMP_SR_TAMP3F_Msk

+#define TAMP_SR_ITAMP1F_Pos          (16U)

+#define TAMP_SR_ITAMP1F_Msk          (0x1UL << TAMP_SR_ITAMP1F_Pos)            /*!< 0x00010000 */

+#define TAMP_SR_ITAMP1F              TAMP_SR_ITAMP1F_Msk

+#define TAMP_SR_ITAMP2F_Pos          (17U)

+#define TAMP_SR_ITAMP2F_Msk          (0x1UL << TAMP_SR_ITAMP2F_Pos)            /*!< 0x00020000 */

+#define TAMP_SR_ITAMP2F              TAMP_SR_ITAMP2F_Msk

+#define TAMP_SR_ITAMP3F_Pos          (18U)

+#define TAMP_SR_ITAMP3F_Msk          (0x1UL << TAMP_SR_ITAMP3F_Pos)            /*!< 0x00040000 */

+#define TAMP_SR_ITAMP3F              TAMP_SR_ITAMP3F_Msk

+#define TAMP_SR_ITAMP4F_Pos          (19U)

+#define TAMP_SR_ITAMP4F_Msk          (0x1UL << TAMP_SR_ITAMP4F_Pos)            /*!< 0x00080000 */

+#define TAMP_SR_ITAMP4F              TAMP_SR_ITAMP4F_Msk

+#define TAMP_SR_ITAMP5F_Pos          (20U)

+#define TAMP_SR_ITAMP5F_Msk          (0x1UL << TAMP_SR_ITAMP5F_Pos)            /*!< 0x00100000 */

+#define TAMP_SR_ITAMP5F              TAMP_SR_ITAMP5F_Msk

+#define TAMP_SR_ITAMP6F_Pos          (21U)

+#define TAMP_SR_ITAMP6F_Msk          (0x1UL << TAMP_SR_ITAMP6F_Pos)            /*!< 0x00200000 */

+#define TAMP_SR_ITAMP6F              TAMP_SR_ITAMP6F_Msk

+#define TAMP_SR_ITAMP8F_Pos          (23U)

+#define TAMP_SR_ITAMP8F_Msk          (0x1UL << TAMP_SR_ITAMP8F_Pos)            /*!< 0x00800000 */

+#define TAMP_SR_ITAMP8F              TAMP_SR_ITAMP8F_Msk

+

+/********************  Bits definition for TAMP_MISR register  ************ *****/

+#define TAMP_MISR_TAMP1MF_Pos        (0U)

+#define TAMP_MISR_TAMP1MF_Msk        (0x1UL << TAMP_MISR_TAMP1MF_Pos)           /*!< 0x00000001 */

+#define TAMP_MISR_TAMP1MF            TAMP_MISR_TAMP1MF_Msk

+#define TAMP_MISR_TAMP2MF_Pos        (1U)

+#define TAMP_MISR_TAMP2MF_Msk        (0x1UL << TAMP_MISR_TAMP2MF_Pos)           /*!< 0x00000002 */

+#define TAMP_MISR_TAMP2MF            TAMP_MISR_TAMP2MF_Msk

+#define TAMP_MISR_TAMP3MF_Pos        (2U)

+#define TAMP_MISR_TAMP3MF_Msk        (0x1UL << TAMP_MISR_TAMP3MF_Pos)          /*!< 0x00000004 */

+#define TAMP_MISR_TAMP3MF            TAMP_MISR_TAMP3MF_Msk

+#define TAMP_MISR_ITAMP1MF_Pos       (16U)

+#define TAMP_MISR_ITAMP1MF_Msk       (0x1UL << TAMP_MISR_ITAMP1MF_Pos)         /*!< 0x00010000 */

+#define TAMP_MISR_ITAMP1MF           TAMP_MISR_ITAMP1MF_Msk

+#define TAMP_MISR_ITAMP2MF_Pos       (17U)

+#define TAMP_MISR_ITAMP2MF_Msk       (0x1UL << TAMP_MISR_ITAMP2MF_Pos)         /*!< 0x00020000 */

+#define TAMP_MISR_ITAMP2MF           TAMP_MISR_ITAMP2MF_Msk

+#define TAMP_MISR_ITAMP3MF_Pos       (18U)

+#define TAMP_MISR_ITAMP3MF_Msk       (0x1UL << TAMP_MISR_ITAMP3MF_Pos)         /*!< 0x00040000 */

+#define TAMP_MISR_ITAMP3MF           TAMP_MISR_ITAMP3MF_Msk

+#define TAMP_MISR_ITAMP4MF_Pos       (19U)

+#define TAMP_MISR_ITAMP4MF_Msk       (0x1UL << TAMP_MISR_ITAMP4MF_Pos)         /*!< 0x00080000 */

+#define TAMP_MISR_ITAMP4MF           TAMP_MISR_ITAMP4MF_Msk

+#define TAMP_MISR_ITAMP5MF_Pos       (20U)

+#define TAMP_MISR_ITAMP5MF_Msk       (0x1UL << TAMP_MISR_ITAMP5MF_Pos)         /*!< 0x00100000 */

+#define TAMP_MISR_ITAMP5MF           TAMP_MISR_ITAMP5MF_Msk

+#define TAMP_MISR_ITAMP6MF_Pos       (21U)

+#define TAMP_MISR_ITAMP6MF_Msk       (0x1UL << TAMP_MISR_ITAMP6MF_Pos)         /*!< 0x00200000 */

+#define TAMP_MISR_ITAMP6MF           TAMP_MISR_ITAMP6MF_Msk

+#define TAMP_MISR_ITAMP8MF_Pos       (23U)

+#define TAMP_MISR_ITAMP8MF_Msk       (0x1UL << TAMP_MISR_ITAMP8MF_Pos)         /*!< 0x00800000 */

+#define TAMP_MISR_ITAMP8MF           TAMP_MISR_ITAMP8MF_Msk

+

+/********************  Bits definition for TAMP_SCR register  *****************/

+#define TAMP_SCR_CTAMP1F_Pos         (0U)

+#define TAMP_SCR_CTAMP1F_Msk         (0x1UL << TAMP_SCR_CTAMP1F_Pos)            /*!< 0x00000001 */

+#define TAMP_SCR_CTAMP1F             TAMP_SCR_CTAMP1F_Msk

+#define TAMP_SCR_CTAMP2F_Pos         (1U)

+#define TAMP_SCR_CTAMP2F_Msk         (0x1UL << TAMP_SCR_CTAMP2F_Pos)            /*!< 0x00000002 */

+#define TAMP_SCR_CTAMP2F             TAMP_SCR_CTAMP2F_Msk

+#define TAMP_SCR_CTAMP3F_Pos         (2U)

+#define TAMP_SCR_CTAMP3F_Msk         (0x1UL << TAMP_SCR_CTAMP3F_Pos)           /*!< 0x00000004 */

+#define TAMP_SCR_CTAMP3F             TAMP_SCR_CTAMP3F_Msk

+#define TAMP_SCR_CITAMP1F_Pos        (16U)

+#define TAMP_SCR_CITAMP1F_Msk        (0x1UL << TAMP_SCR_CITAMP1F_Pos)          /*!< 0x00010000 */

+#define TAMP_SCR_CITAMP1F            TAMP_SCR_CITAMP1F_Msk

+#define TAMP_SCR_CITAMP2F_Pos        (17U)

+#define TAMP_SCR_CITAMP2F_Msk        (0x1UL << TAMP_SCR_CITAMP2F_Pos)          /*!< 0x00020000 */

+#define TAMP_SCR_CITAMP2F            TAMP_SCR_CITAMP2F_Msk

+#define TAMP_SCR_CITAMP3F_Pos        (18U)

+#define TAMP_SCR_CITAMP3F_Msk        (0x1UL << TAMP_SCR_CITAMP3F_Pos)          /*!< 0x00040000 */

+#define TAMP_SCR_CITAMP3F            TAMP_SCR_CITAMP3F_Msk

+#define TAMP_SCR_CITAMP4F_Pos        (19U)

+#define TAMP_SCR_CITAMP4F_Msk        (0x1UL << TAMP_SCR_CITAMP4F_Pos)          /*!< 0x00080000 */

+#define TAMP_SCR_CITAMP4F            TAMP_SCR_CITAMP4F_Msk

+#define TAMP_SCR_CITAMP5F_Pos        (20U)

+#define TAMP_SCR_CITAMP5F_Msk        (0x1UL << TAMP_SCR_CITAMP5F_Pos)          /*!< 0x00100000 */

+#define TAMP_SCR_CITAMP5F            TAMP_SCR_CITAMP5F_Msk

+#define TAMP_SCR_CITAMP6F_Pos        (21U)

+#define TAMP_SCR_CITAMP6F_Msk        (0x1UL << TAMP_SCR_CITAMP6F_Pos)          /*!< 0x00200000 */

+#define TAMP_SCR_CITAMP6F            TAMP_SCR_CITAMP6F_Msk

+#define TAMP_SCR_CITAMP8F_Pos        (23U)

+#define TAMP_SCR_CITAMP8F_Msk        (0x1UL << TAMP_SCR_CITAMP8F_Pos)          /*!< 0x00800000 */

+#define TAMP_SCR_CITAMP8F            TAMP_SCR_CITAMP8F_Msk

+

+/********************  Bits definition for TAMP_COUNTR register  **************/

+#define TAMP_COUNTR_Pos              (16U)

+#define TAMP_COUNTR_Msk              (0xFFFFUL << TAMP_COUNTR_Pos)             /*!< 0xFFFF0000 */

+#define TAMP_COUNTR                  TAMP_COUNTR_Msk

+

+/********************  Bits definition for TAMP_OR register  ******************/

+#define TAMP_OR_OUT3_RMP_Pos         (0U)

+#define TAMP_OR_OUT3_RMP_Msk         (0x1UL << TAMP_OR_OUT3_RMP_Pos)           /*!< 0x00000001 */

+#define TAMP_OR_OUT3_RMP             TAMP_OR_OUT3_RMP_Msk

+

+/********************  Bits definition for TAMP_BKP0R register  ***************/

+#define TAMP_BKP0R_Pos               (0U)

+#define TAMP_BKP0R_Msk               (0xFFFFFFFFUL << TAMP_BKP0R_Pos)           /*!< 0xFFFFFFFF */

+#define TAMP_BKP0R                   TAMP_BKP0R_Msk

+

+/********************  Bits definition for TAMP_BKP1R register  ****************/

+#define TAMP_BKP1R_Pos               (0U)

+#define TAMP_BKP1R_Msk               (0xFFFFFFFFUL << TAMP_BKP1R_Pos)           /*!< 0xFFFFFFFF */

+#define TAMP_BKP1R                   TAMP_BKP1R_Msk

+

+/********************  Bits definition for TAMP_BKP2R register  ****************/

+#define TAMP_BKP2R_Pos               (0U)

+#define TAMP_BKP2R_Msk               (0xFFFFFFFFUL << TAMP_BKP2R_Pos)           /*!< 0xFFFFFFFF */

+#define TAMP_BKP2R                   TAMP_BKP2R_Msk

+

+/********************  Bits definition for TAMP_BKP3R register  ****************/

+#define TAMP_BKP3R_Pos               (0U)

+#define TAMP_BKP3R_Msk               (0xFFFFFFFFUL << TAMP_BKP3R_Pos)           /*!< 0xFFFFFFFF */

+#define TAMP_BKP3R                   TAMP_BKP3R_Msk

+

+/********************  Bits definition for TAMP_BKP4R register  ****************/

+#define TAMP_BKP4R_Pos               (0U)

+#define TAMP_BKP4R_Msk               (0xFFFFFFFFUL << TAMP_BKP4R_Pos)           /*!< 0xFFFFFFFF */

+#define TAMP_BKP4R                   TAMP_BKP4R_Msk

+

+/********************  Bits definition for TAMP_BKP5R register  ****************/

+#define TAMP_BKP5R_Pos               (0U)

+#define TAMP_BKP5R_Msk               (0xFFFFFFFFUL << TAMP_BKP5R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP5R                   TAMP_BKP5R_Msk

+

+/********************  Bits definition for TAMP_BKP6R register  ****************/

+#define TAMP_BKP6R_Pos               (0U)

+#define TAMP_BKP6R_Msk               (0xFFFFFFFFUL << TAMP_BKP6R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP6R                   TAMP_BKP6R_Msk

+

+/********************  Bits definition for TAMP_BKP7R register  ****************/

+#define TAMP_BKP7R_Pos               (0U)

+#define TAMP_BKP7R_Msk               (0xFFFFFFFFUL << TAMP_BKP7R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP7R                   TAMP_BKP7R_Msk

+

+/********************  Bits definition for TAMP_BKP8R register  ****************/

+#define TAMP_BKP8R_Pos               (0U)

+#define TAMP_BKP8R_Msk               (0xFFFFFFFFUL << TAMP_BKP8R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP8R                   TAMP_BKP8R_Msk

+

+/********************  Bits definition for TAMP_BKP9R register  ****************/

+#define TAMP_BKP9R_Pos               (0U)

+#define TAMP_BKP9R_Msk               (0xFFFFFFFFUL << TAMP_BKP9R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP9R                   TAMP_BKP9R_Msk

+

+/********************  Bits definition for TAMP_BKP10R register  ***************/

+#define TAMP_BKP10R_Pos              (0U)

+#define TAMP_BKP10R_Msk              (0xFFFFFFFFUL << TAMP_BKP10R_Pos)         /*!< 0xFFFFFFFF */

+#define TAMP_BKP10R                  TAMP_BKP10R_Msk

+

+/********************  Bits definition for TAMP_BKP11R register  ***************/

+#define TAMP_BKP11R_Pos              (0U)

+#define TAMP_BKP11R_Msk              (0xFFFFFFFFUL << TAMP_BKP11R_Pos)         /*!< 0xFFFFFFFF */

+#define TAMP_BKP11R                  TAMP_BKP11R_Msk

+

+/********************  Bits definition for TAMP_BKP12R register  ***************/

+#define TAMP_BKP12R_Pos              (0U)

+#define TAMP_BKP12R_Msk              (0xFFFFFFFFUL << TAMP_BKP12R_Pos)         /*!< 0xFFFFFFFF */

+#define TAMP_BKP12R                  TAMP_BKP12R_Msk

+

+/********************  Bits definition for TAMP_BKP13R register  ***************/

+#define TAMP_BKP13R_Pos              (0U)

+#define TAMP_BKP13R_Msk              (0xFFFFFFFFUL << TAMP_BKP13R_Pos)         /*!< 0xFFFFFFFF */

+#define TAMP_BKP13R                  TAMP_BKP13R_Msk

+

+/********************  Bits definition for TAMP_BKP14R register  ***************/

+#define TAMP_BKP14R_Pos              (0U)

+#define TAMP_BKP14R_Msk              (0xFFFFFFFFUL << TAMP_BKP14R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP14R                  TAMP_BKP14R_Msk

+

+/********************  Bits definition for TAMP_BKP15R register  ***************/

+#define TAMP_BKP15R_Pos              (0U)

+#define TAMP_BKP15R_Msk              (0xFFFFFFFFUL << TAMP_BKP15R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP15R                  TAMP_BKP15R_Msk

+

+/********************  Bits definition for TAMP_BKP16R register  ***************/

+#define TAMP_BKP16R_Pos              (0U)

+#define TAMP_BKP16R_Msk              (0xFFFFFFFFUL << TAMP_BKP16R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP16R                  TAMP_BKP16R_Msk

+

+/********************  Bits definition for TAMP_BKP17R register  ***************/

+#define TAMP_BKP17R_Pos              (0U)

+#define TAMP_BKP17R_Msk              (0xFFFFFFFFUL << TAMP_BKP17R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP17R                  TAMP_BKP17R_Msk

+

+/********************  Bits definition for TAMP_BKP18R register  ***************/

+#define TAMP_BKP18R_Pos              (0U)

+#define TAMP_BKP18R_Msk              (0xFFFFFFFFUL << TAMP_BKP18R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP18R                  TAMP_BKP18R_Msk

+

+/********************  Bits definition for TAMP_BKP19R register  ***************/

+#define TAMP_BKP19R_Pos              (0U)

+#define TAMP_BKP19R_Msk              (0xFFFFFFFFUL << TAMP_BKP19R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP19R                  TAMP_BKP19R_Msk

+

+/********************  Bits definition for TAMP_BKP20R register  ***************/

+#define TAMP_BKP20R_Pos              (0U)

+#define TAMP_BKP20R_Msk              (0xFFFFFFFFUL << TAMP_BKP20R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP20R                  TAMP_BKP20R_Msk

+

+/********************  Bits definition for TAMP_BKP21R register  ***************/

+#define TAMP_BKP21R_Pos              (0U)

+#define TAMP_BKP21R_Msk              (0xFFFFFFFFUL << TAMP_BKP21R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP21R                  TAMP_BKP21R_Msk

+

+/********************  Bits definition for TAMP_BKP22R register  ***************/

+#define TAMP_BKP22R_Pos              (0U)

+#define TAMP_BKP22R_Msk              (0xFFFFFFFFUL << TAMP_BKP22R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP22R                  TAMP_BKP22R_Msk

+

+/********************  Bits definition for TAMP_BKP23R register  ***************/

+#define TAMP_BKP23R_Pos              (0U)

+#define TAMP_BKP23R_Msk              (0xFFFFFFFFUL << TAMP_BKP23R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP23R                  TAMP_BKP23R_Msk

+

+/********************  Bits definition for TAMP_BKP24R register  ***************/

+#define TAMP_BKP24R_Pos              (0U)

+#define TAMP_BKP24R_Msk              (0xFFFFFFFFUL << TAMP_BKP24R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP24R                  TAMP_BKP24R_Msk

+

+/********************  Bits definition for TAMP_BKP25R register  ***************/

+#define TAMP_BKP25R_Pos              (0U)

+#define TAMP_BKP25R_Msk              (0xFFFFFFFFUL << TAMP_BKP25R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP25R                  TAMP_BKP25R_Msk

+

+/********************  Bits definition for TAMP_BKP26R register  ***************/

+#define TAMP_BKP26R_Pos              (0U)

+#define TAMP_BKP26R_Msk              (0xFFFFFFFFUL << TAMP_BKP26R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP26R                  TAMP_BKP26R_Msk

+

+/********************  Bits definition for TAMP_BKP27R register  ***************/

+#define TAMP_BKP27R_Pos              (0U)

+#define TAMP_BKP27R_Msk              (0xFFFFFFFFUL << TAMP_BKP27R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP27R                  TAMP_BKP27R_Msk

+

+/********************  Bits definition for TAMP_BKP28R register  ***************/

+#define TAMP_BKP28R_Pos              (0U)

+#define TAMP_BKP28R_Msk              (0xFFFFFFFFUL << TAMP_BKP28R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP28R                  TAMP_BKP28R_Msk

+

+/********************  Bits definition for TAMP_BKP29R register  ***************/

+#define TAMP_BKP29R_Pos              (0U)

+#define TAMP_BKP29R_Msk              (0xFFFFFFFFUL << TAMP_BKP29R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP29R                  TAMP_BKP29R_Msk

+

+/********************  Bits definition for TAMP_BKP30R register  ***************/

+#define TAMP_BKP30R_Pos              (0U)

+#define TAMP_BKP30R_Msk              (0xFFFFFFFFUL << TAMP_BKP30R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP30R                  TAMP_BKP30R_Msk

+

+/********************  Bits definition for TAMP_BKP31R register  ***************/

+#define TAMP_BKP31R_Pos              (0U)

+#define TAMP_BKP31R_Msk              (0xFFFFFFFFUL << TAMP_BKP31R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP31R                  TAMP_BKP31R_Msk

+

+/******************** Number of backup registers ******************************/

+#define TAMP_BKP_NUMBER_Pos             (5U)

+#define TAMP_BKP_NUMBER_Msk             (0x1UL << TAMP_BKP_NUMBER_Pos)         /*!< 0x00000080 */

+#define TAMP_BKP_NUMBER                 TAMP_BKP_NUMBER_Msk                    /*!< 32 BKPREG  */

+

+/******************************************************************************/

+/*                                                                            */

+/*                              SPDIF-RX Interface                            */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for SPDIF_CR register  ******************/

+#define SPDIFRX_CR_SPDIFEN_Pos      (0U)

+#define SPDIFRX_CR_SPDIFEN_Msk      (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)          /*!< 0x00000003 */

+#define SPDIFRX_CR_SPDIFEN          SPDIFRX_CR_SPDIFEN_Msk                     /*!<Peripheral Block Enable                      */

+#define SPDIFRX_CR_RXDMAEN_Pos      (2U)

+#define SPDIFRX_CR_RXDMAEN_Msk      (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)          /*!< 0x00000004 */

+#define SPDIFRX_CR_RXDMAEN          SPDIFRX_CR_RXDMAEN_Msk                     /*!<Receiver DMA Enable for data flow            */

+#define SPDIFRX_CR_RXSTEO_Pos       (3U)

+#define SPDIFRX_CR_RXSTEO_Msk       (0x1UL << SPDIFRX_CR_RXSTEO_Pos)           /*!< 0x00000008 */

+#define SPDIFRX_CR_RXSTEO           SPDIFRX_CR_RXSTEO_Msk                      /*!<Stereo Mode                                  */

+#define SPDIFRX_CR_DRFMT_Pos        (4U)

+#define SPDIFRX_CR_DRFMT_Msk        (0x3UL << SPDIFRX_CR_DRFMT_Pos)            /*!< 0x00000030 */

+#define SPDIFRX_CR_DRFMT            SPDIFRX_CR_DRFMT_Msk                       /*!<RX Data format                               */

+#define SPDIFRX_CR_PMSK_Pos         (6U)

+#define SPDIFRX_CR_PMSK_Msk         (0x1UL << SPDIFRX_CR_PMSK_Pos)             /*!< 0x00000040 */

+#define SPDIFRX_CR_PMSK             SPDIFRX_CR_PMSK_Msk                        /*!<Mask Parity error bit                        */

+#define SPDIFRX_CR_VMSK_Pos         (7U)

+#define SPDIFRX_CR_VMSK_Msk         (0x1UL << SPDIFRX_CR_VMSK_Pos)             /*!< 0x00000080 */

+#define SPDIFRX_CR_VMSK             SPDIFRX_CR_VMSK_Msk                        /*!<Mask of Validity bit                         */

+#define SPDIFRX_CR_CUMSK_Pos        (8U)

+#define SPDIFRX_CR_CUMSK_Msk        (0x1UL << SPDIFRX_CR_CUMSK_Pos)            /*!< 0x00000100 */

+#define SPDIFRX_CR_CUMSK            SPDIFRX_CR_CUMSK_Msk                       /*!<Mask of channel status and user bits         */

+#define SPDIFRX_CR_PTMSK_Pos        (9U)

+#define SPDIFRX_CR_PTMSK_Msk        (0x1UL << SPDIFRX_CR_PTMSK_Pos)            /*!< 0x00000200 */

+#define SPDIFRX_CR_PTMSK            SPDIFRX_CR_PTMSK_Msk                       /*!<Mask of Preamble Type bits                   */

+#define SPDIFRX_CR_CBDMAEN_Pos      (10U)

+#define SPDIFRX_CR_CBDMAEN_Msk      (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)          /*!< 0x00000400 */

+#define SPDIFRX_CR_CBDMAEN          SPDIFRX_CR_CBDMAEN_Msk                     /*!<Control Buffer DMA ENable for control flow   */

+#define SPDIFRX_CR_CHSEL_Pos        (11U)

+#define SPDIFRX_CR_CHSEL_Msk        (0x1UL << SPDIFRX_CR_CHSEL_Pos)            /*!< 0x00000800 */

+#define SPDIFRX_CR_CHSEL            SPDIFRX_CR_CHSEL_Msk                       /*!<Channel Selection                            */

+#define SPDIFRX_CR_NBTR_Pos         (12U)

+#define SPDIFRX_CR_NBTR_Msk         (0x3UL << SPDIFRX_CR_NBTR_Pos)             /*!< 0x00003000 */

+#define SPDIFRX_CR_NBTR             SPDIFRX_CR_NBTR_Msk                        /*!<Maximum allowed re-tries during synchronization phase */

+#define SPDIFRX_CR_WFA_Pos          (14U)

+#define SPDIFRX_CR_WFA_Msk          (0x1UL << SPDIFRX_CR_WFA_Pos)              /*!< 0x00004000 */

+#define SPDIFRX_CR_WFA              SPDIFRX_CR_WFA_Msk                         /*!<Wait For Activity     */

+#define SPDIFRX_CR_INSEL_Pos        (16U)

+#define SPDIFRX_CR_INSEL_Msk        (0x7UL << SPDIFRX_CR_INSEL_Pos)            /*!< 0x00070000 */

+#define SPDIFRX_CR_INSEL            SPDIFRX_CR_INSEL_Msk                       /*!<SPDIF input selection */

+#define SPDIFRX_CR_CKSEN_Pos        (20U)

+#define SPDIFRX_CR_CKSEN_Msk        (0x1UL << SPDIFRX_CR_CKSEN_Pos)            /*!< 0x00100000 */

+#define SPDIFRX_CR_CKSEN            SPDIFRX_CR_CKSEN_Msk                       /*!<Symbol Clock Enable */

+#define SPDIFRX_CR_CKSBKPEN_Pos     (21U)

+#define SPDIFRX_CR_CKSBKPEN_Msk     (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)         /*!< 0x00200000 */

+#define SPDIFRX_CR_CKSBKPEN         SPDIFRX_CR_CKSBKPEN_Msk                    /*!<Backup Symbol Clock Enable */

+

+/*******************  Bit definition for SPDIFRX_IMR register  *******************/

+#define SPDIFRX_IMR_RXNEIE_Pos      (0U)

+#define SPDIFRX_IMR_RXNEIE_Msk      (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)          /*!< 0x00000001 */

+#define SPDIFRX_IMR_RXNEIE          SPDIFRX_IMR_RXNEIE_Msk                     /*!<RXNE interrupt enable                              */

+#define SPDIFRX_IMR_CSRNEIE_Pos     (1U)

+#define SPDIFRX_IMR_CSRNEIE_Msk     (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)         /*!< 0x00000002 */

+#define SPDIFRX_IMR_CSRNEIE         SPDIFRX_IMR_CSRNEIE_Msk                    /*!<Control Buffer Ready Interrupt Enable              */

+#define SPDIFRX_IMR_PERRIE_Pos      (2U)

+#define SPDIFRX_IMR_PERRIE_Msk      (0x1UL << SPDIFRX_IMR_PERRIE_Pos)          /*!< 0x00000004 */

+#define SPDIFRX_IMR_PERRIE          SPDIFRX_IMR_PERRIE_Msk                     /*!<Parity error interrupt enable                      */

+#define SPDIFRX_IMR_OVRIE_Pos       (3U)

+#define SPDIFRX_IMR_OVRIE_Msk       (0x1UL << SPDIFRX_IMR_OVRIE_Pos)           /*!< 0x00000008 */

+#define SPDIFRX_IMR_OVRIE           SPDIFRX_IMR_OVRIE_Msk                      /*!<Overrun error Interrupt Enable                     */

+#define SPDIFRX_IMR_SBLKIE_Pos      (4U)

+#define SPDIFRX_IMR_SBLKIE_Msk      (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)          /*!< 0x00000010 */

+#define SPDIFRX_IMR_SBLKIE          SPDIFRX_IMR_SBLKIE_Msk                     /*!<Synchronization Block Detected Interrupt Enable    */

+#define SPDIFRX_IMR_SYNCDIE_Pos     (5U)

+#define SPDIFRX_IMR_SYNCDIE_Msk     (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)         /*!< 0x00000020 */

+#define SPDIFRX_IMR_SYNCDIE         SPDIFRX_IMR_SYNCDIE_Msk                    /*!<Synchronization Done                               */

+#define SPDIFRX_IMR_IFEIE_Pos       (6U)

+#define SPDIFRX_IMR_IFEIE_Msk       (0x1UL << SPDIFRX_IMR_IFEIE_Pos)           /*!< 0x00000040 */

+#define SPDIFRX_IMR_IFEIE           SPDIFRX_IMR_IFEIE_Msk                      /*!<Serial Interface Error Interrupt Enable            */

+

+/*******************  Bit definition for SPDIFRX_SR register  *******************/

+#define SPDIFRX_SR_RXNE_Pos         (0U)

+#define SPDIFRX_SR_RXNE_Msk         (0x1UL << SPDIFRX_SR_RXNE_Pos)             /*!< 0x00000001 */

+#define SPDIFRX_SR_RXNE             SPDIFRX_SR_RXNE_Msk                        /*!<Read data register not empty                          */

+#define SPDIFRX_SR_CSRNE_Pos        (1U)

+#define SPDIFRX_SR_CSRNE_Msk        (0x1UL << SPDIFRX_SR_CSRNE_Pos)            /*!< 0x00000002 */

+#define SPDIFRX_SR_CSRNE            SPDIFRX_SR_CSRNE_Msk                       /*!<The Control Buffer register is not empty              */

+#define SPDIFRX_SR_PERR_Pos         (2U)

+#define SPDIFRX_SR_PERR_Msk         (0x1UL << SPDIFRX_SR_PERR_Pos)             /*!< 0x00000004 */

+#define SPDIFRX_SR_PERR             SPDIFRX_SR_PERR_Msk                        /*!<Parity error                                          */

+#define SPDIFRX_SR_OVR_Pos          (3U)

+#define SPDIFRX_SR_OVR_Msk          (0x1UL << SPDIFRX_SR_OVR_Pos)              /*!< 0x00000008 */

+#define SPDIFRX_SR_OVR              SPDIFRX_SR_OVR_Msk                         /*!<Overrun error                                         */

+#define SPDIFRX_SR_SBD_Pos          (4U)

+#define SPDIFRX_SR_SBD_Msk          (0x1UL << SPDIFRX_SR_SBD_Pos)              /*!< 0x00000010 */

+#define SPDIFRX_SR_SBD              SPDIFRX_SR_SBD_Msk                         /*!<Synchronization Block Detected                        */

+#define SPDIFRX_SR_SYNCD_Pos        (5U)

+#define SPDIFRX_SR_SYNCD_Msk        (0x1UL << SPDIFRX_SR_SYNCD_Pos)            /*!< 0x00000020 */

+#define SPDIFRX_SR_SYNCD            SPDIFRX_SR_SYNCD_Msk                       /*!<Synchronization Done                                  */

+#define SPDIFRX_SR_FERR_Pos         (6U)

+#define SPDIFRX_SR_FERR_Msk         (0x1UL << SPDIFRX_SR_FERR_Pos)             /*!< 0x00000040 */

+#define SPDIFRX_SR_FERR             SPDIFRX_SR_FERR_Msk                        /*!<Framing error                                         */

+#define SPDIFRX_SR_SERR_Pos         (7U)

+#define SPDIFRX_SR_SERR_Msk         (0x1UL << SPDIFRX_SR_SERR_Pos)             /*!< 0x00000080 */

+#define SPDIFRX_SR_SERR             SPDIFRX_SR_SERR_Msk                        /*!<Synchronization error                                 */

+#define SPDIFRX_SR_TERR_Pos         (8U)

+#define SPDIFRX_SR_TERR_Msk         (0x1UL << SPDIFRX_SR_TERR_Pos)             /*!< 0x00000100 */

+#define SPDIFRX_SR_TERR             SPDIFRX_SR_TERR_Msk                        /*!<Time-out error                                        */

+#define SPDIFRX_SR_WIDTH5_Pos       (16U)

+#define SPDIFRX_SR_WIDTH5_Msk       (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)        /*!< 0x7FFF0000 */

+#define SPDIFRX_SR_WIDTH5           SPDIFRX_SR_WIDTH5_Msk                      /*!<Duration of 5 symbols counted with spdif_clk          */

+

+/*******************  Bit definition for SPDIFRX_IFCR register  *******************/

+#define SPDIFRX_IFCR_PERRCF_Pos     (2U)

+#define SPDIFRX_IFCR_PERRCF_Msk     (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)         /*!< 0x00000004 */

+#define SPDIFRX_IFCR_PERRCF         SPDIFRX_IFCR_PERRCF_Msk                    /*!<Clears the Parity error flag                         */

+#define SPDIFRX_IFCR_OVRCF_Pos      (3U)

+#define SPDIFRX_IFCR_OVRCF_Msk      (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)          /*!< 0x00000008 */

+#define SPDIFRX_IFCR_OVRCF          SPDIFRX_IFCR_OVRCF_Msk                     /*!<Clears the Overrun error flag                        */

+#define SPDIFRX_IFCR_SBDCF_Pos      (4U)

+#define SPDIFRX_IFCR_SBDCF_Msk      (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)          /*!< 0x00000010 */

+#define SPDIFRX_IFCR_SBDCF          SPDIFRX_IFCR_SBDCF_Msk                     /*!<Clears the Synchronization Block Detected flag       */

+#define SPDIFRX_IFCR_SYNCDCF_Pos    (5U)

+#define SPDIFRX_IFCR_SYNCDCF_Msk    (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)        /*!< 0x00000020 */

+#define SPDIFRX_IFCR_SYNCDCF        SPDIFRX_IFCR_SYNCDCF_Msk                   /*!<Clears the Synchronization Done flag                 */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/

+#define SPDIFRX_DR0_DR_Pos          (0U)

+#define SPDIFRX_DR0_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)         /*!< 0x00FFFFFF */

+#define SPDIFRX_DR0_DR              SPDIFRX_DR0_DR_Msk                         /*!<Data value            */

+#define SPDIFRX_DR0_PE_Pos          (24U)

+#define SPDIFRX_DR0_PE_Msk          (0x1UL << SPDIFRX_DR0_PE_Pos)              /*!< 0x01000000 */

+#define SPDIFRX_DR0_PE              SPDIFRX_DR0_PE_Msk                         /*!<Parity Error bit      */

+#define SPDIFRX_DR0_V_Pos           (25U)

+#define SPDIFRX_DR0_V_Msk           (0x1UL << SPDIFRX_DR0_V_Pos)               /*!< 0x02000000 */

+#define SPDIFRX_DR0_V               SPDIFRX_DR0_V_Msk                          /*!<Validity bit          */

+#define SPDIFRX_DR0_U_Pos           (26U)

+#define SPDIFRX_DR0_U_Msk           (0x1UL << SPDIFRX_DR0_U_Pos)               /*!< 0x04000000 */

+#define SPDIFRX_DR0_U               SPDIFRX_DR0_U_Msk                          /*!<User bit              */

+#define SPDIFRX_DR0_C_Pos           (27U)

+#define SPDIFRX_DR0_C_Msk           (0x1UL << SPDIFRX_DR0_C_Pos)               /*!< 0x08000000 */

+#define SPDIFRX_DR0_C               SPDIFRX_DR0_C_Msk                          /*!<Channel Status bit    */

+#define SPDIFRX_DR0_PT_Pos          (28U)

+#define SPDIFRX_DR0_PT_Msk          (0x3UL << SPDIFRX_DR0_PT_Pos)              /*!< 0x30000000 */

+#define SPDIFRX_DR0_PT              SPDIFRX_DR0_PT_Msk                         /*!<Preamble Type         */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/

+#define SPDIFRX_DR1_DR_Pos          (8U)

+#define SPDIFRX_DR1_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)         /*!< 0xFFFFFF00 */

+#define SPDIFRX_DR1_DR              SPDIFRX_DR1_DR_Msk                         /*!<Data value            */

+#define SPDIFRX_DR1_PT_Pos          (4U)

+#define SPDIFRX_DR1_PT_Msk          (0x3UL << SPDIFRX_DR1_PT_Pos)              /*!< 0x00000030 */

+#define SPDIFRX_DR1_PT              SPDIFRX_DR1_PT_Msk                         /*!<Preamble Type         */

+#define SPDIFRX_DR1_C_Pos           (3U)

+#define SPDIFRX_DR1_C_Msk           (0x1UL << SPDIFRX_DR1_C_Pos)               /*!< 0x00000008 */

+#define SPDIFRX_DR1_C               SPDIFRX_DR1_C_Msk                          /*!<Channel Status bit    */

+#define SPDIFRX_DR1_U_Pos           (2U)

+#define SPDIFRX_DR1_U_Msk           (0x1UL << SPDIFRX_DR1_U_Pos)               /*!< 0x00000004 */

+#define SPDIFRX_DR1_U               SPDIFRX_DR1_U_Msk                          /*!<User bit              */

+#define SPDIFRX_DR1_V_Pos           (1U)

+#define SPDIFRX_DR1_V_Msk           (0x1UL << SPDIFRX_DR1_V_Pos)               /*!< 0x00000002 */

+#define SPDIFRX_DR1_V               SPDIFRX_DR1_V_Msk                          /*!<Validity bit          */

+#define SPDIFRX_DR1_PE_Pos          (0U)

+#define SPDIFRX_DR1_PE_Msk          (0x1UL << SPDIFRX_DR1_PE_Pos)              /*!< 0x00000001 */

+#define SPDIFRX_DR1_PE              SPDIFRX_DR1_PE_Msk                         /*!<Parity Error bit      */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/

+#define SPDIFRX_DR1_DRNL1_Pos       (16U)

+#define SPDIFRX_DR1_DRNL1_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)        /*!< 0xFFFF0000 */

+#define SPDIFRX_DR1_DRNL1           SPDIFRX_DR1_DRNL1_Msk                      /*!<Data value Channel B      */

+#define SPDIFRX_DR1_DRNL2_Pos       (0U)

+#define SPDIFRX_DR1_DRNL2_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)        /*!< 0x0000FFFF */

+#define SPDIFRX_DR1_DRNL2           SPDIFRX_DR1_DRNL2_Msk                      /*!<Data value Channel A      */

+

+/*******************  Bit definition for SPDIFRX_CSR register   *******************/

+#define SPDIFRX_CSR_USR_Pos         (0U)

+#define SPDIFRX_CSR_USR_Msk         (0xFFFFUL << SPDIFRX_CSR_USR_Pos)          /*!< 0x0000FFFF */

+#define SPDIFRX_CSR_USR             SPDIFRX_CSR_USR_Msk                        /*!<User data information           */

+#define SPDIFRX_CSR_CS_Pos          (16U)

+#define SPDIFRX_CSR_CS_Msk          (0xFFUL << SPDIFRX_CSR_CS_Pos)             /*!< 0x00FF0000 */

+#define SPDIFRX_CSR_CS              SPDIFRX_CSR_CS_Msk                         /*!<Channel A status information    */

+#define SPDIFRX_CSR_SOB_Pos         (24U)

+#define SPDIFRX_CSR_SOB_Msk         (0x1UL << SPDIFRX_CSR_SOB_Pos)             /*!< 0x01000000 */

+#define SPDIFRX_CSR_SOB             SPDIFRX_CSR_SOB_Msk                        /*!<Start Of Block                  */

+

+/*******************  Bit definition for SPDIFRX_DIR register    *******************/

+#define SPDIFRX_DIR_THI_Pos         (0U)

+#define SPDIFRX_DIR_THI_Msk         (0x1FFFUL << SPDIFRX_DIR_THI_Pos)          /*!< 0x00001FFF */

+#define SPDIFRX_DIR_THI             SPDIFRX_DIR_THI_Msk                        /*!<Threshold LOW      */

+#define SPDIFRX_DIR_TLO_Pos         (16U)

+#define SPDIFRX_DIR_TLO_Msk         (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)          /*!< 0x1FFF0000 */

+#define SPDIFRX_DIR_TLO             SPDIFRX_DIR_TLO_Msk                        /*!<Threshold HIGH     */

+

+/*******************  Bit definition for SPDIFRX_VERR register    *******************/

+#define SPDIFRX_VERR_MINREV_Pos     (0U)

+#define SPDIFRX_VERR_MINREV_Msk     (0xFUL << SPDIFRX_VERR_MINREV_Pos)         /*!< 0x0000000F */

+#define SPDIFRX_VERR_MINREV         SPDIFRX_VERR_MINREV_Msk                    /*!<SPDIFRX Minor revision     */

+#define SPDIFRX_VERR_MAJREV_Pos     (4U)

+#define SPDIFRX_VERR_MAJREV_Msk     (0xFUL << SPDIFRX_VERR_MAJREV_Pos)         /*!< 0x000000F0 */

+#define SPDIFRX_VERR_MAJREV         SPDIFRX_VERR_MAJREV_Msk                    /*!<SPDIFRX Major revision     */

+

+/*******************  Bit definition for SPDIFRX_IDR register    *******************/

+#define SPDIFRX_IDR_ID_Pos          (0U)

+#define SPDIFRX_IDR_ID_Msk          (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos)       /*!< 0xFFFFFFFF */

+#define SPDIFRX_IDR_ID              SPDIFRX_IDR_ID_Msk                         /*!<SPDIFRX identifier     */

+

+/*******************  Bit definition for SPDIFRX_SIDR register    *******************/

+#define SPDIFRX_SIDR_SID_Pos        (0U)

+#define SPDIFRX_SIDR_SID_Msk        (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos)     /*!< 0xFFFFFFFF */

+#define SPDIFRX_SIDR_SID            SPDIFRX_SIDR_SID_Msk                       /*!<Size of the memory region allocated to SPDIFRX registers */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          Serial Audio Interface                            */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  SAI VERSION  ********************************/

+#define SAI_VER_V2_1

+

+/********************  Bit definition for SAI_GCR register  *******************/

+#define SAI_GCR_SYNCIN_Pos         (0U)

+#define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000003 */

+#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */

+#define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */

+#define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */

+

+#define SAI_GCR_SYNCOUT_Pos        (4U)

+#define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000030 */

+#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */

+#define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */

+#define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */

+

+/*******************  Bit definition for SAI_xCR1 register  *******************/

+#define SAI_xCR1_MODE_Pos          (0U)

+#define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */

+#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */

+#define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */

+#define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */

+

+#define SAI_xCR1_PRTCFG_Pos        (2U)

+#define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */

+#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */

+#define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */

+#define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */

+

+#define SAI_xCR1_DS_Pos            (5U)

+#define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */

+#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */

+#define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */

+#define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */

+#define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */

+

+#define SAI_xCR1_LSBFIRST_Pos      (8U)

+#define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */

+#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */

+#define SAI_xCR1_CKSTR_Pos         (9U)

+#define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */

+#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */

+

+#define SAI_xCR1_SYNCEN_Pos        (10U)

+#define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */

+#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */

+#define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */

+#define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */

+

+#define SAI_xCR1_MONO_Pos          (12U)

+#define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */

+#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */

+#define SAI_xCR1_OUTDRIV_Pos       (13U)

+#define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */

+#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */

+#define SAI_xCR1_SAIEN_Pos         (16U)

+#define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */

+#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */

+#define SAI_xCR1_DMAEN_Pos         (17U)

+#define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */

+#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */

+#define SAI_xCR1_NODIV_Pos         (19U)

+#define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */

+#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */

+

+#define SAI_xCR1_MCKDIV_Pos        (20U)

+#define SAI_xCR1_MCKDIV_Msk        (0x3FUL << SAI_xCR1_MCKDIV_Pos)             /*!< 0x03F00000 */

+#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[5:0] (Master ClocK Divider)  */

+#define SAI_xCR1_MCKDIV_0          (0x01UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00100000 */

+#define SAI_xCR1_MCKDIV_1          (0x02UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00200000 */

+#define SAI_xCR1_MCKDIV_2          (0x04UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00400000 */

+#define SAI_xCR1_MCKDIV_3          (0x08UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00800000 */

+#define SAI_xCR1_MCKDIV_4          (0x10UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x01000000 */

+#define SAI_xCR1_MCKDIV_5          (0x20UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x02000000 */

+

+#define SAI_xCR1_MCKEN_Pos         (27U)

+#define SAI_xCR1_MCKEN_Msk         (0x1UL << SAI_xCR1_MCKEN_Pos)               /*!< 0x08000000 */

+#define SAI_xCR1_MCKEN             SAI_xCR1_MCKEN_Msk                          /*!<Master ClocK enable */

+

+#define SAI_xCR1_OSR_Pos           (26U)

+#define SAI_xCR1_OSR_Msk           (0x1UL << SAI_xCR1_OSR_Pos)                 /*!< 0x04000000 */

+#define SAI_xCR1_OSR               SAI_xCR1_OSR_Msk                            /*!<OverSampling Ratio for master clock  */

+

+/* Legacy define */

+#define  SAI_xCR1_NOMCK               SAI_xCR1_NODIV

+

+/*******************  Bit definition for SAI_xCR2 register  *******************/

+#define SAI_xCR2_FTH_Pos           (0U)

+#define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */

+#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */

+#define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */

+#define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */

+#define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */

+

+#define SAI_xCR2_FFLUSH_Pos        (3U)

+#define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */

+#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */

+#define SAI_xCR2_TRIS_Pos          (4U)

+#define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */

+#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */

+#define SAI_xCR2_MUTE_Pos          (5U)

+#define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */

+#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */

+#define SAI_xCR2_MUTEVAL_Pos       (6U)

+#define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */

+#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */

+

+#define SAI_xCR2_MUTECNT_Pos       (7U)

+#define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */

+#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */

+#define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */

+#define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */

+#define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */

+#define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */

+#define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */

+#define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */

+

+#define SAI_xCR2_CPL_Pos           (13U)

+#define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */

+#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */

+

+#define SAI_xCR2_COMP_Pos          (14U)

+#define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */

+#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */

+#define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */

+#define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */

+

+/******************  Bit definition for SAI_xFRCR register  *******************/

+#define SAI_xFRCR_FRL_Pos          (0U)

+#define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */

+#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](FRame Length)  */

+#define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */

+#define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */

+#define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */

+#define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */

+#define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */

+#define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */

+#define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */

+#define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */

+

+#define SAI_xFRCR_FSALL_Pos        (8U)

+#define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */

+#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FSALL[6:0] (Frame Synchronization Active Level Length)  */

+#define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */

+#define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */

+#define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */

+#define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */

+#define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */

+#define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */

+#define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */

+

+#define SAI_xFRCR_FSDEF_Pos        (16U)

+#define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */

+#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!<Frame Synchronization Definition  */

+#define SAI_xFRCR_FSPOL_Pos        (17U)

+#define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */

+#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */

+#define SAI_xFRCR_FSOFF_Pos        (18U)

+#define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */

+#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */

+

+/* Legacy define */

+#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL

+

+/******************  Bit definition for SAI_xSLOTR register  *******************/

+#define SAI_xSLOTR_FBOFF_Pos       (0U)

+#define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */

+#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FBOFF[4:0](First Bit Offset)  */

+#define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */

+#define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */

+#define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */

+#define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */

+#define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */

+

+#define SAI_xSLOTR_SLOTSZ_Pos      (6U)

+#define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */

+#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */

+#define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */

+#define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */

+

+#define SAI_xSLOTR_NBSLOT_Pos      (8U)

+#define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */

+#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */

+#define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */

+#define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */

+#define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */

+#define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */

+

+#define SAI_xSLOTR_SLOTEN_Pos      (16U)

+#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */

+#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */

+

+/*******************  Bit definition for SAI_xIMR register  *******************/

+#define SAI_xIMR_OVRUDRIE_Pos      (0U)

+#define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */

+#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */

+#define SAI_xIMR_MUTEDETIE_Pos     (1U)

+#define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */

+#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */

+#define SAI_xIMR_WCKCFGIE_Pos      (2U)

+#define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */

+#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */

+#define SAI_xIMR_FREQIE_Pos        (3U)

+#define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */

+#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */

+#define SAI_xIMR_CNRDYIE_Pos       (4U)

+#define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */

+#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */

+#define SAI_xIMR_AFSDETIE_Pos      (5U)

+#define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */

+#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */

+#define SAI_xIMR_LFSDETIE_Pos      (6U)

+#define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */

+#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */

+

+/********************  Bit definition for SAI_xSR register  *******************/

+#define SAI_xSR_OVRUDR_Pos         (0U)

+#define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */

+#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */

+#define SAI_xSR_MUTEDET_Pos        (1U)

+#define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */

+#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */

+#define SAI_xSR_WCKCFG_Pos         (2U)

+#define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */

+#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */

+#define SAI_xSR_FREQ_Pos           (3U)

+#define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */

+#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */

+#define SAI_xSR_CNRDY_Pos          (4U)

+#define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */

+#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */

+#define SAI_xSR_AFSDET_Pos         (5U)

+#define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */

+#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */

+#define SAI_xSR_LFSDET_Pos         (6U)

+#define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */

+#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */

+

+#define SAI_xSR_FLVL_Pos           (16U)

+#define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */

+#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */

+#define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */

+#define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */

+#define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */

+

+/******************  Bit definition for SAI_xCLRFR register  ******************/

+#define SAI_xCLRFR_COVRUDR_Pos     (0U)

+#define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */

+#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */

+#define SAI_xCLRFR_CMUTEDET_Pos    (1U)

+#define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */

+#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */

+#define SAI_xCLRFR_CWCKCFG_Pos     (2U)

+#define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */

+#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */

+#define SAI_xCLRFR_CFREQ_Pos       (3U)

+#define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */

+#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */

+#define SAI_xCLRFR_CCNRDY_Pos      (4U)

+#define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */

+#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */

+#define SAI_xCLRFR_CAFSDET_Pos     (5U)

+#define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */

+#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */

+#define SAI_xCLRFR_CLFSDET_Pos     (6U)

+#define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */

+#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */

+

+/******************  Bit definition for SAI_xDR register  *********************/

+#define SAI_xDR_DATA_Pos           (0U)

+#define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */

+#define SAI_xDR_DATA               SAI_xDR_DATA_Msk

+

+/*******************  Bit definition for SAI_PDMCR register  ******************/

+#define SAI_PDMCR_PDMEN_Pos        (0U)

+#define SAI_PDMCR_PDMEN_Msk        (0x1UL << SAI_PDMCR_PDMEN_Pos)              /*!< 0x00000001 */

+#define SAI_PDMCR_PDMEN            SAI_PDMCR_PDMEN_Msk                         /*!<PDM Enable                                          */

+

+#define SAI_PDMCR_MICNBR_Pos       (4U)

+#define SAI_PDMCR_MICNBR_Msk       (0x3UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000030 */

+#define SAI_PDMCR_MICNBR           SAI_PDMCR_MICNBR_Msk                        /*!<Number of microphones                               */

+#define SAI_PDMCR_MICNBR_0         (0x1UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000010 */

+#define SAI_PDMCR_MICNBR_1         (0x2UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000020 */

+

+#define SAI_PDMCR_CKEN1_Pos        (8U)

+#define SAI_PDMCR_CKEN1_Msk        (0x1UL << SAI_PDMCR_CKEN1_Pos)              /*!< 0x00000100 */

+#define SAI_PDMCR_CKEN1            SAI_PDMCR_CKEN1_Msk                         /*!<Clock enable of bitstream clock number 1            */

+#define SAI_PDMCR_CKEN2_Pos        (9U)

+#define SAI_PDMCR_CKEN2_Msk        (0x1UL << SAI_PDMCR_CKEN2_Pos)              /*!< 0x00000200 */

+#define SAI_PDMCR_CKEN2            SAI_PDMCR_CKEN2_Msk                         /*!<Clock enable of bitstream clock number 2            */

+#define SAI_PDMCR_CKEN3_Pos        (10U)

+#define SAI_PDMCR_CKEN3_Msk        (0x1UL << SAI_PDMCR_CKEN3_Pos)              /*!< 0x00000400 */

+#define SAI_PDMCR_CKEN3            SAI_PDMCR_CKEN3_Msk                         /*!<Clock enable of bitstream clock number 3            */

+#define SAI_PDMCR_CKEN4_Pos        (11U)

+#define SAI_PDMCR_CKEN4_Msk        (0x1UL << SAI_PDMCR_CKEN4_Pos)              /*!< 0x00000800 */

+#define SAI_PDMCR_CKEN4            SAI_PDMCR_CKEN4_Msk                         /*!<Clock enable of bitstream clock number 4            */

+

+/******************  Bit definition for SAI_PDMDLY register  ******************/

+#define SAI_PDMDLY_DLYM1L_Pos      (0U)

+#define SAI_PDMDLY_DLYM1L_Msk      (0x7UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000007 */

+#define SAI_PDMDLY_DLYM1L          SAI_PDMDLY_DLYM1L_Msk                       /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */

+#define SAI_PDMDLY_DLYM1L_0        (0x1UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000001 */

+#define SAI_PDMDLY_DLYM1L_1        (0x2UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000002 */

+#define SAI_PDMDLY_DLYM1L_2        (0x4UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000004 */

+

+#define SAI_PDMDLY_DLYM1R_Pos      (4U)

+#define SAI_PDMDLY_DLYM1R_Msk      (0x7UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000070 */

+#define SAI_PDMDLY_DLYM1R          SAI_PDMDLY_DLYM1R_Msk                       /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */

+#define SAI_PDMDLY_DLYM1R_0        (0x1UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000010 */

+#define SAI_PDMDLY_DLYM1R_1        (0x2UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000020 */

+#define SAI_PDMDLY_DLYM1R_2        (0x4UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000040 */

+

+#define SAI_PDMDLY_DLYM2L_Pos      (8U)

+#define SAI_PDMDLY_DLYM2L_Msk      (0x7UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000700 */

+#define SAI_PDMDLY_DLYM2L          SAI_PDMDLY_DLYM2L_Msk                       /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */

+#define SAI_PDMDLY_DLYM2L_0        (0x1UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000100 */

+#define SAI_PDMDLY_DLYM2L_1        (0x2UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000200 */

+#define SAI_PDMDLY_DLYM2L_2        (0x4UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000400 */

+

+#define SAI_PDMDLY_DLYM2R_Pos      (12U)

+#define SAI_PDMDLY_DLYM2R_Msk      (0x7UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00007000 */

+#define SAI_PDMDLY_DLYM2R          SAI_PDMDLY_DLYM2R_Msk                       /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/

+#define SAI_PDMDLY_DLYM2R_0        (0x1UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00001000 */

+#define SAI_PDMDLY_DLYM2R_1        (0x2UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00002000 */

+#define SAI_PDMDLY_DLYM2R_2        (0x4UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00004000 */

+

+#define SAI_PDMDLY_DLYM3L_Pos      (16U)

+#define SAI_PDMDLY_DLYM3L_Msk      (0x7UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00070000 */

+#define SAI_PDMDLY_DLYM3L          SAI_PDMDLY_DLYM3L_Msk                       /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/

+#define SAI_PDMDLY_DLYM3L_0        (0x1UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00010000 */

+#define SAI_PDMDLY_DLYM3L_1        (0x2UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00020000 */

+#define SAI_PDMDLY_DLYM3L_2        (0x4UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00040000 */

+

+#define SAI_PDMDLY_DLYM3R_Pos      (20U)

+#define SAI_PDMDLY_DLYM3R_Msk      (0x7UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00700000 */

+#define SAI_PDMDLY_DLYM3R          SAI_PDMDLY_DLYM3R_Msk                       /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/

+#define SAI_PDMDLY_DLYM3R_0        (0x1UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00100000 */

+#define SAI_PDMDLY_DLYM3R_1        (0x2UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00200000 */

+#define SAI_PDMDLY_DLYM3R_2        (0x4UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00400000 */

+

+#define SAI_PDMDLY_DLYM4L_Pos      (24U)

+#define SAI_PDMDLY_DLYM4L_Msk      (0x7UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x07000000 */

+#define SAI_PDMDLY_DLYM4L          SAI_PDMDLY_DLYM4L_Msk                       /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/

+#define SAI_PDMDLY_DLYM4L_0        (0x1UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x01000000 */

+#define SAI_PDMDLY_DLYM4L_1        (0x2UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x02000000 */

+#define SAI_PDMDLY_DLYM4L_2        (0x4UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x04000000 */

+

+#define SAI_PDMDLY_DLYM4R_Pos      (28U)

+#define SAI_PDMDLY_DLYM4R_Msk      (0x7UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x70000000 */

+#define SAI_PDMDLY_DLYM4R          SAI_PDMDLY_DLYM4R_Msk                       /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/

+#define SAI_PDMDLY_DLYM4R_0        (0x1UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x10000000 */

+#define SAI_PDMDLY_DLYM4R_1        (0x2UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x20000000 */

+#define SAI_PDMDLY_DLYM4R_2        (0x4UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x40000000 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           SDMMC Interface                                  */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for SDMMC_POWER register  ******************/

+#define SDMMC_POWER_PWRCTRL_Pos          (0U)

+#define SDMMC_POWER_PWRCTRL_Msk          (0x3UL << SDMMC_POWER_PWRCTRL_Pos)    /*!< 0x00000003 */

+#define SDMMC_POWER_PWRCTRL              SDMMC_POWER_PWRCTRL_Msk               /*!<PWRCTRL[1:0] bits (Power supply control bits) */

+#define SDMMC_POWER_PWRCTRL_0            (0x1UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000001 */

+#define SDMMC_POWER_PWRCTRL_1            (0x2UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000002 */

+#define SDMMC_POWER_VSWITCH_Pos          (2U)

+#define SDMMC_POWER_VSWITCH_Msk          (0x1UL << SDMMC_POWER_VSWITCH_Pos)    /*!< 0x00000004 */

+#define SDMMC_POWER_VSWITCH              SDMMC_POWER_VSWITCH_Msk               /*!<Voltage switch sequence start */

+#define SDMMC_POWER_VSWITCHEN_Pos        (3U)

+#define SDMMC_POWER_VSWITCHEN_Msk        (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)  /*!< 0x00000008 */

+#define SDMMC_POWER_VSWITCHEN            SDMMC_POWER_VSWITCHEN_Msk             /*!<Voltage switch procedure enable */

+#define SDMMC_POWER_DIRPOL_Pos           (4U)

+#define SDMMC_POWER_DIRPOL_Msk           (0x1UL << SDMMC_POWER_DIRPOL_Pos)     /*!< 0x00000010 */

+#define SDMMC_POWER_DIRPOL               SDMMC_POWER_DIRPOL_Msk                /*!<Data and Command direction signals polarity selection */

+

+/******************  Bit definition for SDMMC_CLKCR register  ******************/

+#define SDMMC_CLKCR_CLKDIV_Pos           (0U)

+#define SDMMC_CLKCR_CLKDIV_Msk           (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)   /*!< 0x000003FF */

+#define SDMMC_CLKCR_CLKDIV               SDMMC_CLKCR_CLKDIV_Msk                /*!<Clock divide factor             */

+#define SDMMC_CLKCR_PWRSAV_Pos           (12U)

+#define SDMMC_CLKCR_PWRSAV_Msk           (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)     /*!< 0x00001000 */

+#define SDMMC_CLKCR_PWRSAV               SDMMC_CLKCR_PWRSAV_Msk                /*!<Power saving configuration bit  */

+

+#define SDMMC_CLKCR_WIDBUS_Pos           (14U)

+#define SDMMC_CLKCR_WIDBUS_Msk           (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)     /*!< 0x0000C000 */

+#define SDMMC_CLKCR_WIDBUS               SDMMC_CLKCR_WIDBUS_Msk                /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */

+#define SDMMC_CLKCR_WIDBUS_0             (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00004000 */

+#define SDMMC_CLKCR_WIDBUS_1             (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00008000 */

+

+#define SDMMC_CLKCR_NEGEDGE_Pos          (16U)

+#define SDMMC_CLKCR_NEGEDGE_Msk          (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)    /*!< 0x00010000 */

+#define SDMMC_CLKCR_NEGEDGE              SDMMC_CLKCR_NEGEDGE_Msk               /*!<SDMMC_CK dephasing selection bit */

+#define SDMMC_CLKCR_HWFC_EN_Pos          (17U)

+#define SDMMC_CLKCR_HWFC_EN_Msk          (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)    /*!< 0x00020000 */

+#define SDMMC_CLKCR_HWFC_EN              SDMMC_CLKCR_HWFC_EN_Msk               /*!<HW Flow Control enable           */

+#define SDMMC_CLKCR_DDR_Pos              (18U)

+#define SDMMC_CLKCR_DDR_Msk              (0x1UL << SDMMC_CLKCR_DDR_Pos)        /*!< 0x00040000 */

+#define SDMMC_CLKCR_DDR                  SDMMC_CLKCR_DDR_Msk                   /*!<Data rate signaling selection    */

+#define SDMMC_CLKCR_BUSSPEED_Pos         (19U)

+#define SDMMC_CLKCR_BUSSPEED_Msk         (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)   /*!< 0x00080000 */

+#define SDMMC_CLKCR_BUSSPEED             SDMMC_CLKCR_BUSSPEED_Msk              /*!<Bus speed mode selection         */

+#define SDMMC_CLKCR_SELCLKRX_Pos         (20U)

+#define SDMMC_CLKCR_SELCLKRX_Msk         (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)   /*!< 0x00300000 */

+#define SDMMC_CLKCR_SELCLKRX             SDMMC_CLKCR_SELCLKRX_Msk              /*!<SELCLKRX[1:0] bits (Receive clock selection) */

+#define SDMMC_CLKCR_SELCLKRX_0           (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00100000 */

+#define SDMMC_CLKCR_SELCLKRX_1           (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00200000 */

+

+/*******************  Bit definition for SDMMC_ARG register  *******************/

+#define SDMMC_ARG_CMDARG_Pos             (0U)

+#define SDMMC_ARG_CMDARG_Msk             (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_ARG_CMDARG                 SDMMC_ARG_CMDARG_Msk                  /*!<Command argument */

+

+/*******************  Bit definition for SDMMC_CMD register  *******************/

+#define SDMMC_CMD_CMDINDEX_Pos           (0U)

+#define SDMMC_CMD_CMDINDEX_Msk           (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)    /*!< 0x0000003F */

+#define SDMMC_CMD_CMDINDEX               SDMMC_CMD_CMDINDEX_Msk                /*!<Command Index                               */

+#define SDMMC_CMD_CMDTRANS_Pos           (6U)

+#define SDMMC_CMD_CMDTRANS_Msk           (0x1UL << SDMMC_CMD_CMDTRANS_Pos)     /*!< 0x00000040 */

+#define SDMMC_CMD_CMDTRANS               SDMMC_CMD_CMDTRANS_Msk                /*!<CPSM Treats command as a Data Transfer      */

+#define SDMMC_CMD_CMDSTOP_Pos            (7U)

+#define SDMMC_CMD_CMDSTOP_Msk            (0x1UL << SDMMC_CMD_CMDSTOP_Pos)      /*!< 0x00000080 */

+#define SDMMC_CMD_CMDSTOP                SDMMC_CMD_CMDSTOP_Msk                 /*!<CPSM Treats command as a Stop               */

+

+#define SDMMC_CMD_WAITRESP_Pos           (8U)

+#define SDMMC_CMD_WAITRESP_Msk           (0x3UL << SDMMC_CMD_WAITRESP_Pos)     /*!< 0x00000300 */

+#define SDMMC_CMD_WAITRESP               SDMMC_CMD_WAITRESP_Msk                /*!<WAITRESP[1:0] bits (Wait for response bits) */

+#define SDMMC_CMD_WAITRESP_0             (0x1UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000100 */

+#define SDMMC_CMD_WAITRESP_1             (0x2UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000200 */

+

+#define SDMMC_CMD_WAITINT_Pos            (10U)

+#define SDMMC_CMD_WAITINT_Msk            (0x1UL << SDMMC_CMD_WAITINT_Pos)      /*!< 0x00000400 */

+#define SDMMC_CMD_WAITINT                SDMMC_CMD_WAITINT_Msk                 /*!<CPSM Waits for Interrupt Request                               */

+#define SDMMC_CMD_WAITPEND_Pos           (11U)

+#define SDMMC_CMD_WAITPEND_Msk           (0x1UL << SDMMC_CMD_WAITPEND_Pos)     /*!< 0x00000800 */

+#define SDMMC_CMD_WAITPEND               SDMMC_CMD_WAITPEND_Msk                /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */

+#define SDMMC_CMD_CPSMEN_Pos             (12U)

+#define SDMMC_CMD_CPSMEN_Msk             (0x1UL << SDMMC_CMD_CPSMEN_Pos)       /*!< 0x00001000 */

+#define SDMMC_CMD_CPSMEN                 SDMMC_CMD_CPSMEN_Msk                  /*!<Command path state machine (CPSM) Enable bit                   */

+#define SDMMC_CMD_DTHOLD_Pos             (13U)

+#define SDMMC_CMD_DTHOLD_Msk             (0x1UL << SDMMC_CMD_DTHOLD_Pos)       /*!< 0x00002000 */

+#define SDMMC_CMD_DTHOLD                 SDMMC_CMD_DTHOLD_Msk                  /*!<Hold new data block transmission and reception in the DPSM     */

+#define SDMMC_CMD_BOOTMODE_Pos           (14U)

+#define SDMMC_CMD_BOOTMODE_Msk           (0x1UL << SDMMC_CMD_BOOTMODE_Pos)     /*!< 0x00004000 */

+#define SDMMC_CMD_BOOTMODE               SDMMC_CMD_BOOTMODE_Msk                /*!<Boot mode                                                      */

+#define SDMMC_CMD_BOOTEN_Pos             (15U)

+#define SDMMC_CMD_BOOTEN_Msk             (0x1UL << SDMMC_CMD_BOOTEN_Pos)       /*!< 0x00008000 */

+#define SDMMC_CMD_BOOTEN                 SDMMC_CMD_BOOTEN_Msk                  /*!<Enable Boot mode procedure                                     */

+#define SDMMC_CMD_CMDSUSPEND_Pos         (16U)

+#define SDMMC_CMD_CMDSUSPEND_Msk         (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)   /*!< 0x00010000 */

+#define SDMMC_CMD_CMDSUSPEND             SDMMC_CMD_CMDSUSPEND_Msk              /*!<CPSM Treats command as a Suspend or Resume command             */

+

+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/

+#define SDMMC_RESPCMD_RESPCMD_Pos        (0U)

+#define SDMMC_RESPCMD_RESPCMD_Msk        (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */

+#define SDMMC_RESPCMD_RESPCMD            SDMMC_RESPCMD_RESPCMD_Msk             /*!<Response command index */

+

+/******************  Bit definition for SDMMC_RESP0 register  ******************/

+#define SDMMC_RESP0_CARDSTATUS0_Pos      (0U)

+#define SDMMC_RESP0_CARDSTATUS0_Msk      (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP0_CARDSTATUS0          SDMMC_RESP0_CARDSTATUS0_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP1 register  ******************/

+#define SDMMC_RESP1_CARDSTATUS1_Pos      (0U)

+#define SDMMC_RESP1_CARDSTATUS1_Msk      (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP1_CARDSTATUS1          SDMMC_RESP1_CARDSTATUS1_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP2 register  ******************/

+#define SDMMC_RESP2_CARDSTATUS2_Pos      (0U)

+#define SDMMC_RESP2_CARDSTATUS2_Msk      (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP2_CARDSTATUS2          SDMMC_RESP2_CARDSTATUS2_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP3 register  ******************/

+#define SDMMC_RESP3_CARDSTATUS3_Pos      (0U)

+#define SDMMC_RESP3_CARDSTATUS3_Msk      (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP3_CARDSTATUS3          SDMMC_RESP3_CARDSTATUS3_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP4 register  ******************/

+#define SDMMC_RESP4_CARDSTATUS4_Pos      (0U)

+#define SDMMC_RESP4_CARDSTATUS4_Msk      (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP4_CARDSTATUS4          SDMMC_RESP4_CARDSTATUS4_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_DTIMER register  *****************/

+#define SDMMC_DTIMER_DATATIME_Pos        (0U)

+#define SDMMC_DTIMER_DATATIME_Msk        (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_DTIMER_DATATIME            SDMMC_DTIMER_DATATIME_Msk             /*!<Data timeout period. */

+

+/******************  Bit definition for SDMMC_DLEN register  *******************/

+#define SDMMC_DLEN_DATALENGTH_Pos        (0U)

+#define SDMMC_DLEN_DATALENGTH_Msk        (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_DLEN_DATALENGTH            SDMMC_DLEN_DATALENGTH_Msk             /*!<Data length value    */

+

+/******************  Bit definition for SDMMC_DCTRL register  ******************/

+#define SDMMC_DCTRL_DTEN_Pos             (0U)

+#define SDMMC_DCTRL_DTEN_Msk             (0x1UL << SDMMC_DCTRL_DTEN_Pos)       /*!< 0x00000001 */

+#define SDMMC_DCTRL_DTEN                 SDMMC_DCTRL_DTEN_Msk                  /*!<Data transfer enabled bit                */

+#define SDMMC_DCTRL_DTDIR_Pos            (1U)

+#define SDMMC_DCTRL_DTDIR_Msk            (0x1UL << SDMMC_DCTRL_DTDIR_Pos)      /*!< 0x00000002 */

+#define SDMMC_DCTRL_DTDIR                SDMMC_DCTRL_DTDIR_Msk                 /*!<Data transfer direction selection        */

+#define SDMMC_DCTRL_DTMODE_Pos           (2U)

+#define SDMMC_DCTRL_DTMODE_Msk           (0x3UL << SDMMC_DCTRL_DTMODE_Pos)     /*!< 0x0000000C */

+#define SDMMC_DCTRL_DTMODE               SDMMC_DCTRL_DTMODE_Msk                /*!<DTMODE[1:0] Data transfer mode selection */

+#define SDMMC_DCTRL_DTMODE_0             (0x1UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000004 */

+#define SDMMC_DCTRL_DTMODE_1             (0x2UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000008 */

+

+#define SDMMC_DCTRL_DBLOCKSIZE_Pos       (4U)

+#define SDMMC_DCTRL_DBLOCKSIZE_Msk       (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */

+#define SDMMC_DCTRL_DBLOCKSIZE           SDMMC_DCTRL_DBLOCKSIZE_Msk            /*!<DBLOCKSIZE[3:0] bits (Data block size) */

+#define SDMMC_DCTRL_DBLOCKSIZE_0         (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000010 */

+#define SDMMC_DCTRL_DBLOCKSIZE_1         (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000020 */

+#define SDMMC_DCTRL_DBLOCKSIZE_2         (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000040 */

+#define SDMMC_DCTRL_DBLOCKSIZE_3         (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000080 */

+

+#define SDMMC_DCTRL_RWSTART_Pos          (8U)

+#define SDMMC_DCTRL_RWSTART_Msk          (0x1UL << SDMMC_DCTRL_RWSTART_Pos)    /*!< 0x00000100 */

+#define SDMMC_DCTRL_RWSTART              SDMMC_DCTRL_RWSTART_Msk               /*!<Read wait start                                 */

+#define SDMMC_DCTRL_RWSTOP_Pos           (9U)

+#define SDMMC_DCTRL_RWSTOP_Msk           (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)     /*!< 0x00000200 */

+#define SDMMC_DCTRL_RWSTOP               SDMMC_DCTRL_RWSTOP_Msk                /*!<Read wait stop                                  */

+#define SDMMC_DCTRL_RWMOD_Pos            (10U)

+#define SDMMC_DCTRL_RWMOD_Msk            (0x1UL << SDMMC_DCTRL_RWMOD_Pos)      /*!< 0x00000400 */

+#define SDMMC_DCTRL_RWMOD                SDMMC_DCTRL_RWMOD_Msk                 /*!<Read wait mode                                  */

+#define SDMMC_DCTRL_SDIOEN_Pos           (11U)

+#define SDMMC_DCTRL_SDIOEN_Msk           (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)     /*!< 0x00000800 */

+#define SDMMC_DCTRL_SDIOEN               SDMMC_DCTRL_SDIOEN_Msk                /*!<SD I/O enable functions                         */

+#define SDMMC_DCTRL_BOOTACKEN_Pos        (12U)

+#define SDMMC_DCTRL_BOOTACKEN_Msk        (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)  /*!< 0x00001000 */

+#define SDMMC_DCTRL_BOOTACKEN            SDMMC_DCTRL_BOOTACKEN_Msk             /*!<Enable the reception of the Boot Acknowledgment */

+#define SDMMC_DCTRL_FIFORST_Pos          (13U)

+#define SDMMC_DCTRL_FIFORST_Msk          (0x1UL << SDMMC_DCTRL_FIFORST_Pos)    /*!< 0x00002000 */

+#define SDMMC_DCTRL_FIFORST              SDMMC_DCTRL_FIFORST_Msk               /*!<FIFO reset                                      */

+

+/******************  Bit definition for SDMMC_DCOUNT register  *****************/

+#define SDMMC_DCOUNT_DATACOUNT_Pos       (0U)

+#define SDMMC_DCOUNT_DATACOUNT_Msk       (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_DCOUNT_DATACOUNT           SDMMC_DCOUNT_DATACOUNT_Msk            /*!<Data count value */

+

+/******************  Bit definition for SDMMC_STA register  ********************/

+#define SDMMC_STA_CCRCFAIL_Pos           (0U)

+#define SDMMC_STA_CCRCFAIL_Msk           (0x1UL << SDMMC_STA_CCRCFAIL_Pos)     /*!< 0x00000001 */

+#define SDMMC_STA_CCRCFAIL               SDMMC_STA_CCRCFAIL_Msk                /*!<Command response received (CRC check failed)  */

+#define SDMMC_STA_DCRCFAIL_Pos           (1U)

+#define SDMMC_STA_DCRCFAIL_Msk           (0x1UL << SDMMC_STA_DCRCFAIL_Pos)     /*!< 0x00000002 */

+#define SDMMC_STA_DCRCFAIL               SDMMC_STA_DCRCFAIL_Msk                /*!<Data block sent/received (CRC check failed)   */

+#define SDMMC_STA_CTIMEOUT_Pos           (2U)

+#define SDMMC_STA_CTIMEOUT_Msk           (0x1UL << SDMMC_STA_CTIMEOUT_Pos)     /*!< 0x00000004 */

+#define SDMMC_STA_CTIMEOUT               SDMMC_STA_CTIMEOUT_Msk                /*!<Command response timeout                      */

+#define SDMMC_STA_DTIMEOUT_Pos           (3U)

+#define SDMMC_STA_DTIMEOUT_Msk           (0x1UL << SDMMC_STA_DTIMEOUT_Pos)     /*!< 0x00000008 */

+#define SDMMC_STA_DTIMEOUT               SDMMC_STA_DTIMEOUT_Msk                /*!<Data timeout                                  */

+#define SDMMC_STA_TXUNDERR_Pos           (4U)

+#define SDMMC_STA_TXUNDERR_Msk           (0x1UL << SDMMC_STA_TXUNDERR_Pos)     /*!< 0x00000010 */

+#define SDMMC_STA_TXUNDERR               SDMMC_STA_TXUNDERR_Msk                /*!<Transmit FIFO underrun error                  */

+#define SDMMC_STA_RXOVERR_Pos            (5U)

+#define SDMMC_STA_RXOVERR_Msk            (0x1UL << SDMMC_STA_RXOVERR_Pos)      /*!< 0x00000020 */

+#define SDMMC_STA_RXOVERR                SDMMC_STA_RXOVERR_Msk                 /*!<Received FIFO overrun error                   */

+#define SDMMC_STA_CMDREND_Pos            (6U)

+#define SDMMC_STA_CMDREND_Msk            (0x1UL << SDMMC_STA_CMDREND_Pos)      /*!< 0x00000040 */

+#define SDMMC_STA_CMDREND                SDMMC_STA_CMDREND_Msk                 /*!<Command response received (CRC check passed)  */

+#define SDMMC_STA_CMDSENT_Pos            (7U)

+#define SDMMC_STA_CMDSENT_Msk            (0x1UL << SDMMC_STA_CMDSENT_Pos)      /*!< 0x00000080 */

+#define SDMMC_STA_CMDSENT                SDMMC_STA_CMDSENT_Msk                 /*!<Command sent (no response required)           */

+#define SDMMC_STA_DATAEND_Pos            (8U)

+#define SDMMC_STA_DATAEND_Msk            (0x1UL << SDMMC_STA_DATAEND_Pos)      /*!< 0x00000100 */

+#define SDMMC_STA_DATAEND                SDMMC_STA_DATAEND_Msk                 /*!<Data end (data counter, SDIDCOUNT, is zero)   */

+#define SDMMC_STA_DHOLD_Pos              (9U)

+#define SDMMC_STA_DHOLD_Msk              (0x1UL << SDMMC_STA_DHOLD_Pos)        /*!< 0x00000200 */

+#define SDMMC_STA_DHOLD                  SDMMC_STA_DHOLD_Msk                   /*!<Data transfer Hold                                                      */

+#define SDMMC_STA_DBCKEND_Pos            (10U)

+#define SDMMC_STA_DBCKEND_Msk            (0x1UL << SDMMC_STA_DBCKEND_Pos)      /*!< 0x00000400 */

+#define SDMMC_STA_DBCKEND                SDMMC_STA_DBCKEND_Msk                 /*!<Data block sent/received (CRC check passed)   */

+#define SDMMC_STA_DABORT_Pos             (11U)

+#define SDMMC_STA_DABORT_Msk             (0x1UL << SDMMC_STA_DABORT_Pos)       /*!< 0x00000800 */

+#define SDMMC_STA_DABORT                 SDMMC_STA_DABORT_Msk                  /*!<Data transfer aborted by CMD12                                          */

+#define SDMMC_STA_DPSMACT_Pos            (12U)

+#define SDMMC_STA_DPSMACT_Msk            (0x1UL << SDMMC_STA_DPSMACT_Pos)      /*!< 0x00001000 */

+#define SDMMC_STA_DPSMACT                SDMMC_STA_DPSMACT_Msk                 /*!<Data path state machine active                                       */

+#define SDMMC_STA_CPSMACT_Pos            (13U)

+#define SDMMC_STA_CPSMACT_Msk            (0x1UL << SDMMC_STA_CPSMACT_Pos)      /*!< 0x00002000 */

+#define SDMMC_STA_CPSMACT                SDMMC_STA_CPSMACT_Msk                 /*!<Command path state machine active                                          */

+#define SDMMC_STA_TXFIFOHE_Pos           (14U)

+#define SDMMC_STA_TXFIFOHE_Msk           (0x1UL << SDMMC_STA_TXFIFOHE_Pos)     /*!< 0x00004000 */

+#define SDMMC_STA_TXFIFOHE               SDMMC_STA_TXFIFOHE_Msk                /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */

+#define SDMMC_STA_RXFIFOHF_Pos           (15U)

+#define SDMMC_STA_RXFIFOHF_Msk           (0x1UL << SDMMC_STA_RXFIFOHF_Pos)     /*!< 0x00008000 */

+#define SDMMC_STA_RXFIFOHF               SDMMC_STA_RXFIFOHF_Msk                /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */

+#define SDMMC_STA_TXFIFOF_Pos            (16U)

+#define SDMMC_STA_TXFIFOF_Msk            (0x1UL << SDMMC_STA_TXFIFOF_Pos)      /*!< 0x00010000 */

+#define SDMMC_STA_TXFIFOF                SDMMC_STA_TXFIFOF_Msk                 /*!<Transmit FIFO full                            */

+#define SDMMC_STA_RXFIFOF_Pos            (17U)

+#define SDMMC_STA_RXFIFOF_Msk            (0x1UL << SDMMC_STA_RXFIFOF_Pos)      /*!< 0x00020000 */

+#define SDMMC_STA_RXFIFOF                SDMMC_STA_RXFIFOF_Msk                 /*!<Receive FIFO full                             */

+#define SDMMC_STA_TXFIFOE_Pos            (18U)

+#define SDMMC_STA_TXFIFOE_Msk            (0x1UL << SDMMC_STA_TXFIFOE_Pos)      /*!< 0x00040000 */

+#define SDMMC_STA_TXFIFOE                SDMMC_STA_TXFIFOE_Msk                 /*!<Transmit FIFO empty                           */

+#define SDMMC_STA_RXFIFOE_Pos            (19U)

+#define SDMMC_STA_RXFIFOE_Msk            (0x1UL << SDMMC_STA_RXFIFOE_Pos)      /*!< 0x00080000 */

+#define SDMMC_STA_RXFIFOE                SDMMC_STA_RXFIFOE_Msk                 /*!<Receive FIFO empty                            */

+#define SDMMC_STA_BUSYD0_Pos             (20U)

+#define SDMMC_STA_BUSYD0_Msk             (0x1UL << SDMMC_STA_BUSYD0_Pos)       /*!< 0x00100000 */

+#define SDMMC_STA_BUSYD0                 SDMMC_STA_BUSYD0_Msk                  /*!<Inverted value of SDMMC_D0 line (Busy)                                  */

+#define SDMMC_STA_BUSYD0END_Pos          (21U)

+#define SDMMC_STA_BUSYD0END_Msk          (0x1UL << SDMMC_STA_BUSYD0END_Pos)    /*!< 0x00200000 */

+#define SDMMC_STA_BUSYD0END              SDMMC_STA_BUSYD0END_Msk               /*!<End of SDMMC_D0 Busy following a CMD response detected                  */

+#define SDMMC_STA_SDIOIT_Pos             (22U)

+#define SDMMC_STA_SDIOIT_Msk             (0x1UL << SDMMC_STA_SDIOIT_Pos)       /*!< 0x00400000 */

+#define SDMMC_STA_SDIOIT                 SDMMC_STA_SDIOIT_Msk                  /*!<SDIO interrupt received                                                 */

+#define SDMMC_STA_ACKFAIL_Pos            (23U)

+#define SDMMC_STA_ACKFAIL_Msk            (0x1UL << SDMMC_STA_ACKFAIL_Pos)      /*!< 0x00800000 */

+#define SDMMC_STA_ACKFAIL                SDMMC_STA_ACKFAIL_Msk                 /*!<Boot Acknowledgment received (BootAck check fail)                       */

+#define SDMMC_STA_ACKTIMEOUT_Pos         (24U)

+#define SDMMC_STA_ACKTIMEOUT_Msk         (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)   /*!< 0x01000000 */

+#define SDMMC_STA_ACKTIMEOUT             SDMMC_STA_ACKTIMEOUT_Msk              /*!<Boot Acknowledgment timeout                                             */

+#define SDMMC_STA_VSWEND_Pos             (25U)

+#define SDMMC_STA_VSWEND_Msk             (0x1UL << SDMMC_STA_VSWEND_Pos)       /*!< 0x02000000 */

+#define SDMMC_STA_VSWEND                 SDMMC_STA_VSWEND_Msk                  /*!<Voltage switch critical timing section completion                       */

+#define SDMMC_STA_CKSTOP_Pos             (26U)

+#define SDMMC_STA_CKSTOP_Msk             (0x1UL << SDMMC_STA_CKSTOP_Pos)       /*!< 0x04000000 */

+#define SDMMC_STA_CKSTOP                 SDMMC_STA_CKSTOP_Msk                  /*!<SDMMC_CK stopped in Voltage switch procedure                            */

+#define SDMMC_STA_IDMATE_Pos             (27U)

+#define SDMMC_STA_IDMATE_Msk             (0x1UL << SDMMC_STA_IDMATE_Pos)       /*!< 0x08000000 */

+#define SDMMC_STA_IDMATE                 SDMMC_STA_IDMATE_Msk                  /*!<IDMA transfer error                                                     */

+#define SDMMC_STA_IDMABTC_Pos            (28U)

+#define SDMMC_STA_IDMABTC_Msk            (0x1UL << SDMMC_STA_IDMABTC_Pos)      /*!< 0x10000000 */

+#define SDMMC_STA_IDMABTC                SDMMC_STA_IDMABTC_Msk                 /*!<IDMA buffer transfer complete                                           */

+

+/*******************  Bit definition for SDMMC_ICR register  *******************/

+#define SDMMC_ICR_CCRCFAILC_Pos          (0U)

+#define SDMMC_ICR_CCRCFAILC_Msk          (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)    /*!< 0x00000001 */

+#define SDMMC_ICR_CCRCFAILC              SDMMC_ICR_CCRCFAILC_Msk               /*!<CCRCFAIL flag clear bit */

+#define SDMMC_ICR_DCRCFAILC_Pos          (1U)

+#define SDMMC_ICR_DCRCFAILC_Msk          (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)    /*!< 0x00000002 */

+#define SDMMC_ICR_DCRCFAILC              SDMMC_ICR_DCRCFAILC_Msk               /*!<DCRCFAIL flag clear bit */

+#define SDMMC_ICR_CTIMEOUTC_Pos          (2U)

+#define SDMMC_ICR_CTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)    /*!< 0x00000004 */

+#define SDMMC_ICR_CTIMEOUTC              SDMMC_ICR_CTIMEOUTC_Msk               /*!<CTIMEOUT flag clear bit */

+#define SDMMC_ICR_DTIMEOUTC_Pos          (3U)

+#define SDMMC_ICR_DTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)    /*!< 0x00000008 */

+#define SDMMC_ICR_DTIMEOUTC              SDMMC_ICR_DTIMEOUTC_Msk               /*!<DTIMEOUT flag clear bit */

+#define SDMMC_ICR_TXUNDERRC_Pos          (4U)

+#define SDMMC_ICR_TXUNDERRC_Msk          (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)    /*!< 0x00000010 */

+#define SDMMC_ICR_TXUNDERRC              SDMMC_ICR_TXUNDERRC_Msk               /*!<TXUNDERR flag clear bit */

+#define SDMMC_ICR_RXOVERRC_Pos           (5U)

+#define SDMMC_ICR_RXOVERRC_Msk           (0x1UL << SDMMC_ICR_RXOVERRC_Pos)     /*!< 0x00000020 */

+#define SDMMC_ICR_RXOVERRC               SDMMC_ICR_RXOVERRC_Msk                /*!<RXOVERR flag clear bit  */

+#define SDMMC_ICR_CMDRENDC_Pos           (6U)

+#define SDMMC_ICR_CMDRENDC_Msk           (0x1UL << SDMMC_ICR_CMDRENDC_Pos)     /*!< 0x00000040 */

+#define SDMMC_ICR_CMDRENDC               SDMMC_ICR_CMDRENDC_Msk                /*!<CMDREND flag clear bit  */

+#define SDMMC_ICR_CMDSENTC_Pos           (7U)

+#define SDMMC_ICR_CMDSENTC_Msk           (0x1UL << SDMMC_ICR_CMDSENTC_Pos)     /*!< 0x00000080 */

+#define SDMMC_ICR_CMDSENTC               SDMMC_ICR_CMDSENTC_Msk                /*!<CMDSENT flag clear bit  */

+#define SDMMC_ICR_DATAENDC_Pos           (8U)

+#define SDMMC_ICR_DATAENDC_Msk           (0x1UL << SDMMC_ICR_DATAENDC_Pos)     /*!< 0x00000100 */

+#define SDMMC_ICR_DATAENDC               SDMMC_ICR_DATAENDC_Msk                /*!<DATAEND flag clear bit  */

+#define SDMMC_ICR_DHOLDC_Pos             (9U)

+#define SDMMC_ICR_DHOLDC_Msk             (0x1UL << SDMMC_ICR_DHOLDC_Pos)       /*!< 0x00000200 */

+#define SDMMC_ICR_DHOLDC                 SDMMC_ICR_DHOLDC_Msk                  /*!<DHOLD flag clear bit       */

+#define SDMMC_ICR_DBCKENDC_Pos           (10U)

+#define SDMMC_ICR_DBCKENDC_Msk           (0x1UL << SDMMC_ICR_DBCKENDC_Pos)     /*!< 0x00000400 */

+#define SDMMC_ICR_DBCKENDC               SDMMC_ICR_DBCKENDC_Msk                /*!<DBCKEND flag clear bit  */

+#define SDMMC_ICR_DABORTC_Pos            (11U)

+#define SDMMC_ICR_DABORTC_Msk            (0x1UL << SDMMC_ICR_DABORTC_Pos)      /*!< 0x00000800 */

+#define SDMMC_ICR_DABORTC                SDMMC_ICR_DABORTC_Msk                 /*!<DABORTC flag clear bit     */

+#define SDMMC_ICR_BUSYD0ENDC_Pos         (21U)

+#define SDMMC_ICR_BUSYD0ENDC_Msk         (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)   /*!< 0x00200000 */

+#define SDMMC_ICR_BUSYD0ENDC             SDMMC_ICR_BUSYD0ENDC_Msk              /*!<BUSYD0ENDC flag clear bit  */

+#define SDMMC_ICR_SDIOITC_Pos            (22U)

+#define SDMMC_ICR_SDIOITC_Msk            (0x1UL << SDMMC_ICR_SDIOITC_Pos)      /*!< 0x00400000 */

+#define SDMMC_ICR_SDIOITC                SDMMC_ICR_SDIOITC_Msk                 /*!<SDIOIT flag clear bit      */

+#define SDMMC_ICR_ACKFAILC_Pos           (23U)

+#define SDMMC_ICR_ACKFAILC_Msk           (0x1UL << SDMMC_ICR_ACKFAILC_Pos)     /*!< 0x00800000 */

+#define SDMMC_ICR_ACKFAILC               SDMMC_ICR_ACKFAILC_Msk                /*!<ACKFAILC flag clear bit    */

+#define SDMMC_ICR_ACKTIMEOUTC_Pos        (24U)

+#define SDMMC_ICR_ACKTIMEOUTC_Msk        (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)  /*!< 0x01000000 */

+#define SDMMC_ICR_ACKTIMEOUTC            SDMMC_ICR_ACKTIMEOUTC_Msk             /*!<ACKTIMEOUTC flag clear bit */

+#define SDMMC_ICR_VSWENDC_Pos            (25U)

+#define SDMMC_ICR_VSWENDC_Msk            (0x1UL << SDMMC_ICR_VSWENDC_Pos)      /*!< 0x02000000 */

+#define SDMMC_ICR_VSWENDC                SDMMC_ICR_VSWENDC_Msk                 /*!<VSWENDC flag clear bit     */

+#define SDMMC_ICR_CKSTOPC_Pos            (26U)

+#define SDMMC_ICR_CKSTOPC_Msk            (0x1UL << SDMMC_ICR_CKSTOPC_Pos)      /*!< 0x04000000 */

+#define SDMMC_ICR_CKSTOPC                SDMMC_ICR_CKSTOPC_Msk                 /*!<CKSTOPC flag clear bit     */

+#define SDMMC_ICR_IDMATEC_Pos            (27U)

+#define SDMMC_ICR_IDMATEC_Msk            (0x1UL << SDMMC_ICR_IDMATEC_Pos)      /*!< 0x08000000 */

+#define SDMMC_ICR_IDMATEC                SDMMC_ICR_IDMATEC_Msk                 /*!<IDMATEC flag clear bit     */

+#define SDMMC_ICR_IDMABTCC_Pos           (28U)

+#define SDMMC_ICR_IDMABTCC_Msk           (0x1UL << SDMMC_ICR_IDMABTCC_Pos)     /*!< 0x10000000 */

+#define SDMMC_ICR_IDMABTCC               SDMMC_ICR_IDMABTCC_Msk                /*!<IDMABTCC flag clear bit    */

+

+/******************  Bit definition for SDMMC_MASK register  *******************/

+#define SDMMC_MASK_CCRCFAILIE_Pos        (0U)

+#define SDMMC_MASK_CCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)  /*!< 0x00000001 */

+#define SDMMC_MASK_CCRCFAILIE            SDMMC_MASK_CCRCFAILIE_Msk             /*!<Command CRC Fail Interrupt Enable          */

+#define SDMMC_MASK_DCRCFAILIE_Pos        (1U)

+#define SDMMC_MASK_DCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)  /*!< 0x00000002 */

+#define SDMMC_MASK_DCRCFAILIE            SDMMC_MASK_DCRCFAILIE_Msk             /*!<Data CRC Fail Interrupt Enable             */

+#define SDMMC_MASK_CTIMEOUTIE_Pos        (2U)

+#define SDMMC_MASK_CTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)  /*!< 0x00000004 */

+#define SDMMC_MASK_CTIMEOUTIE            SDMMC_MASK_CTIMEOUTIE_Msk             /*!<Command TimeOut Interrupt Enable           */

+#define SDMMC_MASK_DTIMEOUTIE_Pos        (3U)

+#define SDMMC_MASK_DTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)  /*!< 0x00000008 */

+#define SDMMC_MASK_DTIMEOUTIE            SDMMC_MASK_DTIMEOUTIE_Msk             /*!<Data TimeOut Interrupt Enable              */

+#define SDMMC_MASK_TXUNDERRIE_Pos        (4U)

+#define SDMMC_MASK_TXUNDERRIE_Msk        (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)  /*!< 0x00000010 */

+#define SDMMC_MASK_TXUNDERRIE            SDMMC_MASK_TXUNDERRIE_Msk             /*!<Tx FIFO UnderRun Error Interrupt Enable    */

+#define SDMMC_MASK_RXOVERRIE_Pos         (5U)

+#define SDMMC_MASK_RXOVERRIE_Msk         (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)   /*!< 0x00000020 */

+#define SDMMC_MASK_RXOVERRIE             SDMMC_MASK_RXOVERRIE_Msk              /*!<Rx FIFO OverRun Error Interrupt Enable     */

+#define SDMMC_MASK_CMDRENDIE_Pos         (6U)

+#define SDMMC_MASK_CMDRENDIE_Msk         (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)   /*!< 0x00000040 */

+#define SDMMC_MASK_CMDRENDIE             SDMMC_MASK_CMDRENDIE_Msk              /*!<Command Response Received Interrupt Enable */

+#define SDMMC_MASK_CMDSENTIE_Pos         (7U)

+#define SDMMC_MASK_CMDSENTIE_Msk         (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)   /*!< 0x00000080 */

+#define SDMMC_MASK_CMDSENTIE             SDMMC_MASK_CMDSENTIE_Msk              /*!<Command Sent Interrupt Enable              */

+#define SDMMC_MASK_DATAENDIE_Pos         (8U)

+#define SDMMC_MASK_DATAENDIE_Msk         (0x1UL << SDMMC_MASK_DATAENDIE_Pos)   /*!< 0x00000100 */

+#define SDMMC_MASK_DATAENDIE             SDMMC_MASK_DATAENDIE_Msk              /*!<Data End Interrupt Enable                  */

+#define SDMMC_MASK_DHOLDIE_Pos           (9U)

+#define SDMMC_MASK_DHOLDIE_Msk           (0x1UL << SDMMC_MASK_DHOLDIE_Pos)     /*!< 0x00000200 */

+#define SDMMC_MASK_DHOLDIE               SDMMC_MASK_DHOLDIE_Msk                /*!<Data Hold Interrupt Enable                 */

+#define SDMMC_MASK_DBCKENDIE_Pos         (10U)

+#define SDMMC_MASK_DBCKENDIE_Msk         (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)   /*!< 0x00000400 */

+#define SDMMC_MASK_DBCKENDIE             SDMMC_MASK_DBCKENDIE_Msk              /*!<Data Block End Interrupt Enable            */

+#define SDMMC_MASK_DABORTIE_Pos          (11U)

+#define SDMMC_MASK_DABORTIE_Msk          (0x1UL << SDMMC_MASK_DABORTIE_Pos)    /*!< 0x00000800 */

+#define SDMMC_MASK_DABORTIE              SDMMC_MASK_DABORTIE_Msk               /*!<Data transfer aborted interrupt enable     */

+

+#define SDMMC_MASK_TXFIFOHEIE_Pos        (14U)

+#define SDMMC_MASK_TXFIFOHEIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)  /*!< 0x00004000 */

+#define SDMMC_MASK_TXFIFOHEIE            SDMMC_MASK_TXFIFOHEIE_Msk             /*!<Tx FIFO Half Empty interrupt Enable        */

+#define SDMMC_MASK_RXFIFOHFIE_Pos        (15U)

+#define SDMMC_MASK_RXFIFOHFIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)  /*!< 0x00008000 */

+#define SDMMC_MASK_RXFIFOHFIE            SDMMC_MASK_RXFIFOHFIE_Msk             /*!<Rx FIFO Half Full interrupt Enable         */

+

+#define SDMMC_MASK_RXFIFOFIE_Pos         (17U)

+#define SDMMC_MASK_RXFIFOFIE_Msk         (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)   /*!< 0x00020000 */

+#define SDMMC_MASK_RXFIFOFIE             SDMMC_MASK_RXFIFOFIE_Msk              /*!<Rx FIFO Full interrupt Enable              */

+#define SDMMC_MASK_TXFIFOEIE_Pos         (18U)

+#define SDMMC_MASK_TXFIFOEIE_Msk         (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)   /*!< 0x00040000 */

+#define SDMMC_MASK_TXFIFOEIE             SDMMC_MASK_TXFIFOEIE_Msk              /*!<Tx FIFO Empty interrupt Enable             */

+

+#define SDMMC_MASK_BUSYD0ENDIE_Pos       (21U)

+#define SDMMC_MASK_BUSYD0ENDIE_Msk       (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */

+#define SDMMC_MASK_BUSYD0ENDIE           SDMMC_MASK_BUSYD0ENDIE_Msk            /*!<BUSYD0ENDIE interrupt Enable */

+#define SDMMC_MASK_SDIOITIE_Pos           (22U)

+#define SDMMC_MASK_SDIOITIE_Msk           (0x1UL << SDMMC_MASK_SDIOITIE_Pos)     /*!< 0x00400000 */

+#define SDMMC_MASK_SDIOITIE               SDMMC_MASK_SDIOITIE_Msk                /*!<SDMMC Mode Interrupt Received interrupt Enable */

+#define SDMMC_MASK_ACKFAILIE_Pos         (23U)

+#define SDMMC_MASK_ACKFAILIE_Msk         (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)   /*!< 0x00800000 */

+#define SDMMC_MASK_ACKFAILIE             SDMMC_MASK_ACKFAILIE_Msk              /*!<Acknowledgment Fail Interrupt Enable */

+#define SDMMC_MASK_ACKTIMEOUTIE_Pos      (24U)

+#define SDMMC_MASK_ACKTIMEOUTIE_Msk      (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */

+#define SDMMC_MASK_ACKTIMEOUTIE          SDMMC_MASK_ACKTIMEOUTIE_Msk           /*!<Acknowledgment timeout Interrupt Enable */

+#define SDMMC_MASK_VSWENDIE_Pos          (25U)

+#define SDMMC_MASK_VSWENDIE_Msk          (0x1UL << SDMMC_MASK_VSWENDIE_Pos)    /*!< 0x02000000 */

+#define SDMMC_MASK_VSWENDIE              SDMMC_MASK_VSWENDIE_Msk               /*!<Voltage switch critical timing section completion Interrupt Enable */

+#define SDMMC_MASK_CKSTOPIE_Pos          (26U)

+#define SDMMC_MASK_CKSTOPIE_Msk          (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)    /*!< 0x04000000 */

+#define SDMMC_MASK_CKSTOPIE              SDMMC_MASK_CKSTOPIE_Msk               /*!<Voltage Switch clock stopped Interrupt Enable */

+#define SDMMC_MASK_IDMABTCIE_Pos         (28U)

+#define SDMMC_MASK_IDMABTCIE_Msk         (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)   /*!< 0x10000000 */

+#define SDMMC_MASK_IDMABTCIE             SDMMC_MASK_IDMABTCIE_Msk              /*!<IDMA buffer transfer complete Interrupt Enable */

+

+/*****************  Bit definition for SDMMC_ACKTIME register  *****************/

+#define SDMMC_ACKTIME_ACKTIME_Pos        (0U)

+#define SDMMC_ACKTIME_ACKTIME_Msk        (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_ACKTIME_ACKTIME            SDMMC_ACKTIME_ACKTIME_Msk             /*!<Boot acknowledgment timeout period */

+

+/******************  Bit definition for SDMMC_FIFO register  *******************/

+#define SDMMC_FIFO_FIFODATA_Pos          (0U)

+#define SDMMC_FIFO_FIFODATA_Msk          (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_FIFO_FIFODATA              SDMMC_FIFO_FIFODATA_Msk               /*!<Receive and transmit FIFO data */

+

+/******************  Bit definition for SDMMC_IDMACTRL register ****************/

+#define SDMMC_IDMA_IDMAEN_Pos            (0U)

+#define SDMMC_IDMA_IDMAEN_Msk            (0x1UL << SDMMC_IDMA_IDMAEN_Pos)      /*!< 0x00000001 */

+#define SDMMC_IDMA_IDMAEN                SDMMC_IDMA_IDMAEN_Msk                 /*!< Enable the internal DMA of the SDMMC peripheral */

+#define SDMMC_IDMA_IDMABMODE_Pos         (1U)

+#define SDMMC_IDMA_IDMABMODE_Msk         (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)   /*!< 0x00000002 */

+#define SDMMC_IDMA_IDMABMODE             SDMMC_IDMA_IDMABMODE_Msk              /*!< Enable double buffer mode for IDMA */

+#define SDMMC_IDMA_IDMABACT_Pos          (2U)

+#define SDMMC_IDMA_IDMABACT_Msk          (0x1UL << SDMMC_IDMA_IDMABACT_Pos)    /*!< 0x00000004 */

+#define SDMMC_IDMA_IDMABACT              SDMMC_IDMA_IDMABACT_Msk               /*!< Uses buffer 1 when double buffer mode is selected */

+

+/*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/

+#define SDMMC_IDMABSIZE_IDMABNDT_Pos     (5U)

+#define SDMMC_IDMABSIZE_IDMABNDT_Msk     (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */

+#define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */

+

+/*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/

+#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */

+

+/*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/

+#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                        Delay Block Interface (DLYB)                        */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for DLYB_CR register  ********************/

+#define DLYB_CR_DEN_Pos         (0U)

+#define DLYB_CR_DEN_Msk         (0x1UL << DLYB_CR_DEN_Pos)                     /*!< 0x00000001 */

+#define DLYB_CR_DEN             DLYB_CR_DEN_Msk                                /*!<Delay Block enable */

+#define DLYB_CR_SEN_Pos         (1U)

+#define DLYB_CR_SEN_Msk         (0x1UL << DLYB_CR_SEN_Pos)                     /*!< 0x00000002 */

+#define DLYB_CR_SEN             DLYB_CR_SEN_Msk                                /*!<Sampler length enable */

+

+

+/*******************  Bit definition for DLYB_CFGR register  ********************/

+#define DLYB_CFGR_SEL_Pos       (0U)

+#define DLYB_CFGR_SEL_Msk       (0xFUL << DLYB_CFGR_SEL_Pos)                   /*!< 0x0000000F */

+#define DLYB_CFGR_SEL           DLYB_CFGR_SEL_Msk                              /*!<Select the phase for the Output clock[3:0] */

+#define DLYB_CFGR_SEL_0         (0x1UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000001 */

+#define DLYB_CFGR_SEL_1         (0x2UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000002 */

+#define DLYB_CFGR_SEL_2         (0x3UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000003 */

+#define DLYB_CFGR_SEL_3         (0x8UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000008 */

+

+#define DLYB_CFGR_UNIT_Pos      (8U)

+#define DLYB_CFGR_UNIT_Msk      (0x7FUL << DLYB_CFGR_UNIT_Pos)                 /*!< 0x00007F00 */

+#define DLYB_CFGR_UNIT          DLYB_CFGR_UNIT_Msk                             /*!<Delay Defines the delay of a Unit delay cell[6:0] */

+#define DLYB_CFGR_UNIT_0        (0x01UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000100 */

+#define DLYB_CFGR_UNIT_1        (0x02UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000200 */

+#define DLYB_CFGR_UNIT_2        (0x04UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000400 */

+#define DLYB_CFGR_UNIT_3        (0x08UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000800 */

+#define DLYB_CFGR_UNIT_4        (0x10UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00001000 */

+#define DLYB_CFGR_UNIT_5        (0x20UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00002000 */

+#define DLYB_CFGR_UNIT_6        (0x40UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00004000 */

+

+#define DLYB_CFGR_LNG_Pos       (16U)

+#define DLYB_CFGR_LNG_Msk       (0xFFFUL << DLYB_CFGR_LNG_Pos)                 /*!< 0x0FFF0000 */

+#define DLYB_CFGR_LNG           DLYB_CFGR_LNG_Msk                              /*!<Delay line length value[11:0] */

+#define DLYB_CFGR_LNG_0         (0x001UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00010000 */

+#define DLYB_CFGR_LNG_1         (0x002UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00020000 */

+#define DLYB_CFGR_LNG_2         (0x004UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00040000 */

+#define DLYB_CFGR_LNG_3         (0x008UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00080000 */

+#define DLYB_CFGR_LNG_4         (0x010UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00100000 */

+#define DLYB_CFGR_LNG_5         (0x020UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00200000 */

+#define DLYB_CFGR_LNG_6         (0x040UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00400000 */

+#define DLYB_CFGR_LNG_7         (0x080UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00800000 */

+#define DLYB_CFGR_LNG_8         (0x100UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x01000000 */

+#define DLYB_CFGR_LNG_9         (0x200UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x02000000 */

+#define DLYB_CFGR_LNG_10        (0x400UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x04000000 */

+#define DLYB_CFGR_LNG_11        (0x800UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x08000000 */

+

+#define DLYB_CFGR_LNGF_Pos      (31U)

+#define DLYB_CFGR_LNGF_Msk      (0x1UL << DLYB_CFGR_LNGF_Pos)                  /*!< 0x80000000 */

+#define DLYB_CFGR_LNGF          DLYB_CFGR_LNGF_Msk                             /*!<Length valid flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                   Serial Peripheral Interface (SPI/I2S)                    */

+/*                                                                            */

+/******************************************************************************/

+#define SPI_SPI6I2S_SUPPORT       /*!<SPI6 I2S support feature */

+/*******************  Bit definition for SPI_CR1 register  ********************/

+#define SPI_CR1_SPE_Pos             (0U)

+#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000001 */

+#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<Serial Peripheral Enable                         */

+#define SPI_CR1_MASRX_Pos           (8U)

+#define SPI_CR1_MASRX_Msk           (0x1UL << SPI_CR1_MASRX_Pos)               /*!< 0x00000100 */

+#define SPI_CR1_MASRX               SPI_CR1_MASRX_Msk                          /*!<Master automatic SUSP in Receive mode            */

+#define SPI_CR1_CSTART_Pos          (9U)

+#define SPI_CR1_CSTART_Msk          (0x1UL << SPI_CR1_CSTART_Pos)              /*!< 0x00000200 */

+#define SPI_CR1_CSTART              SPI_CR1_CSTART_Msk                         /*!<Master transfer start                            */

+#define SPI_CR1_CSUSP_Pos           (10U)

+#define SPI_CR1_CSUSP_Msk           (0x1UL << SPI_CR1_CSUSP_Pos)               /*!< 0x00000400 */

+#define SPI_CR1_CSUSP               SPI_CR1_CSUSP_Msk                          /*!<Master SUSPend request                           */

+#define SPI_CR1_HDDIR_Pos           (11U)

+#define SPI_CR1_HDDIR_Msk           (0x1UL << SPI_CR1_HDDIR_Pos)               /*!< 0x00000800 */

+#define SPI_CR1_HDDIR               SPI_CR1_HDDIR_Msk                          /*!<Rx/Tx direction at Half-duplex mode              */

+#define SPI_CR1_SSI_Pos             (12U)

+#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00001000 */

+#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal SS signal input level                   */

+#define SPI_CR1_CRC33_17_Pos        (13U)

+#define SPI_CR1_CRC33_17_Msk        (0x1UL << SPI_CR1_CRC33_17_Pos)            /*!< 0x00002000 */

+#define SPI_CR1_CRC33_17             SPI_CR1_CRC33_17_Msk                      /*!<32-bit CRC polynomial configuration              */

+#define SPI_CR1_RCRCINI_Pos         (14U)

+#define SPI_CR1_RCRCINI_Msk         (0x1UL << SPI_CR1_RCRCINI_Pos)             /*!< 0x00004000 */

+#define SPI_CR1_RCRCINI             SPI_CR1_RCRCINI_Msk                        /*!<CRC init pattern control for receiver            */

+#define SPI_CR1_TCRCINI_Pos         (15U)

+#define SPI_CR1_TCRCINI_Msk         (0x1UL << SPI_CR1_TCRCINI_Pos)             /*!< 0x00008000 */

+#define SPI_CR1_TCRCINI             SPI_CR1_TCRCINI_Msk                        /*!<CRC init pattern control for transmitter         */

+#define SPI_CR1_IOLOCK_Pos          (16U)

+#define SPI_CR1_IOLOCK_Msk          (0x1UL << SPI_CR1_IOLOCK_Pos)              /*!< 0x00010000 */

+#define SPI_CR1_IOLOCK              SPI_CR1_IOLOCK_Msk                         /*!<Locking the AF configuration of associated IOs   */

+

+/*******************  Bit definition for SPI_CR2 register  ********************/

+#define SPI_CR2_TSER_Pos            (16U)

+#define SPI_CR2_TSER_Msk            (0xFFFFUL << SPI_CR2_TSER_Pos)             /*!< 0xFFFF0000 */

+#define SPI_CR2_TSER                SPI_CR2_TSER_Msk                           /*!<Number of data transfer extension                */

+#define SPI_CR2_TSIZE_Pos           (0U)

+#define SPI_CR2_TSIZE_Msk           (0xFFFFUL << SPI_CR2_TSIZE_Pos)            /*!< 0x0000FFFF */

+#define SPI_CR2_TSIZE               SPI_CR2_TSIZE_Msk                          /*!<Number of data at current transfer               */

+

+/*******************  Bit definition for SPI_CFG1 register  ********************/

+#define SPI_CFG1_DSIZE_Pos          (0U)

+#define SPI_CFG1_DSIZE_Msk          (0x1FUL << SPI_CFG1_DSIZE_Pos)             /*!< 0x0000001F */

+#define SPI_CFG1_DSIZE              SPI_CFG1_DSIZE_Msk                         /*!<DSIZE[4:0]: Bits number in single SPI data frame */

+#define SPI_CFG1_DSIZE_0            (0x01UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000001 */

+#define SPI_CFG1_DSIZE_1            (0x02UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000002 */

+#define SPI_CFG1_DSIZE_2            (0x04UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000004 */

+#define SPI_CFG1_DSIZE_3            (0x08UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000008 */

+#define SPI_CFG1_DSIZE_4            (0x10UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000010 */

+

+#define SPI_CFG1_FTHLV_Pos          (5U)

+#define SPI_CFG1_FTHLV_Msk          (0xFUL << SPI_CFG1_FTHLV_Pos)              /*!< 0x000001E0 */

+#define SPI_CFG1_FTHLV              SPI_CFG1_FTHLV_Msk                         /*!<FTHVL [3:0]: FIFO threshold level*/

+#define SPI_CFG1_FTHLV_0            (0x1UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000020 */

+#define SPI_CFG1_FTHLV_1            (0x2UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000040 */

+#define SPI_CFG1_FTHLV_2            (0x4UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000080 */

+#define SPI_CFG1_FTHLV_3            (0x8UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000100 */

+

+#define SPI_CFG1_UDRCFG_Pos         (9U)

+#define SPI_CFG1_UDRCFG_Msk         (0x3UL << SPI_CFG1_UDRCFG_Pos)             /*!< 0x00000600 */

+#define SPI_CFG1_UDRCFG             SPI_CFG1_UDRCFG_Msk                        /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */

+#define SPI_CFG1_UDRCFG_0           (0x1UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000200 */

+#define SPI_CFG1_UDRCFG_1           (0x2UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000400 */

+

+

+#define SPI_CFG1_UDRDET_Pos         (11U)

+#define SPI_CFG1_UDRDET_Msk         (0x3UL << SPI_CFG1_UDRDET_Pos)             /*!< 0x00001800 */

+#define SPI_CFG1_UDRDET             SPI_CFG1_UDRDET_Msk                        /*!<UDRDET[1:0]: Detection of underrun condition     */

+#define SPI_CFG1_UDRDET_0           (0x1UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00000800 */

+#define SPI_CFG1_UDRDET_1           (0x2UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00001000 */

+

+#define SPI_CFG1_RXDMAEN_Pos        (14U)

+#define SPI_CFG1_RXDMAEN_Msk        (0x1UL << SPI_CFG1_RXDMAEN_Pos)            /*!< 0x00004000 */

+#define SPI_CFG1_RXDMAEN            SPI_CFG1_RXDMAEN_Msk                       /*!<Rx DMA stream enable                */

+#define SPI_CFG1_TXDMAEN_Pos        (15U)

+#define SPI_CFG1_TXDMAEN_Msk        (0x1UL << SPI_CFG1_TXDMAEN_Pos)            /*!< 0x00008000 */

+#define SPI_CFG1_TXDMAEN            SPI_CFG1_TXDMAEN_Msk                       /*!<Tx DMA stream enable                */

+

+#define SPI_CFG1_CRCSIZE_Pos        (16U)

+#define SPI_CFG1_CRCSIZE_Msk        (0x1FUL << SPI_CFG1_CRCSIZE_Pos)           /*!< 0x001F0000 */

+#define SPI_CFG1_CRCSIZE            SPI_CFG1_CRCSIZE_Msk                       /*!<CRCSIZE [4:0]: Length of CRC frame*/

+#define SPI_CFG1_CRCSIZE_0          (0x01UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00010000 */

+#define SPI_CFG1_CRCSIZE_1          (0x02UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00020000 */

+#define SPI_CFG1_CRCSIZE_2          (0x04UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00040000 */

+#define SPI_CFG1_CRCSIZE_3          (0x08UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00080000 */

+#define SPI_CFG1_CRCSIZE_4          (0x10UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00100000 */

+

+#define SPI_CFG1_CRCEN_Pos          (22U)

+#define SPI_CFG1_CRCEN_Msk          (0x1UL << SPI_CFG1_CRCEN_Pos)              /*!< 0x00400000 */

+#define SPI_CFG1_CRCEN              SPI_CFG1_CRCEN_Msk                         /*!<Hardware CRC computation enable */

+

+#define SPI_CFG1_MBR_Pos            (28U)

+#define SPI_CFG1_MBR_Msk            (0x7UL << SPI_CFG1_MBR_Pos)                /*!< 0x70000000 */

+#define SPI_CFG1_MBR                SPI_CFG1_MBR_Msk                           /*!<Master baud rate                */

+#define SPI_CFG1_MBR_0              (0x1UL << SPI_CFG1_MBR_Pos)                 /*!< 0x10000000 */

+#define SPI_CFG1_MBR_1              (0x2UL << SPI_CFG1_MBR_Pos)                 /*!< 0x20000000 */

+#define SPI_CFG1_MBR_2              (0x4UL << SPI_CFG1_MBR_Pos)                 /*!< 0x40000000 */

+

+/*******************  Bit definition for SPI_CFG2 register  ********************/

+#define SPI_CFG2_MSSI_Pos           (0U)

+#define SPI_CFG2_MSSI_Msk           (0xFUL << SPI_CFG2_MSSI_Pos)               /*!< 0x0000000F */

+#define SPI_CFG2_MSSI               SPI_CFG2_MSSI_Msk                          /*!<Master SS Idleness */

+#define SPI_CFG2_MSSI_0             (0x1UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000001 */

+#define SPI_CFG2_MSSI_1             (0x2UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000002 */

+#define SPI_CFG2_MSSI_2             (0x4UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000004 */

+#define SPI_CFG2_MSSI_3             (0x8UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000008 */

+

+#define SPI_CFG2_MIDI_Pos           (4U)

+#define SPI_CFG2_MIDI_Msk           (0xFUL << SPI_CFG2_MIDI_Pos)               /*!< 0x000000F0 */

+#define SPI_CFG2_MIDI               SPI_CFG2_MIDI_Msk                          /*!<Master Inter-Data Idleness */

+#define SPI_CFG2_MIDI_0             (0x1UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000010 */

+#define SPI_CFG2_MIDI_1             (0x2UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000020 */

+#define SPI_CFG2_MIDI_2             (0x4UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000040 */

+#define SPI_CFG2_MIDI_3             (0x8UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000080 */

+

+#define SPI_CFG2_IOSWP_Pos          (15U)

+#define SPI_CFG2_IOSWP_Msk          (0x1UL << SPI_CFG2_IOSWP_Pos)              /*!< 0x00008000 */

+#define SPI_CFG2_IOSWP              SPI_CFG2_IOSWP_Msk                         /*!<Swap functionality of MISO and MOSI pins */

+

+#define SPI_CFG2_COMM_Pos           (17U)

+#define SPI_CFG2_COMM_Msk           (0x3UL << SPI_CFG2_COMM_Pos)               /*!< 0x00060000 */

+#define SPI_CFG2_COMM               SPI_CFG2_COMM_Msk                          /*!<COMM [1:0]: SPI Communication Mode*/

+#define SPI_CFG2_COMM_0             (0x1UL << SPI_CFG2_COMM_Pos)                /*!< 0x00020000 */

+#define SPI_CFG2_COMM_1             (0x2UL << SPI_CFG2_COMM_Pos)                /*!< 0x00040000 */

+

+#define SPI_CFG2_SP_Pos             (19U)

+#define SPI_CFG2_SP_Msk             (0x7UL << SPI_CFG2_SP_Pos)                 /*!< 0x00380000 */

+#define SPI_CFG2_SP                 SPI_CFG2_SP_Msk                            /*!<SP[2:0]: Serial Protocol */

+#define SPI_CFG2_SP_0               (0x1UL << SPI_CFG2_SP_Pos)                  /*!< 0x00080000 */

+#define SPI_CFG2_SP_1               (0x2UL << SPI_CFG2_SP_Pos)                  /*!< 0x00100000 */

+#define SPI_CFG2_SP_2               (0x4UL << SPI_CFG2_SP_Pos)                  /*!< 0x00200000 */

+

+#define SPI_CFG2_MASTER_Pos         (22U)

+#define SPI_CFG2_MASTER_Msk         (0x1UL << SPI_CFG2_MASTER_Pos)             /*!< 0x00400000 */

+#define SPI_CFG2_MASTER             SPI_CFG2_MASTER_Msk                        /*!<SPI Master           */

+#define SPI_CFG2_LSBFRST_Pos        (23U)

+#define SPI_CFG2_LSBFRST_Msk        (0x1UL << SPI_CFG2_LSBFRST_Pos)            /*!< 0x00800000 */

+#define SPI_CFG2_LSBFRST            SPI_CFG2_LSBFRST_Msk                       /*!<Data frame format               */

+#define SPI_CFG2_CPHA_Pos           (24U)

+#define SPI_CFG2_CPHA_Msk           (0x1UL << SPI_CFG2_CPHA_Pos)               /*!< 0x01000000 */

+#define SPI_CFG2_CPHA               SPI_CFG2_CPHA_Msk                          /*!<Clock Phase      */

+#define SPI_CFG2_CPOL_Pos           (25U)

+#define SPI_CFG2_CPOL_Msk           (0x1UL << SPI_CFG2_CPOL_Pos)               /*!< 0x02000000 */

+#define SPI_CFG2_CPOL               SPI_CFG2_CPOL_Msk                          /*!<Clock Polarity   */

+#define SPI_CFG2_SSM_Pos            (26U)

+#define SPI_CFG2_SSM_Msk            (0x1UL << SPI_CFG2_SSM_Pos)                /*!< 0x04000000 */

+#define SPI_CFG2_SSM                SPI_CFG2_SSM_Msk                           /*!<Software slave management */

+

+#define SPI_CFG2_SSIOP_Pos          (28U)

+#define SPI_CFG2_SSIOP_Msk          (0x1UL << SPI_CFG2_SSIOP_Pos)              /*!< 0x10000000 */

+#define SPI_CFG2_SSIOP              SPI_CFG2_SSIOP_Msk                         /*!<SS input/output polarity */

+#define SPI_CFG2_SSOE_Pos           (29U)

+#define SPI_CFG2_SSOE_Msk           (0x1UL << SPI_CFG2_SSOE_Pos)               /*!< 0x20000000 */

+#define SPI_CFG2_SSOE               SPI_CFG2_SSOE_Msk                          /*!<SS output enable */

+#define SPI_CFG2_SSOM_Pos           (30U)

+#define SPI_CFG2_SSOM_Msk           (0x1UL << SPI_CFG2_SSOM_Pos)               /*!< 0x40000000 */

+#define SPI_CFG2_SSOM               SPI_CFG2_SSOM_Msk                          /*!<SS output management in master mode */

+

+#define SPI_CFG2_AFCNTR_Pos         (31U)

+#define SPI_CFG2_AFCNTR_Msk         (0x1UL << SPI_CFG2_AFCNTR_Pos)             /*!< 0x80000000 */

+#define SPI_CFG2_AFCNTR             SPI_CFG2_AFCNTR_Msk                        /*!<Alternate function GPIOs control */

+

+/*******************  Bit definition for SPI_IER register  ********************/

+#define SPI_IER_RXPIE_Pos           (0U)

+#define SPI_IER_RXPIE_Msk           (0x1UL << SPI_IER_RXPIE_Pos)               /*!< 0x00000001 */

+#define SPI_IER_RXPIE               SPI_IER_RXPIE_Msk                          /*!<RXP Interrupt Enable            */

+#define SPI_IER_TXPIE_Pos           (1U)

+#define SPI_IER_TXPIE_Msk           (0x1UL << SPI_IER_TXPIE_Pos)               /*!< 0x00000002 */

+#define SPI_IER_TXPIE               SPI_IER_TXPIE_Msk                          /*!<TXP interrupt enable            */

+#define SPI_IER_DXPIE_Pos           (2U)

+#define SPI_IER_DXPIE_Msk           (0x1UL << SPI_IER_DXPIE_Pos)               /*!< 0x00000004 */

+#define SPI_IER_DXPIE               SPI_IER_DXPIE_Msk                          /*!<DXP interrupt enable            */

+#define SPI_IER_EOTIE_Pos           (3U)

+#define SPI_IER_EOTIE_Msk           (0x1UL << SPI_IER_EOTIE_Pos)               /*!< 0x00000008 */

+#define SPI_IER_EOTIE               SPI_IER_EOTIE_Msk                          /*!<EOT/SUSP/TXC interrupt enable   */

+#define SPI_IER_TXTFIE_Pos          (4U)

+#define SPI_IER_TXTFIE_Msk          (0x1UL << SPI_IER_TXTFIE_Pos)              /*!< 0x00000010 */

+#define SPI_IER_TXTFIE              SPI_IER_TXTFIE_Msk                         /*!<TXTF interrupt enable           */

+#define SPI_IER_UDRIE_Pos           (5U)

+#define SPI_IER_UDRIE_Msk           (0x1UL << SPI_IER_UDRIE_Pos)               /*!< 0x00000020 */

+#define SPI_IER_UDRIE               SPI_IER_UDRIE_Msk                          /*!<UDR interrupt enable            */

+#define SPI_IER_OVRIE_Pos           (6U)

+#define SPI_IER_OVRIE_Msk           (0x1UL << SPI_IER_OVRIE_Pos)               /*!< 0x00000040 */

+#define SPI_IER_OVRIE               SPI_IER_OVRIE_Msk                          /*!<OVR interrupt enable            */

+#define SPI_IER_CRCEIE_Pos          (7U)

+#define SPI_IER_CRCEIE_Msk          (0x1UL << SPI_IER_CRCEIE_Pos)               /*!< 0x00000080 */

+#define SPI_IER_CRCEIE              SPI_IER_CRCEIE_Msk                          /*!<CRCE interrupt enable           */

+#define SPI_IER_TIFREIE_Pos         (8U)

+#define SPI_IER_TIFREIE_Msk         (0x1UL << SPI_IER_TIFREIE_Pos)             /*!< 0x00000100 */

+#define SPI_IER_TIFREIE             SPI_IER_TIFREIE_Msk                        /*!<TI Frame Error interrupt enable */

+#define SPI_IER_MODFIE_Pos          (9U)

+#define SPI_IER_MODFIE_Msk          (0x1UL << SPI_IER_MODFIE_Pos)              /*!< 0x00000200 */

+#define SPI_IER_MODFIE              SPI_IER_MODFIE_Msk                         /*!<MODF interrupt enable           */

+#define SPI_IER_TSERFIE_Pos         (10U)

+#define SPI_IER_TSERFIE_Msk         (0x1UL << SPI_IER_TSERFIE_Pos)              /*!< 0x00000400 */

+#define SPI_IER_TSERFIE             SPI_IER_TSERFIE_Msk                        /*!<TSERF interrupt enable          */

+

+/*******************  Bit definition for SPI_SR register  ********************/

+#define SPI_SR_RXP_Pos              (0U)

+#define SPI_SR_RXP_Msk              (0x1UL << SPI_SR_RXP_Pos)                  /*!< 0x00000001 */

+#define SPI_SR_RXP                  SPI_SR_RXP_Msk                             /*!<Rx-Packet available             */

+#define SPI_SR_TXP_Pos              (1U)

+#define SPI_SR_TXP_Msk              (0x1UL << SPI_SR_TXP_Pos)                  /*!< 0x00000002 */

+#define SPI_SR_TXP                  SPI_SR_TXP_Msk                             /*!<Tx-Packet space available       */

+#define SPI_SR_DXP_Pos              (2U)

+#define SPI_SR_DXP_Msk              (0x1UL << SPI_SR_DXP_Pos)                  /*!< 0x00000004 */

+#define SPI_SR_DXP                  SPI_SR_DXP_Msk                             /*!<Duplex Packet available         */

+#define SPI_SR_EOT_Pos              (3U)

+#define SPI_SR_EOT_Msk              (0x1UL << SPI_SR_EOT_Pos)                  /*!< 0x00000008 */

+#define SPI_SR_EOT                  SPI_SR_EOT_Msk                             /*!<Duplex Packet available         */

+#define SPI_SR_TXTF_Pos             (4U)

+#define SPI_SR_TXTF_Msk             (0x1UL << SPI_SR_TXTF_Pos)                 /*!< 0x00000010 */

+#define SPI_SR_TXTF                 SPI_SR_TXTF_Msk                            /*!<Transmission Transfer Filled    */

+#define SPI_SR_UDR_Pos              (5U)

+#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000020 */

+#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<UDR at Slave transmission       */

+#define SPI_SR_OVR_Pos              (6U)

+#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */

+#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Rx-Packet available             */

+#define SPI_SR_CRCE_Pos             (7U)

+#define SPI_SR_CRCE_Msk             (0x1UL << SPI_SR_CRCE_Pos)                 /*!< 0x00000080 */

+#define SPI_SR_CRCE                 SPI_SR_CRCE_Msk                            /*!<CRC Error Detected              */

+#define SPI_SR_TIFRE_Pos            (8U)

+#define SPI_SR_TIFRE_Msk            (0x1UL << SPI_SR_TIFRE_Pos)                /*!< 0x00000100 */

+#define SPI_SR_TIFRE                SPI_SR_TIFRE_Msk                           /*!<TI frame format error Detected  */

+#define SPI_SR_MODF_Pos             (9U)

+#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000200 */

+#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode Fault Detected             */

+#define SPI_SR_TSERF_Pos            (10U)

+#define SPI_SR_TSERF_Msk            (0x1UL << SPI_SR_TSERF_Pos)                /*!< 0x00000400 */

+#define SPI_SR_TSERF                SPI_SR_TSERF_Msk                           /*!<Number of SPI data to be transacted reloaded     */

+#define SPI_SR_SUSP_Pos             (11U)

+#define SPI_SR_SUSP_Msk             (0x1UL << SPI_SR_SUSP_Pos)                 /*!< 0x00000800 */

+#define SPI_SR_SUSP                 SPI_SR_SUSP_Msk                            /*!<SUSP is set by hardware  */

+#define SPI_SR_TXC_Pos              (12U)

+#define SPI_SR_TXC_Msk              (0x1UL << SPI_SR_TXC_Pos)                  /*!< 0x00001000 */

+#define SPI_SR_TXC                  SPI_SR_TXC_Msk                             /*!<TxFIFO transmission complete */

+#define SPI_SR_RXPLVL_Pos           (13U)

+#define SPI_SR_RXPLVL_Msk           (0x3UL << SPI_SR_RXPLVL_Pos)               /*!< 0x00006000 */

+#define SPI_SR_RXPLVL               SPI_SR_RXPLVL_Msk                          /*!<RxFIFO Packing Level                             */

+#define SPI_SR_RXPLVL_0             (0x1UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00002000 */

+#define SPI_SR_RXPLVL_1             (0x2UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00004000 */

+#define SPI_SR_RXWNE_Pos            (15U)

+#define SPI_SR_RXWNE_Msk            (0x1UL << SPI_SR_RXWNE_Pos)                /*!< 0x00008000 */

+#define SPI_SR_RXWNE                SPI_SR_RXWNE_Msk                           /*!<Rx FIFO Word Not Empty                           */

+#define SPI_SR_CTSIZE_Pos           (16U)

+#define SPI_SR_CTSIZE_Msk           (0xFFFFUL << SPI_SR_CTSIZE_Pos)            /*!< 0xFFFF0000 */

+#define SPI_SR_CTSIZE               SPI_SR_CTSIZE_Msk                          /*!<Number of data frames remaining in TSIZE         */

+

+/*******************  Bit definition for SPI_IFCR register  ********************/

+#define SPI_IFCR_EOTC_Pos           (3U)

+#define SPI_IFCR_EOTC_Msk           (0x1UL << SPI_IFCR_EOTC_Pos)               /*!< 0x00000008 */

+#define SPI_IFCR_EOTC               SPI_IFCR_EOTC_Msk                          /*!<End Of Transfer flag clear              */

+#define SPI_IFCR_TXTFC_Pos          (4U)

+#define SPI_IFCR_TXTFC_Msk          (0x1UL << SPI_IFCR_TXTFC_Pos)              /*!< 0x00000010 */

+#define SPI_IFCR_TXTFC              SPI_IFCR_TXTFC_Msk                         /*!<Transmission Transfer Filled flag clear */

+#define SPI_IFCR_UDRC_Pos           (5U)

+#define SPI_IFCR_UDRC_Msk           (0x1UL << SPI_IFCR_UDRC_Pos)               /*!< 0x00000020 */

+#define SPI_IFCR_UDRC               SPI_IFCR_UDRC_Msk                          /*!<Underrun flag clear                     */

+#define SPI_IFCR_OVRC_Pos           (6U)

+#define SPI_IFCR_OVRC_Msk           (0x1UL << SPI_IFCR_OVRC_Pos)               /*!< 0x00000040 */

+#define SPI_IFCR_OVRC               SPI_IFCR_OVRC_Msk                          /*!<Overrun flag clear                      */

+#define SPI_IFCR_CRCEC_Pos          (7U)

+#define SPI_IFCR_CRCEC_Msk          (0x1UL << SPI_IFCR_CRCEC_Pos)              /*!< 0x00000080 */

+#define SPI_IFCR_CRCEC              SPI_IFCR_CRCEC_Msk                         /*!<CRC Error flag clear                    */

+#define SPI_IFCR_TIFREC_Pos         (8U)

+#define SPI_IFCR_TIFREC_Msk         (0x1UL << SPI_IFCR_TIFREC_Pos)             /*!< 0x00000100 */

+#define SPI_IFCR_TIFREC             SPI_IFCR_TIFREC_Msk                        /*!<TI frame format error flag clear        */

+#define SPI_IFCR_MODFC_Pos          (9U)

+#define SPI_IFCR_MODFC_Msk          (0x1UL << SPI_IFCR_MODFC_Pos)              /*!< 0x00000200 */

+#define SPI_IFCR_MODFC              SPI_IFCR_MODFC_Msk                         /*!<Mode Fault flag clear                   */

+#define SPI_IFCR_TSERFC_Pos         (10U)

+#define SPI_IFCR_TSERFC_Msk         (0x1UL << SPI_IFCR_TSERFC_Pos)             /*!< 0x00000400 */

+#define SPI_IFCR_TSERFC             SPI_IFCR_TSERFC_Msk                        /*!<TSERFC flag clear                       */

+#define SPI_IFCR_SUSPC_Pos          (11U)

+#define SPI_IFCR_SUSPC_Msk          (0x1UL << SPI_IFCR_SUSPC_Pos)              /*!< 0x00000800 */

+#define SPI_IFCR_SUSPC              SPI_IFCR_SUSPC_Msk                         /*!<SUSPend flag clear                      */

+

+/*******************  Bit definition for SPI_TXDR register  ********************/

+#define SPI_TXDR_TXDR_Pos           (0U)

+#define SPI_TXDR_TXDR_Msk           (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)        /*!< 0xFFFFFFFF */

+#define SPI_TXDR_TXDR               SPI_TXDR_TXDR_Msk                          /* Transmit Data Register */

+

+/*******************  Bit definition for SPI_RXDR register  ********************/

+#define SPI_RXDR_RXDR_Pos           (0U)

+#define SPI_RXDR_RXDR_Msk           (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)        /*!< 0xFFFFFFFF */

+#define SPI_RXDR_RXDR               SPI_RXDR_RXDR_Msk                          /* Receive Data Register  */

+

+/*******************  Bit definition for SPI_CRCPOLY register  ********************/

+#define SPI_CRCPOLY_CRCPOLY_Pos     (0U)

+#define SPI_CRCPOLY_CRCPOLY_Msk     (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)  /*!< 0xFFFFFFFF */

+#define SPI_CRCPOLY_CRCPOLY         SPI_CRCPOLY_CRCPOLY_Msk                    /* CRC Polynomial register  */

+

+/*******************  Bit definition for SPI_TXCRC register  ********************/

+#define SPI_TXCRC_TXCRC_Pos         (0U)

+#define SPI_TXCRC_TXCRC_Msk         (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_TXCRC_TXCRC             SPI_TXCRC_TXCRC_Msk                        /* CRCRegister for transmitter */

+

+/*******************  Bit definition for SPI_RXCRC register  ********************/

+#define SPI_RXCRC_RXCRC_Pos         (0U)

+#define SPI_RXCRC_RXCRC_Msk         (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_RXCRC_RXCRC             SPI_RXCRC_RXCRC_Msk                        /* CRCRegister for receiver */

+

+/*******************  Bit definition for SPI_UDRDR register  ********************/

+#define SPI_UDRDR_UDRDR_Pos         (0U)

+#define SPI_UDRDR_UDRDR_Msk         (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_UDRDR_UDRDR             SPI_UDRDR_UDRDR_Msk                        /* Data at slave underrun condition */

+

+/******************  Bit definition for SPI_I2SCFGR register  *****************/

+#define SPI_I2SCFGR_I2SMOD_Pos      (0U)

+#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000001 */

+#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */

+#define SPI_I2SCFGR_I2SCFG_Pos      (1U)

+#define SPI_I2SCFGR_I2SCFG_Msk      (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x0000000E */

+#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[2:0] I2S configuration mode                */

+#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000002 */

+#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000004 */

+#define SPI_I2SCFGR_I2SCFG_2        (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000008 */

+#define SPI_I2SCFGR_I2SSTD_Pos      (4U)

+#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */

+#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] I2S standard selection                */

+#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */

+#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */

+#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)

+#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */

+#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                         */

+#define SPI_I2SCFGR_DATLEN_Pos      (8U)

+#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000300 */

+#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] Data length to be transferred         */

+#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000100 */

+#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000200 */

+#define SPI_I2SCFGR_CHLEN_Pos       (10U)

+#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000400 */

+#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */

+#define SPI_I2SCFGR_CKPOL_Pos       (11U)

+#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000800 */

+#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<Steady state clock polarity                       */

+#define SPI_I2SCFGR_FIXCH_Pos       (12U)

+#define SPI_I2SCFGR_FIXCH_Msk       (0x1UL << SPI_I2SCFGR_FIXCH_Pos)           /*!< 0x00001000 */

+#define SPI_I2SCFGR_FIXCH           SPI_I2SCFGR_FIXCH_Msk                      /*!<Fixed channel length in SLAVE                     */

+#define SPI_I2SCFGR_WSINV_Pos       (13U)

+#define SPI_I2SCFGR_WSINV_Msk       (0x1UL << SPI_I2SCFGR_WSINV_Pos)           /*!< 0x00002000 */

+#define SPI_I2SCFGR_WSINV           SPI_I2SCFGR_WSINV_Msk                      /*!<Word select inversion                             */

+#define SPI_I2SCFGR_DATFMT_Pos      (14U)

+#define SPI_I2SCFGR_DATFMT_Msk      (0x1UL << SPI_I2SCFGR_DATFMT_Pos)          /*!< 0x00004000 */

+#define SPI_I2SCFGR_DATFMT          SPI_I2SCFGR_DATFMT_Msk                     /*!<Data format                                       */

+#define SPI_I2SCFGR_I2SDIV_Pos      (16U)

+#define SPI_I2SCFGR_I2SDIV_Msk      (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)         /*!< 0x00FF0000 */

+#define SPI_I2SCFGR_I2SDIV          SPI_I2SCFGR_I2SDIV_Msk                     /*!<I2S Linear prescaler */

+#define SPI_I2SCFGR_ODD_Pos         (24U)

+#define SPI_I2SCFGR_ODD_Msk         (0x1UL << SPI_I2SCFGR_ODD_Pos)             /*!< 0x01000000 */

+#define SPI_I2SCFGR_ODD             SPI_I2SCFGR_ODD_Msk                        /*!<Odd factor for the prescaler */

+#define SPI_I2SCFGR_MCKOE_Pos       (25U)

+#define SPI_I2SCFGR_MCKOE_Msk       (0x1UL << SPI_I2SCFGR_MCKOE_Pos)           /*!< 0x02000000 */

+#define SPI_I2SCFGR_MCKOE           SPI_I2SCFGR_MCKOE_Msk                      /*!<Master Clock Output Enable */

+

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                 SYSCFG                                     */

+/*                                                                            */

+/******************************************************************************/

+

+/******************  Bit definition for SYSCFG_PMCR register  ******************/

+#define SYSCFG_PMCR_I2C1_FMP_Pos        (0U)

+#define SYSCFG_PMCR_I2C1_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos)    /*!< 0x00000001 */

+#define SYSCFG_PMCR_I2C1_FMP            SYSCFG_PMCR_I2C1_FMP_Msk               /*!< I2C1 Fast mode plus */

+#define SYSCFG_PMCR_I2C2_FMP_Pos        (1U)

+#define SYSCFG_PMCR_I2C2_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos)    /*!< 0x00000002 */

+#define SYSCFG_PMCR_I2C2_FMP            SYSCFG_PMCR_I2C2_FMP_Msk               /*!< I2C2 Fast mode plus */

+#define SYSCFG_PMCR_I2C3_FMP_Pos        (2U)

+#define SYSCFG_PMCR_I2C3_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos)    /*!< 0x00000004 */

+#define SYSCFG_PMCR_I2C3_FMP            SYSCFG_PMCR_I2C3_FMP_Msk               /*!< I2C3 Fast mode plus */

+#define SYSCFG_PMCR_I2C4_FMP_Pos        (3U)

+#define SYSCFG_PMCR_I2C4_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos)    /*!< 0x00000008 */

+#define SYSCFG_PMCR_I2C4_FMP            SYSCFG_PMCR_I2C4_FMP_Msk               /*!< I2C4 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB6_FMP_Pos     (4U)

+#define SYSCFG_PMCR_I2C_PB6_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */

+#define SYSCFG_PMCR_I2C_PB6_FMP         SYSCFG_PMCR_I2C_PB6_FMP_Msk            /*!< I2C PB6 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB7_FMP_Pos     (5U)

+#define SYSCFG_PMCR_I2C_PB7_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */

+#define SYSCFG_PMCR_I2C_PB7_FMP         SYSCFG_PMCR_I2C_PB7_FMP_Msk            /*!< I2C PB7 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB8_FMP_Pos     (6U)

+#define SYSCFG_PMCR_I2C_PB8_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */

+#define SYSCFG_PMCR_I2C_PB8_FMP         SYSCFG_PMCR_I2C_PB8_FMP_Msk            /*!< I2C PB8 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB9_FMP_Pos     (7U)

+#define SYSCFG_PMCR_I2C_PB9_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */

+#define SYSCFG_PMCR_I2C_PB9_FMP         SYSCFG_PMCR_I2C_PB9_FMP_Msk            /*!< I2C PB9 Fast mode plus */

+#define SYSCFG_PMCR_PA0SO_Pos           (24U)

+#define SYSCFG_PMCR_PA0SO_Msk           (0x1UL << SYSCFG_PMCR_PA0SO_Pos)       /*!< 0x01000000 */

+#define SYSCFG_PMCR_PA0SO               SYSCFG_PMCR_PA0SO_Msk                  /*!< PA0 Switch Open */

+#define SYSCFG_PMCR_PA1SO_Pos           (25U)

+#define SYSCFG_PMCR_PA1SO_Msk           (0x1UL << SYSCFG_PMCR_PA1SO_Pos)       /*!< 0x02000000 */

+#define SYSCFG_PMCR_PA1SO               SYSCFG_PMCR_PA1SO_Msk                  /*!< PA1 Switch Open */

+#define SYSCFG_PMCR_PC2SO_Pos           (26U)

+#define SYSCFG_PMCR_PC2SO_Msk           (0x1UL << SYSCFG_PMCR_PC2SO_Pos)       /*!< 0x04000000 */

+#define SYSCFG_PMCR_PC2SO               SYSCFG_PMCR_PC2SO_Msk                  /*!< PC2 Switch Open */

+#define SYSCFG_PMCR_PC3SO_Pos           (27U)

+#define SYSCFG_PMCR_PC3SO_Msk           (0x1UL << SYSCFG_PMCR_PC3SO_Pos)       /*!< 0x08000000 */

+#define SYSCFG_PMCR_PC3SO               SYSCFG_PMCR_PC3SO_Msk                  /*!< PC3 Switch Open */

+

+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/

+#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)

+#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */

+#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)

+#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */

+#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)

+#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000F00 */

+#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */

+#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)

+#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x0000F000 */

+#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */

+/**

+  * @brief   EXTI0 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */

+

+/**

+  * @brief   EXTI1 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */

+/**

+  * @brief   EXTI2 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */

+

+/**

+  * @brief   EXTI3 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/

+#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)

+#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */

+#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)

+#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */

+#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)

+#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000F00 */

+#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */

+#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)

+#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x0000F000 */

+#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */

+/**

+  * @brief   EXTI4 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */

+/**

+  * @brief   EXTI5 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */

+/**

+  * @brief   EXTI6 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */

+

+/**

+  * @brief   EXTI7 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/

+#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)

+#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */

+#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)

+#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */

+#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)

+#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000F00 */

+#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */

+#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)

+#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x0000F000 */

+#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */

+

+/**

+  * @brief   EXTI8 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */

+

+/**

+  * @brief   EXTI9 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */

+

+/**

+  * @brief   EXTI10 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */

+

+/**

+  * @brief   EXTI11 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/

+#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)

+#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x0000000F */

+#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */

+#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)

+#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x000000F0 */

+#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */

+#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)

+#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000F00 */

+#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */

+#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)

+#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x0000F000 */

+#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */

+/**

+  * @brief   EXTI12 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */

+/**

+  * @brief   EXTI13 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */

+/**

+  * @brief   EXTI14 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */

+/**

+  * @brief   EXTI15 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */

+

+/******************  Bit definition for SYSCFG_CFGR register  ******************/

+#define SYSCFG_CFGR_PVDL_Pos            (2U)

+#define SYSCFG_CFGR_PVDL_Msk            (0x1UL << SYSCFG_CFGR_PVDL_Pos)        /*!< 0x00000004 */

+#define SYSCFG_CFGR_PVDL                SYSCFG_CFGR_PVDL_Msk                   /*!<PVD lock enable bit */

+#define SYSCFG_CFGR_FLASHL_Pos          (3U)

+#define SYSCFG_CFGR_FLASHL_Msk          (0x1UL << SYSCFG_CFGR_FLASHL_Pos)      /*!< 0x00000008 */

+#define SYSCFG_CFGR_FLASHL              SYSCFG_CFGR_FLASHL_Msk                 /*!<FLASH double ECC error lock bit */

+#define SYSCFG_CFGR_CM7L_Pos            (6U)

+#define SYSCFG_CFGR_CM7L_Msk            (0x1UL << SYSCFG_CFGR_CM7L_Pos)        /*!< 0x00000040 */

+#define SYSCFG_CFGR_CM7L                SYSCFG_CFGR_CM7L_Msk                   /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */

+#define SYSCFG_CFGR_DTCML_Pos           (13U)

+#define SYSCFG_CFGR_DTCML_Msk           (0x1UL << SYSCFG_CFGR_DTCML_Pos)       /*!< 0x00002000 */

+#define SYSCFG_CFGR_DTCML               SYSCFG_CFGR_DTCML_Msk                  /*!<DTCM double ECC error lock bit */

+#define SYSCFG_CFGR_ITCML_Pos           (14U)

+#define SYSCFG_CFGR_ITCML_Msk           (0x1UL << SYSCFG_CFGR_ITCML_Pos)       /*!< 0x00004000 */

+#define SYSCFG_CFGR_ITCML               SYSCFG_CFGR_ITCML_Msk                  /*!<ITCM double ECC error lock bit */

+/******************  Bit definition for SYSCFG_CCCSR register  ******************/

+#define SYSCFG_CCCSR_EN_Pos             (0U)

+#define SYSCFG_CCCSR_EN_Msk             (0x1UL << SYSCFG_CCCSR_EN_Pos)         /*!< 0x00000001 */

+#define SYSCFG_CCCSR_EN                 SYSCFG_CCCSR_EN_Msk                    /*!< I/O compensation cell enable */

+#define SYSCFG_CCCSR_CS_Pos             (1U)

+#define SYSCFG_CCCSR_CS_Msk             (0x1UL << SYSCFG_CCCSR_CS_Pos)         /*!< 0x00000002 */

+#define SYSCFG_CCCSR_CS                 SYSCFG_CCCSR_CS_Msk                    /*!< I/O compensation cell code selection */

+#define SYSCFG_CCCSR_CS_MMC_Pos         (3U)

+#define SYSCFG_CCCSR_CS_MMC_Msk         (0x1UL << SYSCFG_CCCSR_CS_MMC_Pos)         /*!< 0x00000004 */

+#define SYSCFG_CCCSR_CS_MMC             SYSCFG_CCCSR_CS_MMC_Msk                    /*!< I/O compensation cell code selection */

+#define SYSCFG_CCCSR_READY_Pos          (8U)

+#define SYSCFG_CCCSR_READY_Msk          (0x1UL << SYSCFG_CCCSR_READY_Pos)      /*!< 0x00000100 */

+#define SYSCFG_CCCSR_READY              SYSCFG_CCCSR_READY_Msk                 /*!< I/O compensation cell ready flag */

+#define SYSCFG_CCCSR_HSLV0_Pos           (16U)

+#define SYSCFG_CCCSR_HSLV0_Msk           (0x1UL << SYSCFG_CCCSR_HSLV0_Pos)       /*!< 0x00010000 */

+#define SYSCFG_CCCSR_HSLV0               SYSCFG_CCCSR_HSLV0_Msk                  /*!< High-speed at low-voltage */

+#define SYSCFG_CCCSR_HSLV1_Pos           (17U)

+#define SYSCFG_CCCSR_HSLV1_Msk           (0x1UL << SYSCFG_CCCSR_HSLV1_Pos)       /*!< 0x00020000 */

+#define SYSCFG_CCCSR_HSLV1               SYSCFG_CCCSR_HSLV1_Msk                  /*!< High-speed at low-voltage */

+#define SYSCFG_CCCSR_HSLV2_Pos           (18U)

+#define SYSCFG_CCCSR_HSLV2_Msk           (0x1UL << SYSCFG_CCCSR_HSLV2_Pos)       /*!< 0x00040000 */

+#define SYSCFG_CCCSR_HSLV2               SYSCFG_CCCSR_HSLV2_Msk                  /*!< High-speed at low-voltage */

+#define SYSCFG_CCCSR_HSLV3_Pos           (19U)

+#define SYSCFG_CCCSR_HSLV3_Msk           (0x1UL << SYSCFG_CCCSR_HSLV3_Pos)       /*!< 0x00080000 */

+#define SYSCFG_CCCSR_HSLV3               SYSCFG_CCCSR_HSLV3_Msk                  /*!< High-speed at low-voltage */

+/******************  Bit definition for SYSCFG_CCVR register  *******************/

+#define SYSCFG_CCVR_NCV_Pos             (0U)

+#define SYSCFG_CCVR_NCV_Msk             (0xFUL << SYSCFG_CCVR_NCV_Pos)         /*!< 0x0000000F */

+#define SYSCFG_CCVR_NCV                 SYSCFG_CCVR_NCV_Msk                    /*!< NMOS compensation value */

+#define SYSCFG_CCVR_PCV_Pos             (4U)

+#define SYSCFG_CCVR_PCV_Msk             (0xFUL << SYSCFG_CCVR_PCV_Pos)         /*!< 0x000000F0 */

+#define SYSCFG_CCVR_PCV                 SYSCFG_CCVR_PCV_Msk                    /*!< PMOS compensation value */

+

+/******************  Bit definition for SYSCFG_CCCR register  *******************/

+#define SYSCFG_CCCR_NCC_Pos             (0U)

+#define SYSCFG_CCCR_NCC_Msk             (0xFUL << SYSCFG_CCCR_NCC_Pos)         /*!< 0x0000000F */

+#define SYSCFG_CCCR_NCC                 SYSCFG_CCCR_NCC_Msk                    /*!< NMOS compensation code */

+#define SYSCFG_CCCR_PCC_Pos             (4U)

+#define SYSCFG_CCCR_PCC_Msk             (0xFUL << SYSCFG_CCCR_PCC_Pos)         /*!< 0x000000F0 */

+#define SYSCFG_CCCR_PCC                 SYSCFG_CCCR_PCC_Msk                    /*!< PMOS compensation code */

+#define SYSCFG_CCCR_NCC_MMC_Pos         (8U)

+#define SYSCFG_CCCR_NCC_MMC_Msk         (0xFUL << SYSCFG_CCCR_NCC_MMC_Pos)     /*!< 0x00000F00 */

+#define SYSCFG_CCCR_NCC_MMC             SYSCFG_CCCR_NCC_MMC_Msk                /*!< NMOS compensation code */

+#define SYSCFG_CCCR_PCC_MMC_Pos         (12U)

+#define SYSCFG_CCCR_PCC_MMC_Msk         (0xFUL << SYSCFG_CCCR_PCC_MMC_Pos)     /*!< 0x0000F000 */

+#define SYSCFG_CCCR_PCC_MMC             SYSCFG_CCCR_PCC_MMC_Msk                /*!< PMOS compensation code */

+/******************************************************************************/

+/*                                                                            */

+/*                    Digital Temperature Sensor (DTS)                        */

+/*                                                                            */

+/******************************************************************************/

+

+/******************  Bit definition for DTS_CFGR1 register  ******************/

+#define DTS_CFGR1_TS1_EN_Pos               (0U)

+#define DTS_CFGR1_TS1_EN_Msk               (0x1UL << DTS_CFGR1_TS1_EN_Pos) /*!< 0x00000001 */

+#define DTS_CFGR1_TS1_EN                   DTS_CFGR1_TS1_EN_Msk        /*!< DTS Enable */

+#define DTS_CFGR1_TS1_START_Pos            (4U)

+#define DTS_CFGR1_TS1_START_Msk            (0x1UL << DTS_CFGR1_TS1_START_Pos) /*!< 0x00000010 */

+#define DTS_CFGR1_TS1_START                DTS_CFGR1_TS1_START_Msk     /*!< Proceed to a frequency measurement on DTS */

+#define DTS_CFGR1_TS1_INTRIG_SEL_Pos       (8U)

+#define DTS_CFGR1_TS1_INTRIG_SEL_Msk       (0xFUL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000F00 */

+#define DTS_CFGR1_TS1_INTRIG_SEL           DTS_CFGR1_TS1_INTRIG_SEL_Msk /*!< Input triggers selection bits [3:0] for DTS */

+#define DTS_CFGR1_TS1_INTRIG_SEL_0         (0x1UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000100 */

+#define DTS_CFGR1_TS1_INTRIG_SEL_1         (0x2UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000200 */

+#define DTS_CFGR1_TS1_INTRIG_SEL_2         (0x4UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000400 */

+#define DTS_CFGR1_TS1_INTRIG_SEL_3         (0x8UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000800 */

+#define DTS_CFGR1_TS1_SMP_TIME_Pos         (16U)

+#define DTS_CFGR1_TS1_SMP_TIME_Msk         (0xFUL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x000F0000 */

+#define DTS_CFGR1_TS1_SMP_TIME             DTS_CFGR1_TS1_SMP_TIME_Msk  /*!< Sample time [3:0] for DTS */

+#define DTS_CFGR1_TS1_SMP_TIME_0           (0x1UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00010000 */

+#define DTS_CFGR1_TS1_SMP_TIME_1           (0x2UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00020000 */

+#define DTS_CFGR1_TS1_SMP_TIME_2           (0x4UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00040000 */

+#define DTS_CFGR1_TS1_SMP_TIME_3           (0x8UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00080000 */

+#define DTS_CFGR1_REFCLK_SEL_Pos           (20U)

+#define DTS_CFGR1_REFCLK_SEL_Msk           (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */

+#define DTS_CFGR1_REFCLK_SEL               DTS_CFGR1_REFCLK_SEL_Msk    /*!< Reference Clock Selection */

+#define DTS_CFGR1_Q_MEAS_OPT_Pos           (21U)

+#define DTS_CFGR1_Q_MEAS_OPT_Msk           (0x1UL << DTS_CFGR1_Q_MEAS_OPT_Pos) /*!< 0x00200000 */

+#define DTS_CFGR1_Q_MEAS_OPT               DTS_CFGR1_Q_MEAS_OPT_Msk    /*!< Quick measure option bit  */

+#define DTS_CFGR1_HSREF_CLK_DIV_Pos        (24U)

+#define DTS_CFGR1_HSREF_CLK_DIV_Msk        (0x7FUL << DTS_CFGR1_HSREF_CLK_DIV_Pos) /*!< 0x7F000000 */

+#define DTS_CFGR1_HSREF_CLK_DIV            DTS_CFGR1_HSREF_CLK_DIV_Msk /*!< High Speed Clock Divider Ratio [6:0]*/

+

+/******************  Bit definition for DTS_T0VALR1 register  ******************/

+#define DTS_T0VALR1_TS1_FMT0_Pos           (0U)

+#define DTS_T0VALR1_TS1_FMT0_Msk           (0xFFFFUL << DTS_T0VALR1_TS1_FMT0_Pos) /*!< 0x0000FFFF */

+#define DTS_T0VALR1_TS1_FMT0               DTS_T0VALR1_TS1_FMT0_Msk    /*!< Engineering value of the measured frequency at T0 for DTS */

+#define DTS_T0VALR1_TS1_T0_Pos             (16U)

+#define DTS_T0VALR1_TS1_T0_Msk             (0x3UL << DTS_T0VALR1_TS1_T0_Pos) /*!< 0x00030000 */

+#define DTS_T0VALR1_TS1_T0                 DTS_T0VALR1_TS1_T0_Msk      /*!< Engineering value of the DTSerature T0 for DTS */

+

+/******************  Bit definition for DTS_RAMPVALR register  ******************/

+#define DTS_RAMPVALR_TS1_RAMP_COEFF_Pos    (0U)

+#define DTS_RAMPVALR_TS1_RAMP_COEFF_Msk    (0xFFFFUL << DTS_RAMPVALR_TS1_RAMP_COEFF_Pos) /*!< 0x0000FFFF */

+#define DTS_RAMPVALR_TS1_RAMP_COEFF        DTS_RAMPVALR_TS1_RAMP_COEFF_Msk /*!< Engineering value of the ramp coefficient for DTS */

+

+/******************  Bit definition for DTS_ITR1 register      ******************/

+#define DTS_ITR1_TS1_LITTHD_Pos            (0U)

+#define DTS_ITR1_TS1_LITTHD_Msk            (0xFFFFUL << DTS_ITR1_TS1_LITTHD_Pos) /*!< 0x0000FFFF */

+#define DTS_ITR1_TS1_LITTHD                DTS_ITR1_TS1_LITTHD_Msk     /*!< Low interrupt threshold[15:0] for DTS */

+#define DTS_ITR1_TS1_HITTHD_Pos            (16U)

+#define DTS_ITR1_TS1_HITTHD_Msk            (0xFFFFUL << DTS_ITR1_TS1_HITTHD_Pos) /*!< 0xFFFF0000 */

+#define DTS_ITR1_TS1_HITTHD                DTS_ITR1_TS1_HITTHD_Msk     /*!< High interrupt threshold[15:0] for DTS */

+

+/******************  Bit definition for DTS_DR register        ******************/

+#define DTS_DR_TS1_MFREQ_Pos               (0U)

+#define DTS_DR_TS1_MFREQ_Msk               (0xFFFFUL << DTS_DR_TS1_MFREQ_Pos) /*!< 0x0000FFFF */

+#define DTS_DR_TS1_MFREQ                   DTS_DR_TS1_MFREQ_Msk        /*!< Measured Frequency[15:0] for DTS */

+

+/******************  Bit definition for DTS_SR register        ******************/

+#define DTS_SR_TS1_ITEF_Pos                (0U)

+#define DTS_SR_TS1_ITEF_Msk                (0x1UL << DTS_SR_TS1_ITEF_Pos) /*!< 0x00000001 */

+#define DTS_SR_TS1_ITEF                    DTS_SR_TS1_ITEF_Msk         /*!< Interrupt flag for end of measure for DTS */

+#define DTS_SR_TS1_ITLF_Pos                (1U)

+#define DTS_SR_TS1_ITLF_Msk                (0x1UL << DTS_SR_TS1_ITLF_Pos) /*!< 0x00000002 */

+#define DTS_SR_TS1_ITLF                    DTS_SR_TS1_ITLF_Msk         /*!< Interrupt flag for low threshold for DTS  */

+#define DTS_SR_TS1_ITHF_Pos                (2U)

+#define DTS_SR_TS1_ITHF_Msk                (0x1UL << DTS_SR_TS1_ITHF_Pos) /*!< 0x00000004 */

+#define DTS_SR_TS1_ITHF                    DTS_SR_TS1_ITHF_Msk         /*!< Interrupt flag for high threshold for DTS */

+#define DTS_SR_TS1_AITEF_Pos               (4U)

+#define DTS_SR_TS1_AITEF_Msk               (0x1UL << DTS_SR_TS1_AITEF_Pos) /*!< 0x00000010 */

+#define DTS_SR_TS1_AITEF                   DTS_SR_TS1_AITEF_Msk        /*!< Asynchronous interrupt flag for end of measure for DTS */

+#define DTS_SR_TS1_AITLF_Pos               (5U)

+#define DTS_SR_TS1_AITLF_Msk               (0x1UL << DTS_SR_TS1_AITLF_Pos) /*!< 0x00000020 */

+#define DTS_SR_TS1_AITLF                   DTS_SR_TS1_AITLF_Msk        /*!< Asynchronous interrupt flag for low threshold for DTS  */

+#define DTS_SR_TS1_AITHF_Pos               (6U)

+#define DTS_SR_TS1_AITHF_Msk               (0x1UL << DTS_SR_TS1_AITHF_Pos) /*!< 0x00000040 */

+#define DTS_SR_TS1_AITHF                   DTS_SR_TS1_AITHF_Msk        /*!< Asynchronous interrupt flag for high threshold for DTS */

+#define DTS_SR_TS1_RDY_Pos                 (15U)

+#define DTS_SR_TS1_RDY_Msk                 (0x1UL << DTS_SR_TS1_RDY_Pos) /*!< 0x00008000 */

+#define DTS_SR_TS1_RDY                     DTS_SR_TS1_RDY_Msk          /*!< DTS ready flag */

+

+/******************  Bit definition for DTS_ITENR register      ******************/

+#define DTS_ITENR_TS1_ITEEN_Pos            (0U)

+#define DTS_ITENR_TS1_ITEEN_Msk            (0x1UL << DTS_ITENR_TS1_ITEEN_Pos) /*!< 0x00000001 */

+#define DTS_ITENR_TS1_ITEEN                DTS_ITENR_TS1_ITEEN_Msk     /*!< Enable interrupt flag for end of measure for DTS */

+#define DTS_ITENR_TS1_ITLEN_Pos            (1U)

+#define DTS_ITENR_TS1_ITLEN_Msk            (0x1UL << DTS_ITENR_TS1_ITLEN_Pos) /*!< 0x00000002 */

+#define DTS_ITENR_TS1_ITLEN                DTS_ITENR_TS1_ITLEN_Msk     /*!< Enable interrupt flag for low threshold for DTS  */

+#define DTS_ITENR_TS1_ITHEN_Pos            (2U)

+#define DTS_ITENR_TS1_ITHEN_Msk            (0x1UL << DTS_ITENR_TS1_ITHEN_Pos) /*!< 0x00000004 */

+#define DTS_ITENR_TS1_ITHEN                DTS_ITENR_TS1_ITHEN_Msk     /*!< Enable interrupt flag for high threshold for DTS */

+#define DTS_ITENR_TS1_AITEEN_Pos           (4U)

+#define DTS_ITENR_TS1_AITEEN_Msk           (0x1UL << DTS_ITENR_TS1_AITEEN_Pos) /*!< 0x00000010 */

+#define DTS_ITENR_TS1_AITEEN               DTS_ITENR_TS1_AITEEN_Msk    /*!< Enable asynchronous interrupt flag for end of measure for DTS */

+#define DTS_ITENR_TS1_AITLEN_Pos           (5U)

+#define DTS_ITENR_TS1_AITLEN_Msk           (0x1UL << DTS_ITENR_TS1_AITLEN_Pos) /*!< 0x00000020 */

+#define DTS_ITENR_TS1_AITLEN               DTS_ITENR_TS1_AITLEN_Msk    /*!< Enable Asynchronous interrupt flag for low threshold for DTS  */

+#define DTS_ITENR_TS1_AITHEN_Pos           (6U)

+#define DTS_ITENR_TS1_AITHEN_Msk           (0x1UL << DTS_ITENR_TS1_AITHEN_Pos) /*!< 0x00000040 */

+#define DTS_ITENR_TS1_AITHEN               DTS_ITENR_TS1_AITHEN_Msk    /*!< Enable asynchronous interrupt flag for high threshold for DTS */

+

+/******************  Bit definition for DTS_ICIFR register      ******************/

+#define DTS_ICIFR_TS1_CITEF_Pos            (0U)

+#define DTS_ICIFR_TS1_CITEF_Msk            (0x1UL << DTS_ICIFR_TS1_CITEF_Pos) /*!< 0x00000001 */

+#define DTS_ICIFR_TS1_CITEF                DTS_ICIFR_TS1_CITEF_Msk     /*!< Clear the IT flag for End Of Measure for DTS */

+#define DTS_ICIFR_TS1_CITLF_Pos            (1U)

+#define DTS_ICIFR_TS1_CITLF_Msk            (0x1UL << DTS_ICIFR_TS1_CITLF_Pos) /*!< 0x00000002 */

+#define DTS_ICIFR_TS1_CITLF                DTS_ICIFR_TS1_CITLF_Msk     /*!< Clear the IT flag for low threshold for DTS  */

+#define DTS_ICIFR_TS1_CITHF_Pos            (2U)

+#define DTS_ICIFR_TS1_CITHF_Msk            (0x1UL << DTS_ICIFR_TS1_CITHF_Pos) /*!< 0x00000004 */

+#define DTS_ICIFR_TS1_CITHF                DTS_ICIFR_TS1_CITHF_Msk     /*!< Clear the IT flag for high threshold on DTS  */

+#define DTS_ICIFR_TS1_CAITEF_Pos           (4U)

+#define DTS_ICIFR_TS1_CAITEF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITEF_Pos) /*!< 0x00000010 */

+#define DTS_ICIFR_TS1_CAITEF               DTS_ICIFR_TS1_CAITEF_Msk    /*!< Clear the asynchronous IT flag for End Of Measure for DTS */

+#define DTS_ICIFR_TS1_CAITLF_Pos           (5U)

+#define DTS_ICIFR_TS1_CAITLF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITLF_Pos) /*!< 0x00000020 */

+#define DTS_ICIFR_TS1_CAITLF               DTS_ICIFR_TS1_CAITLF_Msk    /*!< Clear the asynchronous IT flag for low threshold for DTS  */

+#define DTS_ICIFR_TS1_CAITHF_Pos           (6U)

+#define DTS_ICIFR_TS1_CAITHF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITHF_Pos) /*!< 0x00000040 */

+#define DTS_ICIFR_TS1_CAITHF               DTS_ICIFR_TS1_CAITHF_Msk    /*!< Clear the asynchronous IT flag for high threshold on DTS  */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    TIM                                     */

+/*                                                                            */

+/******************************************************************************/

+#define TIM_BREAK_INPUT_SUPPORT             /*!<TIM Break input feature */

+

+/*******************  Bit definition for TIM_CR1 register  ********************/

+#define TIM_CR1_CEN_Pos           (0U)

+#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */

+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */

+#define TIM_CR1_UDIS_Pos          (1U)

+#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */

+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */

+#define TIM_CR1_URS_Pos           (2U)

+#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */

+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */

+#define TIM_CR1_OPM_Pos           (3U)

+#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */

+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */

+#define TIM_CR1_DIR_Pos           (4U)

+#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */

+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */

+

+#define TIM_CR1_CMS_Pos           (5U)

+#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */

+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */

+#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */

+#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */

+

+#define TIM_CR1_ARPE_Pos          (7U)

+#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */

+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */

+

+#define TIM_CR1_CKD_Pos           (8U)

+#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */

+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */

+#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */

+#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */

+

+#define TIM_CR1_UIFREMAP_Pos      (11U)

+#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */

+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */

+

+/*******************  Bit definition for TIM_CR2 register  ********************/

+#define TIM_CR2_CCPC_Pos          (0U)

+#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */

+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */

+#define TIM_CR2_CCUS_Pos          (2U)

+#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */

+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */

+#define TIM_CR2_CCDS_Pos          (3U)

+#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */

+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */

+

+#define TIM_CR2_MMS_Pos           (4U)

+#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */

+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */

+#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */

+#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */

+#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */

+

+#define TIM_CR2_TI1S_Pos          (7U)

+#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */

+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */

+#define TIM_CR2_OIS1_Pos          (8U)

+#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */

+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */

+#define TIM_CR2_OIS1N_Pos         (9U)

+#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */

+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */

+#define TIM_CR2_OIS2_Pos          (10U)

+#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */

+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */

+#define TIM_CR2_OIS2N_Pos         (11U)

+#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */

+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */

+#define TIM_CR2_OIS3_Pos          (12U)

+#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */

+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */

+#define TIM_CR2_OIS3N_Pos         (13U)

+#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */

+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */

+#define TIM_CR2_OIS4_Pos          (14U)

+#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */

+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */

+#define TIM_CR2_OIS5_Pos          (16U)

+#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */

+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */

+#define TIM_CR2_OIS6_Pos          (17U)

+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */

+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */

+

+#define TIM_CR2_MMS2_Pos          (20U)

+#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */

+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */

+#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */

+#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */

+#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */

+#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */

+

+/*******************  Bit definition for TIM_SMCR register  *******************/

+#define TIM_SMCR_SMS_Pos          (0U)

+#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */

+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */

+#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */

+#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */

+#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */

+#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */

+

+#define TIM_SMCR_TS_Pos           (4U)

+#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */

+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[4:0] bits (Trigger selection) */

+#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)                /*!< 0x00000010 */

+#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)                /*!< 0x00000020 */

+#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)                /*!< 0x00000040 */

+#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)                /*!< 0x00100000 */

+#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)                /*!< 0x00200000 */

+

+#define TIM_SMCR_MSM_Pos          (7U)

+#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */

+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */

+

+#define TIM_SMCR_ETF_Pos          (8U)

+#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */

+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */

+#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */

+#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */

+#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */

+#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */

+

+#define TIM_SMCR_ETPS_Pos         (12U)

+#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */

+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */

+#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */

+#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */

+

+#define TIM_SMCR_ECE_Pos          (14U)

+#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */

+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */

+#define TIM_SMCR_ETP_Pos          (15U)

+#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */

+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */

+

+/*******************  Bit definition for TIM_DIER register  *******************/

+#define TIM_DIER_UIE_Pos          (0U)

+#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */

+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */

+#define TIM_DIER_CC1IE_Pos        (1U)

+#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */

+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */

+#define TIM_DIER_CC2IE_Pos        (2U)

+#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */

+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */

+#define TIM_DIER_CC3IE_Pos        (3U)

+#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */

+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */

+#define TIM_DIER_CC4IE_Pos        (4U)

+#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */

+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */

+#define TIM_DIER_COMIE_Pos        (5U)

+#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */

+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */

+#define TIM_DIER_TIE_Pos          (6U)

+#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */

+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */

+#define TIM_DIER_BIE_Pos          (7U)

+#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */

+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */

+#define TIM_DIER_UDE_Pos          (8U)

+#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */

+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */

+#define TIM_DIER_CC1DE_Pos        (9U)

+#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */

+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */

+#define TIM_DIER_CC2DE_Pos        (10U)

+#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */

+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */

+#define TIM_DIER_CC3DE_Pos        (11U)

+#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */

+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */

+#define TIM_DIER_CC4DE_Pos        (12U)

+#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */

+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */

+#define TIM_DIER_COMDE_Pos        (13U)

+#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */

+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */

+#define TIM_DIER_TDE_Pos          (14U)

+#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */

+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */

+

+/********************  Bit definition for TIM_SR register  ********************/

+#define TIM_SR_UIF_Pos            (0U)

+#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */

+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */

+#define TIM_SR_CC1IF_Pos          (1U)

+#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */

+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */

+#define TIM_SR_CC2IF_Pos          (2U)

+#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */

+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */

+#define TIM_SR_CC3IF_Pos          (3U)

+#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */

+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */

+#define TIM_SR_CC4IF_Pos          (4U)

+#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */

+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */

+#define TIM_SR_COMIF_Pos          (5U)

+#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */

+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */

+#define TIM_SR_TIF_Pos            (6U)

+#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */

+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */

+#define TIM_SR_BIF_Pos            (7U)

+#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */

+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */

+#define TIM_SR_B2IF_Pos           (8U)

+#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */

+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break2 interrupt Flag */

+#define TIM_SR_CC1OF_Pos          (9U)

+#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */

+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */

+#define TIM_SR_CC2OF_Pos          (10U)

+#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */

+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */

+#define TIM_SR_CC3OF_Pos          (11U)

+#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */

+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */

+#define TIM_SR_CC4OF_Pos          (12U)

+#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */

+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */

+#define TIM_SR_CC5IF_Pos          (16U)

+#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */

+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */

+#define TIM_SR_CC6IF_Pos          (17U)

+#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */

+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */

+#define TIM_SR_SBIF_Pos           (13U)

+#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */

+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!< System Break Flag */

+

+/*******************  Bit definition for TIM_EGR register  ********************/

+#define TIM_EGR_UG_Pos            (0U)

+#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */

+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */

+#define TIM_EGR_CC1G_Pos          (1U)

+#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */

+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */

+#define TIM_EGR_CC2G_Pos          (2U)

+#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */

+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */

+#define TIM_EGR_CC3G_Pos          (3U)

+#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */

+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */

+#define TIM_EGR_CC4G_Pos          (4U)

+#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */

+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */

+#define TIM_EGR_COMG_Pos          (5U)

+#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */

+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */

+#define TIM_EGR_TG_Pos            (6U)

+#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */

+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */

+#define TIM_EGR_BG_Pos            (7U)

+#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */

+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */

+#define TIM_EGR_B2G_Pos           (8U)

+#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */

+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break Generation */

+

+

+/******************  Bit definition for TIM_CCMR1 register  *******************/

+#define TIM_CCMR1_CC1S_Pos        (0U)

+#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */

+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */

+#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */

+#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */

+

+#define TIM_CCMR1_OC1FE_Pos       (2U)

+#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */

+#define TIM_CCMR1_OC1PE_Pos       (3U)

+#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */

+

+#define TIM_CCMR1_OC1M_Pos        (4U)

+#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */

+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */

+#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */

+#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */

+#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */

+#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR1_OC1CE_Pos       (7U)

+#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */

+

+#define TIM_CCMR1_CC2S_Pos        (8U)

+#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */

+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */

+#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */

+#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */

+

+#define TIM_CCMR1_OC2FE_Pos       (10U)

+#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */

+#define TIM_CCMR1_OC2PE_Pos       (11U)

+#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */

+

+#define TIM_CCMR1_OC2M_Pos        (12U)

+#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */

+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */

+#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */

+#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */

+#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */

+#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */

+

+#define TIM_CCMR1_OC2CE_Pos       (15U)

+#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */

+

+/*----------------------------------------------------------------------------*/

+

+#define TIM_CCMR1_IC1PSC_Pos      (2U)

+#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */

+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */

+#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */

+

+#define TIM_CCMR1_IC1F_Pos        (4U)

+#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */

+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */

+#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */

+

+#define TIM_CCMR1_IC2PSC_Pos      (10U)

+#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */

+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */

+#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */

+

+#define TIM_CCMR1_IC2F_Pos        (12U)

+#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */

+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */

+#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */

+

+/******************  Bit definition for TIM_CCMR2 register  *******************/

+#define TIM_CCMR2_CC3S_Pos        (0U)

+#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */

+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */

+#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */

+#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */

+

+#define TIM_CCMR2_OC3FE_Pos       (2U)

+#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */

+#define TIM_CCMR2_OC3PE_Pos       (3U)

+#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */

+

+#define TIM_CCMR2_OC3M_Pos        (4U)

+#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */

+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */

+#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR2_OC3CE_Pos       (7U)

+#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */

+

+#define TIM_CCMR2_CC4S_Pos        (8U)

+#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */

+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */

+#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */

+#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */

+

+#define TIM_CCMR2_OC4FE_Pos       (10U)

+#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */

+#define TIM_CCMR2_OC4PE_Pos       (11U)

+#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */

+

+#define TIM_CCMR2_OC4M_Pos        (12U)

+#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */

+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */

+#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */

+

+#define TIM_CCMR2_OC4CE_Pos       (15U)

+#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */

+

+/*----------------------------------------------------------------------------*/

+

+#define TIM_CCMR2_IC3PSC_Pos      (2U)

+#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */

+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */

+#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */

+

+#define TIM_CCMR2_IC3F_Pos        (4U)

+#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */

+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */

+#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */

+

+#define TIM_CCMR2_IC4PSC_Pos      (10U)

+#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */

+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */

+#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */

+

+#define TIM_CCMR2_IC4F_Pos        (12U)

+#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */

+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */

+#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */

+

+/*******************  Bit definition for TIM_CCER register  *******************/

+#define TIM_CCER_CC1E_Pos         (0U)

+#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */

+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */

+#define TIM_CCER_CC1P_Pos         (1U)

+#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */

+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */

+#define TIM_CCER_CC1NE_Pos        (2U)

+#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */

+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */

+#define TIM_CCER_CC1NP_Pos        (3U)

+#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */

+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */

+#define TIM_CCER_CC2E_Pos         (4U)

+#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */

+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */

+#define TIM_CCER_CC2P_Pos         (5U)

+#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */

+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */

+#define TIM_CCER_CC2NE_Pos        (6U)

+#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */

+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */

+#define TIM_CCER_CC2NP_Pos        (7U)

+#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */

+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */

+#define TIM_CCER_CC3E_Pos         (8U)

+#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */

+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */

+#define TIM_CCER_CC3P_Pos         (9U)

+#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */

+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */

+#define TIM_CCER_CC3NE_Pos        (10U)

+#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */

+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */

+#define TIM_CCER_CC3NP_Pos        (11U)

+#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */

+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */

+#define TIM_CCER_CC4E_Pos         (12U)

+#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */

+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */

+#define TIM_CCER_CC4P_Pos         (13U)

+#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */

+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */

+#define TIM_CCER_CC4NP_Pos        (15U)

+#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */

+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */

+#define TIM_CCER_CC5E_Pos         (16U)

+#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */

+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */

+#define TIM_CCER_CC5P_Pos         (17U)

+#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */

+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */

+#define TIM_CCER_CC6E_Pos         (20U)

+#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */

+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */

+#define TIM_CCER_CC6P_Pos         (21U)

+#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */

+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */

+/*******************  Bit definition for TIM_CNT register  ********************/

+#define TIM_CNT_CNT_Pos           (0U)

+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */

+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */

+#define TIM_CNT_UIFCPY_Pos        (31U)

+#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */

+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy */

+/*******************  Bit definition for TIM_PSC register  ********************/

+#define TIM_PSC_PSC_Pos           (0U)

+#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */

+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */

+

+/*******************  Bit definition for TIM_ARR register  ********************/

+#define TIM_ARR_ARR_Pos           (0U)

+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */

+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */

+

+/*******************  Bit definition for TIM_RCR register  ********************/

+#define TIM_RCR_REP_Pos           (0U)

+#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                  /*!< 0x000000FF */

+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */

+

+/*******************  Bit definition for TIM_CCR1 register  *******************/

+#define TIM_CCR1_CCR1_Pos         (0U)

+#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */

+

+/*******************  Bit definition for TIM_CCR2 register  *******************/

+#define TIM_CCR2_CCR2_Pos         (0U)

+#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */

+

+/*******************  Bit definition for TIM_CCR3 register  *******************/

+#define TIM_CCR3_CCR3_Pos         (0U)

+#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */

+

+/*******************  Bit definition for TIM_CCR4 register  *******************/

+#define TIM_CCR4_CCR4_Pos         (0U)

+#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */

+

+/*******************  Bit definition for TIM_CCR5 register  *******************/

+#define TIM_CCR5_CCR5_Pos         (0U)

+#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */

+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */

+#define TIM_CCR5_GC5C1_Pos        (29U)

+#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */

+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */

+#define TIM_CCR5_GC5C2_Pos        (30U)

+#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */

+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */

+#define TIM_CCR5_GC5C3_Pos        (31U)

+#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */

+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */

+

+/*******************  Bit definition for TIM_CCR6 register  *******************/

+#define TIM_CCR6_CCR6_Pos         (0U)

+#define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */

+

+/*******************  Bit definition for TIM_BDTR register  *******************/

+#define TIM_BDTR_DTG_Pos          (0U)

+#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */

+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */

+#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */

+#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */

+#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */

+#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */

+#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */

+#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */

+#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */

+#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */

+

+#define TIM_BDTR_LOCK_Pos         (8U)

+#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */

+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */

+#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */

+#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */

+

+#define TIM_BDTR_OSSI_Pos         (10U)

+#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */

+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */

+#define TIM_BDTR_OSSR_Pos         (11U)

+#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */

+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */

+#define TIM_BDTR_BKE_Pos          (12U)

+#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */

+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break1 */

+#define TIM_BDTR_BKP_Pos          (13U)

+#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */

+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break1 */

+#define TIM_BDTR_AOE_Pos          (14U)

+#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */

+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */

+#define TIM_BDTR_MOE_Pos          (15U)

+#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */

+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */

+

+#define TIM_BDTR_BKF_Pos          (16U)

+#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */

+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break1 */

+#define TIM_BDTR_BK2F_Pos         (20U)

+#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */

+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break2 */

+

+#define TIM_BDTR_BK2E_Pos         (24U)

+#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */

+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break2 */

+#define TIM_BDTR_BK2P_Pos         (25U)

+#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */

+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */

+

+/*******************  Bit definition for TIM_DCR register  ********************/

+#define TIM_DCR_DBA_Pos           (0U)

+#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */

+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */

+#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */

+#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */

+#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */

+#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */

+#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */

+

+#define TIM_DCR_DBL_Pos           (8U)

+#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */

+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */

+#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */

+#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */

+#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */

+#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */

+#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */

+

+/*******************  Bit definition for TIM_DMAR register  *******************/

+#define TIM_DMAR_DMAB_Pos         (0U)

+#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */

+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */

+

+/******************  Bit definition for TIM_CCMR3 register  *******************/

+#define TIM_CCMR3_OC5FE_Pos       (2U)

+#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */

+#define TIM_CCMR3_OC5PE_Pos       (3U)

+#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */

+

+#define TIM_CCMR3_OC5M_Pos        (4U)

+#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */

+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */

+#define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR3_OC5CE_Pos       (7U)

+#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */

+

+#define TIM_CCMR3_OC6FE_Pos       (10U)

+#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 4 Fast enable */

+#define TIM_CCMR3_OC6PE_Pos       (11U)

+#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */

+

+#define TIM_CCMR3_OC6M_Pos        (12U)

+#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */

+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */

+#define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */

+

+#define TIM_CCMR3_OC6CE_Pos       (15U)

+#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 4 Clear Enable */

+/*******************  Bit definition for TIM1_AF1 register  *********************/

+#define TIM1_AF1_BKINE_Pos        (0U)

+#define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */

+#define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */

+#define TIM1_AF1_BKCMP1E_Pos      (1U)

+#define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */

+#define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM1_AF1_BKCMP2E_Pos      (2U)

+#define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */

+#define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit */

+#define TIM1_AF1_BKDF1BK0E_Pos    (8U)

+#define TIM1_AF1_BKDF1BK0E_Msk    (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)            /*!< 0x00000100 */

+#define TIM1_AF1_BKDF1BK0E        TIM1_AF1_BKDF1BK0E_Msk                       /*!<BKDF1BK0E Break input DFSDM Break 0 */

+#define TIM1_AF1_BKINP_Pos        (9U)

+#define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */

+#define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */

+#define TIM1_AF1_BKCMP1P_Pos      (10U)

+#define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */

+#define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM1_AF1_BKCMP2P_Pos      (11U)

+#define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */

+#define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */

+

+#define TIM1_AF1_ETRSEL_Pos       (14U)

+#define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */

+#define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */

+#define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00004000 */

+#define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00008000 */

+#define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00010000 */

+#define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM1_AF2 register  *********************/

+#define TIM1_AF2_BK2INE_Pos       (0U)

+#define TIM1_AF2_BK2INE_Msk       (0x1UL << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */

+#define TIM1_AF2_BK2INE           TIM1_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */

+#define TIM1_AF2_BK2CMP1E_Pos     (1U)

+#define TIM1_AF2_BK2CMP1E_Msk     (0x1UL << TIM1_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */

+#define TIM1_AF2_BK2CMP1E         TIM1_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */

+#define TIM1_AF2_BK2CMP2E_Pos     (2U)

+#define TIM1_AF2_BK2CMP2E_Msk     (0x1UL << TIM1_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */

+#define TIM1_AF2_BK2CMP2E         TIM1_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */

+#define TIM1_AF2_BK2DFBK1E_Pos    (8U)

+#define TIM1_AF2_BK2DFBK1E_Msk    (0x1UL << TIM1_AF2_BK2DFBK1E_Pos)            /*!< 0x00000100 */

+#define TIM1_AF2_BK2DFBK1E        TIM1_AF2_BK2DFBK1E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 1 */

+#define TIM1_AF2_BK2INP_Pos       (9U)

+#define TIM1_AF2_BK2INP_Msk       (0x1UL << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */

+#define TIM1_AF2_BK2INP           TIM1_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */

+#define TIM1_AF2_BK2CMP1P_Pos     (10U)

+#define TIM1_AF2_BK2CMP1P_Msk     (0x1UL << TIM1_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */

+#define TIM1_AF2_BK2CMP1P         TIM1_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */

+#define TIM1_AF2_BK2CMP2P_Pos     (11U)

+#define TIM1_AF2_BK2CMP2P_Msk     (0x1UL << TIM1_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */

+#define TIM1_AF2_BK2CMP2P         TIM1_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */

+

+/*******************  Bit definition for TIM_TISEL register  *********************/

+#define TIM_TISEL_TI1SEL_Pos      (0U)

+#define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */

+#define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/

+#define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000001 */

+#define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000002 */

+#define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000004 */

+#define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000008 */

+

+#define TIM_TISEL_TI2SEL_Pos      (8U)

+#define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */

+#define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/

+#define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000100 */

+#define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000200 */

+#define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000400 */

+#define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000800 */

+

+#define TIM_TISEL_TI3SEL_Pos      (16U)

+#define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */

+#define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/

+#define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00010000 */

+#define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00020000 */

+#define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00040000 */

+#define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00080000 */

+

+#define TIM_TISEL_TI4SEL_Pos      (24U)

+#define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */

+#define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/

+#define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x01000000 */

+#define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x02000000 */

+#define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x04000000 */

+#define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x08000000 */

+

+/*******************  Bit definition for TIM8_AF1 register  *********************/

+#define TIM8_AF1_BKINE_Pos        (0U)

+#define TIM8_AF1_BKINE_Msk        (0x1UL << TIM8_AF1_BKINE_Pos)                /*!< 0x00000001 */

+#define TIM8_AF1_BKINE            TIM8_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */

+#define TIM8_AF1_BKCMP1E_Pos      (1U)

+#define TIM8_AF1_BKCMP1E_Msk      (0x1UL << TIM8_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */

+#define TIM8_AF1_BKCMP1E          TIM8_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM8_AF1_BKCMP2E_Pos      (2U)

+#define TIM8_AF1_BKCMP2E_Msk      (0x1UL << TIM8_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */

+#define TIM8_AF1_BKCMP2E          TIM8_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM8_AF1_BKDFBK2E_Pos     (8U)

+#define TIM8_AF1_BKDFBK2E_Msk     (0x1UL << TIM8_AF1_BKDFBK2E_Pos)             /*!< 0x00000100 */

+#define TIM8_AF1_BKDFBK2E         TIM8_AF1_BKDFBK2E_Msk                        /*!<BKDFBK2E Break input DFSDM Break 2 */

+#define TIM8_AF1_BKINP_Pos        (9U)

+#define TIM8_AF1_BKINP_Msk        (0x1UL << TIM8_AF1_BKINP_Pos)                /*!< 0x00000200 */

+#define TIM8_AF1_BKINP            TIM8_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */

+#define TIM8_AF1_BKCMP1P_Pos      (10U)

+#define TIM8_AF1_BKCMP1P_Msk      (0x1UL << TIM8_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */

+#define TIM8_AF1_BKCMP1P          TIM8_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM8_AF1_BKCMP2P_Pos      (11U)

+#define TIM8_AF1_BKCMP2P_Msk      (0x1UL << TIM8_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */

+#define TIM8_AF1_BKCMP2P          TIM8_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */

+

+#define TIM8_AF1_ETRSEL_Pos       (14U)

+#define TIM8_AF1_ETRSEL_Msk       (0xFUL << TIM8_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */

+#define TIM8_AF1_ETRSEL           TIM8_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */

+#define TIM8_AF1_ETRSEL_0         (0x1UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00004000 */

+#define TIM8_AF1_ETRSEL_1         (0x2UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00008000 */

+#define TIM8_AF1_ETRSEL_2         (0x4UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00010000 */

+#define TIM8_AF1_ETRSEL_3         (0x8UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00020000 */

+/*******************  Bit definition for TIM8_AF2 register  *********************/

+#define TIM8_AF2_BK2INE_Pos       (0U)

+#define TIM8_AF2_BK2INE_Msk       (0x1UL << TIM8_AF2_BK2INE_Pos)               /*!< 0x00000001 */

+#define TIM8_AF2_BK2INE           TIM8_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */

+#define TIM8_AF2_BK2CMP1E_Pos     (1U)

+#define TIM8_AF2_BK2CMP1E_Msk     (0x1UL << TIM8_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */

+#define TIM8_AF2_BK2CMP1E         TIM8_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */

+#define TIM8_AF2_BK2CMP2E_Pos     (2U)

+#define TIM8_AF2_BK2CMP2E_Msk     (0x1UL << TIM8_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */

+#define TIM8_AF2_BK2CMP2E         TIM8_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */

+#define TIM8_AF2_BK2DFBK3E_Pos    (8U)

+#define TIM8_AF2_BK2DFBK3E_Msk    (0x1UL << TIM8_AF2_BK2DFBK3E_Pos)            /*!< 0x00000100 */

+#define TIM8_AF2_BK2DFBK3E        TIM8_AF2_BK2DFBK3E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 3 */

+#define TIM8_AF2_BK2INP_Pos       (9U)

+#define TIM8_AF2_BK2INP_Msk       (0x1UL << TIM8_AF2_BK2INP_Pos)               /*!< 0x00000200 */

+#define TIM8_AF2_BK2INP           TIM8_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */

+#define TIM8_AF2_BK2CMP1P_Pos     (10U)

+#define TIM8_AF2_BK2CMP1P_Msk     (0x1UL << TIM8_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */

+#define TIM8_AF2_BK2CMP1P         TIM8_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */

+#define TIM8_AF2_BK2CMP2P_Pos     (11U)

+#define TIM8_AF2_BK2CMP2P_Msk     (0x1UL << TIM8_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */

+#define TIM8_AF2_BK2CMP2P         TIM8_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */

+

+/*******************  Bit definition for TIM2_AF1 register  *********************/

+#define TIM2_AF1_ETRSEL_Pos      (14U)

+#define TIM2_AF1_ETRSEL_Msk      (0xFUL << TIM2_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM2_AF1_ETRSEL          TIM2_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */

+#define TIM2_AF1_ETRSEL_0        (0x1UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM2_AF1_ETRSEL_1        (0x2UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM2_AF1_ETRSEL_2        (0x4UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM2_AF1_ETRSEL_3        (0x8UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM3_AF1 register  *********************/

+#define TIM3_AF1_ETRSEL_Pos      (14U)

+#define TIM3_AF1_ETRSEL_Msk      (0xFUL << TIM3_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM3_AF1_ETRSEL          TIM3_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */

+#define TIM3_AF1_ETRSEL_0        (0x1UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM3_AF1_ETRSEL_1        (0x2UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM3_AF1_ETRSEL_2        (0x4UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM3_AF1_ETRSEL_3        (0x8UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM5_AF1 register  *********************/

+#define TIM5_AF1_ETRSEL_Pos      (14U)

+#define TIM5_AF1_ETRSEL_Msk      (0xFUL << TIM5_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM5_AF1_ETRSEL          TIM5_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */

+#define TIM5_AF1_ETRSEL_0        (0x1UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM5_AF1_ETRSEL_1        (0x2UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM5_AF1_ETRSEL_2        (0x4UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM5_AF1_ETRSEL_3        (0x8UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM15_AF1 register  *********************/

+#define TIM15_AF1_BKINE_Pos        (0U)

+#define TIM15_AF1_BKINE_Msk        (0x1UL << TIM15_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM15_AF1_BKINE            TIM15_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM15_AF1_BKCMP1E_Pos      (1U)

+#define TIM15_AF1_BKCMP1E_Msk      (0x1UL << TIM15_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM15_AF1_BKCMP1E          TIM15_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM15_AF1_BKCMP2E_Pos      (2U)

+#define TIM15_AF1_BKCMP2E_Msk      (0x1UL << TIM15_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM15_AF1_BKCMP2E          TIM15_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM15_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM15_AF1_BKDF1BK2E_Msk    (0x1UL << TIM15_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM15_AF1_BKDF1BK2E        TIM15_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[0] enable */

+#define TIM15_AF1_BKINP_Pos        (9U)

+#define TIM15_AF1_BKINP_Msk        (0x1UL << TIM15_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM15_AF1_BKINP            TIM15_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM15_AF1_BKCMP1P_Pos      (10U)

+#define TIM15_AF1_BKCMP1P_Msk      (0x1UL << TIM15_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM15_AF1_BKCMP1P          TIM15_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM15_AF1_BKCMP2P_Pos      (11U)

+#define TIM15_AF1_BKCMP2P_Msk      (0x1UL << TIM15_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM15_AF1_BKCMP2P          TIM15_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/*******************  Bit definition for TIM16_ register  *********************/

+#define TIM16_AF1_BKINE_Pos        (0U)

+#define TIM16_AF1_BKINE_Msk        (0x1UL << TIM16_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM16_AF1_BKINE            TIM16_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM16_AF1_BKCMP1E_Pos      (1U)

+#define TIM16_AF1_BKCMP1E_Msk      (0x1UL << TIM16_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM16_AF1_BKCMP1E          TIM16_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM16_AF1_BKCMP2E_Pos      (2U)

+#define TIM16_AF1_BKCMP2E_Msk      (0x1UL << TIM16_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM16_AF1_BKCMP2E          TIM16_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM16_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM16_AF1_BKDF1BK2E_Msk    (0x1UL << TIM16_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM16_AF1_BKDF1BK2E        TIM16_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[1] enable */

+#define TIM16_AF1_BKINP_Pos        (9U)

+#define TIM16_AF1_BKINP_Msk        (0x1UL << TIM16_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM16_AF1_BKINP            TIM16_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM16_AF1_BKCMP1P_Pos      (10U)

+#define TIM16_AF1_BKCMP1P_Msk      (0x1UL << TIM16_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM16_AF1_BKCMP1P          TIM16_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM16_AF1_BKCMP2P_Pos      (11U)

+#define TIM16_AF1_BKCMP2P_Msk      (0x1UL << TIM16_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM16_AF1_BKCMP2P          TIM16_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/*******************  Bit definition for TIM17_AF1 register  *********************/

+#define TIM17_AF1_BKINE_Pos        (0U)

+#define TIM17_AF1_BKINE_Msk        (0x1UL << TIM17_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM17_AF1_BKINE            TIM17_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM17_AF1_BKCMP1E_Pos      (1U)

+#define TIM17_AF1_BKCMP1E_Msk      (0x1UL << TIM17_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM17_AF1_BKCMP1E          TIM17_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM17_AF1_BKCMP2E_Pos      (2U)

+#define TIM17_AF1_BKCMP2E_Msk      (0x1UL << TIM17_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM17_AF1_BKCMP2E          TIM17_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM17_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM17_AF1_BKDF1BK2E_Msk    (0x1UL << TIM17_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM17_AF1_BKDF1BK2E        TIM17_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[2] enable */

+#define TIM17_AF1_BKINP_Pos        (9U)

+#define TIM17_AF1_BKINP_Msk        (0x1UL << TIM17_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM17_AF1_BKINP            TIM17_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM17_AF1_BKCMP1P_Pos      (10U)

+#define TIM17_AF1_BKCMP1P_Msk      (0x1UL << TIM17_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM17_AF1_BKCMP1P          TIM17_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM17_AF1_BKCMP2P_Pos      (11U)

+#define TIM17_AF1_BKCMP2P_Msk      (0x1UL << TIM17_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM17_AF1_BKCMP2P          TIM17_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Low Power Timer (LPTTIM)                           */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for LPTIM_ISR register  *******************/

+#define LPTIM_ISR_CMPM_Pos          (0U)

+#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */

+#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */

+#define LPTIM_ISR_ARRM_Pos          (1U)

+#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */

+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */

+#define LPTIM_ISR_EXTTRIG_Pos       (2U)

+#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */

+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */

+#define LPTIM_ISR_CMPOK_Pos         (3U)

+#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */

+#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */

+#define LPTIM_ISR_ARROK_Pos         (4U)

+#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */

+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */

+#define LPTIM_ISR_UP_Pos            (5U)

+#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */

+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */

+#define LPTIM_ISR_DOWN_Pos          (6U)

+#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */

+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */

+

+/******************  Bit definition for LPTIM_ICR register  *******************/

+#define LPTIM_ICR_CMPMCF_Pos        (0U)

+#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */

+#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */

+#define LPTIM_ICR_ARRMCF_Pos        (1U)

+#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */

+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */

+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)

+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */

+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */

+#define LPTIM_ICR_CMPOKCF_Pos       (3U)

+#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */

+#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */

+#define LPTIM_ICR_ARROKCF_Pos       (4U)

+#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */

+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */

+#define LPTIM_ICR_UPCF_Pos          (5U)

+#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */

+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */

+#define LPTIM_ICR_DOWNCF_Pos        (6U)

+#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */

+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */

+

+/******************  Bit definition for LPTIM_IER register ********************/

+#define LPTIM_IER_CMPMIE_Pos        (0U)

+#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */

+#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */

+#define LPTIM_IER_ARRMIE_Pos        (1U)

+#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */

+#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */

+#define LPTIM_IER_EXTTRIGIE_Pos     (2U)

+#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */

+#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */

+#define LPTIM_IER_CMPOKIE_Pos       (3U)

+#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */

+#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */

+#define LPTIM_IER_ARROKIE_Pos       (4U)

+#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */

+#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */

+#define LPTIM_IER_UPIE_Pos          (5U)

+#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */

+#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */

+#define LPTIM_IER_DOWNIE_Pos        (6U)

+#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */

+#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */

+

+/******************  Bit definition for LPTIM_CFGR register *******************/

+#define LPTIM_CFGR_CKSEL_Pos        (0U)

+#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */

+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */

+

+#define LPTIM_CFGR_CKPOL_Pos        (1U)

+#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */

+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */

+#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */

+#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */

+

+#define LPTIM_CFGR_CKFLT_Pos        (3U)

+#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */

+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */

+#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */

+#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */

+

+#define LPTIM_CFGR_TRGFLT_Pos       (6U)

+#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */

+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */

+#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */

+#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */

+

+#define LPTIM_CFGR_PRESC_Pos        (9U)

+#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */

+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */

+#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */

+#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */

+#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */

+

+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)

+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */

+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */

+#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */

+#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */

+#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */

+

+#define LPTIM_CFGR_TRIGEN_Pos       (17U)

+#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */

+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */

+#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */

+#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */

+

+#define LPTIM_CFGR_TIMOUT_Pos       (19U)

+#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */

+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */

+#define LPTIM_CFGR_WAVE_Pos         (20U)

+#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */

+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */

+#define LPTIM_CFGR_WAVPOL_Pos       (21U)

+#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */

+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */

+#define LPTIM_CFGR_PRELOAD_Pos      (22U)

+#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */

+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */

+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)

+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */

+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */

+#define LPTIM_CFGR_ENC_Pos          (24U)

+#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */

+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */

+

+/******************  Bit definition for LPTIM_CR register  ********************/

+#define LPTIM_CR_ENABLE_Pos         (0U)

+#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */

+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */

+#define LPTIM_CR_SNGSTRT_Pos        (1U)

+#define LPTIM_CR_SNGSTRT_Msk        (0x40001UL << LPTIM_CR_SNGSTRT_Pos)        /*!< 0x00080002 */

+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */

+#define LPTIM_CR_CNTSTRT_Pos        (2U)

+#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */

+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */

+#define LPTIM_CR_COUNTRST_Pos       (3U)

+#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */

+#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Timer Counter reset in synchronous mode*/

+#define LPTIM_CR_RSTARE_Pos         (4U)

+#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */

+#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Timer Counter reset after read enable (asynchronously)*/

+

+

+/******************  Bit definition for LPTIM_CMP register  *******************/

+#define LPTIM_CMP_CMP_Pos           (0U)

+#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */

+

+/******************  Bit definition for LPTIM_ARR register  *******************/

+#define LPTIM_ARR_ARR_Pos           (0U)

+#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */

+

+/******************  Bit definition for LPTIM_CNT register  *******************/

+#define LPTIM_CNT_CNT_Pos           (0U)

+#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */

+

+/******************  Bit definition for LPTIM_CFGR2 register  *****************/

+#define LPTIM_CFGR2_IN1SEL_Pos      (0U)

+#define LPTIM_CFGR2_IN1SEL_Msk      (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000003 */

+#define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< IN1SEL[1:0] bits (Remap selection) */

+#define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000001 */

+#define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000002 */

+#define LPTIM_CFGR2_IN2SEL_Pos      (4U)

+#define LPTIM_CFGR2_IN2SEL_Msk      (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000030 */

+#define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< IN2SEL[5:4] bits (Remap selection) */

+#define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000010 */

+#define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000020 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    OCTOSPI                                 */

+/*                                                                            */

+/******************************************************************************/

+/*****************  Bit definition for OCTOSPI_CR register  *******************/

+#define OCTOSPI_CR_EN_Pos              (0U)

+#define OCTOSPI_CR_EN_Msk              (0x1UL << OCTOSPI_CR_EN_Pos)             /*!< 0x00000001 */

+#define OCTOSPI_CR_EN                  OCTOSPI_CR_EN_Msk                       /*!< Enable */

+#define OCTOSPI_CR_ABORT_Pos           (1U)

+#define OCTOSPI_CR_ABORT_Msk           (0x1UL << OCTOSPI_CR_ABORT_Pos)          /*!< 0x00000002 */

+#define OCTOSPI_CR_ABORT               OCTOSPI_CR_ABORT_Msk                    /*!< Abort request */

+#define OCTOSPI_CR_DMAEN_Pos           (2U)

+#define OCTOSPI_CR_DMAEN_Msk           (0x1UL << OCTOSPI_CR_DMAEN_Pos)          /*!< 0x00000004 */

+#define OCTOSPI_CR_DMAEN               OCTOSPI_CR_DMAEN_Msk                    /*!< DMA Enable */

+#define OCTOSPI_CR_TCEN_Pos            (3U)

+#define OCTOSPI_CR_TCEN_Msk            (0x1UL << OCTOSPI_CR_TCEN_Pos)           /*!< 0x00000008 */

+#define OCTOSPI_CR_TCEN                OCTOSPI_CR_TCEN_Msk                     /*!< Timeout Counter Enable */

+#define OCTOSPI_CR_DQM_Pos             (6U)

+#define OCTOSPI_CR_DQM_Msk             (0x1UL << OCTOSPI_CR_DQM_Pos)            /*!< 0x00000040 */

+#define OCTOSPI_CR_DQM                 OCTOSPI_CR_DQM_Msk                      /*!< Dual-Quad Mode */

+#define OCTOSPI_CR_FSEL_Pos            (7U)

+#define OCTOSPI_CR_FSEL_Msk            (0x1UL << OCTOSPI_CR_FSEL_Pos)           /*!< 0x00000080 */

+#define OCTOSPI_CR_FSEL                OCTOSPI_CR_FSEL_Msk                     /*!< Flash Select */

+#define OCTOSPI_CR_FTHRES_Pos          (8U)

+#define OCTOSPI_CR_FTHRES_Msk          (0x1FUL << OCTOSPI_CR_FTHRES_Pos)        /*!< 0x00001F00 */

+#define OCTOSPI_CR_FTHRES              OCTOSPI_CR_FTHRES_Msk                   /*!< FIFO Threshold Level */

+#define OCTOSPI_CR_TEIE_Pos            (16U)

+#define OCTOSPI_CR_TEIE_Msk            (0x1UL << OCTOSPI_CR_TEIE_Pos)           /*!< 0x00010000 */

+#define OCTOSPI_CR_TEIE                OCTOSPI_CR_TEIE_Msk                     /*!< Transfer Error Interrupt Enable */

+#define OCTOSPI_CR_TCIE_Pos            (17U)

+#define OCTOSPI_CR_TCIE_Msk            (0x1UL << OCTOSPI_CR_TCIE_Pos)           /*!< 0x00020000 */

+#define OCTOSPI_CR_TCIE                OCTOSPI_CR_TCIE_Msk                     /*!< Transfer Complete Interrupt Enable */

+#define OCTOSPI_CR_FTIE_Pos            (18U)

+#define OCTOSPI_CR_FTIE_Msk            (0x1UL << OCTOSPI_CR_FTIE_Pos)           /*!< 0x00040000 */

+#define OCTOSPI_CR_FTIE                OCTOSPI_CR_FTIE_Msk                     /*!< FIFO Threshold Interrupt Enable */

+#define OCTOSPI_CR_SMIE_Pos            (19U)

+#define OCTOSPI_CR_SMIE_Msk            (0x1UL << OCTOSPI_CR_SMIE_Pos)           /*!< 0x00080000 */

+#define OCTOSPI_CR_SMIE                OCTOSPI_CR_SMIE_Msk                     /*!< Status Match Interrupt Enable */

+#define OCTOSPI_CR_TOIE_Pos            (20U)

+#define OCTOSPI_CR_TOIE_Msk            (0x1UL << OCTOSPI_CR_TOIE_Pos)           /*!< 0x00100000 */

+#define OCTOSPI_CR_TOIE                OCTOSPI_CR_TOIE_Msk                     /*!< TimeOut Interrupt Enable */

+#define OCTOSPI_CR_APMS_Pos            (22U)

+#define OCTOSPI_CR_APMS_Msk            (0x1UL << OCTOSPI_CR_APMS_Pos)           /*!< 0x00400000 */

+#define OCTOSPI_CR_APMS                OCTOSPI_CR_APMS_Msk                     /*!< Automatic Poll Mode Stop */

+#define OCTOSPI_CR_PMM_Pos             (23U)

+#define OCTOSPI_CR_PMM_Msk             (0x1UL << OCTOSPI_CR_PMM_Pos)            /*!< 0x00800000 */

+#define OCTOSPI_CR_PMM                 OCTOSPI_CR_PMM_Msk                      /*!< Polling Match Mode */

+#define OCTOSPI_CR_FMODE_Pos           (28U)

+#define OCTOSPI_CR_FMODE_Msk           (0x3UL << OCTOSPI_CR_FMODE_Pos)          /*!< 0x30000000 */

+#define OCTOSPI_CR_FMODE               OCTOSPI_CR_FMODE_Msk                    /*!< Functional Mode */

+#define OCTOSPI_CR_FMODE_0             (0x1UL << OCTOSPI_CR_FMODE_Pos)          /*!< 0x10000000 */

+#define OCTOSPI_CR_FMODE_1             (0x2UL << OCTOSPI_CR_FMODE_Pos)          /*!< 0x20000000 */

+

+/****************  Bit definition for OCTOSPI_DCR1 register  ******************/

+#define OCTOSPI_DCR1_CKMODE_Pos        (0U)

+#define OCTOSPI_DCR1_CKMODE_Msk        (0x1UL << OCTOSPI_DCR1_CKMODE_Pos)       /*!< 0x00000001 */

+#define OCTOSPI_DCR1_CKMODE            OCTOSPI_DCR1_CKMODE_Msk                 /*!< Mode 0 / Mode 3 */

+#define OCTOSPI_DCR1_FRCK_Pos          (1U)

+#define OCTOSPI_DCR1_FRCK_Msk          (0x1UL << OCTOSPI_DCR1_FRCK_Pos)         /*!< 0x00000002 */

+#define OCTOSPI_DCR1_FRCK              OCTOSPI_DCR1_FRCK_Msk                   /*!< Free Running Clock */

+#define OCTOSPI_DCR1_DLYBYP_Pos        (3U)

+#define OCTOSPI_DCR1_DLYBYP_Msk        (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos)       /*!< 0x00000008 */

+#define OCTOSPI_DCR1_DLYBYP            OCTOSPI_DCR1_DLYBYP_Msk                 /*!< Delay Block */

+#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)

+#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */

+#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */

+#define OCTOSPI_DCR1_CSHT_Pos          (8U)

+#define OCTOSPI_DCR1_CSHT_Msk          (0x7UL << OCTOSPI_DCR1_CSHT_Pos)         /*!< 0x00000700 */

+#define OCTOSPI_DCR1_CSHT              OCTOSPI_DCR1_CSHT_Msk                   /*!< Chip Select High Time */

+#define OCTOSPI_DCR1_DEVSIZE_Pos       (16U)

+#define OCTOSPI_DCR1_DEVSIZE_Msk       (0x1FUL << OCTOSPI_DCR1_DEVSIZE_Pos)     /*!< 0x001F0000 */

+#define OCTOSPI_DCR1_DEVSIZE           OCTOSPI_DCR1_DEVSIZE_Msk                /*!< Device Size */

+#define OCTOSPI_DCR1_MTYP_Pos          (24U)

+#define OCTOSPI_DCR1_MTYP_Msk          (0x7UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x07000000 */

+#define OCTOSPI_DCR1_MTYP              OCTOSPI_DCR1_MTYP_Msk                   /*!< Memory Type */

+#define OCTOSPI_DCR1_MTYP_0            (0x1UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x01000000 */

+#define OCTOSPI_DCR1_MTYP_1            (0x2UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x02000000 */

+#define OCTOSPI_DCR1_MTYP_2            (0x4UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x04000000 */

+

+/****************  Bit definition for OCTOSPI_DCR2 register  ******************/

+#define OCTOSPI_DCR2_PRESCALER_Pos     (0U)

+#define OCTOSPI_DCR2_PRESCALER_Msk     (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos)   /*!< 0x000000FF */

+#define OCTOSPI_DCR2_PRESCALER         OCTOSPI_DCR2_PRESCALER_Msk              /*!< Clock prescaler */

+#define OCTOSPI_DCR2_WRAPSIZE_Pos      (16U)

+#define OCTOSPI_DCR2_WRAPSIZE_Msk      (0x7UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00070000 */

+#define OCTOSPI_DCR2_WRAPSIZE          OCTOSPI_DCR2_WRAPSIZE_Msk               /*!< Wrap Size */

+#define OCTOSPI_DCR2_WRAPSIZE_0        (0x1UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00010000 */

+#define OCTOSPI_DCR2_WRAPSIZE_1        (0x2UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00020000 */

+#define OCTOSPI_DCR2_WRAPSIZE_2        (0x4UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00040000 */

+

+/****************  Bit definition for OCTOSPI_DCR3 register  ******************/

+#define OCTOSPI_DCR3_MAXTRAN_Pos       (0U)

+#define OCTOSPI_DCR3_MAXTRAN_Msk       (0xFFUL << OCTOSPI_DCR3_MAXTRAN_Pos)     /*!< 0x000000FF */

+#define OCTOSPI_DCR3_MAXTRAN           OCTOSPI_DCR3_MAXTRAN_Msk                /*!< Maximum Transfer */

+#define OCTOSPI_DCR3_CSBOUND_Pos       (16U)

+#define OCTOSPI_DCR3_CSBOUND_Msk       (0x1FUL << OCTOSPI_DCR3_CSBOUND_Pos)     /*!< 0x001F0000 */

+#define OCTOSPI_DCR3_CSBOUND           OCTOSPI_DCR3_CSBOUND_Msk                /*!< CS Boundary */

+

+/****************  Bit definition for OCTOSPI_DCR4 register  ******************/

+#define OCTOSPI_DCR4_REFRESH_Pos       (0U)

+#define OCTOSPI_DCR4_REFRESH_Msk       (0xFFFFFFFFUL << OCTOSPI_DCR4_REFRESH_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_DCR4_REFRESH           OCTOSPI_DCR4_REFRESH_Msk                /*!< Refresh rate */

+

+/*****************  Bit definition for OCTOSPI_SR register  *******************/

+#define OCTOSPI_SR_TEF_Pos             (0U)

+#define OCTOSPI_SR_TEF_Msk             (0x1UL << OCTOSPI_SR_TEF_Pos)            /*!< 0x00000001 */

+#define OCTOSPI_SR_TEF                 OCTOSPI_SR_TEF_Msk                      /*!< Transfer Error Flag */

+#define OCTOSPI_SR_TCF_Pos             (1U)

+#define OCTOSPI_SR_TCF_Msk             (0x1UL << OCTOSPI_SR_TCF_Pos)            /*!< 0x00000002 */

+#define OCTOSPI_SR_TCF                 OCTOSPI_SR_TCF_Msk                      /*!< Transfer Complete Flag */

+#define OCTOSPI_SR_FTF_Pos             (2U)

+#define OCTOSPI_SR_FTF_Msk             (0x1UL << OCTOSPI_SR_FTF_Pos)            /*!< 0x00000004 */

+#define OCTOSPI_SR_FTF                 OCTOSPI_SR_FTF_Msk                      /*!< FIFO Threshold Flag */

+#define OCTOSPI_SR_SMF_Pos             (3U)

+#define OCTOSPI_SR_SMF_Msk             (0x1UL << OCTOSPI_SR_SMF_Pos)            /*!< 0x00000008 */

+#define OCTOSPI_SR_SMF                 OCTOSPI_SR_SMF_Msk                      /*!< Status Match Flag */

+#define OCTOSPI_SR_TOF_Pos             (4U)

+#define OCTOSPI_SR_TOF_Msk             (0x1UL << OCTOSPI_SR_TOF_Pos)            /*!< 0x00000010 */

+#define OCTOSPI_SR_TOF                 OCTOSPI_SR_TOF_Msk                      /*!< Timeout Flag */

+#define OCTOSPI_SR_BUSY_Pos            (5U)

+#define OCTOSPI_SR_BUSY_Msk            (0x1UL << OCTOSPI_SR_BUSY_Pos)           /*!< 0x00000020 */

+#define OCTOSPI_SR_BUSY                OCTOSPI_SR_BUSY_Msk                     /*!< Busy */

+#define OCTOSPI_SR_FLEVEL_Pos          (8U)

+#define OCTOSPI_SR_FLEVEL_Msk          (0x3FUL << OCTOSPI_SR_FLEVEL_Pos)        /*!< 0x00003F00 */

+#define OCTOSPI_SR_FLEVEL              OCTOSPI_SR_FLEVEL_Msk                   /*!< FIFO Level */

+

+/****************  Bit definition for OCTOSPI_FCR register  *******************/

+#define OCTOSPI_FCR_CTEF_Pos           (0U)

+#define OCTOSPI_FCR_CTEF_Msk           (0x1UL << OCTOSPI_FCR_CTEF_Pos)          /*!< 0x00000001 */

+#define OCTOSPI_FCR_CTEF               OCTOSPI_FCR_CTEF_Msk                    /*!< Clear Transfer Error Flag */

+#define OCTOSPI_FCR_CTCF_Pos           (1U)

+#define OCTOSPI_FCR_CTCF_Msk           (0x1UL << OCTOSPI_FCR_CTCF_Pos)          /*!< 0x00000002 */

+#define OCTOSPI_FCR_CTCF               OCTOSPI_FCR_CTCF_Msk                    /*!< Clear Transfer Complete Flag */

+#define OCTOSPI_FCR_CSMF_Pos           (3U)

+#define OCTOSPI_FCR_CSMF_Msk           (0x1UL << OCTOSPI_FCR_CSMF_Pos)          /*!< 0x00000008 */

+#define OCTOSPI_FCR_CSMF               OCTOSPI_FCR_CSMF_Msk                    /*!< Clear Status Match Flag */

+#define OCTOSPI_FCR_CTOF_Pos           (4U)

+#define OCTOSPI_FCR_CTOF_Msk           (0x1UL << OCTOSPI_FCR_CTOF_Pos)          /*!< 0x00000010 */

+#define OCTOSPI_FCR_CTOF               OCTOSPI_FCR_CTOF_Msk                    /*!< Clear Timeout Flag */

+

+/****************  Bit definition for OCTOSPI_DLR register  *******************/

+#define OCTOSPI_DLR_DL_Pos             (0U)

+#define OCTOSPI_DLR_DL_Msk             (0xFFFFFFFFUL << OCTOSPI_DLR_DL_Pos)     /*!< 0xFFFFFFFF */

+#define OCTOSPI_DLR_DL                 OCTOSPI_DLR_DL_Msk                      /*!< Data Length */

+

+/*****************  Bit definition for OCTOSPI_AR register  *******************/

+#define OCTOSPI_AR_ADDRESS_Pos         (0U)

+#define OCTOSPI_AR_ADDRESS_Msk         (0xFFFFFFFFUL << OCTOSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_AR_ADDRESS             OCTOSPI_AR_ADDRESS_Msk                  /*!< Address */

+

+/*****************  Bit definition for OCTOSPI_DR register  *******************/

+#define OCTOSPI_DR_DATA_Pos            (0U)

+#define OCTOSPI_DR_DATA_Msk            (0xFFFFFFFFUL << OCTOSPI_DR_DATA_Pos)    /*!< 0xFFFFFFFF */

+#define OCTOSPI_DR_DATA                OCTOSPI_DR_DATA_Msk                     /*!< Data */

+

+/***************  Bit definition for OCTOSPI_PSMKR register  ******************/

+#define OCTOSPI_PSMKR_MASK_Pos         (0U)

+#define OCTOSPI_PSMKR_MASK_Msk         (0xFFFFFFFFUL << OCTOSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_PSMKR_MASK             OCTOSPI_PSMKR_MASK_Msk                  /*!< Status mask */

+

+/***************  Bit definition for OCTOSPI_PSMAR register  ******************/

+#define OCTOSPI_PSMAR_MATCH_Pos        (0U)

+#define OCTOSPI_PSMAR_MATCH_Msk        (0xFFFFFFFFUL << OCTOSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_PSMAR_MATCH            OCTOSPI_PSMAR_MATCH_Msk                 /*!< Status match */

+

+/****************  Bit definition for OCTOSPI_PIR register  *******************/

+#define OCTOSPI_PIR_INTERVAL_Pos       (0U)

+#define OCTOSPI_PIR_INTERVAL_Msk       (0xFFFFUL << OCTOSPI_PIR_INTERVAL_Pos)   /*!< 0x0000FFFF */

+#define OCTOSPI_PIR_INTERVAL           OCTOSPI_PIR_INTERVAL_Msk                /*!< Polling Interval */

+

+/****************  Bit definition for OCTOSPI_CCR register  *******************/

+#define OCTOSPI_CCR_IMODE_Pos          (0U)

+#define OCTOSPI_CCR_IMODE_Msk          (0x7UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000007 */

+#define OCTOSPI_CCR_IMODE              OCTOSPI_CCR_IMODE_Msk                   /*!< Instruction Mode */

+#define OCTOSPI_CCR_IMODE_0            (0x1UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000001 */

+#define OCTOSPI_CCR_IMODE_1            (0x2UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000002 */

+#define OCTOSPI_CCR_IMODE_2            (0x4UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000004 */

+#define OCTOSPI_CCR_IDTR_Pos           (3U)

+#define OCTOSPI_CCR_IDTR_Msk           (0x1UL << OCTOSPI_CCR_IDTR_Pos)          /*!< 0x00000008 */

+#define OCTOSPI_CCR_IDTR               OCTOSPI_CCR_IDTR_Msk                    /*!< Instruction Double Transfer Rate */

+#define OCTOSPI_CCR_ISIZE_Pos          (4U)

+#define OCTOSPI_CCR_ISIZE_Msk          (0x3UL << OCTOSPI_CCR_ISIZE_Pos)         /*!< 0x00000030 */

+#define OCTOSPI_CCR_ISIZE              OCTOSPI_CCR_ISIZE_Msk                   /*!< Instruction Size */

+#define OCTOSPI_CCR_ISIZE_0            (0x1UL << OCTOSPI_CCR_ISIZE_Pos)         /*!< 0x00000010 */

+#define OCTOSPI_CCR_ISIZE_1            (0x2UL << OCTOSPI_CCR_ISIZE_Pos)         /*!< 0x00000020 */

+#define OCTOSPI_CCR_ADMODE_Pos         (8U)

+#define OCTOSPI_CCR_ADMODE_Msk         (0x7UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000700 */

+#define OCTOSPI_CCR_ADMODE             OCTOSPI_CCR_ADMODE_Msk                  /*!< Address Mode */

+#define OCTOSPI_CCR_ADMODE_0           (0x1UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000100 */

+#define OCTOSPI_CCR_ADMODE_1           (0x2UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000200 */

+#define OCTOSPI_CCR_ADMODE_2           (0x4UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000400 */

+#define OCTOSPI_CCR_ADDTR_Pos          (11U)

+#define OCTOSPI_CCR_ADDTR_Msk          (0x1UL << OCTOSPI_CCR_ADDTR_Pos)         /*!< 0x00000800 */

+#define OCTOSPI_CCR_ADDTR              OCTOSPI_CCR_ADDTR_Msk                   /*!< Address Double Transfer Rate */

+#define OCTOSPI_CCR_ADSIZE_Pos         (12U)

+#define OCTOSPI_CCR_ADSIZE_Msk         (0x3UL << OCTOSPI_CCR_ADSIZE_Pos)        /*!< 0x00003000 */

+#define OCTOSPI_CCR_ADSIZE             OCTOSPI_CCR_ADSIZE_Msk                  /*!< Address Size */

+#define OCTOSPI_CCR_ADSIZE_0           (0x1UL << OCTOSPI_CCR_ADSIZE_Pos)        /*!< 0x00001000 */

+#define OCTOSPI_CCR_ADSIZE_1           (0x2UL << OCTOSPI_CCR_ADSIZE_Pos)        /*!< 0x00002000 */

+#define OCTOSPI_CCR_ABMODE_Pos         (16U)

+#define OCTOSPI_CCR_ABMODE_Msk         (0x7UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00070000 */

+#define OCTOSPI_CCR_ABMODE             OCTOSPI_CCR_ABMODE_Msk                  /*!< Alternate Bytes Mode */

+#define OCTOSPI_CCR_ABMODE_0           (0x1UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00010000 */

+#define OCTOSPI_CCR_ABMODE_1           (0x2UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00020000 */

+#define OCTOSPI_CCR_ABMODE_2           (0x4UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00040000 */

+#define OCTOSPI_CCR_ABDTR_Pos          (19U)

+#define OCTOSPI_CCR_ABDTR_Msk          (0x1UL << OCTOSPI_CCR_ABDTR_Pos)         /*!< 0x00080000 */

+#define OCTOSPI_CCR_ABDTR              OCTOSPI_CCR_ABDTR_Msk                   /*!< Alternate Bytes Double Transfer Rate */

+#define OCTOSPI_CCR_ABSIZE_Pos         (20U)

+#define OCTOSPI_CCR_ABSIZE_Msk         (0x3UL << OCTOSPI_CCR_ABSIZE_Pos)        /*!< 0x00300000 */

+#define OCTOSPI_CCR_ABSIZE             OCTOSPI_CCR_ABSIZE_Msk                  /*!< Alternate Bytes Size */

+#define OCTOSPI_CCR_ABSIZE_0           (0x1UL << OCTOSPI_CCR_ABSIZE_Pos)        /*!< 0x00100000 */

+#define OCTOSPI_CCR_ABSIZE_1           (0x2UL << OCTOSPI_CCR_ABSIZE_Pos)        /*!< 0x00200000 */

+#define OCTOSPI_CCR_DMODE_Pos          (24U)

+#define OCTOSPI_CCR_DMODE_Msk          (0x7UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x07000000 */

+#define OCTOSPI_CCR_DMODE              OCTOSPI_CCR_DMODE_Msk                   /*!< Data Mode */

+#define OCTOSPI_CCR_DMODE_0            (0x1UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x01000000 */

+#define OCTOSPI_CCR_DMODE_1            (0x2UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x02000000 */

+#define OCTOSPI_CCR_DMODE_2            (0x4UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x04000000 */

+#define OCTOSPI_CCR_DDTR_Pos           (27U)

+#define OCTOSPI_CCR_DDTR_Msk           (0x1UL << OCTOSPI_CCR_DDTR_Pos)          /*!< 0x08000000 */

+#define OCTOSPI_CCR_DDTR               OCTOSPI_CCR_DDTR_Msk                    /*!< Data Double Transfer Rate */

+#define OCTOSPI_CCR_DQSE_Pos           (29U)

+#define OCTOSPI_CCR_DQSE_Msk           (0x1UL << OCTOSPI_CCR_DQSE_Pos)          /*!< 0x20000000 */

+#define OCTOSPI_CCR_DQSE               OCTOSPI_CCR_DQSE_Msk                    /*!< DQS Enable */

+#define OCTOSPI_CCR_SIOO_Pos           (31U)

+#define OCTOSPI_CCR_SIOO_Msk           (0x1UL << OCTOSPI_CCR_SIOO_Pos)          /*!< 0x80000000 */

+#define OCTOSPI_CCR_SIOO               OCTOSPI_CCR_SIOO_Msk                    /*!< Send Instruction Only Once Mode */

+

+/****************  Bit definition for OCTOSPI_TCR register  *******************/

+#define OCTOSPI_TCR_DCYC_Pos           (0U)

+#define OCTOSPI_TCR_DCYC_Msk           (0x1FUL << OCTOSPI_TCR_DCYC_Pos)         /*!< 0x0000001F */

+#define OCTOSPI_TCR_DCYC               OCTOSPI_TCR_DCYC_Msk                    /*!< Number of Dummy Cycles */

+#define OCTOSPI_TCR_DHQC_Pos           (28U)

+#define OCTOSPI_TCR_DHQC_Msk           (0x1UL << OCTOSPI_TCR_DHQC_Pos)          /*!< 0x10000000 */

+#define OCTOSPI_TCR_DHQC               OCTOSPI_TCR_DHQC_Msk                    /*!< Delay Hold Quarter Cycle */

+#define OCTOSPI_TCR_SSHIFT_Pos         (30U)

+#define OCTOSPI_TCR_SSHIFT_Msk         (0x1UL << OCTOSPI_TCR_SSHIFT_Pos)        /*!< 0x40000000 */

+#define OCTOSPI_TCR_SSHIFT             OCTOSPI_TCR_SSHIFT_Msk                  /*!< Sample Shift */

+

+/*****************  Bit definition for OCTOSPI_IR register  *******************/

+#define OCTOSPI_IR_INSTRUCTION_Pos     (0U)

+#define OCTOSPI_IR_INSTRUCTION_Msk     (0xFFFFFFFFUL << OCTOSPI_IR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_IR_INSTRUCTION         OCTOSPI_IR_INSTRUCTION_Msk              /*!< Instruction */

+

+/****************  Bit definition for OCTOSPI_ABR register  *******************/

+#define OCTOSPI_ABR_ALTERNATE_Pos      (0U)

+#define OCTOSPI_ABR_ALTERNATE_Msk      (0xFFFFFFFFUL << OCTOSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_ABR_ALTERNATE          OCTOSPI_ABR_ALTERNATE_Msk               /*!< Alternate Bytes */

+

+/****************  Bit definition for OCTOSPI_LPTR register  ******************/

+#define OCTOSPI_LPTR_TIMEOUT_Pos       (0U)

+#define OCTOSPI_LPTR_TIMEOUT_Msk       (0xFFFFUL << OCTOSPI_LPTR_TIMEOUT_Pos)   /*!< 0x0000FFFF */

+#define OCTOSPI_LPTR_TIMEOUT           OCTOSPI_LPTR_TIMEOUT_Msk                /*!< Timeout period */

+

+/****************  Bit definition for OCTOSPI_WPCCR register  *******************/

+#define OCTOSPI_WPCCR_IMODE_Pos        (0U)

+#define OCTOSPI_WPCCR_IMODE_Msk        (0x7UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000007 */

+#define OCTOSPI_WPCCR_IMODE            OCTOSPI_WPCCR_IMODE_Msk                 /*!< Instruction Mode */

+#define OCTOSPI_WPCCR_IMODE_0          (0x1UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000001 */

+#define OCTOSPI_WPCCR_IMODE_1          (0x2UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000002 */

+#define OCTOSPI_WPCCR_IMODE_2          (0x4UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000004 */

+#define OCTOSPI_WPCCR_IDTR_Pos         (3U)

+#define OCTOSPI_WPCCR_IDTR_Msk         (0x1UL << OCTOSPI_WPCCR_IDTR_Pos)        /*!< 0x00000008 */

+#define OCTOSPI_WPCCR_IDTR             OCTOSPI_WPCCR_IDTR_Msk                  /*!< Instruction Double Transfer Rate */

+#define OCTOSPI_WPCCR_ISIZE_Pos        (4U)

+#define OCTOSPI_WPCCR_ISIZE_Msk        (0x3UL << OCTOSPI_WPCCR_ISIZE_Pos)       /*!< 0x00000030 */

+#define OCTOSPI_WPCCR_ISIZE            OCTOSPI_WPCCR_ISIZE_Msk                 /*!< Instruction Size */

+#define OCTOSPI_WPCCR_ISIZE_0          (0x1UL << OCTOSPI_WPCCR_ISIZE_Pos)       /*!< 0x00000010 */

+#define OCTOSPI_WPCCR_ISIZE_1          (0x2UL << OCTOSPI_WPCCR_ISIZE_Pos)       /*!< 0x00000020 */

+#define OCTOSPI_WPCCR_ADMODE_Pos       (8U)

+#define OCTOSPI_WPCCR_ADMODE_Msk       (0x7UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000700 */

+#define OCTOSPI_WPCCR_ADMODE           OCTOSPI_WPCCR_ADMODE_Msk                /*!< Address Mode */

+#define OCTOSPI_WPCCR_ADMODE_0         (0x1UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000100 */

+#define OCTOSPI_WPCCR_ADMODE_1         (0x2UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000200 */

+#define OCTOSPI_WPCCR_ADMODE_2         (0x4UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000400 */

+#define OCTOSPI_WPCCR_ADDTR_Pos        (11U)

+#define OCTOSPI_WPCCR_ADDTR_Msk        (0x1UL << OCTOSPI_WPCCR_ADDTR_Pos)       /*!< 0x00000800 */

+#define OCTOSPI_WPCCR_ADDTR            OCTOSPI_WPCCR_ADDTR_Msk                 /*!< Address Double Transfer Rate */

+#define OCTOSPI_WPCCR_ADSIZE_Pos       (12U)

+#define OCTOSPI_WPCCR_ADSIZE_Msk       (0x3UL << OCTOSPI_WPCCR_ADSIZE_Pos)      /*!< 0x00003000 */

+#define OCTOSPI_WPCCR_ADSIZE           OCTOSPI_WPCCR_ADSIZE_Msk                /*!< Address Size */

+#define OCTOSPI_WPCCR_ADSIZE_0         (0x1UL << OCTOSPI_WPCCR_ADSIZE_Pos)      /*!< 0x00001000 */

+#define OCTOSPI_WPCCR_ADSIZE_1         (0x2UL << OCTOSPI_WPCCR_ADSIZE_Pos)      /*!< 0x00002000 */

+#define OCTOSPI_WPCCR_ABMODE_Pos       (16U)

+#define OCTOSPI_WPCCR_ABMODE_Msk       (0x7UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00070000 */

+#define OCTOSPI_WPCCR_ABMODE           OCTOSPI_WPCCR_ABMODE_Msk                /*!< Alternate Bytes Mode */

+#define OCTOSPI_WPCCR_ABMODE_0         (0x1UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00010000 */

+#define OCTOSPI_WPCCR_ABMODE_1         (0x2UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00020000 */

+#define OCTOSPI_WPCCR_ABMODE_2         (0x4UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00040000 */

+#define OCTOSPI_WPCCR_ABDTR_Pos        (19U)

+#define OCTOSPI_WPCCR_ABDTR_Msk        (0x1UL << OCTOSPI_WPCCR_ABDTR_Pos)       /*!< 0x00080000 */

+#define OCTOSPI_WPCCR_ABDTR            OCTOSPI_WPCCR_ABDTR_Msk                 /*!< Alternate Bytes Double Transfer Rate */

+#define OCTOSPI_WPCCR_ABSIZE_Pos       (20U)

+#define OCTOSPI_WPCCR_ABSIZE_Msk       (0x3UL << OCTOSPI_WPCCR_ABSIZE_Pos)      /*!< 0x00300000 */

+#define OCTOSPI_WPCCR_ABSIZE           OCTOSPI_WPCCR_ABSIZE_Msk                /*!< Alternate Bytes Size */

+#define OCTOSPI_WPCCR_ABSIZE_0         (0x1UL << OCTOSPI_WPCCR_ABSIZE_Pos)      /*!< 0x00100000 */

+#define OCTOSPI_WPCCR_ABSIZE_1         (0x2UL << OCTOSPI_WPCCR_ABSIZE_Pos)      /*!< 0x00200000 */

+#define OCTOSPI_WPCCR_DMODE_Pos        (24U)

+#define OCTOSPI_WPCCR_DMODE_Msk        (0x7UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x07000000 */

+#define OCTOSPI_WPCCR_DMODE            OCTOSPI_WPCCR_DMODE_Msk                 /*!< Data Mode */

+#define OCTOSPI_WPCCR_DMODE_0          (0x1UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x01000000 */

+#define OCTOSPI_WPCCR_DMODE_1          (0x2UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x02000000 */

+#define OCTOSPI_WPCCR_DMODE_2          (0x4UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x04000000 */

+#define OCTOSPI_WPCCR_DDTR_Pos         (27U)

+#define OCTOSPI_WPCCR_DDTR_Msk         (0x1UL << OCTOSPI_WPCCR_DDTR_Pos)        /*!< 0x08000000 */

+#define OCTOSPI_WPCCR_DDTR             OCTOSPI_WPCCR_DDTR_Msk                  /*!< Data Double Transfer Rate */

+#define OCTOSPI_WPCCR_DQSE_Pos         (29U)

+#define OCTOSPI_WPCCR_DQSE_Msk         (0x1UL << OCTOSPI_WPCCR_DQSE_Pos)        /*!< 0x20000000 */

+#define OCTOSPI_WPCCR_DQSE             OCTOSPI_WPCCR_DQSE_Msk                  /*!< DQS Enable */

+#define OCTOSPI_WPCCR_SIOO_Pos         (31U)

+#define OCTOSPI_WPCCR_SIOO_Msk         (0x1UL << OCTOSPI_WPCCR_SIOO_Pos)        /*!< 0x80000000 */

+#define OCTOSPI_WPCCR_SIOO             OCTOSPI_WPCCR_SIOO_Msk                  /*!< Send Instruction Only Once Mode */

+

+/****************  Bit definition for OCTOSPI_WPTCR register  *******************/

+#define OCTOSPI_WPTCR_DCYC_Pos         (0U)

+#define OCTOSPI_WPTCR_DCYC_Msk         (0x1FUL << OCTOSPI_WPTCR_DCYC_Pos)       /*!< 0x0000001F */

+#define OCTOSPI_WPTCR_DCYC             OCTOSPI_WPTCR_DCYC_Msk                  /*!< Number of Dummy Cycles */

+#define OCTOSPI_WPTCR_DHQC_Pos         (28U)

+#define OCTOSPI_WPTCR_DHQC_Msk         (0x1UL << OCTOSPI_WPTCR_DHQC_Pos)        /*!< 0x10000000 */

+#define OCTOSPI_WPTCR_DHQC             OCTOSPI_WPTCR_DHQC_Msk                  /*!< Delay Hold Quarter Cycle */

+#define OCTOSPI_WPTCR_SSHIFT_Pos       (30U)

+#define OCTOSPI_WPTCR_SSHIFT_Msk       (0x1UL << OCTOSPI_WPTCR_SSHIFT_Pos)      /*!< 0x40000000 */

+#define OCTOSPI_WPTCR_SSHIFT           OCTOSPI_WPTCR_SSHIFT_Msk                /*!< Sample Shift */

+

+/*****************  Bit definition for OCTOSPI_WPIR register  *******************/

+#define OCTOSPI_WPIR_INSTRUCTION_Pos   (0U)

+#define OCTOSPI_WPIR_INSTRUCTION_Msk   (0xFFFFFFFFUL << OCTOSPI_WPIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_WPIR_INSTRUCTION       OCTOSPI_WPIR_INSTRUCTION_Msk            /*!< Instruction */

+

+/****************  Bit definition for OCTOSPI_WPABR register  *******************/

+#define OCTOSPI_WPABR_ALTERNATE_Pos    (0U)

+#define OCTOSPI_WPABR_ALTERNATE_Msk    (0xFFFFFFFFUL << OCTOSPI_WPABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_WPABR_ALTERNATE        OCTOSPI_WPABR_ALTERNATE_Msk             /*!< Alternate Bytes */

+

+/****************  Bit definition for OCTOSPI_WCCR register  ******************/

+#define OCTOSPI_WCCR_IMODE_Pos         (0U)

+#define OCTOSPI_WCCR_IMODE_Msk         (0x7UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000007 */

+#define OCTOSPI_WCCR_IMODE             OCTOSPI_WCCR_IMODE_Msk                  /*!< Instruction Mode */

+#define OCTOSPI_WCCR_IMODE_0           (0x1UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000001 */

+#define OCTOSPI_WCCR_IMODE_1           (0x2UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000002 */

+#define OCTOSPI_WCCR_IMODE_2           (0x4UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000004 */

+#define OCTOSPI_WCCR_IDTR_Pos          (3U)

+#define OCTOSPI_WCCR_IDTR_Msk          (0x1UL << OCTOSPI_WCCR_IDTR_Pos)         /*!< 0x00000008 */

+#define OCTOSPI_WCCR_IDTR              OCTOSPI_WCCR_IDTR_Msk                   /*!< Instruction Double Transfer Rate */

+#define OCTOSPI_WCCR_ISIZE_Pos         (4U)

+#define OCTOSPI_WCCR_ISIZE_Msk         (0x3UL << OCTOSPI_WCCR_ISIZE_Pos)        /*!< 0x00000030 */

+#define OCTOSPI_WCCR_ISIZE             OCTOSPI_WCCR_ISIZE_Msk                  /*!< Instruction Size */

+#define OCTOSPI_WCCR_ISIZE_0           (0x1UL << OCTOSPI_WCCR_ISIZE_Pos)        /*!< 0x00000010 */

+#define OCTOSPI_WCCR_ISIZE_1           (0x2UL << OCTOSPI_WCCR_ISIZE_Pos)        /*!< 0x00000020 */

+#define OCTOSPI_WCCR_ADMODE_Pos        (8U)

+#define OCTOSPI_WCCR_ADMODE_Msk        (0x7UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000700 */

+#define OCTOSPI_WCCR_ADMODE            OCTOSPI_WCCR_ADMODE_Msk                 /*!< Address Mode */

+#define OCTOSPI_WCCR_ADMODE_0          (0x1UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000100 */

+#define OCTOSPI_WCCR_ADMODE_1          (0x2UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000200 */

+#define OCTOSPI_WCCR_ADMODE_2          (0x4UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000400 */

+#define OCTOSPI_WCCR_ADDTR_Pos         (11U)

+#define OCTOSPI_WCCR_ADDTR_Msk         (0x1UL << OCTOSPI_WCCR_ADDTR_Pos)        /*!< 0x00000800 */

+#define OCTOSPI_WCCR_ADDTR             OCTOSPI_WCCR_ADDTR_Msk                  /*!< Address Double Transfer Rate */

+#define OCTOSPI_WCCR_ADSIZE_Pos        (12U)

+#define OCTOSPI_WCCR_ADSIZE_Msk        (0x3UL << OCTOSPI_WCCR_ADSIZE_Pos)       /*!< 0x00003000 */

+#define OCTOSPI_WCCR_ADSIZE            OCTOSPI_WCCR_ADSIZE_Msk                 /*!< Address Size */

+#define OCTOSPI_WCCR_ADSIZE_0          (0x1UL << OCTOSPI_WCCR_ADSIZE_Pos)       /*!< 0x00001000 */

+#define OCTOSPI_WCCR_ADSIZE_1          (0x2UL << OCTOSPI_WCCR_ADSIZE_Pos)       /*!< 0x00002000 */

+#define OCTOSPI_WCCR_ABMODE_Pos        (16U)

+#define OCTOSPI_WCCR_ABMODE_Msk        (0x7UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00070000 */

+#define OCTOSPI_WCCR_ABMODE            OCTOSPI_WCCR_ABMODE_Msk                 /*!< Alternate Bytes Mode */

+#define OCTOSPI_WCCR_ABMODE_0          (0x1UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00010000 */

+#define OCTOSPI_WCCR_ABMODE_1          (0x2UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00020000 */

+#define OCTOSPI_WCCR_ABMODE_2          (0x4UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00040000 */

+#define OCTOSPI_WCCR_ABDTR_Pos         (19U)

+#define OCTOSPI_WCCR_ABDTR_Msk         (0x1UL << OCTOSPI_WCCR_ABDTR_Pos)        /*!< 0x00080000 */

+#define OCTOSPI_WCCR_ABDTR             OCTOSPI_WCCR_ABDTR_Msk                  /*!< Alternate Bytes Double Transfer Rate */

+#define OCTOSPI_WCCR_ABSIZE_Pos        (20U)

+#define OCTOSPI_WCCR_ABSIZE_Msk        (0x3UL << OCTOSPI_WCCR_ABSIZE_Pos)       /*!< 0x00300000 */

+#define OCTOSPI_WCCR_ABSIZE            OCTOSPI_WCCR_ABSIZE_Msk                 /*!< Alternate Bytes Size */

+#define OCTOSPI_WCCR_ABSIZE_0          (0x1UL << OCTOSPI_WCCR_ABSIZE_Pos)       /*!< 0x00100000 */

+#define OCTOSPI_WCCR_ABSIZE_1          (0x2UL << OCTOSPI_WCCR_ABSIZE_Pos)       /*!< 0x00200000 */

+#define OCTOSPI_WCCR_DMODE_Pos         (24U)

+#define OCTOSPI_WCCR_DMODE_Msk         (0x7UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x07000000 */

+#define OCTOSPI_WCCR_DMODE             OCTOSPI_WCCR_DMODE_Msk                  /*!< Data Mode */

+#define OCTOSPI_WCCR_DMODE_0           (0x1UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x01000000 */

+#define OCTOSPI_WCCR_DMODE_1           (0x2UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x02000000 */

+#define OCTOSPI_WCCR_DMODE_2           (0x4UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x04000000 */

+#define OCTOSPI_WCCR_DDTR_Pos          (27U)

+#define OCTOSPI_WCCR_DDTR_Msk          (0x1UL << OCTOSPI_WCCR_DDTR_Pos)         /*!< 0x08000000 */

+#define OCTOSPI_WCCR_DDTR              OCTOSPI_WCCR_DDTR_Msk                   /*!< Data Double Transfer Rate */

+#define OCTOSPI_WCCR_DQSE_Pos          (29U)

+#define OCTOSPI_WCCR_DQSE_Msk          (0x1UL << OCTOSPI_WCCR_DQSE_Pos)         /*!< 0x20000000 */

+#define OCTOSPI_WCCR_DQSE              OCTOSPI_WCCR_DQSE_Msk                   /*!< DQS Enable */

+#define OCTOSPI_WCCR_SIOO_Pos          (31U)

+#define OCTOSPI_WCCR_SIOO_Msk          (0x1UL << OCTOSPI_WCCR_SIOO_Pos)         /*!< 0x80000000 */

+#define OCTOSPI_WCCR_SIOO              OCTOSPI_WCCR_SIOO_Msk                   /*!< Send Instruction Only Once Mode */

+

+/****************  Bit definition for OCTOSPI_WTCR register  ******************/

+#define OCTOSPI_WTCR_DCYC_Pos          (0U)

+#define OCTOSPI_WTCR_DCYC_Msk          (0x1FUL << OCTOSPI_WTCR_DCYC_Pos)        /*!< 0x0000001F */

+#define OCTOSPI_WTCR_DCYC              OCTOSPI_WTCR_DCYC_Msk                   /*!< Number of Dummy Cycles */

+

+/****************  Bit definition for OCTOSPI_WIR register  *******************/

+#define OCTOSPI_WIR_INSTRUCTION_Pos    (0U)

+#define OCTOSPI_WIR_INSTRUCTION_Msk    (0xFFFFFFFFUL << OCTOSPI_WIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_WIR_INSTRUCTION        OCTOSPI_WIR_INSTRUCTION_Msk             /*!< Instruction */

+

+/****************  Bit definition for OCTOSPI_WABR register  ******************/

+#define OCTOSPI_WABR_ALTERNATE_Pos     (0U)

+#define OCTOSPI_WABR_ALTERNATE_Msk     (0xFFFFFFFFUL << OCTOSPI_WABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_WABR_ALTERNATE         OCTOSPI_WABR_ALTERNATE_Msk              /*!< Alternate Bytes */

+

+/****************  Bit definition for OCTOSPI_HLCR register  ******************/

+#define OCTOSPI_HLCR_LM_Pos            (0U)

+#define OCTOSPI_HLCR_LM_Msk            (0x1UL << OCTOSPI_HLCR_LM_Pos)           /*!< 0x00000001 */

+#define OCTOSPI_HLCR_LM                OCTOSPI_HLCR_LM_Msk                     /*!< Latency Mode */

+#define OCTOSPI_HLCR_WZL_Pos           (1U)

+#define OCTOSPI_HLCR_WZL_Msk           (0x1UL << OCTOSPI_HLCR_WZL_Pos)          /*!< 0x00000002 */

+#define OCTOSPI_HLCR_WZL               OCTOSPI_HLCR_WZL_Msk                    /*!< Write Zero Latency */

+#define OCTOSPI_HLCR_TACC_Pos          (8U)

+#define OCTOSPI_HLCR_TACC_Msk          (0xFFUL << OCTOSPI_HLCR_TACC_Pos)        /*!< 0x0000FF00 */

+#define OCTOSPI_HLCR_TACC              OCTOSPI_HLCR_TACC_Msk                   /*!< Access Time */

+#define OCTOSPI_HLCR_TRWR_Pos          (16U)

+#define OCTOSPI_HLCR_TRWR_Msk          (0xFFUL << OCTOSPI_HLCR_TRWR_Pos)        /*!< 0x00FF0000 */

+#define OCTOSPI_HLCR_TRWR              OCTOSPI_HLCR_TRWR_Msk                   /*!< Read Write Recovery Time */

+

+/****************  Bit definition for OCTOSPI_VER register  *******************/

+#define OCTOSPI_VER_VER_Pos            (0U)

+#define OCTOSPI_VER_VER_Msk            (0xFFUL << OCTOSPI_VER_VER_Pos)          /*!< 0x000000FF */

+#define OCTOSPI_VER_VER                OCTOSPI_VER_VER_Msk                     /*!< Version */

+

+/*****************  Bit definition for OCTOSPI_ID register  *******************/

+#define OCTOSPI_ID_ID_Pos              (0U)

+#define OCTOSPI_ID_ID_Msk              (0xFFFFFFFFUL << OCTOSPI_ID_ID_Pos)      /*!< 0xFFFFFFFF */

+#define OCTOSPI_ID_ID                  OCTOSPI_ID_ID_Msk                       /*!< Identification */

+

+/****************  Bit definition for OCTOSPI_MID register  *******************/

+#define OCTOSPI_MID_MID_Pos            (0U)

+#define OCTOSPI_MID_MID_Msk            (0xFFFFFFFFUL << OCTOSPI_MID_MID_Pos)    /*!< 0xFFFFFFFF */

+#define OCTOSPI_MID_MID                OCTOSPI_MID_MID_Msk                     /*!< Magic ID */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                  OCTOSPIM                                  */

+/*                                                                            */

+/******************************************************************************/

+

+/***************  Bit definition for OCTOSPIM_CR register  ********************/

+#define OCTOSPIM_CR_MUXEN_Pos          (0U)

+#define OCTOSPIM_CR_MUXEN_Msk          (0x1UL << OCTOSPIM_CR_MUXEN_Pos)        /*!< 0x00000001 */

+#define OCTOSPIM_CR_MUXEN              OCTOSPIM_CR_MUXEN_Msk                   /*!< Multiplexed mode enable */

+#define OCTOSPIM_CR_REQ2ACK_TIME_Pos   (16U)

+#define OCTOSPIM_CR_REQ2ACK_TIME_Msk   (0xFFUL << OCTOSPIM_CR_REQ2ACK_TIME_Pos)/*!< 0x00FF0000 */

+#define OCTOSPIM_CR_REQ2ACK_TIME       OCTOSPIM_CR_REQ2ACK_TIME_Msk            /*!< REQ to ACK time */

+

+/***************  Bit definition for OCTOSPIM_PCR register  *******************/

+#define OCTOSPIM_PCR_CLKEN_Pos         (0U)

+#define OCTOSPIM_PCR_CLKEN_Msk         (0x1UL << OCTOSPIM_PCR_CLKEN_Pos)        /*!< 0x00000001 */

+#define OCTOSPIM_PCR_CLKEN             OCTOSPIM_PCR_CLKEN_Msk                   /*!< CLK/CLKn Enable for Port n */

+#define OCTOSPIM_PCR_CLKSRC_Pos        (1U)

+#define OCTOSPIM_PCR_CLKSRC_Msk        (0x1UL << OCTOSPIM_PCR_CLKSRC_Pos)       /*!< 0x00000002 */

+#define OCTOSPIM_PCR_CLKSRC            OCTOSPIM_PCR_CLKSRC_Msk                  /*!< CLK/CLKn Source for Port n */

+#define OCTOSPIM_PCR_DQSEN_Pos         (4U)

+#define OCTOSPIM_PCR_DQSEN_Msk         (0x1UL << OCTOSPIM_PCR_DQSEN_Pos)        /*!< 0x00000010 */

+#define OCTOSPIM_PCR_DQSEN             OCTOSPIM_PCR_DQSEN_Msk                   /*!< DQS Enable for Port n */

+#define OCTOSPIM_PCR_DQSSRC_Pos        (5U)

+#define OCTOSPIM_PCR_DQSSRC_Msk        (0x1UL << OCTOSPIM_PCR_DQSSRC_Pos)       /*!< 0x00000020 */

+#define OCTOSPIM_PCR_DQSSRC            OCTOSPIM_PCR_DQSSRC_Msk                  /*!< DQS Source for Port n */

+#define OCTOSPIM_PCR_NCSEN_Pos         (8U)

+#define OCTOSPIM_PCR_NCSEN_Msk         (0x1UL << OCTOSPIM_PCR_NCSEN_Pos)        /*!< 0x00000100 */

+#define OCTOSPIM_PCR_NCSEN             OCTOSPIM_PCR_NCSEN_Msk                   /*!< nCS Enable for Port n */

+#define OCTOSPIM_PCR_NCSSRC_Pos        (9U)

+#define OCTOSPIM_PCR_NCSSRC_Msk        (0x1UL << OCTOSPIM_PCR_NCSSRC_Pos)       /*!< 0x00000200 */

+#define OCTOSPIM_PCR_NCSSRC            OCTOSPIM_PCR_NCSSRC_Msk                  /*!< nCS Source for Port n */

+#define OCTOSPIM_PCR_IOLEN_Pos         (16U)

+#define OCTOSPIM_PCR_IOLEN_Msk         (0x1UL << OCTOSPIM_PCR_IOLEN_Pos)        /*!< 0x00010000 */

+#define OCTOSPIM_PCR_IOLEN             OCTOSPIM_PCR_IOLEN_Msk                   /*!< IO[3:0] Enable for Port n */

+#define OCTOSPIM_PCR_IOLSRC_Pos        (17U)

+#define OCTOSPIM_PCR_IOLSRC_Msk        (0x3UL << OCTOSPIM_PCR_IOLSRC_Pos)       /*!< 0x00060000 */

+#define OCTOSPIM_PCR_IOLSRC            OCTOSPIM_PCR_IOLSRC_Msk                  /*!< IO[3:0] Source for Port n */

+#define OCTOSPIM_PCR_IOLSRC_0          (0x1UL << OCTOSPIM_PCR_IOLSRC_Pos)       /*!< 0x00020000 */

+#define OCTOSPIM_PCR_IOLSRC_1          (0x2UL << OCTOSPIM_PCR_IOLSRC_Pos)       /*!< 0x00040000 */

+#define OCTOSPIM_PCR_IOHEN_Pos         (24U)

+#define OCTOSPIM_PCR_IOHEN_Msk         (0x1UL << OCTOSPIM_PCR_IOHEN_Pos)        /*!< 0x01000000 */

+#define OCTOSPIM_PCR_IOHEN             OCTOSPIM_PCR_IOHEN_Msk                   /*!< IO[7:4] Enable for Port n */

+#define OCTOSPIM_PCR_IOHSRC_Pos        (25U)

+#define OCTOSPIM_PCR_IOHSRC_Msk        (0x3UL << OCTOSPIM_PCR_IOHSRC_Pos)       /*!< 0x06000000 */

+#define OCTOSPIM_PCR_IOHSRC            OCTOSPIM_PCR_IOHSRC_Msk                  /*!< IO[7:4] Source for Port n */

+#define OCTOSPIM_PCR_IOHSRC_0          (0x1UL << OCTOSPIM_PCR_IOHSRC_Pos)       /*!< 0x02000000 */

+#define OCTOSPIM_PCR_IOHSRC_1          (0x2UL << OCTOSPIM_PCR_IOHSRC_Pos)       /*!< 0x04000000 */

+/******************************************************************************/

+/*                                                                            */

+/*                      Analog Comparators (COMP)                             */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for COMP_SR register  ********************/

+#define COMP_SR_C1VAL_Pos            (0U)

+#define COMP_SR_C1VAL_Msk            (0x1UL << COMP_SR_C1VAL_Pos)              /*!< 0x00000001 */

+#define COMP_SR_C1VAL                COMP_SR_C1VAL_Msk

+#define COMP_SR_C2VAL_Pos            (1U)

+#define COMP_SR_C2VAL_Msk            (0x1UL << COMP_SR_C2VAL_Pos)              /*!< 0x00000002 */

+#define COMP_SR_C2VAL                COMP_SR_C2VAL_Msk

+#define COMP_SR_C1IF_Pos             (16U)

+#define COMP_SR_C1IF_Msk             (0x1UL << COMP_SR_C1IF_Pos)               /*!< 0x00010000 */

+#define COMP_SR_C1IF                 COMP_SR_C1IF_Msk

+#define COMP_SR_C2IF_Pos             (17U)

+#define COMP_SR_C2IF_Msk             (0x1UL << COMP_SR_C2IF_Pos)               /*!< 0x00020000 */

+#define COMP_SR_C2IF                 COMP_SR_C2IF_Msk

+/*******************  Bit definition for COMP_ICFR register  ********************/

+#define COMP_ICFR_C1IF_Pos           (16U)

+#define COMP_ICFR_C1IF_Msk           (0x1UL << COMP_ICFR_C1IF_Pos)             /*!< 0x00010000 */

+#define COMP_ICFR_C1IF               COMP_ICFR_C1IF_Msk

+#define COMP_ICFR_C2IF_Pos           (17U)

+#define COMP_ICFR_C2IF_Msk           (0x1UL << COMP_ICFR_C2IF_Pos)             /*!< 0x00020000 */

+#define COMP_ICFR_C2IF               COMP_ICFR_C2IF_Msk

+/*******************  Bit definition for COMP_OR register  ********************/

+#define COMP_OR_AFOPA6_Pos           (0U)

+#define COMP_OR_AFOPA6_Msk           (0x1UL << COMP_OR_AFOPA6_Pos)             /*!< 0x00000001 */

+#define COMP_OR_AFOPA6               COMP_OR_AFOPA6_Msk

+#define COMP_OR_AFOPA8_Pos           (1U)

+#define COMP_OR_AFOPA8_Msk           (0x1UL << COMP_OR_AFOPA8_Pos)             /*!< 0x00000002 */

+#define COMP_OR_AFOPA8               COMP_OR_AFOPA8_Msk

+#define COMP_OR_AFOPB12_Pos          (2U)

+#define COMP_OR_AFOPB12_Msk          (0x1UL << COMP_OR_AFOPB12_Pos)            /*!< 0x00000004 */

+#define COMP_OR_AFOPB12              COMP_OR_AFOPB12_Msk

+#define COMP_OR_AFOPE6_Pos           (3U)

+#define COMP_OR_AFOPE6_Msk           (0x1UL << COMP_OR_AFOPE6_Pos)             /*!< 0x00000008 */

+#define COMP_OR_AFOPE6               COMP_OR_AFOPE6_Msk

+#define COMP_OR_AFOPE15_Pos          (4U)

+#define COMP_OR_AFOPE15_Msk          (0x1UL << COMP_OR_AFOPE15_Pos)            /*!< 0x00000010 */

+#define COMP_OR_AFOPE15              COMP_OR_AFOPE15_Msk

+#define COMP_OR_AFOPG2_Pos           (5U)

+#define COMP_OR_AFOPG2_Msk           (0x1UL << COMP_OR_AFOPG2_Pos)             /*!< 0x00000020 */

+#define COMP_OR_AFOPG2               COMP_OR_AFOPG2_Msk

+#define COMP_OR_AFOPG3_Pos           (6U)

+#define COMP_OR_AFOPG3_Msk           (0x1UL << COMP_OR_AFOPG3_Pos)             /*!< 0x00000040 */

+#define COMP_OR_AFOPG3               COMP_OR_AFOPG3_Msk

+#define COMP_OR_AFOPG4_Pos           (7U)

+#define COMP_OR_AFOPG4_Msk           (0x1UL << COMP_OR_AFOPG4_Pos)             /*!< 0x00000080 */

+#define COMP_OR_AFOPG4               COMP_OR_AFOPG4_Msk

+#define COMP_OR_AFOPI1_Pos           (8U)

+#define COMP_OR_AFOPI1_Msk           (0x1UL << COMP_OR_AFOPI1_Pos)             /*!< 0x00000100 */

+#define COMP_OR_AFOPI1               COMP_OR_AFOPI1_Msk

+#define COMP_OR_AFOPI4_Pos           (9U)

+#define COMP_OR_AFOPI4_Msk           (0x1UL << COMP_OR_AFOPI4_Pos)             /*!< 0x00000200 */

+#define COMP_OR_AFOPI4               COMP_OR_AFOPI4_Msk

+#define COMP_OR_AFOPK2_Pos           (10U)

+#define COMP_OR_AFOPK2_Msk           (0x1UL << COMP_OR_AFOPK2_Pos)             /*!< 0x00000400 */

+#define COMP_OR_AFOPK2               COMP_OR_AFOPK2_Msk

+

+/*!< ******************  Bit definition for COMP_CFGRx register  ********************/

+#define COMP_CFGRx_EN_Pos            (0U)

+#define COMP_CFGRx_EN_Msk            (0x1UL << COMP_CFGRx_EN_Pos)              /*!< 0x00000001 */

+#define COMP_CFGRx_EN                COMP_CFGRx_EN_Msk                         /*!< COMPx enable bit                     */

+#define COMP_CFGRx_BRGEN_Pos         (1U)

+#define COMP_CFGRx_BRGEN_Msk         (0x1UL << COMP_CFGRx_BRGEN_Pos)           /*!< 0x00000002 */

+#define COMP_CFGRx_BRGEN             COMP_CFGRx_BRGEN_Msk                      /*!< COMPx Scaler bridge enable           */

+#define COMP_CFGRx_SCALEN_Pos        (2U)

+#define COMP_CFGRx_SCALEN_Msk        (0x1UL << COMP_CFGRx_SCALEN_Pos)          /*!< 0x00000004 */

+#define COMP_CFGRx_SCALEN            COMP_CFGRx_SCALEN_Msk                     /*!< COMPx Voltage scaler enable bit      */

+#define COMP_CFGRx_POLARITY_Pos      (3U)

+#define COMP_CFGRx_POLARITY_Msk      (0x1UL << COMP_CFGRx_POLARITY_Pos)        /*!< 0x00000008 */

+#define COMP_CFGRx_POLARITY          COMP_CFGRx_POLARITY_Msk                   /*!< COMPx  polarity selection bit        */

+#define COMP_CFGRx_WINMODE_Pos       (4U)

+#define COMP_CFGRx_WINMODE_Msk       (0x1UL << COMP_CFGRx_WINMODE_Pos)         /*!< 0x00000010 */

+#define COMP_CFGRx_WINMODE           COMP_CFGRx_WINMODE_Msk                    /*!< COMPx Windows mode selection bit     */

+#define COMP_CFGRx_ITEN_Pos          (6U)

+#define COMP_CFGRx_ITEN_Msk          (0x1UL << COMP_CFGRx_ITEN_Pos)            /*!< 0x00000040 */

+#define COMP_CFGRx_ITEN              COMP_CFGRx_ITEN_Msk                       /*!< COMPx  interrupt enable              */

+#define COMP_CFGRx_HYST_Pos          (8U)

+#define COMP_CFGRx_HYST_Msk          (0x3UL << COMP_CFGRx_HYST_Pos)            /*!< 0x00000300 */

+#define COMP_CFGRx_HYST              COMP_CFGRx_HYST_Msk                       /*!< COMPx  hysteresis selection bits     */

+#define COMP_CFGRx_HYST_0            (0x1UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000100 */

+#define COMP_CFGRx_HYST_1            (0x2UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000200 */

+#define COMP_CFGRx_PWRMODE_Pos       (12U)

+#define COMP_CFGRx_PWRMODE_Msk       (0x3UL << COMP_CFGRx_PWRMODE_Pos)         /*!< 0x00003000 */

+#define COMP_CFGRx_PWRMODE           COMP_CFGRx_PWRMODE_Msk                    /*!< COMPx Power Mode of the comparator   */

+#define COMP_CFGRx_PWRMODE_0         (0x1UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00001000 */

+#define COMP_CFGRx_PWRMODE_1         (0x2UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00002000 */

+#define COMP_CFGRx_INMSEL_Pos        (16U)

+#define COMP_CFGRx_INMSEL_Msk        (0xFUL << COMP_CFGRx_INMSEL_Pos)          /*!< 0x000F0000 */

+#define COMP_CFGRx_INMSEL            COMP_CFGRx_INMSEL_Msk                     /*!< COMPx  input minus selection bit  */

+#define COMP_CFGRx_INMSEL_0          (0x1UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00010000 */

+#define COMP_CFGRx_INMSEL_1          (0x2UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00020000 */

+#define COMP_CFGRx_INMSEL_2          (0x4UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00040000 */

+#define COMP_CFGRx_INMSEL_3          (0x8UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00080000 */

+#define COMP_CFGRx_INPSEL_Pos        (20U)

+#define COMP_CFGRx_INPSEL_Msk        (0x1UL << COMP_CFGRx_INPSEL_Pos)          /*!< 0x00100000 */

+#define COMP_CFGRx_INPSEL            COMP_CFGRx_INPSEL_Msk                     /*!< COMPx  input plus selection bit       */

+#define COMP_CFGRx_INP2SEL_Pos        (22U)

+#define COMP_CFGRx_INP2SEL_Msk        (0x1UL << COMP_CFGRx_INP2SEL_Pos)        /*!< 0x00400000 */

+#define COMP_CFGRx_INP2SEL            COMP_CFGRx_INP2SEL_Msk                   /*!< COMPx  input plus 2 selection bit     */

+#define COMP_CFGRx_BLANKING_Pos      (24U)

+#define COMP_CFGRx_BLANKING_Msk      (0xFUL << COMP_CFGRx_BLANKING_Pos)        /*!< 0x0F000000 */

+#define COMP_CFGRx_BLANKING          COMP_CFGRx_BLANKING_Msk                   /*!< COMPx  blanking source selection bits */

+#define COMP_CFGRx_BLANKING_0        (0x1UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x01000000 */

+#define COMP_CFGRx_BLANKING_1        (0x2UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x02000000 */

+#define COMP_CFGRx_BLANKING_2        (0x4UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x04000000 */

+#define COMP_CFGRx_LOCK_Pos          (31U)

+#define COMP_CFGRx_LOCK_Msk          (0x1UL << COMP_CFGRx_LOCK_Pos)            /*!< 0x80000000 */

+#define COMP_CFGRx_LOCK              COMP_CFGRx_LOCK_Msk                       /*!< COMPx Lock Bit                        */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for USART_CR1 register  *******************/

+#define USART_CR1_UE_Pos                (0U)

+#define USART_CR1_UE_Msk                (0x1UL << USART_CR1_UE_Pos)            /*!< 0x00000001 */

+#define USART_CR1_UE                    USART_CR1_UE_Msk                       /*!< USART Enable */

+#define USART_CR1_UESM_Pos              (1U)

+#define USART_CR1_UESM_Msk              (0x1UL << USART_CR1_UESM_Pos)          /*!< 0x00000002 */

+#define USART_CR1_UESM                  USART_CR1_UESM_Msk                     /*!< USART Enable in STOP Mode */

+#define USART_CR1_RE_Pos                (2U)

+#define USART_CR1_RE_Msk                (0x1UL << USART_CR1_RE_Pos)            /*!< 0x00000004 */

+#define USART_CR1_RE                    USART_CR1_RE_Msk                       /*!< Receiver Enable */

+#define USART_CR1_TE_Pos                (3U)

+#define USART_CR1_TE_Msk                (0x1UL << USART_CR1_TE_Pos)            /*!< 0x00000008 */

+#define USART_CR1_TE                    USART_CR1_TE_Msk                       /*!< Transmitter Enable */

+#define USART_CR1_IDLEIE_Pos            (4U)

+#define USART_CR1_IDLEIE_Msk            (0x1UL << USART_CR1_IDLEIE_Pos)        /*!< 0x00000010 */

+#define USART_CR1_IDLEIE                USART_CR1_IDLEIE_Msk                   /*!< IDLE Interrupt Enable */

+#define USART_CR1_RXNEIE_RXFNEIE_Pos    (5U)

+#define USART_CR1_RXNEIE_RXFNEIE_Msk    (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */

+#define USART_CR1_RXNEIE_RXFNEIE        USART_CR1_RXNEIE_RXFNEIE_Msk           /*!< RXNE and RX FIFO Not Empty Interrupt Enable */

+#define USART_CR1_TCIE_Pos              (6U)

+#define USART_CR1_TCIE_Msk              (0x1UL << USART_CR1_TCIE_Pos)          /*!< 0x00000040 */

+#define USART_CR1_TCIE                  USART_CR1_TCIE_Msk                     /*!< Transmission Complete Interrupt Enable */

+#define USART_CR1_TXEIE_TXFNFIE_Pos     (7U)

+#define USART_CR1_TXEIE_TXFNFIE_Msk     (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */

+#define USART_CR1_TXEIE_TXFNFIE         USART_CR1_TXEIE_TXFNFIE_Msk            /*!< TXE and TX FIFO Not Full Interrupt Enable */

+#define USART_CR1_PEIE_Pos              (8U)

+#define USART_CR1_PEIE_Msk              (0x1UL << USART_CR1_PEIE_Pos)          /*!< 0x00000100 */

+#define USART_CR1_PEIE                  USART_CR1_PEIE_Msk                     /*!< PE Interrupt Enable */

+#define USART_CR1_PS_Pos                (9U)

+#define USART_CR1_PS_Msk                (0x1UL << USART_CR1_PS_Pos)            /*!< 0x00000200 */

+#define USART_CR1_PS                    USART_CR1_PS_Msk                       /*!< Parity Selection */

+#define USART_CR1_PCE_Pos               (10U)

+#define USART_CR1_PCE_Msk               (0x1UL << USART_CR1_PCE_Pos)           /*!< 0x00000400 */

+#define USART_CR1_PCE                   USART_CR1_PCE_Msk                      /*!< Parity Control Enable */

+#define USART_CR1_WAKE_Pos              (11U)

+#define USART_CR1_WAKE_Msk              (0x1UL << USART_CR1_WAKE_Pos)          /*!< 0x00000800 */

+#define USART_CR1_WAKE                  USART_CR1_WAKE_Msk                     /*!< Receiver Wakeup method */

+#define USART_CR1_M_Pos                 (12U)

+#define USART_CR1_M_Msk                 (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */

+#define USART_CR1_M                     USART_CR1_M_Msk                        /*!< Word length */

+#define USART_CR1_M0_Pos                (12U)

+#define USART_CR1_M0_Msk                (0x1UL << USART_CR1_M0_Pos)            /*!< 0x00001000 */

+#define USART_CR1_M0                    USART_CR1_M0_Msk                       /*!< Word length - Bit 0 */

+#define USART_CR1_MME_Pos               (13U)

+#define USART_CR1_MME_Msk               (0x1UL << USART_CR1_MME_Pos)           /*!< 0x00002000 */

+#define USART_CR1_MME                   USART_CR1_MME_Msk                      /*!< Mute Mode Enable */

+#define USART_CR1_CMIE_Pos              (14U)

+#define USART_CR1_CMIE_Msk              (0x1UL << USART_CR1_CMIE_Pos)          /*!< 0x00004000 */

+#define USART_CR1_CMIE                  USART_CR1_CMIE_Msk                     /*!< Character match interrupt enable */

+#define USART_CR1_OVER8_Pos             (15U)

+#define USART_CR1_OVER8_Msk             (0x1UL << USART_CR1_OVER8_Pos)         /*!< 0x00008000 */

+#define USART_CR1_OVER8                 USART_CR1_OVER8_Msk                    /*!< Oversampling by 8-bit or 16-bit mode */

+#define USART_CR1_DEDT_Pos              (16U)

+#define USART_CR1_DEDT_Msk              (0x1FUL << USART_CR1_DEDT_Pos)         /*!< 0x001F0000 */

+#define USART_CR1_DEDT                  USART_CR1_DEDT_Msk                     /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */

+#define USART_CR1_DEDT_0                (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */

+#define USART_CR1_DEDT_1                (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */

+#define USART_CR1_DEDT_2                (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */

+#define USART_CR1_DEDT_3                (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */

+#define USART_CR1_DEDT_4                (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */

+#define USART_CR1_DEAT_Pos              (21U)

+#define USART_CR1_DEAT_Msk              (0x1FUL << USART_CR1_DEAT_Pos)         /*!< 0x03E00000 */

+#define USART_CR1_DEAT                  USART_CR1_DEAT_Msk                     /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */

+#define USART_CR1_DEAT_0                (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */

+#define USART_CR1_DEAT_1                (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */

+#define USART_CR1_DEAT_2                (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */

+#define USART_CR1_DEAT_3                (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */

+#define USART_CR1_DEAT_4                (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */

+#define USART_CR1_RTOIE_Pos             (26U)

+#define USART_CR1_RTOIE_Msk             (0x1UL << USART_CR1_RTOIE_Pos)         /*!< 0x04000000 */

+#define USART_CR1_RTOIE                 USART_CR1_RTOIE_Msk                    /*!< Receive Time Out interrupt enable */

+#define USART_CR1_EOBIE_Pos             (27U)

+#define USART_CR1_EOBIE_Msk             (0x1UL << USART_CR1_EOBIE_Pos)         /*!< 0x08000000 */

+#define USART_CR1_EOBIE                 USART_CR1_EOBIE_Msk                    /*!< End of Block interrupt enable */

+#define USART_CR1_M1_Pos                (28U)

+#define USART_CR1_M1_Msk                (0x1UL << USART_CR1_M1_Pos)            /*!< 0x10000000 */

+#define USART_CR1_M1                    USART_CR1_M1_Msk                       /*!< Word length - Bit 1 */

+#define USART_CR1_FIFOEN_Pos            (29U)

+#define USART_CR1_FIFOEN_Msk            (0x1UL << USART_CR1_FIFOEN_Pos)        /*!< 0x20000000 */

+#define USART_CR1_FIFOEN                USART_CR1_FIFOEN_Msk                   /*!< FIFO mode enable */

+#define USART_CR1_TXFEIE_Pos            (30U)

+#define USART_CR1_TXFEIE_Msk            (0x1UL << USART_CR1_TXFEIE_Pos)        /*!< 0x40000000 */

+#define USART_CR1_TXFEIE                USART_CR1_TXFEIE_Msk                   /*!< TXFIFO empty interrupt enable */

+#define USART_CR1_RXFFIE_Pos            (31U)

+#define USART_CR1_RXFFIE_Msk            (0x1UL << USART_CR1_RXFFIE_Pos)        /*!< 0x80000000 */

+#define USART_CR1_RXFFIE                USART_CR1_RXFFIE_Msk                   /*!< RXFIFO Full interrupt enable */

+

+/* Legacy define */

+#define  USART_CR1_RXNEIE  USART_CR1_RXNEIE_RXFNEIE

+#define  USART_CR1_TXEIE   USART_CR1_TXEIE_TXFNFIE

+

+/******************  Bit definition for USART_CR2 register  *******************/

+#define USART_CR2_SLVEN_Pos             (0U)

+#define USART_CR2_SLVEN_Msk             (0x1UL << USART_CR2_SLVEN_Pos)         /*!< 0x00000001 */

+#define USART_CR2_SLVEN                 USART_CR2_SLVEN_Msk                    /*!< Synchronous Slave mode Enable */

+#define USART_CR2_DIS_NSS_Pos           (3U)

+#define USART_CR2_DIS_NSS_Msk           (0x1UL << USART_CR2_DIS_NSS_Pos)       /*!< 0x00000008 */

+#define USART_CR2_DIS_NSS               USART_CR2_DIS_NSS_Msk                  /*!< Negative Slave Select (NSS) pin management */

+#define USART_CR2_ADDM7_Pos             (4U)

+#define USART_CR2_ADDM7_Msk             (0x1UL << USART_CR2_ADDM7_Pos)         /*!< 0x00000010 */

+#define USART_CR2_ADDM7                 USART_CR2_ADDM7_Msk                    /*!< 7-bit or 4-bit Address Detection */

+#define USART_CR2_LBDL_Pos              (5U)

+#define USART_CR2_LBDL_Msk              (0x1UL << USART_CR2_LBDL_Pos)          /*!< 0x00000020 */

+#define USART_CR2_LBDL                  USART_CR2_LBDL_Msk                     /*!< LIN Break Detection Length */

+#define USART_CR2_LBDIE_Pos             (6U)

+#define USART_CR2_LBDIE_Msk             (0x1UL << USART_CR2_LBDIE_Pos)         /*!< 0x00000040 */

+#define USART_CR2_LBDIE                 USART_CR2_LBDIE_Msk                    /*!< LIN Break Detection Interrupt Enable */

+#define USART_CR2_LBCL_Pos              (8U)

+#define USART_CR2_LBCL_Msk              (0x1UL << USART_CR2_LBCL_Pos)          /*!< 0x00000100 */

+#define USART_CR2_LBCL                  USART_CR2_LBCL_Msk                     /*!< Last Bit Clock pulse */

+#define USART_CR2_CPHA_Pos              (9U)

+#define USART_CR2_CPHA_Msk              (0x1UL << USART_CR2_CPHA_Pos)          /*!< 0x00000200 */

+#define USART_CR2_CPHA                  USART_CR2_CPHA_Msk                     /*!< Clock Phase */

+#define USART_CR2_CPOL_Pos              (10U)

+#define USART_CR2_CPOL_Msk              (0x1UL << USART_CR2_CPOL_Pos)          /*!< 0x00000400 */

+#define USART_CR2_CPOL                  USART_CR2_CPOL_Msk                     /*!< Clock Polarity */

+#define USART_CR2_CLKEN_Pos             (11U)

+#define USART_CR2_CLKEN_Msk             (0x1UL << USART_CR2_CLKEN_Pos)         /*!< 0x00000800 */

+#define USART_CR2_CLKEN                 USART_CR2_CLKEN_Msk                    /*!< Clock Enable */

+#define USART_CR2_STOP_Pos              (12U)

+#define USART_CR2_STOP_Msk              (0x3UL << USART_CR2_STOP_Pos)          /*!< 0x00003000 */

+#define USART_CR2_STOP                  USART_CR2_STOP_Msk                     /*!< STOP[1:0] bits (STOP bits) */

+#define USART_CR2_STOP_0                (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */

+#define USART_CR2_STOP_1                (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */

+#define USART_CR2_LINEN_Pos             (14U)

+#define USART_CR2_LINEN_Msk             (0x1UL << USART_CR2_LINEN_Pos)         /*!< 0x00004000 */

+#define USART_CR2_LINEN                 USART_CR2_LINEN_Msk                    /*!< LIN mode enable */

+#define USART_CR2_SWAP_Pos              (15U)

+#define USART_CR2_SWAP_Msk              (0x1UL << USART_CR2_SWAP_Pos)          /*!< 0x00008000 */

+#define USART_CR2_SWAP                  USART_CR2_SWAP_Msk                     /*!< SWAP TX/RX pins */

+#define USART_CR2_RXINV_Pos             (16U)

+#define USART_CR2_RXINV_Msk             (0x1UL << USART_CR2_RXINV_Pos)         /*!< 0x00010000 */

+#define USART_CR2_RXINV                 USART_CR2_RXINV_Msk                    /*!< RX pin active level inversion */

+#define USART_CR2_TXINV_Pos             (17U)

+#define USART_CR2_TXINV_Msk             (0x1UL << USART_CR2_TXINV_Pos)         /*!< 0x00020000 */

+#define USART_CR2_TXINV                 USART_CR2_TXINV_Msk                    /*!< TX pin active level inversion */

+#define USART_CR2_DATAINV_Pos           (18U)

+#define USART_CR2_DATAINV_Msk           (0x1UL << USART_CR2_DATAINV_Pos)       /*!< 0x00040000 */

+#define USART_CR2_DATAINV               USART_CR2_DATAINV_Msk                  /*!< Binary data inversion */

+#define USART_CR2_MSBFIRST_Pos          (19U)

+#define USART_CR2_MSBFIRST_Msk          (0x1UL << USART_CR2_MSBFIRST_Pos)      /*!< 0x00080000 */

+#define USART_CR2_MSBFIRST              USART_CR2_MSBFIRST_Msk                 /*!< Most Significant Bit First */

+#define USART_CR2_ABREN_Pos             (20U)

+#define USART_CR2_ABREN_Msk             (0x1UL << USART_CR2_ABREN_Pos)         /*!< 0x00100000 */

+#define USART_CR2_ABREN                 USART_CR2_ABREN_Msk                    /*!< Auto Baud-Rate Enable*/

+#define USART_CR2_ABRMODE_Pos           (21U)

+#define USART_CR2_ABRMODE_Msk           (0x3UL << USART_CR2_ABRMODE_Pos)       /*!< 0x00600000 */

+#define USART_CR2_ABRMODE               USART_CR2_ABRMODE_Msk                  /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */

+#define USART_CR2_ABRMODE_0             (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */

+#define USART_CR2_ABRMODE_1             (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */

+#define USART_CR2_RTOEN_Pos             (23U)

+#define USART_CR2_RTOEN_Msk             (0x1UL << USART_CR2_RTOEN_Pos)         /*!< 0x00800000 */

+#define USART_CR2_RTOEN                 USART_CR2_RTOEN_Msk                    /*!< Receiver Time-Out enable */

+#define USART_CR2_ADD_Pos               (24U)

+#define USART_CR2_ADD_Msk               (0xFFUL << USART_CR2_ADD_Pos)          /*!< 0xFF000000 */

+#define USART_CR2_ADD                   USART_CR2_ADD_Msk                      /*!< Address of the USART node */

+

+/******************  Bit definition for USART_CR3 register  *******************/

+#define USART_CR3_EIE_Pos               (0U)

+#define USART_CR3_EIE_Msk               (0x1UL << USART_CR3_EIE_Pos)           /*!< 0x00000001 */

+#define USART_CR3_EIE                   USART_CR3_EIE_Msk                      /*!< Error Interrupt Enable */

+#define USART_CR3_IREN_Pos              (1U)

+#define USART_CR3_IREN_Msk              (0x1UL << USART_CR3_IREN_Pos)          /*!< 0x00000002 */

+#define USART_CR3_IREN                  USART_CR3_IREN_Msk                     /*!< IrDA mode Enable */

+#define USART_CR3_IRLP_Pos              (2U)

+#define USART_CR3_IRLP_Msk              (0x1UL << USART_CR3_IRLP_Pos)          /*!< 0x00000004 */

+#define USART_CR3_IRLP                  USART_CR3_IRLP_Msk                     /*!< IrDA Low-Power */

+#define USART_CR3_HDSEL_Pos             (3U)

+#define USART_CR3_HDSEL_Msk             (0x1UL << USART_CR3_HDSEL_Pos)         /*!< 0x00000008 */

+#define USART_CR3_HDSEL                 USART_CR3_HDSEL_Msk                    /*!< Half-Duplex Selection */

+#define USART_CR3_NACK_Pos              (4U)

+#define USART_CR3_NACK_Msk              (0x1UL << USART_CR3_NACK_Pos)          /*!< 0x00000010 */

+#define USART_CR3_NACK                  USART_CR3_NACK_Msk                     /*!< SmartCard NACK enable */

+#define USART_CR3_SCEN_Pos              (5U)

+#define USART_CR3_SCEN_Msk              (0x1UL << USART_CR3_SCEN_Pos)          /*!< 0x00000020 */

+#define USART_CR3_SCEN                  USART_CR3_SCEN_Msk                     /*!< SmartCard mode enable */

+#define USART_CR3_DMAR_Pos              (6U)

+#define USART_CR3_DMAR_Msk              (0x1UL << USART_CR3_DMAR_Pos)          /*!< 0x00000040 */

+#define USART_CR3_DMAR                  USART_CR3_DMAR_Msk                     /*!< DMA Enable Receiver */

+#define USART_CR3_DMAT_Pos              (7U)

+#define USART_CR3_DMAT_Msk              (0x1UL << USART_CR3_DMAT_Pos)          /*!< 0x00000080 */

+#define USART_CR3_DMAT                  USART_CR3_DMAT_Msk                     /*!< DMA Enable Transmitter */

+#define USART_CR3_RTSE_Pos              (8U)

+#define USART_CR3_RTSE_Msk              (0x1UL << USART_CR3_RTSE_Pos)          /*!< 0x00000100 */

+#define USART_CR3_RTSE                  USART_CR3_RTSE_Msk                     /*!< RTS Enable */

+#define USART_CR3_CTSE_Pos              (9U)

+#define USART_CR3_CTSE_Msk              (0x1UL << USART_CR3_CTSE_Pos)          /*!< 0x00000200 */

+#define USART_CR3_CTSE                  USART_CR3_CTSE_Msk                     /*!< CTS Enable */

+#define USART_CR3_CTSIE_Pos             (10U)

+#define USART_CR3_CTSIE_Msk             (0x1UL << USART_CR3_CTSIE_Pos)         /*!< 0x00000400 */

+#define USART_CR3_CTSIE                 USART_CR3_CTSIE_Msk                    /*!< CTS Interrupt Enable */

+#define USART_CR3_ONEBIT_Pos            (11U)

+#define USART_CR3_ONEBIT_Msk            (0x1UL << USART_CR3_ONEBIT_Pos)        /*!< 0x00000800 */

+#define USART_CR3_ONEBIT                USART_CR3_ONEBIT_Msk                   /*!< One sample bit method enable */

+#define USART_CR3_OVRDIS_Pos            (12U)

+#define USART_CR3_OVRDIS_Msk            (0x1UL << USART_CR3_OVRDIS_Pos)        /*!< 0x00001000 */

+#define USART_CR3_OVRDIS                USART_CR3_OVRDIS_Msk                   /*!< Overrun Disable */

+#define USART_CR3_DDRE_Pos              (13U)

+#define USART_CR3_DDRE_Msk              (0x1UL << USART_CR3_DDRE_Pos)          /*!< 0x00002000 */

+#define USART_CR3_DDRE                  USART_CR3_DDRE_Msk                     /*!< DMA Disable on Reception Error */

+#define USART_CR3_DEM_Pos               (14U)

+#define USART_CR3_DEM_Msk               (0x1UL << USART_CR3_DEM_Pos)           /*!< 0x00004000 */

+#define USART_CR3_DEM                   USART_CR3_DEM_Msk                      /*!< Driver Enable Mode */

+#define USART_CR3_DEP_Pos               (15U)

+#define USART_CR3_DEP_Msk               (0x1UL << USART_CR3_DEP_Pos)           /*!< 0x00008000 */

+#define USART_CR3_DEP                   USART_CR3_DEP_Msk                      /*!< Driver Enable Polarity Selection */

+#define USART_CR3_SCARCNT_Pos           (17U)

+#define USART_CR3_SCARCNT_Msk           (0x7UL << USART_CR3_SCARCNT_Pos)       /*!< 0x000E0000 */

+#define USART_CR3_SCARCNT               USART_CR3_SCARCNT_Msk                  /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */

+#define USART_CR3_SCARCNT_0             (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */

+#define USART_CR3_SCARCNT_1             (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */

+#define USART_CR3_SCARCNT_2             (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */

+#define USART_CR3_WUS_Pos               (20U)

+#define USART_CR3_WUS_Msk               (0x3UL << USART_CR3_WUS_Pos)           /*!< 0x00300000 */

+#define USART_CR3_WUS                   USART_CR3_WUS_Msk                      /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */

+#define USART_CR3_WUS_0                 (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */

+#define USART_CR3_WUS_1                 (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */

+#define USART_CR3_WUFIE_Pos             (22U)

+#define USART_CR3_WUFIE_Msk             (0x1UL << USART_CR3_WUFIE_Pos)         /*!< 0x00400000 */

+#define USART_CR3_WUFIE                 USART_CR3_WUFIE_Msk                    /*!< Wake Up Interrupt Enable */

+#define USART_CR3_TXFTIE_Pos            (23U)

+#define USART_CR3_TXFTIE_Msk            (0x1UL << USART_CR3_TXFTIE_Pos)        /*!< 0x00800000 */

+#define USART_CR3_TXFTIE                USART_CR3_TXFTIE_Msk                   /*!< TXFIFO threshold interrupt enable */

+#define USART_CR3_TCBGTIE_Pos           (24U)

+#define USART_CR3_TCBGTIE_Msk           (0x1UL << USART_CR3_TCBGTIE_Pos)       /*!< 0x01000000 */

+#define USART_CR3_TCBGTIE               USART_CR3_TCBGTIE_Msk                  /*!< Transmission Complete before guard time, interrupt enable */

+#define USART_CR3_RXFTCFG_Pos           (25U)

+#define USART_CR3_RXFTCFG_Msk           (0x7UL << USART_CR3_RXFTCFG_Pos)       /*!< 0x0E000000 */

+#define USART_CR3_RXFTCFG               USART_CR3_RXFTCFG_Msk                  /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */

+#define USART_CR3_RXFTCFG_0             (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */

+#define USART_CR3_RXFTCFG_1             (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */

+#define USART_CR3_RXFTCFG_2             (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */

+#define USART_CR3_RXFTIE_Pos            (28U)

+#define USART_CR3_RXFTIE_Msk            (0x1UL << USART_CR3_RXFTIE_Pos)        /*!< 0x10000000 */

+#define USART_CR3_RXFTIE                USART_CR3_RXFTIE_Msk                   /*!< RXFIFO threshold interrupt enable */

+#define USART_CR3_TXFTCFG_Pos           (29U)

+#define USART_CR3_TXFTCFG_Msk           (0x7UL << USART_CR3_TXFTCFG_Pos)       /*!< 0xE0000000 */

+#define USART_CR3_TXFTCFG               USART_CR3_TXFTCFG_Msk                  /*!< TXFIFO [2:0] threshold configuration */

+#define USART_CR3_TXFTCFG_0             (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */

+#define USART_CR3_TXFTCFG_1             (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */

+#define USART_CR3_TXFTCFG_2             (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */

+

+/******************  Bit definition for USART_BRR register  *******************/

+#define USART_BRR_DIV_FRACTION_Pos      (0U)

+#define USART_BRR_DIV_FRACTION_Msk      (0xFUL << USART_BRR_DIV_FRACTION_Pos)  /*!< 0x0000000F */

+#define USART_BRR_DIV_FRACTION          USART_BRR_DIV_FRACTION_Msk             /*!< Fraction of USARTDIV */

+#define USART_BRR_DIV_MANTISSA_Pos      (4U)

+#define USART_BRR_DIV_MANTISSA_Msk      (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */

+#define USART_BRR_DIV_MANTISSA          USART_BRR_DIV_MANTISSA_Msk             /*!< Mantissa of USARTDIV */

+

+/******************  Bit definition for USART_GTPR register  ******************/

+#define USART_GTPR_PSC_Pos              (0U)

+#define USART_GTPR_PSC_Msk              (0xFFUL << USART_GTPR_PSC_Pos)         /*!< 0x000000FF */

+#define USART_GTPR_PSC                  USART_GTPR_PSC_Msk                     /*!< PSC[7:0] bits (Prescaler value) */

+#define USART_GTPR_GT_Pos               (8U)

+#define USART_GTPR_GT_Msk               (0xFFUL << USART_GTPR_GT_Pos)          /*!< 0x0000FF00 */

+#define USART_GTPR_GT                   USART_GTPR_GT_Msk                      /*!< GT[7:0] bits (Guard time value) */

+

+/*******************  Bit definition for USART_RTOR register  *****************/

+#define USART_RTOR_RTO_Pos              (0U)

+#define USART_RTOR_RTO_Msk              (0xFFFFFFUL << USART_RTOR_RTO_Pos)     /*!< 0x00FFFFFF */

+#define USART_RTOR_RTO                  USART_RTOR_RTO_Msk                     /*!< Receiver Time Out Value */

+#define USART_RTOR_BLEN_Pos             (24U)

+#define USART_RTOR_BLEN_Msk             (0xFFUL << USART_RTOR_BLEN_Pos)        /*!< 0xFF000000 */

+#define USART_RTOR_BLEN                 USART_RTOR_BLEN_Msk                    /*!< Block Length */

+

+/*******************  Bit definition for USART_RQR register  ******************/

+#define USART_RQR_ABRRQ_Pos             (0U)

+#define USART_RQR_ABRRQ_Msk             (0x1UL << USART_RQR_ABRRQ_Pos)         /*!< 0x00000001 */

+#define USART_RQR_ABRRQ                 USART_RQR_ABRRQ_Msk                    /*!< Auto-Baud Rate Request */

+#define USART_RQR_SBKRQ_Pos             (1U)

+#define USART_RQR_SBKRQ_Msk             (0x1UL << USART_RQR_SBKRQ_Pos)         /*!< 0x00000002 */

+#define USART_RQR_SBKRQ                 USART_RQR_SBKRQ_Msk                    /*!< Send Break Request */

+#define USART_RQR_MMRQ_Pos              (2U)

+#define USART_RQR_MMRQ_Msk              (0x1UL << USART_RQR_MMRQ_Pos)          /*!< 0x00000004 */

+#define USART_RQR_MMRQ                  USART_RQR_MMRQ_Msk                     /*!< Mute Mode Request */

+#define USART_RQR_RXFRQ_Pos             (3U)

+#define USART_RQR_RXFRQ_Msk             (0x1UL << USART_RQR_RXFRQ_Pos)         /*!< 0x00000008 */

+#define USART_RQR_RXFRQ                 USART_RQR_RXFRQ_Msk                    /*!< Receive Data flush Request */

+#define USART_RQR_TXFRQ_Pos             (4U)

+#define USART_RQR_TXFRQ_Msk             (0x1UL << USART_RQR_TXFRQ_Pos)         /*!< 0x00000010 */

+#define USART_RQR_TXFRQ                 USART_RQR_TXFRQ_Msk                    /*!< Transmit data flush Request */

+

+/*******************  Bit definition for USART_ISR register  ******************/

+#define USART_ISR_PE_Pos                (0U)

+#define USART_ISR_PE_Msk                (0x1UL << USART_ISR_PE_Pos)            /*!< 0x00000001 */

+#define USART_ISR_PE                    USART_ISR_PE_Msk                       /*!< Parity Error */

+#define USART_ISR_FE_Pos                (1U)

+#define USART_ISR_FE_Msk                (0x1UL << USART_ISR_FE_Pos)            /*!< 0x00000002 */

+#define USART_ISR_FE                    USART_ISR_FE_Msk                       /*!< Framing Error */

+#define USART_ISR_NE_Pos                (2U)

+#define USART_ISR_NE_Msk                (0x1UL << USART_ISR_NE_Pos)            /*!< 0x00000004 */

+#define USART_ISR_NE                    USART_ISR_NE_Msk                       /*!< Noise detected Flag */

+#define USART_ISR_ORE_Pos               (3U)

+#define USART_ISR_ORE_Msk               (0x1UL << USART_ISR_ORE_Pos)           /*!< 0x00000008 */

+#define USART_ISR_ORE                   USART_ISR_ORE_Msk                      /*!< OverRun Error */

+#define USART_ISR_IDLE_Pos              (4U)

+#define USART_ISR_IDLE_Msk              (0x1UL << USART_ISR_IDLE_Pos)          /*!< 0x00000010 */

+#define USART_ISR_IDLE                  USART_ISR_IDLE_Msk                     /*!< IDLE line detected */

+#define USART_ISR_RXNE_RXFNE_Pos        (5U)

+#define USART_ISR_RXNE_RXFNE_Msk        (0x1UL << USART_ISR_RXNE_RXFNE_Pos)    /*!< 0x00000020 */

+#define USART_ISR_RXNE_RXFNE            USART_ISR_RXNE_RXFNE_Msk               /*!< Read Data Register or RX FIFO Not Empty */

+#define USART_ISR_TC_Pos                (6U)

+#define USART_ISR_TC_Msk                (0x1UL << USART_ISR_TC_Pos)            /*!< 0x00000040 */

+#define USART_ISR_TC                    USART_ISR_TC_Msk                       /*!< Transmission Complete */

+#define USART_ISR_TXE_TXFNF_Pos         (7U)

+#define USART_ISR_TXE_TXFNF_Msk         (0x1UL << USART_ISR_TXE_TXFNF_Pos)     /*!< 0x00000080 */

+#define USART_ISR_TXE_TXFNF             USART_ISR_TXE_TXFNF_Msk                /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */

+#define USART_ISR_LBDF_Pos              (8U)

+#define USART_ISR_LBDF_Msk              (0x1UL << USART_ISR_LBDF_Pos)          /*!< 0x00000100 */

+#define USART_ISR_LBDF                  USART_ISR_LBDF_Msk                     /*!< LIN Break Detection Flag */

+#define USART_ISR_CTSIF_Pos             (9U)

+#define USART_ISR_CTSIF_Msk             (0x1UL << USART_ISR_CTSIF_Pos)         /*!< 0x00000200 */

+#define USART_ISR_CTSIF                 USART_ISR_CTSIF_Msk                    /*!< CTS interrupt flag */

+#define USART_ISR_CTS_Pos               (10U)

+#define USART_ISR_CTS_Msk               (0x1UL << USART_ISR_CTS_Pos)           /*!< 0x00000400 */

+#define USART_ISR_CTS                   USART_ISR_CTS_Msk                      /*!< CTS flag */

+#define USART_ISR_RTOF_Pos              (11U)

+#define USART_ISR_RTOF_Msk              (0x1UL << USART_ISR_RTOF_Pos)          /*!< 0x00000800 */

+#define USART_ISR_RTOF                  USART_ISR_RTOF_Msk                     /*!< Receiver Time Out */

+#define USART_ISR_EOBF_Pos              (12U)

+#define USART_ISR_EOBF_Msk              (0x1UL << USART_ISR_EOBF_Pos)          /*!< 0x00001000 */

+#define USART_ISR_EOBF                  USART_ISR_EOBF_Msk                     /*!< End Of Block Flag */

+#define USART_ISR_UDR_Pos               (13U)

+#define USART_ISR_UDR_Msk               (0x1UL << USART_ISR_UDR_Pos)           /*!< 0x00002000 */

+#define USART_ISR_UDR                   USART_ISR_UDR_Msk                      /*!< SPI slave underrun error flag */

+#define USART_ISR_ABRE_Pos              (14U)

+#define USART_ISR_ABRE_Msk              (0x1UL << USART_ISR_ABRE_Pos)          /*!< 0x00004000 */

+#define USART_ISR_ABRE                  USART_ISR_ABRE_Msk                     /*!< Auto-Baud Rate Error */

+#define USART_ISR_ABRF_Pos              (15U)

+#define USART_ISR_ABRF_Msk              (0x1UL << USART_ISR_ABRF_Pos)          /*!< 0x00008000 */

+#define USART_ISR_ABRF                  USART_ISR_ABRF_Msk                     /*!< Auto-Baud Rate Flag */

+#define USART_ISR_BUSY_Pos              (16U)

+#define USART_ISR_BUSY_Msk              (0x1UL << USART_ISR_BUSY_Pos)          /*!< 0x00010000 */

+#define USART_ISR_BUSY                  USART_ISR_BUSY_Msk                     /*!< Busy Flag */

+#define USART_ISR_CMF_Pos               (17U)

+#define USART_ISR_CMF_Msk               (0x1UL << USART_ISR_CMF_Pos)           /*!< 0x00020000 */

+#define USART_ISR_CMF                   USART_ISR_CMF_Msk                      /*!< Character Match Flag */

+#define USART_ISR_SBKF_Pos              (18U)

+#define USART_ISR_SBKF_Msk              (0x1UL << USART_ISR_SBKF_Pos)          /*!< 0x00040000 */

+#define USART_ISR_SBKF                  USART_ISR_SBKF_Msk                     /*!< Send Break Flag */

+#define USART_ISR_RWU_Pos               (19U)

+#define USART_ISR_RWU_Msk               (0x1UL << USART_ISR_RWU_Pos)           /*!< 0x00080000 */

+#define USART_ISR_RWU                   USART_ISR_RWU_Msk                      /*!< Receive Wake Up from mute mode Flag */

+#define USART_ISR_WUF_Pos               (20U)

+#define USART_ISR_WUF_Msk               (0x1UL << USART_ISR_WUF_Pos)           /*!< 0x00100000 */

+#define USART_ISR_WUF                   USART_ISR_WUF_Msk                      /*!< Wake Up from stop mode Flag */

+#define USART_ISR_TEACK_Pos             (21U)

+#define USART_ISR_TEACK_Msk             (0x1UL << USART_ISR_TEACK_Pos)         /*!< 0x00200000 */

+#define USART_ISR_TEACK                 USART_ISR_TEACK_Msk                    /*!< Transmit Enable Acknowledge Flag */

+#define USART_ISR_REACK_Pos             (22U)

+#define USART_ISR_REACK_Msk             (0x1UL << USART_ISR_REACK_Pos)         /*!< 0x00400000 */

+#define USART_ISR_REACK                 USART_ISR_REACK_Msk                    /*!< Receive Enable Acknowledge Flag */

+#define USART_ISR_TXFE_Pos              (23U)

+#define USART_ISR_TXFE_Msk              (0x1UL << USART_ISR_TXFE_Pos)          /*!< 0x00800000 */

+#define USART_ISR_TXFE                  USART_ISR_TXFE_Msk                     /*!< TXFIFO Empty */

+#define USART_ISR_RXFF_Pos              (24U)

+#define USART_ISR_RXFF_Msk              (0x1UL << USART_ISR_RXFF_Pos)          /*!< 0x01000000 */

+#define USART_ISR_RXFF                  USART_ISR_RXFF_Msk                     /*!< RXFIFO Full Flag */

+#define USART_ISR_TCBGT_Pos             (25U)

+#define USART_ISR_TCBGT_Msk             (0x1UL << USART_ISR_TCBGT_Pos)         /*!< 0x02000000 */

+#define USART_ISR_TCBGT                 USART_ISR_TCBGT_Msk                    /*!< Transmission complete before guard time Flag */

+#define USART_ISR_RXFT_Pos              (26U)

+#define USART_ISR_RXFT_Msk              (0x1UL << USART_ISR_RXFT_Pos)          /*!< 0x04000000 */

+#define USART_ISR_RXFT                  USART_ISR_RXFT_Msk                     /*!< RXFIFO threshold Flag */

+#define USART_ISR_TXFT_Pos              (27U)

+#define USART_ISR_TXFT_Msk              (0x1UL << USART_ISR_TXFT_Pos)          /*!< 0x08000000 */

+#define USART_ISR_TXFT                  USART_ISR_TXFT_Msk                     /*!< TXFIFO threshold Flag */

+

+/*******************  Bit definition for USART_ICR register  ******************/

+#define USART_ICR_PECF_Pos              (0U)

+#define USART_ICR_PECF_Msk              (0x1UL << USART_ICR_PECF_Pos)          /*!< 0x00000001 */

+#define USART_ICR_PECF                  USART_ICR_PECF_Msk                     /*!< Parity Error Clear Flag */

+#define USART_ICR_FECF_Pos              (1U)

+#define USART_ICR_FECF_Msk              (0x1UL << USART_ICR_FECF_Pos)          /*!< 0x00000002 */

+#define USART_ICR_FECF                  USART_ICR_FECF_Msk                     /*!< Framing Error Clear Flag */

+#define USART_ICR_NECF_Pos              (2U)

+#define USART_ICR_NECF_Msk              (0x1UL << USART_ICR_NECF_Pos)          /*!< 0x00000004 */

+#define USART_ICR_NECF                  USART_ICR_NECF_Msk                     /*!< Noise detected Clear Flag */

+#define USART_ICR_ORECF_Pos             (3U)

+#define USART_ICR_ORECF_Msk             (0x1UL << USART_ICR_ORECF_Pos)         /*!< 0x00000008 */

+#define USART_ICR_ORECF                 USART_ICR_ORECF_Msk                    /*!< OverRun Error Clear Flag */

+#define USART_ICR_IDLECF_Pos            (4U)

+#define USART_ICR_IDLECF_Msk            (0x1UL << USART_ICR_IDLECF_Pos)        /*!< 0x00000010 */

+#define USART_ICR_IDLECF                USART_ICR_IDLECF_Msk                   /*!< IDLE line detected Clear Flag */

+#define USART_ICR_TXFECF_Pos            (5U)

+#define USART_ICR_TXFECF_Msk            (0x1UL << USART_ICR_TXFECF_Pos)        /*!< 0x00000020 */

+#define USART_ICR_TXFECF                USART_ICR_TXFECF_Msk                   /*!< TXFIFO empty clear flag */

+#define USART_ICR_TCCF_Pos              (6U)

+#define USART_ICR_TCCF_Msk              (0x1UL << USART_ICR_TCCF_Pos)          /*!< 0x00000040 */

+#define USART_ICR_TCCF                  USART_ICR_TCCF_Msk                     /*!< Transmission Complete Clear Flag */

+#define USART_ICR_TCBGTCF_Pos           (7U)

+#define USART_ICR_TCBGTCF_Msk           (0x1UL << USART_ICR_TCBGTCF_Pos)       /*!< 0x00000080 */

+#define USART_ICR_TCBGTCF               USART_ICR_TCBGTCF_Msk                  /*!< Transmission complete before guard time Clear Flag */

+#define USART_ICR_LBDCF_Pos             (8U)

+#define USART_ICR_LBDCF_Msk             (0x1UL << USART_ICR_LBDCF_Pos)         /*!< 0x00000100 */

+#define USART_ICR_LBDCF                 USART_ICR_LBDCF_Msk                    /*!< LIN Break Detection Clear Flag */

+#define USART_ICR_CTSCF_Pos             (9U)

+#define USART_ICR_CTSCF_Msk             (0x1UL << USART_ICR_CTSCF_Pos)         /*!< 0x00000200 */

+#define USART_ICR_CTSCF                 USART_ICR_CTSCF_Msk                    /*!< CTS Interrupt Clear Flag */

+#define USART_ICR_RTOCF_Pos             (11U)

+#define USART_ICR_RTOCF_Msk             (0x1UL << USART_ICR_RTOCF_Pos)         /*!< 0x00000800 */

+#define USART_ICR_RTOCF                 USART_ICR_RTOCF_Msk                    /*!< Receiver Time Out Clear Flag */

+#define USART_ICR_EOBCF_Pos             (12U)

+#define USART_ICR_EOBCF_Msk             (0x1UL << USART_ICR_EOBCF_Pos)         /*!< 0x00001000 */

+#define USART_ICR_EOBCF                 USART_ICR_EOBCF_Msk                    /*!< End Of Block Clear Flag */

+#define USART_ICR_UDRCF_Pos             (13U)

+#define USART_ICR_UDRCF_Msk             (0x1UL << USART_ICR_UDRCF_Pos)         /*!< 0x00002000 */

+#define USART_ICR_UDRCF                 USART_ICR_UDRCF_Msk                    /*!< SPI slave underrun clear flag */

+#define USART_ICR_CMCF_Pos              (17U)

+#define USART_ICR_CMCF_Msk              (0x1UL << USART_ICR_CMCF_Pos)          /*!< 0x00020000 */

+#define USART_ICR_CMCF                  USART_ICR_CMCF_Msk                     /*!< Character Match Clear Flag */

+#define USART_ICR_WUCF_Pos              (20U)

+#define USART_ICR_WUCF_Msk              (0x1UL << USART_ICR_WUCF_Pos)          /*!< 0x00100000 */

+#define USART_ICR_WUCF                  USART_ICR_WUCF_Msk                     /*!< Wake Up from stop mode Clear Flag */

+

+/*******************  Bit definition for USART_RDR register  ******************/

+#define USART_RDR_RDR_Pos               (0U)

+#define USART_RDR_RDR_Msk               (0x1FFUL << USART_RDR_RDR_Pos)         /*!< 0x000001FF */

+#define USART_RDR_RDR                   USART_RDR_RDR_Msk                      /*!< RDR[8:0] bits (Receive Data value) */

+

+/*******************  Bit definition for USART_TDR register  ******************/

+#define USART_TDR_TDR_Pos               (0U)

+#define USART_TDR_TDR_Msk               (0x1FFUL << USART_TDR_TDR_Pos)         /*!< 0x000001FF */

+#define USART_TDR_TDR                   USART_TDR_TDR_Msk                      /*!< TDR[8:0] bits (Transmit Data value) */

+

+/*******************  Bit definition for USART_PRESC register  ******************/

+#define USART_PRESC_PRESCALER_Pos       (0U)

+#define USART_PRESC_PRESCALER_Msk       (0xFUL << USART_PRESC_PRESCALER_Pos)   /*!< 0x0000000F */

+#define USART_PRESC_PRESCALER           USART_PRESC_PRESCALER_Msk              /*!< PRESCALER[3:0] bits (Clock prescaler) */

+#define USART_PRESC_PRESCALER_0         (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */

+#define USART_PRESC_PRESCALER_1         (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */

+#define USART_PRESC_PRESCALER_2         (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */

+#define USART_PRESC_PRESCALER_3         (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */

+

+/******************************************************************************/

+/*                                                                            */

+/*           Single Wire Protocol Master Interface (SWPMI)                    */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for SWPMI_CR register   ********************/

+#define SWPMI_CR_RXDMA_Pos       (0U)

+#define SWPMI_CR_RXDMA_Msk       (0x1UL << SWPMI_CR_RXDMA_Pos)                 /*!< 0x00000001 */

+#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */

+#define SWPMI_CR_TXDMA_Pos       (1U)

+#define SWPMI_CR_TXDMA_Msk       (0x1UL << SWPMI_CR_TXDMA_Pos)                 /*!< 0x00000002 */

+#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */

+#define SWPMI_CR_RXMODE_Pos      (2U)

+#define SWPMI_CR_RXMODE_Msk      (0x1UL << SWPMI_CR_RXMODE_Pos)                /*!< 0x00000004 */

+#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */

+#define SWPMI_CR_TXMODE_Pos      (3U)

+#define SWPMI_CR_TXMODE_Msk      (0x1UL << SWPMI_CR_TXMODE_Pos)                /*!< 0x00000008 */

+#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */

+#define SWPMI_CR_LPBK_Pos        (4U)

+#define SWPMI_CR_LPBK_Msk        (0x1UL << SWPMI_CR_LPBK_Pos)                  /*!< 0x00000010 */

+#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */

+#define SWPMI_CR_SWPACT_Pos      (5U)

+#define SWPMI_CR_SWPACT_Msk      (0x1UL << SWPMI_CR_SWPACT_Pos)                /*!< 0x00000020 */

+#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */

+#define SWPMI_CR_DEACT_Pos       (10U)

+#define SWPMI_CR_DEACT_Msk       (0x1UL << SWPMI_CR_DEACT_Pos)                 /*!< 0x00000400 */

+#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */

+#define SWPMI_CR_SWPEN_Pos       (11U)

+#define SWPMI_CR_SWPEN_Msk       (0x1UL << SWPMI_CR_SWPEN_Pos)                 /*!< 0x00000800 */

+#define SWPMI_CR_SWPEN           SWPMI_CR_SWPEN_Msk                            /*!<Single wire protocol master transceiver enable       */

+

+/*******************  Bit definition for SWPMI_BRR register  ********************/

+#define SWPMI_BRR_BR_Pos         (0U)

+#define SWPMI_BRR_BR_Msk         (0xFFUL << SWPMI_BRR_BR_Pos)                  /*!< 0x000000FF */

+#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[7:0] bits (Bitrate prescaler) */

+

+/*******************  Bit definition for SWPMI_ISR register  ********************/

+#define SWPMI_ISR_RXBFF_Pos      (0U)

+#define SWPMI_ISR_RXBFF_Msk      (0x1UL << SWPMI_ISR_RXBFF_Pos)                /*!< 0x00000001 */

+#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */

+#define SWPMI_ISR_TXBEF_Pos      (1U)

+#define SWPMI_ISR_TXBEF_Msk      (0x1UL << SWPMI_ISR_TXBEF_Pos)                /*!< 0x00000002 */

+#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */

+#define SWPMI_ISR_RXBERF_Pos     (2U)

+#define SWPMI_ISR_RXBERF_Msk     (0x1UL << SWPMI_ISR_RXBERF_Pos)               /*!< 0x00000004 */

+#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */

+#define SWPMI_ISR_RXOVRF_Pos     (3U)

+#define SWPMI_ISR_RXOVRF_Msk     (0x1UL << SWPMI_ISR_RXOVRF_Pos)               /*!< 0x00000008 */

+#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */

+#define SWPMI_ISR_TXUNRF_Pos     (4U)

+#define SWPMI_ISR_TXUNRF_Msk     (0x1UL << SWPMI_ISR_TXUNRF_Pos)               /*!< 0x00000010 */

+#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */

+#define SWPMI_ISR_RXNE_Pos       (5U)

+#define SWPMI_ISR_RXNE_Msk       (0x1UL << SWPMI_ISR_RXNE_Pos)                 /*!< 0x00000020 */

+#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */

+#define SWPMI_ISR_TXE_Pos        (6U)

+#define SWPMI_ISR_TXE_Msk        (0x1UL << SWPMI_ISR_TXE_Pos)                  /*!< 0x00000040 */

+#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */

+#define SWPMI_ISR_TCF_Pos        (7U)

+#define SWPMI_ISR_TCF_Msk        (0x1UL << SWPMI_ISR_TCF_Pos)                  /*!< 0x00000080 */

+#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */

+#define SWPMI_ISR_SRF_Pos        (8U)

+#define SWPMI_ISR_SRF_Msk        (0x1UL << SWPMI_ISR_SRF_Pos)                  /*!< 0x00000100 */

+#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */

+#define SWPMI_ISR_SUSP_Pos       (9U)

+#define SWPMI_ISR_SUSP_Msk       (0x1UL << SWPMI_ISR_SUSP_Pos)                 /*!< 0x00000200 */

+#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */

+#define SWPMI_ISR_DEACTF_Pos     (10U)

+#define SWPMI_ISR_DEACTF_Msk     (0x1UL << SWPMI_ISR_DEACTF_Pos)               /*!< 0x00000400 */

+#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */

+#define SWPMI_ISR_RDYF_Pos       (11U)

+#define SWPMI_ISR_RDYF_Msk       (0x1UL << SWPMI_ISR_RDYF_Pos)                 /*!< 0x00000800 */

+#define SWPMI_ISR_RDYF           SWPMI_ISR_RDYF_Msk                            /*!<Transceiver ready flag          */

+

+/*******************  Bit definition for SWPMI_ICR register  ********************/

+#define SWPMI_ICR_CRXBFF_Pos     (0U)

+#define SWPMI_ICR_CRXBFF_Msk     (0x1UL << SWPMI_ICR_CRXBFF_Pos)               /*!< 0x00000001 */

+#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */

+#define SWPMI_ICR_CTXBEF_Pos     (1U)

+#define SWPMI_ICR_CTXBEF_Msk     (0x1UL << SWPMI_ICR_CTXBEF_Pos)               /*!< 0x00000002 */

+#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */

+#define SWPMI_ICR_CRXBERF_Pos    (2U)

+#define SWPMI_ICR_CRXBERF_Msk    (0x1UL << SWPMI_ICR_CRXBERF_Pos)              /*!< 0x00000004 */

+#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */

+#define SWPMI_ICR_CRXOVRF_Pos    (3U)

+#define SWPMI_ICR_CRXOVRF_Msk    (0x1UL << SWPMI_ICR_CRXOVRF_Pos)              /*!< 0x00000008 */

+#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */

+#define SWPMI_ICR_CTXUNRF_Pos    (4U)

+#define SWPMI_ICR_CTXUNRF_Msk    (0x1UL << SWPMI_ICR_CTXUNRF_Pos)              /*!< 0x00000010 */

+#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */

+#define SWPMI_ICR_CTCF_Pos       (7U)

+#define SWPMI_ICR_CTCF_Msk       (0x1UL << SWPMI_ICR_CTCF_Pos)                 /*!< 0x00000080 */

+#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */

+#define SWPMI_ICR_CSRF_Pos       (8U)

+#define SWPMI_ICR_CSRF_Msk       (0x1UL << SWPMI_ICR_CSRF_Pos)                 /*!< 0x00000100 */

+#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */

+#define SWPMI_ICR_CRDYF_Pos      (11U)

+#define SWPMI_ICR_CRDYF_Msk      (0x1UL << SWPMI_ICR_CRDYF_Pos)                /*!< 0x00000800 */

+#define SWPMI_ICR_CRDYF          SWPMI_ICR_CRDYF_Msk                           /*!<Clear transceiver ready flag         */

+

+/*******************  Bit definition for SWPMI_IER register  ********************/

+#define SWPMI_IER_RXBFIE_Pos     (0U)

+#define SWPMI_IER_RXBFIE_Msk     (0x1UL << SWPMI_IER_RXBFIE_Pos)               /*!< 0x00000001 */

+#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */

+#define SWPMI_IER_TXBEIE_Pos     (1U)

+#define SWPMI_IER_TXBEIE_Msk     (0x1UL << SWPMI_IER_TXBEIE_Pos)               /*!< 0x00000002 */

+#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */

+#define SWPMI_IER_RXBERIE_Pos    (2U)

+#define SWPMI_IER_RXBERIE_Msk    (0x1UL << SWPMI_IER_RXBERIE_Pos)              /*!< 0x00000004 */

+#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */

+#define SWPMI_IER_RXOVRIE_Pos    (3U)

+#define SWPMI_IER_RXOVRIE_Msk    (0x1UL << SWPMI_IER_RXOVRIE_Pos)              /*!< 0x00000008 */

+#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */

+#define SWPMI_IER_TXUNRIE_Pos    (4U)

+#define SWPMI_IER_TXUNRIE_Msk    (0x1UL << SWPMI_IER_TXUNRIE_Pos)              /*!< 0x00000010 */

+#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */

+#define SWPMI_IER_RIE_Pos        (5U)

+#define SWPMI_IER_RIE_Msk        (0x1UL << SWPMI_IER_RIE_Pos)                  /*!< 0x00000020 */

+#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */

+#define SWPMI_IER_TIE_Pos        (6U)

+#define SWPMI_IER_TIE_Msk        (0x1UL << SWPMI_IER_TIE_Pos)                  /*!< 0x00000040 */

+#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */

+#define SWPMI_IER_TCIE_Pos       (7U)

+#define SWPMI_IER_TCIE_Msk       (0x1UL << SWPMI_IER_TCIE_Pos)                 /*!< 0x00000080 */

+#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */

+#define SWPMI_IER_SRIE_Pos       (8U)

+#define SWPMI_IER_SRIE_Msk       (0x1UL << SWPMI_IER_SRIE_Pos)                 /*!< 0x00000100 */

+#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */

+#define SWPMI_IER_RDYIE_Pos      (11U)

+#define SWPMI_IER_RDYIE_Msk      (0x1UL << SWPMI_IER_RDYIE_Pos)                /*!< 0x00000800 */

+#define SWPMI_IER_RDYIE          SWPMI_IER_RDYIE_Msk                           /*!<Transceiver ready interrupt enable          */

+

+/*******************  Bit definition for SWPMI_RFL register  ********************/

+#define SWPMI_RFL_RFL_Pos        (0U)

+#define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */

+#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */

+#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */

+

+/*******************  Bit definition for SWPMI_TDR register  ********************/

+#define SWPMI_TDR_TD_Pos         (0U)

+#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)            /*!< 0xFFFFFFFF */

+#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */

+

+/*******************  Bit definition for SWPMI_RDR register  ********************/

+#define SWPMI_RDR_RD_Pos         (0U)

+#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)            /*!< 0xFFFFFFFF */

+#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Recive Data Register           */

+

+

+/*******************  Bit definition for SWPMI_OR register  ********************/

+#define SWPMI_OR_TBYP_Pos        (0U)

+#define SWPMI_OR_TBYP_Msk        (0x1UL << SWPMI_OR_TBYP_Pos)                  /*!< 0x00000001 */

+#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */

+#define SWPMI_OR_CLASS_Pos       (1U)

+#define SWPMI_OR_CLASS_Msk       (0x1UL << SWPMI_OR_CLASS_Pos)                 /*!< 0x00000002 */

+#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP CLASS selection */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            Window WATCHDOG                                 */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for WWDG_CR register  ********************/

+#define WWDG_CR_T_Pos           (0U)

+#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */

+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */

+#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */

+#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */

+#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */

+#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */

+#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */

+#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */

+#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */

+

+#define WWDG_CR_WDGA_Pos        (7U)

+#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */

+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */

+

+/*******************  Bit definition for WWDG_CFR register  *******************/

+#define WWDG_CFR_W_Pos          (0U)

+#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */

+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */

+#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */

+#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */

+#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */

+#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */

+#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */

+#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */

+#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */

+

+#define WWDG_CFR_EWI_Pos        (9U)

+#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */

+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */

+

+#define WWDG_CFR_WDGTB_Pos      (11U)

+#define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */

+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */

+#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000800 */

+#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00001000 */

+#define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00002000 */

+

+/*******************  Bit definition for WWDG_SR register  ********************/

+#define WWDG_SR_EWIF_Pos        (0U)

+#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */

+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                DBG                                         */

+/*                                                                            */

+/******************************************************************************/

+/*********************************  DEVICE ID  ********************************/

+#define STM32H7_DEV_ID           0x480UL

+

+/********************  Bit definition for DBGMCU_IDCODE register  *************/

+#define DBGMCU_IDCODE_DEV_ID_Pos          (0U)

+#define DBGMCU_IDCODE_DEV_ID_Msk          (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */

+#define DBGMCU_IDCODE_DEV_ID              DBGMCU_IDCODE_DEV_ID_Msk

+#define DBGMCU_IDCODE_REV_ID_Pos          (16U)

+#define DBGMCU_IDCODE_REV_ID_Msk          (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */

+#define DBGMCU_IDCODE_REV_ID              DBGMCU_IDCODE_REV_ID_Msk

+

+/********************  Bit definition for DBGMCU_CR register  *****************/

+#define DBGMCU_CR_DBG_SLEEPCD_Pos         (0U)

+#define DBGMCU_CR_DBG_SLEEPCD_Msk         (0x1UL << DBGMCU_CR_DBG_SLEEPCD_Pos) /*!< 0x00000001 */

+#define DBGMCU_CR_DBG_SLEEPCD             DBGMCU_CR_DBG_SLEEPCD_Msk

+#define DBGMCU_CR_DBG_STOPCD_Pos          (1U)

+#define DBGMCU_CR_DBG_STOPCD_Msk          (0x1UL << DBGMCU_CR_DBG_STOPCD_Pos)  /*!< 0x00000002 */

+#define DBGMCU_CR_DBG_STOPCD              DBGMCU_CR_DBG_STOPCD_Msk

+#define DBGMCU_CR_DBG_STANDBYCD_Pos       (2U)

+#define DBGMCU_CR_DBG_STANDBYCD_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYCD_Pos) /*!< 0x00000004 */

+#define DBGMCU_CR_DBG_STANDBYCD           DBGMCU_CR_DBG_STANDBYCD_Msk

+

+/* Legacy defines */

+#define DBGMCU_CR_DBG_SLEEPD1_Pos         DBGMCU_CR_DBG_SLEEPCD_Pos

+#define DBGMCU_CR_DBG_SLEEPD1_Msk         DBGMCU_CR_DBG_SLEEPCD_Msk

+#define DBGMCU_CR_DBG_SLEEPD1             DBGMCU_CR_DBG_SLEEPCD

+#define DBGMCU_CR_DBG_STOPD1_Pos          DBGMCU_CR_DBG_STOPCD_Pos

+#define DBGMCU_CR_DBG_STOPD1_Msk          DBGMCU_CR_DBG_STOPCD_Msk

+#define DBGMCU_CR_DBG_STOPD1              DBGMCU_CR_DBG_STOPCD

+#define DBGMCU_CR_DBG_STANDBYD1_Pos       DBGMCU_CR_DBG_STANDBYCD_Pos

+#define DBGMCU_CR_DBG_STANDBYD1_Msk       DBGMCU_CR_DBG_STANDBYCD_Msk

+#define DBGMCU_CR_DBG_STANDBYD1           DBGMCU_CR_DBG_STANDBYCD

+#define DBGMCU_CR_DBG_STOPSRD_Pos          (7U)

+#define DBGMCU_CR_DBG_STOPSRD_Msk          (0x1UL << DBGMCU_CR_DBG_STOPSRD_Pos)  /*!< 0x00000080 */

+#define DBGMCU_CR_DBG_STOPSRD              DBGMCU_CR_DBG_STOPSRD_Msk

+#define DBGMCU_CR_DBG_STANDBYSRD_Pos       (8U)

+#define DBGMCU_CR_DBG_STANDBYSRD_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYSRD_Pos) /*!< 0x00000100 */

+#define DBGMCU_CR_DBG_STANDBYSRD           DBGMCU_CR_DBG_STANDBYSRD_Msk

+

+/* Legacy defines */

+#define DBGMCU_CR_DBG_STOPD3_Pos          DBGMCU_CR_DBG_STOPSRD_Pos

+#define DBGMCU_CR_DBG_STOPD3_Msk          DBGMCU_CR_DBG_STOPSRD_Msk

+#define DBGMCU_CR_DBG_STOPD3              DBGMCU_CR_DBG_STOPSRD

+#define DBGMCU_CR_DBG_STANDBYD3_Pos       DBGMCU_CR_DBG_STANDBYSRD_Pos

+#define DBGMCU_CR_DBG_STANDBYD3_Msk       DBGMCU_CR_DBG_STANDBYSRD_Msk

+#define DBGMCU_CR_DBG_STANDBYD3           DBGMCU_CR_DBG_STANDBYSRD

+

+#define DBGMCU_CR_DBG_TRACECKEN_Pos       (20U)

+#define DBGMCU_CR_DBG_TRACECKEN_Msk       (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */

+#define DBGMCU_CR_DBG_TRACECKEN           DBGMCU_CR_DBG_TRACECKEN_Msk

+#define DBGMCU_CR_DBG_CKCDEN_Pos          (21U)

+#define DBGMCU_CR_DBG_CKCDEN_Msk          (0x1UL << DBGMCU_CR_DBG_CKCDEN_Pos)  /*!< 0x00200000 */

+#define DBGMCU_CR_DBG_CKCDEN              DBGMCU_CR_DBG_CKCDEN_Msk

+#define DBGMCU_CR_DBG_CKSRDEN_Pos          (22U)

+#define DBGMCU_CR_DBG_CKSRDEN_Msk          (0x1UL << DBGMCU_CR_DBG_CKSRDEN_Pos)  /*!< 0x00400000 */

+#define DBGMCU_CR_DBG_CKSRDEN              DBGMCU_CR_DBG_CKSRDEN_Msk

+

+/* Legacy defines */

+#define DBGMCU_CR_DBG_CKD1EN_Pos          DBGMCU_CR_DBG_CKCDEN_Pos

+#define DBGMCU_CR_DBG_CKD1EN_Msk          DBGMCU_CR_DBG_CKCDEN_Msk

+#define DBGMCU_CR_DBG_CKD1EN              DBGMCU_CR_DBG_CKCDEN

+#define DBGMCU_CR_DBG_CKD3EN_Pos          DBGMCU_CR_DBG_CKSRDEN_Pos

+#define DBGMCU_CR_DBG_CKD3EN_Msk          DBGMCU_CR_DBG_CKSRDEN_Msk

+#define DBGMCU_CR_DBG_CKD3EN              DBGMCU_CR_DBG_CKSRDEN

+

+#define DBGMCU_CR_DBG_TRGOEN_Pos          (28U)

+#define DBGMCU_CR_DBG_TRGOEN_Msk          (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)  /*!< 0x10000000 */

+#define DBGMCU_CR_DBG_TRGOEN              DBGMCU_CR_DBG_TRGOEN_Msk

+

+/********************  Bit definition for APB3FZ1 register  ************/

+#define DBGMCU_APB3FZ1_DBG_WWDG1_Pos      (6U)

+#define DBGMCU_APB3FZ1_DBG_WWDG1_Msk      (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB3FZ1_DBG_WWDG1          DBGMCU_APB3FZ1_DBG_WWDG1_Msk

+/********************  Bit definition for APB1LFZ1 register  ************/

+#define DBGMCU_APB1LFZ1_DBG_TIM2_Pos      (0U)

+#define DBGMCU_APB1LFZ1_DBG_TIM2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB1LFZ1_DBG_TIM2          DBGMCU_APB1LFZ1_DBG_TIM2_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM3_Pos      (1U)

+#define DBGMCU_APB1LFZ1_DBG_TIM3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB1LFZ1_DBG_TIM3          DBGMCU_APB1LFZ1_DBG_TIM3_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM4_Pos      (2U)

+#define DBGMCU_APB1LFZ1_DBG_TIM4_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */

+#define DBGMCU_APB1LFZ1_DBG_TIM4          DBGMCU_APB1LFZ1_DBG_TIM4_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM5_Pos      (3U)

+#define DBGMCU_APB1LFZ1_DBG_TIM5_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */

+#define DBGMCU_APB1LFZ1_DBG_TIM5          DBGMCU_APB1LFZ1_DBG_TIM5_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM6_Pos      (4U)

+#define DBGMCU_APB1LFZ1_DBG_TIM6_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */

+#define DBGMCU_APB1LFZ1_DBG_TIM6          DBGMCU_APB1LFZ1_DBG_TIM6_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM7_Pos      (5U)

+#define DBGMCU_APB1LFZ1_DBG_TIM7_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */

+#define DBGMCU_APB1LFZ1_DBG_TIM7          DBGMCU_APB1LFZ1_DBG_TIM7_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM12_Pos     (6U)

+#define DBGMCU_APB1LFZ1_DBG_TIM12_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB1LFZ1_DBG_TIM12         DBGMCU_APB1LFZ1_DBG_TIM12_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM13_Pos     (7U)

+#define DBGMCU_APB1LFZ1_DBG_TIM13_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB1LFZ1_DBG_TIM13         DBGMCU_APB1LFZ1_DBG_TIM13_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM14_Pos     (8U)

+#define DBGMCU_APB1LFZ1_DBG_TIM14_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */

+#define DBGMCU_APB1LFZ1_DBG_TIM14         DBGMCU_APB1LFZ1_DBG_TIM14_Msk

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos    (9U)

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1        DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C1_Pos      (21U)

+#define DBGMCU_APB1LFZ1_DBG_I2C1_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C1          DBGMCU_APB1LFZ1_DBG_I2C1_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C2_Pos      (22U)

+#define DBGMCU_APB1LFZ1_DBG_I2C2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C2          DBGMCU_APB1LFZ1_DBG_I2C2_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C3_Pos      (23U)

+#define DBGMCU_APB1LFZ1_DBG_I2C3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C3          DBGMCU_APB1LFZ1_DBG_I2C3_Msk

+

+/********************  Bit definition for APB2FZ1 register  ************/

+#define DBGMCU_APB2FZ1_DBG_TIM1_Pos       (0U)

+#define DBGMCU_APB2FZ1_DBG_TIM1_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB2FZ1_DBG_TIM1           DBGMCU_APB2FZ1_DBG_TIM1_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM8_Pos       (1U)

+#define DBGMCU_APB2FZ1_DBG_TIM8_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB2FZ1_DBG_TIM8           DBGMCU_APB2FZ1_DBG_TIM8_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM15_Pos      (16U)

+#define DBGMCU_APB2FZ1_DBG_TIM15_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB2FZ1_DBG_TIM15          DBGMCU_APB2FZ1_DBG_TIM15_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM16_Pos      (17U)

+#define DBGMCU_APB2FZ1_DBG_TIM16_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */

+#define DBGMCU_APB2FZ1_DBG_TIM16          DBGMCU_APB2FZ1_DBG_TIM16_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM17_Pos      (18U)

+#define DBGMCU_APB2FZ1_DBG_TIM17_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB2FZ1_DBG_TIM17          DBGMCU_APB2FZ1_DBG_TIM17_Msk

+/********************  Bit definition for APB4FZ1 register  ************/

+#define DBGMCU_APB4FZ1_DBG_I2C4_Pos       (7U)

+#define DBGMCU_APB4FZ1_DBG_I2C4_Msk       (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB4FZ1_DBG_I2C4           DBGMCU_APB4FZ1_DBG_I2C4_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos     (9U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM2         DBGMCU_APB4FZ1_DBG_LPTIM2_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos     (10U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM3         DBGMCU_APB4FZ1_DBG_LPTIM3_Msk

+#define DBGMCU_APB4FZ1_DBG_RTC_Pos        (16U)

+#define DBGMCU_APB4FZ1_DBG_RTC_Msk        (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB4FZ1_DBG_RTC            DBGMCU_APB4FZ1_DBG_RTC_Msk

+#define DBGMCU_APB4FZ1_DBG_IWDG1_Pos      (18U)

+#define DBGMCU_APB4FZ1_DBG_IWDG1_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB4FZ1_DBG_IWDG1          DBGMCU_APB4FZ1_DBG_IWDG1_Msk

+/******************************************************************************/

+/*                                                                            */

+/*                             RAM ECC monitoring                             */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for RAMECC_IER register  ******************/

+#define RAMECC_IER_GECCDEBWIE_Pos         (3U)

+#define RAMECC_IER_GECCDEBWIE_Msk         (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)  /*!< 0x00000008 */

+#define RAMECC_IER_GECCDEBWIE             RAMECC_IER_GECCDEBWIE_Msk             /*!< Global ECC double error on byte write (BW) interrupt enable */

+#define RAMECC_IER_GECCDEIE_Pos           (2U)

+#define RAMECC_IER_GECCDEIE_Msk           (0x1UL << RAMECC_IER_GECCDEIE_Pos)    /*!< 0x00000004 */

+#define RAMECC_IER_GECCDEIE               RAMECC_IER_GECCDEIE_Msk               /*!< Global ECC double error interrupt enable */

+#define RAMECC_IER_GECCSEIE_Pos           (1U)

+#define RAMECC_IER_GECCSEIE_Msk           (0x1UL << RAMECC_IER_GECCSEIE_Pos)    /*!< 0x00000002 */

+#define RAMECC_IER_GECCSEIE               RAMECC_IER_GECCSEIE_Msk               /*!< Global ECC single error interrupt enable */

+#define RAMECC_IER_GIE_Pos                (0U)

+#define RAMECC_IER_GIE_Msk                (0x1UL << RAMECC_IER_GIE_Pos)         /*!< 0x00000001 */

+#define RAMECC_IER_GIE                    RAMECC_IER_GIE_Msk                    /*!< Global interrupt enable */

+

+/*******************  Bit definition for RAMECC_CR register  ******************/

+#define RAMECC_CR_ECCELEN_Pos             (5U)

+#define RAMECC_CR_ECCELEN_Msk             (0x1UL << RAMECC_CR_ECCELEN_Pos)      /*!< 0x00000020 */

+#define RAMECC_CR_ECCELEN                 RAMECC_CR_ECCELEN_Msk                 /*!< ECC error latching enable */

+#define RAMECC_CR_ECCDEBWIE_Pos           (4U)

+#define RAMECC_CR_ECCDEBWIE_Msk           (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)    /*!< 0x00000010 */

+#define RAMECC_CR_ECCDEBWIE               RAMECC_CR_ECCDEBWIE_Msk               /*!< ECC double error on byte write (BW) interrupt enable */

+#define RAMECC_CR_ECCDEIE_Pos             (3U)

+#define RAMECC_CR_ECCDEIE_Msk             (0x1UL << RAMECC_CR_ECCDEIE_Pos)      /*!< 0x00000008 */

+#define RAMECC_CR_ECCDEIE                 RAMECC_CR_ECCDEIE_Msk                 /*!< ECC double error interrupt enable */

+#define RAMECC_CR_ECCSEIE_Pos             (2U)

+#define RAMECC_CR_ECCSEIE_Msk             (0x1UL << RAMECC_CR_ECCSEIE_Pos)      /*!< 0x00000004 */

+#define RAMECC_CR_ECCSEIE                 RAMECC_CR_ECCSEIE_Msk                 /*!< ECC single error interrupt enable */

+

+/*******************  Bit definition for RAMECC_SR register  ******************/

+#define RAMECC_SR_DEBWDF_Pos             (2U)

+#define RAMECC_SR_DEBWDF_Msk             (0x1UL << RAMECC_SR_DEBWDF_Pos)        /*!< 0x00000004 */

+#define RAMECC_SR_DEBWDF                 RAMECC_SR_DEBWDF_Msk                   /*!< ECC double error on byte write (BW) detected flag */

+#define RAMECC_SR_DEDF_Pos               (1U)

+#define RAMECC_SR_DEDF_Msk               (0x1UL << RAMECC_SR_DEDF_Pos)          /*!< 0x00000002 */

+#define RAMECC_SR_DEDF                   RAMECC_SR_DEDF_Msk                     /*!< ECC double error detected flag */

+#define RAMECC_SR_SEDCF_Pos              (0U)

+#define RAMECC_SR_SEDCF_Msk              (0x1UL << RAMECC_SR_SEDCF_Pos)         /*!< 0x00000001 */

+#define RAMECC_SR_SEDCF                  RAMECC_SR_SEDCF_Msk                    /*!< ECC single error detected and corrected flag */

+

+/******************  Bit definition for RAMECC_FAR register  ******************/

+#define RAMECC_FAR_FADD_Pos              (0U)

+#define RAMECC_FAR_FADD_Msk              (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)  /*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FADD                  RAMECC_FAR_FADD_Msk                    /*!< ECC error failing address */

+

+/******************  Bit definition for RAMECC_FDRL register  *****************/

+#define RAMECC_FAR_FDATAL_Pos            (0U)

+#define RAMECC_FAR_FDATAL_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FDATAL                RAMECC_FAR_FDATAL_Msk                  /*!< ECC error failing address */

+

+/******************  Bit definition for RAMECC_FDRH register  *****************/

+#define RAMECC_FAR_FDATAH_Pos            (0U)

+#define RAMECC_FAR_FDATAH_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FDATAH                RAMECC_FAR_FDATAH_Msk                  /* Failing data high (64-bit memory) */

+

+/*****************  Bit definition for RAMECC_FECR register  ******************/

+#define RAMECC_FECR_FEC_Pos              (0U)

+#define RAMECC_FECR_FEC_Msk              (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)  /*!< 0xFFFFFFFF */

+#define RAMECC_FECR_FEC                  RAMECC_FECR_FEC_Msk                    /*!< Failing error code */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                MDIOS                                        */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for MDIOS_CR register  *******************/

+#define MDIOS_CR_EN_Pos                (0U)

+#define MDIOS_CR_EN_Msk                (0x1UL << MDIOS_CR_EN_Pos)              /*!< 0x00000001 */

+#define MDIOS_CR_EN                    MDIOS_CR_EN_Msk                         /*!<  MDIOS slave peripheral enable */

+#define MDIOS_CR_WRIE_Pos              (1U)

+#define MDIOS_CR_WRIE_Msk              (0x1UL << MDIOS_CR_WRIE_Pos)            /*!< 0x00000002 */

+#define MDIOS_CR_WRIE                  MDIOS_CR_WRIE_Msk                       /*!<  MDIOS slave register write interrupt enable. */

+#define MDIOS_CR_RDIE_Pos              (2U)

+#define MDIOS_CR_RDIE_Msk              (0x1UL << MDIOS_CR_RDIE_Pos)            /*!< 0x00000004 */

+#define MDIOS_CR_RDIE                  MDIOS_CR_RDIE_Msk                       /*!<  MDIOS slave register read interrupt enable. */

+#define MDIOS_CR_EIE_Pos               (3U)

+#define MDIOS_CR_EIE_Msk               (0x1UL << MDIOS_CR_EIE_Pos)             /*!< 0x00000008 */

+#define MDIOS_CR_EIE                   MDIOS_CR_EIE_Msk                        /*!<  MDIOS slave register error interrupt enable. */

+#define MDIOS_CR_DPC_Pos               (7U)

+#define MDIOS_CR_DPC_Msk               (0x1UL << MDIOS_CR_DPC_Pos)             /*!< 0x00000080 */

+#define MDIOS_CR_DPC                   MDIOS_CR_DPC_Msk                        /*!<  MDIOS slave disable preamble check. */

+#define MDIOS_CR_PORT_ADDRESS_Pos      (8U)

+#define MDIOS_CR_PORT_ADDRESS_Msk      (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)   /*!< 0x00001F00 */

+#define MDIOS_CR_PORT_ADDRESS          MDIOS_CR_PORT_ADDRESS_Msk               /*!<  MDIOS slave port address mask. */

+#define MDIOS_CR_PORT_ADDRESS_0        (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000100 */

+#define MDIOS_CR_PORT_ADDRESS_1        (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000200 */

+#define MDIOS_CR_PORT_ADDRESS_2        (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000400 */

+#define MDIOS_CR_PORT_ADDRESS_3        (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000800 */

+#define MDIOS_CR_PORT_ADDRESS_4        (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001000 */

+

+/********************  Bit definition for MDIOS_SR register  *******************/

+#define MDIOS_SR_PERF_Pos              (0U)

+#define MDIOS_SR_PERF_Msk              (0x1UL << MDIOS_SR_PERF_Pos)            /*!< 0x00000001 */

+#define MDIOS_SR_PERF                  MDIOS_SR_PERF_Msk                       /*!<  MDIOS slave turnaround error flag*/

+#define MDIOS_SR_SERF_Pos              (1U)

+#define MDIOS_SR_SERF_Msk              (0x1UL << MDIOS_SR_SERF_Pos)            /*!< 0x00000002 */

+#define MDIOS_SR_SERF                  MDIOS_SR_SERF_Msk                       /*!<  MDIOS slave start error flag */

+#define MDIOS_SR_TERF_Pos              (2U)

+#define MDIOS_SR_TERF_Msk              (0x1UL << MDIOS_SR_TERF_Pos)            /*!< 0x00000004 */

+#define MDIOS_SR_TERF                  MDIOS_SR_TERF_Msk                       /*!<  MDIOS slave preamble error flag */

+

+/********************  Bit definition for MDIOS_CLRFR register  *******************/

+#define MDIOS_SR_CPERF_Pos             (0U)

+#define MDIOS_SR_CPERF_Msk             (0x1UL << MDIOS_SR_CPERF_Pos)           /*!< 0x00000001 */

+#define MDIOS_SR_CPERF                 MDIOS_SR_CPERF_Msk                      /*!<  MDIOS slave Clear the turnaround error flag */

+#define MDIOS_SR_CSERF_Pos             (1U)

+#define MDIOS_SR_CSERF_Msk             (0x1UL << MDIOS_SR_CSERF_Pos)           /*!< 0x00000002 */

+#define MDIOS_SR_CSERF                 MDIOS_SR_CSERF_Msk                      /*!<  MDIOS slave Clear the start error flag */

+#define MDIOS_SR_CTERF_Pos             (2U)

+#define MDIOS_SR_CTERF_Msk             (0x1UL << MDIOS_SR_CTERF_Pos)           /*!< 0x00000004 */

+#define MDIOS_SR_CTERF                 MDIOS_SR_CTERF_Msk                      /*!<  MDIOS slave Clear the preamble error flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                       USB_OTG                              */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/

+#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)

+#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */

+#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */

+#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)

+#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */

+#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */

+#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)

+#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */

+#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */

+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)

+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */

+#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */

+#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)

+#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */

+#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */

+#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)

+#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */

+#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */

+#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)

+#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */

+#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */

+#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)

+#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */

+#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */

+#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)

+#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */

+#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */

+#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)

+#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */

+#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */

+#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)

+#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */

+#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */

+#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)

+#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */

+#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */

+#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)

+#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */

+#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */

+#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)

+#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */

+#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */

+#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)

+#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */

+#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */

+#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)

+#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */

+#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */

+#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)

+#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */

+#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */

+#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)

+#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */

+#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */

+

+/********************  Bit definition forUSB_OTG_HCFG register  ********************/

+

+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)

+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */

+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */

+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)

+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */

+

+/********************  Bit definition forUSB_OTG_DCFG register  ********************/

+

+#define USB_OTG_DCFG_DSPD_Pos                    (0U)

+#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */

+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */

+#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */

+#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)

+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */

+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */

+

+#define USB_OTG_DCFG_DAD_Pos                     (4U)

+#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */

+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */

+#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */

+#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */

+#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */

+#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */

+#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */

+#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */

+#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */

+

+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)

+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */

+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */

+#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */

+#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */

+

+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)

+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */

+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */

+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */

+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */

+

+/********************  Bit definition forUSB_OTG_PCGCR register  ********************/

+#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)

+#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */

+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */

+#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)

+#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */

+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */

+#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)

+#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */

+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */

+

+/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/

+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)

+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */

+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */

+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)

+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */

+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */

+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)

+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */

+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */

+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)

+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */

+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */

+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)

+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */

+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */

+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)

+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */

+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */

+

+/********************  Bit definition forUSB_OTG_DCTL register  ********************/

+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)

+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */

+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */

+#define USB_OTG_DCTL_SDIS_Pos                    (1U)

+#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */

+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */

+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)

+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */

+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */

+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)

+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */

+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */

+

+#define USB_OTG_DCTL_TCTL_Pos                    (4U)

+#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */

+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */

+#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */

+#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */

+#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */

+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)

+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */

+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */

+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)

+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */

+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */

+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)

+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */

+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */

+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)

+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */

+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */

+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)

+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */

+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */

+

+/********************  Bit definition forUSB_OTG_HFIR register  ********************/

+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)

+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */

+

+/********************  Bit definition forUSB_OTG_HFNUM register  ********************/

+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)

+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */

+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)

+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */

+

+/********************  Bit definition forUSB_OTG_DSTS register  ********************/

+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)

+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */

+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */

+

+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)

+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */

+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */

+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */

+#define USB_OTG_DSTS_EERR_Pos                    (3U)

+#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */

+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */

+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)

+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */

+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */

+

+/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/

+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)

+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */

+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */

+

+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)

+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */

+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */

+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */

+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */

+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */

+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */

+#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */

+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)

+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */

+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */

+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)

+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */

+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */

+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)

+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */

+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */

+

+/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/

+

+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)

+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */

+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */

+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */

+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */

+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */

+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)

+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */

+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */

+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)

+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */

+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */

+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)

+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */

+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */

+

+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)

+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */

+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */

+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */

+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */

+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */

+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */

+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)

+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */

+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */

+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)

+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */

+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */

+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)

+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */

+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */

+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)

+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */

+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */

+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)

+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */

+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */

+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)

+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */

+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */

+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)

+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */

+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */

+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)

+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */

+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */

+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)

+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */

+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */

+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)

+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */

+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */

+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)

+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */

+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */

+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)

+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */

+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */

+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)

+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */

+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */

+

+/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/

+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)

+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */

+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */

+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)

+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */

+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */

+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)

+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */

+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */

+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)

+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */

+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */

+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)

+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */

+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */

+

+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)

+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */

+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */

+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */

+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */

+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */

+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */

+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */

+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)

+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */

+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */

+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)

+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */

+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */

+

+/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/

+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)

+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */

+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)

+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */

+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)

+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */

+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)

+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */

+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)

+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */

+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)

+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */

+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)

+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */

+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)

+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */

+

+/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/

+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)

+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */

+

+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)

+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */

+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */

+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */

+

+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)

+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */

+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */

+

+/********************  Bit definition forUSB_OTG_HAINT register  ********************/

+#define USB_OTG_HAINT_HAINT_Pos                  (0U)

+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */

+

+/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/

+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)

+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */

+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)

+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */

+#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)

+#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */

+#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask               */

+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)

+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */

+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)

+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */

+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)

+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */

+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)

+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */

+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)

+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */

+#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)

+#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */

+#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)

+#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask               */

+#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)

+#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask               */

+#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)

+#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                */

+

+/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/

+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)

+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */

+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */

+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)

+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */

+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */

+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)

+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */

+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */

+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)

+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */

+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */

+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)

+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */

+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */

+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)

+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */

+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */

+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)

+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */

+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */

+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)

+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */

+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */

+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)

+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */

+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */

+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)

+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */

+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */

+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)

+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */

+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */

+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)

+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */

+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */

+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)

+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */

+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */

+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)

+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */

+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */

+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)

+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */

+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */

+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)

+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */

+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */

+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)

+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */

+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */

+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)

+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */

+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */

+#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)

+#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */

+#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */

+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)

+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */

+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */

+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)

+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */

+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */

+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)

+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */

+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */

+#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)

+#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */

+#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */

+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)

+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */

+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */

+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)

+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */

+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */

+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)

+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */

+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */

+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)

+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */

+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */

+

+/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/

+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)

+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */

+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */

+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)

+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */

+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */

+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)

+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */

+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */

+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)

+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */

+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */

+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)

+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */

+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */

+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)

+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */

+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */

+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)

+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */

+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */

+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)

+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */

+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */

+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)

+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */

+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */

+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)

+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */

+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */

+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)

+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */

+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */

+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)

+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */

+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */

+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)

+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */

+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */

+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)

+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */

+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */

+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)

+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */

+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */

+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)

+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */

+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */

+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)

+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */

+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */

+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)

+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */

+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */

+#define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)

+#define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */

+#define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */

+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)

+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */

+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */

+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)

+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */

+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */

+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)

+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */

+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */

+#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)

+#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */

+#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */

+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)

+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */

+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */

+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)

+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */

+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */

+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)

+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */

+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */

+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)

+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */

+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */

+

+/********************  Bit definition forUSB_OTG_DAINT register  ********************/

+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)

+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */

+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)

+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */

+

+/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/

+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)

+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */

+

+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/

+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)

+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */

+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */

+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)

+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */

+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */

+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)

+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */

+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */

+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)

+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */

+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */

+

+/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/

+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)

+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */

+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)

+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */

+

+/********************  Bit definition for OTG register  ********************/

+

+#define USB_OTG_CHNUM_Pos                        (0U)

+#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)  /*!< 0x0000000F */

+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */

+#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */

+#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */

+#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */

+#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */

+#define USB_OTG_BCNT_Pos                         (4U)

+#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */

+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */

+

+#define USB_OTG_DPID_Pos                         (15U)

+#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)   /*!< 0x00018000 */

+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */

+#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */

+#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */

+

+#define USB_OTG_PKTSTS_Pos                       (17U)

+#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */

+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */

+#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */

+#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */

+#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */

+#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */

+

+#define USB_OTG_EPNUM_Pos                        (0U)

+#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)  /*!< 0x0000000F */

+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */

+#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */

+#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */

+#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */

+#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */

+

+#define USB_OTG_FRMNUM_Pos                       (21U)

+#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */

+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */

+#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */

+#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */

+#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */

+#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */

+

+/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/

+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)

+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/

+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)

+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */

+

+/********************  Bit definition for OTG register  ********************/

+#define USB_OTG_NPTXFSA_Pos                      (0U)

+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */

+#define USB_OTG_NPTXFD_Pos                       (16U)

+#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */

+#define USB_OTG_TX0FSA_Pos                       (0U)

+#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */

+#define USB_OTG_TX0FD_Pos                        (16U)

+#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */

+

+/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/

+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)

+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */

+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */

+

+/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/

+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)

+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */

+

+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)

+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */

+

+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)

+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/

+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)

+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */

+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */

+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)

+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */

+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */

+

+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)

+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */

+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */

+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */

+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)

+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */

+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */

+

+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)

+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */

+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */

+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)

+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */

+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */

+

+/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */

+

+/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/

+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)

+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */

+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */

+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)

+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */

+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */

+

+/********************  Bit definition forUSB_OTG_GCCFG register  ********************/

+#define USB_OTG_GCCFG_DCDET_Pos                  (0U)

+#define USB_OTG_GCCFG_DCDET_Msk                  (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */

+#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */

+#define USB_OTG_GCCFG_PDET_Pos                   (1U)

+#define USB_OTG_GCCFG_PDET_Msk                   (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */

+#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */

+#define USB_OTG_GCCFG_SDET_Pos                   (2U)

+#define USB_OTG_GCCFG_SDET_Msk                   (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */

+#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */

+#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)

+#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */

+#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */

+#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)

+#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */

+#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */

+#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)

+#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */

+#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */

+#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)

+#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */

+#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/

+#define USB_OTG_GCCFG_PDEN_Pos                   (19U)

+#define USB_OTG_GCCFG_PDEN_Msk                   (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */

+#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/

+#define USB_OTG_GCCFG_SDEN_Pos                   (20U)

+#define USB_OTG_GCCFG_SDEN_Msk                   (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */

+#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */

+#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)

+#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */

+#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */

+

+/********************  Bit definition forUSB_OTG_GPWRDN) register  ********************/

+#define USB_OTG_GPWRDN_ADPMEN_Pos                (0U)

+#define USB_OTG_GPWRDN_ADPMEN_Msk                (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */

+#define USB_OTG_GPWRDN_ADPMEN                    USB_OTG_GPWRDN_ADPMEN_Msk     /*!< ADP module enable */

+#define USB_OTG_GPWRDN_ADPIF_Pos                 (23U)

+#define USB_OTG_GPWRDN_ADPIF_Msk                 (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */

+#define USB_OTG_GPWRDN_ADPIF                     USB_OTG_GPWRDN_ADPIF_Msk      /*!< ADP Interrupt flag */

+

+/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/

+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)

+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */

+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)

+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */

+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */

+

+/********************  Bit definition forUSB_OTG_CID register  ********************/

+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)

+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */

+

+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/

+#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)

+#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */

+#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */

+#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)

+#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */

+#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */

+#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)

+#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */

+#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */

+#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)

+#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */

+#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */

+#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)

+#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */

+#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */

+#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)

+#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */

+#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */

+#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)

+#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */

+#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */

+#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)

+#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */

+#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */

+#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)

+#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */

+#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */

+#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)

+#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */

+#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */

+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)

+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */

+#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */

+#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)

+#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */

+#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */

+#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)

+#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */

+#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */

+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)

+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */

+#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */

+#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)

+#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */

+#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */

+

+/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/

+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)

+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */

+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)

+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */

+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)

+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */

+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)

+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */

+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)

+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */

+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)

+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */

+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)

+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */

+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)

+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */

+

+/********************  Bit definition forUSB_OTG_HPRT register  ********************/

+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)

+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */

+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */

+#define USB_OTG_HPRT_PCDET_Pos                   (1U)

+#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */

+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */

+#define USB_OTG_HPRT_PENA_Pos                    (2U)

+#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */

+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */

+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)

+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */

+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */

+#define USB_OTG_HPRT_POCA_Pos                    (4U)

+#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */

+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */

+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)

+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */

+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */

+#define USB_OTG_HPRT_PRES_Pos                    (6U)

+#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */

+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume   */

+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)

+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */

+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend  */

+#define USB_OTG_HPRT_PRST_Pos                    (8U)

+#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */

+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset    */

+

+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)

+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */

+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */

+#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */

+#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */

+#define USB_OTG_HPRT_PPWR_Pos                    (12U)

+#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */

+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */

+

+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)

+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */

+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */

+#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */

+#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */

+#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */

+#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */

+

+#define USB_OTG_HPRT_PSPD_Pos                    (17U)

+#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */

+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */

+#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */

+#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */

+

+/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/

+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)

+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)

+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)

+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */

+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)

+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */

+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)

+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */

+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)

+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */

+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)

+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)

+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)

+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)

+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */

+

+/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/

+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)

+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */

+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)

+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/

+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)

+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */

+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)

+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */

+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */

+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)

+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */

+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */

+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)

+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */

+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */

+

+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)

+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */

+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */

+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)

+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */

+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */

+

+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)

+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */

+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */

+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */

+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */

+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */

+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */

+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)

+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */

+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */

+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)

+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */

+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */

+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)

+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */

+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)

+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */

+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)

+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */

+

+/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/

+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)

+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */

+

+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)

+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */

+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */

+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */

+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */

+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */

+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */

+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)

+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */

+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */

+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)

+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */

+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */

+

+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)

+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */

+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */

+

+#define USB_OTG_HCCHAR_MC_Pos                    (20U)

+#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */

+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */

+#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */

+#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */

+

+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)

+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */

+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */

+#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */

+#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */

+#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */

+#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */

+#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */

+#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */

+#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */

+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)

+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */

+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)

+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */

+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)

+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */

+

+/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/

+

+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)

+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */

+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */

+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */

+

+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)

+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */

+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */

+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */

+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */

+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */

+

+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)

+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */

+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */

+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */

+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */

+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)

+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */

+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */

+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)

+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */

+

+/********************  Bit definition forUSB_OTG_HCINT register  ********************/

+#define USB_OTG_HCINT_XFRC_Pos                   (0U)

+#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */

+#define USB_OTG_HCINT_CHH_Pos                    (1U)

+#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */

+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)

+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */

+#define USB_OTG_HCINT_STALL_Pos                  (3U)

+#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */

+#define USB_OTG_HCINT_NAK_Pos                    (4U)

+#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */

+#define USB_OTG_HCINT_ACK_Pos                    (5U)

+#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */

+#define USB_OTG_HCINT_NYET_Pos                   (6U)

+#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */

+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */

+#define USB_OTG_HCINT_TXERR_Pos                  (7U)

+#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */

+#define USB_OTG_HCINT_BBERR_Pos                  (8U)

+#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */

+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)

+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */

+#define USB_OTG_HCINT_DTERR_Pos                  (10U)

+#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */

+

+/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/

+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)

+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */

+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)

+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */

+#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)

+#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */

+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)

+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */

+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)

+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */

+#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)

+#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */

+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)

+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */

+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)

+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */

+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */

+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)

+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */

+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)

+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */

+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)

+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */

+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */

+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)

+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */

+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */

+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)

+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */

+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */

+

+/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/

+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)

+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */

+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)

+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */

+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)

+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */

+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)

+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */

+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)

+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */

+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)

+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */

+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)

+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */

+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */

+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)

+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */

+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)

+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */

+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)

+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */

+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)

+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */

+

+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/

+

+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)

+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */

+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)

+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */

+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)

+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */

+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */

+/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/

+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)

+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */

+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)

+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */

+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)

+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */

+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)

+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */

+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */

+#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */

+#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/

+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)

+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */

+

+/********************  Bit definition forUSB_OTG_HCDMA register  ********************/

+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)

+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */

+

+/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/

+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)

+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */

+

+/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/

+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)

+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */

+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)

+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/

+

+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)

+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */

+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)

+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */

+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */

+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)

+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */

+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */

+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)

+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */

+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)

+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */

+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */

+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)

+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */

+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */

+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)

+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */

+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */

+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)

+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */

+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */

+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)

+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */

+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */

+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)

+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */

+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)

+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */

+

+/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/

+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)

+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */

+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)

+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */

+#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)

+#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */

+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)

+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */

+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)

+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */

+#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)

+#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< OUT Status Phase Received interrupt */

+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)

+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */

+#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)

+#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */

+#define USB_OTG_DOEPINT_BNA_Pos                  (9U)

+#define USB_OTG_DOEPINT_BNA_Msk                  (0x1UL << USB_OTG_DOEPINT_BNA_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPINT_BNA                      USB_OTG_DOEPINT_BNA_Msk   /*!< Buffer not available interrupt */

+#define USB_OTG_DOEPINT_BERR_Pos                 (12U)

+#define USB_OTG_DOEPINT_BERR_Msk                 (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPINT_BERR                      USB_OTG_DOEPINT_BERR_Msk   /*!< Babble error interrupt */

+#define USB_OTG_DOEPINT_NAK_Pos                  (13U)

+#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */

+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)

+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */

+#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)

+#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */

+#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */

+

+/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/

+

+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)

+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */

+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)

+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */

+

+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)

+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */

+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */

+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */

+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition for PCGCCTL register  ********************/

+#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)

+#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */

+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */

+#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)

+#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */

+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */

+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)

+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */

+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/** @addtogroup Exported_macros

+  * @{

+  */

+

+/******************************* ADC Instances ********************************/

+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \

+                                       ((INSTANCE) == ADC2))

+

+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)

+

+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)

+

+/******************************** COMP Instances ******************************/

+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \

+                                       ((INSTANCE) == COMP2))

+

+#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)

+/******************** COMP Instances with window mode capability **************/

+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)

+

+/******************************** DTS Instances ******************************/

+#define IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS)

+

+/******************************* CRC Instances ********************************/

+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

+

+/******************************* DAC Instances ********************************/

+#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1)|| \

+                                       ((INSTANCE) == DAC2))

+/******************************* DCMI Instances *******************************/

+#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)

+

+/******************************* DELAYBLOCK Instances *******************************/

+#define IS_DLYB_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DLYB_SDMMC1) || \

+                                         ((INSTANCE) == DLYB_SDMMC2) || \

+                                         ((INSTANCE) == DLYB_OCTOSPI1) || \

+                                         ((INSTANCE) == DLYB_OCTOSPI2) )

+/****************************** DFSDM Instances *******************************/

+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \

+                                         ((INSTANCE) == DFSDM1_Filter1) || \

+                                         ((INSTANCE) == DFSDM1_Filter2) || \

+                                         ((INSTANCE) == DFSDM1_Filter3) || \

+                                         ((INSTANCE) == DFSDM1_Filter4) || \

+                                         ((INSTANCE) == DFSDM1_Filter5) || \

+                                         ((INSTANCE) == DFSDM1_Filter6) || \

+                                         ((INSTANCE) == DFSDM1_Filter7) || \

+                                         ((INSTANCE) == DFSDM2_Filter0))

+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \

+                                                 ((INSTANCE) == DFSDM1_Channel1) || \

+                                                 ((INSTANCE) == DFSDM1_Channel2) || \

+                                                 ((INSTANCE) == DFSDM1_Channel3) || \

+                                                 ((INSTANCE) == DFSDM1_Channel4) || \

+                                                 ((INSTANCE) == DFSDM1_Channel5) || \

+                                                 ((INSTANCE) == DFSDM1_Channel6) || \

+                                                 ((INSTANCE) == DFSDM1_Channel7) || \

+                                                 ((INSTANCE) == DFSDM2_Channel0) || \

+                                                 ((INSTANCE) == DFSDM2_Channel1))

+/****************************** RAMECC Instances ******************************/

+#define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC_Monitor1)   || \

+                                                  ((INSTANCE) == RAMECC_Monitor2)   || \

+                                                  ((INSTANCE) == RAMECC_Monitor3))

+

+/******************************** DMA Instances *******************************/

+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \

+                                       ((INSTANCE) == DMA1_Stream1)   || \

+                                       ((INSTANCE) == DMA1_Stream2)   || \

+                                       ((INSTANCE) == DMA1_Stream3)   || \

+                                       ((INSTANCE) == DMA1_Stream4)   || \

+                                       ((INSTANCE) == DMA1_Stream5)   || \

+                                       ((INSTANCE) == DMA1_Stream6)   || \

+                                       ((INSTANCE) == DMA1_Stream7)   || \

+                                       ((INSTANCE) == DMA2_Stream0)   || \

+                                       ((INSTANCE) == DMA2_Stream1)   || \

+                                       ((INSTANCE) == DMA2_Stream2)   || \

+                                       ((INSTANCE) == DMA2_Stream3)   || \

+                                       ((INSTANCE) == DMA2_Stream4)   || \

+                                       ((INSTANCE) == DMA2_Stream5)   || \

+                                       ((INSTANCE) == DMA2_Stream6)   || \

+                                       ((INSTANCE) == DMA2_Stream7)   || \

+                                       ((INSTANCE) == BDMA1_Channel0) || \

+                                       ((INSTANCE) == BDMA1_Channel1) || \

+                                       ((INSTANCE) == BDMA1_Channel2) || \

+                                       ((INSTANCE) == BDMA1_Channel3) || \

+                                       ((INSTANCE) == BDMA1_Channel4) || \

+                                       ((INSTANCE) == BDMA1_Channel5) || \

+                                       ((INSTANCE) == BDMA1_Channel6) || \

+                                       ((INSTANCE) == BDMA1_Channel7) || \

+                                       ((INSTANCE) == BDMA2_Channel0) || \

+                                       ((INSTANCE) == BDMA2_Channel1) || \

+                                       ((INSTANCE) == BDMA2_Channel2) || \

+                                       ((INSTANCE) == BDMA2_Channel3) || \

+                                       ((INSTANCE) == BDMA2_Channel4) || \

+                                       ((INSTANCE) == BDMA2_Channel5) || \

+                                       ((INSTANCE) == BDMA2_Channel6) || \

+                                       ((INSTANCE) == BDMA2_Channel7))

+

+/****************************** BDMA CHANNEL Instances ***************************/

+#define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA1_Channel0) || \

+                                            ((INSTANCE) == BDMA1_Channel1) || \

+                                            ((INSTANCE) == BDMA1_Channel2) || \

+                                            ((INSTANCE) == BDMA1_Channel3) || \

+                                            ((INSTANCE) == BDMA1_Channel4) || \

+                                            ((INSTANCE) == BDMA1_Channel5) || \

+                                            ((INSTANCE) == BDMA1_Channel6) || \

+                                            ((INSTANCE) == BDMA1_Channel7) || \

+                                            ((INSTANCE) == BDMA2_Channel0) || \

+                                            ((INSTANCE) == BDMA2_Channel1) || \

+                                            ((INSTANCE) == BDMA2_Channel2) || \

+                                            ((INSTANCE) == BDMA2_Channel3) || \

+                                            ((INSTANCE) == BDMA2_Channel4) || \

+                                            ((INSTANCE) == BDMA2_Channel5) || \

+                                            ((INSTANCE) == BDMA2_Channel6) || \

+                                            ((INSTANCE) == BDMA2_Channel7))

+

+/****************************** DMA DMAMUX ALL Instances ***************************/

+#define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)    || \

+                                               ((INSTANCE) == DMA1_Stream1)    || \

+                                               ((INSTANCE) == DMA1_Stream2)    || \

+                                               ((INSTANCE) == DMA1_Stream3)    || \

+                                               ((INSTANCE) == DMA1_Stream4)    || \

+                                               ((INSTANCE) == DMA1_Stream5)    || \

+                                               ((INSTANCE) == DMA1_Stream6)    || \

+                                               ((INSTANCE) == DMA1_Stream7)    || \

+                                               ((INSTANCE) == DMA2_Stream0)    || \

+                                               ((INSTANCE) == DMA2_Stream1)    || \

+                                               ((INSTANCE) == DMA2_Stream2)    || \

+                                               ((INSTANCE) == DMA2_Stream3)    || \

+                                               ((INSTANCE) == DMA2_Stream4)    || \

+                                               ((INSTANCE) == DMA2_Stream5)    || \

+                                               ((INSTANCE) == DMA2_Stream6)    || \

+                                               ((INSTANCE) == DMA2_Stream7)    || \

+                                               ((INSTANCE) == BDMA2_Channel0)  || \

+                                               ((INSTANCE) == BDMA2_Channel1)  || \

+                                               ((INSTANCE) == BDMA2_Channel2)  || \

+                                               ((INSTANCE) == BDMA2_Channel3)  || \

+                                               ((INSTANCE) == BDMA2_Channel4)  || \

+                                               ((INSTANCE) == BDMA2_Channel5)  || \

+                                               ((INSTANCE) == BDMA2_Channel6)  || \

+                                               ((INSTANCE) == BDMA2_Channel7))

+

+/****************************** BDMA DMAMUX Instances ***************************/

+#define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == BDMA2_Channel0) || \

+                                                    ((INSTANCE) == BDMA2_Channel1) || \

+                                                    ((INSTANCE) == BDMA2_Channel2) || \

+                                                    ((INSTANCE) == BDMA2_Channel3) || \

+                                                    ((INSTANCE) == BDMA2_Channel4) || \

+                                                    ((INSTANCE) == BDMA2_Channel5) || \

+                                                    ((INSTANCE) == BDMA2_Channel6) || \

+                                                    ((INSTANCE) == BDMA2_Channel7))

+

+/****************************** DMA STREAM Instances ***************************/

+#define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \

+                                          ((INSTANCE) == DMA1_Stream1)   || \

+                                          ((INSTANCE) == DMA1_Stream2)   || \

+                                          ((INSTANCE) == DMA1_Stream3)   || \

+                                          ((INSTANCE) == DMA1_Stream4)   || \

+                                          ((INSTANCE) == DMA1_Stream5)   || \

+                                          ((INSTANCE) == DMA1_Stream6)   || \

+                                          ((INSTANCE) == DMA1_Stream7)   || \

+                                          ((INSTANCE) == DMA2_Stream0)   || \

+                                          ((INSTANCE) == DMA2_Stream1)   || \

+                                          ((INSTANCE) == DMA2_Stream2)   || \

+                                          ((INSTANCE) == DMA2_Stream3)   || \

+                                          ((INSTANCE) == DMA2_Stream4)   || \

+                                          ((INSTANCE) == DMA2_Stream5)   || \

+                                          ((INSTANCE) == DMA2_Stream6)   || \

+                                          ((INSTANCE) == DMA2_Stream7))

+

+/****************************** DMA DMAMUX Instances ***************************/

+#define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)   || \

+                                                  ((INSTANCE) == DMA1_Stream1)   || \

+                                                  ((INSTANCE) == DMA1_Stream2)   || \

+                                                  ((INSTANCE) == DMA1_Stream3)   || \

+                                                  ((INSTANCE) == DMA1_Stream4)   || \

+                                                  ((INSTANCE) == DMA1_Stream5)   || \

+                                                  ((INSTANCE) == DMA1_Stream6)   || \

+                                                  ((INSTANCE) == DMA1_Stream7)   || \

+                                                  ((INSTANCE) == DMA2_Stream0)   || \

+                                                  ((INSTANCE) == DMA2_Stream1)   || \

+                                                  ((INSTANCE) == DMA2_Stream2)   || \

+                                                  ((INSTANCE) == DMA2_Stream3)   || \

+                                                  ((INSTANCE) == DMA2_Stream4)   || \

+                                                  ((INSTANCE) == DMA2_Stream5)   || \

+                                                  ((INSTANCE) == DMA2_Stream6)   || \

+                                                  ((INSTANCE) == DMA2_Stream7))

+

+/******************************** DMA Request Generator Instances **************/

+#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator1) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator2) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator3) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator4) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator5) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator6) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator7) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator0) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator1) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator2) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator3) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator4) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator5) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator6) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator7))

+

+/******************************* DMA2D Instances *******************************/

+#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)

+

+/******************************* OTFDEC Instances ******************************/

+#define IS_OTFDEC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == OTFDEC1) || \

+                                              ((__INSTANCE__) == OTFDEC2))

+

+/****************************** PSSI Instance *********************************/

+#define IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI)

+

+/******************************** MDMA Request Generator Instances **************/

+#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0)  || \

+                                               ((INSTANCE) == MDMA_Channel1)  || \

+                                               ((INSTANCE) == MDMA_Channel2)  || \

+                                               ((INSTANCE) == MDMA_Channel3)  || \

+                                               ((INSTANCE) == MDMA_Channel4)  || \

+                                               ((INSTANCE) == MDMA_Channel5)  || \

+                                               ((INSTANCE) == MDMA_Channel6)  || \

+                                               ((INSTANCE) == MDMA_Channel7)  || \

+                                               ((INSTANCE) == MDMA_Channel8)  || \

+                                               ((INSTANCE) == MDMA_Channel9)  || \

+                                               ((INSTANCE) == MDMA_Channel10) || \

+                                               ((INSTANCE) == MDMA_Channel11) || \

+                                               ((INSTANCE) == MDMA_Channel12) || \

+                                               ((INSTANCE) == MDMA_Channel13) || \

+                                               ((INSTANCE) == MDMA_Channel14) || \

+                                               ((INSTANCE) == MDMA_Channel15))

+

+

+/******************************* FDCAN Instances ******************************/

+#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \

+                                             ((__INSTANCE__) == FDCAN2))

+

+#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)

+

+/******************************* GFXMMU Instances *******************************/

+#define IS_GFXMMU_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GFXMMU)

+

+/******************************* GPIO Instances *******************************/

+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \

+                                        ((INSTANCE) == GPIOB) || \

+                                        ((INSTANCE) == GPIOC) || \

+                                        ((INSTANCE) == GPIOD) || \

+                                        ((INSTANCE) == GPIOE) || \

+                                        ((INSTANCE) == GPIOF) || \

+                                        ((INSTANCE) == GPIOG) || \

+                                        ((INSTANCE) == GPIOH) || \

+                                        ((INSTANCE) == GPIOI) || \

+                                        ((INSTANCE) == GPIOJ) || \

+                                        ((INSTANCE) == GPIOK))

+

+/******************************* GPIO AF Instances ****************************/

+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)

+

+/**************************** GPIO Lock Instances *****************************/

+/* On H7, all GPIO Bank support the Lock mechanism */

+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)

+

+/******************************** HSEM Instances *******************************/

+#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)

+#define HSEM_CPU1_COREID         (0x00000001U) /* Semaphore Core CM7 ID */

+#define HSEM_CR_COREID_CPU1      (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)

+#define HSEM_CR_COREID_CURRENT   (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)

+

+#define HSEM_SEMID_MIN     (0U)       /* HSEM ID Min*/

+#define HSEM_SEMID_MAX     (15U)      /* HSEM ID Max */

+

+#define HSEM_PROCESSID_MIN (0U)       /* HSEM Process ID Min */

+#define HSEM_PROCESSID_MAX (255U)     /* HSEM Process ID Max */

+

+#define HSEM_CLEAR_KEY_MIN (0U)       /* HSEM clear Key Min value */

+#define HSEM_CLEAR_KEY_MAX (0xFFFFU)  /* HSEM clear Key Max value */

+

+/******************************** I2C Instances *******************************/

+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

+                                       ((INSTANCE) == I2C2) || \

+                                       ((INSTANCE) == I2C3) || \

+                                       ((INSTANCE) == I2C4))

+/************** I2C Instances : wakeup capability from stop modes *************/

+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)

+

+/****************************** SMBUS Instances *******************************/

+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

+                                         ((INSTANCE) == I2C2) || \

+                                         ((INSTANCE) == I2C3) || \

+                                         ((INSTANCE) == I2C4))

+/******************************** I2S Instances *******************************/

+#define IS_I2S_ALL_INSTANCE(INSTANCE)   (((INSTANCE) == SPI1) || \

+                                         ((INSTANCE) == SPI2) || \

+                                         ((INSTANCE) == SPI3) || \

+                                         ((INSTANCE) == SPI6))

+

+/****************************** LTDC Instances ********************************/

+#define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)

+

+/******************************* RNG Instances ********************************/

+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)

+

+/****************************** RTC Instances *********************************/

+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)

+

+/****************************** SDMMC Instances *********************************/

+#define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \

+                                           ((_INSTANCE_) == SDMMC2))

+

+/******************************** SMBUS Instances *****************************/

+#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)

+

+/******************************** SPI Instances *******************************/

+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \

+                                       ((INSTANCE) == SPI2) || \

+                                       ((INSTANCE) == SPI3) || \

+                                       ((INSTANCE) == SPI4) || \

+                                       ((INSTANCE) == SPI5) || \

+                                       ((INSTANCE) == SPI6))

+

+#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \

+                                           ((INSTANCE) == SPI2) || \

+                                           ((INSTANCE) == SPI3))

+

+/******************************** SWPMI Instances *****************************/

+#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)

+

+/****************** LPTIM Instances : All supported instances *****************/

+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \

+                                         ((INSTANCE) == LPTIM2) || \

+                                         ((INSTANCE) == LPTIM3))

+

+/****************** LPTIM Instances : supporting encoder interface **************/

+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \

+                                                           ((INSTANCE) == LPTIM2))

+

+/****************** TIM Instances : All supported instances *******************/

+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM6)   || \

+                                         ((INSTANCE) == TIM7)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM13)  || \

+                                         ((INSTANCE) == TIM14)  || \

+                                         ((INSTANCE) == TIM15)  || \

+                                         ((INSTANCE) == TIM16)  || \

+                                         ((INSTANCE) == TIM17))

+

+/************* TIM Instances : at least 1 capture/compare channel *************/

+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM13)  || \

+                                         ((INSTANCE) == TIM14)  || \

+                                         ((INSTANCE) == TIM15)  || \

+                                         ((INSTANCE) == TIM16)  || \

+                                         ((INSTANCE) == TIM17))

+

+/************ TIM Instances : at least 2 capture/compare channels *************/

+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM15))

+

+/************ TIM Instances : at least 3 capture/compare channels *************/

+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8))

+

+/************ TIM Instances : at least 4 capture/compare channels *************/

+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8))

+

+/************ TIM Instances : at least 5 capture/compare channels *************/

+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM8))

+/************ TIM Instances : at least 6 capture/compare channels *************/

+#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM8))

+

+/******************** TIM Instances : Advanced-control timers *****************/

+#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \

+                                                ((__INSTANCE__) == TIM8))

+

+/******************** TIM Instances : Advanced-control timers *****************/

+

+/******************* TIM Instances : Timer input XOR function *****************/

+#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : DMA requests generation (UDE) *************/

+#define IS_TIM_DMA_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM6)   || \

+                                           ((INSTANCE) == TIM7)   || \

+                                           ((INSTANCE) == TIM8)   || \

+                                           ((INSTANCE) == TIM15)  || \

+                                           ((INSTANCE) == TIM16)  || \

+                                           ((INSTANCE) == TIM17))

+

+/************ TIM Instances : DMA requests generation (CCxDE) *****************/

+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15)  || \

+                                            ((INSTANCE) == TIM16)  || \

+                                            ((INSTANCE) == TIM17))

+

+/************ TIM Instances : DMA requests generation (COMDE) *****************/

+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15))

+

+/******************** TIM Instances : DMA burst feature ***********************/

+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8))

+

+/*************** TIM Instances : external trigger reamp input available *******/

+#define IS_TIM_ETR_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : remapping capability **********************/

+#define IS_TIM_REMAP_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \

+                                          ((INSTANCE) == TIM2)  || \

+                                          ((INSTANCE) == TIM3)  || \

+                                          ((INSTANCE) == TIM5)  || \

+                                          ((INSTANCE) == TIM8)  || \

+                                          ((INSTANCE) == TIM16) || \

+                                          ((INSTANCE) == TIM17))

+

+/*************** TIM Instances : external trigger reamp input available *******/

+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                              ((INSTANCE) == TIM2)   || \

+                                              ((INSTANCE) == TIM3)   || \

+                                              ((INSTANCE) == TIM5)   || \

+                                              ((INSTANCE) == TIM8))

+

+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/

+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM6)   || \

+                                            ((INSTANCE) == TIM7)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15))

+

+/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/

+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM8)   || \

+                                           ((INSTANCE) == TIM12))

+

+/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/

+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM8))

+

+/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/

+#define IS_TIM_TISEL_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)   || \

+                                          ((INSTANCE) == TIM2)   || \

+                                          ((INSTANCE) == TIM3)   || \

+                                          ((INSTANCE) == TIM4)   || \

+                                          ((INSTANCE) == TIM5)   || \

+                                          ((INSTANCE) == TIM8)   || \

+                                          ((INSTANCE) == TIM15)  || \

+                                          ((INSTANCE) == TIM16)  || \

+                                          ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting commutation event *************/

+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \

+                                                     ((INSTANCE) == TIM8)    || \

+                                                     ((INSTANCE) == TIM15)   || \

+                                                     ((INSTANCE) == TIM16)   || \

+                                                     ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting encoder interface **************/

+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1)  || \

+                                                      ((__INSTANCE__) == TIM2)      || \

+                                                      ((__INSTANCE__) == TIM3)      || \

+                                                      ((__INSTANCE__) == TIM4)      || \

+                                                      ((__INSTANCE__) == TIM5)      || \

+                                                      ((__INSTANCE__) == TIM8))

+

+/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/

+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                                       ((INSTANCE) == TIM8))

+/******************* TIM Instances : output(s) available **********************/

+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \

+    ((((INSTANCE) == TIM1) &&                  \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4) ||          \

+      ((CHANNEL) == TIM_CHANNEL_5) ||          \

+      ((CHANNEL) == TIM_CHANNEL_6)))           \

+     ||                                        \

+     (((INSTANCE) == TIM2) &&                  \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM3) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1)||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM4) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM5) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM8) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4) ||          \

+      ((CHANNEL) == TIM_CHANNEL_5) ||          \

+      ((CHANNEL) == TIM_CHANNEL_6)))           \

+  ||                                           \

+     (((INSTANCE) == TIM12) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2)))           \

+  ||                                           \

+     (((INSTANCE) == TIM13) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM14) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM15) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+     ((CHANNEL) == TIM_CHANNEL_2)))            \

+  ||                                           \

+     (((INSTANCE) == TIM16) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM17) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1))))

+

+/****************** TIM Instances : supporting the break function *************/

+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\

+      (((INSTANCE) == TIM1)    || \

+      ((INSTANCE) == TIM8)     || \

+       ((INSTANCE) == TIM15)   || \

+       ((INSTANCE) == TIM16)   || \

+       ((INSTANCE) == TIM17))

+

+/************** TIM Instances : supporting Break source selection *************/

+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \

+                                               ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting complementary output(s) ********/

+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \

+   ((((INSTANCE) == TIM1) &&                    \

+     (((CHANNEL) == TIM_CHANNEL_1) ||           \

+      ((CHANNEL) == TIM_CHANNEL_2) ||           \

+      ((CHANNEL) == TIM_CHANNEL_3)))            \

+ ||                                             \

+      (((INSTANCE) == TIM8) &&                  \

+      (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||           \

+      ((CHANNEL) == TIM_CHANNEL_3)))            \

+    ||                                          \

+    (((INSTANCE) == TIM15) &&                   \

+      ((CHANNEL) == TIM_CHANNEL_1))             \

+    ||                                          \

+    (((INSTANCE) == TIM16) &&                   \

+     ((CHANNEL) == TIM_CHANNEL_1))              \

+    ||                                          \

+    (((INSTANCE) == TIM17) &&                   \

+     ((CHANNEL) == TIM_CHANNEL_1)))

+

+/****************** TIM Instances : supporting counting mode selection ********/

+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting repetition counter *************/

+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15)   || \

+   ((INSTANCE) == TIM16)   || \

+   ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting synchronization ****************/

+#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\

+    (((__INSTANCE__) == TIM1)    || \

+     ((__INSTANCE__) == TIM2)    || \

+     ((__INSTANCE__) == TIM3)    || \

+     ((__INSTANCE__) == TIM4)    || \

+     ((__INSTANCE__) == TIM5)    || \

+     ((__INSTANCE__) == TIM6)    || \

+     ((__INSTANCE__) == TIM8)    || \

+     ((__INSTANCE__) == TIM12)   || \

+     ((__INSTANCE__) == TIM15))

+

+/****************** TIM Instances : supporting clock division *****************/

+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15)   || \

+   ((INSTANCE) == TIM16)   || \

+   ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting external clock mode 1 for ETRF input */

+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting external clock mode 2 **********/

+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\

+ (((INSTANCE) == TIM1)     || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/

+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/

+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : supporting OCxREF clear *******************/

+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3))

+

+/****************** TIM Instances : TIM_32B_COUNTER ***************************/

+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM5))

+

+/****************** TIM Instances : TIM_BKIN2 ***************************/

+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting Hall sensor interface **********/

+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)  || \

+                                                             ((__INSTANCE__) == TIM2)  || \

+                                                             ((__INSTANCE__) == TIM3)  || \

+                                                             ((__INSTANCE__) == TIM4)  || \

+                                                             ((__INSTANCE__) == TIM5)  || \

+                                                             ((__INSTANCE__) == TIM15) || \

+                                                             ((__INSTANCE__) == TIM8))

+

+/******************** USART Instances : Synchronous mode **********************/

+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                     ((INSTANCE) == USART2) || \

+                                     ((INSTANCE) == USART3) || \

+                                     ((INSTANCE) == USART6) || \

+                                     ((INSTANCE) == USART10))

+

+/******************** USART Instances : SPI slave mode ************************/

+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                              ((INSTANCE) == USART2) || \

+                                              ((INSTANCE) == USART3) || \

+                                              ((INSTANCE) == USART6) || \

+                                              ((INSTANCE) == USART10))

+

+/******************** UART Instances : Asynchronous mode **********************/

+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                    ((INSTANCE) == USART2) || \

+                                    ((INSTANCE) == USART3) || \

+                                    ((INSTANCE) == UART4)  || \

+                                    ((INSTANCE) == UART5)  || \

+                                    ((INSTANCE) == USART6) || \

+                                    ((INSTANCE) == UART7)  || \

+                                    ((INSTANCE) == UART8)  || \

+                                    ((INSTANCE) == UART9)  || \

+                                    ((INSTANCE) == USART10))

+

+/******************** UART Instances : FIFO mode.******************************/

+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                         ((INSTANCE) == USART2) || \

+                                         ((INSTANCE) == USART3) || \

+                                         ((INSTANCE) == UART4)  || \

+                                         ((INSTANCE) == UART5)  || \

+                                         ((INSTANCE) == USART6) || \

+                                         ((INSTANCE) == UART7)  || \

+                                         ((INSTANCE) == UART8)  || \

+                                         ((INSTANCE) == UART9)  || \

+                                         ((INSTANCE) == USART10)|| \

+                                         ((INSTANCE) == LPUART1))

+

+/****************** UART Instances : Auto Baud Rate detection *****************/

+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                            ((INSTANCE) == USART2) || \

+                                                            ((INSTANCE) == USART3) || \

+                                                            ((INSTANCE) == UART4)  || \

+                                                            ((INSTANCE) == UART5)  || \

+                                                            ((INSTANCE) == USART6) || \

+                                                            ((INSTANCE) == UART7)  || \

+                                                            ((INSTANCE) == UART8)  || \

+                                                            ((INSTANCE) == UART9)  || \

+                                                            ((INSTANCE) == USART10))

+

+/*********************** UART Instances : Driver Enable ***********************/

+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                  ((INSTANCE) == USART2) || \

+                                                  ((INSTANCE) == USART3) || \

+                                                  ((INSTANCE) == UART4)  || \

+                                                  ((INSTANCE) == UART5)  || \

+                                                  ((INSTANCE) == USART6) || \

+                                                  ((INSTANCE) == UART7)  || \

+                                                  ((INSTANCE) == UART8)  || \

+                                                  ((INSTANCE) == UART9)  || \

+                                                  ((INSTANCE) == USART10)|| \

+                                                  ((INSTANCE) == LPUART1))

+

+/********************* UART Instances : Half-Duplex mode **********************/

+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                               ((INSTANCE) == USART2) || \

+                                               ((INSTANCE) == USART3) || \

+                                               ((INSTANCE) == UART4)  || \

+                                               ((INSTANCE) == UART5)  || \

+                                               ((INSTANCE) == USART6) || \

+                                               ((INSTANCE) == UART7)  || \

+                                               ((INSTANCE) == UART8)  || \

+                                               ((INSTANCE) == UART9)  || \

+                                               ((INSTANCE) == USART10)|| \

+                                               ((INSTANCE) == LPUART1))

+

+/******************* UART Instances : Hardware Flow control *******************/

+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                           ((INSTANCE) == USART2) || \

+                                           ((INSTANCE) == USART3) || \

+                                           ((INSTANCE) == UART4)  || \

+                                           ((INSTANCE) == UART5)  || \

+                                           ((INSTANCE) == USART6) || \

+                                           ((INSTANCE) == UART7)  || \

+                                           ((INSTANCE) == UART8)  || \

+                                           ((INSTANCE) == UART9)  || \

+                                           ((INSTANCE) == USART10)|| \

+                                           ((INSTANCE) == LPUART1))

+

+/************************* UART Instances : LIN mode **************************/

+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                        ((INSTANCE) == USART2) || \

+                                        ((INSTANCE) == USART3) || \

+                                        ((INSTANCE) == UART4)  || \

+                                        ((INSTANCE) == UART5)  || \

+                                        ((INSTANCE) == USART6) || \

+                                        ((INSTANCE) == UART7)  || \

+                                        ((INSTANCE) == UART8)  || \

+                                        ((INSTANCE) == UART9)  || \

+                                        ((INSTANCE) == USART10))

+

+/****************** UART Instances : Wake-up from Stop mode *******************/

+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                    ((INSTANCE) == USART2) || \

+                                                    ((INSTANCE) == USART3) || \

+                                                    ((INSTANCE) == UART4)  || \

+                                                    ((INSTANCE) == UART5)  || \

+                                                    ((INSTANCE) == USART6) || \

+                                                    ((INSTANCE) == UART7)  || \

+                                                    ((INSTANCE) == UART8)  || \

+                                                    ((INSTANCE) == UART9)  || \

+                                                    ((INSTANCE) == USART10)|| \

+                                                    ((INSTANCE) == LPUART1))

+

+/************************* UART Instances : IRDA mode *************************/

+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                    ((INSTANCE) == USART2) || \

+                                    ((INSTANCE) == USART3) || \

+                                    ((INSTANCE) == UART4)  || \

+                                    ((INSTANCE) == UART5)  || \

+                                    ((INSTANCE) == USART6) || \

+                                    ((INSTANCE) == UART7)  || \

+                                    ((INSTANCE) == UART8)  || \

+                                    ((INSTANCE) == UART9)  || \

+                                    ((INSTANCE) == USART10))

+

+/********************* USART Instances : Smard card mode **********************/

+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                         ((INSTANCE) == USART2) || \

+                                         ((INSTANCE) == USART3) || \

+                                         ((INSTANCE) == USART6) ||\

+                                         ((INSTANCE) == USART10))

+

+/****************************** LPUART Instance *******************************/

+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)

+

+/****************************** IWDG Instances ********************************/

+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG1)

+/****************************** USB Instances ********************************/

+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)

+

+/****************************** WWDG Instances ********************************/

+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG1)

+/****************************** MDIOS Instances ********************************/

+#define IS_MDIOS_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == MDIOS)

+

+/****************************** CEC Instances *********************************/

+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)

+

+/****************************** SAI Instances ********************************/

+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \

+                                       ((INSTANCE) == SAI1_Block_B) || \

+                                       ((INSTANCE) == SAI2_Block_A) || \

+                                       ((INSTANCE) == SAI2_Block_B))

+

+/****************************** SPDIFRX Instances ********************************/

+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)

+

+/****************************** OPAMP Instances *******************************/

+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \

+                                         ((INSTANCE) == OPAMP2))

+

+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)

+

+/*********************** USB OTG PCD Instances ********************************/

+#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS)

+

+/*********************** USB OTG HCD Instances ********************************/

+#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS)

+

+/******************************************************************************/

+/*  For a painless codes migration between the STM32H7xx device product       */

+/*  lines, or with STM32F7xx devices the aliases defined below are put        */

+/*   in place to overcome the differences in the interrupt handlers and IRQn  */

+/*   definitions. No need to update developed interrupt code when moving      */

+/*  across product lines within the same STM32H7 Family                       */

+/******************************************************************************/

+

+/* Aliases for __IRQn */

+#define  RNG_IRQn                       HASH_RNG_IRQn

+#define  TIM1_BRK_TIM9_IRQn             TIM1_BRK_IRQn

+#define  TIM1_UP_TIM10_IRQn             TIM1_UP_IRQn

+#define  TIM1_TRG_COM_TIM11_IRQn        TIM1_TRG_COM_IRQn

+#define  PVD_IRQn                       PVD_AVD_IRQn

+

+/* Aliases for BDMA __IRQn */

+#define  BDMA_Channel0_IRQn             BDMA2_Channel0_IRQn

+#define  BDMA_Channel1_IRQn             BDMA2_Channel1_IRQn

+#define  BDMA_Channel2_IRQn             BDMA2_Channel2_IRQn

+#define  BDMA_Channel3_IRQn             BDMA2_Channel3_IRQn

+#define  BDMA_Channel4_IRQn             BDMA2_Channel4_IRQn

+#define  BDMA_Channel5_IRQn             BDMA2_Channel5_IRQn

+#define  BDMA_Channel6_IRQn             BDMA2_Channel6_IRQn

+#define  BDMA_Channel7_IRQn             BDMA2_Channel7_IRQn

+

+/* Aliases for PWR __IRQn */

+#define  PVD_AVD_IRQn                   PVD_PVM_IRQn

+

+/* Aliases for DCMI/PSSI __IRQn */

+#define  DCMI_IRQn                      DCMI_PSSI_IRQn

+

+/* Aliases for __IRQHandler */

+#define   RNG_IRQHandler               HASH_RNG_IRQHandler

+#define TIM1_BRK_TIM9_IRQHandler       TIM1_BRK_IRQHandler

+#define TIM1_UP_TIM9_IRQHandler        TIM1_UP_IRQHandler

+#define TIM1_TRG_COM_TIM11_IRQHandler  TIM1_TRG_COM_IRQHandler

+#define PVD_IRQHandler                 PVD_AVD_IRQHandler

+

+

+/* Aliases for BDMA __IRQHandler */

+#define  BDMA_Channel0_IRQHandler      BDMA2_Channel0_IRQHandler

+#define  BDMA_Channel1_IRQHandler      BDMA2_Channel1_IRQHandler

+#define  BDMA_Channel2_IRQHandler      BDMA2_Channel2_IRQHandler

+#define  BDMA_Channel3_IRQHandler      BDMA2_Channel3_IRQHandler

+#define  BDMA_Channel4_IRQHandler      BDMA2_Channel4_IRQHandler

+#define  BDMA_Channel5_IRQHandler      BDMA2_Channel5_IRQHandler

+#define  BDMA_Channel6_IRQHandler      BDMA2_Channel6_IRQHandler

+#define  BDMA_Channel7_IRQHandler      BDMA2_Channel7_IRQHandler

+

+/* Aliases for PWR __IRQHandler */

+#define  PVD_AVD_IRQHandler            PVD_PVM_IRQHandler

+

+/* Aliases for DCMI/PSSI __IRQHandler */

+#define  DCMI_IRQHandler               DCMI_PSSI_IRQHandler

+

+/* Alias for BDMA defines */

+#define BDMA_BASE              BDMA2_BASE

+#define BDMA_Channel0_BASE     BDMA2_Channel0_BASE

+#define BDMA_Channel1_BASE     BDMA2_Channel1_BASE

+#define BDMA_Channel2_BASE     BDMA2_Channel2_BASE

+#define BDMA_Channel3_BASE     BDMA2_Channel3_BASE

+#define BDMA_Channel4_BASE     BDMA2_Channel4_BASE

+#define BDMA_Channel5_BASE     BDMA2_Channel5_BASE

+#define BDMA_Channel6_BASE     BDMA2_Channel6_BASE

+#define BDMA_Channel7_BASE     BDMA2_Channel7_BASE

+

+#define BDMA                   BDMA2

+#define BDMA_Channel0          BDMA2_Channel0

+#define BDMA_Channel1          BDMA2_Channel1

+#define BDMA_Channel2          BDMA2_Channel2

+#define BDMA_Channel3          BDMA2_Channel3

+#define BDMA_Channel4          BDMA2_Channel4

+#define BDMA_Channel5          BDMA2_Channel5

+#define BDMA_Channel6          BDMA2_Channel6

+#define BDMA_Channel7          BDMA2_Channel7

+

+/* Alias for PWR defines */

+#define PWR_CPUCR_RUN_D3       PWR_CPUCR_RUN_SRD

+#define PWR_CPUCR_PDDS_D3      PWR_CPUCR_PDDS_SRD

+#define PWR_CPUCR_PDDS_D1      PWR_CPUCR_RETDS_CD

+

+#define PWR_D3CR_VOS           PWR_SRDCR_VOS

+

+#define PWR_D3CR_VOS_0         PWR_SRDCR_VOS_0

+#define PWR_D3CR_VOS_1         PWR_SRDCR_VOS_1

+#define PWR_D3CR_VOSRDY        PWR_SRDCR_VOSRDY

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif /* __cplusplus */

+

+#endif /* STM32H7B3xx_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7b3xxq.h b/bsps/arm/stm32h7/include/stm32h7b3xxq.h
new file mode 100644
index 0000000000..1f444c2454
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7b3xxq.h
@@ -0,0 +1,22907 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7b3xxq.h

+  * @author  MCD Application Team

+  * @brief   CMSIS STM32H7B3xxQ Device Peripheral Access Layer Header File.

+  *

+  *          This file contains:

+  *           - Data structures and the address mapping for all peripherals

+  *           - Peripheral's registers declarations and bits definition

+  *           - Macros to access peripheral's registers hardware

+  *

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/** @addtogroup CMSIS_Device

+  * @{

+  */

+

+/** @addtogroup stm32h7b3xxq

+  * @{

+  */

+

+#ifndef STM32H7B3xxQ_H

+#define STM32H7B3xxQ_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif /* __cplusplus */

+

+/** @addtogroup Peripheral_interrupt_number_definition

+  * @{

+  */

+

+/**

+ * @brief STM32H7XX Interrupt Number Definition, according to the selected device

+ *        in @ref Library_configuration_section

+ */

+typedef enum

+{

+/******  Cortex-M Processor Exceptions Numbers *****************************************************************/

+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */

+  HardFault_IRQn              = -13,    /*!< 4 Cortex-M Memory Management Interrupt                            */

+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M Memory Management Interrupt                            */

+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M Bus Fault Interrupt                                    */

+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M Usage Fault Interrupt                                  */

+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M SV Call Interrupt                                     */

+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M Debug Monitor Interrupt                               */

+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M Pend SV Interrupt                                     */

+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M System Tick Interrupt                                 */

+/******  STM32 specific Interrupt Numbers **********************************************************************/

+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it)                   */

+  PVD_PVM_IRQn                = 1,      /*!< PVD/PVM through EXTI Line detection Interrupt                     */

+  RTC_TAMP_STAMP_CSS_LSE_IRQn = 2,      /*!< Tamper, TimeStamp, CSS and LSE interrupts through the EXTI line   */

+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */

+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */

+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */

+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */

+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */

+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */

+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */

+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */

+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */

+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */

+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */

+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */

+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */

+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */

+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */

+  ADC_IRQn                    = 18,     /*!< ADC1 and  ADC2 global Interrupts                                  */

+  FDCAN1_IT0_IRQn             = 19,     /*!< FDCAN1 Interrupt line 0                                           */

+  FDCAN2_IT0_IRQn             = 20,     /*!< FDCAN2 Interrupt line 0                                           */

+  FDCAN1_IT1_IRQn             = 21,     /*!< FDCAN1 Interrupt line 1                                           */

+  FDCAN2_IT1_IRQn             = 22,     /*!< FDCAN2 Interrupt line 1                                           */

+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */

+  TIM1_BRK_IRQn               = 24,     /*!< TIM1 Break Interrupt                                              */

+  TIM1_UP_IRQn                = 25,     /*!< TIM1 Update Interrupt                                             */

+  TIM1_TRG_COM_IRQn           = 26,     /*!< TIM1 Trigger and Commutation Interrupt                            */

+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */

+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */

+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */

+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */

+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */

+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */

+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */

+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */

+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */

+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */

+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */

+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */

+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */

+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */

+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */

+  DFSDM2_IRQn                 = 42,     /*!< DFSDM2 global Interrupt                                           */

+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */

+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */

+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */

+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */

+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */

+  FMC_IRQn                    = 48,     /*!< FMC global Interrupt                                              */

+  SDMMC1_IRQn                 = 49,     /*!< SDMMC1 global Interrupt                                           */

+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */

+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */

+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */

+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */

+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */

+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */

+  DMA2_Stream0_IRQn           = 56,     /*!<   DMA2 Stream 0 global Interrupt                                  */

+  DMA2_Stream1_IRQn           = 57,     /*!<   DMA2 Stream 1 global Interrupt                                  */

+  DMA2_Stream2_IRQn           = 58,     /*!<   DMA2 Stream 2 global Interrupt                                  */

+  DMA2_Stream3_IRQn           = 59,     /*!<   DMA2 Stream 3 global Interrupt                                  */

+  DMA2_Stream4_IRQn           = 60,     /*!<   DMA2 Stream 4 global Interrupt                                  */

+  FDCAN_CAL_IRQn              = 63,     /*!< FDCAN Calibration unit Interrupt                                  */

+  DFSDM1_FLT4_IRQn            = 64,     /*!< DFSDM Filter4 Interrupt                                           */

+  DFSDM1_FLT5_IRQn            = 65,     /*!< DFSDM Filter5 Interrupt                                           */

+  DFSDM1_FLT6_IRQn            = 66,     /*!< DFSDM Filter6 Interrupt                                           */

+  DFSDM1_FLT7_IRQn            = 67,     /*!< DFSDM Filter7 Interrupt                                           */

+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */

+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */

+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */

+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */

+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */

+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */

+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */

+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */

+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */

+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */

+  DCMI_PSSI_IRQn              = 78,     /*!< DCMI and PSSI global interrupt                                    */

+  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */

+  HASH_RNG_IRQn               = 80,     /*!< HASH and RNG global interrupt                                     */

+  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */

+  UART7_IRQn                  = 82,     /*!< UART7 global interrupt                                            */

+  UART8_IRQn                  = 83,     /*!< UART8 global interrupt                                            */

+  SPI4_IRQn                   = 84,     /*!< SPI4 global Interrupt                                             */

+  SPI5_IRQn                   = 85,     /*!< SPI5 global Interrupt                                             */

+  SPI6_IRQn                   = 86,     /*!< SPI6 global Interrupt                                             */

+  SAI1_IRQn                   = 87,     /*!< SAI1 global Interrupt                                             */

+  LTDC_IRQn                   = 88,     /*!< LTDC global Interrupt                                             */

+  LTDC_ER_IRQn                = 89,     /*!< LTDC Error global Interrupt                                       */

+  DMA2D_IRQn                  = 90,     /*!< DMA2D global Interrupt                                            */

+  SAI2_IRQn                   = 91,     /*!< SAI2 global Interrupt                                             */

+  OCTOSPI1_IRQn               = 92,     /*!< OCTOSPI1 global interrupt                                         */

+  LPTIM1_IRQn                 = 93,     /*!< LP TIM1 interrupt                                                 */

+  CEC_IRQn                    = 94,     /*!< HDMI-CEC global Interrupt                                         */

+  I2C4_EV_IRQn                = 95,     /*!< I2C4 Event Interrupt                                              */

+  I2C4_ER_IRQn                = 96,     /*!< I2C4 Error Interrupt                                              */

+  SPDIF_RX_IRQn               = 97,     /*!< SPDIF-RX global Interrupt                                         */

+  DMAMUX1_OVR_IRQn            = 102,    /*!<DMAMUX1 Overrun interrupt                                          */

+  DFSDM1_FLT0_IRQn            = 110,    /*!<DFSDM Filter1 Interrupt                                            */

+  DFSDM1_FLT1_IRQn            = 111,    /*!<DFSDM Filter2 Interrupt                                            */

+  DFSDM1_FLT2_IRQn            = 112,    /*!<DFSDM Filter3 Interrupt                                            */

+  DFSDM1_FLT3_IRQn            = 113,    /*!<DFSDM Filter4 Interrupt                                            */

+  SWPMI1_IRQn                 = 115,    /*!< Serial Wire Interface 1 global interrupt                          */

+  TIM15_IRQn                  = 116,    /*!< TIM15 global Interrupt                                            */

+  TIM16_IRQn                  = 117,    /*!< TIM16 global Interrupt                                            */

+  TIM17_IRQn                  = 118,    /*!< TIM17 global Interrupt                                            */

+  MDIOS_WKUP_IRQn             = 119,    /*!< MDIOS Wakeup  Interrupt                                           */

+  MDIOS_IRQn                  = 120,    /*!< MDIOS global Interrupt                                            */

+  JPEG_IRQn                   = 121,    /*!< JPEG global Interrupt                                             */

+  MDMA_IRQn                   = 122,    /*!< MDMA global Interrupt                                             */

+  SDMMC2_IRQn                 = 124,    /*!< SDMMC2 global Interrupt                                           */

+  HSEM1_IRQn                  = 125,    /*!< HSEM1 global Interrupt                                            */

+  DAC2_IRQn                   = 127,    /*!< DAC2 global Interrupt                                             */

+  DMAMUX2_OVR_IRQn            = 128,    /*!<DMAMUX2 Overrun interrupt                                          */

+  BDMA2_Channel0_IRQn         = 129,    /*!< BDMA2 Channel 0 global Interrupt                                  */

+  BDMA2_Channel1_IRQn         = 130,    /*!< BDMA2 Channel 1 global Interrupt                                  */

+  BDMA2_Channel2_IRQn         = 131,    /*!< BDMA2 Channel 2 global Interrupt                                  */

+  BDMA2_Channel3_IRQn         = 132,    /*!< BDMA2 Channel 3 global Interrupt                                  */

+  BDMA2_Channel4_IRQn         = 133,    /*!< BDMA2 Channel 4 global Interrupt                                  */

+  BDMA2_Channel5_IRQn         = 134,    /*!< BDMA2 Channel 5 global Interrupt                                  */

+  BDMA2_Channel6_IRQn         = 135,    /*!< BDMA2 Channel 6 global Interrupt                                  */

+  BDMA2_Channel7_IRQn         = 136,    /*!< BDMA2 Channel 7 global Interrupt                                  */

+  COMP_IRQn                   = 137 ,   /*!< COMP global Interrupt                                             */

+  LPTIM2_IRQn                 = 138,    /*!< LP TIM2 global interrupt                                          */

+  LPTIM3_IRQn                 = 139,    /*!< LP TIM3 global interrupt                                          */

+  UART9_IRQn                  = 140,    /*!< UART9 global interrupt                                            */

+  USART10_IRQn                = 141,    /*!< USART10 global interrupt                                          */

+  LPUART1_IRQn                = 142,    /*!< LP UART1 interrupt                                                */

+  WWDG_RST_IRQn               = 143,    /*!<Window Watchdog Event interrupt                                    */

+  CRS_IRQn                    = 144,    /*!< Clock Recovery Global Interrupt                                   */

+  ECC_IRQn                    = 145,    /*!< ECC diagnostic Global Interrupt                                   */

+  DTS_IRQn                    = 147,    /*!< Digital Temperature Sensor Global Interrupt                       */

+  WAKEUP_PIN_IRQn             = 149,    /*!< Interrupt for all 6 wake-up pins                                  */

+  OCTOSPI2_IRQn               = 150,    /*!< OctoSPI2 global interrupt                                         */

+  OTFDEC1_IRQn                = 151,    /*!< OTFDEC1 global interrupt                                          */

+  OTFDEC2_IRQn                = 152,    /*!< OTFDEC2 global interrupt                                          */

+  GFXMMU_IRQn                 = 153,    /*!< GFXMMU global interrupt                                           */

+  BDMA1_IRQn                  = 154,    /*!< BDMA1 for DFSM global interrupt                                   */

+} IRQn_Type;

+

+/**

+  * @}

+  */

+

+/** @addtogroup Configuration_section_for_CMSIS

+  * @{

+  */

+

+#define SMPS       /*!< Switched mode power supply feature */

+

+

+

+/**

+  * @brief Configuration of the Cortex-M7 Processor and Core Peripherals

+   */

+#define __CM7_REV               0x0100U   /*!< Cortex-M7 revision r1p0                       */

+#define __MPU_PRESENT             1       /*!< CM7 provides an MPU                           */

+#define __NVIC_PRIO_BITS          4       /*!< CM7 uses 4 Bits for the Priority Levels       */

+#define __Vendor_SysTickConfig    0       /*!< Set to 1 if different SysTick Config is used  */

+#define __FPU_PRESENT             1       /*!< FPU present                                   */

+#define __ICACHE_PRESENT          1       /*!< CM7 instruction cache present                 */

+#define __DCACHE_PRESENT          1       /*!< CM7 data cache present                        */

+#include "core_cm7.h"                     /*!< Cortex-M7 processor and core peripherals      */

+

+/**

+  * @}

+  */

+

+

+

+

+#include "system_stm32h7xx.h"

+#include <stdint.h>

+

+/** @addtogroup Peripheral_registers_structures

+  * @{

+  */

+

+/**

+  * @brief Analog to Digital Converter

+  */

+

+typedef struct

+{

+  __IO uint32_t ISR;              /*!< ADC Interrupt and Status Register,                          Address offset: 0x00 */

+  __IO uint32_t IER;              /*!< ADC Interrupt Enable Register,                              Address offset: 0x04 */

+  __IO uint32_t CR;               /*!< ADC control register,                                       Address offset: 0x08 */

+  __IO uint32_t CFGR;             /*!< ADC Configuration register,                                 Address offset: 0x0C */

+  __IO uint32_t CFGR2;            /*!< ADC Configuration register 2,                               Address offset: 0x10 */

+  __IO uint32_t SMPR1;            /*!< ADC sample time register 1,                                 Address offset: 0x14 */

+  __IO uint32_t SMPR2;            /*!< ADC sample time register 2,                                 Address offset: 0x18 */

+  __IO uint32_t PCSEL;            /*!< ADC pre-channel selection,                                  Address offset: 0x1C */

+  __IO uint32_t LTR1;             /*!< ADC watchdog Lower threshold register 1,                    Address offset: 0x20 */

+  __IO uint32_t HTR1;             /*!< ADC watchdog higher threshold register 1,                   Address offset: 0x24 */

+  uint32_t      RESERVED1;        /*!< Reserved, 0x028                                                                  */

+  uint32_t      RESERVED2;        /*!< Reserved, 0x02C                                                                  */

+  __IO uint32_t SQR1;             /*!< ADC regular sequence register 1,                            Address offset: 0x30 */

+  __IO uint32_t SQR2;             /*!< ADC regular sequence register 2,                            Address offset: 0x34 */

+  __IO uint32_t SQR3;             /*!< ADC regular sequence register 3,                            Address offset: 0x38 */

+  __IO uint32_t SQR4;             /*!< ADC regular sequence register 4,                            Address offset: 0x3C */

+  __IO uint32_t DR;               /*!< ADC regular data register,                                  Address offset: 0x40 */

+  uint32_t      RESERVED3;        /*!< Reserved, 0x044                                                                  */

+  uint32_t      RESERVED4;        /*!< Reserved, 0x048                                                                  */

+  __IO uint32_t JSQR;             /*!< ADC injected sequence register,                             Address offset: 0x4C */

+  uint32_t      RESERVED5[4];     /*!< Reserved, 0x050 - 0x05C                                                          */

+  __IO uint32_t OFR1;             /*!< ADC offset register 1,                                      Address offset: 0x60 */

+  __IO uint32_t OFR2;             /*!< ADC offset register 2,                                      Address offset: 0x64 */

+  __IO uint32_t OFR3;             /*!< ADC offset register 3,                                      Address offset: 0x68 */

+  __IO uint32_t OFR4;             /*!< ADC offset register 4,                                      Address offset: 0x6C */

+  uint32_t      RESERVED6[4];     /*!< Reserved, 0x070 - 0x07C                                                          */

+  __IO uint32_t JDR1;             /*!< ADC injected data register 1,                               Address offset: 0x80 */

+  __IO uint32_t JDR2;             /*!< ADC injected data register 2,                               Address offset: 0x84 */

+  __IO uint32_t JDR3;             /*!< ADC injected data register 3,                               Address offset: 0x88 */

+  __IO uint32_t JDR4;             /*!< ADC injected data register 4,                               Address offset: 0x8C */

+  uint32_t      RESERVED7[4];     /*!< Reserved, 0x090 - 0x09C                                                          */

+  __IO uint32_t AWD2CR;           /*!< ADC  Analog Watchdog 2 Configuration Register,              Address offset: 0xA0 */

+  __IO uint32_t AWD3CR;           /*!< ADC  Analog Watchdog 3 Configuration Register,              Address offset: 0xA4 */

+  uint32_t      RESERVED8;        /*!< Reserved, 0x0A8                                                                  */

+  uint32_t      RESERVED9;        /*!< Reserved, 0x0AC                                                                  */

+  __IO uint32_t LTR2;             /*!< ADC watchdog Lower threshold register 2,                    Address offset: 0xB0 */

+  __IO uint32_t HTR2;             /*!< ADC watchdog Higher threshold register 2,                   Address offset: 0xB4 */

+  __IO uint32_t LTR3;             /*!< ADC watchdog Lower threshold register 3,                    Address offset: 0xB8 */

+  __IO uint32_t HTR3;             /*!< ADC watchdog Higher threshold register 3,                   Address offset: 0xBC */

+  __IO uint32_t DIFSEL;           /*!< ADC  Differential Mode Selection Register,                  Address offset: 0xC0 */

+  __IO uint32_t CALFACT;          /*!< ADC  Calibration Factors,                                   Address offset: 0xC4 */

+  __IO uint32_t CALFACT2;         /*!< ADC  Linearity Calibration Factors,                         Address offset: 0xC8 */

+} ADC_TypeDef;

+

+

+typedef struct

+{

+__IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */

+uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */

+__IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */

+__IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */

+__IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */

+

+} ADC_Common_TypeDef;

+

+

+/**

+  * @brief VREFBUF

+  */

+

+typedef struct

+{

+  __IO uint32_t CSR;         /*!< VREFBUF control and status register,         Address offset: 0x00 */

+  __IO uint32_t CCR;         /*!< VREFBUF calibration and control register,    Address offset: 0x04 */

+} VREFBUF_TypeDef;

+

+

+/**

+  * @brief FD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t CREL;         /*!< FDCAN Core Release register,                                     Address offset: 0x000 */

+  __IO uint32_t ENDN;         /*!< FDCAN Endian register,                                           Address offset: 0x004 */

+  __IO uint32_t RESERVED1;    /*!< Reserved,                                                                        0x008 */

+  __IO uint32_t DBTP;         /*!< FDCAN Data Bit Timing & Prescaler register,                      Address offset: 0x00C */

+  __IO uint32_t TEST;         /*!< FDCAN Test register,                                             Address offset: 0x010 */

+  __IO uint32_t RWD;          /*!< FDCAN RAM Watchdog register,                                     Address offset: 0x014 */

+  __IO uint32_t CCCR;         /*!< FDCAN CC Control register,                                       Address offset: 0x018 */

+  __IO uint32_t NBTP;         /*!< FDCAN Nominal Bit Timing & Prescaler register,                   Address offset: 0x01C */

+  __IO uint32_t TSCC;         /*!< FDCAN Timestamp Counter Configuration register,                  Address offset: 0x020 */

+  __IO uint32_t TSCV;         /*!< FDCAN Timestamp Counter Value register,                          Address offset: 0x024 */

+  __IO uint32_t TOCC;         /*!< FDCAN Timeout Counter Configuration register,                    Address offset: 0x028 */

+  __IO uint32_t TOCV;         /*!< FDCAN Timeout Counter Value register,                            Address offset: 0x02C */

+  __IO uint32_t RESERVED2[4]; /*!< Reserved,                                                                0x030 - 0x03C */

+  __IO uint32_t ECR;          /*!< FDCAN Error Counter register,                                    Address offset: 0x040 */

+  __IO uint32_t PSR;          /*!< FDCAN Protocol Status register,                                  Address offset: 0x044 */

+  __IO uint32_t TDCR;         /*!< FDCAN Transmitter Delay Compensation register,                   Address offset: 0x048 */

+  __IO uint32_t RESERVED3;    /*!< Reserved,                                                                        0x04C */

+  __IO uint32_t IR;           /*!< FDCAN Interrupt register,                                        Address offset: 0x050 */

+  __IO uint32_t IE;           /*!< FDCAN Interrupt Enable register,                                 Address offset: 0x054 */

+  __IO uint32_t ILS;          /*!< FDCAN Interrupt Line Select register,                            Address offset: 0x058 */

+  __IO uint32_t ILE;          /*!< FDCAN Interrupt Line Enable register,                            Address offset: 0x05C */

+  __IO uint32_t RESERVED4[8]; /*!< Reserved,                                                                0x060 - 0x07C */

+  __IO uint32_t GFC;          /*!< FDCAN Global Filter Configuration register,                      Address offset: 0x080 */

+  __IO uint32_t SIDFC;        /*!< FDCAN Standard ID Filter Configuration register,                 Address offset: 0x084 */

+  __IO uint32_t XIDFC;        /*!< FDCAN Extended ID Filter Configuration register,                 Address offset: 0x088 */

+  __IO uint32_t RESERVED5;    /*!< Reserved,                                                                        0x08C */

+  __IO uint32_t XIDAM;        /*!< FDCAN Extended ID AND Mask register,                             Address offset: 0x090 */

+  __IO uint32_t HPMS;         /*!< FDCAN High Priority Message Status register,                     Address offset: 0x094 */

+  __IO uint32_t NDAT1;        /*!< FDCAN New Data 1 register,                                       Address offset: 0x098 */

+  __IO uint32_t NDAT2;        /*!< FDCAN New Data 2 register,                                       Address offset: 0x09C */

+  __IO uint32_t RXF0C;        /*!< FDCAN Rx FIFO 0 Configuration register,                          Address offset: 0x0A0 */

+  __IO uint32_t RXF0S;        /*!< FDCAN Rx FIFO 0 Status register,                                 Address offset: 0x0A4 */

+  __IO uint32_t RXF0A;        /*!< FDCAN Rx FIFO 0 Acknowledge register,                            Address offset: 0x0A8 */

+  __IO uint32_t RXBC;         /*!< FDCAN Rx Buffer Configuration register,                          Address offset: 0x0AC */

+  __IO uint32_t RXF1C;        /*!< FDCAN Rx FIFO 1 Configuration register,                          Address offset: 0x0B0 */

+  __IO uint32_t RXF1S;        /*!< FDCAN Rx FIFO 1 Status register,                                 Address offset: 0x0B4 */

+  __IO uint32_t RXF1A;        /*!< FDCAN Rx FIFO 1 Acknowledge register,                            Address offset: 0x0B8 */

+  __IO uint32_t RXESC;        /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register,        Address offset: 0x0BC */

+  __IO uint32_t TXBC;         /*!< FDCAN Tx Buffer Configuration register,                          Address offset: 0x0C0 */

+  __IO uint32_t TXFQS;        /*!< FDCAN Tx FIFO/Queue Status register,                             Address offset: 0x0C4 */

+  __IO uint32_t TXESC;        /*!< FDCAN Tx Buffer Element Size Configuration register,             Address offset: 0x0C8 */

+  __IO uint32_t TXBRP;        /*!< FDCAN Tx Buffer Request Pending register,                        Address offset: 0x0CC */

+  __IO uint32_t TXBAR;        /*!< FDCAN Tx Buffer Add Request register,                            Address offset: 0x0D0 */

+  __IO uint32_t TXBCR;        /*!< FDCAN Tx Buffer Cancellation Request register,                   Address offset: 0x0D4 */

+  __IO uint32_t TXBTO;        /*!< FDCAN Tx Buffer Transmission Occurred register,                  Address offset: 0x0D8 */

+  __IO uint32_t TXBCF;        /*!< FDCAN Tx Buffer Cancellation Finished register,                  Address offset: 0x0DC */

+  __IO uint32_t TXBTIE;       /*!< FDCAN Tx Buffer Transmission Interrupt Enable register,          Address offset: 0x0E0 */

+  __IO uint32_t TXBCIE;       /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */

+  __IO uint32_t RESERVED6[2]; /*!< Reserved,                                                                0x0E8 - 0x0EC */

+  __IO uint32_t TXEFC;        /*!< FDCAN Tx Event FIFO Configuration register,                      Address offset: 0x0F0 */

+  __IO uint32_t TXEFS;        /*!< FDCAN Tx Event FIFO Status register,                             Address offset: 0x0F4 */

+  __IO uint32_t TXEFA;        /*!< FDCAN Tx Event FIFO Acknowledge register,                        Address offset: 0x0F8 */

+  __IO uint32_t RESERVED7;    /*!< Reserved,                                                                        0x0FC */

+} FDCAN_GlobalTypeDef;

+

+/**

+  * @brief TTFD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t TTTMC;          /*!< TT Trigger Memory Configuration register,    Address offset: 0x100 */

+  __IO uint32_t TTRMC;          /*!< TT Reference Message Configuration register, Address offset: 0x104 */

+  __IO uint32_t TTOCF;          /*!< TT Operation Configuration register,         Address offset: 0x108 */

+  __IO uint32_t TTMLM;          /*!< TT Matrix Limits register,                   Address offset: 0x10C */

+  __IO uint32_t TURCF;          /*!< TUR Configuration register,                  Address offset: 0x110 */

+  __IO uint32_t TTOCN;          /*!< TT Operation Control register,               Address offset: 0x114 */

+  __IO uint32_t TTGTP;          /*!< TT Global Time Preset register,              Address offset: 0x118 */

+  __IO uint32_t TTTMK;          /*!< TT Time Mark register,                       Address offset: 0x11C */

+  __IO uint32_t TTIR;           /*!< TT Interrupt register,                       Address offset: 0x120 */

+  __IO uint32_t TTIE;           /*!< TT Interrupt Enable register,                Address offset: 0x124 */

+  __IO uint32_t TTILS;          /*!< TT Interrupt Line Select register,           Address offset: 0x128 */

+  __IO uint32_t TTOST;          /*!< TT Operation Status register,                Address offset: 0x12C */

+  __IO uint32_t TURNA;          /*!< TT TUR Numerator Actual register,            Address offset: 0x130 */

+  __IO uint32_t TTLGT;          /*!< TT Local and Global Time register,           Address offset: 0x134 */

+  __IO uint32_t TTCTC;          /*!< TT Cycle Time and Count register,            Address offset: 0x138 */

+  __IO uint32_t TTCPT;          /*!< TT Capture Time register,                    Address offset: 0x13C */

+  __IO uint32_t TTCSM;          /*!< TT Cycle Sync Mark register,                 Address offset: 0x140 */

+  __IO uint32_t RESERVED1[111]; /*!< Reserved,                                            0x144 - 0x2FC */

+  __IO uint32_t TTTS;           /*!< TT Trigger Select register,                  Address offset: 0x300 */

+} TTCAN_TypeDef;

+

+/**

+  * @brief FD Controller Area Network

+  */

+

+typedef struct

+{

+  __IO uint32_t CREL;  /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */

+  __IO uint32_t CCFG;  /*!< Calibration Configuration register,           Address offset: 0x04 */

+  __IO uint32_t CSTAT; /*!< Calibration Status register,                  Address offset: 0x08 */

+  __IO uint32_t CWD;   /*!< Calibration Watchdog register,                Address offset: 0x0C */

+  __IO uint32_t IR;    /*!< CCU Interrupt register,                       Address offset: 0x10 */

+  __IO uint32_t IE;    /*!< CCU Interrupt Enable register,                Address offset: 0x14 */

+} FDCAN_ClockCalibrationUnit_TypeDef;

+

+

+/**

+  * @brief Consumer Electronics Control

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;           /*!< CEC control register,              Address offset:0x00 */

+  __IO uint32_t CFGR;         /*!< CEC configuration register,        Address offset:0x04 */

+  __IO uint32_t TXDR;         /*!< CEC Tx data register ,             Address offset:0x08 */

+  __IO uint32_t RXDR;         /*!< CEC Rx Data Register,              Address offset:0x0C */

+  __IO uint32_t ISR;          /*!< CEC Interrupt and Status Register, Address offset:0x10 */

+  __IO uint32_t IER;          /*!< CEC interrupt enable register,     Address offset:0x14 */

+}CEC_TypeDef;

+

+/**

+  * @brief CRC calculation unit

+  */

+

+typedef struct

+{

+  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */

+  __IO uint32_t IDR;         /*!< CRC Independent data register,               Address offset: 0x04 */

+  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */

+  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */

+  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */

+  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */

+} CRC_TypeDef;

+

+

+/**

+  * @brief Clock Recovery System

+  */

+typedef struct

+{

+__IO uint32_t CR;            /*!< CRS ccontrol register,              Address offset: 0x00 */

+__IO uint32_t CFGR;          /*!< CRS configuration register,         Address offset: 0x04 */

+__IO uint32_t ISR;           /*!< CRS interrupt and status register,  Address offset: 0x08 */

+__IO uint32_t ICR;           /*!< CRS interrupt flag clear register,  Address offset: 0x0C */

+} CRS_TypeDef;

+

+

+/**

+  * @brief Digital to Analog Converter

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */

+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */

+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */

+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */

+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */

+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */

+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */

+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */

+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */

+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */

+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */

+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */

+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */

+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */

+  __IO uint32_t CCR;      /*!< DAC calibration control register,                        Address offset: 0x38 */

+  __IO uint32_t MCR;      /*!< DAC mode control register,                               Address offset: 0x3C */

+  __IO uint32_t SHSR1;    /*!< DAC Sample and Hold sample time register 1,              Address offset: 0x40 */

+  __IO uint32_t SHSR2;    /*!< DAC Sample and Hold sample time register 2,              Address offset: 0x44 */

+  __IO uint32_t SHHR;     /*!< DAC Sample and Hold hold time register,                  Address offset: 0x48 */

+  __IO uint32_t SHRR;     /*!< DAC Sample and Hold refresh time register,               Address offset: 0x4C */

+} DAC_TypeDef;

+

+/**

+  * @brief DFSDM module registers

+  */

+typedef struct

+{

+  __IO uint32_t FLTCR1;          /*!< DFSDM control register1,                          Address offset: 0x100 */

+  __IO uint32_t FLTCR2;          /*!< DFSDM control register2,                          Address offset: 0x104 */

+  __IO uint32_t FLTISR;          /*!< DFSDM interrupt and status register,              Address offset: 0x108 */

+  __IO uint32_t FLTICR;          /*!< DFSDM interrupt flag clear register,              Address offset: 0x10C */

+  __IO uint32_t FLTJCHGR;        /*!< DFSDM injected channel group selection register,  Address offset: 0x110 */

+  __IO uint32_t FLTFCR;          /*!< DFSDM filter control register,                    Address offset: 0x114 */

+  __IO uint32_t FLTJDATAR;       /*!< DFSDM data register for injected group,           Address offset: 0x118 */

+  __IO uint32_t FLTRDATAR;       /*!< DFSDM data register for regular group,            Address offset: 0x11C */

+  __IO uint32_t FLTAWHTR;        /*!< DFSDM analog watchdog high threshold register,    Address offset: 0x120 */

+  __IO uint32_t FLTAWLTR;        /*!< DFSDM analog watchdog low threshold register,     Address offset: 0x124 */

+  __IO uint32_t FLTAWSR;         /*!< DFSDM analog watchdog status register             Address offset: 0x128 */

+  __IO uint32_t FLTAWCFR;        /*!< DFSDM analog watchdog clear flag register         Address offset: 0x12C */

+  __IO uint32_t FLTEXMAX;        /*!< DFSDM extreme detector maximum register,          Address offset: 0x130 */

+  __IO uint32_t FLTEXMIN;        /*!< DFSDM extreme detector minimum register           Address offset: 0x134 */

+  __IO uint32_t FLTCNVTIMR;      /*!< DFSDM conversion timer,                           Address offset: 0x138 */

+} DFSDM_Filter_TypeDef;

+

+/**

+  * @brief DFSDM channel configuration registers

+  */

+typedef struct

+{

+  __IO uint32_t CHCFGR1;      /*!< DFSDM channel configuration register1,            Address offset: 0x00 */

+  __IO uint32_t CHCFGR2;      /*!< DFSDM channel configuration register2,            Address offset: 0x04 */

+  __IO uint32_t CHAWSCDR;     /*!< DFSDM channel analog watchdog and

+                                   short circuit detector register,                  Address offset: 0x08 */

+  __IO uint32_t CHWDATAR;     /*!< DFSDM channel watchdog filter data register,      Address offset: 0x0C */

+  __IO uint32_t CHDATINR;     /*!< DFSDM channel data input register,                Address offset: 0x10 */

+  __IO uint32_t CHDLYR;       /*!< DFSDM channel delay register,                     Address offset: 0x14 */

+} DFSDM_Channel_TypeDef;

+

+/**

+  * @brief Debug MCU

+  */

+typedef struct

+{

+  __IO uint32_t IDCODE;        /*!< MCU device ID code,                     Address offset: 0x00 */

+  __IO uint32_t CR;            /*!< Debug MCU configuration register,       Address offset: 0x04 */

+  uint32_t RESERVED4[11];      /*!< Reserved,                             Address offset: 0x08 */

+  __IO uint32_t APB3FZ1;     /*!< Debug MCU APB3FZ1 freeze register,    Address offset: 0x34 */

+  uint32_t RESERVED5;          /*!< Reserved,                             Address offset: 0x38 */

+  __IO uint32_t APB1LFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x3C */

+  uint32_t RESERVED6;          /*!< Reserved,                             Address offset: 0x40 */

+  __IO uint32_t APB1HFZ1;    /*!< Debug MCU APB1LFZ1 freeze register,   Address offset: 0x44 */

+  uint32_t RESERVED7;          /*!< Reserved,                             Address offset: 0x48 */

+  __IO uint32_t APB2FZ1;     /*!< Debug MCU APB2FZ1 freeze register,    Address offset: 0x4C */

+  uint32_t RESERVED8;          /*!< Reserved,                             Address offset: 0x50 */

+  __IO uint32_t APB4FZ1;     /*!< Debug MCU APB4FZ1 freeze register,    Address offset: 0x54 */

+}DBGMCU_TypeDef;

+/**

+  * @brief DCMI

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */

+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */

+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */

+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */

+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */

+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */

+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */

+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */

+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */

+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */

+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */

+} DCMI_TypeDef;

+

+/**

+  * @brief PSSI

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;             /*!< PSSI control register 1,               Address offset: 0x000 */

+  __IO uint32_t SR;             /*!< PSSI status register,                  Address offset: 0x004 */

+  __IO uint32_t RIS;            /*!< PSSI raw interrupt status register,    Address offset: 0x008 */

+  __IO uint32_t IER;            /*!< PSSI interrupt enable register,        Address offset: 0x00C */

+  __IO uint32_t MIS;            /*!< PSSI masked interrupt status register, Address offset: 0x010 */

+  __IO uint32_t ICR;            /*!< PSSI interrupt clear register,         Address offset: 0x014 */

+  __IO uint32_t RESERVED1[4];   /*!< Reserved,                                      0x018 - 0x024 */

+  __IO uint32_t DR;             /*!< PSSI data register,                    Address offset: 0x028 */

+  __IO uint32_t RESERVED2[241]; /*!< Reserved,                                      0x02C - 0x3EC */

+  __IO uint32_t HWCFGR;         /*!< PSSI IP HW configuration register,     Address offset: 0x3F0 */

+  __IO uint32_t VERR;           /*!< PSSI IP version register,              Address offset: 0x3F4 */

+  __IO uint32_t IPIDR;          /*!< PSSI IP ID register,                   Address offset: 0x3F8 */

+  __IO uint32_t SIDR;           /*!< PSSI SIZE ID register,                 Address offset: 0x3FC */

+} PSSI_TypeDef;

+

+/**

+  * @brief DMA Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */

+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */

+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */

+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */

+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */

+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */

+} DMA_Stream_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */

+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */

+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */

+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */

+} DMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CCR;          /*!< DMA channel x configuration register          */

+  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register         */

+  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register     */

+  __IO uint32_t CM0AR;        /*!< DMA channel x memory 0 address register       */

+  __IO uint32_t CM1AR;        /*!< DMA channel x memory 1 address register       */

+} BDMA_Channel_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */

+  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */

+} BDMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CCR;        /*!< DMA Multiplexer Channel x Control Register   */

+}DMAMUX_Channel_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CSR;      /*!< DMA Channel Status Register     */

+  __IO uint32_t  CFR;      /*!< DMA Channel Clear Flag Register */

+}DMAMUX_ChannelStatus_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  RGCR;        /*!< DMA Request Generator x Control Register   */

+}DMAMUX_RequestGen_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  RGSR;        /*!< DMA Request Generator Status Register       */

+  __IO uint32_t  RGCFR;       /*!< DMA Request Generator Clear Flag Register   */

+}DMAMUX_RequestGenStatus_TypeDef;

+

+/**

+  * @brief MDMA Controller

+  */

+typedef struct

+{

+  __IO uint32_t  GISR0;   /*!< MDMA Global Interrupt/Status Register 0,          Address offset: 0x00 */

+}MDMA_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t  CISR;      /*!< MDMA channel x interrupt/status register,             Address offset: 0x40 */

+  __IO uint32_t  CIFCR;     /*!< MDMA channel x interrupt flag clear register,         Address offset: 0x44 */

+  __IO uint32_t  CESR;      /*!< MDMA Channel x error status register,                 Address offset: 0x48 */

+  __IO uint32_t  CCR;       /*!< MDMA channel x control register,                      Address offset: 0x4C */

+  __IO uint32_t  CTCR;      /*!< MDMA channel x Transfer Configuration register,       Address offset: 0x50 */

+  __IO uint32_t  CBNDTR;    /*!< MDMA Channel x block number of data register,         Address offset: 0x54 */

+  __IO uint32_t  CSAR;      /*!< MDMA channel x source address register,               Address offset: 0x58 */

+  __IO uint32_t  CDAR;      /*!< MDMA channel x destination address register,          Address offset: 0x5C */

+  __IO uint32_t  CBRUR;     /*!< MDMA channel x Block Repeat address Update register,  Address offset: 0x60 */

+  __IO uint32_t  CLAR;      /*!< MDMA channel x Link Address register,                 Address offset: 0x64 */

+  __IO uint32_t  CTBR;      /*!< MDMA channel x Trigger and Bus selection Register,    Address offset: 0x68 */

+  uint32_t       RESERVED0; /*!< Reserved, 0x68                                                             */

+  __IO uint32_t  CMAR;      /*!< MDMA channel x Mask address register,                 Address offset: 0x70 */

+  __IO uint32_t  CMDR;      /*!< MDMA channel x Mask Data register,                    Address offset: 0x74 */

+}MDMA_Channel_TypeDef;

+

+/**

+  * @brief DMA2D Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;            /*!< DMA2D Control Register,                         Address offset: 0x00 */

+  __IO uint32_t ISR;           /*!< DMA2D Interrupt Status Register,                Address offset: 0x04 */

+  __IO uint32_t IFCR;          /*!< DMA2D Interrupt Flag Clear Register,            Address offset: 0x08 */

+  __IO uint32_t FGMAR;         /*!< DMA2D Foreground Memory Address Register,       Address offset: 0x0C */

+  __IO uint32_t FGOR;          /*!< DMA2D Foreground Offset Register,               Address offset: 0x10 */

+  __IO uint32_t BGMAR;         /*!< DMA2D Background Memory Address Register,       Address offset: 0x14 */

+  __IO uint32_t BGOR;          /*!< DMA2D Background Offset Register,               Address offset: 0x18 */

+  __IO uint32_t FGPFCCR;       /*!< DMA2D Foreground PFC Control Register,          Address offset: 0x1C */

+  __IO uint32_t FGCOLR;        /*!< DMA2D Foreground Color Register,                Address offset: 0x20 */

+  __IO uint32_t BGPFCCR;       /*!< DMA2D Background PFC Control Register,          Address offset: 0x24 */

+  __IO uint32_t BGCOLR;        /*!< DMA2D Background Color Register,                Address offset: 0x28 */

+  __IO uint32_t FGCMAR;        /*!< DMA2D Foreground CLUT Memory Address Register,  Address offset: 0x2C */

+  __IO uint32_t BGCMAR;        /*!< DMA2D Background CLUT Memory Address Register,  Address offset: 0x30 */

+  __IO uint32_t OPFCCR;        /*!< DMA2D Output PFC Control Register,              Address offset: 0x34 */

+  __IO uint32_t OCOLR;         /*!< DMA2D Output Color Register,                    Address offset: 0x38 */

+  __IO uint32_t OMAR;          /*!< DMA2D Output Memory Address Register,           Address offset: 0x3C */

+  __IO uint32_t OOR;           /*!< DMA2D Output Offset Register,                   Address offset: 0x40 */

+  __IO uint32_t NLR;           /*!< DMA2D Number of Line Register,                  Address offset: 0x44 */

+  __IO uint32_t LWR;           /*!< DMA2D Line Watermark Register,                  Address offset: 0x48 */

+  __IO uint32_t AMTCR;         /*!< DMA2D AHB Master Timer Configuration Register,  Address offset: 0x4C */

+  uint32_t      RESERVED[236]; /*!< Reserved, 0x50-0x3FF */

+  __IO uint32_t FGCLUT[256];   /*!< DMA2D Foreground CLUT,                          Address offset:400-7FF */

+  __IO uint32_t BGCLUT[256];   /*!< DMA2D Background CLUT,                          Address offset:800-BFF */

+} DMA2D_TypeDef;

+

+

+/**

+  * @brief External Interrupt/Event Controller

+  */

+

+typedef struct

+{

+__IO uint32_t RTSR1;               /*!< EXTI Rising trigger selection register,          Address offset: 0x00 */

+__IO uint32_t FTSR1;               /*!< EXTI Falling trigger selection register,         Address offset: 0x04 */

+__IO uint32_t SWIER1;              /*!< EXTI Software interrupt event register,          Address offset: 0x08 */

+__IO uint32_t D3PMR1;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */

+__IO uint32_t D3PCR1L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L)     Address offset: 0x10 */

+__IO uint32_t D3PCR1H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H)   Address offset: 0x14 */

+uint32_t      RESERVED1[2];        /*!< Reserved,                                        0x18 to 0x1C         */

+__IO uint32_t RTSR2;               /*!< EXTI Rising trigger selection register,          Address offset: 0x20 */

+__IO uint32_t FTSR2;               /*!< EXTI Falling trigger selection register,         Address offset: 0x24 */

+__IO uint32_t SWIER2;              /*!< EXTI Software interrupt event register,          Address offset: 0x28 */

+__IO uint32_t D3PMR2;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */

+__IO uint32_t D3PCR2L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L)  Address offset: 0x30 */

+__IO uint32_t D3PCR2H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */

+uint32_t      RESERVED2[2];        /*!< Reserved,                                        0x38 to 0x3C         */

+__IO uint32_t RTSR3;               /*!< EXTI Rising trigger selection register,          Address offset: 0x40 */

+__IO uint32_t FTSR3;               /*!< EXTI Falling trigger selection register,         Address offset: 0x44 */

+__IO uint32_t SWIER3;              /*!< EXTI Software interrupt event register,          Address offset: 0x48 */

+__IO uint32_t D3PMR3;              /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */

+__IO uint32_t D3PCR3L;             /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */

+__IO uint32_t D3PCR3H;             /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */

+uint32_t      RESERVED3[10];       /*!< Reserved,                                        0x58 to 0x7C         */

+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                    Address offset: 0x80 */

+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                        Address offset: 0x84 */

+__IO uint32_t PR1;                 /*!< EXTI Pending register,                           Address offset: 0x88 */

+uint32_t      RESERVED4;           /*!< Reserved,                                        0x8C                 */

+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                    Address offset: 0x90 */

+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                        Address offset: 0x94 */

+__IO uint32_t PR2;                 /*!< EXTI Pending register,                           Address offset: 0x98 */

+uint32_t      RESERVED5;           /*!< Reserved,                                        0x9C                 */

+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                    Address offset: 0xA0 */

+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                        Address offset: 0xA4 */

+__IO uint32_t PR3;                 /*!< EXTI Pending register,                           Address offset: 0xA8 */

+}EXTI_TypeDef;

+

+typedef struct

+{

+__IO uint32_t IMR1;                /*!< EXTI Interrupt mask register,                Address offset: 0x00 */

+__IO uint32_t EMR1;                /*!< EXTI Event mask register,                    Address offset: 0x04 */

+__IO uint32_t PR1;                 /*!< EXTI Pending register,                       Address offset: 0x08 */

+uint32_t      RESERVED1;           /*!< Reserved, 0x0C                                                    */

+__IO uint32_t IMR2;                /*!< EXTI Interrupt mask register,                Address offset: 0x10 */

+__IO uint32_t EMR2;                /*!< EXTI Event mask register,                    Address offset: 0x14 */

+__IO uint32_t PR2;                 /*!< EXTI Pending register,                       Address offset: 0x18 */

+uint32_t      RESERVED2;           /*!< Reserved, 0x1C                                                    */

+__IO uint32_t IMR3;                /*!< EXTI Interrupt mask register,                Address offset: 0x20 */

+__IO uint32_t EMR3;                /*!< EXTI Event mask register,                    Address offset: 0x24 */

+__IO uint32_t PR3;                 /*!< EXTI Pending register,                       Address offset: 0x28 */

+}EXTI_Core_TypeDef;

+

+

+/**

+  * @brief FLASH Registers

+  */

+

+typedef struct

+{

+  __IO uint32_t ACR;             /*!< FLASH access control register,                            Address offset: 0x00  */

+  __IO uint32_t KEYR1;           /*!< Flash Key Register for bank1,                             Address offset: 0x04  */

+  __IO uint32_t OPTKEYR;         /*!< Flash Option Key Register,                                Address offset: 0x08  */

+  __IO uint32_t CR1;             /*!< Flash Control Register for bank1,                         Address offset: 0x0C  */

+  __IO uint32_t SR1;             /*!< Flash Status Register for bank1,                          Address offset: 0x10  */

+  __IO uint32_t CCR1;            /*!< Flash Control Register for bank1,                         Address offset: 0x14  */

+  __IO uint32_t OPTCR;           /*!< Flash Option Control Register,                            Address offset: 0x18  */

+  __IO uint32_t OPTSR_CUR;       /*!< Flash Option Status Current Register,                     Address offset: 0x1C  */

+  __IO uint32_t OPTSR_PRG;       /*!< Flash Option Status to Program Register,                  Address offset: 0x20  */

+  __IO uint32_t OPTCCR;          /*!< Flash Option Clear Control Register,                      Address offset: 0x24  */

+  __IO uint32_t PRAR_CUR1;       /*!< Flash Current Protection Address Register for bank1,      Address offset: 0x28  */

+  __IO uint32_t PRAR_PRG1;       /*!< Flash Protection Address to Program Register for bank1,   Address offset: 0x2C  */

+  __IO uint32_t SCAR_CUR1;       /*!< Flash Current Secure Address Register for bank1,          Address offset: 0x30  */

+  __IO uint32_t SCAR_PRG1;       /*!< Flash Secure Address to Program Register for bank1,       Address offset: 0x34  */

+  __IO uint32_t WPSN_CUR1;       /*!< Flash Current Write Protection Register on bank1,         Address offset: 0x38  */

+  __IO uint32_t WPSN_PRG1;       /*!< Flash Write Protection to Program Register on bank1,      Address offset: 0x3C  */

+  __IO uint32_t BOOT_CUR;        /*!< Flash Current Boot Address for Pelican Core Register,     Address offset: 0x40  */

+  __IO uint32_t BOOT_PRG;        /*!< Flash Boot Address to Program for Pelican Core Register,  Address offset: 0x44  */

+  uint32_t      RESERVED0[2];    /*!< Reserved, 0x48 to 0x4C                                                          */

+  __IO uint32_t CRCCR1;          /*!< Flash CRC Control register For Bank1 Register ,           Address offset: 0x50  */

+  __IO uint32_t CRCSADD1;        /*!< Flash CRC Start Address Register for Bank1 ,              Address offset: 0x54  */

+  __IO uint32_t CRCEADD1;        /*!< Flash CRC End Address Register for Bank1 ,                Address offset: 0x58  */

+  __IO uint32_t CRCDATA;         /*!< Flash CRC Data Register for Bank1 ,                       Address offset: 0x5C  */

+  __IO uint32_t ECC_FA1;         /*!< Flash ECC Fail Address For Bank1 Register ,               Address offset: 0x60  */

+  uint32_t      RESERVED;        /*!< Reserved, 0x64                                                                  */

+  __IO uint32_t OTPBL_CUR;       /*!< Flash Current OTP Block Lock Register,                    Address offset: 0x68  */

+  __IO uint32_t OTPBL_PRG;       /*!< Flash OTP Block Lock to Program Register,                 Address offset: 0x6C  */

+  uint32_t      RESERVED1[37];   /*!< Reserved, 0x70 to 0x100                                                         */

+  __IO uint32_t KEYR2;           /*!< Flash Key Register for bank2,                             Address offset: 0x104 */

+  uint32_t      RESERVED2;       /*!< Reserved, 0x108                                                                 */

+  __IO uint32_t CR2;             /*!< Flash Control Register for bank2,                         Address offset: 0x10C */

+  __IO uint32_t SR2;             /*!< Flash Status Register for bank2,                          Address offset: 0x110 */

+  __IO uint32_t CCR2;            /*!< Flash Status Register for bank2,                          Address offset: 0x114 */

+  uint32_t      RESERVED3[4];    /*!< Reserved, 0x118 to 0x124                                                        */

+  __IO uint32_t PRAR_CUR2;       /*!< Flash Current Protection Address Register for bank2,      Address offset: 0x128 */

+  __IO uint32_t PRAR_PRG2;       /*!< Flash Protection Address to Program Register for bank2,   Address offset: 0x12C */

+  __IO uint32_t SCAR_CUR2;       /*!< Flash Current Secure Address Register for bank2,          Address offset: 0x130 */

+  __IO uint32_t SCAR_PRG2;       /*!< Flash Secure Address Register for bank2,                  Address offset: 0x134 */

+  __IO uint32_t WPSN_CUR2;       /*!< Flash Current Write Protection Register on bank2,         Address offset: 0x138 */

+  __IO uint32_t WPSN_PRG2;       /*!< Flash Write Protection to Program Register on bank2,      Address offset: 0x13C */

+  uint32_t      RESERVED4[4];    /*!< Reserved, 0x140 to 0x14C                                                        */

+  __IO uint32_t CRCCR2;          /*!< Flash CRC Control register For Bank2 Register ,           Address offset: 0x150 */

+  __IO uint32_t CRCSADD2;        /*!< Flash CRC Start Address Register for Bank2 ,              Address offset: 0x154 */

+  __IO uint32_t CRCEADD2;        /*!< Flash CRC End Address Register for Bank2 ,                Address offset: 0x158 */

+  __IO uint32_t CRCDATA2;        /*!< Flash CRC Data Register for Bank2 ,                       Address offset: 0x15C */

+  __IO uint32_t ECC_FA2;         /*!< Flash ECC Fail Address For Bank2 Register ,               Address offset: 0x160 */

+} FLASH_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */

+} FMC_Bank1_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank1E

+  */

+

+typedef struct

+{

+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */

+} FMC_Bank1E_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank2

+  */

+

+typedef struct

+{

+  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */

+  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */

+  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */

+  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */

+  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */

+  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */

+} FMC_Bank2_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank3

+  */

+

+typedef struct

+{

+  __IO uint32_t PCR;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */

+  __IO uint32_t SR;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */

+  __IO uint32_t PMEM;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */

+  __IO uint32_t PATT;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */

+  uint32_t      RESERVED;  /*!< Reserved, 0x90                                                            */

+  __IO uint32_t ECCR;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */

+} FMC_Bank3_TypeDef;

+

+/**

+  * @brief Flexible Memory Controller Bank5 and 6

+  */

+

+

+typedef struct

+{

+  __IO uint32_t SDCR[2];        /*!< SDRAM Control registers ,      Address offset: 0x140-0x144  */

+  __IO uint32_t SDTR[2];        /*!< SDRAM Timing registers ,       Address offset: 0x148-0x14C  */

+  __IO uint32_t SDCMR;       /*!< SDRAM Command Mode register,    Address offset: 0x150  */

+  __IO uint32_t SDRTR;       /*!< SDRAM Refresh Timer register,   Address offset: 0x154  */

+  __IO uint32_t SDSR;        /*!< SDRAM Status register,          Address offset: 0x158  */

+} FMC_Bank5_6_TypeDef;

+

+/**

+  * @brief GFXMMU registers

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;              /*!< GFXMMU configuration register,                     Address offset: 0x00 */

+  __IO uint32_t SR;              /*!< GFXMMU status register,                            Address offset: 0x04 */

+  __IO uint32_t FCR;             /*!< GFXMMU flag clear register,                        Address offset: 0x08 */

+  __IO uint32_t CCR;             /*!< GFXMMU Cache Control Register,                     Address offset: 0x0C */

+  __IO uint32_t DVR;             /*!< GFXMMU default value register,                     Address offset: 0x10 */

+       uint32_t RESERVED1[3];    /*!< Reserved1,                                         Address offset: 0x14 to 0x1C */

+  __IO uint32_t B0CR;            /*!< GFXMMU buffer 0 configuration register,            Address offset: 0x20 */

+  __IO uint32_t B1CR;            /*!< GFXMMU buffer 1 configuration register,            Address offset: 0x24 */

+  __IO uint32_t B2CR;            /*!< GFXMMU buffer 2 configuration register,            Address offset: 0x28 */

+  __IO uint32_t B3CR;            /*!< GFXMMU buffer 3 configuration register,            Address offset: 0x2C */

+       uint32_t RESERVED2[1012]; /*!< Reserved2,                                         Address offset: 0x30 to 0xFFC */

+  __IO uint32_t LUT[2048];       /*!< GFXMMU LUT registers,                              Address offset: 0x1000 to 0x2FFC

+                                      For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */

+} GFXMMU_TypeDef;

+/**

+  * @brief General Purpose I/O

+  */

+

+typedef struct

+{

+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */

+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */

+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */

+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */

+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */

+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */

+  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset,               Address offset: 0x18      */

+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */

+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */

+} GPIO_TypeDef;

+

+/**

+  * @brief Operational Amplifier (OPAMP)

+  */

+

+typedef struct

+{

+  __IO uint32_t CSR;          /*!< OPAMP control/status register,                      Address offset: 0x00 */

+  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,     Address offset: 0x04 */

+  __IO uint32_t HSOTR;        /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */

+} OPAMP_TypeDef;

+

+/**

+  * @brief System configuration controller

+  */

+

+typedef struct

+{

+ uint32_t RESERVED1;           /*!< Reserved,                                           Address offset: 0x00        */

+ __IO uint32_t PMCR;           /*!< SYSCFG peripheral mode configuration register,      Address offset: 0x04        */

+ __IO uint32_t EXTICR[4];      /*!< SYSCFG external interrupt configuration registers,  Address offset: 0x08-0x14   */

+ __IO uint32_t CFGR;           /*!< SYSCFG configuration registers,                     Address offset: 0x18        */

+ uint32_t RESERVED2;           /*!< Reserved,                                           Address offset: 0x1C        */

+ __IO uint32_t CCCSR;          /*!< SYSCFG compensation cell control/status register,   Address offset: 0x20        */

+ __IO uint32_t CCVR;           /*!< SYSCFG compensation cell value register,            Address offset: 0x24        */

+ __IO uint32_t CCCR;           /*!< SYSCFG compensation cell code register,             Address offset: 0x28        */

+

+} SYSCFG_TypeDef;

+

+/**

+  * @brief Inter-integrated Circuit Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */

+  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */

+  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */

+  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */

+  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */

+  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */

+  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */

+  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */

+  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */

+  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */

+  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */

+} I2C_TypeDef;

+

+/**

+  * @brief Independent WATCHDOG

+  */

+

+typedef struct

+{

+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */

+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */

+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */

+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */

+  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */

+} IWDG_TypeDef;

+

+

+/**

+  * @brief JPEG Codec

+  */

+typedef struct

+{

+  __IO uint32_t CONFR0;          /*!< JPEG Codec Control Register (JPEG_CONFR0),        Address offset: 00h       */

+  __IO uint32_t CONFR1;          /*!< JPEG Codec Control Register (JPEG_CONFR1),        Address offset: 04h       */

+  __IO uint32_t CONFR2;          /*!< JPEG Codec Control Register (JPEG_CONFR2),        Address offset: 08h       */

+  __IO uint32_t CONFR3;          /*!< JPEG Codec Control Register (JPEG_CONFR3),        Address offset: 0Ch       */

+  __IO uint32_t CONFR4;          /*!< JPEG Codec Control Register (JPEG_CONFR4),        Address offset: 10h       */

+  __IO uint32_t CONFR5;          /*!< JPEG Codec Control Register (JPEG_CONFR5),        Address offset: 14h       */

+  __IO uint32_t CONFR6;          /*!< JPEG Codec Control Register (JPEG_CONFR6),        Address offset: 18h       */

+  __IO uint32_t CONFR7;          /*!< JPEG Codec Control Register (JPEG_CONFR7),        Address offset: 1Ch       */

+  uint32_t  Reserved20[4];       /* Reserved                                            Address offset: 20h-2Ch   */

+  __IO uint32_t CR;              /*!< JPEG Control Register (JPEG_CR),                  Address offset: 30h       */

+  __IO uint32_t SR;              /*!< JPEG Status Register (JPEG_SR),                   Address offset: 34h       */

+  __IO uint32_t CFR;             /*!< JPEG Clear Flag Register (JPEG_CFR),              Address offset: 38h       */

+  uint32_t  Reserved3c;          /* Reserved                                            Address offset: 3Ch       */

+  __IO uint32_t DIR;             /*!< JPEG Data Input Register (JPEG_DIR),              Address offset: 40h       */

+  __IO uint32_t DOR;             /*!< JPEG Data Output Register (JPEG_DOR),             Address offset: 44h       */

+  uint32_t  Reserved48[2];       /* Reserved                                            Address offset: 48h-4Ch   */

+  __IO uint32_t QMEM0[16];       /*!< JPEG quantization tables 0,                       Address offset: 50h-8Ch   */

+  __IO uint32_t QMEM1[16];       /*!< JPEG quantization tables 1,                       Address offset: 90h-CCh   */

+  __IO uint32_t QMEM2[16];       /*!< JPEG quantization tables 2,                       Address offset: D0h-10Ch  */

+  __IO uint32_t QMEM3[16];       /*!< JPEG quantization tables 3,                       Address offset: 110h-14Ch */

+  __IO uint32_t HUFFMIN[16];     /*!< JPEG HuffMin tables,                              Address offset: 150h-18Ch */

+  __IO uint32_t HUFFBASE[32];    /*!< JPEG HuffSymb tables,                             Address offset: 190h-20Ch */

+  __IO uint32_t HUFFSYMB[84];    /*!< JPEG HUFFSYMB tables,                             Address offset: 210h-35Ch */

+  __IO uint32_t DHTMEM[103];     /*!< JPEG DHTMem tables,                               Address offset: 360h-4F8h */

+  uint32_t  Reserved4FC;         /* Reserved                                            Address offset: 4FCh      */

+  __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0,                 Address offset: 500h-65Ch */

+  __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1,                 Address offset: 660h-7BCh */

+  __IO uint32_t HUFFENC_DC0[8];  /*!< JPEG encodor, DC Huffman table 0,                 Address offset: 7C0h-7DCh */

+  __IO uint32_t HUFFENC_DC1[8];  /*!< JPEG encodor, DC Huffman table 1,                 Address offset: 7E0h-7FCh */

+

+} JPEG_TypeDef;

+

+/**

+  * @brief LCD-TFT Display Controller

+  */

+

+typedef struct

+{

+  uint32_t      RESERVED0[2];  /*!< Reserved, 0x00-0x04                                                       */

+  __IO uint32_t SSCR;          /*!< LTDC Synchronization Size Configuration Register,    Address offset: 0x08 */

+  __IO uint32_t BPCR;          /*!< LTDC Back Porch Configuration Register,              Address offset: 0x0C */

+  __IO uint32_t AWCR;          /*!< LTDC Active Width Configuration Register,            Address offset: 0x10 */

+  __IO uint32_t TWCR;          /*!< LTDC Total Width Configuration Register,             Address offset: 0x14 */

+  __IO uint32_t GCR;           /*!< LTDC Global Control Register,                        Address offset: 0x18 */

+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x1C-0x20                                                       */

+  __IO uint32_t SRCR;          /*!< LTDC Shadow Reload Configuration Register,           Address offset: 0x24 */

+  uint32_t      RESERVED2[1];  /*!< Reserved, 0x28                                                            */

+  __IO uint32_t BCCR;          /*!< LTDC Background Color Configuration Register,        Address offset: 0x2C */

+  uint32_t      RESERVED3[1];  /*!< Reserved, 0x30                                                            */

+  __IO uint32_t IER;           /*!< LTDC Interrupt Enable Register,                      Address offset: 0x34 */

+  __IO uint32_t ISR;           /*!< LTDC Interrupt Status Register,                      Address offset: 0x38 */

+  __IO uint32_t ICR;           /*!< LTDC Interrupt Clear Register,                       Address offset: 0x3C */

+  __IO uint32_t LIPCR;         /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */

+  __IO uint32_t CPSR;          /*!< LTDC Current Position Status Register,               Address offset: 0x44 */

+  __IO uint32_t CDSR;         /*!< LTDC Current Display Status Register,                 Address offset: 0x48 */

+} LTDC_TypeDef;

+

+/**

+  * @brief LCD-TFT Display layer x Controller

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;            /*!< LTDC Layerx Control Register                                  Address offset: 0x84 */

+  __IO uint32_t WHPCR;         /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */

+  __IO uint32_t WVPCR;         /*!< LTDC Layerx Window Vertical Position Configuration Register   Address offset: 0x8C */

+  __IO uint32_t CKCR;          /*!< LTDC Layerx Color Keying Configuration Register               Address offset: 0x90 */

+  __IO uint32_t PFCR;          /*!< LTDC Layerx Pixel Format Configuration Register               Address offset: 0x94 */

+  __IO uint32_t CACR;          /*!< LTDC Layerx Constant Alpha Configuration Register             Address offset: 0x98 */

+  __IO uint32_t DCCR;          /*!< LTDC Layerx Default Color Configuration Register              Address offset: 0x9C */

+  __IO uint32_t BFCR;          /*!< LTDC Layerx Blending Factors Configuration Register           Address offset: 0xA0 */

+  uint32_t      RESERVED0[2];  /*!< Reserved */

+  __IO uint32_t CFBAR;         /*!< LTDC Layerx Color Frame Buffer Address Register               Address offset: 0xAC */

+  __IO uint32_t CFBLR;         /*!< LTDC Layerx Color Frame Buffer Length Register                Address offset: 0xB0 */

+  __IO uint32_t CFBLNR;        /*!< LTDC Layerx ColorFrame Buffer Line Number Register            Address offset: 0xB4 */

+  uint32_t      RESERVED1[3];  /*!< Reserved */

+  __IO uint32_t CLUTWR;         /*!< LTDC Layerx CLUT Write Register                               Address offset: 0x144 */

+

+} LTDC_Layer_TypeDef;

+

+/**

+  * @brief Power Control

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;       /*!< PWR power control register 1,            Address offset: 0x00 */

+  __IO uint32_t CSR1;      /*!< PWR power control status register 1,     Address offset: 0x04 */

+  __IO uint32_t CR2;       /*!< PWR power control register 2,            Address offset: 0x08 */

+  __IO uint32_t CR3;       /*!< PWR power control register 3,            Address offset: 0x0C */

+  __IO uint32_t CPUCR;     /*!< PWR CPU control register,                Address offset: 0x10 */

+       uint32_t RESERVED0; /*!< Reserved,                                Address offset: 0x14 */

+  __IO uint32_t SRDCR;     /*!< PWR SRD domain control register,         Address offset: 0x18 */

+       uint32_t RESERVED1; /*!< Reserved,                                Address offset: 0x1C */

+  __IO uint32_t WKUPCR;    /*!< PWR wakeup clear register,               Address offset: 0x20 */

+  __IO uint32_t WKUPFR;    /*!< PWR wakeup flag register,                Address offset: 0x24 */

+  __IO uint32_t WKUPEPR;   /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */

+} PWR_TypeDef;

+

+/**

+  * @brief Reset and Clock Control

+  */

+

+typedef struct

+{

+ __IO uint32_t CR;             /*!< RCC clock control register,                                              Address offset: 0x00  */

+ __IO uint32_t HSICFGR;        /*!< HSI Clock Calibration Register,                                          Address offset: 0x04  */

+ __IO uint32_t CRRCR;          /*!< Clock Recovery RC  Register,                                             Address offset: 0x08  */

+ __IO uint32_t CSICFGR;        /*!< CSI Clock Calibration Register,                                          Address offset: 0x0C  */

+ __IO uint32_t CFGR;           /*!< RCC clock configuration register,                                        Address offset: 0x10  */

+ uint32_t     RESERVED1;       /*!< Reserved,                                                                Address offset: 0x14  */

+ __IO uint32_t CDCFGR1;         /*!< RCC Domain 1 configuration register,                                    Address offset: 0x18  */

+ __IO uint32_t CDCFGR2;         /*!< RCC Domain 2 configuration register,                                    Address offset: 0x1C  */

+ __IO uint32_t SRDCFGR;         /*!< RCC Domain 3 configuration register,                                    Address offset: 0x20  */

+ uint32_t     RESERVED2;       /*!< Reserved,                                                                Address offset: 0x24  */

+ __IO uint32_t PLLCKSELR;      /*!< RCC PLLs Clock Source Selection Register,                                Address offset: 0x28  */

+ __IO uint32_t PLLCFGR;        /*!< RCC PLLs  Configuration Register,                                        Address offset: 0x2C  */

+ __IO uint32_t PLL1DIVR;       /*!< RCC PLL1 Dividers Configuration Register,                                Address offset: 0x30  */

+ __IO uint32_t PLL1FRACR;      /*!< RCC PLL1 Fractional Divider Configuration Register,                      Address offset: 0x34  */

+ __IO uint32_t PLL2DIVR;       /*!< RCC PLL2 Dividers Configuration Register,                                Address offset: 0x38  */

+ __IO uint32_t PLL2FRACR;      /*!< RCC PLL2 Fractional Divider Configuration Register,                      Address offset: 0x3C  */

+ __IO uint32_t PLL3DIVR;       /*!< RCC PLL3 Dividers Configuration Register,                                Address offset: 0x40  */

+ __IO uint32_t PLL3FRACR;      /*!< RCC PLL3 Fractional Divider Configuration Register,                      Address offset: 0x44  */

+ uint32_t      RESERVED3;      /*!< Reserved,                                                                Address offset: 0x48  */

+ __IO uint32_t  CDCCIPR;       /*!< RCC Domain 1 Kernel Clock Configuration Register                         Address offset: 0x4C  */

+ __IO uint32_t  CDCCIP1R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x50  */

+ __IO uint32_t  CDCCIP2R;      /*!< RCC Domain 2 Kernel Clock Configuration Register                         Address offset: 0x54  */

+ __IO uint32_t  SRDCCIPR;       /*!< RCC Domain 3 Kernel Clock Configuration Register                         Address offset: 0x58  */

+ uint32_t      RESERVED4;      /*!< Reserved,                                                                Address offset: 0x5C  */

+ __IO uint32_t  CIER;          /*!< RCC Clock Source Interrupt Enable Register                               Address offset: 0x60  */

+ __IO uint32_t  CIFR;          /*!< RCC Clock Source Interrupt Flag Register                                 Address offset: 0x64  */

+ __IO uint32_t  CICR;          /*!< RCC Clock Source Interrupt Clear Register                                Address offset: 0x68  */

+ uint32_t     RESERVED5;       /*!< Reserved,                                                                Address offset: 0x6C  */

+ __IO uint32_t  BDCR;          /*!< RCC Vswitch Backup Domain Control Register,                              Address offset: 0x70  */

+ __IO uint32_t  CSR;           /*!< RCC clock control & status register,                                     Address offset: 0x74  */

+ uint32_t     RESERVED6;       /*!< Reserved,                                                                Address offset: 0x78  */

+ __IO uint32_t AHB3RSTR;       /*!< RCC AHB3 peripheral reset register,                                      Address offset: 0x7C  */

+ __IO uint32_t AHB1RSTR;       /*!< RCC AHB1 peripheral reset register,                                      Address offset: 0x80  */

+ __IO uint32_t AHB2RSTR;       /*!< RCC AHB2 peripheral reset register,                                      Address offset: 0x84  */

+ __IO uint32_t AHB4RSTR;       /*!< RCC AHB4 peripheral reset register,                                      Address offset: 0x88  */

+ __IO uint32_t APB3RSTR;       /*!< RCC APB3 peripheral reset register,                                      Address offset: 0x8C  */

+ __IO uint32_t APB1LRSTR;      /*!< RCC APB1 peripheral reset Low Word register,                             Address offset: 0x90  */

+ __IO uint32_t APB1HRSTR;      /*!< RCC APB1 peripheral reset High Word register,                            Address offset: 0x94  */

+ __IO uint32_t APB2RSTR;       /*!< RCC APB2 peripheral reset register,                                      Address offset: 0x98  */

+ __IO uint32_t APB4RSTR;       /*!< RCC APB4 peripheral reset register,                                      Address offset: 0x9C  */

+ uint32_t     RESERVED7;       /*!< Reserved,                                                                Address offset: 0xA0  */

+ uint32_t     RESERVED8;       /*!< Reserved,                                                                Address offset: 0xA4  */

+ __IO uint32_t SRDAMR;         /*!< RCC Domain 3 Autonomous Mode Register,                                   Address offset: 0xA8  */

+  uint32_t     RESERVED9;      /*!< Reserved, 0xAC-0xAF                                                      Address offset: 0xAC  */

+ __IO uint32_t CKGAENR;        /*!< AXI Clocks Gating Enable Register,                                       Address offset: 0xB0  */

+  uint32_t     RESERVED10[31];   /*!< Reserved, 0xAC-0xAF                                                    Address offset: 0xAC  */

+ __IO uint32_t RSR;            /*!< RCC Reset status register,                                               Address offset: 0xD0  */

+ __IO uint32_t AHB3ENR;        /*!< RCC AHB3 peripheral clock  register,                                     Address offset: 0xD4  */

+ __IO uint32_t AHB1ENR;        /*!< RCC AHB1 peripheral clock  register,                                     Address offset: 0xD8  */

+ __IO uint32_t AHB2ENR;        /*!< RCC AHB2 peripheral clock  register,                                     Address offset: 0xDC  */

+ __IO uint32_t AHB4ENR;        /*!< RCC AHB4 peripheral clock  register,                                     Address offset: 0xE0  */

+ __IO uint32_t APB3ENR;        /*!< RCC APB3 peripheral clock  register,                                     Address offset: 0xE4  */

+ __IO uint32_t APB1LENR;       /*!< RCC APB1 peripheral clock  Low Word register,                            Address offset: 0xE8  */

+ __IO uint32_t APB1HENR;       /*!< RCC APB1 peripheral clock  High Word register,                           Address offset: 0xEC  */

+ __IO uint32_t APB2ENR;        /*!< RCC APB2 peripheral clock  register,                                     Address offset: 0xF0  */

+ __IO uint32_t APB4ENR;        /*!< RCC APB4 peripheral clock  register,                                     Address offset: 0xF4  */

+ uint32_t      RESERVED12;      /*!< Reserved,                                                                Address offset: 0xF8  */

+ __IO uint32_t AHB3LPENR;      /*!< RCC AHB3 peripheral sleep clock  register,                               Address offset: 0xFC  */

+ __IO uint32_t AHB1LPENR;      /*!< RCC AHB1 peripheral sleep clock  register,                               Address offset: 0x100 */

+ __IO uint32_t AHB2LPENR;      /*!< RCC AHB2 peripheral sleep clock  register,                               Address offset: 0x104 */

+ __IO uint32_t AHB4LPENR;      /*!< RCC AHB4 peripheral sleep clock  register,                               Address offset: 0x108 */

+ __IO uint32_t APB3LPENR;      /*!< RCC APB3 peripheral sleep clock  register,                               Address offset: 0x10C */

+ __IO uint32_t APB1LLPENR;     /*!< RCC APB1 peripheral sleep clock  Low Word register,                      Address offset: 0x110 */

+ __IO uint32_t APB1HLPENR;     /*!< RCC APB1 peripheral sleep clock  High Word register,                     Address offset: 0x114 */

+ __IO uint32_t APB2LPENR;      /*!< RCC APB2 peripheral sleep clock  register,                               Address offset: 0x118 */

+ __IO uint32_t APB4LPENR;      /*!< RCC APB4 peripheral sleep clock  register,                               Address offset: 0x11C */

+ uint32_t     RESERVED13[4];   /*!< Reserved, 0x120-0x12C                                                    Address offset: 0x120 */

+

+} RCC_TypeDef;

+

+

+/**

+  * @brief Real-Time Clock

+  */

+typedef struct

+{

+  __IO uint32_t TR;             /*!< RTC time register,                              Address offset: 0x00 */

+  __IO uint32_t DR;             /*!< RTC date register,                              Address offset: 0x04 */

+  __IO uint32_t SSR;            /*!< RTC sub second register,                        Address offset: 0x08 */

+  __IO uint32_t ICSR;           /*!< RTC initialization control and status register, Address offset: 0x0C */

+  __IO uint32_t PRER;           /*!< RTC prescaler register,                         Address offset: 0x10 */

+  __IO uint32_t WUTR;           /*!< RTC wakeup timer register,                      Address offset: 0x14 */

+  __IO uint32_t CR;             /*!< RTC control register,                           Address offset: 0x18 */

+       uint32_t RESERVED0;      /*!< Reserved,                                       Address offset: 0x1C */

+       uint32_t RESERVED1;      /*!< Reserved,                                       Address offset: 0x20 */

+  __IO uint32_t WPR;            /*!< RTC write protection register,                  Address offset: 0x24 */

+  __IO uint32_t CALR;           /*!< RTC calibration register,                       Address offset: 0x28 */

+  __IO uint32_t SHIFTR;         /*!< RTC shift control register,                     Address offset: 0x2C */

+  __IO uint32_t TSTR;           /*!< RTC time stamp time register,                   Address offset: 0x30 */

+  __IO uint32_t TSDR;           /*!< RTC time stamp date register,                   Address offset: 0x34 */

+  __IO uint32_t TSSSR;          /*!< RTC time-stamp sub second register,             Address offset: 0x38 */

+       uint32_t RESERVED2;      /*!< Reserved,                                       Address offset: 0x3C */

+  __IO uint32_t ALRMAR;         /*!< RTC alarm A register,                           Address offset: 0x40 */

+  __IO uint32_t ALRMASSR;       /*!< RTC alarm A sub second register,                Address offset: 0x44 */

+  __IO uint32_t ALRMBR;         /*!< RTC alarm B register,                           Address offset: 0x48 */

+  __IO uint32_t ALRMBSSR;       /*!< RTC alarm B sub second register,                Address offset: 0x4C */

+  __IO uint32_t SR;             /*!< RTC Status register,                            Address offset: 0x50 */

+  __IO uint32_t MISR;           /*!< RTC masked interrupt status register,           Address offset: 0x54 */

+       uint32_t RESERVED3;      /*!< Reserved,                                       Address offset: 0x58 */

+  __IO uint32_t SCR;            /*!< RTC status Clear register,                      Address offset: 0x5C */

+  __IO uint32_t CFGR;           /*!< RTC configuration register,                     Address offset: 0x60 */

+} RTC_TypeDef;

+

+/**

+  * @brief Tamper and backup registers

+  */

+typedef struct

+{

+  __IO uint32_t CR1;            /*!< TAMP configuration register 1,            Address offset: 0x00 */

+  __IO uint32_t CR2;            /*!< TAMP configuration register 2,            Address offset: 0x04 */

+       uint32_t RESERVED0;      /*!< Reserved,                                 Address offset: 0x08 */

+  __IO uint32_t FLTCR;          /*!< TAMP filter control register,             Address offset: 0x0C */

+  __IO uint32_t ATCR1;          /*!< TAMP active tamper control register,      Address offset: 0x10 */

+  __IO uint32_t ATSEEDR;        /*!< TAMP active tamper seed register,         Address offset: 0x14 */

+  __IO uint32_t ATOR;           /*!< TAMP active tamper output register,       Address offset: 0x18 */

+       uint32_t RESERVED1[4];   /*!< Reserved,                                 Address offset: 0x1C -- 0x28 */

+  __IO uint32_t IER;            /*!< TAMP interrupt enable register,           Address offset: 0x2C */

+  __IO uint32_t SR;             /*!< TAMP status register,                     Address offset: 0x30 */

+  __IO uint32_t MISR;           /*!< TAMP masked interrupt status register,    Address offset: 0x34 */

+       uint32_t RESERVED2;      /*!< Reserved,                                 Address offset: 0x38 */

+  __IO uint32_t SCR;            /*!< TAMP status clear register,               Address offset: 0x3C */

+  __IO uint32_t COUNTR;         /*!< TAMP monotonic counter register,          Address offset: 0x40 */

+       uint32_t RESERVED3[3];   /*!< Reserved,                                 Address offset: 0x44 -- 0x4C */

+  __IO uint32_t CFGR;           /*!< TAMP configuration register,              Address offset: 0x50 */

+       uint32_t RESERVED4[43];  /*!< Reserved,                                 Address offset: 0x54 -- 0xFC */

+  __IO uint32_t BKP0R;          /*!< TAMP backup register 0,                   Address offset: 0x100 */

+  __IO uint32_t BKP1R;          /*!< TAMP backup register 1,                   Address offset: 0x104 */

+  __IO uint32_t BKP2R;          /*!< TAMP backup register 2,                   Address offset: 0x108 */

+  __IO uint32_t BKP3R;          /*!< TAMP backup register 3,                   Address offset: 0x10C */

+  __IO uint32_t BKP4R;          /*!< TAMP backup register 4,                   Address offset: 0x110 */

+  __IO uint32_t BKP5R;          /*!< TAMP backup register 5,                   Address offset: 0x114 */

+  __IO uint32_t BKP6R;          /*!< TAMP backup register 6,                   Address offset: 0x118 */

+  __IO uint32_t BKP7R;          /*!< TAMP backup register 7,                   Address offset: 0x11C */

+  __IO uint32_t BKP8R;          /*!< TAMP backup register 8,                   Address offset: 0x120 */

+  __IO uint32_t BKP9R;          /*!< TAMP backup register 9,                   Address offset: 0x124 */

+  __IO uint32_t BKP10R;         /*!< TAMP backup register 10,                  Address offset: 0x128 */

+  __IO uint32_t BKP11R;         /*!< TAMP backup register 11,                  Address offset: 0x12C */

+  __IO uint32_t BKP12R;         /*!< TAMP backup register 12,                  Address offset: 0x130 */

+  __IO uint32_t BKP13R;         /*!< TAMP backup register 13,                  Address offset: 0x134 */

+  __IO uint32_t BKP14R;         /*!< TAMP backup register 14,                  Address offset: 0x138 */

+  __IO uint32_t BKP15R;         /*!< TAMP backup register 15,                  Address offset: 0x13C */

+  __IO uint32_t BKP16R;         /*!< TAMP backup register 16,                  Address offset: 0x140 */

+  __IO uint32_t BKP17R;         /*!< TAMP backup register 17,                  Address offset: 0x144 */

+  __IO uint32_t BKP18R;         /*!< TAMP backup register 18,                  Address offset: 0x148 */

+  __IO uint32_t BKP19R;         /*!< TAMP backup register 19,                  Address offset: 0x14C */

+  __IO uint32_t BKP20R;         /*!< TAMP backup register 20,                  Address offset: 0x150 */

+  __IO uint32_t BKP21R;         /*!< TAMP backup register 21,                  Address offset: 0x154 */

+  __IO uint32_t BKP22R;         /*!< TAMP backup register 22,                  Address offset: 0x158 */

+  __IO uint32_t BKP23R;         /*!< TAMP backup register 23,                  Address offset: 0x15C */

+  __IO uint32_t BKP24R;         /*!< TAMP backup register 24,                  Address offset: 0x160 */

+  __IO uint32_t BKP25R;         /*!< TAMP backup register 25,                  Address offset: 0x164 */

+  __IO uint32_t BKP26R;         /*!< TAMP backup register 26,                  Address offset: 0x168 */

+  __IO uint32_t BKP27R;         /*!< TAMP backup register 27,                  Address offset: 0x16C */

+  __IO uint32_t BKP28R;         /*!< TAMP backup register 28,                  Address offset: 0x170 */

+  __IO uint32_t BKP29R;         /*!< TAMP backup register 29,                  Address offset: 0x174 */

+  __IO uint32_t BKP30R;         /*!< TAMP backup register 30,                  Address offset: 0x178 */

+  __IO uint32_t BKP31R;         /*!< TAMP backup register 31,                  Address offset: 0x17C */

+} TAMP_TypeDef;

+

+/**

+  * @brief Serial Audio Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t GCR;           /*!< SAI global configuration register, Address offset: 0x00 */

+  uint32_t      RESERVED0[16]; /*!< Reserved, 0x04 - 0x43                                   */

+  __IO uint32_t PDMCR;         /*!< SAI PDM control register,          Address offset: 0x44 */

+  __IO uint32_t PDMDLY;        /*!< SAI PDM delay register,            Address offset: 0x48 */

+} SAI_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CR1;      /*!< SAI block x configuration register 1,     Address offset: 0x04 */

+  __IO uint32_t CR2;      /*!< SAI block x configuration register 2,     Address offset: 0x08 */

+  __IO uint32_t FRCR;     /*!< SAI block x frame configuration register, Address offset: 0x0C */

+  __IO uint32_t SLOTR;    /*!< SAI block x slot register,                Address offset: 0x10 */

+  __IO uint32_t IMR;      /*!< SAI block x interrupt mask register,      Address offset: 0x14 */

+  __IO uint32_t SR;       /*!< SAI block x status register,              Address offset: 0x18 */

+  __IO uint32_t CLRFR;    /*!< SAI block x clear flag register,          Address offset: 0x1C */

+  __IO uint32_t DR;       /*!< SAI block x data register,                Address offset: 0x20 */

+} SAI_Block_TypeDef;

+

+/**

+  * @brief SPDIF-RX Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t   CR;           /*!< Control register,                   Address offset: 0x00 */

+  __IO uint32_t   IMR;          /*!< Interrupt mask register,            Address offset: 0x04 */

+  __IO uint32_t   SR;           /*!< Status register,                    Address offset: 0x08 */

+  __IO uint32_t   IFCR;         /*!< Interrupt Flag Clear register,      Address offset: 0x0C */

+  __IO uint32_t   DR;           /*!< Data input register,                Address offset: 0x10 */

+  __IO uint32_t   CSR;          /*!< Channel Status register,            Address offset: 0x14 */

+  __IO uint32_t   DIR;          /*!< Debug Information register,         Address offset: 0x18 */

+  uint32_t        RESERVED2;    /*!< Reserved,  0x1A                                          */

+} SPDIFRX_TypeDef;

+

+

+/**

+  * @brief Secure digital input/output Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t POWER;          /*!< SDMMC power control register,             Address offset: 0x00  */

+  __IO uint32_t CLKCR;          /*!< SDMMC clock control register,             Address offset: 0x04  */

+  __IO uint32_t ARG;            /*!< SDMMC argument register,                  Address offset: 0x08  */

+  __IO uint32_t CMD;            /*!< SDMMC command register,                   Address offset: 0x0C  */

+  __I uint32_t  RESPCMD;        /*!< SDMMC command response register,          Address offset: 0x10  */

+  __I uint32_t  RESP1;          /*!< SDMMC response 1 register,                Address offset: 0x14  */

+  __I uint32_t  RESP2;          /*!< SDMMC response 2 register,                Address offset: 0x18  */

+  __I uint32_t  RESP3;          /*!< SDMMC response 3 register,                Address offset: 0x1C  */

+  __I uint32_t  RESP4;          /*!< SDMMC response 4 register,                Address offset: 0x20  */

+  __IO uint32_t DTIMER;         /*!< SDMMC data timer register,                Address offset: 0x24  */

+  __IO uint32_t DLEN;           /*!< SDMMC data length register,               Address offset: 0x28  */

+  __IO uint32_t DCTRL;          /*!< SDMMC data control register,              Address offset: 0x2C  */

+  __I uint32_t  DCOUNT;         /*!< SDMMC data counter register,              Address offset: 0x30  */

+  __I uint32_t  STA;            /*!< SDMMC status register,                    Address offset: 0x34  */

+  __IO uint32_t ICR;            /*!< SDMMC interrupt clear register,           Address offset: 0x38  */

+  __IO uint32_t MASK;           /*!< SDMMC mask register,                      Address offset: 0x3C  */

+  __IO uint32_t ACKTIME;        /*!< SDMMC Acknowledgement timer register,     Address offset: 0x40  */

+  uint32_t      RESERVED0[3];   /*!< Reserved, 0x44 - 0x4C - 0x4C                                    */

+  __IO uint32_t IDMACTRL;       /*!< SDMMC DMA control register,               Address offset: 0x50  */

+  __IO uint32_t IDMABSIZE;      /*!< SDMMC DMA buffer size register,           Address offset: 0x54  */

+  __IO uint32_t IDMABASE0;      /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58  */

+  __IO uint32_t IDMABASE1;      /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C  */

+  uint32_t      RESERVED1[8];   /*!< Reserved, 0x60-0x7C                                             */

+  __IO uint32_t FIFO;           /*!< SDMMC data FIFO register,                 Address offset: 0x80  */

+  uint32_t      RESERVED2[222]; /*!< Reserved, 0x84-0x3F8                                            */

+  __IO uint32_t IPVR;           /*!< SDMMC data FIFO register,                 Address offset: 0x3FC */

+} SDMMC_TypeDef;

+

+

+/**

+  * @brief Delay Block DLYB

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;          /*!< DELAY BLOCK control register,  Address offset: 0x00 */

+  __IO uint32_t CFGR;        /*!< DELAY BLOCK configuration register,  Address offset: 0x04 */

+} DLYB_TypeDef;

+

+/**

+  * @brief HW Semaphore HSEM

+  */

+

+typedef struct

+{

+  __IO uint32_t R[32];      /*!< 2-step write lock and read back registers,     Address offset: 00h-7Ch  */

+  __IO uint32_t RLR[32];    /*!< 1-step read lock registers,                    Address offset: 80h-FCh  */

+  __IO uint32_t C1IER;      /*!< HSEM Interrupt enable register ,             Address offset: 100h     */

+  __IO uint32_t C1ICR;      /*!< HSEM Interrupt clear register ,              Address offset: 104h     */

+  __IO uint32_t C1ISR;      /*!< HSEM Interrupt Status register ,             Address offset: 108h     */

+  __IO uint32_t C1MISR;     /*!< HSEM Interrupt Masked Status register ,      Address offset: 10Ch     */

+  uint32_t  Reserved[12];   /* Reserved                                       Address offset: 110h-13Ch  */

+  __IO uint32_t CR;         /*!< HSEM Semaphore clear register ,                Address offset: 140h      */

+  __IO uint32_t KEYR;       /*!< HSEM Semaphore clear key register ,            Address offset: 144h      */

+

+} HSEM_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t IER;        /*!< HSEM interrupt enable register ,                Address offset:   0h     */

+  __IO uint32_t ICR;        /*!< HSEM interrupt clear register ,                 Address offset:   4h     */

+  __IO uint32_t ISR;        /*!< HSEM interrupt status register ,                Address offset:   8h     */

+  __IO uint32_t MISR;       /*!< HSEM masked interrupt status register ,         Address offset:   Ch     */

+} HSEM_Common_TypeDef;

+

+/**

+  * @brief Serial Peripheral Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;           /*!< SPI/I2S Control register 1,                      Address offset: 0x00 */

+  __IO uint32_t CR2;           /*!< SPI Control register 2,                          Address offset: 0x04 */

+  __IO uint32_t CFG1;          /*!< SPI Configuration register 1,                    Address offset: 0x08 */

+  __IO uint32_t CFG2;          /*!< SPI Configuration register 2,                    Address offset: 0x0C */

+  __IO uint32_t IER;           /*!< SPI/I2S Interrupt Enable register,               Address offset: 0x10 */

+  __IO uint32_t SR;            /*!< SPI/I2S Status register,                         Address offset: 0x14 */

+  __IO uint32_t IFCR;          /*!< SPI/I2S Interrupt/Status flags clear register,   Address offset: 0x18 */

+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                        */

+  __IO uint32_t TXDR;          /*!< SPI/I2S Transmit data register,                  Address offset: 0x20 */

+  uint32_t      RESERVED1[3];  /*!< Reserved, 0x24-0x2C                                                   */

+  __IO uint32_t RXDR;          /*!< SPI/I2S Receive data register,                   Address offset: 0x30 */

+  uint32_t      RESERVED2[3];  /*!< Reserved, 0x34-0x3C                                                   */

+  __IO uint32_t CRCPOLY;       /*!< SPI CRC Polynomial register,                     Address offset: 0x40 */

+  __IO uint32_t TXCRC;         /*!< SPI Transmitter CRC register,                    Address offset: 0x44 */

+  __IO uint32_t RXCRC;         /*!< SPI Receiver CRC register,                       Address offset: 0x48 */

+  __IO uint32_t UDRDR;         /*!< SPI Underrun data register,                      Address offset: 0x4C */

+  __IO uint32_t I2SCFGR;       /*!< I2S Configuration register,                      Address offset: 0x50 */

+

+} SPI_TypeDef;

+

+/**

+  * @brief DTS

+  */

+typedef struct

+{

+  __IO uint32_t CFGR1;         /*!< DTS configuration register,                Address offset: 0x00 */

+  uint32_t RESERVED0;          /*!< Reserved,                                  Address offset: 0x04 */

+  __IO uint32_t T0VALR1;       /*!< DTS T0 Value register,                     Address offset: 0x08 */

+  uint32_t RESERVED1;          /*!< Reserved,                                  Address offset: 0x0C */

+  __IO uint32_t RAMPVALR;      /*!< DTS Ramp value register,                   Address offset: 0x10 */

+  __IO uint32_t ITR1;          /*!< DTS Interrupt threshold register,          Address offset: 0x14 */

+  uint32_t RESERVED2;          /*!< Reserved,                                  Address offset: 0x18 */

+  __IO uint32_t DR;            /*!< DTS data register,                         Address offset: 0x1C */

+  __IO uint32_t SR;            /*!< DTS status register                        Address offset: 0x20 */

+  __IO uint32_t ITENR;         /*!< DTS Interrupt enable register,             Address offset: 0x24 */

+  __IO uint32_t ICIFR;         /*!< DTS Clear Interrupt flag register,         Address offset: 0x28 */

+  __IO uint32_t OR;            /*!< DTS option register 1,                     Address offset: 0x2C */

+}

+DTS_TypeDef;

+

+/**

+  * @brief TIM

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;         /*!< TIM control register 1,                   Address offset: 0x00 */

+  __IO uint32_t CR2;         /*!< TIM control register 2,                   Address offset: 0x04 */

+  __IO uint32_t SMCR;        /*!< TIM slave mode control register,          Address offset: 0x08 */

+  __IO uint32_t DIER;        /*!< TIM DMA/interrupt enable register,        Address offset: 0x0C */

+  __IO uint32_t SR;          /*!< TIM status register,                      Address offset: 0x10 */

+  __IO uint32_t EGR;         /*!< TIM event generation register,            Address offset: 0x14 */

+  __IO uint32_t CCMR1;       /*!< TIM capture/compare mode register 1,      Address offset: 0x18 */

+  __IO uint32_t CCMR2;       /*!< TIM capture/compare mode register 2,      Address offset: 0x1C */

+  __IO uint32_t CCER;        /*!< TIM capture/compare enable register,      Address offset: 0x20 */

+  __IO uint32_t CNT;         /*!< TIM counter register,                     Address offset: 0x24 */

+  __IO uint32_t PSC;         /*!< TIM prescaler,                            Address offset: 0x28 */

+  __IO uint32_t ARR;         /*!< TIM auto-reload register,                 Address offset: 0x2C */

+  __IO uint32_t RCR;         /*!< TIM repetition counter register,          Address offset: 0x30 */

+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,           Address offset: 0x34 */

+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,           Address offset: 0x38 */

+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,           Address offset: 0x3C */

+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,           Address offset: 0x40 */

+  __IO uint32_t BDTR;        /*!< TIM break and dead-time register,         Address offset: 0x44 */

+  __IO uint32_t DCR;         /*!< TIM DMA control register,                 Address offset: 0x48 */

+  __IO uint32_t DMAR;        /*!< TIM DMA address for full transfer,        Address offset: 0x4C */

+  uint32_t      RESERVED1;   /*!< Reserved, 0x50                                                 */

+  __IO uint32_t CCMR3;       /*!< TIM capture/compare mode register 3,      Address offset: 0x54 */

+  __IO uint32_t CCR5;        /*!< TIM capture/compare register5,            Address offset: 0x58 */

+  __IO uint32_t CCR6;        /*!< TIM capture/compare register6,            Address offset: 0x5C */

+  __IO uint32_t AF1;         /*!< TIM alternate function option register 1, Address offset: 0x60 */

+  __IO uint32_t AF2;         /*!< TIM alternate function option register 2, Address offset: 0x64 */

+  __IO uint32_t TISEL;       /*!< TIM Input Selection register,             Address offset: 0x68 */

+} TIM_TypeDef;

+

+/**

+  * @brief LPTIMIMER

+  */

+typedef struct

+{

+  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,         Address offset: 0x00 */

+  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,              Address offset: 0x04 */

+  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,             Address offset: 0x08 */

+  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                Address offset: 0x0C */

+  __IO uint32_t CR;       /*!< LPTIM Control register,                      Address offset: 0x10 */

+  __IO uint32_t CMP;      /*!< LPTIM Compare register,                      Address offset: 0x14 */

+  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                   Address offset: 0x18 */

+  __IO uint32_t CNT;      /*!< LPTIM Counter register,                      Address offset: 0x1C */

+  uint32_t  RESERVED1;    /*!< Reserved, 0x20                                                    */

+  __IO uint32_t CFGR2;    /*!< LPTIM Configuration register,                Address offset: 0x24 */

+} LPTIM_TypeDef;

+

+/**

+  * @brief Comparator

+  */

+typedef struct

+{

+  __IO uint32_t SR;        /*!< Comparator status register,                    Address offset: 0x00 */

+  __IO uint32_t ICFR;      /*!< Comparator interrupt clear flag register,       Address offset: 0x04 */

+  __IO uint32_t OR;        /*!< Comparator option register,                  Address offset: 0x08 */

+} COMPOPT_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CFGR;      /*!< Comparator configuration register  ,           Address offset: 0x00 */

+} COMP_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CFGR;       /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */

+} COMP_Common_TypeDef;

+/**

+  * @brief Universal Synchronous Asynchronous Receiver Transmitter

+  */

+

+typedef struct

+{

+  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */

+  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */

+  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */

+  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */

+  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */

+  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */

+  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */

+  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */

+  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */

+  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */

+  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */

+  __IO uint32_t PRESC;  /*!< USART clock Prescaler register,           Address offset: 0x2C */

+} USART_TypeDef;

+

+/**

+  * @brief Single Wire Protocol Master Interface SPWMI

+  */

+typedef struct

+{

+  __IO uint32_t CR;          /*!< SWPMI Configuration/Control register,     Address offset: 0x00 */

+  __IO uint32_t BRR;         /*!< SWPMI bitrate register,                   Address offset: 0x04 */

+    uint32_t  RESERVED1;     /*!< Reserved, 0x08                                                 */

+  __IO uint32_t ISR;         /*!< SWPMI Interrupt and Status register,      Address offset: 0x0C */

+  __IO uint32_t ICR;         /*!< SWPMI Interrupt Flag Clear register,      Address offset: 0x10 */

+  __IO uint32_t IER;         /*!< SWPMI Interrupt Enable register,          Address offset: 0x14 */

+  __IO uint32_t RFL;         /*!< SWPMI Receive Frame Length register,      Address offset: 0x18 */

+  __IO uint32_t TDR;         /*!< SWPMI Transmit data register,             Address offset: 0x1C */

+  __IO uint32_t RDR;         /*!< SWPMI Receive data register,              Address offset: 0x20 */

+  __IO uint32_t OR;          /*!< SWPMI Option register,                    Address offset: 0x24 */

+} SWPMI_TypeDef;

+

+/**

+  * @brief Window WATCHDOG

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */

+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */

+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */

+} WWDG_TypeDef;

+

+

+/**

+  * @brief RAM_ECC_Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t CR;           /*!< RAMECC monitor configuration register          */

+  __IO uint32_t SR;           /*!< RAMECC monitor status register                 */

+  __IO uint32_t FAR;          /*!< RAMECC monitor failing address register        */

+  __IO uint32_t FDRL;         /*!< RAMECC monitor failing data low register       */

+  __IO uint32_t FDRH;         /*!< RAMECC monitor failing data high register      */

+  __IO uint32_t FECR;         /*!< RAMECC monitor failing ECC error code register */

+} RAMECC_MonitorTypeDef;

+

+typedef struct

+{

+  __IO uint32_t IER;          /*!< RAMECC interrupt enable register */

+} RAMECC_TypeDef;

+/**

+  * @}

+  */

+

+

+/**

+  * @brief Crypto Processor

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;         /*!< CRYP control register,                                    Address offset: 0x00 */

+  __IO uint32_t SR;         /*!< CRYP status register,                                     Address offset: 0x04 */

+  __IO uint32_t DIN;         /*!< CRYP data input register,                                Address offset: 0x08 */

+  __IO uint32_t DOUT;       /*!< CRYP data output register,                                Address offset: 0x0C */

+  __IO uint32_t DMACR;      /*!< CRYP DMA control register,                                Address offset: 0x10 */

+  __IO uint32_t IMSCR;      /*!< CRYP interrupt mask set/clear register,                   Address offset: 0x14 */

+  __IO uint32_t RISR;       /*!< CRYP raw interrupt status register,                       Address offset: 0x18 */

+  __IO uint32_t MISR;       /*!< CRYP masked interrupt status register,                    Address offset: 0x1C */

+  __IO uint32_t K0LR;       /*!< CRYP key left  register 0,                                Address offset: 0x20 */

+  __IO uint32_t K0RR;       /*!< CRYP key right register 0,                                Address offset: 0x24 */

+  __IO uint32_t K1LR;       /*!< CRYP key left  register 1,                                Address offset: 0x28 */

+  __IO uint32_t K1RR;       /*!< CRYP key right register 1,                                Address offset: 0x2C */

+  __IO uint32_t K2LR;       /*!< CRYP key left  register 2,                                Address offset: 0x30 */

+  __IO uint32_t K2RR;       /*!< CRYP key right register 2,                                Address offset: 0x34 */

+  __IO uint32_t K3LR;       /*!< CRYP key left  register 3,                                Address offset: 0x38 */

+  __IO uint32_t K3RR;       /*!< CRYP key right register 3,                                Address offset: 0x3C */

+  __IO uint32_t IV0LR;      /*!< CRYP initialization vector left-word  register 0,         Address offset: 0x40 */

+  __IO uint32_t IV0RR;      /*!< CRYP initialization vector right-word register 0,         Address offset: 0x44 */

+  __IO uint32_t IV1LR;      /*!< CRYP initialization vector left-word  register 1,         Address offset: 0x48 */

+  __IO uint32_t IV1RR;      /*!< CRYP initialization vector right-word register 1,         Address offset: 0x4C */

+  __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0,        Address offset: 0x50 */

+  __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1,        Address offset: 0x54 */

+  __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2,        Address offset: 0x58 */

+  __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3,        Address offset: 0x5C */

+  __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4,        Address offset: 0x60 */

+  __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5,        Address offset: 0x64 */

+  __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6,        Address offset: 0x68 */

+  __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7,        Address offset: 0x6C */

+  __IO uint32_t CSGCM0R;    /*!< CRYP GCM/GMAC context swap register 0,                    Address offset: 0x70 */

+  __IO uint32_t CSGCM1R;    /*!< CRYP GCM/GMAC context swap register 1,                    Address offset: 0x74 */

+  __IO uint32_t CSGCM2R;    /*!< CRYP GCM/GMAC context swap register 2,                    Address offset: 0x78 */

+  __IO uint32_t CSGCM3R;    /*!< CRYP GCM/GMAC context swap register 3,                    Address offset: 0x7C */

+  __IO uint32_t CSGCM4R;    /*!< CRYP GCM/GMAC context swap register 4,                    Address offset: 0x80 */

+  __IO uint32_t CSGCM5R;    /*!< CRYP GCM/GMAC context swap register 5,                    Address offset: 0x84 */

+  __IO uint32_t CSGCM6R;    /*!< CRYP GCM/GMAC context swap register 6,                    Address offset: 0x88 */

+  __IO uint32_t CSGCM7R;    /*!< CRYP GCM/GMAC context swap register 7,                    Address offset: 0x8C */

+} CRYP_TypeDef;

+

+/**

+  * @brief HASH

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;               /*!< HASH control register,          Address offset: 0x00        */

+  __IO uint32_t DIN;              /*!< HASH data input register,       Address offset: 0x04        */

+  __IO uint32_t STR;              /*!< HASH start register,            Address offset: 0x08        */

+  __IO uint32_t HR[5];            /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */

+  __IO uint32_t IMR;              /*!< HASH interrupt enable register, Address offset: 0x20        */

+  __IO uint32_t SR;               /*!< HASH status register,           Address offset: 0x24        */

+       uint32_t RESERVED[52];     /*!< Reserved, 0x28-0xF4                                         */

+  __IO uint32_t CSR[54];          /*!< HASH context swap registers,    Address offset: 0x0F8-0x1CC */

+} HASH_TypeDef;

+

+/**

+  * @brief HASH_DIGEST

+  */

+

+typedef struct

+{

+  __IO uint32_t HR[8];     /*!< HASH digest registers,          Address offset: 0x310-0x32C */

+} HASH_DIGEST_TypeDef;

+

+

+/**

+  * @brief RNG

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */

+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */

+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */

+  uint32_t RESERVED;

+  __IO uint32_t HTCR;  /*!< RNG health test configuration register, Address offset: 0x10 */

+} RNG_TypeDef;

+

+/**

+  * @brief MDIOS

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;

+  __IO uint32_t WRFR;

+  __IO uint32_t CWRFR;

+  __IO uint32_t RDFR;

+  __IO uint32_t CRDFR;

+  __IO uint32_t SR;

+  __IO uint32_t CLRFR;

+  uint32_t RESERVED[57];

+  __IO uint32_t DINR0;

+  __IO uint32_t DINR1;

+  __IO uint32_t DINR2;

+  __IO uint32_t DINR3;

+  __IO uint32_t DINR4;

+  __IO uint32_t DINR5;

+  __IO uint32_t DINR6;

+  __IO uint32_t DINR7;

+  __IO uint32_t DINR8;

+  __IO uint32_t DINR9;

+  __IO uint32_t DINR10;

+  __IO uint32_t DINR11;

+  __IO uint32_t DINR12;

+  __IO uint32_t DINR13;

+  __IO uint32_t DINR14;

+  __IO uint32_t DINR15;

+  __IO uint32_t DINR16;

+  __IO uint32_t DINR17;

+  __IO uint32_t DINR18;

+  __IO uint32_t DINR19;

+  __IO uint32_t DINR20;

+  __IO uint32_t DINR21;

+  __IO uint32_t DINR22;

+  __IO uint32_t DINR23;

+  __IO uint32_t DINR24;

+  __IO uint32_t DINR25;

+  __IO uint32_t DINR26;

+  __IO uint32_t DINR27;

+  __IO uint32_t DINR28;

+  __IO uint32_t DINR29;

+  __IO uint32_t DINR30;

+  __IO uint32_t DINR31;

+  __IO uint32_t DOUTR0;

+  __IO uint32_t DOUTR1;

+  __IO uint32_t DOUTR2;

+  __IO uint32_t DOUTR3;

+  __IO uint32_t DOUTR4;

+  __IO uint32_t DOUTR5;

+  __IO uint32_t DOUTR6;

+  __IO uint32_t DOUTR7;

+  __IO uint32_t DOUTR8;

+  __IO uint32_t DOUTR9;

+  __IO uint32_t DOUTR10;

+  __IO uint32_t DOUTR11;

+  __IO uint32_t DOUTR12;

+  __IO uint32_t DOUTR13;

+  __IO uint32_t DOUTR14;

+  __IO uint32_t DOUTR15;

+  __IO uint32_t DOUTR16;

+  __IO uint32_t DOUTR17;

+  __IO uint32_t DOUTR18;

+  __IO uint32_t DOUTR19;

+  __IO uint32_t DOUTR20;

+  __IO uint32_t DOUTR21;

+  __IO uint32_t DOUTR22;

+  __IO uint32_t DOUTR23;

+  __IO uint32_t DOUTR24;

+  __IO uint32_t DOUTR25;

+  __IO uint32_t DOUTR26;

+  __IO uint32_t DOUTR27;

+  __IO uint32_t DOUTR28;

+  __IO uint32_t DOUTR29;

+  __IO uint32_t DOUTR30;

+  __IO uint32_t DOUTR31;

+} MDIOS_TypeDef;

+

+

+/**

+  * @brief USB_OTG_Core_Registers

+  */

+typedef struct

+{

+ __IO uint32_t GOTGCTL;               /*!< USB_OTG Control and Status Register          000h */

+  __IO uint32_t GOTGINT;              /*!< USB_OTG Interrupt Register                   004h */

+  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */

+  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */

+  __IO uint32_t GRSTCTL;              /*!< Core Reset Register                          010h */

+  __IO uint32_t GINTSTS;              /*!< Core Interrupt Register                      014h */

+  __IO uint32_t GINTMSK;              /*!< Core Interrupt Mask Register                 018h */

+  __IO uint32_t GRXSTSR;              /*!< Receive Sts Q Read Register                  01Ch */

+  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */

+  __IO uint32_t GRXFSIZ;              /*!< Receive FIFO Size Register                   024h */

+  __IO uint32_t DIEPTXF0_HNPTXFSIZ;   /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */

+  __IO uint32_t HNPTXSTS;             /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */

+  uint32_t Reserved30[2];             /*!< Reserved                                     030h */

+  __IO uint32_t GCCFG;                /*!< General Purpose IO Register                  038h */

+  __IO uint32_t CID;                  /*!< User ID Register                             03Ch */

+  __IO uint32_t GSNPSID;              /* USB_OTG core ID                                040h*/

+  __IO uint32_t GHWCFG1;              /* User HW config1                                044h*/

+  __IO uint32_t GHWCFG2;              /* User HW config2                                048h*/

+  __IO uint32_t GHWCFG3;              /*!< User HW config3                              04Ch */

+  uint32_t  Reserved6;                /*!< Reserved                                     050h */

+  __IO uint32_t GLPMCFG;              /*!< LPM Register                                 054h */

+  __IO uint32_t GPWRDN;               /*!< Power Down Register                          058h */

+  __IO uint32_t GDFIFOCFG;            /*!< DFIFO Software Config Register               05Ch */

+   __IO uint32_t GADPCTL;             /*!< ADP Timer, Control and Status Register       60Ch */

+    uint32_t  Reserved43[39];         /*!< Reserved                                058h-0FFh */

+  __IO uint32_t HPTXFSIZ;             /*!< Host Periodic Tx FIFO Size Reg               100h */

+  __IO uint32_t DIEPTXF[0x0F];        /*!< dev Periodic Transmit FIFO */

+} USB_OTG_GlobalTypeDef;

+

+

+/**

+  * @brief USB_OTG_device_Registers

+  */

+typedef struct

+{

+  __IO uint32_t DCFG;            /*!< dev Configuration Register   800h */

+  __IO uint32_t DCTL;            /*!< dev Control Register         804h */

+  __IO uint32_t DSTS;            /*!< dev Status Register (RO)     808h */

+  uint32_t Reserved0C;           /*!< Reserved                     80Ch */

+  __IO uint32_t DIEPMSK;         /*!< dev IN Endpoint Mask         810h */

+  __IO uint32_t DOEPMSK;         /*!< dev OUT Endpoint Mask        814h */

+  __IO uint32_t DAINT;           /*!< dev All Endpoints Itr Reg    818h */

+  __IO uint32_t DAINTMSK;        /*!< dev All Endpoints Itr Mask   81Ch */

+  uint32_t  Reserved20;          /*!< Reserved                     820h */

+  uint32_t Reserved9;            /*!< Reserved                     824h */

+  __IO uint32_t DVBUSDIS;        /*!< dev VBUS discharge Register  828h */

+  __IO uint32_t DVBUSPULSE;      /*!< dev VBUS Pulse Register      82Ch */

+  __IO uint32_t DTHRCTL;         /*!< dev threshold                830h */

+  __IO uint32_t DIEPEMPMSK;      /*!< dev empty msk                834h */

+  __IO uint32_t DEACHINT;        /*!< dedicated EP interrupt       838h */

+  __IO uint32_t DEACHMSK;        /*!< dedicated EP msk             83Ch */

+  uint32_t Reserved40;           /*!< dedicated EP mask            840h */

+  __IO uint32_t DINEP1MSK;       /*!< dedicated EP mask            844h */

+  uint32_t  Reserved44[15];      /*!< Reserved                 844-87Ch */

+  __IO uint32_t DOUTEP1MSK;      /*!< dedicated EP msk             884h */

+} USB_OTG_DeviceTypeDef;

+

+

+/**

+  * @brief USB_OTG_IN_Endpoint-Specific_Register

+  */

+typedef struct

+{

+  __IO uint32_t DIEPCTL;           /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */

+  uint32_t Reserved04;             /*!< Reserved                       900h + (ep_num * 20h) + 04h */

+  __IO uint32_t DIEPINT;           /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */

+  uint32_t Reserved0C;             /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */

+  __IO uint32_t DIEPTSIZ;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */

+  __IO uint32_t DIEPDMA;           /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */

+  __IO uint32_t DTXFSTS;           /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */

+  uint32_t Reserved18;             /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */

+} USB_OTG_INEndpointTypeDef;

+

+

+/**

+  * @brief USB_OTG_OUT_Endpoint-Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t DOEPCTL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */

+  uint32_t Reserved04;         /*!< Reserved                               B00h + (ep_num * 20h) + 04h */

+  __IO uint32_t DOEPINT;       /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */

+  uint32_t Reserved0C;         /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */

+  __IO uint32_t DOEPTSIZ;      /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */

+  __IO uint32_t DOEPDMA;       /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */

+  uint32_t Reserved18[2];      /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */

+} USB_OTG_OUTEndpointTypeDef;

+

+

+/**

+  * @brief USB_OTG_Host_Mode_Register_Structures

+  */

+typedef struct

+{

+  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */

+  __IO uint32_t HFIR;             /*!< Host Frame Interval Register         404h */

+  __IO uint32_t HFNUM;            /*!< Host Frame Nbr/Frame Remaining       408h */

+  uint32_t Reserved40C;           /*!< Reserved                             40Ch */

+  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */

+  __IO uint32_t HAINT;            /*!< Host All Channels Interrupt Register 414h */

+  __IO uint32_t HAINTMSK;         /*!< Host All Channels Interrupt Mask     418h */

+} USB_OTG_HostTypeDef;

+

+/**

+  * @brief USB_OTG_Host_Channel_Specific_Registers

+  */

+typedef struct

+{

+  __IO uint32_t HCCHAR;           /*!< Host Channel Characteristics Register    500h */

+  __IO uint32_t HCSPLT;           /*!< Host Channel Split Control Register      504h */

+  __IO uint32_t HCINT;            /*!< Host Channel Interrupt Register          508h */

+  __IO uint32_t HCINTMSK;         /*!< Host Channel Interrupt Mask Register     50Ch */

+  __IO uint32_t HCTSIZ;           /*!< Host Channel Transfer Size Register      510h */

+  __IO uint32_t HCDMA;            /*!< Host Channel DMA Address Register        514h */

+  uint32_t Reserved[2];           /*!< Reserved                                      */

+} USB_OTG_HostChannelTypeDef;

+/**

+  * @}

+  */

+

+/**

+  * @brief OCTO Serial Peripheral Interface

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;          /*!< OCTOSPI Control register,                           Address offset: 0x000 */

+  uint32_t RESERVED;         /*!< Reserved,                                           Address offset: 0x004 */

+  __IO uint32_t DCR1;        /*!< OCTOSPI Device Configuration register 1,            Address offset: 0x008 */

+  __IO uint32_t DCR2;        /*!< OCTOSPI Device Configuration register 2,            Address offset: 0x00C */

+  __IO uint32_t DCR3;        /*!< OCTOSPI Device Configuration register 3,            Address offset: 0x010 */

+  __IO uint32_t DCR4;        /*!< OCTOSPI Device Configuration register 4,            Address offset: 0x014 */

+  uint32_t RESERVED1[2];     /*!< Reserved,                                           Address offset: 0x018-0x01C */

+  __IO uint32_t SR;          /*!< OCTOSPI Status register,                            Address offset: 0x020 */

+  __IO uint32_t FCR;         /*!< OCTOSPI Flag Clear register,                        Address offset: 0x024 */

+  uint32_t RESERVED2[6];     /*!< Reserved,                                           Address offset: 0x028-0x03C */

+  __IO uint32_t DLR;         /*!< OCTOSPI Data Length register,                       Address offset: 0x040 */

+  uint32_t RESERVED3;        /*!< Reserved,                                           Address offset: 0x044 */

+  __IO uint32_t AR;          /*!< OCTOSPI Address register,                           Address offset: 0x048 */

+  uint32_t RESERVED4;        /*!< Reserved,                                           Address offset: 0x04C */

+  __IO uint32_t DR;          /*!< OCTOSPI Data register,                              Address offset: 0x050 */

+  uint32_t RESERVED5[11];    /*!< Reserved,                                           Address offset: 0x054-0x07C */

+  __IO uint32_t PSMKR;       /*!< OCTOSPI Polling Status Mask register,               Address offset: 0x080 */

+  uint32_t RESERVED6;        /*!< Reserved,                                           Address offset: 0x084 */

+  __IO uint32_t PSMAR;       /*!< OCTOSPI Polling Status Match register,              Address offset: 0x088 */

+  uint32_t RESERVED7;        /*!< Reserved,                                           Address offset: 0x08C */

+  __IO uint32_t PIR;         /*!< OCTOSPI Polling Interval register,                  Address offset: 0x090 */

+  uint32_t RESERVED8[27];    /*!< Reserved,                                           Address offset: 0x094-0x0FC */

+  __IO uint32_t CCR;         /*!< OCTOSPI Communication Configuration register,       Address offset: 0x100 */

+  uint32_t RESERVED9;        /*!< Reserved,                                           Address offset: 0x104 */

+  __IO uint32_t TCR;         /*!< OCTOSPI Timing Configuration register,              Address offset: 0x108 */

+  uint32_t RESERVED10;       /*!< Reserved,                                           Address offset: 0x10C */

+  __IO uint32_t IR;          /*!< OCTOSPI Instruction register,                       Address offset: 0x110 */

+  uint32_t RESERVED11[3];    /*!< Reserved,                                           Address offset: 0x114-0x11C */

+  __IO uint32_t ABR;         /*!< OCTOSPI Alternate Bytes register,                   Address offset: 0x120 */

+  uint32_t RESERVED12[3];    /*!< Reserved,                                           Address offset: 0x124-0x12C */

+  __IO uint32_t LPTR;        /*!< OCTOSPI Low Power Timeout register,                 Address offset: 0x130 */

+  uint32_t RESERVED13[3];    /*!< Reserved,                                           Address offset: 0x134-0x13C */

+  __IO uint32_t WPCCR;       /*!< OCTOSPI Wrap Communication Configuration register,  Address offset: 0x140 */

+  uint32_t RESERVED14;       /*!< Reserved,                                           Address offset: 0x144 */

+  __IO uint32_t WPTCR;       /*!< OCTOSPI Wrap Timing Configuration register,         Address offset: 0x148 */

+  uint32_t RESERVED15;       /*!< Reserved,                                           Address offset: 0x14C */

+  __IO uint32_t WPIR;        /*!< OCTOSPI Wrap Instruction register,                  Address offset: 0x150 */

+  uint32_t RESERVED16[3];    /*!< Reserved,                                           Address offset: 0x154-0x15C */

+  __IO uint32_t WPABR;       /*!< OCTOSPI Wrap Alternate Bytes register,              Address offset: 0x160 */

+  uint32_t RESERVED17[7];    /*!< Reserved,                                           Address offset: 0x164-0x17C */

+  __IO uint32_t WCCR;        /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */

+  uint32_t RESERVED18;       /*!< Reserved,                                           Address offset: 0x184 */

+  __IO uint32_t WTCR;        /*!< OCTOSPI Write Timing Configuration register,        Address offset: 0x188 */

+  uint32_t RESERVED19;       /*!< Reserved,                                           Address offset: 0x18C */

+  __IO uint32_t WIR;         /*!< OCTOSPI Write Instruction register,                 Address offset: 0x190 */

+  uint32_t RESERVED20[3];    /*!< Reserved,                                           Address offset: 0x194-0x19C */

+  __IO uint32_t WABR;        /*!< OCTOSPI Write Alternate Bytes register,             Address offset: 0x1A0 */

+  uint32_t RESERVED21[23];   /*!< Reserved,                                           Address offset: 0x1A4-0x1FC */

+  __IO uint32_t HLCR;        /*!< OCTOSPI Hyperbus Latency Configuration register,    Address offset: 0x200 */

+  uint32_t RESERVED22[122];  /*!< Reserved,                                           Address offset: 0x204-0x3EC */

+  __IO uint32_t HWCFGR;      /*!< OCTOSPI HW Configuration register,                  Address offset: 0x3F0 */

+  __IO uint32_t VER;         /*!< OCTOSPI Version register,                           Address offset: 0x3F4 */

+  __IO uint32_t ID;          /*!< OCTOSPI Identification register,                    Address offset: 0x3F8 */

+  __IO uint32_t MID;         /*!< OCTOPSI HW Magic ID register,                       Address offset: 0x3FC */

+} OCTOSPI_TypeDef;

+

+/**

+  * @}

+  */

+/**

+  * @brief OCTO Serial Peripheral Interface IO Manager

+  */

+

+typedef struct

+{

+  __IO uint32_t CR;          /*!< OCTOSPI IO Manager Control register,                 Address offset: 0x00 */

+  __IO uint32_t PCR[3];      /*!< OCTOSPI IO Manager Port[1:3] Configuration register, Address offset: 0x04-0x20 */

+} OCTOSPIM_TypeDef;

+

+/**

+  * @}

+  */

+

+/**

+  * @brief OTFD register

+  */

+typedef struct

+{

+  __IO uint32_t REG_CONFIGR;

+  __IO uint32_t REG_START_ADDR;

+  __IO uint32_t REG_END_ADDR;

+  __IO uint32_t REG_NONCER0;

+  __IO uint32_t REG_NONCER1;

+  __IO uint32_t REG_KEYR0;

+  __IO uint32_t REG_KEYR1;

+  __IO uint32_t REG_KEYR2;

+  __IO uint32_t REG_KEYR3;

+} OTFDEC_Region_TypeDef;

+

+typedef struct

+{

+  __IO uint32_t CR;

+  uint32_t RESERVED1[191];

+  __IO uint32_t ISR;

+  __IO uint32_t ICR;

+  __IO uint32_t IER;

+  uint32_t RESERVED2[56];

+  __IO uint32_t HWCFGR2;

+  __IO uint32_t HWCFGR1;

+  __IO uint32_t VERR;

+  __IO uint32_t IPIDR;

+  __IO uint32_t SIDR;

+} OTFDEC_TypeDef;

+/**

+  * @}

+  */

+

+/** @addtogroup Peripheral_memory_map

+  * @{

+  */

+#define CD_ITCMRAM_BASE           (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM  */

+#define CD_DTCMRAM_BASE           (0x20000000UL) /*!< Base address of : 128KB (2x64KB) system data RAM accessible over DTCM                   */

+#define CD_AXIFLASH_BASE          (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI                */

+

+#define CD_AXISRAM1_BASE          (0x24000000UL) /*!< Base address of : (up to 256KB) system data RAM1 accessible over over AXI                */

+#define CD_AXISRAM2_BASE          (0x24040000UL) /*!< Base address of : (up to 384KB) system data RAM2 accessible over over AXI                */

+#define CD_AXISRAM3_BASE          (0x240A0000UL) /*!< Base address of : (up to 384KB) system data RAM3 accessible over over AXI                */

+#define CD_AHBSRAM1_BASE          (0x30000000UL) /*!< Base address of : (up to 64KB) system data RAM1 accessible over over AXI->AHB Bridge     */

+#define CD_AHBSRAM2_BASE          (0x30010000UL) /*!< Base address of : (up to 64KB) system data RAM2 accessible over over AXI->AHB Bridge     */

+

+#define SRD_BKPSRAM_BASE           (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge                                */

+#define SRD_SRAM_BASE              (0x38000000UL) /*!< Base address of : Backup SRAM(32 KB) over AXI->AHB Bridge                               */

+

+#define OCTOSPI1_BASE             (0x90000000UL) /*!< Base address of : OCTOSPI1 memories  accessible over AXI                                 */

+#define OCTOSPI2_BASE             (0x70000000UL) /*!< Base address of : OCTOSPI2 memories  accessible over AXI                                 */

+

+#define FLASH_BANK1_BASE          (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI                          */

+#define FLASH_BANK2_BASE          (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI                          */

+#define FLASH_END                 (0x081FFFFFUL) /*!< FLASH end address                                                                       */

+

+/* Legacy define */

+#define FLASH_BASE                FLASH_BANK1_BASE

+#define D1_AXISRAM_BASE           CD_AXISRAM1_BASE

+

+#define FLASH_OTP_BASE            (0x08FFF000UL) /*!< Base address of : (up to 1KB) embedded FLASH Bank1 OTP Area                           */

+#define FLASH_OTP_END             (0x08FFF3FFUL) /*!< End address of : (up to 1KB) embedded FLASH Bank1 OTP Area                            */

+

+

+/*!< Device electronic signature memory map */

+#define UID_BASE                  (0x08FFF800UL)            /*!< Unique device ID register base address */

+#define FLASHSIZE_BASE            (0x08FFF80CUL)            /*!< FLASH Size register base address */

+#define PACKAGE_BASE              (0x08FFF80EUL)            /*!< Package Data register base address */

+

+#define PERIPH_BASE               (0x40000000UL) /*!< Base address of : AHB/ABP Peripherals                                                    */

+/*!< Peripheral memory map */

+#define CD_APB1PERIPH_BASE        PERIPH_BASE                   /*!<  D2_APB1PERIPH_BASE        PERIPH_BASE                                    */

+#define CD_APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)   /*!<  D2_APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)                    */

+#define CD_AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)   /*!<  D2_AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)                    */

+#define CD_AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)   /*!<  D2_AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)                    */

+

+#define CD_APB3PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)   /*!<  D1_APB1PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)                    */

+#define CD_AHB3PERIPH_BASE       (PERIPH_BASE + 0x12000000UL)   /*!<  D1_AHB1PERIPH_BASE       (PERIPH_BASE + 0x12000000UL)                    */

+

+#define SRD_APB4PERIPH_BASE      (PERIPH_BASE + 0x18000000UL)   /*!<  D3_APB1PERIPH_BASE       (PERIPH_BASE + 0x18000000UL)                    */

+#define SRD_AHB4PERIPH_BASE      (PERIPH_BASE + 0x18020000UL)   /*!<  D3_AHB1PERIPH_BASE       (PERIPH_BASE + 0x18020000UL)                    */

+

+/*!< Legacy Peripheral memory map */

+#define APB1PERIPH_BASE        PERIPH_BASE

+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)

+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)

+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x08020000UL)

+

+/*!< CD_AHB3PERIPH peripherals */

+#define MDMA_BASE             (CD_AHB3PERIPH_BASE + 0x0000UL)

+#define DMA2D_BASE            (CD_AHB3PERIPH_BASE + 0x1000UL)

+#define FLASH_R_BASE          (CD_AHB3PERIPH_BASE + 0x2000UL)

+#define JPGDEC_BASE           (CD_AHB3PERIPH_BASE + 0x3000UL)

+#define FMC_R_BASE            (CD_AHB3PERIPH_BASE + 0x4000UL)

+#define OCTOSPI1_R_BASE       (CD_AHB3PERIPH_BASE + 0x5000UL)

+#define DLYB_OCTOSPI1_BASE    (CD_AHB3PERIPH_BASE + 0x6000UL)

+#define SDMMC1_BASE           (CD_AHB3PERIPH_BASE + 0x7000UL)

+#define DLYB_SDMMC1_BASE      (CD_AHB3PERIPH_BASE + 0x8000UL)

+#define RAMECC_BASE           (CD_AHB3PERIPH_BASE + 0x9000UL)

+#define OCTOSPI2_R_BASE       (CD_AHB3PERIPH_BASE + 0xA000UL)

+#define DLYB_OCTOSPI2_BASE    (CD_AHB3PERIPH_BASE + 0xB000UL)

+#define OCTOSPIM_BASE         (CD_AHB3PERIPH_BASE + 0xB400UL)

+

+/*!< CD_AHB1PERIPH peripherals */

+

+#define DMA1_BASE               (CD_AHB1PERIPH_BASE + 0x0000UL)

+#define DMA2_BASE               (CD_AHB1PERIPH_BASE + 0x0400UL)

+#define DMAMUX1_BASE            (CD_AHB1PERIPH_BASE + 0x0800UL)

+#define ADC1_BASE               (CD_AHB1PERIPH_BASE + 0x2000UL)

+#define ADC2_BASE               (CD_AHB1PERIPH_BASE + 0x2100UL)

+#define ADC12_COMMON_BASE       (CD_AHB1PERIPH_BASE + 0x2300UL)

+#define CRC_BASE                (CD_AHB1PERIPH_BASE + 0x3000UL)

+

+/*!< USB registers base address */

+#define USB1_OTG_HS_PERIPH_BASE              (0x40040000UL)

+#define USB_OTG_GLOBAL_BASE                  (0x000UL)

+#define USB_OTG_DEVICE_BASE                  (0x800UL)

+#define USB_OTG_IN_ENDPOINT_BASE             (0x900UL)

+#define USB_OTG_OUT_ENDPOINT_BASE            (0xB00UL)

+#define USB_OTG_EP_REG_SIZE                  (0x20UL)

+#define USB_OTG_HOST_BASE                    (0x400UL)

+#define USB_OTG_HOST_PORT_BASE               (0x440UL)

+#define USB_OTG_HOST_CHANNEL_BASE            (0x500UL)

+#define USB_OTG_HOST_CHANNEL_SIZE            (0x20UL)

+#define USB_OTG_PCGCCTL_BASE                 (0xE00UL)

+#define USB_OTG_FIFO_BASE                    (0x1000UL)

+#define USB_OTG_FIFO_SIZE                    (0x1000UL)

+

+/*!< CD_AHB2PERIPH peripherals */

+

+#define DCMI_BASE              (CD_AHB2PERIPH_BASE + 0x0000UL)

+#define PSSI_BASE              (CD_AHB2PERIPH_BASE + 0x0400UL)

+#define HSEM_BASE              (CD_AHB2PERIPH_BASE + 0x0800UL)

+#define CRYP_BASE              (CD_AHB2PERIPH_BASE + 0x1000UL)

+#define HASH_BASE              (CD_AHB2PERIPH_BASE + 0x1400UL)

+#define HASH_DIGEST_BASE       (CD_AHB2PERIPH_BASE + 0x1710UL)

+#define RNG_BASE               (CD_AHB2PERIPH_BASE + 0x1800UL)

+#define SDMMC2_BASE            (CD_AHB2PERIPH_BASE + 0x2400UL)

+#define DLYB_SDMMC2_BASE       (CD_AHB2PERIPH_BASE + 0x2800UL)

+#define BDMA1_BASE             (CD_AHB2PERIPH_BASE + 0x2C00UL)

+

+/*!< SRD_AHB4PERIPH peripherals */

+#define GPIOA_BASE            (SRD_AHB4PERIPH_BASE + 0x0000UL)

+#define GPIOB_BASE            (SRD_AHB4PERIPH_BASE + 0x0400UL)

+#define GPIOC_BASE            (SRD_AHB4PERIPH_BASE + 0x0800UL)

+#define GPIOD_BASE            (SRD_AHB4PERIPH_BASE + 0x0C00UL)

+#define GPIOE_BASE            (SRD_AHB4PERIPH_BASE + 0x1000UL)

+#define GPIOF_BASE            (SRD_AHB4PERIPH_BASE + 0x1400UL)

+#define GPIOG_BASE            (SRD_AHB4PERIPH_BASE + 0x1800UL)

+#define GPIOH_BASE            (SRD_AHB4PERIPH_BASE + 0x1C00UL)

+#define GPIOI_BASE            (SRD_AHB4PERIPH_BASE + 0x2000UL)

+#define GPIOJ_BASE            (SRD_AHB4PERIPH_BASE + 0x2400UL)

+#define GPIOK_BASE            (SRD_AHB4PERIPH_BASE + 0x2800UL)

+#define RCC_BASE              (SRD_AHB4PERIPH_BASE + 0x4400UL)

+#define PWR_BASE              (SRD_AHB4PERIPH_BASE + 0x4800UL)

+#define BDMA2_BASE            (SRD_AHB4PERIPH_BASE + 0x5400UL)

+#define DMAMUX2_BASE          (SRD_AHB4PERIPH_BASE + 0x5800UL)

+

+/*!< CD_APB3PERIPH peripherals */

+#define LTDC_BASE             (CD_APB3PERIPH_BASE + 0x1000UL)

+#define LTDC_Layer1_BASE      (LTDC_BASE + 0x84UL)

+#define LTDC_Layer2_BASE      (LTDC_BASE + 0x104UL)

+#define WWDG1_BASE            (CD_APB3PERIPH_BASE + 0x3000UL)

+

+/*!< CD_APB1PERIPH peripherals */

+#define TIM2_BASE             (CD_APB1PERIPH_BASE + 0x0000UL)

+#define TIM3_BASE             (CD_APB1PERIPH_BASE + 0x0400UL)

+#define TIM4_BASE             (CD_APB1PERIPH_BASE + 0x0800UL)

+#define TIM5_BASE             (CD_APB1PERIPH_BASE + 0x0C00UL)

+#define TIM6_BASE             (CD_APB1PERIPH_BASE + 0x1000UL)

+#define TIM7_BASE             (CD_APB1PERIPH_BASE + 0x1400UL)

+#define TIM12_BASE            (CD_APB1PERIPH_BASE + 0x1800UL)

+#define TIM13_BASE            (CD_APB1PERIPH_BASE + 0x1C00UL)

+#define TIM14_BASE            (CD_APB1PERIPH_BASE + 0x2000UL)

+#define LPTIM1_BASE           (CD_APB1PERIPH_BASE + 0x2400UL)

+

+#define SPI2_BASE             (CD_APB1PERIPH_BASE + 0x3800UL)

+#define SPI3_BASE             (CD_APB1PERIPH_BASE + 0x3C00UL)

+#define SPDIFRX_BASE          (CD_APB1PERIPH_BASE + 0x4000UL)

+#define USART2_BASE           (CD_APB1PERIPH_BASE + 0x4400UL)

+#define USART3_BASE           (CD_APB1PERIPH_BASE + 0x4800UL)

+#define UART4_BASE            (CD_APB1PERIPH_BASE + 0x4C00UL)

+#define UART5_BASE            (CD_APB1PERIPH_BASE + 0x5000UL)

+#define I2C1_BASE             (CD_APB1PERIPH_BASE + 0x5400UL)

+#define I2C2_BASE             (CD_APB1PERIPH_BASE + 0x5800UL)

+#define I2C3_BASE             (CD_APB1PERIPH_BASE + 0x5C00UL)

+#define CEC_BASE              (CD_APB1PERIPH_BASE + 0x6C00UL)

+#define DAC1_BASE             (CD_APB1PERIPH_BASE + 0x7400UL)

+#define UART7_BASE            (CD_APB1PERIPH_BASE + 0x7800UL)

+#define UART8_BASE            (CD_APB1PERIPH_BASE + 0x7C00UL)

+#define CRS_BASE              (CD_APB1PERIPH_BASE + 0x8400UL)

+#define SWPMI1_BASE           (CD_APB1PERIPH_BASE + 0x8800UL)

+#define OPAMP_BASE            (CD_APB1PERIPH_BASE + 0x9000UL)

+#define OPAMP1_BASE           (CD_APB1PERIPH_BASE + 0x9000UL)

+#define OPAMP2_BASE           (CD_APB1PERIPH_BASE + 0x9010UL)

+#define MDIOS_BASE            (CD_APB1PERIPH_BASE + 0x9400UL)

+#define FDCAN1_BASE           (CD_APB1PERIPH_BASE + 0xA000UL)

+#define FDCAN2_BASE           (CD_APB1PERIPH_BASE + 0xA400UL)

+#define FDCAN_CCU_BASE        (CD_APB1PERIPH_BASE + 0xA800UL)

+#define SRAMCAN_BASE          (CD_APB1PERIPH_BASE + 0xAC00UL)

+

+/*!< CD_APB2PERIPH peripherals */

+

+#define TIM1_BASE             (CD_APB2PERIPH_BASE + 0x0000UL)

+#define TIM8_BASE             (CD_APB2PERIPH_BASE + 0x0400UL)

+#define USART1_BASE           (CD_APB2PERIPH_BASE + 0x1000UL)

+#define USART6_BASE           (CD_APB2PERIPH_BASE + 0x1400UL)

+#define UART9_BASE            (CD_APB2PERIPH_BASE + 0x1800UL)

+#define USART10_BASE          (CD_APB2PERIPH_BASE + 0x1C00UL)

+#define SPI1_BASE             (CD_APB2PERIPH_BASE + 0x3000UL)

+#define SPI4_BASE             (CD_APB2PERIPH_BASE + 0x3400UL)

+#define TIM15_BASE            (CD_APB2PERIPH_BASE + 0x4000UL)

+#define TIM16_BASE            (CD_APB2PERIPH_BASE + 0x4400UL)

+#define TIM17_BASE            (CD_APB2PERIPH_BASE + 0x4800UL)

+#define SPI5_BASE             (CD_APB2PERIPH_BASE + 0x5000UL)

+#define SAI1_BASE             (CD_APB2PERIPH_BASE + 0x5800UL)

+#define SAI1_Block_A_BASE     (SAI1_BASE + 0x004UL)

+#define SAI1_Block_B_BASE     (SAI1_BASE + 0x024UL)

+#define SAI2_BASE             (CD_APB2PERIPH_BASE + 0x5C00UL)

+#define SAI2_Block_A_BASE     (SAI2_BASE + 0x004UL)

+#define SAI2_Block_B_BASE     (SAI2_BASE + 0x024UL)

+#define DFSDM1_BASE           (CD_APB2PERIPH_BASE + 0x7800UL)

+#define DFSDM1_Channel0_BASE  (DFSDM1_BASE + 0x00UL)

+#define DFSDM1_Channel1_BASE  (DFSDM1_BASE + 0x20UL)

+#define DFSDM1_Channel2_BASE  (DFSDM1_BASE + 0x40UL)

+#define DFSDM1_Channel3_BASE  (DFSDM1_BASE + 0x60UL)

+#define DFSDM1_Channel4_BASE  (DFSDM1_BASE + 0x80UL)

+#define DFSDM1_Channel5_BASE  (DFSDM1_BASE + 0xA0UL)

+#define DFSDM1_Channel6_BASE  (DFSDM1_BASE + 0xC0UL)

+#define DFSDM1_Channel7_BASE  (DFSDM1_BASE + 0xE0UL)

+#define DFSDM1_Filter0_BASE   (DFSDM1_BASE + 0x100UL)

+#define DFSDM1_Filter1_BASE   (DFSDM1_BASE + 0x180UL)

+#define DFSDM1_Filter2_BASE   (DFSDM1_BASE + 0x200UL)

+#define DFSDM1_Filter3_BASE   (DFSDM1_BASE + 0x280UL)

+#define DFSDM1_Filter4_BASE   (DFSDM1_BASE + 0x300UL)

+#define DFSDM1_Filter5_BASE   (DFSDM1_BASE + 0x380UL)

+#define DFSDM1_Filter6_BASE   (DFSDM1_BASE + 0x400UL)

+#define DFSDM1_Filter7_BASE   (DFSDM1_BASE + 0x480UL)

+/*!< SRD_APB4PERIPH peripherals */

+#define EXTI_BASE             (SRD_APB4PERIPH_BASE + 0x0000UL)

+#define EXTI_D1_BASE          (EXTI_BASE + 0x0080UL)

+#define SYSCFG_BASE           (SRD_APB4PERIPH_BASE + 0x0400UL)

+#define LPUART1_BASE          (SRD_APB4PERIPH_BASE + 0x0C00UL)

+#define SPI6_BASE             (SRD_APB4PERIPH_BASE + 0x1400UL)

+#define I2C4_BASE             (SRD_APB4PERIPH_BASE + 0x1C00UL)

+#define LPTIM2_BASE           (SRD_APB4PERIPH_BASE + 0x2400UL)

+#define LPTIM3_BASE           (SRD_APB4PERIPH_BASE + 0x2800UL)

+#define DAC2_BASE             (SRD_APB4PERIPH_BASE + 0x3400UL)

+#define COMP12_BASE           (SRD_APB4PERIPH_BASE + 0x3800UL)

+#define COMP1_BASE            (COMP12_BASE + 0x0CUL)

+#define COMP2_BASE            (COMP12_BASE + 0x10UL)

+#define VREFBUF_BASE          (SRD_APB4PERIPH_BASE + 0x3C00UL)

+#define RTC_BASE              (SRD_APB4PERIPH_BASE + 0x4000UL)

+#define TAMP_BASE             (SRD_APB4PERIPH_BASE + 0x4400UL)

+#define IWDG1_BASE            (SRD_APB4PERIPH_BASE + 0x4800UL)

+

+#define DTS_BASE              (SRD_APB4PERIPH_BASE + 0x6800UL)

+

+#define DFSDM2_BASE           (SRD_APB4PERIPH_BASE + 0x6C00UL)

+#define DFSDM2_Channel0_BASE  (DFSDM2_BASE + 0x00UL)

+#define DFSDM2_Channel1_BASE  (DFSDM2_BASE + 0x20UL)

+#define DFSDM2_FLT0_BASE      (DFSDM2_BASE + 0x100UL)

+

+/*!< CD_AHB3PERIPH peripherals */

+

+#define OTFDEC1_BASE          (CD_AHB3PERIPH_BASE + 0xB800UL)

+#define OTFDEC1_REGION1_BASE  (OTFDEC1_BASE + 0x20UL)

+#define OTFDEC1_REGION2_BASE  (OTFDEC1_BASE + 0x50UL)

+#define OTFDEC1_REGION3_BASE  (OTFDEC1_BASE + 0x80UL)

+#define OTFDEC1_REGION4_BASE  (OTFDEC1_BASE + 0xB0UL)

+#define OTFDEC2_BASE          (CD_AHB3PERIPH_BASE + 0xBC00UL)

+#define OTFDEC2_REGION1_BASE  (OTFDEC2_BASE + 0x20UL)

+#define OTFDEC2_REGION2_BASE  (OTFDEC2_BASE + 0x50UL)

+#define OTFDEC2_REGION3_BASE  (OTFDEC2_BASE + 0x80UL)

+#define OTFDEC2_REGION4_BASE  (OTFDEC2_BASE + 0xB0UL)

+#define GFXMMU_BASE           (CD_AHB3PERIPH_BASE + 0xC000UL)

+

+#define BDMA1_Channel0_BASE    (BDMA1_BASE + 0x0008UL)

+#define BDMA1_Channel1_BASE    (BDMA1_BASE + 0x001CUL)

+#define BDMA1_Channel2_BASE    (BDMA1_BASE + 0x0030UL)

+#define BDMA1_Channel3_BASE    (BDMA1_BASE + 0x0044UL)

+#define BDMA1_Channel4_BASE    (BDMA1_BASE + 0x0058UL)

+#define BDMA1_Channel5_BASE    (BDMA1_BASE + 0x006CUL)

+#define BDMA1_Channel6_BASE    (BDMA1_BASE + 0x0080UL)

+#define BDMA1_Channel7_BASE    (BDMA1_BASE + 0x0094UL)

+

+#define BDMA2_Channel0_BASE    (BDMA2_BASE + 0x0008UL)

+#define BDMA2_Channel1_BASE    (BDMA2_BASE + 0x001CUL)

+#define BDMA2_Channel2_BASE    (BDMA2_BASE + 0x0030UL)

+#define BDMA2_Channel3_BASE    (BDMA2_BASE + 0x0044UL)

+#define BDMA2_Channel4_BASE    (BDMA2_BASE + 0x0058UL)

+#define BDMA2_Channel5_BASE    (BDMA2_BASE + 0x006CUL)

+#define BDMA2_Channel6_BASE    (BDMA2_BASE + 0x0080UL)

+#define BDMA2_Channel7_BASE    (BDMA2_BASE + 0x0094UL)

+

+

+#define DMAMUX2_Channel0_BASE    (DMAMUX2_BASE)

+#define DMAMUX2_Channel1_BASE    (DMAMUX2_BASE + 0x0004UL)

+#define DMAMUX2_Channel2_BASE    (DMAMUX2_BASE + 0x0008UL)

+#define DMAMUX2_Channel3_BASE    (DMAMUX2_BASE + 0x000CUL)

+#define DMAMUX2_Channel4_BASE    (DMAMUX2_BASE + 0x0010UL)

+#define DMAMUX2_Channel5_BASE    (DMAMUX2_BASE + 0x0014UL)

+#define DMAMUX2_Channel6_BASE    (DMAMUX2_BASE + 0x0018UL)

+#define DMAMUX2_Channel7_BASE    (DMAMUX2_BASE + 0x001CUL)

+

+#define DMAMUX2_RequestGenerator0_BASE  (DMAMUX2_BASE + 0x0100UL)

+#define DMAMUX2_RequestGenerator1_BASE  (DMAMUX2_BASE + 0x0104UL)

+#define DMAMUX2_RequestGenerator2_BASE  (DMAMUX2_BASE + 0x0108UL)

+#define DMAMUX2_RequestGenerator3_BASE  (DMAMUX2_BASE + 0x010CUL)

+#define DMAMUX2_RequestGenerator4_BASE  (DMAMUX2_BASE + 0x0110UL)

+#define DMAMUX2_RequestGenerator5_BASE  (DMAMUX2_BASE + 0x0114UL)

+#define DMAMUX2_RequestGenerator6_BASE  (DMAMUX2_BASE + 0x0118UL)

+#define DMAMUX2_RequestGenerator7_BASE  (DMAMUX2_BASE + 0x011CUL)

+

+#define DMAMUX2_ChannelStatus_BASE      (DMAMUX2_BASE + 0x0080UL)

+#define DMAMUX2_RequestGenStatus_BASE   (DMAMUX2_BASE + 0x0140UL)

+

+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)

+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)

+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)

+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)

+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)

+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)

+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)

+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)

+

+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)

+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)

+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)

+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)

+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)

+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)

+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)

+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)

+

+

+#define DMAMUX1_Channel0_BASE    (DMAMUX1_BASE)

+#define DMAMUX1_Channel1_BASE    (DMAMUX1_BASE + 0x0004UL)

+#define DMAMUX1_Channel2_BASE    (DMAMUX1_BASE + 0x0008UL)

+#define DMAMUX1_Channel3_BASE    (DMAMUX1_BASE + 0x000CUL)

+#define DMAMUX1_Channel4_BASE    (DMAMUX1_BASE + 0x0010UL)

+#define DMAMUX1_Channel5_BASE    (DMAMUX1_BASE + 0x0014UL)

+#define DMAMUX1_Channel6_BASE    (DMAMUX1_BASE + 0x0018UL)

+#define DMAMUX1_Channel7_BASE    (DMAMUX1_BASE + 0x001CUL)

+#define DMAMUX1_Channel8_BASE    (DMAMUX1_BASE + 0x0020UL)

+#define DMAMUX1_Channel9_BASE    (DMAMUX1_BASE + 0x0024UL)

+#define DMAMUX1_Channel10_BASE   (DMAMUX1_BASE + 0x0028UL)

+#define DMAMUX1_Channel11_BASE   (DMAMUX1_BASE + 0x002CUL)

+#define DMAMUX1_Channel12_BASE   (DMAMUX1_BASE + 0x0030UL)

+#define DMAMUX1_Channel13_BASE   (DMAMUX1_BASE + 0x0034UL)

+#define DMAMUX1_Channel14_BASE   (DMAMUX1_BASE + 0x0038UL)

+#define DMAMUX1_Channel15_BASE   (DMAMUX1_BASE + 0x003CUL)

+

+#define DMAMUX1_RequestGenerator0_BASE  (DMAMUX1_BASE + 0x0100UL)

+#define DMAMUX1_RequestGenerator1_BASE  (DMAMUX1_BASE + 0x0104UL)

+#define DMAMUX1_RequestGenerator2_BASE  (DMAMUX1_BASE + 0x0108UL)

+#define DMAMUX1_RequestGenerator3_BASE  (DMAMUX1_BASE + 0x010CUL)

+#define DMAMUX1_RequestGenerator4_BASE  (DMAMUX1_BASE + 0x0110UL)

+#define DMAMUX1_RequestGenerator5_BASE  (DMAMUX1_BASE + 0x0114UL)

+#define DMAMUX1_RequestGenerator6_BASE  (DMAMUX1_BASE + 0x0118UL)

+#define DMAMUX1_RequestGenerator7_BASE  (DMAMUX1_BASE + 0x011CUL)

+

+#define DMAMUX1_ChannelStatus_BASE      (DMAMUX1_BASE + 0x0080UL)

+#define DMAMUX1_RequestGenStatus_BASE   (DMAMUX1_BASE + 0x0140UL)

+

+/*!< FMC Banks registers base  address */

+#define FMC_Bank1_R_BASE      (FMC_R_BASE + 0x0000UL)

+#define FMC_Bank1E_R_BASE     (FMC_R_BASE + 0x0104UL)

+#define FMC_Bank2_R_BASE      (FMC_R_BASE + 0x0060UL)

+#define FMC_Bank3_R_BASE      (FMC_R_BASE + 0x0080UL)

+#define FMC_Bank5_6_R_BASE    (FMC_R_BASE + 0x0140UL)

+

+/* Debug MCU registers base address */

+#define DBGMCU_BASE           (0x5C001000UL)

+

+#define MDMA_Channel0_BASE    (MDMA_BASE + 0x00000040UL)

+#define MDMA_Channel1_BASE    (MDMA_BASE + 0x00000080UL)

+#define MDMA_Channel2_BASE    (MDMA_BASE + 0x000000C0UL)

+#define MDMA_Channel3_BASE    (MDMA_BASE + 0x00000100UL)

+#define MDMA_Channel4_BASE    (MDMA_BASE + 0x00000140UL)

+#define MDMA_Channel5_BASE    (MDMA_BASE + 0x00000180UL)

+#define MDMA_Channel6_BASE    (MDMA_BASE + 0x000001C0UL)

+#define MDMA_Channel7_BASE    (MDMA_BASE + 0x00000200UL)

+#define MDMA_Channel8_BASE    (MDMA_BASE + 0x00000240UL)

+#define MDMA_Channel9_BASE    (MDMA_BASE + 0x00000280UL)

+#define MDMA_Channel10_BASE   (MDMA_BASE + 0x000002C0UL)

+#define MDMA_Channel11_BASE   (MDMA_BASE + 0x00000300UL)

+#define MDMA_Channel12_BASE   (MDMA_BASE + 0x00000340UL)

+#define MDMA_Channel13_BASE   (MDMA_BASE + 0x00000380UL)

+#define MDMA_Channel14_BASE   (MDMA_BASE + 0x000003C0UL)

+#define MDMA_Channel15_BASE   (MDMA_BASE + 0x00000400UL)

+#define MDMA_Channel16_BASE   (MDMA_BASE + 0x00000440UL)

+

+/* GFXMMU virtual buffers base address */

+#define GFXMMU_VIRTUAL_BUFFERS_BASE  (0x25000000UL)

+#define GFXMMU_VIRTUAL_BUFFER0_BASE  (GFXMMU_VIRTUAL_BUFFERS_BASE)

+#define GFXMMU_VIRTUAL_BUFFER1_BASE  (GFXMMU_VIRTUAL_BUFFERS_BASE + 0x400000UL)

+#define GFXMMU_VIRTUAL_BUFFER2_BASE  (GFXMMU_VIRTUAL_BUFFERS_BASE + 0x800000UL)

+#define GFXMMU_VIRTUAL_BUFFER3_BASE  (GFXMMU_VIRTUAL_BUFFERS_BASE + 0xC00000UL)

+

+#define RAMECC_Monitor1_BASE (RAMECC_BASE + 0x20UL)

+#define RAMECC_Monitor2_BASE (RAMECC_BASE + 0x40UL)

+#define RAMECC_Monitor3_BASE (RAMECC_BASE + 0x60UL)

+

+/**

+  * @}

+  */

+

+/** @addtogroup Peripheral_declaration

+  * @{

+  */

+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)

+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)

+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)

+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)

+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)

+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)

+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)

+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)

+#define VREFBUF             ((VREFBUF_TypeDef *) VREFBUF_BASE)

+#define RTC                 ((RTC_TypeDef *) RTC_BASE)

+#define TAMP                ((TAMP_TypeDef *) TAMP_BASE)

+#define WWDG1               ((WWDG_TypeDef *) WWDG1_BASE)

+

+

+#define IWDG1               ((IWDG_TypeDef *) IWDG1_BASE)

+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)

+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)

+#define SPI4                ((SPI_TypeDef *) SPI4_BASE)

+#define SPI5                ((SPI_TypeDef *) SPI5_BASE)

+#define SPI6                ((SPI_TypeDef *) SPI6_BASE)

+#define USART2              ((USART_TypeDef *) USART2_BASE)

+#define USART3              ((USART_TypeDef *) USART3_BASE)

+#define USART6              ((USART_TypeDef *) USART6_BASE)

+#define USART10             ((USART_TypeDef *) USART10_BASE)

+#define UART7               ((USART_TypeDef *) UART7_BASE)

+#define UART8               ((USART_TypeDef *) UART8_BASE)

+#define UART9               ((USART_TypeDef *) UART9_BASE)

+#define CRS                 ((CRS_TypeDef *) CRS_BASE)

+#define UART4               ((USART_TypeDef *) UART4_BASE)

+#define UART5               ((USART_TypeDef *) UART5_BASE)

+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)

+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)

+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)

+#define I2C4                ((I2C_TypeDef *) I2C4_BASE)

+#define FDCAN1              ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)

+#define FDCAN2              ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)

+#define FDCAN_CCU           ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)

+#define CEC                 ((CEC_TypeDef *) CEC_BASE)

+#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)

+#define PWR                 ((PWR_TypeDef *) PWR_BASE)

+#define DAC1                ((DAC_TypeDef *) DAC1_BASE)

+#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)

+#define SWPMI1              ((SWPMI_TypeDef *) SWPMI1_BASE)

+#define LPTIM2              ((LPTIM_TypeDef *) LPTIM2_BASE)

+#define LPTIM3              ((LPTIM_TypeDef *) LPTIM3_BASE)

+#define DTS                 ((DTS_TypeDef *) DTS_BASE)

+

+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)

+#define COMP12              ((COMPOPT_TypeDef *) COMP12_BASE)

+#define COMP1               ((COMP_TypeDef *) COMP1_BASE)

+#define COMP2               ((COMP_TypeDef *) COMP2_BASE)

+#define COMP12_COMMON       ((COMP_Common_TypeDef *) COMP2_BASE)

+#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)

+#define OPAMP1              ((OPAMP_TypeDef *) OPAMP1_BASE)

+#define OPAMP2              ((OPAMP_TypeDef *) OPAMP2_BASE)

+

+

+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)

+#define EXTI_D1             ((EXTI_Core_TypeDef *) EXTI_D1_BASE)

+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)

+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)

+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)

+#define USART1              ((USART_TypeDef *) USART1_BASE)

+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)

+#define TIM15               ((TIM_TypeDef *) TIM15_BASE)

+#define TIM16               ((TIM_TypeDef *) TIM16_BASE)

+#define TIM17               ((TIM_TypeDef *) TIM17_BASE)

+#define SAI1                ((SAI_TypeDef *) SAI1_BASE)

+#define SAI1_Block_A        ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)

+#define SAI1_Block_B        ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)

+#define SAI2                ((SAI_TypeDef *) SAI2_BASE)

+#define SAI2_Block_A        ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)

+#define SAI2_Block_B        ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)

+

+#define SPDIFRX             ((SPDIFRX_TypeDef *) SPDIFRX_BASE)

+#define DFSDM1_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)

+#define DFSDM1_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)

+#define DFSDM1_Channel2     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)

+#define DFSDM1_Channel3     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)

+#define DFSDM1_Channel4     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)

+#define DFSDM1_Channel5     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)

+#define DFSDM1_Channel6     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)

+#define DFSDM1_Channel7     ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)

+#define DFSDM1_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)

+#define DFSDM1_Filter1      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)

+#define DFSDM1_Filter2      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)

+#define DFSDM1_Filter3      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)

+#define DFSDM1_Filter4      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter4_BASE)

+#define DFSDM1_Filter5      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter5_BASE)

+#define DFSDM1_Filter6      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter6_BASE)

+#define DFSDM1_Filter7      ((DFSDM_Filter_TypeDef *) DFSDM1_Filter7_BASE)

+#define DFSDM2_Channel0     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel0_BASE)

+#define DFSDM2_Channel1     ((DFSDM_Channel_TypeDef *) DFSDM2_Channel1_BASE)

+#define DFSDM2_Filter0      ((DFSDM_Filter_TypeDef *) DFSDM2_FLT0_BASE)

+#define DMA2D               ((DMA2D_TypeDef *) DMA2D_BASE)

+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)

+#define PSSI                ((PSSI_TypeDef *) PSSI_BASE)

+#define RCC                 ((RCC_TypeDef *) RCC_BASE)

+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)

+#define CRC                 ((CRC_TypeDef *) CRC_BASE)

+

+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)

+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)

+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)

+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)

+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)

+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)

+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)

+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)

+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)

+#define GPIOJ               ((GPIO_TypeDef *) GPIOJ_BASE)

+#define GPIOK               ((GPIO_TypeDef *) GPIOK_BASE)

+

+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)

+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)

+#define ADC12_COMMON        ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)

+

+#define CRYP                ((CRYP_TypeDef *) CRYP_BASE)

+#define HASH                ((HASH_TypeDef *) HASH_BASE)

+#define HASH_DIGEST         ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)

+#define RNG                 ((RNG_TypeDef *) RNG_BASE)

+#define SDMMC2              ((SDMMC_TypeDef *) SDMMC2_BASE)

+#define DLYB_SDMMC2         ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)

+

+#define BDMA1                ((BDMA_TypeDef *) BDMA1_BASE)

+#define BDMA1_Channel0       ((BDMA_Channel_TypeDef *) BDMA1_Channel0_BASE)

+#define BDMA1_Channel1       ((BDMA_Channel_TypeDef *) BDMA1_Channel1_BASE)

+#define BDMA1_Channel2       ((BDMA_Channel_TypeDef *) BDMA1_Channel2_BASE)

+#define BDMA1_Channel3       ((BDMA_Channel_TypeDef *) BDMA1_Channel3_BASE)

+#define BDMA1_Channel4       ((BDMA_Channel_TypeDef *) BDMA1_Channel4_BASE)

+#define BDMA1_Channel5       ((BDMA_Channel_TypeDef *) BDMA1_Channel5_BASE)

+#define BDMA1_Channel6       ((BDMA_Channel_TypeDef *) BDMA1_Channel6_BASE)

+#define BDMA1_Channel7       ((BDMA_Channel_TypeDef *) BDMA1_Channel7_BASE)

+

+#define BDMA2                ((BDMA_TypeDef *) BDMA2_BASE)

+#define BDMA2_Channel0       ((BDMA_Channel_TypeDef *) BDMA2_Channel0_BASE)

+#define BDMA2_Channel1       ((BDMA_Channel_TypeDef *) BDMA2_Channel1_BASE)

+#define BDMA2_Channel2       ((BDMA_Channel_TypeDef *) BDMA2_Channel2_BASE)

+#define BDMA2_Channel3       ((BDMA_Channel_TypeDef *) BDMA2_Channel3_BASE)

+#define BDMA2_Channel4       ((BDMA_Channel_TypeDef *) BDMA2_Channel4_BASE)

+#define BDMA2_Channel5       ((BDMA_Channel_TypeDef *) BDMA2_Channel5_BASE)

+#define BDMA2_Channel6       ((BDMA_Channel_TypeDef *) BDMA2_Channel6_BASE)

+#define BDMA2_Channel7       ((BDMA_Channel_TypeDef *) BDMA2_Channel7_BASE)

+

+#define RAMECC               ((RAMECC_TypeDef *)RAMECC_BASE)

+#define RAMECC_Monitor1      ((RAMECC_MonitorTypeDef *)RAMECC_Monitor1_BASE)

+#define RAMECC_Monitor2      ((RAMECC_MonitorTypeDef *)RAMECC_Monitor2_BASE)

+#define RAMECC_Monitor3      ((RAMECC_MonitorTypeDef *)RAMECC_Monitor3_BASE)

+

+#define DMAMUX2                ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)

+#define DMAMUX2_Channel0       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)

+#define DMAMUX2_Channel1       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)

+#define DMAMUX2_Channel2       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)

+#define DMAMUX2_Channel3       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)

+#define DMAMUX2_Channel4       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)

+#define DMAMUX2_Channel5       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)

+#define DMAMUX2_Channel6       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)

+#define DMAMUX2_Channel7       ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)

+

+

+#define DMAMUX2_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)

+#define DMAMUX2_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)

+#define DMAMUX2_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)

+#define DMAMUX2_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)

+#define DMAMUX2_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)

+#define DMAMUX2_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)

+#define DMAMUX2_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)

+#define DMAMUX2_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)

+

+#define DMAMUX2_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)

+#define DMAMUX2_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)

+

+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)

+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)

+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)

+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)

+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)

+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)

+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)

+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)

+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)

+

+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)

+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)

+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)

+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)

+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)

+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)

+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)

+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)

+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)

+

+

+#define DMAMUX1              ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)

+#define DMAMUX1_Channel0     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)

+#define DMAMUX1_Channel1     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)

+#define DMAMUX1_Channel2     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)

+#define DMAMUX1_Channel3     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)

+#define DMAMUX1_Channel4     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)

+#define DMAMUX1_Channel5     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)

+#define DMAMUX1_Channel6     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)

+#define DMAMUX1_Channel7     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)

+#define DMAMUX1_Channel8     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)

+#define DMAMUX1_Channel9     ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)

+#define DMAMUX1_Channel10    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)

+#define DMAMUX1_Channel11    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)

+#define DMAMUX1_Channel12    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)

+#define DMAMUX1_Channel13    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)

+#define DMAMUX1_Channel14    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)

+#define DMAMUX1_Channel15    ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)

+

+#define DMAMUX1_RequestGenerator0  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)

+#define DMAMUX1_RequestGenerator1  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)

+#define DMAMUX1_RequestGenerator2  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)

+#define DMAMUX1_RequestGenerator3  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)

+#define DMAMUX1_RequestGenerator4  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)

+#define DMAMUX1_RequestGenerator5  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)

+#define DMAMUX1_RequestGenerator6  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)

+#define DMAMUX1_RequestGenerator7  ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)

+

+#define DMAMUX1_ChannelStatus      ((DMAMUX_ChannelStatus_TypeDef *)    DMAMUX1_ChannelStatus_BASE)

+#define DMAMUX1_RequestGenStatus   ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)

+

+

+#define FMC_Bank1_R           ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)

+#define FMC_Bank1E_R          ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)

+#define FMC_Bank2_R           ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)

+#define FMC_Bank3_R           ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)

+#define FMC_Bank5_6_R         ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)

+

+#define DAC2                ((DAC_TypeDef *) DAC2_BASE)

+#define OCTOSPI1            ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)

+#define DLYB_OCTOSPI1       ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE)

+#define OCTOSPI2            ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)

+#define DLYB_OCTOSPI2       ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE)

+#define OCTOSPIM            ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)

+

+#define OTFDEC1               ((OTFDEC_TypeDef *) OTFDEC1_BASE)

+#define OTFDEC1_REGION1       ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE)

+#define OTFDEC1_REGION2       ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE)

+#define OTFDEC1_REGION3       ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE)

+#define OTFDEC1_REGION4       ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE)

+

+#define OTFDEC2               ((OTFDEC_TypeDef *) OTFDEC2_BASE)

+#define OTFDEC2_REGION1       ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE)

+#define OTFDEC2_REGION2       ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE)

+#define OTFDEC2_REGION3       ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE)

+#define OTFDEC2_REGION4       ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE)

+#define GFXMMU              ((GFXMMU_TypeDef *) GFXMMU_BASE)

+

+#define SDMMC1                ((SDMMC_TypeDef *) SDMMC1_BASE)

+#define DLYB_SDMMC1           ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)

+

+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)

+

+#define JPEG                ((JPEG_TypeDef *) JPGDEC_BASE)

+#define HSEM                ((HSEM_TypeDef *) HSEM_BASE)

+#define HSEM_COMMON         ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))

+

+#define LTDC                ((LTDC_TypeDef *)LTDC_BASE)

+#define LTDC_Layer1         ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)

+#define LTDC_Layer2         ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)

+

+#define MDIOS               ((MDIOS_TypeDef *) MDIOS_BASE)

+

+#define MDMA                ((MDMA_TypeDef *)MDMA_BASE)

+#define MDMA_Channel0       ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)

+#define MDMA_Channel1       ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)

+#define MDMA_Channel2       ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)

+#define MDMA_Channel3       ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)

+#define MDMA_Channel4       ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)

+#define MDMA_Channel5       ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)

+#define MDMA_Channel6       ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)

+#define MDMA_Channel7       ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)

+#define MDMA_Channel8       ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)

+#define MDMA_Channel9       ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)

+#define MDMA_Channel10      ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)

+#define MDMA_Channel11      ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)

+#define MDMA_Channel12      ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)

+#define MDMA_Channel13      ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)

+#define MDMA_Channel14      ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)

+#define MDMA_Channel15      ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)

+

+

+#define USB1_OTG_HS         ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)

+

+/* Legacy defines */

+#define USB_OTG_HS                   USB1_OTG_HS

+#define USB_OTG_HS_PERIPH_BASE       USB1_OTG_HS_PERIPH_BASE

+

+/**

+  * @}

+  */

+

+/** @addtogroup Exported_constants

+  * @{

+  */

+

+  /** @addtogroup Peripheral_Registers_Bits_Definition

+  * @{

+  */

+

+/******************************************************************************/

+/*                         Peripheral Registers_Bits_Definition               */

+/******************************************************************************/

+

+/******************************************************************************/

+/*                                                                            */

+/*                        Analog to Digital Converter                         */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  ADC VERSION  ********************************/

+#define ADC_VER_V5_3

+/********************  Bit definition for ADC_ISR register  ********************/

+#define ADC_ISR_ADRDY_Pos                 (0U)

+#define ADC_ISR_ADRDY_Msk                 (0x1UL << ADC_ISR_ADRDY_Pos)         /*!< 0x00000001 */

+#define ADC_ISR_ADRDY                     ADC_ISR_ADRDY_Msk                    /*!< ADC Ready (ADRDY) flag  */

+#define ADC_ISR_EOSMP_Pos                 (1U)

+#define ADC_ISR_EOSMP_Msk                 (0x1UL << ADC_ISR_EOSMP_Pos)         /*!< 0x00000002 */

+#define ADC_ISR_EOSMP                     ADC_ISR_EOSMP_Msk                    /*!< ADC End of Sampling flag */

+#define ADC_ISR_EOC_Pos                   (2U)

+#define ADC_ISR_EOC_Msk                   (0x1UL << ADC_ISR_EOC_Pos)           /*!< 0x00000004 */

+#define ADC_ISR_EOC                       ADC_ISR_EOC_Msk                      /*!< ADC End of Regular Conversion flag */

+#define ADC_ISR_EOS_Pos                   (3U)

+#define ADC_ISR_EOS_Msk                   (0x1UL << ADC_ISR_EOS_Pos)           /*!< 0x00000008 */

+#define ADC_ISR_EOS                       ADC_ISR_EOS_Msk                      /*!< ADC End of Regular sequence of Conversions flag */

+#define ADC_ISR_OVR_Pos                   (4U)

+#define ADC_ISR_OVR_Msk                   (0x1UL << ADC_ISR_OVR_Pos)           /*!< 0x00000010 */

+#define ADC_ISR_OVR                       ADC_ISR_OVR_Msk                      /*!< ADC overrun flag */

+#define ADC_ISR_JEOC_Pos                  (5U)

+#define ADC_ISR_JEOC_Msk                  (0x1UL << ADC_ISR_JEOC_Pos)          /*!< 0x00000020 */

+#define ADC_ISR_JEOC                      ADC_ISR_JEOC_Msk                     /*!< ADC End of Injected Conversion flag */

+#define ADC_ISR_JEOS_Pos                  (6U)

+#define ADC_ISR_JEOS_Msk                  (0x1UL << ADC_ISR_JEOS_Pos)          /*!< 0x00000040 */

+#define ADC_ISR_JEOS                      ADC_ISR_JEOS_Msk                     /*!< ADC End of Injected sequence of Conversions flag */

+#define ADC_ISR_AWD1_Pos                  (7U)

+#define ADC_ISR_AWD1_Msk                  (0x1UL << ADC_ISR_AWD1_Pos)          /*!< 0x00000080 */

+#define ADC_ISR_AWD1                      ADC_ISR_AWD1_Msk                     /*!< ADC Analog watchdog 1 flag */

+#define ADC_ISR_AWD2_Pos                  (8U)

+#define ADC_ISR_AWD2_Msk                  (0x1UL << ADC_ISR_AWD2_Pos)          /*!< 0x00000100 */

+#define ADC_ISR_AWD2                      ADC_ISR_AWD2_Msk                     /*!< ADC Analog watchdog 2 flag */

+#define ADC_ISR_AWD3_Pos                  (9U)

+#define ADC_ISR_AWD3_Msk                  (0x1UL << ADC_ISR_AWD3_Pos)          /*!< 0x00000200 */

+#define ADC_ISR_AWD3                      ADC_ISR_AWD3_Msk                     /*!< ADC Analog watchdog 3 flag */

+#define ADC_ISR_JQOVF_Pos                 (10U)

+#define ADC_ISR_JQOVF_Msk                 (0x1UL << ADC_ISR_JQOVF_Pos)         /*!< 0x00000400 */

+#define ADC_ISR_JQOVF                     ADC_ISR_JQOVF_Msk                    /*!< ADC Injected Context Queue Overflow flag */

+

+/********************  Bit definition for ADC_IER register  ********************/

+#define ADC_IER_ADRDYIE_Pos               (0U)

+#define ADC_IER_ADRDYIE_Msk               (0x1UL << ADC_IER_ADRDYIE_Pos)       /*!< 0x00000001 */

+#define ADC_IER_ADRDYIE                   ADC_IER_ADRDYIE_Msk                  /*!< ADC Ready (ADRDY) interrupt source */

+#define ADC_IER_EOSMPIE_Pos               (1U)

+#define ADC_IER_EOSMPIE_Msk               (0x1UL << ADC_IER_EOSMPIE_Pos)       /*!< 0x00000002 */

+#define ADC_IER_EOSMPIE                   ADC_IER_EOSMPIE_Msk                  /*!< ADC End of Sampling interrupt source */

+#define ADC_IER_EOCIE_Pos                 (2U)

+#define ADC_IER_EOCIE_Msk                 (0x1UL << ADC_IER_EOCIE_Pos)         /*!< 0x00000004 */

+#define ADC_IER_EOCIE                     ADC_IER_EOCIE_Msk                    /*!< ADC End of Regular Conversion interrupt source */

+#define ADC_IER_EOSIE_Pos                 (3U)

+#define ADC_IER_EOSIE_Msk                 (0x1UL << ADC_IER_EOSIE_Pos)         /*!< 0x00000008 */

+#define ADC_IER_EOSIE                     ADC_IER_EOSIE_Msk                    /*!< ADC End of Regular sequence of Conversions interrupt source */

+#define ADC_IER_OVRIE_Pos                 (4U)

+#define ADC_IER_OVRIE_Msk                 (0x1UL << ADC_IER_OVRIE_Pos)         /*!< 0x00000010 */

+#define ADC_IER_OVRIE                     ADC_IER_OVRIE_Msk                    /*!< ADC overrun interrupt source */

+#define ADC_IER_JEOCIE_Pos                (5U)

+#define ADC_IER_JEOCIE_Msk                (0x1UL << ADC_IER_JEOCIE_Pos)        /*!< 0x00000020 */

+#define ADC_IER_JEOCIE                    ADC_IER_JEOCIE_Msk                   /*!< ADC End of Injected Conversion interrupt source */

+#define ADC_IER_JEOSIE_Pos                (6U)

+#define ADC_IER_JEOSIE_Msk                (0x1UL << ADC_IER_JEOSIE_Pos)        /*!< 0x00000040 */

+#define ADC_IER_JEOSIE                    ADC_IER_JEOSIE_Msk                   /*!< ADC End of Injected sequence of Conversions interrupt source */

+#define ADC_IER_AWD1IE_Pos                (7U)

+#define ADC_IER_AWD1IE_Msk                (0x1UL << ADC_IER_AWD1IE_Pos)        /*!< 0x00000080 */

+#define ADC_IER_AWD1IE                    ADC_IER_AWD1IE_Msk                   /*!< ADC Analog watchdog 1 interrupt source */

+#define ADC_IER_AWD2IE_Pos                (8U)

+#define ADC_IER_AWD2IE_Msk                (0x1UL << ADC_IER_AWD2IE_Pos)        /*!< 0x00000100 */

+#define ADC_IER_AWD2IE                    ADC_IER_AWD2IE_Msk                   /*!< ADC Analog watchdog 2 interrupt source */

+#define ADC_IER_AWD3IE_Pos                (9U)

+#define ADC_IER_AWD3IE_Msk                (0x1UL << ADC_IER_AWD3IE_Pos)        /*!< 0x00000200 */

+#define ADC_IER_AWD3IE                    ADC_IER_AWD3IE_Msk                   /*!< ADC Analog watchdog 3 interrupt source */

+#define ADC_IER_JQOVFIE_Pos               (10U)

+#define ADC_IER_JQOVFIE_Msk               (0x1UL << ADC_IER_JQOVFIE_Pos)       /*!< 0x00000400 */

+#define ADC_IER_JQOVFIE                   ADC_IER_JQOVFIE_Msk                  /*!< ADC Injected Context Queue Overflow interrupt source */

+

+/********************  Bit definition for ADC_CR register  ********************/

+#define ADC_CR_ADEN_Pos                   (0U)

+#define ADC_CR_ADEN_Msk                   (0x1UL << ADC_CR_ADEN_Pos)           /*!< 0x00000001 */

+#define ADC_CR_ADEN                       ADC_CR_ADEN_Msk                      /*!< ADC Enable control */

+#define ADC_CR_ADDIS_Pos                  (1U)

+#define ADC_CR_ADDIS_Msk                  (0x1UL << ADC_CR_ADDIS_Pos)          /*!< 0x00000002 */

+#define ADC_CR_ADDIS                      ADC_CR_ADDIS_Msk                     /*!< ADC Disable command */

+#define ADC_CR_ADSTART_Pos                (2U)

+#define ADC_CR_ADSTART_Msk                (0x1UL << ADC_CR_ADSTART_Pos)        /*!< 0x00000004 */

+#define ADC_CR_ADSTART                    ADC_CR_ADSTART_Msk                   /*!< ADC Start of Regular conversion */

+#define ADC_CR_JADSTART_Pos               (3U)

+#define ADC_CR_JADSTART_Msk               (0x1UL << ADC_CR_JADSTART_Pos)       /*!< 0x00000008 */

+#define ADC_CR_JADSTART                   ADC_CR_JADSTART_Msk                  /*!< ADC Start of injected conversion */

+#define ADC_CR_ADSTP_Pos                  (4U)

+#define ADC_CR_ADSTP_Msk                  (0x1UL << ADC_CR_ADSTP_Pos)          /*!< 0x00000010 */

+#define ADC_CR_ADSTP                      ADC_CR_ADSTP_Msk                     /*!< ADC Stop of Regular conversion */

+#define ADC_CR_JADSTP_Pos                 (5U)

+#define ADC_CR_JADSTP_Msk                 (0x1UL << ADC_CR_JADSTP_Pos)         /*!< 0x00000020 */

+#define ADC_CR_JADSTP                     ADC_CR_JADSTP_Msk                    /*!< ADC Stop of injected conversion */

+#define ADC_CR_BOOST_Pos                  (8U)

+#define ADC_CR_BOOST_Msk                  (0x3UL << ADC_CR_BOOST_Pos)          /*!< 0x00000300 */

+#define ADC_CR_BOOST                      ADC_CR_BOOST_Msk                     /*!< ADC Boost Mode configuration */

+#define ADC_CR_BOOST_0                    (0x1UL << ADC_CR_BOOST_Pos)           /*!< 0x00000100 */

+#define ADC_CR_BOOST_1                    (0x2UL << ADC_CR_BOOST_Pos)           /*!< 0x00000200 */

+#define ADC_CR_ADCALLIN_Pos               (16U)

+#define ADC_CR_ADCALLIN_Msk               (0x1UL << ADC_CR_ADCALLIN_Pos)       /*!< 0x00010000 */

+#define ADC_CR_ADCALLIN                   ADC_CR_ADCALLIN_Msk                  /*!< ADC Linearity calibration */

+#define ADC_CR_LINCALRDYW1_Pos            (22U)

+#define ADC_CR_LINCALRDYW1_Msk            (0x1UL << ADC_CR_LINCALRDYW1_Pos)    /*!< 0x00400000 */

+#define ADC_CR_LINCALRDYW1                ADC_CR_LINCALRDYW1_Msk               /*!< ADC Linearity calibration ready Word 1 */

+#define ADC_CR_LINCALRDYW2_Pos            (23U)

+#define ADC_CR_LINCALRDYW2_Msk            (0x1UL << ADC_CR_LINCALRDYW2_Pos)    /*!< 0x00800000 */

+#define ADC_CR_LINCALRDYW2                ADC_CR_LINCALRDYW2_Msk               /*!< ADC Linearity calibration ready Word 2 */

+#define ADC_CR_LINCALRDYW3_Pos            (24U)

+#define ADC_CR_LINCALRDYW3_Msk            (0x1UL << ADC_CR_LINCALRDYW3_Pos)    /*!< 0x01000000 */

+#define ADC_CR_LINCALRDYW3                ADC_CR_LINCALRDYW3_Msk               /*!< ADC Linearity calibration ready Word 3 */

+#define ADC_CR_LINCALRDYW4_Pos            (25U)

+#define ADC_CR_LINCALRDYW4_Msk            (0x1UL << ADC_CR_LINCALRDYW4_Pos)    /*!< 0x02000000 */

+#define ADC_CR_LINCALRDYW4                ADC_CR_LINCALRDYW4_Msk               /*!< ADC Linearity calibration ready Word 4 */

+#define ADC_CR_LINCALRDYW5_Pos            (26U)

+#define ADC_CR_LINCALRDYW5_Msk            (0x1UL << ADC_CR_LINCALRDYW5_Pos)    /*!< 0x04000000 */

+#define ADC_CR_LINCALRDYW5                ADC_CR_LINCALRDYW5_Msk               /*!< ADC Linearity calibration ready Word 5 */

+#define ADC_CR_LINCALRDYW6_Pos            (27U)

+#define ADC_CR_LINCALRDYW6_Msk            (0x1UL << ADC_CR_LINCALRDYW6_Pos)    /*!< 0x08000000 */

+#define ADC_CR_LINCALRDYW6                ADC_CR_LINCALRDYW6_Msk               /*!< ADC Linearity calibration ready Word 6 */

+#define ADC_CR_ADVREGEN_Pos               (28U)

+#define ADC_CR_ADVREGEN_Msk               (0x1UL << ADC_CR_ADVREGEN_Pos)       /*!< 0x10000000 */

+#define ADC_CR_ADVREGEN                   ADC_CR_ADVREGEN_Msk                  /*!< ADC Voltage regulator Enable */

+#define ADC_CR_DEEPPWD_Pos                (29U)

+#define ADC_CR_DEEPPWD_Msk                (0x1UL << ADC_CR_DEEPPWD_Pos)        /*!< 0x20000000 */

+#define ADC_CR_DEEPPWD                    ADC_CR_DEEPPWD_Msk                   /*!< ADC Deep power down Enable */

+#define ADC_CR_ADCALDIF_Pos               (30U)

+#define ADC_CR_ADCALDIF_Msk               (0x1UL << ADC_CR_ADCALDIF_Pos)       /*!< 0x40000000 */

+#define ADC_CR_ADCALDIF                   ADC_CR_ADCALDIF_Msk                  /*!< ADC Differential Mode for calibration */

+#define ADC_CR_ADCAL_Pos                  (31U)

+#define ADC_CR_ADCAL_Msk                  (0x1UL << ADC_CR_ADCAL_Pos)          /*!< 0x80000000 */

+#define ADC_CR_ADCAL                      ADC_CR_ADCAL_Msk                     /*!< ADC Calibration */

+

+/********************  Bit definition for ADC_CFGR register  ********************/

+#define ADC_CFGR_DMNGT_Pos                (0U)

+#define ADC_CFGR_DMNGT_Msk                (0x3UL << ADC_CFGR_DMNGT_Pos)        /*!< 0x00000003 */

+#define ADC_CFGR_DMNGT                    ADC_CFGR_DMNGT_Msk                   /*!< ADC Data Management configuration */

+#define ADC_CFGR_DMNGT_0                  (0x1UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000001 */

+#define ADC_CFGR_DMNGT_1                  (0x2UL << ADC_CFGR_DMNGT_Pos)         /*!< 0x00000002 */

+

+#define ADC_CFGR_RES_Pos                  (2U)

+#define ADC_CFGR_RES_Msk                  (0x7UL << ADC_CFGR_RES_Pos)          /*!< 0x0000001C */

+#define ADC_CFGR_RES                      ADC_CFGR_RES_Msk                     /*!< ADC Data resolution */

+#define ADC_CFGR_RES_0                    (0x1UL << ADC_CFGR_RES_Pos)           /*!< 0x00000004 */

+#define ADC_CFGR_RES_1                    (0x2UL << ADC_CFGR_RES_Pos)           /*!< 0x00000008 */

+#define ADC_CFGR_RES_2                    (0x4UL << ADC_CFGR_RES_Pos)           /*!< 0x00000010 */

+

+#define ADC_CFGR_EXTSEL_Pos               (5U)

+#define ADC_CFGR_EXTSEL_Msk               (0x1FUL << ADC_CFGR_EXTSEL_Pos)      /*!< 0x000003E0 */

+#define ADC_CFGR_EXTSEL                   ADC_CFGR_EXTSEL_Msk                  /*!< ADC External trigger selection for regular group */

+#define ADC_CFGR_EXTSEL_0                 (0x01UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000020 */

+#define ADC_CFGR_EXTSEL_1                 (0x02UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000040 */

+#define ADC_CFGR_EXTSEL_2                 (0x04UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000080 */

+#define ADC_CFGR_EXTSEL_3                 (0x08UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000100 */

+#define ADC_CFGR_EXTSEL_4                 (0x10UL << ADC_CFGR_EXTSEL_Pos)       /*!< 0x00000200 */

+

+#define ADC_CFGR_EXTEN_Pos                (10U)

+#define ADC_CFGR_EXTEN_Msk                (0x3UL << ADC_CFGR_EXTEN_Pos)        /*!< 0x00000C00 */

+#define ADC_CFGR_EXTEN                    ADC_CFGR_EXTEN_Msk                   /*!< ADC External trigger enable and polarity selection for regular channels */

+#define ADC_CFGR_EXTEN_0                  (0x1UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000400 */

+#define ADC_CFGR_EXTEN_1                  (0x2UL << ADC_CFGR_EXTEN_Pos)         /*!< 0x00000800 */

+

+#define ADC_CFGR_OVRMOD_Pos               (12U)

+#define ADC_CFGR_OVRMOD_Msk               (0x1UL << ADC_CFGR_OVRMOD_Pos)       /*!< 0x00001000 */

+#define ADC_CFGR_OVRMOD                   ADC_CFGR_OVRMOD_Msk                  /*!< ADC overrun mode */

+#define ADC_CFGR_CONT_Pos                 (13U)

+#define ADC_CFGR_CONT_Msk                 (0x1UL << ADC_CFGR_CONT_Pos)         /*!< 0x00002000 */

+#define ADC_CFGR_CONT                     ADC_CFGR_CONT_Msk                    /*!< ADC Single/continuous conversion mode for regular conversion */

+#define ADC_CFGR_AUTDLY_Pos               (14U)

+#define ADC_CFGR_AUTDLY_Msk               (0x1UL << ADC_CFGR_AUTDLY_Pos)       /*!< 0x00004000 */

+#define ADC_CFGR_AUTDLY                   ADC_CFGR_AUTDLY_Msk                  /*!< ADC Delayed conversion mode */

+

+#define ADC_CFGR_DISCEN_Pos               (16U)

+#define ADC_CFGR_DISCEN_Msk               (0x1UL << ADC_CFGR_DISCEN_Pos)       /*!< 0x00010000 */

+#define ADC_CFGR_DISCEN                   ADC_CFGR_DISCEN_Msk                  /*!< ADC Discontinuous mode for regular channels */

+

+#define ADC_CFGR_DISCNUM_Pos              (17U)

+#define ADC_CFGR_DISCNUM_Msk              (0x7UL << ADC_CFGR_DISCNUM_Pos)      /*!< 0x000E0000 */

+#define ADC_CFGR_DISCNUM                  ADC_CFGR_DISCNUM_Msk                 /*!< ADC Discontinuous mode channel count */

+#define ADC_CFGR_DISCNUM_0                (0x1UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00020000 */

+#define ADC_CFGR_DISCNUM_1                (0x2UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00040000 */

+#define ADC_CFGR_DISCNUM_2                (0x4UL << ADC_CFGR_DISCNUM_Pos)       /*!< 0x00080000 */

+

+#define ADC_CFGR_JDISCEN_Pos              (20U)

+#define ADC_CFGR_JDISCEN_Msk              (0x1UL << ADC_CFGR_JDISCEN_Pos)      /*!< 0x00100000 */

+#define ADC_CFGR_JDISCEN                  ADC_CFGR_JDISCEN_Msk                 /*!< ADC Discontinuous mode on injected channels */

+#define ADC_CFGR_JQM_Pos                  (21U)

+#define ADC_CFGR_JQM_Msk                  (0x1UL << ADC_CFGR_JQM_Pos)          /*!< 0x00200000 */

+#define ADC_CFGR_JQM                      ADC_CFGR_JQM_Msk                     /*!< ADC JSQR Queue mode */

+#define ADC_CFGR_AWD1SGL_Pos              (22U)

+#define ADC_CFGR_AWD1SGL_Msk              (0x1UL << ADC_CFGR_AWD1SGL_Pos)      /*!< 0x00400000 */

+#define ADC_CFGR_AWD1SGL                  ADC_CFGR_AWD1SGL_Msk                 /*!< Enable the watchdog 1 on a single channel or on all channels */

+#define ADC_CFGR_AWD1EN_Pos               (23U)

+#define ADC_CFGR_AWD1EN_Msk               (0x1UL << ADC_CFGR_AWD1EN_Pos)       /*!< 0x00800000 */

+#define ADC_CFGR_AWD1EN                   ADC_CFGR_AWD1EN_Msk                  /*!< ADC Analog watchdog 1 enable on regular Channels */

+#define ADC_CFGR_JAWD1EN_Pos              (24U)

+#define ADC_CFGR_JAWD1EN_Msk              (0x1UL << ADC_CFGR_JAWD1EN_Pos)      /*!< 0x01000000 */

+#define ADC_CFGR_JAWD1EN                  ADC_CFGR_JAWD1EN_Msk                 /*!< ADC Analog watchdog 1 enable on injected Channels */

+#define ADC_CFGR_JAUTO_Pos                (25U)

+#define ADC_CFGR_JAUTO_Msk                (0x1UL << ADC_CFGR_JAUTO_Pos)        /*!< 0x02000000 */

+#define ADC_CFGR_JAUTO                    ADC_CFGR_JAUTO_Msk                   /*!< ADC Automatic injected group conversion */

+

+#define ADC_CFGR_AWD1CH_Pos               (26U)

+#define ADC_CFGR_AWD1CH_Msk               (0x1FUL << ADC_CFGR_AWD1CH_Pos)      /*!< 0x7C000000 */

+#define ADC_CFGR_AWD1CH                   ADC_CFGR_AWD1CH_Msk                  /*!< ADC Analog watchdog 1 Channel selection */

+#define ADC_CFGR_AWD1CH_0                 (0x01UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x04000000 */

+#define ADC_CFGR_AWD1CH_1                 (0x02UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x08000000 */

+#define ADC_CFGR_AWD1CH_2                 (0x04UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x10000000 */

+#define ADC_CFGR_AWD1CH_3                 (0x08UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x20000000 */

+#define ADC_CFGR_AWD1CH_4                 (0x10UL << ADC_CFGR_AWD1CH_Pos)       /*!< 0x40000000 */

+

+#define ADC_CFGR_JQDIS_Pos                (31U)

+#define ADC_CFGR_JQDIS_Msk                (0x1UL << ADC_CFGR_JQDIS_Pos)        /*!< 0x80000000 */

+#define ADC_CFGR_JQDIS                    ADC_CFGR_JQDIS_Msk                   /*!< ADC Injected queue disable */

+

+/********************  Bit definition for ADC_CFGR2 register  ********************/

+#define ADC_CFGR2_ROVSE_Pos               (0U)

+#define ADC_CFGR2_ROVSE_Msk               (0x1UL << ADC_CFGR2_ROVSE_Pos)       /*!< 0x00000001 */

+#define ADC_CFGR2_ROVSE                   ADC_CFGR2_ROVSE_Msk                  /*!< ADC Regular group oversampler enable */

+#define ADC_CFGR2_JOVSE_Pos               (1U)

+#define ADC_CFGR2_JOVSE_Msk               (0x1UL << ADC_CFGR2_JOVSE_Pos)       /*!< 0x00000002 */

+#define ADC_CFGR2_JOVSE                   ADC_CFGR2_JOVSE_Msk                  /*!< ADC Injected group oversampler enable */

+

+#define ADC_CFGR2_OVSS_Pos                (5U)

+#define ADC_CFGR2_OVSS_Msk                (0xFUL << ADC_CFGR2_OVSS_Pos)        /*!< 0x000001E0 */

+#define ADC_CFGR2_OVSS                    ADC_CFGR2_OVSS_Msk                   /*!< ADC Regular Oversampling shift */

+#define ADC_CFGR2_OVSS_0                  (0x1UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000020 */

+#define ADC_CFGR2_OVSS_1                  (0x2UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000040 */

+#define ADC_CFGR2_OVSS_2                  (0x4UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000080 */

+#define ADC_CFGR2_OVSS_3                  (0x8UL << ADC_CFGR2_OVSS_Pos)         /*!< 0x00000100 */

+

+#define ADC_CFGR2_TROVS_Pos               (9U)

+#define ADC_CFGR2_TROVS_Msk               (0x1UL << ADC_CFGR2_TROVS_Pos)       /*!< 0x00000200 */

+#define ADC_CFGR2_TROVS                   ADC_CFGR2_TROVS_Msk                  /*!< ADC Triggered regular Oversampling */

+#define ADC_CFGR2_ROVSM_Pos               (10U)

+#define ADC_CFGR2_ROVSM_Msk               (0x1UL << ADC_CFGR2_ROVSM_Pos)       /*!< 0x00000400 */

+#define ADC_CFGR2_ROVSM                   ADC_CFGR2_ROVSM_Msk                  /*!< ADC Regular oversampling mode */

+

+#define ADC_CFGR2_RSHIFT1_Pos             (11U)

+#define ADC_CFGR2_RSHIFT1_Msk             (0x1UL << ADC_CFGR2_RSHIFT1_Pos)     /*!< 0x00000800 */

+#define ADC_CFGR2_RSHIFT1                 ADC_CFGR2_RSHIFT1_Msk                /*!< ADC Right-shift data after Offset 1 correction */

+#define ADC_CFGR2_RSHIFT2_Pos             (12U)

+#define ADC_CFGR2_RSHIFT2_Msk             (0x1UL << ADC_CFGR2_RSHIFT2_Pos)     /*!< 0x00001000 */

+#define ADC_CFGR2_RSHIFT2                 ADC_CFGR2_RSHIFT2_Msk                /*!< ADC Right-shift data after Offset 2 correction */

+#define ADC_CFGR2_RSHIFT3_Pos             (13U)

+#define ADC_CFGR2_RSHIFT3_Msk             (0x1UL << ADC_CFGR2_RSHIFT3_Pos)     /*!< 0x00002000 */

+#define ADC_CFGR2_RSHIFT3                 ADC_CFGR2_RSHIFT3_Msk                /*!< ADC Right-shift data after Offset 3 correction */

+#define ADC_CFGR2_RSHIFT4_Pos             (14U)

+#define ADC_CFGR2_RSHIFT4_Msk             (0x1UL << ADC_CFGR2_RSHIFT4_Pos)     /*!< 0x00004000 */

+#define ADC_CFGR2_RSHIFT4                 ADC_CFGR2_RSHIFT4_Msk                /*!< ADC Right-shift data after Offset 4 correction */

+

+#define ADC_CFGR2_OVSR_Pos                (16U)

+#define ADC_CFGR2_OVSR_Msk                (0x3FFUL << ADC_CFGR2_OVSR_Pos)      /*!< 0x03FF0000 */

+#define ADC_CFGR2_OVSR                    ADC_CFGR2_OVSR_Msk                   /*!< ADC oversampling Ratio */

+#define ADC_CFGR2_OVSR_0                  (0x001UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00010000 */

+#define ADC_CFGR2_OVSR_1                  (0x002UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00020000 */

+#define ADC_CFGR2_OVSR_2                  (0x004UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00040000 */

+#define ADC_CFGR2_OVSR_3                  (0x008UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00080000 */

+#define ADC_CFGR2_OVSR_4                  (0x010UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00100000 */

+#define ADC_CFGR2_OVSR_5                  (0x020UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00200000 */

+#define ADC_CFGR2_OVSR_6                  (0x040UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00400000 */

+#define ADC_CFGR2_OVSR_7                  (0x080UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x00800000 */

+#define ADC_CFGR2_OVSR_8                  (0x100UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x01000000 */

+#define ADC_CFGR2_OVSR_9                  (0x200UL << ADC_CFGR2_OVSR_Pos)       /*!< 0x02000000 */

+

+#define ADC_CFGR2_LSHIFT_Pos              (28U)

+#define ADC_CFGR2_LSHIFT_Msk              (0xFUL << ADC_CFGR2_LSHIFT_Pos)      /*!< 0xF0000000 */

+#define ADC_CFGR2_LSHIFT                  ADC_CFGR2_LSHIFT_Msk                 /*!< ADC Left shift factor */

+#define ADC_CFGR2_LSHIFT_0                (0x1UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x10000000 */

+#define ADC_CFGR2_LSHIFT_1                (0x2UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x20000000 */

+#define ADC_CFGR2_LSHIFT_2                (0x4UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x40000000 */

+#define ADC_CFGR2_LSHIFT_3                (0x8UL << ADC_CFGR2_LSHIFT_Pos)       /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_SMPR1 register  ********************/

+#define ADC_SMPR1_SMP0_Pos                (0U)

+#define ADC_SMPR1_SMP0_Msk                (0x7UL << ADC_SMPR1_SMP0_Pos)        /*!< 0x00000007 */

+#define ADC_SMPR1_SMP0                    ADC_SMPR1_SMP0_Msk                   /*!< ADC Channel 0 Sampling time selection  */

+#define ADC_SMPR1_SMP0_0                  (0x1UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000001 */

+#define ADC_SMPR1_SMP0_1                  (0x2UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000002 */

+#define ADC_SMPR1_SMP0_2                  (0x4UL << ADC_SMPR1_SMP0_Pos)         /*!< 0x00000004 */

+

+#define ADC_SMPR1_SMP1_Pos                (3U)

+#define ADC_SMPR1_SMP1_Msk                (0x7UL << ADC_SMPR1_SMP1_Pos)        /*!< 0x00000038 */

+#define ADC_SMPR1_SMP1                    ADC_SMPR1_SMP1_Msk                   /*!< ADC Channel 1 Sampling time selection  */

+#define ADC_SMPR1_SMP1_0                  (0x1UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000008 */

+#define ADC_SMPR1_SMP1_1                  (0x2UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000010 */

+#define ADC_SMPR1_SMP1_2                  (0x4UL << ADC_SMPR1_SMP1_Pos)         /*!< 0x00000020 */

+

+#define ADC_SMPR1_SMP2_Pos                (6U)

+#define ADC_SMPR1_SMP2_Msk                (0x7UL << ADC_SMPR1_SMP2_Pos)        /*!< 0x000001C0 */

+#define ADC_SMPR1_SMP2                    ADC_SMPR1_SMP2_Msk                   /*!< ADC Channel 2 Sampling time selection  */

+#define ADC_SMPR1_SMP2_0                  (0x1UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000040 */

+#define ADC_SMPR1_SMP2_1                  (0x2UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000080 */

+#define ADC_SMPR1_SMP2_2                  (0x4UL << ADC_SMPR1_SMP2_Pos)         /*!< 0x00000100 */

+

+#define ADC_SMPR1_SMP3_Pos                (9U)

+#define ADC_SMPR1_SMP3_Msk                (0x7UL << ADC_SMPR1_SMP3_Pos)        /*!< 0x00000E00 */

+#define ADC_SMPR1_SMP3                    ADC_SMPR1_SMP3_Msk                   /*!< ADC Channel 3 Sampling time selection  */

+#define ADC_SMPR1_SMP3_0                  (0x1UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000200 */

+#define ADC_SMPR1_SMP3_1                  (0x2UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000400 */

+#define ADC_SMPR1_SMP3_2                  (0x4UL << ADC_SMPR1_SMP3_Pos)         /*!< 0x00000800 */

+

+#define ADC_SMPR1_SMP4_Pos                (12U)

+#define ADC_SMPR1_SMP4_Msk                (0x7UL << ADC_SMPR1_SMP4_Pos)        /*!< 0x00007000 */

+#define ADC_SMPR1_SMP4                    ADC_SMPR1_SMP4_Msk                   /*!< ADC Channel 4 Sampling time selection  */

+#define ADC_SMPR1_SMP4_0                  (0x1UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00001000 */

+#define ADC_SMPR1_SMP4_1                  (0x2UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00002000 */

+#define ADC_SMPR1_SMP4_2                  (0x4UL << ADC_SMPR1_SMP4_Pos)         /*!< 0x00004000 */

+

+#define ADC_SMPR1_SMP5_Pos                (15U)

+#define ADC_SMPR1_SMP5_Msk                (0x7UL << ADC_SMPR1_SMP5_Pos)        /*!< 0x00038000 */

+#define ADC_SMPR1_SMP5                    ADC_SMPR1_SMP5_Msk                   /*!< ADC Channel 5 Sampling time selection  */

+#define ADC_SMPR1_SMP5_0                  (0x1UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00008000 */

+#define ADC_SMPR1_SMP5_1                  (0x2UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00010000 */

+#define ADC_SMPR1_SMP5_2                  (0x4UL << ADC_SMPR1_SMP5_Pos)         /*!< 0x00020000 */

+

+#define ADC_SMPR1_SMP6_Pos                (18U)

+#define ADC_SMPR1_SMP6_Msk                (0x7UL << ADC_SMPR1_SMP6_Pos)        /*!< 0x001C0000 */

+#define ADC_SMPR1_SMP6                    ADC_SMPR1_SMP6_Msk                   /*!< ADC Channel 6 Sampling time selection  */

+#define ADC_SMPR1_SMP6_0                  (0x1UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00040000 */

+#define ADC_SMPR1_SMP6_1                  (0x2UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00080000 */

+#define ADC_SMPR1_SMP6_2                  (0x4UL << ADC_SMPR1_SMP6_Pos)         /*!< 0x00100000 */

+

+#define ADC_SMPR1_SMP7_Pos                (21U)

+#define ADC_SMPR1_SMP7_Msk                (0x7UL << ADC_SMPR1_SMP7_Pos)        /*!< 0x00E00000 */

+#define ADC_SMPR1_SMP7                    ADC_SMPR1_SMP7_Msk                   /*!< ADC Channel 7 Sampling time selection  */

+#define ADC_SMPR1_SMP7_0                  (0x1UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00200000 */

+#define ADC_SMPR1_SMP7_1                  (0x2UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00400000 */

+#define ADC_SMPR1_SMP7_2                  (0x4UL << ADC_SMPR1_SMP7_Pos)         /*!< 0x00800000 */

+

+#define ADC_SMPR1_SMP8_Pos                (24U)

+#define ADC_SMPR1_SMP8_Msk                (0x7UL << ADC_SMPR1_SMP8_Pos)        /*!< 0x07000000 */

+#define ADC_SMPR1_SMP8                    ADC_SMPR1_SMP8_Msk                   /*!< ADC Channel 8 Sampling time selection  */

+#define ADC_SMPR1_SMP8_0                  (0x1UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x01000000 */

+#define ADC_SMPR1_SMP8_1                  (0x2UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x02000000 */

+#define ADC_SMPR1_SMP8_2                  (0x4UL << ADC_SMPR1_SMP8_Pos)         /*!< 0x04000000 */

+

+#define ADC_SMPR1_SMP9_Pos                (27U)

+#define ADC_SMPR1_SMP9_Msk                (0x7UL << ADC_SMPR1_SMP9_Pos)        /*!< 0x38000000 */

+#define ADC_SMPR1_SMP9                    ADC_SMPR1_SMP9_Msk                   /*!< ADC Channel 9 Sampling time selection  */

+#define ADC_SMPR1_SMP9_0                  (0x1UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x08000000 */

+#define ADC_SMPR1_SMP9_1                  (0x2UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x10000000 */

+#define ADC_SMPR1_SMP9_2                  (0x4UL << ADC_SMPR1_SMP9_Pos)         /*!< 0x20000000 */

+

+/********************  Bit definition for ADC_SMPR2 register  ********************/

+#define ADC_SMPR2_SMP10_Pos               (0U)

+#define ADC_SMPR2_SMP10_Msk               (0x7UL << ADC_SMPR2_SMP10_Pos)       /*!< 0x00000007 */

+#define ADC_SMPR2_SMP10                   ADC_SMPR2_SMP10_Msk                  /*!< ADC Channel 10 Sampling time selection  */

+#define ADC_SMPR2_SMP10_0                 (0x1UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000001 */

+#define ADC_SMPR2_SMP10_1                 (0x2UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000002 */

+#define ADC_SMPR2_SMP10_2                 (0x4UL << ADC_SMPR2_SMP10_Pos)        /*!< 0x00000004 */

+

+#define ADC_SMPR2_SMP11_Pos               (3U)

+#define ADC_SMPR2_SMP11_Msk               (0x7UL << ADC_SMPR2_SMP11_Pos)       /*!< 0x00000038 */

+#define ADC_SMPR2_SMP11                   ADC_SMPR2_SMP11_Msk                  /*!< ADC Channel 11 Sampling time selection  */

+#define ADC_SMPR2_SMP11_0                 (0x1UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000008 */

+#define ADC_SMPR2_SMP11_1                 (0x2UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000010 */

+#define ADC_SMPR2_SMP11_2                 (0x4UL << ADC_SMPR2_SMP11_Pos)        /*!< 0x00000020 */

+

+#define ADC_SMPR2_SMP12_Pos               (6U)

+#define ADC_SMPR2_SMP12_Msk               (0x7UL << ADC_SMPR2_SMP12_Pos)       /*!< 0x000001C0 */

+#define ADC_SMPR2_SMP12                   ADC_SMPR2_SMP12_Msk                  /*!< ADC Channel 12 Sampling time selection  */

+#define ADC_SMPR2_SMP12_0                 (0x1UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000040 */

+#define ADC_SMPR2_SMP12_1                 (0x2UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000080 */

+#define ADC_SMPR2_SMP12_2                 (0x4UL << ADC_SMPR2_SMP12_Pos)        /*!< 0x00000100 */

+

+#define ADC_SMPR2_SMP13_Pos               (9U)

+#define ADC_SMPR2_SMP13_Msk               (0x7UL << ADC_SMPR2_SMP13_Pos)       /*!< 0x00000E00 */

+#define ADC_SMPR2_SMP13                   ADC_SMPR2_SMP13_Msk                  /*!< ADC Channel 13 Sampling time selection  */

+#define ADC_SMPR2_SMP13_0                 (0x1UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000200 */

+#define ADC_SMPR2_SMP13_1                 (0x2UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000400 */

+#define ADC_SMPR2_SMP13_2                 (0x4UL << ADC_SMPR2_SMP13_Pos)        /*!< 0x00000800 */

+

+#define ADC_SMPR2_SMP14_Pos               (12U)

+#define ADC_SMPR2_SMP14_Msk               (0x7UL << ADC_SMPR2_SMP14_Pos)       /*!< 0x00007000 */

+#define ADC_SMPR2_SMP14                   ADC_SMPR2_SMP14_Msk                  /*!< ADC Channel 14 Sampling time selection  */

+#define ADC_SMPR2_SMP14_0                 (0x1UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00001000 */

+#define ADC_SMPR2_SMP14_1                 (0x2UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00002000 */

+#define ADC_SMPR2_SMP14_2                 (0x4UL << ADC_SMPR2_SMP14_Pos)        /*!< 0x00004000 */

+

+#define ADC_SMPR2_SMP15_Pos               (15U)

+#define ADC_SMPR2_SMP15_Msk               (0x7UL << ADC_SMPR2_SMP15_Pos)       /*!< 0x00038000 */

+#define ADC_SMPR2_SMP15                   ADC_SMPR2_SMP15_Msk                  /*!< ADC Channel 15 Sampling time selection  */

+#define ADC_SMPR2_SMP15_0                 (0x1UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00008000 */

+#define ADC_SMPR2_SMP15_1                 (0x2UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00010000 */

+#define ADC_SMPR2_SMP15_2                 (0x4UL << ADC_SMPR2_SMP15_Pos)        /*!< 0x00020000 */

+

+#define ADC_SMPR2_SMP16_Pos               (18U)

+#define ADC_SMPR2_SMP16_Msk               (0x7UL << ADC_SMPR2_SMP16_Pos)       /*!< 0x001C0000 */

+#define ADC_SMPR2_SMP16                   ADC_SMPR2_SMP16_Msk                  /*!< ADC Channel 16 Sampling time selection  */

+#define ADC_SMPR2_SMP16_0                 (0x1UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00040000 */

+#define ADC_SMPR2_SMP16_1                 (0x2UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00080000 */

+#define ADC_SMPR2_SMP16_2                 (0x4UL << ADC_SMPR2_SMP16_Pos)        /*!< 0x00100000 */

+

+#define ADC_SMPR2_SMP17_Pos               (21U)

+#define ADC_SMPR2_SMP17_Msk               (0x7UL << ADC_SMPR2_SMP17_Pos)       /*!< 0x00E00000 */

+#define ADC_SMPR2_SMP17                   ADC_SMPR2_SMP17_Msk                  /*!< ADC Channel 17 Sampling time selection  */

+#define ADC_SMPR2_SMP17_0                 (0x1UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00200000 */

+#define ADC_SMPR2_SMP17_1                 (0x2UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00400000 */

+#define ADC_SMPR2_SMP17_2                 (0x4UL << ADC_SMPR2_SMP17_Pos)        /*!< 0x00800000 */

+

+#define ADC_SMPR2_SMP18_Pos               (24U)

+#define ADC_SMPR2_SMP18_Msk               (0x7UL << ADC_SMPR2_SMP18_Pos)       /*!< 0x07000000 */

+#define ADC_SMPR2_SMP18                   ADC_SMPR2_SMP18_Msk                  /*!< ADC Channel 18 Sampling time selection  */

+#define ADC_SMPR2_SMP18_0                 (0x1UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x01000000 */

+#define ADC_SMPR2_SMP18_1                 (0x2UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x02000000 */

+#define ADC_SMPR2_SMP18_2                 (0x4UL << ADC_SMPR2_SMP18_Pos)        /*!< 0x04000000 */

+

+#define ADC_SMPR2_SMP19_Pos               (27U)

+#define ADC_SMPR2_SMP19_Msk               (0x7UL << ADC_SMPR2_SMP19_Pos)       /*!< 0x38000000 */

+#define ADC_SMPR2_SMP19                   ADC_SMPR2_SMP19_Msk                  /*!< ADC Channel 19 Sampling time selection  */

+#define ADC_SMPR2_SMP19_0                 (0x1UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x08000000 */

+#define ADC_SMPR2_SMP19_1                 (0x2UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x10000000 */

+#define ADC_SMPR2_SMP19_2                 (0x4UL << ADC_SMPR2_SMP19_Pos)        /*!< 0x20000000 */

+

+/********************  Bit definition for ADC_PCSEL register  ********************/

+#define ADC_PCSEL_PCSEL_Pos               (0U)

+#define ADC_PCSEL_PCSEL_Msk               (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos)   /*!< 0x000FFFFF */

+#define ADC_PCSEL_PCSEL                   ADC_PCSEL_PCSEL_Msk                  /*!< ADC pre channel selection */

+#define ADC_PCSEL_PCSEL_0                 (0x00001UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000001 */

+#define ADC_PCSEL_PCSEL_1                 (0x00002UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000002 */

+#define ADC_PCSEL_PCSEL_2                 (0x00004UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000004 */

+#define ADC_PCSEL_PCSEL_3                 (0x00008UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000008 */

+#define ADC_PCSEL_PCSEL_4                 (0x00010UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000010 */

+#define ADC_PCSEL_PCSEL_5                 (0x00020UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000020 */

+#define ADC_PCSEL_PCSEL_6                 (0x00040UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000040 */

+#define ADC_PCSEL_PCSEL_7                 (0x00080UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000080 */

+#define ADC_PCSEL_PCSEL_8                 (0x00100UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000100 */

+#define ADC_PCSEL_PCSEL_9                 (0x00200UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000200 */

+#define ADC_PCSEL_PCSEL_10                (0x00400UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000400 */

+#define ADC_PCSEL_PCSEL_11                (0x00800UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00000800 */

+#define ADC_PCSEL_PCSEL_12                (0x01000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00001000 */

+#define ADC_PCSEL_PCSEL_13                (0x02000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00002000 */

+#define ADC_PCSEL_PCSEL_14                (0x04000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00004000 */

+#define ADC_PCSEL_PCSEL_15                (0x08000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00008000 */

+#define ADC_PCSEL_PCSEL_16                (0x10000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00010000 */

+#define ADC_PCSEL_PCSEL_17                (0x20000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00020000 */

+#define ADC_PCSEL_PCSEL_18                (0x40000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00040000 */

+#define ADC_PCSEL_PCSEL_19                (0x80000UL << ADC_PCSEL_PCSEL_Pos)    /*!< 0x00080000 */

+

+/*****************  Bit definition for ADC_LTR1, 2, 3 registers *****************/

+#define ADC_LTR_LT_Pos                    (0U)

+#define ADC_LTR_LT_Msk                    (0x3FFFFFFUL << ADC_LTR_LT_Pos)      /*!< 0x03FFFFFF */

+#define ADC_LTR_LT                        ADC_LTR_LT_Msk                       /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */

+

+/*****************  Bit definition for ADC_HTR1, 2, 3 registers  ****************/

+#define ADC_HTR_HT_Pos                    (0U)

+#define ADC_HTR_HT_Msk                    (0x3FFFFFFUL << ADC_HTR_HT_Pos)      /*!< 0x03FFFFFF */

+#define ADC_HTR_HT                        ADC_HTR_HT_Msk                       /*!< ADC Analog watchdog 1,2 and 3 higher threshold */

+

+

+/********************  Bit definition for ADC_SQR1 register  ********************/

+#define ADC_SQR1_L_Pos                    (0U)

+#define ADC_SQR1_L_Msk                    (0xFUL << ADC_SQR1_L_Pos)            /*!< 0x0000000F */

+#define ADC_SQR1_L                        ADC_SQR1_L_Msk                       /*!< ADC regular channel sequence lenght */

+#define ADC_SQR1_L_0                      (0x1UL << ADC_SQR1_L_Pos)             /*!< 0x00000001 */

+#define ADC_SQR1_L_1                      (0x2UL << ADC_SQR1_L_Pos)             /*!< 0x00000002 */

+#define ADC_SQR1_L_2                      (0x4UL << ADC_SQR1_L_Pos)             /*!< 0x00000004 */

+#define ADC_SQR1_L_3                      (0x8UL << ADC_SQR1_L_Pos)             /*!< 0x00000008 */

+

+#define ADC_SQR1_SQ1_Pos                  (6U)

+#define ADC_SQR1_SQ1_Msk                  (0x1FUL << ADC_SQR1_SQ1_Pos)         /*!< 0x000007C0 */

+#define ADC_SQR1_SQ1                      ADC_SQR1_SQ1_Msk                     /*!< ADC 1st conversion in regular sequence */

+#define ADC_SQR1_SQ1_0                    (0x01UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000040 */

+#define ADC_SQR1_SQ1_1                    (0x02UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000080 */

+#define ADC_SQR1_SQ1_2                    (0x04UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000100 */

+#define ADC_SQR1_SQ1_3                    (0x08UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000200 */

+#define ADC_SQR1_SQ1_4                    (0x10UL << ADC_SQR1_SQ1_Pos)          /*!< 0x00000400 */

+

+#define ADC_SQR1_SQ2_Pos                  (12U)

+#define ADC_SQR1_SQ2_Msk                  (0x1FUL << ADC_SQR1_SQ2_Pos)         /*!< 0x0001F000 */

+#define ADC_SQR1_SQ2                      ADC_SQR1_SQ2_Msk                     /*!< ADC 2nd conversion in regular sequence */

+#define ADC_SQR1_SQ2_0                    (0x01UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00001000 */

+#define ADC_SQR1_SQ2_1                    (0x02UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00002000 */

+#define ADC_SQR1_SQ2_2                    (0x04UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00004000 */

+#define ADC_SQR1_SQ2_3                    (0x08UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00008000 */

+#define ADC_SQR1_SQ2_4                    (0x10UL << ADC_SQR1_SQ2_Pos)          /*!< 0x00010000 */

+

+#define ADC_SQR1_SQ3_Pos                  (18U)

+#define ADC_SQR1_SQ3_Msk                  (0x1FUL << ADC_SQR1_SQ3_Pos)         /*!< 0x007C0000 */

+#define ADC_SQR1_SQ3                      ADC_SQR1_SQ3_Msk                     /*!< ADC 3rd conversion in regular sequence */

+#define ADC_SQR1_SQ3_0                    (0x01UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00040000 */

+#define ADC_SQR1_SQ3_1                    (0x02UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00080000 */

+#define ADC_SQR1_SQ3_2                    (0x04UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00100000 */

+#define ADC_SQR1_SQ3_3                    (0x08UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00200000 */

+#define ADC_SQR1_SQ3_4                    (0x10UL << ADC_SQR1_SQ3_Pos)          /*!< 0x00400000 */

+

+#define ADC_SQR1_SQ4_Pos                  (24U)

+#define ADC_SQR1_SQ4_Msk                  (0x1FUL << ADC_SQR1_SQ4_Pos)         /*!< 0x1F000000 */

+#define ADC_SQR1_SQ4                      ADC_SQR1_SQ4_Msk                     /*!< ADC 4th conversion in regular sequence */

+#define ADC_SQR1_SQ4_0                    (0x01UL << ADC_SQR1_SQ4_Pos)          /*!< 0x01000000 */

+#define ADC_SQR1_SQ4_1                    (0x02UL << ADC_SQR1_SQ4_Pos)          /*!< 0x02000000 */

+#define ADC_SQR1_SQ4_2                    (0x04UL << ADC_SQR1_SQ4_Pos)          /*!< 0x04000000 */

+#define ADC_SQR1_SQ4_3                    (0x08UL << ADC_SQR1_SQ4_Pos)          /*!< 0x08000000 */

+#define ADC_SQR1_SQ4_4                    (0x10UL << ADC_SQR1_SQ4_Pos)          /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR2 register  ********************/

+#define ADC_SQR2_SQ5_Pos                  (0U)

+#define ADC_SQR2_SQ5_Msk                  (0x1FUL << ADC_SQR2_SQ5_Pos)         /*!< 0x0000001F */

+#define ADC_SQR2_SQ5                      ADC_SQR2_SQ5_Msk                     /*!< ADC 5th conversion in regular sequence */

+#define ADC_SQR2_SQ5_0                    (0x01UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000001 */

+#define ADC_SQR2_SQ5_1                    (0x02UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000002 */

+#define ADC_SQR2_SQ5_2                    (0x04UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000004 */

+#define ADC_SQR2_SQ5_3                    (0x08UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000008 */

+#define ADC_SQR2_SQ5_4                    (0x10UL << ADC_SQR2_SQ5_Pos)          /*!< 0x00000010 */

+

+#define ADC_SQR2_SQ6_Pos                  (6U)

+#define ADC_SQR2_SQ6_Msk                  (0x1FUL << ADC_SQR2_SQ6_Pos)         /*!< 0x000007C0 */

+#define ADC_SQR2_SQ6                      ADC_SQR2_SQ6_Msk                     /*!< ADC 6th conversion in regular sequence */

+#define ADC_SQR2_SQ6_0                    (0x01UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000040 */

+#define ADC_SQR2_SQ6_1                    (0x02UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000080 */

+#define ADC_SQR2_SQ6_2                    (0x04UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000100 */

+#define ADC_SQR2_SQ6_3                    (0x08UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000200 */

+#define ADC_SQR2_SQ6_4                    (0x10UL << ADC_SQR2_SQ6_Pos)          /*!< 0x00000400 */

+

+#define ADC_SQR2_SQ7_Pos                  (12U)

+#define ADC_SQR2_SQ7_Msk                  (0x1FUL << ADC_SQR2_SQ7_Pos)         /*!< 0x0001F000 */

+#define ADC_SQR2_SQ7                      ADC_SQR2_SQ7_Msk                     /*!< ADC 7th conversion in regular sequence */

+#define ADC_SQR2_SQ7_0                    (0x01UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00001000 */

+#define ADC_SQR2_SQ7_1                    (0x02UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00002000 */

+#define ADC_SQR2_SQ7_2                    (0x04UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00004000 */

+#define ADC_SQR2_SQ7_3                    (0x08UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00008000 */

+#define ADC_SQR2_SQ7_4                    (0x10UL << ADC_SQR2_SQ7_Pos)          /*!< 0x00010000 */

+

+#define ADC_SQR2_SQ8_Pos                  (18U)

+#define ADC_SQR2_SQ8_Msk                  (0x1FUL << ADC_SQR2_SQ8_Pos)         /*!< 0x007C0000 */

+#define ADC_SQR2_SQ8                      ADC_SQR2_SQ8_Msk                     /*!< ADC 8th conversion in regular sequence */

+#define ADC_SQR2_SQ8_0                    (0x01UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00040000 */

+#define ADC_SQR2_SQ8_1                    (0x02UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00080000 */

+#define ADC_SQR2_SQ8_2                    (0x04UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00100000 */

+#define ADC_SQR2_SQ8_3                    (0x08UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00200000 */

+#define ADC_SQR2_SQ8_4                    (0x10UL << ADC_SQR2_SQ8_Pos)          /*!< 0x00400000 */

+

+#define ADC_SQR2_SQ9_Pos                  (24U)

+#define ADC_SQR2_SQ9_Msk                  (0x1FUL << ADC_SQR2_SQ9_Pos)         /*!< 0x1F000000 */

+#define ADC_SQR2_SQ9                      ADC_SQR2_SQ9_Msk                     /*!< ADC 9th conversion in regular sequence */

+#define ADC_SQR2_SQ9_0                    (0x01UL << ADC_SQR2_SQ9_Pos)          /*!< 0x01000000 */

+#define ADC_SQR2_SQ9_1                    (0x02UL << ADC_SQR2_SQ9_Pos)          /*!< 0x02000000 */

+#define ADC_SQR2_SQ9_2                    (0x04UL << ADC_SQR2_SQ9_Pos)          /*!< 0x04000000 */

+#define ADC_SQR2_SQ9_3                    (0x08UL << ADC_SQR2_SQ9_Pos)          /*!< 0x08000000 */

+#define ADC_SQR2_SQ9_4                    (0x10UL << ADC_SQR2_SQ9_Pos)          /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR3 register  ********************/

+#define ADC_SQR3_SQ10_Pos                 (0U)

+#define ADC_SQR3_SQ10_Msk                 (0x1FUL << ADC_SQR3_SQ10_Pos)        /*!< 0x0000001F */

+#define ADC_SQR3_SQ10                     ADC_SQR3_SQ10_Msk                    /*!< ADC 10th conversion in regular sequence */

+#define ADC_SQR3_SQ10_0                   (0x01UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000001 */

+#define ADC_SQR3_SQ10_1                   (0x02UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000002 */

+#define ADC_SQR3_SQ10_2                   (0x04UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000004 */

+#define ADC_SQR3_SQ10_3                   (0x08UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000008 */

+#define ADC_SQR3_SQ10_4                   (0x10UL << ADC_SQR3_SQ10_Pos)         /*!< 0x00000010 */

+

+#define ADC_SQR3_SQ11_Pos                 (6U)

+#define ADC_SQR3_SQ11_Msk                 (0x1FUL << ADC_SQR3_SQ11_Pos)        /*!< 0x000007C0 */

+#define ADC_SQR3_SQ11                     ADC_SQR3_SQ11_Msk                    /*!< ADC 11th conversion in regular sequence */

+#define ADC_SQR3_SQ11_0                   (0x01UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000040 */

+#define ADC_SQR3_SQ11_1                   (0x02UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000080 */

+#define ADC_SQR3_SQ11_2                   (0x04UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000100 */

+#define ADC_SQR3_SQ11_3                   (0x08UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000200 */

+#define ADC_SQR3_SQ11_4                   (0x10UL << ADC_SQR3_SQ11_Pos)         /*!< 0x00000400 */

+

+#define ADC_SQR3_SQ12_Pos                 (12U)

+#define ADC_SQR3_SQ12_Msk                 (0x1FUL << ADC_SQR3_SQ12_Pos)        /*!< 0x0001F000 */

+#define ADC_SQR3_SQ12                     ADC_SQR3_SQ12_Msk                    /*!< ADC 12th conversion in regular sequence */

+#define ADC_SQR3_SQ12_0                   (0x01UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00001000 */

+#define ADC_SQR3_SQ12_1                   (0x02UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00002000 */

+#define ADC_SQR3_SQ12_2                   (0x04UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00004000 */

+#define ADC_SQR3_SQ12_3                   (0x08UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00008000 */

+#define ADC_SQR3_SQ12_4                   (0x10UL << ADC_SQR3_SQ12_Pos)         /*!< 0x00010000 */

+

+#define ADC_SQR3_SQ13_Pos                 (18U)

+#define ADC_SQR3_SQ13_Msk                 (0x1FUL << ADC_SQR3_SQ13_Pos)        /*!< 0x007C0000 */

+#define ADC_SQR3_SQ13                     ADC_SQR3_SQ13_Msk                    /*!< ADC 13th conversion in regular sequence */

+#define ADC_SQR3_SQ13_0                   (0x01UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00040000 */

+#define ADC_SQR3_SQ13_1                   (0x02UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00080000 */

+#define ADC_SQR3_SQ13_2                   (0x04UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00100000 */

+#define ADC_SQR3_SQ13_3                   (0x08UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00200000 */

+#define ADC_SQR3_SQ13_4                   (0x10UL << ADC_SQR3_SQ13_Pos)         /*!< 0x00400000 */

+

+#define ADC_SQR3_SQ14_Pos                 (24U)

+#define ADC_SQR3_SQ14_Msk                 (0x1FUL << ADC_SQR3_SQ14_Pos)        /*!< 0x1F000000 */

+#define ADC_SQR3_SQ14                     ADC_SQR3_SQ14_Msk                    /*!< ADC 14th conversion in regular sequence */

+#define ADC_SQR3_SQ14_0                   (0x01UL << ADC_SQR3_SQ14_Pos)         /*!< 0x01000000 */

+#define ADC_SQR3_SQ14_1                   (0x02UL << ADC_SQR3_SQ14_Pos)         /*!< 0x02000000 */

+#define ADC_SQR3_SQ14_2                   (0x04UL << ADC_SQR3_SQ14_Pos)         /*!< 0x04000000 */

+#define ADC_SQR3_SQ14_3                   (0x08UL << ADC_SQR3_SQ14_Pos)         /*!< 0x08000000 */

+#define ADC_SQR3_SQ14_4                   (0x10UL << ADC_SQR3_SQ14_Pos)         /*!< 0x10000000 */

+

+/********************  Bit definition for ADC_SQR4 register  ********************/

+#define ADC_SQR4_SQ15_Pos                 (0U)

+#define ADC_SQR4_SQ15_Msk                 (0x1FUL << ADC_SQR4_SQ15_Pos)        /*!< 0x0000001F */

+#define ADC_SQR4_SQ15                     ADC_SQR4_SQ15_Msk                    /*!< ADC 15th conversion in regular sequence */

+#define ADC_SQR4_SQ15_0                   (0x01UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000001 */

+#define ADC_SQR4_SQ15_1                   (0x02UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000002 */

+#define ADC_SQR4_SQ15_2                   (0x04UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000004 */

+#define ADC_SQR4_SQ15_3                   (0x08UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000008 */

+#define ADC_SQR4_SQ15_4                   (0x10UL << ADC_SQR4_SQ15_Pos)         /*!< 0x00000010 */

+

+#define ADC_SQR4_SQ16_Pos                 (6U)

+#define ADC_SQR4_SQ16_Msk                 (0x1FUL << ADC_SQR4_SQ16_Pos)        /*!< 0x000007C0 */

+#define ADC_SQR4_SQ16                     ADC_SQR4_SQ16_Msk                    /*!< ADC 16th conversion in regular sequence */

+#define ADC_SQR4_SQ16_0                   (0x01UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000040 */

+#define ADC_SQR4_SQ16_1                   (0x02UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000080 */

+#define ADC_SQR4_SQ16_2                   (0x04UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000100 */

+#define ADC_SQR4_SQ16_3                   (0x08UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000200 */

+#define ADC_SQR4_SQ16_4                   (0x10UL << ADC_SQR4_SQ16_Pos)         /*!< 0x00000400 */

+/********************  Bit definition for ADC_DR register  ********************/

+#define ADC_DR_RDATA_Pos                  (0U)

+#define ADC_DR_RDATA_Msk                  (0xFFFFFFFFUL << ADC_DR_RDATA_Pos)   /*!< 0xFFFFFFFF */

+#define ADC_DR_RDATA                      ADC_DR_RDATA_Msk                     /*!< ADC regular Data converted */

+

+/********************  Bit definition for ADC_JSQR register  ********************/

+#define ADC_JSQR_JL_Pos                   (0U)

+#define ADC_JSQR_JL_Msk                   (0x3UL << ADC_JSQR_JL_Pos)           /*!< 0x00000003 */

+#define ADC_JSQR_JL                       ADC_JSQR_JL_Msk                      /*!< ADC injected channel sequence length */

+#define ADC_JSQR_JL_0                     (0x1UL << ADC_JSQR_JL_Pos)           /*!< 0x00000001 */

+#define ADC_JSQR_JL_1                     (0x2UL << ADC_JSQR_JL_Pos)           /*!< 0x00000002 */

+

+#define ADC_JSQR_JEXTSEL_Pos              (2U)

+#define ADC_JSQR_JEXTSEL_Msk              (0x1FUL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x0000007C */

+#define ADC_JSQR_JEXTSEL                  ADC_JSQR_JEXTSEL_Msk                 /*!< ADC external trigger selection for injected group */

+#define ADC_JSQR_JEXTSEL_0                (0x01UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000004 */

+#define ADC_JSQR_JEXTSEL_1                (0x02UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000008 */

+#define ADC_JSQR_JEXTSEL_2                (0x04UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000010 */

+#define ADC_JSQR_JEXTSEL_3                (0x08UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000020 */

+#define ADC_JSQR_JEXTSEL_4                (0x10UL << ADC_JSQR_JEXTSEL_Pos)     /*!< 0x00000040 */

+

+#define ADC_JSQR_JEXTEN_Pos               (7U)

+#define ADC_JSQR_JEXTEN_Msk               (0x3UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000180 */

+#define ADC_JSQR_JEXTEN                   ADC_JSQR_JEXTEN_Msk                  /*!< ADC external trigger enable and polarity selection for injected channels */

+#define ADC_JSQR_JEXTEN_0                 (0x1UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000080 */

+#define ADC_JSQR_JEXTEN_1                 (0x2UL << ADC_JSQR_JEXTEN_Pos)       /*!< 0x00000100 */

+

+#define ADC_JSQR_JSQ1_Pos                 (9U)

+#define ADC_JSQR_JSQ1_Msk                 (0x1FUL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00003E00 */

+#define ADC_JSQR_JSQ1                     ADC_JSQR_JSQ1_Msk                    /*!< ADC 1st conversion in injected sequence */

+#define ADC_JSQR_JSQ1_0                   (0x01UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000200 */

+#define ADC_JSQR_JSQ1_1                   (0x02UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000400 */

+#define ADC_JSQR_JSQ1_2                   (0x04UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00000800 */

+#define ADC_JSQR_JSQ1_3                   (0x08UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00001000 */

+#define ADC_JSQR_JSQ1_4                   (0x10UL << ADC_JSQR_JSQ1_Pos)        /*!< 0x00002000 */

+

+#define ADC_JSQR_JSQ2_Pos                 (15U)

+#define ADC_JSQR_JSQ2_Msk                 (0x1FUL << ADC_JSQR_JSQ2_Pos)        /*!< 0x000F8000 */

+#define ADC_JSQR_JSQ2                     ADC_JSQR_JSQ2_Msk                    /*!< ADC 2nd conversion in injected sequence */

+#define ADC_JSQR_JSQ2_0                   (0x01UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00008000 */

+#define ADC_JSQR_JSQ2_1                   (0x02UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00010000 */

+#define ADC_JSQR_JSQ2_2                   (0x04UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00020000 */

+#define ADC_JSQR_JSQ2_3                   (0x08UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00040000 */

+#define ADC_JSQR_JSQ2_4                   (0x10UL << ADC_JSQR_JSQ2_Pos)        /*!< 0x00080000 */

+

+#define ADC_JSQR_JSQ3_Pos                 (21U)

+#define ADC_JSQR_JSQ3_Msk                 (0x1FUL << ADC_JSQR_JSQ3_Pos)        /*!< 0x03E00000 */

+#define ADC_JSQR_JSQ3                     ADC_JSQR_JSQ3_Msk                    /*!< ADC 3rd conversion in injected sequence */

+#define ADC_JSQR_JSQ3_0                   (0x01UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00200000 */

+#define ADC_JSQR_JSQ3_1                   (0x02UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00400000 */

+#define ADC_JSQR_JSQ3_2                   (0x04UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x00800000 */

+#define ADC_JSQR_JSQ3_3                   (0x08UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x01000000 */

+#define ADC_JSQR_JSQ3_4                   (0x10UL << ADC_JSQR_JSQ3_Pos)        /*!< 0x02000000 */

+

+#define ADC_JSQR_JSQ4_Pos                 (27U)

+#define ADC_JSQR_JSQ4_Msk                 (0x1FUL << ADC_JSQR_JSQ4_Pos)        /*!< 0xF8000000 */

+#define ADC_JSQR_JSQ4                     ADC_JSQR_JSQ4_Msk                    /*!< ADC 4th conversion in injected sequence */

+#define ADC_JSQR_JSQ4_0                   (0x01UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x08000000 */

+#define ADC_JSQR_JSQ4_1                   (0x02UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x10000000 */

+#define ADC_JSQR_JSQ4_2                   (0x04UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x20000000 */

+#define ADC_JSQR_JSQ4_3                   (0x08UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x40000000 */

+#define ADC_JSQR_JSQ4_4                   (0x10UL << ADC_JSQR_JSQ4_Pos)        /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_OFR1 register  ********************/

+#define ADC_OFR1_OFFSET1_Pos              (0U)

+#define ADC_OFR1_OFFSET1_Msk              (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR1_OFFSET1                  ADC_OFR1_OFFSET1_Msk                  /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */

+#define ADC_OFR1_OFFSET1_0                (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */

+#define ADC_OFR1_OFFSET1_1                (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */

+#define ADC_OFR1_OFFSET1_2                (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */

+#define ADC_OFR1_OFFSET1_3                (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */

+#define ADC_OFR1_OFFSET1_4                (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */

+#define ADC_OFR1_OFFSET1_5                (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */

+#define ADC_OFR1_OFFSET1_6                (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */

+#define ADC_OFR1_OFFSET1_7                (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */

+#define ADC_OFR1_OFFSET1_8                (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */

+#define ADC_OFR1_OFFSET1_9                (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */

+#define ADC_OFR1_OFFSET1_10               (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */

+#define ADC_OFR1_OFFSET1_11               (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */

+#define ADC_OFR1_OFFSET1_12               (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */

+#define ADC_OFR1_OFFSET1_13               (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */

+#define ADC_OFR1_OFFSET1_14               (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */

+#define ADC_OFR1_OFFSET1_15               (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */

+#define ADC_OFR1_OFFSET1_16               (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */

+#define ADC_OFR1_OFFSET1_17               (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */

+#define ADC_OFR1_OFFSET1_18               (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */

+#define ADC_OFR1_OFFSET1_19               (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */

+#define ADC_OFR1_OFFSET1_20               (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */

+#define ADC_OFR1_OFFSET1_21               (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */

+#define ADC_OFR1_OFFSET1_22               (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */

+#define ADC_OFR1_OFFSET1_23               (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */

+#define ADC_OFR1_OFFSET1_24               (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */

+#define ADC_OFR1_OFFSET1_25               (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR1_OFFSET1_CH_Pos           (26U)

+#define ADC_OFR1_OFFSET1_CH_Msk           (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR1_OFFSET1_CH               ADC_OFR1_OFFSET1_CH_Msk               /*!< ADC Channel selection for the data offset 1 */

+#define ADC_OFR1_OFFSET1_CH_0             (0x01UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR1_OFFSET1_CH_1             (0x02UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR1_OFFSET1_CH_2             (0x04UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR1_OFFSET1_CH_3             (0x08UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR1_OFFSET1_CH_4             (0x10UL << ADC_OFR1_OFFSET1_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR1_SSATE_Pos                (31U)

+#define ADC_OFR1_SSATE_Msk                (0x1UL << ADC_OFR1_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR1_SSATE                    ADC_OFR1_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR2 register  ********************/

+#define ADC_OFR2_OFFSET2_Pos              (0U)

+#define ADC_OFR2_OFFSET2_Msk              (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR2_OFFSET2                  ADC_OFR2_OFFSET2_Msk                  /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */

+#define ADC_OFR2_OFFSET2_0                (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */

+#define ADC_OFR2_OFFSET2_1                (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */

+#define ADC_OFR2_OFFSET2_2                (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */

+#define ADC_OFR2_OFFSET2_3                (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */

+#define ADC_OFR2_OFFSET2_4                (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */

+#define ADC_OFR2_OFFSET2_5                (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */

+#define ADC_OFR2_OFFSET2_6                (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */

+#define ADC_OFR2_OFFSET2_7                (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */

+#define ADC_OFR2_OFFSET2_8                (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */

+#define ADC_OFR2_OFFSET2_9                (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */

+#define ADC_OFR2_OFFSET2_10               (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */

+#define ADC_OFR2_OFFSET2_11               (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */

+#define ADC_OFR2_OFFSET2_12               (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */

+#define ADC_OFR2_OFFSET2_13               (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */

+#define ADC_OFR2_OFFSET2_14               (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */

+#define ADC_OFR2_OFFSET2_15               (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */

+#define ADC_OFR2_OFFSET2_16               (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */

+#define ADC_OFR2_OFFSET2_17               (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */

+#define ADC_OFR2_OFFSET2_18               (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */

+#define ADC_OFR2_OFFSET2_19               (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */

+#define ADC_OFR2_OFFSET2_20               (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */

+#define ADC_OFR2_OFFSET2_21               (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */

+#define ADC_OFR2_OFFSET2_22               (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */

+#define ADC_OFR2_OFFSET2_23               (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */

+#define ADC_OFR2_OFFSET2_24               (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */

+#define ADC_OFR2_OFFSET2_25               (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR2_OFFSET2_CH_Pos           (26U)

+#define ADC_OFR2_OFFSET2_CH_Msk           (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR2_OFFSET2_CH               ADC_OFR2_OFFSET2_CH_Msk               /*!< ADC Channel selection for the data offset 2 */

+#define ADC_OFR2_OFFSET2_CH_0             (0x01UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR2_OFFSET2_CH_1             (0x02UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR2_OFFSET2_CH_2             (0x04UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR2_OFFSET2_CH_3             (0x08UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR2_OFFSET2_CH_4             (0x10UL << ADC_OFR2_OFFSET2_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR2_SSATE_Pos                (31U)

+#define ADC_OFR2_SSATE_Msk                (0x1UL << ADC_OFR2_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR2_SSATE                    ADC_OFR2_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR3 register  ********************/

+#define ADC_OFR3_OFFSET3_Pos              (0U)

+#define ADC_OFR3_OFFSET3_Msk              (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR3_OFFSET3                  ADC_OFR3_OFFSET3_Msk                  /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */

+#define ADC_OFR3_OFFSET3_0                (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */

+#define ADC_OFR3_OFFSET3_1                (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */

+#define ADC_OFR3_OFFSET3_2                (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */

+#define ADC_OFR3_OFFSET3_3                (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */

+#define ADC_OFR3_OFFSET3_4                (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */

+#define ADC_OFR3_OFFSET3_5                (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */

+#define ADC_OFR3_OFFSET3_6                (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */

+#define ADC_OFR3_OFFSET3_7                (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */

+#define ADC_OFR3_OFFSET3_8                (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */

+#define ADC_OFR3_OFFSET3_9                (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */

+#define ADC_OFR3_OFFSET3_10               (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */

+#define ADC_OFR3_OFFSET3_11               (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */

+#define ADC_OFR3_OFFSET3_12               (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */

+#define ADC_OFR3_OFFSET3_13               (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */

+#define ADC_OFR3_OFFSET3_14               (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */

+#define ADC_OFR3_OFFSET3_15               (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */

+#define ADC_OFR3_OFFSET3_16               (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */

+#define ADC_OFR3_OFFSET3_17               (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */

+#define ADC_OFR3_OFFSET3_18               (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */

+#define ADC_OFR3_OFFSET3_19               (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */

+#define ADC_OFR3_OFFSET3_20               (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */

+#define ADC_OFR3_OFFSET3_21               (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */

+#define ADC_OFR3_OFFSET3_22               (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */

+#define ADC_OFR3_OFFSET3_23               (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */

+#define ADC_OFR3_OFFSET3_24               (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */

+#define ADC_OFR3_OFFSET3_25               (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR3_OFFSET3_CH_Pos           (26U)

+#define ADC_OFR3_OFFSET3_CH_Msk           (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR3_OFFSET3_CH               ADC_OFR3_OFFSET3_CH_Msk               /*!< ADC Channel selection for the data offset 3 */

+#define ADC_OFR3_OFFSET3_CH_0             (0x01UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR3_OFFSET3_CH_1             (0x02UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR3_OFFSET3_CH_2             (0x04UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR3_OFFSET3_CH_3             (0x08UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR3_OFFSET3_CH_4             (0x10UL << ADC_OFR3_OFFSET3_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR3_SSATE_Pos                (31U)

+#define ADC_OFR3_SSATE_Msk                (0x1UL << ADC_OFR3_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR3_SSATE                    ADC_OFR3_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_OFR4 register  ********************/

+#define ADC_OFR4_OFFSET4_Pos              (0U)

+#define ADC_OFR4_OFFSET4_Msk              (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */

+#define ADC_OFR4_OFFSET4                  ADC_OFR4_OFFSET4_Msk                  /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */

+#define ADC_OFR4_OFFSET4_0                (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */

+#define ADC_OFR4_OFFSET4_1                (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */

+#define ADC_OFR4_OFFSET4_2                (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */

+#define ADC_OFR4_OFFSET4_3                (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */

+#define ADC_OFR4_OFFSET4_4                (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */

+#define ADC_OFR4_OFFSET4_5                (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */

+#define ADC_OFR4_OFFSET4_6                (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */

+#define ADC_OFR4_OFFSET4_7                (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */

+#define ADC_OFR4_OFFSET4_8                (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */

+#define ADC_OFR4_OFFSET4_9                (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */

+#define ADC_OFR4_OFFSET4_10               (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */

+#define ADC_OFR4_OFFSET4_11               (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */

+#define ADC_OFR4_OFFSET4_12               (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */

+#define ADC_OFR4_OFFSET4_13               (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */

+#define ADC_OFR4_OFFSET4_14               (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */

+#define ADC_OFR4_OFFSET4_15               (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */

+#define ADC_OFR4_OFFSET4_16               (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */

+#define ADC_OFR4_OFFSET4_17               (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */

+#define ADC_OFR4_OFFSET4_18               (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */

+#define ADC_OFR4_OFFSET4_19               (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */

+#define ADC_OFR4_OFFSET4_20               (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */

+#define ADC_OFR4_OFFSET4_21               (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */

+#define ADC_OFR4_OFFSET4_22               (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */

+#define ADC_OFR4_OFFSET4_23               (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */

+#define ADC_OFR4_OFFSET4_24               (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */

+#define ADC_OFR4_OFFSET4_25               (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */

+

+#define ADC_OFR4_OFFSET4_CH_Pos           (26U)

+#define ADC_OFR4_OFFSET4_CH_Msk           (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x7C000000 */

+#define ADC_OFR4_OFFSET4_CH               ADC_OFR4_OFFSET4_CH_Msk               /*!< ADC Channel selection for the data offset 4 */

+#define ADC_OFR4_OFFSET4_CH_0             (0x01UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x04000000 */

+#define ADC_OFR4_OFFSET4_CH_1             (0x02UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x08000000 */

+#define ADC_OFR4_OFFSET4_CH_2             (0x04UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x10000000 */

+#define ADC_OFR4_OFFSET4_CH_3             (0x08UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x20000000 */

+#define ADC_OFR4_OFFSET4_CH_4             (0x10UL << ADC_OFR4_OFFSET4_CH_Pos)   /*!< 0x40000000 */

+

+#define ADC_OFR4_SSATE_Pos                (31U)

+#define ADC_OFR4_SSATE_Msk                (0x1UL << ADC_OFR4_SSATE_Pos)         /*!< 0x80000000 */

+#define ADC_OFR4_SSATE                    ADC_OFR4_SSATE_Msk                    /*!< ADC Signed saturation Enable */

+

+

+/********************  Bit definition for ADC_JDR1 register  ********************/

+#define ADC_JDR1_JDATA_Pos                (0U)

+#define ADC_JDR1_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR1_JDATA                    ADC_JDR1_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR1_JDATA_0                  (0x00000001UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR1_JDATA_1                  (0x00000002UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR1_JDATA_2                  (0x00000004UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR1_JDATA_3                  (0x00000008UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR1_JDATA_4                  (0x00000010UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR1_JDATA_5                  (0x00000020UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR1_JDATA_6                  (0x00000040UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR1_JDATA_7                  (0x00000080UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR1_JDATA_8                  (0x00000100UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR1_JDATA_9                  (0x00000200UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR1_JDATA_10                 (0x00000400UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR1_JDATA_11                 (0x00000800UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR1_JDATA_12                 (0x00001000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR1_JDATA_13                 (0x00002000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR1_JDATA_14                 (0x00004000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR1_JDATA_15                 (0x00008000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR1_JDATA_16                 (0x00010000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR1_JDATA_17                 (0x00020000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR1_JDATA_18                 (0x00040000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR1_JDATA_19                 (0x00080000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR1_JDATA_20                 (0x00100000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR1_JDATA_21                 (0x00200000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR1_JDATA_22                 (0x00400000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR1_JDATA_23                 (0x00800000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR1_JDATA_24                 (0x01000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR1_JDATA_25                 (0x02000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR1_JDATA_26                 (0x04000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR1_JDATA_27                 (0x08000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR1_JDATA_28                 (0x10000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR1_JDATA_29                 (0x20000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR1_JDATA_30                 (0x40000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR1_JDATA_31                 (0x80000000UL << ADC_JDR1_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR2 register  ********************/

+#define ADC_JDR2_JDATA_Pos                (0U)

+#define ADC_JDR2_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR2_JDATA                    ADC_JDR2_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR2_JDATA_0                  (0x00000001UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR2_JDATA_1                  (0x00000002UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR2_JDATA_2                  (0x00000004UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR2_JDATA_3                  (0x00000008UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR2_JDATA_4                  (0x00000010UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR2_JDATA_5                  (0x00000020UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR2_JDATA_6                  (0x00000040UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR2_JDATA_7                  (0x00000080UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR2_JDATA_8                  (0x00000100UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR2_JDATA_9                  (0x00000200UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR2_JDATA_10                 (0x00000400UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR2_JDATA_11                 (0x00000800UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR2_JDATA_12                 (0x00001000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR2_JDATA_13                 (0x00002000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR2_JDATA_14                 (0x00004000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR2_JDATA_15                 (0x00008000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR2_JDATA_16                 (0x00010000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR2_JDATA_17                 (0x00020000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR2_JDATA_18                 (0x00040000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR2_JDATA_19                 (0x00080000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR2_JDATA_20                 (0x00100000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR2_JDATA_21                 (0x00200000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR2_JDATA_22                 (0x00400000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR2_JDATA_23                 (0x00800000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR2_JDATA_24                 (0x01000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR2_JDATA_25                 (0x02000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR2_JDATA_26                 (0x04000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR2_JDATA_27                 (0x08000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR2_JDATA_28                 (0x10000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR2_JDATA_29                 (0x20000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR2_JDATA_30                 (0x40000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR2_JDATA_31                 (0x80000000UL << ADC_JDR2_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR3 register  ********************/

+#define ADC_JDR3_JDATA_Pos                (0U)

+#define ADC_JDR3_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR3_JDATA                    ADC_JDR3_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR3_JDATA_0                  (0x00000001UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR3_JDATA_1                  (0x00000002UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR3_JDATA_2                  (0x00000004UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR3_JDATA_3                  (0x00000008UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR3_JDATA_4                  (0x00000010UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR3_JDATA_5                  (0x00000020UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR3_JDATA_6                  (0x00000040UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR3_JDATA_7                  (0x00000080UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR3_JDATA_8                  (0x00000100UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR3_JDATA_9                  (0x00000200UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR3_JDATA_10                 (0x00000400UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR3_JDATA_11                 (0x00000800UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR3_JDATA_12                 (0x00001000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR3_JDATA_13                 (0x00002000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR3_JDATA_14                 (0x00004000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR3_JDATA_15                 (0x00008000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR3_JDATA_16                 (0x00010000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR3_JDATA_17                 (0x00020000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR3_JDATA_18                 (0x00040000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR3_JDATA_19                 (0x00080000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR3_JDATA_20                 (0x00100000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR3_JDATA_21                 (0x00200000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR3_JDATA_22                 (0x00400000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR3_JDATA_23                 (0x00800000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR3_JDATA_24                 (0x01000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR3_JDATA_25                 (0x02000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR3_JDATA_26                 (0x04000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR3_JDATA_27                 (0x08000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR3_JDATA_28                 (0x10000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR3_JDATA_29                 (0x20000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR3_JDATA_30                 (0x40000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR3_JDATA_31                 (0x80000000UL << ADC_JDR3_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_JDR4 register  ********************/

+#define ADC_JDR4_JDATA_Pos                (0U)

+#define ADC_JDR4_JDATA_Msk                (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos)  /*!< 0xFFFFFFFF */

+#define ADC_JDR4_JDATA                    ADC_JDR4_JDATA_Msk                    /*!< ADC Injected DATA */

+#define ADC_JDR4_JDATA_0                  (0x00000001UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000001 */

+#define ADC_JDR4_JDATA_1                  (0x00000002UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000002 */

+#define ADC_JDR4_JDATA_2                  (0x00000004UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000004 */

+#define ADC_JDR4_JDATA_3                  (0x00000008UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000008 */

+#define ADC_JDR4_JDATA_4                  (0x00000010UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000010 */

+#define ADC_JDR4_JDATA_5                  (0x00000020UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000020 */

+#define ADC_JDR4_JDATA_6                  (0x00000040UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000040 */

+#define ADC_JDR4_JDATA_7                  (0x00000080UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000080 */

+#define ADC_JDR4_JDATA_8                  (0x00000100UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000100 */

+#define ADC_JDR4_JDATA_9                  (0x00000200UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000200 */

+#define ADC_JDR4_JDATA_10                 (0x00000400UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000400 */

+#define ADC_JDR4_JDATA_11                 (0x00000800UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00000800 */

+#define ADC_JDR4_JDATA_12                 (0x00001000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00001000 */

+#define ADC_JDR4_JDATA_13                 (0x00002000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00002000 */

+#define ADC_JDR4_JDATA_14                 (0x00004000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00004000 */

+#define ADC_JDR4_JDATA_15                 (0x00008000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00008000 */

+#define ADC_JDR4_JDATA_16                 (0x00010000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00010000 */

+#define ADC_JDR4_JDATA_17                 (0x00020000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00020000 */

+#define ADC_JDR4_JDATA_18                 (0x00040000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00040000 */

+#define ADC_JDR4_JDATA_19                 (0x00080000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00080000 */

+#define ADC_JDR4_JDATA_20                 (0x00100000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00100000 */

+#define ADC_JDR4_JDATA_21                 (0x00200000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00200000 */

+#define ADC_JDR4_JDATA_22                 (0x00400000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00400000 */

+#define ADC_JDR4_JDATA_23                 (0x00800000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x00800000 */

+#define ADC_JDR4_JDATA_24                 (0x01000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x01000000 */

+#define ADC_JDR4_JDATA_25                 (0x02000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x02000000 */

+#define ADC_JDR4_JDATA_26                 (0x04000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x04000000 */

+#define ADC_JDR4_JDATA_27                 (0x08000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x08000000 */

+#define ADC_JDR4_JDATA_28                 (0x10000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x10000000 */

+#define ADC_JDR4_JDATA_29                 (0x20000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x20000000 */

+#define ADC_JDR4_JDATA_30                 (0x40000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x40000000 */

+#define ADC_JDR4_JDATA_31                 (0x80000000UL << ADC_JDR4_JDATA_Pos)  /*!< 0x80000000 */

+

+/********************  Bit definition for ADC_AWD2CR register  ********************/

+#define ADC_AWD2CR_AWD2CH_Pos             (0U)

+#define ADC_AWD2CR_AWD2CH_Msk             (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x000FFFFF */

+#define ADC_AWD2CR_AWD2CH                 ADC_AWD2CR_AWD2CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */

+#define ADC_AWD2CR_AWD2CH_0               (0x00001UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000001 */

+#define ADC_AWD2CR_AWD2CH_1               (0x00002UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000002 */

+#define ADC_AWD2CR_AWD2CH_2               (0x00004UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000004 */

+#define ADC_AWD2CR_AWD2CH_3               (0x00008UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000008 */

+#define ADC_AWD2CR_AWD2CH_4               (0x00010UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000010 */

+#define ADC_AWD2CR_AWD2CH_5               (0x00020UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000020 */

+#define ADC_AWD2CR_AWD2CH_6               (0x00040UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000040 */

+#define ADC_AWD2CR_AWD2CH_7               (0x00080UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000080 */

+#define ADC_AWD2CR_AWD2CH_8               (0x00100UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000100 */

+#define ADC_AWD2CR_AWD2CH_9               (0x00200UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000200 */

+#define ADC_AWD2CR_AWD2CH_10              (0x00400UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000400 */

+#define ADC_AWD2CR_AWD2CH_11              (0x00800UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00000800 */

+#define ADC_AWD2CR_AWD2CH_12              (0x01000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00001000 */

+#define ADC_AWD2CR_AWD2CH_13              (0x02000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00002000 */

+#define ADC_AWD2CR_AWD2CH_14              (0x04000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00004000 */

+#define ADC_AWD2CR_AWD2CH_15              (0x08000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00008000 */

+#define ADC_AWD2CR_AWD2CH_16              (0x10000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00010000 */

+#define ADC_AWD2CR_AWD2CH_17              (0x20000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00020000 */

+#define ADC_AWD2CR_AWD2CH_18              (0x40000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00040000 */

+#define ADC_AWD2CR_AWD2CH_19              (0x80000UL << ADC_AWD2CR_AWD2CH_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_AWD3CR register  ********************/

+#define ADC_AWD3CR_AWD3CH_Pos             (0U)

+#define ADC_AWD3CR_AWD3CH_Msk             (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x000FFFFF */

+#define ADC_AWD3CR_AWD3CH                 ADC_AWD3CR_AWD3CH_Msk                 /*!< ADC Analog watchdog 2 channel selection */

+#define ADC_AWD3CR_AWD3CH_0               (0x00001UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000001 */

+#define ADC_AWD3CR_AWD3CH_1               (0x00002UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000002 */

+#define ADC_AWD3CR_AWD3CH_2               (0x00004UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000004 */

+#define ADC_AWD3CR_AWD3CH_3               (0x00008UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000008 */

+#define ADC_AWD3CR_AWD3CH_4               (0x00010UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000010 */

+#define ADC_AWD3CR_AWD3CH_5               (0x00020UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000020 */

+#define ADC_AWD3CR_AWD3CH_6               (0x00040UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000040 */

+#define ADC_AWD3CR_AWD3CH_7               (0x00080UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000080 */

+#define ADC_AWD3CR_AWD3CH_8               (0x00100UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000100 */

+#define ADC_AWD3CR_AWD3CH_9               (0x00200UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000200 */

+#define ADC_AWD3CR_AWD3CH_10              (0x00400UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000400 */

+#define ADC_AWD3CR_AWD3CH_11              (0x00800UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00000800 */

+#define ADC_AWD3CR_AWD3CH_12              (0x01000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00001000 */

+#define ADC_AWD3CR_AWD3CH_13              (0x02000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00002000 */

+#define ADC_AWD3CR_AWD3CH_14              (0x04000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00004000 */

+#define ADC_AWD3CR_AWD3CH_15              (0x08000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00008000 */

+#define ADC_AWD3CR_AWD3CH_16              (0x10000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00010000 */

+#define ADC_AWD3CR_AWD3CH_17              (0x20000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00020000 */

+#define ADC_AWD3CR_AWD3CH_18              (0x40000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00040000 */

+#define ADC_AWD3CR_AWD3CH_19              (0x80000UL << ADC_AWD3CR_AWD3CH_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_DIFSEL register  ********************/

+#define ADC_DIFSEL_DIFSEL_Pos             (0U)

+#define ADC_DIFSEL_DIFSEL_Msk             (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x000FFFFF */

+#define ADC_DIFSEL_DIFSEL                 ADC_DIFSEL_DIFSEL_Msk                 /*!< ADC differential modes for channels 1 to 18 */

+#define ADC_DIFSEL_DIFSEL_0               (0x00001UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000001 */

+#define ADC_DIFSEL_DIFSEL_1               (0x00002UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000002 */

+#define ADC_DIFSEL_DIFSEL_2               (0x00004UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000004 */

+#define ADC_DIFSEL_DIFSEL_3               (0x00008UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000008 */

+#define ADC_DIFSEL_DIFSEL_4               (0x00010UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000010 */

+#define ADC_DIFSEL_DIFSEL_5               (0x00020UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000020 */

+#define ADC_DIFSEL_DIFSEL_6               (0x00040UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000040 */

+#define ADC_DIFSEL_DIFSEL_7               (0x00080UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000080 */

+#define ADC_DIFSEL_DIFSEL_8               (0x00100UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000100 */

+#define ADC_DIFSEL_DIFSEL_9               (0x00200UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000200 */

+#define ADC_DIFSEL_DIFSEL_10              (0x00400UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000400 */

+#define ADC_DIFSEL_DIFSEL_11              (0x00800UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00000800 */

+#define ADC_DIFSEL_DIFSEL_12              (0x01000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00001000 */

+#define ADC_DIFSEL_DIFSEL_13              (0x02000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00002000 */

+#define ADC_DIFSEL_DIFSEL_14              (0x04000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00004000 */

+#define ADC_DIFSEL_DIFSEL_15              (0x08000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00008000 */

+#define ADC_DIFSEL_DIFSEL_16              (0x10000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00010000 */

+#define ADC_DIFSEL_DIFSEL_17              (0x20000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00020000 */

+#define ADC_DIFSEL_DIFSEL_18              (0x40000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00040000 */

+#define ADC_DIFSEL_DIFSEL_19              (0x80000UL << ADC_DIFSEL_DIFSEL_Pos)  /*!< 0x00080000 */

+

+/********************  Bit definition for ADC_CALFACT register  ********************/

+#define ADC_CALFACT_CALFACT_S_Pos         (0U)

+#define ADC_CALFACT_CALFACT_S_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */

+#define ADC_CALFACT_CALFACT_S             ADC_CALFACT_CALFACT_S_Msk              /*!< ADC calibration factors in single-ended mode */

+#define ADC_CALFACT_CALFACT_S_0           (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */

+#define ADC_CALFACT_CALFACT_S_1           (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */

+#define ADC_CALFACT_CALFACT_S_2           (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */

+#define ADC_CALFACT_CALFACT_S_3           (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */

+#define ADC_CALFACT_CALFACT_S_4           (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */

+#define ADC_CALFACT_CALFACT_S_5           (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */

+#define ADC_CALFACT_CALFACT_S_6           (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */

+#define ADC_CALFACT_CALFACT_S_7           (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */

+#define ADC_CALFACT_CALFACT_S_8           (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */

+#define ADC_CALFACT_CALFACT_S_9           (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */

+#define ADC_CALFACT_CALFACT_S_10          (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */

+#define ADC_CALFACT_CALFACT_D_Pos         (16U)

+#define ADC_CALFACT_CALFACT_D_Msk         (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */

+#define ADC_CALFACT_CALFACT_D             ADC_CALFACT_CALFACT_D_Msk              /*!< ADC calibration factors in differential mode */

+#define ADC_CALFACT_CALFACT_D_0           (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */

+#define ADC_CALFACT_CALFACT_D_1           (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */

+#define ADC_CALFACT_CALFACT_D_2           (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */

+#define ADC_CALFACT_CALFACT_D_3           (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */

+#define ADC_CALFACT_CALFACT_D_4           (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */

+#define ADC_CALFACT_CALFACT_D_5           (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */

+#define ADC_CALFACT_CALFACT_D_6           (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */

+#define ADC_CALFACT_CALFACT_D_7           (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */

+#define ADC_CALFACT_CALFACT_D_8           (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */

+#define ADC_CALFACT_CALFACT_D_9           (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */

+#define ADC_CALFACT_CALFACT_D_10          (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */

+

+/********************  Bit definition for ADC_CALFACT2 register  ********************/

+#define ADC_CALFACT2_LINCALFACT_Pos       (0U)

+#define ADC_CALFACT2_LINCALFACT_Msk       (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */

+#define ADC_CALFACT2_LINCALFACT           ADC_CALFACT2_LINCALFACT_Msk                   /*!< ADC Linearity calibration factors */

+#define ADC_CALFACT2_LINCALFACT_0         (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */

+#define ADC_CALFACT2_LINCALFACT_1         (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */

+#define ADC_CALFACT2_LINCALFACT_2         (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */

+#define ADC_CALFACT2_LINCALFACT_3         (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */

+#define ADC_CALFACT2_LINCALFACT_4         (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */

+#define ADC_CALFACT2_LINCALFACT_5         (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */

+#define ADC_CALFACT2_LINCALFACT_6         (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */

+#define ADC_CALFACT2_LINCALFACT_7         (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */

+#define ADC_CALFACT2_LINCALFACT_8         (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */

+#define ADC_CALFACT2_LINCALFACT_9         (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */

+#define ADC_CALFACT2_LINCALFACT_10        (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */

+#define ADC_CALFACT2_LINCALFACT_11        (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */

+#define ADC_CALFACT2_LINCALFACT_12        (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */

+#define ADC_CALFACT2_LINCALFACT_13        (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */

+#define ADC_CALFACT2_LINCALFACT_14        (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */

+#define ADC_CALFACT2_LINCALFACT_15        (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */

+#define ADC_CALFACT2_LINCALFACT_16        (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */

+#define ADC_CALFACT2_LINCALFACT_17        (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */

+#define ADC_CALFACT2_LINCALFACT_18        (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */

+#define ADC_CALFACT2_LINCALFACT_19        (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */

+#define ADC_CALFACT2_LINCALFACT_20        (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */

+#define ADC_CALFACT2_LINCALFACT_21        (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */

+#define ADC_CALFACT2_LINCALFACT_22        (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */

+#define ADC_CALFACT2_LINCALFACT_23        (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */

+#define ADC_CALFACT2_LINCALFACT_24        (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */

+#define ADC_CALFACT2_LINCALFACT_25        (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */

+#define ADC_CALFACT2_LINCALFACT_26        (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */

+#define ADC_CALFACT2_LINCALFACT_27        (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */

+#define ADC_CALFACT2_LINCALFACT_28        (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */

+#define ADC_CALFACT2_LINCALFACT_29        (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */

+

+/*************************  ADC Common registers  *****************************/

+/********************  Bit definition for ADC_CSR register  ********************/

+#define ADC_CSR_ADRDY_MST_Pos             (0U)

+#define ADC_CSR_ADRDY_MST_Msk             (0x1UL << ADC_CSR_ADRDY_MST_Pos)     /*!< 0x00000001 */

+#define ADC_CSR_ADRDY_MST                 ADC_CSR_ADRDY_MST_Msk                /*!< Master ADC ready */

+#define ADC_CSR_EOSMP_MST_Pos             (1U)

+#define ADC_CSR_EOSMP_MST_Msk             (0x1UL << ADC_CSR_EOSMP_MST_Pos)     /*!< 0x00000002 */

+#define ADC_CSR_EOSMP_MST                 ADC_CSR_EOSMP_MST_Msk                /*!< End of sampling phase flag of the master ADC */

+#define ADC_CSR_EOC_MST_Pos               (2U)

+#define ADC_CSR_EOC_MST_Msk               (0x1UL << ADC_CSR_EOC_MST_Pos)       /*!< 0x00000004 */

+#define ADC_CSR_EOC_MST                   ADC_CSR_EOC_MST_Msk                  /*!< End of regular conversion of the master ADC */

+#define ADC_CSR_EOS_MST_Pos               (3U)

+#define ADC_CSR_EOS_MST_Msk               (0x1UL << ADC_CSR_EOS_MST_Pos)       /*!< 0x00000008 */

+#define ADC_CSR_EOS_MST                   ADC_CSR_EOS_MST_Msk                  /*!< End of regular sequence flag of the master ADC */

+#define ADC_CSR_OVR_MST_Pos               (4U)

+#define ADC_CSR_OVR_MST_Msk               (0x1UL << ADC_CSR_OVR_MST_Pos)       /*!< 0x00000010 */

+#define ADC_CSR_OVR_MST                   ADC_CSR_OVR_MST_Msk                  /*!< Overrun flag of the master ADC */

+#define ADC_CSR_JEOC_MST_Pos              (5U)

+#define ADC_CSR_JEOC_MST_Msk              (0x1UL << ADC_CSR_JEOC_MST_Pos)      /*!< 0x00000020 */

+#define ADC_CSR_JEOC_MST                  ADC_CSR_JEOC_MST_Msk                 /*!< End of injected conversion of the master ADC */

+#define ADC_CSR_JEOS_MST_Pos              (6U)

+#define ADC_CSR_JEOS_MST_Msk              (0x1UL << ADC_CSR_JEOS_MST_Pos)      /*!< 0x00000040 */

+#define ADC_CSR_JEOS_MST                  ADC_CSR_JEOS_MST_Msk                 /*!< End of injected sequence flag of the master ADC */

+#define ADC_CSR_AWD1_MST_Pos              (7U)

+#define ADC_CSR_AWD1_MST_Msk              (0x1UL << ADC_CSR_AWD1_MST_Pos)      /*!< 0x00000080 */

+#define ADC_CSR_AWD1_MST                  ADC_CSR_AWD1_MST_Msk                 /*!< Analog watchdog 1 flag of the master ADC */

+#define ADC_CSR_AWD2_MST_Pos              (8U)

+#define ADC_CSR_AWD2_MST_Msk              (0x1UL << ADC_CSR_AWD2_MST_Pos)      /*!< 0x00000100 */

+#define ADC_CSR_AWD2_MST                  ADC_CSR_AWD2_MST_Msk                 /*!< Analog watchdog 2 flag of the master ADC */

+#define ADC_CSR_AWD3_MST_Pos              (9U)

+#define ADC_CSR_AWD3_MST_Msk              (0x1UL << ADC_CSR_AWD3_MST_Pos)      /*!< 0x00000200 */

+#define ADC_CSR_AWD3_MST                  ADC_CSR_AWD3_MST_Msk                 /*!< Analog watchdog 3 flag of the master ADC */

+#define ADC_CSR_JQOVF_MST_Pos             (10U)

+#define ADC_CSR_JQOVF_MST_Msk             (0x1UL << ADC_CSR_JQOVF_MST_Pos)     /*!< 0x00000400 */

+#define ADC_CSR_JQOVF_MST                 ADC_CSR_JQOVF_MST_Msk                /*!< Injected context queue overflow flag of the master ADC */

+#define ADC_CSR_ADRDY_SLV_Pos             (16U)

+#define ADC_CSR_ADRDY_SLV_Msk             (0x1UL << ADC_CSR_ADRDY_SLV_Pos)     /*!< 0x00010000 */

+#define ADC_CSR_ADRDY_SLV                 ADC_CSR_ADRDY_SLV_Msk                /*!< Slave ADC ready */

+#define ADC_CSR_EOSMP_SLV_Pos             (17U)

+#define ADC_CSR_EOSMP_SLV_Msk             (0x1UL << ADC_CSR_EOSMP_SLV_Pos)     /*!< 0x00020000 */

+#define ADC_CSR_EOSMP_SLV                 ADC_CSR_EOSMP_SLV_Msk                /*!< End of sampling phase flag of the slave ADC */

+#define ADC_CSR_EOC_SLV_Pos               (18U)

+#define ADC_CSR_EOC_SLV_Msk               (0x1UL << ADC_CSR_EOC_SLV_Pos)       /*!< 0x00040000 */

+#define ADC_CSR_EOC_SLV                   ADC_CSR_EOC_SLV_Msk                  /*!< End of regular conversion of the slave ADC */

+#define ADC_CSR_EOS_SLV_Pos               (19U)

+#define ADC_CSR_EOS_SLV_Msk               (0x1UL << ADC_CSR_EOS_SLV_Pos)       /*!< 0x00080000 */

+#define ADC_CSR_EOS_SLV                   ADC_CSR_EOS_SLV_Msk                  /*!< End of regular sequence flag of the slave ADC */

+#define ADC_CSR_OVR_SLV_Pos               (20U)

+#define ADC_CSR_OVR_SLV_Msk               (0x1UL << ADC_CSR_OVR_SLV_Pos)       /*!< 0x00100000 */

+#define ADC_CSR_OVR_SLV                   ADC_CSR_OVR_SLV_Msk                  /*!< Overrun flag of the slave ADC */

+#define ADC_CSR_JEOC_SLV_Pos              (21U)

+#define ADC_CSR_JEOC_SLV_Msk              (0x1UL << ADC_CSR_JEOC_SLV_Pos)      /*!< 0x00200000 */

+#define ADC_CSR_JEOC_SLV                  ADC_CSR_JEOC_SLV_Msk                 /*!< End of injected conversion of the slave ADC */

+#define ADC_CSR_JEOS_SLV_Pos              (22U)

+#define ADC_CSR_JEOS_SLV_Msk              (0x1UL << ADC_CSR_JEOS_SLV_Pos)      /*!< 0x00400000 */

+#define ADC_CSR_JEOS_SLV                  ADC_CSR_JEOS_SLV_Msk                 /*!< End of injected sequence flag of the slave ADC */

+#define ADC_CSR_AWD1_SLV_Pos              (23U)

+#define ADC_CSR_AWD1_SLV_Msk              (0x1UL << ADC_CSR_AWD1_SLV_Pos)      /*!< 0x00800000 */

+#define ADC_CSR_AWD1_SLV                  ADC_CSR_AWD1_SLV_Msk                 /*!< Analog watchdog 1 flag of the slave ADC */

+#define ADC_CSR_AWD2_SLV_Pos              (24U)

+#define ADC_CSR_AWD2_SLV_Msk              (0x1UL << ADC_CSR_AWD2_SLV_Pos)      /*!< 0x01000000 */

+#define ADC_CSR_AWD2_SLV                  ADC_CSR_AWD2_SLV_Msk                 /*!< Analog watchdog 2 flag of the slave ADC */

+#define ADC_CSR_AWD3_SLV_Pos              (25U)

+#define ADC_CSR_AWD3_SLV_Msk              (0x1UL << ADC_CSR_AWD3_SLV_Pos)      /*!< 0x02000000 */

+#define ADC_CSR_AWD3_SLV                  ADC_CSR_AWD3_SLV_Msk                 /*!< Analog watchdog 3 flag of the slave ADC */

+#define ADC_CSR_JQOVF_SLV_Pos             (26U)

+#define ADC_CSR_JQOVF_SLV_Msk             (0x1UL << ADC_CSR_JQOVF_SLV_Pos)     /*!< 0x04000000 */

+#define ADC_CSR_JQOVF_SLV                 ADC_CSR_JQOVF_SLV_Msk                /*!< Injected context queue overflow flag of the slave ADC */

+

+/********************  Bit definition for ADC_CCR register  ********************/

+#define ADC_CCR_DUAL_Pos                  (0U)

+#define ADC_CCR_DUAL_Msk                  (0x1FUL << ADC_CCR_DUAL_Pos)          /*!< 0x0000001F */

+#define ADC_CCR_DUAL                      ADC_CCR_DUAL_Msk                      /*!< Dual ADC mode selection */

+#define ADC_CCR_DUAL_0                    (0x01UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000001 */

+#define ADC_CCR_DUAL_1                    (0x02UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000002 */

+#define ADC_CCR_DUAL_2                    (0x04UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000004 */

+#define ADC_CCR_DUAL_3                    (0x08UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000008 */

+#define ADC_CCR_DUAL_4                    (0x10UL << ADC_CCR_DUAL_Pos)          /*!< 0x00000010 */

+

+#define ADC_CCR_DELAY_Pos                 (8U)

+#define ADC_CCR_DELAY_Msk                 (0xFUL << ADC_CCR_DELAY_Pos)          /*!< 0x00000F00 */

+#define ADC_CCR_DELAY                     ADC_CCR_DELAY_Msk                     /*!< Delay between 2 sampling phases */

+#define ADC_CCR_DELAY_0                   (0x1UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000100 */

+#define ADC_CCR_DELAY_1                   (0x2UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000200 */

+#define ADC_CCR_DELAY_2                   (0x4UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000400 */

+#define ADC_CCR_DELAY_3                   (0x8UL << ADC_CCR_DELAY_Pos)          /*!< 0x00000800 */

+

+

+#define ADC_CCR_DAMDF_Pos                 (14U)

+#define ADC_CCR_DAMDF_Msk                 (0x3UL << ADC_CCR_DAMDF_Pos)          /*!< 0x0000C000 */

+#define ADC_CCR_DAMDF                     ADC_CCR_DAMDF_Msk                     /*!< Dual ADC mode Data format */

+#define ADC_CCR_DAMDF_0                   (0x1UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00004000 */

+#define ADC_CCR_DAMDF_1                   (0x2UL << ADC_CCR_DAMDF_Pos)          /*!< 0x00008000 */

+

+#define ADC_CCR_CKMODE_Pos                (16U)

+#define ADC_CCR_CKMODE_Msk                (0x3UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00030000 */

+#define ADC_CCR_CKMODE                    ADC_CCR_CKMODE_Msk                    /*!< ADC clock mode */

+#define ADC_CCR_CKMODE_0                  (0x1UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00010000 */

+#define ADC_CCR_CKMODE_1                  (0x2UL << ADC_CCR_CKMODE_Pos)         /*!< 0x00020000 */

+

+#define ADC_CCR_PRESC_Pos                 (18U)

+#define ADC_CCR_PRESC_Msk                 (0xFUL << ADC_CCR_PRESC_Pos)          /*!< 0x003C0000 */

+#define ADC_CCR_PRESC                     ADC_CCR_PRESC_Msk                     /*!< ADC prescaler */

+#define ADC_CCR_PRESC_0                   (0x1UL << ADC_CCR_PRESC_Pos)          /*!< 0x00040000 */

+#define ADC_CCR_PRESC_1                   (0x2UL << ADC_CCR_PRESC_Pos)          /*!< 0x00080000 */

+#define ADC_CCR_PRESC_2                   (0x4UL << ADC_CCR_PRESC_Pos)          /*!< 0x00100000 */

+#define ADC_CCR_PRESC_3                   (0x8UL << ADC_CCR_PRESC_Pos)          /*!< 0x00200000 */

+

+#define ADC_CCR_VREFEN_Pos                (22U)

+#define ADC_CCR_VREFEN_Msk                (0x1UL << ADC_CCR_VREFEN_Pos)         /*!< 0x00400000 */

+#define ADC_CCR_VREFEN                    ADC_CCR_VREFEN_Msk                    /*!< VREFINT enable */

+#define ADC_CCR_TSEN_Pos                  (23U)

+#define ADC_CCR_TSEN_Msk                  (0x1UL << ADC_CCR_TSEN_Pos)           /*!< 0x00800000 */

+#define ADC_CCR_TSEN                      ADC_CCR_TSEN_Msk                      /*!< Temperature sensor enable */

+#define ADC_CCR_VBATEN_Pos                (24U)

+#define ADC_CCR_VBATEN_Msk                (0x1UL << ADC_CCR_VBATEN_Pos)         /*!< 0x01000000 */

+#define ADC_CCR_VBATEN                    ADC_CCR_VBATEN_Msk                    /*!< VBAT enable */

+

+/********************  Bit definition for ADC_CDR register  *******************/

+#define ADC_CDR_RDATA_MST_Pos             (0U)

+#define ADC_CDR_RDATA_MST_Msk             (0xFFFFUL << ADC_CDR_RDATA_MST_Pos)   /*!< 0x0000FFFF */

+#define ADC_CDR_RDATA_MST                 ADC_CDR_RDATA_MST_Msk                 /*!< ADC multimode master group regular conversion data */

+

+#define ADC_CDR_RDATA_SLV_Pos             (16U)

+#define ADC_CDR_RDATA_SLV_Msk             (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos)   /*!< 0xFFFF0000 */

+#define ADC_CDR_RDATA_SLV                 ADC_CDR_RDATA_SLV_Msk                 /*!< ADC multimode slave group regular conversion data */

+

+/********************  Bit definition for ADC_CDR2 register  ******************/

+#define ADC_CDR2_RDATA_ALT_Pos            (0U)

+#define ADC_CDR2_RDATA_ALT_Msk            (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */

+#define ADC_CDR2_RDATA_ALT                ADC_CDR2_RDATA_ALT_Msk                   /*!< Regular data of the master/slave alternated ADCs */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                   VREFBUF                                  */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for VREFBUF_CSR register  ****************/

+#define VREFBUF_CSR_ENVR_Pos        (0U)

+#define VREFBUF_CSR_ENVR_Msk        (0x1UL << VREFBUF_CSR_ENVR_Pos)            /*!< 0x00000001 */

+#define VREFBUF_CSR_ENVR            VREFBUF_CSR_ENVR_Msk                       /*!<Voltage reference buffer enable */

+#define VREFBUF_CSR_HIZ_Pos         (1U)

+#define VREFBUF_CSR_HIZ_Msk         (0x1UL << VREFBUF_CSR_HIZ_Pos)             /*!< 0x00000002 */

+#define VREFBUF_CSR_HIZ             VREFBUF_CSR_HIZ_Msk                        /*!<High impedance mode             */

+#define VREFBUF_CSR_VRR_Pos         (3U)

+#define VREFBUF_CSR_VRR_Msk         (0x1UL << VREFBUF_CSR_VRR_Pos)             /*!< 0x00000008 */

+#define VREFBUF_CSR_VRR             VREFBUF_CSR_VRR_Msk                        /*!<Voltage reference buffer ready  */

+#define VREFBUF_CSR_VRS_Pos         (4U)

+#define VREFBUF_CSR_VRS_Msk         (0x7UL << VREFBUF_CSR_VRS_Pos)             /*!< 0x00000070 */

+#define VREFBUF_CSR_VRS             VREFBUF_CSR_VRS_Msk                        /*!<Voltage reference scale         */

+

+#define VREFBUF_CSR_VRS_OUT1        ((uint32_t)0x00000000)                     /*!<Voltage reference VREF_OUT1     */

+#define VREFBUF_CSR_VRS_OUT2_Pos    (4U)

+#define VREFBUF_CSR_VRS_OUT2_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos)        /*!< 0x00000010 */

+#define VREFBUF_CSR_VRS_OUT2        VREFBUF_CSR_VRS_OUT2_Msk                   /*!<Voltage reference VREF_OUT2     */

+#define VREFBUF_CSR_VRS_OUT3_Pos    (5U)

+#define VREFBUF_CSR_VRS_OUT3_Msk    (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos)        /*!< 0x00000020 */

+#define VREFBUF_CSR_VRS_OUT3        VREFBUF_CSR_VRS_OUT3_Msk                   /*!<Voltage reference VREF_OUT3     */

+#define VREFBUF_CSR_VRS_OUT4_Pos    (4U)

+#define VREFBUF_CSR_VRS_OUT4_Msk    (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos)        /*!< 0x00000030 */

+#define VREFBUF_CSR_VRS_OUT4        VREFBUF_CSR_VRS_OUT4_Msk                   /*!<Voltage reference VREF_OUT4     */

+

+/*******************  Bit definition for VREFBUF_CCR register  ****************/

+#define VREFBUF_CCR_TRIM_Pos        (0U)

+#define VREFBUF_CCR_TRIM_Msk        (0x3FUL << VREFBUF_CCR_TRIM_Pos)           /*!< 0x0000003F */

+#define VREFBUF_CCR_TRIM            VREFBUF_CCR_TRIM_Msk                       /*!<TRIM[5:0] bits (Trimming code)  */

+

+/******************************************************************************/

+/*                                                                            */

+/*                 Flexible Datarate Controller Area Network                  */

+/*                                                                            */

+/******************************************************************************/

+/*!<FDCAN control and status registers */

+/*****************  Bit definition for FDCAN_CREL register  *******************/

+#define FDCAN_CREL_DAY_Pos        (0U)

+#define FDCAN_CREL_DAY_Msk        (0xFFUL << FDCAN_CREL_DAY_Pos)               /*!< 0x000000FF */

+#define FDCAN_CREL_DAY            FDCAN_CREL_DAY_Msk                           /*!<Timestamp Day                           */

+#define FDCAN_CREL_MON_Pos        (8U)

+#define FDCAN_CREL_MON_Msk        (0xFFUL << FDCAN_CREL_MON_Pos)               /*!< 0x0000FF00 */

+#define FDCAN_CREL_MON            FDCAN_CREL_MON_Msk                           /*!<Timestamp Month                         */

+#define FDCAN_CREL_YEAR_Pos       (16U)

+#define FDCAN_CREL_YEAR_Msk       (0xFUL << FDCAN_CREL_YEAR_Pos)               /*!< 0x000F0000 */

+#define FDCAN_CREL_YEAR           FDCAN_CREL_YEAR_Msk                          /*!<Timestamp Year                          */

+#define FDCAN_CREL_SUBSTEP_Pos    (20U)

+#define FDCAN_CREL_SUBSTEP_Msk    (0xFUL << FDCAN_CREL_SUBSTEP_Pos)            /*!< 0x00F00000 */

+#define FDCAN_CREL_SUBSTEP        FDCAN_CREL_SUBSTEP_Msk                       /*!<Sub-step of Core release                */

+#define FDCAN_CREL_STEP_Pos       (24U)

+#define FDCAN_CREL_STEP_Msk       (0xFUL << FDCAN_CREL_STEP_Pos)               /*!< 0x0F000000 */

+#define FDCAN_CREL_STEP           FDCAN_CREL_STEP_Msk                          /*!<Step of Core release                    */

+#define FDCAN_CREL_REL_Pos        (28U)

+#define FDCAN_CREL_REL_Msk        (0xFUL << FDCAN_CREL_REL_Pos)                /*!< 0xF0000000 */

+#define FDCAN_CREL_REL            FDCAN_CREL_REL_Msk                           /*!<Core release                            */

+

+/*****************  Bit definition for FDCAN_ENDN register  *******************/

+#define FDCAN_ENDN_ETV_Pos        (0U)

+#define FDCAN_ENDN_ETV_Msk        (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_ENDN_ETV            FDCAN_ENDN_ETV_Msk                           /*!<Endiannes Test Value                    */

+

+/*****************  Bit definition for FDCAN_DBTP register  *******************/

+#define FDCAN_DBTP_DSJW_Pos       (0U)

+#define FDCAN_DBTP_DSJW_Msk       (0xFUL << FDCAN_DBTP_DSJW_Pos)               /*!< 0x0000000F */

+#define FDCAN_DBTP_DSJW           FDCAN_DBTP_DSJW_Msk                          /*!<Synchronization Jump Width              */

+#define FDCAN_DBTP_DTSEG2_Pos     (4U)

+#define FDCAN_DBTP_DTSEG2_Msk     (0xFUL << FDCAN_DBTP_DTSEG2_Pos)             /*!< 0x000000F0 */

+#define FDCAN_DBTP_DTSEG2         FDCAN_DBTP_DTSEG2_Msk                        /*!<Data time segment after sample point    */

+#define FDCAN_DBTP_DTSEG1_Pos     (8U)

+#define FDCAN_DBTP_DTSEG1_Msk     (0x1FUL << FDCAN_DBTP_DTSEG1_Pos)            /*!< 0x00001F00 */

+#define FDCAN_DBTP_DTSEG1         FDCAN_DBTP_DTSEG1_Msk                        /*!<Data time segment before sample point   */

+#define FDCAN_DBTP_DBRP_Pos       (16U)

+#define FDCAN_DBTP_DBRP_Msk       (0x1FUL << FDCAN_DBTP_DBRP_Pos)              /*!< 0x001F0000 */

+#define FDCAN_DBTP_DBRP           FDCAN_DBTP_DBRP_Msk                          /*!<Data BIt Rate Prescaler                 */

+#define FDCAN_DBTP_TDC_Pos        (23U)

+#define FDCAN_DBTP_TDC_Msk        (0x1UL << FDCAN_DBTP_TDC_Pos)                /*!< 0x00800000 */

+#define FDCAN_DBTP_TDC            FDCAN_DBTP_TDC_Msk                           /*!<Transceiver Delay Compensation          */

+

+/*****************  Bit definition for FDCAN_TEST register  *******************/

+#define FDCAN_TEST_LBCK_Pos       (4U)

+#define FDCAN_TEST_LBCK_Msk       (0x1UL << FDCAN_TEST_LBCK_Pos)               /*!< 0x00000010 */

+#define FDCAN_TEST_LBCK           FDCAN_TEST_LBCK_Msk                          /*!<Loop Back mode                           */

+#define FDCAN_TEST_TX_Pos         (5U)

+#define FDCAN_TEST_TX_Msk         (0x3UL << FDCAN_TEST_TX_Pos)                 /*!< 0x00000060 */

+#define FDCAN_TEST_TX             FDCAN_TEST_TX_Msk                            /*!<Control of Transmit Pin                  */

+#define FDCAN_TEST_RX_Pos         (7U)

+#define FDCAN_TEST_RX_Msk         (0x1UL << FDCAN_TEST_RX_Pos)                 /*!< 0x00000080 */

+#define FDCAN_TEST_RX             FDCAN_TEST_RX_Msk                            /*!<Receive Pin                              */

+

+/*****************  Bit definition for FDCAN_RWD register  ********************/

+#define FDCAN_RWD_WDC_Pos         (0U)

+#define FDCAN_RWD_WDC_Msk         (0xFFUL << FDCAN_RWD_WDC_Pos)                /*!< 0x000000FF */

+#define FDCAN_RWD_WDC             FDCAN_RWD_WDC_Msk                            /*!<Watchdog configuration                   */

+#define FDCAN_RWD_WDV_Pos         (8U)

+#define FDCAN_RWD_WDV_Msk         (0xFFUL << FDCAN_RWD_WDV_Pos)                /*!< 0x0000FF00 */

+#define FDCAN_RWD_WDV             FDCAN_RWD_WDV_Msk                            /*!<Watchdog value                           */

+

+/*****************  Bit definition for FDCAN_CCCR register  ********************/

+#define FDCAN_CCCR_INIT_Pos       (0U)

+#define FDCAN_CCCR_INIT_Msk       (0x1UL << FDCAN_CCCR_INIT_Pos)               /*!< 0x00000001 */

+#define FDCAN_CCCR_INIT           FDCAN_CCCR_INIT_Msk                          /*!<Initialization                           */

+#define FDCAN_CCCR_CCE_Pos        (1U)

+#define FDCAN_CCCR_CCE_Msk        (0x1UL << FDCAN_CCCR_CCE_Pos)                /*!< 0x00000002 */

+#define FDCAN_CCCR_CCE            FDCAN_CCCR_CCE_Msk                           /*!<Configuration Change Enable              */

+#define FDCAN_CCCR_ASM_Pos        (2U)

+#define FDCAN_CCCR_ASM_Msk        (0x1UL << FDCAN_CCCR_ASM_Pos)                /*!< 0x00000004 */

+#define FDCAN_CCCR_ASM            FDCAN_CCCR_ASM_Msk                           /*!<ASM Restricted Operation Mode            */

+#define FDCAN_CCCR_CSA_Pos        (3U)

+#define FDCAN_CCCR_CSA_Msk        (0x1UL << FDCAN_CCCR_CSA_Pos)                /*!< 0x00000008 */

+#define FDCAN_CCCR_CSA            FDCAN_CCCR_CSA_Msk                           /*!<Clock Stop Acknowledge                   */

+#define FDCAN_CCCR_CSR_Pos        (4U)

+#define FDCAN_CCCR_CSR_Msk        (0x1UL << FDCAN_CCCR_CSR_Pos)                /*!< 0x00000010 */

+#define FDCAN_CCCR_CSR            FDCAN_CCCR_CSR_Msk                           /*!<Clock Stop Request                       */

+#define FDCAN_CCCR_MON_Pos        (5U)

+#define FDCAN_CCCR_MON_Msk        (0x1UL << FDCAN_CCCR_MON_Pos)                /*!< 0x00000020 */

+#define FDCAN_CCCR_MON            FDCAN_CCCR_MON_Msk                           /*!<Bus Monitoring Mode                      */

+#define FDCAN_CCCR_DAR_Pos        (6U)

+#define FDCAN_CCCR_DAR_Msk        (0x1UL << FDCAN_CCCR_DAR_Pos)                /*!< 0x00000040 */

+#define FDCAN_CCCR_DAR            FDCAN_CCCR_DAR_Msk                           /*!<Disable Automatic Retransmission         */

+#define FDCAN_CCCR_TEST_Pos       (7U)

+#define FDCAN_CCCR_TEST_Msk       (0x1UL << FDCAN_CCCR_TEST_Pos)               /*!< 0x00000080 */

+#define FDCAN_CCCR_TEST           FDCAN_CCCR_TEST_Msk                          /*!<Test Mode Enable                         */

+#define FDCAN_CCCR_FDOE_Pos       (8U)

+#define FDCAN_CCCR_FDOE_Msk       (0x1UL << FDCAN_CCCR_FDOE_Pos)               /*!< 0x00000100 */

+#define FDCAN_CCCR_FDOE           FDCAN_CCCR_FDOE_Msk                          /*!<FD Operation Enable                      */

+#define FDCAN_CCCR_BRSE_Pos       (9U)

+#define FDCAN_CCCR_BRSE_Msk       (0x1UL << FDCAN_CCCR_BRSE_Pos)               /*!< 0x00000200 */

+#define FDCAN_CCCR_BRSE           FDCAN_CCCR_BRSE_Msk                          /*!<FDCAN Bit Rate Switching                 */

+#define FDCAN_CCCR_PXHD_Pos       (12U)

+#define FDCAN_CCCR_PXHD_Msk       (0x1UL << FDCAN_CCCR_PXHD_Pos)               /*!< 0x00001000 */

+#define FDCAN_CCCR_PXHD           FDCAN_CCCR_PXHD_Msk                          /*!<Protocol Exception Handling Disable      */

+#define FDCAN_CCCR_EFBI_Pos       (13U)

+#define FDCAN_CCCR_EFBI_Msk       (0x1UL << FDCAN_CCCR_EFBI_Pos)               /*!< 0x00002000 */

+#define FDCAN_CCCR_EFBI           FDCAN_CCCR_EFBI_Msk                          /*!<Edge Filtering during Bus Integration    */

+#define FDCAN_CCCR_TXP_Pos        (14U)

+#define FDCAN_CCCR_TXP_Msk        (0x1UL << FDCAN_CCCR_TXP_Pos)                /*!< 0x00004000 */

+#define FDCAN_CCCR_TXP            FDCAN_CCCR_TXP_Msk                           /*!<Two CAN bit times Pause                  */

+#define FDCAN_CCCR_NISO_Pos       (15U)

+#define FDCAN_CCCR_NISO_Msk       (0x1UL << FDCAN_CCCR_NISO_Pos)               /*!< 0x00008000 */

+#define FDCAN_CCCR_NISO           FDCAN_CCCR_NISO_Msk                          /*!<Non ISO Operation                        */

+

+/*****************  Bit definition for FDCAN_NBTP register  ********************/

+#define FDCAN_NBTP_NTSEG2_Pos     (0U)

+#define FDCAN_NBTP_NTSEG2_Msk     (0x7FUL << FDCAN_NBTP_NTSEG2_Pos)            /*!< 0x0000007F */

+#define FDCAN_NBTP_NTSEG2         FDCAN_NBTP_NTSEG2_Msk                        /*!<Nominal Time segment after sample point  */

+#define FDCAN_NBTP_NTSEG1_Pos     (8U)

+#define FDCAN_NBTP_NTSEG1_Msk     (0xFFUL << FDCAN_NBTP_NTSEG1_Pos)            /*!< 0x0000FF00 */

+#define FDCAN_NBTP_NTSEG1         FDCAN_NBTP_NTSEG1_Msk                        /*!<Nominal Time segment before sample point */

+#define FDCAN_NBTP_NBRP_Pos       (16U)

+#define FDCAN_NBTP_NBRP_Msk       (0x1FFUL << FDCAN_NBTP_NBRP_Pos)             /*!< 0x01FF0000 */

+#define FDCAN_NBTP_NBRP           FDCAN_NBTP_NBRP_Msk                          /*!<Bit Rate Prescaler                       */

+#define FDCAN_NBTP_NSJW_Pos       (25U)

+#define FDCAN_NBTP_NSJW_Msk       (0x7FUL << FDCAN_NBTP_NSJW_Pos)              /*!< 0xFE000000 */

+#define FDCAN_NBTP_NSJW           FDCAN_NBTP_NSJW_Msk                          /*!<Nominal (Re)Synchronization Jump Width   */

+

+/*****************  Bit definition for FDCAN_TSCC register  ********************/

+#define FDCAN_TSCC_TSS_Pos        (0U)

+#define FDCAN_TSCC_TSS_Msk        (0x3UL << FDCAN_TSCC_TSS_Pos)                /*!< 0x00000003 */

+#define FDCAN_TSCC_TSS            FDCAN_TSCC_TSS_Msk                           /*!<Timestamp Select                         */

+#define FDCAN_TSCC_TCP_Pos        (16U)

+#define FDCAN_TSCC_TCP_Msk        (0xFUL << FDCAN_TSCC_TCP_Pos)                /*!< 0x000F0000 */

+#define FDCAN_TSCC_TCP            FDCAN_TSCC_TCP_Msk                           /*!<Timestamp Counter Prescaler              */

+

+/*****************  Bit definition for FDCAN_TSCV register  ********************/

+#define FDCAN_TSCV_TSC_Pos        (0U)

+#define FDCAN_TSCV_TSC_Msk        (0xFFFFUL << FDCAN_TSCV_TSC_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TSCV_TSC            FDCAN_TSCV_TSC_Msk                           /*!<Timestamp Counter                        */

+

+/*****************  Bit definition for FDCAN_TOCC register  ********************/

+#define FDCAN_TOCC_ETOC_Pos       (0U)

+#define FDCAN_TOCC_ETOC_Msk       (0x1UL << FDCAN_TOCC_ETOC_Pos)               /*!< 0x00000001 */

+#define FDCAN_TOCC_ETOC           FDCAN_TOCC_ETOC_Msk                          /*!<Enable Timeout Counter                   */

+#define FDCAN_TOCC_TOS_Pos        (1U)

+#define FDCAN_TOCC_TOS_Msk        (0x3UL << FDCAN_TOCC_TOS_Pos)                /*!< 0x00000006 */

+#define FDCAN_TOCC_TOS            FDCAN_TOCC_TOS_Msk                           /*!<Timeout Select                           */

+#define FDCAN_TOCC_TOP_Pos        (16U)

+#define FDCAN_TOCC_TOP_Msk        (0xFFFFUL << FDCAN_TOCC_TOP_Pos)             /*!< 0xFFFF0000 */

+#define FDCAN_TOCC_TOP            FDCAN_TOCC_TOP_Msk                           /*!<Timeout Period                           */

+

+/*****************  Bit definition for FDCAN_TOCV register  ********************/

+#define FDCAN_TOCV_TOC_Pos        (0U)

+#define FDCAN_TOCV_TOC_Msk        (0xFFFFUL << FDCAN_TOCV_TOC_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TOCV_TOC            FDCAN_TOCV_TOC_Msk                           /*!<Timeout Counter                          */

+

+/*****************  Bit definition for FDCAN_ECR register  *********************/

+#define FDCAN_ECR_TEC_Pos         (0U)

+#define FDCAN_ECR_TEC_Msk         (0xFUL << FDCAN_ECR_TEC_Pos)                 /*!< 0x0000000F */

+#define FDCAN_ECR_TEC             FDCAN_ECR_TEC_Msk                            /*!<Transmit Error Counter                   */

+#define FDCAN_ECR_REC_Pos         (8U)

+#define FDCAN_ECR_REC_Msk         (0x7FUL << FDCAN_ECR_REC_Pos)                /*!< 0x00007F00 */

+#define FDCAN_ECR_REC             FDCAN_ECR_REC_Msk                            /*!<Receive Error Counter                    */

+#define FDCAN_ECR_RP_Pos          (15U)

+#define FDCAN_ECR_RP_Msk          (0x1UL << FDCAN_ECR_RP_Pos)                  /*!< 0x00008000 */

+#define FDCAN_ECR_RP              FDCAN_ECR_RP_Msk                             /*!<Receive Error Passive                    */

+#define FDCAN_ECR_CEL_Pos         (16U)

+#define FDCAN_ECR_CEL_Msk         (0xFFUL << FDCAN_ECR_CEL_Pos)                /*!< 0x00FF0000 */

+#define FDCAN_ECR_CEL             FDCAN_ECR_CEL_Msk                            /*!<CAN Error Logging                        */

+

+/*****************  Bit definition for FDCAN_PSR register  *********************/

+#define FDCAN_PSR_LEC_Pos         (0U)

+#define FDCAN_PSR_LEC_Msk         (0x7UL << FDCAN_PSR_LEC_Pos)                 /*!< 0x00000007 */

+#define FDCAN_PSR_LEC             FDCAN_PSR_LEC_Msk                            /*!<Last Error Code                          */

+#define FDCAN_PSR_ACT_Pos         (3U)

+#define FDCAN_PSR_ACT_Msk         (0x3UL << FDCAN_PSR_ACT_Pos)                 /*!< 0x00000018 */

+#define FDCAN_PSR_ACT             FDCAN_PSR_ACT_Msk                            /*!<Activity                                 */

+#define FDCAN_PSR_EP_Pos          (5U)

+#define FDCAN_PSR_EP_Msk          (0x1UL << FDCAN_PSR_EP_Pos)                  /*!< 0x00000020 */

+#define FDCAN_PSR_EP              FDCAN_PSR_EP_Msk                             /*!<Error Passive                            */

+#define FDCAN_PSR_EW_Pos          (6U)

+#define FDCAN_PSR_EW_Msk          (0x1UL << FDCAN_PSR_EW_Pos)                  /*!< 0x00000040 */

+#define FDCAN_PSR_EW              FDCAN_PSR_EW_Msk                             /*!<Warning Status                           */

+#define FDCAN_PSR_BO_Pos          (7U)

+#define FDCAN_PSR_BO_Msk          (0x1UL << FDCAN_PSR_BO_Pos)                  /*!< 0x00000080 */

+#define FDCAN_PSR_BO              FDCAN_PSR_BO_Msk                             /*!<Bus_Off Status                           */

+#define FDCAN_PSR_DLEC_Pos        (8U)

+#define FDCAN_PSR_DLEC_Msk        (0x7UL << FDCAN_PSR_DLEC_Pos)                /*!< 0x00000700 */

+#define FDCAN_PSR_DLEC            FDCAN_PSR_DLEC_Msk                           /*!<Data Last Error Code                     */

+#define FDCAN_PSR_RESI_Pos        (11U)

+#define FDCAN_PSR_RESI_Msk        (0x1UL << FDCAN_PSR_RESI_Pos)                /*!< 0x00000800 */

+#define FDCAN_PSR_RESI            FDCAN_PSR_RESI_Msk                           /*!<ESI flag of last received FDCAN Message  */

+#define FDCAN_PSR_RBRS_Pos        (12U)

+#define FDCAN_PSR_RBRS_Msk        (0x1UL << FDCAN_PSR_RBRS_Pos)                /*!< 0x00001000 */

+#define FDCAN_PSR_RBRS            FDCAN_PSR_RBRS_Msk                           /*!<BRS flag of last received FDCAN Message  */

+#define FDCAN_PSR_REDL_Pos        (13U)

+#define FDCAN_PSR_REDL_Msk        (0x1UL << FDCAN_PSR_REDL_Pos)                /*!< 0x00002000 */

+#define FDCAN_PSR_REDL            FDCAN_PSR_REDL_Msk                           /*!<Received FDCAN Message                   */

+#define FDCAN_PSR_PXE_Pos         (14U)

+#define FDCAN_PSR_PXE_Msk         (0x1UL << FDCAN_PSR_PXE_Pos)                 /*!< 0x00004000 */

+#define FDCAN_PSR_PXE             FDCAN_PSR_PXE_Msk                            /*!<Protocol Exception Event                 */

+#define FDCAN_PSR_TDCV_Pos        (16U)

+#define FDCAN_PSR_TDCV_Msk        (0x7FUL << FDCAN_PSR_TDCV_Pos)               /*!< 0x007F0000 */

+#define FDCAN_PSR_TDCV            FDCAN_PSR_TDCV_Msk                           /*!<Transmitter Delay Compensation Value     */

+

+/*****************  Bit definition for FDCAN_TDCR register  ********************/

+#define FDCAN_TDCR_TDCF_Pos       (0U)

+#define FDCAN_TDCR_TDCF_Msk       (0x7FUL << FDCAN_TDCR_TDCF_Pos)              /*!< 0x0000007F */

+#define FDCAN_TDCR_TDCF           FDCAN_TDCR_TDCF_Msk                          /*!<Transmitter Delay Compensation Filter    */

+#define FDCAN_TDCR_TDCO_Pos       (8U)

+#define FDCAN_TDCR_TDCO_Msk       (0x7FUL << FDCAN_TDCR_TDCO_Pos)              /*!< 0x00007F00 */

+#define FDCAN_TDCR_TDCO           FDCAN_TDCR_TDCO_Msk                          /*!<Transmitter Delay Compensation Offset    */

+

+/*****************  Bit definition for FDCAN_IR register  **********************/

+#define FDCAN_IR_RF0N_Pos         (0U)

+#define FDCAN_IR_RF0N_Msk         (0x1UL << FDCAN_IR_RF0N_Pos)                 /*!< 0x00000001 */

+#define FDCAN_IR_RF0N             FDCAN_IR_RF0N_Msk                            /*!<Rx FIFO 0 New Message                    */

+#define FDCAN_IR_RF0W_Pos         (1U)

+#define FDCAN_IR_RF0W_Msk         (0x1UL << FDCAN_IR_RF0W_Pos)                 /*!< 0x00000002 */

+#define FDCAN_IR_RF0W             FDCAN_IR_RF0W_Msk                            /*!<Rx FIFO 0 Watermark Reached              */

+#define FDCAN_IR_RF0F_Pos         (2U)

+#define FDCAN_IR_RF0F_Msk         (0x1UL << FDCAN_IR_RF0F_Pos)                 /*!< 0x00000004 */

+#define FDCAN_IR_RF0F             FDCAN_IR_RF0F_Msk                            /*!<Rx FIFO 0 Full                           */

+#define FDCAN_IR_RF0L_Pos         (3U)

+#define FDCAN_IR_RF0L_Msk         (0x1UL << FDCAN_IR_RF0L_Pos)                 /*!< 0x00000008 */

+#define FDCAN_IR_RF0L             FDCAN_IR_RF0L_Msk                            /*!<Rx FIFO 0 Message Lost                   */

+#define FDCAN_IR_RF1N_Pos         (4U)

+#define FDCAN_IR_RF1N_Msk         (0x1UL << FDCAN_IR_RF1N_Pos)                 /*!< 0x00000010 */

+#define FDCAN_IR_RF1N             FDCAN_IR_RF1N_Msk                            /*!<Rx FIFO 1 New Message                    */

+#define FDCAN_IR_RF1W_Pos         (5U)

+#define FDCAN_IR_RF1W_Msk         (0x1UL << FDCAN_IR_RF1W_Pos)                 /*!< 0x00000020 */

+#define FDCAN_IR_RF1W             FDCAN_IR_RF1W_Msk                            /*!<Rx FIFO 1 Watermark Reached              */

+#define FDCAN_IR_RF1F_Pos         (6U)

+#define FDCAN_IR_RF1F_Msk         (0x1UL << FDCAN_IR_RF1F_Pos)                 /*!< 0x00000040 */

+#define FDCAN_IR_RF1F             FDCAN_IR_RF1F_Msk                            /*!<Rx FIFO 1 Full                           */

+#define FDCAN_IR_RF1L_Pos         (7U)

+#define FDCAN_IR_RF1L_Msk         (0x1UL << FDCAN_IR_RF1L_Pos)                 /*!< 0x00000080 */

+#define FDCAN_IR_RF1L             FDCAN_IR_RF1L_Msk                            /*!<Rx FIFO 1 Message Lost                   */

+#define FDCAN_IR_HPM_Pos          (8U)

+#define FDCAN_IR_HPM_Msk          (0x1UL << FDCAN_IR_HPM_Pos)                  /*!< 0x00000100 */

+#define FDCAN_IR_HPM              FDCAN_IR_HPM_Msk                             /*!<High Priority Message                    */

+#define FDCAN_IR_TC_Pos           (9U)

+#define FDCAN_IR_TC_Msk           (0x1UL << FDCAN_IR_TC_Pos)                   /*!< 0x00000200 */

+#define FDCAN_IR_TC               FDCAN_IR_TC_Msk                              /*!<Transmission Completed                   */

+#define FDCAN_IR_TCF_Pos          (10U)

+#define FDCAN_IR_TCF_Msk          (0x1UL << FDCAN_IR_TCF_Pos)                  /*!< 0x00000400 */

+#define FDCAN_IR_TCF              FDCAN_IR_TCF_Msk                             /*!<Transmission Cancellation Finished       */

+#define FDCAN_IR_TFE_Pos          (11U)

+#define FDCAN_IR_TFE_Msk          (0x1UL << FDCAN_IR_TFE_Pos)                  /*!< 0x00000800 */

+#define FDCAN_IR_TFE              FDCAN_IR_TFE_Msk                             /*!<Tx FIFO Empty                            */

+#define FDCAN_IR_TEFN_Pos         (12U)

+#define FDCAN_IR_TEFN_Msk         (0x1UL << FDCAN_IR_TEFN_Pos)                 /*!< 0x00001000 */

+#define FDCAN_IR_TEFN             FDCAN_IR_TEFN_Msk                            /*!<Tx Event FIFO New Entry                  */

+#define FDCAN_IR_TEFW_Pos         (13U)

+#define FDCAN_IR_TEFW_Msk         (0x1UL << FDCAN_IR_TEFW_Pos)                 /*!< 0x00002000 */

+#define FDCAN_IR_TEFW             FDCAN_IR_TEFW_Msk                            /*!<Tx Event FIFO Watermark Reached          */

+#define FDCAN_IR_TEFF_Pos         (14U)

+#define FDCAN_IR_TEFF_Msk         (0x1UL << FDCAN_IR_TEFF_Pos)                 /*!< 0x00004000 */

+#define FDCAN_IR_TEFF             FDCAN_IR_TEFF_Msk                            /*!<Tx Event FIFO Full                       */

+#define FDCAN_IR_TEFL_Pos         (15U)

+#define FDCAN_IR_TEFL_Msk         (0x1UL << FDCAN_IR_TEFL_Pos)                 /*!< 0x00008000 */

+#define FDCAN_IR_TEFL             FDCAN_IR_TEFL_Msk                            /*!<Tx Event FIFO Element Lost               */

+#define FDCAN_IR_TSW_Pos          (16U)

+#define FDCAN_IR_TSW_Msk          (0x1UL << FDCAN_IR_TSW_Pos)                  /*!< 0x00010000 */

+#define FDCAN_IR_TSW              FDCAN_IR_TSW_Msk                             /*!<Timestamp Wraparound                     */

+#define FDCAN_IR_MRAF_Pos         (17U)

+#define FDCAN_IR_MRAF_Msk         (0x1UL << FDCAN_IR_MRAF_Pos)                 /*!< 0x00020000 */

+#define FDCAN_IR_MRAF             FDCAN_IR_MRAF_Msk                            /*!<Message RAM Access Failure               */

+#define FDCAN_IR_TOO_Pos          (18U)

+#define FDCAN_IR_TOO_Msk          (0x1UL << FDCAN_IR_TOO_Pos)                  /*!< 0x00040000 */

+#define FDCAN_IR_TOO              FDCAN_IR_TOO_Msk                             /*!<Timeout Occurred                         */

+#define FDCAN_IR_DRX_Pos          (19U)

+#define FDCAN_IR_DRX_Msk          (0x1UL << FDCAN_IR_DRX_Pos)                  /*!< 0x00080000 */

+#define FDCAN_IR_DRX              FDCAN_IR_DRX_Msk                             /*!<Message stored to Dedicated Rx Buffer    */

+#define FDCAN_IR_ELO_Pos          (22U)

+#define FDCAN_IR_ELO_Msk          (0x1UL << FDCAN_IR_ELO_Pos)                  /*!< 0x00400000 */

+#define FDCAN_IR_ELO              FDCAN_IR_ELO_Msk                             /*!<Error Logging Overflow                   */

+#define FDCAN_IR_EP_Pos           (23U)

+#define FDCAN_IR_EP_Msk           (0x1UL << FDCAN_IR_EP_Pos)                   /*!< 0x00800000 */

+#define FDCAN_IR_EP               FDCAN_IR_EP_Msk                              /*!<Error Passive                            */

+#define FDCAN_IR_EW_Pos           (24U)

+#define FDCAN_IR_EW_Msk           (0x1UL << FDCAN_IR_EW_Pos)                   /*!< 0x01000000 */

+#define FDCAN_IR_EW               FDCAN_IR_EW_Msk                              /*!<Warning Status                           */

+#define FDCAN_IR_BO_Pos           (25U)

+#define FDCAN_IR_BO_Msk           (0x1UL << FDCAN_IR_BO_Pos)                   /*!< 0x02000000 */

+#define FDCAN_IR_BO               FDCAN_IR_BO_Msk                              /*!<Bus_Off Status                           */

+#define FDCAN_IR_WDI_Pos          (26U)

+#define FDCAN_IR_WDI_Msk          (0x1UL << FDCAN_IR_WDI_Pos)                  /*!< 0x04000000 */

+#define FDCAN_IR_WDI              FDCAN_IR_WDI_Msk                             /*!<Watchdog Interrupt                       */

+#define FDCAN_IR_PEA_Pos          (27U)

+#define FDCAN_IR_PEA_Msk          (0x1UL << FDCAN_IR_PEA_Pos)                  /*!< 0x08000000 */

+#define FDCAN_IR_PEA              FDCAN_IR_PEA_Msk                             /*!<Protocol Error in Arbitration Phase      */

+#define FDCAN_IR_PED_Pos          (28U)

+#define FDCAN_IR_PED_Msk          (0x1UL << FDCAN_IR_PED_Pos)                  /*!< 0x10000000 */

+#define FDCAN_IR_PED              FDCAN_IR_PED_Msk                             /*!<Protocol Error in Data Phase             */

+#define FDCAN_IR_ARA_Pos          (29U)

+#define FDCAN_IR_ARA_Msk          (0x1UL << FDCAN_IR_ARA_Pos)                  /*!< 0x20000000 */

+#define FDCAN_IR_ARA              FDCAN_IR_ARA_Msk                             /*!<Access to Reserved Address               */

+

+/*****************  Bit definition for FDCAN_IE register  **********************/

+#define FDCAN_IE_RF0NE_Pos        (0U)

+#define FDCAN_IE_RF0NE_Msk        (0x1UL << FDCAN_IE_RF0NE_Pos)                /*!< 0x00000001 */

+#define FDCAN_IE_RF0NE            FDCAN_IE_RF0NE_Msk                           /*!<Rx FIFO 0 New Message Enable                 */

+#define FDCAN_IE_RF0WE_Pos        (1U)

+#define FDCAN_IE_RF0WE_Msk        (0x1UL << FDCAN_IE_RF0WE_Pos)                /*!< 0x00000002 */

+#define FDCAN_IE_RF0WE            FDCAN_IE_RF0WE_Msk                           /*!<Rx FIFO 0 Watermark Reached Enable           */

+#define FDCAN_IE_RF0FE_Pos        (2U)

+#define FDCAN_IE_RF0FE_Msk        (0x1UL << FDCAN_IE_RF0FE_Pos)                /*!< 0x00000004 */

+#define FDCAN_IE_RF0FE            FDCAN_IE_RF0FE_Msk                           /*!<Rx FIFO 0 Full Enable                        */

+#define FDCAN_IE_RF0LE_Pos        (3U)

+#define FDCAN_IE_RF0LE_Msk        (0x1UL << FDCAN_IE_RF0LE_Pos)                /*!< 0x00000008 */

+#define FDCAN_IE_RF0LE            FDCAN_IE_RF0LE_Msk                           /*!<Rx FIFO 0 Message Lost Enable                */

+#define FDCAN_IE_RF1NE_Pos        (4U)

+#define FDCAN_IE_RF1NE_Msk        (0x1UL << FDCAN_IE_RF1NE_Pos)                /*!< 0x00000010 */

+#define FDCAN_IE_RF1NE            FDCAN_IE_RF1NE_Msk                           /*!<Rx FIFO 1 New Message Enable                 */

+#define FDCAN_IE_RF1WE_Pos        (5U)

+#define FDCAN_IE_RF1WE_Msk        (0x1UL << FDCAN_IE_RF1WE_Pos)                /*!< 0x00000020 */

+#define FDCAN_IE_RF1WE            FDCAN_IE_RF1WE_Msk                           /*!<Rx FIFO 1 Watermark Reached Enable           */

+#define FDCAN_IE_RF1FE_Pos        (6U)

+#define FDCAN_IE_RF1FE_Msk        (0x1UL << FDCAN_IE_RF1FE_Pos)                /*!< 0x00000040 */

+#define FDCAN_IE_RF1FE            FDCAN_IE_RF1FE_Msk                           /*!<Rx FIFO 1 Full Enable                        */

+#define FDCAN_IE_RF1LE_Pos        (7U)

+#define FDCAN_IE_RF1LE_Msk        (0x1UL << FDCAN_IE_RF1LE_Pos)                /*!< 0x00000080 */

+#define FDCAN_IE_RF1LE            FDCAN_IE_RF1LE_Msk                           /*!<Rx FIFO 1 Message Lost Enable                */

+#define FDCAN_IE_HPME_Pos         (8U)

+#define FDCAN_IE_HPME_Msk         (0x1UL << FDCAN_IE_HPME_Pos)                 /*!< 0x00000100 */

+#define FDCAN_IE_HPME             FDCAN_IE_HPME_Msk                            /*!<High Priority Message Enable                 */

+#define FDCAN_IE_TCE_Pos          (9U)

+#define FDCAN_IE_TCE_Msk          (0x1UL << FDCAN_IE_TCE_Pos)                  /*!< 0x00000200 */

+#define FDCAN_IE_TCE              FDCAN_IE_TCE_Msk                             /*!<Transmission Completed Enable                */

+#define FDCAN_IE_TCFE_Pos         (10U)

+#define FDCAN_IE_TCFE_Msk         (0x1UL << FDCAN_IE_TCFE_Pos)                 /*!< 0x00000400 */

+#define FDCAN_IE_TCFE             FDCAN_IE_TCFE_Msk                            /*!<Transmission Cancellation Finished Enable    */

+#define FDCAN_IE_TFEE_Pos         (11U)

+#define FDCAN_IE_TFEE_Msk         (0x1UL << FDCAN_IE_TFEE_Pos)                 /*!< 0x00000800 */

+#define FDCAN_IE_TFEE             FDCAN_IE_TFEE_Msk                            /*!<Tx FIFO Empty Enable                         */

+#define FDCAN_IE_TEFNE_Pos        (12U)

+#define FDCAN_IE_TEFNE_Msk        (0x1UL << FDCAN_IE_TEFNE_Pos)                /*!< 0x00001000 */

+#define FDCAN_IE_TEFNE            FDCAN_IE_TEFNE_Msk                           /*!<Tx Event FIFO New Entry Enable               */

+#define FDCAN_IE_TEFWE_Pos        (13U)

+#define FDCAN_IE_TEFWE_Msk        (0x1UL << FDCAN_IE_TEFWE_Pos)                /*!< 0x00002000 */

+#define FDCAN_IE_TEFWE            FDCAN_IE_TEFWE_Msk                           /*!<Tx Event FIFO Watermark Reached Enable       */

+#define FDCAN_IE_TEFFE_Pos        (14U)

+#define FDCAN_IE_TEFFE_Msk        (0x1UL << FDCAN_IE_TEFFE_Pos)                /*!< 0x00004000 */

+#define FDCAN_IE_TEFFE            FDCAN_IE_TEFFE_Msk                           /*!<Tx Event FIFO Full Enable                    */

+#define FDCAN_IE_TEFLE_Pos        (15U)

+#define FDCAN_IE_TEFLE_Msk        (0x1UL << FDCAN_IE_TEFLE_Pos)                /*!< 0x00008000 */

+#define FDCAN_IE_TEFLE            FDCAN_IE_TEFLE_Msk                           /*!<Tx Event FIFO Element Lost Enable            */

+#define FDCAN_IE_TSWE_Pos         (16U)

+#define FDCAN_IE_TSWE_Msk         (0x1UL << FDCAN_IE_TSWE_Pos)                 /*!< 0x00010000 */

+#define FDCAN_IE_TSWE             FDCAN_IE_TSWE_Msk                            /*!<Timestamp Wraparound Enable                  */

+#define FDCAN_IE_MRAFE_Pos        (17U)

+#define FDCAN_IE_MRAFE_Msk        (0x1UL << FDCAN_IE_MRAFE_Pos)                /*!< 0x00020000 */

+#define FDCAN_IE_MRAFE            FDCAN_IE_MRAFE_Msk                           /*!<Message RAM Access Failure Enable            */

+#define FDCAN_IE_TOOE_Pos         (18U)

+#define FDCAN_IE_TOOE_Msk         (0x1UL << FDCAN_IE_TOOE_Pos)                 /*!< 0x00040000 */

+#define FDCAN_IE_TOOE             FDCAN_IE_TOOE_Msk                            /*!<Timeout Occurred Enable                      */

+#define FDCAN_IE_DRXE_Pos         (19U)

+#define FDCAN_IE_DRXE_Msk         (0x1UL << FDCAN_IE_DRXE_Pos)                 /*!< 0x00080000 */

+#define FDCAN_IE_DRXE             FDCAN_IE_DRXE_Msk                            /*!<Message stored to Dedicated Rx Buffer Enable */

+#define FDCAN_IE_BECE_Pos         (20U)

+#define FDCAN_IE_BECE_Msk         (0x1UL << FDCAN_IE_BECE_Pos)                 /*!< 0x00100000 */

+#define FDCAN_IE_BECE             FDCAN_IE_BECE_Msk                            /*!<Bit Error Corrected Interrupt Enable         */

+#define FDCAN_IE_BEUE_Pos         (21U)

+#define FDCAN_IE_BEUE_Msk         (0x1UL << FDCAN_IE_BEUE_Pos)                 /*!< 0x00200000 */

+#define FDCAN_IE_BEUE             FDCAN_IE_BEUE_Msk                            /*!<Bit Error Uncorrected Interrupt Enable       */

+#define FDCAN_IE_ELOE_Pos         (22U)

+#define FDCAN_IE_ELOE_Msk         (0x1UL << FDCAN_IE_ELOE_Pos)                 /*!< 0x00400000 */

+#define FDCAN_IE_ELOE             FDCAN_IE_ELOE_Msk                            /*!<Error Logging Overflow Enable                */

+#define FDCAN_IE_EPE_Pos          (23U)

+#define FDCAN_IE_EPE_Msk          (0x1UL << FDCAN_IE_EPE_Pos)                  /*!< 0x00800000 */

+#define FDCAN_IE_EPE              FDCAN_IE_EPE_Msk                             /*!<Error Passive Enable                         */

+#define FDCAN_IE_EWE_Pos          (24U)

+#define FDCAN_IE_EWE_Msk          (0x1UL << FDCAN_IE_EWE_Pos)                  /*!< 0x01000000 */

+#define FDCAN_IE_EWE              FDCAN_IE_EWE_Msk                             /*!<Warning Status Enable                        */

+#define FDCAN_IE_BOE_Pos          (25U)

+#define FDCAN_IE_BOE_Msk          (0x1UL << FDCAN_IE_BOE_Pos)                  /*!< 0x02000000 */

+#define FDCAN_IE_BOE              FDCAN_IE_BOE_Msk                             /*!<Bus_Off Status Enable                        */

+#define FDCAN_IE_WDIE_Pos         (26U)

+#define FDCAN_IE_WDIE_Msk         (0x1UL << FDCAN_IE_WDIE_Pos)                 /*!< 0x04000000 */

+#define FDCAN_IE_WDIE             FDCAN_IE_WDIE_Msk                            /*!<Watchdog Interrupt Enable                    */

+#define FDCAN_IE_PEAE_Pos         (27U)

+#define FDCAN_IE_PEAE_Msk         (0x1UL << FDCAN_IE_PEAE_Pos)                 /*!< 0x08000000 */

+#define FDCAN_IE_PEAE             FDCAN_IE_PEAE_Msk                            /*!<Protocol Error in Arbitration Phase Enable   */

+#define FDCAN_IE_PEDE_Pos         (28U)

+#define FDCAN_IE_PEDE_Msk         (0x1UL << FDCAN_IE_PEDE_Pos)                 /*!< 0x10000000 */

+#define FDCAN_IE_PEDE             FDCAN_IE_PEDE_Msk                            /*!<Protocol Error in Data Phase Enable          */

+#define FDCAN_IE_ARAE_Pos         (29U)

+#define FDCAN_IE_ARAE_Msk         (0x1UL << FDCAN_IE_ARAE_Pos)                 /*!< 0x20000000 */

+#define FDCAN_IE_ARAE             FDCAN_IE_ARAE_Msk                            /*!<Access to Reserved Address Enable            */

+

+/*****************  Bit definition for FDCAN_ILS register  **********************/

+#define FDCAN_ILS_RF0NL_Pos       (0U)

+#define FDCAN_ILS_RF0NL_Msk       (0x1UL << FDCAN_ILS_RF0NL_Pos)               /*!< 0x00000001 */

+#define FDCAN_ILS_RF0NL           FDCAN_ILS_RF0NL_Msk                          /*!<Rx FIFO 0 New Message Line                  */

+#define FDCAN_ILS_RF0WL_Pos       (1U)

+#define FDCAN_ILS_RF0WL_Msk       (0x1UL << FDCAN_ILS_RF0WL_Pos)               /*!< 0x00000002 */

+#define FDCAN_ILS_RF0WL           FDCAN_ILS_RF0WL_Msk                          /*!<Rx FIFO 0 Watermark Reached Line            */

+#define FDCAN_ILS_RF0FL_Pos       (2U)

+#define FDCAN_ILS_RF0FL_Msk       (0x1UL << FDCAN_ILS_RF0FL_Pos)               /*!< 0x00000004 */

+#define FDCAN_ILS_RF0FL           FDCAN_ILS_RF0FL_Msk                          /*!<Rx FIFO 0 Full Line                         */

+#define FDCAN_ILS_RF0LL_Pos       (3U)

+#define FDCAN_ILS_RF0LL_Msk       (0x1UL << FDCAN_ILS_RF0LL_Pos)               /*!< 0x00000008 */

+#define FDCAN_ILS_RF0LL           FDCAN_ILS_RF0LL_Msk                          /*!<Rx FIFO 0 Message Lost Line                 */

+#define FDCAN_ILS_RF1NL_Pos       (4U)

+#define FDCAN_ILS_RF1NL_Msk       (0x1UL << FDCAN_ILS_RF1NL_Pos)               /*!< 0x00000010 */

+#define FDCAN_ILS_RF1NL           FDCAN_ILS_RF1NL_Msk                          /*!<Rx FIFO 1 New Message Line                  */

+#define FDCAN_ILS_RF1WL_Pos       (5U)

+#define FDCAN_ILS_RF1WL_Msk       (0x1UL << FDCAN_ILS_RF1WL_Pos)               /*!< 0x00000020 */

+#define FDCAN_ILS_RF1WL           FDCAN_ILS_RF1WL_Msk                          /*!<Rx FIFO 1 Watermark Reached Line            */

+#define FDCAN_ILS_RF1FL_Pos       (6U)

+#define FDCAN_ILS_RF1FL_Msk       (0x1UL << FDCAN_ILS_RF1FL_Pos)               /*!< 0x00000040 */

+#define FDCAN_ILS_RF1FL           FDCAN_ILS_RF1FL_Msk                          /*!<Rx FIFO 1 Full Line                         */

+#define FDCAN_ILS_RF1LL_Pos       (7U)

+#define FDCAN_ILS_RF1LL_Msk       (0x1UL << FDCAN_ILS_RF1LL_Pos)               /*!< 0x00000080 */

+#define FDCAN_ILS_RF1LL           FDCAN_ILS_RF1LL_Msk                          /*!<Rx FIFO 1 Message Lost Line                 */

+#define FDCAN_ILS_HPML_Pos        (8U)

+#define FDCAN_ILS_HPML_Msk        (0x1UL << FDCAN_ILS_HPML_Pos)                /*!< 0x00000100 */

+#define FDCAN_ILS_HPML            FDCAN_ILS_HPML_Msk                           /*!<High Priority Message Line                  */

+#define FDCAN_ILS_TCL_Pos         (9U)

+#define FDCAN_ILS_TCL_Msk         (0x1UL << FDCAN_ILS_TCL_Pos)                 /*!< 0x00000200 */

+#define FDCAN_ILS_TCL             FDCAN_ILS_TCL_Msk                            /*!<Transmission Completed Line                 */

+#define FDCAN_ILS_TCFL_Pos        (10U)

+#define FDCAN_ILS_TCFL_Msk        (0x1UL << FDCAN_ILS_TCFL_Pos)                /*!< 0x00000400 */

+#define FDCAN_ILS_TCFL            FDCAN_ILS_TCFL_Msk                           /*!<Transmission Cancellation Finished Line     */

+#define FDCAN_ILS_TFEL_Pos        (11U)

+#define FDCAN_ILS_TFEL_Msk        (0x1UL << FDCAN_ILS_TFEL_Pos)                /*!< 0x00000800 */

+#define FDCAN_ILS_TFEL            FDCAN_ILS_TFEL_Msk                           /*!<Tx FIFO Empty Line                          */

+#define FDCAN_ILS_TEFNL_Pos       (12U)

+#define FDCAN_ILS_TEFNL_Msk       (0x1UL << FDCAN_ILS_TEFNL_Pos)               /*!< 0x00001000 */

+#define FDCAN_ILS_TEFNL           FDCAN_ILS_TEFNL_Msk                          /*!<Tx Event FIFO New Entry Line                */

+#define FDCAN_ILS_TEFWL_Pos       (13U)

+#define FDCAN_ILS_TEFWL_Msk       (0x1UL << FDCAN_ILS_TEFWL_Pos)               /*!< 0x00002000 */

+#define FDCAN_ILS_TEFWL           FDCAN_ILS_TEFWL_Msk                          /*!<Tx Event FIFO Watermark Reached Line        */

+#define FDCAN_ILS_TEFFL_Pos       (14U)

+#define FDCAN_ILS_TEFFL_Msk       (0x1UL << FDCAN_ILS_TEFFL_Pos)               /*!< 0x00004000 */

+#define FDCAN_ILS_TEFFL           FDCAN_ILS_TEFFL_Msk                          /*!<Tx Event FIFO Full Line                     */

+#define FDCAN_ILS_TEFLL_Pos       (15U)

+#define FDCAN_ILS_TEFLL_Msk       (0x1UL << FDCAN_ILS_TEFLL_Pos)               /*!< 0x00008000 */

+#define FDCAN_ILS_TEFLL           FDCAN_ILS_TEFLL_Msk                          /*!<Tx Event FIFO Element Lost Line             */

+#define FDCAN_ILS_TSWL_Pos        (16U)

+#define FDCAN_ILS_TSWL_Msk        (0x1UL << FDCAN_ILS_TSWL_Pos)                /*!< 0x00010000 */

+#define FDCAN_ILS_TSWL            FDCAN_ILS_TSWL_Msk                           /*!<Timestamp Wraparound Line                   */

+#define FDCAN_ILS_MRAFE_Pos       (17U)

+#define FDCAN_ILS_MRAFE_Msk       (0x1UL << FDCAN_ILS_MRAFE_Pos)               /*!< 0x00020000 */

+#define FDCAN_ILS_MRAFE           FDCAN_ILS_MRAFE_Msk                          /*!<Message RAM Access Failure Line             */

+#define FDCAN_ILS_TOOE_Pos        (18U)

+#define FDCAN_ILS_TOOE_Msk        (0x1UL << FDCAN_ILS_TOOE_Pos)                /*!< 0x00040000 */

+#define FDCAN_ILS_TOOE            FDCAN_ILS_TOOE_Msk                           /*!<Timeout Occurred Line                       */

+#define FDCAN_ILS_DRXE_Pos        (19U)

+#define FDCAN_ILS_DRXE_Msk        (0x1UL << FDCAN_ILS_DRXE_Pos)                /*!< 0x00080000 */

+#define FDCAN_ILS_DRXE            FDCAN_ILS_DRXE_Msk                           /*!<Message stored to Dedicated Rx Buffer Line  */

+#define FDCAN_ILS_BECE_Pos        (20U)

+#define FDCAN_ILS_BECE_Msk        (0x1UL << FDCAN_ILS_BECE_Pos)                /*!< 0x00100000 */

+#define FDCAN_ILS_BECE            FDCAN_ILS_BECE_Msk                           /*!<Bit Error Corrected Interrupt Line          */

+#define FDCAN_ILS_BEUE_Pos        (21U)

+#define FDCAN_ILS_BEUE_Msk        (0x1UL << FDCAN_ILS_BEUE_Pos)                /*!< 0x00200000 */

+#define FDCAN_ILS_BEUE            FDCAN_ILS_BEUE_Msk                           /*!<Bit Error Uncorrected Interrupt Line        */

+#define FDCAN_ILS_ELOE_Pos        (22U)

+#define FDCAN_ILS_ELOE_Msk        (0x1UL << FDCAN_ILS_ELOE_Pos)                /*!< 0x00400000 */

+#define FDCAN_ILS_ELOE            FDCAN_ILS_ELOE_Msk                           /*!<Error Logging Overflow Line                 */

+#define FDCAN_ILS_EPE_Pos         (23U)

+#define FDCAN_ILS_EPE_Msk         (0x1UL << FDCAN_ILS_EPE_Pos)                 /*!< 0x00800000 */

+#define FDCAN_ILS_EPE             FDCAN_ILS_EPE_Msk                            /*!<Error Passive Line                          */

+#define FDCAN_ILS_EWE_Pos         (24U)

+#define FDCAN_ILS_EWE_Msk         (0x1UL << FDCAN_ILS_EWE_Pos)                 /*!< 0x01000000 */

+#define FDCAN_ILS_EWE             FDCAN_ILS_EWE_Msk                            /*!<Warning Status Line                         */

+#define FDCAN_ILS_BOE_Pos         (25U)

+#define FDCAN_ILS_BOE_Msk         (0x1UL << FDCAN_ILS_BOE_Pos)                 /*!< 0x02000000 */

+#define FDCAN_ILS_BOE             FDCAN_ILS_BOE_Msk                            /*!<Bus_Off Status Line                         */

+#define FDCAN_ILS_WDIE_Pos        (26U)

+#define FDCAN_ILS_WDIE_Msk        (0x1UL << FDCAN_ILS_WDIE_Pos)                /*!< 0x04000000 */

+#define FDCAN_ILS_WDIE            FDCAN_ILS_WDIE_Msk                           /*!<Watchdog Interrupt Line                     */

+#define FDCAN_ILS_PEAE_Pos        (27U)

+#define FDCAN_ILS_PEAE_Msk        (0x1UL << FDCAN_ILS_PEAE_Pos)                /*!< 0x08000000 */

+#define FDCAN_ILS_PEAE            FDCAN_ILS_PEAE_Msk                           /*!<Protocol Error in Arbitration Phase Line    */

+#define FDCAN_ILS_PEDE_Pos        (28U)

+#define FDCAN_ILS_PEDE_Msk        (0x1UL << FDCAN_ILS_PEDE_Pos)                /*!< 0x10000000 */

+#define FDCAN_ILS_PEDE            FDCAN_ILS_PEDE_Msk                           /*!<Protocol Error in Data Phase Line           */

+#define FDCAN_ILS_ARAE_Pos        (29U)

+#define FDCAN_ILS_ARAE_Msk        (0x1UL << FDCAN_ILS_ARAE_Pos)                /*!< 0x20000000 */

+#define FDCAN_ILS_ARAE            FDCAN_ILS_ARAE_Msk                           /*!<Access to Reserved Address Line             */

+

+/*****************  Bit definition for FDCAN_ILE register  **********************/

+#define FDCAN_ILE_EINT0_Pos       (0U)

+#define FDCAN_ILE_EINT0_Msk       (0x1UL << FDCAN_ILE_EINT0_Pos)               /*!< 0x00000001 */

+#define FDCAN_ILE_EINT0           FDCAN_ILE_EINT0_Msk                          /*!<Enable Interrupt Line 0                   */

+#define FDCAN_ILE_EINT1_Pos       (1U)

+#define FDCAN_ILE_EINT1_Msk       (0x1UL << FDCAN_ILE_EINT1_Pos)               /*!< 0x00000002 */

+#define FDCAN_ILE_EINT1           FDCAN_ILE_EINT1_Msk                          /*!<Enable Interrupt Line 1                   */

+

+/*****************  Bit definition for FDCAN_GFC register  **********************/

+#define FDCAN_GFC_RRFE_Pos        (0U)

+#define FDCAN_GFC_RRFE_Msk        (0x1UL << FDCAN_GFC_RRFE_Pos)                /*!< 0x00000001 */

+#define FDCAN_GFC_RRFE            FDCAN_GFC_RRFE_Msk                           /*!<Reject Remote Frames Extended             */

+#define FDCAN_GFC_RRFS_Pos        (1U)

+#define FDCAN_GFC_RRFS_Msk        (0x1UL << FDCAN_GFC_RRFS_Pos)                /*!< 0x00000002 */

+#define FDCAN_GFC_RRFS            FDCAN_GFC_RRFS_Msk                           /*!<Reject Remote Frames Standard             */

+#define FDCAN_GFC_ANFE_Pos        (2U)

+#define FDCAN_GFC_ANFE_Msk        (0x3UL << FDCAN_GFC_ANFE_Pos)                /*!< 0x0000000C */

+#define FDCAN_GFC_ANFE            FDCAN_GFC_ANFE_Msk                           /*!<Accept Non-matching Frames Extended       */

+#define FDCAN_GFC_ANFS_Pos        (4U)

+#define FDCAN_GFC_ANFS_Msk        (0x3UL << FDCAN_GFC_ANFS_Pos)                /*!< 0x00000030 */

+#define FDCAN_GFC_ANFS            FDCAN_GFC_ANFS_Msk                           /*!<Accept Non-matching Frames Standard       */

+

+/*****************  Bit definition for FDCAN_SIDFC register  ********************/

+#define FDCAN_SIDFC_FLSSA_Pos     (2U)

+#define FDCAN_SIDFC_FLSSA_Msk     (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos)          /*!< 0x0000FFFC */

+#define FDCAN_SIDFC_FLSSA         FDCAN_SIDFC_FLSSA_Msk                        /*!<Filter List Standard Start Address        */

+#define FDCAN_SIDFC_LSS_Pos       (16U)

+#define FDCAN_SIDFC_LSS_Msk       (0xFFUL << FDCAN_SIDFC_LSS_Pos)              /*!< 0x00FF0000 */

+#define FDCAN_SIDFC_LSS           FDCAN_SIDFC_LSS_Msk                          /*!<List Size Standard                        */

+

+/*****************  Bit definition for FDCAN_XIDFC register  ********************/

+#define FDCAN_XIDFC_FLESA_Pos     (2U)

+#define FDCAN_XIDFC_FLESA_Msk     (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos)          /*!< 0x0000FFFC */

+#define FDCAN_XIDFC_FLESA         FDCAN_XIDFC_FLESA_Msk                        /*!<Filter List Standard Start Address        */

+#define FDCAN_XIDFC_LSE_Pos       (16U)

+#define FDCAN_XIDFC_LSE_Msk       (0x7FUL << FDCAN_XIDFC_LSE_Pos)              /*!< 0x007F0000 */

+#define FDCAN_XIDFC_LSE           FDCAN_XIDFC_LSE_Msk                          /*!<List Size Extended                        */

+

+/*****************  Bit definition for FDCAN_XIDAM register  ********************/

+#define FDCAN_XIDAM_EIDM_Pos      (0U)

+#define FDCAN_XIDAM_EIDM_Msk      (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos)       /*!< 0x1FFFFFFF */

+#define FDCAN_XIDAM_EIDM          FDCAN_XIDAM_EIDM_Msk                         /*!<Extended ID Mask                          */

+

+/*****************  Bit definition for FDCAN_HPMS register  *********************/

+#define FDCAN_HPMS_BIDX_Pos       (0U)

+#define FDCAN_HPMS_BIDX_Msk       (0x3FUL << FDCAN_HPMS_BIDX_Pos)              /*!< 0x0000003F */

+#define FDCAN_HPMS_BIDX           FDCAN_HPMS_BIDX_Msk                          /*!<Buffer Index                              */

+#define FDCAN_HPMS_MSI_Pos        (6U)

+#define FDCAN_HPMS_MSI_Msk        (0x3UL << FDCAN_HPMS_MSI_Pos)                /*!< 0x000000C0 */

+#define FDCAN_HPMS_MSI            FDCAN_HPMS_MSI_Msk                           /*!<Message Storage Indicator                 */

+#define FDCAN_HPMS_FIDX_Pos       (8U)

+#define FDCAN_HPMS_FIDX_Msk       (0x7FUL << FDCAN_HPMS_FIDX_Pos)              /*!< 0x00007F00 */

+#define FDCAN_HPMS_FIDX           FDCAN_HPMS_FIDX_Msk                          /*!<Filter Index                              */

+#define FDCAN_HPMS_FLST_Pos       (15U)

+#define FDCAN_HPMS_FLST_Msk       (0x1UL << FDCAN_HPMS_FLST_Pos)               /*!< 0x00008000 */

+#define FDCAN_HPMS_FLST           FDCAN_HPMS_FLST_Msk                          /*!<Filter List                               */

+

+/*****************  Bit definition for FDCAN_NDAT1 register  ********************/

+#define FDCAN_NDAT1_ND0_Pos       (0U)

+#define FDCAN_NDAT1_ND0_Msk       (0x1UL << FDCAN_NDAT1_ND0_Pos)               /*!< 0x00000001 */

+#define FDCAN_NDAT1_ND0           FDCAN_NDAT1_ND0_Msk                          /*!<New Data flag of Rx Buffer 0              */

+#define FDCAN_NDAT1_ND1_Pos       (1U)

+#define FDCAN_NDAT1_ND1_Msk       (0x1UL << FDCAN_NDAT1_ND1_Pos)               /*!< 0x00000002 */

+#define FDCAN_NDAT1_ND1           FDCAN_NDAT1_ND1_Msk                          /*!<New Data flag of Rx Buffer 1              */

+#define FDCAN_NDAT1_ND2_Pos       (2U)

+#define FDCAN_NDAT1_ND2_Msk       (0x1UL << FDCAN_NDAT1_ND2_Pos)               /*!< 0x00000004 */

+#define FDCAN_NDAT1_ND2           FDCAN_NDAT1_ND2_Msk                          /*!<New Data flag of Rx Buffer 2              */

+#define FDCAN_NDAT1_ND3_Pos       (3U)

+#define FDCAN_NDAT1_ND3_Msk       (0x1UL << FDCAN_NDAT1_ND3_Pos)               /*!< 0x00000008 */

+#define FDCAN_NDAT1_ND3           FDCAN_NDAT1_ND3_Msk                          /*!<New Data flag of Rx Buffer 3              */

+#define FDCAN_NDAT1_ND4_Pos       (4U)

+#define FDCAN_NDAT1_ND4_Msk       (0x1UL << FDCAN_NDAT1_ND4_Pos)               /*!< 0x00000010 */

+#define FDCAN_NDAT1_ND4           FDCAN_NDAT1_ND4_Msk                          /*!<New Data flag of Rx Buffer 4              */

+#define FDCAN_NDAT1_ND5_Pos       (5U)

+#define FDCAN_NDAT1_ND5_Msk       (0x1UL << FDCAN_NDAT1_ND5_Pos)               /*!< 0x00000020 */

+#define FDCAN_NDAT1_ND5           FDCAN_NDAT1_ND5_Msk                          /*!<New Data flag of Rx Buffer 5              */

+#define FDCAN_NDAT1_ND6_Pos       (6U)

+#define FDCAN_NDAT1_ND6_Msk       (0x1UL << FDCAN_NDAT1_ND6_Pos)               /*!< 0x00000040 */

+#define FDCAN_NDAT1_ND6           FDCAN_NDAT1_ND6_Msk                          /*!<New Data flag of Rx Buffer 6              */

+#define FDCAN_NDAT1_ND7_Pos       (7U)

+#define FDCAN_NDAT1_ND7_Msk       (0x1UL << FDCAN_NDAT1_ND7_Pos)               /*!< 0x00000080 */

+#define FDCAN_NDAT1_ND7           FDCAN_NDAT1_ND7_Msk                          /*!<New Data flag of Rx Buffer 7              */

+#define FDCAN_NDAT1_ND8_Pos       (8U)

+#define FDCAN_NDAT1_ND8_Msk       (0x1UL << FDCAN_NDAT1_ND8_Pos)               /*!< 0x00000100 */

+#define FDCAN_NDAT1_ND8           FDCAN_NDAT1_ND8_Msk                          /*!<New Data flag of Rx Buffer 8              */

+#define FDCAN_NDAT1_ND9_Pos       (9U)

+#define FDCAN_NDAT1_ND9_Msk       (0x1UL << FDCAN_NDAT1_ND9_Pos)               /*!< 0x00000200 */

+#define FDCAN_NDAT1_ND9           FDCAN_NDAT1_ND9_Msk                          /*!<New Data flag of Rx Buffer 9              */

+#define FDCAN_NDAT1_ND10_Pos      (10U)

+#define FDCAN_NDAT1_ND10_Msk      (0x1UL << FDCAN_NDAT1_ND10_Pos)              /*!< 0x00000400 */

+#define FDCAN_NDAT1_ND10          FDCAN_NDAT1_ND10_Msk                         /*!<New Data flag of Rx Buffer 10             */

+#define FDCAN_NDAT1_ND11_Pos      (11U)

+#define FDCAN_NDAT1_ND11_Msk      (0x1UL << FDCAN_NDAT1_ND11_Pos)              /*!< 0x00000800 */

+#define FDCAN_NDAT1_ND11          FDCAN_NDAT1_ND11_Msk                         /*!<New Data flag of Rx Buffer 11             */

+#define FDCAN_NDAT1_ND12_Pos      (12U)

+#define FDCAN_NDAT1_ND12_Msk      (0x1UL << FDCAN_NDAT1_ND12_Pos)              /*!< 0x00001000 */

+#define FDCAN_NDAT1_ND12          FDCAN_NDAT1_ND12_Msk                         /*!<New Data flag of Rx Buffer 12             */

+#define FDCAN_NDAT1_ND13_Pos      (13U)

+#define FDCAN_NDAT1_ND13_Msk      (0x1UL << FDCAN_NDAT1_ND13_Pos)              /*!< 0x00002000 */

+#define FDCAN_NDAT1_ND13          FDCAN_NDAT1_ND13_Msk                         /*!<New Data flag of Rx Buffer 13             */

+#define FDCAN_NDAT1_ND14_Pos      (14U)

+#define FDCAN_NDAT1_ND14_Msk      (0x1UL << FDCAN_NDAT1_ND14_Pos)              /*!< 0x00004000 */

+#define FDCAN_NDAT1_ND14          FDCAN_NDAT1_ND14_Msk                         /*!<New Data flag of Rx Buffer 14             */

+#define FDCAN_NDAT1_ND15_Pos      (15U)

+#define FDCAN_NDAT1_ND15_Msk      (0x1UL << FDCAN_NDAT1_ND15_Pos)              /*!< 0x00008000 */

+#define FDCAN_NDAT1_ND15          FDCAN_NDAT1_ND15_Msk                         /*!<New Data flag of Rx Buffer 15             */

+#define FDCAN_NDAT1_ND16_Pos      (16U)

+#define FDCAN_NDAT1_ND16_Msk      (0x1UL << FDCAN_NDAT1_ND16_Pos)              /*!< 0x00010000 */

+#define FDCAN_NDAT1_ND16          FDCAN_NDAT1_ND16_Msk                         /*!<New Data flag of Rx Buffer 16             */

+#define FDCAN_NDAT1_ND17_Pos      (17U)

+#define FDCAN_NDAT1_ND17_Msk      (0x1UL << FDCAN_NDAT1_ND17_Pos)              /*!< 0x00020000 */

+#define FDCAN_NDAT1_ND17          FDCAN_NDAT1_ND17_Msk                         /*!<New Data flag of Rx Buffer 17             */

+#define FDCAN_NDAT1_ND18_Pos      (18U)

+#define FDCAN_NDAT1_ND18_Msk      (0x1UL << FDCAN_NDAT1_ND18_Pos)              /*!< 0x00040000 */

+#define FDCAN_NDAT1_ND18          FDCAN_NDAT1_ND18_Msk                         /*!<New Data flag of Rx Buffer 18             */

+#define FDCAN_NDAT1_ND19_Pos      (19U)

+#define FDCAN_NDAT1_ND19_Msk      (0x1UL << FDCAN_NDAT1_ND19_Pos)              /*!< 0x00080000 */

+#define FDCAN_NDAT1_ND19          FDCAN_NDAT1_ND19_Msk                         /*!<New Data flag of Rx Buffer 19             */

+#define FDCAN_NDAT1_ND20_Pos      (20U)

+#define FDCAN_NDAT1_ND20_Msk      (0x1UL << FDCAN_NDAT1_ND20_Pos)              /*!< 0x00100000 */

+#define FDCAN_NDAT1_ND20          FDCAN_NDAT1_ND20_Msk                         /*!<New Data flag of Rx Buffer 20             */

+#define FDCAN_NDAT1_ND21_Pos      (21U)

+#define FDCAN_NDAT1_ND21_Msk      (0x1UL << FDCAN_NDAT1_ND21_Pos)              /*!< 0x00200000 */

+#define FDCAN_NDAT1_ND21          FDCAN_NDAT1_ND21_Msk                         /*!<New Data flag of Rx Buffer 21             */

+#define FDCAN_NDAT1_ND22_Pos      (22U)

+#define FDCAN_NDAT1_ND22_Msk      (0x1UL << FDCAN_NDAT1_ND22_Pos)              /*!< 0x00400000 */

+#define FDCAN_NDAT1_ND22          FDCAN_NDAT1_ND22_Msk                         /*!<New Data flag of Rx Buffer 22             */

+#define FDCAN_NDAT1_ND23_Pos      (23U)

+#define FDCAN_NDAT1_ND23_Msk      (0x1UL << FDCAN_NDAT1_ND23_Pos)              /*!< 0x00800000 */

+#define FDCAN_NDAT1_ND23          FDCAN_NDAT1_ND23_Msk                         /*!<New Data flag of Rx Buffer 23             */

+#define FDCAN_NDAT1_ND24_Pos      (24U)

+#define FDCAN_NDAT1_ND24_Msk      (0x1UL << FDCAN_NDAT1_ND24_Pos)              /*!< 0x01000000 */

+#define FDCAN_NDAT1_ND24          FDCAN_NDAT1_ND24_Msk                         /*!<New Data flag of Rx Buffer 24             */

+#define FDCAN_NDAT1_ND25_Pos      (25U)

+#define FDCAN_NDAT1_ND25_Msk      (0x1UL << FDCAN_NDAT1_ND25_Pos)              /*!< 0x02000000 */

+#define FDCAN_NDAT1_ND25          FDCAN_NDAT1_ND25_Msk                         /*!<New Data flag of Rx Buffer 25             */

+#define FDCAN_NDAT1_ND26_Pos      (26U)

+#define FDCAN_NDAT1_ND26_Msk      (0x1UL << FDCAN_NDAT1_ND26_Pos)              /*!< 0x04000000 */

+#define FDCAN_NDAT1_ND26          FDCAN_NDAT1_ND26_Msk                         /*!<New Data flag of Rx Buffer 26             */

+#define FDCAN_NDAT1_ND27_Pos      (27U)

+#define FDCAN_NDAT1_ND27_Msk      (0x1UL << FDCAN_NDAT1_ND27_Pos)              /*!< 0x08000000 */

+#define FDCAN_NDAT1_ND27          FDCAN_NDAT1_ND27_Msk                         /*!<New Data flag of Rx Buffer 27             */

+#define FDCAN_NDAT1_ND28_Pos      (28U)

+#define FDCAN_NDAT1_ND28_Msk      (0x1UL << FDCAN_NDAT1_ND28_Pos)              /*!< 0x10000000 */

+#define FDCAN_NDAT1_ND28          FDCAN_NDAT1_ND28_Msk                         /*!<New Data flag of Rx Buffer 28             */

+#define FDCAN_NDAT1_ND29_Pos      (29U)

+#define FDCAN_NDAT1_ND29_Msk      (0x1UL << FDCAN_NDAT1_ND29_Pos)              /*!< 0x20000000 */

+#define FDCAN_NDAT1_ND29          FDCAN_NDAT1_ND29_Msk                         /*!<New Data flag of Rx Buffer 29             */

+#define FDCAN_NDAT1_ND30_Pos      (30U)

+#define FDCAN_NDAT1_ND30_Msk      (0x1UL << FDCAN_NDAT1_ND30_Pos)              /*!< 0x40000000 */

+#define FDCAN_NDAT1_ND30          FDCAN_NDAT1_ND30_Msk                         /*!<New Data flag of Rx Buffer 30             */

+#define FDCAN_NDAT1_ND31_Pos      (31U)

+#define FDCAN_NDAT1_ND31_Msk      (0x1UL << FDCAN_NDAT1_ND31_Pos)              /*!< 0x80000000 */

+#define FDCAN_NDAT1_ND31          FDCAN_NDAT1_ND31_Msk                         /*!<New Data flag of Rx Buffer 31             */

+

+/*****************  Bit definition for FDCAN_NDAT2 register  ********************/

+#define FDCAN_NDAT2_ND32_Pos      (0U)

+#define FDCAN_NDAT2_ND32_Msk      (0x1UL << FDCAN_NDAT2_ND32_Pos)              /*!< 0x00000001 */

+#define FDCAN_NDAT2_ND32          FDCAN_NDAT2_ND32_Msk                         /*!<New Data flag of Rx Buffer 32             */

+#define FDCAN_NDAT2_ND33_Pos      (1U)

+#define FDCAN_NDAT2_ND33_Msk      (0x1UL << FDCAN_NDAT2_ND33_Pos)              /*!< 0x00000002 */

+#define FDCAN_NDAT2_ND33          FDCAN_NDAT2_ND33_Msk                         /*!<New Data flag of Rx Buffer 33             */

+#define FDCAN_NDAT2_ND34_Pos      (2U)

+#define FDCAN_NDAT2_ND34_Msk      (0x1UL << FDCAN_NDAT2_ND34_Pos)              /*!< 0x00000004 */

+#define FDCAN_NDAT2_ND34          FDCAN_NDAT2_ND34_Msk                         /*!<New Data flag of Rx Buffer 34             */

+#define FDCAN_NDAT2_ND35_Pos      (3U)

+#define FDCAN_NDAT2_ND35_Msk      (0x1UL << FDCAN_NDAT2_ND35_Pos)              /*!< 0x00000008 */

+#define FDCAN_NDAT2_ND35          FDCAN_NDAT2_ND35_Msk                         /*!<New Data flag of Rx Buffer 35             */

+#define FDCAN_NDAT2_ND36_Pos      (4U)

+#define FDCAN_NDAT2_ND36_Msk      (0x1UL << FDCAN_NDAT2_ND36_Pos)              /*!< 0x00000010 */

+#define FDCAN_NDAT2_ND36          FDCAN_NDAT2_ND36_Msk                         /*!<New Data flag of Rx Buffer 36             */

+#define FDCAN_NDAT2_ND37_Pos      (5U)

+#define FDCAN_NDAT2_ND37_Msk      (0x1UL << FDCAN_NDAT2_ND37_Pos)              /*!< 0x00000020 */

+#define FDCAN_NDAT2_ND37          FDCAN_NDAT2_ND37_Msk                         /*!<New Data flag of Rx Buffer 37             */

+#define FDCAN_NDAT2_ND38_Pos      (6U)

+#define FDCAN_NDAT2_ND38_Msk      (0x1UL << FDCAN_NDAT2_ND38_Pos)              /*!< 0x00000040 */

+#define FDCAN_NDAT2_ND38          FDCAN_NDAT2_ND38_Msk                         /*!<New Data flag of Rx Buffer 38             */

+#define FDCAN_NDAT2_ND39_Pos      (7U)

+#define FDCAN_NDAT2_ND39_Msk      (0x1UL << FDCAN_NDAT2_ND39_Pos)              /*!< 0x00000080 */

+#define FDCAN_NDAT2_ND39          FDCAN_NDAT2_ND39_Msk                         /*!<New Data flag of Rx Buffer 39             */

+#define FDCAN_NDAT2_ND40_Pos      (8U)

+#define FDCAN_NDAT2_ND40_Msk      (0x1UL << FDCAN_NDAT2_ND40_Pos)              /*!< 0x00000100 */

+#define FDCAN_NDAT2_ND40          FDCAN_NDAT2_ND40_Msk                         /*!<New Data flag of Rx Buffer 40             */

+#define FDCAN_NDAT2_ND41_Pos      (9U)

+#define FDCAN_NDAT2_ND41_Msk      (0x1UL << FDCAN_NDAT2_ND41_Pos)              /*!< 0x00000200 */

+#define FDCAN_NDAT2_ND41          FDCAN_NDAT2_ND41_Msk                         /*!<New Data flag of Rx Buffer 41             */

+#define FDCAN_NDAT2_ND42_Pos      (10U)

+#define FDCAN_NDAT2_ND42_Msk      (0x1UL << FDCAN_NDAT2_ND42_Pos)              /*!< 0x00000400 */

+#define FDCAN_NDAT2_ND42          FDCAN_NDAT2_ND42_Msk                         /*!<New Data flag of Rx Buffer 42             */

+#define FDCAN_NDAT2_ND43_Pos      (11U)

+#define FDCAN_NDAT2_ND43_Msk      (0x1UL << FDCAN_NDAT2_ND43_Pos)              /*!< 0x00000800 */

+#define FDCAN_NDAT2_ND43          FDCAN_NDAT2_ND43_Msk                         /*!<New Data flag of Rx Buffer 43             */

+#define FDCAN_NDAT2_ND44_Pos      (12U)

+#define FDCAN_NDAT2_ND44_Msk      (0x1UL << FDCAN_NDAT2_ND44_Pos)              /*!< 0x00001000 */

+#define FDCAN_NDAT2_ND44          FDCAN_NDAT2_ND44_Msk                         /*!<New Data flag of Rx Buffer 44             */

+#define FDCAN_NDAT2_ND45_Pos      (13U)

+#define FDCAN_NDAT2_ND45_Msk      (0x1UL << FDCAN_NDAT2_ND45_Pos)              /*!< 0x00002000 */

+#define FDCAN_NDAT2_ND45          FDCAN_NDAT2_ND45_Msk                         /*!<New Data flag of Rx Buffer 45             */

+#define FDCAN_NDAT2_ND46_Pos      (14U)

+#define FDCAN_NDAT2_ND46_Msk      (0x1UL << FDCAN_NDAT2_ND46_Pos)              /*!< 0x00004000 */

+#define FDCAN_NDAT2_ND46          FDCAN_NDAT2_ND46_Msk                         /*!<New Data flag of Rx Buffer 46             */

+#define FDCAN_NDAT2_ND47_Pos      (15U)

+#define FDCAN_NDAT2_ND47_Msk      (0x1UL << FDCAN_NDAT2_ND47_Pos)              /*!< 0x00008000 */

+#define FDCAN_NDAT2_ND47          FDCAN_NDAT2_ND47_Msk                         /*!<New Data flag of Rx Buffer 47             */

+#define FDCAN_NDAT2_ND48_Pos      (16U)

+#define FDCAN_NDAT2_ND48_Msk      (0x1UL << FDCAN_NDAT2_ND48_Pos)              /*!< 0x00010000 */

+#define FDCAN_NDAT2_ND48          FDCAN_NDAT2_ND48_Msk                         /*!<New Data flag of Rx Buffer 48             */

+#define FDCAN_NDAT2_ND49_Pos      (17U)

+#define FDCAN_NDAT2_ND49_Msk      (0x1UL << FDCAN_NDAT2_ND49_Pos)              /*!< 0x00020000 */

+#define FDCAN_NDAT2_ND49          FDCAN_NDAT2_ND49_Msk                         /*!<New Data flag of Rx Buffer 49             */

+#define FDCAN_NDAT2_ND50_Pos      (18U)

+#define FDCAN_NDAT2_ND50_Msk      (0x1UL << FDCAN_NDAT2_ND50_Pos)              /*!< 0x00040000 */

+#define FDCAN_NDAT2_ND50          FDCAN_NDAT2_ND50_Msk                         /*!<New Data flag of Rx Buffer 50             */

+#define FDCAN_NDAT2_ND51_Pos      (19U)

+#define FDCAN_NDAT2_ND51_Msk      (0x1UL << FDCAN_NDAT2_ND51_Pos)              /*!< 0x00080000 */

+#define FDCAN_NDAT2_ND51          FDCAN_NDAT2_ND51_Msk                         /*!<New Data flag of Rx Buffer 51             */

+#define FDCAN_NDAT2_ND52_Pos      (20U)

+#define FDCAN_NDAT2_ND52_Msk      (0x1UL << FDCAN_NDAT2_ND52_Pos)              /*!< 0x00100000 */

+#define FDCAN_NDAT2_ND52          FDCAN_NDAT2_ND52_Msk                         /*!<New Data flag of Rx Buffer 52             */

+#define FDCAN_NDAT2_ND53_Pos      (21U)

+#define FDCAN_NDAT2_ND53_Msk      (0x1UL << FDCAN_NDAT2_ND53_Pos)              /*!< 0x00200000 */

+#define FDCAN_NDAT2_ND53          FDCAN_NDAT2_ND53_Msk                         /*!<New Data flag of Rx Buffer 53             */

+#define FDCAN_NDAT2_ND54_Pos      (22U)

+#define FDCAN_NDAT2_ND54_Msk      (0x1UL << FDCAN_NDAT2_ND54_Pos)              /*!< 0x00400000 */

+#define FDCAN_NDAT2_ND54          FDCAN_NDAT2_ND54_Msk                         /*!<New Data flag of Rx Buffer 54             */

+#define FDCAN_NDAT2_ND55_Pos      (23U)

+#define FDCAN_NDAT2_ND55_Msk      (0x1UL << FDCAN_NDAT2_ND55_Pos)              /*!< 0x00800000 */

+#define FDCAN_NDAT2_ND55          FDCAN_NDAT2_ND55_Msk                         /*!<New Data flag of Rx Buffer 55             */

+#define FDCAN_NDAT2_ND56_Pos      (24U)

+#define FDCAN_NDAT2_ND56_Msk      (0x1UL << FDCAN_NDAT2_ND56_Pos)              /*!< 0x01000000 */

+#define FDCAN_NDAT2_ND56          FDCAN_NDAT2_ND56_Msk                         /*!<New Data flag of Rx Buffer 56             */

+#define FDCAN_NDAT2_ND57_Pos      (25U)

+#define FDCAN_NDAT2_ND57_Msk      (0x1UL << FDCAN_NDAT2_ND57_Pos)              /*!< 0x02000000 */

+#define FDCAN_NDAT2_ND57          FDCAN_NDAT2_ND57_Msk                         /*!<New Data flag of Rx Buffer 57             */

+#define FDCAN_NDAT2_ND58_Pos      (26U)

+#define FDCAN_NDAT2_ND58_Msk      (0x1UL << FDCAN_NDAT2_ND58_Pos)              /*!< 0x04000000 */

+#define FDCAN_NDAT2_ND58          FDCAN_NDAT2_ND58_Msk                         /*!<New Data flag of Rx Buffer 58             */

+#define FDCAN_NDAT2_ND59_Pos      (27U)

+#define FDCAN_NDAT2_ND59_Msk      (0x1UL << FDCAN_NDAT2_ND59_Pos)              /*!< 0x08000000 */

+#define FDCAN_NDAT2_ND59          FDCAN_NDAT2_ND59_Msk                         /*!<New Data flag of Rx Buffer 59             */

+#define FDCAN_NDAT2_ND60_Pos      (28U)

+#define FDCAN_NDAT2_ND60_Msk      (0x1UL << FDCAN_NDAT2_ND60_Pos)              /*!< 0x10000000 */

+#define FDCAN_NDAT2_ND60          FDCAN_NDAT2_ND60_Msk                         /*!<New Data flag of Rx Buffer 60             */

+#define FDCAN_NDAT2_ND61_Pos      (29U)

+#define FDCAN_NDAT2_ND61_Msk      (0x1UL << FDCAN_NDAT2_ND61_Pos)              /*!< 0x20000000 */

+#define FDCAN_NDAT2_ND61          FDCAN_NDAT2_ND61_Msk                         /*!<New Data flag of Rx Buffer 61             */

+#define FDCAN_NDAT2_ND62_Pos      (30U)

+#define FDCAN_NDAT2_ND62_Msk      (0x1UL << FDCAN_NDAT2_ND62_Pos)              /*!< 0x40000000 */

+#define FDCAN_NDAT2_ND62          FDCAN_NDAT2_ND62_Msk                         /*!<New Data flag of Rx Buffer 62             */

+#define FDCAN_NDAT2_ND63_Pos      (31U)

+#define FDCAN_NDAT2_ND63_Msk      (0x1UL << FDCAN_NDAT2_ND63_Pos)              /*!< 0x80000000 */

+#define FDCAN_NDAT2_ND63          FDCAN_NDAT2_ND63_Msk                         /*!<New Data flag of Rx Buffer 63             */

+

+/*****************  Bit definition for FDCAN_RXF0C register  ********************/

+#define FDCAN_RXF0C_F0SA_Pos      (2U)

+#define FDCAN_RXF0C_F0SA_Msk      (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_RXF0C_F0SA          FDCAN_RXF0C_F0SA_Msk                         /*!<Rx FIFO 0 Start Address                   */

+#define FDCAN_RXF0C_F0S_Pos       (16U)

+#define FDCAN_RXF0C_F0S_Msk       (0x7FUL << FDCAN_RXF0C_F0S_Pos)              /*!< 0x007F0000 */

+#define FDCAN_RXF0C_F0S           FDCAN_RXF0C_F0S_Msk                          /*!<Number of Rx FIFO 0 elements              */

+#define FDCAN_RXF0C_F0WM_Pos      (24U)

+#define FDCAN_RXF0C_F0WM_Msk      (0x7FUL << FDCAN_RXF0C_F0WM_Pos)             /*!< 0x7F000000 */

+#define FDCAN_RXF0C_F0WM          FDCAN_RXF0C_F0WM_Msk                         /*!<FIFO 0 Watermark                          */

+#define FDCAN_RXF0C_F0OM_Pos      (31U)

+#define FDCAN_RXF0C_F0OM_Msk      (0x1UL << FDCAN_RXF0C_F0OM_Pos)              /*!< 0x80000000 */

+#define FDCAN_RXF0C_F0OM          FDCAN_RXF0C_F0OM_Msk                         /*!<FIFO 0 Operation Mode                     */

+

+/*****************  Bit definition for FDCAN_RXF0S register  ********************/

+#define FDCAN_RXF0S_F0FL_Pos      (0U)

+#define FDCAN_RXF0S_F0FL_Msk      (0x7FUL << FDCAN_RXF0S_F0FL_Pos)             /*!< 0x0000007F */

+#define FDCAN_RXF0S_F0FL          FDCAN_RXF0S_F0FL_Msk                         /*!<Rx FIFO 0 Fill Level                      */

+#define FDCAN_RXF0S_F0GI_Pos      (8U)

+#define FDCAN_RXF0S_F0GI_Msk      (0x3FUL << FDCAN_RXF0S_F0GI_Pos)             /*!< 0x00003F00 */

+#define FDCAN_RXF0S_F0GI          FDCAN_RXF0S_F0GI_Msk                         /*!<Rx FIFO 0 Get Index                       */

+#define FDCAN_RXF0S_F0PI_Pos      (16U)

+#define FDCAN_RXF0S_F0PI_Msk      (0x3FUL << FDCAN_RXF0S_F0PI_Pos)             /*!< 0x003F0000 */

+#define FDCAN_RXF0S_F0PI          FDCAN_RXF0S_F0PI_Msk                         /*!<Rx FIFO 0 Put Index                       */

+#define FDCAN_RXF0S_F0F_Pos       (24U)

+#define FDCAN_RXF0S_F0F_Msk       (0x1UL << FDCAN_RXF0S_F0F_Pos)               /*!< 0x01000000 */

+#define FDCAN_RXF0S_F0F           FDCAN_RXF0S_F0F_Msk                          /*!<Rx FIFO 0 Full                            */

+#define FDCAN_RXF0S_RF0L_Pos      (25U)

+#define FDCAN_RXF0S_RF0L_Msk      (0x1UL << FDCAN_RXF0S_RF0L_Pos)              /*!< 0x02000000 */

+#define FDCAN_RXF0S_RF0L          FDCAN_RXF0S_RF0L_Msk                         /*!<Rx FIFO 0 Message Lost                    */

+

+/*****************  Bit definition for FDCAN_RXF0A register  ********************/

+#define FDCAN_RXF0A_F0AI_Pos      (0U)

+#define FDCAN_RXF0A_F0AI_Msk      (0x3FUL << FDCAN_RXF0A_F0AI_Pos)             /*!< 0x0000003F */

+#define FDCAN_RXF0A_F0AI          FDCAN_RXF0A_F0AI_Msk                         /*!<Rx FIFO 0 Acknowledge Index               */

+

+/*****************  Bit definition for FDCAN_RXBC register  ********************/

+#define FDCAN_RXBC_RBSA_Pos       (2U)

+#define FDCAN_RXBC_RBSA_Msk       (0x3FFFUL << FDCAN_RXBC_RBSA_Pos)            /*!< 0x0000FFFC */

+#define FDCAN_RXBC_RBSA           FDCAN_RXBC_RBSA_Msk                          /*!<Rx Buffer Start Address                   */

+

+/*****************  Bit definition for FDCAN_RXF1C register  ********************/

+#define FDCAN_RXF1C_F1SA_Pos      (2U)

+#define FDCAN_RXF1C_F1SA_Msk      (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_RXF1C_F1SA          FDCAN_RXF1C_F1SA_Msk                         /*!<Rx FIFO 1 Start Address                   */

+#define FDCAN_RXF1C_F1S_Pos       (16U)

+#define FDCAN_RXF1C_F1S_Msk       (0x7FUL << FDCAN_RXF1C_F1S_Pos)              /*!< 0x007F0000 */

+#define FDCAN_RXF1C_F1S           FDCAN_RXF1C_F1S_Msk                          /*!<Number of Rx FIFO 1 elements              */

+#define FDCAN_RXF1C_F1WM_Pos      (24U)

+#define FDCAN_RXF1C_F1WM_Msk      (0x7FUL << FDCAN_RXF1C_F1WM_Pos)             /*!< 0x7F000000 */

+#define FDCAN_RXF1C_F1WM          FDCAN_RXF1C_F1WM_Msk                         /*!<Rx FIFO 1 Watermark                       */

+#define FDCAN_RXF1C_F1OM_Pos      (31U)

+#define FDCAN_RXF1C_F1OM_Msk      (0x1UL << FDCAN_RXF1C_F1OM_Pos)              /*!< 0x80000000 */

+#define FDCAN_RXF1C_F1OM          FDCAN_RXF1C_F1OM_Msk                         /*!<FIFO 1 Operation Mode                     */

+

+/*****************  Bit definition for FDCAN_RXF1S register  ********************/

+#define FDCAN_RXF1S_F1FL_Pos      (0U)

+#define FDCAN_RXF1S_F1FL_Msk      (0x7FUL << FDCAN_RXF1S_F1FL_Pos)             /*!< 0x0000007F */

+#define FDCAN_RXF1S_F1FL          FDCAN_RXF1S_F1FL_Msk                         /*!<Rx FIFO 1 Fill Level                      */

+#define FDCAN_RXF1S_F1GI_Pos      (8U)

+#define FDCAN_RXF1S_F1GI_Msk      (0x3FUL << FDCAN_RXF1S_F1GI_Pos)             /*!< 0x00003F00 */

+#define FDCAN_RXF1S_F1GI          FDCAN_RXF1S_F1GI_Msk                         /*!<Rx FIFO 1 Get Index                       */

+#define FDCAN_RXF1S_F1PI_Pos      (16U)

+#define FDCAN_RXF1S_F1PI_Msk      (0x3FUL << FDCAN_RXF1S_F1PI_Pos)             /*!< 0x003F0000 */

+#define FDCAN_RXF1S_F1PI          FDCAN_RXF1S_F1PI_Msk                         /*!<Rx FIFO 1 Put Index                       */

+#define FDCAN_RXF1S_F1F_Pos       (24U)

+#define FDCAN_RXF1S_F1F_Msk       (0x1UL << FDCAN_RXF1S_F1F_Pos)               /*!< 0x01000000 */

+#define FDCAN_RXF1S_F1F           FDCAN_RXF1S_F1F_Msk                          /*!<Rx FIFO 1 Full                            */

+#define FDCAN_RXF1S_RF1L_Pos      (25U)

+#define FDCAN_RXF1S_RF1L_Msk      (0x1UL << FDCAN_RXF1S_RF1L_Pos)              /*!< 0x02000000 */

+#define FDCAN_RXF1S_RF1L          FDCAN_RXF1S_RF1L_Msk                         /*!<Rx FIFO 1 Message Lost                    */

+

+/*****************  Bit definition for FDCAN_RXF1A register  ********************/

+#define FDCAN_RXF1A_F1AI_Pos      (0U)

+#define FDCAN_RXF1A_F1AI_Msk      (0x3FUL << FDCAN_RXF1A_F1AI_Pos)             /*!< 0x0000003F */

+#define FDCAN_RXF1A_F1AI          FDCAN_RXF1A_F1AI_Msk                         /*!<Rx FIFO 1 Acknowledge Index               */

+

+/*****************  Bit definition for FDCAN_RXESC register  ********************/

+#define FDCAN_RXESC_F0DS_Pos      (0U)

+#define FDCAN_RXESC_F0DS_Msk      (0x7UL << FDCAN_RXESC_F0DS_Pos)              /*!< 0x00000007 */

+#define FDCAN_RXESC_F0DS          FDCAN_RXESC_F0DS_Msk                         /*!<Rx FIFO 1 Data Field Size                 */

+#define FDCAN_RXESC_F1DS_Pos      (4U)

+#define FDCAN_RXESC_F1DS_Msk      (0x7UL << FDCAN_RXESC_F1DS_Pos)              /*!< 0x00000070 */

+#define FDCAN_RXESC_F1DS          FDCAN_RXESC_F1DS_Msk                         /*!<Rx FIFO 0 Data Field Size                 */

+#define FDCAN_RXESC_RBDS_Pos      (8U)

+#define FDCAN_RXESC_RBDS_Msk      (0x7UL << FDCAN_RXESC_RBDS_Pos)              /*!< 0x00000700 */

+#define FDCAN_RXESC_RBDS          FDCAN_RXESC_RBDS_Msk                         /*!<Rx Buffer Data Field Size                 */

+

+/*****************  Bit definition for FDCAN_TXBC register  *********************/

+#define FDCAN_TXBC_TBSA_Pos       (2U)

+#define FDCAN_TXBC_TBSA_Msk       (0x3FFFUL << FDCAN_TXBC_TBSA_Pos)            /*!< 0x0000FFFC */

+#define FDCAN_TXBC_TBSA           FDCAN_TXBC_TBSA_Msk                          /*!<Tx Buffers Start Address                  */

+#define FDCAN_TXBC_NDTB_Pos       (16U)

+#define FDCAN_TXBC_NDTB_Msk       (0x3FUL << FDCAN_TXBC_NDTB_Pos)              /*!< 0x003F0000 */

+#define FDCAN_TXBC_NDTB           FDCAN_TXBC_NDTB_Msk                          /*!<Number of Dedicated Transmit Buffers      */

+#define FDCAN_TXBC_TFQS_Pos       (24U)

+#define FDCAN_TXBC_TFQS_Msk       (0x3FUL << FDCAN_TXBC_TFQS_Pos)              /*!< 0x3F000000 */

+#define FDCAN_TXBC_TFQS           FDCAN_TXBC_TFQS_Msk                          /*!<Transmit FIFO/Queue Size                  */

+#define FDCAN_TXBC_TFQM_Pos       (30U)

+#define FDCAN_TXBC_TFQM_Msk       (0x1UL << FDCAN_TXBC_TFQM_Pos)               /*!< 0x40000000 */

+#define FDCAN_TXBC_TFQM           FDCAN_TXBC_TFQM_Msk                          /*!<Tx FIFO/Queue Mode                        */

+

+/*****************  Bit definition for FDCAN_TXFQS register  *********************/

+#define FDCAN_TXFQS_TFFL_Pos      (0U)

+#define FDCAN_TXFQS_TFFL_Msk      (0x3FUL << FDCAN_TXFQS_TFFL_Pos)             /*!< 0x0000003F */

+#define FDCAN_TXFQS_TFFL          FDCAN_TXFQS_TFFL_Msk                         /*!<Tx FIFO Free Level                        */

+#define FDCAN_TXFQS_TFGI_Pos      (8U)

+#define FDCAN_TXFQS_TFGI_Msk      (0x1FUL << FDCAN_TXFQS_TFGI_Pos)             /*!< 0x00001F00 */

+#define FDCAN_TXFQS_TFGI          FDCAN_TXFQS_TFGI_Msk                         /*!<Tx FIFO Get Index                         */

+#define FDCAN_TXFQS_TFQPI_Pos     (16U)

+#define FDCAN_TXFQS_TFQPI_Msk     (0x1FUL << FDCAN_TXFQS_TFQPI_Pos)            /*!< 0x001F0000 */

+#define FDCAN_TXFQS_TFQPI         FDCAN_TXFQS_TFQPI_Msk                        /*!<Tx FIFO/Queue Put Index                   */

+#define FDCAN_TXFQS_TFQF_Pos      (21U)

+#define FDCAN_TXFQS_TFQF_Msk      (0x1UL << FDCAN_TXFQS_TFQF_Pos)              /*!< 0x00200000 */

+#define FDCAN_TXFQS_TFQF          FDCAN_TXFQS_TFQF_Msk                         /*!<Tx FIFO/Queue Full                        */

+

+/*****************  Bit definition for FDCAN_TXESC register  *********************/

+#define FDCAN_TXESC_TBDS_Pos      (0U)

+#define FDCAN_TXESC_TBDS_Msk      (0x7UL << FDCAN_TXESC_TBDS_Pos)              /*!< 0x00000007 */

+#define FDCAN_TXESC_TBDS          FDCAN_TXESC_TBDS_Msk                         /*!<Tx Buffer Data Field Size                 */

+

+/*****************  Bit definition for FDCAN_TXBRP register  *********************/

+#define FDCAN_TXBRP_TRP_Pos       (0U)

+#define FDCAN_TXBRP_TRP_Msk       (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos)        /*!< 0xFFFFFFFF */

+#define FDCAN_TXBRP_TRP           FDCAN_TXBRP_TRP_Msk                          /*!<Transmission Request Pending              */

+

+/*****************  Bit definition for FDCAN_TXBAR register  *********************/

+#define FDCAN_TXBAR_AR_Pos        (0U)

+#define FDCAN_TXBAR_AR_Msk        (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBAR_AR            FDCAN_TXBAR_AR_Msk                           /*!<Add Request                               */

+

+/*****************  Bit definition for FDCAN_TXBCR register  *********************/

+#define FDCAN_TXBCR_CR_Pos        (0U)

+#define FDCAN_TXBCR_CR_Msk        (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCR_CR            FDCAN_TXBCR_CR_Msk                           /*!<Cancellation Request                      */

+

+/*****************  Bit definition for FDCAN_TXBTO register  *********************/

+#define FDCAN_TXBTO_TO_Pos        (0U)

+#define FDCAN_TXBTO_TO_Msk        (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBTO_TO            FDCAN_TXBTO_TO_Msk                           /*!<Transmission Occurred                     */

+

+/*****************  Bit definition for FDCAN_TXBCF register  *********************/

+#define FDCAN_TXBCF_CF_Pos        (0U)

+#define FDCAN_TXBCF_CF_Msk        (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos)         /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCF_CF            FDCAN_TXBCF_CF_Msk                           /*!<Cancellation Finished                     */

+

+/*****************  Bit definition for FDCAN_TXBTIE register  ********************/

+#define FDCAN_TXBTIE_TIE_Pos      (0U)

+#define FDCAN_TXBTIE_TIE_Msk      (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos)       /*!< 0xFFFFFFFF */

+#define FDCAN_TXBTIE_TIE          FDCAN_TXBTIE_TIE_Msk                         /*!<Transmission Interrupt Enable             */

+

+/*****************  Bit definition for FDCAN_ TXBCIE register  *******************/

+#define FDCAN_TXBCIE_CFIE_Pos     (0U)

+#define FDCAN_TXBCIE_CFIE_Msk     (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos)      /*!< 0xFFFFFFFF */

+#define FDCAN_TXBCIE_CFIE         FDCAN_TXBCIE_CFIE_Msk                        /*!<Cancellation Finished Interrupt Enable    */

+

+/*****************  Bit definition for FDCAN_TXEFC register  *********************/

+#define FDCAN_TXEFC_EFSA_Pos      (2U)

+#define FDCAN_TXEFC_EFSA_Msk      (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_TXEFC_EFSA          FDCAN_TXEFC_EFSA_Msk                         /*!<Event FIFO Start Address                  */

+#define FDCAN_TXEFC_EFS_Pos       (16U)

+#define FDCAN_TXEFC_EFS_Msk       (0x3FUL << FDCAN_TXEFC_EFS_Pos)              /*!< 0x003F0000 */

+#define FDCAN_TXEFC_EFS           FDCAN_TXEFC_EFS_Msk                          /*!<Event FIFO Size                           */

+#define FDCAN_TXEFC_EFWM_Pos      (24U)

+#define FDCAN_TXEFC_EFWM_Msk      (0x3FUL << FDCAN_TXEFC_EFWM_Pos)             /*!< 0x3F000000 */

+#define FDCAN_TXEFC_EFWM          FDCAN_TXEFC_EFWM_Msk                         /*!<Event FIFO Watermark                      */

+

+/*****************  Bit definition for FDCAN_TXEFS register  *********************/

+#define FDCAN_TXEFS_EFFL_Pos      (0U)

+#define FDCAN_TXEFS_EFFL_Msk      (0x3FUL << FDCAN_TXEFS_EFFL_Pos)             /*!< 0x0000003F */

+#define FDCAN_TXEFS_EFFL          FDCAN_TXEFS_EFFL_Msk                         /*!<Event FIFO Fill Level                     */

+#define FDCAN_TXEFS_EFGI_Pos      (8U)

+#define FDCAN_TXEFS_EFGI_Msk      (0x1FUL << FDCAN_TXEFS_EFGI_Pos)             /*!< 0x00001F00 */

+#define FDCAN_TXEFS_EFGI          FDCAN_TXEFS_EFGI_Msk                         /*!<Event FIFO Get Index                      */

+#define FDCAN_TXEFS_EFPI_Pos      (16U)

+#define FDCAN_TXEFS_EFPI_Msk      (0x1FUL << FDCAN_TXEFS_EFPI_Pos)             /*!< 0x001F0000 */

+#define FDCAN_TXEFS_EFPI          FDCAN_TXEFS_EFPI_Msk                         /*!<Event FIFO Put Index                      */

+#define FDCAN_TXEFS_EFF_Pos       (24U)

+#define FDCAN_TXEFS_EFF_Msk       (0x1UL << FDCAN_TXEFS_EFF_Pos)               /*!< 0x01000000 */

+#define FDCAN_TXEFS_EFF           FDCAN_TXEFS_EFF_Msk                          /*!<Event FIFO Full                           */

+#define FDCAN_TXEFS_TEFL_Pos      (25U)

+#define FDCAN_TXEFS_TEFL_Msk      (0x1UL << FDCAN_TXEFS_TEFL_Pos)              /*!< 0x02000000 */

+#define FDCAN_TXEFS_TEFL          FDCAN_TXEFS_TEFL_Msk                         /*!<Tx Event FIFO Element Lost                */

+

+/*****************  Bit definition for FDCAN_TXEFA register  *********************/

+#define FDCAN_TXEFA_EFAI_Pos      (0U)

+#define FDCAN_TXEFA_EFAI_Msk      (0x1FUL << FDCAN_TXEFA_EFAI_Pos)             /*!< 0x0000001F */

+#define FDCAN_TXEFA_EFAI          FDCAN_TXEFA_EFAI_Msk                         /*!<Event FIFO Acknowledge Index              */

+

+/*****************  Bit definition for FDCAN_TTTMC register  *********************/

+#define FDCAN_TTTMC_TMSA_Pos      (2U)

+#define FDCAN_TTTMC_TMSA_Msk      (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos)           /*!< 0x0000FFFC */

+#define FDCAN_TTTMC_TMSA          FDCAN_TTTMC_TMSA_Msk                         /*!<Trigger Memory Start Address              */

+#define FDCAN_TTTMC_TME_Pos       (16U)

+#define FDCAN_TTTMC_TME_Msk       (0x7FUL << FDCAN_TTTMC_TME_Pos)              /*!< 0x007F0000 */

+#define FDCAN_TTTMC_TME           FDCAN_TTTMC_TME_Msk                          /*!<Trigger Memory Elements                   */

+

+/*****************  Bit definition for FDCAN_TTRMC register  *********************/

+#define FDCAN_TTRMC_RID_Pos       (0U)

+#define FDCAN_TTRMC_RID_Msk       (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos)        /*!< 0x1FFFFFFF */

+#define FDCAN_TTRMC_RID           FDCAN_TTRMC_RID_Msk                          /*!<Reference Identifier                      */

+#define FDCAN_TTRMC_XTD_Pos       (30U)

+#define FDCAN_TTRMC_XTD_Msk       (0x1UL << FDCAN_TTRMC_XTD_Pos)               /*!< 0x40000000 */

+#define FDCAN_TTRMC_XTD           FDCAN_TTRMC_XTD_Msk                          /*!< Extended Identifier                      */

+#define FDCAN_TTRMC_RMPS_Pos      (31U)

+#define FDCAN_TTRMC_RMPS_Msk      (0x1UL << FDCAN_TTRMC_RMPS_Pos)              /*!< 0x80000000 */

+#define FDCAN_TTRMC_RMPS          FDCAN_TTRMC_RMPS_Msk                         /*!<Reference Message Payload Select          */

+

+/*****************  Bit definition for FDCAN_TTOCF register  *********************/

+#define FDCAN_TTOCF_OM_Pos        (0U)

+#define FDCAN_TTOCF_OM_Msk        (0x3UL << FDCAN_TTOCF_OM_Pos)                /*!< 0x00000003 */

+#define FDCAN_TTOCF_OM            FDCAN_TTOCF_OM_Msk                           /*!<Operation Mode                            */

+#define FDCAN_TTOCF_GEN_Pos       (3U)

+#define FDCAN_TTOCF_GEN_Msk       (0x1UL << FDCAN_TTOCF_GEN_Pos)               /*!< 0x00000008 */

+#define FDCAN_TTOCF_GEN           FDCAN_TTOCF_GEN_Msk                          /*!<Gap Enable                                */

+#define FDCAN_TTOCF_TM_Pos        (4U)

+#define FDCAN_TTOCF_TM_Msk        (0x1UL << FDCAN_TTOCF_TM_Pos)                /*!< 0x00000010 */

+#define FDCAN_TTOCF_TM            FDCAN_TTOCF_TM_Msk                           /*!<Time Master                               */

+#define FDCAN_TTOCF_LDSDL_Pos     (5U)

+#define FDCAN_TTOCF_LDSDL_Msk     (0x7UL << FDCAN_TTOCF_LDSDL_Pos)             /*!< 0x000000E0 */

+#define FDCAN_TTOCF_LDSDL         FDCAN_TTOCF_LDSDL_Msk                        /*!<LD of Synchronization Deviation Limit     */

+#define FDCAN_TTOCF_IRTO_Pos      (8U)

+#define FDCAN_TTOCF_IRTO_Msk      (0x7FUL << FDCAN_TTOCF_IRTO_Pos)             /*!< 0x00007F00 */

+#define FDCAN_TTOCF_IRTO          FDCAN_TTOCF_IRTO_Msk                         /*!<Initial Reference Trigger Offset          */

+#define FDCAN_TTOCF_EECS_Pos      (15U)

+#define FDCAN_TTOCF_EECS_Msk      (0x1UL << FDCAN_TTOCF_EECS_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTOCF_EECS          FDCAN_TTOCF_EECS_Msk                         /*!<Enable External Clock Synchronization     */

+#define FDCAN_TTOCF_AWL_Pos       (16U)

+#define FDCAN_TTOCF_AWL_Msk       (0xFFUL << FDCAN_TTOCF_AWL_Pos)              /*!< 0x00FF0000 */

+#define FDCAN_TTOCF_AWL           FDCAN_TTOCF_AWL_Msk                          /*!<Application Watchdog Limit                */

+#define FDCAN_TTOCF_EGTF_Pos      (24U)

+#define FDCAN_TTOCF_EGTF_Msk      (0x1UL << FDCAN_TTOCF_EGTF_Pos)              /*!< 0x01000000 */

+#define FDCAN_TTOCF_EGTF          FDCAN_TTOCF_EGTF_Msk                         /*!<Enable Global Time Filtering              */

+#define FDCAN_TTOCF_ECC_Pos       (25U)

+#define FDCAN_TTOCF_ECC_Msk       (0x1UL << FDCAN_TTOCF_ECC_Pos)               /*!< 0x02000000 */

+#define FDCAN_TTOCF_ECC           FDCAN_TTOCF_ECC_Msk                          /*!<Enable Clock Calibration                  */

+#define FDCAN_TTOCF_EVTP_Pos      (26U)

+#define FDCAN_TTOCF_EVTP_Msk      (0x1UL << FDCAN_TTOCF_EVTP_Pos)              /*!< 0x04000000 */

+#define FDCAN_TTOCF_EVTP          FDCAN_TTOCF_EVTP_Msk                         /*!<Event Trigger Polarity                    */

+

+/*****************  Bit definition for FDCAN_TTMLM register  *********************/

+#define FDCAN_TTMLM_CCM_Pos       (0U)

+#define FDCAN_TTMLM_CCM_Msk       (0x3FUL << FDCAN_TTMLM_CCM_Pos)              /*!< 0x0000003F */

+#define FDCAN_TTMLM_CCM           FDCAN_TTMLM_CCM_Msk                          /*!<Cycle Count Max                           */

+#define FDCAN_TTMLM_CSS_Pos       (6U)

+#define FDCAN_TTMLM_CSS_Msk       (0x3UL << FDCAN_TTMLM_CSS_Pos)               /*!< 0x000000C0 */

+#define FDCAN_TTMLM_CSS           FDCAN_TTMLM_CSS_Msk                          /*!<Cycle Start Synchronization               */

+#define FDCAN_TTMLM_TXEW_Pos      (8U)

+#define FDCAN_TTMLM_TXEW_Msk      (0xFUL << FDCAN_TTMLM_TXEW_Pos)              /*!< 0x00000F00 */

+#define FDCAN_TTMLM_TXEW          FDCAN_TTMLM_TXEW_Msk                         /*!<Tx Enable Window                          */

+#define FDCAN_TTMLM_ENTT_Pos      (16U)

+#define FDCAN_TTMLM_ENTT_Msk      (0xFFFUL << FDCAN_TTMLM_ENTT_Pos)            /*!< 0x0FFF0000 */

+#define FDCAN_TTMLM_ENTT          FDCAN_TTMLM_ENTT_Msk                         /*!<Expected Number of Tx Triggers            */

+

+/*****************  Bit definition for FDCAN_TURCF register  *********************/

+#define FDCAN_TURCF_NCL_Pos       (0U)

+#define FDCAN_TURCF_NCL_Msk       (0xFFFFUL << FDCAN_TURCF_NCL_Pos)            /*!< 0x0000FFFF */

+#define FDCAN_TURCF_NCL           FDCAN_TURCF_NCL_Msk                          /*!<Numerator Configuration Low               */

+#define FDCAN_TURCF_DC_Pos        (16U)

+#define FDCAN_TURCF_DC_Msk        (0x3FFFUL << FDCAN_TURCF_DC_Pos)             /*!< 0x3FFF0000 */

+#define FDCAN_TURCF_DC            FDCAN_TURCF_DC_Msk                           /*!<Denominator Configuration                 */

+#define FDCAN_TURCF_ELT_Pos       (31U)

+#define FDCAN_TURCF_ELT_Msk       (0x1UL << FDCAN_TURCF_ELT_Pos)               /*!< 0x80000000 */

+#define FDCAN_TURCF_ELT           FDCAN_TURCF_ELT_Msk                          /*!<Enable Local Time                         */

+

+/*****************  Bit definition for FDCAN_TTOCN register  ********************/

+#define FDCAN_TTOCN_SGT_Pos       (0U)

+#define FDCAN_TTOCN_SGT_Msk       (0x1UL << FDCAN_TTOCN_SGT_Pos)               /*!< 0x00000001 */

+#define FDCAN_TTOCN_SGT           FDCAN_TTOCN_SGT_Msk                          /*!<Set Global time                           */

+#define FDCAN_TTOCN_ECS_Pos       (1U)

+#define FDCAN_TTOCN_ECS_Msk       (0x1UL << FDCAN_TTOCN_ECS_Pos)               /*!< 0x00000002 */

+#define FDCAN_TTOCN_ECS           FDCAN_TTOCN_ECS_Msk                          /*!<External Clock Synchronization            */

+#define FDCAN_TTOCN_SWP_Pos       (2U)

+#define FDCAN_TTOCN_SWP_Msk       (0x1UL << FDCAN_TTOCN_SWP_Pos)               /*!< 0x00000004 */

+#define FDCAN_TTOCN_SWP           FDCAN_TTOCN_SWP_Msk                          /*!<Stop Watch Polarity                       */

+#define FDCAN_TTOCN_SWS_Pos       (3U)

+#define FDCAN_TTOCN_SWS_Msk       (0x3UL << FDCAN_TTOCN_SWS_Pos)               /*!< 0x00000018 */

+#define FDCAN_TTOCN_SWS           FDCAN_TTOCN_SWS_Msk                          /*!<Stop Watch Source                         */

+#define FDCAN_TTOCN_RTIE_Pos      (5U)

+#define FDCAN_TTOCN_RTIE_Msk      (0x1UL << FDCAN_TTOCN_RTIE_Pos)              /*!< 0x00000020 */

+#define FDCAN_TTOCN_RTIE          FDCAN_TTOCN_RTIE_Msk                         /*!<Register Time Mark Interrupt Pulse Enable */

+#define FDCAN_TTOCN_TMC_Pos       (6U)

+#define FDCAN_TTOCN_TMC_Msk       (0x3UL << FDCAN_TTOCN_TMC_Pos)               /*!< 0x000000C0 */

+#define FDCAN_TTOCN_TMC           FDCAN_TTOCN_TMC_Msk                          /*!<Register Time Mark Compare                */

+#define FDCAN_TTOCN_TTIE_Pos      (8U)

+#define FDCAN_TTOCN_TTIE_Msk      (0x1UL << FDCAN_TTOCN_TTIE_Pos)              /*!< 0x00000100 */

+#define FDCAN_TTOCN_TTIE          FDCAN_TTOCN_TTIE_Msk                         /*!<Trigger Time Mark Interrupt Pulse Enable  */

+#define FDCAN_TTOCN_GCS_Pos       (9U)

+#define FDCAN_TTOCN_GCS_Msk       (0x1UL << FDCAN_TTOCN_GCS_Pos)               /*!< 0x00000200 */

+#define FDCAN_TTOCN_GCS           FDCAN_TTOCN_GCS_Msk                          /*!<Gap Control Select                        */

+#define FDCAN_TTOCN_FGP_Pos       (10U)

+#define FDCAN_TTOCN_FGP_Msk       (0x1UL << FDCAN_TTOCN_FGP_Pos)               /*!< 0x00000400 */

+#define FDCAN_TTOCN_FGP           FDCAN_TTOCN_FGP_Msk                          /*!<Finish Gap                                */

+#define FDCAN_TTOCN_TMG_Pos       (11U)

+#define FDCAN_TTOCN_TMG_Msk       (0x1UL << FDCAN_TTOCN_TMG_Pos)               /*!< 0x00000800 */

+#define FDCAN_TTOCN_TMG           FDCAN_TTOCN_TMG_Msk                          /*!<Time Mark Gap                             */

+#define FDCAN_TTOCN_NIG_Pos       (12U)

+#define FDCAN_TTOCN_NIG_Msk       (0x1UL << FDCAN_TTOCN_NIG_Pos)               /*!< 0x00001000 */

+#define FDCAN_TTOCN_NIG           FDCAN_TTOCN_NIG_Msk                          /*!<Next is Gap                               */

+#define FDCAN_TTOCN_ESCN_Pos      (13U)

+#define FDCAN_TTOCN_ESCN_Msk      (0x1UL << FDCAN_TTOCN_ESCN_Pos)              /*!< 0x00002000 */

+#define FDCAN_TTOCN_ESCN          FDCAN_TTOCN_ESCN_Msk                         /*!<External Synchronization Control          */

+#define FDCAN_TTOCN_LCKC_Pos      (15U)

+#define FDCAN_TTOCN_LCKC_Msk      (0x1UL << FDCAN_TTOCN_LCKC_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTOCN_LCKC          FDCAN_TTOCN_LCKC_Msk                         /*!<TT Operation Control Register Locked      */

+

+/*****************  Bit definition for FDCAN_TTGTP register  ********************/

+#define FDCAN_TTGTP_TP_Pos        (0U)

+#define FDCAN_TTGTP_TP_Msk        (0xFFFFUL << FDCAN_TTGTP_TP_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTGTP_TP            FDCAN_TTGTP_TP_Msk                           /*!<Time Preset                               */

+#define FDCAN_TTGTP_CTP_Pos       (16U)

+#define FDCAN_TTGTP_CTP_Msk       (0xFFFFUL << FDCAN_TTGTP_CTP_Pos)            /*!< 0xFFFF0000 */

+#define FDCAN_TTGTP_CTP           FDCAN_TTGTP_CTP_Msk                          /*!<Cycle Time Target Phase                   */

+

+/*****************  Bit definition for FDCAN_TTTMK register  ********************/

+#define FDCAN_TTTMK_TM_Pos        (0U)

+#define FDCAN_TTTMK_TM_Msk        (0xFFFFUL << FDCAN_TTTMK_TM_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTTMK_TM            FDCAN_TTTMK_TM_Msk                           /*!<Time Mark                                 */

+#define FDCAN_TTTMK_TICC_Pos      (16U)

+#define FDCAN_TTTMK_TICC_Msk      (0x7FUL << FDCAN_TTTMK_TICC_Pos)             /*!< 0x007F0000 */

+#define FDCAN_TTTMK_TICC          FDCAN_TTTMK_TICC_Msk                         /*!<Time Mark Cycle Code                      */

+#define FDCAN_TTTMK_LCKM_Pos      (31U)

+#define FDCAN_TTTMK_LCKM_Msk      (0x1UL << FDCAN_TTTMK_LCKM_Pos)              /*!< 0x80000000 */

+#define FDCAN_TTTMK_LCKM          FDCAN_TTTMK_LCKM_Msk                         /*!<TT Time Mark Register Locked              */

+

+/*****************  Bit definition for FDCAN_TTIR register  ********************/

+#define FDCAN_TTIR_SBC_Pos        (0U)

+#define FDCAN_TTIR_SBC_Msk        (0x1UL << FDCAN_TTIR_SBC_Pos)                /*!< 0x00000001 */

+#define FDCAN_TTIR_SBC            FDCAN_TTIR_SBC_Msk                           /*!<Start of Basic Cycle                      */

+#define FDCAN_TTIR_SMC_Pos        (1U)

+#define FDCAN_TTIR_SMC_Msk        (0x1UL << FDCAN_TTIR_SMC_Pos)                /*!< 0x00000002 */

+#define FDCAN_TTIR_SMC            FDCAN_TTIR_SMC_Msk                           /*!<Start of Matrix Cycle                     */

+#define FDCAN_TTIR_CSM_Pos        (2U)

+#define FDCAN_TTIR_CSM_Msk        (0x1UL << FDCAN_TTIR_CSM_Pos)                /*!< 0x00000004 */

+#define FDCAN_TTIR_CSM            FDCAN_TTIR_CSM_Msk                           /*!<Change of Synchronization Mode            */

+#define FDCAN_TTIR_SOG_Pos        (3U)

+#define FDCAN_TTIR_SOG_Msk        (0x1UL << FDCAN_TTIR_SOG_Pos)                /*!< 0x00000008 */

+#define FDCAN_TTIR_SOG            FDCAN_TTIR_SOG_Msk                           /*!<Start of Gap                              */

+#define FDCAN_TTIR_RTMI_Pos       (4U)

+#define FDCAN_TTIR_RTMI_Msk       (0x1UL << FDCAN_TTIR_RTMI_Pos)               /*!< 0x00000010 */

+#define FDCAN_TTIR_RTMI           FDCAN_TTIR_RTMI_Msk                          /*!<Register Time Mark Interrupt              */

+#define FDCAN_TTIR_TTMI_Pos       (5U)

+#define FDCAN_TTIR_TTMI_Msk       (0x1UL << FDCAN_TTIR_TTMI_Pos)               /*!< 0x00000020 */

+#define FDCAN_TTIR_TTMI           FDCAN_TTIR_TTMI_Msk                          /*!<Trigger Time Mark Event Internal          */

+#define FDCAN_TTIR_SWE_Pos        (6U)

+#define FDCAN_TTIR_SWE_Msk        (0x1UL << FDCAN_TTIR_SWE_Pos)                /*!< 0x00000040 */

+#define FDCAN_TTIR_SWE            FDCAN_TTIR_SWE_Msk                           /*!<Stop Watch Event                          */

+#define FDCAN_TTIR_GTW_Pos        (7U)

+#define FDCAN_TTIR_GTW_Msk        (0x1UL << FDCAN_TTIR_GTW_Pos)                /*!< 0x00000080 */

+#define FDCAN_TTIR_GTW            FDCAN_TTIR_GTW_Msk                           /*!<Global Time Wrap                          */

+#define FDCAN_TTIR_GTD_Pos        (8U)

+#define FDCAN_TTIR_GTD_Msk        (0x1UL << FDCAN_TTIR_GTD_Pos)                /*!< 0x00000100 */

+#define FDCAN_TTIR_GTD            FDCAN_TTIR_GTD_Msk                           /*!<Global Time Discontinuity                 */

+#define FDCAN_TTIR_GTE_Pos        (9U)

+#define FDCAN_TTIR_GTE_Msk        (0x1UL << FDCAN_TTIR_GTE_Pos)                /*!< 0x00000200 */

+#define FDCAN_TTIR_GTE            FDCAN_TTIR_GTE_Msk                           /*!<Global Time Error                         */

+#define FDCAN_TTIR_TXU_Pos        (10U)

+#define FDCAN_TTIR_TXU_Msk        (0x1UL << FDCAN_TTIR_TXU_Pos)                /*!< 0x00000400 */

+#define FDCAN_TTIR_TXU            FDCAN_TTIR_TXU_Msk                           /*!<Tx Count Underflow                        */

+#define FDCAN_TTIR_TXO_Pos        (11U)

+#define FDCAN_TTIR_TXO_Msk        (0x1UL << FDCAN_TTIR_TXO_Pos)                /*!< 0x00000800 */

+#define FDCAN_TTIR_TXO            FDCAN_TTIR_TXO_Msk                           /*!<Tx Count Overflow                         */

+#define FDCAN_TTIR_SE1_Pos        (12U)

+#define FDCAN_TTIR_SE1_Msk        (0x1UL << FDCAN_TTIR_SE1_Pos)                /*!< 0x00001000 */

+#define FDCAN_TTIR_SE1            FDCAN_TTIR_SE1_Msk                           /*!<Scheduling Error 1                        */

+#define FDCAN_TTIR_SE2_Pos        (13U)

+#define FDCAN_TTIR_SE2_Msk        (0x1UL << FDCAN_TTIR_SE2_Pos)                /*!< 0x00002000 */

+#define FDCAN_TTIR_SE2            FDCAN_TTIR_SE2_Msk                           /*!<Scheduling Error 2                        */

+#define FDCAN_TTIR_ELC_Pos        (14U)

+#define FDCAN_TTIR_ELC_Msk        (0x1UL << FDCAN_TTIR_ELC_Pos)                /*!< 0x00004000 */

+#define FDCAN_TTIR_ELC            FDCAN_TTIR_ELC_Msk                           /*!<Error Level Changed                       */

+#define FDCAN_TTIR_IWT_Pos        (15U)

+#define FDCAN_TTIR_IWT_Msk        (0x1UL << FDCAN_TTIR_IWT_Pos)                /*!< 0x00008000 */

+#define FDCAN_TTIR_IWT            FDCAN_TTIR_IWT_Msk                           /*!<Initialization Watch Trigger              */

+#define FDCAN_TTIR_WT_Pos         (16U)

+#define FDCAN_TTIR_WT_Msk         (0x1UL << FDCAN_TTIR_WT_Pos)                 /*!< 0x00010000 */

+#define FDCAN_TTIR_WT             FDCAN_TTIR_WT_Msk                            /*!<Watch Trigger                             */

+#define FDCAN_TTIR_AW_Pos         (17U)

+#define FDCAN_TTIR_AW_Msk         (0x1UL << FDCAN_TTIR_AW_Pos)                 /*!< 0x00020000 */

+#define FDCAN_TTIR_AW             FDCAN_TTIR_AW_Msk                            /*!<Application Watchdog                      */

+#define FDCAN_TTIR_CER_Pos        (18U)

+#define FDCAN_TTIR_CER_Msk        (0x1UL << FDCAN_TTIR_CER_Pos)                /*!< 0x00040000 */

+#define FDCAN_TTIR_CER            FDCAN_TTIR_CER_Msk                           /*!<Configuration Error                       */

+

+/*****************  Bit definition for FDCAN_TTIE register  ********************/

+#define FDCAN_TTIE_SBCE_Pos       (0U)

+#define FDCAN_TTIE_SBCE_Msk       (0x1UL << FDCAN_TTIE_SBCE_Pos)               /*!< 0x00000001 */

+#define FDCAN_TTIE_SBCE           FDCAN_TTIE_SBCE_Msk                          /*!<Start of Basic Cycle Interrupt Enable             */

+#define FDCAN_TTIE_SMCE_Pos       (1U)

+#define FDCAN_TTIE_SMCE_Msk       (0x1UL << FDCAN_TTIE_SMCE_Pos)               /*!< 0x00000002 */

+#define FDCAN_TTIE_SMCE           FDCAN_TTIE_SMCE_Msk                          /*!<Start of Matrix Cycle Interrupt Enable            */

+#define FDCAN_TTIE_CSME_Pos       (2U)

+#define FDCAN_TTIE_CSME_Msk       (0x1UL << FDCAN_TTIE_CSME_Pos)               /*!< 0x00000004 */

+#define FDCAN_TTIE_CSME           FDCAN_TTIE_CSME_Msk                          /*!<Change of Synchronization Mode Interrupt Enable   */

+#define FDCAN_TTIE_SOGE_Pos       (3U)

+#define FDCAN_TTIE_SOGE_Msk       (0x1UL << FDCAN_TTIE_SOGE_Pos)               /*!< 0x00000008 */

+#define FDCAN_TTIE_SOGE           FDCAN_TTIE_SOGE_Msk                          /*!<Start of Gap Interrupt Enable                     */

+#define FDCAN_TTIE_RTMIE_Pos      (4U)

+#define FDCAN_TTIE_RTMIE_Msk      (0x1UL << FDCAN_TTIE_RTMIE_Pos)              /*!< 0x00000010 */

+#define FDCAN_TTIE_RTMIE          FDCAN_TTIE_RTMIE_Msk                         /*!<Register Time Mark Interrupt Interrupt Enable     */

+#define FDCAN_TTIE_TTMIE_Pos      (5U)

+#define FDCAN_TTIE_TTMIE_Msk      (0x1UL << FDCAN_TTIE_TTMIE_Pos)              /*!< 0x00000020 */

+#define FDCAN_TTIE_TTMIE          FDCAN_TTIE_TTMIE_Msk                         /*!<Trigger Time Mark Event Internal Interrupt Enable */

+#define FDCAN_TTIE_SWEE_Pos       (6U)

+#define FDCAN_TTIE_SWEE_Msk       (0x1UL << FDCAN_TTIE_SWEE_Pos)               /*!< 0x00000040 */

+#define FDCAN_TTIE_SWEE           FDCAN_TTIE_SWEE_Msk                          /*!<Stop Watch Event Interrupt Enable                 */

+#define FDCAN_TTIE_GTWE_Pos       (7U)

+#define FDCAN_TTIE_GTWE_Msk       (0x1UL << FDCAN_TTIE_GTWE_Pos)               /*!< 0x00000080 */

+#define FDCAN_TTIE_GTWE           FDCAN_TTIE_GTWE_Msk                          /*!<Global Time Wrap Interrupt Enable                 */

+#define FDCAN_TTIE_GTDE_Pos       (8U)

+#define FDCAN_TTIE_GTDE_Msk       (0x1UL << FDCAN_TTIE_GTDE_Pos)               /*!< 0x00000100 */

+#define FDCAN_TTIE_GTDE           FDCAN_TTIE_GTDE_Msk                          /*!<Global Time Discontinuity Interrupt Enable        */

+#define FDCAN_TTIE_GTEE_Pos       (9U)

+#define FDCAN_TTIE_GTEE_Msk       (0x1UL << FDCAN_TTIE_GTEE_Pos)               /*!< 0x00000200 */

+#define FDCAN_TTIE_GTEE           FDCAN_TTIE_GTEE_Msk                          /*!<Global Time Error Interrupt Enable                */

+#define FDCAN_TTIE_TXUE_Pos       (10U)

+#define FDCAN_TTIE_TXUE_Msk       (0x1UL << FDCAN_TTIE_TXUE_Pos)               /*!< 0x00000400 */

+#define FDCAN_TTIE_TXUE           FDCAN_TTIE_TXUE_Msk                          /*!<Tx Count Underflow Interrupt Enable               */

+#define FDCAN_TTIE_TXOE_Pos       (11U)

+#define FDCAN_TTIE_TXOE_Msk       (0x1UL << FDCAN_TTIE_TXOE_Pos)               /*!< 0x00000800 */

+#define FDCAN_TTIE_TXOE           FDCAN_TTIE_TXOE_Msk                          /*!<Tx Count Overflow Interrupt Enable                */

+#define FDCAN_TTIE_SE1E_Pos       (12U)

+#define FDCAN_TTIE_SE1E_Msk       (0x1UL << FDCAN_TTIE_SE1E_Pos)               /*!< 0x00001000 */

+#define FDCAN_TTIE_SE1E           FDCAN_TTIE_SE1E_Msk                          /*!<Scheduling Error 1 Interrupt Enable               */

+#define FDCAN_TTIE_SE2E_Pos       (13U)

+#define FDCAN_TTIE_SE2E_Msk       (0x1UL << FDCAN_TTIE_SE2E_Pos)               /*!< 0x00002000 */

+#define FDCAN_TTIE_SE2E           FDCAN_TTIE_SE2E_Msk                          /*!<Scheduling Error 2 Interrupt Enable               */

+#define FDCAN_TTIE_ELCE_Pos       (14U)

+#define FDCAN_TTIE_ELCE_Msk       (0x1UL << FDCAN_TTIE_ELCE_Pos)               /*!< 0x00004000 */

+#define FDCAN_TTIE_ELCE           FDCAN_TTIE_ELCE_Msk                          /*!<Error Level Changed Interrupt Enable              */

+#define FDCAN_TTIE_IWTE_Pos       (15U)

+#define FDCAN_TTIE_IWTE_Msk       (0x1UL << FDCAN_TTIE_IWTE_Pos)               /*!< 0x00008000 */

+#define FDCAN_TTIE_IWTE           FDCAN_TTIE_IWTE_Msk                          /*!<Initialization Watch Trigger Interrupt Enable     */

+#define FDCAN_TTIE_WTE_Pos        (16U)

+#define FDCAN_TTIE_WTE_Msk        (0x1UL << FDCAN_TTIE_WTE_Pos)                /*!< 0x00010000 */

+#define FDCAN_TTIE_WTE            FDCAN_TTIE_WTE_Msk                           /*!<Watch Trigger Interrupt Enable                    */

+#define FDCAN_TTIE_AWE_Pos        (17U)

+#define FDCAN_TTIE_AWE_Msk        (0x1UL << FDCAN_TTIE_AWE_Pos)                /*!< 0x00020000 */

+#define FDCAN_TTIE_AWE            FDCAN_TTIE_AWE_Msk                           /*!<Application Watchdog Interrupt Enable             */

+#define FDCAN_TTIE_CERE_Pos       (18U)

+#define FDCAN_TTIE_CERE_Msk       (0x1UL << FDCAN_TTIE_CERE_Pos)               /*!< 0x00040000 */

+#define FDCAN_TTIE_CERE           FDCAN_TTIE_CERE_Msk                          /*!<Configuration Error Interrupt Enable              */

+

+/*****************  Bit definition for FDCAN_TTILS register  ********************/

+#define FDCAN_TTILS_SBCS_Pos      (0U)

+#define FDCAN_TTILS_SBCS_Msk      (0x1UL << FDCAN_TTILS_SBCS_Pos)              /*!< 0x00000001 */

+#define FDCAN_TTILS_SBCS          FDCAN_TTILS_SBCS_Msk                         /*!<Start of Basic Cycle Interrupt Line               */

+#define FDCAN_TTILS_SMCS_Pos      (1U)

+#define FDCAN_TTILS_SMCS_Msk      (0x1UL << FDCAN_TTILS_SMCS_Pos)              /*!< 0x00000002 */

+#define FDCAN_TTILS_SMCS          FDCAN_TTILS_SMCS_Msk                         /*!<Start of Matrix Cycle Interrupt Line              */

+#define FDCAN_TTILS_CSMS_Pos      (2U)

+#define FDCAN_TTILS_CSMS_Msk      (0x1UL << FDCAN_TTILS_CSMS_Pos)              /*!< 0x00000004 */

+#define FDCAN_TTILS_CSMS          FDCAN_TTILS_CSMS_Msk                         /*!<Change of Synchronization Mode Interrupt Line     */

+#define FDCAN_TTILS_SOGS_Pos      (3U)

+#define FDCAN_TTILS_SOGS_Msk      (0x1UL << FDCAN_TTILS_SOGS_Pos)              /*!< 0x00000008 */

+#define FDCAN_TTILS_SOGS          FDCAN_TTILS_SOGS_Msk                         /*!<Start of Gap Interrupt Line                       */

+#define FDCAN_TTILS_RTMIS_Pos     (4U)

+#define FDCAN_TTILS_RTMIS_Msk     (0x1UL << FDCAN_TTILS_RTMIS_Pos)             /*!< 0x00000010 */

+#define FDCAN_TTILS_RTMIS         FDCAN_TTILS_RTMIS_Msk                        /*!<Register Time Mark Interrupt Interrupt Line       */

+#define FDCAN_TTILS_TTMIS_Pos     (5U)

+#define FDCAN_TTILS_TTMIS_Msk     (0x1UL << FDCAN_TTILS_TTMIS_Pos)             /*!< 0x00000020 */

+#define FDCAN_TTILS_TTMIS         FDCAN_TTILS_TTMIS_Msk                        /*!<Trigger Time Mark Event Internal Interrupt Line   */

+#define FDCAN_TTILS_SWES_Pos      (6U)

+#define FDCAN_TTILS_SWES_Msk      (0x1UL << FDCAN_TTILS_SWES_Pos)              /*!< 0x00000040 */

+#define FDCAN_TTILS_SWES          FDCAN_TTILS_SWES_Msk                         /*!<Stop Watch Event Interrupt Line                   */

+#define FDCAN_TTILS_GTWS_Pos      (7U)

+#define FDCAN_TTILS_GTWS_Msk      (0x1UL << FDCAN_TTILS_GTWS_Pos)              /*!< 0x00000080 */

+#define FDCAN_TTILS_GTWS          FDCAN_TTILS_GTWS_Msk                         /*!<Global Time Wrap Interrupt Line                   */

+#define FDCAN_TTILS_GTDS_Pos      (8U)

+#define FDCAN_TTILS_GTDS_Msk      (0x1UL << FDCAN_TTILS_GTDS_Pos)              /*!< 0x00000100 */

+#define FDCAN_TTILS_GTDS          FDCAN_TTILS_GTDS_Msk                         /*!<Global Time Discontinuity Interrupt Line          */

+#define FDCAN_TTILS_GTES_Pos      (9U)

+#define FDCAN_TTILS_GTES_Msk      (0x1UL << FDCAN_TTILS_GTES_Pos)              /*!< 0x00000200 */

+#define FDCAN_TTILS_GTES          FDCAN_TTILS_GTES_Msk                         /*!<Global Time Error Interrupt Line                  */

+#define FDCAN_TTILS_TXUS_Pos      (10U)

+#define FDCAN_TTILS_TXUS_Msk      (0x1UL << FDCAN_TTILS_TXUS_Pos)              /*!< 0x00000400 */

+#define FDCAN_TTILS_TXUS          FDCAN_TTILS_TXUS_Msk                         /*!<Tx Count Underflow Interrupt Line                 */

+#define FDCAN_TTILS_TXOS_Pos      (11U)

+#define FDCAN_TTILS_TXOS_Msk      (0x1UL << FDCAN_TTILS_TXOS_Pos)              /*!< 0x00000800 */

+#define FDCAN_TTILS_TXOS          FDCAN_TTILS_TXOS_Msk                         /*!<Tx Count Overflow Interrupt Line                  */

+#define FDCAN_TTILS_SE1S_Pos      (12U)

+#define FDCAN_TTILS_SE1S_Msk      (0x1UL << FDCAN_TTILS_SE1S_Pos)              /*!< 0x00001000 */

+#define FDCAN_TTILS_SE1S          FDCAN_TTILS_SE1S_Msk                         /*!<Scheduling Error 1 Interrupt Line                 */

+#define FDCAN_TTILS_SE2S_Pos      (13U)

+#define FDCAN_TTILS_SE2S_Msk      (0x1UL << FDCAN_TTILS_SE2S_Pos)              /*!< 0x00002000 */

+#define FDCAN_TTILS_SE2S          FDCAN_TTILS_SE2S_Msk                         /*!<Scheduling Error 2 Interrupt Line                 */

+#define FDCAN_TTILS_ELCS_Pos      (14U)

+#define FDCAN_TTILS_ELCS_Msk      (0x1UL << FDCAN_TTILS_ELCS_Pos)              /*!< 0x00004000 */

+#define FDCAN_TTILS_ELCS          FDCAN_TTILS_ELCS_Msk                         /*!<Error Level Changed Interrupt Line                */

+#define FDCAN_TTILS_IWTS_Pos      (15U)

+#define FDCAN_TTILS_IWTS_Msk      (0x1UL << FDCAN_TTILS_IWTS_Pos)              /*!< 0x00008000 */

+#define FDCAN_TTILS_IWTS          FDCAN_TTILS_IWTS_Msk                         /*!<Initialization Watch Trigger Interrupt Line       */

+#define FDCAN_TTILS_WTS_Pos       (16U)

+#define FDCAN_TTILS_WTS_Msk       (0x1UL << FDCAN_TTILS_WTS_Pos)               /*!< 0x00010000 */

+#define FDCAN_TTILS_WTS           FDCAN_TTILS_WTS_Msk                          /*!<Watch Trigger Interrupt Line                      */

+#define FDCAN_TTILS_AWS_Pos       (17U)

+#define FDCAN_TTILS_AWS_Msk       (0x1UL << FDCAN_TTILS_AWS_Pos)               /*!< 0x00020000 */

+#define FDCAN_TTILS_AWS           FDCAN_TTILS_AWS_Msk                          /*!<Application Watchdog Interrupt Line               */

+#define FDCAN_TTILS_CERS_Pos      (18U)

+#define FDCAN_TTILS_CERS_Msk      (0x1UL << FDCAN_TTILS_CERS_Pos)              /*!< 0x00040000 */

+#define FDCAN_TTILS_CERS          FDCAN_TTILS_CERS_Msk                         /*!<Configuration Error Interrupt Line                */

+

+/*****************  Bit definition for FDCAN_TTOST register  ********************/

+#define FDCAN_TTOST_EL_Pos        (0U)

+#define FDCAN_TTOST_EL_Msk        (0x3UL << FDCAN_TTOST_EL_Pos)                /*!< 0x00000003 */

+#define FDCAN_TTOST_EL            FDCAN_TTOST_EL_Msk                           /*!<Error Level                              */

+#define FDCAN_TTOST_MS_Pos        (2U)

+#define FDCAN_TTOST_MS_Msk        (0x3UL << FDCAN_TTOST_MS_Pos)                /*!< 0x0000000C */

+#define FDCAN_TTOST_MS            FDCAN_TTOST_MS_Msk                           /*!<Master State                             */

+#define FDCAN_TTOST_SYS_Pos       (4U)

+#define FDCAN_TTOST_SYS_Msk       (0x3UL << FDCAN_TTOST_SYS_Pos)               /*!< 0x00000030 */

+#define FDCAN_TTOST_SYS           FDCAN_TTOST_SYS_Msk                          /*!<Synchronization State                    */

+#define FDCAN_TTOST_QGTP_Pos      (6U)

+#define FDCAN_TTOST_QGTP_Msk      (0x1UL << FDCAN_TTOST_QGTP_Pos)              /*!< 0x00000040 */

+#define FDCAN_TTOST_QGTP          FDCAN_TTOST_QGTP_Msk                         /*!<Quality of Global Time Phase             */

+#define FDCAN_TTOST_QCS_Pos       (7U)

+#define FDCAN_TTOST_QCS_Msk       (0x1UL << FDCAN_TTOST_QCS_Pos)               /*!< 0x00000080 */

+#define FDCAN_TTOST_QCS           FDCAN_TTOST_QCS_Msk                          /*!<Quality of Clock Speed                   */

+#define FDCAN_TTOST_RTO_Pos       (8U)

+#define FDCAN_TTOST_RTO_Msk       (0xFFUL << FDCAN_TTOST_RTO_Pos)              /*!< 0x0000FF00 */

+#define FDCAN_TTOST_RTO           FDCAN_TTOST_RTO_Msk                          /*!<Reference Trigger Offset                 */

+#define FDCAN_TTOST_WGTD_Pos      (22U)

+#define FDCAN_TTOST_WGTD_Msk      (0x1UL << FDCAN_TTOST_WGTD_Pos)              /*!< 0x00400000 */

+#define FDCAN_TTOST_WGTD          FDCAN_TTOST_WGTD_Msk                         /*!<Wait for Global Time Discontinuity       */

+#define FDCAN_TTOST_GFI_Pos       (23U)

+#define FDCAN_TTOST_GFI_Msk       (0x1UL << FDCAN_TTOST_GFI_Pos)               /*!< 0x00800000 */

+#define FDCAN_TTOST_GFI           FDCAN_TTOST_GFI_Msk                          /*!<Gap Finished Indicator                   */

+#define FDCAN_TTOST_TMP_Pos       (24U)

+#define FDCAN_TTOST_TMP_Msk       (0x7UL << FDCAN_TTOST_TMP_Pos)               /*!< 0x07000000 */

+#define FDCAN_TTOST_TMP           FDCAN_TTOST_TMP_Msk                          /*!<Time Master Priority                     */

+#define FDCAN_TTOST_GSI_Pos       (27U)

+#define FDCAN_TTOST_GSI_Msk       (0x1UL << FDCAN_TTOST_GSI_Pos)               /*!< 0x08000000 */

+#define FDCAN_TTOST_GSI           FDCAN_TTOST_GSI_Msk                          /*!<Gap Started Indicator                    */

+#define FDCAN_TTOST_WFE_Pos       (28U)

+#define FDCAN_TTOST_WFE_Msk       (0x1UL << FDCAN_TTOST_WFE_Pos)               /*!< 0x10000000 */

+#define FDCAN_TTOST_WFE           FDCAN_TTOST_WFE_Msk                          /*!<Wait for Event                           */

+#define FDCAN_TTOST_AWE_Pos       (29U)

+#define FDCAN_TTOST_AWE_Msk       (0x1UL << FDCAN_TTOST_AWE_Pos)               /*!< 0x20000000 */

+#define FDCAN_TTOST_AWE           FDCAN_TTOST_AWE_Msk                          /*!<Application Watchdog Event               */

+#define FDCAN_TTOST_WECS_Pos      (30U)

+#define FDCAN_TTOST_WECS_Msk      (0x1UL << FDCAN_TTOST_WECS_Pos)              /*!< 0x40000000 */

+#define FDCAN_TTOST_WECS          FDCAN_TTOST_WECS_Msk                         /*!<Wait for External Clock Synchronization  */

+#define FDCAN_TTOST_SPL_Pos       (31U)

+#define FDCAN_TTOST_SPL_Msk       (0x1UL << FDCAN_TTOST_SPL_Pos)               /*!< 0x80000000 */

+#define FDCAN_TTOST_SPL           FDCAN_TTOST_SPL_Msk                          /*!<Schedule Phase Lock                      */

+

+/*****************  Bit definition for FDCAN_TURNA register  ********************/

+#define FDCAN_TURNA_NAV_Pos       (0U)

+#define FDCAN_TURNA_NAV_Msk       (0x3FFFFUL << FDCAN_TURNA_NAV_Pos)           /*!< 0x0003FFFF */

+#define FDCAN_TURNA_NAV           FDCAN_TURNA_NAV_Msk                          /*!<Numerator Actual Value                   */

+

+/*****************  Bit definition for FDCAN_TTLGT register  ********************/

+#define FDCAN_TTLGT_LT_Pos        (0U)

+#define FDCAN_TTLGT_LT_Msk        (0xFFFFUL << FDCAN_TTLGT_LT_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTLGT_LT            FDCAN_TTLGT_LT_Msk                           /*!<Local Time                               */

+#define FDCAN_TTLGT_GT_Pos        (16U)

+#define FDCAN_TTLGT_GT_Msk        (0xFFFFUL << FDCAN_TTLGT_GT_Pos)             /*!< 0xFFFF0000 */

+#define FDCAN_TTLGT_GT            FDCAN_TTLGT_GT_Msk                           /*!<Global Time                              */

+

+/*****************  Bit definition for FDCAN_TTCTC register  ********************/

+#define FDCAN_TTCTC_CT_Pos        (0U)

+#define FDCAN_TTCTC_CT_Msk        (0xFFFFUL << FDCAN_TTCTC_CT_Pos)             /*!< 0x0000FFFF */

+#define FDCAN_TTCTC_CT            FDCAN_TTCTC_CT_Msk                           /*!<Cycle Time                               */

+#define FDCAN_TTCTC_CC_Pos        (16U)

+#define FDCAN_TTCTC_CC_Msk        (0x3FUL << FDCAN_TTCTC_CC_Pos)               /*!< 0x003F0000 */

+#define FDCAN_TTCTC_CC            FDCAN_TTCTC_CC_Msk                           /*!<Cycle Count                              */

+

+/*****************  Bit definition for FDCAN_TTCPT register  ********************/

+#define FDCAN_TTCPT_CCV_Pos       (0U)

+#define FDCAN_TTCPT_CCV_Msk       (0x3FUL << FDCAN_TTCPT_CCV_Pos)              /*!< 0x0000003F */

+#define FDCAN_TTCPT_CCV           FDCAN_TTCPT_CCV_Msk                          /*!<Cycle Count Value                        */

+#define FDCAN_TTCPT_SWV_Pos       (16U)

+#define FDCAN_TTCPT_SWV_Msk       (0xFFFFUL << FDCAN_TTCPT_SWV_Pos)            /*!< 0xFFFF0000 */

+#define FDCAN_TTCPT_SWV           FDCAN_TTCPT_SWV_Msk                          /*!<Stop Watch Value                         */

+

+/*****************  Bit definition for FDCAN_TTCSM register  ********************/

+#define FDCAN_TTCSM_CSM_Pos       (0U)

+#define FDCAN_TTCSM_CSM_Msk       (0xFFFFUL << FDCAN_TTCSM_CSM_Pos)            /*!< 0x0000FFFF */

+#define FDCAN_TTCSM_CSM           FDCAN_TTCSM_CSM_Msk                          /*!<Cycle Sync Mark                          */

+

+/*****************  Bit definition for FDCAN_TTTS register  *********************/

+#define FDCAN_TTTS_SWTSEL_Pos     (0U)

+#define FDCAN_TTTS_SWTSEL_Msk     (0x3UL << FDCAN_TTTS_SWTSEL_Pos)             /*!< 0x00000003 */

+#define FDCAN_TTTS_SWTSEL         FDCAN_TTTS_SWTSEL_Msk                        /*!<Stop watch trigger input selection       */

+#define FDCAN_TTTS_EVTSEL_Pos     (4U)

+#define FDCAN_TTTS_EVTSEL_Msk     (0x3UL << FDCAN_TTTS_EVTSEL_Pos)             /*!< 0x00000030 */

+#define FDCAN_TTTS_EVTSEL         FDCAN_TTTS_EVTSEL_Msk                        /*!<Event trigger input selection            */

+

+/********************************************************************************/

+/*                                                                              */

+/*                      FDCANCCU (Clock Calibration unit)                       */

+/*                                                                              */

+/********************************************************************************/

+

+/*****************  Bit definition for FDCANCCU_CREL register  ******************/

+#define FDCANCCU_CREL_DAY_Pos        (0U)

+#define FDCANCCU_CREL_DAY_Msk        (0xFFUL << FDCANCCU_CREL_DAY_Pos)         /*!< 0x000000FF */

+#define FDCANCCU_CREL_DAY            FDCANCCU_CREL_DAY_Msk                     /*!<Timestamp Day                           */

+#define FDCANCCU_CREL_MON_Pos        (8U)

+#define FDCANCCU_CREL_MON_Msk        (0xFFUL << FDCANCCU_CREL_MON_Pos)         /*!< 0x0000FF00 */

+#define FDCANCCU_CREL_MON            FDCANCCU_CREL_MON_Msk                     /*!<Timestamp Month                         */

+#define FDCANCCU_CREL_YEAR_Pos       (16U)

+#define FDCANCCU_CREL_YEAR_Msk       (0xFUL << FDCANCCU_CREL_YEAR_Pos)         /*!< 0x000F0000 */

+#define FDCANCCU_CREL_YEAR           FDCANCCU_CREL_YEAR_Msk                    /*!<Timestamp Year                          */

+#define FDCANCCU_CREL_SUBSTEP_Pos    (20U)

+#define FDCANCCU_CREL_SUBSTEP_Msk    (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos)      /*!< 0x00F00000 */

+#define FDCANCCU_CREL_SUBSTEP        FDCANCCU_CREL_SUBSTEP_Msk                 /*!<Sub-step of Core release                */

+#define FDCANCCU_CREL_STEP_Pos       (24U)

+#define FDCANCCU_CREL_STEP_Msk       (0xFUL << FDCANCCU_CREL_STEP_Pos)         /*!< 0x0F000000 */

+#define FDCANCCU_CREL_STEP           FDCANCCU_CREL_STEP_Msk                    /*!<Step of Core release                    */

+#define FDCANCCU_CREL_REL_Pos        (28U)

+#define FDCANCCU_CREL_REL_Msk        (0xFUL << FDCANCCU_CREL_REL_Pos)          /*!< 0xF0000000 */

+#define FDCANCCU_CREL_REL            FDCANCCU_CREL_REL_Msk                     /*!<Core release                            */

+

+/*****************  Bit definition for FDCANCCU_CCFG register  ******************/

+#define FDCANCCU_CCFG_TQBT_Pos       (0U)

+#define FDCANCCU_CCFG_TQBT_Msk       (0x1FUL << FDCANCCU_CCFG_TQBT_Pos)        /*!< 0x0000001F */

+#define FDCANCCU_CCFG_TQBT           FDCANCCU_CCFG_TQBT_Msk                    /*!<Time Quanta per Bit Time                */

+#define FDCANCCU_CCFG_BCC_Pos        (6U)

+#define FDCANCCU_CCFG_BCC_Msk        (0x1UL << FDCANCCU_CCFG_BCC_Pos)          /*!< 0x00000040 */

+#define FDCANCCU_CCFG_BCC            FDCANCCU_CCFG_BCC_Msk                     /*!<Bypass Clock Calibration                */

+#define FDCANCCU_CCFG_CFL_Pos        (7U)

+#define FDCANCCU_CCFG_CFL_Msk        (0x1UL << FDCANCCU_CCFG_CFL_Pos)          /*!< 0x00000080 */

+#define FDCANCCU_CCFG_CFL            FDCANCCU_CCFG_CFL_Msk                     /*!<Calibration Field Length                */

+#define FDCANCCU_CCFG_OCPM_Pos       (8U)

+#define FDCANCCU_CCFG_OCPM_Msk       (0xFFUL << FDCANCCU_CCFG_OCPM_Pos)        /*!< 0x0000FF00 */

+#define FDCANCCU_CCFG_OCPM           FDCANCCU_CCFG_OCPM_Msk                    /*!<Oscillator Clock Periods Minimum        */

+#define FDCANCCU_CCFG_CDIV_Pos       (16U)

+#define FDCANCCU_CCFG_CDIV_Msk       (0xFUL << FDCANCCU_CCFG_CDIV_Pos)         /*!< 0x000F0000 */

+#define FDCANCCU_CCFG_CDIV           FDCANCCU_CCFG_CDIV_Msk                    /*!<Clock Divider                           */

+#define FDCANCCU_CCFG_SWR_Pos        (31U)

+#define FDCANCCU_CCFG_SWR_Msk        (0x1UL << FDCANCCU_CCFG_SWR_Pos)          /*!< 0x80000000 */

+#define FDCANCCU_CCFG_SWR            FDCANCCU_CCFG_SWR_Msk                     /*!<Software Reset                          */

+

+/*****************  Bit definition for FDCANCCU_CSTAT register  *****************/

+#define FDCANCCU_CSTAT_OCPC_Pos      (0U)

+#define FDCANCCU_CSTAT_OCPC_Msk      (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos)    /*!< 0x0003FFFF */

+#define FDCANCCU_CSTAT_OCPC          FDCANCCU_CSTAT_OCPC_Msk                   /*!<Oscillator Clock Period Counter        */

+#define FDCANCCU_CSTAT_TQC_Pos       (18U)

+#define FDCANCCU_CSTAT_TQC_Msk       (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos)       /*!< 0x1FFC0000 */

+#define FDCANCCU_CSTAT_TQC           FDCANCCU_CSTAT_TQC_Msk                    /*!<Time Quanta Counter                    */

+#define FDCANCCU_CSTAT_CALS_Pos      (30U)

+#define FDCANCCU_CSTAT_CALS_Msk      (0x3UL << FDCANCCU_CSTAT_CALS_Pos)        /*!< 0xC0000000 */

+#define FDCANCCU_CSTAT_CALS          FDCANCCU_CSTAT_CALS_Msk                   /*!<Calibration State                      */

+

+/******************  Bit definition for FDCANCCU_CWD register  ******************/

+#define FDCANCCU_CWD_WDC_Pos         (0U)

+#define FDCANCCU_CWD_WDC_Msk         (0xFFFFUL << FDCANCCU_CWD_WDC_Pos)        /*!< 0x0000FFFF */

+#define FDCANCCU_CWD_WDC             FDCANCCU_CWD_WDC_Msk                      /*!<Watchdog Configuration                 */

+#define FDCANCCU_CWD_WDV_Pos         (16U)

+#define FDCANCCU_CWD_WDV_Msk         (0xFFFFUL << FDCANCCU_CWD_WDV_Pos)        /*!< 0xFFFF0000 */

+#define FDCANCCU_CWD_WDV             FDCANCCU_CWD_WDV_Msk                      /*!<Watchdog Value                         */

+

+/******************  Bit definition for FDCANCCU_IR register  *******************/

+#define FDCANCCU_IR_CWE_Pos          (0U)

+#define FDCANCCU_IR_CWE_Msk          (0x1UL << FDCANCCU_IR_CWE_Pos)            /*!< 0x00000001 */

+#define FDCANCCU_IR_CWE              FDCANCCU_IR_CWE_Msk                       /*!<Calibration Watchdog Event             */

+#define FDCANCCU_IR_CSC_Pos          (1U)

+#define FDCANCCU_IR_CSC_Msk          (0x1UL << FDCANCCU_IR_CSC_Pos)            /*!< 0x00000002 */

+#define FDCANCCU_IR_CSC              FDCANCCU_IR_CSC_Msk                       /*!<Calibration State Changed              */

+

+/******************  Bit definition for FDCANCCU_IE register  *******************/

+#define FDCANCCU_IE_CWEE_Pos         (0U)

+#define FDCANCCU_IE_CWEE_Msk         (0x1UL << FDCANCCU_IE_CWEE_Pos)           /*!< 0x00000001 */

+#define FDCANCCU_IE_CWEE             FDCANCCU_IE_CWEE_Msk                      /*!<Calibration Watchdog Event Enable      */

+#define FDCANCCU_IE_CSCE_Pos         (1U)

+#define FDCANCCU_IE_CSCE_Msk         (0x1UL << FDCANCCU_IE_CSCE_Pos)           /*!< 0x00000002 */

+#define FDCANCCU_IE_CSCE             FDCANCCU_IE_CSCE_Msk                      /*!<Calibration State Changed Enable       */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          HDMI-CEC (CEC)                                    */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for CEC_CR register  *********************/

+#define CEC_CR_CECEN_Pos         (0U)

+#define CEC_CR_CECEN_Msk         (0x1UL << CEC_CR_CECEN_Pos)                   /*!< 0x00000001 */

+#define CEC_CR_CECEN             CEC_CR_CECEN_Msk                              /*!< CEC Enable                                */

+#define CEC_CR_TXSOM_Pos         (1U)

+#define CEC_CR_TXSOM_Msk         (0x1UL << CEC_CR_TXSOM_Pos)                   /*!< 0x00000002 */

+#define CEC_CR_TXSOM             CEC_CR_TXSOM_Msk                              /*!< CEC Tx Start Of Message                   */

+#define CEC_CR_TXEOM_Pos         (2U)

+#define CEC_CR_TXEOM_Msk         (0x1UL << CEC_CR_TXEOM_Pos)                   /*!< 0x00000004 */

+#define CEC_CR_TXEOM             CEC_CR_TXEOM_Msk                              /*!< CEC Tx End Of Message                     */

+

+/*******************  Bit definition for CEC_CFGR register  *******************/

+#define CEC_CFGR_SFT_Pos         (0U)

+#define CEC_CFGR_SFT_Msk         (0x7UL << CEC_CFGR_SFT_Pos)                   /*!< 0x00000007 */

+#define CEC_CFGR_SFT             CEC_CFGR_SFT_Msk                              /*!< CEC Signal Free Time                      */

+#define CEC_CFGR_RXTOL_Pos       (3U)

+#define CEC_CFGR_RXTOL_Msk       (0x1UL << CEC_CFGR_RXTOL_Pos)                 /*!< 0x00000008 */

+#define CEC_CFGR_RXTOL           CEC_CFGR_RXTOL_Msk                            /*!< CEC Tolerance                             */

+#define CEC_CFGR_BRESTP_Pos      (4U)

+#define CEC_CFGR_BRESTP_Msk      (0x1UL << CEC_CFGR_BRESTP_Pos)                /*!< 0x00000010 */

+#define CEC_CFGR_BRESTP          CEC_CFGR_BRESTP_Msk                           /*!< CEC Rx Stop                               */

+#define CEC_CFGR_BREGEN_Pos      (5U)

+#define CEC_CFGR_BREGEN_Msk      (0x1UL << CEC_CFGR_BREGEN_Pos)                /*!< 0x00000020 */

+#define CEC_CFGR_BREGEN          CEC_CFGR_BREGEN_Msk                           /*!< CEC Bit Rising Error generation           */

+#define CEC_CFGR_LBPEGEN_Pos     (6U)

+#define CEC_CFGR_LBPEGEN_Msk     (0x1UL << CEC_CFGR_LBPEGEN_Pos)               /*!< 0x00000040 */

+#define CEC_CFGR_LBPEGEN         CEC_CFGR_LBPEGEN_Msk                          /*!< CEC Long Bit Period Error generation      */

+#define CEC_CFGR_SFTOPT_Pos      (8U)

+#define CEC_CFGR_SFTOPT_Msk      (0x1UL << CEC_CFGR_SFTOPT_Pos)                /*!< 0x00000100 */

+#define CEC_CFGR_SFTOPT          CEC_CFGR_SFTOPT_Msk                           /*!< CEC Signal Free Time optional             */

+#define CEC_CFGR_BRDNOGEN_Pos    (7U)

+#define CEC_CFGR_BRDNOGEN_Msk    (0x1UL << CEC_CFGR_BRDNOGEN_Pos)              /*!< 0x00000080 */

+#define CEC_CFGR_BRDNOGEN        CEC_CFGR_BRDNOGEN_Msk                         /*!< CEC Broadcast No error generation         */

+#define CEC_CFGR_OAR_Pos         (16U)

+#define CEC_CFGR_OAR_Msk         (0x7FFFUL << CEC_CFGR_OAR_Pos)                /*!< 0x7FFF0000 */

+#define CEC_CFGR_OAR             CEC_CFGR_OAR_Msk                              /*!< CEC Own Address                           */

+#define CEC_CFGR_LSTN_Pos        (31U)

+#define CEC_CFGR_LSTN_Msk        (0x1UL << CEC_CFGR_LSTN_Pos)                  /*!< 0x80000000 */

+#define CEC_CFGR_LSTN            CEC_CFGR_LSTN_Msk                             /*!< CEC Listen mode                           */

+

+/*******************  Bit definition for CEC_TXDR register  *******************/

+#define CEC_TXDR_TXD_Pos         (0U)

+#define CEC_TXDR_TXD_Msk         (0xFFUL << CEC_TXDR_TXD_Pos)                  /*!< 0x000000FF */

+#define CEC_TXDR_TXD             CEC_TXDR_TXD_Msk                              /*!< CEC Tx Data                               */

+

+/*******************  Bit definition for CEC_RXDR register  *******************/

+#define CEC_RXDR_RXD_Pos         (0U)

+#define CEC_RXDR_RXD_Msk         (0xFFUL << CEC_RXDR_RXD_Pos)                  /*!< 0x000000FF */

+#define CEC_RXDR_RXD             CEC_RXDR_RXD_Msk                              /*!< CEC Rx Data                               */

+

+/*******************  Bit definition for CEC_ISR register  ********************/

+#define CEC_ISR_RXBR_Pos         (0U)

+#define CEC_ISR_RXBR_Msk         (0x1UL << CEC_ISR_RXBR_Pos)                   /*!< 0x00000001 */

+#define CEC_ISR_RXBR             CEC_ISR_RXBR_Msk                              /*!< CEC Rx-Byte Received                      */

+#define CEC_ISR_RXEND_Pos        (1U)

+#define CEC_ISR_RXEND_Msk        (0x1UL << CEC_ISR_RXEND_Pos)                  /*!< 0x00000002 */

+#define CEC_ISR_RXEND            CEC_ISR_RXEND_Msk                             /*!< CEC End Of Reception                      */

+#define CEC_ISR_RXOVR_Pos        (2U)

+#define CEC_ISR_RXOVR_Msk        (0x1UL << CEC_ISR_RXOVR_Pos)                  /*!< 0x00000004 */

+#define CEC_ISR_RXOVR            CEC_ISR_RXOVR_Msk                             /*!< CEC Rx-Overrun                            */

+#define CEC_ISR_BRE_Pos          (3U)

+#define CEC_ISR_BRE_Msk          (0x1UL << CEC_ISR_BRE_Pos)                    /*!< 0x00000008 */

+#define CEC_ISR_BRE              CEC_ISR_BRE_Msk                               /*!< CEC Rx Bit Rising Error                   */

+#define CEC_ISR_SBPE_Pos         (4U)

+#define CEC_ISR_SBPE_Msk         (0x1UL << CEC_ISR_SBPE_Pos)                   /*!< 0x00000010 */

+#define CEC_ISR_SBPE             CEC_ISR_SBPE_Msk                              /*!< CEC Rx Short Bit period Error             */

+#define CEC_ISR_LBPE_Pos         (5U)

+#define CEC_ISR_LBPE_Msk         (0x1UL << CEC_ISR_LBPE_Pos)                   /*!< 0x00000020 */

+#define CEC_ISR_LBPE             CEC_ISR_LBPE_Msk                              /*!< CEC Rx Long Bit period Error              */

+#define CEC_ISR_RXACKE_Pos       (6U)

+#define CEC_ISR_RXACKE_Msk       (0x1UL << CEC_ISR_RXACKE_Pos)                 /*!< 0x00000040 */

+#define CEC_ISR_RXACKE           CEC_ISR_RXACKE_Msk                            /*!< CEC Rx Missing Acknowledge                */

+#define CEC_ISR_ARBLST_Pos       (7U)

+#define CEC_ISR_ARBLST_Msk       (0x1UL << CEC_ISR_ARBLST_Pos)                 /*!< 0x00000080 */

+#define CEC_ISR_ARBLST           CEC_ISR_ARBLST_Msk                            /*!< CEC Arbitration Lost                      */

+#define CEC_ISR_TXBR_Pos         (8U)

+#define CEC_ISR_TXBR_Msk         (0x1UL << CEC_ISR_TXBR_Pos)                   /*!< 0x00000100 */

+#define CEC_ISR_TXBR             CEC_ISR_TXBR_Msk                              /*!< CEC Tx Byte Request                       */

+#define CEC_ISR_TXEND_Pos        (9U)

+#define CEC_ISR_TXEND_Msk        (0x1UL << CEC_ISR_TXEND_Pos)                  /*!< 0x00000200 */

+#define CEC_ISR_TXEND            CEC_ISR_TXEND_Msk                             /*!< CEC End of Transmission                   */

+#define CEC_ISR_TXUDR_Pos        (10U)

+#define CEC_ISR_TXUDR_Msk        (0x1UL << CEC_ISR_TXUDR_Pos)                  /*!< 0x00000400 */

+#define CEC_ISR_TXUDR            CEC_ISR_TXUDR_Msk                             /*!< CEC Tx-Buffer Underrun                    */

+#define CEC_ISR_TXERR_Pos        (11U)

+#define CEC_ISR_TXERR_Msk        (0x1UL << CEC_ISR_TXERR_Pos)                  /*!< 0x00000800 */

+#define CEC_ISR_TXERR            CEC_ISR_TXERR_Msk                             /*!< CEC Tx-Error                              */

+#define CEC_ISR_TXACKE_Pos       (12U)

+#define CEC_ISR_TXACKE_Msk       (0x1UL << CEC_ISR_TXACKE_Pos)                 /*!< 0x00001000 */

+#define CEC_ISR_TXACKE           CEC_ISR_TXACKE_Msk                            /*!< CEC Tx Missing Acknowledge                */

+

+/*******************  Bit definition for CEC_IER register  ********************/

+#define CEC_IER_RXBRIE_Pos       (0U)

+#define CEC_IER_RXBRIE_Msk       (0x1UL << CEC_IER_RXBRIE_Pos)                 /*!< 0x00000001 */

+#define CEC_IER_RXBRIE           CEC_IER_RXBRIE_Msk                            /*!< CEC Rx-Byte Received IT Enable            */

+#define CEC_IER_RXENDIE_Pos      (1U)

+#define CEC_IER_RXENDIE_Msk      (0x1UL << CEC_IER_RXENDIE_Pos)                /*!< 0x00000002 */

+#define CEC_IER_RXENDIE          CEC_IER_RXENDIE_Msk                           /*!< CEC End Of Reception IT Enable            */

+#define CEC_IER_RXOVRIE_Pos      (2U)

+#define CEC_IER_RXOVRIE_Msk      (0x1UL << CEC_IER_RXOVRIE_Pos)                /*!< 0x00000004 */

+#define CEC_IER_RXOVRIE          CEC_IER_RXOVRIE_Msk                           /*!< CEC Rx-Overrun IT Enable                  */

+#define CEC_IER_BREIE_Pos        (3U)

+#define CEC_IER_BREIE_Msk        (0x1UL << CEC_IER_BREIE_Pos)                  /*!< 0x00000008 */

+#define CEC_IER_BREIE            CEC_IER_BREIE_Msk                             /*!< CEC Rx Bit Rising Error IT Enable         */

+#define CEC_IER_SBPEIE_Pos       (4U)

+#define CEC_IER_SBPEIE_Msk       (0x1UL << CEC_IER_SBPEIE_Pos)                 /*!< 0x00000010 */

+#define CEC_IER_SBPEIE           CEC_IER_SBPEIE_Msk                            /*!< CEC Rx Short Bit period Error IT Enable   */

+#define CEC_IER_LBPEIE_Pos       (5U)

+#define CEC_IER_LBPEIE_Msk       (0x1UL << CEC_IER_LBPEIE_Pos)                 /*!< 0x00000020 */

+#define CEC_IER_LBPEIE           CEC_IER_LBPEIE_Msk                            /*!< CEC Rx Long Bit period Error IT Enable    */

+#define CEC_IER_RXACKEIE_Pos     (6U)

+#define CEC_IER_RXACKEIE_Msk     (0x1UL << CEC_IER_RXACKEIE_Pos)               /*!< 0x00000040 */

+#define CEC_IER_RXACKEIE         CEC_IER_RXACKEIE_Msk                          /*!< CEC Rx Missing Acknowledge IT Enable      */

+#define CEC_IER_ARBLSTIE_Pos     (7U)

+#define CEC_IER_ARBLSTIE_Msk     (0x1UL << CEC_IER_ARBLSTIE_Pos)               /*!< 0x00000080 */

+#define CEC_IER_ARBLSTIE         CEC_IER_ARBLSTIE_Msk                          /*!< CEC Arbitration Lost IT Enable            */

+#define CEC_IER_TXBRIE_Pos       (8U)

+#define CEC_IER_TXBRIE_Msk       (0x1UL << CEC_IER_TXBRIE_Pos)                 /*!< 0x00000100 */

+#define CEC_IER_TXBRIE           CEC_IER_TXBRIE_Msk                            /*!< CEC Tx Byte Request  IT Enable            */

+#define CEC_IER_TXENDIE_Pos      (9U)

+#define CEC_IER_TXENDIE_Msk      (0x1UL << CEC_IER_TXENDIE_Pos)                /*!< 0x00000200 */

+#define CEC_IER_TXENDIE          CEC_IER_TXENDIE_Msk                           /*!< CEC End of Transmission IT Enable         */

+#define CEC_IER_TXUDRIE_Pos      (10U)

+#define CEC_IER_TXUDRIE_Msk      (0x1UL << CEC_IER_TXUDRIE_Pos)                /*!< 0x00000400 */

+#define CEC_IER_TXUDRIE          CEC_IER_TXUDRIE_Msk                           /*!< CEC Tx-Buffer Underrun IT Enable          */

+#define CEC_IER_TXERRIE_Pos      (11U)

+#define CEC_IER_TXERRIE_Msk      (0x1UL << CEC_IER_TXERRIE_Pos)                /*!< 0x00000800 */

+#define CEC_IER_TXERRIE          CEC_IER_TXERRIE_Msk                           /*!< CEC Tx-Error IT Enable                    */

+#define CEC_IER_TXACKEIE_Pos     (12U)

+#define CEC_IER_TXACKEIE_Msk     (0x1UL << CEC_IER_TXACKEIE_Pos)               /*!< 0x00001000 */

+#define CEC_IER_TXACKEIE         CEC_IER_TXACKEIE_Msk                          /*!< CEC Tx Missing Acknowledge IT Enable      */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          CRC calculation unit                              */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for CRC_DR register  *********************/

+#define CRC_DR_DR_Pos            (0U)

+#define CRC_DR_DR_Msk            (0xFFFFFFFFUL << CRC_DR_DR_Pos)               /*!< 0xFFFFFFFF */

+#define CRC_DR_DR                CRC_DR_DR_Msk                                 /*!< Data register bits */

+

+/*******************  Bit definition for CRC_IDR register  ********************/

+#define CRC_IDR_IDR_Pos          (0U)

+#define CRC_IDR_IDR_Msk          (0xFFFFFFFFUL << CRC_IDR_IDR_Pos)             /*!< 0xFFFFFFFF */

+#define CRC_IDR_IDR              CRC_IDR_IDR_Msk                               /*!< General-purpose 32-bit data register bits */

+

+/********************  Bit definition for CRC_CR register  ********************/

+#define CRC_CR_RESET_Pos         (0U)

+#define CRC_CR_RESET_Msk         (0x1UL << CRC_CR_RESET_Pos)                   /*!< 0x00000001 */

+#define CRC_CR_RESET             CRC_CR_RESET_Msk                              /*!< RESET the CRC computation unit bit */

+#define CRC_CR_POLYSIZE_Pos      (3U)

+#define CRC_CR_POLYSIZE_Msk      (0x3UL << CRC_CR_POLYSIZE_Pos)                /*!< 0x00000018 */

+#define CRC_CR_POLYSIZE          CRC_CR_POLYSIZE_Msk                           /*!< Polynomial size bits */

+#define CRC_CR_POLYSIZE_0        (0x1UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000008 */

+#define CRC_CR_POLYSIZE_1        (0x2UL << CRC_CR_POLYSIZE_Pos)                 /*!< 0x00000010 */

+#define CRC_CR_REV_IN_Pos        (5U)

+#define CRC_CR_REV_IN_Msk        (0x3UL << CRC_CR_REV_IN_Pos)                  /*!< 0x00000060 */

+#define CRC_CR_REV_IN            CRC_CR_REV_IN_Msk                             /*!< REV_IN Reverse Input Data bits */

+#define CRC_CR_REV_IN_0          (0x1UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000020 */

+#define CRC_CR_REV_IN_1          (0x2UL << CRC_CR_REV_IN_Pos)                   /*!< 0x00000040 */

+#define CRC_CR_REV_OUT_Pos       (7U)

+#define CRC_CR_REV_OUT_Msk       (0x1UL << CRC_CR_REV_OUT_Pos)                 /*!< 0x00000080 */

+#define CRC_CR_REV_OUT           CRC_CR_REV_OUT_Msk                            /*!< REV_OUT Reverse Output Data bits */

+

+/*******************  Bit definition for CRC_INIT register  *******************/

+#define CRC_INIT_INIT_Pos        (0U)

+#define CRC_INIT_INIT_Msk        (0xFFFFFFFFUL << CRC_INIT_INIT_Pos)           /*!< 0xFFFFFFFF */

+#define CRC_INIT_INIT            CRC_INIT_INIT_Msk                             /*!< Initial CRC value bits */

+

+/*******************  Bit definition for CRC_POL register  ********************/

+#define CRC_POL_POL_Pos          (0U)

+#define CRC_POL_POL_Msk          (0xFFFFFFFFUL << CRC_POL_POL_Pos)             /*!< 0xFFFFFFFF */

+#define CRC_POL_POL              CRC_POL_POL_Msk                               /*!< Coefficients of the polynomial */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          CRS Clock Recovery System                         */

+/******************************************************************************/

+

+/*******************  Bit definition for CRS_CR register  *********************/

+#define CRS_CR_SYNCOKIE_Pos       (0U)

+#define CRS_CR_SYNCOKIE_Msk       (0x1UL << CRS_CR_SYNCOKIE_Pos)               /*!< 0x00000001 */

+#define CRS_CR_SYNCOKIE           CRS_CR_SYNCOKIE_Msk                          /*!< SYNC event OK interrupt enable */

+#define CRS_CR_SYNCWARNIE_Pos     (1U)

+#define CRS_CR_SYNCWARNIE_Msk     (0x1UL << CRS_CR_SYNCWARNIE_Pos)             /*!< 0x00000002 */

+#define CRS_CR_SYNCWARNIE         CRS_CR_SYNCWARNIE_Msk                        /*!< SYNC warning interrupt enable */

+#define CRS_CR_ERRIE_Pos          (2U)

+#define CRS_CR_ERRIE_Msk          (0x1UL << CRS_CR_ERRIE_Pos)                  /*!< 0x00000004 */

+#define CRS_CR_ERRIE              CRS_CR_ERRIE_Msk                             /*!< SYNC error or trimming error interrupt enable */

+#define CRS_CR_ESYNCIE_Pos        (3U)

+#define CRS_CR_ESYNCIE_Msk        (0x1UL << CRS_CR_ESYNCIE_Pos)                /*!< 0x00000008 */

+#define CRS_CR_ESYNCIE            CRS_CR_ESYNCIE_Msk                           /*!< Expected SYNC interrupt enable */

+#define CRS_CR_CEN_Pos            (5U)

+#define CRS_CR_CEN_Msk            (0x1UL << CRS_CR_CEN_Pos)                    /*!< 0x00000020 */

+#define CRS_CR_CEN                CRS_CR_CEN_Msk                               /*!< Frequency error counter enable */

+#define CRS_CR_AUTOTRIMEN_Pos     (6U)

+#define CRS_CR_AUTOTRIMEN_Msk     (0x1UL << CRS_CR_AUTOTRIMEN_Pos)             /*!< 0x00000040 */

+#define CRS_CR_AUTOTRIMEN         CRS_CR_AUTOTRIMEN_Msk                        /*!< Automatic trimming enable */

+#define CRS_CR_SWSYNC_Pos         (7U)

+#define CRS_CR_SWSYNC_Msk         (0x1UL << CRS_CR_SWSYNC_Pos)                 /*!< 0x00000080 */

+#define CRS_CR_SWSYNC             CRS_CR_SWSYNC_Msk                            /*!< Generate software SYNC event */

+#define CRS_CR_TRIM_Pos           (8U)

+#define CRS_CR_TRIM_Msk           (0x3FUL << CRS_CR_TRIM_Pos)                  /*!< 0x00003F00 */

+#define CRS_CR_TRIM               CRS_CR_TRIM_Msk                              /*!< HSI48 oscillator smooth trimming */

+

+/*******************  Bit definition for CRS_CFGR register  *********************/

+#define CRS_CFGR_RELOAD_Pos       (0U)

+#define CRS_CFGR_RELOAD_Msk       (0xFFFFUL << CRS_CFGR_RELOAD_Pos)            /*!< 0x0000FFFF */

+#define CRS_CFGR_RELOAD           CRS_CFGR_RELOAD_Msk                          /*!< Counter reload value */

+#define CRS_CFGR_FELIM_Pos        (16U)

+#define CRS_CFGR_FELIM_Msk        (0xFFUL << CRS_CFGR_FELIM_Pos)               /*!< 0x00FF0000 */

+#define CRS_CFGR_FELIM            CRS_CFGR_FELIM_Msk                           /*!< Frequency error limit */

+

+#define CRS_CFGR_SYNCDIV_Pos      (24U)

+#define CRS_CFGR_SYNCDIV_Msk      (0x7UL << CRS_CFGR_SYNCDIV_Pos)              /*!< 0x07000000 */

+#define CRS_CFGR_SYNCDIV          CRS_CFGR_SYNCDIV_Msk                         /*!< SYNC divider */

+#define CRS_CFGR_SYNCDIV_0        (0x1UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x01000000 */

+#define CRS_CFGR_SYNCDIV_1        (0x2UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x02000000 */

+#define CRS_CFGR_SYNCDIV_2        (0x4UL << CRS_CFGR_SYNCDIV_Pos)               /*!< 0x04000000 */

+

+#define CRS_CFGR_SYNCSRC_Pos      (28U)

+#define CRS_CFGR_SYNCSRC_Msk      (0x3UL << CRS_CFGR_SYNCSRC_Pos)              /*!< 0x30000000 */

+#define CRS_CFGR_SYNCSRC          CRS_CFGR_SYNCSRC_Msk                         /*!< SYNC signal source selection */

+#define CRS_CFGR_SYNCSRC_0        (0x1UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x10000000 */

+#define CRS_CFGR_SYNCSRC_1        (0x2UL << CRS_CFGR_SYNCSRC_Pos)               /*!< 0x20000000 */

+

+#define CRS_CFGR_SYNCPOL_Pos      (31U)

+#define CRS_CFGR_SYNCPOL_Msk      (0x1UL << CRS_CFGR_SYNCPOL_Pos)              /*!< 0x80000000 */

+#define CRS_CFGR_SYNCPOL          CRS_CFGR_SYNCPOL_Msk                         /*!< SYNC polarity selection */

+

+/*******************  Bit definition for CRS_ISR register  *********************/

+#define CRS_ISR_SYNCOKF_Pos       (0U)

+#define CRS_ISR_SYNCOKF_Msk       (0x1UL << CRS_ISR_SYNCOKF_Pos)               /*!< 0x00000001 */

+#define CRS_ISR_SYNCOKF           CRS_ISR_SYNCOKF_Msk                          /*!< SYNC event OK flag */

+#define CRS_ISR_SYNCWARNF_Pos     (1U)

+#define CRS_ISR_SYNCWARNF_Msk     (0x1UL << CRS_ISR_SYNCWARNF_Pos)             /*!< 0x00000002 */

+#define CRS_ISR_SYNCWARNF         CRS_ISR_SYNCWARNF_Msk                        /*!< SYNC warning flag */

+#define CRS_ISR_ERRF_Pos          (2U)

+#define CRS_ISR_ERRF_Msk          (0x1UL << CRS_ISR_ERRF_Pos)                  /*!< 0x00000004 */

+#define CRS_ISR_ERRF              CRS_ISR_ERRF_Msk                             /*!< Error flag */

+#define CRS_ISR_ESYNCF_Pos        (3U)

+#define CRS_ISR_ESYNCF_Msk        (0x1UL << CRS_ISR_ESYNCF_Pos)                /*!< 0x00000008 */

+#define CRS_ISR_ESYNCF            CRS_ISR_ESYNCF_Msk                           /*!< Expected SYNC flag */

+#define CRS_ISR_SYNCERR_Pos       (8U)

+#define CRS_ISR_SYNCERR_Msk       (0x1UL << CRS_ISR_SYNCERR_Pos)               /*!< 0x00000100 */

+#define CRS_ISR_SYNCERR           CRS_ISR_SYNCERR_Msk                          /*!< SYNC error */

+#define CRS_ISR_SYNCMISS_Pos      (9U)

+#define CRS_ISR_SYNCMISS_Msk      (0x1UL << CRS_ISR_SYNCMISS_Pos)              /*!< 0x00000200 */

+#define CRS_ISR_SYNCMISS          CRS_ISR_SYNCMISS_Msk                         /*!< SYNC missed */

+#define CRS_ISR_TRIMOVF_Pos       (10U)

+#define CRS_ISR_TRIMOVF_Msk       (0x1UL << CRS_ISR_TRIMOVF_Pos)               /*!< 0x00000400 */

+#define CRS_ISR_TRIMOVF           CRS_ISR_TRIMOVF_Msk                          /*!< Trimming overflow or underflow */

+#define CRS_ISR_FEDIR_Pos         (15U)

+#define CRS_ISR_FEDIR_Msk         (0x1UL << CRS_ISR_FEDIR_Pos)                 /*!< 0x00008000 */

+#define CRS_ISR_FEDIR             CRS_ISR_FEDIR_Msk                            /*!< Frequency error direction */

+#define CRS_ISR_FECAP_Pos         (16U)

+#define CRS_ISR_FECAP_Msk         (0xFFFFUL << CRS_ISR_FECAP_Pos)              /*!< 0xFFFF0000 */

+#define CRS_ISR_FECAP             CRS_ISR_FECAP_Msk                            /*!< Frequency error capture */

+

+/*******************  Bit definition for CRS_ICR register  *********************/

+#define CRS_ICR_SYNCOKC_Pos       (0U)

+#define CRS_ICR_SYNCOKC_Msk       (0x1UL << CRS_ICR_SYNCOKC_Pos)               /*!< 0x00000001 */

+#define CRS_ICR_SYNCOKC           CRS_ICR_SYNCOKC_Msk                          /*!< SYNC event OK clear flag */

+#define CRS_ICR_SYNCWARNC_Pos     (1U)

+#define CRS_ICR_SYNCWARNC_Msk     (0x1UL << CRS_ICR_SYNCWARNC_Pos)             /*!< 0x00000002 */

+#define CRS_ICR_SYNCWARNC         CRS_ICR_SYNCWARNC_Msk                        /*!< SYNC warning clear flag */

+#define CRS_ICR_ERRC_Pos          (2U)

+#define CRS_ICR_ERRC_Msk          (0x1UL << CRS_ICR_ERRC_Pos)                  /*!< 0x00000004 */

+#define CRS_ICR_ERRC              CRS_ICR_ERRC_Msk                             /*!< Error clear flag */

+#define CRS_ICR_ESYNCC_Pos        (3U)

+#define CRS_ICR_ESYNCC_Msk        (0x1UL << CRS_ICR_ESYNCC_Pos)                /*!< 0x00000008 */

+#define CRS_ICR_ESYNCC            CRS_ICR_ESYNCC_Msk                           /*!< Expected SYNC clear flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            Crypto Processor                                */

+/*                                                                            */

+/******************************************************************************/

+/********************************  CRYP VER  **********************************/

+#define  CRYP_VER_2_2

+/******************* Bits definition for CRYP_CR register  ********************/

+#define CRYP_CR_ALGODIR_Pos              (2U)

+#define CRYP_CR_ALGODIR_Msk              (0x1UL << CRYP_CR_ALGODIR_Pos)        /*!< 0x00000004 */

+#define CRYP_CR_ALGODIR                  CRYP_CR_ALGODIR_Msk

+

+#define CRYP_CR_ALGOMODE_Pos             (3U)

+#define CRYP_CR_ALGOMODE_Msk             (0x10007UL << CRYP_CR_ALGOMODE_Pos)   /*!< 0x00080038 */

+#define CRYP_CR_ALGOMODE                 CRYP_CR_ALGOMODE_Msk

+#define CRYP_CR_ALGOMODE_0               (0x00001UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000008 */

+#define CRYP_CR_ALGOMODE_1               (0x00002UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000010 */

+#define CRYP_CR_ALGOMODE_2               (0x00004UL << CRYP_CR_ALGOMODE_Pos)    /*!< 0x00000020 */

+#define CRYP_CR_ALGOMODE_TDES_ECB        ((uint32_t)0x00000000)

+#define CRYP_CR_ALGOMODE_TDES_CBC_Pos    (3U)

+#define CRYP_CR_ALGOMODE_TDES_CBC_Msk    (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */

+#define CRYP_CR_ALGOMODE_TDES_CBC        CRYP_CR_ALGOMODE_TDES_CBC_Msk

+#define CRYP_CR_ALGOMODE_DES_ECB_Pos     (4U)

+#define CRYP_CR_ALGOMODE_DES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_DES_ECB_Pos) /*!< 0x00000010 */

+#define CRYP_CR_ALGOMODE_DES_ECB         CRYP_CR_ALGOMODE_DES_ECB_Msk

+#define CRYP_CR_ALGOMODE_DES_CBC_Pos     (3U)

+#define CRYP_CR_ALGOMODE_DES_CBC_Msk     (0x3UL << CRYP_CR_ALGOMODE_DES_CBC_Pos) /*!< 0x00000018 */

+#define CRYP_CR_ALGOMODE_DES_CBC         CRYP_CR_ALGOMODE_DES_CBC_Msk

+#define CRYP_CR_ALGOMODE_AES_ECB_Pos     (5U)

+#define CRYP_CR_ALGOMODE_AES_ECB_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */

+#define CRYP_CR_ALGOMODE_AES_ECB         CRYP_CR_ALGOMODE_AES_ECB_Msk

+#define CRYP_CR_ALGOMODE_AES_CBC_Pos     (3U)

+#define CRYP_CR_ALGOMODE_AES_CBC_Msk     (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */

+#define CRYP_CR_ALGOMODE_AES_CBC         CRYP_CR_ALGOMODE_AES_CBC_Msk

+#define CRYP_CR_ALGOMODE_AES_CTR_Pos     (4U)

+#define CRYP_CR_ALGOMODE_AES_CTR_Msk     (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */

+#define CRYP_CR_ALGOMODE_AES_CTR         CRYP_CR_ALGOMODE_AES_CTR_Msk

+#define CRYP_CR_ALGOMODE_AES_KEY_Pos     (3U)

+#define CRYP_CR_ALGOMODE_AES_KEY_Msk     (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */

+#define CRYP_CR_ALGOMODE_AES_KEY         CRYP_CR_ALGOMODE_AES_KEY_Msk

+#define CRYP_CR_ALGOMODE_AES_GCM_Pos     (19U)

+#define CRYP_CR_ALGOMODE_AES_GCM_Msk     (0x1UL << CRYP_CR_ALGOMODE_AES_GCM_Pos) /*!< 0x00080000 */

+#define CRYP_CR_ALGOMODE_AES_GCM         CRYP_CR_ALGOMODE_AES_GCM_Msk

+#define CRYP_CR_ALGOMODE_AES_CCM_Pos     (3U)

+#define CRYP_CR_ALGOMODE_AES_CCM_Msk     (0x10001UL << CRYP_CR_ALGOMODE_AES_CCM_Pos) /*!< 0x00080008 */

+#define CRYP_CR_ALGOMODE_AES_CCM         CRYP_CR_ALGOMODE_AES_CCM_Msk

+

+#define CRYP_CR_DATATYPE_Pos             (6U)

+#define CRYP_CR_DATATYPE_Msk             (0x3UL << CRYP_CR_DATATYPE_Pos)       /*!< 0x000000C0 */

+#define CRYP_CR_DATATYPE                 CRYP_CR_DATATYPE_Msk

+#define CRYP_CR_DATATYPE_0               (0x1UL << CRYP_CR_DATATYPE_Pos)        /*!< 0x00000040 */

+#define CRYP_CR_DATATYPE_1               (0x2UL << CRYP_CR_DATATYPE_Pos)        /*!< 0x00000080 */

+#define CRYP_CR_KEYSIZE_Pos              (8U)

+#define CRYP_CR_KEYSIZE_Msk              (0x3UL << CRYP_CR_KEYSIZE_Pos)        /*!< 0x00000300 */

+#define CRYP_CR_KEYSIZE                  CRYP_CR_KEYSIZE_Msk

+#define CRYP_CR_KEYSIZE_0                (0x1UL << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000100 */

+#define CRYP_CR_KEYSIZE_1                (0x2UL << CRYP_CR_KEYSIZE_Pos)         /*!< 0x00000200 */

+#define CRYP_CR_FFLUSH_Pos               (14U)

+#define CRYP_CR_FFLUSH_Msk               (0x1UL << CRYP_CR_FFLUSH_Pos)         /*!< 0x00004000 */

+#define CRYP_CR_FFLUSH                   CRYP_CR_FFLUSH_Msk

+#define CRYP_CR_CRYPEN_Pos               (15U)

+#define CRYP_CR_CRYPEN_Msk               (0x1UL << CRYP_CR_CRYPEN_Pos)         /*!< 0x00008000 */

+#define CRYP_CR_CRYPEN                   CRYP_CR_CRYPEN_Msk

+

+#define CRYP_CR_GCM_CCMPH_Pos            (16U)

+#define CRYP_CR_GCM_CCMPH_Msk            (0x3UL << CRYP_CR_GCM_CCMPH_Pos)      /*!< 0x00030000 */

+#define CRYP_CR_GCM_CCMPH                CRYP_CR_GCM_CCMPH_Msk

+#define CRYP_CR_GCM_CCMPH_0              (0x1UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00010000 */

+#define CRYP_CR_GCM_CCMPH_1              (0x2UL << CRYP_CR_GCM_CCMPH_Pos)       /*!< 0x00020000 */

+#define CRYP_CR_ALGOMODE_3               ((uint32_t)0x00080000)

+#define CRYP_CR_NPBLB_Pos                (20U)

+#define CRYP_CR_NPBLB_Msk                (0xFUL << CRYP_CR_NPBLB_Pos)          /*!< 0x00F00000 */

+#define CRYP_CR_NPBLB                    CRYP_CR_NPBLB_Msk

+

+/****************** Bits definition for CRYP_SR register  *********************/

+#define CRYP_SR_IFEM_Pos                 (0U)

+#define CRYP_SR_IFEM_Msk                 (0x1UL << CRYP_SR_IFEM_Pos)           /*!< 0x00000001 */

+#define CRYP_SR_IFEM                     CRYP_SR_IFEM_Msk

+#define CRYP_SR_IFNF_Pos                 (1U)

+#define CRYP_SR_IFNF_Msk                 (0x1UL << CRYP_SR_IFNF_Pos)           /*!< 0x00000002 */

+#define CRYP_SR_IFNF                     CRYP_SR_IFNF_Msk

+#define CRYP_SR_OFNE_Pos                 (2U)

+#define CRYP_SR_OFNE_Msk                 (0x1UL << CRYP_SR_OFNE_Pos)           /*!< 0x00000004 */

+#define CRYP_SR_OFNE                     CRYP_SR_OFNE_Msk

+#define CRYP_SR_OFFU_Pos                 (3U)

+#define CRYP_SR_OFFU_Msk                 (0x1UL << CRYP_SR_OFFU_Pos)           /*!< 0x00000008 */

+#define CRYP_SR_OFFU                     CRYP_SR_OFFU_Msk

+#define CRYP_SR_BUSY_Pos                 (4U)

+#define CRYP_SR_BUSY_Msk                 (0x1UL << CRYP_SR_BUSY_Pos)           /*!< 0x00000010 */

+#define CRYP_SR_BUSY                     CRYP_SR_BUSY_Msk

+/****************** Bits definition for CRYP_DMACR register  ******************/

+#define CRYP_DMACR_DIEN_Pos              (0U)

+#define CRYP_DMACR_DIEN_Msk              (0x1UL << CRYP_DMACR_DIEN_Pos)        /*!< 0x00000001 */

+#define CRYP_DMACR_DIEN                  CRYP_DMACR_DIEN_Msk

+#define CRYP_DMACR_DOEN_Pos              (1U)

+#define CRYP_DMACR_DOEN_Msk              (0x1UL << CRYP_DMACR_DOEN_Pos)        /*!< 0x00000002 */

+#define CRYP_DMACR_DOEN                  CRYP_DMACR_DOEN_Msk

+/*****************  Bits definition for CRYP_IMSCR register  ******************/

+#define CRYP_IMSCR_INIM_Pos              (0U)

+#define CRYP_IMSCR_INIM_Msk              (0x1UL << CRYP_IMSCR_INIM_Pos)        /*!< 0x00000001 */

+#define CRYP_IMSCR_INIM                  CRYP_IMSCR_INIM_Msk

+#define CRYP_IMSCR_OUTIM_Pos             (1U)

+#define CRYP_IMSCR_OUTIM_Msk             (0x1UL << CRYP_IMSCR_OUTIM_Pos)       /*!< 0x00000002 */

+#define CRYP_IMSCR_OUTIM                 CRYP_IMSCR_OUTIM_Msk

+/****************** Bits definition for CRYP_RISR register  *******************/

+#define CRYP_RISR_INRIS_Pos              (0U)

+#define CRYP_RISR_INRIS_Msk              (0x1UL << CRYP_RISR_INRIS_Pos)        /*!< 0x00000001 */

+#define CRYP_RISR_INRIS                  CRYP_RISR_INRIS_Msk

+#define CRYP_RISR_OUTRIS_Pos             (1U)

+#define CRYP_RISR_OUTRIS_Msk             (0x1UL << CRYP_RISR_OUTRIS_Pos)       /*!< 0x00000002 */

+#define CRYP_RISR_OUTRIS                 CRYP_RISR_OUTRIS_Msk

+/****************** Bits definition for CRYP_MISR register  *******************/

+#define CRYP_MISR_INMIS_Pos              (0U)

+#define CRYP_MISR_INMIS_Msk              (0x1UL << CRYP_MISR_INMIS_Pos)        /*!< 0x00000001 */

+#define CRYP_MISR_INMIS                  CRYP_MISR_INMIS_Msk

+#define CRYP_MISR_OUTMIS_Pos             (1U)

+#define CRYP_MISR_OUTMIS_Msk             (0x1UL << CRYP_MISR_OUTMIS_Pos)       /*!< 0x00000002 */

+#define CRYP_MISR_OUTMIS                 CRYP_MISR_OUTMIS_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                      Digital to Analog Converter                           */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for DAC_CR register  ********************/

+#define DAC_CR_EN1_Pos              (0U)

+#define DAC_CR_EN1_Msk              (0x1UL << DAC_CR_EN1_Pos)                  /*!< 0x00000001 */

+#define DAC_CR_EN1                  DAC_CR_EN1_Msk                             /*!<DAC channel1 enable */

+#define DAC_CR_TEN1_Pos             (1U)

+#define DAC_CR_TEN1_Msk             (0x1UL << DAC_CR_TEN1_Pos)                 /*!< 0x00000002 */

+#define DAC_CR_TEN1                 DAC_CR_TEN1_Msk                            /*!<DAC channel1 Trigger enable */

+

+#define DAC_CR_TSEL1_Pos            (2U)

+#define DAC_CR_TSEL1_Msk            (0xFUL << DAC_CR_TSEL1_Pos)                /*!< 0x0000003C */

+#define DAC_CR_TSEL1                DAC_CR_TSEL1_Msk                           /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */

+#define DAC_CR_TSEL1_0              (0x1UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000004 */

+#define DAC_CR_TSEL1_1              (0x2UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000008 */

+#define DAC_CR_TSEL1_2              (0x4UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000010 */

+#define DAC_CR_TSEL1_3              (0x8UL << DAC_CR_TSEL1_Pos)                 /*!< 0x00000020 */

+

+

+#define DAC_CR_WAVE1_Pos            (6U)

+#define DAC_CR_WAVE1_Msk            (0x3UL << DAC_CR_WAVE1_Pos)                /*!< 0x000000C0 */

+#define DAC_CR_WAVE1                DAC_CR_WAVE1_Msk                           /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */

+#define DAC_CR_WAVE1_0              (0x1UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000040 */

+#define DAC_CR_WAVE1_1              (0x2UL << DAC_CR_WAVE1_Pos)                 /*!< 0x00000080 */

+

+#define DAC_CR_MAMP1_Pos            (8U)

+#define DAC_CR_MAMP1_Msk            (0xFUL << DAC_CR_MAMP1_Pos)                /*!< 0x00000F00 */

+#define DAC_CR_MAMP1                DAC_CR_MAMP1_Msk                           /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */

+#define DAC_CR_MAMP1_0              (0x1UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000100 */

+#define DAC_CR_MAMP1_1              (0x2UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000200 */

+#define DAC_CR_MAMP1_2              (0x4UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000400 */

+#define DAC_CR_MAMP1_3              (0x8UL << DAC_CR_MAMP1_Pos)                 /*!< 0x00000800 */

+

+#define DAC_CR_DMAEN1_Pos           (12U)

+#define DAC_CR_DMAEN1_Msk           (0x1UL << DAC_CR_DMAEN1_Pos)               /*!< 0x00001000 */

+#define DAC_CR_DMAEN1               DAC_CR_DMAEN1_Msk                          /*!<DAC channel1 DMA enable */

+#define DAC_CR_DMAUDRIE1_Pos        (13U)

+#define DAC_CR_DMAUDRIE1_Msk        (0x1UL << DAC_CR_DMAUDRIE1_Pos)            /*!< 0x00002000 */

+#define DAC_CR_DMAUDRIE1            DAC_CR_DMAUDRIE1_Msk                       /*!<DAC channel 1 DMA underrun interrupt enable  >*/

+#define DAC_CR_CEN1_Pos             (14U)

+#define DAC_CR_CEN1_Msk             (0x1UL << DAC_CR_CEN1_Pos)                 /*!< 0x00004000 */

+#define DAC_CR_CEN1                 DAC_CR_CEN1_Msk                            /*!<DAC channel 1 calibration enable >*/

+

+#define DAC_CR_EN2_Pos              (16U)

+#define DAC_CR_EN2_Msk              (0x1UL << DAC_CR_EN2_Pos)                  /*!< 0x00010000 */

+#define DAC_CR_EN2                  DAC_CR_EN2_Msk                             /*!<DAC channel2 enable */

+#define DAC_CR_TEN2_Pos             (17U)

+#define DAC_CR_TEN2_Msk             (0x1UL << DAC_CR_TEN2_Pos)                 /*!< 0x00020000 */

+#define DAC_CR_TEN2                 DAC_CR_TEN2_Msk                            /*!<DAC channel2 Trigger enable */

+

+#define DAC_CR_TSEL2_Pos            (18U)

+#define DAC_CR_TSEL2_Msk            (0xFUL << DAC_CR_TSEL2_Pos)                /*!< 0x003C0000 */

+#define DAC_CR_TSEL2                DAC_CR_TSEL2_Msk                           /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */

+#define DAC_CR_TSEL2_0              (0x1UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00040000 */

+#define DAC_CR_TSEL2_1              (0x2UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00080000 */

+#define DAC_CR_TSEL2_2              (0x4UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00100000 */

+#define DAC_CR_TSEL2_3              (0x8UL << DAC_CR_TSEL2_Pos)                 /*!< 0x00200000 */

+

+

+#define DAC_CR_WAVE2_Pos            (22U)

+#define DAC_CR_WAVE2_Msk            (0x3UL << DAC_CR_WAVE2_Pos)                /*!< 0x00C00000 */

+#define DAC_CR_WAVE2                DAC_CR_WAVE2_Msk                           /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */

+#define DAC_CR_WAVE2_0              (0x1UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00400000 */

+#define DAC_CR_WAVE2_1              (0x2UL << DAC_CR_WAVE2_Pos)                 /*!< 0x00800000 */

+

+#define DAC_CR_MAMP2_Pos            (24U)

+#define DAC_CR_MAMP2_Msk            (0xFUL << DAC_CR_MAMP2_Pos)                /*!< 0x0F000000 */

+#define DAC_CR_MAMP2                DAC_CR_MAMP2_Msk                           /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */

+#define DAC_CR_MAMP2_0              (0x1UL << DAC_CR_MAMP2_Pos)                 /*!< 0x01000000 */

+#define DAC_CR_MAMP2_1              (0x2UL << DAC_CR_MAMP2_Pos)                 /*!< 0x02000000 */

+#define DAC_CR_MAMP2_2              (0x4UL << DAC_CR_MAMP2_Pos)                 /*!< 0x04000000 */

+#define DAC_CR_MAMP2_3              (0x8UL << DAC_CR_MAMP2_Pos)                 /*!< 0x08000000 */

+

+#define DAC_CR_DMAEN2_Pos           (28U)

+#define DAC_CR_DMAEN2_Msk           (0x1UL << DAC_CR_DMAEN2_Pos)               /*!< 0x10000000 */

+#define DAC_CR_DMAEN2               DAC_CR_DMAEN2_Msk                          /*!<DAC channel2 DMA enabled */

+#define DAC_CR_DMAUDRIE2_Pos        (29U)

+#define DAC_CR_DMAUDRIE2_Msk        (0x1UL << DAC_CR_DMAUDRIE2_Pos)            /*!< 0x20000000 */

+#define DAC_CR_DMAUDRIE2            DAC_CR_DMAUDRIE2_Msk                       /*!<DAC channel2 DMA underrun interrupt enable  >*/

+#define DAC_CR_CEN2_Pos             (30U)

+#define DAC_CR_CEN2_Msk             (0x1UL << DAC_CR_CEN2_Pos)                 /*!< 0x40000000 */

+#define DAC_CR_CEN2                 DAC_CR_CEN2_Msk                            /*!<DAC channel2 calibration enable >*/

+

+/*****************  Bit definition for DAC_SWTRIGR register  ******************/

+#define DAC_SWTRIGR_SWTRIG1_Pos     (0U)

+#define DAC_SWTRIGR_SWTRIG1_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)         /*!< 0x00000001 */

+#define DAC_SWTRIGR_SWTRIG1         DAC_SWTRIGR_SWTRIG1_Msk                    /*!<DAC channel1 software trigger */

+#define DAC_SWTRIGR_SWTRIG2_Pos     (1U)

+#define DAC_SWTRIGR_SWTRIG2_Msk     (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)         /*!< 0x00000002 */

+#define DAC_SWTRIGR_SWTRIG2         DAC_SWTRIGR_SWTRIG2_Msk                    /*!<DAC channel2 software trigger */

+

+/*****************  Bit definition for DAC_DHR12R1 register  ******************/

+#define DAC_DHR12R1_DACC1DHR_Pos    (0U)

+#define DAC_DHR12R1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12R1_DACC1DHR        DAC_DHR12R1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12L1 register  ******************/

+#define DAC_DHR12L1_DACC1DHR_Pos    (4U)

+#define DAC_DHR12L1_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12L1_DACC1DHR        DAC_DHR12L1_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8R1 register  ******************/

+#define DAC_DHR8R1_DACC1DHR_Pos     (0U)

+#define DAC_DHR8R1_DACC1DHR_Msk     (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8R1_DACC1DHR         DAC_DHR8R1_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12R2 register  ******************/

+#define DAC_DHR12R2_DACC2DHR_Pos    (0U)

+#define DAC_DHR12R2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12R2_DACC2DHR        DAC_DHR12R2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12L2 register  ******************/

+#define DAC_DHR12L2_DACC2DHR_Pos    (4U)

+#define DAC_DHR12L2_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12L2_DACC2DHR        DAC_DHR12L2_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8R2 register  ******************/

+#define DAC_DHR8R2_DACC2DHR_Pos     (0U)

+#define DAC_DHR8R2_DACC2DHR_Msk     (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8R2_DACC2DHR         DAC_DHR8R2_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12RD register  ******************/

+#define DAC_DHR12RD_DACC1DHR_Pos    (0U)

+#define DAC_DHR12RD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)      /*!< 0x00000FFF */

+#define DAC_DHR12RD_DACC1DHR        DAC_DHR12RD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Right aligned data */

+#define DAC_DHR12RD_DACC2DHR_Pos    (16U)

+#define DAC_DHR12RD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)      /*!< 0x0FFF0000 */

+#define DAC_DHR12RD_DACC2DHR        DAC_DHR12RD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Right aligned data */

+

+/*****************  Bit definition for DAC_DHR12LD register  ******************/

+#define DAC_DHR12LD_DACC1DHR_Pos    (4U)

+#define DAC_DHR12LD_DACC1DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)      /*!< 0x0000FFF0 */

+#define DAC_DHR12LD_DACC1DHR        DAC_DHR12LD_DACC1DHR_Msk                   /*!<DAC channel1 12-bit Left aligned data */

+#define DAC_DHR12LD_DACC2DHR_Pos    (20U)

+#define DAC_DHR12LD_DACC2DHR_Msk    (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)      /*!< 0xFFF00000 */

+#define DAC_DHR12LD_DACC2DHR        DAC_DHR12LD_DACC2DHR_Msk                   /*!<DAC channel2 12-bit Left aligned data */

+

+/******************  Bit definition for DAC_DHR8RD register  ******************/

+#define DAC_DHR8RD_DACC1DHR_Pos     (0U)

+#define DAC_DHR8RD_DACC1DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)        /*!< 0x000000FF */

+#define DAC_DHR8RD_DACC1DHR         DAC_DHR8RD_DACC1DHR_Msk                    /*!<DAC channel1 8-bit Right aligned data */

+#define DAC_DHR8RD_DACC2DHR_Pos     (8U)

+#define DAC_DHR8RD_DACC2DHR_Msk     (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)        /*!< 0x0000FF00 */

+#define DAC_DHR8RD_DACC2DHR         DAC_DHR8RD_DACC2DHR_Msk                    /*!<DAC channel2 8-bit Right aligned data */

+

+/*******************  Bit definition for DAC_DOR1 register  *******************/

+#define DAC_DOR1_DACC1DOR_Pos       (0U)

+#define DAC_DOR1_DACC1DOR_Msk       (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)         /*!< 0x00000FFF */

+#define DAC_DOR1_DACC1DOR           DAC_DOR1_DACC1DOR_Msk                      /*!<DAC channel1 data output */

+

+/*******************  Bit definition for DAC_DOR2 register  *******************/

+#define DAC_DOR2_DACC2DOR_Pos       (0U)

+#define DAC_DOR2_DACC2DOR_Msk       (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)         /*!< 0x00000FFF */

+#define DAC_DOR2_DACC2DOR           DAC_DOR2_DACC2DOR_Msk                      /*!<DAC channel2 data output */

+

+/********************  Bit definition for DAC_SR register  ********************/

+#define DAC_SR_DMAUDR1_Pos          (13U)

+#define DAC_SR_DMAUDR1_Msk          (0x1UL << DAC_SR_DMAUDR1_Pos)              /*!< 0x00002000 */

+#define DAC_SR_DMAUDR1              DAC_SR_DMAUDR1_Msk                         /*!<DAC channel1 DMA underrun flag */

+#define DAC_SR_CAL_FLAG1_Pos        (14U)

+#define DAC_SR_CAL_FLAG1_Msk        (0x1UL << DAC_SR_CAL_FLAG1_Pos)            /*!< 0x00004000 */

+#define DAC_SR_CAL_FLAG1            DAC_SR_CAL_FLAG1_Msk                       /*!<DAC channel1 calibration offset status */

+#define DAC_SR_BWST1_Pos            (15U)

+#define DAC_SR_BWST1_Msk            (0x4001UL << DAC_SR_BWST1_Pos)             /*!< 0x20008000 */

+#define DAC_SR_BWST1                DAC_SR_BWST1_Msk                           /*!<DAC channel1 busy writing sample time flag */

+

+#define DAC_SR_DMAUDR2_Pos          (29U)

+#define DAC_SR_DMAUDR2_Msk          (0x1UL << DAC_SR_DMAUDR2_Pos)              /*!< 0x20000000 */

+#define DAC_SR_DMAUDR2              DAC_SR_DMAUDR2_Msk                         /*!<DAC channel2 DMA underrun flag */

+#define DAC_SR_CAL_FLAG2_Pos        (30U)

+#define DAC_SR_CAL_FLAG2_Msk        (0x1UL << DAC_SR_CAL_FLAG2_Pos)            /*!< 0x40000000 */

+#define DAC_SR_CAL_FLAG2            DAC_SR_CAL_FLAG2_Msk                       /*!<DAC channel2 calibration offset status */

+#define DAC_SR_BWST2_Pos            (31U)

+#define DAC_SR_BWST2_Msk            (0x1UL << DAC_SR_BWST2_Pos)                /*!< 0x80000000 */

+#define DAC_SR_BWST2                DAC_SR_BWST2_Msk                           /*!<DAC channel2 busy writing sample time flag */

+

+/*******************  Bit definition for DAC_CCR register  ********************/

+#define DAC_CCR_OTRIM1_Pos          (0U)

+#define DAC_CCR_OTRIM1_Msk          (0x1FUL << DAC_CCR_OTRIM1_Pos)             /*!< 0x0000001F */

+#define DAC_CCR_OTRIM1              DAC_CCR_OTRIM1_Msk                         /*!<DAC channel1 offset trimming value */

+#define DAC_CCR_OTRIM2_Pos          (16U)

+#define DAC_CCR_OTRIM2_Msk          (0x1FUL << DAC_CCR_OTRIM2_Pos)             /*!< 0x001F0000 */

+#define DAC_CCR_OTRIM2              DAC_CCR_OTRIM2_Msk                         /*!<DAC channel2 offset trimming value */

+

+/*******************  Bit definition for DAC_MCR register  *******************/

+#define DAC_MCR_MODE1_Pos           (0U)

+#define DAC_MCR_MODE1_Msk           (0x7UL << DAC_MCR_MODE1_Pos)               /*!< 0x00000007 */

+#define DAC_MCR_MODE1               DAC_MCR_MODE1_Msk                          /*!<MODE1[2:0] (DAC channel1 mode) */

+#define DAC_MCR_MODE1_0             (0x1UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000001 */

+#define DAC_MCR_MODE1_1             (0x2UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000002 */

+#define DAC_MCR_MODE1_2             (0x4UL << DAC_MCR_MODE1_Pos)                /*!< 0x00000004 */

+

+#define DAC_MCR_MODE2_Pos           (16U)

+#define DAC_MCR_MODE2_Msk           (0x7UL << DAC_MCR_MODE2_Pos)               /*!< 0x00070000 */

+#define DAC_MCR_MODE2               DAC_MCR_MODE2_Msk                          /*!<MODE2[2:0] (DAC channel2 mode) */

+#define DAC_MCR_MODE2_0             (0x1UL << DAC_MCR_MODE2_Pos)                /*!< 0x00010000 */

+#define DAC_MCR_MODE2_1             (0x2UL << DAC_MCR_MODE2_Pos)                /*!< 0x00020000 */

+#define DAC_MCR_MODE2_2             (0x4UL << DAC_MCR_MODE2_Pos)                /*!< 0x00040000 */

+

+/******************  Bit definition for DAC_SHSR1 register  ******************/

+#define DAC_SHSR1_TSAMPLE1_Pos      (0U)

+#define DAC_SHSR1_TSAMPLE1_Msk      (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos)        /*!< 0x000003FF */

+#define DAC_SHSR1_TSAMPLE1          DAC_SHSR1_TSAMPLE1_Msk                     /*!<DAC channel1 sample time */

+

+/******************  Bit definition for DAC_SHSR2 register  ******************/

+#define DAC_SHSR2_TSAMPLE2_Pos      (0U)

+#define DAC_SHSR2_TSAMPLE2_Msk      (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos)        /*!< 0x000003FF */

+#define DAC_SHSR2_TSAMPLE2          DAC_SHSR2_TSAMPLE2_Msk                     /*!<DAC channel2 sample time */

+

+/******************  Bit definition for DAC_SHHR register  ******************/

+#define DAC_SHHR_THOLD1_Pos         (0U)

+#define DAC_SHHR_THOLD1_Msk         (0x3FFUL << DAC_SHHR_THOLD1_Pos)           /*!< 0x000003FF */

+#define DAC_SHHR_THOLD1             DAC_SHHR_THOLD1_Msk                        /*!<DAC channel1 hold time */

+#define DAC_SHHR_THOLD2_Pos         (16U)

+#define DAC_SHHR_THOLD2_Msk         (0x3FFUL << DAC_SHHR_THOLD2_Pos)           /*!< 0x03FF0000 */

+#define DAC_SHHR_THOLD2             DAC_SHHR_THOLD2_Msk                        /*!<DAC channel2 hold time */

+

+/******************  Bit definition for DAC_SHRR register  ******************/

+#define DAC_SHRR_TREFRESH1_Pos      (0U)

+#define DAC_SHRR_TREFRESH1_Msk      (0xFFUL << DAC_SHRR_TREFRESH1_Pos)         /*!< 0x000000FF */

+#define DAC_SHRR_TREFRESH1          DAC_SHRR_TREFRESH1_Msk                     /*!<DAC channel1 refresh time */

+#define DAC_SHRR_TREFRESH2_Pos      (16U)

+#define DAC_SHRR_TREFRESH2_Msk      (0xFFUL << DAC_SHRR_TREFRESH2_Pos)         /*!< 0x00FF0000 */

+#define DAC_SHRR_TREFRESH2          DAC_SHRR_TREFRESH2_Msk                     /*!<DAC channel2 refresh time */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    DCMI                                    */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DCMI_CR register  ******************/

+#define DCMI_CR_CAPTURE_Pos        (0U)

+#define DCMI_CR_CAPTURE_Msk        (0x1UL << DCMI_CR_CAPTURE_Pos)              /*!< 0x00000001 */

+#define DCMI_CR_CAPTURE            DCMI_CR_CAPTURE_Msk

+#define DCMI_CR_CM_Pos             (1U)

+#define DCMI_CR_CM_Msk             (0x1UL << DCMI_CR_CM_Pos)                   /*!< 0x00000002 */

+#define DCMI_CR_CM                 DCMI_CR_CM_Msk

+#define DCMI_CR_CROP_Pos           (2U)

+#define DCMI_CR_CROP_Msk           (0x1UL << DCMI_CR_CROP_Pos)                 /*!< 0x00000004 */

+#define DCMI_CR_CROP               DCMI_CR_CROP_Msk

+#define DCMI_CR_JPEG_Pos           (3U)

+#define DCMI_CR_JPEG_Msk           (0x1UL << DCMI_CR_JPEG_Pos)                 /*!< 0x00000008 */

+#define DCMI_CR_JPEG               DCMI_CR_JPEG_Msk

+#define DCMI_CR_ESS_Pos            (4U)

+#define DCMI_CR_ESS_Msk            (0x1UL << DCMI_CR_ESS_Pos)                  /*!< 0x00000010 */

+#define DCMI_CR_ESS                DCMI_CR_ESS_Msk

+#define DCMI_CR_PCKPOL_Pos         (5U)

+#define DCMI_CR_PCKPOL_Msk         (0x1UL << DCMI_CR_PCKPOL_Pos)               /*!< 0x00000020 */

+#define DCMI_CR_PCKPOL             DCMI_CR_PCKPOL_Msk

+#define DCMI_CR_HSPOL_Pos          (6U)

+#define DCMI_CR_HSPOL_Msk          (0x1UL << DCMI_CR_HSPOL_Pos)                /*!< 0x00000040 */

+#define DCMI_CR_HSPOL              DCMI_CR_HSPOL_Msk

+#define DCMI_CR_VSPOL_Pos          (7U)

+#define DCMI_CR_VSPOL_Msk          (0x1UL << DCMI_CR_VSPOL_Pos)                /*!< 0x00000080 */

+#define DCMI_CR_VSPOL              DCMI_CR_VSPOL_Msk

+#define DCMI_CR_FCRC_0             ((uint32_t)0x00000100U)

+#define DCMI_CR_FCRC_1             ((uint32_t)0x00000200U)

+#define DCMI_CR_EDM_0              ((uint32_t)0x00000400U)

+#define DCMI_CR_EDM_1              ((uint32_t)0x00000800U)

+#define DCMI_CR_CRE_Pos            (12U)

+#define DCMI_CR_CRE_Msk            (0x1UL << DCMI_CR_CRE_Pos)                  /*!< 0x00001000 */

+#define DCMI_CR_CRE                DCMI_CR_CRE_Msk

+#define DCMI_CR_ENABLE_Pos         (14U)

+#define DCMI_CR_ENABLE_Msk         (0x1UL << DCMI_CR_ENABLE_Pos)               /*!< 0x00004000 */

+#define DCMI_CR_ENABLE             DCMI_CR_ENABLE_Msk

+#define DCMI_CR_BSM_Pos            (16U)

+#define DCMI_CR_BSM_Msk            (0x3UL << DCMI_CR_BSM_Pos)                  /*!< 0x00030000 */

+#define DCMI_CR_BSM                DCMI_CR_BSM_Msk

+#define DCMI_CR_BSM_0              (0x1UL << DCMI_CR_BSM_Pos)                   /*!< 0x00010000 */

+#define DCMI_CR_BSM_1              (0x2UL << DCMI_CR_BSM_Pos)                   /*!< 0x00020000 */

+#define DCMI_CR_OEBS_Pos           (18U)

+#define DCMI_CR_OEBS_Msk           (0x1UL << DCMI_CR_OEBS_Pos)                 /*!< 0x00040000 */

+#define DCMI_CR_OEBS               DCMI_CR_OEBS_Msk

+#define DCMI_CR_LSM_Pos            (19U)

+#define DCMI_CR_LSM_Msk            (0x1UL << DCMI_CR_LSM_Pos)                  /*!< 0x00080000 */

+#define DCMI_CR_LSM                DCMI_CR_LSM_Msk

+#define DCMI_CR_OELS_Pos           (20U)

+#define DCMI_CR_OELS_Msk           (0x1UL << DCMI_CR_OELS_Pos)                 /*!< 0x00100000 */

+#define DCMI_CR_OELS               DCMI_CR_OELS_Msk

+

+/********************  Bits definition for DCMI_SR register  ******************/

+#define DCMI_SR_HSYNC_Pos          (0U)

+#define DCMI_SR_HSYNC_Msk          (0x1UL << DCMI_SR_HSYNC_Pos)                /*!< 0x00000001 */

+#define DCMI_SR_HSYNC              DCMI_SR_HSYNC_Msk

+#define DCMI_SR_VSYNC_Pos          (1U)

+#define DCMI_SR_VSYNC_Msk          (0x1UL << DCMI_SR_VSYNC_Pos)                /*!< 0x00000002 */

+#define DCMI_SR_VSYNC              DCMI_SR_VSYNC_Msk

+#define DCMI_SR_FNE_Pos            (2U)

+#define DCMI_SR_FNE_Msk            (0x1UL << DCMI_SR_FNE_Pos)                  /*!< 0x00000004 */

+#define DCMI_SR_FNE                DCMI_SR_FNE_Msk

+

+/********************  Bits definition for DCMI_RIS register   ****************/

+#define DCMI_RIS_FRAME_RIS_Pos     (0U)

+#define DCMI_RIS_FRAME_RIS_Msk     (0x1UL << DCMI_RIS_FRAME_RIS_Pos)           /*!< 0x00000001 */

+#define DCMI_RIS_FRAME_RIS         DCMI_RIS_FRAME_RIS_Msk

+#define DCMI_RIS_OVR_RIS_Pos       (1U)

+#define DCMI_RIS_OVR_RIS_Msk       (0x1UL << DCMI_RIS_OVR_RIS_Pos)             /*!< 0x00000002 */

+#define DCMI_RIS_OVR_RIS           DCMI_RIS_OVR_RIS_Msk

+#define DCMI_RIS_ERR_RIS_Pos       (2U)

+#define DCMI_RIS_ERR_RIS_Msk       (0x1UL << DCMI_RIS_ERR_RIS_Pos)             /*!< 0x00000004 */

+#define DCMI_RIS_ERR_RIS           DCMI_RIS_ERR_RIS_Msk

+#define DCMI_RIS_VSYNC_RIS_Pos     (3U)

+#define DCMI_RIS_VSYNC_RIS_Msk     (0x1UL << DCMI_RIS_VSYNC_RIS_Pos)           /*!< 0x00000008 */

+#define DCMI_RIS_VSYNC_RIS         DCMI_RIS_VSYNC_RIS_Msk

+#define DCMI_RIS_LINE_RIS_Pos      (4U)

+#define DCMI_RIS_LINE_RIS_Msk      (0x1UL << DCMI_RIS_LINE_RIS_Pos)            /*!< 0x00000010 */

+#define DCMI_RIS_LINE_RIS          DCMI_RIS_LINE_RIS_Msk

+

+/********************  Bits definition for DCMI_IER register  *****************/

+#define DCMI_IER_FRAME_IE_Pos      (0U)

+#define DCMI_IER_FRAME_IE_Msk      (0x1UL << DCMI_IER_FRAME_IE_Pos)            /*!< 0x00000001 */

+#define DCMI_IER_FRAME_IE          DCMI_IER_FRAME_IE_Msk

+#define DCMI_IER_OVR_IE_Pos        (1U)

+#define DCMI_IER_OVR_IE_Msk        (0x1UL << DCMI_IER_OVR_IE_Pos)              /*!< 0x00000002 */

+#define DCMI_IER_OVR_IE            DCMI_IER_OVR_IE_Msk

+#define DCMI_IER_ERR_IE_Pos        (2U)

+#define DCMI_IER_ERR_IE_Msk        (0x1UL << DCMI_IER_ERR_IE_Pos)              /*!< 0x00000004 */

+#define DCMI_IER_ERR_IE            DCMI_IER_ERR_IE_Msk

+#define DCMI_IER_VSYNC_IE_Pos      (3U)

+#define DCMI_IER_VSYNC_IE_Msk      (0x1UL << DCMI_IER_VSYNC_IE_Pos)            /*!< 0x00000008 */

+#define DCMI_IER_VSYNC_IE          DCMI_IER_VSYNC_IE_Msk

+#define DCMI_IER_LINE_IE_Pos       (4U)

+#define DCMI_IER_LINE_IE_Msk       (0x1UL << DCMI_IER_LINE_IE_Pos)             /*!< 0x00000010 */

+#define DCMI_IER_LINE_IE           DCMI_IER_LINE_IE_Msk

+

+

+/********************  Bits definition for DCMI_MIS register  *****************/

+#define DCMI_MIS_FRAME_MIS_Pos     (0U)

+#define DCMI_MIS_FRAME_MIS_Msk     (0x1UL << DCMI_MIS_FRAME_MIS_Pos)           /*!< 0x00000001 */

+#define DCMI_MIS_FRAME_MIS         DCMI_MIS_FRAME_MIS_Msk

+#define DCMI_MIS_OVR_MIS_Pos       (1U)

+#define DCMI_MIS_OVR_MIS_Msk       (0x1UL << DCMI_MIS_OVR_MIS_Pos)             /*!< 0x00000002 */

+#define DCMI_MIS_OVR_MIS           DCMI_MIS_OVR_MIS_Msk

+#define DCMI_MIS_ERR_MIS_Pos       (2U)

+#define DCMI_MIS_ERR_MIS_Msk       (0x1UL << DCMI_MIS_ERR_MIS_Pos)             /*!< 0x00000004 */

+#define DCMI_MIS_ERR_MIS           DCMI_MIS_ERR_MIS_Msk

+#define DCMI_MIS_VSYNC_MIS_Pos     (3U)

+#define DCMI_MIS_VSYNC_MIS_Msk     (0x1UL << DCMI_MIS_VSYNC_MIS_Pos)           /*!< 0x00000008 */

+#define DCMI_MIS_VSYNC_MIS         DCMI_MIS_VSYNC_MIS_Msk

+#define DCMI_MIS_LINE_MIS_Pos      (4U)

+#define DCMI_MIS_LINE_MIS_Msk      (0x1UL << DCMI_MIS_LINE_MIS_Pos)            /*!< 0x00000010 */

+#define DCMI_MIS_LINE_MIS          DCMI_MIS_LINE_MIS_Msk

+

+

+/********************  Bits definition for DCMI_ICR register  *****************/

+#define DCMI_ICR_FRAME_ISC_Pos     (0U)

+#define DCMI_ICR_FRAME_ISC_Msk     (0x1UL << DCMI_ICR_FRAME_ISC_Pos)           /*!< 0x00000001 */

+#define DCMI_ICR_FRAME_ISC         DCMI_ICR_FRAME_ISC_Msk

+#define DCMI_ICR_OVR_ISC_Pos       (1U)

+#define DCMI_ICR_OVR_ISC_Msk       (0x1UL << DCMI_ICR_OVR_ISC_Pos)             /*!< 0x00000002 */

+#define DCMI_ICR_OVR_ISC           DCMI_ICR_OVR_ISC_Msk

+#define DCMI_ICR_ERR_ISC_Pos       (2U)

+#define DCMI_ICR_ERR_ISC_Msk       (0x1UL << DCMI_ICR_ERR_ISC_Pos)             /*!< 0x00000004 */

+#define DCMI_ICR_ERR_ISC           DCMI_ICR_ERR_ISC_Msk

+#define DCMI_ICR_VSYNC_ISC_Pos     (3U)

+#define DCMI_ICR_VSYNC_ISC_Msk     (0x1UL << DCMI_ICR_VSYNC_ISC_Pos)           /*!< 0x00000008 */

+#define DCMI_ICR_VSYNC_ISC         DCMI_ICR_VSYNC_ISC_Msk

+#define DCMI_ICR_LINE_ISC_Pos      (4U)

+#define DCMI_ICR_LINE_ISC_Msk      (0x1UL << DCMI_ICR_LINE_ISC_Pos)            /*!< 0x00000010 */

+#define DCMI_ICR_LINE_ISC          DCMI_ICR_LINE_ISC_Msk

+

+

+/********************  Bits definition for DCMI_ESCR register  ******************/

+#define DCMI_ESCR_FSC_Pos          (0U)

+#define DCMI_ESCR_FSC_Msk          (0xFFUL << DCMI_ESCR_FSC_Pos)               /*!< 0x000000FF */

+#define DCMI_ESCR_FSC              DCMI_ESCR_FSC_Msk

+#define DCMI_ESCR_LSC_Pos          (8U)

+#define DCMI_ESCR_LSC_Msk          (0xFFUL << DCMI_ESCR_LSC_Pos)               /*!< 0x0000FF00 */

+#define DCMI_ESCR_LSC              DCMI_ESCR_LSC_Msk

+#define DCMI_ESCR_LEC_Pos          (16U)

+#define DCMI_ESCR_LEC_Msk          (0xFFUL << DCMI_ESCR_LEC_Pos)               /*!< 0x00FF0000 */

+#define DCMI_ESCR_LEC              DCMI_ESCR_LEC_Msk

+#define DCMI_ESCR_FEC_Pos          (24U)

+#define DCMI_ESCR_FEC_Msk          (0xFFUL << DCMI_ESCR_FEC_Pos)               /*!< 0xFF000000 */

+#define DCMI_ESCR_FEC              DCMI_ESCR_FEC_Msk

+

+/********************  Bits definition for DCMI_ESUR register  ******************/

+#define DCMI_ESUR_FSU_Pos          (0U)

+#define DCMI_ESUR_FSU_Msk          (0xFFUL << DCMI_ESUR_FSU_Pos)               /*!< 0x000000FF */

+#define DCMI_ESUR_FSU              DCMI_ESUR_FSU_Msk

+#define DCMI_ESUR_LSU_Pos          (8U)

+#define DCMI_ESUR_LSU_Msk          (0xFFUL << DCMI_ESUR_LSU_Pos)               /*!< 0x0000FF00 */

+#define DCMI_ESUR_LSU              DCMI_ESUR_LSU_Msk

+#define DCMI_ESUR_LEU_Pos          (16U)

+#define DCMI_ESUR_LEU_Msk          (0xFFUL << DCMI_ESUR_LEU_Pos)               /*!< 0x00FF0000 */

+#define DCMI_ESUR_LEU              DCMI_ESUR_LEU_Msk

+#define DCMI_ESUR_FEU_Pos          (24U)

+#define DCMI_ESUR_FEU_Msk          (0xFFUL << DCMI_ESUR_FEU_Pos)               /*!< 0xFF000000 */

+#define DCMI_ESUR_FEU              DCMI_ESUR_FEU_Msk

+

+/********************  Bits definition for DCMI_CWSTRT register  ******************/

+#define DCMI_CWSTRT_HOFFCNT_Pos    (0U)

+#define DCMI_CWSTRT_HOFFCNT_Msk    (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos)       /*!< 0x00003FFF */

+#define DCMI_CWSTRT_HOFFCNT        DCMI_CWSTRT_HOFFCNT_Msk

+#define DCMI_CWSTRT_VST_Pos        (16U)

+#define DCMI_CWSTRT_VST_Msk        (0x1FFFUL << DCMI_CWSTRT_VST_Pos)           /*!< 0x1FFF0000 */

+#define DCMI_CWSTRT_VST            DCMI_CWSTRT_VST_Msk

+

+/********************  Bits definition for DCMI_CWSIZE register  ******************/

+#define DCMI_CWSIZE_CAPCNT_Pos     (0U)

+#define DCMI_CWSIZE_CAPCNT_Msk     (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos)        /*!< 0x00003FFF */

+#define DCMI_CWSIZE_CAPCNT         DCMI_CWSIZE_CAPCNT_Msk

+#define DCMI_CWSIZE_VLINE_Pos      (16U)

+#define DCMI_CWSIZE_VLINE_Msk      (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos)         /*!< 0x3FFF0000 */

+#define DCMI_CWSIZE_VLINE          DCMI_CWSIZE_VLINE_Msk

+

+/********************  Bits definition for DCMI_DR register  ******************/

+#define DCMI_DR_BYTE0_Pos          (0U)

+#define DCMI_DR_BYTE0_Msk          (0xFFUL << DCMI_DR_BYTE0_Pos)               /*!< 0x000000FF */

+#define DCMI_DR_BYTE0              DCMI_DR_BYTE0_Msk

+#define DCMI_DR_BYTE1_Pos          (8U)

+#define DCMI_DR_BYTE1_Msk          (0xFFUL << DCMI_DR_BYTE1_Pos)               /*!< 0x0000FF00 */

+#define DCMI_DR_BYTE1              DCMI_DR_BYTE1_Msk

+#define DCMI_DR_BYTE2_Pos          (16U)

+#define DCMI_DR_BYTE2_Msk          (0xFFUL << DCMI_DR_BYTE2_Pos)               /*!< 0x00FF0000 */

+#define DCMI_DR_BYTE2              DCMI_DR_BYTE2_Msk

+#define DCMI_DR_BYTE3_Pos          (24U)

+#define DCMI_DR_BYTE3_Msk          (0xFFUL << DCMI_DR_BYTE3_Pos)               /*!< 0xFF000000 */

+#define DCMI_DR_BYTE3              DCMI_DR_BYTE3_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                 Digital Filter for Sigma Delta Modulators                  */

+/*                                                                            */

+/******************************************************************************/

+

+/****************   DFSDM channel configuration registers  ********************/

+

+/***************  Bit definition for DFSDM_CHCFGR1 register  ******************/

+#define DFSDM_CHCFGR1_DFSDMEN_Pos       (31U)

+#define DFSDM_CHCFGR1_DFSDMEN_Msk       (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos)   /*!< 0x80000000 */

+#define DFSDM_CHCFGR1_DFSDMEN           DFSDM_CHCFGR1_DFSDMEN_Msk              /*!< Global enable for DFSDM interface */

+#define DFSDM_CHCFGR1_CKOUTSRC_Pos      (30U)

+#define DFSDM_CHCFGR1_CKOUTSRC_Msk      (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos)  /*!< 0x40000000 */

+#define DFSDM_CHCFGR1_CKOUTSRC          DFSDM_CHCFGR1_CKOUTSRC_Msk             /*!< Output serial clock source selection */

+#define DFSDM_CHCFGR1_CKOUTDIV_Pos      (16U)

+#define DFSDM_CHCFGR1_CKOUTDIV_Msk      (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */

+#define DFSDM_CHCFGR1_CKOUTDIV          DFSDM_CHCFGR1_CKOUTDIV_Msk             /*!< CKOUTDIV[7:0] output serial clock divider */

+#define DFSDM_CHCFGR1_DATPACK_Pos       (14U)

+#define DFSDM_CHCFGR1_DATPACK_Msk       (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos)   /*!< 0x0000C000 */

+#define DFSDM_CHCFGR1_DATPACK           DFSDM_CHCFGR1_DATPACK_Msk              /*!< DATPACK[1:0] Data packing mode */

+#define DFSDM_CHCFGR1_DATPACK_1         (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00008000 */

+#define DFSDM_CHCFGR1_DATPACK_0         (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos)    /*!< 0x00004000 */

+#define DFSDM_CHCFGR1_DATMPX_Pos        (12U)

+#define DFSDM_CHCFGR1_DATMPX_Msk        (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos)    /*!< 0x00003000 */

+#define DFSDM_CHCFGR1_DATMPX            DFSDM_CHCFGR1_DATMPX_Msk               /*!< DATMPX[1:0] Input data multiplexer for channel y */

+#define DFSDM_CHCFGR1_DATMPX_1          (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00002000 */

+#define DFSDM_CHCFGR1_DATMPX_0          (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos)     /*!< 0x00001000 */

+#define DFSDM_CHCFGR1_CHINSEL_Pos       (8U)

+#define DFSDM_CHCFGR1_CHINSEL_Msk       (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos)   /*!< 0x00000100 */

+#define DFSDM_CHCFGR1_CHINSEL           DFSDM_CHCFGR1_CHINSEL_Msk              /*!< Serial inputs selection for channel y */

+#define DFSDM_CHCFGR1_CHEN_Pos          (7U)

+#define DFSDM_CHCFGR1_CHEN_Msk          (0x1UL << DFSDM_CHCFGR1_CHEN_Pos)      /*!< 0x00000080 */

+#define DFSDM_CHCFGR1_CHEN              DFSDM_CHCFGR1_CHEN_Msk                 /*!< Channel y enable */

+#define DFSDM_CHCFGR1_CKABEN_Pos        (6U)

+#define DFSDM_CHCFGR1_CKABEN_Msk        (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos)    /*!< 0x00000040 */

+#define DFSDM_CHCFGR1_CKABEN            DFSDM_CHCFGR1_CKABEN_Msk               /*!< Clock absence detector enable on channel y */

+#define DFSDM_CHCFGR1_SCDEN_Pos         (5U)

+#define DFSDM_CHCFGR1_SCDEN_Msk         (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos)     /*!< 0x00000020 */

+#define DFSDM_CHCFGR1_SCDEN             DFSDM_CHCFGR1_SCDEN_Msk                /*!< Short circuit detector enable on channel y */

+#define DFSDM_CHCFGR1_SPICKSEL_Pos      (2U)

+#define DFSDM_CHCFGR1_SPICKSEL_Msk      (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos)  /*!< 0x0000000C */

+#define DFSDM_CHCFGR1_SPICKSEL          DFSDM_CHCFGR1_SPICKSEL_Msk             /*!< SPICKSEL[1:0] SPI clock select for channel y */

+#define DFSDM_CHCFGR1_SPICKSEL_1        (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000008 */

+#define DFSDM_CHCFGR1_SPICKSEL_0        (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos)   /*!< 0x00000004 */

+#define DFSDM_CHCFGR1_SITP_Pos          (0U)

+#define DFSDM_CHCFGR1_SITP_Msk          (0x3UL << DFSDM_CHCFGR1_SITP_Pos)      /*!< 0x00000003 */

+#define DFSDM_CHCFGR1_SITP              DFSDM_CHCFGR1_SITP_Msk                 /*!< SITP[1:0] Serial interface type for channel y */

+#define DFSDM_CHCFGR1_SITP_1            (0x2UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000002 */

+#define DFSDM_CHCFGR1_SITP_0            (0x1UL << DFSDM_CHCFGR1_SITP_Pos)       /*!< 0x00000001 */

+

+/***************  Bit definition for DFSDM_CHCFGR2 register  ******************/

+#define DFSDM_CHCFGR2_OFFSET_Pos        (8U)

+#define DFSDM_CHCFGR2_OFFSET_Msk        (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_CHCFGR2_OFFSET            DFSDM_CHCFGR2_OFFSET_Msk               /*!< OFFSET[23:0] 24-bit calibration offset for channel y */

+#define DFSDM_CHCFGR2_DTRBS_Pos         (3U)

+#define DFSDM_CHCFGR2_DTRBS_Msk         (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos)    /*!< 0x000000F8 */

+#define DFSDM_CHCFGR2_DTRBS             DFSDM_CHCFGR2_DTRBS_Msk                /*!< DTRBS[4:0] Data right bit-shift for channel y */

+

+/******************  Bit definition for DFSDM_CHAWSCDR register *****************/

+#define DFSDM_CHAWSCDR_AWFORD_Pos       (22U)

+#define DFSDM_CHAWSCDR_AWFORD_Msk       (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos)   /*!< 0x00C00000 */

+#define DFSDM_CHAWSCDR_AWFORD           DFSDM_CHAWSCDR_AWFORD_Msk              /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */

+#define DFSDM_CHAWSCDR_AWFORD_1         (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00800000 */

+#define DFSDM_CHAWSCDR_AWFORD_0         (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos)    /*!< 0x00400000 */

+#define DFSDM_CHAWSCDR_AWFOSR_Pos       (16U)

+#define DFSDM_CHAWSCDR_AWFOSR_Msk       (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos)  /*!< 0x001F0000 */

+#define DFSDM_CHAWSCDR_AWFOSR           DFSDM_CHAWSCDR_AWFOSR_Msk              /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */

+#define DFSDM_CHAWSCDR_BKSCD_Pos        (12U)

+#define DFSDM_CHAWSCDR_BKSCD_Msk        (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos)    /*!< 0x0000F000 */

+#define DFSDM_CHAWSCDR_BKSCD            DFSDM_CHAWSCDR_BKSCD_Msk               /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */

+#define DFSDM_CHAWSCDR_SCDT_Pos         (0U)

+#define DFSDM_CHAWSCDR_SCDT_Msk         (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos)    /*!< 0x000000FF */

+#define DFSDM_CHAWSCDR_SCDT             DFSDM_CHAWSCDR_SCDT_Msk                /*!< SCDT[7:0] Short circuit detector threshold for channel y */

+

+/****************  Bit definition for DFSDM_CHWDATR register *******************/

+#define DFSDM_CHWDATR_WDATA_Pos         (0U)

+#define DFSDM_CHWDATR_WDATA_Msk         (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos)  /*!< 0x0000FFFF */

+#define DFSDM_CHWDATR_WDATA             DFSDM_CHWDATR_WDATA_Msk                /*!< WDATA[15:0] Input channel y watchdog data */

+

+/****************  Bit definition for DFSDM_CHDATINR register *****************/

+#define DFSDM_CHDATINR_INDAT0_Pos       (0U)

+#define DFSDM_CHDATINR_INDAT0_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */

+#define DFSDM_CHDATINR_INDAT0           DFSDM_CHDATINR_INDAT0_Msk              /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */

+#define DFSDM_CHDATINR_INDAT1_Pos       (16U)

+#define DFSDM_CHDATINR_INDAT1_Msk       (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */

+#define DFSDM_CHDATINR_INDAT1           DFSDM_CHDATINR_INDAT1_Msk              /*!< INDAT0[15:0] Input data for channel y */

+

+/****************  Bit definition for DFSDM_CHDLYR register *****************/

+#define DFSDM_CHDLYR_PLSSKP_Pos         (0U)

+#define DFSDM_CHDLYR_PLSSKP_Msk         (0x3FUL << DFSDM_CHDLYR_PLSSKP_Pos)    /*!< 0x0000003F*/

+#define DFSDM_CHDLYR_PLSSKP             DFSDM_CHDLYR_PLSSKP_Msk

+/************************   DFSDM module registers  ****************************/

+

+/********************  Bit definition for DFSDM_FLTCR1 register *******************/

+#define DFSDM_FLTCR1_AWFSEL_Pos         (30U)

+#define DFSDM_FLTCR1_AWFSEL_Msk         (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos)     /*!< 0x40000000 */

+#define DFSDM_FLTCR1_AWFSEL             DFSDM_FLTCR1_AWFSEL_Msk                /*!< Analog watchdog fast mode select */

+#define DFSDM_FLTCR1_FAST_Pos           (29U)

+#define DFSDM_FLTCR1_FAST_Msk           (0x1UL << DFSDM_FLTCR1_FAST_Pos)       /*!< 0x20000000 */

+#define DFSDM_FLTCR1_FAST               DFSDM_FLTCR1_FAST_Msk                  /*!< Fast conversion mode selection */

+#define DFSDM_FLTCR1_RCH_Pos            (24U)

+#define DFSDM_FLTCR1_RCH_Msk            (0x7UL << DFSDM_FLTCR1_RCH_Pos)        /*!< 0x07000000 */

+#define DFSDM_FLTCR1_RCH                DFSDM_FLTCR1_RCH_Msk                   /*!< RCH[2:0] Regular channel selection */

+#define DFSDM_FLTCR1_RDMAEN_Pos         (21U)

+#define DFSDM_FLTCR1_RDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos)     /*!< 0x00200000 */

+#define DFSDM_FLTCR1_RDMAEN             DFSDM_FLTCR1_RDMAEN_Msk                /*!< DMA channel enabled to read data for the regular conversion */

+#define DFSDM_FLTCR1_RSYNC_Pos          (19U)

+#define DFSDM_FLTCR1_RSYNC_Msk          (0x1UL << DFSDM_FLTCR1_RSYNC_Pos)      /*!< 0x00080000 */

+#define DFSDM_FLTCR1_RSYNC              DFSDM_FLTCR1_RSYNC_Msk                 /*!< Launch regular conversion synchronously with DFSDMx */

+#define DFSDM_FLTCR1_RCONT_Pos          (18U)

+#define DFSDM_FLTCR1_RCONT_Msk          (0x1UL << DFSDM_FLTCR1_RCONT_Pos)      /*!< 0x00040000 */

+#define DFSDM_FLTCR1_RCONT              DFSDM_FLTCR1_RCONT_Msk                 /*!< Continuous mode selection for regular conversions */

+#define DFSDM_FLTCR1_RSWSTART_Pos       (17U)

+#define DFSDM_FLTCR1_RSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos)   /*!< 0x00020000 */

+#define DFSDM_FLTCR1_RSWSTART           DFSDM_FLTCR1_RSWSTART_Msk              /*!< Software start of a conversion on the regular channel */

+#define DFSDM_FLTCR1_JEXTEN_Pos         (13U)

+#define DFSDM_FLTCR1_JEXTEN_Msk         (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos)     /*!< 0x00006000 */

+#define DFSDM_FLTCR1_JEXTEN             DFSDM_FLTCR1_JEXTEN_Msk                /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */

+#define DFSDM_FLTCR1_JEXTEN_1           (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00004000 */

+#define DFSDM_FLTCR1_JEXTEN_0           (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos)      /*!< 0x00002000 */

+#define DFSDM_FLTCR1_JEXTSEL_Pos        (8U)

+#define DFSDM_FLTCR1_JEXTSEL_Msk        (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos)   /*!< 0x00001F00 */

+#define DFSDM_FLTCR1_JEXTSEL            DFSDM_FLTCR1_JEXTSEL_Msk               /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */

+#define DFSDM_FLTCR1_JEXTSEL_0          (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000100 */

+#define DFSDM_FLTCR1_JEXTSEL_1          (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000200 */

+#define DFSDM_FLTCR1_JEXTSEL_2          (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000400 */

+#define DFSDM_FLTCR1_JEXTSEL_3          (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00000800 */

+#define DFSDM_FLTCR1_JEXTSEL_4          (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos)    /*!< 0x00001000 */

+

+#define DFSDM_FLTCR1_JDMAEN_Pos         (5U)

+#define DFSDM_FLTCR1_JDMAEN_Msk         (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos)     /*!< 0x00000020 */

+#define DFSDM_FLTCR1_JDMAEN             DFSDM_FLTCR1_JDMAEN_Msk                /*!< DMA channel enabled to read data for the injected channel group */

+#define DFSDM_FLTCR1_JSCAN_Pos          (4U)

+#define DFSDM_FLTCR1_JSCAN_Msk          (0x1UL << DFSDM_FLTCR1_JSCAN_Pos)      /*!< 0x00000010 */

+#define DFSDM_FLTCR1_JSCAN              DFSDM_FLTCR1_JSCAN_Msk                 /*!< Scanning conversion in continuous mode selection for injected conversions */

+#define DFSDM_FLTCR1_JSYNC_Pos          (3U)

+#define DFSDM_FLTCR1_JSYNC_Msk          (0x1UL << DFSDM_FLTCR1_JSYNC_Pos)      /*!< 0x00000008 */

+#define DFSDM_FLTCR1_JSYNC              DFSDM_FLTCR1_JSYNC_Msk                 /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger  */

+#define DFSDM_FLTCR1_JSWSTART_Pos       (1U)

+#define DFSDM_FLTCR1_JSWSTART_Msk       (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos)   /*!< 0x00000002 */

+#define DFSDM_FLTCR1_JSWSTART           DFSDM_FLTCR1_JSWSTART_Msk              /*!< Start the conversion of the injected group of channels */

+#define DFSDM_FLTCR1_DFEN_Pos           (0U)

+#define DFSDM_FLTCR1_DFEN_Msk           (0x1UL << DFSDM_FLTCR1_DFEN_Pos)       /*!< 0x00000001 */

+#define DFSDM_FLTCR1_DFEN               DFSDM_FLTCR1_DFEN_Msk                  /*!< DFSDM enable */

+

+/********************  Bit definition for DFSDM_FLTCR2 register *******************/

+#define DFSDM_FLTCR2_AWDCH_Pos          (16U)

+#define DFSDM_FLTCR2_AWDCH_Msk          (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos)     /*!< 0x00FF0000 */

+#define DFSDM_FLTCR2_AWDCH              DFSDM_FLTCR2_AWDCH_Msk                 /*!< AWDCH[7:0] Analog watchdog channel selection */

+#define DFSDM_FLTCR2_EXCH_Pos           (8U)

+#define DFSDM_FLTCR2_EXCH_Msk           (0xFFUL << DFSDM_FLTCR2_EXCH_Pos)      /*!< 0x0000FF00 */

+#define DFSDM_FLTCR2_EXCH               DFSDM_FLTCR2_EXCH_Msk                  /*!< EXCH[7:0] Extreme detector channel selection */

+#define DFSDM_FLTCR2_CKABIE_Pos         (6U)

+#define DFSDM_FLTCR2_CKABIE_Msk         (0x1UL << DFSDM_FLTCR2_CKABIE_Pos)     /*!< 0x00000040 */

+#define DFSDM_FLTCR2_CKABIE             DFSDM_FLTCR2_CKABIE_Msk                /*!< Clock absence interrupt enable */

+#define DFSDM_FLTCR2_SCDIE_Pos          (5U)

+#define DFSDM_FLTCR2_SCDIE_Msk          (0x1UL << DFSDM_FLTCR2_SCDIE_Pos)      /*!< 0x00000020 */

+#define DFSDM_FLTCR2_SCDIE              DFSDM_FLTCR2_SCDIE_Msk                 /*!< Short circuit detector interrupt enable */

+#define DFSDM_FLTCR2_AWDIE_Pos          (4U)

+#define DFSDM_FLTCR2_AWDIE_Msk          (0x1UL << DFSDM_FLTCR2_AWDIE_Pos)      /*!< 0x00000010 */

+#define DFSDM_FLTCR2_AWDIE              DFSDM_FLTCR2_AWDIE_Msk                 /*!< Analog watchdog interrupt enable */

+#define DFSDM_FLTCR2_ROVRIE_Pos         (3U)

+#define DFSDM_FLTCR2_ROVRIE_Msk         (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos)     /*!< 0x00000008 */

+#define DFSDM_FLTCR2_ROVRIE             DFSDM_FLTCR2_ROVRIE_Msk                /*!< Regular data overrun interrupt enable */

+#define DFSDM_FLTCR2_JOVRIE_Pos         (2U)

+#define DFSDM_FLTCR2_JOVRIE_Msk         (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos)     /*!< 0x00000004 */

+#define DFSDM_FLTCR2_JOVRIE             DFSDM_FLTCR2_JOVRIE_Msk                /*!< Injected data overrun interrupt enable */

+#define DFSDM_FLTCR2_REOCIE_Pos         (1U)

+#define DFSDM_FLTCR2_REOCIE_Msk         (0x1UL << DFSDM_FLTCR2_REOCIE_Pos)     /*!< 0x00000002 */

+#define DFSDM_FLTCR2_REOCIE             DFSDM_FLTCR2_REOCIE_Msk                /*!< Regular end of conversion interrupt enable */

+#define DFSDM_FLTCR2_JEOCIE_Pos         (0U)

+#define DFSDM_FLTCR2_JEOCIE_Msk         (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos)     /*!< 0x00000001 */

+#define DFSDM_FLTCR2_JEOCIE             DFSDM_FLTCR2_JEOCIE_Msk                /*!< Injected end of conversion interrupt enable */

+

+/********************  Bit definition for DFSDM_FLTISR register *******************/

+#define DFSDM_FLTISR_SCDF_Pos           (24U)

+#define DFSDM_FLTISR_SCDF_Msk           (0xFFUL << DFSDM_FLTISR_SCDF_Pos)      /*!< 0xFF000000 */

+#define DFSDM_FLTISR_SCDF               DFSDM_FLTISR_SCDF_Msk                  /*!< SCDF[7:0] Short circuit detector flag */

+#define DFSDM_FLTISR_CKABF_Pos          (16U)

+#define DFSDM_FLTISR_CKABF_Msk          (0xFFUL << DFSDM_FLTISR_CKABF_Pos)     /*!< 0x00FF0000 */

+#define DFSDM_FLTISR_CKABF              DFSDM_FLTISR_CKABF_Msk                 /*!< CKABF[7:0] Clock absence flag */

+#define DFSDM_FLTISR_RCIP_Pos           (14U)

+#define DFSDM_FLTISR_RCIP_Msk           (0x1UL << DFSDM_FLTISR_RCIP_Pos)       /*!< 0x00004000 */

+#define DFSDM_FLTISR_RCIP               DFSDM_FLTISR_RCIP_Msk                  /*!< Regular conversion in progress status */

+#define DFSDM_FLTISR_JCIP_Pos           (13U)

+#define DFSDM_FLTISR_JCIP_Msk           (0x1UL << DFSDM_FLTISR_JCIP_Pos)       /*!< 0x00002000 */

+#define DFSDM_FLTISR_JCIP               DFSDM_FLTISR_JCIP_Msk                  /*!< Injected conversion in progress status */

+#define DFSDM_FLTISR_AWDF_Pos           (4U)

+#define DFSDM_FLTISR_AWDF_Msk           (0x1UL << DFSDM_FLTISR_AWDF_Pos)       /*!< 0x00000010 */

+#define DFSDM_FLTISR_AWDF               DFSDM_FLTISR_AWDF_Msk                  /*!< Analog watchdog */

+#define DFSDM_FLTISR_ROVRF_Pos          (3U)

+#define DFSDM_FLTISR_ROVRF_Msk          (0x1UL << DFSDM_FLTISR_ROVRF_Pos)      /*!< 0x00000008 */

+#define DFSDM_FLTISR_ROVRF              DFSDM_FLTISR_ROVRF_Msk                 /*!< Regular conversion overrun flag */

+#define DFSDM_FLTISR_JOVRF_Pos          (2U)

+#define DFSDM_FLTISR_JOVRF_Msk          (0x1UL << DFSDM_FLTISR_JOVRF_Pos)      /*!< 0x00000004 */

+#define DFSDM_FLTISR_JOVRF              DFSDM_FLTISR_JOVRF_Msk                 /*!< Injected conversion overrun flag */

+#define DFSDM_FLTISR_REOCF_Pos          (1U)

+#define DFSDM_FLTISR_REOCF_Msk          (0x1UL << DFSDM_FLTISR_REOCF_Pos)      /*!< 0x00000002 */

+#define DFSDM_FLTISR_REOCF              DFSDM_FLTISR_REOCF_Msk                 /*!< End of regular conversion flag */

+#define DFSDM_FLTISR_JEOCF_Pos          (0U)

+#define DFSDM_FLTISR_JEOCF_Msk          (0x1UL << DFSDM_FLTISR_JEOCF_Pos)      /*!< 0x00000001 */

+#define DFSDM_FLTISR_JEOCF              DFSDM_FLTISR_JEOCF_Msk                 /*!< End of injected conversion flag */

+

+/********************  Bit definition for DFSDM_FLTICR register *******************/

+#define DFSDM_FLTICR_CLRSCDF_Pos        (24U)

+#define DFSDM_FLTICR_CLRSCDF_Msk        (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos)   /*!< 0xFF000000 */

+#define DFSDM_FLTICR_CLRSCDF            DFSDM_FLTICR_CLRSCDF_Msk               /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */

+#define DFSDM_FLTICR_CLRCKABF_Pos       (16U)

+#define DFSDM_FLTICR_CLRCKABF_Msk       (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos)  /*!< 0x00FF0000 */

+#define DFSDM_FLTICR_CLRCKABF           DFSDM_FLTICR_CLRCKABF_Msk              /*!< CLRCKABF[7:0] Clear the clock absence flag */

+#define DFSDM_FLTICR_CLRROVRF_Pos       (3U)

+#define DFSDM_FLTICR_CLRROVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos)   /*!< 0x00000008 */

+#define DFSDM_FLTICR_CLRROVRF           DFSDM_FLTICR_CLRROVRF_Msk              /*!< Clear the regular conversion overrun flag */

+#define DFSDM_FLTICR_CLRJOVRF_Pos       (2U)

+#define DFSDM_FLTICR_CLRJOVRF_Msk       (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos)   /*!< 0x00000004 */

+#define DFSDM_FLTICR_CLRJOVRF           DFSDM_FLTICR_CLRJOVRF_Msk              /*!< Clear the injected conversion overrun flag */

+

+/*******************  Bit definition for DFSDM_FLTJCHGR register ******************/

+#define DFSDM_FLTJCHGR_JCHG_Pos         (0U)

+#define DFSDM_FLTJCHGR_JCHG_Msk         (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos)    /*!< 0x000000FF */

+#define DFSDM_FLTJCHGR_JCHG             DFSDM_FLTJCHGR_JCHG_Msk                /*!< JCHG[7:0] Injected channel group selection */

+

+/********************  Bit definition for DFSDM_FLTFCR register *******************/

+#define DFSDM_FLTFCR_FORD_Pos           (29U)

+#define DFSDM_FLTFCR_FORD_Msk           (0x7UL << DFSDM_FLTFCR_FORD_Pos)       /*!< 0xE0000000 */

+#define DFSDM_FLTFCR_FORD               DFSDM_FLTFCR_FORD_Msk                  /*!< FORD[2:0] Sinc filter order */

+#define DFSDM_FLTFCR_FORD_2             (0x4UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x80000000 */

+#define DFSDM_FLTFCR_FORD_1             (0x2UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x40000000 */

+#define DFSDM_FLTFCR_FORD_0             (0x1UL << DFSDM_FLTFCR_FORD_Pos)        /*!< 0x20000000 */

+#define DFSDM_FLTFCR_FOSR_Pos           (16U)

+#define DFSDM_FLTFCR_FOSR_Msk           (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos)     /*!< 0x03FF0000 */

+#define DFSDM_FLTFCR_FOSR               DFSDM_FLTFCR_FOSR_Msk                  /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */

+#define DFSDM_FLTFCR_IOSR_Pos           (0U)

+#define DFSDM_FLTFCR_IOSR_Msk           (0xFFUL << DFSDM_FLTFCR_IOSR_Pos)      /*!< 0x000000FF */

+#define DFSDM_FLTFCR_IOSR               DFSDM_FLTFCR_IOSR_Msk                  /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */

+

+/******************  Bit definition for DFSDM_FLTJDATAR register *****************/

+#define DFSDM_FLTJDATAR_JDATA_Pos       (8U)

+#define DFSDM_FLTJDATAR_JDATA_Msk       (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTJDATAR_JDATA           DFSDM_FLTJDATAR_JDATA_Msk              /*!< JDATA[23:0] Injected group conversion data */

+#define DFSDM_FLTJDATAR_JDATACH_Pos     (0U)

+#define DFSDM_FLTJDATAR_JDATACH_Msk     (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */

+#define DFSDM_FLTJDATAR_JDATACH         DFSDM_FLTJDATAR_JDATACH_Msk            /*!< JDATACH[2:0] Injected channel most recently converted */

+

+/******************  Bit definition for DFSDM_FLTRDATAR register *****************/

+#define DFSDM_FLTRDATAR_RDATA_Pos       (8U)

+#define DFSDM_FLTRDATAR_RDATA_Msk       (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTRDATAR_RDATA           DFSDM_FLTRDATAR_RDATA_Msk              /*!< RDATA[23:0] Regular channel conversion data */

+#define DFSDM_FLTRDATAR_RPEND_Pos       (4U)

+#define DFSDM_FLTRDATAR_RPEND_Msk       (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos)   /*!< 0x00000010 */

+#define DFSDM_FLTRDATAR_RPEND           DFSDM_FLTRDATAR_RPEND_Msk              /*!< RPEND Regular channel pending data */

+#define DFSDM_FLTRDATAR_RDATACH_Pos     (0U)

+#define DFSDM_FLTRDATAR_RDATACH_Msk     (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */

+#define DFSDM_FLTRDATAR_RDATACH         DFSDM_FLTRDATAR_RDATACH_Msk            /*!< RDATACH[2:0] Regular channel most recently converted */

+

+/******************  Bit definition for DFSDM_FLTAWHTR register ******************/

+#define DFSDM_FLTAWHTR_AWHT_Pos         (8U)

+#define DFSDM_FLTAWHTR_AWHT_Msk         (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTAWHTR_AWHT             DFSDM_FLTAWHTR_AWHT_Msk                /*!< AWHT[23:0] Analog watchdog high threshold */

+#define DFSDM_FLTAWHTR_BKAWH_Pos        (0U)

+#define DFSDM_FLTAWHTR_BKAWH_Msk        (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos)    /*!< 0x0000000F */

+#define DFSDM_FLTAWHTR_BKAWH            DFSDM_FLTAWHTR_BKAWH_Msk               /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */

+

+/******************  Bit definition for DFSDM_FLTAWLTR register ******************/

+#define DFSDM_FLTAWLTR_AWLT_Pos         (8U)

+#define DFSDM_FLTAWLTR_AWLT_Msk         (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTAWLTR_AWLT             DFSDM_FLTAWLTR_AWLT_Msk                /*!< AWHT[23:0] Analog watchdog low threshold */

+#define DFSDM_FLTAWLTR_BKAWL_Pos        (0U)

+#define DFSDM_FLTAWLTR_BKAWL_Msk        (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos)    /*!< 0x0000000F */

+#define DFSDM_FLTAWLTR_BKAWL            DFSDM_FLTAWLTR_BKAWL_Msk               /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */

+

+/******************  Bit definition for DFSDM_FLTAWSR register ******************/

+#define DFSDM_FLTAWSR_AWHTF_Pos         (8U)

+#define DFSDM_FLTAWSR_AWHTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos)    /*!< 0x0000FF00 */

+#define DFSDM_FLTAWSR_AWHTF             DFSDM_FLTAWSR_AWHTF_Msk                /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */

+#define DFSDM_FLTAWSR_AWLTF_Pos         (0U)

+#define DFSDM_FLTAWSR_AWLTF_Msk         (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos)    /*!< 0x000000FF */

+#define DFSDM_FLTAWSR_AWLTF             DFSDM_FLTAWSR_AWLTF_Msk                /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */

+

+/******************  Bit definition for DFSDM_FLTAWCFR) register *****************/

+#define DFSDM_FLTAWCFR_CLRAWHTF_Pos     (8U)

+#define DFSDM_FLTAWCFR_CLRAWHTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */

+#define DFSDM_FLTAWCFR_CLRAWHTF         DFSDM_FLTAWCFR_CLRAWHTF_Msk            /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */

+#define DFSDM_FLTAWCFR_CLRAWLTF_Pos     (0U)

+#define DFSDM_FLTAWCFR_CLRAWLTF_Msk     (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */

+#define DFSDM_FLTAWCFR_CLRAWLTF         DFSDM_FLTAWCFR_CLRAWLTF_Msk            /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */

+

+/******************  Bit definition for DFSDM_FLTEXMAX register ******************/

+#define DFSDM_FLTEXMAX_EXMAX_Pos        (8U)

+#define DFSDM_FLTEXMAX_EXMAX_Msk        (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTEXMAX_EXMAX            DFSDM_FLTEXMAX_EXMAX_Msk               /*!< EXMAX[23:0] Extreme detector maximum value */

+#define DFSDM_FLTEXMAX_EXMAXCH_Pos      (0U)

+#define DFSDM_FLTEXMAX_EXMAXCH_Msk      (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos)  /*!< 0x00000007 */

+#define DFSDM_FLTEXMAX_EXMAXCH          DFSDM_FLTEXMAX_EXMAXCH_Msk             /*!< EXMAXCH[2:0] Extreme detector maximum data channel */

+

+/******************  Bit definition for DFSDM_FLTEXMIN register ******************/

+#define DFSDM_FLTEXMIN_EXMIN_Pos        (8U)

+#define DFSDM_FLTEXMIN_EXMIN_Msk        (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */

+#define DFSDM_FLTEXMIN_EXMIN            DFSDM_FLTEXMIN_EXMIN_Msk               /*!< EXMIN[23:0] Extreme detector minimum value */

+#define DFSDM_FLTEXMIN_EXMINCH_Pos      (0U)

+#define DFSDM_FLTEXMIN_EXMINCH_Msk      (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos)  /*!< 0x00000007 */

+#define DFSDM_FLTEXMIN_EXMINCH          DFSDM_FLTEXMIN_EXMINCH_Msk             /*!< EXMINCH[2:0] Extreme detector minimum data channel */

+

+/******************  Bit definition for DFSDM_FLTCNVTIMR register ******************/

+#define DFSDM_FLTCNVTIMR_CNVCNT_Pos     (4U)

+#define DFSDM_FLTCNVTIMR_CNVCNT_Msk     (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */

+#define DFSDM_FLTCNVTIMR_CNVCNT         DFSDM_FLTCNVTIMR_CNVCNT_Msk            /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           BDMA Controller                                  */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for BDMA_ISR register  ********************/

+#define BDMA_ISR_GIF0_Pos       (0U)

+#define BDMA_ISR_GIF0_Msk       (0x1UL << BDMA_ISR_GIF0_Pos)                   /*!< 0x00000001 */

+#define BDMA_ISR_GIF0           BDMA_ISR_GIF0_Msk                              /*!< Channel 0 Global interrupt flag */

+#define BDMA_ISR_TCIF0_Pos      (1U)

+#define BDMA_ISR_TCIF0_Msk      (0x1UL << BDMA_ISR_TCIF0_Pos)                  /*!< 0x00000002 */

+#define BDMA_ISR_TCIF0          BDMA_ISR_TCIF0_Msk                             /*!< Channel 0 Transfer Complete flag */

+#define BDMA_ISR_HTIF0_Pos      (2U)

+#define BDMA_ISR_HTIF0_Msk      (0x1UL << BDMA_ISR_HTIF0_Pos)                  /*!< 0x00000004 */

+#define BDMA_ISR_HTIF0          BDMA_ISR_HTIF0_Msk                             /*!< Channel 0 Half Transfer flag */

+#define BDMA_ISR_TEIF0_Pos      (3U)

+#define BDMA_ISR_TEIF0_Msk      (0x1UL << BDMA_ISR_TEIF0_Pos)                  /*!< 0x00000008 */

+#define BDMA_ISR_TEIF0          BDMA_ISR_TEIF0_Msk                             /*!< Channel 0 Transfer Error flag */

+#define BDMA_ISR_GIF1_Pos       (4U)

+#define BDMA_ISR_GIF1_Msk       (0x1UL << BDMA_ISR_GIF1_Pos)                   /*!< 0x00000010 */

+#define BDMA_ISR_GIF1           BDMA_ISR_GIF1_Msk                              /*!< Channel 1 Global interrupt flag */

+#define BDMA_ISR_TCIF1_Pos      (5U)

+#define BDMA_ISR_TCIF1_Msk      (0x1UL << BDMA_ISR_TCIF1_Pos)                  /*!< 0x00000020 */

+#define BDMA_ISR_TCIF1          BDMA_ISR_TCIF1_Msk                             /*!< Channel 1 Transfer Complete flag */

+#define BDMA_ISR_HTIF1_Pos      (6U)

+#define BDMA_ISR_HTIF1_Msk      (0x1UL << BDMA_ISR_HTIF1_Pos)                  /*!< 0x00000040 */

+#define BDMA_ISR_HTIF1          BDMA_ISR_HTIF1_Msk                             /*!< Channel 1 Half Transfer flag */

+#define BDMA_ISR_TEIF1_Pos      (7U)

+#define BDMA_ISR_TEIF1_Msk      (0x1UL << BDMA_ISR_TEIF1_Pos)                  /*!< 0x00000080 */

+#define BDMA_ISR_TEIF1          BDMA_ISR_TEIF1_Msk                             /*!< Channel 1 Transfer Error flag */

+#define BDMA_ISR_GIF2_Pos       (8U)

+#define BDMA_ISR_GIF2_Msk       (0x1UL << BDMA_ISR_GIF2_Pos)                   /*!< 0x00000100 */

+#define BDMA_ISR_GIF2           BDMA_ISR_GIF2_Msk                              /*!< Channel 2 Global interrupt flag */

+#define BDMA_ISR_TCIF2_Pos      (9U)

+#define BDMA_ISR_TCIF2_Msk      (0x1UL << BDMA_ISR_TCIF2_Pos)                  /*!< 0x00000200 */

+#define BDMA_ISR_TCIF2          BDMA_ISR_TCIF2_Msk                             /*!< Channel 2 Transfer Complete flag */

+#define BDMA_ISR_HTIF2_Pos      (10U)

+#define BDMA_ISR_HTIF2_Msk      (0x1UL << BDMA_ISR_HTIF2_Pos)                  /*!< 0x00000400 */

+#define BDMA_ISR_HTIF2          BDMA_ISR_HTIF2_Msk                             /*!< Channel 2 Half Transfer flag */

+#define BDMA_ISR_TEIF2_Pos      (11U)

+#define BDMA_ISR_TEIF2_Msk      (0x1UL << BDMA_ISR_TEIF2_Pos)                  /*!< 0x00000800 */

+#define BDMA_ISR_TEIF2          BDMA_ISR_TEIF2_Msk                             /*!< Channel 2 Transfer Error flag */

+#define BDMA_ISR_GIF3_Pos       (12U)

+#define BDMA_ISR_GIF3_Msk       (0x1UL << BDMA_ISR_GIF3_Pos)                   /*!< 0x00001000 */

+#define BDMA_ISR_GIF3           BDMA_ISR_GIF3_Msk                              /*!< Channel 3 Global interrupt flag */

+#define BDMA_ISR_TCIF3_Pos      (13U)

+#define BDMA_ISR_TCIF3_Msk      (0x1UL << BDMA_ISR_TCIF3_Pos)                  /*!< 0x00002000 */

+#define BDMA_ISR_TCIF3          BDMA_ISR_TCIF3_Msk                             /*!< Channel 3 Transfer Complete flag */

+#define BDMA_ISR_HTIF3_Pos      (14U)

+#define BDMA_ISR_HTIF3_Msk      (0x1UL << BDMA_ISR_HTIF3_Pos)                  /*!< 0x00004000 */

+#define BDMA_ISR_HTIF3          BDMA_ISR_HTIF3_Msk                             /*!< Channel 3 Half Transfer flag */

+#define BDMA_ISR_TEIF3_Pos      (15U)

+#define BDMA_ISR_TEIF3_Msk      (0x1UL << BDMA_ISR_TEIF3_Pos)                  /*!< 0x00008000 */

+#define BDMA_ISR_TEIF3          BDMA_ISR_TEIF3_Msk                             /*!< Channel 3 Transfer Error flag */

+#define BDMA_ISR_GIF4_Pos       (16U)

+#define BDMA_ISR_GIF4_Msk       (0x1UL << BDMA_ISR_GIF4_Pos)                   /*!< 0x00010000 */

+#define BDMA_ISR_GIF4           BDMA_ISR_GIF4_Msk                              /*!< Channel 4 Global interrupt flag */

+#define BDMA_ISR_TCIF4_Pos      (17U)

+#define BDMA_ISR_TCIF4_Msk      (0x1UL << BDMA_ISR_TCIF4_Pos)                  /*!< 0x00020000 */

+#define BDMA_ISR_TCIF4          BDMA_ISR_TCIF4_Msk                             /*!< Channel 4 Transfer Complete flag */

+#define BDMA_ISR_HTIF4_Pos      (18U)

+#define BDMA_ISR_HTIF4_Msk      (0x1UL << BDMA_ISR_HTIF4_Pos)                  /*!< 0x00040000 */

+#define BDMA_ISR_HTIF4          BDMA_ISR_HTIF4_Msk                             /*!< Channel 4 Half Transfer flag */

+#define BDMA_ISR_TEIF4_Pos      (19U)

+#define BDMA_ISR_TEIF4_Msk      (0x1UL << BDMA_ISR_TEIF4_Pos)                  /*!< 0x00080000 */

+#define BDMA_ISR_TEIF4          BDMA_ISR_TEIF4_Msk                             /*!< Channel 4 Transfer Error flag */

+#define BDMA_ISR_GIF5_Pos       (20U)

+#define BDMA_ISR_GIF5_Msk       (0x1UL << BDMA_ISR_GIF5_Pos)                   /*!< 0x00100000 */

+#define BDMA_ISR_GIF5           BDMA_ISR_GIF5_Msk                              /*!< Channel 5 Global interrupt flag */

+#define BDMA_ISR_TCIF5_Pos      (21U)

+#define BDMA_ISR_TCIF5_Msk      (0x1UL << BDMA_ISR_TCIF5_Pos)                  /*!< 0x00200000 */

+#define BDMA_ISR_TCIF5          BDMA_ISR_TCIF5_Msk                             /*!< Channel 5 Transfer Complete flag */

+#define BDMA_ISR_HTIF5_Pos      (22U)

+#define BDMA_ISR_HTIF5_Msk      (0x1UL << BDMA_ISR_HTIF5_Pos)                  /*!< 0x00400000 */

+#define BDMA_ISR_HTIF5          BDMA_ISR_HTIF5_Msk                             /*!< Channel 5 Half Transfer flag */

+#define BDMA_ISR_TEIF5_Pos      (23U)

+#define BDMA_ISR_TEIF5_Msk      (0x1UL << BDMA_ISR_TEIF5_Pos)                  /*!< 0x00800000 */

+#define BDMA_ISR_TEIF5          BDMA_ISR_TEIF5_Msk                             /*!< Channel 5 Transfer Error flag */

+#define BDMA_ISR_GIF6_Pos       (24U)

+#define BDMA_ISR_GIF6_Msk       (0x1UL << BDMA_ISR_GIF6_Pos)                   /*!< 0x01000000 */

+#define BDMA_ISR_GIF6           BDMA_ISR_GIF6_Msk                              /*!< Channel 6 Global interrupt flag */

+#define BDMA_ISR_TCIF6_Pos      (25U)

+#define BDMA_ISR_TCIF6_Msk      (0x1UL << BDMA_ISR_TCIF6_Pos)                  /*!< 0x02000000 */

+#define BDMA_ISR_TCIF6          BDMA_ISR_TCIF6_Msk                             /*!< Channel 6 Transfer Complete flag */

+#define BDMA_ISR_HTIF6_Pos      (26U)

+#define BDMA_ISR_HTIF6_Msk      (0x1UL << BDMA_ISR_HTIF6_Pos)                  /*!< 0x04000000 */

+#define BDMA_ISR_HTIF6          BDMA_ISR_HTIF6_Msk                             /*!< Channel 6 Half Transfer flag */

+#define BDMA_ISR_TEIF6_Pos      (27U)

+#define BDMA_ISR_TEIF6_Msk      (0x1UL << BDMA_ISR_TEIF6_Pos)                  /*!< 0x08000000 */

+#define BDMA_ISR_TEIF6          BDMA_ISR_TEIF6_Msk                             /*!< Channel 6 Transfer Error flag */

+#define BDMA_ISR_GIF7_Pos       (28U)

+#define BDMA_ISR_GIF7_Msk       (0x1UL << BDMA_ISR_GIF7_Pos)                   /*!< 0x10000000 */

+#define BDMA_ISR_GIF7           BDMA_ISR_GIF7_Msk                              /*!< Channel 7 Global interrupt flag */

+#define BDMA_ISR_TCIF7_Pos      (29U)

+#define BDMA_ISR_TCIF7_Msk      (0x1UL << BDMA_ISR_TCIF7_Pos)                  /*!< 0x20000000 */

+#define BDMA_ISR_TCIF7          BDMA_ISR_TCIF7_Msk                             /*!< Channel 7 Transfer Complete flag */

+#define BDMA_ISR_HTIF7_Pos      (30U)

+#define BDMA_ISR_HTIF7_Msk      (0x1UL << BDMA_ISR_HTIF7_Pos)                  /*!< 0x40000000 */

+#define BDMA_ISR_HTIF7          BDMA_ISR_HTIF7_Msk                             /*!< Channel 7 Half Transfer flag */

+#define BDMA_ISR_TEIF7_Pos      (31U)

+#define BDMA_ISR_TEIF7_Msk      (0x1UL << BDMA_ISR_TEIF7_Pos)                  /*!< 0x80000000 */

+#define BDMA_ISR_TEIF7          BDMA_ISR_TEIF7_Msk                             /*!< Channel 7 Transfer Error flag */

+

+/*******************  Bit definition for BDMA_IFCR register  *******************/

+#define BDMA_IFCR_CGIF0_Pos     (0U)

+#define BDMA_IFCR_CGIF0_Msk     (0x1UL << BDMA_IFCR_CGIF0_Pos)                 /*!< 0x00000001 */

+#define BDMA_IFCR_CGIF0         BDMA_IFCR_CGIF0_Msk                            /*!< Channel 0 Global interrupt clearr */

+#define BDMA_IFCR_CTCIF0_Pos    (1U)

+#define BDMA_IFCR_CTCIF0_Msk    (0x1UL << BDMA_IFCR_CTCIF0_Pos)                /*!< 0x00000002 */

+#define BDMA_IFCR_CTCIF0        BDMA_IFCR_CTCIF0_Msk                           /*!< Channel 0 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF0_Pos    (2U)

+#define BDMA_IFCR_CHTIF0_Msk    (0x1UL << BDMA_IFCR_CHTIF0_Pos)                /*!< 0x00000004 */

+#define BDMA_IFCR_CHTIF0        BDMA_IFCR_CHTIF0_Msk                           /*!< Channel 0 Half Transfer clear */

+#define BDMA_IFCR_CTEIF0_Pos    (3U)

+#define BDMA_IFCR_CTEIF0_Msk    (0x1UL << BDMA_IFCR_CTEIF0_Pos)                /*!< 0x00000008 */

+#define BDMA_IFCR_CTEIF0        BDMA_IFCR_CTEIF0_Msk                           /*!< Channel 0 Transfer Error clear */

+#define BDMA_IFCR_CGIF1_Pos     (4U)

+#define BDMA_IFCR_CGIF1_Msk     (0x1UL << BDMA_IFCR_CGIF1_Pos)                 /*!< 0x00000010 */

+#define BDMA_IFCR_CGIF1         BDMA_IFCR_CGIF1_Msk                            /*!< Channel 1 Global interrupt clear */

+#define BDMA_IFCR_CTCIF1_Pos    (5U)

+#define BDMA_IFCR_CTCIF1_Msk    (0x1UL << BDMA_IFCR_CTCIF1_Pos)                /*!< 0x00000020 */

+#define BDMA_IFCR_CTCIF1        BDMA_IFCR_CTCIF1_Msk                           /*!< Channel 1 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF1_Pos    (6U)

+#define BDMA_IFCR_CHTIF1_Msk    (0x1UL << BDMA_IFCR_CHTIF1_Pos)                /*!< 0x00000040 */

+#define BDMA_IFCR_CHTIF1        BDMA_IFCR_CHTIF1_Msk                           /*!< Channel 1 Half Transfer clear */

+#define BDMA_IFCR_CTEIF1_Pos    (7U)

+#define BDMA_IFCR_CTEIF1_Msk    (0x1UL << BDMA_IFCR_CTEIF1_Pos)                /*!< 0x00000080 */

+#define BDMA_IFCR_CTEIF1        BDMA_IFCR_CTEIF1_Msk                           /*!< Channel 1 Transfer Error clear */

+#define BDMA_IFCR_CGIF2_Pos     (8U)

+#define BDMA_IFCR_CGIF2_Msk     (0x1UL << BDMA_IFCR_CGIF2_Pos)                 /*!< 0x00000100 */

+#define BDMA_IFCR_CGIF2         BDMA_IFCR_CGIF2_Msk                            /*!< Channel 2 Global interrupt clear */

+#define BDMA_IFCR_CTCIF2_Pos    (9U)

+#define BDMA_IFCR_CTCIF2_Msk    (0x1UL << BDMA_IFCR_CTCIF2_Pos)                /*!< 0x00000200 */

+#define BDMA_IFCR_CTCIF2        BDMA_IFCR_CTCIF2_Msk                           /*!< Channel 2 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF2_Pos    (10U)

+#define BDMA_IFCR_CHTIF2_Msk    (0x1UL << BDMA_IFCR_CHTIF2_Pos)                /*!< 0x00000400 */

+#define BDMA_IFCR_CHTIF2        BDMA_IFCR_CHTIF2_Msk                           /*!< Channel 2 Half Transfer clear */

+#define BDMA_IFCR_CTEIF2_Pos    (11U)

+#define BDMA_IFCR_CTEIF2_Msk    (0x1UL << BDMA_IFCR_CTEIF2_Pos)                /*!< 0x00000800 */

+#define BDMA_IFCR_CTEIF2        BDMA_IFCR_CTEIF2_Msk                           /*!< Channel 2 Transfer Error clear */

+#define BDMA_IFCR_CGIF3_Pos     (12U)

+#define BDMA_IFCR_CGIF3_Msk     (0x1UL << BDMA_IFCR_CGIF3_Pos)                 /*!< 0x00001000 */

+#define BDMA_IFCR_CGIF3         BDMA_IFCR_CGIF3_Msk                            /*!< Channel 3 Global interrupt clear */

+#define BDMA_IFCR_CTCIF3_Pos    (13U)

+#define BDMA_IFCR_CTCIF3_Msk    (0x1UL << BDMA_IFCR_CTCIF3_Pos)                /*!< 0x00002000 */

+#define BDMA_IFCR_CTCIF3        BDMA_IFCR_CTCIF3_Msk                           /*!< Channel 3 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF3_Pos    (14U)

+#define BDMA_IFCR_CHTIF3_Msk    (0x1UL << BDMA_IFCR_CHTIF3_Pos)                /*!< 0x00004000 */

+#define BDMA_IFCR_CHTIF3        BDMA_IFCR_CHTIF3_Msk                           /*!< Channel 3 Half Transfer clear */

+#define BDMA_IFCR_CTEIF3_Pos    (15U)

+#define BDMA_IFCR_CTEIF3_Msk    (0x1UL << BDMA_IFCR_CTEIF3_Pos)                /*!< 0x00008000 */

+#define BDMA_IFCR_CTEIF3        BDMA_IFCR_CTEIF3_Msk                           /*!< Channel 3 Transfer Error clear */

+#define BDMA_IFCR_CGIF4_Pos     (16U)

+#define BDMA_IFCR_CGIF4_Msk     (0x1UL << BDMA_IFCR_CGIF4_Pos)                 /*!< 0x00010000 */

+#define BDMA_IFCR_CGIF4         BDMA_IFCR_CGIF4_Msk                            /*!< Channel 4 Global interrupt clear */

+#define BDMA_IFCR_CTCIF4_Pos    (17U)

+#define BDMA_IFCR_CTCIF4_Msk    (0x1UL << BDMA_IFCR_CTCIF4_Pos)                /*!< 0x00020000 */

+#define BDMA_IFCR_CTCIF4        BDMA_IFCR_CTCIF4_Msk                           /*!< Channel 4 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF4_Pos    (18U)

+#define BDMA_IFCR_CHTIF4_Msk    (0x1UL << BDMA_IFCR_CHTIF4_Pos)                /*!< 0x00040000 */

+#define BDMA_IFCR_CHTIF4        BDMA_IFCR_CHTIF4_Msk                           /*!< Channel 4 Half Transfer clear */

+#define BDMA_IFCR_CTEIF4_Pos    (19U)

+#define BDMA_IFCR_CTEIF4_Msk    (0x1UL << BDMA_IFCR_CTEIF4_Pos)                /*!< 0x00080000 */

+#define BDMA_IFCR_CTEIF4        BDMA_IFCR_CTEIF4_Msk                           /*!< Channel 4 Transfer Error clear */

+#define BDMA_IFCR_CGIF5_Pos     (20U)

+#define BDMA_IFCR_CGIF5_Msk     (0x1UL << BDMA_IFCR_CGIF5_Pos)                 /*!< 0x00100000 */

+#define BDMA_IFCR_CGIF5         BDMA_IFCR_CGIF5_Msk                            /*!< Channel 5 Global interrupt clear */

+#define BDMA_IFCR_CTCIF5_Pos    (21U)

+#define BDMA_IFCR_CTCIF5_Msk    (0x1UL << BDMA_IFCR_CTCIF5_Pos)                /*!< 0x00200000 */

+#define BDMA_IFCR_CTCIF5        BDMA_IFCR_CTCIF5_Msk                           /*!< Channel 5 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF5_Pos    (22U)

+#define BDMA_IFCR_CHTIF5_Msk    (0x1UL << BDMA_IFCR_CHTIF5_Pos)                /*!< 0x00400000 */

+#define BDMA_IFCR_CHTIF5        BDMA_IFCR_CHTIF5_Msk                           /*!< Channel 5 Half Transfer clear */

+#define BDMA_IFCR_CTEIF5_Pos    (23U)

+#define BDMA_IFCR_CTEIF5_Msk    (0x1UL << BDMA_IFCR_CTEIF5_Pos)                /*!< 0x00800000 */

+#define BDMA_IFCR_CTEIF5        BDMA_IFCR_CTEIF5_Msk                           /*!< Channel 5 Transfer Error clear */

+#define BDMA_IFCR_CGIF6_Pos     (24U)

+#define BDMA_IFCR_CGIF6_Msk     (0x1UL << BDMA_IFCR_CGIF6_Pos)                 /*!< 0x01000000 */

+#define BDMA_IFCR_CGIF6         BDMA_IFCR_CGIF6_Msk                            /*!< Channel 6 Global interrupt clear */

+#define BDMA_IFCR_CTCIF6_Pos    (25U)

+#define BDMA_IFCR_CTCIF6_Msk    (0x1UL << BDMA_IFCR_CTCIF6_Pos)                /*!< 0x02000000 */

+#define BDMA_IFCR_CTCIF6        BDMA_IFCR_CTCIF6_Msk                           /*!< Channel 6 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF6_Pos    (26U)

+#define BDMA_IFCR_CHTIF6_Msk    (0x1UL << BDMA_IFCR_CHTIF6_Pos)                /*!< 0x04000000 */

+#define BDMA_IFCR_CHTIF6        BDMA_IFCR_CHTIF6_Msk                           /*!< Channel 6 Half Transfer clear */

+#define BDMA_IFCR_CTEIF6_Pos    (27U)

+#define BDMA_IFCR_CTEIF6_Msk    (0x1UL << BDMA_IFCR_CTEIF6_Pos)                /*!< 0x08000000 */

+#define BDMA_IFCR_CTEIF6        BDMA_IFCR_CTEIF6_Msk                           /*!< Channel 6 Transfer Error clear */

+#define BDMA_IFCR_CGIF7_Pos     (28U)

+#define BDMA_IFCR_CGIF7_Msk     (0x1UL << BDMA_IFCR_CGIF7_Pos)                 /*!< 0x10000000 */

+#define BDMA_IFCR_CGIF7         BDMA_IFCR_CGIF7_Msk                            /*!< Channel 7 Global interrupt clear */

+#define BDMA_IFCR_CTCIF7_Pos    (29U)

+#define BDMA_IFCR_CTCIF7_Msk    (0x1UL << BDMA_IFCR_CTCIF7_Pos)                /*!< 0x20000000 */

+#define BDMA_IFCR_CTCIF7        BDMA_IFCR_CTCIF7_Msk                           /*!< Channel 7 Transfer Complete clear */

+#define BDMA_IFCR_CHTIF7_Pos    (30U)

+#define BDMA_IFCR_CHTIF7_Msk    (0x1UL << BDMA_IFCR_CHTIF7_Pos)                /*!< 0x40000000 */

+#define BDMA_IFCR_CHTIF7        BDMA_IFCR_CHTIF7_Msk                           /*!< Channel 7 Half Transfer clear */

+#define BDMA_IFCR_CTEIF7_Pos    (31U)

+#define BDMA_IFCR_CTEIF7_Msk    (0x1UL << BDMA_IFCR_CTEIF7_Pos)                /*!< 0x80000000 */

+#define BDMA_IFCR_CTEIF7        BDMA_IFCR_CTEIF7_Msk                           /*!< Channel 7 Transfer Error clear */

+

+/*******************  Bit definition for BDMA_CCR register  ********************/

+#define BDMA_CCR_EN_Pos         (0U)

+#define BDMA_CCR_EN_Msk         (0x1UL << BDMA_CCR_EN_Pos)                     /*!< 0x00000001 */

+#define BDMA_CCR_EN             BDMA_CCR_EN_Msk                                /*!< Channel enable                      */

+#define BDMA_CCR_TCIE_Pos       (1U)

+#define BDMA_CCR_TCIE_Msk       (0x1UL << BDMA_CCR_TCIE_Pos)                   /*!< 0x00000002 */

+#define BDMA_CCR_TCIE           BDMA_CCR_TCIE_Msk                              /*!< Transfer complete interrupt enable  */

+#define BDMA_CCR_HTIE_Pos       (2U)

+#define BDMA_CCR_HTIE_Msk       (0x1UL << BDMA_CCR_HTIE_Pos)                   /*!< 0x00000004 */

+#define BDMA_CCR_HTIE           BDMA_CCR_HTIE_Msk                              /*!< Half Transfer interrupt enable      */

+#define BDMA_CCR_TEIE_Pos       (3U)

+#define BDMA_CCR_TEIE_Msk       (0x1UL << BDMA_CCR_TEIE_Pos)                   /*!< 0x00000008 */

+#define BDMA_CCR_TEIE           BDMA_CCR_TEIE_Msk                              /*!< Transfer error interrupt enable     */

+#define BDMA_CCR_DIR_Pos        (4U)

+#define BDMA_CCR_DIR_Msk        (0x1UL << BDMA_CCR_DIR_Pos)                    /*!< 0x00000010 */

+#define BDMA_CCR_DIR            BDMA_CCR_DIR_Msk                               /*!< Data transfer direction             */

+#define BDMA_CCR_CIRC_Pos       (5U)

+#define BDMA_CCR_CIRC_Msk       (0x1UL << BDMA_CCR_CIRC_Pos)                   /*!< 0x00000020 */

+#define BDMA_CCR_CIRC           BDMA_CCR_CIRC_Msk                              /*!< Circular mode                       */

+#define BDMA_CCR_PINC_Pos       (6U)

+#define BDMA_CCR_PINC_Msk       (0x1UL << BDMA_CCR_PINC_Pos)                   /*!< 0x00000040 */

+#define BDMA_CCR_PINC           BDMA_CCR_PINC_Msk                              /*!< Peripheral increment mode           */

+#define BDMA_CCR_MINC_Pos       (7U)

+#define BDMA_CCR_MINC_Msk       (0x1UL << BDMA_CCR_MINC_Pos)                   /*!< 0x00000080 */

+#define BDMA_CCR_MINC           BDMA_CCR_MINC_Msk                              /*!< Memory increment mode               */

+

+#define BDMA_CCR_PSIZE_Pos      (8U)

+#define BDMA_CCR_PSIZE_Msk      (0x3UL << BDMA_CCR_PSIZE_Pos)                  /*!< 0x00000300 */

+#define BDMA_CCR_PSIZE          BDMA_CCR_PSIZE_Msk                             /*!< PSIZE[1:0] bits (Peripheral size)   */

+#define BDMA_CCR_PSIZE_0        (0x1UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000100 */

+#define BDMA_CCR_PSIZE_1        (0x2UL << BDMA_CCR_PSIZE_Pos)                   /*!< 0x00000200 */

+

+#define BDMA_CCR_MSIZE_Pos      (10U)

+#define BDMA_CCR_MSIZE_Msk      (0x3UL << BDMA_CCR_MSIZE_Pos)                  /*!< 0x00000C00 */

+#define BDMA_CCR_MSIZE          BDMA_CCR_MSIZE_Msk                             /*!< MSIZE[1:0] bits (Memory size)       */

+#define BDMA_CCR_MSIZE_0        (0x1UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000400 */

+#define BDMA_CCR_MSIZE_1        (0x2UL << BDMA_CCR_MSIZE_Pos)                   /*!< 0x00000800 */

+

+#define BDMA_CCR_PL_Pos         (12U)

+#define BDMA_CCR_PL_Msk         (0x3UL << BDMA_CCR_PL_Pos)                     /*!< 0x00003000 */

+#define BDMA_CCR_PL             BDMA_CCR_PL_Msk                                /*!< PL[1:0] bits(Channel Priority level)*/

+#define BDMA_CCR_PL_0           (0x1UL << BDMA_CCR_PL_Pos)                      /*!< 0x00001000 */

+#define BDMA_CCR_PL_1           (0x2UL << BDMA_CCR_PL_Pos)                      /*!< 0x00002000 */

+

+#define BDMA_CCR_MEM2MEM_Pos    (14U)

+#define BDMA_CCR_MEM2MEM_Msk    (0x1UL << BDMA_CCR_MEM2MEM_Pos)                /*!< 0x00004000 */

+#define BDMA_CCR_MEM2MEM        BDMA_CCR_MEM2MEM_Msk                           /*!< Memory to memory mode               */

+#define BDMA_CCR_DBM_Pos        (15U)

+#define BDMA_CCR_DBM_Msk        (0x1UL << BDMA_CCR_DBM_Pos)                    /*!< 0x0000A000 */

+#define BDMA_CCR_DBM            BDMA_CCR_DBM_Msk                               /*!< Memory to memory mode               */

+#define BDMA_CCR_CT_Pos         (16U)

+#define BDMA_CCR_CT_Msk         (0x1UL << BDMA_CCR_CT_Pos)                     /*!< 0x00010000 */

+#define BDMA_CCR_CT             BDMA_CCR_CT_Msk                                /*!< Memory to memory mode               */

+

+/******************  Bit definition for BDMA_CNDTR register  *******************/

+#define BDMA_CNDTR_NDT_Pos      (0U)

+#define BDMA_CNDTR_NDT_Msk      (0xFFFFUL << BDMA_CNDTR_NDT_Pos)               /*!< 0x0000FFFF */

+#define BDMA_CNDTR_NDT          BDMA_CNDTR_NDT_Msk                             /*!< Number of data to Transfer          */

+

+/******************  Bit definition for BDMA_CPAR register  ********************/

+#define BDMA_CPAR_PA_Pos        (0U)

+#define BDMA_CPAR_PA_Msk        (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CPAR_PA            BDMA_CPAR_PA_Msk                               /*!< Peripheral Address                  */

+

+/******************  Bit definition for BDMA_CM0AR register  ********************/

+#define BDMA_CM0AR_MA_Pos        (0U)

+#define BDMA_CM0AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CM0AR_MA            BDMA_CM0AR_MA_Msk                               /*!< Memory Address                      */

+

+/******************  Bit definition for BDMA_CM1AR register  ********************/

+#define BDMA_CM1AR_MA_Pos        (0U)

+#define BDMA_CM1AR_MA_Msk        (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos)             /*!< 0xFFFFFFFF */

+#define BDMA_CM1AR_MA            BDMA_CM1AR_MA_Msk                               /*!< Memory Address                      */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             DMA Controller                                 */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DMA_SxCR register  *****************/

+#define DMA_SxCR_MBURST_Pos      (23U)

+#define DMA_SxCR_MBURST_Msk      (0x3UL << DMA_SxCR_MBURST_Pos)                /*!< 0x01800000 */

+#define DMA_SxCR_MBURST          DMA_SxCR_MBURST_Msk                           /*!< Memory burst transfer configuration */

+#define DMA_SxCR_MBURST_0        (0x1UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x00800000 */

+#define DMA_SxCR_MBURST_1        (0x2UL << DMA_SxCR_MBURST_Pos)                 /*!< 0x01000000 */

+#define DMA_SxCR_PBURST_Pos      (21U)

+#define DMA_SxCR_PBURST_Msk      (0x3UL << DMA_SxCR_PBURST_Pos)                /*!< 0x00600000 */

+#define DMA_SxCR_PBURST          DMA_SxCR_PBURST_Msk                           /*!< Peripheral burst transfer configuration */

+#define DMA_SxCR_PBURST_0        (0x1UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00200000 */

+#define DMA_SxCR_PBURST_1        (0x2UL << DMA_SxCR_PBURST_Pos)                 /*!< 0x00400000 */

+#define DMA_SxCR_TRBUFF_Pos      (20U)

+#define DMA_SxCR_TRBUFF_Msk      (0x1UL << DMA_SxCR_TRBUFF_Pos)                 /*!< 0x00100000 */

+#define DMA_SxCR_TRBUFF          DMA_SxCR_TRBUFF_Msk                            /*!< bufferable transfers enabled/disable */

+#define DMA_SxCR_CT_Pos          (19U)

+#define DMA_SxCR_CT_Msk          (0x1UL << DMA_SxCR_CT_Pos)                    /*!< 0x00080000 */

+#define DMA_SxCR_CT              DMA_SxCR_CT_Msk                               /*!< Current target (only in double buffer mode) */

+#define DMA_SxCR_DBM_Pos         (18U)

+#define DMA_SxCR_DBM_Msk         (0x1UL << DMA_SxCR_DBM_Pos)                   /*!< 0x00040000 */

+#define DMA_SxCR_DBM             DMA_SxCR_DBM_Msk                              /*!< Double buffer mode */

+#define DMA_SxCR_PL_Pos          (16U)

+#define DMA_SxCR_PL_Msk          (0x3UL << DMA_SxCR_PL_Pos)                    /*!< 0x00030000 */

+#define DMA_SxCR_PL              DMA_SxCR_PL_Msk                               /*!< Priority level */

+#define DMA_SxCR_PL_0            (0x1UL << DMA_SxCR_PL_Pos)                     /*!< 0x00010000 */

+#define DMA_SxCR_PL_1            (0x2UL << DMA_SxCR_PL_Pos)                     /*!< 0x00020000 */

+#define DMA_SxCR_PINCOS_Pos      (15U)

+#define DMA_SxCR_PINCOS_Msk      (0x1UL << DMA_SxCR_PINCOS_Pos)                /*!< 0x00008000 */

+#define DMA_SxCR_PINCOS          DMA_SxCR_PINCOS_Msk                           /*!< Peripheral increment offset size */

+#define DMA_SxCR_MSIZE_Pos       (13U)

+#define DMA_SxCR_MSIZE_Msk       (0x3UL << DMA_SxCR_MSIZE_Pos)                 /*!< 0x00006000 */

+#define DMA_SxCR_MSIZE           DMA_SxCR_MSIZE_Msk                            /*!< Memory data size */

+#define DMA_SxCR_MSIZE_0         (0x1UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00002000 */

+#define DMA_SxCR_MSIZE_1         (0x2UL << DMA_SxCR_MSIZE_Pos)                  /*!< 0x00004000 */

+#define DMA_SxCR_PSIZE_Pos       (11U)

+#define DMA_SxCR_PSIZE_Msk       (0x3UL << DMA_SxCR_PSIZE_Pos)                 /*!< 0x00001800 */

+#define DMA_SxCR_PSIZE           DMA_SxCR_PSIZE_Msk                            /*< Peripheral data size */

+#define DMA_SxCR_PSIZE_0         (0x1UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00000800 */

+#define DMA_SxCR_PSIZE_1         (0x2UL << DMA_SxCR_PSIZE_Pos)                  /*!< 0x00001000 */

+#define DMA_SxCR_MINC_Pos        (10U)

+#define DMA_SxCR_MINC_Msk        (0x1UL << DMA_SxCR_MINC_Pos)                  /*!< 0x00000400 */

+#define DMA_SxCR_MINC            DMA_SxCR_MINC_Msk                             /*!< Memory increment mode */

+#define DMA_SxCR_PINC_Pos        (9U)

+#define DMA_SxCR_PINC_Msk        (0x1UL << DMA_SxCR_PINC_Pos)                  /*!< 0x00000200 */

+#define DMA_SxCR_PINC            DMA_SxCR_PINC_Msk                             /*!< Peripheral increment mode */

+#define DMA_SxCR_CIRC_Pos        (8U)

+#define DMA_SxCR_CIRC_Msk        (0x1UL << DMA_SxCR_CIRC_Pos)                  /*!< 0x00000100 */

+#define DMA_SxCR_CIRC            DMA_SxCR_CIRC_Msk                             /*!< Circular mode */

+#define DMA_SxCR_DIR_Pos         (6U)

+#define DMA_SxCR_DIR_Msk         (0x3UL << DMA_SxCR_DIR_Pos)                   /*!< 0x000000C0 */

+#define DMA_SxCR_DIR             DMA_SxCR_DIR_Msk                              /*!< Data transfer direction */

+#define DMA_SxCR_DIR_0           (0x1UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000040 */

+#define DMA_SxCR_DIR_1           (0x2UL << DMA_SxCR_DIR_Pos)                    /*!< 0x00000080 */

+#define DMA_SxCR_PFCTRL_Pos      (5U)

+#define DMA_SxCR_PFCTRL_Msk      (0x1UL << DMA_SxCR_PFCTRL_Pos)                /*!< 0x00000020 */

+#define DMA_SxCR_PFCTRL          DMA_SxCR_PFCTRL_Msk                           /*!< Peripheral flow controller */

+#define DMA_SxCR_TCIE_Pos        (4U)

+#define DMA_SxCR_TCIE_Msk        (0x1UL << DMA_SxCR_TCIE_Pos)                  /*!< 0x00000010 */

+#define DMA_SxCR_TCIE            DMA_SxCR_TCIE_Msk                             /*!< Transfer complete interrupt enable */

+#define DMA_SxCR_HTIE_Pos        (3U)

+#define DMA_SxCR_HTIE_Msk        (0x1UL << DMA_SxCR_HTIE_Pos)                  /*!< 0x00000008 */

+#define DMA_SxCR_HTIE            DMA_SxCR_HTIE_Msk                             /*!< Half transfer interrupt enable */

+#define DMA_SxCR_TEIE_Pos        (2U)

+#define DMA_SxCR_TEIE_Msk        (0x1UL << DMA_SxCR_TEIE_Pos)                  /*!< 0x00000004 */

+#define DMA_SxCR_TEIE            DMA_SxCR_TEIE_Msk                             /*!< Transfer error interrupt enable */

+#define DMA_SxCR_DMEIE_Pos       (1U)

+#define DMA_SxCR_DMEIE_Msk       (0x1UL << DMA_SxCR_DMEIE_Pos)                 /*!< 0x00000002 */

+#define DMA_SxCR_DMEIE           DMA_SxCR_DMEIE_Msk                            /*!< Direct mode error interrupt enable */

+#define DMA_SxCR_EN_Pos          (0U)

+#define DMA_SxCR_EN_Msk          (0x1UL << DMA_SxCR_EN_Pos)                    /*!< 0x00000001 */

+#define DMA_SxCR_EN              DMA_SxCR_EN_Msk                               /*!< Stream enable / flag stream ready when read low */

+

+/********************  Bits definition for DMA_SxCNDTR register  **************/

+#define DMA_SxNDT_Pos            (0U)

+#define DMA_SxNDT_Msk            (0xFFFFUL << DMA_SxNDT_Pos)                   /*!< 0x0000FFFF */

+#define DMA_SxNDT                DMA_SxNDT_Msk                                 /*!< Number of data items to transfer */

+#define DMA_SxNDT_0              (0x0001UL << DMA_SxNDT_Pos)                    /*!< 0x00000001 */

+#define DMA_SxNDT_1              (0x0002UL << DMA_SxNDT_Pos)                    /*!< 0x00000002 */

+#define DMA_SxNDT_2              (0x0004UL << DMA_SxNDT_Pos)                    /*!< 0x00000004 */

+#define DMA_SxNDT_3              (0x0008UL << DMA_SxNDT_Pos)                    /*!< 0x00000008 */

+#define DMA_SxNDT_4              (0x0010UL << DMA_SxNDT_Pos)                    /*!< 0x00000010 */

+#define DMA_SxNDT_5              (0x0020UL << DMA_SxNDT_Pos)                    /*!< 0x00000020 */

+#define DMA_SxNDT_6              (0x0040UL << DMA_SxNDT_Pos)                    /*!< 0x00000040 */

+#define DMA_SxNDT_7              (0x0080UL << DMA_SxNDT_Pos)                    /*!< 0x00000080 */

+#define DMA_SxNDT_8              (0x0100UL << DMA_SxNDT_Pos)                    /*!< 0x00000100 */

+#define DMA_SxNDT_9              (0x0200UL << DMA_SxNDT_Pos)                    /*!< 0x00000200 */

+#define DMA_SxNDT_10             (0x0400UL << DMA_SxNDT_Pos)                    /*!< 0x00000400 */

+#define DMA_SxNDT_11             (0x0800UL << DMA_SxNDT_Pos)                    /*!< 0x00000800 */

+#define DMA_SxNDT_12             (0x1000UL << DMA_SxNDT_Pos)                    /*!< 0x00001000 */

+#define DMA_SxNDT_13             (0x2000UL << DMA_SxNDT_Pos)                    /*!< 0x00002000 */

+#define DMA_SxNDT_14             (0x4000UL << DMA_SxNDT_Pos)                    /*!< 0x00004000 */

+#define DMA_SxNDT_15             (0x8000UL << DMA_SxNDT_Pos)                    /*!< 0x00008000 */

+

+/********************  Bits definition for DMA_SxFCR register  ****************/

+#define DMA_SxFCR_FEIE_Pos       (7U)

+#define DMA_SxFCR_FEIE_Msk       (0x1UL << DMA_SxFCR_FEIE_Pos)                 /*!< 0x00000080 */

+#define DMA_SxFCR_FEIE           DMA_SxFCR_FEIE_Msk                            /*!< FIFO error interrupt enable */

+#define DMA_SxFCR_FS_Pos         (3U)

+#define DMA_SxFCR_FS_Msk         (0x7UL << DMA_SxFCR_FS_Pos)                   /*!< 0x00000038 */

+#define DMA_SxFCR_FS             DMA_SxFCR_FS_Msk                              /*!< FIFO status */

+#define DMA_SxFCR_FS_0           (0x1UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000008 */

+#define DMA_SxFCR_FS_1           (0x2UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000010 */

+#define DMA_SxFCR_FS_2           (0x4UL << DMA_SxFCR_FS_Pos)                    /*!< 0x00000020 */

+#define DMA_SxFCR_DMDIS_Pos      (2U)

+#define DMA_SxFCR_DMDIS_Msk      (0x1UL << DMA_SxFCR_DMDIS_Pos)                /*!< 0x00000004 */

+#define DMA_SxFCR_DMDIS          DMA_SxFCR_DMDIS_Msk                           /*!< Direct mode disable */

+#define DMA_SxFCR_FTH_Pos        (0U)

+#define DMA_SxFCR_FTH_Msk        (0x3UL << DMA_SxFCR_FTH_Pos)                  /*!< 0x00000003 */

+#define DMA_SxFCR_FTH            DMA_SxFCR_FTH_Msk                             /*!< FIFO threshold selection */

+#define DMA_SxFCR_FTH_0          (0x1UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000001 */

+#define DMA_SxFCR_FTH_1          (0x2UL << DMA_SxFCR_FTH_Pos)                   /*!< 0x00000002 */

+

+/********************  Bits definition for DMA_LISR register  *****************/

+#define DMA_LISR_TCIF3_Pos       (27U)

+#define DMA_LISR_TCIF3_Msk       (0x1UL << DMA_LISR_TCIF3_Pos)                 /*!< 0x08000000 */

+#define DMA_LISR_TCIF3           DMA_LISR_TCIF3_Msk                            /*!<  Stream 3 transfer complete interrupt flag */

+#define DMA_LISR_HTIF3_Pos       (26U)

+#define DMA_LISR_HTIF3_Msk       (0x1UL << DMA_LISR_HTIF3_Pos)                 /*!< 0x04000000 */

+#define DMA_LISR_HTIF3           DMA_LISR_HTIF3_Msk                            /*!<  Stream 3 half transfer interrupt flag */

+#define DMA_LISR_TEIF3_Pos       (25U)

+#define DMA_LISR_TEIF3_Msk       (0x1UL << DMA_LISR_TEIF3_Pos)                 /*!< 0x02000000 */

+#define DMA_LISR_TEIF3           DMA_LISR_TEIF3_Msk                            /*!<  Stream 3 transfer error interrupt flag */

+#define DMA_LISR_DMEIF3_Pos      (24U)

+#define DMA_LISR_DMEIF3_Msk      (0x1UL << DMA_LISR_DMEIF3_Pos)                /*!< 0x01000000 */

+#define DMA_LISR_DMEIF3          DMA_LISR_DMEIF3_Msk                           /*!<  Stream 3 direct mode error interrupt flag */

+#define DMA_LISR_FEIF3_Pos       (22U)

+#define DMA_LISR_FEIF3_Msk       (0x1UL << DMA_LISR_FEIF3_Pos)                 /*!< 0x00400000 */

+#define DMA_LISR_FEIF3           DMA_LISR_FEIF3_Msk                            /*!<  Stream 3 FIFO error interrupt flag */

+#define DMA_LISR_TCIF2_Pos       (21U)

+#define DMA_LISR_TCIF2_Msk       (0x1UL << DMA_LISR_TCIF2_Pos)                 /*!< 0x00200000 */

+#define DMA_LISR_TCIF2           DMA_LISR_TCIF2_Msk                            /*!<  Stream 2 transfer complete interrupt flag */

+#define DMA_LISR_HTIF2_Pos       (20U)

+#define DMA_LISR_HTIF2_Msk       (0x1UL << DMA_LISR_HTIF2_Pos)                 /*!< 0x00100000 */

+#define DMA_LISR_HTIF2           DMA_LISR_HTIF2_Msk                            /*!<  Stream 2 half transfer interrupt flag */

+#define DMA_LISR_TEIF2_Pos       (19U)

+#define DMA_LISR_TEIF2_Msk       (0x1UL << DMA_LISR_TEIF2_Pos)                 /*!< 0x00080000 */

+#define DMA_LISR_TEIF2           DMA_LISR_TEIF2_Msk                            /*!<  Stream 2 transfer error interrupt flag */

+#define DMA_LISR_DMEIF2_Pos      (18U)

+#define DMA_LISR_DMEIF2_Msk      (0x1UL << DMA_LISR_DMEIF2_Pos)                /*!< 0x00040000 */

+#define DMA_LISR_DMEIF2          DMA_LISR_DMEIF2_Msk                           /*!<  Stream 2 direct mode error interrupt flag */

+#define DMA_LISR_FEIF2_Pos       (16U)

+#define DMA_LISR_FEIF2_Msk       (0x1UL << DMA_LISR_FEIF2_Pos)                 /*!< 0x00010000 */

+#define DMA_LISR_FEIF2           DMA_LISR_FEIF2_Msk                            /*!<  Stream 2 FIFO error interrupt flag */

+#define DMA_LISR_TCIF1_Pos       (11U)

+#define DMA_LISR_TCIF1_Msk       (0x1UL << DMA_LISR_TCIF1_Pos)                 /*!< 0x00000800 */

+#define DMA_LISR_TCIF1           DMA_LISR_TCIF1_Msk                            /*!<  Stream 1 transfer complete interrupt flag */

+#define DMA_LISR_HTIF1_Pos       (10U)

+#define DMA_LISR_HTIF1_Msk       (0x1UL << DMA_LISR_HTIF1_Pos)                 /*!< 0x00000400 */

+#define DMA_LISR_HTIF1           DMA_LISR_HTIF1_Msk                            /*!<  Stream 1 half transfer interrupt flag */

+#define DMA_LISR_TEIF1_Pos       (9U)

+#define DMA_LISR_TEIF1_Msk       (0x1UL << DMA_LISR_TEIF1_Pos)                 /*!< 0x00000200 */

+#define DMA_LISR_TEIF1           DMA_LISR_TEIF1_Msk                            /*!<  Stream 1 transfer error interrupt flag */

+#define DMA_LISR_DMEIF1_Pos      (8U)

+#define DMA_LISR_DMEIF1_Msk      (0x1UL << DMA_LISR_DMEIF1_Pos)                /*!< 0x00000100 */

+#define DMA_LISR_DMEIF1          DMA_LISR_DMEIF1_Msk                           /*!<  Stream 1 direct mode error interrupt flag */

+#define DMA_LISR_FEIF1_Pos       (6U)

+#define DMA_LISR_FEIF1_Msk       (0x1UL << DMA_LISR_FEIF1_Pos)                 /*!< 0x00000040 */

+#define DMA_LISR_FEIF1           DMA_LISR_FEIF1_Msk                            /*!<  Stream 1 FIFO error interrupt flag */

+#define DMA_LISR_TCIF0_Pos       (5U)

+#define DMA_LISR_TCIF0_Msk       (0x1UL << DMA_LISR_TCIF0_Pos)                 /*!< 0x00000020 */

+#define DMA_LISR_TCIF0           DMA_LISR_TCIF0_Msk                            /*!<  Stream 0 transfer complete interrupt flag */

+#define DMA_LISR_HTIF0_Pos       (4U)

+#define DMA_LISR_HTIF0_Msk       (0x1UL << DMA_LISR_HTIF0_Pos)                 /*!< 0x00000010 */

+#define DMA_LISR_HTIF0           DMA_LISR_HTIF0_Msk                            /*!<  Stream 0 half transfer interrupt flag */

+#define DMA_LISR_TEIF0_Pos       (3U)

+#define DMA_LISR_TEIF0_Msk       (0x1UL << DMA_LISR_TEIF0_Pos)                 /*!< 0x00000008 */

+#define DMA_LISR_TEIF0           DMA_LISR_TEIF0_Msk                            /*!<  Stream 0 transfer error interrupt flag */

+#define DMA_LISR_DMEIF0_Pos      (2U)

+#define DMA_LISR_DMEIF0_Msk      (0x1UL << DMA_LISR_DMEIF0_Pos)                /*!< 0x00000004 */

+#define DMA_LISR_DMEIF0          DMA_LISR_DMEIF0_Msk                           /*!<  Stream 0 direct mode error interrupt flag */

+#define DMA_LISR_FEIF0_Pos       (0U)

+#define DMA_LISR_FEIF0_Msk       (0x1UL << DMA_LISR_FEIF0_Pos)                 /*!< 0x00000001 */

+#define DMA_LISR_FEIF0           DMA_LISR_FEIF0_Msk                            /*!<  Stream 0 FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_HISR register  *****************/

+#define DMA_HISR_TCIF7_Pos       (27U)

+#define DMA_HISR_TCIF7_Msk       (0x1UL << DMA_HISR_TCIF7_Pos)                 /*!< 0x08000000 */

+#define DMA_HISR_TCIF7           DMA_HISR_TCIF7_Msk                            /*!<  Stream 7 transfer complete interrupt flag */

+#define DMA_HISR_HTIF7_Pos       (26U)

+#define DMA_HISR_HTIF7_Msk       (0x1UL << DMA_HISR_HTIF7_Pos)                 /*!< 0x04000000 */

+#define DMA_HISR_HTIF7           DMA_HISR_HTIF7_Msk                            /*!<  Stream 7 half transfer interrupt flag */

+#define DMA_HISR_TEIF7_Pos       (25U)

+#define DMA_HISR_TEIF7_Msk       (0x1UL << DMA_HISR_TEIF7_Pos)                 /*!< 0x02000000 */

+#define DMA_HISR_TEIF7           DMA_HISR_TEIF7_Msk                            /*!<  Stream 7 transfer error interrupt flag */

+#define DMA_HISR_DMEIF7_Pos      (24U)

+#define DMA_HISR_DMEIF7_Msk      (0x1UL << DMA_HISR_DMEIF7_Pos)                /*!< 0x01000000 */

+#define DMA_HISR_DMEIF7          DMA_HISR_DMEIF7_Msk                           /*!<  Stream 7 direct mode error interrupt flag */

+#define DMA_HISR_FEIF7_Pos       (22U)

+#define DMA_HISR_FEIF7_Msk       (0x1UL << DMA_HISR_FEIF7_Pos)                 /*!< 0x00400000 */

+#define DMA_HISR_FEIF7           DMA_HISR_FEIF7_Msk                            /*!<  Stream 7 FIFO error interrupt flag */

+#define DMA_HISR_TCIF6_Pos       (21U)

+#define DMA_HISR_TCIF6_Msk       (0x1UL << DMA_HISR_TCIF6_Pos)                 /*!< 0x00200000 */

+#define DMA_HISR_TCIF6           DMA_HISR_TCIF6_Msk                            /*!<  Stream 6 transfer complete interrupt flag */

+#define DMA_HISR_HTIF6_Pos       (20U)

+#define DMA_HISR_HTIF6_Msk       (0x1UL << DMA_HISR_HTIF6_Pos)                 /*!< 0x00100000 */

+#define DMA_HISR_HTIF6           DMA_HISR_HTIF6_Msk                            /*!<  Stream 6 half transfer interrupt flag */

+#define DMA_HISR_TEIF6_Pos       (19U)

+#define DMA_HISR_TEIF6_Msk       (0x1UL << DMA_HISR_TEIF6_Pos)                 /*!< 0x00080000 */

+#define DMA_HISR_TEIF6           DMA_HISR_TEIF6_Msk                            /*!<  Stream 6 transfer error interrupt flag */

+#define DMA_HISR_DMEIF6_Pos      (18U)

+#define DMA_HISR_DMEIF6_Msk      (0x1UL << DMA_HISR_DMEIF6_Pos)                /*!< 0x00040000 */

+#define DMA_HISR_DMEIF6          DMA_HISR_DMEIF6_Msk                           /*!<  Stream 6 direct mode error interrupt flag */

+#define DMA_HISR_FEIF6_Pos       (16U)

+#define DMA_HISR_FEIF6_Msk       (0x1UL << DMA_HISR_FEIF6_Pos)                 /*!< 0x00010000 */

+#define DMA_HISR_FEIF6           DMA_HISR_FEIF6_Msk                            /*!<  Stream 6 FIFO error interrupt flag */

+#define DMA_HISR_TCIF5_Pos       (11U)

+#define DMA_HISR_TCIF5_Msk       (0x1UL << DMA_HISR_TCIF5_Pos)                 /*!< 0x00000800 */

+#define DMA_HISR_TCIF5           DMA_HISR_TCIF5_Msk                            /*!<  Stream 5 transfer complete interrupt flag */

+#define DMA_HISR_HTIF5_Pos       (10U)

+#define DMA_HISR_HTIF5_Msk       (0x1UL << DMA_HISR_HTIF5_Pos)                 /*!< 0x00000400 */

+#define DMA_HISR_HTIF5           DMA_HISR_HTIF5_Msk                            /*!<  Stream 5 half transfer interrupt flag */

+#define DMA_HISR_TEIF5_Pos       (9U)

+#define DMA_HISR_TEIF5_Msk       (0x1UL << DMA_HISR_TEIF5_Pos)                 /*!< 0x00000200 */

+#define DMA_HISR_TEIF5           DMA_HISR_TEIF5_Msk                            /*!<  Stream 5 transfer error interrupt flag */

+#define DMA_HISR_DMEIF5_Pos      (8U)

+#define DMA_HISR_DMEIF5_Msk      (0x1UL << DMA_HISR_DMEIF5_Pos)                /*!< 0x00000100 */

+#define DMA_HISR_DMEIF5          DMA_HISR_DMEIF5_Msk                           /*!<  Stream 5 direct mode error interrupt flag */

+#define DMA_HISR_FEIF5_Pos       (6U)

+#define DMA_HISR_FEIF5_Msk       (0x1UL << DMA_HISR_FEIF5_Pos)                 /*!< 0x00000040 */

+#define DMA_HISR_FEIF5           DMA_HISR_FEIF5_Msk                            /*!<  Stream 5 FIFO error interrupt flag */

+#define DMA_HISR_TCIF4_Pos       (5U)

+#define DMA_HISR_TCIF4_Msk       (0x1UL << DMA_HISR_TCIF4_Pos)                 /*!< 0x00000020 */

+#define DMA_HISR_TCIF4           DMA_HISR_TCIF4_Msk                            /*!<  Stream 4 transfer complete interrupt flag */

+#define DMA_HISR_HTIF4_Pos       (4U)

+#define DMA_HISR_HTIF4_Msk       (0x1UL << DMA_HISR_HTIF4_Pos)                 /*!< 0x00000010 */

+#define DMA_HISR_HTIF4           DMA_HISR_HTIF4_Msk                            /*!<  Stream 4 half transfer interrupt flag */

+#define DMA_HISR_TEIF4_Pos       (3U)

+#define DMA_HISR_TEIF4_Msk       (0x1UL << DMA_HISR_TEIF4_Pos)                 /*!< 0x00000008 */

+#define DMA_HISR_TEIF4           DMA_HISR_TEIF4_Msk                            /*!<  Stream 4 transfer error interrupt flag */

+#define DMA_HISR_DMEIF4_Pos      (2U)

+#define DMA_HISR_DMEIF4_Msk      (0x1UL << DMA_HISR_DMEIF4_Pos)                /*!< 0x00000004 */

+#define DMA_HISR_DMEIF4          DMA_HISR_DMEIF4_Msk                           /*!<  Stream 4 direct mode error interrupt flag */

+#define DMA_HISR_FEIF4_Pos       (0U)

+#define DMA_HISR_FEIF4_Msk       (0x1UL << DMA_HISR_FEIF4_Pos)                 /*!< 0x00000001 */

+#define DMA_HISR_FEIF4           DMA_HISR_FEIF4_Msk                            /*!<  Stream 4 FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_LIFCR register  ****************/

+#define DMA_LIFCR_CTCIF3_Pos     (27U)

+#define DMA_LIFCR_CTCIF3_Msk     (0x1UL << DMA_LIFCR_CTCIF3_Pos)               /*!< 0x08000000 */

+#define DMA_LIFCR_CTCIF3         DMA_LIFCR_CTCIF3_Msk                          /*!<  Stream 3 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF3_Pos     (26U)

+#define DMA_LIFCR_CHTIF3_Msk     (0x1UL << DMA_LIFCR_CHTIF3_Pos)               /*!< 0x04000000 */

+#define DMA_LIFCR_CHTIF3         DMA_LIFCR_CHTIF3_Msk                          /*!<  Stream 3 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF3_Pos     (25U)

+#define DMA_LIFCR_CTEIF3_Msk     (0x1UL << DMA_LIFCR_CTEIF3_Pos)               /*!< 0x02000000 */

+#define DMA_LIFCR_CTEIF3         DMA_LIFCR_CTEIF3_Msk                          /*!<  Stream 3 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF3_Pos    (24U)

+#define DMA_LIFCR_CDMEIF3_Msk    (0x1UL << DMA_LIFCR_CDMEIF3_Pos)              /*!< 0x01000000 */

+#define DMA_LIFCR_CDMEIF3        DMA_LIFCR_CDMEIF3_Msk                         /*!<  Stream 3 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF3_Pos     (22U)

+#define DMA_LIFCR_CFEIF3_Msk     (0x1UL << DMA_LIFCR_CFEIF3_Pos)               /*!< 0x00400000 */

+#define DMA_LIFCR_CFEIF3         DMA_LIFCR_CFEIF3_Msk                          /*!<  Stream 3 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF2_Pos     (21U)

+#define DMA_LIFCR_CTCIF2_Msk     (0x1UL << DMA_LIFCR_CTCIF2_Pos)               /*!< 0x00200000 */

+#define DMA_LIFCR_CTCIF2         DMA_LIFCR_CTCIF2_Msk                          /*!<  Stream 2 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF2_Pos     (20U)

+#define DMA_LIFCR_CHTIF2_Msk     (0x1UL << DMA_LIFCR_CHTIF2_Pos)               /*!< 0x00100000 */

+#define DMA_LIFCR_CHTIF2         DMA_LIFCR_CHTIF2_Msk                          /*!<  Stream 2 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF2_Pos     (19U)

+#define DMA_LIFCR_CTEIF2_Msk     (0x1UL << DMA_LIFCR_CTEIF2_Pos)               /*!< 0x00080000 */

+#define DMA_LIFCR_CTEIF2         DMA_LIFCR_CTEIF2_Msk                          /*!<  Stream 2 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF2_Pos    (18U)

+#define DMA_LIFCR_CDMEIF2_Msk    (0x1UL << DMA_LIFCR_CDMEIF2_Pos)              /*!< 0x00040000 */

+#define DMA_LIFCR_CDMEIF2        DMA_LIFCR_CDMEIF2_Msk                         /*!<  Stream 2 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF2_Pos     (16U)

+#define DMA_LIFCR_CFEIF2_Msk     (0x1UL << DMA_LIFCR_CFEIF2_Pos)               /*!< 0x00010000 */

+#define DMA_LIFCR_CFEIF2         DMA_LIFCR_CFEIF2_Msk                          /*!<  Stream 2 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF1_Pos     (11U)

+#define DMA_LIFCR_CTCIF1_Msk     (0x1UL << DMA_LIFCR_CTCIF1_Pos)               /*!< 0x00000800 */

+#define DMA_LIFCR_CTCIF1         DMA_LIFCR_CTCIF1_Msk                          /*!<  Stream 1 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF1_Pos     (10U)

+#define DMA_LIFCR_CHTIF1_Msk     (0x1UL << DMA_LIFCR_CHTIF1_Pos)               /*!< 0x00000400 */

+#define DMA_LIFCR_CHTIF1         DMA_LIFCR_CHTIF1_Msk                          /*!<  Stream 1 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF1_Pos     (9U)

+#define DMA_LIFCR_CTEIF1_Msk     (0x1UL << DMA_LIFCR_CTEIF1_Pos)               /*!< 0x00000200 */

+#define DMA_LIFCR_CTEIF1         DMA_LIFCR_CTEIF1_Msk                          /*!<  Stream 1 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF1_Pos    (8U)

+#define DMA_LIFCR_CDMEIF1_Msk    (0x1UL << DMA_LIFCR_CDMEIF1_Pos)              /*!< 0x00000100 */

+#define DMA_LIFCR_CDMEIF1        DMA_LIFCR_CDMEIF1_Msk                         /*!<  Stream 1 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF1_Pos     (6U)

+#define DMA_LIFCR_CFEIF1_Msk     (0x1UL << DMA_LIFCR_CFEIF1_Pos)               /*!< 0x00000040 */

+#define DMA_LIFCR_CFEIF1         DMA_LIFCR_CFEIF1_Msk                          /*!<  Stream 1 clear FIFO error interrupt flag */

+#define DMA_LIFCR_CTCIF0_Pos     (5U)

+#define DMA_LIFCR_CTCIF0_Msk     (0x1UL << DMA_LIFCR_CTCIF0_Pos)               /*!< 0x00000020 */

+#define DMA_LIFCR_CTCIF0         DMA_LIFCR_CTCIF0_Msk                          /*!<  Stream 0 clear transfer complete interrupt flag */

+#define DMA_LIFCR_CHTIF0_Pos     (4U)

+#define DMA_LIFCR_CHTIF0_Msk     (0x1UL << DMA_LIFCR_CHTIF0_Pos)               /*!< 0x00000010 */

+#define DMA_LIFCR_CHTIF0         DMA_LIFCR_CHTIF0_Msk                          /*!<  Stream 0 clear half transfer interrupt flag */

+#define DMA_LIFCR_CTEIF0_Pos     (3U)

+#define DMA_LIFCR_CTEIF0_Msk     (0x1UL << DMA_LIFCR_CTEIF0_Pos)               /*!< 0x00000008 */

+#define DMA_LIFCR_CTEIF0         DMA_LIFCR_CTEIF0_Msk                          /*!<  Stream 0 clear transfer error interrupt flag */

+#define DMA_LIFCR_CDMEIF0_Pos    (2U)

+#define DMA_LIFCR_CDMEIF0_Msk    (0x1UL << DMA_LIFCR_CDMEIF0_Pos)              /*!< 0x00000004 */

+#define DMA_LIFCR_CDMEIF0        DMA_LIFCR_CDMEIF0_Msk                         /*!<  Stream 0 clear direct mode error interrupt flag */

+#define DMA_LIFCR_CFEIF0_Pos     (0U)

+#define DMA_LIFCR_CFEIF0_Msk     (0x1UL << DMA_LIFCR_CFEIF0_Pos)               /*!< 0x00000001 */

+#define DMA_LIFCR_CFEIF0         DMA_LIFCR_CFEIF0_Msk                          /*!<  Stream 0 clear FIFO error interrupt flag */

+

+/********************  Bits definition for DMA_HIFCR  register  ****************/

+#define DMA_HIFCR_CTCIF7_Pos     (27U)

+#define DMA_HIFCR_CTCIF7_Msk     (0x1UL << DMA_HIFCR_CTCIF7_Pos)               /*!< 0x08000000 */

+#define DMA_HIFCR_CTCIF7         DMA_HIFCR_CTCIF7_Msk                          /*!<  Stream 7 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF7_Pos     (26U)

+#define DMA_HIFCR_CHTIF7_Msk     (0x1UL << DMA_HIFCR_CHTIF7_Pos)               /*!< 0x04000000 */

+#define DMA_HIFCR_CHTIF7         DMA_HIFCR_CHTIF7_Msk                          /*!<  Stream 7 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF7_Pos     (25U)

+#define DMA_HIFCR_CTEIF7_Msk     (0x1UL << DMA_HIFCR_CTEIF7_Pos)               /*!< 0x02000000 */

+#define DMA_HIFCR_CTEIF7         DMA_HIFCR_CTEIF7_Msk                          /*!<  Stream 7 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF7_Pos    (24U)

+#define DMA_HIFCR_CDMEIF7_Msk    (0x1UL << DMA_HIFCR_CDMEIF7_Pos)              /*!< 0x01000000 */

+#define DMA_HIFCR_CDMEIF7        DMA_HIFCR_CDMEIF7_Msk                         /*!<  Stream 7 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF7_Pos     (22U)

+#define DMA_HIFCR_CFEIF7_Msk     (0x1UL << DMA_HIFCR_CFEIF7_Pos)               /*!< 0x00400000 */

+#define DMA_HIFCR_CFEIF7         DMA_HIFCR_CFEIF7_Msk                          /*!<  Stream 7 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF6_Pos     (21U)

+#define DMA_HIFCR_CTCIF6_Msk     (0x1UL << DMA_HIFCR_CTCIF6_Pos)               /*!< 0x00200000 */

+#define DMA_HIFCR_CTCIF6         DMA_HIFCR_CTCIF6_Msk                          /*!<  Stream 6 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF6_Pos     (20U)

+#define DMA_HIFCR_CHTIF6_Msk     (0x1UL << DMA_HIFCR_CHTIF6_Pos)               /*!< 0x00100000 */

+#define DMA_HIFCR_CHTIF6         DMA_HIFCR_CHTIF6_Msk                          /*!<  Stream 6 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF6_Pos     (19U)

+#define DMA_HIFCR_CTEIF6_Msk     (0x1UL << DMA_HIFCR_CTEIF6_Pos)               /*!< 0x00080000 */

+#define DMA_HIFCR_CTEIF6         DMA_HIFCR_CTEIF6_Msk                          /*!<  Stream 6 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF6_Pos    (18U)

+#define DMA_HIFCR_CDMEIF6_Msk    (0x1UL << DMA_HIFCR_CDMEIF6_Pos)              /*!< 0x00040000 */

+#define DMA_HIFCR_CDMEIF6        DMA_HIFCR_CDMEIF6_Msk                         /*!<  Stream 6 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF6_Pos     (16U)

+#define DMA_HIFCR_CFEIF6_Msk     (0x1UL << DMA_HIFCR_CFEIF6_Pos)               /*!< 0x00010000 */

+#define DMA_HIFCR_CFEIF6         DMA_HIFCR_CFEIF6_Msk                          /*!<  Stream 6 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF5_Pos     (11U)

+#define DMA_HIFCR_CTCIF5_Msk     (0x1UL << DMA_HIFCR_CTCIF5_Pos)               /*!< 0x00000800 */

+#define DMA_HIFCR_CTCIF5         DMA_HIFCR_CTCIF5_Msk                          /*!<  Stream 5 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF5_Pos     (10U)

+#define DMA_HIFCR_CHTIF5_Msk     (0x1UL << DMA_HIFCR_CHTIF5_Pos)               /*!< 0x00000400 */

+#define DMA_HIFCR_CHTIF5         DMA_HIFCR_CHTIF5_Msk                          /*!<  Stream 5 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF5_Pos     (9U)

+#define DMA_HIFCR_CTEIF5_Msk     (0x1UL << DMA_HIFCR_CTEIF5_Pos)               /*!< 0x00000200 */

+#define DMA_HIFCR_CTEIF5         DMA_HIFCR_CTEIF5_Msk                          /*!<  Stream 5 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF5_Pos    (8U)

+#define DMA_HIFCR_CDMEIF5_Msk    (0x1UL << DMA_HIFCR_CDMEIF5_Pos)              /*!< 0x00000100 */

+#define DMA_HIFCR_CDMEIF5        DMA_HIFCR_CDMEIF5_Msk                         /*!<  Stream 5 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF5_Pos     (6U)

+#define DMA_HIFCR_CFEIF5_Msk     (0x1UL << DMA_HIFCR_CFEIF5_Pos)               /*!< 0x00000040 */

+#define DMA_HIFCR_CFEIF5         DMA_HIFCR_CFEIF5_Msk                          /*!<  Stream 5 clear FIFO error interrupt flag */

+#define DMA_HIFCR_CTCIF4_Pos     (5U)

+#define DMA_HIFCR_CTCIF4_Msk     (0x1UL << DMA_HIFCR_CTCIF4_Pos)               /*!< 0x00000020 */

+#define DMA_HIFCR_CTCIF4         DMA_HIFCR_CTCIF4_Msk                          /*!<  Stream 4 clear transfer complete interrupt flag */

+#define DMA_HIFCR_CHTIF4_Pos     (4U)

+#define DMA_HIFCR_CHTIF4_Msk     (0x1UL << DMA_HIFCR_CHTIF4_Pos)               /*!< 0x00000010 */

+#define DMA_HIFCR_CHTIF4         DMA_HIFCR_CHTIF4_Msk                          /*!<  Stream 4 clear half transfer interrupt flag */

+#define DMA_HIFCR_CTEIF4_Pos     (3U)

+#define DMA_HIFCR_CTEIF4_Msk     (0x1UL << DMA_HIFCR_CTEIF4_Pos)               /*!< 0x00000008 */

+#define DMA_HIFCR_CTEIF4         DMA_HIFCR_CTEIF4_Msk                          /*!<  Stream 4 clear transfer error interrupt flag */

+#define DMA_HIFCR_CDMEIF4_Pos    (2U)

+#define DMA_HIFCR_CDMEIF4_Msk    (0x1UL << DMA_HIFCR_CDMEIF4_Pos)              /*!< 0x00000004 */

+#define DMA_HIFCR_CDMEIF4        DMA_HIFCR_CDMEIF4_Msk                         /*!<  Stream 4 clear direct mode error interrupt flag */

+#define DMA_HIFCR_CFEIF4_Pos     (0U)

+#define DMA_HIFCR_CFEIF4_Msk     (0x1UL << DMA_HIFCR_CFEIF4_Pos)               /*!< 0x00000001 */

+#define DMA_HIFCR_CFEIF4         DMA_HIFCR_CFEIF4_Msk                          /*!<  Stream 4 clear FIFO error interrupt flag */

+

+/******************  Bit definition for DMA_SxPAR register  ********************/

+#define DMA_SxPAR_PA_Pos         (0U)

+#define DMA_SxPAR_PA_Msk         (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos)            /*!< 0xFFFFFFFF */

+#define DMA_SxPAR_PA             DMA_SxPAR_PA_Msk                              /*!< Peripheral Address */

+

+/******************  Bit definition for DMA_SxM0AR register  ********************/

+#define DMA_SxM0AR_M0A_Pos       (0U)

+#define DMA_SxM0AR_M0A_Msk       (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos)          /*!< 0xFFFFFFFF */

+#define DMA_SxM0AR_M0A           DMA_SxM0AR_M0A_Msk                            /*!< Memory 0 Address */

+

+/******************  Bit definition for DMA_SxM1AR register  ********************/

+#define DMA_SxM1AR_M1A_Pos       (0U)

+#define DMA_SxM1AR_M1A_Msk       (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos)          /*!< 0xFFFFFFFF */

+#define DMA_SxM1AR_M1A           DMA_SxM1AR_M1A_Msk                            /*!< Memory 1 Address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                             DMAMUX Controller                              */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for DMAMUX_CxCR register  **************/

+#define DMAMUX_CxCR_DMAREQ_ID_Pos      (0U)

+#define DMAMUX_CxCR_DMAREQ_ID_Msk      (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos)   /*!< 0x000000FF */

+#define DMAMUX_CxCR_DMAREQ_ID          DMAMUX_CxCR_DMAREQ_ID_Msk               /*!<  DMA request identification */

+#define DMAMUX_CxCR_DMAREQ_ID_0        (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000001 */

+#define DMAMUX_CxCR_DMAREQ_ID_1        (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000002 */

+#define DMAMUX_CxCR_DMAREQ_ID_2        (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000004 */

+#define DMAMUX_CxCR_DMAREQ_ID_3        (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000008 */

+#define DMAMUX_CxCR_DMAREQ_ID_4        (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000010 */

+#define DMAMUX_CxCR_DMAREQ_ID_5        (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000020 */

+#define DMAMUX_CxCR_DMAREQ_ID_6        (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000040 */

+#define DMAMUX_CxCR_DMAREQ_ID_7        (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos)    /*!< 0x00000080 */

+#define DMAMUX_CxCR_SOIE_Pos           (8U)

+#define DMAMUX_CxCR_SOIE_Msk           (0x1UL << DMAMUX_CxCR_SOIE_Pos)         /*!< 0x00000100 */

+#define DMAMUX_CxCR_SOIE               DMAMUX_CxCR_SOIE_Msk                    /*!<  Synchronization overrun interrupt enable */

+#define DMAMUX_CxCR_EGE_Pos            (9U)

+#define DMAMUX_CxCR_EGE_Msk            (0x1UL << DMAMUX_CxCR_EGE_Pos)          /*!< 0x00000200 */

+#define DMAMUX_CxCR_EGE                DMAMUX_CxCR_EGE_Msk                     /*!<  Event generation enable */

+#define DMAMUX_CxCR_SE_Pos             (16U)

+#define DMAMUX_CxCR_SE_Msk             (0x1UL << DMAMUX_CxCR_SE_Pos)           /*!< 0x00010000 */

+#define DMAMUX_CxCR_SE                 DMAMUX_CxCR_SE_Msk                      /*!<  Synchronization enable */

+#define DMAMUX_CxCR_SPOL_Pos           (17U)

+#define DMAMUX_CxCR_SPOL_Msk           (0x3UL << DMAMUX_CxCR_SPOL_Pos)         /*!< 0x00060000 */

+#define DMAMUX_CxCR_SPOL               DMAMUX_CxCR_SPOL_Msk                    /*!<  Synchronization polarity */

+#define DMAMUX_CxCR_SPOL_0             (0x1UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00020000 */

+#define DMAMUX_CxCR_SPOL_1             (0x2UL << DMAMUX_CxCR_SPOL_Pos)          /*!< 0x00040000 */

+#define DMAMUX_CxCR_NBREQ_Pos          (19U)

+#define DMAMUX_CxCR_NBREQ_Msk          (0x1FUL << DMAMUX_CxCR_NBREQ_Pos)       /*!< 0x00F80000 */

+#define DMAMUX_CxCR_NBREQ              DMAMUX_CxCR_NBREQ_Msk                   /*!<  Number of DMA requests minus 1 to forward */

+#define DMAMUX_CxCR_NBREQ_0            (0x01UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00080000 */

+#define DMAMUX_CxCR_NBREQ_1            (0x02UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00100000 */

+#define DMAMUX_CxCR_NBREQ_2            (0x04UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00200000 */

+#define DMAMUX_CxCR_NBREQ_3            (0x08UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00400000 */

+#define DMAMUX_CxCR_NBREQ_4            (0x10UL << DMAMUX_CxCR_NBREQ_Pos)        /*!< 0x00800000 */

+#define DMAMUX_CxCR_SYNC_ID_Pos        (24U)

+#define DMAMUX_CxCR_SYNC_ID_Msk        (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos)     /*!< 0x1F000000 */

+#define DMAMUX_CxCR_SYNC_ID            DMAMUX_CxCR_SYNC_ID_Msk                 /*!<  Synchronization identification */

+#define DMAMUX_CxCR_SYNC_ID_0          (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x01000000 */

+#define DMAMUX_CxCR_SYNC_ID_1          (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x02000000 */

+#define DMAMUX_CxCR_SYNC_ID_2          (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x04000000 */

+#define DMAMUX_CxCR_SYNC_ID_3          (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x08000000 */

+#define DMAMUX_CxCR_SYNC_ID_4          (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos)      /*!< 0x10000000 */

+

+/********************  Bits definition for DMAMUX_CSR register  **************/

+#define DMAMUX_CSR_SOF0_Pos            (0U)

+#define DMAMUX_CSR_SOF0_Msk            (0x1UL << DMAMUX_CSR_SOF0_Pos)          /*!< 0x00000001 */

+#define DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0_Msk                     /*!< Channel 0 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF1_Pos            (1U)

+#define DMAMUX_CSR_SOF1_Msk            (0x1UL << DMAMUX_CSR_SOF1_Pos)          /*!< 0x00000002 */

+#define DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1_Msk                     /*!< Channel 1 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF2_Pos            (2U)

+#define DMAMUX_CSR_SOF2_Msk            (0x1UL << DMAMUX_CSR_SOF2_Pos)          /*!< 0x00000004 */

+#define DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2_Msk                     /*!< Channel 2 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF3_Pos            (3U)

+#define DMAMUX_CSR_SOF3_Msk            (0x1UL << DMAMUX_CSR_SOF3_Pos)          /*!< 0x00000008 */

+#define DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3_Msk                     /*!< Channel 3 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF4_Pos            (4U)

+#define DMAMUX_CSR_SOF4_Msk            (0x1UL << DMAMUX_CSR_SOF4_Pos)          /*!< 0x00000010 */

+#define DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4_Msk                     /*!< Channel 4 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF5_Pos            (5U)

+#define DMAMUX_CSR_SOF5_Msk            (0x1UL << DMAMUX_CSR_SOF5_Pos)          /*!< 0x00000020 */

+#define DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5_Msk                     /*!< Channel 5 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF6_Pos            (6U)

+#define DMAMUX_CSR_SOF6_Msk            (0x1UL << DMAMUX_CSR_SOF6_Pos)          /*!< 0x00000040 */

+#define DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6_Msk                     /*!< Channel 6 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF7_Pos            (7U)

+#define DMAMUX_CSR_SOF7_Msk            (0x1UL << DMAMUX_CSR_SOF7_Pos)          /*!< 0x00000080 */

+#define DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7_Msk                     /*!< Channel 7 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF8_Pos            (8U)

+#define DMAMUX_CSR_SOF8_Msk            (0x1UL << DMAMUX_CSR_SOF8_Pos)          /*!< 0x00000100 */

+#define DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8_Msk                     /*!< Channel 8 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF9_Pos            (9U)

+#define DMAMUX_CSR_SOF9_Msk            (0x1UL << DMAMUX_CSR_SOF9_Pos)          /*!< 0x00000200 */

+#define DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9_Msk                     /*!< Channel 9 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF10_Pos           (10U)

+#define DMAMUX_CSR_SOF10_Msk           (0x1UL << DMAMUX_CSR_SOF10_Pos)         /*!< 0x00000400 */

+#define DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10_Msk                    /*!< Channel 10 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF11_Pos           (11U)

+#define DMAMUX_CSR_SOF11_Msk           (0x1UL << DMAMUX_CSR_SOF11_Pos)         /*!< 0x00000800 */

+#define DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11_Msk                    /*!< Channel 11 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF12_Pos           (12U)

+#define DMAMUX_CSR_SOF12_Msk           (0x1UL << DMAMUX_CSR_SOF12_Pos)         /*!< 0x00001000 */

+#define DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12_Msk                    /*!< Channel 12 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF13_Pos           (13U)

+#define DMAMUX_CSR_SOF13_Msk           (0x1UL << DMAMUX_CSR_SOF13_Pos)         /*!< 0x00002000 */

+#define DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13_Msk                    /*!< Channel 13 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF14_Pos           (14U)

+#define DMAMUX_CSR_SOF14_Msk           (0x1UL << DMAMUX_CSR_SOF14_Pos)         /*!< 0x00004000 */

+#define DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14_Msk                    /*!< Channel 14 Synchronization overrun event flag */

+#define DMAMUX_CSR_SOF15_Pos           (15U)

+#define DMAMUX_CSR_SOF15_Msk           (0x1UL << DMAMUX_CSR_SOF15_Pos)         /*!< 0x00008000 */

+#define DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15_Msk                    /*!< Channel 15 Synchronization overrun event flag */

+

+/********************  Bits definition for DMAMUX_CFR register  **************/

+#define DMAMUX_CFR_CSOF0_Pos           (0U)

+#define DMAMUX_CFR_CSOF0_Msk           (0x1UL << DMAMUX_CFR_CSOF0_Pos)         /*!< 0x00000001 */

+#define DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0_Msk                    /*!< Channel 0 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF1_Pos           (1U)

+#define DMAMUX_CFR_CSOF1_Msk           (0x1UL << DMAMUX_CFR_CSOF1_Pos)         /*!< 0x00000002 */

+#define DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1_Msk                    /*!< Channel 1 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF2_Pos           (2U)

+#define DMAMUX_CFR_CSOF2_Msk           (0x1UL << DMAMUX_CFR_CSOF2_Pos)         /*!< 0x00000004 */

+#define DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2_Msk                    /*!< Channel 2 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF3_Pos           (3U)

+#define DMAMUX_CFR_CSOF3_Msk           (0x1UL << DMAMUX_CFR_CSOF3_Pos)         /*!< 0x00000008 */

+#define DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3_Msk                    /*!< Channel 3 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF4_Pos           (4U)

+#define DMAMUX_CFR_CSOF4_Msk           (0x1UL << DMAMUX_CFR_CSOF4_Pos)         /*!< 0x00000010 */

+#define DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4_Msk                    /*!< Channel 4 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF5_Pos           (5U)

+#define DMAMUX_CFR_CSOF5_Msk           (0x1UL << DMAMUX_CFR_CSOF5_Pos)         /*!< 0x00000020 */

+#define DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5_Msk                    /*!< Channel 5 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF6_Pos           (6U)

+#define DMAMUX_CFR_CSOF6_Msk           (0x1UL << DMAMUX_CFR_CSOF6_Pos)         /*!< 0x00000040 */

+#define DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6_Msk                    /*!< Channel 6 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF7_Pos           (7U)

+#define DMAMUX_CFR_CSOF7_Msk           (0x1UL << DMAMUX_CFR_CSOF7_Pos)         /*!< 0x00000080 */

+#define DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7_Msk                    /*!< Channel 7 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF8_Pos           (8U)

+#define DMAMUX_CFR_CSOF8_Msk           (0x1UL << DMAMUX_CFR_CSOF8_Pos)         /*!< 0x00000100 */

+#define DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8_Msk                    /*!< Channel 8 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF9_Pos           (9U)

+#define DMAMUX_CFR_CSOF9_Msk           (0x1UL << DMAMUX_CFR_CSOF9_Pos)         /*!< 0x00000200 */

+#define DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9_Msk                    /*!< Channel 9 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF10_Pos          (10U)

+#define DMAMUX_CFR_CSOF10_Msk          (0x1UL << DMAMUX_CFR_CSOF10_Pos)        /*!< 0x00000400 */

+#define DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10_Msk                   /*!< Channel 10 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF11_Pos          (11U)

+#define DMAMUX_CFR_CSOF11_Msk          (0x1UL << DMAMUX_CFR_CSOF11_Pos)        /*!< 0x00000800 */

+#define DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11_Msk                   /*!< Channel 11 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF12_Pos          (12U)

+#define DMAMUX_CFR_CSOF12_Msk          (0x1UL << DMAMUX_CFR_CSOF12_Pos)        /*!< 0x00001000 */

+#define DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12_Msk                   /*!< Channel 12 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF13_Pos          (13U)

+#define DMAMUX_CFR_CSOF13_Msk          (0x1UL << DMAMUX_CFR_CSOF13_Pos)        /*!< 0x00002000 */

+#define DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13_Msk                   /*!< Channel 13 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF14_Pos          (14U)

+#define DMAMUX_CFR_CSOF14_Msk          (0x1UL << DMAMUX_CFR_CSOF14_Pos)        /*!< 0x00004000 */

+#define DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14_Msk                   /*!< Channel 14 Clear synchronization overrun event flag */

+#define DMAMUX_CFR_CSOF15_Pos          (15U)

+#define DMAMUX_CFR_CSOF15_Msk          (0x1UL << DMAMUX_CFR_CSOF15_Pos)        /*!< 0x00008000 */

+#define DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15_Msk                   /*!< Channel 15 Clear synchronization overrun event flag */

+

+/********************  Bits definition for DMAMUX_RGxCR register  ************/

+#define DMAMUX_RGxCR_SIG_ID_Pos        (0U)

+#define DMAMUX_RGxCR_SIG_ID_Msk        (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos)     /*!< 0x0000001F */

+#define DMAMUX_RGxCR_SIG_ID            DMAMUX_RGxCR_SIG_ID_Msk                 /*!< Signal identification */

+#define DMAMUX_RGxCR_SIG_ID_0          (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000001 */

+#define DMAMUX_RGxCR_SIG_ID_1          (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000002 */

+#define DMAMUX_RGxCR_SIG_ID_2          (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000004 */

+#define DMAMUX_RGxCR_SIG_ID_3          (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000008 */

+#define DMAMUX_RGxCR_SIG_ID_4          (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos)      /*!< 0x00000010 */

+#define DMAMUX_RGxCR_OIE_Pos           (8U)

+#define DMAMUX_RGxCR_OIE_Msk           (0x1UL << DMAMUX_RGxCR_OIE_Pos)         /*!< 0x00000100 */

+#define DMAMUX_RGxCR_OIE               DMAMUX_RGxCR_OIE_Msk                    /*!< Trigger overrun interrupt enable */

+#define DMAMUX_RGxCR_GE_Pos            (16U)

+#define DMAMUX_RGxCR_GE_Msk            (0x1UL << DMAMUX_RGxCR_GE_Pos)          /*!< 0x00010000 */

+#define DMAMUX_RGxCR_GE                DMAMUX_RGxCR_GE_Msk                     /*!< DMA request generator enable */

+#define DMAMUX_RGxCR_GPOL_Pos          (17U)

+#define DMAMUX_RGxCR_GPOL_Msk          (0x3UL << DMAMUX_RGxCR_GPOL_Pos)        /*!< 0x00060000 */

+#define DMAMUX_RGxCR_GPOL              DMAMUX_RGxCR_GPOL_Msk                   /*!< DMA request generator trigger polarity */

+#define DMAMUX_RGxCR_GPOL_0            (0x1UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00020000 */

+#define DMAMUX_RGxCR_GPOL_1            (0x2UL << DMAMUX_RGxCR_GPOL_Pos)         /*!< 0x00040000 */

+#define DMAMUX_RGxCR_GNBREQ_Pos        (19U)

+#define DMAMUX_RGxCR_GNBREQ_Msk        (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos)     /*!< 0x00F80000 */

+#define DMAMUX_RGxCR_GNBREQ            DMAMUX_RGxCR_GNBREQ_Msk                 /*!< Number of DMA requests to be generated */

+#define DMAMUX_RGxCR_GNBREQ_0          (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00080000 */

+#define DMAMUX_RGxCR_GNBREQ_1          (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00100000 */

+#define DMAMUX_RGxCR_GNBREQ_2          (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00200000 */

+#define DMAMUX_RGxCR_GNBREQ_3          (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00400000 */

+#define DMAMUX_RGxCR_GNBREQ_4          (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos)      /*!< 0x00800000 */

+

+/********************  Bits definition for DMAMUX_RGSR register  **************/

+#define DMAMUX_RGSR_OF0_Pos            (0U)

+#define DMAMUX_RGSR_OF0_Msk            (0x1UL << DMAMUX_RGSR_OF0_Pos)          /*!< 0x00000001 */

+#define DMAMUX_RGSR_OF0                DMAMUX_RGSR_OF0_Msk                     /*!< Request generator channel 0 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF1_Pos            (1U)

+#define DMAMUX_RGSR_OF1_Msk            (0x1UL << DMAMUX_RGSR_OF1_Pos)          /*!< 0x00000002 */

+#define DMAMUX_RGSR_OF1                DMAMUX_RGSR_OF1_Msk                     /*!< Request generator channel 1 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF2_Pos            (2U)

+#define DMAMUX_RGSR_OF2_Msk            (0x1UL << DMAMUX_RGSR_OF2_Pos)          /*!< 0x00000004 */

+#define DMAMUX_RGSR_OF2                DMAMUX_RGSR_OF2_Msk                     /*!< Request generator channel 2 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF3_Pos            (3U)

+#define DMAMUX_RGSR_OF3_Msk            (0x1UL << DMAMUX_RGSR_OF3_Pos)          /*!< 0x00000008 */

+#define DMAMUX_RGSR_OF3                DMAMUX_RGSR_OF3_Msk                     /*!< Request generator channel 3 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF4_Pos            (4U)

+#define DMAMUX_RGSR_OF4_Msk            (0x1UL << DMAMUX_RGSR_OF4_Pos)          /*!< 0x00000010 */

+#define DMAMUX_RGSR_OF4                DMAMUX_RGSR_OF4_Msk                     /*!< Request generator channel 4 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF5_Pos            (5U)

+#define DMAMUX_RGSR_OF5_Msk            (0x1UL << DMAMUX_RGSR_OF5_Pos)          /*!< 0x00000020 */

+#define DMAMUX_RGSR_OF5                DMAMUX_RGSR_OF5_Msk                     /*!< Request generator channel 5 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF6_Pos            (6U)

+#define DMAMUX_RGSR_OF6_Msk            (0x1UL << DMAMUX_RGSR_OF6_Pos)          /*!< 0x00000040 */

+#define DMAMUX_RGSR_OF6                DMAMUX_RGSR_OF6_Msk                     /*!< Request generator channel 6 Trigger overrun event flag */

+#define DMAMUX_RGSR_OF7_Pos            (7U)

+#define DMAMUX_RGSR_OF7_Msk            (0x1UL << DMAMUX_RGSR_OF7_Pos)          /*!< 0x00000080 */

+#define DMAMUX_RGSR_OF7                DMAMUX_RGSR_OF7_Msk                     /*!< Request generator channel 7 Trigger overrun event flag */

+

+/********************  Bits definition for DMAMUX_RGCFR register  **************/

+#define DMAMUX_RGCFR_COF0_Pos          (0U)

+#define DMAMUX_RGCFR_COF0_Msk          (0x1UL << DMAMUX_RGCFR_COF0_Pos)        /*!< 0x00000001 */

+#define DMAMUX_RGCFR_COF0              DMAMUX_RGCFR_COF0_Msk                   /*!< Request generator channel 0 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF1_Pos          (1U)

+#define DMAMUX_RGCFR_COF1_Msk          (0x1UL << DMAMUX_RGCFR_COF1_Pos)        /*!< 0x00000002 */

+#define DMAMUX_RGCFR_COF1              DMAMUX_RGCFR_COF1_Msk                   /*!< Request generator channel 1 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF2_Pos          (2U)

+#define DMAMUX_RGCFR_COF2_Msk          (0x1UL << DMAMUX_RGCFR_COF2_Pos)        /*!< 0x00000004 */

+#define DMAMUX_RGCFR_COF2              DMAMUX_RGCFR_COF2_Msk                   /*!< Request generator channel 2 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF3_Pos          (3U)

+#define DMAMUX_RGCFR_COF3_Msk          (0x1UL << DMAMUX_RGCFR_COF3_Pos)        /*!< 0x00000008 */

+#define DMAMUX_RGCFR_COF3              DMAMUX_RGCFR_COF3_Msk                   /*!< Request generator channel 3 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF4_Pos          (4U)

+#define DMAMUX_RGCFR_COF4_Msk          (0x1UL << DMAMUX_RGCFR_COF4_Pos)        /*!< 0x00000010 */

+#define DMAMUX_RGCFR_COF4              DMAMUX_RGCFR_COF4_Msk                   /*!< Request generator channel 4 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF5_Pos          (5U)

+#define DMAMUX_RGCFR_COF5_Msk          (0x1UL << DMAMUX_RGCFR_COF5_Pos)        /*!< 0x00000020 */

+#define DMAMUX_RGCFR_COF5              DMAMUX_RGCFR_COF5_Msk                   /*!< Request generator channel 5 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF6_Pos          (6U)

+#define DMAMUX_RGCFR_COF6_Msk          (0x1UL << DMAMUX_RGCFR_COF6_Pos)        /*!< 0x00000040 */

+#define DMAMUX_RGCFR_COF6              DMAMUX_RGCFR_COF6_Msk                   /*!< Request generator channel 6 Clear trigger overrun event flag */

+#define DMAMUX_RGCFR_COF7_Pos          (7U)

+#define DMAMUX_RGCFR_COF7_Msk          (0x1UL << DMAMUX_RGCFR_COF7_Pos)        /*!< 0x00000080 */

+#define DMAMUX_RGCFR_COF7              DMAMUX_RGCFR_COF7_Msk                   /*!< Request generator channel 7 Clear trigger overrun event flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         AHB Master DMA2D Controller (DMA2D)                */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for DMA2D_CR register  ******************/

+

+#define DMA2D_CR_START_Pos         (0U)

+#define DMA2D_CR_START_Msk         (0x1UL << DMA2D_CR_START_Pos)               /*!< 0x00000001 */

+#define DMA2D_CR_START             DMA2D_CR_START_Msk                          /*!< Start transfer                          */

+#define DMA2D_CR_SUSP_Pos          (1U)

+#define DMA2D_CR_SUSP_Msk          (0x1UL << DMA2D_CR_SUSP_Pos)                /*!< 0x00000002 */

+#define DMA2D_CR_SUSP              DMA2D_CR_SUSP_Msk                           /*!< Suspend transfer                        */

+#define DMA2D_CR_ABORT_Pos         (2U)

+#define DMA2D_CR_ABORT_Msk         (0x1UL << DMA2D_CR_ABORT_Pos)               /*!< 0x00000004 */

+#define DMA2D_CR_ABORT             DMA2D_CR_ABORT_Msk                          /*!< Abort transfer                          */

+#define DMA2D_CR_LOM_Pos           (6U)

+#define DMA2D_CR_LOM_Msk           (0x1UL << DMA2D_CR_LOM_Pos)                 /*!< 0x00000040 */

+#define DMA2D_CR_LOM               DMA2D_CR_LOM_Msk                            /*!< Line Offset Mode                         */

+#define DMA2D_CR_TEIE_Pos          (8U)

+#define DMA2D_CR_TEIE_Msk          (0x1UL << DMA2D_CR_TEIE_Pos)                /*!< 0x00000100 */

+#define DMA2D_CR_TEIE              DMA2D_CR_TEIE_Msk                           /*!< Transfer Error Interrupt Enable         */

+#define DMA2D_CR_TCIE_Pos          (9U)

+#define DMA2D_CR_TCIE_Msk          (0x1UL << DMA2D_CR_TCIE_Pos)                /*!< 0x00000200 */

+#define DMA2D_CR_TCIE              DMA2D_CR_TCIE_Msk                           /*!< Transfer Complete Interrupt Enable      */

+#define DMA2D_CR_TWIE_Pos          (10U)

+#define DMA2D_CR_TWIE_Msk          (0x1UL << DMA2D_CR_TWIE_Pos)                /*!< 0x00000400 */

+#define DMA2D_CR_TWIE              DMA2D_CR_TWIE_Msk                           /*!< Transfer Watermark Interrupt Enable     */

+#define DMA2D_CR_CAEIE_Pos         (11U)

+#define DMA2D_CR_CAEIE_Msk         (0x1UL << DMA2D_CR_CAEIE_Pos)               /*!< 0x00000800 */

+#define DMA2D_CR_CAEIE             DMA2D_CR_CAEIE_Msk                          /*!< CLUT Access Error Interrupt Enable      */

+#define DMA2D_CR_CTCIE_Pos         (12U)

+#define DMA2D_CR_CTCIE_Msk         (0x1UL << DMA2D_CR_CTCIE_Pos)               /*!< 0x00001000 */

+#define DMA2D_CR_CTCIE             DMA2D_CR_CTCIE_Msk                          /*!< CLUT Transfer Complete Interrupt Enable */

+#define DMA2D_CR_CEIE_Pos          (13U)

+#define DMA2D_CR_CEIE_Msk          (0x1UL << DMA2D_CR_CEIE_Pos)                /*!< 0x00002000 */

+#define DMA2D_CR_CEIE              DMA2D_CR_CEIE_Msk                           /*!< Configuration Error Interrupt Enable    */

+#define DMA2D_CR_MODE_Pos          (16U)

+#define DMA2D_CR_MODE_Msk          (0x7UL << DMA2D_CR_MODE_Pos)                /*!< 0x00070000 */

+#define DMA2D_CR_MODE              DMA2D_CR_MODE_Msk                           /*!< DMA2D Mode[2:0]                         */

+#define DMA2D_CR_MODE_0            (0x1UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00010000 */

+#define DMA2D_CR_MODE_1            (0x2UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00020000 */

+#define DMA2D_CR_MODE_2            (0x4UL << DMA2D_CR_MODE_Pos)                 /*!< 0x00040000 */

+

+/********************  Bit definition for DMA2D_ISR register  *****************/

+

+#define DMA2D_ISR_TEIF_Pos         (0U)

+#define DMA2D_ISR_TEIF_Msk         (0x1UL << DMA2D_ISR_TEIF_Pos)               /*!< 0x00000001 */

+#define DMA2D_ISR_TEIF             DMA2D_ISR_TEIF_Msk                          /*!< Transfer Error Interrupt Flag         */

+#define DMA2D_ISR_TCIF_Pos         (1U)

+#define DMA2D_ISR_TCIF_Msk         (0x1UL << DMA2D_ISR_TCIF_Pos)               /*!< 0x00000002 */

+#define DMA2D_ISR_TCIF             DMA2D_ISR_TCIF_Msk                          /*!< Transfer Complete Interrupt Flag      */

+#define DMA2D_ISR_TWIF_Pos         (2U)

+#define DMA2D_ISR_TWIF_Msk         (0x1UL << DMA2D_ISR_TWIF_Pos)               /*!< 0x00000004 */

+#define DMA2D_ISR_TWIF             DMA2D_ISR_TWIF_Msk                          /*!< Transfer Watermark Interrupt Flag     */

+#define DMA2D_ISR_CAEIF_Pos        (3U)

+#define DMA2D_ISR_CAEIF_Msk        (0x1UL << DMA2D_ISR_CAEIF_Pos)              /*!< 0x00000008 */

+#define DMA2D_ISR_CAEIF            DMA2D_ISR_CAEIF_Msk                         /*!< CLUT Access Error Interrupt Flag      */

+#define DMA2D_ISR_CTCIF_Pos        (4U)

+#define DMA2D_ISR_CTCIF_Msk        (0x1UL << DMA2D_ISR_CTCIF_Pos)              /*!< 0x00000010 */

+#define DMA2D_ISR_CTCIF            DMA2D_ISR_CTCIF_Msk                         /*!< CLUT Transfer Complete Interrupt Flag */

+#define DMA2D_ISR_CEIF_Pos         (5U)

+#define DMA2D_ISR_CEIF_Msk         (0x1UL << DMA2D_ISR_CEIF_Pos)               /*!< 0x00000020 */

+#define DMA2D_ISR_CEIF             DMA2D_ISR_CEIF_Msk                          /*!< Configuration Error Interrupt Flag    */

+

+/********************  Bit definition for DMA2D_IFCR register  ****************/

+

+#define DMA2D_IFCR_CTEIF_Pos       (0U)

+#define DMA2D_IFCR_CTEIF_Msk       (0x1UL << DMA2D_IFCR_CTEIF_Pos)             /*!< 0x00000001 */

+#define DMA2D_IFCR_CTEIF           DMA2D_IFCR_CTEIF_Msk                        /*!< Clears Transfer Error Interrupt Flag         */

+#define DMA2D_IFCR_CTCIF_Pos       (1U)

+#define DMA2D_IFCR_CTCIF_Msk       (0x1UL << DMA2D_IFCR_CTCIF_Pos)             /*!< 0x00000002 */

+#define DMA2D_IFCR_CTCIF           DMA2D_IFCR_CTCIF_Msk                        /*!< Clears Transfer Complete Interrupt Flag      */

+#define DMA2D_IFCR_CTWIF_Pos       (2U)

+#define DMA2D_IFCR_CTWIF_Msk       (0x1UL << DMA2D_IFCR_CTWIF_Pos)             /*!< 0x00000004 */

+#define DMA2D_IFCR_CTWIF           DMA2D_IFCR_CTWIF_Msk                        /*!< Clears Transfer Watermark Interrupt Flag     */

+#define DMA2D_IFCR_CAECIF_Pos      (3U)

+#define DMA2D_IFCR_CAECIF_Msk      (0x1UL << DMA2D_IFCR_CAECIF_Pos)            /*!< 0x00000008 */

+#define DMA2D_IFCR_CAECIF          DMA2D_IFCR_CAECIF_Msk                       /*!< Clears CLUT Access Error Interrupt Flag      */

+#define DMA2D_IFCR_CCTCIF_Pos      (4U)

+#define DMA2D_IFCR_CCTCIF_Msk      (0x1UL << DMA2D_IFCR_CCTCIF_Pos)            /*!< 0x00000010 */

+#define DMA2D_IFCR_CCTCIF          DMA2D_IFCR_CCTCIF_Msk                       /*!< Clears CLUT Transfer Complete Interrupt Flag */

+#define DMA2D_IFCR_CCEIF_Pos       (5U)

+#define DMA2D_IFCR_CCEIF_Msk       (0x1UL << DMA2D_IFCR_CCEIF_Pos)             /*!< 0x00000020 */

+#define DMA2D_IFCR_CCEIF           DMA2D_IFCR_CCEIF_Msk                        /*!< Clears Configuration Error Interrupt Flag    */

+

+/********************  Bit definition for DMA2D_FGMAR register  ***************/

+

+#define DMA2D_FGMAR_MA_Pos         (0U)

+#define DMA2D_FGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos)        /*!< 0xFFFFFFFF */

+#define DMA2D_FGMAR_MA             DMA2D_FGMAR_MA_Msk                          /*!< Foreground Memory Address */

+

+/********************  Bit definition for DMA2D_FGOR register  ****************/

+

+#define DMA2D_FGOR_LO_Pos          (0U)

+#define DMA2D_FGOR_LO_Msk          (0xFFFFUL << DMA2D_FGOR_LO_Pos)             /*!< 0x0000FFFF */

+#define DMA2D_FGOR_LO              DMA2D_FGOR_LO_Msk                           /*!< Line Offset */

+

+/********************  Bit definition for DMA2D_BGMAR register  ***************/

+

+#define DMA2D_BGMAR_MA_Pos         (0U)

+#define DMA2D_BGMAR_MA_Msk         (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos)        /*!< 0xFFFFFFFF */

+#define DMA2D_BGMAR_MA             DMA2D_BGMAR_MA_Msk                          /*!< Background Memory Address */

+

+/********************  Bit definition for DMA2D_BGOR register  ****************/

+

+#define DMA2D_BGOR_LO_Pos          (0U)

+#define DMA2D_BGOR_LO_Msk          (0xFFFFUL << DMA2D_BGOR_LO_Pos)             /*!< 0x0000FFFF */

+#define DMA2D_BGOR_LO              DMA2D_BGOR_LO_Msk                           /*!< Line Offset */

+

+/********************  Bit definition for DMA2D_FGPFCCR register  *************/

+

+#define DMA2D_FGPFCCR_CM_Pos       (0U)

+#define DMA2D_FGPFCCR_CM_Msk       (0xFUL << DMA2D_FGPFCCR_CM_Pos)             /*!< 0x0000000F */

+#define DMA2D_FGPFCCR_CM           DMA2D_FGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */

+#define DMA2D_FGPFCCR_CM_0         (0x1UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_FGPFCCR_CM_1         (0x2UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_FGPFCCR_CM_2         (0x4UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_FGPFCCR_CM_3         (0x8UL << DMA2D_FGPFCCR_CM_Pos)              /*!< 0x00000008 */

+#define DMA2D_FGPFCCR_CCM_Pos      (4U)

+#define DMA2D_FGPFCCR_CCM_Msk      (0x1UL << DMA2D_FGPFCCR_CCM_Pos)            /*!< 0x00000010 */

+#define DMA2D_FGPFCCR_CCM          DMA2D_FGPFCCR_CCM_Msk                       /*!< CLUT Color mode */

+#define DMA2D_FGPFCCR_START_Pos    (5U)

+#define DMA2D_FGPFCCR_START_Msk    (0x1UL << DMA2D_FGPFCCR_START_Pos)          /*!< 0x00000020 */

+#define DMA2D_FGPFCCR_START        DMA2D_FGPFCCR_START_Msk                     /*!< Start */

+#define DMA2D_FGPFCCR_CS_Pos       (8U)

+#define DMA2D_FGPFCCR_CS_Msk       (0xFFUL << DMA2D_FGPFCCR_CS_Pos)            /*!< 0x0000FF00 */

+#define DMA2D_FGPFCCR_CS           DMA2D_FGPFCCR_CS_Msk                        /*!< CLUT size */

+#define DMA2D_FGPFCCR_AM_Pos       (16U)

+#define DMA2D_FGPFCCR_AM_Msk       (0x3UL << DMA2D_FGPFCCR_AM_Pos)             /*!< 0x00030000 */

+#define DMA2D_FGPFCCR_AM           DMA2D_FGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */

+#define DMA2D_FGPFCCR_AM_0         (0x1UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00010000 */

+#define DMA2D_FGPFCCR_AM_1         (0x2UL << DMA2D_FGPFCCR_AM_Pos)              /*!< 0x00020000 */

+#define DMA2D_FGPFCCR_CSS_Pos      (18U)

+#define DMA2D_FGPFCCR_CSS_Msk      (0x3UL << DMA2D_FGPFCCR_CSS_Pos)            /*!< 0x000C0000 */

+#define DMA2D_FGPFCCR_CSS          DMA2D_FGPFCCR_CSS_Msk                       /* !< Chroma Sub-Sampling */

+#define DMA2D_FGPFCCR_CSS_0        (0x1UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00040000 */

+#define DMA2D_FGPFCCR_CSS_1        (0x2UL << DMA2D_FGPFCCR_CSS_Pos)             /*!< 0x00080000 */

+#define DMA2D_FGPFCCR_AI_Pos       (20U)

+#define DMA2D_FGPFCCR_AI_Msk       (0x1UL << DMA2D_FGPFCCR_AI_Pos)             /*!< 0x00100000 */

+#define DMA2D_FGPFCCR_AI           DMA2D_FGPFCCR_AI_Msk                        /*!< Foreground Input Alpha Inverted */

+#define DMA2D_FGPFCCR_RBS_Pos      (21U)

+#define DMA2D_FGPFCCR_RBS_Msk      (0x1UL << DMA2D_FGPFCCR_RBS_Pos)            /*!< 0x00200000 */

+#define DMA2D_FGPFCCR_RBS          DMA2D_FGPFCCR_RBS_Msk                       /*!< Foreground Input Red Blue Swap */

+#define DMA2D_FGPFCCR_ALPHA_Pos    (24U)

+#define DMA2D_FGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */

+#define DMA2D_FGPFCCR_ALPHA        DMA2D_FGPFCCR_ALPHA_Msk                     /*!< Alpha value */

+

+/********************  Bit definition for DMA2D_FGCOLR register  **************/

+

+#define DMA2D_FGCOLR_BLUE_Pos      (0U)

+#define DMA2D_FGCOLR_BLUE_Msk      (0xFFUL << DMA2D_FGCOLR_BLUE_Pos)           /*!< 0x000000FF */

+#define DMA2D_FGCOLR_BLUE          DMA2D_FGCOLR_BLUE_Msk                       /*!< Foreground Blue Value */

+#define DMA2D_FGCOLR_GREEN_Pos     (8U)

+#define DMA2D_FGCOLR_GREEN_Msk     (0xFFUL << DMA2D_FGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */

+#define DMA2D_FGCOLR_GREEN         DMA2D_FGCOLR_GREEN_Msk                      /*!< Foreground Green Value */

+#define DMA2D_FGCOLR_RED_Pos       (16U)

+#define DMA2D_FGCOLR_RED_Msk       (0xFFUL << DMA2D_FGCOLR_RED_Pos)            /*!< 0x00FF0000 */

+#define DMA2D_FGCOLR_RED           DMA2D_FGCOLR_RED_Msk                        /*!< Foreground Red Value */

+

+/********************  Bit definition for DMA2D_BGPFCCR register  *************/

+

+#define DMA2D_BGPFCCR_CM_Pos       (0U)

+#define DMA2D_BGPFCCR_CM_Msk       (0xFUL << DMA2D_BGPFCCR_CM_Pos)             /*!< 0x0000000F */

+#define DMA2D_BGPFCCR_CM           DMA2D_BGPFCCR_CM_Msk                        /*!< Input color mode CM[3:0] */

+#define DMA2D_BGPFCCR_CM_0         (0x1UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_BGPFCCR_CM_1         (0x2UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_BGPFCCR_CM_2         (0x4UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_BGPFCCR_CM_3         (0x8UL << DMA2D_BGPFCCR_CM_Pos)              /*!< 0x00000008 */

+#define DMA2D_BGPFCCR_CCM_Pos      (4U)

+#define DMA2D_BGPFCCR_CCM_Msk      (0x1UL << DMA2D_BGPFCCR_CCM_Pos)            /*!< 0x00000010 */

+#define DMA2D_BGPFCCR_CCM          DMA2D_BGPFCCR_CCM_Msk                       /*!< CLUT Color mode */

+#define DMA2D_BGPFCCR_START_Pos    (5U)

+#define DMA2D_BGPFCCR_START_Msk    (0x1UL << DMA2D_BGPFCCR_START_Pos)          /*!< 0x00000020 */

+#define DMA2D_BGPFCCR_START        DMA2D_BGPFCCR_START_Msk                     /*!< Start */

+#define DMA2D_BGPFCCR_CS_Pos       (8U)

+#define DMA2D_BGPFCCR_CS_Msk       (0xFFUL << DMA2D_BGPFCCR_CS_Pos)            /*!< 0x0000FF00 */

+#define DMA2D_BGPFCCR_CS           DMA2D_BGPFCCR_CS_Msk                        /*!< CLUT size */

+#define DMA2D_BGPFCCR_AM_Pos       (16U)

+#define DMA2D_BGPFCCR_AM_Msk       (0x3UL << DMA2D_BGPFCCR_AM_Pos)             /*!< 0x00030000 */

+#define DMA2D_BGPFCCR_AM           DMA2D_BGPFCCR_AM_Msk                        /*!< Alpha mode AM[1:0] */

+#define DMA2D_BGPFCCR_AM_0         (0x1UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00010000 */

+#define DMA2D_BGPFCCR_AM_1         (0x2UL << DMA2D_BGPFCCR_AM_Pos)              /*!< 0x00020000 */

+#define DMA2D_BGPFCCR_AI_Pos       (20U)

+#define DMA2D_BGPFCCR_AI_Msk       (0x1UL << DMA2D_BGPFCCR_AI_Pos)             /*!< 0x00100000 */

+#define DMA2D_BGPFCCR_AI           DMA2D_BGPFCCR_AI_Msk                        /*!< background Input Alpha Inverted */

+#define DMA2D_BGPFCCR_RBS_Pos      (21U)

+#define DMA2D_BGPFCCR_RBS_Msk      (0x1UL << DMA2D_BGPFCCR_RBS_Pos)            /*!< 0x00200000 */

+#define DMA2D_BGPFCCR_RBS          DMA2D_BGPFCCR_RBS_Msk                       /*!< Background Input Red Blue Swap */

+#define DMA2D_BGPFCCR_ALPHA_Pos    (24U)

+#define DMA2D_BGPFCCR_ALPHA_Msk    (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos)         /*!< 0xFF000000 */

+#define DMA2D_BGPFCCR_ALPHA        DMA2D_BGPFCCR_ALPHA_Msk                     /*!< background Input Alpha value */

+

+/********************  Bit definition for DMA2D_BGCOLR register  **************/

+

+#define DMA2D_BGCOLR_BLUE_Pos      (0U)

+#define DMA2D_BGCOLR_BLUE_Msk      (0xFFUL << DMA2D_BGCOLR_BLUE_Pos)           /*!< 0x000000FF */

+#define DMA2D_BGCOLR_BLUE          DMA2D_BGCOLR_BLUE_Msk                       /*!< Background Blue Value */

+#define DMA2D_BGCOLR_GREEN_Pos     (8U)

+#define DMA2D_BGCOLR_GREEN_Msk     (0xFFUL << DMA2D_BGCOLR_GREEN_Pos)          /*!< 0x0000FF00 */

+#define DMA2D_BGCOLR_GREEN         DMA2D_BGCOLR_GREEN_Msk                      /*!< Background Green Value */

+#define DMA2D_BGCOLR_RED_Pos       (16U)

+#define DMA2D_BGCOLR_RED_Msk       (0xFFUL << DMA2D_BGCOLR_RED_Pos)            /*!< 0x00FF0000 */

+#define DMA2D_BGCOLR_RED           DMA2D_BGCOLR_RED_Msk                        /*!< Background Red Value */

+

+/********************  Bit definition for DMA2D_FGCMAR register  **************/

+

+#define DMA2D_FGCMAR_MA_Pos        (0U)

+#define DMA2D_FGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */

+#define DMA2D_FGCMAR_MA            DMA2D_FGCMAR_MA_Msk                         /*!< Foreground CLUT Memory Address */

+

+/********************  Bit definition for DMA2D_BGCMAR register  **************/

+

+#define DMA2D_BGCMAR_MA_Pos        (0U)

+#define DMA2D_BGCMAR_MA_Msk        (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos)       /*!< 0xFFFFFFFF */

+#define DMA2D_BGCMAR_MA            DMA2D_BGCMAR_MA_Msk                         /*!< Background CLUT Memory Address */

+

+/********************  Bit definition for DMA2D_OPFCCR register  **************/

+

+#define DMA2D_OPFCCR_CM_Pos        (0U)

+#define DMA2D_OPFCCR_CM_Msk        (0x7UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000007 */

+#define DMA2D_OPFCCR_CM            DMA2D_OPFCCR_CM_Msk                         /*!< Output Color mode CM[2:0] */

+#define DMA2D_OPFCCR_CM_0          (0x1UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000001 */

+#define DMA2D_OPFCCR_CM_1          (0x2UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000002 */

+#define DMA2D_OPFCCR_CM_2          (0x4UL << DMA2D_OPFCCR_CM_Pos)              /*!< 0x00000004 */

+#define DMA2D_OPFCCR_SB_Pos        (8U)

+#define DMA2D_OPFCCR_SB_Msk        (0x1UL << DMA2D_OPFCCR_SB_Pos)              /*!< 0x00000100 */

+#define DMA2D_OPFCCR_SB            DMA2D_OPFCCR_SB_Msk                         /*!< Swap Bytes */

+#define DMA2D_OPFCCR_AI_Pos        (20U)

+#define DMA2D_OPFCCR_AI_Msk        (0x1UL << DMA2D_OPFCCR_AI_Pos)              /*!< 0x00100000 */

+#define DMA2D_OPFCCR_AI            DMA2D_OPFCCR_AI_Msk                         /*!< Output Alpha Inverted */

+#define DMA2D_OPFCCR_RBS_Pos       (21U)

+#define DMA2D_OPFCCR_RBS_Msk       (0x1UL << DMA2D_OPFCCR_RBS_Pos)             /*!< 0x00200000 */

+#define DMA2D_OPFCCR_RBS           DMA2D_OPFCCR_RBS_Msk                        /*!< Output Red Blue Swap */

+

+/********************  Bit definition for DMA2D_OCOLR register  ***************/

+

+/*!<Mode_ARGB8888/RGB888 */

+

+#define DMA2D_OCOLR_BLUE_1_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_1_Msk     (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos)            /*0x000000FFU*/

+#define DMA2D_OCOLR_BLUE_1         DMA2D_OCOLR_BLUE_1_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_1_Pos    (8U)

+#define DMA2D_OCOLR_GREEN_1_Msk    (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos)            /*0x0000FF00U)*/

+#define DMA2D_OCOLR_GREEN_1        DMA2D_OCOLR_GREEN_1_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_1_Pos      (16U)

+#define DMA2D_OCOLR_RED_1_Msk      (0xFFUL << DMA2D_OCOLR_RED_1_Pos)            /*0x00FF0000U */

+#define DMA2D_OCOLR_RED_1          DMA2D_OCOLR_RED_1_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_1_Pos    (24U)

+#define DMA2D_OCOLR_ALPHA_1_Msk    (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos)          /*0xFF000000U*/

+#define DMA2D_OCOLR_ALPHA_1        DMA2D_OCOLR_ALPHA_1_Msk                     /*!< Output Alpha Channel Value */

+

+/*!<Mode_RGB565 */

+#define DMA2D_OCOLR_BLUE_2_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_2_Msk     (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos)            /*0x0000001FU*/

+#define DMA2D_OCOLR_BLUE_2         DMA2D_OCOLR_BLUE_2_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_2_Pos    (5U)

+#define DMA2D_OCOLR_GREEN_2_Msk    (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos)          /* 0x000007E0U */

+#define DMA2D_OCOLR_GREEN_2        DMA2D_OCOLR_GREEN_2_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_2_Pos      (11U)

+#define DMA2D_OCOLR_RED_2_Msk      (0xF8UL<<DMA2D_OCOLR_RED_2_Pos)              /*0x0000F800U*/

+#define DMA2D_OCOLR_RED_2          DMA2D_OCOLR_RED_2_Msk                       /*!< Output Red Value */

+

+/*!<Mode_ARGB1555 */

+#define DMA2D_OCOLR_BLUE_3_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_3_Msk     (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos)           /*0x0000001FU*/

+#define DMA2D_OCOLR_BLUE_3         DMA2D_OCOLR_BLUE_3_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_3_Pos    (5U)

+#define DMA2D_OCOLR_GREEN_3_Msk    (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos)          /*0x000003E0U*/

+#define DMA2D_OCOLR_GREEN_3        DMA2D_OCOLR_GREEN_3_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_3_Pos      (10U)

+#define DMA2D_OCOLR_RED_3_Msk      (0x7CUL << DMA2D_OCOLR_RED_3_Pos)            /* 0x00007C00U*/

+#define DMA2D_OCOLR_RED_3          DMA2D_OCOLR_RED_3_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_3_Pos    (15U)

+#define DMA2D_OCOLR_ALPHA_3_Msk    (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos)           /*0x00008000U*/

+#define DMA2D_OCOLR_ALPHA_3        DMA2D_OCOLR_ALPHA_3_Msk                     /*!< Output Alpha Channel Value */

+

+/*!<Mode_ARGB4444 */

+#define DMA2D_OCOLR_BLUE_4_Pos     (0U)

+#define DMA2D_OCOLR_BLUE_4_Msk     (0xFUL << DMA2D_OCOLR_BLUE_4_Pos)            /*0x0000000FU*/

+#define DMA2D_OCOLR_BLUE_4         DMA2D_OCOLR_BLUE_4_Msk                      /*!< Output BLUE Value */

+#define DMA2D_OCOLR_GREEN_4_Pos    (4U)

+#define DMA2D_OCOLR_GREEN_4_Msk    (0xFUL << DMA2D_OCOLR_GREEN_4_Pos)           /*0x000000F0U*/

+#define DMA2D_OCOLR_GREEN_4        DMA2D_OCOLR_GREEN_4_Msk                     /*!< Output GREEN Value  */

+#define DMA2D_OCOLR_RED_4_Pos      (8U)

+#define DMA2D_OCOLR_RED_4_Msk      (0xFUL << DMA2D_OCOLR_RED_4_Pos)             /*0x00000F00U*/

+#define DMA2D_OCOLR_RED_4          DMA2D_OCOLR_RED_4_Msk                       /*!< Output Red Value */

+#define DMA2D_OCOLR_ALPHA_4_Pos    (12U)

+#define DMA2D_OCOLR_ALPHA_4_Msk    (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos)            /*0x0000F000U*/

+#define DMA2D_OCOLR_ALPHA_4        DMA2D_OCOLR_ALPHA_4_Msk                     /*!< Output Alpha Channel Value */

+

+/********************  Bit definition for DMA2D_OMAR register  ****************/

+

+#define DMA2D_OMAR_MA_Pos          (0U)

+#define DMA2D_OMAR_MA_Msk          (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos)         /*!< 0xFFFFFFFF */

+#define DMA2D_OMAR_MA              DMA2D_OMAR_MA_Msk                           /*!< Output Memory Address */

+

+/********************  Bit definition for DMA2D_OOR register  *****************/

+

+#define DMA2D_OOR_LO_Pos           (0U)

+#define DMA2D_OOR_LO_Msk           (0xFFFFUL << DMA2D_OOR_LO_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_OOR_LO               DMA2D_OOR_LO_Msk                            /*!< Output Line Offset */

+

+/********************  Bit definition for DMA2D_NLR register  *****************/

+

+#define DMA2D_NLR_NL_Pos           (0U)

+#define DMA2D_NLR_NL_Msk           (0xFFFFUL << DMA2D_NLR_NL_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_NLR_NL               DMA2D_NLR_NL_Msk                            /*!< Number of Lines */

+#define DMA2D_NLR_PL_Pos           (16U)

+#define DMA2D_NLR_PL_Msk           (0x3FFFUL << DMA2D_NLR_PL_Pos)              /*!< 0x3FFF0000 */

+#define DMA2D_NLR_PL               DMA2D_NLR_PL_Msk                            /*!< Pixel per Lines */

+

+/********************  Bit definition for DMA2D_LWR register  *****************/

+

+#define DMA2D_LWR_LW_Pos           (0U)

+#define DMA2D_LWR_LW_Msk           (0xFFFFUL << DMA2D_LWR_LW_Pos)              /*!< 0x0000FFFF */

+#define DMA2D_LWR_LW               DMA2D_LWR_LW_Msk                            /*!< Line Watermark */

+

+/********************  Bit definition for DMA2D_AMTCR register  ***************/

+

+#define DMA2D_AMTCR_EN_Pos         (0U)

+#define DMA2D_AMTCR_EN_Msk         (0x1UL << DMA2D_AMTCR_EN_Pos)               /*!< 0x00000001 */

+#define DMA2D_AMTCR_EN             DMA2D_AMTCR_EN_Msk                          /*!< Enable */

+#define DMA2D_AMTCR_DT_Pos         (8U)

+#define DMA2D_AMTCR_DT_Msk         (0xFFUL << DMA2D_AMTCR_DT_Pos)              /*!< 0x0000FF00 */

+#define DMA2D_AMTCR_DT             DMA2D_AMTCR_DT_Msk                          /*!< Dead Time */

+

+

+/********************  Bit definition for DMA2D_FGCLUT register  **************/

+

+/********************  Bit definition for DMA2D_BGCLUT register  **************/

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                    External Interrupt/Event Controller                     */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for EXTI_RTSR1 register  *******************/

+#define EXTI_RTSR1_TR_Pos          (0U)

+#define EXTI_RTSR1_TR_Msk          (0x3FFFFFUL << EXTI_RTSR1_TR_Pos)           /*!< 0x003FFFFF */

+#define EXTI_RTSR1_TR              EXTI_RTSR1_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR1_TR0_Pos         (0U)

+#define EXTI_RTSR1_TR0_Msk         (0x1UL << EXTI_RTSR1_TR0_Pos)               /*!< 0x00000001 */

+#define EXTI_RTSR1_TR0             EXTI_RTSR1_TR0_Msk                          /*!< Rising trigger event configuration bit of line 0 */

+#define EXTI_RTSR1_TR1_Pos         (1U)

+#define EXTI_RTSR1_TR1_Msk         (0x1UL << EXTI_RTSR1_TR1_Pos)               /*!< 0x00000002 */

+#define EXTI_RTSR1_TR1             EXTI_RTSR1_TR1_Msk                          /*!< Rising trigger event configuration bit of line 1 */

+#define EXTI_RTSR1_TR2_Pos         (2U)

+#define EXTI_RTSR1_TR2_Msk         (0x1UL << EXTI_RTSR1_TR2_Pos)               /*!< 0x00000004 */

+#define EXTI_RTSR1_TR2             EXTI_RTSR1_TR2_Msk                          /*!< Rising trigger event configuration bit of line 2 */

+#define EXTI_RTSR1_TR3_Pos         (3U)

+#define EXTI_RTSR1_TR3_Msk         (0x1UL << EXTI_RTSR1_TR3_Pos)               /*!< 0x00000008 */

+#define EXTI_RTSR1_TR3             EXTI_RTSR1_TR3_Msk                          /*!< Rising trigger event configuration bit of line 3 */

+#define EXTI_RTSR1_TR4_Pos         (4U)

+#define EXTI_RTSR1_TR4_Msk         (0x1UL << EXTI_RTSR1_TR4_Pos)               /*!< 0x00000010 */

+#define EXTI_RTSR1_TR4             EXTI_RTSR1_TR4_Msk                          /*!< Rising trigger event configuration bit of line 4 */

+#define EXTI_RTSR1_TR5_Pos         (5U)

+#define EXTI_RTSR1_TR5_Msk         (0x1UL << EXTI_RTSR1_TR5_Pos)               /*!< 0x00000020 */

+#define EXTI_RTSR1_TR5             EXTI_RTSR1_TR5_Msk                          /*!< Rising trigger event configuration bit of line 5 */

+#define EXTI_RTSR1_TR6_Pos         (6U)

+#define EXTI_RTSR1_TR6_Msk         (0x1UL << EXTI_RTSR1_TR6_Pos)               /*!< 0x00000040 */

+#define EXTI_RTSR1_TR6             EXTI_RTSR1_TR6_Msk                          /*!< Rising trigger event configuration bit of line 6 */

+#define EXTI_RTSR1_TR7_Pos         (7U)

+#define EXTI_RTSR1_TR7_Msk         (0x1UL << EXTI_RTSR1_TR7_Pos)               /*!< 0x00000080 */

+#define EXTI_RTSR1_TR7             EXTI_RTSR1_TR7_Msk                          /*!< Rising trigger event configuration bit of line 7 */

+#define EXTI_RTSR1_TR8_Pos         (8U)

+#define EXTI_RTSR1_TR8_Msk         (0x1UL << EXTI_RTSR1_TR8_Pos)               /*!< 0x00000100 */

+#define EXTI_RTSR1_TR8             EXTI_RTSR1_TR8_Msk                          /*!< Rising trigger event configuration bit of line 8 */

+#define EXTI_RTSR1_TR9_Pos         (9U)

+#define EXTI_RTSR1_TR9_Msk         (0x1UL << EXTI_RTSR1_TR9_Pos)               /*!< 0x00000200 */

+#define EXTI_RTSR1_TR9             EXTI_RTSR1_TR9_Msk                          /*!< Rising trigger event configuration bit of line 9 */

+#define EXTI_RTSR1_TR10_Pos        (10U)

+#define EXTI_RTSR1_TR10_Msk        (0x1UL << EXTI_RTSR1_TR10_Pos)              /*!< 0x00000400 */

+#define EXTI_RTSR1_TR10            EXTI_RTSR1_TR10_Msk                         /*!< Rising trigger event configuration bit of line 10 */

+#define EXTI_RTSR1_TR11_Pos        (11U)

+#define EXTI_RTSR1_TR11_Msk        (0x1UL << EXTI_RTSR1_TR11_Pos)              /*!< 0x00000800 */

+#define EXTI_RTSR1_TR11            EXTI_RTSR1_TR11_Msk                         /*!< Rising trigger event configuration bit of line 11 */

+#define EXTI_RTSR1_TR12_Pos        (12U)

+#define EXTI_RTSR1_TR12_Msk        (0x1UL << EXTI_RTSR1_TR12_Pos)              /*!< 0x00001000 */

+#define EXTI_RTSR1_TR12            EXTI_RTSR1_TR12_Msk                         /*!< Rising trigger event configuration bit of line 12 */

+#define EXTI_RTSR1_TR13_Pos        (13U)

+#define EXTI_RTSR1_TR13_Msk        (0x1UL << EXTI_RTSR1_TR13_Pos)              /*!< 0x00002000 */

+#define EXTI_RTSR1_TR13            EXTI_RTSR1_TR13_Msk                         /*!< Rising trigger event configuration bit of line 13 */

+#define EXTI_RTSR1_TR14_Pos        (14U)

+#define EXTI_RTSR1_TR14_Msk        (0x1UL << EXTI_RTSR1_TR14_Pos)              /*!< 0x00004000 */

+#define EXTI_RTSR1_TR14            EXTI_RTSR1_TR14_Msk                         /*!< Rising trigger event configuration bit of line 14 */

+#define EXTI_RTSR1_TR15_Pos        (15U)

+#define EXTI_RTSR1_TR15_Msk        (0x1UL << EXTI_RTSR1_TR15_Pos)              /*!< 0x00008000 */

+#define EXTI_RTSR1_TR15            EXTI_RTSR1_TR15_Msk                         /*!< Rising trigger event configuration bit of line 15 */

+#define EXTI_RTSR1_TR16_Pos        (16U)

+#define EXTI_RTSR1_TR16_Msk        (0x1UL << EXTI_RTSR1_TR16_Pos)              /*!< 0x00010000 */

+#define EXTI_RTSR1_TR16            EXTI_RTSR1_TR16_Msk                         /*!< Rising trigger event configuration bit of line 16 */

+#define EXTI_RTSR1_TR17_Pos        (17U)

+#define EXTI_RTSR1_TR17_Msk        (0x1UL << EXTI_RTSR1_TR17_Pos)              /*!< 0x00020000 */

+#define EXTI_RTSR1_TR17            EXTI_RTSR1_TR17_Msk                         /*!< Rising trigger event configuration bit of line 17 */

+#define EXTI_RTSR1_TR18_Pos        (18U)

+#define EXTI_RTSR1_TR18_Msk        (0x1UL << EXTI_RTSR1_TR18_Pos)              /*!< 0x00040000 */

+#define EXTI_RTSR1_TR18            EXTI_RTSR1_TR18_Msk                         /*!< Rising trigger event configuration bit of line 18 */

+#define EXTI_RTSR1_TR19_Pos        (19U)

+#define EXTI_RTSR1_TR19_Msk        (0x1UL << EXTI_RTSR1_TR19_Pos)              /*!< 0x00080000 */

+#define EXTI_RTSR1_TR19            EXTI_RTSR1_TR19_Msk                         /*!< Rising trigger event configuration bit of line 19 */

+#define EXTI_RTSR1_TR20_Pos        (20U)

+#define EXTI_RTSR1_TR20_Msk        (0x1UL << EXTI_RTSR1_TR20_Pos)              /*!< 0x00100000 */

+#define EXTI_RTSR1_TR20            EXTI_RTSR1_TR20_Msk                         /*!< Rising trigger event configuration bit of line 20 */

+#define EXTI_RTSR1_TR21_Pos        (21U)

+#define EXTI_RTSR1_TR21_Msk        (0x1UL << EXTI_RTSR1_TR21_Pos)              /*!< 0x00200000 */

+#define EXTI_RTSR1_TR21            EXTI_RTSR1_TR21_Msk                         /*!< Rising trigger event configuration bit of line 21 */

+

+/******************  Bit definition for EXTI_FTSR1 register  *******************/

+#define EXTI_FTSR1_TR_Pos          (0U)

+#define EXTI_FTSR1_TR_Msk          (0x3FFFFFUL << EXTI_FTSR1_TR_Pos)           /*!< 0x003FFFFF */

+#define EXTI_FTSR1_TR              EXTI_FTSR1_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR1_TR0_Pos         (0U)

+#define EXTI_FTSR1_TR0_Msk         (0x1UL << EXTI_FTSR1_TR0_Pos)               /*!< 0x00000001 */

+#define EXTI_FTSR1_TR0             EXTI_FTSR1_TR0_Msk                          /*!< Falling trigger event configuration bit of line 0 */

+#define EXTI_FTSR1_TR1_Pos         (1U)

+#define EXTI_FTSR1_TR1_Msk         (0x1UL << EXTI_FTSR1_TR1_Pos)               /*!< 0x00000002 */

+#define EXTI_FTSR1_TR1             EXTI_FTSR1_TR1_Msk                          /*!< Falling trigger event configuration bit of line 1 */

+#define EXTI_FTSR1_TR2_Pos         (2U)

+#define EXTI_FTSR1_TR2_Msk         (0x1UL << EXTI_FTSR1_TR2_Pos)               /*!< 0x00000004 */

+#define EXTI_FTSR1_TR2             EXTI_FTSR1_TR2_Msk                          /*!< Falling trigger event configuration bit of line 2 */

+#define EXTI_FTSR1_TR3_Pos         (3U)

+#define EXTI_FTSR1_TR3_Msk         (0x1UL << EXTI_FTSR1_TR3_Pos)               /*!< 0x00000008 */

+#define EXTI_FTSR1_TR3             EXTI_FTSR1_TR3_Msk                          /*!< Falling trigger event configuration bit of line 3 */

+#define EXTI_FTSR1_TR4_Pos         (4U)

+#define EXTI_FTSR1_TR4_Msk         (0x1UL << EXTI_FTSR1_TR4_Pos)               /*!< 0x00000010 */

+#define EXTI_FTSR1_TR4             EXTI_FTSR1_TR4_Msk                          /*!< Falling trigger event configuration bit of line 4 */

+#define EXTI_FTSR1_TR5_Pos         (5U)

+#define EXTI_FTSR1_TR5_Msk         (0x1UL << EXTI_FTSR1_TR5_Pos)               /*!< 0x00000020 */

+#define EXTI_FTSR1_TR5             EXTI_FTSR1_TR5_Msk                          /*!< Falling trigger event configuration bit of line 5 */

+#define EXTI_FTSR1_TR6_Pos         (6U)

+#define EXTI_FTSR1_TR6_Msk         (0x1UL << EXTI_FTSR1_TR6_Pos)               /*!< 0x00000040 */

+#define EXTI_FTSR1_TR6             EXTI_FTSR1_TR6_Msk                          /*!< Falling trigger event configuration bit of line 6 */

+#define EXTI_FTSR1_TR7_Pos         (7U)

+#define EXTI_FTSR1_TR7_Msk         (0x1UL << EXTI_FTSR1_TR7_Pos)               /*!< 0x00000080 */

+#define EXTI_FTSR1_TR7             EXTI_FTSR1_TR7_Msk                          /*!< Falling trigger event configuration bit of line 7 */

+#define EXTI_FTSR1_TR8_Pos         (8U)

+#define EXTI_FTSR1_TR8_Msk         (0x1UL << EXTI_FTSR1_TR8_Pos)               /*!< 0x00000100 */

+#define EXTI_FTSR1_TR8             EXTI_FTSR1_TR8_Msk                          /*!< Falling trigger event configuration bit of line 8 */

+#define EXTI_FTSR1_TR9_Pos         (9U)

+#define EXTI_FTSR1_TR9_Msk         (0x1UL << EXTI_FTSR1_TR9_Pos)               /*!< 0x00000200 */

+#define EXTI_FTSR1_TR9             EXTI_FTSR1_TR9_Msk                          /*!< Falling trigger event configuration bit of line 9 */

+#define EXTI_FTSR1_TR10_Pos        (10U)

+#define EXTI_FTSR1_TR10_Msk        (0x1UL << EXTI_FTSR1_TR10_Pos)              /*!< 0x00000400 */

+#define EXTI_FTSR1_TR10            EXTI_FTSR1_TR10_Msk                         /*!< Falling trigger event configuration bit of line 10 */

+#define EXTI_FTSR1_TR11_Pos        (11U)

+#define EXTI_FTSR1_TR11_Msk        (0x1UL << EXTI_FTSR1_TR11_Pos)              /*!< 0x00000800 */

+#define EXTI_FTSR1_TR11            EXTI_FTSR1_TR11_Msk                         /*!< Falling trigger event configuration bit of line 11 */

+#define EXTI_FTSR1_TR12_Pos        (12U)

+#define EXTI_FTSR1_TR12_Msk        (0x1UL << EXTI_FTSR1_TR12_Pos)              /*!< 0x00001000 */

+#define EXTI_FTSR1_TR12            EXTI_FTSR1_TR12_Msk                         /*!< Falling trigger event configuration bit of line 12 */

+#define EXTI_FTSR1_TR13_Pos        (13U)

+#define EXTI_FTSR1_TR13_Msk        (0x1UL << EXTI_FTSR1_TR13_Pos)              /*!< 0x00002000 */

+#define EXTI_FTSR1_TR13            EXTI_FTSR1_TR13_Msk                         /*!< Falling trigger event configuration bit of line 13 */

+#define EXTI_FTSR1_TR14_Pos        (14U)

+#define EXTI_FTSR1_TR14_Msk        (0x1UL << EXTI_FTSR1_TR14_Pos)              /*!< 0x00004000 */

+#define EXTI_FTSR1_TR14            EXTI_FTSR1_TR14_Msk                         /*!< Falling trigger event configuration bit of line 14 */

+#define EXTI_FTSR1_TR15_Pos        (15U)

+#define EXTI_FTSR1_TR15_Msk        (0x1UL << EXTI_FTSR1_TR15_Pos)              /*!< 0x00008000 */

+#define EXTI_FTSR1_TR15            EXTI_FTSR1_TR15_Msk                         /*!< Falling trigger event configuration bit of line 15 */

+#define EXTI_FTSR1_TR16_Pos        (16U)

+#define EXTI_FTSR1_TR16_Msk        (0x1UL << EXTI_FTSR1_TR16_Pos)              /*!< 0x00010000 */

+#define EXTI_FTSR1_TR16            EXTI_FTSR1_TR16_Msk                         /*!< Falling trigger event configuration bit of line 16 */

+#define EXTI_FTSR1_TR17_Pos        (17U)

+#define EXTI_FTSR1_TR17_Msk        (0x1UL << EXTI_FTSR1_TR17_Pos)              /*!< 0x00020000 */

+#define EXTI_FTSR1_TR17            EXTI_FTSR1_TR17_Msk                         /*!< Falling trigger event configuration bit of line 17 */

+#define EXTI_FTSR1_TR18_Pos        (18U)

+#define EXTI_FTSR1_TR18_Msk        (0x1UL << EXTI_FTSR1_TR18_Pos)              /*!< 0x00040000 */

+#define EXTI_FTSR1_TR18            EXTI_FTSR1_TR18_Msk                         /*!< Falling trigger event configuration bit of line 18 */

+#define EXTI_FTSR1_TR19_Pos        (19U)

+#define EXTI_FTSR1_TR19_Msk        (0x1UL << EXTI_FTSR1_TR19_Pos)              /*!< 0x00080000 */

+#define EXTI_FTSR1_TR19            EXTI_FTSR1_TR19_Msk                         /*!< Falling trigger event configuration bit of line 19 */

+#define EXTI_FTSR1_TR20_Pos        (20U)

+#define EXTI_FTSR1_TR20_Msk        (0x1UL << EXTI_FTSR1_TR20_Pos)              /*!< 0x00100000 */

+#define EXTI_FTSR1_TR20            EXTI_FTSR1_TR20_Msk                         /*!< Falling trigger event configuration bit of line 20 */

+#define EXTI_FTSR1_TR21_Pos        (21U)

+#define EXTI_FTSR1_TR21_Msk        (0x1UL << EXTI_FTSR1_TR21_Pos)              /*!< 0x00200000 */

+#define EXTI_FTSR1_TR21            EXTI_FTSR1_TR21_Msk                         /*!< Falling trigger event configuration bit of line 21 */

+

+/******************  Bit definition for EXTI_SWIER1 register  ******************/

+#define EXTI_SWIER1_SWIER0_Pos     (0U)

+#define EXTI_SWIER1_SWIER0_Msk     (0x1UL << EXTI_SWIER1_SWIER0_Pos)           /*!< 0x00000001 */

+#define EXTI_SWIER1_SWIER0         EXTI_SWIER1_SWIER0_Msk                      /*!< Software Interrupt on line 0 */

+#define EXTI_SWIER1_SWIER1_Pos     (1U)

+#define EXTI_SWIER1_SWIER1_Msk     (0x1UL << EXTI_SWIER1_SWIER1_Pos)           /*!< 0x00000002 */

+#define EXTI_SWIER1_SWIER1         EXTI_SWIER1_SWIER1_Msk                      /*!< Software Interrupt on line 1 */

+#define EXTI_SWIER1_SWIER2_Pos     (2U)

+#define EXTI_SWIER1_SWIER2_Msk     (0x1UL << EXTI_SWIER1_SWIER2_Pos)           /*!< 0x00000004 */

+#define EXTI_SWIER1_SWIER2         EXTI_SWIER1_SWIER2_Msk                      /*!< Software Interrupt on line 2 */

+#define EXTI_SWIER1_SWIER3_Pos     (3U)

+#define EXTI_SWIER1_SWIER3_Msk     (0x1UL << EXTI_SWIER1_SWIER3_Pos)           /*!< 0x00000008 */

+#define EXTI_SWIER1_SWIER3         EXTI_SWIER1_SWIER3_Msk                      /*!< Software Interrupt on line 3 */

+#define EXTI_SWIER1_SWIER4_Pos     (4U)

+#define EXTI_SWIER1_SWIER4_Msk     (0x1UL << EXTI_SWIER1_SWIER4_Pos)           /*!< 0x00000010 */

+#define EXTI_SWIER1_SWIER4         EXTI_SWIER1_SWIER4_Msk                      /*!< Software Interrupt on line 4 */

+#define EXTI_SWIER1_SWIER5_Pos     (5U)

+#define EXTI_SWIER1_SWIER5_Msk     (0x1UL << EXTI_SWIER1_SWIER5_Pos)           /*!< 0x00000020 */

+#define EXTI_SWIER1_SWIER5         EXTI_SWIER1_SWIER5_Msk                      /*!< Software Interrupt on line 5 */

+#define EXTI_SWIER1_SWIER6_Pos     (6U)

+#define EXTI_SWIER1_SWIER6_Msk     (0x1UL << EXTI_SWIER1_SWIER6_Pos)           /*!< 0x00000040 */

+#define EXTI_SWIER1_SWIER6         EXTI_SWIER1_SWIER6_Msk                      /*!< Software Interrupt on line 6 */

+#define EXTI_SWIER1_SWIER7_Pos     (7U)

+#define EXTI_SWIER1_SWIER7_Msk     (0x1UL << EXTI_SWIER1_SWIER7_Pos)           /*!< 0x00000080 */

+#define EXTI_SWIER1_SWIER7         EXTI_SWIER1_SWIER7_Msk                      /*!< Software Interrupt on line 7 */

+#define EXTI_SWIER1_SWIER8_Pos     (8U)

+#define EXTI_SWIER1_SWIER8_Msk     (0x1UL << EXTI_SWIER1_SWIER8_Pos)           /*!< 0x00000100 */

+#define EXTI_SWIER1_SWIER8         EXTI_SWIER1_SWIER8_Msk                      /*!< Software Interrupt on line 8 */

+#define EXTI_SWIER1_SWIER9_Pos     (9U)

+#define EXTI_SWIER1_SWIER9_Msk     (0x1UL << EXTI_SWIER1_SWIER9_Pos)           /*!< 0x00000200 */

+#define EXTI_SWIER1_SWIER9         EXTI_SWIER1_SWIER9_Msk                      /*!< Software Interrupt on line 9 */

+#define EXTI_SWIER1_SWIER10_Pos    (10U)

+#define EXTI_SWIER1_SWIER10_Msk    (0x1UL << EXTI_SWIER1_SWIER10_Pos)          /*!< 0x00000400 */

+#define EXTI_SWIER1_SWIER10        EXTI_SWIER1_SWIER10_Msk                     /*!< Software Interrupt on line 10 */

+#define EXTI_SWIER1_SWIER11_Pos    (11U)

+#define EXTI_SWIER1_SWIER11_Msk    (0x1UL << EXTI_SWIER1_SWIER11_Pos)          /*!< 0x00000800 */

+#define EXTI_SWIER1_SWIER11        EXTI_SWIER1_SWIER11_Msk                     /*!< Software Interrupt on line 11 */

+#define EXTI_SWIER1_SWIER12_Pos    (12U)

+#define EXTI_SWIER1_SWIER12_Msk    (0x1UL << EXTI_SWIER1_SWIER12_Pos)          /*!< 0x00001000 */

+#define EXTI_SWIER1_SWIER12        EXTI_SWIER1_SWIER12_Msk                     /*!< Software Interrupt on line 12 */

+#define EXTI_SWIER1_SWIER13_Pos    (13U)

+#define EXTI_SWIER1_SWIER13_Msk    (0x1UL << EXTI_SWIER1_SWIER13_Pos)          /*!< 0x00002000 */

+#define EXTI_SWIER1_SWIER13        EXTI_SWIER1_SWIER13_Msk                     /*!< Software Interrupt on line 13 */

+#define EXTI_SWIER1_SWIER14_Pos    (14U)

+#define EXTI_SWIER1_SWIER14_Msk    (0x1UL << EXTI_SWIER1_SWIER14_Pos)          /*!< 0x00004000 */

+#define EXTI_SWIER1_SWIER14        EXTI_SWIER1_SWIER14_Msk                     /*!< Software Interrupt on line 14 */

+#define EXTI_SWIER1_SWIER15_Pos    (15U)

+#define EXTI_SWIER1_SWIER15_Msk    (0x1UL << EXTI_SWIER1_SWIER15_Pos)          /*!< 0x00008000 */

+#define EXTI_SWIER1_SWIER15        EXTI_SWIER1_SWIER15_Msk                     /*!< Software Interrupt on line 15 */

+#define EXTI_SWIER1_SWIER16_Pos    (16U)

+#define EXTI_SWIER1_SWIER16_Msk    (0x1UL << EXTI_SWIER1_SWIER16_Pos)          /*!< 0x00010000 */

+#define EXTI_SWIER1_SWIER16        EXTI_SWIER1_SWIER16_Msk                     /*!< Software Interrupt on line 16 */

+#define EXTI_SWIER1_SWIER17_Pos    (17U)

+#define EXTI_SWIER1_SWIER17_Msk    (0x1UL << EXTI_SWIER1_SWIER17_Pos)          /*!< 0x00020000 */

+#define EXTI_SWIER1_SWIER17        EXTI_SWIER1_SWIER17_Msk                     /*!< Software Interrupt on line 17 */

+#define EXTI_SWIER1_SWIER18_Pos    (18U)

+#define EXTI_SWIER1_SWIER18_Msk    (0x1UL << EXTI_SWIER1_SWIER18_Pos)          /*!< 0x00040000 */

+#define EXTI_SWIER1_SWIER18        EXTI_SWIER1_SWIER18_Msk                     /*!< Software Interrupt on line 18 */

+#define EXTI_SWIER1_SWIER19_Pos    (19U)

+#define EXTI_SWIER1_SWIER19_Msk    (0x1UL << EXTI_SWIER1_SWIER19_Pos)          /*!< 0x00080000 */

+#define EXTI_SWIER1_SWIER19        EXTI_SWIER1_SWIER19_Msk                     /*!< Software Interrupt on line 19 */

+#define EXTI_SWIER1_SWIER20_Pos    (20U)

+#define EXTI_SWIER1_SWIER20_Msk    (0x1UL << EXTI_SWIER1_SWIER20_Pos)          /*!< 0x00100000 */

+#define EXTI_SWIER1_SWIER20        EXTI_SWIER1_SWIER20_Msk                     /*!< Software Interrupt on line 20 */

+#define EXTI_SWIER1_SWIER21_Pos    (21U)

+#define EXTI_SWIER1_SWIER21_Msk    (0x1UL << EXTI_SWIER1_SWIER21_Pos)          /*!< 0x00200000 */

+#define EXTI_SWIER1_SWIER21        EXTI_SWIER1_SWIER21_Msk                     /*!< Software Interrupt on line 21 */

+

+/******************  Bit definition for EXTI_D3PMR1 register  ******************/

+#define EXTI_D3PMR1_MR0_Pos        (0U)

+#define EXTI_D3PMR1_MR0_Msk        (0x1UL << EXTI_D3PMR1_MR0_Pos)              /*!< 0x00000001 */

+#define EXTI_D3PMR1_MR0            EXTI_D3PMR1_MR0_Msk                         /*!< Pending Mask Event for line 0  */

+#define EXTI_D3PMR1_MR1_Pos        (1U)

+#define EXTI_D3PMR1_MR1_Msk        (0x1UL << EXTI_D3PMR1_MR1_Pos)              /*!< 0x00000002 */

+#define EXTI_D3PMR1_MR1            EXTI_D3PMR1_MR1_Msk                         /*!< Pending Mask Event for line 1  */

+#define EXTI_D3PMR1_MR2_Pos        (2U)

+#define EXTI_D3PMR1_MR2_Msk        (0x1UL << EXTI_D3PMR1_MR2_Pos)              /*!< 0x00000004 */

+#define EXTI_D3PMR1_MR2            EXTI_D3PMR1_MR2_Msk                         /*!< Pending Mask Event for line 2  */

+#define EXTI_D3PMR1_MR3_Pos        (3U)

+#define EXTI_D3PMR1_MR3_Msk        (0x1UL << EXTI_D3PMR1_MR3_Pos)              /*!< 0x00000008 */

+#define EXTI_D3PMR1_MR3            EXTI_D3PMR1_MR3_Msk                         /*!< Pending Mask Event for line 3  */

+#define EXTI_D3PMR1_MR4_Pos        (4U)

+#define EXTI_D3PMR1_MR4_Msk        (0x1UL << EXTI_D3PMR1_MR4_Pos)              /*!< 0x00000010 */

+#define EXTI_D3PMR1_MR4            EXTI_D3PMR1_MR4_Msk                         /*!< Pending Mask Event for line 4  */

+#define EXTI_D3PMR1_MR5_Pos        (5U)

+#define EXTI_D3PMR1_MR5_Msk        (0x1UL << EXTI_D3PMR1_MR5_Pos)              /*!< 0x00000020 */

+#define EXTI_D3PMR1_MR5            EXTI_D3PMR1_MR5_Msk                         /*!< Pending Mask Event for line 5  */

+#define EXTI_D3PMR1_MR6_Pos        (6U)

+#define EXTI_D3PMR1_MR6_Msk        (0x1UL << EXTI_D3PMR1_MR6_Pos)              /*!< 0x00000040 */

+#define EXTI_D3PMR1_MR6            EXTI_D3PMR1_MR6_Msk                         /*!< Pending Mask Event for line 6  */

+#define EXTI_D3PMR1_MR7_Pos        (7U)

+#define EXTI_D3PMR1_MR7_Msk        (0x1UL << EXTI_D3PMR1_MR7_Pos)              /*!< 0x00000080 */

+#define EXTI_D3PMR1_MR7            EXTI_D3PMR1_MR7_Msk                         /*!< Pending Mask Event for line 7  */

+#define EXTI_D3PMR1_MR8_Pos        (8U)

+#define EXTI_D3PMR1_MR8_Msk        (0x1UL << EXTI_D3PMR1_MR8_Pos)              /*!< 0x00000100 */

+#define EXTI_D3PMR1_MR8            EXTI_D3PMR1_MR8_Msk                         /*!< Pending Mask Event for line 8  */

+#define EXTI_D3PMR1_MR9_Pos        (9U)

+#define EXTI_D3PMR1_MR9_Msk        (0x1UL << EXTI_D3PMR1_MR9_Pos)              /*!< 0x00000200 */

+#define EXTI_D3PMR1_MR9            EXTI_D3PMR1_MR9_Msk                         /*!< Pending Mask Event for line 9  */

+#define EXTI_D3PMR1_MR10_Pos       (10U)

+#define EXTI_D3PMR1_MR10_Msk       (0x1UL << EXTI_D3PMR1_MR10_Pos)             /*!< 0x00000400 */

+#define EXTI_D3PMR1_MR10           EXTI_D3PMR1_MR10_Msk                        /*!< Pending Mask Event for line 10 */

+#define EXTI_D3PMR1_MR11_Pos       (11U)

+#define EXTI_D3PMR1_MR11_Msk       (0x1UL << EXTI_D3PMR1_MR11_Pos)             /*!< 0x00000800 */

+#define EXTI_D3PMR1_MR11           EXTI_D3PMR1_MR11_Msk                        /*!< Pending Mask Event for line 11 */

+#define EXTI_D3PMR1_MR12_Pos       (12U)

+#define EXTI_D3PMR1_MR12_Msk       (0x1UL << EXTI_D3PMR1_MR12_Pos)             /*!< 0x00001000 */

+#define EXTI_D3PMR1_MR12           EXTI_D3PMR1_MR12_Msk                        /*!< Pending Mask Event for line 12 */

+#define EXTI_D3PMR1_MR13_Pos       (13U)

+#define EXTI_D3PMR1_MR13_Msk       (0x1UL << EXTI_D3PMR1_MR13_Pos)             /*!< 0x00002000 */

+#define EXTI_D3PMR1_MR13           EXTI_D3PMR1_MR13_Msk                        /*!< Pending Mask Event for line 13 */

+#define EXTI_D3PMR1_MR14_Pos       (14U)

+#define EXTI_D3PMR1_MR14_Msk       (0x1UL << EXTI_D3PMR1_MR14_Pos)             /*!< 0x00004000 */

+#define EXTI_D3PMR1_MR14           EXTI_D3PMR1_MR14_Msk                        /*!< Pending Mask Event for line 14 */

+#define EXTI_D3PMR1_MR15_Pos       (15U)

+#define EXTI_D3PMR1_MR15_Msk       (0x1UL << EXTI_D3PMR1_MR15_Pos)             /*!< 0x00008000 */

+#define EXTI_D3PMR1_MR15           EXTI_D3PMR1_MR15_Msk                        /*!< Pending Mask Event for line 15 */

+#define EXTI_D3PMR1_MR19_Pos       (19U)

+#define EXTI_D3PMR1_MR19_Msk       (0x1UL << EXTI_D3PMR1_MR19_Pos)             /*!< 0x00080000 */

+#define EXTI_D3PMR1_MR19           EXTI_D3PMR1_MR19_Msk                        /*!< Pending Mask Event for line 19 */

+#define EXTI_D3PMR1_MR20_Pos       (20U)

+#define EXTI_D3PMR1_MR20_Msk       (0x1UL << EXTI_D3PMR1_MR20_Pos)             /*!< 0x00100000 */

+#define EXTI_D3PMR1_MR20           EXTI_D3PMR1_MR20_Msk                        /*!< Pending Mask Event for line 20 */

+#define EXTI_D3PMR1_MR21_Pos       (21U)

+#define EXTI_D3PMR1_MR21_Msk       (0x1UL << EXTI_D3PMR1_MR21_Pos)             /*!< 0x00200000 */

+#define EXTI_D3PMR1_MR21           EXTI_D3PMR1_MR21_Msk                        /*!< Pending Mask Event for line 21 */

+#define EXTI_D3PMR1_MR25_Pos       (24U)

+#define EXTI_D3PMR1_MR25_Msk       (0x1UL << EXTI_D3PMR1_MR25_Pos)             /*!< 0x01000000 */

+#define EXTI_D3PMR1_MR25           EXTI_D3PMR1_MR25_Msk                        /*!< Pending Mask Event for line 25 */

+

+/*******************  Bit definition for EXTI_D3PCR1L register  ****************/

+#define EXTI_D3PCR1L_PCS0_Pos       (0U)

+#define EXTI_D3PCR1L_PCS0_Msk       (0x3UL << EXTI_D3PCR1L_PCS0_Pos)           /*!< 0x00000003 */

+#define EXTI_D3PCR1L_PCS0           EXTI_D3PCR1L_PCS0_Msk                      /*!< D3 Pending request clear input signal selection on line 0 */

+#define EXTI_D3PCR1L_PCS1_Pos       (2U)

+#define EXTI_D3PCR1L_PCS1_Msk       (0x3UL << EXTI_D3PCR1L_PCS1_Pos)           /*!< 0x000000C0 */

+#define EXTI_D3PCR1L_PCS1           EXTI_D3PCR1L_PCS1_Msk                      /*!< D3 Pending request clear input signal selection on line 1 */

+#define EXTI_D3PCR1L_PCS2_Pos       (4U)

+#define EXTI_D3PCR1L_PCS2_Msk       (0x3UL << EXTI_D3PCR1L_PCS2_Pos)           /*!< 0x00000030 */

+#define EXTI_D3PCR1L_PCS2           EXTI_D3PCR1L_PCS2_Msk                      /*!< D3 Pending request clear input signal selection on line 2 */

+#define EXTI_D3PCR1L_PCS3_Pos       (6U)

+#define EXTI_D3PCR1L_PCS3_Msk       (0x3UL << EXTI_D3PCR1L_PCS3_Pos)           /*!< 0x000000C0 */

+#define EXTI_D3PCR1L_PCS3           EXTI_D3PCR1L_PCS3_Msk                      /*!< D3 Pending request clear input signal selection on line 3 */

+#define EXTI_D3PCR1L_PCS4_Pos       (8U)

+#define EXTI_D3PCR1L_PCS4_Msk       (0x3UL << EXTI_D3PCR1L_PCS4_Pos)           /*!< 0x00000300 */

+#define EXTI_D3PCR1L_PCS4           EXTI_D3PCR1L_PCS4_Msk                      /*!< D3 Pending request clear input signal selection on line 4 */

+#define EXTI_D3PCR1L_PCS5_Pos       (10U)

+#define EXTI_D3PCR1L_PCS5_Msk       (0x3UL << EXTI_D3PCR1L_PCS5_Pos)           /*!< 0x00000C00 */

+#define EXTI_D3PCR1L_PCS5           EXTI_D3PCR1L_PCS5_Msk                      /*!< D3 Pending request clear input signal selection on line 5 */

+#define EXTI_D3PCR1L_PCS6_Pos       (12U)

+#define EXTI_D3PCR1L_PCS6_Msk       (0x3UL << EXTI_D3PCR1L_PCS6_Pos)           /*!< 0x00003000 */

+#define EXTI_D3PCR1L_PCS6           EXTI_D3PCR1L_PCS6_Msk                      /*!< D3 Pending request clear input signal selection on line 6 */

+#define EXTI_D3PCR1L_PCS7_Pos       (14U)

+#define EXTI_D3PCR1L_PCS7_Msk       (0x3UL << EXTI_D3PCR1L_PCS7_Pos)           /*!< 0x0000C000 */

+#define EXTI_D3PCR1L_PCS7           EXTI_D3PCR1L_PCS7_Msk                      /*!< D3 Pending request clear input signal selection on line 7 */

+#define EXTI_D3PCR1L_PCS8_Pos       (16U)

+#define EXTI_D3PCR1L_PCS8_Msk       (0x3UL << EXTI_D3PCR1L_PCS8_Pos)           /*!< 0x00030000 */

+#define EXTI_D3PCR1L_PCS8           EXTI_D3PCR1L_PCS8_Msk                      /*!< D3 Pending request clear input signal selection on line 8 */

+#define EXTI_D3PCR1L_PCS9_Pos       (18U)

+#define EXTI_D3PCR1L_PCS9_Msk       (0x3UL << EXTI_D3PCR1L_PCS9_Pos)           /*!< 0x000C0000 */

+#define EXTI_D3PCR1L_PCS9           EXTI_D3PCR1L_PCS9_Msk                      /*!< D3 Pending request clear input signal selection on line 9 */

+#define EXTI_D3PCR1L_PCS10_Pos      (20U)

+#define EXTI_D3PCR1L_PCS10_Msk      (0x3UL << EXTI_D3PCR1L_PCS10_Pos)          /*!< 0x00300000 */

+#define EXTI_D3PCR1L_PCS10          EXTI_D3PCR1L_PCS10_Msk                     /*!< D3 Pending request clear input signal selection on line 10*/

+#define EXTI_D3PCR1L_PCS11_Pos      (22U)

+#define EXTI_D3PCR1L_PCS11_Msk      (0x3UL << EXTI_D3PCR1L_PCS11_Pos)          /*!< 0x00C00000 */

+#define EXTI_D3PCR1L_PCS11          EXTI_D3PCR1L_PCS11_Msk                     /*!< D3 Pending request clear input signal selection on line 11*/

+#define EXTI_D3PCR1L_PCS12_Pos      (24U)

+#define EXTI_D3PCR1L_PCS12_Msk      (0x3UL << EXTI_D3PCR1L_PCS12_Pos)          /*!< 0x03000000 */

+#define EXTI_D3PCR1L_PCS12          EXTI_D3PCR1L_PCS12_Msk                     /*!< D3 Pending request clear input signal selection on line 12*/

+#define EXTI_D3PCR1L_PCS13_Pos      (26U)

+#define EXTI_D3PCR1L_PCS13_Msk      (0x3UL << EXTI_D3PCR1L_PCS13_Pos)          /*!< 0x0C000000 */

+#define EXTI_D3PCR1L_PCS13          EXTI_D3PCR1L_PCS13_Msk                     /*!< D3 Pending request clear input signal selection on line 13*/

+#define EXTI_D3PCR1L_PCS14_Pos      (28U)

+#define EXTI_D3PCR1L_PCS14_Msk      (0x3UL << EXTI_D3PCR1L_PCS14_Pos)          /*!< 0x30000000 */

+#define EXTI_D3PCR1L_PCS14          EXTI_D3PCR1L_PCS14_Msk                     /*!< D3 Pending request clear input signal selection on line 14*/

+#define EXTI_D3PCR1L_PCS15_Pos      (30U)

+#define EXTI_D3PCR1L_PCS15_Msk      (0x3UL << EXTI_D3PCR1L_PCS15_Pos)          /*!< 0xC0000000 */

+#define EXTI_D3PCR1L_PCS15          EXTI_D3PCR1L_PCS15_Msk                     /*!< D3 Pending request clear input signal selection on line 15*/

+

+/*******************  Bit definition for EXTI_D3PCR1H register  ****************/

+#define EXTI_D3PCR1H_PCS19_Pos       (6U)

+#define EXTI_D3PCR1H_PCS19_Msk       (0x3UL << EXTI_D3PCR1H_PCS19_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR1H_PCS19           EXTI_D3PCR1H_PCS19_Msk                    /*!< D3 Pending request clear input signal selection on line 19 */

+#define EXTI_D3PCR1H_PCS20_Pos       (8U)

+#define EXTI_D3PCR1H_PCS20_Msk       (0x3UL << EXTI_D3PCR1H_PCS20_Pos)         /*!< 0x00000300 */

+#define EXTI_D3PCR1H_PCS20           EXTI_D3PCR1H_PCS20_Msk                    /*!< D3 Pending request clear input signal selection on line 20 */

+#define EXTI_D3PCR1H_PCS21_Pos       (10U)

+#define EXTI_D3PCR1H_PCS21_Msk       (0x3UL << EXTI_D3PCR1H_PCS21_Pos)         /*!< 0x00000C00 */

+#define EXTI_D3PCR1H_PCS21           EXTI_D3PCR1H_PCS21_Msk                    /*!< D3 Pending request clear input signal selection on line 21 */

+#define EXTI_D3PCR1H_PCS25_Pos       (18U)

+#define EXTI_D3PCR1H_PCS25_Msk       (0x3UL << EXTI_D3PCR1H_PCS25_Pos)         /*!< 0x000C0000 */

+#define EXTI_D3PCR1H_PCS25           EXTI_D3PCR1H_PCS25_Msk                    /*!< D3 Pending request clear input signal selection on line 25 */

+

+/******************  Bit definition for EXTI_RTSR2 register  *******************/

+#define EXTI_RTSR2_TR_Pos          (17U)

+#define EXTI_RTSR2_TR_Msk          (0x5UL << EXTI_RTSR2_TR_Pos)                /*!< 0x000A0000 */

+#define EXTI_RTSR2_TR              EXTI_RTSR2_TR_Msk                           /*!< Rising trigger event configuration bit */

+#define EXTI_RTSR2_TR49_Pos        (17U)

+#define EXTI_RTSR2_TR49_Msk        (0x1UL << EXTI_RTSR2_TR49_Pos)              /*!< 0x00020000 */

+#define EXTI_RTSR2_TR49            EXTI_RTSR2_TR49_Msk                         /*!< Rising trigger event configuration bit of line 49 */

+#define EXTI_RTSR2_TR51_Pos        (19U)

+#define EXTI_RTSR2_TR51_Msk        (0x1UL << EXTI_RTSR2_TR51_Pos)              /*!< 0x00080000 */

+#define EXTI_RTSR2_TR51            EXTI_RTSR2_TR51_Msk                         /*!< Rising trigger event configuration bit of line 51 */

+

+/******************  Bit definition for EXTI_FTSR2 register  *******************/

+#define EXTI_FTSR2_TR_Pos          (17U)

+#define EXTI_FTSR2_TR_Msk          (0x5UL << EXTI_FTSR2_TR_Pos)                /*!< 0x000A0000 */

+#define EXTI_FTSR2_TR              EXTI_FTSR2_TR_Msk                           /*!< Falling trigger event configuration bit */

+#define EXTI_FTSR2_TR49_Pos        (17U)

+#define EXTI_FTSR2_TR49_Msk        (0x1UL << EXTI_FTSR2_TR49_Pos)              /*!< 0x00020000 */

+#define EXTI_FTSR2_TR49            EXTI_FTSR2_TR49_Msk                         /*!< Falling trigger event configuration bit of line 49 */

+#define EXTI_FTSR2_TR51_Pos        (19U)

+#define EXTI_FTSR2_TR51_Msk        (0x1UL << EXTI_FTSR2_TR51_Pos)              /*!< 0x00080000 */

+#define EXTI_FTSR2_TR51            EXTI_FTSR2_TR51_Msk                         /*!< Falling trigger event configuration bit of line 51 */

+

+/******************  Bit definition for EXTI_SWIER2 register  ******************/

+#define EXTI_SWIER2_SWIER49_Pos    (17U)

+#define EXTI_SWIER2_SWIER49_Msk    (0x1UL << EXTI_SWIER2_SWIER49_Pos)          /*!< 0x00020000 */

+#define EXTI_SWIER2_SWIER49        EXTI_SWIER2_SWIER49_Msk                     /*!< Software Interrupt on line 49 */

+#define EXTI_SWIER2_SWIER51_Pos    (19U)

+#define EXTI_SWIER2_SWIER51_Msk    (0x1UL << EXTI_SWIER2_SWIER51_Pos)          /*!< 0x00080000 */

+#define EXTI_SWIER2_SWIER51        EXTI_SWIER2_SWIER51_Msk                     /*!< Software Interrupt on line 51 */

+

+/******************  Bit definition for EXTI_D3PMR2 register  ******************/

+#define EXTI_D3PMR2_MR34_Pos       (2U)

+#define EXTI_D3PMR2_MR34_Msk       (0x1UL << EXTI_D3PMR2_MR34_Pos)             /*!< 0x00000004 */

+#define EXTI_D3PMR2_MR34           EXTI_D3PMR2_MR34_Msk                        /*!< Pending Mask Event for line 34  */

+#define EXTI_D3PMR2_MR35_Pos       (3U)

+#define EXTI_D3PMR2_MR35_Msk       (0x1UL << EXTI_D3PMR2_MR35_Pos)             /*!< 0x00000008 */

+#define EXTI_D3PMR2_MR35           EXTI_D3PMR2_MR35_Msk                        /*!< Pending Mask Event for line 35  */

+#define EXTI_D3PMR2_MR41_Pos       (9U)

+#define EXTI_D3PMR2_MR41_Msk       (0x1UL << EXTI_D3PMR2_MR41_Pos)             /*!< 0x00000200 */

+#define EXTI_D3PMR2_MR41           EXTI_D3PMR2_MR41_Msk                        /*!< Pending Mask Event for line 41  */

+#define EXTI_D3PMR2_MR48_Pos       (16U)

+#define EXTI_D3PMR2_MR48_Msk       (0x1UL << EXTI_D3PMR2_MR48_Pos)             /*!< 0x00010000 */

+#define EXTI_D3PMR2_MR48           EXTI_D3PMR2_MR48_Msk                        /*!< Pending Mask Event for line 48  */

+#define EXTI_D3PMR2_MR49_Pos       (17U)

+#define EXTI_D3PMR2_MR49_Msk       (0x1UL << EXTI_D3PMR2_MR49_Pos)             /*!< 0x00020000 */

+#define EXTI_D3PMR2_MR49           EXTI_D3PMR2_MR49_Msk                        /*!< Pending Mask Event for line 49  */

+#define EXTI_D3PMR2_MR50_Pos       (18U)

+#define EXTI_D3PMR2_MR50_Msk       (0x1UL << EXTI_D3PMR2_MR50_Pos)             /*!< 0x00040000 */

+#define EXTI_D3PMR2_MR50           EXTI_D3PMR2_MR50_Msk                        /*!< Pending Mask Event for line 50  */

+#define EXTI_D3PMR2_MR51_Pos       (19U)

+#define EXTI_D3PMR2_MR51_Msk       (0x1UL << EXTI_D3PMR2_MR51_Pos)             /*!< 0x00080000 */

+#define EXTI_D3PMR2_MR51           EXTI_D3PMR2_MR51_Msk                        /*!< Pending Mask Event for line 51  */

+/*******************  Bit definition for EXTI_D3PCR2L register  ****************/

+#define EXTI_D3PCR2L_PCS34_Pos       (4U)

+#define EXTI_D3PCR2L_PCS34_Msk       (0x3UL << EXTI_D3PCR2L_PCS34_Pos)         /*!< 0x00000030 */

+#define EXTI_D3PCR2L_PCS34           EXTI_D3PCR2L_PCS34_Msk                    /*!< D3 Pending request clear input signal selection on line 34 */

+#define EXTI_D3PCR2L_PCS35_Pos       (6U)

+#define EXTI_D3PCR2L_PCS35_Msk       (0x3UL << EXTI_D3PCR2L_PCS35_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR2L_PCS35           EXTI_D3PCR2L_PCS35_Msk                    /*!< D3 Pending request clear input signal selection on line 35 */

+#define EXTI_D3PCR2L_PCS41_Pos       (18U)

+#define EXTI_D3PCR2L_PCS41_Msk       (0x3UL << EXTI_D3PCR2L_PCS41_Pos)         /*!< 0x000C0000 */

+#define EXTI_D3PCR2L_PCS41           EXTI_D3PCR2L_PCS41_Msk                    /*!< D3 Pending request clear input signal selection on line 41 */

+

+

+/*******************  Bit definition for EXTI_D3PCR2H register  ****************/

+#define EXTI_D3PCR2H_PCS48_Pos       (0U)

+#define EXTI_D3PCR2H_PCS48_Msk       (0x3UL << EXTI_D3PCR2H_PCS48_Pos)         /*!< 0x00000003 */

+#define EXTI_D3PCR2H_PCS48           EXTI_D3PCR2H_PCS48_Msk                    /*!< D3 Pending request clear input signal selection on line 48 */

+#define EXTI_D3PCR2H_PCS49_Pos       (2U)

+#define EXTI_D3PCR2H_PCS49_Msk       (0x3UL << EXTI_D3PCR2H_PCS49_Pos)         /*!< 0x0000000C */

+#define EXTI_D3PCR2H_PCS49           EXTI_D3PCR2H_PCS49_Msk                    /*!< D3 Pending request clear input signal selection on line 49 */

+#define EXTI_D3PCR2H_PCS50_Pos       (4U)

+#define EXTI_D3PCR2H_PCS50_Msk       (0x3UL << EXTI_D3PCR2H_PCS50_Pos)         /*!< 0x00000030 */

+#define EXTI_D3PCR2H_PCS50           EXTI_D3PCR2H_PCS50_Msk                    /*!< D3 Pending request clear input signal selection on line 50 */

+#define EXTI_D3PCR2H_PCS51_Pos       (6U)

+#define EXTI_D3PCR2H_PCS51_Msk       (0x3UL << EXTI_D3PCR2H_PCS51_Pos)         /*!< 0x000000C0 */

+#define EXTI_D3PCR2H_PCS51           EXTI_D3PCR2H_PCS51_Msk                    /*!< D3 Pending request clear input signal selection on line 51 */

+/******************  Bit definition for EXTI_RTSR3 register  *******************/

+#define EXTI_RTSR3_TR_Pos          (18U)

+#define EXTI_RTSR3_TR_Msk          (0x9UL << EXTI_RTSR3_TR_Pos)                /*!< 0x00240000 */

+#define EXTI_RTSR3_TR              EXTI_RTSR3_TR_Msk                           /*!< Rising trigger event configuration bit            */

+#define EXTI_RTSR3_TR82_Pos        (18U)

+#define EXTI_RTSR3_TR82_Msk        (0x1UL << EXTI_RTSR3_TR82_Pos)              /*!< 0x00040000 */

+#define EXTI_RTSR3_TR82            EXTI_RTSR3_TR82_Msk                         /*!< Rising trigger event configuration bit of line 82 */

+#define EXTI_RTSR3_TR85_Pos        (21U)

+#define EXTI_RTSR3_TR85_Msk        (0x1UL << EXTI_RTSR3_TR85_Pos)              /*!< 0x00200000 */

+#define EXTI_RTSR3_TR85            EXTI_RTSR3_TR85_Msk                         /*!< Rising trigger event configuration bit of line 85 */

+

+/******************  Bit definition for EXTI_FTSR3 register  *******************/

+#define EXTI_FTSR3_TR_Pos          (18U)

+#define EXTI_FTSR3_TR_Msk          (0x9UL << EXTI_FTSR3_TR_Pos)                /*!< 0x00240000 */

+#define EXTI_FTSR3_TR              EXTI_FTSR3_TR_Msk                           /*!< Falling trigger event configuration bit            */

+#define EXTI_FTSR3_TR82_Pos        (18U)

+#define EXTI_FTSR3_TR82_Msk        (0x1UL << EXTI_FTSR3_TR82_Pos)              /*!< 0x00040000 */

+#define EXTI_FTSR3_TR82            EXTI_FTSR3_TR82_Msk                         /*!< Falling trigger event configuration bit of line 82 */

+#define EXTI_FTSR3_TR85_Pos        (21U)

+#define EXTI_FTSR3_TR85_Msk        (0x1UL << EXTI_FTSR3_TR85_Pos)              /*!< 0x00200000 */

+#define EXTI_FTSR3_TR85            EXTI_FTSR3_TR85_Msk                         /*!< Falling trigger event configuration bit of line 85 */

+

+/******************  Bit definition for EXTI_SWIER3 register  ******************/

+#define EXTI_SWIER3_SWI_Pos        (18U)

+#define EXTI_SWIER3_SWI_Msk        (0x9UL << EXTI_SWIER3_SWI_Pos)              /*!< 0x00240000 */

+#define EXTI_SWIER3_SWI            EXTI_SWIER3_SWI_Msk                         /*!< Software Interrupt event bit */

+#define EXTI_SWIER3_SWIER82_Pos    (18U)

+#define EXTI_SWIER3_SWIER82_Msk    (0x1UL << EXTI_SWIER3_SWIER82_Pos)          /*!< 0x00040000 */

+#define EXTI_SWIER3_SWIER82        EXTI_SWIER3_SWIER82_Msk                     /*!< Software Interrupt on line 82 */

+#define EXTI_SWIER3_SWIER85_Pos    (21U)

+#define EXTI_SWIER3_SWIER85_Msk    (0x1UL << EXTI_SWIER3_SWIER85_Pos)          /*!< 0x00200000 */

+#define EXTI_SWIER3_SWIER85        EXTI_SWIER3_SWIER85_Msk                     /*!< Software Interrupt on line 85 */

+

+/******************  Bit definition for EXTI_D3PMR3 register  ******************/

+#define EXTI_D3PMR3_MR88_Pos       (24U)

+#define EXTI_D3PMR3_MR88_Msk       (0x1UL << EXTI_D3PMR3_MR88_Pos)             /*!< 0x01000000 */

+#define EXTI_D3PMR3_MR88           EXTI_D3PMR3_MR88_Msk                        /*!< Pending Mask Event for line 88  */

+

+/*******************  Bit definition for EXTI_D3PCR3H register  ****************/

+#define EXTI_D3PCR3H_PCS88_Pos       (16U)

+#define EXTI_D3PCR3H_PCS88_Msk       (0x3UL << EXTI_D3PCR3H_PCS88_Pos)         /*!< 0x00030000 */

+#define EXTI_D3PCR3H_PCS88           EXTI_D3PCR3H_PCS88_Msk                    /*!< D3 Pending request clear input signal selection on line 88 */

+

+/*******************  Bit definition for EXTI_IMR1 register  *******************/

+#define EXTI_IMR1_IM_Pos           (0U)

+#define EXTI_IMR1_IM_Msk           (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos)          /*!< 0xFFFFFFFF */

+#define EXTI_IMR1_IM               EXTI_IMR1_IM_Msk                            /*!< Interrupt Mask */

+#define EXTI_IMR1_IM0_Pos          (0U)

+#define EXTI_IMR1_IM0_Msk          (0x1UL << EXTI_IMR1_IM0_Pos)                /*!< 0x00000001 */

+#define EXTI_IMR1_IM0              EXTI_IMR1_IM0_Msk                           /*!< Interrupt Mask on line 0 */

+#define EXTI_IMR1_IM1_Pos          (1U)

+#define EXTI_IMR1_IM1_Msk          (0x1UL << EXTI_IMR1_IM1_Pos)                /*!< 0x00000002 */

+#define EXTI_IMR1_IM1              EXTI_IMR1_IM1_Msk                           /*!< Interrupt Mask on line 1 */

+#define EXTI_IMR1_IM2_Pos          (2U)

+#define EXTI_IMR1_IM2_Msk          (0x1UL << EXTI_IMR1_IM2_Pos)                /*!< 0x00000004 */

+#define EXTI_IMR1_IM2              EXTI_IMR1_IM2_Msk                           /*!< Interrupt Mask on line 2 */

+#define EXTI_IMR1_IM3_Pos          (3U)

+#define EXTI_IMR1_IM3_Msk          (0x1UL << EXTI_IMR1_IM3_Pos)                /*!< 0x00000008 */

+#define EXTI_IMR1_IM3              EXTI_IMR1_IM3_Msk                           /*!< Interrupt Mask on line 3 */

+#define EXTI_IMR1_IM4_Pos          (4U)

+#define EXTI_IMR1_IM4_Msk          (0x1UL << EXTI_IMR1_IM4_Pos)                /*!< 0x00000010 */

+#define EXTI_IMR1_IM4              EXTI_IMR1_IM4_Msk                           /*!< Interrupt Mask on line 4 */

+#define EXTI_IMR1_IM5_Pos          (5U)

+#define EXTI_IMR1_IM5_Msk          (0x1UL << EXTI_IMR1_IM5_Pos)                /*!< 0x00000020 */

+#define EXTI_IMR1_IM5              EXTI_IMR1_IM5_Msk                           /*!< Interrupt Mask on line 5 */

+#define EXTI_IMR1_IM6_Pos          (6U)

+#define EXTI_IMR1_IM6_Msk          (0x1UL << EXTI_IMR1_IM6_Pos)                /*!< 0x00000040 */

+#define EXTI_IMR1_IM6              EXTI_IMR1_IM6_Msk                           /*!< Interrupt Mask on line 6 */

+#define EXTI_IMR1_IM7_Pos          (7U)

+#define EXTI_IMR1_IM7_Msk          (0x1UL << EXTI_IMR1_IM7_Pos)                /*!< 0x00000080 */

+#define EXTI_IMR1_IM7              EXTI_IMR1_IM7_Msk                           /*!< Interrupt Mask on line 7 */

+#define EXTI_IMR1_IM8_Pos          (8U)

+#define EXTI_IMR1_IM8_Msk          (0x1UL << EXTI_IMR1_IM8_Pos)                /*!< 0x00000100 */

+#define EXTI_IMR1_IM8              EXTI_IMR1_IM8_Msk                           /*!< Interrupt Mask on line 8 */

+#define EXTI_IMR1_IM9_Pos          (9U)

+#define EXTI_IMR1_IM9_Msk          (0x1UL << EXTI_IMR1_IM9_Pos)                /*!< 0x00000200 */

+#define EXTI_IMR1_IM9              EXTI_IMR1_IM9_Msk                           /*!< Interrupt Mask on line 9 */

+#define EXTI_IMR1_IM10_Pos         (10U)

+#define EXTI_IMR1_IM10_Msk         (0x1UL << EXTI_IMR1_IM10_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR1_IM10             EXTI_IMR1_IM10_Msk                          /*!< Interrupt Mask on line 10 */

+#define EXTI_IMR1_IM11_Pos         (11U)

+#define EXTI_IMR1_IM11_Msk         (0x1UL << EXTI_IMR1_IM11_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR1_IM11             EXTI_IMR1_IM11_Msk                          /*!< Interrupt Mask on line 11 */

+#define EXTI_IMR1_IM12_Pos         (12U)

+#define EXTI_IMR1_IM12_Msk         (0x1UL << EXTI_IMR1_IM12_Pos)               /*!< 0x00001000 */

+#define EXTI_IMR1_IM12             EXTI_IMR1_IM12_Msk                          /*!< Interrupt Mask on line 12 */

+#define EXTI_IMR1_IM13_Pos         (13U)

+#define EXTI_IMR1_IM13_Msk         (0x1UL << EXTI_IMR1_IM13_Pos)               /*!< 0x00002000 */

+#define EXTI_IMR1_IM13             EXTI_IMR1_IM13_Msk                          /*!< Interrupt Mask on line 13 */

+#define EXTI_IMR1_IM14_Pos         (14U)

+#define EXTI_IMR1_IM14_Msk         (0x1UL << EXTI_IMR1_IM14_Pos)               /*!< 0x00004000 */

+#define EXTI_IMR1_IM14             EXTI_IMR1_IM14_Msk                          /*!< Interrupt Mask on line 14 */

+#define EXTI_IMR1_IM15_Pos         (15U)

+#define EXTI_IMR1_IM15_Msk         (0x1UL << EXTI_IMR1_IM15_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR1_IM15             EXTI_IMR1_IM15_Msk                          /*!< Interrupt Mask on line 15 */

+#define EXTI_IMR1_IM16_Pos         (16U)

+#define EXTI_IMR1_IM16_Msk         (0x1UL << EXTI_IMR1_IM16_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR1_IM16             EXTI_IMR1_IM16_Msk                          /*!< Interrupt Mask on line 16 */

+#define EXTI_IMR1_IM17_Pos         (17U)

+#define EXTI_IMR1_IM17_Msk         (0x1UL << EXTI_IMR1_IM17_Pos)               /*!< 0x00020000 */

+#define EXTI_IMR1_IM17             EXTI_IMR1_IM17_Msk                          /*!< Interrupt Mask on line 17 */

+#define EXTI_IMR1_IM18_Pos         (18U)

+#define EXTI_IMR1_IM18_Msk         (0x1UL << EXTI_IMR1_IM18_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR1_IM18             EXTI_IMR1_IM18_Msk                          /*!< Interrupt Mask on line 18 */

+#define EXTI_IMR1_IM19_Pos         (19U)

+#define EXTI_IMR1_IM19_Msk         (0x1UL << EXTI_IMR1_IM19_Pos)               /*!< 0x00080000 */

+#define EXTI_IMR1_IM19             EXTI_IMR1_IM19_Msk                          /*!< Interrupt Mask on line 19 */

+#define EXTI_IMR1_IM20_Pos         (20U)

+#define EXTI_IMR1_IM20_Msk         (0x1UL << EXTI_IMR1_IM20_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR1_IM20             EXTI_IMR1_IM20_Msk                          /*!< Interrupt Mask on line 20 */

+#define EXTI_IMR1_IM21_Pos         (21U)

+#define EXTI_IMR1_IM21_Msk         (0x1UL << EXTI_IMR1_IM21_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR1_IM21             EXTI_IMR1_IM21_Msk                          /*!< Interrupt Mask on line 21 */

+#define EXTI_IMR1_IM22_Pos         (22U)

+#define EXTI_IMR1_IM22_Msk         (0x1UL << EXTI_IMR1_IM22_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR1_IM22             EXTI_IMR1_IM22_Msk                          /*!< Interrupt Mask on line 22 */

+#define EXTI_IMR1_IM23_Pos         (23U)

+#define EXTI_IMR1_IM23_Msk         (0x1UL << EXTI_IMR1_IM23_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR1_IM23             EXTI_IMR1_IM23_Msk                          /*!< Interrupt Mask on line 23 */

+#define EXTI_IMR1_IM24_Pos         (24U)

+#define EXTI_IMR1_IM24_Msk         (0x1UL << EXTI_IMR1_IM24_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR1_IM24             EXTI_IMR1_IM24_Msk                          /*!< Interrupt Mask on line 24 */

+#define EXTI_IMR1_IM25_Pos         (25U)

+#define EXTI_IMR1_IM25_Msk         (0x1UL << EXTI_IMR1_IM25_Pos)               /*!< 0x02000000 */

+#define EXTI_IMR1_IM25             EXTI_IMR1_IM25_Msk                          /*!< Interrupt Mask on line 25 */

+#define EXTI_IMR1_IM26_Pos         (26U)

+#define EXTI_IMR1_IM26_Msk         (0x1UL << EXTI_IMR1_IM26_Pos)               /*!< 0x04000000 */

+#define EXTI_IMR1_IM26             EXTI_IMR1_IM26_Msk                          /*!< Interrupt Mask on line 26 */

+#define EXTI_IMR1_IM27_Pos         (27U)

+#define EXTI_IMR1_IM27_Msk         (0x1UL << EXTI_IMR1_IM27_Pos)               /*!< 0x08000000 */

+#define EXTI_IMR1_IM27             EXTI_IMR1_IM27_Msk                          /*!< Interrupt Mask on line 27 */

+#define EXTI_IMR1_IM28_Pos         (28U)

+#define EXTI_IMR1_IM28_Msk         (0x1UL << EXTI_IMR1_IM28_Pos)               /*!< 0x10000000 */

+#define EXTI_IMR1_IM28             EXTI_IMR1_IM28_Msk                          /*!< Interrupt Mask on line 28 */

+#define EXTI_IMR1_IM29_Pos         (29U)

+#define EXTI_IMR1_IM29_Msk         (0x1UL << EXTI_IMR1_IM29_Pos)               /*!< 0x20000000 */

+#define EXTI_IMR1_IM29             EXTI_IMR1_IM29_Msk                          /*!< Interrupt Mask on line 29 */

+#define EXTI_IMR1_IM30_Pos         (30U)

+#define EXTI_IMR1_IM30_Msk         (0x1UL << EXTI_IMR1_IM30_Pos)               /*!< 0x40000000 */

+#define EXTI_IMR1_IM30             EXTI_IMR1_IM30_Msk                          /*!< Interrupt Mask on line 30 */

+#define EXTI_IMR1_IM31_Pos         (31U)

+#define EXTI_IMR1_IM31_Msk         (0x1UL << EXTI_IMR1_IM31_Pos)               /*!< 0x80000000 */

+#define EXTI_IMR1_IM31             EXTI_IMR1_IM31_Msk                          /*!< Interrupt Mask on line 31 */

+

+/*******************  Bit definition for EXTI_EMR1 register  *******************/

+#define EXTI_EMR1_EM_Pos           (0U)

+#define EXTI_EMR1_EM_Msk           (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos)          /*!< 0xFFFFFFFF */

+#define EXTI_EMR1_EM               EXTI_EMR1_EM_Msk                            /*!< Event Mask */

+#define EXTI_EMR1_EM0_Pos          (0U)

+#define EXTI_EMR1_EM0_Msk          (0x1UL << EXTI_EMR1_EM0_Pos)                /*!< 0x00000001 */

+#define EXTI_EMR1_EM0              EXTI_EMR1_EM0_Msk                           /*!< Event Mask on line 0 */

+#define EXTI_EMR1_EM1_Pos          (1U)

+#define EXTI_EMR1_EM1_Msk          (0x1UL << EXTI_EMR1_EM1_Pos)                /*!< 0x00000002 */

+#define EXTI_EMR1_EM1              EXTI_EMR1_EM1_Msk                           /*!< Event Mask on line 1 */

+#define EXTI_EMR1_EM2_Pos          (2U)

+#define EXTI_EMR1_EM2_Msk          (0x1UL << EXTI_EMR1_EM2_Pos)                /*!< 0x00000004 */

+#define EXTI_EMR1_EM2              EXTI_EMR1_EM2_Msk                           /*!< Event Mask on line 2 */

+#define EXTI_EMR1_EM3_Pos          (3U)

+#define EXTI_EMR1_EM3_Msk          (0x1UL << EXTI_EMR1_EM3_Pos)                /*!< 0x00000008 */

+#define EXTI_EMR1_EM3              EXTI_EMR1_EM3_Msk                           /*!< Event Mask on line 3 */

+#define EXTI_EMR1_EM4_Pos          (4U)

+#define EXTI_EMR1_EM4_Msk          (0x1UL << EXTI_EMR1_EM4_Pos)                /*!< 0x00000010 */

+#define EXTI_EMR1_EM4              EXTI_EMR1_EM4_Msk                           /*!< Event Mask on line 4 */

+#define EXTI_EMR1_EM5_Pos          (5U)

+#define EXTI_EMR1_EM5_Msk          (0x1UL << EXTI_EMR1_EM5_Pos)                /*!< 0x00000020 */

+#define EXTI_EMR1_EM5              EXTI_EMR1_EM5_Msk                           /*!< Event Mask on line 5 */

+#define EXTI_EMR1_EM6_Pos          (6U)

+#define EXTI_EMR1_EM6_Msk          (0x1UL << EXTI_EMR1_EM6_Pos)                /*!< 0x00000040 */

+#define EXTI_EMR1_EM6              EXTI_EMR1_EM6_Msk                           /*!< Event Mask on line 6 */

+#define EXTI_EMR1_EM7_Pos          (7U)

+#define EXTI_EMR1_EM7_Msk          (0x1UL << EXTI_EMR1_EM7_Pos)                /*!< 0x00000080 */

+#define EXTI_EMR1_EM7              EXTI_EMR1_EM7_Msk                           /*!< Event Mask on line 7 */

+#define EXTI_EMR1_EM8_Pos          (8U)

+#define EXTI_EMR1_EM8_Msk          (0x1UL << EXTI_EMR1_EM8_Pos)                /*!< 0x00000100 */

+#define EXTI_EMR1_EM8              EXTI_EMR1_EM8_Msk                           /*!< Event Mask on line 8 */

+#define EXTI_EMR1_EM9_Pos          (9U)

+#define EXTI_EMR1_EM9_Msk          (0x1UL << EXTI_EMR1_EM9_Pos)                /*!< 0x00000200 */

+#define EXTI_EMR1_EM9              EXTI_EMR1_EM9_Msk                           /*!< Event Mask on line 9 */

+#define EXTI_EMR1_EM10_Pos         (10U)

+#define EXTI_EMR1_EM10_Msk         (0x1UL << EXTI_EMR1_EM10_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR1_EM10             EXTI_EMR1_EM10_Msk                          /*!< Event Mask on line 10 */

+#define EXTI_EMR1_EM11_Pos         (11U)

+#define EXTI_EMR1_EM11_Msk         (0x1UL << EXTI_EMR1_EM11_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR1_EM11             EXTI_EMR1_EM11_Msk                          /*!< Event Mask on line 11 */

+#define EXTI_EMR1_EM12_Pos         (12U)

+#define EXTI_EMR1_EM12_Msk         (0x1UL << EXTI_EMR1_EM12_Pos)               /*!< 0x00001000 */

+#define EXTI_EMR1_EM12             EXTI_EMR1_EM12_Msk                          /*!< Event Mask on line 12 */

+#define EXTI_EMR1_EM13_Pos         (13U)

+#define EXTI_EMR1_EM13_Msk         (0x1UL << EXTI_EMR1_EM13_Pos)               /*!< 0x00002000 */

+#define EXTI_EMR1_EM13             EXTI_EMR1_EM13_Msk                          /*!< Event Mask on line 13 */

+#define EXTI_EMR1_EM14_Pos         (14U)

+#define EXTI_EMR1_EM14_Msk         (0x1UL << EXTI_EMR1_EM14_Pos)               /*!< 0x00004000 */

+#define EXTI_EMR1_EM14             EXTI_EMR1_EM14_Msk                          /*!< Event Mask on line 14 */

+#define EXTI_EMR1_EM15_Pos         (15U)

+#define EXTI_EMR1_EM15_Msk         (0x1UL << EXTI_EMR1_EM15_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR1_EM15             EXTI_EMR1_EM15_Msk                          /*!< Event Mask on line 15 */

+#define EXTI_EMR1_EM16_Pos         (16U)

+#define EXTI_EMR1_EM16_Msk         (0x1UL << EXTI_EMR1_EM16_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR1_EM16             EXTI_EMR1_EM16_Msk                          /*!< Event Mask on line 16 */

+#define EXTI_EMR1_EM17_Pos         (17U)

+#define EXTI_EMR1_EM17_Msk         (0x1UL << EXTI_EMR1_EM17_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR1_EM17             EXTI_EMR1_EM17_Msk                          /*!< Event Mask on line 17 */

+#define EXTI_EMR1_EM18_Pos         (18U)

+#define EXTI_EMR1_EM18_Msk         (0x1UL << EXTI_EMR1_EM18_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR1_EM18             EXTI_EMR1_EM18_Msk                          /*!< Event Mask on line 18 */

+#define EXTI_EMR1_EM20_Pos         (20U)

+#define EXTI_EMR1_EM20_Msk         (0x1UL << EXTI_EMR1_EM20_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR1_EM20             EXTI_EMR1_EM20_Msk                          /*!< Event Mask on line 20 */

+#define EXTI_EMR1_EM21_Pos         (21U)

+#define EXTI_EMR1_EM21_Msk         (0x1UL << EXTI_EMR1_EM21_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR1_EM21             EXTI_EMR1_EM21_Msk                          /*!< Event Mask on line 21 */

+#define EXTI_EMR1_EM22_Pos         (22U)

+#define EXTI_EMR1_EM22_Msk         (0x1UL << EXTI_EMR1_EM22_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR1_EM22             EXTI_EMR1_EM22_Msk                          /*!< Event Mask on line 22 */

+#define EXTI_EMR1_EM23_Pos         (23U)

+#define EXTI_EMR1_EM23_Msk         (0x1UL << EXTI_EMR1_EM23_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR1_EM23             EXTI_EMR1_EM23_Msk                          /*!< Event Mask on line 23 */

+#define EXTI_EMR1_EM24_Pos         (24U)

+#define EXTI_EMR1_EM24_Msk         (0x1UL << EXTI_EMR1_EM24_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR1_EM24             EXTI_EMR1_EM24_Msk                          /*!< Event Mask on line 24 */

+#define EXTI_EMR1_EM25_Pos         (25U)

+#define EXTI_EMR1_EM25_Msk         (0x1UL << EXTI_EMR1_EM25_Pos)               /*!< 0x02000000 */

+#define EXTI_EMR1_EM25             EXTI_EMR1_EM25_Msk                          /*!< Event Mask on line 25 */

+#define EXTI_EMR1_EM26_Pos         (26U)

+#define EXTI_EMR1_EM26_Msk         (0x1UL << EXTI_EMR1_EM26_Pos)               /*!< 0x04000000 */

+#define EXTI_EMR1_EM26             EXTI_EMR1_EM26_Msk                          /*!< Event Mask on line 26 */

+#define EXTI_EMR1_EM27_Pos         (27U)

+#define EXTI_EMR1_EM27_Msk         (0x1UL << EXTI_EMR1_EM27_Pos)               /*!< 0x08000000 */

+#define EXTI_EMR1_EM27             EXTI_EMR1_EM27_Msk                          /*!< Event Mask on line 27 */

+#define EXTI_EMR1_EM28_Pos         (28U)

+#define EXTI_EMR1_EM28_Msk         (0x1UL << EXTI_EMR1_EM28_Pos)               /*!< 0x10000000 */

+#define EXTI_EMR1_EM28             EXTI_EMR1_EM28_Msk                          /*!< Event Mask on line 28 */

+#define EXTI_EMR1_EM29_Pos         (29U)

+#define EXTI_EMR1_EM29_Msk         (0x1UL << EXTI_EMR1_EM29_Pos)               /*!< 0x20000000 */

+#define EXTI_EMR1_EM29             EXTI_EMR1_EM29_Msk                          /*!< Event Mask on line 29 */

+#define EXTI_EMR1_EM30_Pos         (30U)

+#define EXTI_EMR1_EM30_Msk         (0x1UL << EXTI_EMR1_EM30_Pos)               /*!< 0x40000000 */

+#define EXTI_EMR1_EM30             EXTI_EMR1_EM30_Msk                          /*!< Event Mask on line 30 */

+#define EXTI_EMR1_EM31_Pos         (31U)

+#define EXTI_EMR1_EM31_Msk         (0x1UL << EXTI_EMR1_EM31_Pos)               /*!< 0x80000000 */

+#define EXTI_EMR1_EM31             EXTI_EMR1_EM31_Msk                          /*!< Event Mask on line 31 */

+

+/*******************  Bit definition for EXTI_PR1 register  ********************/

+#define EXTI_PR1_PR_Pos            (0U)

+#define EXTI_PR1_PR_Msk            (0x3FFFFFUL << EXTI_PR1_PR_Pos)             /*!< 0x003FFFFF */

+#define EXTI_PR1_PR                EXTI_PR1_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR1_PR0_Pos           (0U)

+#define EXTI_PR1_PR0_Msk           (0x1UL << EXTI_PR1_PR0_Pos)                 /*!< 0x00000001 */

+#define EXTI_PR1_PR0               EXTI_PR1_PR0_Msk                            /*!< Pending bit for line 0 */

+#define EXTI_PR1_PR1_Pos           (1U)

+#define EXTI_PR1_PR1_Msk           (0x1UL << EXTI_PR1_PR1_Pos)                 /*!< 0x00000002 */

+#define EXTI_PR1_PR1               EXTI_PR1_PR1_Msk                            /*!< Pending bit for line 1 */

+#define EXTI_PR1_PR2_Pos           (2U)

+#define EXTI_PR1_PR2_Msk           (0x1UL << EXTI_PR1_PR2_Pos)                 /*!< 0x00000004 */

+#define EXTI_PR1_PR2               EXTI_PR1_PR2_Msk                            /*!< Pending bit for line 2 */

+#define EXTI_PR1_PR3_Pos           (3U)

+#define EXTI_PR1_PR3_Msk           (0x1UL << EXTI_PR1_PR3_Pos)                 /*!< 0x00000008 */

+#define EXTI_PR1_PR3               EXTI_PR1_PR3_Msk                            /*!< Pending bit for line 3 */

+#define EXTI_PR1_PR4_Pos           (4U)

+#define EXTI_PR1_PR4_Msk           (0x1UL << EXTI_PR1_PR4_Pos)                 /*!< 0x00000010 */

+#define EXTI_PR1_PR4               EXTI_PR1_PR4_Msk                            /*!< Pending bit for line 4 */

+#define EXTI_PR1_PR5_Pos           (5U)

+#define EXTI_PR1_PR5_Msk           (0x1UL << EXTI_PR1_PR5_Pos)                 /*!< 0x00000020 */

+#define EXTI_PR1_PR5               EXTI_PR1_PR5_Msk                            /*!< Pending bit for line 5 */

+#define EXTI_PR1_PR6_Pos           (6U)

+#define EXTI_PR1_PR6_Msk           (0x1UL << EXTI_PR1_PR6_Pos)                 /*!< 0x00000040 */

+#define EXTI_PR1_PR6               EXTI_PR1_PR6_Msk                            /*!< Pending bit for line 6 */

+#define EXTI_PR1_PR7_Pos           (7U)

+#define EXTI_PR1_PR7_Msk           (0x1UL << EXTI_PR1_PR7_Pos)                 /*!< 0x00000080 */

+#define EXTI_PR1_PR7               EXTI_PR1_PR7_Msk                            /*!< Pending bit for line 7 */

+#define EXTI_PR1_PR8_Pos           (8U)

+#define EXTI_PR1_PR8_Msk           (0x1UL << EXTI_PR1_PR8_Pos)                 /*!< 0x00000100 */

+#define EXTI_PR1_PR8               EXTI_PR1_PR8_Msk                            /*!< Pending bit for line 8 */

+#define EXTI_PR1_PR9_Pos           (9U)

+#define EXTI_PR1_PR9_Msk           (0x1UL << EXTI_PR1_PR9_Pos)                 /*!< 0x00000200 */

+#define EXTI_PR1_PR9               EXTI_PR1_PR9_Msk                            /*!< Pending bit for line 9 */

+#define EXTI_PR1_PR10_Pos          (10U)

+#define EXTI_PR1_PR10_Msk          (0x1UL << EXTI_PR1_PR10_Pos)                /*!< 0x00000400 */

+#define EXTI_PR1_PR10              EXTI_PR1_PR10_Msk                           /*!< Pending bit for line 10 */

+#define EXTI_PR1_PR11_Pos          (11U)

+#define EXTI_PR1_PR11_Msk          (0x1UL << EXTI_PR1_PR11_Pos)                /*!< 0x00000800 */

+#define EXTI_PR1_PR11              EXTI_PR1_PR11_Msk                           /*!< Pending bit for line 11 */

+#define EXTI_PR1_PR12_Pos          (12U)

+#define EXTI_PR1_PR12_Msk          (0x1UL << EXTI_PR1_PR12_Pos)                /*!< 0x00001000 */

+#define EXTI_PR1_PR12              EXTI_PR1_PR12_Msk                           /*!< Pending bit for line 12 */

+#define EXTI_PR1_PR13_Pos          (13U)

+#define EXTI_PR1_PR13_Msk          (0x1UL << EXTI_PR1_PR13_Pos)                /*!< 0x00002000 */

+#define EXTI_PR1_PR13              EXTI_PR1_PR13_Msk                           /*!< Pending bit for line 13 */

+#define EXTI_PR1_PR14_Pos          (14U)

+#define EXTI_PR1_PR14_Msk          (0x1UL << EXTI_PR1_PR14_Pos)                /*!< 0x00004000 */

+#define EXTI_PR1_PR14              EXTI_PR1_PR14_Msk                           /*!< Pending bit for line 14 */

+#define EXTI_PR1_PR15_Pos          (15U)

+#define EXTI_PR1_PR15_Msk          (0x1UL << EXTI_PR1_PR15_Pos)                /*!< 0x00008000 */

+#define EXTI_PR1_PR15              EXTI_PR1_PR15_Msk                           /*!< Pending bit for line 15 */

+#define EXTI_PR1_PR16_Pos          (16U)

+#define EXTI_PR1_PR16_Msk          (0x1UL << EXTI_PR1_PR16_Pos)                /*!< 0x00010000 */

+#define EXTI_PR1_PR16              EXTI_PR1_PR16_Msk                           /*!< Pending bit for line 16 */

+#define EXTI_PR1_PR17_Pos          (17U)

+#define EXTI_PR1_PR17_Msk          (0x1UL << EXTI_PR1_PR17_Pos)                /*!< 0x00020000 */

+#define EXTI_PR1_PR17              EXTI_PR1_PR17_Msk                           /*!< Pending bit for line 17 */

+#define EXTI_PR1_PR18_Pos          (18U)

+#define EXTI_PR1_PR18_Msk          (0x1UL << EXTI_PR1_PR18_Pos)                /*!< 0x00040000 */

+#define EXTI_PR1_PR18              EXTI_PR1_PR18_Msk                           /*!< Pending bit for line 18 */

+#define EXTI_PR1_PR19_Pos          (19U)

+#define EXTI_PR1_PR19_Msk          (0x1UL << EXTI_PR1_PR19_Pos)                /*!< 0x00080000 */

+#define EXTI_PR1_PR19              EXTI_PR1_PR19_Msk                           /*!< Pending bit for line 19 */

+#define EXTI_PR1_PR20_Pos          (20U)

+#define EXTI_PR1_PR20_Msk          (0x1UL << EXTI_PR1_PR20_Pos)                /*!< 0x00100000 */

+#define EXTI_PR1_PR20              EXTI_PR1_PR20_Msk                           /*!< Pending bit for line 20 */

+#define EXTI_PR1_PR21_Pos          (21U)

+#define EXTI_PR1_PR21_Msk          (0x1UL << EXTI_PR1_PR21_Pos)                /*!< 0x00200000 */

+#define EXTI_PR1_PR21              EXTI_PR1_PR21_Msk                           /*!< Pending bit for line 21 */

+

+/*******************  Bit definition for EXTI_IMR2 register  *******************/

+#define EXTI_IMR2_IM_Pos           (0U)

+#define EXTI_IMR2_IM_Msk           (0xFFFF8FFFUL << EXTI_IMR2_IM_Pos)          /*!< 0xFFFF8FFF */

+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            /*!< Interrupt Mask            */

+#define EXTI_IMR2_IM32_Pos         (0U)

+#define EXTI_IMR2_IM32_Msk         (0x1UL << EXTI_IMR2_IM32_Pos)               /*!< 0x00000001 */

+#define EXTI_IMR2_IM32             EXTI_IMR2_IM32_Msk                          /*!< Interrupt Mask on line 32 */

+#define EXTI_IMR2_IM33_Pos         (1U)

+#define EXTI_IMR2_IM33_Msk         (0x1UL << EXTI_IMR2_IM33_Pos)               /*!< 0x00000002 */

+#define EXTI_IMR2_IM33             EXTI_IMR2_IM33_Msk                          /*!< Interrupt Mask on line 33 */

+#define EXTI_IMR2_IM34_Pos         (2U)

+#define EXTI_IMR2_IM34_Msk         (0x1UL << EXTI_IMR2_IM34_Pos)               /*!< 0x00000004 */

+#define EXTI_IMR2_IM34             EXTI_IMR2_IM34_Msk                          /*!< Interrupt Mask on line 34 */

+#define EXTI_IMR2_IM35_Pos         (3U)

+#define EXTI_IMR2_IM35_Msk         (0x1UL << EXTI_IMR2_IM35_Pos)               /*!< 0x00000008 */

+#define EXTI_IMR2_IM35             EXTI_IMR2_IM35_Msk                          /*!< Interrupt Mask on line 35 */

+#define EXTI_IMR2_IM36_Pos         (4U)

+#define EXTI_IMR2_IM36_Msk         (0x1UL << EXTI_IMR2_IM36_Pos)               /*!< 0x00000010 */

+#define EXTI_IMR2_IM36             EXTI_IMR2_IM36_Msk                          /*!< Interrupt Mask on line 36 */

+#define EXTI_IMR2_IM37_Pos         (5U)

+#define EXTI_IMR2_IM37_Msk         (0x1UL << EXTI_IMR2_IM37_Pos)               /*!< 0x00000020 */

+#define EXTI_IMR2_IM37             EXTI_IMR2_IM37_Msk                          /*!< Interrupt Mask on line 37 */

+#define EXTI_IMR2_IM38_Pos         (6U)

+#define EXTI_IMR2_IM38_Msk         (0x1UL << EXTI_IMR2_IM38_Pos)               /*!< 0x00000040 */

+#define EXTI_IMR2_IM38             EXTI_IMR2_IM38_Msk                          /*!< Interrupt Mask on line 38 */

+#define EXTI_IMR2_IM39_Pos         (7U)

+#define EXTI_IMR2_IM39_Msk         (0x1UL << EXTI_IMR2_IM39_Pos)               /*!< 0x00000080 */

+#define EXTI_IMR2_IM39             EXTI_IMR2_IM39_Msk                          /*!< Interrupt Mask on line 39 */

+#define EXTI_IMR2_IM40_Pos         (8U)

+#define EXTI_IMR2_IM40_Msk         (0x1UL << EXTI_IMR2_IM40_Pos)               /*!< 0x00000100 */

+#define EXTI_IMR2_IM40             EXTI_IMR2_IM40_Msk                          /*!< Interrupt Mask on line 40 */

+#define EXTI_IMR2_IM41_Pos         (9U)

+#define EXTI_IMR2_IM41_Msk         (0x1UL << EXTI_IMR2_IM41_Pos)               /*!< 0x00000200 */

+#define EXTI_IMR2_IM41             EXTI_IMR2_IM41_Msk                          /*!< Interrupt Mask on line 41 */

+#define EXTI_IMR2_IM42_Pos         (10U)

+#define EXTI_IMR2_IM42_Msk         (0x1UL << EXTI_IMR2_IM42_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR2_IM42             EXTI_IMR2_IM42_Msk                          /*!< Interrupt Mask on line 42 */

+#define EXTI_IMR2_IM43_Pos         (11U)

+#define EXTI_IMR2_IM43_Msk         (0x1UL << EXTI_IMR2_IM43_Pos)               /*!< 0x00000800 */

+#define EXTI_IMR2_IM43             EXTI_IMR2_IM43_Msk                          /*!< Interrupt Mask on line 43 */

+#define EXTI_IMR2_IM47_Pos         (15U)

+#define EXTI_IMR2_IM47_Msk         (0x1UL << EXTI_IMR2_IM47_Pos)               /*!< 0x00008000 */

+#define EXTI_IMR2_IM47             EXTI_IMR2_IM47_Msk                          /*!< Interrupt Mask on line 47 */

+#define EXTI_IMR2_IM48_Pos         (16U)

+#define EXTI_IMR2_IM48_Msk         (0x1UL << EXTI_IMR2_IM48_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR2_IM48             EXTI_IMR2_IM48_Msk                          /*!< Interrupt Mask on line 48 */

+#define EXTI_IMR2_IM49_Pos         (17U)

+#define EXTI_IMR2_IM49_Msk         (0x1UL << EXTI_IMR2_IM49_Pos)               /*!< 0x00020000 */

+#define EXTI_IMR2_IM49             EXTI_IMR2_IM49_Msk                          /*!< Interrupt Mask on line 49 */

+#define EXTI_IMR2_IM50_Pos         (18U)

+#define EXTI_IMR2_IM50_Msk         (0x1UL << EXTI_IMR2_IM50_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR2_IM50             EXTI_IMR2_IM50_Msk                          /*!< Interrupt Mask on line 50 */

+#define EXTI_IMR2_IM51_Pos         (19U)

+#define EXTI_IMR2_IM51_Msk         (0x1UL << EXTI_IMR2_IM51_Pos)               /*!< 0x00080000 */

+#define EXTI_IMR2_IM51             EXTI_IMR2_IM51_Msk                          /*!< Interrupt Mask on line 51 */

+#define EXTI_IMR2_IM52_Pos         (20U)

+#define EXTI_IMR2_IM52_Msk         (0x1UL << EXTI_IMR2_IM52_Pos)               /*!< 0x00100000 */

+#define EXTI_IMR2_IM52             EXTI_IMR2_IM52_Msk                          /*!< Interrupt Mask on line 52 */

+#define EXTI_IMR2_IM53_Pos         (21U)

+#define EXTI_IMR2_IM53_Msk         (0x1UL << EXTI_IMR2_IM53_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR2_IM53             EXTI_IMR2_IM53_Msk                          /*!< Interrupt Mask on line 53 */

+#define EXTI_IMR2_IM54_Pos         (22U)

+#define EXTI_IMR2_IM54_Msk         (0x1UL << EXTI_IMR2_IM54_Pos)               /*!< 0x00400000 */

+#define EXTI_IMR2_IM54             EXTI_IMR2_IM54_Msk                          /*!< Interrupt Mask on line 54 */

+#define EXTI_IMR2_IM55_Pos         (23U)

+#define EXTI_IMR2_IM55_Msk         (0x1UL << EXTI_IMR2_IM55_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR2_IM55             EXTI_IMR2_IM55_Msk                          /*!< Interrupt Mask on line 55 */

+#define EXTI_IMR2_IM56_Pos         (24U)

+#define EXTI_IMR2_IM56_Msk         (0x1UL << EXTI_IMR2_IM56_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR2_IM56             EXTI_IMR2_IM56_Msk                          /*!< Interrupt Mask on line 56 */

+#define EXTI_IMR2_IM57_Pos         (25U)

+#define EXTI_IMR2_IM57_Msk         (0x1UL << EXTI_IMR2_IM57_Pos)               /*!< 0x02000000 */

+#define EXTI_IMR2_IM57             EXTI_IMR2_IM57_Msk                          /*!< Interrupt Mask on line 57 */

+#define EXTI_IMR2_IM58_Pos         (26U)

+#define EXTI_IMR2_IM58_Msk         (0x1UL << EXTI_IMR2_IM58_Pos)               /*!< 0x04000000 */

+#define EXTI_IMR2_IM58             EXTI_IMR2_IM58_Msk                          /*!< Interrupt Mask on line 58 */

+#define EXTI_IMR2_IM59_Pos         (27U)

+#define EXTI_IMR2_IM59_Msk         (0x1UL << EXTI_IMR2_IM59_Pos)               /*!< 0x08000000 */

+#define EXTI_IMR2_IM59             EXTI_IMR2_IM59_Msk                          /*!< Interrupt Mask on line 59 */

+#define EXTI_IMR2_IM60_Pos         (28U)

+#define EXTI_IMR2_IM60_Msk         (0x1UL << EXTI_IMR2_IM60_Pos)               /*!< 0x10000000 */

+#define EXTI_IMR2_IM60             EXTI_IMR2_IM60_Msk                          /*!< Interrupt Mask on line 60 */

+#define EXTI_IMR2_IM61_Pos         (29U)

+#define EXTI_IMR2_IM61_Msk         (0x1UL << EXTI_IMR2_IM61_Pos)               /*!< 0x20000000 */

+#define EXTI_IMR2_IM61             EXTI_IMR2_IM61_Msk                          /*!< Interrupt Mask on line 61 */

+#define EXTI_IMR2_IM62_Pos         (30U)

+#define EXTI_IMR2_IM62_Msk         (0x1UL << EXTI_IMR2_IM62_Pos)               /*!< 0x40000000 */

+#define EXTI_IMR2_IM62             EXTI_IMR2_IM62_Msk                          /*!< Interrupt Mask on line 62 */

+#define EXTI_IMR2_IM63_Pos         (31U)

+#define EXTI_IMR2_IM63_Msk         (0x1UL << EXTI_IMR2_IM63_Pos)               /*!< 0x80000000 */

+#define EXTI_IMR2_IM63             EXTI_IMR2_IM63_Msk                          /*!< Interrupt Mask on line 63 */

+

+/*******************  Bit definition for EXTI_EMR2 register  *******************/

+#define EXTI_EMR2_EM_Pos           (0U)

+#define EXTI_EMR2_EM_Msk           (0xFFFF8FFFUL << EXTI_EMR2_EM_Pos)          /*!< 0xFFFF8FFF */

+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            /*!< Event Mask           */

+#define EXTI_EMR2_EM32_Pos         (0U)

+#define EXTI_EMR2_EM32_Msk         (0x1UL << EXTI_EMR2_EM32_Pos)               /*!< 0x00000001 */

+#define EXTI_EMR2_EM32             EXTI_EMR2_EM32_Msk                          /*!< Event Mask on line 32*/

+#define EXTI_EMR2_EM33_Pos         (1U)

+#define EXTI_EMR2_EM33_Msk         (0x1UL << EXTI_EMR2_EM33_Pos)               /*!< 0x00000002 */

+#define EXTI_EMR2_EM33             EXTI_EMR2_EM33_Msk                          /*!< Event Mask on line 33*/

+#define EXTI_EMR2_EM34_Pos         (2U)

+#define EXTI_EMR2_EM34_Msk         (0x1UL << EXTI_EMR2_EM34_Pos)               /*!< 0x00000004 */

+#define EXTI_EMR2_EM34             EXTI_EMR2_EM34_Msk                          /*!< Event Mask on line 34*/

+#define EXTI_EMR2_EM35_Pos         (3U)

+#define EXTI_EMR2_EM35_Msk         (0x1UL << EXTI_EMR2_EM35_Pos)               /*!< 0x00000008 */

+#define EXTI_EMR2_EM35             EXTI_EMR2_EM35_Msk                          /*!< Event Mask on line 35*/

+#define EXTI_EMR2_EM36_Pos         (4U)

+#define EXTI_EMR2_EM36_Msk         (0x1UL << EXTI_EMR2_EM36_Pos)               /*!< 0x00000010 */

+#define EXTI_EMR2_EM36             EXTI_EMR2_EM36_Msk                          /*!< Event Mask on line 36*/

+#define EXTI_EMR2_EM37_Pos         (5U)

+#define EXTI_EMR2_EM37_Msk         (0x1UL << EXTI_EMR2_EM37_Pos)               /*!< 0x00000020 */

+#define EXTI_EMR2_EM37             EXTI_EMR2_EM37_Msk                          /*!< Event Mask on line 37*/

+#define EXTI_EMR2_EM38_Pos         (6U)

+#define EXTI_EMR2_EM38_Msk         (0x1UL << EXTI_EMR2_EM38_Pos)               /*!< 0x00000040 */

+#define EXTI_EMR2_EM38             EXTI_EMR2_EM38_Msk                          /*!< Event Mask on line 38*/

+#define EXTI_EMR2_EM39_Pos         (7U)

+#define EXTI_EMR2_EM39_Msk         (0x1UL << EXTI_EMR2_EM39_Pos)               /*!< 0x00000080 */

+#define EXTI_EMR2_EM39             EXTI_EMR2_EM39_Msk                          /*!< Event Mask on line 39*/

+#define EXTI_EMR2_EM40_Pos         (8U)

+#define EXTI_EMR2_EM40_Msk         (0x1UL << EXTI_EMR2_EM40_Pos)               /*!< 0x00000100 */

+#define EXTI_EMR2_EM40             EXTI_EMR2_EM40_Msk                          /*!< Event Mask on line 40*/

+#define EXTI_EMR2_EM41_Pos         (9U)

+#define EXTI_EMR2_EM41_Msk         (0x1UL << EXTI_EMR2_EM41_Pos)               /*!< 0x00000200 */

+#define EXTI_EMR2_EM41             EXTI_EMR2_EM41_Msk                          /*!< Event Mask on line 41*/

+#define EXTI_EMR2_EM42_Pos         (10U)

+#define EXTI_EMR2_EM42_Msk         (0x1UL << EXTI_EMR2_EM42_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR2_EM42             EXTI_EMR2_EM42_Msk                          /*!< Event Mask on line 42 */

+#define EXTI_EMR2_EM43_Pos         (11U)

+#define EXTI_EMR2_EM43_Msk         (0x1UL << EXTI_EMR2_EM43_Pos)               /*!< 0x00000800 */

+#define EXTI_EMR2_EM43             EXTI_EMR2_EM43_Msk                          /*!< Event Mask on line 43 */

+#define EXTI_EMR2_EM47_Pos         (15U)

+#define EXTI_EMR2_EM47_Msk         (0x1UL << EXTI_EMR2_EM47_Pos)               /*!< 0x00008000 */

+#define EXTI_EMR2_EM47             EXTI_EMR2_EM47_Msk                          /*!< Event Mask on line 47 */

+#define EXTI_EMR2_EM48_Pos         (16U)

+#define EXTI_EMR2_EM48_Msk         (0x1UL << EXTI_EMR2_EM48_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR2_EM48             EXTI_EMR2_EM48_Msk                          /*!< Event Mask on line 48 */

+#define EXTI_EMR2_EM49_Pos         (17U)

+#define EXTI_EMR2_EM49_Msk         (0x1UL << EXTI_EMR2_EM49_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR2_EM49             EXTI_EMR2_EM49_Msk                          /*!< Event Mask on line 49 */

+#define EXTI_EMR2_EM50_Pos         (18U)

+#define EXTI_EMR2_EM50_Msk         (0x1UL << EXTI_EMR2_EM50_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR2_EM50             EXTI_EMR2_EM50_Msk                          /*!< Event Mask on line 50 */

+#define EXTI_EMR2_EM51_Pos         (19U)

+#define EXTI_EMR2_EM51_Msk         (0x1UL << EXTI_EMR2_EM51_Pos)               /*!< 0x00080000 */

+#define EXTI_EMR2_EM51             EXTI_EMR2_EM51_Msk                          /*!< Event Mask on line 51 */

+#define EXTI_EMR2_EM52_Pos         (20U)

+#define EXTI_EMR2_EM52_Msk         (0x1UL << EXTI_EMR2_EM52_Pos)               /*!< 0x00100000 */

+#define EXTI_EMR2_EM52             EXTI_EMR2_EM52_Msk                          /*!< Event Mask on line 52 */

+#define EXTI_EMR2_EM53_Pos         (21U)

+#define EXTI_EMR2_EM53_Msk         (0x1UL << EXTI_EMR2_EM53_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR2_EM53             EXTI_EMR2_EM53_Msk                          /*!< Event Mask on line 53 */

+#define EXTI_EMR2_EM54_Pos         (22U)

+#define EXTI_EMR2_EM54_Msk         (0x1UL << EXTI_EMR2_EM54_Pos)               /*!< 0x00400000 */

+#define EXTI_EMR2_EM54             EXTI_EMR2_EM54_Msk                          /*!< Event Mask on line 54 */

+#define EXTI_EMR2_EM55_Pos         (23U)

+#define EXTI_EMR2_EM55_Msk         (0x1UL << EXTI_EMR2_EM55_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR2_EM55             EXTI_EMR2_EM55_Msk                          /*!< Event Mask on line 55 */

+#define EXTI_EMR2_EM56_Pos         (24U)

+#define EXTI_EMR2_EM56_Msk         (0x1UL << EXTI_EMR2_EM56_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR2_EM56             EXTI_EMR2_EM56_Msk                          /*!< Event Mask on line 56 */

+#define EXTI_EMR2_EM57_Pos         (25U)

+#define EXTI_EMR2_EM57_Msk         (0x1UL << EXTI_EMR2_EM57_Pos)               /*!< 0x02000000 */

+#define EXTI_EMR2_EM57             EXTI_EMR2_EM57_Msk                          /*!< Event Mask on line 57 */

+#define EXTI_EMR2_EM58_Pos         (26U)

+#define EXTI_EMR2_EM58_Msk         (0x1UL << EXTI_EMR2_EM58_Pos)               /*!< 0x04000000 */

+#define EXTI_EMR2_EM58             EXTI_EMR2_EM58_Msk                          /*!< Event Mask on line 58 */

+#define EXTI_EMR2_EM59_Pos         (27U)

+#define EXTI_EMR2_EM59_Msk         (0x1UL << EXTI_EMR2_EM59_Pos)               /*!< 0x08000000 */

+#define EXTI_EMR2_EM59             EXTI_EMR2_EM59_Msk                          /*!< Event Mask on line 59 */

+#define EXTI_EMR2_EM60_Pos         (28U)

+#define EXTI_EMR2_EM60_Msk         (0x1UL << EXTI_EMR2_EM60_Pos)               /*!< 0x10000000 */

+#define EXTI_EMR2_EM60             EXTI_EMR2_EM60_Msk                          /*!< Event Mask on line 60 */

+#define EXTI_EMR2_EM61_Pos         (29U)

+#define EXTI_EMR2_EM61_Msk         (0x1UL << EXTI_EMR2_EM61_Pos)               /*!< 0x20000000 */

+#define EXTI_EMR2_EM61             EXTI_EMR2_EM61_Msk                          /*!< Event Mask on line 61 */

+#define EXTI_EMR2_EM62_Pos         (30U)

+#define EXTI_EMR2_EM62_Msk         (0x1UL << EXTI_EMR2_EM62_Pos)               /*!< 0x40000000 */

+#define EXTI_EMR2_EM62             EXTI_EMR2_EM62_Msk                          /*!< Event Mask on line 62 */

+#define EXTI_EMR2_EM63_Pos         (31U)

+#define EXTI_EMR2_EM63_Msk         (0x1UL << EXTI_EMR2_EM63_Pos)               /*!< 0x80000000 */

+#define EXTI_EMR2_EM63             EXTI_EMR2_EM63_Msk                          /*!< Event Mask on line 63 */

+

+/*******************  Bit definition for EXTI_PR2 register  ********************/

+#define EXTI_PR2_PR_Pos            (17U)

+#define EXTI_PR2_PR_Msk            (0x5UL << EXTI_PR2_PR_Pos)                  /*!< 0x000A0000 */

+#define EXTI_PR2_PR                EXTI_PR2_PR_Msk                             /*!< Pending bit */

+#define EXTI_PR2_PR49_Pos          (17U)

+#define EXTI_PR2_PR49_Msk          (0x1UL << EXTI_PR2_PR49_Pos)                /*!< 0x00020000 */

+#define EXTI_PR2_PR49              EXTI_PR2_PR49_Msk                           /*!< Pending bit for line 49 */

+#define EXTI_PR2_PR51_Pos          (19U)

+#define EXTI_PR2_PR51_Msk          (0x1UL << EXTI_PR2_PR51_Pos)                /*!< 0x00080000 */

+#define EXTI_PR2_PR51              EXTI_PR2_PR51_Msk                           /*!< Pending bit for line 51 */

+

+/*******************  Bit definition for EXTI_IMR3 register  *******************/

+#define EXTI_IMR3_IM_Pos           (0U)

+#define EXTI_IMR3_IM_Msk           (0x001A527FFUL << EXTI_IMR3_IM_Pos)         /*!< 0x001A527FF */

+#define EXTI_IMR3_IM               EXTI_IMR3_IM_Msk                            /*!< Interrupt Mask            */

+#define EXTI_IMR3_IM64_Pos         (0U)

+#define EXTI_IMR3_IM64_Msk         (0x1UL << EXTI_IMR3_IM64_Pos)               /*!< 0x00000001 */

+#define EXTI_IMR3_IM64             EXTI_IMR3_IM64_Msk                          /*!< Interrupt Mask on line 64 */

+#define EXTI_IMR3_IM65_Pos         (1U)

+#define EXTI_IMR3_IM65_Msk         (0x1UL << EXTI_IMR3_IM65_Pos)               /*!< 0x00000002 */

+#define EXTI_IMR3_IM65             EXTI_IMR3_IM65_Msk                          /*!< Interrupt Mask on line 65 */

+#define EXTI_IMR3_IM66_Pos         (2U)

+#define EXTI_IMR3_IM66_Msk         (0x1UL << EXTI_IMR3_IM66_Pos)               /*!< 0x00000004 */

+#define EXTI_IMR3_IM66             EXTI_IMR3_IM66_Msk                          /*!< Interrupt Mask on line 66 */

+#define EXTI_IMR3_IM67_Pos         (3U)

+#define EXTI_IMR3_IM67_Msk         (0x1UL << EXTI_IMR3_IM67_Pos)               /*!< 0x00000008 */

+#define EXTI_IMR3_IM67             EXTI_IMR3_IM67_Msk                          /*!< Interrupt Mask on line 67 */

+#define EXTI_IMR3_IM68_Pos         (4U)

+#define EXTI_IMR3_IM68_Msk         (0x1UL << EXTI_IMR3_IM68_Pos)               /*!< 0x00000010 */

+#define EXTI_IMR3_IM68             EXTI_IMR3_IM68_Msk                          /*!< Interrupt Mask on line 68 */

+#define EXTI_IMR3_IM69_Pos         (5U)

+#define EXTI_IMR3_IM69_Msk         (0x1UL << EXTI_IMR3_IM69_Pos)               /*!< 0x00000020 */

+#define EXTI_IMR3_IM69             EXTI_IMR3_IM69_Msk                          /*!< Interrupt Mask on line 69 */

+#define EXTI_IMR3_IM70_Pos         (6U)

+#define EXTI_IMR3_IM70_Msk         (0x1UL << EXTI_IMR3_IM70_Pos)               /*!< 0x00000040 */

+#define EXTI_IMR3_IM70             EXTI_IMR3_IM70_Msk                          /*!< Interrupt Mask on line 70 */

+#define EXTI_IMR3_IM71_Pos         (7U)

+#define EXTI_IMR3_IM71_Msk         (0x1UL << EXTI_IMR3_IM71_Pos)               /*!< 0x00000080 */

+#define EXTI_IMR3_IM71             EXTI_IMR3_IM71_Msk                          /*!< Interrupt Mask on line 71 */

+#define EXTI_IMR3_IM72_Pos         (8U)

+#define EXTI_IMR3_IM72_Msk         (0x1UL << EXTI_IMR3_IM72_Pos)               /*!< 0x00000100 */

+#define EXTI_IMR3_IM72             EXTI_IMR3_IM72_Msk                          /*!< Interrupt Mask on line 72 */

+#define EXTI_IMR3_IM73_Pos         (9U)

+#define EXTI_IMR3_IM73_Msk         (0x1UL << EXTI_IMR3_IM73_Pos)               /*!< 0x00000200 */

+#define EXTI_IMR3_IM73             EXTI_IMR3_IM73_Msk                          /*!< Interrupt Mask on line 73 */

+#define EXTI_IMR3_IM74_Pos         (10U)

+#define EXTI_IMR3_IM74_Msk         (0x1UL << EXTI_IMR3_IM74_Pos)               /*!< 0x00000400 */

+#define EXTI_IMR3_IM74             EXTI_IMR3_IM74_Msk                          /*!< Interrupt Mask on line 74 */

+#define EXTI_IMR3_IM77_Pos         (13U)

+#define EXTI_IMR3_IM77_Msk         (0x1UL << EXTI_IMR3_IM77_Pos)               /*!< 0x00002000 */

+#define EXTI_IMR3_IM77             EXTI_IMR3_IM77_Msk                          /*!< Interrupt Mask on line 77 */

+#define EXTI_IMR3_IM80_Pos         (16U)

+#define EXTI_IMR3_IM80_Msk         (0x1UL << EXTI_IMR3_IM80_Pos)               /*!< 0x00010000 */

+#define EXTI_IMR3_IM80             EXTI_IMR3_IM80_Msk                          /*!< Interrupt Mask on line 80 */

+#define EXTI_IMR3_IM82_Pos         (18U)

+#define EXTI_IMR3_IM82_Msk         (0x1UL << EXTI_IMR3_IM82_Pos)               /*!< 0x00040000 */

+#define EXTI_IMR3_IM82             EXTI_IMR3_IM82_Msk                          /*!< Interrupt Mask on line 82 */

+#define EXTI_IMR3_IM85_Pos         (21U)

+#define EXTI_IMR3_IM85_Msk         (0x1UL << EXTI_IMR3_IM85_Pos)               /*!< 0x00200000 */

+#define EXTI_IMR3_IM85             EXTI_IMR3_IM85_Msk                          /*!< Interrupt Mask on line 85 */

+#define EXTI_IMR3_IM87_Pos         (23U)

+#define EXTI_IMR3_IM87_Msk         (0x1UL << EXTI_IMR3_IM87_Pos)               /*!< 0x00800000 */

+#define EXTI_IMR3_IM87             EXTI_IMR3_IM87_Msk                          /*!< Interrupt Mask on line 87 */

+

+

+#define EXTI_IMR3_IM88_Pos         (24U)

+#define EXTI_IMR3_IM88_Msk         (0x1UL << EXTI_IMR3_IM88_Pos)               /*!< 0x01000000 */

+#define EXTI_IMR3_IM88             EXTI_IMR3_IM88_Msk                          /*!< Interrupt Mask on line 88 */

+

+/*******************  Bit definition for EXTI_EMR3 register  *******************/

+#define EXTI_EMR3_EM_Pos           (0U)

+#define EXTI_EMR3_EM_Msk           (0x01A527FFUL << EXTI_EMR3_EM_Pos)          /*!< 0x01A527FF */

+#define EXTI_EMR3_EM               EXTI_EMR3_EM_Msk                            /*!< Event Mask           */

+#define EXTI_EMR3_EM64_Pos         (0U)

+#define EXTI_EMR3_EM64_Msk         (0x1UL << EXTI_EMR3_EM64_Pos)               /*!< 0x00000001 */

+#define EXTI_EMR3_EM64             EXTI_EMR3_EM64_Msk                          /*!< Event Mask on line 64*/

+#define EXTI_EMR3_EM65_Pos         (1U)

+#define EXTI_EMR3_EM65_Msk         (0x1UL << EXTI_EMR3_EM65_Pos)               /*!< 0x00000002 */

+#define EXTI_EMR3_EM65             EXTI_EMR3_EM65_Msk                          /*!< Event Mask on line 65*/

+#define EXTI_EMR3_EM66_Pos         (2U)

+#define EXTI_EMR3_EM66_Msk         (0x1UL << EXTI_EMR3_EM66_Pos)               /*!< 0x00000004 */

+#define EXTI_EMR3_EM66             EXTI_EMR3_EM66_Msk                          /*!< Event Mask on line 66*/

+#define EXTI_EMR3_EM67_Pos         (3U)

+#define EXTI_EMR3_EM67_Msk         (0x1UL << EXTI_EMR3_EM67_Pos)               /*!< 0x00000008 */

+#define EXTI_EMR3_EM67             EXTI_EMR3_EM67_Msk                          /*!< Event Mask on line 67*/

+#define EXTI_EMR3_EM68_Pos         (4U)

+#define EXTI_EMR3_EM68_Msk         (0x1UL << EXTI_EMR3_EM68_Pos)               /*!< 0x00000010 */

+#define EXTI_EMR3_EM68             EXTI_EMR3_EM68_Msk                          /*!< Event Mask on line 68*/

+#define EXTI_EMR3_EM69_Pos         (5U)

+#define EXTI_EMR3_EM69_Msk         (0x1UL << EXTI_EMR3_EM69_Pos)               /*!< 0x00000020 */

+#define EXTI_EMR3_EM69             EXTI_EMR3_EM69_Msk                          /*!< Event Mask on line 69*/

+#define EXTI_EMR3_EM70_Pos         (6U)

+#define EXTI_EMR3_EM70_Msk         (0x1UL << EXTI_EMR3_EM70_Pos)               /*!< 0x00000040 */

+#define EXTI_EMR3_EM70             EXTI_EMR3_EM70_Msk                          /*!< Event Mask on line 70*/

+#define EXTI_EMR3_EM71_Pos         (7U)

+#define EXTI_EMR3_EM71_Msk         (0x1UL << EXTI_EMR3_EM71_Pos)               /*!< 0x00000080 */

+#define EXTI_EMR3_EM71             EXTI_EMR3_EM71_Msk                          /*!< Event Mask on line 71*/

+#define EXTI_EMR3_EM72_Pos         (8U)

+#define EXTI_EMR3_EM72_Msk         (0x1UL << EXTI_EMR3_EM72_Pos)               /*!< 0x00000100 */

+#define EXTI_EMR3_EM72             EXTI_EMR3_EM72_Msk                          /*!< Event Mask on line 72*/

+#define EXTI_EMR3_EM73_Pos         (9U)

+#define EXTI_EMR3_EM73_Msk         (0x1UL << EXTI_EMR3_EM73_Pos)               /*!< 0x00000200 */

+#define EXTI_EMR3_EM73             EXTI_EMR3_EM73_Msk                          /*!< Event Mask on line 73*/

+#define EXTI_EMR3_EM74_Pos         (10U)

+#define EXTI_EMR3_EM74_Msk         (0x1UL << EXTI_EMR3_EM74_Pos)               /*!< 0x00000400 */

+#define EXTI_EMR3_EM74             EXTI_EMR3_EM74_Msk                          /*!< Event Mask on line 74 */

+#define EXTI_EMR3_EM77_Pos         (13U)

+#define EXTI_EMR3_EM77_Msk         (0x1UL << EXTI_EMR3_EM77_Pos)               /*!< 0x00002000 */

+#define EXTI_EMR3_EM77             EXTI_EMR3_EM77_Msk                          /*!< Event Mask on line 77 */

+#define EXTI_EMR3_EM80_Pos         (16U)

+#define EXTI_EMR3_EM80_Msk         (0x1UL << EXTI_EMR3_EM80_Pos)               /*!< 0x00010000 */

+#define EXTI_EMR3_EM80             EXTI_EMR3_EM80_Msk                          /*!< Event Mask on line 80 */

+#define EXTI_EMR3_EM81_Pos         (17U)

+#define EXTI_EMR3_EM81_Msk         (0x1UL << EXTI_EMR3_EM81_Pos)               /*!< 0x00020000 */

+#define EXTI_EMR3_EM81             EXTI_EMR3_EM81_Msk                          /*!< Event Mask on line 81 */

+#define EXTI_EMR3_EM82_Pos         (18U)

+#define EXTI_EMR3_EM82_Msk         (0x1UL << EXTI_EMR3_EM82_Pos)               /*!< 0x00040000 */

+#define EXTI_EMR3_EM82             EXTI_EMR3_EM82_Msk                          /*!< Event Mask on line 82 */

+#define EXTI_EMR3_EM85_Pos         (21U)

+#define EXTI_EMR3_EM85_Msk         (0x1UL << EXTI_EMR3_EM85_Pos)               /*!< 0x00200000 */

+#define EXTI_EMR3_EM85             EXTI_EMR3_EM85_Msk                          /*!< Event Mask on line 85 */

+#define EXTI_EMR3_EM87_Pos         (23U)

+#define EXTI_EMR3_EM87_Msk         (0x1UL << EXTI_EMR3_EM87_Pos)               /*!< 0x00800000 */

+#define EXTI_EMR3_EM87             EXTI_EMR3_EM87_Msk                          /*!< Event Mask on line 87 */

+

+#define EXTI_EMR3_EM88_Pos         (24U)

+#define EXTI_EMR3_EM88_Msk         (0x1UL << EXTI_EMR3_EM88_Pos)               /*!< 0x01000000 */

+#define EXTI_EMR3_EM88             EXTI_EMR3_EM88_Msk                          /*!< Event Mask on line 88 */

+

+/*******************  Bit definition for EXTI_PR3 register  ********************/

+#define EXTI_PR3_PR_Pos            (18U)

+#define EXTI_PR3_PR_Msk            (0x9UL << EXTI_PR3_PR_Pos)                  /*!< 0x00240000 */

+#define EXTI_PR3_PR                EXTI_PR3_PR_Msk                             /*!< Pending bit             */

+#define EXTI_PR3_PR82_Pos          (18U)

+#define EXTI_PR3_PR82_Msk          (0x1UL << EXTI_PR3_PR82_Pos)                /*!< 0x00040000 */

+#define EXTI_PR3_PR82              EXTI_PR3_PR82_Msk                           /*!< Pending bit for line 82 */

+#define EXTI_PR3_PR85_Pos          (21U)

+#define EXTI_PR3_PR85_Msk          (0x1UL << EXTI_PR3_PR85_Pos)                /*!< 0x00200000 */

+#define EXTI_PR3_PR85              EXTI_PR3_PR85_Msk                           /*!< Pending bit for line 85 */

+/******************************************************************************/

+/*                                                                            */

+/*                                    FLASH                                   */

+/*                                                                            */

+/******************************************************************************/

+/*

+* @brief FLASH Global Defines

+*/

+#define FLASH_SECTOR_TOTAL                   128U                  /* 128 sectors */

+#define FLASH_SIZE                           0x200000UL            /* 2 MB   */

+#define FLASH_BANK_SIZE                      (FLASH_SIZE >> 1)     /* 1 MB   */

+#define FLASH_SECTOR_SIZE                    0x00002000UL          /* 8 KB   */

+#define FLASH_LATENCY_DEFAULT                FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycles */

+#define FLASH_NB_32BITWORD_IN_FLASHWORD      4U                    /* 128 bits */

+#define DUAL_BANK                                                  /* Dual-bank Flash */

+

+/*******************  Bits definition for FLASH_ACR register  **********************/

+#define FLASH_ACR_LATENCY_Pos                (0U)

+#define FLASH_ACR_LATENCY_Msk                (0xFUL << FLASH_ACR_LATENCY_Pos)  /*!< 0x0000000F */

+#define FLASH_ACR_LATENCY                    FLASH_ACR_LATENCY_Msk             /*!< Read Latency */

+#define FLASH_ACR_LATENCY_0WS                (0x00000000UL)

+#define FLASH_ACR_LATENCY_1WS                (0x00000001UL)

+#define FLASH_ACR_LATENCY_2WS                (0x00000002UL)

+#define FLASH_ACR_LATENCY_3WS                (0x00000003UL)

+#define FLASH_ACR_LATENCY_4WS                (0x00000004UL)

+#define FLASH_ACR_LATENCY_5WS                (0x00000005UL)

+#define FLASH_ACR_LATENCY_6WS                (0x00000006UL)

+#define FLASH_ACR_LATENCY_7WS                (0x00000007UL)

+#define FLASH_ACR_LATENCY_8WS                (0x00000008UL)

+#define FLASH_ACR_LATENCY_9WS                (0x00000009UL)

+#define FLASH_ACR_LATENCY_10WS               (0x0000000AUL)

+#define FLASH_ACR_LATENCY_11WS               (0x0000000BUL)

+#define FLASH_ACR_LATENCY_12WS               (0x0000000CUL)

+#define FLASH_ACR_LATENCY_13WS               (0x0000000DUL)

+#define FLASH_ACR_LATENCY_14WS               (0x0000000EUL)

+#define FLASH_ACR_LATENCY_15WS               (0x0000000FUL)

+#define FLASH_ACR_WRHIGHFREQ_Pos             (4U)

+#define FLASH_ACR_WRHIGHFREQ_Msk             (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000030 */

+#define FLASH_ACR_WRHIGHFREQ                 FLASH_ACR_WRHIGHFREQ_Msk             /*!< Flash signal delay */

+#define FLASH_ACR_WRHIGHFREQ_0               (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000010 */

+#define FLASH_ACR_WRHIGHFREQ_1               (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos)  /*!< 0x00000020 */

+

+/*******************  Bits definition for FLASH_CR register  ***********************/

+#define FLASH_CR_LOCK_Pos                    (0U)

+#define FLASH_CR_LOCK_Msk                    (0x1UL << FLASH_CR_LOCK_Pos)      /*!< 0x00000001 */

+#define FLASH_CR_LOCK                        FLASH_CR_LOCK_Msk                 /*!< Configuration lock bit */

+#define FLASH_CR_PG_Pos                      (1U)

+#define FLASH_CR_PG_Msk                      (0x1UL << FLASH_CR_PG_Pos)        /*!< 0x00000002 */

+#define FLASH_CR_PG                          FLASH_CR_PG_Msk                   /*!< Internal buffer control bit */

+#define FLASH_CR_SER_Pos                     (2U)

+#define FLASH_CR_SER_Msk                     (0x1UL << FLASH_CR_SER_Pos)       /*!< 0x00000004 */

+#define FLASH_CR_SER                         FLASH_CR_SER_Msk                  /*!< Sector erase request */

+#define FLASH_CR_BER_Pos                     (3U)

+#define FLASH_CR_BER_Msk                     (0x1UL << FLASH_CR_BER_Pos)       /*!< 0x00000008 */

+#define FLASH_CR_BER                         FLASH_CR_BER_Msk                  /*!< Bank erase request */

+#define FLASH_CR_FW_Pos                      (4U)

+#define FLASH_CR_FW_Msk                      (0x1UL << FLASH_CR_FW_Pos)        /*!< 0x00000010 */

+#define FLASH_CR_FW                          FLASH_CR_FW_Msk                   /*!< Write forcing control bit */

+#define FLASH_CR_START_Pos                   (5U)

+#define FLASH_CR_START_Msk                   (0x1UL << FLASH_CR_START_Pos)     /*!< 0x00000020 */

+#define FLASH_CR_START                       FLASH_CR_START_Msk                /*!< Erase start control bit */

+#define FLASH_CR_SNB_Pos                     (6U)

+#define FLASH_CR_SNB_Msk                     (0x7FUL << FLASH_CR_SNB_Pos)      /*!< 0x00001FC0 */

+#define FLASH_CR_SNB                         FLASH_CR_SNB_Msk                  /*!< Sector erase selection number */

+#define FLASH_CR_SNB_0                       (0x01UL << FLASH_CR_SNB_Pos)      /*!< 0x00000040 */

+#define FLASH_CR_SNB_1                       (0x02UL << FLASH_CR_SNB_Pos)      /*!< 0x00000080 */

+#define FLASH_CR_SNB_2                       (0x04UL << FLASH_CR_SNB_Pos)      /*!< 0x00000100 */

+#define FLASH_CR_SNB_3                       (0x08UL << FLASH_CR_SNB_Pos)      /*!< 0x00000200 */

+#define FLASH_CR_SNB_4                       (0x10UL << FLASH_CR_SNB_Pos)      /*!< 0x00000400 */

+#define FLASH_CR_SNB_5                       (0x20UL << FLASH_CR_SNB_Pos)      /*!< 0x00000800 */

+#define FLASH_CR_SNB_6                       (0x40UL << FLASH_CR_SNB_Pos)      /*!< 0x00001000 */

+#define FLASH_CR_CRC_EN_Pos                  (15U)

+#define FLASH_CR_CRC_EN_Msk                  (0x1UL << FLASH_CR_CRC_EN_Pos)    /*!< 0x00008000 */

+#define FLASH_CR_CRC_EN                      FLASH_CR_CRC_EN_Msk               /*!< CRC control bit */

+#define FLASH_CR_EOPIE_Pos                   (16U)

+#define FLASH_CR_EOPIE_Msk                   (0x1UL << FLASH_CR_EOPIE_Pos)     /*!< 0x00010000 */

+#define FLASH_CR_EOPIE                       FLASH_CR_EOPIE_Msk                /*!< End-of-program interrupt control bit */

+#define FLASH_CR_WRPERRIE_Pos                (17U)

+#define FLASH_CR_WRPERRIE_Msk                (0x1UL << FLASH_CR_WRPERRIE_Pos)  /*!< 0x00020000 */

+#define FLASH_CR_WRPERRIE                    FLASH_CR_WRPERRIE_Msk             /*!< Write protection error interrupt enable bit */

+#define FLASH_CR_PGSERRIE_Pos                (18U)

+#define FLASH_CR_PGSERRIE_Msk                (0x1UL << FLASH_CR_PGSERRIE_Pos)  /*!< 0x00040000 */

+#define FLASH_CR_PGSERRIE                    FLASH_CR_PGSERRIE_Msk             /*!< Programming sequence error interrupt enable bit */

+#define FLASH_CR_STRBERRIE_Pos               (19U)

+#define FLASH_CR_STRBERRIE_Msk               (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */

+#define FLASH_CR_STRBERRIE                   FLASH_CR_STRBERRIE_Msk            /*!< Strobe error interrupt enable bit */

+#define FLASH_CR_INCERRIE_Pos                (21U)

+#define FLASH_CR_INCERRIE_Msk                (0x1UL << FLASH_CR_INCERRIE_Pos)  /*!< 0x00200000 */

+#define FLASH_CR_INCERRIE                    FLASH_CR_INCERRIE_Msk             /*!< Inconsistency error interrupt enable bit */

+#define FLASH_CR_RDPERRIE_Pos                (23U)

+#define FLASH_CR_RDPERRIE_Msk                (0x1UL << FLASH_CR_RDPERRIE_Pos)  /*!< 0x00800000 */

+#define FLASH_CR_RDPERRIE                    FLASH_CR_RDPERRIE_Msk             /*!< Read protection error interrupt enable bit */

+#define FLASH_CR_RDSERRIE_Pos                (24U)

+#define FLASH_CR_RDSERRIE_Msk                (0x1UL << FLASH_CR_RDSERRIE_Pos)  /*!< 0x01000000 */

+#define FLASH_CR_RDSERRIE                    FLASH_CR_RDSERRIE_Msk             /*!< Secure error interrupt enable bit */

+#define FLASH_CR_SNECCERRIE_Pos              (25U)

+#define FLASH_CR_SNECCERRIE_Msk              (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */

+#define FLASH_CR_SNECCERRIE                  FLASH_CR_SNECCERRIE_Msk            /*!< ECC single correction error interrupt enable bit */

+#define FLASH_CR_DBECCERRIE_Pos              (26U)

+#define FLASH_CR_DBECCERRIE_Msk              (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */

+#define FLASH_CR_DBECCERRIE                  FLASH_CR_DBECCERRIE_Msk            /*!< ECC double detection error interrupt enable bit */

+#define FLASH_CR_CRCENDIE_Pos                (27U)

+#define FLASH_CR_CRCENDIE_Msk                (0x1UL << FLASH_CR_CRCENDIE_Pos)  /*!< 0x08000000 */

+#define FLASH_CR_CRCENDIE                    FLASH_CR_CRCENDIE_Msk             /*!< CRC end of calculation interrupt enable bit */

+#define FLASH_CR_CRCRDERRIE_Pos              (28U)

+#define FLASH_CR_CRCRDERRIE_Msk              (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */

+#define FLASH_CR_CRCRDERRIE                  FLASH_CR_CRCRDERRIE_Msk            /*!< CRC read error interrupt enable bit */

+

+/*******************  Bits definition for FLASH_SR register  ***********************/

+#define FLASH_SR_BSY_Pos                     (0U)

+#define FLASH_SR_BSY_Msk                     (0x1UL << FLASH_SR_BSY_Pos)       /*!< 0x00000001 */

+#define FLASH_SR_BSY                         FLASH_SR_BSY_Msk                  /*!< Busy flag */

+#define FLASH_SR_WBNE_Pos                    (1U)

+#define FLASH_SR_WBNE_Msk                    (0x1UL << FLASH_SR_WBNE_Pos)      /*!< 0x00000002 */

+#define FLASH_SR_WBNE                        FLASH_SR_WBNE_Msk                 /*!< Write buffer not empty flag */

+#define FLASH_SR_QW_Pos                      (2U)

+#define FLASH_SR_QW_Msk                      (0x1UL << FLASH_SR_QW_Pos)        /*!< 0x00000004 */

+#define FLASH_SR_QW                          FLASH_SR_QW_Msk                   /*!< Wait queue flag */

+#define FLASH_SR_CRC_BUSY_Pos                (3U)

+#define FLASH_SR_CRC_BUSY_Msk                (0x1UL << FLASH_SR_CRC_BUSY_Pos)  /*!< 0x00000008 */

+#define FLASH_SR_CRC_BUSY                    FLASH_SR_CRC_BUSY_Msk             /*!< CRC busy flag */

+#define FLASH_SR_EOP_Pos                     (16U)

+#define FLASH_SR_EOP_Msk                     (0x1UL << FLASH_SR_EOP_Pos)       /*!< 0x00010000 */

+#define FLASH_SR_EOP                         FLASH_SR_EOP_Msk                  /*!< End-of-program flag */

+#define FLASH_SR_WRPERR_Pos                  (17U)

+#define FLASH_SR_WRPERR_Msk                  (0x1UL << FLASH_SR_WRPERR_Pos)    /*!< 0x00020000 */

+#define FLASH_SR_WRPERR                      FLASH_SR_WRPERR_Msk               /*!< Write protection error flag */

+#define FLASH_SR_PGSERR_Pos                  (18U)

+#define FLASH_SR_PGSERR_Msk                  (0x1UL << FLASH_SR_PGSERR_Pos)    /*!< 0x00040000 */

+#define FLASH_SR_PGSERR                      FLASH_SR_PGSERR_Msk               /*!< Programming sequence error flag */

+#define FLASH_SR_STRBERR_Pos                 (19U)

+#define FLASH_SR_STRBERR_Msk                 (0x1UL << FLASH_SR_STRBERR_Pos)   /*!< 0x00080000 */

+#define FLASH_SR_STRBERR                     FLASH_SR_STRBERR_Msk              /*!< Strobe error flag */

+#define FLASH_SR_INCERR_Pos                  (21U)

+#define FLASH_SR_INCERR_Msk                  (0x1UL << FLASH_SR_INCERR_Pos)    /*!< 0x00200000 */

+#define FLASH_SR_INCERR                      FLASH_SR_INCERR_Msk               /*!< Inconsistency error flag */

+#define FLASH_SR_RDPERR_Pos                  (23U)

+#define FLASH_SR_RDPERR_Msk                  (0x1UL << FLASH_SR_RDPERR_Pos)    /*!< 0x00800000 */

+#define FLASH_SR_RDPERR                      FLASH_SR_RDPERR_Msk               /*!< Read protection error flag */

+#define FLASH_SR_RDSERR_Pos                  (24U)

+#define FLASH_SR_RDSERR_Msk                  (0x1UL << FLASH_SR_RDSERR_Pos)    /*!< 0x01000000 */

+#define FLASH_SR_RDSERR                      FLASH_SR_RDSERR_Msk               /*!< Secure error flag */

+#define FLASH_SR_SNECCERR_Pos                (25U)

+#define FLASH_SR_SNECCERR_Msk                (0x1UL << FLASH_SR_SNECCERR_Pos)  /*!< 0x02000000 */

+#define FLASH_SR_SNECCERR                    FLASH_SR_SNECCERR_Msk             /*!< Single correction error flag */

+#define FLASH_SR_DBECCERR_Pos                (26U)

+#define FLASH_SR_DBECCERR_Msk                (0x1UL << FLASH_SR_DBECCERR_Pos)  /*!< 0x04000000 */

+#define FLASH_SR_DBECCERR                    FLASH_SR_DBECCERR_Msk             /*!< ECC double detection error flag */

+#define FLASH_SR_CRCEND_Pos                  (27U)

+#define FLASH_SR_CRCEND_Msk                  (0x1UL << FLASH_SR_CRCEND_Pos)    /*!< 0x08000000 */

+#define FLASH_SR_CRCEND                      FLASH_SR_CRCEND_Msk               /*!< CRC end of calculation flag */

+#define FLASH_SR_CRCRDERR_Pos                (28U)

+#define FLASH_SR_CRCRDERR_Msk                (0x1UL << FLASH_SR_CRCRDERR_Pos)  /*!< 0x10000000 */

+#define FLASH_SR_CRCRDERR                    FLASH_SR_CRCRDERR_Msk             /*!< CRC read error flag */

+

+/*******************  Bits definition for FLASH_CCR register  *******************/

+#define FLASH_CCR_CLR_EOP_Pos                (16U)

+#define FLASH_CCR_CLR_EOP_Msk                (0x1UL << FLASH_CCR_CLR_EOP_Pos)  /*!< 0x00010000 */

+#define FLASH_CCR_CLR_EOP                    FLASH_CCR_CLR_EOP_Msk             /*!< EOP flag clear bit */

+#define FLASH_CCR_CLR_WRPERR_Pos             (17U)

+#define FLASH_CCR_CLR_WRPERR_Msk             (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */

+#define FLASH_CCR_CLR_WRPERR                 FLASH_CCR_CLR_WRPERR_Msk            /*!< WRPERR flag clear bit */

+#define FLASH_CCR_CLR_PGSERR_Pos             (18U)

+#define FLASH_CCR_CLR_PGSERR_Msk             (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */

+#define FLASH_CCR_CLR_PGSERR                 FLASH_CCR_CLR_PGSERR_Msk            /*!< PGSERR flag clear bit */

+#define FLASH_CCR_CLR_STRBERR_Pos            (19U)

+#define FLASH_CCR_CLR_STRBERR_Msk            (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */

+#define FLASH_CCR_CLR_STRBERR                FLASH_CCR_CLR_STRBERR_Msk            /*!< STRBERR flag clear bit */

+#define FLASH_CCR_CLR_INCERR_Pos             (21U)

+#define FLASH_CCR_CLR_INCERR_Msk             (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */

+#define FLASH_CCR_CLR_INCERR                 FLASH_CCR_CLR_INCERR_Msk            /*!< INCERR flag clear bit */

+#define FLASH_CCR_CLR_RDPERR_Pos             (23U)

+#define FLASH_CCR_CLR_RDPERR_Msk             (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */

+#define FLASH_CCR_CLR_RDPERR                 FLASH_CCR_CLR_RDPERR_Msk            /*!< RDPERR flag clear bit */

+#define FLASH_CCR_CLR_RDSERR_Pos             (24U)

+#define FLASH_CCR_CLR_RDSERR_Msk             (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */

+#define FLASH_CCR_CLR_RDSERR                 FLASH_CCR_CLR_RDSERR_Msk            /*!< RDSERR flag clear bit */

+#define FLASH_CCR_CLR_SNECCERR_Pos           (25U)

+#define FLASH_CCR_CLR_SNECCERR_Msk           (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */

+#define FLASH_CCR_CLR_SNECCERR               FLASH_CCR_CLR_SNECCERR_Msk            /*!< SNECCERR flag clear bit */

+#define FLASH_CCR_CLR_DBECCERR_Pos           (26U)

+#define FLASH_CCR_CLR_DBECCERR_Msk           (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */

+#define FLASH_CCR_CLR_DBECCERR               FLASH_CCR_CLR_DBECCERR_Msk            /*!< DBECCERR flag clear bit */

+#define FLASH_CCR_CLR_CRCEND_Pos             (27U)

+#define FLASH_CCR_CLR_CRCEND_Msk             (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */

+#define FLASH_CCR_CLR_CRCEND                 FLASH_CCR_CLR_CRCEND_Msk            /*!< CRCEND flag clear bit */

+#define FLASH_CCR_CLR_CRCRDERR_Pos           (28U)

+#define FLASH_CCR_CLR_CRCRDERR_Msk           (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */

+#define FLASH_CCR_CLR_CRCRDERR               FLASH_CCR_CLR_CRCRDERR_Msk            /*!< CRCRDERR flag clear bit */

+

+/*******************  Bits definition for FLASH_OPTCR register  *******************/

+#define FLASH_OPTCR_OPTLOCK_Pos              (0U)

+#define FLASH_OPTCR_OPTLOCK_Msk              (0x1UL << FLASH_OPTCR_OPTLOCK_Pos)  /*!< 0x00000001 */

+#define FLASH_OPTCR_OPTLOCK                  FLASH_OPTCR_OPTLOCK_Msk             /*!< FLASH_OPTCR lock option configuration bit */

+#define FLASH_OPTCR_OPTSTART_Pos             (1U)

+#define FLASH_OPTCR_OPTSTART_Msk             (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */

+#define FLASH_OPTCR_OPTSTART                 FLASH_OPTCR_OPTSTART_Msk            /*!< Option byte start change option configuration bit */

+#define FLASH_OPTCR_MER_Pos                  (4U)

+#define FLASH_OPTCR_MER_Msk                  (0x1UL << FLASH_OPTCR_MER_Pos)      /*!< 0x00000010 */

+#define FLASH_OPTCR_MER                      FLASH_OPTCR_MER_Msk                 /*!< Mass erase request */

+#define FLASH_OPTCR_PG_OTP_Pos               (5U)

+#define FLASH_OPTCR_PG_OTP_Msk               (0x1UL << FLASH_OPTCR_PG_OTP_Pos)   /*!< 0x00000020 */

+#define FLASH_OPTCR_PG_OTP                   FLASH_OPTCR_PG_OTP_Msk              /*!< OTP program control bit */

+#define FLASH_OPTCR_OPTCHANGEERRIE_Pos       (30U)

+#define FLASH_OPTCR_OPTCHANGEERRIE_Msk       (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */

+#define FLASH_OPTCR_OPTCHANGEERRIE           FLASH_OPTCR_OPTCHANGEERRIE_Msk            /*!< Option byte change error interrupt enable bit */

+#define FLASH_OPTCR_SWAP_BANK_Pos            (31U)

+#define FLASH_OPTCR_SWAP_BANK_Msk            (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */

+#define FLASH_OPTCR_SWAP_BANK                FLASH_OPTCR_SWAP_BANK_Msk            /*!< Bank swapping option configuration bit */

+

+/*******************  Bits definition for FLASH_OPTSR register  ***************/

+#define FLASH_OPTSR_OPT_BUSY_Pos             (0U)

+#define FLASH_OPTSR_OPT_BUSY_Msk             (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */

+#define FLASH_OPTSR_OPT_BUSY                 FLASH_OPTSR_OPT_BUSY_Msk            /*!< Option byte change ongoing flag */

+#define FLASH_OPTSR_BOR_LEV_Pos              (2U)

+#define FLASH_OPTSR_BOR_LEV_Msk              (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */

+#define FLASH_OPTSR_BOR_LEV                  FLASH_OPTSR_BOR_LEV_Msk            /*!< Brownout level option status bit */

+#define FLASH_OPTSR_BOR_LEV_0                (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */

+#define FLASH_OPTSR_BOR_LEV_1                (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */

+#define FLASH_OPTSR_IWDG1_SW_Pos             (4U)

+#define FLASH_OPTSR_IWDG1_SW_Msk             (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */

+#define FLASH_OPTSR_IWDG1_SW                 FLASH_OPTSR_IWDG1_SW_Msk            /*!< IWDG1 control mode option status bit */

+#define FLASH_OPTSR_NRST_STOP_D1_Pos         (6U)

+#define FLASH_OPTSR_NRST_STOP_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */

+#define FLASH_OPTSR_NRST_STOP_D1             FLASH_OPTSR_NRST_STOP_D1_Msk            /*!< D1 domain DStop entry reset option status bit */

+#define FLASH_OPTSR_NRST_STBY_D1_Pos         (7U)

+#define FLASH_OPTSR_NRST_STBY_D1_Msk         (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */

+#define FLASH_OPTSR_NRST_STBY_D1             FLASH_OPTSR_NRST_STBY_D1_Msk            /*!< D1 domain DStandby entry reset option status bit */

+#define FLASH_OPTSR_RDP_Pos                  (8U)

+#define FLASH_OPTSR_RDP_Msk                  (0xFFUL << FLASH_OPTSR_RDP_Pos)   /*!< 0x0000FF00 */

+#define FLASH_OPTSR_RDP                      FLASH_OPTSR_RDP_Msk               /*!< Readout protection level option status byte */

+#define FLASH_OPTSR_VDDMMC_HSLV_Pos          (16U)

+#define FLASH_OPTSR_VDDMMC_HSLV_Msk          (0x1UL << FLASH_OPTSR_VDDMMC_HSLV_Pos) /*!< 0x00010000 */

+#define FLASH_OPTSR_VDDMMC_HSLV              FLASH_OPTSR_VDDMMC_HSLV_Msk            /*!< VDDMMC I/O high-speed at low-voltage status bit (below 2.5V) */

+#define FLASH_OPTSR_FZ_IWDG_STOP_Pos         (17U)

+#define FLASH_OPTSR_FZ_IWDG_STOP_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */

+#define FLASH_OPTSR_FZ_IWDG_STOP             FLASH_OPTSR_FZ_IWDG_STOP_Msk            /*!< IWDG Stop mode freeze option status bit */

+#define FLASH_OPTSR_FZ_IWDG_SDBY_Pos         (18U)

+#define FLASH_OPTSR_FZ_IWDG_SDBY_Msk         (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */

+#define FLASH_OPTSR_FZ_IWDG_SDBY             FLASH_OPTSR_FZ_IWDG_SDBY_Msk            /*!< IWDG Standby mode freeze option status bit */

+#define FLASH_OPTSR_ST_RAM_SIZE_Pos          (19U)

+#define FLASH_OPTSR_ST_RAM_SIZE_Msk          (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */

+#define FLASH_OPTSR_ST_RAM_SIZE              FLASH_OPTSR_ST_RAM_SIZE_Msk            /*!< ST RAM size option status */

+#define FLASH_OPTSR_ST_RAM_SIZE_0            (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */

+#define FLASH_OPTSR_ST_RAM_SIZE_1            (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */

+#define FLASH_OPTSR_SECURITY_Pos             (21U)

+#define FLASH_OPTSR_SECURITY_Msk             (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */

+#define FLASH_OPTSR_SECURITY                 FLASH_OPTSR_SECURITY_Msk            /*!< Security enable option status bit */

+#define FLASH_OPTSR_IO_HSLV_Pos              (29U)

+#define FLASH_OPTSR_IO_HSLV_Msk              (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */

+#define FLASH_OPTSR_IO_HSLV                  FLASH_OPTSR_IO_HSLV_Msk            /*!< I/O high-speed at low-voltage status bit */

+#define FLASH_OPTSR_OPTCHANGEERR_Pos         (30U)

+#define FLASH_OPTSR_OPTCHANGEERR_Msk         (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */

+#define FLASH_OPTSR_OPTCHANGEERR             FLASH_OPTSR_OPTCHANGEERR_Msk            /*!< Option byte change error flag */

+#define FLASH_OPTSR_SWAP_BANK_OPT_Pos        (31U)

+#define FLASH_OPTSR_SWAP_BANK_OPT_Msk        (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */

+#define FLASH_OPTSR_SWAP_BANK_OPT            FLASH_OPTSR_SWAP_BANK_OPT_Msk            /*!< Bank swapping option status bit */

+

+/*******************  Bits definition for FLASH_OPTCCR register  *******************/

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos    (30U)

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk    (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */

+#define FLASH_OPTCCR_CLR_OPTCHANGEERR        FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk            /*!< OPTCHANGEERR reset bit */

+

+/*******************  Bits definition for FLASH_PRAR register  *********************/

+#define FLASH_PRAR_PROT_AREA_START_Pos       (0U)

+#define FLASH_PRAR_PROT_AREA_START_Msk       (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */

+#define FLASH_PRAR_PROT_AREA_START           FLASH_PRAR_PROT_AREA_START_Msk              /*!< PCROP area start status bits */

+#define FLASH_PRAR_PROT_AREA_END_Pos         (16U)

+#define FLASH_PRAR_PROT_AREA_END_Msk         (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */

+#define FLASH_PRAR_PROT_AREA_END             FLASH_PRAR_PROT_AREA_END_Msk              /*!< PCROP area end status bits */

+#define FLASH_PRAR_DMEP_Pos                  (31U)

+#define FLASH_PRAR_DMEP_Msk                  (0x1UL << FLASH_PRAR_DMEP_Pos)    /*!< 0x80000000 */

+#define FLASH_PRAR_DMEP                      FLASH_PRAR_DMEP_Msk               /*!< PCROP protected erase enable option status bit */

+

+/*******************  Bits definition for FLASH_SCAR register  *********************/

+#define FLASH_SCAR_SEC_AREA_START_Pos        (0U)

+#define FLASH_SCAR_SEC_AREA_START_Msk        (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */

+#define FLASH_SCAR_SEC_AREA_START            FLASH_SCAR_SEC_AREA_START_Msk              /*!< Secure-only area start status bits */

+#define FLASH_SCAR_SEC_AREA_END_Pos          (16U)

+#define FLASH_SCAR_SEC_AREA_END_Msk          (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */

+#define FLASH_SCAR_SEC_AREA_END              FLASH_SCAR_SEC_AREA_END_Msk              /*!< Secure-only area end status bits */

+#define FLASH_SCAR_DMES_Pos                  (31U)

+#define FLASH_SCAR_DMES_Msk                  (0x1UL << FLASH_SCAR_DMES_Pos)    /*!< 0x80000000 */

+#define FLASH_SCAR_DMES                      FLASH_SCAR_DMES_Msk               /*!< Secure access protected erase enable option status bit */

+

+/*******************  Bits definition for FLASH_WPSN register  *********************/

+#define FLASH_WPSN_WRPSN_Pos                 (0U)

+#define FLASH_WPSN_WRPSN_Msk                 (0xFFFFFFFFUL << FLASH_WPSN_WRPSN_Pos)  /*!< 0xFFFFFFFF */

+#define FLASH_WPSN_WRPSN                     FLASH_WPSN_WRPSN_Msk              /*!< Sector write protection option status byte */

+

+/*******************  Bits definition for FLASH_BOOT_CUR register  ****************/

+#define FLASH_BOOT_ADD0_Pos                  (0U)

+#define FLASH_BOOT_ADD0_Msk                  (0xFFFFUL << FLASH_BOOT_ADD0_Pos) /*!< 0x0000FFFF */

+#define FLASH_BOOT_ADD0                      FLASH_BOOT_ADD0_Msk               /*!< Arm Cortex-M7 boot address 0 */

+#define FLASH_BOOT_ADD1_Pos                  (16U)

+#define FLASH_BOOT_ADD1_Msk                  (0xFFFFUL << FLASH_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */

+#define FLASH_BOOT_ADD1                      FLASH_BOOT_ADD1_Msk               /*!< Arm Cortex-M7 boot address 1 */

+

+

+/*******************  Bits definition for FLASH_CRCCR register  ********************/

+#define FLASH_CRCCR_CRC_SECT_Pos             (0U)

+#define FLASH_CRCCR_CRC_SECT_Msk             (0x3FUL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x0000003F */

+#define FLASH_CRCCR_CRC_SECT                 FLASH_CRCCR_CRC_SECT_Msk             /*!< CRC sector number */

+#define FLASH_CRCCR_CRC_BY_SECT_Pos          (8U)

+#define FLASH_CRCCR_CRC_BY_SECT_Msk          (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */

+#define FLASH_CRCCR_CRC_BY_SECT              FLASH_CRCCR_CRC_BY_SECT_Msk            /*!< CRC sector mode select bit */

+#define FLASH_CRCCR_ADD_SECT_Pos             (9U)

+#define FLASH_CRCCR_ADD_SECT_Msk             (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */

+#define FLASH_CRCCR_ADD_SECT                 FLASH_CRCCR_ADD_SECT_Msk            /*!< CRC sector select bit */

+#define FLASH_CRCCR_CLEAN_SECT_Pos           (10U)

+#define FLASH_CRCCR_CLEAN_SECT_Msk           (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */

+#define FLASH_CRCCR_CLEAN_SECT               FLASH_CRCCR_CLEAN_SECT_Msk            /*!< CRC sector list clear bit */

+#define FLASH_CRCCR_START_CRC_Pos            (16U)

+#define FLASH_CRCCR_START_CRC_Msk            (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */

+#define FLASH_CRCCR_START_CRC                FLASH_CRCCR_START_CRC_Msk            /*!< CRC start bit */

+#define FLASH_CRCCR_CLEAN_CRC_Pos            (17U)

+#define FLASH_CRCCR_CLEAN_CRC_Msk            (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */

+#define FLASH_CRCCR_CLEAN_CRC                FLASH_CRCCR_CLEAN_CRC_Msk            /*!< CRC clear bit */

+#define FLASH_CRCCR_CRC_BURST_Pos            (20U)

+#define FLASH_CRCCR_CRC_BURST_Msk            (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */

+#define FLASH_CRCCR_CRC_BURST                FLASH_CRCCR_CRC_BURST_Msk            /*!< CRC burst size */

+#define FLASH_CRCCR_CRC_BURST_0              (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */

+#define FLASH_CRCCR_CRC_BURST_1              (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */

+#define FLASH_CRCCR_ALL_BANK_Pos             (22U)

+#define FLASH_CRCCR_ALL_BANK_Msk             (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */

+#define FLASH_CRCCR_ALL_BANK                 FLASH_CRCCR_ALL_BANK_Msk            /*!< CRC select bit */

+

+/*******************  Bits definition for FLASH_CRCSADD register  ****************/

+#define FLASH_CRCSADD_CRC_START_ADDR_Pos     (0U)

+#define FLASH_CRCSADD_CRC_START_ADDR_Msk     (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCSADD_CRC_START_ADDR         FLASH_CRCSADD_CRC_START_ADDR_Msk                   /*!< CRC start address */

+

+/*******************  Bits definition for FLASH_CRCEADD register  ****************/

+#define FLASH_CRCEADD_CRC_END_ADDR_Pos       (0U)

+#define FLASH_CRCEADD_CRC_END_ADDR_Msk       (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCEADD_CRC_END_ADDR           FLASH_CRCEADD_CRC_END_ADDR_Msk                   /*!< CRC end address */

+

+/*******************  Bits definition for FLASH_CRCDATA register  ***************/

+#define FLASH_CRCDATA_CRC_DATA_Pos           (0U)

+#define FLASH_CRCDATA_CRC_DATA_Msk           (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */

+#define FLASH_CRCDATA_CRC_DATA               FLASH_CRCDATA_CRC_DATA_Msk                   /*!< CRC result */

+

+/*******************  Bits definition for FLASH_ECC_FA register  *******************/

+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos       (0U)

+#define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk       (0xFFFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x0000FFFF */

+#define FLASH_ECC_FA_FAIL_ECC_ADDR           FLASH_ECC_FA_FAIL_ECC_ADDR_Msk               /*!< ECC error address */

+#define FLASH_ECC_FA_OTP_FAIL_ECC_Pos        (31U)

+#define FLASH_ECC_FA_OTP_FAIL_ECC_Msk        (0x1UL << FLASH_ECC_FA_OTP_FAIL_ECC_Pos) /*!< 0x80000000 */

+#define FLASH_ECC_FA_OTP_FAIL_ECC            FLASH_ECC_FA_OTP_FAIL_ECC_Msk            /*!< OTP ECC error bit */

+

+/*******************  Bits definition for FLASH_OTPBL register  *******************/

+#define FLASH_OTPBL_LOCKBL_Pos               (0U)

+#define FLASH_OTPBL_LOCKBL_Msk               (0xFFFFUL << FLASH_OTPBL_LOCKBL_Pos) /*!< 0x0000FFFF */

+#define FLASH_OTPBL_LOCKBL                   FLASH_OTPBL_LOCKBL_Msk               /*!< OTP Block Lock */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          Flexible Memory Controller                        */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for FMC_BCR1 register  *******************/

+#define FMC_BCR1_CCLKEN_Pos        (20U)

+#define FMC_BCR1_CCLKEN_Msk        (0x1UL << FMC_BCR1_CCLKEN_Pos)              /*!< 0x00100000 */

+#define FMC_BCR1_CCLKEN            FMC_BCR1_CCLKEN_Msk                         /*!<Continous clock enable     */

+#define FMC_BCR1_WFDIS_Pos         (21U)

+#define FMC_BCR1_WFDIS_Msk         (0x1UL << FMC_BCR1_WFDIS_Pos)               /*!< 0x00200000 */

+#define FMC_BCR1_WFDIS             FMC_BCR1_WFDIS_Msk                          /*!<Write FIFO Disable         */

+

+#define FMC_BCR1_BMAP_Pos          (24U)

+#define FMC_BCR1_BMAP_Msk          (0x3UL << FMC_BCR1_BMAP_Pos)                /*!< 0x03000000 */

+#define FMC_BCR1_BMAP              FMC_BCR1_BMAP_Msk                           /*!<BMAP[1:0] FMC bank mapping */

+#define FMC_BCR1_BMAP_0            (0x1UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x01000000 */

+#define FMC_BCR1_BMAP_1            (0x2UL << FMC_BCR1_BMAP_Pos)                 /*!< 0x02000000 */

+

+#define FMC_BCR1_FMCEN_Pos         (31U)

+#define FMC_BCR1_FMCEN_Msk         (0x1UL << FMC_BCR1_FMCEN_Pos)               /*!< 0x80000000 */

+#define FMC_BCR1_FMCEN             FMC_BCR1_FMCEN_Msk                          /*!<FMC controller Enable */

+/******************  Bit definition for FMC_BCRx registers (x=1..4)  *********/

+#define FMC_BCRx_MBKEN_Pos         (0U)

+#define FMC_BCRx_MBKEN_Msk         (0x1UL << FMC_BCRx_MBKEN_Pos)               /*!< 0x00000001 */

+#define FMC_BCRx_MBKEN             FMC_BCRx_MBKEN_Msk                          /*!<Memory bank enable bit                 */

+#define FMC_BCRx_MUXEN_Pos         (1U)

+#define FMC_BCRx_MUXEN_Msk         (0x1UL << FMC_BCRx_MUXEN_Pos)               /*!< 0x00000002 */

+#define FMC_BCRx_MUXEN             FMC_BCRx_MUXEN_Msk                          /*!<Address/data multiplexing enable bit   */

+

+#define FMC_BCRx_MTYP_Pos          (2U)

+#define FMC_BCRx_MTYP_Msk          (0x3UL << FMC_BCRx_MTYP_Pos)                /*!< 0x0000000C */

+#define FMC_BCRx_MTYP              FMC_BCRx_MTYP_Msk                           /*!<MTYP[1:0] bits (Memory type)           */

+#define FMC_BCRx_MTYP_0            (0x1UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000004 */

+#define FMC_BCRx_MTYP_1            (0x2UL << FMC_BCRx_MTYP_Pos)                 /*!< 0x00000008 */

+

+#define FMC_BCRx_MWID_Pos          (4U)

+#define FMC_BCRx_MWID_Msk          (0x3UL << FMC_BCRx_MWID_Pos)                /*!< 0x00000030 */

+#define FMC_BCRx_MWID              FMC_BCRx_MWID_Msk                           /*!<MWID[1:0] bits (Memory data bus width) */

+#define FMC_BCRx_MWID_0            (0x1UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000010 */

+#define FMC_BCRx_MWID_1            (0x2UL << FMC_BCRx_MWID_Pos)                 /*!< 0x00000020 */

+

+#define FMC_BCRx_FACCEN_Pos        (6U)

+#define FMC_BCRx_FACCEN_Msk        (0x1UL << FMC_BCRx_FACCEN_Pos)              /*!< 0x00000040 */

+#define FMC_BCRx_FACCEN            FMC_BCRx_FACCEN_Msk                         /*!<Flash access enable        */

+#define FMC_BCRx_BURSTEN_Pos       (8U)

+#define FMC_BCRx_BURSTEN_Msk       (0x1UL << FMC_BCRx_BURSTEN_Pos)             /*!< 0x00000100 */

+#define FMC_BCRx_BURSTEN           FMC_BCRx_BURSTEN_Msk                        /*!<Burst enable bit           */

+#define FMC_BCRx_WAITPOL_Pos       (9U)

+#define FMC_BCRx_WAITPOL_Msk       (0x1UL << FMC_BCRx_WAITPOL_Pos)             /*!< 0x00000200 */

+#define FMC_BCRx_WAITPOL           FMC_BCRx_WAITPOL_Msk                        /*!<Wait signal polarity bit   */

+#define FMC_BCRx_WAITCFG_Pos       (11U)

+#define FMC_BCRx_WAITCFG_Msk       (0x1UL << FMC_BCRx_WAITCFG_Pos)             /*!< 0x00000800 */

+#define FMC_BCRx_WAITCFG           FMC_BCRx_WAITCFG_Msk                        /*!<Wait timing configuration  */

+#define FMC_BCRx_WREN_Pos          (12U)

+#define FMC_BCRx_WREN_Msk          (0x1UL << FMC_BCRx_WREN_Pos)                /*!< 0x00001000 */

+#define FMC_BCRx_WREN              FMC_BCRx_WREN_Msk                           /*!<Write enable bit           */

+#define FMC_BCRx_WAITEN_Pos        (13U)

+#define FMC_BCRx_WAITEN_Msk        (0x1UL << FMC_BCRx_WAITEN_Pos)              /*!< 0x00002000 */

+#define FMC_BCRx_WAITEN            FMC_BCRx_WAITEN_Msk                         /*!<Wait enable bit            */

+#define FMC_BCRx_EXTMOD_Pos        (14U)

+#define FMC_BCRx_EXTMOD_Msk        (0x1UL << FMC_BCRx_EXTMOD_Pos)              /*!< 0x00004000 */

+#define FMC_BCRx_EXTMOD            FMC_BCRx_EXTMOD_Msk                         /*!<Extended mode enable       */

+#define FMC_BCRx_ASYNCWAIT_Pos     (15U)

+#define FMC_BCRx_ASYNCWAIT_Msk     (0x1UL << FMC_BCRx_ASYNCWAIT_Pos)           /*!< 0x00008000 */

+#define FMC_BCRx_ASYNCWAIT         FMC_BCRx_ASYNCWAIT_Msk                      /*!<Asynchronous wait          */

+

+#define FMC_BCRx_CPSIZE_Pos        (16U)

+#define FMC_BCRx_CPSIZE_Msk        (0x7UL << FMC_BCRx_CPSIZE_Pos)              /*!< 0x00070000 */

+#define FMC_BCRx_CPSIZE            FMC_BCRx_CPSIZE_Msk                         /*!<PSIZE[2:0] bits CRAM Page Size */

+#define FMC_BCRx_CPSIZE_0          (0x1UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00010000 */

+#define FMC_BCRx_CPSIZE_1          (0x2UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00020000 */

+#define FMC_BCRx_CPSIZE_2          (0x4UL << FMC_BCRx_CPSIZE_Pos)               /*!< 0x00040000 */

+

+#define FMC_BCRx_CBURSTRW_Pos      (19U)

+#define FMC_BCRx_CBURSTRW_Msk      (0x1UL << FMC_BCRx_CBURSTRW_Pos)            /*!< 0x00080000 */

+#define FMC_BCRx_CBURSTRW          FMC_BCRx_CBURSTRW_Msk                       /*!<Write burst enable         */

+

+/******************  Bit definition for FMC_BTRx registers (x=1..4)  *********/

+#define FMC_BTRx_ADDSET_Pos        (0U)

+#define FMC_BTRx_ADDSET_Msk        (0xFUL << FMC_BTRx_ADDSET_Pos)              /*!< 0x0000000F */

+#define FMC_BTRx_ADDSET            FMC_BTRx_ADDSET_Msk                         /*!<ADDSET[3:0] bits (Address setup phase duration) */

+#define FMC_BTRx_ADDSET_0          (0x1UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000001 */

+#define FMC_BTRx_ADDSET_1          (0x2UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000002 */

+#define FMC_BTRx_ADDSET_2          (0x4UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000004 */

+#define FMC_BTRx_ADDSET_3          (0x8UL << FMC_BTRx_ADDSET_Pos)               /*!< 0x00000008 */

+

+#define FMC_BTRx_ADDHLD_Pos        (4U)

+#define FMC_BTRx_ADDHLD_Msk        (0xFUL << FMC_BTRx_ADDHLD_Pos)              /*!< 0x000000F0 */

+#define FMC_BTRx_ADDHLD            FMC_BTRx_ADDHLD_Msk                         /*!<ADDHLD[3:0] bits (Address-hold phase duration)  */

+#define FMC_BTRx_ADDHLD_0          (0x1UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000010 */

+#define FMC_BTRx_ADDHLD_1          (0x2UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000020 */

+#define FMC_BTRx_ADDHLD_2          (0x4UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000040 */

+#define FMC_BTRx_ADDHLD_3          (0x8UL << FMC_BTRx_ADDHLD_Pos)               /*!< 0x00000080 */

+

+#define FMC_BTRx_DATAST_Pos        (8U)

+#define FMC_BTRx_DATAST_Msk        (0xFFUL << FMC_BTRx_DATAST_Pos)             /*!< 0x0000FF00 */

+#define FMC_BTRx_DATAST            FMC_BTRx_DATAST_Msk                         /*!<DATAST [3:0] bits (Data-phase duration) */

+#define FMC_BTRx_DATAST_0          (0x01UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000100 */

+#define FMC_BTRx_DATAST_1          (0x02UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000200 */

+#define FMC_BTRx_DATAST_2          (0x04UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000400 */

+#define FMC_BTRx_DATAST_3          (0x08UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00000800 */

+#define FMC_BTRx_DATAST_4          (0x10UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00001000 */

+#define FMC_BTRx_DATAST_5          (0x20UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00002000 */

+#define FMC_BTRx_DATAST_6          (0x40UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00004000 */

+#define FMC_BTRx_DATAST_7          (0x80UL << FMC_BTRx_DATAST_Pos)              /*!< 0x00008000 */

+

+#define FMC_BTRx_BUSTURN_Pos       (16U)

+#define FMC_BTRx_BUSTURN_Msk       (0xFUL << FMC_BTRx_BUSTURN_Pos)             /*!< 0x000F0000 */

+#define FMC_BTRx_BUSTURN           FMC_BTRx_BUSTURN_Msk                        /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */

+#define FMC_BTRx_BUSTURN_0         (0x1UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00010000 */

+#define FMC_BTRx_BUSTURN_1         (0x2UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00020000 */

+#define FMC_BTRx_BUSTURN_2         (0x4UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00040000 */

+#define FMC_BTRx_BUSTURN_3         (0x8UL << FMC_BTRx_BUSTURN_Pos)              /*!< 0x00080000 */

+

+#define FMC_BTRx_CLKDIV_Pos        (20U)

+#define FMC_BTRx_CLKDIV_Msk        (0xFUL << FMC_BTRx_CLKDIV_Pos)              /*!< 0x00F00000 */

+#define FMC_BTRx_CLKDIV            FMC_BTRx_CLKDIV_Msk                         /*!<CLKDIV[3:0] bits (Clock divide ratio) */

+#define FMC_BTRx_CLKDIV_0          (0x1UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00100000 */

+#define FMC_BTRx_CLKDIV_1          (0x2UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00200000 */

+#define FMC_BTRx_CLKDIV_2          (0x4UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00400000 */

+#define FMC_BTRx_CLKDIV_3          (0x8UL << FMC_BTRx_CLKDIV_Pos)               /*!< 0x00800000 */

+

+#define FMC_BTRx_DATLAT_Pos        (24U)

+#define FMC_BTRx_DATLAT_Msk        (0xFUL << FMC_BTRx_DATLAT_Pos)              /*!< 0x0F000000 */

+#define FMC_BTRx_DATLAT            FMC_BTRx_DATLAT_Msk                         /*!<DATLA[3:0] bits (Data latency) */

+#define FMC_BTRx_DATLAT_0          (0x1UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x01000000 */

+#define FMC_BTRx_DATLAT_1          (0x2UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x02000000 */

+#define FMC_BTRx_DATLAT_2          (0x4UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x04000000 */

+#define FMC_BTRx_DATLAT_3          (0x8UL << FMC_BTRx_DATLAT_Pos)               /*!< 0x08000000 */

+

+#define FMC_BTRx_ACCMOD_Pos        (28U)

+#define FMC_BTRx_ACCMOD_Msk        (0x3UL << FMC_BTRx_ACCMOD_Pos)              /*!< 0x30000000 */

+#define FMC_BTRx_ACCMOD            FMC_BTRx_ACCMOD_Msk                         /*!<ACCMOD[1:0] bits (Access mode) */

+#define FMC_BTRx_ACCMOD_0          (0x1UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x10000000 */

+#define FMC_BTRx_ACCMOD_1          (0x2UL << FMC_BTRx_ACCMOD_Pos)               /*!< 0x20000000 */

+

+/******************  Bit definition for FMC_BWTRx registers (x=1..4)  *********/

+#define FMC_BWTRx_ADDSET_Pos       (0U)

+#define FMC_BWTRx_ADDSET_Msk       (0xFUL << FMC_BWTRx_ADDSET_Pos)             /*!< 0x0000000F */

+#define FMC_BWTRx_ADDSET           FMC_BWTRx_ADDSET_Msk                        /*!<ADDSET[3:0] bits (Address setup phase duration) */

+#define FMC_BWTRx_ADDSET_0         (0x1UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000001 */

+#define FMC_BWTRx_ADDSET_1         (0x2UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000002 */

+#define FMC_BWTRx_ADDSET_2         (0x4UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000004 */

+#define FMC_BWTRx_ADDSET_3         (0x8UL << FMC_BWTRx_ADDSET_Pos)              /*!< 0x00000008 */

+

+#define FMC_BWTRx_ADDHLD_Pos       (4U)

+#define FMC_BWTRx_ADDHLD_Msk       (0xFUL << FMC_BWTRx_ADDHLD_Pos)             /*!< 0x000000F0 */

+#define FMC_BWTRx_ADDHLD           FMC_BWTRx_ADDHLD_Msk                        /*!<ADDHLD[3:0] bits (Address-hold phase duration) */

+#define FMC_BWTRx_ADDHLD_0         (0x1UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000010 */

+#define FMC_BWTRx_ADDHLD_1         (0x2UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000020 */

+#define FMC_BWTRx_ADDHLD_2         (0x4UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000040 */

+#define FMC_BWTRx_ADDHLD_3         (0x8UL << FMC_BWTRx_ADDHLD_Pos)              /*!< 0x00000080 */

+

+#define FMC_BWTRx_DATAST_Pos       (8U)

+#define FMC_BWTRx_DATAST_Msk       (0xFFUL << FMC_BWTRx_DATAST_Pos)            /*!< 0x0000FF00 */

+#define FMC_BWTRx_DATAST           FMC_BWTRx_DATAST_Msk                        /*!<DATAST [3:0] bits (Data-phase duration) */

+#define FMC_BWTRx_DATAST_0         (0x01UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000100 */

+#define FMC_BWTRx_DATAST_1         (0x02UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000200 */

+#define FMC_BWTRx_DATAST_2         (0x04UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000400 */

+#define FMC_BWTRx_DATAST_3         (0x08UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00000800 */

+#define FMC_BWTRx_DATAST_4         (0x10UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00001000 */

+#define FMC_BWTRx_DATAST_5         (0x20UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00002000 */

+#define FMC_BWTRx_DATAST_6         (0x40UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00004000 */

+#define FMC_BWTRx_DATAST_7         (0x80UL << FMC_BWTRx_DATAST_Pos)             /*!< 0x00008000 */

+

+#define FMC_BWTRx_BUSTURN_Pos      (16U)

+#define FMC_BWTRx_BUSTURN_Msk      (0xFUL << FMC_BWTRx_BUSTURN_Pos)            /*!< 0x000F0000 */

+#define FMC_BWTRx_BUSTURN          FMC_BWTRx_BUSTURN_Msk                       /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */

+#define FMC_BWTRx_BUSTURN_0        (0x1UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00010000 */

+#define FMC_BWTRx_BUSTURN_1        (0x2UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00020000 */

+#define FMC_BWTRx_BUSTURN_2        (0x4UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00040000 */

+#define FMC_BWTRx_BUSTURN_3        (0x8UL << FMC_BWTRx_BUSTURN_Pos)             /*!< 0x00080000 */

+

+#define FMC_BWTRx_ACCMOD_Pos       (28U)

+#define FMC_BWTRx_ACCMOD_Msk       (0x3UL << FMC_BWTRx_ACCMOD_Pos)             /*!< 0x30000000 */

+#define FMC_BWTRx_ACCMOD           FMC_BWTRx_ACCMOD_Msk                        /*!<ACCMOD[1:0] bits (Access mode) */

+#define FMC_BWTRx_ACCMOD_0         (0x1UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x10000000 */

+#define FMC_BWTRx_ACCMOD_1         (0x2UL << FMC_BWTRx_ACCMOD_Pos)              /*!< 0x20000000 */

+

+/******************  Bit definition for FMC_PCR register  *******************/

+#define FMC_PCR_PWAITEN_Pos        (1U)

+#define FMC_PCR_PWAITEN_Msk        (0x1UL << FMC_PCR_PWAITEN_Pos)              /*!< 0x00000002 */

+#define FMC_PCR_PWAITEN            FMC_PCR_PWAITEN_Msk                         /*!<Wait feature enable bit                   */

+#define FMC_PCR_PBKEN_Pos          (2U)

+#define FMC_PCR_PBKEN_Msk          (0x1UL << FMC_PCR_PBKEN_Pos)                /*!< 0x00000004 */

+#define FMC_PCR_PBKEN              FMC_PCR_PBKEN_Msk                           /*!<NAND Flash memory bank enable bit */

+

+#define FMC_PCR_PWID_Pos           (4U)

+#define FMC_PCR_PWID_Msk           (0x3UL << FMC_PCR_PWID_Pos)                 /*!< 0x00000030 */

+#define FMC_PCR_PWID               FMC_PCR_PWID_Msk                            /*!<PWID[1:0] bits (NAND Flash databus width) */

+#define FMC_PCR_PWID_0             (0x1UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000010 */

+#define FMC_PCR_PWID_1             (0x2UL << FMC_PCR_PWID_Pos)                  /*!< 0x00000020 */

+

+#define FMC_PCR_ECCEN_Pos          (6U)

+#define FMC_PCR_ECCEN_Msk          (0x1UL << FMC_PCR_ECCEN_Pos)                /*!< 0x00000040 */

+#define FMC_PCR_ECCEN              FMC_PCR_ECCEN_Msk                           /*!<ECC computation logic enable bit          */

+

+#define FMC_PCR_TCLR_Pos           (9U)

+#define FMC_PCR_TCLR_Msk           (0xFUL << FMC_PCR_TCLR_Pos)                 /*!< 0x00001E00 */

+#define FMC_PCR_TCLR               FMC_PCR_TCLR_Msk                            /*!<TCLR[3:0] bits (CLE to RE delay)          */

+#define FMC_PCR_TCLR_0             (0x1UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000200 */

+#define FMC_PCR_TCLR_1             (0x2UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000400 */

+#define FMC_PCR_TCLR_2             (0x4UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00000800 */

+#define FMC_PCR_TCLR_3             (0x8UL << FMC_PCR_TCLR_Pos)                  /*!< 0x00001000 */

+

+#define FMC_PCR_TAR_Pos            (13U)

+#define FMC_PCR_TAR_Msk            (0xFUL << FMC_PCR_TAR_Pos)                  /*!< 0x0001E000 */

+#define FMC_PCR_TAR                FMC_PCR_TAR_Msk                             /*!<TAR[3:0] bits (ALE to RE delay)           */

+#define FMC_PCR_TAR_0              (0x1UL << FMC_PCR_TAR_Pos)                   /*!< 0x00002000 */

+#define FMC_PCR_TAR_1              (0x2UL << FMC_PCR_TAR_Pos)                   /*!< 0x00004000 */

+#define FMC_PCR_TAR_2              (0x4UL << FMC_PCR_TAR_Pos)                   /*!< 0x00008000 */

+#define FMC_PCR_TAR_3              (0x8UL << FMC_PCR_TAR_Pos)                   /*!< 0x00010000 */

+

+#define FMC_PCR_ECCPS_Pos          (17U)

+#define FMC_PCR_ECCPS_Msk          (0x7UL << FMC_PCR_ECCPS_Pos)                /*!< 0x000E0000 */

+#define FMC_PCR_ECCPS              FMC_PCR_ECCPS_Msk                           /*!<ECCPS[1:0] bits (ECC page size)           */

+#define FMC_PCR_ECCPS_0            (0x1UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00020000 */

+#define FMC_PCR_ECCPS_1            (0x2UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00040000 */

+#define FMC_PCR_ECCPS_2            (0x4UL << FMC_PCR_ECCPS_Pos)                 /*!< 0x00080000 */

+

+/*******************  Bit definition for FMC_SR register  *******************/

+#define FMC_SR_IRS_Pos             (0U)

+#define FMC_SR_IRS_Msk             (0x1UL << FMC_SR_IRS_Pos)                   /*!< 0x00000001 */

+#define FMC_SR_IRS                 FMC_SR_IRS_Msk                              /*!<Interrupt Rising Edge status                */

+#define FMC_SR_ILS_Pos             (1U)

+#define FMC_SR_ILS_Msk             (0x1UL << FMC_SR_ILS_Pos)                   /*!< 0x00000002 */

+#define FMC_SR_ILS                 FMC_SR_ILS_Msk                              /*!<Interrupt Level status                      */

+#define FMC_SR_IFS_Pos             (2U)

+#define FMC_SR_IFS_Msk             (0x1UL << FMC_SR_IFS_Pos)                   /*!< 0x00000004 */

+#define FMC_SR_IFS                 FMC_SR_IFS_Msk                              /*!<Interrupt Falling Edge status               */

+#define FMC_SR_IREN_Pos            (3U)

+#define FMC_SR_IREN_Msk            (0x1UL << FMC_SR_IREN_Pos)                  /*!< 0x00000008 */

+#define FMC_SR_IREN                FMC_SR_IREN_Msk                             /*!<Interrupt Rising Edge detection Enable bit  */

+#define FMC_SR_ILEN_Pos            (4U)

+#define FMC_SR_ILEN_Msk            (0x1UL << FMC_SR_ILEN_Pos)                  /*!< 0x00000010 */

+#define FMC_SR_ILEN                FMC_SR_ILEN_Msk                             /*!<Interrupt Level detection Enable bit        */

+#define FMC_SR_IFEN_Pos            (5U)

+#define FMC_SR_IFEN_Msk            (0x1UL << FMC_SR_IFEN_Pos)                  /*!< 0x00000020 */

+#define FMC_SR_IFEN                FMC_SR_IFEN_Msk                             /*!<Interrupt Falling Edge detection Enable bit */

+#define FMC_SR_FEMPT_Pos           (6U)

+#define FMC_SR_FEMPT_Msk           (0x1UL << FMC_SR_FEMPT_Pos)                 /*!< 0x00000040 */

+#define FMC_SR_FEMPT               FMC_SR_FEMPT_Msk                            /*!<FIFO empty                                  */

+

+/******************  Bit definition for FMC_PMEM register  ******************/

+#define FMC_PMEM_MEMSET_Pos       (0U)

+#define FMC_PMEM_MEMSET_Msk       (0xFFUL << FMC_PMEM_MEMSET_Pos)            /*!< 0x000000FF */

+#define FMC_PMEM_MEMSET           FMC_PMEM_MEMSET_Msk                        /*!<MEMSET[7:0] bits (Common memory setup time) */

+#define FMC_PMEM_MEMSET_0         (0x01UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000001 */

+#define FMC_PMEM_MEMSET_1         (0x02UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000002 */

+#define FMC_PMEM_MEMSET_2         (0x04UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000004 */

+#define FMC_PMEM_MEMSET_3         (0x08UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000008 */

+#define FMC_PMEM_MEMSET_4         (0x10UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000010 */

+#define FMC_PMEM_MEMSET_5         (0x20UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000020 */

+#define FMC_PMEM_MEMSET_6         (0x40UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000040 */

+#define FMC_PMEM_MEMSET_7         (0x80UL << FMC_PMEM_MEMSET_Pos)             /*!< 0x00000080 */

+

+#define FMC_PMEM_MEMWAIT_Pos      (8U)

+#define FMC_PMEM_MEMWAIT_Msk      (0xFFUL << FMC_PMEM_MEMWAIT_Pos)           /*!< 0x0000FF00 */

+#define FMC_PMEM_MEMWAIT          FMC_PMEM_MEMWAIT_Msk                       /*!<MEMWAIT[7:0] bits (Common memory wait time) */

+#define FMC_PMEM_MEMWAIT_0        (0x01UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000100 */

+#define FMC_PMEM_MEMWAIT_1        (0x02UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000200 */

+#define FMC_PMEM_MEMWAIT_2        (0x04UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000400 */

+#define FMC_PMEM_MEMWAIT_3        (0x08UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00000800 */

+#define FMC_PMEM_MEMWAIT_4        (0x10UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00001000 */

+#define FMC_PMEM_MEMWAIT_5        (0x20UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00002000 */

+#define FMC_PMEM_MEMWAIT_6        (0x40UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00004000 */

+#define FMC_PMEM_MEMWAIT_7        (0x80UL << FMC_PMEM_MEMWAIT_Pos)            /*!< 0x00008000 */

+

+#define FMC_PMEM_MEMHOLD_Pos      (16U)

+#define FMC_PMEM_MEMHOLD_Msk      (0xFFUL << FMC_PMEM_MEMHOLD_Pos)           /*!< 0x00FF0000 */

+#define FMC_PMEM_MEMHOLD          FMC_PMEM_MEMHOLD_Msk                       /*!<MEMHOLD[7:0] bits (Common memory hold time) */

+#define FMC_PMEM_MEMHOLD_0        (0x01UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00010000 */

+#define FMC_PMEM_MEMHOLD_1        (0x02UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00020000 */

+#define FMC_PMEM_MEMHOLD_2        (0x04UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00040000 */

+#define FMC_PMEM_MEMHOLD_3        (0x08UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00080000 */

+#define FMC_PMEM_MEMHOLD_4        (0x10UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00100000 */

+#define FMC_PMEM_MEMHOLD_5        (0x20UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00200000 */

+#define FMC_PMEM_MEMHOLD_6        (0x40UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00400000 */

+#define FMC_PMEM_MEMHOLD_7        (0x80UL << FMC_PMEM_MEMHOLD_Pos)            /*!< 0x00800000 */

+

+#define FMC_PMEM_MEMHIZ_Pos       (24U)

+#define FMC_PMEM_MEMHIZ_Msk       (0xFFUL << FMC_PMEM_MEMHIZ_Pos)            /*!< 0xFF000000 */

+#define FMC_PMEM_MEMHIZ           FMC_PMEM_MEMHIZ_Msk                        /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */

+#define FMC_PMEM_MEMHIZ_0         (0x01UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x01000000 */

+#define FMC_PMEM_MEMHIZ_1         (0x02UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x02000000 */

+#define FMC_PMEM_MEMHIZ_2         (0x04UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x04000000 */

+#define FMC_PMEM_MEMHIZ_3         (0x08UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x08000000 */

+#define FMC_PMEM_MEMHIZ_4         (0x10UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x10000000 */

+#define FMC_PMEM_MEMHIZ_5         (0x20UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x20000000 */

+#define FMC_PMEM_MEMHIZ_6         (0x40UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x40000000 */

+#define FMC_PMEM_MEMHIZ_7         (0x80UL << FMC_PMEM_MEMHIZ_Pos)             /*!< 0x80000000 */

+

+/******************  Bit definition for FMC_PATT register  ******************/

+#define FMC_PATT_ATTSET_Pos       (0U)

+#define FMC_PATT_ATTSET_Msk       (0xFFUL << FMC_PATT_ATTSET_Pos)            /*!< 0x000000FF */

+#define FMC_PATT_ATTSET           FMC_PATT_ATTSET_Msk                        /*!<ATTSET[7:0] bits (Attribute memory setup time) */

+#define FMC_PATT_ATTSET_0         (0x01UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000001 */

+#define FMC_PATT_ATTSET_1         (0x02UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000002 */

+#define FMC_PATT_ATTSET_2         (0x04UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000004 */

+#define FMC_PATT_ATTSET_3         (0x08UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000008 */

+#define FMC_PATT_ATTSET_4         (0x10UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000010 */

+#define FMC_PATT_ATTSET_5         (0x20UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000020 */

+#define FMC_PATT_ATTSET_6         (0x40UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000040 */

+#define FMC_PATT_ATTSET_7         (0x80UL << FMC_PATT_ATTSET_Pos)             /*!< 0x00000080 */

+

+#define FMC_PATT_ATTWAIT_Pos      (8U)

+#define FMC_PATT_ATTWAIT_Msk      (0xFFUL << FMC_PATT_ATTWAIT_Pos)           /*!< 0x0000FF00 */

+#define FMC_PATT_ATTWAIT          FMC_PATT_ATTWAIT_Msk                       /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */

+#define FMC_PATT_ATTWAIT_0        (0x01UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000100 */

+#define FMC_PATT_ATTWAIT_1        (0x02UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000200 */

+#define FMC_PATT_ATTWAIT_2        (0x04UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000400 */

+#define FMC_PATT_ATTWAIT_3        (0x08UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00000800 */

+#define FMC_PATT_ATTWAIT_4        (0x10UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00001000 */

+#define FMC_PATT_ATTWAIT_5        (0x20UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00002000 */

+#define FMC_PATT_ATTWAIT_6        (0x40UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00004000 */

+#define FMC_PATT_ATTWAIT_7        (0x80UL << FMC_PATT_ATTWAIT_Pos)            /*!< 0x00008000 */

+

+#define FMC_PATT_ATTHOLD_Pos      (16U)

+#define FMC_PATT_ATTHOLD_Msk      (0xFFUL << FMC_PATT_ATTHOLD_Pos)           /*!< 0x00FF0000 */

+#define FMC_PATT_ATTHOLD          FMC_PATT_ATTHOLD_Msk                       /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */

+#define FMC_PATT_ATTHOLD_0        (0x01UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00010000 */

+#define FMC_PATT_ATTHOLD_1        (0x02UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00020000 */

+#define FMC_PATT_ATTHOLD_2        (0x04UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00040000 */

+#define FMC_PATT_ATTHOLD_3        (0x08UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00080000 */

+#define FMC_PATT_ATTHOLD_4        (0x10UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00100000 */

+#define FMC_PATT_ATTHOLD_5        (0x20UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00200000 */

+#define FMC_PATT_ATTHOLD_6        (0x40UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00400000 */

+#define FMC_PATT_ATTHOLD_7        (0x80UL << FMC_PATT_ATTHOLD_Pos)            /*!< 0x00800000 */

+

+#define FMC_PATT_ATTHIZ_Pos       (24U)

+#define FMC_PATT_ATTHIZ_Msk       (0xFFUL << FMC_PATT_ATTHIZ_Pos)            /*!< 0xFF000000 */

+#define FMC_PATT_ATTHIZ           FMC_PATT_ATTHIZ_Msk                        /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */

+#define FMC_PATT_ATTHIZ_0         (0x01UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x01000000 */

+#define FMC_PATT_ATTHIZ_1         (0x02UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x02000000 */

+#define FMC_PATT_ATTHIZ_2         (0x04UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x04000000 */

+#define FMC_PATT_ATTHIZ_3         (0x08UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x08000000 */

+#define FMC_PATT_ATTHIZ_4         (0x10UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x10000000 */

+#define FMC_PATT_ATTHIZ_5         (0x20UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x20000000 */

+#define FMC_PATT_ATTHIZ_6         (0x40UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x40000000 */

+#define FMC_PATT_ATTHIZ_7         (0x80UL << FMC_PATT_ATTHIZ_Pos)             /*!< 0x80000000 */

+

+/******************  Bit definition for FMC_ECCR3 register  ******************/

+#define FMC_ECCR3_ECC3_Pos         (0U)

+#define FMC_ECCR3_ECC3_Msk         (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos)        /*!< 0xFFFFFFFF */

+#define FMC_ECCR3_ECC3             FMC_ECCR3_ECC3_Msk                          /*!<ECC result */

+

+/******************  Bit definition for FMC_SDCRx registers (x=1..4)  *********/

+#define FMC_SDCRx_NC_Pos           (0U)

+#define FMC_SDCRx_NC_Msk           (0x3UL << FMC_SDCRx_NC_Pos)                 /*!< 0x00000003 */

+#define FMC_SDCRx_NC               FMC_SDCRx_NC_Msk                            /*!<NC[1:0] bits (Number of column bits) */

+#define FMC_SDCRx_NC_0             (0x1UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000001 */

+#define FMC_SDCRx_NC_1             (0x2UL << FMC_SDCRx_NC_Pos)                  /*!< 0x00000002 */

+

+#define FMC_SDCRx_NR_Pos           (2U)

+#define FMC_SDCRx_NR_Msk           (0x3UL << FMC_SDCRx_NR_Pos)                 /*!< 0x0000000C */

+#define FMC_SDCRx_NR               FMC_SDCRx_NR_Msk                            /*!<NR[1:0] bits (Number of row bits) */

+#define FMC_SDCRx_NR_0             (0x1UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000004 */

+#define FMC_SDCRx_NR_1             (0x2UL << FMC_SDCRx_NR_Pos)                  /*!< 0x00000008 */

+

+#define FMC_SDCRx_MWID_Pos         (4U)

+#define FMC_SDCRx_MWID_Msk         (0x3UL << FMC_SDCRx_MWID_Pos)               /*!< 0x00000030 */

+#define FMC_SDCRx_MWID             FMC_SDCRx_MWID_Msk                          /*!<NR[1:0] bits (Number of row bits) */

+#define FMC_SDCRx_MWID_0           (0x1UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000010 */

+#define FMC_SDCRx_MWID_1           (0x2UL << FMC_SDCRx_MWID_Pos)                /*!< 0x00000020 */

+

+#define FMC_SDCRx_NB_Pos           (6U)

+#define FMC_SDCRx_NB_Msk           (0x1UL << FMC_SDCRx_NB_Pos)                 /*!< 0x00000040 */

+#define FMC_SDCRx_NB               FMC_SDCRx_NB_Msk                            /*!<Number of internal bank */

+

+#define FMC_SDCRx_CAS_Pos          (7U)

+#define FMC_SDCRx_CAS_Msk          (0x3UL << FMC_SDCRx_CAS_Pos)                /*!< 0x00000180 */

+#define FMC_SDCRx_CAS              FMC_SDCRx_CAS_Msk                           /*!<CAS[1:0] bits (CAS latency) */

+#define FMC_SDCRx_CAS_0            (0x1UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000080 */

+#define FMC_SDCRx_CAS_1            (0x2UL << FMC_SDCRx_CAS_Pos)                 /*!< 0x00000100 */

+

+#define FMC_SDCRx_WP_Pos           (9U)

+#define FMC_SDCRx_WP_Msk           (0x1UL << FMC_SDCRx_WP_Pos)                 /*!< 0x00000200 */

+#define FMC_SDCRx_WP               FMC_SDCRx_WP_Msk                            /*!<Write protection */

+

+#define FMC_SDCRx_SDCLK_Pos        (10U)

+#define FMC_SDCRx_SDCLK_Msk        (0x3UL << FMC_SDCRx_SDCLK_Pos)              /*!< 0x00000C00 */

+#define FMC_SDCRx_SDCLK            FMC_SDCRx_SDCLK_Msk                         /*!<SDRAM clock configuration */

+#define FMC_SDCRx_SDCLK_0          (0x1UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000400 */

+#define FMC_SDCRx_SDCLK_1          (0x2UL << FMC_SDCRx_SDCLK_Pos)               /*!< 0x00000800 */

+

+#define FMC_SDCRx_RBURST_Pos       (12U)

+#define FMC_SDCRx_RBURST_Msk       (0x1UL << FMC_SDCRx_RBURST_Pos)             /*!< 0x00001000 */

+#define FMC_SDCRx_RBURST           FMC_SDCRx_RBURST_Msk                        /*!<Read burst */

+

+#define FMC_SDCRx_RPIPE_Pos        (13U)

+#define FMC_SDCRx_RPIPE_Msk        (0x3UL << FMC_SDCRx_RPIPE_Pos)              /*!< 0x00006000 */

+#define FMC_SDCRx_RPIPE            FMC_SDCRx_RPIPE_Msk                         /*!<Write protection */

+#define FMC_SDCRx_RPIPE_0          (0x1UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00002000 */

+#define FMC_SDCRx_RPIPE_1          (0x2UL << FMC_SDCRx_RPIPE_Pos)               /*!< 0x00004000 */

+

+/******************  Bit definition for FMC_SDTRx(1,2) register  ******************/

+#define FMC_SDTRx_TMRD_Pos         (0U)

+#define FMC_SDTRx_TMRD_Msk         (0xFUL << FMC_SDTRx_TMRD_Pos)               /*!< 0x0000000F */

+#define FMC_SDTRx_TMRD             FMC_SDTRx_TMRD_Msk                          /*!<TMRD[3:0] bits (Load mode register to active) */

+#define FMC_SDTRx_TMRD_0           (0x1UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000001 */

+#define FMC_SDTRx_TMRD_1           (0x2UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000002 */

+#define FMC_SDTRx_TMRD_2           (0x4UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000004 */

+#define FMC_SDTRx_TMRD_3           (0x8UL << FMC_SDTRx_TMRD_Pos)                /*!< 0x00000008 */

+

+#define FMC_SDTRx_TXSR_Pos         (4U)

+#define FMC_SDTRx_TXSR_Msk         (0xFUL << FMC_SDTRx_TXSR_Pos)               /*!< 0x000000F0 */

+#define FMC_SDTRx_TXSR             FMC_SDTRx_TXSR_Msk                          /*!<TXSR[3:0] bits (Exit self refresh) */

+#define FMC_SDTRx_TXSR_0           (0x1UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000010 */

+#define FMC_SDTRx_TXSR_1           (0x2UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000020 */

+#define FMC_SDTRx_TXSR_2           (0x4UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000040 */

+#define FMC_SDTRx_TXSR_3           (0x8UL << FMC_SDTRx_TXSR_Pos)                /*!< 0x00000080 */

+

+#define FMC_SDTRx_TRAS_Pos         (8U)

+#define FMC_SDTRx_TRAS_Msk         (0xFUL << FMC_SDTRx_TRAS_Pos)               /*!< 0x00000F00 */

+#define FMC_SDTRx_TRAS             FMC_SDTRx_TRAS_Msk                          /*!<TRAS[3:0] bits (Self refresh time) */

+#define FMC_SDTRx_TRAS_0           (0x1UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000100 */

+#define FMC_SDTRx_TRAS_1           (0x2UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000200 */

+#define FMC_SDTRx_TRAS_2           (0x4UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000400 */

+#define FMC_SDTRx_TRAS_3           (0x8UL << FMC_SDTRx_TRAS_Pos)                /*!< 0x00000800 */

+

+#define FMC_SDTRx_TRC_Pos          (12U)

+#define FMC_SDTRx_TRC_Msk          (0xFUL << FMC_SDTRx_TRC_Pos)                /*!< 0x0000F000 */

+#define FMC_SDTRx_TRC              FMC_SDTRx_TRC_Msk                           /*!<TRC[2:0] bits (Row cycle delay) */

+#define FMC_SDTRx_TRC_0            (0x1UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00001000 */

+#define FMC_SDTRx_TRC_1            (0x2UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00002000 */

+#define FMC_SDTRx_TRC_2            (0x4UL << FMC_SDTRx_TRC_Pos)                 /*!< 0x00004000 */

+

+#define FMC_SDTRx_TWR_Pos          (16U)

+#define FMC_SDTRx_TWR_Msk          (0xFUL << FMC_SDTRx_TWR_Pos)                /*!< 0x000F0000 */

+#define FMC_SDTRx_TWR              FMC_SDTRx_TWR_Msk                           /*!<TRC[2:0] bits (Write recovery delay) */

+#define FMC_SDTRx_TWR_0            (0x1UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00010000 */

+#define FMC_SDTRx_TWR_1            (0x2UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00020000 */

+#define FMC_SDTRx_TWR_2            (0x4UL << FMC_SDTRx_TWR_Pos)                 /*!< 0x00040000 */

+

+#define FMC_SDTRx_TRP_Pos          (20U)

+#define FMC_SDTRx_TRP_Msk          (0xFUL << FMC_SDTRx_TRP_Pos)                /*!< 0x00F00000 */

+#define FMC_SDTRx_TRP              FMC_SDTRx_TRP_Msk                           /*!<TRP[2:0] bits (Row precharge delay) */

+#define FMC_SDTRx_TRP_0            (0x1UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00100000 */

+#define FMC_SDTRx_TRP_1            (0x2UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00200000 */

+#define FMC_SDTRx_TRP_2            (0x4UL << FMC_SDTRx_TRP_Pos)                 /*!< 0x00400000 */

+

+#define FMC_SDTRx_TRCD_Pos         (24U)

+#define FMC_SDTRx_TRCD_Msk         (0xFUL << FMC_SDTRx_TRCD_Pos)               /*!< 0x0F000000 */

+#define FMC_SDTRx_TRCD             FMC_SDTRx_TRCD_Msk                          /*!<TRP[2:0] bits (Row to column delay) */

+#define FMC_SDTRx_TRCD_0           (0x1UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x01000000 */

+#define FMC_SDTRx_TRCD_1           (0x2UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x02000000 */

+#define FMC_SDTRx_TRCD_2           (0x4UL << FMC_SDTRx_TRCD_Pos)                /*!< 0x04000000 */

+

+/******************  Bit definition for FMC_SDCMR register  ******************/

+#define FMC_SDCMR_MODE_Pos         (0U)

+#define FMC_SDCMR_MODE_Msk         (0x7UL << FMC_SDCMR_MODE_Pos)               /*!< 0x00000007 */

+#define FMC_SDCMR_MODE             FMC_SDCMR_MODE_Msk                          /*!<MODE[2:0] bits (Command mode) */

+#define FMC_SDCMR_MODE_0           (0x1UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000001 */

+#define FMC_SDCMR_MODE_1           (0x2UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000002 */

+#define FMC_SDCMR_MODE_2           (0x3UL << FMC_SDCMR_MODE_Pos)                /*!< 0x00000003 */

+

+#define FMC_SDCMR_CTB2_Pos         (3U)

+#define FMC_SDCMR_CTB2_Msk         (0x1UL << FMC_SDCMR_CTB2_Pos)               /*!< 0x00000008 */

+#define FMC_SDCMR_CTB2             FMC_SDCMR_CTB2_Msk                          /*!<Command target 2 */

+

+#define FMC_SDCMR_CTB1_Pos         (4U)

+#define FMC_SDCMR_CTB1_Msk         (0x1UL << FMC_SDCMR_CTB1_Pos)               /*!< 0x00000010 */

+#define FMC_SDCMR_CTB1             FMC_SDCMR_CTB1_Msk                          /*!<Command target 1 */

+

+#define FMC_SDCMR_NRFS_Pos         (5U)

+#define FMC_SDCMR_NRFS_Msk         (0xFUL << FMC_SDCMR_NRFS_Pos)               /*!< 0x000001E0 */

+#define FMC_SDCMR_NRFS             FMC_SDCMR_NRFS_Msk                          /*!<NRFS[3:0] bits (Number of auto-refresh) */

+#define FMC_SDCMR_NRFS_0           (0x1UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000020 */

+#define FMC_SDCMR_NRFS_1           (0x2UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000040 */

+#define FMC_SDCMR_NRFS_2           (0x4UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000080 */

+#define FMC_SDCMR_NRFS_3           (0x8UL << FMC_SDCMR_NRFS_Pos)                /*!< 0x00000100 */

+

+#define FMC_SDCMR_MRD_Pos          (9U)

+#define FMC_SDCMR_MRD_Msk          (0x1FFFUL << FMC_SDCMR_MRD_Pos)             /*!< 0x003FFE00 */

+#define FMC_SDCMR_MRD              FMC_SDCMR_MRD_Msk                           /*!<MRD[12:0] bits (Mode register definition) */

+

+/******************  Bit definition for FMC_SDRTR register  ******************/

+#define FMC_SDRTR_CRE_Pos          (0U)

+#define FMC_SDRTR_CRE_Msk          (0x1UL << FMC_SDRTR_CRE_Pos)                /*!< 0x00000001 */

+#define FMC_SDRTR_CRE              FMC_SDRTR_CRE_Msk                           /*!<Clear refresh error flag */

+

+#define FMC_SDRTR_COUNT_Pos        (1U)

+#define FMC_SDRTR_COUNT_Msk        (0x1FFFUL << FMC_SDRTR_COUNT_Pos)           /*!< 0x00003FFE */

+#define FMC_SDRTR_COUNT            FMC_SDRTR_COUNT_Msk                         /*!<COUNT[12:0] bits (Refresh timer count) */

+

+#define FMC_SDRTR_REIE_Pos         (14U)

+#define FMC_SDRTR_REIE_Msk         (0x1UL << FMC_SDRTR_REIE_Pos)               /*!< 0x00004000 */

+#define FMC_SDRTR_REIE             FMC_SDRTR_REIE_Msk                          /*!<RES interupt enable */

+

+/******************  Bit definition for FMC_SDSR register  ******************/

+#define FMC_SDSR_RE_Pos            (0U)

+#define FMC_SDSR_RE_Msk            (0x1UL << FMC_SDSR_RE_Pos)                  /*!< 0x00000001 */

+#define FMC_SDSR_RE                FMC_SDSR_RE_Msk                             /*!<Refresh error flag */

+

+#define FMC_SDSR_MODES1_Pos        (1U)

+#define FMC_SDSR_MODES1_Msk        (0x3UL << FMC_SDSR_MODES1_Pos)              /*!< 0x00000006 */

+#define FMC_SDSR_MODES1            FMC_SDSR_MODES1_Msk                         /*!<MODES1[1:0]bits (Status mode for bank 1) */

+#define FMC_SDSR_MODES1_0          (0x1UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000002 */

+#define FMC_SDSR_MODES1_1          (0x2UL << FMC_SDSR_MODES1_Pos)               /*!< 0x00000004 */

+

+#define FMC_SDSR_MODES2_Pos        (3U)

+#define FMC_SDSR_MODES2_Msk        (0x3UL << FMC_SDSR_MODES2_Pos)              /*!< 0x00000018 */

+#define FMC_SDSR_MODES2            FMC_SDSR_MODES2_Msk                         /*!<MODES2[1:0]bits (Status mode for bank 2) */

+#define FMC_SDSR_MODES2_0          (0x1UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000008 */

+#define FMC_SDSR_MODES2_1          (0x2UL << FMC_SDSR_MODES2_Pos)               /*!< 0x00000010 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                       Graphic MMU (GFXMMU)                                 */

+/*                                                                            */

+/******************************************************************************/

+/****************** Bits definition for GFXMMU_CR register ********************/

+#define GFXMMU_CR_B0OIE_Pos                (0U)

+#define GFXMMU_CR_B0OIE_Msk                (0x1UL << GFXMMU_CR_B0OIE_Pos)       /*!< 0x00000001 */

+#define GFXMMU_CR_B0OIE                    GFXMMU_CR_B0OIE_Msk                 /*!< Buffer 0 overflow interrupt enable */

+#define GFXMMU_CR_B1OIE_Pos                (1U)

+#define GFXMMU_CR_B1OIE_Msk                (0x1UL << GFXMMU_CR_B1OIE_Pos)       /*!< 0x00000002 */

+#define GFXMMU_CR_B1OIE                    GFXMMU_CR_B1OIE_Msk                 /*!< Buffer 1 overflow interrupt enable */

+#define GFXMMU_CR_B2OIE_Pos                (2U)

+#define GFXMMU_CR_B2OIE_Msk                (0x1UL << GFXMMU_CR_B2OIE_Pos)       /*!< 0x00000004 */

+#define GFXMMU_CR_B2OIE                    GFXMMU_CR_B2OIE_Msk                 /*!< Buffer 2 overflow interrupt enable */

+#define GFXMMU_CR_B3OIE_Pos                (3U)

+#define GFXMMU_CR_B3OIE_Msk                (0x1UL << GFXMMU_CR_B3OIE_Pos)       /*!< 0x00000008 */

+#define GFXMMU_CR_B3OIE                    GFXMMU_CR_B3OIE_Msk                 /*!< Buffer 3 overflow interrupt enable */

+#define GFXMMU_CR_AMEIE_Pos                (4U)

+#define GFXMMU_CR_AMEIE_Msk                (0x1UL << GFXMMU_CR_AMEIE_Pos)       /*!< 0x00000010 */

+#define GFXMMU_CR_AMEIE                    GFXMMU_CR_AMEIE_Msk                 /*!< AHB master error interrupt enable */

+#define GFXMMU_CR_192BM_Pos                (6U)

+#define GFXMMU_CR_192BM_Msk                (0x1UL << GFXMMU_CR_192BM_Pos)       /*!< 0x00000040 */

+#define GFXMMU_CR_192BM                    GFXMMU_CR_192BM_Msk                 /*!< 192 block mode */

+#define GFXMMU_CR_CE_Pos                   (7U)

+#define GFXMMU_CR_CE_Msk                   (0x1UL << GFXMMU_CR_CE_Pos)          /*!< 0x00000080 */

+#define GFXMMU_CR_CE                       GFXMMU_CR_CE_Msk                    /*!< Cache Enable */

+#define GFXMMU_CR_CL_Pos                   (8U)

+#define GFXMMU_CR_CL_Msk                   (0x1UL << GFXMMU_CR_CL_Pos)          /*!< 0x00000100 */

+#define GFXMMU_CR_CL                       GFXMMU_CR_CL_Msk                    /*!< Cache Lock */

+#define GFXMMU_CR_CLB_Pos                  (9U)

+#define GFXMMU_CR_CLB_Msk                  (0x3UL << GFXMMU_CR_CLB_Pos)         /*!< 0x00000600 */

+#define GFXMMU_CR_CLB                      GFXMMU_CR_CLB_Msk                   /*!< CLB[1:0]: Cache Lock Buffer */

+#define GFXMMU_CR_CLB_0                    (0x1UL << GFXMMU_CR_CLB_Pos)         /*!< Cache locked on buffer 1 */

+#define GFXMMU_CR_CLB_1                    (0x2UL << GFXMMU_CR_CLB_Pos)         /*!< Cache locked on buffer 2 */

+#define GFXMMU_CR_FC_Pos                   (11U)

+#define GFXMMU_CR_FC_Msk                   (0x1UL << GFXMMU_CR_FC_Pos)          /*!< 0x00000800 */

+#define GFXMMU_CR_FC                       GFXMMU_CR_FC_Msk                    /*!< Force Caching */

+#define GFXMMU_CR_PD_Pos                   (12U)

+#define GFXMMU_CR_PD_Msk                   (0x1UL << GFXMMU_CR_PD_Pos)          /*!< 0x00001000 */

+#define GFXMMU_CR_PD                       GFXMMU_CR_PD_Msk                    /*!< Prefetch Disable */

+#define GFXMMU_CR_OC_Pos                   (16U)

+#define GFXMMU_CR_OC_Msk                   (0x1UL << GFXMMU_CR_OC_Pos)          /*!< 0x00002000 */

+#define GFXMMU_CR_OC                       GFXMMU_CR_OC_Msk                    /*!< Outter Cachability */

+#define GFXMMU_CR_OB_Pos                   (17U)

+#define GFXMMU_CR_OB_Msk                   (0x1UL << GFXMMU_CR_OB_Pos)          /*!< 0x00002000 */

+#define GFXMMU_CR_OB                       GFXMMU_CR_OB_Msk                    /*!< Outter Bufferability */

+

+/****************** Bits definition for GFXMMU_SR register ********************/

+#define GFXMMU_SR_B0OF_Pos                 (0U)

+#define GFXMMU_SR_B0OF_Msk                 (0x1UL << GFXMMU_SR_B0OF_Pos)        /*!< 0x00000001 */

+#define GFXMMU_SR_B0OF                     GFXMMU_SR_B0OF_Msk                  /*!< Buffer 0 overflow flag */

+#define GFXMMU_SR_B1OF_Pos                 (1U)

+#define GFXMMU_SR_B1OF_Msk                 (0x1UL << GFXMMU_SR_B1OF_Pos)        /*!< 0x00000002 */

+#define GFXMMU_SR_B1OF                     GFXMMU_SR_B1OF_Msk                  /*!< Buffer 1 overflow flag */

+#define GFXMMU_SR_B2OF_Pos                 (2U)

+#define GFXMMU_SR_B2OF_Msk                 (0x1UL << GFXMMU_SR_B2OF_Pos)        /*!< 0x00000004 */

+#define GFXMMU_SR_B2OF                     GFXMMU_SR_B2OF_Msk                  /*!< Buffer 2 overflow flag */

+#define GFXMMU_SR_B3OF_Pos                 (3U)

+#define GFXMMU_SR_B3OF_Msk                 (0x1UL << GFXMMU_SR_B3OF_Pos)        /*!< 0x00000008 */

+#define GFXMMU_SR_B3OF                     GFXMMU_SR_B3OF_Msk                  /*!< Buffer 3 overflow flag */

+#define GFXMMU_SR_AMEF_Pos                 (4U)

+#define GFXMMU_SR_AMEF_Msk                 (0x1UL << GFXMMU_SR_AMEF_Pos)        /*!< 0x00000010 */

+#define GFXMMU_SR_AMEF                     GFXMMU_SR_AMEF_Msk                  /*!< AHB master error flag */

+

+/****************** Bits definition for GFXMMU_FCR register *******************/

+#define GFXMMU_FCR_CB0OF_Pos               (0U)

+#define GFXMMU_FCR_CB0OF_Msk               (0x1UL << GFXMMU_FCR_CB0OF_Pos)      /*!< 0x00000001 */

+#define GFXMMU_FCR_CB0OF                   GFXMMU_FCR_CB0OF_Msk                /*!< Clear buffer 0 overflow flag */

+#define GFXMMU_FCR_CB1OF_Pos               (1U)

+#define GFXMMU_FCR_CB1OF_Msk               (0x1UL << GFXMMU_FCR_CB1OF_Pos)      /*!< 0x00000002 */

+#define GFXMMU_FCR_CB1OF                   GFXMMU_FCR_CB1OF_Msk                /*!< Clear buffer 1 overflow flag */

+#define GFXMMU_FCR_CB2OF_Pos               (2U)

+#define GFXMMU_FCR_CB2OF_Msk               (0x1UL << GFXMMU_FCR_CB2OF_Pos)      /*!< 0x00000004 */

+#define GFXMMU_FCR_CB2OF                   GFXMMU_FCR_CB2OF_Msk                /*!< Clear buffer 2 overflow flag */

+#define GFXMMU_FCR_CB3OF_Pos               (3U)

+#define GFXMMU_FCR_CB3OF_Msk               (0x1UL << GFXMMU_FCR_CB3OF_Pos)      /*!< 0x00000008 */

+#define GFXMMU_FCR_CB3OF                   GFXMMU_FCR_CB3OF_Msk                /*!< Clear buffer 3 overflow flag */

+#define GFXMMU_FCR_CAMEF_Pos               (4U)

+#define GFXMMU_FCR_CAMEF_Msk               (0x1UL << GFXMMU_FCR_CAMEF_Pos)      /*!< 0x00000010 */

+#define GFXMMU_FCR_CAMEF                   GFXMMU_FCR_CAMEF_Msk                /*!< Clear AHB master error flag */

+

+/****************** Bits definition for GFXMMU_CCR register *******************/

+#define GFXMMU_CCR_FF_Pos                  (0U)

+#define GFXMMU_CCR_FF_Msk                  (0x1UL << GFXMMU_CCR_FF_Pos)         /*!< 0x00000001 */

+#define GFXMMU_CCR_FF                      GFXMMU_CCR_FF_Msk                   /*!< Clear buffer 0 overflow flag */

+#define GFXMMU_CCR_FI_Pos                  (1U)

+#define GFXMMU_CCR_FI_Msk                  (0x1UL << GFXMMU_CCR_FI_Pos)         /*!< 0x00000002 */

+#define GFXMMU_CCR_FI                      GFXMMU_CCR_FI_Msk                   /*!< Clear buffer 1 overflow flag */

+

+/****************** Bits definition for GFXMMU_DVR register *******************/

+#define GFXMMU_DVR_DV_Pos                  (0U)

+#define GFXMMU_DVR_DV_Msk                  (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos)  /*!< 0xFFFFFFFF */

+#define GFXMMU_DVR_DV                      GFXMMU_DVR_DV_Msk                   /*!< DV[31:0] bits (Default value) */

+

+/****************** Bits definition for GFXMMU_B0CR register ******************/

+#define GFXMMU_B0CR_PBO_Pos                (4U)

+#define GFXMMU_B0CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B0CR_PBO_Pos)   /*!< 0x007FFFF0 */

+#define GFXMMU_B0CR_PBO                    GFXMMU_B0CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */

+#define GFXMMU_B0CR_PBBA_Pos               (23U)

+#define GFXMMU_B0CR_PBBA_Msk               (0x1FFUL << GFXMMU_B0CR_PBBA_Pos)    /*!< 0xFF800000 */

+#define GFXMMU_B0CR_PBBA                   GFXMMU_B0CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */

+

+/****************** Bits definition for GFXMMU_B1CR register ******************/

+#define GFXMMU_B1CR_PBO_Pos                (4U)

+#define GFXMMU_B1CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos)   /*!< 0x007FFFF0 */

+#define GFXMMU_B1CR_PBO                    GFXMMU_B1CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */

+#define GFXMMU_B1CR_PBBA_Pos               (23U)

+#define GFXMMU_B1CR_PBBA_Msk               (0x1FFUL << GFXMMU_B1CR_PBBA_Pos)    /*!< 0xFF800000 */

+#define GFXMMU_B1CR_PBBA                   GFXMMU_B1CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */

+

+/****************** Bits definition for GFXMMU_B2CR register ******************/

+#define GFXMMU_B2CR_PBO_Pos                (4U)

+#define GFXMMU_B2CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B2CR_PBO_Pos)   /*!< 0x007FFFF0 */

+#define GFXMMU_B2CR_PBO                    GFXMMU_B2CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */

+#define GFXMMU_B2CR_PBBA_Pos               (23U)

+#define GFXMMU_B2CR_PBBA_Msk               (0x1FFUL << GFXMMU_B2CR_PBBA_Pos)    /*!< 0xFF800000 */

+#define GFXMMU_B2CR_PBBA                   GFXMMU_B2CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */

+

+/****************** Bits definition for GFXMMU_B3CR register ******************/

+#define GFXMMU_B3CR_PBO_Pos                (4U)

+#define GFXMMU_B3CR_PBO_Msk                (0x7FFFFUL << GFXMMU_B3CR_PBO_Pos)   /*!< 0x007FFFF0 */

+#define GFXMMU_B3CR_PBO                    GFXMMU_B3CR_PBO_Msk                 /*!< PB0[22:4] bits (Physical buffer offset) */

+#define GFXMMU_B3CR_PBBA_Pos               (23U)

+#define GFXMMU_B3CR_PBBA_Msk               (0x1FFUL << GFXMMU_B3CR_PBBA_Pos)    /*!< 0xFF800000 */

+#define GFXMMU_B3CR_PBBA                   GFXMMU_B3CR_PBBA_Msk                /*!< PBBA[31:23] bits (Physical buffer base address) */

+

+/****************** Bits definition for GFXMMU_LUTxL register *****************/

+#define GFXMMU_LUTxL_EN_Pos                (0U)

+#define GFXMMU_LUTxL_EN_Msk                (0x1UL << GFXMMU_LUTxL_EN_Pos)       /*!< 0x00000001 */

+#define GFXMMU_LUTxL_EN                    GFXMMU_LUTxL_EN_Msk                 /*!< Enable */

+#define GFXMMU_LUTxL_FVB_Pos               (8U)

+#define GFXMMU_LUTxL_FVB_Msk               (0xFFUL << GFXMMU_LUTxL_FVB_Pos)     /*!< 0x0000FF00 */

+#define GFXMMU_LUTxL_FVB                   GFXMMU_LUTxL_FVB_Msk                /*!< FVB[7:0] bits (First visible block) */

+#define GFXMMU_LUTxL_LVB_Pos               (16U)

+#define GFXMMU_LUTxL_LVB_Msk               (0xFFUL << GFXMMU_LUTxL_LVB_Pos)     /*!< 0x00FF0000 */

+#define GFXMMU_LUTxL_LVB                   GFXMMU_LUTxL_LVB_Msk                /*!< LVB[7:0] bits (Last visible block) */

+

+/****************** Bits definition for GFXMMU_LUTxH register *****************/

+#define GFXMMU_LUTxH_LO_Pos                (4U)

+#define GFXMMU_LUTxH_LO_Msk                (0x3FFFFUL << GFXMMU_LUTxH_LO_Pos)   /*!< 0x003FFFF0 */

+#define GFXMMU_LUTxH_LO                    GFXMMU_LUTxH_LO_Msk                 /*!< LO[21:4] bits (Line offset) */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            General Purpose I/O                             */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bits definition for GPIO_MODER register  *****************/

+#define GPIO_MODER_MODE0_Pos           (0U)

+#define GPIO_MODER_MODE0_Msk           (0x3UL << GPIO_MODER_MODE0_Pos)         /*!< 0x00000003 */

+#define GPIO_MODER_MODE0               GPIO_MODER_MODE0_Msk

+#define GPIO_MODER_MODE0_0             (0x1UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000001 */

+#define GPIO_MODER_MODE0_1             (0x2UL << GPIO_MODER_MODE0_Pos)          /*!< 0x00000002 */

+

+#define GPIO_MODER_MODE1_Pos           (2U)

+#define GPIO_MODER_MODE1_Msk           (0x3UL << GPIO_MODER_MODE1_Pos)         /*!< 0x0000000C */

+#define GPIO_MODER_MODE1               GPIO_MODER_MODE1_Msk

+#define GPIO_MODER_MODE1_0             (0x1UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000004 */

+#define GPIO_MODER_MODE1_1             (0x2UL << GPIO_MODER_MODE1_Pos)          /*!< 0x00000008 */

+

+#define GPIO_MODER_MODE2_Pos           (4U)

+#define GPIO_MODER_MODE2_Msk           (0x3UL << GPIO_MODER_MODE2_Pos)         /*!< 0x00000030 */

+#define GPIO_MODER_MODE2               GPIO_MODER_MODE2_Msk

+#define GPIO_MODER_MODE2_0             (0x1UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000010 */

+#define GPIO_MODER_MODE2_1             (0x2UL << GPIO_MODER_MODE2_Pos)          /*!< 0x00000020 */

+

+#define GPIO_MODER_MODE3_Pos           (6U)

+#define GPIO_MODER_MODE3_Msk           (0x3UL << GPIO_MODER_MODE3_Pos)         /*!< 0x000000C0 */

+#define GPIO_MODER_MODE3               GPIO_MODER_MODE3_Msk

+#define GPIO_MODER_MODE3_0             (0x1UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000040 */

+#define GPIO_MODER_MODE3_1             (0x2UL << GPIO_MODER_MODE3_Pos)          /*!< 0x00000080 */

+

+#define GPIO_MODER_MODE4_Pos           (8U)

+#define GPIO_MODER_MODE4_Msk           (0x3UL << GPIO_MODER_MODE4_Pos)         /*!< 0x00000300 */

+#define GPIO_MODER_MODE4               GPIO_MODER_MODE4_Msk

+#define GPIO_MODER_MODE4_0             (0x1UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000100 */

+#define GPIO_MODER_MODE4_1             (0x2UL << GPIO_MODER_MODE4_Pos)          /*!< 0x00000200 */

+

+#define GPIO_MODER_MODE5_Pos           (10U)

+#define GPIO_MODER_MODE5_Msk           (0x3UL << GPIO_MODER_MODE5_Pos)         /*!< 0x00000C00 */

+#define GPIO_MODER_MODE5               GPIO_MODER_MODE5_Msk

+#define GPIO_MODER_MODE5_0             (0x1UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000400 */

+#define GPIO_MODER_MODE5_1             (0x2UL << GPIO_MODER_MODE5_Pos)          /*!< 0x00000800 */

+

+#define GPIO_MODER_MODE6_Pos           (12U)

+#define GPIO_MODER_MODE6_Msk           (0x3UL << GPIO_MODER_MODE6_Pos)         /*!< 0x00003000 */

+#define GPIO_MODER_MODE6               GPIO_MODER_MODE6_Msk

+#define GPIO_MODER_MODE6_0             (0x1UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00001000 */

+#define GPIO_MODER_MODE6_1             (0x2UL << GPIO_MODER_MODE6_Pos)          /*!< 0x00002000 */

+

+#define GPIO_MODER_MODE7_Pos           (14U)

+#define GPIO_MODER_MODE7_Msk           (0x3UL << GPIO_MODER_MODE7_Pos)         /*!< 0x0000C000 */

+#define GPIO_MODER_MODE7               GPIO_MODER_MODE7_Msk

+#define GPIO_MODER_MODE7_0             (0x1UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00004000 */

+#define GPIO_MODER_MODE7_1             (0x2UL << GPIO_MODER_MODE7_Pos)          /*!< 0x00008000 */

+

+#define GPIO_MODER_MODE8_Pos           (16U)

+#define GPIO_MODER_MODE8_Msk           (0x3UL << GPIO_MODER_MODE8_Pos)         /*!< 0x00030000 */

+#define GPIO_MODER_MODE8               GPIO_MODER_MODE8_Msk

+#define GPIO_MODER_MODE8_0             (0x1UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00010000 */

+#define GPIO_MODER_MODE8_1             (0x2UL << GPIO_MODER_MODE8_Pos)          /*!< 0x00020000 */

+

+#define GPIO_MODER_MODE9_Pos           (18U)

+#define GPIO_MODER_MODE9_Msk           (0x3UL << GPIO_MODER_MODE9_Pos)         /*!< 0x000C0000 */

+#define GPIO_MODER_MODE9               GPIO_MODER_MODE9_Msk

+#define GPIO_MODER_MODE9_0             (0x1UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00040000 */

+#define GPIO_MODER_MODE9_1             (0x2UL << GPIO_MODER_MODE9_Pos)          /*!< 0x00080000 */

+

+#define GPIO_MODER_MODE10_Pos          (20U)

+#define GPIO_MODER_MODE10_Msk          (0x3UL << GPIO_MODER_MODE10_Pos)        /*!< 0x00300000 */

+#define GPIO_MODER_MODE10              GPIO_MODER_MODE10_Msk

+#define GPIO_MODER_MODE10_0            (0x1UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00100000 */

+#define GPIO_MODER_MODE10_1            (0x2UL << GPIO_MODER_MODE10_Pos)         /*!< 0x00200000 */

+

+#define GPIO_MODER_MODE11_Pos          (22U)

+#define GPIO_MODER_MODE11_Msk          (0x3UL << GPIO_MODER_MODE11_Pos)        /*!< 0x00C00000 */

+#define GPIO_MODER_MODE11              GPIO_MODER_MODE11_Msk

+#define GPIO_MODER_MODE11_0            (0x1UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00400000 */

+#define GPIO_MODER_MODE11_1            (0x2UL << GPIO_MODER_MODE11_Pos)         /*!< 0x00800000 */

+

+#define GPIO_MODER_MODE12_Pos          (24U)

+#define GPIO_MODER_MODE12_Msk          (0x3UL << GPIO_MODER_MODE12_Pos)        /*!< 0x03000000 */

+#define GPIO_MODER_MODE12              GPIO_MODER_MODE12_Msk

+#define GPIO_MODER_MODE12_0            (0x1UL << GPIO_MODER_MODE12_Pos)         /*!< 0x01000000 */

+#define GPIO_MODER_MODE12_1            (0x2UL << GPIO_MODER_MODE12_Pos)         /*!< 0x02000000 */

+

+#define GPIO_MODER_MODE13_Pos          (26U)

+#define GPIO_MODER_MODE13_Msk          (0x3UL << GPIO_MODER_MODE13_Pos)        /*!< 0x0C000000 */

+#define GPIO_MODER_MODE13              GPIO_MODER_MODE13_Msk

+#define GPIO_MODER_MODE13_0            (0x1UL << GPIO_MODER_MODE13_Pos)         /*!< 0x04000000 */

+#define GPIO_MODER_MODE13_1            (0x2UL << GPIO_MODER_MODE13_Pos)         /*!< 0x08000000 */

+

+#define GPIO_MODER_MODE14_Pos          (28U)

+#define GPIO_MODER_MODE14_Msk          (0x3UL << GPIO_MODER_MODE14_Pos)        /*!< 0x30000000 */

+#define GPIO_MODER_MODE14              GPIO_MODER_MODE14_Msk

+#define GPIO_MODER_MODE14_0            (0x1UL << GPIO_MODER_MODE14_Pos)         /*!< 0x10000000 */

+#define GPIO_MODER_MODE14_1            (0x2UL << GPIO_MODER_MODE14_Pos)         /*!< 0x20000000 */

+

+#define GPIO_MODER_MODE15_Pos          (30U)

+#define GPIO_MODER_MODE15_Msk          (0x3UL << GPIO_MODER_MODE15_Pos)        /*!< 0xC0000000 */

+#define GPIO_MODER_MODE15              GPIO_MODER_MODE15_Msk

+#define GPIO_MODER_MODE15_0            (0x1UL << GPIO_MODER_MODE15_Pos)         /*!< 0x40000000 */

+#define GPIO_MODER_MODE15_1            (0x2UL << GPIO_MODER_MODE15_Pos)         /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_OTYPER register  ****************/

+#define GPIO_OTYPER_OT0_Pos            (0U)

+#define GPIO_OTYPER_OT0_Msk            (0x1UL << GPIO_OTYPER_OT0_Pos)          /*!< 0x00000001 */

+#define GPIO_OTYPER_OT0                GPIO_OTYPER_OT0_Msk

+#define GPIO_OTYPER_OT1_Pos            (1U)

+#define GPIO_OTYPER_OT1_Msk            (0x1UL << GPIO_OTYPER_OT1_Pos)          /*!< 0x00000002 */

+#define GPIO_OTYPER_OT1                GPIO_OTYPER_OT1_Msk

+#define GPIO_OTYPER_OT2_Pos            (2U)

+#define GPIO_OTYPER_OT2_Msk            (0x1UL << GPIO_OTYPER_OT2_Pos)          /*!< 0x00000004 */

+#define GPIO_OTYPER_OT2                GPIO_OTYPER_OT2_Msk

+#define GPIO_OTYPER_OT3_Pos            (3U)

+#define GPIO_OTYPER_OT3_Msk            (0x1UL << GPIO_OTYPER_OT3_Pos)          /*!< 0x00000008 */

+#define GPIO_OTYPER_OT3                GPIO_OTYPER_OT3_Msk

+#define GPIO_OTYPER_OT4_Pos            (4U)

+#define GPIO_OTYPER_OT4_Msk            (0x1UL << GPIO_OTYPER_OT4_Pos)          /*!< 0x00000010 */

+#define GPIO_OTYPER_OT4                GPIO_OTYPER_OT4_Msk

+#define GPIO_OTYPER_OT5_Pos            (5U)

+#define GPIO_OTYPER_OT5_Msk            (0x1UL << GPIO_OTYPER_OT5_Pos)          /*!< 0x00000020 */

+#define GPIO_OTYPER_OT5                GPIO_OTYPER_OT5_Msk

+#define GPIO_OTYPER_OT6_Pos            (6U)

+#define GPIO_OTYPER_OT6_Msk            (0x1UL << GPIO_OTYPER_OT6_Pos)          /*!< 0x00000040 */

+#define GPIO_OTYPER_OT6                GPIO_OTYPER_OT6_Msk

+#define GPIO_OTYPER_OT7_Pos            (7U)

+#define GPIO_OTYPER_OT7_Msk            (0x1UL << GPIO_OTYPER_OT7_Pos)          /*!< 0x00000080 */

+#define GPIO_OTYPER_OT7                GPIO_OTYPER_OT7_Msk

+#define GPIO_OTYPER_OT8_Pos            (8U)

+#define GPIO_OTYPER_OT8_Msk            (0x1UL << GPIO_OTYPER_OT8_Pos)          /*!< 0x00000100 */

+#define GPIO_OTYPER_OT8                GPIO_OTYPER_OT8_Msk

+#define GPIO_OTYPER_OT9_Pos            (9U)

+#define GPIO_OTYPER_OT9_Msk            (0x1UL << GPIO_OTYPER_OT9_Pos)          /*!< 0x00000200 */

+#define GPIO_OTYPER_OT9                GPIO_OTYPER_OT9_Msk

+#define GPIO_OTYPER_OT10_Pos           (10U)

+#define GPIO_OTYPER_OT10_Msk           (0x1UL << GPIO_OTYPER_OT10_Pos)         /*!< 0x00000400 */

+#define GPIO_OTYPER_OT10               GPIO_OTYPER_OT10_Msk

+#define GPIO_OTYPER_OT11_Pos           (11U)

+#define GPIO_OTYPER_OT11_Msk           (0x1UL << GPIO_OTYPER_OT11_Pos)         /*!< 0x00000800 */

+#define GPIO_OTYPER_OT11               GPIO_OTYPER_OT11_Msk

+#define GPIO_OTYPER_OT12_Pos           (12U)

+#define GPIO_OTYPER_OT12_Msk           (0x1UL << GPIO_OTYPER_OT12_Pos)         /*!< 0x00001000 */

+#define GPIO_OTYPER_OT12               GPIO_OTYPER_OT12_Msk

+#define GPIO_OTYPER_OT13_Pos           (13U)

+#define GPIO_OTYPER_OT13_Msk           (0x1UL << GPIO_OTYPER_OT13_Pos)         /*!< 0x00002000 */

+#define GPIO_OTYPER_OT13               GPIO_OTYPER_OT13_Msk

+#define GPIO_OTYPER_OT14_Pos           (14U)

+#define GPIO_OTYPER_OT14_Msk           (0x1UL << GPIO_OTYPER_OT14_Pos)         /*!< 0x00004000 */

+#define GPIO_OTYPER_OT14               GPIO_OTYPER_OT14_Msk

+#define GPIO_OTYPER_OT15_Pos           (15U)

+#define GPIO_OTYPER_OT15_Msk           (0x1UL << GPIO_OTYPER_OT15_Pos)         /*!< 0x00008000 */

+#define GPIO_OTYPER_OT15               GPIO_OTYPER_OT15_Msk

+

+/******************  Bits definition for GPIO_OSPEEDR register  ***************/

+#define GPIO_OSPEEDR_OSPEED0_Pos       (0U)

+#define GPIO_OSPEEDR_OSPEED0_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos)     /*!< 0x00000003 */

+#define GPIO_OSPEEDR_OSPEED0           GPIO_OSPEEDR_OSPEED0_Msk

+#define GPIO_OSPEEDR_OSPEED0_0         (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000001 */

+#define GPIO_OSPEEDR_OSPEED0_1         (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos)      /*!< 0x00000002 */

+

+#define GPIO_OSPEEDR_OSPEED1_Pos       (2U)

+#define GPIO_OSPEEDR_OSPEED1_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos)     /*!< 0x0000000C */

+#define GPIO_OSPEEDR_OSPEED1           GPIO_OSPEEDR_OSPEED1_Msk

+#define GPIO_OSPEEDR_OSPEED1_0         (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000004 */

+#define GPIO_OSPEEDR_OSPEED1_1         (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos)      /*!< 0x00000008 */

+

+#define GPIO_OSPEEDR_OSPEED2_Pos       (4U)

+#define GPIO_OSPEEDR_OSPEED2_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos)     /*!< 0x00000030 */

+#define GPIO_OSPEEDR_OSPEED2           GPIO_OSPEEDR_OSPEED2_Msk

+#define GPIO_OSPEEDR_OSPEED2_0         (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000010 */

+#define GPIO_OSPEEDR_OSPEED2_1         (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos)      /*!< 0x00000020 */

+

+#define GPIO_OSPEEDR_OSPEED3_Pos       (6U)

+#define GPIO_OSPEEDR_OSPEED3_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos)     /*!< 0x000000C0 */

+#define GPIO_OSPEEDR_OSPEED3           GPIO_OSPEEDR_OSPEED3_Msk

+#define GPIO_OSPEEDR_OSPEED3_0         (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000040 */

+#define GPIO_OSPEEDR_OSPEED3_1         (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos)      /*!< 0x00000080 */

+

+#define GPIO_OSPEEDR_OSPEED4_Pos       (8U)

+#define GPIO_OSPEEDR_OSPEED4_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos)     /*!< 0x00000300 */

+#define GPIO_OSPEEDR_OSPEED4           GPIO_OSPEEDR_OSPEED4_Msk

+#define GPIO_OSPEEDR_OSPEED4_0         (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000100 */

+#define GPIO_OSPEEDR_OSPEED4_1         (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos)      /*!< 0x00000200 */

+

+#define GPIO_OSPEEDR_OSPEED5_Pos       (10U)

+#define GPIO_OSPEEDR_OSPEED5_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos)     /*!< 0x00000C00 */

+#define GPIO_OSPEEDR_OSPEED5           GPIO_OSPEEDR_OSPEED5_Msk

+#define GPIO_OSPEEDR_OSPEED5_0         (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000400 */

+#define GPIO_OSPEEDR_OSPEED5_1         (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos)      /*!< 0x00000800 */

+

+#define GPIO_OSPEEDR_OSPEED6_Pos       (12U)

+#define GPIO_OSPEEDR_OSPEED6_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos)     /*!< 0x00003000 */

+#define GPIO_OSPEEDR_OSPEED6           GPIO_OSPEEDR_OSPEED6_Msk

+#define GPIO_OSPEEDR_OSPEED6_0         (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00001000 */

+#define GPIO_OSPEEDR_OSPEED6_1         (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos)      /*!< 0x00002000 */

+

+#define GPIO_OSPEEDR_OSPEED7_Pos       (14U)

+#define GPIO_OSPEEDR_OSPEED7_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos)     /*!< 0x0000C000 */

+#define GPIO_OSPEEDR_OSPEED7           GPIO_OSPEEDR_OSPEED7_Msk

+#define GPIO_OSPEEDR_OSPEED7_0         (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00004000 */

+#define GPIO_OSPEEDR_OSPEED7_1         (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos)      /*!< 0x00008000 */

+

+#define GPIO_OSPEEDR_OSPEED8_Pos       (16U)

+#define GPIO_OSPEEDR_OSPEED8_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos)     /*!< 0x00030000 */

+#define GPIO_OSPEEDR_OSPEED8           GPIO_OSPEEDR_OSPEED8_Msk

+#define GPIO_OSPEEDR_OSPEED8_0         (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00010000 */

+#define GPIO_OSPEEDR_OSPEED8_1         (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos)      /*!< 0x00020000 */

+

+#define GPIO_OSPEEDR_OSPEED9_Pos       (18U)

+#define GPIO_OSPEEDR_OSPEED9_Msk       (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos)     /*!< 0x000C0000 */

+#define GPIO_OSPEEDR_OSPEED9           GPIO_OSPEEDR_OSPEED9_Msk

+#define GPIO_OSPEEDR_OSPEED9_0         (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00040000 */

+#define GPIO_OSPEEDR_OSPEED9_1         (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos)      /*!< 0x00080000 */

+

+#define GPIO_OSPEEDR_OSPEED10_Pos      (20U)

+#define GPIO_OSPEEDR_OSPEED10_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos)    /*!< 0x00300000 */

+#define GPIO_OSPEEDR_OSPEED10          GPIO_OSPEEDR_OSPEED10_Msk

+#define GPIO_OSPEEDR_OSPEED10_0        (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00100000 */

+#define GPIO_OSPEEDR_OSPEED10_1        (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos)     /*!< 0x00200000 */

+

+#define GPIO_OSPEEDR_OSPEED11_Pos      (22U)

+#define GPIO_OSPEEDR_OSPEED11_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos)    /*!< 0x00C00000 */

+#define GPIO_OSPEEDR_OSPEED11          GPIO_OSPEEDR_OSPEED11_Msk

+#define GPIO_OSPEEDR_OSPEED11_0        (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00400000 */

+#define GPIO_OSPEEDR_OSPEED11_1        (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos)     /*!< 0x00800000 */

+

+#define GPIO_OSPEEDR_OSPEED12_Pos      (24U)

+#define GPIO_OSPEEDR_OSPEED12_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos)    /*!< 0x03000000 */

+#define GPIO_OSPEEDR_OSPEED12          GPIO_OSPEEDR_OSPEED12_Msk

+#define GPIO_OSPEEDR_OSPEED12_0        (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x01000000 */

+#define GPIO_OSPEEDR_OSPEED12_1        (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos)     /*!< 0x02000000 */

+

+#define GPIO_OSPEEDR_OSPEED13_Pos      (26U)

+#define GPIO_OSPEEDR_OSPEED13_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos)    /*!< 0x0C000000 */

+#define GPIO_OSPEEDR_OSPEED13          GPIO_OSPEEDR_OSPEED13_Msk

+#define GPIO_OSPEEDR_OSPEED13_0        (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x04000000 */

+#define GPIO_OSPEEDR_OSPEED13_1        (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos)     /*!< 0x08000000 */

+

+#define GPIO_OSPEEDR_OSPEED14_Pos      (28U)

+#define GPIO_OSPEEDR_OSPEED14_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos)    /*!< 0x30000000 */

+#define GPIO_OSPEEDR_OSPEED14          GPIO_OSPEEDR_OSPEED14_Msk

+#define GPIO_OSPEEDR_OSPEED14_0        (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x10000000 */

+#define GPIO_OSPEEDR_OSPEED14_1        (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos)     /*!< 0x20000000 */

+

+#define GPIO_OSPEEDR_OSPEED15_Pos      (30U)

+#define GPIO_OSPEEDR_OSPEED15_Msk      (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos)    /*!< 0xC0000000 */

+#define GPIO_OSPEEDR_OSPEED15          GPIO_OSPEEDR_OSPEED15_Msk

+#define GPIO_OSPEEDR_OSPEED15_0        (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x40000000 */

+#define GPIO_OSPEEDR_OSPEED15_1        (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos)     /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_PUPDR register  *****************/

+#define GPIO_PUPDR_PUPD0_Pos           (0U)

+#define GPIO_PUPDR_PUPD0_Msk           (0x3UL << GPIO_PUPDR_PUPD0_Pos)         /*!< 0x00000003 */

+#define GPIO_PUPDR_PUPD0               GPIO_PUPDR_PUPD0_Msk

+#define GPIO_PUPDR_PUPD0_0             (0x1UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000001 */

+#define GPIO_PUPDR_PUPD0_1             (0x2UL << GPIO_PUPDR_PUPD0_Pos)          /*!< 0x00000002 */

+

+#define GPIO_PUPDR_PUPD1_Pos           (2U)

+#define GPIO_PUPDR_PUPD1_Msk           (0x3UL << GPIO_PUPDR_PUPD1_Pos)         /*!< 0x0000000C */

+#define GPIO_PUPDR_PUPD1               GPIO_PUPDR_PUPD1_Msk

+#define GPIO_PUPDR_PUPD1_0             (0x1UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000004 */

+#define GPIO_PUPDR_PUPD1_1             (0x2UL << GPIO_PUPDR_PUPD1_Pos)          /*!< 0x00000008 */

+

+#define GPIO_PUPDR_PUPD2_Pos           (4U)

+#define GPIO_PUPDR_PUPD2_Msk           (0x3UL << GPIO_PUPDR_PUPD2_Pos)         /*!< 0x00000030 */

+#define GPIO_PUPDR_PUPD2               GPIO_PUPDR_PUPD2_Msk

+#define GPIO_PUPDR_PUPD2_0             (0x1UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000010 */

+#define GPIO_PUPDR_PUPD2_1             (0x2UL << GPIO_PUPDR_PUPD2_Pos)          /*!< 0x00000020 */

+

+#define GPIO_PUPDR_PUPD3_Pos           (6U)

+#define GPIO_PUPDR_PUPD3_Msk           (0x3UL << GPIO_PUPDR_PUPD3_Pos)         /*!< 0x000000C0 */

+#define GPIO_PUPDR_PUPD3               GPIO_PUPDR_PUPD3_Msk

+#define GPIO_PUPDR_PUPD3_0             (0x1UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000040 */

+#define GPIO_PUPDR_PUPD3_1             (0x2UL << GPIO_PUPDR_PUPD3_Pos)          /*!< 0x00000080 */

+

+#define GPIO_PUPDR_PUPD4_Pos           (8U)

+#define GPIO_PUPDR_PUPD4_Msk           (0x3UL << GPIO_PUPDR_PUPD4_Pos)         /*!< 0x00000300 */

+#define GPIO_PUPDR_PUPD4               GPIO_PUPDR_PUPD4_Msk

+#define GPIO_PUPDR_PUPD4_0             (0x1UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000100 */

+#define GPIO_PUPDR_PUPD4_1             (0x2UL << GPIO_PUPDR_PUPD4_Pos)          /*!< 0x00000200 */

+

+#define GPIO_PUPDR_PUPD5_Pos           (10U)

+#define GPIO_PUPDR_PUPD5_Msk           (0x3UL << GPIO_PUPDR_PUPD5_Pos)         /*!< 0x00000C00 */

+#define GPIO_PUPDR_PUPD5               GPIO_PUPDR_PUPD5_Msk

+#define GPIO_PUPDR_PUPD5_0             (0x1UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000400 */

+#define GPIO_PUPDR_PUPD5_1             (0x2UL << GPIO_PUPDR_PUPD5_Pos)          /*!< 0x00000800 */

+

+#define GPIO_PUPDR_PUPD6_Pos           (12U)

+#define GPIO_PUPDR_PUPD6_Msk           (0x3UL << GPIO_PUPDR_PUPD6_Pos)         /*!< 0x00003000 */

+#define GPIO_PUPDR_PUPD6               GPIO_PUPDR_PUPD6_Msk

+#define GPIO_PUPDR_PUPD6_0             (0x1UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00001000 */

+#define GPIO_PUPDR_PUPD6_1             (0x2UL << GPIO_PUPDR_PUPD6_Pos)          /*!< 0x00002000 */

+

+#define GPIO_PUPDR_PUPD7_Pos           (14U)

+#define GPIO_PUPDR_PUPD7_Msk           (0x3UL << GPIO_PUPDR_PUPD7_Pos)         /*!< 0x0000C000 */

+#define GPIO_PUPDR_PUPD7               GPIO_PUPDR_PUPD7_Msk

+#define GPIO_PUPDR_PUPD7_0             (0x1UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00004000 */

+#define GPIO_PUPDR_PUPD7_1             (0x2UL << GPIO_PUPDR_PUPD7_Pos)          /*!< 0x00008000 */

+

+#define GPIO_PUPDR_PUPD8_Pos           (16U)

+#define GPIO_PUPDR_PUPD8_Msk           (0x3UL << GPIO_PUPDR_PUPD8_Pos)         /*!< 0x00030000 */

+#define GPIO_PUPDR_PUPD8               GPIO_PUPDR_PUPD8_Msk

+#define GPIO_PUPDR_PUPD8_0             (0x1UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00010000 */

+#define GPIO_PUPDR_PUPD8_1             (0x2UL << GPIO_PUPDR_PUPD8_Pos)          /*!< 0x00020000 */

+

+#define GPIO_PUPDR_PUPD9_Pos           (18U)

+#define GPIO_PUPDR_PUPD9_Msk           (0x3UL << GPIO_PUPDR_PUPD9_Pos)         /*!< 0x000C0000 */

+#define GPIO_PUPDR_PUPD9               GPIO_PUPDR_PUPD9_Msk

+#define GPIO_PUPDR_PUPD9_0             (0x1UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00040000 */

+#define GPIO_PUPDR_PUPD9_1             (0x2UL << GPIO_PUPDR_PUPD9_Pos)          /*!< 0x00080000 */

+

+#define GPIO_PUPDR_PUPD10_Pos          (20U)

+#define GPIO_PUPDR_PUPD10_Msk          (0x3UL << GPIO_PUPDR_PUPD10_Pos)        /*!< 0x00300000 */

+#define GPIO_PUPDR_PUPD10              GPIO_PUPDR_PUPD10_Msk

+#define GPIO_PUPDR_PUPD10_0            (0x1UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00100000 */

+#define GPIO_PUPDR_PUPD10_1            (0x2UL << GPIO_PUPDR_PUPD10_Pos)         /*!< 0x00200000 */

+

+#define GPIO_PUPDR_PUPD11_Pos          (22U)

+#define GPIO_PUPDR_PUPD11_Msk          (0x3UL << GPIO_PUPDR_PUPD11_Pos)        /*!< 0x00C00000 */

+#define GPIO_PUPDR_PUPD11              GPIO_PUPDR_PUPD11_Msk

+#define GPIO_PUPDR_PUPD11_0            (0x1UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00400000 */

+#define GPIO_PUPDR_PUPD11_1            (0x2UL << GPIO_PUPDR_PUPD11_Pos)         /*!< 0x00800000 */

+

+#define GPIO_PUPDR_PUPD12_Pos          (24U)

+#define GPIO_PUPDR_PUPD12_Msk          (0x3UL << GPIO_PUPDR_PUPD12_Pos)        /*!< 0x03000000 */

+#define GPIO_PUPDR_PUPD12              GPIO_PUPDR_PUPD12_Msk

+#define GPIO_PUPDR_PUPD12_0            (0x1UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x01000000 */

+#define GPIO_PUPDR_PUPD12_1            (0x2UL << GPIO_PUPDR_PUPD12_Pos)         /*!< 0x02000000 */

+

+#define GPIO_PUPDR_PUPD13_Pos          (26U)

+#define GPIO_PUPDR_PUPD13_Msk          (0x3UL << GPIO_PUPDR_PUPD13_Pos)        /*!< 0x0C000000 */

+#define GPIO_PUPDR_PUPD13              GPIO_PUPDR_PUPD13_Msk

+#define GPIO_PUPDR_PUPD13_0            (0x1UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x04000000 */

+#define GPIO_PUPDR_PUPD13_1            (0x2UL << GPIO_PUPDR_PUPD13_Pos)         /*!< 0x08000000 */

+

+#define GPIO_PUPDR_PUPD14_Pos          (28U)

+#define GPIO_PUPDR_PUPD14_Msk          (0x3UL << GPIO_PUPDR_PUPD14_Pos)        /*!< 0x30000000 */

+#define GPIO_PUPDR_PUPD14              GPIO_PUPDR_PUPD14_Msk

+#define GPIO_PUPDR_PUPD14_0            (0x1UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x10000000 */

+#define GPIO_PUPDR_PUPD14_1            (0x2UL << GPIO_PUPDR_PUPD14_Pos)         /*!< 0x20000000 */

+

+#define GPIO_PUPDR_PUPD15_Pos          (30U)

+#define GPIO_PUPDR_PUPD15_Msk          (0x3UL << GPIO_PUPDR_PUPD15_Pos)        /*!< 0xC0000000 */

+#define GPIO_PUPDR_PUPD15              GPIO_PUPDR_PUPD15_Msk

+#define GPIO_PUPDR_PUPD15_0            (0x1UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x40000000 */

+#define GPIO_PUPDR_PUPD15_1            (0x2UL << GPIO_PUPDR_PUPD15_Pos)         /*!< 0x80000000 */

+

+/******************  Bits definition for GPIO_IDR register  *******************/

+#define GPIO_IDR_ID0_Pos               (0U)

+#define GPIO_IDR_ID0_Msk               (0x1UL << GPIO_IDR_ID0_Pos)             /*!< 0x00000001 */

+#define GPIO_IDR_ID0                   GPIO_IDR_ID0_Msk

+#define GPIO_IDR_ID1_Pos               (1U)

+#define GPIO_IDR_ID1_Msk               (0x1UL << GPIO_IDR_ID1_Pos)             /*!< 0x00000002 */

+#define GPIO_IDR_ID1                   GPIO_IDR_ID1_Msk

+#define GPIO_IDR_ID2_Pos               (2U)

+#define GPIO_IDR_ID2_Msk               (0x1UL << GPIO_IDR_ID2_Pos)             /*!< 0x00000004 */

+#define GPIO_IDR_ID2                   GPIO_IDR_ID2_Msk

+#define GPIO_IDR_ID3_Pos               (3U)

+#define GPIO_IDR_ID3_Msk               (0x1UL << GPIO_IDR_ID3_Pos)             /*!< 0x00000008 */

+#define GPIO_IDR_ID3                   GPIO_IDR_ID3_Msk

+#define GPIO_IDR_ID4_Pos               (4U)

+#define GPIO_IDR_ID4_Msk               (0x1UL << GPIO_IDR_ID4_Pos)             /*!< 0x00000010 */

+#define GPIO_IDR_ID4                   GPIO_IDR_ID4_Msk

+#define GPIO_IDR_ID5_Pos               (5U)

+#define GPIO_IDR_ID5_Msk               (0x1UL << GPIO_IDR_ID5_Pos)             /*!< 0x00000020 */

+#define GPIO_IDR_ID5                   GPIO_IDR_ID5_Msk

+#define GPIO_IDR_ID6_Pos               (6U)

+#define GPIO_IDR_ID6_Msk               (0x1UL << GPIO_IDR_ID6_Pos)             /*!< 0x00000040 */

+#define GPIO_IDR_ID6                   GPIO_IDR_ID6_Msk

+#define GPIO_IDR_ID7_Pos               (7U)

+#define GPIO_IDR_ID7_Msk               (0x1UL << GPIO_IDR_ID7_Pos)             /*!< 0x00000080 */

+#define GPIO_IDR_ID7                   GPIO_IDR_ID7_Msk

+#define GPIO_IDR_ID8_Pos               (8U)

+#define GPIO_IDR_ID8_Msk               (0x1UL << GPIO_IDR_ID8_Pos)             /*!< 0x00000100 */

+#define GPIO_IDR_ID8                   GPIO_IDR_ID8_Msk

+#define GPIO_IDR_ID9_Pos               (9U)

+#define GPIO_IDR_ID9_Msk               (0x1UL << GPIO_IDR_ID9_Pos)             /*!< 0x00000200 */

+#define GPIO_IDR_ID9                   GPIO_IDR_ID9_Msk

+#define GPIO_IDR_ID10_Pos              (10U)

+#define GPIO_IDR_ID10_Msk              (0x1UL << GPIO_IDR_ID10_Pos)            /*!< 0x00000400 */

+#define GPIO_IDR_ID10                  GPIO_IDR_ID10_Msk

+#define GPIO_IDR_ID11_Pos              (11U)

+#define GPIO_IDR_ID11_Msk              (0x1UL << GPIO_IDR_ID11_Pos)            /*!< 0x00000800 */

+#define GPIO_IDR_ID11                  GPIO_IDR_ID11_Msk

+#define GPIO_IDR_ID12_Pos              (12U)

+#define GPIO_IDR_ID12_Msk              (0x1UL << GPIO_IDR_ID12_Pos)            /*!< 0x00001000 */

+#define GPIO_IDR_ID12                  GPIO_IDR_ID12_Msk

+#define GPIO_IDR_ID13_Pos              (13U)

+#define GPIO_IDR_ID13_Msk              (0x1UL << GPIO_IDR_ID13_Pos)            /*!< 0x00002000 */

+#define GPIO_IDR_ID13                  GPIO_IDR_ID13_Msk

+#define GPIO_IDR_ID14_Pos              (14U)

+#define GPIO_IDR_ID14_Msk              (0x1UL << GPIO_IDR_ID14_Pos)            /*!< 0x00004000 */

+#define GPIO_IDR_ID14                  GPIO_IDR_ID14_Msk

+#define GPIO_IDR_ID15_Pos              (15U)

+#define GPIO_IDR_ID15_Msk              (0x1UL << GPIO_IDR_ID15_Pos)            /*!< 0x00008000 */

+#define GPIO_IDR_ID15                  GPIO_IDR_ID15_Msk

+

+/******************  Bits definition for GPIO_ODR register  *******************/

+#define GPIO_ODR_OD0_Pos               (0U)

+#define GPIO_ODR_OD0_Msk               (0x1UL << GPIO_ODR_OD0_Pos)             /*!< 0x00000001 */

+#define GPIO_ODR_OD0                   GPIO_ODR_OD0_Msk

+#define GPIO_ODR_OD1_Pos               (1U)

+#define GPIO_ODR_OD1_Msk               (0x1UL << GPIO_ODR_OD1_Pos)             /*!< 0x00000002 */

+#define GPIO_ODR_OD1                   GPIO_ODR_OD1_Msk

+#define GPIO_ODR_OD2_Pos               (2U)

+#define GPIO_ODR_OD2_Msk               (0x1UL << GPIO_ODR_OD2_Pos)             /*!< 0x00000004 */

+#define GPIO_ODR_OD2                   GPIO_ODR_OD2_Msk

+#define GPIO_ODR_OD3_Pos               (3U)

+#define GPIO_ODR_OD3_Msk               (0x1UL << GPIO_ODR_OD3_Pos)             /*!< 0x00000008 */

+#define GPIO_ODR_OD3                   GPIO_ODR_OD3_Msk

+#define GPIO_ODR_OD4_Pos               (4U)

+#define GPIO_ODR_OD4_Msk               (0x1UL << GPIO_ODR_OD4_Pos)             /*!< 0x00000010 */

+#define GPIO_ODR_OD4                   GPIO_ODR_OD4_Msk

+#define GPIO_ODR_OD5_Pos               (5U)

+#define GPIO_ODR_OD5_Msk               (0x1UL << GPIO_ODR_OD5_Pos)             /*!< 0x00000020 */

+#define GPIO_ODR_OD5                   GPIO_ODR_OD5_Msk

+#define GPIO_ODR_OD6_Pos               (6U)

+#define GPIO_ODR_OD6_Msk               (0x1UL << GPIO_ODR_OD6_Pos)             /*!< 0x00000040 */

+#define GPIO_ODR_OD6                   GPIO_ODR_OD6_Msk

+#define GPIO_ODR_OD7_Pos               (7U)

+#define GPIO_ODR_OD7_Msk               (0x1UL << GPIO_ODR_OD7_Pos)             /*!< 0x00000080 */

+#define GPIO_ODR_OD7                   GPIO_ODR_OD7_Msk

+#define GPIO_ODR_OD8_Pos               (8U)

+#define GPIO_ODR_OD8_Msk               (0x1UL << GPIO_ODR_OD8_Pos)             /*!< 0x00000100 */

+#define GPIO_ODR_OD8                   GPIO_ODR_OD8_Msk

+#define GPIO_ODR_OD9_Pos               (9U)

+#define GPIO_ODR_OD9_Msk               (0x1UL << GPIO_ODR_OD9_Pos)             /*!< 0x00000200 */

+#define GPIO_ODR_OD9                   GPIO_ODR_OD9_Msk

+#define GPIO_ODR_OD10_Pos              (10U)

+#define GPIO_ODR_OD10_Msk              (0x1UL << GPIO_ODR_OD10_Pos)            /*!< 0x00000400 */

+#define GPIO_ODR_OD10                  GPIO_ODR_OD10_Msk

+#define GPIO_ODR_OD11_Pos              (11U)

+#define GPIO_ODR_OD11_Msk              (0x1UL << GPIO_ODR_OD11_Pos)            /*!< 0x00000800 */

+#define GPIO_ODR_OD11                  GPIO_ODR_OD11_Msk

+#define GPIO_ODR_OD12_Pos              (12U)

+#define GPIO_ODR_OD12_Msk              (0x1UL << GPIO_ODR_OD12_Pos)            /*!< 0x00001000 */

+#define GPIO_ODR_OD12                  GPIO_ODR_OD12_Msk

+#define GPIO_ODR_OD13_Pos              (13U)

+#define GPIO_ODR_OD13_Msk              (0x1UL << GPIO_ODR_OD13_Pos)            /*!< 0x00002000 */

+#define GPIO_ODR_OD13                  GPIO_ODR_OD13_Msk

+#define GPIO_ODR_OD14_Pos              (14U)

+#define GPIO_ODR_OD14_Msk              (0x1UL << GPIO_ODR_OD14_Pos)            /*!< 0x00004000 */

+#define GPIO_ODR_OD14                  GPIO_ODR_OD14_Msk

+#define GPIO_ODR_OD15_Pos              (15U)

+#define GPIO_ODR_OD15_Msk              (0x1UL << GPIO_ODR_OD15_Pos)            /*!< 0x00008000 */

+#define GPIO_ODR_OD15                  GPIO_ODR_OD15_Msk

+

+/******************  Bits definition for GPIO_BSRR register  ******************/

+#define GPIO_BSRR_BS0_Pos              (0U)

+#define GPIO_BSRR_BS0_Msk              (0x1UL << GPIO_BSRR_BS0_Pos)            /*!< 0x00000001 */

+#define GPIO_BSRR_BS0                  GPIO_BSRR_BS0_Msk

+#define GPIO_BSRR_BS1_Pos              (1U)

+#define GPIO_BSRR_BS1_Msk              (0x1UL << GPIO_BSRR_BS1_Pos)            /*!< 0x00000002 */

+#define GPIO_BSRR_BS1                  GPIO_BSRR_BS1_Msk

+#define GPIO_BSRR_BS2_Pos              (2U)

+#define GPIO_BSRR_BS2_Msk              (0x1UL << GPIO_BSRR_BS2_Pos)            /*!< 0x00000004 */

+#define GPIO_BSRR_BS2                  GPIO_BSRR_BS2_Msk

+#define GPIO_BSRR_BS3_Pos              (3U)

+#define GPIO_BSRR_BS3_Msk              (0x1UL << GPIO_BSRR_BS3_Pos)            /*!< 0x00000008 */

+#define GPIO_BSRR_BS3                  GPIO_BSRR_BS3_Msk

+#define GPIO_BSRR_BS4_Pos              (4U)

+#define GPIO_BSRR_BS4_Msk              (0x1UL << GPIO_BSRR_BS4_Pos)            /*!< 0x00000010 */

+#define GPIO_BSRR_BS4                  GPIO_BSRR_BS4_Msk

+#define GPIO_BSRR_BS5_Pos              (5U)

+#define GPIO_BSRR_BS5_Msk              (0x1UL << GPIO_BSRR_BS5_Pos)            /*!< 0x00000020 */

+#define GPIO_BSRR_BS5                  GPIO_BSRR_BS5_Msk

+#define GPIO_BSRR_BS6_Pos              (6U)

+#define GPIO_BSRR_BS6_Msk              (0x1UL << GPIO_BSRR_BS6_Pos)            /*!< 0x00000040 */

+#define GPIO_BSRR_BS6                  GPIO_BSRR_BS6_Msk

+#define GPIO_BSRR_BS7_Pos              (7U)

+#define GPIO_BSRR_BS7_Msk              (0x1UL << GPIO_BSRR_BS7_Pos)            /*!< 0x00000080 */

+#define GPIO_BSRR_BS7                  GPIO_BSRR_BS7_Msk

+#define GPIO_BSRR_BS8_Pos              (8U)

+#define GPIO_BSRR_BS8_Msk              (0x1UL << GPIO_BSRR_BS8_Pos)            /*!< 0x00000100 */

+#define GPIO_BSRR_BS8                  GPIO_BSRR_BS8_Msk

+#define GPIO_BSRR_BS9_Pos              (9U)

+#define GPIO_BSRR_BS9_Msk              (0x1UL << GPIO_BSRR_BS9_Pos)            /*!< 0x00000200 */

+#define GPIO_BSRR_BS9                  GPIO_BSRR_BS9_Msk

+#define GPIO_BSRR_BS10_Pos             (10U)

+#define GPIO_BSRR_BS10_Msk             (0x1UL << GPIO_BSRR_BS10_Pos)           /*!< 0x00000400 */

+#define GPIO_BSRR_BS10                 GPIO_BSRR_BS10_Msk

+#define GPIO_BSRR_BS11_Pos             (11U)

+#define GPIO_BSRR_BS11_Msk             (0x1UL << GPIO_BSRR_BS11_Pos)           /*!< 0x00000800 */

+#define GPIO_BSRR_BS11                 GPIO_BSRR_BS11_Msk

+#define GPIO_BSRR_BS12_Pos             (12U)

+#define GPIO_BSRR_BS12_Msk             (0x1UL << GPIO_BSRR_BS12_Pos)           /*!< 0x00001000 */

+#define GPIO_BSRR_BS12                 GPIO_BSRR_BS12_Msk

+#define GPIO_BSRR_BS13_Pos             (13U)

+#define GPIO_BSRR_BS13_Msk             (0x1UL << GPIO_BSRR_BS13_Pos)           /*!< 0x00002000 */

+#define GPIO_BSRR_BS13                 GPIO_BSRR_BS13_Msk

+#define GPIO_BSRR_BS14_Pos             (14U)

+#define GPIO_BSRR_BS14_Msk             (0x1UL << GPIO_BSRR_BS14_Pos)           /*!< 0x00004000 */

+#define GPIO_BSRR_BS14                 GPIO_BSRR_BS14_Msk

+#define GPIO_BSRR_BS15_Pos             (15U)

+#define GPIO_BSRR_BS15_Msk             (0x1UL << GPIO_BSRR_BS15_Pos)           /*!< 0x00008000 */

+#define GPIO_BSRR_BS15                 GPIO_BSRR_BS15_Msk

+#define GPIO_BSRR_BR0_Pos              (16U)

+#define GPIO_BSRR_BR0_Msk              (0x1UL << GPIO_BSRR_BR0_Pos)            /*!< 0x00010000 */

+#define GPIO_BSRR_BR0                  GPIO_BSRR_BR0_Msk

+#define GPIO_BSRR_BR1_Pos              (17U)

+#define GPIO_BSRR_BR1_Msk              (0x1UL << GPIO_BSRR_BR1_Pos)            /*!< 0x00020000 */

+#define GPIO_BSRR_BR1                  GPIO_BSRR_BR1_Msk

+#define GPIO_BSRR_BR2_Pos              (18U)

+#define GPIO_BSRR_BR2_Msk              (0x1UL << GPIO_BSRR_BR2_Pos)            /*!< 0x00040000 */

+#define GPIO_BSRR_BR2                  GPIO_BSRR_BR2_Msk

+#define GPIO_BSRR_BR3_Pos              (19U)

+#define GPIO_BSRR_BR3_Msk              (0x1UL << GPIO_BSRR_BR3_Pos)            /*!< 0x00080000 */

+#define GPIO_BSRR_BR3                  GPIO_BSRR_BR3_Msk

+#define GPIO_BSRR_BR4_Pos              (20U)

+#define GPIO_BSRR_BR4_Msk              (0x1UL << GPIO_BSRR_BR4_Pos)            /*!< 0x00100000 */

+#define GPIO_BSRR_BR4                  GPIO_BSRR_BR4_Msk

+#define GPIO_BSRR_BR5_Pos              (21U)

+#define GPIO_BSRR_BR5_Msk              (0x1UL << GPIO_BSRR_BR5_Pos)            /*!< 0x00200000 */

+#define GPIO_BSRR_BR5                  GPIO_BSRR_BR5_Msk

+#define GPIO_BSRR_BR6_Pos              (22U)

+#define GPIO_BSRR_BR6_Msk              (0x1UL << GPIO_BSRR_BR6_Pos)            /*!< 0x00400000 */

+#define GPIO_BSRR_BR6                  GPIO_BSRR_BR6_Msk

+#define GPIO_BSRR_BR7_Pos              (23U)

+#define GPIO_BSRR_BR7_Msk              (0x1UL << GPIO_BSRR_BR7_Pos)            /*!< 0x00800000 */

+#define GPIO_BSRR_BR7                  GPIO_BSRR_BR7_Msk

+#define GPIO_BSRR_BR8_Pos              (24U)

+#define GPIO_BSRR_BR8_Msk              (0x1UL << GPIO_BSRR_BR8_Pos)            /*!< 0x01000000 */

+#define GPIO_BSRR_BR8                  GPIO_BSRR_BR8_Msk

+#define GPIO_BSRR_BR9_Pos              (25U)

+#define GPIO_BSRR_BR9_Msk              (0x1UL << GPIO_BSRR_BR9_Pos)            /*!< 0x02000000 */

+#define GPIO_BSRR_BR9                  GPIO_BSRR_BR9_Msk

+#define GPIO_BSRR_BR10_Pos             (26U)

+#define GPIO_BSRR_BR10_Msk             (0x1UL << GPIO_BSRR_BR10_Pos)           /*!< 0x04000000 */

+#define GPIO_BSRR_BR10                 GPIO_BSRR_BR10_Msk

+#define GPIO_BSRR_BR11_Pos             (27U)

+#define GPIO_BSRR_BR11_Msk             (0x1UL << GPIO_BSRR_BR11_Pos)           /*!< 0x08000000 */

+#define GPIO_BSRR_BR11                 GPIO_BSRR_BR11_Msk

+#define GPIO_BSRR_BR12_Pos             (28U)

+#define GPIO_BSRR_BR12_Msk             (0x1UL << GPIO_BSRR_BR12_Pos)           /*!< 0x10000000 */

+#define GPIO_BSRR_BR12                 GPIO_BSRR_BR12_Msk

+#define GPIO_BSRR_BR13_Pos             (29U)

+#define GPIO_BSRR_BR13_Msk             (0x1UL << GPIO_BSRR_BR13_Pos)           /*!< 0x20000000 */

+#define GPIO_BSRR_BR13                 GPIO_BSRR_BR13_Msk

+#define GPIO_BSRR_BR14_Pos             (30U)

+#define GPIO_BSRR_BR14_Msk             (0x1UL << GPIO_BSRR_BR14_Pos)           /*!< 0x40000000 */

+#define GPIO_BSRR_BR14                 GPIO_BSRR_BR14_Msk

+#define GPIO_BSRR_BR15_Pos             (31U)

+#define GPIO_BSRR_BR15_Msk             (0x1UL << GPIO_BSRR_BR15_Pos)           /*!< 0x80000000 */

+#define GPIO_BSRR_BR15                 GPIO_BSRR_BR15_Msk

+

+/****************** Bit definition for GPIO_LCKR register *********************/

+#define GPIO_LCKR_LCK0_Pos             (0U)

+#define GPIO_LCKR_LCK0_Msk             (0x1UL << GPIO_LCKR_LCK0_Pos)           /*!< 0x00000001 */

+#define GPIO_LCKR_LCK0                 GPIO_LCKR_LCK0_Msk

+#define GPIO_LCKR_LCK1_Pos             (1U)

+#define GPIO_LCKR_LCK1_Msk             (0x1UL << GPIO_LCKR_LCK1_Pos)           /*!< 0x00000002 */

+#define GPIO_LCKR_LCK1                 GPIO_LCKR_LCK1_Msk

+#define GPIO_LCKR_LCK2_Pos             (2U)

+#define GPIO_LCKR_LCK2_Msk             (0x1UL << GPIO_LCKR_LCK2_Pos)           /*!< 0x00000004 */

+#define GPIO_LCKR_LCK2                 GPIO_LCKR_LCK2_Msk

+#define GPIO_LCKR_LCK3_Pos             (3U)

+#define GPIO_LCKR_LCK3_Msk             (0x1UL << GPIO_LCKR_LCK3_Pos)           /*!< 0x00000008 */

+#define GPIO_LCKR_LCK3                 GPIO_LCKR_LCK3_Msk

+#define GPIO_LCKR_LCK4_Pos             (4U)

+#define GPIO_LCKR_LCK4_Msk             (0x1UL << GPIO_LCKR_LCK4_Pos)           /*!< 0x00000010 */

+#define GPIO_LCKR_LCK4                 GPIO_LCKR_LCK4_Msk

+#define GPIO_LCKR_LCK5_Pos             (5U)

+#define GPIO_LCKR_LCK5_Msk             (0x1UL << GPIO_LCKR_LCK5_Pos)           /*!< 0x00000020 */

+#define GPIO_LCKR_LCK5                 GPIO_LCKR_LCK5_Msk

+#define GPIO_LCKR_LCK6_Pos             (6U)

+#define GPIO_LCKR_LCK6_Msk             (0x1UL << GPIO_LCKR_LCK6_Pos)           /*!< 0x00000040 */

+#define GPIO_LCKR_LCK6                 GPIO_LCKR_LCK6_Msk

+#define GPIO_LCKR_LCK7_Pos             (7U)

+#define GPIO_LCKR_LCK7_Msk             (0x1UL << GPIO_LCKR_LCK7_Pos)           /*!< 0x00000080 */

+#define GPIO_LCKR_LCK7                 GPIO_LCKR_LCK7_Msk

+#define GPIO_LCKR_LCK8_Pos             (8U)

+#define GPIO_LCKR_LCK8_Msk             (0x1UL << GPIO_LCKR_LCK8_Pos)           /*!< 0x00000100 */

+#define GPIO_LCKR_LCK8                 GPIO_LCKR_LCK8_Msk

+#define GPIO_LCKR_LCK9_Pos             (9U)

+#define GPIO_LCKR_LCK9_Msk             (0x1UL << GPIO_LCKR_LCK9_Pos)           /*!< 0x00000200 */

+#define GPIO_LCKR_LCK9                 GPIO_LCKR_LCK9_Msk

+#define GPIO_LCKR_LCK10_Pos            (10U)

+#define GPIO_LCKR_LCK10_Msk            (0x1UL << GPIO_LCKR_LCK10_Pos)          /*!< 0x00000400 */

+#define GPIO_LCKR_LCK10                GPIO_LCKR_LCK10_Msk

+#define GPIO_LCKR_LCK11_Pos            (11U)

+#define GPIO_LCKR_LCK11_Msk            (0x1UL << GPIO_LCKR_LCK11_Pos)          /*!< 0x00000800 */

+#define GPIO_LCKR_LCK11                GPIO_LCKR_LCK11_Msk

+#define GPIO_LCKR_LCK12_Pos            (12U)

+#define GPIO_LCKR_LCK12_Msk            (0x1UL << GPIO_LCKR_LCK12_Pos)          /*!< 0x00001000 */

+#define GPIO_LCKR_LCK12                GPIO_LCKR_LCK12_Msk

+#define GPIO_LCKR_LCK13_Pos            (13U)

+#define GPIO_LCKR_LCK13_Msk            (0x1UL << GPIO_LCKR_LCK13_Pos)          /*!< 0x00002000 */

+#define GPIO_LCKR_LCK13                GPIO_LCKR_LCK13_Msk

+#define GPIO_LCKR_LCK14_Pos            (14U)

+#define GPIO_LCKR_LCK14_Msk            (0x1UL << GPIO_LCKR_LCK14_Pos)          /*!< 0x00004000 */

+#define GPIO_LCKR_LCK14                GPIO_LCKR_LCK14_Msk

+#define GPIO_LCKR_LCK15_Pos            (15U)

+#define GPIO_LCKR_LCK15_Msk            (0x1UL << GPIO_LCKR_LCK15_Pos)          /*!< 0x00008000 */

+#define GPIO_LCKR_LCK15                GPIO_LCKR_LCK15_Msk

+#define GPIO_LCKR_LCKK_Pos             (16U)

+#define GPIO_LCKR_LCKK_Msk             (0x1UL << GPIO_LCKR_LCKK_Pos)           /*!< 0x00010000 */

+#define GPIO_LCKR_LCKK                 GPIO_LCKR_LCKK_Msk

+

+/****************** Bit definition for GPIO_AFRL register  ********************/

+#define GPIO_AFRL_AFSEL0_Pos           (0U)

+#define GPIO_AFRL_AFSEL0_Msk           (0xFUL << GPIO_AFRL_AFSEL0_Pos)         /*!< 0x0000000F */

+#define GPIO_AFRL_AFSEL0               GPIO_AFRL_AFSEL0_Msk

+#define GPIO_AFRL_AFSEL0_0             (0x1UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000001 */

+#define GPIO_AFRL_AFSEL0_1             (0x2UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000002 */

+#define GPIO_AFRL_AFSEL0_2             (0x4UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000004 */

+#define GPIO_AFRL_AFSEL0_3             (0x8UL << GPIO_AFRL_AFSEL0_Pos)          /*!< 0x00000008 */

+#define GPIO_AFRL_AFSEL1_Pos           (4U)

+#define GPIO_AFRL_AFSEL1_Msk           (0xFUL << GPIO_AFRL_AFSEL1_Pos)         /*!< 0x000000F0 */

+#define GPIO_AFRL_AFSEL1               GPIO_AFRL_AFSEL1_Msk

+#define GPIO_AFRL_AFSEL1_0             (0x1UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000010 */

+#define GPIO_AFRL_AFSEL1_1             (0x2UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000020 */

+#define GPIO_AFRL_AFSEL1_2             (0x4UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000040 */

+#define GPIO_AFRL_AFSEL1_3             (0x8UL << GPIO_AFRL_AFSEL1_Pos)          /*!< 0x00000080 */

+#define GPIO_AFRL_AFSEL2_Pos           (8U)

+#define GPIO_AFRL_AFSEL2_Msk           (0xFUL << GPIO_AFRL_AFSEL2_Pos)         /*!< 0x00000F00 */

+#define GPIO_AFRL_AFSEL2               GPIO_AFRL_AFSEL2_Msk

+#define GPIO_AFRL_AFSEL2_0             (0x1UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000100 */

+#define GPIO_AFRL_AFSEL2_1             (0x2UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000200 */

+#define GPIO_AFRL_AFSEL2_2             (0x4UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000400 */

+#define GPIO_AFRL_AFSEL2_3             (0x8UL << GPIO_AFRL_AFSEL2_Pos)          /*!< 0x00000800 */

+#define GPIO_AFRL_AFSEL3_Pos           (12U)

+#define GPIO_AFRL_AFSEL3_Msk           (0xFUL << GPIO_AFRL_AFSEL3_Pos)         /*!< 0x0000F000 */

+#define GPIO_AFRL_AFSEL3               GPIO_AFRL_AFSEL3_Msk

+#define GPIO_AFRL_AFSEL3_0             (0x1UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00001000 */

+#define GPIO_AFRL_AFSEL3_1             (0x2UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00002000 */

+#define GPIO_AFRL_AFSEL3_2             (0x4UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00004000 */

+#define GPIO_AFRL_AFSEL3_3             (0x8UL << GPIO_AFRL_AFSEL3_Pos)          /*!< 0x00008000 */

+#define GPIO_AFRL_AFSEL4_Pos           (16U)

+#define GPIO_AFRL_AFSEL4_Msk           (0xFUL << GPIO_AFRL_AFSEL4_Pos)         /*!< 0x000F0000 */

+#define GPIO_AFRL_AFSEL4               GPIO_AFRL_AFSEL4_Msk

+#define GPIO_AFRL_AFSEL4_0             (0x1UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00010000 */

+#define GPIO_AFRL_AFSEL4_1             (0x2UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00020000 */

+#define GPIO_AFRL_AFSEL4_2             (0x4UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00040000 */

+#define GPIO_AFRL_AFSEL4_3             (0x8UL << GPIO_AFRL_AFSEL4_Pos)          /*!< 0x00080000 */

+#define GPIO_AFRL_AFSEL5_Pos           (20U)

+#define GPIO_AFRL_AFSEL5_Msk           (0xFUL << GPIO_AFRL_AFSEL5_Pos)         /*!< 0x00F00000 */

+#define GPIO_AFRL_AFSEL5               GPIO_AFRL_AFSEL5_Msk

+#define GPIO_AFRL_AFSEL5_0             (0x1UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00100000 */

+#define GPIO_AFRL_AFSEL5_1             (0x2UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00200000 */

+#define GPIO_AFRL_AFSEL5_2             (0x4UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00400000 */

+#define GPIO_AFRL_AFSEL5_3             (0x8UL << GPIO_AFRL_AFSEL5_Pos)          /*!< 0x00800000 */

+#define GPIO_AFRL_AFSEL6_Pos           (24U)

+#define GPIO_AFRL_AFSEL6_Msk           (0xFUL << GPIO_AFRL_AFSEL6_Pos)         /*!< 0x0F000000 */

+#define GPIO_AFRL_AFSEL6               GPIO_AFRL_AFSEL6_Msk

+#define GPIO_AFRL_AFSEL6_0             (0x1UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x01000000 */

+#define GPIO_AFRL_AFSEL6_1             (0x2UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x02000000 */

+#define GPIO_AFRL_AFSEL6_2             (0x4UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x04000000 */

+#define GPIO_AFRL_AFSEL6_3             (0x8UL << GPIO_AFRL_AFSEL6_Pos)          /*!< 0x08000000 */

+#define GPIO_AFRL_AFSEL7_Pos           (28U)

+#define GPIO_AFRL_AFSEL7_Msk           (0xFUL << GPIO_AFRL_AFSEL7_Pos)         /*!< 0xF0000000 */

+#define GPIO_AFRL_AFSEL7               GPIO_AFRL_AFSEL7_Msk

+#define GPIO_AFRL_AFSEL7_0             (0x1UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x10000000 */

+#define GPIO_AFRL_AFSEL7_1             (0x2UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x20000000 */

+#define GPIO_AFRL_AFSEL7_2             (0x4UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x40000000 */

+#define GPIO_AFRL_AFSEL7_3             (0x8UL << GPIO_AFRL_AFSEL7_Pos)          /*!< 0x80000000 */

+

+/* Legacy defines */

+#define GPIO_AFRL_AFRL0                      GPIO_AFRL_AFSEL0

+#define GPIO_AFRL_AFRL1                      GPIO_AFRL_AFSEL1

+#define GPIO_AFRL_AFRL2                      GPIO_AFRL_AFSEL2

+#define GPIO_AFRL_AFRL3                      GPIO_AFRL_AFSEL3

+#define GPIO_AFRL_AFRL4                      GPIO_AFRL_AFSEL4

+#define GPIO_AFRL_AFRL5                      GPIO_AFRL_AFSEL5

+#define GPIO_AFRL_AFRL6                      GPIO_AFRL_AFSEL6

+#define GPIO_AFRL_AFRL7                      GPIO_AFRL_AFSEL7

+

+/****************** Bit definition for GPIO_AFRH register  ********************/

+#define GPIO_AFRH_AFSEL8_Pos           (0U)

+#define GPIO_AFRH_AFSEL8_Msk           (0xFUL << GPIO_AFRH_AFSEL8_Pos)         /*!< 0x0000000F */

+#define GPIO_AFRH_AFSEL8               GPIO_AFRH_AFSEL8_Msk

+#define GPIO_AFRH_AFSEL8_0             (0x1UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000001 */

+#define GPIO_AFRH_AFSEL8_1             (0x2UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000002 */

+#define GPIO_AFRH_AFSEL8_2             (0x4UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000004 */

+#define GPIO_AFRH_AFSEL8_3             (0x8UL << GPIO_AFRH_AFSEL8_Pos)          /*!< 0x00000008 */

+#define GPIO_AFRH_AFSEL9_Pos           (4U)

+#define GPIO_AFRH_AFSEL9_Msk           (0xFUL << GPIO_AFRH_AFSEL9_Pos)         /*!< 0x000000F0 */

+#define GPIO_AFRH_AFSEL9               GPIO_AFRH_AFSEL9_Msk

+#define GPIO_AFRH_AFSEL9_0             (0x1UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000010 */

+#define GPIO_AFRH_AFSEL9_1             (0x2UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000020 */

+#define GPIO_AFRH_AFSEL9_2             (0x4UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000040 */

+#define GPIO_AFRH_AFSEL9_3             (0x8UL << GPIO_AFRH_AFSEL9_Pos)          /*!< 0x00000080 */

+#define GPIO_AFRH_AFSEL10_Pos          (8U)

+#define GPIO_AFRH_AFSEL10_Msk          (0xFUL << GPIO_AFRH_AFSEL10_Pos)        /*!< 0x00000F00 */

+#define GPIO_AFRH_AFSEL10              GPIO_AFRH_AFSEL10_Msk

+#define GPIO_AFRH_AFSEL10_0            (0x1UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000100 */

+#define GPIO_AFRH_AFSEL10_1            (0x2UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000200 */

+#define GPIO_AFRH_AFSEL10_2            (0x4UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000400 */

+#define GPIO_AFRH_AFSEL10_3            (0x8UL << GPIO_AFRH_AFSEL10_Pos)         /*!< 0x00000800 */

+#define GPIO_AFRH_AFSEL11_Pos          (12U)

+#define GPIO_AFRH_AFSEL11_Msk          (0xFUL << GPIO_AFRH_AFSEL11_Pos)        /*!< 0x0000F000 */

+#define GPIO_AFRH_AFSEL11              GPIO_AFRH_AFSEL11_Msk

+#define GPIO_AFRH_AFSEL11_0            (0x1UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00001000 */

+#define GPIO_AFRH_AFSEL11_1            (0x2UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00002000 */

+#define GPIO_AFRH_AFSEL11_2            (0x4UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00004000 */

+#define GPIO_AFRH_AFSEL11_3            (0x8UL << GPIO_AFRH_AFSEL11_Pos)         /*!< 0x00008000 */

+#define GPIO_AFRH_AFSEL12_Pos          (16U)

+#define GPIO_AFRH_AFSEL12_Msk          (0xFUL << GPIO_AFRH_AFSEL12_Pos)        /*!< 0x000F0000 */

+#define GPIO_AFRH_AFSEL12              GPIO_AFRH_AFSEL12_Msk

+#define GPIO_AFRH_AFSEL12_0            (0x1UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00010000 */

+#define GPIO_AFRH_AFSEL12_1            (0x2UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00020000 */

+#define GPIO_AFRH_AFSEL12_2            (0x4UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00040000 */

+#define GPIO_AFRH_AFSEL12_3            (0x8UL << GPIO_AFRH_AFSEL12_Pos)         /*!< 0x00080000 */

+#define GPIO_AFRH_AFSEL13_Pos          (20U)

+#define GPIO_AFRH_AFSEL13_Msk          (0xFUL << GPIO_AFRH_AFSEL13_Pos)        /*!< 0x00F00000 */

+#define GPIO_AFRH_AFSEL13              GPIO_AFRH_AFSEL13_Msk

+#define GPIO_AFRH_AFSEL13_0            (0x1UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00100000 */

+#define GPIO_AFRH_AFSEL13_1            (0x2UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00200000 */

+#define GPIO_AFRH_AFSEL13_2            (0x4UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00400000 */

+#define GPIO_AFRH_AFSEL13_3            (0x8UL << GPIO_AFRH_AFSEL13_Pos)         /*!< 0x00800000 */

+#define GPIO_AFRH_AFSEL14_Pos          (24U)

+#define GPIO_AFRH_AFSEL14_Msk          (0xFUL << GPIO_AFRH_AFSEL14_Pos)        /*!< 0x0F000000 */

+#define GPIO_AFRH_AFSEL14              GPIO_AFRH_AFSEL14_Msk

+#define GPIO_AFRH_AFSEL14_0            (0x1UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x01000000 */

+#define GPIO_AFRH_AFSEL14_1            (0x2UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x02000000 */

+#define GPIO_AFRH_AFSEL14_2            (0x4UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x04000000 */

+#define GPIO_AFRH_AFSEL14_3            (0x8UL << GPIO_AFRH_AFSEL14_Pos)         /*!< 0x08000000 */

+#define GPIO_AFRH_AFSEL15_Pos          (28U)

+#define GPIO_AFRH_AFSEL15_Msk          (0xFUL << GPIO_AFRH_AFSEL15_Pos)        /*!< 0xF0000000 */

+#define GPIO_AFRH_AFSEL15              GPIO_AFRH_AFSEL15_Msk

+#define GPIO_AFRH_AFSEL15_0            (0x1UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x10000000 */

+#define GPIO_AFRH_AFSEL15_1            (0x2UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x20000000 */

+#define GPIO_AFRH_AFSEL15_2            (0x4UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x40000000 */

+#define GPIO_AFRH_AFSEL15_3            (0x8UL << GPIO_AFRH_AFSEL15_Pos)         /*!< 0x80000000 */

+

+/* Legacy defines */

+#define GPIO_AFRH_AFRH0                      GPIO_AFRH_AFSEL8

+#define GPIO_AFRH_AFRH1                      GPIO_AFRH_AFSEL9

+#define GPIO_AFRH_AFRH2                      GPIO_AFRH_AFSEL10

+#define GPIO_AFRH_AFRH3                      GPIO_AFRH_AFSEL11

+#define GPIO_AFRH_AFRH4                      GPIO_AFRH_AFSEL12

+#define GPIO_AFRH_AFRH5                      GPIO_AFRH_AFSEL13

+#define GPIO_AFRH_AFRH6                      GPIO_AFRH_AFSEL14

+#define GPIO_AFRH_AFRH7                      GPIO_AFRH_AFSEL15

+

+/******************************************************************************/

+/*                                                                            */

+/*                        HSEM HW Semaphore                                   */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for HSEM_R register  ********************/

+#define HSEM_R_PROCID_Pos         (0U)

+#define HSEM_R_PROCID_Msk         (0xFFUL << HSEM_R_PROCID_Pos)                /*!< 0x000000FF */

+#define HSEM_R_PROCID             HSEM_R_PROCID_Msk                            /*!<Semaphore ProcessID */

+#define HSEM_R_COREID_Pos         (8U)

+#define HSEM_R_COREID_Msk         (0xFFUL << HSEM_R_COREID_Pos)                /*!< 0x0000FF00 */

+#define HSEM_R_COREID             HSEM_R_COREID_Msk                            /*!<Semaphore CoreID.   */

+#define HSEM_R_LOCK_Pos           (31U)

+#define HSEM_R_LOCK_Msk           (0x1UL << HSEM_R_LOCK_Pos)                   /*!< 0x80000000 */

+#define HSEM_R_LOCK               HSEM_R_LOCK_Msk                              /*!<Lock indication.    */

+

+/********************  Bit definition for HSEM_RLR register  ******************/

+#define HSEM_RLR_PROCID_Pos       (0U)

+#define HSEM_RLR_PROCID_Msk       (0xFFUL << HSEM_RLR_PROCID_Pos)              /*!< 0x000000FF */

+#define HSEM_RLR_PROCID           HSEM_RLR_PROCID_Msk                          /*!<Semaphore ProcessID */

+#define HSEM_RLR_COREID_Pos       (8U)

+#define HSEM_RLR_COREID_Msk       (0xFFUL << HSEM_RLR_COREID_Pos)              /*!< 0x0000FF00 */

+#define HSEM_RLR_COREID           HSEM_RLR_COREID_Msk                          /*!<Semaphore CoreID.   */

+#define HSEM_RLR_LOCK_Pos         (31U)

+#define HSEM_RLR_LOCK_Msk         (0x1UL << HSEM_RLR_LOCK_Pos)                 /*!< 0x80000000 */

+#define HSEM_RLR_LOCK             HSEM_RLR_LOCK_Msk                            /*!<Lock indication.    */

+

+/********************  Bit definition for HSEM_C1IER register  *****************/

+#define HSEM_C1IER_ISE0_Pos       (0U)

+#define HSEM_C1IER_ISE0_Msk       (0x1UL << HSEM_C1IER_ISE0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1IER_ISE0           HSEM_C1IER_ISE0_Msk                          /*!<semaphore 0 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE1_Pos       (1U)

+#define HSEM_C1IER_ISE1_Msk       (0x1UL << HSEM_C1IER_ISE1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1IER_ISE1           HSEM_C1IER_ISE1_Msk                          /*!<semaphore 1 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE2_Pos       (2U)

+#define HSEM_C1IER_ISE2_Msk       (0x1UL << HSEM_C1IER_ISE2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1IER_ISE2           HSEM_C1IER_ISE2_Msk                          /*!<semaphore 2 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE3_Pos       (3U)

+#define HSEM_C1IER_ISE3_Msk       (0x1UL << HSEM_C1IER_ISE3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1IER_ISE3           HSEM_C1IER_ISE3_Msk                          /*!<semaphore 3 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE4_Pos       (4U)

+#define HSEM_C1IER_ISE4_Msk       (0x1UL << HSEM_C1IER_ISE4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1IER_ISE4           HSEM_C1IER_ISE4_Msk                          /*!<semaphore 4 , interrupt 0 enable bit.  */

+#define HSEM_C1IER_ISE5_Pos       (5U)

+#define HSEM_C1IER_ISE5_Msk       (0x1UL << HSEM_C1IER_ISE5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1IER_ISE5           HSEM_C1IER_ISE5_Msk                          /*!<semaphore 5 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE6_Pos       (6U)

+#define HSEM_C1IER_ISE6_Msk       (0x1UL << HSEM_C1IER_ISE6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1IER_ISE6           HSEM_C1IER_ISE6_Msk                          /*!<semaphore 6 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE7_Pos       (7U)

+#define HSEM_C1IER_ISE7_Msk       (0x1UL << HSEM_C1IER_ISE7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1IER_ISE7           HSEM_C1IER_ISE7_Msk                          /*!<semaphore 7 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE8_Pos       (8U)

+#define HSEM_C1IER_ISE8_Msk       (0x1UL << HSEM_C1IER_ISE8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1IER_ISE8           HSEM_C1IER_ISE8_Msk                          /*!<semaphore 8 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE9_Pos       (9U)

+#define HSEM_C1IER_ISE9_Msk       (0x1UL << HSEM_C1IER_ISE9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1IER_ISE9           HSEM_C1IER_ISE9_Msk                          /*!<semaphore 9 interrupt 0 enable bit.    */

+#define HSEM_C1IER_ISE10_Pos      (10U)

+#define HSEM_C1IER_ISE10_Msk      (0x1UL << HSEM_C1IER_ISE10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1IER_ISE10          HSEM_C1IER_ISE10_Msk                         /*!<semaphore 10 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE11_Pos      (11U)

+#define HSEM_C1IER_ISE11_Msk      (0x1UL << HSEM_C1IER_ISE11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1IER_ISE11          HSEM_C1IER_ISE11_Msk                         /*!<semaphore 11 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE12_Pos      (12U)

+#define HSEM_C1IER_ISE12_Msk      (0x1UL << HSEM_C1IER_ISE12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1IER_ISE12          HSEM_C1IER_ISE12_Msk                         /*!<semaphore 12 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE13_Pos      (13U)

+#define HSEM_C1IER_ISE13_Msk      (0x1UL << HSEM_C1IER_ISE13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1IER_ISE13          HSEM_C1IER_ISE13_Msk                         /*!<semaphore 13 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE14_Pos      (14U)

+#define HSEM_C1IER_ISE14_Msk      (0x1UL << HSEM_C1IER_ISE14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1IER_ISE14          HSEM_C1IER_ISE14_Msk                         /*!<semaphore 14 interrupt 0 enable bit.   */

+#define HSEM_C1IER_ISE15_Pos      (15U)

+#define HSEM_C1IER_ISE15_Msk      (0x1UL << HSEM_C1IER_ISE15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1IER_ISE15          HSEM_C1IER_ISE15_Msk                         /*!<semaphore 15 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE16_Pos      (16U)

+#define HSEM_C1IER_ISE16_Msk      (0x1UL << HSEM_C1IER_ISE16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1IER_ISE16          HSEM_C1IER_ISE16_Msk                         /*!<semaphore 16 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE17_Pos      (17U)

+#define HSEM_C1IER_ISE17_Msk      (0x1UL << HSEM_C1IER_ISE17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1IER_ISE17          HSEM_C1IER_ISE17_Msk                         /*!<semaphore 17 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE18_Pos      (18U)

+#define HSEM_C1IER_ISE18_Msk      (0x1UL << HSEM_C1IER_ISE18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1IER_ISE18          HSEM_C1IER_ISE18_Msk                         /*!<semaphore 18 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE19_Pos      (19U)

+#define HSEM_C1IER_ISE19_Msk      (0x1UL << HSEM_C1IER_ISE19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1IER_ISE19          HSEM_C1IER_ISE19_Msk                         /*!<semaphore 19 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE20_Pos      (20U)

+#define HSEM_C1IER_ISE20_Msk      (0x1UL << HSEM_C1IER_ISE20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1IER_ISE20          HSEM_C1IER_ISE20_Msk                         /*!<semaphore 20 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE21_Pos      (21U)

+#define HSEM_C1IER_ISE21_Msk      (0x1UL << HSEM_C1IER_ISE21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1IER_ISE21          HSEM_C1IER_ISE21_Msk                         /*!<semaphore 21 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE22_Pos      (22U)

+#define HSEM_C1IER_ISE22_Msk      (0x1UL << HSEM_C1IER_ISE22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1IER_ISE22          HSEM_C1IER_ISE22_Msk                         /*!<semaphore 22 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE23_Pos      (23U)

+#define HSEM_C1IER_ISE23_Msk      (0x1UL << HSEM_C1IER_ISE23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1IER_ISE23          HSEM_C1IER_ISE23_Msk                         /*!<semaphore 23 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE24_Pos      (24U)

+#define HSEM_C1IER_ISE24_Msk      (0x1UL << HSEM_C1IER_ISE24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1IER_ISE24          HSEM_C1IER_ISE24_Msk                         /*!<semaphore 24 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE25_Pos      (25U)

+#define HSEM_C1IER_ISE25_Msk      (0x1UL << HSEM_C1IER_ISE25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1IER_ISE25          HSEM_C1IER_ISE25_Msk                         /*!<semaphore 25 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE26_Pos      (26U)

+#define HSEM_C1IER_ISE26_Msk      (0x1UL << HSEM_C1IER_ISE26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1IER_ISE26          HSEM_C1IER_ISE26_Msk                         /*!<semaphore 26 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE27_Pos      (27U)

+#define HSEM_C1IER_ISE27_Msk      (0x1UL << HSEM_C1IER_ISE27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1IER_ISE27          HSEM_C1IER_ISE27_Msk                         /*!<semaphore 27 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE28_Pos      (28U)

+#define HSEM_C1IER_ISE28_Msk      (0x1UL << HSEM_C1IER_ISE28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1IER_ISE28          HSEM_C1IER_ISE28_Msk                         /*!<semaphore 28 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE29_Pos      (29U)

+#define HSEM_C1IER_ISE29_Msk      (0x1UL << HSEM_C1IER_ISE29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1IER_ISE29          HSEM_C1IER_ISE29_Msk                         /*!<semaphore 29 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE30_Pos      (30U)

+#define HSEM_C1IER_ISE30_Msk      (0x1UL << HSEM_C1IER_ISE30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1IER_ISE30          HSEM_C1IER_ISE30_Msk                         /*!<semaphore 30 interrupt 0 enable bit. */

+#define HSEM_C1IER_ISE31_Pos      (31U)

+#define HSEM_C1IER_ISE31_Msk      (0x1UL << HSEM_C1IER_ISE31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1IER_ISE31          HSEM_C1IER_ISE31_Msk                         /*!<semaphore 31 interrupt 0 enable bit. */

+

+/********************  Bit definition for HSEM_C1ICR register  *****************/

+#define HSEM_C1ICR_ISC0_Pos       (0U)

+#define HSEM_C1ICR_ISC0_Msk       (0x1UL << HSEM_C1ICR_ISC0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1ICR_ISC0           HSEM_C1ICR_ISC0_Msk                          /*!<semaphore 0 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC1_Pos       (1U)

+#define HSEM_C1ICR_ISC1_Msk       (0x1UL << HSEM_C1ICR_ISC1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1ICR_ISC1           HSEM_C1ICR_ISC1_Msk                          /*!<semaphore 1 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC2_Pos       (2U)

+#define HSEM_C1ICR_ISC2_Msk       (0x1UL << HSEM_C1ICR_ISC2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1ICR_ISC2           HSEM_C1ICR_ISC2_Msk                          /*!<semaphore 2 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC3_Pos       (3U)

+#define HSEM_C1ICR_ISC3_Msk       (0x1UL << HSEM_C1ICR_ISC3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1ICR_ISC3           HSEM_C1ICR_ISC3_Msk                          /*!<semaphore 3 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC4_Pos       (4U)

+#define HSEM_C1ICR_ISC4_Msk       (0x1UL << HSEM_C1ICR_ISC4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1ICR_ISC4           HSEM_C1ICR_ISC4_Msk                          /*!<semaphore 4 , interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC5_Pos       (5U)

+#define HSEM_C1ICR_ISC5_Msk       (0x1UL << HSEM_C1ICR_ISC5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1ICR_ISC5           HSEM_C1ICR_ISC5_Msk                          /*!<semaphore 5 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC6_Pos       (6U)

+#define HSEM_C1ICR_ISC6_Msk       (0x1UL << HSEM_C1ICR_ISC6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1ICR_ISC6           HSEM_C1ICR_ISC6_Msk                          /*!<semaphore 6 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC7_Pos       (7U)

+#define HSEM_C1ICR_ISC7_Msk       (0x1UL << HSEM_C1ICR_ISC7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1ICR_ISC7           HSEM_C1ICR_ISC7_Msk                          /*!<semaphore 7 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC8_Pos       (8U)

+#define HSEM_C1ICR_ISC8_Msk       (0x1UL << HSEM_C1ICR_ISC8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1ICR_ISC8           HSEM_C1ICR_ISC8_Msk                          /*!<semaphore 8 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC9_Pos       (9U)

+#define HSEM_C1ICR_ISC9_Msk       (0x1UL << HSEM_C1ICR_ISC9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1ICR_ISC9           HSEM_C1ICR_ISC9_Msk                          /*!<semaphore 9 interrupt 0 clear bit.  */

+#define HSEM_C1ICR_ISC10_Pos      (10U)

+#define HSEM_C1ICR_ISC10_Msk      (0x1UL << HSEM_C1ICR_ISC10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1ICR_ISC10          HSEM_C1ICR_ISC10_Msk                         /*!<semaphore 10 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC11_Pos      (11U)

+#define HSEM_C1ICR_ISC11_Msk      (0x1UL << HSEM_C1ICR_ISC11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1ICR_ISC11          HSEM_C1ICR_ISC11_Msk                         /*!<semaphore 11 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC12_Pos      (12U)

+#define HSEM_C1ICR_ISC12_Msk      (0x1UL << HSEM_C1ICR_ISC12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1ICR_ISC12          HSEM_C1ICR_ISC12_Msk                         /*!<semaphore 12 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC13_Pos      (13U)

+#define HSEM_C1ICR_ISC13_Msk      (0x1UL << HSEM_C1ICR_ISC13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1ICR_ISC13          HSEM_C1ICR_ISC13_Msk                         /*!<semaphore 13 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC14_Pos      (14U)

+#define HSEM_C1ICR_ISC14_Msk      (0x1UL << HSEM_C1ICR_ISC14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1ICR_ISC14          HSEM_C1ICR_ISC14_Msk                         /*!<semaphore 14 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC15_Pos      (15U)

+#define HSEM_C1ICR_ISC15_Msk      (0x1UL << HSEM_C1ICR_ISC15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1ICR_ISC15          HSEM_C1ICR_ISC15_Msk                         /*!<semaphore 15 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC16_Pos      (16U)

+#define HSEM_C1ICR_ISC16_Msk      (0x1UL << HSEM_C1ICR_ISC16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1ICR_ISC16          HSEM_C1ICR_ISC16_Msk                         /*!<semaphore 16 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC17_Pos      (17U)

+#define HSEM_C1ICR_ISC17_Msk      (0x1UL << HSEM_C1ICR_ISC17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1ICR_ISC17          HSEM_C1ICR_ISC17_Msk                         /*!<semaphore 17 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC18_Pos      (18U)

+#define HSEM_C1ICR_ISC18_Msk      (0x1UL << HSEM_C1ICR_ISC18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1ICR_ISC18          HSEM_C1ICR_ISC18_Msk                         /*!<semaphore 18 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC19_Pos      (19U)

+#define HSEM_C1ICR_ISC19_Msk      (0x1UL << HSEM_C1ICR_ISC19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1ICR_ISC19          HSEM_C1ICR_ISC19_Msk                         /*!<semaphore 19 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC20_Pos      (20U)

+#define HSEM_C1ICR_ISC20_Msk      (0x1UL << HSEM_C1ICR_ISC20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1ICR_ISC20          HSEM_C1ICR_ISC20_Msk                         /*!<semaphore 20 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC21_Pos      (21U)

+#define HSEM_C1ICR_ISC21_Msk      (0x1UL << HSEM_C1ICR_ISC21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1ICR_ISC21          HSEM_C1ICR_ISC21_Msk                         /*!<semaphore 21 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC22_Pos      (22U)

+#define HSEM_C1ICR_ISC22_Msk      (0x1UL << HSEM_C1ICR_ISC22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1ICR_ISC22          HSEM_C1ICR_ISC22_Msk                         /*!<semaphore 22 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC23_Pos      (23U)

+#define HSEM_C1ICR_ISC23_Msk      (0x1UL << HSEM_C1ICR_ISC23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1ICR_ISC23          HSEM_C1ICR_ISC23_Msk                         /*!<semaphore 23 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC24_Pos      (24U)

+#define HSEM_C1ICR_ISC24_Msk      (0x1UL << HSEM_C1ICR_ISC24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1ICR_ISC24          HSEM_C1ICR_ISC24_Msk                         /*!<semaphore 24 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC25_Pos      (25U)

+#define HSEM_C1ICR_ISC25_Msk      (0x1UL << HSEM_C1ICR_ISC25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1ICR_ISC25          HSEM_C1ICR_ISC25_Msk                         /*!<semaphore 25 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC26_Pos      (26U)

+#define HSEM_C1ICR_ISC26_Msk      (0x1UL << HSEM_C1ICR_ISC26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1ICR_ISC26          HSEM_C1ICR_ISC26_Msk                         /*!<semaphore 26 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC27_Pos      (27U)

+#define HSEM_C1ICR_ISC27_Msk      (0x1UL << HSEM_C1ICR_ISC27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1ICR_ISC27          HSEM_C1ICR_ISC27_Msk                         /*!<semaphore 27 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC28_Pos      (28U)

+#define HSEM_C1ICR_ISC28_Msk      (0x1UL << HSEM_C1ICR_ISC28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1ICR_ISC28          HSEM_C1ICR_ISC28_Msk                         /*!<semaphore 28 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC29_Pos      (29U)

+#define HSEM_C1ICR_ISC29_Msk      (0x1UL << HSEM_C1ICR_ISC29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1ICR_ISC29          HSEM_C1ICR_ISC29_Msk                         /*!<semaphore 29 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC30_Pos      (30U)

+#define HSEM_C1ICR_ISC30_Msk      (0x1UL << HSEM_C1ICR_ISC30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1ICR_ISC30          HSEM_C1ICR_ISC30_Msk                         /*!<semaphore 30 interrupt 0 clear bit. */

+#define HSEM_C1ICR_ISC31_Pos      (31U)

+#define HSEM_C1ICR_ISC31_Msk      (0x1UL << HSEM_C1ICR_ISC31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1ICR_ISC31          HSEM_C1ICR_ISC31_Msk                         /*!<semaphore 31 interrupt 0 clear bit. */

+

+/********************  Bit definition for HSEM_C1ISR register  *****************/

+#define HSEM_C1ISR_ISF0_Pos       (0U)

+#define HSEM_C1ISR_ISF0_Msk       (0x1UL << HSEM_C1ISR_ISF0_Pos)               /*!< 0x00000001 */

+#define HSEM_C1ISR_ISF0           HSEM_C1ISR_ISF0_Msk                          /*!<semaphore 0 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF1_Pos       (1U)

+#define HSEM_C1ISR_ISF1_Msk       (0x1UL << HSEM_C1ISR_ISF1_Pos)               /*!< 0x00000002 */

+#define HSEM_C1ISR_ISF1           HSEM_C1ISR_ISF1_Msk                          /*!<semaphore 1 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF2_Pos       (2U)

+#define HSEM_C1ISR_ISF2_Msk       (0x1UL << HSEM_C1ISR_ISF2_Pos)               /*!< 0x00000004 */

+#define HSEM_C1ISR_ISF2           HSEM_C1ISR_ISF2_Msk                          /*!<semaphore 2 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF3_Pos       (3U)

+#define HSEM_C1ISR_ISF3_Msk       (0x1UL << HSEM_C1ISR_ISF3_Pos)               /*!< 0x00000008 */

+#define HSEM_C1ISR_ISF3           HSEM_C1ISR_ISF3_Msk                          /*!<semaphore 3 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF4_Pos       (4U)

+#define HSEM_C1ISR_ISF4_Msk       (0x1UL << HSEM_C1ISR_ISF4_Pos)               /*!< 0x00000010 */

+#define HSEM_C1ISR_ISF4           HSEM_C1ISR_ISF4_Msk                          /*!<semaphore 4 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF5_Pos       (5U)

+#define HSEM_C1ISR_ISF5_Msk       (0x1UL << HSEM_C1ISR_ISF5_Pos)               /*!< 0x00000020 */

+#define HSEM_C1ISR_ISF5           HSEM_C1ISR_ISF5_Msk                          /*!<semaphore 5 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF6_Pos       (6U)

+#define HSEM_C1ISR_ISF6_Msk       (0x1UL << HSEM_C1ISR_ISF6_Pos)               /*!< 0x00000040 */

+#define HSEM_C1ISR_ISF6           HSEM_C1ISR_ISF6_Msk                          /*!<semaphore 6 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF7_Pos       (7U)

+#define HSEM_C1ISR_ISF7_Msk       (0x1UL << HSEM_C1ISR_ISF7_Pos)               /*!< 0x00000080 */

+#define HSEM_C1ISR_ISF7           HSEM_C1ISR_ISF7_Msk                          /*!<semaphore 7 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF8_Pos       (8U)

+#define HSEM_C1ISR_ISF8_Msk       (0x1UL << HSEM_C1ISR_ISF8_Pos)               /*!< 0x00000100 */

+#define HSEM_C1ISR_ISF8           HSEM_C1ISR_ISF8_Msk                          /*!<semaphore 8 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF9_Pos       (9U)

+#define HSEM_C1ISR_ISF9_Msk       (0x1UL << HSEM_C1ISR_ISF9_Pos)               /*!< 0x00000200 */

+#define HSEM_C1ISR_ISF9           HSEM_C1ISR_ISF9_Msk                          /*!<semaphore 9 interrupt 0 status bit.  */

+#define HSEM_C1ISR_ISF10_Pos      (10U)

+#define HSEM_C1ISR_ISF10_Msk      (0x1UL << HSEM_C1ISR_ISF10_Pos)              /*!< 0x00000400 */

+#define HSEM_C1ISR_ISF10          HSEM_C1ISR_ISF10_Msk                         /*!<semaphore 10 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF11_Pos      (11U)

+#define HSEM_C1ISR_ISF11_Msk      (0x1UL << HSEM_C1ISR_ISF11_Pos)              /*!< 0x00000800 */

+#define HSEM_C1ISR_ISF11          HSEM_C1ISR_ISF11_Msk                         /*!<semaphore 11 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF12_Pos      (12U)

+#define HSEM_C1ISR_ISF12_Msk      (0x1UL << HSEM_C1ISR_ISF12_Pos)              /*!< 0x00001000 */

+#define HSEM_C1ISR_ISF12          HSEM_C1ISR_ISF12_Msk                         /*!<semaphore 12 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF13_Pos      (13U)

+#define HSEM_C1ISR_ISF13_Msk      (0x1UL << HSEM_C1ISR_ISF13_Pos)              /*!< 0x00002000 */

+#define HSEM_C1ISR_ISF13          HSEM_C1ISR_ISF13_Msk                         /*!<semaphore 13 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF14_Pos      (14U)

+#define HSEM_C1ISR_ISF14_Msk      (0x1UL << HSEM_C1ISR_ISF14_Pos)              /*!< 0x00004000 */

+#define HSEM_C1ISR_ISF14          HSEM_C1ISR_ISF14_Msk                         /*!<semaphore 14 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF15_Pos      (15U)

+#define HSEM_C1ISR_ISF15_Msk      (0x1UL << HSEM_C1ISR_ISF15_Pos)              /*!< 0x00008000 */

+#define HSEM_C1ISR_ISF15          HSEM_C1ISR_ISF15_Msk                         /*!<semaphore 15 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF16_Pos      (16U)

+#define HSEM_C1ISR_ISF16_Msk      (0x1UL << HSEM_C1ISR_ISF16_Pos)              /*!< 0x00010000 */

+#define HSEM_C1ISR_ISF16          HSEM_C1ISR_ISF16_Msk                         /*!<semaphore 16 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF17_Pos      (17U)

+#define HSEM_C1ISR_ISF17_Msk      (0x1UL << HSEM_C1ISR_ISF17_Pos)              /*!< 0x00020000 */

+#define HSEM_C1ISR_ISF17          HSEM_C1ISR_ISF17_Msk                         /*!<semaphore 17 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF18_Pos      (18U)

+#define HSEM_C1ISR_ISF18_Msk      (0x1UL << HSEM_C1ISR_ISF18_Pos)              /*!< 0x00040000 */

+#define HSEM_C1ISR_ISF18          HSEM_C1ISR_ISF18_Msk                         /*!<semaphore 18 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF19_Pos      (19U)

+#define HSEM_C1ISR_ISF19_Msk      (0x1UL << HSEM_C1ISR_ISF19_Pos)              /*!< 0x00080000 */

+#define HSEM_C1ISR_ISF19          HSEM_C1ISR_ISF19_Msk                         /*!<semaphore 19 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF20_Pos      (20U)

+#define HSEM_C1ISR_ISF20_Msk      (0x1UL << HSEM_C1ISR_ISF20_Pos)              /*!< 0x00100000 */

+#define HSEM_C1ISR_ISF20          HSEM_C1ISR_ISF20_Msk                         /*!<semaphore 20 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF21_Pos      (21U)

+#define HSEM_C1ISR_ISF21_Msk      (0x1UL << HSEM_C1ISR_ISF21_Pos)              /*!< 0x00200000 */

+#define HSEM_C1ISR_ISF21          HSEM_C1ISR_ISF21_Msk                         /*!<semaphore 21 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF22_Pos      (22U)

+#define HSEM_C1ISR_ISF22_Msk      (0x1UL << HSEM_C1ISR_ISF22_Pos)              /*!< 0x00400000 */

+#define HSEM_C1ISR_ISF22          HSEM_C1ISR_ISF22_Msk                         /*!<semaphore 22 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF23_Pos      (23U)

+#define HSEM_C1ISR_ISF23_Msk      (0x1UL << HSEM_C1ISR_ISF23_Pos)              /*!< 0x00800000 */

+#define HSEM_C1ISR_ISF23          HSEM_C1ISR_ISF23_Msk                         /*!<semaphore 23 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF24_Pos      (24U)

+#define HSEM_C1ISR_ISF24_Msk      (0x1UL << HSEM_C1ISR_ISF24_Pos)              /*!< 0x01000000 */

+#define HSEM_C1ISR_ISF24          HSEM_C1ISR_ISF24_Msk                         /*!<semaphore 24 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF25_Pos      (25U)

+#define HSEM_C1ISR_ISF25_Msk      (0x1UL << HSEM_C1ISR_ISF25_Pos)              /*!< 0x02000000 */

+#define HSEM_C1ISR_ISF25          HSEM_C1ISR_ISF25_Msk                         /*!<semaphore 25 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF26_Pos      (26U)

+#define HSEM_C1ISR_ISF26_Msk      (0x1UL << HSEM_C1ISR_ISF26_Pos)              /*!< 0x04000000 */

+#define HSEM_C1ISR_ISF26          HSEM_C1ISR_ISF26_Msk                         /*!<semaphore 26 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF27_Pos      (27U)

+#define HSEM_C1ISR_ISF27_Msk      (0x1UL << HSEM_C1ISR_ISF27_Pos)              /*!< 0x08000000 */

+#define HSEM_C1ISR_ISF27          HSEM_C1ISR_ISF27_Msk                         /*!<semaphore 27 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF28_Pos      (28U)

+#define HSEM_C1ISR_ISF28_Msk      (0x1UL << HSEM_C1ISR_ISF28_Pos)              /*!< 0x10000000 */

+#define HSEM_C1ISR_ISF28          HSEM_C1ISR_ISF28_Msk                         /*!<semaphore 28 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF29_Pos      (29U)

+#define HSEM_C1ISR_ISF29_Msk      (0x1UL << HSEM_C1ISR_ISF29_Pos)              /*!< 0x20000000 */

+#define HSEM_C1ISR_ISF29          HSEM_C1ISR_ISF29_Msk                         /*!<semaphore 29 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF30_Pos      (30U)

+#define HSEM_C1ISR_ISF30_Msk      (0x1UL << HSEM_C1ISR_ISF30_Pos)              /*!< 0x40000000 */

+#define HSEM_C1ISR_ISF30          HSEM_C1ISR_ISF30_Msk                         /*!<semaphore 30 interrupt 0 status bit. */

+#define HSEM_C1ISR_ISF31_Pos      (31U)

+#define HSEM_C1ISR_ISF31_Msk      (0x1UL << HSEM_C1ISR_ISF31_Pos)              /*!< 0x80000000 */

+#define HSEM_C1ISR_ISF31          HSEM_C1ISR_ISF31_Msk                         /*!<semaphore 31 interrupt 0 status bit. */

+

+/********************  Bit definition for HSEM_C1MISR register  *****************/

+#define HSEM_C1MISR_MISF0_Pos     (0U)

+#define HSEM_C1MISR_MISF0_Msk     (0x1UL << HSEM_C1MISR_MISF0_Pos)             /*!< 0x00000001 */

+#define HSEM_C1MISR_MISF0         HSEM_C1MISR_MISF0_Msk                        /*!<semaphore 0 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF1_Pos     (1U)

+#define HSEM_C1MISR_MISF1_Msk     (0x1UL << HSEM_C1MISR_MISF1_Pos)             /*!< 0x00000002 */

+#define HSEM_C1MISR_MISF1         HSEM_C1MISR_MISF1_Msk                        /*!<semaphore 1 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF2_Pos     (2U)

+#define HSEM_C1MISR_MISF2_Msk     (0x1UL << HSEM_C1MISR_MISF2_Pos)             /*!< 0x00000004 */

+#define HSEM_C1MISR_MISF2         HSEM_C1MISR_MISF2_Msk                        /*!<semaphore 2 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF3_Pos     (3U)

+#define HSEM_C1MISR_MISF3_Msk     (0x1UL << HSEM_C1MISR_MISF3_Pos)             /*!< 0x00000008 */

+#define HSEM_C1MISR_MISF3         HSEM_C1MISR_MISF3_Msk                        /*!<semaphore 3 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF4_Pos     (4U)

+#define HSEM_C1MISR_MISF4_Msk     (0x1UL << HSEM_C1MISR_MISF4_Pos)             /*!< 0x00000010 */

+#define HSEM_C1MISR_MISF4         HSEM_C1MISR_MISF4_Msk                        /*!<semaphore 4 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF5_Pos     (5U)

+#define HSEM_C1MISR_MISF5_Msk     (0x1UL << HSEM_C1MISR_MISF5_Pos)             /*!< 0x00000020 */

+#define HSEM_C1MISR_MISF5         HSEM_C1MISR_MISF5_Msk                        /*!<semaphore 5 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF6_Pos     (6U)

+#define HSEM_C1MISR_MISF6_Msk     (0x1UL << HSEM_C1MISR_MISF6_Pos)             /*!< 0x00000040 */

+#define HSEM_C1MISR_MISF6         HSEM_C1MISR_MISF6_Msk                        /*!<semaphore 6 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF7_Pos     (7U)

+#define HSEM_C1MISR_MISF7_Msk     (0x1UL << HSEM_C1MISR_MISF7_Pos)             /*!< 0x00000080 */

+#define HSEM_C1MISR_MISF7         HSEM_C1MISR_MISF7_Msk                        /*!<semaphore 7 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF8_Pos     (8U)

+#define HSEM_C1MISR_MISF8_Msk     (0x1UL << HSEM_C1MISR_MISF8_Pos)             /*!< 0x00000100 */

+#define HSEM_C1MISR_MISF8         HSEM_C1MISR_MISF8_Msk                        /*!<semaphore 8 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF9_Pos     (9U)

+#define HSEM_C1MISR_MISF9_Msk     (0x1UL << HSEM_C1MISR_MISF9_Pos)             /*!< 0x00000200 */

+#define HSEM_C1MISR_MISF9         HSEM_C1MISR_MISF9_Msk                        /*!<semaphore 9 interrupt 0 masked status bit.  */

+#define HSEM_C1MISR_MISF10_Pos    (10U)

+#define HSEM_C1MISR_MISF10_Msk    (0x1UL << HSEM_C1MISR_MISF10_Pos)            /*!< 0x00000400 */

+#define HSEM_C1MISR_MISF10        HSEM_C1MISR_MISF10_Msk                       /*!<semaphore 10 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF11_Pos    (11U)

+#define HSEM_C1MISR_MISF11_Msk    (0x1UL << HSEM_C1MISR_MISF11_Pos)            /*!< 0x00000800 */

+#define HSEM_C1MISR_MISF11        HSEM_C1MISR_MISF11_Msk                       /*!<semaphore 11 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF12_Pos    (12U)

+#define HSEM_C1MISR_MISF12_Msk    (0x1UL << HSEM_C1MISR_MISF12_Pos)            /*!< 0x00001000 */

+#define HSEM_C1MISR_MISF12        HSEM_C1MISR_MISF12_Msk                       /*!<semaphore 12 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF13_Pos    (13U)

+#define HSEM_C1MISR_MISF13_Msk    (0x1UL << HSEM_C1MISR_MISF13_Pos)            /*!< 0x00002000 */

+#define HSEM_C1MISR_MISF13        HSEM_C1MISR_MISF13_Msk                       /*!<semaphore 13 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF14_Pos    (14U)

+#define HSEM_C1MISR_MISF14_Msk    (0x1UL << HSEM_C1MISR_MISF14_Pos)            /*!< 0x00004000 */

+#define HSEM_C1MISR_MISF14        HSEM_C1MISR_MISF14_Msk                       /*!<semaphore 14 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF15_Pos    (15U)

+#define HSEM_C1MISR_MISF15_Msk    (0x1UL << HSEM_C1MISR_MISF15_Pos)            /*!< 0x00008000 */

+#define HSEM_C1MISR_MISF15        HSEM_C1MISR_MISF15_Msk                       /*!<semaphore 15 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF16_Pos    (16U)

+#define HSEM_C1MISR_MISF16_Msk    (0x1UL << HSEM_C1MISR_MISF16_Pos)            /*!< 0x00010000 */

+#define HSEM_C1MISR_MISF16        HSEM_C1MISR_MISF16_Msk                       /*!<semaphore 16 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF17_Pos    (17U)

+#define HSEM_C1MISR_MISF17_Msk    (0x1UL << HSEM_C1MISR_MISF17_Pos)            /*!< 0x00020000 */

+#define HSEM_C1MISR_MISF17        HSEM_C1MISR_MISF17_Msk                       /*!<semaphore 17 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF18_Pos    (18U)

+#define HSEM_C1MISR_MISF18_Msk    (0x1UL << HSEM_C1MISR_MISF18_Pos)            /*!< 0x00040000 */

+#define HSEM_C1MISR_MISF18        HSEM_C1MISR_MISF18_Msk                       /*!<semaphore 18 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF19_Pos    (19U)

+#define HSEM_C1MISR_MISF19_Msk    (0x1UL << HSEM_C1MISR_MISF19_Pos)            /*!< 0x00080000 */

+#define HSEM_C1MISR_MISF19        HSEM_C1MISR_MISF19_Msk                       /*!<semaphore 19 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF20_Pos    (20U)

+#define HSEM_C1MISR_MISF20_Msk    (0x1UL << HSEM_C1MISR_MISF20_Pos)            /*!< 0x00100000 */

+#define HSEM_C1MISR_MISF20        HSEM_C1MISR_MISF20_Msk                       /*!<semaphore 20 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF21_Pos    (21U)

+#define HSEM_C1MISR_MISF21_Msk    (0x1UL << HSEM_C1MISR_MISF21_Pos)            /*!< 0x00200000 */

+#define HSEM_C1MISR_MISF21        HSEM_C1MISR_MISF21_Msk                       /*!<semaphore 21 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF22_Pos    (22U)

+#define HSEM_C1MISR_MISF22_Msk    (0x1UL << HSEM_C1MISR_MISF22_Pos)            /*!< 0x00400000 */

+#define HSEM_C1MISR_MISF22        HSEM_C1MISR_MISF22_Msk                       /*!<semaphore 22 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF23_Pos    (23U)

+#define HSEM_C1MISR_MISF23_Msk    (0x1UL << HSEM_C1MISR_MISF23_Pos)            /*!< 0x00800000 */

+#define HSEM_C1MISR_MISF23        HSEM_C1MISR_MISF23_Msk                       /*!<semaphore 23 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF24_Pos    (24U)

+#define HSEM_C1MISR_MISF24_Msk    (0x1UL << HSEM_C1MISR_MISF24_Pos)            /*!< 0x01000000 */

+#define HSEM_C1MISR_MISF24        HSEM_C1MISR_MISF24_Msk                       /*!<semaphore 24 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF25_Pos    (25U)

+#define HSEM_C1MISR_MISF25_Msk    (0x1UL << HSEM_C1MISR_MISF25_Pos)            /*!< 0x02000000 */

+#define HSEM_C1MISR_MISF25        HSEM_C1MISR_MISF25_Msk                       /*!<semaphore 25 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF26_Pos    (26U)

+#define HSEM_C1MISR_MISF26_Msk    (0x1UL << HSEM_C1MISR_MISF26_Pos)            /*!< 0x04000000 */

+#define HSEM_C1MISR_MISF26        HSEM_C1MISR_MISF26_Msk                       /*!<semaphore 26 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF27_Pos    (27U)

+#define HSEM_C1MISR_MISF27_Msk    (0x1UL << HSEM_C1MISR_MISF27_Pos)            /*!< 0x08000000 */

+#define HSEM_C1MISR_MISF27        HSEM_C1MISR_MISF27_Msk                       /*!<semaphore 27 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF28_Pos    (28U)

+#define HSEM_C1MISR_MISF28_Msk    (0x1UL << HSEM_C1MISR_MISF28_Pos)            /*!< 0x10000000 */

+#define HSEM_C1MISR_MISF28        HSEM_C1MISR_MISF28_Msk                       /*!<semaphore 28 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF29_Pos    (29U)

+#define HSEM_C1MISR_MISF29_Msk    (0x1UL << HSEM_C1MISR_MISF29_Pos)            /*!< 0x20000000 */

+#define HSEM_C1MISR_MISF29        HSEM_C1MISR_MISF29_Msk                       /*!<semaphore 29 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF30_Pos    (30U)

+#define HSEM_C1MISR_MISF30_Msk    (0x1UL << HSEM_C1MISR_MISF30_Pos)            /*!< 0x40000000 */

+#define HSEM_C1MISR_MISF30        HSEM_C1MISR_MISF30_Msk                       /*!<semaphore 30 interrupt 0 masked status bit. */

+#define HSEM_C1MISR_MISF31_Pos    (31U)

+#define HSEM_C1MISR_MISF31_Msk    (0x1UL << HSEM_C1MISR_MISF31_Pos)            /*!< 0x80000000 */

+#define HSEM_C1MISR_MISF31        HSEM_C1MISR_MISF31_Msk                       /*!<semaphore 31 interrupt 0 masked status bit. */

+

+/********************  Bit definition for HSEM_CR register  *****************/

+#define HSEM_CR_COREID_Pos        (8U)

+#define HSEM_CR_COREID_Msk        (0xFFUL << HSEM_CR_COREID_Pos)               /*!< 0x0000FF00 */

+#define HSEM_CR_COREID            HSEM_CR_COREID_Msk                           /*!<CoreID of semaphores to be cleared. */

+#define HSEM_CR_KEY_Pos           (16U)

+#define HSEM_CR_KEY_Msk           (0xFFFFUL << HSEM_CR_KEY_Pos)                /*!< 0xFFFF0000 */

+#define HSEM_CR_KEY               HSEM_CR_KEY_Msk                              /*!<semaphores clear key. */

+

+/********************  Bit definition for HSEM_KEYR register  *****************/

+#define HSEM_KEYR_KEY_Pos         (16U)

+#define HSEM_KEYR_KEY_Msk         (0xFFFFUL << HSEM_KEYR_KEY_Pos)              /*!< 0xFFFF0000 */

+#define HSEM_KEYR_KEY             HSEM_KEYR_KEY_Msk                            /*!<semaphores clear key. */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    HASH                                    */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bits definition for HASH_CR register  ********************/

+#define HASH_CR_INIT_Pos          (2U)

+#define HASH_CR_INIT_Msk          (0x1UL << HASH_CR_INIT_Pos)                  /*!< 0x00000004 */

+#define HASH_CR_INIT              HASH_CR_INIT_Msk

+#define HASH_CR_DMAE_Pos          (3U)

+#define HASH_CR_DMAE_Msk          (0x1UL << HASH_CR_DMAE_Pos)                  /*!< 0x00000008 */

+#define HASH_CR_DMAE              HASH_CR_DMAE_Msk

+#define HASH_CR_DATATYPE_Pos      (4U)

+#define HASH_CR_DATATYPE_Msk      (0x3UL << HASH_CR_DATATYPE_Pos)              /*!< 0x00000030 */

+#define HASH_CR_DATATYPE          HASH_CR_DATATYPE_Msk

+#define HASH_CR_DATATYPE_0        (0x1UL << HASH_CR_DATATYPE_Pos)               /*!< 0x00000010 */

+#define HASH_CR_DATATYPE_1        (0x2UL << HASH_CR_DATATYPE_Pos)               /*!< 0x00000020 */

+#define HASH_CR_MODE_Pos          (6U)

+#define HASH_CR_MODE_Msk          (0x1UL << HASH_CR_MODE_Pos)                  /*!< 0x00000040 */

+#define HASH_CR_MODE              HASH_CR_MODE_Msk

+#define HASH_CR_ALGO_Pos          (7U)

+#define HASH_CR_ALGO_Msk          (0x801UL << HASH_CR_ALGO_Pos)                /*!< 0x00040080 */

+#define HASH_CR_ALGO              HASH_CR_ALGO_Msk

+#define HASH_CR_ALGO_0            (0x001UL << HASH_CR_ALGO_Pos)                 /*!< 0x00000080 */

+#define HASH_CR_ALGO_1            (0x800UL << HASH_CR_ALGO_Pos)                 /*!< 0x00040000 */

+#define HASH_CR_NBW_Pos           (8U)

+#define HASH_CR_NBW_Msk           (0xFUL << HASH_CR_NBW_Pos)                   /*!< 0x00000F00 */

+#define HASH_CR_NBW               HASH_CR_NBW_Msk

+#define HASH_CR_NBW_0             (0x1UL << HASH_CR_NBW_Pos)                    /*!< 0x00000100 */

+#define HASH_CR_NBW_1             (0x2UL << HASH_CR_NBW_Pos)                    /*!< 0x00000200 */

+#define HASH_CR_NBW_2             (0x4UL << HASH_CR_NBW_Pos)                    /*!< 0x00000400 */

+#define HASH_CR_NBW_3             (0x8UL << HASH_CR_NBW_Pos)                    /*!< 0x00000800 */

+#define HASH_CR_DINNE_Pos         (12U)

+#define HASH_CR_DINNE_Msk         (0x1UL << HASH_CR_DINNE_Pos)                 /*!< 0x00001000 */

+#define HASH_CR_DINNE             HASH_CR_DINNE_Msk

+#define HASH_CR_MDMAT_Pos         (13U)

+#define HASH_CR_MDMAT_Msk         (0x1UL << HASH_CR_MDMAT_Pos)                 /*!< 0x00002000 */

+#define HASH_CR_MDMAT             HASH_CR_MDMAT_Msk

+#define HASH_CR_LKEY_Pos          (16U)

+#define HASH_CR_LKEY_Msk          (0x1UL << HASH_CR_LKEY_Pos)                  /*!< 0x00010000 */

+#define HASH_CR_LKEY              HASH_CR_LKEY_Msk

+

+/******************  Bits definition for HASH_STR register  *******************/

+#define HASH_STR_NBLW_Pos         (0U)

+#define HASH_STR_NBLW_Msk         (0x1FUL << HASH_STR_NBLW_Pos)                /*!< 0x0000001F */

+#define HASH_STR_NBLW             HASH_STR_NBLW_Msk

+#define HASH_STR_NBLW_0           (0x01UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000001 */

+#define HASH_STR_NBLW_1           (0x02UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000002 */

+#define HASH_STR_NBLW_2           (0x04UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000004 */

+#define HASH_STR_NBLW_3           (0x08UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000008 */

+#define HASH_STR_NBLW_4           (0x10UL << HASH_STR_NBLW_Pos)                 /*!< 0x00000010 */

+#define HASH_STR_DCAL_Pos         (8U)

+#define HASH_STR_DCAL_Msk         (0x1UL << HASH_STR_DCAL_Pos)                 /*!< 0x00000100 */

+#define HASH_STR_DCAL             HASH_STR_DCAL_Msk

+

+/******************  Bits definition for HASH_IMR register  *******************/

+#define HASH_IMR_DINIE_Pos        (0U)

+#define HASH_IMR_DINIE_Msk        (0x1UL << HASH_IMR_DINIE_Pos)                /*!< 0x00000001 */

+#define HASH_IMR_DINIE            HASH_IMR_DINIE_Msk

+#define HASH_IMR_DCIE_Pos         (1U)

+#define HASH_IMR_DCIE_Msk         (0x1UL << HASH_IMR_DCIE_Pos)                 /*!< 0x00000002 */

+#define HASH_IMR_DCIE             HASH_IMR_DCIE_Msk

+

+/******************  Bits definition for HASH_SR register  ********************/

+#define HASH_SR_DINIS_Pos         (0U)

+#define HASH_SR_DINIS_Msk         (0x1UL << HASH_SR_DINIS_Pos)                 /*!< 0x00000001 */

+#define HASH_SR_DINIS             HASH_SR_DINIS_Msk

+#define HASH_SR_DCIS_Pos          (1U)

+#define HASH_SR_DCIS_Msk          (0x1UL << HASH_SR_DCIS_Pos)                  /*!< 0x00000002 */

+#define HASH_SR_DCIS              HASH_SR_DCIS_Msk

+#define HASH_SR_DMAS_Pos          (2U)

+#define HASH_SR_DMAS_Msk          (0x1UL << HASH_SR_DMAS_Pos)                  /*!< 0x00000004 */

+#define HASH_SR_DMAS              HASH_SR_DMAS_Msk

+#define HASH_SR_BUSY_Pos          (3U)

+#define HASH_SR_BUSY_Msk          (0x1UL << HASH_SR_BUSY_Pos)                  /*!< 0x00000008 */

+#define HASH_SR_BUSY              HASH_SR_BUSY_Msk

+/******************************************************************************/

+/*                                                                            */

+/*                      Inter-integrated Circuit Interface (I2C)              */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for I2C_CR1 register  *******************/

+#define I2C_CR1_PE_Pos               (0U)

+#define I2C_CR1_PE_Msk               (0x1UL << I2C_CR1_PE_Pos)                 /*!< 0x00000001 */

+#define I2C_CR1_PE                   I2C_CR1_PE_Msk                            /*!< Peripheral enable */

+#define I2C_CR1_TXIE_Pos             (1U)

+#define I2C_CR1_TXIE_Msk             (0x1UL << I2C_CR1_TXIE_Pos)               /*!< 0x00000002 */

+#define I2C_CR1_TXIE                 I2C_CR1_TXIE_Msk                          /*!< TX interrupt enable */

+#define I2C_CR1_RXIE_Pos             (2U)

+#define I2C_CR1_RXIE_Msk             (0x1UL << I2C_CR1_RXIE_Pos)               /*!< 0x00000004 */

+#define I2C_CR1_RXIE                 I2C_CR1_RXIE_Msk                          /*!< RX interrupt enable */

+#define I2C_CR1_ADDRIE_Pos           (3U)

+#define I2C_CR1_ADDRIE_Msk           (0x1UL << I2C_CR1_ADDRIE_Pos)             /*!< 0x00000008 */

+#define I2C_CR1_ADDRIE               I2C_CR1_ADDRIE_Msk                        /*!< Address match interrupt enable */

+#define I2C_CR1_NACKIE_Pos           (4U)

+#define I2C_CR1_NACKIE_Msk           (0x1UL << I2C_CR1_NACKIE_Pos)             /*!< 0x00000010 */

+#define I2C_CR1_NACKIE               I2C_CR1_NACKIE_Msk                        /*!< NACK received interrupt enable */

+#define I2C_CR1_STOPIE_Pos           (5U)

+#define I2C_CR1_STOPIE_Msk           (0x1UL << I2C_CR1_STOPIE_Pos)             /*!< 0x00000020 */

+#define I2C_CR1_STOPIE               I2C_CR1_STOPIE_Msk                        /*!< STOP detection interrupt enable */

+#define I2C_CR1_TCIE_Pos             (6U)

+#define I2C_CR1_TCIE_Msk             (0x1UL << I2C_CR1_TCIE_Pos)               /*!< 0x00000040 */

+#define I2C_CR1_TCIE                 I2C_CR1_TCIE_Msk                          /*!< Transfer complete interrupt enable */

+#define I2C_CR1_ERRIE_Pos            (7U)

+#define I2C_CR1_ERRIE_Msk            (0x1UL << I2C_CR1_ERRIE_Pos)              /*!< 0x00000080 */

+#define I2C_CR1_ERRIE                I2C_CR1_ERRIE_Msk                         /*!< Errors interrupt enable */

+#define I2C_CR1_DNF_Pos              (8U)

+#define I2C_CR1_DNF_Msk              (0xFUL << I2C_CR1_DNF_Pos)                /*!< 0x00000F00 */

+#define I2C_CR1_DNF                  I2C_CR1_DNF_Msk                           /*!< Digital noise filter */

+#define I2C_CR1_ANFOFF_Pos           (12U)

+#define I2C_CR1_ANFOFF_Msk           (0x1UL << I2C_CR1_ANFOFF_Pos)             /*!< 0x00001000 */

+#define I2C_CR1_ANFOFF               I2C_CR1_ANFOFF_Msk                        /*!< Analog noise filter OFF */

+#define I2C_CR1_TXDMAEN_Pos          (14U)

+#define I2C_CR1_TXDMAEN_Msk          (0x1UL << I2C_CR1_TXDMAEN_Pos)            /*!< 0x00004000 */

+#define I2C_CR1_TXDMAEN              I2C_CR1_TXDMAEN_Msk                       /*!< DMA transmission requests enable */

+#define I2C_CR1_RXDMAEN_Pos          (15U)

+#define I2C_CR1_RXDMAEN_Msk          (0x1UL << I2C_CR1_RXDMAEN_Pos)            /*!< 0x00008000 */

+#define I2C_CR1_RXDMAEN              I2C_CR1_RXDMAEN_Msk                       /*!< DMA reception requests enable */

+#define I2C_CR1_SBC_Pos              (16U)

+#define I2C_CR1_SBC_Msk              (0x1UL << I2C_CR1_SBC_Pos)                /*!< 0x00010000 */

+#define I2C_CR1_SBC                  I2C_CR1_SBC_Msk                           /*!< Slave byte control */

+#define I2C_CR1_NOSTRETCH_Pos        (17U)

+#define I2C_CR1_NOSTRETCH_Msk        (0x1UL << I2C_CR1_NOSTRETCH_Pos)          /*!< 0x00020000 */

+#define I2C_CR1_NOSTRETCH            I2C_CR1_NOSTRETCH_Msk                     /*!< Clock stretching disable */

+#define I2C_CR1_WUPEN_Pos            (18U)

+#define I2C_CR1_WUPEN_Msk            (0x1UL << I2C_CR1_WUPEN_Pos)              /*!< 0x00040000 */

+#define I2C_CR1_WUPEN                I2C_CR1_WUPEN_Msk                         /*!< Wakeup from STOP enable */

+#define I2C_CR1_GCEN_Pos             (19U)

+#define I2C_CR1_GCEN_Msk             (0x1UL << I2C_CR1_GCEN_Pos)               /*!< 0x00080000 */

+#define I2C_CR1_GCEN                 I2C_CR1_GCEN_Msk                          /*!< General call enable */

+#define I2C_CR1_SMBHEN_Pos           (20U)

+#define I2C_CR1_SMBHEN_Msk           (0x1UL << I2C_CR1_SMBHEN_Pos)             /*!< 0x00100000 */

+#define I2C_CR1_SMBHEN               I2C_CR1_SMBHEN_Msk                        /*!< SMBus host address enable */

+#define I2C_CR1_SMBDEN_Pos           (21U)

+#define I2C_CR1_SMBDEN_Msk           (0x1UL << I2C_CR1_SMBDEN_Pos)             /*!< 0x00200000 */

+#define I2C_CR1_SMBDEN               I2C_CR1_SMBDEN_Msk                        /*!< SMBus device default address enable */

+#define I2C_CR1_ALERTEN_Pos          (22U)

+#define I2C_CR1_ALERTEN_Msk          (0x1UL << I2C_CR1_ALERTEN_Pos)            /*!< 0x00400000 */

+#define I2C_CR1_ALERTEN              I2C_CR1_ALERTEN_Msk                       /*!< SMBus alert enable */

+#define I2C_CR1_PECEN_Pos            (23U)

+#define I2C_CR1_PECEN_Msk            (0x1UL << I2C_CR1_PECEN_Pos)              /*!< 0x00800000 */

+#define I2C_CR1_PECEN                I2C_CR1_PECEN_Msk                         /*!< PEC enable */

+

+/******************  Bit definition for I2C_CR2 register  ********************/

+#define I2C_CR2_SADD_Pos             (0U)

+#define I2C_CR2_SADD_Msk             (0x3FFUL << I2C_CR2_SADD_Pos)             /*!< 0x000003FF */

+#define I2C_CR2_SADD                 I2C_CR2_SADD_Msk                          /*!< Slave address (master mode) */

+#define I2C_CR2_RD_WRN_Pos           (10U)

+#define I2C_CR2_RD_WRN_Msk           (0x1UL << I2C_CR2_RD_WRN_Pos)             /*!< 0x00000400 */

+#define I2C_CR2_RD_WRN               I2C_CR2_RD_WRN_Msk                        /*!< Transfer direction (master mode) */

+#define I2C_CR2_ADD10_Pos            (11U)

+#define I2C_CR2_ADD10_Msk            (0x1UL << I2C_CR2_ADD10_Pos)              /*!< 0x00000800 */

+#define I2C_CR2_ADD10                I2C_CR2_ADD10_Msk                         /*!< 10-bit addressing mode (master mode) */

+#define I2C_CR2_HEAD10R_Pos          (12U)

+#define I2C_CR2_HEAD10R_Msk          (0x1UL << I2C_CR2_HEAD10R_Pos)            /*!< 0x00001000 */

+#define I2C_CR2_HEAD10R              I2C_CR2_HEAD10R_Msk                       /*!< 10-bit address header only read direction (master mode) */

+#define I2C_CR2_START_Pos            (13U)

+#define I2C_CR2_START_Msk            (0x1UL << I2C_CR2_START_Pos)              /*!< 0x00002000 */

+#define I2C_CR2_START                I2C_CR2_START_Msk                         /*!< START generation */

+#define I2C_CR2_STOP_Pos             (14U)

+#define I2C_CR2_STOP_Msk             (0x1UL << I2C_CR2_STOP_Pos)               /*!< 0x00004000 */

+#define I2C_CR2_STOP                 I2C_CR2_STOP_Msk                          /*!< STOP generation (master mode) */

+#define I2C_CR2_NACK_Pos             (15U)

+#define I2C_CR2_NACK_Msk             (0x1UL << I2C_CR2_NACK_Pos)               /*!< 0x00008000 */

+#define I2C_CR2_NACK                 I2C_CR2_NACK_Msk                          /*!< NACK generation (slave mode) */

+#define I2C_CR2_NBYTES_Pos           (16U)

+#define I2C_CR2_NBYTES_Msk           (0xFFUL << I2C_CR2_NBYTES_Pos)            /*!< 0x00FF0000 */

+#define I2C_CR2_NBYTES               I2C_CR2_NBYTES_Msk                        /*!< Number of bytes */

+#define I2C_CR2_RELOAD_Pos           (24U)

+#define I2C_CR2_RELOAD_Msk           (0x1UL << I2C_CR2_RELOAD_Pos)             /*!< 0x01000000 */

+#define I2C_CR2_RELOAD               I2C_CR2_RELOAD_Msk                        /*!< NBYTES reload mode */

+#define I2C_CR2_AUTOEND_Pos          (25U)

+#define I2C_CR2_AUTOEND_Msk          (0x1UL << I2C_CR2_AUTOEND_Pos)            /*!< 0x02000000 */

+#define I2C_CR2_AUTOEND              I2C_CR2_AUTOEND_Msk                       /*!< Automatic end mode (master mode) */

+#define I2C_CR2_PECBYTE_Pos          (26U)

+#define I2C_CR2_PECBYTE_Msk          (0x1UL << I2C_CR2_PECBYTE_Pos)            /*!< 0x04000000 */

+#define I2C_CR2_PECBYTE              I2C_CR2_PECBYTE_Msk                       /*!< Packet error checking byte */

+

+/*******************  Bit definition for I2C_OAR1 register  ******************/

+#define I2C_OAR1_OA1_Pos             (0U)

+#define I2C_OAR1_OA1_Msk             (0x3FFUL << I2C_OAR1_OA1_Pos)             /*!< 0x000003FF */

+#define I2C_OAR1_OA1                 I2C_OAR1_OA1_Msk                          /*!< Interface own address 1 */

+#define I2C_OAR1_OA1MODE_Pos         (10U)

+#define I2C_OAR1_OA1MODE_Msk         (0x1UL << I2C_OAR1_OA1MODE_Pos)           /*!< 0x00000400 */

+#define I2C_OAR1_OA1MODE             I2C_OAR1_OA1MODE_Msk                      /*!< Own address 1 10-bit mode */

+#define I2C_OAR1_OA1EN_Pos           (15U)

+#define I2C_OAR1_OA1EN_Msk           (0x1UL << I2C_OAR1_OA1EN_Pos)             /*!< 0x00008000 */

+#define I2C_OAR1_OA1EN               I2C_OAR1_OA1EN_Msk                        /*!< Own address 1 enable */

+

+/*******************  Bit definition for I2C_OAR2 register  ******************/

+#define I2C_OAR2_OA2_Pos             (1U)

+#define I2C_OAR2_OA2_Msk             (0x7FUL << I2C_OAR2_OA2_Pos)              /*!< 0x000000FE */

+#define I2C_OAR2_OA2                 I2C_OAR2_OA2_Msk                          /*!< Interface own address 2 */

+#define I2C_OAR2_OA2MSK_Pos          (8U)

+#define I2C_OAR2_OA2MSK_Msk          (0x7UL << I2C_OAR2_OA2MSK_Pos)            /*!< 0x00000700 */

+#define I2C_OAR2_OA2MSK              I2C_OAR2_OA2MSK_Msk                       /*!< Own address 2 masks */

+#define I2C_OAR2_OA2NOMASK           0x00000000UL                              /*!< No mask */

+#define I2C_OAR2_OA2MASK01_Pos       (8U)

+#define I2C_OAR2_OA2MASK01_Msk       (0x1UL << I2C_OAR2_OA2MASK01_Pos)         /*!< 0x00000100 */

+#define I2C_OAR2_OA2MASK01           I2C_OAR2_OA2MASK01_Msk                    /*!< OA2[1] is masked, Only OA2[7:2] are compared */

+#define I2C_OAR2_OA2MASK02_Pos       (9U)

+#define I2C_OAR2_OA2MASK02_Msk       (0x1UL << I2C_OAR2_OA2MASK02_Pos)         /*!< 0x00000200 */

+#define I2C_OAR2_OA2MASK02           I2C_OAR2_OA2MASK02_Msk                    /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */

+#define I2C_OAR2_OA2MASK03_Pos       (8U)

+#define I2C_OAR2_OA2MASK03_Msk       (0x3UL << I2C_OAR2_OA2MASK03_Pos)         /*!< 0x00000300 */

+#define I2C_OAR2_OA2MASK03           I2C_OAR2_OA2MASK03_Msk                    /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */

+#define I2C_OAR2_OA2MASK04_Pos       (10U)

+#define I2C_OAR2_OA2MASK04_Msk       (0x1UL << I2C_OAR2_OA2MASK04_Pos)         /*!< 0x00000400 */

+#define I2C_OAR2_OA2MASK04           I2C_OAR2_OA2MASK04_Msk                    /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */

+#define I2C_OAR2_OA2MASK05_Pos       (8U)

+#define I2C_OAR2_OA2MASK05_Msk       (0x5UL << I2C_OAR2_OA2MASK05_Pos)         /*!< 0x00000500 */

+#define I2C_OAR2_OA2MASK05           I2C_OAR2_OA2MASK05_Msk                    /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */

+#define I2C_OAR2_OA2MASK06_Pos       (9U)

+#define I2C_OAR2_OA2MASK06_Msk       (0x3UL << I2C_OAR2_OA2MASK06_Pos)         /*!< 0x00000600 */

+#define I2C_OAR2_OA2MASK06           I2C_OAR2_OA2MASK06_Msk                    /*!< OA2[6:1] is masked, Only OA2[7] are compared */

+#define I2C_OAR2_OA2MASK07_Pos       (8U)

+#define I2C_OAR2_OA2MASK07_Msk       (0x7UL << I2C_OAR2_OA2MASK07_Pos)         /*!< 0x00000700 */

+#define I2C_OAR2_OA2MASK07           I2C_OAR2_OA2MASK07_Msk                    /*!< OA2[7:1] is masked, No comparison is done */

+#define I2C_OAR2_OA2EN_Pos           (15U)

+#define I2C_OAR2_OA2EN_Msk           (0x1UL << I2C_OAR2_OA2EN_Pos)             /*!< 0x00008000 */

+#define I2C_OAR2_OA2EN               I2C_OAR2_OA2EN_Msk                        /*!< Own address 2 enable */

+

+/*******************  Bit definition for I2C_TIMINGR register *******************/

+#define I2C_TIMINGR_SCLL_Pos         (0U)

+#define I2C_TIMINGR_SCLL_Msk         (0xFFUL << I2C_TIMINGR_SCLL_Pos)          /*!< 0x000000FF */

+#define I2C_TIMINGR_SCLL             I2C_TIMINGR_SCLL_Msk                      /*!< SCL low period (master mode) */

+#define I2C_TIMINGR_SCLH_Pos         (8U)

+#define I2C_TIMINGR_SCLH_Msk         (0xFFUL << I2C_TIMINGR_SCLH_Pos)          /*!< 0x0000FF00 */

+#define I2C_TIMINGR_SCLH             I2C_TIMINGR_SCLH_Msk                      /*!< SCL high period (master mode) */

+#define I2C_TIMINGR_SDADEL_Pos       (16U)

+#define I2C_TIMINGR_SDADEL_Msk       (0xFUL << I2C_TIMINGR_SDADEL_Pos)         /*!< 0x000F0000 */

+#define I2C_TIMINGR_SDADEL           I2C_TIMINGR_SDADEL_Msk                    /*!< Data hold time */

+#define I2C_TIMINGR_SCLDEL_Pos       (20U)

+#define I2C_TIMINGR_SCLDEL_Msk       (0xFUL << I2C_TIMINGR_SCLDEL_Pos)         /*!< 0x00F00000 */

+#define I2C_TIMINGR_SCLDEL           I2C_TIMINGR_SCLDEL_Msk                    /*!< Data setup time */

+#define I2C_TIMINGR_PRESC_Pos        (28U)

+#define I2C_TIMINGR_PRESC_Msk        (0xFUL << I2C_TIMINGR_PRESC_Pos)          /*!< 0xF0000000 */

+#define I2C_TIMINGR_PRESC            I2C_TIMINGR_PRESC_Msk                     /*!< Timings prescaler */

+

+/******************* Bit definition for I2C_TIMEOUTR register *******************/

+#define I2C_TIMEOUTR_TIMEOUTA_Pos    (0U)

+#define I2C_TIMEOUTR_TIMEOUTA_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos)    /*!< 0x00000FFF */

+#define I2C_TIMEOUTR_TIMEOUTA        I2C_TIMEOUTR_TIMEOUTA_Msk                 /*!< Bus timeout A */

+#define I2C_TIMEOUTR_TIDLE_Pos       (12U)

+#define I2C_TIMEOUTR_TIDLE_Msk       (0x1UL << I2C_TIMEOUTR_TIDLE_Pos)         /*!< 0x00001000 */

+#define I2C_TIMEOUTR_TIDLE           I2C_TIMEOUTR_TIDLE_Msk                    /*!< Idle clock timeout detection */

+#define I2C_TIMEOUTR_TIMOUTEN_Pos    (15U)

+#define I2C_TIMEOUTR_TIMOUTEN_Msk    (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos)      /*!< 0x00008000 */

+#define I2C_TIMEOUTR_TIMOUTEN        I2C_TIMEOUTR_TIMOUTEN_Msk                 /*!< Clock timeout enable */

+#define I2C_TIMEOUTR_TIMEOUTB_Pos    (16U)

+#define I2C_TIMEOUTR_TIMEOUTB_Msk    (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos)    /*!< 0x0FFF0000 */

+#define I2C_TIMEOUTR_TIMEOUTB        I2C_TIMEOUTR_TIMEOUTB_Msk                 /*!< Bus timeout B*/

+#define I2C_TIMEOUTR_TEXTEN_Pos      (31U)

+#define I2C_TIMEOUTR_TEXTEN_Msk      (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos)        /*!< 0x80000000 */

+#define I2C_TIMEOUTR_TEXTEN          I2C_TIMEOUTR_TEXTEN_Msk                   /*!< Extended clock timeout enable */

+

+/******************  Bit definition for I2C_ISR register  *********************/

+#define I2C_ISR_TXE_Pos              (0U)

+#define I2C_ISR_TXE_Msk              (0x1UL << I2C_ISR_TXE_Pos)                /*!< 0x00000001 */

+#define I2C_ISR_TXE                  I2C_ISR_TXE_Msk                           /*!< Transmit data register empty */

+#define I2C_ISR_TXIS_Pos             (1U)

+#define I2C_ISR_TXIS_Msk             (0x1UL << I2C_ISR_TXIS_Pos)               /*!< 0x00000002 */

+#define I2C_ISR_TXIS                 I2C_ISR_TXIS_Msk                          /*!< Transmit interrupt status */

+#define I2C_ISR_RXNE_Pos             (2U)

+#define I2C_ISR_RXNE_Msk             (0x1UL << I2C_ISR_RXNE_Pos)               /*!< 0x00000004 */

+#define I2C_ISR_RXNE                 I2C_ISR_RXNE_Msk                          /*!< Receive data register not empty */

+#define I2C_ISR_ADDR_Pos             (3U)

+#define I2C_ISR_ADDR_Msk             (0x1UL << I2C_ISR_ADDR_Pos)               /*!< 0x00000008 */

+#define I2C_ISR_ADDR                 I2C_ISR_ADDR_Msk                          /*!< Address matched (slave mode)*/

+#define I2C_ISR_NACKF_Pos            (4U)

+#define I2C_ISR_NACKF_Msk            (0x1UL << I2C_ISR_NACKF_Pos)              /*!< 0x00000010 */

+#define I2C_ISR_NACKF                I2C_ISR_NACKF_Msk                         /*!< NACK received flag */

+#define I2C_ISR_STOPF_Pos            (5U)

+#define I2C_ISR_STOPF_Msk            (0x1UL << I2C_ISR_STOPF_Pos)              /*!< 0x00000020 */

+#define I2C_ISR_STOPF                I2C_ISR_STOPF_Msk                         /*!< STOP detection flag */

+#define I2C_ISR_TC_Pos               (6U)

+#define I2C_ISR_TC_Msk               (0x1UL << I2C_ISR_TC_Pos)                 /*!< 0x00000040 */

+#define I2C_ISR_TC                   I2C_ISR_TC_Msk                            /*!< Transfer complete (master mode) */

+#define I2C_ISR_TCR_Pos              (7U)

+#define I2C_ISR_TCR_Msk              (0x1UL << I2C_ISR_TCR_Pos)                /*!< 0x00000080 */

+#define I2C_ISR_TCR                  I2C_ISR_TCR_Msk                           /*!< Transfer complete reload */

+#define I2C_ISR_BERR_Pos             (8U)

+#define I2C_ISR_BERR_Msk             (0x1UL << I2C_ISR_BERR_Pos)               /*!< 0x00000100 */

+#define I2C_ISR_BERR                 I2C_ISR_BERR_Msk                          /*!< Bus error */

+#define I2C_ISR_ARLO_Pos             (9U)

+#define I2C_ISR_ARLO_Msk             (0x1UL << I2C_ISR_ARLO_Pos)               /*!< 0x00000200 */

+#define I2C_ISR_ARLO                 I2C_ISR_ARLO_Msk                          /*!< Arbitration lost */

+#define I2C_ISR_OVR_Pos              (10U)

+#define I2C_ISR_OVR_Msk              (0x1UL << I2C_ISR_OVR_Pos)                /*!< 0x00000400 */

+#define I2C_ISR_OVR                  I2C_ISR_OVR_Msk                           /*!< Overrun/Underrun */

+#define I2C_ISR_PECERR_Pos           (11U)

+#define I2C_ISR_PECERR_Msk           (0x1UL << I2C_ISR_PECERR_Pos)             /*!< 0x00000800 */

+#define I2C_ISR_PECERR               I2C_ISR_PECERR_Msk                        /*!< PEC error in reception */

+#define I2C_ISR_TIMEOUT_Pos          (12U)

+#define I2C_ISR_TIMEOUT_Msk          (0x1UL << I2C_ISR_TIMEOUT_Pos)            /*!< 0x00001000 */

+#define I2C_ISR_TIMEOUT              I2C_ISR_TIMEOUT_Msk                       /*!< Timeout or Tlow detection flag */

+#define I2C_ISR_ALERT_Pos            (13U)

+#define I2C_ISR_ALERT_Msk            (0x1UL << I2C_ISR_ALERT_Pos)              /*!< 0x00002000 */

+#define I2C_ISR_ALERT                I2C_ISR_ALERT_Msk                         /*!< SMBus alert */

+#define I2C_ISR_BUSY_Pos             (15U)

+#define I2C_ISR_BUSY_Msk             (0x1UL << I2C_ISR_BUSY_Pos)               /*!< 0x00008000 */

+#define I2C_ISR_BUSY                 I2C_ISR_BUSY_Msk                          /*!< Bus busy */

+#define I2C_ISR_DIR_Pos              (16U)

+#define I2C_ISR_DIR_Msk              (0x1UL << I2C_ISR_DIR_Pos)                /*!< 0x00010000 */

+#define I2C_ISR_DIR                  I2C_ISR_DIR_Msk                           /*!< Transfer direction (slave mode) */

+#define I2C_ISR_ADDCODE_Pos          (17U)

+#define I2C_ISR_ADDCODE_Msk          (0x7FUL << I2C_ISR_ADDCODE_Pos)           /*!< 0x00FE0000 */

+#define I2C_ISR_ADDCODE              I2C_ISR_ADDCODE_Msk                       /*!< Address match code (slave mode) */

+

+/******************  Bit definition for I2C_ICR register  *********************/

+#define I2C_ICR_ADDRCF_Pos           (3U)

+#define I2C_ICR_ADDRCF_Msk           (0x1UL << I2C_ICR_ADDRCF_Pos)             /*!< 0x00000008 */

+#define I2C_ICR_ADDRCF               I2C_ICR_ADDRCF_Msk                        /*!< Address matched clear flag */

+#define I2C_ICR_NACKCF_Pos           (4U)

+#define I2C_ICR_NACKCF_Msk           (0x1UL << I2C_ICR_NACKCF_Pos)             /*!< 0x00000010 */

+#define I2C_ICR_NACKCF               I2C_ICR_NACKCF_Msk                        /*!< NACK clear flag */

+#define I2C_ICR_STOPCF_Pos           (5U)

+#define I2C_ICR_STOPCF_Msk           (0x1UL << I2C_ICR_STOPCF_Pos)             /*!< 0x00000020 */

+#define I2C_ICR_STOPCF               I2C_ICR_STOPCF_Msk                        /*!< STOP detection clear flag */

+#define I2C_ICR_BERRCF_Pos           (8U)

+#define I2C_ICR_BERRCF_Msk           (0x1UL << I2C_ICR_BERRCF_Pos)             /*!< 0x00000100 */

+#define I2C_ICR_BERRCF               I2C_ICR_BERRCF_Msk                        /*!< Bus error clear flag */

+#define I2C_ICR_ARLOCF_Pos           (9U)

+#define I2C_ICR_ARLOCF_Msk           (0x1UL << I2C_ICR_ARLOCF_Pos)             /*!< 0x00000200 */

+#define I2C_ICR_ARLOCF               I2C_ICR_ARLOCF_Msk                        /*!< Arbitration lost clear flag */

+#define I2C_ICR_OVRCF_Pos            (10U)

+#define I2C_ICR_OVRCF_Msk            (0x1UL << I2C_ICR_OVRCF_Pos)              /*!< 0x00000400 */

+#define I2C_ICR_OVRCF                I2C_ICR_OVRCF_Msk                         /*!< Overrun/Underrun clear flag */

+#define I2C_ICR_PECCF_Pos            (11U)

+#define I2C_ICR_PECCF_Msk            (0x1UL << I2C_ICR_PECCF_Pos)              /*!< 0x00000800 */

+#define I2C_ICR_PECCF                I2C_ICR_PECCF_Msk                         /*!< PAC error clear flag */

+#define I2C_ICR_TIMOUTCF_Pos         (12U)

+#define I2C_ICR_TIMOUTCF_Msk         (0x1UL << I2C_ICR_TIMOUTCF_Pos)           /*!< 0x00001000 */

+#define I2C_ICR_TIMOUTCF             I2C_ICR_TIMOUTCF_Msk                      /*!< Timeout clear flag */

+#define I2C_ICR_ALERTCF_Pos          (13U)

+#define I2C_ICR_ALERTCF_Msk          (0x1UL << I2C_ICR_ALERTCF_Pos)            /*!< 0x00002000 */

+#define I2C_ICR_ALERTCF              I2C_ICR_ALERTCF_Msk                       /*!< Alert clear flag */

+

+/******************  Bit definition for I2C_PECR register  *********************/

+#define I2C_PECR_PEC_Pos             (0U)

+#define I2C_PECR_PEC_Msk             (0xFFUL << I2C_PECR_PEC_Pos)              /*!< 0x000000FF */

+#define I2C_PECR_PEC                 I2C_PECR_PEC_Msk                          /*!< PEC register */

+

+/******************  Bit definition for I2C_RXDR register  *********************/

+#define I2C_RXDR_RXDATA_Pos          (0U)

+#define I2C_RXDR_RXDATA_Msk          (0xFFUL << I2C_RXDR_RXDATA_Pos)           /*!< 0x000000FF */

+#define I2C_RXDR_RXDATA              I2C_RXDR_RXDATA_Msk                       /*!< 8-bit receive data */

+

+/******************  Bit definition for I2C_TXDR register  *********************/

+#define I2C_TXDR_TXDATA_Pos          (0U)

+#define I2C_TXDR_TXDATA_Msk          (0xFFUL << I2C_TXDR_TXDATA_Pos)           /*!< 0x000000FF */

+#define I2C_TXDR_TXDATA              I2C_TXDR_TXDATA_Msk                       /*!< 8-bit transmit data */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           Independent WATCHDOG                             */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for IWDG_KR register  ********************/

+#define IWDG_KR_KEY_Pos      (0U)

+#define IWDG_KR_KEY_Msk      (0xFFFFUL << IWDG_KR_KEY_Pos)                     /*!< 0x0000FFFF */

+#define IWDG_KR_KEY          IWDG_KR_KEY_Msk                                   /*!<Key value (write only, read 0000h)  */

+

+/*******************  Bit definition for IWDG_PR register  ********************/

+#define IWDG_PR_PR_Pos       (0U)

+#define IWDG_PR_PR_Msk       (0x7UL << IWDG_PR_PR_Pos)                         /*!< 0x00000007 */

+#define IWDG_PR_PR           IWDG_PR_PR_Msk                                    /*!<PR[2:0] (Prescaler divider)         */

+#define IWDG_PR_PR_0         (0x1UL << IWDG_PR_PR_Pos)                          /*!< 0x00000001 */

+#define IWDG_PR_PR_1         (0x2UL << IWDG_PR_PR_Pos)                          /*!< 0x00000002 */

+#define IWDG_PR_PR_2         (0x4UL << IWDG_PR_PR_Pos)                          /*!< 0x00000004 */

+

+/*******************  Bit definition for IWDG_RLR register  *******************/

+#define IWDG_RLR_RL_Pos      (0U)

+#define IWDG_RLR_RL_Msk      (0xFFFUL << IWDG_RLR_RL_Pos)                      /*!< 0x00000FFF */

+#define IWDG_RLR_RL          IWDG_RLR_RL_Msk                                   /*!<Watchdog counter reload value        */

+

+/*******************  Bit definition for IWDG_SR register  ********************/

+#define IWDG_SR_PVU_Pos      (0U)

+#define IWDG_SR_PVU_Msk      (0x1UL << IWDG_SR_PVU_Pos)                        /*!< 0x00000001 */

+#define IWDG_SR_PVU          IWDG_SR_PVU_Msk                                   /*!< Watchdog prescaler value update */

+#define IWDG_SR_RVU_Pos      (1U)

+#define IWDG_SR_RVU_Msk      (0x1UL << IWDG_SR_RVU_Pos)                        /*!< 0x00000002 */

+#define IWDG_SR_RVU          IWDG_SR_RVU_Msk                                   /*!< Watchdog counter reload value update */

+#define IWDG_SR_WVU_Pos      (2U)

+#define IWDG_SR_WVU_Msk      (0x1UL << IWDG_SR_WVU_Pos)                        /*!< 0x00000004 */

+#define IWDG_SR_WVU          IWDG_SR_WVU_Msk                                   /*!< Watchdog counter window value update */

+

+/*******************  Bit definition for IWDG_KR register  ********************/

+#define IWDG_WINR_WIN_Pos    (0U)

+#define IWDG_WINR_WIN_Msk    (0xFFFUL << IWDG_WINR_WIN_Pos)                    /*!< 0x00000FFF */

+#define IWDG_WINR_WIN        IWDG_WINR_WIN_Msk                                 /*!< Watchdog counter window value */

+

+/******************************************************************************/

+/*                                                                            */

+/*                        JPEG Encoder/Decoder                                */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for CONFR0 register  ********************/

+#define JPEG_CONFR0_START_Pos           (0U)

+#define JPEG_CONFR0_START_Msk           (0x1UL << JPEG_CONFR0_START_Pos)       /*!< 0x00000001 */

+#define JPEG_CONFR0_START               JPEG_CONFR0_START_Msk                  /*!<Start/Stop bit */

+

+/********************  Bit definition for CONFR1 register  ********************/

+#define JPEG_CONFR1_NF_Pos              (0U)

+#define JPEG_CONFR1_NF_Msk              (0x3UL << JPEG_CONFR1_NF_Pos)          /*!< 0x00000003 */

+#define JPEG_CONFR1_NF                  JPEG_CONFR1_NF_Msk                     /*!<Number of color components */

+#define JPEG_CONFR1_NF_0                (0x1UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000001 */

+#define JPEG_CONFR1_NF_1                (0x2UL << JPEG_CONFR1_NF_Pos)           /*!< 0x00000002 */

+#define JPEG_CONFR1_DE_Pos              (3U)

+#define JPEG_CONFR1_DE_Msk              (0x1UL << JPEG_CONFR1_DE_Pos)          /*!< 0x00000008 */

+#define JPEG_CONFR1_DE                  JPEG_CONFR1_DE_Msk                     /*!<Decoding Enable */

+#define JPEG_CONFR1_COLORSPACE_Pos      (4U)

+#define JPEG_CONFR1_COLORSPACE_Msk      (0x3UL << JPEG_CONFR1_COLORSPACE_Pos)  /*!< 0x00000030 */

+#define JPEG_CONFR1_COLORSPACE          JPEG_CONFR1_COLORSPACE_Msk             /*!<Color Space */

+#define JPEG_CONFR1_COLORSPACE_0        (0x1UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000010 */

+#define JPEG_CONFR1_COLORSPACE_1        (0x2UL << JPEG_CONFR1_COLORSPACE_Pos)   /*!< 0x00000020 */

+#define JPEG_CONFR1_NS_Pos              (6U)

+#define JPEG_CONFR1_NS_Msk              (0x3UL << JPEG_CONFR1_NS_Pos)          /*!< 0x000000C0 */

+#define JPEG_CONFR1_NS                  JPEG_CONFR1_NS_Msk                     /*!<Number of components for Scan */

+#define JPEG_CONFR1_NS_0                (0x1UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR1_NS_1                (0x2UL << JPEG_CONFR1_NS_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR1_HDR_Pos             (8U)

+#define JPEG_CONFR1_HDR_Msk             (0x1UL << JPEG_CONFR1_HDR_Pos)         /*!< 0x00000100 */

+#define JPEG_CONFR1_HDR                 JPEG_CONFR1_HDR_Msk                    /*!<Header Processing On/Off */

+#define JPEG_CONFR1_YSIZE_Pos           (16U)

+#define JPEG_CONFR1_YSIZE_Msk           (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos)    /*!< 0xFFFF0000 */

+#define JPEG_CONFR1_YSIZE               JPEG_CONFR1_YSIZE_Msk                  /*!<Number of lines in source image */

+

+/********************  Bit definition for CONFR2 register  ********************/

+#define JPEG_CONFR2_NMCU_Pos            (0U)

+#define JPEG_CONFR2_NMCU_Msk            (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos)  /*!< 0x03FFFFFF */

+#define JPEG_CONFR2_NMCU                JPEG_CONFR2_NMCU_Msk                   /*!<Number of MCU units minus 1 to encode */

+

+/********************  Bit definition for CONFR3 register  ********************/

+#define JPEG_CONFR3_XSIZE_Pos           (16U)

+#define JPEG_CONFR3_XSIZE_Msk           (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos)    /*!< 0xFFFF0000 */

+#define JPEG_CONFR3_XSIZE               JPEG_CONFR3_XSIZE_Msk                  /*!<Number of pixels per line */

+

+/********************  Bit definition for CONFR4 register  ********************/

+#define JPEG_CONFR4_HD_Pos              (0U)

+#define JPEG_CONFR4_HD_Msk              (0x1UL << JPEG_CONFR4_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR4_HD                  JPEG_CONFR4_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR4_HA_Pos              (1U)

+#define JPEG_CONFR4_HA_Msk              (0x1UL << JPEG_CONFR4_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR4_HA                  JPEG_CONFR4_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR4_QT_Pos              (2U)

+#define JPEG_CONFR4_QT_Msk              (0x3UL << JPEG_CONFR4_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR4_QT                  JPEG_CONFR4_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR4_QT_0                (0x1UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR4_QT_1                (0x2UL << JPEG_CONFR4_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR4_NB_Pos              (4U)

+#define JPEG_CONFR4_NB_Msk              (0xFUL << JPEG_CONFR4_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR4_NB                  JPEG_CONFR4_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR4_NB_0                (0x1UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR4_NB_1                (0x2UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR4_NB_2                (0x4UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR4_NB_3                (0x8UL << JPEG_CONFR4_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR4_VSF_Pos             (8U)

+#define JPEG_CONFR4_VSF_Msk             (0xFUL << JPEG_CONFR4_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR4_VSF                 JPEG_CONFR4_VSF_Msk                    /*!<Vertical sampling factor for component 1 */

+#define JPEG_CONFR4_VSF_0               (0x1UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR4_VSF_1               (0x2UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR4_VSF_2               (0x4UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR4_VSF_3               (0x8UL << JPEG_CONFR4_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR4_HSF_Pos             (12U)

+#define JPEG_CONFR4_HSF_Msk             (0xFUL << JPEG_CONFR4_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR4_HSF                 JPEG_CONFR4_HSF_Msk                    /*!<Horizontal sampling factor for component 1 */

+#define JPEG_CONFR4_HSF_0               (0x1UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR4_HSF_1               (0x2UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR4_HSF_2               (0x4UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR4_HSF_3               (0x8UL << JPEG_CONFR4_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR5 register  ********************/

+#define JPEG_CONFR5_HD_Pos              (0U)

+#define JPEG_CONFR5_HD_Msk              (0x1UL << JPEG_CONFR5_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR5_HD                  JPEG_CONFR5_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR5_HA_Pos              (1U)

+#define JPEG_CONFR5_HA_Msk              (0x1UL << JPEG_CONFR5_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR5_HA                  JPEG_CONFR5_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR5_QT_Pos              (2U)

+#define JPEG_CONFR5_QT_Msk              (0x3UL << JPEG_CONFR5_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR5_QT                  JPEG_CONFR5_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR5_QT_0                (0x1UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR5_QT_1                (0x2UL << JPEG_CONFR5_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR5_NB_Pos              (4U)

+#define JPEG_CONFR5_NB_Msk              (0xFUL << JPEG_CONFR5_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR5_NB                  JPEG_CONFR5_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR5_NB_0                (0x1UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR5_NB_1                (0x2UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR5_NB_2                (0x4UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR5_NB_3                (0x8UL << JPEG_CONFR5_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR5_VSF_Pos             (8U)

+#define JPEG_CONFR5_VSF_Msk             (0xFUL << JPEG_CONFR5_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR5_VSF                 JPEG_CONFR5_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR5_VSF_0               (0x1UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR5_VSF_1               (0x2UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR5_VSF_2               (0x4UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR5_VSF_3               (0x8UL << JPEG_CONFR5_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR5_HSF_Pos             (12U)

+#define JPEG_CONFR5_HSF_Msk             (0xFUL << JPEG_CONFR5_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR5_HSF                 JPEG_CONFR5_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR5_HSF_0               (0x1UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR5_HSF_1               (0x2UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR5_HSF_2               (0x4UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR5_HSF_3               (0x8UL << JPEG_CONFR5_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR6 register  ********************/

+#define JPEG_CONFR6_HD_Pos              (0U)

+#define JPEG_CONFR6_HD_Msk              (0x1UL << JPEG_CONFR6_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR6_HD                  JPEG_CONFR6_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR6_HA_Pos              (1U)

+#define JPEG_CONFR6_HA_Msk              (0x1UL << JPEG_CONFR6_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR6_HA                  JPEG_CONFR6_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR6_QT_Pos              (2U)

+#define JPEG_CONFR6_QT_Msk              (0x3UL << JPEG_CONFR6_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR6_QT                  JPEG_CONFR6_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR6_QT_0                (0x1UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR6_QT_1                (0x2UL << JPEG_CONFR6_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR6_NB_Pos              (4U)

+#define JPEG_CONFR6_NB_Msk              (0xFUL << JPEG_CONFR6_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR6_NB                  JPEG_CONFR6_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR6_NB_0                (0x1UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR6_NB_1                (0x2UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR6_NB_2                (0x4UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR6_NB_3                (0x8UL << JPEG_CONFR6_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR6_VSF_Pos             (8U)

+#define JPEG_CONFR6_VSF_Msk             (0xFUL << JPEG_CONFR6_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR6_VSF                 JPEG_CONFR6_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR6_VSF_0               (0x1UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR6_VSF_1               (0x2UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR6_VSF_2               (0x4UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR6_VSF_3               (0x8UL << JPEG_CONFR6_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR6_HSF_Pos             (12U)

+#define JPEG_CONFR6_HSF_Msk             (0xFUL << JPEG_CONFR6_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR6_HSF                 JPEG_CONFR6_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR6_HSF_0               (0x1UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR6_HSF_1               (0x2UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR6_HSF_2               (0x4UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR6_HSF_3               (0x8UL << JPEG_CONFR6_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CONFR7 register  ********************/

+#define JPEG_CONFR7_HD_Pos              (0U)

+#define JPEG_CONFR7_HD_Msk              (0x1UL << JPEG_CONFR7_HD_Pos)          /*!< 0x00000001 */

+#define JPEG_CONFR7_HD                  JPEG_CONFR7_HD_Msk                     /*!<Selects the Huffman table for encoding the DC coefficients */

+#define JPEG_CONFR7_HA_Pos              (1U)

+#define JPEG_CONFR7_HA_Msk              (0x1UL << JPEG_CONFR7_HA_Pos)          /*!< 0x00000002 */

+#define JPEG_CONFR7_HA                  JPEG_CONFR7_HA_Msk                     /*!<Selects the Huffman table for encoding the AC coefficients */

+#define JPEG_CONFR7_QT_Pos              (2U)

+#define JPEG_CONFR7_QT_Msk              (0x3UL << JPEG_CONFR7_QT_Pos)          /*!< 0x0000000C */

+#define JPEG_CONFR7_QT                  JPEG_CONFR7_QT_Msk                     /*!<Selects quantization table associated with a color component */

+#define JPEG_CONFR7_QT_0                (0x1UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000004 */

+#define JPEG_CONFR7_QT_1                (0x2UL << JPEG_CONFR7_QT_Pos)           /*!< 0x00000008 */

+#define JPEG_CONFR7_NB_Pos              (4U)

+#define JPEG_CONFR7_NB_Msk              (0xFUL << JPEG_CONFR7_NB_Pos)          /*!< 0x000000F0 */

+#define JPEG_CONFR7_NB                  JPEG_CONFR7_NB_Msk                     /*!<Number of data units minus 1 that belong to a particular color in the MCU */

+#define JPEG_CONFR7_NB_0                (0x1UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000010 */

+#define JPEG_CONFR7_NB_1                (0x2UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000020 */

+#define JPEG_CONFR7_NB_2                (0x4UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000040 */

+#define JPEG_CONFR7_NB_3                (0x8UL << JPEG_CONFR7_NB_Pos)           /*!< 0x00000080 */

+#define JPEG_CONFR7_VSF_Pos             (8U)

+#define JPEG_CONFR7_VSF_Msk             (0xFUL << JPEG_CONFR7_VSF_Pos)         /*!< 0x00000F00 */

+#define JPEG_CONFR7_VSF                 JPEG_CONFR7_VSF_Msk                    /*!<Vertical sampling factor for component 2 */

+#define JPEG_CONFR7_VSF_0               (0x1UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000100 */

+#define JPEG_CONFR7_VSF_1               (0x2UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000200 */

+#define JPEG_CONFR7_VSF_2               (0x4UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000400 */

+#define JPEG_CONFR7_VSF_3               (0x8UL << JPEG_CONFR7_VSF_Pos)          /*!< 0x00000800 */

+#define JPEG_CONFR7_HSF_Pos             (12U)

+#define JPEG_CONFR7_HSF_Msk             (0xFUL << JPEG_CONFR7_HSF_Pos)         /*!< 0x0000F000 */

+#define JPEG_CONFR7_HSF                 JPEG_CONFR7_HSF_Msk                    /*!<Horizontal sampling factor for component 2 */

+#define JPEG_CONFR7_HSF_0               (0x1UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00001000 */

+#define JPEG_CONFR7_HSF_1               (0x2UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00002000 */

+#define JPEG_CONFR7_HSF_2               (0x4UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00004000 */

+#define JPEG_CONFR7_HSF_3               (0x8UL << JPEG_CONFR7_HSF_Pos)          /*!< 0x00008000 */

+

+/********************  Bit definition for CR register  ********************/

+#define JPEG_CR_JCEN_Pos                (0U)

+#define JPEG_CR_JCEN_Msk                (0x1UL << JPEG_CR_JCEN_Pos)            /*!< 0x00000001 */

+#define JPEG_CR_JCEN                    JPEG_CR_JCEN_Msk                       /*!<Enable the JPEG Codec Core */

+#define JPEG_CR_IFTIE_Pos               (1U)

+#define JPEG_CR_IFTIE_Msk               (0x1UL << JPEG_CR_IFTIE_Pos)           /*!< 0x00000002 */

+#define JPEG_CR_IFTIE                   JPEG_CR_IFTIE_Msk                      /*!<Input FIFO Threshold Interrupt Enable */

+#define JPEG_CR_IFNFIE_Pos              (2U)

+#define JPEG_CR_IFNFIE_Msk              (0x1UL << JPEG_CR_IFNFIE_Pos)          /*!< 0x00000004 */

+#define JPEG_CR_IFNFIE                  JPEG_CR_IFNFIE_Msk                     /*!<Input FIFO Not Full Interrupt Enable */

+#define JPEG_CR_OFTIE_Pos               (3U)

+#define JPEG_CR_OFTIE_Msk               (0x1UL << JPEG_CR_OFTIE_Pos)           /*!< 0x00000008 */

+#define JPEG_CR_OFTIE                   JPEG_CR_OFTIE_Msk                      /*!<Output FIFO Threshold Interrupt Enable */

+#define JPEG_CR_OFNEIE_Pos              (4U)

+#define JPEG_CR_OFNEIE_Msk              (0x1UL << JPEG_CR_OFNEIE_Pos)          /*!< 0x00000010 */

+#define JPEG_CR_OFNEIE                  JPEG_CR_OFNEIE_Msk                     /*!<Output FIFO Not Empty Interrupt Enable */

+#define JPEG_CR_EOCIE_Pos               (5U)

+#define JPEG_CR_EOCIE_Msk               (0x1UL << JPEG_CR_EOCIE_Pos)           /*!< 0x00000020 */

+#define JPEG_CR_EOCIE                   JPEG_CR_EOCIE_Msk                      /*!<End of Conversion Interrupt Enable */

+#define JPEG_CR_HPDIE_Pos               (6U)

+#define JPEG_CR_HPDIE_Msk               (0x1UL << JPEG_CR_HPDIE_Pos)           /*!< 0x00000040 */

+#define JPEG_CR_HPDIE                   JPEG_CR_HPDIE_Msk                      /*!<Header Parsing Done Interrupt Enable */

+#define JPEG_CR_IFF_Pos                 (13U)

+#define JPEG_CR_IFF_Msk                 (0x1UL << JPEG_CR_IFF_Pos)             /*!< 0x00002000 */

+#define JPEG_CR_IFF                     JPEG_CR_IFF_Msk                        /*!<Flush the input FIFO */

+#define JPEG_CR_OFF_Pos                 (14U)

+#define JPEG_CR_OFF_Msk                 (0x1UL << JPEG_CR_OFF_Pos)             /*!< 0x00004000 */

+#define JPEG_CR_OFF                     JPEG_CR_OFF_Msk                        /*!<Flush the output FIFO */

+

+/********************  Bit definition for SR register  ********************/

+#define JPEG_SR_IFTF_Pos                (1U)

+#define JPEG_SR_IFTF_Msk                (0x1UL << JPEG_SR_IFTF_Pos)            /*!< 0x00000002 */

+#define JPEG_SR_IFTF                    JPEG_SR_IFTF_Msk                       /*!<Input FIFO is not full and is bellow its threshold flag */

+#define JPEG_SR_IFNFF_Pos               (2U)

+#define JPEG_SR_IFNFF_Msk               (0x1UL << JPEG_SR_IFNFF_Pos)           /*!< 0x00000004 */

+#define JPEG_SR_IFNFF                   JPEG_SR_IFNFF_Msk                      /*!<Input FIFO Not Full Flag, a data can be written */

+#define JPEG_SR_OFTF_Pos                (3U)

+#define JPEG_SR_OFTF_Msk                (0x1UL << JPEG_SR_OFTF_Pos)            /*!< 0x00000008 */

+#define JPEG_SR_OFTF                    JPEG_SR_OFTF_Msk                       /*!<Output FIFO is not empty and has reach its threshold */

+#define JPEG_SR_OFNEF_Pos               (4U)

+#define JPEG_SR_OFNEF_Msk               (0x1UL << JPEG_SR_OFNEF_Pos)           /*!< 0x00000010 */

+#define JPEG_SR_OFNEF                   JPEG_SR_OFNEF_Msk                      /*!<Output FIFO is not empty, a data is available */

+#define JPEG_SR_EOCF_Pos                (5U)

+#define JPEG_SR_EOCF_Msk                (0x1UL << JPEG_SR_EOCF_Pos)            /*!< 0x00000020 */

+#define JPEG_SR_EOCF                    JPEG_SR_EOCF_Msk                       /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */

+#define JPEG_SR_HPDF_Pos                (6U)

+#define JPEG_SR_HPDF_Msk                (0x1UL << JPEG_SR_HPDF_Pos)            /*!< 0x00000040 */

+#define JPEG_SR_HPDF                    JPEG_SR_HPDF_Msk                       /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */

+#define JPEG_SR_COF_Pos                 (7U)

+#define JPEG_SR_COF_Msk                 (0x1UL << JPEG_SR_COF_Pos)             /*!< 0x00000080 */

+#define JPEG_SR_COF                     JPEG_SR_COF_Msk                        /*!<JPEG Codec operation on going flag */

+

+/********************  Bit definition for CFR register  ********************/

+#define JPEG_CFR_CEOCF_Pos              (4U)

+#define JPEG_CFR_CEOCF_Msk              (0x1UL << JPEG_CFR_CEOCF_Pos)          /*!< 0x00000010 */

+#define JPEG_CFR_CEOCF                  JPEG_CFR_CEOCF_Msk                     /*!<Clear End of Conversion Flag */

+#define JPEG_CFR_CHPDF_Pos              (5U)

+#define JPEG_CFR_CHPDF_Msk              (0x1UL << JPEG_CFR_CHPDF_Pos)          /*!< 0x00000020 */

+#define JPEG_CFR_CHPDF                  JPEG_CFR_CHPDF_Msk                     /*!<Clear Header Parsing Done Flag */

+

+/********************  Bit definition for DIR register  ********************/

+#define JPEG_DIR_DATAIN_Pos             (0U)

+#define JPEG_DIR_DATAIN_Msk             (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos)  /*!< 0xFFFFFFFF */

+#define JPEG_DIR_DATAIN                 JPEG_DIR_DATAIN_Msk                    /*!<Data Input FIFO */

+

+/********************  Bit definition for DOR register  ********************/

+#define JPEG_DOR_DATAOUT_Pos            (0U)

+#define JPEG_DOR_DATAOUT_Msk            (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */

+#define JPEG_DOR_DATAOUT                JPEG_DOR_DATAOUT_Msk                   /*!<Data Output FIFO */

+

+/******************************************************************************/

+/*                                                                            */

+/*                      LCD-TFT Display Controller (LTDC)                     */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for LTDC_SSCR register  *****************/

+

+#define LTDC_SSCR_VSH_Pos            (0U)

+#define LTDC_SSCR_VSH_Msk            (0x7FFUL << LTDC_SSCR_VSH_Pos)            /*!< 0x000007FF */

+#define LTDC_SSCR_VSH                LTDC_SSCR_VSH_Msk                         /*!< Vertical Synchronization Height  */

+#define LTDC_SSCR_HSW_Pos            (16U)

+#define LTDC_SSCR_HSW_Msk            (0xFFFUL << LTDC_SSCR_HSW_Pos)            /*!< 0x0FFF0000 */

+#define LTDC_SSCR_HSW                LTDC_SSCR_HSW_Msk                         /*!< Horizontal Synchronization Width */

+

+/********************  Bit definition for LTDC_BPCR register  *****************/

+

+#define LTDC_BPCR_AVBP_Pos           (0U)

+#define LTDC_BPCR_AVBP_Msk           (0x7FFUL << LTDC_BPCR_AVBP_Pos)           /*!< 0x000007FF */

+#define LTDC_BPCR_AVBP               LTDC_BPCR_AVBP_Msk                        /*!< Accumulated Vertical Back Porch   */

+#define LTDC_BPCR_AHBP_Pos           (16U)

+#define LTDC_BPCR_AHBP_Msk           (0xFFFUL << LTDC_BPCR_AHBP_Pos)           /*!< 0x0FFF0000 */

+#define LTDC_BPCR_AHBP               LTDC_BPCR_AHBP_Msk                        /*!< Accumulated Horizontal Back Porch */

+

+/********************  Bit definition for LTDC_AWCR register  *****************/

+

+#define LTDC_AWCR_AAH_Pos            (0U)

+#define LTDC_AWCR_AAH_Msk            (0x7FFUL << LTDC_AWCR_AAH_Pos)            /*!< 0x000007FF */

+#define LTDC_AWCR_AAH                LTDC_AWCR_AAH_Msk                         /*!< Accumulated Active heigh */

+#define LTDC_AWCR_AAW_Pos            (16U)

+#define LTDC_AWCR_AAW_Msk            (0xFFFUL << LTDC_AWCR_AAW_Pos)            /*!< 0x0FFF0000 */

+#define LTDC_AWCR_AAW                LTDC_AWCR_AAW_Msk                         /*!< Accumulated Active Width */

+

+/********************  Bit definition for LTDC_TWCR register  *****************/

+

+#define LTDC_TWCR_TOTALH_Pos         (0U)

+#define LTDC_TWCR_TOTALH_Msk         (0x7FFUL << LTDC_TWCR_TOTALH_Pos)         /*!< 0x000007FF */

+#define LTDC_TWCR_TOTALH             LTDC_TWCR_TOTALH_Msk                      /*!< Total Heigh */

+#define LTDC_TWCR_TOTALW_Pos         (16U)

+#define LTDC_TWCR_TOTALW_Msk         (0xFFFUL << LTDC_TWCR_TOTALW_Pos)         /*!< 0x0FFF0000 */

+#define LTDC_TWCR_TOTALW             LTDC_TWCR_TOTALW_Msk                      /*!< Total Width */

+

+/********************  Bit definition for LTDC_GCR register  ******************/

+

+#define LTDC_GCR_LTDCEN_Pos          (0U)

+#define LTDC_GCR_LTDCEN_Msk          (0x1UL << LTDC_GCR_LTDCEN_Pos)            /*!< 0x00000001 */

+#define LTDC_GCR_LTDCEN              LTDC_GCR_LTDCEN_Msk                       /*!< LCD-TFT controller enable bit       */

+#define LTDC_GCR_DBW_Pos             (4U)

+#define LTDC_GCR_DBW_Msk             (0x7UL << LTDC_GCR_DBW_Pos)               /*!< 0x00000070 */

+#define LTDC_GCR_DBW                 LTDC_GCR_DBW_Msk                          /*!< Dither Blue Width                   */

+#define LTDC_GCR_DGW_Pos             (8U)

+#define LTDC_GCR_DGW_Msk             (0x7UL << LTDC_GCR_DGW_Pos)               /*!< 0x00000700 */

+#define LTDC_GCR_DGW                 LTDC_GCR_DGW_Msk                          /*!< Dither Green Width                  */

+#define LTDC_GCR_DRW_Pos             (12U)

+#define LTDC_GCR_DRW_Msk             (0x7UL << LTDC_GCR_DRW_Pos)               /*!< 0x00007000 */

+#define LTDC_GCR_DRW                 LTDC_GCR_DRW_Msk                          /*!< Dither Red Width                    */

+#define LTDC_GCR_DEN_Pos             (16U)

+#define LTDC_GCR_DEN_Msk             (0x1UL << LTDC_GCR_DEN_Pos)               /*!< 0x00010000 */

+#define LTDC_GCR_DEN                 LTDC_GCR_DEN_Msk                          /*!< Dither Enable                       */

+#define LTDC_GCR_PCPOL_Pos           (28U)

+#define LTDC_GCR_PCPOL_Msk           (0x1UL << LTDC_GCR_PCPOL_Pos)             /*!< 0x10000000 */

+#define LTDC_GCR_PCPOL               LTDC_GCR_PCPOL_Msk                        /*!< Pixel Clock Polarity                */

+#define LTDC_GCR_DEPOL_Pos           (29U)

+#define LTDC_GCR_DEPOL_Msk           (0x1UL << LTDC_GCR_DEPOL_Pos)             /*!< 0x20000000 */

+#define LTDC_GCR_DEPOL               LTDC_GCR_DEPOL_Msk                        /*!< Data Enable Polarity                */

+#define LTDC_GCR_VSPOL_Pos           (30U)

+#define LTDC_GCR_VSPOL_Msk           (0x1UL << LTDC_GCR_VSPOL_Pos)             /*!< 0x40000000 */

+#define LTDC_GCR_VSPOL               LTDC_GCR_VSPOL_Msk                        /*!< Vertical Synchronization Polarity   */

+#define LTDC_GCR_HSPOL_Pos           (31U)

+#define LTDC_GCR_HSPOL_Msk           (0x1UL << LTDC_GCR_HSPOL_Pos)             /*!< 0x80000000 */

+#define LTDC_GCR_HSPOL               LTDC_GCR_HSPOL_Msk                        /*!< Horizontal Synchronization Polarity */

+

+

+/********************  Bit definition for LTDC_SRCR register  *****************/

+

+#define LTDC_SRCR_IMR_Pos            (0U)

+#define LTDC_SRCR_IMR_Msk            (0x1UL << LTDC_SRCR_IMR_Pos)              /*!< 0x00000001 */

+#define LTDC_SRCR_IMR                LTDC_SRCR_IMR_Msk                         /*!< Immediate Reload         */

+#define LTDC_SRCR_VBR_Pos            (1U)

+#define LTDC_SRCR_VBR_Msk            (0x1UL << LTDC_SRCR_VBR_Pos)              /*!< 0x00000002 */

+#define LTDC_SRCR_VBR                LTDC_SRCR_VBR_Msk                         /*!< Vertical Blanking Reload */

+

+/********************  Bit definition for LTDC_BCCR register  *****************/

+

+#define LTDC_BCCR_BCBLUE_Pos         (0U)

+#define LTDC_BCCR_BCBLUE_Msk         (0xFFUL << LTDC_BCCR_BCBLUE_Pos)          /*!< 0x000000FF */

+#define LTDC_BCCR_BCBLUE             LTDC_BCCR_BCBLUE_Msk                      /*!< Background Blue value  */

+#define LTDC_BCCR_BCGREEN_Pos        (8U)

+#define LTDC_BCCR_BCGREEN_Msk        (0xFFUL << LTDC_BCCR_BCGREEN_Pos)         /*!< 0x0000FF00 */

+#define LTDC_BCCR_BCGREEN            LTDC_BCCR_BCGREEN_Msk                     /*!< Background Green value */

+#define LTDC_BCCR_BCRED_Pos          (16U)

+#define LTDC_BCCR_BCRED_Msk          (0xFFUL << LTDC_BCCR_BCRED_Pos)           /*!< 0x00FF0000 */

+#define LTDC_BCCR_BCRED              LTDC_BCCR_BCRED_Msk                       /*!< Background Red value   */

+

+/********************  Bit definition for LTDC_IER register  ******************/

+

+#define LTDC_IER_LIE_Pos             (0U)

+#define LTDC_IER_LIE_Msk             (0x1UL << LTDC_IER_LIE_Pos)               /*!< 0x00000001 */

+#define LTDC_IER_LIE                 LTDC_IER_LIE_Msk                          /*!< Line Interrupt Enable            */

+#define LTDC_IER_FUIE_Pos            (1U)

+#define LTDC_IER_FUIE_Msk            (0x1UL << LTDC_IER_FUIE_Pos)              /*!< 0x00000002 */

+#define LTDC_IER_FUIE                LTDC_IER_FUIE_Msk                         /*!< FIFO Underrun Interrupt Enable   */

+#define LTDC_IER_TERRIE_Pos          (2U)

+#define LTDC_IER_TERRIE_Msk          (0x1UL << LTDC_IER_TERRIE_Pos)            /*!< 0x00000004 */

+#define LTDC_IER_TERRIE              LTDC_IER_TERRIE_Msk                       /*!< Transfer Error Interrupt Enable  */

+#define LTDC_IER_RRIE_Pos            (3U)

+#define LTDC_IER_RRIE_Msk            (0x1UL << LTDC_IER_RRIE_Pos)              /*!< 0x00000008 */

+#define LTDC_IER_RRIE                LTDC_IER_RRIE_Msk                         /*!< Register Reload interrupt enable */

+

+/********************  Bit definition for LTDC_ISR register  ******************/

+

+#define LTDC_ISR_LIF_Pos             (0U)

+#define LTDC_ISR_LIF_Msk             (0x1UL << LTDC_ISR_LIF_Pos)               /*!< 0x00000001 */

+#define LTDC_ISR_LIF                 LTDC_ISR_LIF_Msk                          /*!< Line Interrupt Flag */

+#define LTDC_ISR_FUIF_Pos            (1U)

+#define LTDC_ISR_FUIF_Msk            (0x1UL << LTDC_ISR_FUIF_Pos)              /*!< 0x00000002 */

+#define LTDC_ISR_FUIF                LTDC_ISR_FUIF_Msk                         /*!< FIFO Underrun Interrupt Flag */

+#define LTDC_ISR_TERRIF_Pos          (2U)

+#define LTDC_ISR_TERRIF_Msk          (0x1UL << LTDC_ISR_TERRIF_Pos)            /*!< 0x00000004 */

+#define LTDC_ISR_TERRIF              LTDC_ISR_TERRIF_Msk                       /*!< Transfer Error Interrupt Flag */

+#define LTDC_ISR_RRIF_Pos            (3U)

+#define LTDC_ISR_RRIF_Msk            (0x1UL << LTDC_ISR_RRIF_Pos)              /*!< 0x00000008 */

+#define LTDC_ISR_RRIF                LTDC_ISR_RRIF_Msk                         /*!< Register Reload interrupt Flag */

+

+/********************  Bit definition for LTDC_ICR register  ******************/

+

+#define LTDC_ICR_CLIF_Pos            (0U)

+#define LTDC_ICR_CLIF_Msk            (0x1UL << LTDC_ICR_CLIF_Pos)              /*!< 0x00000001 */

+#define LTDC_ICR_CLIF                LTDC_ICR_CLIF_Msk                         /*!< Clears the Line Interrupt Flag */

+#define LTDC_ICR_CFUIF_Pos           (1U)

+#define LTDC_ICR_CFUIF_Msk           (0x1UL << LTDC_ICR_CFUIF_Pos)             /*!< 0x00000002 */

+#define LTDC_ICR_CFUIF               LTDC_ICR_CFUIF_Msk                        /*!< Clears the FIFO Underrun Interrupt Flag */

+#define LTDC_ICR_CTERRIF_Pos         (2U)

+#define LTDC_ICR_CTERRIF_Msk         (0x1UL << LTDC_ICR_CTERRIF_Pos)           /*!< 0x00000004 */

+#define LTDC_ICR_CTERRIF             LTDC_ICR_CTERRIF_Msk                      /*!< Clears the Transfer Error Interrupt Flag */

+#define LTDC_ICR_CRRIF_Pos           (3U)

+#define LTDC_ICR_CRRIF_Msk           (0x1UL << LTDC_ICR_CRRIF_Pos)             /*!< 0x00000008 */

+#define LTDC_ICR_CRRIF               LTDC_ICR_CRRIF_Msk                        /*!< Clears Register Reload interrupt Flag */

+

+/********************  Bit definition for LTDC_LIPCR register  ****************/

+

+#define LTDC_LIPCR_LIPOS_Pos         (0U)

+#define LTDC_LIPCR_LIPOS_Msk         (0x7FFUL << LTDC_LIPCR_LIPOS_Pos)         /*!< 0x000007FF */

+#define LTDC_LIPCR_LIPOS             LTDC_LIPCR_LIPOS_Msk                      /*!< Line Interrupt Position */

+

+/********************  Bit definition for LTDC_CPSR register  *****************/

+

+#define LTDC_CPSR_CYPOS_Pos          (0U)

+#define LTDC_CPSR_CYPOS_Msk          (0xFFFFUL << LTDC_CPSR_CYPOS_Pos)         /*!< 0x0000FFFF */

+#define LTDC_CPSR_CYPOS              LTDC_CPSR_CYPOS_Msk                       /*!< Current Y Position */

+#define LTDC_CPSR_CXPOS_Pos          (16U)

+#define LTDC_CPSR_CXPOS_Msk          (0xFFFFUL << LTDC_CPSR_CXPOS_Pos)         /*!< 0xFFFF0000 */

+#define LTDC_CPSR_CXPOS              LTDC_CPSR_CXPOS_Msk                       /*!< Current X Position */

+

+/********************  Bit definition for LTDC_CDSR register  *****************/

+

+#define LTDC_CDSR_VDES_Pos           (0U)

+#define LTDC_CDSR_VDES_Msk           (0x1UL << LTDC_CDSR_VDES_Pos)             /*!< 0x00000001 */

+#define LTDC_CDSR_VDES               LTDC_CDSR_VDES_Msk                        /*!< Vertical Data Enable Status       */

+#define LTDC_CDSR_HDES_Pos           (1U)

+#define LTDC_CDSR_HDES_Msk           (0x1UL << LTDC_CDSR_HDES_Pos)             /*!< 0x00000002 */

+#define LTDC_CDSR_HDES               LTDC_CDSR_HDES_Msk                        /*!< Horizontal Data Enable Status     */

+#define LTDC_CDSR_VSYNCS_Pos         (2U)

+#define LTDC_CDSR_VSYNCS_Msk         (0x1UL << LTDC_CDSR_VSYNCS_Pos)           /*!< 0x00000004 */

+#define LTDC_CDSR_VSYNCS             LTDC_CDSR_VSYNCS_Msk                      /*!< Vertical Synchronization Status   */

+#define LTDC_CDSR_HSYNCS_Pos         (3U)

+#define LTDC_CDSR_HSYNCS_Msk         (0x1UL << LTDC_CDSR_HSYNCS_Pos)           /*!< 0x00000008 */

+#define LTDC_CDSR_HSYNCS             LTDC_CDSR_HSYNCS_Msk                      /*!< Horizontal Synchronization Status */

+

+/********************  Bit definition for LTDC_LxCR register  *****************/

+

+#define LTDC_LxCR_LEN_Pos            (0U)

+#define LTDC_LxCR_LEN_Msk            (0x1UL << LTDC_LxCR_LEN_Pos)              /*!< 0x00000001 */

+#define LTDC_LxCR_LEN                LTDC_LxCR_LEN_Msk                         /*!< Layer Enable              */

+#define LTDC_LxCR_COLKEN_Pos         (1U)

+#define LTDC_LxCR_COLKEN_Msk         (0x1UL << LTDC_LxCR_COLKEN_Pos)           /*!< 0x00000002 */

+#define LTDC_LxCR_COLKEN             LTDC_LxCR_COLKEN_Msk                      /*!< Color Keying Enable       */

+#define LTDC_LxCR_CLUTEN_Pos         (4U)

+#define LTDC_LxCR_CLUTEN_Msk         (0x1UL << LTDC_LxCR_CLUTEN_Pos)           /*!< 0x00000010 */

+#define LTDC_LxCR_CLUTEN             LTDC_LxCR_CLUTEN_Msk                      /*!< Color Lockup Table Enable */

+

+/********************  Bit definition for LTDC_LxWHPCR register  **************/

+

+#define LTDC_LxWHPCR_WHSTPOS_Pos     (0U)

+#define LTDC_LxWHPCR_WHSTPOS_Msk     (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos)     /*!< 0x00000FFF */

+#define LTDC_LxWHPCR_WHSTPOS         LTDC_LxWHPCR_WHSTPOS_Msk                  /*!< Window Horizontal Start Position */

+#define LTDC_LxWHPCR_WHSPPOS_Pos     (16U)

+#define LTDC_LxWHPCR_WHSPPOS_Msk     (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos)    /*!< 0xFFFF0000 */

+#define LTDC_LxWHPCR_WHSPPOS         LTDC_LxWHPCR_WHSPPOS_Msk                  /*!< Window Horizontal Stop Position  */

+

+/********************  Bit definition for LTDC_LxWVPCR register  **************/

+

+#define LTDC_LxWVPCR_WVSTPOS_Pos     (0U)

+#define LTDC_LxWVPCR_WVSTPOS_Msk     (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos)     /*!< 0x00000FFF */

+#define LTDC_LxWVPCR_WVSTPOS         LTDC_LxWVPCR_WVSTPOS_Msk                  /*!< Window Vertical Start Position */

+#define LTDC_LxWVPCR_WVSPPOS_Pos     (16U)

+#define LTDC_LxWVPCR_WVSPPOS_Msk     (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos)    /*!< 0xFFFF0000 */

+#define LTDC_LxWVPCR_WVSPPOS         LTDC_LxWVPCR_WVSPPOS_Msk                  /*!< Window Vertical Stop Position  */

+

+/********************  Bit definition for LTDC_LxCKCR register  ***************/

+

+#define LTDC_LxCKCR_CKBLUE_Pos       (0U)

+#define LTDC_LxCKCR_CKBLUE_Msk       (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCKCR_CKBLUE           LTDC_LxCKCR_CKBLUE_Msk                    /*!< Color Key Blue value  */

+#define LTDC_LxCKCR_CKGREEN_Pos      (8U)

+#define LTDC_LxCKCR_CKGREEN_Msk      (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxCKCR_CKGREEN          LTDC_LxCKCR_CKGREEN_Msk                   /*!< Color Key Green value */

+#define LTDC_LxCKCR_CKRED_Pos        (16U)

+#define LTDC_LxCKCR_CKRED_Msk        (0xFFUL << LTDC_LxCKCR_CKRED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxCKCR_CKRED            LTDC_LxCKCR_CKRED_Msk                     /*!< Color Key Red value   */

+

+/********************  Bit definition for LTDC_LxPFCR register  ***************/

+

+#define LTDC_LxPFCR_PF_Pos           (0U)

+#define LTDC_LxPFCR_PF_Msk           (0x7UL << LTDC_LxPFCR_PF_Pos)             /*!< 0x00000007 */

+#define LTDC_LxPFCR_PF               LTDC_LxPFCR_PF_Msk                        /*!< Pixel Format */

+

+/********************  Bit definition for LTDC_LxCACR register  ***************/

+

+#define LTDC_LxCACR_CONSTA_Pos       (0U)

+#define LTDC_LxCACR_CONSTA_Msk       (0xFFUL << LTDC_LxCACR_CONSTA_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCACR_CONSTA           LTDC_LxCACR_CONSTA_Msk                    /*!< Constant Alpha */

+

+/********************  Bit definition for LTDC_LxDCCR register  ***************/

+

+#define LTDC_LxDCCR_DCBLUE_Pos       (0U)

+#define LTDC_LxDCCR_DCBLUE_Msk       (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxDCCR_DCBLUE           LTDC_LxDCCR_DCBLUE_Msk                    /*!< Default Color Blue  */

+#define LTDC_LxDCCR_DCGREEN_Pos      (8U)

+#define LTDC_LxDCCR_DCGREEN_Msk      (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxDCCR_DCGREEN          LTDC_LxDCCR_DCGREEN_Msk                   /*!< Default Color Green */

+#define LTDC_LxDCCR_DCRED_Pos        (16U)

+#define LTDC_LxDCCR_DCRED_Msk        (0xFFUL << LTDC_LxDCCR_DCRED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxDCCR_DCRED            LTDC_LxDCCR_DCRED_Msk                     /*!< Default Color Red   */

+#define LTDC_LxDCCR_DCALPHA_Pos      (24U)

+#define LTDC_LxDCCR_DCALPHA_Msk      (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos)       /*!< 0xFF000000 */

+#define LTDC_LxDCCR_DCALPHA          LTDC_LxDCCR_DCALPHA_Msk                   /*!< Default Color Alpha */

+

+/********************  Bit definition for LTDC_LxBFCR register  ***************/

+

+#define LTDC_LxBFCR_BF2_Pos          (0U)

+#define LTDC_LxBFCR_BF2_Msk          (0x7UL << LTDC_LxBFCR_BF2_Pos)            /*!< 0x00000007 */

+#define LTDC_LxBFCR_BF2              LTDC_LxBFCR_BF2_Msk                       /*!< Blending Factor 2 */

+#define LTDC_LxBFCR_BF1_Pos          (8U)

+#define LTDC_LxBFCR_BF1_Msk          (0x7UL << LTDC_LxBFCR_BF1_Pos)            /*!< 0x00000700 */

+#define LTDC_LxBFCR_BF1              LTDC_LxBFCR_BF1_Msk                       /*!< Blending Factor 1 */

+

+/********************  Bit definition for LTDC_LxCFBAR register  **************/

+

+#define LTDC_LxCFBAR_CFBADD_Pos      (0U)

+#define LTDC_LxCFBAR_CFBADD_Msk      (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */

+#define LTDC_LxCFBAR_CFBADD          LTDC_LxCFBAR_CFBADD_Msk                   /*!< Color Frame Buffer Start Address */

+

+/********************  Bit definition for LTDC_LxCFBLR register  **************/

+

+#define LTDC_LxCFBLR_CFBLL_Pos       (0U)

+#define LTDC_LxCFBLR_CFBLL_Msk       (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos)      /*!< 0x00001FFF */

+#define LTDC_LxCFBLR_CFBLL           LTDC_LxCFBLR_CFBLL_Msk                    /*!< Color Frame Buffer Line Length    */

+#define LTDC_LxCFBLR_CFBP_Pos        (16U)

+#define LTDC_LxCFBLR_CFBP_Msk        (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos)       /*!< 0x1FFF0000 */

+#define LTDC_LxCFBLR_CFBP            LTDC_LxCFBLR_CFBP_Msk                     /*!< Color Frame Buffer Pitch in bytes */

+

+/********************  Bit definition for LTDC_LxCFBLNR register  *************/

+

+#define LTDC_LxCFBLNR_CFBLNBR_Pos    (0U)

+#define LTDC_LxCFBLNR_CFBLNBR_Msk    (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos)    /*!< 0x000007FF */

+#define LTDC_LxCFBLNR_CFBLNBR        LTDC_LxCFBLNR_CFBLNBR_Msk                 /*!< Frame Buffer Line Number */

+

+/********************  Bit definition for LTDC_LxCLUTWR register  *************/

+

+#define LTDC_LxCLUTWR_BLUE_Pos       (0U)

+#define LTDC_LxCLUTWR_BLUE_Msk       (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos)        /*!< 0x000000FF */

+#define LTDC_LxCLUTWR_BLUE           LTDC_LxCLUTWR_BLUE_Msk                    /*!< Blue value   */

+#define LTDC_LxCLUTWR_GREEN_Pos      (8U)

+#define LTDC_LxCLUTWR_GREEN_Msk      (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos)       /*!< 0x0000FF00 */

+#define LTDC_LxCLUTWR_GREEN          LTDC_LxCLUTWR_GREEN_Msk                   /*!< Green value  */

+#define LTDC_LxCLUTWR_RED_Pos        (16U)

+#define LTDC_LxCLUTWR_RED_Msk        (0xFFUL << LTDC_LxCLUTWR_RED_Pos)         /*!< 0x00FF0000 */

+#define LTDC_LxCLUTWR_RED            LTDC_LxCLUTWR_RED_Msk                     /*!< Red value    */

+#define LTDC_LxCLUTWR_CLUTADD_Pos    (24U)

+#define LTDC_LxCLUTWR_CLUTADD_Msk    (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos)     /*!< 0xFF000000 */

+#define LTDC_LxCLUTWR_CLUTADD        LTDC_LxCLUTWR_CLUTADD_Msk                 /*!< CLUT address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                     MDMA                                   */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for MDMA_GISR0 register  ****************/

+#define MDMA_GISR0_GIF0_Pos       (0U)

+#define MDMA_GISR0_GIF0_Msk       (0x1UL << MDMA_GISR0_GIF0_Pos)               /*!< 0x00000001 */

+#define MDMA_GISR0_GIF0           MDMA_GISR0_GIF0_Msk                          /*!< Channel 0 global interrupt flag */

+#define MDMA_GISR0_GIF1_Pos       (1U)

+#define MDMA_GISR0_GIF1_Msk       (0x1UL << MDMA_GISR0_GIF1_Pos)               /*!< 0x00000002 */

+#define MDMA_GISR0_GIF1           MDMA_GISR0_GIF1_Msk                          /*!< Channel 1 global interrupt flag */

+#define MDMA_GISR0_GIF2_Pos       (2U)

+#define MDMA_GISR0_GIF2_Msk       (0x1UL << MDMA_GISR0_GIF2_Pos)               /*!< 0x00000004 */

+#define MDMA_GISR0_GIF2           MDMA_GISR0_GIF2_Msk                          /*!< Channel 2 global interrupt flag */

+#define MDMA_GISR0_GIF3_Pos       (3U)

+#define MDMA_GISR0_GIF3_Msk       (0x1UL << MDMA_GISR0_GIF3_Pos)               /*!< 0x00000008 */

+#define MDMA_GISR0_GIF3           MDMA_GISR0_GIF3_Msk                          /*!< Channel 3 global interrupt flag */

+#define MDMA_GISR0_GIF4_Pos       (4U)

+#define MDMA_GISR0_GIF4_Msk       (0x1UL << MDMA_GISR0_GIF4_Pos)               /*!< 0x00000010 */

+#define MDMA_GISR0_GIF4           MDMA_GISR0_GIF4_Msk                          /*!< Channel 4 global interrupt flag */

+#define MDMA_GISR0_GIF5_Pos       (5U)

+#define MDMA_GISR0_GIF5_Msk       (0x1UL << MDMA_GISR0_GIF5_Pos)               /*!< 0x00000020 */

+#define MDMA_GISR0_GIF5           MDMA_GISR0_GIF5_Msk                          /*!< Channel 5 global interrupt flag */

+#define MDMA_GISR0_GIF6_Pos       (6U)

+#define MDMA_GISR0_GIF6_Msk       (0x1UL << MDMA_GISR0_GIF6_Pos)               /*!< 0x00000040 */

+#define MDMA_GISR0_GIF6           MDMA_GISR0_GIF6_Msk                          /*!< Channel 6 global interrupt flag */

+#define MDMA_GISR0_GIF7_Pos       (7U)

+#define MDMA_GISR0_GIF7_Msk       (0x1UL << MDMA_GISR0_GIF7_Pos)               /*!< 0x00000080 */

+#define MDMA_GISR0_GIF7           MDMA_GISR0_GIF7_Msk                          /*!< Channel 7 global interrupt flag */

+#define MDMA_GISR0_GIF8_Pos       (8U)

+#define MDMA_GISR0_GIF8_Msk       (0x1UL << MDMA_GISR0_GIF8_Pos)               /*!< 0x00000100 */

+#define MDMA_GISR0_GIF8           MDMA_GISR0_GIF8_Msk                          /*!< Channel 8 global interrupt flag */

+#define MDMA_GISR0_GIF9_Pos       (9U)

+#define MDMA_GISR0_GIF9_Msk       (0x1UL << MDMA_GISR0_GIF9_Pos)               /*!< 0x00000200 */

+#define MDMA_GISR0_GIF9           MDMA_GISR0_GIF9_Msk                          /*!< Channel 9 global interrupt flag */

+#define MDMA_GISR0_GIF10_Pos      (10U)

+#define MDMA_GISR0_GIF10_Msk      (0x1UL << MDMA_GISR0_GIF10_Pos)              /*!< 0x00000400 */

+#define MDMA_GISR0_GIF10          MDMA_GISR0_GIF10_Msk                         /*!< Channel 10 global interrupt flag */

+#define MDMA_GISR0_GIF11_Pos      (11U)

+#define MDMA_GISR0_GIF11_Msk      (0x1UL << MDMA_GISR0_GIF11_Pos)              /*!< 0x00000800 */

+#define MDMA_GISR0_GIF11          MDMA_GISR0_GIF11_Msk                         /*!< Channel 11 global interrupt flag */

+#define MDMA_GISR0_GIF12_Pos      (12U)

+#define MDMA_GISR0_GIF12_Msk      (0x1UL << MDMA_GISR0_GIF12_Pos)              /*!< 0x00001000 */

+#define MDMA_GISR0_GIF12          MDMA_GISR0_GIF12_Msk                         /*!< Channel 12 global interrupt flag */

+#define MDMA_GISR0_GIF13_Pos      (13U)

+#define MDMA_GISR0_GIF13_Msk      (0x1UL << MDMA_GISR0_GIF13_Pos)              /*!< 0x00002000 */

+#define MDMA_GISR0_GIF13          MDMA_GISR0_GIF13_Msk                         /*!< Channel 13 global interrupt flag */

+#define MDMA_GISR0_GIF14_Pos      (14U)

+#define MDMA_GISR0_GIF14_Msk      (0x1UL << MDMA_GISR0_GIF14_Pos)              /*!< 0x00004000 */

+#define MDMA_GISR0_GIF14          MDMA_GISR0_GIF14_Msk                         /*!< Channel 14 global interrupt flag */

+#define MDMA_GISR0_GIF15_Pos      (15U)

+#define MDMA_GISR0_GIF15_Msk      (0x1UL << MDMA_GISR0_GIF15_Pos)              /*!< 0x00008000 */

+#define MDMA_GISR0_GIF15          MDMA_GISR0_GIF15_Msk                         /*!< Channel 15 global interrupt flag */

+

+/********************  Bit definition for MDMA_CxISR register  ****************/

+#define MDMA_CISR_TEIF_Pos        (0U)

+#define MDMA_CISR_TEIF_Msk        (0x1UL << MDMA_CISR_TEIF_Pos)                /*!< 0x00000001 */

+#define MDMA_CISR_TEIF            MDMA_CISR_TEIF_Msk                           /*!< Channel x transfer error interrupt flag */

+#define MDMA_CISR_CTCIF_Pos       (1U)

+#define MDMA_CISR_CTCIF_Msk       (0x1UL << MDMA_CISR_CTCIF_Pos)               /*!< 0x00000002 */

+#define MDMA_CISR_CTCIF           MDMA_CISR_CTCIF_Msk                          /*!< Channel x Channel Transfer Complete interrupt flag */

+#define MDMA_CISR_BRTIF_Pos       (2U)

+#define MDMA_CISR_BRTIF_Msk       (0x1UL << MDMA_CISR_BRTIF_Pos)               /*!< 0x00000004 */

+#define MDMA_CISR_BRTIF           MDMA_CISR_BRTIF_Msk                          /*!< Channel x block repeat transfer complete interrupt flag */

+#define MDMA_CISR_BTIF_Pos        (3U)

+#define MDMA_CISR_BTIF_Msk        (0x1UL << MDMA_CISR_BTIF_Pos)                /*!< 0x00000008 */

+#define MDMA_CISR_BTIF            MDMA_CISR_BTIF_Msk                           /*!< Channel x block transfer complete interrupt flag */

+#define MDMA_CISR_TCIF_Pos        (4U)

+#define MDMA_CISR_TCIF_Msk        (0x1UL << MDMA_CISR_TCIF_Pos)                /*!< 0x00000010 */

+#define MDMA_CISR_TCIF            MDMA_CISR_TCIF_Msk                           /*!< Channel x buffer transfer complete interrupt flag */

+#define MDMA_CISR_CRQA_Pos        (16U)

+#define MDMA_CISR_CRQA_Msk        (0x1UL << MDMA_CISR_CRQA_Pos)                /*!< 0x00010000 */

+#define MDMA_CISR_CRQA            MDMA_CISR_CRQA_Msk                           /*!< Channel x ReQest Active flag */

+

+/********************  Bit definition for MDMA_CxIFCR register  ****************/

+#define MDMA_CIFCR_CTEIF_Pos      (0U)

+#define MDMA_CIFCR_CTEIF_Msk      (0x1UL << MDMA_CIFCR_CTEIF_Pos)              /*!< 0x00000001 */

+#define MDMA_CIFCR_CTEIF          MDMA_CIFCR_CTEIF_Msk                         /*!< Channel x clear transfer error interrupt flag */

+#define MDMA_CIFCR_CCTCIF_Pos     (1U)

+#define MDMA_CIFCR_CCTCIF_Msk     (0x1UL << MDMA_CIFCR_CCTCIF_Pos)             /*!< 0x00000002 */

+#define MDMA_CIFCR_CCTCIF         MDMA_CIFCR_CCTCIF_Msk                        /*!< Clear Channel transfer complete interrupt flag for channel x */

+#define MDMA_CIFCR_CBRTIF_Pos     (2U)

+#define MDMA_CIFCR_CBRTIF_Msk     (0x1UL << MDMA_CIFCR_CBRTIF_Pos)             /*!< 0x00000004 */

+#define MDMA_CIFCR_CBRTIF         MDMA_CIFCR_CBRTIF_Msk                        /*!< Channel x clear block repeat transfer complete interrupt flag */

+#define MDMA_CIFCR_CBTIF_Pos      (3U)

+#define MDMA_CIFCR_CBTIF_Msk      (0x1UL << MDMA_CIFCR_CBTIF_Pos)              /*!< 0x00000008 */

+#define MDMA_CIFCR_CBTIF          MDMA_CIFCR_CBTIF_Msk                         /*!< Channel x Clear block transfer complete interrupt flag */

+#define MDMA_CIFCR_CLTCIF_Pos     (4U)

+#define MDMA_CIFCR_CLTCIF_Msk     (0x1UL << MDMA_CIFCR_CLTCIF_Pos)             /*!< 0x00000010 */

+#define MDMA_CIFCR_CLTCIF         MDMA_CIFCR_CLTCIF_Msk                        /*!< CLear Transfer buffer Complete Interrupt Flag for channel */

+

+/********************  Bit definition for MDMA_CxESR register  ****************/

+#define MDMA_CESR_TEA_Pos         (0U)

+#define MDMA_CESR_TEA_Msk         (0x7FUL << MDMA_CESR_TEA_Pos)                /*!< 0x0000007F */

+#define MDMA_CESR_TEA             MDMA_CESR_TEA_Msk                            /*!< Transfer Error Address */

+#define MDMA_CESR_TED_Pos         (7U)

+#define MDMA_CESR_TED_Msk         (0x1UL << MDMA_CESR_TED_Pos)                 /*!< 0x00000080 */

+#define MDMA_CESR_TED             MDMA_CESR_TED_Msk                            /*!< Transfer Error Direction */

+#define MDMA_CESR_TELD_Pos        (8U)

+#define MDMA_CESR_TELD_Msk        (0x1UL << MDMA_CESR_TELD_Pos)                /*!< 0x00000100 */

+#define MDMA_CESR_TELD            MDMA_CESR_TELD_Msk                           /*!< Transfer Error Link Data */

+#define MDMA_CESR_TEMD_Pos        (9U)

+#define MDMA_CESR_TEMD_Msk        (0x1UL << MDMA_CESR_TEMD_Pos)                /*!< 0x00000200 */

+#define MDMA_CESR_TEMD            MDMA_CESR_TEMD_Msk                           /*!< Transfer Error Mask Data */

+#define MDMA_CESR_ASE_Pos         (10U)

+#define MDMA_CESR_ASE_Msk         (0x1UL << MDMA_CESR_ASE_Pos)                 /*!< 0x00000400 */

+#define MDMA_CESR_ASE             MDMA_CESR_ASE_Msk                            /*!< Address/Size Error       */

+#define MDMA_CESR_BSE_Pos         (11U)

+#define MDMA_CESR_BSE_Msk         (0x1UL << MDMA_CESR_BSE_Pos)                 /*!< 0x00000800 */

+#define MDMA_CESR_BSE             MDMA_CESR_BSE_Msk                            /*!< Block Size Error         */

+

+/********************  Bit definition for MDMA_CxCR register  ****************/

+#define MDMA_CCR_EN_Pos           (0U)

+#define MDMA_CCR_EN_Msk           (0x1UL << MDMA_CCR_EN_Pos)                   /*!< 0x00000001 */

+#define MDMA_CCR_EN               MDMA_CCR_EN_Msk                              /*!< Channel enable / flag channel ready when read low */

+#define MDMA_CCR_TEIE_Pos         (1U)

+#define MDMA_CCR_TEIE_Msk         (0x1UL << MDMA_CCR_TEIE_Pos)                 /*!< 0x00000002 */

+#define MDMA_CCR_TEIE             MDMA_CCR_TEIE_Msk                            /*!< Transfer error interrupt enable */

+#define MDMA_CCR_CTCIE_Pos        (2U)

+#define MDMA_CCR_CTCIE_Msk        (0x1UL << MDMA_CCR_CTCIE_Pos)                /*!< 0x00000004 */

+#define MDMA_CCR_CTCIE            MDMA_CCR_CTCIE_Msk                           /*!< Channel Transfer Complete interrupt enable */

+#define MDMA_CCR_BRTIE_Pos        (3U)

+#define MDMA_CCR_BRTIE_Msk        (0x1UL << MDMA_CCR_BRTIE_Pos)                /*!< 0x00000008 */

+#define MDMA_CCR_BRTIE            MDMA_CCR_BRTIE_Msk                           /*!< Block Repeat transfer interrupt enable */

+#define MDMA_CCR_BTIE_Pos         (4U)

+#define MDMA_CCR_BTIE_Msk         (0x1UL << MDMA_CCR_BTIE_Pos)                 /*!< 0x00000010 */

+#define MDMA_CCR_BTIE             MDMA_CCR_BTIE_Msk                            /*!< Block Transfer interrupt enable */

+#define MDMA_CCR_TCIE_Pos         (5U)

+#define MDMA_CCR_TCIE_Msk         (0x1UL << MDMA_CCR_TCIE_Pos)                 /*!< 0x00000020 */

+#define MDMA_CCR_TCIE             MDMA_CCR_TCIE_Msk                            /*!< buffer Transfer Complete interrupt enable */

+#define MDMA_CCR_PL_Pos           (6U)

+#define MDMA_CCR_PL_Msk           (0x3UL << MDMA_CCR_PL_Pos)                   /*!< 0x000000C0 */

+#define MDMA_CCR_PL               MDMA_CCR_PL_Msk                              /*!< Priority level */

+#define MDMA_CCR_PL_0             (0x1UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000040 */

+#define MDMA_CCR_PL_1             (0x2UL << MDMA_CCR_PL_Pos)                    /*!< 0x00000080 */

+#define MDMA_CCR_BEX_Pos          (12U)

+#define MDMA_CCR_BEX_Msk          (0x1UL << MDMA_CCR_BEX_Pos)                  /*!< 0x00001000 */

+#define MDMA_CCR_BEX              MDMA_CCR_BEX_Msk                             /*!< Byte Endianess eXchange */

+#define MDMA_CCR_HEX_Pos          (13U)

+#define MDMA_CCR_HEX_Msk          (0x1UL << MDMA_CCR_HEX_Pos)                  /*!< 0x00002000 */

+#define MDMA_CCR_HEX              MDMA_CCR_HEX_Msk                             /*!< Half word Endianess eXchange */

+#define MDMA_CCR_WEX_Pos          (14U)

+#define MDMA_CCR_WEX_Msk          (0x1UL << MDMA_CCR_WEX_Pos)                  /*!< 0x00004000 */

+#define MDMA_CCR_WEX              MDMA_CCR_WEX_Msk                             /*!< Word Endianess eXchange */

+#define MDMA_CCR_SWRQ_Pos         (16U)

+#define MDMA_CCR_SWRQ_Msk         (0x1UL << MDMA_CCR_SWRQ_Pos)                 /*!< 0x00010000 */

+#define MDMA_CCR_SWRQ             MDMA_CCR_SWRQ_Msk                            /*!< SW ReQuest */

+

+/********************  Bit definition for MDMA_CxTCR register  ****************/

+#define MDMA_CTCR_SINC_Pos        (0U)

+#define MDMA_CTCR_SINC_Msk        (0x3UL << MDMA_CTCR_SINC_Pos)                /*!< 0x00000003 */

+#define MDMA_CTCR_SINC            MDMA_CTCR_SINC_Msk                           /*!< Source increment mode */

+#define MDMA_CTCR_SINC_0          (0x1UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000001 */

+#define MDMA_CTCR_SINC_1          (0x2UL << MDMA_CTCR_SINC_Pos)                 /*!< 0x00000002 */

+#define MDMA_CTCR_DINC_Pos        (2U)

+#define MDMA_CTCR_DINC_Msk        (0x3UL << MDMA_CTCR_DINC_Pos)                /*!< 0x0000000C */

+#define MDMA_CTCR_DINC            MDMA_CTCR_DINC_Msk                           /*!< Source increment mode */

+#define MDMA_CTCR_DINC_0          (0x1UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000004 */

+#define MDMA_CTCR_DINC_1          (0x2UL << MDMA_CTCR_DINC_Pos)                 /*!< 0x00000008 */

+#define MDMA_CTCR_SSIZE_Pos       (4U)

+#define MDMA_CTCR_SSIZE_Msk       (0x3UL << MDMA_CTCR_SSIZE_Pos)               /*!< 0x00000030 */

+#define MDMA_CTCR_SSIZE           MDMA_CTCR_SSIZE_Msk                          /*!< Source data size */

+#define MDMA_CTCR_SSIZE_0         (0x1UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000010 */

+#define MDMA_CTCR_SSIZE_1         (0x2UL << MDMA_CTCR_SSIZE_Pos)                /*!< 0x00000020 */

+#define MDMA_CTCR_DSIZE_Pos       (6U)

+#define MDMA_CTCR_DSIZE_Msk       (0x3UL << MDMA_CTCR_DSIZE_Pos)               /*!< 0x000000C0 */

+#define MDMA_CTCR_DSIZE           MDMA_CTCR_DSIZE_Msk                          /*!< Destination data size */

+#define MDMA_CTCR_DSIZE_0         (0x1UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000040 */

+#define MDMA_CTCR_DSIZE_1         (0x2UL << MDMA_CTCR_DSIZE_Pos)                /*!< 0x00000080 */

+#define MDMA_CTCR_SINCOS_Pos      (8U)

+#define MDMA_CTCR_SINCOS_Msk      (0x3UL << MDMA_CTCR_SINCOS_Pos)              /*!< 0x00000300 */

+#define MDMA_CTCR_SINCOS          MDMA_CTCR_SINCOS_Msk                         /*!< Source increment offset size */

+#define MDMA_CTCR_SINCOS_0        (0x1UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000100 */

+#define MDMA_CTCR_SINCOS_1        (0x2UL << MDMA_CTCR_SINCOS_Pos)               /*!< 0x00000200 */

+#define MDMA_CTCR_DINCOS_Pos      (10U)

+#define MDMA_CTCR_DINCOS_Msk      (0x3UL << MDMA_CTCR_DINCOS_Pos)              /*!< 0x00000C00 */

+#define MDMA_CTCR_DINCOS          MDMA_CTCR_DINCOS_Msk                         /*!< Destination increment offset size */

+#define MDMA_CTCR_DINCOS_0        (0x1UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000400 */

+#define MDMA_CTCR_DINCOS_1        (0x2UL << MDMA_CTCR_DINCOS_Pos)               /*!< 0x00000800 */

+#define MDMA_CTCR_SBURST_Pos      (12U)

+#define MDMA_CTCR_SBURST_Msk      (0x7UL << MDMA_CTCR_SBURST_Pos)              /*!< 0x00007000 */

+#define MDMA_CTCR_SBURST          MDMA_CTCR_SBURST_Msk                         /*!< Source burst transfer configuration */

+#define MDMA_CTCR_SBURST_0        (0x1UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00001000 */

+#define MDMA_CTCR_SBURST_1        (0x2UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00002000 */

+#define MDMA_CTCR_SBURST_2        (0x4UL << MDMA_CTCR_SBURST_Pos)               /*!< 0x00004000 */

+#define MDMA_CTCR_DBURST_Pos      (15U)

+#define MDMA_CTCR_DBURST_Msk      (0x7UL << MDMA_CTCR_DBURST_Pos)              /*!< 0x00038000 */

+#define MDMA_CTCR_DBURST          MDMA_CTCR_DBURST_Msk                         /*!< Destination burst transfer configuration */

+#define MDMA_CTCR_DBURST_0        (0x1UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00008000 */

+#define MDMA_CTCR_DBURST_1        (0x2UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00010000 */

+#define MDMA_CTCR_DBURST_2        (0x4UL << MDMA_CTCR_DBURST_Pos)               /*!< 0x00020000 */

+#define MDMA_CTCR_TLEN_Pos        (18U)

+#define MDMA_CTCR_TLEN_Msk        (0x7FUL << MDMA_CTCR_TLEN_Pos)               /*!< 0x01FC0000 */

+#define MDMA_CTCR_TLEN            MDMA_CTCR_TLEN_Msk                           /*!< buffer Transfer Length (number of bytes - 1) */

+#define MDMA_CTCR_PKE_Pos         (25U)

+#define MDMA_CTCR_PKE_Msk         (0x1UL << MDMA_CTCR_PKE_Pos)                 /*!< 0x02000000 */

+#define MDMA_CTCR_PKE             MDMA_CTCR_PKE_Msk                            /*!< PacK Enable */

+#define MDMA_CTCR_PAM_Pos         (26U)

+#define MDMA_CTCR_PAM_Msk         (0x3UL << MDMA_CTCR_PAM_Pos)                 /*!< 0x0C000000 */

+#define MDMA_CTCR_PAM             MDMA_CTCR_PAM_Msk                            /*!< Padding/Alignement Mode */

+#define MDMA_CTCR_PAM_0           (0x1UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x4000000 */

+#define MDMA_CTCR_PAM_1           (0x2UL << MDMA_CTCR_PAM_Pos)                  /*!< 0x8000000 */

+#define MDMA_CTCR_TRGM_Pos        (28U)

+#define MDMA_CTCR_TRGM_Msk        (0x3UL << MDMA_CTCR_TRGM_Pos)                /*!< 0x30000000 */

+#define MDMA_CTCR_TRGM            MDMA_CTCR_TRGM_Msk                           /*!< Trigger Mode */

+#define MDMA_CTCR_TRGM_0          (0x1UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x10000000 */

+#define MDMA_CTCR_TRGM_1          (0x2UL << MDMA_CTCR_TRGM_Pos)                 /*!< 0x20000000 */

+#define MDMA_CTCR_SWRM_Pos        (30U)

+#define MDMA_CTCR_SWRM_Msk        (0x1UL << MDMA_CTCR_SWRM_Pos)                /*!< 0x40000000 */

+#define MDMA_CTCR_SWRM            MDMA_CTCR_SWRM_Msk                           /*!< SW Request Mode */

+#define MDMA_CTCR_BWM_Pos         (31U)

+#define MDMA_CTCR_BWM_Msk         (0x1UL << MDMA_CTCR_BWM_Pos)                 /*!< 0x80000000 */

+#define MDMA_CTCR_BWM             MDMA_CTCR_BWM_Msk                            /*!< Bufferable Write Mode */

+

+/********************  Bit definition for MDMA_CxBNDTR register  ****************/

+#define MDMA_CBNDTR_BNDT_Pos      (0U)

+#define MDMA_CBNDTR_BNDT_Msk      (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos)          /*!< 0x0001FFFF */

+#define MDMA_CBNDTR_BNDT          MDMA_CBNDTR_BNDT_Msk                         /*!< Block Number of data bytes to transfer */

+#define MDMA_CBNDTR_BRSUM_Pos     (18U)

+#define MDMA_CBNDTR_BRSUM_Msk     (0x1UL << MDMA_CBNDTR_BRSUM_Pos)             /*!< 0x00040000 */

+#define MDMA_CBNDTR_BRSUM         MDMA_CBNDTR_BRSUM_Msk                        /*!< Block Repeat Source address Update Mode */

+#define MDMA_CBNDTR_BRDUM_Pos     (19U)

+#define MDMA_CBNDTR_BRDUM_Msk     (0x1UL << MDMA_CBNDTR_BRDUM_Pos)             /*!< 0x00080000 */

+#define MDMA_CBNDTR_BRDUM         MDMA_CBNDTR_BRDUM_Msk                        /*!< Block Repeat Destination address Update Mode */

+#define MDMA_CBNDTR_BRC_Pos       (20U)

+#define MDMA_CBNDTR_BRC_Msk       (0xFFFUL << MDMA_CBNDTR_BRC_Pos)             /*!< 0xFFF00000 */

+#define MDMA_CBNDTR_BRC           MDMA_CBNDTR_BRC_Msk                          /*!< Block Repeat Count */

+

+/********************  Bit definition for MDMA_CxSAR register  ****************/

+#define MDMA_CSAR_SAR_Pos         (0U)

+#define MDMA_CSAR_SAR_Msk         (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CSAR_SAR             MDMA_CSAR_SAR_Msk                            /*!< Source address */

+

+/********************  Bit definition for MDMA_CxDAR register  ****************/

+#define MDMA_CDAR_DAR_Pos         (0U)

+#define MDMA_CDAR_DAR_Msk         (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CDAR_DAR             MDMA_CDAR_DAR_Msk                            /*!< Destination address */

+

+/********************  Bit definition for MDMA_CxBRUR  ************************/

+#define MDMA_CBRUR_SUV_Pos        (0U)

+#define MDMA_CBRUR_SUV_Msk        (0xFFFFUL << MDMA_CBRUR_SUV_Pos)             /*!< 0x0000FFFF */

+#define MDMA_CBRUR_SUV            MDMA_CBRUR_SUV_Msk                           /*!< Source address Update Value */

+#define MDMA_CBRUR_DUV_Pos        (16U)

+#define MDMA_CBRUR_DUV_Msk        (0xFFFFUL << MDMA_CBRUR_DUV_Pos)             /*!< 0xFFFF0000 */

+#define MDMA_CBRUR_DUV            MDMA_CBRUR_DUV_Msk                           /*!< Destination address Update Value */

+

+/********************  Bit definition for MDMA_CxLAR  *************************/

+#define MDMA_CLAR_LAR_Pos         (0U)

+#define MDMA_CLAR_LAR_Msk         (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CLAR_LAR             MDMA_CLAR_LAR_Msk                            /*!< Link Address Register */

+

+/********************  Bit definition for MDMA_CxTBR)  ************************/

+#define MDMA_CTBR_TSEL_Pos        (0U)

+#define MDMA_CTBR_TSEL_Msk        (0xFFUL << MDMA_CTBR_TSEL_Pos)               /*!< 0x000000FF */

+#define MDMA_CTBR_TSEL            MDMA_CTBR_TSEL_Msk                           /*!< Trigger SELection */

+#define MDMA_CTBR_SBUS_Pos        (16U)

+#define MDMA_CTBR_SBUS_Msk        (0x1UL << MDMA_CTBR_SBUS_Pos)                /*!< 0x00010000 */

+#define MDMA_CTBR_SBUS            MDMA_CTBR_SBUS_Msk                           /*!< Source BUS select */

+#define MDMA_CTBR_DBUS_Pos        (17U)

+#define MDMA_CTBR_DBUS_Msk        (0x1UL << MDMA_CTBR_DBUS_Pos)                /*!< 0x00020000 */

+#define MDMA_CTBR_DBUS            MDMA_CTBR_DBUS_Msk                           /*!< Destination BUS select */

+

+/********************  Bit definition for MDMA_CxMAR)  ************************/

+#define MDMA_CMAR_MAR_Pos         (0U)

+#define MDMA_CMAR_MAR_Msk         (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CMAR_MAR             MDMA_CMAR_MAR_Msk                            /*!< Mask address */

+

+/********************  Bit definition for MDMA_CxMDR)  ************************/

+#define MDMA_CMDR_MDR_Pos         (0U)

+#define MDMA_CMDR_MDR_Msk         (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos)          /*!< 0xFFFFFFFF */

+#define MDMA_CMDR_MDR             MDMA_CMDR_MDR_Msk                            /*!< Mask Data */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Operational Amplifier (OPAMP)                      */

+/*                                                                            */

+/******************************************************************************/

+/*********************  Bit definition for OPAMPx_CSR register  ***************/

+#define OPAMP_CSR_OPAMPxEN_Pos           (0U)

+#define OPAMP_CSR_OPAMPxEN_Msk           (0x1UL << OPAMP_CSR_OPAMPxEN_Pos)     /*!< 0x00000001 */

+#define OPAMP_CSR_OPAMPxEN               OPAMP_CSR_OPAMPxEN_Msk                /*!< OPAMP enable */

+#define OPAMP_CSR_FORCEVP_Pos            (1U)

+#define OPAMP_CSR_FORCEVP_Msk            (0x1UL << OPAMP_CSR_FORCEVP_Pos)      /*!< 0x00000002 */

+#define OPAMP_CSR_FORCEVP                OPAMP_CSR_FORCEVP_Msk                 /*!< Force internal reference on VP */

+

+#define OPAMP_CSR_VPSEL_Pos              (2U)

+#define OPAMP_CSR_VPSEL_Msk              (0x3UL << OPAMP_CSR_VPSEL_Pos)        /*!< 0x0000000C */

+#define OPAMP_CSR_VPSEL                  OPAMP_CSR_VPSEL_Msk                   /*!< Non inverted input selection */

+#define OPAMP_CSR_VPSEL_0                (0x1UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000004 */

+#define OPAMP_CSR_VPSEL_1                (0x2UL << OPAMP_CSR_VPSEL_Pos)         /*!< 0x00000008 */

+

+#define OPAMP_CSR_VMSEL_Pos              (5U)

+#define OPAMP_CSR_VMSEL_Msk              (0x3UL << OPAMP_CSR_VMSEL_Pos)        /*!< 0x00000060 */

+#define OPAMP_CSR_VMSEL                  OPAMP_CSR_VMSEL_Msk                   /*!< Inverting input selection */

+#define OPAMP_CSR_VMSEL_0                (0x1UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000020 */

+#define OPAMP_CSR_VMSEL_1                (0x2UL << OPAMP_CSR_VMSEL_Pos)         /*!< 0x00000040 */

+

+#define OPAMP_CSR_OPAHSM_Pos             (8U)

+#define OPAMP_CSR_OPAHSM_Msk             (0x1UL << OPAMP_CSR_OPAHSM_Pos)       /*!< 0x00000100 */

+#define OPAMP_CSR_OPAHSM                 OPAMP_CSR_OPAHSM_Msk                  /*!< Operational amplifier high speed mode */

+#define OPAMP_CSR_CALON_Pos              (11U)

+#define OPAMP_CSR_CALON_Msk              (0x1UL << OPAMP_CSR_CALON_Pos)        /*!< 0x00000800 */

+#define OPAMP_CSR_CALON                  OPAMP_CSR_CALON_Msk                   /*!< Calibration mode enable */

+

+#define OPAMP_CSR_CALSEL_Pos             (12U)

+#define OPAMP_CSR_CALSEL_Msk             (0x3UL << OPAMP_CSR_CALSEL_Pos)       /*!< 0x00003000 */

+#define OPAMP_CSR_CALSEL                 OPAMP_CSR_CALSEL_Msk                  /*!< Calibration selection */

+#define OPAMP_CSR_CALSEL_0               (0x1UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00001000 */

+#define OPAMP_CSR_CALSEL_1               (0x2UL << OPAMP_CSR_CALSEL_Pos)        /*!< 0x00002000 */

+

+#define OPAMP_CSR_PGGAIN_Pos             (14U)

+#define OPAMP_CSR_PGGAIN_Msk             (0xFUL << OPAMP_CSR_PGGAIN_Pos)       /*!< 0x0003C000 */

+#define OPAMP_CSR_PGGAIN                 OPAMP_CSR_PGGAIN_Msk                  /*!< Operational amplifier Programmable amplifier gain value */

+#define OPAMP_CSR_PGGAIN_0               (0x1UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00004000 */

+#define OPAMP_CSR_PGGAIN_1               (0x2UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00008000 */

+#define OPAMP_CSR_PGGAIN_2               (0x4UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00010000 */

+#define OPAMP_CSR_PGGAIN_3               (0x8UL << OPAMP_CSR_PGGAIN_Pos)        /*!< 0x00020000 */

+

+#define OPAMP_CSR_USERTRIM_Pos           (18U)

+#define OPAMP_CSR_USERTRIM_Msk           (0x1UL << OPAMP_CSR_USERTRIM_Pos)     /*!< 0x00040000 */

+#define OPAMP_CSR_USERTRIM               OPAMP_CSR_USERTRIM_Msk                /*!< User trimming enable */

+#define OPAMP_CSR_TSTREF_Pos             (29U)

+#define OPAMP_CSR_TSTREF_Msk             (0x1UL << OPAMP_CSR_TSTREF_Pos)       /*!< 0x20000000 */

+#define OPAMP_CSR_TSTREF                 OPAMP_CSR_TSTREF_Msk                  /*!< OpAmp calibration reference voltage output control */

+#define OPAMP_CSR_CALOUT_Pos             (30U)

+#define OPAMP_CSR_CALOUT_Msk             (0x1UL << OPAMP_CSR_CALOUT_Pos)       /*!< 0x40000000 */

+#define OPAMP_CSR_CALOUT                 OPAMP_CSR_CALOUT_Msk                  /*!< Operational amplifier calibration output */

+

+/*********************  Bit definition for OPAMP1_CSR register  ***************/

+#define OPAMP1_CSR_OPAEN_Pos              (0U)

+#define OPAMP1_CSR_OPAEN_Msk              (0x1UL << OPAMP1_CSR_OPAEN_Pos)      /*!< 0x00000001 */

+#define OPAMP1_CSR_OPAEN                  OPAMP1_CSR_OPAEN_Msk                 /*!< Operational amplifier1 Enable */

+#define OPAMP1_CSR_FORCEVP_Pos            (1U)

+#define OPAMP1_CSR_FORCEVP_Msk            (0x1UL << OPAMP1_CSR_FORCEVP_Pos)    /*!< 0x00000002 */

+#define OPAMP1_CSR_FORCEVP                OPAMP1_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */

+

+#define OPAMP1_CSR_VPSEL_Pos              (2U)

+#define OPAMP1_CSR_VPSEL_Msk              (0x3UL << OPAMP1_CSR_VPSEL_Pos)      /*!< 0x0000000C */

+#define OPAMP1_CSR_VPSEL                  OPAMP1_CSR_VPSEL_Msk                 /*!< Non inverted input selection */

+#define OPAMP1_CSR_VPSEL_0                (0x1UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000004 */

+#define OPAMP1_CSR_VPSEL_1                (0x2UL << OPAMP1_CSR_VPSEL_Pos)       /*!< 0x00000008 */

+

+#define OPAMP1_CSR_VMSEL_Pos              (5U)

+#define OPAMP1_CSR_VMSEL_Msk              (0x3UL << OPAMP1_CSR_VMSEL_Pos)      /*!< 0x00000060 */

+#define OPAMP1_CSR_VMSEL                  OPAMP1_CSR_VMSEL_Msk                 /*!< Inverting input selection */

+#define OPAMP1_CSR_VMSEL_0                (0x1UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000020 */

+#define OPAMP1_CSR_VMSEL_1                (0x2UL << OPAMP1_CSR_VMSEL_Pos)       /*!< 0x00000040 */

+

+#define OPAMP1_CSR_OPAHSM_Pos             (8U)

+#define OPAMP1_CSR_OPAHSM_Msk             (0x1UL << OPAMP1_CSR_OPAHSM_Pos)     /*!< 0x00000100 */

+#define OPAMP1_CSR_OPAHSM                 OPAMP1_CSR_OPAHSM_Msk                /*!< Operational amplifier1 high speed mode */

+#define OPAMP1_CSR_CALON_Pos              (11U)

+#define OPAMP1_CSR_CALON_Msk              (0x1UL << OPAMP1_CSR_CALON_Pos)      /*!< 0x00000800 */

+#define OPAMP1_CSR_CALON                  OPAMP1_CSR_CALON_Msk                 /*!< Calibration mode enable */

+

+#define OPAMP1_CSR_CALSEL_Pos             (12U)

+#define OPAMP1_CSR_CALSEL_Msk             (0x3UL << OPAMP1_CSR_CALSEL_Pos)     /*!< 0x00003000 */

+#define OPAMP1_CSR_CALSEL                 OPAMP1_CSR_CALSEL_Msk                /*!< Calibration selection */

+#define OPAMP1_CSR_CALSEL_0               (0x1UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00001000 */

+#define OPAMP1_CSR_CALSEL_1               (0x2UL << OPAMP1_CSR_CALSEL_Pos)      /*!< 0x00002000 */

+

+#define OPAMP1_CSR_PGGAIN_Pos             (14U)

+#define OPAMP1_CSR_PGGAIN_Msk             (0xFUL << OPAMP1_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */

+#define OPAMP1_CSR_PGGAIN                 OPAMP1_CSR_PGGAIN_Msk                /*!< Operational amplifier1 Programmable amplifier gain value */

+#define OPAMP1_CSR_PGGAIN_0               (0x1UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00004000 */

+#define OPAMP1_CSR_PGGAIN_1               (0x2UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00008000 */

+#define OPAMP1_CSR_PGGAIN_2               (0x4UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00010000 */

+#define OPAMP1_CSR_PGGAIN_3               (0x8UL << OPAMP1_CSR_PGGAIN_Pos)      /*!< 0x00020000 */

+

+#define OPAMP1_CSR_USERTRIM_Pos           (18U)

+#define OPAMP1_CSR_USERTRIM_Msk           (0x1UL << OPAMP1_CSR_USERTRIM_Pos)   /*!< 0x00040000 */

+#define OPAMP1_CSR_USERTRIM               OPAMP1_CSR_USERTRIM_Msk              /*!< User trimming enable */

+#define OPAMP1_CSR_TSTREF_Pos             (29U)

+#define OPAMP1_CSR_TSTREF_Msk             (0x1UL << OPAMP1_CSR_TSTREF_Pos)     /*!< 0x20000000 */

+#define OPAMP1_CSR_TSTREF                 OPAMP1_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */

+#define OPAMP1_CSR_CALOUT_Pos             (30U)

+#define OPAMP1_CSR_CALOUT_Msk             (0x1UL << OPAMP1_CSR_CALOUT_Pos)     /*!< 0x40000000 */

+#define OPAMP1_CSR_CALOUT                 OPAMP1_CSR_CALOUT_Msk                /*!< Operational amplifier1 calibration output */

+

+/*********************  Bit definition for OPAMP2_CSR register  ***************/

+#define OPAMP2_CSR_OPAEN_Pos              (0U)

+#define OPAMP2_CSR_OPAEN_Msk              (0x1UL << OPAMP2_CSR_OPAEN_Pos)      /*!< 0x00000001 */

+#define OPAMP2_CSR_OPAEN                  OPAMP2_CSR_OPAEN_Msk                 /*!< Operational amplifier2 Enable */

+#define OPAMP2_CSR_FORCEVP_Pos            (1U)

+#define OPAMP2_CSR_FORCEVP_Msk            (0x1UL << OPAMP2_CSR_FORCEVP_Pos)    /*!< 0x00000002 */

+#define OPAMP2_CSR_FORCEVP                OPAMP2_CSR_FORCEVP_Msk               /*!< Force internal reference on VP */

+

+#define OPAMP2_CSR_VPSEL_Pos              (2U)

+#define OPAMP2_CSR_VPSEL_Msk              (0x3UL << OPAMP2_CSR_VPSEL_Pos)      /*!< 0x0000000C */

+#define OPAMP2_CSR_VPSEL                  OPAMP2_CSR_VPSEL_Msk                 /*!< Non inverted input selection */

+#define OPAMP2_CSR_VPSEL_0                (0x1UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000004 */

+#define OPAMP2_CSR_VPSEL_1                (0x2UL << OPAMP2_CSR_VPSEL_Pos)       /*!< 0x00000008 */

+

+#define OPAMP2_CSR_VMSEL_Pos              (5U)

+#define OPAMP2_CSR_VMSEL_Msk              (0x3UL << OPAMP2_CSR_VMSEL_Pos)      /*!< 0x00000060 */

+#define OPAMP2_CSR_VMSEL                  OPAMP2_CSR_VMSEL_Msk                 /*!< Inverting input selection */

+#define OPAMP2_CSR_VMSEL_0                (0x1UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000020 */

+#define OPAMP2_CSR_VMSEL_1                (0x2UL << OPAMP2_CSR_VMSEL_Pos)       /*!< 0x00000040 */

+

+#define OPAMP2_CSR_OPAHSM_Pos             (8U)

+#define OPAMP2_CSR_OPAHSM_Msk             (0x1UL << OPAMP2_CSR_OPAHSM_Pos)     /*!< 0x00000100 */

+#define OPAMP2_CSR_OPAHSM                 OPAMP2_CSR_OPAHSM_Msk                /*!< Operational amplifier2 high speed mode */

+#define OPAMP2_CSR_CALON_Pos              (11U)

+#define OPAMP2_CSR_CALON_Msk              (0x1UL << OPAMP2_CSR_CALON_Pos)      /*!< 0x00000800 */

+#define OPAMP2_CSR_CALON                  OPAMP2_CSR_CALON_Msk                 /*!< Calibration mode enable */

+

+#define OPAMP2_CSR_CALSEL_Pos             (12U)

+#define OPAMP2_CSR_CALSEL_Msk             (0x3UL << OPAMP2_CSR_CALSEL_Pos)     /*!< 0x00003000 */

+#define OPAMP2_CSR_CALSEL                 OPAMP2_CSR_CALSEL_Msk                /*!< Calibration selection */

+#define OPAMP2_CSR_CALSEL_0               (0x1UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00001000 */

+#define OPAMP2_CSR_CALSEL_1               (0x2UL << OPAMP2_CSR_CALSEL_Pos)      /*!< 0x00002000 */

+

+#define OPAMP2_CSR_PGGAIN_Pos             (14U)

+#define OPAMP2_CSR_PGGAIN_Msk             (0xFUL << OPAMP2_CSR_PGGAIN_Pos)     /*!< 0x0003C000 */

+#define OPAMP2_CSR_PGGAIN                 OPAMP2_CSR_PGGAIN_Msk                /*!< Operational amplifier2 Programmable amplifier gain value */

+#define OPAMP2_CSR_PGGAIN_0               (0x1UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00004000 */

+#define OPAMP2_CSR_PGGAIN_1               (0x2UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00008000 */

+#define OPAMP2_CSR_PGGAIN_2               (0x4UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00010000 */

+#define OPAMP2_CSR_PGGAIN_3               (0x8UL << OPAMP2_CSR_PGGAIN_Pos)      /*!< 0x00020000 */

+

+#define OPAMP2_CSR_USERTRIM_Pos           (18U)

+#define OPAMP2_CSR_USERTRIM_Msk           (0x1UL << OPAMP2_CSR_USERTRIM_Pos)   /*!< 0x00040000 */

+#define OPAMP2_CSR_USERTRIM               OPAMP2_CSR_USERTRIM_Msk              /*!< User trimming enable */

+#define OPAMP2_CSR_TSTREF_Pos             (29U)

+#define OPAMP2_CSR_TSTREF_Msk             (0x1UL << OPAMP2_CSR_TSTREF_Pos)     /*!< 0x20000000 */

+#define OPAMP2_CSR_TSTREF                 OPAMP2_CSR_TSTREF_Msk                /*!< OpAmp calibration reference voltage output control */

+#define OPAMP2_CSR_CALOUT_Pos             (30U)

+#define OPAMP2_CSR_CALOUT_Msk             (0x1UL << OPAMP2_CSR_CALOUT_Pos)     /*!< 0x40000000 */

+#define OPAMP2_CSR_CALOUT                 OPAMP2_CSR_CALOUT_Msk                /*!< Operational amplifier2 calibration output */

+

+/*******************  Bit definition for OPAMP_OTR register  ******************/

+#define OPAMP_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP_OTR_TRIMOFFSETN            OPAMP_OTR_TRIMOFFSETN_Msk             /*!< Trim for NMOS differential pairs */

+#define OPAMP_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP_OTR_TRIMOFFSETP            OPAMP_OTR_TRIMOFFSETP_Msk             /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP1_OTR register  ******************/

+#define OPAMP1_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP1_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP1_OTR_TRIMOFFSETN            OPAMP1_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */

+#define OPAMP1_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP1_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP1_OTR_TRIMOFFSETP            OPAMP1_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP2_OTR register  ******************/

+#define OPAMP2_OTR_TRIMOFFSETN_Pos        (0U)

+#define OPAMP2_OTR_TRIMOFFSETN_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP2_OTR_TRIMOFFSETN            OPAMP2_OTR_TRIMOFFSETN_Msk           /*!< Trim for NMOS differential pairs */

+#define OPAMP2_OTR_TRIMOFFSETP_Pos        (8U)

+#define OPAMP2_OTR_TRIMOFFSETP_Msk        (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP2_OTR_TRIMOFFSETP            OPAMP2_OTR_TRIMOFFSETP_Msk           /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP_HSOTR register  ****************/

+#define OPAMP_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP_HSOTR_TRIMHSOFFSETN        OPAMP_HSOTR_TRIMHSOFFSETN_Msk         /*!< Trim for NMOS differential pairs */

+#define OPAMP_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP_HSOTR_TRIMHSOFFSETP        OPAMP_HSOTR_TRIMHSOFFSETP_Msk         /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP1_HSOTR register  ****************/

+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP1_HSOTR_TRIMHSOFFSETN        OPAMP1_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */

+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP1_HSOTR_TRIMHSOFFSETP        OPAMP1_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */

+

+/*******************  Bit definition for OPAMP2_HSOTR register  ****************/

+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos    (0U)

+#define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */

+#define OPAMP2_HSOTR_TRIMHSOFFSETN        OPAMP2_HSOTR_TRIMHSOFFSETN_Msk       /*!< Trim for NMOS differential pairs */

+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos    (8U)

+#define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk    (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */

+#define OPAMP2_HSOTR_TRIMHSOFFSETP        OPAMP2_HSOTR_TRIMHSOFFSETP_Msk       /*!< Trim for PMOS differential pairs */

+

+/******************************************************************************/

+/*                                                                            */

+/*                Parallel Synchronous Slave Interface (PSSI )                */

+/*                                                                            */

+/******************************************************************************/

+

+/********************  Bit definition for PSSI_CR register  *******************/

+#define PSSI_CR_OUTEN_Pos               (31U)

+#define PSSI_CR_OUTEN_Msk               (0x1UL << PSSI_CR_OUTEN_Pos)           /*!< 0x80000000 */

+#define PSSI_CR_OUTEN                   PSSI_CR_OUTEN_Msk                      /*!< Data direction selection */

+#define PSSI_CR_DMAEN_Pos               (30U)

+#define PSSI_CR_DMAEN_Msk               (0x1UL << PSSI_CR_DMAEN_Pos)           /*!< 0x40000000 */

+#define PSSI_CR_DMAEN                   PSSI_CR_DMAEN_Msk                      /*!< DMA enable */

+#define PSSI_CR_DERDYCFG_Pos            (18U)

+#define PSSI_CR_DERDYCFG_Msk            (0x7UL << PSSI_CR_DERDYCFG_Pos)        /*!< 0x001C0000 */

+#define PSSI_CR_DERDYCFG                PSSI_CR_DERDYCFG_Msk                   /*!< Data enable and ready configuration */

+#define PSSI_CR_ENABLE_Pos              (14U)

+#define PSSI_CR_ENABLE_Msk              (0x1UL << PSSI_CR_ENABLE_Pos)          /*!< 0x00004000 */

+#define PSSI_CR_ENABLE                  PSSI_CR_ENABLE_Msk                     /*!< PSSI enable */

+#define PSSI_CR_EDM_Pos                 (10U)

+#define PSSI_CR_EDM_Msk                 (0x3UL << PSSI_CR_EDM_Pos)             /*!< 0x00000C00 */

+#define PSSI_CR_EDM                     PSSI_CR_EDM_Msk                        /*!< Extended data mode */

+#define PSSI_CR_RDYPOL_Pos              (8U)

+#define PSSI_CR_RDYPOL_Msk              (0x1UL << PSSI_CR_RDYPOL_Pos)          /*!< 0x00000C00 */

+#define PSSI_CR_RDYPOL                  PSSI_CR_RDYPOL_Msk                     /*!< Ready polarity */

+#define PSSI_CR_DEPOL_Pos               (6U)

+#define PSSI_CR_DEPOL_Msk               (0x1UL << PSSI_CR_DEPOL_Pos)           /*!< 0x00000C00 */

+#define PSSI_CR_DEPOL                   PSSI_CR_DEPOL_Msk                      /*!<  Data enable polarity */

+#define PSSI_CR_CKPOL_Pos               (5U)

+#define PSSI_CR_CKPOL_Msk               (0x1UL << PSSI_CR_CKPOL_Pos)           /*!< 0x00000C00 */

+#define PSSI_CR_CKPOL                   PSSI_CR_CKPOL_Msk                      /*!< Parallel data clock polarity */

+/********************  Bit definition for PSSI_SR register  *******************/

+#define PSSI_SR_RTT1B_Pos               (3U)

+#define PSSI_SR_RTT1B_Msk               (0x1UL << PSSI_SR_RTT1B_Pos)           /*!< 0x00000008 */

+#define PSSI_SR_RTT1B                   PSSI_SR_RTT1B_Msk                      /*!< Ready to transfer one byte */

+#define PSSI_SR_RTT4B_Pos               (2U)

+#define PSSI_SR_RTT4B_Msk               (0x1UL << PSSI_SR_RTT4B_Pos)           /*!< 0x00000004 */

+#define PSSI_SR_RTT4B                   PSSI_SR_RTT4B_Msk                      /*!< Ready to transfer four bytes */

+/********************  Bit definition for PSSI_RIS register  *******************/

+#define PSSI_RIS_OVR_RIS_Pos            (1U)

+#define PSSI_RIS_OVR_RIS_Msk            (0x1UL << PSSI_RIS_OVR_RIS_Pos)        /*!< 0x00000002 */

+#define PSSI_RIS_OVR_RIS                PSSI_RIS_OVR_RIS_Msk                   /*!< Data buffer overrun/underrun raw interrupt status */

+/********************  Bit definition for PSSI_IER register  *******************/

+#define PSSI_IER_OVR_IE_Pos             (1U)

+#define PSSI_IER_OVR_IE_Msk             (0x1UL << PSSI_IER_OVR_IE_Pos)         /*!< 0x00000002 */

+#define PSSI_IER_OVR_IE                 PSSI_IER_OVR_IE_Msk                    /*!< Data buffer overrun/underrun interrupt enable */

+/********************  Bit definition for PSSI_MIS register  *******************/

+#define PSSI_MIS_OVR_MIS_Pos            (1U)

+#define PSSI_MIS_OVR_MIS_Msk            (0x1UL << PSSI_MIS_OVR_MIS_Pos)        /*!< 0x00000002 */

+#define PSSI_MIS_OVR_MIS                PSSI_MIS_OVR_MIS_Msk                   /*!< Data buffer overrun/underrun masked interrupt status */

+/********************  Bit definition for PSSI_ICR register  *******************/

+#define PSSI_ICR_OVR_ISC_Pos            (1U)

+#define PSSI_ICR_OVR_ISC_Msk            (0x1UL << PSSI_ICR_OVR_ISC_Pos)        /*!< 0x00000002 */

+#define PSSI_ICR_OVR_ISC                PSSI_ICR_OVR_ISC_Msk                   /*!< Data buffer overrun/underrun interrupt status clear */

+/********************  Bit definition for PSSI_DR register  *******************/

+#define PSSI_DR_DR_Pos                  (0U)

+#define PSSI_DR_DR_Msk                  (0xFFFFFFFFUL << PSSI_DR_DR_Pos)       /*!< 0xFFFFFFF */

+#define PSSI_DR_DR                      PSSI_DR_DR_Msk                         /*!< Data register  */

+

+/******************************************************************************/

+/*                                                                            */

+/*                              On The Fly Decryption                         */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for OTFDEC_CR register  ******************/

+#define OTFDEC_CR_ENC_Pos                      (0U)

+#define OTFDEC_CR_ENC_Msk                      (0x1UL << OTFDEC_CR_ENC_Pos)                  /*!< 0x00000001 */

+#define OTFDEC_CR_ENC                          OTFDEC_CR_ENC_Msk                             /*!< Encryption mode bit */

+

+/******************  Bit definition for OTFDEC_PRIVCFGR register  ************/

+#define OTFDEC_PRIVCFGR_PRIV_Pos               (0U)

+#define OTFDEC_PRIVCFGR_PRIV_Msk               (0x1UL << OTFDEC_PRIVCFGR_PRIV_Pos)           /*!< 0x00000001 */

+#define OTFDEC_PRIVCFGR_PRIV                   OTFDEC_PRIVCFGR_PRIV_Msk                      /*!< Privileged access protection */

+

+/******************  Bit definition for OTFDEC_REG_CONFIGR register  *********/

+#define OTFDEC_REG_CONFIGR_REG_EN_Pos          (0U)

+#define OTFDEC_REG_CONFIGR_REG_EN_Msk          (0x1UL << OTFDEC_REG_CONFIGR_REG_EN_Pos)      /*!< 0x00000001 */

+#define OTFDEC_REG_CONFIGR_REG_EN              OTFDEC_REG_CONFIGR_REG_EN_Msk                 /*!< Region on-the-fly decryption enable */

+

+#define OTFDEC_REG_CONFIGR_CONFIGLOCK_Pos      (1U)

+#define OTFDEC_REG_CONFIGR_CONFIGLOCK_Msk      (0x1UL << OTFDEC_REG_CONFIGR_CONFIGLOCK_Pos)  /*!< 0x00000002 */

+#define OTFDEC_REG_CONFIGR_CONFIGLOCK          OTFDEC_REG_CONFIGR_CONFIGLOCK_Msk             /*!< Region config lock */

+

+#define OTFDEC_REG_CONFIGR_KEYLOCK_Pos         (2U)

+#define OTFDEC_REG_CONFIGR_KEYLOCK_Msk         (0x1UL << OTFDEC_REG_CONFIGR_KEYLOCK_Pos)     /*!< 0x00000004 */

+#define OTFDEC_REG_CONFIGR_KEYLOCK             OTFDEC_REG_CONFIGR_KEYLOCK_Msk                /*!< Region key lock */

+

+#define OTFDEC_REG_CONFIGR_MODE_Pos            (4U)

+#define OTFDEC_REG_CONFIGR_MODE_Msk            (0x3UL << OTFDEC_REG_CONFIGR_MODE_Pos)        /*!< 0x00000030 */

+#define OTFDEC_REG_CONFIGR_MODE                OTFDEC_REG_CONFIGR_MODE_Msk                   /*!< Region operating mode */

+#define OTFDEC_REG_CONFIGR_MODE_0              (0x1UL << OTFDEC_REG_CONFIGR_MODE_Pos)        /*!< 0x00000010 */

+#define OTFDEC_REG_CONFIGR_MODE_1              (0x2UL << OTFDEC_REG_CONFIGR_MODE_Pos)        /*!< 0x00000020 */

+

+#define OTFDEC_REG_CONFIGR_KEYCRC_Pos          (8U)

+#define OTFDEC_REG_CONFIGR_KEYCRC_Msk          (0xFFUL << OTFDEC_REG_CONFIGR_KEYCRC_Pos)     /*!< 0x0000FF00 */

+#define OTFDEC_REG_CONFIGR_KEYCRC              OTFDEC_REG_CONFIGR_KEYCRC_Msk                 /*!< Region key 8-bit CRC */

+

+#define OTFDEC_REG_CONFIGR_VERSION_Pos         (16U)

+#define OTFDEC_REG_CONFIGR_VERSION_Msk         (0xFFFFUL << OTFDEC_REG_CONFIGR_VERSION_Pos)  /*!< 0xFFFF0000 */

+#define OTFDEC_REG_CONFIGR_VERSION             OTFDEC_REG_CONFIGR_VERSION_Msk                /*!< Region firmware version */

+

+/******************  Bit definition for OTFDEC_REG_START_ADDR register  ******/

+#define OTFDEC_REG_START_ADDR_Pos              (0U)

+#define OTFDEC_REG_START_ADDR_Msk              (0xFFFFFFFFUL << OTFDEC_REG_START_ADDR_Pos)   /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_START_ADDR                  OTFDEC_REG_START_ADDR_Msk                     /*!< Region AHB start address */

+

+/******************  Bit definition for OTFDEC_REG_END_ADDR register  ********/

+#define OTFDEC_REG_END_ADDR_Pos                (0U)

+#define OTFDEC_REG_END_ADDR_Msk                (0xFFFFFFFFUL << OTFDEC_REG_END_ADDR_Pos)     /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_END_ADDR                    OTFDEC_REG_END_ADDR_Msk                       /*!< Region AHB end address */

+

+/******************  Bit definition for OTFDEC_REG_NONCER0 register  *********/

+#define OTFDEC_REG_NONCER0_Pos                 (0U)

+#define OTFDEC_REG_NONCER0_Msk                 (0xFFFFFFFFUL << OTFDEC_REG_NONCER0_Pos)      /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_NONCER0                     OTFDEC_REG_NONCER0_Msk                        /*!< Region Nonce Register (LSB nonce[31:0]) */

+

+/******************  Bit definition for OTFDEC_REG_NONCER1 register  *********/

+#define OTFDEC_REG_NONCER1_Pos                 (0U)

+#define OTFDEC_REG_NONCER1_Msk                 (0xFFFFFFFFUL << OTFDEC_REG_NONCER1_Pos)      /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_NONCER1                     OTFDEC_REG_NONCER1_Msk                        /*!< Region Nonce Register (MSB nonce[63:32]) */

+

+/******************  Bit definition for OTFDEC_REG_KEYR0 register  ***********/

+#define OTFDEC_REG_KEYR0_Pos                   (0U)

+#define OTFDEC_REG_KEYR0_Msk                   (0xFFFFFFFFUL << OTFDEC_REG_KEYR0_Pos)        /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_KEYR0                       OTFDEC_REG_KEYR0_Msk                          /*!< Region Key Register (LSB key[31:0]) */

+

+/******************  Bit definition for OTFDEC_REG_KEYR1 register  ***********/

+#define OTFDEC_REG_KEYR1_Pos                   (0U)

+#define OTFDEC_REG_KEYR1_Msk                   (0xFFFFFFFFUL << OTFDEC_REG_KEYR1_Pos)        /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_KEYR1                       OTFDEC_REG_KEYR1_Msk                          /*!< Region Key Register (key[63:32]) */

+

+/******************  Bit definition for OTFDEC_REG_KEYR2 register  ***********/

+#define OTFDEC_REG_KEYR2_Pos                   (0U)

+#define OTFDEC_REG_KEYR2_Msk                   (0xFFFFFFFFUL << OTFDEC_REG_KEYR2_Pos)        /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_KEYR2                       OTFDEC_REG_KEYR2_Msk                          /*!< Region Key Register (key[95:64]) */

+

+/******************  Bit definition for OTFDEC_REG_KEYR3 register  ***********/

+#define OTFDEC_REG_KEYR3_Pos                   (0U)

+#define OTFDEC_REG_KEYR3_Msk                   (0xFFFFFFFFUL << OTFDEC_REG_KEYR3_Pos)        /*!< 0xFFFFFFFF */

+#define OTFDEC_REG_KEYR3                       OTFDEC_REG_KEYR3_Msk                          /*!< Region Key Register (key[127:96]) */

+

+/******************  Bit definition for OTFDEC_ISR register  *****************/

+#define OTFDEC_ISR_SEIF_Pos                    (0U)

+#define OTFDEC_ISR_SEIF_Msk                    (0x1UL << OTFDEC_ISR_SEIF_Pos)                /*!< 0x00000001 */

+#define OTFDEC_ISR_SEIF                        OTFDEC_ISR_SEIF_Msk                           /*!< Security Error Interrupt Flag status bit before enable (mask) */

+

+#define OTFDEC_ISR_XONEIF_Pos                  (1U)

+#define OTFDEC_ISR_XONEIF_Msk                  (0x1UL << OTFDEC_ISR_XONEIF_Pos)              /*!< 0x00000002 */

+#define OTFDEC_ISR_XONEIF                      OTFDEC_ISR_XONEIF_Msk                         /*!< Execute-only Error Interrupt Flag status bit before enable (mask) */

+

+#define OTFDEC_ISR_KEIF_Pos                    (2U)

+#define OTFDEC_ISR_KEIF_Msk                    (0x1UL << OTFDEC_ISR_KEIF_Pos)                /*!< 0x00000004 */

+#define OTFDEC_ISR_KEIF                        OTFDEC_ISR_KEIF_Msk                           /*!< Key Error Interrupt Flag status bit before enable (mask) */

+

+/******************  Bit definition  for OTFDEC_ICR register  *****************/

+#define OTFDEC_ICR_SEIF_Pos                    (0U)

+#define OTFDEC_ICR_SEIF_Msk                    (0x1UL << OTFDEC_ICR_SEIF_Pos)                /*!< 0x00000001 */

+#define OTFDEC_ICR_SEIF                        OTFDEC_ICR_SEIF_Msk                           /*!< Security Error Interrupt Flag clear bit */

+

+#define OTFDEC_ICR_XONEIF_Pos                  (1U)

+#define OTFDEC_ICR_XONEIF_Msk                  (0x1UL << OTFDEC_ICR_XONEIF_Pos)              /*!< 0x00000002 */

+#define OTFDEC_ICR_XONEIF                      OTFDEC_ICR_XONEIF_Msk                         /*!< Execute-only Error Interrupt Flag clear bit */

+

+#define OTFDEC_ICR_KEIF_Pos                    (2U)

+#define OTFDEC_ICR_KEIF_Msk                    (0x1UL << OTFDEC_ICR_KEIF_Pos)                /*!< 0x00000004 */

+#define OTFDEC_ICR_KEIF                        OTFDEC_ICR_KEIF_Msk                           /*!< Key Error Interrupt Flag clear bit */

+

+/******************  Bit definition for OTFDEC_IER register  *****************/

+#define OTFDEC_IER_SEIE_Pos                    (0U)

+#define OTFDEC_IER_SEIE_Msk                    (0x1UL << OTFDEC_IER_SEIE_Pos)                /*!< 0x00000001 */

+#define OTFDEC_IER_SEIE                        OTFDEC_IER_SEIE_Msk                           /*!< Security Error Interrupt Enable bit */

+

+#define OTFDEC_IER_XONEIE_Pos                  (1U)

+#define OTFDEC_IER_XONEIE_Msk                  (0x1UL << OTFDEC_IER_XONEIE_Pos)              /*!< 0x00000002 */

+#define OTFDEC_IER_XONEIE                      OTFDEC_IER_XONEIE_Msk                         /*!< Execute-only Error Interrupt Enable bit */

+

+#define OTFDEC_IER_KEIE_Pos                    (2U)

+#define OTFDEC_IER_KEIE_Msk                    (0x1UL << OTFDEC_IER_KEIE_Pos)                /*!< 0x00000004 */

+#define OTFDEC_IER_KEIE                        OTFDEC_IER_KEIE_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                             Power Control                                  */

+/*                                                                            */

+/******************************************************************************/

+/*************************  NUMBER OF POWER DOMAINS  **************************/

+#define POWER_DOMAINS_NUMBER           2U                                      /*!< 2 Domains */

+

+/********************  Bit definition for PWR_CR1 register  *******************/

+#define PWR_CR1_SRDRAMSO_Pos           (27U)

+#define PWR_CR1_SRDRAMSO_Msk           (0x1UL << PWR_CR1_SRDRAMSO_Pos)         /*!< 0x08000000 */

+#define PWR_CR1_SRDRAMSO               PWR_CR1_SRDRAMSO_Msk                    /*!< SmartRun Domain AHB Memory Shut-Off in DStop/DStop2 Low-Power Mode */

+#define PWR_CR1_HSITFSO_Pos            (26U)

+#define PWR_CR1_HSITFSO_Msk            (0x1UL << PWR_CR1_HSITFSO_Pos)          /*!< 0x04000000 */

+#define PWR_CR1_HSITFSO                PWR_CR1_HSITFSO_Msk                     /*!< High-Speed Interfaces USB and FDCAN Memories Shut-off in DStop/DStop2 Mode */

+#define PWR_CR1_GFXSO_Pos              (25U)

+#define PWR_CR1_GFXSO_Msk              (0x1UL << PWR_CR1_GFXSO_Pos)            /*!< 0x02000000 */

+#define PWR_CR1_GFXSO                  PWR_CR1_GFXSO_Msk                       /*!< GFXMMU and JPEG Memories Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_ITCMSO_Pos             (24U)

+#define PWR_CR1_ITCMSO_Msk             (0x1UL << PWR_CR1_ITCMSO_Pos)           /*!< 0x01000000 */

+#define PWR_CR1_ITCMSO                 PWR_CR1_ITCMSO_Msk                      /*!< Instruction TCM and ETM Memories Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_AHBRAM2SO_Pos          (23U)

+#define PWR_CR1_AHBRAM2SO_Msk          (0x1UL << PWR_CR1_AHBRAM2SO_Pos)        /*!< 0x00800000 */

+#define PWR_CR1_AHBRAM2SO              PWR_CR1_AHBRAM2SO_Msk                   /*!< AHB RAM2 Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_AHBRAM1SO_Pos          (22U)

+#define PWR_CR1_AHBRAM1SO_Msk          (0x1UL << PWR_CR1_AHBRAM1SO_Pos)        /*!< 0x00400000 */

+#define PWR_CR1_AHBRAM1SO              PWR_CR1_AHBRAM1SO_Msk                   /*!< AHB RAM1 Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_AXIRAM3SO_Pos          (21U)

+#define PWR_CR1_AXIRAM3SO_Msk          (0x1UL << PWR_CR1_AXIRAM3SO_Pos)        /*!< 0x00200000 */

+#define PWR_CR1_AXIRAM3SO              PWR_CR1_AXIRAM3SO_Msk                   /*!< AXI RAM3 Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_AXIRAM2SO_Pos          (20U)

+#define PWR_CR1_AXIRAM2SO_Msk          (0x1UL << PWR_CR1_AXIRAM2SO_Pos)        /*!< 0x00100000 */

+#define PWR_CR1_AXIRAM2SO              PWR_CR1_AXIRAM2SO_Msk                   /*!< AXI RAM2 Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_AXIRAM1SO_Pos          (19U)

+#define PWR_CR1_AXIRAM1SO_Msk          (0x1UL << PWR_CR1_AXIRAM1SO_Pos)        /*!< 0x00080000 */

+#define PWR_CR1_AXIRAM1SO              PWR_CR1_AXIRAM1SO_Msk                   /*!< AXI RAM1 Shut-Off in DStop/DStop2 Mode */

+#define PWR_CR1_ALS_Pos                (17U)

+#define PWR_CR1_ALS_Msk                (0x3UL << PWR_CR1_ALS_Pos)              /*!< 0x00060000 */

+#define PWR_CR1_ALS                    PWR_CR1_ALS_Msk                         /*!< Analog Voltage Detector level selection */

+#define PWR_CR1_ALS_0                  (0x1UL << PWR_CR1_ALS_Pos)              /*!< 0x00020000 */

+#define PWR_CR1_ALS_1                  (0x2UL << PWR_CR1_ALS_Pos)              /*!< 0x00040000 */

+#define PWR_CR1_AVDEN_Pos              (16U)

+#define PWR_CR1_AVDEN_Msk              (0x1UL << PWR_CR1_AVDEN_Pos)            /*!< 0x00010000 */

+#define PWR_CR1_AVDEN                  PWR_CR1_AVDEN_Msk                       /*!< Analog Voltage Detector Enable */

+#define PWR_CR1_SVOS_Pos               (14U)

+#define PWR_CR1_SVOS_Msk               (0x3UL << PWR_CR1_SVOS_Pos)             /*!< 0x0000C000 */

+#define PWR_CR1_SVOS                   PWR_CR1_SVOS_Msk                        /*!< System STOP mode Voltage Scaling selection */

+#define PWR_CR1_SVOS_0                 (0x1UL << PWR_CR1_SVOS_Pos)             /*!< 0x00004000 */

+#define PWR_CR1_SVOS_1                 (0x2UL << PWR_CR1_SVOS_Pos)             /*!< 0x00008000 */

+#define PWR_CR1_AVD_READY_Pos          (13U)

+#define PWR_CR1_AVD_READY_Msk          (0x1UL << PWR_CR1_AVD_READY_Pos)        /*!< 0x00002000 */

+#define PWR_CR1_AVD_READY              PWR_CR1_AVD_READY_Msk                   /*!< Analog Voltage Ready. */

+#define PWR_CR1_BOOSTE_Pos             (12U)

+#define PWR_CR1_BOOSTE_Msk             (0x1UL << PWR_CR1_BOOSTE_Pos)           /*!< 0x00001000 */

+#define PWR_CR1_BOOSTE                 PWR_CR1_BOOSTE_Msk                      /*!< Analog Switch VBoost control */

+#define PWR_CR1_FLPS_Pos               (9U)

+#define PWR_CR1_FLPS_Msk               (0x1UL << PWR_CR1_FLPS_Pos)             /*!< 0x00000200 */

+#define PWR_CR1_FLPS                   PWR_CR1_FLPS_Msk                        /*!< Flash low power mode in DSTOP */

+#define PWR_CR1_DBP_Pos                (8U)

+#define PWR_CR1_DBP_Msk                (0x1UL << PWR_CR1_DBP_Pos)              /*!< 0x00000100 */

+#define PWR_CR1_DBP                    PWR_CR1_DBP_Msk                         /*!< Disable Back-up domain Protection */

+#define PWR_CR1_PLS_Pos                (5U)

+#define PWR_CR1_PLS_Msk                (0x7UL << PWR_CR1_PLS_Pos)              /*!< 0x000000E0 */

+#define PWR_CR1_PLS                    PWR_CR1_PLS_Msk                         /*!< Programmable Voltage Detector level selection */

+#define PWR_CR1_PLS_0                  (0x1UL << PWR_CR1_PLS_Pos)              /*!< 0x00000020 */

+#define PWR_CR1_PLS_1                  (0x2UL << PWR_CR1_PLS_Pos)              /*!< 0x00000040 */

+#define PWR_CR1_PLS_2                  (0x4UL << PWR_CR1_PLS_Pos)              /*!< 0x00000080 */

+#define PWR_CR1_PVDEN_Pos              (4U)

+#define PWR_CR1_PVDEN_Msk              (0x1UL << PWR_CR1_PVDEN_Pos)            /*!< 0x00000010 */

+#define PWR_CR1_PVDEN                  PWR_CR1_PVDEN_Msk                       /*!< Programmable Voltage detector enable */

+#define PWR_CR1_LPDS_Pos               (0U)

+#define PWR_CR1_LPDS_Msk               (0x1UL << PWR_CR1_LPDS_Pos)             /*!< 0x00000001 */

+#define PWR_CR1_LPDS                   PWR_CR1_LPDS_Msk                        /*!< Low Power Deepsleep with SVOS3 */

+

+/*!< PVD level configuration */

+#define PWR_CR1_PLS_LEV0               (0UL)                                   /*!< PVD level 0 */

+#define PWR_CR1_PLS_LEV1_Pos           (5U)

+#define PWR_CR1_PLS_LEV1_Msk           (0x1UL << PWR_CR1_PLS_LEV1_Pos)         /*!< 0x00000020 */

+#define PWR_CR1_PLS_LEV1               PWR_CR1_PLS_LEV1_Msk                    /*!< PVD level 1 */

+#define PWR_CR1_PLS_LEV2_Pos           (6U)

+#define PWR_CR1_PLS_LEV2_Msk           (0x1UL << PWR_CR1_PLS_LEV2_Pos)         /*!< 0x00000040 */

+#define PWR_CR1_PLS_LEV2               PWR_CR1_PLS_LEV2_Msk                    /*!< PVD level 2 */

+#define PWR_CR1_PLS_LEV3_Pos           (5U)

+#define PWR_CR1_PLS_LEV3_Msk           (0x3UL << PWR_CR1_PLS_LEV3_Pos)         /*!< 0x00000060 */

+#define PWR_CR1_PLS_LEV3               PWR_CR1_PLS_LEV3_Msk                    /*!< PVD level 3 */

+#define PWR_CR1_PLS_LEV4_Pos           (7U)

+#define PWR_CR1_PLS_LEV4_Msk           (0x1UL << PWR_CR1_PLS_LEV4_Pos)         /*!< 0x00000080 */

+#define PWR_CR1_PLS_LEV4               PWR_CR1_PLS_LEV4_Msk                    /*!< PVD level 4 */

+#define PWR_CR1_PLS_LEV5_Pos           (5U)

+#define PWR_CR1_PLS_LEV5_Msk           (0x5UL << PWR_CR1_PLS_LEV5_Pos)         /*!< 0x000000A0 */

+#define PWR_CR1_PLS_LEV5               PWR_CR1_PLS_LEV5_Msk                    /*!< PVD level 5 */

+#define PWR_CR1_PLS_LEV6_Pos           (6U)

+#define PWR_CR1_PLS_LEV6_Msk           (0x3UL << PWR_CR1_PLS_LEV6_Pos)         /*!< 0x000000C0 */

+#define PWR_CR1_PLS_LEV6               PWR_CR1_PLS_LEV6_Msk                    /*!< PVD level 6 */

+#define PWR_CR1_PLS_LEV7_Pos           (5U)

+#define PWR_CR1_PLS_LEV7_Msk           (0x7UL << PWR_CR1_PLS_LEV7_Pos)         /*!< 0x000000E0 */

+#define PWR_CR1_PLS_LEV7               PWR_CR1_PLS_LEV7_Msk                    /*!< PVD level 7 */

+

+/*!< AVD level configuration */

+#define PWR_CR1_ALS_LEV0               (0UL)                                   /*!< AVD level 0 */

+#define PWR_CR1_ALS_LEV1_Pos           (17U)

+#define PWR_CR1_ALS_LEV1_Msk           (0x1UL << PWR_CR1_ALS_LEV1_Pos)         /*!< 0x00020000 */

+#define PWR_CR1_ALS_LEV1               PWR_CR1_ALS_LEV1_Msk                    /*!< AVD level 1 */

+#define PWR_CR1_ALS_LEV2_Pos           (18U)

+#define PWR_CR1_ALS_LEV2_Msk           (0x1UL << PWR_CR1_ALS_LEV2_Pos)         /*!< 0x00040000 */

+#define PWR_CR1_ALS_LEV2               PWR_CR1_ALS_LEV2_Msk                    /*!< AVD level 2 */

+#define PWR_CR1_ALS_LEV3_Pos           (17U)

+#define PWR_CR1_ALS_LEV3_Msk           (0x3UL << PWR_CR1_ALS_LEV3_Pos)         /*!< 0x00060000 */

+#define PWR_CR1_ALS_LEV3               PWR_CR1_ALS_LEV3_Msk                    /*!< AVD level 3 */

+

+/********************  Bit definition for PWR_CSR1 register  ******************/

+#define PWR_CSR1_MMCVDO_Pos            (17U)

+#define PWR_CSR1_MMCVDO_Msk            (0x1UL << PWR_CSR1_MMCVDO_Pos)          /*!< 0x00020000                        */

+#define PWR_CSR1_MMCVDO                PWR_CSR1_MMCVDO_Msk                     /*!< voltage detector output on VDDMMC */

+#define PWR_CSR1_AVDO_Pos              (16U)

+#define PWR_CSR1_AVDO_Msk              (0x1UL << PWR_CSR1_AVDO_Pos)            /*!< 0x00010000 */

+#define PWR_CSR1_AVDO                  PWR_CSR1_AVDO_Msk                       /*!< Analog Voltage Detect Output */

+#define PWR_CSR1_ACTVOS_Pos            (14U)

+#define PWR_CSR1_ACTVOS_Msk            (0x3UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x0000C000 */

+#define PWR_CSR1_ACTVOS                PWR_CSR1_ACTVOS_Msk                     /*!< Current actual used VOS for VDD11 Voltage Scaling */

+#define PWR_CSR1_ACTVOS_0              (0x1UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00004000 */

+#define PWR_CSR1_ACTVOS_1              (0x2UL << PWR_CSR1_ACTVOS_Pos)          /*!< 0x00008000 */

+#define PWR_CSR1_ACTVOSRDY_Pos         (13U)

+#define PWR_CSR1_ACTVOSRDY_Msk         (0x1UL << PWR_CSR1_ACTVOSRDY_Pos)       /*!< 0x00002000 */

+#define PWR_CSR1_ACTVOSRDY             PWR_CSR1_ACTVOSRDY_Msk                  /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling  */

+#define PWR_CSR1_PVDO_Pos              (4U)

+#define PWR_CSR1_PVDO_Msk              (0x1UL << PWR_CSR1_PVDO_Pos)            /*!< 0x00000010 */

+#define PWR_CSR1_PVDO                  PWR_CSR1_PVDO_Msk                       /*!< Programmable Voltage Detect Output */

+

+/********************  Bit definition for PWR_CR2 register  *******************/

+#define PWR_CR2_TEMPH_Pos              (23U)

+#define PWR_CR2_TEMPH_Msk              (0x1UL << PWR_CR2_TEMPH_Pos)            /*!< 0x00800000 */

+#define PWR_CR2_TEMPH                  PWR_CR2_TEMPH_Msk                       /*!< Monitored temperature level above high threshold */

+#define PWR_CR2_TEMPL_Pos              (22U)

+#define PWR_CR2_TEMPL_Msk              (0x1UL << PWR_CR2_TEMPL_Pos)            /*!< 0x00400000 */

+#define PWR_CR2_TEMPL                  PWR_CR2_TEMPL_Msk                       /*!< Monitored temperature level above low threshold */

+#define PWR_CR2_VBATH_Pos              (21U)

+#define PWR_CR2_VBATH_Msk              (0x1UL << PWR_CR2_VBATH_Pos)            /*!< 0x00200000 */

+#define PWR_CR2_VBATH                  PWR_CR2_VBATH_Msk                       /*!< Monitored VBAT level above high threshold */

+#define PWR_CR2_VBATL_Pos              (20U)

+#define PWR_CR2_VBATL_Msk              (0x1UL << PWR_CR2_VBATL_Pos)            /*!< 0x00100000 */

+#define PWR_CR2_VBATL                  PWR_CR2_VBATL_Msk                       /*!< Monitored VBAT level above low threshold */

+#define PWR_CR2_BRRDY_Pos              (16U)

+#define PWR_CR2_BRRDY_Msk              (0x1UL << PWR_CR2_BRRDY_Pos)            /*!< 0x00010000 */

+#define PWR_CR2_BRRDY                  PWR_CR2_BRRDY_Msk                       /*!< Backup regulator ready */

+#define PWR_CR2_MONEN_Pos              (4U)

+#define PWR_CR2_MONEN_Msk              (0x1UL << PWR_CR2_MONEN_Pos)            /*!< 0x00000010 */

+#define PWR_CR2_MONEN                  PWR_CR2_MONEN_Msk                       /*!< VBAT and temperature monitoring enable */

+#define PWR_CR2_BREN_Pos               (0U)

+#define PWR_CR2_BREN_Msk               (0x1UL << PWR_CR2_BREN_Pos)             /*!< 0x00000001 */

+#define PWR_CR2_BREN                   PWR_CR2_BREN_Msk                        /*!< Backup regulator enable */

+

+/********************  Bit definition for PWR_CR3 register  *******************/

+#define PWR_CR3_USB33RDY_Pos           (26U)

+#define PWR_CR3_USB33RDY_Msk           (0x1UL << PWR_CR3_USB33RDY_Pos)         /*!< 0x04000000 */

+#define PWR_CR3_USB33RDY               PWR_CR3_USB33RDY_Msk                    /*!< USB supply ready */

+#define PWR_CR3_USBREGEN_Pos           (25U)

+#define PWR_CR3_USBREGEN_Msk           (0x1UL << PWR_CR3_USBREGEN_Pos)         /*!< 0x02000000 */

+#define PWR_CR3_USBREGEN               PWR_CR3_USBREGEN_Msk                    /*!< USB regulator enable */

+#define PWR_CR3_USB33DEN_Pos           (24U)

+#define PWR_CR3_USB33DEN_Msk           (0x1UL << PWR_CR3_USB33DEN_Pos)         /*!< 0x01000000 */

+#define PWR_CR3_USB33DEN               PWR_CR3_USB33DEN_Msk                    /*!< VDD33_USB voltage level detector enable */

+#define PWR_CR3_SMPSEXTRDY_Pos         (16U)

+#define PWR_CR3_SMPSEXTRDY_Msk         (0x1UL << PWR_CR3_SMPSEXTRDY_Pos)       /*!< 0x00010000 */

+#define PWR_CR3_SMPSEXTRDY             PWR_CR3_SMPSEXTRDY_Msk                  /*!< SMPS External supply ready */

+#define PWR_CR3_VBRS_Pos               (9U)

+#define PWR_CR3_VBRS_Msk               (0x1UL << PWR_CR3_VBRS_Pos)             /*!< 0x00000200 */

+#define PWR_CR3_VBRS                   PWR_CR3_VBRS_Msk                        /*!< VBAT charging resistor selection */

+#define PWR_CR3_VBE_Pos                (8U)

+#define PWR_CR3_VBE_Msk                (0x1UL << PWR_CR3_VBE_Pos)              /*!< 0x00000100 */

+#define PWR_CR3_VBE                    PWR_CR3_VBE_Msk                         /*!< VBAT charging enable */

+#define PWR_CR3_SMPSLEVEL_Pos          (4U)

+#define PWR_CR3_SMPSLEVEL_Msk          (0x3UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000030 */

+#define PWR_CR3_SMPSLEVEL              PWR_CR3_SMPSLEVEL_Msk                   /*!< SMPS output Voltage */

+#define PWR_CR3_SMPSLEVEL_0            (0x1UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000010 */

+#define PWR_CR3_SMPSLEVEL_1            (0x2UL << PWR_CR3_SMPSLEVEL_Pos)        /*!< 0x00000020 */

+#define PWR_CR3_SMPSEXTHP_Pos          (3U)

+#define PWR_CR3_SMPSEXTHP_Msk          (0x1UL << PWR_CR3_SMPSEXTHP_Pos)        /*!< 0x00000008 */

+#define PWR_CR3_SMPSEXTHP              PWR_CR3_SMPSEXTHP_Msk                   /*!< SMPS forced ON and in High Power MR mode */

+#define PWR_CR3_SMPSEN_Pos             (2U)

+#define PWR_CR3_SMPSEN_Msk             (0x1UL << PWR_CR3_SMPSEN_Pos)           /*!< 0x00000004 */

+#define PWR_CR3_SMPSEN                 PWR_CR3_SMPSEN_Msk                      /*!< SMPS Enable */

+#define PWR_CR3_LDOEN_Pos              (1U)

+#define PWR_CR3_LDOEN_Msk              (0x1UL << PWR_CR3_LDOEN_Pos)            /*!< 0x00000002 */

+#define PWR_CR3_LDOEN                  PWR_CR3_LDOEN_Msk                       /*!< Low Drop Output regulator enable */

+#define PWR_CR3_BYPASS_Pos             (0U)

+#define PWR_CR3_BYPASS_Msk             (0x1UL << PWR_CR3_BYPASS_Pos)           /*!< 0x00000001 */

+#define PWR_CR3_BYPASS                 PWR_CR3_BYPASS_Msk                      /*!< Power Management Unit bypass */

+

+/********************  Bit definition for PWR_CPUCR register  *****************/

+#define PWR_CPUCR_RUN_SRD_Pos          (11U)

+#define PWR_CPUCR_RUN_SRD_Msk          (0x1UL << PWR_CPUCR_RUN_SRD_Pos)        /*!< 0x00000800 */

+#define PWR_CPUCR_RUN_SRD              PWR_CPUCR_RUN_SRD_Msk                   /*!< Keep system SRD domain in RUN mode regardless of the CPU sub-systems modes */

+#define PWR_CPUCR_CSSF_Pos             (9U)

+#define PWR_CPUCR_CSSF_Msk             (0x1UL << PWR_CPUCR_CSSF_Pos)           /*!< 0x00000200 */

+#define PWR_CPUCR_CSSF                 PWR_CPUCR_CSSF_Msk                      /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */

+#define PWR_CPUCR_SBF_Pos              (6U)

+#define PWR_CPUCR_SBF_Msk              (0x1UL << PWR_CPUCR_SBF_Pos)            /*!< 0x00000040 */

+#define PWR_CPUCR_SBF                  PWR_CPUCR_SBF_Msk                       /*!< System STANDBY Flag */

+#define PWR_CPUCR_STOPF_Pos            (5U)

+#define PWR_CPUCR_STOPF_Msk            (0x1UL << PWR_CPUCR_STOPF_Pos)          /*!< 0x00000020 */

+#define PWR_CPUCR_STOPF                PWR_CPUCR_STOPF_Msk                     /*!< STOP Flag */

+#define PWR_CPUCR_PDDS_SRD_Pos         (2U)

+#define PWR_CPUCR_PDDS_SRD_Msk         (0x1UL << PWR_CPUCR_PDDS_SRD_Pos)       /*!< 0x00000004 */

+#define PWR_CPUCR_PDDS_SRD             PWR_CPUCR_PDDS_SRD_Msk                  /*!< System SRD domain Power Down Deepsleep */

+#define PWR_CPUCR_RETDS_CD_Pos         (0U)

+#define PWR_CPUCR_RETDS_CD_Msk         (0x1UL << PWR_CPUCR_RETDS_CD_Pos)       /*!< 0x00000001 */

+#define PWR_CPUCR_RETDS_CD             PWR_CPUCR_RETDS_CD_Msk                  /*!< CD domain Power Down Deepsleep selection */

+/********************  Bit definition for PWR_SRDCR register  *****************/

+#define PWR_SRDCR_VOS_Pos              (14U)

+#define PWR_SRDCR_VOS_Msk              (0x3UL << PWR_SRDCR_VOS_Pos)             /*!< 0x0000C000 */

+#define PWR_SRDCR_VOS                  PWR_SRDCR_VOS_Msk                        /*!< Voltage Scaling selection according performance */

+#define PWR_SRDCR_VOS_0                (0x1UL << PWR_SRDCR_VOS_Pos)             /*!< 0x00004000 */

+#define PWR_SRDCR_VOS_1                (0x2UL << PWR_SRDCR_VOS_Pos)             /*!< 0x00008000 */

+#define PWR_SRDCR_VOSRDY_Pos           (13U)

+#define PWR_SRDCR_VOSRDY_Msk           (0x1UL << PWR_SRDCR_VOSRDY_Pos)          /*!< 0x00002000 */

+#define PWR_SRDCR_VOSRDY               PWR_SRDCR_VOSRDY_Msk                     /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */

+/******************  Bit definition for PWR_WKUPCR register  ******************/

+#define PWR_WKUPCR_WKUPC6_Pos          (5U)

+#define PWR_WKUPCR_WKUPC6_Msk          (0x1UL << PWR_WKUPCR_WKUPC6_Pos)        /*!< 0x00000020 */

+#define PWR_WKUPCR_WKUPC6              PWR_WKUPCR_WKUPC6_Msk                   /*!< Clear Wakeup Pin Flag 6 */

+#define PWR_WKUPCR_WKUPC5_Pos          (4U)

+#define PWR_WKUPCR_WKUPC5_Msk          (0x1UL << PWR_WKUPCR_WKUPC5_Pos)        /*!< 0x00000010 */

+#define PWR_WKUPCR_WKUPC5              PWR_WKUPCR_WKUPC5_Msk                   /*!< Clear Wakeup Pin Flag 5 */

+#define PWR_WKUPCR_WKUPC4_Pos          (3U)

+#define PWR_WKUPCR_WKUPC4_Msk          (0x1UL << PWR_WKUPCR_WKUPC4_Pos)        /*!< 0x00000008 */

+#define PWR_WKUPCR_WKUPC4              PWR_WKUPCR_WKUPC4_Msk                   /*!< Clear Wakeup Pin Flag 4 */

+#define PWR_WKUPCR_WKUPC3_Pos          (2U)

+#define PWR_WKUPCR_WKUPC3_Msk          (0x1UL << PWR_WKUPCR_WKUPC3_Pos)        /*!< 0x00000004 */

+#define PWR_WKUPCR_WKUPC3              PWR_WKUPCR_WKUPC3_Msk                   /*!< Clear Wakeup Pin Flag 3 */

+#define PWR_WKUPCR_WKUPC2_Pos          (1U)

+#define PWR_WKUPCR_WKUPC2_Msk          (0x1UL << PWR_WKUPCR_WKUPC2_Pos)        /*!< 0x00000002 */

+#define PWR_WKUPCR_WKUPC2              PWR_WKUPCR_WKUPC2_Msk                   /*!< Clear Wakeup Pin Flag 2 */

+#define PWR_WKUPCR_WKUPC1_Pos          (0U)

+#define PWR_WKUPCR_WKUPC1_Msk          (0x1UL << PWR_WKUPCR_WKUPC1_Pos)        /*!< 0x00000001 */

+#define PWR_WKUPCR_WKUPC1              PWR_WKUPCR_WKUPC1_Msk                   /*!< Clear Wakeup Pin Flag 1 */

+

+/********************  Bit definition for PWR_WKUPFR register  ****************/

+#define PWR_WKUPFR_WKUPF6_Pos          (5U)

+#define PWR_WKUPFR_WKUPF6_Msk          (0x1UL << PWR_WKUPFR_WKUPF6_Pos)        /*!< 0x00000020 */

+#define PWR_WKUPFR_WKUPF6              PWR_WKUPFR_WKUPF6_Msk                   /*!< Wakeup Pin Flag 6 */

+#define PWR_WKUPFR_WKUPF5_Pos          (4U)

+#define PWR_WKUPFR_WKUPF5_Msk          (0x1UL << PWR_WKUPFR_WKUPF5_Pos)        /*!< 0x00000010 */

+#define PWR_WKUPFR_WKUPF5              PWR_WKUPFR_WKUPF5_Msk                   /*!< Wakeup Pin Flag 5 */

+#define PWR_WKUPFR_WKUPF4_Pos          (3U)

+#define PWR_WKUPFR_WKUPF4_Msk          (0x1UL << PWR_WKUPFR_WKUPF4_Pos)        /*!< 0x00000008 */

+#define PWR_WKUPFR_WKUPF4              PWR_WKUPFR_WKUPF4_Msk                   /*!< Wakeup Pin Flag 4 */

+#define PWR_WKUPFR_WKUPF3_Pos          (2U)

+#define PWR_WKUPFR_WKUPF3_Msk          (0x1UL << PWR_WKUPFR_WKUPF3_Pos)        /*!< 0x00000004 */

+#define PWR_WKUPFR_WKUPF3              PWR_WKUPFR_WKUPF3_Msk                   /*!< Wakeup Pin Flag 3 */

+#define PWR_WKUPFR_WKUPF2_Pos          (1U)

+#define PWR_WKUPFR_WKUPF2_Msk          (0x1UL << PWR_WKUPFR_WKUPF2_Pos)        /*!< 0x00000002 */

+#define PWR_WKUPFR_WKUPF2              PWR_WKUPFR_WKUPF2_Msk                   /*!< Wakeup Pin Flag 2 */

+#define PWR_WKUPFR_WKUPF1_Pos          (0U)

+#define PWR_WKUPFR_WKUPF1_Msk          (0x1UL << PWR_WKUPFR_WKUPF1_Pos)        /*!< 0x00000001 */

+#define PWR_WKUPFR_WKUPF1              PWR_WKUPFR_WKUPF1_Msk                   /*!< Wakeup Pin Flag 1 */

+

+/******************  Bit definition for PWR_WKUPEPR register  *****************/

+#define PWR_WKUPEPR_WKUPPUPD6_Pos      (26U)

+#define PWR_WKUPEPR_WKUPPUPD6_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x0C000000 */

+#define PWR_WKUPEPR_WKUPPUPD6          PWR_WKUPEPR_WKUPPUPD6_Msk               /*!< Wakeup Pin pull configuration for WKUP6 */

+#define PWR_WKUPEPR_WKUPPUPD6_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x04000000 */

+#define PWR_WKUPEPR_WKUPPUPD6_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos)    /*!< 0x08000000 */

+#define PWR_WKUPEPR_WKUPPUPD5_Pos      (24U)

+#define PWR_WKUPEPR_WKUPPUPD5_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x03000000 */

+#define PWR_WKUPEPR_WKUPPUPD5          PWR_WKUPEPR_WKUPPUPD5_Msk               /*!< Wakeup Pin pull configuration for WKUP5 */

+#define PWR_WKUPEPR_WKUPPUPD5_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x01000000 */

+#define PWR_WKUPEPR_WKUPPUPD5_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos)    /*!< 0x02000000 */

+#define PWR_WKUPEPR_WKUPPUPD4_Pos      (22U)

+#define PWR_WKUPEPR_WKUPPUPD4_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00C00000 */

+#define PWR_WKUPEPR_WKUPPUPD4          PWR_WKUPEPR_WKUPPUPD4_Msk               /*!< Wakeup Pin pull configuration for WKUP4 */

+#define PWR_WKUPEPR_WKUPPUPD4_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00400000 */

+#define PWR_WKUPEPR_WKUPPUPD4_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos)    /*!< 0x00800000 */

+#define PWR_WKUPEPR_WKUPPUPD3_Pos      (20U)

+#define PWR_WKUPEPR_WKUPPUPD3_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00300000 */

+#define PWR_WKUPEPR_WKUPPUPD3          PWR_WKUPEPR_WKUPPUPD3_Msk               /*!< Wakeup Pin pull configuration for WKUP3 */

+#define PWR_WKUPEPR_WKUPPUPD3_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00100000 */

+#define PWR_WKUPEPR_WKUPPUPD3_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos)    /*!< 0x00200000 */

+#define PWR_WKUPEPR_WKUPPUPD2_Pos      (18U)

+#define PWR_WKUPEPR_WKUPPUPD2_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x000C0000 */

+#define PWR_WKUPEPR_WKUPPUPD2          PWR_WKUPEPR_WKUPPUPD2_Msk               /*!< Wakeup Pin pull configuration for WKUP2 */

+#define PWR_WKUPEPR_WKUPPUPD2_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00040000 */

+#define PWR_WKUPEPR_WKUPPUPD2_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos)    /*!< 0x00080000 */

+#define PWR_WKUPEPR_WKUPPUPD1_Pos      (16U)

+#define PWR_WKUPEPR_WKUPPUPD1_Msk      (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00030000 */

+#define PWR_WKUPEPR_WKUPPUPD1          PWR_WKUPEPR_WKUPPUPD1_Msk               /*!< Wakeup Pin pull configuration for WKUP1 */

+#define PWR_WKUPEPR_WKUPPUPD1_0        (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00010000 */

+#define PWR_WKUPEPR_WKUPPUPD1_1        (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos)    /*!< 0x00020000 */

+#define PWR_WKUPEPR_WKUPP6_Pos         (13U)

+#define PWR_WKUPEPR_WKUPP6_Msk         (0x1UL << PWR_WKUPEPR_WKUPP6_Pos)       /*!< 0x00002000 */

+#define PWR_WKUPEPR_WKUPP6             PWR_WKUPEPR_WKUPP6_Msk                  /*!< Wakeup Pin Polarity for WKUP6 */

+#define PWR_WKUPEPR_WKUPP5_Pos         (12U)

+#define PWR_WKUPEPR_WKUPP5_Msk         (0x1UL << PWR_WKUPEPR_WKUPP5_Pos)       /*!< 0x00001000 */

+#define PWR_WKUPEPR_WKUPP5             PWR_WKUPEPR_WKUPP5_Msk                  /*!< Wakeup Pin Polarity for WKUP5 */

+#define PWR_WKUPEPR_WKUPP4_Pos         (11U)

+#define PWR_WKUPEPR_WKUPP4_Msk         (0x1UL << PWR_WKUPEPR_WKUPP4_Pos)       /*!< 0x00000800 */

+#define PWR_WKUPEPR_WKUPP4             PWR_WKUPEPR_WKUPP4_Msk                  /*!< Wakeup Pin Polarity for WKUP4 */

+#define PWR_WKUPEPR_WKUPP3_Pos         (10U)

+#define PWR_WKUPEPR_WKUPP3_Msk         (0x1UL << PWR_WKUPEPR_WKUPP3_Pos)       /*!< 0x00000400 */

+#define PWR_WKUPEPR_WKUPP3             PWR_WKUPEPR_WKUPP3_Msk                  /*!< Wakeup Pin Polarity for WKUP3 */

+#define PWR_WKUPEPR_WKUPP2_Pos         (9U)

+#define PWR_WKUPEPR_WKUPP2_Msk         (0x1UL << PWR_WKUPEPR_WKUPP2_Pos)       /*!< 0x00000200 */

+#define PWR_WKUPEPR_WKUPP2             PWR_WKUPEPR_WKUPP2_Msk                  /*!< Wakeup Pin Polarity for WKUP2 */

+#define PWR_WKUPEPR_WKUPP1_Pos         (8U)

+#define PWR_WKUPEPR_WKUPP1_Msk         (0x1UL << PWR_WKUPEPR_WKUPP1_Pos)       /*!< 0x00000100 */

+#define PWR_WKUPEPR_WKUPP1             PWR_WKUPEPR_WKUPP1_Msk                  /*!< Wakeup Pin Polarity for WKUP1 */

+#define PWR_WKUPEPR_WKUPEN6_Pos        (5U)

+#define PWR_WKUPEPR_WKUPEN6_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos)      /*!< 0x00000020 */

+#define PWR_WKUPEPR_WKUPEN6            PWR_WKUPEPR_WKUPEN6_Msk                 /*!< Enable Wakeup Pin WKUP6 */

+#define PWR_WKUPEPR_WKUPEN5_Pos        (4U)

+#define PWR_WKUPEPR_WKUPEN5_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos)      /*!< 0x00000010 */

+#define PWR_WKUPEPR_WKUPEN5            PWR_WKUPEPR_WKUPEN5_Msk                 /*!< Enable Wakeup Pin WKUP5 */

+#define PWR_WKUPEPR_WKUPEN4_Pos        (3U)

+#define PWR_WKUPEPR_WKUPEN4_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos)      /*!< 0x00000008 */

+#define PWR_WKUPEPR_WKUPEN4            PWR_WKUPEPR_WKUPEN4_Msk                 /*!< Enable Wakeup Pin WKUP4 */

+#define PWR_WKUPEPR_WKUPEN3_Pos        (2U)

+#define PWR_WKUPEPR_WKUPEN3_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos)      /*!< 0x00000004 */

+#define PWR_WKUPEPR_WKUPEN3            PWR_WKUPEPR_WKUPEN3_Msk                 /*!< Enable Wakeup Pin WKUP3 */

+#define PWR_WKUPEPR_WKUPEN2_Pos        (1U)

+#define PWR_WKUPEPR_WKUPEN2_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos)      /*!< 0x00000002 */

+#define PWR_WKUPEPR_WKUPEN2            PWR_WKUPEPR_WKUPEN2_Msk                 /*!< Enable Wakeup Pin WKUP2 */

+#define PWR_WKUPEPR_WKUPEN1_Pos        (0U)

+#define PWR_WKUPEPR_WKUPEN1_Msk        (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos)      /*!< 0x00000001 */

+#define PWR_WKUPEPR_WKUPEN1            PWR_WKUPEPR_WKUPEN1_Msk                 /*!< Enable Wakeup Pin WKUP1 */

+#define PWR_WKUPEPR_WKUPEN_Pos         (0U)

+#define PWR_WKUPEPR_WKUPEN_Msk         (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos)      /*!< 0x0000003F */

+#define PWR_WKUPEPR_WKUPEN             PWR_WKUPEPR_WKUPEN_Msk                  /*!< Enable all Wakeup Pin */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Reset and Clock Control                            */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  RCC VERSION  ********************************/

+#define RCC_VER_2_0

+

+/********************  Bit definition for RCC_CR register  ********************/

+#define RCC_CR_HSION_Pos                       (0U)

+#define RCC_CR_HSION_Msk                       (0x1UL << RCC_CR_HSION_Pos)     /*!< 0x00000001 */

+#define RCC_CR_HSION                           RCC_CR_HSION_Msk                /*!< Internal High Speed clock enable */

+#define RCC_CR_HSIKERON_Pos                    (1U)

+#define RCC_CR_HSIKERON_Msk                    (0x1UL << RCC_CR_HSIKERON_Pos)  /*!< 0x00000002 */

+#define RCC_CR_HSIKERON                        RCC_CR_HSIKERON_Msk             /*!< Internal High Speed clock enable for some IPs Kernel */

+#define RCC_CR_HSIRDY_Pos                      (2U)

+#define RCC_CR_HSIRDY_Msk                      (0x1UL << RCC_CR_HSIRDY_Pos)    /*!< 0x00000004 */

+#define RCC_CR_HSIRDY                          RCC_CR_HSIRDY_Msk               /*!< Internal High Speed clock ready flag */

+#define RCC_CR_HSIDIV_Pos                      (3U)

+#define RCC_CR_HSIDIV_Msk                      (0x3UL << RCC_CR_HSIDIV_Pos)    /*!< 0x00000018 */

+#define RCC_CR_HSIDIV                          RCC_CR_HSIDIV_Msk               /*!< Internal High Speed clock divider selection */

+#define RCC_CR_HSIDIV_1                        (0x0UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000000 */

+#define RCC_CR_HSIDIV_2                        (0x1UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000008 */

+#define RCC_CR_HSIDIV_4                        (0x2UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000010 */

+#define RCC_CR_HSIDIV_8                        (0x3UL << RCC_CR_HSIDIV_Pos)     /*!< 0x00000018 */

+

+#define RCC_CR_HSIDIVF_Pos                     (5U)

+#define RCC_CR_HSIDIVF_Msk                     (0x1UL << RCC_CR_HSIDIVF_Pos)   /*!< 0x00000020 */

+#define RCC_CR_HSIDIVF                         RCC_CR_HSIDIVF_Msk              /*!< HSI Divider flag */

+#define RCC_CR_CSION_Pos                       (7U)

+#define RCC_CR_CSION_Msk                       (0x1UL << RCC_CR_CSION_Pos)     /*!< 0x00000080 */

+#define RCC_CR_CSION                           RCC_CR_CSION_Msk                /*!< The Internal RC 4MHz oscillator clock enable */

+#define RCC_CR_CSIRDY_Pos                      (8U)

+#define RCC_CR_CSIRDY_Msk                      (0x1UL << RCC_CR_CSIRDY_Pos)    /*!< 0x00000100 */

+#define RCC_CR_CSIRDY                          RCC_CR_CSIRDY_Msk               /*!< The Internal RC 4MHz oscillator clock ready */

+#define RCC_CR_CSIKERON_Pos                    (9U)

+#define RCC_CR_CSIKERON_Msk                    (0x1UL << RCC_CR_CSIKERON_Pos)  /*!< 0x00000200 */

+#define RCC_CR_CSIKERON                        RCC_CR_CSIKERON_Msk             /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */

+#define RCC_CR_HSI48ON_Pos                     (12U)

+#define RCC_CR_HSI48ON_Msk                     (0x1UL << RCC_CR_HSI48ON_Pos)   /*!< 0x00001000 */

+#define RCC_CR_HSI48ON                         RCC_CR_HSI48ON_Msk              /*!< HSI48 clock enable clock enable  */

+#define RCC_CR_HSI48RDY_Pos                    (13U)

+#define RCC_CR_HSI48RDY_Msk                    (0x1UL << RCC_CR_HSI48RDY_Pos)  /*!< 0x00002000 */

+#define RCC_CR_HSI48RDY                        RCC_CR_HSI48RDY_Msk             /*!< HSI48 clock ready */

+

+#define RCC_CR_CPUCKRDY_Pos                     (14U)

+#define RCC_CR_CPUCKRDY_Msk                     (0x1UL << RCC_CR_CPUCKRDY_Pos)   /*!< 0x00004000 */

+#define RCC_CR_CPUCKRDY                         RCC_CR_CPUCKRDY_Msk              /*!< CPU domain clocks ready flag  */

+#define RCC_CR_CDCKRDY_Pos                     (15U)

+#define RCC_CR_CDCKRDY_Msk                     (0x1UL << RCC_CR_CDCKRDY_Pos)   /*!< 0x00008000 */

+#define RCC_CR_CDCKRDY                         RCC_CR_CDCKRDY_Msk              /*!< CD domain clocks ready flag */

+

+#define RCC_CR_HSEON_Pos                       (16U)

+#define RCC_CR_HSEON_Msk                       (0x1UL << RCC_CR_HSEON_Pos)     /*!< 0x00010000 */

+#define RCC_CR_HSEON                           RCC_CR_HSEON_Msk                /*!< External High Speed clock enable */

+#define RCC_CR_HSERDY_Pos                      (17U)

+#define RCC_CR_HSERDY_Msk                      (0x1UL << RCC_CR_HSERDY_Pos)    /*!< 0x00020000 */

+#define RCC_CR_HSERDY                          RCC_CR_HSERDY_Msk               /*!< External High Speed clock ready */

+#define RCC_CR_HSEBYP_Pos                      (18U)

+#define RCC_CR_HSEBYP_Msk                      (0x1UL << RCC_CR_HSEBYP_Pos)    /*!< 0x00040000 */

+#define RCC_CR_HSEBYP                          RCC_CR_HSEBYP_Msk               /*!< External High Speed clock Bypass */

+#define RCC_CR_CSSHSEON_Pos                    (19U)

+#define RCC_CR_CSSHSEON_Msk                    (0x1UL << RCC_CR_CSSHSEON_Pos)  /*!< 0x00080000 */

+#define RCC_CR_CSSHSEON                        RCC_CR_CSSHSEON_Msk             /*!< HSE Clock security System enable */

+

+#define RCC_CR_HSEEXT_Pos                    (20U)

+#define RCC_CR_HSEEXT_Msk                    (0x1UL << RCC_CR_HSEEXT_Pos)  /*!< 0x00080000 */

+#define RCC_CR_HSEEXT                        RCC_CR_HSEEXT_Msk             /*!< HSE Clock security System enable */

+

+#define RCC_CR_PLL1ON_Pos                      (24U)

+#define RCC_CR_PLL1ON_Msk                      (0x1UL << RCC_CR_PLL1ON_Pos)    /*!< 0x01000000 */

+#define RCC_CR_PLL1ON                          RCC_CR_PLL1ON_Msk               /*!< System PLL1 clock enable */

+#define RCC_CR_PLL1RDY_Pos                     (25U)

+#define RCC_CR_PLL1RDY_Msk                     (0x1UL << RCC_CR_PLL1RDY_Pos)   /*!< 0x02000000 */

+#define RCC_CR_PLL1RDY                         RCC_CR_PLL1RDY_Msk              /*!< System PLL1 clock ready */

+#define RCC_CR_PLL2ON_Pos                      (26U)

+#define RCC_CR_PLL2ON_Msk                      (0x1UL << RCC_CR_PLL2ON_Pos)    /*!< 0x04000000 */

+#define RCC_CR_PLL2ON                          RCC_CR_PLL2ON_Msk               /*!< System PLL2 clock enable */

+#define RCC_CR_PLL2RDY_Pos                     (27U)

+#define RCC_CR_PLL2RDY_Msk                     (0x1UL << RCC_CR_PLL2RDY_Pos)   /*!< 0x08000000 */

+#define RCC_CR_PLL2RDY                         RCC_CR_PLL2RDY_Msk              /*!< System PLL2 clock ready */

+#define RCC_CR_PLL3ON_Pos                      (28U)

+#define RCC_CR_PLL3ON_Msk                      (0x1UL << RCC_CR_PLL3ON_Pos)    /*!< 0x10000000 */

+#define RCC_CR_PLL3ON                          RCC_CR_PLL3ON_Msk               /*!< System PLL3 clock enable */

+#define RCC_CR_PLL3RDY_Pos                     (29U)

+#define RCC_CR_PLL3RDY_Msk                     (0x1UL << RCC_CR_PLL3RDY_Pos)   /*!< 0x20000000 */

+#define RCC_CR_PLL3RDY                         RCC_CR_PLL3RDY_Msk              /*!< System PLL3 clock ready */

+

+/*Legacy */

+#define RCC_CR_PLLON_Pos                       (24U)

+#define RCC_CR_PLLON_Msk                       (0x1UL << RCC_CR_PLLON_Pos)     /*!< 0x01000000 */

+#define RCC_CR_PLLON                           RCC_CR_PLLON_Msk                /*!< System PLL clock enable */

+#define RCC_CR_PLLRDY_Pos                      (25U)

+#define RCC_CR_PLLRDY_Msk                      (0x1UL << RCC_CR_PLLRDY_Pos)    /*!< 0x02000000 */

+#define RCC_CR_PLLRDY                          RCC_CR_PLLRDY_Msk               /*!< System PLL clock ready */

+

+/********************  Bit definition for RCC_HSICFGR register  ***************/

+/*!< HSICAL configuration */

+#define RCC_HSICFGR_HSICAL_Pos                 (0U)

+#define RCC_HSICFGR_HSICAL_Msk                 (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */

+#define RCC_HSICFGR_HSICAL                     RCC_HSICFGR_HSICAL_Msk          /*!< HSICAL[11:0] bits */

+#define RCC_HSICFGR_HSICAL_0                   (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */

+#define RCC_HSICFGR_HSICAL_1                   (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */

+#define RCC_HSICFGR_HSICAL_2                   (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */

+#define RCC_HSICFGR_HSICAL_3                   (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */

+#define RCC_HSICFGR_HSICAL_4                   (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */

+#define RCC_HSICFGR_HSICAL_5                   (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */

+#define RCC_HSICFGR_HSICAL_6                   (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */

+#define RCC_HSICFGR_HSICAL_7                   (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */

+#define RCC_HSICFGR_HSICAL_8                   (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */

+#define RCC_HSICFGR_HSICAL_9                   (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */

+#define RCC_HSICFGR_HSICAL_10                  (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */

+#define RCC_HSICFGR_HSICAL_11                  (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */

+

+/*!< HSITRIM configuration */

+#define RCC_HSICFGR_HSITRIM_Pos                (24U)

+#define RCC_HSICFGR_HSITRIM_Msk                (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */

+#define RCC_HSICFGR_HSITRIM                    RCC_HSICFGR_HSITRIM_Msk         /*!< HSITRIM[6:0] bits */

+#define RCC_HSICFGR_HSITRIM_0                  (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */

+#define RCC_HSICFGR_HSITRIM_1                  (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */

+#define RCC_HSICFGR_HSITRIM_2                  (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */

+#define RCC_HSICFGR_HSITRIM_3                  (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */

+#define RCC_HSICFGR_HSITRIM_4                  (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */

+#define RCC_HSICFGR_HSITRIM_5                  (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */

+#define RCC_HSICFGR_HSITRIM_6                  (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */

+

+

+/********************  Bit definition for RCC_CRRCR register  *****************/

+

+/*!< HSI48CAL configuration */

+#define RCC_CRRCR_HSI48CAL_Pos                 (0U)

+#define RCC_CRRCR_HSI48CAL_Msk                 (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */

+#define RCC_CRRCR_HSI48CAL                     RCC_CRRCR_HSI48CAL_Msk          /*!< HSI48CAL[9:0] bits */

+#define RCC_CRRCR_HSI48CAL_0                   (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */

+#define RCC_CRRCR_HSI48CAL_1                   (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */

+#define RCC_CRRCR_HSI48CAL_2                   (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */

+#define RCC_CRRCR_HSI48CAL_3                   (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */

+#define RCC_CRRCR_HSI48CAL_4                   (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */

+#define RCC_CRRCR_HSI48CAL_5                   (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */

+#define RCC_CRRCR_HSI48CAL_6                   (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */

+#define RCC_CRRCR_HSI48CAL_7                   (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */

+#define RCC_CRRCR_HSI48CAL_8                   (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */

+#define RCC_CRRCR_HSI48CAL_9                   (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */

+

+

+/********************  Bit definition for RCC_CSICFGR register  *****************/

+/*!< CSICAL configuration */

+#define RCC_CSICFGR_CSICAL_Pos                 (0U)

+#define RCC_CSICFGR_CSICAL_Msk                 (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */

+#define RCC_CSICFGR_CSICAL                     RCC_CSICFGR_CSICAL_Msk          /*!< CSICAL[7:0] bits */

+#define RCC_CSICFGR_CSICAL_0                   (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */

+#define RCC_CSICFGR_CSICAL_1                   (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */

+#define RCC_CSICFGR_CSICAL_2                   (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */

+#define RCC_CSICFGR_CSICAL_3                   (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */

+#define RCC_CSICFGR_CSICAL_4                   (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */

+#define RCC_CSICFGR_CSICAL_5                   (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */

+#define RCC_CSICFGR_CSICAL_6                   (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */

+#define RCC_CSICFGR_CSICAL_7                   (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */

+

+/*!< CSITRIM configuration */

+#define RCC_CSICFGR_CSITRIM_Pos                (24U)

+#define RCC_CSICFGR_CSITRIM_Msk                (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */

+#define RCC_CSICFGR_CSITRIM                    RCC_CSICFGR_CSITRIM_Msk         /*!< CSITRIM[5:0] bits */

+#define RCC_CSICFGR_CSITRIM_0                  (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */

+#define RCC_CSICFGR_CSITRIM_1                  (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */

+#define RCC_CSICFGR_CSITRIM_2                  (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */

+#define RCC_CSICFGR_CSITRIM_3                  (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */

+#define RCC_CSICFGR_CSITRIM_4                  (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */

+#define RCC_CSICFGR_CSITRIM_5                  (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */

+

+/********************  Bit definition for RCC_CFGR register  ******************/

+/*!< SW configuration */

+#define RCC_CFGR_SW_Pos                        (0U)

+#define RCC_CFGR_SW_Msk                        (0x7UL << RCC_CFGR_SW_Pos)           /*!< 0x00000007 */

+#define RCC_CFGR_SW                            RCC_CFGR_SW_Msk                     /*!< SW[2:0] bits (System clock Switch) */

+#define RCC_CFGR_SW_0                          (0x1UL << RCC_CFGR_SW_Pos)           /*!< 0x00000001 */

+#define RCC_CFGR_SW_1                          (0x2UL << RCC_CFGR_SW_Pos)           /*!< 0x00000002 */

+#define RCC_CFGR_SW_2                          (0x4UL << RCC_CFGR_SW_Pos)           /*!< 0x00000004 */

+

+#define RCC_CFGR_SW_HSI                        (0x00000000UL)                       /*!< HSI selection as system clock */

+#define RCC_CFGR_SW_CSI                        (0x00000001UL)                       /*!< CSI selection as system clock */

+#define RCC_CFGR_SW_HSE                        (0x00000002UL)                       /*!< HSE selection as system clock */

+#define RCC_CFGR_SW_PLL1                       (0x00000003UL)                       /*!< PLL1 selection as system clock */

+

+/*!< SWS configuration */

+#define RCC_CFGR_SWS_Pos                       (3U)

+#define RCC_CFGR_SWS_Msk                       (0x7UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000038 */

+#define RCC_CFGR_SWS                           RCC_CFGR_SWS_Msk                    /*!< SWS[2:0] bits (System Clock Switch Status) */

+#define RCC_CFGR_SWS_0                         (0x1UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000008 */

+#define RCC_CFGR_SWS_1                         (0x2UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000010 */

+#define RCC_CFGR_SWS_2                         (0x4UL << RCC_CFGR_SWS_Pos)          /*!< 0x00000020 */

+

+#define RCC_CFGR_SWS_HSI                       (0x00000000UL)                       /*!< HSI used as system clock */

+#define RCC_CFGR_SWS_CSI                       (0x00000008UL)                       /*!< CSI used as system clock */

+#define RCC_CFGR_SWS_HSE                       (0x00000010UL)                       /*!< HSE used as system clock */

+#define RCC_CFGR_SWS_PLL1                      (0x00000018UL)                       /*!< PLL1 used as system clock */

+

+#define RCC_CFGR_STOPWUCK_Pos                  (6U)

+#define RCC_CFGR_STOPWUCK_Msk                  (0x1UL << RCC_CFGR_STOPWUCK_Pos)     /*!< 0x00000040 */

+#define RCC_CFGR_STOPWUCK                      RCC_CFGR_STOPWUCK_Msk                /*!< Wake Up from stop and CSS backup clock selection */

+

+#define RCC_CFGR_STOPKERWUCK_Pos               (7U)

+#define RCC_CFGR_STOPKERWUCK_Msk               (0x1UL << RCC_CFGR_STOPKERWUCK_Pos)  /*!< 0x00000080 */

+#define RCC_CFGR_STOPKERWUCK                   RCC_CFGR_STOPKERWUCK_Msk             /*!< Kernel Clock Selection after a Wake Up from STOP */

+

+/*!< RTCPRE configuration */

+#define RCC_CFGR_RTCPRE_Pos                    (8U)

+#define RCC_CFGR_RTCPRE_Msk                    (0x3FUL << RCC_CFGR_RTCPRE_Pos)

+#define RCC_CFGR_RTCPRE                        RCC_CFGR_RTCPRE_Msk                  /*!< 0x00003F00 */

+#define RCC_CFGR_RTCPRE_0                      (0x1UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000100 */

+#define RCC_CFGR_RTCPRE_1                      (0x2UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000200 */

+#define RCC_CFGR_RTCPRE_2                      (0x4UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000400 */

+#define RCC_CFGR_RTCPRE_3                      (0x8UL << RCC_CFGR_RTCPRE_Pos)        /*!< 0x00000800 */

+#define RCC_CFGR_RTCPRE_4                      (0x10UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00001000 */

+#define RCC_CFGR_RTCPRE_5                      (0x20UL << RCC_CFGR_RTCPRE_Pos)       /*!< 0x00002000 */

+

+

+/*!< TIMPRE configuration */

+#define RCC_CFGR_TIMPRE_Pos                    (15U)

+#define RCC_CFGR_TIMPRE_Msk                    (0x1UL << RCC_CFGR_TIMPRE_Pos)

+#define RCC_CFGR_TIMPRE                        RCC_CFGR_TIMPRE_Msk                  /*!< 0x00008000 */

+

+/*!< MCO1 configuration */

+#define RCC_CFGR_MCO1_Pos                      (22U)

+#define RCC_CFGR_MCO1_Msk                      (0x7UL << RCC_CFGR_MCO1_Pos)

+#define RCC_CFGR_MCO1                          RCC_CFGR_MCO1_Msk                       /*!< 0x01C00000 */

+#define RCC_CFGR_MCO1_0                        (0x1UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00400000 */

+#define RCC_CFGR_MCO1_1                        (0x2UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x00800000 */

+#define RCC_CFGR_MCO1_2                        (0x4UL <<  RCC_CFGR_MCO1_Pos)            /*!< 0x01000000 */

+

+#define RCC_CFGR_MCO1PRE_Pos                   (18U)

+#define RCC_CFGR_MCO1PRE_Msk                   (0xFUL << RCC_CFGR_MCO1PRE_Pos)

+#define RCC_CFGR_MCO1PRE                       RCC_CFGR_MCO1PRE_Msk                    /*!< 0x003C0000 */

+#define RCC_CFGR_MCO1PRE_0                     (0x1UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00040000 */

+#define RCC_CFGR_MCO1PRE_1                     (0x2UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00080000 */

+#define RCC_CFGR_MCO1PRE_2                     (0x4UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00100000 */

+#define RCC_CFGR_MCO1PRE_3                     (0x8UL << RCC_CFGR_MCO1PRE_Pos)          /*!< 0x00200000 */

+

+#define RCC_CFGR_MCO2PRE_Pos                   (25U)

+#define RCC_CFGR_MCO2PRE_Msk                   (0xFUL << RCC_CFGR_MCO2PRE_Pos)

+#define RCC_CFGR_MCO2PRE                       RCC_CFGR_MCO2PRE_Msk                    /*!< 0x1E000000 */

+#define RCC_CFGR_MCO2PRE_0                     (0x1UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x02000000 */

+#define RCC_CFGR_MCO2PRE_1                     (0x2UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x04000000 */

+#define RCC_CFGR_MCO2PRE_2                     (0x4UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x08000000 */

+#define RCC_CFGR_MCO2PRE_3                     (0x8UL << RCC_CFGR_MCO2PRE_Pos)          /*!< 0x10000000 */

+

+#define RCC_CFGR_MCO2_Pos                      (29U)

+#define RCC_CFGR_MCO2_Msk                      (0x7UL << RCC_CFGR_MCO2_Pos)

+#define RCC_CFGR_MCO2                          RCC_CFGR_MCO2_Msk                       /*!< 0xE0000000 */

+#define RCC_CFGR_MCO2_0                        (0x1UL << RCC_CFGR_MCO2_Pos)             /*!< 0x20000000 */

+#define RCC_CFGR_MCO2_1                        (0x2UL << RCC_CFGR_MCO2_Pos)             /*!< 0x40000000 */

+#define RCC_CFGR_MCO2_2                        (0x4UL << RCC_CFGR_MCO2_Pos)             /*!< 0x80000000 */

+

+/********************  Bit definition for RCC_D1CFGR register  ******************/

+/*!< D1HPRE configuration */

+#define RCC_CDCFGR1_HPRE_Pos                    (0U)

+#define RCC_CDCFGR1_HPRE_Msk                    (0xFUL << RCC_CDCFGR1_HPRE_Pos)  /*!< 0x0000000F */

+#define RCC_CDCFGR1_HPRE                        RCC_CDCFGR1_HPRE_Msk             /*!< HPRE[3:0] bits (AHB3 prescaler) */

+#define RCC_CDCFGR1_HPRE_0                      (0x1UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000001 */

+#define RCC_CDCFGR1_HPRE_1                      (0x2UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000002 */

+#define RCC_CDCFGR1_HPRE_2                      (0x4UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000004 */

+#define RCC_CDCFGR1_HPRE_3                      (0x8UL << RCC_CDCFGR1_HPRE_Pos)   /*!< 0x00000008 */

+

+#define RCC_CDCFGR1_HPRE_DIV1                   ((uint32_t)0x00000000)                 /*!< AHB3 Clock not divided */

+#define RCC_CDCFGR1_HPRE_DIV2_Pos               (3U)

+#define RCC_CDCFGR1_HPRE_DIV2_Msk               (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos)   /*!< 0x00000008 */

+#define RCC_CDCFGR1_HPRE_DIV2                   RCC_CDCFGR1_HPRE_DIV2_Msk              /*!< AHB3 Clock divided by 2 */

+#define RCC_CDCFGR1_HPRE_DIV4_Pos               (0U)

+#define RCC_CDCFGR1_HPRE_DIV4_Msk               (0x9UL << RCC_CDCFGR1_HPRE_DIV4_Pos)   /*!< 0x00000009 */

+#define RCC_CDCFGR1_HPRE_DIV4                   RCC_CDCFGR1_HPRE_DIV4_Msk              /*!< AHB3 Clock divided by 4 */

+#define RCC_CDCFGR1_HPRE_DIV8_Pos               (1U)

+#define RCC_CDCFGR1_HPRE_DIV8_Msk               (0x5UL << RCC_CDCFGR1_HPRE_DIV8_Pos)   /*!< 0x0000000A */

+#define RCC_CDCFGR1_HPRE_DIV8                   RCC_CDCFGR1_HPRE_DIV8_Msk              /*!< AHB3 Clock divided by 8 */

+#define RCC_CDCFGR1_HPRE_DIV16_Pos              (0U)

+#define RCC_CDCFGR1_HPRE_DIV16_Msk              (0xBUL << RCC_CDCFGR1_HPRE_DIV16_Pos)  /*!< 0x0000000B */

+#define RCC_CDCFGR1_HPRE_DIV16                  RCC_CDCFGR1_HPRE_DIV16_Msk             /*!< AHB3 Clock divided by 16 */

+#define RCC_CDCFGR1_HPRE_DIV64_Pos              (2U)

+#define RCC_CDCFGR1_HPRE_DIV64_Msk              (0x3UL << RCC_CDCFGR1_HPRE_DIV64_Pos)  /*!< 0x0000000C */

+#define RCC_CDCFGR1_HPRE_DIV64                  RCC_CDCFGR1_HPRE_DIV64_Msk             /*!< AHB3 Clock divided by 64 */

+#define RCC_CDCFGR1_HPRE_DIV128_Pos             (0U)

+#define RCC_CDCFGR1_HPRE_DIV128_Msk             (0xDUL << RCC_CDCFGR1_HPRE_DIV128_Pos) /*!< 0x0000000D */

+#define RCC_CDCFGR1_HPRE_DIV128                 RCC_CDCFGR1_HPRE_DIV128_Msk            /*!< AHB3 Clock divided by 128 */

+#define RCC_CDCFGR1_HPRE_DIV256_Pos             (1U)

+#define RCC_CDCFGR1_HPRE_DIV256_Msk             (0x7UL << RCC_CDCFGR1_HPRE_DIV256_Pos) /*!< 0x0000000E */

+#define RCC_CDCFGR1_HPRE_DIV256                 RCC_CDCFGR1_HPRE_DIV256_Msk            /*!< AHB3 Clock divided by 256 */

+#define RCC_CDCFGR1_HPRE_DIV512_Pos             (0U)

+#define RCC_CDCFGR1_HPRE_DIV512_Msk             (0xFUL << RCC_CDCFGR1_HPRE_DIV512_Pos) /*!< 0x0000000F */

+#define RCC_CDCFGR1_HPRE_DIV512                 RCC_CDCFGR1_HPRE_DIV512_Msk            /*!< AHB3 Clock divided by 512 */

+

+/*!< D1PPRE configuration */

+#define RCC_CDCFGR1_CDPPRE_Pos                  (4U)

+#define RCC_CDCFGR1_CDPPRE_Msk                  (0x7UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000070 */

+#define RCC_CDCFGR1_CDPPRE                      RCC_CDCFGR1_CDPPRE_Msk                 /*!< CDPRE[2:0] bits (APB3 prescaler) */

+#define RCC_CDCFGR1_CDPPRE_0                    (0x1UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000010 */

+#define RCC_CDCFGR1_CDPPRE_1                    (0x2UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000020 */

+#define RCC_CDCFGR1_CDPPRE_2                    (0x4UL << RCC_CDCFGR1_CDPPRE_Pos)      /*!< 0x00000040 */

+

+#define RCC_CDCFGR1_CDPPRE_DIV1                 ((uint32_t)0x00000000)                 /*!< APB3 clock not divided */

+#define RCC_CDCFGR1_CDPPRE_DIV2_Pos             (6U)

+#define RCC_CDCFGR1_CDPPRE_DIV2_Msk             (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_CDCFGR1_CDPPRE_DIV2                 RCC_CDCFGR1_CDPPRE_DIV2_Msk            /*!< APB3 clock divided by 2 */

+#define RCC_CDCFGR1_CDPPRE_DIV4_Pos             (4U)

+#define RCC_CDCFGR1_CDPPRE_DIV4_Msk             (0x5UL << RCC_CDCFGR1_CDPPRE_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_CDCFGR1_CDPPRE_DIV4                 RCC_CDCFGR1_CDPPRE_DIV4_Msk            /*!< APB3 clock divided by 4 */

+#define RCC_CDCFGR1_CDPPRE_DIV8_Pos             (5U)

+#define RCC_CDCFGR1_CDPPRE_DIV8_Msk             (0x3UL << RCC_CDCFGR1_CDPPRE_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_CDCFGR1_CDPPRE_DIV8                 RCC_CDCFGR1_CDPPRE_DIV8_Msk            /*!< APB3 clock divided by 8 */

+#define RCC_CDCFGR1_CDPPRE_DIV16_Pos            (4U)

+#define RCC_CDCFGR1_CDPPRE_DIV16_Msk            (0x7UL << RCC_CDCFGR1_CDPPRE_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_CDCFGR1_CDPPRE_DIV16                RCC_CDCFGR1_CDPPRE_DIV16_Msk            /*!< APB3 clock divided by 16 */

+

+#define RCC_CDCFGR1_CDCPRE_Pos                  (8U)

+#define RCC_CDCFGR1_CDCPRE_Msk                  (0xFUL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000F00 */

+#define RCC_CDCFGR1_CDCPRE                      RCC_CDCFGR1_CDCPRE_Msk                  /*!< CDCPRE[2:0] bits (Domain 1 Core prescaler) */

+#define RCC_CDCFGR1_CDCPRE_0                    (0x1UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000100 */

+#define RCC_CDCFGR1_CDCPRE_1                    (0x2UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000200 */

+#define RCC_CDCFGR1_CDCPRE_2                    (0x4UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000400 */

+#define RCC_CDCFGR1_CDCPRE_3                    (0x8UL << RCC_CDCFGR1_CDCPRE_Pos)       /*!< 0x00000800 */

+

+#define RCC_CDCFGR1_CDCPRE_DIV1                 ((uint32_t)0x00000000)                  /*!< Domain 1 Core clock not divided */

+#define RCC_CDCFGR1_CDCPRE_DIV2_Pos             (11U)

+#define RCC_CDCFGR1_CDCPRE_DIV2_Msk             (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos)  /*!< 0x00000800 */

+#define RCC_CDCFGR1_CDCPRE_DIV2                 RCC_CDCFGR1_CDCPRE_DIV2_Msk             /*!< Domain 1 Core clock divided by 2 */

+#define RCC_CDCFGR1_CDCPRE_DIV4_Pos             (8U)

+#define RCC_CDCFGR1_CDCPRE_DIV4_Msk             (0x9UL << RCC_CDCFGR1_CDCPRE_DIV4_Pos)  /*!< 0x00000900 */

+#define RCC_CDCFGR1_CDCPRE_DIV4                 RCC_CDCFGR1_CDCPRE_DIV4_Msk             /*!< Domain 1 Core clock divided by 4 */

+#define RCC_CDCFGR1_CDCPRE_DIV8_Pos             (9U)

+#define RCC_CDCFGR1_CDCPRE_DIV8_Msk             (0x5UL << RCC_CDCFGR1_CDCPRE_DIV8_Pos)  /*!< 0x00000A00 */

+#define RCC_CDCFGR1_CDCPRE_DIV8                 RCC_CDCFGR1_CDCPRE_DIV8_Msk             /*!< Domain 1 Core clock divided by 8 */

+#define RCC_CDCFGR1_CDCPRE_DIV16_Pos            (8U)

+#define RCC_CDCFGR1_CDCPRE_DIV16_Msk            (0xBUL << RCC_CDCFGR1_CDCPRE_DIV16_Pos) /*!< 0x00000B00 */

+#define RCC_CDCFGR1_CDCPRE_DIV16                RCC_CDCFGR1_CDCPRE_DIV16_Msk            /*!< Domain 1 Core clock divided by 16 */

+#define RCC_CDCFGR1_CDCPRE_DIV64_Pos            (10U)

+#define RCC_CDCFGR1_CDCPRE_DIV64_Msk            (0x3UL << RCC_CDCFGR1_CDCPRE_DIV64_Pos) /*!< 0x00000C00 */

+#define RCC_CDCFGR1_CDCPRE_DIV64                RCC_CDCFGR1_CDCPRE_DIV64_Msk            /*!< Domain 1 Core clock divided by 64 */

+#define RCC_CDCFGR1_CDCPRE_DIV128_Pos           (8U)

+#define RCC_CDCFGR1_CDCPRE_DIV128_Msk           (0xDUL << RCC_CDCFGR1_CDCPRE_DIV128_Pos)/*!< 0x00000D00 */

+#define RCC_CDCFGR1_CDCPRE_DIV128               RCC_CDCFGR1_CDCPRE_DIV128_Msk           /*!< Domain 1 Core clock divided by 128 */

+#define RCC_CDCFGR1_CDCPRE_DIV256_Pos           (9U)

+#define RCC_CDCFGR1_CDCPRE_DIV256_Msk           (0x7UL << RCC_CDCFGR1_CDCPRE_DIV256_Pos)/*!< 0x00000E00 */

+#define RCC_CDCFGR1_CDCPRE_DIV256               RCC_CDCFGR1_CDCPRE_DIV256_Msk           /*!< Domain 1 Core clock divided by 256 */

+#define RCC_CDCFGR1_CDCPRE_DIV512_Pos           (8U)

+#define RCC_CDCFGR1_CDCPRE_DIV512_Msk           (0xFUL << RCC_CDCFGR1_CDCPRE_DIV512_Pos)/*!< 0x00000F00 */

+#define RCC_CDCFGR1_CDCPRE_DIV512               RCC_CDCFGR1_CDCPRE_DIV512_Msk           /*!< Domain 1 Core clock divided by 512 */

+

+/********************  Bit definition for RCC_CDCFGR2 register  ******************/

+/*!< CDPPRE1 configuration */

+#define RCC_CDCFGR2_CDPPRE1_Pos                 (4U)

+#define RCC_CDCFGR2_CDPPRE1_Msk                 (0x7UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000070 */

+#define RCC_CDCFGR2_CDPPRE1                     RCC_CDCFGR2_CDPPRE1_Msk          /*!< D1PPRE1[2:0] bits (APB1 prescaler) */

+#define RCC_CDCFGR2_CDPPRE1_0                   (0x1UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000010 */

+#define RCC_CDCFGR2_CDPPRE1_1                   (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */

+#define RCC_CDCFGR2_CDPPRE1_2                   (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */

+

+#define RCC_CDCFGR2_CDPPRE1_DIV1                ((uint32_t)0x00000000)          /*!< APB1 clock not divided */

+#define RCC_CDCFGR2_CDPPRE1_DIV2_Pos            (6U)

+#define RCC_CDCFGR2_CDPPRE1_DIV2_Msk            (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_CDCFGR2_CDPPRE1_DIV2                RCC_CDCFGR2_CDPPRE1_DIV2_Msk     /*!< APB1 clock divided by 2 */

+#define RCC_CDCFGR2_CDPPRE1_DIV4_Pos            (4U)

+#define RCC_CDCFGR2_CDPPRE1_DIV4_Msk            (0x5UL << RCC_CDCFGR2_CDPPRE1_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_CDCFGR2_CDPPRE1_DIV4                RCC_CDCFGR2_CDPPRE1_DIV4_Msk     /*!< APB1 clock divided by 4 */

+#define RCC_CDCFGR2_CDPPRE1_DIV8_Pos            (5U)

+#define RCC_CDCFGR2_CDPPRE1_DIV8_Msk            (0x3UL << RCC_CDCFGR2_CDPPRE1_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_CDCFGR2_CDPPRE1_DIV8                RCC_CDCFGR2_CDPPRE1_DIV8_Msk     /*!< APB1 clock divided by 8 */

+#define RCC_CDCFGR2_CDPPRE1_DIV16_Pos           (4U)

+#define RCC_CDCFGR2_CDPPRE1_DIV16_Msk           (0x7UL << RCC_CDCFGR2_CDPPRE1_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_CDCFGR2_CDPPRE1_DIV16               RCC_CDCFGR2_CDPPRE1_DIV16_Msk    /*!< APB1 clock divided by 16 */

+

+/*!< CDPPRE2 configuration */

+#define RCC_CDCFGR2_CDPPRE2_Pos                 (8U)

+#define RCC_CDCFGR2_CDPPRE2_Msk                 (0x7UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000700 */

+#define RCC_CDCFGR2_CDPPRE2                     RCC_CDCFGR2_CDPPRE2_Msk          /*!< CDPPRE2[2:0] bits (APB2 prescaler) */

+#define RCC_CDCFGR2_CDPPRE2_0                   (0x1UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000100 */

+#define RCC_CDCFGR2_CDPPRE2_1                   (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */

+#define RCC_CDCFGR2_CDPPRE2_2                   (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */

+

+#define RCC_CDCFGR2_CDPPRE2_DIV1                ((uint32_t)0x00000000)          /*!< APB2 clock not divided */

+#define RCC_CDCFGR2_CDPPRE2_DIV2_Pos            (10U)

+#define RCC_CDCFGR2_CDPPRE2_DIV2_Msk            (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */

+#define RCC_CDCFGR2_CDPPRE2_DIV2                RCC_CDCFGR2_CDPPRE2_DIV2_Msk     /*!< APB2 clock divided by 2 */

+#define RCC_CDCFGR2_CDPPRE2_DIV4_Pos            (8U)

+#define RCC_CDCFGR2_CDPPRE2_DIV4_Msk            (0x5UL << RCC_CDCFGR2_CDPPRE2_DIV4_Pos) /*!< 0x00000500 */

+#define RCC_CDCFGR2_CDPPRE2_DIV4                RCC_CDCFGR2_CDPPRE2_DIV4_Msk     /*!< APB2 clock divided by 4 */

+#define RCC_CDCFGR2_CDPPRE2_DIV8_Pos            (9U)

+#define RCC_CDCFGR2_CDPPRE2_DIV8_Msk            (0x3UL << RCC_CDCFGR2_CDPPRE2_DIV8_Pos) /*!< 0x00000600 */

+#define RCC_CDCFGR2_CDPPRE2_DIV8                RCC_CDCFGR2_CDPPRE2_DIV8_Msk     /*!< APB2 clock divided by 8 */

+#define RCC_CDCFGR2_CDPPRE2_DIV16_Pos           (8U)

+#define RCC_CDCFGR2_CDPPRE2_DIV16_Msk           (0x7UL << RCC_CDCFGR2_CDPPRE2_DIV16_Pos) /*!< 0x00000700 */

+#define RCC_CDCFGR2_CDPPRE2_DIV16               RCC_CDCFGR2_CDPPRE2_DIV16_Msk    /*!< APB2 clock divided by 16 */

+

+/********************  Bit definition for RCC_SRDCFGR register  ******************/

+/*!< SRDPPRE configuration */

+#define RCC_SRDCFGR_SRDPPRE_Pos                  (4U)

+#define RCC_SRDCFGR_SRDPPRE_Msk                  (0x7UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000070 */

+#define RCC_SRDCFGR_SRDPPRE                      RCC_SRDCFGR_SRDPPRE_Msk           /*!< SRDPPRE1[2:0] bits (APB4 prescaler) */

+#define RCC_SRDCFGR_SRDPPRE_0                    (0x1UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000010 */

+#define RCC_SRDCFGR_SRDPPRE_1                    (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */

+#define RCC_SRDCFGR_SRDPPRE_2                    (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */

+

+#define RCC_SRDCFGR_SRDPPRE_DIV1                 ((uint32_t)0x00000000)          /*!< APB4 clock not divided */

+#define RCC_SRDCFGR_SRDPPRE_DIV2_Pos             (6U)

+#define RCC_SRDCFGR_SRDPPRE_DIV2_Msk             (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */

+#define RCC_SRDCFGR_SRDPPRE_DIV2                 RCC_SRDCFGR_SRDPPRE_DIV2_Msk      /*!< APB4 clock divided by 2 */

+#define RCC_SRDCFGR_SRDPPRE_DIV4_Pos             (4U)

+#define RCC_SRDCFGR_SRDPPRE_DIV4_Msk             (0x5UL << RCC_SRDCFGR_SRDPPRE_DIV4_Pos) /*!< 0x00000050 */

+#define RCC_SRDCFGR_SRDPPRE_DIV4                 RCC_SRDCFGR_SRDPPRE_DIV4_Msk      /*!< APB4 clock divided by 4 */

+#define RCC_SRDCFGR_SRDPPRE_DIV8_Pos             (5U)

+#define RCC_SRDCFGR_SRDPPRE_DIV8_Msk             (0x3UL << RCC_SRDCFGR_SRDPPRE_DIV8_Pos) /*!< 0x00000060 */

+#define RCC_SRDCFGR_SRDPPRE_DIV8                 RCC_SRDCFGR_SRDPPRE_DIV8_Msk      /*!< APB4 clock divided by 8 */

+#define RCC_SRDCFGR_SRDPPRE_DIV16_Pos            (4U)

+#define RCC_SRDCFGR_SRDPPRE_DIV16_Msk            (0x7UL << RCC_SRDCFGR_SRDPPRE_DIV16_Pos) /*!< 0x00000070 */

+#define RCC_SRDCFGR_SRDPPRE_DIV16                RCC_SRDCFGR_SRDPPRE_DIV16_Msk     /*!< APB4 clock divided by 16 */

+

+/********************  Bit definition for RCC_PLLCKSELR register  *************/

+

+#define RCC_PLLCKSELR_PLLSRC_Pos               (0U)

+#define RCC_PLLCKSELR_PLLSRC_Msk               (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */

+#define RCC_PLLCKSELR_PLLSRC                   RCC_PLLCKSELR_PLLSRC_Msk

+

+#define RCC_PLLCKSELR_PLLSRC_HSI               ((uint32_t)0x00000000)          /*!< HSI source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_CSI_Pos           (0U)

+#define RCC_PLLCKSELR_PLLSRC_CSI_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */

+#define RCC_PLLCKSELR_PLLSRC_CSI               RCC_PLLCKSELR_PLLSRC_CSI_Msk    /*!< CSI source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_HSE_Pos           (1U)

+#define RCC_PLLCKSELR_PLLSRC_HSE_Msk           (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */

+#define RCC_PLLCKSELR_PLLSRC_HSE               RCC_PLLCKSELR_PLLSRC_HSE_Msk    /*!< HSE source clock selected */

+#define RCC_PLLCKSELR_PLLSRC_NONE_Pos          (0U)

+#define RCC_PLLCKSELR_PLLSRC_NONE_Msk          (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */

+#define RCC_PLLCKSELR_PLLSRC_NONE              RCC_PLLCKSELR_PLLSRC_NONE_Msk   /*!< No source clock selected  */

+

+#define RCC_PLLCKSELR_DIVM1_Pos                (4U)

+#define RCC_PLLCKSELR_DIVM1_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */

+#define RCC_PLLCKSELR_DIVM1                    RCC_PLLCKSELR_DIVM1_Msk

+#define RCC_PLLCKSELR_DIVM1_0                  (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */

+#define RCC_PLLCKSELR_DIVM1_1                  (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */

+#define RCC_PLLCKSELR_DIVM1_2                  (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */

+#define RCC_PLLCKSELR_DIVM1_3                  (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */

+#define RCC_PLLCKSELR_DIVM1_4                  (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */

+#define RCC_PLLCKSELR_DIVM1_5                  (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */

+

+#define RCC_PLLCKSELR_DIVM2_Pos                (12U)

+#define RCC_PLLCKSELR_DIVM2_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */

+#define RCC_PLLCKSELR_DIVM2                    RCC_PLLCKSELR_DIVM2_Msk

+#define RCC_PLLCKSELR_DIVM2_0                  (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */

+#define RCC_PLLCKSELR_DIVM2_1                  (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */

+#define RCC_PLLCKSELR_DIVM2_2                  (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */

+#define RCC_PLLCKSELR_DIVM2_3                  (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */

+#define RCC_PLLCKSELR_DIVM2_4                  (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */

+#define RCC_PLLCKSELR_DIVM2_5                  (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */

+

+#define RCC_PLLCKSELR_DIVM3_Pos                (20U)

+#define RCC_PLLCKSELR_DIVM3_Msk                (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */

+#define RCC_PLLCKSELR_DIVM3                    RCC_PLLCKSELR_DIVM3_Msk

+#define RCC_PLLCKSELR_DIVM3_0                  (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */

+#define RCC_PLLCKSELR_DIVM3_1                  (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */

+#define RCC_PLLCKSELR_DIVM3_2                  (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */

+#define RCC_PLLCKSELR_DIVM3_3                  (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */

+#define RCC_PLLCKSELR_DIVM3_4                  (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */

+#define RCC_PLLCKSELR_DIVM3_5                  (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */

+

+/********************  Bit definition for RCC_PLLCFGR register  ***************/

+

+#define RCC_PLLCFGR_PLL1FRACEN_Pos             (0U)

+#define RCC_PLLCFGR_PLL1FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */

+#define RCC_PLLCFGR_PLL1FRACEN                 RCC_PLLCFGR_PLL1FRACEN_Msk

+#define RCC_PLLCFGR_PLL1VCOSEL_Pos             (1U)

+#define RCC_PLLCFGR_PLL1VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */

+#define RCC_PLLCFGR_PLL1VCOSEL                 RCC_PLLCFGR_PLL1VCOSEL_Msk

+#define RCC_PLLCFGR_PLL1RGE_Pos                (2U)

+#define RCC_PLLCFGR_PLL1RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */

+#define RCC_PLLCFGR_PLL1RGE                    RCC_PLLCFGR_PLL1RGE_Msk

+#define RCC_PLLCFGR_PLL1RGE_0                  (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL1RGE_1                  (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */

+#define RCC_PLLCFGR_PLL1RGE_2                  (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */

+#define RCC_PLLCFGR_PLL1RGE_3                  (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */

+

+#define RCC_PLLCFGR_PLL2FRACEN_Pos             (4U)

+#define RCC_PLLCFGR_PLL2FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */

+#define RCC_PLLCFGR_PLL2FRACEN                 RCC_PLLCFGR_PLL2FRACEN_Msk

+#define RCC_PLLCFGR_PLL2VCOSEL_Pos             (5U)

+#define RCC_PLLCFGR_PLL2VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */

+#define RCC_PLLCFGR_PLL2VCOSEL                 RCC_PLLCFGR_PLL2VCOSEL_Msk

+#define RCC_PLLCFGR_PLL2RGE_Pos                (6U)

+#define RCC_PLLCFGR_PLL2RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */

+#define RCC_PLLCFGR_PLL2RGE                    RCC_PLLCFGR_PLL2RGE_Msk

+#define RCC_PLLCFGR_PLL2RGE_0                  (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL2RGE_1                  (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */

+#define RCC_PLLCFGR_PLL2RGE_2                  (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */

+#define RCC_PLLCFGR_PLL2RGE_3                  (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */

+

+#define RCC_PLLCFGR_PLL3FRACEN_Pos             (8U)

+#define RCC_PLLCFGR_PLL3FRACEN_Msk             (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */

+#define RCC_PLLCFGR_PLL3FRACEN                 RCC_PLLCFGR_PLL3FRACEN_Msk

+#define RCC_PLLCFGR_PLL3VCOSEL_Pos             (9U)

+#define RCC_PLLCFGR_PLL3VCOSEL_Msk             (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */

+#define RCC_PLLCFGR_PLL3VCOSEL                 RCC_PLLCFGR_PLL3VCOSEL_Msk

+#define RCC_PLLCFGR_PLL3RGE_Pos                (10U)

+#define RCC_PLLCFGR_PLL3RGE_Msk                (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */

+#define RCC_PLLCFGR_PLL3RGE                    RCC_PLLCFGR_PLL3RGE_Msk

+#define RCC_PLLCFGR_PLL3RGE_0                  (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */

+#define RCC_PLLCFGR_PLL3RGE_1                  (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */

+#define RCC_PLLCFGR_PLL3RGE_2                  (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */

+#define RCC_PLLCFGR_PLL3RGE_3                  (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */

+

+#define RCC_PLLCFGR_DIVP1EN_Pos                (16U)

+#define RCC_PLLCFGR_DIVP1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */

+#define RCC_PLLCFGR_DIVP1EN                    RCC_PLLCFGR_DIVP1EN_Msk

+#define RCC_PLLCFGR_DIVQ1EN_Pos                (17U)

+#define RCC_PLLCFGR_DIVQ1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */

+#define RCC_PLLCFGR_DIVQ1EN                    RCC_PLLCFGR_DIVQ1EN_Msk

+#define RCC_PLLCFGR_DIVR1EN_Pos                (18U)

+#define RCC_PLLCFGR_DIVR1EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */

+#define RCC_PLLCFGR_DIVR1EN                    RCC_PLLCFGR_DIVR1EN_Msk

+

+#define RCC_PLLCFGR_DIVP2EN_Pos                (19U)

+#define RCC_PLLCFGR_DIVP2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */

+#define RCC_PLLCFGR_DIVP2EN                    RCC_PLLCFGR_DIVP2EN_Msk

+#define RCC_PLLCFGR_DIVQ2EN_Pos                (20U)

+#define RCC_PLLCFGR_DIVQ2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */

+#define RCC_PLLCFGR_DIVQ2EN                    RCC_PLLCFGR_DIVQ2EN_Msk

+#define RCC_PLLCFGR_DIVR2EN_Pos                (21U)

+#define RCC_PLLCFGR_DIVR2EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */

+#define RCC_PLLCFGR_DIVR2EN                    RCC_PLLCFGR_DIVR2EN_Msk

+

+#define RCC_PLLCFGR_DIVP3EN_Pos                (22U)

+#define RCC_PLLCFGR_DIVP3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */

+#define RCC_PLLCFGR_DIVP3EN                    RCC_PLLCFGR_DIVP3EN_Msk

+#define RCC_PLLCFGR_DIVQ3EN_Pos                (23U)

+#define RCC_PLLCFGR_DIVQ3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */

+#define RCC_PLLCFGR_DIVQ3EN                    RCC_PLLCFGR_DIVQ3EN_Msk

+#define RCC_PLLCFGR_DIVR3EN_Pos                (24U)

+#define RCC_PLLCFGR_DIVR3EN_Msk                (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */

+#define RCC_PLLCFGR_DIVR3EN                    RCC_PLLCFGR_DIVR3EN_Msk

+

+

+/********************  Bit definition for RCC_PLL1DIVR register  ***************/

+#define RCC_PLL1DIVR_N1_Pos                    (0U)

+#define RCC_PLL1DIVR_N1_Msk                    (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */

+#define RCC_PLL1DIVR_N1                        RCC_PLL1DIVR_N1_Msk

+#define RCC_PLL1DIVR_P1_Pos                    (9U)

+#define RCC_PLL1DIVR_P1_Msk                    (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL1DIVR_P1                        RCC_PLL1DIVR_P1_Msk

+#define RCC_PLL1DIVR_Q1_Pos                    (16U)

+#define RCC_PLL1DIVR_Q1_Msk                    (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */

+#define RCC_PLL1DIVR_Q1                        RCC_PLL1DIVR_Q1_Msk

+#define RCC_PLL1DIVR_R1_Pos                    (24U)

+#define RCC_PLL1DIVR_R1_Msk                    (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */

+#define RCC_PLL1DIVR_R1                        RCC_PLL1DIVR_R1_Msk

+

+/********************  Bit definition for RCC_PLL1FRACR register  ***************/

+#define RCC_PLL1FRACR_FRACN1_Pos               (3U)

+#define RCC_PLL1FRACR_FRACN1_Msk               (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL1FRACR_FRACN1                   RCC_PLL1FRACR_FRACN1_Msk

+

+/********************  Bit definition for RCC_PLL2DIVR register  ***************/

+#define RCC_PLL2DIVR_N2_Pos                    (0U)

+#define RCC_PLL2DIVR_N2_Msk                    (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */

+#define RCC_PLL2DIVR_N2                        RCC_PLL2DIVR_N2_Msk

+#define RCC_PLL2DIVR_P2_Pos                    (9U)

+#define RCC_PLL2DIVR_P2_Msk                    (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL2DIVR_P2                        RCC_PLL2DIVR_P2_Msk

+#define RCC_PLL2DIVR_Q2_Pos                    (16U)

+#define RCC_PLL2DIVR_Q2_Msk                    (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */

+#define RCC_PLL2DIVR_Q2                        RCC_PLL2DIVR_Q2_Msk

+#define RCC_PLL2DIVR_R2_Pos                    (24U)

+#define RCC_PLL2DIVR_R2_Msk                    (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */

+#define RCC_PLL2DIVR_R2                        RCC_PLL2DIVR_R2_Msk

+

+/********************  Bit definition for RCC_PLL2FRACR register  ***************/

+#define RCC_PLL2FRACR_FRACN2_Pos               (3U)

+#define RCC_PLL2FRACR_FRACN2_Msk               (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL2FRACR_FRACN2                   RCC_PLL2FRACR_FRACN2_Msk

+

+/********************  Bit definition for RCC_PLL3DIVR register  ***************/

+#define RCC_PLL3DIVR_N3_Pos                    (0U)

+#define RCC_PLL3DIVR_N3_Msk                    (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */

+#define RCC_PLL3DIVR_N3                        RCC_PLL3DIVR_N3_Msk

+#define RCC_PLL3DIVR_P3_Pos                    (9U)

+#define RCC_PLL3DIVR_P3_Msk                    (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */

+#define RCC_PLL3DIVR_P3                        RCC_PLL3DIVR_P3_Msk

+#define RCC_PLL3DIVR_Q3_Pos                    (16U)

+#define RCC_PLL3DIVR_Q3_Msk                    (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */

+#define RCC_PLL3DIVR_Q3                        RCC_PLL3DIVR_Q3_Msk

+#define RCC_PLL3DIVR_R3_Pos                    (24U)

+#define RCC_PLL3DIVR_R3_Msk                    (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */

+#define RCC_PLL3DIVR_R3                        RCC_PLL3DIVR_R3_Msk

+

+/********************  Bit definition for RCC_PLL3FRACR register  ***************/

+#define RCC_PLL3FRACR_FRACN3_Pos               (3U)

+#define RCC_PLL3FRACR_FRACN3_Msk               (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */

+#define RCC_PLL3FRACR_FRACN3                   RCC_PLL3FRACR_FRACN3_Msk

+

+/********************  Bit definition for RCC_CDCCIPR register  ***************/

+#define RCC_CDCCIPR_FMCSEL_Pos                 (0U)

+#define RCC_CDCCIPR_FMCSEL_Msk                 (0x3UL << RCC_CDCCIPR_FMCSEL_Pos)     /*!< 0x00000003 */

+#define RCC_CDCCIPR_FMCSEL                     RCC_CDCCIPR_FMCSEL_Msk

+#define RCC_CDCCIPR_FMCSEL_0                   (0x1UL << RCC_CDCCIPR_FMCSEL_Pos)     /*!< 0x00000001 */

+#define RCC_CDCCIPR_FMCSEL_1                   (0x2UL << RCC_CDCCIPR_FMCSEL_Pos)     /*!< 0x00000002 */

+#define RCC_CDCCIPR_OCTOSPISEL_Pos             (4U)

+#define RCC_CDCCIPR_OCTOSPISEL_Msk             (0x3UL << RCC_CDCCIPR_OCTOSPISEL_Pos) /*!< 0x00000030 */

+#define RCC_CDCCIPR_OCTOSPISEL                 RCC_CDCCIPR_OCTOSPISEL_Msk

+#define RCC_CDCCIPR_OCTOSPISEL_0               (0x1UL << RCC_CDCCIPR_OCTOSPISEL_Pos) /*!< 0x00000010 */

+#define RCC_CDCCIPR_OCTOSPISEL_1               (0x2UL << RCC_CDCCIPR_OCTOSPISEL_Pos) /*!< 0x00000020 */

+#define RCC_CDCCIPR_SDMMCSEL_Pos               (16U)

+#define RCC_CDCCIPR_SDMMCSEL_Msk               (0x1UL << RCC_CDCCIPR_SDMMCSEL_Pos)   /*!< 0x00010000 */

+#define RCC_CDCCIPR_SDMMCSEL                   RCC_CDCCIPR_SDMMCSEL_Msk

+#define RCC_CDCCIPR_CKPERSEL_Pos               (28U)

+#define RCC_CDCCIPR_CKPERSEL_Msk               (0x3UL << RCC_CDCCIPR_CKPERSEL_Pos)   /*!< 0x30000000 */

+#define RCC_CDCCIPR_CKPERSEL                   RCC_CDCCIPR_CKPERSEL_Msk

+#define RCC_CDCCIPR_CKPERSEL_0                 (0x1UL << RCC_CDCCIPR_CKPERSEL_Pos)   /*!< 0x10000000 */

+#define RCC_CDCCIPR_CKPERSEL_1                 (0x2UL << RCC_CDCCIPR_CKPERSEL_Pos)   /*!< 0x20000000 */

+

+/********************  Bit definition for RCC_CDCCIP1R register  ***************/

+#define RCC_CDCCIP1R_SAI1SEL_Pos               (0U)

+#define RCC_CDCCIP1R_SAI1SEL_Msk               (0x7UL << RCC_CDCCIP1R_SAI1SEL_Pos)   /*!< 0x00000007 */

+#define RCC_CDCCIP1R_SAI1SEL                   RCC_CDCCIP1R_SAI1SEL_Msk

+#define RCC_CDCCIP1R_SAI1SEL_0                 (0x1UL << RCC_CDCCIP1R_SAI1SEL_Pos)   /*!< 0x00000001 */

+#define RCC_CDCCIP1R_SAI1SEL_1                 (0x2UL << RCC_CDCCIP1R_SAI1SEL_Pos)   /*!< 0x00000002 */

+#define RCC_CDCCIP1R_SAI1SEL_2                 (0x4UL << RCC_CDCCIP1R_SAI1SEL_Pos)   /*!< 0x00000004 */

+

+#define RCC_CDCCIP1R_SAI2ASEL_Pos              (6U)

+#define RCC_CDCCIP1R_SAI2ASEL_Msk              (0x7UL << RCC_CDCCIP1R_SAI2ASEL_Pos)  /*!< 0x000001C0 */

+#define RCC_CDCCIP1R_SAI2ASEL                  RCC_CDCCIP1R_SAI2ASEL_Msk

+#define RCC_CDCCIP1R_SAI2ASEL_0                (0x1UL << RCC_CDCCIP1R_SAI2ASEL_Pos)  /*!< 0x00000040 */

+#define RCC_CDCCIP1R_SAI2ASEL_1                (0x2UL << RCC_CDCCIP1R_SAI2ASEL_Pos)  /*!< 0x00000080 */

+#define RCC_CDCCIP1R_SAI2ASEL_2                (0x4UL << RCC_CDCCIP1R_SAI2ASEL_Pos)  /*!< 0x00000100 */

+

+#define RCC_CDCCIP1R_SAI2BSEL_Pos              (9U)

+#define RCC_CDCCIP1R_SAI2BSEL_Msk              (0x7UL << RCC_CDCCIP1R_SAI2BSEL_Pos)  /*!< 0x00000E00 */

+#define RCC_CDCCIP1R_SAI2BSEL                  RCC_CDCCIP1R_SAI2BSEL_Msk

+#define RCC_CDCCIP1R_SAI2BSEL_0                (0x1UL << RCC_CDCCIP1R_SAI2BSEL_Pos)  /*!< 0x00000200 */

+#define RCC_CDCCIP1R_SAI2BSEL_1                (0x2UL << RCC_CDCCIP1R_SAI2BSEL_Pos)  /*!< 0x00000400 */

+#define RCC_CDCCIP1R_SAI2BSEL_2                (0x4UL << RCC_CDCCIP1R_SAI2BSEL_Pos)  /*!< 0x00000800 */

+

+#define RCC_CDCCIP1R_SPI123SEL_Pos             (12U)

+#define RCC_CDCCIP1R_SPI123SEL_Msk             (0x7UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */

+#define RCC_CDCCIP1R_SPI123SEL                 RCC_CDCCIP1R_SPI123SEL_Msk

+#define RCC_CDCCIP1R_SPI123SEL_0               (0x1UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */

+#define RCC_CDCCIP1R_SPI123SEL_1               (0x2UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */

+#define RCC_CDCCIP1R_SPI123SEL_2               (0x4UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */

+

+#define RCC_CDCCIP1R_SPI45SEL_Pos              (16U)

+#define RCC_CDCCIP1R_SPI45SEL_Msk              (0x7UL << RCC_CDCCIP1R_SPI45SEL_Pos)  /*!< 0x00070000 */

+#define RCC_CDCCIP1R_SPI45SEL                  RCC_CDCCIP1R_SPI45SEL_Msk

+#define RCC_CDCCIP1R_SPI45SEL_0                (0x1UL << RCC_CDCCIP1R_SPI45SEL_Pos)  /*!< 0x00010000 */

+#define RCC_CDCCIP1R_SPI45SEL_1                (0x2UL << RCC_CDCCIP1R_SPI45SEL_Pos)  /*!< 0x00020000 */

+#define RCC_CDCCIP1R_SPI45SEL_2                (0x4UL << RCC_CDCCIP1R_SPI45SEL_Pos)  /*!< 0x00040000 */

+

+#define RCC_CDCCIP1R_SPDIFSEL_Pos              (20U)

+#define RCC_CDCCIP1R_SPDIFSEL_Msk              (0x3UL << RCC_CDCCIP1R_SPDIFSEL_Pos)  /*!< 0x00300000 */

+#define RCC_CDCCIP1R_SPDIFSEL                  RCC_CDCCIP1R_SPDIFSEL_Msk

+#define RCC_CDCCIP1R_SPDIFSEL_0                (0x1UL << RCC_CDCCIP1R_SPDIFSEL_Pos)  /*!< 0x00100000 */

+#define RCC_CDCCIP1R_SPDIFSEL_1                (0x2UL << RCC_CDCCIP1R_SPDIFSEL_Pos)  /*!< 0x00200000 */

+

+#define RCC_CDCCIP1R_DFSDM1SEL_Pos             (24U)

+#define RCC_CDCCIP1R_DFSDM1SEL_Msk             (0x1UL << RCC_CDCCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */

+#define RCC_CDCCIP1R_DFSDM1SEL                 RCC_CDCCIP1R_DFSDM1SEL_Msk

+

+#define RCC_CDCCIP1R_FDCANSEL_Pos              (28U)

+#define RCC_CDCCIP1R_FDCANSEL_Msk              (0x3UL << RCC_CDCCIP1R_FDCANSEL_Pos)  /*!< 0x30000000 */

+#define RCC_CDCCIP1R_FDCANSEL                  RCC_CDCCIP1R_FDCANSEL_Msk

+#define RCC_CDCCIP1R_FDCANSEL_0                (0x1UL << RCC_CDCCIP1R_FDCANSEL_Pos)  /*!< 0x10000000 */

+#define RCC_CDCCIP1R_FDCANSEL_1                (0x2UL << RCC_CDCCIP1R_FDCANSEL_Pos)  /*!< 0x20000000 */

+

+#define RCC_CDCCIP1R_SWPSEL_Pos                (31U)

+#define RCC_CDCCIP1R_SWPSEL_Msk                (0x1UL << RCC_CDCCIP1R_SWPSEL_Pos)    /*!< 0x80000000 */

+#define RCC_CDCCIP1R_SWPSEL                    RCC_CDCCIP1R_SWPSEL_Msk

+

+/********************  Bit definition for RCC_CDCCIP2R register  ***************/

+#define RCC_CDCCIP2R_USART234578SEL_Pos        (0U)

+#define RCC_CDCCIP2R_USART234578SEL_Msk        (0x7UL << RCC_CDCCIP2R_USART234578SEL_Pos)   /*!< 0x00000007 */

+#define RCC_CDCCIP2R_USART234578SEL            RCC_CDCCIP2R_USART234578SEL_Msk

+#define RCC_CDCCIP2R_USART234578SEL_0          (0x1UL << RCC_CDCCIP2R_USART234578SEL_Pos)   /*!< 0x00000001 */

+#define RCC_CDCCIP2R_USART234578SEL_1          (0x2UL << RCC_CDCCIP2R_USART234578SEL_Pos)   /*!< 0x00000002 */

+#define RCC_CDCCIP2R_USART234578SEL_2          (0x4UL << RCC_CDCCIP2R_USART234578SEL_Pos)   /*!< 0x00000004 */

+

+#define RCC_CDCCIP2R_USART16910SEL_Pos         (3U)

+#define RCC_CDCCIP2R_USART16910SEL_Msk         (0x7UL << RCC_CDCCIP2R_USART16910SEL_Pos)    /*!< 0x00000038 */

+#define RCC_CDCCIP2R_USART16910SEL             RCC_CDCCIP2R_USART16910SEL_Msk

+#define RCC_CDCCIP2R_USART16910SEL_0           (0x1UL << RCC_CDCCIP2R_USART16910SEL_Pos)    /*!< 0x00000008 */

+#define RCC_CDCCIP2R_USART16910SEL_1           (0x2UL << RCC_CDCCIP2R_USART16910SEL_Pos)    /*!< 0x00000010 */

+#define RCC_CDCCIP2R_USART16910SEL_2           (0x4UL << RCC_CDCCIP2R_USART16910SEL_Pos)    /*!< 0x00000020 */

+

+#define RCC_CDCCIP2R_RNGSEL_Pos                (8U)

+#define RCC_CDCCIP2R_RNGSEL_Msk                (0x3UL << RCC_CDCCIP2R_RNGSEL_Pos)           /*!< 0x00000300 */

+#define RCC_CDCCIP2R_RNGSEL                    RCC_CDCCIP2R_RNGSEL_Msk

+#define RCC_CDCCIP2R_RNGSEL_0                  (0x1UL << RCC_CDCCIP2R_RNGSEL_Pos)           /*!< 0x00000100 */

+#define RCC_CDCCIP2R_RNGSEL_1                  (0x2UL << RCC_CDCCIP2R_RNGSEL_Pos)           /*!< 0x00000200 */

+

+#define RCC_CDCCIP2R_I2C123SEL_Pos             (12U)

+#define RCC_CDCCIP2R_I2C123SEL_Msk             (0x3UL << RCC_CDCCIP2R_I2C123SEL_Pos)        /*!< 0x00003000 */

+#define RCC_CDCCIP2R_I2C123SEL                 RCC_CDCCIP2R_I2C123SEL_Msk

+#define RCC_CDCCIP2R_I2C123SEL_0               (0x1UL << RCC_CDCCIP2R_I2C123SEL_Pos)        /*!< 0x00001000 */

+#define RCC_CDCCIP2R_I2C123SEL_1               (0x2UL << RCC_CDCCIP2R_I2C123SEL_Pos)        /*!< 0x00002000 */

+

+#define RCC_CDCCIP2R_USBSEL_Pos                (20U)

+#define RCC_CDCCIP2R_USBSEL_Msk                (0x3UL << RCC_CDCCIP2R_USBSEL_Pos)           /*!< 0x00300000 */

+#define RCC_CDCCIP2R_USBSEL                    RCC_CDCCIP2R_USBSEL_Msk

+#define RCC_CDCCIP2R_USBSEL_0                  (0x1UL << RCC_CDCCIP2R_USBSEL_Pos)           /*!< 0x00100000 */

+#define RCC_CDCCIP2R_USBSEL_1                  (0x2UL << RCC_CDCCIP2R_USBSEL_Pos)           /*!< 0x00200000 */

+

+#define RCC_CDCCIP2R_CECSEL_Pos                (22U)

+#define RCC_CDCCIP2R_CECSEL_Msk                (0x3UL << RCC_CDCCIP2R_CECSEL_Pos)           /*!< 0x00C00000 */

+#define RCC_CDCCIP2R_CECSEL                    RCC_CDCCIP2R_CECSEL_Msk

+#define RCC_CDCCIP2R_CECSEL_0                  (0x1UL << RCC_CDCCIP2R_CECSEL_Pos)           /*!< 0x00400000 */

+#define RCC_CDCCIP2R_CECSEL_1                  (0x2UL << RCC_CDCCIP2R_CECSEL_Pos)           /*!< 0x00800000 */

+

+#define RCC_CDCCIP2R_LPTIM1SEL_Pos             (28U)

+#define RCC_CDCCIP2R_LPTIM1SEL_Msk             (0x7UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)        /*!< 0x70000000 */

+#define RCC_CDCCIP2R_LPTIM1SEL                 RCC_CDCCIP2R_LPTIM1SEL_Msk

+#define RCC_CDCCIP2R_LPTIM1SEL_0               (0x1UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)        /*!< 0x10000000 */

+#define RCC_CDCCIP2R_LPTIM1SEL_1               (0x2UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)        /*!< 0x20000000 */

+#define RCC_CDCCIP2R_LPTIM1SEL_2               (0x4UL << RCC_CDCCIP2R_LPTIM1SEL_Pos)        /*!< 0x40000000 */

+

+/********************  Bit definition for RCC_SRDCCIPR register  ***************/

+#define RCC_SRDCCIPR_LPUART1SEL_Pos             (0U)

+#define RCC_SRDCCIPR_LPUART1SEL_Msk             (0x7UL << RCC_SRDCCIPR_LPUART1SEL_Pos)      /*!< 0x00000007 */

+#define RCC_SRDCCIPR_LPUART1SEL                 RCC_SRDCCIPR_LPUART1SEL_Msk

+#define RCC_SRDCCIPR_LPUART1SEL_0               (0x1UL << RCC_SRDCCIPR_LPUART1SEL_Pos)      /*!< 0x00000001 */

+#define RCC_SRDCCIPR_LPUART1SEL_1               (0x2UL << RCC_SRDCCIPR_LPUART1SEL_Pos)      /*!< 0x00000002 */

+#define RCC_SRDCCIPR_LPUART1SEL_2               (0x4UL << RCC_SRDCCIPR_LPUART1SEL_Pos)      /*!< 0x00000004 */

+

+#define RCC_SRDCCIPR_I2C4SEL_Pos                (8U)

+#define RCC_SRDCCIPR_I2C4SEL_Msk                (0x3UL << RCC_SRDCCIPR_I2C4SEL_Pos)         /*!< 0x00000300 */

+#define RCC_SRDCCIPR_I2C4SEL                    RCC_SRDCCIPR_I2C4SEL_Msk

+#define RCC_SRDCCIPR_I2C4SEL_0                  (0x1UL << RCC_SRDCCIPR_I2C4SEL_Pos)         /*!< 0x00000100 */

+#define RCC_SRDCCIPR_I2C4SEL_1                  (0x2UL << RCC_SRDCCIPR_I2C4SEL_Pos)         /*!< 0x00000200 */

+

+#define RCC_SRDCCIPR_LPTIM2SEL_Pos              (10U)

+#define RCC_SRDCCIPR_LPTIM2SEL_Msk              (0x7UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)       /*!< 0x00001C00 */

+#define RCC_SRDCCIPR_LPTIM2SEL                  RCC_SRDCCIPR_LPTIM2SEL_Msk

+#define RCC_SRDCCIPR_LPTIM2SEL_0                (0x1UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)       /*!< 0x00000400 */

+#define RCC_SRDCCIPR_LPTIM2SEL_1                (0x2UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)       /*!< 0x00000800 */

+#define RCC_SRDCCIPR_LPTIM2SEL_2                (0x4UL << RCC_SRDCCIPR_LPTIM2SEL_Pos)       /*!< 0x00001000 */

+

+#define RCC_SRDCCIPR_LPTIM3SEL_Pos            (13U)

+#define RCC_SRDCCIPR_LPTIM3SEL_Msk            (0x7UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)         /*!< 0x0000E000 */

+#define RCC_SRDCCIPR_LPTIM3SEL                RCC_SRDCCIPR_LPTIM3SEL_Msk

+#define RCC_SRDCCIPR_LPTIM3SEL_0              (0x1UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)         /*!< 0x00002000 */

+#define RCC_SRDCCIPR_LPTIM3SEL_1              (0x2UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)         /*!< 0x00004000 */

+#define RCC_SRDCCIPR_LPTIM3SEL_2              (0x4UL << RCC_SRDCCIPR_LPTIM3SEL_Pos)         /*!< 0x00008000 */

+

+#define RCC_SRDCCIPR_ADCSEL_Pos                 (16U)

+#define RCC_SRDCCIPR_ADCSEL_Msk                 (0x3UL << RCC_SRDCCIPR_ADCSEL_Pos)          /*!< 0x00030000 */

+#define RCC_SRDCCIPR_ADCSEL                     RCC_SRDCCIPR_ADCSEL_Msk

+#define RCC_SRDCCIPR_ADCSEL_0                   (0x1UL << RCC_SRDCCIPR_ADCSEL_Pos)          /*!< 0x00010000 */

+#define RCC_SRDCCIPR_ADCSEL_1                   (0x2UL << RCC_SRDCCIPR_ADCSEL_Pos)          /*!< 0x00020000 */

+

+#define RCC_SRDCCIPR_DFSDM2SEL_Pos              (27U)

+#define RCC_SRDCCIPR_DFSDM2SEL_Msk              (0x1UL << RCC_SRDCCIPR_DFSDM2SEL_Pos)       /*!< 0x08000000 */

+#define RCC_SRDCCIPR_DFSDM2SEL                   RCC_SRDCCIPR_DFSDM2SEL_Msk

+

+#define RCC_SRDCCIPR_SPI6SEL_Pos                (28U)

+#define RCC_SRDCCIPR_SPI6SEL_Msk                (0x7UL << RCC_SRDCCIPR_SPI6SEL_Pos)         /*!< 0x70000000 */

+#define RCC_SRDCCIPR_SPI6SEL                    RCC_SRDCCIPR_SPI6SEL_Msk

+#define RCC_SRDCCIPR_SPI6SEL_0                  (0x1UL << RCC_SRDCCIPR_SPI6SEL_Pos)         /*!< 0x10000000 */

+#define RCC_SRDCCIPR_SPI6SEL_1                  (0x2UL << RCC_SRDCCIPR_SPI6SEL_Pos)         /*!< 0x20000000 */

+#define RCC_SRDCCIPR_SPI6SEL_2                  (0x4UL << RCC_SRDCCIPR_SPI6SEL_Pos)         /*!< 0x40000000 */

+

+/********************  Bit definition for RCC_CIER register  ******************/

+#define RCC_CIER_LSIRDYIE_Pos                  (0U)

+#define RCC_CIER_LSIRDYIE_Msk                  (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */

+#define RCC_CIER_LSIRDYIE                      RCC_CIER_LSIRDYIE_Msk

+#define RCC_CIER_LSERDYIE_Pos                  (1U)

+#define RCC_CIER_LSERDYIE_Msk                  (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */

+#define RCC_CIER_LSERDYIE                      RCC_CIER_LSERDYIE_Msk

+#define RCC_CIER_HSIRDYIE_Pos                  (2U)

+#define RCC_CIER_HSIRDYIE_Msk                  (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */

+#define RCC_CIER_HSIRDYIE                      RCC_CIER_HSIRDYIE_Msk

+#define RCC_CIER_HSERDYIE_Pos                  (3U)

+#define RCC_CIER_HSERDYIE_Msk                  (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */

+#define RCC_CIER_HSERDYIE                      RCC_CIER_HSERDYIE_Msk

+#define RCC_CIER_CSIRDYIE_Pos                  (4U)

+#define RCC_CIER_CSIRDYIE_Msk                  (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */

+#define RCC_CIER_CSIRDYIE                      RCC_CIER_CSIRDYIE_Msk

+#define RCC_CIER_HSI48RDYIE_Pos                (5U)

+#define RCC_CIER_HSI48RDYIE_Msk                (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */

+#define RCC_CIER_HSI48RDYIE                    RCC_CIER_HSI48RDYIE_Msk

+#define RCC_CIER_PLL1RDYIE_Pos                 (6U)

+#define RCC_CIER_PLL1RDYIE_Msk                 (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */

+#define RCC_CIER_PLL1RDYIE                     RCC_CIER_PLL1RDYIE_Msk

+#define RCC_CIER_PLL2RDYIE_Pos                 (7U)

+#define RCC_CIER_PLL2RDYIE_Msk                 (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */

+#define RCC_CIER_PLL2RDYIE                     RCC_CIER_PLL2RDYIE_Msk

+#define RCC_CIER_PLL3RDYIE_Pos                 (8U)

+#define RCC_CIER_PLL3RDYIE_Msk                 (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */

+#define RCC_CIER_PLL3RDYIE                     RCC_CIER_PLL3RDYIE_Msk

+#define RCC_CIER_LSECSSIE_Pos                  (9U)

+#define RCC_CIER_LSECSSIE_Msk                  (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */

+#define RCC_CIER_LSECSSIE                      RCC_CIER_LSECSSIE_Msk

+

+/********************  Bit definition for RCC_CIFR register  ******************/

+#define RCC_CIFR_LSIRDYF_Pos                   (0U)

+#define RCC_CIFR_LSIRDYF_Msk                   (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */

+#define RCC_CIFR_LSIRDYF                       RCC_CIFR_LSIRDYF_Msk

+#define RCC_CIFR_LSERDYF_Pos                   (1U)

+#define RCC_CIFR_LSERDYF_Msk                   (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */

+#define RCC_CIFR_LSERDYF                       RCC_CIFR_LSERDYF_Msk

+#define RCC_CIFR_HSIRDYF_Pos                   (2U)

+#define RCC_CIFR_HSIRDYF_Msk                   (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */

+#define RCC_CIFR_HSIRDYF                       RCC_CIFR_HSIRDYF_Msk

+#define RCC_CIFR_HSERDYF_Pos                   (3U)

+#define RCC_CIFR_HSERDYF_Msk                   (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */

+#define RCC_CIFR_HSERDYF                       RCC_CIFR_HSERDYF_Msk

+#define RCC_CIFR_CSIRDYF_Pos                   (4U)

+#define RCC_CIFR_CSIRDYF_Msk                   (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */

+#define RCC_CIFR_CSIRDYF                       RCC_CIFR_CSIRDYF_Msk

+#define RCC_CIFR_HSI48RDYF_Pos                 (5U)

+#define RCC_CIFR_HSI48RDYF_Msk                 (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */

+#define RCC_CIFR_HSI48RDYF                     RCC_CIFR_HSI48RDYF_Msk

+#define RCC_CIFR_PLLRDYF_Pos                   (6U)

+#define RCC_CIFR_PLLRDYF_Msk                   (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */

+#define RCC_CIFR_PLLRDYF                       RCC_CIFR_PLLRDYF_Msk

+#define RCC_CIFR_PLL2RDYF_Pos                  (7U)

+#define RCC_CIFR_PLL2RDYF_Msk                  (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */

+#define RCC_CIFR_PLL2RDYF                      RCC_CIFR_PLL2RDYF_Msk

+#define RCC_CIFR_PLL3RDYF_Pos                  (8U)

+#define RCC_CIFR_PLL3RDYF_Msk                  (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */

+#define RCC_CIFR_PLL3RDYF                      RCC_CIFR_PLL3RDYF_Msk

+#define RCC_CIFR_LSECSSF_Pos                   (9U)

+#define RCC_CIFR_LSECSSF_Msk                   (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */

+#define RCC_CIFR_LSECSSF                       RCC_CIFR_LSECSSF_Msk

+#define RCC_CIFR_HSECSSF_Pos                   (10U)

+#define RCC_CIFR_HSECSSF_Msk                   (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */

+#define RCC_CIFR_HSECSSF                       RCC_CIFR_HSECSSF_Msk

+

+/********************  Bit definition for RCC_CICR register  ******************/

+#define RCC_CICR_LSIRDYC_Pos                   (0U)

+#define RCC_CICR_LSIRDYC_Msk                   (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */

+#define RCC_CICR_LSIRDYC                       RCC_CICR_LSIRDYC_Msk

+#define RCC_CICR_LSERDYC_Pos                   (1U)

+#define RCC_CICR_LSERDYC_Msk                   (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */

+#define RCC_CICR_LSERDYC                       RCC_CICR_LSERDYC_Msk

+#define RCC_CICR_HSIRDYC_Pos                   (2U)

+#define RCC_CICR_HSIRDYC_Msk                   (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */

+#define RCC_CICR_HSIRDYC                       RCC_CICR_HSIRDYC_Msk

+#define RCC_CICR_HSERDYC_Pos                   (3U)

+#define RCC_CICR_HSERDYC_Msk                   (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */

+#define RCC_CICR_HSERDYC                       RCC_CICR_HSERDYC_Msk

+#define RCC_CICR_CSIRDYC_Pos                   (4U)

+#define RCC_CICR_CSIRDYC_Msk                   (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */

+#define RCC_CICR_CSIRDYC                       RCC_CICR_CSIRDYC_Msk

+#define RCC_CICR_HSI48RDYC_Pos                 (5U)

+#define RCC_CICR_HSI48RDYC_Msk                 (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */

+#define RCC_CICR_HSI48RDYC                     RCC_CICR_HSI48RDYC_Msk

+#define RCC_CICR_PLLRDYC_Pos                   (6U)

+#define RCC_CICR_PLLRDYC_Msk                   (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */

+#define RCC_CICR_PLLRDYC                       RCC_CICR_PLLRDYC_Msk

+#define RCC_CICR_PLL2RDYC_Pos                  (7U)

+#define RCC_CICR_PLL2RDYC_Msk                  (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */

+#define RCC_CICR_PLL2RDYC                      RCC_CICR_PLL2RDYC_Msk

+#define RCC_CICR_PLL3RDYC_Pos                  (8U)

+#define RCC_CICR_PLL3RDYC_Msk                  (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */

+#define RCC_CICR_PLL3RDYC                      RCC_CICR_PLL3RDYC_Msk

+#define RCC_CICR_LSECSSC_Pos                   (9U)

+#define RCC_CICR_LSECSSC_Msk                   (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */

+#define RCC_CICR_LSECSSC                       RCC_CICR_LSECSSC_Msk

+#define RCC_CICR_HSECSSC_Pos                   (10U)

+#define RCC_CICR_HSECSSC_Msk                   (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */

+#define RCC_CICR_HSECSSC                       RCC_CICR_HSECSSC_Msk

+

+/********************  Bit definition for RCC_BDCR register  ******************/

+#define RCC_BDCR_LSEON_Pos                     (0U)

+#define RCC_BDCR_LSEON_Msk                     (0x1UL << RCC_BDCR_LSEON_Pos)   /*!< 0x00000001 */

+#define RCC_BDCR_LSEON                         RCC_BDCR_LSEON_Msk

+#define RCC_BDCR_LSERDY_Pos                    (1U)

+#define RCC_BDCR_LSERDY_Msk                    (0x1UL << RCC_BDCR_LSERDY_Pos)  /*!< 0x00000002 */

+#define RCC_BDCR_LSERDY                        RCC_BDCR_LSERDY_Msk

+#define RCC_BDCR_LSEBYP_Pos                    (2U)

+#define RCC_BDCR_LSEBYP_Msk                    (0x1UL << RCC_BDCR_LSEBYP_Pos)  /*!< 0x00000004 */

+#define RCC_BDCR_LSEBYP                        RCC_BDCR_LSEBYP_Msk

+

+#define RCC_BDCR_LSEDRV_Pos                    (3U)

+#define RCC_BDCR_LSEDRV_Msk                    (0x3UL << RCC_BDCR_LSEDRV_Pos)  /*!< 0x00000018 */

+#define RCC_BDCR_LSEDRV                        RCC_BDCR_LSEDRV_Msk

+#define RCC_BDCR_LSEDRV_0                      (0x1UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000008 */

+#define RCC_BDCR_LSEDRV_1                      (0x2UL << RCC_BDCR_LSEDRV_Pos)   /*!< 0x00000010 */

+

+#define RCC_BDCR_LSECSSON_Pos                  (5U)

+#define RCC_BDCR_LSECSSON_Msk                  (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */

+#define RCC_BDCR_LSECSSON                      RCC_BDCR_LSECSSON_Msk

+#define RCC_BDCR_LSECSSD_Pos                   (6U)

+#define RCC_BDCR_LSECSSD_Msk                   (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */

+#define RCC_BDCR_LSECSSD                       RCC_BDCR_LSECSSD_Msk

+#define RCC_BDCR_LSEEXT_Pos                    (7U)

+#define RCC_BDCR_LSEEXT_Msk                    (0x1UL << RCC_BDCR_LSEEXT_Pos)  /*!< 0x00000080 */

+#define RCC_BDCR_LSEEXT                        RCC_BDCR_LSEEXT_Msk

+

+#define RCC_BDCR_RTCSEL_Pos                    (8U)

+#define RCC_BDCR_RTCSEL_Msk                    (0x3UL << RCC_BDCR_RTCSEL_Pos)  /*!< 0x00000300 */

+#define RCC_BDCR_RTCSEL                        RCC_BDCR_RTCSEL_Msk

+#define RCC_BDCR_RTCSEL_0                      (0x1UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000100 */

+#define RCC_BDCR_RTCSEL_1                      (0x2UL << RCC_BDCR_RTCSEL_Pos)   /*!< 0x00000200 */

+

+#define RCC_BDCR_RTCEN_Pos                     (15U)

+#define RCC_BDCR_RTCEN_Msk                     (0x1UL << RCC_BDCR_RTCEN_Pos)   /*!< 0x00008000 */

+#define RCC_BDCR_RTCEN                         RCC_BDCR_RTCEN_Msk

+#define RCC_BDCR_VSWRST_Pos                    (16U)

+#define RCC_BDCR_VSWRST_Msk                    (0x1UL << RCC_BDCR_VSWRST_Pos)   /*!< 0x00010000 */

+#define RCC_BDCR_VSWRST                        RCC_BDCR_VSWRST_Msk

+/* Legacy define */

+#define RCC_BDCR_BDRST_Pos                     RCC_BDCR_VSWRST_Pos

+#define RCC_BDCR_BDRST_Msk                     RCC_BDCR_VSWRST_Msk

+#define RCC_BDCR_BDRST                         RCC_BDCR_VSWRST

+/********************  Bit definition for RCC_CSR register  *******************/

+#define RCC_CSR_LSION_Pos                      (0U)

+#define RCC_CSR_LSION_Msk                      (0x1UL << RCC_CSR_LSION_Pos)    /*!< 0x00000001 */

+#define RCC_CSR_LSION                          RCC_CSR_LSION_Msk

+#define RCC_CSR_LSIRDY_Pos                     (1U)

+#define RCC_CSR_LSIRDY_Msk                     (0x1UL << RCC_CSR_LSIRDY_Pos)   /*!< 0x00000002 */

+#define RCC_CSR_LSIRDY                         RCC_CSR_LSIRDY_Msk

+

+

+/********************  Bit definition for RCC_AHB3ENR register  **************/

+#define RCC_AHB3ENR_MDMAEN_Pos                 (0U)

+#define RCC_AHB3ENR_MDMAEN_Msk                 (0x1UL << RCC_AHB3ENR_MDMAEN_Pos)       /*!< 0x00000001 */

+#define RCC_AHB3ENR_MDMAEN                     RCC_AHB3ENR_MDMAEN_Msk

+#define RCC_AHB3ENR_DMA2DEN_Pos                (4U)

+#define RCC_AHB3ENR_DMA2DEN_Msk                (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos)      /*!< 0x00000010 */

+#define RCC_AHB3ENR_DMA2DEN                    RCC_AHB3ENR_DMA2DEN_Msk

+#define RCC_AHB3ENR_JPGDECEN_Pos               (5U)

+#define RCC_AHB3ENR_JPGDECEN_Msk               (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos)     /*!< 0x00000020 */

+#define RCC_AHB3ENR_JPGDECEN                   RCC_AHB3ENR_JPGDECEN_Msk

+#define RCC_AHB3ENR_FMCEN_Pos                  (12U)

+#define RCC_AHB3ENR_FMCEN_Msk                  (0x1UL << RCC_AHB3ENR_FMCEN_Pos)        /*!< 0x00001000 */

+#define RCC_AHB3ENR_FMCEN                      RCC_AHB3ENR_FMCEN_Msk

+#define RCC_AHB3ENR_OSPI1EN_Pos                (14U)

+#define RCC_AHB3ENR_OSPI1EN_Msk                (0x1UL << RCC_AHB3ENR_OSPI1EN_Pos)      /*!< 0x00004000 */

+#define RCC_AHB3ENR_OSPI1EN                    RCC_AHB3ENR_OSPI1EN_Msk

+#define RCC_AHB3ENR_SDMMC1EN_Pos               (16U)

+#define RCC_AHB3ENR_SDMMC1EN_Msk               (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos)     /*!< 0x00010000 */

+#define RCC_AHB3ENR_SDMMC1EN                   RCC_AHB3ENR_SDMMC1EN_Msk

+#define RCC_AHB3ENR_OSPI2EN_Pos                (19U)

+#define RCC_AHB3ENR_OSPI2EN_Msk                (0x1UL << RCC_AHB3ENR_OSPI2EN_Pos)      /*!< 0x00040000 */

+#define RCC_AHB3ENR_OSPI2EN                    RCC_AHB3ENR_OSPI2EN_Msk

+#define RCC_AHB3ENR_IOMNGREN_Pos               (21U)

+#define RCC_AHB3ENR_IOMNGREN_Msk               (0x1UL << RCC_AHB3ENR_IOMNGREN_Pos)     /*!< 0x00100000 */

+#define RCC_AHB3ENR_IOMNGREN                   RCC_AHB3ENR_IOMNGREN_Msk

+#define RCC_AHB3ENR_OTFDEC1EN_Pos              (22U)

+#define RCC_AHB3ENR_OTFDEC1EN_Msk              (0x1UL << RCC_AHB3ENR_OTFDEC1EN_Pos)    /*!< 0x00200000 */

+#define RCC_AHB3ENR_OTFDEC1EN                  RCC_AHB3ENR_OTFDEC1EN_Msk

+#define RCC_AHB3ENR_OTFDEC2EN_Pos              (23U)

+#define RCC_AHB3ENR_OTFDEC2EN_Msk              (0x1UL << RCC_AHB3ENR_OTFDEC2EN_Pos)    /*!< 0x00400000 */

+#define RCC_AHB3ENR_OTFDEC2EN                  RCC_AHB3ENR_OTFDEC2EN_Msk

+#define RCC_AHB3ENR_GFXMMUEN_Pos               (24U)

+#define RCC_AHB3ENR_GFXMMUEN_Msk               (0x1UL << RCC_AHB3ENR_GFXMMUEN_Pos)     /*!< 0x00800000 */

+#define RCC_AHB3ENR_GFXMMUEN                   RCC_AHB3ENR_GFXMMUEN_Msk

+

+/********************  Bit definition for RCC_AHB1ENR register  ***************/

+#define RCC_AHB1ENR_DMA1EN_Pos                 (0U)

+#define RCC_AHB1ENR_DMA1EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA1EN_Pos)          /*!< 0x00000001 */

+#define RCC_AHB1ENR_DMA1EN                     RCC_AHB1ENR_DMA1EN_Msk

+#define RCC_AHB1ENR_DMA2EN_Pos                 (1U)

+#define RCC_AHB1ENR_DMA2EN_Msk                 (0x1UL << RCC_AHB1ENR_DMA2EN_Pos)          /*!< 0x00000002 */

+#define RCC_AHB1ENR_DMA2EN                     RCC_AHB1ENR_DMA2EN_Msk

+#define RCC_AHB1ENR_ADC12EN_Pos                (5U)

+#define RCC_AHB1ENR_ADC12EN_Msk                (0x1UL << RCC_AHB1ENR_ADC12EN_Pos)         /*!< 0x00000020 */

+#define RCC_AHB1ENR_ADC12EN                    RCC_AHB1ENR_ADC12EN_Msk

+#define RCC_AHB1ENR_CRCEN_Pos                  (9U)

+#define RCC_AHB1ENR_CRCEN_Msk                  (0x1UL << RCC_AHB1ENR_CRCEN_Pos)           /*!< 0x00000200 */

+#define RCC_AHB1ENR_CRCEN                      RCC_AHB1ENR_CRCEN_Msk

+#define RCC_AHB1ENR_USB1OTGHSEN_Pos            (25U)

+#define RCC_AHB1ENR_USB1OTGHSEN_Msk            (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos)     /*!< 0x02000000 */

+#define RCC_AHB1ENR_USB1OTGHSEN                RCC_AHB1ENR_USB1OTGHSEN_Msk

+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos        (26U)

+#define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk        (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */

+#define RCC_AHB1ENR_USB1OTGHSULPIEN            RCC_AHB1ENR_USB1OTGHSULPIEN_Msk

+

+/********************  Bit definition for RCC_AHB2ENR register  ***************/

+#define RCC_AHB2ENR_DCMI_PSSIEN_Pos            (0U)

+#define RCC_AHB2ENR_DCMI_PSSIEN_Msk            (0x1UL << RCC_AHB2ENR_DCMI_PSSIEN_Pos)     /*!< 0x00000001 */

+#define RCC_AHB2ENR_DCMI_PSSIEN                RCC_AHB2ENR_DCMI_PSSIEN_Msk

+#define RCC_AHB2ENR_HSEMEN_Pos                 (2U)

+#define RCC_AHB2ENR_HSEMEN_Msk                 (0x1UL << RCC_AHB2ENR_HSEMEN_Pos)          /*!< 0x00000004 */

+#define RCC_AHB2ENR_HSEMEN                     RCC_AHB2ENR_HSEMEN_Msk

+#define RCC_AHB2ENR_CRYPEN_Pos                 (4U)

+#define RCC_AHB2ENR_CRYPEN_Msk                 (0x1UL << RCC_AHB2ENR_CRYPEN_Pos)          /*!< 0x00000010 */

+#define RCC_AHB2ENR_CRYPEN                     RCC_AHB2ENR_CRYPEN_Msk

+#define RCC_AHB2ENR_HASHEN_Pos                 (5U)

+#define RCC_AHB2ENR_HASHEN_Msk                 (0x1UL << RCC_AHB2ENR_HASHEN_Pos)          /*!< 0x00000020 */

+#define RCC_AHB2ENR_HASHEN                     RCC_AHB2ENR_HASHEN_Msk

+#define RCC_AHB2ENR_RNGEN_Pos                  (6U)

+#define RCC_AHB2ENR_RNGEN_Msk                  (0x1UL << RCC_AHB2ENR_RNGEN_Pos)           /*!< 0x00000040 */

+#define RCC_AHB2ENR_RNGEN                      RCC_AHB2ENR_RNGEN_Msk

+#define RCC_AHB2ENR_SDMMC2EN_Pos               (9U)

+#define RCC_AHB2ENR_SDMMC2EN_Msk               (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos)        /*!< 0x00000200 */

+#define RCC_AHB2ENR_SDMMC2EN                   RCC_AHB2ENR_SDMMC2EN_Msk

+#define RCC_AHB2ENR_BDMA1EN_Pos                (11U)

+#define RCC_AHB2ENR_BDMA1EN_Msk                (0x1UL << RCC_AHB2ENR_BDMA1EN_Pos)         /*!< 0x00000800 */

+#define RCC_AHB2ENR_BDMA1EN                    RCC_AHB2ENR_BDMA1EN_Msk

+#define RCC_AHB2ENR_AHBSRAM1EN_Pos             (29U)

+#define RCC_AHB2ENR_AHBSRAM1EN_Msk             (0x1UL << RCC_AHB2ENR_AHBSRAM1EN_Pos)       /*!< 0x20000000 */

+#define RCC_AHB2ENR_AHBSRAM1EN                 RCC_AHB2ENR_AHBSRAM1EN_Msk

+#define RCC_AHB2ENR_AHBSRAM2EN_Pos             (30U)

+#define RCC_AHB2ENR_AHBSRAM2EN_Msk             (0x1UL << RCC_AHB2ENR_AHBSRAM2EN_Pos)       /*!< 0x40000000 */

+#define RCC_AHB2ENR_AHBSRAM2EN                 RCC_AHB2ENR_AHBSRAM2EN_Msk

+

+/* Legacy define */

+#define RCC_AHB2ENR_DCMIEN_Pos                 RCC_AHB2ENR_DCMI_PSSIEN_Pos

+#define RCC_AHB2ENR_DCMIEN_Msk                 RCC_AHB2ENR_DCMI_PSSIEN_Msk

+#define RCC_AHB2ENR_DCMIEN                     RCC_AHB2ENR_DCMI_PSSIEN

+

+/********************  Bit definition for RCC_AHB4ENR register  ******************/

+#define RCC_AHB4ENR_GPIOAEN_Pos                (0U)

+#define RCC_AHB4ENR_GPIOAEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos)         /*!< 0x00000001 */

+#define RCC_AHB4ENR_GPIOAEN                    RCC_AHB4ENR_GPIOAEN_Msk

+#define RCC_AHB4ENR_GPIOBEN_Pos                (1U)

+#define RCC_AHB4ENR_GPIOBEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos)         /*!< 0x00000002 */

+#define RCC_AHB4ENR_GPIOBEN                    RCC_AHB4ENR_GPIOBEN_Msk

+#define RCC_AHB4ENR_GPIOCEN_Pos                (2U)

+#define RCC_AHB4ENR_GPIOCEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos)         /*!< 0x00000004 */

+#define RCC_AHB4ENR_GPIOCEN                    RCC_AHB4ENR_GPIOCEN_Msk

+#define RCC_AHB4ENR_GPIODEN_Pos                (3U)

+#define RCC_AHB4ENR_GPIODEN_Msk                (0x1UL << RCC_AHB4ENR_GPIODEN_Pos)         /*!< 0x00000008 */

+#define RCC_AHB4ENR_GPIODEN                    RCC_AHB4ENR_GPIODEN_Msk

+#define RCC_AHB4ENR_GPIOEEN_Pos                (4U)

+#define RCC_AHB4ENR_GPIOEEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos)         /*!< 0x00000010 */

+#define RCC_AHB4ENR_GPIOEEN                    RCC_AHB4ENR_GPIOEEN_Msk

+#define RCC_AHB4ENR_GPIOFEN_Pos                (5U)

+#define RCC_AHB4ENR_GPIOFEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos)         /*!< 0x00000020 */

+#define RCC_AHB4ENR_GPIOFEN                    RCC_AHB4ENR_GPIOFEN_Msk

+#define RCC_AHB4ENR_GPIOGEN_Pos                (6U)

+#define RCC_AHB4ENR_GPIOGEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos)         /*!< 0x00000040 */

+#define RCC_AHB4ENR_GPIOGEN                    RCC_AHB4ENR_GPIOGEN_Msk

+#define RCC_AHB4ENR_GPIOHEN_Pos                (7U)

+#define RCC_AHB4ENR_GPIOHEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos)         /*!< 0x00000080 */

+#define RCC_AHB4ENR_GPIOHEN                    RCC_AHB4ENR_GPIOHEN_Msk

+#define RCC_AHB4ENR_GPIOIEN_Pos                (8U)

+#define RCC_AHB4ENR_GPIOIEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos)         /*!< 0x00000100 */

+#define RCC_AHB4ENR_GPIOIEN                    RCC_AHB4ENR_GPIOIEN_Msk

+#define RCC_AHB4ENR_GPIOJEN_Pos                (9U)

+#define RCC_AHB4ENR_GPIOJEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos)         /*!< 0x00000200 */

+#define RCC_AHB4ENR_GPIOJEN                    RCC_AHB4ENR_GPIOJEN_Msk

+#define RCC_AHB4ENR_GPIOKEN_Pos                (10U)

+#define RCC_AHB4ENR_GPIOKEN_Msk                (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos)         /*!< 0x00000400 */

+#define RCC_AHB4ENR_GPIOKEN                    RCC_AHB4ENR_GPIOKEN_Msk

+#define RCC_AHB4ENR_BDMA2EN_Pos                (21U)

+#define RCC_AHB4ENR_BDMA2EN_Msk                (0x1UL << RCC_AHB4ENR_BDMA2EN_Pos)         /*!< 0x00080000 */

+#define RCC_AHB4ENR_BDMA2EN                    RCC_AHB4ENR_BDMA2EN_Msk

+#define RCC_AHB4ENR_BKPRAMEN_Pos               (28U)

+#define RCC_AHB4ENR_BKPRAMEN_Msk               (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos)        /*!< 0x10000000 */

+#define RCC_AHB4ENR_BKPRAMEN                   RCC_AHB4ENR_BKPRAMEN_Msk

+#define RCC_AHB4ENR_SRDSRAMEN_Pos              (29U)

+#define RCC_AHB4ENR_SRDSRAMEN_Msk              (0x1UL << RCC_AHB4ENR_SRDSRAMEN_Pos)       /*!< 0x20000000 */

+#define RCC_AHB4ENR_SRDSRAMEN                  RCC_AHB4ENR_SRDSRAMEN_Msk

+

+/********************  Bit definition for RCC_APB3ENR register  ******************/

+#define RCC_APB3ENR_LTDCEN_Pos                 (3U)

+#define RCC_APB3ENR_LTDCEN_Msk                 (0x1UL << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */

+#define RCC_APB3ENR_LTDCEN                     RCC_APB3ENR_LTDCEN_Msk

+#define RCC_APB3ENR_WWDGEN_Pos                 (6U)

+#define RCC_APB3ENR_WWDGEN_Msk                 (0x1UL << RCC_APB3ENR_WWDGEN_Pos) /*!< 0x00000040 */

+#define RCC_APB3ENR_WWDGEN                     RCC_APB3ENR_WWDGEN_Msk

+

+/* Legacy define */

+#define RCC_APB3ENR_WWDG1EN_Pos                 RCC_APB3ENR_WWDGEN_Pos

+#define RCC_APB3ENR_WWDG1EN_Msk                 RCC_APB3ENR_WWDGEN_Msk

+#define RCC_APB3ENR_WWDG1EN                     RCC_APB3ENR_WWDGEN

+/********************  Bit definition for RCC_APB1LENR register  ******************/

+

+#define RCC_APB1LENR_TIM2EN_Pos                (0U)

+#define RCC_APB1LENR_TIM2EN_Msk                (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */

+#define RCC_APB1LENR_TIM2EN                    RCC_APB1LENR_TIM2EN_Msk

+#define RCC_APB1LENR_TIM3EN_Pos                (1U)

+#define RCC_APB1LENR_TIM3EN_Msk                (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */

+#define RCC_APB1LENR_TIM3EN                    RCC_APB1LENR_TIM3EN_Msk

+#define RCC_APB1LENR_TIM4EN_Pos                (2U)

+#define RCC_APB1LENR_TIM4EN_Msk                (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */

+#define RCC_APB1LENR_TIM4EN                    RCC_APB1LENR_TIM4EN_Msk

+#define RCC_APB1LENR_TIM5EN_Pos                (3U)

+#define RCC_APB1LENR_TIM5EN_Msk                (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */

+#define RCC_APB1LENR_TIM5EN                    RCC_APB1LENR_TIM5EN_Msk

+#define RCC_APB1LENR_TIM6EN_Pos                (4U)

+#define RCC_APB1LENR_TIM6EN_Msk                (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */

+#define RCC_APB1LENR_TIM6EN                    RCC_APB1LENR_TIM6EN_Msk

+#define RCC_APB1LENR_TIM7EN_Pos                (5U)

+#define RCC_APB1LENR_TIM7EN_Msk                (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */

+#define RCC_APB1LENR_TIM7EN                    RCC_APB1LENR_TIM7EN_Msk

+#define RCC_APB1LENR_TIM12EN_Pos               (6U)

+#define RCC_APB1LENR_TIM12EN_Msk               (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */

+#define RCC_APB1LENR_TIM12EN                   RCC_APB1LENR_TIM12EN_Msk

+#define RCC_APB1LENR_TIM13EN_Pos               (7U)

+#define RCC_APB1LENR_TIM13EN_Msk               (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */

+#define RCC_APB1LENR_TIM13EN                   RCC_APB1LENR_TIM13EN_Msk

+#define RCC_APB1LENR_TIM14EN_Pos               (8U)

+#define RCC_APB1LENR_TIM14EN_Msk               (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */

+#define RCC_APB1LENR_TIM14EN                   RCC_APB1LENR_TIM14EN_Msk

+#define RCC_APB1LENR_LPTIM1EN_Pos              (9U)

+#define RCC_APB1LENR_LPTIM1EN_Msk              (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */

+#define RCC_APB1LENR_LPTIM1EN                  RCC_APB1LENR_LPTIM1EN_Msk

+

+

+#define RCC_APB1LENR_SPI2EN_Pos                (14U)

+#define RCC_APB1LENR_SPI2EN_Msk                (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */

+#define RCC_APB1LENR_SPI2EN                    RCC_APB1LENR_SPI2EN_Msk

+#define RCC_APB1LENR_SPI3EN_Pos                (15U)

+#define RCC_APB1LENR_SPI3EN_Msk                (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */

+#define RCC_APB1LENR_SPI3EN                    RCC_APB1LENR_SPI3EN_Msk

+#define RCC_APB1LENR_SPDIFRXEN_Pos             (16U)

+#define RCC_APB1LENR_SPDIFRXEN_Msk             (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */

+#define RCC_APB1LENR_SPDIFRXEN                 RCC_APB1LENR_SPDIFRXEN_Msk

+#define RCC_APB1LENR_USART2EN_Pos              (17U)

+#define RCC_APB1LENR_USART2EN_Msk              (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */

+#define RCC_APB1LENR_USART2EN                  RCC_APB1LENR_USART2EN_Msk

+#define RCC_APB1LENR_USART3EN_Pos              (18U)

+#define RCC_APB1LENR_USART3EN_Msk              (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */

+#define RCC_APB1LENR_USART3EN                  RCC_APB1LENR_USART3EN_Msk

+#define RCC_APB1LENR_UART4EN_Pos               (19U)

+#define RCC_APB1LENR_UART4EN_Msk               (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */

+#define RCC_APB1LENR_UART4EN                   RCC_APB1LENR_UART4EN_Msk

+#define RCC_APB1LENR_UART5EN_Pos               (20U)

+#define RCC_APB1LENR_UART5EN_Msk               (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */

+#define RCC_APB1LENR_UART5EN                   RCC_APB1LENR_UART5EN_Msk

+#define RCC_APB1LENR_I2C1EN_Pos                (21U)

+#define RCC_APB1LENR_I2C1EN_Msk                (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */

+#define RCC_APB1LENR_I2C1EN                    RCC_APB1LENR_I2C1EN_Msk

+#define RCC_APB1LENR_I2C2EN_Pos                (22U)

+#define RCC_APB1LENR_I2C2EN_Msk                (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */

+#define RCC_APB1LENR_I2C2EN                    RCC_APB1LENR_I2C2EN_Msk

+#define RCC_APB1LENR_I2C3EN_Pos                (23U)

+#define RCC_APB1LENR_I2C3EN_Msk                (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */

+#define RCC_APB1LENR_I2C3EN                    RCC_APB1LENR_I2C3EN_Msk

+#define RCC_APB1LENR_CECEN_Pos                 (27U)

+#define RCC_APB1LENR_CECEN_Msk                 (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */

+#define RCC_APB1LENR_CECEN                     RCC_APB1LENR_CECEN_Msk

+#define RCC_APB1LENR_DAC12EN_Pos               (29U)

+#define RCC_APB1LENR_DAC12EN_Msk               (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */

+#define RCC_APB1LENR_DAC12EN                   RCC_APB1LENR_DAC12EN_Msk

+#define RCC_APB1LENR_UART7EN_Pos               (30U)

+#define RCC_APB1LENR_UART7EN_Msk               (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */

+#define RCC_APB1LENR_UART7EN                   RCC_APB1LENR_UART7EN_Msk

+#define RCC_APB1LENR_UART8EN_Pos               (31U)

+#define RCC_APB1LENR_UART8EN_Msk               (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */

+#define RCC_APB1LENR_UART8EN                   RCC_APB1LENR_UART8EN_Msk

+

+/* Legacy define */

+#define RCC_APB1LENR_HDMICECEN_Pos             RCC_APB1LENR_CECEN_Pos

+#define RCC_APB1LENR_HDMICECEN_Msk             RCC_APB1LENR_CECEN_Msk

+#define RCC_APB1LENR_HDMICECEN                 RCC_APB1LENR_CECEN

+/********************  Bit definition for RCC_APB1HENR register  ******************/

+#define RCC_APB1HENR_CRSEN_Pos                 (1U)

+#define RCC_APB1HENR_CRSEN_Msk                 (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1HENR_CRSEN                     RCC_APB1HENR_CRSEN_Msk

+#define RCC_APB1HENR_SWPMIEN_Pos               (2U)

+#define RCC_APB1HENR_SWPMIEN_Msk               (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1HENR_SWPMIEN                   RCC_APB1HENR_SWPMIEN_Msk

+#define RCC_APB1HENR_OPAMPEN_Pos               (4U)

+#define RCC_APB1HENR_OPAMPEN_Msk               (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1HENR_OPAMPEN                   RCC_APB1HENR_OPAMPEN_Msk

+#define RCC_APB1HENR_MDIOSEN_Pos               (5U)

+#define RCC_APB1HENR_MDIOSEN_Msk               (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1HENR_MDIOSEN                   RCC_APB1HENR_MDIOSEN_Msk

+#define RCC_APB1HENR_FDCANEN_Pos               (8U)

+#define RCC_APB1HENR_FDCANEN_Msk               (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1HENR_FDCANEN                   RCC_APB1HENR_FDCANEN_Msk

+

+/********************  Bit definition for RCC_APB2ENR register  ******************/

+#define RCC_APB2ENR_TIM1EN_Pos                 (0U)

+#define RCC_APB2ENR_TIM1EN_Msk                 (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */

+#define RCC_APB2ENR_TIM1EN                     RCC_APB2ENR_TIM1EN_Msk

+#define RCC_APB2ENR_TIM8EN_Pos                 (1U)

+#define RCC_APB2ENR_TIM8EN_Msk                 (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */

+#define RCC_APB2ENR_TIM8EN                     RCC_APB2ENR_TIM8EN_Msk

+#define RCC_APB2ENR_USART1EN_Pos               (4U)

+#define RCC_APB2ENR_USART1EN_Msk               (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */

+#define RCC_APB2ENR_USART1EN                   RCC_APB2ENR_USART1EN_Msk

+#define RCC_APB2ENR_USART6EN_Pos               (5U)

+#define RCC_APB2ENR_USART6EN_Msk               (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */

+#define RCC_APB2ENR_USART6EN                   RCC_APB2ENR_USART6EN_Msk

+#define RCC_APB2ENR_UART9EN_Pos                (6U)

+#define RCC_APB2ENR_UART9EN_Msk                (0x1UL << RCC_APB2ENR_UART9EN_Pos) /*!< 0x00000040 */

+#define RCC_APB2ENR_UART9EN                    RCC_APB2ENR_UART9EN_Msk

+#define RCC_APB2ENR_USART10EN_Pos              (7U)

+#define RCC_APB2ENR_USART10EN_Msk              (0x1UL << RCC_APB2ENR_USART10EN_Pos) /*!< 0x00000080 */

+#define RCC_APB2ENR_USART10EN                   RCC_APB2ENR_USART10EN_Msk

+#define RCC_APB2ENR_SPI1EN_Pos                 (12U)

+#define RCC_APB2ENR_SPI1EN_Msk                 (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */

+#define RCC_APB2ENR_SPI1EN                     RCC_APB2ENR_SPI1EN_Msk

+#define RCC_APB2ENR_SPI4EN_Pos                 (13U)

+#define RCC_APB2ENR_SPI4EN_Msk                 (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */

+#define RCC_APB2ENR_SPI4EN                     RCC_APB2ENR_SPI4EN_Msk

+#define RCC_APB2ENR_TIM15EN_Pos                (16U)

+#define RCC_APB2ENR_TIM15EN_Msk                (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */

+#define RCC_APB2ENR_TIM15EN                    RCC_APB2ENR_TIM15EN_Msk

+#define RCC_APB2ENR_TIM16EN_Pos                (17U)

+#define RCC_APB2ENR_TIM16EN_Msk                (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */

+#define RCC_APB2ENR_TIM16EN                    RCC_APB2ENR_TIM16EN_Msk

+#define RCC_APB2ENR_TIM17EN_Pos                (18U)

+#define RCC_APB2ENR_TIM17EN_Msk                (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */

+#define RCC_APB2ENR_TIM17EN                    RCC_APB2ENR_TIM17EN_Msk

+#define RCC_APB2ENR_SPI5EN_Pos                 (20U)

+#define RCC_APB2ENR_SPI5EN_Msk                 (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */

+#define RCC_APB2ENR_SPI5EN                     RCC_APB2ENR_SPI5EN_Msk

+#define RCC_APB2ENR_SAI1EN_Pos                 (22U)

+#define RCC_APB2ENR_SAI1EN_Msk                 (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */

+#define RCC_APB2ENR_SAI1EN                     RCC_APB2ENR_SAI1EN_Msk

+#define RCC_APB2ENR_SAI2EN_Pos                 (23U)

+#define RCC_APB2ENR_SAI2EN_Msk                 (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */

+#define RCC_APB2ENR_SAI2EN                     RCC_APB2ENR_SAI2EN_Msk

+#define RCC_APB2ENR_DFSDM1EN_Pos               (30U)

+#define RCC_APB2ENR_DFSDM1EN_Msk               (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x40000000 */

+#define RCC_APB2ENR_DFSDM1EN                   RCC_APB2ENR_DFSDM1EN_Msk

+

+/********************  Bit definition for RCC_APB4ENR register  ******************/

+#define RCC_APB4ENR_SYSCFGEN_Pos               (1U)

+#define RCC_APB4ENR_SYSCFGEN_Msk               (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */

+#define RCC_APB4ENR_SYSCFGEN                   RCC_APB4ENR_SYSCFGEN_Msk

+#define RCC_APB4ENR_LPUART1EN_Pos              (3U)

+#define RCC_APB4ENR_LPUART1EN_Msk              (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */

+#define RCC_APB4ENR_LPUART1EN                  RCC_APB4ENR_LPUART1EN_Msk

+#define RCC_APB4ENR_SPI6EN_Pos                 (5U)

+#define RCC_APB4ENR_SPI6EN_Msk                 (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */

+#define RCC_APB4ENR_SPI6EN                     RCC_APB4ENR_SPI6EN_Msk

+#define RCC_APB4ENR_I2C4EN_Pos                 (7U)

+#define RCC_APB4ENR_I2C4EN_Msk                 (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */

+#define RCC_APB4ENR_I2C4EN                     RCC_APB4ENR_I2C4EN_Msk

+#define RCC_APB4ENR_LPTIM2EN_Pos               (9U)

+#define RCC_APB4ENR_LPTIM2EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */

+#define RCC_APB4ENR_LPTIM2EN                   RCC_APB4ENR_LPTIM2EN_Msk

+#define RCC_APB4ENR_LPTIM3EN_Pos               (10U)

+#define RCC_APB4ENR_LPTIM3EN_Msk               (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */

+#define RCC_APB4ENR_LPTIM3EN                   RCC_APB4ENR_LPTIM3EN_Msk

+#define RCC_APB4ENR_DAC2EN_Pos                 (13U)

+#define RCC_APB4ENR_DAC2EN_Msk                 (0x1UL << RCC_APB4ENR_DAC2EN_Pos) /*!< 0x00002000 */

+#define RCC_APB4ENR_DAC2EN                     RCC_APB4ENR_DAC2EN_Msk

+#define RCC_APB4ENR_COMP12EN_Pos               (14U)

+#define RCC_APB4ENR_COMP12EN_Msk               (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */

+#define RCC_APB4ENR_COMP12EN                   RCC_APB4ENR_COMP12EN_Msk

+#define RCC_APB4ENR_VREFEN_Pos                 (15U)

+#define RCC_APB4ENR_VREFEN_Msk                 (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */

+#define RCC_APB4ENR_VREFEN                     RCC_APB4ENR_VREFEN_Msk

+#define RCC_APB4ENR_RTCAPBEN_Pos               (16U)

+#define RCC_APB4ENR_RTCAPBEN_Msk               (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */

+#define RCC_APB4ENR_RTCAPBEN                   RCC_APB4ENR_RTCAPBEN_Msk

+

+#define RCC_APB4ENR_DTSEN_Pos                  (26U)

+#define RCC_APB4ENR_DTSEN_Msk                  (0x1UL << RCC_APB4ENR_DTSEN_Pos) /*!< 0x04000000 */

+#define RCC_APB4ENR_DTSEN                      RCC_APB4ENR_DTSEN_Msk

+#define RCC_APB4ENR_DFSDM2EN_Pos               (27U)

+#define RCC_APB4ENR_DFSDM2EN_Msk               (0x1UL << RCC_APB4ENR_DFSDM2EN_Pos) /*!< 0x08000000 */

+#define RCC_APB4ENR_DFSDM2EN                   RCC_APB4ENR_DFSDM2EN_Msk

+

+/********************  Bit definition for RCC_AHB3RSTR register  ***************/

+#define RCC_AHB3RSTR_MDMARST_Pos               (0U)

+#define RCC_AHB3RSTR_MDMARST_Msk               (0x1UL << RCC_AHB3RSTR_MDMARST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB3RSTR_MDMARST                   RCC_AHB3RSTR_MDMARST_Msk

+#define RCC_AHB3RSTR_DMA2DRST_Pos              (4U)

+#define RCC_AHB3RSTR_DMA2DRST_Msk              (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos)     /*!< 0x00000010 */

+#define RCC_AHB3RSTR_DMA2DRST                  RCC_AHB3RSTR_DMA2DRST_Msk

+#define RCC_AHB3RSTR_JPGDECRST_Pos             (5U)

+#define RCC_AHB3RSTR_JPGDECRST_Msk             (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos)    /*!< 0x00000020 */

+#define RCC_AHB3RSTR_JPGDECRST                 RCC_AHB3RSTR_JPGDECRST_Msk

+#define RCC_AHB3RSTR_FMCRST_Pos                (12U)

+#define RCC_AHB3RSTR_FMCRST_Msk                (0x1UL << RCC_AHB3RSTR_FMCRST_Pos)      /*!< 0x00001000 */

+#define RCC_AHB3RSTR_FMCRST                    RCC_AHB3RSTR_FMCRST_Msk

+#define RCC_AHB3RSTR_OSPI1RST_Pos              (14U)

+#define RCC_AHB3RSTR_OSPI1RST_Msk              (0x1UL << RCC_AHB3RSTR_OSPI1RST_Pos)    /*!< 0x00004000 */

+#define RCC_AHB3RSTR_OSPI1RST                   RCC_AHB3RSTR_OSPI1RST_Msk

+#define RCC_AHB3RSTR_SDMMC1RST_Pos             (16U)

+#define RCC_AHB3RSTR_SDMMC1RST_Msk             (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos)   /*!< 0x00010000 */

+#define RCC_AHB3RSTR_SDMMC1RST                 RCC_AHB3RSTR_SDMMC1RST_Msk

+#define RCC_AHB3RSTR_OSPI2RST_Pos              (19U)

+#define RCC_AHB3RSTR_OSPI2RST_Msk              (0x1UL << RCC_AHB3RSTR_OSPI2RST_Pos)    /*!< 0x00008000 */

+#define RCC_AHB3RSTR_OSPI2RST                  RCC_AHB3RSTR_OSPI2RST_Msk

+#define RCC_AHB3RSTR_IOMNGRRST_Pos             (21U)

+#define RCC_AHB3RSTR_IOMNGRRST_Msk             (0x1UL << RCC_AHB3RSTR_IOMNGRRST_Pos)   /*!< 0x00020000 */

+#define RCC_AHB3RSTR_IOMNGRRST                 RCC_AHB3RSTR_IOMNGRRST_Msk

+#define RCC_AHB3RSTR_OTFDEC1RST_Pos            (22U)

+#define RCC_AHB3RSTR_OTFDEC1RST_Msk            (0x1UL << RCC_AHB3RSTR_OTFDEC1RST_Pos)  /*!< 0x00040000 */

+#define RCC_AHB3RSTR_OTFDEC1RST                RCC_AHB3RSTR_OTFDEC1RST_Msk

+#define RCC_AHB3RSTR_OTFDEC2RST_Pos            (23U)

+#define RCC_AHB3RSTR_OTFDEC2RST_Msk            (0x1UL << RCC_AHB3RSTR_OTFDEC2RST_Pos)  /*!< 0x00080000 */

+#define RCC_AHB3RSTR_OTFDEC2RST                RCC_AHB3RSTR_OTFDEC2RST_Msk

+#define RCC_AHB3RSTR_GFXMMURST_Pos             (24U)

+#define RCC_AHB3RSTR_GFXMMURST_Msk             (0x1UL << RCC_AHB3RSTR_GFXMMURST_Pos)   /*!< 0x00100000 */

+#define RCC_AHB3RSTR_GFXMMURST                 RCC_AHB3RSTR_GFXMMURST_Msk

+

+

+/********************  Bit definition for RCC_AHB1RSTR register  ***************/

+#define RCC_AHB1RSTR_DMA1RST_Pos               (0U)

+#define RCC_AHB1RSTR_DMA1RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB1RSTR_DMA1RST                   RCC_AHB1RSTR_DMA1RST_Msk

+#define RCC_AHB1RSTR_DMA2RST_Pos               (1U)

+#define RCC_AHB1RSTR_DMA2RST_Msk               (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos)      /*!< 0x00000002 */

+#define RCC_AHB1RSTR_DMA2RST                   RCC_AHB1RSTR_DMA2RST_Msk

+#define RCC_AHB1RSTR_ADC12RST_Pos              (5U)

+#define RCC_AHB1RSTR_ADC12RST_Msk              (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos)     /*!< 0x00000020 */

+#define RCC_AHB1RSTR_ADC12RST                  RCC_AHB1RSTR_ADC12RST_Msk

+#define RCC_AHB1RSTR_CRCRST_Pos                (9U)

+#define RCC_AHB1RSTR_CRCRST_Msk                (0x1UL << RCC_AHB1RSTR_CRCRST_Pos)       /*!< 0x00000200 */

+#define RCC_AHB1RSTR_CRCRST                    RCC_AHB1RSTR_CRCRST_Msk

+#define RCC_AHB1RSTR_USB1OTGHSRST_Pos          (25U)

+#define RCC_AHB1RSTR_USB1OTGHSRST_Msk          (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */

+#define RCC_AHB1RSTR_USB1OTGHSRST              RCC_AHB1RSTR_USB1OTGHSRST_Msk

+

+/********************  Bit definition for RCC_AHB2RSTR register  ***************/

+#define RCC_AHB2RSTR_DCMI_PSSIRST_Pos          (0U)

+#define RCC_AHB2RSTR_DCMI_PSSIRST_Msk          (0x1UL << RCC_AHB2RSTR_DCMI_PSSIRST_Pos)  /*!< 0x00000001 */

+#define RCC_AHB2RSTR_DCMI_PSSIRST              RCC_AHB2RSTR_DCMI_PSSIRST_Msk

+#define RCC_AHB2RSTR_HSEMRST_Pos               (2U)

+#define RCC_AHB2RSTR_HSEMRST_Msk               (0x1UL << RCC_AHB2RSTR_HSEMRST_Pos)       /*!< 0x00000004 */

+#define RCC_AHB2RSTR_HSEMRST                   RCC_AHB2RSTR_HSEMRST_Msk

+#define RCC_AHB2RSTR_CRYPRST_Pos               (4U)

+#define RCC_AHB2RSTR_CRYPRST_Msk               (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos)       /*!< 0x00000010 */

+#define RCC_AHB2RSTR_CRYPRST                   RCC_AHB2RSTR_CRYPRST_Msk

+#define RCC_AHB2RSTR_HASHRST_Pos               (5U)

+#define RCC_AHB2RSTR_HASHRST_Msk               (0x1UL << RCC_AHB2RSTR_HASHRST_Pos)       /*!< 0x00000020 */

+#define RCC_AHB2RSTR_HASHRST                   RCC_AHB2RSTR_HASHRST_Msk

+#define RCC_AHB2RSTR_RNGRST_Pos                (6U)

+#define RCC_AHB2RSTR_RNGRST_Msk                (0x1UL << RCC_AHB2RSTR_RNGRST_Pos)        /*!< 0x00000040 */

+#define RCC_AHB2RSTR_RNGRST                    RCC_AHB2RSTR_RNGRST_Msk

+#define RCC_AHB2RSTR_SDMMC2RST_Pos             (9U)

+#define RCC_AHB2RSTR_SDMMC2RST_Msk             (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos)     /*!< 0x00000200 */

+#define RCC_AHB2RSTR_SDMMC2RST                 RCC_AHB2RSTR_SDMMC2RST_Msk

+#define RCC_AHB2RSTR_BDMA1RST_Pos              (11U)

+#define RCC_AHB2RSTR_BDMA1RST_Msk              (0x1UL << RCC_AHB2RSTR_BDMA1RST_Pos)      /*!< 0x00000200 */

+#define RCC_AHB2RSTR_BDMA1RST                  RCC_AHB2RSTR_BDMA1RST_Msk

+

+/* Legacy define */

+#define RCC_AHB2RSTR_DCMIRST_Pos               RCC_AHB2RSTR_DCMI_PSSIRST_Pos

+#define RCC_AHB2RSTR_DCMIRST_Msk               RCC_AHB2RSTR_DCMI_PSSIRST_Msk

+#define RCC_AHB2RSTR_DCMIRST                   RCC_AHB2RSTR_DCMI_PSSIRST

+/********************  Bit definition for RCC_AHB4RSTR register  ******************/

+#define RCC_AHB4RSTR_GPIOARST_Pos              (0U)

+#define RCC_AHB4RSTR_GPIOARST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos)      /*!< 0x00000001 */

+#define RCC_AHB4RSTR_GPIOARST                  RCC_AHB4RSTR_GPIOARST_Msk

+#define RCC_AHB4RSTR_GPIOBRST_Pos              (1U)

+#define RCC_AHB4RSTR_GPIOBRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos)      /*!< 0x00000002 */

+#define RCC_AHB4RSTR_GPIOBRST                  RCC_AHB4RSTR_GPIOBRST_Msk

+#define RCC_AHB4RSTR_GPIOCRST_Pos              (2U)

+#define RCC_AHB4RSTR_GPIOCRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos)      /*!< 0x00000004 */

+#define RCC_AHB4RSTR_GPIOCRST                  RCC_AHB4RSTR_GPIOCRST_Msk

+#define RCC_AHB4RSTR_GPIODRST_Pos              (3U)

+#define RCC_AHB4RSTR_GPIODRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos)      /*!< 0x00000008 */

+#define RCC_AHB4RSTR_GPIODRST                  RCC_AHB4RSTR_GPIODRST_Msk

+#define RCC_AHB4RSTR_GPIOERST_Pos              (4U)

+#define RCC_AHB4RSTR_GPIOERST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos)      /*!< 0x00000010 */

+#define RCC_AHB4RSTR_GPIOERST                  RCC_AHB4RSTR_GPIOERST_Msk

+#define RCC_AHB4RSTR_GPIOFRST_Pos              (5U)

+#define RCC_AHB4RSTR_GPIOFRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos)       /*!< 0x00000020 */

+#define RCC_AHB4RSTR_GPIOFRST                  RCC_AHB4RSTR_GPIOFRST_Msk

+#define RCC_AHB4RSTR_GPIOGRST_Pos              (6U)

+#define RCC_AHB4RSTR_GPIOGRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos)       /*!< 0x00000040 */

+#define RCC_AHB4RSTR_GPIOGRST                  RCC_AHB4RSTR_GPIOGRST_Msk

+#define RCC_AHB4RSTR_GPIOHRST_Pos              (7U)

+#define RCC_AHB4RSTR_GPIOHRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos)       /*!< 0x00000080 */

+#define RCC_AHB4RSTR_GPIOHRST                  RCC_AHB4RSTR_GPIOHRST_Msk

+#define RCC_AHB4RSTR_GPIOIRST_Pos              (8U)

+#define RCC_AHB4RSTR_GPIOIRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos)       /*!< 0x00000100 */

+#define RCC_AHB4RSTR_GPIOIRST                  RCC_AHB4RSTR_GPIOIRST_Msk

+#define RCC_AHB4RSTR_GPIOJRST_Pos              (9U)

+#define RCC_AHB4RSTR_GPIOJRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos)       /*!< 0x00000200 */

+#define RCC_AHB4RSTR_GPIOJRST                  RCC_AHB4RSTR_GPIOJRST_Msk

+#define RCC_AHB4RSTR_GPIOKRST_Pos              (10U)

+#define RCC_AHB4RSTR_GPIOKRST_Msk              (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos)       /*!< 0x00000400 */

+#define RCC_AHB4RSTR_GPIOKRST                  RCC_AHB4RSTR_GPIOKRST_Msk

+#define RCC_AHB4RSTR_BDMA2RST_Pos              (21U)

+#define RCC_AHB4RSTR_BDMA2RST_Msk              (0x1UL << RCC_AHB4RSTR_BDMA2RST_Pos)       /*!< 0x00200000 */

+#define RCC_AHB4RSTR_BDMA2RST                   RCC_AHB4RSTR_BDMA2RST_Msk

+

+

+/********************  Bit definition for RCC_APB3RSTR register  ******************/

+#define RCC_APB3RSTR_LTDCRST_Pos               (3U)

+#define RCC_APB3RSTR_LTDCRST_Msk               (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */

+#define RCC_APB3RSTR_LTDCRST                   RCC_APB3RSTR_LTDCRST_Msk

+

+/********************  Bit definition for RCC_APB1LRSTR register  ******************/

+

+#define RCC_APB1LRSTR_TIM2RST_Pos              (0U)

+#define RCC_APB1LRSTR_TIM2RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */

+#define RCC_APB1LRSTR_TIM2RST                  RCC_APB1LRSTR_TIM2RST_Msk

+#define RCC_APB1LRSTR_TIM3RST_Pos              (1U)

+#define RCC_APB1LRSTR_TIM3RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */

+#define RCC_APB1LRSTR_TIM3RST                  RCC_APB1LRSTR_TIM3RST_Msk

+#define RCC_APB1LRSTR_TIM4RST_Pos              (2U)

+#define RCC_APB1LRSTR_TIM4RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */

+#define RCC_APB1LRSTR_TIM4RST                  RCC_APB1LRSTR_TIM4RST_Msk

+#define RCC_APB1LRSTR_TIM5RST_Pos              (3U)

+#define RCC_APB1LRSTR_TIM5RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */

+#define RCC_APB1LRSTR_TIM5RST                  RCC_APB1LRSTR_TIM5RST_Msk

+#define RCC_APB1LRSTR_TIM6RST_Pos              (4U)

+#define RCC_APB1LRSTR_TIM6RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */

+#define RCC_APB1LRSTR_TIM6RST                  RCC_APB1LRSTR_TIM6RST_Msk

+#define RCC_APB1LRSTR_TIM7RST_Pos              (5U)

+#define RCC_APB1LRSTR_TIM7RST_Msk              (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */

+#define RCC_APB1LRSTR_TIM7RST                  RCC_APB1LRSTR_TIM7RST_Msk

+#define RCC_APB1LRSTR_TIM12RST_Pos             (6U)

+#define RCC_APB1LRSTR_TIM12RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */

+#define RCC_APB1LRSTR_TIM12RST                 RCC_APB1LRSTR_TIM12RST_Msk

+#define RCC_APB1LRSTR_TIM13RST_Pos             (7U)

+#define RCC_APB1LRSTR_TIM13RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */

+#define RCC_APB1LRSTR_TIM13RST                 RCC_APB1LRSTR_TIM13RST_Msk

+#define RCC_APB1LRSTR_TIM14RST_Pos             (8U)

+#define RCC_APB1LRSTR_TIM14RST_Msk             (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */

+#define RCC_APB1LRSTR_TIM14RST                 RCC_APB1LRSTR_TIM14RST_Msk

+#define RCC_APB1LRSTR_LPTIM1RST_Pos            (9U)

+#define RCC_APB1LRSTR_LPTIM1RST_Msk            (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */

+#define RCC_APB1LRSTR_LPTIM1RST                RCC_APB1LRSTR_LPTIM1RST_Msk

+#define RCC_APB1LRSTR_SPI2RST_Pos              (14U)

+#define RCC_APB1LRSTR_SPI2RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */

+#define RCC_APB1LRSTR_SPI2RST                  RCC_APB1LRSTR_SPI2RST_Msk

+#define RCC_APB1LRSTR_SPI3RST_Pos              (15U)

+#define RCC_APB1LRSTR_SPI3RST_Msk              (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */

+#define RCC_APB1LRSTR_SPI3RST                  RCC_APB1LRSTR_SPI3RST_Msk

+#define RCC_APB1LRSTR_SPDIFRXRST_Pos           (16U)

+#define RCC_APB1LRSTR_SPDIFRXRST_Msk           (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */

+#define RCC_APB1LRSTR_SPDIFRXRST               RCC_APB1LRSTR_SPDIFRXRST_Msk

+#define RCC_APB1LRSTR_USART2RST_Pos            (17U)

+#define RCC_APB1LRSTR_USART2RST_Msk            (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */

+#define RCC_APB1LRSTR_USART2RST                RCC_APB1LRSTR_USART2RST_Msk

+#define RCC_APB1LRSTR_USART3RST_Pos            (18U)

+#define RCC_APB1LRSTR_USART3RST_Msk            (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */

+#define RCC_APB1LRSTR_USART3RST                RCC_APB1LRSTR_USART3RST_Msk

+#define RCC_APB1LRSTR_UART4RST_Pos             (19U)

+#define RCC_APB1LRSTR_UART4RST_Msk             (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */

+#define RCC_APB1LRSTR_UART4RST                 RCC_APB1LRSTR_UART4RST_Msk

+#define RCC_APB1LRSTR_UART5RST_Pos             (20U)

+#define RCC_APB1LRSTR_UART5RST_Msk             (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */

+#define RCC_APB1LRSTR_UART5RST                 RCC_APB1LRSTR_UART5RST_Msk

+#define RCC_APB1LRSTR_I2C1RST_Pos              (21U)

+#define RCC_APB1LRSTR_I2C1RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */

+#define RCC_APB1LRSTR_I2C1RST                  RCC_APB1LRSTR_I2C1RST_Msk

+#define RCC_APB1LRSTR_I2C2RST_Pos              (22U)

+#define RCC_APB1LRSTR_I2C2RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */

+#define RCC_APB1LRSTR_I2C2RST                  RCC_APB1LRSTR_I2C2RST_Msk

+#define RCC_APB1LRSTR_I2C3RST_Pos              (23U)

+#define RCC_APB1LRSTR_I2C3RST_Msk              (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */

+#define RCC_APB1LRSTR_I2C3RST                  RCC_APB1LRSTR_I2C3RST_Msk

+#define RCC_APB1LRSTR_CECRST_Pos               (27U)

+#define RCC_APB1LRSTR_CECRST_Msk               (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */

+#define RCC_APB1LRSTR_CECRST                   RCC_APB1LRSTR_CECRST_Msk

+#define RCC_APB1LRSTR_DAC12RST_Pos             (29U)

+#define RCC_APB1LRSTR_DAC12RST_Msk             (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */

+#define RCC_APB1LRSTR_DAC12RST                 RCC_APB1LRSTR_DAC12RST_Msk

+#define RCC_APB1LRSTR_UART7RST_Pos             (30U)

+#define RCC_APB1LRSTR_UART7RST_Msk             (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */

+#define RCC_APB1LRSTR_UART7RST                 RCC_APB1LRSTR_UART7RST_Msk

+#define RCC_APB1LRSTR_UART8RST_Pos             (31U)

+#define RCC_APB1LRSTR_UART8RST_Msk             (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */

+#define RCC_APB1LRSTR_UART8RST                 RCC_APB1LRSTR_UART8RST_Msk

+

+/* Legacy define */

+#define RCC_APB1LRSTR_HDMICECRST_Pos           RCC_APB1LRSTR_CECRST_Pos

+#define RCC_APB1LRSTR_HDMICECRST_Msk           RCC_APB1LRSTR_CECRST_Msk

+#define RCC_APB1LRSTR_HDMICECRST               RCC_APB1LRSTR_CECRST

+/********************  Bit definition for RCC_APB1HRSTR register  ******************/

+#define RCC_APB1HRSTR_CRSRST_Pos               (1U)

+#define RCC_APB1HRSTR_CRSRST_Msk               (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */

+#define RCC_APB1HRSTR_CRSRST                   RCC_APB1HRSTR_CRSRST_Msk

+#define RCC_APB1HRSTR_SWPMIRST_Pos             (2U)

+#define RCC_APB1HRSTR_SWPMIRST_Msk             (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */

+#define RCC_APB1HRSTR_SWPMIRST                 RCC_APB1HRSTR_SWPMIRST_Msk

+#define RCC_APB1HRSTR_OPAMPRST_Pos             (4U)

+#define RCC_APB1HRSTR_OPAMPRST_Msk             (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */

+#define RCC_APB1HRSTR_OPAMPRST                 RCC_APB1HRSTR_OPAMPRST_Msk

+#define RCC_APB1HRSTR_MDIOSRST_Pos             (5U)

+#define RCC_APB1HRSTR_MDIOSRST_Msk             (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */

+#define RCC_APB1HRSTR_MDIOSRST                 RCC_APB1HRSTR_MDIOSRST_Msk

+#define RCC_APB1HRSTR_FDCANRST_Pos             (8U)

+#define RCC_APB1HRSTR_FDCANRST_Msk             (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */

+#define RCC_APB1HRSTR_FDCANRST                 RCC_APB1HRSTR_FDCANRST_Msk

+

+/********************  Bit definition for RCC_APB2RSTR register  ******************/

+#define RCC_APB2RSTR_TIM1RST_Pos               (0U)

+#define RCC_APB2RSTR_TIM1RST_Msk               (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */

+#define RCC_APB2RSTR_TIM1RST                   RCC_APB2RSTR_TIM1RST_Msk

+#define RCC_APB2RSTR_TIM8RST_Pos               (1U)

+#define RCC_APB2RSTR_TIM8RST_Msk               (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */

+#define RCC_APB2RSTR_TIM8RST                   RCC_APB2RSTR_TIM8RST_Msk

+#define RCC_APB2RSTR_USART1RST_Pos             (4U)

+#define RCC_APB2RSTR_USART1RST_Msk             (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */

+#define RCC_APB2RSTR_USART1RST                 RCC_APB2RSTR_USART1RST_Msk

+#define RCC_APB2RSTR_USART6RST_Pos             (5U)

+#define RCC_APB2RSTR_USART6RST_Msk             (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */

+#define RCC_APB2RSTR_USART6RST                 RCC_APB2RSTR_USART6RST_Msk

+#define RCC_APB2RSTR_UART9RST_Pos              (6U)

+#define RCC_APB2RSTR_UART9RST_Msk              (0x1UL << RCC_APB2RSTR_UART9RST_Pos) /*!< 0x00000040 */

+#define RCC_APB2RSTR_UART9RST                  RCC_APB2RSTR_UART9RST_Msk

+#define RCC_APB2RSTR_USART10RST_Pos            (7U)

+#define RCC_APB2RSTR_USART10RST_Msk            (0x1UL << RCC_APB2RSTR_USART10RST_Pos) /*!< 0x00000080 */

+#define RCC_APB2RSTR_USART10RST                RCC_APB2RSTR_USART10RST_Msk

+#define RCC_APB2RSTR_SPI1RST_Pos               (12U)

+#define RCC_APB2RSTR_SPI1RST_Msk               (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */

+#define RCC_APB2RSTR_SPI1RST                   RCC_APB2RSTR_SPI1RST_Msk

+#define RCC_APB2RSTR_SPI4RST_Pos               (13U)

+#define RCC_APB2RSTR_SPI4RST_Msk               (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */

+#define RCC_APB2RSTR_SPI4RST                   RCC_APB2RSTR_SPI4RST_Msk

+#define RCC_APB2RSTR_TIM15RST_Pos              (16U)

+#define RCC_APB2RSTR_TIM15RST_Msk              (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */

+#define RCC_APB2RSTR_TIM15RST                  RCC_APB2RSTR_TIM15RST_Msk

+#define RCC_APB2RSTR_TIM16RST_Pos              (17U)

+#define RCC_APB2RSTR_TIM16RST_Msk              (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */

+#define RCC_APB2RSTR_TIM16RST                  RCC_APB2RSTR_TIM16RST_Msk

+#define RCC_APB2RSTR_TIM17RST_Pos              (18U)

+#define RCC_APB2RSTR_TIM17RST_Msk              (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */

+#define RCC_APB2RSTR_TIM17RST                  RCC_APB2RSTR_TIM17RST_Msk

+#define RCC_APB2RSTR_SPI5RST_Pos               (20U)

+#define RCC_APB2RSTR_SPI5RST_Msk               (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */

+#define RCC_APB2RSTR_SPI5RST                   RCC_APB2RSTR_SPI5RST_Msk

+#define RCC_APB2RSTR_SAI1RST_Pos               (22U)

+#define RCC_APB2RSTR_SAI1RST_Msk               (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */

+#define RCC_APB2RSTR_SAI1RST                   RCC_APB2RSTR_SAI1RST_Msk

+#define RCC_APB2RSTR_SAI2RST_Pos               (23U)

+#define RCC_APB2RSTR_SAI2RST_Msk               (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */

+#define RCC_APB2RSTR_SAI2RST                   RCC_APB2RSTR_SAI2RST_Msk

+#define RCC_APB2RSTR_DFSDM1RST_Pos             (30U)

+#define RCC_APB2RSTR_DFSDM1RST_Msk             (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */

+#define RCC_APB2RSTR_DFSDM1RST                 RCC_APB2RSTR_DFSDM1RST_Msk

+

+/********************  Bit definition for RCC_APB4RSTR register  ******************/

+#define RCC_APB4RSTR_SYSCFGRST_Pos             (1U)

+#define RCC_APB4RSTR_SYSCFGRST_Msk             (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */

+#define RCC_APB4RSTR_SYSCFGRST                 RCC_APB4RSTR_SYSCFGRST_Msk

+#define RCC_APB4RSTR_LPUART1RST_Pos            (3U)

+#define RCC_APB4RSTR_LPUART1RST_Msk            (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */

+#define RCC_APB4RSTR_LPUART1RST                RCC_APB4RSTR_LPUART1RST_Msk

+#define RCC_APB4RSTR_SPI6RST_Pos               (5U)

+#define RCC_APB4RSTR_SPI6RST_Msk               (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */

+#define RCC_APB4RSTR_SPI6RST                   RCC_APB4RSTR_SPI6RST_Msk

+#define RCC_APB4RSTR_I2C4RST_Pos               (7U)

+#define RCC_APB4RSTR_I2C4RST_Msk               (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */

+#define RCC_APB4RSTR_I2C4RST                   RCC_APB4RSTR_I2C4RST_Msk

+#define RCC_APB4RSTR_LPTIM2RST_Pos             (9U)

+#define RCC_APB4RSTR_LPTIM2RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */

+#define RCC_APB4RSTR_LPTIM2RST                 RCC_APB4RSTR_LPTIM2RST_Msk

+#define RCC_APB4RSTR_LPTIM3RST_Pos             (10U)

+#define RCC_APB4RSTR_LPTIM3RST_Msk             (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */

+#define RCC_APB4RSTR_LPTIM3RST                 RCC_APB4RSTR_LPTIM3RST_Msk

+#define RCC_APB4RSTR_DAC2RST_Pos               (13U)

+#define RCC_APB4RSTR_DAC2RST_Msk               (0x1UL << RCC_APB4RSTR_DAC2RST_Pos) /*!< 0x00001000 */

+#define RCC_APB4RSTR_DAC2RST                    RCC_APB4RSTR_DAC2RST_Msk

+#define RCC_APB4RSTR_COMP12RST_Pos             (14U)

+#define RCC_APB4RSTR_COMP12RST_Msk             (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */

+#define RCC_APB4RSTR_COMP12RST                 RCC_APB4RSTR_COMP12RST_Msk

+#define RCC_APB4RSTR_VREFRST_Pos               (15U)

+#define RCC_APB4RSTR_VREFRST_Msk               (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */

+#define RCC_APB4RSTR_VREFRST                   RCC_APB4RSTR_VREFRST_Msk

+

+#define RCC_APB4RSTR_DTSRST_Pos                (26U)

+#define RCC_APB4RSTR_DTSRST_Msk                (0x1UL << RCC_APB4RSTR_DTSRST_Pos) /*!< 0x04000000 */

+#define RCC_APB4RSTR_DTSRST                    RCC_APB4RSTR_DTSRST_Msk

+#define RCC_APB4RSTR_DFSDM2RST_Pos             (27U)

+#define RCC_APB4RSTR_DFSDM2RST_Msk             (0x1UL << RCC_APB4RSTR_DFSDM2RST_Pos) /*!< 0x08000000 */

+#define RCC_APB4RSTR_DFSDM2RST                 RCC_APB4RSTR_DFSDM2RST_Msk

+

+

+/********************  Bit definition for RCC_SRDAMR register  ********************/

+#define RCC_SRDAMR_BDMA2AMEN_Pos               (0U)

+#define RCC_SRDAMR_BDMA2AMEN_Msk               (0x1UL << RCC_SRDAMR_BDMA2AMEN_Pos) /*!< 0x00000001 */

+#define RCC_SRDAMR_BDMA2AMEN                   RCC_SRDAMR_BDMA2AMEN_Msk

+#define RCC_SRDAMR_GPIOAMEN_Pos                (1U)

+#define RCC_SRDAMR_GPIOAMEN_Msk                (0x1UL << RCC_SRDAMR_GPIOAMEN_Pos) /*!< 0x00000001 */

+#define RCC_SRDAMR_GPIOAMEN                    RCC_SRDAMR_GPIOAMEN_Msk

+#define RCC_SRDAMR_LPUART1AMEN_Pos             (3U)

+#define RCC_SRDAMR_LPUART1AMEN_Msk             (0x1UL << RCC_SRDAMR_LPUART1AMEN_Pos) /*!< 0x00000008 */

+#define RCC_SRDAMR_LPUART1AMEN                 RCC_SRDAMR_LPUART1AMEN_Msk

+#define RCC_SRDAMR_SPI6AMEN_Pos                (5U)

+#define RCC_SRDAMR_SPI6AMEN_Msk                (0x1UL << RCC_SRDAMR_SPI6AMEN_Pos) /*!< 0x00000020 */

+#define RCC_SRDAMR_SPI6AMEN                    RCC_SRDAMR_SPI6AMEN_Msk

+#define RCC_SRDAMR_I2C4AMEN_Pos                (7U)

+#define RCC_SRDAMR_I2C4AMEN_Msk                (0x1UL << RCC_SRDAMR_I2C4AMEN_Pos) /*!< 0x00000080 */

+#define RCC_SRDAMR_I2C4AMEN                    RCC_SRDAMR_I2C4AMEN_Msk

+#define RCC_SRDAMR_LPTIM2AMEN_Pos              (9U)

+#define RCC_SRDAMR_LPTIM2AMEN_Msk              (0x1UL << RCC_SRDAMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */

+#define RCC_SRDAMR_LPTIM2AMEN                  RCC_SRDAMR_LPTIM2AMEN_Msk

+#define RCC_SRDAMR_LPTIM3AMEN_Pos              (10U)

+#define RCC_SRDAMR_LPTIM3AMEN_Msk              (0x1UL << RCC_SRDAMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */

+#define RCC_SRDAMR_LPTIM3AMEN                  RCC_SRDAMR_LPTIM3AMEN_Msk

+#define RCC_SRDAMR_DAC2AMEN_Pos                (13U)

+#define RCC_SRDAMR_DAC2AMEN_Msk                (0x1UL << RCC_SRDAMR_DAC2AMEN_Pos) /*!< 0x00004000 */

+#define RCC_SRDAMR_DAC2AMEN                    RCC_SRDAMR_DAC2AMEN_Msk

+#define RCC_SRDAMR_COMP12AMEN_Pos              (14U)

+#define RCC_SRDAMR_COMP12AMEN_Msk              (0x1UL << RCC_SRDAMR_COMP12AMEN_Pos) /*!< 0x00004000 */

+#define RCC_SRDAMR_COMP12AMEN                  RCC_SRDAMR_COMP12AMEN_Msk

+#define RCC_SRDAMR_VREFAMEN_Pos                (15U)

+#define RCC_SRDAMR_VREFAMEN_Msk                (0x1UL << RCC_SRDAMR_VREFAMEN_Pos) /*!< 0x00008000 */

+#define RCC_SRDAMR_VREFAMEN                     RCC_SRDAMR_VREFAMEN_Msk

+#define RCC_SRDAMR_RTCAMEN_Pos                 (16U)

+#define RCC_SRDAMR_RTCAMEN_Msk                 (0x1UL << RCC_SRDAMR_RTCAMEN_Pos) /*!< 0x00010000 */

+#define RCC_SRDAMR_RTCAMEN                     RCC_SRDAMR_RTCAMEN_Msk

+#define RCC_SRDAMR_DTSAMEN_Pos                 (26U)

+#define RCC_SRDAMR_DTSAMEN_Msk                 (0x1UL << RCC_SRDAMR_DTSAMEN_Pos) /*!< 0x04000000 */

+#define RCC_SRDAMR_DTSAMEN                     RCC_SRDAMR_DTSAMEN_Msk

+#define RCC_SRDAMR_DFSDM2AMEN_Pos              (27U)

+#define RCC_SRDAMR_DFSDM2AMEN_Msk              (0x1UL << RCC_SRDAMR_DFSDM2AMEN_Pos) /*!< 0x20000000 */

+#define RCC_SRDAMR_DFSDM2AMEN                   RCC_SRDAMR_DFSDM2AMEN_Msk

+#define RCC_SRDAMR_BKPRAMAMEN_Pos              (28U)

+#define RCC_SRDAMR_BKPRAMAMEN_Msk              (0x1UL << RCC_SRDAMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */

+#define RCC_SRDAMR_BKPRAMAMEN                  RCC_SRDAMR_BKPRAMAMEN_Msk

+#define RCC_SRDAMR_SRDSRAMAMEN_Pos             (29U)

+#define RCC_SRDAMR_SRDSRAMAMEN_Msk             (0x1UL << RCC_SRDAMR_SRDSRAMAMEN_Pos) /*!< 0x20000000 */

+#define RCC_SRDAMR_SRDSRAMAMEN                  RCC_SRDAMR_SRDSRAMAMEN_Msk

+/********************  Bit definition for RCC_CKGAENR register  ********************/

+#define RCC_CKGAENR_AXICKG_Pos                 (0U)

+#define RCC_CKGAENR_AXICKG_Msk                 (0x1UL << RCC_CKGAENR_AXICKG_Pos) /*!< 0x00000001 */

+#define RCC_CKGAENR_AXICKG                      RCC_CKGAENR_AXICKG_Msk

+#define RCC_CKGAENR_AHBCKG_Pos                 (1U)

+#define RCC_CKGAENR_AHBCKG_Msk                 (0x1UL << RCC_CKGAENR_AHBCKG_Pos) /*!< 0x00000002 */

+#define RCC_CKGAENR_AHBCKG                     RCC_CKGAENR_AHBCKG_Msk

+#define RCC_CKGAENR_CPUCKG_Pos                 (2U)

+#define RCC_CKGAENR_CPUCKG_Msk                 (0x1UL << RCC_CKGAENR_CPUCKG_Pos) /*!< 0x00000004 */

+#define RCC_CKGAENR_CPUCKG                     RCC_CKGAENR_CPUCKG_Msk

+#define RCC_CKGAENR_SDMMCCKG_Pos               (3U)

+#define RCC_CKGAENR_SDMMCCKG_Msk               (0x1UL << RCC_CKGAENR_SDMMCCKG_Pos) /*!< 0x00000008 */

+#define RCC_CKGAENR_SDMMCCKG                    RCC_CKGAENR_SDMMCCKG_Msk

+#define RCC_CKGAENR_MDMACKG_Pos                (4U)

+#define RCC_CKGAENR_MDMACKG_Msk                (0x1UL << RCC_CKGAENR_MDMACKG_Pos) /*!< 0x00000010 */

+#define RCC_CKGAENR_MDMACKG                    RCC_CKGAENR_MDMACKG_Msk

+#define RCC_CKGAENR_DMA2DCKG_Pos               (5U)

+#define RCC_CKGAENR_DMA2DCKG_Msk               (0x1UL << RCC_CKGAENR_DMA2DCKG_Pos) /*!< 0x00000020 */

+#define RCC_CKGAENR_DMA2DCKG                    RCC_CKGAENR_DMA2DCKG_Msk

+#define RCC_CKGAENR_LTDCCKG_Pos                (6U)

+#define RCC_CKGAENR_LTDCCKG_Msk                (0x1UL << RCC_CKGAENR_LTDCCKG_Pos) /*!< 0x00000040 */

+#define RCC_CKGAENR_LTDCCKG                    RCC_CKGAENR_LTDCCKG_Msk

+#define RCC_CKGAENR_GFXMMUMCKG_Pos             (7U)

+#define RCC_CKGAENR_GFXMMUMCKG_Msk             (0x1UL << RCC_CKGAENR_GFXMMUMCKG_Pos) /*!< 0x00000080 */

+#define RCC_CKGAENR_GFXMMUMCKG                 RCC_CKGAENR_GFXMMUMCKG_Msk

+#define RCC_CKGAENR_AHB12CKG_Pos               (8U)

+#define RCC_CKGAENR_AHB12CKG_Msk               (0x1UL << RCC_CKGAENR_AHB12CKG_Pos) /*!< 0x00000100 */

+#define RCC_CKGAENR_AHB12CKG                   RCC_CKGAENR_AHB12CKG_Msk

+#define RCC_CKGAENR_AHB34CKG_Pos               (9U)

+#define RCC_CKGAENR_AHB34CKG_Msk               (0x1UL << RCC_CKGAENR_AHB34CKG_Pos) /*!< 0x00000200 */

+#define RCC_CKGAENR_AHB34CKG                   RCC_CKGAENR_AHB34CKG_Msk

+#define RCC_CKGAENR_FLIFTCKG_Pos               (10U)

+#define RCC_CKGAENR_FLIFTCKG_Msk               (0x1UL << RCC_CKGAENR_FLIFTCKG_Pos) /*!< 0x00000400 */

+#define RCC_CKGAENR_FLIFTCKG                   RCC_CKGAENR_FLIFTCKG_Msk

+#define RCC_CKGAENR_OCTOSPI2CKG_Pos            (11U)

+#define RCC_CKGAENR_OCTOSPI2CKG_Msk            (0x1UL << RCC_CKGAENR_OCTOSPI2CKG_Pos) /*!< 0x00000800 */

+#define RCC_CKGAENR_OCTOSPI2CKG                RCC_CKGAENR_OCTOSPI2CKG_Msk

+#define RCC_CKGAENR_FMCCKG_Pos                 (12U)

+#define RCC_CKGAENR_FMCCKG_Msk                 (0x1UL << RCC_CKGAENR_FMCCKG_Pos) /*!< 0x00001000 */

+#define RCC_CKGAENR_FMCCKG                     RCC_CKGAENR_FMCCKG_Msk

+#define RCC_CKGAENR_OCTOSPI1CKG_Pos            (13U)

+#define RCC_CKGAENR_OCTOSPI1CKG_Msk            (0x1UL << RCC_CKGAENR_OCTOSPI1CKG_Pos) /*!< 0x00002000 */

+#define RCC_CKGAENR_OCTOSPI1CKG                RCC_CKGAENR_OCTOSPI1CKG_Msk

+#define RCC_CKGAENR_AXIRAM1CKG_Pos             (14U)

+#define RCC_CKGAENR_AXIRAM1CKG_Msk             (0x1UL << RCC_CKGAENR_AXIRAM1CKG_Pos) /*!< 0x00004000 */

+#define RCC_CKGAENR_AXIRAM1CKG                 RCC_CKGAENR_AXIRAM1CKG_Msk

+#define RCC_CKGAENR_AXIRAM2CKG_Pos             (15U)

+#define RCC_CKGAENR_AXIRAM2CKG_Msk             (0x1UL << RCC_CKGAENR_AXIRAM2CKG_Pos) /*!< 0x00008000 */

+#define RCC_CKGAENR_AXIRAM2CKG                 RCC_CKGAENR_AXIRAM2CKG_Msk

+#define RCC_CKGAENR_AXIRAM3CKG_Pos             (16U)

+#define RCC_CKGAENR_AXIRAM3CKG_Msk             (0x1UL << RCC_CKGAENR_AXIRAM3CKG_Pos) /*!< 0x00010000 */

+#define RCC_CKGAENR_AXIRAM3CKG                 RCC_CKGAENR_AXIRAM3CKG_Msk

+#define RCC_CKGAENR_GFXMMUSCKG_Pos             (17U)

+#define RCC_CKGAENR_GFXMMUSCKG_Msk             (0x1UL << RCC_CKGAENR_GFXMMUSCKG_Pos) /*!< 0x00020000 */

+#define RCC_CKGAENR_GFXMMUSCKG                 RCC_CKGAENR_GFXMMUSCKG_Msk

+#define RCC_CKGAENR_ECCRAMCKG_Pos              (29U)

+#define RCC_CKGAENR_ECCRAMCKG_Msk              (0x1UL << RCC_CKGAENR_ECCRAMCKG_Pos) /*!< 0x20000000 */

+#define RCC_CKGAENR_ECCRAMCKG                  RCC_CKGAENR_ECCRAMCKG_Msk

+#define RCC_CKGAENR_EXTICKG_Pos                (30U)

+#define RCC_CKGAENR_EXTICKG_Msk                (0x1UL << RCC_CKGAENR_EXTICKG_Pos) /*!< 0x40000000 */

+#define RCC_CKGAENR_EXTICKG                    RCC_CKGAENR_EXTICKG_Msk

+#define RCC_CKGAENR_JTAGCKG_Pos                (31U)

+#define RCC_CKGAENR_JTAGCKG_Msk                (0x1UL << RCC_CKGAENR_JTAGCKG_Pos) /*!< 0x80000008 */

+#define RCC_CKGAENR_JTAGCKG                    RCC_CKGAENR_JTAGCKG_Msk

+/********************  Bit definition for RCC_AHB3LPENR register  **************/

+#define RCC_AHB3LPENR_MDMALPEN_Pos             (0U)

+#define RCC_AHB3LPENR_MDMALPEN_Msk             (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos)         /*!< 0x00000001 */

+#define RCC_AHB3LPENR_MDMALPEN                 RCC_AHB3LPENR_MDMALPEN_Msk

+#define RCC_AHB3LPENR_DMA2DLPEN_Pos            (4U)

+#define RCC_AHB3LPENR_DMA2DLPEN_Msk            (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos)        /*!< 0x00000010 */

+#define RCC_AHB3LPENR_DMA2DLPEN                RCC_AHB3LPENR_DMA2DLPEN_Msk

+#define RCC_AHB3LPENR_JPGDECLPEN_Pos           (5U)

+#define RCC_AHB3LPENR_JPGDECLPEN_Msk           (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos)       /*!< 0x00000020 */

+#define RCC_AHB3LPENR_JPGDECLPEN               RCC_AHB3LPENR_JPGDECLPEN_Msk

+#define RCC_AHB3LPENR_FLASHLPEN_Pos            (8U)

+#define RCC_AHB3LPENR_FLASHLPEN_Msk            (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos)        /*!< 0x00000100 */

+#define RCC_AHB3LPENR_FLASHLPEN                RCC_AHB3LPENR_FLASHLPEN_Msk

+#define RCC_AHB3LPENR_FMCLPEN_Pos              (12U)

+#define RCC_AHB3LPENR_FMCLPEN_Msk              (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos)          /*!< 0x00001000 */

+#define RCC_AHB3LPENR_FMCLPEN                  RCC_AHB3LPENR_FMCLPEN_Msk

+#define RCC_AHB3LPENR_OSPI1LPEN_Pos            (14U)

+#define RCC_AHB3LPENR_OSPI1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_OSPI1LPEN_Pos)        /*!< 0x00004000 */

+#define RCC_AHB3LPENR_OSPI1LPEN                RCC_AHB3LPENR_OSPI1LPEN_Msk

+#define RCC_AHB3LPENR_SDMMC1LPEN_Pos           (16U)

+#define RCC_AHB3LPENR_SDMMC1LPEN_Msk           (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos)       /*!< 0x00010000 */

+#define RCC_AHB3LPENR_SDMMC1LPEN               RCC_AHB3LPENR_SDMMC1LPEN_Msk

+#define RCC_AHB3LPENR_OSPI2LPEN_Pos            (19U)

+#define RCC_AHB3LPENR_OSPI2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_OSPI2LPEN_Pos)        /*!< 0x00080000 */

+#define RCC_AHB3LPENR_OSPI2LPEN                RCC_AHB3LPENR_OSPI2LPEN_Msk

+#define RCC_AHB3LPENR_IOMNGRLPEN_Pos           (21U)

+#define RCC_AHB3LPENR_IOMNGRLPEN_Msk           (0x1UL << RCC_AHB3LPENR_IOMNGRLPEN_Pos)       /*!< 0x00200000 */

+#define RCC_AHB3LPENR_IOMNGRLPEN               RCC_AHB3LPENR_IOMNGRLPEN_Msk

+#define RCC_AHB3LPENR_OTFDEC1LPEN_Pos          (22U)

+#define RCC_AHB3LPENR_OTFDEC1LPEN_Msk          (0x1UL << RCC_AHB3LPENR_OTFDEC1LPEN_Pos)      /*!< 0x00400000 */

+#define RCC_AHB3LPENR_OTFDEC1LPEN              RCC_AHB3LPENR_OTFDEC1LPEN_Msk

+#define RCC_AHB3LPENR_OTFDEC2LPEN_Pos          (23U)

+#define RCC_AHB3LPENR_OTFDEC2LPEN_Msk          (0x1UL << RCC_AHB3LPENR_OTFDEC2LPEN_Pos)      /*!< 0x00800000 */

+#define RCC_AHB3LPENR_OTFDEC2LPEN              RCC_AHB3LPENR_OTFDEC2LPEN_Msk

+#define RCC_AHB3LPENR_GFXMMULPEN_Pos           (24U)

+#define RCC_AHB3LPENR_GFXMMULPEN_Msk           (0x1UL << RCC_AHB3LPENR_GFXMMULPEN_Pos)       /*!< 0x01000000 */

+#define RCC_AHB3LPENR_GFXMMULPEN               RCC_AHB3LPENR_GFXMMULPEN_Msk

+#define RCC_AHB3LPENR_AXISRAM2LPEN_Pos         (26U)

+#define RCC_AHB3LPENR_AXISRAM2LPEN_Msk         (0x1UL << RCC_AHB3LPENR_AXISRAM2LPEN_Pos)     /*!< 0x02000000 */

+#define RCC_AHB3LPENR_AXISRAM2LPEN             RCC_AHB3LPENR_AXISRAM2LPEN_Msk

+#define RCC_AHB3LPENR_AXISRAM3LPEN_Pos         (27U)

+#define RCC_AHB3LPENR_AXISRAM3LPEN_Msk         (0x1UL << RCC_AHB3LPENR_AXISRAM3LPEN_Pos)     /*!< 0x04000000 */

+#define RCC_AHB3LPENR_AXISRAM3LPEN             RCC_AHB3LPENR_AXISRAM3LPEN_Msk

+#define RCC_AHB3LPENR_DTCM1LPEN_Pos            (28U)

+#define RCC_AHB3LPENR_DTCM1LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos)        /*!< 0x10000000 */

+#define RCC_AHB3LPENR_DTCM1LPEN                RCC_AHB3LPENR_DTCM1LPEN_Msk

+#define RCC_AHB3LPENR_DTCM2LPEN_Pos            (29U)

+#define RCC_AHB3LPENR_DTCM2LPEN_Msk            (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos)        /*!< 0x20000000 */

+#define RCC_AHB3LPENR_DTCM2LPEN                RCC_AHB3LPENR_DTCM2LPEN_Msk

+#define RCC_AHB3LPENR_ITCMLPEN_Pos             (30U)

+#define RCC_AHB3LPENR_ITCMLPEN_Msk             (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos)         /*!< 0x40000000 */

+#define RCC_AHB3LPENR_ITCMLPEN                 RCC_AHB3LPENR_ITCMLPEN_Msk

+#define RCC_AHB3LPENR_AXISRAM1LPEN_Pos         (31U)

+#define RCC_AHB3LPENR_AXISRAM1LPEN_Msk         (0x1UL << RCC_AHB3LPENR_AXISRAM1LPEN_Pos)      /*!< 0x80000000 */

+#define RCC_AHB3LPENR_AXISRAM1LPEN             RCC_AHB3LPENR_AXISRAM1LPEN_Msk

+

+

+/* Legacy define */

+#define RCC_AHB3LPENR_AXISRAMLPEN_Pos          RCC_AHB3LPENR_AXISRAM1LPEN_Pos

+#define RCC_AHB3LPENR_AXISRAMLPEN_Msk          RCC_AHB3LPENR_AXISRAM1LPEN_Msk

+#define RCC_AHB3LPENR_AXISRAMLPEN              RCC_AHB3LPENR_AXISRAM1LPEN

+/********************  Bit definition for RCC_AHB1LPENR register  ***************/

+#define RCC_AHB1LPENR_DMA1LPEN_Pos             (0U)

+#define RCC_AHB1LPENR_DMA1LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB1LPENR_DMA1LPEN                 RCC_AHB1LPENR_DMA1LPEN_Msk

+#define RCC_AHB1LPENR_DMA2LPEN_Pos             (1U)

+#define RCC_AHB1LPENR_DMA2LPEN_Msk             (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */

+#define RCC_AHB1LPENR_DMA2LPEN                 RCC_AHB1LPENR_DMA2LPEN_Msk

+#define RCC_AHB1LPENR_ADC12LPEN_Pos            (5U)

+#define RCC_AHB1LPENR_ADC12LPEN_Msk            (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB1LPENR_ADC12LPEN                RCC_AHB1LPENR_ADC12LPEN_Msk

+#define RCC_AHB1LPENR_CRCLPEN_Pos              (9U)

+#define RCC_AHB1LPENR_CRCLPEN_Msk              (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00008000 */

+#define RCC_AHB1LPENR_CRCLPEN                   RCC_AHB1LPENR_CRCLPEN_Msk

+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos        (25U)

+#define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk        (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */

+#define RCC_AHB1LPENR_USB1OTGHSLPEN            RCC_AHB1LPENR_USB1OTGHSLPEN_Msk

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos    (26U)

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk    (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */

+#define RCC_AHB1LPENR_USB1OTGHSULPILPEN        RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk

+

+/********************  Bit definition for RCC_AHB2LPENR register  ***************/

+#define RCC_AHB2LPENR_DCMI_PSSILPEN_Pos        (0U)

+#define RCC_AHB2LPENR_DCMI_PSSILPEN_Msk        (0x1UL << RCC_AHB2LPENR_DCMI_PSSILPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB2LPENR_DCMI_PSSILPEN            RCC_AHB2LPENR_DCMI_PSSILPEN_Msk

+#define RCC_AHB2LPENR_CRYPLPEN_Pos             (4U)

+#define RCC_AHB2LPENR_CRYPLPEN_Msk             (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */

+#define RCC_AHB2LPENR_CRYPLPEN                 RCC_AHB2LPENR_CRYPLPEN_Msk

+#define RCC_AHB2LPENR_HASHLPEN_Pos             (5U)

+#define RCC_AHB2LPENR_HASHLPEN_Msk             (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB2LPENR_HASHLPEN                 RCC_AHB2LPENR_HASHLPEN_Msk

+#define RCC_AHB2LPENR_RNGLPEN_Pos              (6U)

+#define RCC_AHB2LPENR_RNGLPEN_Msk              (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */

+#define RCC_AHB2LPENR_RNGLPEN                  RCC_AHB2LPENR_RNGLPEN_Msk

+#define RCC_AHB2LPENR_SDMMC2LPEN_Pos           (9U)

+#define RCC_AHB2LPENR_SDMMC2LPEN_Msk           (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */

+#define RCC_AHB2LPENR_SDMMC2LPEN               RCC_AHB2LPENR_SDMMC2LPEN_Msk

+#define RCC_AHB2LPENR_BDMA1LPEN_Pos            (11U)

+#define RCC_AHB2LPENR_BDMA1LPEN_Msk            (0x1UL << RCC_AHB2LPENR_BDMA1LPEN_Pos)   /*!< 0x00000800 */

+#define RCC_AHB2LPENR_BDMA1LPEN                RCC_AHB2LPENR_BDMA1LPEN_Msk

+#define RCC_AHB2LPENR_AHBSRAM1LPEN_Pos         (29U)

+#define RCC_AHB2LPENR_AHBSRAM1LPEN_Msk         (0x1UL << RCC_AHB2LPENR_AHBSRAM1LPEN_Pos) /*!< 0x20000000 */

+#define RCC_AHB2LPENR_AHBSRAM1LPEN             RCC_AHB2LPENR_AHBSRAM1LPEN_Msk

+#define RCC_AHB2LPENR_AHBSRAM2LPEN_Pos         (30U)

+#define RCC_AHB2LPENR_AHBSRAM2LPEN_Msk         (0x1UL << RCC_AHB2LPENR_AHBSRAM2LPEN_Pos) /*!< 0x40000000 */

+#define RCC_AHB2LPENR_AHBSRAM2LPEN             RCC_AHB2LPENR_AHBSRAM2LPEN_Msk

+

+/* Legacy define */

+#define RCC_AHB2LPENR_DFSDMDMALPEN_Pos         RCC_AHB2LPENR_BDMA1LPEN_Pos

+#define RCC_AHB2LPENR_DFSDMDMALPEN_Msk         RCC_AHB2LPENR_BDMA1LPEN_Msk

+#define RCC_AHB2LPENR_DFSDMDMALPEN             RCC_AHB2LPENR_BDMA1LPEN

+#define RCC_AHB2LPENR_DCMILPEN_Pos             RCC_AHB2LPENR_DCMI_PSSILPEN_Pos

+#define RCC_AHB2LPENR_DCMILPEN_Msk             RCC_AHB2LPENR_DCMI_PSSILPEN_Msk

+#define RCC_AHB2LPENR_DCMILPEN                 RCC_AHB2LPENR_DCMI_PSSILPEN

+

+/********************  Bit definition for RCC_AHB4LPENR register  ******************/

+#define RCC_AHB4LPENR_GPIOALPEN_Pos            (0U)

+#define RCC_AHB4LPENR_GPIOALPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */

+#define RCC_AHB4LPENR_GPIOALPEN                RCC_AHB4LPENR_GPIOALPEN_Msk

+#define RCC_AHB4LPENR_GPIOBLPEN_Pos            (1U)

+#define RCC_AHB4LPENR_GPIOBLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */

+#define RCC_AHB4LPENR_GPIOBLPEN                RCC_AHB4LPENR_GPIOBLPEN_Msk

+#define RCC_AHB4LPENR_GPIOCLPEN_Pos            (2U)

+#define RCC_AHB4LPENR_GPIOCLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */

+#define RCC_AHB4LPENR_GPIOCLPEN                RCC_AHB4LPENR_GPIOCLPEN_Msk

+#define RCC_AHB4LPENR_GPIODLPEN_Pos            (3U)

+#define RCC_AHB4LPENR_GPIODLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */

+#define RCC_AHB4LPENR_GPIODLPEN                RCC_AHB4LPENR_GPIODLPEN_Msk

+#define RCC_AHB4LPENR_GPIOELPEN_Pos            (4U)

+#define RCC_AHB4LPENR_GPIOELPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */

+#define RCC_AHB4LPENR_GPIOELPEN                RCC_AHB4LPENR_GPIOELPEN_Msk

+#define RCC_AHB4LPENR_GPIOFLPEN_Pos            (5U)

+#define RCC_AHB4LPENR_GPIOFLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */

+#define RCC_AHB4LPENR_GPIOFLPEN                RCC_AHB4LPENR_GPIOFLPEN_Msk

+#define RCC_AHB4LPENR_GPIOGLPEN_Pos            (6U)

+#define RCC_AHB4LPENR_GPIOGLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */

+#define RCC_AHB4LPENR_GPIOGLPEN                RCC_AHB4LPENR_GPIOGLPEN_Msk

+#define RCC_AHB4LPENR_GPIOHLPEN_Pos            (7U)

+#define RCC_AHB4LPENR_GPIOHLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */

+#define RCC_AHB4LPENR_GPIOHLPEN                RCC_AHB4LPENR_GPIOHLPEN_Msk

+#define RCC_AHB4LPENR_GPIOILPEN_Pos            (8U)

+#define RCC_AHB4LPENR_GPIOILPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */

+#define RCC_AHB4LPENR_GPIOILPEN                RCC_AHB4LPENR_GPIOILPEN_Msk

+#define RCC_AHB4LPENR_GPIOJLPEN_Pos            (9U)

+#define RCC_AHB4LPENR_GPIOJLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */

+#define RCC_AHB4LPENR_GPIOJLPEN                RCC_AHB4LPENR_GPIOJLPEN_Msk

+#define RCC_AHB4LPENR_GPIOKLPEN_Pos            (10U)

+#define RCC_AHB4LPENR_GPIOKLPEN_Msk            (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */

+#define RCC_AHB4LPENR_GPIOKLPEN                RCC_AHB4LPENR_GPIOKLPEN_Msk

+#define RCC_AHB4LPENR_BDMA2LPEN_Pos             (21U)

+#define RCC_AHB4LPENR_BDMA2LPEN_Msk             (0x1UL << RCC_AHB4LPENR_BDMA2LPEN_Pos) /*!< 0x00200000 */

+#define RCC_AHB4LPENR_BDMA2LPEN                 RCC_AHB4LPENR_BDMA2LPEN_Msk

+#define RCC_AHB4LPENR_BKPRAMLPEN_Pos           (28U)

+#define RCC_AHB4LPENR_BKPRAMLPEN_Msk           (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */

+#define RCC_AHB4LPENR_BKPRAMLPEN               RCC_AHB4LPENR_BKPRAMLPEN_Msk

+#define RCC_AHB4LPENR_SRDSRAMLPEN_Pos          (29U)

+#define RCC_AHB4LPENR_SRDSRAMLPEN_Msk          (0x1UL << RCC_AHB4LPENR_SRDSRAMLPEN_Pos) /*!< 0x20000000 */

+#define RCC_AHB4LPENR_SRDSRAMLPEN              RCC_AHB4LPENR_SRDSRAMLPEN_Msk

+

+/********************  Bit definition for RCC_APB3LPENR register  ******************/

+#define RCC_APB3LPENR_LTDCLPEN_Pos             (3U)

+#define RCC_APB3LPENR_LTDCLPEN_Msk             (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB3LPENR_LTDCLPEN                 RCC_APB3LPENR_LTDCLPEN_Msk

+#define RCC_APB3LPENR_WWDGLPEN_Pos             (6U)

+#define RCC_APB3LPENR_WWDGLPEN_Msk             (0x1UL << RCC_APB3LPENR_WWDGLPEN_Pos)  /*!< 0x00000040 */

+#define RCC_APB3LPENR_WWDGLPEN                 RCC_APB3LPENR_WWDGLPEN_Msk

+

+/* Legacy define */

+#define RCC_APB3LPENR_WWDG1LPEN_Pos            RCC_APB3LPENR_WWDGLPEN_Pos

+#define RCC_APB3LPENR_WWDG1LPEN_Msk            RCC_APB3LPENR_WWDGLPEN_Msk

+#define RCC_APB3LPENR_WWDG1LPEN                RCC_APB3LPENR_WWDGLPEN

+/********************  Bit definition for RCC_APB1LLPENR register  ******************/

+

+#define RCC_APB1LLPENR_TIM2LPEN_Pos            (0U)

+#define RCC_APB1LLPENR_TIM2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */

+#define RCC_APB1LLPENR_TIM2LPEN                RCC_APB1LLPENR_TIM2LPEN_Msk

+#define RCC_APB1LLPENR_TIM3LPEN_Pos            (1U)

+#define RCC_APB1LLPENR_TIM3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1LLPENR_TIM3LPEN                RCC_APB1LLPENR_TIM3LPEN_Msk

+#define RCC_APB1LLPENR_TIM4LPEN_Pos            (2U)

+#define RCC_APB1LLPENR_TIM4LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1LLPENR_TIM4LPEN                RCC_APB1LLPENR_TIM4LPEN_Msk

+#define RCC_APB1LLPENR_TIM5LPEN_Pos            (3U)

+#define RCC_APB1LLPENR_TIM5LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB1LLPENR_TIM5LPEN                RCC_APB1LLPENR_TIM5LPEN_Msk

+#define RCC_APB1LLPENR_TIM6LPEN_Pos            (4U)

+#define RCC_APB1LLPENR_TIM6LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1LLPENR_TIM6LPEN                RCC_APB1LLPENR_TIM6LPEN_Msk

+#define RCC_APB1LLPENR_TIM7LPEN_Pos            (5U)

+#define RCC_APB1LLPENR_TIM7LPEN_Msk            (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1LLPENR_TIM7LPEN                RCC_APB1LLPENR_TIM7LPEN_Msk

+#define RCC_APB1LLPENR_TIM12LPEN_Pos           (6U)

+#define RCC_APB1LLPENR_TIM12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */

+#define RCC_APB1LLPENR_TIM12LPEN               RCC_APB1LLPENR_TIM12LPEN_Msk

+#define RCC_APB1LLPENR_TIM13LPEN_Pos           (7U)

+#define RCC_APB1LLPENR_TIM13LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB1LLPENR_TIM13LPEN               RCC_APB1LLPENR_TIM13LPEN_Msk

+#define RCC_APB1LLPENR_TIM14LPEN_Pos           (8U)

+#define RCC_APB1LLPENR_TIM14LPEN_Msk           (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1LLPENR_TIM14LPEN               RCC_APB1LLPENR_TIM14LPEN_Msk

+#define RCC_APB1LLPENR_LPTIM1LPEN_Pos          (9U)

+#define RCC_APB1LLPENR_LPTIM1LPEN_Msk          (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */

+#define RCC_APB1LLPENR_LPTIM1LPEN              RCC_APB1LLPENR_LPTIM1LPEN_Msk

+

+

+#define RCC_APB1LLPENR_SPI2LPEN_Pos            (14U)

+#define RCC_APB1LLPENR_SPI2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */

+#define RCC_APB1LLPENR_SPI2LPEN                RCC_APB1LLPENR_SPI2LPEN_Msk

+#define RCC_APB1LLPENR_SPI3LPEN_Pos            (15U)

+#define RCC_APB1LLPENR_SPI3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */

+#define RCC_APB1LLPENR_SPI3LPEN                RCC_APB1LLPENR_SPI3LPEN_Msk

+#define RCC_APB1LLPENR_SPDIFRXLPEN_Pos         (16U)

+#define RCC_APB1LLPENR_SPDIFRXLPEN_Msk         (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB1LLPENR_SPDIFRXLPEN             RCC_APB1LLPENR_SPDIFRXLPEN_Msk

+#define RCC_APB1LLPENR_USART2LPEN_Pos          (17U)

+#define RCC_APB1LLPENR_USART2LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */

+#define RCC_APB1LLPENR_USART2LPEN              RCC_APB1LLPENR_USART2LPEN_Msk

+#define RCC_APB1LLPENR_USART3LPEN_Pos          (18U)

+#define RCC_APB1LLPENR_USART3LPEN_Msk          (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */

+#define RCC_APB1LLPENR_USART3LPEN              RCC_APB1LLPENR_USART3LPEN_Msk

+#define RCC_APB1LLPENR_UART4LPEN_Pos           (19U)

+#define RCC_APB1LLPENR_UART4LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */

+#define RCC_APB1LLPENR_UART4LPEN               RCC_APB1LLPENR_UART4LPEN_Msk

+#define RCC_APB1LLPENR_UART5LPEN_Pos           (20U)

+#define RCC_APB1LLPENR_UART5LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */

+#define RCC_APB1LLPENR_UART5LPEN               RCC_APB1LLPENR_UART5LPEN_Msk

+#define RCC_APB1LLPENR_I2C1LPEN_Pos            (21U)

+#define RCC_APB1LLPENR_I2C1LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */

+#define RCC_APB1LLPENR_I2C1LPEN                RCC_APB1LLPENR_I2C1LPEN_Msk

+#define RCC_APB1LLPENR_I2C2LPEN_Pos            (22U)

+#define RCC_APB1LLPENR_I2C2LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */

+#define RCC_APB1LLPENR_I2C2LPEN                RCC_APB1LLPENR_I2C2LPEN_Msk

+#define RCC_APB1LLPENR_I2C3LPEN_Pos            (23U)

+#define RCC_APB1LLPENR_I2C3LPEN_Msk            (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */

+#define RCC_APB1LLPENR_I2C3LPEN                RCC_APB1LLPENR_I2C3LPEN_Msk

+#define RCC_APB1LLPENR_CECLPEN_Pos             (27U)

+#define RCC_APB1LLPENR_CECLPEN_Msk             (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */

+#define RCC_APB1LLPENR_CECLPEN                 RCC_APB1LLPENR_CECLPEN_Msk

+#define RCC_APB1LLPENR_DAC12LPEN_Pos           (29U)

+#define RCC_APB1LLPENR_DAC12LPEN_Msk           (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */

+#define RCC_APB1LLPENR_DAC12LPEN               RCC_APB1LLPENR_DAC12LPEN_Msk

+#define RCC_APB1LLPENR_UART7LPEN_Pos           (30U)

+#define RCC_APB1LLPENR_UART7LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */

+#define RCC_APB1LLPENR_UART7LPEN               RCC_APB1LLPENR_UART7LPEN_Msk

+#define RCC_APB1LLPENR_UART8LPEN_Pos           (31U)

+#define RCC_APB1LLPENR_UART8LPEN_Msk           (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */

+#define RCC_APB1LLPENR_UART8LPEN               RCC_APB1LLPENR_UART8LPEN_Msk

+

+/* Legacy define */

+#define RCC_APB1LLPENR_HDMICECEN_Pos           RCC_APB1LLPENR_CECLPEN_Pos

+#define RCC_APB1LLPENR_HDMICECEN_Msk           RCC_APB1LLPENR_CECLPEN_Msk

+#define RCC_APB1LLPENR_HDMICECEN               RCC_APB1LLPENR_CECLPEN

+/********************  Bit definition for RCC_APB1HLPENR register  ******************/

+#define RCC_APB1HLPENR_CRSLPEN_Pos             (1U)

+#define RCC_APB1HLPENR_CRSLPEN_Msk             (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB1HLPENR_CRSLPEN                 RCC_APB1HLPENR_CRSLPEN_Msk

+#define RCC_APB1HLPENR_SWPMILPEN_Pos           (2U)

+#define RCC_APB1HLPENR_SWPMILPEN_Msk           (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */

+#define RCC_APB1HLPENR_SWPMILPEN               RCC_APB1HLPENR_SWPMILPEN_Msk

+#define RCC_APB1HLPENR_OPAMPLPEN_Pos           (4U)

+#define RCC_APB1HLPENR_OPAMPLPEN_Msk           (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB1HLPENR_OPAMPLPEN               RCC_APB1HLPENR_OPAMPLPEN_Msk

+#define RCC_APB1HLPENR_MDIOSLPEN_Pos           (5U)

+#define RCC_APB1HLPENR_MDIOSLPEN_Msk           (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB1HLPENR_MDIOSLPEN               RCC_APB1HLPENR_MDIOSLPEN_Msk

+#define RCC_APB1HLPENR_FDCANLPEN_Pos           (8U)

+#define RCC_APB1HLPENR_FDCANLPEN_Msk           (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */

+#define RCC_APB1HLPENR_FDCANLPEN               RCC_APB1HLPENR_FDCANLPEN_Msk

+

+/********************  Bit definition for RCC_APB2LPENR register  ******************/

+#define RCC_APB2LPENR_TIM1LPEN_Pos             (0U)

+#define RCC_APB2LPENR_TIM1LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */

+#define RCC_APB2LPENR_TIM1LPEN                 RCC_APB2LPENR_TIM1LPEN_Msk

+#define RCC_APB2LPENR_TIM8LPEN_Pos             (1U)

+#define RCC_APB2LPENR_TIM8LPEN_Msk             (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB2LPENR_TIM8LPEN                 RCC_APB2LPENR_TIM8LPEN_Msk

+#define RCC_APB2LPENR_USART1LPEN_Pos           (4U)

+#define RCC_APB2LPENR_USART1LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */

+#define RCC_APB2LPENR_USART1LPEN               RCC_APB2LPENR_USART1LPEN_Msk

+#define RCC_APB2LPENR_USART6LPEN_Pos           (5U)

+#define RCC_APB2LPENR_USART6LPEN_Msk           (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB2LPENR_USART6LPEN               RCC_APB2LPENR_USART6LPEN_Msk

+#define RCC_APB2LPENR_UART9LPEN_Pos            (6U)

+#define RCC_APB2LPENR_UART9LPEN_Msk            (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos) /*!< 0x00000040 */

+#define RCC_APB2LPENR_UART9LPEN                 RCC_APB2LPENR_UART9LPEN_Msk

+#define RCC_APB2LPENR_USART10LPEN_Pos          (7U)

+#define RCC_APB2LPENR_USART10LPEN_Msk          (0x1UL << RCC_APB2LPENR_USART10LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB2LPENR_USART10LPEN               RCC_APB2LPENR_USART10LPEN_Msk

+#define RCC_APB2LPENR_SPI1LPEN_Pos             (12U)

+#define RCC_APB2LPENR_SPI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */

+#define RCC_APB2LPENR_SPI1LPEN                 RCC_APB2LPENR_SPI1LPEN_Msk

+#define RCC_APB2LPENR_SPI4LPEN_Pos             (13U)

+#define RCC_APB2LPENR_SPI4LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */

+#define RCC_APB2LPENR_SPI4LPEN                 RCC_APB2LPENR_SPI4LPEN_Msk

+#define RCC_APB2LPENR_TIM15LPEN_Pos            (16U)

+#define RCC_APB2LPENR_TIM15LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB2LPENR_TIM15LPEN                RCC_APB2LPENR_TIM15LPEN_Msk

+#define RCC_APB2LPENR_TIM16LPEN_Pos            (17U)

+#define RCC_APB2LPENR_TIM16LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */

+#define RCC_APB2LPENR_TIM16LPEN                RCC_APB2LPENR_TIM16LPEN_Msk

+#define RCC_APB2LPENR_TIM17LPEN_Pos            (18U)

+#define RCC_APB2LPENR_TIM17LPEN_Msk            (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */

+#define RCC_APB2LPENR_TIM17LPEN                RCC_APB2LPENR_TIM17LPEN_Msk

+#define RCC_APB2LPENR_SPI5LPEN_Pos             (20U)

+#define RCC_APB2LPENR_SPI5LPEN_Msk             (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */

+#define RCC_APB2LPENR_SPI5LPEN                 RCC_APB2LPENR_SPI5LPEN_Msk

+#define RCC_APB2LPENR_SAI1LPEN_Pos             (22U)

+#define RCC_APB2LPENR_SAI1LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */

+#define RCC_APB2LPENR_SAI1LPEN                 RCC_APB2LPENR_SAI1LPEN_Msk

+#define RCC_APB2LPENR_SAI2LPEN_Pos             (23U)

+#define RCC_APB2LPENR_SAI2LPEN_Msk             (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */

+#define RCC_APB2LPENR_SAI2LPEN                 RCC_APB2LPENR_SAI2LPEN_Msk

+#define RCC_APB2LPENR_DFSDM1LPEN_Pos           (30U)

+#define RCC_APB2LPENR_DFSDM1LPEN_Msk           (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x40000000 */

+#define RCC_APB2LPENR_DFSDM1LPEN               RCC_APB2LPENR_DFSDM1LPEN_Msk

+

+/********************  Bit definition for RCC_APB4LPENR register  ******************/

+#define RCC_APB4LPENR_SYSCFGLPEN_Pos           (1U)

+#define RCC_APB4LPENR_SYSCFGLPEN_Msk           (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */

+#define RCC_APB4LPENR_SYSCFGLPEN               RCC_APB4LPENR_SYSCFGLPEN_Msk

+#define RCC_APB4LPENR_LPUART1LPEN_Pos          (3U)

+#define RCC_APB4LPENR_LPUART1LPEN_Msk          (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */

+#define RCC_APB4LPENR_LPUART1LPEN              RCC_APB4LPENR_LPUART1LPEN_Msk

+#define RCC_APB4LPENR_SPI6LPEN_Pos             (5U)

+#define RCC_APB4LPENR_SPI6LPEN_Msk             (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */

+#define RCC_APB4LPENR_SPI6LPEN                 RCC_APB4LPENR_SPI6LPEN_Msk

+#define RCC_APB4LPENR_I2C4LPEN_Pos             (7U)

+#define RCC_APB4LPENR_I2C4LPEN_Msk             (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */

+#define RCC_APB4LPENR_I2C4LPEN                 RCC_APB4LPENR_I2C4LPEN_Msk

+#define RCC_APB4LPENR_LPTIM2LPEN_Pos           (9U)

+#define RCC_APB4LPENR_LPTIM2LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */

+#define RCC_APB4LPENR_LPTIM2LPEN               RCC_APB4LPENR_LPTIM2LPEN_Msk

+#define RCC_APB4LPENR_LPTIM3LPEN_Pos           (10U)

+#define RCC_APB4LPENR_LPTIM3LPEN_Msk           (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */

+#define RCC_APB4LPENR_LPTIM3LPEN               RCC_APB4LPENR_LPTIM3LPEN_Msk

+#define RCC_APB4LPENR_DAC2LPEN_Pos             (13U)

+#define RCC_APB4LPENR_DAC2LPEN_Msk             (0x1UL << RCC_APB4LPENR_DAC2LPEN_Pos) /*!< 0x00002000 */

+#define RCC_APB4LPENR_DAC2LPEN                 RCC_APB4LPENR_DAC2LPEN_Msk

+#define RCC_APB4LPENR_COMP12LPEN_Pos           (14U)

+#define RCC_APB4LPENR_COMP12LPEN_Msk           (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */

+#define RCC_APB4LPENR_COMP12LPEN               RCC_APB4LPENR_COMP12LPEN_Msk

+#define RCC_APB4LPENR_VREFLPEN_Pos             (15U)

+#define RCC_APB4LPENR_VREFLPEN_Msk             (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */

+#define RCC_APB4LPENR_VREFLPEN                 RCC_APB4LPENR_VREFLPEN_Msk

+#define RCC_APB4LPENR_RTCAPBLPEN_Pos           (16U)

+#define RCC_APB4LPENR_RTCAPBLPEN_Msk           (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */

+#define RCC_APB4LPENR_RTCAPBLPEN               RCC_APB4LPENR_RTCAPBLPEN_Msk

+

+#define RCC_APB4LPENR_DTSLPEN_Pos              (26U)

+#define RCC_APB4LPENR_DTSLPEN_Msk              (0x1UL << RCC_APB4LPENR_DTSLPEN_Pos) /*!< 0x04000000 */

+#define RCC_APB4LPENR_DTSLPEN                  RCC_APB4LPENR_DTSLPEN_Msk

+#define RCC_APB4LPENR_DFSDM2LPEN_Pos           (27U)

+#define RCC_APB4LPENR_DFSDM2LPEN_Msk           (0x1UL << RCC_APB4LPENR_DFSDM2LPEN_Pos) /*!< 0x08000000 */

+#define RCC_APB4LPENR_DFSDM2LPEN                RCC_APB4LPENR_DFSDM2LPEN_Msk

+

+/********************  Bit definition for RCC_RSR register  *******************/

+#define RCC_RSR_RMVF_Pos                       (16U)

+#define RCC_RSR_RMVF_Msk                       (0x1UL << RCC_RSR_RMVF_Pos)     /*!< 0x00010000 */

+#define RCC_RSR_RMVF                           RCC_RSR_RMVF_Msk

+#define RCC_RSR_CDRSTF_Pos                     (19U)

+#define RCC_RSR_CDRSTF_Msk                     (0x1UL << RCC_RSR_CDRSTF_Pos)   /*!< 0x00080000 */

+#define RCC_RSR_CDRSTF                         RCC_RSR_CDRSTF_Msk

+#define RCC_RSR_BORRSTF_Pos                    (21U)

+#define RCC_RSR_BORRSTF_Msk                    (0x1UL << RCC_RSR_BORRSTF_Pos)  /*!< 0x00200000 */

+#define RCC_RSR_BORRSTF                        RCC_RSR_BORRSTF_Msk

+#define RCC_RSR_PINRSTF_Pos                    (22U)

+#define RCC_RSR_PINRSTF_Msk                    (0x1UL << RCC_RSR_PINRSTF_Pos)  /*!< 0x00400000 */

+#define RCC_RSR_PINRSTF                        RCC_RSR_PINRSTF_Msk

+#define RCC_RSR_PORRSTF_Pos                    (23U)

+#define RCC_RSR_PORRSTF_Msk                    (0x1UL << RCC_RSR_PORRSTF_Pos)  /*!< 0x00800000 */

+#define RCC_RSR_PORRSTF                        RCC_RSR_PORRSTF_Msk

+#define RCC_RSR_SFTRSTF_Pos                    (24U)

+#define RCC_RSR_SFTRSTF_Msk                    (0x1UL << RCC_RSR_SFTRSTF_Pos)  /*!< 0x01000000 */

+#define RCC_RSR_SFTRSTF                        RCC_RSR_SFTRSTF_Msk

+#define RCC_RSR_IWDGRSTF_Pos                   (26U)

+#define RCC_RSR_IWDGRSTF_Msk                   (0x1UL << RCC_RSR_IWDGRSTF_Pos) /*!< 0x04000000 */

+#define RCC_RSR_IWDGRSTF                       RCC_RSR_IWDGRSTF_Msk

+#define RCC_RSR_WWDGRSTF_Pos                   (28U)

+#define RCC_RSR_WWDGRSTF_Msk                   (0x1UL << RCC_RSR_WWDGRSTF_Pos) /*!< 0x10000000 */

+#define RCC_RSR_WWDGRSTF                       RCC_RSR_WWDGRSTF_Msk

+

+#define RCC_RSR_LPWRRSTF_Pos                   (30U)

+#define RCC_RSR_LPWRRSTF_Msk                   (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */

+#define RCC_RSR_LPWRRSTF                       RCC_RSR_LPWRRSTF_Msk

+

+

+/* Legacy define */

+#define RCC_RSR_IWDG1RSTF_Pos                  RCC_RSR_IWDGRSTF_Pos

+#define RCC_RSR_IWDG1RSTF_Msk                  RCC_RSR_IWDGRSTF_Msk

+#define RCC_RSR_IWDG1RSTF                      RCC_RSR_IWDGRSTF

+#define RCC_RSR_WWDG1RSTF_Pos                  RCC_RSR_WWDGRSTF_Pos

+#define RCC_RSR_WWDG1RSTF_Msk                  RCC_RSR_WWDGRSTF_Msk

+#define RCC_RSR_WWDG1RSTF                      RCC_RSR_WWDGRSTF

+/******************************************************************************/

+/*                                                                            */

+/*                                    RNG                                     */

+/*                                                                            */

+/******************************************************************************/

+/***************************    RNG VER  **************************************/

+#define RNG_VER_3_1

+/********************  Bits definition for RNG_CR register  *******************/

+#define RNG_CR_RNGEN_Pos    (2U)

+#define RNG_CR_RNGEN_Msk    (0x1UL << RNG_CR_RNGEN_Pos)                        /*!< 0x00000004 */

+#define RNG_CR_RNGEN        RNG_CR_RNGEN_Msk

+#define RNG_CR_IE_Pos       (3U)

+#define RNG_CR_IE_Msk       (0x1UL << RNG_CR_IE_Pos)                           /*!< 0x00000008 */

+#define RNG_CR_IE           RNG_CR_IE_Msk

+#define RNG_CR_CED_Pos      (5U)

+#define RNG_CR_CED_Msk      (0x1UL << RNG_CR_CED_Pos)                          /*!< 0x00000020 */

+#define RNG_CR_CED          RNG_CR_CED_Msk

+#define RNG_CR_RNG_CONFIG3_Pos      (8U)

+#define RNG_CR_RNG_CONFIG3_Msk      (0xFUL << RNG_CR_RNG_CONFIG3_Pos)          /*!< 0x00000F00 */

+#define RNG_CR_RNG_CONFIG3          RNG_CR_RNG_CONFIG3_Msk

+#define RNG_CR_NISTC_Pos            (12U)

+#define RNG_CR_NISTC_Msk            (0x1UL << RNG_CR_NISTC_Pos)                /*!< 0x00001000 */

+#define RNG_CR_NISTC                RNG_CR_NISTC_Msk

+#define RNG_CR_RNG_CONFIG2_Pos      (13U)

+#define RNG_CR_RNG_CONFIG2_Msk      (0x7UL << RNG_CR_RNG_CONFIG2_Pos)          /*!< 0x0000E000 */

+#define RNG_CR_RNG_CONFIG2          RNG_CR_RNG_CONFIG2_Msk

+#define RNG_CR_CLKDIV_Pos           (16U)

+#define RNG_CR_CLKDIV_Msk           (0xFUL << RNG_CR_CLKDIV_Pos)               /*!< 0x000F0000 */

+#define RNG_CR_CLKDIV               RNG_CR_CLKDIV_Msk

+#define RNG_CR_CLKDIV_0             (0x1U << RNG_CR_CLKDIV_Pos)                /*!< 0x00010000 */

+#define RNG_CR_CLKDIV_1             (0x2U << RNG_CR_CLKDIV_Pos)                /*!< 0x00020000 */

+#define RNG_CR_CLKDIV_2             (0x4U << RNG_CR_CLKDIV_Pos)                /*!< 0x00040000 */

+#define RNG_CR_CLKDIV_3             (0x8U << RNG_CR_CLKDIV_Pos)                /*!< 0x00080000 */

+#define RNG_CR_RNG_CONFIG1_Pos      (20U)

+#define RNG_CR_RNG_CONFIG1_Msk      (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)         /*!< 0x03F00000 */

+#define RNG_CR_RNG_CONFIG1          RNG_CR_RNG_CONFIG1_Msk

+#define RNG_CR_CONDRST_Pos         (30U)

+#define RNG_CR_CONDRST_Msk         (0x1UL << RNG_CR_CONDRST_Pos)                  /*!< 0x40000000 */

+#define RNG_CR_CONDRST             RNG_CR_CONDRST_Msk

+#define RNG_CR_CONFIGLOCK_Pos      (31U)

+#define RNG_CR_CONFIGLOCK_Msk      (0x1UL << RNG_CR_CONFIGLOCK_Pos)            /*!< 0x80000000 */

+#define RNG_CR_CONFIGLOCK          RNG_CR_CONFIGLOCK_Msk

+

+/********************  Bits definition for RNG_SR register  *******************/

+#define RNG_SR_DRDY_Pos     (0U)

+#define RNG_SR_DRDY_Msk     (0x1UL << RNG_SR_DRDY_Pos)                         /*!< 0x00000001 */

+#define RNG_SR_DRDY         RNG_SR_DRDY_Msk

+#define RNG_SR_CECS_Pos     (1U)

+#define RNG_SR_CECS_Msk     (0x1UL << RNG_SR_CECS_Pos)                         /*!< 0x00000002 */

+#define RNG_SR_CECS         RNG_SR_CECS_Msk

+#define RNG_SR_SECS_Pos     (2U)

+#define RNG_SR_SECS_Msk     (0x1UL << RNG_SR_SECS_Pos)                         /*!< 0x00000004 */

+#define RNG_SR_SECS         RNG_SR_SECS_Msk

+#define RNG_SR_CEIS_Pos     (5U)

+#define RNG_SR_CEIS_Msk     (0x1UL << RNG_SR_CEIS_Pos)                         /*!< 0x00000020 */

+#define RNG_SR_CEIS         RNG_SR_CEIS_Msk

+#define RNG_SR_SEIS_Pos     (6U)

+#define RNG_SR_SEIS_Msk     (0x1UL << RNG_SR_SEIS_Pos)                         /*!< 0x00000040 */

+#define RNG_SR_SEIS         RNG_SR_SEIS_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                           Real-Time Clock (RTC)                            */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for RTC_TR register  *******************/

+#define RTC_TR_PM_Pos                  (22U)

+#define RTC_TR_PM_Msk                  (0x1UL << RTC_TR_PM_Pos)                /*!< 0x00400000 */

+#define RTC_TR_PM                      RTC_TR_PM_Msk

+#define RTC_TR_HT_Pos                  (20U)

+#define RTC_TR_HT_Msk                  (0x3UL << RTC_TR_HT_Pos)                /*!< 0x00300000 */

+#define RTC_TR_HT                      RTC_TR_HT_Msk

+#define RTC_TR_HT_0                    (0x1UL << RTC_TR_HT_Pos)                 /*!< 0x00100000 */

+#define RTC_TR_HT_1                    (0x2UL << RTC_TR_HT_Pos)                 /*!< 0x00200000 */

+#define RTC_TR_HU_Pos                  (16U)

+#define RTC_TR_HU_Msk                  (0xFUL << RTC_TR_HU_Pos)                /*!< 0x000F0000 */

+#define RTC_TR_HU                      RTC_TR_HU_Msk

+#define RTC_TR_HU_0                    (0x1UL << RTC_TR_HU_Pos)                 /*!< 0x00010000 */

+#define RTC_TR_HU_1                    (0x2UL << RTC_TR_HU_Pos)                 /*!< 0x00020000 */

+#define RTC_TR_HU_2                    (0x4UL << RTC_TR_HU_Pos)                 /*!< 0x00040000 */

+#define RTC_TR_HU_3                    (0x8UL << RTC_TR_HU_Pos)                 /*!< 0x00080000 */

+#define RTC_TR_MNT_Pos                 (12U)

+#define RTC_TR_MNT_Msk                 (0x7UL << RTC_TR_MNT_Pos)               /*!< 0x00007000 */

+#define RTC_TR_MNT                     RTC_TR_MNT_Msk

+#define RTC_TR_MNT_0                   (0x1UL << RTC_TR_MNT_Pos)                /*!< 0x00001000 */

+#define RTC_TR_MNT_1                   (0x2UL << RTC_TR_MNT_Pos)                /*!< 0x00002000 */

+#define RTC_TR_MNT_2                   (0x4UL << RTC_TR_MNT_Pos)                /*!< 0x00004000 */

+#define RTC_TR_MNU_Pos                 (8U)

+#define RTC_TR_MNU_Msk                 (0xFUL << RTC_TR_MNU_Pos)               /*!< 0x00000F00 */

+#define RTC_TR_MNU                     RTC_TR_MNU_Msk

+#define RTC_TR_MNU_0                   (0x1UL << RTC_TR_MNU_Pos)                /*!< 0x00000100 */

+#define RTC_TR_MNU_1                   (0x2UL << RTC_TR_MNU_Pos)                /*!< 0x00000200 */

+#define RTC_TR_MNU_2                   (0x4UL << RTC_TR_MNU_Pos)                /*!< 0x00000400 */

+#define RTC_TR_MNU_3                   (0x8UL << RTC_TR_MNU_Pos)                /*!< 0x00000800 */

+#define RTC_TR_ST_Pos                  (4U)

+#define RTC_TR_ST_Msk                  (0x7UL << RTC_TR_ST_Pos)                /*!< 0x00000070 */

+#define RTC_TR_ST                      RTC_TR_ST_Msk

+#define RTC_TR_ST_0                    (0x1UL << RTC_TR_ST_Pos)                 /*!< 0x00000010 */

+#define RTC_TR_ST_1                    (0x2UL << RTC_TR_ST_Pos)                 /*!< 0x00000020 */

+#define RTC_TR_ST_2                    (0x4UL << RTC_TR_ST_Pos)                 /*!< 0x00000040 */

+#define RTC_TR_SU_Pos                  (0U)

+#define RTC_TR_SU_Msk                  (0xFUL << RTC_TR_SU_Pos)                /*!< 0x0000000F */

+#define RTC_TR_SU                      RTC_TR_SU_Msk

+#define RTC_TR_SU_0                    (0x1UL << RTC_TR_SU_Pos)                 /*!< 0x00000001 */

+#define RTC_TR_SU_1                    (0x2UL << RTC_TR_SU_Pos)                 /*!< 0x00000002 */

+#define RTC_TR_SU_2                    (0x4UL << RTC_TR_SU_Pos)                 /*!< 0x00000004 */

+#define RTC_TR_SU_3                    (0x8UL << RTC_TR_SU_Pos)                 /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_DR register  *******************/

+#define RTC_DR_YT_Pos                  (20U)

+#define RTC_DR_YT_Msk                  (0xFUL << RTC_DR_YT_Pos)                /*!< 0x00F00000 */

+#define RTC_DR_YT                      RTC_DR_YT_Msk

+#define RTC_DR_YT_0                    (0x1UL << RTC_DR_YT_Pos)                 /*!< 0x00100000 */

+#define RTC_DR_YT_1                    (0x2UL << RTC_DR_YT_Pos)                 /*!< 0x00200000 */

+#define RTC_DR_YT_2                    (0x4UL << RTC_DR_YT_Pos)                 /*!< 0x00400000 */

+#define RTC_DR_YT_3                    (0x8UL << RTC_DR_YT_Pos)                 /*!< 0x00800000 */

+#define RTC_DR_YU_Pos                  (16U)

+#define RTC_DR_YU_Msk                  (0xFUL << RTC_DR_YU_Pos)                /*!< 0x000F0000 */

+#define RTC_DR_YU                      RTC_DR_YU_Msk

+#define RTC_DR_YU_0                    (0x1UL << RTC_DR_YU_Pos)                 /*!< 0x00010000 */

+#define RTC_DR_YU_1                    (0x2UL << RTC_DR_YU_Pos)                 /*!< 0x00020000 */

+#define RTC_DR_YU_2                    (0x4UL << RTC_DR_YU_Pos)                 /*!< 0x00040000 */

+#define RTC_DR_YU_3                    (0x8UL << RTC_DR_YU_Pos)                 /*!< 0x00080000 */

+#define RTC_DR_WDU_Pos                 (13U)

+#define RTC_DR_WDU_Msk                 (0x7UL << RTC_DR_WDU_Pos)               /*!< 0x0000E000 */

+#define RTC_DR_WDU                     RTC_DR_WDU_Msk

+#define RTC_DR_WDU_0                   (0x1UL << RTC_DR_WDU_Pos)                /*!< 0x00002000 */

+#define RTC_DR_WDU_1                   (0x2UL << RTC_DR_WDU_Pos)                /*!< 0x00004000 */

+#define RTC_DR_WDU_2                   (0x4UL << RTC_DR_WDU_Pos)                /*!< 0x00008000 */

+#define RTC_DR_MT_Pos                  (12U)

+#define RTC_DR_MT_Msk                  (0x1UL << RTC_DR_MT_Pos)                /*!< 0x00001000 */

+#define RTC_DR_MT                      RTC_DR_MT_Msk

+#define RTC_DR_MU_Pos                  (8U)

+#define RTC_DR_MU_Msk                  (0xFUL << RTC_DR_MU_Pos)                /*!< 0x00000F00 */

+#define RTC_DR_MU                      RTC_DR_MU_Msk

+#define RTC_DR_MU_0                    (0x1UL << RTC_DR_MU_Pos)                 /*!< 0x00000100 */

+#define RTC_DR_MU_1                    (0x2UL << RTC_DR_MU_Pos)                 /*!< 0x00000200 */

+#define RTC_DR_MU_2                    (0x4UL << RTC_DR_MU_Pos)                 /*!< 0x00000400 */

+#define RTC_DR_MU_3                    (0x8UL << RTC_DR_MU_Pos)                 /*!< 0x00000800 */

+#define RTC_DR_DT_Pos                  (4U)

+#define RTC_DR_DT_Msk                  (0x3UL << RTC_DR_DT_Pos)                /*!< 0x00000030 */

+#define RTC_DR_DT                      RTC_DR_DT_Msk

+#define RTC_DR_DT_0                    (0x1UL << RTC_DR_DT_Pos)                 /*!< 0x00000010 */

+#define RTC_DR_DT_1                    (0x2UL << RTC_DR_DT_Pos)                 /*!< 0x00000020 */

+#define RTC_DR_DU_Pos                  (0U)

+#define RTC_DR_DU_Msk                  (0xFUL << RTC_DR_DU_Pos)                /*!< 0x0000000F */

+#define RTC_DR_DU                      RTC_DR_DU_Msk

+#define RTC_DR_DU_0                    (0x1UL << RTC_DR_DU_Pos)                 /*!< 0x00000001 */

+#define RTC_DR_DU_1                    (0x2UL << RTC_DR_DU_Pos)                 /*!< 0x00000002 */

+#define RTC_DR_DU_2                    (0x4UL << RTC_DR_DU_Pos)                 /*!< 0x00000004 */

+#define RTC_DR_DU_3                    (0x8UL << RTC_DR_DU_Pos)                 /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_CR register  *******************/

+#define RTC_CR_OUT2EN_Pos            (31U)

+#define RTC_CR_OUT2EN_Msk            (0x1UL << RTC_CR_OUT2EN_Pos)              /*!< 0x80000000 */

+#define RTC_CR_OUT2EN                RTC_CR_OUT2EN_Msk                         /*!<RTC_OUT2 output enable */

+#define RTC_CR_TAMPALRM_TYPE_Pos     (30U)

+#define RTC_CR_TAMPALRM_TYPE_Msk     (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos)       /*!< 0x40000000 */

+#define RTC_CR_TAMPALRM_TYPE         RTC_CR_TAMPALRM_TYPE_Msk                  /*!<TAMPALARM output type  */

+#define RTC_CR_TAMPALRM_PU_Pos       (29U)

+#define RTC_CR_TAMPALRM_PU_Msk       (0x1UL << RTC_CR_TAMPALRM_PU_Pos)         /*!< 0x20000000 */

+#define RTC_CR_TAMPALRM_PU           RTC_CR_TAMPALRM_PU_Msk                    /*!<TAMPALARM output pull-up config */

+#define RTC_CR_TAMPOE_Pos            (26U)

+#define RTC_CR_TAMPOE_Msk            (0x1UL << RTC_CR_TAMPOE_Pos)              /*!< 0x04000000 */

+#define RTC_CR_TAMPOE                RTC_CR_TAMPOE_Msk                         /*!<Tamper detection output enable on TAMPALARM  */

+#define RTC_CR_TAMPTS_Pos            (25U)

+#define RTC_CR_TAMPTS_Msk            (0x1UL << RTC_CR_TAMPTS_Pos)              /*!< 0x02000000 */

+#define RTC_CR_TAMPTS                RTC_CR_TAMPTS_Msk                         /*!<Activate timestamp on tamper detection event  */

+#define RTC_CR_ITSE_Pos                (24U)

+#define RTC_CR_ITSE_Msk                (0x1UL << RTC_CR_ITSE_Pos)              /*!< 0x01000000 */

+#define RTC_CR_ITSE                    RTC_CR_ITSE_Msk

+#define RTC_CR_COE_Pos                 (23U)

+#define RTC_CR_COE_Msk                 (0x1UL << RTC_CR_COE_Pos)               /*!< 0x00800000 */

+#define RTC_CR_COE                     RTC_CR_COE_Msk

+#define RTC_CR_OSEL_Pos                (21U)

+#define RTC_CR_OSEL_Msk                (0x3UL << RTC_CR_OSEL_Pos)              /*!< 0x00600000 */

+#define RTC_CR_OSEL                    RTC_CR_OSEL_Msk

+#define RTC_CR_OSEL_0                  (0x1UL << RTC_CR_OSEL_Pos)               /*!< 0x00200000 */

+#define RTC_CR_OSEL_1                  (0x2UL << RTC_CR_OSEL_Pos)               /*!< 0x00400000 */

+#define RTC_CR_POL_Pos                 (20U)

+#define RTC_CR_POL_Msk                 (0x1UL << RTC_CR_POL_Pos)               /*!< 0x00100000 */

+#define RTC_CR_POL                     RTC_CR_POL_Msk

+#define RTC_CR_COSEL_Pos               (19U)

+#define RTC_CR_COSEL_Msk               (0x1UL << RTC_CR_COSEL_Pos)             /*!< 0x00080000 */

+#define RTC_CR_COSEL                   RTC_CR_COSEL_Msk

+#define RTC_CR_BKP_Pos                 (18U)

+#define RTC_CR_BKP_Msk                 (0x1UL << RTC_CR_BKP_Pos)               /*!< 0x00040000 */

+#define RTC_CR_BKP                     RTC_CR_BKP_Msk

+#define RTC_CR_SUB1H_Pos               (17U)

+#define RTC_CR_SUB1H_Msk               (0x1UL << RTC_CR_SUB1H_Pos)             /*!< 0x00020000 */

+#define RTC_CR_SUB1H                   RTC_CR_SUB1H_Msk

+#define RTC_CR_ADD1H_Pos               (16U)

+#define RTC_CR_ADD1H_Msk               (0x1UL << RTC_CR_ADD1H_Pos)             /*!< 0x00010000 */

+#define RTC_CR_ADD1H                   RTC_CR_ADD1H_Msk

+#define RTC_CR_TSIE_Pos                (15U)

+#define RTC_CR_TSIE_Msk                (0x1UL << RTC_CR_TSIE_Pos)              /*!< 0x00008000 */

+#define RTC_CR_TSIE                    RTC_CR_TSIE_Msk

+#define RTC_CR_WUTIE_Pos               (14U)

+#define RTC_CR_WUTIE_Msk               (0x1UL << RTC_CR_WUTIE_Pos)             /*!< 0x00004000 */

+#define RTC_CR_WUTIE                   RTC_CR_WUTIE_Msk

+#define RTC_CR_ALRBIE_Pos              (13U)

+#define RTC_CR_ALRBIE_Msk              (0x1UL << RTC_CR_ALRBIE_Pos)            /*!< 0x00002000 */

+#define RTC_CR_ALRBIE                  RTC_CR_ALRBIE_Msk

+#define RTC_CR_ALRAIE_Pos              (12U)

+#define RTC_CR_ALRAIE_Msk              (0x1UL << RTC_CR_ALRAIE_Pos)            /*!< 0x00001000 */

+#define RTC_CR_ALRAIE                  RTC_CR_ALRAIE_Msk

+#define RTC_CR_TSE_Pos                 (11U)

+#define RTC_CR_TSE_Msk                 (0x1UL << RTC_CR_TSE_Pos)               /*!< 0x00000800 */

+#define RTC_CR_TSE                     RTC_CR_TSE_Msk

+#define RTC_CR_WUTE_Pos                (10U)

+#define RTC_CR_WUTE_Msk                (0x1UL << RTC_CR_WUTE_Pos)              /*!< 0x00000400 */

+#define RTC_CR_WUTE                    RTC_CR_WUTE_Msk

+#define RTC_CR_ALRBE_Pos               (9U)

+#define RTC_CR_ALRBE_Msk               (0x1UL << RTC_CR_ALRBE_Pos)             /*!< 0x00000200 */

+#define RTC_CR_ALRBE                   RTC_CR_ALRBE_Msk

+#define RTC_CR_ALRAE_Pos               (8U)

+#define RTC_CR_ALRAE_Msk               (0x1UL << RTC_CR_ALRAE_Pos)             /*!< 0x00000100 */

+#define RTC_CR_ALRAE                   RTC_CR_ALRAE_Msk

+#define RTC_CR_FMT_Pos                 (6U)

+#define RTC_CR_FMT_Msk                 (0x1UL << RTC_CR_FMT_Pos)               /*!< 0x00000040 */

+#define RTC_CR_FMT                     RTC_CR_FMT_Msk

+#define RTC_CR_BYPSHAD_Pos             (5U)

+#define RTC_CR_BYPSHAD_Msk             (0x1UL << RTC_CR_BYPSHAD_Pos)           /*!< 0x00000020 */

+#define RTC_CR_BYPSHAD                 RTC_CR_BYPSHAD_Msk

+#define RTC_CR_REFCKON_Pos             (4U)

+#define RTC_CR_REFCKON_Msk             (0x1UL << RTC_CR_REFCKON_Pos)           /*!< 0x00000010 */

+#define RTC_CR_REFCKON                 RTC_CR_REFCKON_Msk

+#define RTC_CR_TSEDGE_Pos              (3U)

+#define RTC_CR_TSEDGE_Msk              (0x1UL << RTC_CR_TSEDGE_Pos)            /*!< 0x00000008 */

+#define RTC_CR_TSEDGE                  RTC_CR_TSEDGE_Msk

+#define RTC_CR_WUCKSEL_Pos             (0U)

+#define RTC_CR_WUCKSEL_Msk             (0x7UL << RTC_CR_WUCKSEL_Pos)           /*!< 0x00000007 */

+#define RTC_CR_WUCKSEL                 RTC_CR_WUCKSEL_Msk

+#define RTC_CR_WUCKSEL_0               (0x1UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000001 */

+#define RTC_CR_WUCKSEL_1               (0x2UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000002 */

+#define RTC_CR_WUCKSEL_2               (0x4UL << RTC_CR_WUCKSEL_Pos)            /*!< 0x00000004 */

+

+/********************  Bits definition for RTC_ICSR register  ******************/

+#define RTC_ICSR_RECALPF_Pos         (16U)

+#define RTC_ICSR_RECALPF_Msk         (0x1UL << RTC_ICSR_RECALPF_Pos)           /*!< 0x00010000 */

+#define RTC_ICSR_RECALPF             RTC_ICSR_RECALPF_Msk

+#define RTC_ICSR_INIT_Pos            (7U)

+#define RTC_ICSR_INIT_Msk            (0x1UL << RTC_ICSR_INIT_Pos)              /*!< 0x00000080 */

+#define RTC_ICSR_INIT                RTC_ICSR_INIT_Msk

+#define RTC_ICSR_INITF_Pos           (6U)

+#define RTC_ICSR_INITF_Msk           (0x1UL << RTC_ICSR_INITF_Pos)             /*!< 0x00000040 */

+#define RTC_ICSR_INITF               RTC_ICSR_INITF_Msk

+#define RTC_ICSR_RSF_Pos             (5U)

+#define RTC_ICSR_RSF_Msk             (0x1UL << RTC_ICSR_RSF_Pos)               /*!< 0x00000020 */

+#define RTC_ICSR_RSF                 RTC_ICSR_RSF_Msk

+#define RTC_ICSR_INITS_Pos           (4U)

+#define RTC_ICSR_INITS_Msk           (0x1UL << RTC_ICSR_INITS_Pos)             /*!< 0x00000010 */

+#define RTC_ICSR_INITS               RTC_ICSR_INITS_Msk

+#define RTC_ICSR_SHPF_Pos            (3U)

+#define RTC_ICSR_SHPF_Msk            (0x1UL << RTC_ICSR_SHPF_Pos)              /*!< 0x00000008 */

+#define RTC_ICSR_SHPF                RTC_ICSR_SHPF_Msk

+#define RTC_ICSR_WUTWF_Pos           (2U)

+#define RTC_ICSR_WUTWF_Msk           (0x1UL << RTC_ICSR_WUTWF_Pos)             /*!< 0x00000004 */

+#define RTC_ICSR_WUTWF               RTC_ICSR_WUTWF_Msk

+#define RTC_ICSR_ALRBWF_Pos          (1U)

+#define RTC_ICSR_ALRBWF_Msk          (0x1UL << RTC_ICSR_ALRBWF_Pos)            /*!< 0x00000002 */

+#define RTC_ICSR_ALRBWF              RTC_ICSR_ALRBWF_Msk

+#define RTC_ICSR_ALRAWF_Pos          (0U)

+#define RTC_ICSR_ALRAWF_Msk          (0x1UL << RTC_ICSR_ALRAWF_Pos)            /*!< 0x00000001 */

+#define RTC_ICSR_ALRAWF              RTC_ICSR_ALRAWF_Msk

+

+/********************  Bits definition for RTC_PRER register  *****************/

+#define RTC_PRER_PREDIV_A_Pos          (16U)

+#define RTC_PRER_PREDIV_A_Msk          (0x7FUL << RTC_PRER_PREDIV_A_Pos)       /*!< 0x007F0000 */

+#define RTC_PRER_PREDIV_A              RTC_PRER_PREDIV_A_Msk

+#define RTC_PRER_PREDIV_S_Pos          (0U)

+#define RTC_PRER_PREDIV_S_Msk          (0x7FFFUL << RTC_PRER_PREDIV_S_Pos)     /*!< 0x00007FFF */

+#define RTC_PRER_PREDIV_S              RTC_PRER_PREDIV_S_Msk

+

+/********************  Bits definition for RTC_WUTR register  *****************/

+#define RTC_WUTR_WUT_Pos               (0U)

+#define RTC_WUTR_WUT_Msk               (0xFFFFUL << RTC_WUTR_WUT_Pos)          /*!< 0x0000FFFF */

+#define RTC_WUTR_WUT                   RTC_WUTR_WUT_Msk

+

+/********************  Bits definition for RTC_ALRMAR register  ***************/

+#define RTC_ALRMAR_MSK4_Pos            (31U)

+#define RTC_ALRMAR_MSK4_Msk            (0x1UL << RTC_ALRMAR_MSK4_Pos)          /*!< 0x80000000 */

+#define RTC_ALRMAR_MSK4                RTC_ALRMAR_MSK4_Msk

+#define RTC_ALRMAR_WDSEL_Pos           (30U)

+#define RTC_ALRMAR_WDSEL_Msk           (0x1UL << RTC_ALRMAR_WDSEL_Pos)         /*!< 0x40000000 */

+#define RTC_ALRMAR_WDSEL               RTC_ALRMAR_WDSEL_Msk

+#define RTC_ALRMAR_DT_Pos              (28U)

+#define RTC_ALRMAR_DT_Msk              (0x3UL << RTC_ALRMAR_DT_Pos)            /*!< 0x30000000 */

+#define RTC_ALRMAR_DT                  RTC_ALRMAR_DT_Msk

+#define RTC_ALRMAR_DT_0                (0x1UL << RTC_ALRMAR_DT_Pos)             /*!< 0x10000000 */

+#define RTC_ALRMAR_DT_1                (0x2UL << RTC_ALRMAR_DT_Pos)             /*!< 0x20000000 */

+#define RTC_ALRMAR_DU_Pos              (24U)

+#define RTC_ALRMAR_DU_Msk              (0xFUL << RTC_ALRMAR_DU_Pos)            /*!< 0x0F000000 */

+#define RTC_ALRMAR_DU                  RTC_ALRMAR_DU_Msk

+#define RTC_ALRMAR_DU_0                (0x1UL << RTC_ALRMAR_DU_Pos)             /*!< 0x01000000 */

+#define RTC_ALRMAR_DU_1                (0x2UL << RTC_ALRMAR_DU_Pos)             /*!< 0x02000000 */

+#define RTC_ALRMAR_DU_2                (0x4UL << RTC_ALRMAR_DU_Pos)             /*!< 0x04000000 */

+#define RTC_ALRMAR_DU_3                (0x8UL << RTC_ALRMAR_DU_Pos)             /*!< 0x08000000 */

+#define RTC_ALRMAR_MSK3_Pos            (23U)

+#define RTC_ALRMAR_MSK3_Msk            (0x1UL << RTC_ALRMAR_MSK3_Pos)          /*!< 0x00800000 */

+#define RTC_ALRMAR_MSK3                RTC_ALRMAR_MSK3_Msk

+#define RTC_ALRMAR_PM_Pos              (22U)

+#define RTC_ALRMAR_PM_Msk              (0x1UL << RTC_ALRMAR_PM_Pos)            /*!< 0x00400000 */

+#define RTC_ALRMAR_PM                  RTC_ALRMAR_PM_Msk

+#define RTC_ALRMAR_HT_Pos              (20U)

+#define RTC_ALRMAR_HT_Msk              (0x3UL << RTC_ALRMAR_HT_Pos)            /*!< 0x00300000 */

+#define RTC_ALRMAR_HT                  RTC_ALRMAR_HT_Msk

+#define RTC_ALRMAR_HT_0                (0x1UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00100000 */

+#define RTC_ALRMAR_HT_1                (0x2UL << RTC_ALRMAR_HT_Pos)             /*!< 0x00200000 */

+#define RTC_ALRMAR_HU_Pos              (16U)

+#define RTC_ALRMAR_HU_Msk              (0xFUL << RTC_ALRMAR_HU_Pos)            /*!< 0x000F0000 */

+#define RTC_ALRMAR_HU                  RTC_ALRMAR_HU_Msk

+#define RTC_ALRMAR_HU_0                (0x1UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00010000 */

+#define RTC_ALRMAR_HU_1                (0x2UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00020000 */

+#define RTC_ALRMAR_HU_2                (0x4UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00040000 */

+#define RTC_ALRMAR_HU_3                (0x8UL << RTC_ALRMAR_HU_Pos)             /*!< 0x00080000 */

+#define RTC_ALRMAR_MSK2_Pos            (15U)

+#define RTC_ALRMAR_MSK2_Msk            (0x1UL << RTC_ALRMAR_MSK2_Pos)          /*!< 0x00008000 */

+#define RTC_ALRMAR_MSK2                RTC_ALRMAR_MSK2_Msk

+#define RTC_ALRMAR_MNT_Pos             (12U)

+#define RTC_ALRMAR_MNT_Msk             (0x7UL << RTC_ALRMAR_MNT_Pos)           /*!< 0x00007000 */

+#define RTC_ALRMAR_MNT                 RTC_ALRMAR_MNT_Msk

+#define RTC_ALRMAR_MNT_0               (0x1UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00001000 */

+#define RTC_ALRMAR_MNT_1               (0x2UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00002000 */

+#define RTC_ALRMAR_MNT_2               (0x4UL << RTC_ALRMAR_MNT_Pos)            /*!< 0x00004000 */

+#define RTC_ALRMAR_MNU_Pos             (8U)

+#define RTC_ALRMAR_MNU_Msk             (0xFUL << RTC_ALRMAR_MNU_Pos)           /*!< 0x00000F00 */

+#define RTC_ALRMAR_MNU                 RTC_ALRMAR_MNU_Msk

+#define RTC_ALRMAR_MNU_0               (0x1UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000100 */

+#define RTC_ALRMAR_MNU_1               (0x2UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000200 */

+#define RTC_ALRMAR_MNU_2               (0x4UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000400 */

+#define RTC_ALRMAR_MNU_3               (0x8UL << RTC_ALRMAR_MNU_Pos)            /*!< 0x00000800 */

+#define RTC_ALRMAR_MSK1_Pos            (7U)

+#define RTC_ALRMAR_MSK1_Msk            (0x1UL << RTC_ALRMAR_MSK1_Pos)          /*!< 0x00000080 */

+#define RTC_ALRMAR_MSK1                RTC_ALRMAR_MSK1_Msk

+#define RTC_ALRMAR_ST_Pos              (4U)

+#define RTC_ALRMAR_ST_Msk              (0x7UL << RTC_ALRMAR_ST_Pos)            /*!< 0x00000070 */

+#define RTC_ALRMAR_ST                  RTC_ALRMAR_ST_Msk

+#define RTC_ALRMAR_ST_0                (0x1UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000010 */

+#define RTC_ALRMAR_ST_1                (0x2UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000020 */

+#define RTC_ALRMAR_ST_2                (0x4UL << RTC_ALRMAR_ST_Pos)             /*!< 0x00000040 */

+#define RTC_ALRMAR_SU_Pos              (0U)

+#define RTC_ALRMAR_SU_Msk              (0xFUL << RTC_ALRMAR_SU_Pos)            /*!< 0x0000000F */

+#define RTC_ALRMAR_SU                  RTC_ALRMAR_SU_Msk

+#define RTC_ALRMAR_SU_0                (0x1UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000001 */

+#define RTC_ALRMAR_SU_1                (0x2UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000002 */

+#define RTC_ALRMAR_SU_2                (0x4UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000004 */

+#define RTC_ALRMAR_SU_3                (0x8UL << RTC_ALRMAR_SU_Pos)             /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_ALRMBR register  ***************/

+#define RTC_ALRMBR_MSK4_Pos            (31U)

+#define RTC_ALRMBR_MSK4_Msk            (0x1UL << RTC_ALRMBR_MSK4_Pos)          /*!< 0x80000000 */

+#define RTC_ALRMBR_MSK4                RTC_ALRMBR_MSK4_Msk

+#define RTC_ALRMBR_WDSEL_Pos           (30U)

+#define RTC_ALRMBR_WDSEL_Msk           (0x1UL << RTC_ALRMBR_WDSEL_Pos)         /*!< 0x40000000 */

+#define RTC_ALRMBR_WDSEL               RTC_ALRMBR_WDSEL_Msk

+#define RTC_ALRMBR_DT_Pos              (28U)

+#define RTC_ALRMBR_DT_Msk              (0x3UL << RTC_ALRMBR_DT_Pos)            /*!< 0x30000000 */

+#define RTC_ALRMBR_DT                  RTC_ALRMBR_DT_Msk

+#define RTC_ALRMBR_DT_0                (0x1UL << RTC_ALRMBR_DT_Pos)             /*!< 0x10000000 */

+#define RTC_ALRMBR_DT_1                (0x2UL << RTC_ALRMBR_DT_Pos)             /*!< 0x20000000 */

+#define RTC_ALRMBR_DU_Pos              (24U)

+#define RTC_ALRMBR_DU_Msk              (0xFUL << RTC_ALRMBR_DU_Pos)            /*!< 0x0F000000 */

+#define RTC_ALRMBR_DU                  RTC_ALRMBR_DU_Msk

+#define RTC_ALRMBR_DU_0                (0x1UL << RTC_ALRMBR_DU_Pos)             /*!< 0x01000000 */

+#define RTC_ALRMBR_DU_1                (0x2UL << RTC_ALRMBR_DU_Pos)             /*!< 0x02000000 */

+#define RTC_ALRMBR_DU_2                (0x4UL << RTC_ALRMBR_DU_Pos)             /*!< 0x04000000 */

+#define RTC_ALRMBR_DU_3                (0x8UL << RTC_ALRMBR_DU_Pos)             /*!< 0x08000000 */

+#define RTC_ALRMBR_MSK3_Pos            (23U)

+#define RTC_ALRMBR_MSK3_Msk            (0x1UL << RTC_ALRMBR_MSK3_Pos)          /*!< 0x00800000 */

+#define RTC_ALRMBR_MSK3                RTC_ALRMBR_MSK3_Msk

+#define RTC_ALRMBR_PM_Pos              (22U)

+#define RTC_ALRMBR_PM_Msk              (0x1UL << RTC_ALRMBR_PM_Pos)            /*!< 0x00400000 */

+#define RTC_ALRMBR_PM                  RTC_ALRMBR_PM_Msk

+#define RTC_ALRMBR_HT_Pos              (20U)

+#define RTC_ALRMBR_HT_Msk              (0x3UL << RTC_ALRMBR_HT_Pos)            /*!< 0x00300000 */

+#define RTC_ALRMBR_HT                  RTC_ALRMBR_HT_Msk

+#define RTC_ALRMBR_HT_0                (0x1UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00100000 */

+#define RTC_ALRMBR_HT_1                (0x2UL << RTC_ALRMBR_HT_Pos)             /*!< 0x00200000 */

+#define RTC_ALRMBR_HU_Pos              (16U)

+#define RTC_ALRMBR_HU_Msk              (0xFUL << RTC_ALRMBR_HU_Pos)            /*!< 0x000F0000 */

+#define RTC_ALRMBR_HU                  RTC_ALRMBR_HU_Msk

+#define RTC_ALRMBR_HU_0                (0x1UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00010000 */

+#define RTC_ALRMBR_HU_1                (0x2UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00020000 */

+#define RTC_ALRMBR_HU_2                (0x4UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00040000 */

+#define RTC_ALRMBR_HU_3                (0x8UL << RTC_ALRMBR_HU_Pos)             /*!< 0x00080000 */

+#define RTC_ALRMBR_MSK2_Pos            (15U)

+#define RTC_ALRMBR_MSK2_Msk            (0x1UL << RTC_ALRMBR_MSK2_Pos)          /*!< 0x00008000 */

+#define RTC_ALRMBR_MSK2                RTC_ALRMBR_MSK2_Msk

+#define RTC_ALRMBR_MNT_Pos             (12U)

+#define RTC_ALRMBR_MNT_Msk             (0x7UL << RTC_ALRMBR_MNT_Pos)           /*!< 0x00007000 */

+#define RTC_ALRMBR_MNT                 RTC_ALRMBR_MNT_Msk

+#define RTC_ALRMBR_MNT_0               (0x1UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00001000 */

+#define RTC_ALRMBR_MNT_1               (0x2UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00002000 */

+#define RTC_ALRMBR_MNT_2               (0x4UL << RTC_ALRMBR_MNT_Pos)            /*!< 0x00004000 */

+#define RTC_ALRMBR_MNU_Pos             (8U)

+#define RTC_ALRMBR_MNU_Msk             (0xFUL << RTC_ALRMBR_MNU_Pos)           /*!< 0x00000F00 */

+#define RTC_ALRMBR_MNU                 RTC_ALRMBR_MNU_Msk

+#define RTC_ALRMBR_MNU_0               (0x1UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000100 */

+#define RTC_ALRMBR_MNU_1               (0x2UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000200 */

+#define RTC_ALRMBR_MNU_2               (0x4UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000400 */

+#define RTC_ALRMBR_MNU_3               (0x8UL << RTC_ALRMBR_MNU_Pos)            /*!< 0x00000800 */

+#define RTC_ALRMBR_MSK1_Pos            (7U)

+#define RTC_ALRMBR_MSK1_Msk            (0x1UL << RTC_ALRMBR_MSK1_Pos)          /*!< 0x00000080 */

+#define RTC_ALRMBR_MSK1                RTC_ALRMBR_MSK1_Msk

+#define RTC_ALRMBR_ST_Pos              (4U)

+#define RTC_ALRMBR_ST_Msk              (0x7UL << RTC_ALRMBR_ST_Pos)            /*!< 0x00000070 */

+#define RTC_ALRMBR_ST                  RTC_ALRMBR_ST_Msk

+#define RTC_ALRMBR_ST_0                (0x1UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000010 */

+#define RTC_ALRMBR_ST_1                (0x2UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000020 */

+#define RTC_ALRMBR_ST_2                (0x4UL << RTC_ALRMBR_ST_Pos)             /*!< 0x00000040 */

+#define RTC_ALRMBR_SU_Pos              (0U)

+#define RTC_ALRMBR_SU_Msk              (0xFUL << RTC_ALRMBR_SU_Pos)            /*!< 0x0000000F */

+#define RTC_ALRMBR_SU                  RTC_ALRMBR_SU_Msk

+#define RTC_ALRMBR_SU_0                (0x1UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000001 */

+#define RTC_ALRMBR_SU_1                (0x2UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000002 */

+#define RTC_ALRMBR_SU_2                (0x4UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000004 */

+#define RTC_ALRMBR_SU_3                (0x8UL << RTC_ALRMBR_SU_Pos)             /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_WPR register  ******************/

+#define RTC_WPR_KEY_Pos                (0U)

+#define RTC_WPR_KEY_Msk                (0xFFUL << RTC_WPR_KEY_Pos)             /*!< 0x000000FF */

+#define RTC_WPR_KEY                    RTC_WPR_KEY_Msk

+

+/********************  Bits definition for RTC_SSR register  ******************/

+#define RTC_SSR_SS_Pos                 (0U)

+#define RTC_SSR_SS_Msk                 (0xFFFFUL << RTC_SSR_SS_Pos)            /*!< 0x0000FFFF */

+#define RTC_SSR_SS                     RTC_SSR_SS_Msk

+

+/********************  Bits definition for RTC_SHIFTR register  ***************/

+#define RTC_SHIFTR_SUBFS_Pos           (0U)

+#define RTC_SHIFTR_SUBFS_Msk           (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos)      /*!< 0x00007FFF */

+#define RTC_SHIFTR_SUBFS               RTC_SHIFTR_SUBFS_Msk

+#define RTC_SHIFTR_ADD1S_Pos           (31U)

+#define RTC_SHIFTR_ADD1S_Msk           (0x1UL << RTC_SHIFTR_ADD1S_Pos)         /*!< 0x80000000 */

+#define RTC_SHIFTR_ADD1S               RTC_SHIFTR_ADD1S_Msk

+

+/********************  Bits definition for RTC_TSTR register  *****************/

+#define RTC_TSTR_PM_Pos                (22U)

+#define RTC_TSTR_PM_Msk                (0x1UL << RTC_TSTR_PM_Pos)              /*!< 0x00400000 */

+#define RTC_TSTR_PM                    RTC_TSTR_PM_Msk

+#define RTC_TSTR_HT_Pos                (20U)

+#define RTC_TSTR_HT_Msk                (0x3UL << RTC_TSTR_HT_Pos)              /*!< 0x00300000 */

+#define RTC_TSTR_HT                    RTC_TSTR_HT_Msk

+#define RTC_TSTR_HT_0                  (0x1UL << RTC_TSTR_HT_Pos)               /*!< 0x00100000 */

+#define RTC_TSTR_HT_1                  (0x2UL << RTC_TSTR_HT_Pos)               /*!< 0x00200000 */

+#define RTC_TSTR_HU_Pos                (16U)

+#define RTC_TSTR_HU_Msk                (0xFUL << RTC_TSTR_HU_Pos)              /*!< 0x000F0000 */

+#define RTC_TSTR_HU                    RTC_TSTR_HU_Msk

+#define RTC_TSTR_HU_0                  (0x1UL << RTC_TSTR_HU_Pos)               /*!< 0x00010000 */

+#define RTC_TSTR_HU_1                  (0x2UL << RTC_TSTR_HU_Pos)               /*!< 0x00020000 */

+#define RTC_TSTR_HU_2                  (0x4UL << RTC_TSTR_HU_Pos)               /*!< 0x00040000 */

+#define RTC_TSTR_HU_3                  (0x8UL << RTC_TSTR_HU_Pos)               /*!< 0x00080000 */

+#define RTC_TSTR_MNT_Pos               (12U)

+#define RTC_TSTR_MNT_Msk               (0x7UL << RTC_TSTR_MNT_Pos)             /*!< 0x00007000 */

+#define RTC_TSTR_MNT                   RTC_TSTR_MNT_Msk

+#define RTC_TSTR_MNT_0                 (0x1UL << RTC_TSTR_MNT_Pos)              /*!< 0x00001000 */

+#define RTC_TSTR_MNT_1                 (0x2UL << RTC_TSTR_MNT_Pos)              /*!< 0x00002000 */

+#define RTC_TSTR_MNT_2                 (0x4UL << RTC_TSTR_MNT_Pos)              /*!< 0x00004000 */

+#define RTC_TSTR_MNU_Pos               (8U)

+#define RTC_TSTR_MNU_Msk               (0xFUL << RTC_TSTR_MNU_Pos)             /*!< 0x00000F00 */

+#define RTC_TSTR_MNU                   RTC_TSTR_MNU_Msk

+#define RTC_TSTR_MNU_0                 (0x1UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000100 */

+#define RTC_TSTR_MNU_1                 (0x2UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000200 */

+#define RTC_TSTR_MNU_2                 (0x4UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000400 */

+#define RTC_TSTR_MNU_3                 (0x8UL << RTC_TSTR_MNU_Pos)              /*!< 0x00000800 */

+#define RTC_TSTR_ST_Pos                (4U)

+#define RTC_TSTR_ST_Msk                (0x7UL << RTC_TSTR_ST_Pos)              /*!< 0x00000070 */

+#define RTC_TSTR_ST                    RTC_TSTR_ST_Msk

+#define RTC_TSTR_ST_0                  (0x1UL << RTC_TSTR_ST_Pos)               /*!< 0x00000010 */

+#define RTC_TSTR_ST_1                  (0x2UL << RTC_TSTR_ST_Pos)               /*!< 0x00000020 */

+#define RTC_TSTR_ST_2                  (0x4UL << RTC_TSTR_ST_Pos)               /*!< 0x00000040 */

+#define RTC_TSTR_SU_Pos                (0U)

+#define RTC_TSTR_SU_Msk                (0xFUL << RTC_TSTR_SU_Pos)              /*!< 0x0000000F */

+#define RTC_TSTR_SU                    RTC_TSTR_SU_Msk

+#define RTC_TSTR_SU_0                  (0x1UL << RTC_TSTR_SU_Pos)               /*!< 0x00000001 */

+#define RTC_TSTR_SU_1                  (0x2UL << RTC_TSTR_SU_Pos)               /*!< 0x00000002 */

+#define RTC_TSTR_SU_2                  (0x4UL << RTC_TSTR_SU_Pos)               /*!< 0x00000004 */

+#define RTC_TSTR_SU_3                  (0x8UL << RTC_TSTR_SU_Pos)               /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_TSDR register  *****************/

+#define RTC_TSDR_WDU_Pos               (13U)

+#define RTC_TSDR_WDU_Msk               (0x7UL << RTC_TSDR_WDU_Pos)             /*!< 0x0000E000 */

+#define RTC_TSDR_WDU                   RTC_TSDR_WDU_Msk

+#define RTC_TSDR_WDU_0                 (0x1UL << RTC_TSDR_WDU_Pos)              /*!< 0x00002000 */

+#define RTC_TSDR_WDU_1                 (0x2UL << RTC_TSDR_WDU_Pos)              /*!< 0x00004000 */

+#define RTC_TSDR_WDU_2                 (0x4UL << RTC_TSDR_WDU_Pos)              /*!< 0x00008000 */

+#define RTC_TSDR_MT_Pos                (12U)

+#define RTC_TSDR_MT_Msk                (0x1UL << RTC_TSDR_MT_Pos)              /*!< 0x00001000 */

+#define RTC_TSDR_MT                    RTC_TSDR_MT_Msk

+#define RTC_TSDR_MU_Pos                (8U)

+#define RTC_TSDR_MU_Msk                (0xFUL << RTC_TSDR_MU_Pos)              /*!< 0x00000F00 */

+#define RTC_TSDR_MU                    RTC_TSDR_MU_Msk

+#define RTC_TSDR_MU_0                  (0x1UL << RTC_TSDR_MU_Pos)               /*!< 0x00000100 */

+#define RTC_TSDR_MU_1                  (0x2UL << RTC_TSDR_MU_Pos)               /*!< 0x00000200 */

+#define RTC_TSDR_MU_2                  (0x4UL << RTC_TSDR_MU_Pos)               /*!< 0x00000400 */

+#define RTC_TSDR_MU_3                  (0x8UL << RTC_TSDR_MU_Pos)               /*!< 0x00000800 */

+#define RTC_TSDR_DT_Pos                (4U)

+#define RTC_TSDR_DT_Msk                (0x3UL << RTC_TSDR_DT_Pos)              /*!< 0x00000030 */

+#define RTC_TSDR_DT                    RTC_TSDR_DT_Msk

+#define RTC_TSDR_DT_0                  (0x1UL << RTC_TSDR_DT_Pos)               /*!< 0x00000010 */

+#define RTC_TSDR_DT_1                  (0x2UL << RTC_TSDR_DT_Pos)               /*!< 0x00000020 */

+#define RTC_TSDR_DU_Pos                (0U)

+#define RTC_TSDR_DU_Msk                (0xFUL << RTC_TSDR_DU_Pos)              /*!< 0x0000000F */

+#define RTC_TSDR_DU                    RTC_TSDR_DU_Msk

+#define RTC_TSDR_DU_0                  (0x1UL << RTC_TSDR_DU_Pos)               /*!< 0x00000001 */

+#define RTC_TSDR_DU_1                  (0x2UL << RTC_TSDR_DU_Pos)               /*!< 0x00000002 */

+#define RTC_TSDR_DU_2                  (0x4UL << RTC_TSDR_DU_Pos)               /*!< 0x00000004 */

+#define RTC_TSDR_DU_3                  (0x8UL << RTC_TSDR_DU_Pos)               /*!< 0x00000008 */

+

+/********************  Bits definition for RTC_TSSSR register  ****************/

+#define RTC_TSSSR_SS_Pos               (0U)

+#define RTC_TSSSR_SS_Msk               (0xFFFFUL << RTC_TSSSR_SS_Pos)          /*!< 0x0000FFFF */

+#define RTC_TSSSR_SS                   RTC_TSSSR_SS_Msk

+

+/********************  Bits definition for RTC_CALR register  *****************/

+#define RTC_CALR_CALP_Pos              (15U)

+#define RTC_CALR_CALP_Msk              (0x1UL << RTC_CALR_CALP_Pos)            /*!< 0x00008000 */

+#define RTC_CALR_CALP                  RTC_CALR_CALP_Msk

+#define RTC_CALR_CALW8_Pos             (14U)

+#define RTC_CALR_CALW8_Msk             (0x1UL << RTC_CALR_CALW8_Pos)           /*!< 0x00004000 */

+#define RTC_CALR_CALW8                 RTC_CALR_CALW8_Msk

+#define RTC_CALR_CALW16_Pos            (13U)

+#define RTC_CALR_CALW16_Msk            (0x1UL << RTC_CALR_CALW16_Pos)          /*!< 0x00002000 */

+#define RTC_CALR_CALW16                RTC_CALR_CALW16_Msk

+#define RTC_CALR_CALM_Pos              (0U)

+#define RTC_CALR_CALM_Msk              (0x1FFUL << RTC_CALR_CALM_Pos)          /*!< 0x000001FF */

+#define RTC_CALR_CALM                  RTC_CALR_CALM_Msk

+#define RTC_CALR_CALM_0                (0x001UL << RTC_CALR_CALM_Pos)           /*!< 0x00000001 */

+#define RTC_CALR_CALM_1                (0x002UL << RTC_CALR_CALM_Pos)           /*!< 0x00000002 */

+#define RTC_CALR_CALM_2                (0x004UL << RTC_CALR_CALM_Pos)           /*!< 0x00000004 */

+#define RTC_CALR_CALM_3                (0x008UL << RTC_CALR_CALM_Pos)           /*!< 0x00000008 */

+#define RTC_CALR_CALM_4                (0x010UL << RTC_CALR_CALM_Pos)           /*!< 0x00000010 */

+#define RTC_CALR_CALM_5                (0x020UL << RTC_CALR_CALM_Pos)           /*!< 0x00000020 */

+#define RTC_CALR_CALM_6                (0x040UL << RTC_CALR_CALM_Pos)           /*!< 0x00000040 */

+#define RTC_CALR_CALM_7                (0x080UL << RTC_CALR_CALM_Pos)           /*!< 0x00000080 */

+#define RTC_CALR_CALM_8                (0x100UL << RTC_CALR_CALM_Pos)           /*!< 0x00000100 */

+

+

+/********************  Bits definition for RTC_ALRMASSR register  *************/

+#define RTC_ALRMASSR_MASKSS_Pos        (24U)

+#define RTC_ALRMASSR_MASKSS_Msk        (0xFUL << RTC_ALRMASSR_MASKSS_Pos)      /*!< 0x0F000000 */

+#define RTC_ALRMASSR_MASKSS            RTC_ALRMASSR_MASKSS_Msk

+#define RTC_ALRMASSR_MASKSS_0          (0x1UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x01000000 */

+#define RTC_ALRMASSR_MASKSS_1          (0x2UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x02000000 */

+#define RTC_ALRMASSR_MASKSS_2          (0x4UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x04000000 */

+#define RTC_ALRMASSR_MASKSS_3          (0x8UL << RTC_ALRMASSR_MASKSS_Pos)       /*!< 0x08000000 */

+#define RTC_ALRMASSR_SS_Pos            (0U)

+#define RTC_ALRMASSR_SS_Msk            (0x7FFFUL << RTC_ALRMASSR_SS_Pos)       /*!< 0x00007FFF */

+#define RTC_ALRMASSR_SS                RTC_ALRMASSR_SS_Msk

+

+/********************  Bits definition for RTC_ALRMBSSR register  *************/

+#define RTC_ALRMBSSR_MASKSS_Pos        (24U)

+#define RTC_ALRMBSSR_MASKSS_Msk        (0xFUL << RTC_ALRMBSSR_MASKSS_Pos)      /*!< 0x0F000000 */

+#define RTC_ALRMBSSR_MASKSS            RTC_ALRMBSSR_MASKSS_Msk

+#define RTC_ALRMBSSR_MASKSS_0          (0x1UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x01000000 */

+#define RTC_ALRMBSSR_MASKSS_1          (0x2UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x02000000 */

+#define RTC_ALRMBSSR_MASKSS_2          (0x4UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x04000000 */

+#define RTC_ALRMBSSR_MASKSS_3          (0x8UL << RTC_ALRMBSSR_MASKSS_Pos)       /*!< 0x08000000 */

+#define RTC_ALRMBSSR_SS_Pos            (0U)

+#define RTC_ALRMBSSR_SS_Msk            (0x7FFFUL << RTC_ALRMBSSR_SS_Pos)       /*!< 0x00007FFF */

+#define RTC_ALRMBSSR_SS                RTC_ALRMBSSR_SS_Msk

+

+

+/********************  Bits definition for RTC_SR register  *******************/

+#define RTC_SR_ITSF_Pos              (5U)

+#define RTC_SR_ITSF_Msk              (0x1UL << RTC_SR_ITSF_Pos)                 /*!< 0x00000020 */

+#define RTC_SR_ITSF                  RTC_SR_ITSF_Msk

+#define RTC_SR_TSOVF_Pos             (4U)

+#define RTC_SR_TSOVF_Msk             (0x1UL << RTC_SR_TSOVF_Pos)                /*!< 0x00000010 */

+#define RTC_SR_TSOVF                 RTC_SR_TSOVF_Msk

+#define RTC_SR_TSF_Pos               (3U)

+#define RTC_SR_TSF_Msk               (0x1UL << RTC_SR_TSF_Pos)                  /*!< 0x00000008 */

+#define RTC_SR_TSF                   RTC_SR_TSF_Msk

+#define RTC_SR_WUTF_Pos              (2U)

+#define RTC_SR_WUTF_Msk              (0x1UL << RTC_SR_WUTF_Pos)                 /*!< 0x00000004 */

+#define RTC_SR_WUTF                  RTC_SR_WUTF_Msk

+#define RTC_SR_ALRBF_Pos             (1U)

+#define RTC_SR_ALRBF_Msk             (0x1UL << RTC_SR_ALRBF_Pos)                /*!< 0x00000002 */

+#define RTC_SR_ALRBF                 RTC_SR_ALRBF_Msk

+#define RTC_SR_ALRAF_Pos             (0U)

+#define RTC_SR_ALRAF_Msk             (0x1UL << RTC_SR_ALRAF_Pos)                /*!< 0x00000001 */

+#define RTC_SR_ALRAF                 RTC_SR_ALRAF_Msk

+

+/********************  Bits definition for RTC_MISR register  *****************/

+#define RTC_MISR_ITSMF_Pos           (5U)

+#define RTC_MISR_ITSMF_Msk           (0x1UL << RTC_MISR_ITSMF_Pos)              /*!< 0x00000020 */

+#define RTC_MISR_ITSMF               RTC_MISR_ITSMF_Msk

+#define RTC_MISR_TSOVMF_Pos          (4U)

+#define RTC_MISR_TSOVMF_Msk          (0x1UL << RTC_MISR_TSOVMF_Pos)             /*!< 0x00000010 */

+#define RTC_MISR_TSOVMF              RTC_MISR_TSOVMF_Msk

+#define RTC_MISR_TSMF_Pos            (3U)

+#define RTC_MISR_TSMF_Msk            (0x1UL << RTC_MISR_TSMF_Pos)               /*!< 0x00000008 */

+#define RTC_MISR_TSMF                RTC_MISR_TSMF_Msk

+#define RTC_MISR_WUTMF_Pos           (2U)

+#define RTC_MISR_WUTMF_Msk           (0x1UL << RTC_MISR_WUTMF_Pos)              /*!< 0x00000004 */

+#define RTC_MISR_WUTMF               RTC_MISR_WUTMF_Msk

+#define RTC_MISR_ALRBMF_Pos          (1U)

+#define RTC_MISR_ALRBMF_Msk          (0x1UL << RTC_MISR_ALRBMF_Pos)             /*!< 0x00000002 */

+#define RTC_MISR_ALRBMF              RTC_MISR_ALRBMF_Msk

+#define RTC_MISR_ALRAMF_Pos          (0U)

+#define RTC_MISR_ALRAMF_Msk          (0x1UL << RTC_MISR_ALRAMF_Pos)             /*!< 0x00000001 */

+#define RTC_MISR_ALRAMF              RTC_MISR_ALRAMF_Msk

+

+/********************  Bits definition for RTC_SCR register  ******************/

+#define RTC_SCR_CITSF_Pos            (5U)

+#define RTC_SCR_CITSF_Msk            (0x1UL << RTC_SCR_CITSF_Pos)               /*!< 0x00000020 */

+#define RTC_SCR_CITSF                RTC_SCR_CITSF_Msk

+#define RTC_SCR_CTSOVF_Pos           (4U)

+#define RTC_SCR_CTSOVF_Msk           (0x1UL << RTC_SCR_CTSOVF_Pos)              /*!< 0x00000010 */

+#define RTC_SCR_CTSOVF               RTC_SCR_CTSOVF_Msk

+#define RTC_SCR_CTSF_Pos             (3U)

+#define RTC_SCR_CTSF_Msk             (0x1UL << RTC_SCR_CTSF_Pos)                /*!< 0x00000008 */

+#define RTC_SCR_CTSF                 RTC_SCR_CTSF_Msk

+#define RTC_SCR_CWUTF_Pos            (2U)

+#define RTC_SCR_CWUTF_Msk            (0x1UL << RTC_SCR_CWUTF_Pos)               /*!< 0x00000004 */

+#define RTC_SCR_CWUTF                RTC_SCR_CWUTF_Msk

+#define RTC_SCR_CALRBF_Pos           (1U)

+#define RTC_SCR_CALRBF_Msk           (0x1UL << RTC_SCR_CALRBF_Pos)              /*!< 0x00000002 */

+#define RTC_SCR_CALRBF               RTC_SCR_CALRBF_Msk

+#define RTC_SCR_CALRAF_Pos           (0U)

+#define RTC_SCR_CALRAF_Msk           (0x1UL << RTC_SCR_CALRAF_Pos)              /*!< 0x00000001 */

+#define RTC_SCR_CALRAF               RTC_SCR_CALRAF_Msk

+

+/******************************************************************************/

+/*                                                                            */

+/*                     Tamper and backup register (TAMP)                      */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bits definition for TAMP_CR1 register  *****************/

+#define TAMP_CR1_TAMP1E_Pos          (0U)

+#define TAMP_CR1_TAMP1E_Msk          (0x1UL << TAMP_CR1_TAMP1E_Pos)            /*!< 0x00000001 */

+#define TAMP_CR1_TAMP1E              TAMP_CR1_TAMP1E_Msk

+#define TAMP_CR1_TAMP2E_Pos          (1U)

+#define TAMP_CR1_TAMP2E_Msk          (0x1UL << TAMP_CR1_TAMP2E_Pos)            /*!< 0x00000002 */

+#define TAMP_CR1_TAMP2E              TAMP_CR1_TAMP2E_Msk

+#define TAMP_CR1_TAMP3E_Pos          (2U)

+#define TAMP_CR1_TAMP3E_Msk          (0x1UL << TAMP_CR1_TAMP3E_Pos)            /*!< 0x00000004 */

+#define TAMP_CR1_TAMP3E              TAMP_CR1_TAMP3E_Msk

+#define TAMP_CR1_ITAMP1E_Pos         (16U)

+#define TAMP_CR1_ITAMP1E_Msk         (0x1UL << TAMP_CR1_ITAMP1E_Pos)           /*!< 0x00010000 */

+#define TAMP_CR1_ITAMP1E             TAMP_CR1_ITAMP1E_Msk

+#define TAMP_CR1_ITAMP2E_Pos         (17U)

+#define TAMP_CR1_ITAMP2E_Msk         (0x1UL << TAMP_CR1_ITAMP2E_Pos)           /*!< 0x00020000 */

+#define TAMP_CR1_ITAMP2E             TAMP_CR1_ITAMP2E_Msk

+#define TAMP_CR1_ITAMP3E_Pos         (18U)

+#define TAMP_CR1_ITAMP3E_Msk         (0x1UL << TAMP_CR1_ITAMP3E_Pos)           /*!< 0x00040000 */

+#define TAMP_CR1_ITAMP3E             TAMP_CR1_ITAMP3E_Msk

+#define TAMP_CR1_ITAMP4E_Pos         (19U)

+#define TAMP_CR1_ITAMP4E_Msk         (0x1UL << TAMP_CR1_ITAMP4E_Pos)           /*!< 0x00080000 */

+#define TAMP_CR1_ITAMP4E             TAMP_CR1_ITAMP4E_Msk

+#define TAMP_CR1_ITAMP5E_Pos         (20U)

+#define TAMP_CR1_ITAMP5E_Msk         (0x1UL << TAMP_CR1_ITAMP5E_Pos)           /*!< 0x00100000 */

+#define TAMP_CR1_ITAMP5E             TAMP_CR1_ITAMP5E_Msk

+#define TAMP_CR1_ITAMP6E_Pos         (21U)

+#define TAMP_CR1_ITAMP6E_Msk         (0x1UL << TAMP_CR1_ITAMP6E_Pos)           /*!< 0x00200000 */

+#define TAMP_CR1_ITAMP6E             TAMP_CR1_ITAMP6E_Msk

+#define TAMP_CR1_ITAMP8E_Pos         (23U)

+#define TAMP_CR1_ITAMP8E_Msk         (0x1UL << TAMP_CR1_ITAMP8E_Pos)           /*!< 0x00800000 */

+#define TAMP_CR1_ITAMP8E             TAMP_CR1_ITAMP8E_Msk

+

+/********************  Bits definition for TAMP_CR2 register  *****************/

+#define TAMP_CR2_TAMP1NOERASE_Pos    (0U)

+#define TAMP_CR2_TAMP1NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos)      /*!< 0x00000001 */

+#define TAMP_CR2_TAMP1NOERASE        TAMP_CR2_TAMP1NOERASE_Msk

+#define TAMP_CR2_TAMP2NOERASE_Pos    (1U)

+#define TAMP_CR2_TAMP2NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos)      /*!< 0x00000002 */

+#define TAMP_CR2_TAMP2NOERASE        TAMP_CR2_TAMP2NOERASE_Msk

+#define TAMP_CR2_TAMP3NOERASE_Pos    (2U)

+#define TAMP_CR2_TAMP3NOERASE_Msk    (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos)      /*!< 0x00000004 */

+#define TAMP_CR2_TAMP3NOERASE        TAMP_CR2_TAMP3NOERASE_Msk

+#define TAMP_CR2_TAMP1MSK_Pos        (16U)

+#define TAMP_CR2_TAMP1MSK_Msk        (0x1UL << TAMP_CR2_TAMP1MSK_Pos)          /*!< 0x00010000 */

+#define TAMP_CR2_TAMP1MSK            TAMP_CR2_TAMP1MSK_Msk

+#define TAMP_CR2_TAMP2MSK_Pos        (17U)

+#define TAMP_CR2_TAMP2MSK_Msk        (0x1UL << TAMP_CR2_TAMP2MSK_Pos)          /*!< 0x00020000 */

+#define TAMP_CR2_TAMP2MSK            TAMP_CR2_TAMP2MSK_Msk

+#define TAMP_CR2_TAMP3MSK_Pos        (18U)

+#define TAMP_CR2_TAMP3MSK_Msk        (0x1UL << TAMP_CR2_TAMP3MSK_Pos)          /*!< 0x00040000 */

+#define TAMP_CR2_TAMP3MSK            TAMP_CR2_TAMP3MSK_Msk

+#define TAMP_CR2_TAMP1TRG_Pos        (24U)

+#define TAMP_CR2_TAMP1TRG_Msk        (0x1UL << TAMP_CR2_TAMP1TRG_Pos)          /*!< 0x01000000 */

+#define TAMP_CR2_TAMP1TRG            TAMP_CR2_TAMP1TRG_Msk

+#define TAMP_CR2_TAMP2TRG_Pos        (25U)

+#define TAMP_CR2_TAMP2TRG_Msk        (0x1UL << TAMP_CR2_TAMP2TRG_Pos)          /*!< 0x02000000 */

+#define TAMP_CR2_TAMP2TRG            TAMP_CR2_TAMP2TRG_Msk

+#define TAMP_CR2_TAMP3TRG_Pos        (26U)

+#define TAMP_CR2_TAMP3TRG_Msk        (0x1UL << TAMP_CR2_TAMP3TRG_Pos)          /*!< 0x04000000 */

+#define TAMP_CR2_TAMP3TRG            TAMP_CR2_TAMP3TRG_Msk

+

+/********************  Bits definition for TAMP_FLTCR register  ***************/

+#define TAMP_FLTCR_TAMPFREQ_Pos      (0U)

+#define TAMP_FLTCR_TAMPFREQ_Msk      (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000007 */

+#define TAMP_FLTCR_TAMPFREQ          TAMP_FLTCR_TAMPFREQ_Msk

+#define TAMP_FLTCR_TAMPFREQ_0        (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000001 */

+#define TAMP_FLTCR_TAMPFREQ_1        (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000002 */

+#define TAMP_FLTCR_TAMPFREQ_2        (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos)         /*!< 0x00000004 */

+#define TAMP_FLTCR_TAMPFLT_Pos       (3U)

+#define TAMP_FLTCR_TAMPFLT_Msk       (0x3UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000018 */

+#define TAMP_FLTCR_TAMPFLT           TAMP_FLTCR_TAMPFLT_Msk

+#define TAMP_FLTCR_TAMPFLT_0         (0x1UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000008 */

+#define TAMP_FLTCR_TAMPFLT_1         (0x2UL << TAMP_FLTCR_TAMPFLT_Pos)          /*!< 0x00000010 */

+#define TAMP_FLTCR_TAMPPRCH_Pos      (5U)

+#define TAMP_FLTCR_TAMPPRCH_Msk      (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000060 */

+#define TAMP_FLTCR_TAMPPRCH          TAMP_FLTCR_TAMPPRCH_Msk

+#define TAMP_FLTCR_TAMPPRCH_0        (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000020 */

+#define TAMP_FLTCR_TAMPPRCH_1        (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos)         /*!< 0x00000040 */

+#define TAMP_FLTCR_TAMPPUDIS_Pos     (7U)

+#define TAMP_FLTCR_TAMPPUDIS_Msk     (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos)        /*!< 0x00000080 */

+#define TAMP_FLTCR_TAMPPUDIS         TAMP_FLTCR_TAMPPUDIS_Msk

+

+/*******************  Bits definition for TAMP_ATCR1 register  ****************/

+#define TAMP_ATCR1_TAMP1AM_Pos       (0U)

+#define TAMP_ATCR1_TAMP1AM_Msk       (0x1UL << TAMP_ATCR1_TAMP1AM_Pos)         /*!< 0x00000001 */

+#define TAMP_ATCR1_TAMP1AM           TAMP_ATCR1_TAMP1AM_Msk

+#define TAMP_ATCR1_TAMP2AM_Pos       (1U)

+#define TAMP_ATCR1_TAMP2AM_Msk       (0x1UL << TAMP_ATCR1_TAMP2AM_Pos)         /*!< 0x00000002 */

+#define TAMP_ATCR1_TAMP2AM           TAMP_ATCR1_TAMP2AM_Msk

+#define TAMP_ATCR1_TAMP3AM_Pos       (2U)

+#define TAMP_ATCR1_TAMP3AM_Msk       (0x1UL << TAMP_ATCR1_TAMP3AM_Pos)         /*!< 0x00000004 */

+#define TAMP_ATCR1_TAMP3AM           TAMP_ATCR1_TAMP3AM_Msk

+#define TAMP_ATCR1_ATOSEL1_Pos       (8U)

+#define TAMP_ATCR1_ATOSEL1_Msk       (0x3UL << TAMP_ATCR1_ATOSEL1_Pos)          /*!< 0x00000300 */

+#define TAMP_ATCR1_ATOSEL1            TAMP_ATCR1_ATOSEL1_Msk

+#define TAMP_ATCR1_ATOSEL1_0         (0x1UL << TAMP_ATCR1_ATOSEL1_Pos)         /*!< 0x00000100 */

+#define TAMP_ATCR1_ATOSEL1_1         (0x2UL << TAMP_ATCR1_ATOSEL1_Pos)         /*!< 0x00000200 */

+#define TAMP_ATCR1_ATOSEL2_Pos       (10U)

+#define TAMP_ATCR1_ATOSEL2_Msk       (0x3UL << TAMP_ATCR1_ATOSEL2_Pos)          /*!< 0x00000C00 */

+#define TAMP_ATCR1_ATOSEL2            TAMP_ATCR1_ATOSEL2_Msk

+#define TAMP_ATCR1_ATOSEL2_0         (0x1UL << TAMP_ATCR1_ATOSEL2_Pos)         /*!< 0x00000400 */

+#define TAMP_ATCR1_ATOSEL2_1         (0x2UL << TAMP_ATCR1_ATOSEL2_Pos)         /*!< 0x00000800 */

+#define TAMP_ATCR1_ATOSEL3_Pos       (12U)

+#define TAMP_ATCR1_ATOSEL3_Msk       (0x3UL << TAMP_ATCR1_ATOSEL3_Pos)          /*!< 0x00003000 */

+#define TAMP_ATCR1_ATOSEL3            TAMP_ATCR1_ATOSEL3_Msk

+#define TAMP_ATCR1_ATOSEL3_0         (0x1UL << TAMP_ATCR1_ATOSEL3_Pos)         /*!< 0x00001000 */

+#define TAMP_ATCR1_ATOSEL3_1         (0x2UL << TAMP_ATCR1_ATOSEL3_Pos)         /*!< 0x00002000 */

+#define TAMP_ATCR1_ATOSEL4_Pos       (14U)

+#define TAMP_ATCR1_ATOSEL4_Msk       (0x3UL << TAMP_ATCR1_ATOSEL4_Pos)          /*!< 0x0000C000 */

+#define TAMP_ATCR1_ATOSEL4            TAMP_ATCR1_ATOSEL4_Msk

+#define TAMP_ATCR1_ATOSEL4_0         (0x1UL << TAMP_ATCR1_ATOSEL4_Pos)         /*!< 0x00004000 */

+#define TAMP_ATCR1_ATOSEL4_1         (0x2UL << TAMP_ATCR1_ATOSEL4_Pos)         /*!< 0x00008000 */

+#define TAMP_ATCR1_ATCKSEL_Pos       (16U)

+#define TAMP_ATCR1_ATCKSEL_Msk       (0x7UL << TAMP_ATCR1_ATCKSEL_Pos)          /*!< 0x00070000 */

+#define TAMP_ATCR1_ATCKSEL            TAMP_ATCR1_ATCKSEL_Msk

+#define TAMP_ATCR1_ATCKSEL_0         (0x1UL << TAMP_ATCR1_ATCKSEL_Pos)         /*!< 0x00010000 */

+#define TAMP_ATCR1_ATCKSEL_1         (0x2UL << TAMP_ATCR1_ATCKSEL_Pos)         /*!< 0x00020000 */

+#define TAMP_ATCR1_ATCKSEL_2         (0x4UL << TAMP_ATCR1_ATCKSEL_Pos)         /*!< 0x00040000 */

+#define TAMP_ATCR1_ATPER_Pos         (24U)

+#define TAMP_ATCR1_ATPER_Msk         (0x7UL << TAMP_ATCR1_ATPER_Pos)           /*!< 0x07000000 */

+#define TAMP_ATCR1_ATPER             TAMP_ATCR1_ATPER_Msk

+#define TAMP_ATCR1_ATOSHARE_Pos      (30U)

+#define TAMP_ATCR1_ATOSHARE_Msk      (0x1UL << TAMP_ATCR1_ATOSHARE_Pos)        /*!< 0x40000000 */

+#define TAMP_ATCR1_ATOSHARE          TAMP_ATCR1_ATOSHARE_Msk

+#define TAMP_ATCR1_FLTEN_Pos         (31U)

+#define TAMP_ATCR1_FLTEN_Msk         (0x1UL << TAMP_ATCR1_FLTEN_Pos)           /*!< 0x80000000 */

+#define TAMP_ATCR1_FLTEN             TAMP_ATCR1_FLTEN_Msk

+

+/********************  Bits definition for TAMP_ATSEEDR register  *************/

+#define TAMP_ATSEEDR_SEED_Pos        (0U)

+#define TAMP_ATSEEDR_SEED_Msk        (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos)   /*!< 0xFFFFFFFF */

+#define TAMP_ATSEEDR_SEED            TAMP_ATSEEDR_SEED_Msk

+

+/********************  Bits definition for TAMP_ATOR register  ****************/

+#define TAMP_ATOR_PRNG_Pos           (0U)

+#define TAMP_ATOR_PRNG_Msk           (0x000000FFUL << TAMP_ATOR_PRNG_Pos)      /*!< 0x000000FF */

+#define TAMP_ATOR_PRNG               TAMP_ATOR_PRNG_Msk

+#define TAMP_ATOR_SEEDF_Pos          (14U)

+#define TAMP_ATOR_SEEDF_Msk          (0x01UL << TAMP_ATOR_SEEDF_Pos)           /*!< 0x00004000 */

+#define TAMP_ATOR_SEEDF              TAMP_ATOR_SEEDF_Msk

+#define TAMP_ATOR_INITS_Pos          (15U)

+#define TAMP_ATOR_INITS_Msk          (0x01UL << TAMP_ATOR_INITS_Pos)           /*!< 0x00008000 */

+#define TAMP_ATOR_INITS              TAMP_ATOR_INITS_Msk

+

+/********************  Bits definition for TAMP_IER register  *****************/

+#define TAMP_IER_TAMP1IE_Pos         (0U)

+#define TAMP_IER_TAMP1IE_Msk         (0x1UL << TAMP_IER_TAMP1IE_Pos)           /*!< 0x00000001 */

+#define TAMP_IER_TAMP1IE             TAMP_IER_TAMP1IE_Msk

+#define TAMP_IER_TAMP2IE_Pos         (1U)

+#define TAMP_IER_TAMP2IE_Msk         (0x1UL << TAMP_IER_TAMP2IE_Pos)           /*!< 0x00000002 */

+#define TAMP_IER_TAMP2IE             TAMP_IER_TAMP2IE_Msk

+#define TAMP_IER_TAMP3IE_Pos         (2U)

+#define TAMP_IER_TAMP3IE_Msk         (0x1UL << TAMP_IER_TAMP3IE_Pos)           /*!< 0x00000004 */

+#define TAMP_IER_TAMP3IE             TAMP_IER_TAMP3IE_Msk

+#define TAMP_IER_ITAMP1IE_Pos        (16U)

+#define TAMP_IER_ITAMP1IE_Msk        (0x1UL << TAMP_IER_ITAMP1IE_Pos)          /*!< 0x00010000 */

+#define TAMP_IER_ITAMP1IE            TAMP_IER_ITAMP1IE_Msk

+#define TAMP_IER_ITAMP2IE_Pos        (17U)

+#define TAMP_IER_ITAMP2IE_Msk        (0x1UL << TAMP_IER_ITAMP2IE_Pos)          /*!< 0x00020000 */

+#define TAMP_IER_ITAMP2IE            TAMP_IER_ITAMP2IE_Msk

+#define TAMP_IER_ITAMP3IE_Pos        (18U)

+#define TAMP_IER_ITAMP3IE_Msk        (0x1UL << TAMP_IER_ITAMP3IE_Pos)          /*!< 0x00040000 */

+#define TAMP_IER_ITAMP3IE            TAMP_IER_ITAMP3IE_Msk

+#define TAMP_IER_ITAMP4IE_Pos        (19U)

+#define TAMP_IER_ITAMP4IE_Msk        (0x1UL << TAMP_IER_ITAMP4IE_Pos)          /*!< 0x00080000 */

+#define TAMP_IER_ITAMP4IE            TAMP_IER_ITAMP4IE_Msk

+#define TAMP_IER_ITAMP5IE_Pos        (20U)

+#define TAMP_IER_ITAMP5IE_Msk        (0x1UL << TAMP_IER_ITAMP5IE_Pos)          /*!< 0x00100000 */

+#define TAMP_IER_ITAMP5IE            TAMP_IER_ITAMP5IE_Msk

+#define TAMP_IER_ITAMP6IE_Pos        (21U)

+#define TAMP_IER_ITAMP6IE_Msk        (0x1UL << TAMP_IER_ITAMP6IE_Pos)          /*!< 0x00200000 */

+#define TAMP_IER_ITAMP6IE            TAMP_IER_ITAMP6IE_Msk

+#define TAMP_IER_ITAMP8IE_Pos        (23U)

+#define TAMP_IER_ITAMP8IE_Msk        (0x1UL << TAMP_IER_ITAMP8IE_Pos)          /*!< 0x00800000 */

+#define TAMP_IER_ITAMP8IE            TAMP_IER_ITAMP8IE_Msk

+

+/********************  Bits definition for TAMP_SR register  *****************/

+#define TAMP_SR_TAMP1F_Pos           (0U)

+#define TAMP_SR_TAMP1F_Msk           (0x1UL << TAMP_SR_TAMP1F_Pos)             /*!< 0x00000001 */

+#define TAMP_SR_TAMP1F               TAMP_SR_TAMP1F_Msk

+#define TAMP_SR_TAMP2F_Pos           (1U)

+#define TAMP_SR_TAMP2F_Msk           (0x1UL << TAMP_SR_TAMP2F_Pos)             /*!< 0x00000002 */

+#define TAMP_SR_TAMP2F               TAMP_SR_TAMP2F_Msk

+#define TAMP_SR_TAMP3F_Pos           (2U)

+#define TAMP_SR_TAMP3F_Msk           (0x1UL << TAMP_SR_TAMP3F_Pos)             /*!< 0x00000004 */

+#define TAMP_SR_TAMP3F               TAMP_SR_TAMP3F_Msk

+#define TAMP_SR_ITAMP1F_Pos          (16U)

+#define TAMP_SR_ITAMP1F_Msk          (0x1UL << TAMP_SR_ITAMP1F_Pos)            /*!< 0x00010000 */

+#define TAMP_SR_ITAMP1F              TAMP_SR_ITAMP1F_Msk

+#define TAMP_SR_ITAMP2F_Pos          (17U)

+#define TAMP_SR_ITAMP2F_Msk          (0x1UL << TAMP_SR_ITAMP2F_Pos)            /*!< 0x00020000 */

+#define TAMP_SR_ITAMP2F              TAMP_SR_ITAMP2F_Msk

+#define TAMP_SR_ITAMP3F_Pos          (18U)

+#define TAMP_SR_ITAMP3F_Msk          (0x1UL << TAMP_SR_ITAMP3F_Pos)            /*!< 0x00040000 */

+#define TAMP_SR_ITAMP3F              TAMP_SR_ITAMP3F_Msk

+#define TAMP_SR_ITAMP4F_Pos          (19U)

+#define TAMP_SR_ITAMP4F_Msk          (0x1UL << TAMP_SR_ITAMP4F_Pos)            /*!< 0x00080000 */

+#define TAMP_SR_ITAMP4F              TAMP_SR_ITAMP4F_Msk

+#define TAMP_SR_ITAMP5F_Pos          (20U)

+#define TAMP_SR_ITAMP5F_Msk          (0x1UL << TAMP_SR_ITAMP5F_Pos)            /*!< 0x00100000 */

+#define TAMP_SR_ITAMP5F              TAMP_SR_ITAMP5F_Msk

+#define TAMP_SR_ITAMP6F_Pos          (21U)

+#define TAMP_SR_ITAMP6F_Msk          (0x1UL << TAMP_SR_ITAMP6F_Pos)            /*!< 0x00200000 */

+#define TAMP_SR_ITAMP6F              TAMP_SR_ITAMP6F_Msk

+#define TAMP_SR_ITAMP8F_Pos          (23U)

+#define TAMP_SR_ITAMP8F_Msk          (0x1UL << TAMP_SR_ITAMP8F_Pos)            /*!< 0x00800000 */

+#define TAMP_SR_ITAMP8F              TAMP_SR_ITAMP8F_Msk

+

+/********************  Bits definition for TAMP_MISR register  ************ *****/

+#define TAMP_MISR_TAMP1MF_Pos        (0U)

+#define TAMP_MISR_TAMP1MF_Msk        (0x1UL << TAMP_MISR_TAMP1MF_Pos)           /*!< 0x00000001 */

+#define TAMP_MISR_TAMP1MF            TAMP_MISR_TAMP1MF_Msk

+#define TAMP_MISR_TAMP2MF_Pos        (1U)

+#define TAMP_MISR_TAMP2MF_Msk        (0x1UL << TAMP_MISR_TAMP2MF_Pos)           /*!< 0x00000002 */

+#define TAMP_MISR_TAMP2MF            TAMP_MISR_TAMP2MF_Msk

+#define TAMP_MISR_TAMP3MF_Pos        (2U)

+#define TAMP_MISR_TAMP3MF_Msk        (0x1UL << TAMP_MISR_TAMP3MF_Pos)          /*!< 0x00000004 */

+#define TAMP_MISR_TAMP3MF            TAMP_MISR_TAMP3MF_Msk

+#define TAMP_MISR_ITAMP1MF_Pos       (16U)

+#define TAMP_MISR_ITAMP1MF_Msk       (0x1UL << TAMP_MISR_ITAMP1MF_Pos)         /*!< 0x00010000 */

+#define TAMP_MISR_ITAMP1MF           TAMP_MISR_ITAMP1MF_Msk

+#define TAMP_MISR_ITAMP2MF_Pos       (17U)

+#define TAMP_MISR_ITAMP2MF_Msk       (0x1UL << TAMP_MISR_ITAMP2MF_Pos)         /*!< 0x00020000 */

+#define TAMP_MISR_ITAMP2MF           TAMP_MISR_ITAMP2MF_Msk

+#define TAMP_MISR_ITAMP3MF_Pos       (18U)

+#define TAMP_MISR_ITAMP3MF_Msk       (0x1UL << TAMP_MISR_ITAMP3MF_Pos)         /*!< 0x00040000 */

+#define TAMP_MISR_ITAMP3MF           TAMP_MISR_ITAMP3MF_Msk

+#define TAMP_MISR_ITAMP4MF_Pos       (19U)

+#define TAMP_MISR_ITAMP4MF_Msk       (0x1UL << TAMP_MISR_ITAMP4MF_Pos)         /*!< 0x00080000 */

+#define TAMP_MISR_ITAMP4MF           TAMP_MISR_ITAMP4MF_Msk

+#define TAMP_MISR_ITAMP5MF_Pos       (20U)

+#define TAMP_MISR_ITAMP5MF_Msk       (0x1UL << TAMP_MISR_ITAMP5MF_Pos)         /*!< 0x00100000 */

+#define TAMP_MISR_ITAMP5MF           TAMP_MISR_ITAMP5MF_Msk

+#define TAMP_MISR_ITAMP6MF_Pos       (21U)

+#define TAMP_MISR_ITAMP6MF_Msk       (0x1UL << TAMP_MISR_ITAMP6MF_Pos)         /*!< 0x00200000 */

+#define TAMP_MISR_ITAMP6MF           TAMP_MISR_ITAMP6MF_Msk

+#define TAMP_MISR_ITAMP8MF_Pos       (23U)

+#define TAMP_MISR_ITAMP8MF_Msk       (0x1UL << TAMP_MISR_ITAMP8MF_Pos)         /*!< 0x00800000 */

+#define TAMP_MISR_ITAMP8MF           TAMP_MISR_ITAMP8MF_Msk

+

+/********************  Bits definition for TAMP_SCR register  *****************/

+#define TAMP_SCR_CTAMP1F_Pos         (0U)

+#define TAMP_SCR_CTAMP1F_Msk         (0x1UL << TAMP_SCR_CTAMP1F_Pos)            /*!< 0x00000001 */

+#define TAMP_SCR_CTAMP1F             TAMP_SCR_CTAMP1F_Msk

+#define TAMP_SCR_CTAMP2F_Pos         (1U)

+#define TAMP_SCR_CTAMP2F_Msk         (0x1UL << TAMP_SCR_CTAMP2F_Pos)            /*!< 0x00000002 */

+#define TAMP_SCR_CTAMP2F             TAMP_SCR_CTAMP2F_Msk

+#define TAMP_SCR_CTAMP3F_Pos         (2U)

+#define TAMP_SCR_CTAMP3F_Msk         (0x1UL << TAMP_SCR_CTAMP3F_Pos)           /*!< 0x00000004 */

+#define TAMP_SCR_CTAMP3F             TAMP_SCR_CTAMP3F_Msk

+#define TAMP_SCR_CITAMP1F_Pos        (16U)

+#define TAMP_SCR_CITAMP1F_Msk        (0x1UL << TAMP_SCR_CITAMP1F_Pos)          /*!< 0x00010000 */

+#define TAMP_SCR_CITAMP1F            TAMP_SCR_CITAMP1F_Msk

+#define TAMP_SCR_CITAMP2F_Pos        (17U)

+#define TAMP_SCR_CITAMP2F_Msk        (0x1UL << TAMP_SCR_CITAMP2F_Pos)          /*!< 0x00020000 */

+#define TAMP_SCR_CITAMP2F            TAMP_SCR_CITAMP2F_Msk

+#define TAMP_SCR_CITAMP3F_Pos        (18U)

+#define TAMP_SCR_CITAMP3F_Msk        (0x1UL << TAMP_SCR_CITAMP3F_Pos)          /*!< 0x00040000 */

+#define TAMP_SCR_CITAMP3F            TAMP_SCR_CITAMP3F_Msk

+#define TAMP_SCR_CITAMP4F_Pos        (19U)

+#define TAMP_SCR_CITAMP4F_Msk        (0x1UL << TAMP_SCR_CITAMP4F_Pos)          /*!< 0x00080000 */

+#define TAMP_SCR_CITAMP4F            TAMP_SCR_CITAMP4F_Msk

+#define TAMP_SCR_CITAMP5F_Pos        (20U)

+#define TAMP_SCR_CITAMP5F_Msk        (0x1UL << TAMP_SCR_CITAMP5F_Pos)          /*!< 0x00100000 */

+#define TAMP_SCR_CITAMP5F            TAMP_SCR_CITAMP5F_Msk

+#define TAMP_SCR_CITAMP6F_Pos        (21U)

+#define TAMP_SCR_CITAMP6F_Msk        (0x1UL << TAMP_SCR_CITAMP6F_Pos)          /*!< 0x00200000 */

+#define TAMP_SCR_CITAMP6F            TAMP_SCR_CITAMP6F_Msk

+#define TAMP_SCR_CITAMP8F_Pos        (23U)

+#define TAMP_SCR_CITAMP8F_Msk        (0x1UL << TAMP_SCR_CITAMP8F_Pos)          /*!< 0x00800000 */

+#define TAMP_SCR_CITAMP8F            TAMP_SCR_CITAMP8F_Msk

+

+/********************  Bits definition for TAMP_COUNTR register  **************/

+#define TAMP_COUNTR_Pos              (16U)

+#define TAMP_COUNTR_Msk              (0xFFFFUL << TAMP_COUNTR_Pos)             /*!< 0xFFFF0000 */

+#define TAMP_COUNTR                  TAMP_COUNTR_Msk

+

+/********************  Bits definition for TAMP_OR register  ******************/

+#define TAMP_OR_OUT3_RMP_Pos         (0U)

+#define TAMP_OR_OUT3_RMP_Msk         (0x1UL << TAMP_OR_OUT3_RMP_Pos)           /*!< 0x00000001 */

+#define TAMP_OR_OUT3_RMP             TAMP_OR_OUT3_RMP_Msk

+

+/********************  Bits definition for TAMP_BKP0R register  ***************/

+#define TAMP_BKP0R_Pos               (0U)

+#define TAMP_BKP0R_Msk               (0xFFFFFFFFUL << TAMP_BKP0R_Pos)           /*!< 0xFFFFFFFF */

+#define TAMP_BKP0R                   TAMP_BKP0R_Msk

+

+/********************  Bits definition for TAMP_BKP1R register  ****************/

+#define TAMP_BKP1R_Pos               (0U)

+#define TAMP_BKP1R_Msk               (0xFFFFFFFFUL << TAMP_BKP1R_Pos)           /*!< 0xFFFFFFFF */

+#define TAMP_BKP1R                   TAMP_BKP1R_Msk

+

+/********************  Bits definition for TAMP_BKP2R register  ****************/

+#define TAMP_BKP2R_Pos               (0U)

+#define TAMP_BKP2R_Msk               (0xFFFFFFFFUL << TAMP_BKP2R_Pos)           /*!< 0xFFFFFFFF */

+#define TAMP_BKP2R                   TAMP_BKP2R_Msk

+

+/********************  Bits definition for TAMP_BKP3R register  ****************/

+#define TAMP_BKP3R_Pos               (0U)

+#define TAMP_BKP3R_Msk               (0xFFFFFFFFUL << TAMP_BKP3R_Pos)           /*!< 0xFFFFFFFF */

+#define TAMP_BKP3R                   TAMP_BKP3R_Msk

+

+/********************  Bits definition for TAMP_BKP4R register  ****************/

+#define TAMP_BKP4R_Pos               (0U)

+#define TAMP_BKP4R_Msk               (0xFFFFFFFFUL << TAMP_BKP4R_Pos)           /*!< 0xFFFFFFFF */

+#define TAMP_BKP4R                   TAMP_BKP4R_Msk

+

+/********************  Bits definition for TAMP_BKP5R register  ****************/

+#define TAMP_BKP5R_Pos               (0U)

+#define TAMP_BKP5R_Msk               (0xFFFFFFFFUL << TAMP_BKP5R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP5R                   TAMP_BKP5R_Msk

+

+/********************  Bits definition for TAMP_BKP6R register  ****************/

+#define TAMP_BKP6R_Pos               (0U)

+#define TAMP_BKP6R_Msk               (0xFFFFFFFFUL << TAMP_BKP6R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP6R                   TAMP_BKP6R_Msk

+

+/********************  Bits definition for TAMP_BKP7R register  ****************/

+#define TAMP_BKP7R_Pos               (0U)

+#define TAMP_BKP7R_Msk               (0xFFFFFFFFUL << TAMP_BKP7R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP7R                   TAMP_BKP7R_Msk

+

+/********************  Bits definition for TAMP_BKP8R register  ****************/

+#define TAMP_BKP8R_Pos               (0U)

+#define TAMP_BKP8R_Msk               (0xFFFFFFFFUL << TAMP_BKP8R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP8R                   TAMP_BKP8R_Msk

+

+/********************  Bits definition for TAMP_BKP9R register  ****************/

+#define TAMP_BKP9R_Pos               (0U)

+#define TAMP_BKP9R_Msk               (0xFFFFFFFFUL << TAMP_BKP9R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP9R                   TAMP_BKP9R_Msk

+

+/********************  Bits definition for TAMP_BKP10R register  ***************/

+#define TAMP_BKP10R_Pos              (0U)

+#define TAMP_BKP10R_Msk              (0xFFFFFFFFUL << TAMP_BKP10R_Pos)         /*!< 0xFFFFFFFF */

+#define TAMP_BKP10R                  TAMP_BKP10R_Msk

+

+/********************  Bits definition for TAMP_BKP11R register  ***************/

+#define TAMP_BKP11R_Pos              (0U)

+#define TAMP_BKP11R_Msk              (0xFFFFFFFFUL << TAMP_BKP11R_Pos)         /*!< 0xFFFFFFFF */

+#define TAMP_BKP11R                  TAMP_BKP11R_Msk

+

+/********************  Bits definition for TAMP_BKP12R register  ***************/

+#define TAMP_BKP12R_Pos              (0U)

+#define TAMP_BKP12R_Msk              (0xFFFFFFFFUL << TAMP_BKP12R_Pos)         /*!< 0xFFFFFFFF */

+#define TAMP_BKP12R                  TAMP_BKP12R_Msk

+

+/********************  Bits definition for TAMP_BKP13R register  ***************/

+#define TAMP_BKP13R_Pos              (0U)

+#define TAMP_BKP13R_Msk              (0xFFFFFFFFUL << TAMP_BKP13R_Pos)         /*!< 0xFFFFFFFF */

+#define TAMP_BKP13R                  TAMP_BKP13R_Msk

+

+/********************  Bits definition for TAMP_BKP14R register  ***************/

+#define TAMP_BKP14R_Pos              (0U)

+#define TAMP_BKP14R_Msk              (0xFFFFFFFFUL << TAMP_BKP14R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP14R                  TAMP_BKP14R_Msk

+

+/********************  Bits definition for TAMP_BKP15R register  ***************/

+#define TAMP_BKP15R_Pos              (0U)

+#define TAMP_BKP15R_Msk              (0xFFFFFFFFUL << TAMP_BKP15R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP15R                  TAMP_BKP15R_Msk

+

+/********************  Bits definition for TAMP_BKP16R register  ***************/

+#define TAMP_BKP16R_Pos              (0U)

+#define TAMP_BKP16R_Msk              (0xFFFFFFFFUL << TAMP_BKP16R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP16R                  TAMP_BKP16R_Msk

+

+/********************  Bits definition for TAMP_BKP17R register  ***************/

+#define TAMP_BKP17R_Pos              (0U)

+#define TAMP_BKP17R_Msk              (0xFFFFFFFFUL << TAMP_BKP17R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP17R                  TAMP_BKP17R_Msk

+

+/********************  Bits definition for TAMP_BKP18R register  ***************/

+#define TAMP_BKP18R_Pos              (0U)

+#define TAMP_BKP18R_Msk              (0xFFFFFFFFUL << TAMP_BKP18R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP18R                  TAMP_BKP18R_Msk

+

+/********************  Bits definition for TAMP_BKP19R register  ***************/

+#define TAMP_BKP19R_Pos              (0U)

+#define TAMP_BKP19R_Msk              (0xFFFFFFFFUL << TAMP_BKP19R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP19R                  TAMP_BKP19R_Msk

+

+/********************  Bits definition for TAMP_BKP20R register  ***************/

+#define TAMP_BKP20R_Pos              (0U)

+#define TAMP_BKP20R_Msk              (0xFFFFFFFFUL << TAMP_BKP20R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP20R                  TAMP_BKP20R_Msk

+

+/********************  Bits definition for TAMP_BKP21R register  ***************/

+#define TAMP_BKP21R_Pos              (0U)

+#define TAMP_BKP21R_Msk              (0xFFFFFFFFUL << TAMP_BKP21R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP21R                  TAMP_BKP21R_Msk

+

+/********************  Bits definition for TAMP_BKP22R register  ***************/

+#define TAMP_BKP22R_Pos              (0U)

+#define TAMP_BKP22R_Msk              (0xFFFFFFFFUL << TAMP_BKP22R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP22R                  TAMP_BKP22R_Msk

+

+/********************  Bits definition for TAMP_BKP23R register  ***************/

+#define TAMP_BKP23R_Pos              (0U)

+#define TAMP_BKP23R_Msk              (0xFFFFFFFFUL << TAMP_BKP23R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP23R                  TAMP_BKP23R_Msk

+

+/********************  Bits definition for TAMP_BKP24R register  ***************/

+#define TAMP_BKP24R_Pos              (0U)

+#define TAMP_BKP24R_Msk              (0xFFFFFFFFUL << TAMP_BKP24R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP24R                  TAMP_BKP24R_Msk

+

+/********************  Bits definition for TAMP_BKP25R register  ***************/

+#define TAMP_BKP25R_Pos              (0U)

+#define TAMP_BKP25R_Msk              (0xFFFFFFFFUL << TAMP_BKP25R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP25R                  TAMP_BKP25R_Msk

+

+/********************  Bits definition for TAMP_BKP26R register  ***************/

+#define TAMP_BKP26R_Pos              (0U)

+#define TAMP_BKP26R_Msk              (0xFFFFFFFFUL << TAMP_BKP26R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP26R                  TAMP_BKP26R_Msk

+

+/********************  Bits definition for TAMP_BKP27R register  ***************/

+#define TAMP_BKP27R_Pos              (0U)

+#define TAMP_BKP27R_Msk              (0xFFFFFFFFUL << TAMP_BKP27R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP27R                  TAMP_BKP27R_Msk

+

+/********************  Bits definition for TAMP_BKP28R register  ***************/

+#define TAMP_BKP28R_Pos              (0U)

+#define TAMP_BKP28R_Msk              (0xFFFFFFFFUL << TAMP_BKP28R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP28R                  TAMP_BKP28R_Msk

+

+/********************  Bits definition for TAMP_BKP29R register  ***************/

+#define TAMP_BKP29R_Pos              (0U)

+#define TAMP_BKP29R_Msk              (0xFFFFFFFFUL << TAMP_BKP29R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP29R                  TAMP_BKP29R_Msk

+

+/********************  Bits definition for TAMP_BKP30R register  ***************/

+#define TAMP_BKP30R_Pos              (0U)

+#define TAMP_BKP30R_Msk              (0xFFFFFFFFUL << TAMP_BKP30R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP30R                  TAMP_BKP30R_Msk

+

+/********************  Bits definition for TAMP_BKP31R register  ***************/

+#define TAMP_BKP31R_Pos              (0U)

+#define TAMP_BKP31R_Msk              (0xFFFFFFFFUL << TAMP_BKP31R_Pos)          /*!< 0xFFFFFFFF */

+#define TAMP_BKP31R                  TAMP_BKP31R_Msk

+

+/******************** Number of backup registers ******************************/

+#define TAMP_BKP_NUMBER_Pos             (5U)

+#define TAMP_BKP_NUMBER_Msk             (0x1UL << TAMP_BKP_NUMBER_Pos)         /*!< 0x00000080 */

+#define TAMP_BKP_NUMBER                 TAMP_BKP_NUMBER_Msk                    /*!< 32 BKPREG  */

+

+/******************************************************************************/

+/*                                                                            */

+/*                              SPDIF-RX Interface                            */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for SPDIF_CR register  ******************/

+#define SPDIFRX_CR_SPDIFEN_Pos      (0U)

+#define SPDIFRX_CR_SPDIFEN_Msk      (0x3UL << SPDIFRX_CR_SPDIFEN_Pos)          /*!< 0x00000003 */

+#define SPDIFRX_CR_SPDIFEN          SPDIFRX_CR_SPDIFEN_Msk                     /*!<Peripheral Block Enable                      */

+#define SPDIFRX_CR_RXDMAEN_Pos      (2U)

+#define SPDIFRX_CR_RXDMAEN_Msk      (0x1UL << SPDIFRX_CR_RXDMAEN_Pos)          /*!< 0x00000004 */

+#define SPDIFRX_CR_RXDMAEN          SPDIFRX_CR_RXDMAEN_Msk                     /*!<Receiver DMA Enable for data flow            */

+#define SPDIFRX_CR_RXSTEO_Pos       (3U)

+#define SPDIFRX_CR_RXSTEO_Msk       (0x1UL << SPDIFRX_CR_RXSTEO_Pos)           /*!< 0x00000008 */

+#define SPDIFRX_CR_RXSTEO           SPDIFRX_CR_RXSTEO_Msk                      /*!<Stereo Mode                                  */

+#define SPDIFRX_CR_DRFMT_Pos        (4U)

+#define SPDIFRX_CR_DRFMT_Msk        (0x3UL << SPDIFRX_CR_DRFMT_Pos)            /*!< 0x00000030 */

+#define SPDIFRX_CR_DRFMT            SPDIFRX_CR_DRFMT_Msk                       /*!<RX Data format                               */

+#define SPDIFRX_CR_PMSK_Pos         (6U)

+#define SPDIFRX_CR_PMSK_Msk         (0x1UL << SPDIFRX_CR_PMSK_Pos)             /*!< 0x00000040 */

+#define SPDIFRX_CR_PMSK             SPDIFRX_CR_PMSK_Msk                        /*!<Mask Parity error bit                        */

+#define SPDIFRX_CR_VMSK_Pos         (7U)

+#define SPDIFRX_CR_VMSK_Msk         (0x1UL << SPDIFRX_CR_VMSK_Pos)             /*!< 0x00000080 */

+#define SPDIFRX_CR_VMSK             SPDIFRX_CR_VMSK_Msk                        /*!<Mask of Validity bit                         */

+#define SPDIFRX_CR_CUMSK_Pos        (8U)

+#define SPDIFRX_CR_CUMSK_Msk        (0x1UL << SPDIFRX_CR_CUMSK_Pos)            /*!< 0x00000100 */

+#define SPDIFRX_CR_CUMSK            SPDIFRX_CR_CUMSK_Msk                       /*!<Mask of channel status and user bits         */

+#define SPDIFRX_CR_PTMSK_Pos        (9U)

+#define SPDIFRX_CR_PTMSK_Msk        (0x1UL << SPDIFRX_CR_PTMSK_Pos)            /*!< 0x00000200 */

+#define SPDIFRX_CR_PTMSK            SPDIFRX_CR_PTMSK_Msk                       /*!<Mask of Preamble Type bits                   */

+#define SPDIFRX_CR_CBDMAEN_Pos      (10U)

+#define SPDIFRX_CR_CBDMAEN_Msk      (0x1UL << SPDIFRX_CR_CBDMAEN_Pos)          /*!< 0x00000400 */

+#define SPDIFRX_CR_CBDMAEN          SPDIFRX_CR_CBDMAEN_Msk                     /*!<Control Buffer DMA ENable for control flow   */

+#define SPDIFRX_CR_CHSEL_Pos        (11U)

+#define SPDIFRX_CR_CHSEL_Msk        (0x1UL << SPDIFRX_CR_CHSEL_Pos)            /*!< 0x00000800 */

+#define SPDIFRX_CR_CHSEL            SPDIFRX_CR_CHSEL_Msk                       /*!<Channel Selection                            */

+#define SPDIFRX_CR_NBTR_Pos         (12U)

+#define SPDIFRX_CR_NBTR_Msk         (0x3UL << SPDIFRX_CR_NBTR_Pos)             /*!< 0x00003000 */

+#define SPDIFRX_CR_NBTR             SPDIFRX_CR_NBTR_Msk                        /*!<Maximum allowed re-tries during synchronization phase */

+#define SPDIFRX_CR_WFA_Pos          (14U)

+#define SPDIFRX_CR_WFA_Msk          (0x1UL << SPDIFRX_CR_WFA_Pos)              /*!< 0x00004000 */

+#define SPDIFRX_CR_WFA              SPDIFRX_CR_WFA_Msk                         /*!<Wait For Activity     */

+#define SPDIFRX_CR_INSEL_Pos        (16U)

+#define SPDIFRX_CR_INSEL_Msk        (0x7UL << SPDIFRX_CR_INSEL_Pos)            /*!< 0x00070000 */

+#define SPDIFRX_CR_INSEL            SPDIFRX_CR_INSEL_Msk                       /*!<SPDIF input selection */

+#define SPDIFRX_CR_CKSEN_Pos        (20U)

+#define SPDIFRX_CR_CKSEN_Msk        (0x1UL << SPDIFRX_CR_CKSEN_Pos)            /*!< 0x00100000 */

+#define SPDIFRX_CR_CKSEN            SPDIFRX_CR_CKSEN_Msk                       /*!<Symbol Clock Enable */

+#define SPDIFRX_CR_CKSBKPEN_Pos     (21U)

+#define SPDIFRX_CR_CKSBKPEN_Msk     (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos)         /*!< 0x00200000 */

+#define SPDIFRX_CR_CKSBKPEN         SPDIFRX_CR_CKSBKPEN_Msk                    /*!<Backup Symbol Clock Enable */

+

+/*******************  Bit definition for SPDIFRX_IMR register  *******************/

+#define SPDIFRX_IMR_RXNEIE_Pos      (0U)

+#define SPDIFRX_IMR_RXNEIE_Msk      (0x1UL << SPDIFRX_IMR_RXNEIE_Pos)          /*!< 0x00000001 */

+#define SPDIFRX_IMR_RXNEIE          SPDIFRX_IMR_RXNEIE_Msk                     /*!<RXNE interrupt enable                              */

+#define SPDIFRX_IMR_CSRNEIE_Pos     (1U)

+#define SPDIFRX_IMR_CSRNEIE_Msk     (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos)         /*!< 0x00000002 */

+#define SPDIFRX_IMR_CSRNEIE         SPDIFRX_IMR_CSRNEIE_Msk                    /*!<Control Buffer Ready Interrupt Enable              */

+#define SPDIFRX_IMR_PERRIE_Pos      (2U)

+#define SPDIFRX_IMR_PERRIE_Msk      (0x1UL << SPDIFRX_IMR_PERRIE_Pos)          /*!< 0x00000004 */

+#define SPDIFRX_IMR_PERRIE          SPDIFRX_IMR_PERRIE_Msk                     /*!<Parity error interrupt enable                      */

+#define SPDIFRX_IMR_OVRIE_Pos       (3U)

+#define SPDIFRX_IMR_OVRIE_Msk       (0x1UL << SPDIFRX_IMR_OVRIE_Pos)           /*!< 0x00000008 */

+#define SPDIFRX_IMR_OVRIE           SPDIFRX_IMR_OVRIE_Msk                      /*!<Overrun error Interrupt Enable                     */

+#define SPDIFRX_IMR_SBLKIE_Pos      (4U)

+#define SPDIFRX_IMR_SBLKIE_Msk      (0x1UL << SPDIFRX_IMR_SBLKIE_Pos)          /*!< 0x00000010 */

+#define SPDIFRX_IMR_SBLKIE          SPDIFRX_IMR_SBLKIE_Msk                     /*!<Synchronization Block Detected Interrupt Enable    */

+#define SPDIFRX_IMR_SYNCDIE_Pos     (5U)

+#define SPDIFRX_IMR_SYNCDIE_Msk     (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos)         /*!< 0x00000020 */

+#define SPDIFRX_IMR_SYNCDIE         SPDIFRX_IMR_SYNCDIE_Msk                    /*!<Synchronization Done                               */

+#define SPDIFRX_IMR_IFEIE_Pos       (6U)

+#define SPDIFRX_IMR_IFEIE_Msk       (0x1UL << SPDIFRX_IMR_IFEIE_Pos)           /*!< 0x00000040 */

+#define SPDIFRX_IMR_IFEIE           SPDIFRX_IMR_IFEIE_Msk                      /*!<Serial Interface Error Interrupt Enable            */

+

+/*******************  Bit definition for SPDIFRX_SR register  *******************/

+#define SPDIFRX_SR_RXNE_Pos         (0U)

+#define SPDIFRX_SR_RXNE_Msk         (0x1UL << SPDIFRX_SR_RXNE_Pos)             /*!< 0x00000001 */

+#define SPDIFRX_SR_RXNE             SPDIFRX_SR_RXNE_Msk                        /*!<Read data register not empty                          */

+#define SPDIFRX_SR_CSRNE_Pos        (1U)

+#define SPDIFRX_SR_CSRNE_Msk        (0x1UL << SPDIFRX_SR_CSRNE_Pos)            /*!< 0x00000002 */

+#define SPDIFRX_SR_CSRNE            SPDIFRX_SR_CSRNE_Msk                       /*!<The Control Buffer register is not empty              */

+#define SPDIFRX_SR_PERR_Pos         (2U)

+#define SPDIFRX_SR_PERR_Msk         (0x1UL << SPDIFRX_SR_PERR_Pos)             /*!< 0x00000004 */

+#define SPDIFRX_SR_PERR             SPDIFRX_SR_PERR_Msk                        /*!<Parity error                                          */

+#define SPDIFRX_SR_OVR_Pos          (3U)

+#define SPDIFRX_SR_OVR_Msk          (0x1UL << SPDIFRX_SR_OVR_Pos)              /*!< 0x00000008 */

+#define SPDIFRX_SR_OVR              SPDIFRX_SR_OVR_Msk                         /*!<Overrun error                                         */

+#define SPDIFRX_SR_SBD_Pos          (4U)

+#define SPDIFRX_SR_SBD_Msk          (0x1UL << SPDIFRX_SR_SBD_Pos)              /*!< 0x00000010 */

+#define SPDIFRX_SR_SBD              SPDIFRX_SR_SBD_Msk                         /*!<Synchronization Block Detected                        */

+#define SPDIFRX_SR_SYNCD_Pos        (5U)

+#define SPDIFRX_SR_SYNCD_Msk        (0x1UL << SPDIFRX_SR_SYNCD_Pos)            /*!< 0x00000020 */

+#define SPDIFRX_SR_SYNCD            SPDIFRX_SR_SYNCD_Msk                       /*!<Synchronization Done                                  */

+#define SPDIFRX_SR_FERR_Pos         (6U)

+#define SPDIFRX_SR_FERR_Msk         (0x1UL << SPDIFRX_SR_FERR_Pos)             /*!< 0x00000040 */

+#define SPDIFRX_SR_FERR             SPDIFRX_SR_FERR_Msk                        /*!<Framing error                                         */

+#define SPDIFRX_SR_SERR_Pos         (7U)

+#define SPDIFRX_SR_SERR_Msk         (0x1UL << SPDIFRX_SR_SERR_Pos)             /*!< 0x00000080 */

+#define SPDIFRX_SR_SERR             SPDIFRX_SR_SERR_Msk                        /*!<Synchronization error                                 */

+#define SPDIFRX_SR_TERR_Pos         (8U)

+#define SPDIFRX_SR_TERR_Msk         (0x1UL << SPDIFRX_SR_TERR_Pos)             /*!< 0x00000100 */

+#define SPDIFRX_SR_TERR             SPDIFRX_SR_TERR_Msk                        /*!<Time-out error                                        */

+#define SPDIFRX_SR_WIDTH5_Pos       (16U)

+#define SPDIFRX_SR_WIDTH5_Msk       (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos)        /*!< 0x7FFF0000 */

+#define SPDIFRX_SR_WIDTH5           SPDIFRX_SR_WIDTH5_Msk                      /*!<Duration of 5 symbols counted with spdif_clk          */

+

+/*******************  Bit definition for SPDIFRX_IFCR register  *******************/

+#define SPDIFRX_IFCR_PERRCF_Pos     (2U)

+#define SPDIFRX_IFCR_PERRCF_Msk     (0x1UL << SPDIFRX_IFCR_PERRCF_Pos)         /*!< 0x00000004 */

+#define SPDIFRX_IFCR_PERRCF         SPDIFRX_IFCR_PERRCF_Msk                    /*!<Clears the Parity error flag                         */

+#define SPDIFRX_IFCR_OVRCF_Pos      (3U)

+#define SPDIFRX_IFCR_OVRCF_Msk      (0x1UL << SPDIFRX_IFCR_OVRCF_Pos)          /*!< 0x00000008 */

+#define SPDIFRX_IFCR_OVRCF          SPDIFRX_IFCR_OVRCF_Msk                     /*!<Clears the Overrun error flag                        */

+#define SPDIFRX_IFCR_SBDCF_Pos      (4U)

+#define SPDIFRX_IFCR_SBDCF_Msk      (0x1UL << SPDIFRX_IFCR_SBDCF_Pos)          /*!< 0x00000010 */

+#define SPDIFRX_IFCR_SBDCF          SPDIFRX_IFCR_SBDCF_Msk                     /*!<Clears the Synchronization Block Detected flag       */

+#define SPDIFRX_IFCR_SYNCDCF_Pos    (5U)

+#define SPDIFRX_IFCR_SYNCDCF_Msk    (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos)        /*!< 0x00000020 */

+#define SPDIFRX_IFCR_SYNCDCF        SPDIFRX_IFCR_SYNCDCF_Msk                   /*!<Clears the Synchronization Done flag                 */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b00 case) *******************/

+#define SPDIFRX_DR0_DR_Pos          (0U)

+#define SPDIFRX_DR0_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos)         /*!< 0x00FFFFFF */

+#define SPDIFRX_DR0_DR              SPDIFRX_DR0_DR_Msk                         /*!<Data value            */

+#define SPDIFRX_DR0_PE_Pos          (24U)

+#define SPDIFRX_DR0_PE_Msk          (0x1UL << SPDIFRX_DR0_PE_Pos)              /*!< 0x01000000 */

+#define SPDIFRX_DR0_PE              SPDIFRX_DR0_PE_Msk                         /*!<Parity Error bit      */

+#define SPDIFRX_DR0_V_Pos           (25U)

+#define SPDIFRX_DR0_V_Msk           (0x1UL << SPDIFRX_DR0_V_Pos)               /*!< 0x02000000 */

+#define SPDIFRX_DR0_V               SPDIFRX_DR0_V_Msk                          /*!<Validity bit          */

+#define SPDIFRX_DR0_U_Pos           (26U)

+#define SPDIFRX_DR0_U_Msk           (0x1UL << SPDIFRX_DR0_U_Pos)               /*!< 0x04000000 */

+#define SPDIFRX_DR0_U               SPDIFRX_DR0_U_Msk                          /*!<User bit              */

+#define SPDIFRX_DR0_C_Pos           (27U)

+#define SPDIFRX_DR0_C_Msk           (0x1UL << SPDIFRX_DR0_C_Pos)               /*!< 0x08000000 */

+#define SPDIFRX_DR0_C               SPDIFRX_DR0_C_Msk                          /*!<Channel Status bit    */

+#define SPDIFRX_DR0_PT_Pos          (28U)

+#define SPDIFRX_DR0_PT_Msk          (0x3UL << SPDIFRX_DR0_PT_Pos)              /*!< 0x30000000 */

+#define SPDIFRX_DR0_PT              SPDIFRX_DR0_PT_Msk                         /*!<Preamble Type         */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b01 case) *******************/

+#define SPDIFRX_DR1_DR_Pos          (8U)

+#define SPDIFRX_DR1_DR_Msk          (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos)         /*!< 0xFFFFFF00 */

+#define SPDIFRX_DR1_DR              SPDIFRX_DR1_DR_Msk                         /*!<Data value            */

+#define SPDIFRX_DR1_PT_Pos          (4U)

+#define SPDIFRX_DR1_PT_Msk          (0x3UL << SPDIFRX_DR1_PT_Pos)              /*!< 0x00000030 */

+#define SPDIFRX_DR1_PT              SPDIFRX_DR1_PT_Msk                         /*!<Preamble Type         */

+#define SPDIFRX_DR1_C_Pos           (3U)

+#define SPDIFRX_DR1_C_Msk           (0x1UL << SPDIFRX_DR1_C_Pos)               /*!< 0x00000008 */

+#define SPDIFRX_DR1_C               SPDIFRX_DR1_C_Msk                          /*!<Channel Status bit    */

+#define SPDIFRX_DR1_U_Pos           (2U)

+#define SPDIFRX_DR1_U_Msk           (0x1UL << SPDIFRX_DR1_U_Pos)               /*!< 0x00000004 */

+#define SPDIFRX_DR1_U               SPDIFRX_DR1_U_Msk                          /*!<User bit              */

+#define SPDIFRX_DR1_V_Pos           (1U)

+#define SPDIFRX_DR1_V_Msk           (0x1UL << SPDIFRX_DR1_V_Pos)               /*!< 0x00000002 */

+#define SPDIFRX_DR1_V               SPDIFRX_DR1_V_Msk                          /*!<Validity bit          */

+#define SPDIFRX_DR1_PE_Pos          (0U)

+#define SPDIFRX_DR1_PE_Msk          (0x1UL << SPDIFRX_DR1_PE_Pos)              /*!< 0x00000001 */

+#define SPDIFRX_DR1_PE              SPDIFRX_DR1_PE_Msk                         /*!<Parity Error bit      */

+

+/*******************  Bit definition for SPDIFRX_DR register  (DRFMT = 0b10 case) *******************/

+#define SPDIFRX_DR1_DRNL1_Pos       (16U)

+#define SPDIFRX_DR1_DRNL1_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos)        /*!< 0xFFFF0000 */

+#define SPDIFRX_DR1_DRNL1           SPDIFRX_DR1_DRNL1_Msk                      /*!<Data value Channel B      */

+#define SPDIFRX_DR1_DRNL2_Pos       (0U)

+#define SPDIFRX_DR1_DRNL2_Msk       (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos)        /*!< 0x0000FFFF */

+#define SPDIFRX_DR1_DRNL2           SPDIFRX_DR1_DRNL2_Msk                      /*!<Data value Channel A      */

+

+/*******************  Bit definition for SPDIFRX_CSR register   *******************/

+#define SPDIFRX_CSR_USR_Pos         (0U)

+#define SPDIFRX_CSR_USR_Msk         (0xFFFFUL << SPDIFRX_CSR_USR_Pos)          /*!< 0x0000FFFF */

+#define SPDIFRX_CSR_USR             SPDIFRX_CSR_USR_Msk                        /*!<User data information           */

+#define SPDIFRX_CSR_CS_Pos          (16U)

+#define SPDIFRX_CSR_CS_Msk          (0xFFUL << SPDIFRX_CSR_CS_Pos)             /*!< 0x00FF0000 */

+#define SPDIFRX_CSR_CS              SPDIFRX_CSR_CS_Msk                         /*!<Channel A status information    */

+#define SPDIFRX_CSR_SOB_Pos         (24U)

+#define SPDIFRX_CSR_SOB_Msk         (0x1UL << SPDIFRX_CSR_SOB_Pos)             /*!< 0x01000000 */

+#define SPDIFRX_CSR_SOB             SPDIFRX_CSR_SOB_Msk                        /*!<Start Of Block                  */

+

+/*******************  Bit definition for SPDIFRX_DIR register    *******************/

+#define SPDIFRX_DIR_THI_Pos         (0U)

+#define SPDIFRX_DIR_THI_Msk         (0x1FFFUL << SPDIFRX_DIR_THI_Pos)          /*!< 0x00001FFF */

+#define SPDIFRX_DIR_THI             SPDIFRX_DIR_THI_Msk                        /*!<Threshold LOW      */

+#define SPDIFRX_DIR_TLO_Pos         (16U)

+#define SPDIFRX_DIR_TLO_Msk         (0x1FFFUL << SPDIFRX_DIR_TLO_Pos)          /*!< 0x1FFF0000 */

+#define SPDIFRX_DIR_TLO             SPDIFRX_DIR_TLO_Msk                        /*!<Threshold HIGH     */

+

+/*******************  Bit definition for SPDIFRX_VERR register    *******************/

+#define SPDIFRX_VERR_MINREV_Pos     (0U)

+#define SPDIFRX_VERR_MINREV_Msk     (0xFUL << SPDIFRX_VERR_MINREV_Pos)         /*!< 0x0000000F */

+#define SPDIFRX_VERR_MINREV         SPDIFRX_VERR_MINREV_Msk                    /*!<SPDIFRX Minor revision     */

+#define SPDIFRX_VERR_MAJREV_Pos     (4U)

+#define SPDIFRX_VERR_MAJREV_Msk     (0xFUL << SPDIFRX_VERR_MAJREV_Pos)         /*!< 0x000000F0 */

+#define SPDIFRX_VERR_MAJREV         SPDIFRX_VERR_MAJREV_Msk                    /*!<SPDIFRX Major revision     */

+

+/*******************  Bit definition for SPDIFRX_IDR register    *******************/

+#define SPDIFRX_IDR_ID_Pos          (0U)

+#define SPDIFRX_IDR_ID_Msk          (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos)       /*!< 0xFFFFFFFF */

+#define SPDIFRX_IDR_ID              SPDIFRX_IDR_ID_Msk                         /*!<SPDIFRX identifier     */

+

+/*******************  Bit definition for SPDIFRX_SIDR register    *******************/

+#define SPDIFRX_SIDR_SID_Pos        (0U)

+#define SPDIFRX_SIDR_SID_Msk        (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos)     /*!< 0xFFFFFFFF */

+#define SPDIFRX_SIDR_SID            SPDIFRX_SIDR_SID_Msk                       /*!<Size of the memory region allocated to SPDIFRX registers */

+

+/******************************************************************************/

+/*                                                                            */

+/*                          Serial Audio Interface                            */

+/*                                                                            */

+/******************************************************************************/

+/*******************************  SAI VERSION  ********************************/

+#define SAI_VER_V2_1

+

+/********************  Bit definition for SAI_GCR register  *******************/

+#define SAI_GCR_SYNCIN_Pos         (0U)

+#define SAI_GCR_SYNCIN_Msk         (0x3UL << SAI_GCR_SYNCIN_Pos)               /*!< 0x00000003 */

+#define SAI_GCR_SYNCIN             SAI_GCR_SYNCIN_Msk                          /*!<SYNCIN[1:0] bits (Synchronization Inputs)   */

+#define SAI_GCR_SYNCIN_0           (0x1UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000001 */

+#define SAI_GCR_SYNCIN_1           (0x2UL << SAI_GCR_SYNCIN_Pos)                /*!< 0x00000002 */

+

+#define SAI_GCR_SYNCOUT_Pos        (4U)

+#define SAI_GCR_SYNCOUT_Msk        (0x3UL << SAI_GCR_SYNCOUT_Pos)              /*!< 0x00000030 */

+#define SAI_GCR_SYNCOUT            SAI_GCR_SYNCOUT_Msk                         /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */

+#define SAI_GCR_SYNCOUT_0          (0x1UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000010 */

+#define SAI_GCR_SYNCOUT_1          (0x2UL << SAI_GCR_SYNCOUT_Pos)               /*!< 0x00000020 */

+

+/*******************  Bit definition for SAI_xCR1 register  *******************/

+#define SAI_xCR1_MODE_Pos          (0U)

+#define SAI_xCR1_MODE_Msk          (0x3UL << SAI_xCR1_MODE_Pos)                /*!< 0x00000003 */

+#define SAI_xCR1_MODE              SAI_xCR1_MODE_Msk                           /*!<MODE[1:0] bits (Audio Block Mode)           */

+#define SAI_xCR1_MODE_0            (0x1UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000001 */

+#define SAI_xCR1_MODE_1            (0x2UL << SAI_xCR1_MODE_Pos)                 /*!< 0x00000002 */

+

+#define SAI_xCR1_PRTCFG_Pos        (2U)

+#define SAI_xCR1_PRTCFG_Msk        (0x3UL << SAI_xCR1_PRTCFG_Pos)              /*!< 0x0000000C */

+#define SAI_xCR1_PRTCFG            SAI_xCR1_PRTCFG_Msk                         /*!<PRTCFG[1:0] bits (Protocol Configuration)   */

+#define SAI_xCR1_PRTCFG_0          (0x1UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000004 */

+#define SAI_xCR1_PRTCFG_1          (0x2UL << SAI_xCR1_PRTCFG_Pos)               /*!< 0x00000008 */

+

+#define SAI_xCR1_DS_Pos            (5U)

+#define SAI_xCR1_DS_Msk            (0x7UL << SAI_xCR1_DS_Pos)                  /*!< 0x000000E0 */

+#define SAI_xCR1_DS                SAI_xCR1_DS_Msk                             /*!<DS[1:0] bits (Data Size) */

+#define SAI_xCR1_DS_0              (0x1UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000020 */

+#define SAI_xCR1_DS_1              (0x2UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000040 */

+#define SAI_xCR1_DS_2              (0x4UL << SAI_xCR1_DS_Pos)                   /*!< 0x00000080 */

+

+#define SAI_xCR1_LSBFIRST_Pos      (8U)

+#define SAI_xCR1_LSBFIRST_Msk      (0x1UL << SAI_xCR1_LSBFIRST_Pos)            /*!< 0x00000100 */

+#define SAI_xCR1_LSBFIRST          SAI_xCR1_LSBFIRST_Msk                       /*!<LSB First Configuration  */

+#define SAI_xCR1_CKSTR_Pos         (9U)

+#define SAI_xCR1_CKSTR_Msk         (0x1UL << SAI_xCR1_CKSTR_Pos)               /*!< 0x00000200 */

+#define SAI_xCR1_CKSTR             SAI_xCR1_CKSTR_Msk                          /*!<ClocK STRobing edge      */

+

+#define SAI_xCR1_SYNCEN_Pos        (10U)

+#define SAI_xCR1_SYNCEN_Msk        (0x3UL << SAI_xCR1_SYNCEN_Pos)              /*!< 0x00000C00 */

+#define SAI_xCR1_SYNCEN            SAI_xCR1_SYNCEN_Msk                         /*!<SYNCEN[1:0](SYNChronization ENable) */

+#define SAI_xCR1_SYNCEN_0          (0x1UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000400 */

+#define SAI_xCR1_SYNCEN_1          (0x2UL << SAI_xCR1_SYNCEN_Pos)               /*!< 0x00000800 */

+

+#define SAI_xCR1_MONO_Pos          (12U)

+#define SAI_xCR1_MONO_Msk          (0x1UL << SAI_xCR1_MONO_Pos)                /*!< 0x00001000 */

+#define SAI_xCR1_MONO              SAI_xCR1_MONO_Msk                           /*!<Mono mode                  */

+#define SAI_xCR1_OUTDRIV_Pos       (13U)

+#define SAI_xCR1_OUTDRIV_Msk       (0x1UL << SAI_xCR1_OUTDRIV_Pos)             /*!< 0x00002000 */

+#define SAI_xCR1_OUTDRIV           SAI_xCR1_OUTDRIV_Msk                        /*!<Output Drive               */

+#define SAI_xCR1_SAIEN_Pos         (16U)

+#define SAI_xCR1_SAIEN_Msk         (0x1UL << SAI_xCR1_SAIEN_Pos)               /*!< 0x00010000 */

+#define SAI_xCR1_SAIEN             SAI_xCR1_SAIEN_Msk                          /*!<Audio Block enable         */

+#define SAI_xCR1_DMAEN_Pos         (17U)

+#define SAI_xCR1_DMAEN_Msk         (0x1UL << SAI_xCR1_DMAEN_Pos)               /*!< 0x00020000 */

+#define SAI_xCR1_DMAEN             SAI_xCR1_DMAEN_Msk                          /*!<DMA enable                 */

+#define SAI_xCR1_NODIV_Pos         (19U)

+#define SAI_xCR1_NODIV_Msk         (0x1UL << SAI_xCR1_NODIV_Pos)               /*!< 0x00080000 */

+#define SAI_xCR1_NODIV             SAI_xCR1_NODIV_Msk                          /*!<No Divider Configuration   */

+

+#define SAI_xCR1_MCKDIV_Pos        (20U)

+#define SAI_xCR1_MCKDIV_Msk        (0x3FUL << SAI_xCR1_MCKDIV_Pos)             /*!< 0x03F00000 */

+#define SAI_xCR1_MCKDIV            SAI_xCR1_MCKDIV_Msk                         /*!<MCKDIV[5:0] (Master ClocK Divider)  */

+#define SAI_xCR1_MCKDIV_0          (0x01UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00100000 */

+#define SAI_xCR1_MCKDIV_1          (0x02UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00200000 */

+#define SAI_xCR1_MCKDIV_2          (0x04UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00400000 */

+#define SAI_xCR1_MCKDIV_3          (0x08UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x00800000 */

+#define SAI_xCR1_MCKDIV_4          (0x10UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x01000000 */

+#define SAI_xCR1_MCKDIV_5          (0x20UL << SAI_xCR1_MCKDIV_Pos)              /*!< 0x02000000 */

+

+#define SAI_xCR1_MCKEN_Pos         (27U)

+#define SAI_xCR1_MCKEN_Msk         (0x1UL << SAI_xCR1_MCKEN_Pos)               /*!< 0x08000000 */

+#define SAI_xCR1_MCKEN             SAI_xCR1_MCKEN_Msk                          /*!<Master ClocK enable */

+

+#define SAI_xCR1_OSR_Pos           (26U)

+#define SAI_xCR1_OSR_Msk           (0x1UL << SAI_xCR1_OSR_Pos)                 /*!< 0x04000000 */

+#define SAI_xCR1_OSR               SAI_xCR1_OSR_Msk                            /*!<OverSampling Ratio for master clock  */

+

+/* Legacy define */

+#define  SAI_xCR1_NOMCK               SAI_xCR1_NODIV

+

+/*******************  Bit definition for SAI_xCR2 register  *******************/

+#define SAI_xCR2_FTH_Pos           (0U)

+#define SAI_xCR2_FTH_Msk           (0x7UL << SAI_xCR2_FTH_Pos)                 /*!< 0x00000007 */

+#define SAI_xCR2_FTH               SAI_xCR2_FTH_Msk                            /*!<FTH[2:0](Fifo THreshold)  */

+#define SAI_xCR2_FTH_0             (0x1UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000001 */

+#define SAI_xCR2_FTH_1             (0x2UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000002 */

+#define SAI_xCR2_FTH_2             (0x4UL << SAI_xCR2_FTH_Pos)                  /*!< 0x00000004 */

+

+#define SAI_xCR2_FFLUSH_Pos        (3U)

+#define SAI_xCR2_FFLUSH_Msk        (0x1UL << SAI_xCR2_FFLUSH_Pos)              /*!< 0x00000008 */

+#define SAI_xCR2_FFLUSH            SAI_xCR2_FFLUSH_Msk                         /*!<Fifo FLUSH                       */

+#define SAI_xCR2_TRIS_Pos          (4U)

+#define SAI_xCR2_TRIS_Msk          (0x1UL << SAI_xCR2_TRIS_Pos)                /*!< 0x00000010 */

+#define SAI_xCR2_TRIS              SAI_xCR2_TRIS_Msk                           /*!<TRIState Management on data line */

+#define SAI_xCR2_MUTE_Pos          (5U)

+#define SAI_xCR2_MUTE_Msk          (0x1UL << SAI_xCR2_MUTE_Pos)                /*!< 0x00000020 */

+#define SAI_xCR2_MUTE              SAI_xCR2_MUTE_Msk                           /*!<Mute mode                        */

+#define SAI_xCR2_MUTEVAL_Pos       (6U)

+#define SAI_xCR2_MUTEVAL_Msk       (0x1UL << SAI_xCR2_MUTEVAL_Pos)             /*!< 0x00000040 */

+#define SAI_xCR2_MUTEVAL           SAI_xCR2_MUTEVAL_Msk                        /*!<Muate value                      */

+

+#define SAI_xCR2_MUTECNT_Pos       (7U)

+#define SAI_xCR2_MUTECNT_Msk       (0x3FUL << SAI_xCR2_MUTECNT_Pos)            /*!< 0x00001F80 */

+#define SAI_xCR2_MUTECNT           SAI_xCR2_MUTECNT_Msk                        /*!<MUTECNT[5:0] (MUTE counter) */

+#define SAI_xCR2_MUTECNT_0         (0x01UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000080 */

+#define SAI_xCR2_MUTECNT_1         (0x02UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000100 */

+#define SAI_xCR2_MUTECNT_2         (0x04UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000200 */

+#define SAI_xCR2_MUTECNT_3         (0x08UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000400 */

+#define SAI_xCR2_MUTECNT_4         (0x10UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00000800 */

+#define SAI_xCR2_MUTECNT_5         (0x20UL << SAI_xCR2_MUTECNT_Pos)             /*!< 0x00001000 */

+

+#define SAI_xCR2_CPL_Pos           (13U)

+#define SAI_xCR2_CPL_Msk           (0x1UL << SAI_xCR2_CPL_Pos)                 /*!< 0x00002000 */

+#define SAI_xCR2_CPL               SAI_xCR2_CPL_Msk                            /*!< Complement Bit             */

+

+#define SAI_xCR2_COMP_Pos          (14U)

+#define SAI_xCR2_COMP_Msk          (0x3UL << SAI_xCR2_COMP_Pos)                /*!< 0x0000C000 */

+#define SAI_xCR2_COMP              SAI_xCR2_COMP_Msk                           /*!<COMP[1:0] (Companding mode) */

+#define SAI_xCR2_COMP_0            (0x1UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00004000 */

+#define SAI_xCR2_COMP_1            (0x2UL << SAI_xCR2_COMP_Pos)                 /*!< 0x00008000 */

+

+/******************  Bit definition for SAI_xFRCR register  *******************/

+#define SAI_xFRCR_FRL_Pos          (0U)

+#define SAI_xFRCR_FRL_Msk          (0xFFUL << SAI_xFRCR_FRL_Pos)               /*!< 0x000000FF */

+#define SAI_xFRCR_FRL              SAI_xFRCR_FRL_Msk                           /*!<FRL[7:0](FRame Length)  */

+#define SAI_xFRCR_FRL_0            (0x01UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000001 */

+#define SAI_xFRCR_FRL_1            (0x02UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000002 */

+#define SAI_xFRCR_FRL_2            (0x04UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000004 */

+#define SAI_xFRCR_FRL_3            (0x08UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000008 */

+#define SAI_xFRCR_FRL_4            (0x10UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000010 */

+#define SAI_xFRCR_FRL_5            (0x20UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000020 */

+#define SAI_xFRCR_FRL_6            (0x40UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000040 */

+#define SAI_xFRCR_FRL_7            (0x80UL << SAI_xFRCR_FRL_Pos)                /*!< 0x00000080 */

+

+#define SAI_xFRCR_FSALL_Pos        (8U)

+#define SAI_xFRCR_FSALL_Msk        (0x7FUL << SAI_xFRCR_FSALL_Pos)             /*!< 0x00007F00 */

+#define SAI_xFRCR_FSALL            SAI_xFRCR_FSALL_Msk                         /*!<FSALL[6:0] (Frame Synchronization Active Level Length)  */

+#define SAI_xFRCR_FSALL_0          (0x01UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000100 */

+#define SAI_xFRCR_FSALL_1          (0x02UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000200 */

+#define SAI_xFRCR_FSALL_2          (0x04UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000400 */

+#define SAI_xFRCR_FSALL_3          (0x08UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00000800 */

+#define SAI_xFRCR_FSALL_4          (0x10UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00001000 */

+#define SAI_xFRCR_FSALL_5          (0x20UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00002000 */

+#define SAI_xFRCR_FSALL_6          (0x40UL << SAI_xFRCR_FSALL_Pos)              /*!< 0x00004000 */

+

+#define SAI_xFRCR_FSDEF_Pos        (16U)

+#define SAI_xFRCR_FSDEF_Msk        (0x1UL << SAI_xFRCR_FSDEF_Pos)              /*!< 0x00010000 */

+#define SAI_xFRCR_FSDEF            SAI_xFRCR_FSDEF_Msk                         /*!<Frame Synchronization Definition  */

+#define SAI_xFRCR_FSPOL_Pos        (17U)

+#define SAI_xFRCR_FSPOL_Msk        (0x1UL << SAI_xFRCR_FSPOL_Pos)              /*!< 0x00020000 */

+#define SAI_xFRCR_FSPOL            SAI_xFRCR_FSPOL_Msk                         /*!<Frame Synchronization POLarity    */

+#define SAI_xFRCR_FSOFF_Pos        (18U)

+#define SAI_xFRCR_FSOFF_Msk        (0x1UL << SAI_xFRCR_FSOFF_Pos)              /*!< 0x00040000 */

+#define SAI_xFRCR_FSOFF            SAI_xFRCR_FSOFF_Msk                         /*!<Frame Synchronization OFFset      */

+

+/* Legacy define */

+#define  SAI_xFRCR_FSPO                      SAI_xFRCR_FSPOL

+

+/******************  Bit definition for SAI_xSLOTR register  *******************/

+#define SAI_xSLOTR_FBOFF_Pos       (0U)

+#define SAI_xSLOTR_FBOFF_Msk       (0x1FUL << SAI_xSLOTR_FBOFF_Pos)            /*!< 0x0000001F */

+#define SAI_xSLOTR_FBOFF           SAI_xSLOTR_FBOFF_Msk                        /*!<FBOFF[4:0](First Bit Offset)  */

+#define SAI_xSLOTR_FBOFF_0         (0x01UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000001 */

+#define SAI_xSLOTR_FBOFF_1         (0x02UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000002 */

+#define SAI_xSLOTR_FBOFF_2         (0x04UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000004 */

+#define SAI_xSLOTR_FBOFF_3         (0x08UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000008 */

+#define SAI_xSLOTR_FBOFF_4         (0x10UL << SAI_xSLOTR_FBOFF_Pos)             /*!< 0x00000010 */

+

+#define SAI_xSLOTR_SLOTSZ_Pos      (6U)

+#define SAI_xSLOTR_SLOTSZ_Msk      (0x3UL << SAI_xSLOTR_SLOTSZ_Pos)            /*!< 0x000000C0 */

+#define SAI_xSLOTR_SLOTSZ          SAI_xSLOTR_SLOTSZ_Msk                       /*!<SLOTSZ[1:0] (Slot size)  */

+#define SAI_xSLOTR_SLOTSZ_0        (0x1UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000040 */

+#define SAI_xSLOTR_SLOTSZ_1        (0x2UL << SAI_xSLOTR_SLOTSZ_Pos)             /*!< 0x00000080 */

+

+#define SAI_xSLOTR_NBSLOT_Pos      (8U)

+#define SAI_xSLOTR_NBSLOT_Msk      (0xFUL << SAI_xSLOTR_NBSLOT_Pos)            /*!< 0x00000F00 */

+#define SAI_xSLOTR_NBSLOT          SAI_xSLOTR_NBSLOT_Msk                       /*!<NBSLOT[3:0] (Number of Slot in audio Frame)  */

+#define SAI_xSLOTR_NBSLOT_0        (0x1UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000100 */

+#define SAI_xSLOTR_NBSLOT_1        (0x2UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000200 */

+#define SAI_xSLOTR_NBSLOT_2        (0x4UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000400 */

+#define SAI_xSLOTR_NBSLOT_3        (0x8UL << SAI_xSLOTR_NBSLOT_Pos)             /*!< 0x00000800 */

+

+#define SAI_xSLOTR_SLOTEN_Pos      (16U)

+#define SAI_xSLOTR_SLOTEN_Msk      (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos)         /*!< 0xFFFF0000 */

+#define SAI_xSLOTR_SLOTEN          SAI_xSLOTR_SLOTEN_Msk                       /*!<SLOTEN[15:0] (Slot Enable)  */

+

+/*******************  Bit definition for SAI_xIMR register  *******************/

+#define SAI_xIMR_OVRUDRIE_Pos      (0U)

+#define SAI_xIMR_OVRUDRIE_Msk      (0x1UL << SAI_xIMR_OVRUDRIE_Pos)            /*!< 0x00000001 */

+#define SAI_xIMR_OVRUDRIE          SAI_xIMR_OVRUDRIE_Msk                       /*!<Overrun underrun interrupt enable                              */

+#define SAI_xIMR_MUTEDETIE_Pos     (1U)

+#define SAI_xIMR_MUTEDETIE_Msk     (0x1UL << SAI_xIMR_MUTEDETIE_Pos)           /*!< 0x00000002 */

+#define SAI_xIMR_MUTEDETIE         SAI_xIMR_MUTEDETIE_Msk                      /*!<Mute detection interrupt enable                                */

+#define SAI_xIMR_WCKCFGIE_Pos      (2U)

+#define SAI_xIMR_WCKCFGIE_Msk      (0x1UL << SAI_xIMR_WCKCFGIE_Pos)            /*!< 0x00000004 */

+#define SAI_xIMR_WCKCFGIE          SAI_xIMR_WCKCFGIE_Msk                       /*!<Wrong Clock Configuration interrupt enable                     */

+#define SAI_xIMR_FREQIE_Pos        (3U)

+#define SAI_xIMR_FREQIE_Msk        (0x1UL << SAI_xIMR_FREQIE_Pos)              /*!< 0x00000008 */

+#define SAI_xIMR_FREQIE            SAI_xIMR_FREQIE_Msk                         /*!<FIFO request interrupt enable                                  */

+#define SAI_xIMR_CNRDYIE_Pos       (4U)

+#define SAI_xIMR_CNRDYIE_Msk       (0x1UL << SAI_xIMR_CNRDYIE_Pos)             /*!< 0x00000010 */

+#define SAI_xIMR_CNRDYIE           SAI_xIMR_CNRDYIE_Msk                        /*!<Codec not ready interrupt enable                               */

+#define SAI_xIMR_AFSDETIE_Pos      (5U)

+#define SAI_xIMR_AFSDETIE_Msk      (0x1UL << SAI_xIMR_AFSDETIE_Pos)            /*!< 0x00000020 */

+#define SAI_xIMR_AFSDETIE          SAI_xIMR_AFSDETIE_Msk                       /*!<Anticipated frame synchronization detection interrupt enable   */

+#define SAI_xIMR_LFSDETIE_Pos      (6U)

+#define SAI_xIMR_LFSDETIE_Msk      (0x1UL << SAI_xIMR_LFSDETIE_Pos)            /*!< 0x00000040 */

+#define SAI_xIMR_LFSDETIE          SAI_xIMR_LFSDETIE_Msk                       /*!<Late frame synchronization detection interrupt enable          */

+

+/********************  Bit definition for SAI_xSR register  *******************/

+#define SAI_xSR_OVRUDR_Pos         (0U)

+#define SAI_xSR_OVRUDR_Msk         (0x1UL << SAI_xSR_OVRUDR_Pos)               /*!< 0x00000001 */

+#define SAI_xSR_OVRUDR             SAI_xSR_OVRUDR_Msk                          /*!<Overrun underrun                               */

+#define SAI_xSR_MUTEDET_Pos        (1U)

+#define SAI_xSR_MUTEDET_Msk        (0x1UL << SAI_xSR_MUTEDET_Pos)              /*!< 0x00000002 */

+#define SAI_xSR_MUTEDET            SAI_xSR_MUTEDET_Msk                         /*!<Mute detection                                 */

+#define SAI_xSR_WCKCFG_Pos         (2U)

+#define SAI_xSR_WCKCFG_Msk         (0x1UL << SAI_xSR_WCKCFG_Pos)               /*!< 0x00000004 */

+#define SAI_xSR_WCKCFG             SAI_xSR_WCKCFG_Msk                          /*!<Wrong Clock Configuration                      */

+#define SAI_xSR_FREQ_Pos           (3U)

+#define SAI_xSR_FREQ_Msk           (0x1UL << SAI_xSR_FREQ_Pos)                 /*!< 0x00000008 */

+#define SAI_xSR_FREQ               SAI_xSR_FREQ_Msk                            /*!<FIFO request                                   */

+#define SAI_xSR_CNRDY_Pos          (4U)

+#define SAI_xSR_CNRDY_Msk          (0x1UL << SAI_xSR_CNRDY_Pos)                /*!< 0x00000010 */

+#define SAI_xSR_CNRDY              SAI_xSR_CNRDY_Msk                           /*!<Codec not ready                                */

+#define SAI_xSR_AFSDET_Pos         (5U)

+#define SAI_xSR_AFSDET_Msk         (0x1UL << SAI_xSR_AFSDET_Pos)               /*!< 0x00000020 */

+#define SAI_xSR_AFSDET             SAI_xSR_AFSDET_Msk                          /*!<Anticipated frame synchronization detection    */

+#define SAI_xSR_LFSDET_Pos         (6U)

+#define SAI_xSR_LFSDET_Msk         (0x1UL << SAI_xSR_LFSDET_Pos)               /*!< 0x00000040 */

+#define SAI_xSR_LFSDET             SAI_xSR_LFSDET_Msk                          /*!<Late frame synchronization detection           */

+

+#define SAI_xSR_FLVL_Pos           (16U)

+#define SAI_xSR_FLVL_Msk           (0x7UL << SAI_xSR_FLVL_Pos)                 /*!< 0x00070000 */

+#define SAI_xSR_FLVL               SAI_xSR_FLVL_Msk                            /*!<FLVL[2:0] (FIFO Level Threshold)               */

+#define SAI_xSR_FLVL_0             (0x1UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00010000 */

+#define SAI_xSR_FLVL_1             (0x2UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00020000 */

+#define SAI_xSR_FLVL_2             (0x4UL << SAI_xSR_FLVL_Pos)                  /*!< 0x00040000 */

+

+/******************  Bit definition for SAI_xCLRFR register  ******************/

+#define SAI_xCLRFR_COVRUDR_Pos     (0U)

+#define SAI_xCLRFR_COVRUDR_Msk     (0x1UL << SAI_xCLRFR_COVRUDR_Pos)           /*!< 0x00000001 */

+#define SAI_xCLRFR_COVRUDR         SAI_xCLRFR_COVRUDR_Msk                      /*!<Clear Overrun underrun                               */

+#define SAI_xCLRFR_CMUTEDET_Pos    (1U)

+#define SAI_xCLRFR_CMUTEDET_Msk    (0x1UL << SAI_xCLRFR_CMUTEDET_Pos)          /*!< 0x00000002 */

+#define SAI_xCLRFR_CMUTEDET        SAI_xCLRFR_CMUTEDET_Msk                     /*!<Clear Mute detection                                 */

+#define SAI_xCLRFR_CWCKCFG_Pos     (2U)

+#define SAI_xCLRFR_CWCKCFG_Msk     (0x1UL << SAI_xCLRFR_CWCKCFG_Pos)           /*!< 0x00000004 */

+#define SAI_xCLRFR_CWCKCFG         SAI_xCLRFR_CWCKCFG_Msk                      /*!<Clear Wrong Clock Configuration                      */

+#define SAI_xCLRFR_CFREQ_Pos       (3U)

+#define SAI_xCLRFR_CFREQ_Msk       (0x1UL << SAI_xCLRFR_CFREQ_Pos)             /*!< 0x00000008 */

+#define SAI_xCLRFR_CFREQ           SAI_xCLRFR_CFREQ_Msk                        /*!<Clear FIFO request                                   */

+#define SAI_xCLRFR_CCNRDY_Pos      (4U)

+#define SAI_xCLRFR_CCNRDY_Msk      (0x1UL << SAI_xCLRFR_CCNRDY_Pos)            /*!< 0x00000010 */

+#define SAI_xCLRFR_CCNRDY          SAI_xCLRFR_CCNRDY_Msk                       /*!<Clear Codec not ready                                */

+#define SAI_xCLRFR_CAFSDET_Pos     (5U)

+#define SAI_xCLRFR_CAFSDET_Msk     (0x1UL << SAI_xCLRFR_CAFSDET_Pos)           /*!< 0x00000020 */

+#define SAI_xCLRFR_CAFSDET         SAI_xCLRFR_CAFSDET_Msk                      /*!<Clear Anticipated frame synchronization detection    */

+#define SAI_xCLRFR_CLFSDET_Pos     (6U)

+#define SAI_xCLRFR_CLFSDET_Msk     (0x1UL << SAI_xCLRFR_CLFSDET_Pos)           /*!< 0x00000040 */

+#define SAI_xCLRFR_CLFSDET         SAI_xCLRFR_CLFSDET_Msk                      /*!<Clear Late frame synchronization detection           */

+

+/******************  Bit definition for SAI_xDR register  *********************/

+#define SAI_xDR_DATA_Pos           (0U)

+#define SAI_xDR_DATA_Msk           (0xFFFFFFFFUL << SAI_xDR_DATA_Pos)          /*!< 0xFFFFFFFF */

+#define SAI_xDR_DATA               SAI_xDR_DATA_Msk

+

+/*******************  Bit definition for SAI_PDMCR register  ******************/

+#define SAI_PDMCR_PDMEN_Pos        (0U)

+#define SAI_PDMCR_PDMEN_Msk        (0x1UL << SAI_PDMCR_PDMEN_Pos)              /*!< 0x00000001 */

+#define SAI_PDMCR_PDMEN            SAI_PDMCR_PDMEN_Msk                         /*!<PDM Enable                                          */

+

+#define SAI_PDMCR_MICNBR_Pos       (4U)

+#define SAI_PDMCR_MICNBR_Msk       (0x3UL << SAI_PDMCR_MICNBR_Pos)             /*!< 0x00000030 */

+#define SAI_PDMCR_MICNBR           SAI_PDMCR_MICNBR_Msk                        /*!<Number of microphones                               */

+#define SAI_PDMCR_MICNBR_0         (0x1UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000010 */

+#define SAI_PDMCR_MICNBR_1         (0x2UL << SAI_PDMCR_MICNBR_Pos)              /*!< 0x00000020 */

+

+#define SAI_PDMCR_CKEN1_Pos        (8U)

+#define SAI_PDMCR_CKEN1_Msk        (0x1UL << SAI_PDMCR_CKEN1_Pos)              /*!< 0x00000100 */

+#define SAI_PDMCR_CKEN1            SAI_PDMCR_CKEN1_Msk                         /*!<Clock enable of bitstream clock number 1            */

+#define SAI_PDMCR_CKEN2_Pos        (9U)

+#define SAI_PDMCR_CKEN2_Msk        (0x1UL << SAI_PDMCR_CKEN2_Pos)              /*!< 0x00000200 */

+#define SAI_PDMCR_CKEN2            SAI_PDMCR_CKEN2_Msk                         /*!<Clock enable of bitstream clock number 2            */

+#define SAI_PDMCR_CKEN3_Pos        (10U)

+#define SAI_PDMCR_CKEN3_Msk        (0x1UL << SAI_PDMCR_CKEN3_Pos)              /*!< 0x00000400 */

+#define SAI_PDMCR_CKEN3            SAI_PDMCR_CKEN3_Msk                         /*!<Clock enable of bitstream clock number 3            */

+#define SAI_PDMCR_CKEN4_Pos        (11U)

+#define SAI_PDMCR_CKEN4_Msk        (0x1UL << SAI_PDMCR_CKEN4_Pos)              /*!< 0x00000800 */

+#define SAI_PDMCR_CKEN4            SAI_PDMCR_CKEN4_Msk                         /*!<Clock enable of bitstream clock number 4            */

+

+/******************  Bit definition for SAI_PDMDLY register  ******************/

+#define SAI_PDMDLY_DLYM1L_Pos      (0U)

+#define SAI_PDMDLY_DLYM1L_Msk      (0x7UL << SAI_PDMDLY_DLYM1L_Pos)            /*!< 0x00000007 */

+#define SAI_PDMDLY_DLYM1L          SAI_PDMDLY_DLYM1L_Msk                       /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */

+#define SAI_PDMDLY_DLYM1L_0        (0x1UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000001 */

+#define SAI_PDMDLY_DLYM1L_1        (0x2UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000002 */

+#define SAI_PDMDLY_DLYM1L_2        (0x4UL << SAI_PDMDLY_DLYM1L_Pos)             /*!< 0x00000004 */

+

+#define SAI_PDMDLY_DLYM1R_Pos      (4U)

+#define SAI_PDMDLY_DLYM1R_Msk      (0x7UL << SAI_PDMDLY_DLYM1R_Pos)            /*!< 0x00000070 */

+#define SAI_PDMDLY_DLYM1R          SAI_PDMDLY_DLYM1R_Msk                       /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */

+#define SAI_PDMDLY_DLYM1R_0        (0x1UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000010 */

+#define SAI_PDMDLY_DLYM1R_1        (0x2UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000020 */

+#define SAI_PDMDLY_DLYM1R_2        (0x4UL << SAI_PDMDLY_DLYM1R_Pos)             /*!< 0x00000040 */

+

+#define SAI_PDMDLY_DLYM2L_Pos      (8U)

+#define SAI_PDMDLY_DLYM2L_Msk      (0x7UL << SAI_PDMDLY_DLYM2L_Pos)            /*!< 0x00000700 */

+#define SAI_PDMDLY_DLYM2L          SAI_PDMDLY_DLYM2L_Msk                       /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */

+#define SAI_PDMDLY_DLYM2L_0        (0x1UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000100 */

+#define SAI_PDMDLY_DLYM2L_1        (0x2UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000200 */

+#define SAI_PDMDLY_DLYM2L_2        (0x4UL << SAI_PDMDLY_DLYM2L_Pos)             /*!< 0x00000400 */

+

+#define SAI_PDMDLY_DLYM2R_Pos      (12U)

+#define SAI_PDMDLY_DLYM2R_Msk      (0x7UL << SAI_PDMDLY_DLYM2R_Pos)            /*!< 0x00007000 */

+#define SAI_PDMDLY_DLYM2R          SAI_PDMDLY_DLYM2R_Msk                       /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/

+#define SAI_PDMDLY_DLYM2R_0        (0x1UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00001000 */

+#define SAI_PDMDLY_DLYM2R_1        (0x2UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00002000 */

+#define SAI_PDMDLY_DLYM2R_2        (0x4UL << SAI_PDMDLY_DLYM2R_Pos)             /*!< 0x00004000 */

+

+#define SAI_PDMDLY_DLYM3L_Pos      (16U)

+#define SAI_PDMDLY_DLYM3L_Msk      (0x7UL << SAI_PDMDLY_DLYM3L_Pos)            /*!< 0x00070000 */

+#define SAI_PDMDLY_DLYM3L          SAI_PDMDLY_DLYM3L_Msk                       /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/

+#define SAI_PDMDLY_DLYM3L_0        (0x1UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00010000 */

+#define SAI_PDMDLY_DLYM3L_1        (0x2UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00020000 */

+#define SAI_PDMDLY_DLYM3L_2        (0x4UL << SAI_PDMDLY_DLYM3L_Pos)             /*!< 0x00040000 */

+

+#define SAI_PDMDLY_DLYM3R_Pos      (20U)

+#define SAI_PDMDLY_DLYM3R_Msk      (0x7UL << SAI_PDMDLY_DLYM3R_Pos)            /*!< 0x00700000 */

+#define SAI_PDMDLY_DLYM3R          SAI_PDMDLY_DLYM3R_Msk                       /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/

+#define SAI_PDMDLY_DLYM3R_0        (0x1UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00100000 */

+#define SAI_PDMDLY_DLYM3R_1        (0x2UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00200000 */

+#define SAI_PDMDLY_DLYM3R_2        (0x4UL << SAI_PDMDLY_DLYM3R_Pos)             /*!< 0x00400000 */

+

+#define SAI_PDMDLY_DLYM4L_Pos      (24U)

+#define SAI_PDMDLY_DLYM4L_Msk      (0x7UL << SAI_PDMDLY_DLYM4L_Pos)            /*!< 0x07000000 */

+#define SAI_PDMDLY_DLYM4L          SAI_PDMDLY_DLYM4L_Msk                       /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/

+#define SAI_PDMDLY_DLYM4L_0        (0x1UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x01000000 */

+#define SAI_PDMDLY_DLYM4L_1        (0x2UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x02000000 */

+#define SAI_PDMDLY_DLYM4L_2        (0x4UL << SAI_PDMDLY_DLYM4L_Pos)             /*!< 0x04000000 */

+

+#define SAI_PDMDLY_DLYM4R_Pos      (28U)

+#define SAI_PDMDLY_DLYM4R_Msk      (0x7UL << SAI_PDMDLY_DLYM4R_Pos)            /*!< 0x70000000 */

+#define SAI_PDMDLY_DLYM4R          SAI_PDMDLY_DLYM4R_Msk                       /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/

+#define SAI_PDMDLY_DLYM4R_0        (0x1UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x10000000 */

+#define SAI_PDMDLY_DLYM4R_1        (0x2UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x20000000 */

+#define SAI_PDMDLY_DLYM4R_2        (0x4UL << SAI_PDMDLY_DLYM4R_Pos)             /*!< 0x40000000 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                           SDMMC Interface                                  */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for SDMMC_POWER register  ******************/

+#define SDMMC_POWER_PWRCTRL_Pos          (0U)

+#define SDMMC_POWER_PWRCTRL_Msk          (0x3UL << SDMMC_POWER_PWRCTRL_Pos)    /*!< 0x00000003 */

+#define SDMMC_POWER_PWRCTRL              SDMMC_POWER_PWRCTRL_Msk               /*!<PWRCTRL[1:0] bits (Power supply control bits) */

+#define SDMMC_POWER_PWRCTRL_0            (0x1UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000001 */

+#define SDMMC_POWER_PWRCTRL_1            (0x2UL << SDMMC_POWER_PWRCTRL_Pos)     /*!< 0x00000002 */

+#define SDMMC_POWER_VSWITCH_Pos          (2U)

+#define SDMMC_POWER_VSWITCH_Msk          (0x1UL << SDMMC_POWER_VSWITCH_Pos)    /*!< 0x00000004 */

+#define SDMMC_POWER_VSWITCH              SDMMC_POWER_VSWITCH_Msk               /*!<Voltage switch sequence start */

+#define SDMMC_POWER_VSWITCHEN_Pos        (3U)

+#define SDMMC_POWER_VSWITCHEN_Msk        (0x1UL << SDMMC_POWER_VSWITCHEN_Pos)  /*!< 0x00000008 */

+#define SDMMC_POWER_VSWITCHEN            SDMMC_POWER_VSWITCHEN_Msk             /*!<Voltage switch procedure enable */

+#define SDMMC_POWER_DIRPOL_Pos           (4U)

+#define SDMMC_POWER_DIRPOL_Msk           (0x1UL << SDMMC_POWER_DIRPOL_Pos)     /*!< 0x00000010 */

+#define SDMMC_POWER_DIRPOL               SDMMC_POWER_DIRPOL_Msk                /*!<Data and Command direction signals polarity selection */

+

+/******************  Bit definition for SDMMC_CLKCR register  ******************/

+#define SDMMC_CLKCR_CLKDIV_Pos           (0U)

+#define SDMMC_CLKCR_CLKDIV_Msk           (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos)   /*!< 0x000003FF */

+#define SDMMC_CLKCR_CLKDIV               SDMMC_CLKCR_CLKDIV_Msk                /*!<Clock divide factor             */

+#define SDMMC_CLKCR_PWRSAV_Pos           (12U)

+#define SDMMC_CLKCR_PWRSAV_Msk           (0x1UL << SDMMC_CLKCR_PWRSAV_Pos)     /*!< 0x00001000 */

+#define SDMMC_CLKCR_PWRSAV               SDMMC_CLKCR_PWRSAV_Msk                /*!<Power saving configuration bit  */

+

+#define SDMMC_CLKCR_WIDBUS_Pos           (14U)

+#define SDMMC_CLKCR_WIDBUS_Msk           (0x3UL << SDMMC_CLKCR_WIDBUS_Pos)     /*!< 0x0000C000 */

+#define SDMMC_CLKCR_WIDBUS               SDMMC_CLKCR_WIDBUS_Msk                /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */

+#define SDMMC_CLKCR_WIDBUS_0             (0x1UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00004000 */

+#define SDMMC_CLKCR_WIDBUS_1             (0x2UL << SDMMC_CLKCR_WIDBUS_Pos)      /*!< 0x00008000 */

+

+#define SDMMC_CLKCR_NEGEDGE_Pos          (16U)

+#define SDMMC_CLKCR_NEGEDGE_Msk          (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos)    /*!< 0x00010000 */

+#define SDMMC_CLKCR_NEGEDGE              SDMMC_CLKCR_NEGEDGE_Msk               /*!<SDMMC_CK dephasing selection bit */

+#define SDMMC_CLKCR_HWFC_EN_Pos          (17U)

+#define SDMMC_CLKCR_HWFC_EN_Msk          (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos)    /*!< 0x00020000 */

+#define SDMMC_CLKCR_HWFC_EN              SDMMC_CLKCR_HWFC_EN_Msk               /*!<HW Flow Control enable           */

+#define SDMMC_CLKCR_DDR_Pos              (18U)

+#define SDMMC_CLKCR_DDR_Msk              (0x1UL << SDMMC_CLKCR_DDR_Pos)        /*!< 0x00040000 */

+#define SDMMC_CLKCR_DDR                  SDMMC_CLKCR_DDR_Msk                   /*!<Data rate signaling selection    */

+#define SDMMC_CLKCR_BUSSPEED_Pos         (19U)

+#define SDMMC_CLKCR_BUSSPEED_Msk         (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos)   /*!< 0x00080000 */

+#define SDMMC_CLKCR_BUSSPEED             SDMMC_CLKCR_BUSSPEED_Msk              /*!<Bus speed mode selection         */

+#define SDMMC_CLKCR_SELCLKRX_Pos         (20U)

+#define SDMMC_CLKCR_SELCLKRX_Msk         (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos)   /*!< 0x00300000 */

+#define SDMMC_CLKCR_SELCLKRX             SDMMC_CLKCR_SELCLKRX_Msk              /*!<SELCLKRX[1:0] bits (Receive clock selection) */

+#define SDMMC_CLKCR_SELCLKRX_0           (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00100000 */

+#define SDMMC_CLKCR_SELCLKRX_1           (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos)    /*!< 0x00200000 */

+

+/*******************  Bit definition for SDMMC_ARG register  *******************/

+#define SDMMC_ARG_CMDARG_Pos             (0U)

+#define SDMMC_ARG_CMDARG_Msk             (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_ARG_CMDARG                 SDMMC_ARG_CMDARG_Msk                  /*!<Command argument */

+

+/*******************  Bit definition for SDMMC_CMD register  *******************/

+#define SDMMC_CMD_CMDINDEX_Pos           (0U)

+#define SDMMC_CMD_CMDINDEX_Msk           (0x3FUL << SDMMC_CMD_CMDINDEX_Pos)    /*!< 0x0000003F */

+#define SDMMC_CMD_CMDINDEX               SDMMC_CMD_CMDINDEX_Msk                /*!<Command Index                               */

+#define SDMMC_CMD_CMDTRANS_Pos           (6U)

+#define SDMMC_CMD_CMDTRANS_Msk           (0x1UL << SDMMC_CMD_CMDTRANS_Pos)     /*!< 0x00000040 */

+#define SDMMC_CMD_CMDTRANS               SDMMC_CMD_CMDTRANS_Msk                /*!<CPSM Treats command as a Data Transfer      */

+#define SDMMC_CMD_CMDSTOP_Pos            (7U)

+#define SDMMC_CMD_CMDSTOP_Msk            (0x1UL << SDMMC_CMD_CMDSTOP_Pos)      /*!< 0x00000080 */

+#define SDMMC_CMD_CMDSTOP                SDMMC_CMD_CMDSTOP_Msk                 /*!<CPSM Treats command as a Stop               */

+

+#define SDMMC_CMD_WAITRESP_Pos           (8U)

+#define SDMMC_CMD_WAITRESP_Msk           (0x3UL << SDMMC_CMD_WAITRESP_Pos)     /*!< 0x00000300 */

+#define SDMMC_CMD_WAITRESP               SDMMC_CMD_WAITRESP_Msk                /*!<WAITRESP[1:0] bits (Wait for response bits) */

+#define SDMMC_CMD_WAITRESP_0             (0x1UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000100 */

+#define SDMMC_CMD_WAITRESP_1             (0x2UL << SDMMC_CMD_WAITRESP_Pos)      /*!< 0x00000200 */

+

+#define SDMMC_CMD_WAITINT_Pos            (10U)

+#define SDMMC_CMD_WAITINT_Msk            (0x1UL << SDMMC_CMD_WAITINT_Pos)      /*!< 0x00000400 */

+#define SDMMC_CMD_WAITINT                SDMMC_CMD_WAITINT_Msk                 /*!<CPSM Waits for Interrupt Request                               */

+#define SDMMC_CMD_WAITPEND_Pos           (11U)

+#define SDMMC_CMD_WAITPEND_Msk           (0x1UL << SDMMC_CMD_WAITPEND_Pos)     /*!< 0x00000800 */

+#define SDMMC_CMD_WAITPEND               SDMMC_CMD_WAITPEND_Msk                /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */

+#define SDMMC_CMD_CPSMEN_Pos             (12U)

+#define SDMMC_CMD_CPSMEN_Msk             (0x1UL << SDMMC_CMD_CPSMEN_Pos)       /*!< 0x00001000 */

+#define SDMMC_CMD_CPSMEN                 SDMMC_CMD_CPSMEN_Msk                  /*!<Command path state machine (CPSM) Enable bit                   */

+#define SDMMC_CMD_DTHOLD_Pos             (13U)

+#define SDMMC_CMD_DTHOLD_Msk             (0x1UL << SDMMC_CMD_DTHOLD_Pos)       /*!< 0x00002000 */

+#define SDMMC_CMD_DTHOLD                 SDMMC_CMD_DTHOLD_Msk                  /*!<Hold new data block transmission and reception in the DPSM     */

+#define SDMMC_CMD_BOOTMODE_Pos           (14U)

+#define SDMMC_CMD_BOOTMODE_Msk           (0x1UL << SDMMC_CMD_BOOTMODE_Pos)     /*!< 0x00004000 */

+#define SDMMC_CMD_BOOTMODE               SDMMC_CMD_BOOTMODE_Msk                /*!<Boot mode                                                      */

+#define SDMMC_CMD_BOOTEN_Pos             (15U)

+#define SDMMC_CMD_BOOTEN_Msk             (0x1UL << SDMMC_CMD_BOOTEN_Pos)       /*!< 0x00008000 */

+#define SDMMC_CMD_BOOTEN                 SDMMC_CMD_BOOTEN_Msk                  /*!<Enable Boot mode procedure                                     */

+#define SDMMC_CMD_CMDSUSPEND_Pos         (16U)

+#define SDMMC_CMD_CMDSUSPEND_Msk         (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos)   /*!< 0x00010000 */

+#define SDMMC_CMD_CMDSUSPEND             SDMMC_CMD_CMDSUSPEND_Msk              /*!<CPSM Treats command as a Suspend or Resume command             */

+

+/*****************  Bit definition for SDMMC_RESPCMD register  *****************/

+#define SDMMC_RESPCMD_RESPCMD_Pos        (0U)

+#define SDMMC_RESPCMD_RESPCMD_Msk        (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */

+#define SDMMC_RESPCMD_RESPCMD            SDMMC_RESPCMD_RESPCMD_Msk             /*!<Response command index */

+

+/******************  Bit definition for SDMMC_RESP0 register  ******************/

+#define SDMMC_RESP0_CARDSTATUS0_Pos      (0U)

+#define SDMMC_RESP0_CARDSTATUS0_Msk      (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP0_CARDSTATUS0          SDMMC_RESP0_CARDSTATUS0_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP1 register  ******************/

+#define SDMMC_RESP1_CARDSTATUS1_Pos      (0U)

+#define SDMMC_RESP1_CARDSTATUS1_Msk      (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP1_CARDSTATUS1          SDMMC_RESP1_CARDSTATUS1_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP2 register  ******************/

+#define SDMMC_RESP2_CARDSTATUS2_Pos      (0U)

+#define SDMMC_RESP2_CARDSTATUS2_Msk      (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP2_CARDSTATUS2          SDMMC_RESP2_CARDSTATUS2_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP3 register  ******************/

+#define SDMMC_RESP3_CARDSTATUS3_Pos      (0U)

+#define SDMMC_RESP3_CARDSTATUS3_Msk      (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP3_CARDSTATUS3          SDMMC_RESP3_CARDSTATUS3_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_RESP4 register  ******************/

+#define SDMMC_RESP4_CARDSTATUS4_Pos      (0U)

+#define SDMMC_RESP4_CARDSTATUS4_Msk      (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_RESP4_CARDSTATUS4          SDMMC_RESP4_CARDSTATUS4_Msk           /*!<Card Status */

+

+/******************  Bit definition for SDMMC_DTIMER register  *****************/

+#define SDMMC_DTIMER_DATATIME_Pos        (0U)

+#define SDMMC_DTIMER_DATATIME_Msk        (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_DTIMER_DATATIME            SDMMC_DTIMER_DATATIME_Msk             /*!<Data timeout period. */

+

+/******************  Bit definition for SDMMC_DLEN register  *******************/

+#define SDMMC_DLEN_DATALENGTH_Pos        (0U)

+#define SDMMC_DLEN_DATALENGTH_Msk        (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_DLEN_DATALENGTH            SDMMC_DLEN_DATALENGTH_Msk             /*!<Data length value    */

+

+/******************  Bit definition for SDMMC_DCTRL register  ******************/

+#define SDMMC_DCTRL_DTEN_Pos             (0U)

+#define SDMMC_DCTRL_DTEN_Msk             (0x1UL << SDMMC_DCTRL_DTEN_Pos)       /*!< 0x00000001 */

+#define SDMMC_DCTRL_DTEN                 SDMMC_DCTRL_DTEN_Msk                  /*!<Data transfer enabled bit                */

+#define SDMMC_DCTRL_DTDIR_Pos            (1U)

+#define SDMMC_DCTRL_DTDIR_Msk            (0x1UL << SDMMC_DCTRL_DTDIR_Pos)      /*!< 0x00000002 */

+#define SDMMC_DCTRL_DTDIR                SDMMC_DCTRL_DTDIR_Msk                 /*!<Data transfer direction selection        */

+#define SDMMC_DCTRL_DTMODE_Pos           (2U)

+#define SDMMC_DCTRL_DTMODE_Msk           (0x3UL << SDMMC_DCTRL_DTMODE_Pos)     /*!< 0x0000000C */

+#define SDMMC_DCTRL_DTMODE               SDMMC_DCTRL_DTMODE_Msk                /*!<DTMODE[1:0] Data transfer mode selection */

+#define SDMMC_DCTRL_DTMODE_0             (0x1UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000004 */

+#define SDMMC_DCTRL_DTMODE_1             (0x2UL << SDMMC_DCTRL_DTMODE_Pos)      /*!< 0x00000008 */

+

+#define SDMMC_DCTRL_DBLOCKSIZE_Pos       (4U)

+#define SDMMC_DCTRL_DBLOCKSIZE_Msk       (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */

+#define SDMMC_DCTRL_DBLOCKSIZE           SDMMC_DCTRL_DBLOCKSIZE_Msk            /*!<DBLOCKSIZE[3:0] bits (Data block size) */

+#define SDMMC_DCTRL_DBLOCKSIZE_0         (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000010 */

+#define SDMMC_DCTRL_DBLOCKSIZE_1         (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000020 */

+#define SDMMC_DCTRL_DBLOCKSIZE_2         (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000040 */

+#define SDMMC_DCTRL_DBLOCKSIZE_3         (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos)  /*!< 0x00000080 */

+

+#define SDMMC_DCTRL_RWSTART_Pos          (8U)

+#define SDMMC_DCTRL_RWSTART_Msk          (0x1UL << SDMMC_DCTRL_RWSTART_Pos)    /*!< 0x00000100 */

+#define SDMMC_DCTRL_RWSTART              SDMMC_DCTRL_RWSTART_Msk               /*!<Read wait start                                 */

+#define SDMMC_DCTRL_RWSTOP_Pos           (9U)

+#define SDMMC_DCTRL_RWSTOP_Msk           (0x1UL << SDMMC_DCTRL_RWSTOP_Pos)     /*!< 0x00000200 */

+#define SDMMC_DCTRL_RWSTOP               SDMMC_DCTRL_RWSTOP_Msk                /*!<Read wait stop                                  */

+#define SDMMC_DCTRL_RWMOD_Pos            (10U)

+#define SDMMC_DCTRL_RWMOD_Msk            (0x1UL << SDMMC_DCTRL_RWMOD_Pos)      /*!< 0x00000400 */

+#define SDMMC_DCTRL_RWMOD                SDMMC_DCTRL_RWMOD_Msk                 /*!<Read wait mode                                  */

+#define SDMMC_DCTRL_SDIOEN_Pos           (11U)

+#define SDMMC_DCTRL_SDIOEN_Msk           (0x1UL << SDMMC_DCTRL_SDIOEN_Pos)     /*!< 0x00000800 */

+#define SDMMC_DCTRL_SDIOEN               SDMMC_DCTRL_SDIOEN_Msk                /*!<SD I/O enable functions                         */

+#define SDMMC_DCTRL_BOOTACKEN_Pos        (12U)

+#define SDMMC_DCTRL_BOOTACKEN_Msk        (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos)  /*!< 0x00001000 */

+#define SDMMC_DCTRL_BOOTACKEN            SDMMC_DCTRL_BOOTACKEN_Msk             /*!<Enable the reception of the Boot Acknowledgment */

+#define SDMMC_DCTRL_FIFORST_Pos          (13U)

+#define SDMMC_DCTRL_FIFORST_Msk          (0x1UL << SDMMC_DCTRL_FIFORST_Pos)    /*!< 0x00002000 */

+#define SDMMC_DCTRL_FIFORST              SDMMC_DCTRL_FIFORST_Msk               /*!<FIFO reset                                      */

+

+/******************  Bit definition for SDMMC_DCOUNT register  *****************/

+#define SDMMC_DCOUNT_DATACOUNT_Pos       (0U)

+#define SDMMC_DCOUNT_DATACOUNT_Msk       (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_DCOUNT_DATACOUNT           SDMMC_DCOUNT_DATACOUNT_Msk            /*!<Data count value */

+

+/******************  Bit definition for SDMMC_STA register  ********************/

+#define SDMMC_STA_CCRCFAIL_Pos           (0U)

+#define SDMMC_STA_CCRCFAIL_Msk           (0x1UL << SDMMC_STA_CCRCFAIL_Pos)     /*!< 0x00000001 */

+#define SDMMC_STA_CCRCFAIL               SDMMC_STA_CCRCFAIL_Msk                /*!<Command response received (CRC check failed)  */

+#define SDMMC_STA_DCRCFAIL_Pos           (1U)

+#define SDMMC_STA_DCRCFAIL_Msk           (0x1UL << SDMMC_STA_DCRCFAIL_Pos)     /*!< 0x00000002 */

+#define SDMMC_STA_DCRCFAIL               SDMMC_STA_DCRCFAIL_Msk                /*!<Data block sent/received (CRC check failed)   */

+#define SDMMC_STA_CTIMEOUT_Pos           (2U)

+#define SDMMC_STA_CTIMEOUT_Msk           (0x1UL << SDMMC_STA_CTIMEOUT_Pos)     /*!< 0x00000004 */

+#define SDMMC_STA_CTIMEOUT               SDMMC_STA_CTIMEOUT_Msk                /*!<Command response timeout                      */

+#define SDMMC_STA_DTIMEOUT_Pos           (3U)

+#define SDMMC_STA_DTIMEOUT_Msk           (0x1UL << SDMMC_STA_DTIMEOUT_Pos)     /*!< 0x00000008 */

+#define SDMMC_STA_DTIMEOUT               SDMMC_STA_DTIMEOUT_Msk                /*!<Data timeout                                  */

+#define SDMMC_STA_TXUNDERR_Pos           (4U)

+#define SDMMC_STA_TXUNDERR_Msk           (0x1UL << SDMMC_STA_TXUNDERR_Pos)     /*!< 0x00000010 */

+#define SDMMC_STA_TXUNDERR               SDMMC_STA_TXUNDERR_Msk                /*!<Transmit FIFO underrun error                  */

+#define SDMMC_STA_RXOVERR_Pos            (5U)

+#define SDMMC_STA_RXOVERR_Msk            (0x1UL << SDMMC_STA_RXOVERR_Pos)      /*!< 0x00000020 */

+#define SDMMC_STA_RXOVERR                SDMMC_STA_RXOVERR_Msk                 /*!<Received FIFO overrun error                   */

+#define SDMMC_STA_CMDREND_Pos            (6U)

+#define SDMMC_STA_CMDREND_Msk            (0x1UL << SDMMC_STA_CMDREND_Pos)      /*!< 0x00000040 */

+#define SDMMC_STA_CMDREND                SDMMC_STA_CMDREND_Msk                 /*!<Command response received (CRC check passed)  */

+#define SDMMC_STA_CMDSENT_Pos            (7U)

+#define SDMMC_STA_CMDSENT_Msk            (0x1UL << SDMMC_STA_CMDSENT_Pos)      /*!< 0x00000080 */

+#define SDMMC_STA_CMDSENT                SDMMC_STA_CMDSENT_Msk                 /*!<Command sent (no response required)           */

+#define SDMMC_STA_DATAEND_Pos            (8U)

+#define SDMMC_STA_DATAEND_Msk            (0x1UL << SDMMC_STA_DATAEND_Pos)      /*!< 0x00000100 */

+#define SDMMC_STA_DATAEND                SDMMC_STA_DATAEND_Msk                 /*!<Data end (data counter, SDIDCOUNT, is zero)   */

+#define SDMMC_STA_DHOLD_Pos              (9U)

+#define SDMMC_STA_DHOLD_Msk              (0x1UL << SDMMC_STA_DHOLD_Pos)        /*!< 0x00000200 */

+#define SDMMC_STA_DHOLD                  SDMMC_STA_DHOLD_Msk                   /*!<Data transfer Hold                                                      */

+#define SDMMC_STA_DBCKEND_Pos            (10U)

+#define SDMMC_STA_DBCKEND_Msk            (0x1UL << SDMMC_STA_DBCKEND_Pos)      /*!< 0x00000400 */

+#define SDMMC_STA_DBCKEND                SDMMC_STA_DBCKEND_Msk                 /*!<Data block sent/received (CRC check passed)   */

+#define SDMMC_STA_DABORT_Pos             (11U)

+#define SDMMC_STA_DABORT_Msk             (0x1UL << SDMMC_STA_DABORT_Pos)       /*!< 0x00000800 */

+#define SDMMC_STA_DABORT                 SDMMC_STA_DABORT_Msk                  /*!<Data transfer aborted by CMD12                                          */

+#define SDMMC_STA_DPSMACT_Pos            (12U)

+#define SDMMC_STA_DPSMACT_Msk            (0x1UL << SDMMC_STA_DPSMACT_Pos)      /*!< 0x00001000 */

+#define SDMMC_STA_DPSMACT                SDMMC_STA_DPSMACT_Msk                 /*!<Data path state machine active                                       */

+#define SDMMC_STA_CPSMACT_Pos            (13U)

+#define SDMMC_STA_CPSMACT_Msk            (0x1UL << SDMMC_STA_CPSMACT_Pos)      /*!< 0x00002000 */

+#define SDMMC_STA_CPSMACT                SDMMC_STA_CPSMACT_Msk                 /*!<Command path state machine active                                          */

+#define SDMMC_STA_TXFIFOHE_Pos           (14U)

+#define SDMMC_STA_TXFIFOHE_Msk           (0x1UL << SDMMC_STA_TXFIFOHE_Pos)     /*!< 0x00004000 */

+#define SDMMC_STA_TXFIFOHE               SDMMC_STA_TXFIFOHE_Msk                /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */

+#define SDMMC_STA_RXFIFOHF_Pos           (15U)

+#define SDMMC_STA_RXFIFOHF_Msk           (0x1UL << SDMMC_STA_RXFIFOHF_Pos)     /*!< 0x00008000 */

+#define SDMMC_STA_RXFIFOHF               SDMMC_STA_RXFIFOHF_Msk                /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */

+#define SDMMC_STA_TXFIFOF_Pos            (16U)

+#define SDMMC_STA_TXFIFOF_Msk            (0x1UL << SDMMC_STA_TXFIFOF_Pos)      /*!< 0x00010000 */

+#define SDMMC_STA_TXFIFOF                SDMMC_STA_TXFIFOF_Msk                 /*!<Transmit FIFO full                            */

+#define SDMMC_STA_RXFIFOF_Pos            (17U)

+#define SDMMC_STA_RXFIFOF_Msk            (0x1UL << SDMMC_STA_RXFIFOF_Pos)      /*!< 0x00020000 */

+#define SDMMC_STA_RXFIFOF                SDMMC_STA_RXFIFOF_Msk                 /*!<Receive FIFO full                             */

+#define SDMMC_STA_TXFIFOE_Pos            (18U)

+#define SDMMC_STA_TXFIFOE_Msk            (0x1UL << SDMMC_STA_TXFIFOE_Pos)      /*!< 0x00040000 */

+#define SDMMC_STA_TXFIFOE                SDMMC_STA_TXFIFOE_Msk                 /*!<Transmit FIFO empty                           */

+#define SDMMC_STA_RXFIFOE_Pos            (19U)

+#define SDMMC_STA_RXFIFOE_Msk            (0x1UL << SDMMC_STA_RXFIFOE_Pos)      /*!< 0x00080000 */

+#define SDMMC_STA_RXFIFOE                SDMMC_STA_RXFIFOE_Msk                 /*!<Receive FIFO empty                            */

+#define SDMMC_STA_BUSYD0_Pos             (20U)

+#define SDMMC_STA_BUSYD0_Msk             (0x1UL << SDMMC_STA_BUSYD0_Pos)       /*!< 0x00100000 */

+#define SDMMC_STA_BUSYD0                 SDMMC_STA_BUSYD0_Msk                  /*!<Inverted value of SDMMC_D0 line (Busy)                                  */

+#define SDMMC_STA_BUSYD0END_Pos          (21U)

+#define SDMMC_STA_BUSYD0END_Msk          (0x1UL << SDMMC_STA_BUSYD0END_Pos)    /*!< 0x00200000 */

+#define SDMMC_STA_BUSYD0END              SDMMC_STA_BUSYD0END_Msk               /*!<End of SDMMC_D0 Busy following a CMD response detected                  */

+#define SDMMC_STA_SDIOIT_Pos             (22U)

+#define SDMMC_STA_SDIOIT_Msk             (0x1UL << SDMMC_STA_SDIOIT_Pos)       /*!< 0x00400000 */

+#define SDMMC_STA_SDIOIT                 SDMMC_STA_SDIOIT_Msk                  /*!<SDIO interrupt received                                                 */

+#define SDMMC_STA_ACKFAIL_Pos            (23U)

+#define SDMMC_STA_ACKFAIL_Msk            (0x1UL << SDMMC_STA_ACKFAIL_Pos)      /*!< 0x00800000 */

+#define SDMMC_STA_ACKFAIL                SDMMC_STA_ACKFAIL_Msk                 /*!<Boot Acknowledgment received (BootAck check fail)                       */

+#define SDMMC_STA_ACKTIMEOUT_Pos         (24U)

+#define SDMMC_STA_ACKTIMEOUT_Msk         (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos)   /*!< 0x01000000 */

+#define SDMMC_STA_ACKTIMEOUT             SDMMC_STA_ACKTIMEOUT_Msk              /*!<Boot Acknowledgment timeout                                             */

+#define SDMMC_STA_VSWEND_Pos             (25U)

+#define SDMMC_STA_VSWEND_Msk             (0x1UL << SDMMC_STA_VSWEND_Pos)       /*!< 0x02000000 */

+#define SDMMC_STA_VSWEND                 SDMMC_STA_VSWEND_Msk                  /*!<Voltage switch critical timing section completion                       */

+#define SDMMC_STA_CKSTOP_Pos             (26U)

+#define SDMMC_STA_CKSTOP_Msk             (0x1UL << SDMMC_STA_CKSTOP_Pos)       /*!< 0x04000000 */

+#define SDMMC_STA_CKSTOP                 SDMMC_STA_CKSTOP_Msk                  /*!<SDMMC_CK stopped in Voltage switch procedure                            */

+#define SDMMC_STA_IDMATE_Pos             (27U)

+#define SDMMC_STA_IDMATE_Msk             (0x1UL << SDMMC_STA_IDMATE_Pos)       /*!< 0x08000000 */

+#define SDMMC_STA_IDMATE                 SDMMC_STA_IDMATE_Msk                  /*!<IDMA transfer error                                                     */

+#define SDMMC_STA_IDMABTC_Pos            (28U)

+#define SDMMC_STA_IDMABTC_Msk            (0x1UL << SDMMC_STA_IDMABTC_Pos)      /*!< 0x10000000 */

+#define SDMMC_STA_IDMABTC                SDMMC_STA_IDMABTC_Msk                 /*!<IDMA buffer transfer complete                                           */

+

+/*******************  Bit definition for SDMMC_ICR register  *******************/

+#define SDMMC_ICR_CCRCFAILC_Pos          (0U)

+#define SDMMC_ICR_CCRCFAILC_Msk          (0x1UL << SDMMC_ICR_CCRCFAILC_Pos)    /*!< 0x00000001 */

+#define SDMMC_ICR_CCRCFAILC              SDMMC_ICR_CCRCFAILC_Msk               /*!<CCRCFAIL flag clear bit */

+#define SDMMC_ICR_DCRCFAILC_Pos          (1U)

+#define SDMMC_ICR_DCRCFAILC_Msk          (0x1UL << SDMMC_ICR_DCRCFAILC_Pos)    /*!< 0x00000002 */

+#define SDMMC_ICR_DCRCFAILC              SDMMC_ICR_DCRCFAILC_Msk               /*!<DCRCFAIL flag clear bit */

+#define SDMMC_ICR_CTIMEOUTC_Pos          (2U)

+#define SDMMC_ICR_CTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos)    /*!< 0x00000004 */

+#define SDMMC_ICR_CTIMEOUTC              SDMMC_ICR_CTIMEOUTC_Msk               /*!<CTIMEOUT flag clear bit */

+#define SDMMC_ICR_DTIMEOUTC_Pos          (3U)

+#define SDMMC_ICR_DTIMEOUTC_Msk          (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos)    /*!< 0x00000008 */

+#define SDMMC_ICR_DTIMEOUTC              SDMMC_ICR_DTIMEOUTC_Msk               /*!<DTIMEOUT flag clear bit */

+#define SDMMC_ICR_TXUNDERRC_Pos          (4U)

+#define SDMMC_ICR_TXUNDERRC_Msk          (0x1UL << SDMMC_ICR_TXUNDERRC_Pos)    /*!< 0x00000010 */

+#define SDMMC_ICR_TXUNDERRC              SDMMC_ICR_TXUNDERRC_Msk               /*!<TXUNDERR flag clear bit */

+#define SDMMC_ICR_RXOVERRC_Pos           (5U)

+#define SDMMC_ICR_RXOVERRC_Msk           (0x1UL << SDMMC_ICR_RXOVERRC_Pos)     /*!< 0x00000020 */

+#define SDMMC_ICR_RXOVERRC               SDMMC_ICR_RXOVERRC_Msk                /*!<RXOVERR flag clear bit  */

+#define SDMMC_ICR_CMDRENDC_Pos           (6U)

+#define SDMMC_ICR_CMDRENDC_Msk           (0x1UL << SDMMC_ICR_CMDRENDC_Pos)     /*!< 0x00000040 */

+#define SDMMC_ICR_CMDRENDC               SDMMC_ICR_CMDRENDC_Msk                /*!<CMDREND flag clear bit  */

+#define SDMMC_ICR_CMDSENTC_Pos           (7U)

+#define SDMMC_ICR_CMDSENTC_Msk           (0x1UL << SDMMC_ICR_CMDSENTC_Pos)     /*!< 0x00000080 */

+#define SDMMC_ICR_CMDSENTC               SDMMC_ICR_CMDSENTC_Msk                /*!<CMDSENT flag clear bit  */

+#define SDMMC_ICR_DATAENDC_Pos           (8U)

+#define SDMMC_ICR_DATAENDC_Msk           (0x1UL << SDMMC_ICR_DATAENDC_Pos)     /*!< 0x00000100 */

+#define SDMMC_ICR_DATAENDC               SDMMC_ICR_DATAENDC_Msk                /*!<DATAEND flag clear bit  */

+#define SDMMC_ICR_DHOLDC_Pos             (9U)

+#define SDMMC_ICR_DHOLDC_Msk             (0x1UL << SDMMC_ICR_DHOLDC_Pos)       /*!< 0x00000200 */

+#define SDMMC_ICR_DHOLDC                 SDMMC_ICR_DHOLDC_Msk                  /*!<DHOLD flag clear bit       */

+#define SDMMC_ICR_DBCKENDC_Pos           (10U)

+#define SDMMC_ICR_DBCKENDC_Msk           (0x1UL << SDMMC_ICR_DBCKENDC_Pos)     /*!< 0x00000400 */

+#define SDMMC_ICR_DBCKENDC               SDMMC_ICR_DBCKENDC_Msk                /*!<DBCKEND flag clear bit  */

+#define SDMMC_ICR_DABORTC_Pos            (11U)

+#define SDMMC_ICR_DABORTC_Msk            (0x1UL << SDMMC_ICR_DABORTC_Pos)      /*!< 0x00000800 */

+#define SDMMC_ICR_DABORTC                SDMMC_ICR_DABORTC_Msk                 /*!<DABORTC flag clear bit     */

+#define SDMMC_ICR_BUSYD0ENDC_Pos         (21U)

+#define SDMMC_ICR_BUSYD0ENDC_Msk         (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos)   /*!< 0x00200000 */

+#define SDMMC_ICR_BUSYD0ENDC             SDMMC_ICR_BUSYD0ENDC_Msk              /*!<BUSYD0ENDC flag clear bit  */

+#define SDMMC_ICR_SDIOITC_Pos            (22U)

+#define SDMMC_ICR_SDIOITC_Msk            (0x1UL << SDMMC_ICR_SDIOITC_Pos)      /*!< 0x00400000 */

+#define SDMMC_ICR_SDIOITC                SDMMC_ICR_SDIOITC_Msk                 /*!<SDIOIT flag clear bit      */

+#define SDMMC_ICR_ACKFAILC_Pos           (23U)

+#define SDMMC_ICR_ACKFAILC_Msk           (0x1UL << SDMMC_ICR_ACKFAILC_Pos)     /*!< 0x00800000 */

+#define SDMMC_ICR_ACKFAILC               SDMMC_ICR_ACKFAILC_Msk                /*!<ACKFAILC flag clear bit    */

+#define SDMMC_ICR_ACKTIMEOUTC_Pos        (24U)

+#define SDMMC_ICR_ACKTIMEOUTC_Msk        (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos)  /*!< 0x01000000 */

+#define SDMMC_ICR_ACKTIMEOUTC            SDMMC_ICR_ACKTIMEOUTC_Msk             /*!<ACKTIMEOUTC flag clear bit */

+#define SDMMC_ICR_VSWENDC_Pos            (25U)

+#define SDMMC_ICR_VSWENDC_Msk            (0x1UL << SDMMC_ICR_VSWENDC_Pos)      /*!< 0x02000000 */

+#define SDMMC_ICR_VSWENDC                SDMMC_ICR_VSWENDC_Msk                 /*!<VSWENDC flag clear bit     */

+#define SDMMC_ICR_CKSTOPC_Pos            (26U)

+#define SDMMC_ICR_CKSTOPC_Msk            (0x1UL << SDMMC_ICR_CKSTOPC_Pos)      /*!< 0x04000000 */

+#define SDMMC_ICR_CKSTOPC                SDMMC_ICR_CKSTOPC_Msk                 /*!<CKSTOPC flag clear bit     */

+#define SDMMC_ICR_IDMATEC_Pos            (27U)

+#define SDMMC_ICR_IDMATEC_Msk            (0x1UL << SDMMC_ICR_IDMATEC_Pos)      /*!< 0x08000000 */

+#define SDMMC_ICR_IDMATEC                SDMMC_ICR_IDMATEC_Msk                 /*!<IDMATEC flag clear bit     */

+#define SDMMC_ICR_IDMABTCC_Pos           (28U)

+#define SDMMC_ICR_IDMABTCC_Msk           (0x1UL << SDMMC_ICR_IDMABTCC_Pos)     /*!< 0x10000000 */

+#define SDMMC_ICR_IDMABTCC               SDMMC_ICR_IDMABTCC_Msk                /*!<IDMABTCC flag clear bit    */

+

+/******************  Bit definition for SDMMC_MASK register  *******************/

+#define SDMMC_MASK_CCRCFAILIE_Pos        (0U)

+#define SDMMC_MASK_CCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos)  /*!< 0x00000001 */

+#define SDMMC_MASK_CCRCFAILIE            SDMMC_MASK_CCRCFAILIE_Msk             /*!<Command CRC Fail Interrupt Enable          */

+#define SDMMC_MASK_DCRCFAILIE_Pos        (1U)

+#define SDMMC_MASK_DCRCFAILIE_Msk        (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos)  /*!< 0x00000002 */

+#define SDMMC_MASK_DCRCFAILIE            SDMMC_MASK_DCRCFAILIE_Msk             /*!<Data CRC Fail Interrupt Enable             */

+#define SDMMC_MASK_CTIMEOUTIE_Pos        (2U)

+#define SDMMC_MASK_CTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos)  /*!< 0x00000004 */

+#define SDMMC_MASK_CTIMEOUTIE            SDMMC_MASK_CTIMEOUTIE_Msk             /*!<Command TimeOut Interrupt Enable           */

+#define SDMMC_MASK_DTIMEOUTIE_Pos        (3U)

+#define SDMMC_MASK_DTIMEOUTIE_Msk        (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos)  /*!< 0x00000008 */

+#define SDMMC_MASK_DTIMEOUTIE            SDMMC_MASK_DTIMEOUTIE_Msk             /*!<Data TimeOut Interrupt Enable              */

+#define SDMMC_MASK_TXUNDERRIE_Pos        (4U)

+#define SDMMC_MASK_TXUNDERRIE_Msk        (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos)  /*!< 0x00000010 */

+#define SDMMC_MASK_TXUNDERRIE            SDMMC_MASK_TXUNDERRIE_Msk             /*!<Tx FIFO UnderRun Error Interrupt Enable    */

+#define SDMMC_MASK_RXOVERRIE_Pos         (5U)

+#define SDMMC_MASK_RXOVERRIE_Msk         (0x1UL << SDMMC_MASK_RXOVERRIE_Pos)   /*!< 0x00000020 */

+#define SDMMC_MASK_RXOVERRIE             SDMMC_MASK_RXOVERRIE_Msk              /*!<Rx FIFO OverRun Error Interrupt Enable     */

+#define SDMMC_MASK_CMDRENDIE_Pos         (6U)

+#define SDMMC_MASK_CMDRENDIE_Msk         (0x1UL << SDMMC_MASK_CMDRENDIE_Pos)   /*!< 0x00000040 */

+#define SDMMC_MASK_CMDRENDIE             SDMMC_MASK_CMDRENDIE_Msk              /*!<Command Response Received Interrupt Enable */

+#define SDMMC_MASK_CMDSENTIE_Pos         (7U)

+#define SDMMC_MASK_CMDSENTIE_Msk         (0x1UL << SDMMC_MASK_CMDSENTIE_Pos)   /*!< 0x00000080 */

+#define SDMMC_MASK_CMDSENTIE             SDMMC_MASK_CMDSENTIE_Msk              /*!<Command Sent Interrupt Enable              */

+#define SDMMC_MASK_DATAENDIE_Pos         (8U)

+#define SDMMC_MASK_DATAENDIE_Msk         (0x1UL << SDMMC_MASK_DATAENDIE_Pos)   /*!< 0x00000100 */

+#define SDMMC_MASK_DATAENDIE             SDMMC_MASK_DATAENDIE_Msk              /*!<Data End Interrupt Enable                  */

+#define SDMMC_MASK_DHOLDIE_Pos           (9U)

+#define SDMMC_MASK_DHOLDIE_Msk           (0x1UL << SDMMC_MASK_DHOLDIE_Pos)     /*!< 0x00000200 */

+#define SDMMC_MASK_DHOLDIE               SDMMC_MASK_DHOLDIE_Msk                /*!<Data Hold Interrupt Enable                 */

+#define SDMMC_MASK_DBCKENDIE_Pos         (10U)

+#define SDMMC_MASK_DBCKENDIE_Msk         (0x1UL << SDMMC_MASK_DBCKENDIE_Pos)   /*!< 0x00000400 */

+#define SDMMC_MASK_DBCKENDIE             SDMMC_MASK_DBCKENDIE_Msk              /*!<Data Block End Interrupt Enable            */

+#define SDMMC_MASK_DABORTIE_Pos          (11U)

+#define SDMMC_MASK_DABORTIE_Msk          (0x1UL << SDMMC_MASK_DABORTIE_Pos)    /*!< 0x00000800 */

+#define SDMMC_MASK_DABORTIE              SDMMC_MASK_DABORTIE_Msk               /*!<Data transfer aborted interrupt enable     */

+

+#define SDMMC_MASK_TXFIFOHEIE_Pos        (14U)

+#define SDMMC_MASK_TXFIFOHEIE_Msk        (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos)  /*!< 0x00004000 */

+#define SDMMC_MASK_TXFIFOHEIE            SDMMC_MASK_TXFIFOHEIE_Msk             /*!<Tx FIFO Half Empty interrupt Enable        */

+#define SDMMC_MASK_RXFIFOHFIE_Pos        (15U)

+#define SDMMC_MASK_RXFIFOHFIE_Msk        (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos)  /*!< 0x00008000 */

+#define SDMMC_MASK_RXFIFOHFIE            SDMMC_MASK_RXFIFOHFIE_Msk             /*!<Rx FIFO Half Full interrupt Enable         */

+

+#define SDMMC_MASK_RXFIFOFIE_Pos         (17U)

+#define SDMMC_MASK_RXFIFOFIE_Msk         (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos)   /*!< 0x00020000 */

+#define SDMMC_MASK_RXFIFOFIE             SDMMC_MASK_RXFIFOFIE_Msk              /*!<Rx FIFO Full interrupt Enable              */

+#define SDMMC_MASK_TXFIFOEIE_Pos         (18U)

+#define SDMMC_MASK_TXFIFOEIE_Msk         (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos)   /*!< 0x00040000 */

+#define SDMMC_MASK_TXFIFOEIE             SDMMC_MASK_TXFIFOEIE_Msk              /*!<Tx FIFO Empty interrupt Enable             */

+

+#define SDMMC_MASK_BUSYD0ENDIE_Pos       (21U)

+#define SDMMC_MASK_BUSYD0ENDIE_Msk       (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */

+#define SDMMC_MASK_BUSYD0ENDIE           SDMMC_MASK_BUSYD0ENDIE_Msk            /*!<BUSYD0ENDIE interrupt Enable */

+#define SDMMC_MASK_SDIOITIE_Pos           (22U)

+#define SDMMC_MASK_SDIOITIE_Msk           (0x1UL << SDMMC_MASK_SDIOITIE_Pos)     /*!< 0x00400000 */

+#define SDMMC_MASK_SDIOITIE               SDMMC_MASK_SDIOITIE_Msk                /*!<SDMMC Mode Interrupt Received interrupt Enable */

+#define SDMMC_MASK_ACKFAILIE_Pos         (23U)

+#define SDMMC_MASK_ACKFAILIE_Msk         (0x1UL << SDMMC_MASK_ACKFAILIE_Pos)   /*!< 0x00800000 */

+#define SDMMC_MASK_ACKFAILIE             SDMMC_MASK_ACKFAILIE_Msk              /*!<Acknowledgment Fail Interrupt Enable */

+#define SDMMC_MASK_ACKTIMEOUTIE_Pos      (24U)

+#define SDMMC_MASK_ACKTIMEOUTIE_Msk      (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */

+#define SDMMC_MASK_ACKTIMEOUTIE          SDMMC_MASK_ACKTIMEOUTIE_Msk           /*!<Acknowledgment timeout Interrupt Enable */

+#define SDMMC_MASK_VSWENDIE_Pos          (25U)

+#define SDMMC_MASK_VSWENDIE_Msk          (0x1UL << SDMMC_MASK_VSWENDIE_Pos)    /*!< 0x02000000 */

+#define SDMMC_MASK_VSWENDIE              SDMMC_MASK_VSWENDIE_Msk               /*!<Voltage switch critical timing section completion Interrupt Enable */

+#define SDMMC_MASK_CKSTOPIE_Pos          (26U)

+#define SDMMC_MASK_CKSTOPIE_Msk          (0x1UL << SDMMC_MASK_CKSTOPIE_Pos)    /*!< 0x04000000 */

+#define SDMMC_MASK_CKSTOPIE              SDMMC_MASK_CKSTOPIE_Msk               /*!<Voltage Switch clock stopped Interrupt Enable */

+#define SDMMC_MASK_IDMABTCIE_Pos         (28U)

+#define SDMMC_MASK_IDMABTCIE_Msk         (0x1UL << SDMMC_MASK_IDMABTCIE_Pos)   /*!< 0x10000000 */

+#define SDMMC_MASK_IDMABTCIE             SDMMC_MASK_IDMABTCIE_Msk              /*!<IDMA buffer transfer complete Interrupt Enable */

+

+/*****************  Bit definition for SDMMC_ACKTIME register  *****************/

+#define SDMMC_ACKTIME_ACKTIME_Pos        (0U)

+#define SDMMC_ACKTIME_ACKTIME_Msk        (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */

+#define SDMMC_ACKTIME_ACKTIME            SDMMC_ACKTIME_ACKTIME_Msk             /*!<Boot acknowledgment timeout period */

+

+/******************  Bit definition for SDMMC_FIFO register  *******************/

+#define SDMMC_FIFO_FIFODATA_Pos          (0U)

+#define SDMMC_FIFO_FIFODATA_Msk          (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */

+#define SDMMC_FIFO_FIFODATA              SDMMC_FIFO_FIFODATA_Msk               /*!<Receive and transmit FIFO data */

+

+/******************  Bit definition for SDMMC_IDMACTRL register ****************/

+#define SDMMC_IDMA_IDMAEN_Pos            (0U)

+#define SDMMC_IDMA_IDMAEN_Msk            (0x1UL << SDMMC_IDMA_IDMAEN_Pos)      /*!< 0x00000001 */

+#define SDMMC_IDMA_IDMAEN                SDMMC_IDMA_IDMAEN_Msk                 /*!< Enable the internal DMA of the SDMMC peripheral */

+#define SDMMC_IDMA_IDMABMODE_Pos         (1U)

+#define SDMMC_IDMA_IDMABMODE_Msk         (0x1UL << SDMMC_IDMA_IDMABMODE_Pos)   /*!< 0x00000002 */

+#define SDMMC_IDMA_IDMABMODE             SDMMC_IDMA_IDMABMODE_Msk              /*!< Enable double buffer mode for IDMA */

+#define SDMMC_IDMA_IDMABACT_Pos          (2U)

+#define SDMMC_IDMA_IDMABACT_Msk          (0x1UL << SDMMC_IDMA_IDMABACT_Pos)    /*!< 0x00000004 */

+#define SDMMC_IDMA_IDMABACT              SDMMC_IDMA_IDMABACT_Msk               /*!< Uses buffer 1 when double buffer mode is selected */

+

+/*****************  Bit definition for SDMMC_IDMABSIZE register  ***************/

+#define SDMMC_IDMABSIZE_IDMABNDT_Pos     (5U)

+#define SDMMC_IDMABSIZE_IDMABNDT_Msk     (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */

+#define SDMMC_IDMABSIZE_IDMABNDT         SDMMC_IDMABSIZE_IDMABNDT_Msk          /*!< Number of transfers per buffer */

+

+/*****************  Bit definition for SDMMC_IDMABASE0 register  ***************/

+#define SDMMC_IDMABASE0_IDMABASE0        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 0 memory base address */

+

+/*****************  Bit definition for SDMMC_IDMABASE1 register  ***************/

+#define SDMMC_IDMABASE1_IDMABASE1        ((uint32_t)0xFFFFFFFF)                /*!< Buffer 1 memory base address */

+

+/******************************************************************************/

+/*                                                                            */

+/*                        Delay Block Interface (DLYB)                        */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for DLYB_CR register  ********************/

+#define DLYB_CR_DEN_Pos         (0U)

+#define DLYB_CR_DEN_Msk         (0x1UL << DLYB_CR_DEN_Pos)                     /*!< 0x00000001 */

+#define DLYB_CR_DEN             DLYB_CR_DEN_Msk                                /*!<Delay Block enable */

+#define DLYB_CR_SEN_Pos         (1U)

+#define DLYB_CR_SEN_Msk         (0x1UL << DLYB_CR_SEN_Pos)                     /*!< 0x00000002 */

+#define DLYB_CR_SEN             DLYB_CR_SEN_Msk                                /*!<Sampler length enable */

+

+

+/*******************  Bit definition for DLYB_CFGR register  ********************/

+#define DLYB_CFGR_SEL_Pos       (0U)

+#define DLYB_CFGR_SEL_Msk       (0xFUL << DLYB_CFGR_SEL_Pos)                   /*!< 0x0000000F */

+#define DLYB_CFGR_SEL           DLYB_CFGR_SEL_Msk                              /*!<Select the phase for the Output clock[3:0] */

+#define DLYB_CFGR_SEL_0         (0x1UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000001 */

+#define DLYB_CFGR_SEL_1         (0x2UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000002 */

+#define DLYB_CFGR_SEL_2         (0x3UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000003 */

+#define DLYB_CFGR_SEL_3         (0x8UL << DLYB_CFGR_SEL_Pos)                    /*!< 0x00000008 */

+

+#define DLYB_CFGR_UNIT_Pos      (8U)

+#define DLYB_CFGR_UNIT_Msk      (0x7FUL << DLYB_CFGR_UNIT_Pos)                 /*!< 0x00007F00 */

+#define DLYB_CFGR_UNIT          DLYB_CFGR_UNIT_Msk                             /*!<Delay Defines the delay of a Unit delay cell[6:0] */

+#define DLYB_CFGR_UNIT_0        (0x01UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000100 */

+#define DLYB_CFGR_UNIT_1        (0x02UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000200 */

+#define DLYB_CFGR_UNIT_2        (0x04UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000400 */

+#define DLYB_CFGR_UNIT_3        (0x08UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00000800 */

+#define DLYB_CFGR_UNIT_4        (0x10UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00001000 */

+#define DLYB_CFGR_UNIT_5        (0x20UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00002000 */

+#define DLYB_CFGR_UNIT_6        (0x40UL << DLYB_CFGR_UNIT_Pos)                  /*!< 0x00004000 */

+

+#define DLYB_CFGR_LNG_Pos       (16U)

+#define DLYB_CFGR_LNG_Msk       (0xFFFUL << DLYB_CFGR_LNG_Pos)                 /*!< 0x0FFF0000 */

+#define DLYB_CFGR_LNG           DLYB_CFGR_LNG_Msk                              /*!<Delay line length value[11:0] */

+#define DLYB_CFGR_LNG_0         (0x001UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00010000 */

+#define DLYB_CFGR_LNG_1         (0x002UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00020000 */

+#define DLYB_CFGR_LNG_2         (0x004UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00040000 */

+#define DLYB_CFGR_LNG_3         (0x008UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00080000 */

+#define DLYB_CFGR_LNG_4         (0x010UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00100000 */

+#define DLYB_CFGR_LNG_5         (0x020UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00200000 */

+#define DLYB_CFGR_LNG_6         (0x040UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00400000 */

+#define DLYB_CFGR_LNG_7         (0x080UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x00800000 */

+#define DLYB_CFGR_LNG_8         (0x100UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x01000000 */

+#define DLYB_CFGR_LNG_9         (0x200UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x02000000 */

+#define DLYB_CFGR_LNG_10        (0x400UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x04000000 */

+#define DLYB_CFGR_LNG_11        (0x800UL << DLYB_CFGR_LNG_Pos)                  /*!< 0x08000000 */

+

+#define DLYB_CFGR_LNGF_Pos      (31U)

+#define DLYB_CFGR_LNGF_Msk      (0x1UL << DLYB_CFGR_LNGF_Pos)                  /*!< 0x80000000 */

+#define DLYB_CFGR_LNGF          DLYB_CFGR_LNGF_Msk                             /*!<Length valid flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                   Serial Peripheral Interface (SPI/I2S)                    */

+/*                                                                            */

+/******************************************************************************/

+#define SPI_SPI6I2S_SUPPORT       /*!<SPI6 I2S support feature */

+/*******************  Bit definition for SPI_CR1 register  ********************/

+#define SPI_CR1_SPE_Pos             (0U)

+#define SPI_CR1_SPE_Msk             (0x1UL << SPI_CR1_SPE_Pos)                 /*!< 0x00000001 */

+#define SPI_CR1_SPE                 SPI_CR1_SPE_Msk                            /*!<Serial Peripheral Enable                         */

+#define SPI_CR1_MASRX_Pos           (8U)

+#define SPI_CR1_MASRX_Msk           (0x1UL << SPI_CR1_MASRX_Pos)               /*!< 0x00000100 */

+#define SPI_CR1_MASRX               SPI_CR1_MASRX_Msk                          /*!<Master automatic SUSP in Receive mode            */

+#define SPI_CR1_CSTART_Pos          (9U)

+#define SPI_CR1_CSTART_Msk          (0x1UL << SPI_CR1_CSTART_Pos)              /*!< 0x00000200 */

+#define SPI_CR1_CSTART              SPI_CR1_CSTART_Msk                         /*!<Master transfer start                            */

+#define SPI_CR1_CSUSP_Pos           (10U)

+#define SPI_CR1_CSUSP_Msk           (0x1UL << SPI_CR1_CSUSP_Pos)               /*!< 0x00000400 */

+#define SPI_CR1_CSUSP               SPI_CR1_CSUSP_Msk                          /*!<Master SUSPend request                           */

+#define SPI_CR1_HDDIR_Pos           (11U)

+#define SPI_CR1_HDDIR_Msk           (0x1UL << SPI_CR1_HDDIR_Pos)               /*!< 0x00000800 */

+#define SPI_CR1_HDDIR               SPI_CR1_HDDIR_Msk                          /*!<Rx/Tx direction at Half-duplex mode              */

+#define SPI_CR1_SSI_Pos             (12U)

+#define SPI_CR1_SSI_Msk             (0x1UL << SPI_CR1_SSI_Pos)                 /*!< 0x00001000 */

+#define SPI_CR1_SSI                 SPI_CR1_SSI_Msk                            /*!<Internal SS signal input level                   */

+#define SPI_CR1_CRC33_17_Pos        (13U)

+#define SPI_CR1_CRC33_17_Msk        (0x1UL << SPI_CR1_CRC33_17_Pos)            /*!< 0x00002000 */

+#define SPI_CR1_CRC33_17             SPI_CR1_CRC33_17_Msk                      /*!<32-bit CRC polynomial configuration              */

+#define SPI_CR1_RCRCINI_Pos         (14U)

+#define SPI_CR1_RCRCINI_Msk         (0x1UL << SPI_CR1_RCRCINI_Pos)             /*!< 0x00004000 */

+#define SPI_CR1_RCRCINI             SPI_CR1_RCRCINI_Msk                        /*!<CRC init pattern control for receiver            */

+#define SPI_CR1_TCRCINI_Pos         (15U)

+#define SPI_CR1_TCRCINI_Msk         (0x1UL << SPI_CR1_TCRCINI_Pos)             /*!< 0x00008000 */

+#define SPI_CR1_TCRCINI             SPI_CR1_TCRCINI_Msk                        /*!<CRC init pattern control for transmitter         */

+#define SPI_CR1_IOLOCK_Pos          (16U)

+#define SPI_CR1_IOLOCK_Msk          (0x1UL << SPI_CR1_IOLOCK_Pos)              /*!< 0x00010000 */

+#define SPI_CR1_IOLOCK              SPI_CR1_IOLOCK_Msk                         /*!<Locking the AF configuration of associated IOs   */

+

+/*******************  Bit definition for SPI_CR2 register  ********************/

+#define SPI_CR2_TSER_Pos            (16U)

+#define SPI_CR2_TSER_Msk            (0xFFFFUL << SPI_CR2_TSER_Pos)             /*!< 0xFFFF0000 */

+#define SPI_CR2_TSER                SPI_CR2_TSER_Msk                           /*!<Number of data transfer extension                */

+#define SPI_CR2_TSIZE_Pos           (0U)

+#define SPI_CR2_TSIZE_Msk           (0xFFFFUL << SPI_CR2_TSIZE_Pos)            /*!< 0x0000FFFF */

+#define SPI_CR2_TSIZE               SPI_CR2_TSIZE_Msk                          /*!<Number of data at current transfer               */

+

+/*******************  Bit definition for SPI_CFG1 register  ********************/

+#define SPI_CFG1_DSIZE_Pos          (0U)

+#define SPI_CFG1_DSIZE_Msk          (0x1FUL << SPI_CFG1_DSIZE_Pos)             /*!< 0x0000001F */

+#define SPI_CFG1_DSIZE              SPI_CFG1_DSIZE_Msk                         /*!<DSIZE[4:0]: Bits number in single SPI data frame */

+#define SPI_CFG1_DSIZE_0            (0x01UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000001 */

+#define SPI_CFG1_DSIZE_1            (0x02UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000002 */

+#define SPI_CFG1_DSIZE_2            (0x04UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000004 */

+#define SPI_CFG1_DSIZE_3            (0x08UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000008 */

+#define SPI_CFG1_DSIZE_4            (0x10UL << SPI_CFG1_DSIZE_Pos)              /*!< 0x00000010 */

+

+#define SPI_CFG1_FTHLV_Pos          (5U)

+#define SPI_CFG1_FTHLV_Msk          (0xFUL << SPI_CFG1_FTHLV_Pos)              /*!< 0x000001E0 */

+#define SPI_CFG1_FTHLV              SPI_CFG1_FTHLV_Msk                         /*!<FTHVL [3:0]: FIFO threshold level*/

+#define SPI_CFG1_FTHLV_0            (0x1UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000020 */

+#define SPI_CFG1_FTHLV_1            (0x2UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000040 */

+#define SPI_CFG1_FTHLV_2            (0x4UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000080 */

+#define SPI_CFG1_FTHLV_3            (0x8UL << SPI_CFG1_FTHLV_Pos)               /*!< 0x00000100 */

+

+#define SPI_CFG1_UDRCFG_Pos         (9U)

+#define SPI_CFG1_UDRCFG_Msk         (0x3UL << SPI_CFG1_UDRCFG_Pos)             /*!< 0x00000600 */

+#define SPI_CFG1_UDRCFG             SPI_CFG1_UDRCFG_Msk                        /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */

+#define SPI_CFG1_UDRCFG_0           (0x1UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000200 */

+#define SPI_CFG1_UDRCFG_1           (0x2UL << SPI_CFG1_UDRCFG_Pos)              /*!< 0x00000400 */

+

+

+#define SPI_CFG1_UDRDET_Pos         (11U)

+#define SPI_CFG1_UDRDET_Msk         (0x3UL << SPI_CFG1_UDRDET_Pos)             /*!< 0x00001800 */

+#define SPI_CFG1_UDRDET             SPI_CFG1_UDRDET_Msk                        /*!<UDRDET[1:0]: Detection of underrun condition     */

+#define SPI_CFG1_UDRDET_0           (0x1UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00000800 */

+#define SPI_CFG1_UDRDET_1           (0x2UL << SPI_CFG1_UDRDET_Pos)              /*!< 0x00001000 */

+

+#define SPI_CFG1_RXDMAEN_Pos        (14U)

+#define SPI_CFG1_RXDMAEN_Msk        (0x1UL << SPI_CFG1_RXDMAEN_Pos)            /*!< 0x00004000 */

+#define SPI_CFG1_RXDMAEN            SPI_CFG1_RXDMAEN_Msk                       /*!<Rx DMA stream enable                */

+#define SPI_CFG1_TXDMAEN_Pos        (15U)

+#define SPI_CFG1_TXDMAEN_Msk        (0x1UL << SPI_CFG1_TXDMAEN_Pos)            /*!< 0x00008000 */

+#define SPI_CFG1_TXDMAEN            SPI_CFG1_TXDMAEN_Msk                       /*!<Tx DMA stream enable                */

+

+#define SPI_CFG1_CRCSIZE_Pos        (16U)

+#define SPI_CFG1_CRCSIZE_Msk        (0x1FUL << SPI_CFG1_CRCSIZE_Pos)           /*!< 0x001F0000 */

+#define SPI_CFG1_CRCSIZE            SPI_CFG1_CRCSIZE_Msk                       /*!<CRCSIZE [4:0]: Length of CRC frame*/

+#define SPI_CFG1_CRCSIZE_0          (0x01UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00010000 */

+#define SPI_CFG1_CRCSIZE_1          (0x02UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00020000 */

+#define SPI_CFG1_CRCSIZE_2          (0x04UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00040000 */

+#define SPI_CFG1_CRCSIZE_3          (0x08UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00080000 */

+#define SPI_CFG1_CRCSIZE_4          (0x10UL << SPI_CFG1_CRCSIZE_Pos)            /*!< 0x00100000 */

+

+#define SPI_CFG1_CRCEN_Pos          (22U)

+#define SPI_CFG1_CRCEN_Msk          (0x1UL << SPI_CFG1_CRCEN_Pos)              /*!< 0x00400000 */

+#define SPI_CFG1_CRCEN              SPI_CFG1_CRCEN_Msk                         /*!<Hardware CRC computation enable */

+

+#define SPI_CFG1_MBR_Pos            (28U)

+#define SPI_CFG1_MBR_Msk            (0x7UL << SPI_CFG1_MBR_Pos)                /*!< 0x70000000 */

+#define SPI_CFG1_MBR                SPI_CFG1_MBR_Msk                           /*!<Master baud rate                */

+#define SPI_CFG1_MBR_0              (0x1UL << SPI_CFG1_MBR_Pos)                 /*!< 0x10000000 */

+#define SPI_CFG1_MBR_1              (0x2UL << SPI_CFG1_MBR_Pos)                 /*!< 0x20000000 */

+#define SPI_CFG1_MBR_2              (0x4UL << SPI_CFG1_MBR_Pos)                 /*!< 0x40000000 */

+

+/*******************  Bit definition for SPI_CFG2 register  ********************/

+#define SPI_CFG2_MSSI_Pos           (0U)

+#define SPI_CFG2_MSSI_Msk           (0xFUL << SPI_CFG2_MSSI_Pos)               /*!< 0x0000000F */

+#define SPI_CFG2_MSSI               SPI_CFG2_MSSI_Msk                          /*!<Master SS Idleness */

+#define SPI_CFG2_MSSI_0             (0x1UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000001 */

+#define SPI_CFG2_MSSI_1             (0x2UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000002 */

+#define SPI_CFG2_MSSI_2             (0x4UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000004 */

+#define SPI_CFG2_MSSI_3             (0x8UL << SPI_CFG2_MSSI_Pos)                /*!< 0x00000008 */

+

+#define SPI_CFG2_MIDI_Pos           (4U)

+#define SPI_CFG2_MIDI_Msk           (0xFUL << SPI_CFG2_MIDI_Pos)               /*!< 0x000000F0 */

+#define SPI_CFG2_MIDI               SPI_CFG2_MIDI_Msk                          /*!<Master Inter-Data Idleness */

+#define SPI_CFG2_MIDI_0             (0x1UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000010 */

+#define SPI_CFG2_MIDI_1             (0x2UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000020 */

+#define SPI_CFG2_MIDI_2             (0x4UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000040 */

+#define SPI_CFG2_MIDI_3             (0x8UL << SPI_CFG2_MIDI_Pos)                /*!< 0x00000080 */

+

+#define SPI_CFG2_IOSWP_Pos          (15U)

+#define SPI_CFG2_IOSWP_Msk          (0x1UL << SPI_CFG2_IOSWP_Pos)              /*!< 0x00008000 */

+#define SPI_CFG2_IOSWP              SPI_CFG2_IOSWP_Msk                         /*!<Swap functionality of MISO and MOSI pins */

+

+#define SPI_CFG2_COMM_Pos           (17U)

+#define SPI_CFG2_COMM_Msk           (0x3UL << SPI_CFG2_COMM_Pos)               /*!< 0x00060000 */

+#define SPI_CFG2_COMM               SPI_CFG2_COMM_Msk                          /*!<COMM [1:0]: SPI Communication Mode*/

+#define SPI_CFG2_COMM_0             (0x1UL << SPI_CFG2_COMM_Pos)                /*!< 0x00020000 */

+#define SPI_CFG2_COMM_1             (0x2UL << SPI_CFG2_COMM_Pos)                /*!< 0x00040000 */

+

+#define SPI_CFG2_SP_Pos             (19U)

+#define SPI_CFG2_SP_Msk             (0x7UL << SPI_CFG2_SP_Pos)                 /*!< 0x00380000 */

+#define SPI_CFG2_SP                 SPI_CFG2_SP_Msk                            /*!<SP[2:0]: Serial Protocol */

+#define SPI_CFG2_SP_0               (0x1UL << SPI_CFG2_SP_Pos)                  /*!< 0x00080000 */

+#define SPI_CFG2_SP_1               (0x2UL << SPI_CFG2_SP_Pos)                  /*!< 0x00100000 */

+#define SPI_CFG2_SP_2               (0x4UL << SPI_CFG2_SP_Pos)                  /*!< 0x00200000 */

+

+#define SPI_CFG2_MASTER_Pos         (22U)

+#define SPI_CFG2_MASTER_Msk         (0x1UL << SPI_CFG2_MASTER_Pos)             /*!< 0x00400000 */

+#define SPI_CFG2_MASTER             SPI_CFG2_MASTER_Msk                        /*!<SPI Master           */

+#define SPI_CFG2_LSBFRST_Pos        (23U)

+#define SPI_CFG2_LSBFRST_Msk        (0x1UL << SPI_CFG2_LSBFRST_Pos)            /*!< 0x00800000 */

+#define SPI_CFG2_LSBFRST            SPI_CFG2_LSBFRST_Msk                       /*!<Data frame format               */

+#define SPI_CFG2_CPHA_Pos           (24U)

+#define SPI_CFG2_CPHA_Msk           (0x1UL << SPI_CFG2_CPHA_Pos)               /*!< 0x01000000 */

+#define SPI_CFG2_CPHA               SPI_CFG2_CPHA_Msk                          /*!<Clock Phase      */

+#define SPI_CFG2_CPOL_Pos           (25U)

+#define SPI_CFG2_CPOL_Msk           (0x1UL << SPI_CFG2_CPOL_Pos)               /*!< 0x02000000 */

+#define SPI_CFG2_CPOL               SPI_CFG2_CPOL_Msk                          /*!<Clock Polarity   */

+#define SPI_CFG2_SSM_Pos            (26U)

+#define SPI_CFG2_SSM_Msk            (0x1UL << SPI_CFG2_SSM_Pos)                /*!< 0x04000000 */

+#define SPI_CFG2_SSM                SPI_CFG2_SSM_Msk                           /*!<Software slave management */

+

+#define SPI_CFG2_SSIOP_Pos          (28U)

+#define SPI_CFG2_SSIOP_Msk          (0x1UL << SPI_CFG2_SSIOP_Pos)              /*!< 0x10000000 */

+#define SPI_CFG2_SSIOP              SPI_CFG2_SSIOP_Msk                         /*!<SS input/output polarity */

+#define SPI_CFG2_SSOE_Pos           (29U)

+#define SPI_CFG2_SSOE_Msk           (0x1UL << SPI_CFG2_SSOE_Pos)               /*!< 0x20000000 */

+#define SPI_CFG2_SSOE               SPI_CFG2_SSOE_Msk                          /*!<SS output enable */

+#define SPI_CFG2_SSOM_Pos           (30U)

+#define SPI_CFG2_SSOM_Msk           (0x1UL << SPI_CFG2_SSOM_Pos)               /*!< 0x40000000 */

+#define SPI_CFG2_SSOM               SPI_CFG2_SSOM_Msk                          /*!<SS output management in master mode */

+

+#define SPI_CFG2_AFCNTR_Pos         (31U)

+#define SPI_CFG2_AFCNTR_Msk         (0x1UL << SPI_CFG2_AFCNTR_Pos)             /*!< 0x80000000 */

+#define SPI_CFG2_AFCNTR             SPI_CFG2_AFCNTR_Msk                        /*!<Alternate function GPIOs control */

+

+/*******************  Bit definition for SPI_IER register  ********************/

+#define SPI_IER_RXPIE_Pos           (0U)

+#define SPI_IER_RXPIE_Msk           (0x1UL << SPI_IER_RXPIE_Pos)               /*!< 0x00000001 */

+#define SPI_IER_RXPIE               SPI_IER_RXPIE_Msk                          /*!<RXP Interrupt Enable            */

+#define SPI_IER_TXPIE_Pos           (1U)

+#define SPI_IER_TXPIE_Msk           (0x1UL << SPI_IER_TXPIE_Pos)               /*!< 0x00000002 */

+#define SPI_IER_TXPIE               SPI_IER_TXPIE_Msk                          /*!<TXP interrupt enable            */

+#define SPI_IER_DXPIE_Pos           (2U)

+#define SPI_IER_DXPIE_Msk           (0x1UL << SPI_IER_DXPIE_Pos)               /*!< 0x00000004 */

+#define SPI_IER_DXPIE               SPI_IER_DXPIE_Msk                          /*!<DXP interrupt enable            */

+#define SPI_IER_EOTIE_Pos           (3U)

+#define SPI_IER_EOTIE_Msk           (0x1UL << SPI_IER_EOTIE_Pos)               /*!< 0x00000008 */

+#define SPI_IER_EOTIE               SPI_IER_EOTIE_Msk                          /*!<EOT/SUSP/TXC interrupt enable   */

+#define SPI_IER_TXTFIE_Pos          (4U)

+#define SPI_IER_TXTFIE_Msk          (0x1UL << SPI_IER_TXTFIE_Pos)              /*!< 0x00000010 */

+#define SPI_IER_TXTFIE              SPI_IER_TXTFIE_Msk                         /*!<TXTF interrupt enable           */

+#define SPI_IER_UDRIE_Pos           (5U)

+#define SPI_IER_UDRIE_Msk           (0x1UL << SPI_IER_UDRIE_Pos)               /*!< 0x00000020 */

+#define SPI_IER_UDRIE               SPI_IER_UDRIE_Msk                          /*!<UDR interrupt enable            */

+#define SPI_IER_OVRIE_Pos           (6U)

+#define SPI_IER_OVRIE_Msk           (0x1UL << SPI_IER_OVRIE_Pos)               /*!< 0x00000040 */

+#define SPI_IER_OVRIE               SPI_IER_OVRIE_Msk                          /*!<OVR interrupt enable            */

+#define SPI_IER_CRCEIE_Pos          (7U)

+#define SPI_IER_CRCEIE_Msk          (0x1UL << SPI_IER_CRCEIE_Pos)               /*!< 0x00000080 */

+#define SPI_IER_CRCEIE              SPI_IER_CRCEIE_Msk                          /*!<CRCE interrupt enable           */

+#define SPI_IER_TIFREIE_Pos         (8U)

+#define SPI_IER_TIFREIE_Msk         (0x1UL << SPI_IER_TIFREIE_Pos)             /*!< 0x00000100 */

+#define SPI_IER_TIFREIE             SPI_IER_TIFREIE_Msk                        /*!<TI Frame Error interrupt enable */

+#define SPI_IER_MODFIE_Pos          (9U)

+#define SPI_IER_MODFIE_Msk          (0x1UL << SPI_IER_MODFIE_Pos)              /*!< 0x00000200 */

+#define SPI_IER_MODFIE              SPI_IER_MODFIE_Msk                         /*!<MODF interrupt enable           */

+#define SPI_IER_TSERFIE_Pos         (10U)

+#define SPI_IER_TSERFIE_Msk         (0x1UL << SPI_IER_TSERFIE_Pos)              /*!< 0x00000400 */

+#define SPI_IER_TSERFIE             SPI_IER_TSERFIE_Msk                        /*!<TSERF interrupt enable          */

+

+/*******************  Bit definition for SPI_SR register  ********************/

+#define SPI_SR_RXP_Pos              (0U)

+#define SPI_SR_RXP_Msk              (0x1UL << SPI_SR_RXP_Pos)                  /*!< 0x00000001 */

+#define SPI_SR_RXP                  SPI_SR_RXP_Msk                             /*!<Rx-Packet available             */

+#define SPI_SR_TXP_Pos              (1U)

+#define SPI_SR_TXP_Msk              (0x1UL << SPI_SR_TXP_Pos)                  /*!< 0x00000002 */

+#define SPI_SR_TXP                  SPI_SR_TXP_Msk                             /*!<Tx-Packet space available       */

+#define SPI_SR_DXP_Pos              (2U)

+#define SPI_SR_DXP_Msk              (0x1UL << SPI_SR_DXP_Pos)                  /*!< 0x00000004 */

+#define SPI_SR_DXP                  SPI_SR_DXP_Msk                             /*!<Duplex Packet available         */

+#define SPI_SR_EOT_Pos              (3U)

+#define SPI_SR_EOT_Msk              (0x1UL << SPI_SR_EOT_Pos)                  /*!< 0x00000008 */

+#define SPI_SR_EOT                  SPI_SR_EOT_Msk                             /*!<Duplex Packet available         */

+#define SPI_SR_TXTF_Pos             (4U)

+#define SPI_SR_TXTF_Msk             (0x1UL << SPI_SR_TXTF_Pos)                 /*!< 0x00000010 */

+#define SPI_SR_TXTF                 SPI_SR_TXTF_Msk                            /*!<Transmission Transfer Filled    */

+#define SPI_SR_UDR_Pos              (5U)

+#define SPI_SR_UDR_Msk              (0x1UL << SPI_SR_UDR_Pos)                  /*!< 0x00000020 */

+#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!<UDR at Slave transmission       */

+#define SPI_SR_OVR_Pos              (6U)

+#define SPI_SR_OVR_Msk              (0x1UL << SPI_SR_OVR_Pos)                  /*!< 0x00000040 */

+#define SPI_SR_OVR                  SPI_SR_OVR_Msk                             /*!<Rx-Packet available             */

+#define SPI_SR_CRCE_Pos             (7U)

+#define SPI_SR_CRCE_Msk             (0x1UL << SPI_SR_CRCE_Pos)                 /*!< 0x00000080 */

+#define SPI_SR_CRCE                 SPI_SR_CRCE_Msk                            /*!<CRC Error Detected              */

+#define SPI_SR_TIFRE_Pos            (8U)

+#define SPI_SR_TIFRE_Msk            (0x1UL << SPI_SR_TIFRE_Pos)                /*!< 0x00000100 */

+#define SPI_SR_TIFRE                SPI_SR_TIFRE_Msk                           /*!<TI frame format error Detected  */

+#define SPI_SR_MODF_Pos             (9U)

+#define SPI_SR_MODF_Msk             (0x1UL << SPI_SR_MODF_Pos)                 /*!< 0x00000200 */

+#define SPI_SR_MODF                 SPI_SR_MODF_Msk                            /*!<Mode Fault Detected             */

+#define SPI_SR_TSERF_Pos            (10U)

+#define SPI_SR_TSERF_Msk            (0x1UL << SPI_SR_TSERF_Pos)                /*!< 0x00000400 */

+#define SPI_SR_TSERF                SPI_SR_TSERF_Msk                           /*!<Number of SPI data to be transacted reloaded     */

+#define SPI_SR_SUSP_Pos             (11U)

+#define SPI_SR_SUSP_Msk             (0x1UL << SPI_SR_SUSP_Pos)                 /*!< 0x00000800 */

+#define SPI_SR_SUSP                 SPI_SR_SUSP_Msk                            /*!<SUSP is set by hardware  */

+#define SPI_SR_TXC_Pos              (12U)

+#define SPI_SR_TXC_Msk              (0x1UL << SPI_SR_TXC_Pos)                  /*!< 0x00001000 */

+#define SPI_SR_TXC                  SPI_SR_TXC_Msk                             /*!<TxFIFO transmission complete */

+#define SPI_SR_RXPLVL_Pos           (13U)

+#define SPI_SR_RXPLVL_Msk           (0x3UL << SPI_SR_RXPLVL_Pos)               /*!< 0x00006000 */

+#define SPI_SR_RXPLVL               SPI_SR_RXPLVL_Msk                          /*!<RxFIFO Packing Level                             */

+#define SPI_SR_RXPLVL_0             (0x1UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00002000 */

+#define SPI_SR_RXPLVL_1             (0x2UL << SPI_SR_RXPLVL_Pos)                /*!< 0x00004000 */

+#define SPI_SR_RXWNE_Pos            (15U)

+#define SPI_SR_RXWNE_Msk            (0x1UL << SPI_SR_RXWNE_Pos)                /*!< 0x00008000 */

+#define SPI_SR_RXWNE                SPI_SR_RXWNE_Msk                           /*!<Rx FIFO Word Not Empty                           */

+#define SPI_SR_CTSIZE_Pos           (16U)

+#define SPI_SR_CTSIZE_Msk           (0xFFFFUL << SPI_SR_CTSIZE_Pos)            /*!< 0xFFFF0000 */

+#define SPI_SR_CTSIZE               SPI_SR_CTSIZE_Msk                          /*!<Number of data frames remaining in TSIZE         */

+

+/*******************  Bit definition for SPI_IFCR register  ********************/

+#define SPI_IFCR_EOTC_Pos           (3U)

+#define SPI_IFCR_EOTC_Msk           (0x1UL << SPI_IFCR_EOTC_Pos)               /*!< 0x00000008 */

+#define SPI_IFCR_EOTC               SPI_IFCR_EOTC_Msk                          /*!<End Of Transfer flag clear              */

+#define SPI_IFCR_TXTFC_Pos          (4U)

+#define SPI_IFCR_TXTFC_Msk          (0x1UL << SPI_IFCR_TXTFC_Pos)              /*!< 0x00000010 */

+#define SPI_IFCR_TXTFC              SPI_IFCR_TXTFC_Msk                         /*!<Transmission Transfer Filled flag clear */

+#define SPI_IFCR_UDRC_Pos           (5U)

+#define SPI_IFCR_UDRC_Msk           (0x1UL << SPI_IFCR_UDRC_Pos)               /*!< 0x00000020 */

+#define SPI_IFCR_UDRC               SPI_IFCR_UDRC_Msk                          /*!<Underrun flag clear                     */

+#define SPI_IFCR_OVRC_Pos           (6U)

+#define SPI_IFCR_OVRC_Msk           (0x1UL << SPI_IFCR_OVRC_Pos)               /*!< 0x00000040 */

+#define SPI_IFCR_OVRC               SPI_IFCR_OVRC_Msk                          /*!<Overrun flag clear                      */

+#define SPI_IFCR_CRCEC_Pos          (7U)

+#define SPI_IFCR_CRCEC_Msk          (0x1UL << SPI_IFCR_CRCEC_Pos)              /*!< 0x00000080 */

+#define SPI_IFCR_CRCEC              SPI_IFCR_CRCEC_Msk                         /*!<CRC Error flag clear                    */

+#define SPI_IFCR_TIFREC_Pos         (8U)

+#define SPI_IFCR_TIFREC_Msk         (0x1UL << SPI_IFCR_TIFREC_Pos)             /*!< 0x00000100 */

+#define SPI_IFCR_TIFREC             SPI_IFCR_TIFREC_Msk                        /*!<TI frame format error flag clear        */

+#define SPI_IFCR_MODFC_Pos          (9U)

+#define SPI_IFCR_MODFC_Msk          (0x1UL << SPI_IFCR_MODFC_Pos)              /*!< 0x00000200 */

+#define SPI_IFCR_MODFC              SPI_IFCR_MODFC_Msk                         /*!<Mode Fault flag clear                   */

+#define SPI_IFCR_TSERFC_Pos         (10U)

+#define SPI_IFCR_TSERFC_Msk         (0x1UL << SPI_IFCR_TSERFC_Pos)             /*!< 0x00000400 */

+#define SPI_IFCR_TSERFC             SPI_IFCR_TSERFC_Msk                        /*!<TSERFC flag clear                       */

+#define SPI_IFCR_SUSPC_Pos          (11U)

+#define SPI_IFCR_SUSPC_Msk          (0x1UL << SPI_IFCR_SUSPC_Pos)              /*!< 0x00000800 */

+#define SPI_IFCR_SUSPC              SPI_IFCR_SUSPC_Msk                         /*!<SUSPend flag clear                      */

+

+/*******************  Bit definition for SPI_TXDR register  ********************/

+#define SPI_TXDR_TXDR_Pos           (0U)

+#define SPI_TXDR_TXDR_Msk           (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos)        /*!< 0xFFFFFFFF */

+#define SPI_TXDR_TXDR               SPI_TXDR_TXDR_Msk                          /* Transmit Data Register */

+

+/*******************  Bit definition for SPI_RXDR register  ********************/

+#define SPI_RXDR_RXDR_Pos           (0U)

+#define SPI_RXDR_RXDR_Msk           (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos)        /*!< 0xFFFFFFFF */

+#define SPI_RXDR_RXDR               SPI_RXDR_RXDR_Msk                          /* Receive Data Register  */

+

+/*******************  Bit definition for SPI_CRCPOLY register  ********************/

+#define SPI_CRCPOLY_CRCPOLY_Pos     (0U)

+#define SPI_CRCPOLY_CRCPOLY_Msk     (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)  /*!< 0xFFFFFFFF */

+#define SPI_CRCPOLY_CRCPOLY         SPI_CRCPOLY_CRCPOLY_Msk                    /* CRC Polynomial register  */

+

+/*******************  Bit definition for SPI_TXCRC register  ********************/

+#define SPI_TXCRC_TXCRC_Pos         (0U)

+#define SPI_TXCRC_TXCRC_Msk         (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_TXCRC_TXCRC             SPI_TXCRC_TXCRC_Msk                        /* CRCRegister for transmitter */

+

+/*******************  Bit definition for SPI_RXCRC register  ********************/

+#define SPI_RXCRC_RXCRC_Pos         (0U)

+#define SPI_RXCRC_RXCRC_Msk         (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_RXCRC_RXCRC             SPI_RXCRC_RXCRC_Msk                        /* CRCRegister for receiver */

+

+/*******************  Bit definition for SPI_UDRDR register  ********************/

+#define SPI_UDRDR_UDRDR_Pos         (0U)

+#define SPI_UDRDR_UDRDR_Msk         (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos)      /*!< 0xFFFFFFFF */

+#define SPI_UDRDR_UDRDR             SPI_UDRDR_UDRDR_Msk                        /* Data at slave underrun condition */

+

+/******************  Bit definition for SPI_I2SCFGR register  *****************/

+#define SPI_I2SCFGR_I2SMOD_Pos      (0U)

+#define SPI_I2SCFGR_I2SMOD_Msk      (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)          /*!< 0x00000001 */

+#define SPI_I2SCFGR_I2SMOD          SPI_I2SCFGR_I2SMOD_Msk                     /*!<I2S mode selection */

+#define SPI_I2SCFGR_I2SCFG_Pos      (1U)

+#define SPI_I2SCFGR_I2SCFG_Msk      (0x7UL << SPI_I2SCFGR_I2SCFG_Pos)          /*!< 0x0000000E */

+#define SPI_I2SCFGR_I2SCFG          SPI_I2SCFGR_I2SCFG_Msk                     /*!<I2SCFG[2:0] I2S configuration mode                */

+#define SPI_I2SCFGR_I2SCFG_0        (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000002 */

+#define SPI_I2SCFGR_I2SCFG_1        (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000004 */

+#define SPI_I2SCFGR_I2SCFG_2        (0x4UL << SPI_I2SCFGR_I2SCFG_Pos)           /*!< 0x00000008 */

+#define SPI_I2SCFGR_I2SSTD_Pos      (4U)

+#define SPI_I2SCFGR_I2SSTD_Msk      (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)          /*!< 0x00000030 */

+#define SPI_I2SCFGR_I2SSTD          SPI_I2SCFGR_I2SSTD_Msk                     /*!<I2SSTD[1:0] I2S standard selection                */

+#define SPI_I2SCFGR_I2SSTD_0        (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000010 */

+#define SPI_I2SCFGR_I2SSTD_1        (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)           /*!< 0x00000020 */

+#define SPI_I2SCFGR_PCMSYNC_Pos     (7U)

+#define SPI_I2SCFGR_PCMSYNC_Msk     (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)         /*!< 0x00000080 */

+#define SPI_I2SCFGR_PCMSYNC         SPI_I2SCFGR_PCMSYNC_Msk                    /*!<PCM frame synchronization                         */

+#define SPI_I2SCFGR_DATLEN_Pos      (8U)

+#define SPI_I2SCFGR_DATLEN_Msk      (0x3UL << SPI_I2SCFGR_DATLEN_Pos)          /*!< 0x00000300 */

+#define SPI_I2SCFGR_DATLEN          SPI_I2SCFGR_DATLEN_Msk                     /*!<DATLEN[1:0] Data length to be transferred         */

+#define SPI_I2SCFGR_DATLEN_0        (0x1UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000100 */

+#define SPI_I2SCFGR_DATLEN_1        (0x2UL << SPI_I2SCFGR_DATLEN_Pos)           /*!< 0x00000200 */

+#define SPI_I2SCFGR_CHLEN_Pos       (10U)

+#define SPI_I2SCFGR_CHLEN_Msk       (0x1UL << SPI_I2SCFGR_CHLEN_Pos)           /*!< 0x00000400 */

+#define SPI_I2SCFGR_CHLEN           SPI_I2SCFGR_CHLEN_Msk                      /*!<Channel length (number of bits per audio channel) */

+#define SPI_I2SCFGR_CKPOL_Pos       (11U)

+#define SPI_I2SCFGR_CKPOL_Msk       (0x1UL << SPI_I2SCFGR_CKPOL_Pos)           /*!< 0x00000800 */

+#define SPI_I2SCFGR_CKPOL           SPI_I2SCFGR_CKPOL_Msk                      /*!<Steady state clock polarity                       */

+#define SPI_I2SCFGR_FIXCH_Pos       (12U)

+#define SPI_I2SCFGR_FIXCH_Msk       (0x1UL << SPI_I2SCFGR_FIXCH_Pos)           /*!< 0x00001000 */

+#define SPI_I2SCFGR_FIXCH           SPI_I2SCFGR_FIXCH_Msk                      /*!<Fixed channel length in SLAVE                     */

+#define SPI_I2SCFGR_WSINV_Pos       (13U)

+#define SPI_I2SCFGR_WSINV_Msk       (0x1UL << SPI_I2SCFGR_WSINV_Pos)           /*!< 0x00002000 */

+#define SPI_I2SCFGR_WSINV           SPI_I2SCFGR_WSINV_Msk                      /*!<Word select inversion                             */

+#define SPI_I2SCFGR_DATFMT_Pos      (14U)

+#define SPI_I2SCFGR_DATFMT_Msk      (0x1UL << SPI_I2SCFGR_DATFMT_Pos)          /*!< 0x00004000 */

+#define SPI_I2SCFGR_DATFMT          SPI_I2SCFGR_DATFMT_Msk                     /*!<Data format                                       */

+#define SPI_I2SCFGR_I2SDIV_Pos      (16U)

+#define SPI_I2SCFGR_I2SDIV_Msk      (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos)         /*!< 0x00FF0000 */

+#define SPI_I2SCFGR_I2SDIV          SPI_I2SCFGR_I2SDIV_Msk                     /*!<I2S Linear prescaler */

+#define SPI_I2SCFGR_ODD_Pos         (24U)

+#define SPI_I2SCFGR_ODD_Msk         (0x1UL << SPI_I2SCFGR_ODD_Pos)             /*!< 0x01000000 */

+#define SPI_I2SCFGR_ODD             SPI_I2SCFGR_ODD_Msk                        /*!<Odd factor for the prescaler */

+#define SPI_I2SCFGR_MCKOE_Pos       (25U)

+#define SPI_I2SCFGR_MCKOE_Msk       (0x1UL << SPI_I2SCFGR_MCKOE_Pos)           /*!< 0x02000000 */

+#define SPI_I2SCFGR_MCKOE           SPI_I2SCFGR_MCKOE_Msk                      /*!<Master Clock Output Enable */

+

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                 SYSCFG                                     */

+/*                                                                            */

+/******************************************************************************/

+

+/******************  Bit definition for SYSCFG_PMCR register  ******************/

+#define SYSCFG_PMCR_I2C1_FMP_Pos        (0U)

+#define SYSCFG_PMCR_I2C1_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos)    /*!< 0x00000001 */

+#define SYSCFG_PMCR_I2C1_FMP            SYSCFG_PMCR_I2C1_FMP_Msk               /*!< I2C1 Fast mode plus */

+#define SYSCFG_PMCR_I2C2_FMP_Pos        (1U)

+#define SYSCFG_PMCR_I2C2_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos)    /*!< 0x00000002 */

+#define SYSCFG_PMCR_I2C2_FMP            SYSCFG_PMCR_I2C2_FMP_Msk               /*!< I2C2 Fast mode plus */

+#define SYSCFG_PMCR_I2C3_FMP_Pos        (2U)

+#define SYSCFG_PMCR_I2C3_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos)    /*!< 0x00000004 */

+#define SYSCFG_PMCR_I2C3_FMP            SYSCFG_PMCR_I2C3_FMP_Msk               /*!< I2C3 Fast mode plus */

+#define SYSCFG_PMCR_I2C4_FMP_Pos        (3U)

+#define SYSCFG_PMCR_I2C4_FMP_Msk        (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos)    /*!< 0x00000008 */

+#define SYSCFG_PMCR_I2C4_FMP            SYSCFG_PMCR_I2C4_FMP_Msk               /*!< I2C4 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB6_FMP_Pos     (4U)

+#define SYSCFG_PMCR_I2C_PB6_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */

+#define SYSCFG_PMCR_I2C_PB6_FMP         SYSCFG_PMCR_I2C_PB6_FMP_Msk            /*!< I2C PB6 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB7_FMP_Pos     (5U)

+#define SYSCFG_PMCR_I2C_PB7_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */

+#define SYSCFG_PMCR_I2C_PB7_FMP         SYSCFG_PMCR_I2C_PB7_FMP_Msk            /*!< I2C PB7 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB8_FMP_Pos     (6U)

+#define SYSCFG_PMCR_I2C_PB8_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */

+#define SYSCFG_PMCR_I2C_PB8_FMP         SYSCFG_PMCR_I2C_PB8_FMP_Msk            /*!< I2C PB8 Fast mode plus */

+#define SYSCFG_PMCR_I2C_PB9_FMP_Pos     (7U)

+#define SYSCFG_PMCR_I2C_PB9_FMP_Msk     (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */

+#define SYSCFG_PMCR_I2C_PB9_FMP         SYSCFG_PMCR_I2C_PB9_FMP_Msk            /*!< I2C PB9 Fast mode plus */

+#define SYSCFG_PMCR_PA0SO_Pos           (24U)

+#define SYSCFG_PMCR_PA0SO_Msk           (0x1UL << SYSCFG_PMCR_PA0SO_Pos)       /*!< 0x01000000 */

+#define SYSCFG_PMCR_PA0SO               SYSCFG_PMCR_PA0SO_Msk                  /*!< PA0 Switch Open */

+#define SYSCFG_PMCR_PA1SO_Pos           (25U)

+#define SYSCFG_PMCR_PA1SO_Msk           (0x1UL << SYSCFG_PMCR_PA1SO_Pos)       /*!< 0x02000000 */

+#define SYSCFG_PMCR_PA1SO               SYSCFG_PMCR_PA1SO_Msk                  /*!< PA1 Switch Open */

+#define SYSCFG_PMCR_PC2SO_Pos           (26U)

+#define SYSCFG_PMCR_PC2SO_Msk           (0x1UL << SYSCFG_PMCR_PC2SO_Pos)       /*!< 0x04000000 */

+#define SYSCFG_PMCR_PC2SO               SYSCFG_PMCR_PC2SO_Msk                  /*!< PC2 Switch Open */

+#define SYSCFG_PMCR_PC3SO_Pos           (27U)

+#define SYSCFG_PMCR_PC3SO_Msk           (0x1UL << SYSCFG_PMCR_PC3SO_Pos)       /*!< 0x08000000 */

+#define SYSCFG_PMCR_PC3SO               SYSCFG_PMCR_PC3SO_Msk                  /*!< PC3 Switch Open */

+

+/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/

+#define SYSCFG_EXTICR1_EXTI0_Pos        (0U)

+#define SYSCFG_EXTICR1_EXTI0_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR1_EXTI0            SYSCFG_EXTICR1_EXTI0_Msk               /*!<EXTI 0 configuration */

+#define SYSCFG_EXTICR1_EXTI1_Pos        (4U)

+#define SYSCFG_EXTICR1_EXTI1_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR1_EXTI1            SYSCFG_EXTICR1_EXTI1_Msk               /*!<EXTI 1 configuration */

+#define SYSCFG_EXTICR1_EXTI2_Pos        (8U)

+#define SYSCFG_EXTICR1_EXTI2_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos)    /*!< 0x00000F00 */

+#define SYSCFG_EXTICR1_EXTI2            SYSCFG_EXTICR1_EXTI2_Msk               /*!<EXTI 2 configuration */

+#define SYSCFG_EXTICR1_EXTI3_Pos        (12U)

+#define SYSCFG_EXTICR1_EXTI3_Msk        (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos)    /*!< 0x0000F000 */

+#define SYSCFG_EXTICR1_EXTI3            SYSCFG_EXTICR1_EXTI3_Msk               /*!<EXTI 3 configuration */

+/**

+  * @brief   EXTI0 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000)                 /*!<PA[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001)                 /*!<PB[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002)                 /*!<PC[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003)                 /*!<PD[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004)                 /*!<PE[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000005)                 /*!<PF[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000006)                 /*!<PG[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000007)                 /*!<PH[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PI         ((uint32_t)0x00000008)                 /*!<PI[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PJ         ((uint32_t)0x00000009)                 /*!<PJ[0] pin */

+#define SYSCFG_EXTICR1_EXTI0_PK         ((uint32_t)0x0000000A)                 /*!<PK[0] pin */

+

+/**

+  * @brief   EXTI1 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000)                 /*!<PA[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010)                 /*!<PB[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020)                 /*!<PC[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030)                 /*!<PD[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040)                 /*!<PE[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000050)                 /*!<PF[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000060)                 /*!<PG[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000070)                 /*!<PH[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PI         ((uint32_t)0x00000080)                 /*!<PI[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PJ         ((uint32_t)0x00000090)                 /*!<PJ[1] pin */

+#define SYSCFG_EXTICR1_EXTI1_PK         ((uint32_t)0x000000A0)                 /*!<PK[1] pin */

+/**

+  * @brief   EXTI2 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000)                 /*!<PA[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100)                 /*!<PB[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200)                 /*!<PC[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300)                 /*!<PD[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400)                 /*!<PE[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000500)                 /*!<PF[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000600)                 /*!<PG[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000700)                 /*!<PH[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PI         ((uint32_t)0x00000800)                 /*!<PI[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PJ         ((uint32_t)0x00000900)                 /*!<PJ[2] pin */

+#define SYSCFG_EXTICR1_EXTI2_PK         ((uint32_t)0x00000A00)                 /*!<PK[2] pin */

+

+/**

+  * @brief   EXTI3 configuration

+  */

+#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000)                 /*!<PA[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000)                 /*!<PB[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000)                 /*!<PC[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000)                 /*!<PD[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000)                 /*!<PE[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00005000)                 /*!<PF[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00006000)                 /*!<PG[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PH         ((uint32_t)0x00007000)                 /*!<PH[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PI         ((uint32_t)0x00008000)                 /*!<PI[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PJ         ((uint32_t)0x00009000)                 /*!<PJ[3] pin */

+#define SYSCFG_EXTICR1_EXTI3_PK         ((uint32_t)0x0000A000)                 /*!<PK[3] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR2 register  ***************/

+#define SYSCFG_EXTICR2_EXTI4_Pos        (0U)

+#define SYSCFG_EXTICR2_EXTI4_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR2_EXTI4            SYSCFG_EXTICR2_EXTI4_Msk               /*!<EXTI 4 configuration */

+#define SYSCFG_EXTICR2_EXTI5_Pos        (4U)

+#define SYSCFG_EXTICR2_EXTI5_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR2_EXTI5            SYSCFG_EXTICR2_EXTI5_Msk               /*!<EXTI 5 configuration */

+#define SYSCFG_EXTICR2_EXTI6_Pos        (8U)

+#define SYSCFG_EXTICR2_EXTI6_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos)    /*!< 0x00000F00 */

+#define SYSCFG_EXTICR2_EXTI6            SYSCFG_EXTICR2_EXTI6_Msk               /*!<EXTI 6 configuration */

+#define SYSCFG_EXTICR2_EXTI7_Pos        (12U)

+#define SYSCFG_EXTICR2_EXTI7_Msk        (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos)    /*!< 0x0000F000 */

+#define SYSCFG_EXTICR2_EXTI7            SYSCFG_EXTICR2_EXTI7_Msk               /*!<EXTI 7 configuration */

+/**

+  * @brief   EXTI4 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000)                 /*!<PA[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001)                 /*!<PB[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002)                 /*!<PC[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003)                 /*!<PD[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004)                 /*!<PE[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000005)                 /*!<PF[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000006)                 /*!<PG[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PH         ((uint32_t)0x00000007)                 /*!<PH[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PI         ((uint32_t)0x00000008)                 /*!<PI[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PJ         ((uint32_t)0x00000009)                 /*!<PJ[4] pin */

+#define SYSCFG_EXTICR2_EXTI4_PK         ((uint32_t)0x0000000A)                 /*!<PK[4] pin */

+/**

+  * @brief   EXTI5 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000)                 /*!<PA[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010)                 /*!<PB[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020)                 /*!<PC[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030)                 /*!<PD[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040)                 /*!<PE[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000050)                 /*!<PF[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000060)                 /*!<PG[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PH         ((uint32_t)0x00000070)                 /*!<PH[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PI         ((uint32_t)0x00000080)                 /*!<PI[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PJ         ((uint32_t)0x00000090)                 /*!<PJ[5] pin */

+#define SYSCFG_EXTICR2_EXTI5_PK         ((uint32_t)0x000000A0)                 /*!<PK[5] pin */

+/**

+  * @brief   EXTI6 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000)                 /*!<PA[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100)                 /*!<PB[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200)                 /*!<PC[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300)                 /*!<PD[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400)                 /*!<PE[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000500)                 /*!<PF[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000600)                 /*!<PG[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PH         ((uint32_t)0x00000700)                 /*!<PH[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PI         ((uint32_t)0x00000800)                 /*!<PI[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PJ         ((uint32_t)0x00000900)                 /*!<PJ[6] pin */

+#define SYSCFG_EXTICR2_EXTI6_PK         ((uint32_t)0x00000A00)                 /*!<PK[6] pin */

+

+/**

+  * @brief   EXTI7 configuration

+  */

+#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000)                 /*!<PA[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000)                 /*!<PB[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000)                 /*!<PC[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000)                 /*!<PD[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000)                 /*!<PE[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00005000)                 /*!<PF[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00006000)                 /*!<PG[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PH         ((uint32_t)0x00007000)                 /*!<PH[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PI         ((uint32_t)0x00008000)                 /*!<PI[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PJ         ((uint32_t)0x00009000)                 /*!<PJ[7] pin */

+#define SYSCFG_EXTICR2_EXTI7_PK         ((uint32_t)0x0000A000)                 /*!<PK[7] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR3 register  ***************/

+#define SYSCFG_EXTICR3_EXTI8_Pos        (0U)

+#define SYSCFG_EXTICR3_EXTI8_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos)    /*!< 0x0000000F */

+#define SYSCFG_EXTICR3_EXTI8            SYSCFG_EXTICR3_EXTI8_Msk               /*!<EXTI 8 configuration */

+#define SYSCFG_EXTICR3_EXTI9_Pos        (4U)

+#define SYSCFG_EXTICR3_EXTI9_Msk        (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos)    /*!< 0x000000F0 */

+#define SYSCFG_EXTICR3_EXTI9            SYSCFG_EXTICR3_EXTI9_Msk               /*!<EXTI 9 configuration */

+#define SYSCFG_EXTICR3_EXTI10_Pos       (8U)

+#define SYSCFG_EXTICR3_EXTI10_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos)   /*!< 0x00000F00 */

+#define SYSCFG_EXTICR3_EXTI10           SYSCFG_EXTICR3_EXTI10_Msk              /*!<EXTI 10 configuration */

+#define SYSCFG_EXTICR3_EXTI11_Pos       (12U)

+#define SYSCFG_EXTICR3_EXTI11_Msk       (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos)   /*!< 0x0000F000 */

+#define SYSCFG_EXTICR3_EXTI11           SYSCFG_EXTICR3_EXTI11_Msk              /*!<EXTI 11 configuration */

+

+/**

+  * @brief   EXTI8 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000)                 /*!<PA[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001)                 /*!<PB[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002)                 /*!<PC[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003)                 /*!<PD[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004)                 /*!<PE[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000005)                 /*!<PF[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000006)                 /*!<PG[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PH         ((uint32_t)0x00000007)                 /*!<PH[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PI         ((uint32_t)0x00000008)                 /*!<PI[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PJ         ((uint32_t)0x00000009)                 /*!<PJ[8] pin */

+#define SYSCFG_EXTICR3_EXTI8_PK         ((uint32_t)0x0000000A)                 /*!<PK[8] pin */

+

+/**

+  * @brief   EXTI9 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000)                 /*!<PA[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010)                 /*!<PB[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020)                 /*!<PC[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030)                 /*!<PD[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040)                 /*!<PE[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000050)                 /*!<PF[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000060)                 /*!<PG[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000070)                 /*!<PH[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PI         ((uint32_t)0x00000080)                 /*!<PI[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PJ         ((uint32_t)0x00000090)                 /*!<PJ[9] pin */

+#define SYSCFG_EXTICR3_EXTI9_PK         ((uint32_t)0x000000A0)                 /*!<PK[9] pin */

+

+/**

+  * @brief   EXTI10 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000)                 /*!<PA[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100)                 /*!<PB[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200)                 /*!<PC[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300)                 /*!<PD[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400)                 /*!<PE[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000500)                 /*!<PF[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000600)                 /*!<PG[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000700)                 /*!<PH[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PI        ((uint32_t)0x00000800)                 /*!<PI[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PJ        ((uint32_t)0x00000900)                 /*!<PJ[10] pin */

+#define SYSCFG_EXTICR3_EXTI10_PK        ((uint32_t)0x00000A00)                 /*!<PK[10] pin */

+

+/**

+  * @brief   EXTI11 configuration

+  */

+#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000)                 /*!<PA[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000)                 /*!<PB[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000)                 /*!<PC[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000)                 /*!<PD[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000)                 /*!<PE[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00005000)                 /*!<PF[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00006000)                 /*!<PG[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PH        ((uint32_t)0x00007000)                 /*!<PH[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PI        ((uint32_t)0x00008000)                 /*!<PI[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PJ        ((uint32_t)0x00009000)                 /*!<PJ[11] pin */

+#define SYSCFG_EXTICR3_EXTI11_PK        ((uint32_t)0x0000A000)                 /*!<PK[11] pin */

+

+/*****************  Bit definition for SYSCFG_EXTICR4 register  ***************/

+#define SYSCFG_EXTICR4_EXTI12_Pos       (0U)

+#define SYSCFG_EXTICR4_EXTI12_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos)   /*!< 0x0000000F */

+#define SYSCFG_EXTICR4_EXTI12           SYSCFG_EXTICR4_EXTI12_Msk              /*!<EXTI 12 configuration */

+#define SYSCFG_EXTICR4_EXTI13_Pos       (4U)

+#define SYSCFG_EXTICR4_EXTI13_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos)   /*!< 0x000000F0 */

+#define SYSCFG_EXTICR4_EXTI13           SYSCFG_EXTICR4_EXTI13_Msk              /*!<EXTI 13 configuration */

+#define SYSCFG_EXTICR4_EXTI14_Pos       (8U)

+#define SYSCFG_EXTICR4_EXTI14_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos)   /*!< 0x00000F00 */

+#define SYSCFG_EXTICR4_EXTI14           SYSCFG_EXTICR4_EXTI14_Msk              /*!<EXTI 14 configuration */

+#define SYSCFG_EXTICR4_EXTI15_Pos       (12U)

+#define SYSCFG_EXTICR4_EXTI15_Msk       (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos)   /*!< 0x0000F000 */

+#define SYSCFG_EXTICR4_EXTI15           SYSCFG_EXTICR4_EXTI15_Msk              /*!<EXTI 15 configuration */

+/**

+  * @brief   EXTI12 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000)                 /*!<PA[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001)                 /*!<PB[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002)                 /*!<PC[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003)                 /*!<PD[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004)                 /*!<PE[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000005)                 /*!<PF[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000006)                 /*!<PG[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PH        ((uint32_t)0x00000007)                 /*!<PH[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PI        ((uint32_t)0x00000008)                 /*!<PI[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PJ        ((uint32_t)0x00000009)                 /*!<PJ[12] pin */

+#define SYSCFG_EXTICR4_EXTI12_PK        ((uint32_t)0x0000000A)                 /*!<PK[12] pin */

+/**

+  * @brief   EXTI13 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000)                 /*!<PA[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010)                 /*!<PB[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020)                 /*!<PC[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030)                 /*!<PD[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040)                 /*!<PE[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000050)                 /*!<PF[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000060)                 /*!<PG[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PH        ((uint32_t)0x00000070)                 /*!<PH[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PI        ((uint32_t)0x00000080)                 /*!<PI[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PJ        ((uint32_t)0x00000090)                 /*!<PJ[13] pin */

+#define SYSCFG_EXTICR4_EXTI13_PK        ((uint32_t)0x000000A0)                 /*!<PK[13] pin */

+/**

+  * @brief   EXTI14 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000)                 /*!<PA[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100)                 /*!<PB[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200)                 /*!<PC[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300)                 /*!<PD[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400)                 /*!<PE[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000500)                 /*!<PF[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000600)                 /*!<PG[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PH        ((uint32_t)0x00000700)                 /*!<PH[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PI        ((uint32_t)0x00000800)                 /*!<PI[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PJ        ((uint32_t)0x00000900)                 /*!<PJ[14] pin */

+#define SYSCFG_EXTICR4_EXTI14_PK        ((uint32_t)0x00000A00)                 /*!<PK[14] pin */

+/**

+  * @brief   EXTI15 configuration

+  */

+#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000)                 /*!<PA[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000)                 /*!<PB[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000)                 /*!<PC[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000)                 /*!<PD[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000)                 /*!<PE[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00005000)                 /*!<PF[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00006000)                 /*!<PG[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PH        ((uint32_t)0x00007000)                 /*!<PH[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PI        ((uint32_t)0x00008000)                 /*!<PI[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PJ        ((uint32_t)0x00009000)                 /*!<PJ[15] pin */

+#define SYSCFG_EXTICR4_EXTI15_PK        ((uint32_t)0x0000A000)                 /*!<PK[15] pin */

+

+/******************  Bit definition for SYSCFG_CFGR register  ******************/

+#define SYSCFG_CFGR_PVDL_Pos            (2U)

+#define SYSCFG_CFGR_PVDL_Msk            (0x1UL << SYSCFG_CFGR_PVDL_Pos)        /*!< 0x00000004 */

+#define SYSCFG_CFGR_PVDL                SYSCFG_CFGR_PVDL_Msk                   /*!<PVD lock enable bit */

+#define SYSCFG_CFGR_FLASHL_Pos          (3U)

+#define SYSCFG_CFGR_FLASHL_Msk          (0x1UL << SYSCFG_CFGR_FLASHL_Pos)      /*!< 0x00000008 */

+#define SYSCFG_CFGR_FLASHL              SYSCFG_CFGR_FLASHL_Msk                 /*!<FLASH double ECC error lock bit */

+#define SYSCFG_CFGR_CM7L_Pos            (6U)

+#define SYSCFG_CFGR_CM7L_Msk            (0x1UL << SYSCFG_CFGR_CM7L_Pos)        /*!< 0x00000040 */

+#define SYSCFG_CFGR_CM7L                SYSCFG_CFGR_CM7L_Msk                   /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */

+#define SYSCFG_CFGR_DTCML_Pos           (13U)

+#define SYSCFG_CFGR_DTCML_Msk           (0x1UL << SYSCFG_CFGR_DTCML_Pos)       /*!< 0x00002000 */

+#define SYSCFG_CFGR_DTCML               SYSCFG_CFGR_DTCML_Msk                  /*!<DTCM double ECC error lock bit */

+#define SYSCFG_CFGR_ITCML_Pos           (14U)

+#define SYSCFG_CFGR_ITCML_Msk           (0x1UL << SYSCFG_CFGR_ITCML_Pos)       /*!< 0x00004000 */

+#define SYSCFG_CFGR_ITCML               SYSCFG_CFGR_ITCML_Msk                  /*!<ITCM double ECC error lock bit */

+/******************  Bit definition for SYSCFG_CCCSR register  ******************/

+#define SYSCFG_CCCSR_EN_Pos             (0U)

+#define SYSCFG_CCCSR_EN_Msk             (0x1UL << SYSCFG_CCCSR_EN_Pos)         /*!< 0x00000001 */

+#define SYSCFG_CCCSR_EN                 SYSCFG_CCCSR_EN_Msk                    /*!< I/O compensation cell enable */

+#define SYSCFG_CCCSR_CS_Pos             (1U)

+#define SYSCFG_CCCSR_CS_Msk             (0x1UL << SYSCFG_CCCSR_CS_Pos)         /*!< 0x00000002 */

+#define SYSCFG_CCCSR_CS                 SYSCFG_CCCSR_CS_Msk                    /*!< I/O compensation cell code selection */

+#define SYSCFG_CCCSR_CS_MMC_Pos         (3U)

+#define SYSCFG_CCCSR_CS_MMC_Msk         (0x1UL << SYSCFG_CCCSR_CS_MMC_Pos)         /*!< 0x00000004 */

+#define SYSCFG_CCCSR_CS_MMC             SYSCFG_CCCSR_CS_MMC_Msk                    /*!< I/O compensation cell code selection */

+#define SYSCFG_CCCSR_READY_Pos          (8U)

+#define SYSCFG_CCCSR_READY_Msk          (0x1UL << SYSCFG_CCCSR_READY_Pos)      /*!< 0x00000100 */

+#define SYSCFG_CCCSR_READY              SYSCFG_CCCSR_READY_Msk                 /*!< I/O compensation cell ready flag */

+#define SYSCFG_CCCSR_HSLV0_Pos           (16U)

+#define SYSCFG_CCCSR_HSLV0_Msk           (0x1UL << SYSCFG_CCCSR_HSLV0_Pos)       /*!< 0x00010000 */

+#define SYSCFG_CCCSR_HSLV0               SYSCFG_CCCSR_HSLV0_Msk                  /*!< High-speed at low-voltage */

+#define SYSCFG_CCCSR_HSLV1_Pos           (17U)

+#define SYSCFG_CCCSR_HSLV1_Msk           (0x1UL << SYSCFG_CCCSR_HSLV1_Pos)       /*!< 0x00020000 */

+#define SYSCFG_CCCSR_HSLV1               SYSCFG_CCCSR_HSLV1_Msk                  /*!< High-speed at low-voltage */

+#define SYSCFG_CCCSR_HSLV2_Pos           (18U)

+#define SYSCFG_CCCSR_HSLV2_Msk           (0x1UL << SYSCFG_CCCSR_HSLV2_Pos)       /*!< 0x00040000 */

+#define SYSCFG_CCCSR_HSLV2               SYSCFG_CCCSR_HSLV2_Msk                  /*!< High-speed at low-voltage */

+#define SYSCFG_CCCSR_HSLV3_Pos           (19U)

+#define SYSCFG_CCCSR_HSLV3_Msk           (0x1UL << SYSCFG_CCCSR_HSLV3_Pos)       /*!< 0x00080000 */

+#define SYSCFG_CCCSR_HSLV3               SYSCFG_CCCSR_HSLV3_Msk                  /*!< High-speed at low-voltage */

+/******************  Bit definition for SYSCFG_CCVR register  *******************/

+#define SYSCFG_CCVR_NCV_Pos             (0U)

+#define SYSCFG_CCVR_NCV_Msk             (0xFUL << SYSCFG_CCVR_NCV_Pos)         /*!< 0x0000000F */

+#define SYSCFG_CCVR_NCV                 SYSCFG_CCVR_NCV_Msk                    /*!< NMOS compensation value */

+#define SYSCFG_CCVR_PCV_Pos             (4U)

+#define SYSCFG_CCVR_PCV_Msk             (0xFUL << SYSCFG_CCVR_PCV_Pos)         /*!< 0x000000F0 */

+#define SYSCFG_CCVR_PCV                 SYSCFG_CCVR_PCV_Msk                    /*!< PMOS compensation value */

+

+/******************  Bit definition for SYSCFG_CCCR register  *******************/

+#define SYSCFG_CCCR_NCC_Pos             (0U)

+#define SYSCFG_CCCR_NCC_Msk             (0xFUL << SYSCFG_CCCR_NCC_Pos)         /*!< 0x0000000F */

+#define SYSCFG_CCCR_NCC                 SYSCFG_CCCR_NCC_Msk                    /*!< NMOS compensation code */

+#define SYSCFG_CCCR_PCC_Pos             (4U)

+#define SYSCFG_CCCR_PCC_Msk             (0xFUL << SYSCFG_CCCR_PCC_Pos)         /*!< 0x000000F0 */

+#define SYSCFG_CCCR_PCC                 SYSCFG_CCCR_PCC_Msk                    /*!< PMOS compensation code */

+#define SYSCFG_CCCR_NCC_MMC_Pos         (8U)

+#define SYSCFG_CCCR_NCC_MMC_Msk         (0xFUL << SYSCFG_CCCR_NCC_MMC_Pos)     /*!< 0x00000F00 */

+#define SYSCFG_CCCR_NCC_MMC             SYSCFG_CCCR_NCC_MMC_Msk                /*!< NMOS compensation code */

+#define SYSCFG_CCCR_PCC_MMC_Pos         (12U)

+#define SYSCFG_CCCR_PCC_MMC_Msk         (0xFUL << SYSCFG_CCCR_PCC_MMC_Pos)     /*!< 0x0000F000 */

+#define SYSCFG_CCCR_PCC_MMC             SYSCFG_CCCR_PCC_MMC_Msk                /*!< PMOS compensation code */

+/******************************************************************************/

+/*                                                                            */

+/*                    Digital Temperature Sensor (DTS)                        */

+/*                                                                            */

+/******************************************************************************/

+

+/******************  Bit definition for DTS_CFGR1 register  ******************/

+#define DTS_CFGR1_TS1_EN_Pos               (0U)

+#define DTS_CFGR1_TS1_EN_Msk               (0x1UL << DTS_CFGR1_TS1_EN_Pos) /*!< 0x00000001 */

+#define DTS_CFGR1_TS1_EN                   DTS_CFGR1_TS1_EN_Msk        /*!< DTS Enable */

+#define DTS_CFGR1_TS1_START_Pos            (4U)

+#define DTS_CFGR1_TS1_START_Msk            (0x1UL << DTS_CFGR1_TS1_START_Pos) /*!< 0x00000010 */

+#define DTS_CFGR1_TS1_START                DTS_CFGR1_TS1_START_Msk     /*!< Proceed to a frequency measurement on DTS */

+#define DTS_CFGR1_TS1_INTRIG_SEL_Pos       (8U)

+#define DTS_CFGR1_TS1_INTRIG_SEL_Msk       (0xFUL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000F00 */

+#define DTS_CFGR1_TS1_INTRIG_SEL           DTS_CFGR1_TS1_INTRIG_SEL_Msk /*!< Input triggers selection bits [3:0] for DTS */

+#define DTS_CFGR1_TS1_INTRIG_SEL_0         (0x1UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000100 */

+#define DTS_CFGR1_TS1_INTRIG_SEL_1         (0x2UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000200 */

+#define DTS_CFGR1_TS1_INTRIG_SEL_2         (0x4UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000400 */

+#define DTS_CFGR1_TS1_INTRIG_SEL_3         (0x8UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000800 */

+#define DTS_CFGR1_TS1_SMP_TIME_Pos         (16U)

+#define DTS_CFGR1_TS1_SMP_TIME_Msk         (0xFUL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x000F0000 */

+#define DTS_CFGR1_TS1_SMP_TIME             DTS_CFGR1_TS1_SMP_TIME_Msk  /*!< Sample time [3:0] for DTS */

+#define DTS_CFGR1_TS1_SMP_TIME_0           (0x1UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00010000 */

+#define DTS_CFGR1_TS1_SMP_TIME_1           (0x2UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00020000 */

+#define DTS_CFGR1_TS1_SMP_TIME_2           (0x4UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00040000 */

+#define DTS_CFGR1_TS1_SMP_TIME_3           (0x8UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00080000 */

+#define DTS_CFGR1_REFCLK_SEL_Pos           (20U)

+#define DTS_CFGR1_REFCLK_SEL_Msk           (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */

+#define DTS_CFGR1_REFCLK_SEL               DTS_CFGR1_REFCLK_SEL_Msk    /*!< Reference Clock Selection */

+#define DTS_CFGR1_Q_MEAS_OPT_Pos           (21U)

+#define DTS_CFGR1_Q_MEAS_OPT_Msk           (0x1UL << DTS_CFGR1_Q_MEAS_OPT_Pos) /*!< 0x00200000 */

+#define DTS_CFGR1_Q_MEAS_OPT               DTS_CFGR1_Q_MEAS_OPT_Msk    /*!< Quick measure option bit  */

+#define DTS_CFGR1_HSREF_CLK_DIV_Pos        (24U)

+#define DTS_CFGR1_HSREF_CLK_DIV_Msk        (0x7FUL << DTS_CFGR1_HSREF_CLK_DIV_Pos) /*!< 0x7F000000 */

+#define DTS_CFGR1_HSREF_CLK_DIV            DTS_CFGR1_HSREF_CLK_DIV_Msk /*!< High Speed Clock Divider Ratio [6:0]*/

+

+/******************  Bit definition for DTS_T0VALR1 register  ******************/

+#define DTS_T0VALR1_TS1_FMT0_Pos           (0U)

+#define DTS_T0VALR1_TS1_FMT0_Msk           (0xFFFFUL << DTS_T0VALR1_TS1_FMT0_Pos) /*!< 0x0000FFFF */

+#define DTS_T0VALR1_TS1_FMT0               DTS_T0VALR1_TS1_FMT0_Msk    /*!< Engineering value of the measured frequency at T0 for DTS */

+#define DTS_T0VALR1_TS1_T0_Pos             (16U)

+#define DTS_T0VALR1_TS1_T0_Msk             (0x3UL << DTS_T0VALR1_TS1_T0_Pos) /*!< 0x00030000 */

+#define DTS_T0VALR1_TS1_T0                 DTS_T0VALR1_TS1_T0_Msk      /*!< Engineering value of the DTSerature T0 for DTS */

+

+/******************  Bit definition for DTS_RAMPVALR register  ******************/

+#define DTS_RAMPVALR_TS1_RAMP_COEFF_Pos    (0U)

+#define DTS_RAMPVALR_TS1_RAMP_COEFF_Msk    (0xFFFFUL << DTS_RAMPVALR_TS1_RAMP_COEFF_Pos) /*!< 0x0000FFFF */

+#define DTS_RAMPVALR_TS1_RAMP_COEFF        DTS_RAMPVALR_TS1_RAMP_COEFF_Msk /*!< Engineering value of the ramp coefficient for DTS */

+

+/******************  Bit definition for DTS_ITR1 register      ******************/

+#define DTS_ITR1_TS1_LITTHD_Pos            (0U)

+#define DTS_ITR1_TS1_LITTHD_Msk            (0xFFFFUL << DTS_ITR1_TS1_LITTHD_Pos) /*!< 0x0000FFFF */

+#define DTS_ITR1_TS1_LITTHD                DTS_ITR1_TS1_LITTHD_Msk     /*!< Low interrupt threshold[15:0] for DTS */

+#define DTS_ITR1_TS1_HITTHD_Pos            (16U)

+#define DTS_ITR1_TS1_HITTHD_Msk            (0xFFFFUL << DTS_ITR1_TS1_HITTHD_Pos) /*!< 0xFFFF0000 */

+#define DTS_ITR1_TS1_HITTHD                DTS_ITR1_TS1_HITTHD_Msk     /*!< High interrupt threshold[15:0] for DTS */

+

+/******************  Bit definition for DTS_DR register        ******************/

+#define DTS_DR_TS1_MFREQ_Pos               (0U)

+#define DTS_DR_TS1_MFREQ_Msk               (0xFFFFUL << DTS_DR_TS1_MFREQ_Pos) /*!< 0x0000FFFF */

+#define DTS_DR_TS1_MFREQ                   DTS_DR_TS1_MFREQ_Msk        /*!< Measured Frequency[15:0] for DTS */

+

+/******************  Bit definition for DTS_SR register        ******************/

+#define DTS_SR_TS1_ITEF_Pos                (0U)

+#define DTS_SR_TS1_ITEF_Msk                (0x1UL << DTS_SR_TS1_ITEF_Pos) /*!< 0x00000001 */

+#define DTS_SR_TS1_ITEF                    DTS_SR_TS1_ITEF_Msk         /*!< Interrupt flag for end of measure for DTS */

+#define DTS_SR_TS1_ITLF_Pos                (1U)

+#define DTS_SR_TS1_ITLF_Msk                (0x1UL << DTS_SR_TS1_ITLF_Pos) /*!< 0x00000002 */

+#define DTS_SR_TS1_ITLF                    DTS_SR_TS1_ITLF_Msk         /*!< Interrupt flag for low threshold for DTS  */

+#define DTS_SR_TS1_ITHF_Pos                (2U)

+#define DTS_SR_TS1_ITHF_Msk                (0x1UL << DTS_SR_TS1_ITHF_Pos) /*!< 0x00000004 */

+#define DTS_SR_TS1_ITHF                    DTS_SR_TS1_ITHF_Msk         /*!< Interrupt flag for high threshold for DTS */

+#define DTS_SR_TS1_AITEF_Pos               (4U)

+#define DTS_SR_TS1_AITEF_Msk               (0x1UL << DTS_SR_TS1_AITEF_Pos) /*!< 0x00000010 */

+#define DTS_SR_TS1_AITEF                   DTS_SR_TS1_AITEF_Msk        /*!< Asynchronous interrupt flag for end of measure for DTS */

+#define DTS_SR_TS1_AITLF_Pos               (5U)

+#define DTS_SR_TS1_AITLF_Msk               (0x1UL << DTS_SR_TS1_AITLF_Pos) /*!< 0x00000020 */

+#define DTS_SR_TS1_AITLF                   DTS_SR_TS1_AITLF_Msk        /*!< Asynchronous interrupt flag for low threshold for DTS  */

+#define DTS_SR_TS1_AITHF_Pos               (6U)

+#define DTS_SR_TS1_AITHF_Msk               (0x1UL << DTS_SR_TS1_AITHF_Pos) /*!< 0x00000040 */

+#define DTS_SR_TS1_AITHF                   DTS_SR_TS1_AITHF_Msk        /*!< Asynchronous interrupt flag for high threshold for DTS */

+#define DTS_SR_TS1_RDY_Pos                 (15U)

+#define DTS_SR_TS1_RDY_Msk                 (0x1UL << DTS_SR_TS1_RDY_Pos) /*!< 0x00008000 */

+#define DTS_SR_TS1_RDY                     DTS_SR_TS1_RDY_Msk          /*!< DTS ready flag */

+

+/******************  Bit definition for DTS_ITENR register      ******************/

+#define DTS_ITENR_TS1_ITEEN_Pos            (0U)

+#define DTS_ITENR_TS1_ITEEN_Msk            (0x1UL << DTS_ITENR_TS1_ITEEN_Pos) /*!< 0x00000001 */

+#define DTS_ITENR_TS1_ITEEN                DTS_ITENR_TS1_ITEEN_Msk     /*!< Enable interrupt flag for end of measure for DTS */

+#define DTS_ITENR_TS1_ITLEN_Pos            (1U)

+#define DTS_ITENR_TS1_ITLEN_Msk            (0x1UL << DTS_ITENR_TS1_ITLEN_Pos) /*!< 0x00000002 */

+#define DTS_ITENR_TS1_ITLEN                DTS_ITENR_TS1_ITLEN_Msk     /*!< Enable interrupt flag for low threshold for DTS  */

+#define DTS_ITENR_TS1_ITHEN_Pos            (2U)

+#define DTS_ITENR_TS1_ITHEN_Msk            (0x1UL << DTS_ITENR_TS1_ITHEN_Pos) /*!< 0x00000004 */

+#define DTS_ITENR_TS1_ITHEN                DTS_ITENR_TS1_ITHEN_Msk     /*!< Enable interrupt flag for high threshold for DTS */

+#define DTS_ITENR_TS1_AITEEN_Pos           (4U)

+#define DTS_ITENR_TS1_AITEEN_Msk           (0x1UL << DTS_ITENR_TS1_AITEEN_Pos) /*!< 0x00000010 */

+#define DTS_ITENR_TS1_AITEEN               DTS_ITENR_TS1_AITEEN_Msk    /*!< Enable asynchronous interrupt flag for end of measure for DTS */

+#define DTS_ITENR_TS1_AITLEN_Pos           (5U)

+#define DTS_ITENR_TS1_AITLEN_Msk           (0x1UL << DTS_ITENR_TS1_AITLEN_Pos) /*!< 0x00000020 */

+#define DTS_ITENR_TS1_AITLEN               DTS_ITENR_TS1_AITLEN_Msk    /*!< Enable Asynchronous interrupt flag for low threshold for DTS  */

+#define DTS_ITENR_TS1_AITHEN_Pos           (6U)

+#define DTS_ITENR_TS1_AITHEN_Msk           (0x1UL << DTS_ITENR_TS1_AITHEN_Pos) /*!< 0x00000040 */

+#define DTS_ITENR_TS1_AITHEN               DTS_ITENR_TS1_AITHEN_Msk    /*!< Enable asynchronous interrupt flag for high threshold for DTS */

+

+/******************  Bit definition for DTS_ICIFR register      ******************/

+#define DTS_ICIFR_TS1_CITEF_Pos            (0U)

+#define DTS_ICIFR_TS1_CITEF_Msk            (0x1UL << DTS_ICIFR_TS1_CITEF_Pos) /*!< 0x00000001 */

+#define DTS_ICIFR_TS1_CITEF                DTS_ICIFR_TS1_CITEF_Msk     /*!< Clear the IT flag for End Of Measure for DTS */

+#define DTS_ICIFR_TS1_CITLF_Pos            (1U)

+#define DTS_ICIFR_TS1_CITLF_Msk            (0x1UL << DTS_ICIFR_TS1_CITLF_Pos) /*!< 0x00000002 */

+#define DTS_ICIFR_TS1_CITLF                DTS_ICIFR_TS1_CITLF_Msk     /*!< Clear the IT flag for low threshold for DTS  */

+#define DTS_ICIFR_TS1_CITHF_Pos            (2U)

+#define DTS_ICIFR_TS1_CITHF_Msk            (0x1UL << DTS_ICIFR_TS1_CITHF_Pos) /*!< 0x00000004 */

+#define DTS_ICIFR_TS1_CITHF                DTS_ICIFR_TS1_CITHF_Msk     /*!< Clear the IT flag for high threshold on DTS  */

+#define DTS_ICIFR_TS1_CAITEF_Pos           (4U)

+#define DTS_ICIFR_TS1_CAITEF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITEF_Pos) /*!< 0x00000010 */

+#define DTS_ICIFR_TS1_CAITEF               DTS_ICIFR_TS1_CAITEF_Msk    /*!< Clear the asynchronous IT flag for End Of Measure for DTS */

+#define DTS_ICIFR_TS1_CAITLF_Pos           (5U)

+#define DTS_ICIFR_TS1_CAITLF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITLF_Pos) /*!< 0x00000020 */

+#define DTS_ICIFR_TS1_CAITLF               DTS_ICIFR_TS1_CAITLF_Msk    /*!< Clear the asynchronous IT flag for low threshold for DTS  */

+#define DTS_ICIFR_TS1_CAITHF_Pos           (6U)

+#define DTS_ICIFR_TS1_CAITHF_Msk           (0x1UL << DTS_ICIFR_TS1_CAITHF_Pos) /*!< 0x00000040 */

+#define DTS_ICIFR_TS1_CAITHF               DTS_ICIFR_TS1_CAITHF_Msk    /*!< Clear the asynchronous IT flag for high threshold on DTS  */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    TIM                                     */

+/*                                                                            */

+/******************************************************************************/

+#define TIM_BREAK_INPUT_SUPPORT             /*!<TIM Break input feature */

+

+/*******************  Bit definition for TIM_CR1 register  ********************/

+#define TIM_CR1_CEN_Pos           (0U)

+#define TIM_CR1_CEN_Msk           (0x1UL << TIM_CR1_CEN_Pos)                   /*!< 0x00000001 */

+#define TIM_CR1_CEN               TIM_CR1_CEN_Msk                              /*!<Counter enable */

+#define TIM_CR1_UDIS_Pos          (1U)

+#define TIM_CR1_UDIS_Msk          (0x1UL << TIM_CR1_UDIS_Pos)                  /*!< 0x00000002 */

+#define TIM_CR1_UDIS              TIM_CR1_UDIS_Msk                             /*!<Update disable */

+#define TIM_CR1_URS_Pos           (2U)

+#define TIM_CR1_URS_Msk           (0x1UL << TIM_CR1_URS_Pos)                   /*!< 0x00000004 */

+#define TIM_CR1_URS               TIM_CR1_URS_Msk                              /*!<Update request source */

+#define TIM_CR1_OPM_Pos           (3U)

+#define TIM_CR1_OPM_Msk           (0x1UL << TIM_CR1_OPM_Pos)                   /*!< 0x00000008 */

+#define TIM_CR1_OPM               TIM_CR1_OPM_Msk                              /*!<One pulse mode */

+#define TIM_CR1_DIR_Pos           (4U)

+#define TIM_CR1_DIR_Msk           (0x1UL << TIM_CR1_DIR_Pos)                   /*!< 0x00000010 */

+#define TIM_CR1_DIR               TIM_CR1_DIR_Msk                              /*!<Direction */

+

+#define TIM_CR1_CMS_Pos           (5U)

+#define TIM_CR1_CMS_Msk           (0x3UL << TIM_CR1_CMS_Pos)                   /*!< 0x00000060 */

+#define TIM_CR1_CMS               TIM_CR1_CMS_Msk                              /*!<CMS[1:0] bits (Center-aligned mode selection) */

+#define TIM_CR1_CMS_0             (0x1UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000020 */

+#define TIM_CR1_CMS_1             (0x2UL << TIM_CR1_CMS_Pos)                    /*!< 0x00000040 */

+

+#define TIM_CR1_ARPE_Pos          (7U)

+#define TIM_CR1_ARPE_Msk          (0x1UL << TIM_CR1_ARPE_Pos)                  /*!< 0x00000080 */

+#define TIM_CR1_ARPE              TIM_CR1_ARPE_Msk                             /*!<Auto-reload preload enable */

+

+#define TIM_CR1_CKD_Pos           (8U)

+#define TIM_CR1_CKD_Msk           (0x3UL << TIM_CR1_CKD_Pos)                   /*!< 0x00000300 */

+#define TIM_CR1_CKD               TIM_CR1_CKD_Msk                              /*!<CKD[1:0] bits (clock division) */

+#define TIM_CR1_CKD_0             (0x1UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000100 */

+#define TIM_CR1_CKD_1             (0x2UL << TIM_CR1_CKD_Pos)                    /*!< 0x00000200 */

+

+#define TIM_CR1_UIFREMAP_Pos      (11U)

+#define TIM_CR1_UIFREMAP_Msk      (0x1UL << TIM_CR1_UIFREMAP_Pos)              /*!< 0x00000800 */

+#define TIM_CR1_UIFREMAP          TIM_CR1_UIFREMAP_Msk                         /*!<Update interrupt flag remap */

+

+/*******************  Bit definition for TIM_CR2 register  ********************/

+#define TIM_CR2_CCPC_Pos          (0U)

+#define TIM_CR2_CCPC_Msk          (0x1UL << TIM_CR2_CCPC_Pos)                  /*!< 0x00000001 */

+#define TIM_CR2_CCPC              TIM_CR2_CCPC_Msk                             /*!<Capture/Compare Preloaded Control */

+#define TIM_CR2_CCUS_Pos          (2U)

+#define TIM_CR2_CCUS_Msk          (0x1UL << TIM_CR2_CCUS_Pos)                  /*!< 0x00000004 */

+#define TIM_CR2_CCUS              TIM_CR2_CCUS_Msk                             /*!<Capture/Compare Control Update Selection */

+#define TIM_CR2_CCDS_Pos          (3U)

+#define TIM_CR2_CCDS_Msk          (0x1UL << TIM_CR2_CCDS_Pos)                  /*!< 0x00000008 */

+#define TIM_CR2_CCDS              TIM_CR2_CCDS_Msk                             /*!<Capture/Compare DMA Selection */

+

+#define TIM_CR2_MMS_Pos           (4U)

+#define TIM_CR2_MMS_Msk           (0x7UL << TIM_CR2_MMS_Pos)                   /*!< 0x00000070 */

+#define TIM_CR2_MMS               TIM_CR2_MMS_Msk                              /*!<MMS[2:0] bits (Master Mode Selection) */

+#define TIM_CR2_MMS_0             (0x1UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000010 */

+#define TIM_CR2_MMS_1             (0x2UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000020 */

+#define TIM_CR2_MMS_2             (0x4UL << TIM_CR2_MMS_Pos)                    /*!< 0x00000040 */

+

+#define TIM_CR2_TI1S_Pos          (7U)

+#define TIM_CR2_TI1S_Msk          (0x1UL << TIM_CR2_TI1S_Pos)                  /*!< 0x00000080 */

+#define TIM_CR2_TI1S              TIM_CR2_TI1S_Msk                             /*!<TI1 Selection */

+#define TIM_CR2_OIS1_Pos          (8U)

+#define TIM_CR2_OIS1_Msk          (0x1UL << TIM_CR2_OIS1_Pos)                  /*!< 0x00000100 */

+#define TIM_CR2_OIS1              TIM_CR2_OIS1_Msk                             /*!<Output Idle state 1 (OC1 output) */

+#define TIM_CR2_OIS1N_Pos         (9U)

+#define TIM_CR2_OIS1N_Msk         (0x1UL << TIM_CR2_OIS1N_Pos)                 /*!< 0x00000200 */

+#define TIM_CR2_OIS1N             TIM_CR2_OIS1N_Msk                            /*!<Output Idle state 1 (OC1N output) */

+#define TIM_CR2_OIS2_Pos          (10U)

+#define TIM_CR2_OIS2_Msk          (0x1UL << TIM_CR2_OIS2_Pos)                  /*!< 0x00000400 */

+#define TIM_CR2_OIS2              TIM_CR2_OIS2_Msk                             /*!<Output Idle state 2 (OC2 output) */

+#define TIM_CR2_OIS2N_Pos         (11U)

+#define TIM_CR2_OIS2N_Msk         (0x1UL << TIM_CR2_OIS2N_Pos)                 /*!< 0x00000800 */

+#define TIM_CR2_OIS2N             TIM_CR2_OIS2N_Msk                            /*!<Output Idle state 2 (OC2N output) */

+#define TIM_CR2_OIS3_Pos          (12U)

+#define TIM_CR2_OIS3_Msk          (0x1UL << TIM_CR2_OIS3_Pos)                  /*!< 0x00001000 */

+#define TIM_CR2_OIS3              TIM_CR2_OIS3_Msk                             /*!<Output Idle state 3 (OC3 output) */

+#define TIM_CR2_OIS3N_Pos         (13U)

+#define TIM_CR2_OIS3N_Msk         (0x1UL << TIM_CR2_OIS3N_Pos)                 /*!< 0x00002000 */

+#define TIM_CR2_OIS3N             TIM_CR2_OIS3N_Msk                            /*!<Output Idle state 3 (OC3N output) */

+#define TIM_CR2_OIS4_Pos          (14U)

+#define TIM_CR2_OIS4_Msk          (0x1UL << TIM_CR2_OIS4_Pos)                  /*!< 0x00004000 */

+#define TIM_CR2_OIS4              TIM_CR2_OIS4_Msk                             /*!<Output Idle state 4 (OC4 output) */

+#define TIM_CR2_OIS5_Pos          (16U)

+#define TIM_CR2_OIS5_Msk          (0x1UL << TIM_CR2_OIS5_Pos)                  /*!< 0x00010000 */

+#define TIM_CR2_OIS5              TIM_CR2_OIS5_Msk                             /*!<Output Idle state 4 (OC4 output) */

+#define TIM_CR2_OIS6_Pos          (17U)

+#define TIM_CR2_OIS6_Msk          (0x1UL << TIM_CR2_OIS6_Pos)                  /*!< 0x00020000 */

+#define TIM_CR2_OIS6              TIM_CR2_OIS6_Msk                             /*!<Output Idle state 4 (OC4 output) */

+

+#define TIM_CR2_MMS2_Pos          (20U)

+#define TIM_CR2_MMS2_Msk          (0xFUL << TIM_CR2_MMS2_Pos)                  /*!< 0x00F00000 */

+#define TIM_CR2_MMS2              TIM_CR2_MMS2_Msk                             /*!<MMS[2:0] bits (Master Mode Selection) */

+#define TIM_CR2_MMS2_0            (0x1UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00100000 */

+#define TIM_CR2_MMS2_1            (0x2UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00200000 */

+#define TIM_CR2_MMS2_2            (0x4UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00400000 */

+#define TIM_CR2_MMS2_3            (0x8UL << TIM_CR2_MMS2_Pos)                   /*!< 0x00800000 */

+

+/*******************  Bit definition for TIM_SMCR register  *******************/

+#define TIM_SMCR_SMS_Pos          (0U)

+#define TIM_SMCR_SMS_Msk          (0x10007UL << TIM_SMCR_SMS_Pos)              /*!< 0x00010007 */

+#define TIM_SMCR_SMS              TIM_SMCR_SMS_Msk                             /*!<SMS[2:0] bits (Slave mode selection) */

+#define TIM_SMCR_SMS_0            (0x00001UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000001 */

+#define TIM_SMCR_SMS_1            (0x00002UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000002 */

+#define TIM_SMCR_SMS_2            (0x00004UL << TIM_SMCR_SMS_Pos)               /*!< 0x00000004 */

+#define TIM_SMCR_SMS_3            (0x10000UL << TIM_SMCR_SMS_Pos)               /*!< 0x00010000 */

+

+#define TIM_SMCR_TS_Pos           (4U)

+#define TIM_SMCR_TS_Msk           (0x30007UL << TIM_SMCR_TS_Pos)               /*!< 0x00300070 */

+#define TIM_SMCR_TS               TIM_SMCR_TS_Msk                              /*!<TS[4:0] bits (Trigger selection) */

+#define TIM_SMCR_TS_0             (0x00001UL << TIM_SMCR_TS_Pos)                /*!< 0x00000010 */

+#define TIM_SMCR_TS_1             (0x00002UL << TIM_SMCR_TS_Pos)                /*!< 0x00000020 */

+#define TIM_SMCR_TS_2             (0x00004UL << TIM_SMCR_TS_Pos)                /*!< 0x00000040 */

+#define TIM_SMCR_TS_3             (0x10000UL << TIM_SMCR_TS_Pos)                /*!< 0x00100000 */

+#define TIM_SMCR_TS_4             (0x20000UL << TIM_SMCR_TS_Pos)                /*!< 0x00200000 */

+

+#define TIM_SMCR_MSM_Pos          (7U)

+#define TIM_SMCR_MSM_Msk          (0x1UL << TIM_SMCR_MSM_Pos)                  /*!< 0x00000080 */

+#define TIM_SMCR_MSM              TIM_SMCR_MSM_Msk                             /*!<Master/slave mode */

+

+#define TIM_SMCR_ETF_Pos          (8U)

+#define TIM_SMCR_ETF_Msk          (0xFUL << TIM_SMCR_ETF_Pos)                  /*!< 0x00000F00 */

+#define TIM_SMCR_ETF              TIM_SMCR_ETF_Msk                             /*!<ETF[3:0] bits (External trigger filter) */

+#define TIM_SMCR_ETF_0            (0x1UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000100 */

+#define TIM_SMCR_ETF_1            (0x2UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000200 */

+#define TIM_SMCR_ETF_2            (0x4UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000400 */

+#define TIM_SMCR_ETF_3            (0x8UL << TIM_SMCR_ETF_Pos)                   /*!< 0x00000800 */

+

+#define TIM_SMCR_ETPS_Pos         (12U)

+#define TIM_SMCR_ETPS_Msk         (0x3UL << TIM_SMCR_ETPS_Pos)                 /*!< 0x00003000 */

+#define TIM_SMCR_ETPS             TIM_SMCR_ETPS_Msk                            /*!<ETPS[1:0] bits (External trigger prescaler) */

+#define TIM_SMCR_ETPS_0           (0x1UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00001000 */

+#define TIM_SMCR_ETPS_1           (0x2UL << TIM_SMCR_ETPS_Pos)                  /*!< 0x00002000 */

+

+#define TIM_SMCR_ECE_Pos          (14U)

+#define TIM_SMCR_ECE_Msk          (0x1UL << TIM_SMCR_ECE_Pos)                  /*!< 0x00004000 */

+#define TIM_SMCR_ECE              TIM_SMCR_ECE_Msk                             /*!<External clock enable */

+#define TIM_SMCR_ETP_Pos          (15U)

+#define TIM_SMCR_ETP_Msk          (0x1UL << TIM_SMCR_ETP_Pos)                  /*!< 0x00008000 */

+#define TIM_SMCR_ETP              TIM_SMCR_ETP_Msk                             /*!<External trigger polarity */

+

+/*******************  Bit definition for TIM_DIER register  *******************/

+#define TIM_DIER_UIE_Pos          (0U)

+#define TIM_DIER_UIE_Msk          (0x1UL << TIM_DIER_UIE_Pos)                  /*!< 0x00000001 */

+#define TIM_DIER_UIE              TIM_DIER_UIE_Msk                             /*!<Update interrupt enable */

+#define TIM_DIER_CC1IE_Pos        (1U)

+#define TIM_DIER_CC1IE_Msk        (0x1UL << TIM_DIER_CC1IE_Pos)                /*!< 0x00000002 */

+#define TIM_DIER_CC1IE            TIM_DIER_CC1IE_Msk                           /*!<Capture/Compare 1 interrupt enable */

+#define TIM_DIER_CC2IE_Pos        (2U)

+#define TIM_DIER_CC2IE_Msk        (0x1UL << TIM_DIER_CC2IE_Pos)                /*!< 0x00000004 */

+#define TIM_DIER_CC2IE            TIM_DIER_CC2IE_Msk                           /*!<Capture/Compare 2 interrupt enable */

+#define TIM_DIER_CC3IE_Pos        (3U)

+#define TIM_DIER_CC3IE_Msk        (0x1UL << TIM_DIER_CC3IE_Pos)                /*!< 0x00000008 */

+#define TIM_DIER_CC3IE            TIM_DIER_CC3IE_Msk                           /*!<Capture/Compare 3 interrupt enable */

+#define TIM_DIER_CC4IE_Pos        (4U)

+#define TIM_DIER_CC4IE_Msk        (0x1UL << TIM_DIER_CC4IE_Pos)                /*!< 0x00000010 */

+#define TIM_DIER_CC4IE            TIM_DIER_CC4IE_Msk                           /*!<Capture/Compare 4 interrupt enable */

+#define TIM_DIER_COMIE_Pos        (5U)

+#define TIM_DIER_COMIE_Msk        (0x1UL << TIM_DIER_COMIE_Pos)                /*!< 0x00000020 */

+#define TIM_DIER_COMIE            TIM_DIER_COMIE_Msk                           /*!<COM interrupt enable */

+#define TIM_DIER_TIE_Pos          (6U)

+#define TIM_DIER_TIE_Msk          (0x1UL << TIM_DIER_TIE_Pos)                  /*!< 0x00000040 */

+#define TIM_DIER_TIE              TIM_DIER_TIE_Msk                             /*!<Trigger interrupt enable */

+#define TIM_DIER_BIE_Pos          (7U)

+#define TIM_DIER_BIE_Msk          (0x1UL << TIM_DIER_BIE_Pos)                  /*!< 0x00000080 */

+#define TIM_DIER_BIE              TIM_DIER_BIE_Msk                             /*!<Break interrupt enable */

+#define TIM_DIER_UDE_Pos          (8U)

+#define TIM_DIER_UDE_Msk          (0x1UL << TIM_DIER_UDE_Pos)                  /*!< 0x00000100 */

+#define TIM_DIER_UDE              TIM_DIER_UDE_Msk                             /*!<Update DMA request enable */

+#define TIM_DIER_CC1DE_Pos        (9U)

+#define TIM_DIER_CC1DE_Msk        (0x1UL << TIM_DIER_CC1DE_Pos)                /*!< 0x00000200 */

+#define TIM_DIER_CC1DE            TIM_DIER_CC1DE_Msk                           /*!<Capture/Compare 1 DMA request enable */

+#define TIM_DIER_CC2DE_Pos        (10U)

+#define TIM_DIER_CC2DE_Msk        (0x1UL << TIM_DIER_CC2DE_Pos)                /*!< 0x00000400 */

+#define TIM_DIER_CC2DE            TIM_DIER_CC2DE_Msk                           /*!<Capture/Compare 2 DMA request enable */

+#define TIM_DIER_CC3DE_Pos        (11U)

+#define TIM_DIER_CC3DE_Msk        (0x1UL << TIM_DIER_CC3DE_Pos)                /*!< 0x00000800 */

+#define TIM_DIER_CC3DE            TIM_DIER_CC3DE_Msk                           /*!<Capture/Compare 3 DMA request enable */

+#define TIM_DIER_CC4DE_Pos        (12U)

+#define TIM_DIER_CC4DE_Msk        (0x1UL << TIM_DIER_CC4DE_Pos)                /*!< 0x00001000 */

+#define TIM_DIER_CC4DE            TIM_DIER_CC4DE_Msk                           /*!<Capture/Compare 4 DMA request enable */

+#define TIM_DIER_COMDE_Pos        (13U)

+#define TIM_DIER_COMDE_Msk        (0x1UL << TIM_DIER_COMDE_Pos)                /*!< 0x00002000 */

+#define TIM_DIER_COMDE            TIM_DIER_COMDE_Msk                           /*!<COM DMA request enable */

+#define TIM_DIER_TDE_Pos          (14U)

+#define TIM_DIER_TDE_Msk          (0x1UL << TIM_DIER_TDE_Pos)                  /*!< 0x00004000 */

+#define TIM_DIER_TDE              TIM_DIER_TDE_Msk                             /*!<Trigger DMA request enable */

+

+/********************  Bit definition for TIM_SR register  ********************/

+#define TIM_SR_UIF_Pos            (0U)

+#define TIM_SR_UIF_Msk            (0x1UL << TIM_SR_UIF_Pos)                    /*!< 0x00000001 */

+#define TIM_SR_UIF                TIM_SR_UIF_Msk                               /*!<Update interrupt Flag */

+#define TIM_SR_CC1IF_Pos          (1U)

+#define TIM_SR_CC1IF_Msk          (0x1UL << TIM_SR_CC1IF_Pos)                  /*!< 0x00000002 */

+#define TIM_SR_CC1IF              TIM_SR_CC1IF_Msk                             /*!<Capture/Compare 1 interrupt Flag */

+#define TIM_SR_CC2IF_Pos          (2U)

+#define TIM_SR_CC2IF_Msk          (0x1UL << TIM_SR_CC2IF_Pos)                  /*!< 0x00000004 */

+#define TIM_SR_CC2IF              TIM_SR_CC2IF_Msk                             /*!<Capture/Compare 2 interrupt Flag */

+#define TIM_SR_CC3IF_Pos          (3U)

+#define TIM_SR_CC3IF_Msk          (0x1UL << TIM_SR_CC3IF_Pos)                  /*!< 0x00000008 */

+#define TIM_SR_CC3IF              TIM_SR_CC3IF_Msk                             /*!<Capture/Compare 3 interrupt Flag */

+#define TIM_SR_CC4IF_Pos          (4U)

+#define TIM_SR_CC4IF_Msk          (0x1UL << TIM_SR_CC4IF_Pos)                  /*!< 0x00000010 */

+#define TIM_SR_CC4IF              TIM_SR_CC4IF_Msk                             /*!<Capture/Compare 4 interrupt Flag */

+#define TIM_SR_COMIF_Pos          (5U)

+#define TIM_SR_COMIF_Msk          (0x1UL << TIM_SR_COMIF_Pos)                  /*!< 0x00000020 */

+#define TIM_SR_COMIF              TIM_SR_COMIF_Msk                             /*!<COM interrupt Flag */

+#define TIM_SR_TIF_Pos            (6U)

+#define TIM_SR_TIF_Msk            (0x1UL << TIM_SR_TIF_Pos)                    /*!< 0x00000040 */

+#define TIM_SR_TIF                TIM_SR_TIF_Msk                               /*!<Trigger interrupt Flag */

+#define TIM_SR_BIF_Pos            (7U)

+#define TIM_SR_BIF_Msk            (0x1UL << TIM_SR_BIF_Pos)                    /*!< 0x00000080 */

+#define TIM_SR_BIF                TIM_SR_BIF_Msk                               /*!<Break interrupt Flag */

+#define TIM_SR_B2IF_Pos           (8U)

+#define TIM_SR_B2IF_Msk           (0x1UL << TIM_SR_B2IF_Pos)                   /*!< 0x00000100 */

+#define TIM_SR_B2IF               TIM_SR_B2IF_Msk                              /*!<Break2 interrupt Flag */

+#define TIM_SR_CC1OF_Pos          (9U)

+#define TIM_SR_CC1OF_Msk          (0x1UL << TIM_SR_CC1OF_Pos)                  /*!< 0x00000200 */

+#define TIM_SR_CC1OF              TIM_SR_CC1OF_Msk                             /*!<Capture/Compare 1 Overcapture Flag */

+#define TIM_SR_CC2OF_Pos          (10U)

+#define TIM_SR_CC2OF_Msk          (0x1UL << TIM_SR_CC2OF_Pos)                  /*!< 0x00000400 */

+#define TIM_SR_CC2OF              TIM_SR_CC2OF_Msk                             /*!<Capture/Compare 2 Overcapture Flag */

+#define TIM_SR_CC3OF_Pos          (11U)

+#define TIM_SR_CC3OF_Msk          (0x1UL << TIM_SR_CC3OF_Pos)                  /*!< 0x00000800 */

+#define TIM_SR_CC3OF              TIM_SR_CC3OF_Msk                             /*!<Capture/Compare 3 Overcapture Flag */

+#define TIM_SR_CC4OF_Pos          (12U)

+#define TIM_SR_CC4OF_Msk          (0x1UL << TIM_SR_CC4OF_Pos)                  /*!< 0x00001000 */

+#define TIM_SR_CC4OF              TIM_SR_CC4OF_Msk                             /*!<Capture/Compare 4 Overcapture Flag */

+#define TIM_SR_CC5IF_Pos          (16U)

+#define TIM_SR_CC5IF_Msk          (0x1UL << TIM_SR_CC5IF_Pos)                  /*!< 0x00010000 */

+#define TIM_SR_CC5IF              TIM_SR_CC5IF_Msk                             /*!<Capture/Compare 5 interrupt Flag */

+#define TIM_SR_CC6IF_Pos          (17U)

+#define TIM_SR_CC6IF_Msk          (0x1UL << TIM_SR_CC6IF_Pos)                  /*!< 0x00020000 */

+#define TIM_SR_CC6IF              TIM_SR_CC6IF_Msk                             /*!<Capture/Compare 6 interrupt Flag */

+#define TIM_SR_SBIF_Pos           (13U)

+#define TIM_SR_SBIF_Msk           (0x1UL << TIM_SR_SBIF_Pos)                   /*!< 0x00002000 */

+#define TIM_SR_SBIF               TIM_SR_SBIF_Msk                              /*!< System Break Flag */

+

+/*******************  Bit definition for TIM_EGR register  ********************/

+#define TIM_EGR_UG_Pos            (0U)

+#define TIM_EGR_UG_Msk            (0x1UL << TIM_EGR_UG_Pos)                    /*!< 0x00000001 */

+#define TIM_EGR_UG                TIM_EGR_UG_Msk                               /*!<Update Generation */

+#define TIM_EGR_CC1G_Pos          (1U)

+#define TIM_EGR_CC1G_Msk          (0x1UL << TIM_EGR_CC1G_Pos)                  /*!< 0x00000002 */

+#define TIM_EGR_CC1G              TIM_EGR_CC1G_Msk                             /*!<Capture/Compare 1 Generation */

+#define TIM_EGR_CC2G_Pos          (2U)

+#define TIM_EGR_CC2G_Msk          (0x1UL << TIM_EGR_CC2G_Pos)                  /*!< 0x00000004 */

+#define TIM_EGR_CC2G              TIM_EGR_CC2G_Msk                             /*!<Capture/Compare 2 Generation */

+#define TIM_EGR_CC3G_Pos          (3U)

+#define TIM_EGR_CC3G_Msk          (0x1UL << TIM_EGR_CC3G_Pos)                  /*!< 0x00000008 */

+#define TIM_EGR_CC3G              TIM_EGR_CC3G_Msk                             /*!<Capture/Compare 3 Generation */

+#define TIM_EGR_CC4G_Pos          (4U)

+#define TIM_EGR_CC4G_Msk          (0x1UL << TIM_EGR_CC4G_Pos)                  /*!< 0x00000010 */

+#define TIM_EGR_CC4G              TIM_EGR_CC4G_Msk                             /*!<Capture/Compare 4 Generation */

+#define TIM_EGR_COMG_Pos          (5U)

+#define TIM_EGR_COMG_Msk          (0x1UL << TIM_EGR_COMG_Pos)                  /*!< 0x00000020 */

+#define TIM_EGR_COMG              TIM_EGR_COMG_Msk                             /*!<Capture/Compare Control Update Generation */

+#define TIM_EGR_TG_Pos            (6U)

+#define TIM_EGR_TG_Msk            (0x1UL << TIM_EGR_TG_Pos)                    /*!< 0x00000040 */

+#define TIM_EGR_TG                TIM_EGR_TG_Msk                               /*!<Trigger Generation */

+#define TIM_EGR_BG_Pos            (7U)

+#define TIM_EGR_BG_Msk            (0x1UL << TIM_EGR_BG_Pos)                    /*!< 0x00000080 */

+#define TIM_EGR_BG                TIM_EGR_BG_Msk                               /*!<Break Generation */

+#define TIM_EGR_B2G_Pos           (8U)

+#define TIM_EGR_B2G_Msk           (0x1UL << TIM_EGR_B2G_Pos)                   /*!< 0x00000100 */

+#define TIM_EGR_B2G               TIM_EGR_B2G_Msk                              /*!<Break Generation */

+

+

+/******************  Bit definition for TIM_CCMR1 register  *******************/

+#define TIM_CCMR1_CC1S_Pos        (0U)

+#define TIM_CCMR1_CC1S_Msk        (0x3UL << TIM_CCMR1_CC1S_Pos)                /*!< 0x00000003 */

+#define TIM_CCMR1_CC1S            TIM_CCMR1_CC1S_Msk                           /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */

+#define TIM_CCMR1_CC1S_0          (0x1UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000001 */

+#define TIM_CCMR1_CC1S_1          (0x2UL << TIM_CCMR1_CC1S_Pos)                 /*!< 0x00000002 */

+

+#define TIM_CCMR1_OC1FE_Pos       (2U)

+#define TIM_CCMR1_OC1FE_Msk       (0x1UL << TIM_CCMR1_OC1FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR1_OC1FE           TIM_CCMR1_OC1FE_Msk                          /*!<Output Compare 1 Fast enable */

+#define TIM_CCMR1_OC1PE_Pos       (3U)

+#define TIM_CCMR1_OC1PE_Msk       (0x1UL << TIM_CCMR1_OC1PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR1_OC1PE           TIM_CCMR1_OC1PE_Msk                          /*!<Output Compare 1 Preload enable */

+

+#define TIM_CCMR1_OC1M_Pos        (4U)

+#define TIM_CCMR1_OC1M_Msk        (0x1007UL << TIM_CCMR1_OC1M_Pos)             /*!< 0x00010070 */

+#define TIM_CCMR1_OC1M            TIM_CCMR1_OC1M_Msk                           /*!<OC1M[2:0] bits (Output Compare 1 Mode) */

+#define TIM_CCMR1_OC1M_0          (0x0001UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000010 */

+#define TIM_CCMR1_OC1M_1          (0x0002UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000020 */

+#define TIM_CCMR1_OC1M_2          (0x0004UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00000040 */

+#define TIM_CCMR1_OC1M_3          (0x1000UL << TIM_CCMR1_OC1M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR1_OC1CE_Pos       (7U)

+#define TIM_CCMR1_OC1CE_Msk       (0x1UL << TIM_CCMR1_OC1CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR1_OC1CE           TIM_CCMR1_OC1CE_Msk                          /*!<Output Compare 1Clear Enable */

+

+#define TIM_CCMR1_CC2S_Pos        (8U)

+#define TIM_CCMR1_CC2S_Msk        (0x3UL << TIM_CCMR1_CC2S_Pos)                /*!< 0x00000300 */

+#define TIM_CCMR1_CC2S            TIM_CCMR1_CC2S_Msk                           /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */

+#define TIM_CCMR1_CC2S_0          (0x1UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000100 */

+#define TIM_CCMR1_CC2S_1          (0x2UL << TIM_CCMR1_CC2S_Pos)                 /*!< 0x00000200 */

+

+#define TIM_CCMR1_OC2FE_Pos       (10U)

+#define TIM_CCMR1_OC2FE_Msk       (0x1UL << TIM_CCMR1_OC2FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR1_OC2FE           TIM_CCMR1_OC2FE_Msk                          /*!<Output Compare 2 Fast enable */

+#define TIM_CCMR1_OC2PE_Pos       (11U)

+#define TIM_CCMR1_OC2PE_Msk       (0x1UL << TIM_CCMR1_OC2PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR1_OC2PE           TIM_CCMR1_OC2PE_Msk                          /*!<Output Compare 2 Preload enable */

+

+#define TIM_CCMR1_OC2M_Pos        (12U)

+#define TIM_CCMR1_OC2M_Msk        (0x1007UL << TIM_CCMR1_OC2M_Pos)             /*!< 0x01007000 */

+#define TIM_CCMR1_OC2M            TIM_CCMR1_OC2M_Msk                           /*!<OC2M[2:0] bits (Output Compare 2 Mode) */

+#define TIM_CCMR1_OC2M_0          (0x0001UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00001000 */

+#define TIM_CCMR1_OC2M_1          (0x0002UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00002000 */

+#define TIM_CCMR1_OC2M_2          (0x0004UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x00004000 */

+#define TIM_CCMR1_OC2M_3          (0x1000UL << TIM_CCMR1_OC2M_Pos)              /*!< 0x01000000 */

+

+#define TIM_CCMR1_OC2CE_Pos       (15U)

+#define TIM_CCMR1_OC2CE_Msk       (0x1UL << TIM_CCMR1_OC2CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR1_OC2CE           TIM_CCMR1_OC2CE_Msk                          /*!<Output Compare 2 Clear Enable */

+

+/*----------------------------------------------------------------------------*/

+

+#define TIM_CCMR1_IC1PSC_Pos      (2U)

+#define TIM_CCMR1_IC1PSC_Msk      (0x3UL << TIM_CCMR1_IC1PSC_Pos)              /*!< 0x0000000C */

+#define TIM_CCMR1_IC1PSC          TIM_CCMR1_IC1PSC_Msk                         /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */

+#define TIM_CCMR1_IC1PSC_0        (0x1UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR1_IC1PSC_1        (0x2UL << TIM_CCMR1_IC1PSC_Pos)               /*!< 0x00000008 */

+

+#define TIM_CCMR1_IC1F_Pos        (4U)

+#define TIM_CCMR1_IC1F_Msk        (0xFUL << TIM_CCMR1_IC1F_Pos)                /*!< 0x000000F0 */

+#define TIM_CCMR1_IC1F            TIM_CCMR1_IC1F_Msk                           /*!<IC1F[3:0] bits (Input Capture 1 Filter) */

+#define TIM_CCMR1_IC1F_0          (0x1UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR1_IC1F_1          (0x2UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR1_IC1F_2          (0x4UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR1_IC1F_3          (0x8UL << TIM_CCMR1_IC1F_Pos)                 /*!< 0x00000080 */

+

+#define TIM_CCMR1_IC2PSC_Pos      (10U)

+#define TIM_CCMR1_IC2PSC_Msk      (0x3UL << TIM_CCMR1_IC2PSC_Pos)              /*!< 0x00000C00 */

+#define TIM_CCMR1_IC2PSC          TIM_CCMR1_IC2PSC_Msk                         /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */

+#define TIM_CCMR1_IC2PSC_0        (0x1UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR1_IC2PSC_1        (0x2UL << TIM_CCMR1_IC2PSC_Pos)               /*!< 0x00000800 */

+

+#define TIM_CCMR1_IC2F_Pos        (12U)

+#define TIM_CCMR1_IC2F_Msk        (0xFUL << TIM_CCMR1_IC2F_Pos)                /*!< 0x0000F000 */

+#define TIM_CCMR1_IC2F            TIM_CCMR1_IC2F_Msk                           /*!<IC2F[3:0] bits (Input Capture 2 Filter) */

+#define TIM_CCMR1_IC2F_0          (0x1UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR1_IC2F_1          (0x2UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR1_IC2F_2          (0x4UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR1_IC2F_3          (0x8UL << TIM_CCMR1_IC2F_Pos)                 /*!< 0x00008000 */

+

+/******************  Bit definition for TIM_CCMR2 register  *******************/

+#define TIM_CCMR2_CC3S_Pos        (0U)

+#define TIM_CCMR2_CC3S_Msk        (0x3UL << TIM_CCMR2_CC3S_Pos)                /*!< 0x00000003 */

+#define TIM_CCMR2_CC3S            TIM_CCMR2_CC3S_Msk                           /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */

+#define TIM_CCMR2_CC3S_0          (0x1UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000001 */

+#define TIM_CCMR2_CC3S_1          (0x2UL << TIM_CCMR2_CC3S_Pos)                 /*!< 0x00000002 */

+

+#define TIM_CCMR2_OC3FE_Pos       (2U)

+#define TIM_CCMR2_OC3FE_Msk       (0x1UL << TIM_CCMR2_OC3FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR2_OC3FE           TIM_CCMR2_OC3FE_Msk                          /*!<Output Compare 3 Fast enable */

+#define TIM_CCMR2_OC3PE_Pos       (3U)

+#define TIM_CCMR2_OC3PE_Msk       (0x1UL << TIM_CCMR2_OC3PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR2_OC3PE           TIM_CCMR2_OC3PE_Msk                          /*!<Output Compare 3 Preload enable */

+

+#define TIM_CCMR2_OC3M_Pos        (4U)

+#define TIM_CCMR2_OC3M_Msk        (0x7UL << TIM_CCMR2_OC3M_Pos)                /*!< 0x00000070 */

+#define TIM_CCMR2_OC3M            TIM_CCMR2_OC3M_Msk                           /*!<OC3M[2:0] bits (Output Compare 3 Mode) */

+#define TIM_CCMR2_OC3M_0          (0x1UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR2_OC3M_1          (0x2UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR2_OC3M_2          (0x4UL << TIM_CCMR2_OC3M_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR2_OC3M_3          (0x1000UL << TIM_CCMR2_OC3M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR2_OC3CE_Pos       (7U)

+#define TIM_CCMR2_OC3CE_Msk       (0x1UL << TIM_CCMR2_OC3CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR2_OC3CE           TIM_CCMR2_OC3CE_Msk                          /*!<Output Compare 3 Clear Enable */

+

+#define TIM_CCMR2_CC4S_Pos        (8U)

+#define TIM_CCMR2_CC4S_Msk        (0x3UL << TIM_CCMR2_CC4S_Pos)                /*!< 0x00000300 */

+#define TIM_CCMR2_CC4S            TIM_CCMR2_CC4S_Msk                           /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */

+#define TIM_CCMR2_CC4S_0          (0x1UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000100 */

+#define TIM_CCMR2_CC4S_1          (0x2UL << TIM_CCMR2_CC4S_Pos)                 /*!< 0x00000200 */

+

+#define TIM_CCMR2_OC4FE_Pos       (10U)

+#define TIM_CCMR2_OC4FE_Msk       (0x1UL << TIM_CCMR2_OC4FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR2_OC4FE           TIM_CCMR2_OC4FE_Msk                          /*!<Output Compare 4 Fast enable */

+#define TIM_CCMR2_OC4PE_Pos       (11U)

+#define TIM_CCMR2_OC4PE_Msk       (0x1UL << TIM_CCMR2_OC4PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR2_OC4PE           TIM_CCMR2_OC4PE_Msk                          /*!<Output Compare 4 Preload enable */

+

+#define TIM_CCMR2_OC4M_Pos        (12U)

+#define TIM_CCMR2_OC4M_Msk        (0x7UL << TIM_CCMR2_OC4M_Pos)                /*!< 0x00007000 */

+#define TIM_CCMR2_OC4M            TIM_CCMR2_OC4M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */

+#define TIM_CCMR2_OC4M_0          (0x1UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR2_OC4M_1          (0x2UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR2_OC4M_2          (0x4UL << TIM_CCMR2_OC4M_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR2_OC4M_3          (0x100UL << TIM_CCMR2_OC4M_Pos)               /*!< 0x00100000 */

+

+#define TIM_CCMR2_OC4CE_Pos       (15U)

+#define TIM_CCMR2_OC4CE_Msk       (0x1UL << TIM_CCMR2_OC4CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR2_OC4CE           TIM_CCMR2_OC4CE_Msk                          /*!<Output Compare 4 Clear Enable */

+

+/*----------------------------------------------------------------------------*/

+

+#define TIM_CCMR2_IC3PSC_Pos      (2U)

+#define TIM_CCMR2_IC3PSC_Msk      (0x3UL << TIM_CCMR2_IC3PSC_Pos)              /*!< 0x0000000C */

+#define TIM_CCMR2_IC3PSC          TIM_CCMR2_IC3PSC_Msk                         /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */

+#define TIM_CCMR2_IC3PSC_0        (0x1UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR2_IC3PSC_1        (0x2UL << TIM_CCMR2_IC3PSC_Pos)               /*!< 0x00000008 */

+

+#define TIM_CCMR2_IC3F_Pos        (4U)

+#define TIM_CCMR2_IC3F_Msk        (0xFUL << TIM_CCMR2_IC3F_Pos)                /*!< 0x000000F0 */

+#define TIM_CCMR2_IC3F            TIM_CCMR2_IC3F_Msk                           /*!<IC3F[3:0] bits (Input Capture 3 Filter) */

+#define TIM_CCMR2_IC3F_0          (0x1UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR2_IC3F_1          (0x2UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR2_IC3F_2          (0x4UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR2_IC3F_3          (0x8UL << TIM_CCMR2_IC3F_Pos)                 /*!< 0x00000080 */

+

+#define TIM_CCMR2_IC4PSC_Pos      (10U)

+#define TIM_CCMR2_IC4PSC_Msk      (0x3UL << TIM_CCMR2_IC4PSC_Pos)              /*!< 0x00000C00 */

+#define TIM_CCMR2_IC4PSC          TIM_CCMR2_IC4PSC_Msk                         /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */

+#define TIM_CCMR2_IC4PSC_0        (0x1UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR2_IC4PSC_1        (0x2UL << TIM_CCMR2_IC4PSC_Pos)               /*!< 0x00000800 */

+

+#define TIM_CCMR2_IC4F_Pos        (12U)

+#define TIM_CCMR2_IC4F_Msk        (0xFUL << TIM_CCMR2_IC4F_Pos)                /*!< 0x0000F000 */

+#define TIM_CCMR2_IC4F            TIM_CCMR2_IC4F_Msk                           /*!<IC4F[3:0] bits (Input Capture 4 Filter) */

+#define TIM_CCMR2_IC4F_0          (0x1UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR2_IC4F_1          (0x2UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR2_IC4F_2          (0x4UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR2_IC4F_3          (0x8UL << TIM_CCMR2_IC4F_Pos)                 /*!< 0x00008000 */

+

+/*******************  Bit definition for TIM_CCER register  *******************/

+#define TIM_CCER_CC1E_Pos         (0U)

+#define TIM_CCER_CC1E_Msk         (0x1UL << TIM_CCER_CC1E_Pos)                 /*!< 0x00000001 */

+#define TIM_CCER_CC1E             TIM_CCER_CC1E_Msk                            /*!<Capture/Compare 1 output enable */

+#define TIM_CCER_CC1P_Pos         (1U)

+#define TIM_CCER_CC1P_Msk         (0x1UL << TIM_CCER_CC1P_Pos)                 /*!< 0x00000002 */

+#define TIM_CCER_CC1P             TIM_CCER_CC1P_Msk                            /*!<Capture/Compare 1 output Polarity */

+#define TIM_CCER_CC1NE_Pos        (2U)

+#define TIM_CCER_CC1NE_Msk        (0x1UL << TIM_CCER_CC1NE_Pos)                /*!< 0x00000004 */

+#define TIM_CCER_CC1NE            TIM_CCER_CC1NE_Msk                           /*!<Capture/Compare 1 Complementary output enable */

+#define TIM_CCER_CC1NP_Pos        (3U)

+#define TIM_CCER_CC1NP_Msk        (0x1UL << TIM_CCER_CC1NP_Pos)                /*!< 0x00000008 */

+#define TIM_CCER_CC1NP            TIM_CCER_CC1NP_Msk                           /*!<Capture/Compare 1 Complementary output Polarity */

+#define TIM_CCER_CC2E_Pos         (4U)

+#define TIM_CCER_CC2E_Msk         (0x1UL << TIM_CCER_CC2E_Pos)                 /*!< 0x00000010 */

+#define TIM_CCER_CC2E             TIM_CCER_CC2E_Msk                            /*!<Capture/Compare 2 output enable */

+#define TIM_CCER_CC2P_Pos         (5U)

+#define TIM_CCER_CC2P_Msk         (0x1UL << TIM_CCER_CC2P_Pos)                 /*!< 0x00000020 */

+#define TIM_CCER_CC2P             TIM_CCER_CC2P_Msk                            /*!<Capture/Compare 2 output Polarity */

+#define TIM_CCER_CC2NE_Pos        (6U)

+#define TIM_CCER_CC2NE_Msk        (0x1UL << TIM_CCER_CC2NE_Pos)                /*!< 0x00000040 */

+#define TIM_CCER_CC2NE            TIM_CCER_CC2NE_Msk                           /*!<Capture/Compare 2 Complementary output enable */

+#define TIM_CCER_CC2NP_Pos        (7U)

+#define TIM_CCER_CC2NP_Msk        (0x1UL << TIM_CCER_CC2NP_Pos)                /*!< 0x00000080 */

+#define TIM_CCER_CC2NP            TIM_CCER_CC2NP_Msk                           /*!<Capture/Compare 2 Complementary output Polarity */

+#define TIM_CCER_CC3E_Pos         (8U)

+#define TIM_CCER_CC3E_Msk         (0x1UL << TIM_CCER_CC3E_Pos)                 /*!< 0x00000100 */

+#define TIM_CCER_CC3E             TIM_CCER_CC3E_Msk                            /*!<Capture/Compare 3 output enable */

+#define TIM_CCER_CC3P_Pos         (9U)

+#define TIM_CCER_CC3P_Msk         (0x1UL << TIM_CCER_CC3P_Pos)                 /*!< 0x00000200 */

+#define TIM_CCER_CC3P             TIM_CCER_CC3P_Msk                            /*!<Capture/Compare 3 output Polarity */

+#define TIM_CCER_CC3NE_Pos        (10U)

+#define TIM_CCER_CC3NE_Msk        (0x1UL << TIM_CCER_CC3NE_Pos)                /*!< 0x00000400 */

+#define TIM_CCER_CC3NE            TIM_CCER_CC3NE_Msk                           /*!<Capture/Compare 3 Complementary output enable */

+#define TIM_CCER_CC3NP_Pos        (11U)

+#define TIM_CCER_CC3NP_Msk        (0x1UL << TIM_CCER_CC3NP_Pos)                /*!< 0x00000800 */

+#define TIM_CCER_CC3NP            TIM_CCER_CC3NP_Msk                           /*!<Capture/Compare 3 Complementary output Polarity */

+#define TIM_CCER_CC4E_Pos         (12U)

+#define TIM_CCER_CC4E_Msk         (0x1UL << TIM_CCER_CC4E_Pos)                 /*!< 0x00001000 */

+#define TIM_CCER_CC4E             TIM_CCER_CC4E_Msk                            /*!<Capture/Compare 4 output enable */

+#define TIM_CCER_CC4P_Pos         (13U)

+#define TIM_CCER_CC4P_Msk         (0x1UL << TIM_CCER_CC4P_Pos)                 /*!< 0x00002000 */

+#define TIM_CCER_CC4P             TIM_CCER_CC4P_Msk                            /*!<Capture/Compare 4 output Polarity */

+#define TIM_CCER_CC4NP_Pos        (15U)

+#define TIM_CCER_CC4NP_Msk        (0x1UL << TIM_CCER_CC4NP_Pos)                /*!< 0x00008000 */

+#define TIM_CCER_CC4NP            TIM_CCER_CC4NP_Msk                           /*!<Capture/Compare 4 Complementary output Polarity */

+#define TIM_CCER_CC5E_Pos         (16U)

+#define TIM_CCER_CC5E_Msk         (0x1UL << TIM_CCER_CC5E_Pos)                 /*!< 0x00010000 */

+#define TIM_CCER_CC5E             TIM_CCER_CC5E_Msk                            /*!<Capture/Compare 5 output enable */

+#define TIM_CCER_CC5P_Pos         (17U)

+#define TIM_CCER_CC5P_Msk         (0x1UL << TIM_CCER_CC5P_Pos)                 /*!< 0x00020000 */

+#define TIM_CCER_CC5P             TIM_CCER_CC5P_Msk                            /*!<Capture/Compare 5 output Polarity */

+#define TIM_CCER_CC6E_Pos         (20U)

+#define TIM_CCER_CC6E_Msk         (0x1UL << TIM_CCER_CC6E_Pos)                 /*!< 0x00100000 */

+#define TIM_CCER_CC6E             TIM_CCER_CC6E_Msk                            /*!<Capture/Compare 6 output enable */

+#define TIM_CCER_CC6P_Pos         (21U)

+#define TIM_CCER_CC6P_Msk         (0x1UL << TIM_CCER_CC6P_Pos)                 /*!< 0x00200000 */

+#define TIM_CCER_CC6P             TIM_CCER_CC6P_Msk                            /*!<Capture/Compare 6 output Polarity */

+/*******************  Bit definition for TIM_CNT register  ********************/

+#define TIM_CNT_CNT_Pos           (0U)

+#define TIM_CNT_CNT_Msk           (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)            /*!< 0xFFFFFFFF */

+#define TIM_CNT_CNT               TIM_CNT_CNT_Msk                              /*!<Counter Value */

+#define TIM_CNT_UIFCPY_Pos        (31U)

+#define TIM_CNT_UIFCPY_Msk        (0x1UL << TIM_CNT_UIFCPY_Pos)                /*!< 0x80000000 */

+#define TIM_CNT_UIFCPY            TIM_CNT_UIFCPY_Msk                           /*!<Update interrupt flag copy */

+/*******************  Bit definition for TIM_PSC register  ********************/

+#define TIM_PSC_PSC_Pos           (0U)

+#define TIM_PSC_PSC_Msk           (0xFFFFUL << TIM_PSC_PSC_Pos)                /*!< 0x0000FFFF */

+#define TIM_PSC_PSC               TIM_PSC_PSC_Msk                              /*!<Prescaler Value */

+

+/*******************  Bit definition for TIM_ARR register  ********************/

+#define TIM_ARR_ARR_Pos           (0U)

+#define TIM_ARR_ARR_Msk           (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)            /*!< 0xFFFFFFFF */

+#define TIM_ARR_ARR               TIM_ARR_ARR_Msk                              /*!<actual auto-reload Value */

+

+/*******************  Bit definition for TIM_RCR register  ********************/

+#define TIM_RCR_REP_Pos           (0U)

+#define TIM_RCR_REP_Msk           (0xFFUL << TIM_RCR_REP_Pos)                  /*!< 0x000000FF */

+#define TIM_RCR_REP               TIM_RCR_REP_Msk                              /*!<Repetition Counter Value */

+

+/*******************  Bit definition for TIM_CCR1 register  *******************/

+#define TIM_CCR1_CCR1_Pos         (0U)

+#define TIM_CCR1_CCR1_Msk         (0xFFFFUL << TIM_CCR1_CCR1_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR1_CCR1             TIM_CCR1_CCR1_Msk                            /*!<Capture/Compare 1 Value */

+

+/*******************  Bit definition for TIM_CCR2 register  *******************/

+#define TIM_CCR2_CCR2_Pos         (0U)

+#define TIM_CCR2_CCR2_Msk         (0xFFFFUL << TIM_CCR2_CCR2_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR2_CCR2             TIM_CCR2_CCR2_Msk                            /*!<Capture/Compare 2 Value */

+

+/*******************  Bit definition for TIM_CCR3 register  *******************/

+#define TIM_CCR3_CCR3_Pos         (0U)

+#define TIM_CCR3_CCR3_Msk         (0xFFFFUL << TIM_CCR3_CCR3_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR3_CCR3             TIM_CCR3_CCR3_Msk                            /*!<Capture/Compare 3 Value */

+

+/*******************  Bit definition for TIM_CCR4 register  *******************/

+#define TIM_CCR4_CCR4_Pos         (0U)

+#define TIM_CCR4_CCR4_Msk         (0xFFFFUL << TIM_CCR4_CCR4_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR4_CCR4             TIM_CCR4_CCR4_Msk                            /*!<Capture/Compare 4 Value */

+

+/*******************  Bit definition for TIM_CCR5 register  *******************/

+#define TIM_CCR5_CCR5_Pos         (0U)

+#define TIM_CCR5_CCR5_Msk         (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos)          /*!< 0xFFFFFFFF */

+#define TIM_CCR5_CCR5             TIM_CCR5_CCR5_Msk                            /*!<Capture/Compare 5 Value */

+#define TIM_CCR5_GC5C1_Pos        (29U)

+#define TIM_CCR5_GC5C1_Msk        (0x1UL << TIM_CCR5_GC5C1_Pos)                /*!< 0x20000000 */

+#define TIM_CCR5_GC5C1            TIM_CCR5_GC5C1_Msk                           /*!<Group Channel 5 and Channel 1 */

+#define TIM_CCR5_GC5C2_Pos        (30U)

+#define TIM_CCR5_GC5C2_Msk        (0x1UL << TIM_CCR5_GC5C2_Pos)                /*!< 0x40000000 */

+#define TIM_CCR5_GC5C2            TIM_CCR5_GC5C2_Msk                           /*!<Group Channel 5 and Channel 2 */

+#define TIM_CCR5_GC5C3_Pos        (31U)

+#define TIM_CCR5_GC5C3_Msk        (0x1UL << TIM_CCR5_GC5C3_Pos)                /*!< 0x80000000 */

+#define TIM_CCR5_GC5C3            TIM_CCR5_GC5C3_Msk                           /*!<Group Channel 5 and Channel 3 */

+

+/*******************  Bit definition for TIM_CCR6 register  *******************/

+#define TIM_CCR6_CCR6_Pos         (0U)

+#define TIM_CCR6_CCR6_Msk         (0xFFFFUL << TIM_CCR6_CCR6_Pos)              /*!< 0x0000FFFF */

+#define TIM_CCR6_CCR6             TIM_CCR6_CCR6_Msk                            /*!<Capture/Compare 6 Value */

+

+/*******************  Bit definition for TIM_BDTR register  *******************/

+#define TIM_BDTR_DTG_Pos          (0U)

+#define TIM_BDTR_DTG_Msk          (0xFFUL << TIM_BDTR_DTG_Pos)                 /*!< 0x000000FF */

+#define TIM_BDTR_DTG              TIM_BDTR_DTG_Msk                             /*!<DTG[0:7] bits (Dead-Time Generator set-up) */

+#define TIM_BDTR_DTG_0            (0x01UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000001 */

+#define TIM_BDTR_DTG_1            (0x02UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000002 */

+#define TIM_BDTR_DTG_2            (0x04UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000004 */

+#define TIM_BDTR_DTG_3            (0x08UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000008 */

+#define TIM_BDTR_DTG_4            (0x10UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000010 */

+#define TIM_BDTR_DTG_5            (0x20UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000020 */

+#define TIM_BDTR_DTG_6            (0x40UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000040 */

+#define TIM_BDTR_DTG_7            (0x80UL << TIM_BDTR_DTG_Pos)                  /*!< 0x00000080 */

+

+#define TIM_BDTR_LOCK_Pos         (8U)

+#define TIM_BDTR_LOCK_Msk         (0x3UL << TIM_BDTR_LOCK_Pos)                 /*!< 0x00000300 */

+#define TIM_BDTR_LOCK             TIM_BDTR_LOCK_Msk                            /*!<LOCK[1:0] bits (Lock Configuration) */

+#define TIM_BDTR_LOCK_0           (0x1UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000100 */

+#define TIM_BDTR_LOCK_1           (0x2UL << TIM_BDTR_LOCK_Pos)                  /*!< 0x00000200 */

+

+#define TIM_BDTR_OSSI_Pos         (10U)

+#define TIM_BDTR_OSSI_Msk         (0x1UL << TIM_BDTR_OSSI_Pos)                 /*!< 0x00000400 */

+#define TIM_BDTR_OSSI             TIM_BDTR_OSSI_Msk                            /*!<Off-State Selection for Idle mode */

+#define TIM_BDTR_OSSR_Pos         (11U)

+#define TIM_BDTR_OSSR_Msk         (0x1UL << TIM_BDTR_OSSR_Pos)                 /*!< 0x00000800 */

+#define TIM_BDTR_OSSR             TIM_BDTR_OSSR_Msk                            /*!<Off-State Selection for Run mode */

+#define TIM_BDTR_BKE_Pos          (12U)

+#define TIM_BDTR_BKE_Msk          (0x1UL << TIM_BDTR_BKE_Pos)                  /*!< 0x00001000 */

+#define TIM_BDTR_BKE              TIM_BDTR_BKE_Msk                             /*!<Break enable for Break1 */

+#define TIM_BDTR_BKP_Pos          (13U)

+#define TIM_BDTR_BKP_Msk          (0x1UL << TIM_BDTR_BKP_Pos)                  /*!< 0x00002000 */

+#define TIM_BDTR_BKP              TIM_BDTR_BKP_Msk                             /*!<Break Polarity for Break1 */

+#define TIM_BDTR_AOE_Pos          (14U)

+#define TIM_BDTR_AOE_Msk          (0x1UL << TIM_BDTR_AOE_Pos)                  /*!< 0x00004000 */

+#define TIM_BDTR_AOE              TIM_BDTR_AOE_Msk                             /*!<Automatic Output enable */

+#define TIM_BDTR_MOE_Pos          (15U)

+#define TIM_BDTR_MOE_Msk          (0x1UL << TIM_BDTR_MOE_Pos)                  /*!< 0x00008000 */

+#define TIM_BDTR_MOE              TIM_BDTR_MOE_Msk                             /*!<Main Output enable */

+

+#define TIM_BDTR_BKF_Pos          (16U)

+#define TIM_BDTR_BKF_Msk          (0xFUL << TIM_BDTR_BKF_Pos)                  /*!< 0x000F0000 */

+#define TIM_BDTR_BKF              TIM_BDTR_BKF_Msk                             /*!<Break Filter for Break1 */

+#define TIM_BDTR_BK2F_Pos         (20U)

+#define TIM_BDTR_BK2F_Msk         (0xFUL << TIM_BDTR_BK2F_Pos)                 /*!< 0x00F00000 */

+#define TIM_BDTR_BK2F             TIM_BDTR_BK2F_Msk                            /*!<Break Filter for Break2 */

+

+#define TIM_BDTR_BK2E_Pos         (24U)

+#define TIM_BDTR_BK2E_Msk         (0x1UL << TIM_BDTR_BK2E_Pos)                 /*!< 0x01000000 */

+#define TIM_BDTR_BK2E             TIM_BDTR_BK2E_Msk                            /*!<Break enable for Break2 */

+#define TIM_BDTR_BK2P_Pos         (25U)

+#define TIM_BDTR_BK2P_Msk         (0x1UL << TIM_BDTR_BK2P_Pos)                 /*!< 0x02000000 */

+#define TIM_BDTR_BK2P             TIM_BDTR_BK2P_Msk                            /*!<Break Polarity for Break2 */

+

+/*******************  Bit definition for TIM_DCR register  ********************/

+#define TIM_DCR_DBA_Pos           (0U)

+#define TIM_DCR_DBA_Msk           (0x1FUL << TIM_DCR_DBA_Pos)                  /*!< 0x0000001F */

+#define TIM_DCR_DBA               TIM_DCR_DBA_Msk                              /*!<DBA[4:0] bits (DMA Base Address) */

+#define TIM_DCR_DBA_0             (0x01UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000001 */

+#define TIM_DCR_DBA_1             (0x02UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000002 */

+#define TIM_DCR_DBA_2             (0x04UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000004 */

+#define TIM_DCR_DBA_3             (0x08UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000008 */

+#define TIM_DCR_DBA_4             (0x10UL << TIM_DCR_DBA_Pos)                   /*!< 0x00000010 */

+

+#define TIM_DCR_DBL_Pos           (8U)

+#define TIM_DCR_DBL_Msk           (0x1FUL << TIM_DCR_DBL_Pos)                  /*!< 0x00001F00 */

+#define TIM_DCR_DBL               TIM_DCR_DBL_Msk                              /*!<DBL[4:0] bits (DMA Burst Length) */

+#define TIM_DCR_DBL_0             (0x01UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000100 */

+#define TIM_DCR_DBL_1             (0x02UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000200 */

+#define TIM_DCR_DBL_2             (0x04UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000400 */

+#define TIM_DCR_DBL_3             (0x08UL << TIM_DCR_DBL_Pos)                   /*!< 0x00000800 */

+#define TIM_DCR_DBL_4             (0x10UL << TIM_DCR_DBL_Pos)                   /*!< 0x00001000 */

+

+/*******************  Bit definition for TIM_DMAR register  *******************/

+#define TIM_DMAR_DMAB_Pos         (0U)

+#define TIM_DMAR_DMAB_Msk         (0xFFFFUL << TIM_DMAR_DMAB_Pos)              /*!< 0x0000FFFF */

+#define TIM_DMAR_DMAB             TIM_DMAR_DMAB_Msk                            /*!<DMA register for burst accesses */

+

+/******************  Bit definition for TIM_CCMR3 register  *******************/

+#define TIM_CCMR3_OC5FE_Pos       (2U)

+#define TIM_CCMR3_OC5FE_Msk       (0x1UL << TIM_CCMR3_OC5FE_Pos)               /*!< 0x00000004 */

+#define TIM_CCMR3_OC5FE           TIM_CCMR3_OC5FE_Msk                          /*!<Output Compare 5 Fast enable */

+#define TIM_CCMR3_OC5PE_Pos       (3U)

+#define TIM_CCMR3_OC5PE_Msk       (0x1UL << TIM_CCMR3_OC5PE_Pos)               /*!< 0x00000008 */

+#define TIM_CCMR3_OC5PE           TIM_CCMR3_OC5PE_Msk                          /*!<Output Compare 5 Preload enable */

+

+#define TIM_CCMR3_OC5M_Pos        (4U)

+#define TIM_CCMR3_OC5M_Msk        (0x7UL << TIM_CCMR3_OC5M_Pos)                /*!< 0x00000070 */

+#define TIM_CCMR3_OC5M            TIM_CCMR3_OC5M_Msk                           /*!<OC5M[2:0] bits (Output Compare 5 Mode) */

+#define TIM_CCMR3_OC5M_0          (0x1UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000010 */

+#define TIM_CCMR3_OC5M_1          (0x2UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000020 */

+#define TIM_CCMR3_OC5M_2          (0x4UL << TIM_CCMR3_OC5M_Pos)                 /*!< 0x00000040 */

+#define TIM_CCMR3_OC5M_3          (0x1000UL << TIM_CCMR3_OC5M_Pos)              /*!< 0x00010000 */

+

+#define TIM_CCMR3_OC5CE_Pos       (7U)

+#define TIM_CCMR3_OC5CE_Msk       (0x1UL << TIM_CCMR3_OC5CE_Pos)               /*!< 0x00000080 */

+#define TIM_CCMR3_OC5CE           TIM_CCMR3_OC5CE_Msk                          /*!<Output Compare 5 Clear Enable */

+

+#define TIM_CCMR3_OC6FE_Pos       (10U)

+#define TIM_CCMR3_OC6FE_Msk       (0x1UL << TIM_CCMR3_OC6FE_Pos)               /*!< 0x00000400 */

+#define TIM_CCMR3_OC6FE           TIM_CCMR3_OC6FE_Msk                          /*!<Output Compare 4 Fast enable */

+#define TIM_CCMR3_OC6PE_Pos       (11U)

+#define TIM_CCMR3_OC6PE_Msk       (0x1UL << TIM_CCMR3_OC6PE_Pos)               /*!< 0x00000800 */

+#define TIM_CCMR3_OC6PE           TIM_CCMR3_OC6PE_Msk                          /*!<Output Compare 4 Preload enable */

+

+#define TIM_CCMR3_OC6M_Pos        (12U)

+#define TIM_CCMR3_OC6M_Msk        (0x7UL << TIM_CCMR3_OC6M_Pos)                /*!< 0x00007000 */

+#define TIM_CCMR3_OC6M            TIM_CCMR3_OC6M_Msk                           /*!<OC4M[2:0] bits (Output Compare 4 Mode) */

+#define TIM_CCMR3_OC6M_0          (0x1UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00001000 */

+#define TIM_CCMR3_OC6M_1          (0x2UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00002000 */

+#define TIM_CCMR3_OC6M_2          (0x4UL << TIM_CCMR3_OC6M_Pos)                 /*!< 0x00004000 */

+#define TIM_CCMR3_OC6M_3          (0x100UL << TIM_CCMR3_OC6M_Pos)               /*!< 0x00100000 */

+

+#define TIM_CCMR3_OC6CE_Pos       (15U)

+#define TIM_CCMR3_OC6CE_Msk       (0x1UL << TIM_CCMR3_OC6CE_Pos)               /*!< 0x00008000 */

+#define TIM_CCMR3_OC6CE           TIM_CCMR3_OC6CE_Msk                          /*!<Output Compare 4 Clear Enable */

+/*******************  Bit definition for TIM1_AF1 register  *********************/

+#define TIM1_AF1_BKINE_Pos        (0U)

+#define TIM1_AF1_BKINE_Msk        (0x1UL << TIM1_AF1_BKINE_Pos)                /*!< 0x00000001 */

+#define TIM1_AF1_BKINE            TIM1_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */

+#define TIM1_AF1_BKCMP1E_Pos      (1U)

+#define TIM1_AF1_BKCMP1E_Msk      (0x1UL << TIM1_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */

+#define TIM1_AF1_BKCMP1E          TIM1_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM1_AF1_BKCMP2E_Pos      (2U)

+#define TIM1_AF1_BKCMP2E_Msk      (0x1UL << TIM1_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */

+#define TIM1_AF1_BKCMP2E          TIM1_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit */

+#define TIM1_AF1_BKDF1BK0E_Pos    (8U)

+#define TIM1_AF1_BKDF1BK0E_Msk    (0x1UL << TIM1_AF1_BKDF1BK0E_Pos)            /*!< 0x00000100 */

+#define TIM1_AF1_BKDF1BK0E        TIM1_AF1_BKDF1BK0E_Msk                       /*!<BKDF1BK0E Break input DFSDM Break 0 */

+#define TIM1_AF1_BKINP_Pos        (9U)

+#define TIM1_AF1_BKINP_Msk        (0x1UL << TIM1_AF1_BKINP_Pos)                /*!< 0x00000200 */

+#define TIM1_AF1_BKINP            TIM1_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */

+#define TIM1_AF1_BKCMP1P_Pos      (10U)

+#define TIM1_AF1_BKCMP1P_Msk      (0x1UL << TIM1_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */

+#define TIM1_AF1_BKCMP1P          TIM1_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM1_AF1_BKCMP2P_Pos      (11U)

+#define TIM1_AF1_BKCMP2P_Msk      (0x1UL << TIM1_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */

+#define TIM1_AF1_BKCMP2P          TIM1_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */

+

+#define TIM1_AF1_ETRSEL_Pos       (14U)

+#define TIM1_AF1_ETRSEL_Msk       (0xFUL << TIM1_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */

+#define TIM1_AF1_ETRSEL           TIM1_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */

+#define TIM1_AF1_ETRSEL_0         (0x1UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00004000 */

+#define TIM1_AF1_ETRSEL_1         (0x2UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00008000 */

+#define TIM1_AF1_ETRSEL_2         (0x4UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00010000 */

+#define TIM1_AF1_ETRSEL_3         (0x8UL << TIM1_AF1_ETRSEL_Pos)                /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM1_AF2 register  *********************/

+#define TIM1_AF2_BK2INE_Pos       (0U)

+#define TIM1_AF2_BK2INE_Msk       (0x1UL << TIM1_AF2_BK2INE_Pos)               /*!< 0x00000001 */

+#define TIM1_AF2_BK2INE           TIM1_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */

+#define TIM1_AF2_BK2CMP1E_Pos     (1U)

+#define TIM1_AF2_BK2CMP1E_Msk     (0x1UL << TIM1_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */

+#define TIM1_AF2_BK2CMP1E         TIM1_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */

+#define TIM1_AF2_BK2CMP2E_Pos     (2U)

+#define TIM1_AF2_BK2CMP2E_Msk     (0x1UL << TIM1_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */

+#define TIM1_AF2_BK2CMP2E         TIM1_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */

+#define TIM1_AF2_BK2DFBK1E_Pos    (8U)

+#define TIM1_AF2_BK2DFBK1E_Msk    (0x1UL << TIM1_AF2_BK2DFBK1E_Pos)            /*!< 0x00000100 */

+#define TIM1_AF2_BK2DFBK1E        TIM1_AF2_BK2DFBK1E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 1 */

+#define TIM1_AF2_BK2INP_Pos       (9U)

+#define TIM1_AF2_BK2INP_Msk       (0x1UL << TIM1_AF2_BK2INP_Pos)               /*!< 0x00000200 */

+#define TIM1_AF2_BK2INP           TIM1_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */

+#define TIM1_AF2_BK2CMP1P_Pos     (10U)

+#define TIM1_AF2_BK2CMP1P_Msk     (0x1UL << TIM1_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */

+#define TIM1_AF2_BK2CMP1P         TIM1_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */

+#define TIM1_AF2_BK2CMP2P_Pos     (11U)

+#define TIM1_AF2_BK2CMP2P_Msk     (0x1UL << TIM1_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */

+#define TIM1_AF2_BK2CMP2P         TIM1_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */

+

+/*******************  Bit definition for TIM_TISEL register  *********************/

+#define TIM_TISEL_TI1SEL_Pos      (0U)

+#define TIM_TISEL_TI1SEL_Msk      (0xFUL << TIM_TISEL_TI1SEL_Pos)              /*!< 0x0000000F */

+#define TIM_TISEL_TI1SEL          TIM_TISEL_TI1SEL_Msk                         /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/

+#define TIM_TISEL_TI1SEL_0        (0x1UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000001 */

+#define TIM_TISEL_TI1SEL_1        (0x2UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000002 */

+#define TIM_TISEL_TI1SEL_2        (0x4UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000004 */

+#define TIM_TISEL_TI1SEL_3        (0x8UL << TIM_TISEL_TI1SEL_Pos)               /*!< 0x00000008 */

+

+#define TIM_TISEL_TI2SEL_Pos      (8U)

+#define TIM_TISEL_TI2SEL_Msk      (0xFUL << TIM_TISEL_TI2SEL_Pos)              /*!< 0x00000F00 */

+#define TIM_TISEL_TI2SEL          TIM_TISEL_TI2SEL_Msk                         /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/

+#define TIM_TISEL_TI2SEL_0        (0x1UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000100 */

+#define TIM_TISEL_TI2SEL_1        (0x2UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000200 */

+#define TIM_TISEL_TI2SEL_2        (0x4UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000400 */

+#define TIM_TISEL_TI2SEL_3        (0x8UL << TIM_TISEL_TI2SEL_Pos)               /*!< 0x00000800 */

+

+#define TIM_TISEL_TI3SEL_Pos      (16U)

+#define TIM_TISEL_TI3SEL_Msk      (0xFUL << TIM_TISEL_TI3SEL_Pos)              /*!< 0x000F0000 */

+#define TIM_TISEL_TI3SEL          TIM_TISEL_TI3SEL_Msk                         /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/

+#define TIM_TISEL_TI3SEL_0        (0x1UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00010000 */

+#define TIM_TISEL_TI3SEL_1        (0x2UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00020000 */

+#define TIM_TISEL_TI3SEL_2        (0x4UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00040000 */

+#define TIM_TISEL_TI3SEL_3        (0x8UL << TIM_TISEL_TI3SEL_Pos)               /*!< 0x00080000 */

+

+#define TIM_TISEL_TI4SEL_Pos      (24U)

+#define TIM_TISEL_TI4SEL_Msk      (0xFUL << TIM_TISEL_TI4SEL_Pos)              /*!< 0x0F000000 */

+#define TIM_TISEL_TI4SEL          TIM_TISEL_TI4SEL_Msk                         /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/

+#define TIM_TISEL_TI4SEL_0        (0x1UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x01000000 */

+#define TIM_TISEL_TI4SEL_1        (0x2UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x02000000 */

+#define TIM_TISEL_TI4SEL_2        (0x4UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x04000000 */

+#define TIM_TISEL_TI4SEL_3        (0x8UL << TIM_TISEL_TI4SEL_Pos)               /*!< 0x08000000 */

+

+/*******************  Bit definition for TIM8_AF1 register  *********************/

+#define TIM8_AF1_BKINE_Pos        (0U)

+#define TIM8_AF1_BKINE_Msk        (0x1UL << TIM8_AF1_BKINE_Pos)                /*!< 0x00000001 */

+#define TIM8_AF1_BKINE            TIM8_AF1_BKINE_Msk                           /*!<BKINE Break input enable bit */

+#define TIM8_AF1_BKCMP1E_Pos      (1U)

+#define TIM8_AF1_BKCMP1E_Msk      (0x1UL << TIM8_AF1_BKCMP1E_Pos)              /*!< 0x00000002 */

+#define TIM8_AF1_BKCMP1E          TIM8_AF1_BKCMP1E_Msk                         /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM8_AF1_BKCMP2E_Pos      (2U)

+#define TIM8_AF1_BKCMP2E_Msk      (0x1UL << TIM8_AF1_BKCMP2E_Pos)              /*!< 0x00000004 */

+#define TIM8_AF1_BKCMP2E          TIM8_AF1_BKCMP2E_Msk                         /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM8_AF1_BKDFBK2E_Pos     (8U)

+#define TIM8_AF1_BKDFBK2E_Msk     (0x1UL << TIM8_AF1_BKDFBK2E_Pos)             /*!< 0x00000100 */

+#define TIM8_AF1_BKDFBK2E         TIM8_AF1_BKDFBK2E_Msk                        /*!<BKDFBK2E Break input DFSDM Break 2 */

+#define TIM8_AF1_BKINP_Pos        (9U)

+#define TIM8_AF1_BKINP_Msk        (0x1UL << TIM8_AF1_BKINP_Pos)                /*!< 0x00000200 */

+#define TIM8_AF1_BKINP            TIM8_AF1_BKINP_Msk                           /*!<BRKINP Break input polarity */

+#define TIM8_AF1_BKCMP1P_Pos      (10U)

+#define TIM8_AF1_BKCMP1P_Msk      (0x1UL << TIM8_AF1_BKCMP1P_Pos)              /*!< 0x00000400 */

+#define TIM8_AF1_BKCMP1P          TIM8_AF1_BKCMP1P_Msk                         /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM8_AF1_BKCMP2P_Pos      (11U)

+#define TIM8_AF1_BKCMP2P_Msk      (0x1UL << TIM8_AF1_BKCMP2P_Pos)              /*!< 0x00000800 */

+#define TIM8_AF1_BKCMP2P          TIM8_AF1_BKCMP2P_Msk                         /*!<BKCMP2P Break COMP2 input polarity */

+

+#define TIM8_AF1_ETRSEL_Pos       (14U)

+#define TIM8_AF1_ETRSEL_Msk       (0xFUL << TIM8_AF1_ETRSEL_Pos)               /*!< 0x0003C000 */

+#define TIM8_AF1_ETRSEL           TIM8_AF1_ETRSEL_Msk                          /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */

+#define TIM8_AF1_ETRSEL_0         (0x1UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00004000 */

+#define TIM8_AF1_ETRSEL_1         (0x2UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00008000 */

+#define TIM8_AF1_ETRSEL_2         (0x4UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00010000 */

+#define TIM8_AF1_ETRSEL_3         (0x8UL << TIM8_AF1_ETRSEL_Pos)                /*!< 0x00020000 */

+/*******************  Bit definition for TIM8_AF2 register  *********************/

+#define TIM8_AF2_BK2INE_Pos       (0U)

+#define TIM8_AF2_BK2INE_Msk       (0x1UL << TIM8_AF2_BK2INE_Pos)               /*!< 0x00000001 */

+#define TIM8_AF2_BK2INE           TIM8_AF2_BK2INE_Msk                          /*!<BK2INE Break input 2 enable bit */

+#define TIM8_AF2_BK2CMP1E_Pos     (1U)

+#define TIM8_AF2_BK2CMP1E_Msk     (0x1UL << TIM8_AF2_BK2CMP1E_Pos)             /*!< 0x00000002 */

+#define TIM8_AF2_BK2CMP1E         TIM8_AF2_BK2CMP1E_Msk                        /*!<BK2CMP1E Break2 Compare1 Enable bit */

+#define TIM8_AF2_BK2CMP2E_Pos     (2U)

+#define TIM8_AF2_BK2CMP2E_Msk     (0x1UL << TIM8_AF2_BK2CMP2E_Pos)             /*!< 0x00000004 */

+#define TIM8_AF2_BK2CMP2E         TIM8_AF2_BK2CMP2E_Msk                        /*!<BK2CMP1E Break2 Compare2 Enable bit  */

+#define TIM8_AF2_BK2DFBK3E_Pos    (8U)

+#define TIM8_AF2_BK2DFBK3E_Msk    (0x1UL << TIM8_AF2_BK2DFBK3E_Pos)            /*!< 0x00000100 */

+#define TIM8_AF2_BK2DFBK3E        TIM8_AF2_BK2DFBK3E_Msk                       /*!<BK2DFBK1E Break input2 DFSDM Break 3 */

+#define TIM8_AF2_BK2INP_Pos       (9U)

+#define TIM8_AF2_BK2INP_Msk       (0x1UL << TIM8_AF2_BK2INP_Pos)               /*!< 0x00000200 */

+#define TIM8_AF2_BK2INP           TIM8_AF2_BK2INP_Msk                          /*!<BRKINP Break2 input polarity */

+#define TIM8_AF2_BK2CMP1P_Pos     (10U)

+#define TIM8_AF2_BK2CMP1P_Msk     (0x1UL << TIM8_AF2_BK2CMP1P_Pos)             /*!< 0x00000400 */

+#define TIM8_AF2_BK2CMP1P         TIM8_AF2_BK2CMP1P_Msk                        /*!<BKCMP1P Break2 COMP1 input polarity */

+#define TIM8_AF2_BK2CMP2P_Pos     (11U)

+#define TIM8_AF2_BK2CMP2P_Msk     (0x1UL << TIM8_AF2_BK2CMP2P_Pos)             /*!< 0x00000800 */

+#define TIM8_AF2_BK2CMP2P         TIM8_AF2_BK2CMP2P_Msk                        /*!<BKCMP2P Break2 COMP2 input polarity */

+

+/*******************  Bit definition for TIM2_AF1 register  *********************/

+#define TIM2_AF1_ETRSEL_Pos      (14U)

+#define TIM2_AF1_ETRSEL_Msk      (0xFUL << TIM2_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM2_AF1_ETRSEL          TIM2_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */

+#define TIM2_AF1_ETRSEL_0        (0x1UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM2_AF1_ETRSEL_1        (0x2UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM2_AF1_ETRSEL_2        (0x4UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM2_AF1_ETRSEL_3        (0x8UL << TIM2_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM3_AF1 register  *********************/

+#define TIM3_AF1_ETRSEL_Pos      (14U)

+#define TIM3_AF1_ETRSEL_Msk      (0xFUL << TIM3_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM3_AF1_ETRSEL          TIM3_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */

+#define TIM3_AF1_ETRSEL_0        (0x1UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM3_AF1_ETRSEL_1        (0x2UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM3_AF1_ETRSEL_2        (0x4UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM3_AF1_ETRSEL_3        (0x8UL << TIM3_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM5_AF1 register  *********************/

+#define TIM5_AF1_ETRSEL_Pos      (14U)

+#define TIM5_AF1_ETRSEL_Msk      (0xFUL << TIM5_AF1_ETRSEL_Pos)                /*!< 0x0003C000 */

+#define TIM5_AF1_ETRSEL          TIM5_AF1_ETRSEL_Msk                           /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */

+#define TIM5_AF1_ETRSEL_0        (0x1UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00004000 */

+#define TIM5_AF1_ETRSEL_1        (0x2UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00008000 */

+#define TIM5_AF1_ETRSEL_2        (0x4UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00010000 */

+#define TIM5_AF1_ETRSEL_3        (0x8UL << TIM5_AF1_ETRSEL_Pos)                 /*!< 0x00020000 */

+

+/*******************  Bit definition for TIM15_AF1 register  *********************/

+#define TIM15_AF1_BKINE_Pos        (0U)

+#define TIM15_AF1_BKINE_Msk        (0x1UL << TIM15_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM15_AF1_BKINE            TIM15_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM15_AF1_BKCMP1E_Pos      (1U)

+#define TIM15_AF1_BKCMP1E_Msk      (0x1UL << TIM15_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM15_AF1_BKCMP1E          TIM15_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM15_AF1_BKCMP2E_Pos      (2U)

+#define TIM15_AF1_BKCMP2E_Msk      (0x1UL << TIM15_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM15_AF1_BKCMP2E          TIM15_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM15_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM15_AF1_BKDF1BK2E_Msk    (0x1UL << TIM15_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM15_AF1_BKDF1BK2E        TIM15_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[0] enable */

+#define TIM15_AF1_BKINP_Pos        (9U)

+#define TIM15_AF1_BKINP_Msk        (0x1UL << TIM15_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM15_AF1_BKINP            TIM15_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM15_AF1_BKCMP1P_Pos      (10U)

+#define TIM15_AF1_BKCMP1P_Msk      (0x1UL << TIM15_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM15_AF1_BKCMP1P          TIM15_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM15_AF1_BKCMP2P_Pos      (11U)

+#define TIM15_AF1_BKCMP2P_Msk      (0x1UL << TIM15_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM15_AF1_BKCMP2P          TIM15_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/*******************  Bit definition for TIM16_ register  *********************/

+#define TIM16_AF1_BKINE_Pos        (0U)

+#define TIM16_AF1_BKINE_Msk        (0x1UL << TIM16_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM16_AF1_BKINE            TIM16_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM16_AF1_BKCMP1E_Pos      (1U)

+#define TIM16_AF1_BKCMP1E_Msk      (0x1UL << TIM16_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM16_AF1_BKCMP1E          TIM16_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM16_AF1_BKCMP2E_Pos      (2U)

+#define TIM16_AF1_BKCMP2E_Msk      (0x1UL << TIM16_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM16_AF1_BKCMP2E          TIM16_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM16_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM16_AF1_BKDF1BK2E_Msk    (0x1UL << TIM16_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM16_AF1_BKDF1BK2E        TIM16_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[1] enable */

+#define TIM16_AF1_BKINP_Pos        (9U)

+#define TIM16_AF1_BKINP_Msk        (0x1UL << TIM16_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM16_AF1_BKINP            TIM16_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM16_AF1_BKCMP1P_Pos      (10U)

+#define TIM16_AF1_BKCMP1P_Msk      (0x1UL << TIM16_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM16_AF1_BKCMP1P          TIM16_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM16_AF1_BKCMP2P_Pos      (11U)

+#define TIM16_AF1_BKCMP2P_Msk      (0x1UL << TIM16_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM16_AF1_BKCMP2P          TIM16_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/*******************  Bit definition for TIM17_AF1 register  *********************/

+#define TIM17_AF1_BKINE_Pos        (0U)

+#define TIM17_AF1_BKINE_Msk        (0x1UL << TIM17_AF1_BKINE_Pos)              /*!< 0x00000001 */

+#define TIM17_AF1_BKINE            TIM17_AF1_BKINE_Msk                         /*!<BKINE Break input enable bit */

+#define TIM17_AF1_BKCMP1E_Pos      (1U)

+#define TIM17_AF1_BKCMP1E_Msk      (0x1UL << TIM17_AF1_BKCMP1E_Pos)            /*!< 0x00000002 */

+#define TIM17_AF1_BKCMP1E          TIM17_AF1_BKCMP1E_Msk                       /*!<BKCMP1E Break Compare1 Enable bit */

+#define TIM17_AF1_BKCMP2E_Pos      (2U)

+#define TIM17_AF1_BKCMP2E_Msk      (0x1UL << TIM17_AF1_BKCMP2E_Pos)            /*!< 0x00000004 */

+#define TIM17_AF1_BKCMP2E          TIM17_AF1_BKCMP2E_Msk                       /*!<BKCMP1E Break Compare2 Enable bit  */

+#define TIM17_AF1_BKDF1BK2E_Pos    (8U)

+#define TIM17_AF1_BKDF1BK2E_Msk    (0x1UL << TIM17_AF1_BKDF1BK2E_Pos)          /*!< 0x00000100 */

+#define TIM17_AF1_BKDF1BK2E        TIM17_AF1_BKDF1BK2E_Msk                     /*!<BRK dfsdm1_break[2] enable */

+#define TIM17_AF1_BKINP_Pos        (9U)

+#define TIM17_AF1_BKINP_Msk        (0x1UL << TIM17_AF1_BKINP_Pos)              /*!< 0x00000200 */

+#define TIM17_AF1_BKINP            TIM17_AF1_BKINP_Msk                         /*!<BRKINP Break input polarity */

+#define TIM17_AF1_BKCMP1P_Pos      (10U)

+#define TIM17_AF1_BKCMP1P_Msk      (0x1UL << TIM17_AF1_BKCMP1P_Pos)            /*!< 0x00000400 */

+#define TIM17_AF1_BKCMP1P          TIM17_AF1_BKCMP1P_Msk                       /*!<BKCMP1P Break COMP1 input polarity */

+#define TIM17_AF1_BKCMP2P_Pos      (11U)

+#define TIM17_AF1_BKCMP2P_Msk      (0x1UL << TIM17_AF1_BKCMP2P_Pos)            /*!< 0x00000800 */

+#define TIM17_AF1_BKCMP2P          TIM17_AF1_BKCMP2P_Msk                       /*!<BKCMP2P Break COMP2 input polarity */

+

+/******************************************************************************/

+/*                                                                            */

+/*                         Low Power Timer (LPTTIM)                           */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for LPTIM_ISR register  *******************/

+#define LPTIM_ISR_CMPM_Pos          (0U)

+#define LPTIM_ISR_CMPM_Msk          (0x1UL << LPTIM_ISR_CMPM_Pos)              /*!< 0x00000001 */

+#define LPTIM_ISR_CMPM              LPTIM_ISR_CMPM_Msk                         /*!< Compare match */

+#define LPTIM_ISR_ARRM_Pos          (1U)

+#define LPTIM_ISR_ARRM_Msk          (0x1UL << LPTIM_ISR_ARRM_Pos)              /*!< 0x00000002 */

+#define LPTIM_ISR_ARRM              LPTIM_ISR_ARRM_Msk                         /*!< Autoreload match */

+#define LPTIM_ISR_EXTTRIG_Pos       (2U)

+#define LPTIM_ISR_EXTTRIG_Msk       (0x1UL << LPTIM_ISR_EXTTRIG_Pos)           /*!< 0x00000004 */

+#define LPTIM_ISR_EXTTRIG           LPTIM_ISR_EXTTRIG_Msk                      /*!< External trigger edge event */

+#define LPTIM_ISR_CMPOK_Pos         (3U)

+#define LPTIM_ISR_CMPOK_Msk         (0x1UL << LPTIM_ISR_CMPOK_Pos)             /*!< 0x00000008 */

+#define LPTIM_ISR_CMPOK             LPTIM_ISR_CMPOK_Msk                        /*!< Compare register update OK */

+#define LPTIM_ISR_ARROK_Pos         (4U)

+#define LPTIM_ISR_ARROK_Msk         (0x1UL << LPTIM_ISR_ARROK_Pos)             /*!< 0x00000010 */

+#define LPTIM_ISR_ARROK             LPTIM_ISR_ARROK_Msk                        /*!< Autoreload register update OK */

+#define LPTIM_ISR_UP_Pos            (5U)

+#define LPTIM_ISR_UP_Msk            (0x1UL << LPTIM_ISR_UP_Pos)                /*!< 0x00000020 */

+#define LPTIM_ISR_UP                LPTIM_ISR_UP_Msk                           /*!< Counter direction change down to up */

+#define LPTIM_ISR_DOWN_Pos          (6U)

+#define LPTIM_ISR_DOWN_Msk          (0x1UL << LPTIM_ISR_DOWN_Pos)              /*!< 0x00000040 */

+#define LPTIM_ISR_DOWN              LPTIM_ISR_DOWN_Msk                         /*!< Counter direction change up to down */

+

+/******************  Bit definition for LPTIM_ICR register  *******************/

+#define LPTIM_ICR_CMPMCF_Pos        (0U)

+#define LPTIM_ICR_CMPMCF_Msk        (0x1UL << LPTIM_ICR_CMPMCF_Pos)            /*!< 0x00000001 */

+#define LPTIM_ICR_CMPMCF            LPTIM_ICR_CMPMCF_Msk                       /*!< Compare match Clear Flag */

+#define LPTIM_ICR_ARRMCF_Pos        (1U)

+#define LPTIM_ICR_ARRMCF_Msk        (0x1UL << LPTIM_ICR_ARRMCF_Pos)            /*!< 0x00000002 */

+#define LPTIM_ICR_ARRMCF            LPTIM_ICR_ARRMCF_Msk                       /*!< Autoreload match Clear Flag */

+#define LPTIM_ICR_EXTTRIGCF_Pos     (2U)

+#define LPTIM_ICR_EXTTRIGCF_Msk     (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos)         /*!< 0x00000004 */

+#define LPTIM_ICR_EXTTRIGCF         LPTIM_ICR_EXTTRIGCF_Msk                    /*!< External trigger edge event Clear Flag */

+#define LPTIM_ICR_CMPOKCF_Pos       (3U)

+#define LPTIM_ICR_CMPOKCF_Msk       (0x1UL << LPTIM_ICR_CMPOKCF_Pos)           /*!< 0x00000008 */

+#define LPTIM_ICR_CMPOKCF           LPTIM_ICR_CMPOKCF_Msk                      /*!< Compare register update OK Clear Flag */

+#define LPTIM_ICR_ARROKCF_Pos       (4U)

+#define LPTIM_ICR_ARROKCF_Msk       (0x1UL << LPTIM_ICR_ARROKCF_Pos)           /*!< 0x00000010 */

+#define LPTIM_ICR_ARROKCF           LPTIM_ICR_ARROKCF_Msk                      /*!< Autoreload register update OK Clear Flag */

+#define LPTIM_ICR_UPCF_Pos          (5U)

+#define LPTIM_ICR_UPCF_Msk          (0x1UL << LPTIM_ICR_UPCF_Pos)              /*!< 0x00000020 */

+#define LPTIM_ICR_UPCF              LPTIM_ICR_UPCF_Msk                         /*!< Counter direction change down to up Clear Flag */

+#define LPTIM_ICR_DOWNCF_Pos        (6U)

+#define LPTIM_ICR_DOWNCF_Msk        (0x1UL << LPTIM_ICR_DOWNCF_Pos)            /*!< 0x00000040 */

+#define LPTIM_ICR_DOWNCF            LPTIM_ICR_DOWNCF_Msk                       /*!< Counter direction change up to down Clear Flag */

+

+/******************  Bit definition for LPTIM_IER register ********************/

+#define LPTIM_IER_CMPMIE_Pos        (0U)

+#define LPTIM_IER_CMPMIE_Msk        (0x1UL << LPTIM_IER_CMPMIE_Pos)            /*!< 0x00000001 */

+#define LPTIM_IER_CMPMIE            LPTIM_IER_CMPMIE_Msk                       /*!< Compare match Interrupt Enable */

+#define LPTIM_IER_ARRMIE_Pos        (1U)

+#define LPTIM_IER_ARRMIE_Msk        (0x1UL << LPTIM_IER_ARRMIE_Pos)            /*!< 0x00000002 */

+#define LPTIM_IER_ARRMIE            LPTIM_IER_ARRMIE_Msk                       /*!< Autoreload match Interrupt Enable */

+#define LPTIM_IER_EXTTRIGIE_Pos     (2U)

+#define LPTIM_IER_EXTTRIGIE_Msk     (0x1UL << LPTIM_IER_EXTTRIGIE_Pos)         /*!< 0x00000004 */

+#define LPTIM_IER_EXTTRIGIE         LPTIM_IER_EXTTRIGIE_Msk                    /*!< External trigger edge event Interrupt Enable */

+#define LPTIM_IER_CMPOKIE_Pos       (3U)

+#define LPTIM_IER_CMPOKIE_Msk       (0x1UL << LPTIM_IER_CMPOKIE_Pos)           /*!< 0x00000008 */

+#define LPTIM_IER_CMPOKIE           LPTIM_IER_CMPOKIE_Msk                      /*!< Compare register update OK Interrupt Enable */

+#define LPTIM_IER_ARROKIE_Pos       (4U)

+#define LPTIM_IER_ARROKIE_Msk       (0x1UL << LPTIM_IER_ARROKIE_Pos)           /*!< 0x00000010 */

+#define LPTIM_IER_ARROKIE           LPTIM_IER_ARROKIE_Msk                      /*!< Autoreload register update OK Interrupt Enable */

+#define LPTIM_IER_UPIE_Pos          (5U)

+#define LPTIM_IER_UPIE_Msk          (0x1UL << LPTIM_IER_UPIE_Pos)              /*!< 0x00000020 */

+#define LPTIM_IER_UPIE              LPTIM_IER_UPIE_Msk                         /*!< Counter direction change down to up Interrupt Enable */

+#define LPTIM_IER_DOWNIE_Pos        (6U)

+#define LPTIM_IER_DOWNIE_Msk        (0x1UL << LPTIM_IER_DOWNIE_Pos)            /*!< 0x00000040 */

+#define LPTIM_IER_DOWNIE            LPTIM_IER_DOWNIE_Msk                       /*!< Counter direction change up to down Interrupt Enable */

+

+/******************  Bit definition for LPTIM_CFGR register *******************/

+#define LPTIM_CFGR_CKSEL_Pos        (0U)

+#define LPTIM_CFGR_CKSEL_Msk        (0x1UL << LPTIM_CFGR_CKSEL_Pos)            /*!< 0x00000001 */

+#define LPTIM_CFGR_CKSEL            LPTIM_CFGR_CKSEL_Msk                       /*!< Clock selector */

+

+#define LPTIM_CFGR_CKPOL_Pos        (1U)

+#define LPTIM_CFGR_CKPOL_Msk        (0x3UL << LPTIM_CFGR_CKPOL_Pos)            /*!< 0x00000006 */

+#define LPTIM_CFGR_CKPOL            LPTIM_CFGR_CKPOL_Msk                       /*!< CKPOL[1:0] bits (Clock polarity) */

+#define LPTIM_CFGR_CKPOL_0          (0x1UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000002 */

+#define LPTIM_CFGR_CKPOL_1          (0x2UL << LPTIM_CFGR_CKPOL_Pos)             /*!< 0x00000004 */

+

+#define LPTIM_CFGR_CKFLT_Pos        (3U)

+#define LPTIM_CFGR_CKFLT_Msk        (0x3UL << LPTIM_CFGR_CKFLT_Pos)            /*!< 0x00000018 */

+#define LPTIM_CFGR_CKFLT            LPTIM_CFGR_CKFLT_Msk                       /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */

+#define LPTIM_CFGR_CKFLT_0          (0x1UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000008 */

+#define LPTIM_CFGR_CKFLT_1          (0x2UL << LPTIM_CFGR_CKFLT_Pos)             /*!< 0x00000010 */

+

+#define LPTIM_CFGR_TRGFLT_Pos       (6U)

+#define LPTIM_CFGR_TRGFLT_Msk       (0x3UL << LPTIM_CFGR_TRGFLT_Pos)           /*!< 0x000000C0 */

+#define LPTIM_CFGR_TRGFLT           LPTIM_CFGR_TRGFLT_Msk                      /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */

+#define LPTIM_CFGR_TRGFLT_0         (0x1UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000040 */

+#define LPTIM_CFGR_TRGFLT_1         (0x2UL << LPTIM_CFGR_TRGFLT_Pos)            /*!< 0x00000080 */

+

+#define LPTIM_CFGR_PRESC_Pos        (9U)

+#define LPTIM_CFGR_PRESC_Msk        (0x7UL << LPTIM_CFGR_PRESC_Pos)            /*!< 0x00000E00 */

+#define LPTIM_CFGR_PRESC            LPTIM_CFGR_PRESC_Msk                       /*!< PRESC[2:0] bits (Clock prescaler) */

+#define LPTIM_CFGR_PRESC_0          (0x1UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000200 */

+#define LPTIM_CFGR_PRESC_1          (0x2UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000400 */

+#define LPTIM_CFGR_PRESC_2          (0x4UL << LPTIM_CFGR_PRESC_Pos)             /*!< 0x00000800 */

+

+#define LPTIM_CFGR_TRIGSEL_Pos      (13U)

+#define LPTIM_CFGR_TRIGSEL_Msk      (0x7UL << LPTIM_CFGR_TRIGSEL_Pos)          /*!< 0x0000E000 */

+#define LPTIM_CFGR_TRIGSEL          LPTIM_CFGR_TRIGSEL_Msk                     /*!< TRIGSEL[2:0]] bits (Trigger selector) */

+#define LPTIM_CFGR_TRIGSEL_0        (0x1UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00002000 */

+#define LPTIM_CFGR_TRIGSEL_1        (0x2UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00004000 */

+#define LPTIM_CFGR_TRIGSEL_2        (0x4UL << LPTIM_CFGR_TRIGSEL_Pos)           /*!< 0x00008000 */

+

+#define LPTIM_CFGR_TRIGEN_Pos       (17U)

+#define LPTIM_CFGR_TRIGEN_Msk       (0x3UL << LPTIM_CFGR_TRIGEN_Pos)           /*!< 0x00060000 */

+#define LPTIM_CFGR_TRIGEN           LPTIM_CFGR_TRIGEN_Msk                      /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */

+#define LPTIM_CFGR_TRIGEN_0         (0x1UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00020000 */

+#define LPTIM_CFGR_TRIGEN_1         (0x2UL << LPTIM_CFGR_TRIGEN_Pos)            /*!< 0x00040000 */

+

+#define LPTIM_CFGR_TIMOUT_Pos       (19U)

+#define LPTIM_CFGR_TIMOUT_Msk       (0x1UL << LPTIM_CFGR_TIMOUT_Pos)           /*!< 0x00080000 */

+#define LPTIM_CFGR_TIMOUT           LPTIM_CFGR_TIMOUT_Msk                      /*!< Timout enable */

+#define LPTIM_CFGR_WAVE_Pos         (20U)

+#define LPTIM_CFGR_WAVE_Msk         (0x1UL << LPTIM_CFGR_WAVE_Pos)             /*!< 0x00100000 */

+#define LPTIM_CFGR_WAVE             LPTIM_CFGR_WAVE_Msk                        /*!< Waveform shape */

+#define LPTIM_CFGR_WAVPOL_Pos       (21U)

+#define LPTIM_CFGR_WAVPOL_Msk       (0x1UL << LPTIM_CFGR_WAVPOL_Pos)           /*!< 0x00200000 */

+#define LPTIM_CFGR_WAVPOL           LPTIM_CFGR_WAVPOL_Msk                      /*!< Waveform shape polarity */

+#define LPTIM_CFGR_PRELOAD_Pos      (22U)

+#define LPTIM_CFGR_PRELOAD_Msk      (0x1UL << LPTIM_CFGR_PRELOAD_Pos)          /*!< 0x00400000 */

+#define LPTIM_CFGR_PRELOAD          LPTIM_CFGR_PRELOAD_Msk                     /*!< Reg update mode */

+#define LPTIM_CFGR_COUNTMODE_Pos    (23U)

+#define LPTIM_CFGR_COUNTMODE_Msk    (0x1UL << LPTIM_CFGR_COUNTMODE_Pos)        /*!< 0x00800000 */

+#define LPTIM_CFGR_COUNTMODE        LPTIM_CFGR_COUNTMODE_Msk                   /*!< Counter mode enable */

+#define LPTIM_CFGR_ENC_Pos          (24U)

+#define LPTIM_CFGR_ENC_Msk          (0x1UL << LPTIM_CFGR_ENC_Pos)              /*!< 0x01000000 */

+#define LPTIM_CFGR_ENC              LPTIM_CFGR_ENC_Msk                         /*!< Encoder mode enable */

+

+/******************  Bit definition for LPTIM_CR register  ********************/

+#define LPTIM_CR_ENABLE_Pos         (0U)

+#define LPTIM_CR_ENABLE_Msk         (0x1UL << LPTIM_CR_ENABLE_Pos)             /*!< 0x00000001 */

+#define LPTIM_CR_ENABLE             LPTIM_CR_ENABLE_Msk                        /*!< LPTIMer enable */

+#define LPTIM_CR_SNGSTRT_Pos        (1U)

+#define LPTIM_CR_SNGSTRT_Msk        (0x40001UL << LPTIM_CR_SNGSTRT_Pos)        /*!< 0x00080002 */

+#define LPTIM_CR_SNGSTRT            LPTIM_CR_SNGSTRT_Msk                       /*!< Timer start in single mode */

+#define LPTIM_CR_CNTSTRT_Pos        (2U)

+#define LPTIM_CR_CNTSTRT_Msk        (0x1UL << LPTIM_CR_CNTSTRT_Pos)            /*!< 0x00000004 */

+#define LPTIM_CR_CNTSTRT            LPTIM_CR_CNTSTRT_Msk                       /*!< Timer start in continuous mode */

+#define LPTIM_CR_COUNTRST_Pos       (3U)

+#define LPTIM_CR_COUNTRST_Msk       (0x1UL << LPTIM_CR_COUNTRST_Pos)           /*!< 0x00000008 */

+#define LPTIM_CR_COUNTRST           LPTIM_CR_COUNTRST_Msk                      /*!< Timer Counter reset in synchronous mode*/

+#define LPTIM_CR_RSTARE_Pos         (4U)

+#define LPTIM_CR_RSTARE_Msk         (0x1UL << LPTIM_CR_RSTARE_Pos)             /*!< 0x00000010 */

+#define LPTIM_CR_RSTARE             LPTIM_CR_RSTARE_Msk                        /*!< Timer Counter reset after read enable (asynchronously)*/

+

+

+/******************  Bit definition for LPTIM_CMP register  *******************/

+#define LPTIM_CMP_CMP_Pos           (0U)

+#define LPTIM_CMP_CMP_Msk           (0xFFFFUL << LPTIM_CMP_CMP_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_CMP_CMP               LPTIM_CMP_CMP_Msk                          /*!< Compare register */

+

+/******************  Bit definition for LPTIM_ARR register  *******************/

+#define LPTIM_ARR_ARR_Pos           (0U)

+#define LPTIM_ARR_ARR_Msk           (0xFFFFUL << LPTIM_ARR_ARR_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_ARR_ARR               LPTIM_ARR_ARR_Msk                          /*!< Auto reload register */

+

+/******************  Bit definition for LPTIM_CNT register  *******************/

+#define LPTIM_CNT_CNT_Pos           (0U)

+#define LPTIM_CNT_CNT_Msk           (0xFFFFUL << LPTIM_CNT_CNT_Pos)            /*!< 0x0000FFFF */

+#define LPTIM_CNT_CNT               LPTIM_CNT_CNT_Msk                          /*!< Counter register */

+

+/******************  Bit definition for LPTIM_CFGR2 register  *****************/

+#define LPTIM_CFGR2_IN1SEL_Pos      (0U)

+#define LPTIM_CFGR2_IN1SEL_Msk      (0x3UL << LPTIM_CFGR2_IN1SEL_Pos)          /*!< 0x00000003 */

+#define LPTIM_CFGR2_IN1SEL          LPTIM_CFGR2_IN1SEL_Msk                     /*!< IN1SEL[1:0] bits (Remap selection) */

+#define LPTIM_CFGR2_IN1SEL_0        (0x1UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000001 */

+#define LPTIM_CFGR2_IN1SEL_1        (0x2UL << LPTIM_CFGR2_IN1SEL_Pos)           /*!< 0x00000002 */

+#define LPTIM_CFGR2_IN2SEL_Pos      (4U)

+#define LPTIM_CFGR2_IN2SEL_Msk      (0x3UL << LPTIM_CFGR2_IN2SEL_Pos)          /*!< 0x00000030 */

+#define LPTIM_CFGR2_IN2SEL          LPTIM_CFGR2_IN2SEL_Msk                     /*!< IN2SEL[5:4] bits (Remap selection) */

+#define LPTIM_CFGR2_IN2SEL_0        (0x1UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000010 */

+#define LPTIM_CFGR2_IN2SEL_1        (0x2UL << LPTIM_CFGR2_IN2SEL_Pos)           /*!< 0x00000020 */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                    OCTOSPI                                 */

+/*                                                                            */

+/******************************************************************************/

+/*****************  Bit definition for OCTOSPI_CR register  *******************/

+#define OCTOSPI_CR_EN_Pos              (0U)

+#define OCTOSPI_CR_EN_Msk              (0x1UL << OCTOSPI_CR_EN_Pos)             /*!< 0x00000001 */

+#define OCTOSPI_CR_EN                  OCTOSPI_CR_EN_Msk                       /*!< Enable */

+#define OCTOSPI_CR_ABORT_Pos           (1U)

+#define OCTOSPI_CR_ABORT_Msk           (0x1UL << OCTOSPI_CR_ABORT_Pos)          /*!< 0x00000002 */

+#define OCTOSPI_CR_ABORT               OCTOSPI_CR_ABORT_Msk                    /*!< Abort request */

+#define OCTOSPI_CR_DMAEN_Pos           (2U)

+#define OCTOSPI_CR_DMAEN_Msk           (0x1UL << OCTOSPI_CR_DMAEN_Pos)          /*!< 0x00000004 */

+#define OCTOSPI_CR_DMAEN               OCTOSPI_CR_DMAEN_Msk                    /*!< DMA Enable */

+#define OCTOSPI_CR_TCEN_Pos            (3U)

+#define OCTOSPI_CR_TCEN_Msk            (0x1UL << OCTOSPI_CR_TCEN_Pos)           /*!< 0x00000008 */

+#define OCTOSPI_CR_TCEN                OCTOSPI_CR_TCEN_Msk                     /*!< Timeout Counter Enable */

+#define OCTOSPI_CR_DQM_Pos             (6U)

+#define OCTOSPI_CR_DQM_Msk             (0x1UL << OCTOSPI_CR_DQM_Pos)            /*!< 0x00000040 */

+#define OCTOSPI_CR_DQM                 OCTOSPI_CR_DQM_Msk                      /*!< Dual-Quad Mode */

+#define OCTOSPI_CR_FSEL_Pos            (7U)

+#define OCTOSPI_CR_FSEL_Msk            (0x1UL << OCTOSPI_CR_FSEL_Pos)           /*!< 0x00000080 */

+#define OCTOSPI_CR_FSEL                OCTOSPI_CR_FSEL_Msk                     /*!< Flash Select */

+#define OCTOSPI_CR_FTHRES_Pos          (8U)

+#define OCTOSPI_CR_FTHRES_Msk          (0x1FUL << OCTOSPI_CR_FTHRES_Pos)        /*!< 0x00001F00 */

+#define OCTOSPI_CR_FTHRES              OCTOSPI_CR_FTHRES_Msk                   /*!< FIFO Threshold Level */

+#define OCTOSPI_CR_TEIE_Pos            (16U)

+#define OCTOSPI_CR_TEIE_Msk            (0x1UL << OCTOSPI_CR_TEIE_Pos)           /*!< 0x00010000 */

+#define OCTOSPI_CR_TEIE                OCTOSPI_CR_TEIE_Msk                     /*!< Transfer Error Interrupt Enable */

+#define OCTOSPI_CR_TCIE_Pos            (17U)

+#define OCTOSPI_CR_TCIE_Msk            (0x1UL << OCTOSPI_CR_TCIE_Pos)           /*!< 0x00020000 */

+#define OCTOSPI_CR_TCIE                OCTOSPI_CR_TCIE_Msk                     /*!< Transfer Complete Interrupt Enable */

+#define OCTOSPI_CR_FTIE_Pos            (18U)

+#define OCTOSPI_CR_FTIE_Msk            (0x1UL << OCTOSPI_CR_FTIE_Pos)           /*!< 0x00040000 */

+#define OCTOSPI_CR_FTIE                OCTOSPI_CR_FTIE_Msk                     /*!< FIFO Threshold Interrupt Enable */

+#define OCTOSPI_CR_SMIE_Pos            (19U)

+#define OCTOSPI_CR_SMIE_Msk            (0x1UL << OCTOSPI_CR_SMIE_Pos)           /*!< 0x00080000 */

+#define OCTOSPI_CR_SMIE                OCTOSPI_CR_SMIE_Msk                     /*!< Status Match Interrupt Enable */

+#define OCTOSPI_CR_TOIE_Pos            (20U)

+#define OCTOSPI_CR_TOIE_Msk            (0x1UL << OCTOSPI_CR_TOIE_Pos)           /*!< 0x00100000 */

+#define OCTOSPI_CR_TOIE                OCTOSPI_CR_TOIE_Msk                     /*!< TimeOut Interrupt Enable */

+#define OCTOSPI_CR_APMS_Pos            (22U)

+#define OCTOSPI_CR_APMS_Msk            (0x1UL << OCTOSPI_CR_APMS_Pos)           /*!< 0x00400000 */

+#define OCTOSPI_CR_APMS                OCTOSPI_CR_APMS_Msk                     /*!< Automatic Poll Mode Stop */

+#define OCTOSPI_CR_PMM_Pos             (23U)

+#define OCTOSPI_CR_PMM_Msk             (0x1UL << OCTOSPI_CR_PMM_Pos)            /*!< 0x00800000 */

+#define OCTOSPI_CR_PMM                 OCTOSPI_CR_PMM_Msk                      /*!< Polling Match Mode */

+#define OCTOSPI_CR_FMODE_Pos           (28U)

+#define OCTOSPI_CR_FMODE_Msk           (0x3UL << OCTOSPI_CR_FMODE_Pos)          /*!< 0x30000000 */

+#define OCTOSPI_CR_FMODE               OCTOSPI_CR_FMODE_Msk                    /*!< Functional Mode */

+#define OCTOSPI_CR_FMODE_0             (0x1UL << OCTOSPI_CR_FMODE_Pos)          /*!< 0x10000000 */

+#define OCTOSPI_CR_FMODE_1             (0x2UL << OCTOSPI_CR_FMODE_Pos)          /*!< 0x20000000 */

+

+/****************  Bit definition for OCTOSPI_DCR1 register  ******************/

+#define OCTOSPI_DCR1_CKMODE_Pos        (0U)

+#define OCTOSPI_DCR1_CKMODE_Msk        (0x1UL << OCTOSPI_DCR1_CKMODE_Pos)       /*!< 0x00000001 */

+#define OCTOSPI_DCR1_CKMODE            OCTOSPI_DCR1_CKMODE_Msk                 /*!< Mode 0 / Mode 3 */

+#define OCTOSPI_DCR1_FRCK_Pos          (1U)

+#define OCTOSPI_DCR1_FRCK_Msk          (0x1UL << OCTOSPI_DCR1_FRCK_Pos)         /*!< 0x00000002 */

+#define OCTOSPI_DCR1_FRCK              OCTOSPI_DCR1_FRCK_Msk                   /*!< Free Running Clock */

+#define OCTOSPI_DCR1_DLYBYP_Pos        (3U)

+#define OCTOSPI_DCR1_DLYBYP_Msk        (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos)       /*!< 0x00000008 */

+#define OCTOSPI_DCR1_DLYBYP            OCTOSPI_DCR1_DLYBYP_Msk                 /*!< Delay Block */

+#define OCTOSPI_DCR1_CKCSHT_Pos        (4U)

+#define OCTOSPI_DCR1_CKCSHT_Msk        (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos)       /*!< 0x00000070 */

+#define OCTOSPI_DCR1_CKCSHT            OCTOSPI_DCR1_CKCSHT_Msk                 /*!< Clocked Chip Select High Time */

+#define OCTOSPI_DCR1_CSHT_Pos          (8U)

+#define OCTOSPI_DCR1_CSHT_Msk          (0x7UL << OCTOSPI_DCR1_CSHT_Pos)         /*!< 0x00000700 */

+#define OCTOSPI_DCR1_CSHT              OCTOSPI_DCR1_CSHT_Msk                   /*!< Chip Select High Time */

+#define OCTOSPI_DCR1_DEVSIZE_Pos       (16U)

+#define OCTOSPI_DCR1_DEVSIZE_Msk       (0x1FUL << OCTOSPI_DCR1_DEVSIZE_Pos)     /*!< 0x001F0000 */

+#define OCTOSPI_DCR1_DEVSIZE           OCTOSPI_DCR1_DEVSIZE_Msk                /*!< Device Size */

+#define OCTOSPI_DCR1_MTYP_Pos          (24U)

+#define OCTOSPI_DCR1_MTYP_Msk          (0x7UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x07000000 */

+#define OCTOSPI_DCR1_MTYP              OCTOSPI_DCR1_MTYP_Msk                   /*!< Memory Type */

+#define OCTOSPI_DCR1_MTYP_0            (0x1UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x01000000 */

+#define OCTOSPI_DCR1_MTYP_1            (0x2UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x02000000 */

+#define OCTOSPI_DCR1_MTYP_2            (0x4UL << OCTOSPI_DCR1_MTYP_Pos)         /*!< 0x04000000 */

+

+/****************  Bit definition for OCTOSPI_DCR2 register  ******************/

+#define OCTOSPI_DCR2_PRESCALER_Pos     (0U)

+#define OCTOSPI_DCR2_PRESCALER_Msk     (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos)   /*!< 0x000000FF */

+#define OCTOSPI_DCR2_PRESCALER         OCTOSPI_DCR2_PRESCALER_Msk              /*!< Clock prescaler */

+#define OCTOSPI_DCR2_WRAPSIZE_Pos      (16U)

+#define OCTOSPI_DCR2_WRAPSIZE_Msk      (0x7UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00070000 */

+#define OCTOSPI_DCR2_WRAPSIZE          OCTOSPI_DCR2_WRAPSIZE_Msk               /*!< Wrap Size */

+#define OCTOSPI_DCR2_WRAPSIZE_0        (0x1UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00010000 */

+#define OCTOSPI_DCR2_WRAPSIZE_1        (0x2UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00020000 */

+#define OCTOSPI_DCR2_WRAPSIZE_2        (0x4UL << OCTOSPI_DCR2_WRAPSIZE_Pos)     /*!< 0x00040000 */

+

+/****************  Bit definition for OCTOSPI_DCR3 register  ******************/

+#define OCTOSPI_DCR3_MAXTRAN_Pos       (0U)

+#define OCTOSPI_DCR3_MAXTRAN_Msk       (0xFFUL << OCTOSPI_DCR3_MAXTRAN_Pos)     /*!< 0x000000FF */

+#define OCTOSPI_DCR3_MAXTRAN           OCTOSPI_DCR3_MAXTRAN_Msk                /*!< Maximum Transfer */

+#define OCTOSPI_DCR3_CSBOUND_Pos       (16U)

+#define OCTOSPI_DCR3_CSBOUND_Msk       (0x1FUL << OCTOSPI_DCR3_CSBOUND_Pos)     /*!< 0x001F0000 */

+#define OCTOSPI_DCR3_CSBOUND           OCTOSPI_DCR3_CSBOUND_Msk                /*!< CS Boundary */

+

+/****************  Bit definition for OCTOSPI_DCR4 register  ******************/

+#define OCTOSPI_DCR4_REFRESH_Pos       (0U)

+#define OCTOSPI_DCR4_REFRESH_Msk       (0xFFFFFFFFUL << OCTOSPI_DCR4_REFRESH_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_DCR4_REFRESH           OCTOSPI_DCR4_REFRESH_Msk                /*!< Refresh rate */

+

+/*****************  Bit definition for OCTOSPI_SR register  *******************/

+#define OCTOSPI_SR_TEF_Pos             (0U)

+#define OCTOSPI_SR_TEF_Msk             (0x1UL << OCTOSPI_SR_TEF_Pos)            /*!< 0x00000001 */

+#define OCTOSPI_SR_TEF                 OCTOSPI_SR_TEF_Msk                      /*!< Transfer Error Flag */

+#define OCTOSPI_SR_TCF_Pos             (1U)

+#define OCTOSPI_SR_TCF_Msk             (0x1UL << OCTOSPI_SR_TCF_Pos)            /*!< 0x00000002 */

+#define OCTOSPI_SR_TCF                 OCTOSPI_SR_TCF_Msk                      /*!< Transfer Complete Flag */

+#define OCTOSPI_SR_FTF_Pos             (2U)

+#define OCTOSPI_SR_FTF_Msk             (0x1UL << OCTOSPI_SR_FTF_Pos)            /*!< 0x00000004 */

+#define OCTOSPI_SR_FTF                 OCTOSPI_SR_FTF_Msk                      /*!< FIFO Threshold Flag */

+#define OCTOSPI_SR_SMF_Pos             (3U)

+#define OCTOSPI_SR_SMF_Msk             (0x1UL << OCTOSPI_SR_SMF_Pos)            /*!< 0x00000008 */

+#define OCTOSPI_SR_SMF                 OCTOSPI_SR_SMF_Msk                      /*!< Status Match Flag */

+#define OCTOSPI_SR_TOF_Pos             (4U)

+#define OCTOSPI_SR_TOF_Msk             (0x1UL << OCTOSPI_SR_TOF_Pos)            /*!< 0x00000010 */

+#define OCTOSPI_SR_TOF                 OCTOSPI_SR_TOF_Msk                      /*!< Timeout Flag */

+#define OCTOSPI_SR_BUSY_Pos            (5U)

+#define OCTOSPI_SR_BUSY_Msk            (0x1UL << OCTOSPI_SR_BUSY_Pos)           /*!< 0x00000020 */

+#define OCTOSPI_SR_BUSY                OCTOSPI_SR_BUSY_Msk                     /*!< Busy */

+#define OCTOSPI_SR_FLEVEL_Pos          (8U)

+#define OCTOSPI_SR_FLEVEL_Msk          (0x3FUL << OCTOSPI_SR_FLEVEL_Pos)        /*!< 0x00003F00 */

+#define OCTOSPI_SR_FLEVEL              OCTOSPI_SR_FLEVEL_Msk                   /*!< FIFO Level */

+

+/****************  Bit definition for OCTOSPI_FCR register  *******************/

+#define OCTOSPI_FCR_CTEF_Pos           (0U)

+#define OCTOSPI_FCR_CTEF_Msk           (0x1UL << OCTOSPI_FCR_CTEF_Pos)          /*!< 0x00000001 */

+#define OCTOSPI_FCR_CTEF               OCTOSPI_FCR_CTEF_Msk                    /*!< Clear Transfer Error Flag */

+#define OCTOSPI_FCR_CTCF_Pos           (1U)

+#define OCTOSPI_FCR_CTCF_Msk           (0x1UL << OCTOSPI_FCR_CTCF_Pos)          /*!< 0x00000002 */

+#define OCTOSPI_FCR_CTCF               OCTOSPI_FCR_CTCF_Msk                    /*!< Clear Transfer Complete Flag */

+#define OCTOSPI_FCR_CSMF_Pos           (3U)

+#define OCTOSPI_FCR_CSMF_Msk           (0x1UL << OCTOSPI_FCR_CSMF_Pos)          /*!< 0x00000008 */

+#define OCTOSPI_FCR_CSMF               OCTOSPI_FCR_CSMF_Msk                    /*!< Clear Status Match Flag */

+#define OCTOSPI_FCR_CTOF_Pos           (4U)

+#define OCTOSPI_FCR_CTOF_Msk           (0x1UL << OCTOSPI_FCR_CTOF_Pos)          /*!< 0x00000010 */

+#define OCTOSPI_FCR_CTOF               OCTOSPI_FCR_CTOF_Msk                    /*!< Clear Timeout Flag */

+

+/****************  Bit definition for OCTOSPI_DLR register  *******************/

+#define OCTOSPI_DLR_DL_Pos             (0U)

+#define OCTOSPI_DLR_DL_Msk             (0xFFFFFFFFUL << OCTOSPI_DLR_DL_Pos)     /*!< 0xFFFFFFFF */

+#define OCTOSPI_DLR_DL                 OCTOSPI_DLR_DL_Msk                      /*!< Data Length */

+

+/*****************  Bit definition for OCTOSPI_AR register  *******************/

+#define OCTOSPI_AR_ADDRESS_Pos         (0U)

+#define OCTOSPI_AR_ADDRESS_Msk         (0xFFFFFFFFUL << OCTOSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_AR_ADDRESS             OCTOSPI_AR_ADDRESS_Msk                  /*!< Address */

+

+/*****************  Bit definition for OCTOSPI_DR register  *******************/

+#define OCTOSPI_DR_DATA_Pos            (0U)

+#define OCTOSPI_DR_DATA_Msk            (0xFFFFFFFFUL << OCTOSPI_DR_DATA_Pos)    /*!< 0xFFFFFFFF */

+#define OCTOSPI_DR_DATA                OCTOSPI_DR_DATA_Msk                     /*!< Data */

+

+/***************  Bit definition for OCTOSPI_PSMKR register  ******************/

+#define OCTOSPI_PSMKR_MASK_Pos         (0U)

+#define OCTOSPI_PSMKR_MASK_Msk         (0xFFFFFFFFUL << OCTOSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_PSMKR_MASK             OCTOSPI_PSMKR_MASK_Msk                  /*!< Status mask */

+

+/***************  Bit definition for OCTOSPI_PSMAR register  ******************/

+#define OCTOSPI_PSMAR_MATCH_Pos        (0U)

+#define OCTOSPI_PSMAR_MATCH_Msk        (0xFFFFFFFFUL << OCTOSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_PSMAR_MATCH            OCTOSPI_PSMAR_MATCH_Msk                 /*!< Status match */

+

+/****************  Bit definition for OCTOSPI_PIR register  *******************/

+#define OCTOSPI_PIR_INTERVAL_Pos       (0U)

+#define OCTOSPI_PIR_INTERVAL_Msk       (0xFFFFUL << OCTOSPI_PIR_INTERVAL_Pos)   /*!< 0x0000FFFF */

+#define OCTOSPI_PIR_INTERVAL           OCTOSPI_PIR_INTERVAL_Msk                /*!< Polling Interval */

+

+/****************  Bit definition for OCTOSPI_CCR register  *******************/

+#define OCTOSPI_CCR_IMODE_Pos          (0U)

+#define OCTOSPI_CCR_IMODE_Msk          (0x7UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000007 */

+#define OCTOSPI_CCR_IMODE              OCTOSPI_CCR_IMODE_Msk                   /*!< Instruction Mode */

+#define OCTOSPI_CCR_IMODE_0            (0x1UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000001 */

+#define OCTOSPI_CCR_IMODE_1            (0x2UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000002 */

+#define OCTOSPI_CCR_IMODE_2            (0x4UL << OCTOSPI_CCR_IMODE_Pos)         /*!< 0x00000004 */

+#define OCTOSPI_CCR_IDTR_Pos           (3U)

+#define OCTOSPI_CCR_IDTR_Msk           (0x1UL << OCTOSPI_CCR_IDTR_Pos)          /*!< 0x00000008 */

+#define OCTOSPI_CCR_IDTR               OCTOSPI_CCR_IDTR_Msk                    /*!< Instruction Double Transfer Rate */

+#define OCTOSPI_CCR_ISIZE_Pos          (4U)

+#define OCTOSPI_CCR_ISIZE_Msk          (0x3UL << OCTOSPI_CCR_ISIZE_Pos)         /*!< 0x00000030 */

+#define OCTOSPI_CCR_ISIZE              OCTOSPI_CCR_ISIZE_Msk                   /*!< Instruction Size */

+#define OCTOSPI_CCR_ISIZE_0            (0x1UL << OCTOSPI_CCR_ISIZE_Pos)         /*!< 0x00000010 */

+#define OCTOSPI_CCR_ISIZE_1            (0x2UL << OCTOSPI_CCR_ISIZE_Pos)         /*!< 0x00000020 */

+#define OCTOSPI_CCR_ADMODE_Pos         (8U)

+#define OCTOSPI_CCR_ADMODE_Msk         (0x7UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000700 */

+#define OCTOSPI_CCR_ADMODE             OCTOSPI_CCR_ADMODE_Msk                  /*!< Address Mode */

+#define OCTOSPI_CCR_ADMODE_0           (0x1UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000100 */

+#define OCTOSPI_CCR_ADMODE_1           (0x2UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000200 */

+#define OCTOSPI_CCR_ADMODE_2           (0x4UL << OCTOSPI_CCR_ADMODE_Pos)        /*!< 0x00000400 */

+#define OCTOSPI_CCR_ADDTR_Pos          (11U)

+#define OCTOSPI_CCR_ADDTR_Msk          (0x1UL << OCTOSPI_CCR_ADDTR_Pos)         /*!< 0x00000800 */

+#define OCTOSPI_CCR_ADDTR              OCTOSPI_CCR_ADDTR_Msk                   /*!< Address Double Transfer Rate */

+#define OCTOSPI_CCR_ADSIZE_Pos         (12U)

+#define OCTOSPI_CCR_ADSIZE_Msk         (0x3UL << OCTOSPI_CCR_ADSIZE_Pos)        /*!< 0x00003000 */

+#define OCTOSPI_CCR_ADSIZE             OCTOSPI_CCR_ADSIZE_Msk                  /*!< Address Size */

+#define OCTOSPI_CCR_ADSIZE_0           (0x1UL << OCTOSPI_CCR_ADSIZE_Pos)        /*!< 0x00001000 */

+#define OCTOSPI_CCR_ADSIZE_1           (0x2UL << OCTOSPI_CCR_ADSIZE_Pos)        /*!< 0x00002000 */

+#define OCTOSPI_CCR_ABMODE_Pos         (16U)

+#define OCTOSPI_CCR_ABMODE_Msk         (0x7UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00070000 */

+#define OCTOSPI_CCR_ABMODE             OCTOSPI_CCR_ABMODE_Msk                  /*!< Alternate Bytes Mode */

+#define OCTOSPI_CCR_ABMODE_0           (0x1UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00010000 */

+#define OCTOSPI_CCR_ABMODE_1           (0x2UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00020000 */

+#define OCTOSPI_CCR_ABMODE_2           (0x4UL << OCTOSPI_CCR_ABMODE_Pos)        /*!< 0x00040000 */

+#define OCTOSPI_CCR_ABDTR_Pos          (19U)

+#define OCTOSPI_CCR_ABDTR_Msk          (0x1UL << OCTOSPI_CCR_ABDTR_Pos)         /*!< 0x00080000 */

+#define OCTOSPI_CCR_ABDTR              OCTOSPI_CCR_ABDTR_Msk                   /*!< Alternate Bytes Double Transfer Rate */

+#define OCTOSPI_CCR_ABSIZE_Pos         (20U)

+#define OCTOSPI_CCR_ABSIZE_Msk         (0x3UL << OCTOSPI_CCR_ABSIZE_Pos)        /*!< 0x00300000 */

+#define OCTOSPI_CCR_ABSIZE             OCTOSPI_CCR_ABSIZE_Msk                  /*!< Alternate Bytes Size */

+#define OCTOSPI_CCR_ABSIZE_0           (0x1UL << OCTOSPI_CCR_ABSIZE_Pos)        /*!< 0x00100000 */

+#define OCTOSPI_CCR_ABSIZE_1           (0x2UL << OCTOSPI_CCR_ABSIZE_Pos)        /*!< 0x00200000 */

+#define OCTOSPI_CCR_DMODE_Pos          (24U)

+#define OCTOSPI_CCR_DMODE_Msk          (0x7UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x07000000 */

+#define OCTOSPI_CCR_DMODE              OCTOSPI_CCR_DMODE_Msk                   /*!< Data Mode */

+#define OCTOSPI_CCR_DMODE_0            (0x1UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x01000000 */

+#define OCTOSPI_CCR_DMODE_1            (0x2UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x02000000 */

+#define OCTOSPI_CCR_DMODE_2            (0x4UL << OCTOSPI_CCR_DMODE_Pos)         /*!< 0x04000000 */

+#define OCTOSPI_CCR_DDTR_Pos           (27U)

+#define OCTOSPI_CCR_DDTR_Msk           (0x1UL << OCTOSPI_CCR_DDTR_Pos)          /*!< 0x08000000 */

+#define OCTOSPI_CCR_DDTR               OCTOSPI_CCR_DDTR_Msk                    /*!< Data Double Transfer Rate */

+#define OCTOSPI_CCR_DQSE_Pos           (29U)

+#define OCTOSPI_CCR_DQSE_Msk           (0x1UL << OCTOSPI_CCR_DQSE_Pos)          /*!< 0x20000000 */

+#define OCTOSPI_CCR_DQSE               OCTOSPI_CCR_DQSE_Msk                    /*!< DQS Enable */

+#define OCTOSPI_CCR_SIOO_Pos           (31U)

+#define OCTOSPI_CCR_SIOO_Msk           (0x1UL << OCTOSPI_CCR_SIOO_Pos)          /*!< 0x80000000 */

+#define OCTOSPI_CCR_SIOO               OCTOSPI_CCR_SIOO_Msk                    /*!< Send Instruction Only Once Mode */

+

+/****************  Bit definition for OCTOSPI_TCR register  *******************/

+#define OCTOSPI_TCR_DCYC_Pos           (0U)

+#define OCTOSPI_TCR_DCYC_Msk           (0x1FUL << OCTOSPI_TCR_DCYC_Pos)         /*!< 0x0000001F */

+#define OCTOSPI_TCR_DCYC               OCTOSPI_TCR_DCYC_Msk                    /*!< Number of Dummy Cycles */

+#define OCTOSPI_TCR_DHQC_Pos           (28U)

+#define OCTOSPI_TCR_DHQC_Msk           (0x1UL << OCTOSPI_TCR_DHQC_Pos)          /*!< 0x10000000 */

+#define OCTOSPI_TCR_DHQC               OCTOSPI_TCR_DHQC_Msk                    /*!< Delay Hold Quarter Cycle */

+#define OCTOSPI_TCR_SSHIFT_Pos         (30U)

+#define OCTOSPI_TCR_SSHIFT_Msk         (0x1UL << OCTOSPI_TCR_SSHIFT_Pos)        /*!< 0x40000000 */

+#define OCTOSPI_TCR_SSHIFT             OCTOSPI_TCR_SSHIFT_Msk                  /*!< Sample Shift */

+

+/*****************  Bit definition for OCTOSPI_IR register  *******************/

+#define OCTOSPI_IR_INSTRUCTION_Pos     (0U)

+#define OCTOSPI_IR_INSTRUCTION_Msk     (0xFFFFFFFFUL << OCTOSPI_IR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_IR_INSTRUCTION         OCTOSPI_IR_INSTRUCTION_Msk              /*!< Instruction */

+

+/****************  Bit definition for OCTOSPI_ABR register  *******************/

+#define OCTOSPI_ABR_ALTERNATE_Pos      (0U)

+#define OCTOSPI_ABR_ALTERNATE_Msk      (0xFFFFFFFFUL << OCTOSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_ABR_ALTERNATE          OCTOSPI_ABR_ALTERNATE_Msk               /*!< Alternate Bytes */

+

+/****************  Bit definition for OCTOSPI_LPTR register  ******************/

+#define OCTOSPI_LPTR_TIMEOUT_Pos       (0U)

+#define OCTOSPI_LPTR_TIMEOUT_Msk       (0xFFFFUL << OCTOSPI_LPTR_TIMEOUT_Pos)   /*!< 0x0000FFFF */

+#define OCTOSPI_LPTR_TIMEOUT           OCTOSPI_LPTR_TIMEOUT_Msk                /*!< Timeout period */

+

+/****************  Bit definition for OCTOSPI_WPCCR register  *******************/

+#define OCTOSPI_WPCCR_IMODE_Pos        (0U)

+#define OCTOSPI_WPCCR_IMODE_Msk        (0x7UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000007 */

+#define OCTOSPI_WPCCR_IMODE            OCTOSPI_WPCCR_IMODE_Msk                 /*!< Instruction Mode */

+#define OCTOSPI_WPCCR_IMODE_0          (0x1UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000001 */

+#define OCTOSPI_WPCCR_IMODE_1          (0x2UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000002 */

+#define OCTOSPI_WPCCR_IMODE_2          (0x4UL << OCTOSPI_WPCCR_IMODE_Pos)       /*!< 0x00000004 */

+#define OCTOSPI_WPCCR_IDTR_Pos         (3U)

+#define OCTOSPI_WPCCR_IDTR_Msk         (0x1UL << OCTOSPI_WPCCR_IDTR_Pos)        /*!< 0x00000008 */

+#define OCTOSPI_WPCCR_IDTR             OCTOSPI_WPCCR_IDTR_Msk                  /*!< Instruction Double Transfer Rate */

+#define OCTOSPI_WPCCR_ISIZE_Pos        (4U)

+#define OCTOSPI_WPCCR_ISIZE_Msk        (0x3UL << OCTOSPI_WPCCR_ISIZE_Pos)       /*!< 0x00000030 */

+#define OCTOSPI_WPCCR_ISIZE            OCTOSPI_WPCCR_ISIZE_Msk                 /*!< Instruction Size */

+#define OCTOSPI_WPCCR_ISIZE_0          (0x1UL << OCTOSPI_WPCCR_ISIZE_Pos)       /*!< 0x00000010 */

+#define OCTOSPI_WPCCR_ISIZE_1          (0x2UL << OCTOSPI_WPCCR_ISIZE_Pos)       /*!< 0x00000020 */

+#define OCTOSPI_WPCCR_ADMODE_Pos       (8U)

+#define OCTOSPI_WPCCR_ADMODE_Msk       (0x7UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000700 */

+#define OCTOSPI_WPCCR_ADMODE           OCTOSPI_WPCCR_ADMODE_Msk                /*!< Address Mode */

+#define OCTOSPI_WPCCR_ADMODE_0         (0x1UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000100 */

+#define OCTOSPI_WPCCR_ADMODE_1         (0x2UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000200 */

+#define OCTOSPI_WPCCR_ADMODE_2         (0x4UL << OCTOSPI_WPCCR_ADMODE_Pos)      /*!< 0x00000400 */

+#define OCTOSPI_WPCCR_ADDTR_Pos        (11U)

+#define OCTOSPI_WPCCR_ADDTR_Msk        (0x1UL << OCTOSPI_WPCCR_ADDTR_Pos)       /*!< 0x00000800 */

+#define OCTOSPI_WPCCR_ADDTR            OCTOSPI_WPCCR_ADDTR_Msk                 /*!< Address Double Transfer Rate */

+#define OCTOSPI_WPCCR_ADSIZE_Pos       (12U)

+#define OCTOSPI_WPCCR_ADSIZE_Msk       (0x3UL << OCTOSPI_WPCCR_ADSIZE_Pos)      /*!< 0x00003000 */

+#define OCTOSPI_WPCCR_ADSIZE           OCTOSPI_WPCCR_ADSIZE_Msk                /*!< Address Size */

+#define OCTOSPI_WPCCR_ADSIZE_0         (0x1UL << OCTOSPI_WPCCR_ADSIZE_Pos)      /*!< 0x00001000 */

+#define OCTOSPI_WPCCR_ADSIZE_1         (0x2UL << OCTOSPI_WPCCR_ADSIZE_Pos)      /*!< 0x00002000 */

+#define OCTOSPI_WPCCR_ABMODE_Pos       (16U)

+#define OCTOSPI_WPCCR_ABMODE_Msk       (0x7UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00070000 */

+#define OCTOSPI_WPCCR_ABMODE           OCTOSPI_WPCCR_ABMODE_Msk                /*!< Alternate Bytes Mode */

+#define OCTOSPI_WPCCR_ABMODE_0         (0x1UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00010000 */

+#define OCTOSPI_WPCCR_ABMODE_1         (0x2UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00020000 */

+#define OCTOSPI_WPCCR_ABMODE_2         (0x4UL << OCTOSPI_WPCCR_ABMODE_Pos)      /*!< 0x00040000 */

+#define OCTOSPI_WPCCR_ABDTR_Pos        (19U)

+#define OCTOSPI_WPCCR_ABDTR_Msk        (0x1UL << OCTOSPI_WPCCR_ABDTR_Pos)       /*!< 0x00080000 */

+#define OCTOSPI_WPCCR_ABDTR            OCTOSPI_WPCCR_ABDTR_Msk                 /*!< Alternate Bytes Double Transfer Rate */

+#define OCTOSPI_WPCCR_ABSIZE_Pos       (20U)

+#define OCTOSPI_WPCCR_ABSIZE_Msk       (0x3UL << OCTOSPI_WPCCR_ABSIZE_Pos)      /*!< 0x00300000 */

+#define OCTOSPI_WPCCR_ABSIZE           OCTOSPI_WPCCR_ABSIZE_Msk                /*!< Alternate Bytes Size */

+#define OCTOSPI_WPCCR_ABSIZE_0         (0x1UL << OCTOSPI_WPCCR_ABSIZE_Pos)      /*!< 0x00100000 */

+#define OCTOSPI_WPCCR_ABSIZE_1         (0x2UL << OCTOSPI_WPCCR_ABSIZE_Pos)      /*!< 0x00200000 */

+#define OCTOSPI_WPCCR_DMODE_Pos        (24U)

+#define OCTOSPI_WPCCR_DMODE_Msk        (0x7UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x07000000 */

+#define OCTOSPI_WPCCR_DMODE            OCTOSPI_WPCCR_DMODE_Msk                 /*!< Data Mode */

+#define OCTOSPI_WPCCR_DMODE_0          (0x1UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x01000000 */

+#define OCTOSPI_WPCCR_DMODE_1          (0x2UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x02000000 */

+#define OCTOSPI_WPCCR_DMODE_2          (0x4UL << OCTOSPI_WPCCR_DMODE_Pos)       /*!< 0x04000000 */

+#define OCTOSPI_WPCCR_DDTR_Pos         (27U)

+#define OCTOSPI_WPCCR_DDTR_Msk         (0x1UL << OCTOSPI_WPCCR_DDTR_Pos)        /*!< 0x08000000 */

+#define OCTOSPI_WPCCR_DDTR             OCTOSPI_WPCCR_DDTR_Msk                  /*!< Data Double Transfer Rate */

+#define OCTOSPI_WPCCR_DQSE_Pos         (29U)

+#define OCTOSPI_WPCCR_DQSE_Msk         (0x1UL << OCTOSPI_WPCCR_DQSE_Pos)        /*!< 0x20000000 */

+#define OCTOSPI_WPCCR_DQSE             OCTOSPI_WPCCR_DQSE_Msk                  /*!< DQS Enable */

+#define OCTOSPI_WPCCR_SIOO_Pos         (31U)

+#define OCTOSPI_WPCCR_SIOO_Msk         (0x1UL << OCTOSPI_WPCCR_SIOO_Pos)        /*!< 0x80000000 */

+#define OCTOSPI_WPCCR_SIOO             OCTOSPI_WPCCR_SIOO_Msk                  /*!< Send Instruction Only Once Mode */

+

+/****************  Bit definition for OCTOSPI_WPTCR register  *******************/

+#define OCTOSPI_WPTCR_DCYC_Pos         (0U)

+#define OCTOSPI_WPTCR_DCYC_Msk         (0x1FUL << OCTOSPI_WPTCR_DCYC_Pos)       /*!< 0x0000001F */

+#define OCTOSPI_WPTCR_DCYC             OCTOSPI_WPTCR_DCYC_Msk                  /*!< Number of Dummy Cycles */

+#define OCTOSPI_WPTCR_DHQC_Pos         (28U)

+#define OCTOSPI_WPTCR_DHQC_Msk         (0x1UL << OCTOSPI_WPTCR_DHQC_Pos)        /*!< 0x10000000 */

+#define OCTOSPI_WPTCR_DHQC             OCTOSPI_WPTCR_DHQC_Msk                  /*!< Delay Hold Quarter Cycle */

+#define OCTOSPI_WPTCR_SSHIFT_Pos       (30U)

+#define OCTOSPI_WPTCR_SSHIFT_Msk       (0x1UL << OCTOSPI_WPTCR_SSHIFT_Pos)      /*!< 0x40000000 */

+#define OCTOSPI_WPTCR_SSHIFT           OCTOSPI_WPTCR_SSHIFT_Msk                /*!< Sample Shift */

+

+/*****************  Bit definition for OCTOSPI_WPIR register  *******************/

+#define OCTOSPI_WPIR_INSTRUCTION_Pos   (0U)

+#define OCTOSPI_WPIR_INSTRUCTION_Msk   (0xFFFFFFFFUL << OCTOSPI_WPIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_WPIR_INSTRUCTION       OCTOSPI_WPIR_INSTRUCTION_Msk            /*!< Instruction */

+

+/****************  Bit definition for OCTOSPI_WPABR register  *******************/

+#define OCTOSPI_WPABR_ALTERNATE_Pos    (0U)

+#define OCTOSPI_WPABR_ALTERNATE_Msk    (0xFFFFFFFFUL << OCTOSPI_WPABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_WPABR_ALTERNATE        OCTOSPI_WPABR_ALTERNATE_Msk             /*!< Alternate Bytes */

+

+/****************  Bit definition for OCTOSPI_WCCR register  ******************/

+#define OCTOSPI_WCCR_IMODE_Pos         (0U)

+#define OCTOSPI_WCCR_IMODE_Msk         (0x7UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000007 */

+#define OCTOSPI_WCCR_IMODE             OCTOSPI_WCCR_IMODE_Msk                  /*!< Instruction Mode */

+#define OCTOSPI_WCCR_IMODE_0           (0x1UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000001 */

+#define OCTOSPI_WCCR_IMODE_1           (0x2UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000002 */

+#define OCTOSPI_WCCR_IMODE_2           (0x4UL << OCTOSPI_WCCR_IMODE_Pos)        /*!< 0x00000004 */

+#define OCTOSPI_WCCR_IDTR_Pos          (3U)

+#define OCTOSPI_WCCR_IDTR_Msk          (0x1UL << OCTOSPI_WCCR_IDTR_Pos)         /*!< 0x00000008 */

+#define OCTOSPI_WCCR_IDTR              OCTOSPI_WCCR_IDTR_Msk                   /*!< Instruction Double Transfer Rate */

+#define OCTOSPI_WCCR_ISIZE_Pos         (4U)

+#define OCTOSPI_WCCR_ISIZE_Msk         (0x3UL << OCTOSPI_WCCR_ISIZE_Pos)        /*!< 0x00000030 */

+#define OCTOSPI_WCCR_ISIZE             OCTOSPI_WCCR_ISIZE_Msk                  /*!< Instruction Size */

+#define OCTOSPI_WCCR_ISIZE_0           (0x1UL << OCTOSPI_WCCR_ISIZE_Pos)        /*!< 0x00000010 */

+#define OCTOSPI_WCCR_ISIZE_1           (0x2UL << OCTOSPI_WCCR_ISIZE_Pos)        /*!< 0x00000020 */

+#define OCTOSPI_WCCR_ADMODE_Pos        (8U)

+#define OCTOSPI_WCCR_ADMODE_Msk        (0x7UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000700 */

+#define OCTOSPI_WCCR_ADMODE            OCTOSPI_WCCR_ADMODE_Msk                 /*!< Address Mode */

+#define OCTOSPI_WCCR_ADMODE_0          (0x1UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000100 */

+#define OCTOSPI_WCCR_ADMODE_1          (0x2UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000200 */

+#define OCTOSPI_WCCR_ADMODE_2          (0x4UL << OCTOSPI_WCCR_ADMODE_Pos)       /*!< 0x00000400 */

+#define OCTOSPI_WCCR_ADDTR_Pos         (11U)

+#define OCTOSPI_WCCR_ADDTR_Msk         (0x1UL << OCTOSPI_WCCR_ADDTR_Pos)        /*!< 0x00000800 */

+#define OCTOSPI_WCCR_ADDTR             OCTOSPI_WCCR_ADDTR_Msk                  /*!< Address Double Transfer Rate */

+#define OCTOSPI_WCCR_ADSIZE_Pos        (12U)

+#define OCTOSPI_WCCR_ADSIZE_Msk        (0x3UL << OCTOSPI_WCCR_ADSIZE_Pos)       /*!< 0x00003000 */

+#define OCTOSPI_WCCR_ADSIZE            OCTOSPI_WCCR_ADSIZE_Msk                 /*!< Address Size */

+#define OCTOSPI_WCCR_ADSIZE_0          (0x1UL << OCTOSPI_WCCR_ADSIZE_Pos)       /*!< 0x00001000 */

+#define OCTOSPI_WCCR_ADSIZE_1          (0x2UL << OCTOSPI_WCCR_ADSIZE_Pos)       /*!< 0x00002000 */

+#define OCTOSPI_WCCR_ABMODE_Pos        (16U)

+#define OCTOSPI_WCCR_ABMODE_Msk        (0x7UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00070000 */

+#define OCTOSPI_WCCR_ABMODE            OCTOSPI_WCCR_ABMODE_Msk                 /*!< Alternate Bytes Mode */

+#define OCTOSPI_WCCR_ABMODE_0          (0x1UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00010000 */

+#define OCTOSPI_WCCR_ABMODE_1          (0x2UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00020000 */

+#define OCTOSPI_WCCR_ABMODE_2          (0x4UL << OCTOSPI_WCCR_ABMODE_Pos)       /*!< 0x00040000 */

+#define OCTOSPI_WCCR_ABDTR_Pos         (19U)

+#define OCTOSPI_WCCR_ABDTR_Msk         (0x1UL << OCTOSPI_WCCR_ABDTR_Pos)        /*!< 0x00080000 */

+#define OCTOSPI_WCCR_ABDTR             OCTOSPI_WCCR_ABDTR_Msk                  /*!< Alternate Bytes Double Transfer Rate */

+#define OCTOSPI_WCCR_ABSIZE_Pos        (20U)

+#define OCTOSPI_WCCR_ABSIZE_Msk        (0x3UL << OCTOSPI_WCCR_ABSIZE_Pos)       /*!< 0x00300000 */

+#define OCTOSPI_WCCR_ABSIZE            OCTOSPI_WCCR_ABSIZE_Msk                 /*!< Alternate Bytes Size */

+#define OCTOSPI_WCCR_ABSIZE_0          (0x1UL << OCTOSPI_WCCR_ABSIZE_Pos)       /*!< 0x00100000 */

+#define OCTOSPI_WCCR_ABSIZE_1          (0x2UL << OCTOSPI_WCCR_ABSIZE_Pos)       /*!< 0x00200000 */

+#define OCTOSPI_WCCR_DMODE_Pos         (24U)

+#define OCTOSPI_WCCR_DMODE_Msk         (0x7UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x07000000 */

+#define OCTOSPI_WCCR_DMODE             OCTOSPI_WCCR_DMODE_Msk                  /*!< Data Mode */

+#define OCTOSPI_WCCR_DMODE_0           (0x1UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x01000000 */

+#define OCTOSPI_WCCR_DMODE_1           (0x2UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x02000000 */

+#define OCTOSPI_WCCR_DMODE_2           (0x4UL << OCTOSPI_WCCR_DMODE_Pos)        /*!< 0x04000000 */

+#define OCTOSPI_WCCR_DDTR_Pos          (27U)

+#define OCTOSPI_WCCR_DDTR_Msk          (0x1UL << OCTOSPI_WCCR_DDTR_Pos)         /*!< 0x08000000 */

+#define OCTOSPI_WCCR_DDTR              OCTOSPI_WCCR_DDTR_Msk                   /*!< Data Double Transfer Rate */

+#define OCTOSPI_WCCR_DQSE_Pos          (29U)

+#define OCTOSPI_WCCR_DQSE_Msk          (0x1UL << OCTOSPI_WCCR_DQSE_Pos)         /*!< 0x20000000 */

+#define OCTOSPI_WCCR_DQSE              OCTOSPI_WCCR_DQSE_Msk                   /*!< DQS Enable */

+#define OCTOSPI_WCCR_SIOO_Pos          (31U)

+#define OCTOSPI_WCCR_SIOO_Msk          (0x1UL << OCTOSPI_WCCR_SIOO_Pos)         /*!< 0x80000000 */

+#define OCTOSPI_WCCR_SIOO              OCTOSPI_WCCR_SIOO_Msk                   /*!< Send Instruction Only Once Mode */

+

+/****************  Bit definition for OCTOSPI_WTCR register  ******************/

+#define OCTOSPI_WTCR_DCYC_Pos          (0U)

+#define OCTOSPI_WTCR_DCYC_Msk          (0x1FUL << OCTOSPI_WTCR_DCYC_Pos)        /*!< 0x0000001F */

+#define OCTOSPI_WTCR_DCYC              OCTOSPI_WTCR_DCYC_Msk                   /*!< Number of Dummy Cycles */

+

+/****************  Bit definition for OCTOSPI_WIR register  *******************/

+#define OCTOSPI_WIR_INSTRUCTION_Pos    (0U)

+#define OCTOSPI_WIR_INSTRUCTION_Msk    (0xFFFFFFFFUL << OCTOSPI_WIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_WIR_INSTRUCTION        OCTOSPI_WIR_INSTRUCTION_Msk             /*!< Instruction */

+

+/****************  Bit definition for OCTOSPI_WABR register  ******************/

+#define OCTOSPI_WABR_ALTERNATE_Pos     (0U)

+#define OCTOSPI_WABR_ALTERNATE_Msk     (0xFFFFFFFFUL << OCTOSPI_WABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */

+#define OCTOSPI_WABR_ALTERNATE         OCTOSPI_WABR_ALTERNATE_Msk              /*!< Alternate Bytes */

+

+/****************  Bit definition for OCTOSPI_HLCR register  ******************/

+#define OCTOSPI_HLCR_LM_Pos            (0U)

+#define OCTOSPI_HLCR_LM_Msk            (0x1UL << OCTOSPI_HLCR_LM_Pos)           /*!< 0x00000001 */

+#define OCTOSPI_HLCR_LM                OCTOSPI_HLCR_LM_Msk                     /*!< Latency Mode */

+#define OCTOSPI_HLCR_WZL_Pos           (1U)

+#define OCTOSPI_HLCR_WZL_Msk           (0x1UL << OCTOSPI_HLCR_WZL_Pos)          /*!< 0x00000002 */

+#define OCTOSPI_HLCR_WZL               OCTOSPI_HLCR_WZL_Msk                    /*!< Write Zero Latency */

+#define OCTOSPI_HLCR_TACC_Pos          (8U)

+#define OCTOSPI_HLCR_TACC_Msk          (0xFFUL << OCTOSPI_HLCR_TACC_Pos)        /*!< 0x0000FF00 */

+#define OCTOSPI_HLCR_TACC              OCTOSPI_HLCR_TACC_Msk                   /*!< Access Time */

+#define OCTOSPI_HLCR_TRWR_Pos          (16U)

+#define OCTOSPI_HLCR_TRWR_Msk          (0xFFUL << OCTOSPI_HLCR_TRWR_Pos)        /*!< 0x00FF0000 */

+#define OCTOSPI_HLCR_TRWR              OCTOSPI_HLCR_TRWR_Msk                   /*!< Read Write Recovery Time */

+

+/****************  Bit definition for OCTOSPI_VER register  *******************/

+#define OCTOSPI_VER_VER_Pos            (0U)

+#define OCTOSPI_VER_VER_Msk            (0xFFUL << OCTOSPI_VER_VER_Pos)          /*!< 0x000000FF */

+#define OCTOSPI_VER_VER                OCTOSPI_VER_VER_Msk                     /*!< Version */

+

+/*****************  Bit definition for OCTOSPI_ID register  *******************/

+#define OCTOSPI_ID_ID_Pos              (0U)

+#define OCTOSPI_ID_ID_Msk              (0xFFFFFFFFUL << OCTOSPI_ID_ID_Pos)      /*!< 0xFFFFFFFF */

+#define OCTOSPI_ID_ID                  OCTOSPI_ID_ID_Msk                       /*!< Identification */

+

+/****************  Bit definition for OCTOSPI_MID register  *******************/

+#define OCTOSPI_MID_MID_Pos            (0U)

+#define OCTOSPI_MID_MID_Msk            (0xFFFFFFFFUL << OCTOSPI_MID_MID_Pos)    /*!< 0xFFFFFFFF */

+#define OCTOSPI_MID_MID                OCTOSPI_MID_MID_Msk                     /*!< Magic ID */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                  OCTOSPIM                                  */

+/*                                                                            */

+/******************************************************************************/

+

+/***************  Bit definition for OCTOSPIM_CR register  ********************/

+#define OCTOSPIM_CR_MUXEN_Pos          (0U)

+#define OCTOSPIM_CR_MUXEN_Msk          (0x1UL << OCTOSPIM_CR_MUXEN_Pos)        /*!< 0x00000001 */

+#define OCTOSPIM_CR_MUXEN              OCTOSPIM_CR_MUXEN_Msk                   /*!< Multiplexed mode enable */

+#define OCTOSPIM_CR_REQ2ACK_TIME_Pos   (16U)

+#define OCTOSPIM_CR_REQ2ACK_TIME_Msk   (0xFFUL << OCTOSPIM_CR_REQ2ACK_TIME_Pos)/*!< 0x00FF0000 */

+#define OCTOSPIM_CR_REQ2ACK_TIME       OCTOSPIM_CR_REQ2ACK_TIME_Msk            /*!< REQ to ACK time */

+

+/***************  Bit definition for OCTOSPIM_PCR register  *******************/

+#define OCTOSPIM_PCR_CLKEN_Pos         (0U)

+#define OCTOSPIM_PCR_CLKEN_Msk         (0x1UL << OCTOSPIM_PCR_CLKEN_Pos)        /*!< 0x00000001 */

+#define OCTOSPIM_PCR_CLKEN             OCTOSPIM_PCR_CLKEN_Msk                   /*!< CLK/CLKn Enable for Port n */

+#define OCTOSPIM_PCR_CLKSRC_Pos        (1U)

+#define OCTOSPIM_PCR_CLKSRC_Msk        (0x1UL << OCTOSPIM_PCR_CLKSRC_Pos)       /*!< 0x00000002 */

+#define OCTOSPIM_PCR_CLKSRC            OCTOSPIM_PCR_CLKSRC_Msk                  /*!< CLK/CLKn Source for Port n */

+#define OCTOSPIM_PCR_DQSEN_Pos         (4U)

+#define OCTOSPIM_PCR_DQSEN_Msk         (0x1UL << OCTOSPIM_PCR_DQSEN_Pos)        /*!< 0x00000010 */

+#define OCTOSPIM_PCR_DQSEN             OCTOSPIM_PCR_DQSEN_Msk                   /*!< DQS Enable for Port n */

+#define OCTOSPIM_PCR_DQSSRC_Pos        (5U)

+#define OCTOSPIM_PCR_DQSSRC_Msk        (0x1UL << OCTOSPIM_PCR_DQSSRC_Pos)       /*!< 0x00000020 */

+#define OCTOSPIM_PCR_DQSSRC            OCTOSPIM_PCR_DQSSRC_Msk                  /*!< DQS Source for Port n */

+#define OCTOSPIM_PCR_NCSEN_Pos         (8U)

+#define OCTOSPIM_PCR_NCSEN_Msk         (0x1UL << OCTOSPIM_PCR_NCSEN_Pos)        /*!< 0x00000100 */

+#define OCTOSPIM_PCR_NCSEN             OCTOSPIM_PCR_NCSEN_Msk                   /*!< nCS Enable for Port n */

+#define OCTOSPIM_PCR_NCSSRC_Pos        (9U)

+#define OCTOSPIM_PCR_NCSSRC_Msk        (0x1UL << OCTOSPIM_PCR_NCSSRC_Pos)       /*!< 0x00000200 */

+#define OCTOSPIM_PCR_NCSSRC            OCTOSPIM_PCR_NCSSRC_Msk                  /*!< nCS Source for Port n */

+#define OCTOSPIM_PCR_IOLEN_Pos         (16U)

+#define OCTOSPIM_PCR_IOLEN_Msk         (0x1UL << OCTOSPIM_PCR_IOLEN_Pos)        /*!< 0x00010000 */

+#define OCTOSPIM_PCR_IOLEN             OCTOSPIM_PCR_IOLEN_Msk                   /*!< IO[3:0] Enable for Port n */

+#define OCTOSPIM_PCR_IOLSRC_Pos        (17U)

+#define OCTOSPIM_PCR_IOLSRC_Msk        (0x3UL << OCTOSPIM_PCR_IOLSRC_Pos)       /*!< 0x00060000 */

+#define OCTOSPIM_PCR_IOLSRC            OCTOSPIM_PCR_IOLSRC_Msk                  /*!< IO[3:0] Source for Port n */

+#define OCTOSPIM_PCR_IOLSRC_0          (0x1UL << OCTOSPIM_PCR_IOLSRC_Pos)       /*!< 0x00020000 */

+#define OCTOSPIM_PCR_IOLSRC_1          (0x2UL << OCTOSPIM_PCR_IOLSRC_Pos)       /*!< 0x00040000 */

+#define OCTOSPIM_PCR_IOHEN_Pos         (24U)

+#define OCTOSPIM_PCR_IOHEN_Msk         (0x1UL << OCTOSPIM_PCR_IOHEN_Pos)        /*!< 0x01000000 */

+#define OCTOSPIM_PCR_IOHEN             OCTOSPIM_PCR_IOHEN_Msk                   /*!< IO[7:4] Enable for Port n */

+#define OCTOSPIM_PCR_IOHSRC_Pos        (25U)

+#define OCTOSPIM_PCR_IOHSRC_Msk        (0x3UL << OCTOSPIM_PCR_IOHSRC_Pos)       /*!< 0x06000000 */

+#define OCTOSPIM_PCR_IOHSRC            OCTOSPIM_PCR_IOHSRC_Msk                  /*!< IO[7:4] Source for Port n */

+#define OCTOSPIM_PCR_IOHSRC_0          (0x1UL << OCTOSPIM_PCR_IOHSRC_Pos)       /*!< 0x02000000 */

+#define OCTOSPIM_PCR_IOHSRC_1          (0x2UL << OCTOSPIM_PCR_IOHSRC_Pos)       /*!< 0x04000000 */

+/******************************************************************************/

+/*                                                                            */

+/*                      Analog Comparators (COMP)                             */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for COMP_SR register  ********************/

+#define COMP_SR_C1VAL_Pos            (0U)

+#define COMP_SR_C1VAL_Msk            (0x1UL << COMP_SR_C1VAL_Pos)              /*!< 0x00000001 */

+#define COMP_SR_C1VAL                COMP_SR_C1VAL_Msk

+#define COMP_SR_C2VAL_Pos            (1U)

+#define COMP_SR_C2VAL_Msk            (0x1UL << COMP_SR_C2VAL_Pos)              /*!< 0x00000002 */

+#define COMP_SR_C2VAL                COMP_SR_C2VAL_Msk

+#define COMP_SR_C1IF_Pos             (16U)

+#define COMP_SR_C1IF_Msk             (0x1UL << COMP_SR_C1IF_Pos)               /*!< 0x00010000 */

+#define COMP_SR_C1IF                 COMP_SR_C1IF_Msk

+#define COMP_SR_C2IF_Pos             (17U)

+#define COMP_SR_C2IF_Msk             (0x1UL << COMP_SR_C2IF_Pos)               /*!< 0x00020000 */

+#define COMP_SR_C2IF                 COMP_SR_C2IF_Msk

+/*******************  Bit definition for COMP_ICFR register  ********************/

+#define COMP_ICFR_C1IF_Pos           (16U)

+#define COMP_ICFR_C1IF_Msk           (0x1UL << COMP_ICFR_C1IF_Pos)             /*!< 0x00010000 */

+#define COMP_ICFR_C1IF               COMP_ICFR_C1IF_Msk

+#define COMP_ICFR_C2IF_Pos           (17U)

+#define COMP_ICFR_C2IF_Msk           (0x1UL << COMP_ICFR_C2IF_Pos)             /*!< 0x00020000 */

+#define COMP_ICFR_C2IF               COMP_ICFR_C2IF_Msk

+/*******************  Bit definition for COMP_OR register  ********************/

+#define COMP_OR_AFOPA6_Pos           (0U)

+#define COMP_OR_AFOPA6_Msk           (0x1UL << COMP_OR_AFOPA6_Pos)             /*!< 0x00000001 */

+#define COMP_OR_AFOPA6               COMP_OR_AFOPA6_Msk

+#define COMP_OR_AFOPA8_Pos           (1U)

+#define COMP_OR_AFOPA8_Msk           (0x1UL << COMP_OR_AFOPA8_Pos)             /*!< 0x00000002 */

+#define COMP_OR_AFOPA8               COMP_OR_AFOPA8_Msk

+#define COMP_OR_AFOPB12_Pos          (2U)

+#define COMP_OR_AFOPB12_Msk          (0x1UL << COMP_OR_AFOPB12_Pos)            /*!< 0x00000004 */

+#define COMP_OR_AFOPB12              COMP_OR_AFOPB12_Msk

+#define COMP_OR_AFOPE6_Pos           (3U)

+#define COMP_OR_AFOPE6_Msk           (0x1UL << COMP_OR_AFOPE6_Pos)             /*!< 0x00000008 */

+#define COMP_OR_AFOPE6               COMP_OR_AFOPE6_Msk

+#define COMP_OR_AFOPE15_Pos          (4U)

+#define COMP_OR_AFOPE15_Msk          (0x1UL << COMP_OR_AFOPE15_Pos)            /*!< 0x00000010 */

+#define COMP_OR_AFOPE15              COMP_OR_AFOPE15_Msk

+#define COMP_OR_AFOPG2_Pos           (5U)

+#define COMP_OR_AFOPG2_Msk           (0x1UL << COMP_OR_AFOPG2_Pos)             /*!< 0x00000020 */

+#define COMP_OR_AFOPG2               COMP_OR_AFOPG2_Msk

+#define COMP_OR_AFOPG3_Pos           (6U)

+#define COMP_OR_AFOPG3_Msk           (0x1UL << COMP_OR_AFOPG3_Pos)             /*!< 0x00000040 */

+#define COMP_OR_AFOPG3               COMP_OR_AFOPG3_Msk

+#define COMP_OR_AFOPG4_Pos           (7U)

+#define COMP_OR_AFOPG4_Msk           (0x1UL << COMP_OR_AFOPG4_Pos)             /*!< 0x00000080 */

+#define COMP_OR_AFOPG4               COMP_OR_AFOPG4_Msk

+#define COMP_OR_AFOPI1_Pos           (8U)

+#define COMP_OR_AFOPI1_Msk           (0x1UL << COMP_OR_AFOPI1_Pos)             /*!< 0x00000100 */

+#define COMP_OR_AFOPI1               COMP_OR_AFOPI1_Msk

+#define COMP_OR_AFOPI4_Pos           (9U)

+#define COMP_OR_AFOPI4_Msk           (0x1UL << COMP_OR_AFOPI4_Pos)             /*!< 0x00000200 */

+#define COMP_OR_AFOPI4               COMP_OR_AFOPI4_Msk

+#define COMP_OR_AFOPK2_Pos           (10U)

+#define COMP_OR_AFOPK2_Msk           (0x1UL << COMP_OR_AFOPK2_Pos)             /*!< 0x00000400 */

+#define COMP_OR_AFOPK2               COMP_OR_AFOPK2_Msk

+

+/*!< ******************  Bit definition for COMP_CFGRx register  ********************/

+#define COMP_CFGRx_EN_Pos            (0U)

+#define COMP_CFGRx_EN_Msk            (0x1UL << COMP_CFGRx_EN_Pos)              /*!< 0x00000001 */

+#define COMP_CFGRx_EN                COMP_CFGRx_EN_Msk                         /*!< COMPx enable bit                     */

+#define COMP_CFGRx_BRGEN_Pos         (1U)

+#define COMP_CFGRx_BRGEN_Msk         (0x1UL << COMP_CFGRx_BRGEN_Pos)           /*!< 0x00000002 */

+#define COMP_CFGRx_BRGEN             COMP_CFGRx_BRGEN_Msk                      /*!< COMPx Scaler bridge enable           */

+#define COMP_CFGRx_SCALEN_Pos        (2U)

+#define COMP_CFGRx_SCALEN_Msk        (0x1UL << COMP_CFGRx_SCALEN_Pos)          /*!< 0x00000004 */

+#define COMP_CFGRx_SCALEN            COMP_CFGRx_SCALEN_Msk                     /*!< COMPx Voltage scaler enable bit      */

+#define COMP_CFGRx_POLARITY_Pos      (3U)

+#define COMP_CFGRx_POLARITY_Msk      (0x1UL << COMP_CFGRx_POLARITY_Pos)        /*!< 0x00000008 */

+#define COMP_CFGRx_POLARITY          COMP_CFGRx_POLARITY_Msk                   /*!< COMPx  polarity selection bit        */

+#define COMP_CFGRx_WINMODE_Pos       (4U)

+#define COMP_CFGRx_WINMODE_Msk       (0x1UL << COMP_CFGRx_WINMODE_Pos)         /*!< 0x00000010 */

+#define COMP_CFGRx_WINMODE           COMP_CFGRx_WINMODE_Msk                    /*!< COMPx Windows mode selection bit     */

+#define COMP_CFGRx_ITEN_Pos          (6U)

+#define COMP_CFGRx_ITEN_Msk          (0x1UL << COMP_CFGRx_ITEN_Pos)            /*!< 0x00000040 */

+#define COMP_CFGRx_ITEN              COMP_CFGRx_ITEN_Msk                       /*!< COMPx  interrupt enable              */

+#define COMP_CFGRx_HYST_Pos          (8U)

+#define COMP_CFGRx_HYST_Msk          (0x3UL << COMP_CFGRx_HYST_Pos)            /*!< 0x00000300 */

+#define COMP_CFGRx_HYST              COMP_CFGRx_HYST_Msk                       /*!< COMPx  hysteresis selection bits     */

+#define COMP_CFGRx_HYST_0            (0x1UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000100 */

+#define COMP_CFGRx_HYST_1            (0x2UL << COMP_CFGRx_HYST_Pos)             /*!< 0x00000200 */

+#define COMP_CFGRx_PWRMODE_Pos       (12U)

+#define COMP_CFGRx_PWRMODE_Msk       (0x3UL << COMP_CFGRx_PWRMODE_Pos)         /*!< 0x00003000 */

+#define COMP_CFGRx_PWRMODE           COMP_CFGRx_PWRMODE_Msk                    /*!< COMPx Power Mode of the comparator   */

+#define COMP_CFGRx_PWRMODE_0         (0x1UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00001000 */

+#define COMP_CFGRx_PWRMODE_1         (0x2UL << COMP_CFGRx_PWRMODE_Pos)          /*!< 0x00002000 */

+#define COMP_CFGRx_INMSEL_Pos        (16U)

+#define COMP_CFGRx_INMSEL_Msk        (0xFUL << COMP_CFGRx_INMSEL_Pos)          /*!< 0x000F0000 */

+#define COMP_CFGRx_INMSEL            COMP_CFGRx_INMSEL_Msk                     /*!< COMPx  input minus selection bit  */

+#define COMP_CFGRx_INMSEL_0          (0x1UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00010000 */

+#define COMP_CFGRx_INMSEL_1          (0x2UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00020000 */

+#define COMP_CFGRx_INMSEL_2          (0x4UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00040000 */

+#define COMP_CFGRx_INMSEL_3          (0x8UL << COMP_CFGRx_INMSEL_Pos)           /*!< 0x00080000 */

+#define COMP_CFGRx_INPSEL_Pos        (20U)

+#define COMP_CFGRx_INPSEL_Msk        (0x1UL << COMP_CFGRx_INPSEL_Pos)          /*!< 0x00100000 */

+#define COMP_CFGRx_INPSEL            COMP_CFGRx_INPSEL_Msk                     /*!< COMPx  input plus selection bit       */

+#define COMP_CFGRx_INP2SEL_Pos        (22U)

+#define COMP_CFGRx_INP2SEL_Msk        (0x1UL << COMP_CFGRx_INP2SEL_Pos)        /*!< 0x00400000 */

+#define COMP_CFGRx_INP2SEL            COMP_CFGRx_INP2SEL_Msk                   /*!< COMPx  input plus 2 selection bit     */

+#define COMP_CFGRx_BLANKING_Pos      (24U)

+#define COMP_CFGRx_BLANKING_Msk      (0xFUL << COMP_CFGRx_BLANKING_Pos)        /*!< 0x0F000000 */

+#define COMP_CFGRx_BLANKING          COMP_CFGRx_BLANKING_Msk                   /*!< COMPx  blanking source selection bits */

+#define COMP_CFGRx_BLANKING_0        (0x1UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x01000000 */

+#define COMP_CFGRx_BLANKING_1        (0x2UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x02000000 */

+#define COMP_CFGRx_BLANKING_2        (0x4UL << COMP_CFGRx_BLANKING_Pos)         /*!< 0x04000000 */

+#define COMP_CFGRx_LOCK_Pos          (31U)

+#define COMP_CFGRx_LOCK_Msk          (0x1UL << COMP_CFGRx_LOCK_Pos)            /*!< 0x80000000 */

+#define COMP_CFGRx_LOCK              COMP_CFGRx_LOCK_Msk                       /*!< COMPx Lock Bit                        */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for USART_CR1 register  *******************/

+#define USART_CR1_UE_Pos                (0U)

+#define USART_CR1_UE_Msk                (0x1UL << USART_CR1_UE_Pos)            /*!< 0x00000001 */

+#define USART_CR1_UE                    USART_CR1_UE_Msk                       /*!< USART Enable */

+#define USART_CR1_UESM_Pos              (1U)

+#define USART_CR1_UESM_Msk              (0x1UL << USART_CR1_UESM_Pos)          /*!< 0x00000002 */

+#define USART_CR1_UESM                  USART_CR1_UESM_Msk                     /*!< USART Enable in STOP Mode */

+#define USART_CR1_RE_Pos                (2U)

+#define USART_CR1_RE_Msk                (0x1UL << USART_CR1_RE_Pos)            /*!< 0x00000004 */

+#define USART_CR1_RE                    USART_CR1_RE_Msk                       /*!< Receiver Enable */

+#define USART_CR1_TE_Pos                (3U)

+#define USART_CR1_TE_Msk                (0x1UL << USART_CR1_TE_Pos)            /*!< 0x00000008 */

+#define USART_CR1_TE                    USART_CR1_TE_Msk                       /*!< Transmitter Enable */

+#define USART_CR1_IDLEIE_Pos            (4U)

+#define USART_CR1_IDLEIE_Msk            (0x1UL << USART_CR1_IDLEIE_Pos)        /*!< 0x00000010 */

+#define USART_CR1_IDLEIE                USART_CR1_IDLEIE_Msk                   /*!< IDLE Interrupt Enable */

+#define USART_CR1_RXNEIE_RXFNEIE_Pos    (5U)

+#define USART_CR1_RXNEIE_RXFNEIE_Msk    (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */

+#define USART_CR1_RXNEIE_RXFNEIE        USART_CR1_RXNEIE_RXFNEIE_Msk           /*!< RXNE and RX FIFO Not Empty Interrupt Enable */

+#define USART_CR1_TCIE_Pos              (6U)

+#define USART_CR1_TCIE_Msk              (0x1UL << USART_CR1_TCIE_Pos)          /*!< 0x00000040 */

+#define USART_CR1_TCIE                  USART_CR1_TCIE_Msk                     /*!< Transmission Complete Interrupt Enable */

+#define USART_CR1_TXEIE_TXFNFIE_Pos     (7U)

+#define USART_CR1_TXEIE_TXFNFIE_Msk     (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */

+#define USART_CR1_TXEIE_TXFNFIE         USART_CR1_TXEIE_TXFNFIE_Msk            /*!< TXE and TX FIFO Not Full Interrupt Enable */

+#define USART_CR1_PEIE_Pos              (8U)

+#define USART_CR1_PEIE_Msk              (0x1UL << USART_CR1_PEIE_Pos)          /*!< 0x00000100 */

+#define USART_CR1_PEIE                  USART_CR1_PEIE_Msk                     /*!< PE Interrupt Enable */

+#define USART_CR1_PS_Pos                (9U)

+#define USART_CR1_PS_Msk                (0x1UL << USART_CR1_PS_Pos)            /*!< 0x00000200 */

+#define USART_CR1_PS                    USART_CR1_PS_Msk                       /*!< Parity Selection */

+#define USART_CR1_PCE_Pos               (10U)

+#define USART_CR1_PCE_Msk               (0x1UL << USART_CR1_PCE_Pos)           /*!< 0x00000400 */

+#define USART_CR1_PCE                   USART_CR1_PCE_Msk                      /*!< Parity Control Enable */

+#define USART_CR1_WAKE_Pos              (11U)

+#define USART_CR1_WAKE_Msk              (0x1UL << USART_CR1_WAKE_Pos)          /*!< 0x00000800 */

+#define USART_CR1_WAKE                  USART_CR1_WAKE_Msk                     /*!< Receiver Wakeup method */

+#define USART_CR1_M_Pos                 (12U)

+#define USART_CR1_M_Msk                 (0x10001UL << USART_CR1_M_Pos)         /*!< 0x10001000 */

+#define USART_CR1_M                     USART_CR1_M_Msk                        /*!< Word length */

+#define USART_CR1_M0_Pos                (12U)

+#define USART_CR1_M0_Msk                (0x1UL << USART_CR1_M0_Pos)            /*!< 0x00001000 */

+#define USART_CR1_M0                    USART_CR1_M0_Msk                       /*!< Word length - Bit 0 */

+#define USART_CR1_MME_Pos               (13U)

+#define USART_CR1_MME_Msk               (0x1UL << USART_CR1_MME_Pos)           /*!< 0x00002000 */

+#define USART_CR1_MME                   USART_CR1_MME_Msk                      /*!< Mute Mode Enable */

+#define USART_CR1_CMIE_Pos              (14U)

+#define USART_CR1_CMIE_Msk              (0x1UL << USART_CR1_CMIE_Pos)          /*!< 0x00004000 */

+#define USART_CR1_CMIE                  USART_CR1_CMIE_Msk                     /*!< Character match interrupt enable */

+#define USART_CR1_OVER8_Pos             (15U)

+#define USART_CR1_OVER8_Msk             (0x1UL << USART_CR1_OVER8_Pos)         /*!< 0x00008000 */

+#define USART_CR1_OVER8                 USART_CR1_OVER8_Msk                    /*!< Oversampling by 8-bit or 16-bit mode */

+#define USART_CR1_DEDT_Pos              (16U)

+#define USART_CR1_DEDT_Msk              (0x1FUL << USART_CR1_DEDT_Pos)         /*!< 0x001F0000 */

+#define USART_CR1_DEDT                  USART_CR1_DEDT_Msk                     /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */

+#define USART_CR1_DEDT_0                (0x01UL << USART_CR1_DEDT_Pos)          /*!< 0x00010000 */

+#define USART_CR1_DEDT_1                (0x02UL << USART_CR1_DEDT_Pos)          /*!< 0x00020000 */

+#define USART_CR1_DEDT_2                (0x04UL << USART_CR1_DEDT_Pos)          /*!< 0x00040000 */

+#define USART_CR1_DEDT_3                (0x08UL << USART_CR1_DEDT_Pos)          /*!< 0x00080000 */

+#define USART_CR1_DEDT_4                (0x10UL << USART_CR1_DEDT_Pos)          /*!< 0x00100000 */

+#define USART_CR1_DEAT_Pos              (21U)

+#define USART_CR1_DEAT_Msk              (0x1FUL << USART_CR1_DEAT_Pos)         /*!< 0x03E00000 */

+#define USART_CR1_DEAT                  USART_CR1_DEAT_Msk                     /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */

+#define USART_CR1_DEAT_0                (0x01UL << USART_CR1_DEAT_Pos)          /*!< 0x00200000 */

+#define USART_CR1_DEAT_1                (0x02UL << USART_CR1_DEAT_Pos)          /*!< 0x00400000 */

+#define USART_CR1_DEAT_2                (0x04UL << USART_CR1_DEAT_Pos)          /*!< 0x00800000 */

+#define USART_CR1_DEAT_3                (0x08UL << USART_CR1_DEAT_Pos)          /*!< 0x01000000 */

+#define USART_CR1_DEAT_4                (0x10UL << USART_CR1_DEAT_Pos)          /*!< 0x02000000 */

+#define USART_CR1_RTOIE_Pos             (26U)

+#define USART_CR1_RTOIE_Msk             (0x1UL << USART_CR1_RTOIE_Pos)         /*!< 0x04000000 */

+#define USART_CR1_RTOIE                 USART_CR1_RTOIE_Msk                    /*!< Receive Time Out interrupt enable */

+#define USART_CR1_EOBIE_Pos             (27U)

+#define USART_CR1_EOBIE_Msk             (0x1UL << USART_CR1_EOBIE_Pos)         /*!< 0x08000000 */

+#define USART_CR1_EOBIE                 USART_CR1_EOBIE_Msk                    /*!< End of Block interrupt enable */

+#define USART_CR1_M1_Pos                (28U)

+#define USART_CR1_M1_Msk                (0x1UL << USART_CR1_M1_Pos)            /*!< 0x10000000 */

+#define USART_CR1_M1                    USART_CR1_M1_Msk                       /*!< Word length - Bit 1 */

+#define USART_CR1_FIFOEN_Pos            (29U)

+#define USART_CR1_FIFOEN_Msk            (0x1UL << USART_CR1_FIFOEN_Pos)        /*!< 0x20000000 */

+#define USART_CR1_FIFOEN                USART_CR1_FIFOEN_Msk                   /*!< FIFO mode enable */

+#define USART_CR1_TXFEIE_Pos            (30U)

+#define USART_CR1_TXFEIE_Msk            (0x1UL << USART_CR1_TXFEIE_Pos)        /*!< 0x40000000 */

+#define USART_CR1_TXFEIE                USART_CR1_TXFEIE_Msk                   /*!< TXFIFO empty interrupt enable */

+#define USART_CR1_RXFFIE_Pos            (31U)

+#define USART_CR1_RXFFIE_Msk            (0x1UL << USART_CR1_RXFFIE_Pos)        /*!< 0x80000000 */

+#define USART_CR1_RXFFIE                USART_CR1_RXFFIE_Msk                   /*!< RXFIFO Full interrupt enable */

+

+/* Legacy define */

+#define  USART_CR1_RXNEIE  USART_CR1_RXNEIE_RXFNEIE

+#define  USART_CR1_TXEIE   USART_CR1_TXEIE_TXFNFIE

+

+/******************  Bit definition for USART_CR2 register  *******************/

+#define USART_CR2_SLVEN_Pos             (0U)

+#define USART_CR2_SLVEN_Msk             (0x1UL << USART_CR2_SLVEN_Pos)         /*!< 0x00000001 */

+#define USART_CR2_SLVEN                 USART_CR2_SLVEN_Msk                    /*!< Synchronous Slave mode Enable */

+#define USART_CR2_DIS_NSS_Pos           (3U)

+#define USART_CR2_DIS_NSS_Msk           (0x1UL << USART_CR2_DIS_NSS_Pos)       /*!< 0x00000008 */

+#define USART_CR2_DIS_NSS               USART_CR2_DIS_NSS_Msk                  /*!< Negative Slave Select (NSS) pin management */

+#define USART_CR2_ADDM7_Pos             (4U)

+#define USART_CR2_ADDM7_Msk             (0x1UL << USART_CR2_ADDM7_Pos)         /*!< 0x00000010 */

+#define USART_CR2_ADDM7                 USART_CR2_ADDM7_Msk                    /*!< 7-bit or 4-bit Address Detection */

+#define USART_CR2_LBDL_Pos              (5U)

+#define USART_CR2_LBDL_Msk              (0x1UL << USART_CR2_LBDL_Pos)          /*!< 0x00000020 */

+#define USART_CR2_LBDL                  USART_CR2_LBDL_Msk                     /*!< LIN Break Detection Length */

+#define USART_CR2_LBDIE_Pos             (6U)

+#define USART_CR2_LBDIE_Msk             (0x1UL << USART_CR2_LBDIE_Pos)         /*!< 0x00000040 */

+#define USART_CR2_LBDIE                 USART_CR2_LBDIE_Msk                    /*!< LIN Break Detection Interrupt Enable */

+#define USART_CR2_LBCL_Pos              (8U)

+#define USART_CR2_LBCL_Msk              (0x1UL << USART_CR2_LBCL_Pos)          /*!< 0x00000100 */

+#define USART_CR2_LBCL                  USART_CR2_LBCL_Msk                     /*!< Last Bit Clock pulse */

+#define USART_CR2_CPHA_Pos              (9U)

+#define USART_CR2_CPHA_Msk              (0x1UL << USART_CR2_CPHA_Pos)          /*!< 0x00000200 */

+#define USART_CR2_CPHA                  USART_CR2_CPHA_Msk                     /*!< Clock Phase */

+#define USART_CR2_CPOL_Pos              (10U)

+#define USART_CR2_CPOL_Msk              (0x1UL << USART_CR2_CPOL_Pos)          /*!< 0x00000400 */

+#define USART_CR2_CPOL                  USART_CR2_CPOL_Msk                     /*!< Clock Polarity */

+#define USART_CR2_CLKEN_Pos             (11U)

+#define USART_CR2_CLKEN_Msk             (0x1UL << USART_CR2_CLKEN_Pos)         /*!< 0x00000800 */

+#define USART_CR2_CLKEN                 USART_CR2_CLKEN_Msk                    /*!< Clock Enable */

+#define USART_CR2_STOP_Pos              (12U)

+#define USART_CR2_STOP_Msk              (0x3UL << USART_CR2_STOP_Pos)          /*!< 0x00003000 */

+#define USART_CR2_STOP                  USART_CR2_STOP_Msk                     /*!< STOP[1:0] bits (STOP bits) */

+#define USART_CR2_STOP_0                (0x1UL << USART_CR2_STOP_Pos)           /*!< 0x00001000 */

+#define USART_CR2_STOP_1                (0x2UL << USART_CR2_STOP_Pos)           /*!< 0x00002000 */

+#define USART_CR2_LINEN_Pos             (14U)

+#define USART_CR2_LINEN_Msk             (0x1UL << USART_CR2_LINEN_Pos)         /*!< 0x00004000 */

+#define USART_CR2_LINEN                 USART_CR2_LINEN_Msk                    /*!< LIN mode enable */

+#define USART_CR2_SWAP_Pos              (15U)

+#define USART_CR2_SWAP_Msk              (0x1UL << USART_CR2_SWAP_Pos)          /*!< 0x00008000 */

+#define USART_CR2_SWAP                  USART_CR2_SWAP_Msk                     /*!< SWAP TX/RX pins */

+#define USART_CR2_RXINV_Pos             (16U)

+#define USART_CR2_RXINV_Msk             (0x1UL << USART_CR2_RXINV_Pos)         /*!< 0x00010000 */

+#define USART_CR2_RXINV                 USART_CR2_RXINV_Msk                    /*!< RX pin active level inversion */

+#define USART_CR2_TXINV_Pos             (17U)

+#define USART_CR2_TXINV_Msk             (0x1UL << USART_CR2_TXINV_Pos)         /*!< 0x00020000 */

+#define USART_CR2_TXINV                 USART_CR2_TXINV_Msk                    /*!< TX pin active level inversion */

+#define USART_CR2_DATAINV_Pos           (18U)

+#define USART_CR2_DATAINV_Msk           (0x1UL << USART_CR2_DATAINV_Pos)       /*!< 0x00040000 */

+#define USART_CR2_DATAINV               USART_CR2_DATAINV_Msk                  /*!< Binary data inversion */

+#define USART_CR2_MSBFIRST_Pos          (19U)

+#define USART_CR2_MSBFIRST_Msk          (0x1UL << USART_CR2_MSBFIRST_Pos)      /*!< 0x00080000 */

+#define USART_CR2_MSBFIRST              USART_CR2_MSBFIRST_Msk                 /*!< Most Significant Bit First */

+#define USART_CR2_ABREN_Pos             (20U)

+#define USART_CR2_ABREN_Msk             (0x1UL << USART_CR2_ABREN_Pos)         /*!< 0x00100000 */

+#define USART_CR2_ABREN                 USART_CR2_ABREN_Msk                    /*!< Auto Baud-Rate Enable*/

+#define USART_CR2_ABRMODE_Pos           (21U)

+#define USART_CR2_ABRMODE_Msk           (0x3UL << USART_CR2_ABRMODE_Pos)       /*!< 0x00600000 */

+#define USART_CR2_ABRMODE               USART_CR2_ABRMODE_Msk                  /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */

+#define USART_CR2_ABRMODE_0             (0x1UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00200000 */

+#define USART_CR2_ABRMODE_1             (0x2UL << USART_CR2_ABRMODE_Pos)        /*!< 0x00400000 */

+#define USART_CR2_RTOEN_Pos             (23U)

+#define USART_CR2_RTOEN_Msk             (0x1UL << USART_CR2_RTOEN_Pos)         /*!< 0x00800000 */

+#define USART_CR2_RTOEN                 USART_CR2_RTOEN_Msk                    /*!< Receiver Time-Out enable */

+#define USART_CR2_ADD_Pos               (24U)

+#define USART_CR2_ADD_Msk               (0xFFUL << USART_CR2_ADD_Pos)          /*!< 0xFF000000 */

+#define USART_CR2_ADD                   USART_CR2_ADD_Msk                      /*!< Address of the USART node */

+

+/******************  Bit definition for USART_CR3 register  *******************/

+#define USART_CR3_EIE_Pos               (0U)

+#define USART_CR3_EIE_Msk               (0x1UL << USART_CR3_EIE_Pos)           /*!< 0x00000001 */

+#define USART_CR3_EIE                   USART_CR3_EIE_Msk                      /*!< Error Interrupt Enable */

+#define USART_CR3_IREN_Pos              (1U)

+#define USART_CR3_IREN_Msk              (0x1UL << USART_CR3_IREN_Pos)          /*!< 0x00000002 */

+#define USART_CR3_IREN                  USART_CR3_IREN_Msk                     /*!< IrDA mode Enable */

+#define USART_CR3_IRLP_Pos              (2U)

+#define USART_CR3_IRLP_Msk              (0x1UL << USART_CR3_IRLP_Pos)          /*!< 0x00000004 */

+#define USART_CR3_IRLP                  USART_CR3_IRLP_Msk                     /*!< IrDA Low-Power */

+#define USART_CR3_HDSEL_Pos             (3U)

+#define USART_CR3_HDSEL_Msk             (0x1UL << USART_CR3_HDSEL_Pos)         /*!< 0x00000008 */

+#define USART_CR3_HDSEL                 USART_CR3_HDSEL_Msk                    /*!< Half-Duplex Selection */

+#define USART_CR3_NACK_Pos              (4U)

+#define USART_CR3_NACK_Msk              (0x1UL << USART_CR3_NACK_Pos)          /*!< 0x00000010 */

+#define USART_CR3_NACK                  USART_CR3_NACK_Msk                     /*!< SmartCard NACK enable */

+#define USART_CR3_SCEN_Pos              (5U)

+#define USART_CR3_SCEN_Msk              (0x1UL << USART_CR3_SCEN_Pos)          /*!< 0x00000020 */

+#define USART_CR3_SCEN                  USART_CR3_SCEN_Msk                     /*!< SmartCard mode enable */

+#define USART_CR3_DMAR_Pos              (6U)

+#define USART_CR3_DMAR_Msk              (0x1UL << USART_CR3_DMAR_Pos)          /*!< 0x00000040 */

+#define USART_CR3_DMAR                  USART_CR3_DMAR_Msk                     /*!< DMA Enable Receiver */

+#define USART_CR3_DMAT_Pos              (7U)

+#define USART_CR3_DMAT_Msk              (0x1UL << USART_CR3_DMAT_Pos)          /*!< 0x00000080 */

+#define USART_CR3_DMAT                  USART_CR3_DMAT_Msk                     /*!< DMA Enable Transmitter */

+#define USART_CR3_RTSE_Pos              (8U)

+#define USART_CR3_RTSE_Msk              (0x1UL << USART_CR3_RTSE_Pos)          /*!< 0x00000100 */

+#define USART_CR3_RTSE                  USART_CR3_RTSE_Msk                     /*!< RTS Enable */

+#define USART_CR3_CTSE_Pos              (9U)

+#define USART_CR3_CTSE_Msk              (0x1UL << USART_CR3_CTSE_Pos)          /*!< 0x00000200 */

+#define USART_CR3_CTSE                  USART_CR3_CTSE_Msk                     /*!< CTS Enable */

+#define USART_CR3_CTSIE_Pos             (10U)

+#define USART_CR3_CTSIE_Msk             (0x1UL << USART_CR3_CTSIE_Pos)         /*!< 0x00000400 */

+#define USART_CR3_CTSIE                 USART_CR3_CTSIE_Msk                    /*!< CTS Interrupt Enable */

+#define USART_CR3_ONEBIT_Pos            (11U)

+#define USART_CR3_ONEBIT_Msk            (0x1UL << USART_CR3_ONEBIT_Pos)        /*!< 0x00000800 */

+#define USART_CR3_ONEBIT                USART_CR3_ONEBIT_Msk                   /*!< One sample bit method enable */

+#define USART_CR3_OVRDIS_Pos            (12U)

+#define USART_CR3_OVRDIS_Msk            (0x1UL << USART_CR3_OVRDIS_Pos)        /*!< 0x00001000 */

+#define USART_CR3_OVRDIS                USART_CR3_OVRDIS_Msk                   /*!< Overrun Disable */

+#define USART_CR3_DDRE_Pos              (13U)

+#define USART_CR3_DDRE_Msk              (0x1UL << USART_CR3_DDRE_Pos)          /*!< 0x00002000 */

+#define USART_CR3_DDRE                  USART_CR3_DDRE_Msk                     /*!< DMA Disable on Reception Error */

+#define USART_CR3_DEM_Pos               (14U)

+#define USART_CR3_DEM_Msk               (0x1UL << USART_CR3_DEM_Pos)           /*!< 0x00004000 */

+#define USART_CR3_DEM                   USART_CR3_DEM_Msk                      /*!< Driver Enable Mode */

+#define USART_CR3_DEP_Pos               (15U)

+#define USART_CR3_DEP_Msk               (0x1UL << USART_CR3_DEP_Pos)           /*!< 0x00008000 */

+#define USART_CR3_DEP                   USART_CR3_DEP_Msk                      /*!< Driver Enable Polarity Selection */

+#define USART_CR3_SCARCNT_Pos           (17U)

+#define USART_CR3_SCARCNT_Msk           (0x7UL << USART_CR3_SCARCNT_Pos)       /*!< 0x000E0000 */

+#define USART_CR3_SCARCNT               USART_CR3_SCARCNT_Msk                  /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */

+#define USART_CR3_SCARCNT_0             (0x1UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00020000 */

+#define USART_CR3_SCARCNT_1             (0x2UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00040000 */

+#define USART_CR3_SCARCNT_2             (0x4UL << USART_CR3_SCARCNT_Pos)        /*!< 0x00080000 */

+#define USART_CR3_WUS_Pos               (20U)

+#define USART_CR3_WUS_Msk               (0x3UL << USART_CR3_WUS_Pos)           /*!< 0x00300000 */

+#define USART_CR3_WUS                   USART_CR3_WUS_Msk                      /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */

+#define USART_CR3_WUS_0                 (0x1UL << USART_CR3_WUS_Pos)            /*!< 0x00100000 */

+#define USART_CR3_WUS_1                 (0x2UL << USART_CR3_WUS_Pos)            /*!< 0x00200000 */

+#define USART_CR3_WUFIE_Pos             (22U)

+#define USART_CR3_WUFIE_Msk             (0x1UL << USART_CR3_WUFIE_Pos)         /*!< 0x00400000 */

+#define USART_CR3_WUFIE                 USART_CR3_WUFIE_Msk                    /*!< Wake Up Interrupt Enable */

+#define USART_CR3_TXFTIE_Pos            (23U)

+#define USART_CR3_TXFTIE_Msk            (0x1UL << USART_CR3_TXFTIE_Pos)        /*!< 0x00800000 */

+#define USART_CR3_TXFTIE                USART_CR3_TXFTIE_Msk                   /*!< TXFIFO threshold interrupt enable */

+#define USART_CR3_TCBGTIE_Pos           (24U)

+#define USART_CR3_TCBGTIE_Msk           (0x1UL << USART_CR3_TCBGTIE_Pos)       /*!< 0x01000000 */

+#define USART_CR3_TCBGTIE               USART_CR3_TCBGTIE_Msk                  /*!< Transmission Complete before guard time, interrupt enable */

+#define USART_CR3_RXFTCFG_Pos           (25U)

+#define USART_CR3_RXFTCFG_Msk           (0x7UL << USART_CR3_RXFTCFG_Pos)       /*!< 0x0E000000 */

+#define USART_CR3_RXFTCFG               USART_CR3_RXFTCFG_Msk                  /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */

+#define USART_CR3_RXFTCFG_0             (0x1UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x02000000 */

+#define USART_CR3_RXFTCFG_1             (0x2UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x04000000 */

+#define USART_CR3_RXFTCFG_2             (0x4UL << USART_CR3_RXFTCFG_Pos)        /*!< 0x08000000 */

+#define USART_CR3_RXFTIE_Pos            (28U)

+#define USART_CR3_RXFTIE_Msk            (0x1UL << USART_CR3_RXFTIE_Pos)        /*!< 0x10000000 */

+#define USART_CR3_RXFTIE                USART_CR3_RXFTIE_Msk                   /*!< RXFIFO threshold interrupt enable */

+#define USART_CR3_TXFTCFG_Pos           (29U)

+#define USART_CR3_TXFTCFG_Msk           (0x7UL << USART_CR3_TXFTCFG_Pos)       /*!< 0xE0000000 */

+#define USART_CR3_TXFTCFG               USART_CR3_TXFTCFG_Msk                  /*!< TXFIFO [2:0] threshold configuration */

+#define USART_CR3_TXFTCFG_0             (0x1UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x20000000 */

+#define USART_CR3_TXFTCFG_1             (0x2UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x40000000 */

+#define USART_CR3_TXFTCFG_2             (0x4UL << USART_CR3_TXFTCFG_Pos)        /*!< 0x80000000 */

+

+/******************  Bit definition for USART_BRR register  *******************/

+#define USART_BRR_DIV_FRACTION_Pos      (0U)

+#define USART_BRR_DIV_FRACTION_Msk      (0xFUL << USART_BRR_DIV_FRACTION_Pos)  /*!< 0x0000000F */

+#define USART_BRR_DIV_FRACTION          USART_BRR_DIV_FRACTION_Msk             /*!< Fraction of USARTDIV */

+#define USART_BRR_DIV_MANTISSA_Pos      (4U)

+#define USART_BRR_DIV_MANTISSA_Msk      (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */

+#define USART_BRR_DIV_MANTISSA          USART_BRR_DIV_MANTISSA_Msk             /*!< Mantissa of USARTDIV */

+

+/******************  Bit definition for USART_GTPR register  ******************/

+#define USART_GTPR_PSC_Pos              (0U)

+#define USART_GTPR_PSC_Msk              (0xFFUL << USART_GTPR_PSC_Pos)         /*!< 0x000000FF */

+#define USART_GTPR_PSC                  USART_GTPR_PSC_Msk                     /*!< PSC[7:0] bits (Prescaler value) */

+#define USART_GTPR_GT_Pos               (8U)

+#define USART_GTPR_GT_Msk               (0xFFUL << USART_GTPR_GT_Pos)          /*!< 0x0000FF00 */

+#define USART_GTPR_GT                   USART_GTPR_GT_Msk                      /*!< GT[7:0] bits (Guard time value) */

+

+/*******************  Bit definition for USART_RTOR register  *****************/

+#define USART_RTOR_RTO_Pos              (0U)

+#define USART_RTOR_RTO_Msk              (0xFFFFFFUL << USART_RTOR_RTO_Pos)     /*!< 0x00FFFFFF */

+#define USART_RTOR_RTO                  USART_RTOR_RTO_Msk                     /*!< Receiver Time Out Value */

+#define USART_RTOR_BLEN_Pos             (24U)

+#define USART_RTOR_BLEN_Msk             (0xFFUL << USART_RTOR_BLEN_Pos)        /*!< 0xFF000000 */

+#define USART_RTOR_BLEN                 USART_RTOR_BLEN_Msk                    /*!< Block Length */

+

+/*******************  Bit definition for USART_RQR register  ******************/

+#define USART_RQR_ABRRQ_Pos             (0U)

+#define USART_RQR_ABRRQ_Msk             (0x1UL << USART_RQR_ABRRQ_Pos)         /*!< 0x00000001 */

+#define USART_RQR_ABRRQ                 USART_RQR_ABRRQ_Msk                    /*!< Auto-Baud Rate Request */

+#define USART_RQR_SBKRQ_Pos             (1U)

+#define USART_RQR_SBKRQ_Msk             (0x1UL << USART_RQR_SBKRQ_Pos)         /*!< 0x00000002 */

+#define USART_RQR_SBKRQ                 USART_RQR_SBKRQ_Msk                    /*!< Send Break Request */

+#define USART_RQR_MMRQ_Pos              (2U)

+#define USART_RQR_MMRQ_Msk              (0x1UL << USART_RQR_MMRQ_Pos)          /*!< 0x00000004 */

+#define USART_RQR_MMRQ                  USART_RQR_MMRQ_Msk                     /*!< Mute Mode Request */

+#define USART_RQR_RXFRQ_Pos             (3U)

+#define USART_RQR_RXFRQ_Msk             (0x1UL << USART_RQR_RXFRQ_Pos)         /*!< 0x00000008 */

+#define USART_RQR_RXFRQ                 USART_RQR_RXFRQ_Msk                    /*!< Receive Data flush Request */

+#define USART_RQR_TXFRQ_Pos             (4U)

+#define USART_RQR_TXFRQ_Msk             (0x1UL << USART_RQR_TXFRQ_Pos)         /*!< 0x00000010 */

+#define USART_RQR_TXFRQ                 USART_RQR_TXFRQ_Msk                    /*!< Transmit data flush Request */

+

+/*******************  Bit definition for USART_ISR register  ******************/

+#define USART_ISR_PE_Pos                (0U)

+#define USART_ISR_PE_Msk                (0x1UL << USART_ISR_PE_Pos)            /*!< 0x00000001 */

+#define USART_ISR_PE                    USART_ISR_PE_Msk                       /*!< Parity Error */

+#define USART_ISR_FE_Pos                (1U)

+#define USART_ISR_FE_Msk                (0x1UL << USART_ISR_FE_Pos)            /*!< 0x00000002 */

+#define USART_ISR_FE                    USART_ISR_FE_Msk                       /*!< Framing Error */

+#define USART_ISR_NE_Pos                (2U)

+#define USART_ISR_NE_Msk                (0x1UL << USART_ISR_NE_Pos)            /*!< 0x00000004 */

+#define USART_ISR_NE                    USART_ISR_NE_Msk                       /*!< Noise detected Flag */

+#define USART_ISR_ORE_Pos               (3U)

+#define USART_ISR_ORE_Msk               (0x1UL << USART_ISR_ORE_Pos)           /*!< 0x00000008 */

+#define USART_ISR_ORE                   USART_ISR_ORE_Msk                      /*!< OverRun Error */

+#define USART_ISR_IDLE_Pos              (4U)

+#define USART_ISR_IDLE_Msk              (0x1UL << USART_ISR_IDLE_Pos)          /*!< 0x00000010 */

+#define USART_ISR_IDLE                  USART_ISR_IDLE_Msk                     /*!< IDLE line detected */

+#define USART_ISR_RXNE_RXFNE_Pos        (5U)

+#define USART_ISR_RXNE_RXFNE_Msk        (0x1UL << USART_ISR_RXNE_RXFNE_Pos)    /*!< 0x00000020 */

+#define USART_ISR_RXNE_RXFNE            USART_ISR_RXNE_RXFNE_Msk               /*!< Read Data Register or RX FIFO Not Empty */

+#define USART_ISR_TC_Pos                (6U)

+#define USART_ISR_TC_Msk                (0x1UL << USART_ISR_TC_Pos)            /*!< 0x00000040 */

+#define USART_ISR_TC                    USART_ISR_TC_Msk                       /*!< Transmission Complete */

+#define USART_ISR_TXE_TXFNF_Pos         (7U)

+#define USART_ISR_TXE_TXFNF_Msk         (0x1UL << USART_ISR_TXE_TXFNF_Pos)     /*!< 0x00000080 */

+#define USART_ISR_TXE_TXFNF             USART_ISR_TXE_TXFNF_Msk                /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */

+#define USART_ISR_LBDF_Pos              (8U)

+#define USART_ISR_LBDF_Msk              (0x1UL << USART_ISR_LBDF_Pos)          /*!< 0x00000100 */

+#define USART_ISR_LBDF                  USART_ISR_LBDF_Msk                     /*!< LIN Break Detection Flag */

+#define USART_ISR_CTSIF_Pos             (9U)

+#define USART_ISR_CTSIF_Msk             (0x1UL << USART_ISR_CTSIF_Pos)         /*!< 0x00000200 */

+#define USART_ISR_CTSIF                 USART_ISR_CTSIF_Msk                    /*!< CTS interrupt flag */

+#define USART_ISR_CTS_Pos               (10U)

+#define USART_ISR_CTS_Msk               (0x1UL << USART_ISR_CTS_Pos)           /*!< 0x00000400 */

+#define USART_ISR_CTS                   USART_ISR_CTS_Msk                      /*!< CTS flag */

+#define USART_ISR_RTOF_Pos              (11U)

+#define USART_ISR_RTOF_Msk              (0x1UL << USART_ISR_RTOF_Pos)          /*!< 0x00000800 */

+#define USART_ISR_RTOF                  USART_ISR_RTOF_Msk                     /*!< Receiver Time Out */

+#define USART_ISR_EOBF_Pos              (12U)

+#define USART_ISR_EOBF_Msk              (0x1UL << USART_ISR_EOBF_Pos)          /*!< 0x00001000 */

+#define USART_ISR_EOBF                  USART_ISR_EOBF_Msk                     /*!< End Of Block Flag */

+#define USART_ISR_UDR_Pos               (13U)

+#define USART_ISR_UDR_Msk               (0x1UL << USART_ISR_UDR_Pos)           /*!< 0x00002000 */

+#define USART_ISR_UDR                   USART_ISR_UDR_Msk                      /*!< SPI slave underrun error flag */

+#define USART_ISR_ABRE_Pos              (14U)

+#define USART_ISR_ABRE_Msk              (0x1UL << USART_ISR_ABRE_Pos)          /*!< 0x00004000 */

+#define USART_ISR_ABRE                  USART_ISR_ABRE_Msk                     /*!< Auto-Baud Rate Error */

+#define USART_ISR_ABRF_Pos              (15U)

+#define USART_ISR_ABRF_Msk              (0x1UL << USART_ISR_ABRF_Pos)          /*!< 0x00008000 */

+#define USART_ISR_ABRF                  USART_ISR_ABRF_Msk                     /*!< Auto-Baud Rate Flag */

+#define USART_ISR_BUSY_Pos              (16U)

+#define USART_ISR_BUSY_Msk              (0x1UL << USART_ISR_BUSY_Pos)          /*!< 0x00010000 */

+#define USART_ISR_BUSY                  USART_ISR_BUSY_Msk                     /*!< Busy Flag */

+#define USART_ISR_CMF_Pos               (17U)

+#define USART_ISR_CMF_Msk               (0x1UL << USART_ISR_CMF_Pos)           /*!< 0x00020000 */

+#define USART_ISR_CMF                   USART_ISR_CMF_Msk                      /*!< Character Match Flag */

+#define USART_ISR_SBKF_Pos              (18U)

+#define USART_ISR_SBKF_Msk              (0x1UL << USART_ISR_SBKF_Pos)          /*!< 0x00040000 */

+#define USART_ISR_SBKF                  USART_ISR_SBKF_Msk                     /*!< Send Break Flag */

+#define USART_ISR_RWU_Pos               (19U)

+#define USART_ISR_RWU_Msk               (0x1UL << USART_ISR_RWU_Pos)           /*!< 0x00080000 */

+#define USART_ISR_RWU                   USART_ISR_RWU_Msk                      /*!< Receive Wake Up from mute mode Flag */

+#define USART_ISR_WUF_Pos               (20U)

+#define USART_ISR_WUF_Msk               (0x1UL << USART_ISR_WUF_Pos)           /*!< 0x00100000 */

+#define USART_ISR_WUF                   USART_ISR_WUF_Msk                      /*!< Wake Up from stop mode Flag */

+#define USART_ISR_TEACK_Pos             (21U)

+#define USART_ISR_TEACK_Msk             (0x1UL << USART_ISR_TEACK_Pos)         /*!< 0x00200000 */

+#define USART_ISR_TEACK                 USART_ISR_TEACK_Msk                    /*!< Transmit Enable Acknowledge Flag */

+#define USART_ISR_REACK_Pos             (22U)

+#define USART_ISR_REACK_Msk             (0x1UL << USART_ISR_REACK_Pos)         /*!< 0x00400000 */

+#define USART_ISR_REACK                 USART_ISR_REACK_Msk                    /*!< Receive Enable Acknowledge Flag */

+#define USART_ISR_TXFE_Pos              (23U)

+#define USART_ISR_TXFE_Msk              (0x1UL << USART_ISR_TXFE_Pos)          /*!< 0x00800000 */

+#define USART_ISR_TXFE                  USART_ISR_TXFE_Msk                     /*!< TXFIFO Empty */

+#define USART_ISR_RXFF_Pos              (24U)

+#define USART_ISR_RXFF_Msk              (0x1UL << USART_ISR_RXFF_Pos)          /*!< 0x01000000 */

+#define USART_ISR_RXFF                  USART_ISR_RXFF_Msk                     /*!< RXFIFO Full Flag */

+#define USART_ISR_TCBGT_Pos             (25U)

+#define USART_ISR_TCBGT_Msk             (0x1UL << USART_ISR_TCBGT_Pos)         /*!< 0x02000000 */

+#define USART_ISR_TCBGT                 USART_ISR_TCBGT_Msk                    /*!< Transmission complete before guard time Flag */

+#define USART_ISR_RXFT_Pos              (26U)

+#define USART_ISR_RXFT_Msk              (0x1UL << USART_ISR_RXFT_Pos)          /*!< 0x04000000 */

+#define USART_ISR_RXFT                  USART_ISR_RXFT_Msk                     /*!< RXFIFO threshold Flag */

+#define USART_ISR_TXFT_Pos              (27U)

+#define USART_ISR_TXFT_Msk              (0x1UL << USART_ISR_TXFT_Pos)          /*!< 0x08000000 */

+#define USART_ISR_TXFT                  USART_ISR_TXFT_Msk                     /*!< TXFIFO threshold Flag */

+

+/*******************  Bit definition for USART_ICR register  ******************/

+#define USART_ICR_PECF_Pos              (0U)

+#define USART_ICR_PECF_Msk              (0x1UL << USART_ICR_PECF_Pos)          /*!< 0x00000001 */

+#define USART_ICR_PECF                  USART_ICR_PECF_Msk                     /*!< Parity Error Clear Flag */

+#define USART_ICR_FECF_Pos              (1U)

+#define USART_ICR_FECF_Msk              (0x1UL << USART_ICR_FECF_Pos)          /*!< 0x00000002 */

+#define USART_ICR_FECF                  USART_ICR_FECF_Msk                     /*!< Framing Error Clear Flag */

+#define USART_ICR_NECF_Pos              (2U)

+#define USART_ICR_NECF_Msk              (0x1UL << USART_ICR_NECF_Pos)          /*!< 0x00000004 */

+#define USART_ICR_NECF                  USART_ICR_NECF_Msk                     /*!< Noise detected Clear Flag */

+#define USART_ICR_ORECF_Pos             (3U)

+#define USART_ICR_ORECF_Msk             (0x1UL << USART_ICR_ORECF_Pos)         /*!< 0x00000008 */

+#define USART_ICR_ORECF                 USART_ICR_ORECF_Msk                    /*!< OverRun Error Clear Flag */

+#define USART_ICR_IDLECF_Pos            (4U)

+#define USART_ICR_IDLECF_Msk            (0x1UL << USART_ICR_IDLECF_Pos)        /*!< 0x00000010 */

+#define USART_ICR_IDLECF                USART_ICR_IDLECF_Msk                   /*!< IDLE line detected Clear Flag */

+#define USART_ICR_TXFECF_Pos            (5U)

+#define USART_ICR_TXFECF_Msk            (0x1UL << USART_ICR_TXFECF_Pos)        /*!< 0x00000020 */

+#define USART_ICR_TXFECF                USART_ICR_TXFECF_Msk                   /*!< TXFIFO empty clear flag */

+#define USART_ICR_TCCF_Pos              (6U)

+#define USART_ICR_TCCF_Msk              (0x1UL << USART_ICR_TCCF_Pos)          /*!< 0x00000040 */

+#define USART_ICR_TCCF                  USART_ICR_TCCF_Msk                     /*!< Transmission Complete Clear Flag */

+#define USART_ICR_TCBGTCF_Pos           (7U)

+#define USART_ICR_TCBGTCF_Msk           (0x1UL << USART_ICR_TCBGTCF_Pos)       /*!< 0x00000080 */

+#define USART_ICR_TCBGTCF               USART_ICR_TCBGTCF_Msk                  /*!< Transmission complete before guard time Clear Flag */

+#define USART_ICR_LBDCF_Pos             (8U)

+#define USART_ICR_LBDCF_Msk             (0x1UL << USART_ICR_LBDCF_Pos)         /*!< 0x00000100 */

+#define USART_ICR_LBDCF                 USART_ICR_LBDCF_Msk                    /*!< LIN Break Detection Clear Flag */

+#define USART_ICR_CTSCF_Pos             (9U)

+#define USART_ICR_CTSCF_Msk             (0x1UL << USART_ICR_CTSCF_Pos)         /*!< 0x00000200 */

+#define USART_ICR_CTSCF                 USART_ICR_CTSCF_Msk                    /*!< CTS Interrupt Clear Flag */

+#define USART_ICR_RTOCF_Pos             (11U)

+#define USART_ICR_RTOCF_Msk             (0x1UL << USART_ICR_RTOCF_Pos)         /*!< 0x00000800 */

+#define USART_ICR_RTOCF                 USART_ICR_RTOCF_Msk                    /*!< Receiver Time Out Clear Flag */

+#define USART_ICR_EOBCF_Pos             (12U)

+#define USART_ICR_EOBCF_Msk             (0x1UL << USART_ICR_EOBCF_Pos)         /*!< 0x00001000 */

+#define USART_ICR_EOBCF                 USART_ICR_EOBCF_Msk                    /*!< End Of Block Clear Flag */

+#define USART_ICR_UDRCF_Pos             (13U)

+#define USART_ICR_UDRCF_Msk             (0x1UL << USART_ICR_UDRCF_Pos)         /*!< 0x00002000 */

+#define USART_ICR_UDRCF                 USART_ICR_UDRCF_Msk                    /*!< SPI slave underrun clear flag */

+#define USART_ICR_CMCF_Pos              (17U)

+#define USART_ICR_CMCF_Msk              (0x1UL << USART_ICR_CMCF_Pos)          /*!< 0x00020000 */

+#define USART_ICR_CMCF                  USART_ICR_CMCF_Msk                     /*!< Character Match Clear Flag */

+#define USART_ICR_WUCF_Pos              (20U)

+#define USART_ICR_WUCF_Msk              (0x1UL << USART_ICR_WUCF_Pos)          /*!< 0x00100000 */

+#define USART_ICR_WUCF                  USART_ICR_WUCF_Msk                     /*!< Wake Up from stop mode Clear Flag */

+

+/*******************  Bit definition for USART_RDR register  ******************/

+#define USART_RDR_RDR_Pos               (0U)

+#define USART_RDR_RDR_Msk               (0x1FFUL << USART_RDR_RDR_Pos)         /*!< 0x000001FF */

+#define USART_RDR_RDR                   USART_RDR_RDR_Msk                      /*!< RDR[8:0] bits (Receive Data value) */

+

+/*******************  Bit definition for USART_TDR register  ******************/

+#define USART_TDR_TDR_Pos               (0U)

+#define USART_TDR_TDR_Msk               (0x1FFUL << USART_TDR_TDR_Pos)         /*!< 0x000001FF */

+#define USART_TDR_TDR                   USART_TDR_TDR_Msk                      /*!< TDR[8:0] bits (Transmit Data value) */

+

+/*******************  Bit definition for USART_PRESC register  ******************/

+#define USART_PRESC_PRESCALER_Pos       (0U)

+#define USART_PRESC_PRESCALER_Msk       (0xFUL << USART_PRESC_PRESCALER_Pos)   /*!< 0x0000000F */

+#define USART_PRESC_PRESCALER           USART_PRESC_PRESCALER_Msk              /*!< PRESCALER[3:0] bits (Clock prescaler) */

+#define USART_PRESC_PRESCALER_0         (0x1UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000001 */

+#define USART_PRESC_PRESCALER_1         (0x2UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000002 */

+#define USART_PRESC_PRESCALER_2         (0x4UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000004 */

+#define USART_PRESC_PRESCALER_3         (0x8UL << USART_PRESC_PRESCALER_Pos)    /*!< 0x00000008 */

+

+/******************************************************************************/

+/*                                                                            */

+/*           Single Wire Protocol Master Interface (SWPMI)                    */

+/*                                                                            */

+/******************************************************************************/

+

+/*******************  Bit definition for SWPMI_CR register   ********************/

+#define SWPMI_CR_RXDMA_Pos       (0U)

+#define SWPMI_CR_RXDMA_Msk       (0x1UL << SWPMI_CR_RXDMA_Pos)                 /*!< 0x00000001 */

+#define SWPMI_CR_RXDMA           SWPMI_CR_RXDMA_Msk                            /*!<Reception DMA enable                                 */

+#define SWPMI_CR_TXDMA_Pos       (1U)

+#define SWPMI_CR_TXDMA_Msk       (0x1UL << SWPMI_CR_TXDMA_Pos)                 /*!< 0x00000002 */

+#define SWPMI_CR_TXDMA           SWPMI_CR_TXDMA_Msk                            /*!<Transmission DMA enable                              */

+#define SWPMI_CR_RXMODE_Pos      (2U)

+#define SWPMI_CR_RXMODE_Msk      (0x1UL << SWPMI_CR_RXMODE_Pos)                /*!< 0x00000004 */

+#define SWPMI_CR_RXMODE          SWPMI_CR_RXMODE_Msk                           /*!<Reception buffering mode                             */

+#define SWPMI_CR_TXMODE_Pos      (3U)

+#define SWPMI_CR_TXMODE_Msk      (0x1UL << SWPMI_CR_TXMODE_Pos)                /*!< 0x00000008 */

+#define SWPMI_CR_TXMODE          SWPMI_CR_TXMODE_Msk                           /*!<Transmission buffering mode                          */

+#define SWPMI_CR_LPBK_Pos        (4U)

+#define SWPMI_CR_LPBK_Msk        (0x1UL << SWPMI_CR_LPBK_Pos)                  /*!< 0x00000010 */

+#define SWPMI_CR_LPBK            SWPMI_CR_LPBK_Msk                             /*!<Loopback mode enable                                 */

+#define SWPMI_CR_SWPACT_Pos      (5U)

+#define SWPMI_CR_SWPACT_Msk      (0x1UL << SWPMI_CR_SWPACT_Pos)                /*!< 0x00000020 */

+#define SWPMI_CR_SWPACT          SWPMI_CR_SWPACT_Msk                           /*!<Single wire protocol master interface activate       */

+#define SWPMI_CR_DEACT_Pos       (10U)

+#define SWPMI_CR_DEACT_Msk       (0x1UL << SWPMI_CR_DEACT_Pos)                 /*!< 0x00000400 */

+#define SWPMI_CR_DEACT           SWPMI_CR_DEACT_Msk                            /*!<Single wire protocol master interface deactivate     */

+#define SWPMI_CR_SWPEN_Pos       (11U)

+#define SWPMI_CR_SWPEN_Msk       (0x1UL << SWPMI_CR_SWPEN_Pos)                 /*!< 0x00000800 */

+#define SWPMI_CR_SWPEN           SWPMI_CR_SWPEN_Msk                            /*!<Single wire protocol master transceiver enable       */

+

+/*******************  Bit definition for SWPMI_BRR register  ********************/

+#define SWPMI_BRR_BR_Pos         (0U)

+#define SWPMI_BRR_BR_Msk         (0xFFUL << SWPMI_BRR_BR_Pos)                  /*!< 0x000000FF */

+#define SWPMI_BRR_BR             SWPMI_BRR_BR_Msk                              /*!<BR[7:0] bits (Bitrate prescaler) */

+

+/*******************  Bit definition for SWPMI_ISR register  ********************/

+#define SWPMI_ISR_RXBFF_Pos      (0U)

+#define SWPMI_ISR_RXBFF_Msk      (0x1UL << SWPMI_ISR_RXBFF_Pos)                /*!< 0x00000001 */

+#define SWPMI_ISR_RXBFF          SWPMI_ISR_RXBFF_Msk                           /*!<Receive buffer full flag        */

+#define SWPMI_ISR_TXBEF_Pos      (1U)

+#define SWPMI_ISR_TXBEF_Msk      (0x1UL << SWPMI_ISR_TXBEF_Pos)                /*!< 0x00000002 */

+#define SWPMI_ISR_TXBEF          SWPMI_ISR_TXBEF_Msk                           /*!<Transmit buffer empty flag      */

+#define SWPMI_ISR_RXBERF_Pos     (2U)

+#define SWPMI_ISR_RXBERF_Msk     (0x1UL << SWPMI_ISR_RXBERF_Pos)               /*!< 0x00000004 */

+#define SWPMI_ISR_RXBERF         SWPMI_ISR_RXBERF_Msk                          /*!<Receive CRC error flag          */

+#define SWPMI_ISR_RXOVRF_Pos     (3U)

+#define SWPMI_ISR_RXOVRF_Msk     (0x1UL << SWPMI_ISR_RXOVRF_Pos)               /*!< 0x00000008 */

+#define SWPMI_ISR_RXOVRF         SWPMI_ISR_RXOVRF_Msk                          /*!<Receive overrun error flag      */

+#define SWPMI_ISR_TXUNRF_Pos     (4U)

+#define SWPMI_ISR_TXUNRF_Msk     (0x1UL << SWPMI_ISR_TXUNRF_Pos)               /*!< 0x00000010 */

+#define SWPMI_ISR_TXUNRF         SWPMI_ISR_TXUNRF_Msk                          /*!<Transmit underrun error flag    */

+#define SWPMI_ISR_RXNE_Pos       (5U)

+#define SWPMI_ISR_RXNE_Msk       (0x1UL << SWPMI_ISR_RXNE_Pos)                 /*!< 0x00000020 */

+#define SWPMI_ISR_RXNE           SWPMI_ISR_RXNE_Msk                            /*!<Receive data register not empty */

+#define SWPMI_ISR_TXE_Pos        (6U)

+#define SWPMI_ISR_TXE_Msk        (0x1UL << SWPMI_ISR_TXE_Pos)                  /*!< 0x00000040 */

+#define SWPMI_ISR_TXE            SWPMI_ISR_TXE_Msk                             /*!<Transmit data register empty    */

+#define SWPMI_ISR_TCF_Pos        (7U)

+#define SWPMI_ISR_TCF_Msk        (0x1UL << SWPMI_ISR_TCF_Pos)                  /*!< 0x00000080 */

+#define SWPMI_ISR_TCF            SWPMI_ISR_TCF_Msk                             /*!<Transfer complete flag          */

+#define SWPMI_ISR_SRF_Pos        (8U)

+#define SWPMI_ISR_SRF_Msk        (0x1UL << SWPMI_ISR_SRF_Pos)                  /*!< 0x00000100 */

+#define SWPMI_ISR_SRF            SWPMI_ISR_SRF_Msk                             /*!<Slave resume flag               */

+#define SWPMI_ISR_SUSP_Pos       (9U)

+#define SWPMI_ISR_SUSP_Msk       (0x1UL << SWPMI_ISR_SUSP_Pos)                 /*!< 0x00000200 */

+#define SWPMI_ISR_SUSP           SWPMI_ISR_SUSP_Msk                            /*!<SUSPEND flag                    */

+#define SWPMI_ISR_DEACTF_Pos     (10U)

+#define SWPMI_ISR_DEACTF_Msk     (0x1UL << SWPMI_ISR_DEACTF_Pos)               /*!< 0x00000400 */

+#define SWPMI_ISR_DEACTF         SWPMI_ISR_DEACTF_Msk                          /*!<DEACTIVATED flag                */

+#define SWPMI_ISR_RDYF_Pos       (11U)

+#define SWPMI_ISR_RDYF_Msk       (0x1UL << SWPMI_ISR_RDYF_Pos)                 /*!< 0x00000800 */

+#define SWPMI_ISR_RDYF           SWPMI_ISR_RDYF_Msk                            /*!<Transceiver ready flag          */

+

+/*******************  Bit definition for SWPMI_ICR register  ********************/

+#define SWPMI_ICR_CRXBFF_Pos     (0U)

+#define SWPMI_ICR_CRXBFF_Msk     (0x1UL << SWPMI_ICR_CRXBFF_Pos)               /*!< 0x00000001 */

+#define SWPMI_ICR_CRXBFF         SWPMI_ICR_CRXBFF_Msk                          /*!<Clear receive buffer full flag       */

+#define SWPMI_ICR_CTXBEF_Pos     (1U)

+#define SWPMI_ICR_CTXBEF_Msk     (0x1UL << SWPMI_ICR_CTXBEF_Pos)               /*!< 0x00000002 */

+#define SWPMI_ICR_CTXBEF         SWPMI_ICR_CTXBEF_Msk                          /*!<Clear transmit buffer empty flag     */

+#define SWPMI_ICR_CRXBERF_Pos    (2U)

+#define SWPMI_ICR_CRXBERF_Msk    (0x1UL << SWPMI_ICR_CRXBERF_Pos)              /*!< 0x00000004 */

+#define SWPMI_ICR_CRXBERF        SWPMI_ICR_CRXBERF_Msk                         /*!<Clear receive CRC error flag         */

+#define SWPMI_ICR_CRXOVRF_Pos    (3U)

+#define SWPMI_ICR_CRXOVRF_Msk    (0x1UL << SWPMI_ICR_CRXOVRF_Pos)              /*!< 0x00000008 */

+#define SWPMI_ICR_CRXOVRF        SWPMI_ICR_CRXOVRF_Msk                         /*!<Clear receive overrun error flag     */

+#define SWPMI_ICR_CTXUNRF_Pos    (4U)

+#define SWPMI_ICR_CTXUNRF_Msk    (0x1UL << SWPMI_ICR_CTXUNRF_Pos)              /*!< 0x00000010 */

+#define SWPMI_ICR_CTXUNRF        SWPMI_ICR_CTXUNRF_Msk                         /*!<Clear transmit underrun error flag   */

+#define SWPMI_ICR_CTCF_Pos       (7U)

+#define SWPMI_ICR_CTCF_Msk       (0x1UL << SWPMI_ICR_CTCF_Pos)                 /*!< 0x00000080 */

+#define SWPMI_ICR_CTCF           SWPMI_ICR_CTCF_Msk                            /*!<Clear transfer complete flag         */

+#define SWPMI_ICR_CSRF_Pos       (8U)

+#define SWPMI_ICR_CSRF_Msk       (0x1UL << SWPMI_ICR_CSRF_Pos)                 /*!< 0x00000100 */

+#define SWPMI_ICR_CSRF           SWPMI_ICR_CSRF_Msk                            /*!<Clear slave resume flag              */

+#define SWPMI_ICR_CRDYF_Pos      (11U)

+#define SWPMI_ICR_CRDYF_Msk      (0x1UL << SWPMI_ICR_CRDYF_Pos)                /*!< 0x00000800 */

+#define SWPMI_ICR_CRDYF          SWPMI_ICR_CRDYF_Msk                           /*!<Clear transceiver ready flag         */

+

+/*******************  Bit definition for SWPMI_IER register  ********************/

+#define SWPMI_IER_RXBFIE_Pos     (0U)

+#define SWPMI_IER_RXBFIE_Msk     (0x1UL << SWPMI_IER_RXBFIE_Pos)               /*!< 0x00000001 */

+#define SWPMI_IER_RXBFIE         SWPMI_IER_RXBFIE_Msk                          /*!<Receive buffer full interrupt enable        */

+#define SWPMI_IER_TXBEIE_Pos     (1U)

+#define SWPMI_IER_TXBEIE_Msk     (0x1UL << SWPMI_IER_TXBEIE_Pos)               /*!< 0x00000002 */

+#define SWPMI_IER_TXBEIE         SWPMI_IER_TXBEIE_Msk                          /*!<Transmit buffer empty interrupt enable      */

+#define SWPMI_IER_RXBERIE_Pos    (2U)

+#define SWPMI_IER_RXBERIE_Msk    (0x1UL << SWPMI_IER_RXBERIE_Pos)              /*!< 0x00000004 */

+#define SWPMI_IER_RXBERIE        SWPMI_IER_RXBERIE_Msk                         /*!<Receive CRC error interrupt enable          */

+#define SWPMI_IER_RXOVRIE_Pos    (3U)

+#define SWPMI_IER_RXOVRIE_Msk    (0x1UL << SWPMI_IER_RXOVRIE_Pos)              /*!< 0x00000008 */

+#define SWPMI_IER_RXOVRIE        SWPMI_IER_RXOVRIE_Msk                         /*!<Receive overrun error interrupt enable      */

+#define SWPMI_IER_TXUNRIE_Pos    (4U)

+#define SWPMI_IER_TXUNRIE_Msk    (0x1UL << SWPMI_IER_TXUNRIE_Pos)              /*!< 0x00000010 */

+#define SWPMI_IER_TXUNRIE        SWPMI_IER_TXUNRIE_Msk                         /*!<Transmit underrun error interrupt enable    */

+#define SWPMI_IER_RIE_Pos        (5U)

+#define SWPMI_IER_RIE_Msk        (0x1UL << SWPMI_IER_RIE_Pos)                  /*!< 0x00000020 */

+#define SWPMI_IER_RIE            SWPMI_IER_RIE_Msk                             /*!<Receive interrupt enable                    */

+#define SWPMI_IER_TIE_Pos        (6U)

+#define SWPMI_IER_TIE_Msk        (0x1UL << SWPMI_IER_TIE_Pos)                  /*!< 0x00000040 */

+#define SWPMI_IER_TIE            SWPMI_IER_TIE_Msk                             /*!<Transmit interrupt enable                   */

+#define SWPMI_IER_TCIE_Pos       (7U)

+#define SWPMI_IER_TCIE_Msk       (0x1UL << SWPMI_IER_TCIE_Pos)                 /*!< 0x00000080 */

+#define SWPMI_IER_TCIE           SWPMI_IER_TCIE_Msk                            /*!<Transmit complete interrupt enable          */

+#define SWPMI_IER_SRIE_Pos       (8U)

+#define SWPMI_IER_SRIE_Msk       (0x1UL << SWPMI_IER_SRIE_Pos)                 /*!< 0x00000100 */

+#define SWPMI_IER_SRIE           SWPMI_IER_SRIE_Msk                            /*!<Slave resume interrupt enable               */

+#define SWPMI_IER_RDYIE_Pos      (11U)

+#define SWPMI_IER_RDYIE_Msk      (0x1UL << SWPMI_IER_RDYIE_Pos)                /*!< 0x00000800 */

+#define SWPMI_IER_RDYIE          SWPMI_IER_RDYIE_Msk                           /*!<Transceiver ready interrupt enable          */

+

+/*******************  Bit definition for SWPMI_RFL register  ********************/

+#define SWPMI_RFL_RFL_Pos        (0U)

+#define SWPMI_RFL_RFL_Msk        (0x1FUL << SWPMI_RFL_RFL_Pos)                 /*!< 0x0000001F */

+#define SWPMI_RFL_RFL            SWPMI_RFL_RFL_Msk                             /*!<RFL[4:0] bits (Receive Frame length) */

+#define SWPMI_RFL_RFL_0_1        ((uint32_t)0x00000003)                        /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */

+

+/*******************  Bit definition for SWPMI_TDR register  ********************/

+#define SWPMI_TDR_TD_Pos         (0U)

+#define SWPMI_TDR_TD_Msk         (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos)            /*!< 0xFFFFFFFF */

+#define SWPMI_TDR_TD             SWPMI_TDR_TD_Msk                              /*!<Transmit Data Register         */

+

+/*******************  Bit definition for SWPMI_RDR register  ********************/

+#define SWPMI_RDR_RD_Pos         (0U)

+#define SWPMI_RDR_RD_Msk         (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos)            /*!< 0xFFFFFFFF */

+#define SWPMI_RDR_RD             SWPMI_RDR_RD_Msk                              /*!<Recive Data Register           */

+

+

+/*******************  Bit definition for SWPMI_OR register  ********************/

+#define SWPMI_OR_TBYP_Pos        (0U)

+#define SWPMI_OR_TBYP_Msk        (0x1UL << SWPMI_OR_TBYP_Pos)                  /*!< 0x00000001 */

+#define SWPMI_OR_TBYP            SWPMI_OR_TBYP_Msk                             /*!<SWP Transceiver Bypass */

+#define SWPMI_OR_CLASS_Pos       (1U)

+#define SWPMI_OR_CLASS_Msk       (0x1UL << SWPMI_OR_CLASS_Pos)                 /*!< 0x00000002 */

+#define SWPMI_OR_CLASS           SWPMI_OR_CLASS_Msk                            /*!<SWP CLASS selection */

+

+/******************************************************************************/

+/*                                                                            */

+/*                            Window WATCHDOG                                 */

+/*                                                                            */

+/******************************************************************************/

+/*******************  Bit definition for WWDG_CR register  ********************/

+#define WWDG_CR_T_Pos           (0U)

+#define WWDG_CR_T_Msk           (0x7FUL << WWDG_CR_T_Pos)                      /*!< 0x0000007F */

+#define WWDG_CR_T               WWDG_CR_T_Msk                                  /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */

+#define WWDG_CR_T_0             (0x01UL << WWDG_CR_T_Pos)                       /*!< 0x00000001 */

+#define WWDG_CR_T_1             (0x02UL << WWDG_CR_T_Pos)                       /*!< 0x00000002 */

+#define WWDG_CR_T_2             (0x04UL << WWDG_CR_T_Pos)                       /*!< 0x00000004 */

+#define WWDG_CR_T_3             (0x08UL << WWDG_CR_T_Pos)                       /*!< 0x00000008 */

+#define WWDG_CR_T_4             (0x10UL << WWDG_CR_T_Pos)                       /*!< 0x00000010 */

+#define WWDG_CR_T_5             (0x20UL << WWDG_CR_T_Pos)                       /*!< 0x00000020 */

+#define WWDG_CR_T_6             (0x40UL << WWDG_CR_T_Pos)                       /*!< 0x00000040 */

+

+#define WWDG_CR_WDGA_Pos        (7U)

+#define WWDG_CR_WDGA_Msk        (0x1UL << WWDG_CR_WDGA_Pos)                    /*!< 0x00000080 */

+#define WWDG_CR_WDGA            WWDG_CR_WDGA_Msk                               /*!<Activation bit */

+

+/*******************  Bit definition for WWDG_CFR register  *******************/

+#define WWDG_CFR_W_Pos          (0U)

+#define WWDG_CFR_W_Msk          (0x7FUL << WWDG_CFR_W_Pos)                     /*!< 0x0000007F */

+#define WWDG_CFR_W              WWDG_CFR_W_Msk                                 /*!<W[6:0] bits (7-bit window value) */

+#define WWDG_CFR_W_0            (0x01UL << WWDG_CFR_W_Pos)                      /*!< 0x00000001 */

+#define WWDG_CFR_W_1            (0x02UL << WWDG_CFR_W_Pos)                      /*!< 0x00000002 */

+#define WWDG_CFR_W_2            (0x04UL << WWDG_CFR_W_Pos)                      /*!< 0x00000004 */

+#define WWDG_CFR_W_3            (0x08UL << WWDG_CFR_W_Pos)                      /*!< 0x00000008 */

+#define WWDG_CFR_W_4            (0x10UL << WWDG_CFR_W_Pos)                      /*!< 0x00000010 */

+#define WWDG_CFR_W_5            (0x20UL << WWDG_CFR_W_Pos)                      /*!< 0x00000020 */

+#define WWDG_CFR_W_6            (0x40UL << WWDG_CFR_W_Pos)                      /*!< 0x00000040 */

+

+#define WWDG_CFR_EWI_Pos        (9U)

+#define WWDG_CFR_EWI_Msk        (0x1UL << WWDG_CFR_EWI_Pos)                    /*!< 0x00000200 */

+#define WWDG_CFR_EWI            WWDG_CFR_EWI_Msk                               /*!<Early Wakeup Interrupt */

+

+#define WWDG_CFR_WDGTB_Pos      (11U)

+#define WWDG_CFR_WDGTB_Msk      (0x7UL << WWDG_CFR_WDGTB_Pos)                  /*!< 0x00003800 */

+#define WWDG_CFR_WDGTB          WWDG_CFR_WDGTB_Msk                             /*!<WDGTB[2:0] bits (Timer Base) */

+#define WWDG_CFR_WDGTB_0        (0x1UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00000800 */

+#define WWDG_CFR_WDGTB_1        (0x2UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00001000 */

+#define WWDG_CFR_WDGTB_2        (0x4UL << WWDG_CFR_WDGTB_Pos)                   /*!< 0x00002000 */

+

+/*******************  Bit definition for WWDG_SR register  ********************/

+#define WWDG_SR_EWIF_Pos        (0U)

+#define WWDG_SR_EWIF_Msk        (0x1UL << WWDG_SR_EWIF_Pos)                    /*!< 0x00000001 */

+#define WWDG_SR_EWIF            WWDG_SR_EWIF_Msk                               /*!<Early Wakeup Interrupt Flag */

+

+

+/******************************************************************************/

+/*                                                                            */

+/*                                DBG                                         */

+/*                                                                            */

+/******************************************************************************/

+/*********************************  DEVICE ID  ********************************/

+#define STM32H7_DEV_ID           0x480UL

+

+/********************  Bit definition for DBGMCU_IDCODE register  *************/

+#define DBGMCU_IDCODE_DEV_ID_Pos          (0U)

+#define DBGMCU_IDCODE_DEV_ID_Msk          (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */

+#define DBGMCU_IDCODE_DEV_ID              DBGMCU_IDCODE_DEV_ID_Msk

+#define DBGMCU_IDCODE_REV_ID_Pos          (16U)

+#define DBGMCU_IDCODE_REV_ID_Msk          (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */

+#define DBGMCU_IDCODE_REV_ID              DBGMCU_IDCODE_REV_ID_Msk

+

+/********************  Bit definition for DBGMCU_CR register  *****************/

+#define DBGMCU_CR_DBG_SLEEPCD_Pos         (0U)

+#define DBGMCU_CR_DBG_SLEEPCD_Msk         (0x1UL << DBGMCU_CR_DBG_SLEEPCD_Pos) /*!< 0x00000001 */

+#define DBGMCU_CR_DBG_SLEEPCD             DBGMCU_CR_DBG_SLEEPCD_Msk

+#define DBGMCU_CR_DBG_STOPCD_Pos          (1U)

+#define DBGMCU_CR_DBG_STOPCD_Msk          (0x1UL << DBGMCU_CR_DBG_STOPCD_Pos)  /*!< 0x00000002 */

+#define DBGMCU_CR_DBG_STOPCD              DBGMCU_CR_DBG_STOPCD_Msk

+#define DBGMCU_CR_DBG_STANDBYCD_Pos       (2U)

+#define DBGMCU_CR_DBG_STANDBYCD_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYCD_Pos) /*!< 0x00000004 */

+#define DBGMCU_CR_DBG_STANDBYCD           DBGMCU_CR_DBG_STANDBYCD_Msk

+

+/* Legacy defines */

+#define DBGMCU_CR_DBG_SLEEPD1_Pos         DBGMCU_CR_DBG_SLEEPCD_Pos

+#define DBGMCU_CR_DBG_SLEEPD1_Msk         DBGMCU_CR_DBG_SLEEPCD_Msk

+#define DBGMCU_CR_DBG_SLEEPD1             DBGMCU_CR_DBG_SLEEPCD

+#define DBGMCU_CR_DBG_STOPD1_Pos          DBGMCU_CR_DBG_STOPCD_Pos

+#define DBGMCU_CR_DBG_STOPD1_Msk          DBGMCU_CR_DBG_STOPCD_Msk

+#define DBGMCU_CR_DBG_STOPD1              DBGMCU_CR_DBG_STOPCD

+#define DBGMCU_CR_DBG_STANDBYD1_Pos       DBGMCU_CR_DBG_STANDBYCD_Pos

+#define DBGMCU_CR_DBG_STANDBYD1_Msk       DBGMCU_CR_DBG_STANDBYCD_Msk

+#define DBGMCU_CR_DBG_STANDBYD1           DBGMCU_CR_DBG_STANDBYCD

+#define DBGMCU_CR_DBG_STOPSRD_Pos          (7U)

+#define DBGMCU_CR_DBG_STOPSRD_Msk          (0x1UL << DBGMCU_CR_DBG_STOPSRD_Pos)  /*!< 0x00000080 */

+#define DBGMCU_CR_DBG_STOPSRD              DBGMCU_CR_DBG_STOPSRD_Msk

+#define DBGMCU_CR_DBG_STANDBYSRD_Pos       (8U)

+#define DBGMCU_CR_DBG_STANDBYSRD_Msk       (0x1UL << DBGMCU_CR_DBG_STANDBYSRD_Pos) /*!< 0x00000100 */

+#define DBGMCU_CR_DBG_STANDBYSRD           DBGMCU_CR_DBG_STANDBYSRD_Msk

+

+/* Legacy defines */

+#define DBGMCU_CR_DBG_STOPD3_Pos          DBGMCU_CR_DBG_STOPSRD_Pos

+#define DBGMCU_CR_DBG_STOPD3_Msk          DBGMCU_CR_DBG_STOPSRD_Msk

+#define DBGMCU_CR_DBG_STOPD3              DBGMCU_CR_DBG_STOPSRD

+#define DBGMCU_CR_DBG_STANDBYD3_Pos       DBGMCU_CR_DBG_STANDBYSRD_Pos

+#define DBGMCU_CR_DBG_STANDBYD3_Msk       DBGMCU_CR_DBG_STANDBYSRD_Msk

+#define DBGMCU_CR_DBG_STANDBYD3           DBGMCU_CR_DBG_STANDBYSRD

+

+#define DBGMCU_CR_DBG_TRACECKEN_Pos       (20U)

+#define DBGMCU_CR_DBG_TRACECKEN_Msk       (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */

+#define DBGMCU_CR_DBG_TRACECKEN           DBGMCU_CR_DBG_TRACECKEN_Msk

+#define DBGMCU_CR_DBG_CKCDEN_Pos          (21U)

+#define DBGMCU_CR_DBG_CKCDEN_Msk          (0x1UL << DBGMCU_CR_DBG_CKCDEN_Pos)  /*!< 0x00200000 */

+#define DBGMCU_CR_DBG_CKCDEN              DBGMCU_CR_DBG_CKCDEN_Msk

+#define DBGMCU_CR_DBG_CKSRDEN_Pos          (22U)

+#define DBGMCU_CR_DBG_CKSRDEN_Msk          (0x1UL << DBGMCU_CR_DBG_CKSRDEN_Pos)  /*!< 0x00400000 */

+#define DBGMCU_CR_DBG_CKSRDEN              DBGMCU_CR_DBG_CKSRDEN_Msk

+

+/* Legacy defines */

+#define DBGMCU_CR_DBG_CKD1EN_Pos          DBGMCU_CR_DBG_CKCDEN_Pos

+#define DBGMCU_CR_DBG_CKD1EN_Msk          DBGMCU_CR_DBG_CKCDEN_Msk

+#define DBGMCU_CR_DBG_CKD1EN              DBGMCU_CR_DBG_CKCDEN

+#define DBGMCU_CR_DBG_CKD3EN_Pos          DBGMCU_CR_DBG_CKSRDEN_Pos

+#define DBGMCU_CR_DBG_CKD3EN_Msk          DBGMCU_CR_DBG_CKSRDEN_Msk

+#define DBGMCU_CR_DBG_CKD3EN              DBGMCU_CR_DBG_CKSRDEN

+

+#define DBGMCU_CR_DBG_TRGOEN_Pos          (28U)

+#define DBGMCU_CR_DBG_TRGOEN_Msk          (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos)  /*!< 0x10000000 */

+#define DBGMCU_CR_DBG_TRGOEN              DBGMCU_CR_DBG_TRGOEN_Msk

+

+/********************  Bit definition for APB3FZ1 register  ************/

+#define DBGMCU_APB3FZ1_DBG_WWDG1_Pos      (6U)

+#define DBGMCU_APB3FZ1_DBG_WWDG1_Msk      (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB3FZ1_DBG_WWDG1          DBGMCU_APB3FZ1_DBG_WWDG1_Msk

+/********************  Bit definition for APB1LFZ1 register  ************/

+#define DBGMCU_APB1LFZ1_DBG_TIM2_Pos      (0U)

+#define DBGMCU_APB1LFZ1_DBG_TIM2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB1LFZ1_DBG_TIM2          DBGMCU_APB1LFZ1_DBG_TIM2_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM3_Pos      (1U)

+#define DBGMCU_APB1LFZ1_DBG_TIM3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB1LFZ1_DBG_TIM3          DBGMCU_APB1LFZ1_DBG_TIM3_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM4_Pos      (2U)

+#define DBGMCU_APB1LFZ1_DBG_TIM4_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */

+#define DBGMCU_APB1LFZ1_DBG_TIM4          DBGMCU_APB1LFZ1_DBG_TIM4_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM5_Pos      (3U)

+#define DBGMCU_APB1LFZ1_DBG_TIM5_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */

+#define DBGMCU_APB1LFZ1_DBG_TIM5          DBGMCU_APB1LFZ1_DBG_TIM5_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM6_Pos      (4U)

+#define DBGMCU_APB1LFZ1_DBG_TIM6_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */

+#define DBGMCU_APB1LFZ1_DBG_TIM6          DBGMCU_APB1LFZ1_DBG_TIM6_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM7_Pos      (5U)

+#define DBGMCU_APB1LFZ1_DBG_TIM7_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */

+#define DBGMCU_APB1LFZ1_DBG_TIM7          DBGMCU_APB1LFZ1_DBG_TIM7_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM12_Pos     (6U)

+#define DBGMCU_APB1LFZ1_DBG_TIM12_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */

+#define DBGMCU_APB1LFZ1_DBG_TIM12         DBGMCU_APB1LFZ1_DBG_TIM12_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM13_Pos     (7U)

+#define DBGMCU_APB1LFZ1_DBG_TIM13_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB1LFZ1_DBG_TIM13         DBGMCU_APB1LFZ1_DBG_TIM13_Msk

+#define DBGMCU_APB1LFZ1_DBG_TIM14_Pos     (8U)

+#define DBGMCU_APB1LFZ1_DBG_TIM14_Msk     (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */

+#define DBGMCU_APB1LFZ1_DBG_TIM14         DBGMCU_APB1LFZ1_DBG_TIM14_Msk

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos    (9U)

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk    (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB1LFZ1_DBG_LPTIM1        DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C1_Pos      (21U)

+#define DBGMCU_APB1LFZ1_DBG_I2C1_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C1          DBGMCU_APB1LFZ1_DBG_I2C1_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C2_Pos      (22U)

+#define DBGMCU_APB1LFZ1_DBG_I2C2_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C2          DBGMCU_APB1LFZ1_DBG_I2C2_Msk

+#define DBGMCU_APB1LFZ1_DBG_I2C3_Pos      (23U)

+#define DBGMCU_APB1LFZ1_DBG_I2C3_Msk      (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */

+#define DBGMCU_APB1LFZ1_DBG_I2C3          DBGMCU_APB1LFZ1_DBG_I2C3_Msk

+

+/********************  Bit definition for APB2FZ1 register  ************/

+#define DBGMCU_APB2FZ1_DBG_TIM1_Pos       (0U)

+#define DBGMCU_APB2FZ1_DBG_TIM1_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */

+#define DBGMCU_APB2FZ1_DBG_TIM1           DBGMCU_APB2FZ1_DBG_TIM1_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM8_Pos       (1U)

+#define DBGMCU_APB2FZ1_DBG_TIM8_Msk       (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */

+#define DBGMCU_APB2FZ1_DBG_TIM8           DBGMCU_APB2FZ1_DBG_TIM8_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM15_Pos      (16U)

+#define DBGMCU_APB2FZ1_DBG_TIM15_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB2FZ1_DBG_TIM15          DBGMCU_APB2FZ1_DBG_TIM15_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM16_Pos      (17U)

+#define DBGMCU_APB2FZ1_DBG_TIM16_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */

+#define DBGMCU_APB2FZ1_DBG_TIM16          DBGMCU_APB2FZ1_DBG_TIM16_Msk

+#define DBGMCU_APB2FZ1_DBG_TIM17_Pos      (18U)

+#define DBGMCU_APB2FZ1_DBG_TIM17_Msk      (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB2FZ1_DBG_TIM17          DBGMCU_APB2FZ1_DBG_TIM17_Msk

+/********************  Bit definition for APB4FZ1 register  ************/

+#define DBGMCU_APB4FZ1_DBG_I2C4_Pos       (7U)

+#define DBGMCU_APB4FZ1_DBG_I2C4_Msk       (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */

+#define DBGMCU_APB4FZ1_DBG_I2C4           DBGMCU_APB4FZ1_DBG_I2C4_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos     (9U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM2         DBGMCU_APB4FZ1_DBG_LPTIM2_Msk

+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos     (10U)

+#define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk     (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */

+#define DBGMCU_APB4FZ1_DBG_LPTIM3         DBGMCU_APB4FZ1_DBG_LPTIM3_Msk

+#define DBGMCU_APB4FZ1_DBG_RTC_Pos        (16U)

+#define DBGMCU_APB4FZ1_DBG_RTC_Msk        (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */

+#define DBGMCU_APB4FZ1_DBG_RTC            DBGMCU_APB4FZ1_DBG_RTC_Msk

+#define DBGMCU_APB4FZ1_DBG_IWDG1_Pos      (18U)

+#define DBGMCU_APB4FZ1_DBG_IWDG1_Msk      (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */

+#define DBGMCU_APB4FZ1_DBG_IWDG1          DBGMCU_APB4FZ1_DBG_IWDG1_Msk

+/******************************************************************************/

+/*                                                                            */

+/*                             RAM ECC monitoring                             */

+/*                                                                            */

+/******************************************************************************/

+/******************  Bit definition for RAMECC_IER register  ******************/

+#define RAMECC_IER_GECCDEBWIE_Pos         (3U)

+#define RAMECC_IER_GECCDEBWIE_Msk         (0x1UL << RAMECC_IER_GECCDEBWIE_Pos)  /*!< 0x00000008 */

+#define RAMECC_IER_GECCDEBWIE             RAMECC_IER_GECCDEBWIE_Msk             /*!< Global ECC double error on byte write (BW) interrupt enable */

+#define RAMECC_IER_GECCDEIE_Pos           (2U)

+#define RAMECC_IER_GECCDEIE_Msk           (0x1UL << RAMECC_IER_GECCDEIE_Pos)    /*!< 0x00000004 */

+#define RAMECC_IER_GECCDEIE               RAMECC_IER_GECCDEIE_Msk               /*!< Global ECC double error interrupt enable */

+#define RAMECC_IER_GECCSEIE_Pos           (1U)

+#define RAMECC_IER_GECCSEIE_Msk           (0x1UL << RAMECC_IER_GECCSEIE_Pos)    /*!< 0x00000002 */

+#define RAMECC_IER_GECCSEIE               RAMECC_IER_GECCSEIE_Msk               /*!< Global ECC single error interrupt enable */

+#define RAMECC_IER_GIE_Pos                (0U)

+#define RAMECC_IER_GIE_Msk                (0x1UL << RAMECC_IER_GIE_Pos)         /*!< 0x00000001 */

+#define RAMECC_IER_GIE                    RAMECC_IER_GIE_Msk                    /*!< Global interrupt enable */

+

+/*******************  Bit definition for RAMECC_CR register  ******************/

+#define RAMECC_CR_ECCELEN_Pos             (5U)

+#define RAMECC_CR_ECCELEN_Msk             (0x1UL << RAMECC_CR_ECCELEN_Pos)      /*!< 0x00000020 */

+#define RAMECC_CR_ECCELEN                 RAMECC_CR_ECCELEN_Msk                 /*!< ECC error latching enable */

+#define RAMECC_CR_ECCDEBWIE_Pos           (4U)

+#define RAMECC_CR_ECCDEBWIE_Msk           (0x1UL << RAMECC_CR_ECCDEBWIE_Pos)    /*!< 0x00000010 */

+#define RAMECC_CR_ECCDEBWIE               RAMECC_CR_ECCDEBWIE_Msk               /*!< ECC double error on byte write (BW) interrupt enable */

+#define RAMECC_CR_ECCDEIE_Pos             (3U)

+#define RAMECC_CR_ECCDEIE_Msk             (0x1UL << RAMECC_CR_ECCDEIE_Pos)      /*!< 0x00000008 */

+#define RAMECC_CR_ECCDEIE                 RAMECC_CR_ECCDEIE_Msk                 /*!< ECC double error interrupt enable */

+#define RAMECC_CR_ECCSEIE_Pos             (2U)

+#define RAMECC_CR_ECCSEIE_Msk             (0x1UL << RAMECC_CR_ECCSEIE_Pos)      /*!< 0x00000004 */

+#define RAMECC_CR_ECCSEIE                 RAMECC_CR_ECCSEIE_Msk                 /*!< ECC single error interrupt enable */

+

+/*******************  Bit definition for RAMECC_SR register  ******************/

+#define RAMECC_SR_DEBWDF_Pos             (2U)

+#define RAMECC_SR_DEBWDF_Msk             (0x1UL << RAMECC_SR_DEBWDF_Pos)        /*!< 0x00000004 */

+#define RAMECC_SR_DEBWDF                 RAMECC_SR_DEBWDF_Msk                   /*!< ECC double error on byte write (BW) detected flag */

+#define RAMECC_SR_DEDF_Pos               (1U)

+#define RAMECC_SR_DEDF_Msk               (0x1UL << RAMECC_SR_DEDF_Pos)          /*!< 0x00000002 */

+#define RAMECC_SR_DEDF                   RAMECC_SR_DEDF_Msk                     /*!< ECC double error detected flag */

+#define RAMECC_SR_SEDCF_Pos              (0U)

+#define RAMECC_SR_SEDCF_Msk              (0x1UL << RAMECC_SR_SEDCF_Pos)         /*!< 0x00000001 */

+#define RAMECC_SR_SEDCF                  RAMECC_SR_SEDCF_Msk                    /*!< ECC single error detected and corrected flag */

+

+/******************  Bit definition for RAMECC_FAR register  ******************/

+#define RAMECC_FAR_FADD_Pos              (0U)

+#define RAMECC_FAR_FADD_Msk              (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos)  /*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FADD                  RAMECC_FAR_FADD_Msk                    /*!< ECC error failing address */

+

+/******************  Bit definition for RAMECC_FDRL register  *****************/

+#define RAMECC_FAR_FDATAL_Pos            (0U)

+#define RAMECC_FAR_FDATAL_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FDATAL                RAMECC_FAR_FDATAL_Msk                  /*!< ECC error failing address */

+

+/******************  Bit definition for RAMECC_FDRH register  *****************/

+#define RAMECC_FAR_FDATAH_Pos            (0U)

+#define RAMECC_FAR_FDATAH_Msk            (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */

+#define RAMECC_FAR_FDATAH                RAMECC_FAR_FDATAH_Msk                  /* Failing data high (64-bit memory) */

+

+/*****************  Bit definition for RAMECC_FECR register  ******************/

+#define RAMECC_FECR_FEC_Pos              (0U)

+#define RAMECC_FECR_FEC_Msk              (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos)  /*!< 0xFFFFFFFF */

+#define RAMECC_FECR_FEC                  RAMECC_FECR_FEC_Msk                    /*!< Failing error code */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                MDIOS                                        */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition for MDIOS_CR register  *******************/

+#define MDIOS_CR_EN_Pos                (0U)

+#define MDIOS_CR_EN_Msk                (0x1UL << MDIOS_CR_EN_Pos)              /*!< 0x00000001 */

+#define MDIOS_CR_EN                    MDIOS_CR_EN_Msk                         /*!<  MDIOS slave peripheral enable */

+#define MDIOS_CR_WRIE_Pos              (1U)

+#define MDIOS_CR_WRIE_Msk              (0x1UL << MDIOS_CR_WRIE_Pos)            /*!< 0x00000002 */

+#define MDIOS_CR_WRIE                  MDIOS_CR_WRIE_Msk                       /*!<  MDIOS slave register write interrupt enable. */

+#define MDIOS_CR_RDIE_Pos              (2U)

+#define MDIOS_CR_RDIE_Msk              (0x1UL << MDIOS_CR_RDIE_Pos)            /*!< 0x00000004 */

+#define MDIOS_CR_RDIE                  MDIOS_CR_RDIE_Msk                       /*!<  MDIOS slave register read interrupt enable. */

+#define MDIOS_CR_EIE_Pos               (3U)

+#define MDIOS_CR_EIE_Msk               (0x1UL << MDIOS_CR_EIE_Pos)             /*!< 0x00000008 */

+#define MDIOS_CR_EIE                   MDIOS_CR_EIE_Msk                        /*!<  MDIOS slave register error interrupt enable. */

+#define MDIOS_CR_DPC_Pos               (7U)

+#define MDIOS_CR_DPC_Msk               (0x1UL << MDIOS_CR_DPC_Pos)             /*!< 0x00000080 */

+#define MDIOS_CR_DPC                   MDIOS_CR_DPC_Msk                        /*!<  MDIOS slave disable preamble check. */

+#define MDIOS_CR_PORT_ADDRESS_Pos      (8U)

+#define MDIOS_CR_PORT_ADDRESS_Msk      (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos)   /*!< 0x00001F00 */

+#define MDIOS_CR_PORT_ADDRESS          MDIOS_CR_PORT_ADDRESS_Msk               /*!<  MDIOS slave port address mask. */

+#define MDIOS_CR_PORT_ADDRESS_0        (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000100 */

+#define MDIOS_CR_PORT_ADDRESS_1        (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000200 */

+#define MDIOS_CR_PORT_ADDRESS_2        (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000400 */

+#define MDIOS_CR_PORT_ADDRESS_3        (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00000800 */

+#define MDIOS_CR_PORT_ADDRESS_4        (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos)    /*!< 0x00001000 */

+

+/********************  Bit definition for MDIOS_SR register  *******************/

+#define MDIOS_SR_PERF_Pos              (0U)

+#define MDIOS_SR_PERF_Msk              (0x1UL << MDIOS_SR_PERF_Pos)            /*!< 0x00000001 */

+#define MDIOS_SR_PERF                  MDIOS_SR_PERF_Msk                       /*!<  MDIOS slave turnaround error flag*/

+#define MDIOS_SR_SERF_Pos              (1U)

+#define MDIOS_SR_SERF_Msk              (0x1UL << MDIOS_SR_SERF_Pos)            /*!< 0x00000002 */

+#define MDIOS_SR_SERF                  MDIOS_SR_SERF_Msk                       /*!<  MDIOS slave start error flag */

+#define MDIOS_SR_TERF_Pos              (2U)

+#define MDIOS_SR_TERF_Msk              (0x1UL << MDIOS_SR_TERF_Pos)            /*!< 0x00000004 */

+#define MDIOS_SR_TERF                  MDIOS_SR_TERF_Msk                       /*!<  MDIOS slave preamble error flag */

+

+/********************  Bit definition for MDIOS_CLRFR register  *******************/

+#define MDIOS_SR_CPERF_Pos             (0U)

+#define MDIOS_SR_CPERF_Msk             (0x1UL << MDIOS_SR_CPERF_Pos)           /*!< 0x00000001 */

+#define MDIOS_SR_CPERF                 MDIOS_SR_CPERF_Msk                      /*!<  MDIOS slave Clear the turnaround error flag */

+#define MDIOS_SR_CSERF_Pos             (1U)

+#define MDIOS_SR_CSERF_Msk             (0x1UL << MDIOS_SR_CSERF_Pos)           /*!< 0x00000002 */

+#define MDIOS_SR_CSERF                 MDIOS_SR_CSERF_Msk                      /*!<  MDIOS slave Clear the start error flag */

+#define MDIOS_SR_CTERF_Pos             (2U)

+#define MDIOS_SR_CTERF_Msk             (0x1UL << MDIOS_SR_CTERF_Pos)           /*!< 0x00000004 */

+#define MDIOS_SR_CTERF                 MDIOS_SR_CTERF_Msk                      /*!<  MDIOS slave Clear the preamble error flag */

+

+/******************************************************************************/

+/*                                                                            */

+/*                                       USB_OTG                              */

+/*                                                                            */

+/******************************************************************************/

+/********************  Bit definition forUSB_OTG_GOTGCTL register  ********************/

+#define USB_OTG_GOTGCTL_SRQSCS_Pos               (0U)

+#define USB_OTG_GOTGCTL_SRQSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */

+#define USB_OTG_GOTGCTL_SRQSCS                   USB_OTG_GOTGCTL_SRQSCS_Msk    /*!< Session request success */

+#define USB_OTG_GOTGCTL_SRQ_Pos                  (1U)

+#define USB_OTG_GOTGCTL_SRQ_Msk                  (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */

+#define USB_OTG_GOTGCTL_SRQ                      USB_OTG_GOTGCTL_SRQ_Msk       /*!< Session request */

+#define USB_OTG_GOTGCTL_VBVALOEN_Pos             (2U)

+#define USB_OTG_GOTGCTL_VBVALOEN_Msk             (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */

+#define USB_OTG_GOTGCTL_VBVALOEN                 USB_OTG_GOTGCTL_VBVALOEN_Msk  /*!< VBUS valid override enable */

+#define USB_OTG_GOTGCTL_VBVALOVAL_Pos            (3U)

+#define USB_OTG_GOTGCTL_VBVALOVAL_Msk            (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */

+#define USB_OTG_GOTGCTL_VBVALOVAL                USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */

+#define USB_OTG_GOTGCTL_AVALOEN_Pos              (4U)

+#define USB_OTG_GOTGCTL_AVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */

+#define USB_OTG_GOTGCTL_AVALOEN                  USB_OTG_GOTGCTL_AVALOEN_Msk   /*!< A-peripheral session valid override enable */

+#define USB_OTG_GOTGCTL_AVALOVAL_Pos             (5U)

+#define USB_OTG_GOTGCTL_AVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */

+#define USB_OTG_GOTGCTL_AVALOVAL                 USB_OTG_GOTGCTL_AVALOVAL_Msk  /*!< A-peripheral session valid override value */

+#define USB_OTG_GOTGCTL_BVALOEN_Pos              (6U)

+#define USB_OTG_GOTGCTL_BVALOEN_Msk              (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */

+#define USB_OTG_GOTGCTL_BVALOEN                  USB_OTG_GOTGCTL_BVALOEN_Msk   /*!< B-peripheral session valid override enable */

+#define USB_OTG_GOTGCTL_BVALOVAL_Pos             (7U)

+#define USB_OTG_GOTGCTL_BVALOVAL_Msk             (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */

+#define USB_OTG_GOTGCTL_BVALOVAL                 USB_OTG_GOTGCTL_BVALOVAL_Msk  /*!< B-peripheral session valid override value  */

+#define USB_OTG_GOTGCTL_HNGSCS_Pos               (8U)

+#define USB_OTG_GOTGCTL_HNGSCS_Msk               (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */

+#define USB_OTG_GOTGCTL_HNGSCS                   USB_OTG_GOTGCTL_HNGSCS_Msk    /*!< Host set HNP enable */

+#define USB_OTG_GOTGCTL_HNPRQ_Pos                (9U)

+#define USB_OTG_GOTGCTL_HNPRQ_Msk                (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */

+#define USB_OTG_GOTGCTL_HNPRQ                    USB_OTG_GOTGCTL_HNPRQ_Msk     /*!< HNP request */

+#define USB_OTG_GOTGCTL_HSHNPEN_Pos              (10U)

+#define USB_OTG_GOTGCTL_HSHNPEN_Msk              (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */

+#define USB_OTG_GOTGCTL_HSHNPEN                  USB_OTG_GOTGCTL_HSHNPEN_Msk   /*!< Host set HNP enable */

+#define USB_OTG_GOTGCTL_DHNPEN_Pos               (11U)

+#define USB_OTG_GOTGCTL_DHNPEN_Msk               (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */

+#define USB_OTG_GOTGCTL_DHNPEN                   USB_OTG_GOTGCTL_DHNPEN_Msk    /*!< Device HNP enabled */

+#define USB_OTG_GOTGCTL_EHEN_Pos                 (12U)

+#define USB_OTG_GOTGCTL_EHEN_Msk                 (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */

+#define USB_OTG_GOTGCTL_EHEN                     USB_OTG_GOTGCTL_EHEN_Msk      /*!< Embedded host enable */

+#define USB_OTG_GOTGCTL_CIDSTS_Pos               (16U)

+#define USB_OTG_GOTGCTL_CIDSTS_Msk               (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */

+#define USB_OTG_GOTGCTL_CIDSTS                   USB_OTG_GOTGCTL_CIDSTS_Msk    /*!< Connector ID status */

+#define USB_OTG_GOTGCTL_DBCT_Pos                 (17U)

+#define USB_OTG_GOTGCTL_DBCT_Msk                 (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */

+#define USB_OTG_GOTGCTL_DBCT                     USB_OTG_GOTGCTL_DBCT_Msk      /*!< Long/short debounce time */

+#define USB_OTG_GOTGCTL_ASVLD_Pos                (18U)

+#define USB_OTG_GOTGCTL_ASVLD_Msk                (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */

+#define USB_OTG_GOTGCTL_ASVLD                    USB_OTG_GOTGCTL_ASVLD_Msk     /*!< A-session valid  */

+#define USB_OTG_GOTGCTL_BSESVLD_Pos              (19U)

+#define USB_OTG_GOTGCTL_BSESVLD_Msk              (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */

+#define USB_OTG_GOTGCTL_BSESVLD                  USB_OTG_GOTGCTL_BSESVLD_Msk   /*!< B-session valid */

+#define USB_OTG_GOTGCTL_OTGVER_Pos               (20U)

+#define USB_OTG_GOTGCTL_OTGVER_Msk               (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */

+#define USB_OTG_GOTGCTL_OTGVER                   USB_OTG_GOTGCTL_OTGVER_Msk    /*!< OTG version  */

+

+/********************  Bit definition forUSB_OTG_HCFG register  ********************/

+

+#define USB_OTG_HCFG_FSLSPCS_Pos                 (0U)

+#define USB_OTG_HCFG_FSLSPCS_Msk                 (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */

+#define USB_OTG_HCFG_FSLSPCS                     USB_OTG_HCFG_FSLSPCS_Msk      /*!< FS/LS PHY clock select  */

+#define USB_OTG_HCFG_FSLSPCS_0                   (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCFG_FSLSPCS_1                   (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCFG_FSLSS_Pos                   (2U)

+#define USB_OTG_HCFG_FSLSS_Msk                   (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCFG_FSLSS                       USB_OTG_HCFG_FSLSS_Msk        /*!< FS- and LS-only support */

+

+/********************  Bit definition forUSB_OTG_DCFG register  ********************/

+

+#define USB_OTG_DCFG_DSPD_Pos                    (0U)

+#define USB_OTG_DCFG_DSPD_Msk                    (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */

+#define USB_OTG_DCFG_DSPD                        USB_OTG_DCFG_DSPD_Msk         /*!< Device speed */

+#define USB_OTG_DCFG_DSPD_0                      (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */

+#define USB_OTG_DCFG_DSPD_1                      (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DCFG_NZLSOHSK_Pos                (2U)

+#define USB_OTG_DCFG_NZLSOHSK_Msk                (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */

+#define USB_OTG_DCFG_NZLSOHSK                    USB_OTG_DCFG_NZLSOHSK_Msk     /*!< Nonzero-length status OUT handshake */

+

+#define USB_OTG_DCFG_DAD_Pos                     (4U)

+#define USB_OTG_DCFG_DAD_Msk                     (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */

+#define USB_OTG_DCFG_DAD                         USB_OTG_DCFG_DAD_Msk          /*!< Device address */

+#define USB_OTG_DCFG_DAD_0                       (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */

+#define USB_OTG_DCFG_DAD_1                       (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */

+#define USB_OTG_DCFG_DAD_2                       (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */

+#define USB_OTG_DCFG_DAD_3                       (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */

+#define USB_OTG_DCFG_DAD_4                       (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */

+#define USB_OTG_DCFG_DAD_5                       (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */

+#define USB_OTG_DCFG_DAD_6                       (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */

+

+#define USB_OTG_DCFG_PFIVL_Pos                   (11U)

+#define USB_OTG_DCFG_PFIVL_Msk                   (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */

+#define USB_OTG_DCFG_PFIVL                       USB_OTG_DCFG_PFIVL_Msk        /*!< Periodic (micro)frame interval */

+#define USB_OTG_DCFG_PFIVL_0                     (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */

+#define USB_OTG_DCFG_PFIVL_1                     (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */

+

+#define USB_OTG_DCFG_PERSCHIVL_Pos               (24U)

+#define USB_OTG_DCFG_PERSCHIVL_Msk               (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */

+#define USB_OTG_DCFG_PERSCHIVL                   USB_OTG_DCFG_PERSCHIVL_Msk    /*!< Periodic scheduling interval */

+#define USB_OTG_DCFG_PERSCHIVL_0                 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */

+#define USB_OTG_DCFG_PERSCHIVL_1                 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */

+

+/********************  Bit definition forUSB_OTG_PCGCR register  ********************/

+#define USB_OTG_PCGCR_STPPCLK_Pos                (0U)

+#define USB_OTG_PCGCR_STPPCLK_Msk                (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */

+#define USB_OTG_PCGCR_STPPCLK                    USB_OTG_PCGCR_STPPCLK_Msk     /*!< Stop PHY clock */

+#define USB_OTG_PCGCR_GATEHCLK_Pos               (1U)

+#define USB_OTG_PCGCR_GATEHCLK_Msk               (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */

+#define USB_OTG_PCGCR_GATEHCLK                   USB_OTG_PCGCR_GATEHCLK_Msk    /*!< Gate HCLK */

+#define USB_OTG_PCGCR_PHYSUSP_Pos                (4U)

+#define USB_OTG_PCGCR_PHYSUSP_Msk                (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */

+#define USB_OTG_PCGCR_PHYSUSP                    USB_OTG_PCGCR_PHYSUSP_Msk     /*!< PHY suspended */

+

+/********************  Bit definition forUSB_OTG_GOTGINT register  ********************/

+#define USB_OTG_GOTGINT_SEDET_Pos                (2U)

+#define USB_OTG_GOTGINT_SEDET_Msk                (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */

+#define USB_OTG_GOTGINT_SEDET                    USB_OTG_GOTGINT_SEDET_Msk     /*!< Session end detected                   */

+#define USB_OTG_GOTGINT_SRSSCHG_Pos              (8U)

+#define USB_OTG_GOTGINT_SRSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */

+#define USB_OTG_GOTGINT_SRSSCHG                  USB_OTG_GOTGINT_SRSSCHG_Msk   /*!< Session request success status change  */

+#define USB_OTG_GOTGINT_HNSSCHG_Pos              (9U)

+#define USB_OTG_GOTGINT_HNSSCHG_Msk              (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */

+#define USB_OTG_GOTGINT_HNSSCHG                  USB_OTG_GOTGINT_HNSSCHG_Msk   /*!< Host negotiation success status change */

+#define USB_OTG_GOTGINT_HNGDET_Pos               (17U)

+#define USB_OTG_GOTGINT_HNGDET_Msk               (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */

+#define USB_OTG_GOTGINT_HNGDET                   USB_OTG_GOTGINT_HNGDET_Msk    /*!< Host negotiation detected              */

+#define USB_OTG_GOTGINT_ADTOCHG_Pos              (18U)

+#define USB_OTG_GOTGINT_ADTOCHG_Msk              (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */

+#define USB_OTG_GOTGINT_ADTOCHG                  USB_OTG_GOTGINT_ADTOCHG_Msk   /*!< A-device timeout change                */

+#define USB_OTG_GOTGINT_DBCDNE_Pos               (19U)

+#define USB_OTG_GOTGINT_DBCDNE_Msk               (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */

+#define USB_OTG_GOTGINT_DBCDNE                   USB_OTG_GOTGINT_DBCDNE_Msk    /*!< Debounce done                          */

+

+/********************  Bit definition forUSB_OTG_DCTL register  ********************/

+#define USB_OTG_DCTL_RWUSIG_Pos                  (0U)

+#define USB_OTG_DCTL_RWUSIG_Msk                  (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */

+#define USB_OTG_DCTL_RWUSIG                      USB_OTG_DCTL_RWUSIG_Msk       /*!< Remote wakeup signaling */

+#define USB_OTG_DCTL_SDIS_Pos                    (1U)

+#define USB_OTG_DCTL_SDIS_Msk                    (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */

+#define USB_OTG_DCTL_SDIS                        USB_OTG_DCTL_SDIS_Msk         /*!< Soft disconnect         */

+#define USB_OTG_DCTL_GINSTS_Pos                  (2U)

+#define USB_OTG_DCTL_GINSTS_Msk                  (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */

+#define USB_OTG_DCTL_GINSTS                      USB_OTG_DCTL_GINSTS_Msk       /*!< Global IN NAK status    */

+#define USB_OTG_DCTL_GONSTS_Pos                  (3U)

+#define USB_OTG_DCTL_GONSTS_Msk                  (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */

+#define USB_OTG_DCTL_GONSTS                      USB_OTG_DCTL_GONSTS_Msk       /*!< Global OUT NAK status   */

+

+#define USB_OTG_DCTL_TCTL_Pos                    (4U)

+#define USB_OTG_DCTL_TCTL_Msk                    (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */

+#define USB_OTG_DCTL_TCTL                        USB_OTG_DCTL_TCTL_Msk         /*!< Test control */

+#define USB_OTG_DCTL_TCTL_0                      (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */

+#define USB_OTG_DCTL_TCTL_1                      (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */

+#define USB_OTG_DCTL_TCTL_2                      (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */

+#define USB_OTG_DCTL_SGINAK_Pos                  (7U)

+#define USB_OTG_DCTL_SGINAK_Msk                  (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */

+#define USB_OTG_DCTL_SGINAK                      USB_OTG_DCTL_SGINAK_Msk       /*!< Set global IN NAK         */

+#define USB_OTG_DCTL_CGINAK_Pos                  (8U)

+#define USB_OTG_DCTL_CGINAK_Msk                  (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */

+#define USB_OTG_DCTL_CGINAK                      USB_OTG_DCTL_CGINAK_Msk       /*!< Clear global IN NAK       */

+#define USB_OTG_DCTL_SGONAK_Pos                  (9U)

+#define USB_OTG_DCTL_SGONAK_Msk                  (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */

+#define USB_OTG_DCTL_SGONAK                      USB_OTG_DCTL_SGONAK_Msk       /*!< Set global OUT NAK        */

+#define USB_OTG_DCTL_CGONAK_Pos                  (10U)

+#define USB_OTG_DCTL_CGONAK_Msk                  (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */

+#define USB_OTG_DCTL_CGONAK                      USB_OTG_DCTL_CGONAK_Msk       /*!< Clear global OUT NAK      */

+#define USB_OTG_DCTL_POPRGDNE_Pos                (11U)

+#define USB_OTG_DCTL_POPRGDNE_Msk                (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */

+#define USB_OTG_DCTL_POPRGDNE                    USB_OTG_DCTL_POPRGDNE_Msk     /*!< Power-on programming done */

+

+/********************  Bit definition forUSB_OTG_HFIR register  ********************/

+#define USB_OTG_HFIR_FRIVL_Pos                   (0U)

+#define USB_OTG_HFIR_FRIVL_Msk                   (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HFIR_FRIVL                       USB_OTG_HFIR_FRIVL_Msk        /*!< Frame interval */

+

+/********************  Bit definition forUSB_OTG_HFNUM register  ********************/

+#define USB_OTG_HFNUM_FRNUM_Pos                  (0U)

+#define USB_OTG_HFNUM_FRNUM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HFNUM_FRNUM                      USB_OTG_HFNUM_FRNUM_Msk       /*!< Frame number         */

+#define USB_OTG_HFNUM_FTREM_Pos                  (16U)

+#define USB_OTG_HFNUM_FTREM_Msk                  (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_HFNUM_FTREM                      USB_OTG_HFNUM_FTREM_Msk       /*!< Frame time remaining */

+

+/********************  Bit definition forUSB_OTG_DSTS register  ********************/

+#define USB_OTG_DSTS_SUSPSTS_Pos                 (0U)

+#define USB_OTG_DSTS_SUSPSTS_Msk                 (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */

+#define USB_OTG_DSTS_SUSPSTS                     USB_OTG_DSTS_SUSPSTS_Msk      /*!< Suspend status   */

+

+#define USB_OTG_DSTS_ENUMSPD_Pos                 (1U)

+#define USB_OTG_DSTS_ENUMSPD_Msk                 (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */

+#define USB_OTG_DSTS_ENUMSPD                     USB_OTG_DSTS_ENUMSPD_Msk      /*!< Enumerated speed */

+#define USB_OTG_DSTS_ENUMSPD_0                   (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DSTS_ENUMSPD_1                   (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */

+#define USB_OTG_DSTS_EERR_Pos                    (3U)

+#define USB_OTG_DSTS_EERR_Msk                    (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */

+#define USB_OTG_DSTS_EERR                        USB_OTG_DSTS_EERR_Msk         /*!< Erratic error     */

+#define USB_OTG_DSTS_FNSOF_Pos                   (8U)

+#define USB_OTG_DSTS_FNSOF_Msk                   (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */

+#define USB_OTG_DSTS_FNSOF                       USB_OTG_DSTS_FNSOF_Msk        /*!< Frame number of the received SOF */

+

+/********************  Bit definition forUSB_OTG_GAHBCFG register  ********************/

+#define USB_OTG_GAHBCFG_GINT_Pos                 (0U)

+#define USB_OTG_GAHBCFG_GINT_Msk                 (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */

+#define USB_OTG_GAHBCFG_GINT                     USB_OTG_GAHBCFG_GINT_Msk      /*!< Global interrupt mask */

+

+#define USB_OTG_GAHBCFG_HBSTLEN_Pos              (1U)

+#define USB_OTG_GAHBCFG_HBSTLEN_Msk              (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */

+#define USB_OTG_GAHBCFG_HBSTLEN                  USB_OTG_GAHBCFG_HBSTLEN_Msk   /*!< Burst length/type */

+#define USB_OTG_GAHBCFG_HBSTLEN_0                (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */

+#define USB_OTG_GAHBCFG_HBSTLEN_1                (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */

+#define USB_OTG_GAHBCFG_HBSTLEN_2                (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */

+#define USB_OTG_GAHBCFG_HBSTLEN_3                (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */

+#define USB_OTG_GAHBCFG_HBSTLEN_4                (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */

+#define USB_OTG_GAHBCFG_DMAEN_Pos                (5U)

+#define USB_OTG_GAHBCFG_DMAEN_Msk                (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */

+#define USB_OTG_GAHBCFG_DMAEN                    USB_OTG_GAHBCFG_DMAEN_Msk     /*!< DMA enable */

+#define USB_OTG_GAHBCFG_TXFELVL_Pos              (7U)

+#define USB_OTG_GAHBCFG_TXFELVL_Msk              (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */

+#define USB_OTG_GAHBCFG_TXFELVL                  USB_OTG_GAHBCFG_TXFELVL_Msk   /*!< TxFIFO empty level */

+#define USB_OTG_GAHBCFG_PTXFELVL_Pos             (8U)

+#define USB_OTG_GAHBCFG_PTXFELVL_Msk             (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */

+#define USB_OTG_GAHBCFG_PTXFELVL                 USB_OTG_GAHBCFG_PTXFELVL_Msk  /*!< Periodic TxFIFO empty level */

+

+/********************  Bit definition forUSB_OTG_GUSBCFG register  ********************/

+

+#define USB_OTG_GUSBCFG_TOCAL_Pos                (0U)

+#define USB_OTG_GUSBCFG_TOCAL_Msk                (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */

+#define USB_OTG_GUSBCFG_TOCAL                    USB_OTG_GUSBCFG_TOCAL_Msk     /*!< FS timeout calibration */

+#define USB_OTG_GUSBCFG_TOCAL_0                  (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */

+#define USB_OTG_GUSBCFG_TOCAL_1                  (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */

+#define USB_OTG_GUSBCFG_TOCAL_2                  (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */

+#define USB_OTG_GUSBCFG_PHYSEL_Pos               (6U)

+#define USB_OTG_GUSBCFG_PHYSEL_Msk               (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */

+#define USB_OTG_GUSBCFG_PHYSEL                   USB_OTG_GUSBCFG_PHYSEL_Msk    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */

+#define USB_OTG_GUSBCFG_SRPCAP_Pos               (8U)

+#define USB_OTG_GUSBCFG_SRPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */

+#define USB_OTG_GUSBCFG_SRPCAP                   USB_OTG_GUSBCFG_SRPCAP_Msk    /*!< SRP-capable */

+#define USB_OTG_GUSBCFG_HNPCAP_Pos               (9U)

+#define USB_OTG_GUSBCFG_HNPCAP_Msk               (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */

+#define USB_OTG_GUSBCFG_HNPCAP                   USB_OTG_GUSBCFG_HNPCAP_Msk    /*!< HNP-capable */

+

+#define USB_OTG_GUSBCFG_TRDT_Pos                 (10U)

+#define USB_OTG_GUSBCFG_TRDT_Msk                 (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */

+#define USB_OTG_GUSBCFG_TRDT                     USB_OTG_GUSBCFG_TRDT_Msk      /*!< USB turnaround time */

+#define USB_OTG_GUSBCFG_TRDT_0                   (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */

+#define USB_OTG_GUSBCFG_TRDT_1                   (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */

+#define USB_OTG_GUSBCFG_TRDT_2                   (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */

+#define USB_OTG_GUSBCFG_TRDT_3                   (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */

+#define USB_OTG_GUSBCFG_PHYLPCS_Pos              (15U)

+#define USB_OTG_GUSBCFG_PHYLPCS_Msk              (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */

+#define USB_OTG_GUSBCFG_PHYLPCS                  USB_OTG_GUSBCFG_PHYLPCS_Msk   /*!< PHY Low-power clock select */

+#define USB_OTG_GUSBCFG_ULPIFSLS_Pos             (17U)

+#define USB_OTG_GUSBCFG_ULPIFSLS_Msk             (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */

+#define USB_OTG_GUSBCFG_ULPIFSLS                 USB_OTG_GUSBCFG_ULPIFSLS_Msk  /*!< ULPI FS/LS select               */

+#define USB_OTG_GUSBCFG_ULPIAR_Pos               (18U)

+#define USB_OTG_GUSBCFG_ULPIAR_Msk               (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */

+#define USB_OTG_GUSBCFG_ULPIAR                   USB_OTG_GUSBCFG_ULPIAR_Msk    /*!< ULPI Auto-resume                */

+#define USB_OTG_GUSBCFG_ULPICSM_Pos              (19U)

+#define USB_OTG_GUSBCFG_ULPICSM_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */

+#define USB_OTG_GUSBCFG_ULPICSM                  USB_OTG_GUSBCFG_ULPICSM_Msk   /*!< ULPI Clock SuspendM             */

+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos           (20U)

+#define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */

+#define USB_OTG_GUSBCFG_ULPIEVBUSD               USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive        */

+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos           (21U)

+#define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk           (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */

+#define USB_OTG_GUSBCFG_ULPIEVBUSI               USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator    */

+#define USB_OTG_GUSBCFG_TSDPS_Pos                (22U)

+#define USB_OTG_GUSBCFG_TSDPS_Msk                (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */

+#define USB_OTG_GUSBCFG_TSDPS                    USB_OTG_GUSBCFG_TSDPS_Msk     /*!< TermSel DLine pulsing selection */

+#define USB_OTG_GUSBCFG_PCCI_Pos                 (23U)

+#define USB_OTG_GUSBCFG_PCCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */

+#define USB_OTG_GUSBCFG_PCCI                     USB_OTG_GUSBCFG_PCCI_Msk      /*!< Indicator complement            */

+#define USB_OTG_GUSBCFG_PTCI_Pos                 (24U)

+#define USB_OTG_GUSBCFG_PTCI_Msk                 (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */

+#define USB_OTG_GUSBCFG_PTCI                     USB_OTG_GUSBCFG_PTCI_Msk      /*!< Indicator pass through          */

+#define USB_OTG_GUSBCFG_ULPIIPD_Pos              (25U)

+#define USB_OTG_GUSBCFG_ULPIIPD_Msk              (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */

+#define USB_OTG_GUSBCFG_ULPIIPD                  USB_OTG_GUSBCFG_ULPIIPD_Msk   /*!< ULPI interface protect disable  */

+#define USB_OTG_GUSBCFG_FHMOD_Pos                (29U)

+#define USB_OTG_GUSBCFG_FHMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */

+#define USB_OTG_GUSBCFG_FHMOD                    USB_OTG_GUSBCFG_FHMOD_Msk     /*!< Forced host mode                */

+#define USB_OTG_GUSBCFG_FDMOD_Pos                (30U)

+#define USB_OTG_GUSBCFG_FDMOD_Msk                (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */

+#define USB_OTG_GUSBCFG_FDMOD                    USB_OTG_GUSBCFG_FDMOD_Msk     /*!< Forced peripheral mode          */

+#define USB_OTG_GUSBCFG_CTXPKT_Pos               (31U)

+#define USB_OTG_GUSBCFG_CTXPKT_Msk               (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */

+#define USB_OTG_GUSBCFG_CTXPKT                   USB_OTG_GUSBCFG_CTXPKT_Msk    /*!< Corrupt Tx packet               */

+

+/********************  Bit definition forUSB_OTG_GRSTCTL register  ********************/

+#define USB_OTG_GRSTCTL_CSRST_Pos                (0U)

+#define USB_OTG_GRSTCTL_CSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */

+#define USB_OTG_GRSTCTL_CSRST                    USB_OTG_GRSTCTL_CSRST_Msk     /*!< Core soft reset          */

+#define USB_OTG_GRSTCTL_HSRST_Pos                (1U)

+#define USB_OTG_GRSTCTL_HSRST_Msk                (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */

+#define USB_OTG_GRSTCTL_HSRST                    USB_OTG_GRSTCTL_HSRST_Msk     /*!< HCLK soft reset          */

+#define USB_OTG_GRSTCTL_FCRST_Pos                (2U)

+#define USB_OTG_GRSTCTL_FCRST_Msk                (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */

+#define USB_OTG_GRSTCTL_FCRST                    USB_OTG_GRSTCTL_FCRST_Msk     /*!< Host frame counter reset */

+#define USB_OTG_GRSTCTL_RXFFLSH_Pos              (4U)

+#define USB_OTG_GRSTCTL_RXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */

+#define USB_OTG_GRSTCTL_RXFFLSH                  USB_OTG_GRSTCTL_RXFFLSH_Msk   /*!< RxFIFO flush             */

+#define USB_OTG_GRSTCTL_TXFFLSH_Pos              (5U)

+#define USB_OTG_GRSTCTL_TXFFLSH_Msk              (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */

+#define USB_OTG_GRSTCTL_TXFFLSH                  USB_OTG_GRSTCTL_TXFFLSH_Msk   /*!< TxFIFO flush             */

+

+#define USB_OTG_GRSTCTL_TXFNUM_Pos               (6U)

+#define USB_OTG_GRSTCTL_TXFNUM_Msk               (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */

+#define USB_OTG_GRSTCTL_TXFNUM                   USB_OTG_GRSTCTL_TXFNUM_Msk    /*!< TxFIFO number */

+#define USB_OTG_GRSTCTL_TXFNUM_0                 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */

+#define USB_OTG_GRSTCTL_TXFNUM_1                 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */

+#define USB_OTG_GRSTCTL_TXFNUM_2                 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */

+#define USB_OTG_GRSTCTL_TXFNUM_3                 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */

+#define USB_OTG_GRSTCTL_TXFNUM_4                 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */

+#define USB_OTG_GRSTCTL_DMAREQ_Pos               (30U)

+#define USB_OTG_GRSTCTL_DMAREQ_Msk               (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */

+#define USB_OTG_GRSTCTL_DMAREQ                   USB_OTG_GRSTCTL_DMAREQ_Msk    /*!< DMA request signal */

+#define USB_OTG_GRSTCTL_AHBIDL_Pos               (31U)

+#define USB_OTG_GRSTCTL_AHBIDL_Msk               (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */

+#define USB_OTG_GRSTCTL_AHBIDL                   USB_OTG_GRSTCTL_AHBIDL_Msk    /*!< AHB master idle */

+

+/********************  Bit definition forUSB_OTG_DIEPMSK register  ********************/

+#define USB_OTG_DIEPMSK_XFRCM_Pos                (0U)

+#define USB_OTG_DIEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPMSK_XFRCM                    USB_OTG_DIEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask                 */

+#define USB_OTG_DIEPMSK_EPDM_Pos                 (1U)

+#define USB_OTG_DIEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPMSK_EPDM                     USB_OTG_DIEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask                  */

+#define USB_OTG_DIEPMSK_TOM_Pos                  (3U)

+#define USB_OTG_DIEPMSK_TOM_Msk                  (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPMSK_TOM                      USB_OTG_DIEPMSK_TOM_Msk       /*!< Timeout condition mask (nonisochronous endpoints) */

+#define USB_OTG_DIEPMSK_ITTXFEMSK_Pos            (4U)

+#define USB_OTG_DIEPMSK_ITTXFEMSK_Msk            (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPMSK_ITTXFEMSK                USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */

+#define USB_OTG_DIEPMSK_INEPNMM_Pos              (5U)

+#define USB_OTG_DIEPMSK_INEPNMM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPMSK_INEPNMM                  USB_OTG_DIEPMSK_INEPNMM_Msk   /*!< IN token received with EP mismatch mask           */

+#define USB_OTG_DIEPMSK_INEPNEM_Pos              (6U)

+#define USB_OTG_DIEPMSK_INEPNEM_Msk              (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPMSK_INEPNEM                  USB_OTG_DIEPMSK_INEPNEM_Msk   /*!< IN endpoint NAK effective mask                    */

+#define USB_OTG_DIEPMSK_TXFURM_Pos               (8U)

+#define USB_OTG_DIEPMSK_TXFURM_Msk               (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPMSK_TXFURM                   USB_OTG_DIEPMSK_TXFURM_Msk    /*!< FIFO underrun mask                                */

+#define USB_OTG_DIEPMSK_BIM_Pos                  (9U)

+#define USB_OTG_DIEPMSK_BIM_Msk                  (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPMSK_BIM                      USB_OTG_DIEPMSK_BIM_Msk       /*!< BNA interrupt mask                                */

+

+/********************  Bit definition forUSB_OTG_HPTXSTS register  ********************/

+#define USB_OTG_HPTXSTS_PTXFSAVL_Pos             (0U)

+#define USB_OTG_HPTXSTS_PTXFSAVL_Msk             (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HPTXSTS_PTXFSAVL                 USB_OTG_HPTXSTS_PTXFSAVL_Msk  /*!< Periodic transmit data FIFO space available     */

+

+#define USB_OTG_HPTXSTS_PTXQSAV_Pos              (16U)

+#define USB_OTG_HPTXSTS_PTXQSAV_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */

+#define USB_OTG_HPTXSTS_PTXQSAV                  USB_OTG_HPTXSTS_PTXQSAV_Msk   /*!< Periodic transmit request queue space available */

+#define USB_OTG_HPTXSTS_PTXQSAV_0                (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_1                (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_2                (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_3                (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_4                (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_5                (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_6                (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */

+#define USB_OTG_HPTXSTS_PTXQSAV_7                (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */

+

+#define USB_OTG_HPTXSTS_PTXQTOP_Pos              (24U)

+#define USB_OTG_HPTXSTS_PTXQTOP_Msk              (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP                  USB_OTG_HPTXSTS_PTXQTOP_Msk   /*!< Top of the periodic transmit request queue */

+#define USB_OTG_HPTXSTS_PTXQTOP_0                (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_1                (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_2                (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_3                (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_4                (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_5                (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_6                (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */

+#define USB_OTG_HPTXSTS_PTXQTOP_7                (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */

+

+/********************  Bit definition forUSB_OTG_HAINT register  ********************/

+#define USB_OTG_HAINT_HAINT_Pos                  (0U)

+#define USB_OTG_HAINT_HAINT_Msk                  (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HAINT_HAINT                      USB_OTG_HAINT_HAINT_Msk       /*!< Channel interrupts */

+

+/********************  Bit definition forUSB_OTG_DOEPMSK register  ********************/

+#define USB_OTG_DOEPMSK_XFRCM_Pos                (0U)

+#define USB_OTG_DOEPMSK_XFRCM_Msk                (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPMSK_XFRCM                    USB_OTG_DOEPMSK_XFRCM_Msk     /*!< Transfer completed interrupt mask */

+#define USB_OTG_DOEPMSK_EPDM_Pos                 (1U)

+#define USB_OTG_DOEPMSK_EPDM_Msk                 (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPMSK_EPDM                     USB_OTG_DOEPMSK_EPDM_Msk      /*!< Endpoint disabled interrupt mask               */

+#define USB_OTG_DOEPMSK_AHBERRM_Pos              (2U)

+#define USB_OTG_DOEPMSK_AHBERRM_Msk              (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */

+#define USB_OTG_DOEPMSK_AHBERRM                  USB_OTG_DOEPMSK_AHBERRM_Msk      /*!< OUT transaction AHB Error interrupt mask               */

+#define USB_OTG_DOEPMSK_STUPM_Pos                (3U)

+#define USB_OTG_DOEPMSK_STUPM_Msk                (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPMSK_STUPM                    USB_OTG_DOEPMSK_STUPM_Msk     /*!< SETUP phase done mask                          */

+#define USB_OTG_DOEPMSK_OTEPDM_Pos               (4U)

+#define USB_OTG_DOEPMSK_OTEPDM_Msk               (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPMSK_OTEPDM                   USB_OTG_DOEPMSK_OTEPDM_Msk    /*!< OUT token received when endpoint disabled mask */

+#define USB_OTG_DOEPMSK_OTEPSPRM_Pos             (5U)

+#define USB_OTG_DOEPMSK_OTEPSPRM_Msk             (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPMSK_OTEPSPRM                 USB_OTG_DOEPMSK_OTEPSPRM_Msk  /*!< Status Phase Received mask                     */

+#define USB_OTG_DOEPMSK_B2BSTUP_Pos              (6U)

+#define USB_OTG_DOEPMSK_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPMSK_B2BSTUP                  USB_OTG_DOEPMSK_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received mask       */

+#define USB_OTG_DOEPMSK_OPEM_Pos                 (8U)

+#define USB_OTG_DOEPMSK_OPEM_Msk                 (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPMSK_OPEM                     USB_OTG_DOEPMSK_OPEM_Msk      /*!< OUT packet error mask                          */

+#define USB_OTG_DOEPMSK_BOIM_Pos                 (9U)

+#define USB_OTG_DOEPMSK_BOIM_Msk                 (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPMSK_BOIM                     USB_OTG_DOEPMSK_BOIM_Msk      /*!< BNA interrupt mask                             */

+#define USB_OTG_DOEPMSK_BERRM_Pos                (12U)

+#define USB_OTG_DOEPMSK_BERRM_Msk                (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPMSK_BERRM                    USB_OTG_DOEPMSK_BERRM_Msk      /*!< Babble error interrupt mask               */

+#define USB_OTG_DOEPMSK_NAKM_Pos                 (13U)

+#define USB_OTG_DOEPMSK_NAKM_Msk                 (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPMSK_NAKM                     USB_OTG_DOEPMSK_NAKM_Msk      /*!< OUT Packet NAK interrupt mask               */

+#define USB_OTG_DOEPMSK_NYETM_Pos                (14U)

+#define USB_OTG_DOEPMSK_NYETM_Msk                (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPMSK_NYETM                    USB_OTG_DOEPMSK_NYETM_Msk      /*!< NYET interrupt mask                */

+

+/********************  Bit definition forUSB_OTG_GINTSTS register  ********************/

+#define USB_OTG_GINTSTS_CMOD_Pos                 (0U)

+#define USB_OTG_GINTSTS_CMOD_Msk                 (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */

+#define USB_OTG_GINTSTS_CMOD                     USB_OTG_GINTSTS_CMOD_Msk      /*!< Current mode of operation                      */

+#define USB_OTG_GINTSTS_MMIS_Pos                 (1U)

+#define USB_OTG_GINTSTS_MMIS_Msk                 (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */

+#define USB_OTG_GINTSTS_MMIS                     USB_OTG_GINTSTS_MMIS_Msk      /*!< Mode mismatch interrupt                        */

+#define USB_OTG_GINTSTS_OTGINT_Pos               (2U)

+#define USB_OTG_GINTSTS_OTGINT_Msk               (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */

+#define USB_OTG_GINTSTS_OTGINT                   USB_OTG_GINTSTS_OTGINT_Msk    /*!< OTG interrupt                                  */

+#define USB_OTG_GINTSTS_SOF_Pos                  (3U)

+#define USB_OTG_GINTSTS_SOF_Msk                  (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */

+#define USB_OTG_GINTSTS_SOF                      USB_OTG_GINTSTS_SOF_Msk       /*!< Start of frame                                 */

+#define USB_OTG_GINTSTS_RXFLVL_Pos               (4U)

+#define USB_OTG_GINTSTS_RXFLVL_Msk               (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */

+#define USB_OTG_GINTSTS_RXFLVL                   USB_OTG_GINTSTS_RXFLVL_Msk    /*!< RxFIFO nonempty                                */

+#define USB_OTG_GINTSTS_NPTXFE_Pos               (5U)

+#define USB_OTG_GINTSTS_NPTXFE_Msk               (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */

+#define USB_OTG_GINTSTS_NPTXFE                   USB_OTG_GINTSTS_NPTXFE_Msk    /*!< Nonperiodic TxFIFO empty                       */

+#define USB_OTG_GINTSTS_GINAKEFF_Pos             (6U)

+#define USB_OTG_GINTSTS_GINAKEFF_Msk             (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */

+#define USB_OTG_GINTSTS_GINAKEFF                 USB_OTG_GINTSTS_GINAKEFF_Msk  /*!< Global IN nonperiodic NAK effective            */

+#define USB_OTG_GINTSTS_BOUTNAKEFF_Pos           (7U)

+#define USB_OTG_GINTSTS_BOUTNAKEFF_Msk           (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */

+#define USB_OTG_GINTSTS_BOUTNAKEFF               USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective                       */

+#define USB_OTG_GINTSTS_ESUSP_Pos                (10U)

+#define USB_OTG_GINTSTS_ESUSP_Msk                (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */

+#define USB_OTG_GINTSTS_ESUSP                    USB_OTG_GINTSTS_ESUSP_Msk     /*!< Early suspend                                  */

+#define USB_OTG_GINTSTS_USBSUSP_Pos              (11U)

+#define USB_OTG_GINTSTS_USBSUSP_Msk              (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */

+#define USB_OTG_GINTSTS_USBSUSP                  USB_OTG_GINTSTS_USBSUSP_Msk   /*!< USB suspend                                    */

+#define USB_OTG_GINTSTS_USBRST_Pos               (12U)

+#define USB_OTG_GINTSTS_USBRST_Msk               (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */

+#define USB_OTG_GINTSTS_USBRST                   USB_OTG_GINTSTS_USBRST_Msk    /*!< USB reset                                      */

+#define USB_OTG_GINTSTS_ENUMDNE_Pos              (13U)

+#define USB_OTG_GINTSTS_ENUMDNE_Msk              (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */

+#define USB_OTG_GINTSTS_ENUMDNE                  USB_OTG_GINTSTS_ENUMDNE_Msk   /*!< Enumeration done                               */

+#define USB_OTG_GINTSTS_ISOODRP_Pos              (14U)

+#define USB_OTG_GINTSTS_ISOODRP_Msk              (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */

+#define USB_OTG_GINTSTS_ISOODRP                  USB_OTG_GINTSTS_ISOODRP_Msk   /*!< Isochronous OUT packet dropped interrupt       */

+#define USB_OTG_GINTSTS_EOPF_Pos                 (15U)

+#define USB_OTG_GINTSTS_EOPF_Msk                 (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */

+#define USB_OTG_GINTSTS_EOPF                     USB_OTG_GINTSTS_EOPF_Msk      /*!< End of periodic frame interrupt                */

+#define USB_OTG_GINTSTS_IEPINT_Pos               (18U)

+#define USB_OTG_GINTSTS_IEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */

+#define USB_OTG_GINTSTS_IEPINT                   USB_OTG_GINTSTS_IEPINT_Msk    /*!< IN endpoint interrupt                          */

+#define USB_OTG_GINTSTS_OEPINT_Pos               (19U)

+#define USB_OTG_GINTSTS_OEPINT_Msk               (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */

+#define USB_OTG_GINTSTS_OEPINT                   USB_OTG_GINTSTS_OEPINT_Msk    /*!< OUT endpoint interrupt                         */

+#define USB_OTG_GINTSTS_IISOIXFR_Pos             (20U)

+#define USB_OTG_GINTSTS_IISOIXFR_Msk             (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */

+#define USB_OTG_GINTSTS_IISOIXFR                 USB_OTG_GINTSTS_IISOIXFR_Msk  /*!< Incomplete isochronous IN transfer             */

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos    (21U)

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk    (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */

+#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT        USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer                   */

+#define USB_OTG_GINTSTS_DATAFSUSP_Pos            (22U)

+#define USB_OTG_GINTSTS_DATAFSUSP_Msk            (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */

+#define USB_OTG_GINTSTS_DATAFSUSP                USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended                           */

+#define USB_OTG_GINTSTS_RSTDET_Pos               (23U)

+#define USB_OTG_GINTSTS_RSTDET_Msk               (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */

+#define USB_OTG_GINTSTS_RSTDET                   USB_OTG_GINTSTS_RSTDET_Msk    /*!< Reset detected interrupt                       */

+#define USB_OTG_GINTSTS_HPRTINT_Pos              (24U)

+#define USB_OTG_GINTSTS_HPRTINT_Msk              (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */

+#define USB_OTG_GINTSTS_HPRTINT                  USB_OTG_GINTSTS_HPRTINT_Msk   /*!< Host port interrupt                            */

+#define USB_OTG_GINTSTS_HCINT_Pos                (25U)

+#define USB_OTG_GINTSTS_HCINT_Msk                (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */

+#define USB_OTG_GINTSTS_HCINT                    USB_OTG_GINTSTS_HCINT_Msk     /*!< Host channels interrupt                        */

+#define USB_OTG_GINTSTS_PTXFE_Pos                (26U)

+#define USB_OTG_GINTSTS_PTXFE_Msk                (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */

+#define USB_OTG_GINTSTS_PTXFE                    USB_OTG_GINTSTS_PTXFE_Msk     /*!< Periodic TxFIFO empty                          */

+#define USB_OTG_GINTSTS_LPMINT_Pos               (27U)

+#define USB_OTG_GINTSTS_LPMINT_Msk               (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */

+#define USB_OTG_GINTSTS_LPMINT                   USB_OTG_GINTSTS_LPMINT_Msk    /*!< LPM interrupt                                  */

+#define USB_OTG_GINTSTS_CIDSCHG_Pos              (28U)

+#define USB_OTG_GINTSTS_CIDSCHG_Msk              (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */

+#define USB_OTG_GINTSTS_CIDSCHG                  USB_OTG_GINTSTS_CIDSCHG_Msk   /*!< Connector ID status change                     */

+#define USB_OTG_GINTSTS_DISCINT_Pos              (29U)

+#define USB_OTG_GINTSTS_DISCINT_Msk              (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */

+#define USB_OTG_GINTSTS_DISCINT                  USB_OTG_GINTSTS_DISCINT_Msk   /*!< Disconnect detected interrupt                  */

+#define USB_OTG_GINTSTS_SRQINT_Pos               (30U)

+#define USB_OTG_GINTSTS_SRQINT_Msk               (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */

+#define USB_OTG_GINTSTS_SRQINT                   USB_OTG_GINTSTS_SRQINT_Msk    /*!< Session request/new session detected interrupt */

+#define USB_OTG_GINTSTS_WKUINT_Pos               (31U)

+#define USB_OTG_GINTSTS_WKUINT_Msk               (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */

+#define USB_OTG_GINTSTS_WKUINT                   USB_OTG_GINTSTS_WKUINT_Msk    /*!< Resume/remote wakeup detected interrupt        */

+

+/********************  Bit definition forUSB_OTG_GINTMSK register  ********************/

+#define USB_OTG_GINTMSK_MMISM_Pos                (1U)

+#define USB_OTG_GINTMSK_MMISM_Msk                (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */

+#define USB_OTG_GINTMSK_MMISM                    USB_OTG_GINTMSK_MMISM_Msk     /*!< Mode mismatch interrupt mask                        */

+#define USB_OTG_GINTMSK_OTGINT_Pos               (2U)

+#define USB_OTG_GINTMSK_OTGINT_Msk               (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */

+#define USB_OTG_GINTMSK_OTGINT                   USB_OTG_GINTMSK_OTGINT_Msk    /*!< OTG interrupt mask                                  */

+#define USB_OTG_GINTMSK_SOFM_Pos                 (3U)

+#define USB_OTG_GINTMSK_SOFM_Msk                 (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */

+#define USB_OTG_GINTMSK_SOFM                     USB_OTG_GINTMSK_SOFM_Msk      /*!< Start of frame mask                                 */

+#define USB_OTG_GINTMSK_RXFLVLM_Pos              (4U)

+#define USB_OTG_GINTMSK_RXFLVLM_Msk              (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */

+#define USB_OTG_GINTMSK_RXFLVLM                  USB_OTG_GINTMSK_RXFLVLM_Msk   /*!< Receive FIFO nonempty mask                          */

+#define USB_OTG_GINTMSK_NPTXFEM_Pos              (5U)

+#define USB_OTG_GINTMSK_NPTXFEM_Msk              (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */

+#define USB_OTG_GINTMSK_NPTXFEM                  USB_OTG_GINTMSK_NPTXFEM_Msk   /*!< Nonperiodic TxFIFO empty mask                       */

+#define USB_OTG_GINTMSK_GINAKEFFM_Pos            (6U)

+#define USB_OTG_GINTMSK_GINAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */

+#define USB_OTG_GINTMSK_GINAKEFFM                USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask            */

+#define USB_OTG_GINTMSK_GONAKEFFM_Pos            (7U)

+#define USB_OTG_GINTMSK_GONAKEFFM_Msk            (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */

+#define USB_OTG_GINTMSK_GONAKEFFM                USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask                       */

+#define USB_OTG_GINTMSK_ESUSPM_Pos               (10U)

+#define USB_OTG_GINTMSK_ESUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */

+#define USB_OTG_GINTMSK_ESUSPM                   USB_OTG_GINTMSK_ESUSPM_Msk    /*!< Early suspend mask                                  */

+#define USB_OTG_GINTMSK_USBSUSPM_Pos             (11U)

+#define USB_OTG_GINTMSK_USBSUSPM_Msk             (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */

+#define USB_OTG_GINTMSK_USBSUSPM                 USB_OTG_GINTMSK_USBSUSPM_Msk  /*!< USB suspend mask                                    */

+#define USB_OTG_GINTMSK_USBRST_Pos               (12U)

+#define USB_OTG_GINTMSK_USBRST_Msk               (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */

+#define USB_OTG_GINTMSK_USBRST                   USB_OTG_GINTMSK_USBRST_Msk    /*!< USB reset mask                                      */

+#define USB_OTG_GINTMSK_ENUMDNEM_Pos             (13U)

+#define USB_OTG_GINTMSK_ENUMDNEM_Msk             (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */

+#define USB_OTG_GINTMSK_ENUMDNEM                 USB_OTG_GINTMSK_ENUMDNEM_Msk  /*!< Enumeration done mask                               */

+#define USB_OTG_GINTMSK_ISOODRPM_Pos             (14U)

+#define USB_OTG_GINTMSK_ISOODRPM_Msk             (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */

+#define USB_OTG_GINTMSK_ISOODRPM                 USB_OTG_GINTMSK_ISOODRPM_Msk  /*!< Isochronous OUT packet dropped interrupt mask       */

+#define USB_OTG_GINTMSK_EOPFM_Pos                (15U)

+#define USB_OTG_GINTMSK_EOPFM_Msk                (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */

+#define USB_OTG_GINTMSK_EOPFM                    USB_OTG_GINTMSK_EOPFM_Msk     /*!< End of periodic frame interrupt mask                */

+#define USB_OTG_GINTMSK_EPMISM_Pos               (17U)

+#define USB_OTG_GINTMSK_EPMISM_Msk               (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */

+#define USB_OTG_GINTMSK_EPMISM                   USB_OTG_GINTMSK_EPMISM_Msk    /*!< Endpoint mismatch interrupt mask                    */

+#define USB_OTG_GINTMSK_IEPINT_Pos               (18U)

+#define USB_OTG_GINTMSK_IEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */

+#define USB_OTG_GINTMSK_IEPINT                   USB_OTG_GINTMSK_IEPINT_Msk    /*!< IN endpoints interrupt mask                         */

+#define USB_OTG_GINTMSK_OEPINT_Pos               (19U)

+#define USB_OTG_GINTMSK_OEPINT_Msk               (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */

+#define USB_OTG_GINTMSK_OEPINT                   USB_OTG_GINTMSK_OEPINT_Msk    /*!< OUT endpoints interrupt mask                        */

+#define USB_OTG_GINTMSK_IISOIXFRM_Pos            (20U)

+#define USB_OTG_GINTMSK_IISOIXFRM_Msk            (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */

+#define USB_OTG_GINTMSK_IISOIXFRM                USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask             */

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos      (21U)

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk      (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */

+#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM          USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask                   */

+#define USB_OTG_GINTMSK_FSUSPM_Pos               (22U)

+#define USB_OTG_GINTMSK_FSUSPM_Msk               (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */

+#define USB_OTG_GINTMSK_FSUSPM                   USB_OTG_GINTMSK_FSUSPM_Msk    /*!< Data fetch suspended mask                           */

+#define USB_OTG_GINTMSK_RSTDEM_Pos               (23U)

+#define USB_OTG_GINTMSK_RSTDEM_Msk               (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */

+#define USB_OTG_GINTMSK_RSTDEM                   USB_OTG_GINTMSK_RSTDEM_Msk    /*!< Reset detected interrupt mask                      */

+#define USB_OTG_GINTMSK_PRTIM_Pos                (24U)

+#define USB_OTG_GINTMSK_PRTIM_Msk                (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */

+#define USB_OTG_GINTMSK_PRTIM                    USB_OTG_GINTMSK_PRTIM_Msk     /*!< Host port interrupt mask                            */

+#define USB_OTG_GINTMSK_HCIM_Pos                 (25U)

+#define USB_OTG_GINTMSK_HCIM_Msk                 (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */

+#define USB_OTG_GINTMSK_HCIM                     USB_OTG_GINTMSK_HCIM_Msk      /*!< Host channels interrupt mask                        */

+#define USB_OTG_GINTMSK_PTXFEM_Pos               (26U)

+#define USB_OTG_GINTMSK_PTXFEM_Msk               (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */

+#define USB_OTG_GINTMSK_PTXFEM                   USB_OTG_GINTMSK_PTXFEM_Msk    /*!< Periodic TxFIFO empty mask                          */

+#define USB_OTG_GINTMSK_LPMINTM_Pos              (27U)

+#define USB_OTG_GINTMSK_LPMINTM_Msk              (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */

+#define USB_OTG_GINTMSK_LPMINTM                  USB_OTG_GINTMSK_LPMINTM_Msk   /*!< LPM interrupt Mask                                  */

+#define USB_OTG_GINTMSK_CIDSCHGM_Pos             (28U)

+#define USB_OTG_GINTMSK_CIDSCHGM_Msk             (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */

+#define USB_OTG_GINTMSK_CIDSCHGM                 USB_OTG_GINTMSK_CIDSCHGM_Msk  /*!< Connector ID status change mask                     */

+#define USB_OTG_GINTMSK_DISCINT_Pos              (29U)

+#define USB_OTG_GINTMSK_DISCINT_Msk              (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */

+#define USB_OTG_GINTMSK_DISCINT                  USB_OTG_GINTMSK_DISCINT_Msk   /*!< Disconnect detected interrupt mask                  */

+#define USB_OTG_GINTMSK_SRQIM_Pos                (30U)

+#define USB_OTG_GINTMSK_SRQIM_Msk                (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */

+#define USB_OTG_GINTMSK_SRQIM                    USB_OTG_GINTMSK_SRQIM_Msk     /*!< Session request/new session detected interrupt mask */

+#define USB_OTG_GINTMSK_WUIM_Pos                 (31U)

+#define USB_OTG_GINTMSK_WUIM_Msk                 (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */

+#define USB_OTG_GINTMSK_WUIM                     USB_OTG_GINTMSK_WUIM_Msk      /*!< Resume/remote wakeup detected interrupt mask        */

+

+/********************  Bit definition forUSB_OTG_DAINT register  ********************/

+#define USB_OTG_DAINT_IEPINT_Pos                 (0U)

+#define USB_OTG_DAINT_IEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DAINT_IEPINT                     USB_OTG_DAINT_IEPINT_Msk      /*!< IN endpoint interrupt bits  */

+#define USB_OTG_DAINT_OEPINT_Pos                 (16U)

+#define USB_OTG_DAINT_OEPINT_Msk                 (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DAINT_OEPINT                     USB_OTG_DAINT_OEPINT_Msk      /*!< OUT endpoint interrupt bits */

+

+/********************  Bit definition forUSB_OTG_HAINTMSK register  ********************/

+#define USB_OTG_HAINTMSK_HAINTM_Pos              (0U)

+#define USB_OTG_HAINTMSK_HAINTM_Msk              (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HAINTMSK_HAINTM                  USB_OTG_HAINTMSK_HAINTM_Msk   /*!< Channel interrupt mask */

+

+/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/

+#define USB_OTG_GRXSTSP_EPNUM_Pos                (0U)

+#define USB_OTG_GRXSTSP_EPNUM_Msk                (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */

+#define USB_OTG_GRXSTSP_EPNUM                    USB_OTG_GRXSTSP_EPNUM_Msk     /*!< IN EP interrupt mask bits  */

+#define USB_OTG_GRXSTSP_BCNT_Pos                 (4U)

+#define USB_OTG_GRXSTSP_BCNT_Msk                 (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */

+#define USB_OTG_GRXSTSP_BCNT                     USB_OTG_GRXSTSP_BCNT_Msk      /*!< OUT EP interrupt mask bits */

+#define USB_OTG_GRXSTSP_DPID_Pos                 (15U)

+#define USB_OTG_GRXSTSP_DPID_Msk                 (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */

+#define USB_OTG_GRXSTSP_DPID                     USB_OTG_GRXSTSP_DPID_Msk      /*!< OUT EP interrupt mask bits */

+#define USB_OTG_GRXSTSP_PKTSTS_Pos               (17U)

+#define USB_OTG_GRXSTSP_PKTSTS_Msk               (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */

+#define USB_OTG_GRXSTSP_PKTSTS                   USB_OTG_GRXSTSP_PKTSTS_Msk    /*!< OUT EP interrupt mask bits */

+

+/********************  Bit definition forUSB_OTG_DAINTMSK register  ********************/

+#define USB_OTG_DAINTMSK_IEPM_Pos                (0U)

+#define USB_OTG_DAINTMSK_IEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DAINTMSK_IEPM                    USB_OTG_DAINTMSK_IEPM_Msk     /*!< IN EP interrupt mask bits */

+#define USB_OTG_DAINTMSK_OEPM_Pos                (16U)

+#define USB_OTG_DAINTMSK_OEPM_Msk                (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DAINTMSK_OEPM                    USB_OTG_DAINTMSK_OEPM_Msk     /*!< OUT EP interrupt mask bits */

+

+/********************  Bit definition for OTG register  ********************/

+

+#define USB_OTG_CHNUM_Pos                        (0U)

+#define USB_OTG_CHNUM_Msk                        (0xFUL << USB_OTG_CHNUM_Pos)  /*!< 0x0000000F */

+#define USB_OTG_CHNUM                            USB_OTG_CHNUM_Msk             /*!< Channel number */

+#define USB_OTG_CHNUM_0                          (0x1UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000001 */

+#define USB_OTG_CHNUM_1                          (0x2UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000002 */

+#define USB_OTG_CHNUM_2                          (0x4UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000004 */

+#define USB_OTG_CHNUM_3                          (0x8UL << USB_OTG_CHNUM_Pos)   /*!< 0x00000008 */

+#define USB_OTG_BCNT_Pos                         (4U)

+#define USB_OTG_BCNT_Msk                         (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */

+#define USB_OTG_BCNT                             USB_OTG_BCNT_Msk              /*!< Byte count */

+

+#define USB_OTG_DPID_Pos                         (15U)

+#define USB_OTG_DPID_Msk                         (0x3UL << USB_OTG_DPID_Pos)   /*!< 0x00018000 */

+#define USB_OTG_DPID                             USB_OTG_DPID_Msk              /*!< Data PID */

+#define USB_OTG_DPID_0                           (0x1UL << USB_OTG_DPID_Pos)    /*!< 0x00008000 */

+#define USB_OTG_DPID_1                           (0x2UL << USB_OTG_DPID_Pos)    /*!< 0x00010000 */

+

+#define USB_OTG_PKTSTS_Pos                       (17U)

+#define USB_OTG_PKTSTS_Msk                       (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */

+#define USB_OTG_PKTSTS                           USB_OTG_PKTSTS_Msk            /*!< Packet status */

+#define USB_OTG_PKTSTS_0                         (0x1UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00020000 */

+#define USB_OTG_PKTSTS_1                         (0x2UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00040000 */

+#define USB_OTG_PKTSTS_2                         (0x4UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00080000 */

+#define USB_OTG_PKTSTS_3                         (0x8UL << USB_OTG_PKTSTS_Pos)  /*!< 0x00100000 */

+

+#define USB_OTG_EPNUM_Pos                        (0U)

+#define USB_OTG_EPNUM_Msk                        (0xFUL << USB_OTG_EPNUM_Pos)  /*!< 0x0000000F */

+#define USB_OTG_EPNUM                            USB_OTG_EPNUM_Msk             /*!< Endpoint number */

+#define USB_OTG_EPNUM_0                          (0x1UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000001 */

+#define USB_OTG_EPNUM_1                          (0x2UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000002 */

+#define USB_OTG_EPNUM_2                          (0x4UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000004 */

+#define USB_OTG_EPNUM_3                          (0x8UL << USB_OTG_EPNUM_Pos)   /*!< 0x00000008 */

+

+#define USB_OTG_FRMNUM_Pos                       (21U)

+#define USB_OTG_FRMNUM_Msk                       (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */

+#define USB_OTG_FRMNUM                           USB_OTG_FRMNUM_Msk            /*!< Frame number */

+#define USB_OTG_FRMNUM_0                         (0x1UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00200000 */

+#define USB_OTG_FRMNUM_1                         (0x2UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00400000 */

+#define USB_OTG_FRMNUM_2                         (0x4UL << USB_OTG_FRMNUM_Pos)  /*!< 0x00800000 */

+#define USB_OTG_FRMNUM_3                         (0x8UL << USB_OTG_FRMNUM_Pos)  /*!< 0x01000000 */

+

+/********************  Bit definition forUSB_OTG_GRXFSIZ register  ********************/

+#define USB_OTG_GRXFSIZ_RXFD_Pos                 (0U)

+#define USB_OTG_GRXFSIZ_RXFD_Msk                 (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_GRXFSIZ_RXFD                     USB_OTG_GRXFSIZ_RXFD_Msk      /*!< RxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DVBUSDIS register  ********************/

+#define USB_OTG_DVBUSDIS_VBUSDT_Pos              (0U)

+#define USB_OTG_DVBUSDIS_VBUSDT_Msk              (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DVBUSDIS_VBUSDT                  USB_OTG_DVBUSDIS_VBUSDT_Msk   /*!< Device VBUS discharge time */

+

+/********************  Bit definition for OTG register  ********************/

+#define USB_OTG_NPTXFSA_Pos                      (0U)

+#define USB_OTG_NPTXFSA_Msk                      (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_NPTXFSA                          USB_OTG_NPTXFSA_Msk           /*!< Nonperiodic transmit RAM start address */

+#define USB_OTG_NPTXFD_Pos                       (16U)

+#define USB_OTG_NPTXFD_Msk                       (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_NPTXFD                           USB_OTG_NPTXFD_Msk            /*!< Nonperiodic TxFIFO depth               */

+#define USB_OTG_TX0FSA_Pos                       (0U)

+#define USB_OTG_TX0FSA_Msk                       (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_TX0FSA                           USB_OTG_TX0FSA_Msk            /*!< Endpoint 0 transmit RAM start address  */

+#define USB_OTG_TX0FD_Pos                        (16U)

+#define USB_OTG_TX0FD_Msk                        (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_TX0FD                            USB_OTG_TX0FD_Msk             /*!< Endpoint 0 TxFIFO depth                */

+

+/********************  Bit definition forUSB_OTG_DVBUSPULSE register  ********************/

+#define USB_OTG_DVBUSPULSE_DVBUSP_Pos            (0U)

+#define USB_OTG_DVBUSPULSE_DVBUSP_Msk            (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */

+#define USB_OTG_DVBUSPULSE_DVBUSP                USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */

+

+/********************  Bit definition forUSB_OTG_GNPTXSTS register  ********************/

+#define USB_OTG_GNPTXSTS_NPTXFSAV_Pos            (0U)

+#define USB_OTG_GNPTXSTS_NPTXFSAV_Msk            (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_GNPTXSTS_NPTXFSAV                USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */

+

+#define USB_OTG_GNPTXSTS_NPTQXSAV_Pos            (16U)

+#define USB_OTG_GNPTXSTS_NPTQXSAV_Msk            (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV                USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_0              (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_1              (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_2              (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_3              (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_4              (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_5              (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_6              (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */

+#define USB_OTG_GNPTXSTS_NPTQXSAV_7              (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */

+

+#define USB_OTG_GNPTXSTS_NPTXQTOP_Pos            (24U)

+#define USB_OTG_GNPTXSTS_NPTXQTOP_Msk            (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP                USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_0              (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_1              (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_2              (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_3              (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_4              (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_5              (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */

+#define USB_OTG_GNPTXSTS_NPTXQTOP_6              (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition forUSB_OTG_DTHRCTL register  ********************/

+#define USB_OTG_DTHRCTL_NONISOTHREN_Pos          (0U)

+#define USB_OTG_DTHRCTL_NONISOTHREN_Msk          (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */

+#define USB_OTG_DTHRCTL_NONISOTHREN              USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */

+#define USB_OTG_DTHRCTL_ISOTHREN_Pos             (1U)

+#define USB_OTG_DTHRCTL_ISOTHREN_Msk             (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */

+#define USB_OTG_DTHRCTL_ISOTHREN                 USB_OTG_DTHRCTL_ISOTHREN_Msk  /*!< ISO IN endpoint threshold enable */

+

+#define USB_OTG_DTHRCTL_TXTHRLEN_Pos             (2U)

+#define USB_OTG_DTHRCTL_TXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */

+#define USB_OTG_DTHRCTL_TXTHRLEN                 USB_OTG_DTHRCTL_TXTHRLEN_Msk  /*!< Transmit threshold length */

+#define USB_OTG_DTHRCTL_TXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */

+#define USB_OTG_DTHRCTL_TXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */

+#define USB_OTG_DTHRCTL_RXTHREN_Pos              (16U)

+#define USB_OTG_DTHRCTL_RXTHREN_Msk              (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */

+#define USB_OTG_DTHRCTL_RXTHREN                  USB_OTG_DTHRCTL_RXTHREN_Msk   /*!< Receive threshold enable */

+

+#define USB_OTG_DTHRCTL_RXTHRLEN_Pos             (17U)

+#define USB_OTG_DTHRCTL_RXTHRLEN_Msk             (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN                 USB_OTG_DTHRCTL_RXTHRLEN_Msk  /*!< Receive threshold length */

+#define USB_OTG_DTHRCTL_RXTHRLEN_0               (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_1               (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_2               (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_3               (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_4               (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_5               (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_6               (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_7               (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */

+#define USB_OTG_DTHRCTL_RXTHRLEN_8               (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */

+#define USB_OTG_DTHRCTL_ARPEN_Pos                (27U)

+#define USB_OTG_DTHRCTL_ARPEN_Msk                (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */

+#define USB_OTG_DTHRCTL_ARPEN                    USB_OTG_DTHRCTL_ARPEN_Msk     /*!< Arbiter parking enable */

+

+/********************  Bit definition forUSB_OTG_DIEPEMPMSK register  ********************/

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos         (0U)

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk         (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DIEPEMPMSK_INEPTXFEM             USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */

+

+/********************  Bit definition forUSB_OTG_DEACHINT register  ********************/

+#define USB_OTG_DEACHINT_IEP1INT_Pos             (1U)

+#define USB_OTG_DEACHINT_IEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */

+#define USB_OTG_DEACHINT_IEP1INT                 USB_OTG_DEACHINT_IEP1INT_Msk  /*!< IN endpoint 1interrupt bit   */

+#define USB_OTG_DEACHINT_OEP1INT_Pos             (17U)

+#define USB_OTG_DEACHINT_OEP1INT_Msk             (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */

+#define USB_OTG_DEACHINT_OEP1INT                 USB_OTG_DEACHINT_OEP1INT_Msk  /*!< OUT endpoint 1 interrupt bit */

+

+/********************  Bit definition forUSB_OTG_GCCFG register  ********************/

+#define USB_OTG_GCCFG_DCDET_Pos                  (0U)

+#define USB_OTG_GCCFG_DCDET_Msk                  (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */

+#define USB_OTG_GCCFG_DCDET                      USB_OTG_GCCFG_DCDET_Msk       /*!< Data contact detection (DCD) status */

+#define USB_OTG_GCCFG_PDET_Pos                   (1U)

+#define USB_OTG_GCCFG_PDET_Msk                   (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */

+#define USB_OTG_GCCFG_PDET                       USB_OTG_GCCFG_PDET_Msk        /*!< Primary detection (PD) status */

+#define USB_OTG_GCCFG_SDET_Pos                   (2U)

+#define USB_OTG_GCCFG_SDET_Msk                   (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */

+#define USB_OTG_GCCFG_SDET                       USB_OTG_GCCFG_SDET_Msk        /*!< Secondary detection (SD) status */

+#define USB_OTG_GCCFG_PS2DET_Pos                 (3U)

+#define USB_OTG_GCCFG_PS2DET_Msk                 (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */

+#define USB_OTG_GCCFG_PS2DET                     USB_OTG_GCCFG_PS2DET_Msk      /*!< DM pull-up detection status */

+#define USB_OTG_GCCFG_PWRDWN_Pos                 (16U)

+#define USB_OTG_GCCFG_PWRDWN_Msk                 (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */

+#define USB_OTG_GCCFG_PWRDWN                     USB_OTG_GCCFG_PWRDWN_Msk      /*!< Power down */

+#define USB_OTG_GCCFG_BCDEN_Pos                  (17U)

+#define USB_OTG_GCCFG_BCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */

+#define USB_OTG_GCCFG_BCDEN                      USB_OTG_GCCFG_BCDEN_Msk       /*!< Battery charging detector (BCD) enable */

+#define USB_OTG_GCCFG_DCDEN_Pos                  (18U)

+#define USB_OTG_GCCFG_DCDEN_Msk                  (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */

+#define USB_OTG_GCCFG_DCDEN                      USB_OTG_GCCFG_DCDEN_Msk       /*!< Data contact detection (DCD) mode enable*/

+#define USB_OTG_GCCFG_PDEN_Pos                   (19U)

+#define USB_OTG_GCCFG_PDEN_Msk                   (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */

+#define USB_OTG_GCCFG_PDEN                       USB_OTG_GCCFG_PDEN_Msk        /*!< Primary detection (PD) mode enable*/

+#define USB_OTG_GCCFG_SDEN_Pos                   (20U)

+#define USB_OTG_GCCFG_SDEN_Msk                   (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */

+#define USB_OTG_GCCFG_SDEN                       USB_OTG_GCCFG_SDEN_Msk        /*!< Secondary detection (SD) mode enable */

+#define USB_OTG_GCCFG_VBDEN_Pos                  (21U)

+#define USB_OTG_GCCFG_VBDEN_Msk                  (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */

+#define USB_OTG_GCCFG_VBDEN                      USB_OTG_GCCFG_VBDEN_Msk       /*!< Secondary detection (SD) mode enable */

+

+/********************  Bit definition forUSB_OTG_GPWRDN) register  ********************/

+#define USB_OTG_GPWRDN_ADPMEN_Pos                (0U)

+#define USB_OTG_GPWRDN_ADPMEN_Msk                (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */

+#define USB_OTG_GPWRDN_ADPMEN                    USB_OTG_GPWRDN_ADPMEN_Msk     /*!< ADP module enable */

+#define USB_OTG_GPWRDN_ADPIF_Pos                 (23U)

+#define USB_OTG_GPWRDN_ADPIF_Msk                 (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */

+#define USB_OTG_GPWRDN_ADPIF                     USB_OTG_GPWRDN_ADPIF_Msk      /*!< ADP Interrupt flag */

+

+/********************  Bit definition forUSB_OTG_DEACHINTMSK register  ********************/

+#define USB_OTG_DEACHINTMSK_IEP1INTM_Pos         (1U)

+#define USB_OTG_DEACHINTMSK_IEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DEACHINTMSK_IEP1INTM             USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit  */

+#define USB_OTG_DEACHINTMSK_OEP1INTM_Pos         (17U)

+#define USB_OTG_DEACHINTMSK_OEP1INTM_Msk         (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */

+#define USB_OTG_DEACHINTMSK_OEP1INTM             USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */

+

+/********************  Bit definition forUSB_OTG_CID register  ********************/

+#define USB_OTG_CID_PRODUCT_ID_Pos               (0U)

+#define USB_OTG_CID_PRODUCT_ID_Msk               (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_CID_PRODUCT_ID                   USB_OTG_CID_PRODUCT_ID_Msk    /*!< Product ID field */

+

+/********************  Bit definition for USB_OTG_GLPMCFG register  ********************/

+#define USB_OTG_GLPMCFG_LPMEN_Pos                (0U)

+#define USB_OTG_GLPMCFG_LPMEN_Msk                (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */

+#define USB_OTG_GLPMCFG_LPMEN                    USB_OTG_GLPMCFG_LPMEN_Msk     /*!< LPM support enable                                     */

+#define USB_OTG_GLPMCFG_LPMACK_Pos               (1U)

+#define USB_OTG_GLPMCFG_LPMACK_Msk               (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */

+#define USB_OTG_GLPMCFG_LPMACK                   USB_OTG_GLPMCFG_LPMACK_Msk    /*!< LPM Token acknowledge enable                           */

+#define USB_OTG_GLPMCFG_BESL_Pos                 (2U)

+#define USB_OTG_GLPMCFG_BESL_Msk                 (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */

+#define USB_OTG_GLPMCFG_BESL                     USB_OTG_GLPMCFG_BESL_Msk      /*!< BESL value received with last ACKed LPM Token          */

+#define USB_OTG_GLPMCFG_REMWAKE_Pos              (6U)

+#define USB_OTG_GLPMCFG_REMWAKE_Msk              (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */

+#define USB_OTG_GLPMCFG_REMWAKE                  USB_OTG_GLPMCFG_REMWAKE_Msk   /*!< bRemoteWake value received with last ACKed LPM Token   */

+#define USB_OTG_GLPMCFG_L1SSEN_Pos               (7U)

+#define USB_OTG_GLPMCFG_L1SSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */

+#define USB_OTG_GLPMCFG_L1SSEN                   USB_OTG_GLPMCFG_L1SSEN_Msk    /*!< L1 shallow sleep enable                                */

+#define USB_OTG_GLPMCFG_BESLTHRS_Pos             (8U)

+#define USB_OTG_GLPMCFG_BESLTHRS_Msk             (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */

+#define USB_OTG_GLPMCFG_BESLTHRS                 USB_OTG_GLPMCFG_BESLTHRS_Msk  /*!< BESL threshold                                         */

+#define USB_OTG_GLPMCFG_L1DSEN_Pos               (12U)

+#define USB_OTG_GLPMCFG_L1DSEN_Msk               (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */

+#define USB_OTG_GLPMCFG_L1DSEN                   USB_OTG_GLPMCFG_L1DSEN_Msk    /*!< L1 deep sleep enable                                   */

+#define USB_OTG_GLPMCFG_LPMRSP_Pos               (13U)

+#define USB_OTG_GLPMCFG_LPMRSP_Msk               (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */

+#define USB_OTG_GLPMCFG_LPMRSP                   USB_OTG_GLPMCFG_LPMRSP_Msk    /*!< LPM response                                           */

+#define USB_OTG_GLPMCFG_SLPSTS_Pos               (15U)

+#define USB_OTG_GLPMCFG_SLPSTS_Msk               (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */

+#define USB_OTG_GLPMCFG_SLPSTS                   USB_OTG_GLPMCFG_SLPSTS_Msk    /*!< Port sleep status                                      */

+#define USB_OTG_GLPMCFG_L1RSMOK_Pos              (16U)

+#define USB_OTG_GLPMCFG_L1RSMOK_Msk              (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */

+#define USB_OTG_GLPMCFG_L1RSMOK                  USB_OTG_GLPMCFG_L1RSMOK_Msk   /*!< Sleep State Resume OK                                  */

+#define USB_OTG_GLPMCFG_LPMCHIDX_Pos             (17U)

+#define USB_OTG_GLPMCFG_LPMCHIDX_Msk             (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */

+#define USB_OTG_GLPMCFG_LPMCHIDX                 USB_OTG_GLPMCFG_LPMCHIDX_Msk  /*!< LPM Channel Index                                      */

+#define USB_OTG_GLPMCFG_LPMRCNT_Pos              (21U)

+#define USB_OTG_GLPMCFG_LPMRCNT_Msk              (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */

+#define USB_OTG_GLPMCFG_LPMRCNT                  USB_OTG_GLPMCFG_LPMRCNT_Msk   /*!< LPM retry count                                        */

+#define USB_OTG_GLPMCFG_SNDLPM_Pos               (24U)

+#define USB_OTG_GLPMCFG_SNDLPM_Msk               (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */

+#define USB_OTG_GLPMCFG_SNDLPM                   USB_OTG_GLPMCFG_SNDLPM_Msk    /*!< Send LPM transaction                                   */

+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos           (25U)

+#define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk           (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */

+#define USB_OTG_GLPMCFG_LPMRCNTSTS               USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status                                 */

+#define USB_OTG_GLPMCFG_ENBESL_Pos               (28U)

+#define USB_OTG_GLPMCFG_ENBESL_Msk               (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */

+#define USB_OTG_GLPMCFG_ENBESL                   USB_OTG_GLPMCFG_ENBESL_Msk    /*!< Enable best effort service latency                     */

+

+/********************  Bit definition forUSB_OTG_DIEPEACHMSK1 register  ********************/

+#define USB_OTG_DIEPEACHMSK1_XFRCM_Pos           (0U)

+#define USB_OTG_DIEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPEACHMSK1_XFRCM               USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask                 */

+#define USB_OTG_DIEPEACHMSK1_EPDM_Pos            (1U)

+#define USB_OTG_DIEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPEACHMSK1_EPDM                USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask                  */

+#define USB_OTG_DIEPEACHMSK1_TOM_Pos             (3U)

+#define USB_OTG_DIEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPEACHMSK1_TOM                 USB_OTG_DIEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask (nonisochronous endpoints) */

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos       (4U)

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK           USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask          */

+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos         (5U)

+#define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPEACHMSK1_INEPNMM             USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask           */

+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos         (6U)

+#define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPEACHMSK1_INEPNEM             USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask                    */

+#define USB_OTG_DIEPEACHMSK1_TXFURM_Pos          (8U)

+#define USB_OTG_DIEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPEACHMSK1_TXFURM              USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */

+#define USB_OTG_DIEPEACHMSK1_BIM_Pos             (9U)

+#define USB_OTG_DIEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPEACHMSK1_BIM                 USB_OTG_DIEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */

+#define USB_OTG_DIEPEACHMSK1_NAKM_Pos            (13U)

+#define USB_OTG_DIEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DIEPEACHMSK1_NAKM                USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */

+

+/********************  Bit definition forUSB_OTG_HPRT register  ********************/

+#define USB_OTG_HPRT_PCSTS_Pos                   (0U)

+#define USB_OTG_HPRT_PCSTS_Msk                   (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */

+#define USB_OTG_HPRT_PCSTS                       USB_OTG_HPRT_PCSTS_Msk        /*!< Port connect status        */

+#define USB_OTG_HPRT_PCDET_Pos                   (1U)

+#define USB_OTG_HPRT_PCDET_Msk                   (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */

+#define USB_OTG_HPRT_PCDET                       USB_OTG_HPRT_PCDET_Msk        /*!< Port connect detected      */

+#define USB_OTG_HPRT_PENA_Pos                    (2U)

+#define USB_OTG_HPRT_PENA_Msk                    (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */

+#define USB_OTG_HPRT_PENA                        USB_OTG_HPRT_PENA_Msk         /*!< Port enable                */

+#define USB_OTG_HPRT_PENCHNG_Pos                 (3U)

+#define USB_OTG_HPRT_PENCHNG_Msk                 (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */

+#define USB_OTG_HPRT_PENCHNG                     USB_OTG_HPRT_PENCHNG_Msk      /*!< Port enable/disable change */

+#define USB_OTG_HPRT_POCA_Pos                    (4U)

+#define USB_OTG_HPRT_POCA_Msk                    (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */

+#define USB_OTG_HPRT_POCA                        USB_OTG_HPRT_POCA_Msk         /*!< Port overcurrent active    */

+#define USB_OTG_HPRT_POCCHNG_Pos                 (5U)

+#define USB_OTG_HPRT_POCCHNG_Msk                 (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */

+#define USB_OTG_HPRT_POCCHNG                     USB_OTG_HPRT_POCCHNG_Msk      /*!< Port overcurrent change    */

+#define USB_OTG_HPRT_PRES_Pos                    (6U)

+#define USB_OTG_HPRT_PRES_Msk                    (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */

+#define USB_OTG_HPRT_PRES                        USB_OTG_HPRT_PRES_Msk         /*!< Port resume   */

+#define USB_OTG_HPRT_PSUSP_Pos                   (7U)

+#define USB_OTG_HPRT_PSUSP_Msk                   (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */

+#define USB_OTG_HPRT_PSUSP                       USB_OTG_HPRT_PSUSP_Msk        /*!< Port suspend  */

+#define USB_OTG_HPRT_PRST_Pos                    (8U)

+#define USB_OTG_HPRT_PRST_Msk                    (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */

+#define USB_OTG_HPRT_PRST                        USB_OTG_HPRT_PRST_Msk         /*!< Port reset    */

+

+#define USB_OTG_HPRT_PLSTS_Pos                   (10U)

+#define USB_OTG_HPRT_PLSTS_Msk                   (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */

+#define USB_OTG_HPRT_PLSTS                       USB_OTG_HPRT_PLSTS_Msk        /*!< Port line status */

+#define USB_OTG_HPRT_PLSTS_0                     (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */

+#define USB_OTG_HPRT_PLSTS_1                     (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */

+#define USB_OTG_HPRT_PPWR_Pos                    (12U)

+#define USB_OTG_HPRT_PPWR_Msk                    (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */

+#define USB_OTG_HPRT_PPWR                        USB_OTG_HPRT_PPWR_Msk         /*!< Port power */

+

+#define USB_OTG_HPRT_PTCTL_Pos                   (13U)

+#define USB_OTG_HPRT_PTCTL_Msk                   (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */

+#define USB_OTG_HPRT_PTCTL                       USB_OTG_HPRT_PTCTL_Msk        /*!< Port test control */

+#define USB_OTG_HPRT_PTCTL_0                     (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */

+#define USB_OTG_HPRT_PTCTL_1                     (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */

+#define USB_OTG_HPRT_PTCTL_2                     (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */

+#define USB_OTG_HPRT_PTCTL_3                     (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */

+

+#define USB_OTG_HPRT_PSPD_Pos                    (17U)

+#define USB_OTG_HPRT_PSPD_Msk                    (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */

+#define USB_OTG_HPRT_PSPD                        USB_OTG_HPRT_PSPD_Msk         /*!< Port speed */

+#define USB_OTG_HPRT_PSPD_0                      (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */

+#define USB_OTG_HPRT_PSPD_1                      (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */

+

+/********************  Bit definition forUSB_OTG_DOEPEACHMSK1 register  ********************/

+#define USB_OTG_DOEPEACHMSK1_XFRCM_Pos           (0U)

+#define USB_OTG_DOEPEACHMSK1_XFRCM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPEACHMSK1_XFRCM               USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_EPDM_Pos            (1U)

+#define USB_OTG_DOEPEACHMSK1_EPDM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPEACHMSK1_EPDM                USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_TOM_Pos             (3U)

+#define USB_OTG_DOEPEACHMSK1_TOM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPEACHMSK1_TOM                 USB_OTG_DOEPEACHMSK1_TOM_Msk  /*!< Timeout condition mask */

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos       (4U)

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk       (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK           USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */

+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos         (5U)

+#define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPEACHMSK1_INEPNMM             USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */

+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos         (6U)

+#define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk         (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPEACHMSK1_INEPNEM             USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */

+#define USB_OTG_DOEPEACHMSK1_TXFURM_Pos          (8U)

+#define USB_OTG_DOEPEACHMSK1_TXFURM_Msk          (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPEACHMSK1_TXFURM              USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */

+#define USB_OTG_DOEPEACHMSK1_BIM_Pos             (9U)

+#define USB_OTG_DOEPEACHMSK1_BIM_Msk             (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPEACHMSK1_BIM                 USB_OTG_DOEPEACHMSK1_BIM_Msk  /*!< BNA interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_BERRM_Pos           (12U)

+#define USB_OTG_DOEPEACHMSK1_BERRM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPEACHMSK1_BERRM               USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_NAKM_Pos            (13U)

+#define USB_OTG_DOEPEACHMSK1_NAKM_Msk            (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPEACHMSK1_NAKM                USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */

+#define USB_OTG_DOEPEACHMSK1_NYETM_Pos           (14U)

+#define USB_OTG_DOEPEACHMSK1_NYETM_Msk           (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPEACHMSK1_NYETM               USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */

+

+/********************  Bit definition forUSB_OTG_HPTXFSIZ register  ********************/

+#define USB_OTG_HPTXFSIZ_PTXSA_Pos               (0U)

+#define USB_OTG_HPTXFSIZ_PTXSA_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_HPTXFSIZ_PTXSA                   USB_OTG_HPTXFSIZ_PTXSA_Msk    /*!< Host periodic TxFIFO start address */

+#define USB_OTG_HPTXFSIZ_PTXFD_Pos               (16U)

+#define USB_OTG_HPTXFSIZ_PTXFD_Msk               (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_HPTXFSIZ_PTXFD                   USB_OTG_HPTXFSIZ_PTXFD_Msk    /*!< Host periodic TxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DIEPCTL register  ********************/

+#define USB_OTG_DIEPCTL_MPSIZ_Pos                (0U)

+#define USB_OTG_DIEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_DIEPCTL_MPSIZ                    USB_OTG_DIEPCTL_MPSIZ_Msk     /*!< Maximum packet size */

+#define USB_OTG_DIEPCTL_USBAEP_Pos               (15U)

+#define USB_OTG_DIEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */

+#define USB_OTG_DIEPCTL_USBAEP                   USB_OTG_DIEPCTL_USBAEP_Msk    /*!< USB active endpoint */

+#define USB_OTG_DIEPCTL_EONUM_DPID_Pos           (16U)

+#define USB_OTG_DIEPCTL_EONUM_DPID_Msk           (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */

+#define USB_OTG_DIEPCTL_EONUM_DPID               USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */

+#define USB_OTG_DIEPCTL_NAKSTS_Pos               (17U)

+#define USB_OTG_DIEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */

+#define USB_OTG_DIEPCTL_NAKSTS                   USB_OTG_DIEPCTL_NAKSTS_Msk    /*!< NAK status */

+

+#define USB_OTG_DIEPCTL_EPTYP_Pos                (18U)

+#define USB_OTG_DIEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_DIEPCTL_EPTYP                    USB_OTG_DIEPCTL_EPTYP_Msk     /*!< Endpoint type */

+#define USB_OTG_DIEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_DIEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */

+#define USB_OTG_DIEPCTL_STALL_Pos                (21U)

+#define USB_OTG_DIEPCTL_STALL_Msk                (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */

+#define USB_OTG_DIEPCTL_STALL                    USB_OTG_DIEPCTL_STALL_Msk     /*!< STALL handshake */

+

+#define USB_OTG_DIEPCTL_TXFNUM_Pos               (22U)

+#define USB_OTG_DIEPCTL_TXFNUM_Msk               (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */

+#define USB_OTG_DIEPCTL_TXFNUM                   USB_OTG_DIEPCTL_TXFNUM_Msk    /*!< TxFIFO number */

+#define USB_OTG_DIEPCTL_TXFNUM_0                 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */

+#define USB_OTG_DIEPCTL_TXFNUM_1                 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */

+#define USB_OTG_DIEPCTL_TXFNUM_2                 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */

+#define USB_OTG_DIEPCTL_TXFNUM_3                 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */

+#define USB_OTG_DIEPCTL_CNAK_Pos                 (26U)

+#define USB_OTG_DIEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */

+#define USB_OTG_DIEPCTL_CNAK                     USB_OTG_DIEPCTL_CNAK_Msk      /*!< Clear NAK */

+#define USB_OTG_DIEPCTL_SNAK_Pos                 (27U)

+#define USB_OTG_DIEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */

+#define USB_OTG_DIEPCTL_SNAK                     USB_OTG_DIEPCTL_SNAK_Msk      /*!< Set NAK */

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos       (28U)

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */

+#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM           USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */

+#define USB_OTG_DIEPCTL_SODDFRM_Pos              (29U)

+#define USB_OTG_DIEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_DIEPCTL_SODDFRM                  USB_OTG_DIEPCTL_SODDFRM_Msk   /*!< Set odd frame */

+#define USB_OTG_DIEPCTL_EPDIS_Pos                (30U)

+#define USB_OTG_DIEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_DIEPCTL_EPDIS                    USB_OTG_DIEPCTL_EPDIS_Msk     /*!< Endpoint disable */

+#define USB_OTG_DIEPCTL_EPENA_Pos                (31U)

+#define USB_OTG_DIEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_DIEPCTL_EPENA                    USB_OTG_DIEPCTL_EPENA_Msk     /*!< Endpoint enable */

+

+/********************  Bit definition forUSB_OTG_HCCHAR register  ********************/

+#define USB_OTG_HCCHAR_MPSIZ_Pos                 (0U)

+#define USB_OTG_HCCHAR_MPSIZ_Msk                 (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_HCCHAR_MPSIZ                     USB_OTG_HCCHAR_MPSIZ_Msk      /*!< Maximum packet size */

+

+#define USB_OTG_HCCHAR_EPNUM_Pos                 (11U)

+#define USB_OTG_HCCHAR_EPNUM_Msk                 (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */

+#define USB_OTG_HCCHAR_EPNUM                     USB_OTG_HCCHAR_EPNUM_Msk      /*!< Endpoint number */

+#define USB_OTG_HCCHAR_EPNUM_0                   (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */

+#define USB_OTG_HCCHAR_EPNUM_1                   (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */

+#define USB_OTG_HCCHAR_EPNUM_2                   (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */

+#define USB_OTG_HCCHAR_EPNUM_3                   (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */

+#define USB_OTG_HCCHAR_EPDIR_Pos                 (15U)

+#define USB_OTG_HCCHAR_EPDIR_Msk                 (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */

+#define USB_OTG_HCCHAR_EPDIR                     USB_OTG_HCCHAR_EPDIR_Msk      /*!< Endpoint direction */

+#define USB_OTG_HCCHAR_LSDEV_Pos                 (17U)

+#define USB_OTG_HCCHAR_LSDEV_Msk                 (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */

+#define USB_OTG_HCCHAR_LSDEV                     USB_OTG_HCCHAR_LSDEV_Msk      /*!< Low-speed device */

+

+#define USB_OTG_HCCHAR_EPTYP_Pos                 (18U)

+#define USB_OTG_HCCHAR_EPTYP_Msk                 (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_HCCHAR_EPTYP                     USB_OTG_HCCHAR_EPTYP_Msk      /*!< Endpoint type */

+#define USB_OTG_HCCHAR_EPTYP_0                   (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_HCCHAR_EPTYP_1                   (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */

+

+#define USB_OTG_HCCHAR_MC_Pos                    (20U)

+#define USB_OTG_HCCHAR_MC_Msk                    (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */

+#define USB_OTG_HCCHAR_MC                        USB_OTG_HCCHAR_MC_Msk         /*!< Multi Count (MC) / Error Count (EC) */

+#define USB_OTG_HCCHAR_MC_0                      (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */

+#define USB_OTG_HCCHAR_MC_1                      (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */

+

+#define USB_OTG_HCCHAR_DAD_Pos                   (22U)

+#define USB_OTG_HCCHAR_DAD_Msk                   (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */

+#define USB_OTG_HCCHAR_DAD                       USB_OTG_HCCHAR_DAD_Msk        /*!< Device address */

+#define USB_OTG_HCCHAR_DAD_0                     (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */

+#define USB_OTG_HCCHAR_DAD_1                     (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */

+#define USB_OTG_HCCHAR_DAD_2                     (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */

+#define USB_OTG_HCCHAR_DAD_3                     (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */

+#define USB_OTG_HCCHAR_DAD_4                     (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */

+#define USB_OTG_HCCHAR_DAD_5                     (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */

+#define USB_OTG_HCCHAR_DAD_6                     (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */

+#define USB_OTG_HCCHAR_ODDFRM_Pos                (29U)

+#define USB_OTG_HCCHAR_ODDFRM_Msk                (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_HCCHAR_ODDFRM                    USB_OTG_HCCHAR_ODDFRM_Msk     /*!< Odd frame */

+#define USB_OTG_HCCHAR_CHDIS_Pos                 (30U)

+#define USB_OTG_HCCHAR_CHDIS_Msk                 (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_HCCHAR_CHDIS                     USB_OTG_HCCHAR_CHDIS_Msk      /*!< Channel disable */

+#define USB_OTG_HCCHAR_CHENA_Pos                 (31U)

+#define USB_OTG_HCCHAR_CHENA_Msk                 (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCCHAR_CHENA                     USB_OTG_HCCHAR_CHENA_Msk      /*!< Channel enable */

+

+/********************  Bit definition forUSB_OTG_HCSPLT register  ********************/

+

+#define USB_OTG_HCSPLT_PRTADDR_Pos               (0U)

+#define USB_OTG_HCSPLT_PRTADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */

+#define USB_OTG_HCSPLT_PRTADDR                   USB_OTG_HCSPLT_PRTADDR_Msk    /*!< Port address */

+#define USB_OTG_HCSPLT_PRTADDR_0                 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCSPLT_PRTADDR_1                 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCSPLT_PRTADDR_2                 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCSPLT_PRTADDR_3                 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCSPLT_PRTADDR_4                 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCSPLT_PRTADDR_5                 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCSPLT_PRTADDR_6                 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */

+

+#define USB_OTG_HCSPLT_HUBADDR_Pos               (7U)

+#define USB_OTG_HCSPLT_HUBADDR_Msk               (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */

+#define USB_OTG_HCSPLT_HUBADDR                   USB_OTG_HCSPLT_HUBADDR_Msk    /*!< Hub address */

+#define USB_OTG_HCSPLT_HUBADDR_0                 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCSPLT_HUBADDR_1                 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCSPLT_HUBADDR_2                 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCSPLT_HUBADDR_3                 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCSPLT_HUBADDR_4                 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */

+#define USB_OTG_HCSPLT_HUBADDR_5                 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */

+#define USB_OTG_HCSPLT_HUBADDR_6                 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */

+

+#define USB_OTG_HCSPLT_XACTPOS_Pos               (14U)

+#define USB_OTG_HCSPLT_XACTPOS_Msk               (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */

+#define USB_OTG_HCSPLT_XACTPOS                   USB_OTG_HCSPLT_XACTPOS_Msk    /*!< XACTPOS */

+#define USB_OTG_HCSPLT_XACTPOS_0                 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */

+#define USB_OTG_HCSPLT_XACTPOS_1                 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */

+#define USB_OTG_HCSPLT_COMPLSPLT_Pos             (16U)

+#define USB_OTG_HCSPLT_COMPLSPLT_Msk             (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */

+#define USB_OTG_HCSPLT_COMPLSPLT                 USB_OTG_HCSPLT_COMPLSPLT_Msk  /*!< Do complete split */

+#define USB_OTG_HCSPLT_SPLITEN_Pos               (31U)

+#define USB_OTG_HCSPLT_SPLITEN_Msk               (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCSPLT_SPLITEN                   USB_OTG_HCSPLT_SPLITEN_Msk    /*!< Split enable */

+

+/********************  Bit definition forUSB_OTG_HCINT register  ********************/

+#define USB_OTG_HCINT_XFRC_Pos                   (0U)

+#define USB_OTG_HCINT_XFRC_Msk                   (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCINT_XFRC                       USB_OTG_HCINT_XFRC_Msk        /*!< Transfer completed */

+#define USB_OTG_HCINT_CHH_Pos                    (1U)

+#define USB_OTG_HCINT_CHH_Msk                    (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCINT_CHH                        USB_OTG_HCINT_CHH_Msk         /*!< Channel halted */

+#define USB_OTG_HCINT_AHBERR_Pos                 (2U)

+#define USB_OTG_HCINT_AHBERR_Msk                 (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCINT_AHBERR                     USB_OTG_HCINT_AHBERR_Msk      /*!< AHB error */

+#define USB_OTG_HCINT_STALL_Pos                  (3U)

+#define USB_OTG_HCINT_STALL_Msk                  (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCINT_STALL                      USB_OTG_HCINT_STALL_Msk       /*!< STALL response received interrupt */

+#define USB_OTG_HCINT_NAK_Pos                    (4U)

+#define USB_OTG_HCINT_NAK_Msk                    (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCINT_NAK                        USB_OTG_HCINT_NAK_Msk         /*!< NAK response received interrupt */

+#define USB_OTG_HCINT_ACK_Pos                    (5U)

+#define USB_OTG_HCINT_ACK_Msk                    (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCINT_ACK                        USB_OTG_HCINT_ACK_Msk         /*!< ACK response received/transmitted interrupt */

+#define USB_OTG_HCINT_NYET_Pos                   (6U)

+#define USB_OTG_HCINT_NYET_Msk                   (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */

+#define USB_OTG_HCINT_NYET                       USB_OTG_HCINT_NYET_Msk        /*!< Response received interrupt */

+#define USB_OTG_HCINT_TXERR_Pos                  (7U)

+#define USB_OTG_HCINT_TXERR_Msk                  (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCINT_TXERR                      USB_OTG_HCINT_TXERR_Msk       /*!< Transaction error */

+#define USB_OTG_HCINT_BBERR_Pos                  (8U)

+#define USB_OTG_HCINT_BBERR_Msk                  (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCINT_BBERR                      USB_OTG_HCINT_BBERR_Msk       /*!< Babble error */

+#define USB_OTG_HCINT_FRMOR_Pos                  (9U)

+#define USB_OTG_HCINT_FRMOR_Msk                  (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCINT_FRMOR                      USB_OTG_HCINT_FRMOR_Msk       /*!< Frame overrun */

+#define USB_OTG_HCINT_DTERR_Pos                  (10U)

+#define USB_OTG_HCINT_DTERR_Msk                  (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCINT_DTERR                      USB_OTG_HCINT_DTERR_Msk       /*!< Data toggle error */

+

+/********************  Bit definition forUSB_OTG_DIEPINT register  ********************/

+#define USB_OTG_DIEPINT_XFRC_Pos                 (0U)

+#define USB_OTG_DIEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_DIEPINT_XFRC                     USB_OTG_DIEPINT_XFRC_Msk      /*!< Transfer completed interrupt */

+#define USB_OTG_DIEPINT_EPDISD_Pos               (1U)

+#define USB_OTG_DIEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DIEPINT_EPDISD                   USB_OTG_DIEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */

+#define USB_OTG_DIEPINT_AHBERR_Pos               (2U)

+#define USB_OTG_DIEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_DIEPINT_AHBERR                   USB_OTG_DIEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an IN transaction */

+#define USB_OTG_DIEPINT_TOC_Pos                  (3U)

+#define USB_OTG_DIEPINT_TOC_Msk                  (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */

+#define USB_OTG_DIEPINT_TOC                      USB_OTG_DIEPINT_TOC_Msk       /*!< Timeout condition */

+#define USB_OTG_DIEPINT_ITTXFE_Pos               (4U)

+#define USB_OTG_DIEPINT_ITTXFE_Msk               (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */

+#define USB_OTG_DIEPINT_ITTXFE                   USB_OTG_DIEPINT_ITTXFE_Msk    /*!< IN token received when TxFIFO is empty */

+#define USB_OTG_DIEPINT_INEPNM_Pos               (5U)

+#define USB_OTG_DIEPINT_INEPNM_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */

+#define USB_OTG_DIEPINT_INEPNM                   USB_OTG_DIEPINT_INEPNM_Msk   /*!< IN token received with EP mismatch */

+#define USB_OTG_DIEPINT_INEPNE_Pos               (6U)

+#define USB_OTG_DIEPINT_INEPNE_Msk               (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */

+#define USB_OTG_DIEPINT_INEPNE                   USB_OTG_DIEPINT_INEPNE_Msk    /*!< IN endpoint NAK effective */

+#define USB_OTG_DIEPINT_TXFE_Pos                 (7U)

+#define USB_OTG_DIEPINT_TXFE_Msk                 (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */

+#define USB_OTG_DIEPINT_TXFE                     USB_OTG_DIEPINT_TXFE_Msk      /*!< Transmit FIFO empty */

+#define USB_OTG_DIEPINT_TXFIFOUDRN_Pos           (8U)

+#define USB_OTG_DIEPINT_TXFIFOUDRN_Msk           (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */

+#define USB_OTG_DIEPINT_TXFIFOUDRN               USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */

+#define USB_OTG_DIEPINT_BNA_Pos                  (9U)

+#define USB_OTG_DIEPINT_BNA_Msk                  (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */

+#define USB_OTG_DIEPINT_BNA                      USB_OTG_DIEPINT_BNA_Msk       /*!< Buffer not available interrupt */

+#define USB_OTG_DIEPINT_PKTDRPSTS_Pos            (11U)

+#define USB_OTG_DIEPINT_PKTDRPSTS_Msk            (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */

+#define USB_OTG_DIEPINT_PKTDRPSTS                USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */

+#define USB_OTG_DIEPINT_BERR_Pos                 (12U)

+#define USB_OTG_DIEPINT_BERR_Msk                 (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */

+#define USB_OTG_DIEPINT_BERR                     USB_OTG_DIEPINT_BERR_Msk      /*!< Babble error interrupt */

+#define USB_OTG_DIEPINT_NAK_Pos                  (13U)

+#define USB_OTG_DIEPINT_NAK_Msk                  (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */

+#define USB_OTG_DIEPINT_NAK                      USB_OTG_DIEPINT_NAK_Msk       /*!< NAK interrupt */

+

+/********************  Bit definition forUSB_OTG_HCINTMSK register  ********************/

+#define USB_OTG_HCINTMSK_XFRCM_Pos               (0U)

+#define USB_OTG_HCINTMSK_XFRCM_Msk               (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */

+#define USB_OTG_HCINTMSK_XFRCM                   USB_OTG_HCINTMSK_XFRCM_Msk    /*!< Transfer completed mask */

+#define USB_OTG_HCINTMSK_CHHM_Pos                (1U)

+#define USB_OTG_HCINTMSK_CHHM_Msk                (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */

+#define USB_OTG_HCINTMSK_CHHM                    USB_OTG_HCINTMSK_CHHM_Msk     /*!< Channel halted mask */

+#define USB_OTG_HCINTMSK_AHBERR_Pos              (2U)

+#define USB_OTG_HCINTMSK_AHBERR_Msk              (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_HCINTMSK_AHBERR                  USB_OTG_HCINTMSK_AHBERR_Msk   /*!< AHB error */

+#define USB_OTG_HCINTMSK_STALLM_Pos              (3U)

+#define USB_OTG_HCINTMSK_STALLM_Msk              (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */

+#define USB_OTG_HCINTMSK_STALLM                  USB_OTG_HCINTMSK_STALLM_Msk   /*!< STALL response received interrupt mask */

+#define USB_OTG_HCINTMSK_NAKM_Pos                (4U)

+#define USB_OTG_HCINTMSK_NAKM_Msk                (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */

+#define USB_OTG_HCINTMSK_NAKM                    USB_OTG_HCINTMSK_NAKM_Msk     /*!< NAK response received interrupt mask */

+#define USB_OTG_HCINTMSK_ACKM_Pos                (5U)

+#define USB_OTG_HCINTMSK_ACKM_Msk                (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */

+#define USB_OTG_HCINTMSK_ACKM                    USB_OTG_HCINTMSK_ACKM_Msk     /*!< ACK response received/transmitted interrupt mask */

+#define USB_OTG_HCINTMSK_NYET_Pos                (6U)

+#define USB_OTG_HCINTMSK_NYET_Msk                (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */

+#define USB_OTG_HCINTMSK_NYET                    USB_OTG_HCINTMSK_NYET_Msk     /*!< response received interrupt mask */

+#define USB_OTG_HCINTMSK_TXERRM_Pos              (7U)

+#define USB_OTG_HCINTMSK_TXERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */

+#define USB_OTG_HCINTMSK_TXERRM                  USB_OTG_HCINTMSK_TXERRM_Msk   /*!< Transaction error mask */

+#define USB_OTG_HCINTMSK_BBERRM_Pos              (8U)

+#define USB_OTG_HCINTMSK_BBERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */

+#define USB_OTG_HCINTMSK_BBERRM                  USB_OTG_HCINTMSK_BBERRM_Msk   /*!< Babble error mask */

+#define USB_OTG_HCINTMSK_FRMORM_Pos              (9U)

+#define USB_OTG_HCINTMSK_FRMORM_Msk              (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */

+#define USB_OTG_HCINTMSK_FRMORM                  USB_OTG_HCINTMSK_FRMORM_Msk   /*!< Frame overrun mask */

+#define USB_OTG_HCINTMSK_DTERRM_Pos              (10U)

+#define USB_OTG_HCINTMSK_DTERRM_Msk              (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */

+#define USB_OTG_HCINTMSK_DTERRM                  USB_OTG_HCINTMSK_DTERRM_Msk   /*!< Data toggle error mask */

+

+/********************  Bit definition for USB_OTG_DIEPTSIZ register  ********************/

+

+#define USB_OTG_DIEPTSIZ_XFRSIZ_Pos              (0U)

+#define USB_OTG_DIEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_DIEPTSIZ_XFRSIZ                  USB_OTG_DIEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */

+#define USB_OTG_DIEPTSIZ_PKTCNT_Pos              (19U)

+#define USB_OTG_DIEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_DIEPTSIZ_PKTCNT                  USB_OTG_DIEPTSIZ_PKTCNT_Msk   /*!< Packet count */

+#define USB_OTG_DIEPTSIZ_MULCNT_Pos              (29U)

+#define USB_OTG_DIEPTSIZ_MULCNT_Msk              (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */

+#define USB_OTG_DIEPTSIZ_MULCNT                  USB_OTG_DIEPTSIZ_MULCNT_Msk   /*!< Packet count */

+/********************  Bit definition forUSB_OTG_HCTSIZ register  ********************/

+#define USB_OTG_HCTSIZ_XFRSIZ_Pos                (0U)

+#define USB_OTG_HCTSIZ_XFRSIZ_Msk                (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_HCTSIZ_XFRSIZ                    USB_OTG_HCTSIZ_XFRSIZ_Msk     /*!< Transfer size */

+#define USB_OTG_HCTSIZ_PKTCNT_Pos                (19U)

+#define USB_OTG_HCTSIZ_PKTCNT_Msk                (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_HCTSIZ_PKTCNT                    USB_OTG_HCTSIZ_PKTCNT_Msk     /*!< Packet count */

+#define USB_OTG_HCTSIZ_DOPING_Pos                (31U)

+#define USB_OTG_HCTSIZ_DOPING_Msk                (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */

+#define USB_OTG_HCTSIZ_DOPING                    USB_OTG_HCTSIZ_DOPING_Msk     /*!< Do PING */

+#define USB_OTG_HCTSIZ_DPID_Pos                  (29U)

+#define USB_OTG_HCTSIZ_DPID_Msk                  (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */

+#define USB_OTG_HCTSIZ_DPID                      USB_OTG_HCTSIZ_DPID_Msk       /*!< Data PID */

+#define USB_OTG_HCTSIZ_DPID_0                    (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */

+#define USB_OTG_HCTSIZ_DPID_1                    (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition forUSB_OTG_DIEPDMA register  ********************/

+#define USB_OTG_DIEPDMA_DMAADDR_Pos              (0U)

+#define USB_OTG_DIEPDMA_DMAADDR_Msk              (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_DIEPDMA_DMAADDR                  USB_OTG_DIEPDMA_DMAADDR_Msk   /*!< DMA address */

+

+/********************  Bit definition forUSB_OTG_HCDMA register  ********************/

+#define USB_OTG_HCDMA_DMAADDR_Pos                (0U)

+#define USB_OTG_HCDMA_DMAADDR_Msk                (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */

+#define USB_OTG_HCDMA_DMAADDR                    USB_OTG_HCDMA_DMAADDR_Msk     /*!< DMA address */

+

+/********************  Bit definition forUSB_OTG_DTXFSTS register  ********************/

+#define USB_OTG_DTXFSTS_INEPTFSAV_Pos            (0U)

+#define USB_OTG_DTXFSTS_INEPTFSAV_Msk            (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DTXFSTS_INEPTFSAV                USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */

+

+/********************  Bit definition forUSB_OTG_DIEPTXF register  ********************/

+#define USB_OTG_DIEPTXF_INEPTXSA_Pos             (0U)

+#define USB_OTG_DIEPTXF_INEPTXSA_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */

+#define USB_OTG_DIEPTXF_INEPTXSA                 USB_OTG_DIEPTXF_INEPTXSA_Msk  /*!< IN endpoint FIFOx transmit RAM start address */

+#define USB_OTG_DIEPTXF_INEPTXFD_Pos             (16U)

+#define USB_OTG_DIEPTXF_INEPTXFD_Msk             (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */

+#define USB_OTG_DIEPTXF_INEPTXFD                 USB_OTG_DIEPTXF_INEPTXFD_Msk  /*!< IN endpoint TxFIFO depth */

+

+/********************  Bit definition forUSB_OTG_DOEPCTL register  ********************/

+

+#define USB_OTG_DOEPCTL_MPSIZ_Pos                (0U)

+#define USB_OTG_DOEPCTL_MPSIZ_Msk                (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */

+#define USB_OTG_DOEPCTL_MPSIZ                    USB_OTG_DOEPCTL_MPSIZ_Msk     /*!< Maximum packet size */          /*!<Bit 1 */

+#define USB_OTG_DOEPCTL_USBAEP_Pos               (15U)

+#define USB_OTG_DOEPCTL_USBAEP_Msk               (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */

+#define USB_OTG_DOEPCTL_USBAEP                   USB_OTG_DOEPCTL_USBAEP_Msk    /*!< USB active endpoint */

+#define USB_OTG_DOEPCTL_NAKSTS_Pos               (17U)

+#define USB_OTG_DOEPCTL_NAKSTS_Msk               (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */

+#define USB_OTG_DOEPCTL_NAKSTS                   USB_OTG_DOEPCTL_NAKSTS_Msk    /*!< NAK status */

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos       (28U)

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk       (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */

+#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM           USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */

+#define USB_OTG_DOEPCTL_SODDFRM_Pos              (29U)

+#define USB_OTG_DOEPCTL_SODDFRM_Msk              (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */

+#define USB_OTG_DOEPCTL_SODDFRM                  USB_OTG_DOEPCTL_SODDFRM_Msk   /*!< Set odd frame */

+#define USB_OTG_DOEPCTL_EPTYP_Pos                (18U)

+#define USB_OTG_DOEPCTL_EPTYP_Msk                (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */

+#define USB_OTG_DOEPCTL_EPTYP                    USB_OTG_DOEPCTL_EPTYP_Msk     /*!< Endpoint type */

+#define USB_OTG_DOEPCTL_EPTYP_0                  (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */

+#define USB_OTG_DOEPCTL_EPTYP_1                  (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */

+#define USB_OTG_DOEPCTL_SNPM_Pos                 (20U)

+#define USB_OTG_DOEPCTL_SNPM_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */

+#define USB_OTG_DOEPCTL_SNPM                     USB_OTG_DOEPCTL_SNPM_Msk      /*!< Snoop mode */

+#define USB_OTG_DOEPCTL_STALL_Pos                (21U)

+#define USB_OTG_DOEPCTL_STALL_Msk                (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */

+#define USB_OTG_DOEPCTL_STALL                    USB_OTG_DOEPCTL_STALL_Msk     /*!< STALL handshake */

+#define USB_OTG_DOEPCTL_CNAK_Pos                 (26U)

+#define USB_OTG_DOEPCTL_CNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */

+#define USB_OTG_DOEPCTL_CNAK                     USB_OTG_DOEPCTL_CNAK_Msk      /*!< Clear NAK */

+#define USB_OTG_DOEPCTL_SNAK_Pos                 (27U)

+#define USB_OTG_DOEPCTL_SNAK_Msk                 (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */

+#define USB_OTG_DOEPCTL_SNAK                     USB_OTG_DOEPCTL_SNAK_Msk      /*!< Set NAK */

+#define USB_OTG_DOEPCTL_EPDIS_Pos                (30U)

+#define USB_OTG_DOEPCTL_EPDIS_Msk                (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */

+#define USB_OTG_DOEPCTL_EPDIS                    USB_OTG_DOEPCTL_EPDIS_Msk     /*!< Endpoint disable */

+#define USB_OTG_DOEPCTL_EPENA_Pos                (31U)

+#define USB_OTG_DOEPCTL_EPENA_Msk                (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */

+#define USB_OTG_DOEPCTL_EPENA                    USB_OTG_DOEPCTL_EPENA_Msk     /*!< Endpoint enable */

+

+/********************  Bit definition forUSB_OTG_DOEPINT register  ********************/

+#define USB_OTG_DOEPINT_XFRC_Pos                 (0U)

+#define USB_OTG_DOEPINT_XFRC_Msk                 (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */

+#define USB_OTG_DOEPINT_XFRC                     USB_OTG_DOEPINT_XFRC_Msk      /*!< Transfer completed interrupt */

+#define USB_OTG_DOEPINT_EPDISD_Pos               (1U)

+#define USB_OTG_DOEPINT_EPDISD_Msk               (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */

+#define USB_OTG_DOEPINT_EPDISD                   USB_OTG_DOEPINT_EPDISD_Msk    /*!< Endpoint disabled interrupt */

+#define USB_OTG_DOEPINT_AHBERR_Pos               (2U)

+#define USB_OTG_DOEPINT_AHBERR_Msk               (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */

+#define USB_OTG_DOEPINT_AHBERR                   USB_OTG_DOEPINT_AHBERR_Msk   /*!< AHB Error (AHBErr) during an OUT transaction */

+#define USB_OTG_DOEPINT_STUP_Pos                 (3U)

+#define USB_OTG_DOEPINT_STUP_Msk                 (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */

+#define USB_OTG_DOEPINT_STUP                     USB_OTG_DOEPINT_STUP_Msk      /*!< SETUP phase done */

+#define USB_OTG_DOEPINT_OTEPDIS_Pos              (4U)

+#define USB_OTG_DOEPINT_OTEPDIS_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */

+#define USB_OTG_DOEPINT_OTEPDIS                  USB_OTG_DOEPINT_OTEPDIS_Msk   /*!< OUT token received when endpoint disabled */

+#define USB_OTG_DOEPINT_OTEPSPR_Pos              (5U)

+#define USB_OTG_DOEPINT_OTEPSPR_Msk              (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */

+#define USB_OTG_DOEPINT_OTEPSPR                  USB_OTG_DOEPINT_OTEPSPR_Msk   /*!< OUT Status Phase Received interrupt */

+#define USB_OTG_DOEPINT_B2BSTUP_Pos              (6U)

+#define USB_OTG_DOEPINT_B2BSTUP_Msk              (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */

+#define USB_OTG_DOEPINT_B2BSTUP                  USB_OTG_DOEPINT_B2BSTUP_Msk   /*!< Back-to-back SETUP packets received */

+#define USB_OTG_DOEPINT_OUTPKTERR_Pos            (8U)

+#define USB_OTG_DOEPINT_OUTPKTERR_Msk            (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */

+#define USB_OTG_DOEPINT_OUTPKTERR                USB_OTG_DOEPINT_OUTPKTERR_Msk   /*!< OUT packet error */

+#define USB_OTG_DOEPINT_BNA_Pos                  (9U)

+#define USB_OTG_DOEPINT_BNA_Msk                  (0x1UL << USB_OTG_DOEPINT_BNA_Pos) /*!< 0x00000200 */

+#define USB_OTG_DOEPINT_BNA                      USB_OTG_DOEPINT_BNA_Msk   /*!< Buffer not available interrupt */

+#define USB_OTG_DOEPINT_BERR_Pos                 (12U)

+#define USB_OTG_DOEPINT_BERR_Msk                 (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */

+#define USB_OTG_DOEPINT_BERR                      USB_OTG_DOEPINT_BERR_Msk   /*!< Babble error interrupt */

+#define USB_OTG_DOEPINT_NAK_Pos                  (13U)

+#define USB_OTG_DOEPINT_NAK_Msk                  (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */

+#define USB_OTG_DOEPINT_NAK                      USB_OTG_DOEPINT_NAK_Msk   /*!< NAK Packet is transmitted by the device */

+#define USB_OTG_DOEPINT_NYET_Pos                 (14U)

+#define USB_OTG_DOEPINT_NYET_Msk                 (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */

+#define USB_OTG_DOEPINT_NYET                     USB_OTG_DOEPINT_NYET_Msk      /*!< NYET interrupt */

+#define USB_OTG_DOEPINT_STPKTRX_Pos              (15U)

+#define USB_OTG_DOEPINT_STPKTRX_Msk              (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */

+#define USB_OTG_DOEPINT_STPKTRX                  USB_OTG_DOEPINT_STPKTRX_Msk   /*!< Setup Packet Received */

+

+/********************  Bit definition forUSB_OTG_DOEPTSIZ register  ********************/

+

+#define USB_OTG_DOEPTSIZ_XFRSIZ_Pos              (0U)

+#define USB_OTG_DOEPTSIZ_XFRSIZ_Msk              (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */

+#define USB_OTG_DOEPTSIZ_XFRSIZ                  USB_OTG_DOEPTSIZ_XFRSIZ_Msk   /*!< Transfer size */

+#define USB_OTG_DOEPTSIZ_PKTCNT_Pos              (19U)

+#define USB_OTG_DOEPTSIZ_PKTCNT_Msk              (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */

+#define USB_OTG_DOEPTSIZ_PKTCNT                  USB_OTG_DOEPTSIZ_PKTCNT_Msk   /*!< Packet count */

+

+#define USB_OTG_DOEPTSIZ_STUPCNT_Pos             (29U)

+#define USB_OTG_DOEPTSIZ_STUPCNT_Msk             (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */

+#define USB_OTG_DOEPTSIZ_STUPCNT                 USB_OTG_DOEPTSIZ_STUPCNT_Msk  /*!< SETUP packet count */

+#define USB_OTG_DOEPTSIZ_STUPCNT_0               (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */

+#define USB_OTG_DOEPTSIZ_STUPCNT_1               (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */

+

+/********************  Bit definition for PCGCCTL register  ********************/

+#define USB_OTG_PCGCCTL_STOPCLK_Pos              (0U)

+#define USB_OTG_PCGCCTL_STOPCLK_Msk              (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */

+#define USB_OTG_PCGCCTL_STOPCLK                  USB_OTG_PCGCCTL_STOPCLK_Msk   /*!< SETUP packet count */

+#define USB_OTG_PCGCCTL_GATECLK_Pos              (1U)

+#define USB_OTG_PCGCCTL_GATECLK_Msk              (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */

+#define USB_OTG_PCGCCTL_GATECLK                  USB_OTG_PCGCCTL_GATECLK_Msk   /*!<Bit 0 */

+#define USB_OTG_PCGCCTL_PHYSUSP_Pos              (4U)

+#define USB_OTG_PCGCCTL_PHYSUSP_Msk              (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */

+#define USB_OTG_PCGCCTL_PHYSUSP                  USB_OTG_PCGCCTL_PHYSUSP_Msk   /*!<Bit 1 */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/** @addtogroup Exported_macros

+  * @{

+  */

+

+/******************************* ADC Instances ********************************/

+#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \

+                                       ((INSTANCE) == ADC2))

+

+#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)

+

+#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)

+

+/******************************** COMP Instances ******************************/

+#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \

+                                       ((INSTANCE) == COMP2))

+

+#define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)

+/******************** COMP Instances with window mode capability **************/

+#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)

+

+/******************************** DTS Instances ******************************/

+#define IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS)

+

+/******************************* CRC Instances ********************************/

+#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

+

+/******************************* DAC Instances ********************************/

+#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1)|| \

+                                       ((INSTANCE) == DAC2))

+/******************************* DCMI Instances *******************************/

+#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)

+

+/******************************* DELAYBLOCK Instances *******************************/

+#define IS_DLYB_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DLYB_SDMMC1) || \

+                                         ((INSTANCE) == DLYB_SDMMC2) || \

+                                         ((INSTANCE) == DLYB_OCTOSPI1) || \

+                                         ((INSTANCE) == DLYB_OCTOSPI2) )

+/****************************** DFSDM Instances *******************************/

+#define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \

+                                         ((INSTANCE) == DFSDM1_Filter1) || \

+                                         ((INSTANCE) == DFSDM1_Filter2) || \

+                                         ((INSTANCE) == DFSDM1_Filter3) || \

+                                         ((INSTANCE) == DFSDM1_Filter4) || \

+                                         ((INSTANCE) == DFSDM1_Filter5) || \

+                                         ((INSTANCE) == DFSDM1_Filter6) || \

+                                         ((INSTANCE) == DFSDM1_Filter7) || \

+                                         ((INSTANCE) == DFSDM2_Filter0))

+#define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \

+                                                 ((INSTANCE) == DFSDM1_Channel1) || \

+                                                 ((INSTANCE) == DFSDM1_Channel2) || \

+                                                 ((INSTANCE) == DFSDM1_Channel3) || \

+                                                 ((INSTANCE) == DFSDM1_Channel4) || \

+                                                 ((INSTANCE) == DFSDM1_Channel5) || \

+                                                 ((INSTANCE) == DFSDM1_Channel6) || \

+                                                 ((INSTANCE) == DFSDM1_Channel7) || \

+                                                 ((INSTANCE) == DFSDM2_Channel0) || \

+                                                 ((INSTANCE) == DFSDM2_Channel1))

+/****************************** RAMECC Instances ******************************/

+#define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC_Monitor1)   || \

+                                                  ((INSTANCE) == RAMECC_Monitor2)   || \

+                                                  ((INSTANCE) == RAMECC_Monitor3))

+

+/******************************** DMA Instances *******************************/

+#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \

+                                       ((INSTANCE) == DMA1_Stream1)   || \

+                                       ((INSTANCE) == DMA1_Stream2)   || \

+                                       ((INSTANCE) == DMA1_Stream3)   || \

+                                       ((INSTANCE) == DMA1_Stream4)   || \

+                                       ((INSTANCE) == DMA1_Stream5)   || \

+                                       ((INSTANCE) == DMA1_Stream6)   || \

+                                       ((INSTANCE) == DMA1_Stream7)   || \

+                                       ((INSTANCE) == DMA2_Stream0)   || \

+                                       ((INSTANCE) == DMA2_Stream1)   || \

+                                       ((INSTANCE) == DMA2_Stream2)   || \

+                                       ((INSTANCE) == DMA2_Stream3)   || \

+                                       ((INSTANCE) == DMA2_Stream4)   || \

+                                       ((INSTANCE) == DMA2_Stream5)   || \

+                                       ((INSTANCE) == DMA2_Stream6)   || \

+                                       ((INSTANCE) == DMA2_Stream7)   || \

+                                       ((INSTANCE) == BDMA1_Channel0) || \

+                                       ((INSTANCE) == BDMA1_Channel1) || \

+                                       ((INSTANCE) == BDMA1_Channel2) || \

+                                       ((INSTANCE) == BDMA1_Channel3) || \

+                                       ((INSTANCE) == BDMA1_Channel4) || \

+                                       ((INSTANCE) == BDMA1_Channel5) || \

+                                       ((INSTANCE) == BDMA1_Channel6) || \

+                                       ((INSTANCE) == BDMA1_Channel7) || \

+                                       ((INSTANCE) == BDMA2_Channel0) || \

+                                       ((INSTANCE) == BDMA2_Channel1) || \

+                                       ((INSTANCE) == BDMA2_Channel2) || \

+                                       ((INSTANCE) == BDMA2_Channel3) || \

+                                       ((INSTANCE) == BDMA2_Channel4) || \

+                                       ((INSTANCE) == BDMA2_Channel5) || \

+                                       ((INSTANCE) == BDMA2_Channel6) || \

+                                       ((INSTANCE) == BDMA2_Channel7))

+

+/****************************** BDMA CHANNEL Instances ***************************/

+#define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA1_Channel0) || \

+                                            ((INSTANCE) == BDMA1_Channel1) || \

+                                            ((INSTANCE) == BDMA1_Channel2) || \

+                                            ((INSTANCE) == BDMA1_Channel3) || \

+                                            ((INSTANCE) == BDMA1_Channel4) || \

+                                            ((INSTANCE) == BDMA1_Channel5) || \

+                                            ((INSTANCE) == BDMA1_Channel6) || \

+                                            ((INSTANCE) == BDMA1_Channel7) || \

+                                            ((INSTANCE) == BDMA2_Channel0) || \

+                                            ((INSTANCE) == BDMA2_Channel1) || \

+                                            ((INSTANCE) == BDMA2_Channel2) || \

+                                            ((INSTANCE) == BDMA2_Channel3) || \

+                                            ((INSTANCE) == BDMA2_Channel4) || \

+                                            ((INSTANCE) == BDMA2_Channel5) || \

+                                            ((INSTANCE) == BDMA2_Channel6) || \

+                                            ((INSTANCE) == BDMA2_Channel7))

+

+/****************************** DMA DMAMUX ALL Instances ***************************/

+#define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)    || \

+                                               ((INSTANCE) == DMA1_Stream1)    || \

+                                               ((INSTANCE) == DMA1_Stream2)    || \

+                                               ((INSTANCE) == DMA1_Stream3)    || \

+                                               ((INSTANCE) == DMA1_Stream4)    || \

+                                               ((INSTANCE) == DMA1_Stream5)    || \

+                                               ((INSTANCE) == DMA1_Stream6)    || \

+                                               ((INSTANCE) == DMA1_Stream7)    || \

+                                               ((INSTANCE) == DMA2_Stream0)    || \

+                                               ((INSTANCE) == DMA2_Stream1)    || \

+                                               ((INSTANCE) == DMA2_Stream2)    || \

+                                               ((INSTANCE) == DMA2_Stream3)    || \

+                                               ((INSTANCE) == DMA2_Stream4)    || \

+                                               ((INSTANCE) == DMA2_Stream5)    || \

+                                               ((INSTANCE) == DMA2_Stream6)    || \

+                                               ((INSTANCE) == DMA2_Stream7)    || \

+                                               ((INSTANCE) == BDMA2_Channel0)  || \

+                                               ((INSTANCE) == BDMA2_Channel1)  || \

+                                               ((INSTANCE) == BDMA2_Channel2)  || \

+                                               ((INSTANCE) == BDMA2_Channel3)  || \

+                                               ((INSTANCE) == BDMA2_Channel4)  || \

+                                               ((INSTANCE) == BDMA2_Channel5)  || \

+                                               ((INSTANCE) == BDMA2_Channel6)  || \

+                                               ((INSTANCE) == BDMA2_Channel7))

+

+/****************************** BDMA DMAMUX Instances ***************************/

+#define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == BDMA2_Channel0) || \

+                                                    ((INSTANCE) == BDMA2_Channel1) || \

+                                                    ((INSTANCE) == BDMA2_Channel2) || \

+                                                    ((INSTANCE) == BDMA2_Channel3) || \

+                                                    ((INSTANCE) == BDMA2_Channel4) || \

+                                                    ((INSTANCE) == BDMA2_Channel5) || \

+                                                    ((INSTANCE) == BDMA2_Channel6) || \

+                                                    ((INSTANCE) == BDMA2_Channel7))

+

+/****************************** DMA STREAM Instances ***************************/

+#define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0)   || \

+                                          ((INSTANCE) == DMA1_Stream1)   || \

+                                          ((INSTANCE) == DMA1_Stream2)   || \

+                                          ((INSTANCE) == DMA1_Stream3)   || \

+                                          ((INSTANCE) == DMA1_Stream4)   || \

+                                          ((INSTANCE) == DMA1_Stream5)   || \

+                                          ((INSTANCE) == DMA1_Stream6)   || \

+                                          ((INSTANCE) == DMA1_Stream7)   || \

+                                          ((INSTANCE) == DMA2_Stream0)   || \

+                                          ((INSTANCE) == DMA2_Stream1)   || \

+                                          ((INSTANCE) == DMA2_Stream2)   || \

+                                          ((INSTANCE) == DMA2_Stream3)   || \

+                                          ((INSTANCE) == DMA2_Stream4)   || \

+                                          ((INSTANCE) == DMA2_Stream5)   || \

+                                          ((INSTANCE) == DMA2_Stream6)   || \

+                                          ((INSTANCE) == DMA2_Stream7))

+

+/****************************** DMA DMAMUX Instances ***************************/

+#define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE)  (((INSTANCE) == DMA1_Stream0)   || \

+                                                  ((INSTANCE) == DMA1_Stream1)   || \

+                                                  ((INSTANCE) == DMA1_Stream2)   || \

+                                                  ((INSTANCE) == DMA1_Stream3)   || \

+                                                  ((INSTANCE) == DMA1_Stream4)   || \

+                                                  ((INSTANCE) == DMA1_Stream5)   || \

+                                                  ((INSTANCE) == DMA1_Stream6)   || \

+                                                  ((INSTANCE) == DMA1_Stream7)   || \

+                                                  ((INSTANCE) == DMA2_Stream0)   || \

+                                                  ((INSTANCE) == DMA2_Stream1)   || \

+                                                  ((INSTANCE) == DMA2_Stream2)   || \

+                                                  ((INSTANCE) == DMA2_Stream3)   || \

+                                                  ((INSTANCE) == DMA2_Stream4)   || \

+                                                  ((INSTANCE) == DMA2_Stream5)   || \

+                                                  ((INSTANCE) == DMA2_Stream6)   || \

+                                                  ((INSTANCE) == DMA2_Stream7))

+

+/******************************** DMA Request Generator Instances **************/

+#define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator1) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator2) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator3) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator4) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator5) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator6) || \

+                                                   ((INSTANCE) == DMAMUX1_RequestGenerator7) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator0) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator1) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator2) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator3) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator4) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator5) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator6) || \

+                                                   ((INSTANCE) == DMAMUX2_RequestGenerator7))

+

+/******************************* DMA2D Instances *******************************/

+#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)

+

+/******************************* OTFDEC Instances ******************************/

+#define IS_OTFDEC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == OTFDEC1) || \

+                                              ((__INSTANCE__) == OTFDEC2))

+

+/****************************** PSSI Instance *********************************/

+#define IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI)

+

+/******************************** MDMA Request Generator Instances **************/

+#define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0)  || \

+                                               ((INSTANCE) == MDMA_Channel1)  || \

+                                               ((INSTANCE) == MDMA_Channel2)  || \

+                                               ((INSTANCE) == MDMA_Channel3)  || \

+                                               ((INSTANCE) == MDMA_Channel4)  || \

+                                               ((INSTANCE) == MDMA_Channel5)  || \

+                                               ((INSTANCE) == MDMA_Channel6)  || \

+                                               ((INSTANCE) == MDMA_Channel7)  || \

+                                               ((INSTANCE) == MDMA_Channel8)  || \

+                                               ((INSTANCE) == MDMA_Channel9)  || \

+                                               ((INSTANCE) == MDMA_Channel10) || \

+                                               ((INSTANCE) == MDMA_Channel11) || \

+                                               ((INSTANCE) == MDMA_Channel12) || \

+                                               ((INSTANCE) == MDMA_Channel13) || \

+                                               ((INSTANCE) == MDMA_Channel14) || \

+                                               ((INSTANCE) == MDMA_Channel15))

+

+

+/******************************* FDCAN Instances ******************************/

+#define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \

+                                             ((__INSTANCE__) == FDCAN2))

+

+#define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)

+

+/******************************* GFXMMU Instances *******************************/

+#define IS_GFXMMU_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GFXMMU)

+

+/******************************* GPIO Instances *******************************/

+#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \

+                                        ((INSTANCE) == GPIOB) || \

+                                        ((INSTANCE) == GPIOC) || \

+                                        ((INSTANCE) == GPIOD) || \

+                                        ((INSTANCE) == GPIOE) || \

+                                        ((INSTANCE) == GPIOF) || \

+                                        ((INSTANCE) == GPIOG) || \

+                                        ((INSTANCE) == GPIOH) || \

+                                        ((INSTANCE) == GPIOI) || \

+                                        ((INSTANCE) == GPIOJ) || \

+                                        ((INSTANCE) == GPIOK))

+

+/******************************* GPIO AF Instances ****************************/

+#define IS_GPIO_AF_INSTANCE(INSTANCE)   IS_GPIO_ALL_INSTANCE(INSTANCE)

+

+/**************************** GPIO Lock Instances *****************************/

+/* On H7, all GPIO Bank support the Lock mechanism */

+#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)

+

+/******************************** HSEM Instances *******************************/

+#define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)

+#define HSEM_CPU1_COREID         (0x00000001U) /* Semaphore Core CM7 ID */

+#define HSEM_CR_COREID_CPU1      (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)

+#define HSEM_CR_COREID_CURRENT   (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)

+

+#define HSEM_SEMID_MIN     (0U)       /* HSEM ID Min*/

+#define HSEM_SEMID_MAX     (15U)      /* HSEM ID Max */

+

+#define HSEM_PROCESSID_MIN (0U)       /* HSEM Process ID Min */

+#define HSEM_PROCESSID_MAX (255U)     /* HSEM Process ID Max */

+

+#define HSEM_CLEAR_KEY_MIN (0U)       /* HSEM clear Key Min value */

+#define HSEM_CLEAR_KEY_MAX (0xFFFFU)  /* HSEM clear Key Max value */

+

+/******************************** I2C Instances *******************************/

+#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

+                                       ((INSTANCE) == I2C2) || \

+                                       ((INSTANCE) == I2C3) || \

+                                       ((INSTANCE) == I2C4))

+/************** I2C Instances : wakeup capability from stop modes *************/

+#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)

+

+/****************************** SMBUS Instances *******************************/

+#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \

+                                         ((INSTANCE) == I2C2) || \

+                                         ((INSTANCE) == I2C3) || \

+                                         ((INSTANCE) == I2C4))

+/******************************** I2S Instances *******************************/

+#define IS_I2S_ALL_INSTANCE(INSTANCE)   (((INSTANCE) == SPI1) || \

+                                         ((INSTANCE) == SPI2) || \

+                                         ((INSTANCE) == SPI3) || \

+                                         ((INSTANCE) == SPI6))

+

+/****************************** LTDC Instances ********************************/

+#define IS_LTDC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == LTDC)

+

+/******************************* RNG Instances ********************************/

+#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)

+

+/****************************** RTC Instances *********************************/

+#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)

+

+/****************************** SDMMC Instances *********************************/

+#define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \

+                                           ((_INSTANCE_) == SDMMC2))

+

+/******************************** SMBUS Instances *****************************/

+#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)

+

+/******************************** SPI Instances *******************************/

+#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \

+                                       ((INSTANCE) == SPI2) || \

+                                       ((INSTANCE) == SPI3) || \

+                                       ((INSTANCE) == SPI4) || \

+                                       ((INSTANCE) == SPI5) || \

+                                       ((INSTANCE) == SPI6))

+

+#define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \

+                                           ((INSTANCE) == SPI2) || \

+                                           ((INSTANCE) == SPI3))

+

+/******************************** SWPMI Instances *****************************/

+#define IS_SWPMI_INSTANCE(INSTANCE)  ((INSTANCE) == SWPMI1)

+

+/****************** LPTIM Instances : All supported instances *****************/

+#define IS_LPTIM_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \

+                                         ((INSTANCE) == LPTIM2) || \

+                                         ((INSTANCE) == LPTIM3))

+

+/****************** LPTIM Instances : supporting encoder interface **************/

+#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)     (((INSTANCE) == LPTIM1) || \

+                                                           ((INSTANCE) == LPTIM2))

+

+/****************** TIM Instances : All supported instances *******************/

+#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM6)   || \

+                                         ((INSTANCE) == TIM7)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM13)  || \

+                                         ((INSTANCE) == TIM14)  || \

+                                         ((INSTANCE) == TIM15)  || \

+                                         ((INSTANCE) == TIM16)  || \

+                                         ((INSTANCE) == TIM17))

+

+/************* TIM Instances : at least 1 capture/compare channel *************/

+#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM13)  || \

+                                         ((INSTANCE) == TIM14)  || \

+                                         ((INSTANCE) == TIM15)  || \

+                                         ((INSTANCE) == TIM16)  || \

+                                         ((INSTANCE) == TIM17))

+

+/************ TIM Instances : at least 2 capture/compare channels *************/

+#define IS_TIM_CC2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM12)  || \

+                                         ((INSTANCE) == TIM15))

+

+/************ TIM Instances : at least 3 capture/compare channels *************/

+#define IS_TIM_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8))

+

+/************ TIM Instances : at least 4 capture/compare channels *************/

+#define IS_TIM_CC4_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8))

+

+/************ TIM Instances : at least 5 capture/compare channels *************/

+#define IS_TIM_CC5_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM8))

+/************ TIM Instances : at least 6 capture/compare channels *************/

+#define IS_TIM_CC6_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM8))

+

+/******************** TIM Instances : Advanced-control timers *****************/

+#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \

+                                                ((__INSTANCE__) == TIM8))

+

+/******************** TIM Instances : Advanced-control timers *****************/

+

+/******************* TIM Instances : Timer input XOR function *****************/

+#define IS_TIM_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                         ((INSTANCE) == TIM2)   || \

+                                         ((INSTANCE) == TIM3)   || \

+                                         ((INSTANCE) == TIM4)   || \

+                                         ((INSTANCE) == TIM5)   || \

+                                         ((INSTANCE) == TIM8)   || \

+                                         ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : DMA requests generation (UDE) *************/

+#define IS_TIM_DMA_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM6)   || \

+                                           ((INSTANCE) == TIM7)   || \

+                                           ((INSTANCE) == TIM8)   || \

+                                           ((INSTANCE) == TIM15)  || \

+                                           ((INSTANCE) == TIM16)  || \

+                                           ((INSTANCE) == TIM17))

+

+/************ TIM Instances : DMA requests generation (CCxDE) *****************/

+#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15)  || \

+                                            ((INSTANCE) == TIM16)  || \

+                                            ((INSTANCE) == TIM17))

+

+/************ TIM Instances : DMA requests generation (COMDE) *****************/

+#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15))

+

+/******************** TIM Instances : DMA burst feature ***********************/

+#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM8))

+

+/*************** TIM Instances : external trigger reamp input available *******/

+#define IS_TIM_ETR_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : remapping capability **********************/

+#define IS_TIM_REMAP_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)  || \

+                                          ((INSTANCE) == TIM2)  || \

+                                          ((INSTANCE) == TIM3)  || \

+                                          ((INSTANCE) == TIM5)  || \

+                                          ((INSTANCE) == TIM8)  || \

+                                          ((INSTANCE) == TIM16) || \

+                                          ((INSTANCE) == TIM17))

+

+/*************** TIM Instances : external trigger reamp input available *******/

+#define IS_TIM_ETRSEL_INSTANCE(INSTANCE)     (((INSTANCE) == TIM1)   || \

+                                              ((INSTANCE) == TIM2)   || \

+                                              ((INSTANCE) == TIM3)   || \

+                                              ((INSTANCE) == TIM5)   || \

+                                              ((INSTANCE) == TIM8))

+

+/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/

+#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                            ((INSTANCE) == TIM2)   || \

+                                            ((INSTANCE) == TIM3)   || \

+                                            ((INSTANCE) == TIM4)   || \

+                                            ((INSTANCE) == TIM5)   || \

+                                            ((INSTANCE) == TIM6)   || \

+                                            ((INSTANCE) == TIM7)   || \

+                                            ((INSTANCE) == TIM8)   || \

+                                            ((INSTANCE) == TIM15))

+

+/****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/

+#define IS_TIM_SLAVE_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM2)   || \

+                                           ((INSTANCE) == TIM3)   || \

+                                           ((INSTANCE) == TIM4)   || \

+                                           ((INSTANCE) == TIM5)   || \

+                                           ((INSTANCE) == TIM8)   || \

+                                           ((INSTANCE) == TIM12))

+

+/****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/

+#define IS_TIM_TRGO2_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                           ((INSTANCE) == TIM8))

+

+/****** TIM Instances : TISEL available (TIMx_TISEL available )*********/

+#define IS_TIM_TISEL_INSTANCE(INSTANCE)  (((INSTANCE) == TIM1)   || \

+                                          ((INSTANCE) == TIM2)   || \

+                                          ((INSTANCE) == TIM3)   || \

+                                          ((INSTANCE) == TIM4)   || \

+                                          ((INSTANCE) == TIM5)   || \

+                                          ((INSTANCE) == TIM8)   || \

+                                          ((INSTANCE) == TIM15)  || \

+                                          ((INSTANCE) == TIM16)  || \

+                                          ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting commutation event *************/

+#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)    || \

+                                                     ((INSTANCE) == TIM8)    || \

+                                                     ((INSTANCE) == TIM15)   || \

+                                                     ((INSTANCE) == TIM16)   || \

+                                                     ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting encoder interface **************/

+#define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__)  (((__INSTANCE__) == TIM1)  || \

+                                                      ((__INSTANCE__) == TIM2)      || \

+                                                      ((__INSTANCE__) == TIM3)      || \

+                                                      ((__INSTANCE__) == TIM4)      || \

+                                                      ((__INSTANCE__) == TIM5)      || \

+                                                      ((__INSTANCE__) == TIM8))

+

+/****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/

+#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE)   (((INSTANCE) == TIM1)   || \

+                                                       ((INSTANCE) == TIM8))

+/******************* TIM Instances : output(s) available **********************/

+#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \

+    ((((INSTANCE) == TIM1) &&                  \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4) ||          \

+      ((CHANNEL) == TIM_CHANNEL_5) ||          \

+      ((CHANNEL) == TIM_CHANNEL_6)))           \

+     ||                                        \

+     (((INSTANCE) == TIM2) &&                  \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM3) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1)||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM4) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM5) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4)))           \

+  ||                                           \

+      (((INSTANCE) == TIM8) &&                 \

+      (((CHANNEL) == TIM_CHANNEL_1) ||         \

+      ((CHANNEL) == TIM_CHANNEL_2) ||          \

+      ((CHANNEL) == TIM_CHANNEL_3) ||          \

+      ((CHANNEL) == TIM_CHANNEL_4) ||          \

+      ((CHANNEL) == TIM_CHANNEL_5) ||          \

+      ((CHANNEL) == TIM_CHANNEL_6)))           \

+  ||                                           \

+     (((INSTANCE) == TIM12) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2)))           \

+  ||                                           \

+     (((INSTANCE) == TIM13) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM14) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM15) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1) ||          \

+     ((CHANNEL) == TIM_CHANNEL_2)))            \

+  ||                                           \

+     (((INSTANCE) == TIM16) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1)))           \

+  ||                                           \

+     (((INSTANCE) == TIM17) &&                 \

+     (((CHANNEL) == TIM_CHANNEL_1))))

+

+/****************** TIM Instances : supporting the break function *************/

+#define IS_TIM_BREAK_INSTANCE(INSTANCE)\

+      (((INSTANCE) == TIM1)    || \

+      ((INSTANCE) == TIM8)     || \

+       ((INSTANCE) == TIM15)   || \

+       ((INSTANCE) == TIM16)   || \

+       ((INSTANCE) == TIM17))

+

+/************** TIM Instances : supporting Break source selection *************/

+#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1)   || \

+                                               ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting complementary output(s) ********/

+#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \

+   ((((INSTANCE) == TIM1) &&                    \

+     (((CHANNEL) == TIM_CHANNEL_1) ||           \

+      ((CHANNEL) == TIM_CHANNEL_2) ||           \

+      ((CHANNEL) == TIM_CHANNEL_3)))            \

+ ||                                             \

+      (((INSTANCE) == TIM8) &&                  \

+      (((CHANNEL) == TIM_CHANNEL_1) ||          \

+      ((CHANNEL) == TIM_CHANNEL_2) ||           \

+      ((CHANNEL) == TIM_CHANNEL_3)))            \

+    ||                                          \

+    (((INSTANCE) == TIM15) &&                   \

+      ((CHANNEL) == TIM_CHANNEL_1))             \

+    ||                                          \

+    (((INSTANCE) == TIM16) &&                   \

+     ((CHANNEL) == TIM_CHANNEL_1))              \

+    ||                                          \

+    (((INSTANCE) == TIM17) &&                   \

+     ((CHANNEL) == TIM_CHANNEL_1)))

+

+/****************** TIM Instances : supporting counting mode selection ********/

+#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting repetition counter *************/

+#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15)   || \

+   ((INSTANCE) == TIM16)   || \

+   ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting synchronization ****************/

+#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\

+    (((__INSTANCE__) == TIM1)    || \

+     ((__INSTANCE__) == TIM2)    || \

+     ((__INSTANCE__) == TIM3)    || \

+     ((__INSTANCE__) == TIM4)    || \

+     ((__INSTANCE__) == TIM5)    || \

+     ((__INSTANCE__) == TIM6)    || \

+     ((__INSTANCE__) == TIM8)    || \

+     ((__INSTANCE__) == TIM12)   || \

+     ((__INSTANCE__) == TIM15))

+

+/****************** TIM Instances : supporting clock division *****************/

+#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15)   || \

+   ((INSTANCE) == TIM16)   || \

+   ((INSTANCE) == TIM17))

+

+/****************** TIM Instances : supporting external clock mode 1 for ETRF input */

+#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting external clock mode 2 **********/

+#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\

+ (((INSTANCE) == TIM1)     || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/

+#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/

+#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3)    || \

+   ((INSTANCE) == TIM4)    || \

+   ((INSTANCE) == TIM5)    || \

+   ((INSTANCE) == TIM8)    || \

+   ((INSTANCE) == TIM15))

+

+/****************** TIM Instances : supporting OCxREF clear *******************/

+#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM3))

+

+/****************** TIM Instances : TIM_32B_COUNTER ***************************/

+#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM2)    || \

+   ((INSTANCE) == TIM5))

+

+/****************** TIM Instances : TIM_BKIN2 ***************************/

+#define IS_TIM_BKIN2_INSTANCE(INSTANCE)\

+  (((INSTANCE) == TIM1)    || \

+   ((INSTANCE) == TIM8))

+

+/****************** TIM Instances : supporting Hall sensor interface **********/

+#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1)  || \

+                                                             ((__INSTANCE__) == TIM2)  || \

+                                                             ((__INSTANCE__) == TIM3)  || \

+                                                             ((__INSTANCE__) == TIM4)  || \

+                                                             ((__INSTANCE__) == TIM5)  || \

+                                                             ((__INSTANCE__) == TIM15) || \

+                                                             ((__INSTANCE__) == TIM8))

+

+/******************** USART Instances : Synchronous mode **********************/

+#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                     ((INSTANCE) == USART2) || \

+                                     ((INSTANCE) == USART3) || \

+                                     ((INSTANCE) == USART6) || \

+                                     ((INSTANCE) == USART10))

+

+/******************** USART Instances : SPI slave mode ************************/

+#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                              ((INSTANCE) == USART2) || \

+                                              ((INSTANCE) == USART3) || \

+                                              ((INSTANCE) == USART6) || \

+                                              ((INSTANCE) == USART10))

+

+/******************** UART Instances : Asynchronous mode **********************/

+#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                    ((INSTANCE) == USART2) || \

+                                    ((INSTANCE) == USART3) || \

+                                    ((INSTANCE) == UART4)  || \

+                                    ((INSTANCE) == UART5)  || \

+                                    ((INSTANCE) == USART6) || \

+                                    ((INSTANCE) == UART7)  || \

+                                    ((INSTANCE) == UART8)  || \

+                                    ((INSTANCE) == UART9)  || \

+                                    ((INSTANCE) == USART10))

+

+/******************** UART Instances : FIFO mode.******************************/

+#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                         ((INSTANCE) == USART2) || \

+                                         ((INSTANCE) == USART3) || \

+                                         ((INSTANCE) == UART4)  || \

+                                         ((INSTANCE) == UART5)  || \

+                                         ((INSTANCE) == USART6) || \

+                                         ((INSTANCE) == UART7)  || \

+                                         ((INSTANCE) == UART8)  || \

+                                         ((INSTANCE) == UART9)  || \

+                                         ((INSTANCE) == USART10)|| \

+                                         ((INSTANCE) == LPUART1))

+

+/****************** UART Instances : Auto Baud Rate detection *****************/

+#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                            ((INSTANCE) == USART2) || \

+                                                            ((INSTANCE) == USART3) || \

+                                                            ((INSTANCE) == UART4)  || \

+                                                            ((INSTANCE) == UART5)  || \

+                                                            ((INSTANCE) == USART6) || \

+                                                            ((INSTANCE) == UART7)  || \

+                                                            ((INSTANCE) == UART8)  || \

+                                                            ((INSTANCE) == UART9)  || \

+                                                            ((INSTANCE) == USART10))

+

+/*********************** UART Instances : Driver Enable ***********************/

+#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                  ((INSTANCE) == USART2) || \

+                                                  ((INSTANCE) == USART3) || \

+                                                  ((INSTANCE) == UART4)  || \

+                                                  ((INSTANCE) == UART5)  || \

+                                                  ((INSTANCE) == USART6) || \

+                                                  ((INSTANCE) == UART7)  || \

+                                                  ((INSTANCE) == UART8)  || \

+                                                  ((INSTANCE) == UART9)  || \

+                                                  ((INSTANCE) == USART10)|| \

+                                                  ((INSTANCE) == LPUART1))

+

+/********************* UART Instances : Half-Duplex mode **********************/

+#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                               ((INSTANCE) == USART2) || \

+                                               ((INSTANCE) == USART3) || \

+                                               ((INSTANCE) == UART4)  || \

+                                               ((INSTANCE) == UART5)  || \

+                                               ((INSTANCE) == USART6) || \

+                                               ((INSTANCE) == UART7)  || \

+                                               ((INSTANCE) == UART8)  || \

+                                               ((INSTANCE) == UART9)  || \

+                                               ((INSTANCE) == USART10)|| \

+                                               ((INSTANCE) == LPUART1))

+

+/******************* UART Instances : Hardware Flow control *******************/

+#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                           ((INSTANCE) == USART2) || \

+                                           ((INSTANCE) == USART3) || \

+                                           ((INSTANCE) == UART4)  || \

+                                           ((INSTANCE) == UART5)  || \

+                                           ((INSTANCE) == USART6) || \

+                                           ((INSTANCE) == UART7)  || \

+                                           ((INSTANCE) == UART8)  || \

+                                           ((INSTANCE) == UART9)  || \

+                                           ((INSTANCE) == USART10)|| \

+                                           ((INSTANCE) == LPUART1))

+

+/************************* UART Instances : LIN mode **************************/

+#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                        ((INSTANCE) == USART2) || \

+                                        ((INSTANCE) == USART3) || \

+                                        ((INSTANCE) == UART4)  || \

+                                        ((INSTANCE) == UART5)  || \

+                                        ((INSTANCE) == USART6) || \

+                                        ((INSTANCE) == UART7)  || \

+                                        ((INSTANCE) == UART8)  || \

+                                        ((INSTANCE) == UART9)  || \

+                                        ((INSTANCE) == USART10))

+

+/****************** UART Instances : Wake-up from Stop mode *******************/

+#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                                    ((INSTANCE) == USART2) || \

+                                                    ((INSTANCE) == USART3) || \

+                                                    ((INSTANCE) == UART4)  || \

+                                                    ((INSTANCE) == UART5)  || \

+                                                    ((INSTANCE) == USART6) || \

+                                                    ((INSTANCE) == UART7)  || \

+                                                    ((INSTANCE) == UART8)  || \

+                                                    ((INSTANCE) == UART9)  || \

+                                                    ((INSTANCE) == USART10)|| \

+                                                    ((INSTANCE) == LPUART1))

+

+/************************* UART Instances : IRDA mode *************************/

+#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                    ((INSTANCE) == USART2) || \

+                                    ((INSTANCE) == USART3) || \

+                                    ((INSTANCE) == UART4)  || \

+                                    ((INSTANCE) == UART5)  || \

+                                    ((INSTANCE) == USART6) || \

+                                    ((INSTANCE) == UART7)  || \

+                                    ((INSTANCE) == UART8)  || \

+                                    ((INSTANCE) == UART9)  || \

+                                    ((INSTANCE) == USART10))

+

+/********************* USART Instances : Smard card mode **********************/

+#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \

+                                         ((INSTANCE) == USART2) || \

+                                         ((INSTANCE) == USART3) || \

+                                         ((INSTANCE) == USART6) ||\

+                                         ((INSTANCE) == USART10))

+

+/****************************** LPUART Instance *******************************/

+#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)

+

+/****************************** IWDG Instances ********************************/

+#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG1)

+/****************************** USB Instances ********************************/

+#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)

+

+/****************************** WWDG Instances ********************************/

+#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG1)

+/****************************** MDIOS Instances ********************************/

+#define IS_MDIOS_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == MDIOS)

+

+/****************************** CEC Instances *********************************/

+#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)

+

+/****************************** SAI Instances ********************************/

+#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \

+                                       ((INSTANCE) == SAI1_Block_B) || \

+                                       ((INSTANCE) == SAI2_Block_A) || \

+                                       ((INSTANCE) == SAI2_Block_B))

+

+/****************************** SPDIFRX Instances ********************************/

+#define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)

+

+/****************************** OPAMP Instances *******************************/

+#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \

+                                         ((INSTANCE) == OPAMP2))

+

+#define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)

+

+/*********************** USB OTG PCD Instances ********************************/

+#define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS)

+

+/*********************** USB OTG HCD Instances ********************************/

+#define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS)

+

+/******************************************************************************/

+/*  For a painless codes migration between the STM32H7xx device product       */

+/*  lines, or with STM32F7xx devices the aliases defined below are put        */

+/*   in place to overcome the differences in the interrupt handlers and IRQn  */

+/*   definitions. No need to update developed interrupt code when moving      */

+/*  across product lines within the same STM32H7 Family                       */

+/******************************************************************************/

+

+/* Aliases for __IRQn */

+#define  RNG_IRQn                       HASH_RNG_IRQn

+#define  TIM1_BRK_TIM9_IRQn             TIM1_BRK_IRQn

+#define  TIM1_UP_TIM10_IRQn             TIM1_UP_IRQn

+#define  TIM1_TRG_COM_TIM11_IRQn        TIM1_TRG_COM_IRQn

+#define  PVD_IRQn                       PVD_AVD_IRQn

+

+/* Aliases for BDMA __IRQn */

+#define  BDMA_Channel0_IRQn             BDMA2_Channel0_IRQn

+#define  BDMA_Channel1_IRQn             BDMA2_Channel1_IRQn

+#define  BDMA_Channel2_IRQn             BDMA2_Channel2_IRQn

+#define  BDMA_Channel3_IRQn             BDMA2_Channel3_IRQn

+#define  BDMA_Channel4_IRQn             BDMA2_Channel4_IRQn

+#define  BDMA_Channel5_IRQn             BDMA2_Channel5_IRQn

+#define  BDMA_Channel6_IRQn             BDMA2_Channel6_IRQn

+#define  BDMA_Channel7_IRQn             BDMA2_Channel7_IRQn

+

+/* Aliases for PWR __IRQn */

+#define  PVD_AVD_IRQn                   PVD_PVM_IRQn

+

+/* Aliases for DCMI/PSSI __IRQn */

+#define  DCMI_IRQn                      DCMI_PSSI_IRQn

+

+/* Aliases for __IRQHandler */

+#define   RNG_IRQHandler               HASH_RNG_IRQHandler

+#define TIM1_BRK_TIM9_IRQHandler       TIM1_BRK_IRQHandler

+#define TIM1_UP_TIM9_IRQHandler        TIM1_UP_IRQHandler

+#define TIM1_TRG_COM_TIM11_IRQHandler  TIM1_TRG_COM_IRQHandler

+#define PVD_IRQHandler                 PVD_AVD_IRQHandler

+

+

+/* Aliases for BDMA __IRQHandler */

+#define  BDMA_Channel0_IRQHandler      BDMA2_Channel0_IRQHandler

+#define  BDMA_Channel1_IRQHandler      BDMA2_Channel1_IRQHandler

+#define  BDMA_Channel2_IRQHandler      BDMA2_Channel2_IRQHandler

+#define  BDMA_Channel3_IRQHandler      BDMA2_Channel3_IRQHandler

+#define  BDMA_Channel4_IRQHandler      BDMA2_Channel4_IRQHandler

+#define  BDMA_Channel5_IRQHandler      BDMA2_Channel5_IRQHandler

+#define  BDMA_Channel6_IRQHandler      BDMA2_Channel6_IRQHandler

+#define  BDMA_Channel7_IRQHandler      BDMA2_Channel7_IRQHandler

+

+/* Aliases for PWR __IRQHandler */

+#define  PVD_AVD_IRQHandler            PVD_PVM_IRQHandler

+

+/* Aliases for DCMI/PSSI __IRQHandler */

+#define  DCMI_IRQHandler               DCMI_PSSI_IRQHandler

+

+/* Alias for BDMA defines */

+#define BDMA_BASE              BDMA2_BASE

+#define BDMA_Channel0_BASE     BDMA2_Channel0_BASE

+#define BDMA_Channel1_BASE     BDMA2_Channel1_BASE

+#define BDMA_Channel2_BASE     BDMA2_Channel2_BASE

+#define BDMA_Channel3_BASE     BDMA2_Channel3_BASE

+#define BDMA_Channel4_BASE     BDMA2_Channel4_BASE

+#define BDMA_Channel5_BASE     BDMA2_Channel5_BASE

+#define BDMA_Channel6_BASE     BDMA2_Channel6_BASE

+#define BDMA_Channel7_BASE     BDMA2_Channel7_BASE

+

+#define BDMA                   BDMA2

+#define BDMA_Channel0          BDMA2_Channel0

+#define BDMA_Channel1          BDMA2_Channel1

+#define BDMA_Channel2          BDMA2_Channel2

+#define BDMA_Channel3          BDMA2_Channel3

+#define BDMA_Channel4          BDMA2_Channel4

+#define BDMA_Channel5          BDMA2_Channel5

+#define BDMA_Channel6          BDMA2_Channel6

+#define BDMA_Channel7          BDMA2_Channel7

+

+/* Alias for PWR defines */

+#define PWR_CPUCR_RUN_D3       PWR_CPUCR_RUN_SRD

+#define PWR_CPUCR_PDDS_D3      PWR_CPUCR_PDDS_SRD

+#define PWR_CPUCR_PDDS_D1      PWR_CPUCR_RETDS_CD

+

+#define PWR_D3CR_VOS           PWR_SRDCR_VOS

+

+#define PWR_D3CR_VOS_0         PWR_SRDCR_VOS_0

+#define PWR_D3CR_VOS_1         PWR_SRDCR_VOS_1

+#define PWR_D3CR_VOSRDY        PWR_SRDCR_VOSRDY

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif /* __cplusplus */

+

+#endif /* STM32H7B3xxQ_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx.h b/bsps/arm/stm32h7/include/stm32h7xx.h
new file mode 100644
index 0000000000..f6296181be
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx.h
@@ -0,0 +1,224 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx.h

+  * @author  MCD Application Team

+  * @brief   CMSIS STM32H7xx Device Peripheral Access Layer Header File.

+  *

+  *          The file is the unique include file that the application programmer

+  *          is using in the C source code, usually in main.c. This file contains:

+  *           - Configuration section that allows to select:

+  *              - The STM32H7xx device used in the target application

+  *              - To use or not the peripheral’s drivers in application code(i.e.

+  *                code will be based on direct access to peripheral’s registers

+  *                rather than drivers API), this option is controlled by

+  *                "#define USE_HAL_DRIVER"

+  *

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/** @addtogroup CMSIS

+  * @{

+  */

+

+/** @addtogroup stm32h7xx

+  * @{

+  */

+

+#ifndef STM32H7xx_H

+#define STM32H7xx_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif /* __cplusplus */

+

+/** @addtogroup Library_configuration_section

+  * @{

+  */

+

+/**

+  * @brief STM32 Family

+  */

+#if !defined  (STM32H7)

+#define STM32H7

+#endif /* STM32H7 */

+

+

+/* Uncomment the line below according to the target STM32H7 device used in your

+   application

+  */

+

+#if !defined (STM32H743xx) && !defined (STM32H753xx)  && !defined (STM32H750xx) && !defined (STM32H742xx) && \

+    !defined (STM32H745xx) && !defined (STM32H755xx)  && !defined (STM32H747xx) && !defined (STM32H757xx) && \

+    !defined (STM32H7A3xx) && !defined (STM32H7A3xxQ) && !defined (STM32H7B3xx) && !defined (STM32H7B3xxQ) && !defined (STM32H7B0xx)  && !defined (STM32H7B0xxQ)

+  /* #define STM32H742xx */   /*!< STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI Devices */

+  /* #define STM32H743xx */   /*!< STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI Devices */

+  /* #define STM32H753xx */   /*!< STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI Devices */

+  /* #define STM32H750xx */   /*!< STM32H750V, STM32H750I, STM32H750X Devices */

+  /* #define STM32H747xx */   /*!< STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI Devices */

+  /* #define STM32H757xx */   /*!< STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI Devices */

+  /* #define STM32H745xx */   /*!< STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI Devices  */

+  /* #define STM32H755xx */   /*!< STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI Devices  */

+  /* #define STM32H7B0xx */   /*!< STM32H7B0ABIxQ, STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx, STM32H7B0IBKxQ */

+  /* #define STM32H7A3xx */   /*!< STM32H7A3IIK6, STM32H7A3IIT6, STM32H7A3NIH6, STM32H7A3RIT6, STM32H7A3VIH6, STM32H7A3VIT6, STM32H7A3ZIT6 */

+  /* #define STM32H7A3xxQ */  /*!< STM32H7A3QIY6Q, STM32H7A3IIK6Q, STM32H7A3IIT6Q, STM32H7A3LIH6Q, STM32H7A3VIH6Q, STM32H7A3VIT6Q, STM32H7A3AII6Q, STM32H7A3ZIT6Q */

+  /* #define STM32H7B3xx */   /*!< STM32H7B3IIK6, STM32H7B3IIT6, STM32H7B3NIH6, STM32H7B3RIT6, STM32H7B3VIH6, STM32H7B3VIT6, STM32H7B3ZIT6 */

+  /* #define STM32H7B3xxQ */  /*!< STM32H7B3QIY6Q, STM32H7B3IIK6Q, STM32H7B3IIT6Q, STM32H7B3LIH6Q, STM32H7B3VIH6Q, STM32H7B3VIT6Q, STM32H7B3AII6Q, STM32H7B3ZIT6Q */

+#endif

+

+/*  Tip: To avoid modifying this file each time you need to switch between these

+        devices, you can define the device in your toolchain compiler preprocessor.

+  */

+

+#if defined(DUAL_CORE) && !defined(CORE_CM4) && !defined(CORE_CM7)

+ #error "Dual core device, please select CORE_CM4 or CORE_CM7"

+#endif

+

+#if !defined  (USE_HAL_DRIVER)

+/**

+ * @brief Comment the line below if you will not use the peripherals drivers.

+   In this case, these drivers will not be included and the application code will

+   be based on direct access to peripherals registers

+   */

+  /*#define USE_HAL_DRIVER */

+#endif /* USE_HAL_DRIVER */

+

+/**

+  * @brief CMSIS Device version number V1.8.0

+  */

+#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN   (0x01) /*!< [31:24] main version */

+#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1   (0x08) /*!< [23:16] sub1 version */

+#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */

+#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */

+#define __STM32H7xx_CMSIS_DEVICE_VERSION        ((__CMSIS_DEVICE_VERSION_MAIN     << 24)\

+                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\

+                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\

+                                      |(__CMSIS_DEVICE_HAL_VERSION_RC))

+

+/**

+  * @}

+  */

+

+/** @addtogroup Device_Included

+  * @{

+  */

+

+#if defined(STM32H743xx)

+  #include "stm32h743xx.h"

+#elif defined(STM32H753xx)

+  #include "stm32h753xx.h"

+#elif defined(STM32H750xx)

+  #include "stm32h750xx.h"

+#elif defined(STM32H742xx)

+  #include "stm32h742xx.h"

+#elif defined(STM32H745xx)

+  #include "stm32h745xx.h"

+#elif defined(STM32H755xx)

+  #include "stm32h755xx.h"

+#elif defined(STM32H747xx)

+  #include "stm32h747xx.h"

+#elif defined(STM32H757xx)

+  #include "stm32h757xx.h"

+#elif defined(STM32H7B0xx)

+  #include "stm32h7b0xx.h"

+#elif defined(STM32H7B0xxQ)

+  #include "stm32h7b0xxq.h"

+#elif defined(STM32H7A3xx)

+  #include "stm32h7a3xx.h"

+#elif defined(STM32H7B3xx)

+  #include "stm32h7b3xx.h"

+#elif defined(STM32H7A3xxQ)

+  #include "stm32h7a3xxq.h"

+#elif defined(STM32H7B3xxQ)

+  #include "stm32h7b3xxq.h"

+#else

+ #error "Please select first the target STM32H7xx device used in your application (in stm32h7xx.h file)"

+#endif

+

+/**

+  * @}

+  */

+

+/** @addtogroup Exported_types

+  * @{

+  */

+typedef enum

+{

+  RESET = 0,

+  SET = !RESET

+} FlagStatus, ITStatus;

+

+typedef enum

+{

+  DISABLE = 0,

+  ENABLE = !DISABLE

+} FunctionalState;

+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))

+

+typedef enum

+{

+  SUCCESS = 0,

+  ERROR = !SUCCESS

+} ErrorStatus;

+

+/**

+  * @}

+  */

+

+

+/** @addtogroup Exported_macros

+  * @{

+  */

+#define SET_BIT(REG, BIT)     ((REG) |= (BIT))

+

+#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))

+

+#define READ_BIT(REG, BIT)    ((REG) & (BIT))

+

+#define CLEAR_REG(REG)        ((REG) = (0x0))

+

+#define WRITE_REG(REG, VAL)   ((REG) = (VAL))

+

+#define READ_REG(REG)         ((REG))

+

+#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))

+

+#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL)))

+

+

+/**

+  * @}

+  */

+

+#if defined (USE_HAL_DRIVER)

+ #include "stm32h7xx_hal.h"

+#endif /* USE_HAL_DRIVER */

+

+

+#ifdef __cplusplus

+}

+#endif /* __cplusplus */

+

+#endif /* STM32H7xx_H */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+

+

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal.h b/bsps/arm/stm32h7/include/stm32h7xx_hal.h
new file mode 100644
index 0000000000..2ee957c352
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal.h
@@ -0,0 +1,1078 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal.h

+  * @author  MCD Application Team

+  * @brief   This file contains all the functions prototypes for the HAL

+  *          module driver.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_H

+#define STM32H7xx_HAL_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_conf.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup HAL

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup HAL_TICK_FREQ Tick Frequency

+  * @{

+  */

+typedef enum

+{

+  HAL_TICK_FREQ_10HZ         = 100U,

+  HAL_TICK_FREQ_100HZ        = 10U,

+  HAL_TICK_FREQ_1KHZ         = 1U,

+  HAL_TICK_FREQ_DEFAULT      = HAL_TICK_FREQ_1KHZ

+} HAL_TickFreqTypeDef;

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+

+/** @defgroup REV_ID device revision ID

+  * @{

+  */

+#define REV_ID_Y ((uint32_t)0x1003)  /*!< STM32H7 rev.Y */

+#define REV_ID_B ((uint32_t)0x2000)  /*!< STM32H7 rev.B */

+#define REV_ID_X ((uint32_t)0x2001)  /*!< STM32H7 rev.X */

+#define REV_ID_V ((uint32_t)0x2003)  /*!< STM32H7 rev.V */

+

+/**

+  * @}

+  */

+

+/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale

+  * @{

+  */

+#define SYSCFG_VREFBUF_VOLTAGE_SCALE0   VREFBUF_CSR_VRS_OUT2   /*!< Voltage reference scale 0 (VREF_OUT2) */

+#define SYSCFG_VREFBUF_VOLTAGE_SCALE1   VREFBUF_CSR_VRS_OUT1   /*!< Voltage reference scale 1 (VREF_OUT1) */

+#define SYSCFG_VREFBUF_VOLTAGE_SCALE2   VREFBUF_CSR_VRS_OUT4   /*!< Voltage reference scale 2 (VREF_OUT4) */

+#define SYSCFG_VREFBUF_VOLTAGE_SCALE3   VREFBUF_CSR_VRS_OUT3   /*!< Voltage reference scale 3 (VREF_OUT3) */

+

+

+#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__)  (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \

+                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \

+                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || \

+                                                     ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3))

+

+

+/**

+  * @}

+  */

+

+/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance

+  * @{

+  */

+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE  ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */

+#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE   VREFBUF_CSR_HIZ        /*!< VREF_plus pin is high impedance */

+

+#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__)  (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \

+                                                      ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))

+

+#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__)  (((__VALUE__) > 0UL) && ((__VALUE__) <= VREFBUF_CCR_TRIM))

+

+/**

+  * @}

+  */

+

+#if !defined(SYSCFG_PMCR_BOOSTEN)

+/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO

+  * @{

+  */

+

+/** @brief  Fast-mode Plus driving capability on a specific GPIO

+  */

+#define SYSCFG_FASTMODEPLUS_PB6        SYSCFG_PMCR_I2C_PB6_FMP  /*!< Enable Fast-mode Plus on PB6 */

+#define SYSCFG_FASTMODEPLUS_PB7        SYSCFG_PMCR_I2C_PB7_FMP  /*!< Enable Fast-mode Plus on PB7 */

+#define SYSCFG_FASTMODEPLUS_PB8        SYSCFG_PMCR_I2C_PB8_FMP  /*!< Enable Fast-mode Plus on PB8 */

+#define SYSCFG_FASTMODEPLUS_PB9        SYSCFG_PMCR_I2C_PB9_FMP  /*!< Enable Fast-mode Plus on PB9 */

+

+#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \

+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \

+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \

+                                         (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))

+

+#endif /* ! SYSCFG_PMCR_BOOSTEN */

+/**

+  * @}

+  */

+

+/** @defgroup SYSCFG_Ethernet_Config  Ethernet Config

+  * @{

+  */

+#define SYSCFG_ETH_MII                      ((uint32_t)0x00000000)  /*!< Select the Media Independent Interface */

+#define SYSCFG_ETH_RMII                     SYSCFG_PMCR_EPIS_SEL_2  /*!< Select the Reduced Media Independent Interface */

+

+#define IS_SYSCFG_ETHERNET_CONFIG(CONFIG) (((CONFIG) == SYSCFG_ETH_MII)        || \

+                                          ((CONFIG) == SYSCFG_ETH_RMII))

+

+/**

+  * @}

+  */

+

+

+/** @defgroup SYSCFG_Analog_Switch_Config  Analog Switch Config

+  * @{

+  */

+#define SYSCFG_SWITCH_PA0                       SYSCFG_PMCR_PA0SO  /*!< Select PA0 analog switch */

+#define SYSCFG_SWITCH_PA1                       SYSCFG_PMCR_PA1SO  /*!< Select PA1 analog switch */

+#define SYSCFG_SWITCH_PC2                       SYSCFG_PMCR_PC2SO  /*!< Select PC2 analog switch */

+#define SYSCFG_SWITCH_PC3                       SYSCFG_PMCR_PC3SO  /*!< Select PC3 analog switch */

+

+

+#define IS_SYSCFG_ANALOG_SWITCH(SWITCH)    ((((SWITCH) & SYSCFG_SWITCH_PA0) == SYSCFG_SWITCH_PA0)|| \

+                                           (((SWITCH) & SYSCFG_SWITCH_PA1) == SYSCFG_SWITCH_PA1) || \

+                                           (((SWITCH) & SYSCFG_SWITCH_PC2) == SYSCFG_SWITCH_PC2) || \

+                                           (((SWITCH) & SYSCFG_SWITCH_PC3) == SYSCFG_SWITCH_PC3))

+

+

+#define SYSCFG_SWITCH_PA0_OPEN                       SYSCFG_PMCR_PA0SO       /*!< PA0 analog switch opened */

+#define SYSCFG_SWITCH_PA0_CLOSE                      ((uint32_t)0x00000000)  /*!< PA0 analog switch closed */

+#define SYSCFG_SWITCH_PA1_OPEN                       SYSCFG_PMCR_PA1SO       /*!< PA1 analog switch opened */

+#define SYSCFG_SWITCH_PA1_CLOSE                      ((uint32_t)0x00000000)  /*!< PA1 analog switch closed*/

+#define SYSCFG_SWITCH_PC2_OPEN                       SYSCFG_PMCR_PC2SO       /*!< PC2 analog switch opened */

+#define SYSCFG_SWITCH_PC2_CLOSE                      ((uint32_t)0x00000000)  /*!< PC2 analog switch closed */

+#define SYSCFG_SWITCH_PC3_OPEN                       SYSCFG_PMCR_PC3SO       /*!< PC3 analog switch opened */

+#define SYSCFG_SWITCH_PC3_CLOSE                      ((uint32_t)0x00000000)  /*!< PC3 analog switch closed */

+

+#define IS_SYSCFG_SWITCH_STATE(STATE)      ((((STATE) & SYSCFG_SWITCH_PA0_OPEN) == SYSCFG_SWITCH_PA0_OPEN)    || \

+                                           (((STATE) & SYSCFG_SWITCH_PA0_CLOSE) == SYSCFG_SWITCH_PA0_CLOSE)   || \

+                                           (((STATE) & SYSCFG_SWITCH_PA1_OPEN) == SYSCFG_SWITCH_PA1_OPEN)     || \

+                                           (((STATE) & SYSCFG_SWITCH_PA1_CLOSE) == SYSCFG_SWITCH_PA1_CLOSE)   || \

+                                           (((STATE) & SYSCFG_SWITCH_PC2_OPEN) == SYSCFG_SWITCH_PC2_OPEN)     || \

+                                           (((STATE) & SYSCFG_SWITCH_PC2_CLOSE) == SYSCFG_SWITCH_PC2_CLOSE)   || \

+                                           (((STATE) & SYSCFG_SWITCH_PC3_OPEN) == SYSCFG_SWITCH_PC3_OPEN)     || \

+                                           (((STATE) & SYSCFG_SWITCH_PC3_CLOSE) == SYSCFG_SWITCH_PC3_CLOSE))

+/**

+  * @}

+  */

+

+/** @defgroup SYSCFG_Boot_Config  Boot Config

+  * @{

+  */

+#define SYSCFG_BOOT_ADDR0                    ((uint32_t)0x00000000)  /*!< Select Boot address0 */

+#define SYSCFG_BOOT_ADDR1                    ((uint32_t)0x00000001)  /*!< Select Boot address1 */

+

+#define IS_SYSCFG_BOOT_REGISTER(REGISTER) (((REGISTER) == SYSCFG_BOOT_ADDR0)|| \

+                                          ((REGISTER) == SYSCFG_BOOT_ADDR1))

+

+#define IS_SYSCFG_BOOT_ADDRESS(ADDRESS) ((ADDRESS) < PERIPH_BASE)

+

+/**

+  * @}

+  */

+

+

+/** @defgroup SYSCFG_IOCompenstionCell_Config  IOCompenstionCell Config

+  * @{

+  */

+#define SYSCFG_CELL_CODE                    ((uint32_t)0x00000000)  /*!< Select Code from the cell */

+#define SYSCFG_REGISTER_CODE                 SYSCFG_CCCSR_CS        /*!< Code from the SYSCFG compensation cell code register */

+

+#define IS_SYSCFG_CODE_SELECT(SELECT) (((SELECT) == SYSCFG_CELL_CODE)|| \

+                                        ((SELECT) == SYSCFG_REGISTER_CODE))

+

+#define IS_SYSCFG_CODE_CONFIG(CONFIG) ((CONFIG) < (0x10UL))

+

+/**

+  * @}

+  */

+

+

+

+

+/** @defgroup EXTI_Event_Input_Config  Event Input Config

+  * @{

+  */

+

+#define EXTI_MODE_IT          ((uint32_t)0x00010000)

+#define EXTI_MODE_EVT         ((uint32_t)0x00020000)

+#define EXTI_RISING_EDGE      ((uint32_t)0x00100000)

+#define EXTI_FALLING_EDGE     ((uint32_t)0x00200000)

+

+#define IS_EXTI_EDGE_LINE(EDGE) (((EDGE) == EXTI_RISING_EDGE) || ((EDGE) == EXTI_FALLING_EDGE))

+#define IS_EXTI_MODE_LINE(MODE) (((MODE) == EXTI_MODE_IT) || ((MODE) == EXTI_MODE_EVT))

+

+#define EXTI_LINE0       ((uint32_t)0x00)  /*!< External interrupt LINE 0  */

+#define EXTI_LINE1       ((uint32_t)0x01)  /*!< External interrupt LINE 1  */

+#define EXTI_LINE2       ((uint32_t)0x02)  /*!< External interrupt LINE 2  */

+#define EXTI_LINE3       ((uint32_t)0x03)  /*!< External interrupt LINE 3  */

+#define EXTI_LINE4       ((uint32_t)0x04)  /*!< External interrupt LINE 4  */

+#define EXTI_LINE5       ((uint32_t)0x05)  /*!< External interrupt LINE 5  */

+#define EXTI_LINE6       ((uint32_t)0x06)  /*!< External interrupt LINE 6  */

+#define EXTI_LINE7       ((uint32_t)0x07)  /*!< External interrupt LINE 7  */

+#define EXTI_LINE8       ((uint32_t)0x08)  /*!< External interrupt LINE 8  */

+#define EXTI_LINE9       ((uint32_t)0x09)  /*!< External interrupt LINE 9  */

+#define EXTI_LINE10      ((uint32_t)0x0A)  /*!< External interrupt LINE 10 */

+#define EXTI_LINE11      ((uint32_t)0x0B)  /*!< External interrupt LINE 11 */

+#define EXTI_LINE12      ((uint32_t)0x0C)  /*!< External interrupt LINE 12 */

+#define EXTI_LINE13      ((uint32_t)0x0D)  /*!< External interrupt LINE 13 */

+#define EXTI_LINE14      ((uint32_t)0x0E)  /*!< External interrupt LINE 14 */

+#define EXTI_LINE15      ((uint32_t)0x0F)  /*!< External interrupt LINE 15 */

+#define EXTI_LINE16      ((uint32_t)0x10)

+#define EXTI_LINE17      ((uint32_t)0x11)

+#define EXTI_LINE18      ((uint32_t)0x12)

+#define EXTI_LINE19      ((uint32_t)0x13)

+#define EXTI_LINE20      ((uint32_t)0x14)

+#define EXTI_LINE21      ((uint32_t)0x15)

+#define EXTI_LINE22      ((uint32_t)0x16)

+#define EXTI_LINE23      ((uint32_t)0x17)

+#define EXTI_LINE24      ((uint32_t)0x18)

+#define EXTI_LINE25      ((uint32_t)0x19)

+#define EXTI_LINE26      ((uint32_t)0x1A)

+#define EXTI_LINE27      ((uint32_t)0x1B)

+#define EXTI_LINE28      ((uint32_t)0x1C)

+#define EXTI_LINE29      ((uint32_t)0x1D)

+#define EXTI_LINE30      ((uint32_t)0x1E)

+#define EXTI_LINE31      ((uint32_t)0x1F)

+#define EXTI_LINE32      ((uint32_t)0x20)

+#define EXTI_LINE33      ((uint32_t)0x21)

+#define EXTI_LINE34      ((uint32_t)0x22)

+#define EXTI_LINE35      ((uint32_t)0x23)

+#define EXTI_LINE36      ((uint32_t)0x24)

+#define EXTI_LINE37      ((uint32_t)0x25)

+#define EXTI_LINE38      ((uint32_t)0x26)

+#define EXTI_LINE39      ((uint32_t)0x27)

+

+#define EXTI_LINE40      ((uint32_t)0x28)

+#define EXTI_LINE41      ((uint32_t)0x29)

+#define EXTI_LINE42      ((uint32_t)0x2A)

+#define EXTI_LINE43      ((uint32_t)0x2B)

+#define EXTI_LINE44      ((uint32_t)0x2C)  /* Not available in all family lines */

+/* EXTI_LINE45 Reserved */

+#if defined(DUAL_CORE)

+#define EXTI_LINE46      ((uint32_t)0x2E)

+#else

+/* EXTI_LINE46 Reserved */

+#endif /* DUAL_CORE */

+#define EXTI_LINE47      ((uint32_t)0x2F)

+#define EXTI_LINE48      ((uint32_t)0x30)

+#define EXTI_LINE49      ((uint32_t)0x31)

+#define EXTI_LINE50      ((uint32_t)0x32)

+#define EXTI_LINE51      ((uint32_t)0x33)

+#define EXTI_LINE52      ((uint32_t)0x34)

+#define EXTI_LINE53      ((uint32_t)0x35)

+#define EXTI_LINE54      ((uint32_t)0x36)

+#define EXTI_LINE55      ((uint32_t)0x37)

+#define EXTI_LINE56      ((uint32_t)0x38)

+#define EXTI_LINE57      ((uint32_t)0x39)

+#define EXTI_LINE58      ((uint32_t)0x3A)

+#define EXTI_LINE59      ((uint32_t)0x3B)

+#define EXTI_LINE60      ((uint32_t)0x3C)

+#define EXTI_LINE61      ((uint32_t)0x3D)

+#define EXTI_LINE62      ((uint32_t)0x3E)

+#define EXTI_LINE63      ((uint32_t)0x3F)

+#define EXTI_LINE64      ((uint32_t)0x40)

+#define EXTI_LINE65      ((uint32_t)0x41)

+#define EXTI_LINE66      ((uint32_t)0x42)

+#define EXTI_LINE67      ((uint32_t)0x43)

+#define EXTI_LINE68      ((uint32_t)0x44)

+#define EXTI_LINE69      ((uint32_t)0x45)

+#define EXTI_LINE70      ((uint32_t)0x46)

+#define EXTI_LINE71      ((uint32_t)0x47)

+#define EXTI_LINE72      ((uint32_t)0x48)

+#define EXTI_LINE73      ((uint32_t)0x49)

+#define EXTI_LINE74      ((uint32_t)0x4A)

+#define EXTI_LINE75      ((uint32_t)0x4B)  /* Not available in all family lines */

+#define EXTI_LINE76      ((uint32_t)0x4C)  /* Not available in all family lines */

+#if defined(DUAL_CORE)

+#define EXTI_LINE77      ((uint32_t)0x4D)

+#define EXTI_LINE78      ((uint32_t)0x4E)

+#define EXTI_LINE79      ((uint32_t)0x4F)

+#define EXTI_LINE80      ((uint32_t)0x50)

+#else

+/* EXTI_LINE77 Reserved */

+/* EXTI_LINE78 Reserved */

+/* EXTI_LINE79 Reserved */

+/* EXTI_LINE80 Reserved */

+#endif /* DUAL_CORE */

+/* EXTI_LINE81   Reserved */

+#if defined(DUAL_CORE)

+#define EXTI_LINE82      ((uint32_t)0x52)

+#else

+/* EXTI_LINE82 Reserved */

+#endif /* DUAL_CORE */

+/* EXTI_LINE83   Reserved */

+#if defined(DUAL_CORE)

+#define EXTI_LINE84      ((uint32_t)0x54)

+#else

+/* EXTI_LINE84 Reserved */

+#endif /* DUAL_CORE */

+#define EXTI_LINE85      ((uint32_t)0x55)

+#define EXTI_LINE86      ((uint32_t)0x56)  /* Not available in all family lines */

+#define EXTI_LINE87      ((uint32_t)0x57)

+#define EXTI_LINE88      ((uint32_t)0x58)  /* Not available in all family lines */

+

+#if defined(DUAL_CORE)

+#define IS_HAL_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1) || \

+                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)   || \

+                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)   || \

+                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)   || \

+                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)   || \

+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11)  || \

+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13)  || \

+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15)  || \

+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17)  || \

+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19)  || \

+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21)  || \

+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51)  || \

+                                ((LINE) == EXTI_LINE82) || ((LINE) == EXTI_LINE84)  || \

+                                ((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86))

+#else

+#define IS_HAL_EXTI_CONFIG_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)|| \

+                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)   || \

+                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)   || \

+                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)   || \

+                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)   || \

+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \

+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \

+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \

+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \

+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \

+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \

+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE51) || \

+                                ((LINE) == EXTI_LINE85) || ((LINE) == EXTI_LINE86))

+#endif /* DUAL_CORE */

+

+#if defined(DUAL_CORE)

+#define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)  || \

+                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)  || \

+                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)  || \

+                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)  || \

+                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)  || \

+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \

+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \

+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \

+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \

+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \

+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \

+                                ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \

+                                ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \

+                                ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \

+                                ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \

+                                ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \

+                                ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \

+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \

+                                ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \

+                                ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \

+                                ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \

+                                ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \

+                                ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \

+                                ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \

+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \

+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \

+                                ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \

+                                ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \

+                                ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \

+                                ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \

+                                ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \

+                                ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \

+                                ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \

+                                ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \

+                                ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \

+                                ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \

+                                ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \

+                                ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \

+                                ((LINE) == EXTI_LINE77) || ((LINE) == EXTI_LINE79) || \

+                                ((LINE) == EXTI_LINE84) || ((LINE) == EXTI_LINE85) || \

+                                ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \

+                                ((LINE) == EXTI_LINE78) || \

+                                ((LINE) == EXTI_LINE80) || ((LINE) == EXTI_LINE82))

+#else

+#define IS_EXTI_ALL_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)  || \

+                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)  || \

+                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)  || \

+                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)  || \

+                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)  || \

+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \

+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \

+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \

+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \

+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \

+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \

+                                ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \

+                                ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \

+                                ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \

+                                ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \

+                                ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \

+                                ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \

+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \

+                                ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \

+                                ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \

+                                ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \

+                                ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \

+                                ((LINE) == EXTI_LINE44) || \

+                                ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \

+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \

+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \

+                                ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \

+                                ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \

+                                ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \

+                                ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \

+                                ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \

+                                ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \

+                                ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \

+                                ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \

+                                ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \

+                                ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \

+                                ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \

+                                ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \

+                                ((LINE) == EXTI_LINE85) || \

+                                ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \

+                                ((LINE) == EXTI_LINE88))

+#endif /*DUAL_CORE*/

+

+#if defined(DUAL_CORE)

+#define IS_EXTI_D1_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)  || \

+                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)  || \

+                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)  || \

+                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)  || \

+                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)  || \

+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \

+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \

+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \

+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \

+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \

+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \

+                                ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \

+                                ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \

+                                ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \

+                                ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \

+                                ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \

+                                ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \

+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \

+                                ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \

+                                ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \

+                                ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \

+                                ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \

+                                ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \

+                                ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \

+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \

+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \

+                                ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \

+                                ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \

+                                ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \

+                                ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \

+                                ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \

+                                ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \

+                                ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \

+                                ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \

+                                ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \

+                                ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \

+                                ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \

+                                ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \

+                                ((LINE) == EXTI_LINE77) || ((LINE) == EXTI_LINE79) || \

+                                ((LINE) == EXTI_LINE84) || ((LINE) == EXTI_LINE85) || \

+                                ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))

+#else

+#define IS_EXTI_D1_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)  || \

+                                ((LINE) == EXTI_LINE2)  || ((LINE) == EXTI_LINE3)  || \

+                                ((LINE) == EXTI_LINE4)  || ((LINE) == EXTI_LINE5)  || \

+                                ((LINE) == EXTI_LINE6)  || ((LINE) == EXTI_LINE7)  || \

+                                ((LINE) == EXTI_LINE8)  || ((LINE) == EXTI_LINE9)  || \

+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \

+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \

+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \

+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \

+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \

+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \

+                                ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \

+                                ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \

+                                ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \

+                                ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \

+                                ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \

+                                ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \

+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \

+                                ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \

+                                ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \

+                                ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \

+                                ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \

+                                ((LINE) == EXTI_LINE44) || \

+                                ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \

+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \

+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \

+                                ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \

+                                ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \

+                                ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \

+                                ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \

+                                ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \

+                                ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \

+                                ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \

+                                ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \

+                                ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \

+                                ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \

+                                ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \

+                                ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \

+                                ((LINE) == EXTI_LINE85) || \

+                                ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87) || \

+                                ((LINE) == EXTI_LINE88))

+#endif /*DUAL_CORE*/

+

+#if defined(DUAL_CORE)

+#define IS_EXTI_D2_LINE(LINE) (((LINE) == EXTI_LINE0)  || ((LINE) == EXTI_LINE1)    || \

+                                ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3)   || \

+                                ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5)   || \

+                                ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7)   || \

+                                ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9)   || \

+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \

+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \

+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \

+                                ((LINE) == EXTI_LINE16) || ((LINE) == EXTI_LINE17) || \

+                                ((LINE) == EXTI_LINE18) || ((LINE) == EXTI_LINE19) || \

+                                ((LINE) == EXTI_LINE20) || ((LINE) == EXTI_LINE21) || \

+                                ((LINE) == EXTI_LINE22) || ((LINE) == EXTI_LINE23) || \

+                                ((LINE) == EXTI_LINE24) || ((LINE) == EXTI_LINE25) || \

+                                ((LINE) == EXTI_LINE26) || ((LINE) == EXTI_LINE27) || \

+                                ((LINE) == EXTI_LINE28) || ((LINE) == EXTI_LINE29) || \

+                                ((LINE) == EXTI_LINE30) || ((LINE) == EXTI_LINE31) || \

+                                ((LINE) == EXTI_LINE32) || ((LINE) == EXTI_LINE33) || \

+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \

+                                ((LINE) == EXTI_LINE36) || ((LINE) == EXTI_LINE37) || \

+                                ((LINE) == EXTI_LINE38) || ((LINE) == EXTI_LINE39) || \

+                                ((LINE) == EXTI_LINE40) || ((LINE) == EXTI_LINE41) || \

+                                ((LINE) == EXTI_LINE42) || ((LINE) == EXTI_LINE43) || \

+                                ((LINE) == EXTI_LINE44) || ((LINE) == EXTI_LINE46) || \

+                                ((LINE) == EXTI_LINE47) || ((LINE) == EXTI_LINE48) || \

+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \

+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \

+                                ((LINE) == EXTI_LINE53) || ((LINE) == EXTI_LINE54) || \

+                                ((LINE) == EXTI_LINE55) || ((LINE) == EXTI_LINE56) || \

+                                ((LINE) == EXTI_LINE57) || ((LINE) == EXTI_LINE58) || \

+                                ((LINE) == EXTI_LINE59) || ((LINE) == EXTI_LINE60) || \

+                                ((LINE) == EXTI_LINE61) || ((LINE) == EXTI_LINE62) || \

+                                ((LINE) == EXTI_LINE63) || ((LINE) == EXTI_LINE64) || \

+                                ((LINE) == EXTI_LINE65) || ((LINE) == EXTI_LINE66) || \

+                                ((LINE) == EXTI_LINE67) || ((LINE) == EXTI_LINE68) || \

+                                ((LINE) == EXTI_LINE69) || ((LINE) == EXTI_LINE70) || \

+                                ((LINE) == EXTI_LINE71) || ((LINE) == EXTI_LINE72) || \

+                                ((LINE) == EXTI_LINE73) || ((LINE) == EXTI_LINE74) || \

+                                ((LINE) == EXTI_LINE75) || ((LINE) == EXTI_LINE76) || \

+                                ((LINE) == EXTI_LINE78) || ((LINE) == EXTI_LINE80) || \

+                                ((LINE) == EXTI_LINE82) || ((LINE) == EXTI_LINE85) || \

+                                ((LINE) == EXTI_LINE86) || ((LINE) == EXTI_LINE87))

+#endif /*DUAL_CORE*/

+

+#if defined(DUAL_CORE)

+#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)    || \

+                                ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3)   || \

+                                ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5)   || \

+                                ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7)   || \

+                                ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9)   || \

+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \

+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \

+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \

+                                ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \

+                                ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \

+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \

+                                ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \

+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \

+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \

+                                ((LINE) == EXTI_LINE53))

+#elif (POWER_DOMAINS_NUMBER == 3U)

+#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)    || \

+                                ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3)   || \

+                                ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5)   || \

+                                ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7)   || \

+                                ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9)   || \

+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \

+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \

+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \

+                                ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \

+                                ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \

+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \

+                                ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \

+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \

+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE52) || \

+                                ((LINE) == EXTI_LINE53))

+#else

+#define IS_EXTI_D3_LINE(LINE) (((LINE) == EXTI_LINE0) || ((LINE) == EXTI_LINE1)    || \

+                                ((LINE) == EXTI_LINE2) || ((LINE) == EXTI_LINE3)   || \

+                                ((LINE) == EXTI_LINE4) || ((LINE) == EXTI_LINE5)   || \

+                                ((LINE) == EXTI_LINE6) || ((LINE) == EXTI_LINE7)   || \

+                                ((LINE) == EXTI_LINE8) || ((LINE) == EXTI_LINE9)   || \

+                                ((LINE) == EXTI_LINE10) || ((LINE) == EXTI_LINE11) || \

+                                ((LINE) == EXTI_LINE12) || ((LINE) == EXTI_LINE13) || \

+                                ((LINE) == EXTI_LINE14) || ((LINE) == EXTI_LINE15) || \

+                                ((LINE) == EXTI_LINE19) || ((LINE) == EXTI_LINE20) || \

+                                ((LINE) == EXTI_LINE21) || ((LINE) == EXTI_LINE25) || \

+                                ((LINE) == EXTI_LINE34) || ((LINE) == EXTI_LINE35) || \

+                                ((LINE) == EXTI_LINE41) || ((LINE) == EXTI_LINE48) || \

+                                ((LINE) == EXTI_LINE49) || ((LINE) == EXTI_LINE50) || \

+                                ((LINE) == EXTI_LINE51) || ((LINE) == EXTI_LINE88))

+#endif /*DUAL_CORE*/

+

+

+#define  BDMA_CH6_CLEAR           ((uint32_t)0x00000000)   /*!< BDMA ch6 event selected as D3 domain pendclear source*/

+#define  BDMA_CH7_CLEAR           ((uint32_t)0x00000001)   /*!< BDMA ch7 event selected as D3 domain pendclear source*/

+#if defined (LPTIM4)

+#define  LPTIM4_OUT_CLEAR         ((uint32_t)0x00000002)   /*!< LPTIM4 out selected as D3 domain pendclear source*/

+#else

+#define  LPTIM2_OUT_CLEAR         ((uint32_t)0x00000002)   /*!< LPTIM2 out selected as D3 domain pendclear source*/

+#endif /* LPTIM4 */

+#if defined (LPTIM5)

+#define  LPTIM5_OUT_CLEAR         ((uint32_t)0x00000003)   /*!< LPTIM5 out selected as D3 domain pendclear source*/

+#else

+#define  LPTIM3_OUT_CLEAR         ((uint32_t)0x00000003)   /*!< LPTIM3 out selected as D3 domain pendclear source*/

+#endif /* LPTIM5 */

+#if defined (LPTIM4) && defined (LPTIM5)

+#define IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR)    || \

+                                 ((SOURCE) == LPTIM4_OUT_CLEAR) || ((SOURCE) == LPTIM5_OUT_CLEAR))

+#else

+#define IS_EXTI_D3_CLEAR(SOURCE) (((SOURCE) == BDMA_CH6_CLEAR) || ((SOURCE) == BDMA_CH7_CLEAR)    || \

+                                 ((SOURCE) == LPTIM2_OUT_CLEAR) || ((SOURCE) == LPTIM3_OUT_CLEAR))

+#endif /* LPTIM4 LPTIM5 */

+/**

+  * @}

+  */

+

+

+/** @defgroup FMC_SwapBankMapping_Config  SwapBankMapping Config

+  * @{

+  */

+#define FMC_SWAPBMAP_DISABLE             (0x00000000U)

+#define FMC_SWAPBMAP_SDRAM_SRAM          FMC_BCR1_BMAP_0

+#define FMC_SWAPBMAP_SDRAMB2             FMC_BCR1_BMAP_1

+

+#define IS_FMC_SWAPBMAP_MODE(__MODE__) (((__MODE__) == FMC_SWAPBMAP_DISABLE)    || \

+                                        ((__MODE__) == FMC_SWAPBMAP_SDRAM_SRAM) || \

+                                        ((__MODE__) == FMC_SWAPBMAP_SDRAMB2))

+/**

+  * @}

+  */

+

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup ART_Exported_Macros ART Exported Macros

+  * @{

+  */

+#if defined(DUAL_CORE)

+

+/** @brief  ART Enable Macro.

+  *         Enable the Cortex-M4 ART cache.

+  */

+#define __HAL_ART_ENABLE()   SET_BIT(ART->CTR, ART_CTR_EN)

+

+/** @brief  ART Disable Macro.

+  *         Disable the Cortex-M4 ART cache.

+  */

+#define __HAL_ART_DISABLE()   CLEAR_BIT(ART->CTR, ART_CTR_EN)

+

+/** @brief  ART Cache BaseAddress Config.

+  *         Configure the Cortex-M4 ART cache Base Address.

+  */

+#define __HAL_ART_CONFIG_BASE_ADDRESS(__BASE_ADDRESS__)   MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((__BASE_ADDRESS__) >> 12U) & 0x000FFF00UL))

+

+#endif /* DUAL_CORE */

+/**

+  * @}

+  */

+

+/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros

+  * @{

+  */

+

+/** @brief  SYSCFG Break AXIRAM double ECC lock.

+  *         Enable and lock the connection of AXIRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.

+  * @note   The selected configuration is locked and can be unlocked only by system reset.

+            This feature is available on STM32H7 rev.B and above.

+  */

+#define __HAL_SYSCFG_BREAK_AXISRAM_DBL_ECC_LOCK()     SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML)

+

+/** @brief  SYSCFG Break ITCM double ECC lock.

+  *         Enable and lock the connection of ITCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.

+  * @note   The selected configuration is locked and can be unlocked only by system reset.

+            This feature is available on STM32H7 rev.B and above.

+  */

+#define __HAL_SYSCFG_BREAK_ITCM_DBL_ECC_LOCK()        SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_ITCML)

+

+/** @brief  SYSCFG Break DTCM double ECC lock.

+  *         Enable and lock the connection of DTCM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.

+  * @note   The selected configuration is locked and can be unlocked only by system reset.

+            This feature is available on STM32H7 rev.B and above.

+  */

+#define __HAL_SYSCFG_BREAK_DTCM_DBL_ECC_LOCK()        SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_DTCML)

+

+/** @brief  SYSCFG Break SRAM1 double ECC lock.

+  *         Enable and lock the connection of SRAM1 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.

+  * @note   The selected configuration is locked and can be unlocked only by system reset.

+            This feature is available on STM32H7 rev.B and above.

+  */

+#define __HAL_SYSCFG_BREAK_SRAM1_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM1L)

+

+/** @brief  SYSCFG Break SRAM2 double ECC lock.

+  *         Enable and lock the connection of SRAM2 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.

+  * @note   The selected configuration is locked and can be unlocked only by system reset.

+            This feature is available on STM32H7 rev.B and above.

+  */

+#define __HAL_SYSCFG_BREAK_SRAM2_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM2L)

+

+/** @brief  SYSCFG Break SRAM3 double ECC lock.

+  *         Enable and lock the connection of SRAM3 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.

+  * @note   The selected configuration is locked and can be unlocked only by system reset.

+            This feature is available on STM32H7 rev.B and above.

+  */

+#define __HAL_SYSCFG_BREAK_SRAM3_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM3L)

+

+/** @brief  SYSCFG Break SRAM4 double ECC lock.

+  *         Enable and lock the connection of SRAM4 double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.

+  * @note   The selected configuration is locked and can be unlocked only by system reset.

+            This feature is available on STM32H7 rev.B and above.

+  */

+#define __HAL_SYSCFG_BREAK_SRAM4_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_SRAM4L)

+

+/** @brief  SYSCFG Break Backup SRAM double ECC lock.

+  *         Enable and lock the connection of Backup SRAM double ECC error to TIM1/8/15/16/17 and HRTIMER Break input.

+  * @note   The selected configuration is locked and can be unlocked only by system reset.

+            This feature is available on STM32H7 rev.B and above.

+  */

+#define __HAL_SYSCFG_BREAK_BKRAM_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_BKRAML)

+

+/** @brief  SYSCFG Break Cortex-M7 Lockup lock.

+  *         Enable and lock the connection of Cortex-M7 LOCKUP output to TIM1/8/15/16/17 and HRTIMER Break input.

+  * @note   The selected configuration is locked and can be unlocked only by system reset.

+            This feature is available on STM32H7 rev.B and above.

+  */

+#define __HAL_SYSCFG_BREAK_CM7_LOCKUP_LOCK()          SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM7L)

+

+/** @brief  SYSCFG Break FLASH double ECC lock.

+  *         Enable and lock the connection of Flash double ECC error connection to TIM1/8/15/16/17 and HRTIMER Break input.

+  * @note   The selected configuration is locked and can be unlocked only by system reset.

+            This feature is available on STM32H7 rev.B and above.

+  */

+#define __HAL_SYSCFG_BREAK_FLASH_DBL_ECC_LOCK()       SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_FLASHL)

+

+/** @brief  SYSCFG Break PVD lock.

+  *         Enable and lock the PVD connection to Timer1/8/15/16/17 and HRTIMER Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register.

+  * @note   The selected configuration is locked and can be unlocked only by system reset.

+            This feature is available on STM32H7 rev.B and above.

+  */

+#define __HAL_SYSCFG_BREAK_PVD_LOCK()                 SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_PVDL)

+

+#if defined(DUAL_CORE)

+/** @brief  SYSCFG Break Cortex-M4 Lockup lock.

+  *         Enable and lock the connection of Cortex-M4 LOCKUP output to TIM1/8/15/16/17 and HRTIMER Break input.

+  * @note   The selected configuration is locked and can be unlocked only by system reset.

+            This feature is available on STM32H7 rev.B and above.

+  */

+#define __HAL_SYSCFG_BREAK_CM4_LOCKUP_LOCK()          SET_BIT(SYSCFG->CFGR, SYSCFG_CFGR_CM4L)

+#endif /* DUAL_CORE */

+

+#if !defined(SYSCFG_PMCR_BOOSTEN)

+/** @brief  Fast-mode Plus driving capability enable/disable macros

+  * @param __FASTMODEPLUS__  This parameter can be a value of :

+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6

+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7

+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8

+  *     @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9

+  */

+#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\

+                                                                SET_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\

+                                                               }while(0)

+

+#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\

+                                                                CLEAR_BIT(SYSCFG->PMCR, (__FASTMODEPLUS__));\

+                                                               }while(0)

+

+#endif /* !SYSCFG_PMCR_BOOSTEN */

+/**

+  * @}

+  */

+

+/** @brief  Freeze/Unfreeze Peripherals in Debug mode

+  */

+#define __HAL_DBGMCU_FREEZE_WWDG1()          (DBGMCU->APB3FZ1 |= (DBGMCU_APB3FZ1_DBG_WWDG1))

+

+#define __HAL_DBGMCU_FREEZE_TIM2()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM2))

+#define __HAL_DBGMCU_FREEZE_TIM3()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM3))

+#define __HAL_DBGMCU_FREEZE_TIM4()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM4))

+#define __HAL_DBGMCU_FREEZE_TIM5()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM5))

+#define __HAL_DBGMCU_FREEZE_TIM6()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM6))

+#define __HAL_DBGMCU_FREEZE_TIM7()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM7))

+#define __HAL_DBGMCU_FREEZE_TIM12()          (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM12))

+#define __HAL_DBGMCU_FREEZE_TIM13()          (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM13))

+#define __HAL_DBGMCU_FREEZE_TIM14()          (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_TIM14))

+#define __HAL_DBGMCU_FREEZE_LPTIM1()         (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_LPTIM1))

+#define __HAL_DBGMCU_FREEZE_I2C1()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C1))

+#define __HAL_DBGMCU_FREEZE_I2C2()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C2))

+#define __HAL_DBGMCU_FREEZE_I2C3()           (DBGMCU->APB1LFZ1 |= (DBGMCU_APB1LFZ1_DBG_I2C3))

+#define __HAL_DBGMCU_FREEZE_FDCAN()          (DBGMCU->APB1HFZ1 |= (DBGMCU_APB1HFZ1_DBG_FDCAN))

+

+

+#define __HAL_DBGMCU_FREEZE_TIM1()           (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM1))

+#define __HAL_DBGMCU_FREEZE_TIM8()           (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM8))

+#define __HAL_DBGMCU_FREEZE_TIM15()          (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM15))

+#define __HAL_DBGMCU_FREEZE_TIM16()          (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM16))

+#define __HAL_DBGMCU_FREEZE_TIM17()          (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_TIM17))

+#define __HAL_DBGMCU_FREEZE_HRTIM()          (DBGMCU->APB2FZ1 |= (DBGMCU_APB2FZ1_DBG_HRTIM))

+

+#define __HAL_DBGMCU_FREEZE_I2C4()           (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_I2C4))

+#define __HAL_DBGMCU_FREEZE_LPTIM2()         (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM2))

+#define __HAL_DBGMCU_FREEZE_LPTIM3()         (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM3))

+#define __HAL_DBGMCU_FREEZE_LPTIM4()         (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM4))

+#define __HAL_DBGMCU_FREEZE_LPTIM5()         (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_LPTIM5))

+#define __HAL_DBGMCU_FREEZE_RTC()            (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_RTC))

+#define __HAL_DBGMCU_FREEZE_IWDG1()          (DBGMCU->APB4FZ1 |= (DBGMCU_APB4FZ1_DBG_IWDG1))

+

+

+#define __HAL_DBGMCU_UnFreeze_WWDG1()          (DBGMCU->APB3FZ1  &= ~ (DBGMCU_APB3FZ1_DBG_WWDG1))

+

+#define __HAL_DBGMCU_UnFreeze_TIM2()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM2))

+#define __HAL_DBGMCU_UnFreeze_TIM3()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM3))

+#define __HAL_DBGMCU_UnFreeze_TIM4()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM4))

+#define __HAL_DBGMCU_UnFreeze_TIM5()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM5))

+#define __HAL_DBGMCU_UnFreeze_TIM6()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM6))

+#define __HAL_DBGMCU_UnFreeze_TIM7()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM7))

+#define __HAL_DBGMCU_UnFreeze_TIM12()          (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM12))

+#define __HAL_DBGMCU_UnFreeze_TIM13()          (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM13))

+#define __HAL_DBGMCU_UnFreeze_TIM14()          (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_TIM14))

+#define __HAL_DBGMCU_UnFreeze_LPTIM1()         (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_LPTIM1))

+#define __HAL_DBGMCU_UnFreeze_I2C1()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_I2C1))

+#define __HAL_DBGMCU_UnFreeze_I2C2()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_I2C2))

+#define __HAL_DBGMCU_UnFreeze_I2C3()           (DBGMCU->APB1LFZ1  &= ~ (DBGMCU_APB1LFZ1_DBG_I2C3))

+#define __HAL_DBGMCU_UnFreeze_FDCAN()          (DBGMCU->APB1HFZ1  &= ~ (DBGMCU_APB1HFZ1_DBG_FDCAN))

+

+

+#define __HAL_DBGMCU_UnFreeze_TIM1()           (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM1))

+#define __HAL_DBGMCU_UnFreeze_TIM8()           (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM8))

+#define __HAL_DBGMCU_UnFreeze_TIM15()          (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM15))

+#define __HAL_DBGMCU_UnFreeze_TIM16()          (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM16))

+#define __HAL_DBGMCU_UnFreeze_TIM17()          (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_TIM17))

+#define __HAL_DBGMCU_UnFreeze_HRTIM()          (DBGMCU->APB2FZ1  &= ~ (DBGMCU_APB2FZ1_DBG_HRTIM))

+

+#define __HAL_DBGMCU_UnFreeze_I2C4()           (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_I2C4))

+#define __HAL_DBGMCU_UnFreeze_LPTIM2()         (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM2))

+#define __HAL_DBGMCU_UnFreeze_LPTIM3()         (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM3))

+#define __HAL_DBGMCU_UnFreeze_LPTIM4()         (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM4))

+#define __HAL_DBGMCU_UnFreeze_LPTIM5()         (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_LPTIM5))

+#define __HAL_DBGMCU_UnFreeze_RTC()            (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_RTC))

+#define __HAL_DBGMCU_UnFreeze_IWDG1()          (DBGMCU->APB4FZ1  &= ~ (DBGMCU_APB4FZ1_DBG_IWDG1))

+

+

+#if defined(DUAL_CORE)

+#define __HAL_DBGMCU_FREEZE2_IWDG2()          (DBGMCU->APB4FZ2  |= (DBGMCU_APB4FZ2_DBG_IWDG2))

+#define __HAL_DBGMCU_FREEZE2_WWDG2()          (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_WWDG2))

+

+#define __HAL_DBGMCU_UnFreeze2_IWDG2()        (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_IWDG2))

+#define __HAL_DBGMCU_UnFreeze2_WWDG2()        (DBGMCU->APB1LFZ2 &= ~ (DBGMCU_APB1LFZ2_DBG_WWDG2))

+

+

+#define __HAL_DBGMCU_FREEZE2_WWDG1()          (DBGMCU->APB3FZ2 |= (DBGMCU_APB3FZ2_DBG_WWDG1))

+

+#define __HAL_DBGMCU_FREEZE2_TIM2()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM2))

+#define __HAL_DBGMCU_FREEZE2_TIM3()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM3))

+#define __HAL_DBGMCU_FREEZE2_TIM4()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM4))

+#define __HAL_DBGMCU_FREEZE2_TIM5()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM5))

+#define __HAL_DBGMCU_FREEZE2_TIM6()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM6))

+#define __HAL_DBGMCU_FREEZE2_TIM7()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM7))

+#define __HAL_DBGMCU_FREEZE2_TIM12()          (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM12))

+#define __HAL_DBGMCU_FREEZE2_TIM13()          (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM13))

+#define __HAL_DBGMCU_FREEZE2_TIM14()          (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_TIM14))

+#define __HAL_DBGMCU_FREEZE2_LPTIM1()         (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_LPTIM1))

+#define __HAL_DBGMCU_FREEZE2_I2C1()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C1))

+#define __HAL_DBGMCU_FREEZE2_I2C2()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C2))

+#define __HAL_DBGMCU_FREEZE2_I2C3()           (DBGMCU->APB1LFZ2 |= (DBGMCU_APB1LFZ2_DBG_I2C3))

+#define __HAL_DBGMCU_FREEZE2_FDCAN()          (DBGMCU->APB1HFZ2 |= (DBGMCU_APB1HFZ2_DBG_FDCAN))

+

+

+#define __HAL_DBGMCU_FREEZE2_TIM1()           (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM1))

+#define __HAL_DBGMCU_FREEZE2_TIM8()           (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM8))

+#define __HAL_DBGMCU_FREEZE2_TIM15()          (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM15))

+#define __HAL_DBGMCU_FREEZE2_TIM16()          (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM16))

+#define __HAL_DBGMCU_FREEZE2_TIM17()          (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_TIM17))

+#define __HAL_DBGMCU_FREEZE2_HRTIM()          (DBGMCU->APB2FZ2 |= (DBGMCU_APB2FZ2_DBG_HRTIM))

+

+#define __HAL_DBGMCU_FREEZE2_I2C4()           (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_I2C4))

+#define __HAL_DBGMCU_FREEZE2_LPTIM2()         (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM2))

+#define __HAL_DBGMCU_FREEZE2_LPTIM3()         (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM3))

+#define __HAL_DBGMCU_FREEZE2_LPTIM4()         (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM4))

+#define __HAL_DBGMCU_FREEZE2_LPTIM5()         (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_LPTIM5))

+#define __HAL_DBGMCU_FREEZE2_RTC()            (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_RTC))

+#define __HAL_DBGMCU_FREEZE2_IWDG1()          (DBGMCU->APB4FZ2 |= (DBGMCU_APB4FZ2_DBG_IWDG1))

+

+#define __HAL_DBGMCU_UnFreeze2_WWDG1()          (DBGMCU->APB3FZ2  &= ~ (DBGMCU_APB3FZ2_DBG_WWDG1))

+

+#define __HAL_DBGMCU_UnFreeze2_TIM2()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM2))

+#define __HAL_DBGMCU_UnFreeze2_TIM3()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM3))

+#define __HAL_DBGMCU_UnFreeze2_TIM4()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM4))

+#define __HAL_DBGMCU_UnFreeze2_TIM5()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM5))

+#define __HAL_DBGMCU_UnFreeze2_TIM6()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM6))

+#define __HAL_DBGMCU_UnFreeze2_TIM7()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM7))

+#define __HAL_DBGMCU_UnFreeze2_TIM12()          (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM12))

+#define __HAL_DBGMCU_UnFreeze2_TIM13()          (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM13))

+#define __HAL_DBGMCU_UnFreeze2_TIM14()          (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_TIM14))

+#define __HAL_DBGMCU_UnFreeze2_LPTIM1()         (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_LPTIM1))

+#define __HAL_DBGMCU_UnFreeze2_I2C1()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_I2C1))

+#define __HAL_DBGMCU_UnFreeze2_I2C2()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_I2C2))

+#define __HAL_DBGMCU_UnFreeze2_I2C3()           (DBGMCU->APB1LFZ2  &= ~ (DBGMCU_APB1LFZ2_DBG_I2C3))

+#define __HAL_DBGMCU_UnFreeze2_FDCAN()          (DBGMCU->APB1HFZ2  &= ~ (DBGMCU_APB1HFZ2_DBG_FDCAN))

+

+

+#define __HAL_DBGMCU_UnFreeze2_TIM1()           (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_TIM1))

+#define __HAL_DBGMCU_UnFreeze2_TIM8()           (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_TIM8))

+#define __HAL_DBGMCU_UnFreeze2_TIM15()          (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_TIM15))

+#define __HAL_DBGMCU_UnFreeze2_TIM16()          (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_TIM16))

+#define __HAL_DBGMCU_UnFreeze2_TIM17()          (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_TIM17))

+#define __HAL_DBGMCU_UnFreeze2_HRTIM()          (DBGMCU->APB2FZ2  &= ~ (DBGMCU_APB2FZ2_DBG_HRTIM))

+

+#define __HAL_DBGMCU_UnFreeze2_I2C4()           (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_I2C4))

+#define __HAL_DBGMCU_UnFreeze2_LPTIM2()         (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM2))

+#define __HAL_DBGMCU_UnFreeze2_LPTIM3()         (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM3))

+#define __HAL_DBGMCU_UnFreeze2_LPTIM4()         (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM4))

+#define __HAL_DBGMCU_UnFreeze2_LPTIM5()         (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_LPTIM5))

+#define __HAL_DBGMCU_UnFreeze2_RTC()            (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_RTC))

+#define __HAL_DBGMCU_UnFreeze2_IWDG1()          (DBGMCU->APB4FZ2  &= ~ (DBGMCU_APB4FZ2_DBG_IWDG1))

+

+#endif /*DUAL_CORE*/

+

+/** @defgroup HAL_Private_Macros HAL Private Macros

+  * @{

+  */

+#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ)  || \

+                           ((FREQ) == HAL_TICK_FREQ_100HZ) || \

+                           ((FREQ) == HAL_TICK_FREQ_1KHZ))

+/**

+  * @}

+  */

+

+/* Exported variables --------------------------------------------------------*/

+

+/** @addtogroup HAL_Exported_Variables

+  * @{

+  */

+extern __IO uint32_t uwTick;

+extern uint32_t uwTickPrio;

+extern HAL_TickFreqTypeDef uwTickFreq;

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+

+/* Initialization and de-initialization functions  ******************************/

+HAL_StatusTypeDef HAL_Init(void);

+HAL_StatusTypeDef HAL_DeInit(void);

+void HAL_MspInit(void);

+void HAL_MspDeInit(void);

+HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);

+

+/* Peripheral Control functions  ************************************************/

+void HAL_IncTick(void);

+void HAL_Delay(uint32_t Delay);

+uint32_t HAL_GetTick(void);

+uint32_t HAL_GetTickPrio(void);

+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);

+HAL_TickFreqTypeDef HAL_GetTickFreq(void);

+void HAL_SuspendTick(void);

+void HAL_ResumeTick(void);

+uint32_t HAL_GetHalVersion(void);

+uint32_t HAL_GetREVID(void);

+uint32_t HAL_GetDEVID(void);

+uint32_t HAL_GetUIDw0(void);

+uint32_t HAL_GetUIDw1(void);

+uint32_t HAL_GetUIDw2(void);

+#if defined(SYSCFG_PMCR_EPIS_SEL)

+void HAL_SYSCFG_ETHInterfaceSelect(uint32_t SYSCFG_ETHInterface);

+#endif /* SYSCFG_PMCR_EPIS_SEL */

+void HAL_SYSCFG_AnalogSwitchConfig(uint32_t SYSCFG_AnalogSwitch , uint32_t SYSCFG_SwitchState );

+#if defined(SYSCFG_PMCR_BOOSTEN)

+void HAL_SYSCFG_EnableBOOST(void);

+void HAL_SYSCFG_DisableBOOST(void);

+#endif /* SYSCFG_PMCR_BOOSTEN */

+

+#if defined (SYSCFG_UR2_BOOT_ADD0) ||  defined (SYSCFG_UR2_BCM7_ADD0)

+void HAL_SYSCFG_CM7BootAddConfig(uint32_t BootRegister, uint32_t BootAddress);

+#endif /* SYSCFG_UR2_BOOT_ADD0 || SYSCFG_UR2_BCM7_ADD0*/

+

+#if defined(DUAL_CORE)

+void HAL_SYSCFG_CM4BootAddConfig(uint32_t BootRegister, uint32_t BootAddress);

+void HAL_SYSCFG_EnableCM7BOOT(void);

+void HAL_SYSCFG_DisableCM7BOOT(void);

+void HAL_SYSCFG_EnableCM4BOOT(void);

+void HAL_SYSCFG_DisableCM4BOOT(void);

+#endif /*DUAL_CORE*/

+void HAL_EnableCompensationCell(void);

+void HAL_DisableCompensationCell(void);

+void HAL_SYSCFG_EnableIOSpeedOptimize(void);

+void HAL_SYSCFG_DisableIOSpeedOptimize(void);

+void HAL_SYSCFG_CompensationCodeSelect(uint32_t SYSCFG_CompCode);

+void HAL_SYSCFG_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode);

+#if defined(SYSCFG_CCCR_NCC_MMC)

+void HAL_SYSCFG_VDDMMC_CompensationCodeConfig(uint32_t SYSCFG_PMOSCode, uint32_t SYSCFG_NMOSCode);

+#endif /* SYSCFG_CCCR_NCC_MMC */

+void HAL_EnableDBGSleepMode(void);

+void HAL_DisableDBGSleepMode(void);

+void HAL_EnableDBGStopMode(void);

+void HAL_DisableDBGStopMode(void);

+void HAL_EnableDBGStandbyMode(void);

+void HAL_DisableDBGStandbyMode(void);

+#if defined(DUAL_CORE)

+void HAL_EnableDomain2DBGSleepMode(void);

+void HAL_DisableDomain2DBGSleepMode(void);

+void HAL_EnableDomain2DBGStopMode(void);

+void HAL_DisableDomain2DBGStopMode(void);

+void HAL_EnableDomain2DBGStandbyMode(void);

+void HAL_DisableDomain2DBGStandbyMode(void);

+#endif /*DUAL_CORE*/

+void HAL_EnableDomain3DBGStopMode(void);

+void HAL_DisableDomain3DBGStopMode(void);

+void HAL_EnableDomain3DBGStandbyMode(void);

+void HAL_DisableDomain3DBGStandbyMode(void);

+void HAL_EXTI_EdgeConfig(uint32_t EXTI_Line , uint32_t EXTI_Edge );

+void HAL_EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);

+#if defined(DUAL_CORE)

+void HAL_EXTI_D2_ClearFlag(uint32_t EXTI_Line);

+#endif /*DUAL_CORE*/

+void HAL_EXTI_D1_ClearFlag(uint32_t EXTI_Line);

+void HAL_EXTI_D1_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode,  uint32_t EXTI_LineCmd);

+#if defined(DUAL_CORE)

+void HAL_EXTI_D2_EventInputConfig(uint32_t EXTI_Line , uint32_t EXTI_Mode,  uint32_t EXTI_LineCmd);

+#endif /*DUAL_CORE*/

+void HAL_EXTI_D3_EventInputConfig(uint32_t EXTI_Line, uint32_t EXTI_LineCmd , uint32_t EXTI_ClearSrc);

+void HAL_SetFMCMemorySwappingConfig(uint32_t BankMapConfig);

+uint32_t HAL_GetFMCMemorySwappingConfig(void);

+void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);

+void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);

+void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);

+HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);

+void HAL_SYSCFG_DisableVREFBUF(void);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_adc.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_adc.h
new file mode 100644
index 0000000000..0752dc9ffa
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_adc.h
@@ -0,0 +1,1817 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_adc.h

+  * @author  MCD Application Team

+  * @brief   Header file of ADC HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_ADC_H

+#define STM32H7xx_HAL_ADC_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/* Include low level driver */

+#include "stm32h7xx_ll_adc.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup ADC

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup ADC_Exported_Types ADC Exported Types

+  * @{

+  */

+

+/**

+  * @brief  ADC group regular oversampling structure definition

+  */

+typedef struct

+{

+  uint32_t Ratio;                         /*!< Configures the oversampling ratio.

+                                               This parameter can be a value between 1 and 1024 */

+

+  uint32_t RightBitShift;                 /*!< Configures the division coefficient for the Oversampler.

+                                               This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */

+

+  uint32_t TriggeredMode;                 /*!< Selects the regular triggered oversampling mode.

+                                               This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */

+

+  uint32_t OversamplingStopReset;         /*!< Selects the regular oversampling mode.

+                                               The oversampling is either temporary stopped or reset upon an injected

+                                               sequence interruption.

+                                               If oversampling is enabled on both regular and injected groups, this parameter

+                                               is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE"

+                                               (the oversampling buffer is zeroed during injection sequence).

+                                               This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */

+

+} ADC_OversamplingTypeDef;

+

+/**

+  * @brief  Structure definition of ADC instance and ADC group regular.

+  * @note   Parameters of this structure are shared within 2 scopes:

+  *          - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign,

+  *            ScanConvMode, EOCSelection, LowPowerAutoWait.

+  *          - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion,

+  *            ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling.

+  * @note   The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state.

+  *         ADC state can be either:

+  *          - For all parameters: ADC disabled

+  *          - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular.

+  *          - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected.

+  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed

+  *         without error reporting (as it can be the expected behavior in case of intended action to update another parameter

+  *         (which fulfills the ADC state condition) on the fly).

+  */

+typedef struct

+{

+  uint32_t ClockPrescaler;        /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler.

+                                       This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE.

+                                       Note: The ADC clock configuration is common to all ADC instances.

+                                       Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits,

+                                             AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.

+                                       Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only

+                                             if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC

+                                             must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details.

+                                       Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level.

+                                       Note: This parameter can be modified only if all ADC instances are disabled. */

+

+  uint32_t Resolution;            /*!< Configure the ADC resolution.

+                                       This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */

+

+  uint32_t ScanConvMode;          /*!< Configure the sequencer of ADC groups regular and injected.

+                                       This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.

+                                       If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).

+                                                    Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).

+                                       If enabled:  Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer).

+                                                    Scan direction is upward: from rank 1 to rank 'n'.

+                                       This parameter can be a value of @ref ADC_Scan_mode */

+

+  uint32_t EOCSelection;          /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions.

+                                       This parameter can be a value of @ref ADC_EOCSelection. */

+

+  FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous

+                                       conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software,

+                                       using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue().

+                                       This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun

+                                       for low frequency applications.

+                                       This parameter can be set to ENABLE or DISABLE.

+                                       Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag

+                                             to free the IRQ vector sequencer.

+                                             Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed:

+                                             use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start.

+                                             (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */

+

+  FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular,

+                                       after the first ADC conversion start trigger occurred (software start or external trigger).

+                                       This parameter can be set to ENABLE or DISABLE. */

+

+  uint32_t NbrOfConversion;       /*!< Specify the number of ranks that will be converted within the regular group sequencer.

+                                       To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.

+                                       This parameter must be a number between Min_Data = 1 and Max_Data = 16.

+                                       Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without

+                                       continuous mode or external trigger that could launch a conversion). */

+

+  FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence

+                                       (main sequence subdivided in successive parts).

+                                       Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.

+                                       Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.

+                                       This parameter can be set to ENABLE or DISABLE. */

+

+  uint32_t NbrOfDiscConversion;   /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided.

+                                       If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.

+                                       This parameter must be a number between Min_Data = 1 and Max_Data = 8. */

+

+  uint32_t ExternalTrigConv;      /*!< Select the external event source used to trigger ADC group regular conversion start.

+                                       If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.

+                                       This parameter can be a value of @ref ADC_regular_external_trigger_source.

+                                       Caution: external trigger source is common to all ADC instances. */

+

+  uint32_t ExternalTrigConvEdge;  /*!< Select the external event edge used to trigger ADC group regular conversion start.

+                                       If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.

+                                       This parameter can be a value of @ref ADC_regular_external_trigger_edge */

+

+  uint32_t ConversionDataManagement; /*!< Specifies whether the Data conversion data is managed: using the DMA (oneshot or circular), or stored in the DR register or transfered to DFSDM register.

+                                       Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.

+                                       This parameter can be a value of @ref ADC_ConversionDataManagement.

+                                       Note: This parameter must be modified when no conversion is on going on both regular and injected groups

+                                       (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion). */

+

+  uint32_t Overrun;               /*!< Select the behavior in case of overrun: data overwritten or preserved (default).

+                                       This parameter applies to ADC group regular only.

+                                       This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR.

+                                       Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear

+                                       end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function

+                                       HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear).

+                                       Note: Error reporting with respect to the conversion mode:

+                                             - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data

+                                               overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.

+                                             - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */

+

+  uint32_t LeftBitShift;             /*!< Configures the left shifting applied to the final result with or without oversampling.

+                                          This parameter can be a value of @ref ADCEx_Left_Bit_Shift */

+  FunctionalState OversamplingMode;       /*!< Specify whether the oversampling feature is enabled or disabled.

+                                               This parameter can be set to ENABLE or DISABLE.

+                                               Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */

+

+  ADC_OversamplingTypeDef Oversampling;   /*!< Specify the Oversampling parameters.

+                                               Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */

+

+} ADC_InitTypeDef;

+

+/**

+  * @brief  Structure definition of ADC channel for regular group

+  * @note   The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state.

+  *         ADC state can be either:

+  *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff')

+  *          - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group.

+  *          - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups.

+  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed

+  *         without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition)

+  *         on the fly).

+  */

+typedef struct

+{

+  uint32_t Channel;                /*!< Specify the channel to configure into ADC regular group.

+                                        This parameter can be a value of @ref ADC_HAL_EC_CHANNEL

+                                        Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */

+

+  uint32_t Rank;                   /*!< Specify the rank in the regular group sequencer.

+                                        This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS

+                                        Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by

+                                        the new channel setting (or parameter number of conversions adjusted) */

+

+  uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.

+                                        Unit: ADC clock cycles

+                                        Conversion time is the addition of sampling time and processing time

+                                        (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).

+                                        This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME

+                                        Caution: This parameter applies to a channel that can be used into regular and/or injected group.

+                                                 It overwrites the last setting.

+                                        Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),

+                                              sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)

+                                              Refer to device datasheet for timings values. */

+

+  uint32_t SingleDiff;             /*!< Select single-ended or differential input.

+                                        In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input).

+                                                              Only channel 'i' has to be configured, channel 'i+1' is configured automatically.

+                                        This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING

+                                        Caution: This parameter applies to a channel that can be used in a regular and/or injected group.

+                                                 It overwrites the last setting.

+                                        Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.

+                                        Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.

+                                        Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).

+                                              If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case

+                                        of another parameter update on the fly) */

+

+  uint32_t OffsetNumber;           /*!< Select the offset number

+                                        This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB

+                                        Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */

+

+  uint32_t Offset;                 /*!< Define the offset to be subtracted from the raw converted data.

+                                        Offset value must be a positive number.

+                                        Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF,

+                                        0x3FFF, 0xFFF, 0x3FF or 0xFF respectively.

+                                        Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled

+                                              without continuous mode or external trigger that could launch a conversion). */

+

+  FunctionalState OffsetRightShift;   /*!< Define the Right-shift data after Offset correction.

+                                        This parameter is applied only for 16-bit or 8-bit resolution.

+                                        This parameter can be set to ENABLE or DISABLE.*/

+

+  FunctionalState OffsetSignedSaturation; /*!< Specify whether the Signed saturation feature is used or not.

+                                             This parameter is applied only for 16-bit or 8-bit resolution.

+                                             This parameter can be set to ENABLE or DISABLE. */

+

+} ADC_ChannelConfTypeDef;

+

+/**

+  * @brief  Structure definition of ADC analog watchdog

+  * @note   The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state.

+  *         ADC state can be either:

+  *          - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected.

+  */

+typedef struct

+{

+  uint32_t WatchdogNumber;    /*!< Select which ADC analog watchdog is monitoring the selected channel.

+                                   For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode')

+                                   For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel)

+                                   This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */

+

+  uint32_t WatchdogMode;      /*!< Configure the ADC analog watchdog mode: single/all/none channels.

+                                   For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected.

+                                   For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel.

+                                   This parameter can be a value of @ref ADC_analog_watchdog_mode. */

+

+  uint32_t Channel;           /*!< Select which ADC channel to monitor by analog watchdog.

+                                   For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored).

+                                   For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE').

+                                   This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */

+

+  FunctionalState ITMode;     /*!< Specify whether the analog watchdog is configured in interrupt or polling mode.

+                                   This parameter can be set to ENABLE or DISABLE */

+

+  uint32_t HighThreshold;     /*!< Configure the ADC analog watchdog High threshold value.

+                                   Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number

+                                   between Min_Data = 0x000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively.

+                                   Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits

+                                         the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.

+                                   Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are

+                                         impacted: the comparison of analog watchdog thresholds is done

+                                         on oversampling intermediate computation (after ratio, before shift

+                                         application): intermediate register bitfield [32:7] (26 most significant bits). */

+

+  uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog Low threshold value.

+                                   Depending of ADC resolution selected (16, 14, 12, 10, 8 bits), this parameter must be a number

+                                   between Min_Data = 0x000 and Max_Data = 0xFFFF, 0x3FFF, 0xFFF, 0x3FF or 0xFF respectively.

+                                   Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits

+                                         the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.

+                                   Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are

+                                         impacted: the comparison of analog watchdog thresholds is done

+                                         on oversampling intermediate computation (after ratio, before shift

+                                         application): intermediate register bitfield [32:7] (26 most significant bits). */

+} ADC_AnalogWDGConfTypeDef;

+

+/**

+  * @brief  ADC group injected contexts queue configuration

+  * @note   Structure intended to be used only through structure "ADC_HandleTypeDef"

+  */

+typedef struct

+{

+  uint32_t ContextQueue;                 /*!< Injected channel configuration context: build-up over each

+                                              HAL_ADCEx_InjectedConfigChannel() call to finally initialize

+                                              JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */

+

+  uint32_t ChannelCount;                 /*!< Number of channels in the injected sequence */

+} ADC_InjectionConfigTypeDef;

+

+/** @defgroup ADC_States ADC States

+  * @{

+  */

+

+/**

+  * @brief  HAL ADC state machine: ADC states definition (bitfields)

+  * @note   ADC state machine is managed by bitfields, state must be compared

+  *         with bit by bit.

+  *         For example:

+  *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "

+  *           " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "

+  */

+/* States of ADC global scope */

+#define HAL_ADC_STATE_RESET             (0x00000000UL)   /*!< ADC not yet initialized or disabled */

+#define HAL_ADC_STATE_READY             (0x00000001UL)   /*!< ADC peripheral ready for use */

+#define HAL_ADC_STATE_BUSY_INTERNAL     (0x00000002UL)   /*!< ADC is busy due to an internal process (initialization, calibration) */

+#define HAL_ADC_STATE_TIMEOUT           (0x00000004UL)   /*!< TimeOut occurrence */

+

+/* States of ADC errors */

+#define HAL_ADC_STATE_ERROR_INTERNAL    (0x00000010UL)   /*!< Internal error occurrence */

+#define HAL_ADC_STATE_ERROR_CONFIG      (0x00000020UL)   /*!< Configuration error occurrence */

+#define HAL_ADC_STATE_ERROR_DMA         (0x00000040UL)   /*!< DMA error occurrence */

+

+/* States of ADC group regular */

+#define HAL_ADC_STATE_REG_BUSY          (0x00000100UL)   /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode,

+                                                              external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */

+#define HAL_ADC_STATE_REG_EOC           (0x00000200UL)   /*!< Conversion data available on group regular */

+#define HAL_ADC_STATE_REG_OVR           (0x00000400UL)   /*!< Overrun occurrence */

+#define HAL_ADC_STATE_REG_EOSMP         (0x00000800UL)   /*!< Not available on this STM32 serie: End Of Sampling flag raised  */

+

+/* States of ADC group injected */

+#define HAL_ADC_STATE_INJ_BUSY          (0x00001000UL)   /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode,

+                                                              external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */

+#define HAL_ADC_STATE_INJ_EOC           (0x00002000UL)   /*!< Conversion data available on group injected */

+#define HAL_ADC_STATE_INJ_JQOVF         (0x00004000UL)   /*!< Injected queue overflow occurrence */

+

+/* States of ADC analog watchdogs */

+#define HAL_ADC_STATE_AWD1              (0x00010000UL)   /*!< Out-of-window occurrence of ADC analog watchdog 1 */

+#define HAL_ADC_STATE_AWD2              (0x00020000UL)   /*!< Out-of-window occurrence of ADC analog watchdog 2 */

+#define HAL_ADC_STATE_AWD3              (0x00040000UL)   /*!< Out-of-window occurrence of ADC analog watchdog 3 */

+

+/* States of ADC multi-mode */

+#define HAL_ADC_STATE_MULTIMODE_SLAVE   (0x00100000UL)   /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */

+

+/**

+  * @}

+  */

+

+/**

+  * @brief  ADC handle Structure definition

+  */

+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)

+typedef struct __ADC_HandleTypeDef

+#else

+typedef struct

+#endif

+{

+  ADC_TypeDef                   *Instance;              /*!< Register base address */

+  ADC_InitTypeDef               Init;                   /*!< ADC initialization parameters and regular conversions setting */

+  DMA_HandleTypeDef             *DMA_Handle;            /*!< Pointer DMA Handler */

+  HAL_LockTypeDef               Lock;                   /*!< ADC locking object */

+  __IO uint32_t                 State;                  /*!< ADC communication state (bitmap of ADC states) */

+  __IO uint32_t                 ErrorCode;              /*!< ADC Error code */

+  ADC_InjectionConfigTypeDef    InjectionConfig ;       /*!< ADC injected channel configuration build-up structure */

+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)

+  void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);              /*!< ADC conversion complete callback */

+  void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc);          /*!< ADC conversion DMA half-transfer callback */

+  void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc);      /*!< ADC analog watchdog 1 callback */

+  void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc);                 /*!< ADC error callback */

+  void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc);      /*!< ADC group injected conversion complete callback */

+  void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue overflow callback */

+  void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc);     /*!< ADC analog watchdog 2 callback */

+  void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc);     /*!< ADC analog watchdog 3 callback */

+  void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc);         /*!< ADC end of sampling callback */

+  void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc);               /*!< ADC Msp Init callback */

+  void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc);             /*!< ADC Msp DeInit callback */

+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */

+} ADC_HandleTypeDef;

+

+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  HAL ADC Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_ADC_CONVERSION_COMPLETE_CB_ID     = 0x00U,  /*!< ADC conversion complete callback ID */

+  HAL_ADC_CONVERSION_HALF_CB_ID         = 0x01U,  /*!< ADC conversion DMA half-transfer callback ID */

+  HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID   = 0x02U,  /*!< ADC analog watchdog 1 callback ID */

+  HAL_ADC_ERROR_CB_ID                   = 0x03U,  /*!< ADC error callback ID */

+  HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U,  /*!< ADC group injected conversion complete callback ID */

+  HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID       = 0x05U,  /*!< ADC group injected context queue overflow callback ID */

+  HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID   = 0x06U,  /*!< ADC analog watchdog 2 callback ID */

+  HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID   = 0x07U,  /*!< ADC analog watchdog 3 callback ID */

+  HAL_ADC_END_OF_SAMPLING_CB_ID         = 0x08U,  /*!< ADC end of sampling callback ID */

+  HAL_ADC_MSPINIT_CB_ID                 = 0x09U,  /*!< ADC Msp Init callback ID          */

+  HAL_ADC_MSPDEINIT_CB_ID               = 0x0AU   /*!< ADC Msp DeInit callback ID        */

+} HAL_ADC_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL ADC Callback pointer definition

+  */

+typedef  void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */

+

+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+

+/* Exported constants --------------------------------------------------------*/

+

+/** @defgroup ADC_Exported_Constants ADC Exported Constants

+  * @{

+  */

+

+/** @defgroup ADC_Error_Code ADC Error Code

+  * @{

+  */

+#define HAL_ADC_ERROR_NONE              (0x00U)   /*!< No error                                    */

+#define HAL_ADC_ERROR_INTERNAL          (0x01U)   /*!< ADC peripheral internal error (problem of clocking,

+                                                       enable/disable, erroneous state, ...)       */

+#define HAL_ADC_ERROR_OVR               (0x02U)   /*!< Overrun error                               */

+#define HAL_ADC_ERROR_DMA               (0x04U)   /*!< DMA transfer error                          */

+#define HAL_ADC_ERROR_JQOVF             (0x08U)   /*!< Injected context queue overflow error       */

+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)

+#define HAL_ADC_ERROR_INVALID_CALLBACK  (0x10U)   /*!< Invalid Callback error */

+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source

+  * @{

+  */

+#define ADC_CLOCK_SYNC_PCLK_DIV1           (LL_ADC_CLOCK_SYNC_PCLK_DIV1)  /*!< ADC synchronous clock derived from AHB clock without prescaler */

+#define ADC_CLOCK_SYNC_PCLK_DIV2           (LL_ADC_CLOCK_SYNC_PCLK_DIV2)  /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */

+#define ADC_CLOCK_SYNC_PCLK_DIV4           (LL_ADC_CLOCK_SYNC_PCLK_DIV4)  /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */

+

+#define ADC_CLOCK_ASYNC_DIV1               (LL_ADC_CLOCK_ASYNC_DIV1)      /*!< ADC asynchronous clock without prescaler */

+#define ADC_CLOCK_ASYNC_DIV2               (LL_ADC_CLOCK_ASYNC_DIV2)      /*!< ADC asynchronous clock with prescaler division by 2   */

+#define ADC_CLOCK_ASYNC_DIV4               (LL_ADC_CLOCK_ASYNC_DIV4)      /*!< ADC asynchronous clock with prescaler division by 4   */

+#define ADC_CLOCK_ASYNC_DIV6               (LL_ADC_CLOCK_ASYNC_DIV6)      /*!< ADC asynchronous clock with prescaler division by 6   */

+#define ADC_CLOCK_ASYNC_DIV8               (LL_ADC_CLOCK_ASYNC_DIV8)      /*!< ADC asynchronous clock with prescaler division by 8   */

+#define ADC_CLOCK_ASYNC_DIV10              (LL_ADC_CLOCK_ASYNC_DIV10)     /*!< ADC asynchronous clock with prescaler division by 10  */

+#define ADC_CLOCK_ASYNC_DIV12              (LL_ADC_CLOCK_ASYNC_DIV12)     /*!< ADC asynchronous clock with prescaler division by 12  */

+#define ADC_CLOCK_ASYNC_DIV16              (LL_ADC_CLOCK_ASYNC_DIV16)     /*!< ADC asynchronous clock with prescaler division by 16  */

+#define ADC_CLOCK_ASYNC_DIV32              (LL_ADC_CLOCK_ASYNC_DIV32)     /*!< ADC asynchronous clock with prescaler division by 32  */

+#define ADC_CLOCK_ASYNC_DIV64              (LL_ADC_CLOCK_ASYNC_DIV64)     /*!< ADC asynchronous clock with prescaler division by 64  */

+#define ADC_CLOCK_ASYNC_DIV128             (LL_ADC_CLOCK_ASYNC_DIV128)    /*!< ADC asynchronous clock with prescaler division by 128 */

+#define ADC_CLOCK_ASYNC_DIV256             (LL_ADC_CLOCK_ASYNC_DIV256)    /*!< ADC asynchronous clock with prescaler division by 256 */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_HAL_EC_RESOLUTION  ADC instance - Resolution

+  * @{

+  */

+#define ADC_RESOLUTION_16B                 (LL_ADC_RESOLUTION_16B)  /*!< ADC resolution 16 bits */

+#define ADC_RESOLUTION_14B                 (LL_ADC_RESOLUTION_14B)  /*!< ADC resolution 14 bits */

+#define ADC_RESOLUTION_12B                 (LL_ADC_RESOLUTION_12B)  /*!< ADC resolution 12 bits */

+#define ADC_RESOLUTION_10B                 (LL_ADC_RESOLUTION_10B)  /*!< ADC resolution 10 bits */

+#define ADC_RESOLUTION_8B                  (LL_ADC_RESOLUTION_8B)   /*!< ADC resolution  8 bits */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_Scan_mode ADC sequencer scan mode

+  * @{

+  */

+#define ADC_SCAN_DISABLE         (0x00000000UL)       /*!< Scan mode disabled */

+#define ADC_SCAN_ENABLE          (0x00000001UL)       /*!< Scan mode enabled  */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source

+  * @{

+  */

+/* ADC group regular trigger sources for all ADC instances */

+#define ADC_SOFTWARE_START            (LL_ADC_REG_TRIG_SOFTWARE)                 /*!< ADC group regular conversion trigger internal: SW start. */

+#define ADC_EXTERNALTRIG_T1_CC1       (LL_ADC_REG_TRIG_EXT_TIM1_CH1)             /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIG_T1_CC2       (LL_ADC_REG_TRIG_EXT_TIM1_CH2)             /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIG_T1_CC3       (LL_ADC_REG_TRIG_EXT_TIM1_CH3)             /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIG_T2_CC2       (LL_ADC_REG_TRIG_EXT_TIM2_CH2)             /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIG_T3_TRGO      (LL_ADC_REG_TRIG_EXT_TIM3_TRGO)            /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIG_T4_CC4       (LL_ADC_REG_TRIG_EXT_TIM4_CH4)             /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIG_EXT_IT11     (LL_ADC_REG_TRIG_EXT_EXTI_LINE11)          /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11 event. Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIG_T8_TRGO      (LL_ADC_REG_TRIG_EXT_TIM8_TRGO)            /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIG_T8_TRGO2     (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2)           /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIG_T1_TRGO      (LL_ADC_REG_TRIG_EXT_TIM1_TRGO)            /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIG_T1_TRGO2     (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2)           /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIG_T2_TRGO      (LL_ADC_REG_TRIG_EXT_TIM2_TRGO)            /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIG_T4_TRGO      (LL_ADC_REG_TRIG_EXT_TIM4_TRGO)            /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIG_T6_TRGO      (LL_ADC_REG_TRIG_EXT_TIM6_TRGO)            /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIG_T15_TRGO     (LL_ADC_REG_TRIG_EXT_TIM15_TRGO)           /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIG_T3_CC4       (LL_ADC_REG_TRIG_EXT_TIM3_CH4)             /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIG_HR1_ADCTRG1  (LL_ADC_REG_TRIG_EXT_HRTIM_TRG1)           /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG1 event. Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIG_HR1_ADCTRG3  (LL_ADC_REG_TRIG_EXT_HRTIM_TRG3)           /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG3 event. Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIG_LPTIM1_OUT   (LL_ADC_REG_TRIG_EXT_LPTIM1_OUT)           /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIG_LPTIM2_OUT   (LL_ADC_REG_TRIG_EXT_LPTIM2_OUT)           /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIG_LPTIM3_OUT   (LL_ADC_REG_TRIG_EXT_LPTIM3_OUT)           /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 event OUT. Trigger edge set to rising edge (default setting). */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected)

+  * @{

+  */

+#define ADC_EXTERNALTRIGCONVEDGE_NONE           (0x00000000UL)                      /*!< Regular conversions hardware trigger detection disabled */

+#define ADC_EXTERNALTRIGCONVEDGE_RISING         (LL_ADC_REG_TRIG_EXT_RISING)        /*!< ADC group regular conversion trigger polarity set to rising edge */

+#define ADC_EXTERNALTRIGCONVEDGE_FALLING        (LL_ADC_REG_TRIG_EXT_FALLING)       /*!< ADC group regular conversion trigger polarity set to falling edge */

+#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions

+  * @{

+  */

+#define ADC_EOC_SINGLE_CONV         (ADC_ISR_EOC)                 /*!< End of unitary conversion flag  */

+#define ADC_EOC_SEQ_CONV            (ADC_ISR_EOS)                 /*!< End of sequence conversions flag    */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion data

+  * @{

+  */

+#define ADC_OVR_DATA_PRESERVED             (LL_ADC_REG_OVR_DATA_PRESERVED)    /*!< ADC group regular behavior in case of overrun: data preserved */

+#define ADC_OVR_DATA_OVERWRITTEN           (LL_ADC_REG_OVR_DATA_OVERWRITTEN)  /*!< ADC group regular behavior in case of overrun: data overwritten */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks

+  * @{

+  */

+#define ADC_REGULAR_RANK_1                 (LL_ADC_REG_RANK_1)  /*!< ADC group regular sequencer rank 1 */

+#define ADC_REGULAR_RANK_2                 (LL_ADC_REG_RANK_2)  /*!< ADC group regular sequencer rank 2 */

+#define ADC_REGULAR_RANK_3                 (LL_ADC_REG_RANK_3)  /*!< ADC group regular sequencer rank 3 */

+#define ADC_REGULAR_RANK_4                 (LL_ADC_REG_RANK_4)  /*!< ADC group regular sequencer rank 4 */

+#define ADC_REGULAR_RANK_5                 (LL_ADC_REG_RANK_5)  /*!< ADC group regular sequencer rank 5 */

+#define ADC_REGULAR_RANK_6                 (LL_ADC_REG_RANK_6)  /*!< ADC group regular sequencer rank 6 */

+#define ADC_REGULAR_RANK_7                 (LL_ADC_REG_RANK_7)  /*!< ADC group regular sequencer rank 7 */

+#define ADC_REGULAR_RANK_8                 (LL_ADC_REG_RANK_8)  /*!< ADC group regular sequencer rank 8 */

+#define ADC_REGULAR_RANK_9                 (LL_ADC_REG_RANK_9)  /*!< ADC group regular sequencer rank 9 */

+#define ADC_REGULAR_RANK_10                (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */

+#define ADC_REGULAR_RANK_11                (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */

+#define ADC_REGULAR_RANK_12                (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */

+#define ADC_REGULAR_RANK_13                (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */

+#define ADC_REGULAR_RANK_14                (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */

+#define ADC_REGULAR_RANK_15                (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */

+#define ADC_REGULAR_RANK_16                (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time

+  * @{

+  */

+#define ADC_SAMPLETIME_1CYCLE_5          (LL_ADC_SAMPLINGTIME_1CYCLE_5)     /*!< Sampling time 1.5 ADC clock cycles */

+#define ADC_SAMPLETIME_2CYCLES_5         (LL_ADC_SAMPLINGTIME_2CYCLES_5)    /*!< Sampling time 2.5 ADC clock cycles */

+#define ADC_SAMPLETIME_8CYCLES_5         (LL_ADC_SAMPLINGTIME_8CYCLES_5)    /*!< Sampling time 8.5 ADC clock cycles */

+#define ADC_SAMPLETIME_16CYCLES_5        (LL_ADC_SAMPLINGTIME_16CYCLES_5)   /*!< Sampling time 16.5 ADC clock cycles */

+#define ADC_SAMPLETIME_32CYCLES_5        (LL_ADC_SAMPLINGTIME_32CYCLES_5)   /*!< Sampling time 32.5 ADC clock cycles */

+#define ADC_SAMPLETIME_64CYCLES_5        (LL_ADC_SAMPLINGTIME_64CYCLES_5)   /*!< Sampling time 64.5 ADC clock cycles */

+#define ADC_SAMPLETIME_387CYCLES_5       (LL_ADC_SAMPLINGTIME_387CYCLES_5)  /*!< Sampling time 387.5 ADC clock cycles */

+#define ADC_SAMPLETIME_810CYCLES_5       (LL_ADC_SAMPLINGTIME_810CYCLES_5)  /*!< Sampling time 810.5 ADC clock cycles */

+/**

+  * @}

+  */

+

+/** @defgroup ADCEx_Calibration_Mode   ADC Extended Calibration mode offset mode or linear mode

+  * @{

+  */

+#define ADC_CALIB_OFFSET                   (LL_ADC_CALIB_OFFSET)

+#define ADC_CALIB_OFFSET_LINEARITY         (LL_ADC_CALIB_OFFSET_LINEARITY)

+/**

+  * @}

+  */

+

+/** @defgroup ADC_HAL_EC_CHANNEL  ADC instance - Channel number

+  * @{

+  */

+/* Note: VrefInt, TempSensor and Vbat internal channels are not available on  */

+/*        all ADC instances (refer to Reference Manual).                      */

+#define ADC_CHANNEL_0                      (LL_ADC_CHANNEL_0)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0  */

+#define ADC_CHANNEL_1                      (LL_ADC_CHANNEL_1)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1  */

+#define ADC_CHANNEL_2                      (LL_ADC_CHANNEL_2)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2  */

+#define ADC_CHANNEL_3                      (LL_ADC_CHANNEL_3)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3  */

+#define ADC_CHANNEL_4                      (LL_ADC_CHANNEL_4)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4  */

+#define ADC_CHANNEL_5                      (LL_ADC_CHANNEL_5)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5  */

+#define ADC_CHANNEL_6                      (LL_ADC_CHANNEL_6)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6  */

+#define ADC_CHANNEL_7                      (LL_ADC_CHANNEL_7)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7  */

+#define ADC_CHANNEL_8                      (LL_ADC_CHANNEL_8)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8  */

+#define ADC_CHANNEL_9                      (LL_ADC_CHANNEL_9)               /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9  */

+#define ADC_CHANNEL_10                     (LL_ADC_CHANNEL_10)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */

+#define ADC_CHANNEL_11                     (LL_ADC_CHANNEL_11)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */

+#define ADC_CHANNEL_12                     (LL_ADC_CHANNEL_12)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */

+#define ADC_CHANNEL_13                     (LL_ADC_CHANNEL_13)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */

+#define ADC_CHANNEL_14                     (LL_ADC_CHANNEL_14)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */

+#define ADC_CHANNEL_15                     (LL_ADC_CHANNEL_15)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */

+#define ADC_CHANNEL_16                     (LL_ADC_CHANNEL_16)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */

+#define ADC_CHANNEL_17                     (LL_ADC_CHANNEL_17)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */

+#define ADC_CHANNEL_18                     (LL_ADC_CHANNEL_18)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */

+#define ADC_CHANNEL_19                     (LL_ADC_CHANNEL_19)              /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */

+#define ADC_CHANNEL_VREFINT                (LL_ADC_CHANNEL_VREFINT)         /*!< ADC internal channel connected to VrefInt: Internal voltage reference, channel specific to ADC3. */

+#define ADC_CHANNEL_TEMPSENSOR             (LL_ADC_CHANNEL_TEMPSENSOR)      /*!< ADC internal channel connected to Temperature sensor, channel specific to ADC3. */

+#define ADC_CHANNEL_VBAT                   (LL_ADC_CHANNEL_VBAT)            /*!< ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, channel specific to ADC3. */

+#define ADC_CHANNEL_DAC1CH1_ADC2           (LL_ADC_CHANNEL_DAC1CH1_ADC2)    /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */

+#define ADC_CHANNEL_DAC1CH2_ADC2           (LL_ADC_CHANNEL_DAC1CH2_ADC2)    /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */

+#if defined (LL_ADC_CHANNEL_DAC2CH1_ADC2)

+#define ADC_CHANNEL_DAC2CH1_ADC2           (LL_ADC_CHANNEL_DAC2CH1_ADC2)    /*!< ADC internal channel connected to DAC2 channel 1, channel specific to ADC2 */

+#endif

+/**

+  * @}

+  */

+

+/** @defgroup ADC_ConversionDataManagement ADC Conversion Data Management

+  * @{

+  */

+#define ADC_CONVERSIONDATA_DR                  (0x00000000UL)                          /*!< Regular Conversion data stored in DR register only  */

+#define ADC_CONVERSIONDATA_DFSDM               (ADC_CFGR_DMNGT_1)                      /*!< DFSDM mode selected */

+#define ADC_CONVERSIONDATA_DMA_ONESHOT         (ADC_CFGR_DMNGT_0)                      /*!< DMA one shot mode selected */

+#define ADC_CONVERSIONDATA_DMA_CIRCULAR        (ADC_CFGR_DMNGT_0 | ADC_CFGR_DMNGT_1)   /*!< DMA circular mode selected */

+/**

+  * @}

+  */

+/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number

+  * @{

+  */

+#define ADC_ANALOGWATCHDOG_1               (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */

+#define ADC_ANALOGWATCHDOG_2               (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */

+#define ADC_ANALOGWATCHDOG_3               (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode

+  * @{

+  */

+#define ADC_ANALOGWATCHDOG_NONE                 (0x00000000UL)                                          /*!< No analog watchdog selected                                             */

+#define ADC_ANALOGWATCHDOG_SINGLE_REG           (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN)                    /*!< Analog watchdog applied to a regular group single channel               */

+#define ADC_ANALOGWATCHDOG_SINGLE_INJEC         (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN)                   /*!< Analog watchdog applied to an injected group single channel             */

+#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC      (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */

+#define ADC_ANALOGWATCHDOG_ALL_REG              (ADC_CFGR_AWD1EN)                                       /*!< Analog watchdog applied to regular group all channels                   */

+#define ADC_ANALOGWATCHDOG_ALL_INJEC            (ADC_CFGR_JAWD1EN)                                      /*!< Analog watchdog applied to injected group all channels                  */

+#define ADC_ANALOGWATCHDOG_ALL_REGINJEC         (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN)                    /*!< Analog watchdog applied to regular and injected groups all channels     */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_HAL_EC_OVS_SHIFT  Oversampling - Data shift

+  * @{

+  */

+#define ADC_RIGHTBITSHIFT_NONE             (LL_ADC_OVS_SHIFT_NONE)    /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */

+#define ADC_RIGHTBITSHIFT_1                (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */

+#define ADC_RIGHTBITSHIFT_2                (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */

+#define ADC_RIGHTBITSHIFT_3                (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */

+#define ADC_RIGHTBITSHIFT_4                (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */

+#define ADC_RIGHTBITSHIFT_5                (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */

+#define ADC_RIGHTBITSHIFT_6                (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */

+#define ADC_RIGHTBITSHIFT_7                (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */

+#define ADC_RIGHTBITSHIFT_8                (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */

+#define ADC_RIGHTBITSHIFT_9                (LL_ADC_OVS_SHIFT_RIGHT_9) /*!< ADC oversampling shift of 9 (sum of the ADC conversions data is divided by 512 to result as the ADC oversampling conversion data) */

+#define ADC_RIGHTBITSHIFT_10               (LL_ADC_OVS_SHIFT_RIGHT_10)/*!< ADC oversampling shift of 10 (sum of the ADC conversions data is divided by 1024 to result as the ADC oversampling conversion data) */

+#define ADC_RIGHTBITSHIFT_11               (LL_ADC_OVS_SHIFT_RIGHT_11)/*!< ADC oversampling shift of 11 (sum of the ADC conversions data is divided by 2048 to result as the ADC oversampling conversion data) */

+/**

+  * @}

+  */

+

+/** @defgroup ADCEx_Left_Bit_Shift   ADC Extended Oversampling left Shift

+  * @{

+  */

+#define ADC_LEFTBITSHIFT_NONE  (LL_ADC_LEFT_BIT_SHIFT_NONE)   /*!<  ADC No bit shift */

+#define ADC_LEFTBITSHIFT_1     (LL_ADC_LEFT_BIT_SHIFT_1)      /*!<  ADC 1 bit shift  */

+#define ADC_LEFTBITSHIFT_2     (LL_ADC_LEFT_BIT_SHIFT_2)      /*!<  ADC 2 bits shift */

+#define ADC_LEFTBITSHIFT_3     (LL_ADC_LEFT_BIT_SHIFT_3)      /*!<  ADC 3 bits shift */

+#define ADC_LEFTBITSHIFT_4     (LL_ADC_LEFT_BIT_SHIFT_4)      /*!<  ADC 4 bits shift */

+#define ADC_LEFTBITSHIFT_5     (LL_ADC_LEFT_BIT_SHIFT_5)      /*!<  ADC 5 bits shift */

+#define ADC_LEFTBITSHIFT_6     (LL_ADC_LEFT_BIT_SHIFT_6)      /*!<  ADC 6 bits shift */

+#define ADC_LEFTBITSHIFT_7     (LL_ADC_LEFT_BIT_SHIFT_7)      /*!<  ADC 7 bits shift */

+#define ADC_LEFTBITSHIFT_8     (LL_ADC_LEFT_BIT_SHIFT_8)      /*!<  ADC 8 bits shift */

+#define ADC_LEFTBITSHIFT_9     (LL_ADC_LEFT_BIT_SHIFT_9)      /*!<  ADC 9 bits shift */

+#define ADC_LEFTBITSHIFT_10    (LL_ADC_LEFT_BIT_SHIFT_10)     /*!<  ADC 10 bits shift */

+#define ADC_LEFTBITSHIFT_11    (LL_ADC_LEFT_BIT_SHIFT_11)     /*!<  ADC 11 bits shift */

+#define ADC_LEFTBITSHIFT_12    (LL_ADC_LEFT_BIT_SHIFT_12)     /*!<  ADC 12 bits shift */

+#define ADC_LEFTBITSHIFT_13    (LL_ADC_LEFT_BIT_SHIFT_13)     /*!<  ADC 13 bits shift */

+#define ADC_LEFTBITSHIFT_14    (LL_ADC_LEFT_BIT_SHIFT_14)     /*!<  ADC 14 bits shift */

+#define ADC_LEFTBITSHIFT_15    (LL_ADC_LEFT_BIT_SHIFT_15)     /*!<  ADC 15 bits shift */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE  Oversampling - Discontinuous mode

+  * @{

+  */

+#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER   (LL_ADC_OVS_REG_CONT)          /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */

+#define ADC_TRIGGEREDMODE_MULTI_TRIGGER    (LL_ADC_OVS_REG_DISCONT)       /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_HAL_EC_OVS_SCOPE_REG  Oversampling - Oversampling scope for ADC group regular

+  * @{

+  */

+#define ADC_REGOVERSAMPLING_CONTINUED_MODE    (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained during injection sequence */

+#define ADC_REGOVERSAMPLING_RESUMED_MODE      (LL_ADC_OVS_GRP_REGULAR_RESUMED)   /*!< Oversampling buffer zeroed during injection sequence     */

+/**

+  * @}

+  */

+

+

+/** @defgroup ADC_Event_type ADC Event type

+  * @{

+  */

+#define ADC_EOSMP_EVENT          (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */

+#define ADC_AWD1_EVENT           (ADC_FLAG_AWD1)  /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */

+#define ADC_AWD2_EVENT           (ADC_FLAG_AWD2)  /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */

+#define ADC_AWD3_EVENT           (ADC_FLAG_AWD3)  /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */

+#define ADC_OVR_EVENT            (ADC_FLAG_OVR)   /*!< ADC overrun event */

+#define ADC_JQOVF_EVENT          (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */

+/**

+  * @}

+  */

+#define ADC_AWD_EVENT            ADC_AWD1_EVENT      /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */

+

+/** @defgroup ADC_interrupts_definition ADC interrupts definition

+  * @{

+  */

+#define ADC_IT_RDY           ADC_IER_ADRDYIE    /*!< ADC Ready interrupt source */

+#define ADC_IT_EOSMP         ADC_IER_EOSMPIE    /*!< ADC End of sampling interrupt source */

+#define ADC_IT_EOC           ADC_IER_EOCIE      /*!< ADC End of regular conversion interrupt source */

+#define ADC_IT_EOS           ADC_IER_EOSIE      /*!< ADC End of regular sequence of conversions interrupt source */

+#define ADC_IT_OVR           ADC_IER_OVRIE      /*!< ADC overrun interrupt source */

+#define ADC_IT_JEOC          ADC_IER_JEOCIE     /*!< ADC End of injected conversion interrupt source */

+#define ADC_IT_JEOS          ADC_IER_JEOSIE     /*!< ADC End of injected sequence of conversions interrupt source */

+#define ADC_IT_AWD1          ADC_IER_AWD1IE     /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */

+#define ADC_IT_AWD2          ADC_IER_AWD2IE     /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */

+#define ADC_IT_AWD3          ADC_IER_AWD3IE     /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */

+#define ADC_IT_JQOVF         ADC_IER_JQOVFIE    /*!< ADC Injected Context Queue Overflow interrupt source */

+

+#define ADC_IT_AWD           ADC_IT_AWD1        /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */

+

+/**

+  * @}

+  */

+

+/** @defgroup ADC_flags_definition ADC flags definition

+  * @{

+  */

+#define ADC_FLAG_RDY           ADC_ISR_ADRDY    /*!< ADC Ready flag */

+#define ADC_FLAG_EOSMP         ADC_ISR_EOSMP    /*!< ADC End of Sampling flag */

+#define ADC_FLAG_EOC           ADC_ISR_EOC      /*!< ADC End of Regular Conversion flag */

+#define ADC_FLAG_EOS           ADC_ISR_EOS      /*!< ADC End of Regular sequence of Conversions flag */

+#define ADC_FLAG_OVR           ADC_ISR_OVR      /*!< ADC overrun flag */

+#define ADC_FLAG_JEOC          ADC_ISR_JEOC     /*!< ADC End of Injected Conversion flag */

+#define ADC_FLAG_JEOS          ADC_ISR_JEOS     /*!< ADC End of Injected sequence of Conversions flag */

+#define ADC_FLAG_AWD1          ADC_ISR_AWD1     /*!< ADC Analog watchdog 1 flag (main analog watchdog) */

+#define ADC_FLAG_AWD2          ADC_ISR_AWD2     /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */

+#define ADC_FLAG_AWD3          ADC_ISR_AWD3     /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */

+#define ADC_FLAG_JQOVF         ADC_ISR_JQOVF    /*!< ADC Injected Context Queue Overflow flag */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private macro -------------------------------------------------------------*/

+

+/** @defgroup ADC_Private_Macros ADC Private Macros

+  * @{

+  */

+/* Macro reserved for internal HAL driver usage, not intended to be used in   */

+/* code of final user.                                                        */

+

+/**

+  * @brief Verify the ADC data conversion setting.

+  * @param DATA : programmed DATA conversion mode.

+  * @retval SET (DATA is a valid value) or RESET (DATA is invalid)

+  */

+#define IS_ADC_CONVERSIONDATAMGT(DATA)                                         \

+   ((((DATA) == ADC_CONVERSIONDATA_DR))          || \

+    (((DATA) == ADC_CONVERSIONDATA_DFSDM))       || \

+    (((DATA) == ADC_CONVERSIONDATA_DMA_ONESHOT)) || \

+    (((DATA) == ADC_CONVERSIONDATA_DMA_CIRCULAR)))

+

+/**

+  * @brief Return resolution bits in CFGR register RES[1:0] field.

+  * @param __HANDLE__ ADC handle

+  * @retval Value of bitfield RES in CFGR register.

+  */

+#define ADC_GET_RESOLUTION(__HANDLE__)                                         \

+  (LL_ADC_GetResolution((__HANDLE__)->Instance))

+

+/**

+  * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE").

+  * @param __HANDLE__ ADC handle

+  * @retval None

+  */

+#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)

+

+/**

+  * @brief Verification of ADC state: enabled or disabled.

+  * @param __HANDLE__ ADC handle

+  * @retval SET (ADC enabled) or RESET (ADC disabled)

+  */

+#define ADC_IS_ENABLE(__HANDLE__)                                                    \

+       (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \

+          ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY)                  \

+        ) ? SET : RESET)

+

+/**

+  * @brief Check if conversion is on going on regular group.

+  * @param __HANDLE__ ADC handle

+  * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going)

+  */

+#define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__)                          \

+  (LL_ADC_REG_IsConversionOngoing((__HANDLE__)->Instance))

+

+/**

+  * @brief Check if ADC clock mode is synchronous

+  * @param __HANDLE__: ADC handle

+  * @retval SET (clock mode is synchronous) or RESET (clock mode is asynchronous)

+  */

+#if defined (ADC3)

+#define ADC_IS_SYNCHRONOUS_CLOCK_MODE(__HANDLE__)                                   \

+       (((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2))? \

+     ((ADC12_COMMON->CCR & ADC_CCR_CKMODE) != 0UL)                              \

+     :((((ADC3_COMMON)->CCR) & ADC_CCR_CKMODE) != 0UL))

+#else

+#define ADC_IS_SYNCHRONOUS_CLOCK_MODE(__HANDLE__)     ((ADC12_COMMON->CCR & ADC_CCR_CKMODE) != 0UL)

+

+#endif

+

+/**

+  * @brief Simultaneously clear and set specific bits of the handle State.

+  * @note  ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),

+  *        the first parameter is the ADC handle State, the second parameter is the

+  *        bit field to clear, the third and last parameter is the bit field to set.

+  * @retval None

+  */

+#define ADC_STATE_CLR_SET MODIFY_REG

+

+/**

+  * @brief Verify that a given value is aligned with the ADC resolution range.

+  * @param __RESOLUTION__ ADC resolution (16, 14, 12, 10 or 8 bits).

+  * @param __ADC_VALUE__ value checked against the resolution.

+  * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)

+  */

+#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \

+  ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__))

+

+/**

+  * @brief Verify the length of the scheduled regular conversions group.

+  * @param __LENGTH__ number of programmed conversions.

+  * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large)

+  */

+#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))

+

+

+/**

+  * @brief Verify the number of scheduled regular conversions in discontinuous mode.

+  * @param NUMBER number of scheduled regular conversions in discontinuous mode.

+  * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large)

+  */

+#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))

+

+

+/**

+  * @brief Verify the ADC clock setting.

+  * @param __ADC_CLOCK__ programmed ADC clock.

+  * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid)

+  */

+#define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \

+                                              ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \

+                                              ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \

+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1)     || \

+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2)     || \

+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4)     || \

+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6)     || \

+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8)     || \

+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10)    || \

+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12)    || \

+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16)    || \

+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32)    || \

+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64)    || \

+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128)   || \

+                                              ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) )

+

+/**

+  * @brief Verify the ADC resolution setting.

+  * @param __RESOLUTION__ programmed ADC resolution.

+  * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)

+  */

+#define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_16B) || \

+                                           ((__RESOLUTION__) == ADC_RESOLUTION_14B) || \

+                                           ((__RESOLUTION__) == ADC_RESOLUTION_12B) || \

+                                           ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \

+                                           ((__RESOLUTION__) == ADC_RESOLUTION_8B)    )

+/**

+  * @brief Verify the ADC resolution setting when limited to 8 bits.

+  * @param __RESOLUTION__ programmed ADC resolution when limited to 8 bits.

+  * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)

+  */

+#define IS_ADC_RESOLUTION_8_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B))

+

+/**

+  * @brief Verify the ADC scan mode.

+  * @param __SCAN_MODE__ programmed ADC scan mode.

+  * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid)

+  */

+#define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \

+                                         ((__SCAN_MODE__) == ADC_SCAN_ENABLE)    )

+

+/**

+  * @brief Verify the ADC edge trigger setting for regular group.

+  * @param __EDGE__ programmed ADC edge trigger setting.

+  * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)

+  */

+#define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE)         || \

+                                       ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING)       || \

+                                       ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING)      || \

+                                       ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)  )

+

+/**

+  * @brief Verify the ADC regular conversions external trigger.

+  * @param __REGTRIG__ programmed ADC regular conversions external trigger.

+  * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid)

+  */

+#define IS_ADC_EXTTRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1)        || \

+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2)        || \

+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3)        || \

+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2)        || \

+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO)       || \

+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4)        || \

+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11)      || \

+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO)       || \

+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2)      || \

+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO)       || \

+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2)      || \

+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO)       || \

+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO)       || \

+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO)       || \

+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO)      || \

+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4)        || \

+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_HR1_ADCTRG1)   || \

+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_HR1_ADCTRG3)   || \

+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM1_OUT)    || \

+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM2_OUT)    || \

+                                     ((__REGTRIG__) == ADC_EXTERNALTRIG_LPTIM3_OUT)    || \

+                                     ((__REGTRIG__) == ADC_SOFTWARE_START)           )

+

+/**

+  * @brief Verify the ADC regular conversions check for converted data availability.

+  * @param __EOC_SELECTION__ converted data availability check.

+  * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid)

+  */

+#define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV)    || \

+                                                 ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV)  )

+

+/**

+  * @brief Verify the ADC regular conversions overrun handling.

+  * @param __OVR__ ADC regular conversions overrun handling.

+  * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid)

+  */

+#define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED)  || \

+                                 ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN)  )

+

+/**

+  * @brief Verify the ADC conversions sampling time.

+  * @param __TIME__ ADC conversions sampling time.

+  * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid)

+  */

+#define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_1CYCLE_5)    || \

+                                      ((__TIME__) == ADC_SAMPLETIME_2CYCLES_5)   || \

+                                      ((__TIME__) == ADC_SAMPLETIME_8CYCLES_5)   || \

+                                      ((__TIME__) == ADC_SAMPLETIME_16CYCLES_5)  || \

+                                      ((__TIME__) == ADC_SAMPLETIME_32CYCLES_5)  || \

+                                      ((__TIME__) == ADC_SAMPLETIME_64CYCLES_5)  || \

+                                      ((__TIME__) == ADC_SAMPLETIME_387CYCLES_5) || \

+                                      ((__TIME__) == ADC_SAMPLETIME_810CYCLES_5)   )

+

+/**

+  * @brief Verify the ADC regular channel setting.

+  * @param  __CHANNEL__ programmed ADC regular channel.

+  * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)

+  */

+#define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \

+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \

+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \

+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \

+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \

+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \

+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \

+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \

+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \

+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \

+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \

+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \

+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \

+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \

+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \

+                                          ((__CHANNEL__) == ADC_REGULAR_RANK_16)   )

+

+/**

+  * @}

+  */

+

+

+/* Private constants ---------------------------------------------------------*/

+

+/** @defgroup ADC_Private_Constants ADC Private Constants

+  * @{

+  */

+

+/* Fixed timeout values for ADC conversion (including sampling time)        */

+/* Maximum sampling time is 810.5 ADC clock cycle        */

+/* Maximum conversion time is 16.5 + Maximum sampling time                  */

+/*                       or 16.5  + 810.5 = 827 ADC clock cycles            */

+/* Minimum ADC Clock frequency is 0.35 MHz                                  */

+/* Maximum conversion time is                                               */

+/*              827 / 0.35 MHz = 2.36 ms                                    */

+

+#define ADC_STOP_CONVERSION_TIMEOUT     ( 5UL)     /*!< ADC stop time-out value */

+

+/* Delay for temperature sensor stabilization time.                         */

+/* Maximum delay is 120us (refer device datasheet, parameter tSTART).       */

+/* Unit: us                                                                 */

+#define ADC_TEMPSENSOR_DELAY_US         (LL_ADC_DELAY_TEMPSENSOR_STAB_US)

+

+/* Delay for ADC voltage regulator startup time                               */

+/*  Maximum delay is 10 microseconds                                          */

+/* (refer device RM, parameter Tadcvreg_stup).                                */

+#define ADC_STAB_DELAY_US               ((uint32_t) 10)     /*!< ADC voltage regulator startup time */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+

+/** @defgroup ADC_Exported_Macros ADC Exported Macros

+  * @{

+  */

+/* Macro for internal HAL driver usage, and possibly can be used into code of */

+/* final user.                                                                */

+

+/** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags.

+  * @{

+  */

+

+/** @brief  Reset ADC handle state.

+  * @param __HANDLE__ ADC handle

+  * @retval None

+  */

+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)

+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \

+  do{                                                                          \

+    (__HANDLE__)->State = HAL_ADC_STATE_RESET;                                 \

+    (__HANDLE__)->MspInitCallback = NULL;                                      \

+    (__HANDLE__)->MspDeInitCallback = NULL;                                    \

+  } while(0)

+#else

+#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \

+  ((__HANDLE__)->State = HAL_ADC_STATE_RESET)

+#endif

+

+/**

+  * @brief Enable ADC interrupt.

+  * @param __HANDLE__ ADC handle

+  * @param __INTERRUPT__ ADC Interrupt

+  *        This parameter can be one of the following values:

+  *            @arg @ref ADC_IT_RDY    ADC Ready interrupt source

+  *            @arg @ref ADC_IT_EOSMP  ADC End of Sampling interrupt source

+  *            @arg @ref ADC_IT_EOC    ADC End of Regular Conversion interrupt source

+  *            @arg @ref ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source

+  *            @arg @ref ADC_IT_OVR    ADC overrun interrupt source

+  *            @arg @ref ADC_IT_JEOC   ADC End of Injected Conversion interrupt source

+  *            @arg @ref ADC_IT_JEOS   ADC End of Injected sequence of Conversions interrupt source

+  *            @arg @ref ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)

+  *            @arg @ref ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)

+  *            @arg @ref ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)

+  *            @arg @ref ADC_IT_JQOVF  ADC Injected Context Queue Overflow interrupt source.

+  * @retval None

+  */

+#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                         \

+  (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))

+

+/**

+  * @brief Disable ADC interrupt.

+  * @param __HANDLE__ ADC handle

+  * @param __INTERRUPT__ ADC Interrupt

+  *        This parameter can be one of the following values:

+  *            @arg @ref ADC_IT_RDY    ADC Ready interrupt source

+  *            @arg @ref ADC_IT_EOSMP  ADC End of Sampling interrupt source

+  *            @arg @ref ADC_IT_EOC    ADC End of Regular Conversion interrupt source

+  *            @arg @ref ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source

+  *            @arg @ref ADC_IT_OVR    ADC overrun interrupt source

+  *            @arg @ref ADC_IT_JEOC   ADC End of Injected Conversion interrupt source

+  *            @arg @ref ADC_IT_JEOS   ADC End of Injected sequence of Conversions interrupt source

+  *            @arg @ref ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)

+  *            @arg @ref ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)

+  *            @arg @ref ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)

+  *            @arg @ref ADC_IT_JQOVF  ADC Injected Context Queue Overflow interrupt source.

+  * @retval None

+  */

+#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                        \

+  (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))

+

+/** @brief  Checks if the specified ADC interrupt source is enabled or disabled.

+  * @param __HANDLE__ ADC handle

+  * @param __INTERRUPT__ ADC interrupt source to check

+  *          This parameter can be one of the following values:

+  *            @arg @ref ADC_IT_RDY    ADC Ready interrupt source

+  *            @arg @ref ADC_IT_EOSMP  ADC End of Sampling interrupt source

+  *            @arg @ref ADC_IT_EOC    ADC End of Regular Conversion interrupt source

+  *            @arg @ref ADC_IT_EOS    ADC End of Regular sequence of Conversions interrupt source

+  *            @arg @ref ADC_IT_OVR    ADC overrun interrupt source

+  *            @arg @ref ADC_IT_JEOC   ADC End of Injected Conversion interrupt source

+  *            @arg @ref ADC_IT_JEOS   ADC End of Injected sequence of Conversions interrupt source

+  *            @arg @ref ADC_IT_AWD1   ADC Analog watchdog 1 interrupt source (main analog watchdog)

+  *            @arg @ref ADC_IT_AWD2   ADC Analog watchdog 2 interrupt source (additional analog watchdog)

+  *            @arg @ref ADC_IT_AWD3   ADC Analog watchdog 3 interrupt source (additional analog watchdog)

+  *            @arg @ref ADC_IT_JQOVF  ADC Injected Context Queue Overflow interrupt source.

+  * @retval State of interruption (SET or RESET)

+  */

+#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                     \

+  (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))

+

+/**

+  * @brief Check whether the specified ADC flag is set or not.

+  * @param __HANDLE__ ADC handle

+  * @param __FLAG__ ADC flag

+  *        This parameter can be one of the following values:

+  *            @arg @ref ADC_FLAG_RDY     ADC Ready flag

+  *            @arg @ref ADC_FLAG_EOSMP   ADC End of Sampling flag

+  *            @arg @ref ADC_FLAG_EOC     ADC End of Regular Conversion flag

+  *            @arg @ref ADC_FLAG_EOS     ADC End of Regular sequence of Conversions flag

+  *            @arg @ref ADC_FLAG_OVR     ADC overrun flag

+  *            @arg @ref ADC_FLAG_JEOC    ADC End of Injected Conversion flag

+  *            @arg @ref ADC_FLAG_JEOS    ADC End of Injected sequence of Conversions flag

+  *            @arg @ref ADC_FLAG_AWD1    ADC Analog watchdog 1 flag (main analog watchdog)

+  *            @arg @ref ADC_FLAG_AWD2    ADC Analog watchdog 2 flag (additional analog watchdog)

+  *            @arg @ref ADC_FLAG_AWD3    ADC Analog watchdog 3 flag (additional analog watchdog)

+  *            @arg @ref ADC_FLAG_JQOVF   ADC Injected Context Queue Overflow flag.

+  * @retval State of flag (TRUE or FALSE).

+  */

+#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__)                               \

+  ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))

+

+/**

+  * @brief Clear the specified ADC flag.

+  * @param __HANDLE__ ADC handle

+  * @param __FLAG__ ADC flag

+  *        This parameter can be one of the following values:

+  *            @arg @ref ADC_FLAG_RDY     ADC Ready flag

+  *            @arg @ref ADC_FLAG_EOSMP   ADC End of Sampling flag

+  *            @arg @ref ADC_FLAG_EOC     ADC End of Regular Conversion flag

+  *            @arg @ref ADC_FLAG_EOS     ADC End of Regular sequence of Conversions flag

+  *            @arg @ref ADC_FLAG_OVR     ADC overrun flag

+  *            @arg @ref ADC_FLAG_JEOC    ADC End of Injected Conversion flag

+  *            @arg @ref ADC_FLAG_JEOS    ADC End of Injected sequence of Conversions flag

+  *            @arg @ref ADC_FLAG_AWD1    ADC Analog watchdog 1 flag (main analog watchdog)

+  *            @arg @ref ADC_FLAG_AWD2    ADC Analog watchdog 2 flag (additional analog watchdog)

+  *            @arg @ref ADC_FLAG_AWD3    ADC Analog watchdog 3 flag (additional analog watchdog)

+  *            @arg @ref ADC_FLAG_JQOVF   ADC Injected Context Queue Overflow flag.

+  * @retval None

+  */

+/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */

+#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__)                             \

+  (((__HANDLE__)->Instance->ISR) = (__FLAG__))

+

+/**

+  * @}

+  */

+

+/** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro

+  * @{

+  */

+

+/**

+  * @brief  Helper macro to get ADC channel number in decimal format

+  *         from literals ADC_CHANNEL_x.

+  * @note   Example:

+  *           __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4)

+  *           will return decimal number "4".

+  * @note   The input can be a value from functions where a channel

+  *         number is returned, either defined with number

+  *         or with bitfield (only one bit must be set).

+  * @param  __CHANNEL__ This parameter can be one of the following values:

+  *         @arg @ref ADC_CHANNEL_0           (3)

+  *         @arg @ref ADC_CHANNEL_1           (3)

+  *         @arg @ref ADC_CHANNEL_2           (3)

+  *         @arg @ref ADC_CHANNEL_3           (3)

+  *         @arg @ref ADC_CHANNEL_4           (3)

+  *         @arg @ref ADC_CHANNEL_5           (3)

+  *         @arg @ref ADC_CHANNEL_6

+  *         @arg @ref ADC_CHANNEL_7

+  *         @arg @ref ADC_CHANNEL_8

+  *         @arg @ref ADC_CHANNEL_9

+  *         @arg @ref ADC_CHANNEL_10

+  *         @arg @ref ADC_CHANNEL_11

+  *         @arg @ref ADC_CHANNEL_12

+  *         @arg @ref ADC_CHANNEL_13

+  *         @arg @ref ADC_CHANNEL_14

+  *         @arg @ref ADC_CHANNEL_15

+  *         @arg @ref ADC_CHANNEL_16

+  *         @arg @ref ADC_CHANNEL_17

+  *         @arg @ref ADC_CHANNEL_18

+  *         @arg @ref ADC_CHANNEL_VREFINT      (1)

+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR   (1)

+  *         @arg @ref ADC_CHANNEL_VBAT         (1)

+  *         @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)

+  *         @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)

+  *         

+  *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

+  *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

+  *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

+  *             Other channels are slow channels (conversion rate: refer to reference manual).

+  * @retval Value between Min_Data=0 and Max_Data=18

+  */

+#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                           \

+  __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))

+

+/**

+  * @brief  Helper macro to get ADC channel in literal format ADC_CHANNEL_x

+  *         from number in decimal format.

+  * @note   Example:

+  *           __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4)

+  *           will return a data equivalent to "ADC_CHANNEL_4".

+  * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref ADC_CHANNEL_0           (3)

+  *         @arg @ref ADC_CHANNEL_1           (3)

+  *         @arg @ref ADC_CHANNEL_2           (3)

+  *         @arg @ref ADC_CHANNEL_3           (3)

+  *         @arg @ref ADC_CHANNEL_4           (3)

+  *         @arg @ref ADC_CHANNEL_5           (3)

+  *         @arg @ref ADC_CHANNEL_6

+  *         @arg @ref ADC_CHANNEL_7

+  *         @arg @ref ADC_CHANNEL_8

+  *         @arg @ref ADC_CHANNEL_9

+  *         @arg @ref ADC_CHANNEL_10

+  *         @arg @ref ADC_CHANNEL_11

+  *         @arg @ref ADC_CHANNEL_12

+  *         @arg @ref ADC_CHANNEL_13

+  *         @arg @ref ADC_CHANNEL_14

+  *         @arg @ref ADC_CHANNEL_15

+  *         @arg @ref ADC_CHANNEL_16

+  *         @arg @ref ADC_CHANNEL_17

+  *         @arg @ref ADC_CHANNEL_18

+  *         @arg @ref ADC_CHANNEL_VREFINT      (1)

+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR   (1)

+  *         @arg @ref ADC_CHANNEL_VBAT         (1)

+  *         @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)

+  *         @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)

+  *         

+  *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

+  *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

+  *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

+  *             Other channels are slow channels (conversion rate: refer to reference manual).\n

+  *         (1, 2) For ADC channel read back from ADC register,

+  *                comparison with internal channel parameter to be done

+  *                using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

+  */

+#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                        \

+  __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))

+

+/**

+  * @brief  Helper macro to determine whether the selected channel

+  *         corresponds to literal definitions of driver.

+  * @note   The different literal definitions of ADC channels are:

+  *         - ADC internal channel:

+  *           ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...

+  *         - ADC external channel (channel connected to a GPIO pin):

+  *           ADC_CHANNEL_1, ADC_CHANNEL_2, ...

+  * @note   The channel parameter must be a value defined from literal

+  *         definition of a ADC internal channel (ADC_CHANNEL_VREFINT,

+  *         ADC_CHANNEL_TEMPSENSOR, ...),

+  *         ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...),

+  *         must not be a value from functions where a channel number is

+  *         returned from ADC registers,

+  *         because internal and external channels share the same channel

+  *         number in ADC registers. The differentiation is made only with

+  *         parameters definitions of driver.

+  * @param  __CHANNEL__ This parameter can be one of the following values:

+  *         @arg @ref ADC_CHANNEL_0           (3)

+  *         @arg @ref ADC_CHANNEL_1           (3)

+  *         @arg @ref ADC_CHANNEL_2           (3)

+  *         @arg @ref ADC_CHANNEL_3           (3)

+  *         @arg @ref ADC_CHANNEL_4           (3)

+  *         @arg @ref ADC_CHANNEL_5           (3)

+  *         @arg @ref ADC_CHANNEL_6

+  *         @arg @ref ADC_CHANNEL_7

+  *         @arg @ref ADC_CHANNEL_8

+  *         @arg @ref ADC_CHANNEL_9

+  *         @arg @ref ADC_CHANNEL_10

+  *         @arg @ref ADC_CHANNEL_11

+  *         @arg @ref ADC_CHANNEL_12

+  *         @arg @ref ADC_CHANNEL_13

+  *         @arg @ref ADC_CHANNEL_14

+  *         @arg @ref ADC_CHANNEL_15

+  *         @arg @ref ADC_CHANNEL_16

+  *         @arg @ref ADC_CHANNEL_17

+  *         @arg @ref ADC_CHANNEL_18

+  *         @arg @ref ADC_CHANNEL_VREFINT      (1)

+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR   (1)

+  *         @arg @ref ADC_CHANNEL_VBAT         (1)

+  *         @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)

+  *         @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)

+  *         

+  *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

+  *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

+  *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

+  *             Other channels are slow channels (conversion rate: refer to reference manual).

+  * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).

+  *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.

+  */

+#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                             \

+  __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))

+

+/**

+  * @brief  Helper macro to convert a channel defined from parameter

+  *         definition of a ADC internal channel (ADC_CHANNEL_VREFINT,

+  *         ADC_CHANNEL_TEMPSENSOR, ...),

+  *         to its equivalent parameter definition of a ADC external channel

+  *         (ADC_CHANNEL_1, ADC_CHANNEL_2, ...).

+  * @note   The channel parameter can be, additionally to a value

+  *         defined from parameter definition of a ADC internal channel

+  *         (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...),

+  *         a value defined from parameter definition of

+  *         ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)

+  *         or a value from functions where a channel number is returned

+  *         from ADC registers.

+  * @param  __CHANNEL__ This parameter can be one of the following values:

+  *         @arg @ref ADC_CHANNEL_0           (3)

+  *         @arg @ref ADC_CHANNEL_1           (3)

+  *         @arg @ref ADC_CHANNEL_2           (3)

+  *         @arg @ref ADC_CHANNEL_3           (3)

+  *         @arg @ref ADC_CHANNEL_4           (3)

+  *         @arg @ref ADC_CHANNEL_5           (3)

+  *         @arg @ref ADC_CHANNEL_6

+  *         @arg @ref ADC_CHANNEL_7

+  *         @arg @ref ADC_CHANNEL_8

+  *         @arg @ref ADC_CHANNEL_9

+  *         @arg @ref ADC_CHANNEL_10

+  *         @arg @ref ADC_CHANNEL_11

+  *         @arg @ref ADC_CHANNEL_12

+  *         @arg @ref ADC_CHANNEL_13

+  *         @arg @ref ADC_CHANNEL_14

+  *         @arg @ref ADC_CHANNEL_15

+  *         @arg @ref ADC_CHANNEL_16

+  *         @arg @ref ADC_CHANNEL_17

+  *         @arg @ref ADC_CHANNEL_18

+  *         @arg @ref ADC_CHANNEL_VREFINT      (1)

+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR   (1)

+  *         @arg @ref ADC_CHANNEL_VBAT         (1)

+  *         @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)

+  *         @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)

+  *         

+  *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

+  *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

+  *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

+  *             Other channels are slow channels (conversion rate: refer to reference manual).

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref ADC_CHANNEL_0

+  *         @arg @ref ADC_CHANNEL_1

+  *         @arg @ref ADC_CHANNEL_2

+  *         @arg @ref ADC_CHANNEL_3

+  *         @arg @ref ADC_CHANNEL_4

+  *         @arg @ref ADC_CHANNEL_5

+  *         @arg @ref ADC_CHANNEL_6

+  *         @arg @ref ADC_CHANNEL_7

+  *         @arg @ref ADC_CHANNEL_8

+  *         @arg @ref ADC_CHANNEL_9

+  *         @arg @ref ADC_CHANNEL_10

+  *         @arg @ref ADC_CHANNEL_11

+  *         @arg @ref ADC_CHANNEL_12

+  *         @arg @ref ADC_CHANNEL_13

+  *         @arg @ref ADC_CHANNEL_14

+  *         @arg @ref ADC_CHANNEL_15

+  *         @arg @ref ADC_CHANNEL_16

+  *         @arg @ref ADC_CHANNEL_17

+  *         @arg @ref ADC_CHANNEL_18

+  */

+#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                    \

+  __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))

+

+/**

+  * @brief  Helper macro to determine whether the internal channel

+  *         selected is available on the ADC instance selected.

+  * @note   The channel parameter must be a value defined from parameter

+  *         definition of a ADC internal channel (ADC_CHANNEL_VREFINT,

+  *         ADC_CHANNEL_TEMPSENSOR, ...),

+  *         must not be a value defined from parameter definition of

+  *         ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...)

+  *         or a value from functions where a channel number is

+  *         returned from ADC registers,

+  *         because internal and external channels share the same channel

+  *         number in ADC registers. The differentiation is made only with

+  *         parameters definitions of driver.

+  * @param  __ADC_INSTANCE__ ADC instance

+  * @param  __CHANNEL__ This parameter can be one of the following values:

+  *         @arg @ref ADC_CHANNEL_VREFINT      (1)

+  *         @arg @ref ADC_CHANNEL_TEMPSENSOR   (1)

+  *         @arg @ref ADC_CHANNEL_VBAT         (1)

+  *         @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)

+  *         @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)

+  *         

+  *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

+  *         (2) On STM32H7, parameter available only on ADC instance: ADC2.

+  * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.

+  *         Value "1" if the internal channel selected is available on the ADC instance selected.

+  */

+#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \

+  __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))

+

+/**

+  * @brief  Helper macro to get the ADC multimode conversion data of ADC master

+  *         or ADC slave from raw value with both ADC conversion data concatenated.

+  * @note   This macro is intended to be used when multimode transfer by DMA

+  *         is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().

+  *         In this case the transferred data need to processed with this macro

+  *         to separate the conversion data of ADC master and ADC slave.

+  * @param  __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_MULTI_MASTER

+  *         @arg @ref LL_ADC_MULTI_SLAVE

+  * @param  __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF

+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF

+  */

+#define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__)  \

+  __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__))

+

+/**

+  * @brief  Helper macro to select the ADC common instance

+  *         to which is belonging the selected ADC instance.

+  * @note   ADC common register instance can be used for:

+  *         - Set parameters common to several ADC instances

+  *         - Multimode (for devices with several ADC instances)

+  *         Refer to functions having argument "ADCxy_COMMON" as parameter.

+  * @param  __ADCx__ ADC instance

+  * @retval ADC common register instance

+  */

+#define __HAL_ADC_COMMON_INSTANCE(__ADCx__)                                    \

+  __LL_ADC_COMMON_INSTANCE((__ADCx__))

+

+/**

+  * @brief  Helper macro to check if all ADC instances sharing the same

+  *         ADC common instance are disabled.

+  * @note   This check is required by functions with setting conditioned to

+  *         ADC state:

+  *         All ADC instances of the ADC common group must be disabled.

+  *         Refer to functions having argument "ADCxy_COMMON" as parameter.

+  * @note   On devices with only 1 ADC common instance, parameter of this macro

+  *         is useless and can be ignored (parameter kept for compatibility

+  *         with devices featuring several ADC common instances).

+  * @param  __ADCXY_COMMON__ ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @retval Value "0" if all ADC instances sharing the same ADC common instance

+  *         are disabled.

+  *         Value "1" if at least one ADC instance sharing the same ADC common instance

+  *         is enabled.

+  */

+#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \

+  __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))

+

+/**

+  * @brief  Helper macro to define the ADC conversion data full-scale digital

+  *         value corresponding to the selected ADC resolution.

+  * @note   ADC conversion data full-scale corresponds to voltage range

+  *         determined by analog voltage references Vref+ and Vref-

+  *         (refer to reference manual).

+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

+  *         @arg @ref ADC_RESOLUTION_16B

+  *         @arg @ref ADC_RESOLUTION_14B

+  *         @arg @ref ADC_RESOLUTION_12B

+  *         @arg @ref ADC_RESOLUTION_10B

+  *         @arg @ref ADC_RESOLUTION_8B

+  * @retval ADC conversion data full-scale digital value

+  */

+#define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \

+  __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))

+

+/**

+  * @brief  Helper macro to convert the ADC conversion data from

+  *         a resolution to another resolution.

+  * @param  __DATA__ ADC conversion data to be converted

+  * @param  __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted

+  *         This parameter can be one of the following values:

+  *         @arg @ref ADC_RESOLUTION_16B

+  *         @arg @ref ADC_RESOLUTION_14B

+  *         @arg @ref ADC_RESOLUTION_12B

+  *         @arg @ref ADC_RESOLUTION_10B

+  *         @arg @ref ADC_RESOLUTION_8B

+  * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion

+  *         This parameter can be one of the following values:

+  *         @arg @ref ADC_RESOLUTION_16B

+  *         @arg @ref ADC_RESOLUTION_14B

+  *         @arg @ref ADC_RESOLUTION_12B

+  *         @arg @ref ADC_RESOLUTION_10B

+  *         @arg @ref ADC_RESOLUTION_8B

+  * @retval ADC conversion data to the requested resolution

+  */

+#define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\

+                                          __ADC_RESOLUTION_CURRENT__,\

+                                          __ADC_RESOLUTION_TARGET__)            \

+  __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),                                  \

+                                   (__ADC_RESOLUTION_CURRENT__),                \

+                                   (__ADC_RESOLUTION_TARGET__))

+

+/**

+  * @brief  Helper macro to calculate the voltage (unit: mVolt)

+  *         corresponding to a ADC conversion data (unit: digital value).

+  * @note   Analog reference voltage (Vref+) must be either known from

+  *         user board environment or can be calculated using ADC measurement

+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().

+  * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)

+  * @param  __ADC_DATA__ ADC conversion data (resolution 12 bits)

+  *                       (unit: digital value).

+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

+  *         @arg @ref ADC_RESOLUTION_16B

+  *         @arg @ref ADC_RESOLUTION_14B

+  *         @arg @ref ADC_RESOLUTION_12B

+  *         @arg @ref ADC_RESOLUTION_10B

+  *         @arg @ref ADC_RESOLUTION_8B

+  * @retval ADC conversion data equivalent voltage value (unit: mVolt)

+  */

+#define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\

+                                       __ADC_DATA__,\

+                                       __ADC_RESOLUTION__)                     \

+  __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),                      \

+                                (__ADC_DATA__),                                \

+                                (__ADC_RESOLUTION__))

+

+/**

+  * @brief  Helper macro to calculate analog reference voltage (Vref+)

+  *         (unit: mVolt) from ADC conversion data of internal voltage

+  *         reference VrefInt.

+  * @note   Computation is using VrefInt calibration value

+  *         stored in system memory for each device during production.

+  * @note   This voltage depends on user board environment: voltage level

+  *         connected to pin Vref+.

+  *         On devices with small package, the pin Vref+ is not present

+  *         and internally bonded to pin Vdda.

+  * @note   On this STM32 serie, calibration data of internal voltage reference

+  *         VrefInt corresponds to a resolution of 12 bits,

+  *         this is the recommended ADC resolution to convert voltage of

+  *         internal voltage reference VrefInt.

+  *         Otherwise, this macro performs the processing to scale

+  *         ADC conversion data to 12 bits.

+  * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits)

+  *         of internal voltage reference VrefInt (unit: digital value).

+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

+  *         @arg @ref ADC_RESOLUTION_16B

+  *         @arg @ref ADC_RESOLUTION_14B

+  *         @arg @ref ADC_RESOLUTION_12B

+  *         @arg @ref ADC_RESOLUTION_10B

+  *         @arg @ref ADC_RESOLUTION_8B

+  * @retval Analog reference voltage (unit: mV)

+  */

+#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\

+                                          __ADC_RESOLUTION__)                  \

+  __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),                     \

+                                  (__ADC_RESOLUTION__))

+

+/**

+  * @brief  Helper macro to calculate the temperature (unit: degree Celsius)

+  *         from ADC conversion data of internal temperature sensor.

+  * @note   Computation is using temperature sensor calibration values

+  *         stored in system memory for each device during production.

+  * @note   Calculation formula:

+  *           Temperature = ((TS_ADC_DATA - TS_CAL1)

+  *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))

+  *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP

+  *           with TS_ADC_DATA = temperature sensor raw data measured by ADC

+  *                Avg_Slope = (TS_CAL2 - TS_CAL1)

+  *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)

+  *                TS_CAL1   = equivalent TS_ADC_DATA at temperature

+  *                            TEMP_DEGC_CAL1 (calibrated in factory)

+  *                TS_CAL2   = equivalent TS_ADC_DATA at temperature

+  *                            TEMP_DEGC_CAL2 (calibrated in factory)

+  *         Caution: Calculation relevancy under reserve that calibration

+  *                  parameters are correct (address and data).

+  *                  To calculate temperature using temperature sensor

+  *                  datasheet typical values (generic values less, therefore

+  *                  less accurate than calibrated values),

+  *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().

+  * @note   As calculation input, the analog reference voltage (Vref+) must be

+  *         defined as it impacts the ADC LSB equivalent voltage.

+  * @note   Analog reference voltage (Vref+) must be either known from

+  *         user board environment or can be calculated using ADC measurement

+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().

+  * @note   On this STM32 serie, calibration data of temperature sensor

+  *         corresponds to a resolution of 12 bits,

+  *         this is the recommended ADC resolution to convert voltage of

+  *         temperature sensor.

+  *         Otherwise, this macro performs the processing to scale

+  *         ADC conversion data to 12 bits.

+  * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit: mV)

+  * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal

+  *                                 temperature sensor (unit: digital value).

+  * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature

+  *                                 sensor voltage has been measured.

+  *         This parameter can be one of the following values:

+  *         @arg @ref ADC_RESOLUTION_16B

+  *         @arg @ref ADC_RESOLUTION_14B

+  *         @arg @ref ADC_RESOLUTION_12B

+  *         @arg @ref ADC_RESOLUTION_10B

+  *         @arg @ref ADC_RESOLUTION_8B

+  * @retval Temperature (unit: degree Celsius)

+  */

+#define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\

+                                   __TEMPSENSOR_ADC_DATA__,\

+                                   __ADC_RESOLUTION__)                         \

+  __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),                          \

+                            (__TEMPSENSOR_ADC_DATA__),                         \

+                            (__ADC_RESOLUTION__))

+

+/**

+  * @brief  Helper macro to calculate the temperature (unit: degree Celsius)

+  *         from ADC conversion data of internal temperature sensor.

+  * @note   Computation is using temperature sensor typical values

+  *         (refer to device datasheet).

+  * @note   Calculation formula:

+  *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)

+  *                         / Avg_Slope + CALx_TEMP

+  *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC

+  *                                   (unit: digital value)

+  *                Avg_Slope        = temperature sensor slope

+  *                                   (unit: uV/Degree Celsius)

+  *                TS_TYP_CALx_VOLT = temperature sensor digital value at

+  *                                   temperature CALx_TEMP (unit: mV)

+  *         Caution: Calculation relevancy under reserve the temperature sensor

+  *                  of the current device has characteristics in line with

+  *                  datasheet typical values.

+  *                  If temperature sensor calibration values are available on

+  *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),

+  *                  temperature calculation will be more accurate using

+  *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().

+  * @note   As calculation input, the analog reference voltage (Vref+) must be

+  *         defined as it impacts the ADC LSB equivalent voltage.

+  * @note   Analog reference voltage (Vref+) must be either known from

+  *         user board environment or can be calculated using ADC measurement

+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().

+  * @note   ADC measurement data must correspond to a resolution of 12bits

+  *         (full scale digital value 4095). If not the case, the data must be

+  *         preliminarily rescaled to an equivalent resolution of 12 bits.

+  * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).

+  *                                       On STM32H7, refer to device datasheet parameter "Avg_Slope".

+  * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).

+  *                                       On STM32H7, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).

+  * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)

+  * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit: mV)

+  * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit: digital value).

+  * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.

+  *         This parameter can be one of the following values:

+  *         @arg @ref ADC_RESOLUTION_16B

+  *         @arg @ref ADC_RESOLUTION_14B

+  *         @arg @ref ADC_RESOLUTION_12B

+  *         @arg @ref ADC_RESOLUTION_10B

+  *         @arg @ref ADC_RESOLUTION_8B

+  * @retval Temperature (unit: degree Celsius)

+  */

+#define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\

+                                              __TEMPSENSOR_TYP_CALX_V__,\

+                                              __TEMPSENSOR_CALX_TEMP__,\

+                                              __VREFANALOG_VOLTAGE__,\

+                                              __TEMPSENSOR_ADC_DATA__,\

+                                              __ADC_RESOLUTION__)              \

+  __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),          \

+                                      (__TEMPSENSOR_TYP_CALX_V__),             \

+                                      (__TEMPSENSOR_CALX_TEMP__),              \

+                                      (__VREFANALOG_VOLTAGE__),                \

+                                      (__TEMPSENSOR_ADC_DATA__),               \

+                                      (__ADC_RESOLUTION__))

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Include ADC HAL Extended module */

+#include "stm32h7xx_hal_adc_ex.h"

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup ADC_Exported_Functions

+  * @{

+  */

+

+/** @addtogroup ADC_Exported_Functions_Group1

+  * @brief    Initialization and Configuration functions

+  * @{

+  */

+/* Initialization and de-initialization functions  ****************************/

+HAL_StatusTypeDef       HAL_ADC_Init(ADC_HandleTypeDef *hadc);

+HAL_StatusTypeDef       HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);

+void                    HAL_ADC_MspInit(ADC_HandleTypeDef *hadc);

+void                    HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc);

+

+#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)

+/* Callbacks Register/UnRegister functions  ***********************************/

+HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,

+                                           pADC_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);

+#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/** @addtogroup ADC_Exported_Functions_Group2

+  * @brief    IO operation functions

+  * @{

+  */

+/* IO operation functions  *****************************************************/

+

+/* Blocking mode: Polling */

+HAL_StatusTypeDef       HAL_ADC_Start(ADC_HandleTypeDef *hadc);

+HAL_StatusTypeDef       HAL_ADC_Stop(ADC_HandleTypeDef *hadc);

+HAL_StatusTypeDef       HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);

+HAL_StatusTypeDef       HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout);

+

+/* Non-blocking mode: Interruption */

+HAL_StatusTypeDef       HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc);

+HAL_StatusTypeDef       HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc);

+

+/* Non-blocking mode: DMA */

+HAL_StatusTypeDef       HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);

+HAL_StatusTypeDef       HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);

+

+/* ADC retrieve conversion value intended to be used with polling or interruption */

+uint32_t                HAL_ADC_GetValue(ADC_HandleTypeDef *hadc);

+

+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */

+void                    HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);

+void                    HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc);

+void                    HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc);

+void                    HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc);

+void                    HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);

+/**

+  * @}

+  */

+

+/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions

+  *  @brief    Peripheral Control functions

+  * @{

+  */

+/* Peripheral Control functions ***********************************************/

+HAL_StatusTypeDef       HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig);

+HAL_StatusTypeDef       HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig);

+

+/**

+  * @}

+  */

+

+/* Peripheral State functions *************************************************/

+/** @addtogroup ADC_Exported_Functions_Group4

+  * @{

+  */

+uint32_t                HAL_ADC_GetState(ADC_HandleTypeDef *hadc);

+uint32_t                HAL_ADC_GetError(ADC_HandleTypeDef *hadc);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private functions -----------------------------------------------------------*/

+/** @addtogroup ADC_Private_Functions ADC Private Functions

+  * @{

+  */

+HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup);

+HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc);

+HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc);

+void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);

+void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);

+void ADC_DMAError(DMA_HandleTypeDef *hdma);

+void ADC_ConfigureBoostMode(ADC_HandleTypeDef* hadc);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+

+#endif /* STM32H7xx_HAL_ADC_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_adc_ex.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_adc_ex.h
new file mode 100644
index 0000000000..4d2a29aa26
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_adc_ex.h
@@ -0,0 +1,1242 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_adc_ex.h

+  * @author  MCD Application Team

+  * @brief   Header file of ADC HAL extended module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_ADC_EX_H

+#define STM32H7xx_HAL_ADC_EX_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup ADCEx

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types

+  * @{

+  */

+

+/**

+  * @brief  ADC Injected Conversion Oversampling structure definition

+  */

+typedef struct

+{

+  uint32_t Ratio;                         /*!< Configures the oversampling ratio.

+                                               This parameter can be a value between 1 and 1024 */

+

+  uint32_t RightBitShift;                 /*!< Configures the division coefficient for the Oversampler.

+                                               This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */

+} ADC_InjOversamplingTypeDef;

+

+/**

+  * @brief  Structure definition of ADC group injected and ADC channel affected to ADC group injected

+  * @note   Parameters of this structure are shared within 2 scopes:

+  *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset

+  *          - Scope ADC group injected (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,

+  *            AutoInjectedConv, QueueInjectedContext, ExternalTrigInjecConv, ExternalTrigInjecConvEdge, InjecOversamplingMode, InjecOversampling.

+  * @note   The setting of these parameters by function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.

+  *         ADC state can be either:

+  *          - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')

+  *          - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group.

+  *          - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.

+  *          - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going

+  *            on ADC groups regular and injected.

+  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed

+  *         without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).

+  */

+typedef struct

+{

+  uint32_t InjectedChannel;               /*!< Specifies the channel to configure into ADC group injected.

+                                               This parameter can be a value of @ref ADC_HAL_EC_CHANNEL

+                                               Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */

+

+  uint32_t InjectedRank;                  /*!< Specifies the rank in the ADC group injected sequencer.

+                                               This parameter must be a value of @ref ADC_INJ_SEQ_RANKS.

+                                               Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by

+                                               the new channel setting (or parameter number of conversions adjusted) */

+

+  uint32_t InjectedSamplingTime;          /*!< Sampling time value to be set for the selected channel.

+                                               Unit: ADC clock cycles.

+                                               Conversion time is the addition of sampling time and processing time

+                                               (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits).

+                                               This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME.

+                                               Caution: This parameter applies to a channel that can be used in a regular and/or injected group.

+                                                        It overwrites the last setting.

+                                               Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),

+                                                     sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)

+                                                     Refer to device datasheet for timings values. */

+

+  uint32_t InjectedSingleDiff;            /*!< Selection of single-ended or differential input.

+                                               In differential mode: Differential measurement is between the selected channel 'i' (positive input) and channel 'i+1' (negative input).

+                                               Only channel 'i' has to be configured, channel 'i+1' is configured automatically.

+                                               This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING.

+                                               Caution: This parameter applies to a channel that can be used in a regular and/or injected group.

+                                                        It overwrites the last setting.

+                                               Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.

+                                               Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.

+                                               Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).

+                                               If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case

+                                               of another parameter update on the fly) */

+

+  uint32_t InjectedOffsetNumber;          /*!< Selects the offset number.

+                                               This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB.

+                                               Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */

+

+  uint32_t InjectedOffset;                /*!< Defines the offset to be subtracted from the raw converted data.

+                                               Offset value must be a positive number.

+                                               Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number

+                                               between Min_Data = 0x000 and Max_Data = 0xFFF,  0x3FF, 0xFF or 0x3F respectively.

+                                               Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled

+                                               without continuous mode or external trigger that could launch a conversion). */

+

+  uint32_t InjectedOffsetRightShift;       /*!< Specifies whether the 1 bit Right-shift feature is used or not.

+                                                This parameter is applied only for 16-bit or 8-bit resolution.

+                                                This parameter can be set to ENABLE or DISABLE. */

+

+  FunctionalState InjectedOffsetSignedSaturation;      /*!< Specifies whether the Signed saturation feature is used or not.

+                                               This parameter is applied only for 16-bit or 8-bit resolution.

+                                               This parameter can be set to ENABLE or DISABLE. */

+  uint32_t InjectedLeftBitShift;          /*!< Configures the left shifting applied to the final result with or without oversampling.

+                                               This parameter can be a value of @ref ADCEx_Left_Bit_Shift */

+

+  uint32_t InjectedNbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer.

+                                               To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.

+                                               This parameter must be a number between Min_Data = 1 and Max_Data = 4.

+                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to

+                                                        configure a channel on injected group can impact the configuration of other channels previously set. */

+

+  FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence

+                                               (main sequence subdivided in successive parts).

+                                               Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.

+                                               Discontinuous mode can be enabled only if continuous mode is disabled.

+                                               This parameter can be set to ENABLE or DISABLE.

+                                               Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).

+                                               Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank).

+                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to

+                                                        configure a channel on injected group can impact the configuration of other channels previously set. */

+

+  FunctionalState AutoInjectedConv;       /*!< Enables or disables the selected ADC group injected automatic conversion after regular one

+                                               This parameter can be set to ENABLE or DISABLE.

+                                               Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)

+                                               Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START)

+                                               Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.

+                                                     To maintain JAUTO always enabled, DMA must be configured in circular mode.

+                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to

+                                                        configure a channel on injected group can impact the configuration of other channels previously set. */

+

+  FunctionalState QueueInjectedContext;   /*!< Specifies whether the context queue feature is enabled.

+                                               This parameter can be set to ENABLE or DISABLE.

+                                               If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a

+                                               new injected context is set when queue is full, error is triggered by interruption and through function

+                                               'HAL_ADCEx_InjectedQueueOverflowCallback'.

+                                               Caution: This feature request that the sequence is fully configured before injected conversion start.

+                                                        Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter.

+                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to

+                                                        configure a channel on injected group can impact the configuration of other channels previously set.

+                                               Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */

+

+  uint32_t ExternalTrigInjecConv;         /*!< Selects the external event used to trigger the conversion start of injected group.

+                                               If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled and software trigger is used instead.

+                                               This parameter can be a value of @ref ADC_injected_external_trigger_source.

+                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to

+                                                        configure a channel on injected group can impact the configuration of other channels previously set. */

+

+  uint32_t ExternalTrigInjecConvEdge;     /*!< Selects the external trigger edge of injected group.

+                                               This parameter can be a value of @ref ADC_injected_external_trigger_edge.

+                                               If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.

+                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to

+                                                        configure a channel on injected group can impact the configuration of other channels previously set. */

+

+  FunctionalState InjecOversamplingMode;         /*!< Specifies whether the oversampling feature is enabled or disabled.

+                                                      This parameter can be set to ENABLE or DISABLE.

+                                                      Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */

+

+  ADC_InjOversamplingTypeDef  InjecOversampling; /*!< Specifies the Oversampling parameters.

+                                                      Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled.

+                                                      Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */

+} ADC_InjectionConfTypeDef;

+

+/**

+  * @brief  Structure definition of ADC multimode

+  * @note   The setting of these parameters by function HAL_ADCEx_MultiModeConfigChannel() is conditioned by ADCs state (both Master and Slave ADCs).

+  *         Both Master and Slave ADCs must be disabled.

+  */

+typedef struct

+{

+  uint32_t Mode;              /*!< Configures the ADC to operate in independent or multimode.

+                                   This parameter can be a value of @ref ADC_HAL_EC_MULTI_MODE. */

+

+  uint32_t DualModeData;      /*!< Configures the Dual ADC Mode Data Format:

+                                   This parameter can be a value of @ref ADCEx_Dual_Mode_Data_Format */

+

+  uint32_t TwoSamplingDelay;  /*!< Configures the Delay between 2 sampling phases.

+                                   This parameter can be a value of @ref ADC_HAL_EC_MULTI_TWOSMP_DELAY.

+                                   Delay range depends on selected resolution:

+                                   from 1 to 9 clock cycles for 16 bits,

+                                   from 1 to 9 clock cycles for 14 bits

+                                   from 1 to 8 clock cycles for 12 bits

+                                   from 1 to 6 clock cycles for 10 bits

+                                   from 1 to 6 clock cycles for 8 bits     */

+} ADC_MultiModeTypeDef;

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+

+/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants

+  * @{

+  */

+

+/** @defgroup ADC_injected_external_trigger_source ADC group injected trigger source

+  * @{

+  */

+/* ADC group regular trigger sources for all ADC instances */

+#define ADC_INJECTED_SOFTWARE_START        (LL_ADC_INJ_TRIG_SOFTWARE)            /*!< Software triggers injected group conversion start */

+#define ADC_EXTERNALTRIGINJEC_T1_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO)       /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIGINJEC_T1_CC4       (LL_ADC_INJ_TRIG_EXT_TIM1_CH4)        /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIGINJEC_T2_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM2_TRGO)       /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIGINJEC_T2_CC1       (LL_ADC_INJ_TRIG_EXT_TIM2_CH1)        /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIGINJEC_T3_CC4       (LL_ADC_INJ_TRIG_EXT_TIM3_CH4)        /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIGINJEC_T4_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM4_TRGO)       /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIGINJEC_EXT_IT15     (LL_ADC_INJ_TRIG_EXT_EXTI_LINE15)     /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIGINJEC_T8_CC4       (LL_ADC_INJ_TRIG_EXT_TIM8_CH4)        /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIGINJEC_T1_TRGO2     (LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2)      /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIGINJEC_T8_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO)       /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIGINJEC_T8_TRGO2     (LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2)      /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIGINJEC_T3_CC3       (LL_ADC_INJ_TRIG_EXT_TIM3_CH3)        /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIGINJEC_T3_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM3_TRGO)       /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIGINJEC_T3_CC1       (LL_ADC_INJ_TRIG_EXT_TIM3_CH1)        /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIGINJEC_T6_TRGO      (LL_ADC_INJ_TRIG_EXT_TIM6_TRGO)       /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIGINJEC_T15_TRGO     (LL_ADC_INJ_TRIG_EXT_TIM15_TRGO)      /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG2  (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2)      /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG2 event. Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIGINJEC_HR1_ADCTRG4  (LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4)      /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG4 event. Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIGINJEC_LPTIM1_OUT   (LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT)      /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIGINJEC_LPTIM2_OUT   (LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT)      /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */

+#define ADC_EXTERNALTRIGINJEC_LPTIM3_OUT   (LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT)      /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. Trigger edge set to rising edge (default setting). */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected)

+  * @{

+  */

+#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE           (0x00000000UL)        /*!< Injected conversions hardware trigger detection disabled                             */

+#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING         (ADC_JSQR_JEXTEN_0)   /*!< Injected conversions hardware trigger detection on the rising edge                   */

+#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING        (ADC_JSQR_JEXTEN_1)   /*!< Injected conversions hardware trigger detection on the falling edge                  */

+#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING  (ADC_JSQR_JEXTEN)     /*!< Injected conversions hardware trigger detection on both the rising and falling edges */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING  Channel - Single or differential ending

+  * @{

+  */

+#define ADC_SINGLE_ENDED                (LL_ADC_SINGLE_ENDED)         /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */

+#define ADC_DIFFERENTIAL_ENDED          (LL_ADC_DIFFERENTIAL_ENDED)   /*!< ADC channel ending set to differential (literal also used to set calibration mode) */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_HAL_EC_OFFSET_NB  ADC instance - Offset number

+  * @{

+  */

+#define ADC_OFFSET_NONE              (ADC_OFFSET_4 + 1U) /*!< ADC offset disabled: no offset correction for the selected ADC channel */

+#define ADC_OFFSET_1                 (LL_ADC_OFFSET_1) /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */

+#define ADC_OFFSET_2                 (LL_ADC_OFFSET_2) /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */

+#define ADC_OFFSET_3                 (LL_ADC_OFFSET_3) /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */

+#define ADC_OFFSET_4                 (LL_ADC_OFFSET_4) /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_INJ_SEQ_RANKS  ADC group injected - Sequencer ranks

+  * @{

+  */

+#define ADC_INJECTED_RANK_1                (LL_ADC_INJ_RANK_1) /*!< ADC group injected sequencer rank 1 */

+#define ADC_INJECTED_RANK_2                (LL_ADC_INJ_RANK_2) /*!< ADC group injected sequencer rank 2 */

+#define ADC_INJECTED_RANK_3                (LL_ADC_INJ_RANK_3) /*!< ADC group injected sequencer rank 3 */

+#define ADC_INJECTED_RANK_4                (LL_ADC_INJ_RANK_4) /*!< ADC group injected sequencer rank 4 */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_HAL_EC_MULTI_MODE  Multimode - Mode

+  * @{

+  */

+#define ADC_MODE_INDEPENDENT               (LL_ADC_MULTI_INDEPENDENT)                                          /*!< ADC dual mode disabled (ADC independent mode) */

+#define ADC_DUALMODE_REGSIMULT             (LL_ADC_MULTI_DUAL_REG_SIMULT) /*!< ADC dual mode enabled: group regular simultaneous */

+#define ADC_DUALMODE_INTERL                (LL_ADC_MULTI_DUAL_REG_INTERL) /*!< ADC dual mode enabled: Combined group regular interleaved */

+#define ADC_DUALMODE_INJECSIMULT           (LL_ADC_MULTI_DUAL_INJ_SIMULT) /*!< ADC dual mode enabled: group injected simultaneous */

+#define ADC_DUALMODE_ALTERTRIG             (LL_ADC_MULTI_DUAL_INJ_ALTERN) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */

+#define ADC_DUALMODE_REGSIMULT_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */

+#define ADC_DUALMODE_REGSIMULT_ALTERTRIG   (LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */

+#define ADC_DUALMODE_REGINTERL_INJECSIMULT (LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */

+

+/** @defgroup ADCEx_Dual_Mode_Data_Format ADC Extended Dual Mode Data Formatting

+  * @{

+  */

+#define ADC_DUALMODEDATAFORMAT_DISABLED      (0x00000000UL)                       /*!< Dual ADC mode without data packing: ADCx_CDR and ADCx_CDR2 registers not used */

+#define ADC_DUALMODEDATAFORMAT_32_10_BITS    (ADC_CCR_DAMDF_1)                    /*!< Data formatting mode for 32 down to 10-bit resolution */

+#define ADC_DUALMODEDATAFORMAT_8_BITS        ((ADC_CCR_DAMDF_0 |ADC_CCR_DAMDF_1)) /*!< Data formatting mode for 8-bit resolution */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_HAL_EC_MULTI_TWOSMP_DELAY  Multimode - Delay between two sampling phases

+  * @{

+  */

+#define ADC_TWOSAMPLINGDELAY_1CYCLE        (LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5)   /*!< ADC multimode delay between two sampling phases: 1 ADC clock cycle */

+#define ADC_TWOSAMPLINGDELAY_2CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5)  /*!< ADC multimode delay between two sampling phases: 2 ADC clock cycles */

+#define ADC_TWOSAMPLINGDELAY_3CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5)  /*!< ADC multimode delay between two sampling phases: 3 ADC clock cycles */

+#define ADC_TWOSAMPLINGDELAY_4CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5)  /*!< ADC multimode delay between two sampling phases: 4 ADC clock cycles */

+#define ADC_TWOSAMPLINGDELAY_5CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5)  /*!< ADC multimode delay between two sampling phases: 5 ADC clock cycles */

+#define ADC_TWOSAMPLINGDELAY_6CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5)  /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles */

+#define ADC_TWOSAMPLINGDELAY_7CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5)  /*!< ADC multimode delay between two sampling phases: 7 ADC clock cycles */

+#define ADC_TWOSAMPLINGDELAY_8CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES)   /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles */

+#define ADC_TWOSAMPLINGDELAY_9CYCLES       (LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES)   /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/** @defgroup ADC_HAL_EC_GROUPS  ADC instance - Groups

+  * @{

+  */

+#define ADC_REGULAR_GROUP                  (LL_ADC_GROUP_REGULAR)           /*!< ADC group regular (available on all STM32 devices) */

+#define ADC_INJECTED_GROUP                 (LL_ADC_GROUP_INJECTED)          /*!< ADC group injected (not available on all STM32 devices)*/

+#define ADC_REGULAR_INJECTED_GROUP         (LL_ADC_GROUP_REGULAR_INJECTED)  /*!< ADC both groups regular and injected */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_CFGR_fields ADCx CFGR fields

+  * @{

+  */

+#define ADC_CFGR_FIELDS    (ADC_CFGR_AWD1CH  | ADC_CFGR_JAUTO   | ADC_CFGR_JAWD1EN |\

+                            ADC_CFGR_AWD1EN  | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM     |\

+                            ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN  |\

+                            ADC_CFGR_AUTDLY  | ADC_CFGR_CONT    | ADC_CFGR_OVRMOD  |\

+                            ADC_CFGR_EXTEN   | ADC_CFGR_EXTSEL  | ADC_CFGR_ALIGN   |\

+                            ADC_CFGR_RES     | ADC_CFGR_DMACFG  | ADC_CFGR_DMAEN   )

+/**

+  * @}

+  */

+

+/** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields

+  * @{

+  */

+#define ADC_SMPR1_FIELDS    (ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7 |\

+                             ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4 |\

+                             ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1 |\

+                             ADC_SMPR1_SMP0)

+/**

+  * @}

+  */

+

+/** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields

+  * @{

+  */

+/* ADC_CFGR fields of parameters that can be updated when no conversion

+   (neither regular nor injected) is on-going  */

+#define ADC_CFGR_FIELDS_2  ((uint32_t)(ADC_CFGR_DMNGT | ADC_CFGR_AUTDLY))

+/**

+  * @}

+  */

+

+#if defined(DFSDM1_Channel0)

+/** @defgroup ADC_HAL_EC_REG_DFSDM_TRANSFER ADC group regular - DFSDM transfer of ADC conversion data

+  * @{

+  */

+#define ADC_DFSDM_MODE_DISABLE     (0x00000000UL)                     /*!< ADC conversions are not transferred by DFSDM. */

+#define ADC_DFSDM_MODE_ENABLE      (LL_ADC_REG_DFSDM_TRANSFER_ENABLE) /*!< ADC conversion data are transfered to DFSDM for post processing. The ADC conversion data format must be 16-bit signed and right aligned, refer to reference manual. DFSDM transfer cannot be used if DMA transfer is enabled. */

+/**

+  * @}

+  */

+#endif

+

+/**

+  * @}

+  */

+

+/* Exported macros -----------------------------------------------------------*/

+

+/** @defgroup ADCEx_Exported_Macro ADC Extended Exported Macros

+  * @{

+  */

+

+/** @brief  Force ADC instance in multimode mode independent (multimode disable).

+  * @note   This macro must be used only in case of transition from multimode

+  *         to mode independent and in case of unknown previous state,

+  *         to ensure ADC configuration is in mode independent.

+  * @note   Standard way of multimode configuration change is done from

+  *         HAL ADC handle of ADC master using function

+  *         "HAL_ADCEx_MultiModeConfigChannel(..., ADC_MODE_INDEPENDENT)" )".

+  *         Usage of this macro is not the Standard way of multimode

+  *         configuration and can lead to have HAL ADC handles status

+  *         misaligned. Usage of this macro must be limited to cases

+  *         mentionned above.

+  * @param __HANDLE__ ADC handle.

+  * @retval None

+  */

+#define ADC_FORCE_MODE_INDEPENDENT(__HANDLE__)                                 \

+  LL_ADC_SetMultimode(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance), LL_ADC_MULTI_INDEPENDENT)

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+

+/** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros

+  * @{

+  */

+/* Macro reserved for internal HAL driver usage, not intended to be used in   */

+/* code of final user.                                                        */

+

+/**

+  * @brief Test if conversion trigger of injected group is software start

+  *        or external trigger.

+  * @param __HANDLE__ ADC handle.

+  * @retval SET (software start) or RESET (external trigger).

+  */

+#define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                             \

+  (((__HANDLE__)->Instance->JSQR & ADC_JSQR_JEXTEN) == 0UL)

+

+/**

+  * @brief Check if conversion is on going on regular or injected groups.

+  * @param __HANDLE__ ADC handle.

+  * @retval SET (conversion is on going) or RESET (no conversion is on going).

+  */

+#define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__)                       \

+       (( (((__HANDLE__)->Instance->CR) & (ADC_CR_ADSTART | ADC_CR_JADSTART)) == 0UL \

+        ) ? RESET : SET)

+

+/**

+  * @brief Check if conversion is on going on injected group.

+  * @param __HANDLE__ ADC handle.

+  * @retval Value "0" (no conversion is on going) or value "1" (conversion is on going)

+  */

+#define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__)                         \

+  (LL_ADC_INJ_IsConversionOngoing((__HANDLE__)->Instance))

+

+/**

+  * @brief Check whether or not ADC is independent.

+  * @param __HANDLE__ ADC handle.

+  * @note  When multimode feature is not available, the macro always returns SET.

+  * @retval SET (ADC is independent) or RESET (ADC is not).

+  */

+#if defined (ADC3)

+#define ADC_IS_INDEPENDENT(__HANDLE__)    \

+  ( ( ( ((__HANDLE__)->Instance) == ADC3) \

+    )?                                    \

+     SET                                  \

+     :                                    \

+     RESET                                \

+  )

+#endif

+

+/**

+  * @brief Set the selected injected Channel rank.

+  * @param __CHANNELNB__ Channel number.

+  * @param __RANKNB__ Rank number.

+  * @retval None

+  */

+#define ADC_JSQR_RK(__CHANNELNB__, __RANKNB__) ((((__CHANNELNB__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << ((__RANKNB__) & ADC_INJ_RANK_ID_JSQR_MASK))

+

+/**

+  * @brief Configure ADC injected context queue

+  * @param __INJECT_CONTEXT_QUEUE_MODE__ Injected context queue mode.

+  * @retval None

+  */

+#define ADC_CFGR_INJECT_CONTEXT_QUEUE(__INJECT_CONTEXT_QUEUE_MODE__) ((__INJECT_CONTEXT_QUEUE_MODE__) << ADC_CFGR_JQM_Pos)

+

+/**

+  * @brief Configure ADC discontinuous conversion mode for injected group

+  * @param __INJECT_DISCONTINUOUS_MODE__ Injected discontinuous mode.

+  * @retval None

+  */

+#define ADC_CFGR_INJECT_DISCCONTINUOUS(__INJECT_DISCONTINUOUS_MODE__) ((__INJECT_DISCONTINUOUS_MODE__) <<  ADC_CFGR_JDISCEN_Pos)

+

+/**

+  * @brief Configure ADC discontinuous conversion mode for regular group

+  * @param __REG_DISCONTINUOUS_MODE__ Regular discontinuous mode.

+  * @retval None

+  */

+#define ADC_CFGR_REG_DISCONTINUOUS(__REG_DISCONTINUOUS_MODE__) ((__REG_DISCONTINUOUS_MODE__) << ADC_CFGR_DISCEN_Pos)

+

+/**

+  * @brief Configure the number of discontinuous conversions for regular group.

+  * @param __NBR_DISCONTINUOUS_CONV__ Number of discontinuous conversions.

+  * @retval None

+  */

+#define ADC_CFGR_DISCONTINUOUS_NUM(__NBR_DISCONTINUOUS_CONV__) (((__NBR_DISCONTINUOUS_CONV__) - 1UL) << ADC_CFGR_DISCNUM_Pos)

+

+/**

+  * @brief Configure the ADC auto delay mode.

+  * @param __AUTOWAIT__ Auto delay bit enable or disable.

+  * @retval None

+  */

+#define ADC_CFGR_AUTOWAIT(__AUTOWAIT__) ((__AUTOWAIT__) << ADC_CFGR_AUTDLY_Pos)

+

+/**

+  * @brief Configure ADC continuous conversion mode.

+  * @param __CONTINUOUS_MODE__ Continuous mode.

+  * @retval None

+  */

+#define ADC_CFGR_CONTINUOUS(__CONTINUOUS_MODE__) ((__CONTINUOUS_MODE__) << ADC_CFGR_CONT_Pos)

+

+/**

+  * @brief Enable the ADC DMA continuous request.

+  * @param __DMACONTREQ_MODE__: DMA continuous request mode.

+  * @retval None

+  */

+#define ADC_CFGR_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__))

+

+/**

+  * @brief Configure the channel number into offset OFRx register.

+  * @param __CHANNEL__ ADC Channel.

+  * @retval None

+  */

+#define ADC_OFR_CHANNEL(__CHANNEL__) ((__CHANNEL__) << ADC_OFR1_OFFSET1_CH_Pos)

+

+/**

+  * @brief Configure the channel number into differential mode selection register.

+  * @param __CHANNEL__ ADC Channel.

+  * @retval None

+  */

+#define ADC_DIFSEL_CHANNEL(__CHANNEL__) (1UL << (__CHANNEL__))

+

+/**

+  * @brief Configure calibration factor in differential mode to be set into calibration register.

+  * @param __CALIBRATION_FACTOR__ Calibration factor value.

+  * @retval None

+  */

+#define ADC_CALFACT_DIFF_SET(__CALIBRATION_FACTOR__) (((__CALIBRATION_FACTOR__) & (ADC_CALFACT_CALFACT_D_Pos >> ADC_CALFACT_CALFACT_D_Pos) ) << ADC_CALFACT_CALFACT_D_Pos)

+

+/**

+  * @brief Calibration factor in differential mode to be retrieved from calibration register.

+  * @param __CALIBRATION_FACTOR__ Calibration factor value.

+  * @retval None

+  */

+#define ADC_CALFACT_DIFF_GET(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) >> ADC_CALFACT_CALFACT_D_Pos)

+

+/**

+  * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.

+  * @param __THRESHOLD__ Threshold value.

+  * @retval None

+  */

+#define ADC_TRX_HIGHTHRESHOLD(__THRESHOLD__) ((__THRESHOLD__) << 16UL)

+

+/**

+  * @brief Configure the ADC DMA continuous request for ADC multimode.

+  * @param __DMACONTREQ_MODE__ DMA continuous request mode.

+  * @retval None

+  */

+#define ADC_CCR_MULTI_DMACONTREQ(__DMACONTREQ_MODE__) ((__DMACONTREQ_MODE__) << ADC_CCR_DMACFG_Pos)

+

+/**

+  * @brief Shift the offset in function of the selected ADC resolution.

+  * @note  Offset has to be left-aligned on bit 15, the LSB (right bits) are set to 0

+  *        If resolution 16 bits, no shift.

+  *        If resolution 14 bits, shift of 2 ranks on the left.

+  *        If resolution 12 bits, shift of 4 ranks on the left.

+  *        If resolution 10 bits, shift of 6 ranks on the left.

+  *        If resolution 8 bits, shift of 8 ranks on the left.

+  *        therefore, shift = (16 - resolution) = 16 - (16 - (((RES[2:0]) >> 2)*2))

+  * @param __HANDLE__: ADC handle

+  * @param __OFFSET__: Value to be shifted

+  * @retval None

+  */

+#if defined(ADC_VER_V5_3)

+#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__)                                                     \

+        (                                                                                                       \

+           ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL)                                           \

+              ? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL))                   \

+               :                                                                                                \

+               ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL))  \

+        )

+#else

+#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__)                                                     \

+        (((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL)                                                      \

+          ? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL))                       \

+             :                                                                                                  \

+            ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL)                                          \

+              ? ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL))                   \

+               :                                                                                                \

+               ((__OFFSET__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL))  \

+        )

+#endif /* ADC_VER_V5_3 */

+

+/**

+  * @brief Shift the AWD1 threshold in function of the selected ADC resolution.

+  * @note  Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0.

+  *        If resolution 16 bits, no shift.

+  *        If resolution 14 bits, shift of 2 ranks on the left.

+  *        If resolution 12 bits, shift of 4 ranks on the left.

+  *        If resolution 10 bits, shift of 6 ranks on the left.

+  *        If resolution 8 bits, shift of 8 ranks on the left.

+  *        therefore, shift = (16 - resolution) = 16 - (16- (((RES[2:0]) >> 2)*2))

+  * @param __HANDLE__: ADC handle

+  * @param __THRESHOLD__: Value to be shifted

+  * @retval None

+  */

+#if defined(ADC_VER_V5_3)

+#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__)                                             \

+        (                                                                                                         \

+           ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL)                                             \

+            ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL))                    \

+              :                                                                                                   \

+              ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL))  \

+        )

+#else

+#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__)                                             \

+        (((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL)                                                        \

+         ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL))                       \

+            :                                                                                                     \

+           ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL)                                             \

+            ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL))                    \

+              :                                                                                                   \

+              ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL))  \

+        )

+#endif /* ADC_VER_V5_3 */

+

+/**

+  * @brief Shift the AWD2 and AWD3 threshold in function of the selected ADC resolution.

+  * @note  Thresholds have to be left-aligned on bit 15, the LSB (right bits) are set to 0.

+  *        If resolution 16 bits, no shift.

+  *        If resolution 14 bits, shift of 2 ranks on the left.

+  *        If resolution 12 bits, shift of 4 ranks on the left.

+  *        If resolution 10 bits, shift of 6 ranks on the left.

+  *        If resolution 8 bits, shift of 8 ranks on the left.

+  *        therefore, shift = (16 - resolution) = 16 - (16- (((RES[2:0]) >> 2)*2))

+  * @param __HANDLE__: ADC handle

+  * @param __THRESHOLD__: Value to be shifted

+  * @retval None

+  */

+#if defined(ADC_VER_V5_3)

+#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__)                                              \

+        (                                                                                                           \

+            ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL)                                              \

+              ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL))                    \

+                :                                                                                                   \

+                ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL))  \

+        )

+#else

+#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__)                                              \

+        (((DBGMCU->IDCODE & 0xF0000000UL) == 0x10000000UL)                                                          \

+          ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL))                        \

+            :                                                                                                       \

+            ((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES_2) == 0UL)                                              \

+              ? ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)>> 2UL)*2UL))                    \

+                :                                                                                                   \

+                ((__THRESHOLD__)<<(((((__HANDLE__)->Instance->CFGR) & (ADC_CFGR_RES & 0xFFFFFFF3UL))>> 2UL )*2UL))  \

+        )

+#endif /* ADC_VER_V5_3 */

+/**

+  * @brief Clear Common Control Register.

+  * @param __HANDLE__ ADC handle.

+  * @retval None

+  */

+/**

+  * @brief Report common register to ADC1 and ADC2

+  * @param __HANDLE__: ADC handle

+  * @retval Common control register

+  */

+#define ADC12_COMMON_REGISTER(__HANDLE__)   (ADC12_COMMON)

+#if defined (ADC3)

+/**

+  * @brief Report common register to ADC3

+  * @param __HANDLE__: ADC handle

+  * @retval Common control register

+  */

+#define ADC3_COMMON_REGISTER(__HANDLE__)   (ADC3_COMMON)

+#endif

+/**

+  * @brief Report Master Instance

+  * @param __HANDLE__: ADC handle

+  * @note return same instance if ADC of input handle is independent ADC

+  * @retval Master Instance

+  */

+#if defined (ADC3)

+#define ADC_MASTER_REGISTER(__HANDLE__)                                          \

+  ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC3)) \

+    )?                                                                           \

+     ((__HANDLE__)->Instance)                                                    \

+     :                                                                           \

+     (ADC1)                                                                      \

+  )

+#else

+#define ADC_MASTER_REGISTER(__HANDLE__) ( (ADC1))

+#endif

+

+/**

+  * @brief Check whether or not dual regular conversions are enabled

+  * @param __HANDLE__: ADC handle

+  * @retval SET (dual regular conversions are enabled) or RESET (ADC is independent or no dual regular conversions are enabled)

+  */

+#define ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(__HANDLE__)                        \

+  ( ( ((((__HANDLE__)->Instance) == ADC1) || (((__HANDLE__)->Instance) == ADC2)) \

+    )?                                                                           \

+     ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_MODE_INDEPENDENT)     &&      \

+       ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_INJECSIMULT) &&      \

+       ((ADC12_COMMON->CCR & ADC_CCR_DUAL) != ADC_DUALMODE_ALTERTRIG) )         \

+     :                                                                           \

+     RESET                                                                       \

+  )

+

+/**

+  * @brief Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master

+  * @param __HANDLE__: ADC handle

+  * @retval SET (non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode)

+  */

+#define ADC12_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__)                        \

+  ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC2)     \

+    )?                                                                         \

+     SET                                                                       \

+     :                                                                         \

+     ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == RESET)                            \

+  )

+#if defined (ADC3)

+/**

+  * @brief Verification of condition for ADC start conversion: ADC must be in non-MultiMode or MultiMode with handle of ADC master

+  * @param __HANDLE__: ADC handle

+  * @retval SET (non-MultiMode or Master handle) or RESET (handle of Slave ADC in MultiMode)

+  */

+#define ADC3_NONMULTIMODE_OR_MULTIMODEMASTER(__HANDLE__)                        \

+  ( ( ((__HANDLE__)->Instance == ADC3)                                          \

+    )?                                                                         \

+     SET                                                                       \

+     :                                                                         \

+     ((ADC3_COMMON->CCR & ADC_CCR_DUAL) == RESET)                            \

+  )

+#endif

+/**

+  * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual regular conversions enabled

+  * @param __HANDLE__: ADC handle

+  * @retval SET (Independent or Master, or Slave without dual regular conversions enabled) or RESET (Slave ADC with dual regular conversions enabled)

+  */

+#if defined (ADC3)

+#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__)            \

+  ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3)  \

+    )?                                                                      \

+     SET                                                                    \

+     :                                                                      \

+     ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT)     || \

+       ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \

+       ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))

+#else

+#define ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(__HANDLE__)            \

+  ( ( ((__HANDLE__)->Instance == ADC1)                                      \

+    )?                                                                      \

+     SET                                                                    \

+     :                                                                      \

+     ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT)     || \

+       ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INJECSIMULT) || \

+       ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_ALTERTRIG) ))

+#endif

+

+/**

+  * @brief Ensure ADC Instance is Independent or Master, or is not Slave ADC with dual injected conversions enabled

+  * @param __HANDLE__: ADC handle

+  * @retval SET (non-MultiMode or Master, or Slave without dual injected conversions enabled) or RESET (Slave ADC with dual injected conversions enabled)

+  */

+#if defined (ADC3)

+#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__)         \

+  ( ( ((__HANDLE__)->Instance == ADC1) || ((__HANDLE__)->Instance == ADC3) \

+    )?                                                                     \

+     SET                                                                   \

+     :                                                                     \

+     ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT)    || \

+       ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT)  || \

+       ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))

+#else

+#define ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(__HANDLE__)         \

+  ( ( ((__HANDLE__)->Instance == ADC1)                                    \

+    )?                                                                     \

+     SET                                                                   \

+     :                                                                     \

+     ( ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_MODE_INDEPENDENT)    || \

+       ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_REGSIMULT)  || \

+       ((ADC12_COMMON->CCR & ADC_CCR_DUAL) == ADC_DUALMODE_INTERL) ))

+#endif

+

+#define ADC_CLEAR_COMMON_CONTROL_REGISTER(__HANDLE__) CLEAR_BIT(__LL_ADC_COMMON_INSTANCE((__HANDLE__)->Instance)->CCR, ADC_CCR_CKMODE    | \

+                                                                                                      ADC_CCR_PRESC     | \

+                                                                                                      ADC_CCR_VBATEN    | \

+                                                                                                      ADC_CCR_TSEN      | \

+                                                                                                      ADC_CCR_VREFEN    | \

+                                                                                                      ADC_CCR_DAMDF     | \

+                                                                                                      ADC_CCR_DELAY     | \

+                                                                                                      ADC_CCR_DUAL  )

+

+/**

+  * @brief Set handle instance of the ADC slave associated to the ADC master.

+  * @param __HANDLE_MASTER__ ADC master handle.

+  * @param __HANDLE_SLAVE__ ADC slave handle.

+  * @note if __HANDLE_MASTER__ is the handle of a slave ADC (ADC2) or an independent ADC, __HANDLE_SLAVE__ instance is set to NULL.

+  * @retval None

+  */

+#define ADC_MULTI_SLAVE(__HANDLE_MASTER__, __HANDLE_SLAVE__)             \

+  ( (((__HANDLE_MASTER__)->Instance == ADC1)) ? ((__HANDLE_SLAVE__)->Instance = ADC2) : ((__HANDLE_SLAVE__)->Instance = NULL) )

+

+

+/**

+  * @brief Verify the ADC instance connected to the temperature sensor.

+  * @param __HANDLE__ ADC handle.

+  * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)

+  */

+#if defined(ADC3)

+#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC3)

+#else

+#define ADC_TEMPERATURE_SENSOR_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC2)

+#endif

+

+/**

+  * @brief Verify the ADC instance connected to the battery voltage VBAT.

+  * @param __HANDLE__ ADC handle.

+  * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)

+  */

+#if defined(ADC3)

+#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC3)

+#else

+#define ADC_BATTERY_VOLTAGE_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC2)

+#endif

+

+/**

+  * @brief Verify the ADC instance connected to the internal voltage reference VREFINT.

+  * @param __HANDLE__ ADC handle.

+  * @retval SET (ADC instance is valid) or RESET (ADC instance is invalid)

+  */

+#if defined(ADC3)

+#define ADC_VREFINT_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC3)

+#else

+#define ADC_VREFINT_INSTANCE(__HANDLE__)  (((__HANDLE__)->Instance) == ADC2)

+#endif

+

+/**

+  * @brief Verify the length of scheduled injected conversions group.

+  * @param __LENGTH__ number of programmed conversions.

+  * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large)

+  */

+#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))

+

+/**

+  * @brief Calibration factor size verification (7 bits maximum).

+  * @param __CALIBRATION_FACTOR__ Calibration factor value.

+  * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large)

+  */

+#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU))

+

+

+/**

+  * @brief Verify the ADC channel setting.

+  * @param __CHANNEL__ programmed ADC channel.

+  * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)

+  */

+#define IS_ADC_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_0)           || \

+                                     ((__CHANNEL__) == ADC_CHANNEL_1)           || \

+                                     ((__CHANNEL__) == ADC_CHANNEL_2)           || \

+                                     ((__CHANNEL__) == ADC_CHANNEL_3)           || \

+                                     ((__CHANNEL__) == ADC_CHANNEL_4)           || \

+                                     ((__CHANNEL__) == ADC_CHANNEL_5)           || \

+                                     ((__CHANNEL__) == ADC_CHANNEL_6)           || \

+                                     ((__CHANNEL__) == ADC_CHANNEL_7)           || \

+                                     ((__CHANNEL__) == ADC_CHANNEL_8)           || \

+                                     ((__CHANNEL__) == ADC_CHANNEL_9)           || \

+                                     ((__CHANNEL__) == ADC_CHANNEL_10)          || \

+                                     ((__CHANNEL__) == ADC_CHANNEL_11)          || \

+                                     ((__CHANNEL__) == ADC_CHANNEL_12)          || \

+                                     ((__CHANNEL__) == ADC_CHANNEL_13)          || \

+                                     ((__CHANNEL__) == ADC_CHANNEL_14)          || \

+                                     ((__CHANNEL__) == ADC_CHANNEL_15)          || \

+                                     ((__CHANNEL__) == ADC_CHANNEL_16)          || \

+                                     ((__CHANNEL__) == ADC_CHANNEL_17)          || \

+                                     ((__CHANNEL__) == ADC_CHANNEL_18)          || \

+                                     ((__CHANNEL__) == ADC_CHANNEL_19)          || \

+                                     ((__CHANNEL__) == ADC_CHANNEL_TEMPSENSOR)  || \

+                                     ((__CHANNEL__) == ADC_CHANNEL_VBAT)        || \

+                                     ((__CHANNEL__) == ADC_CHANNEL_DAC1CH1_ADC2)|| \

+                                     ((__CHANNEL__) == ADC_CHANNEL_DAC1CH2_ADC2)|| \

+                                     ((__CHANNEL__) == ADC_CHANNEL_VREFINT)       )

+

+/**

+  * @brief Verify the ADC channel setting in differential mode for ADC1.

+  * @param __CHANNEL__: programmed ADC channel.

+  * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)

+  */

+#define IS_ADC1_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1)      || \

+                                           ((__CHANNEL__) == ADC_CHANNEL_2)      ||\

+                                           ((__CHANNEL__) == ADC_CHANNEL_3)      ||\

+                                           ((__CHANNEL__) == ADC_CHANNEL_4)      ||\

+                                           ((__CHANNEL__) == ADC_CHANNEL_5)      ||\

+                                           ((__CHANNEL__) == ADC_CHANNEL_10)     ||\

+                                           ((__CHANNEL__) == ADC_CHANNEL_11)     ||\

+                                           ((__CHANNEL__) == ADC_CHANNEL_12)     ||\

+                                           ((__CHANNEL__) == ADC_CHANNEL_16)     ||\

+                                           ((__CHANNEL__) == ADC_CHANNEL_18)      )

+

+/**

+  * @brief Verify the ADC channel setting in differential mode for ADC2.

+  * @param __CHANNEL__: programmed ADC channel.

+  * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)

+  */

+#define IS_ADC2_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1)      || \

+                                           ((__CHANNEL__) == ADC_CHANNEL_2)      || \

+                                           ((__CHANNEL__) == ADC_CHANNEL_3)      || \

+                                           ((__CHANNEL__) == ADC_CHANNEL_4)      || \

+                                           ((__CHANNEL__) == ADC_CHANNEL_5)      || \

+                                           ((__CHANNEL__) == ADC_CHANNEL_10)     || \

+                                           ((__CHANNEL__) == ADC_CHANNEL_11)     || \

+                                           ((__CHANNEL__) == ADC_CHANNEL_12)     || \

+                                           ((__CHANNEL__) == ADC_CHANNEL_18)      )

+

+/**

+  * @brief Verify the ADC channel setting in differential mode for ADC3.

+  * @param __CHANNEL__: programmed ADC channel.

+  * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)

+  */

+#define IS_ADC3_DIFF_CHANNEL(__CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1)      || \

+                                           ((__CHANNEL__) == ADC_CHANNEL_2)      || \

+                                           ((__CHANNEL__) == ADC_CHANNEL_3)      || \

+                                           ((__CHANNEL__) == ADC_CHANNEL_4)      || \

+                                           ((__CHANNEL__) == ADC_CHANNEL_5)      || \

+                                           ((__CHANNEL__) == ADC_CHANNEL_10)     || \

+                                           ((__CHANNEL__) == ADC_CHANNEL_11)     || \

+                                           ((__CHANNEL__) == ADC_CHANNEL_13)     || \

+                                           ((__CHANNEL__) == ADC_CHANNEL_14)     || \

+                                           ((__CHANNEL__) == ADC_CHANNEL_15)       )

+

+/**

+  * @brief Verify the ADC single-ended input or differential mode setting.

+  * @param __SING_DIFF__ programmed channel setting.

+  * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)

+  */

+#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED)      || \

+                                                   ((__SING_DIFF__) == ADC_DIFFERENTIAL_ENDED)  )

+

+/**

+  * @brief Verify the ADC offset management setting.

+  * @param __OFFSET_NUMBER__ ADC offset management.

+  * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid)

+  */

+#define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \

+                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_1)    || \

+                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_2)    || \

+                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_3)    || \

+                                                 ((__OFFSET_NUMBER__) == ADC_OFFSET_4)      )

+

+/**

+  * @brief Verify the ADC injected channel setting.

+  * @param __CHANNEL__ programmed ADC injected channel.

+  * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)

+  */

+#define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \

+                                           ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \

+                                           ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \

+                                           ((__CHANNEL__) == ADC_INJECTED_RANK_4)   )

+

+/**

+  * @brief Verify the ADC injected conversions external trigger.

+  * @param __INJTRIG__ programmed ADC injected conversions external trigger.

+  * @retval SET (__INJTRIG__ is a valid value) or RESET (__INJTRIG__ is invalid)

+  */

+#define IS_ADC_EXTTRIGINJEC(__INJTRIG__) (((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO)     || \

+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_CC4)      || \

+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_TRGO)     || \

+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T2_CC1)      || \

+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC4)      || \

+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T4_TRGO)     || \

+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_EXT_IT15)    || \

+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_CC4)      || \

+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T1_TRGO2)    || \

+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO)     || \

+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T8_TRGO2)    || \

+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC3)      || \

+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_TRGO)     || \

+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T3_CC1)      || \

+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T6_TRGO)     || \

+                                          ((__INJTRIG__) == ADC_EXTERNALTRIGINJEC_T15_TRGO)    || \

+                                                                                          \

+                                           ((__INJTRIG__) == ADC_SOFTWARE_START)                   )

+

+/**

+  * @brief Verify the ADC edge trigger setting for injected group.

+  * @param __EDGE__ programmed ADC edge trigger setting.

+  * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)

+  */

+#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)         || \

+                                            ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)       || \

+                                            ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING)      || \

+                                            ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )

+

+/**

+  * @brief Verify the ADC multimode setting.

+  * @param __MODE__ programmed ADC multimode setting.

+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

+  */

+#define IS_ADC_MULTIMODE(__MODE__) (((__MODE__) == ADC_MODE_INDEPENDENT)               || \

+                                    ((__MODE__) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \

+                                    ((__MODE__) == ADC_DUALMODE_REGSIMULT_ALTERTRIG)   || \

+                                    ((__MODE__) == ADC_DUALMODE_REGINTERL_INJECSIMULT) || \

+                                    ((__MODE__) == ADC_DUALMODE_INJECSIMULT)           || \

+                                    ((__MODE__) == ADC_DUALMODE_REGSIMULT)             || \

+                                    ((__MODE__) == ADC_DUALMODE_INTERL)                || \

+                                    ((__MODE__) == ADC_DUALMODE_ALTERTRIG)               )

+

+/**

+  * @brief Verify the ADC dual data mode setting.

+  * @param MODE: programmed ADC dual mode setting.

+  * @retval SET (MODE is valid) or RESET (MODE is invalid)

+  */

+#define IS_ADC_DUAL_DATA_MODE(MODE) (((MODE) == ADC_DUALMODEDATAFORMAT_DISABLED)   || \

+                                     ((MODE) == ADC_DUALMODEDATAFORMAT_32_10_BITS) || \

+                                     ((MODE) == ADC_DUALMODEDATAFORMAT_8_BITS)     )

+

+/**

+  * @brief Verify the ADC multimode delay setting.

+  * @param __DELAY__ programmed ADC multimode delay setting.

+  * @retval SET (__DELAY__ is a valid value) or RESET (__DELAY__ is invalid)

+  */

+#define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_1CYCLE)   || \

+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_2CYCLES)  || \

+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_3CYCLES)  || \

+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_4CYCLES)  || \

+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES)  || \

+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES)  || \

+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES)  || \

+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES)  || \

+                                          ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES)    )

+

+/**

+  * @brief Verify the ADC analog watchdog setting.

+  * @param __WATCHDOG__ programmed ADC analog watchdog setting.

+  * @retval SET (__WATCHDOG__ is valid) or RESET (__WATCHDOG__ is invalid)

+  */

+#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \

+                                                     ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \

+                                                     ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3)   )

+

+/**

+  * @brief Verify the ADC analog watchdog mode setting.

+  * @param __WATCHDOG_MODE__ programmed ADC analog watchdog mode setting.

+  * @retval SET (__WATCHDOG_MODE__ is valid) or RESET (__WATCHDOG_MODE__ is invalid)

+  */

+#define IS_ADC_ANALOG_WATCHDOG_MODE(__WATCHDOG_MODE__) (((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_NONE)             || \

+                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REG)       || \

+                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)     || \

+                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  || \

+                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG)          || \

+                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC)        || \

+                                                        ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)       )

+

+/**

+  * @brief Verify the ADC conversion (regular or injected or both).

+  * @param __CONVERSION__ ADC conversion group.

+  * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)

+  */

+#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP)         || \

+                                                 ((__CONVERSION__) == ADC_INJECTED_GROUP)        || \

+                                                 ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP)  )

+

+/**

+  * @brief Verify the ADC event type.

+  * @param __EVENT__ ADC event.

+  * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)

+  */

+#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT)  || \

+                                      ((__EVENT__) == ADC_AWD_EVENT)    || \

+                                      ((__EVENT__) == ADC_AWD2_EVENT)   || \

+                                      ((__EVENT__) == ADC_AWD3_EVENT)   || \

+                                      ((__EVENT__) == ADC_OVR_EVENT)    || \

+                                      ((__EVENT__) == ADC_JQOVF_EVENT)  )

+

+/**

+  * @brief Verify the ADC oversampling ratio.

+  * @param RATIO: programmed ADC oversampling ratio.

+  * @retval SET (RATIO is a valid value) or RESET (RATIO is invalid)

+  */

+#define IS_ADC_OVERSAMPLING_RATIO(RATIO)  (((RATIO) >= 1UL) && ((RATIO) <= 1024UL))

+

+/**

+  * @brief Verify the ADC oversampling shift.

+  * @param __SHIFT__ programmed ADC oversampling shift.

+  * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)

+  */

+#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__)        (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \

+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_1   ) || \

+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_2   ) || \

+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_3   ) || \

+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_4   ) || \

+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_5   ) || \

+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_6   ) || \

+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_7   ) || \

+                                                  ((__SHIFT__) == ADC_RIGHTBITSHIFT_8   ))

+

+/**

+  * @brief Verify the ADC oversampling triggered mode.

+  * @param __MODE__ programmed ADC oversampling triggered mode.

+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

+  */

+#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \

+                                                      ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )

+

+/**

+  * @brief Verify the ADC oversampling regular conversion resumed or continued mode.

+  * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode.

+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

+  */

+#define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \

+                                               ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )

+

+/**

+  * @brief Verify the DFSDM mode configuration.

+  * @param __HANDLE__ ADC handle.

+  * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For

+  *      this reason, the input parameter is the ADC handle and not the configuration parameter

+  *      directly.

+  * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid)

+  */

+#if defined(DFSDM1_Channel0)

+#define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_DISABLE) || \

+                                          ((__HANDLE__)->Init.DFSDMConfig == ADC_DFSDM_MODE_ENABLE) )

+#else

+#define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET)

+#endif

+

+/**

+  * @brief Return the DFSDM configuration mode.

+  * @param __HANDLE__ ADC handle.

+  * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled).

+  *       For this reason, the input parameter is the ADC handle and not the configuration parameter

+  *       directly.

+  * @retval DFSDM configuration mode

+  */

+#if defined(DFSDM1_Channel0)

+#define ADC_CFGR_DFSDM(__HANDLE__) ((__HANDLE__)->Init.DFSDMConfig)

+#else

+#define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL)

+#endif

+

+/**

+  * @}

+  */

+

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup ADCEx_Exported_Functions

+  * @{

+  */

+

+/** @addtogroup ADCEx_Exported_Functions_Group1

+  * @{

+  */

+/* IO operation functions *****************************************************/

+

+/* ADC calibration */

+HAL_StatusTypeDef       HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t CalibrationMode, uint32_t SingleDiff);

+uint32_t                HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);

+HAL_StatusTypeDef       HAL_ADCEx_LinearCalibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t* LinearCalib_Buffer);

+HAL_StatusTypeDef       HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor);

+HAL_StatusTypeDef       HAL_ADCEx_LinearCalibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t* LinearCalib_Buffer);

+HAL_StatusTypeDef       HAL_ADCEx_LinearCalibration_FactorLoad(ADC_HandleTypeDef *hadc);

+

+

+/* Blocking mode: Polling */

+HAL_StatusTypeDef       HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc);

+HAL_StatusTypeDef       HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc);

+HAL_StatusTypeDef       HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);

+

+/* Non-blocking mode: Interruption */

+HAL_StatusTypeDef       HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc);

+HAL_StatusTypeDef       HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc);

+

+/* ADC multimode */

+HAL_StatusTypeDef       HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);

+HAL_StatusTypeDef       HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef *hadc);

+uint32_t                HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef *hadc);

+

+/* ADC retrieve conversion value intended to be used with polling or interruption */

+uint32_t                HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank);

+

+/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */

+void                    HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc);

+void                    HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc);

+void                    HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc);

+void                    HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc);

+void                    HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc);

+

+/* ADC group regular conversions stop */

+HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc);

+HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc);

+HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc);

+HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef *hadc);

+

+/**

+  * @}

+  */

+

+/** @addtogroup ADCEx_Exported_Functions_Group2

+  * @{

+  */

+/* Peripheral Control functions ***********************************************/

+HAL_StatusTypeDef       HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,ADC_InjectionConfTypeDef* sConfigInjected);

+HAL_StatusTypeDef       HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef *hadc, ADC_MultiModeTypeDef *multimode);

+HAL_StatusTypeDef       HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc);

+HAL_StatusTypeDef       HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc);

+HAL_StatusTypeDef       HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc);

+HAL_StatusTypeDef       HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_ADC_EX_H */

+

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_cec.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_cec.h
new file mode 100644
index 0000000000..f5e58987e2
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_cec.h
@@ -0,0 +1,794 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_cec.h

+  * @author  MCD Application Team

+  * @brief   Header file of CEC HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_CEC_H

+#define STM32H7xx_HAL_CEC_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+#if defined (CEC)

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup CEC

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup CEC_Exported_Types CEC Exported Types

+  * @{

+  */

+

+/**

+  * @brief CEC Init Structure definition

+  */

+typedef struct

+{

+  uint32_t SignalFreeTime;               /*!< Set SFT field, specifies the Signal Free Time.

+                                              It can be one of @ref CEC_Signal_Free_Time

+                                              and belongs to the set {0,...,7} where

+                                              0x0 is the default configuration

+                                              else means 0.5 + (SignalFreeTime - 1) nominal data bit periods */

+

+  uint32_t Tolerance;                    /*!< Set RXTOL bit, specifies the tolerance accepted on the received waveforms,

+                                              it can be a value of @ref CEC_Tolerance : it is either CEC_STANDARD_TOLERANCE

+                                              or CEC_EXTENDED_TOLERANCE */

+

+  uint32_t BRERxStop;                    /*!< Set BRESTP bit @ref CEC_BRERxStop : specifies whether or not a Bit Rising Error stops the reception.

+                                              CEC_NO_RX_STOP_ON_BRE: reception is not stopped.

+                                              CEC_RX_STOP_ON_BRE:    reception is stopped. */

+

+  uint32_t BREErrorBitGen;               /*!< Set BREGEN bit @ref CEC_BREErrorBitGen : specifies whether or not an Error-Bit is generated on the

+                                              CEC line upon Bit Rising Error detection.

+                                              CEC_BRE_ERRORBIT_NO_GENERATION: no error-bit generation.

+                                              CEC_BRE_ERRORBIT_GENERATION:    error-bit generation if BRESTP is set. */

+

+  uint32_t LBPEErrorBitGen;              /*!< Set LBPEGEN bit @ref CEC_LBPEErrorBitGen : specifies whether or not an Error-Bit is generated on the

+                                              CEC line upon Long Bit Period Error detection.

+                                              CEC_LBPE_ERRORBIT_NO_GENERATION:  no error-bit generation.

+                                              CEC_LBPE_ERRORBIT_GENERATION:     error-bit generation. */

+

+  uint32_t BroadcastMsgNoErrorBitGen;    /*!< Set BRDNOGEN bit @ref CEC_BroadCastMsgErrorBitGen : allows to avoid an Error-Bit generation on the CEC line

+                                              upon an error detected on a broadcast message.

+

+                                              It supersedes BREGEN and LBPEGEN bits for a broadcast message error handling. It can take two values:

+

+                                              1) CEC_BROADCASTERROR_ERRORBIT_GENERATION.

+                                                 a) BRE detection: error-bit generation on the CEC line if BRESTP=CEC_RX_STOP_ON_BRE

+                                                    and BREGEN=CEC_BRE_ERRORBIT_NO_GENERATION.

+                                                 b) LBPE detection: error-bit generation on the CEC line

+                                                    if LBPGEN=CEC_LBPE_ERRORBIT_NO_GENERATION.

+

+                                              2) CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION.

+                                                 no error-bit generation in case neither a) nor b) are satisfied. Additionally,

+                                                 there is no error-bit generation in case of Short Bit Period Error detection in

+                                                 a broadcast message while LSTN bit is set. */

+

+  uint32_t SignalFreeTimeOption;         /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.

+                                              CEC_SFT_START_ON_TXSOM SFT:    timer starts when TXSOM is set by software.

+                                              CEC_SFT_START_ON_TX_RX_END:  SFT timer starts automatically at the end of message transmission/reception. */

+

+  uint32_t ListenMode;                   /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:

+

+                                              CEC_REDUCED_LISTENING_MODE: CEC peripheral receives only message addressed to its

+                                                own address (OAR). Messages addressed to different destination are ignored.

+                                                Broadcast messages are always received.

+

+                                              CEC_FULL_LISTENING_MODE: CEC peripheral receives messages addressed to its own

+                                                address (OAR) with positive acknowledge. Messages addressed to different destination

+                                                are received, but without interfering with the CEC bus: no acknowledge sent.  */

+

+  uint16_t  OwnAddress;                 /*!< Own addresses configuration

+                                             This parameter can be a value of @ref CEC_OWN_ADDRESS */

+

+  uint8_t  *RxBuffer;                    /*!< CEC Rx buffer pointeur */

+

+

+} CEC_InitTypeDef;

+

+/**

+  * @brief HAL CEC State definition

+  * @note  HAL CEC State value is a combination of 2 different substates: gState and RxState (see @ref CEC_State_Definition).

+  *        - gState contains CEC state information related to global Handle management

+  *          and also information related to Tx operations.

+  *          gState value coding follow below described bitmap :

+  *          b7 (not used)

+  *             x  : Should be set to 0

+  *          b6  Error information

+  *             0  : No Error

+  *             1  : Error

+  *          b5     IP initilisation status

+  *             0  : Reset (IP not initialized)

+  *             1  : Init done (IP initialized. HAL CEC Init function already called)

+  *          b4-b3  (not used)

+  *             xx : Should be set to 00

+  *          b2     Intrinsic process state

+  *             0  : Ready

+  *             1  : Busy (IP busy with some configuration or internal operations)

+  *          b1     (not used)

+  *             x  : Should be set to 0

+  *          b0     Tx state

+  *             0  : Ready (no Tx operation ongoing)

+  *             1  : Busy (Tx operation ongoing)

+  *        - RxState contains information related to Rx operations.

+  *          RxState value coding follow below described bitmap :

+  *          b7-b6  (not used)

+  *             xx : Should be set to 00

+  *          b5     IP initilisation status

+  *             0  : Reset (IP not initialized)

+  *             1  : Init done (IP initialized)

+  *          b4-b2  (not used)

+  *            xxx : Should be set to 000

+  *          b1     Rx state

+  *             0  : Ready (no Rx operation ongoing)

+  *             1  : Busy (Rx operation ongoing)

+  *          b0     (not used)

+  *             x  : Should be set to 0.

+  */

+typedef uint32_t HAL_CEC_StateTypeDef;

+

+/**

+  * @brief  CEC handle Structure definition

+  */

+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)

+typedef struct __CEC_HandleTypeDef

+#else

+typedef struct

+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */

+{

+  CEC_TypeDef             *Instance;      /*!< CEC registers base address */

+

+  CEC_InitTypeDef         Init;           /*!< CEC communication parameters */

+

+  uint8_t                 *pTxBuffPtr;    /*!< Pointer to CEC Tx transfer Buffer */

+

+  uint16_t                TxXferCount;    /*!< CEC Tx Transfer Counter */

+

+  uint16_t                RxXferSize;     /*!< CEC Rx Transfer size, 0: header received only */

+

+  HAL_LockTypeDef         Lock;           /*!< Locking object */

+

+  HAL_CEC_StateTypeDef    gState;         /*!< CEC state information related to global Handle management

+                                               and also related to Tx operations.

+                                               This parameter can be a value of @ref HAL_CEC_StateTypeDef */

+

+  HAL_CEC_StateTypeDef    RxState;        /*!< CEC state information related to Rx operations.

+                                               This parameter can be a value of @ref HAL_CEC_StateTypeDef */

+

+  uint32_t                ErrorCode;      /*!< For errors handling purposes, copy of ISR register

+                                               in case error is reported */

+

+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)

+  void (* TxCpltCallback)(struct __CEC_HandleTypeDef

+                          *hcec);                                /*!< CEC Tx Transfer completed callback */

+  void (* RxCpltCallback)(struct __CEC_HandleTypeDef *hcec,

+                          uint32_t RxFrameSize);          /*!< CEC Rx Transfer completed callback */

+  void (* ErrorCallback)(struct __CEC_HandleTypeDef *hcec);                                 /*!< CEC error callback */

+

+  void (* MspInitCallback)(struct __CEC_HandleTypeDef *hcec);               /*!< CEC Msp Init callback              */

+  void (* MspDeInitCallback)(struct __CEC_HandleTypeDef *hcec);             /*!< CEC Msp DeInit callback            */

+

+#endif /* (USE_HAL_CEC_REGISTER_CALLBACKS) */

+} CEC_HandleTypeDef;

+

+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  HAL CEC Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_CEC_TX_CPLT_CB_ID      = 0x00U,    /*!< CEC Tx Transfer completed callback ID  */

+  HAL_CEC_RX_CPLT_CB_ID      = 0x01U,    /*!< CEC Rx Transfer completed callback ID  */

+  HAL_CEC_ERROR_CB_ID        = 0x02U,    /*!< CEC error callback ID                 */

+  HAL_CEC_MSPINIT_CB_ID      = 0x03U,    /*!< CEC Msp Init callback ID               */

+  HAL_CEC_MSPDEINIT_CB_ID    = 0x04U     /*!< CEC Msp DeInit callback ID             */

+} HAL_CEC_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL CEC Callback pointer definition

+  */

+typedef  void (*pCEC_CallbackTypeDef)(CEC_HandleTypeDef *hcec);  /*!< pointer to an CEC callback function */

+typedef  void (*pCEC_RxCallbackTypeDef)(CEC_HandleTypeDef *hcec,

+                                        uint32_t RxFrameSize);  /*!< pointer to an Rx Transfer completed callback function */

+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup CEC_Exported_Constants CEC Exported Constants

+  * @{

+  */

+/** @defgroup CEC_State_Definition CEC State Code Definition

+  * @{

+  */

+#define   HAL_CEC_STATE_RESET      ((uint32_t)0x00000000)   /*!< Peripheral is not yet Initialized

+                                                                 Value is allowed for gState and RxState  */

+#define   HAL_CEC_STATE_READY      ((uint32_t)0x00000020)   /*!< Peripheral Initialized and ready for use

+                                                                 Value is allowed for gState and RxState  */

+#define   HAL_CEC_STATE_BUSY       ((uint32_t)0x00000024)   /*!< an internal process is ongoing

+                                                                 Value is allowed for gState only         */

+#define   HAL_CEC_STATE_BUSY_RX    ((uint32_t)0x00000022)   /*!< Data Reception process is ongoing

+                                                                 Value is allowed for RxState only        */

+#define   HAL_CEC_STATE_BUSY_TX    ((uint32_t)0x00000021)   /*!< Data Transmission process is ongoing

+                                                                 Value is allowed for gState only         */

+#define   HAL_CEC_STATE_BUSY_RX_TX ((uint32_t)0x00000023)   /*!< an internal process is ongoing

+                                                                 Value is allowed for gState only         */

+#define   HAL_CEC_STATE_ERROR      ((uint32_t)0x00000050)   /*!< Error Value is allowed for gState only   */

+/**

+  * @}

+  */

+/** @defgroup CEC_Error_Code CEC Error Code

+  * @{

+  */

+#define HAL_CEC_ERROR_NONE    (uint32_t) 0x0000U     /*!< no error                      */

+#define HAL_CEC_ERROR_RXOVR   CEC_ISR_RXOVR          /*!< CEC Rx-Overrun                */

+#define HAL_CEC_ERROR_BRE     CEC_ISR_BRE            /*!< CEC Rx Bit Rising Error       */

+#define HAL_CEC_ERROR_SBPE    CEC_ISR_SBPE           /*!< CEC Rx Short Bit period Error */

+#define HAL_CEC_ERROR_LBPE    CEC_ISR_LBPE           /*!< CEC Rx Long Bit period Error  */

+#define HAL_CEC_ERROR_RXACKE  CEC_ISR_RXACKE         /*!< CEC Rx Missing Acknowledge    */

+#define HAL_CEC_ERROR_ARBLST  CEC_ISR_ARBLST         /*!< CEC Arbitration Lost          */

+#define HAL_CEC_ERROR_TXUDR   CEC_ISR_TXUDR          /*!< CEC Tx-Buffer Underrun        */

+#define HAL_CEC_ERROR_TXERR   CEC_ISR_TXERR          /*!< CEC Tx-Error                  */

+#define HAL_CEC_ERROR_TXACKE  CEC_ISR_TXACKE         /*!< CEC Tx Missing Acknowledge    */

+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)

+#define  HAL_CEC_ERROR_INVALID_CALLBACK ((uint32_t)0x00002000U) /*!< Invalid Callback Error  */

+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/** @defgroup CEC_Signal_Free_Time  CEC Signal Free Time setting parameter

+  * @{

+  */

+#define CEC_DEFAULT_SFT                    ((uint32_t)0x00000000U)

+#define CEC_0_5_BITPERIOD_SFT              ((uint32_t)0x00000001U)

+#define CEC_1_5_BITPERIOD_SFT              ((uint32_t)0x00000002U)

+#define CEC_2_5_BITPERIOD_SFT              ((uint32_t)0x00000003U)

+#define CEC_3_5_BITPERIOD_SFT              ((uint32_t)0x00000004U)

+#define CEC_4_5_BITPERIOD_SFT              ((uint32_t)0x00000005U)

+#define CEC_5_5_BITPERIOD_SFT              ((uint32_t)0x00000006U)

+#define CEC_6_5_BITPERIOD_SFT              ((uint32_t)0x00000007U)

+/**

+  * @}

+  */

+

+/** @defgroup CEC_Tolerance CEC Receiver Tolerance

+  * @{

+  */

+#define CEC_STANDARD_TOLERANCE             ((uint32_t)0x00000000U)

+#define CEC_EXTENDED_TOLERANCE             ((uint32_t)CEC_CFGR_RXTOL)

+/**

+  * @}

+  */

+

+/** @defgroup CEC_BRERxStop CEC Reception Stop on Error

+  * @{

+  */

+#define CEC_NO_RX_STOP_ON_BRE             ((uint32_t)0x00000000U)

+#define CEC_RX_STOP_ON_BRE                ((uint32_t)CEC_CFGR_BRESTP)

+/**

+  * @}

+  */

+

+/** @defgroup CEC_BREErrorBitGen  CEC Error Bit Generation if Bit Rise Error reported

+  * @{

+  */

+#define CEC_BRE_ERRORBIT_NO_GENERATION     ((uint32_t)0x00000000U)

+#define CEC_BRE_ERRORBIT_GENERATION        ((uint32_t)CEC_CFGR_BREGEN)

+/**

+  * @}

+  */

+

+/** @defgroup CEC_LBPEErrorBitGen  CEC Error Bit Generation if Long Bit Period Error reported

+  * @{

+  */

+#define CEC_LBPE_ERRORBIT_NO_GENERATION     ((uint32_t)0x00000000U)

+#define CEC_LBPE_ERRORBIT_GENERATION        ((uint32_t)CEC_CFGR_LBPEGEN)

+/**

+  * @}

+  */

+

+/** @defgroup CEC_BroadCastMsgErrorBitGen  CEC Error Bit Generation on Broadcast message

+  * @{

+  */

+#define CEC_BROADCASTERROR_ERRORBIT_GENERATION     ((uint32_t)0x00000000U)

+#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION  ((uint32_t)CEC_CFGR_BRDNOGEN)

+/**

+  * @}

+  */

+

+/** @defgroup CEC_SFT_Option     CEC Signal Free Time start option

+  * @{

+  */

+#define CEC_SFT_START_ON_TXSOM           ((uint32_t)0x00000000U)

+#define CEC_SFT_START_ON_TX_RX_END       ((uint32_t)CEC_CFGR_SFTOPT)

+/**

+  * @}

+  */

+

+/** @defgroup CEC_Listening_Mode    CEC Listening mode option

+  * @{

+  */

+#define CEC_REDUCED_LISTENING_MODE          ((uint32_t)0x00000000U)

+#define CEC_FULL_LISTENING_MODE             ((uint32_t)CEC_CFGR_LSTN)

+/**

+  * @}

+  */

+

+/** @defgroup CEC_OAR_Position   CEC Device Own Address position in CEC CFGR register

+  * @{

+  */

+#define CEC_CFGR_OAR_LSB_POS            ((uint32_t) 16U)

+/**

+  * @}

+  */

+

+/** @defgroup CEC_Initiator_Position   CEC Initiator logical address position in message header

+  * @{

+  */

+#define CEC_INITIATOR_LSB_POS           ((uint32_t) 4U)

+/**

+  * @}

+  */

+

+/** @defgroup CEC_OWN_ADDRESS   CEC Own Address

+  * @{

+  */

+#define CEC_OWN_ADDRESS_NONE           ((uint16_t) 0x0000U)   /* Reset value */

+#define CEC_OWN_ADDRESS_0              ((uint16_t) 0x0001U)   /* Logical Address 0 */

+#define CEC_OWN_ADDRESS_1              ((uint16_t) 0x0002U)   /* Logical Address 1 */

+#define CEC_OWN_ADDRESS_2              ((uint16_t) 0x0004U)   /* Logical Address 2 */

+#define CEC_OWN_ADDRESS_3              ((uint16_t) 0x0008U)   /* Logical Address 3 */

+#define CEC_OWN_ADDRESS_4              ((uint16_t) 0x0010U)   /* Logical Address 4 */

+#define CEC_OWN_ADDRESS_5              ((uint16_t) 0x0020U)   /* Logical Address 5 */

+#define CEC_OWN_ADDRESS_6              ((uint16_t) 0x0040U)   /* Logical Address 6 */

+#define CEC_OWN_ADDRESS_7              ((uint16_t) 0x0080U)   /* Logical Address 7 */

+#define CEC_OWN_ADDRESS_8              ((uint16_t) 0x0100U)   /* Logical Address 9 */

+#define CEC_OWN_ADDRESS_9              ((uint16_t) 0x0200U)   /* Logical Address 10 */

+#define CEC_OWN_ADDRESS_10             ((uint16_t) 0x0400U)   /* Logical Address 11 */

+#define CEC_OWN_ADDRESS_11             ((uint16_t) 0x0800U)   /* Logical Address 12 */

+#define CEC_OWN_ADDRESS_12             ((uint16_t) 0x1000U)   /* Logical Address 13 */

+#define CEC_OWN_ADDRESS_13             ((uint16_t) 0x2000U)   /* Logical Address 14 */

+#define CEC_OWN_ADDRESS_14             ((uint16_t) 0x4000U)   /* Logical Address 15 */

+/**

+  * @}

+  */

+

+/** @defgroup CEC_Interrupts_Definitions  CEC Interrupts definition

+  * @{

+  */

+#define CEC_IT_TXACKE                   CEC_IER_TXACKEIE

+#define CEC_IT_TXERR                    CEC_IER_TXERRIE

+#define CEC_IT_TXUDR                    CEC_IER_TXUDRIE

+#define CEC_IT_TXEND                    CEC_IER_TXENDIE

+#define CEC_IT_TXBR                     CEC_IER_TXBRIE

+#define CEC_IT_ARBLST                   CEC_IER_ARBLSTIE

+#define CEC_IT_RXACKE                   CEC_IER_RXACKEIE

+#define CEC_IT_LBPE                     CEC_IER_LBPEIE

+#define CEC_IT_SBPE                     CEC_IER_SBPEIE

+#define CEC_IT_BRE                      CEC_IER_BREIE

+#define CEC_IT_RXOVR                    CEC_IER_RXOVRIE

+#define CEC_IT_RXEND                    CEC_IER_RXENDIE

+#define CEC_IT_RXBR                     CEC_IER_RXBRIE

+/**

+  * @}

+  */

+

+/** @defgroup CEC_Flags_Definitions  CEC Flags definition

+  * @{

+  */

+#define CEC_FLAG_TXACKE                 CEC_ISR_TXACKE

+#define CEC_FLAG_TXERR                  CEC_ISR_TXERR

+#define CEC_FLAG_TXUDR                  CEC_ISR_TXUDR

+#define CEC_FLAG_TXEND                  CEC_ISR_TXEND

+#define CEC_FLAG_TXBR                   CEC_ISR_TXBR

+#define CEC_FLAG_ARBLST                 CEC_ISR_ARBLST

+#define CEC_FLAG_RXACKE                 CEC_ISR_RXACKE

+#define CEC_FLAG_LBPE                   CEC_ISR_LBPE

+#define CEC_FLAG_SBPE                   CEC_ISR_SBPE

+#define CEC_FLAG_BRE                    CEC_ISR_BRE

+#define CEC_FLAG_RXOVR                  CEC_ISR_RXOVR

+#define CEC_FLAG_RXEND                  CEC_ISR_RXEND

+#define CEC_FLAG_RXBR                   CEC_ISR_RXBR

+/**

+  * @}

+  */

+

+/** @defgroup CEC_ALL_ERROR CEC all RX or TX errors flags

+  * @{

+  */

+#define CEC_ISR_ALL_ERROR              ((uint32_t)CEC_ISR_RXOVR|CEC_ISR_BRE|CEC_ISR_SBPE|CEC_ISR_LBPE|CEC_ISR_RXACKE|\

+                                        CEC_ISR_ARBLST|CEC_ISR_TXUDR|CEC_ISR_TXERR|CEC_ISR_TXACKE)

+/**

+  * @}

+  */

+

+/** @defgroup CEC_IER_ALL_RX CEC all RX errors interrupts enabling flag

+  * @{

+  */

+#define CEC_IER_RX_ALL_ERR              ((uint32_t)CEC_IER_RXACKEIE|CEC_IER_LBPEIE|CEC_IER_SBPEIE|CEC_IER_BREIE|CEC_IER_RXOVRIE)

+/**

+  * @}

+  */

+

+/** @defgroup CEC_IER_ALL_TX CEC all TX errors interrupts enabling flag

+  * @{

+  */

+#define CEC_IER_TX_ALL_ERR              ((uint32_t)CEC_IER_TXACKEIE|CEC_IER_TXERRIE|CEC_IER_TXUDRIE|CEC_IER_ARBLSTIE)

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macros -----------------------------------------------------------*/

+/** @defgroup CEC_Exported_Macros CEC Exported Macros

+  * @{

+  */

+

+/** @brief  Reset CEC handle gstate & RxState

+  * @param  __HANDLE__ CEC handle.

+  * @retval None

+  */

+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)

+#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{                                                   \

+                                                       (__HANDLE__)->gState = HAL_CEC_STATE_RESET;     \

+                                                       (__HANDLE__)->RxState = HAL_CEC_STATE_RESET;    \

+                                                       (__HANDLE__)->MspInitCallback = NULL;           \

+                                                       (__HANDLE__)->MspDeInitCallback = NULL;         \

+                                                     } while(0)

+#else

+#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{                                                   \

+                                                       (__HANDLE__)->gState = HAL_CEC_STATE_RESET;     \

+                                                       (__HANDLE__)->RxState = HAL_CEC_STATE_RESET;    \

+                                                     } while(0)

+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */

+/** @brief  Checks whether or not the specified CEC interrupt flag is set.

+  * @param  __HANDLE__ specifies the CEC Handle.

+  * @param  __FLAG__ specifies the flag to check.

+  *            @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error

+  *            @arg CEC_FLAG_TXERR: Tx Error.

+  *            @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.

+  *            @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).

+  *            @arg CEC_FLAG_TXBR: Tx-Byte Request.

+  *            @arg CEC_FLAG_ARBLST: Arbitration Lost

+  *            @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge

+  *            @arg CEC_FLAG_LBPE: Rx Long period Error

+  *            @arg CEC_FLAG_SBPE: Rx Short period Error

+  *            @arg CEC_FLAG_BRE: Rx Bit Rising Error

+  *            @arg CEC_FLAG_RXOVR: Rx Overrun.

+  *            @arg CEC_FLAG_RXEND: End Of Reception.

+  *            @arg CEC_FLAG_RXBR: Rx-Byte Received.

+  * @retval ITStatus

+  */

+#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->ISR & (__FLAG__))

+

+/** @brief  Clears the interrupt or status flag when raised (write at 1)

+  * @param  __HANDLE__ specifies the CEC Handle.

+  * @param  __FLAG__ specifies the interrupt/status flag to clear.

+  *        This parameter can be one of the following values:

+  *            @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error

+  *            @arg CEC_FLAG_TXERR: Tx Error.

+  *            @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.

+  *            @arg CEC_FLAG_TXEND: End of transmission (successful transmission of the last byte).

+  *            @arg CEC_FLAG_TXBR: Tx-Byte Request.

+  *            @arg CEC_FLAG_ARBLST: Arbitration Lost

+  *            @arg CEC_FLAG_RXACKE: Rx-Missing Acknowledge

+  *            @arg CEC_FLAG_LBPE: Rx Long period Error

+  *            @arg CEC_FLAG_SBPE: Rx Short period Error

+  *            @arg CEC_FLAG_BRE: Rx Bit Rising Error

+  *            @arg CEC_FLAG_RXOVR: Rx Overrun.

+  *            @arg CEC_FLAG_RXEND: End Of Reception.

+  *            @arg CEC_FLAG_RXBR: Rx-Byte Received.

+  * @retval none

+  */

+#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->ISR |= (__FLAG__))

+

+/** @brief  Enables the specified CEC interrupt.

+  * @param  __HANDLE__ specifies the CEC Handle.

+  * @param  __INTERRUPT__ specifies the CEC interrupt to enable.

+  *          This parameter can be one of the following values:

+  *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable

+  *            @arg CEC_IT_TXERR: Tx Error IT Enable

+  *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable

+  *            @arg CEC_IT_TXEND: End of transmission IT Enable

+  *            @arg CEC_IT_TXBR: Tx-Byte Request IT Enable

+  *            @arg CEC_IT_ARBLST: Arbitration Lost IT Enable

+  *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable

+  *            @arg CEC_IT_LBPE: Rx Long period Error IT Enable

+  *            @arg CEC_IT_SBPE: Rx Short period Error IT Enable

+  *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable

+  *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable

+  *            @arg CEC_IT_RXEND: End Of Reception IT Enable

+  *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable

+  * @retval none

+  */

+#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))

+

+/** @brief  Disables the specified CEC interrupt.

+  * @param  __HANDLE__ specifies the CEC Handle.

+  * @param  __INTERRUPT__ specifies the CEC interrupt to disable.

+  *          This parameter can be one of the following values:

+  *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable

+  *            @arg CEC_IT_TXERR: Tx Error IT Enable

+  *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable

+  *            @arg CEC_IT_TXEND: End of transmission IT Enable

+  *            @arg CEC_IT_TXBR: Tx-Byte Request IT Enable

+  *            @arg CEC_IT_ARBLST: Arbitration Lost IT Enable

+  *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable

+  *            @arg CEC_IT_LBPE: Rx Long period Error IT Enable

+  *            @arg CEC_IT_SBPE: Rx Short period Error IT Enable

+  *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable

+  *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable

+  *            @arg CEC_IT_RXEND: End Of Reception IT Enable

+  *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable

+  * @retval none

+  */

+#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))

+

+/** @brief  Checks whether or not the specified CEC interrupt is enabled.

+  * @param  __HANDLE__ specifies the CEC Handle.

+  * @param  __INTERRUPT__ specifies the CEC interrupt to check.

+  *          This parameter can be one of the following values:

+  *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable

+  *            @arg CEC_IT_TXERR: Tx Error IT Enable

+  *            @arg CEC_IT_TXUDR: Tx-Buffer Underrun IT Enable

+  *            @arg CEC_IT_TXEND: End of transmission IT Enable

+  *            @arg CEC_IT_TXBR: Tx-Byte Request IT Enable

+  *            @arg CEC_IT_ARBLST: Arbitration Lost IT Enable

+  *            @arg CEC_IT_RXACKE: Rx-Missing Acknowledge IT Enable

+  *            @arg CEC_IT_LBPE: Rx Long period Error IT Enable

+  *            @arg CEC_IT_SBPE: Rx Short period Error IT Enable

+  *            @arg CEC_IT_BRE: Rx Bit Rising Error IT Enable

+  *            @arg CEC_IT_RXOVR: Rx Overrun IT Enable

+  *            @arg CEC_IT_RXEND: End Of Reception IT Enable

+  *            @arg CEC_IT_RXBR: Rx-Byte Received IT Enable

+  * @retval FlagStatus

+  */

+#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))

+

+/** @brief  Enables the CEC device

+  * @param  __HANDLE__ specifies the CEC Handle.

+  * @retval none

+  */

+#define __HAL_CEC_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR |=  CEC_CR_CECEN)

+

+/** @brief  Disables the CEC device

+  * @param  __HANDLE__ specifies the CEC Handle.

+  * @retval none

+  */

+#define __HAL_CEC_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR &=  ~CEC_CR_CECEN)

+

+/** @brief  Set Transmission Start flag

+  * @param  __HANDLE__ specifies the CEC Handle.

+  * @retval none

+  */

+#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__)        ((__HANDLE__)->Instance->CR |=  CEC_CR_TXSOM)

+

+/** @brief  Set Transmission End flag

+  * @param  __HANDLE__ specifies the CEC Handle.

+  * @retval none

+  * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.

+  */

+#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__)         ((__HANDLE__)->Instance->CR |=  CEC_CR_TXEOM)

+

+/** @brief  Get Transmission Start flag

+  * @param  __HANDLE__ specifies the CEC Handle.

+  * @retval FlagStatus

+  */

+#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)

+

+/** @brief  Get Transmission End flag

+  * @param  __HANDLE__ specifies the CEC Handle.

+  * @retval FlagStatus

+  */

+#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__)   ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)

+

+/** @brief  Clear OAR register

+  * @param  __HANDLE__ specifies the CEC Handle.

+  * @retval none

+  */

+#define __HAL_CEC_CLEAR_OAR(__HANDLE__)   CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)

+

+/** @brief  Set OAR register (without resetting previously set address in case of multi-address mode)

+  *          To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand

+  * @param  __HANDLE__ specifies the CEC Handle.

+  * @param  __ADDRESS__ Own Address value (CEC logical address is identified by bit position)

+  * @retval none

+  */

+#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__)   SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup CEC_Exported_Functions

+  * @{

+  */

+

+/** @addtogroup CEC_Exported_Functions_Group1

+  * @{

+  */

+/* Initialization and de-initialization functions  ****************************/

+HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);

+HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);

+HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);

+void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);

+void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);

+

+#if (USE_HAL_CEC_REGISTER_CALLBACKS == 1)

+HAL_StatusTypeDef HAL_CEC_RegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID,

+                                           pCEC_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_CEC_UnRegisterCallback(CEC_HandleTypeDef *hcec, HAL_CEC_CallbackIDTypeDef CallbackID);

+

+HAL_StatusTypeDef HAL_CEC_RegisterRxCpltCallback(CEC_HandleTypeDef *hcec, pCEC_RxCallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_CEC_UnRegisterRxCpltCallback(CEC_HandleTypeDef *hcec);

+#endif /* USE_HAL_CEC_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/** @addtogroup CEC_Exported_Functions_Group2

+  * @{

+  */

+/* I/O operation functions  ***************************************************/

+HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress, uint8_t DestinationAddress,

+                                      uint8_t *pData, uint32_t Size);

+uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);

+void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t *Rxbuffer);

+void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);

+void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);

+void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);

+void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);

+/**

+  * @}

+  */

+

+/** @addtogroup CEC_Exported_Functions_Group3

+  * @{

+  */

+/* Peripheral State functions  ************************************************/

+HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec);

+uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private types -------------------------------------------------------------*/

+/** @defgroup CEC_Private_Types CEC Private Types

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private variables ---------------------------------------------------------*/

+/** @defgroup CEC_Private_Variables CEC Private Variables

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup CEC_Private_Constants CEC Private Constants

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup CEC_Private_Macros CEC Private Macros

+  * @{

+  */

+

+#define IS_CEC_SIGNALFREETIME(__SFT__)     ((__SFT__) <= CEC_CFGR_SFT)

+

+#define IS_CEC_TOLERANCE(__RXTOL__)        (((__RXTOL__) == CEC_STANDARD_TOLERANCE) || \

+                                            ((__RXTOL__) == CEC_EXTENDED_TOLERANCE))

+

+#define IS_CEC_BRERXSTOP(__BRERXSTOP__)   (((__BRERXSTOP__) == CEC_NO_RX_STOP_ON_BRE) || \

+                                           ((__BRERXSTOP__) == CEC_RX_STOP_ON_BRE))

+

+#define IS_CEC_BREERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_NO_GENERATION) || \

+                                                ((__ERRORBITGEN__) == CEC_BRE_ERRORBIT_GENERATION))

+

+#define IS_CEC_LBPEERRORBITGEN(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_NO_GENERATION) || \

+                                                 ((__ERRORBITGEN__) == CEC_LBPE_ERRORBIT_GENERATION))

+

+#define IS_CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION(__ERRORBITGEN__) (((__ERRORBITGEN__) == CEC_BROADCASTERROR_ERRORBIT_GENERATION) || \

+                                                                       ((__ERRORBITGEN__) == CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION))

+

+#define IS_CEC_SFTOP(__SFTOP__)          (((__SFTOP__) == CEC_SFT_START_ON_TXSOM) || \

+                                          ((__SFTOP__) == CEC_SFT_START_ON_TX_RX_END))

+

+#define IS_CEC_LISTENING_MODE(__MODE__)     (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \

+                                             ((__MODE__) == CEC_FULL_LISTENING_MODE))

+

+/** @brief Check CEC message size.

+  *       The message size is the payload size: without counting the header,

+  *       it varies from 0 byte (ping operation, one header only, no payload) to

+  *       15 bytes (1 opcode and up to 14 operands following the header).

+  * @param  __SIZE__ CEC message size.

+  * @retval Test result (TRUE or FALSE).

+  */

+#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)

+

+/** @brief Check CEC device Own Address Register (OAR) setting.

+  *        OAR address is written in a 15-bit field within CEC_CFGR register.

+  * @param  __ADDRESS__ CEC own address.

+  * @retval Test result (TRUE or FALSE).

+  */

+#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)

+

+/** @brief Check CEC initiator or destination logical address setting.

+  *        Initiator and destination addresses are coded over 4 bits.

+  * @param  __ADDRESS__ CEC initiator or logical address.

+  * @retval Test result (TRUE or FALSE).

+  */

+#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xFU)

+/**

+  * @}

+  */

+/* Private functions ---------------------------------------------------------*/

+/** @defgroup CEC_Private_Functions CEC Private Functions

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* CEC */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xxHAL_CEC_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_comp.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_comp.h
new file mode 100644
index 0000000000..cea3606f4f
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_comp.h
@@ -0,0 +1,954 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_comp.h

+  * @author  MCD Application Team

+  * @brief   Header file of COMP HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_COMP_H

+#define STM32H7xx_HAL_COMP_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup COMP

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/ 

+/** @defgroup COMP_Exported_Types COMP Exported Types

+  * @{

+  */

+

+/** 

+  * @brief  COMP Init structure definition  

+  */

+typedef struct

+{

+

+  uint32_t WindowMode;         /*!< Set window mode of a pair of comparators instances

+                                    (2 consecutive instances odd and even COMP<x> and COMP<x+1>).

+                                    Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode.

+                                    This parameter can be a value of @ref COMP_WindowMode */

+

+  uint32_t Mode;               /*!< Set comparator operating mode to adjust power and speed.

+                                    Note: For the characteritics of comparator power modes

+                                          (propagation delay and power consumption), refer to device datasheet.

+                                    This parameter can be a value of @ref COMP_PowerMode */

+

+  uint32_t NonInvertingInput;  /*!< Set comparator input plus (non-inverting input).

+                                    This parameter can be a value of @ref COMP_InputPlus */

+

+  uint32_t InvertingInput;     /*!< Set comparator input minus (inverting input).

+                                    This parameter can be a value of @ref COMP_InputMinus */

+

+  uint32_t Hysteresis;         /*!< Set comparator hysteresis mode of the input minus.

+                                    This parameter can be a value of @ref COMP_Hysteresis */

+

+  uint32_t OutputPol;          /*!< Set comparator output polarity.

+                                    This parameter can be a value of @ref COMP_OutputPolarity */

+

+  uint32_t BlankingSrce;       /*!< Set comparator blanking source.

+                                    This parameter can be a value of @ref COMP_BlankingSrce */

+

+  uint32_t TriggerMode;        /*!< Set the comparator output triggering External Interrupt Line (EXTI).

+                                    This parameter can be a value of @ref COMP_EXTI_TriggerMode */

+

+}COMP_InitTypeDef;

+

+/**

+  * @brief  HAL COMP state machine: HAL COMP states definition

+  */

+#define COMP_STATE_BITFIELD_LOCK  ((uint32_t)0x10)

+typedef enum

+{

+  HAL_COMP_STATE_RESET             = 0x00,                                              /*!< COMP not yet initialized                             */

+  HAL_COMP_STATE_RESET_LOCKED      = (HAL_COMP_STATE_RESET | COMP_STATE_BITFIELD_LOCK), /*!< COMP not yet initialized and configuration is locked */

+  HAL_COMP_STATE_READY             = 0x01,                                              /*!< COMP initialized and ready for use                   */

+  HAL_COMP_STATE_READY_LOCKED      = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked         */

+  HAL_COMP_STATE_BUSY              = 0x02,                                              /*!< COMP is running                                      */

+  HAL_COMP_STATE_BUSY_LOCKED       = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK)   /*!< COMP is running and configuration is locked          */

+}HAL_COMP_StateTypeDef;

+

+/** 

+  * @brief  COMP Handle Structure definition

+  */

+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)

+typedef struct __COMP_HandleTypeDef

+#else

+typedef struct

+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */

+{

+  COMP_TypeDef       *Instance;       /*!< Register base address    */

+  COMP_InitTypeDef   Init;            /*!< COMP required parameters */

+  HAL_LockTypeDef    Lock;            /*!< Locking object           */

+  __IO HAL_COMP_StateTypeDef  State;  /*!< COMP communication state */

+  __IO uint32_t      ErrorCode;       /*!< COMP error code */

+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)

+  void (* TriggerCallback)(struct __COMP_HandleTypeDef *hcomp);   /*!< COMP trigger callback */

+  void (* MspInitCallback)(struct __COMP_HandleTypeDef *hcomp);   /*!< COMP Msp Init callback */

+  void (* MspDeInitCallback)(struct __COMP_HandleTypeDef *hcomp); /*!< COMP Msp DeInit callback */

+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */

+

+} COMP_HandleTypeDef;

+

+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  HAL COMP Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_COMP_TRIGGER_CB_ID                = 0x00U,  /*!< COMP trigger callback ID */

+  HAL_COMP_MSPINIT_CB_ID                = 0x01U,  /*!< COMP Msp Init callback ID */

+  HAL_COMP_MSPDEINIT_CB_ID              = 0x02U   /*!< COMP Msp DeInit callback ID */

+} HAL_COMP_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL COMP Callback pointer definition

+  */

+typedef  void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer to a COMP callback function */

+

+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup COMP_Exported_Constants COMP Exported Constants

+  * @{

+  */

+  

+/** @defgroup COMP_Error_Code COMP Error Code

+  * @{

+  */

+#define HAL_COMP_ERROR_NONE             (0x00U)   /*!< No error */

+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)

+#define HAL_COMP_ERROR_INVALID_CALLBACK (0x01U)   /*!< Invalid Callback error */

+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+  

+/** @defgroup COMP_WindowMode COMP Window Mode

+  * @{

+  */

+#define COMP_WINDOWMODE_DISABLE                 ((uint32_t)0x00000000)   /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */

+#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CFGRx_WINMODE)     /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */

+

+/**

+  * @}

+  */

+

+/** @defgroup COMP_PowerMode COMP power mode

+  * @{

+  */

+/* Note: For the characteritics of comparator power modes                     */

+/*       (propagation delay and power consumption),                           */

+/*       refer to device datasheet.                                           */

+#define COMP_POWERMODE_HIGHSPEED       ((uint32_t)0x00000000)   /*!< High Speed */

+#define COMP_POWERMODE_MEDIUMSPEED     (COMP_CFGRx_PWRMODE_0)   /*!< Medium Speed */

+#define COMP_POWERMODE_ULTRALOWPOWER   (COMP_CFGRx_PWRMODE)     /*!< Ultra-low power mode */

+/**

+  * @}

+  */

+

+/** @defgroup COMP_InputPlus COMP input plus (non-inverting input)

+  * @{

+  */

+#define COMP_INPUT_PLUS_IO1            ((uint32_t)0x00000000) /*!< Comparator input plus connected to IO1 (pin PB0 for COMP1, pin PE9 for COMP2) */

+#define COMP_INPUT_PLUS_IO2            (COMP_CFGRx_INPSEL)    /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PE11 for COMP2) */

+#if defined (COMP_CFGRx_INP2SEL)

+#define COMP_INPUT_PLUS_DAC2_CH1       (COMP_CFGRx_INP2SEL)   /*!< Comparator input plus 2 connected to (DAC2_CH1 for COMP1) */

+#endif

+/**

+  * @}

+  */

+

+/** @defgroup COMP_InputMinus COMP input minus (inverting input)

+  * @{

+  */

+#define COMP_INPUT_MINUS_1_4VREFINT     (                                                                                        COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)    /*!< Comparator input minus connected to 1/4 VrefInt */

+#define COMP_INPUT_MINUS_1_2VREFINT     (                                                                  COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)    /*!< Comparator input minus connected to 1/2 VrefInt */

+#define COMP_INPUT_MINUS_3_4VREFINT     (                                            COMP_CFGRx_INMSEL_1                       | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)    /*!< Comparator input minus connected to 3/4 VrefInt */

+#define COMP_INPUT_MINUS_VREFINT        (                                            COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN                   )    /*!< Comparator input minus connected to VrefInt */

+#define COMP_INPUT_MINUS_DAC1_CH1       (                      COMP_CFGRx_INMSEL_2                                                                                   )    /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1) */

+#define COMP_INPUT_MINUS_DAC1_CH2       (                      COMP_CFGRx_INMSEL_2                       | COMP_CFGRx_INMSEL_0                                       )    /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2) */

+#define COMP_INPUT_MINUS_IO1            (                      COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1                                                             )    /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PE10 for COMP2) */

+#define COMP_INPUT_MINUS_IO2            (                      COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0                                       )    /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PE7 for COMP2) */

+#if defined (COMP_CFGRx_INMSEL_3)

+#define COMP_INPUT_MINUS_TPSENS_DAC2CH1 (COMP_CFGRx_INMSEL_3                                                                                                         )    /*!< Comparator input minus connected to (temp sensor which is exist in ADC for COMP1, DAC2_CH1 for COMP2) */

+#define COMP_INPUT_MINUS_VBAT_VDDAP     (COMP_CFGRx_INMSEL_3                                             | COMP_CFGRx_INMSEL_0                                       )    /*!< Comparator input minus connected to (VBAT/4 for COMP1, VDDAP for COMP2) */

+#endif

+/**

+  * @}

+  */

+

+/** @defgroup COMP_Hysteresis COMP hysteresis

+  * @{

+  */

+#define COMP_HYSTERESIS_NONE           ((uint32_t)0x00000000)   /*!< No hysteresis */

+#define COMP_HYSTERESIS_LOW            (COMP_CFGRx_HYST_0)      /*!< Hysteresis level low */

+#define COMP_HYSTERESIS_MEDIUM         (COMP_CFGRx_HYST_1)      /*!< Hysteresis level medium */

+#define COMP_HYSTERESIS_HIGH           (COMP_CFGRx_HYST)        /*!< Hysteresis level high */

+/**

+  * @}

+  */

+

+/** @defgroup COMP_OutputPolarity COMP Output Polarity

+  * @{

+  */

+#define COMP_OUTPUTPOL_NONINVERTED     ((uint32_t)0x00000000)  /*!< COMP output level is not inverted (comparator output is high when the input plus is at a higher voltage than the input minus) */

+#define COMP_OUTPUTPOL_INVERTED        (COMP_CFGRx_POLARITY)   /*!< COMP output level is inverted     (comparator output is low  when the input plus is at a higher voltage than the input minus) */

+/**

+  * @}

+  */

+

+

+/** @defgroup COMP_BlankingSrce  COMP Blanking Source

+  * @{

+  */

+/* Any blanking source can be selected for all comparators */

+#define COMP_BLANKINGSRC_NONE             ((uint32_t)0x00000000)                           /*!< No blanking source */

+#define COMP_BLANKINGSRC_TIM1_OC5         (COMP_CFGRx_BLANKING_0)                          /*!< TIM1 OC5 selected as blanking source for comparator */

+#define COMP_BLANKINGSRC_TIM2_OC3         (COMP_CFGRx_BLANKING_1)                          /*!< TIM2 OC3 selected as blanking source for comparator */

+#define COMP_BLANKINGSRC_TIM3_OC3         (COMP_CFGRx_BLANKING_0 |COMP_CFGRx_BLANKING_1)   /*!< TIM3 OC3 selected as blanking source for compartor */

+#define COMP_BLANKINGSRC_TIM3_OC4         (COMP_CFGRx_BLANKING_2)                          /*!< TIM3 OC4 selected as blanking source for comparator */

+#define COMP_BLANKINGSRC_TIM8_OC5         (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_0)    /*!< TIM8 OC5 selected as blanking source for comparator */

+#define COMP_BLANKINGSRC_TIM15_OC1        (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_1)    /*!< TIM15 OC1 selected as blanking source for comparator */

+/**

+  * @}

+  */

+

+

+

+

+/** @defgroup COMP_OutputLevel COMP Output Level

+  * @{

+  */ 

+

+/* Note: Comparator output level values are fixed to "0" and "1",             */

+/* corresponding COMP register bit is managed by HAL function to match        */

+/* with these values (independently of bit position in register).             */

+

+/* When output polarity is not inverted, comparator output is low when

+   the input plus is at a lower voltage than the input minus */

+#define COMP_OUTPUT_LEVEL_LOW              ((uint32_t)0x00000000)

+/* When output polarity is not inverted, comparator output is high when

+   the input plus is at a higher voltage than the input minus */

+#define COMP_OUTPUT_LEVEL_HIGH             ((uint32_t)0x00000001)

+

+/**

+  * @}

+  */

+

+/** @defgroup COMP_EXTI_TriggerMode COMP output to EXTI

+  * @{

+  */

+#define COMP_TRIGGERMODE_NONE                 ((uint32_t)0x00000000)                                    /*!< Comparator output triggering no External Interrupt Line */

+#define COMP_TRIGGERMODE_IT_RISING            (COMP_EXTI_IT | COMP_EXTI_RISING)                         /*!< Comparator output triggering External Interrupt Line event with interruption, on rising edge */

+#define COMP_TRIGGERMODE_IT_FALLING           (COMP_EXTI_IT | COMP_EXTI_FALLING)                        /*!< Comparator output triggering External Interrupt Line event with interruption, on falling edge */

+#define COMP_TRIGGERMODE_IT_RISING_FALLING    (COMP_EXTI_IT | COMP_EXTI_RISING | COMP_EXTI_FALLING)     /*!< Comparator output triggering External Interrupt Line event with interruption, on both rising and falling edges */

+#define COMP_TRIGGERMODE_EVENT_RISING         (COMP_EXTI_EVENT | COMP_EXTI_RISING)                      /*!< Comparator output triggering External Interrupt Line event only (without interruption), on rising edge */

+#define COMP_TRIGGERMODE_EVENT_FALLING        (COMP_EXTI_EVENT | COMP_EXTI_FALLING)                     /*!< Comparator output triggering External Interrupt Line event only (without interruption), on falling edge */

+#define COMP_TRIGGERMODE_EVENT_RISING_FALLING (COMP_EXTI_EVENT | COMP_EXTI_RISING | COMP_EXTI_FALLING)  /*!< Comparator output triggering External Interrupt Line event only (without interruption), on both rising and falling edges */

+

+/**

+  * @}

+  */

+

+/** @defgroup COMP_Flag COMP Flag

+  * @{

+  */

+#define COMP_FLAG_C1I           COMP_SR_C1IF           /*!< Comparator 1 Interrupt Flag */

+#define COMP_FLAG_C2I           COMP_SR_C2IF           /*!< Comparator 2 Interrupt Flag */

+#define COMP_FLAG_LOCK          COMP_CFGRx_LOCK        /*!< Lock flag */

+/**

+  * @}

+  */

+/** @defgroup COMP_IT_CLEAR_Flags  COMP Interruption Clear Flags

+  * @{

+  */

+#define COMP_CLEAR_C1IF          COMP_ICFR_C1IF     /*!< Clear Comparator 1 Interrupt Flag */

+#define COMP_CLEAR_C2IF          COMP_ICFR_C2IF     /*!< Clear Comparator 2 Interrupt Flag */

+/**

+  * @}

+  */

+/** @defgroup COMP_Interrupts_Definitions COMP Interrupts Definitions

+  * @{

+  */

+#define COMP_IT_EN               COMP_CFGRx_ITEN 

+

+/**

+  * @}

+  */

+  

+

+/**

+  * @}

+  */

+ 

+/* Exported macros -----------------------------------------------------------*/

+/** @defgroup COMP_Exported_Macros COMP Exported Macros

+  * @{

+  */

+/** @defgroup COMP_Handle_Management  COMP Handle Management

+ * @{

+  */

+

+/** @brief  Reset COMP handle state.

+  * @param  __HANDLE__  COMP handle

+  * @retval None

+  */

+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)

+#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{                                                 \

+                                                     (__HANDLE__)->State = HAL_COMP_STATE_RESET;      \

+                                                     (__HANDLE__)->MspInitCallback = NULL;            \

+                                                     (__HANDLE__)->MspDeInitCallback = NULL;          \

+                                                    } while(0)

+#else

+#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)

+#endif

+

+/**

+  * @brief Clear COMP error code (set it to no error code "HAL_COMP_ERROR_NONE").

+  * @param __HANDLE__ COMP handle

+  * @retval None

+  */

+#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE) 

+

+/**

+  * @brief  Enable the specified comparator.

+  * @param  __HANDLE__ COMP handle

+  * @retval None

+  */

+#define __HAL_COMP_ENABLE(__HANDLE__)                 SET_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_EN)

+

+/**

+  * @brief  Disable the specified comparator.

+  * @param  __HANDLE__ COMP handle

+  * @retval None

+  */

+#define __HAL_COMP_DISABLE(__HANDLE__)                CLEAR_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_EN)

+

+/**

+  * @brief  Lock the specified comparator configuration.

+  * @note   Using this macro induce HAL COMP handle state machine being no

+  *         more in line with COMP instance state.

+  *         To keep HAL COMP handle state machine updated, it is recommended

+  *         to use function "HAL_COMP_Lock')".

+  * @param  __HANDLE__ COMP handle

+  * @retval None

+  */

+#define __HAL_COMP_LOCK(__HANDLE__)                   SET_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_LOCK)

+

+/**

+  * @brief  Check whether the specified comparator is locked.

+  * @param  __HANDLE__  COMP handle

+  * @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked

+  */

+#define __HAL_COMP_IS_LOCKED(__HANDLE__)           (READ_BIT((__HANDLE__)->Instance->CFGR, COMP_CFGRx_LOCK) == COMP_CFGRx_LOCK)

+

+/**

+  * @}

+  */

+  

+/** @defgroup COMP_Exti_Management  COMP external interrupt line management

+  * @{

+  */

+

+/**

+  * @brief  Enable the COMP1 EXTI line rising edge trigger. 

+  * @retval None

+  */                                         

+#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE()    SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)

+

+

+/**

+  * @brief  Disable the COMP1 EXTI line rising edge trigger. 

+  * @retval None

+  */                                         

+#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE()    CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP1)

+

+/**

+  * @brief  Enable the COMP1 EXTI line falling edge trigger. 

+  * @retval None

+  */                                         

+#define __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE()    SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)

+

+/**

+  * @brief  Disable the COMP1 EXTI line falling edge trigger.

+  * @retval None

+  */                                         

+#define __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE()    CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP1)

+

+

+/**

+  * @brief  Enable the COMP1 EXTI line rising & falling edge trigger. 

+  * @retval None

+  */                                         

+#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE()   do {                                           \

+                                                               __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE();  \

+                                                               __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE(); \

+                                                             } while(0)

+

+

+/**

+  * @brief  Disable the COMP1 EXTI line rising & falling edge trigger. 

+  * @retval None

+  */                                         

+#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE()  do {                                            \

+                                                               __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE();  \

+                                                               __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE(); \

+                                                             } while(0)

+

+

+/**

+  * @brief  Enable the COMP1 EXTI line in interrupt mode.

+  * @retval None

+  */                                         

+#define __HAL_COMP_COMP1_EXTI_ENABLE_IT()             SET_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP1)

+

+/**

+  * @brief  Disable the COMP1 EXTI line in interrupt mode.

+  * @retval None

+  */

+#define __HAL_COMP_COMP1_EXTI_DISABLE_IT()            CLEAR_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP1)

+

+/**

+  * @brief  Enable the COMP1 EXTI Line in event mode.

+  * @retval None

+  */

+#define __HAL_COMP_COMP1_EXTI_ENABLE_EVENT()           SET_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP1)

+

+/**

+  * @brief  Disable the COMP1 EXTI Line in event mode.

+  * @retval None

+  */

+#define __HAL_COMP_COMP1_EXTI_DISABLE_EVENT()          CLEAR_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP1)

+

+/**

+  * @brief  Check whether the COMP1 EXTI line flag is set or not.

+  * @retval RESET or SET

+  */

+#define __HAL_COMP_COMP1_EXTI_GET_FLAG()              READ_BIT(EXTI_D1->PR1, COMP_EXTI_LINE_COMP1)

+/**

+  * @brief  Clear the COMP1 EXTI flag.

+  * @retval None

+  */

+#define __HAL_COMP_COMP1_EXTI_CLEAR_FLAG()            WRITE_REG(EXTI_D1->PR1, COMP_EXTI_LINE_COMP1)

+

+/**

+  * @brief  Generate a software interrupt on the COMP1 EXTI line.

+  * @retval None

+  */

+#define __HAL_COMP_COMP1_EXTI_GENERATE_SWIT()         SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP1)

+

+/**

+  * @brief  Enable the COMP1 D3 EXTI Line in event mode.

+  * @retval None

+  */

+#define __HAL_COMP_COMP1_EXTID3_ENABLE_EVENT()        SET_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP1)

+

+/**

+  * @brief  Disable the COMP1 D3 EXTI Line in event mode.

+  * @retval None

+  */

+#define __HAL_COMP_COMP1_EXTID3_DISABLE_EVENT()        CLEAR_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP1)

+

+#if defined(DUAL_CORE)

+/**

+  * @brief  Enable the COMP1 D2 EXTI line in interrupt mode.

+  * @retval None

+  */                                         

+#define __HAL_COMP_COMP1_EXTID2_ENABLE_IT()           SET_BIT(EXTI_D2->IMR1, COMP_EXTI_LINE_COMP1)

+

+/**

+  * @brief  Disable the COMP1 D2 EXTI line in interrupt mode.

+  * @retval None

+  */

+#define __HAL_COMP_COMP1_EXTID2_DISABLE_IT()          CLEAR_BIT(EXTI_D2->IMR1, COMP_EXTI_LINE_COMP1)

+

+/**

+  * @brief  Enable the COMP1 D2 EXTI Line in event mode.

+  * @retval None

+  */

+#define __HAL_COMP_COMP1_EXTID2_ENABLE_EVENT()         SET_BIT(EXTI_D2->EMR1, COMP_EXTI_LINE_COMP1)

+

+/**

+  * @brief  Disable the COMP1 D2 EXTI Line in event mode.

+  * @retval None

+  */

+#define __HAL_COMP_COMP1_EXTID2_DISABLE_EVENT()        CLEAR_BIT(EXTI_D2->EMR1, COMP_EXTI_LINE_COMP1)

+

+/**

+  * @brief  Check whether the COMP1 D2 EXTI line flag is set or not.

+  * @retval RESET or SET

+  */

+#define __HAL_COMP_COMP1_EXTID2_GET_FLAG()              READ_BIT(EXTI_D2->PR1, COMP_EXTI_LINE_COMP1)     

+

+/**

+  * @brief  Clear the COMP1 D2 EXTI flag.

+  * @retval None

+  */

+#define __HAL_COMP_COMP1_EXTID2_CLEAR_FLAG()            WRITE_REG(EXTI_D2->PR1, COMP_EXTI_LINE_COMP1)

+

+#endif

+

+/**

+  * @brief  Enable the COMP2 EXTI line rising edge trigger.

+  * @retval None

+  */                                         

+#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()    SET_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)

+

+/**

+  * @brief  Disable the COMP2 EXTI line rising edge trigger.

+  * @retval None

+  */                                         

+#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()   CLEAR_BIT(EXTI->RTSR1, COMP_EXTI_LINE_COMP2)

+

+/**

+  * @brief  Enable the COMP2 EXTI line falling edge trigger.

+  * @retval None

+  */                                         

+#define __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()   SET_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)

+

+/**

+  * @brief  Disable the COMP2 EXTI line falling edge trigger. 

+  * @retval None

+  */                                         

+#define __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, COMP_EXTI_LINE_COMP2)

+

+/**

+  * @brief  Enable the COMP2 EXTI line rising & falling edge trigger.

+  * @retval None

+  */                                         

+#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE()   do {                                           \

+                                                               __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE();  \

+                                                               __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE(); \

+                                                             } while(0)

+

+/**

+  * @brief  Disable the COMP2 EXTI line rising & falling edge trigger.

+  * @retval None

+  */                                         

+#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE()   do {                                           \

+                                                               __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE();  \

+                                                               __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE(); \

+                                                             } while(0)

+/**

+  * @brief  Enable the COMP2 EXTI line.

+  * @retval None

+  */                                         

+#define __HAL_COMP_COMP2_EXTI_ENABLE_IT()             SET_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP2)

+

+/**

+  * @brief  Disable the COMP2 EXTI line.

+  * @retval None

+  */

+#define __HAL_COMP_COMP2_EXTI_DISABLE_IT()            CLEAR_BIT(EXTI_D1->IMR1, COMP_EXTI_LINE_COMP2)

+

+/**

+  * @brief  Enable the COMP2 EXTI Line in event mode.

+  * @retval None

+  */

+#define __HAL_COMP_COMP2_EXTI_ENABLE_EVENT()          SET_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP2)

+

+/**

+  * @brief  Disable the COMP2 EXTI Line in event mode.

+  * @retval None

+  */

+#define __HAL_COMP_COMP2_EXTI_DISABLE_EVENT()          CLEAR_BIT(EXTI_D1->EMR1, COMP_EXTI_LINE_COMP2)

+

+/**

+  * @brief  Check whether the COMP2 EXTI line flag is set or not.

+  * @retval RESET or SET

+  */

+#define __HAL_COMP_COMP2_EXTI_GET_FLAG()              READ_BIT(EXTI_D1->PR1, COMP_EXTI_LINE_COMP2)

+

+/**

+  * @brief  Clear the the COMP2 EXTI flag.

+  * @retval None

+  */

+#define __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()            WRITE_REG(EXTI_D1->PR1, COMP_EXTI_LINE_COMP2)

+

+/**

+  * @brief  Enable the COMP2 D3 EXTI Line in event mode.

+  * @retval None

+  */

+#define __HAL_COMP_COMP2_EXTID3_ENABLE_EVENT()        SET_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP2)

+

+/**

+  * @brief  Disable the COMP2 D3 EXTI Line in event mode.

+  * @retval None

+  */

+#define __HAL_COMP_COMP2_EXTID3_DISABLE_EVENT()       CLEAR_BIT(EXTI->D3PMR1, COMP_EXTI_LINE_COMP2)

+

+/**

+  * @brief  Generate a software interrupt on the COMP2 EXTI line.

+  * @retval None

+  */

+#define __HAL_COMP_COMP2_EXTI_GENERATE_SWIT()         SET_BIT(EXTI->SWIER1, COMP_EXTI_LINE_COMP2)

+

+#if defined(DUAL_CORE)

+/**

+  * @brief  Enable the COMP2 D2 EXTI line

+  * @retval None

+  */                                         

+#define __HAL_COMP_COMP2_EXTID2_ENABLE_IT()           SET_BIT(EXTI_D2->IMR1, COMP_EXTI_LINE_COMP2)

+

+

+/**

+  * @brief  Disable the COMP2 D2 EXTI line.

+  * @retval None

+  */

+#define __HAL_COMP_COMP2_EXTID2_DISABLE_IT()          CLEAR_BIT(EXTI_D2->IMR1, COMP_EXTI_LINE_COMP2)

+

+

+

+/**

+  * @brief  Enable the COMP2 D2 EXTI Line in event mode.

+  * @retval None

+  */

+#define __HAL_COMP_COMP2_EXTID2_ENABLE_EVENT()         SET_BIT(EXTI_D2->EMR1, COMP_EXTI_LINE_COMP2)

+

+

+

+/**

+  * @brief  Disable the COMP2 D2 EXTI Line in event mode.

+  * @retval None

+  */

+#define __HAL_COMP_COMP2_EXTID2_DISABLE_EVENT()        CLEAR_BIT(EXTI_D2->EMR1, COMP_EXTI_LINE_COMP2)

+

+

+/**

+  * @brief  Check whether the COMP2 D2 EXTI line flag is set or not.

+  * @retval RESET or SET

+  */

+#define __HAL_COMP_COMP2_EXTID2_GET_FLAG()            READ_BIT(EXTI_D2->PR1, COMP_EXTI_LINE_COMP2)     

+

+/**

+  * @brief  Clear the the COMP2 D2 EXTI flag.

+  * @retval None

+  */

+#define __HAL_COMP_COMP2_EXTID2_CLEAR_FLAG()          WRITE_REG(EXTI_D2->PR1, COMP_EXTI_LINE_COMP2)

+

+#endif

+/** @brief  Checks if the specified COMP interrupt source is enabled or disabled.

+  * @param  __HANDLE__: specifies the COMP Handle.

+  *         This parameter can be COMP1 where x: 1 or 2 to select the COMP peripheral.

+  * @param  __INTERRUPT__: specifies the COMP interrupt source to check.

+  *          This parameter can be one of the following values:

+  *            @arg COMP_IT_EN: Comparator interrupt enable

+  *   

+  * @retval The new state of __IT__ (TRUE or FALSE)

+  */

+#define __HAL_COMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CFGR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

+

+/** @brief  Checks whether the specified COMP flag is set or not.

+  * @param  __FLAG__: specifies the flag to check.

+  *        This parameter can be one of the following values:

+  *            @arg COMP_FLAG_C1I:  Comparator 1 Interrupt Flag

+  *            @arg COMP_FLAG_C2I:  Comparator 2 Interrupt Flag

+  *            @retval The new state of __FLAG__ (TRUE or FALSE)

+  */

+#define __HAL_COMP_GET_FLAG(__FLAG__)     ((COMP12->SR & (__FLAG__)) == (__FLAG__))   

+

+/** @brief  Clears the specified COMP pending flag.

+  * @param  __FLAG__: specifies the flag to check.

+  *          This parameter can be any combination of the following values:

+  *            @arg COMP_CLEAR_C1IF  : Clear Comparator 1 Interrupt Flag

+  *            @arg COMP_CLEAR_C2IF  : Clear Comparator 2 Interrupt Flag

+  * @retval None

+  */

+#define __HAL_COMP_CLEAR_FLAG(__FLAG__)   (COMP12->ICFR = (__FLAG__))

+

+/** @brief  Clear the COMP C1I  flag.

+  * @retval None

+  */

+#define __HAL_COMP_CLEAR_C1IFLAG()   __HAL_COMP_CLEAR_FLAG( COMP_CLEAR_C1IF)

+

+/** @brief  Clear the COMP C2I  flag.

+  * @retval None

+  */

+#define __HAL_COMP_CLEAR_C2IFLAG()   __HAL_COMP_CLEAR_FLAG( COMP_CLEAR_C2IF)

+

+/** @brief  Enable the specified COMP interrupt.

+  * @param  __HANDLE__: specifies the COMP Handle.

+  * @param  __INTERRUPT__: specifies the COMP interrupt source to enable.

+  *          This parameter can be one of the following values:

+  *            @arg COMP_CFGRx_ITEN :  Comparator  interrupt

+  * @retval None

+  */

+#define __HAL_COMP_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ( ((__HANDLE__)->Instance->CFGR) |= (__INTERRUPT__) )

+

+/** @brief  Disable the specified COMP interrupt.

+  * @param  __HANDLE__: specifies the COMP Handle.

+  * @param  __INTERRUPT__: specifies the COMP interrupt source to enable.

+  *          This parameter can be one of the following values:

+  *            @arg COMP_CFGRx_ITEN :  Comparator  interrupt

+  * @retval None

+  */

+#define __HAL_COMP_DISABLE_IT(__HANDLE__,__INTERRUPT__) (((__HANDLE__)->Instance->CFGR) &= ~(__INTERRUPT__))

+

+/**

+  * @}

+  */

+/** @brief  Enable the specified bit in the Option register.

+  * @param  __AF__: specifies the Alternate Function source selection .

+  *          This parameter can be one of the following values:

+  *            @arg COMP_OR_AFOPA6  :  Alternate Function PA6 source selection

+  *            @arg COMP_OR_AFOPA8  :  Alternate Function PA8 source selection

+  *            @arg COMP_OR_AFOPB12 :  Alternate Function PB12 source selection

+  *            @arg COMP_OR_AFOPE6  :  Alternate Function PE6 source selection

+  *            @arg COMP_OR_AFOPE15 :  Alternate Function PE15 source selection

+  *            @arg COMP_OR_AFOPG2  :  Alternate Function PG2 source selection

+  *            @arg COMP_OR_AFOPG3  :  Alternate Function PG3 source selection

+  *            @arg COMP_OR_AFOPG4  :  Alternate Function PG4 source selection

+  *            @arg COMP_OR_AFOPI1  :  Alternate Function PI1 source selection

+  *            @arg COMP_OR_AFOPI4  :  Alternate Function PI4 source selection 

+  *            @arg COMP_OR_AFOPK2  :  Alternate Function PK2 source selection

+  * @retval None

+  */

+#define __HAL_COMP_ENABLE_OR(__AF__) SET_BIT(COMP12->OR, (__AF__))

+

+/** @brief  Disable the specified bit in the Option register.

+  * @param  __AF__: specifies the Alternate Function source selection .

+  *          This parameter can be one of the following values:

+  *            @arg COMP_OR_AFOPA6  :  Alternate Function PA6 source selection

+  *            @arg COMP_OR_AFOPA8  :  Alternate Function PA8 source selection

+  *            @arg COMP_OR_AFOPB12 :  Alternate Function PB12 source selection

+  *            @arg COMP_OR_AFOPE6  :  Alternate Function PE6 source selection

+  *            @arg COMP_OR_AFOPE15 :  Alternate Function PE15 source selection

+  *            @arg COMP_OR_AFOPG2  :  Alternate Function PG2 source selection

+  *            @arg COMP_OR_AFOPG3  :  Alternate Function PG3 source selection

+  *            @arg COMP_OR_AFOPG4  :  Alternate Function PG4 source selection

+  *            @arg COMP_OR_AFOPI1  :  Alternate Function PI1 source selection

+  *            @arg COMP_OR_AFOPI4  :  Alternate Function PI4 source selection

+  *            @arg COMP_OR_AFOPK2  :  Alternate Function PK2 source selection  

+  * @retval None

+  */

+#define __HAL_COMP_DISABLE_OR(__AF__) CLEAR_BIT(COMP12->OR, (__AF__))

+/**

+  * @}

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup COMP_Private_Constants COMP Private Constants

+  * @{

+  */

+/** @defgroup COMP_ExtiLine COMP EXTI Lines

+  * @{

+  */

+#define COMP_EXTI_LINE_COMP1           (EXTI_IMR1_IM20)  /*!< EXTI line 20 connected to COMP1 output */

+#define COMP_EXTI_LINE_COMP2           (EXTI_IMR1_IM21)  /*!< EXTI line 21 connected to COMP2 output */

+/**

+  * @}

+  */

+/** @defgroup COMP_ExtiLine COMP EXTI Lines

+  * @{

+  */

+#define COMP_EXTI_IT                        ((uint32_t) 0x01)  /*!< EXTI line event with interruption */

+#define COMP_EXTI_EVENT                     ((uint32_t) 0x02)  /*!< EXTI line event only (without interruption) */

+#define COMP_EXTI_RISING                    ((uint32_t) 0x10)  /*!< EXTI line event on rising edge */

+#define COMP_EXTI_FALLING                   ((uint32_t) 0x20)  /*!< EXTI line event on falling edge */

+/**

+  * @}

+  */

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup COMP_Private_Macros COMP Private Macros

+  * @{

+  */

+/** @defgroup COMP_GET_EXTI_LINE COMP Private macros to get EXTI line associated with Comparators 

+  * @{

+  */

+/**

+  * @brief  Get the specified EXTI line for a comparator instance.

+  * @param  __INSTANCE__: specifies the COMP instance.

+  * @retval value of @ref COMP_ExtiLine

+  */

+#define COMP_GET_EXTI_LINE(__INSTANCE__)             (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \

+                                                      COMP_EXTI_LINE_COMP2)

+/**

+  * @}

+  */

+/** @defgroup COMP_IS_COMP_Definitions COMP private macros to check input parameters

+  * @{

+  */

+#define IS_COMP_WINDOWMODE(__WINDOWMODE__)  (((__WINDOWMODE__) == COMP_WINDOWMODE_DISABLE)                || \

+                                             ((__WINDOWMODE__) == COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON)  )

+

+#define IS_COMP_POWERMODE(__POWERMODE__)    (((__POWERMODE__) == COMP_POWERMODE_HIGHSPEED)    || \

+                                             ((__POWERMODE__) == COMP_POWERMODE_MEDIUMSPEED)  || \

+                                             ((__POWERMODE__) == COMP_POWERMODE_ULTRALOWPOWER)  )

+

+#if defined (COMP_CFGRx_INP2SEL)

+#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \

+                                                               ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2) || \

+                                                               ((__INPUT_PLUS__) == COMP_INPUT_PLUS_DAC2_CH1))

+#else

+#define IS_COMP_INPUT_PLUS(__COMP_INSTANCE__, __INPUT_PLUS__) (((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO1) || \

+                                                               ((__INPUT_PLUS__) == COMP_INPUT_PLUS_IO2))                                                              

+#endif                                                             

+

+

+#if defined (COMP_CFGRx_INMSEL_3)

+#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)     || \

+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)     || \

+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)     || \

+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)        || \

+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)       || \

+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2)       || \

+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)            || \

+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2)            || \

+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_TPSENS_DAC2CH1) || \

+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VBAT_VDDAP))

+#else                                          

+#define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT)  || \

+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT)  || \

+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT)  || \

+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_VREFINT)     || \

+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH1)    || \

+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_DAC1_CH2)    || \

+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO1)         || \

+                                                                 ((__INPUT_MINUS__) == COMP_INPUT_MINUS_IO2))                                                                  

+#endif

+

+#define IS_COMP_HYSTERESIS(__HYSTERESIS__)  (((__HYSTERESIS__) == COMP_HYSTERESIS_NONE)   || \

+                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_LOW)    || \

+                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_MEDIUM) || \

+                                             ((__HYSTERESIS__) == COMP_HYSTERESIS_HIGH))

+

+#define IS_COMP_OUTPUTPOL(__POL__)          (((__POL__) == COMP_OUTPUTPOL_NONINVERTED) || \

+                                             ((__POL__) == COMP_OUTPUTPOL_INVERTED))

+

+#define IS_COMP_BLANKINGSRCE(__SOURCE__)    (((__SOURCE__) == COMP_BLANKINGSRC_NONE)      || \

+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5)  || \

+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3)  || \

+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC3)  || \

+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM3_OC4)  || \

+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM8_OC5)  || \

+                                             ((__SOURCE__) == COMP_BLANKINGSRC_TIM15_OC1))

+

+

+#define IS_COMP_TRIGGERMODE(__MODE__)       (((__MODE__) == COMP_TRIGGERMODE_NONE)                 || \

+                                             ((__MODE__) == COMP_TRIGGERMODE_IT_RISING)            || \

+                                             ((__MODE__) == COMP_TRIGGERMODE_IT_FALLING)           || \

+                                             ((__MODE__) == COMP_TRIGGERMODE_IT_RISING_FALLING)    || \

+                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING)         || \

+                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_FALLING)        || \

+                                             ((__MODE__) == COMP_TRIGGERMODE_EVENT_RISING_FALLING))

+

+#define IS_COMP_OUTPUT_LEVEL(__OUTPUT_LEVEL__) (((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_LOW)     || \

+                                                ((__OUTPUT_LEVEL__) == COMP_OUTPUT_LEVEL_HIGH))

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup COMP_Exported_Functions

+  * @{

+  */

+

+/** @addtogroup COMP_Exported_Functions_Group1

+  * @{

+  */

+/* Initialization and de-initialization functions  **********************************/

+HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);

+HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp);

+void              HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);

+void              HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);

+#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)

+/* Callbacks Register/UnRegister functions  ***********************************/

+HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID);

+#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/* IO operation functions  *****************************************************/

+/** @addtogroup COMP_Exported_Functions_Group2

+  * @{

+  */

+HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);

+HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);

+HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp);

+HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp);

+void              HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);

+

+/**

+  * @}

+  */

+

+/* Peripheral Control functions  ************************************************/

+/** @addtogroup COMP_Exported_Functions_Group3

+  * @{

+  */

+HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);

+uint32_t          HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);

+/* Callback in Interrupt mode */

+void              HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);

+/**

+  * @}

+  */

+

+/* Peripheral State functions  **************************************************/

+/** @addtogroup COMP_Exported_Functions_Group4

+  * @{

+  */

+HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);

+uint32_t              HAL_COMP_GetError(COMP_HandleTypeDef *hcomp);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_COMP_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_conf_template.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_conf_template.h
new file mode 100644
index 0000000000..bf33ee73fa
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_conf_template.h
@@ -0,0 +1,501 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_conf_template.h

+  * @author  MCD Application Team

+  * @brief   HAL configuration template file.

+  *          This file should be copied to the application folder and renamed

+  *          to stm32h7xx_hal_conf.h.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_CONF_H

+#define STM32H7xx_HAL_CONF_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Exported types ------------------------------------------------------------*/

+/* Exported constants --------------------------------------------------------*/

+

+/* ########################## Module Selection ############################## */

+/**

+  * @brief This is the list of modules to be used in the HAL driver

+  */

+#define HAL_MODULE_ENABLED

+#define HAL_ADC_MODULE_ENABLED

+#define HAL_CEC_MODULE_ENABLED

+#define HAL_COMP_MODULE_ENABLED

+#define HAL_CORTEX_MODULE_ENABLED

+#define HAL_CRC_MODULE_ENABLED

+#define HAL_CRYP_MODULE_ENABLED

+#define HAL_DAC_MODULE_ENABLED

+#define HAL_DCMI_MODULE_ENABLED

+#define HAL_DFSDM_MODULE_ENABLED

+#define HAL_DMA_MODULE_ENABLED

+#define HAL_DMA2D_MODULE_ENABLED

+#define HAL_DTS_MODULE_ENABLED

+#define HAL_DSI_MODULE_ENABLED

+#define HAL_ETH_MODULE_ENABLED

+#define HAL_EXTI_MODULE_ENABLED

+#define HAL_FDCAN_MODULE_ENABLED

+#define HAL_FLASH_MODULE_ENABLED

+#define HAL_GFXMMU_MODULE_ENABLED

+#define HAL_GPIO_MODULE_ENABLED

+#define HAL_HASH_MODULE_ENABLED

+#define HAL_HCD_MODULE_ENABLED

+#define HAL_HRTIM_MODULE_ENABLED

+#define HAL_HSEM_MODULE_ENABLED

+#define HAL_I2C_MODULE_ENABLED

+#define HAL_I2S_MODULE_ENABLED

+#define HAL_IRDA_MODULE_ENABLED

+#define HAL_IWDG_MODULE_ENABLED

+#define HAL_JPEG_MODULE_ENABLED

+#define HAL_LPTIM_MODULE_ENABLED

+#define HAL_LTDC_MODULE_ENABLED

+#define HAL_MDIOS_MODULE_ENABLED

+#define HAL_MDMA_MODULE_ENABLED

+#define HAL_MMC_MODULE_ENABLED

+#define HAL_NAND_MODULE_ENABLED

+#define HAL_NOR_MODULE_ENABLED

+#define HAL_OPAMP_MODULE_ENABLED

+#define HAL_OSPI_MODULE_ENABLED

+#define HAL_OTFDEC_MODULE_ENABLED

+#define HAL_PCD_MODULE_ENABLED

+#define HAL_PWR_MODULE_ENABLED

+#define HAL_PSSI_MODULE_ENABLED

+#define HAL_QSPI_MODULE_ENABLED

+#define HAL_RAMECC_MODULE_ENABLED

+#define HAL_RCC_MODULE_ENABLED

+#define HAL_RNG_MODULE_ENABLED

+#define HAL_RTC_MODULE_ENABLED

+#define HAL_SAI_MODULE_ENABLED

+#define HAL_SD_MODULE_ENABLED

+#define HAL_SDRAM_MODULE_ENABLED

+#define HAL_SMARTCARD_MODULE_ENABLED

+#define HAL_SMBUS_MODULE_ENABLED

+#define HAL_SPDIFRX_MODULE_ENABLED

+#define HAL_SPI_MODULE_ENABLED

+#define HAL_SRAM_MODULE_ENABLED

+#define HAL_SWPMI_MODULE_ENABLED

+#define HAL_TIM_MODULE_ENABLED

+#define HAL_UART_MODULE_ENABLED

+#define HAL_USART_MODULE_ENABLED

+#define HAL_WWDG_MODULE_ENABLED

+

+/* ########################## Oscillator Values adaptation ####################*/

+/**

+  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.

+  *        This value is used by the RCC HAL module to compute the system frequency

+  *        (when HSE is used as system clock source, directly or through the PLL).

+  */

+#if !defined  (HSE_VALUE)

+#define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */

+#endif /* HSE_VALUE */

+

+#if !defined  (HSE_STARTUP_TIMEOUT)

+  #define HSE_STARTUP_TIMEOUT    ((uint32_t)5000)   /*!< Time out for HSE start up, in ms */

+#endif /* HSE_STARTUP_TIMEOUT */

+

+/**

+  * @brief Internal  oscillator (CSI) default value.

+  *        This value is the default CSI value after Reset.

+  */

+#if !defined  (CSI_VALUE)

+  #define CSI_VALUE    ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/

+#endif /* CSI_VALUE */

+

+/**

+  * @brief Internal High Speed oscillator (HSI) value.

+  *        This value is used by the RCC HAL module to compute the system frequency

+  *        (when HSI is used as system clock source, directly or through the PLL).

+  */

+#if !defined  (HSI_VALUE)

+  #define HSI_VALUE    ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/

+#endif /* HSI_VALUE */

+

+/**

+  * @brief External Low Speed oscillator (LSE) value.

+  *        This value is used by the UART, RTC HAL module to compute the system frequency

+  */

+#if !defined  (LSE_VALUE)

+  #define LSE_VALUE    ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/

+#endif /* LSE_VALUE */

+

+

+#if !defined  (LSE_STARTUP_TIMEOUT)

+  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000)   /*!< Time out for LSE start up, in ms */

+#endif /* LSE_STARTUP_TIMEOUT */

+

+#if !defined  (LSI_VALUE)

+  #define LSI_VALUE  ((uint32_t)32000)      /*!< LSI Typical Value in Hz*/

+#endif /* LSI_VALUE */                      /*!< Value of the Internal Low Speed oscillator in Hz

+                                              The real value may vary depending on the variations

+                                              in voltage and temperature.*/

+

+/**

+  * @brief External clock source for I2S peripheral

+  *        This value is used by the I2S HAL module to compute the I2S clock source

+  *        frequency, this source is inserted directly through I2S_CKIN pad.

+  */

+#if !defined  (EXTERNAL_CLOCK_VALUE)

+  #define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the External clock in Hz*/

+#endif /* EXTERNAL_CLOCK_VALUE */

+

+/* Tip: To avoid modifying this file each time you need to use different HSE,

+   ===  you can define the HSE value in your toolchain compiler preprocessor. */

+

+/* ########################### System Configuration ######################### */

+/**

+  * @brief This is the HAL system configuration section

+  */

+#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */

+#define  TICK_INT_PRIORITY            ((uint32_t)0x0F) /*!< tick interrupt priority */

+#define  USE_RTOS                     0

+#define  USE_SD_TRANSCEIVER           1U               /*!< use uSD Transceiver */

+#define  USE_SPI_CRC                  1U               /*!< use CRC in SPI */

+

+#define  USE_HAL_ADC_REGISTER_CALLBACKS     0U /* ADC register callback disabled     */

+#define  USE_HAL_CEC_REGISTER_CALLBACKS     0U /* CEC register callback disabled     */

+#define  USE_HAL_COMP_REGISTER_CALLBACKS    0U /* COMP register callback disabled    */

+#define  USE_HAL_CRYP_REGISTER_CALLBACKS    0U /* CRYP register callback disabled    */

+#define  USE_HAL_DAC_REGISTER_CALLBACKS     0U /* DAC register callback disabled     */

+#define  USE_HAL_DCMI_REGISTER_CALLBACKS    0U /* DCMI register callback disabled    */

+#define  USE_HAL_DFSDM_REGISTER_CALLBACKS   0U /* DFSDM register callback disabled   */

+#define  USE_HAL_DMA2D_REGISTER_CALLBACKS   0U /* DMA2D register callback disabled   */

+#define  USE_HAL_DSI_REGISTER_CALLBACKS     0U /* DSI register callback disabled     */

+#define  USE_HAL_DTS_REGISTER_CALLBACKS     0U /* DTS register callback disabled     */

+#define  USE_HAL_ETH_REGISTER_CALLBACKS     0U /* ETH register callback disabled     */

+#define  USE_HAL_FDCAN_REGISTER_CALLBACKS   0U /* FDCAN register callback disabled   */

+#define  USE_HAL_NAND_REGISTER_CALLBACKS    0U /* NAND register callback disabled    */

+#define  USE_HAL_NOR_REGISTER_CALLBACKS     0U /* NOR register callback disabled     */

+#define  USE_HAL_SDRAM_REGISTER_CALLBACKS   0U /* SDRAM register callback disabled   */

+#define  USE_HAL_SRAM_REGISTER_CALLBACKS    0U /* SRAM register callback disabled    */

+#define  USE_HAL_HASH_REGISTER_CALLBACKS    0U /* HASH register callback disabled    */

+#define  USE_HAL_HCD_REGISTER_CALLBACKS     0U /* HCD register callback disabled     */

+#define  USE_HAL_GFXMMU_REGISTER_CALLBACKS  0U /* GFXMMU register callback disabled  */

+#define  USE_HAL_HRTIM_REGISTER_CALLBACKS   0U /* HRTIM register callback disabled   */

+#define  USE_HAL_I2C_REGISTER_CALLBACKS     0U /* I2C register callback disabled     */

+#define  USE_HAL_I2S_REGISTER_CALLBACKS     0U /* I2S register callback disabled     */

+#define  USE_HAL_IRDA_REGISTER_CALLBACKS    0U /* IRDA register callback disabled    */

+#define  USE_HAL_JPEG_REGISTER_CALLBACKS    0U /* JPEG register callback disabled    */

+#define  USE_HAL_LPTIM_REGISTER_CALLBACKS   0U /* LPTIM register callback disabled   */

+#define  USE_HAL_LTDC_REGISTER_CALLBACKS    0U /* LTDC register callback disabled    */

+#define  USE_HAL_MDIOS_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */

+#define  USE_HAL_MMC_REGISTER_CALLBACKS     0U /* MMC register callback disabled     */

+#define  USE_HAL_OPAMP_REGISTER_CALLBACKS   0U /* MDIO register callback disabled    */

+#define  USE_HAL_OSPI_REGISTER_CALLBACKS    0U /* OSPI register callback disabled    */

+#define  USE_HAL_OTFDEC_REGISTER_CALLBACKS  0U /* OTFDEC register callback disabled  */

+#define  USE_HAL_PCD_REGISTER_CALLBACKS     0U /* PCD register callback disabled     */

+#define  USE_HAL_QSPI_REGISTER_CALLBACKS    0U /* QSPI register callback disabled    */

+#define  USE_HAL_RNG_REGISTER_CALLBACKS     0U /* RNG register callback disabled     */

+#define  USE_HAL_RTC_REGISTER_CALLBACKS     0U /* RTC register callback disabled     */

+#define  USE_HAL_SAI_REGISTER_CALLBACKS     0U /* SAI register callback disabled     */

+#define  USE_HAL_SD_REGISTER_CALLBACKS      0U /* SD register callback disabled      */

+#define  USE_HAL_SMARTCARD_REGISTER_CALLBACKS  0U /* SMARTCARD register callback disabled */

+#define  USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */

+#define  USE_HAL_SMBUS_REGISTER_CALLBACKS   0U /* SMBUS register callback disabled   */

+#define  USE_HAL_SPI_REGISTER_CALLBACKS     0U /* SPI register callback disabled     */

+#define  USE_HAL_SWPMI_REGISTER_CALLBACKS   0U /* SWPMI register callback disabled   */

+#define  USE_HAL_TIM_REGISTER_CALLBACKS     0U /* TIM register callback disabled     */

+#define  USE_HAL_UART_REGISTER_CALLBACKS    0U /* UART register callback disabled    */

+#define  USE_HAL_USART_REGISTER_CALLBACKS   0U /* USART register callback disabled   */

+#define  USE_HAL_WWDG_REGISTER_CALLBACKS    0U /* WWDG register callback disabled    */

+

+/* ########################### Ethernet Configuration ######################### */

+#define ETH_TX_DESC_CNT         4  /* number of Ethernet Tx DMA descriptors */

+#define ETH_RX_DESC_CNT         4  /* number of Ethernet Rx DMA descriptors */

+

+#define ETH_MAC_ADDR0    ((uint8_t)0x02)

+#define ETH_MAC_ADDR1    ((uint8_t)0x00)

+#define ETH_MAC_ADDR2    ((uint8_t)0x00)

+#define ETH_MAC_ADDR3    ((uint8_t)0x00)

+#define ETH_MAC_ADDR4    ((uint8_t)0x00)

+#define ETH_MAC_ADDR5    ((uint8_t)0x00)

+

+/* ########################## Assert Selection ############################## */

+/**

+  * @brief Uncomment the line below to expanse the "assert_param" macro in the

+  *        HAL drivers code

+  */

+/* #define USE_FULL_ASSERT    1 */

+

+

+/* Includes ------------------------------------------------------------------*/

+/**

+  * @brief Include module's header file

+  */

+

+#ifdef HAL_RCC_MODULE_ENABLED

+  #include "stm32h7xx_hal_rcc.h"

+#endif /* HAL_RCC_MODULE_ENABLED */

+

+#ifdef HAL_GPIO_MODULE_ENABLED

+  #include "stm32h7xx_hal_gpio.h"

+#endif /* HAL_GPIO_MODULE_ENABLED */

+

+#ifdef HAL_DMA_MODULE_ENABLED

+  #include "stm32h7xx_hal_dma.h"

+#endif /* HAL_DMA_MODULE_ENABLED */

+

+#ifdef HAL_MDMA_MODULE_ENABLED

+ #include "stm32h7xx_hal_mdma.h"

+#endif /* HAL_MDMA_MODULE_ENABLED */

+

+#ifdef HAL_HASH_MODULE_ENABLED

+  #include "stm32h7xx_hal_hash.h"

+#endif /* HAL_HASH_MODULE_ENABLED */

+

+#ifdef HAL_DCMI_MODULE_ENABLED

+  #include "stm32h7xx_hal_dcmi.h"

+#endif /* HAL_DCMI_MODULE_ENABLED */

+

+#ifdef HAL_DMA2D_MODULE_ENABLED

+  #include "stm32h7xx_hal_dma2d.h"

+#endif /* HAL_DMA2D_MODULE_ENABLED */

+

+#ifdef HAL_DSI_MODULE_ENABLED

+  #include "stm32h7xx_hal_dsi.h"

+#endif /* HAL_DSI_MODULE_ENABLED */

+

+#ifdef HAL_DFSDM_MODULE_ENABLED

+  #include "stm32h7xx_hal_dfsdm.h"

+#endif /* HAL_DFSDM_MODULE_ENABLED */

+

+#ifdef HAL_DTS_MODULE_ENABLED

+ #include "stm32h7xx_hal_dts.h"

+#endif /* HAL_DTS_MODULE_ENABLED */

+

+#ifdef HAL_ETH_MODULE_ENABLED

+  #include "stm32h7xx_hal_eth.h"

+#endif /* HAL_ETH_MODULE_ENABLED */

+

+#ifdef HAL_EXTI_MODULE_ENABLED

+  #include "stm32h7xx_hal_exti.h"

+#endif /* HAL_EXTI_MODULE_ENABLED */

+

+#ifdef HAL_CORTEX_MODULE_ENABLED

+  #include "stm32h7xx_hal_cortex.h"

+#endif /* HAL_CORTEX_MODULE_ENABLED */

+

+#ifdef HAL_ADC_MODULE_ENABLED

+  #include "stm32h7xx_hal_adc.h"

+#endif /* HAL_ADC_MODULE_ENABLED */

+

+#ifdef HAL_FDCAN_MODULE_ENABLED

+  #include "stm32h7xx_hal_fdcan.h"

+#endif /* HAL_FDCAN_MODULE_ENABLED */

+

+#ifdef HAL_CEC_MODULE_ENABLED

+  #include "stm32h7xx_hal_cec.h"

+#endif /* HAL_CEC_MODULE_ENABLED */

+

+#ifdef HAL_COMP_MODULE_ENABLED

+  #include "stm32h7xx_hal_comp.h"

+#endif /* HAL_COMP_MODULE_ENABLED */

+

+#ifdef HAL_CRC_MODULE_ENABLED

+  #include "stm32h7xx_hal_crc.h"

+#endif /* HAL_CRC_MODULE_ENABLED */

+

+#ifdef HAL_CRYP_MODULE_ENABLED

+  #include "stm32h7xx_hal_cryp.h"

+#endif /* HAL_CRYP_MODULE_ENABLED */

+

+#ifdef HAL_DAC_MODULE_ENABLED

+  #include "stm32h7xx_hal_dac.h"

+#endif /* HAL_DAC_MODULE_ENABLED */

+

+#ifdef HAL_FLASH_MODULE_ENABLED

+  #include "stm32h7xx_hal_flash.h"

+#endif /* HAL_FLASH_MODULE_ENABLED */

+

+#ifdef HAL_GFXMMU_MODULE_ENABLED

+  #include "stm32h7xx_hal_gfxmmu.h"

+#endif /* HAL_GFXMMU_MODULE_ENABLED */

+

+#ifdef HAL_HRTIM_MODULE_ENABLED

+  #include "stm32h7xx_hal_hrtim.h"

+#endif /* HAL_HRTIM_MODULE_ENABLED */

+

+#ifdef HAL_HSEM_MODULE_ENABLED

+  #include "stm32h7xx_hal_hsem.h"

+#endif /* HAL_HSEM_MODULE_ENABLED */

+

+#ifdef HAL_SRAM_MODULE_ENABLED

+  #include "stm32h7xx_hal_sram.h"

+#endif /* HAL_SRAM_MODULE_ENABLED */

+

+#ifdef HAL_NOR_MODULE_ENABLED

+  #include "stm32h7xx_hal_nor.h"

+#endif /* HAL_NOR_MODULE_ENABLED */

+

+#ifdef HAL_NAND_MODULE_ENABLED

+  #include "stm32h7xx_hal_nand.h"

+#endif /* HAL_NAND_MODULE_ENABLED */

+

+#ifdef HAL_I2C_MODULE_ENABLED

+ #include "stm32h7xx_hal_i2c.h"

+#endif /* HAL_I2C_MODULE_ENABLED */

+

+#ifdef HAL_I2S_MODULE_ENABLED

+ #include "stm32h7xx_hal_i2s.h"

+#endif /* HAL_I2S_MODULE_ENABLED */

+

+#ifdef HAL_IWDG_MODULE_ENABLED

+ #include "stm32h7xx_hal_iwdg.h"

+#endif /* HAL_IWDG_MODULE_ENABLED */

+

+#ifdef HAL_JPEG_MODULE_ENABLED

+ #include "stm32h7xx_hal_jpeg.h"

+#endif /* HAL_JPEG_MODULE_ENABLED */

+

+#ifdef HAL_MDIOS_MODULE_ENABLED

+ #include "stm32h7xx_hal_mdios.h"

+#endif /* HAL_MDIOS_MODULE_ENABLED */

+

+#ifdef HAL_MMC_MODULE_ENABLED

+ #include "stm32h7xx_hal_mmc.h"

+#endif /* HAL_MMC_MODULE_ENABLED */

+

+#ifdef HAL_LPTIM_MODULE_ENABLED

+#include "stm32h7xx_hal_lptim.h"

+#endif /* HAL_LPTIM_MODULE_ENABLED */

+

+#ifdef HAL_LTDC_MODULE_ENABLED

+#include "stm32h7xx_hal_ltdc.h"

+#endif /* HAL_LTDC_MODULE_ENABLED */

+

+#ifdef HAL_OPAMP_MODULE_ENABLED

+#include "stm32h7xx_hal_opamp.h"

+#endif /* HAL_OPAMP_MODULE_ENABLED */

+

+#ifdef HAL_OSPI_MODULE_ENABLED

+ #include "stm32h7xx_hal_ospi.h"

+#endif /* HAL_OSPI_MODULE_ENABLED */

+

+#ifdef HAL_OTFDEC_MODULE_ENABLED

+#include "stm32h7xx_hal_otfdec.h"

+#endif /* HAL_OTFDEC_MODULE_ENABLED */

+

+#ifdef HAL_PSSI_MODULE_ENABLED

+ #include "stm32h7xx_hal_pssi.h"

+#endif /* HAL_PSSI_MODULE_ENABLED */

+

+#ifdef HAL_PWR_MODULE_ENABLED

+ #include "stm32h7xx_hal_pwr.h"

+#endif /* HAL_PWR_MODULE_ENABLED */

+

+#ifdef HAL_QSPI_MODULE_ENABLED

+ #include "stm32h7xx_hal_qspi.h"

+#endif /* HAL_QSPI_MODULE_ENABLED */

+

+#ifdef HAL_RAMECC_MODULE_ENABLED

+ #include "stm32h7xx_hal_ramecc.h"

+#endif /* HAL_RAMECC_MODULE_ENABLED */

+

+#ifdef HAL_RNG_MODULE_ENABLED

+ #include "stm32h7xx_hal_rng.h"

+#endif /* HAL_RNG_MODULE_ENABLED */

+

+#ifdef HAL_RTC_MODULE_ENABLED

+ #include "stm32h7xx_hal_rtc.h"

+#endif /* HAL_RTC_MODULE_ENABLED */

+

+#ifdef HAL_SAI_MODULE_ENABLED

+ #include "stm32h7xx_hal_sai.h"

+#endif /* HAL_SAI_MODULE_ENABLED */

+

+#ifdef HAL_SD_MODULE_ENABLED

+ #include "stm32h7xx_hal_sd.h"

+#endif /* HAL_SD_MODULE_ENABLED */

+

+#ifdef HAL_SDRAM_MODULE_ENABLED

+ #include "stm32h7xx_hal_sdram.h"

+#endif /* HAL_SDRAM_MODULE_ENABLED */

+

+#ifdef HAL_SPI_MODULE_ENABLED

+ #include "stm32h7xx_hal_spi.h"

+#endif /* HAL_SPI_MODULE_ENABLED */

+

+#ifdef HAL_SPDIFRX_MODULE_ENABLED

+ #include "stm32h7xx_hal_spdifrx.h"

+#endif /* HAL_SPDIFRX_MODULE_ENABLED */

+

+#ifdef HAL_SWPMI_MODULE_ENABLED

+ #include "stm32h7xx_hal_swpmi.h"

+#endif /* HAL_SWPMI_MODULE_ENABLED */

+

+#ifdef HAL_TIM_MODULE_ENABLED

+ #include "stm32h7xx_hal_tim.h"

+#endif /* HAL_TIM_MODULE_ENABLED */

+

+#ifdef HAL_UART_MODULE_ENABLED

+ #include "stm32h7xx_hal_uart.h"

+#endif /* HAL_UART_MODULE_ENABLED */

+

+#ifdef HAL_USART_MODULE_ENABLED

+ #include "stm32h7xx_hal_usart.h"

+#endif /* HAL_USART_MODULE_ENABLED */

+

+#ifdef HAL_IRDA_MODULE_ENABLED

+ #include "stm32h7xx_hal_irda.h"

+#endif /* HAL_IRDA_MODULE_ENABLED */

+

+#ifdef HAL_SMARTCARD_MODULE_ENABLED

+ #include "stm32h7xx_hal_smartcard.h"

+#endif /* HAL_SMARTCARD_MODULE_ENABLED */

+

+#ifdef HAL_SMBUS_MODULE_ENABLED

+ #include "stm32h7xx_hal_smbus.h"

+#endif /* HAL_SMBUS_MODULE_ENABLED */

+

+#ifdef HAL_WWDG_MODULE_ENABLED

+ #include "stm32h7xx_hal_wwdg.h"

+#endif /* HAL_WWDG_MODULE_ENABLED */

+

+#ifdef HAL_PCD_MODULE_ENABLED

+ #include "stm32h7xx_hal_pcd.h"

+#endif /* HAL_PCD_MODULE_ENABLED */

+

+#ifdef HAL_HCD_MODULE_ENABLED

+ #include "stm32h7xx_hal_hcd.h"

+#endif /* HAL_HCD_MODULE_ENABLED */

+

+/* Exported macro ------------------------------------------------------------*/

+#ifdef  USE_FULL_ASSERT

+/**

+  * @brief  The assert_param macro is used for function's parameters check.

+  * @param  expr: If expr is false, it calls assert_failed function

+  *         which reports the name of the source file and the source

+  *         line number of the call that failed.

+  *         If expr is true, it returns no value.

+  * @retval None

+  */

+  #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__))

+/* Exported functions ------------------------------------------------------- */

+  void assert_failed(uint8_t *file, uint32_t line);

+#else

+  #define assert_param(expr) ((void)0U)

+#endif /* USE_FULL_ASSERT */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_CONF_H */

+

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_cortex.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_cortex.h
new file mode 100644
index 0000000000..4eca439036
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_cortex.h
@@ -0,0 +1,461 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_cortex.h

+  * @author  MCD Application Team

+  * @brief   Header file of CORTEX HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_CORTEX_H

+#define STM32H7xx_HAL_CORTEX_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup CORTEX

+  * @{

+  */

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup CORTEX_Exported_Types Cortex Exported Types

+  * @{

+  */

+

+#if (__MPU_PRESENT == 1)

+/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition

+  * @brief  MPU Region initialization structure

+  * @{

+  */

+typedef struct

+{

+  uint8_t                Enable;                /*!< Specifies the status of the region.

+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Enable                 */

+  uint8_t                Number;                /*!< Specifies the number of the region to protect.

+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Number                 */

+  uint32_t               BaseAddress;           /*!< Specifies the base address of the region to protect.                           */

+  uint8_t                Size;                  /*!< Specifies the size of the region to protect.

+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Size                   */

+  uint8_t                SubRegionDisable;      /*!< Specifies the number of the subregion protection to disable.

+                                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF    */

+  uint8_t                TypeExtField;          /*!< Specifies the TEX field level.

+                                                     This parameter can be a value of @ref CORTEX_MPU_TEX_Levels                    */

+  uint8_t                AccessPermission;      /*!< Specifies the region access permission type.

+                                                     This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes  */

+  uint8_t                DisableExec;           /*!< Specifies the instruction access status.

+                                                     This parameter can be a value of @ref CORTEX_MPU_Instruction_Access            */

+  uint8_t                IsShareable;           /*!< Specifies the shareability status of the protected region.

+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Shareable              */

+  uint8_t                IsCacheable;           /*!< Specifies the cacheable status of the region protected.

+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable              */

+  uint8_t                IsBufferable;          /*!< Specifies the bufferable status of the protected region.

+                                                     This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable             */

+}MPU_Region_InitTypeDef;

+/**

+  * @}

+  */

+#endif /* __MPU_PRESENT */

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+

+/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants

+  * @{

+  */

+

+/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group

+  * @{

+  */

+#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority

+                                                                 4 bits for subpriority */

+#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority

+                                                                 3 bits for subpriority */

+#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority

+                                                                 2 bits for subpriority */

+#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority

+                                                                 1 bits for subpriority */

+#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority

+                                                                 0 bits for subpriority */

+/**

+  * @}

+  */

+

+/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source

+  * @{

+  */

+#define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000)

+#define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004)

+

+/**

+  * @}

+  */

+

+#if (__MPU_PRESENT == 1)

+/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control

+  * @{

+  */

+#define  MPU_HFNMI_PRIVDEF_NONE      ((uint32_t)0x00000000)

+#define  MPU_HARDFAULT_NMI           ((uint32_t)0x00000002)

+#define  MPU_PRIVILEGED_DEFAULT      ((uint32_t)0x00000004)

+#define  MPU_HFNMI_PRIVDEF           ((uint32_t)0x00000006)

+/**

+  * @}

+  */

+

+/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable

+  * @{

+  */

+#define  MPU_REGION_ENABLE     ((uint8_t)0x01)

+#define  MPU_REGION_DISABLE    ((uint8_t)0x00)

+/**

+  * @}

+  */

+

+/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access

+  * @{

+  */

+#define  MPU_INSTRUCTION_ACCESS_ENABLE      ((uint8_t)0x00)

+#define  MPU_INSTRUCTION_ACCESS_DISABLE     ((uint8_t)0x01)

+/**

+  * @}

+  */

+

+/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable

+  * @{

+  */

+#define  MPU_ACCESS_SHAREABLE        ((uint8_t)0x01)

+#define  MPU_ACCESS_NOT_SHAREABLE    ((uint8_t)0x00)

+/**

+  * @}

+  */

+

+/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable

+  * @{

+  */

+#define  MPU_ACCESS_CACHEABLE         ((uint8_t)0x01)

+#define  MPU_ACCESS_NOT_CACHEABLE     ((uint8_t)0x00)

+/**

+  * @}

+  */

+

+/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable

+  * @{

+  */

+#define  MPU_ACCESS_BUFFERABLE         ((uint8_t)0x01)

+#define  MPU_ACCESS_NOT_BUFFERABLE     ((uint8_t)0x00)

+/**

+  * @}

+  */

+

+/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels

+  * @{

+  */

+#define  MPU_TEX_LEVEL0    ((uint8_t)0x00)

+#define  MPU_TEX_LEVEL1    ((uint8_t)0x01)

+#define  MPU_TEX_LEVEL2    ((uint8_t)0x02)

+/**

+  * @}

+  */

+

+/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size

+  * @{

+  */

+#define   MPU_REGION_SIZE_32B      ((uint8_t)0x04)

+#define   MPU_REGION_SIZE_64B      ((uint8_t)0x05)

+#define   MPU_REGION_SIZE_128B     ((uint8_t)0x06)

+#define   MPU_REGION_SIZE_256B     ((uint8_t)0x07)

+#define   MPU_REGION_SIZE_512B     ((uint8_t)0x08)

+#define   MPU_REGION_SIZE_1KB      ((uint8_t)0x09)

+#define   MPU_REGION_SIZE_2KB      ((uint8_t)0x0A)

+#define   MPU_REGION_SIZE_4KB      ((uint8_t)0x0B)

+#define   MPU_REGION_SIZE_8KB      ((uint8_t)0x0C)

+#define   MPU_REGION_SIZE_16KB     ((uint8_t)0x0D)

+#define   MPU_REGION_SIZE_32KB     ((uint8_t)0x0E)

+#define   MPU_REGION_SIZE_64KB     ((uint8_t)0x0F)

+#define   MPU_REGION_SIZE_128KB    ((uint8_t)0x10)

+#define   MPU_REGION_SIZE_256KB    ((uint8_t)0x11)

+#define   MPU_REGION_SIZE_512KB    ((uint8_t)0x12)

+#define   MPU_REGION_SIZE_1MB      ((uint8_t)0x13)

+#define   MPU_REGION_SIZE_2MB      ((uint8_t)0x14)

+#define   MPU_REGION_SIZE_4MB      ((uint8_t)0x15)

+#define   MPU_REGION_SIZE_8MB      ((uint8_t)0x16)

+#define   MPU_REGION_SIZE_16MB     ((uint8_t)0x17)

+#define   MPU_REGION_SIZE_32MB     ((uint8_t)0x18)

+#define   MPU_REGION_SIZE_64MB     ((uint8_t)0x19)

+#define   MPU_REGION_SIZE_128MB    ((uint8_t)0x1A)

+#define   MPU_REGION_SIZE_256MB    ((uint8_t)0x1B)

+#define   MPU_REGION_SIZE_512MB    ((uint8_t)0x1C)

+#define   MPU_REGION_SIZE_1GB      ((uint8_t)0x1D)

+#define   MPU_REGION_SIZE_2GB      ((uint8_t)0x1E)

+#define   MPU_REGION_SIZE_4GB      ((uint8_t)0x1F)

+/**

+  * @}

+  */

+

+/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes

+  * @{

+  */

+#define  MPU_REGION_NO_ACCESS      ((uint8_t)0x00)

+#define  MPU_REGION_PRIV_RW        ((uint8_t)0x01)

+#define  MPU_REGION_PRIV_RW_URO    ((uint8_t)0x02)

+#define  MPU_REGION_FULL_ACCESS    ((uint8_t)0x03)

+#define  MPU_REGION_PRIV_RO        ((uint8_t)0x05)

+#define  MPU_REGION_PRIV_RO_URO    ((uint8_t)0x06)

+/**

+  * @}

+  */

+

+/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number

+  * @{

+  */

+#define  MPU_REGION_NUMBER0    ((uint8_t)0x00)

+#define  MPU_REGION_NUMBER1    ((uint8_t)0x01)

+#define  MPU_REGION_NUMBER2    ((uint8_t)0x02)

+#define  MPU_REGION_NUMBER3    ((uint8_t)0x03)

+#define  MPU_REGION_NUMBER4    ((uint8_t)0x04)

+#define  MPU_REGION_NUMBER5    ((uint8_t)0x05)

+#define  MPU_REGION_NUMBER6    ((uint8_t)0x06)

+#define  MPU_REGION_NUMBER7    ((uint8_t)0x07)

+#if !defined(CORE_CM4)

+#define  MPU_REGION_NUMBER8    ((uint8_t)0x08)

+#define  MPU_REGION_NUMBER9    ((uint8_t)0x09)

+#define  MPU_REGION_NUMBER10   ((uint8_t)0x0A)

+#define  MPU_REGION_NUMBER11   ((uint8_t)0x0B)

+#define  MPU_REGION_NUMBER12   ((uint8_t)0x0C)

+#define  MPU_REGION_NUMBER13   ((uint8_t)0x0D)

+#define  MPU_REGION_NUMBER14   ((uint8_t)0x0E)

+#define  MPU_REGION_NUMBER15   ((uint8_t)0x0F)

+#endif /* !defined(CORE_CM4) */

+

+/**

+  * @}

+  */

+#endif /* __MPU_PRESENT */

+

+/**

+  * @}

+  */

+

+

+/* Exported Macros -----------------------------------------------------------*/

+/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+

+

+/** @defgroup CORTEX_CPU_Identifier CORTEX_CPU_Identifier

+  * @{

+  */

+#define CM7_CPUID        ((uint32_t)0x00000003)

+

+#if defined(DUAL_CORE)

+#define CM4_CPUID        ((uint32_t)0x00000001)

+#endif /*DUAL_CORE*/

+/**

+  * @}

+  */

+

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup CORTEX_Exported_Functions

+  * @{

+  */

+

+/** @addtogroup CORTEX_Exported_Functions_Group1

+ * @{

+ */

+/* Initialization and de-initialization functions *****************************/

+void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);

+void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);

+void HAL_NVIC_EnableIRQ(IRQn_Type IRQn);

+void HAL_NVIC_DisableIRQ(IRQn_Type IRQn);

+void HAL_NVIC_SystemReset(void);

+uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);

+/**

+  * @}

+  */

+

+/** @addtogroup CORTEX_Exported_Functions_Group2

+ * @{

+ */

+/* Peripheral Control functions ***********************************************/

+#if (__MPU_PRESENT == 1)

+void HAL_MPU_Enable(uint32_t MPU_Control);

+void HAL_MPU_Disable(void);

+void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);

+#endif /* __MPU_PRESENT */

+uint32_t HAL_NVIC_GetPriorityGrouping(void);

+void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);

+uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);

+void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);

+void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);

+uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);

+void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);

+void HAL_SYSTICK_IRQHandler(void);

+void HAL_SYSTICK_Callback(void);

+uint32_t HAL_GetCurrentCPUID(void);

+

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup CORTEX_Private_Macros CORTEX Private Macros

+  * @{

+  */

+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \

+                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \

+                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \

+                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \

+                                       ((GROUP) == NVIC_PRIORITYGROUP_4))

+

+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10UL)

+

+#define IS_NVIC_SUB_PRIORITY(PRIORITY)         ((PRIORITY) < 0x10UL)

+

+#define IS_NVIC_DEVICE_IRQ(IRQ)                (((int32_t)IRQ) >= 0x00)

+

+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \

+                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))

+

+#if (__MPU_PRESENT == 1)

+#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \

+                                     ((STATE) == MPU_REGION_DISABLE))

+

+#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \

+                                          ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE))

+

+#define IS_MPU_ACCESS_SHAREABLE(STATE)   (((STATE) == MPU_ACCESS_SHAREABLE) || \

+                                          ((STATE) == MPU_ACCESS_NOT_SHAREABLE))

+

+#define IS_MPU_ACCESS_CACHEABLE(STATE)   (((STATE) == MPU_ACCESS_CACHEABLE) || \

+                                          ((STATE) == MPU_ACCESS_NOT_CACHEABLE))

+

+#define IS_MPU_ACCESS_BUFFERABLE(STATE)   (((STATE) == MPU_ACCESS_BUFFERABLE) || \

+                                          ((STATE) == MPU_ACCESS_NOT_BUFFERABLE))

+

+#define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0)  || \

+                                ((TYPE) == MPU_TEX_LEVEL1)  || \

+                                ((TYPE) == MPU_TEX_LEVEL2))

+

+#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS)   || \

+                                                  ((TYPE) == MPU_REGION_PRIV_RW)     || \

+                                                  ((TYPE) == MPU_REGION_PRIV_RW_URO) || \

+                                                  ((TYPE) == MPU_REGION_FULL_ACCESS) || \

+                                                  ((TYPE) == MPU_REGION_PRIV_RO)     || \

+                                                  ((TYPE) == MPU_REGION_PRIV_RO_URO))

+

+#if !defined(CORE_CM4)

+#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0)  || \

+                                         ((NUMBER) == MPU_REGION_NUMBER1)  || \

+                                         ((NUMBER) == MPU_REGION_NUMBER2)  || \

+                                         ((NUMBER) == MPU_REGION_NUMBER3)  || \

+                                         ((NUMBER) == MPU_REGION_NUMBER4)  || \

+                                         ((NUMBER) == MPU_REGION_NUMBER5)  || \

+                                         ((NUMBER) == MPU_REGION_NUMBER6)  || \

+                                         ((NUMBER) == MPU_REGION_NUMBER7)  || \

+                                         ((NUMBER) == MPU_REGION_NUMBER8)  || \

+                                         ((NUMBER) == MPU_REGION_NUMBER9)  || \

+                                         ((NUMBER) == MPU_REGION_NUMBER10) || \

+                                         ((NUMBER) == MPU_REGION_NUMBER11) || \

+                                         ((NUMBER) == MPU_REGION_NUMBER12) || \

+                                         ((NUMBER) == MPU_REGION_NUMBER13) || \

+                                         ((NUMBER) == MPU_REGION_NUMBER14) || \

+                                         ((NUMBER) == MPU_REGION_NUMBER15))

+#else

+#define IS_MPU_REGION_NUMBER(NUMBER)    (((NUMBER) == MPU_REGION_NUMBER0)  || \

+                                         ((NUMBER) == MPU_REGION_NUMBER1)  || \

+                                         ((NUMBER) == MPU_REGION_NUMBER2)  || \

+                                         ((NUMBER) == MPU_REGION_NUMBER3)  || \

+                                         ((NUMBER) == MPU_REGION_NUMBER4)  || \

+                                         ((NUMBER) == MPU_REGION_NUMBER5)  || \

+                                         ((NUMBER) == MPU_REGION_NUMBER6)  || \

+                                         ((NUMBER) == MPU_REGION_NUMBER7))

+#endif /* !defined(CORE_CM4) */

+

+#define IS_MPU_REGION_SIZE(SIZE)    (((SIZE) == MPU_REGION_SIZE_32B)   || \

+                                     ((SIZE) == MPU_REGION_SIZE_64B)   || \

+                                     ((SIZE) == MPU_REGION_SIZE_128B)  || \

+                                     ((SIZE) == MPU_REGION_SIZE_256B)  || \

+                                     ((SIZE) == MPU_REGION_SIZE_512B)  || \

+                                     ((SIZE) == MPU_REGION_SIZE_1KB)   || \

+                                     ((SIZE) == MPU_REGION_SIZE_2KB)   || \

+                                     ((SIZE) == MPU_REGION_SIZE_4KB)   || \

+                                     ((SIZE) == MPU_REGION_SIZE_8KB)   || \

+                                     ((SIZE) == MPU_REGION_SIZE_16KB)  || \

+                                     ((SIZE) == MPU_REGION_SIZE_32KB)  || \

+                                     ((SIZE) == MPU_REGION_SIZE_64KB)  || \

+                                     ((SIZE) == MPU_REGION_SIZE_128KB) || \

+                                     ((SIZE) == MPU_REGION_SIZE_256KB) || \

+                                     ((SIZE) == MPU_REGION_SIZE_512KB) || \

+                                     ((SIZE) == MPU_REGION_SIZE_1MB)   || \

+                                     ((SIZE) == MPU_REGION_SIZE_2MB)   || \

+                                     ((SIZE) == MPU_REGION_SIZE_4MB)   || \

+                                     ((SIZE) == MPU_REGION_SIZE_8MB)   || \

+                                     ((SIZE) == MPU_REGION_SIZE_16MB)  || \

+                                     ((SIZE) == MPU_REGION_SIZE_32MB)  || \

+                                     ((SIZE) == MPU_REGION_SIZE_64MB)  || \

+                                     ((SIZE) == MPU_REGION_SIZE_128MB) || \

+                                     ((SIZE) == MPU_REGION_SIZE_256MB) || \

+                                     ((SIZE) == MPU_REGION_SIZE_512MB) || \

+                                     ((SIZE) == MPU_REGION_SIZE_1GB)   || \

+                                     ((SIZE) == MPU_REGION_SIZE_2GB)   || \

+                                     ((SIZE) == MPU_REGION_SIZE_4GB))

+

+#define IS_MPU_SUB_REGION_DISABLE(SUBREGION)  ((SUBREGION) < (uint16_t)0x00FF)

+#endif /* __MPU_PRESENT */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_CORTEX_H */

+

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_crc.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_crc.h
new file mode 100644
index 0000000000..224c8af85f
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_crc.h
@@ -0,0 +1,343 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_crc.h

+  * @author  MCD Application Team

+  * @brief   Header file of CRC HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_CRC_H

+#define STM32H7xx_HAL_CRC_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup CRC

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup CRC_Exported_Types CRC Exported Types

+  * @{

+  */

+

+/**

+  * @brief  CRC HAL State Structure definition

+  */

+typedef enum

+{

+  HAL_CRC_STATE_RESET     = 0x00U,  /*!< CRC not yet initialized or disabled */

+  HAL_CRC_STATE_READY     = 0x01U,  /*!< CRC initialized and ready for use   */

+  HAL_CRC_STATE_BUSY      = 0x02U,  /*!< CRC internal process is ongoing     */

+  HAL_CRC_STATE_TIMEOUT   = 0x03U,  /*!< CRC timeout state                   */

+  HAL_CRC_STATE_ERROR     = 0x04U   /*!< CRC error state                     */

+} HAL_CRC_StateTypeDef;

+

+/**

+  * @brief CRC Init Structure definition

+  */

+typedef struct

+{

+  uint8_t DefaultPolynomialUse;       /*!< This parameter is a value of @ref CRC_Default_Polynomial and indicates if default polynomial is used.

+                                            If set to DEFAULT_POLYNOMIAL_ENABLE, resort to default

+                                            X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1.

+                                            In that case, there is no need to set GeneratingPolynomial field.

+                                            If otherwise set to DEFAULT_POLYNOMIAL_DISABLE, GeneratingPolynomial and CRCLength fields must be set. */

+

+  uint8_t DefaultInitValueUse;        /*!< This parameter is a value of @ref CRC_Default_InitValue_Use and indicates if default init value is used.

+                                           If set to DEFAULT_INIT_VALUE_ENABLE, resort to default

+                                           0xFFFFFFFF value. In that case, there is no need to set InitValue field.

+                                           If otherwise set to DEFAULT_INIT_VALUE_DISABLE,  InitValue field must be set. */

+

+  uint32_t GeneratingPolynomial;      /*!< Set CRC generating polynomial as a 7, 8, 16 or 32-bit long value for a polynomial degree

+                                           respectively equal to 7, 8, 16 or 32. This field is written in normal representation,

+                                           e.g., for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65.

+                                           No need to specify it if DefaultPolynomialUse is set to DEFAULT_POLYNOMIAL_ENABLE.   */

+

+  uint32_t CRCLength;                 /*!< This parameter is a value of @ref CRC_Polynomial_Sizes and indicates CRC length.

+                                           Value can be either one of

+                                           @arg @ref CRC_POLYLENGTH_32B                  (32-bit CRC),

+                                           @arg @ref CRC_POLYLENGTH_16B                  (16-bit CRC),

+                                           @arg @ref CRC_POLYLENGTH_8B                   (8-bit CRC),

+                                           @arg @ref CRC_POLYLENGTH_7B                   (7-bit CRC). */

+

+  uint32_t InitValue;                 /*!< Init value to initiate CRC computation. No need to specify it if DefaultInitValueUse

+                                           is set to DEFAULT_INIT_VALUE_ENABLE.   */

+

+  uint32_t InputDataInversionMode;    /*!< This parameter is a value of @ref CRCEx_Input_Data_Inversion and specifies input data inversion mode.

+                                           Can be either one of the following values

+                                           @arg @ref CRC_INPUTDATA_INVERSION_NONE       no input data inversion

+                                           @arg @ref CRC_INPUTDATA_INVERSION_BYTE       byte-wise inversion, 0x1A2B3C4D becomes 0x58D43CB2

+                                           @arg @ref CRC_INPUTDATA_INVERSION_HALFWORD   halfword-wise inversion, 0x1A2B3C4D becomes 0xD458B23C

+                                           @arg @ref CRC_INPUTDATA_INVERSION_WORD       word-wise inversion, 0x1A2B3C4D becomes 0xB23CD458 */

+

+  uint32_t OutputDataInversionMode;   /*!< This parameter is a value of @ref CRCEx_Output_Data_Inversion and specifies output data (i.e. CRC) inversion mode.

+                                            Can be either

+                                            @arg @ref CRC_OUTPUTDATA_INVERSION_DISABLE   no CRC inversion,

+                                            @arg @ref CRC_OUTPUTDATA_INVERSION_ENABLE    CRC 0x11223344 is converted into 0x22CC4488 */

+} CRC_InitTypeDef;

+

+/**

+  * @brief  CRC Handle Structure definition

+  */

+typedef struct

+{

+  CRC_TypeDef                 *Instance;   /*!< Register base address        */

+

+  CRC_InitTypeDef             Init;        /*!< CRC configuration parameters */

+

+  HAL_LockTypeDef             Lock;        /*!< CRC Locking object           */

+

+  __IO HAL_CRC_StateTypeDef   State;       /*!< CRC communication state      */

+

+  uint32_t InputDataFormat;                /*!< This parameter is a value of @ref CRC_Input_Buffer_Format and specifies input data format.

+                                            Can be either

+                                            @arg @ref CRC_INPUTDATA_FORMAT_BYTES       input data is a stream of bytes (8-bit data)

+                                            @arg @ref CRC_INPUTDATA_FORMAT_HALFWORDS   input data is a stream of half-words (16-bit data)

+                                            @arg @ref CRC_INPUTDATA_FORMAT_WORDS       input data is a stream of words (32-bit data)

+

+                                           Note that constant CRC_INPUT_FORMAT_UNDEFINED is defined but an initialization error

+                                           must occur if InputBufferFormat is not one of the three values listed above  */

+} CRC_HandleTypeDef;

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup CRC_Exported_Constants CRC Exported Constants

+  * @{

+  */

+

+/** @defgroup CRC_Default_Polynomial_Value    Default CRC generating polynomial

+  * @{

+  */

+#define DEFAULT_CRC32_POLY      0x04C11DB7U  /*!<  X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2+ X +1 */

+/**

+  * @}

+  */

+

+/** @defgroup CRC_Default_InitValue    Default CRC computation initialization value

+  * @{

+  */

+#define DEFAULT_CRC_INITVALUE   0xFFFFFFFFU  /*!< Initial CRC default value */

+/**

+  * @}

+  */

+

+/** @defgroup CRC_Default_Polynomial    Indicates whether or not default polynomial is used

+  * @{

+  */

+#define DEFAULT_POLYNOMIAL_ENABLE       ((uint8_t)0x00U)  /*!< Enable default generating polynomial 0x04C11DB7  */

+#define DEFAULT_POLYNOMIAL_DISABLE      ((uint8_t)0x01U)  /*!< Disable default generating polynomial 0x04C11DB7 */

+/**

+  * @}

+  */

+

+/** @defgroup CRC_Default_InitValue_Use    Indicates whether or not default init value is used

+  * @{

+  */

+#define DEFAULT_INIT_VALUE_ENABLE      ((uint8_t)0x00U) /*!< Enable initial CRC default value  */

+#define DEFAULT_INIT_VALUE_DISABLE     ((uint8_t)0x01U) /*!< Disable initial CRC default value */

+/**

+  * @}

+  */

+

+/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the peripheral

+  * @{

+  */

+#define CRC_POLYLENGTH_32B                  0x00000000U        /*!< Resort to a 32-bit long generating polynomial */

+#define CRC_POLYLENGTH_16B                  CRC_CR_POLYSIZE_0  /*!< Resort to a 16-bit long generating polynomial */

+#define CRC_POLYLENGTH_8B                   CRC_CR_POLYSIZE_1  /*!< Resort to a 8-bit long generating polynomial  */

+#define CRC_POLYLENGTH_7B                   CRC_CR_POLYSIZE    /*!< Resort to a 7-bit long generating polynomial  */

+/**

+  * @}

+  */

+

+/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions

+  * @{

+  */

+#define HAL_CRC_LENGTH_32B     32U          /*!< 32-bit long CRC */

+#define HAL_CRC_LENGTH_16B     16U          /*!< 16-bit long CRC */

+#define HAL_CRC_LENGTH_8B       8U          /*!< 8-bit long CRC  */

+#define HAL_CRC_LENGTH_7B       7U          /*!< 7-bit long CRC  */

+/**

+  * @}

+  */

+

+/** @defgroup CRC_Input_Buffer_Format Input Buffer Format

+  * @{

+  */

+/* WARNING: CRC_INPUT_FORMAT_UNDEFINED is created for reference purposes but

+ * an error is triggered in HAL_CRC_Init() if InputDataFormat field is set

+ * to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for

+ * the CRC APIs to provide a correct result */

+#define CRC_INPUTDATA_FORMAT_UNDEFINED             0x00000000U  /*!< Undefined input data format    */

+#define CRC_INPUTDATA_FORMAT_BYTES                 0x00000001U  /*!< Input data in byte format      */

+#define CRC_INPUTDATA_FORMAT_HALFWORDS             0x00000002U  /*!< Input data in half-word format */

+#define CRC_INPUTDATA_FORMAT_WORDS                 0x00000003U  /*!< Input data in word format      */

+/**

+  * @}

+  */

+

+/** @defgroup CRC_Aliases CRC API aliases

+  * @{

+  */

+#define HAL_CRC_Input_Data_Reverse   HAL_CRCEx_Input_Data_Reverse    /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility  */

+#define HAL_CRC_Output_Data_Reverse  HAL_CRCEx_Output_Data_Reverse   /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macros -----------------------------------------------------------*/

+/** @defgroup CRC_Exported_Macros CRC Exported Macros

+  * @{

+  */

+

+/** @brief Reset CRC handle state.

+  * @param  __HANDLE__ CRC handle.

+  * @retval None

+  */

+#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)

+

+/**

+  * @brief  Reset CRC Data Register.

+  * @param  __HANDLE__ CRC handle

+  * @retval None

+  */

+#define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)

+

+/**

+  * @brief  Set CRC INIT non-default value

+  * @param  __HANDLE__ CRC handle

+  * @param  __INIT__ 32-bit initial value

+  * @retval None

+  */

+#define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))

+

+/**

+  * @brief Store data in the Independent Data (ID) register.

+  * @param __HANDLE__ CRC handle

+  * @param __VALUE__  Value to be stored in the ID register

+  * @note  Refer to the Reference Manual to get the authorized __VALUE__ length in bits

+  * @retval None

+  */

+#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))

+

+/**

+  * @brief Return the data stored in the Independent Data (ID) register.

+  * @param __HANDLE__ CRC handle

+  * @note  Refer to the Reference Manual to get the authorized __VALUE__ length in bits

+  * @retval Value of the ID register

+  */

+#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)

+/**

+  * @}

+  */

+

+

+/* Private macros --------------------------------------------------------*/

+/** @defgroup  CRC_Private_Macros CRC Private Macros

+  * @{

+  */

+

+#define IS_DEFAULT_POLYNOMIAL(DEFAULT) (((DEFAULT) == DEFAULT_POLYNOMIAL_ENABLE) || \

+                                        ((DEFAULT) == DEFAULT_POLYNOMIAL_DISABLE))

+

+#define IS_DEFAULT_INIT_VALUE(VALUE)  (((VALUE) == DEFAULT_INIT_VALUE_ENABLE) || \

+                                       ((VALUE) == DEFAULT_INIT_VALUE_DISABLE))

+

+#define IS_CRC_POL_LENGTH(LENGTH)     (((LENGTH) == CRC_POLYLENGTH_32B) || \

+                                       ((LENGTH) == CRC_POLYLENGTH_16B) || \

+                                       ((LENGTH) == CRC_POLYLENGTH_8B)  || \

+                                       ((LENGTH) == CRC_POLYLENGTH_7B))

+

+#define IS_CRC_INPUTDATA_FORMAT(FORMAT)           (((FORMAT) == CRC_INPUTDATA_FORMAT_BYTES)     || \

+                                                   ((FORMAT) == CRC_INPUTDATA_FORMAT_HALFWORDS) || \

+                                                   ((FORMAT) == CRC_INPUTDATA_FORMAT_WORDS))

+

+/**

+  * @}

+  */

+

+/* Include CRC HAL Extended module */

+#include "stm32h7xx_hal_crc_ex.h"

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup CRC_Exported_Functions CRC Exported Functions

+  * @{

+  */

+

+/* Initialization and de-initialization functions  ****************************/

+/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions

+  * @{

+  */

+HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc);

+HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc);

+void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);

+void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);

+/**

+  * @}

+  */

+

+/* Peripheral Control functions ***********************************************/

+/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions

+  * @{

+  */

+uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);

+uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);

+/**

+  * @}

+  */

+

+/* Peripheral State and Error functions ***************************************/

+/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions

+  * @{

+  */

+HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_CRC_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_crc_ex.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_crc_ex.h
new file mode 100644
index 0000000000..915dbf24af
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_crc_ex.h
@@ -0,0 +1,153 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_crc_ex.h

+  * @author  MCD Application Team

+  * @brief   Header file of CRC HAL extended module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_CRC_EX_H

+#define STM32H7xx_HAL_CRC_EX_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup CRCEx

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup CRCEx_Exported_Constants CRC Extended Exported Constants

+  * @{

+  */

+

+/** @defgroup CRCEx_Input_Data_Inversion Input Data Inversion Modes

+  * @{

+  */

+#define CRC_INPUTDATA_INVERSION_NONE               0x00000000U     /*!< No input data inversion            */

+#define CRC_INPUTDATA_INVERSION_BYTE               CRC_CR_REV_IN_0 /*!< Byte-wise input data inversion     */

+#define CRC_INPUTDATA_INVERSION_HALFWORD           CRC_CR_REV_IN_1 /*!< HalfWord-wise input data inversion */

+#define CRC_INPUTDATA_INVERSION_WORD               CRC_CR_REV_IN   /*!< Word-wise input data inversion     */

+/**

+  * @}

+  */

+

+/** @defgroup CRCEx_Output_Data_Inversion Output Data Inversion Modes

+  * @{

+  */

+#define CRC_OUTPUTDATA_INVERSION_DISABLE         0x00000000U       /*!< No output data inversion       */

+#define CRC_OUTPUTDATA_INVERSION_ENABLE          CRC_CR_REV_OUT    /*!< Bit-wise output data inversion */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup CRCEx_Exported_Macros CRC Extended Exported Macros

+  * @{

+  */

+

+/**

+  * @brief  Set CRC output reversal

+  * @param  __HANDLE__ CRC handle

+  * @retval None

+  */

+#define  __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)

+

+/**

+  * @brief  Unset CRC output reversal

+  * @param  __HANDLE__ CRC handle

+  * @retval None

+  */

+#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))

+

+/**

+  * @brief  Set CRC non-default polynomial

+  * @param  __HANDLE__ CRC handle

+  * @param  __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial

+  * @retval None

+  */

+#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))

+

+/**

+  * @}

+  */

+

+/* Private macros --------------------------------------------------------*/

+/** @defgroup CRCEx_Private_Macros CRC Extended Private Macros

+  * @{

+  */

+

+#define IS_CRC_INPUTDATA_INVERSION_MODE(MODE)     (((MODE) == CRC_INPUTDATA_INVERSION_NONE)     || \

+                                                   ((MODE) == CRC_INPUTDATA_INVERSION_BYTE)     || \

+                                                   ((MODE) == CRC_INPUTDATA_INVERSION_HALFWORD) || \

+                                                   ((MODE) == CRC_INPUTDATA_INVERSION_WORD))

+

+#define IS_CRC_OUTPUTDATA_INVERSION_MODE(MODE)    (((MODE) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \

+                                                   ((MODE) == CRC_OUTPUTDATA_INVERSION_ENABLE))

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+

+/** @addtogroup CRCEx_Exported_Functions

+  * @{

+  */

+

+/** @addtogroup CRCEx_Exported_Functions_Group1

+  * @{

+  */

+/* Initialization and de-initialization functions  ****************************/

+HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol, uint32_t PolyLength);

+HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t InputReverseMode);

+HAL_StatusTypeDef HAL_CRCEx_Output_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t OutputReverseMode);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_CRC_EX_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_cryp.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_cryp.h
new file mode 100644
index 0000000000..5c4741d8dc
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_cryp.h
@@ -0,0 +1,556 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_cryp.h

+  * @author  MCD Application Team

+  * @brief   Header file of CRYP HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_CRYP_H

+#define STM32H7xx_HAL_CRYP_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+#if defined (CRYP)

+/** @addtogroup CRYP

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup CRYP_Exported_Types CRYP Exported Types

+  * @{

+  */

+

+/**

+  * @brief CRYP Init Structure definition

+  */

+

+typedef struct

+{

+  uint32_t DataType;                   /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.

+                                        This parameter can be a value of @ref CRYP_Data_Type */

+  uint32_t KeySize;                    /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1.

+                                            This parameter can be a value of @ref CRYP_Key_Size */

+  uint32_t *pKey;                      /*!< The key used for encryption/decryption */

+  uint32_t *pInitVect;                 /*!< The initialization vector used also as initialization

+                                         counter in CTR mode */

+  uint32_t Algorithm;                  /*!<  DES/ TDES Algorithm ECB/CBC

+                                        AES Algorithm ECB/CBC/CTR/GCM or CCM

+                                        This parameter can be a value of @ref CRYP_Algorithm_Mode */

+  uint32_t *Header;                    /*!< used only in AES GCM and CCM Algorithm for authentication,

+                                        GCM : also known as Additional Authentication Data

+                                        CCM : named B1 composed of the associated data length and Associated Data. */

+  uint32_t HeaderSize;                /*!< The size of header buffer in word  */

+  uint32_t *B0;                       /*!< B0 is first authentication block used only  in AES CCM mode */

+  uint32_t DataWidthUnit;             /*!< Data With Unit, this parameter can be value of @ref CRYP_Data_Width_Unit*/

+  uint32_t KeyIVConfigSkip;            /*!< CRYP peripheral Key and IV configuration skip, to config Key and Initialization

+                                           Vector only once and to skip configuration for consecutive processings.

+                                           This parameter can be a value of @ref CRYP_Configuration_Skip */

+

+} CRYP_ConfigTypeDef;

+

+

+/**

+  * @brief  CRYP State Structure definition

+  */

+

+typedef enum

+{

+  HAL_CRYP_STATE_RESET             = 0x00U,  /*!< CRYP not yet initialized or disabled  */

+  HAL_CRYP_STATE_READY             = 0x01U,  /*!< CRYP initialized and ready for use    */

+  HAL_CRYP_STATE_BUSY              = 0x02U  /*!< CRYP BUSY, internal processing is ongoing  */

+} HAL_CRYP_STATETypeDef;

+

+

+/**

+  * @brief  CRYP handle Structure definition

+  */

+

+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)

+typedef struct __CRYP_HandleTypeDef

+#else

+typedef struct

+#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */

+{

+

+  CRYP_TypeDef                      *Instance;            /*!< CRYP registers base address */

+

+  CRYP_ConfigTypeDef                Init;             /*!< CRYP required parameters */

+

+  uint32_t                          *pCrypInBuffPtr;  /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */

+

+  uint32_t                          *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */

+

+  __IO uint16_t                     CrypHeaderCount;   /*!< Counter of header data */

+

+  __IO uint16_t                     CrypInCount;      /*!< Counter of input data */

+

+  __IO uint16_t                     CrypOutCount;     /*!< Counter of output data */

+

+  uint16_t                          Size;           /*!< length of input data in word */

+

+  uint32_t                          Phase;            /*!< CRYP peripheral phase */

+

+  DMA_HandleTypeDef                 *hdmain;          /*!< CRYP In DMA handle parameters */

+

+  DMA_HandleTypeDef                 *hdmaout;         /*!< CRYP Out DMA handle parameters */

+

+  HAL_LockTypeDef                   Lock;             /*!< CRYP locking object */

+

+  __IO  HAL_CRYP_STATETypeDef       State;            /*!< CRYP peripheral state */

+

+  __IO uint32_t                     ErrorCode;        /*!< CRYP peripheral error code */

+

+  uint32_t                          Version;          /*!< CRYP1 IP version*/

+

+  uint32_t                          KeyIVConfig;      /*!< CRYP peripheral Key and IV configuration flag, used when

+                                                           configuration can be skipped */

+

+  uint32_t                          SizesSum;         /*!< Sum of successive payloads lengths (in bytes), stored

+                                                           for a single signature computation after several

+                                                           messages processing */

+

+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)

+  void (*InCpltCallback)(struct __CRYP_HandleTypeDef *hcryp);      /*!< CRYP Input FIFO transfer completed callback  */

+  void (*OutCpltCallback)(struct __CRYP_HandleTypeDef *hcryp);     /*!< CRYP Output FIFO transfer completed callback */

+  void (*ErrorCallback)(struct __CRYP_HandleTypeDef *hcryp);       /*!< CRYP Error callback */

+

+  void (* MspInitCallback)(struct __CRYP_HandleTypeDef *hcryp);    /*!< CRYP Msp Init callback  */

+  void (* MspDeInitCallback)(struct __CRYP_HandleTypeDef *hcryp);  /*!< CRYP Msp DeInit callback  */

+

+#endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */

+

+} CRYP_HandleTypeDef;

+

+

+/**

+  * @}

+  */

+

+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)

+/** @defgroup HAL_CRYP_Callback_ID_enumeration_definition HAL CRYP Callback ID enumeration definition

+  * @brief  HAL CRYP Callback ID enumeration definition

+  * @{

+  */

+typedef enum

+{

+  HAL_CRYP_INPUT_COMPLETE_CB_ID    = 0x01U,    /*!< CRYP Input FIFO transfer completed callback ID */

+  HAL_CRYP_OUTPUT_COMPLETE_CB_ID   = 0x02U,    /*!< CRYP Output FIFO transfer completed callback ID */

+  HAL_CRYP_ERROR_CB_ID             = 0x03U,    /*!< CRYP Error callback ID           */

+

+  HAL_CRYP_MSPINIT_CB_ID        = 0x04U,    /*!< CRYP MspInit callback ID         */

+  HAL_CRYP_MSPDEINIT_CB_ID      = 0x05U     /*!< CRYP MspDeInit callback ID       */

+

+} HAL_CRYP_CallbackIDTypeDef;

+/**

+  * @}

+  */

+

+/** @defgroup HAL_CRYP_Callback_pointer_definition HAL CRYP Callback pointer definition

+  * @brief  HAL CRYP Callback pointer definition

+  * @{

+  */

+

+typedef  void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp);    /*!< pointer to a common CRYP callback function */

+

+/**

+  * @}

+  */

+

+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup CRYP_Exported_Constants CRYP Exported Constants

+  * @{

+  */

+

+/** @defgroup CRYP_Error_Definition   CRYP Error Definition

+  * @{

+  */

+#define HAL_CRYP_ERROR_NONE              0x00000000U  /*!< No error        */

+#define HAL_CRYP_ERROR_WRITE             0x00000001U  /*!< Write error     */

+#define HAL_CRYP_ERROR_READ              0x00000002U  /*!< Read error      */

+#define HAL_CRYP_ERROR_DMA               0x00000004U  /*!< DMA error       */

+#define HAL_CRYP_ERROR_BUSY              0x00000008U  /*!< Busy flag error */

+#define HAL_CRYP_ERROR_TIMEOUT           0x00000010U  /*!< Timeout error */

+#define HAL_CRYP_ERROR_NOT_SUPPORTED     0x00000020U  /*!< Not supported mode */

+#define HAL_CRYP_ERROR_AUTH_TAG_SEQUENCE 0x00000040U  /*!< Sequence are not respected only for GCM or CCM */

+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)

+#define  HAL_CRYP_ERROR_INVALID_CALLBACK ((uint32_t)0x00000080U)    /*!< Invalid Callback error  */

+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+

+/** @defgroup CRYP_Data_Width_Unit CRYP Data Width Unit

+  * @{

+  */

+

+#define CRYP_DATAWIDTHUNIT_WORD   0x00000000U  /*!< By default, size unit is word */

+#define CRYP_DATAWIDTHUNIT_BYTE   0x00000001U  /*!< By default, size unit is word */

+

+/**

+  * @}

+  */

+

+/** @defgroup CRYP_Algorithm_Mode CRYP Algorithm Mode

+  * @{

+  */

+

+#define CRYP_DES_ECB     CRYP_CR_ALGOMODE_DES_ECB

+#define CRYP_DES_CBC     CRYP_CR_ALGOMODE_DES_CBC

+#define CRYP_TDES_ECB    CRYP_CR_ALGOMODE_TDES_ECB

+#define CRYP_TDES_CBC    CRYP_CR_ALGOMODE_TDES_CBC

+#define CRYP_AES_ECB     CRYP_CR_ALGOMODE_AES_ECB

+#define CRYP_AES_CBC     CRYP_CR_ALGOMODE_AES_CBC

+#define CRYP_AES_CTR     CRYP_CR_ALGOMODE_AES_CTR

+#define CRYP_AES_GCM     CRYP_CR_ALGOMODE_AES_GCM

+#define CRYP_AES_CCM     CRYP_CR_ALGOMODE_AES_CCM

+

+/**

+  * @}

+  */

+

+/** @defgroup CRYP_Key_Size CRYP Key Size

+  * @{

+  */

+

+#define CRYP_KEYSIZE_128B         0x00000000U

+#define CRYP_KEYSIZE_192B         CRYP_CR_KEYSIZE_0

+#define CRYP_KEYSIZE_256B         CRYP_CR_KEYSIZE_1

+

+/**

+  * @}

+  */

+

+/** @defgroup CRYP_Data_Type CRYP Data Type

+  * @{

+  */

+

+#define CRYP_DATATYPE_32B         0x00000000U

+#define CRYP_DATATYPE_16B         CRYP_CR_DATATYPE_0

+#define CRYP_DATATYPE_8B          CRYP_CR_DATATYPE_1

+#define CRYP_DATATYPE_1B          CRYP_CR_DATATYPE

+

+/**

+  * @}

+  */

+

+/** @defgroup CRYP_Interrupt  CRYP Interrupt

+  * @{

+  */

+

+#define CRYP_IT_INI       CRYP_IMSCR_INIM   /*!< Input FIFO Interrupt */

+#define CRYP_IT_OUTI      CRYP_IMSCR_OUTIM  /*!< Output FIFO Interrupt */

+

+/**

+  * @}

+  */

+

+/** @defgroup CRYP_Flags CRYP Flags

+  * @{

+  */

+

+/* Flags in the SR register */

+#define CRYP_FLAG_IFEM    CRYP_SR_IFEM  /*!< Input FIFO is empty */

+#define CRYP_FLAG_IFNF    CRYP_SR_IFNF  /*!< Input FIFO is not Full */

+#define CRYP_FLAG_OFNE    CRYP_SR_OFNE  /*!< Output FIFO is not empty */

+#define CRYP_FLAG_OFFU    CRYP_SR_OFFU  /*!< Output FIFO is Full */

+#define CRYP_FLAG_BUSY    CRYP_SR_BUSY  /*!< The CRYP core is currently processing a block of data

+                                             or a key preparation (for AES decryption). */

+/* Flags in the RISR register */

+#define CRYP_FLAG_OUTRIS  0x01000002U  /*!< Output FIFO service raw interrupt status */

+#define CRYP_FLAG_INRIS   0x01000001U  /*!< Input FIFO service raw interrupt status*/

+

+/**

+  * @}

+  */

+

+/** @defgroup CRYP_Configuration_Skip CRYP Key and IV Configuration Skip Mode

+  * @{

+  */

+

+#define CRYP_KEYIVCONFIG_ALWAYS        0x00000000U            /*!< Peripheral Key and IV configuration to do systematically */

+#define CRYP_KEYIVCONFIG_ONCE          0x00000001U            /*!< Peripheral Key and IV configuration to do only once      */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macros -----------------------------------------------------------*/

+/** @defgroup CRYP_Exported_Macros CRYP Exported Macros

+  * @{

+  */

+

+/** @brief Reset CRYP handle state

+  * @param  __HANDLE__ specifies the CRYP handle.

+  * @retval None

+  */

+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)

+#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) do{\

+                                                      (__HANDLE__)->State = HAL_CRYP_STATE_RESET;\

+                                                      (__HANDLE__)->MspInitCallback = NULL;\

+                                                      (__HANDLE__)->MspDeInitCallback = NULL;\

+                                                     }while(0)

+#else

+#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_CRYP_STATE_RESET)

+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */

+

+/**

+  * @brief  Enable/Disable the CRYP peripheral.

+  * @param  __HANDLE__: specifies the CRYP handle.

+  * @retval None

+  */

+

+#define __HAL_CRYP_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  CRYP_CR_CRYPEN)

+#define __HAL_CRYP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &=  ~CRYP_CR_CRYPEN)

+

+/** @brief  Check whether the specified CRYP status flag is set or not.

+  * @param  __FLAG__: specifies the flag to check.

+  *         This parameter can be one of the following values for CRYP:

+  *            @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data

+  *                                 or a key preparation (for AES decryption).

+  *            @arg CRYP_FLAG_IFEM: Input FIFO is empty

+  *            @arg CRYP_FLAG_IFNF: Input FIFO is not full

+  *            @arg CRYP_FLAG_INRIS: Input FIFO service raw interrupt is pending

+  *            @arg CRYP_FLAG_OFNE: Output FIFO is not empty

+  *            @arg CRYP_FLAG_OFFU: Output FIFO is full

+  *            @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending

+  * @retval The state of __FLAG__ (TRUE or FALSE).

+  */

+#define CRYP_FLAG_MASK  0x0000001FU

+

+#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \

+                                                   ((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))

+

+/** @brief  Check whether the specified CRYP interrupt is set or not.

+  * @param  __HANDLE__: specifies the CRYP handle.

+  * @param  __INTERRUPT__: specifies the interrupt to check.

+  *         This parameter can be one of the following values for CRYP:

+  *            @arg CRYP_IT_INI: Input FIFO service masked interrupt status

+  *            @arg CRYP_IT_OUTI: Output FIFO service masked interrupt status

+  * @retval The state of __INTERRUPT__ (TRUE or FALSE).

+  */

+

+#define __HAL_CRYP_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MISR & (__INTERRUPT__)) == (__INTERRUPT__))

+

+/**

+  * @brief  Enable the CRYP interrupt.

+  * @param  __HANDLE__: specifies the CRYP handle.

+  * @param  __INTERRUPT__: CRYP Interrupt.

+  *         This parameter can be one of the following values for CRYP:

+  *            @ CRYP_IT_INI : Input FIFO service interrupt mask.

+  *            @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.

+  * @retval None

+  */

+

+#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))

+

+/**

+  * @brief  Disable the CRYP interrupt.

+  * @param  __HANDLE__: specifies the CRYP handle.

+  * @param  __INTERRUPT__: CRYP Interrupt.

+  *         This parameter can be one of the following values for CRYP:

+  *            @ CRYP_IT_INI : Input FIFO service interrupt mask.

+  *            @ CRYP_IT_OUTI : Output FIFO service interrupt mask.CRYP interrupt.

+  * @retval None

+  */

+

+#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))

+

+/**

+  * @}

+  */

+

+/* Include CRYP HAL Extended module */

+#include "stm32h7xx_hal_cryp_ex.h"

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup CRYP_Exported_Functions CRYP Exported Functions

+  * @{

+  */

+

+/** @addtogroup CRYP_Exported_Functions_Group1

+  * @{

+  */

+HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);

+HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);

+void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);

+void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);

+HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);

+HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf);

+#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)

+HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,

+                                            pCRYP_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID);

+#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/** @addtogroup CRYP_Exported_Functions_Group2

+  * @{

+  */

+

+/* encryption/decryption ***********************************/

+HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,

+                                   uint32_t Timeout);

+HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,

+                                   uint32_t Timeout);

+HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);

+HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);

+HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);

+HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output);

+

+/**

+  * @}

+  */

+

+

+/** @addtogroup CRYP_Exported_Functions_Group3

+  * @{

+  */

+/* Interrupt Handler functions  **********************************************/

+void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);

+HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);

+void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);

+void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);

+void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);

+uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private macros --------------------------------------------------------*/

+/** @defgroup CRYP_Private_Macros   CRYP Private Macros

+  * @{

+  */

+

+/** @defgroup CRYP_IS_CRYP_Definitions CRYP Private macros to check input parameters

+  * @{

+  */

+

+#define IS_CRYP_ALGORITHM(ALGORITHM) (((ALGORITHM) == CRYP_DES_ECB)   || \

+                                      ((ALGORITHM)  == CRYP_DES_CBC)   || \

+                                      ((ALGORITHM)  == CRYP_TDES_ECB)  || \

+                                      ((ALGORITHM)  == CRYP_TDES_CBC)  || \

+                                      ((ALGORITHM)  == CRYP_AES_ECB)   || \

+                                      ((ALGORITHM)  == CRYP_AES_CBC)   || \

+                                      ((ALGORITHM)  == CRYP_AES_CTR)   || \

+                                      ((ALGORITHM)  == CRYP_AES_GCM)   || \

+                                      ((ALGORITHM)  == CRYP_AES_CCM))

+

+#define IS_CRYP_KEYSIZE(KEYSIZE)(((KEYSIZE) == CRYP_KEYSIZE_128B)   || \

+                                 ((KEYSIZE) == CRYP_KEYSIZE_192B)   || \

+                                 ((KEYSIZE) == CRYP_KEYSIZE_256B))

+

+#define IS_CRYP_DATATYPE(DATATYPE)(((DATATYPE) == CRYP_DATATYPE_32B)   || \

+                                   ((DATATYPE) == CRYP_DATATYPE_16B) || \

+                                   ((DATATYPE) == CRYP_DATATYPE_8B) || \

+                                   ((DATATYPE) == CRYP_DATATYPE_1B))

+

+#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \

+                             ((CONFIG) == CRYP_KEYIVCONFIG_ONCE))

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup CRYP_Private_Constants CRYP Private Constants

+  * @{

+  */

+

+/**

+  * @}

+  */

+/* Private defines -----------------------------------------------------------*/

+/** @defgroup CRYP_Private_Defines CRYP Private Defines

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private variables ---------------------------------------------------------*/

+/** @defgroup CRYP_Private_Variables CRYP Private Variables

+  * @{

+  */

+

+/**

+  * @}

+  */

+/* Private functions prototypes ----------------------------------------------*/

+/** @defgroup CRYP_Private_Functions_Prototypes CRYP Private Functions Prototypes

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private functions ---------------------------------------------------------*/

+/** @defgroup CRYP_Private_Functions CRYP Private Functions

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+

+/**

+  * @}

+  */

+

+

+#endif /* CRYP */

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_CRYP_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_cryp_ex.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_cryp_ex.h
new file mode 100644
index 0000000000..66b510e917
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_cryp_ex.h
@@ -0,0 +1,123 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_cryp_ex.h

+  * @author  MCD Application Team

+  * @brief   Header file of CRYP HAL Extension module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_CRYP_EX_H

+#define STM32H7xx_HAL_CRYP_EX_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+#if defined (CRYP)

+/** @addtogroup CRYPEx

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/* Exported constants --------------------------------------------------------*/

+

+/* Private types -------------------------------------------------------------*/

+/** @defgroup CRYPEx_Private_Types CRYPEx Private Types

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private variables ---------------------------------------------------------*/

+/** @defgroup CRYPEx_Private_Variables CRYPEx Private Variables

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup CRYPEx_Private_Constants CRYPEx Private Constants

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup CRYPEx_Private_Macros CRYPEx Private Macros

+  * @{

+  */

+

+/**

+  * @}

+ */

+

+/* Private functions ---------------------------------------------------------*/

+/** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions

+  * @{

+  */

+

+/** @addtogroup CRYPEx_Exported_Functions_Group1

+  * @{

+  */

+HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);

+HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout);

+

+

+/**

+  * @}

+  */

+

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+#endif /* CRYP */

+/**

+  * @}

+  */

+

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_CRYP_EX_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_dac.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_dac.h
new file mode 100644
index 0000000000..b6debe3361
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_dac.h
@@ -0,0 +1,546 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_dac.h

+  * @author  MCD Application Team

+  * @brief   Header file of DAC HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_DAC_H

+#define STM32H7xx_HAL_DAC_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+#if defined(DAC1) || defined(DAC2)

+

+/** @addtogroup DAC

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+

+/** @defgroup DAC_Exported_Types DAC Exported Types

+  * @{

+  */

+

+/**

+  * @brief  HAL State structures definition

+  */

+typedef enum

+{

+  HAL_DAC_STATE_RESET             = 0x00U,  /*!< DAC not yet initialized or disabled  */

+  HAL_DAC_STATE_READY             = 0x01U,  /*!< DAC initialized and ready for use    */

+  HAL_DAC_STATE_BUSY              = 0x02U,  /*!< DAC internal processing is ongoing   */

+  HAL_DAC_STATE_TIMEOUT           = 0x03U,  /*!< DAC timeout state                    */

+  HAL_DAC_STATE_ERROR             = 0x04U   /*!< DAC error state                      */

+

+} HAL_DAC_StateTypeDef;

+

+/**

+  * @brief  DAC handle Structure definition

+  */

+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)

+typedef struct __DAC_HandleTypeDef

+#else

+typedef struct

+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */

+{

+  DAC_TypeDef                 *Instance;     /*!< Register base address             */

+

+  __IO HAL_DAC_StateTypeDef   State;         /*!< DAC communication state           */

+

+  HAL_LockTypeDef             Lock;          /*!< DAC locking object                */

+

+  DMA_HandleTypeDef           *DMA_Handle1;  /*!< Pointer DMA handler for channel 1 */

+

+  DMA_HandleTypeDef           *DMA_Handle2;  /*!< Pointer DMA handler for channel 2 */

+

+  __IO uint32_t               ErrorCode;     /*!< DAC Error code                    */

+

+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)

+  void (* ConvCpltCallbackCh1)            (struct __DAC_HandleTypeDef *hdac);

+  void (* ConvHalfCpltCallbackCh1)        (struct __DAC_HandleTypeDef *hdac);

+  void (* ErrorCallbackCh1)               (struct __DAC_HandleTypeDef *hdac);

+  void (* DMAUnderrunCallbackCh1)         (struct __DAC_HandleTypeDef *hdac);

+  void (* ConvCpltCallbackCh2)            (struct __DAC_HandleTypeDef *hdac);

+  void (* ConvHalfCpltCallbackCh2)        (struct __DAC_HandleTypeDef *hdac);

+  void (* ErrorCallbackCh2)               (struct __DAC_HandleTypeDef *hdac);

+  void (* DMAUnderrunCallbackCh2)         (struct __DAC_HandleTypeDef *hdac);

+

+  void (* MspInitCallback)                (struct __DAC_HandleTypeDef *hdac);

+  void (* MspDeInitCallback )             (struct __DAC_HandleTypeDef *hdac);

+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */

+

+} DAC_HandleTypeDef;

+

+/**

+  * @brief   DAC Configuration sample and hold Channel structure definition

+  */

+typedef struct

+{

+  uint32_t DAC_SampleTime ;          /*!< Specifies the Sample time for the selected channel.

+                                          This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.

+                                          This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */

+

+  uint32_t DAC_HoldTime ;            /*!< Specifies the hold time for the selected channel

+                                          This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.

+                                          This parameter must be a number between Min_Data = 0 and Max_Data = 1023 */

+

+  uint32_t DAC_RefreshTime ;         /*!< Specifies the refresh time for the selected channel

+                                          This parameter applies when DAC_SampleAndHold is DAC_SAMPLEANDHOLD_ENABLE.

+                                          This parameter must be a number between Min_Data = 0 and Max_Data = 255 */

+} DAC_SampleAndHoldConfTypeDef;

+

+/**

+  * @brief   DAC Configuration regular Channel structure definition

+  */

+typedef struct

+{

+  uint32_t DAC_SampleAndHold;            /*!< Specifies whether the DAC mode.

+                                              This parameter can be a value of @ref DAC_SampleAndHold */

+

+  uint32_t DAC_Trigger;                  /*!< Specifies the external trigger for the selected DAC channel.

+                                              This parameter can be a value of @ref DAC_trigger_selection */

+

+  uint32_t DAC_OutputBuffer;             /*!< Specifies whether the DAC channel output buffer is enabled or disabled.

+                                               This parameter can be a value of @ref DAC_output_buffer */

+

+  uint32_t DAC_ConnectOnChipPeripheral ; /*!< Specifies whether the DAC output is connected or not to on chip peripheral .

+                                              This parameter can be a value of @ref DAC_ConnectOnChipPeripheral */

+

+  uint32_t DAC_UserTrimming;             /*!< Specifies the trimming mode

+                                              This parameter must be a value of @ref DAC_UserTrimming

+                                              DAC_UserTrimming is either factory or user trimming */

+

+  uint32_t DAC_TrimmingValue;             /*!< Specifies the offset trimming value

+                                               i.e. when DAC_SampleAndHold is DAC_TRIMMING_USER.

+                                               This parameter must be a number between Min_Data = 1 and Max_Data = 31 */

+

+  DAC_SampleAndHoldConfTypeDef  DAC_SampleAndHoldConfig;  /*!< Sample and Hold settings */

+

+} DAC_ChannelConfTypeDef;

+

+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  HAL DAC Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_DAC_CH1_COMPLETE_CB_ID                 = 0x00U,  /*!< DAC CH1 Complete Callback ID      */

+  HAL_DAC_CH1_HALF_COMPLETE_CB_ID            = 0x01U,  /*!< DAC CH1 half Complete Callback ID */

+  HAL_DAC_CH1_ERROR_ID                       = 0x02U,  /*!< DAC CH1 error Callback ID         */

+  HAL_DAC_CH1_UNDERRUN_CB_ID                 = 0x03U,  /*!< DAC CH1 underrun Callback ID      */

+  HAL_DAC_CH2_COMPLETE_CB_ID                 = 0x04U,  /*!< DAC CH2 Complete Callback ID      */

+  HAL_DAC_CH2_HALF_COMPLETE_CB_ID            = 0x05U,  /*!< DAC CH2 half Complete Callback ID */

+  HAL_DAC_CH2_ERROR_ID                       = 0x06U,  /*!< DAC CH2 error Callback ID         */

+  HAL_DAC_CH2_UNDERRUN_CB_ID                 = 0x07U,  /*!< DAC CH2 underrun Callback ID      */

+  HAL_DAC_MSPINIT_CB_ID                      = 0x08U,  /*!< DAC MspInit Callback ID           */

+  HAL_DAC_MSPDEINIT_CB_ID                    = 0x09U,  /*!< DAC MspDeInit Callback ID         */

+  HAL_DAC_ALL_CB_ID                          = 0x0AU   /*!< DAC All ID                        */

+} HAL_DAC_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL DAC Callback pointer definition

+  */

+typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac);

+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+

+/** @defgroup DAC_Exported_Constants DAC Exported Constants

+  * @{

+  */

+

+/** @defgroup DAC_Error_Code DAC Error Code

+  * @{

+  */

+#define  HAL_DAC_ERROR_NONE              0x00U    /*!< No error                          */

+#define  HAL_DAC_ERROR_DMAUNDERRUNCH1    0x01U    /*!< DAC channel1 DMA underrun error   */

+#define  HAL_DAC_ERROR_DMAUNDERRUNCH2    0x02U    /*!< DAC channel2 DMA underrun error   */

+#define  HAL_DAC_ERROR_DMA               0x04U    /*!< DMA error                         */

+#define  HAL_DAC_ERROR_TIMEOUT           0x08U    /*!< Timeout error                     */

+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)

+#define HAL_DAC_ERROR_INVALID_CALLBACK   0x10U    /*!< Invalid callback error            */

+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+/** @defgroup DAC_trigger_selection DAC trigger selection

+  * @{

+  */

+#define DAC_TRIGGER_NONE                0x00000000U                                                                       /*!< Conversion is automatic once the DAC_DHRxxxx register has been loaded, and not by external trigger */

+#define DAC_TRIGGER_SOFTWARE            (                                                                    DAC_CR_TEN1) /*!< Conversion started by software trigger for DAC channel */

+#define DAC_TRIGGER_T1_TRGO             (                                                   DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM1 TRGO selected as external conversion trigger for DAC channel */

+#define DAC_TRIGGER_T2_TRGO             (                                  DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */

+#define DAC_TRIGGER_T4_TRGO             (                                  DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */

+#define DAC_TRIGGER_T5_TRGO             (                 DAC_CR_TSEL1_2                                   | DAC_CR_TEN1) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */

+#define DAC_TRIGGER_T6_TRGO             (                 DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */

+#define DAC_TRIGGER_T7_TRGO             (                 DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */

+#define DAC_TRIGGER_T8_TRGO             (                 DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */

+#define DAC_TRIGGER_T15_TRGO            (DAC_CR_TSEL1_3                                                    | DAC_CR_TEN1) /*!< TIM15 TRGO selected as external conversion trigger for DAC channel */

+#if defined(HRTIM1)

+#define DAC_TRIGGER_HR1_TRGO1           (DAC_CR_TSEL1_3                                   | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< HR1 TRGO1 selected as external conversion trigger for DAC channel */

+#define DAC_TRIGGER_HR1_TRGO2           (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< HR1 TRGO2 selected as external conversion trigger for DAC channel */

+#endif

+#define DAC_TRIGGER_LPTIM1_OUT          (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< LPTIM1 OUT TRGO selected as external conversion trigger for DAC channel */

+#define DAC_TRIGGER_LPTIM2_OUT          (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                                   | DAC_CR_TEN1) /*!< LPTIM2 OUT TRGO selected as external conversion trigger for DAC channel */

+#define DAC_TRIGGER_EXT_IT9             (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */

+#if defined(TIM23)

+#define DAC_TRIGGER_T23_TRGO            (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< TIM23 TRGO selected as external conversion trigger for DAC channel */

+#endif

+#if defined(TIM24)

+#define DAC_TRIGGER_T24_TRGO            (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1) /*!< TIM24 TRGO selected as external conversion trigger for DAC channel */

+#endif

+#if defined(DAC2)

+#define DAC_TRIGGER_LPTIM3_OUT          (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                  | DAC_CR_TEN1) /*!< LPTIM3 OUT TRGO selected as external conversion trigger for DAC channel */

+#endif

+

+/**

+  * @}

+  */

+

+/** @defgroup DAC_output_buffer DAC output buffer

+  * @{

+  */

+#define DAC_OUTPUTBUFFER_ENABLE            0x00000000U

+#define DAC_OUTPUTBUFFER_DISABLE           (DAC_MCR_MODE1_1)

+

+/**

+  * @}

+  */

+

+/** @defgroup DAC_Channel_selection DAC Channel selection

+  * @{

+  */

+#define DAC_CHANNEL_1                      0x00000000U

+#define DAC_CHANNEL_2                      0x00000010U

+/**

+  * @}

+  */

+

+/** @defgroup DAC_data_alignment DAC data alignment

+  * @{

+  */

+#define DAC_ALIGN_12B_R                    0x00000000U

+#define DAC_ALIGN_12B_L                    0x00000004U

+#define DAC_ALIGN_8B_R                     0x00000008U

+

+/**

+  * @}

+  */

+

+/** @defgroup DAC_flags_definition DAC flags definition

+  * @{

+  */

+#define DAC_FLAG_DMAUDR1                   (DAC_SR_DMAUDR1)

+#define DAC_FLAG_DMAUDR2                   (DAC_SR_DMAUDR2)

+

+/**

+  * @}

+  */

+

+/** @defgroup DAC_IT_definition  DAC IT definition

+  * @{

+  */

+#define DAC_IT_DMAUDR1                   (DAC_SR_DMAUDR1)

+#define DAC_IT_DMAUDR2                   (DAC_SR_DMAUDR2)

+

+/**

+  * @}

+  */

+

+/** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral

+  * @{

+  */

+#define DAC_CHIPCONNECT_EXTERNAL       (1UL << 0)

+#define DAC_CHIPCONNECT_INTERNAL       (1UL << 1)

+#define DAC_CHIPCONNECT_BOTH           (1UL << 2)

+

+/**

+  * @}

+  */

+

+/** @defgroup DAC_UserTrimming DAC User Trimming

+  * @{

+  */

+#define DAC_TRIMMING_FACTORY        (0x00000000UL)        /*!< Factory trimming */

+#define DAC_TRIMMING_USER           (0x00000001UL)        /*!< User trimming */

+/**

+  * @}

+  */

+

+/** @defgroup DAC_SampleAndHold DAC power mode

+  * @{

+  */

+#define DAC_SAMPLEANDHOLD_DISABLE     (0x00000000UL)

+#define DAC_SAMPLEANDHOLD_ENABLE      (DAC_MCR_MODE1_2)

+

+/**

+  * @}

+  */

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+

+/** @defgroup DAC_Exported_Macros DAC Exported Macros

+  * @{

+  */

+

+/** @brief Reset DAC handle state.

+  * @param  __HANDLE__ specifies the DAC handle.

+  * @retval None

+  */

+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)

+#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) do {                                                        \

+                                                      (__HANDLE__)->State             = HAL_DAC_STATE_RESET; \

+                                                      (__HANDLE__)->MspInitCallback   = NULL;                \

+                                                      (__HANDLE__)->MspDeInitCallback = NULL;                \

+                                                     } while(0)

+#else

+#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)

+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */

+

+/** @brief Enable the DAC channel.

+  * @param  __HANDLE__ specifies the DAC handle.

+  * @param  __DAC_Channel__ specifies the DAC channel

+  * @retval None

+  */

+#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \

+  ((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))

+

+/** @brief Disable the DAC channel.

+  * @param  __HANDLE__ specifies the DAC handle

+  * @param  __DAC_Channel__ specifies the DAC channel.

+  * @retval None

+  */

+#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \

+  ((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << ((__DAC_Channel__) & 0x10UL)))

+

+/** @brief Set DHR12R1 alignment.

+  * @param  __ALIGNMENT__ specifies the DAC alignment

+  * @retval None

+  */

+#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008UL + (__ALIGNMENT__))

+

+/** @brief  Set DHR12R2 alignment.

+  * @param  __ALIGNMENT__ specifies the DAC alignment

+  * @retval None

+  */

+#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (0x00000014UL + (__ALIGNMENT__))

+

+/** @brief  Set DHR12RD alignment.

+  * @param  __ALIGNMENT__ specifies the DAC alignment

+  * @retval None

+  */

+#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020UL + (__ALIGNMENT__))

+

+/** @brief Enable the DAC interrupt.

+  * @param  __HANDLE__ specifies the DAC handle

+  * @param  __INTERRUPT__ specifies the DAC interrupt.

+  *          This parameter can be any combination of the following values:

+  *            @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt

+  *            @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt

+  * @retval None

+  */

+#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))

+

+/** @brief Disable the DAC interrupt.

+  * @param  __HANDLE__ specifies the DAC handle

+  * @param  __INTERRUPT__ specifies the DAC interrupt.

+  *          This parameter can be any combination of the following values:

+  *            @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt

+  *            @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt

+  * @retval None

+  */

+#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))

+

+/** @brief  Check whether the specified DAC interrupt source is enabled or not.

+  * @param __HANDLE__ DAC handle

+  * @param __INTERRUPT__ DAC interrupt source to check

+  *          This parameter can be any combination of the following values:

+  *            @arg DAC_IT_DMAUDR1 DAC channel 1 DMA underrun interrupt

+  *            @arg DAC_IT_DMAUDR2 DAC channel 2 DMA underrun interrupt

+  * @retval State of interruption (SET or RESET)

+  */

+#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))

+

+/** @brief  Get the selected DAC's flag status.

+  * @param  __HANDLE__ specifies the DAC handle.

+  * @param  __FLAG__ specifies the DAC flag to get.

+  *          This parameter can be any combination of the following values:

+  *            @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag

+  *            @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag

+  * @retval None

+  */

+#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

+

+/** @brief  Clear the DAC's flag.

+  * @param  __HANDLE__ specifies the DAC handle.

+  * @param  __FLAG__ specifies the DAC flag to clear.

+  *          This parameter can be any combination of the following values:

+  *            @arg DAC_FLAG_DMAUDR1 DAC channel 1 DMA underrun flag

+  *            @arg DAC_FLAG_DMAUDR2 DAC channel 2 DMA underrun flag

+  * @retval None

+  */

+#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))

+

+/**

+  * @}

+  */

+

+/* Private macro -------------------------------------------------------------*/

+

+/** @defgroup DAC_Private_Macros DAC Private Macros

+  * @{

+  */

+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \

+                                           ((STATE) == DAC_OUTPUTBUFFER_DISABLE))

+

+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \

+                                 ((CHANNEL) == DAC_CHANNEL_2))

+

+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \

+                             ((ALIGN) == DAC_ALIGN_12B_L) || \

+                             ((ALIGN) == DAC_ALIGN_8B_R))

+

+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0UL)

+

+#define IS_DAC_REFRESHTIME(TIME)   ((TIME) <= 0x000000FFUL)

+

+/**

+  * @}

+  */

+

+/* Include DAC HAL Extended module */

+#include "stm32h7xx_hal_dac_ex.h"

+

+/* Exported functions --------------------------------------------------------*/

+

+/** @addtogroup DAC_Exported_Functions

+  * @{

+  */

+

+/** @addtogroup DAC_Exported_Functions_Group1

+  * @{

+  */

+/* Initialization and de-initialization functions *****************************/

+HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef *hdac);

+HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef *hdac);

+void HAL_DAC_MspInit(DAC_HandleTypeDef *hdac);

+void HAL_DAC_MspDeInit(DAC_HandleTypeDef *hdac);

+

+/**

+  * @}

+  */

+

+/** @addtogroup DAC_Exported_Functions_Group2

+  * @{

+  */

+/* IO operation functions *****************************************************/

+HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef *hdac, uint32_t Channel);

+HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef *hdac, uint32_t Channel);

+HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,

+                                    uint32_t Alignment);

+HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);

+void HAL_DAC_IRQHandler(DAC_HandleTypeDef *hdac);

+HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);

+

+void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef *hdac);

+void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef *hdac);

+void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);

+void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);

+

+#if (USE_HAL_DAC_REGISTER_CALLBACKS == 1)

+/* DAC callback registering/unregistering */

+HAL_StatusTypeDef     HAL_DAC_RegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID,

+                                               pDAC_CallbackTypeDef pCallback);

+HAL_StatusTypeDef     HAL_DAC_UnRegisterCallback(DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID);

+#endif /* USE_HAL_DAC_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+/** @addtogroup DAC_Exported_Functions_Group3

+  * @{

+  */

+/* Peripheral Control functions ***********************************************/

+uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef *hdac, uint32_t Channel);

+HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);

+/**

+  * @}

+  */

+

+/** @addtogroup DAC_Exported_Functions_Group4

+  * @{

+  */

+/* Peripheral State and Error functions ***************************************/

+HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef *hdac);

+uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/** @defgroup DAC_Private_Functions DAC Private Functions

+  * @{

+  */

+void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);

+void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);

+void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* DAC1 || DAC2 */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+

+#endif /*STM32H7xx_HAL_DAC_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_dac_ex.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_dac_ex.h
new file mode 100644
index 0000000000..f98c28ed3b
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_dac_ex.h
@@ -0,0 +1,273 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_dac_ex.h

+  * @author  MCD Application Team

+  * @brief   Header file of DAC HAL Extended module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_DAC_EX_H

+#define STM32H7xx_HAL_DAC_EX_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+#if defined(DAC1) || defined(DAC2)

+

+/** @addtogroup DACEx

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+

+/**

+  * @brief  HAL State structures definition

+  */

+

+/* Exported constants --------------------------------------------------------*/

+

+/** @defgroup DACEx_Exported_Constants DACEx Exported Constants

+  * @{

+  */

+

+/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangle amplitude

+  * @{

+  */

+#define DAC_LFSRUNMASK_BIT0                0x00000000UL                                                        /*!< Unmask DAC channel LFSR bit0 for noise wave generation */

+#define DAC_LFSRUNMASK_BITS1_0             (                                                   DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */

+#define DAC_LFSRUNMASK_BITS2_0             (                                  DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */

+#define DAC_LFSRUNMASK_BITS3_0             (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */

+#define DAC_LFSRUNMASK_BITS4_0             (                 DAC_CR_MAMP1_2                                  ) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */

+#define DAC_LFSRUNMASK_BITS5_0             (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */

+#define DAC_LFSRUNMASK_BITS6_0             (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */

+#define DAC_LFSRUNMASK_BITS7_0             (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */

+#define DAC_LFSRUNMASK_BITS8_0             (DAC_CR_MAMP1_3                                                   ) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */

+#define DAC_LFSRUNMASK_BITS9_0             (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */

+#define DAC_LFSRUNMASK_BITS10_0            (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */

+#define DAC_LFSRUNMASK_BITS11_0            (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */

+#define DAC_TRIANGLEAMPLITUDE_1            0x00000000UL                                                        /*!< Select max triangle amplitude of 1 */

+#define DAC_TRIANGLEAMPLITUDE_3            (                                                   DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */

+#define DAC_TRIANGLEAMPLITUDE_7            (                                  DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 7 */

+#define DAC_TRIANGLEAMPLITUDE_15           (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */

+#define DAC_TRIANGLEAMPLITUDE_31           (                 DAC_CR_MAMP1_2                                  ) /*!< Select max triangle amplitude of 31 */

+#define DAC_TRIANGLEAMPLITUDE_63           (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */

+#define DAC_TRIANGLEAMPLITUDE_127          (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 127 */

+#define DAC_TRIANGLEAMPLITUDE_255          (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */

+#define DAC_TRIANGLEAMPLITUDE_511          (DAC_CR_MAMP1_3                                                   ) /*!< Select max triangle amplitude of 511 */

+#define DAC_TRIANGLEAMPLITUDE_1023         (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */

+#define DAC_TRIANGLEAMPLITUDE_2047         (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Select max triangle amplitude of 2047 */

+#define DAC_TRIANGLEAMPLITUDE_4095         (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+

+

+/* Private macro -------------------------------------------------------------*/

+

+/** @defgroup DACEx_Private_Macros DACEx Private Macros

+  * @{

+  */

+#if defined(HRTIM1)

+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE)       || \

+                                 ((TRIGGER) == DAC_TRIGGER_T1_TRGO)    || \

+                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO)    || \

+                                 ((TRIGGER) == DAC_TRIGGER_T4_TRGO)    || \

+                                 ((TRIGGER) == DAC_TRIGGER_T5_TRGO)    || \

+                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO)    || \

+                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO)    || \

+                                 ((TRIGGER) == DAC_TRIGGER_T8_TRGO)    || \

+                                 ((TRIGGER) == DAC_TRIGGER_T15_TRGO)   || \

+                                 ((TRIGGER) == DAC_TRIGGER_HR1_TRGO1)  || \

+                                 ((TRIGGER) == DAC_TRIGGER_HR1_TRGO2)  || \

+                                 ((TRIGGER) == DAC_TRIGGER_LPTIM1_OUT) || \

+                                 ((TRIGGER) == DAC_TRIGGER_LPTIM2_OUT) || \

+                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9)    || \

+                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))

+#elif defined(DAC2)

+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE)       || \

+                                 ((TRIGGER) == DAC_TRIGGER_T1_TRGO)    || \

+                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO)    || \

+                                 ((TRIGGER) == DAC_TRIGGER_T4_TRGO)    || \

+                                 ((TRIGGER) == DAC_TRIGGER_T5_TRGO)    || \

+                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO)    || \

+                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO)    || \

+                                 ((TRIGGER) == DAC_TRIGGER_T8_TRGO)    || \

+                                 ((TRIGGER) == DAC_TRIGGER_T15_TRGO)   || \

+                                 ((TRIGGER) == DAC_TRIGGER_LPTIM1_OUT) || \

+                                 ((TRIGGER) == DAC_TRIGGER_LPTIM2_OUT) || \

+                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9)    || \

+                                 ((TRIGGER) == DAC_TRIGGER_LPTIM3_OUT) || \

+                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))

+#else

+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE)       || \

+                                 ((TRIGGER) == DAC_TRIGGER_T1_TRGO)    || \

+                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO)    || \

+                                 ((TRIGGER) == DAC_TRIGGER_T4_TRGO)    || \

+                                 ((TRIGGER) == DAC_TRIGGER_T5_TRGO)    || \

+                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO)    || \

+                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO)    || \

+                                 ((TRIGGER) == DAC_TRIGGER_T8_TRGO)    || \

+                                 ((TRIGGER) == DAC_TRIGGER_T15_TRGO)   || \

+                                 ((TRIGGER) == DAC_TRIGGER_LPTIM1_OUT) || \

+                                 ((TRIGGER) == DAC_TRIGGER_LPTIM2_OUT) || \

+                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9)    || \

+                                 ((TRIGGER) == DAC_TRIGGER_T23_TRGO)   || \

+                                 ((TRIGGER) == DAC_TRIGGER_T24_TRGO)   || \

+                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))

+#endif

+

+#define IS_DAC_SAMPLETIME(TIME) ((TIME) <= 0x000003FFU)

+

+#define IS_DAC_HOLDTIME(TIME)   ((TIME) <= 0x000003FFU)

+

+#define IS_DAC_SAMPLEANDHOLD(MODE) (((MODE) == DAC_SAMPLEANDHOLD_DISABLE) || \

+                                    ((MODE) == DAC_SAMPLEANDHOLD_ENABLE))

+

+#define IS_DAC_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)

+

+#define IS_DAC_NEWTRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)

+

+#define IS_DAC_CHIP_CONNECTION(CONNECT) (((CONNECT) == DAC_CHIPCONNECT_EXTERNAL) || \

+                                         ((CONNECT) == DAC_CHIPCONNECT_INTERNAL) || \

+                                         ((CONNECT) == DAC_CHIPCONNECT_BOTH))

+

+#define IS_DAC_TRIMMING(TRIMMING) (((TRIMMING) == DAC_TRIMMING_FACTORY) || \

+                                   ((TRIMMING) == DAC_TRIMMING_USER))

+

+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \

+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \

+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \

+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \

+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \

+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \

+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \

+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \

+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \

+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \

+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \

+                                                      ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \

+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \

+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \

+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \

+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \

+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \

+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \

+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \

+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \

+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \

+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \

+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \

+                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/* Extended features functions ***********************************************/

+

+/** @addtogroup DACEx_Exported_Functions

+  * @{

+  */

+

+/** @addtogroup DACEx_Exported_Functions_Group2

+  * @{

+  */

+/* IO operation functions *****************************************************/

+

+HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);

+HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t Amplitude);

+

+HAL_StatusTypeDef HAL_DACEx_DualStart(DAC_HandleTypeDef *hdac);

+HAL_StatusTypeDef HAL_DACEx_DualStop(DAC_HandleTypeDef *hdac);

+HAL_StatusTypeDef HAL_DACEx_DualStart_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel, uint32_t *pData, uint32_t Length,

+                                          uint32_t Alignment);

+HAL_StatusTypeDef HAL_DACEx_DualStop_DMA(DAC_HandleTypeDef *hdac, uint32_t Channel);

+HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef *hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);

+uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef *hdac);

+

+void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef *hdac);

+void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef *hdac);

+void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac);

+void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac);

+

+

+/**

+  * @}

+  */

+

+/** @addtogroup DACEx_Exported_Functions_Group3

+  * @{

+  */

+/* Peripheral Control functions ***********************************************/

+

+HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel);

+HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_ChannelConfTypeDef *sConfig, uint32_t Channel,

+                                            uint32_t NewTrimmingValue);

+uint32_t HAL_DACEx_GetTrimOffset(DAC_HandleTypeDef *hdac, uint32_t Channel);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/** @addtogroup DACEx_Private_Functions

+  * @{

+  */

+

+/* DAC_DMAConvCpltCh2 / DAC_DMAErrorCh2 / DAC_DMAHalfConvCpltCh2 */

+/* are called by HAL_DAC_Start_DMA */

+void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);

+void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);

+void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* DAC1 || DAC2 */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /*STM32H7xx_HAL_DAC_EX_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_dcmi.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_dcmi.h
new file mode 100644
index 0000000000..d592e61248
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_dcmi.h
@@ -0,0 +1,671 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_dcmi.h

+  * @author  MCD Application Team

+  * @brief   Header file of DCMI HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_DCMI_H

+#define STM32H7xx_HAL_DCMI_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+#if defined (DCMI)

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup DCMI DCMI

+  * @brief DCMI HAL module driver

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup DCMI_Exported_Types DCMI Exported Types

+  * @{

+  */

+/**

+  * @brief  HAL DCMI State structures definition

+  */

+typedef enum

+{

+  HAL_DCMI_STATE_RESET             = 0x00U,  /*!< DCMI not yet initialized or disabled  */

+  HAL_DCMI_STATE_READY             = 0x01U,  /*!< DCMI initialized and ready for use    */

+  HAL_DCMI_STATE_BUSY              = 0x02U,  /*!< DCMI internal processing is ongoing   */

+  HAL_DCMI_STATE_TIMEOUT           = 0x03U,  /*!< DCMI timeout state                    */

+  HAL_DCMI_STATE_ERROR             = 0x04U,  /*!< DCMI error state                      */

+  HAL_DCMI_STATE_SUSPENDED         = 0x05U   /*!< DCMI suspend state                    */

+} HAL_DCMI_StateTypeDef;

+

+/**

+  * @brief   DCMI Embedded Synchronisation CODE Init structure definition

+  */

+typedef struct

+{

+  uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */

+  uint8_t LineStartCode;  /*!< Specifies the code of the line start delimiter.  */

+  uint8_t LineEndCode;    /*!< Specifies the code of the line end delimiter.    */

+  uint8_t FrameEndCode;   /*!< Specifies the code of the frame end delimiter.   */

+} DCMI_CodesInitTypeDef;

+

+/**

+  * @brief   DCMI Embedded Synchronisation UNMASK Init structure definition

+  */

+typedef struct

+{

+  uint8_t FrameStartUnmask; /*!< Specifies the frame start delimiter unmask. */

+  uint8_t LineStartUnmask;  /*!< Specifies the line start delimiter unmask.  */

+  uint8_t LineEndUnmask;    /*!< Specifies the line end delimiter unmask.    */

+  uint8_t FrameEndUnmask;   /*!< Specifies the frame end delimiter unmask.   */

+} DCMI_SyncUnmaskTypeDef;

+/**

+  * @brief   DCMI Init structure definition

+  */

+typedef struct

+{

+  uint32_t  SynchroMode;                /*!< Specifies the Synchronization Mode: Hardware or Embedded.

+                                             This parameter can be a value of @ref DCMI_Synchronization_Mode */

+

+  uint32_t  PCKPolarity;                /*!< Specifies the Pixel clock polarity: Falling or Rising.

+                                             This parameter can be a value of @ref DCMI_PIXCK_Polarity       */

+

+  uint32_t  VSPolarity;                 /*!< Specifies the Vertical synchronization polarity: High or Low.

+                                             This parameter can be a value of @ref DCMI_VSYNC_Polarity       */

+

+  uint32_t  HSPolarity;                 /*!< Specifies the Horizontal synchronization polarity: High or Low.

+                                             This parameter can be a value of @ref DCMI_HSYNC_Polarity       */

+

+  uint32_t  CaptureRate;                /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.

+                                             This parameter can be a value of @ref DCMI_Capture_Rate         */

+

+  uint32_t  ExtendedDataMode;           /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.

+                                             This parameter can be a value of @ref DCMI_Extended_Data_Mode   */

+

+  DCMI_CodesInitTypeDef SyncroCode;     /*!< Specifies the code of the line/frame start delimiter and the

+                                             line/frame end delimiter */

+

+  uint32_t JPEGMode;                    /*!< Enable or Disable the JPEG mode.

+                                             This parameter can be a value of @ref DCMI_MODE_JPEG            */

+

+  uint32_t ByteSelectMode;              /*!< Specifies the data to be captured by the interface

+                                            This parameter can be a value of @ref DCMI_Byte_Select_Mode      */

+

+  uint32_t ByteSelectStart;             /*!< Specifies if the data to be captured by the interface is even or odd

+                                            This parameter can be a value of @ref DCMI_Byte_Select_Start     */

+

+  uint32_t LineSelectMode;              /*!< Specifies the line of data to be captured by the interface

+                                            This parameter can be a value of @ref DCMI_Line_Select_Mode      */

+

+  uint32_t LineSelectStart;             /*!< Specifies if the line of data to be captured by the interface is even or odd

+                                            This parameter can be a value of @ref DCMI_Line_Select_Start     */

+} DCMI_InitTypeDef;

+

+/**

+  * @brief  DCMI handle Structure definition

+  */

+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)

+typedef struct  __DCMI_HandleTypeDef

+#else

+typedef struct

+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */

+{

+  DCMI_TypeDef                  *Instance;           /*!< DCMI Register base address   */

+

+  DCMI_InitTypeDef              Init;                /*!< DCMI parameters              */

+

+  HAL_LockTypeDef               Lock;                /*!< DCMI locking object          */

+

+  __IO HAL_DCMI_StateTypeDef    State;               /*!< DCMI state                   */

+

+  __IO uint32_t                 XferCount;           /*!< DMA transfer counter         */

+

+  __IO uint32_t                 XferSize;            /*!< DMA transfer size            */

+

+  uint32_t                      XferTransferNumber;  /*!< DMA transfer number          */

+

+  uint32_t                      pBuffPtr;            /*!< Pointer to DMA output buffer */

+

+  DMA_HandleTypeDef             *DMA_Handle;         /*!< Pointer to the DMA handler   */

+

+  __IO uint32_t                 ErrorCode;           /*!< DCMI Error code              */

+

+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)

+  void (* FrameEventCallback)(struct __DCMI_HandleTypeDef *hdcmi);       /*!< DCMI Frame Event Callback */

+  void (* VsyncEventCallback)(struct __DCMI_HandleTypeDef *hdcmi);       /*!< DCMI Vsync Event Callback */

+  void (* LineEventCallback)(struct __DCMI_HandleTypeDef *hdcmi);        /*!< DCMI Line Event Callback  */

+  void (* ErrorCallback)(struct __DCMI_HandleTypeDef *hdcmi);            /*!< DCMI Error Callback       */

+  void (* MspInitCallback)(struct __DCMI_HandleTypeDef *hdcmi);          /*!< DCMI Msp Init callback    */

+  void (* MspDeInitCallback)(struct __DCMI_HandleTypeDef *hdcmi);        /*!< DCMI Msp DeInit callback  */

+#endif  /* USE_HAL_DCMI_REGISTER_CALLBACKS */

+} DCMI_HandleTypeDef;

+

+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  HAL DCMI Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_DCMI_FRAME_EVENT_CB_ID    = 0x00U,    /*!< DCMI Frame Event Callback ID */

+  HAL_DCMI_VSYNC_EVENT_CB_ID    = 0x01U,    /*!< DCMI Vsync Event Callback ID */

+  HAL_DCMI_LINE_EVENT_CB_ID     = 0x02U,    /*!< DCMI Line Event Callback ID  */

+  HAL_DCMI_ERROR_CB_ID          = 0x03U,    /*!< DCMI Error Callback ID       */

+  HAL_DCMI_MSPINIT_CB_ID        = 0x04U,    /*!< DCMI MspInit callback ID     */

+  HAL_DCMI_MSPDEINIT_CB_ID      = 0x05U     /*!< DCMI MspDeInit callback ID   */

+

+} HAL_DCMI_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL DCMI Callback pointer definition

+  */

+typedef  void (*pDCMI_CallbackTypeDef)(DCMI_HandleTypeDef * hdcmi); /*!< pointer to a DCMI callback function */

+

+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+/* Exported constants --------------------------------------------------------*/

+

+/** @defgroup DCMI_Exported_Constants DCMI Exported Constants

+  * @{

+  */

+

+/** @defgroup DCMI_Error_Code DCMI Error Code

+  * @{

+  */

+#define HAL_DCMI_ERROR_NONE             (0x00000000U)  /*!< No error              */

+#define HAL_DCMI_ERROR_OVR              (0x00000001U)  /*!< Overrun error         */

+#define HAL_DCMI_ERROR_SYNC             (0x00000002U)  /*!< Synchronization error */

+#define HAL_DCMI_ERROR_TIMEOUT          (0x00000020U)  /*!< Timeout error         */

+#define HAL_DCMI_ERROR_DMA              (0x00000040U)  /*!< DMA error             */

+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)

+#define  HAL_DCMI_ERROR_INVALID_CALLBACK (0x00000080U)    /*!< Invalid Callback error  */

+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/** @defgroup DCMI_Capture_Mode DCMI Capture Mode

+  * @{

+  */

+#define DCMI_MODE_CONTINUOUS           (0x00000000U)  /*!< The received data are transferred continuously

+                                                                    into the destination memory through the DMA             */

+#define DCMI_MODE_SNAPSHOT             ((uint32_t)DCMI_CR_CM)  /*!< Once activated, the interface waits for the start of

+                                                                    frame and then transfers a single frame through the DMA */

+/**

+  * @}

+  */

+

+/** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode

+  * @{

+  */

+#define DCMI_SYNCHRO_HARDWARE        (0x00000000U)   /*!< Hardware synchronization data capture (frame/line start/stop)

+                                                                   is synchronized with the HSYNC/VSYNC signals                  */

+#define DCMI_SYNCHRO_EMBEDDED        ((uint32_t)DCMI_CR_ESS)  /*!< Embedded synchronization data capture is synchronized with

+                                                                   synchronization codes embedded in the data flow               */

+

+/**

+  * @}

+  */

+

+/** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity

+  * @{

+  */

+#define DCMI_PCKPOLARITY_FALLING    (0x00000000U)      /*!< Pixel clock active on Falling edge */

+#define DCMI_PCKPOLARITY_RISING     ((uint32_t)DCMI_CR_PCKPOL)  /*!< Pixel clock active on Rising edge  */

+

+/**

+  * @}

+  */

+

+/** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity

+  * @{

+  */

+#define DCMI_VSPOLARITY_LOW     (0x00000000U)     /*!< Vertical synchronization active Low  */

+#define DCMI_VSPOLARITY_HIGH    ((uint32_t)DCMI_CR_VSPOL)  /*!< Vertical synchronization active High */

+

+/**

+  * @}

+  */

+

+/** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity

+  * @{

+  */

+#define DCMI_HSPOLARITY_LOW     (0x00000000U)     /*!< Horizontal synchronization active Low  */

+#define DCMI_HSPOLARITY_HIGH    ((uint32_t)DCMI_CR_HSPOL)  /*!< Horizontal synchronization active High */

+

+/**

+  * @}

+  */

+

+/** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG

+  * @{

+  */

+#define DCMI_JPEG_DISABLE   (0x00000000U)    /*!< Mode JPEG Disabled  */

+#define DCMI_JPEG_ENABLE    ((uint32_t)DCMI_CR_JPEG)  /*!< Mode JPEG Enabled   */

+

+/**

+  * @}

+  */

+

+/** @defgroup DCMI_Capture_Rate DCMI Capture Rate

+  * @{

+  */

+#define DCMI_CR_ALL_FRAME            (0x00000000U)      /*!< All frames are captured        */

+#define DCMI_CR_ALTERNATE_2_FRAME    ((uint32_t)DCMI_CR_FCRC_0)  /*!< Every alternate frame captured */

+#define DCMI_CR_ALTERNATE_4_FRAME    ((uint32_t)DCMI_CR_FCRC_1)  /*!< One frame in 4 frames captured */

+

+/**

+  * @}

+  */

+

+/** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode

+  * @{

+  */

+#define DCMI_EXTEND_DATA_8B     (0x00000000U)                       /*!< Interface captures 8-bit data on every pixel clock  */

+#define DCMI_EXTEND_DATA_10B    ((uint32_t)DCMI_CR_EDM_0)                    /*!< Interface captures 10-bit data on every pixel clock */

+#define DCMI_EXTEND_DATA_12B    ((uint32_t)DCMI_CR_EDM_1)                    /*!< Interface captures 12-bit data on every pixel clock */

+#define DCMI_EXTEND_DATA_14B    ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1))  /*!< Interface captures 14-bit data on every pixel clock */

+

+/**

+  * @}

+  */

+

+/** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate

+  * @{

+  */

+#define DCMI_WINDOW_COORDINATE    (0x3FFFU)  /*!< Window coordinate */

+

+/**

+  * @}

+  */

+

+/** @defgroup DCMI_Window_Height DCMI Window Height

+  * @{

+  */

+#define DCMI_WINDOW_HEIGHT    (0x1FFFU)  /*!< Window Height */

+

+/**

+  * @}

+  */

+

+/** @defgroup DCMI_interrupt_sources  DCMI interrupt sources

+  * @{

+  */

+#define DCMI_IT_FRAME    ((uint32_t)DCMI_IER_FRAME_IE)    /*!< Capture complete interrupt      */

+#define DCMI_IT_OVR      ((uint32_t)DCMI_IER_OVR_IE)      /*!< Overrun interrupt               */

+#define DCMI_IT_ERR      ((uint32_t)DCMI_IER_ERR_IE)      /*!< Synchronization error interrupt */

+#define DCMI_IT_VSYNC    ((uint32_t)DCMI_IER_VSYNC_IE)    /*!< VSYNC interrupt                 */

+#define DCMI_IT_LINE     ((uint32_t)DCMI_IER_LINE_IE)     /*!< Line interrupt                  */

+/**

+  * @}

+  */

+

+/** @defgroup DCMI_Flags DCMI Flags

+  * @{

+  */

+

+/**

+  * @brief   DCMI SR register

+  */

+#define DCMI_FLAG_HSYNC     ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization between lines)   */

+#define DCMI_FLAG_VSYNC     ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization between frames) */

+#define DCMI_FLAG_FNE       ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE)   /*!< FIFO not empty flag                                                 */

+/**

+  * @brief   DCMI RIS register

+  */

+#define DCMI_FLAG_FRAMERI    ((uint32_t)DCMI_RIS_FRAME_RIS)  /*!< Frame capture complete interrupt flag */

+#define DCMI_FLAG_OVRRI      ((uint32_t)DCMI_RIS_OVR_RIS)    /*!< Overrun interrupt flag                */

+#define DCMI_FLAG_ERRRI      ((uint32_t)DCMI_RIS_ERR_RIS)    /*!< Synchronization error interrupt flag  */

+#define DCMI_FLAG_VSYNCRI    ((uint32_t)DCMI_RIS_VSYNC_RIS)  /*!< VSYNC interrupt flag                  */

+#define DCMI_FLAG_LINERI     ((uint32_t)DCMI_RIS_LINE_RIS)   /*!< Line interrupt flag                   */

+/**

+  * @brief   DCMI MIS register

+  */

+#define DCMI_FLAG_FRAMEMI    ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS)  /*!< DCMI Frame capture complete masked interrupt status */

+#define DCMI_FLAG_OVRMI      ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS  )  /*!< DCMI Overrun masked interrupt status                */

+#define DCMI_FLAG_ERRMI      ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS  )  /*!< DCMI Synchronization error masked interrupt status  */

+#define DCMI_FLAG_VSYNCMI    ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS)  /*!< DCMI VSYNC masked interrupt status                  */

+#define DCMI_FLAG_LINEMI     ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS )  /*!< DCMI Line masked interrupt status                   */

+/**

+  * @}

+  */

+

+/** @defgroup DCMI_Byte_Select_Mode DCMI Byte Select Mode

+  * @{

+  */

+#define DCMI_BSM_ALL                 (0x00000000U) /*!< Interface captures all received data */

+#define DCMI_BSM_OTHER               ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte from the received data */

+#define DCMI_BSM_ALTERNATE_4         ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */

+#define DCMI_BSM_ALTERNATE_2         ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */

+

+/**

+  * @}

+  */

+

+/** @defgroup DCMI_Byte_Select_Start DCMI Byte Select Start

+  * @{

+  */

+#define DCMI_OEBS_ODD               (0x00000000U) /*!< Interface captures first data from the frame/line start, second one being dropped */

+#define DCMI_OEBS_EVEN              ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from the frame/line start, first one being dropped */

+

+/**

+  * @}

+  */

+

+/** @defgroup DCMI_Line_Select_Mode DCMI Line Select Mode

+  * @{

+  */

+#define DCMI_LSM_ALL                 (0x00000000U) /*!< Interface captures all received lines */

+#define DCMI_LSM_ALTERNATE_2         ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */

+

+/**

+  * @}

+  */

+

+/** @defgroup DCMI_Line_Select_Start DCMI Line Select Start

+  * @{

+  */

+#define DCMI_OELS_ODD               (0x00000000U) /*!< Interface captures first line from the frame start, second one being dropped */

+#define DCMI_OELS_EVEN              ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start, first one being dropped */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup DCMI_Exported_Macros DCMI Exported Macros

+  * @{

+  */

+

+/** @brief Reset DCMI handle state

+  * @param  __HANDLE__ specifies the DCMI handle.

+  * @retval None

+  */

+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)

+#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__)  do{                                             \

+                                                       (__HANDLE__)->State = HAL_DCMI_STATE_RESET; \

+                                                       (__HANDLE__)->MspInitCallback = NULL;       \

+                                                       (__HANDLE__)->MspDeInitCallback = NULL;     \

+                                                     } while(0)

+#else

+#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)

+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */

+

+/**

+  * @brief  Enable the DCMI.

+  * @param  __HANDLE__ DCMI handle

+  * @retval None

+  */

+#define __HAL_DCMI_ENABLE(__HANDLE__)    ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)

+

+/**

+  * @brief  Disable the DCMI.

+  * @param  __HANDLE__ DCMI handle

+  * @retval None

+  */

+#define __HAL_DCMI_DISABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))

+

+/* Interrupt & Flag management */

+/**

+  * @brief  Get the DCMI pending flag.

+  * @param  __HANDLE__ DCMI handle

+  * @param  __FLAG__ Get the specified flag.

+  *         This parameter can be one of the following values (no combination allowed)

+  *            @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines)

+  *            @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames)

+  *            @arg DCMI_FLAG_FNE: FIFO empty flag

+  *            @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask

+  *            @arg DCMI_FLAG_OVRRI: Overrun flag mask

+  *            @arg DCMI_FLAG_ERRRI: Synchronization error flag mask

+  *            @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask

+  *            @arg DCMI_FLAG_LINERI: Line flag mask

+  *            @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status

+  *            @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status

+  *            @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status

+  *            @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status

+  *            @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status

+  * @retval The state of FLAG.

+  */

+#define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\

+((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0)? ((__HANDLE__)->Instance->RIS & (__FLAG__)) :\

+ (((__FLAG__) & DCMI_SR_INDEX) == 0x0)? ((__HANDLE__)->Instance->MIS & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))

+

+/**

+  * @brief  Clear the DCMI pending flags.

+  * @param  __HANDLE__ DCMI handle

+  * @param  __FLAG__ specifies the flag to clear.

+  *         This parameter can be any combination of the following values:

+  *            @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask

+  *            @arg DCMI_FLAG_OVFRI: Overflow flag mask

+  *            @arg DCMI_FLAG_ERRRI: Synchronization error flag mask

+  *            @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask

+  *            @arg DCMI_FLAG_LINERI: Line flag mask

+  * @retval None

+  */

+#define __HAL_DCMI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))

+

+/**

+  * @brief  Enable the specified DCMI interrupts.

+  * @param  __HANDLE__    DCMI handle

+  * @param  __INTERRUPT__ specifies the DCMI interrupt sources to be enabled.

+  *         This parameter can be any combination of the following values:

+  *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask

+  *            @arg DCMI_IT_OVF: Overflow interrupt mask

+  *            @arg DCMI_IT_ERR: Synchronization error interrupt mask

+  *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask

+  *            @arg DCMI_IT_LINE: Line interrupt mask

+  * @retval None

+  */

+#define __HAL_DCMI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))

+

+/**

+  * @brief  Disable the specified DCMI interrupts.

+  * @param  __HANDLE__ DCMI handle

+  * @param  __INTERRUPT__ specifies the DCMI interrupt sources to be enabled.

+  *         This parameter can be any combination of the following values:

+  *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask

+  *            @arg DCMI_IT_OVF: Overflow interrupt mask

+  *            @arg DCMI_IT_ERR: Synchronization error interrupt mask

+  *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask

+  *            @arg DCMI_IT_LINE: Line interrupt mask

+  * @retval None

+  */

+#define __HAL_DCMI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))

+

+/**

+  * @brief  Check whether the specified DCMI interrupt has occurred or not.

+  * @param  __HANDLE__ DCMI handle

+  * @param  __INTERRUPT__ specifies the DCMI interrupt source to check.

+  *         This parameter can be one of the following values:

+  *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask

+  *            @arg DCMI_IT_OVF: Overflow interrupt mask

+  *            @arg DCMI_IT_ERR: Synchronization error interrupt mask

+  *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask

+  *            @arg DCMI_IT_LINE: Line interrupt mask

+  * @retval The state of INTERRUPT.

+  */

+#define __HAL_DCMI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MISR & (__INTERRUPT__))

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup DCMI_Exported_Functions DCMI Exported Functions

+  * @{

+  */

+

+/** @addtogroup DCMI_Exported_Functions_Group1 Initialization and Configuration functions

+ * @{

+ */

+/* Initialization and de-initialization functions *****************************/

+HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi);

+HAL_StatusTypeDef HAL_DCMI_DeInit(DCMI_HandleTypeDef *hdcmi);

+void       HAL_DCMI_MspInit(DCMI_HandleTypeDef* hdcmi);

+void       HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);

+

+/* Callbacks Register/UnRegister functions  ***********************************/

+#if (USE_HAL_DCMI_REGISTER_CALLBACKS == 1)

+HAL_StatusTypeDef HAL_DCMI_RegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID, pDCMI_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_DCMI_UnRegisterCallback(DCMI_HandleTypeDef *hdcmi, HAL_DCMI_CallbackIDTypeDef CallbackID);

+#endif /* USE_HAL_DCMI_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+/** @addtogroup DCMI_Exported_Functions_Group2 IO operation functions

+ * @{

+ */

+/* IO operation functions *****************************************************/

+HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);

+HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi);

+HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi);

+HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi);

+void       HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);

+void       HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);

+void       HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);

+void       HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);

+void       HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);

+/**

+  * @}

+  */

+

+/** @addtogroup DCMI_Exported_Functions_Group3 Peripheral Control functions

+ * @{

+ */

+/* Peripheral Control functions ***********************************************/

+HAL_StatusTypeDef     HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);

+HAL_StatusTypeDef     HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);

+HAL_StatusTypeDef     HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);

+HAL_StatusTypeDef     HAL_DCMI_ConfigSyncUnmask(DCMI_HandleTypeDef *hdcmi, DCMI_SyncUnmaskTypeDef *SyncUnmask);

+

+/**

+  * @}

+  */

+

+/** @addtogroup DCMI_Exported_Functions_Group4 Peripheral State functions

+ * @{

+ */

+/* Peripheral State functions *************************************************/

+HAL_DCMI_StateTypeDef HAL_DCMI_GetState(DCMI_HandleTypeDef *hdcmi);

+uint32_t              HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup DCMI_Private_Constants DCMI Private Constants

+  * @{

+  */

+#define DCMI_MIS_INDEX        ((uint32_t)0x1000) /*!< DCMI MIS register index */

+#define DCMI_SR_INDEX         ((uint32_t)0x2000) /*!< DCMI SR register index  */

+/**

+  * @}

+  */

+/* Private macro -------------------------------------------------------------*/

+/** @defgroup DCMI_Private_Macros DCMI Private Macros

+  * @{

+  */

+#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_MODE_CONTINUOUS) || \

+                                   ((MODE) == DCMI_MODE_SNAPSHOT))

+

+#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SYNCHRO_HARDWARE) || \

+                              ((MODE) == DCMI_SYNCHRO_EMBEDDED))

+

+#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPOLARITY_FALLING) || \

+                                      ((POLARITY) == DCMI_PCKPOLARITY_RISING))

+

+#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPOLARITY_LOW) || \

+                                     ((POLARITY) == DCMI_VSPOLARITY_HIGH))

+

+#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPOLARITY_LOW) || \

+                                     ((POLARITY) == DCMI_HSPOLARITY_HIGH))

+

+#define IS_DCMI_MODE_JPEG(JPEG_MODE)(((JPEG_MODE) == DCMI_JPEG_DISABLE) || \

+                                     ((JPEG_MODE) == DCMI_JPEG_ENABLE))

+

+#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CR_ALL_FRAME)         || \

+                                    ((RATE) == DCMI_CR_ALTERNATE_2_FRAME) || \

+                                    ((RATE) == DCMI_CR_ALTERNATE_4_FRAME))

+

+#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_EXTEND_DATA_8B)  || \

+                                    ((DATA) == DCMI_EXTEND_DATA_10B) || \

+                                    ((DATA) == DCMI_EXTEND_DATA_12B) || \

+                                    ((DATA) == DCMI_EXTEND_DATA_14B))

+

+#define IS_DCMI_WINDOW_COORDINATE(COORDINATE) ((COORDINATE) <= DCMI_WINDOW_COORDINATE)

+

+#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)

+

+#define IS_DCMI_BYTE_SELECT_MODE(MODE)(((MODE) == DCMI_BSM_ALL) || \

+                                       ((MODE) == DCMI_BSM_OTHER) || \

+                                       ((MODE) == DCMI_BSM_ALTERNATE_4) || \

+                                       ((MODE) == DCMI_BSM_ALTERNATE_2))

+

+#define IS_DCMI_BYTE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OEBS_ODD) || \

+                                            ((POLARITY) == DCMI_OEBS_EVEN))

+

+#define IS_DCMI_LINE_SELECT_MODE(MODE)(((MODE) == DCMI_LSM_ALL) || \

+                                       ((MODE) == DCMI_LSM_ALTERNATE_2))

+

+#define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \

+                                            ((POLARITY) == DCMI_OELS_EVEN))

+

+/**

+  * @}

+  */

+

+/* Private functions ---------------------------------------------------------*/

+/** @addtogroup DCMI_Private_Functions DCMI Private Functions

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+/**

+  * @}

+  */

+

+#endif /* DCMI */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_DCMI_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_def.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_def.h
new file mode 100644
index 0000000000..fce605de8e
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_def.h
@@ -0,0 +1,188 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_def.h

+  * @author  MCD Application Team

+  * @brief   This file contains HAL common defines, enumeration, macros and

+  *          structures definitions.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_DEF

+#define STM32H7xx_HAL_DEF

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+#include "Legacy/stm32_hal_legacy.h"

+#include <stddef.h>

+#include <math.h>

+

+/* Exported types ------------------------------------------------------------*/

+

+/**

+  * @brief  HAL Status structures definition

+  */

+typedef enum

+{

+  HAL_OK       = 0x00,

+  HAL_ERROR    = 0x01,

+  HAL_BUSY     = 0x02,

+  HAL_TIMEOUT  = 0x03

+} HAL_StatusTypeDef;

+

+/**

+  * @brief  HAL Lock structures definition

+  */

+typedef enum

+{

+  HAL_UNLOCKED = 0x00,

+  HAL_LOCKED   = 0x01

+} HAL_LockTypeDef;

+

+/* Exported macro ------------------------------------------------------------*/

+

+#define HAL_MAX_DELAY      0xFFFFFFFFU

+

+#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) == (BIT))

+#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == 0U)

+

+#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__)               \

+                        do{                                                      \

+                              (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \

+                              (__DMA_HANDLE__).Parent = (__HANDLE__);             \

+                          } while(0)

+

+#define UNUSED(x) ((void)(x))

+

+/** @brief Reset the Handle's State field.

+  * @param __HANDLE__: specifies the Peripheral Handle.

+  * @note  This macro can be used for the following purpose: 

+  *          - When the Handle is declared as local variable; before passing it as parameter

+  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro 

+  *            to set to 0 the Handle's "State" field.

+  *            Otherwise, "State" field may have any random value and the first time the function 

+  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed

+  *            (i.e. HAL_PPP_MspInit() will not be executed).

+  *          - When there is a need to reconfigure the low level hardware: instead of calling

+  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().

+  *            In this later function, when the Handle's "State" field is set to 0, it will execute the function

+  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.

+  * @retval None

+  */

+#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)

+

+#if (USE_RTOS == 1)

+  #error " USE_RTOS should be 0 in the current HAL release "

+#else

+  #define __HAL_LOCK(__HANDLE__)                                           \

+                                do{                                        \

+                                    if((__HANDLE__)->Lock == HAL_LOCKED)   \

+                                    {                                      \

+                                       return HAL_BUSY;                    \

+                                    }                                      \

+                                    else                                   \

+                                    {                                      \

+                                       (__HANDLE__)->Lock = HAL_LOCKED;    \

+                                    }                                      \

+                                  }while (0)

+

+  #define __HAL_UNLOCK(__HANDLE__)                                          \

+                                  do{                                       \

+                                      (__HANDLE__)->Lock = HAL_UNLOCKED;    \

+                                    }while (0)

+#endif /* USE_RTOS */

+

+#if  defined ( __GNUC__ )

+  #ifndef __weak

+    #define __weak   __attribute__((weak))

+  #endif /* __weak */

+  #ifndef __packed

+    #define __packed __attribute__((__packed__))

+  #endif /* __packed */

+#endif /* __GNUC__ */

+

+

+/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */

+#if defined   (__GNUC__)        /* GNU Compiler */

+  #ifndef __ALIGN_END

+    #define __ALIGN_END    __attribute__ ((aligned (4)))

+  #endif /* __ALIGN_END */

+  #ifndef __ALIGN_BEGIN

+    #define __ALIGN_BEGIN

+  #endif /* __ALIGN_BEGIN */

+#else

+  #ifndef __ALIGN_END

+    #define __ALIGN_END

+  #endif /* __ALIGN_END */

+  #ifndef __ALIGN_BEGIN

+    #if defined   (__CC_ARM)      /* ARM Compiler */

+      #define __ALIGN_BEGIN    __align(4)

+    #elif defined (__ICCARM__)    /* IAR Compiler */

+      #define __ALIGN_BEGIN

+    #endif /* __CC_ARM */

+  #endif /* __ALIGN_BEGIN */

+#endif /* __GNUC__ */

+

+/* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */

+#if defined   (__GNUC__)        /* GNU Compiler */

+  #define ALIGN_32BYTES(buf)  buf __attribute__ ((aligned (32)))                                    

+#elif defined (__ICCARM__)    /* IAR Compiler */

+  #define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf  

+#elif defined   (__CC_ARM)      /* ARM Compiler */

+  #define ALIGN_32BYTES(buf) __align(32) buf  

+#endif

+

+/**

+  * @brief  __RAM_FUNC definition

+  */

+#if defined ( __CC_ARM   )

+/* ARM Compiler

+   ------------

+   RAM functions are defined using the toolchain options.

+   Functions that are executed in RAM should reside in a separate source module.

+   Using the 'Options for File' dialog you can simply change the 'Code / Const'

+   area of a module to a memory space in physical RAM.

+   Available memory areas are declared in the 'Target' tab of the 'Options for Target'

+   dialog.

+*/

+#define __RAM_FUNC

+

+#elif defined ( __ICCARM__ )

+/* ICCARM Compiler

+   ---------------

+   RAM functions are defined using a specific toolchain keyword "__ramfunc".

+*/

+#define __RAM_FUNC __ramfunc

+

+#elif defined   (  __GNUC__  )

+/* GNU Compiler

+   ------------

+  RAM functions are defined using a specific toolchain attribute

+   "__attribute__((section(".RamFunc")))".

+*/

+#define __RAM_FUNC __attribute__((section(".RamFunc")))

+

+#endif

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_DEF */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_dfsdm.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_dfsdm.h
new file mode 100644
index 0000000000..c5c9215983
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_dfsdm.h
@@ -0,0 +1,851 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_dfsdm.h

+  * @author  MCD Application Team

+  * @brief   Header file of DFSDM HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_DFSDM_H

+#define STM32H7xx_HAL_DFSDM_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup DFSDM

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup DFSDM_Exported_Types DFSDM Exported Types

+  * @{

+  */

+

+/**

+  * @brief  HAL DFSDM Channel states definition

+  */

+typedef enum

+{

+  HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */

+  HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */

+  HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU  /*!< DFSDM channel state error */

+} HAL_DFSDM_Channel_StateTypeDef;

+

+/**

+  * @brief  DFSDM channel output clock structure definition

+  */

+typedef struct

+{

+  FunctionalState Activation; /*!< Output clock enable/disable */

+  uint32_t        Selection;  /*!< Output clock is system clock or audio clock.

+                                   This parameter can be a value of @ref DFSDM_Channel_OuputClock */

+  uint32_t        Divider;    /*!< Output clock divider.

+                                   This parameter must be a number between Min_Data = 2 and Max_Data = 256 */

+} DFSDM_Channel_OutputClockTypeDef;

+

+/**

+  * @brief  DFSDM channel input structure definition

+  */

+typedef struct

+{

+  uint32_t Multiplexer; /*!< Input is external serial inputs, internal register or ADC output.

+                             This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */

+  uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register.

+                             This parameter can be a value of @ref DFSDM_Channel_DataPacking */

+  uint32_t Pins;        /*!< Input pins are taken from same or following channel.

+                             This parameter can be a value of @ref DFSDM_Channel_InputPins */

+} DFSDM_Channel_InputTypeDef;

+

+/**

+  * @brief  DFSDM channel serial interface structure definition

+  */

+typedef struct

+{

+  uint32_t Type;     /*!< SPI or Manchester modes.

+                          This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */

+  uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point).

+                          This parameter can be a value of @ref DFSDM_Channel_SpiClock */

+} DFSDM_Channel_SerialInterfaceTypeDef;

+

+/**

+  * @brief  DFSDM channel analog watchdog structure definition

+  */

+typedef struct

+{

+  uint32_t FilterOrder;  /*!< Analog watchdog Sinc filter order.

+                              This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */

+  uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio.

+                              This parameter must be a number between Min_Data = 1 and Max_Data = 32 */

+} DFSDM_Channel_AwdTypeDef;

+

+/**

+  * @brief  DFSDM channel init structure definition

+  */

+typedef struct

+{

+  DFSDM_Channel_OutputClockTypeDef     OutputClock;     /*!< DFSDM channel output clock parameters */

+  DFSDM_Channel_InputTypeDef           Input;           /*!< DFSDM channel input parameters */

+  DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */

+  DFSDM_Channel_AwdTypeDef             Awd;             /*!< DFSDM channel analog watchdog parameters */

+  int32_t                              Offset;          /*!< DFSDM channel offset.

+                                                             This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */

+  uint32_t                             RightBitShift;   /*!< DFSDM channel right bit shift.

+                                                             This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */

+} DFSDM_Channel_InitTypeDef;

+

+/**

+  * @brief  DFSDM channel handle structure definition

+  */

+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)

+typedef struct __DFSDM_Channel_HandleTypeDef

+#else

+typedef struct

+#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */

+{

+  DFSDM_Channel_TypeDef          *Instance; /*!< DFSDM channel instance */

+  DFSDM_Channel_InitTypeDef      Init;      /*!< DFSDM channel init parameters */

+  HAL_DFSDM_Channel_StateTypeDef State;     /*!< DFSDM channel state */

+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)

+  void (*CkabCallback)      (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel clock absence detection callback */

+  void (*ScdCallback)       (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel short circuit detection callback */

+  void (*MspInitCallback)   (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP init callback */

+  void (*MspDeInitCallback) (struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP de-init callback */

+#endif

+} DFSDM_Channel_HandleTypeDef;

+

+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  DFSDM channel callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_DFSDM_CHANNEL_CKAB_CB_ID      = 0x00U, /*!< DFSDM channel clock absence detection callback ID */

+  HAL_DFSDM_CHANNEL_SCD_CB_ID       = 0x01U, /*!< DFSDM channel short circuit detection callback ID */

+  HAL_DFSDM_CHANNEL_MSPINIT_CB_ID   = 0x02U, /*!< DFSDM channel MSP init callback ID */

+  HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID = 0x03U  /*!< DFSDM channel MSP de-init callback ID */

+} HAL_DFSDM_Channel_CallbackIDTypeDef;

+

+/**

+  * @brief  DFSDM channel callback pointer definition

+  */

+typedef void (*pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

+#endif

+

+/**

+  * @brief  HAL DFSDM Filter states definition

+  */

+typedef enum

+{

+  HAL_DFSDM_FILTER_STATE_RESET   = 0x00U, /*!< DFSDM filter not initialized */

+  HAL_DFSDM_FILTER_STATE_READY   = 0x01U, /*!< DFSDM filter initialized and ready for use */

+  HAL_DFSDM_FILTER_STATE_REG     = 0x02U, /*!< DFSDM filter regular conversion in progress */

+  HAL_DFSDM_FILTER_STATE_INJ     = 0x03U, /*!< DFSDM filter injected conversion in progress */

+  HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */

+  HAL_DFSDM_FILTER_STATE_ERROR   = 0xFFU  /*!< DFSDM filter state error */

+} HAL_DFSDM_Filter_StateTypeDef;

+

+/**

+  * @brief  DFSDM filter regular conversion parameters structure definition

+  */

+typedef struct

+{

+  uint32_t        Trigger;  /*!< Trigger used to start regular conversion: software or synchronous.

+                                 This parameter can be a value of @ref DFSDM_Filter_Trigger */

+  FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */

+  FunctionalState DmaMode;  /*!< Enable/disable DMA for regular conversion */

+} DFSDM_Filter_RegularParamTypeDef;

+

+/**

+  * @brief  DFSDM filter injected conversion parameters structure definition

+  */

+typedef struct

+{

+  uint32_t        Trigger;        /*!< Trigger used to start injected conversion: software, external or synchronous.

+                                       This parameter can be a value of @ref DFSDM_Filter_Trigger */

+  FunctionalState ScanMode;       /*!< Enable/disable scanning mode for injected conversion */

+  FunctionalState DmaMode;        /*!< Enable/disable DMA for injected conversion */

+  uint32_t        ExtTrigger;     /*!< External trigger.

+                                       This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */

+  uint32_t        ExtTriggerEdge; /*!< External trigger edge: rising, falling or both.

+                                       This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */

+} DFSDM_Filter_InjectedParamTypeDef;

+

+/**

+  * @brief  DFSDM filter parameters structure definition

+  */

+typedef struct

+{

+  uint32_t SincOrder;       /*!< Sinc filter order.

+                                 This parameter can be a value of @ref DFSDM_Filter_SincOrder */

+  uint32_t Oversampling;    /*!< Filter oversampling ratio.

+                                 This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */

+  uint32_t IntOversampling; /*!< Integrator oversampling ratio.

+                                 This parameter must be a number between Min_Data = 1 and Max_Data = 256 */

+} DFSDM_Filter_FilterParamTypeDef;

+

+/**

+  * @brief  DFSDM filter init structure definition

+  */

+typedef struct

+{

+  DFSDM_Filter_RegularParamTypeDef  RegularParam;  /*!< DFSDM regular conversion parameters */

+  DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */

+  DFSDM_Filter_FilterParamTypeDef   FilterParam;   /*!< DFSDM filter parameters */

+} DFSDM_Filter_InitTypeDef;

+

+/**

+  * @brief  DFSDM filter handle structure definition

+  */

+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)

+typedef struct __DFSDM_Filter_HandleTypeDef

+#else

+typedef struct

+#endif /* USE_HAL_DFSDM_REGISTER_CALLBACKS */

+{

+  DFSDM_Filter_TypeDef          *Instance;           /*!< DFSDM filter instance */

+  DFSDM_Filter_InitTypeDef      Init;                /*!< DFSDM filter init parameters */

+  DMA_HandleTypeDef             *hdmaReg;            /*!< Pointer on DMA handler for regular conversions */

+  DMA_HandleTypeDef             *hdmaInj;            /*!< Pointer on DMA handler for injected conversions */

+  uint32_t                      RegularContMode;     /*!< Regular conversion continuous mode */

+  uint32_t                      RegularTrigger;      /*!< Trigger used for regular conversion */

+  uint32_t                      InjectedTrigger;     /*!< Trigger used for injected conversion */

+  uint32_t                      ExtTriggerEdge;      /*!< Rising, falling or both edges selected */

+  FunctionalState               InjectedScanMode;    /*!< Injected scanning mode */

+  uint32_t                      InjectedChannelsNbr; /*!< Number of channels in injected sequence */

+  uint32_t                      InjConvRemaining;    /*!< Injected conversions remaining */

+  HAL_DFSDM_Filter_StateTypeDef State;               /*!< DFSDM filter state */

+  uint32_t                      ErrorCode;           /*!< DFSDM filter error code */

+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)

+  void (*AwdCallback)             (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter,

+                                   uint32_t Channel, uint32_t Threshold);               /*!< DFSDM filter analog watchdog callback */

+  void (*RegConvCpltCallback)     (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter regular conversion complete callback */

+  void (*RegConvHalfCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half regular conversion complete callback */

+  void (*InjConvCpltCallback)     (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter injected conversion complete callback */

+  void (*InjConvHalfCpltCallback) (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half injected conversion complete callback */

+  void (*ErrorCallback)           (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter error callback */

+  void (*MspInitCallback)         (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP init callback */

+  void (*MspDeInitCallback)       (struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP de-init callback */

+#endif

+}DFSDM_Filter_HandleTypeDef;

+

+/**

+  * @brief  DFSDM filter analog watchdog parameters structure definition

+  */

+typedef struct

+{

+  uint32_t DataSource;      /*!< Values from digital filter or from channel watchdog filter.

+                                 This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */

+  uint32_t Channel;         /*!< Analog watchdog channel selection.

+                                 This parameter can be a values combination of @ref DFSDM_Channel_Selection */

+  int32_t  HighThreshold;   /*!< High threshold for the analog watchdog.

+                                 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */

+  int32_t  LowThreshold;    /*!< Low threshold for the analog watchdog.

+                                 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */

+  uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event.

+                                 This parameter can be a values combination of @ref DFSDM_BreakSignals */

+  uint32_t LowBreakSignal;  /*!< Break signal assigned to analog watchdog low threshold event.

+                                 This parameter can be a values combination of @ref DFSDM_BreakSignals */

+} DFSDM_Filter_AwdParamTypeDef;

+

+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  DFSDM filter callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID     = 0x00U, /*!< DFSDM filter regular conversion complete callback ID */

+  HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID = 0x01U, /*!< DFSDM filter half regular conversion complete callback ID */

+  HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID     = 0x02U, /*!< DFSDM filter injected conversion complete callback ID */

+  HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID = 0x03U, /*!< DFSDM filter half injected conversion complete callback ID */

+  HAL_DFSDM_FILTER_ERROR_CB_ID                = 0x04U, /*!< DFSDM filter error callback ID */

+  HAL_DFSDM_FILTER_MSPINIT_CB_ID              = 0x05U, /*!< DFSDM filter MSP init callback ID */

+  HAL_DFSDM_FILTER_MSPDEINIT_CB_ID            = 0x06U  /*!< DFSDM filter MSP de-init callback ID */

+} HAL_DFSDM_Filter_CallbackIDTypeDef;

+

+/**

+  * @brief  DFSDM filter callback pointer definition

+  */

+typedef void (*pDFSDM_Filter_CallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

+typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);

+#endif

+

+/**

+  * @}

+  */

+/* End of exported types -----------------------------------------------------*/

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants

+  * @{

+  */

+

+/** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection

+  * @{

+  */

+#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM    0x00000000U            /*!< Source for ouput clock is system clock */

+#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO     DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */

+/**

+  * @}

+  */

+

+/** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer

+  * @{

+  */

+#define DFSDM_CHANNEL_EXTERNAL_INPUTS    0x00000000U             /*!< Data are taken from external inputs */

+#define DFSDM_CHANNEL_ADC_OUTPUT         DFSDM_CHCFGR1_DATMPX_0  /*!< Data are taken from ADC output */

+#define DFSDM_CHANNEL_INTERNAL_REGISTER  DFSDM_CHCFGR1_DATMPX_1  /*!< Data are taken from internal register */

+/**

+  * @}

+  */

+

+/** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing

+  * @{

+  */

+#define DFSDM_CHANNEL_STANDARD_MODE         0x00000000U             /*!< Standard data packing mode */

+#define DFSDM_CHANNEL_INTERLEAVED_MODE      DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */

+#define DFSDM_CHANNEL_DUAL_MODE             DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */

+/**

+  * @}

+  */

+

+/** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins

+  * @{

+  */

+#define DFSDM_CHANNEL_SAME_CHANNEL_PINS      0x00000000U            /*!< Input from pins on same channel */

+#define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL  /*!< Input from pins on following channel */

+/**

+  * @}

+  */

+

+/** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type

+  * @{

+  */

+#define DFSDM_CHANNEL_SPI_RISING         0x00000000U            /*!< SPI with rising edge */

+#define DFSDM_CHANNEL_SPI_FALLING        DFSDM_CHCFGR1_SITP_0   /*!< SPI with falling edge */

+#define DFSDM_CHANNEL_MANCHESTER_RISING  DFSDM_CHCFGR1_SITP_1   /*!< Manchester with rising edge */

+#define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP     /*!< Manchester with falling edge */

+/**

+  * @}

+  */

+

+/** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection

+  * @{

+  */

+#define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL              0x00000000U              /*!< External SPI clock */

+#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL              DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */

+#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */

+#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING  DFSDM_CHCFGR1_SPICKSEL   /*!< Internal SPI clock divided by 2, rising edge */

+/**

+  * @}

+  */

+

+/** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order

+  * @{

+  */

+#define DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U             /*!< FastSinc filter type */

+#define DFSDM_CHANNEL_SINC1_ORDER    DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */

+#define DFSDM_CHANNEL_SINC2_ORDER    DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */

+#define DFSDM_CHANNEL_SINC3_ORDER    DFSDM_CHAWSCDR_AWFORD   /*!< Sinc 3 filter type */

+/**

+  * @}

+  */

+

+/** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger

+  * @{

+  */

+#define DFSDM_FILTER_SW_TRIGGER   0x00000000U /*!< Software trigger */

+#define DFSDM_FILTER_SYNC_TRIGGER 0x00000001U /*!< Synchronous with DFSDM_FLT0 */

+#define DFSDM_FILTER_EXT_TRIGGER  0x00000002U /*!< External trigger (only for injected conversion) */

+/**

+  * @}

+  */

+

+/** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger

+  * @{

+  */

+#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO       0x00000000U                                       /*!< For all DFSDM filters */

+#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2      DFSDM_FLTCR1_JEXTSEL_0                            /*!< For all DFSDM filters */

+#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO       DFSDM_FLTCR1_JEXTSEL_1                            /*!< For all DFSDM filters */

+#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2      (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */

+#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO       DFSDM_FLTCR1_JEXTSEL_2                            /*!< For all DFSDM filters */

+#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO       (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2)                         /*!< For all DFSDM filters */

+#define DFSDM_FILTER_EXT_TRIG_TIM16_OC1       (DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1)                        /*!< For all DFSDM filters */

+#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO       (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */

+#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO       DFSDM_FLTCR1_JEXTSEL_3 /*!< For all DFSDM filters */

+#define DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG1  (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_0)

+#define DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG3  (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1)

+#define DFSDM_FILTER_EXT_TRIG_EXTI11          (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3) /*!< For all DFSDM filters */

+#define DFSDM_FILTER_EXT_TRIG_EXTI15          (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_0)                           /*!< For all DFSDM filters */

+#define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT      (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1)                           /*!< For all DFSDM filters */

+#define DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT      (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_0)  /*!< For all DFSDM filters */

+#define DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT      (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_2)                           /*!< For all DFSDM filters */

+#if defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ) || defined(STM32H7B0xx) || defined(STM32H7B0xxQ)

+#define DFSDM_FILTER_EXT_TRIG_COMP1_OUT      (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | \

+                                              DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_0)

+#define DFSDM_FILTER_EXT_TRIG_COMP2_OUT      (DFSDM_FLTCR1_JEXTSEL_4 | DFSDM_FLTCR1_JEXTSEL_3 | \

+                                              DFSDM_FLTCR1_JEXTSEL_2 | DFSDM_FLTCR1_JEXTSEL_1)

+#endif /* STM32H7A3xx || STM32H7A3xxQ || STM32H7B3xx || STM32H7B3xxQ || STM32H7B0xx || STM32H7B0xxQ */

+/**

+  * @}

+  */

+

+/** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge

+  * @{

+  */

+#define DFSDM_FILTER_EXT_TRIG_RISING_EDGE  DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */

+#define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */

+#define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES   DFSDM_FLTCR1_JEXTEN   /*!< External rising and falling edges */

+/**

+  * @}

+  */

+

+/** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order

+  * @{

+  */

+#define DFSDM_FILTER_FASTSINC_ORDER 0x00000000U                                 /*!< FastSinc filter type */

+#define DFSDM_FILTER_SINC1_ORDER    DFSDM_FLTFCR_FORD_0                         /*!< Sinc 1 filter type */

+#define DFSDM_FILTER_SINC2_ORDER    DFSDM_FLTFCR_FORD_1                         /*!< Sinc 2 filter type */

+#define DFSDM_FILTER_SINC3_ORDER    (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */

+#define DFSDM_FILTER_SINC4_ORDER    DFSDM_FLTFCR_FORD_2                         /*!< Sinc 4 filter type */

+#define DFSDM_FILTER_SINC5_ORDER    (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */

+/**

+  * @}

+  */

+

+/** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source

+  * @{

+  */

+#define DFSDM_FILTER_AWD_FILTER_DATA  0x00000000U             /*!< From digital filter */

+#define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL     /*!< From analog watchdog channel */

+/**

+  * @}

+  */

+

+/** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code

+  * @{

+  */

+#define DFSDM_FILTER_ERROR_NONE             0x00000000U /*!< No error */

+#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN  0x00000001U /*!< Overrun occurs during regular conversion */

+#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U /*!< Overrun occurs during injected conversion */

+#define DFSDM_FILTER_ERROR_DMA              0x00000003U /*!< DMA error occurs */

+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)

+#define DFSDM_FILTER_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid callback error occurs */

+#endif

+/**

+  * @}

+  */

+

+/** @defgroup DFSDM_BreakSignals DFSDM break signals

+  * @{

+  */

+#define DFSDM_NO_BREAK_SIGNAL 0x00000000U /*!< No break signal */

+#define DFSDM_BREAK_SIGNAL_0  0x00000001U /*!< Break signal 0 */

+#define DFSDM_BREAK_SIGNAL_1  0x00000002U /*!< Break signal 1 */

+#define DFSDM_BREAK_SIGNAL_2  0x00000004U /*!< Break signal 2 */

+#define DFSDM_BREAK_SIGNAL_3  0x00000008U /*!< Break signal 3 */

+/**

+  * @}

+  */

+

+/** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection

+  * @{

+  */

+/* DFSDM Channels ------------------------------------------------------------*/

+/* The DFSDM channels are defined as follows:

+   - in 16-bit LSB the channel mask is set

+   - in 16-bit MSB the channel number is set

+   e.g. for channel 5 definition:

+        - the channel mask is 0x00000020 (bit 5 is set)

+        - the channel number 5 is 0x00050000

+        --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */

+#define DFSDM_CHANNEL_0                              0x00000001U

+#define DFSDM_CHANNEL_1                              0x00010002U

+#define DFSDM_CHANNEL_2                              0x00020004U

+#define DFSDM_CHANNEL_3                              0x00030008U

+#define DFSDM_CHANNEL_4                              0x00040010U

+#define DFSDM_CHANNEL_5                              0x00050020U

+#define DFSDM_CHANNEL_6                              0x00060040U

+#define DFSDM_CHANNEL_7                              0x00070080U

+/**

+  * @}

+  */

+

+/** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode

+  * @{

+  */

+#define DFSDM_CONTINUOUS_CONV_OFF            0x00000000U /*!< Conversion are not continuous */

+#define DFSDM_CONTINUOUS_CONV_ON             0x00000001U /*!< Conversion are continuous */

+/**

+  * @}

+  */

+

+/** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold

+  * @{

+  */

+#define DFSDM_AWD_HIGH_THRESHOLD            0x00000000U /*!< Analog watchdog high threshold */

+#define DFSDM_AWD_LOW_THRESHOLD             0x00000001U /*!< Analog watchdog low threshold */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+/* End of exported constants -------------------------------------------------*/

+

+/* Exported macros -----------------------------------------------------------*/

+/** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros

+ * @{

+ */

+

+/** @brief  Reset DFSDM channel handle state.

+  * @param  __HANDLE__ DFSDM channel handle.

+  * @retval None

+  */

+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)

+#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) do{                                                      \

+                                                               (__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET; \

+                                                               (__HANDLE__)->MspInitCallback = NULL;                \

+                                                               (__HANDLE__)->MspDeInitCallback = NULL;              \

+                                                             } while(0)

+#else

+#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)

+#endif

+

+/** @brief  Reset DFSDM filter handle state.

+  * @param  __HANDLE__ DFSDM filter handle.

+  * @retval None

+  */

+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)

+#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) do{                                                     \

+                                                              (__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET; \

+                                                              (__HANDLE__)->MspInitCallback = NULL;               \

+                                                              (__HANDLE__)->MspDeInitCallback = NULL;             \

+                                                            } while(0)

+#else

+#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)

+#endif

+

+/**

+  * @}

+  */

+/* End of exported macros ----------------------------------------------------*/

+

+#if defined(DFSDM_CHDLYR_PLSSKP)

+/* Include DFSDM HAL Extension module */

+#include "stm32h7xx_hal_dfsdm_ex.h"

+#endif /* DFSDM_CHDLYR_PLSSKP */

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions

+  * @{

+  */

+

+/** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions

+  * @{

+  */

+/* Channel initialization and de-initialization functions *********************/

+HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

+HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

+void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

+void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

+

+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)

+/* Channel callbacks register/unregister functions ****************************/

+HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef        *hdfsdm_channel,

+                                                     HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID,

+                                                     pDFSDM_Channel_CallbackTypeDef      pCallback);

+HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef        *hdfsdm_channel,

+                                                       HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID);

+#endif

+/**

+  * @}

+  */

+

+/** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions

+  * @{

+  */

+/* Channel operation functions ************************************************/

+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

+HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

+

+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);

+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);

+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

+HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

+

+int16_t           HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

+HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);

+

+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);

+HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);

+

+void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

+void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

+/**

+  * @}

+  */

+

+/** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function

+  * @{

+  */

+/* Channel state function *****************************************************/

+HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);

+/**

+  * @}

+  */

+

+/** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions

+  * @{

+  */

+/* Filter initialization and de-initialization functions *********************/

+HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

+HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

+void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

+void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

+

+#if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1)

+/* Filter callbacks register/unregister functions ****************************/

+HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef        *hdfsdm_filter,

+                                                    HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID,

+                                                    pDFSDM_Filter_CallbackTypeDef      pCallback);

+HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef        *hdfsdm_filter,

+                                                      HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID);

+HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef      *hdfsdm_filter,

+                                                       pDFSDM_Filter_AwdCallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

+#endif

+/**

+  * @}

+  */

+

+/** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions

+  * @{

+  */

+/* Filter control functions *********************/

+HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,

+                                                   uint32_t                    Channel,

+                                                   uint32_t                    ContinuousMode);

+HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,

+                                                   uint32_t                    Channel);

+/**

+  * @}

+  */

+

+/** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions

+  * @{

+  */

+/* Filter operation functions *********************/

+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);

+HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);

+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

+HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);

+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);

+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

+HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

+HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,

+                                              DFSDM_Filter_AwdParamTypeDef *awdParam);

+HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

+HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);

+HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

+

+int32_t  HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);

+int32_t  HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);

+int32_t  HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);

+int32_t  HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel);

+uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

+

+void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

+

+HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);

+HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);

+

+void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

+void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

+void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

+void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

+void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);

+void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

+/**

+  * @}

+  */

+

+/** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions

+  * @{

+  */

+/* Filter state functions *****************************************************/

+HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

+uint32_t                      HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+/* End of exported functions -------------------------------------------------*/

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup DFSDM_Private_Macros DFSDM Private Macros

+* @{

+*/

+#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK)          (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \

+                                                       ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))

+#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U))

+#define IS_DFSDM_CHANNEL_INPUT(INPUT)                 (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \

+                                                       ((INPUT) == DFSDM_CHANNEL_ADC_OUTPUT) || \

+                                                       ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))

+#define IS_DFSDM_CHANNEL_DATA_PACKING(MODE)           (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \

+                                                       ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \

+                                                       ((MODE) == DFSDM_CHANNEL_DUAL_MODE))

+#define IS_DFSDM_CHANNEL_INPUT_PINS(PINS)             (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \

+                                                       ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))

+#define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE)  (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \

+                                                       ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \

+                                                       ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \

+                                                       ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))

+#define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE)              (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \

+                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \

+                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \

+                                                       ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))

+#define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER)          (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \

+                                                       ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \

+                                                       ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \

+                                                       ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))

+#define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO)       ((1U <= (RATIO)) && ((RATIO) <= 32U))

+#define IS_DFSDM_CHANNEL_OFFSET(VALUE)                 ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))

+#define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE)        ((VALUE) <= 0x1FU)

+#define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE)          ((VALUE) <= 0xFFU)

+#define IS_DFSDM_FILTER_REG_TRIGGER(TRIG)             (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \

+                                                       ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))

+#define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG)             (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \

+                                                       ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \

+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIGGER))

+#if defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ) || defined(STM32H7B0xx) || defined(STM32H7B0xxQ)

+#define IS_DFSDM_FILTER_EXT_TRIG(TRIG)                (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \

+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \

+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \

+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \

+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \

+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \

+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \

+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \

+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \

+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \

+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || \

+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT) || \

+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT) || \

+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT) || \

+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_COMP1_OUT) || \

+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_COMP2_OUT))

+#else

+#define IS_DFSDM_FILTER_EXT_TRIG(TRIG)                (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \

+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \

+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \

+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \

+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \

+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \

+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \

+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \

+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \

+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG1) || \

+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_HRTIM1_ADCTRG3) || \

+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \

+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || \

+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT) || \

+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT) || \

+                                                       ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT))

+#endif /* STM32H7A3xx || STM32H7A3xxQ || STM32H7B3xx || STM32H7B3xxQ || STM32H7B0xx  || STM32H7B0xxQ */

+#define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE)           (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE)  || \

+                                                       ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE)  || \

+                                                       ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))

+#define IS_DFSDM_FILTER_SINC_ORDER(ORDER)             (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \

+                                                       ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \

+                                                       ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \

+                                                       ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \

+                                                       ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \

+                                                       ((ORDER) == DFSDM_FILTER_SINC5_ORDER))

+#define IS_DFSDM_FILTER_OVS_RATIO(RATIO)               ((1U <= (RATIO)) && ((RATIO) <= 1024U))

+#define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO)    ((1U <= (RATIO)) && ((RATIO) <= 256U))

+#define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA)         (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA)  || \

+                                                       ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))

+#define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE)           ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))

+#define IS_DFSDM_BREAK_SIGNALS(VALUE)                  ((VALUE) <= 0xFU)

+#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL)             (((CHANNEL) == DFSDM_CHANNEL_0)  || \

+                                                       ((CHANNEL) == DFSDM_CHANNEL_1)  || \

+                                                       ((CHANNEL) == DFSDM_CHANNEL_2)  || \

+                                                       ((CHANNEL) == DFSDM_CHANNEL_3)  || \

+                                                       ((CHANNEL) == DFSDM_CHANNEL_4)  || \

+                                                       ((CHANNEL) == DFSDM_CHANNEL_5)  || \

+                                                       ((CHANNEL) == DFSDM_CHANNEL_6)  || \

+                                                       ((CHANNEL) == DFSDM_CHANNEL_7))

+#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL)            (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU))

+#define IS_DFSDM_CONTINUOUS_MODE(MODE)                (((MODE) == DFSDM_CONTINUOUS_CONV_OFF)  || \

+                                                       ((MODE) == DFSDM_CONTINUOUS_CONV_ON))

+#if defined(DFSDM2_Channel0)

+#define IS_DFSDM1_CHANNEL_INSTANCE(INSTANCE)          (((INSTANCE) == DFSDM1_Channel0) || \

+                                                       ((INSTANCE) == DFSDM1_Channel1) || \

+                                                       ((INSTANCE) == DFSDM1_Channel2) || \

+                                                       ((INSTANCE) == DFSDM1_Channel3) || \

+                                                       ((INSTANCE) == DFSDM1_Channel4) || \

+                                                       ((INSTANCE) == DFSDM1_Channel5) || \

+                                                       ((INSTANCE) == DFSDM1_Channel6) || \

+                                                       ((INSTANCE) == DFSDM1_Channel7))

+#define IS_DFSDM1_FILTER_INSTANCE(INSTANCE)           (((INSTANCE) == DFSDM1_Filter0) || \

+                                                       ((INSTANCE) == DFSDM1_Filter1) || \

+                                                       ((INSTANCE) == DFSDM1_Filter2) || \

+                                                       ((INSTANCE) == DFSDM1_Filter3) || \

+                                                       ((INSTANCE) == DFSDM1_Filter4) || \

+                                                       ((INSTANCE) == DFSDM1_Filter5) || \

+                                                       ((INSTANCE) == DFSDM1_Filter6) || \

+                                                       ((INSTANCE) == DFSDM1_Filter7))

+#endif /* DFSDM2_Channel0 */

+/**

+  * @}

+  */

+/* End of private macros -----------------------------------------------------*/

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_DFSDM_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_dfsdm_ex.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_dfsdm_ex.h
new file mode 100644
index 0000000000..e7fe686249
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_dfsdm_ex.h
@@ -0,0 +1,93 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_dfsdm_ex.h

+  * @author  MCD Application Team

+  * @brief   Header file of DFSDM HAL extended module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_DFSDM_EX_H

+#define STM32H7xx_HAL_DFSDM_EX_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+#if defined(DFSDM_CHDLYR_PLSSKP)

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup DFSDMEx

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/* Exported constants --------------------------------------------------------*/

+/* Exported macros -----------------------------------------------------------*/

+/* Exported functions --------------------------------------------------------*/

+

+/** @addtogroup DFSDMEx_Exported_Functions DFSDM Extended Exported Functions

+  * @{

+  */

+

+/** @addtogroup DFSDMEx_Exported_Functions_Group1_Channel Extended channel operation functions

+  * @{

+  */

+

+HAL_StatusTypeDef HAL_DFDSMEx_ChannelSetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t PulsesValue);

+HAL_StatusTypeDef HAL_DFDSMEx_ChannelGetPulsesSkipping(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t *PulsesValue);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+

+/** @addtogroup DFSDMEx_Private_Macros DFSDM Extended Private Macros

+  * @{

+  */

+

+#define IS_DFSDM_CHANNEL_SKIPPING_VALUE(VALUE)   ((VALUE) < 64U)

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* DFSDM_CHDLYR_PLSSKP */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_DFSDM_EX_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_dma.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_dma.h
new file mode 100644
index 0000000000..36d553b0a6
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_dma.h
@@ -0,0 +1,1290 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_dma.h

+  * @author  MCD Application Team

+  * @brief   Header file of DMA HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_DMA_H

+#define STM32H7xx_HAL_DMA_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup DMA

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+

+/** @defgroup DMA_Exported_Types DMA Exported Types

+  * @brief    DMA Exported Types

+  * @{

+  */

+

+/**

+  * @brief  DMA Configuration Structure definition

+  */

+typedef struct

+{

+  uint32_t Request;               /*!< Specifies the request selected for the specified stream.

+                                           This parameter can be a value of @ref DMA_Request_selection              */

+

+  uint32_t Direction;            /*!< Specifies if the data will be transferred from memory to peripheral,

+                                      from memory to memory or from peripheral to memory.

+                                      This parameter can be a value of @ref DMA_Data_transfer_direction              */

+

+  uint32_t PeriphInc;            /*!< Specifies whether the Peripheral address register should be incremented or not.

+                                      This parameter can be a value of @ref DMA_Peripheral_incremented_mode          */

+

+  uint32_t MemInc;               /*!< Specifies whether the memory address register should be incremented or not.

+                                      This parameter can be a value of @ref DMA_Memory_incremented_mode              */

+

+  uint32_t PeriphDataAlignment;  /*!< Specifies the Peripheral data width.

+                                      This parameter can be a value of @ref DMA_Peripheral_data_size                 */

+

+  uint32_t MemDataAlignment;     /*!< Specifies the Memory data width.

+                                      This parameter can be a value of @ref DMA_Memory_data_size                     */

+

+  uint32_t Mode;                 /*!< Specifies the operation mode of the DMAy Streamx.

+                                      This parameter can be a value of @ref DMA_mode

+                                      @note The circular buffer mode cannot be used if the memory-to-memory

+                                            data transfer is configured on the selected Stream                        */

+

+  uint32_t Priority;             /*!< Specifies the software priority for the DMAy Streamx.

+                                      This parameter can be a value of @ref DMA_Priority_level                        */

+

+  uint32_t FIFOMode;             /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.

+                                      This parameter can be a value of @ref DMA_FIFO_direct_mode

+                                      @note The Direct mode (FIFO mode disabled) cannot be used if the

+                                            memory-to-memory data transfer is configured on the selected stream       */

+

+  uint32_t FIFOThreshold;        /*!< Specifies the FIFO threshold level.

+                                      This parameter can be a value of @ref DMA_FIFO_threshold_level                  */

+

+  uint32_t MemBurst;             /*!< Specifies the Burst transfer configuration for the memory transfers.

+                                      It specifies the amount of data to be transferred in a single non interruptible

+                                      transaction.

+                                      This parameter can be a value of @ref DMA_Memory_burst

+                                      @note The burst mode is possible only if the address Increment mode is enabled. */

+

+  uint32_t PeriphBurst;          /*!< Specifies the Burst transfer configuration for the peripheral transfers.

+                                      It specifies the amount of data to be transferred in a single non interruptible

+                                      transaction.

+                                      This parameter can be a value of @ref DMA_Peripheral_burst

+                                      @note The burst mode is possible only if the address Increment mode is enabled. */

+}DMA_InitTypeDef;

+

+/**

+  * @brief  HAL DMA State structures definition

+  */

+typedef enum

+{

+  HAL_DMA_STATE_RESET             = 0x00U,  /*!< DMA not yet initialized or disabled */

+  HAL_DMA_STATE_READY             = 0x01U,  /*!< DMA initialized and ready for use   */

+  HAL_DMA_STATE_BUSY              = 0x02U,  /*!< DMA process is ongoing              */

+  HAL_DMA_STATE_ERROR             = 0x03U,  /*!< DMA error state                     */

+  HAL_DMA_STATE_ABORT             = 0x04U,  /*!< DMA Abort state                     */

+}HAL_DMA_StateTypeDef;

+

+/**

+  * @brief  HAL DMA Transfer complete level structure definition

+  */

+typedef enum

+{

+  HAL_DMA_FULL_TRANSFER      = 0x00U,    /*!< Full transfer     */

+  HAL_DMA_HALF_TRANSFER      = 0x01U,    /*!< Half Transfer     */

+}HAL_DMA_LevelCompleteTypeDef;

+

+/**

+  * @brief  HAL DMA Callbacks IDs structure definition

+  */

+typedef enum

+{

+  HAL_DMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer     */

+  HAL_DMA_XFER_HALFCPLT_CB_ID      = 0x01U,    /*!< Half Transfer     */

+  HAL_DMA_XFER_M1CPLT_CB_ID        = 0x02U,    /*!< M1 Full Transfer  */

+  HAL_DMA_XFER_M1HALFCPLT_CB_ID    = 0x03U,    /*!< M1 Half Transfer  */

+  HAL_DMA_XFER_ERROR_CB_ID         = 0x04U,    /*!< Error             */

+  HAL_DMA_XFER_ABORT_CB_ID         = 0x05U,    /*!< Abort             */

+  HAL_DMA_XFER_ALL_CB_ID           = 0x06U     /*!< All               */

+}HAL_DMA_CallbackIDTypeDef;

+

+/**

+  * @brief  DMA handle Structure definition

+  */

+typedef struct __DMA_HandleTypeDef

+{

+  void                            *Instance;                                                        /*!< Register base address                         */

+

+  DMA_InitTypeDef                 Init;                                                             /*!< DMA communication parameters                  */

+

+  HAL_LockTypeDef                 Lock;                                                             /*!< DMA locking object                            */

+

+  __IO HAL_DMA_StateTypeDef       State;                                                            /*!< DMA transfer state                            */

+

+  void                            *Parent;                                                          /*!< Parent object state                           */

+

+  void                            (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);         /*!< DMA transfer complete callback                */

+

+  void                            (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA Half transfer complete callback           */

+

+  void                            (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma);       /*!< DMA transfer complete Memory1 callback        */

+

+  void                            (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma);   /*!< DMA transfer Half complete Memory1 callback   */

+

+  void                            (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);        /*!< DMA transfer error callback                   */

+

+  void                            (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma);        /*!< DMA transfer Abort callback                   */

+

+ __IO uint32_t                    ErrorCode;                                                        /*!< DMA Error code                                */

+

+ uint32_t                         StreamBaseAddress;                                                /*!< DMA Stream Base Address                       */

+

+ uint32_t                         StreamIndex;                                                      /*!< DMA Stream Index                              */

+

+ DMAMUX_Channel_TypeDef           *DMAmuxChannel;                                                   /*!< DMAMUX Channel Base Address                   */

+

+ DMAMUX_ChannelStatus_TypeDef     *DMAmuxChannelStatus;                                             /*!< DMAMUX Channels Status Base Address           */

+

+ uint32_t                         DMAmuxChannelStatusMask;                                          /*!< DMAMUX Channel Status Mask                    */

+

+

+ DMAMUX_RequestGen_TypeDef        *DMAmuxRequestGen;                                                /*!< DMAMUX request generator Base Address         */

+

+ DMAMUX_RequestGenStatus_TypeDef  *DMAmuxRequestGenStatus;                                          /*!< DMAMUX request generator Status Address       */

+

+ uint32_t                         DMAmuxRequestGenStatusMask;                                       /*!< DMAMUX request generator Status mask          */

+

+}DMA_HandleTypeDef;

+

+/**

+  * @}

+  */

+

+

+/* Exported constants --------------------------------------------------------*/

+

+/** @defgroup DMA_Exported_Constants DMA Exported Constants

+  * @brief    DMA Exported constants

+  * @{

+  */

+

+/** @defgroup DMA_Error_Code DMA Error Code

+  * @brief    DMA Error Code

+  * @{

+  */

+#define HAL_DMA_ERROR_NONE            (0x00000000U)    /*!< No error                                */

+#define HAL_DMA_ERROR_TE              (0x00000001U)    /*!< Transfer error                          */

+#define HAL_DMA_ERROR_FE              (0x00000002U)    /*!< FIFO error                              */

+#define HAL_DMA_ERROR_DME             (0x00000004U)    /*!< Direct Mode error                       */

+#define HAL_DMA_ERROR_TIMEOUT         (0x00000020U)    /*!< Timeout error                           */

+#define HAL_DMA_ERROR_PARAM           (0x00000040U)    /*!< Parameter error                         */

+#define HAL_DMA_ERROR_NO_XFER         (0x00000080U)    /*!< Abort requested with no Xfer ongoing    */

+#define HAL_DMA_ERROR_NOT_SUPPORTED   (0x00000100U)    /*!< Not supported mode                      */

+#define HAL_DMA_ERROR_SYNC            (0x00000200U)    /*!< DMAMUX sync overrun  error              */

+#define HAL_DMA_ERROR_REQGEN          (0x00000400U)    /*!< DMAMUX request generator overrun  error */

+#define HAL_DMA_ERROR_BUSY            (0x00000800U)    /*!< DMA Busy                          error */

+

+/**

+  * @}

+  */

+

+/** @defgroup DMA_Request_selection DMA Request selection

+  * @brief    DMA Request selection

+  * @{

+  */

+/* DMAMUX1 requests */

+#define DMA_REQUEST_MEM2MEM          0U  /*!< memory to memory transfer   */

+

+#define DMA_REQUEST_GENERATOR0       1U  /*!< DMAMUX1 request generator 0 */

+#define DMA_REQUEST_GENERATOR1       2U  /*!< DMAMUX1 request generator 1 */

+#define DMA_REQUEST_GENERATOR2       3U  /*!< DMAMUX1 request generator 2 */

+#define DMA_REQUEST_GENERATOR3       4U  /*!< DMAMUX1 request generator 3 */

+#define DMA_REQUEST_GENERATOR4       5U  /*!< DMAMUX1 request generator 4 */

+#define DMA_REQUEST_GENERATOR5       6U  /*!< DMAMUX1 request generator 5 */

+#define DMA_REQUEST_GENERATOR6       7U  /*!< DMAMUX1 request generator 6 */

+#define DMA_REQUEST_GENERATOR7       8U  /*!< DMAMUX1 request generator 7 */

+

+#define DMA_REQUEST_ADC1             9U  /*!< DMAMUX1 ADC1 request */

+#define DMA_REQUEST_ADC2             10U /*!< DMAMUX1 ADC2 request */

+

+#define DMA_REQUEST_TIM1_CH1         11U  /*!< DMAMUX1 TIM1 CH1 request  */

+#define DMA_REQUEST_TIM1_CH2         12U  /*!< DMAMUX1 TIM1 CH2 request  */

+#define DMA_REQUEST_TIM1_CH3         13U  /*!< DMAMUX1 TIM1 CH3 request  */

+#define DMA_REQUEST_TIM1_CH4         14U  /*!< DMAMUX1 TIM1 CH4 request  */

+#define DMA_REQUEST_TIM1_UP          15U  /*!< DMAMUX1 TIM1 UP request   */

+#define DMA_REQUEST_TIM1_TRIG        16U  /*!< DMAMUX1 TIM1 TRIG request */

+#define DMA_REQUEST_TIM1_COM         17U  /*!< DMAMUX1 TIM1 COM request  */

+

+#define DMA_REQUEST_TIM2_CH1         18U  /*!< DMAMUX1 TIM2 CH1 request  */

+#define DMA_REQUEST_TIM2_CH2         19U  /*!< DMAMUX1 TIM2 CH2 request  */

+#define DMA_REQUEST_TIM2_CH3         20U  /*!< DMAMUX1 TIM2 CH3 request  */

+#define DMA_REQUEST_TIM2_CH4         21U  /*!< DMAMUX1 TIM2 CH4 request  */

+#define DMA_REQUEST_TIM2_UP          22U  /*!< DMAMUX1 TIM2 UP request   */

+

+#define DMA_REQUEST_TIM3_CH1         23U  /*!< DMAMUX1 TIM3 CH1 request  */

+#define DMA_REQUEST_TIM3_CH2         24U  /*!< DMAMUX1 TIM3 CH2 request  */

+#define DMA_REQUEST_TIM3_CH3         25U  /*!< DMAMUX1 TIM3 CH3 request  */

+#define DMA_REQUEST_TIM3_CH4         26U  /*!< DMAMUX1 TIM3 CH4 request  */

+#define DMA_REQUEST_TIM3_UP          27U  /*!< DMAMUX1 TIM3 UP request   */

+#define DMA_REQUEST_TIM3_TRIG        28U  /*!< DMAMUX1 TIM3 TRIG request */

+

+#define DMA_REQUEST_TIM4_CH1         29U  /*!< DMAMUX1 TIM4 CH1 request  */

+#define DMA_REQUEST_TIM4_CH2         30U  /*!< DMAMUX1 TIM4 CH2 request  */

+#define DMA_REQUEST_TIM4_CH3         31U  /*!< DMAMUX1 TIM4 CH3 request  */

+#define DMA_REQUEST_TIM4_UP          32U  /*!< DMAMUX1 TIM4 UP request   */

+

+#define DMA_REQUEST_I2C1_RX          33U  /*!< DMAMUX1 I2C1 RX request   */

+#define DMA_REQUEST_I2C1_TX          34U  /*!< DMAMUX1 I2C1 TX request   */

+#define DMA_REQUEST_I2C2_RX          35U  /*!< DMAMUX1 I2C2 RX request   */

+#define DMA_REQUEST_I2C2_TX          36U  /*!< DMAMUX1 I2C2 TX request   */

+

+#define DMA_REQUEST_SPI1_RX          37U  /*!< DMAMUX1 SPI1 RX request   */

+#define DMA_REQUEST_SPI1_TX          38U  /*!< DMAMUX1 SPI1 TX request   */

+#define DMA_REQUEST_SPI2_RX          39U  /*!< DMAMUX1 SPI2 RX request   */

+#define DMA_REQUEST_SPI2_TX          40U  /*!< DMAMUX1 SPI2 TX request   */

+

+#define DMA_REQUEST_USART1_RX        41U  /*!< DMAMUX1 USART1 RX request */

+#define DMA_REQUEST_USART1_TX        42U  /*!< DMAMUX1 USART1 TX request */

+#define DMA_REQUEST_USART2_RX        43U  /*!< DMAMUX1 USART2 RX request */

+#define DMA_REQUEST_USART2_TX        44U  /*!< DMAMUX1 USART2 TX request */

+#define DMA_REQUEST_USART3_RX        45U  /*!< DMAMUX1 USART3 RX request */

+#define DMA_REQUEST_USART3_TX        46U  /*!< DMAMUX1 USART3 TX request */

+

+#define DMA_REQUEST_TIM8_CH1         47U  /*!< DMAMUX1 TIM8 CH1 request  */

+#define DMA_REQUEST_TIM8_CH2         48U  /*!< DMAMUX1 TIM8 CH2 request  */

+#define DMA_REQUEST_TIM8_CH3         49U  /*!< DMAMUX1 TIM8 CH3 request  */

+#define DMA_REQUEST_TIM8_CH4         50U  /*!< DMAMUX1 TIM8 CH4 request  */

+#define DMA_REQUEST_TIM8_UP          51U  /*!< DMAMUX1 TIM8 UP request   */

+#define DMA_REQUEST_TIM8_TRIG        52U  /*!< DMAMUX1 TIM8 TRIG request */

+#define DMA_REQUEST_TIM8_COM         53U  /*!< DMAMUX1 TIM8 COM request  */

+

+#define DMA_REQUEST_TIM5_CH1         55U  /*!< DMAMUX1 TIM5 CH1 request  */

+#define DMA_REQUEST_TIM5_CH2         56U  /*!< DMAMUX1 TIM5 CH2 request  */

+#define DMA_REQUEST_TIM5_CH3         57U  /*!< DMAMUX1 TIM5 CH3 request  */

+#define DMA_REQUEST_TIM5_CH4         58U  /*!< DMAMUX1 TIM5 CH4 request  */

+#define DMA_REQUEST_TIM5_UP          59U  /*!< DMAMUX1 TIM5 UP request   */

+#define DMA_REQUEST_TIM5_TRIG        60U  /*!< DMAMUX1 TIM5 TRIG request */

+

+#define DMA_REQUEST_SPI3_RX          61U  /*!< DMAMUX1 SPI3 RX request   */

+#define DMA_REQUEST_SPI3_TX          62U  /*!< DMAMUX1 SPI3 TX request   */

+

+#define DMA_REQUEST_UART4_RX         63U  /*!< DMAMUX1 UART4 RX request */

+#define DMA_REQUEST_UART4_TX         64U  /*!< DMAMUX1 UART4 TX request */

+#define DMA_REQUEST_UART5_RX         65U  /*!< DMAMUX1 UART5 RX request */

+#define DMA_REQUEST_UART5_TX         66U  /*!< DMAMUX1 UART5 TX request */

+

+#define DMA_REQUEST_DAC1_CH1         67U  /*!< DMAMUX1 DAC1 Channel 1 request */

+#define DMA_REQUEST_DAC1_CH2         68U  /*!< DMAMUX1 DAC1 Channel 2 request */

+

+#define DMA_REQUEST_TIM6_UP          69U  /*!< DMAMUX1 TIM6 UP request   */

+#define DMA_REQUEST_TIM7_UP          70U  /*!< DMAMUX1 TIM7 UP request   */

+

+#define DMA_REQUEST_USART6_RX        71U  /*!< DMAMUX1 USART6 RX request */

+#define DMA_REQUEST_USART6_TX        72U  /*!< DMAMUX1 USART6 TX request */

+

+#define DMA_REQUEST_I2C3_RX          73U  /*!< DMAMUX1 I2C3 RX request   */

+#define DMA_REQUEST_I2C3_TX          74U  /*!< DMAMUX1 I2C3 TX request   */

+

+#if defined (PSSI)

+#define DMA_REQUEST_DCMI_PSSI        75U  /*!< DMAMUX1 DCMI/PSSI request    */

+#define DMA_REQUEST_DCMI             DMA_REQUEST_DCMI_PSSI /* Legacy define */

+#else

+#define DMA_REQUEST_DCMI             75U  /*!< DMAMUX1 DCMI request         */

+#endif /* PSSI */

+

+#define DMA_REQUEST_CRYP_IN          76U  /*!< DMAMUX1 CRYP IN request   */

+#define DMA_REQUEST_CRYP_OUT         77U  /*!< DMAMUX1 CRYP OUT request  */

+

+#define DMA_REQUEST_HASH_IN          78U  /*!< DMAMUX1 HASH IN request   */

+

+#define DMA_REQUEST_UART7_RX         79U  /*!< DMAMUX1 UART7 RX request  */

+#define DMA_REQUEST_UART7_TX         80U  /*!< DMAMUX1 UART7 TX request  */

+#define DMA_REQUEST_UART8_RX         81U  /*!< DMAMUX1 UART8 RX request  */

+#define DMA_REQUEST_UART8_TX         82U  /*!< DMAMUX1 UART8 TX request  */

+

+#define DMA_REQUEST_SPI4_RX          83U  /*!< DMAMUX1 SPI4 RX request   */

+#define DMA_REQUEST_SPI4_TX          84U  /*!< DMAMUX1 SPI4 TX request   */

+#define DMA_REQUEST_SPI5_RX          85U  /*!< DMAMUX1 SPI5 RX request   */

+#define DMA_REQUEST_SPI5_TX          86U  /*!< DMAMUX1 SPI5 TX request   */

+

+#define DMA_REQUEST_SAI1_A           87U  /*!< DMAMUX1 SAI1 A request    */

+#define DMA_REQUEST_SAI1_B           88U  /*!< DMAMUX1 SAI1 B request    */

+#define DMA_REQUEST_SAI2_A           89U  /*!< DMAMUX1 SAI2 A request    */

+#define DMA_REQUEST_SAI2_B           90U  /*!< DMAMUX1 SAI2 B request    */

+

+#define DMA_REQUEST_SWPMI_RX         91U  /*!< DMAMUX1 SWPMI RX request  */

+#define DMA_REQUEST_SWPMI_TX         92U  /*!< DMAMUX1 SWPMI TX request  */

+

+#define DMA_REQUEST_SPDIF_RX_DT      93U  /*!< DMAMUX1 SPDIF RXDT request*/

+#define DMA_REQUEST_SPDIF_RX_CS      94U  /*!< DMAMUX1 SPDIF RXCS request*/

+

+#if defined(HRTIM1)

+#define DMA_REQUEST_HRTIM_MASTER     95U  /*!< DMAMUX1 HRTIM1 Master request 1 */

+#define DMA_REQUEST_HRTIM_TIMER_A    96U  /*!< DMAMUX1 HRTIM1 TimerA request 2 */

+#define DMA_REQUEST_HRTIM_TIMER_B    97U  /*!< DMAMUX1 HRTIM1 TimerB request 3 */

+#define DMA_REQUEST_HRTIM_TIMER_C    98U  /*!< DMAMUX1 HRTIM1 TimerC request 4 */

+#define DMA_REQUEST_HRTIM_TIMER_D    99U  /*!< DMAMUX1 HRTIM1 TimerD request 5 */

+#define DMA_REQUEST_HRTIM_TIMER_E   100U  /*!< DMAMUX1 HRTIM1 TimerE request 6 */

+#endif /* HRTIM1 */

+

+#define DMA_REQUEST_DFSDM1_FLT0     101U  /*!< DMAMUX1 DFSDM Filter0 request */

+#define DMA_REQUEST_DFSDM1_FLT1     102U  /*!< DMAMUX1 DFSDM Filter1 request */

+#define DMA_REQUEST_DFSDM1_FLT2     103U  /*!< DMAMUX1 DFSDM Filter2 request */

+#define DMA_REQUEST_DFSDM1_FLT3     104U  /*!< DMAMUX1 DFSDM Filter3 request */

+

+#define DMA_REQUEST_TIM15_CH1       105U  /*!< DMAMUX1 TIM15 CH1 request  */

+#define DMA_REQUEST_TIM15_UP        106U  /*!< DMAMUX1 TIM15 UP request   */

+#define DMA_REQUEST_TIM15_TRIG      107U  /*!< DMAMUX1 TIM15 TRIG request */

+#define DMA_REQUEST_TIM15_COM       108U  /*!< DMAMUX1 TIM15 COM request  */

+

+#define DMA_REQUEST_TIM16_CH1       109U  /*!< DMAMUX1 TIM16 CH1 request  */

+#define DMA_REQUEST_TIM16_UP        110U  /*!< DMAMUX1 TIM16 UP request   */

+

+#define DMA_REQUEST_TIM17_CH1       111U  /*!< DMAMUX1 TIM17 CH1 request  */

+#define DMA_REQUEST_TIM17_UP        112U  /*!< DMAMUX1 TIM17 UP request   */

+

+#if defined(SAI3)

+#define DMA_REQUEST_SAI3_A          113U  /*!< DMAMUX1 SAI3 A request  */

+#define DMA_REQUEST_SAI3_B          114U  /*!< DMAMUX1 SAI3 B request  */

+#endif /* SAI3 */

+

+#if defined(ADC3)

+#define DMA_REQUEST_ADC3            115U  /*!< DMAMUX1 ADC3 request  */

+#endif /* ADC3 */

+

+#if defined(UART9)

+#define DMA_REQUEST_UART9_RX        116U  /*!< DMAMUX1 UART9 request  */

+#define DMA_REQUEST_UART9_TX        117U  /*!< DMAMUX1 UART9 request  */

+#endif /* UART9 */

+

+#if defined(USART10)

+#define DMA_REQUEST_USART10_RX      118U  /*!< DMAMUX1 USART10 request  */

+#define DMA_REQUEST_USART10_TX      119U  /*!< DMAMUX1 USART10 request  */

+#endif /* USART10 */

+

+

+/* DMAMUX2 requests */

+#define BDMA_REQUEST_MEM2MEM          0U  /*!< memory to memory transfer   */

+#define BDMA_REQUEST_GENERATOR0       1U  /*!< DMAMUX2 request generator 0 */

+#define BDMA_REQUEST_GENERATOR1       2U  /*!< DMAMUX2 request generator 1 */

+#define BDMA_REQUEST_GENERATOR2       3U  /*!< DMAMUX2 request generator 2 */

+#define BDMA_REQUEST_GENERATOR3       4U  /*!< DMAMUX2 request generator 3 */

+#define BDMA_REQUEST_GENERATOR4       5U  /*!< DMAMUX2 request generator 4 */

+#define BDMA_REQUEST_GENERATOR5       6U  /*!< DMAMUX2 request generator 5 */

+#define BDMA_REQUEST_GENERATOR6       7U  /*!< DMAMUX2 request generator 6 */

+#define BDMA_REQUEST_GENERATOR7       8U  /*!< DMAMUX2 request generator 7 */

+#define BDMA_REQUEST_LPUART1_RX       9U  /*!< DMAMUX2 LP_UART1_RX request */

+#define BDMA_REQUEST_LPUART1_TX      10U  /*!< DMAMUX2 LP_UART1_TX request */

+#define BDMA_REQUEST_SPI6_RX         11U  /*!< DMAMUX2 SPI6 RX request     */

+#define BDMA_REQUEST_SPI6_TX         12U  /*!< DMAMUX2 SPI6 TX request     */

+#define BDMA_REQUEST_I2C4_RX         13U  /*!< DMAMUX2 I2C4 RX request     */

+#define BDMA_REQUEST_I2C4_TX         14U  /*!< DMAMUX2 I2C4 TX request     */

+#if defined(SAI4)

+#define BDMA_REQUEST_SAI4_A          15U  /*!< DMAMUX2 SAI4 A request      */

+#define BDMA_REQUEST_SAI4_B          16U  /*!< DMAMUX2 SAI4 B request      */

+#endif /* SAI4 */

+#if defined(ADC3)

+#define BDMA_REQUEST_ADC3            17U  /*!< DMAMUX2 ADC3 request        */

+#endif /* ADC3 */

+#if defined(DAC2)

+#define BDMA_REQUEST_DAC2_CH1        17U  /*!< DMAMUX2 DAC2 CH1 request    */

+#endif /* DAC2 */

+#if defined(DFSDM2_Channel0)

+#define BDMA_REQUEST_DFSDM2_FLT0     18U  /*!< DMAMUX2 DFSDM2 request      */

+#endif /* DFSDM1_Channel0 */

+

+/**

+  * @}

+  */

+

+/** @defgroup DMA_Data_transfer_direction DMA Data transfer direction

+  * @brief    DMA data transfer direction

+  * @{

+  */

+#define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000U)      /*!< Peripheral to memory direction */

+#define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_SxCR_DIR_0)  /*!< Memory to peripheral direction */

+#define DMA_MEMORY_TO_MEMORY         ((uint32_t)DMA_SxCR_DIR_1)  /*!< Memory to memory direction     */

+/**

+  * @}

+  */

+

+/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode

+  * @brief    DMA peripheral incremented mode

+  * @{

+  */

+#define DMA_PINC_ENABLE        ((uint32_t)DMA_SxCR_PINC)  /*!< Peripheral increment mode enable  */

+#define DMA_PINC_DISABLE       ((uint32_t)0x00000000U)     /*!< Peripheral increment mode disable */

+/**

+  * @}

+  */

+

+/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode

+  * @brief    DMA memory incremented mode

+  * @{

+  */

+#define DMA_MINC_ENABLE         ((uint32_t)DMA_SxCR_MINC)  /*!< Memory increment mode enable  */

+#define DMA_MINC_DISABLE        ((uint32_t)0x00000000U)     /*!< Memory increment mode disable */

+/**

+  * @}

+  */

+

+/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size

+  * @brief    DMA peripheral data size

+  * @{

+  */

+#define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000U)       /*!< Peripheral data alignment: Byte      */

+#define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_PSIZE_0)  /*!< Peripheral data alignment: HalfWord  */

+#define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_SxCR_PSIZE_1)  /*!< Peripheral data alignment: Word      */

+/**

+  * @}

+  */

+

+/** @defgroup DMA_Memory_data_size DMA Memory data size

+  * @brief    DMA memory data size

+  * @{

+  */

+#define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000U)       /*!< Memory data alignment: Byte     */

+#define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_SxCR_MSIZE_0)  /*!< Memory data alignment: HalfWord */

+#define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_SxCR_MSIZE_1)  /*!< Memory data alignment: Word     */

+/**

+  * @}

+  */

+

+/** @defgroup DMA_mode DMA mode

+  * @brief    DMA mode

+  * @{

+  */

+#define DMA_NORMAL              ((uint32_t)0x00000000U)                  /*!< Normal mode                                    */

+#define DMA_CIRCULAR            ((uint32_t)DMA_SxCR_CIRC)                /*!< Circular mode                                  */

+#define DMA_PFCTRL              ((uint32_t)DMA_SxCR_PFCTRL)              /*!< Peripheral flow control mode                   */

+#define DMA_DOUBLE_BUFFER_M0    ((uint32_t)DMA_SxCR_DBM)                 /*!< Double buffer mode with first target memory M0 */

+#define DMA_DOUBLE_BUFFER_M1    ((uint32_t)(DMA_SxCR_DBM | DMA_SxCR_CT)) /*!< Double buffer mode with first target memory M1 */

+/**

+  * @}

+  */

+

+/** @defgroup DMA_Priority_level DMA Priority level

+  * @brief    DMA priority levels

+  * @{

+  */

+#define DMA_PRIORITY_LOW             ((uint32_t)0x00000000U)    /*!< Priority level: Low       */

+#define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_SxCR_PL_0)  /*!< Priority level: Medium    */

+#define DMA_PRIORITY_HIGH            ((uint32_t)DMA_SxCR_PL_1)  /*!< Priority level: High      */

+#define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_SxCR_PL)    /*!< Priority level: Very High */

+/**

+  * @}

+  */

+

+/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode

+  * @brief    DMA FIFO direct mode

+  * @{

+  */

+#define DMA_FIFOMODE_DISABLE        ((uint32_t)0x00000000U)       /*!< FIFO mode disable */

+#define DMA_FIFOMODE_ENABLE         ((uint32_t)DMA_SxFCR_DMDIS)  /*!< FIFO mode enable  */

+/**

+  * @}

+  */

+

+/** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level

+  * @brief    DMA FIFO level

+  * @{

+  */

+#define DMA_FIFO_THRESHOLD_1QUARTERFULL       ((uint32_t)0x00000000U)       /*!< FIFO threshold 1 quart full configuration  */

+#define DMA_FIFO_THRESHOLD_HALFFULL           ((uint32_t)DMA_SxFCR_FTH_0)  /*!< FIFO threshold half full configuration     */

+#define DMA_FIFO_THRESHOLD_3QUARTERSFULL      ((uint32_t)DMA_SxFCR_FTH_1)  /*!< FIFO threshold 3 quarts full configuration */

+#define DMA_FIFO_THRESHOLD_FULL               ((uint32_t)DMA_SxFCR_FTH)    /*!< FIFO threshold full configuration          */

+/**

+  * @}

+  */

+

+/** @defgroup DMA_Memory_burst DMA Memory burst

+  * @brief    DMA memory burst

+  * @{

+  */

+#define DMA_MBURST_SINGLE       ((uint32_t)0x00000000U)

+#define DMA_MBURST_INC4         ((uint32_t)DMA_SxCR_MBURST_0)

+#define DMA_MBURST_INC8         ((uint32_t)DMA_SxCR_MBURST_1)

+#define DMA_MBURST_INC16        ((uint32_t)DMA_SxCR_MBURST)

+/**

+  * @}

+  */

+

+/** @defgroup DMA_Peripheral_burst DMA Peripheral burst

+  * @brief    DMA peripheral burst

+  * @{

+  */

+#define DMA_PBURST_SINGLE       ((uint32_t)0x00000000U)

+#define DMA_PBURST_INC4         ((uint32_t)DMA_SxCR_PBURST_0)

+#define DMA_PBURST_INC8         ((uint32_t)DMA_SxCR_PBURST_1)

+#define DMA_PBURST_INC16        ((uint32_t)DMA_SxCR_PBURST)

+/**

+  * @}

+  */

+

+/** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions

+  * @brief    DMA interrupts definition

+  * @{

+  */

+#define DMA_IT_TC                         ((uint32_t)DMA_SxCR_TCIE)

+#define DMA_IT_HT                         ((uint32_t)DMA_SxCR_HTIE)

+#define DMA_IT_TE                         ((uint32_t)DMA_SxCR_TEIE)

+#define DMA_IT_DME                        ((uint32_t)DMA_SxCR_DMEIE)

+#define DMA_IT_FE                         ((uint32_t)0x00000080U)

+/**

+  * @}

+  */

+

+/** @defgroup DMA_flag_definitions DMA flag definitions

+  * @brief    DMA flag definitions

+  * @{

+  */

+#define DMA_FLAG_FEIF0_4                    ((uint32_t)0x00000001U)

+#define DMA_FLAG_DMEIF0_4                   ((uint32_t)0x00000004U)

+#define DMA_FLAG_TEIF0_4                    ((uint32_t)0x00000008U)

+#define DMA_FLAG_HTIF0_4                    ((uint32_t)0x00000010U)

+#define DMA_FLAG_TCIF0_4                    ((uint32_t)0x00000020U)

+#define DMA_FLAG_FEIF1_5                    ((uint32_t)0x00000040U)

+#define DMA_FLAG_DMEIF1_5                   ((uint32_t)0x00000100U)

+#define DMA_FLAG_TEIF1_5                    ((uint32_t)0x00000200U)

+#define DMA_FLAG_HTIF1_5                    ((uint32_t)0x00000400U)

+#define DMA_FLAG_TCIF1_5                    ((uint32_t)0x00000800U)

+#define DMA_FLAG_FEIF2_6                    ((uint32_t)0x00010000U)

+#define DMA_FLAG_DMEIF2_6                   ((uint32_t)0x00040000U)

+#define DMA_FLAG_TEIF2_6                    ((uint32_t)0x00080000U)

+#define DMA_FLAG_HTIF2_6                    ((uint32_t)0x00100000U)

+#define DMA_FLAG_TCIF2_6                    ((uint32_t)0x00200000U)

+#define DMA_FLAG_FEIF3_7                    ((uint32_t)0x00400000U)

+#define DMA_FLAG_DMEIF3_7                   ((uint32_t)0x01000000U)

+#define DMA_FLAG_TEIF3_7                    ((uint32_t)0x02000000U)

+#define DMA_FLAG_HTIF3_7                    ((uint32_t)0x04000000U)

+#define DMA_FLAG_TCIF3_7                    ((uint32_t)0x08000000U)

+/**

+  * @}

+  */

+

+/** @defgroup BDMA_flag_definitions BDMA flag definitions

+  * @brief    BDMA flag definitions

+  * @{

+  */

+#define BDMA_FLAG_GL0                      ((uint32_t)0x00000001)

+#define BDMA_FLAG_TC0                      ((uint32_t)0x00000002)

+#define BDMA_FLAG_HT0                      ((uint32_t)0x00000004)

+#define BDMA_FLAG_TE0                      ((uint32_t)0x00000008)

+#define BDMA_FLAG_GL1                      ((uint32_t)0x00000010)

+#define BDMA_FLAG_TC1                      ((uint32_t)0x00000020)

+#define BDMA_FLAG_HT1                      ((uint32_t)0x00000040)

+#define BDMA_FLAG_TE1                      ((uint32_t)0x00000080)

+#define BDMA_FLAG_GL2                      ((uint32_t)0x00000100)

+#define BDMA_FLAG_TC2                      ((uint32_t)0x00000200)

+#define BDMA_FLAG_HT2                      ((uint32_t)0x00000400)

+#define BDMA_FLAG_TE2                      ((uint32_t)0x00000800)

+#define BDMA_FLAG_GL3                      ((uint32_t)0x00001000)

+#define BDMA_FLAG_TC3                      ((uint32_t)0x00002000)

+#define BDMA_FLAG_HT3                      ((uint32_t)0x00004000)

+#define BDMA_FLAG_TE3                      ((uint32_t)0x00008000)

+#define BDMA_FLAG_GL4                      ((uint32_t)0x00010000)

+#define BDMA_FLAG_TC4                      ((uint32_t)0x00020000)

+#define BDMA_FLAG_HT4                      ((uint32_t)0x00040000)

+#define BDMA_FLAG_TE4                      ((uint32_t)0x00080000)

+#define BDMA_FLAG_GL5                      ((uint32_t)0x00100000)

+#define BDMA_FLAG_TC5                      ((uint32_t)0x00200000)

+#define BDMA_FLAG_HT5                      ((uint32_t)0x00400000)

+#define BDMA_FLAG_TE5                      ((uint32_t)0x00800000)

+#define BDMA_FLAG_GL6                      ((uint32_t)0x01000000)

+#define BDMA_FLAG_TC6                      ((uint32_t)0x02000000)

+#define BDMA_FLAG_HT6                      ((uint32_t)0x04000000)

+#define BDMA_FLAG_TE6                      ((uint32_t)0x08000000)

+#define BDMA_FLAG_GL7                      ((uint32_t)0x10000000)

+#define BDMA_FLAG_TC7                      ((uint32_t)0x20000000)

+#define BDMA_FLAG_HT7                      ((uint32_t)0x40000000)

+#define BDMA_FLAG_TE7                      ((uint32_t)0x80000000)

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup DMA_Exported_Macros DMA Exported Macros

+  * @{

+  */

+

+/** @brief Reset DMA handle state

+  * @param  __HANDLE__: specifies the DMA handle.

+  * @retval None

+  */

+#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)

+

+/**

+  * @brief  Return the current DMA Stream FIFO filled level.

+  * @param  __HANDLE__: DMA handle

+  * @retval The FIFO filling state.

+  *           - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full

+  *                                              and not empty.

+  *           - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.

+  *           - DMA_FIFOStatus_HalfFull: if more than 1 half-full.

+  *           - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.

+  *           - DMA_FIFOStatus_Empty: when FIFO is empty

+  *           - DMA_FIFOStatus_Full: when FIFO is full

+  */

+#define __HAL_DMA_GET_FS(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (DMA_SxFCR_FS)) : 0)

+

+/**

+  * @brief  Enable the specified DMA Stream.

+  * @param  __HANDLE__: DMA handle

+  * @retval None

+  */

+#define __HAL_DMA_ENABLE(__HANDLE__) \

+((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |=  DMA_SxCR_EN) : \

+(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |=  BDMA_CCR_EN))

+

+/**

+  * @brief  Disable the specified DMA Stream.

+  * @param  __HANDLE__: DMA handle

+  * @retval None

+  */

+#define __HAL_DMA_DISABLE(__HANDLE__) \

+((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &=  ~DMA_SxCR_EN) : \

+(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &=  ~BDMA_CCR_EN))

+

+/* Interrupt & Flag management */

+

+/**

+  * @brief  Return the current DMA Stream transfer complete flag.

+  * @param  __HANDLE__: DMA handle

+  * @retval The specified transfer complete flag index.

+  */

+#if defined(BDMA1)

+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \

+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TC0  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TC0  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TC1  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TC1  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TC2  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TC2  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TC3  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TC3  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TC4  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TC4  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TC5  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TC5  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TC6  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TC6  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TC7  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TC7  :\

+ (uint32_t)0x00000000)

+#else

+#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \

+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TCIF3_7 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TCIF3_7 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TCIF3_7 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TCIF3_7 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TC0   :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TC1   :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TC2   :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TC3   :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TC4   :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TC5   :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TC6   :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TC7   :\

+ (uint32_t)0x00000000)

+#endif /* BDMA1 */

+

+/**

+  * @brief  Return the current DMA Stream half transfer complete flag.

+  * @param  __HANDLE__: DMA handle

+  * @retval The specified half transfer complete flag index.

+  */

+#if defined(BDMA1)

+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\

+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_HT0  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_HT0  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_HT1  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_HT1  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_HT2  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_HT2  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_HT3  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_HT3  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_HT4  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_HT4  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_HT5  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_HT5  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_HT6  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_HT6  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_HT7  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_HT7  :\

+ (uint32_t)0x00000000)

+#else

+#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\

+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_HTIF3_7 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_HTIF3_7 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_HTIF3_7 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_HTIF3_7 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_HT0   :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_HT1   :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_HT2   :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_HT3   :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_HT4   :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_HT5   :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_HT6   :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_HT7   :\

+ (uint32_t)0x00000000)

+#endif /* BDMA1 */

+

+/**

+  * @brief  Return the current DMA Stream transfer error flag.

+  * @param  __HANDLE__: DMA handle

+  * @retval The specified transfer error flag index.

+  */

+#if defined(BDMA1)

+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\

+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_FLAG_TE0  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_FLAG_TE0  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_FLAG_TE1  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_FLAG_TE1  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_FLAG_TE2  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_FLAG_TE2  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_FLAG_TE3  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_FLAG_TE3  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_FLAG_TE4  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_FLAG_TE4  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_FLAG_TE5  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_FLAG_TE5  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_FLAG_TE6  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_FLAG_TE6  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_FLAG_TE7  :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_FLAG_TE7  :\

+ (uint32_t)0x00000000)

+#else

+#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\

+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_TEIF3_7 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_TEIF3_7 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_TEIF3_7 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_TEIF3_7 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_FLAG_TE0   :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_FLAG_TE1   :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_FLAG_TE2   :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_FLAG_TE3   :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_FLAG_TE4   :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_FLAG_TE5   :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_FLAG_TE6   :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_FLAG_TE7   :\

+ (uint32_t)0x00000000)

+#endif /* BDMA1 */

+

+/**

+  * @brief  Return the current DMA Stream FIFO error flag.

+  * @param  __HANDLE__: DMA handle

+  * @retval The specified FIFO error flag index.

+  */

+#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\

+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_FEIF3_7 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_FEIF3_7 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_FEIF3_7 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_FEIF3_7 :\

+  (uint32_t)0x00000000)

+

+/**

+  * @brief  Return the current DMA Stream direct mode error flag.

+  * @param  __HANDLE__: DMA handle

+  * @retval The specified direct mode error flag index.

+  */

+#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\

+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream3))? DMA_FLAG_DMEIF3_7 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream3))? DMA_FLAG_DMEIF3_7 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream7))? DMA_FLAG_DMEIF3_7 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream7))? DMA_FLAG_DMEIF3_7 :\

+  (uint32_t)0x00000000)

+

+/**

+  * @brief  Returns the current BDMA Channel Global interrupt flag.

+  * @param  __HANDLE__: DMA handle

+  * @retval The specified transfer error flag index.

+  */

+#if defined(BDMA1)

+#define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\

+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel0))? BDMA_ISR_GIF0 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel0))? BDMA_ISR_GIF0 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel1))? BDMA_ISR_GIF1 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel1))? BDMA_ISR_GIF1 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel2))? BDMA_ISR_GIF2 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel2))? BDMA_ISR_GIF2 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel3))? BDMA_ISR_GIF3 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel3))? BDMA_ISR_GIF3 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel4))? BDMA_ISR_GIF4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel4))? BDMA_ISR_GIF4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel5))? BDMA_ISR_GIF5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel5))? BDMA_ISR_GIF5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel6))? BDMA_ISR_GIF6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel6))? BDMA_ISR_GIF6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA1_Channel7))? BDMA_ISR_GIF7 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA2_Channel7))? BDMA_ISR_GIF7 :\

+ (uint32_t)0x00000000)

+#else

+#define __HAL_BDMA_GET_GI_FLAG_INDEX(__HANDLE__)\

+(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel0))? BDMA_ISR_GIF0 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel1))? BDMA_ISR_GIF1 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel2))? BDMA_ISR_GIF2 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel3))? BDMA_ISR_GIF3 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel4))? BDMA_ISR_GIF4 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel5))? BDMA_ISR_GIF5 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel6))? BDMA_ISR_GIF6 :\

+ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)BDMA_Channel7))? BDMA_ISR_GIF7 :\

+  (uint32_t)0x00000000)

+#endif /* BDMA1 */

+

+/**

+  * @brief  Get the DMA Stream pending flags.

+  * @param  __HANDLE__: DMA handle

+  * @param  __FLAG__: Get the specified flag.

+  *          This parameter can be any combination of the following values:

+  *            @arg DMA_FLAG_TCIFx: Transfer complete flag.

+  *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.

+  *            @arg DMA_FLAG_TEIFx: Transfer error flag.

+  *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.

+  *            @arg DMA_FLAG_FEIFx: FIFO error flag.

+  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.

+  * @retval The state of FLAG (SET or RESET).

+  */

+#if defined(BDMA1)

+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\

+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)?  (BDMA2->ISR & (__FLAG__)) :\

+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7  )?  (BDMA1->ISR & (__FLAG__)) :\

+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3  )?  (DMA2->HISR & (__FLAG__)) :\

+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7  )?  (DMA2->LISR & (__FLAG__)) :\

+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3  )?  (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))

+#else

+#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\

+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->ISR & (__FLAG__))  :\

+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\

+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\

+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))

+#endif /* BDMA1 */

+

+/**

+  * @brief  Clear the DMA Stream pending flags.

+  * @param  __HANDLE__: DMA handle

+  * @param  __FLAG__: specifies the flag to clear.

+  *          This parameter can be any combination of the following values:

+  *            @arg DMA_FLAG_TCIFx: Transfer complete flag.

+  *            @arg DMA_FLAG_HTIFx: Half transfer complete flag.

+  *            @arg DMA_FLAG_TEIFx: Transfer error flag.

+  *            @arg DMA_FLAG_DMEIFx: Direct mode error flag.

+  *            @arg DMA_FLAG_FEIFx: FIFO error flag.

+  *         Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.

+  * @retval None

+  */

+#if defined(BDMA1)

+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \

+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)BDMA1_Channel7)? (BDMA2->IFCR = (__FLAG__)) :\

+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)?  (BDMA1->IFCR = (__FLAG__)) :\

+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)?  (DMA2->HIFCR = (__FLAG__)) :\

+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)?  (DMA2->LIFCR = (__FLAG__)) :\

+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)?  (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))

+#else

+#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \

+(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream7)? (BDMA->IFCR = (__FLAG__))  :\

+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\

+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\

+ ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))

+#endif /* BDMA1 */

+

+#define DMA_TO_BDMA_IT(__DMA_IT__) \

+((((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE |BDMA_CCR_TEIE) :\

+ (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_HT)) == (DMA_IT_TC | DMA_IT_HT)) ? (BDMA_CCR_TCIE | BDMA_CCR_HTIE) :\

+ (((__DMA_IT__) & (DMA_IT_HT | DMA_IT_TE)) == (DMA_IT_HT | DMA_IT_TE)) ? (BDMA_CCR_HTIE |BDMA_CCR_TEIE)  :\

+ (((__DMA_IT__) & (DMA_IT_TC | DMA_IT_TE)) == (DMA_IT_TC | DMA_IT_TE)) ? (BDMA_CCR_TCIE |BDMA_CCR_TEIE)  :\

+ ((__DMA_IT__) == DMA_IT_TC) ? BDMA_CCR_TCIE :\

+ ((__DMA_IT__) == DMA_IT_HT) ? BDMA_CCR_HTIE :\

+ ((__DMA_IT__) == DMA_IT_TE) ? BDMA_CCR_TEIE :\

+ (uint32_t)0x00000000)

+

+

+#define __HAL_BDMA_CHANNEL_ENABLE_IT(__HANDLE__, __INTERRUPT__) \

+(((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR |= (DMA_TO_BDMA_IT(__INTERRUPT__)))

+

+#define __HAL_DMA_STREAM_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((__INTERRUPT__) != DMA_IT_FE)? \

+(((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR |= (__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR |= (__INTERRUPT__)))

+

+/**

+  * @brief  Enable the specified DMA Stream interrupts.

+  * @param  __HANDLE__: DMA handle

+  * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.

+  *        This parameter can be one of the following values:

+  *           @arg DMA_IT_TC: Transfer complete interrupt mask.

+  *           @arg DMA_IT_HT: Half transfer complete interrupt mask.

+  *           @arg DMA_IT_TE: Transfer error interrupt mask.

+  *           @arg DMA_IT_FE: FIFO error interrupt mask.

+  *           @arg DMA_IT_DME: Direct mode error interrupt.

+  * @retval None

+  */

+#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\

+                                                        (__HAL_DMA_STREAM_ENABLE_IT((__HANDLE__), (__INTERRUPT__))) :\

+                                                        (__HAL_BDMA_CHANNEL_ENABLE_IT((__HANDLE__), (__INTERRUPT__))))

+

+

+#define __HAL_BDMA_CHANNEL_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR &= ~(DMA_TO_BDMA_IT(__INTERRUPT__)))

+

+#define __HAL_DMA_STREAM_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \

+(((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR &= ~(__INTERRUPT__)) : (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR &= ~(__INTERRUPT__)))

+

+/**

+  * @brief  Disable the specified DMA Stream interrupts.

+  * @param  __HANDLE__: DMA handle

+  * @param  __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.

+  *         This parameter can be one of the following values:

+  *            @arg DMA_IT_TC: Transfer complete interrupt mask.

+  *            @arg DMA_IT_HT: Half transfer complete interrupt mask.

+  *            @arg DMA_IT_TE: Transfer error interrupt mask.

+  *            @arg DMA_IT_FE: FIFO error interrupt mask.

+  *            @arg DMA_IT_DME: Direct mode error interrupt.

+  * @retval None

+  */

+#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))?\

+                                                         (__HAL_DMA_STREAM_DISABLE_IT((__HANDLE__), (__INTERRUPT__))) :\

+                                                         (__HAL_BDMA_CHANNEL_DISABLE_IT((__HANDLE__), (__INTERRUPT__))))

+

+

+#define __HAL_BDMA_CHANNEL_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  ((((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CCR & (DMA_TO_BDMA_IT(__INTERRUPT__))))

+

+#define __HAL_DMA_STREAM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__INTERRUPT__) != DMA_IT_FE)? \

+                                                        (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->CR & (__INTERRUPT__)) : \

+                                                        (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->FCR & (__INTERRUPT__)))

+

+/**

+  * @brief  Check whether the specified DMA Stream interrupt is enabled or not.

+  * @param  __HANDLE__: DMA handle

+  * @param  __INTERRUPT__: specifies the DMA interrupt source to check.

+  *         This parameter can be one of the following values:

+  *            @arg DMA_IT_TC: Transfer complete interrupt mask.

+  *            @arg DMA_IT_HT: Half transfer complete interrupt mask.

+  *            @arg DMA_IT_TE: Transfer error interrupt mask.

+  *            @arg DMA_IT_FE: FIFO error interrupt mask.

+  *            @arg DMA_IT_DME: Direct mode error interrupt.

+  * @retval The state of DMA_IT.

+  */

+#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \

+                                                            (__HAL_DMA_STREAM_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))) :\

+                                                            (__HAL_BDMA_CHANNEL_GET_IT_SOURCE((__HANDLE__), (__INTERRUPT__))))

+

+/**

+  * @brief  Writes the number of data units to be transferred on the DMA Stream.

+  * @param  __HANDLE__: DMA handle

+  * @param  __COUNTER__: Number of data units to be transferred (from 0 to 65535)

+  *          Number of data items depends only on the Peripheral data format.

+  *

+  * @note   If Peripheral data format is Bytes: number of data units is equal

+  *         to total number of bytes to be transferred.

+  *

+  * @note   If Peripheral data format is Half-Word: number of data units is

+  *         equal to total number of bytes to be transferred / 2.

+  *

+  * @note   If Peripheral data format is Word: number of data units is equal

+  *         to total  number of bytes to be transferred / 4.

+  *

+  * @retval The number of remaining data units in the current DMAy Streamx transfer.

+  */

+#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \

+                                                        (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR = (uint16_t)(__COUNTER__)) :\

+                                                        (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR = (uint16_t)(__COUNTER__)))

+

+/**

+  * @brief  Returns the number of remaining data units in the current DMAy Streamx transfer.

+  * @param  __HANDLE__: DMA handle

+  *

+  * @retval The number of remaining data units in the current DMA Stream transfer.

+  */

+#define __HAL_DMA_GET_COUNTER(__HANDLE__) ((IS_DMA_STREAM_INSTANCE((__HANDLE__)->Instance))? \

+                                           (((DMA_Stream_TypeDef *)(__HANDLE__)->Instance)->NDTR) :\

+                                           (((BDMA_Channel_TypeDef *)(__HANDLE__)->Instance)->CNDTR))

+

+/**

+  * @}

+  */

+

+/* Include DMA HAL Extension module */

+#include "stm32h7xx_hal_dma_ex.h"

+

+/* Exported functions --------------------------------------------------------*/

+

+/** @defgroup DMA_Exported_Functions DMA Exported Functions

+  * @brief    DMA Exported functions

+  * @{

+  */

+

+/** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions

+  * @brief   Initialization and de-initialization functions

+  * @{

+  */

+HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);

+HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);

+/**

+  * @}

+  */

+

+/** @defgroup DMA_Exported_Functions_Group2 I/O operation functions

+  * @brief   I/O operation functions

+  * @{

+  */

+HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);

+HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);

+HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);

+HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);

+HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);

+void              HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);

+HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));

+HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);

+

+/**

+  * @}

+  */

+

+/** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions

+  * @brief    Peripheral State functions

+  * @{

+  */

+HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);

+uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);

+/**

+  * @}

+  */

+/**

+  * @}

+  */

+/* Private Constants -------------------------------------------------------------*/

+/** @defgroup DMA_Private_Constants DMA Private Constants

+  * @brief    DMA private defines and constants

+  * @{

+  */

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup DMA_Private_Macros DMA Private Macros

+  * @brief    DMA private macros

+  * @{

+  */

+

+#if defined(ADC3)

+#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_ADC3))

+#else

+#define IS_DMA_REQUEST(REQUEST) (((REQUEST) <= DMA_REQUEST_USART10_TX))

+#endif /* ADC3 */

+

+#if defined(ADC3)

+#define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_ADC3))

+#else

+#define IS_BDMA_REQUEST(REQUEST) (((REQUEST) <= BDMA_REQUEST_DFSDM2_FLT0))

+#endif /* ADC3 */

+

+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \

+                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \

+                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY))

+

+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))

+

+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \

+                                            ((STATE) == DMA_PINC_DISABLE))

+

+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \

+                                        ((STATE) == DMA_MINC_DISABLE))

+

+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \

+                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \

+                                           ((SIZE) == DMA_PDATAALIGN_WORD))

+

+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \

+                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \

+                                       ((SIZE) == DMA_MDATAALIGN_WORD ))

+

+#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )           || \

+                           ((MODE) == DMA_CIRCULAR)          || \

+                           ((MODE) == DMA_PFCTRL)            || \

+                           ((MODE) == DMA_DOUBLE_BUFFER_M0)  || \

+                           ((MODE) == DMA_DOUBLE_BUFFER_M1))

+

+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \

+                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \

+                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \

+                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))

+

+#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \

+                                       ((STATE) == DMA_FIFOMODE_ENABLE))

+

+#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \

+                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL)      || \

+                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \

+                                          ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))

+

+#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \

+                                    ((BURST) == DMA_MBURST_INC4)   || \

+                                    ((BURST) == DMA_MBURST_INC8)   || \

+                                    ((BURST) == DMA_MBURST_INC16))

+

+#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \

+                                        ((BURST) == DMA_PBURST_INC4)   || \

+                                        ((BURST) == DMA_PBURST_INC8)   || \

+                                        ((BURST) == DMA_PBURST_INC16))

+/**

+  * @}

+  */

+

+/* Private functions ---------------------------------------------------------*/

+/** @defgroup DMA_Private_Functions DMA Private Functions

+  * @brief    DMA private  functions

+  * @{

+  */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_DMA_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_dma2d.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_dma2d.h
new file mode 100644
index 0000000000..28ca638beb
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_dma2d.h
@@ -0,0 +1,706 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_dma2d.h

+  * @author  MCD Application Team

+  * @brief   Header file of DMA2D HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_DMA2D_H

+#define STM32H7xx_HAL_DMA2D_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+#if defined (DMA2D)

+

+/** @addtogroup DMA2D DMA2D

+  * @brief DMA2D HAL module driver

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup DMA2D_Exported_Types DMA2D Exported Types

+  * @{

+  */

+#define MAX_DMA2D_LAYER  2U  /*!< DMA2D maximum number of layers */

+

+/**

+  * @brief DMA2D CLUT Structure definition

+  */

+typedef struct

+{

+  uint32_t *pCLUT;                  /*!< Configures the DMA2D CLUT memory address.*/

+

+  uint32_t CLUTColorMode;           /*!< Configures the DMA2D CLUT color mode.

+                                         This parameter can be one value of @ref DMA2D_CLUT_CM. */

+

+  uint32_t Size;                    /*!< Configures the DMA2D CLUT size.

+                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/

+} DMA2D_CLUTCfgTypeDef;

+

+/**

+  * @brief DMA2D Init structure definition

+  */

+typedef struct

+{

+  uint32_t             Mode;               /*!< Configures the DMA2D transfer mode.

+                                                This parameter can be one value of @ref DMA2D_Mode. */

+

+  uint32_t             ColorMode;          /*!< Configures the color format of the output image.

+                                                This parameter can be one value of @ref DMA2D_Output_Color_Mode. */

+

+  uint32_t             OutputOffset;       /*!< Specifies the Offset value.

+                                                This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */

+  uint32_t             AlphaInverted;     /*!< Select regular or inverted alpha value for the output pixel format converter.

+                                               This parameter can be one value of @ref DMA2D_Alpha_Inverted. */

+

+  uint32_t             RedBlueSwap;       /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR)

+                                               for the output pixel format converter.

+                                               This parameter can be one value of @ref DMA2D_RB_Swap. */

+

+

+  uint32_t             BytesSwap;         /*!< Select byte regular mode or bytes swap mode (two by two).

+                                               This parameter can be one value of @ref DMA2D_Bytes_Swap. */

+

+  uint32_t             LineOffsetMode;    /*!< Configures how is expressed the line offset for the foreground, background and output.

+                                               This parameter can be one value of @ref DMA2D_Line_Offset_Mode. */

+

+} DMA2D_InitTypeDef;

+

+

+/**

+  * @brief DMA2D Layer structure definition

+  */

+typedef struct

+{

+  uint32_t             InputOffset;       /*!< Configures the DMA2D foreground or background offset.

+                                               This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */

+

+  uint32_t             InputColorMode;    /*!< Configures the DMA2D foreground or background color mode.

+                                               This parameter can be one value of @ref DMA2D_Input_Color_Mode. */

+

+  uint32_t             AlphaMode;         /*!< Configures the DMA2D foreground or background alpha mode.

+                                               This parameter can be one value of @ref DMA2D_Alpha_Mode. */

+

+  uint32_t             InputAlpha;        /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode.

+                                               This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below.

+                                               @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between

+                                               Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where

+                                               - InputAlpha[24:31] is the alpha value ALPHA[0:7]

+                                               - InputAlpha[16:23] is the red value RED[0:7]

+                                               - InputAlpha[8:15] is the green value GREEN[0:7]

+                                               - InputAlpha[0:7] is the blue value BLUE[0:7]. */

+  uint32_t             AlphaInverted;     /*!< Select regular or inverted alpha value.

+                                               This parameter can be one value of @ref DMA2D_Alpha_Inverted. */

+

+  uint32_t             RedBlueSwap;       /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR).

+                                               This parameter can be one value of @ref DMA2D_RB_Swap. */

+

+  uint32_t             ChromaSubSampling; /*!< Configure the chroma sub-sampling mode for the YCbCr color mode

+                                               This parameter can be one value of @ref DMA2D_Chroma_Sub_Sampling */

+

+} DMA2D_LayerCfgTypeDef;

+

+/**

+  * @brief  HAL DMA2D State structures definition

+  */

+typedef enum

+{

+  HAL_DMA2D_STATE_RESET             = 0x00U,    /*!< DMA2D not yet initialized or disabled       */

+  HAL_DMA2D_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */

+  HAL_DMA2D_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */

+  HAL_DMA2D_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */

+  HAL_DMA2D_STATE_ERROR             = 0x04U,    /*!< DMA2D state error                           */

+  HAL_DMA2D_STATE_SUSPEND           = 0x05U     /*!< DMA2D process is suspended                  */

+}HAL_DMA2D_StateTypeDef;

+

+/**

+  * @brief  DMA2D handle Structure definition

+  */

+typedef struct __DMA2D_HandleTypeDef

+{

+  DMA2D_TypeDef               *Instance;                                                    /*!< DMA2D register base address.               */

+

+  DMA2D_InitTypeDef           Init;                                                         /*!< DMA2D communication parameters.            */

+

+  void                        (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d);  /*!< DMA2D transfer complete callback.          */

+

+  void                        (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback.             */

+

+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)

+  void                        (* LineEventCallback)( struct __DMA2D_HandleTypeDef * hdma2d);   /*!< DMA2D line event callback.      */

+

+  void                        (* CLUTLoadingCpltCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D CLUT loading completion callback. */

+

+  void                        (* MspInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d);   /*!< DMA2D Msp Init callback.          */

+

+  void                        (* MspDeInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp DeInit callback.        */

+

+#endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */

+

+  DMA2D_LayerCfgTypeDef       LayerCfg[MAX_DMA2D_LAYER];                                    /*!< DMA2D Layers parameters           */

+

+  HAL_LockTypeDef             Lock;                                                         /*!< DMA2D lock.                                */

+

+  __IO HAL_DMA2D_StateTypeDef State;                                                        /*!< DMA2D transfer state.                      */

+

+  __IO uint32_t               ErrorCode;                                                    /*!< DMA2D error code.                          */

+} DMA2D_HandleTypeDef;

+

+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  HAL DMA2D Callback pointer definition

+  */

+typedef  void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Pointer to a DMA2D common callback function */

+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants

+  * @{

+  */

+

+/** @defgroup DMA2D_Error_Code DMA2D Error Code

+  * @{

+  */

+#define HAL_DMA2D_ERROR_NONE        0x00000000U  /*!< No error             */

+#define HAL_DMA2D_ERROR_TE          0x00000001U  /*!< Transfer error       */

+#define HAL_DMA2D_ERROR_CE          0x00000002U  /*!< Configuration error  */

+#define HAL_DMA2D_ERROR_CAE         0x00000004U  /*!< CLUT access error    */

+#define HAL_DMA2D_ERROR_TIMEOUT     0x00000020U  /*!< Timeout error        */

+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)

+#define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U  /*!< Invalid callback error  */

+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+/** @defgroup DMA2D_Mode DMA2D Mode

+  * @{

+  */

+#define DMA2D_M2M                   0x00000000U                         /*!< DMA2D memory to memory transfer mode */

+#define DMA2D_M2M_PFC               DMA2D_CR_MODE_0                     /*!< DMA2D memory to memory with pixel format conversion transfer mode */

+#define DMA2D_M2M_BLEND             DMA2D_CR_MODE_1                     /*!< DMA2D memory to memory with blending transfer mode */

+#define DMA2D_R2M                   (DMA2D_CR_MODE_1 | DMA2D_CR_MODE_0) /*!< DMA2D register to memory transfer mode */

+#define DMA2D_M2M_BLEND_FG          DMA2D_CR_MODE_2                     /*!< DMA2D memory to memory with blending transfer mode and fixed color FG */

+#define DMA2D_M2M_BLEND_BG          (DMA2D_CR_MODE_2 | DMA2D_CR_MODE_0) /*!< DMA2D memory to memory with blending transfer mode and fixed color BG */

+/**

+  * @}

+  */

+

+/** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode

+  * @{

+  */

+#define DMA2D_OUTPUT_ARGB8888       0x00000000U                           /*!< ARGB8888 DMA2D color mode */

+#define DMA2D_OUTPUT_RGB888         DMA2D_OPFCCR_CM_0                     /*!< RGB888 DMA2D color mode   */

+#define DMA2D_OUTPUT_RGB565         DMA2D_OPFCCR_CM_1                     /*!< RGB565 DMA2D color mode   */

+#define DMA2D_OUTPUT_ARGB1555       (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */

+#define DMA2D_OUTPUT_ARGB4444       DMA2D_OPFCCR_CM_2                     /*!< ARGB4444 DMA2D color mode */

+/**

+  * @}

+  */

+

+/** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode

+  * @{

+  */

+#define DMA2D_INPUT_ARGB8888        0x00000000U  /*!< ARGB8888 color mode */

+#define DMA2D_INPUT_RGB888          0x00000001U  /*!< RGB888 color mode   */

+#define DMA2D_INPUT_RGB565          0x00000002U  /*!< RGB565 color mode   */

+#define DMA2D_INPUT_ARGB1555        0x00000003U  /*!< ARGB1555 color mode */

+#define DMA2D_INPUT_ARGB4444        0x00000004U  /*!< ARGB4444 color mode */

+#define DMA2D_INPUT_L8              0x00000005U  /*!< L8 color mode       */

+#define DMA2D_INPUT_AL44            0x00000006U  /*!< AL44 color mode     */

+#define DMA2D_INPUT_AL88            0x00000007U  /*!< AL88 color mode     */

+#define DMA2D_INPUT_L4              0x00000008U  /*!< L4 color mode       */

+#define DMA2D_INPUT_A8              0x00000009U  /*!< A8 color mode       */

+#define DMA2D_INPUT_A4              0x0000000AU  /*!< A4 color mode       */

+#define DMA2D_INPUT_YCBCR           0x0000000BU  /*!< YCbCr color mode */

+/**

+  * @}

+  */

+

+/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode

+  * @{

+  */

+#define DMA2D_NO_MODIF_ALPHA        0x00000000U  /*!< No modification of the alpha channel value */

+#define DMA2D_REPLACE_ALPHA         0x00000001U  /*!< Replace original alpha channel value by programmed alpha value */

+#define DMA2D_COMBINE_ALPHA         0x00000002U  /*!< Replace original alpha channel value by programmed alpha value

+                                                                with original alpha channel value                              */

+/**

+  * @}

+  */

+

+/** @defgroup DMA2D_Alpha_Inverted DMA2D Alpha Inversion

+  * @{

+  */

+#define DMA2D_REGULAR_ALPHA         0x00000000U  /*!< No modification of the alpha channel value */

+#define DMA2D_INVERTED_ALPHA        0x00000001U  /*!< Invert the alpha channel value */

+/**

+  * @}

+  */

+

+/** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap

+  * @{

+  */

+#define DMA2D_RB_REGULAR            0x00000000U  /*!< Select regular mode (RGB or ARGB) */

+#define DMA2D_RB_SWAP               0x00000001U  /*!< Select swap mode (BGR or ABGR) */

+/**

+  * @}

+  */

+

+

+

+/** @defgroup DMA2D_Line_Offset_Mode DMA2D Line Offset Mode

+  * @{

+  */

+#define DMA2D_LOM_PIXELS            0x00000000U   /*!< Line offsets expressed in pixels */

+#define DMA2D_LOM_BYTES             DMA2D_CR_LOM  /*!< Line offsets expressed in bytes */

+/**

+  * @}

+  */

+

+/** @defgroup DMA2D_Bytes_Swap DMA2D Bytes Swap

+  * @{

+  */

+#define DMA2D_BYTES_REGULAR         0x00000000U      /*!< Bytes in regular order in output FIFO */

+#define DMA2D_BYTES_SWAP            DMA2D_OPFCCR_SB  /*!< Bytes are swapped two by two in output FIFO */

+/**

+  * @}

+  */

+

+/** @defgroup DMA2D_Chroma_Sub_Sampling DMA2D Chroma Sub Sampling

+  * @{

+  */

+#define DMA2D_NO_CSS               0x00000000U  /*!< No chroma sub-sampling 4:4:4 */

+#define DMA2D_CSS_422              0x00000001U  /*!< chroma sub-sampling 4:2:2 */

+#define DMA2D_CSS_420              0x00000002U  /*!< chroma sub-sampling 4:2:0 */

+/**

+  * @}

+  */

+

+/** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode

+  * @{

+  */

+#define DMA2D_CCM_ARGB8888          0x00000000U  /*!< ARGB8888 DMA2D CLUT color mode */

+#define DMA2D_CCM_RGB888            0x00000001U  /*!< RGB888 DMA2D CLUT color mode   */

+/**

+  * @}

+  */

+

+/** @defgroup DMA2D_Interrupts DMA2D Interrupts

+  * @{

+  */

+#define DMA2D_IT_CE                 DMA2D_CR_CEIE            /*!< Configuration Error Interrupt */

+#define DMA2D_IT_CTC                DMA2D_CR_CTCIE           /*!< CLUT Transfer Complete Interrupt */

+#define DMA2D_IT_CAE                DMA2D_CR_CAEIE           /*!< CLUT Access Error Interrupt */

+#define DMA2D_IT_TW                 DMA2D_CR_TWIE            /*!< Transfer Watermark Interrupt */

+#define DMA2D_IT_TC                 DMA2D_CR_TCIE            /*!< Transfer Complete Interrupt */

+#define DMA2D_IT_TE                 DMA2D_CR_TEIE            /*!< Transfer Error Interrupt */

+/**

+  * @}

+  */

+

+/** @defgroup DMA2D_Flags DMA2D Flags

+  * @{

+  */

+#define DMA2D_FLAG_CE               DMA2D_ISR_CEIF           /*!< Configuration Error Interrupt Flag */

+#define DMA2D_FLAG_CTC              DMA2D_ISR_CTCIF          /*!< CLUT Transfer Complete Interrupt Flag */

+#define DMA2D_FLAG_CAE              DMA2D_ISR_CAEIF          /*!< CLUT Access Error Interrupt Flag */

+#define DMA2D_FLAG_TW               DMA2D_ISR_TWIF           /*!< Transfer Watermark Interrupt Flag */

+#define DMA2D_FLAG_TC               DMA2D_ISR_TCIF           /*!< Transfer Complete Interrupt Flag */

+#define DMA2D_FLAG_TE               DMA2D_ISR_TEIF           /*!< Transfer Error Interrupt Flag */

+/**

+  * @}

+  */

+

+/** @defgroup DMA2D_Aliases DMA2D API Aliases

+  * @{

+  */

+#define HAL_DMA2D_DisableCLUT       HAL_DMA2D_CLUTLoading_Abort    /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */

+/**

+  * @}

+  */

+

+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  HAL DMA2D common Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_DMA2D_MSPINIT_CB_ID           = 0x00U,    /*!< DMA2D MspInit callback ID                 */

+  HAL_DMA2D_MSPDEINIT_CB_ID         = 0x01U,    /*!< DMA2D MspDeInit callback ID               */

+  HAL_DMA2D_TRANSFERCOMPLETE_CB_ID  = 0x02U,    /*!< DMA2D transfer complete callback ID       */

+  HAL_DMA2D_TRANSFERERROR_CB_ID     = 0x03U,    /*!< DMA2D transfer error callback ID          */

+  HAL_DMA2D_LINEEVENT_CB_ID         = 0x04U,    /*!< DMA2D line event callback ID              */

+  HAL_DMA2D_CLUTLOADINGCPLT_CB_ID   = 0x05U,    /*!< DMA2D CLUT loading completion callback ID */

+}HAL_DMA2D_CallbackIDTypeDef;

+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */

+

+

+/**

+  * @}

+  */

+/* Exported macros ------------------------------------------------------------*/

+/** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros

+  * @{

+  */

+

+/** @brief Reset DMA2D handle state

+  * @param  __HANDLE__ specifies the DMA2D handle.

+  * @retval None

+  */

+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)

+#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{                                            \

+                                                      (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\

+                                                      (__HANDLE__)->MspInitCallback = NULL;       \

+                                                      (__HANDLE__)->MspDeInitCallback = NULL;     \

+                                                     }while(0)

+#else

+#define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)

+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */

+

+

+/**

+  * @brief  Enable the DMA2D.

+  * @param  __HANDLE__ DMA2D handle

+  * @retval None.

+  */

+#define __HAL_DMA2D_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)

+

+

+/* Interrupt & Flag management */

+/**

+  * @brief  Get the DMA2D pending flags.

+  * @param  __HANDLE__ DMA2D handle

+  * @param  __FLAG__ flag to check.

+  *          This parameter can be any combination of the following values:

+  *            @arg DMA2D_FLAG_CE:  Configuration error flag

+  *            @arg DMA2D_FLAG_CTC: CLUT transfer complete flag

+  *            @arg DMA2D_FLAG_CAE: CLUT access error flag

+  *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag

+  *            @arg DMA2D_FLAG_TC:  Transfer complete flag

+  *            @arg DMA2D_FLAG_TE:  Transfer error flag

+  * @retval The state of FLAG.

+  */

+#define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))

+

+/**

+  * @brief  Clear the DMA2D pending flags.

+  * @param  __HANDLE__ DMA2D handle

+  * @param  __FLAG__ specifies the flag to clear.

+  *          This parameter can be any combination of the following values:

+  *            @arg DMA2D_FLAG_CE:  Configuration error flag

+  *            @arg DMA2D_FLAG_CTC: CLUT transfer complete flag

+  *            @arg DMA2D_FLAG_CAE: CLUT access error flag

+  *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag

+  *            @arg DMA2D_FLAG_TC:  Transfer complete flag

+  *            @arg DMA2D_FLAG_TE:  Transfer error flag

+  * @retval None

+  */

+#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))

+

+/**

+  * @brief  Enable the specified DMA2D interrupts.

+  * @param  __HANDLE__ DMA2D handle

+  * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled.

+  *          This parameter can be any combination of the following values:

+  *            @arg DMA2D_IT_CE:  Configuration error interrupt mask

+  *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask

+  *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask

+  *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask

+  *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask

+  *            @arg DMA2D_IT_TE:  Transfer error interrupt mask

+  * @retval None

+  */

+#define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

+

+/**

+  * @brief  Disable the specified DMA2D interrupts.

+  * @param  __HANDLE__ DMA2D handle

+  * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled.

+  *          This parameter can be any combination of the following values:

+  *            @arg DMA2D_IT_CE:  Configuration error interrupt mask

+  *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask

+  *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask

+  *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask

+  *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask

+  *            @arg DMA2D_IT_TE:  Transfer error interrupt mask

+  * @retval None

+  */

+#define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

+

+/**

+  * @brief  Check whether the specified DMA2D interrupt source is enabled or not.

+  * @param  __HANDLE__ DMA2D handle

+  * @param  __INTERRUPT__ specifies the DMA2D interrupt source to check.

+  *          This parameter can be one of the following values:

+  *            @arg DMA2D_IT_CE:  Configuration error interrupt mask

+  *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask

+  *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask

+  *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask

+  *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask

+  *            @arg DMA2D_IT_TE:  Transfer error interrupt mask

+  * @retval The state of INTERRUPT source.

+  */

+#define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions

+  * @{

+  */

+

+/** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions

+  * @{

+  */

+

+/* Initialization and de-initialization functions *******************************/

+HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);

+HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);

+void              HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);

+void              HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);

+/* Callbacks Register/UnRegister functions  ***********************************/

+#if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)

+HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID);

+#endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+

+/** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions

+  * @{

+  */

+

+/* IO operation functions *******************************************************/

+HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);

+HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height);

+HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);

+HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);

+HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);

+HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);

+HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);

+HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_DMA2D_CLUTStartLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef *CLUTCfg, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);

+void              HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);

+void              HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);

+void              HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);

+

+/**

+  * @}

+  */

+

+/** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions

+  * @{

+  */

+

+/* Peripheral Control functions *************************************************/

+HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);

+HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);

+HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);

+HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);

+

+/**

+  * @}

+  */

+

+/** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions

+  * @{

+  */

+

+/* Peripheral State functions ***************************************************/

+HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);

+uint32_t               HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private constants ---------------------------------------------------------*/

+

+/** @addtogroup DMA2D_Private_Constants DMA2D Private Constants

+  * @{

+  */

+

+/** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark

+  * @{

+  */

+#define DMA2D_LINE_WATERMARK_MAX            DMA2D_LWR_LW       /*!< DMA2D maximum line watermark */

+/**

+  * @}

+  */

+

+/** @defgroup DMA2D_Color_Value DMA2D Color Value

+  * @{

+  */

+#define DMA2D_COLOR_VALUE                 0x000000FFU  /*!< Color value mask */

+/**

+  * @}

+  */

+

+/** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers

+  * @{

+  */

+#define DMA2D_MAX_LAYER         2U         /*!< DMA2D maximum number of layers */

+/**

+  * @}

+  */

+

+/** @defgroup DMA2D_Layers DMA2D Layers

+  * @{

+  */

+#define DMA2D_BACKGROUND_LAYER             0x00000000U   /*!< DMA2D Background Layer (layer 0) */

+#define DMA2D_FOREGROUND_LAYER             0x00000001U   /*!< DMA2D Foreground Layer (layer 1) */

+/**

+  * @}

+  */

+

+/** @defgroup DMA2D_Offset DMA2D Offset

+  * @{

+  */

+#define DMA2D_OFFSET                DMA2D_FGOR_LO            /*!< maximum Line Offset */

+/**

+  * @}

+  */

+

+/** @defgroup DMA2D_Size DMA2D Size

+  * @{

+  */

+#define DMA2D_PIXEL                 (DMA2D_NLR_PL >> 16U)    /*!< DMA2D maximum number of pixels per line */

+#define DMA2D_LINE                  DMA2D_NLR_NL             /*!< DMA2D maximum number of lines           */

+/**

+  * @}

+  */

+

+/** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size

+  * @{

+  */

+#define DMA2D_CLUT_SIZE             (DMA2D_FGPFCCR_CS >> 8U)  /*!< DMA2D maximum CLUT size */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup DMA2D_Private_Macros DMA2D Private Macros

+  * @{

+  */

+#define IS_DMA2D_LAYER(LAYER)                 (((LAYER) == DMA2D_BACKGROUND_LAYER) || ((LAYER) == DMA2D_FOREGROUND_LAYER))

+

+#define IS_DMA2D_MODE(MODE)                   (((MODE) == DMA2D_M2M)          || ((MODE) == DMA2D_M2M_PFC) || \

+                                               ((MODE) == DMA2D_M2M_BLEND)    || ((MODE) == DMA2D_R2M)     || \

+                                               ((MODE) == DMA2D_M2M_BLEND_FG) || ((MODE) == DMA2D_M2M_BLEND_BG))

+

+#define IS_DMA2D_CMODE(MODE_ARGB)             (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888)   || \

+                                               ((MODE_ARGB) == DMA2D_OUTPUT_RGB565)   || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \

+                                               ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))

+

+#define IS_DMA2D_COLOR(COLOR)                 ((COLOR) <= DMA2D_COLOR_VALUE)

+#define IS_DMA2D_LINE(LINE)                   ((LINE) <= DMA2D_LINE)

+#define IS_DMA2D_PIXEL(PIXEL)                 ((PIXEL) <= DMA2D_PIXEL)

+#define IS_DMA2D_OFFSET(OOFFSET)              ((OOFFSET) <= DMA2D_OFFSET)

+

+#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM)   (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888)   || \

+                                               ((INPUT_CM) == DMA2D_INPUT_RGB565)   || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \

+                                               ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8)       || \

+                                               ((INPUT_CM) == DMA2D_INPUT_AL44)     || ((INPUT_CM) == DMA2D_INPUT_AL88)     || \

+                                               ((INPUT_CM) == DMA2D_INPUT_L4)       || ((INPUT_CM) == DMA2D_INPUT_A8)       || \

+                                               ((INPUT_CM) == DMA2D_INPUT_A4)       || ((INPUT_CM) == DMA2D_INPUT_YCBCR))

+

+#define IS_DMA2D_ALPHA_MODE(AlphaMode)        (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \

+                                               ((AlphaMode) == DMA2D_REPLACE_ALPHA)  || \

+                                               ((AlphaMode) == DMA2D_COMBINE_ALPHA))

+

+#define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \

+                                                 ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA))

+

+#define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \

+                                   ((RB_Swap) == DMA2D_RB_SWAP))

+

+#define IS_DMA2D_LOM_MODE(LOM)          (((LOM) == DMA2D_LOM_PIXELS) || \

+                                         ((LOM) == DMA2D_LOM_BYTES))

+

+#define IS_DMA2D_BYTES_SWAP(BYTES_SWAP) (((BYTES_SWAP) == DMA2D_BYTES_REGULAR) || \

+                                         ((BYTES_SWAP) == DMA2D_BYTES_SWAP))

+

+#define IS_DMA2D_CHROMA_SUB_SAMPLING(CSS) (((CSS) == DMA2D_NO_CSS)  || \

+                                           ((CSS) == DMA2D_CSS_422) || \

+                                           ((CSS) == DMA2D_CSS_420))

+

+#define IS_DMA2D_CLUT_CM(CLUT_CM)             (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))

+#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE)         ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)

+#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)

+#define IS_DMA2D_IT(IT)                       (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \

+                                               ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \

+                                               ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))

+#define IS_DMA2D_GET_FLAG(FLAG)               (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \

+                                               ((FLAG) == DMA2D_FLAG_TW)   || ((FLAG) == DMA2D_FLAG_TC)  || \

+                                               ((FLAG) == DMA2D_FLAG_TE)   || ((FLAG) == DMA2D_FLAG_CE))

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* defined (DMA2D) */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_DMA2D_H */

+

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_dma_ex.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_dma_ex.h
new file mode 100644
index 0000000000..4125ae7e6c
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_dma_ex.h
@@ -0,0 +1,312 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_dma_ex.h

+  * @author  MCD Application Team

+  * @brief   Header file of DMA HAL extension module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_DMA_EX_H

+#define STM32H7xx_HAL_DMA_EX_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup DMAEx

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup DMAEx_Exported_Types DMAEx Exported Types

+  * @brief DMAEx Exported types

+  * @{

+  */

+

+/**

+  * @brief  HAL DMA Memory definition

+  */

+typedef enum

+{

+  MEMORY0      = 0x00U,    /*!< Memory 0     */

+  MEMORY1      = 0x01U,    /*!< Memory 1     */

+

+}HAL_DMA_MemoryTypeDef;

+

+/**

+  * @brief  HAL DMAMUX Synchronization configuration structure definition

+  */

+typedef struct

+{

+  uint32_t SyncSignalID;  /*!< Specifies the synchronization signal gating the DMA request in periodic mode.

+                              This parameter can be a value of @ref DMAEx_MUX_SyncSignalID_selection */

+

+  uint32_t SyncPolarity;  /*!< Specifies the polarity of the signal on which the DMA request is synchronized.

+                              This parameter can be a value of @ref DMAEx_MUX_SyncPolarity_selection */

+

+  FunctionalState SyncEnable;  /*!< Specifies if the synchronization shall be enabled or disabled

+                                    This parameter can take the value ENABLE or DISABLE*/

+

+

+  FunctionalState EventEnable;    /*!< Specifies if an event shall be generated once the RequestNumber is reached.

+                                       This parameter can take the value ENABLE or DISABLE */

+

+  uint32_t RequestNumber; /*!< Specifies the number of DMA request that will be authorized after a sync event.

+                               This parameters can be in the range 1 to 32 */

+

+}HAL_DMA_MuxSyncConfigTypeDef;

+

+

+/**

+  * @brief  HAL DMAMUX request generator parameters structure definition

+  */

+typedef struct

+{

+ uint32_t SignalID;      /*!< Specifies the ID of the signal used for DMAMUX request generator

+                              This parameter can be a value of @ref DMAEx_MUX_SignalGeneratorID_selection */

+

+  uint32_t Polarity;       /*!< Specifies the polarity of the signal on which the request is generated.

+                             This parameter can be a value of @ref DMAEx_MUX_RequestGeneneratorPolarity_selection */

+

+  uint32_t RequestNumber;  /*!< Specifies the number of DMA request that will be generated after a signal event.

+                                This parameters can be in the range 1 to 32 */

+

+}HAL_DMA_MuxRequestGeneratorConfigTypeDef;

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+

+/** @defgroup DMAEx_Exported_Constants DMA Exported Constants

+  * @brief    DMAEx Exported constants

+  * @{

+  */

+

+/** @defgroup DMAEx_MUX_SyncSignalID_selection DMAEx MUX SyncSignalID selection

+  * @brief    DMAEx MUX SyncSignalID selection

+  * @{

+  */

+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT   0U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel0 Event */

+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT   1U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel1 Event */

+#define HAL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT   2U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel2 Event */

+#define HAL_DMAMUX1_SYNC_LPTIM1_OUT        3U   /*!< DMAMUX1 synchronization Signal is LPTIM1 OUT             */

+#define HAL_DMAMUX1_SYNC_LPTIM2_OUT        4U   /*!< DMAMUX1 synchronization Signal is LPTIM2 OUT             */

+#define HAL_DMAMUX1_SYNC_LPTIM3_OUT        5U   /*!< DMAMUX1 synchronization Signal is LPTIM3 OUT             */

+#define HAL_DMAMUX1_SYNC_EXTI0             6U   /*!< DMAMUX1 synchronization Signal is EXTI0 IT               */

+#define HAL_DMAMUX1_SYNC_TIM12_TRGO        7U   /*!< DMAMUX1 synchronization Signal is TIM12 TRGO             */

+

+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT   0U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel0 Event */

+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT   1U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel1 Event */

+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT   2U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel2 Event */

+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT   3U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel3 Event */

+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT   4U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel4 Event */

+#define HAL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT   5U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel5 Event */

+#define HAL_DMAMUX2_SYNC_LPUART1_RX_WKUP   6U   /*!< DMAMUX2 synchronization Signal is LPUART1 RX Wakeup      */

+#define HAL_DMAMUX2_SYNC_LPUART1_TX_WKUP   7U   /*!< DMAMUX2 synchronization Signal is LPUART1 TX Wakeup      */

+#define HAL_DMAMUX2_SYNC_LPTIM2_OUT        8U   /*!< DMAMUX2 synchronization Signal is LPTIM2 output          */

+#define HAL_DMAMUX2_SYNC_LPTIM3_OUT        9U   /*!< DMAMUX2 synchronization Signal is LPTIM3 output          */

+#define HAL_DMAMUX2_SYNC_I2C4_WKUP        10U   /*!< DMAMUX2 synchronization Signal is I2C4 Wakeup            */

+#define HAL_DMAMUX2_SYNC_SPI6_WKUP        11U   /*!< DMAMUX2 synchronization Signal is SPI6 Wakeup            */

+#define HAL_DMAMUX2_SYNC_COMP1_OUT        12U   /*!< DMAMUX2 synchronization Signal is Comparator 1 output    */

+#define HAL_DMAMUX2_SYNC_RTC_WKUP         13U   /*!< DMAMUX2 synchronization Signal is RTC Wakeup             */

+#define HAL_DMAMUX2_SYNC_EXTI0            14U   /*!< DMAMUX2 synchronization Signal is EXTI0 IT               */

+#define HAL_DMAMUX2_SYNC_EXTI2            15U   /*!< DMAMUX2 synchronization Signal is EXTI2 IT               */

+

+/**

+  * @}

+  */

+

+/** @defgroup DMAEx_MUX_SyncPolarity_selection DMAEx MUX SyncPolarity selection

+  * @brief    DMAEx MUX SyncPolarity selection

+  * @{

+  */

+#define HAL_DMAMUX_SYNC_NO_EVENT        0x00000000U             /*!< block synchronization events                    */

+#define HAL_DMAMUX_SYNC_RISING          DMAMUX_CxCR_SPOL_0      /*!< synchronize with rising edge events             */

+#define HAL_DMAMUX_SYNC_FALLING         DMAMUX_CxCR_SPOL_1      /*!< synchronize with falling edge events            */

+#define HAL_DMAMUX_SYNC_RISING_FALLING  DMAMUX_CxCR_SPOL        /*!< synchronize with rising and falling edge events */

+

+/**

+  * @}

+  */

+

+

+/** @defgroup DMAEx_MUX_SignalGeneratorID_selection DMAEx MUX SignalGeneratorID selection

+  * @brief    DMAEx MUX SignalGeneratorID selection

+  * @{

+  */

+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT   0U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel0 Event */

+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT   1U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel1 Event */

+#define HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT   2U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel2 Event */

+#define HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT        3U   /*!< DMAMUX1 Request generator Signal is LPTIM1 OUT             */

+#define HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT        4U   /*!< DMAMUX1 Request generator Signal is LPTIM2 OUT             */

+#define HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT        5U   /*!< DMAMUX1 Request generator Signal is LPTIM3 OUT             */

+#define HAL_DMAMUX1_REQ_GEN_EXTI0             6U   /*!< DMAMUX1 Request generator Signal is EXTI0 IT               */

+#define HAL_DMAMUX1_REQ_GEN_TIM12_TRGO        7U   /*!< DMAMUX1 Request generator Signal is TIM12 TRGO             */

+

+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT   0U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel0 Event */

+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT   1U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel1 Event */

+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT   2U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel2 Event */

+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT   3U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel3 Event */

+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT   4U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel4 Event */

+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT   5U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel5 Event */

+#define HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT   6U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel6 Event */

+#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP   7U   /*!< DMAMUX2 Request generator Signal is LPUART1 RX Wakeup      */

+#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP   8U   /*!< DMAMUX2 Request generator Signal is LPUART1 TX Wakeup      */

+#define HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP       9U   /*!< DMAMUX2 Request generator Signal is LPTIM2 Wakeup          */

+#define HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT       10U   /*!< DMAMUX2 Request generator Signal is LPTIM2 OUT             */

+#define HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP      11U   /*!< DMAMUX2 Request generator Signal is LPTIM3 Wakeup          */

+#define HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT       12U   /*!< DMAMUX2 Request generator Signal is LPTIM3 OUT             */

+#if defined(LPTIM4)

+#define HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP      13U   /*!< DMAMUX2 Request generator Signal is LPTIM4 Wakeup          */

+#endif /* LPTIM4 */

+#if defined(LPTIM5)

+#define HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP      14U   /*!< DMAMUX2 Request generator Signal is LPTIM5 Wakeup          */

+#endif /* LPTIM5 */

+#define HAL_DMAMUX2_REQ_GEN_I2C4_WKUP        15U   /*!< DMAMUX2 Request generator Signal is I2C4 Wakeup            */

+#define HAL_DMAMUX2_REQ_GEN_SPI6_WKUP        16U   /*!< DMAMUX2 Request generator Signal is SPI6 Wakeup            */

+#define HAL_DMAMUX2_REQ_GEN_COMP1_OUT        17U   /*!< DMAMUX2 Request generator Signal is Comparator 1 output    */

+#define HAL_DMAMUX2_REQ_GEN_COMP2_OUT        18U   /*!< DMAMUX2 Request generator Signal is Comparator 2 output    */

+#define HAL_DMAMUX2_REQ_GEN_RTC_WKUP         19U   /*!< DMAMUX2 Request generator Signal is RTC Wakeup             */

+#define HAL_DMAMUX2_REQ_GEN_EXTI0            20U   /*!< DMAMUX2 Request generator Signal is EXTI0                  */

+#define HAL_DMAMUX2_REQ_GEN_EXTI2            21U   /*!< DMAMUX2 Request generator Signal is EXTI2                  */

+#define HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT      22U   /*!< DMAMUX2 Request generator Signal is I2C4 IT Event          */

+#define HAL_DMAMUX2_REQ_GEN_SPI6_IT          23U   /*!< DMAMUX2 Request generator Signal is SPI6 IT                */

+#define HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT    24U   /*!< DMAMUX2 Request generator Signal is LPUART1 Tx IT          */

+#define HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT    25U   /*!< DMAMUX2 Request generator Signal is LPUART1 Rx IT          */

+#if defined(ADC3)

+#define HAL_DMAMUX2_REQ_GEN_ADC3_IT          26U   /*!< DMAMUX2 Request generator Signal is ADC3 IT                */

+#define HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT    27U   /*!< DMAMUX2 Request generator Signal is ADC3 Analog Watchdog 1 output */

+#endif /* ADC3 */

+#define HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT      28U   /*!< DMAMUX2 Request generator Signal is BDMA Channel 0 IT      */

+#define HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT      29U   /*!< DMAMUX2 Request generator Signal is BDMA Channel 1 IT      */

+

+

+/**

+  * @}

+  */

+

+/** @defgroup DMAEx_MUX_RequestGeneneratorPolarity_selection DMAEx MUX RequestGeneneratorPolarity selection

+  * @brief    DMAEx MUX RequestGeneneratorPolarity selection

+  * @{

+  */

+#define HAL_DMAMUX_REQ_GEN_NO_EVENT        0x00000000U           /*!< block request generator events                     */

+#define HAL_DMAMUX_REQ_GEN_RISING          DMAMUX_RGxCR_GPOL_0  /*!< generate request on rising edge events             */

+#define HAL_DMAMUX_REQ_GEN_FALLING         DMAMUX_RGxCR_GPOL_1  /*!< generate request on falling edge events            */

+#define HAL_DMAMUX_REQ_GEN_RISING_FALLING  DMAMUX_RGxCR_GPOL    /*!< generate request on rising and falling edge events */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions

+  * @brief   DMAEx Exported functions

+  * @{

+  */

+

+/** @defgroup DMAEx_Exported_Functions_Group1 Extended features functions

+  * @brief   Extended features functions

+  * @{

+  */

+

+/* IO operation functions *******************************************************/

+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);

+HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength);

+HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Address, HAL_DMA_MemoryTypeDef memory);

+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxSync(DMA_HandleTypeDef *hdma, HAL_DMA_MuxSyncConfigTypeDef *pSyncConfig);

+HAL_StatusTypeDef HAL_DMAEx_ConfigMuxRequestGenerator (DMA_HandleTypeDef *hdma, HAL_DMA_MuxRequestGeneratorConfigTypeDef *pRequestGeneratorConfig);

+HAL_StatusTypeDef HAL_DMAEx_EnableMuxRequestGenerator (DMA_HandleTypeDef *hdma);

+HAL_StatusTypeDef HAL_DMAEx_DisableMuxRequestGenerator (DMA_HandleTypeDef *hdma);

+

+void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma);

+/**

+  * @}

+  */

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup DMAEx_Private_Macros DMA Private Macros

+  * @brief    DMAEx private macros

+  * @{

+  */

+

+#define IS_DMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_SYNC_TIM12_TRGO)

+#define IS_BDMA_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_SYNC_EXTI2)

+

+#define IS_DMAMUX_SYNC_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))

+

+#define IS_DMAMUX_SYNC_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_SYNC_NO_EVENT)    || \

+                                           ((POLARITY) == HAL_DMAMUX_SYNC_RISING)   || \

+                                           ((POLARITY) == HAL_DMAMUX_SYNC_FALLING)  || \

+                                           ((POLARITY) == HAL_DMAMUX_SYNC_RISING_FALLING))

+

+#define IS_DMAMUX_SYNC_STATE(SYNC) (((SYNC) == DISABLE)   || ((SYNC) == ENABLE))

+

+#define IS_DMAMUX_SYNC_EVENT(EVENT) (((EVENT) == DISABLE)   || \

+                                     ((EVENT) == ENABLE))

+

+#define IS_DMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX1_REQ_GEN_TIM12_TRGO)

+#define IS_BDMA_DMAMUX_REQUEST_GEN_SIGNAL_ID(SIGNAL_ID) ((SIGNAL_ID) <= HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT)

+

+#define IS_DMAMUX_REQUEST_GEN_REQUEST_NUMBER(REQUEST_NUMBER) (((REQUEST_NUMBER) > 0U) && ((REQUEST_NUMBER) <= 32U))

+

+#define IS_DMAMUX_REQUEST_GEN_POLARITY(POLARITY) (((POLARITY) == HAL_DMAMUX_REQ_GEN_NO_EVENT) || \

+                                                  ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING)   || \

+                                                  ((POLARITY) == HAL_DMAMUX_REQ_GEN_FALLING)   || \

+                                                  ((POLARITY) == HAL_DMAMUX_REQ_GEN_RISING_FALLING))

+

+/**

+  * @}

+  */

+

+/* Private functions ---------------------------------------------------------*/

+/** @defgroup DMAEx_Private_Functions DMAEx Private Functions

+  * @brief DMAEx Private functions

+  * @{

+  */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_DMA_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_dsi.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_dsi.h
new file mode 100644
index 0000000000..ca5293a825
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_dsi.h
@@ -0,0 +1,1352 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_dsi.h

+  * @author  MCD Application Team

+  * @brief   Header file of DSI HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_DSI_H

+#define STM32H7xx_HAL_DSI_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+#if defined(DSI)

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @defgroup DSI DSI

+  * @brief DSI HAL module driver

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/**

+  * @brief  DSI Init Structure definition

+  */

+typedef struct

+{

+  uint32_t AutomaticClockLaneControl;    /*!< Automatic clock lane control

+                                              This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */

+

+  uint32_t TXEscapeCkdiv;                /*!< TX Escape clock division

+                                              The values 0 and 1 stop the TX_ESC clock generation                    */

+

+  uint32_t NumberOfLanes;                /*!< Number of lanes

+                                              This parameter can be any value of @ref DSI_Number_Of_Lanes            */

+

+} DSI_InitTypeDef;

+

+/**

+  * @brief  DSI PLL Clock structure definition

+  */

+typedef struct

+{

+  uint32_t PLLNDIV;                      /*!< PLL Loop Division Factor

+                                              This parameter must be a value between 10 and 125   */

+

+  uint32_t PLLIDF;                       /*!< PLL Input Division Factor

+                                              This parameter can be any value of @ref DSI_PLL_IDF */

+

+  uint32_t PLLODF;                       /*!< PLL Output Division Factor

+                                              This parameter can be any value of @ref DSI_PLL_ODF */

+

+} DSI_PLLInitTypeDef;

+

+/**

+  * @brief  DSI Video mode configuration

+  */

+typedef struct

+{

+  uint32_t VirtualChannelID;             /*!< Virtual channel ID                                                 */

+

+  uint32_t ColorCoding;                  /*!< Color coding for LTDC interface

+                                              This parameter can be any value of @ref DSI_Color_Coding           */

+

+  uint32_t LooselyPacked;                /*!< Enable or disable loosely packed stream (needed only when using

+                                              18-bit configuration).

+                                              This parameter can be any value of @ref DSI_LooselyPacked          */

+

+  uint32_t Mode;                         /*!< Video mode type

+                                              This parameter can be any value of @ref DSI_Video_Mode_Type        */

+

+  uint32_t PacketSize;                   /*!< Video packet size                                                  */

+

+  uint32_t NumberOfChunks;               /*!< Number of chunks                                                   */

+

+  uint32_t NullPacketSize;               /*!< Null packet size                                                   */

+

+  uint32_t HSPolarity;                   /*!< HSYNC pin polarity

+                                              This parameter can be any value of @ref DSI_HSYNC_Polarity         */

+

+  uint32_t VSPolarity;                   /*!< VSYNC pin polarity

+                                              This parameter can be any value of @ref DSI_VSYNC_Active_Polarity  */

+

+  uint32_t DEPolarity;                   /*!< Data Enable pin polarity

+                                              This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity   */

+

+  uint32_t HorizontalSyncActive;         /*!< Horizontal synchronism active duration (in lane byte clock cycles) */

+

+  uint32_t HorizontalBackPorch;          /*!< Horizontal back-porch duration (in lane byte clock cycles)         */

+

+  uint32_t HorizontalLine;               /*!< Horizontal line duration (in lane byte clock cycles)               */

+

+  uint32_t VerticalSyncActive;           /*!< Vertical synchronism active duration                               */

+

+  uint32_t VerticalBackPorch;            /*!< Vertical back-porch duration                                       */

+

+  uint32_t VerticalFrontPorch;           /*!< Vertical front-porch duration                                      */

+

+  uint32_t VerticalActive;               /*!< Vertical active duration                                           */

+

+  uint32_t LPCommandEnable;              /*!< Low-power command enable

+                                              This parameter can be any value of @ref DSI_LP_Command             */

+

+  uint32_t LPLargestPacketSize;          /*!< The size, in bytes, of the low power largest packet that

+                                              can fit in a line during VSA, VBP and VFP regions                  */

+

+  uint32_t LPVACTLargestPacketSize;      /*!< The size, in bytes, of the low power largest packet that

+                                              can fit in a line during VACT region                               */

+

+  uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable

+                                              This parameter can be any value of @ref DSI_LP_HFP                 */

+

+  uint32_t LPHorizontalBackPorchEnable;  /*!< Low-power horizontal back-porch enable

+                                              This parameter can be any value of @ref DSI_LP_HBP                 */

+

+  uint32_t LPVerticalActiveEnable;       /*!< Low-power vertical active enable

+                                              This parameter can be any value of @ref DSI_LP_VACT                */

+

+  uint32_t LPVerticalFrontPorchEnable;   /*!< Low-power vertical front-porch enable

+                                              This parameter can be any value of @ref DSI_LP_VFP                 */

+

+  uint32_t LPVerticalBackPorchEnable;    /*!< Low-power vertical back-porch enable

+                                              This parameter can be any value of @ref DSI_LP_VBP                 */

+

+  uint32_t LPVerticalSyncActiveEnable;   /*!< Low-power vertical sync active enable

+                                              This parameter can be any value of @ref DSI_LP_VSYNC               */

+

+  uint32_t FrameBTAAcknowledgeEnable;    /*!< Frame bus-turn-around acknowledge enable

+                                              This parameter can be any value of @ref DSI_FBTA_acknowledge       */

+

+} DSI_VidCfgTypeDef;

+

+/**

+  * @brief  DSI Adapted command mode configuration

+  */

+typedef struct

+{

+  uint32_t VirtualChannelID;             /*!< Virtual channel ID                                                */

+

+  uint32_t ColorCoding;                  /*!< Color coding for LTDC interface

+                                              This parameter can be any value of @ref DSI_Color_Coding          */

+

+  uint32_t CommandSize;                  /*!< Maximum allowed size for an LTDC write memory command, measured in

+                                              pixels. This parameter can be any value between 0x00 and 0xFFFFU   */

+

+  uint32_t TearingEffectSource;          /*!< Tearing effect source

+                                              This parameter can be any value of @ref DSI_TearingEffectSource   */

+

+  uint32_t TearingEffectPolarity;        /*!< Tearing effect pin polarity

+                                              This parameter can be any value of @ref DSI_TearingEffectPolarity */

+

+  uint32_t HSPolarity;                   /*!< HSYNC pin polarity

+                                              This parameter can be any value of @ref DSI_HSYNC_Polarity        */

+

+  uint32_t VSPolarity;                   /*!< VSYNC pin polarity

+                                              This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */

+

+  uint32_t DEPolarity;                   /*!< Data Enable pin polarity

+                                              This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity  */

+

+  uint32_t VSyncPol;                     /*!< VSync edge on which the LTDC is halted

+                                              This parameter can be any value of @ref DSI_Vsync_Polarity        */

+

+  uint32_t AutomaticRefresh;             /*!< Automatic refresh mode

+                                              This parameter can be any value of @ref DSI_AutomaticRefresh      */

+

+  uint32_t TEAcknowledgeRequest;         /*!< Tearing Effect Acknowledge Request Enable

+                                              This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */

+

+} DSI_CmdCfgTypeDef;

+

+/**

+  * @brief  DSI command transmission mode configuration

+  */

+typedef struct

+{

+  uint32_t LPGenShortWriteNoP;           /*!< Generic Short Write Zero parameters Transmission

+                                              This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP  */

+

+  uint32_t LPGenShortWriteOneP;          /*!< Generic Short Write One parameter Transmission

+                                              This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */

+

+  uint32_t LPGenShortWriteTwoP;          /*!< Generic Short Write Two parameters Transmission

+                                              This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */

+

+  uint32_t LPGenShortReadNoP;            /*!< Generic Short Read Zero parameters Transmission

+                                              This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP   */

+

+  uint32_t LPGenShortReadOneP;           /*!< Generic Short Read One parameter Transmission

+                                              This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP  */

+

+  uint32_t LPGenShortReadTwoP;           /*!< Generic Short Read Two parameters Transmission

+                                              This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP  */

+

+  uint32_t LPGenLongWrite;               /*!< Generic Long Write Transmission

+                                              This parameter can be any value of @ref DSI_LP_LPGenLongWrite      */

+

+  uint32_t LPDcsShortWriteNoP;           /*!< DCS Short Write Zero parameters Transmission

+                                              This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP  */

+

+  uint32_t LPDcsShortWriteOneP;          /*!< DCS Short Write One parameter Transmission

+                                              This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */

+

+  uint32_t LPDcsShortReadNoP;            /*!< DCS Short Read Zero parameters Transmission

+                                              This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP   */

+

+  uint32_t LPDcsLongWrite;               /*!< DCS Long Write Transmission

+                                              This parameter can be any value of @ref DSI_LP_LPDcsLongWrite      */

+

+  uint32_t LPMaxReadPacket;              /*!< Maximum Read Packet Size Transmission

+                                              This parameter can be any value of @ref DSI_LP_LPMaxReadPacket     */

+

+  uint32_t AcknowledgeRequest;           /*!< Acknowledge Request Enable

+                                              This parameter can be any value of @ref DSI_AcknowledgeRequest     */

+

+} DSI_LPCmdTypeDef;

+

+/**

+  * @brief  DSI PHY Timings definition

+  */

+typedef struct

+{

+  uint32_t ClockLaneHS2LPTime;           /*!< The maximum time that the D-PHY clock lane takes to go from high-speed

+                                              to low-power transmission                                              */

+

+  uint32_t ClockLaneLP2HSTime;           /*!< The maximum time that the D-PHY clock lane takes to go from low-power

+                                              to high-speed transmission                                             */

+

+  uint32_t DataLaneHS2LPTime;            /*!< The maximum time that the D-PHY data lanes takes to go from high-speed

+                                              to low-power transmission                                              */

+

+  uint32_t DataLaneLP2HSTime;            /*!< The maximum time that the D-PHY data lanes takes to go from low-power

+                                              to high-speed transmission                                             */

+

+  uint32_t DataLaneMaxReadTime;          /*!< The maximum time required to perform a read command */

+

+  uint32_t StopWaitTime;                 /*!< The minimum wait period to request a High-Speed transmission after the

+                                              Stop state                                                             */

+

+} DSI_PHY_TimerTypeDef;

+

+/**

+  * @brief  DSI HOST Timeouts definition

+  */

+typedef struct

+{

+  uint32_t TimeoutCkdiv;                 /*!< Time-out clock division                                  */

+

+  uint32_t HighSpeedTransmissionTimeout; /*!< High-speed transmission time-out                         */

+

+  uint32_t LowPowerReceptionTimeout;     /*!< Low-power reception time-out                             */

+

+  uint32_t HighSpeedReadTimeout;         /*!< High-speed read time-out                                 */

+

+  uint32_t LowPowerReadTimeout;          /*!< Low-power read time-out                                  */

+

+  uint32_t HighSpeedWriteTimeout;        /*!< High-speed write time-out                                */

+

+  uint32_t HighSpeedWritePrespMode;      /*!< High-speed write presp mode

+                                              This parameter can be any value of @ref DSI_HS_PrespMode */

+

+  uint32_t LowPowerWriteTimeout;         /*!< Low-speed write time-out                                 */

+

+  uint32_t BTATimeout;                   /*!< BTA time-out                                             */

+

+} DSI_HOST_TimeoutTypeDef;

+

+/**

+  * @brief  DSI States Structure definition

+  */

+typedef enum

+{

+  HAL_DSI_STATE_RESET   = 0x00U,

+  HAL_DSI_STATE_READY   = 0x01U,

+  HAL_DSI_STATE_ERROR   = 0x02U,

+  HAL_DSI_STATE_BUSY    = 0x03U,

+  HAL_DSI_STATE_TIMEOUT = 0x04U

+} HAL_DSI_StateTypeDef;

+

+/**

+  * @brief  DSI Handle Structure definition

+  */

+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)

+typedef struct __DSI_HandleTypeDef

+#else

+typedef struct

+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */

+{

+  DSI_TypeDef               *Instance;    /*!< Register base address      */

+  DSI_InitTypeDef           Init;         /*!< DSI required parameters    */

+  HAL_LockTypeDef           Lock;         /*!< DSI peripheral status      */

+  __IO HAL_DSI_StateTypeDef State;        /*!< DSI communication state    */

+  __IO uint32_t             ErrorCode;    /*!< DSI Error code             */

+  uint32_t                  ErrorMsk;     /*!< DSI Error monitoring mask  */

+

+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)

+  void (* TearingEffectCallback)(struct __DSI_HandleTypeDef *hdsi);   /*!< DSI Tearing Effect Callback */

+  void (* EndOfRefreshCallback)(struct __DSI_HandleTypeDef *hdsi);    /*!< DSI End Of Refresh Callback */

+  void (* ErrorCallback)(struct __DSI_HandleTypeDef *hdsi);           /*!< DSI Error Callback          */

+

+  void (* MspInitCallback)(struct __DSI_HandleTypeDef *hdsi);         /*!< DSI Msp Init callback       */

+  void (* MspDeInitCallback)(struct __DSI_HandleTypeDef *hdsi);       /*!< DSI Msp DeInit callback     */

+

+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */

+

+} DSI_HandleTypeDef;

+

+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  HAL DSI Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_DSI_MSPINIT_CB_ID            = 0x00U,    /*!< DSI MspInit callback ID        */

+  HAL_DSI_MSPDEINIT_CB_ID          = 0x01U,    /*!< DSI MspDeInit callback ID      */

+

+  HAL_DSI_TEARING_EFFECT_CB_ID     = 0x02U,    /*!< DSI Tearing Effect Callback ID */

+  HAL_DSI_ENDOF_REFRESH_CB_ID      = 0x03U,    /*!< DSI End Of Refresh Callback ID */

+  HAL_DSI_ERROR_CB_ID              = 0x04U     /*!< DSI Error Callback ID          */

+

+} HAL_DSI_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL DSI Callback pointer definition

+  */

+typedef  void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef *hdsi);  /*!< pointer to an DSI callback function */

+

+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup DSI_Exported_Constants DSI Exported Constants

+  * @{

+  */

+/** @defgroup DSI_DCS_Command DSI DCS Command

+  * @{

+  */

+#define DSI_ENTER_IDLE_MODE       0x39U

+#define DSI_ENTER_INVERT_MODE     0x21U

+#define DSI_ENTER_NORMAL_MODE     0x13U

+#define DSI_ENTER_PARTIAL_MODE    0x12U

+#define DSI_ENTER_SLEEP_MODE      0x10U

+#define DSI_EXIT_IDLE_MODE        0x38U

+#define DSI_EXIT_INVERT_MODE      0x20U

+#define DSI_EXIT_SLEEP_MODE       0x11U

+#define DSI_GET_3D_CONTROL        0x3FU

+#define DSI_GET_ADDRESS_MODE      0x0BU

+#define DSI_GET_BLUE_CHANNEL      0x08U

+#define DSI_GET_DIAGNOSTIC_RESULT 0x0FU

+#define DSI_GET_DISPLAY_MODE      0x0DU

+#define DSI_GET_GREEN_CHANNEL     0x07U

+#define DSI_GET_PIXEL_FORMAT      0x0CU

+#define DSI_GET_POWER_MODE        0x0AU

+#define DSI_GET_RED_CHANNEL       0x06U

+#define DSI_GET_SCANLINE          0x45U

+#define DSI_GET_SIGNAL_MODE       0x0EU

+#define DSI_NOP                   0x00U

+#define DSI_READ_DDB_CONTINUE     0xA8U

+#define DSI_READ_DDB_START        0xA1U

+#define DSI_READ_MEMORY_CONTINUE  0x3EU

+#define DSI_READ_MEMORY_START     0x2EU

+#define DSI_SET_3D_CONTROL        0x3DU

+#define DSI_SET_ADDRESS_MODE      0x36U

+#define DSI_SET_COLUMN_ADDRESS    0x2AU

+#define DSI_SET_DISPLAY_OFF       0x28U

+#define DSI_SET_DISPLAY_ON        0x29U

+#define DSI_SET_GAMMA_CURVE       0x26U

+#define DSI_SET_PAGE_ADDRESS      0x2BU

+#define DSI_SET_PARTIAL_COLUMNS   0x31U

+#define DSI_SET_PARTIAL_ROWS      0x30U

+#define DSI_SET_PIXEL_FORMAT      0x3AU

+#define DSI_SET_SCROLL_AREA       0x33U

+#define DSI_SET_SCROLL_START      0x37U

+#define DSI_SET_TEAR_OFF          0x34U

+#define DSI_SET_TEAR_ON           0x35U

+#define DSI_SET_TEAR_SCANLINE     0x44U

+#define DSI_SET_VSYNC_TIMING      0x40U

+#define DSI_SOFT_RESET            0x01U

+#define DSI_WRITE_LUT             0x2DU

+#define DSI_WRITE_MEMORY_CONTINUE 0x3CU

+#define DSI_WRITE_MEMORY_START    0x2CU

+/**

+  * @}

+  */

+

+/** @defgroup DSI_Video_Mode_Type DSI Video Mode Type

+  * @{

+  */

+#define DSI_VID_MODE_NB_PULSES    0U

+#define DSI_VID_MODE_NB_EVENTS    1U

+#define DSI_VID_MODE_BURST        2U

+/**

+  * @}

+  */

+

+/** @defgroup DSI_Color_Mode DSI Color Mode

+  * @{

+  */

+#define DSI_COLOR_MODE_FULL       0x00000000U

+#define DSI_COLOR_MODE_EIGHT      DSI_WCR_COLM

+/**

+  * @}

+  */

+

+/** @defgroup DSI_ShutDown DSI ShutDown

+  * @{

+  */

+#define DSI_DISPLAY_ON            0x00000000U

+#define DSI_DISPLAY_OFF           DSI_WCR_SHTDN

+/**

+  * @}

+  */

+

+/** @defgroup DSI_LP_Command DSI LP Command

+  * @{

+  */

+#define DSI_LP_COMMAND_DISABLE    0x00000000U

+#define DSI_LP_COMMAND_ENABLE     DSI_VMCR_LPCE

+/**

+  * @}

+  */

+

+/** @defgroup DSI_LP_HFP DSI LP HFP

+  * @{

+  */

+#define DSI_LP_HFP_DISABLE        0x00000000U

+#define DSI_LP_HFP_ENABLE         DSI_VMCR_LPHFPE

+/**

+  * @}

+  */

+

+/** @defgroup DSI_LP_HBP DSI LP HBP

+  * @{

+  */

+#define DSI_LP_HBP_DISABLE        0x00000000U

+#define DSI_LP_HBP_ENABLE         DSI_VMCR_LPHBPE

+/**

+  * @}

+  */

+

+/** @defgroup DSI_LP_VACT DSI LP VACT

+  * @{

+  */

+#define DSI_LP_VACT_DISABLE       0x00000000U

+#define DSI_LP_VACT_ENABLE        DSI_VMCR_LPVAE

+/**

+  * @}

+  */

+

+/** @defgroup DSI_LP_VFP DSI LP VFP

+  * @{

+  */

+#define DSI_LP_VFP_DISABLE       0x00000000U

+#define DSI_LP_VFP_ENABLE        DSI_VMCR_LPVFPE

+/**

+  * @}

+  */

+

+/** @defgroup DSI_LP_VBP DSI LP VBP

+  * @{

+  */

+#define DSI_LP_VBP_DISABLE       0x00000000U

+#define DSI_LP_VBP_ENABLE        DSI_VMCR_LPVBPE

+/**

+  * @}

+  */

+

+/** @defgroup DSI_LP_VSYNC DSI LP VSYNC

+  * @{

+  */

+#define DSI_LP_VSYNC_DISABLE     0x00000000U

+#define DSI_LP_VSYNC_ENABLE      DSI_VMCR_LPVSAE

+/**

+  * @}

+  */

+

+/** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge

+  * @{

+  */

+#define DSI_FBTAA_DISABLE        0x00000000U

+#define DSI_FBTAA_ENABLE         DSI_VMCR_FBTAAE

+/**

+  * @}

+  */

+

+/** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source

+  * @{

+  */

+#define DSI_TE_DSILINK           0x00000000U

+#define DSI_TE_EXTERNAL          DSI_WCFGR_TESRC

+/**

+  * @}

+  */

+

+/** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity

+  * @{

+  */

+#define DSI_TE_RISING_EDGE       0x00000000U

+#define DSI_TE_FALLING_EDGE      DSI_WCFGR_TEPOL

+/**

+  * @}

+  */

+

+/** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity

+  * @{

+  */

+#define DSI_VSYNC_FALLING        0x00000000U

+#define DSI_VSYNC_RISING         DSI_WCFGR_VSPOL

+/**

+  * @}

+  */

+

+/** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh

+  * @{

+  */

+#define DSI_AR_DISABLE           0x00000000U

+#define DSI_AR_ENABLE            DSI_WCFGR_AR

+/**

+  * @}

+  */

+

+/** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request

+  * @{

+  */

+#define DSI_TE_ACKNOWLEDGE_DISABLE 0x00000000U

+#define DSI_TE_ACKNOWLEDGE_ENABLE  DSI_CMCR_TEARE

+/**

+  * @}

+  */

+

+/** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request

+  * @{

+  */

+#define DSI_ACKNOWLEDGE_DISABLE   0x00000000U

+#define DSI_ACKNOWLEDGE_ENABLE    DSI_CMCR_ARE

+/**

+  * @}

+  */

+

+/** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP

+  * @{

+  */

+#define DSI_LP_GSW0P_DISABLE     0x00000000U

+#define DSI_LP_GSW0P_ENABLE      DSI_CMCR_GSW0TX

+/**

+  * @}

+  */

+

+/** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP

+  * @{

+  */

+#define DSI_LP_GSW1P_DISABLE     0x00000000U

+#define DSI_LP_GSW1P_ENABLE      DSI_CMCR_GSW1TX

+/**

+  * @}

+  */

+

+/** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP

+  * @{

+  */

+#define DSI_LP_GSW2P_DISABLE     0x00000000U

+#define DSI_LP_GSW2P_ENABLE      DSI_CMCR_GSW2TX

+/**

+  * @}

+  */

+

+/** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP

+  * @{

+  */

+#define DSI_LP_GSR0P_DISABLE     0x00000000U

+#define DSI_LP_GSR0P_ENABLE      DSI_CMCR_GSR0TX

+/**

+  * @}

+  */

+

+/** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP

+  * @{

+  */

+#define DSI_LP_GSR1P_DISABLE     0x00000000U

+#define DSI_LP_GSR1P_ENABLE      DSI_CMCR_GSR1TX

+/**

+  * @}

+  */

+

+/** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP

+  * @{

+  */

+#define DSI_LP_GSR2P_DISABLE     0x00000000U

+#define DSI_LP_GSR2P_ENABLE      DSI_CMCR_GSR2TX

+/**

+  * @}

+  */

+

+/** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite

+  * @{

+  */

+#define DSI_LP_GLW_DISABLE       0x00000000U

+#define DSI_LP_GLW_ENABLE        DSI_CMCR_GLWTX

+/**

+  * @}

+  */

+

+/** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP

+  * @{

+  */

+#define DSI_LP_DSW0P_DISABLE     0x00000000U

+#define DSI_LP_DSW0P_ENABLE      DSI_CMCR_DSW0TX

+/**

+  * @}

+  */

+

+/** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP

+  * @{

+  */

+#define DSI_LP_DSW1P_DISABLE     0x00000000U

+#define DSI_LP_DSW1P_ENABLE      DSI_CMCR_DSW1TX

+/**

+  * @}

+  */

+

+/** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP

+  * @{

+  */

+#define DSI_LP_DSR0P_DISABLE     0x00000000U

+#define DSI_LP_DSR0P_ENABLE      DSI_CMCR_DSR0TX

+/**

+  * @}

+  */

+

+/** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write

+  * @{

+  */

+#define DSI_LP_DLW_DISABLE       0x00000000U

+#define DSI_LP_DLW_ENABLE        DSI_CMCR_DLWTX

+/**

+  * @}

+  */

+

+/** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet

+  * @{

+  */

+#define DSI_LP_MRDP_DISABLE      0x00000000U

+#define DSI_LP_MRDP_ENABLE       DSI_CMCR_MRDPS

+/**

+  * @}

+  */

+

+/** @defgroup DSI_HS_PrespMode DSI HS Presp Mode

+  * @{

+  */

+#define DSI_HS_PM_DISABLE        0x00000000U

+#define DSI_HS_PM_ENABLE         DSI_TCCR3_PM

+/**

+  * @}

+  */

+

+

+/** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control

+  * @{

+  */

+#define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0x00000000U

+#define DSI_AUTO_CLK_LANE_CTRL_ENABLE  DSI_CLCR_ACR

+/**

+  * @}

+  */

+

+/** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes

+  * @{

+  */

+#define DSI_ONE_DATA_LANE          0U

+#define DSI_TWO_DATA_LANES         1U

+/**

+  * @}

+  */

+

+/** @defgroup DSI_FlowControl DSI Flow Control

+  * @{

+  */

+#define DSI_FLOW_CONTROL_CRC_RX    DSI_PCR_CRCRXE

+#define DSI_FLOW_CONTROL_ECC_RX    DSI_PCR_ECCRXE

+#define DSI_FLOW_CONTROL_BTA       DSI_PCR_BTAE

+#define DSI_FLOW_CONTROL_EOTP_RX   DSI_PCR_ETRXE

+#define DSI_FLOW_CONTROL_EOTP_TX   DSI_PCR_ETTXE

+#define DSI_FLOW_CONTROL_ALL       (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \

+                                    DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \

+                                    DSI_FLOW_CONTROL_EOTP_TX)

+/**

+  * @}

+  */

+

+/** @defgroup DSI_Color_Coding DSI Color Coding

+  * @{

+  */

+#define DSI_RGB565                 0x00000000U /*!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration */

+#define DSI_RGB666                 0x00000003U /*!< The value 0x00000004 can also be used for the RGB666 color mode configuration                 */

+#define DSI_RGB888                 0x00000005U

+/**

+  * @}

+  */

+

+/** @defgroup DSI_LooselyPacked DSI Loosely Packed

+  * @{

+  */

+#define DSI_LOOSELY_PACKED_ENABLE  DSI_LCOLCR_LPE

+#define DSI_LOOSELY_PACKED_DISABLE 0x00000000U

+/**

+  * @}

+  */

+

+/** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity

+  * @{

+  */

+#define DSI_HSYNC_ACTIVE_HIGH       0x00000000U

+#define DSI_HSYNC_ACTIVE_LOW        DSI_LPCR_HSP

+/**

+  * @}

+  */

+

+/** @defgroup DSI_VSYNC_Active_Polarity DSI VSYNC Active Polarity

+  * @{

+  */

+#define DSI_VSYNC_ACTIVE_HIGH       0x00000000U

+#define DSI_VSYNC_ACTIVE_LOW        DSI_LPCR_VSP

+/**

+  * @}

+  */

+

+/** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity

+  * @{

+  */

+#define DSI_DATA_ENABLE_ACTIVE_HIGH 0x00000000U

+#define DSI_DATA_ENABLE_ACTIVE_LOW  DSI_LPCR_DEP

+/**

+  * @}

+  */

+

+/** @defgroup DSI_PLL_IDF DSI PLL IDF

+  * @{

+  */

+#define DSI_PLL_IN_DIV1             0x00000001U

+#define DSI_PLL_IN_DIV2             0x00000002U

+#define DSI_PLL_IN_DIV3             0x00000003U

+#define DSI_PLL_IN_DIV4             0x00000004U

+#define DSI_PLL_IN_DIV5             0x00000005U

+#define DSI_PLL_IN_DIV6             0x00000006U

+#define DSI_PLL_IN_DIV7             0x00000007U

+/**

+  * @}

+  */

+

+/** @defgroup DSI_PLL_ODF DSI PLL ODF

+  * @{

+  */

+#define DSI_PLL_OUT_DIV1            0x00000000U

+#define DSI_PLL_OUT_DIV2            0x00000001U

+#define DSI_PLL_OUT_DIV4            0x00000002U

+#define DSI_PLL_OUT_DIV8            0x00000003U

+/**

+  * @}

+  */

+

+/** @defgroup DSI_Flags DSI Flags

+  * @{

+  */

+#define DSI_FLAG_TE                 DSI_WISR_TEIF

+#define DSI_FLAG_ER                 DSI_WISR_ERIF

+#define DSI_FLAG_BUSY               DSI_WISR_BUSY

+#define DSI_FLAG_PLLLS              DSI_WISR_PLLLS

+#define DSI_FLAG_PLLL               DSI_WISR_PLLLIF

+#define DSI_FLAG_PLLU               DSI_WISR_PLLUIF

+#define DSI_FLAG_RRS                DSI_WISR_RRS

+#define DSI_FLAG_RR                 DSI_WISR_RRIF

+/**

+  * @}

+  */

+

+/** @defgroup DSI_Interrupts DSI Interrupts

+  * @{

+  */

+#define DSI_IT_TE                   DSI_WIER_TEIE

+#define DSI_IT_ER                   DSI_WIER_ERIE

+#define DSI_IT_PLLL                 DSI_WIER_PLLLIE

+#define DSI_IT_PLLU                 DSI_WIER_PLLUIE

+#define DSI_IT_RR                   DSI_WIER_RRIE

+/**

+  * @}

+  */

+

+/** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type

+  * @{

+  */

+#define DSI_DCS_SHORT_PKT_WRITE_P0  0x00000005U /*!< DCS short write, no parameters      */

+#define DSI_DCS_SHORT_PKT_WRITE_P1  0x00000015U /*!< DCS short write, one parameter      */

+#define DSI_GEN_SHORT_PKT_WRITE_P0  0x00000003U /*!< Generic short write, no parameters  */

+#define DSI_GEN_SHORT_PKT_WRITE_P1  0x00000013U /*!< Generic short write, one parameter  */

+#define DSI_GEN_SHORT_PKT_WRITE_P2  0x00000023U /*!< Generic short write, two parameters */

+/**

+  * @}

+  */

+

+/** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type

+  * @{

+  */

+#define DSI_DCS_LONG_PKT_WRITE      0x00000039U /*!< DCS long write     */

+#define DSI_GEN_LONG_PKT_WRITE      0x00000029U /*!< Generic long write */

+/**

+  * @}

+  */

+

+/** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type

+  * @{

+  */

+#define DSI_DCS_SHORT_PKT_READ      0x00000006U /*!< DCS short read                     */

+#define DSI_GEN_SHORT_PKT_READ_P0   0x00000004U /*!< Generic short read, no parameters  */

+#define DSI_GEN_SHORT_PKT_READ_P1   0x00000014U /*!< Generic short read, one parameter  */

+#define DSI_GEN_SHORT_PKT_READ_P2   0x00000024U /*!< Generic short read, two parameters */

+/**

+  * @}

+  */

+

+/** @defgroup DSI_Error_Data_Type DSI Error Data Type

+  * @{

+  */

+#define HAL_DSI_ERROR_NONE              0U

+#define HAL_DSI_ERROR_ACK               0x00000001U /*!< acknowledge errors          */

+#define HAL_DSI_ERROR_PHY               0x00000002U /*!< PHY related errors          */

+#define HAL_DSI_ERROR_TX                0x00000004U /*!< transmission error          */

+#define HAL_DSI_ERROR_RX                0x00000008U /*!< reception error             */

+#define HAL_DSI_ERROR_ECC               0x00000010U /*!< ECC errors                  */

+#define HAL_DSI_ERROR_CRC               0x00000020U /*!< CRC error                   */

+#define HAL_DSI_ERROR_PSE               0x00000040U /*!< Packet Size error           */

+#define HAL_DSI_ERROR_EOT               0x00000080U /*!< End Of Transmission error   */

+#define HAL_DSI_ERROR_OVF               0x00000100U /*!< FIFO overflow error         */

+#define HAL_DSI_ERROR_GEN               0x00000200U /*!< Generic FIFO related errors */

+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)

+#define HAL_DSI_ERROR_INVALID_CALLBACK  0x00000400U /*!< DSI Invalid Callback error  */

+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/** @defgroup DSI_Lane_Group DSI Lane Group

+  * @{

+  */

+#define DSI_CLOCK_LANE              0x00000000U

+#define DSI_DATA_LANES              0x00000001U

+/**

+  * @}

+  */

+

+/** @defgroup DSI_Communication_Delay DSI Communication Delay

+  * @{

+  */

+#define DSI_SLEW_RATE_HSTX          0x00000000U

+#define DSI_SLEW_RATE_LPTX          0x00000001U

+#define DSI_HS_DELAY                0x00000002U

+/**

+  * @}

+  */

+

+/** @defgroup DSI_CustomLane DSI CustomLane

+  * @{

+  */

+#define DSI_SWAP_LANE_PINS          0x00000000U

+#define DSI_INVERT_HS_SIGNAL        0x00000001U

+/**

+  * @}

+  */

+

+/** @defgroup DSI_Lane_Select DSI Lane Select

+  * @{

+  */

+#define DSI_CLK_LANE                0x00000000U

+#define DSI_DATA_LANE0              0x00000001U

+#define DSI_DATA_LANE1              0x00000002U

+/**

+  * @}

+  */

+

+/** @defgroup DSI_PHY_Timing DSI PHY Timing

+  * @{

+  */

+#define DSI_TCLK_POST               0x00000000U

+#define DSI_TLPX_CLK                0x00000001U

+#define DSI_THS_EXIT                0x00000002U

+#define DSI_TLPX_DATA               0x00000003U

+#define DSI_THS_ZERO                0x00000004U

+#define DSI_THS_TRAIL               0x00000005U

+#define DSI_THS_PREPARE             0x00000006U

+#define DSI_TCLK_ZERO               0x00000007U

+#define DSI_TCLK_PREPARE            0x00000008U

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macros -----------------------------------------------------------*/

+/** @defgroup DSI_Exported_Macros DSI Exported Macros

+  * @{

+  */

+

+/**

+  * @brief Reset DSI handle state.

+  * @param  __HANDLE__: DSI handle

+  * @retval None

+  */

+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)

+#define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) do{                                               \

+                                                     (__HANDLE__)->State = HAL_DSI_STATE_RESET;    \

+                                                     (__HANDLE__)->MspInitCallback = NULL;         \

+                                                     (__HANDLE__)->MspDeInitCallback = NULL;       \

+                                                   } while(0)

+#else

+#define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DSI_STATE_RESET)

+#endif /*USE_HAL_DSI_REGISTER_CALLBACKS */

+

+/**

+  * @brief  Enables the DSI host.

+  * @param  __HANDLE__  DSI handle

+  * @retval None.

+  */

+#define __HAL_DSI_ENABLE(__HANDLE__) do { \

+                                          __IO uint32_t tmpreg = 0x00U; \

+                                          SET_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\

+                                          /* Delay after an DSI Host enabling */ \

+                                          tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\

+                                          UNUSED(tmpreg); \

+                                        } while(0U)

+

+/**

+  * @brief  Disables the DSI host.

+  * @param  __HANDLE__  DSI handle

+  * @retval None.

+  */

+#define __HAL_DSI_DISABLE(__HANDLE__) do { \

+                                          __IO uint32_t tmpreg = 0x00U; \

+                                          CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\

+                                          /* Delay after an DSI Host disabling */ \

+                                          tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\

+                                          UNUSED(tmpreg); \

+                                         } while(0U)

+

+/**

+  * @brief  Enables the DSI wrapper.

+  * @param  __HANDLE__  DSI handle

+  * @retval None.

+  */

+#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \

+                                                 __IO uint32_t tmpreg = 0x00U; \

+                                                 SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\

+                                                 /* Delay after an DSI warpper enabling */ \

+                                                 tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\

+                                                 UNUSED(tmpreg); \

+                                                } while(0U)

+

+/**

+  * @brief  Disable the DSI wrapper.

+  * @param  __HANDLE__  DSI handle

+  * @retval None.

+  */

+#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \

+                                                  __IO uint32_t tmpreg = 0x00U; \

+                                                  CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\

+                                                  /* Delay after an DSI warpper disabling*/ \

+                                                  tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\

+                                                  UNUSED(tmpreg); \

+                                                 } while(0U)

+

+/**

+  * @brief  Enables the DSI PLL.

+  * @param  __HANDLE__  DSI handle

+  * @retval None.

+  */

+#define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \

+                                             __IO uint32_t tmpreg = 0x00U; \

+                                             SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\

+                                             /* Delay after an DSI PLL enabling */ \

+                                             tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\

+                                             UNUSED(tmpreg); \

+                                            } while(0U)

+

+/**

+  * @brief  Disables the DSI PLL.

+  * @param  __HANDLE__  DSI handle

+  * @retval None.

+  */

+#define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \

+                                              __IO uint32_t tmpreg = 0x00U; \

+                                              CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\

+                                              /* Delay after an DSI PLL disabling */ \

+                                              tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\

+                                              UNUSED(tmpreg); \

+                                             } while(0U)

+

+/**

+  * @brief  Enables the DSI regulator.

+  * @param  __HANDLE__  DSI handle

+  * @retval None.

+  */

+#define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \

+                                              __IO uint32_t tmpreg = 0x00U; \

+                                              SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\

+                                              /* Delay after an DSI regulator enabling */ \

+                                              tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\

+                                              UNUSED(tmpreg); \

+                                            } while(0U)

+

+/**

+  * @brief  Disables the DSI regulator.

+  * @param  __HANDLE__  DSI handle

+  * @retval None.

+  */

+#define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \

+                                              __IO uint32_t tmpreg = 0x00U; \

+                                              CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\

+                                              /* Delay after an DSI regulator disabling */ \

+                                              tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\

+                                              UNUSED(tmpreg); \

+                                             } while(0U)

+

+/**

+  * @brief  Get the DSI pending flags.

+  * @param  __HANDLE__  DSI handle.

+  * @param  __FLAG__  Get the specified flag.

+  *          This parameter can be any combination of the following values:

+  *            @arg DSI_FLAG_TE   : Tearing Effect Interrupt Flag

+  *            @arg DSI_FLAG_ER   : End of Refresh Interrupt Flag

+  *            @arg DSI_FLAG_BUSY : Busy Flag

+  *            @arg DSI_FLAG_PLLLS: PLL Lock Status

+  *            @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag

+  *            @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag

+  *            @arg DSI_FLAG_RRS  : Regulator Ready Flag

+  *            @arg DSI_FLAG_RR   : Regulator Ready Interrupt Flag

+  * @retval The state of FLAG (SET or RESET).

+  */

+#define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__))

+

+/**

+  * @brief  Clears the DSI pending flags.

+  * @param  __HANDLE__  DSI handle.

+  * @param  __FLAG__  specifies the flag to clear.

+  *          This parameter can be any combination of the following values:

+  *            @arg DSI_FLAG_TE   : Tearing Effect Interrupt Flag

+  *            @arg DSI_FLAG_ER   : End of Refresh Interrupt Flag

+  *            @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag

+  *            @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag

+  *            @arg DSI_FLAG_RR   : Regulator Ready Interrupt Flag

+  * @retval None

+  */

+#define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__))

+

+/**

+  * @brief  Enables the specified DSI interrupts.

+  * @param  __HANDLE__  DSI handle.

+  * @param __INTERRUPT__  specifies the DSI interrupt sources to be enabled.

+  *          This parameter can be any combination of the following values:

+  *            @arg DSI_IT_TE  : Tearing Effect Interrupt

+  *            @arg DSI_IT_ER  : End of Refresh Interrupt

+  *            @arg DSI_IT_PLLL: PLL Lock Interrupt

+  *            @arg DSI_IT_PLLU: PLL Unlock Interrupt

+  *            @arg DSI_IT_RR  : Regulator Ready Interrupt

+  * @retval None

+  */

+#define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER |= (__INTERRUPT__))

+

+/**

+  * @brief  Disables the specified DSI interrupts.

+  * @param  __HANDLE__  DSI handle

+  * @param __INTERRUPT__  specifies the DSI interrupt sources to be disabled.

+  *          This parameter can be any combination of the following values:

+  *            @arg DSI_IT_TE  : Tearing Effect Interrupt

+  *            @arg DSI_IT_ER  : End of Refresh Interrupt

+  *            @arg DSI_IT_PLLL: PLL Lock Interrupt

+  *            @arg DSI_IT_PLLU: PLL Unlock Interrupt

+  *            @arg DSI_IT_RR  : Regulator Ready Interrupt

+  * @retval None

+  */

+#define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__))

+

+/**

+  * @brief  Checks whether the specified DSI interrupt source is enabled or not.

+  * @param  __HANDLE__  DSI handle

+  * @param  __INTERRUPT__  specifies the DSI interrupt source to check.

+  *          This parameter can be one of the following values:

+  *            @arg DSI_IT_TE  : Tearing Effect Interrupt

+  *            @arg DSI_IT_ER  : End of Refresh Interrupt

+  *            @arg DSI_IT_PLLL: PLL Lock Interrupt

+  *            @arg DSI_IT_PLLU: PLL Unlock Interrupt

+  *            @arg DSI_IT_RR  : Regulator Ready Interrupt

+  * @retval The state of INTERRUPT (SET or RESET).

+  */

+#define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__))

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup DSI_Exported_Functions DSI Exported Functions

+  * @{

+  */

+HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit);

+HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi);

+void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi);

+void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi);

+

+void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi);

+void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi);

+void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi);

+void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi);

+

+/* Callbacks Register/UnRegister functions  ***********************************/

+#if (USE_HAL_DSI_REGISTER_CALLBACKS == 1)

+HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID,

+                                           pDSI_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID);

+#endif /* USE_HAL_DSI_REGISTER_CALLBACKS */

+

+HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID);

+HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg);

+HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg);

+HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd);

+HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl);

+HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers);

+HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts);

+HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi);

+HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi);

+HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi);

+HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode);

+HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown);

+HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,

+                                     uint32_t ChannelID,

+                                     uint32_t Mode,

+                                     uint32_t Param1,

+                                     uint32_t Param2);

+HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,

+                                    uint32_t ChannelID,

+                                    uint32_t Mode,

+                                    uint32_t NbParams,

+                                    uint32_t Param1,

+                                    uint8_t *ParametersTable);

+HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,

+                               uint32_t ChannelNbr,

+                               uint8_t *Array,

+                               uint32_t Size,

+                               uint32_t Mode,

+                               uint32_t DCSCmd,

+                               uint8_t *ParametersTable);

+HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi);

+HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi);

+HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi);

+HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi);

+

+HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation);

+HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi);

+

+HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane,

+                                                    uint32_t Value);

+HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency);

+HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State);

+HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane,

+                                                   FunctionalState State);

+HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State,

+                                        uint32_t Value);

+HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State);

+HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State);

+HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State);

+HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State);

+HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State);

+

+uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi);

+HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors);

+HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi);

+/**

+  * @}

+  */

+

+/* Private types -------------------------------------------------------------*/

+/** @defgroup DSI_Private_Types DSI Private Types

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private defines -----------------------------------------------------------*/

+/** @defgroup DSI_Private_Defines DSI Private Defines

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private variables ---------------------------------------------------------*/

+/** @defgroup DSI_Private_Variables DSI Private Variables

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup DSI_Private_Constants DSI Private Constants

+  * @{

+  */

+#define DSI_MAX_RETURN_PKT_SIZE (0x00000037U) /*!< Maximum return packet configuration */

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup DSI_Private_Macros DSI Private Macros

+  * @{

+  */

+#define IS_DSI_PLL_NDIV(NDIV)                       ((10U <= (NDIV)) && ((NDIV) <= 125U))

+#define IS_DSI_PLL_IDF(IDF)                         (((IDF) == DSI_PLL_IN_DIV1) || \

+                                                     ((IDF) == DSI_PLL_IN_DIV2) || \

+                                                     ((IDF) == DSI_PLL_IN_DIV3) || \

+                                                     ((IDF) == DSI_PLL_IN_DIV4) || \

+                                                     ((IDF) == DSI_PLL_IN_DIV5) || \

+                                                     ((IDF) == DSI_PLL_IN_DIV6) || \

+                                                     ((IDF) == DSI_PLL_IN_DIV7))

+#define IS_DSI_PLL_ODF(ODF)                         (((ODF) == DSI_PLL_OUT_DIV1) || \

+                                                     ((ODF) == DSI_PLL_OUT_DIV2) || \

+                                                     ((ODF) == DSI_PLL_OUT_DIV4) || \

+                                                     ((ODF) == DSI_PLL_OUT_DIV8))

+#define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane)    (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE))

+#define IS_DSI_NUMBER_OF_LANES(NumberOfLanes)       (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES))

+#define IS_DSI_FLOW_CONTROL(FlowControl)            (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL)

+#define IS_DSI_COLOR_CODING(ColorCoding)            ((ColorCoding) <= 5U)

+#define IS_DSI_LOOSELY_PACKED(LooselyPacked)        (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE))

+#define IS_DSI_DE_POLARITY(DataEnable)              (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW))

+#define IS_DSI_VSYNC_POLARITY(VSYNC)                (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW))

+#define IS_DSI_HSYNC_POLARITY(HSYNC)                (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW))

+#define IS_DSI_VIDEO_MODE_TYPE(VideoModeType)       (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \

+                                                     ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \

+                                                     ((VideoModeType) == DSI_VID_MODE_BURST))

+#define IS_DSI_COLOR_MODE(ColorMode)                (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT))

+#define IS_DSI_SHUT_DOWN(ShutDown)                  (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF))

+#define IS_DSI_LP_COMMAND(LPCommand)                (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE))

+#define IS_DSI_LP_HFP(LPHFP)                        (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE))

+#define IS_DSI_LP_HBP(LPHBP)                        (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE))

+#define IS_DSI_LP_VACTIVE(LPVActive)                (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE))

+#define IS_DSI_LP_VFP(LPVFP)                        (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE))

+#define IS_DSI_LP_VBP(LPVBP)                        (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE))

+#define IS_DSI_LP_VSYNC(LPVSYNC)                    (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE))

+#define IS_DSI_FBTAA(FrameBTAAcknowledge)           (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE))

+#define IS_DSI_TE_SOURCE(TESource)                  (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL))

+#define IS_DSI_TE_POLARITY(TEPolarity)              (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE))

+#define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh)  (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE))

+#define IS_DSI_VS_POLARITY(VSPolarity)              (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING))

+#define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE))

+#define IS_DSI_ACK_REQUEST(AcknowledgeRequest)      (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE))

+#define IS_DSI_LP_GSW0P(LP_GSW0P)                   (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE))

+#define IS_DSI_LP_GSW1P(LP_GSW1P)                   (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE))

+#define IS_DSI_LP_GSW2P(LP_GSW2P)                   (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE))

+#define IS_DSI_LP_GSR0P(LP_GSR0P)                   (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE))

+#define IS_DSI_LP_GSR1P(LP_GSR1P)                   (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE))

+#define IS_DSI_LP_GSR2P(LP_GSR2P)                   (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE))

+#define IS_DSI_LP_GLW(LP_GLW)                       (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE))

+#define IS_DSI_LP_DSW0P(LP_DSW0P)                   (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE))

+#define IS_DSI_LP_DSW1P(LP_DSW1P)                   (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE))

+#define IS_DSI_LP_DSR0P(LP_DSR0P)                   (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE))

+#define IS_DSI_LP_DLW(LP_DLW)                       (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE))

+#define IS_DSI_LP_MRDP(LP_MRDP)                     (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE))

+#define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE)        (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \

+                                                     ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \

+                                                     ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \

+                                                     ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \

+                                                     ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2))

+#define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE)         (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \

+                                                     ((MODE) == DSI_GEN_LONG_PKT_WRITE))

+#define IS_DSI_READ_PACKET_TYPE(MODE)               (((MODE) == DSI_DCS_SHORT_PKT_READ) || \

+                                                     ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \

+                                                     ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \

+                                                     ((MODE) == DSI_GEN_SHORT_PKT_READ_P2))

+#define IS_DSI_COMMUNICATION_DELAY(CommDelay)       (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY))

+#define IS_DSI_LANE_GROUP(Lane)                     (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES))

+#define IS_DSI_CUSTOM_LANE(CustomLane)              (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL))

+#define IS_DSI_LANE(Lane)                           (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1))

+#define IS_DSI_PHY_TIMING(Timing)                   (((Timing) == DSI_TCLK_POST   ) || \

+                                                     ((Timing) == DSI_TLPX_CLK    ) || \

+                                                     ((Timing) == DSI_THS_EXIT    ) || \

+                                                     ((Timing) == DSI_TLPX_DATA   ) || \

+                                                     ((Timing) == DSI_THS_ZERO    ) || \

+                                                     ((Timing) == DSI_THS_TRAIL   ) || \

+                                                     ((Timing) == DSI_THS_PREPARE ) || \

+                                                     ((Timing) == DSI_TCLK_ZERO   ) || \

+                                                     ((Timing) == DSI_TCLK_PREPARE))

+

+/**

+  * @}

+  */

+

+/* Private functions prototypes ----------------------------------------------*/

+/** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private functions ---------------------------------------------------------*/

+/** @defgroup DSI_Private_Functions DSI Private Functions

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+#endif /* DSI */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_DSI_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_dts.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_dts.h
new file mode 100644
index 0000000000..3aec6cbe0f
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_dts.h
@@ -0,0 +1,483 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_dts.h

+  * @author  MCD Application Team

+  * @brief   Header file of DTS HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef __STM32H7xx_HAL_DTS_H

+#define __STM32H7xx_HAL_DTS_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+#if defined(DTS)

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup DTS

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup DTS_Exported_Types DTS Exported Types

+  * @{

+  */

+

+/**

+  * @brief  DTS Init structure definition

+  */

+typedef struct

+{

+  uint32_t QuickMeasure;  /*!< Specifies the quick measure option selection of the DTS sensor.

+                               This parameter can be a value of @ref DTS_Quick_Measurement */

+

+  uint32_t RefClock;      /*!< Specifies the reference clock selection of the DTS sensor.

+                               This parameter can be a value of @ref DTS_Reference_Clock_Selection */

+

+  uint32_t TriggerInput;  /*!< Specifies the trigger input of the DTS sensor.

+                               This parameter can be a value of @ref DTS_TriggerConfig */

+

+  uint32_t SamplingTime;  /*!< Specifies the sampling time configuration.

+                               This parameter can be a value of @ref DTS_Sampling_Time */

+

+  uint32_t Divider;       /*!< Specifies the high speed clock divider ratio.

+                               This parameter can be a value from 0 to 127 */

+

+  uint32_t HighThreshold;  /*!< Specifies the high threshold of the DTS sensor */

+

+  uint32_t LowThreshold;   /*!< Specifies the low threshold of the DTS sensor */

+

+} DTS_InitTypeDef;

+

+/**

+  * @brief  HAL State structures definition

+  */

+typedef enum

+{

+  HAL_DTS_STATE_RESET       = 0x00UL,     /*!< DTS not yet initialized or disabled */

+  HAL_DTS_STATE_READY       = 0x01UL,     /*!< DTS initialized and ready for use   */

+  HAL_DTS_STATE_BUSY        = 0x02UL,     /*!< DTS is running                      */

+  HAL_DTS_STATE_TIMEOUT     = 0x03UL,     /*!< Timeout state                       */

+  HAL_DTS_STATE_ERROR       = 0x04UL      /*!< Internal Process error              */

+} HAL_DTS_StateTypeDef;

+

+/**

+  * @brief  DTS Handle Structure definition

+  */

+#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)

+typedef struct __DTS_HandleTypeDef

+#else

+typedef struct

+#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */

+{

+  DTS_TypeDef         *Instance;    /*!< Register base address */

+  DTS_InitTypeDef     Init;         /*!< DTS required parameters */

+  HAL_LockTypeDef     Lock;         /*!< DTS Locking object */

+  __IO HAL_DTS_StateTypeDef  State; /*!< DTS peripheral state  */

+#if (USE_HAL_DTS_REGISTER_CALLBACKS == 1)

+  void (* MspInitCallback)(struct __DTS_HandleTypeDef *hdts);         /*!< DTS Base Msp Init Callback                   */

+  void (* MspDeInitCallback)(struct __DTS_HandleTypeDef *hdts);       /*!< DTS Base Msp DeInit Callback                 */

+  void (* DTS_EndCallback)(struct __DTS_HandleTypeDef *hdts);         /*!< End measure Callback                         */

+  void (* DTS_LowCallback)(struct __DTS_HandleTypeDef *hdts);         /*!< low threshold Callback                       */

+  void (* DTS_HighCallback)(struct __DTS_HandleTypeDef *hdts);        /*!< high threshold Callback                      */

+  void (* DTS_AsyncEndCallback)(struct __DTS_HandleTypeDef *hdts);    /*!< Asynchronous end of measure Callback         */

+  void (* DTS_AsyncLowCallback)(struct __DTS_HandleTypeDef *hdts);    /*!< Asynchronous low threshold Callback          */

+  void (* DTS_AsyncHighCallback(struct __DTS_HandleTypeDef *hdts);    /*!< Asynchronous high threshold Callback         */

+#endif /* USE_HAL_DTS_REGISTER_CALLBACKS */

+} DTS_HandleTypeDef;

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup DTS_Exported_Constants DTS Exported Constants

+  * @{

+  */

+

+/** @defgroup DTS_TriggerConfig  DTS Trigger Configuration

+  * @{

+  */

+/* @brief No Hardware trigger detection */

+#define DTS_TRIGGER_HW_NONE   (0UL)

+

+/* @brief External Interrupt Mode with LPTIMER1 trigger detection */

+#define DTS_TRIGGER_LPTIMER1  DTS_CFGR1_TS1_INTRIG_SEL_0

+

+/* @brief External Interrupt Mode with LPTIMER2 trigger detection */

+#define DTS_TRIGGER_LPTIMER2  DTS_CFGR1_TS1_INTRIG_SEL_1

+

+/* @brief External Interrupt Mode with LPTIMER3 trigger detection */

+#define DTS_TRIGGER_LPTIMER3 (DTS_CFGR1_TS1_INTRIG_SEL_0 | DTS_CFGR1_TS1_INTRIG_SEL_1)

+

+/* @brief External Interrupt Mode with EXTI13 trigger detection */

+#define DTS_TRIGGER_EXTI13    DTS_CFGR1_TS1_INTRIG_SEL_2

+/**

+  * @}

+  */

+

+/** @defgroup DTS_Quick_Measurement  DTS Quick Measurement

+  * @{

+  */

+#define DTS_QUICKMEAS_ENABLE    DTS_CFGR1_Q_MEAS_OPT      /*!< Enable the Quick Measure (Measure without calibration) */

+#define DTS_QUICKMEAS_DISABLE   (0x0UL)                   /*!< Disable the Quick Measure (Measure with calibration) */

+/**

+  * @}

+  */

+

+/** @defgroup DTS_Reference_Clock_Selection   DTS Reference Clock Selection

+  * @{

+  */

+#define DTS_REFCLKSEL_LSE   DTS_CFGR1_REFCLK_SEL          /*!< Low speed REF clock (LSE) */

+#define DTS_REFCLKSEL_PCLK (0UL)                          /*!< High speed REF clock (PCLK) */

+/**

+  * @}

+  */

+

+/** @defgroup DTS_Sampling_Time   DTS Sampling Time

+  * @{

+  */

+#define DTS_SMP_TIME_1_CYCLE     DTS_CFGR1_TS1_SMP_TIME_0                                                                                   /*!< 1 clock cycle for the sampling time  */

+#define DTS_SMP_TIME_2_CYCLE     DTS_CFGR1_TS1_SMP_TIME_1                                                                                   /*!< 2 clock cycle for the sampling time  */

+#define DTS_SMP_TIME_3_CYCLE    (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_1)                                                       /*!< 3 clock cycle for the sampling time  */

+#define DTS_SMP_TIME_4_CYCLE    (DTS_CFGR1_TS1_SMP_TIME_2)                                                                                 /*!< 4 clock cycle for the sampling time  */

+#define DTS_SMP_TIME_5_CYCLE    (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_2)                                                       /*!< 5 clock cycle for the sampling time  */

+#define DTS_SMP_TIME_6_CYCLE    (DTS_CFGR1_TS1_SMP_TIME_1 | DTS_CFGR1_TS1_SMP_TIME_2)                                                       /*!< 6 clock cycle for the sampling time  */

+#define DTS_SMP_TIME_7_CYCLE    (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_1 | DTS_CFGR1_TS1_SMP_TIME_2)                            /*!< 7 clock cycle for the sampling time  */

+#define DTS_SMP_TIME_8_CYCLE    (DTS_CFGR1_TS1_SMP_TIME_3)                                                                                  /*!< 8 clock cycle for the sampling time  */

+#define DTS_SMP_TIME_9_CYCLE    (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_3)                                                       /*!< 9 clock cycle for the sampling time  */

+#define DTS_SMP_TIME_10_CYCLE   (DTS_CFGR1_TS1_SMP_TIME_1 | DTS_CFGR1_TS1_SMP_TIME_3)                                                       /*!< 10 clock cycle for the sampling time */

+#define DTS_SMP_TIME_11_CYCLE   (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_1 | DTS_CFGR1_TS1_SMP_TIME_3)                            /*!< 11 clock cycle for the sampling time */

+#define DTS_SMP_TIME_12_CYCLE   (DTS_CFGR1_TS1_SMP_TIME_2 | DTS_CFGR1_TS1_SMP_TIME_3)                                                       /*!< 12 clock cycle for the sampling time */

+#define DTS_SMP_TIME_13_CYCLE   (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_2 | DTS_CFGR1_TS1_SMP_TIME_3)                            /*!< 13 clock cycle for the sampling time */

+#define DTS_SMP_TIME_14_CYCLE   (DTS_CFGR1_TS1_SMP_TIME_1 | DTS_CFGR1_TS1_SMP_TIME_2 | DTS_CFGR1_TS1_SMP_TIME_3)                            /*!< 14 clock cycle for the sampling time */

+#define DTS_SMP_TIME_15_CYCLE   (DTS_CFGR1_TS1_SMP_TIME_0 | DTS_CFGR1_TS1_SMP_TIME_1 | DTS_CFGR1_TS1_SMP_TIME_2 | DTS_CFGR1_TS1_SMP_TIME_3) /*!< 15 clock cycle for the sampling time */

+/**

+  * @}

+  */

+/** @defgroup DTS_Flag_Definitions DTS Flag Definitions

+  * @{

+  */

+#define DTS_FLAG_TS1_ITE   DTS_SR_TS1_ITEF   /*!< Interrupt flag for end of measure for DTS1 */

+#define DTS_FLAG_TS1_ITL   DTS_SR_TS1_ITLF   /*!< Interrupt flag for low threshold for DTS1  */

+#define DTS_FLAG_TS1_ITH   DTS_SR_TS1_ITHF   /*!< Interrupt flag for high threshold for DTS1 */

+#define DTS_FLAG_TS1_AITE  DTS_SR_TS1_AITEF  /*!< Asynchronous Interrupt flag for end of measure for DTS1 */

+#define DTS_FLAG_TS1_AITL  DTS_SR_TS1_AITLF  /*!< Asynchronous Interrupt flag for low threshold for DTS1  */

+#define DTS_FLAG_TS1_AITH  DTS_SR_TS1_AITHF  /*!< Asynchronous Interrupt flag for high threshold for DTS1 */

+#define DTS_FLAG_TS1_RDY   DTS_SR_TS1_RDY    /*!< Ready flag for DTS1 */

+/**

+  * @}

+  */

+

+/** @defgroup DTS_Interrupts_Definitions DTS Interrupts Definitions

+  * @{

+  */

+#define DTS_IT_TS1_ITE  DTS_ITENR_TS1_ITEEN   /*!< Enable interrupt flag for end of measure for DTS1 */

+#define DTS_IT_TS1_ITL  DTS_ITENR_TS1_ITLEN   /*!< Enable interrupt flag for low threshold for DTS1  */

+#define DTS_IT_TS1_ITH  DTS_ITENR_TS1_ITHEN   /*!< Enable interrupt flag for high threshold for DTS1 */

+#define DTS_IT_TS1_AITE DTS_ITENR_TS1_AITEEN  /*!< Enable asynchronous interrupt flag for end of measure for DTS1 */

+#define DTS_IT_TS1_AITL DTS_ITENR_TS1_AITLEN  /*!< Enable asynchronous interrupt flag for low threshold for DTS1  */

+#define DTS_IT_TS1_AITH DTS_ITENR_TS1_AITHEN  /*!< Enable asynchronous interrupt flag for high threshold for DTS1 */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+/* Exported macros -----------------------------------------------------------*/

+/** @defgroup DTS_Exported_Macros DTS Exported Macros

+  * @{

+  */

+

+/** @brief  Reset DTS handle state

+  * @param  __HANDLE__ DTS handle.

+  * @retval None

+  */

+#define __HAL_DTS_RESET_HANDLE_STATE(__HANDLE__)    ((__HANDLE__)->State = HAL_DTS_STATE_RESET)

+

+/**

+  * @brief  Enable the specified DTS sensor

+  * @param  __HANDLE__ DTS handle.

+  * @retval None

+  */

+#define __HAL_DTS_ENABLE(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CFGR1, DTS_CFGR1_TS1_EN)

+

+/**

+  * @brief  Disable the specified DTS sensor

+  * @param  __HANDLE__ DTS handle.

+  * @retval None

+  */

+#define __HAL_DTS_DISABLE(__HANDLE__)    CLEAR_BIT((__HANDLE__)->Instance->CFGR1, DTS_CFGR1_TS1_EN)

+

+/**

+  * @brief  Enable the DTS EXTI line in interrupt mode

+  * @retval None

+  */

+#define __HAL_DTS_EXTI_WAKEUP_ENABLE_IT()  SET_BIT(EXTI->IMR3, DTS_EXTI_LINE_DTS1)

+

+/**

+  * @brief  Disable the DTS EXTI line in interrupt mode

+  * @retval None

+  */

+#define __HAL_DTS_EXTI_WAKEUP_DISABLE_IT()  CLEAR_BIT(EXTI->IMR3, DTS_EXTI_LINE_DTS1)

+

+/**

+  * @brief  Enable the DTS EXTI Line in event mode

+  * @retval None

+  */

+#define __HAL_DTS_EXTI_WAKEUP_ENABLE_EVENT() SET_BIT(EXTI->EMR3, DTS_EXTI_LINE_DTS1)

+

+/**

+  * @brief  Disable the DTS EXTI Line in event mode

+  * @retval None

+  */

+#define __HAL_DTS_EXTI_WAKEUP_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR3, DTS_EXTI_LINE_DTS1)

+

+/** @brief  Checks whether the specified DTS flag is set or not.

+  * @param  __HANDLE__ specifies the DTS Handle.

+  * @param  __FLAG__ specifies the flag to check.

+  *        This parameter can be one of the following values:

+  *            @arg DTS_FLAG_TS1_ITE : interrupt flag for end of measure for DTS1

+  *            @arg DTS_FLAG_TS1_ITL : interrupt flag for low threshold for DTS1

+  *            @arg DTS_FLAG_TS1_ITH : interrupt flag for high threshold for DTS1

+  *            @arg DTS_FLAG_TS1_AITE: asynchronous interrupt flag for end of measure for DTS1

+  *            @arg DTS_FLAG_TS1_AITL: asynchronous interrupt flag for low threshold for DTS1

+  *            @arg DTS_FLAG_TS1_AITH: asynchronous interrupt flag for high threshold for DTS1

+  *            @arg DTS_FLAG_TS1_RDY : Ready flag for DTS1

+  *            @retval The new state of __FLAG__ (SET or RESET).

+  */

+#define __HAL_DTS_GET_FLAG(__HANDLE__, __FLAG__)  \

+        (((((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)))? SET : RESET)

+

+

+/** @brief  Clears the specified DTS pending flag.

+  * @param  __HANDLE__ specifies the DTS Handle.

+  * @param  __FLAG__ specifies the flag to check.

+  *          This parameter can be any combination of the following values:

+  *            @arg DTS_FLAG_TS1_ITE : interrupt flag for end of measure for DTS1

+  *            @arg DTS_FLAG_TS1_ITL : interrupt flag for low threshold for DTS1

+  *            @arg DTS_FLAG_TS1_ITH : interrupt flag for high threshold for DTS1

+  *            @arg DTS_FLAG_TS1_AITE: asynchronous interrupt flag for end of measure for DTS1

+  *            @arg DTS_FLAG_TS1_AITL: asynchronous interrupt flag for low threshold for DTS1

+  *            @arg DTS_FLAG_TS1_AITH: asynchronous interrupt flag for high threshold for DTS1

+  * @retval None

+  */

+#define __HAL_DTS_CLEAR_FLAG(__HANDLE__, __FLAG__)  \

+        ((__HANDLE__)->Instance->ICIFR  = (__FLAG__))

+

+

+/** @brief  Enable the specified DTS interrupt.

+  * @param  __HANDLE__ specifies the DTS Handle.

+  * @param  __INTERRUPT__ specifies the DTS interrupt source to enable.

+  *          This parameter can be one of the following values:

+  *            @arg DTS_IT_TS1_ITE  : interrupt flag for end of measure for DTS1

+  *            @arg DTS_IT_TS1_ITL  : interrupt flag for low of measure for DTS1

+  *            @arg DTS_IT_TS1_ITH  : interrupt flag for high of measure for DTS1

+  *            @arg DTS_IT_TS1_AITE : asynchronous interrupt flag for end of measure for DTS1

+  *            @arg DTS_IT_TS1_AITL : asynchronous interrupt flag for low of measure for DTS1

+  *            @arg DTS_IT_TS1_AITH : asynchronous interrupt flag for high of measure for DTS1

+  * @retval None

+  */

+#define __HAL_DTS_ENABLE_IT(__HANDLE__, __INTERRUPT__)  \

+        SET_BIT((__HANDLE__)->Instance->ITENR, __INTERRUPT__)

+

+

+/** @brief  Disable the specified DTS interrupt.

+  * @param  __HANDLE__ specifies the DTS Handle.

+  * @param  __INTERRUPT__ specifies the DTS interrupt source to enable.

+  *          This parameter can be one of the following values:

+  *            @arg DTS_IT_TS1_ITE  : interrupt flag for end of measure for DTS1

+  *            @arg DTS_IT_TS1_ITL  : interrupt flag for low of measure for DTS1

+  *            @arg DTS_IT_TS1_ITH  : interrupt flag for high of measure for DTS1

+  *            @arg DTS_IT_TS1_AITE : asynchronous interrupt flag for end of measure for DTS1

+  *            @arg DTS_IT_TS1_AITL : asynchronous interrupt flag for low of measure for DTS1

+  *            @arg DTS_IT_TS1_AITH : asynchronous interrupt flag for high of measure for DTS1

+  * @retval None

+  */

+#define __HAL_DTS_DISABLE_IT(__HANDLE__,__INTERRUPT__)  \

+        CLEAR_BIT((__HANDLE__)->Instance->ITENR, __INTERRUPT__)

+

+

+/** @brief  Check whether the specified DTS interrupt source is enabled or not.

+  * @param __HANDLE__ DTS handle.

+  * @param __INTERRUPT__ DTS interrupt source to check

+  *          This parameter can be one of the following values:

+  *            @arg DTS_IT_TS1_ITE  : interrupt flag for end of measure for DTS1

+  *            @arg DTS_IT_TS1_ITL  : interrupt flag for low of measure for DTS1

+  *            @arg DTS_IT_TS1_ITH  : interrupt flag for high of measure for DTS1

+  *            @arg DTS_IT_TS1_AITE : asynchronous interrupt flag for end of measure for DTS1

+  *            @arg DTS_IT_TS1_AITL : asynchronous interrupt flag for low of measure for DTS1

+  *            @arg DTS_IT_TS1_AITH : asynchronous interrupt flag for high of measure for DTS1

+  * @retval State of interruption (SET or RESET)

+  */

+#define __HAL_DTS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  \

+        (( ((__HANDLE__)->Instance->ITENR & (__INTERRUPT__)) == (__INTERRUPT__) \

+        )? SET : RESET)

+

+

+/** @brief  Check whether the specified DTS REFCLK is selected

+  * @param __HANDLE__ DTS handle.

+  * @param __REFCLK__ DTS reference clock to check

+  *          This parameter can be one of the following values:

+  * @arg DTS_REFCLKSEL_LSE:   Low speed REF clock

+  * @arg DTS_REFCLKSEL_PCLK:  High speed REF clock

+  * @retval State of the REF clock tested (SET or RESET)

+  */

+#define __HAL_DTS_GET_REFCLK(__HANDLE__, __REFCLK__)  ((((__HANDLE__)->Instance->CFGR1 & (__REFCLK__)) == (__REFCLK__))? SET : RESET)

+

+/** @brief  Get Trigger

+  * @param __HANDLE__ DTS handle.

+  * @retval One of the following trigger

+  *     DTS_TRIGGER_HW_NONE : No HW trigger (SW trigger)

+  *     DTS_TRIGGER_LPTIMER1: LPTIMER1 trigger

+  *     DTS_TRIGGER_LPTIMER2: LPTIMER2 trigger

+  *     DTS_TRIGGER_LPTIMER3: LPTIMER3 trigger

+  *     DTS_TRIGGER_EXTI13  : EXTI13 trigger

+  */

+#define __HAL_DTS_GET_TRIGGER(__HANDLE__)  ((__HANDLE__)->Instance->CFGR1 & (DTS_CFGR1_TS1_INTRIG_SEL))

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup DTS_Exported_Functions

+  * @{

+  */

+

+/** @addtogroup DTS_Exported_Functions_Group1

+  * @{

+  */

+/* Initialization and de-initialization functions  **********************************/

+HAL_StatusTypeDef HAL_DTS_Init(DTS_HandleTypeDef *hdts);

+HAL_StatusTypeDef HAL_DTS_DeInit(DTS_HandleTypeDef *hdts);

+void              HAL_DTS_MspInit(DTS_HandleTypeDef *hdts);

+void              HAL_DTS_MspDeInit(DTS_HandleTypeDef *hdts);

+/**

+  * @}

+  */

+

+/* IO operation functions  *****************************************************/

+/** @addtogroup DTS_Exported_Functions_Group2

+  * @{

+  */

+HAL_StatusTypeDef HAL_DTS_Start(DTS_HandleTypeDef *hdts);

+HAL_StatusTypeDef HAL_DTS_Stop(DTS_HandleTypeDef *hdts);

+HAL_StatusTypeDef HAL_DTS_GetTemperature(DTS_HandleTypeDef *hdts, int32_t *Temperature);

+HAL_StatusTypeDef HAL_DTS_Start_IT(DTS_HandleTypeDef *hdts);

+HAL_StatusTypeDef HAL_DTS_Stop_IT(DTS_HandleTypeDef *hdts);

+void              HAL_DTS_IRQHandler(DTS_HandleTypeDef *hdts);

+HAL_DTS_StateTypeDef HAL_DTS_GetState(DTS_HandleTypeDef *hdts);

+/* Callback in Interrupt mode */

+void              HAL_DTS_EndCallback(DTS_HandleTypeDef *hdts);

+void              HAL_DTS_LowCallback(DTS_HandleTypeDef *hdts);

+void              HAL_DTS_HighCallback(DTS_HandleTypeDef *hdts);

+void              HAL_DTS_AsyncEndCallback(DTS_HandleTypeDef *hdts);

+void              HAL_DTS_AsyncLowCallback(DTS_HandleTypeDef *hdts);

+void              HAL_DTS_AsyncHighCallback(DTS_HandleTypeDef *hdts);

+/**

+  * @}

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup DTS_Private_Constants DTS Private Constants

+  * @{

+  */

+/** @defgroup DTS_ExtiLine DTS EXTI Lines

+  * @{

+  */

+#define DTS_EXTI_LINE_DTS1           (EXTI_IMR3_IM88)  /*!< EXTI line 88 connected to DTS1 output */

+/**

+  * @}

+  */

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup DTS_Private_Macros DTS Private Macros

+  * @{

+  */

+

+/** @defgroup DTS_IS_DTS_Definitions  DTS Private macros to check input parameters

+  * @{

+  */

+#define IS_DTS_QUICKMEAS(__SEL__)   (((__SEL__) == DTS_QUICKMEAS_DISABLE) || \

+                                     ((__SEL__) == DTS_QUICKMEAS_ENABLE))

+

+#define IS_DTS_REFCLK(__SEL__)      (((__SEL__) == DTS_REFCLKSEL_LSE) || \

+                                     ((__SEL__) == DTS_REFCLKSEL_PCLK))

+

+#define IS_DTS_TRIGGERINPUT(__INPUT__)  (((__INPUT__) == DTS_TRIGGER_HW_NONE)   || \

+                                         ((__INPUT__) == DTS_TRIGGER_LPTIMER1)  || \

+                                         ((__INPUT__) == DTS_TRIGGER_LPTIMER2)  || \

+                                         ((__INPUT__) == DTS_TRIGGER_LPTIMER3)  || \

+                                         ((__INPUT__) == DTS_TRIGGER_EXTI13))

+

+#define IS_DTS_THRESHOLD(__THRESHOLD__)  ((__THRESHOLD__) <= 0xFFFFUL)

+

+#define IS_DTS_DIVIDER_RATIO_NUMBER(__NUMBER__) (((__NUMBER__) >= (2UL)) && ((__NUMBER__) <= (127UL)))

+

+#define IS_DTS_SAMPLINGTIME(__CYCLE__)  (((__CYCLE__) == DTS_SMP_TIME_1_CYCLE)  || \

+                                             ((__CYCLE__) == DTS_SMP_TIME_2_CYCLE)    || \

+                                             ((__CYCLE__) == DTS_SMP_TIME_3_CYCLE)    || \

+                                             ((__CYCLE__) == DTS_SMP_TIME_4_CYCLE)    || \

+                                             ((__CYCLE__) == DTS_SMP_TIME_5_CYCLE)    || \

+                                             ((__CYCLE__) == DTS_SMP_TIME_6_CYCLE)    || \

+                                             ((__CYCLE__) == DTS_SMP_TIME_7_CYCLE)    || \

+                                             ((__CYCLE__) == DTS_SMP_TIME_8_CYCLE)    || \

+                                             ((__CYCLE__) == DTS_SMP_TIME_9_CYCLE)    || \

+                                             ((__CYCLE__) == DTS_SMP_TIME_10_CYCLE)   || \

+                                             ((__CYCLE__) == DTS_SMP_TIME_11_CYCLE)   || \

+                                             ((__CYCLE__) == DTS_SMP_TIME_12_CYCLE)   || \

+                                             ((__CYCLE__) == DTS_SMP_TIME_13_CYCLE)   || \

+                                             ((__CYCLE__) == DTS_SMP_TIME_14_CYCLE)   || \

+                                             ((__CYCLE__) == DTS_SMP_TIME_15_CYCLE))

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private functions ---------------------------------------------------------*/

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* DTS */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* __STM32H7xx_HAL_DTS_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_eth.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_eth.h
new file mode 100644
index 0000000000..bb2bacd68e
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_eth.h
@@ -0,0 +1,1680 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_eth.h

+  * @author  MCD Application Team

+  * @brief   Header file of ETH HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */ 

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_ETH_H

+#define STM32H7xx_HAL_ETH_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+#if defined(ETH)

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup ETH

+  * @{

+  */ 

+

+/* Exported types ------------------------------------------------------------*/

+#ifndef ETH_TX_DESC_CNT

+ #define ETH_TX_DESC_CNT         4U

+#endif

+	 

+#ifndef ETH_RX_DESC_CNT

+ #define ETH_RX_DESC_CNT         4U

+#endif

+

+/*********************** Descriptors struct def section ************************/

+/** @defgroup ETH_Exported_Types ETH Exported Types

+  * @{

+  */

+

+/** 

+  * @brief  ETH DMA Descriptor structure definition

+  */

+typedef struct

+{

+  __IO uint32_t DESC0;

+  __IO uint32_t DESC1;

+  __IO uint32_t DESC2;

+  __IO uint32_t DESC3;

+  __IO uint32_t BackupAddr0; /* used to store rx buffer 1 address */

+  __IO uint32_t BackupAddr1; /* used to store rx buffer 2 address */

+}ETH_DMADescTypeDef;

+/** 

+  * 

+  */

+

+/** 

+  * @brief  ETH Buffers List structure definition

+  */

+typedef struct __ETH_BufferTypeDef

+{

+  uint8_t *buffer;                /*<! buffer address */

+  

+  uint32_t len;                   /*<! buffer length */

+  

+  struct __ETH_BufferTypeDef *next; /*<! Pointer to the next buffer in the list */	

+}ETH_BufferTypeDef;

+/** 

+  * 

+  */

+  

+/** 

+  * @brief  DMA Transmit Descriptors Wrapper structure definition

+  */

+typedef struct

+{

+  uint32_t  TxDesc[ETH_TX_DESC_CNT];     /*<! Tx DMA descriptors addresses */

+  

+  uint32_t  CurTxDesc;               /*<! Current Tx descriptor index for packet transmission */

+  

+}ETH_TxDescListTypeDef;

+/** 

+  * 

+  */

+

+ /** 

+  * @brief  Transmit Packet Configuration structure definition

+  */

+typedef struct

+{

+  uint32_t Attributes;              /*!< Tx packet HW features capabilities. 

+                                         This parameter can be a combination of @ref ETH_Tx_Packet_Attributes*/

+  

+  uint32_t Length;                  /*!< Total packet length   */

+  

+  ETH_BufferTypeDef *TxBuffer;      /*!< Tx buffers pointers */

+  

+  uint32_t SrcAddrCtrl;             /*!< Specifies the source address insertion control.

+                                         This parameter can be a value of @ref ETH_Tx_Packet_Source_Addr_Control */

+  

+  uint32_t CRCPadCtrl;             /*!< Specifies the CRC and Pad insertion and replacement control. 

+                                        This parameter can be a value of @ref ETH_Tx_Packet_CRC_Pad_Control  */

+  

+  uint32_t ChecksumCtrl;           /*!< Specifies the checksum insertion control. 

+                                        This parameter can be a value of @ref ETH_Tx_Packet_Checksum_Control  */

+  

+  uint32_t MaxSegmentSize;         /*!< Sets TCP maximum segment size only when TCP segmentation is enabled. 

+                                        This parameter can be a value from 0x0 to 0x3FFF */

+  

+  uint32_t PayloadLen;             /*!< Sets Total payload length only when TCP segmentation is enabled.     

+                                        This parameter can be a value from 0x0 to 0x3FFFF */

+  

+  uint32_t TCPHeaderLen;           /*!< Sets TCP header length only when TCP segmentation is enabled.

+                                        This parameter can be a value from 0x5 to 0xF */

+

+  uint32_t VlanTag;                /*!< Sets VLAN Tag only when VLAN is enabled. 

+                                        This parameter can be a value from 0x0 to 0xFFFF*/

+  

+  uint32_t VlanCtrl;               /*!< Specifies VLAN Tag insertion control only when VLAN is enabled. 

+                                        This parameter can be a value of @ref ETH_Tx_Packet_VLAN_Control */

+  

+  uint32_t InnerVlanTag;           /*!< Sets Inner VLAN Tag only when Inner VLAN is enabled.

+                                        This parameter can be a value from 0x0 to 0x3FFFF */

+  

+  uint32_t InnerVlanCtrl;          /*!< Specifies Inner VLAN Tag insertion control only when Inner VLAN is enabled. 

+                                        This parameter can be a value of @ref ETH_Tx_Packet_Inner_VLAN_Control   */

+  

+}ETH_TxPacketConfig;

+/** 

+  * 

+  */

+

+/** 

+ * @brief  DMA Receive Descriptors Wrapper structure definition

+ */

+typedef struct

+{

+  uint32_t RxDesc[ETH_RX_DESC_CNT];     /*<! Rx DMA descriptors addresses. */

+  

+  uint32_t CurRxDesc;                   /*<! Current Rx descriptor, ready for next reception. */

+  

+  uint32_t FirstAppDesc;                /*<! First descriptor of last received packet. */

+  

+  uint32_t AppDescNbr;                  /*<! Number of descriptors of last received packet. */

+ 

+  uint32_t AppContextDesc;              /*<! If 1 a context descriptor is present in last received packet.

+                                             If 0 no context descriptor is present in last received packet. */

+  

+  uint32_t ItMode;                      /*<! If 1, DMA will generate the Rx complete interrupt.

+                                             If 0, DMA will not generate the Rx complete interrupt. */ 

+}ETH_RxDescListTypeDef;

+/** 

+  * 

+  */

+

+/** 

+  * @brief  Received Packet Information structure definition

+  */ 

+typedef struct  

+{  

+  uint32_t SegmentCnt;      /*<! Number of Rx Descriptors */

+  

+  uint32_t VlanTag;         /*<! Vlan Tag value */

+  

+  uint32_t InnerVlanTag;    /*<! Inner Vlan Tag value */

+  

+  uint32_t Checksum;        /*<! Rx Checksum status. 

+                                 This parameter can be a value of @ref ETH_Rx_Checksum_Status */

+  

+  uint32_t HeaderType;      /*<! IP header type. 

+                                 This parameter can be a value of @ref ETH_Rx_IP_Header_Type */

+  

+  uint32_t PayloadType;     /*<! Payload type. 

+                                 This parameter can be a value of @ref ETH_Rx_Payload_Type */

+  

+  uint32_t MacFilterStatus; /*<! MAC filter status.  

+                                 This parameter can be a value of @ref ETH_Rx_MAC_Filter_Status */

+  

+  uint32_t L3FilterStatus;  /*<! L3 filter status

+                                 This parameter can be a value of @ref ETH_Rx_L3_Filter_Status */

+  

+  uint32_t L4FilterStatus;  /*<! L4 filter status  

+                                 This parameter can be a value of @ref ETH_Rx_L4_Filter_Status */

+  

+  uint32_t ErrorCode;       /*<! Rx error code  

+                                 This parameter can be a combination of @ref ETH_Rx_Error_Code */

+

+} ETH_RxPacketInfo;

+/** 

+  * 

+  */

+

+/** 

+  * @brief  ETH MAC Configuration Structure definition  

+  */

+typedef struct

+{

+  uint32_t         SourceAddrControl;           /*!< Selects the Source Address Insertion or Replacement Control.                                                           

+                                                     This parameter can be a value of @ref ETH_Source_Addr_Control */                  

+

+  FunctionalState  ChecksumOffload;             /*!< Enables or Disable the checksum checking for received packet payloads TCP, UDP or ICMP headers */    

+

+  uint32_t         InterPacketGapVal;           /*!< Sets the minimum IPG between Packet during transmission.

+                                                     This parameter can be a value of @ref ETH_Inter_Packet_Gap */   

+

+  FunctionalState  GiantPacketSizeLimitControl; /*!< Enables or disables the Giant Packet Size Limit Control. */  

+

+  FunctionalState  Support2KPacket;             /*!< Enables or disables the IEEE 802.3as Support for 2K length Packets */ 

+

+  FunctionalState  CRCStripTypePacket;          /*!< Enables or disables the CRC stripping for Type packets.*/ 

+

+  FunctionalState  AutomaticPadCRCStrip;        /*!< Enables or disables  the Automatic MAC Pad/CRC Stripping.*/ 

+																													 

+  FunctionalState  Watchdog;                    /*!< Enables or disables the Watchdog timer on Rx path

+                                                           When enabled, the MAC allows no more then 2048 bytes to be received.

+                                                           When disabled, the MAC can receive up to 16384 bytes. */  

+

+  FunctionalState  Jabber;                      /*!< Enables or disables Jabber timer on Tx path

+                                                           When enabled, the MAC allows no more then 2048 bytes to be sent.

+                                                           When disabled, the MAC can send up to 16384 bytes. */

+

+  FunctionalState  JumboPacket;                 /*!< Enables or disables receiving Jumbo Packet

+                                                           When enabled, the MAC allows jumbo packets of 9,018 bytes

+                                                           without reporting a giant packet error */

+

+  uint32_t         Speed;                       /*!< Sets the Ethernet speed: 10/100 Mbps.

+                                                           This parameter can be a value of @ref ETH_Speed */

+

+  uint32_t         DuplexMode;                  /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode

+                                                           This parameter can be a value of @ref ETH_Duplex_Mode */

+

+  FunctionalState  LoopbackMode;                /*!< Enables or disables the loopback mode */

+

+  FunctionalState  CarrierSenseBeforeTransmit;  /*!< Enables or disables the Carrier Sense Before Transmission in Full Duplex Mode. */

+

+  FunctionalState  ReceiveOwn;                  /*!< Enables or disables the Receive Own in Half Duplex mode. */  

+

+  FunctionalState  CarrierSenseDuringTransmit;  /*!< Enables or disables the Carrier Sense During Transmission in the Half Duplex mode */

+

+  FunctionalState  RetryTransmission;           /*!< Enables or disables the MAC retry transmission, when a collision occurs in Half Duplex mode.*/

+

+  uint32_t         BackOffLimit;                /*!< Selects the BackOff limit value.

+                                                        This parameter can be a value of @ref ETH_Back_Off_Limit */

+

+  FunctionalState  DeferralCheck;               /*!< Enables or disables the deferral check function in Half Duplex mode. */

+

+  uint32_t         PreambleLength;              /*!< Selects or not the Preamble Length for Transmit packets (Full Duplex mode).

+                                                           This parameter can be a value of @ref ETH_Preamble_Length */ 

+                                                           

+  FunctionalState  UnicastSlowProtocolPacketDetect;   /*!< Enable or disables the Detection of Slow Protocol Packets with unicast address. */   

+

+  FunctionalState  SlowProtocolDetect;          /*!< Enable or disables the Slow Protocol Detection. */   

+

+  FunctionalState  CRCCheckingRxPackets;        /*!< Enable or disables the CRC Checking for Received Packets. */   

+

+  uint32_t         GiantPacketSizeLimit;        /*!< Specifies the packet size that the MAC will declare it as Giant, If it's size is 

+	                                                  greater than the value programmed in this field in units of bytes 

+                                                          This parameter must be a number between Min_Data = 0x618 (1518 byte) and Max_Data = 0x3FFF (32 Kbyte)*/                                                          

+ 

+  FunctionalState  ExtendedInterPacketGap;      /*!< Enable or disables the extended inter packet gap. */ 

+  

+  uint32_t         ExtendedInterPacketGapVal;   /*!< Sets the Extended IPG between Packet during transmission.

+                                                           This parameter can be a value from 0x0 to 0xFF */ 

+  

+  FunctionalState  ProgrammableWatchdog;        /*!< Enable or disables the Programmable Watchdog.*/

+	

+  uint32_t         WatchdogTimeout;             /*!< This field is used as watchdog timeout for a received packet

+                                                        This parameter can be a value of @ref ETH_Watchdog_Timeout */                                                            

+

+   uint32_t        PauseTime;                   /*!< This field holds the value to be used in the Pause Time field in the transmit control packet. 

+                                                   This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */

+

+  FunctionalState  ZeroQuantaPause;             /*!< Enable or disables the automatic generation of Zero Quanta Pause Control packets.*/  

+

+  uint32_t         PauseLowThreshold;           /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Packet.

+                                                   This parameter can be a value of @ref ETH_Pause_Low_Threshold */

+

+  FunctionalState  TransmitFlowControl;         /*!< Enables or disables the MAC to transmit Pause packets in Full Duplex mode

+                                                   or the MAC back pressure operation in Half Duplex mode */

+

+  FunctionalState  UnicastPausePacketDetect;    /*!< Enables or disables the MAC to detect Pause packets with unicast address of the station */

+  

+  FunctionalState  ReceiveFlowControl;          /*!< Enables or disables the MAC to decodes the received Pause packet  

+                                                  and disables its transmitter for a specified (Pause) time */

+																													                                                        	 

+  uint32_t         TransmitQueueMode;           /*!< Specifies the Transmit Queue operating mode.

+                                                      This parameter can be a value of @ref ETH_Transmit_Mode */ 

+

+  uint32_t         ReceiveQueueMode;            /*!< Specifies the Receive Queue operating mode.

+                                                             This parameter can be a value of @ref ETH_Receive_Mode */

+

+  FunctionalState  DropTCPIPChecksumErrorPacket; /*!< Enables or disables Dropping of TCPIP Checksum Error Packets. */ 

+

+  FunctionalState  ForwardRxErrorPacket;        /*!< Enables or disables  forwarding Error Packets. */ 

+

+  FunctionalState  ForwardRxUndersizedGoodPacket;  /*!< Enables or disables  forwarding Undersized Good Packets.*/ 

+} ETH_MACConfigTypeDef;

+/** 

+  * 

+  */

+

+/** 

+  * @brief  ETH DMA Configuration Structure definition  

+  */

+ typedef struct

+ {

+   uint32_t        DMAArbitration;          /*!< Sets the arbitration scheme between DMA Tx and Rx

+                                                         This parameter can be a value of @ref ETH_DMA_Arbitration */

+      

+   FunctionalState AddressAlignedBeats;     /*!< Enables or disables the AHB Master interface address aligned 

+                                                            burst transfers on Read and Write channels  */

+      

+   uint32_t        BurstMode;               /*!< Sets the AHB Master interface burst transfers.

+                                                     This parameter can be a value of @ref ETH_Burst_Mode */

+      

+   FunctionalState RebuildINCRxBurst;       /*!< Enables or disables the AHB Master to rebuild the pending beats 

+                                                   of any initiated burst transfer with INCRx and SINGLE transfers. */

+      

+   FunctionalState PBLx8Mode;               /*!< Enables or disables the PBL multiplication by eight. */

+      

+   uint32_t        TxDMABurstLength;        /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.

+                                                     This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */	

+      

+   FunctionalState SecondPacketOperate;     /*!< Enables or disables the Operate on second Packet mode, which allows the DMA to process a second

+                                                      Packet of Transmit data even before obtaining the status for the first one. */	

+      

+   uint32_t        RxDMABurstLength;        /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.

+                                                    This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */

+      

+   FunctionalState FlushRxPacket;           /*!< Enables or disables the Rx Packet Flush */

+      

+   FunctionalState TCPSegmentation;         /*!< Enables or disables the TCP Segmentation */

+      

+   uint32_t        MaximumSegmentSize;      /*!< Sets the maximum segment size that should be used while segmenting the packet

+                                                  This parameter can be a value from 0x40 to 0x3FFF */    

+} ETH_DMAConfigTypeDef;

+/** 

+  * 

+  */

+

+/** 

+  * @brief  HAL ETH Media Interfaces enum definition  

+  */ 

+typedef enum

+{

+  HAL_ETH_MII_MODE             = 0x00U,   /*!<  Media Independent Interface               */

+  HAL_ETH_RMII_MODE            = 0x01U    /*!<   Reduced Media Independent Interface       */

+}ETH_MediaInterfaceTypeDef;

+/** 

+  * 

+  */

+

+/** 

+  * @brief  ETH Init Structure definition  

+  */

+typedef struct

+{

+   

+  uint8_t                     *MACAddr;                  /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */

+  	

+  ETH_MediaInterfaceTypeDef   MediaInterface;            /*!< Selects the MII interface or the RMII interface. */

+

+  ETH_DMADescTypeDef          *TxDesc;                   /*!< Provides the address of the first DMA Tx descriptor in the list */

+  

+  ETH_DMADescTypeDef          *RxDesc;                   /*!< Provides the address of the first DMA Rx descriptor in the list */

+  

+  uint32_t                    RxBuffLen;                 /*!< Provides the length of Rx buffers size */

+

+}ETH_InitTypeDef;

+/** 

+  * 

+  */

+

+/** 

+  * @brief  HAL State structures definition  

+  */ 

+typedef uint32_t HAL_ETH_StateTypeDef;

+/** 

+  * 

+  */

+

+/** 

+  * @brief  ETH Handle Structure definition  

+  */

+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)

+typedef struct __ETH_HandleTypeDef

+#else

+typedef struct

+#endif

+{

+  ETH_TypeDef                *Instance;                 /*!< Register base address       */

+  

+  ETH_InitTypeDef            Init;                      /*!< Ethernet Init Configuration */

+	

+  ETH_TxDescListTypeDef      TxDescList;                /*!< Tx descriptor wrapper: holds all Tx descriptors list 

+                                                            addresses and current descriptor index  */

+		

+  ETH_RxDescListTypeDef      RxDescList;                /*!< Rx descriptor wrapper: holds all Rx descriptors list 

+                                                            addresses and current descriptor index  */ 

+  

+  HAL_LockTypeDef            Lock;                      /*!< Locking object             */

+ 

+  __IO HAL_ETH_StateTypeDef  gState;                   /*!< ETH state information related to global Handle management 

+                                                              and also related to Tx operations.

+                                                             This parameter can be a value of @ref HAL_ETH_StateTypeDef */

+  

+  __IO HAL_ETH_StateTypeDef  RxState;                   /*!< ETH state information related to Rx operations.

+                                                             This parameter can be a value of @ref HAL_ETH_StateTypeDef */

+  

+  __IO uint32_t              ErrorCode;                 /*!< Holds the global Error code of the ETH HAL status machine 

+                                                             This parameter can be a value of of @ref ETH_Error_Code */

+  

+  __IO uint32_t              DMAErrorCode;              /*!< Holds the DMA Rx Tx Error code when a DMA AIS interrupt occurs

+                                                             This parameter can be a combination of @ref ETH_DMA_Status_Flags */

+  

+  __IO uint32_t              MACErrorCode;              /*!< Holds the MAC Rx Tx Error code when a MAC Rx or Tx status interrupt occurs

+                                                             This parameter can be a combination of @ref ETH_MAC_Rx_Tx_Status */ 

+    

+  __IO uint32_t              MACWakeUpEvent;            /*!< Holds the Wake Up event when the MAC exit the power down mode

+                                                             This parameter can be a value of @ref ETH_MAC_Wake_Up_Event */

+    

+  __IO uint32_t              MACLPIEvent;               /*!< Holds the LPI event when the an LPI status interrupt occurs.

+                                                             This parameter can be a value of @ref ETHEx_LPI_Event */

+                                                             

+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)

+

+  void    (* TxCpltCallback)     ( struct __ETH_HandleTypeDef * heth);   /*!< ETH Tx Complete Callback */

+  void    (* RxCpltCallback)     ( struct __ETH_HandleTypeDef * heth);  /*!< ETH Rx  Complete Callback     */

+  void    (* DMAErrorCallback)   ( struct __ETH_HandleTypeDef * heth);  /*!< ETH DMA Error Callback   */

+  void    (* MACErrorCallback)   ( struct __ETH_HandleTypeDef * heth);  /*!< ETH MAC Error Callback     */

+  void    (* PMTCallback)        ( struct __ETH_HandleTypeDef * heth);  /*!< ETH Power Management Callback            */

+  void    (* EEECallback)        ( struct __ETH_HandleTypeDef * heth);  /*!< ETH EEE Callback   */

+  void    (* WakeUpCallback)     ( struct __ETH_HandleTypeDef * heth);  /*!< ETH Wake UP Callback   */

+

+  void    (* MspInitCallback)    ( struct __ETH_HandleTypeDef * heth);    /*!< ETH Msp Init callback              */

+  void    (* MspDeInitCallback)  ( struct __ETH_HandleTypeDef * heth);    /*!< ETH Msp DeInit callback            */

+

+#endif  /* USE_HAL_ETH_REGISTER_CALLBACKS */                                                             

+

+} ETH_HandleTypeDef;

+/** 

+  * 

+  */

+  

+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  HAL ETH Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_ETH_MSPINIT_CB_ID            = 0x00U,    /*!< ETH MspInit callback ID           */

+  HAL_ETH_MSPDEINIT_CB_ID          = 0x01U,    /*!< ETH MspDeInit callback ID         */

+	

+  HAL_ETH_TX_COMPLETE_CB_ID        = 0x02U,    /*!< ETH Tx Complete Callback ID       */

+  HAL_ETH_RX_COMPLETE_CB_ID        = 0x03U,    /*!< ETH Rx Complete Callback ID       */

+  HAL_ETH_DMA_ERROR_CB_ID          = 0x04U,    /*!< ETH DMA Error Callback ID         */

+  HAL_ETH_MAC_ERROR_CB_ID          = 0x05U,    /*!< ETH MAC Error Callback ID         */

+  HAL_ETH_PMT_CB_ID                = 0x06U,     /*!< ETH Power Management Callback ID  */

+  HAL_ETH_EEE_CB_ID                = 0x07U,     /*!< ETH EEE Callback ID               */

+  HAL_ETH_WAKEUP_CB_ID             = 0x08U     /*!< ETH Wake UP Callback ID           */

+

+

+}HAL_ETH_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL ETH Callback pointer definition

+  */

+typedef  void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef * heth); /*!< pointer to an ETH callback function */

+

+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */

+

+/** 

+  * @brief  ETH MAC filter structure definition

+  */

+typedef struct{

+  FunctionalState PromiscuousMode;          /*!< Enable or Disable Promiscuous Mode */

+  

+  FunctionalState ReceiveAllMode;           /*!< Enable or Disable Receive All Mode */

+  

+  FunctionalState HachOrPerfectFilter;      /*!< Enable or Disable Perfect filtering in addition to Hash filtering */

+  

+  FunctionalState HashUnicast;              /*!< Enable or Disable Hash filtering on unicast packets */

+  

+  FunctionalState HashMulticast;            /*!< Enable or Disable Hash filtering on multicast packets */

+  

+  FunctionalState PassAllMulticast;         /*!< Enable or Disable passing all multicast packets */

+  

+  FunctionalState SrcAddrFiltering;         /*!< Enable or Disable source address filtering module */

+  

+  FunctionalState SrcAddrInverseFiltering;  /*!< Enable or Disable source address inverse filtering */

+  

+  FunctionalState DestAddrInverseFiltering; /*!< Enable or Disable destination address inverse filtering */

+  

+  FunctionalState BroadcastFilter;          /*!< Enable or Disable broadcast filter */

+  

+  uint32_t        ControlPacketsFilter;     /*!< Set the control packets filter

+                                                 This parameter can be a value of @ref ETH_Control_Packets_Filter */

+}ETH_MACFilterConfigTypeDef;

+/** 

+  * 

+  */

+    

+/** 

+  * @brief  ETH Power Down structure definition

+  */

+typedef struct{

+  FunctionalState WakeUpPacket;    /*!< Enable or Disable Wake up packet detection in power down mode */

+  

+  FunctionalState MagicPacket;     /*!< Enable or Disable Magic packet detection in power down mode */

+  

+  FunctionalState GlobalUnicast;    /*!< Enable or Disable Global unicast packet detection in power down mode */

+  

+  FunctionalState WakeUpForward;    /*!< Enable or Disable Forwarding Wake up packets */

+  	

+}ETH_PowerDownConfigTypeDef;

+/** 

+  * 

+  */

+  

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup ETH_Exported_Constants ETH Exported Constants

+  * @{

+  */

+

+/** @defgroup ETH_DMA_Tx_Descriptor_Bit_Definition ETH DMA Tx Descriptor Bit Definition

+  * @{

+  */

+

+/*

+   DMA Tx Normal Desciptor Read Format

+  -----------------------------------------------------------------------------------------------

+  TDES0 |                         Buffer1 or Header Address  [31:0]                              |

+  -----------------------------------------------------------------------------------------------

+  TDES1 |                   Buffer2 Address [31:0] / Next Descriptor Address [31:0]              |

+  -----------------------------------------------------------------------------------------------

+  TDES2 | IOC(31) | TTSE(30) | Buff2 Length[29:16] | VTIR[15:14] | Header or Buff1 Length[13:0]  |

+  -----------------------------------------------------------------------------------------------

+  TDES3 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |

+  -----------------------------------------------------------------------------------------------

+*/

+

+/** 

+  * @brief  Bit definition of TDES0 RF register

+  */ 

+#define ETH_DMATXNDESCRF_B1AP  ((uint32_t)0xFFFFFFFFU)  /*!< Transmit Packet Timestamp Low */

+

+/** 

+  * @brief  Bit definition of TDES1 RF register

+  */ 

+#define ETH_DMATXNDESCRF_B2AP  ((uint32_t)0xFFFFFFFFU)  /*!< Transmit Packet Timestamp High */

+

+/** 

+  * @brief  Bit definition of TDES2 RF register

+  */ 

+#define ETH_DMATXNDESCRF_IOC          ((uint32_t)0x80000000U)  /*!< Interrupt on Completion */

+#define ETH_DMATXNDESCRF_TTSE         ((uint32_t)0x40000000U)  /*!< Transmit Timestamp Enable */

+#define ETH_DMATXNDESCRF_B2L          ((uint32_t)0x3FFF0000U)  /*!< Buffer 2 Length */

+#define ETH_DMATXNDESCRF_VTIR         ((uint32_t)0x0000C000U)  /*!< VLAN Tag Insertion or Replacement mask */

+#define ETH_DMATXNDESCRF_VTIR_DISABLE ((uint32_t)0x00000000U)  /*!< Do not add a VLAN tag. */

+#define ETH_DMATXNDESCRF_VTIR_REMOVE  ((uint32_t)0x00004000U)  /*!< Remove the VLAN tag from the packets before transmission. */

+#define ETH_DMATXNDESCRF_VTIR_INSERT  ((uint32_t)0x00008000U)  /*!< Insert a VLAN tag. */

+#define ETH_DMATXNDESCRF_VTIR_REPLACE ((uint32_t)0x0000C000U)  /*!< Replace the VLAN tag. */

+#define ETH_DMATXNDESCRF_B1L          ((uint32_t)0x00003FFFU)  /*!< Buffer 1 Length */

+#define ETH_DMATXNDESCRF_HL           ((uint32_t)0x000003FFU)  /*!< Header Length */

+

+/** 

+  * @brief  Bit definition of TDES3 RF register

+  */ 

+#define ETH_DMATXNDESCRF_OWN                                 ((uint32_t)0x80000000U)  /*!< OWN bit: descriptor is owned by DMA engine */

+#define ETH_DMATXNDESCRF_CTXT                                ((uint32_t)0x40000000U)  /*!< Context Type */

+#define ETH_DMATXNDESCRF_FD                                  ((uint32_t)0x20000000U)  /*!< First Descriptor */

+#define ETH_DMATXNDESCRF_LD                                  ((uint32_t)0x10000000U)  /*!< Last Descriptor */

+#define ETH_DMATXNDESCRF_CPC                                 ((uint32_t)0x0C000000U)  /*!< CRC Pad Control mask */

+#define ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT                   ((uint32_t)0x00000000U)  /*!< CRC Pad Control: CRC and Pad Insertion */

+#define ETH_DMATXNDESCRF_CPC_CRC_INSERT                      ((uint32_t)0x04000000U)  /*!< CRC Pad Control: CRC Insertion (Disable Pad Insertion) */

+#define ETH_DMATXNDESCRF_CPC_DISABLE                         ((uint32_t)0x08000000U)  /*!< CRC Pad Control: Disable CRC Insertion */

+#define ETH_DMATXNDESCRF_CPC_CRC_REPLACE                     ((uint32_t)0x0C000000U)  /*!< CRC Pad Control: CRC Replacement */

+#define ETH_DMATXNDESCRF_SAIC                                ((uint32_t)0x03800000U)  /*!< SA Insertion Control mask*/

+#define ETH_DMATXNDESCRF_SAIC_DISABLE                        ((uint32_t)0x00000000U)  /*!< SA Insertion Control: Do not include the source address */

+#define ETH_DMATXNDESCRF_SAIC_INSERT                         ((uint32_t)0x00800000U)  /*!< SA Insertion Control: Include or insert the source address */

+#define ETH_DMATXNDESCRF_SAIC_REPLACE                        ((uint32_t)0x01000000U)  /*!< SA Insertion Control: Replace the source address */

+#define ETH_DMATXNDESCRF_THL                                 ((uint32_t)0x00780000U)  /*!< TCP Header Length */

+#define ETH_DMATXNDESCRF_TSE                                 ((uint32_t)0x00040000U)  /*!< TCP segmentation enable */

+#define ETH_DMATXNDESCRF_CIC                                 ((uint32_t)0x00030000U)  /*!< Checksum Insertion Control: 4 cases */ 

+#define ETH_DMATXNDESCRF_CIC_DISABLE                         ((uint32_t)0x00000000U)  /*!< Do Nothing: Checksum Engine is disabled */ 

+#define ETH_DMATXNDESCRF_CIC_IPHDR_INSERT                    ((uint32_t)0x00010000U)  /*!< Only IP header checksum calculation and insertion are enabled. */ 

+#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT            ((uint32_t)0x00020000U)  /*!< IP header checksum and payload checksum calculation and insertion are

+                                                                                          enabled, but pseudo header checksum is not calculated in hardware */ 

+#define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC  ((uint32_t)0x00030000U)  /*!< IP Header checksum and payload checksum calculation and insertion are

+                                                                                          enabled, and pseudo header checksum is calculated in hardware. */ 

+#define ETH_DMATXNDESCRF_TPL                                 ((uint32_t)0x0003FFFFU)  /*!< TCP Payload Length */

+#define ETH_DMATXNDESCRF_FL                                  ((uint32_t)0x00007FFFU)  /*!< Transmit End of Ring */

+

+/*

+   DMA Tx Normal Descriptor Write Back Format

+  -----------------------------------------------------------------------------------------------

+  TDES0 |                         Timestamp Low                                                  |

+  -----------------------------------------------------------------------------------------------

+  TDES1 |                         Timestamp High                                                 |

+  -----------------------------------------------------------------------------------------------

+  TDES2 |                           Reserved[31:0]                                               |

+  -----------------------------------------------------------------------------------------------

+  TDES3 | OWN(31) |                          Status[30:0]                                        |

+  -----------------------------------------------------------------------------------------------

+*/

+

+/** 

+  * @brief  Bit definition of TDES0 WBF register

+  */ 

+#define ETH_DMATXNDESCWBF_TTSL  ((uint32_t)0xFFFFFFFFU)  /*!< Buffer1 Address Pointer or TSO Header Address Pointer */

+

+/** 

+  * @brief  Bit definition of TDES1 WBF register

+  */ 

+#define ETH_DMATXNDESCWBF_TTSH  ((uint32_t)0xFFFFFFFFU)  /*!< Buffer2 Address Pointer */

+

+/** 

+  * @brief  Bit definition of TDES3 WBF register

+  */ 

+#define ETH_DMATXNDESCWBF_OWN                     ((uint32_t)0x80000000U)  /*!< OWN bit: descriptor is owned by DMA engine */

+#define ETH_DMATXNDESCWBF_CTXT                    ((uint32_t)0x40000000U)  /*!< Context Type */

+#define ETH_DMATXNDESCWBF_FD                      ((uint32_t)0x20000000U)  /*!< First Descriptor */

+#define ETH_DMATXNDESCWBF_LD                      ((uint32_t)0x10000000U)  /*!< Last Descriptor */

+#define ETH_DMATXNDESCWBF_TTSS                    ((uint32_t)0x00020000U)  /*!< Tx Timestamp Status */

+#define ETH_DMATXNDESCWBF_DP                      ((uint32_t)0x04000000U)  /*!< Disable Padding */

+#define ETH_DMATXNDESCWBF_TTSE                    ((uint32_t)0x02000000U)  /*!< Transmit Timestamp Enable */

+#define ETH_DMATXNDESCWBF_ES                      ((uint32_t)0x00008000U)  /*!< Error summary: OR of the following bits: IHE || UF || ED || EC || LCO || PCE || NC || LCA || FF || JT */

+#define ETH_DMATXNDESCWBF_JT                      ((uint32_t)0x00004000U)  /*!< Jabber Timeout */

+#define ETH_DMATXNDESCWBF_FF                      ((uint32_t)0x00002000U)  /*!< Packet Flushed: DMA/MTL flushed the packet due to SW flush */

+#define ETH_DMATXNDESCWBF_PCE                     ((uint32_t)0x00001000U)  /*!< Payload Checksum Error */

+#define ETH_DMATXNDESCWBF_LCA                     ((uint32_t)0x00000800U)  /*!< Loss of Carrier: carrier lost during transmission */

+#define ETH_DMATXNDESCWBF_NC                      ((uint32_t)0x00000400U)  /*!< No Carrier: no carrier signal from the transceiver */

+#define ETH_DMATXNDESCWBF_LCO                     ((uint32_t)0x00000200U)  /*!< Late Collision: transmission aborted due to collision */

+#define ETH_DMATXNDESCWBF_EC                      ((uint32_t)0x00000100U)  /*!< Excessive Collision: transmission aborted after 16 collisions */

+#define ETH_DMATXNDESCWBF_CC                      ((uint32_t)0x000000F0U)  /*!< Collision Count */

+#define ETH_DMATXNDESCWBF_ED                      ((uint32_t)0x00000008U)  /*!< Excessive Deferral */

+#define ETH_DMATXNDESCWBF_UF                      ((uint32_t)0x00000004U)  /*!< Underflow Error: late data arrival from the memory */

+#define ETH_DMATXNDESCWBF_DB                      ((uint32_t)0x00000002U)  /*!< Deferred Bit */

+#define ETH_DMATXNDESCWBF_IHE                     ((uint32_t)0x00000004U)  /*!< IP Header Error */

+

+

+/*

+   DMA Tx Context Desciptor

+  -----------------------------------------------------------------------------------------------

+  TDES0 |                               Timestamp Low                                            |

+  -----------------------------------------------------------------------------------------------

+  TDES1 |                               Timestamp High                                           |

+  -----------------------------------------------------------------------------------------------

+  TDES2 |      Inner VLAN Tag[31:16]    | Reserved(15) |     Maximum Segment Size [14:0]         |

+  -----------------------------------------------------------------------------------------------

+  TDES3 | OWN(31) |                          Status[30:0]                                        |

+  -----------------------------------------------------------------------------------------------

+*/

+

+/** 

+  * @brief  Bit definition of Tx context descriptor register 0

+  */ 

+#define ETH_DMATXCDESC_TTSL  ((uint32_t)0xFFFFFFFFU)  /*!< Transmit Packet Timestamp Low */

+

+/** 

+  * @brief  Bit definition of Tx context descriptor register 1

+  */ 

+#define ETH_DMATXCDESC_TTSH  ((uint32_t)0xFFFFFFFFU)  /*!< Transmit Packet Timestamp High */

+

+/** 

+  * @brief  Bit definition of Tx context descriptor register 2

+  */ 

+#define ETH_DMATXCDESC_IVT   ((uint32_t)0xFFFF0000U)  /*!< Inner VLAN Tag */

+#define ETH_DMATXCDESC_MSS   ((uint32_t)0x00003FFFU)  /*!< Maximum Segment Size */

+

+/** 

+  * @brief  Bit definition of Tx context descriptor register 3

+  */

+#define ETH_DMATXCDESC_OWN                     ((uint32_t)0x80000000U)     /*!< OWN bit: descriptor is owned by DMA engine */

+#define ETH_DMATXCDESC_CTXT                    ((uint32_t)0x40000000U)     /*!< Context Type */

+#define ETH_DMATXCDESC_OSTC                    ((uint32_t)0x08000000U)     /*!< One-Step Timestamp Correction Enable */

+#define ETH_DMATXCDESC_TCMSSV                  ((uint32_t)0x04000000U)     /*!< One-Step Timestamp Correction Input or MSS Valid */

+#define ETH_DMATXCDESC_CDE                     ((uint32_t)0x00800000U)     /*!< Context Descriptor Error */

+#define ETH_DMATXCDESC_IVTIR                   ((uint32_t)0x000C0000U)     /*!< Inner VLAN Tag Insert or Replace Mask */

+#define ETH_DMATXCDESC_IVTIR_DISABLE           ((uint32_t)0x00000000U)     /*!< Do not add the inner VLAN tag. */

+#define ETH_DMATXCDESC_IVTIR_REMOVE            ((uint32_t)0x00040000U)     /*!< Remove the inner VLAN tag from the packets before transmission. */

+#define ETH_DMATXCDESC_IVTIR_INSERT            ((uint32_t)0x00080000U)     /*!< Insert the inner VLAN tag. */

+#define ETH_DMATXCDESC_IVTIR_REPLACE           ((uint32_t)0x000C0000U)     /*!< Replace the inner VLAN tag. */

+#define ETH_DMATXCDESC_IVLTV                   ((uint32_t)0x00020000U)     /*!< Inner VLAN Tag Valid */

+#define ETH_DMATXCDESC_VLTV                    ((uint32_t)0x00010000U)     /*!< VLAN Tag Valid */

+#define ETH_DMATXCDESC_VT                      ((uint32_t)0x0000FFFFU)     /*!< VLAN Tag */

+

+/**

+  * @}

+  */ 

+

+

+/** @defgroup ETH_DMA_Rx_Descriptor_Bit_Definition ETH DMA Rx Descriptor Bit Definition

+  * @{

+  */

+

+/*

+  DMA Rx Normal Descriptor read format

+  -----------------------------------------------------------------------------------------------------------

+  RDES0 |                                  Buffer1 or Header Address [31:0]                                 |

+  -----------------------------------------------------------------------------------------------------------

+  RDES1 |                                            Reserved                                               |

+  -----------------------------------------------------------------------------------------------------------

+  RDES2 |                                      Payload or Buffer2 Address[31:0]                             |

+  -----------------------------------------------------------------------------------------------------------

+  RDES3 | OWN(31) | IOC(30) | Reserved [29:26] | BUF2V(25) | BUF1V(24) |           Reserved [23:0]          |

+  -----------------------------------------------------------------------------------------------------------

+*/

+

+/** 

+  * @brief  Bit definition of Rx normal descriptor register 0 read format

+  */

+#define ETH_DMARXNDESCRF_BUF1AP        ((uint32_t)0xFFFFFFFFU)  /*!< Header or Buffer 1 Address Pointer  */

+

+/** 

+  * @brief  Bit definition of Rx normal descriptor register 2 read format

+  */

+#define ETH_DMARXNDESCRF_BUF2AP        ((uint32_t)0xFFFFFFFFU)  /*!< Buffer 2 Address Pointer  */

+

+/** 

+  * @brief  Bit definition of Rx normal descriptor register 3 read format

+  */

+#define ETH_DMARXNDESCRF_OWN         ((uint32_t)0x80000000U)  /*!< OWN bit: descriptor is owned by DMA engine  */

+#define ETH_DMARXNDESCRF_IOC         ((uint32_t)0x40000000U)  /*!< Interrupt Enabled on Completion  */

+#define ETH_DMARXNDESCRF_BUF2V       ((uint32_t)0x02000000U)  /*!< Buffer 2 Address Valid */

+#define ETH_DMARXNDESCRF_BUF1V       ((uint32_t)0x01000000U)  /*!< Buffer 1 Address Valid */

+

+/*

+  DMA Rx Normal Descriptor write back format

+  ---------------------------------------------------------------------------------------------------------------------

+  RDES0 |                 Inner VLAN Tag[31:16]                 |                 Outer VLAN Tag[15:0]                | 

+	---------------------------------------------------------------------------------------------------------------------

+  RDES1 |       OAM code, or MAC Control Opcode [31:16]         |               Extended Status                       |

+  ---------------------------------------------------------------------------------------------------------------------

+  RDES2 |      MAC Filter Status[31:16]        | VF(15) | Reserved [14:12] | ARP Status [11:10] | Header Length [9:0] |

+  ---------------------------------------------------------------------------------------------------------------------

+  RDES3 | OWN(31) | CTXT(30) |  FD(29) | LD(28) |   Status[27:16]     | ES(15) |        Packet Length[14:0]           |

+  ---------------------------------------------------------------------------------------------------------------------

+*/

+

+/** 

+  * @brief  Bit definition of Rx normal descriptor register 0 write back format

+  */

+#define ETH_DMARXNDESCWBF_IVT        ((uint32_t)0xFFFF0000U)  /*!< Inner VLAN Tag  */

+#define ETH_DMARXNDESCWBF_OVT        ((uint32_t)0x0000FFFFU)  /*!< Outer VLAN Tag  */

+

+/** 

+  * @brief  Bit definition of Rx normal descriptor register 1 write back format

+  */

+#define ETH_DMARXNDESCWBF_OPC             ((uint32_t)0xFFFF0000U)  /*!< OAM Sub-Type Code, or MAC Control Packet opcode  */

+#define ETH_DMARXNDESCWBF_TD              ((uint32_t)0x00008000U)  /*!< Timestamp Dropped  */

+#define ETH_DMARXNDESCWBF_TSA             ((uint32_t)0x00004000U)  /*!< Timestamp Available  */

+#define ETH_DMARXNDESCWBF_PV              ((uint32_t)0x00002000U)  /*!< PTP Version  */

+#define ETH_DMARXNDESCWBF_PFT             ((uint32_t)0x00001000U)  /*!< PTP Packet Type  */

+#define ETH_DMARXNDESCWBF_PMT_NO          ((uint32_t)0x00000000U)  /*!< PTP Message Type: No PTP message received  */

+#define ETH_DMARXNDESCWBF_PMT_SYNC        ((uint32_t)0x00000100U)  /*!< PTP Message Type: SYNC (all clock types)  */

+#define ETH_DMARXNDESCWBF_PMT_FUP         ((uint32_t)0x00000200U)  /*!< PTP Message Type: Follow_Up (all clock types)  */

+#define ETH_DMARXNDESCWBF_PMT_DREQ        ((uint32_t)0x00000300U)  /*!< PTP Message Type: Delay_Req (all clock types)  */

+#define ETH_DMARXNDESCWBF_PMT_DRESP       ((uint32_t)0x00000400U)  /*!< PTP Message Type: Delay_Resp (all clock types)  */

+#define ETH_DMARXNDESCWBF_PMT_PDREQ       ((uint32_t)0x00000500U)  /*!< PTP Message Type: Pdelay_Req (in peer-to-peer transparent clock)  */

+#define ETH_DMARXNDESCWBF_PMT_PDRESP      ((uint32_t)0x00000600U)  /*!< PTP Message Type: Pdelay_Resp (in peer-to-peer transparent clock)  */

+#define ETH_DMARXNDESCWBF_PMT_PDRESPFUP   ((uint32_t)0x00000700U)  /*!< PTP Message Type: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock)  */

+#define ETH_DMARXNDESCWBF_PMT_ANNOUNCE    ((uint32_t)0x00000800U)  /*!< PTP Message Type: Announce  */

+#define ETH_DMARXNDESCWBF_PMT_MANAG       ((uint32_t)0x00000900U)  /*!< PTP Message Type: Management  */

+#define ETH_DMARXNDESCWBF_PMT_SIGN        ((uint32_t)0x00000A00U)  /*!< PTP Message Type: Signaling  */

+#define ETH_DMARXNDESCWBF_PMT_RESERVED    ((uint32_t)0x00000F00U)  /*!< PTP Message Type: PTP packet with Reserved message type  */

+#define ETH_DMARXNDESCWBF_IPCE            ((uint32_t)0x00000080U)  /*!< IP Payload Error */

+#define ETH_DMARXNDESCWBF_IPCB            ((uint32_t)0x00000040U)  /*!< IP Checksum Bypassed */

+#define ETH_DMARXNDESCWBF_IPV6            ((uint32_t)0x00000020U)  /*!< IPv6 header Present */

+#define ETH_DMARXNDESCWBF_IPV4            ((uint32_t)0x00000010U)  /*!< IPv4 header Present */

+#define ETH_DMARXNDESCWBF_IPHE            ((uint32_t)0x00000008U)  /*!< IP Header Error */

+#define ETH_DMARXNDESCWBF_PT              ((uint32_t)0x00000003U)  /*!< Payload Type mask */

+#define ETH_DMARXNDESCWBF_PT_UNKNOWN      ((uint32_t)0x00000000U)  /*!< Payload Type: Unknown type or IP/AV payload not processed */

+#define ETH_DMARXNDESCWBF_PT_UDP          ((uint32_t)0x00000001U)  /*!< Payload Type: UDP */

+#define ETH_DMARXNDESCWBF_PT_TCP          ((uint32_t)0x00000002U)  /*!< Payload Type: TCP  */

+#define ETH_DMARXNDESCWBF_PT_ICMP         ((uint32_t)0x00000003U)  /*!< Payload Type: ICMP */

+

+/** 

+  * @brief  Bit definition of Rx normal descriptor register 2 write back format

+  */

+#define ETH_DMARXNDESCWBF_L3L4FM          ((uint32_t)0x20000000U)  /*!< L3 and L4 Filter Number Matched: if reset filter 0 is matched , if set filter 1 is matched */

+#define ETH_DMARXNDESCWBF_L4FM            ((uint32_t)0x10000000U)  /*!< Layer 4 Filter Match                  */

+#define ETH_DMARXNDESCWBF_L3FM            ((uint32_t)0x08000000U)  /*!< Layer 3 Filter Match                  */

+#define ETH_DMARXNDESCWBF_MADRM           ((uint32_t)0x07F80000U)  /*!< MAC Address Match or Hash Value       */

+#define ETH_DMARXNDESCWBF_HF              ((uint32_t)0x00040000U)  /*!< Hash Filter Status                    */

+#define ETH_DMARXNDESCWBF_DAF             ((uint32_t)0x00020000U)  /*!< Destination Address Filter Fail       */

+#define ETH_DMARXNDESCWBF_SAF             ((uint32_t)0x00010000U)  /*!< SA Address Filter Fail                */

+#define ETH_DMARXNDESCWBF_VF              ((uint32_t)0x00008000U)  /*!< VLAN Filter Status                    */

+#define ETH_DMARXNDESCWBF_ARPNR           ((uint32_t)0x00000400U)  /*!< ARP Reply Not Generated               */

+

+

+/** 

+  * @brief  Bit definition of Rx normal descriptor register 3 write back format

+  */

+#define ETH_DMARXNDESCWBF_OWN        ((uint32_t)0x80000000U)  /*!< Own Bit */

+#define ETH_DMARXNDESCWBF_CTXT       ((uint32_t)0x40000000U)  /*!< Receive Context Descriptor */

+#define ETH_DMARXNDESCWBF_FD         ((uint32_t)0x20000000U)  /*!< First Descriptor */

+#define ETH_DMARXNDESCWBF_LD         ((uint32_t)0x10000000U)  /*!< Last Descriptor */

+#define ETH_DMARXNDESCWBF_RS2V       ((uint32_t)0x08000000U)  /*!< Receive Status RDES2 Valid */

+#define ETH_DMARXNDESCWBF_RS1V       ((uint32_t)0x04000000U)  /*!< Receive Status RDES1 Valid */

+#define ETH_DMARXNDESCWBF_RS0V       ((uint32_t)0x02000000U)  /*!< Receive Status RDES0 Valid */

+#define ETH_DMARXNDESCWBF_CE         ((uint32_t)0x01000000U)  /*!< CRC Error */

+#define ETH_DMARXNDESCWBF_GP         ((uint32_t)0x00800000U)  /*!< Giant Packet */

+#define ETH_DMARXNDESCWBF_RWT        ((uint32_t)0x00400000U)  /*!< Receive Watchdog Timeout */

+#define ETH_DMARXNDESCWBF_OE         ((uint32_t)0x00200000U)  /*!< Overflow Error */

+#define ETH_DMARXNDESCWBF_RE         ((uint32_t)0x00100000U)  /*!< Receive Error */

+#define ETH_DMARXNDESCWBF_DE         ((uint32_t)0x00080000U)  /*!< Dribble Bit Error */

+#define ETH_DMARXNDESCWBF_LT         ((uint32_t)0x00070000U)  /*!< Length/Type Field */

+#define ETH_DMARXNDESCWBF_LT_LP      ((uint32_t)0x00000000U)  /*!< The packet is a length packet */

+#define ETH_DMARXNDESCWBF_LT_TP      ((uint32_t)0x00010000U)  /*!< The packet is a type packet */

+#define ETH_DMARXNDESCWBF_LT_ARP     ((uint32_t)0x00030000U)  /*!< The packet is a ARP Request packet type */

+#define ETH_DMARXNDESCWBF_LT_VLAN    ((uint32_t)0x00040000U)  /*!< The packet is a type packet with VLAN Tag */

+#define ETH_DMARXNDESCWBF_LT_DVLAN   ((uint32_t)0x00050000U)  /*!< The packet is a type packet with Double VLAN Tag */

+#define ETH_DMARXNDESCWBF_LT_MAC     ((uint32_t)0x00060000U)  /*!< The packet is a MAC Control packet type */

+#define ETH_DMARXNDESCWBF_LT_OAM     ((uint32_t)0x00070000U)  /*!< The packet is a OAM packet type */

+#define ETH_DMARXNDESCWBF_ES         ((uint32_t)0x00008000U)  /*!< Error Summary */

+#define ETH_DMARXNDESCWBF_PL         ((uint32_t)0x00007FFFU)  /*!< Packet Length */

+

+/*

+  DMA Rx context Descriptor

+  ---------------------------------------------------------------------------------------------------------------------

+  RDES0 |                                     Timestamp Low[31:0]                                                     | 

+	---------------------------------------------------------------------------------------------------------------------

+  RDES1 |                                     Timestamp High[31:0]                                                    |

+  ---------------------------------------------------------------------------------------------------------------------

+  RDES2 |                                          Reserved                                                           |

+  ---------------------------------------------------------------------------------------------------------------------

+  RDES3 | OWN(31) | CTXT(30) |                                Reserved[29:0]                                          |

+  ---------------------------------------------------------------------------------------------------------------------

+*/

+

+/** 

+  * @brief  Bit definition of Rx context descriptor register 0 

+  */

+#define ETH_DMARXCDESC_RTSL        ((uint32_t)0xFFFFFFFFU)  /*!< Receive Packet Timestamp Low  */

+

+/** 

+  * @brief  Bit definition of Rx context descriptor register 1

+  */

+#define ETH_DMARXCDESC_RTSH        ((uint32_t)0xFFFFFFFFU)  /*!< Receive Packet Timestamp High  */

+

+/** 

+  * @brief  Bit definition of Rx context descriptor register 3

+  */

+#define ETH_DMARXCDESC_OWN        ((uint32_t)0x80000000U)  /*!< Own Bit  */

+#define ETH_DMARXCDESC_CTXT       ((uint32_t)0x40000000U)  /*!< Receive Context Descriptor  */

+

+/**

+  * @}

+  */

+

+/** @defgroup ETH_Frame_settings ETH frame settings

+  * @{

+  */ 

+#define ETH_MAX_PACKET_SIZE      ((uint32_t)1528U)    /*!< ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */

+#define ETH_HEADER               ((uint32_t)14U)    /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */

+#define ETH_CRC                  ((uint32_t)4U)    /*!< Ethernet CRC */

+#define ETH_VLAN_TAG             ((uint32_t)4U)    /*!< optional 802.1q VLAN Tag */

+#define ETH_MIN_PAYLOAD          ((uint32_t)46U)    /*!< Minimum Ethernet payload size */

+#define ETH_MAX_PAYLOAD          ((uint32_t)1500U)    /*!< Maximum Ethernet payload size */

+#define ETH_JUMBO_FRAME_PAYLOAD  ((uint32_t)9000U)    /*!< Jumbo frame payload size */

+/**

+  * @}

+  */

+

+/** @defgroup ETH_Error_Code ETH Error Code

+  * @{

+  */ 

+#define HAL_ETH_ERROR_NONE         ((uint32_t)0x00000000U)   /*!< No error            */

+#define HAL_ETH_ERROR_PARAM        ((uint32_t)0x00000001U)   /*!< Busy error          */

+#define HAL_ETH_ERROR_BUSY         ((uint32_t)0x00000002U)   /*!< Parameter error     */

+#define HAL_ETH_ERROR_TIMEOUT      ((uint32_t)0x00000004U)   /*!< Timeout error       */

+#define HAL_ETH_ERROR_DMA          ((uint32_t)0x00000008U)   /*!< DMA transfer error  */

+#define HAL_ETH_ERROR_MAC          ((uint32_t)0x00000010U)   /*!< MAC transfer error  */

+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)

+#define HAL_ETH_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U)    /*!< Invalid Callback error  */

+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/** @defgroup ETH_Tx_Packet_Attributes ETH Tx Packet Attributes

+  * @{

+  */

+#define ETH_TX_PACKETS_FEATURES_CSUM          ((uint32_t)0x00000001U)

+#define ETH_TX_PACKETS_FEATURES_SAIC          ((uint32_t)0x00000002U)

+#define ETH_TX_PACKETS_FEATURES_VLANTAG       ((uint32_t)0x00000004U)

+#define ETH_TX_PACKETS_FEATURES_INNERVLANTAG  ((uint32_t)0x00000008U)

+#define ETH_TX_PACKETS_FEATURES_TSO           ((uint32_t)0x00000010U)

+#define ETH_TX_PACKETS_FEATURES_CRCPAD        ((uint32_t)0x00000020U)

+/**

+  * @}

+  */

+

+/** @defgroup ETH_Tx_Packet_Source_Addr_Control ETH Tx Packet Source Addr Control

+  * @{

+  */

+#define ETH_SRC_ADDR_CONTROL_DISABLE          ETH_DMATXNDESCRF_SAIC_DISABLE

+#define ETH_SRC_ADDR_INSERT                   ETH_DMATXNDESCRF_SAIC_INSERT

+#define ETH_SRC_ADDR_REPLACE                  ETH_DMATXNDESCRF_SAIC_REPLACE

+/**

+  * @}

+  */

+

+/** @defgroup ETH_Tx_Packet_CRC_Pad_Control ETH Tx Packet CRC Pad Control

+  * @{

+  */

+#define ETH_CRC_PAD_DISABLE      ETH_DMATXNDESCRF_CPC_DISABLE

+#define ETH_CRC_PAD_INSERT       ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT

+#define ETH_CRC_INSERT           ETH_DMATXNDESCRF_CPC_CRC_INSERT

+#define ETH_CRC_REPLACE          ETH_DMATXNDESCRF_CPC_CRC_REPLACE

+/**

+  * @}

+  */

+

+/** @defgroup ETH_Tx_Packet_Checksum_Control ETH Tx Packet Checksum Control

+  * @{

+  */

+#define ETH_CHECKSUM_DISABLE                         ETH_DMATXNDESCRF_CIC_DISABLE

+#define ETH_CHECKSUM_IPHDR_INSERT                    ETH_DMATXNDESCRF_CIC_IPHDR_INSERT     

+#define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT            ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT              

+#define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC  ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC         

+/**

+  * @}

+  */

+

+/** @defgroup ETH_Tx_Packet_VLAN_Control ETH Tx Packet VLAN Control

+  * @{

+  */

+#define ETH_VLAN_DISABLE  ETH_DMATXNDESCRF_VTIR_DISABLE

+#define ETH_VLAN_REMOVE   ETH_DMATXNDESCRF_VTIR_REMOVE

+#define ETH_VLAN_INSERT   ETH_DMATXNDESCRF_VTIR_INSERT 

+#define ETH_VLAN_REPLACE  ETH_DMATXNDESCRF_VTIR_REPLACE

+/**

+  * @}

+  */

+

+/** @defgroup ETH_Tx_Packet_Inner_VLAN_Control ETH Tx Packet Inner VLAN Control

+  * @{

+  */

+#define ETH_INNER_VLAN_DISABLE  ETH_DMATXCDESC_IVTIR_DISABLE

+#define ETH_INNER_VLAN_REMOVE   ETH_DMATXCDESC_IVTIR_REMOVE

+#define ETH_INNER_VLAN_INSERT   ETH_DMATXCDESC_IVTIR_INSERT 

+#define ETH_INNER_VLAN_REPLACE  ETH_DMATXCDESC_IVTIR_REPLACE

+/**

+  * @}

+  */

+

+/** @defgroup ETH_Rx_Checksum_Status ETH Rx Checksum Status

+  * @{

+  */

+#define ETH_CHECKSUM_BYPASSED           ETH_DMARXNDESCWBF_IPCB

+#define ETH_CHECKSUM_IP_HEADER_ERROR    ETH_DMARXNDESCWBF_IPHE

+#define ETH_CHECKSUM_IP_PAYLOAD_ERROR   ETH_DMARXNDESCWBF_IPCE

+/**

+  * @}

+  */

+

+/** @defgroup ETH_Rx_IP_Header_Type ETH Rx IP Header Type

+  * @{

+  */

+#define ETH_IP_HEADER_IPV4   ETH_DMARXNDESCWBF_IPV4

+#define ETH_IP_HEADER_IPV6   ETH_DMARXNDESCWBF_IPV6

+/**

+  * @}

+  */

+

+/** @defgroup ETH_Rx_Payload_Type ETH Rx Payload Type

+  * @{

+  */

+#define ETH_IP_PAYLOAD_UNKNOWN   ETH_DMARXNDESCWBF_PT_UNKNOWN

+#define ETH_IP_PAYLOAD_UDP       ETH_DMARXNDESCWBF_PT_UDP

+#define ETH_IP_PAYLOAD_TCP       ETH_DMARXNDESCWBF_PT_TCP

+#define ETH_IP_PAYLOAD_ICMPN     ETH_DMARXNDESCWBF_PT_ICMP

+/**

+  * @}

+  */

+

+/** @defgroup ETH_Rx_MAC_Filter_Status ETH Rx MAC Filter Status

+  * @{

+  */

+#define ETH_HASH_FILTER_PASS        ETH_DMARXNDESCWBF_HF

+#define ETH_VLAN_FILTER_PASS        ETH_DMARXNDESCWBF_VF

+#define ETH_DEST_ADDRESS_FAIL       ETH_DMARXNDESCWBF_DAF

+#define ETH_SOURCE_ADDRESS_FAIL     ETH_DMARXNDESCWBF_SAF

+/**

+  * @}

+  */

+

+/** @defgroup ETH_Rx_L3_Filter_Status ETH Rx L3 Filter Status

+  * @{

+  */

+#define ETH_L3_FILTER0_MATCH        ETH_DMARXNDESCWBF_L3FM

+#define ETH_L3_FILTER1_MATCH        (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM)

+/**

+  * @}

+  */

+

+/** @defgroup ETH_Rx_L4_Filter_Status ETH Rx L4 Filter Status

+  * @{

+  */

+#define ETH_L4_FILTER0_MATCH        ETH_DMARXNDESCWBF_L4FM

+#define ETH_L4_FILTER1_MATCH        (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM)

+/**

+  * @}

+  */

+

+/** @defgroup ETH_Rx_Error_Code ETH Rx Error Code

+  * @{

+  */

+#define ETH_DRIBBLE_BIT_ERROR   ETH_DMARXNDESCWBF_DE

+#define ETH_RECEIVE_ERROR       ETH_DMARXNDESCWBF_RE

+#define ETH_RECEIVE_OVERFLOW    ETH_DMARXNDESCWBF_OE

+#define ETH_WATCHDOG_TIMEOUT    ETH_DMARXNDESCWBF_RWT

+#define ETH_GIANT_PACKET        ETH_DMARXNDESCWBF_GP

+#define ETH_CRC_ERROR           ETH_DMARXNDESCWBF_CE

+/**

+  * @}

+  */

+

+/** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration

+  * @{

+  */ 

+#define ETH_DMAARBITRATION_RX        ETH_DMAMR_DA

+#define ETH_DMAARBITRATION_RX1_TX1   ((uint32_t)0x00000000U)

+#define ETH_DMAARBITRATION_RX2_TX1   ETH_DMAMR_PR_2_1

+#define ETH_DMAARBITRATION_RX3_TX1   ETH_DMAMR_PR_3_1

+#define ETH_DMAARBITRATION_RX4_TX1   ETH_DMAMR_PR_4_1

+#define ETH_DMAARBITRATION_RX5_TX1   ETH_DMAMR_PR_5_1

+#define ETH_DMAARBITRATION_RX6_TX1   ETH_DMAMR_PR_6_1

+#define ETH_DMAARBITRATION_RX7_TX1   ETH_DMAMR_PR_7_1

+#define ETH_DMAARBITRATION_RX8_TX1   ETH_DMAMR_PR_8_1

+#define ETH_DMAARBITRATION_TX        (ETH_DMAMR_TXPR | ETH_DMAMR_DA)

+#define ETH_DMAARBITRATION_TX1_RX1   ((uint32_t)0x00000000U)

+#define ETH_DMAARBITRATION_TX2_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_2_1)

+#define ETH_DMAARBITRATION_TX3_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_3_1)

+#define ETH_DMAARBITRATION_TX4_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_4_1)

+#define ETH_DMAARBITRATION_TX5_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_5_1)

+#define ETH_DMAARBITRATION_TX6_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_6_1)

+#define ETH_DMAARBITRATION_TX7_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_7_1)

+#define ETH_DMAARBITRATION_TX8_RX1   (ETH_DMAMR_TXPR | ETH_DMAMR_PR_8_1)

+/**

+  * @}

+  */

+

+ /** @defgroup ETH_Burst_Mode ETH Burst Mode  

+  * @{

+  */ 

+#define ETH_BURSTLENGTH_FIXED           ETH_DMASBMR_FB

+#define ETH_BURSTLENGTH_MIXED           ETH_DMASBMR_MB

+#define ETH_BURSTLENGTH_UNSPECIFIED     ((uint32_t)0x00000000U)

+/**

+  * @}

+  */

+	

+/** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length

+  * @{

+  */ 

+#define ETH_TXDMABURSTLENGTH_1BEAT          ETH_DMACTCR_TPBL_1PBL   

+#define ETH_TXDMABURSTLENGTH_2BEAT          ETH_DMACTCR_TPBL_2PBL   

+#define ETH_TXDMABURSTLENGTH_4BEAT          ETH_DMACTCR_TPBL_4PBL   

+#define ETH_TXDMABURSTLENGTH_8BEAT          ETH_DMACTCR_TPBL_8PBL   

+#define ETH_TXDMABURSTLENGTH_16BEAT         ETH_DMACTCR_TPBL_16PBL  

+#define ETH_TXDMABURSTLENGTH_32BEAT         ETH_DMACTCR_TPBL_32PBL                  

+/**

+  * @}

+  */

+

+/** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length

+  * @{

+  */ 

+#define ETH_RXDMABURSTLENGTH_1BEAT          ETH_DMACRCR_RPBL_1PBL   

+#define ETH_RXDMABURSTLENGTH_2BEAT          ETH_DMACRCR_RPBL_2PBL   

+#define ETH_RXDMABURSTLENGTH_4BEAT          ETH_DMACRCR_RPBL_4PBL   

+#define ETH_RXDMABURSTLENGTH_8BEAT          ETH_DMACRCR_RPBL_8PBL   

+#define ETH_RXDMABURSTLENGTH_16BEAT         ETH_DMACRCR_RPBL_16PBL  

+#define ETH_RXDMABURSTLENGTH_32BEAT         ETH_DMACRCR_RPBL_32PBL                  

+/**

+  * @}

+  */	

+	

+/** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts

+  * @{

+  */	

+#define ETH_DMA_NORMAL_IT                 ETH_DMACIER_NIE 

+#define ETH_DMA_ABNORMAL_IT               ETH_DMACIER_AIE 

+#define ETH_DMA_CONTEXT_DESC_ERROR_IT     ETH_DMACIER_CDEE

+#define ETH_DMA_FATAL_BUS_ERROR_IT        ETH_DMACIER_FBEE

+#define ETH_DMA_EARLY_RX_IT               ETH_DMACIER_ERIE

+#define ETH_DMA_EARLY_TX_IT               ETH_DMACIER_ETIE

+#define ETH_DMA_RX_WATCHDOG_TIMEOUT_IT    ETH_DMACIER_RWTE

+#define ETH_DMA_RX_PROCESS_STOPPED_IT     ETH_DMACIER_RSE 

+#define ETH_DMA_RX_BUFFER_UNAVAILABLE_IT  ETH_DMACIER_RBUE

+#define ETH_DMA_RX_IT                     ETH_DMACIER_RIE 

+#define ETH_DMA_TX_BUFFER_UNAVAILABLE_IT  ETH_DMACIER_TBUE

+#define ETH_DMA_TX_PROCESS_STOPPED_IT     ETH_DMACIER_TXSE

+#define ETH_DMA_TX_IT                     ETH_DMACIER_TIE 

+/**

+  * @}

+  */

+

+/** @defgroup ETH_DMA_Status_Flags ETH DMA Status Flags

+  * @{

+  */	

+#define ETH_DMA_RX_NO_ERROR_FLAG                 ((uint32_t)0x00000000U)

+#define ETH_DMA_RX_DESC_READ_ERROR_FLAG          (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1 | ETH_DMACSR_REB_BIT_0)     

+#define ETH_DMA_RX_DESC_WRITE_ERROR_FLAG         (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1)       

+#define ETH_DMA_RX_BUFFER_READ_ERROR_FLAG        (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_0)      

+#define ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG        ETH_DMACSR_REB_BIT_2

+#define ETH_DMA_TX_NO_ERROR_FLAG                 ((uint32_t)0x00000000U)

+#define ETH_DMA_TX_DESC_READ_ERROR_FLAG          (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1 | ETH_DMACSR_TEB_BIT_0)     

+#define ETH_DMA_TX_DESC_WRITE_ERROR_FLAG         (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1)      

+#define ETH_DMA_TX_BUFFER_READ_ERROR_FLAG        (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_0)     

+#define ETH_DMA_TX_BUFFER_WRITE_ERROR_FLAG        ETH_DMACSR_TEB_BIT_2

+#define ETH_DMA_CONTEXT_DESC_ERROR_FLAG           ETH_DMACSR_CDE

+#define ETH_DMA_FATAL_BUS_ERROR_FLAG              ETH_DMACSR_FBE

+#define ETH_DMA_EARLY_TX_IT_FLAG                  ETH_DMACSR_ERI

+#define ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG          ETH_DMACSR_RWT

+#define ETH_DMA_RX_PROCESS_STOPPED_FLAG           ETH_DMACSR_RPS

+#define ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG        ETH_DMACSR_RBU

+#define ETH_DMA_TX_PROCESS_STOPPED_FLAG           ETH_DMACSR_TPS

+/**

+  * @}

+  */	

+	

+/** @defgroup ETH_Transmit_Mode ETH Transmit Mode 

+  * @{

+  */ 

+#define ETH_TRANSMITSTOREFORWARD       ETH_MTLTQOMR_TSF

+#define ETH_TRANSMITTHRESHOLD_32       ETH_MTLTQOMR_TTC_32BITS  

+#define ETH_TRANSMITTHRESHOLD_64       ETH_MTLTQOMR_TTC_64BITS  

+#define ETH_TRANSMITTHRESHOLD_96       ETH_MTLTQOMR_TTC_96BITS  

+#define ETH_TRANSMITTHRESHOLD_128      ETH_MTLTQOMR_TTC_128BITS 

+#define ETH_TRANSMITTHRESHOLD_192      ETH_MTLTQOMR_TTC_192BITS 

+#define ETH_TRANSMITTHRESHOLD_256      ETH_MTLTQOMR_TTC_256BITS 

+#define ETH_TRANSMITTHRESHOLD_384      ETH_MTLTQOMR_TTC_384BITS 

+#define ETH_TRANSMITTHRESHOLD_512      ETH_MTLTQOMR_TTC_512BITS 

+/**

+  * @}

+  */

+

+/** @defgroup ETH_Receive_Mode ETH Receive Mode 

+  * @{

+  */ 

+#define ETH_RECEIVESTOREFORWARD        ETH_MTLRQOMR_RSF

+#define ETH_RECEIVETHRESHOLD8_64       ETH_MTLRQOMR_RTC_64BITS  

+#define ETH_RECEIVETHRESHOLD8_32       ETH_MTLRQOMR_RTC_32BITS  

+#define ETH_RECEIVETHRESHOLD8_96       ETH_MTLRQOMR_RTC_96BITS  

+#define ETH_RECEIVETHRESHOLD8_128      ETH_MTLRQOMR_RTC_128BITS 

+/**

+  * @}

+  */

+	

+/** @defgroup ETH_Pause_Low_Threshold  ETH Pause Low Threshold

+  * @{

+  */ 

+#define ETH_PAUSELOWTHRESHOLD_MINUS_4        ETH_MACTFCR_PLT_MINUS4  

+#define ETH_PAUSELOWTHRESHOLD_MINUS_28       ETH_MACTFCR_PLT_MINUS28 

+#define ETH_PAUSELOWTHRESHOLD_MINUS_36       ETH_MACTFCR_PLT_MINUS36  

+#define ETH_PAUSELOWTHRESHOLD_MINUS_144      ETH_MACTFCR_PLT_MINUS144 

+#define ETH_PAUSELOWTHRESHOLD_MINUS_256      ETH_MACTFCR_PLT_MINUS256 

+#define ETH_PAUSELOWTHRESHOLD_MINUS_512      ETH_MACTFCR_PLT_MINUS512 

+/**

+  * @}

+  */

+	

+/** @defgroup ETH_Watchdog_Timeout ETH Watchdog Timeout

+  * @{

+  */ 

+#define ETH_WATCHDOGTIMEOUT_2KB      ETH_MACWTR_WTO_2KB

+#define ETH_WATCHDOGTIMEOUT_3KB      ETH_MACWTR_WTO_3KB

+#define ETH_WATCHDOGTIMEOUT_4KB      ETH_MACWTR_WTO_4KB

+#define ETH_WATCHDOGTIMEOUT_5KB      ETH_MACWTR_WTO_5KB

+#define ETH_WATCHDOGTIMEOUT_6KB      ETH_MACWTR_WTO_6KB

+#define ETH_WATCHDOGTIMEOUT_7KB      ETH_MACWTR_WTO_7KB

+#define ETH_WATCHDOGTIMEOUT_8KB      ETH_MACWTR_WTO_8KB

+#define ETH_WATCHDOGTIMEOUT_9KB      ETH_MACWTR_WTO_9KB

+#define ETH_WATCHDOGTIMEOUT_10KB     ETH_MACWTR_WTO_10KB

+#define ETH_WATCHDOGTIMEOUT_11KB     ETH_MACWTR_WTO_12KB

+#define ETH_WATCHDOGTIMEOUT_12KB     ETH_MACWTR_WTO_12KB

+#define ETH_WATCHDOGTIMEOUT_13KB     ETH_MACWTR_WTO_13KB

+#define ETH_WATCHDOGTIMEOUT_14KB     ETH_MACWTR_WTO_14KB

+#define ETH_WATCHDOGTIMEOUT_15KB     ETH_MACWTR_WTO_15KB

+#define ETH_WATCHDOGTIMEOUT_16KB     ETH_MACWTR_WTO_16KB

+/**

+  * @}

+  */  

+

+/** @defgroup ETH_Inter_Packet_Gap ETH Inter Packet Gap

+  * @{

+  */ 

+#define ETH_INTERPACKETGAP_96BIT   ETH_MACCR_IPG_96BIT 

+#define ETH_INTERPACKETGAP_88BIT   ETH_MACCR_IPG_88BIT 

+#define ETH_INTERPACKETGAP_80BIT   ETH_MACCR_IPG_80BIT  

+#define ETH_INTERPACKETGAP_72BIT   ETH_MACCR_IPG_72BIT 

+#define ETH_INTERPACKETGAP_64BIT   ETH_MACCR_IPG_64BIT  

+#define ETH_INTERPACKETGAP_56BIT   ETH_MACCR_IPG_56BIT  

+#define ETH_INTERPACKETGAP_48BIT   ETH_MACCR_IPG_48BIT 

+#define ETH_INTERPACKETGAP_40BIT   ETH_MACCR_IPG_40BIT 

+/**

+  * @}

+  */

+

+/** @defgroup ETH_Speed  ETH Speed

+  * @{

+  */ 

+#define ETH_SPEED_10M        ((uint32_t)0x00000000U)

+#define ETH_SPEED_100M       ETH_MACCR_FES

+/**

+  * @}

+  */

+

+/** @defgroup ETH_Duplex_Mode ETH Duplex Mode 

+  * @{

+  */ 

+#define ETH_FULLDUPLEX_MODE       ETH_MACCR_DM

+#define ETH_HALFDUPLEX_MODE       ((uint32_t)0x00000000U)

+/**

+  * @}

+  */

+	

+/** @defgroup ETH_Back_Off_Limit ETH Back Off Limit

+  * @{

+  */ 

+#define ETH_BACKOFFLIMIT_10  ETH_MACCR_BL_10

+#define ETH_BACKOFFLIMIT_8   ETH_MACCR_BL_8 

+#define ETH_BACKOFFLIMIT_4   ETH_MACCR_BL_4 

+#define ETH_BACKOFFLIMIT_1   ETH_MACCR_BL_1 

+/**

+  * @}

+  */

+

+/** @defgroup ETH_Preamble_Length ETH Preamble Length

+  * @{

+  */ 

+#define ETH_PREAMBLELENGTH_7      ETH_MACCR_PRELEN_7

+#define ETH_PREAMBLELENGTH_5      ETH_MACCR_PRELEN_5

+#define ETH_PREAMBLELENGTH_3      ETH_MACCR_PRELEN_3

+/**

+  * @}

+  */

+

+/** @defgroup ETH_Source_Addr_Control ETH Source Addr Control

+  * @{

+  */ 

+#define ETH_SOURCEADDRESS_DISABLE           ((uint32_t)0x00000000U)

+#define ETH_SOURCEADDRESS_INSERT_ADDR0      ETH_MACCR_SARC_INSADDR0

+#define ETH_SOURCEADDRESS_INSERT_ADDR1      ETH_MACCR_SARC_INSADDR1

+#define ETH_SOURCEADDRESS_REPLACE_ADDR0     ETH_MACCR_SARC_REPADDR0

+#define ETH_SOURCEADDRESS_REPLACE_ADDR1     ETH_MACCR_SARC_REPADDR1

+/**

+  * @}

+  */

+  

+/** @defgroup ETH_Control_Packets_Filter ETH Control Packets Filter

+  * @{

+  */ 

+#define ETH_CTRLPACKETS_BLOCK_ALL                      ETH_MACPFR_PCF_BLOCKALL

+#define ETH_CTRLPACKETS_FORWARD_ALL_EXCEPT_PA          ETH_MACPFR_PCF_FORWARDALLEXCEPTPA

+#define ETH_CTRLPACKETS_FORWARD_ALL                    ETH_MACPFR_PCF_FORWARDALL

+#define ETH_CTRLPACKETS_FORWARD_PASSED_ADDR_FILTER     ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER

+/**

+  * @}

+  */

+	

+/** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison

+  * @{

+  */ 

+#define ETH_VLANTAGCOMPARISON_16BIT          ((uint32_t)0x00000000U)

+#define ETH_VLANTAGCOMPARISON_12BIT          ETH_MACVTR_ETV

+/**

+  * @}

+  */

+

+/** @defgroup ETH_MAC_addresses ETH MAC addresses

+  * @{

+  */ 

+#define ETH_MAC_ADDRESS0     ((uint32_t)0x00000000U)

+#define ETH_MAC_ADDRESS1     ((uint32_t)0x00000008U)

+#define ETH_MAC_ADDRESS2     ((uint32_t)0x00000010U)

+#define ETH_MAC_ADDRESS3     ((uint32_t)0x00000018U)

+/**

+  * @}

+  */    

+ 

+/** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts

+  * @{

+  */	

+#define ETH_MAC_RX_STATUS_IT     ETH_MACIER_RXSTSIE 

+#define ETH_MAC_TX_STATUS_IT     ETH_MACIER_TXSTSIE 

+#define ETH_MAC_TIMESTAMP_IT     ETH_MACIER_TSIE

+#define ETH_MAC_LPI_IT           ETH_MACIER_LPIIE

+#define ETH_MAC_PMT_IT           ETH_MACIER_PMTIE

+#define ETH_MAC_PHY_IT           ETH_MACIER_PHYIE

+/**

+  * @}

+  */

+

+/** @defgroup ETH_MAC_Wake_Up_Event ETH MAC Wake Up Event

+  * @{

+  */	

+#define ETH_WAKEUP_PACKET_RECIEVED    ETH_MACPCSR_RWKPRCVD 

+#define ETH_MAGIC_PACKET_RECIEVED     ETH_MACPCSR_MGKPRCVD 

+/**

+  * @}

+  */

+

+/** @defgroup ETH_MAC_Rx_Tx_Status ETH MAC Rx Tx Status

+  * @{

+  */

+#define ETH_RECEIVE_WATCHDOG_TIMEOUT        ETH_MACRXTXSR_RWT

+#define ETH_EXECESSIVE_COLLISIONS           ETH_MACRXTXSR_EXCOL

+#define ETH_LATE_COLLISIONS                 ETH_MACRXTXSR_LCOL 

+#define ETH_EXECESSIVE_DEFERRAL             ETH_MACRXTXSR_EXDEF

+#define ETH_LOSS_OF_CARRIER                 ETH_MACRXTXSR_LCARR

+#define ETH_NO_CARRIER                      ETH_MACRXTXSR_NCARR

+#define ETH_TRANSMIT_JABBR_TIMEOUT          ETH_MACRXTXSR_TJT  	

+/**

+  * @}

+  */

+

+/** @defgroup HAL_ETH_StateTypeDef ETH States

+  * @{

+  */

+#define HAL_ETH_STATE_RESET       ((uint32_t)0x00000000U)    /*!< Peripheral not yet Initialized or disabled */

+#define HAL_ETH_STATE_READY       ((uint32_t)0x00000010U)    /*!< Peripheral Communication started           */

+#define HAL_ETH_STATE_BUSY        ((uint32_t)0x00000023U)    /*!< an internal process is ongoing             */

+#define HAL_ETH_STATE_BUSY_TX     ((uint32_t)0x00000021U)    /*!< Transmission process is ongoing            */

+#define HAL_ETH_STATE_BUSY_RX     ((uint32_t)0x00000022U)    /*!< Reception process is ongoing               */

+#define HAL_ETH_STATE_ERROR       ((uint32_t)0x000000E0U)    /*!< Error State                                */

+/**

+  * @}

+  */

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup ETH_Exported_Macros ETH Exported Macros

+  * @{

+  */

+

+/** @brief Reset ETH handle state

+  * @param  __HANDLE__: specifies the ETH handle.

+  * @retval None

+  */

+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)

+#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \

+                                                       (__HANDLE__)->gState = HAL_ETH_STATE_RESET;      \

+                                                       (__HANDLE__)->RxState = HAL_ETH_STATE_RESET;     \

+                                                       (__HANDLE__)->MspInitCallback = NULL;             \

+                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \

+                                                     } while(0)

+#else

+#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \

+                                                       (__HANDLE__)->gState = HAL_ETH_STATE_RESET;      \

+                                                       (__HANDLE__)->RxState = HAL_ETH_STATE_RESET;     \

+                                                     } while(0)

+#endif /*USE_HAL_ETH_REGISTER_CALLBACKS */

+

+/** 

+  * @brief  Enables the specified ETHERNET DMA interrupts.

+  * @param  __HANDLE__   : ETH Handle

+  * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be

+  *   enabled @ref ETH_DMA_Interrupts

+  * @retval None

+  */

+#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->DMACIER |= (__INTERRUPT__))

+

+/**

+  * @brief  Disables the specified ETHERNET DMA interrupts.

+  * @param  __HANDLE__   : ETH Handle

+  * @param  __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be

+  *   disabled. @ref ETH_DMA_Interrupts

+  * @retval None

+  */

+#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)                ((__HANDLE__)->Instance->DMACIER &= ~(__INTERRUPT__))

+

+/**

+  * @brief  Gets the ETHERNET DMA IT source enabled or disabled.

+  * @param  __HANDLE__   : ETH Handle

+  * @param  __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts

+  * @retval The ETH DMA IT Source enabled or disabled

+  */

+#define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      (((__HANDLE__)->Instance->DMACIER &  (__INTERRUPT__)) == (__INTERRUPT__))

+

+/**

+  * @brief  Gets the ETHERNET DMA IT pending bit.

+  * @param  __HANDLE__   : ETH Handle

+  * @param  __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts

+  * @retval The state of ETH DMA IT (SET or RESET)

+  */

+#define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__)      (((__HANDLE__)->Instance->DMACSR &  (__INTERRUPT__)) == (__INTERRUPT__))

+    

+/**

+  * @brief  Clears the ETHERNET DMA IT pending bit.

+  * @param  __HANDLE__   : ETH Handle

+  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts

+  * @retval None

+  */

+#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->DMACSR = (__INTERRUPT__))

+

+/**

+  * @brief  Checks whether the specified ETHERNET DMA flag is set or not.

+* @param  __HANDLE__: ETH Handle

+  * @param  __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags

+  * @retval The state of ETH DMA FLAG (SET or RESET).

+  */

+#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__)                   (((__HANDLE__)->Instance->DMACSR &( __FLAG__)) == ( __FLAG__))  

+

+/**

+  * @brief  Clears the specified ETHERNET DMA flag.

+* @param  __HANDLE__: ETH Handle

+  * @param  __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags

+  * @retval The state of ETH DMA FLAG (SET or RESET).

+  */

+#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__)                   ((__HANDLE__)->Instance->DMACSR = ( __FLAG__))

+    

+/** 

+  * @brief  Enables the specified ETHERNET MAC interrupts.

+  * @param  __HANDLE__   : ETH Handle

+  * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be

+  *   enabled @ref ETH_MAC_Interrupts

+  * @retval None

+  */

+#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__))

+    

+/** 

+  * @brief  Disables the specified ETHERNET MAC interrupts.

+  * @param  __HANDLE__   : ETH Handle

+  * @param  __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be

+  *   enabled @ref ETH_MAC_Interrupts

+  * @retval None

+  */

+#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                 ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__))

+  

+/**

+  * @brief  Checks whether the specified ETHERNET MAC flag is set or not.

+  * @param  __HANDLE__: ETH Handle

+  * @param  __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts

+  * @retval The state of ETH MAC IT (SET or RESET).

+  */

+#define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__)                   (((__HANDLE__)->Instance->MACISR &( __INTERRUPT__)) == ( __INTERRUPT__)) 

+

+/*!< External interrupt line 86 Connected to the ETH wakeup EXTI Line */

+#define ETH_WAKEUP_EXTI_LINE  ((uint32_t)0x00400000U)  /* !<  86 - 64 = 22 */

+

+/**

+  * @brief Enable the ETH WAKEUP Exti Line.

+  * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled.

+  *   @arg ETH_WAKEUP_EXTI_LINE     

+  * @retval None.

+  */

+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__)   (EXTI_D1->IMR3 |= (__EXTI_LINE__))

+

+/**

+  * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not.

+  * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.

+  *   @arg ETH_WAKEUP_EXTI_LINE  

+  * @retval EXTI ETH WAKEUP Line Status.

+  */

+#define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__)  (EXTI_D1->PR3 & (__EXTI_LINE__))

+

+/**

+  * @brief Clear the ETH WAKEUP Exti flag.

+  * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.

+  *   @arg ETH_WAKEUP_EXTI_LINE  

+  * @retval None.

+  */

+#define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 = (__EXTI_LINE__))

+

+#if defined(DUAL_CORE)

+/**

+  * @brief Enable the ETH WAKEUP Exti Line by Core2.

+  * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled.

+  *   @arg ETH_WAKEUP_EXTI_LINE     

+  * @retval None.

+  */

+#define __HAL_ETH_WAKEUP_EXTID2_ENABLE_IT(__EXTI_LINE__)   (EXTI_D2->IMR3 |= (__EXTI_LINE__)) 

+

+/**

+  * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not.

+  * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.

+  *   @arg ETH_WAKEUP_EXTI_LINE  

+  * @retval EXTI ETH WAKEUP Line Status.

+  */

+#define __HAL_ETH_WAKEUP_EXTID2_GET_FLAG(__EXTI_LINE__)  (EXTI_D2->PR3 & (__EXTI_LINE__))

+

+/**

+  * @brief Clear the ETH WAKEUP Exti flag.

+  * @param  __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.

+  *   @arg ETH_WAKEUP_EXTI_LINE  

+  * @retval None.

+  */

+#define __HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D2->PR3 = (__EXTI_LINE__))

+#endif

+

+/**

+  * @brief  enable rising edge interrupt on selected EXTI line.

+  * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.

+  *  @arg ETH_WAKEUP_EXTI_LINE

+  * @retval None

+  */

+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR3 &= ~(__EXTI_LINE__)); \

+                                                                (EXTI->RTSR3 |= (__EXTI_LINE__)) 

+

+/**

+  * @brief  enable falling edge interrupt on selected EXTI line.

+  * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.

+  *  @arg ETH_WAKEUP_EXTI_LINE

+  * @retval None

+  */

+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 &= ~(__EXTI_LINE__));\

+                                                                 (EXTI->FTSR3 |= (__EXTI_LINE__))

+

+/**

+  * @brief  enable falling edge interrupt on selected EXTI line.

+  * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.

+  *  @arg ETH_WAKEUP_EXTI_LINE

+  * @retval None

+  */

+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 |= (__EXTI_LINE__));\

+                                                                        (EXTI->FTSR3 |= (__EXTI_LINE__))

+

+/**

+  * @brief  Generates a Software interrupt on selected EXTI line.

+  * @param  __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.

+  *  @arg ETH_WAKEUP_EXTI_LINE

+  * @retval None

+  */

+#define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER3 |= (__EXTI_LINE__))

+

+/**

+  * @}

+  */

+

+/* Include ETH HAL Extension module */

+#include "stm32h7xx_hal_eth_ex.h"

+

+/* Exported functions --------------------------------------------------------*/

+

+/** @addtogroup ETH_Exported_Functions

+  * @{

+  */

+  

+/** @addtogroup ETH_Exported_Functions_Group1

+  * @{

+  */    

+/* Initialization and de initialization functions  **********************************/

+HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);                        

+HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);                      

+void              HAL_ETH_MspInit(ETH_HandleTypeDef *heth);                    

+void              HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);  

+HAL_StatusTypeDef HAL_ETH_DescAssignMemory(ETH_HandleTypeDef *heth, uint32_t Index, uint8_t *pBuffer1,uint8_t *pBuffer2);

+

+/* Callbacks Register/UnRegister functions  ***********************************/

+#if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)

+HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID);

+#endif /* USE_HAL_ETH_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+/** @addtogroup ETH_Exported_Functions_Group2

+  * @{

+  */

+/* IO operation functions *******************************************************/

+HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);

+HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth);

+HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);

+HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth);

+

+uint8_t           HAL_ETH_IsRxDataAvailable(ETH_HandleTypeDef *heth);

+HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer(ETH_HandleTypeDef *heth, ETH_BufferTypeDef *RxBuffer);

+HAL_StatusTypeDef HAL_ETH_GetRxDataLength(ETH_HandleTypeDef *heth, uint32_t *Length);

+HAL_StatusTypeDef HAL_ETH_GetRxDataInfo(ETH_HandleTypeDef *heth, ETH_RxPacketInfo *RxPacketInfo);

+HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth);

+

+HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout);

+HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig);

+

+HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue);  

+HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue); 

+

+void              HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);

+void              HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);

+void              HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);

+void              HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth);

+void              HAL_ETH_MACErrorCallback(ETH_HandleTypeDef *heth);

+void              HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth);

+void              HAL_ETH_EEECallback(ETH_HandleTypeDef *heth);

+void              HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth);

+/**

+  * @}

+  */

+

+/** @addtogroup ETH_Exported_Functions_Group3

+  * @{

+  */

+/* Peripheral Control functions  **********************************************/

+/* MAC & DMA Configuration APIs  **********************************************/

+HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);

+HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);

+HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);

+HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);

+void              HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth);

+

+/* MAC VLAN Processing APIs    ************************************************/

+void              HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier);

+

+/* MAC L2 Packet Filtering APIs  **********************************************/

+HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);

+HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);

+HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable);

+HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr);

+

+/* MAC Power Down APIs    *****************************************************/

+void              HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig);

+void              HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth);

+HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count);

+

+/**

+  * @}

+  */

+

+/** @addtogroup ETH_Exported_Functions_Group4

+  * @{

+  */

+/* Peripheral State functions  **************************************************/

+HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);

+uint32_t             HAL_ETH_GetError(ETH_HandleTypeDef *heth);

+uint32_t             HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth);

+uint32_t             HAL_ETH_GetMACError(ETH_HandleTypeDef *heth);

+uint32_t             HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth);

+/**

+  * @}

+  */ 

+

+/**

+  * @}

+  */ 

+

+/**

+  * @}

+  */ 

+

+/**

+  * @}

+  */ 

+

+#endif /* ETH */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_ETH_H */

+

+

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_eth_ex.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_eth_ex.h
new file mode 100644
index 0000000000..bb7e0cf3fd
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_eth_ex.h
@@ -0,0 +1,357 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_eth_ex.h

+  * @author  MCD Application Team

+  * @brief   Header file of ETH HAL Extended module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */ 

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_ETH_EX_H

+#define STM32H7xx_HAL_ETH_EX_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+#if defined(ETH)

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup ETHEx

+  * @{

+  */ 

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup ETHEx_Exported_Types ETHEx Exported Types

+  * @{

+  */

+  

+/** 

+  * @brief  ETH RX VLAN structure definition

+  */

+typedef struct{

+  FunctionalState InnerVLANTagInStatus;      /*!< Enables or disables Inner VLAN Tag in Rx Status  */

+	

+  uint32_t StripInnerVLANTag;                /*!< Sets the Inner VLAN Tag Stripping on Receive 

+                                                  This parameter can be a value of @ref ETHEx_Rx_Inner_VLAN_Tag_Stripping */

+	

+  FunctionalState InnerVLANTag;              /*!< Enables or disables Inner VLAN Tag */

+

+  FunctionalState DoubleVLANProcessing;      /*!< Enable or Disable double VLAN processing */

+	

+  FunctionalState VLANTagHashTableMatch;     /*!< Enable or Disable VLAN Tag Hash Table Match */

+	

+  FunctionalState VLANTagInStatus;           /*!< Enable or Disable VLAN Tag in Rx status */

+	

+  uint32_t StripVLANTag;                     /*!< Set the VLAN Tag Stripping on Receive 

+                                                  This parameter can be a value of @ref ETHEx_Rx_VLAN_Tag_Stripping */

+	

+  uint32_t VLANTypeCheck;                    /*!< Enable or Disable VLAN Type Check

+                                                  This parameter can be a value of @ref ETHEx_VLAN_Type_Check */

+																				 

+  FunctionalState VLANTagInverceMatch;       /*!< Enable or disable VLAN Tag Inverse Match */																			 

+}ETH_RxVLANConfigTypeDef;

+/** 

+  * 

+  */

+  

+/** 

+  * @brief  ETH TX VLAN structure definition

+  */

+typedef struct{

+  FunctionalState SourceTxDesc;   /*!< Enable or Disable VLAN tag source from DMA tx descriptors */

+  

+  FunctionalState SVLANType;      /*!< Enable or Disable insertion of SVLAN type */

+	

+  uint32_t VLANTagControl;        /*!< Sets the VLAN tag control in tx packets

+                                      This parameter can be a value of @ref ETHEx_VLAN_Tag_Control */

+}ETH_TxVLANConfigTypeDef;

+/** 

+  * 

+  */

+

+/** 

+  * @brief  ETH L3 filter structure definition

+  */

+typedef struct{

+  uint32_t Protocol;                /*!< Sets the L3 filter protocol to IPv4 or IPv6

+                                         This parameter can be a value of @ref ETHEx_L3_Protocol */

+  

+  uint32_t SrcAddrFilterMatch;      /*!< Sets the L3 filter source address match

+                                         This parameter can be a value of @ref ETHEx_L3_Source_Match */

+  

+  uint32_t DestAddrFilterMatch;     /*!< Sets the L3 filter destination address match

+                                         This parameter can be a value of @ref ETHEx_L3_Destination_Match */

+  

+  uint32_t SrcAddrHigherBitsMatch;  /*!< Sets the L3 filter source address higher bits match

+                                         This parameter can be a value from 0 to 31 */

+  

+  uint32_t DestAddrHigherBitsMatch; /*!< Sets the L3 filter destination address higher bits match

+                                         This parameter can be a value from 0 to 31 */

+  

+  uint32_t Ip4SrcAddr;              /*!< Sets the L3 filter IPv4 source address if IPv4 protocol is used

+                                         This parameter can be a value from 0x0 to 0xFFFFFFFF */

+  

+  uint32_t Ip4DestAddr;             /*!< Sets the L3 filter IPv4 destination  address if IPv4 protocol is used

+                                         This parameter can be a value from 0 to 0xFFFFFFFF  */

+  

+  uint32_t Ip6Addr[4];                 /*!< Sets the L3 filter IPv6 address if IPv6 protocol is used

+                                          This parameter must be a table of 4 words (4* 32 bits) */

+}ETH_L3FilterConfigTypeDef;

+/** 

+  * 

+  */

+

+/** 

+  * @brief  ETH L4 filter structure definition

+  */

+typedef struct{

+  uint32_t Protocol;               /*!< Sets the L4 filter protocol to TCP or UDP

+                                        This parameter can be a value of @ref ETHEx_L4_Protocol */

+  

+  uint32_t SrcPortFilterMatch;     /*!< Sets the L4 filter source port match

+                                        This parameter can be a value of @ref ETHEx_L4_Source_Match */

+  

+  uint32_t DestPortFilterMatch;    /*!< Sets the L4 filter destination port match

+                                        This parameter can be a value of @ref ETHEx_L4_Destination_Match */

+  

+  uint32_t SourcePort;             /*!< Sets the L4 filter source port 

+                                        This parameter must be a value from 0x0 to 0xFFFF */

+  

+  uint32_t DestinationPort;        /*!< Sets the L4 filter destination port 

+                                        This parameter must be a value from 0x0 to 0xFFFF */	

+}ETH_L4FilterConfigTypeDef;

+/** 

+  * 

+  */

+  

+/**

+  * @}

+  */

+  

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup ETHEx_Exported_Constants ETHEx Exported Constants

+  * @{

+  */

+    

+/** @defgroup ETHEx_LPI_Event ETHEx LPI Event

+  * @{

+  */	

+#define ETH_TX_LPI_ENTRY    ETH_MACLCSR_TLPIEN 

+#define ETH_TX_LPI_EXIT     ETH_MACLCSR_TLPIEX 

+#define ETH_RX_LPI_ENTRY    ETH_MACLCSR_RLPIEN

+#define ETH_RX_LPI_EXIT     ETH_MACLCSR_RLPIEX

+/**

+  * @}

+  */

+  

+/** @defgroup ETHEx_L3_Filter ETHEx L3 Filter

+  * @{

+  */

+#define ETH_L3_FILTER_0                 ((uint32_t)0x00000000)

+#define ETH_L3_FILTER_1                 ((uint32_t)0x0000000C)

+/**

+  * @}

+  */

+

+/** @defgroup ETHEx_L4_Filter ETHEx L4 Filter

+  * @{

+  */

+#define ETH_L4_FILTER_0                 ((uint32_t)0x00000000)

+#define ETH_L4_FILTER_1                 ((uint32_t)0x0000000C)

+/**

+  * @}

+  */

+

+/** @defgroup ETHEx_L3_Protocol ETHEx L3 Protocol

+  * @{

+  */

+#define ETH_L3_IPV6_MATCH                       ETH_MACL3L4CR_L3PEN

+#define ETH_L3_IPV4_MATCH                       ((uint32_t)0x00000000)

+/**

+  * @}

+  */

+

+/** @defgroup ETHEx_L3_Source_Match ETHEx L3 Source Match

+  * @{

+  */

+#define ETH_L3_SRC_ADDR_PERFECT_MATCH_ENABLE    ETH_MACL3L4CR_L3SAM

+#define ETH_L3_SRC_ADDR_INVERSE_MATCH_ENABLE    (ETH_MACL3L4CR_L3SAM | ETH_MACL3L4CR_L3SAIM)

+#define ETH_L3_SRC_ADDR_MATCH_DISABLE           ((uint32_t)0x00000000)

+/**

+  * @}

+  */

+	

+/** @defgroup ETHEx_L3_Destination_Match ETHEx L3 Destination Match

+  * @{

+  */

+#define ETH_L3_DEST_ADDR_PERFECT_MATCH_ENABLE   ETH_MACL3L4CR_L3DAM

+#define ETH_L3_DEST_ADDR_INVERSE_MATCH_ENABLE   (ETH_MACL3L4CR_L3DAM | ETH_MACL3L4CR_L3DAIM)

+#define ETH_L3_DEST_ADDR_MATCH_DISABLE          ((uint32_t)0x00000000)

+/**

+  * @}

+  */

+	

+/** @defgroup ETHEx_L4_Protocol ETHEx L4 Protocol

+  * @{

+  */

+#define ETH_L4_UDP_MATCH                        ETH_MACL3L4CR_L4PEN

+#define ETH_L4_TCP_MATCH                        ((uint32_t)0x00000000)

+/**

+  * @}

+  */

+	

+/** @defgroup ETHEx_L4_Source_Match ETHEx L4 Source Match

+  * @{

+  */

+#define ETH_L4_SRC_PORT_PERFECT_MATCH_ENABLE    ETH_MACL3L4CR_L4SPM

+#define ETH_L4_SRC_PORT_INVERSE_MATCH_ENABLE    (ETH_MACL3L4CR_L4SPM |ETH_MACL3L4CR_L4SPIM) 

+#define ETH_L4_SRC_PORT_MATCH_DISABLE           ((uint32_t)0x00000000)

+/**

+  * @}

+  */

+	

+/** @defgroup ETHEx_L4_Destination_Match ETHEx L4 Destination Match

+  * @{

+  */

+#define ETH_L4_DEST_PORT_PERFECT_MATCH_ENABLE   ETH_MACL3L4CR_L4DPM

+#define ETH_L4_DEST_PORT_INVERSE_MATCH_ENABLE   (ETH_MACL3L4CR_L4DPM | ETH_MACL3L4CR_L4DPIM)

+#define ETH_L4_DEST_PORT_MATCH_DISABLE          ((uint32_t)0x00000000)

+/**

+  * @}

+  */

+  

+/** @defgroup ETHEx_Rx_Inner_VLAN_Tag_Stripping ETHEx Rx Inner VLAN Tag Stripping

+  * @{

+  */ 

+#define ETH_INNERVLANTAGRXSTRIPPING_NONE      ETH_MACVTR_EIVLS_DONOTSTRIP

+#define ETH_INNERVLANTAGRXSTRIPPING_IFPASS    ETH_MACVTR_EIVLS_STRIPIFPASS

+#define ETH_INNERVLANTAGRXSTRIPPING_IFFAILS   ETH_MACVTR_EIVLS_STRIPIFFAILS

+#define ETH_INNERVLANTAGRXSTRIPPING_ALWAYS    ETH_MACVTR_EIVLS_ALWAYSSTRIP

+/**

+  * @}

+  */

+

+/** @defgroup ETHEx_Rx_VLAN_Tag_Stripping ETHEx Rx VLAN Tag Stripping

+  * @{

+  */ 

+#define ETH_VLANTAGRXSTRIPPING_NONE      ETH_MACVTR_EVLS_DONOTSTRIP

+#define ETH_VLANTAGRXSTRIPPING_IFPASS    ETH_MACVTR_EVLS_STRIPIFPASS

+#define ETH_VLANTAGRXSTRIPPING_IFFAILS   ETH_MACVTR_EVLS_STRIPIFFAILS

+#define ETH_VLANTAGRXSTRIPPING_ALWAYS    ETH_MACVTR_EVLS_ALWAYSSTRIP

+/**

+  * @}

+  */

+  

+/** @defgroup ETHEx_VLAN_Type_Check ETHEx VLAN Type Check

+  * @{

+  */ 

+#define ETH_VLANTYPECHECK_DISABLE    ETH_MACVTR_DOVLTC

+#define ETH_VLANTYPECHECK_SVLAN      (ETH_MACVTR_ERSVLM | ETH_MACVTR_ESVL)

+#define ETH_VLANTYPECHECK_CVLAN      ((uint32_t)0x00000000)

+/**

+  * @}

+  */

+  

+/** @defgroup ETHEx_VLAN_Tag_Control ETHEx_VLAN_Tag_Control

+  * @{

+  */

+#define ETH_VLANTAGCONTROL_NONE       (ETH_MACVIR_VLP | ETH_MACVIR_VLC_NOVLANTAG)

+#define ETH_VLANTAGCONTROL_DELETE     (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGDELETE)

+#define ETH_VLANTAGCONTROL_INSERT     (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGINSERT)

+#define ETH_VLANTAGCONTROL_REPLACE    (ETH_MACVIR_VLP | ETH_MACVIR_VLC_VLANTAGREPLACE)

+/**

+  * @}

+  */	

+ 

+/** @defgroup ETHEx_Tx_VLAN_Tag ETHEx Tx VLAN Tag

+  * @{

+  */ 

+#define ETH_INNER_TX_VLANTAG    ((uint32_t)0x00000001U)

+#define ETH_OUTER_TX_VLANTAG    ((uint32_t)0x00000000U)

+/**

+  * @}

+  */ 

+  

+/**

+  * @}

+  */

+  

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup ETHEx_Exported_Functions

+  * @{

+  */

+

+/** @addtogroup ETHEx_Exported_Functions_Group1

+  * @{

+  */

+/* MAC ARP Offloading APIs  ***************************************************/

+void              HAL_ETHEx_EnableARPOffload(ETH_HandleTypeDef *heth);

+void              HAL_ETHEx_DisableARPOffload(ETH_HandleTypeDef *heth);

+void              HAL_ETHEx_SetARPAddressMatch(ETH_HandleTypeDef *heth, uint32_t IpAddress); 

+

+/* MAC L3 L4 Filtering APIs ***************************************************/

+void              HAL_ETHEx_EnableL3L4Filtering(ETH_HandleTypeDef *heth);

+void              HAL_ETHEx_DisableL3L4Filtering(ETH_HandleTypeDef *heth);

+HAL_StatusTypeDef HAL_ETHEx_GetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig);

+HAL_StatusTypeDef HAL_ETHEx_GetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig);

+HAL_StatusTypeDef HAL_ETHEx_SetL3FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L3FilterConfigTypeDef *pL3FilterConfig);

+HAL_StatusTypeDef HAL_ETHEx_SetL4FilterConfig(ETH_HandleTypeDef *heth, uint32_t Filter, ETH_L4FilterConfigTypeDef *pL4FilterConfig);

+

+/* MAC VLAN Processing APIs    ************************************************/

+void              HAL_ETHEx_EnableVLANProcessing(ETH_HandleTypeDef *heth);

+void              HAL_ETHEx_DisableVLANProcessing(ETH_HandleTypeDef *heth);

+HAL_StatusTypeDef HAL_ETHEx_GetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);

+HAL_StatusTypeDef HAL_ETHEx_SetRxVLANConfig(ETH_HandleTypeDef *heth, ETH_RxVLANConfigTypeDef *pVlanConfig);

+void              HAL_ETHEx_SetVLANHashTable(ETH_HandleTypeDef *heth, uint32_t VLANHashTable);

+HAL_StatusTypeDef HAL_ETHEx_GetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig);

+HAL_StatusTypeDef HAL_ETHEx_SetTxVLANConfig(ETH_HandleTypeDef *heth, uint32_t VLANTag ,ETH_TxVLANConfigTypeDef *pVlanConfig);

+void              HAL_ETHEx_SetTxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t VLANTag ,uint32_t VLANIdentifier);

+

+/* Energy Efficient Ethernet APIs *********************************************/

+void              HAL_ETHEx_EnterLPIMode(ETH_HandleTypeDef *heth, FunctionalState TxAutomate, FunctionalState TxClockStop);

+void              HAL_ETHEx_ExitLPIMode(ETH_HandleTypeDef *heth);

+uint32_t          HAL_ETHEx_GetMACLPIEvent(ETH_HandleTypeDef *heth);

+ 

+/**

+  * @}

+  */ 

+

+/**

+  * @}

+  */

+    

+/**

+  * @}

+  */ 

+

+/**

+  * @}

+  */

+

+#endif /* ETH */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_ETH_EX_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_exti.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_exti.h
new file mode 100644
index 0000000000..6273f3c347
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_exti.h
@@ -0,0 +1,507 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_exti.h

+  * @author  MCD Application Team

+  * @brief   Header file of EXTI HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_EXTI_H

+#define STM32H7xx_HAL_EXTI_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @defgroup EXTI EXTI

+  * @brief EXTI HAL module driver

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+

+/** @defgroup EXTI_Exported_Types EXTI Exported Types

+  * @{

+  */

+typedef enum

+{

+  HAL_EXTI_COMMON_CB_ID          = 0x00U,

+} EXTI_CallbackIDTypeDef;

+

+

+/**

+  * @brief  EXTI Handle structure definition

+  */

+typedef struct

+{

+  uint32_t Line;                    /*!<  Exti line number */

+  void (* PendingCallback)(void);   /*!<  Exti pending callback */

+} EXTI_HandleTypeDef;

+

+/**

+  * @brief  EXTI Configuration structure definition

+  */

+typedef struct

+{

+  uint32_t Line;           /*!< The Exti line to be configured. This parameter

+                                can be a value of @ref EXTI_Line */

+  uint32_t Mode;           /*!< The Exit Mode to be configured for a core.

+                                This parameter can be a combination of @ref EXTI_Mode */

+  uint32_t Trigger;        /*!< The Exti Trigger to be configured. This parameter

+                                can be a value of @ref EXTI_Trigger */

+  uint32_t GPIOSel;        /*!< The Exti GPIO multiplexer selection to be configured.

+                                This parameter is only possible for line 0 to 15. It

+                                can be a value of @ref EXTI_GPIOSel */

+

+  uint32_t PendClearSource; /*!< Specifies the event pending clear source for D3/SRD

+                                 domain. This parameter can be a value of @ref

+                                 EXTI_PendClear_Source */

+

+} EXTI_ConfigTypeDef;

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup EXTI_Exported_Constants EXTI Exported Constants

+  * @{

+  */

+

+/** @defgroup EXTI_Line  EXTI Line

+  * @{

+  */

+#define EXTI_LINE_0                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x00U)

+#define EXTI_LINE_1                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x01U)

+#define EXTI_LINE_2                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x02U)

+#define EXTI_LINE_3                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x03U)

+#define EXTI_LINE_4                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x04U)

+#define EXTI_LINE_5                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x05U)

+#define EXTI_LINE_6                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x06U)

+#define EXTI_LINE_7                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x07U)

+#define EXTI_LINE_8                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x08U)

+#define EXTI_LINE_9                         (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x09U)

+#define EXTI_LINE_10                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0AU)

+#define EXTI_LINE_11                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0BU)

+#define EXTI_LINE_12                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0CU)

+#define EXTI_LINE_13                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0DU)

+#define EXTI_LINE_14                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0EU)

+#define EXTI_LINE_15                        (EXTI_GPIO     | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x0FU)

+#define EXTI_LINE_16                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x10U)

+#define EXTI_LINE_17                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x11U)

+#define EXTI_LINE_18                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x12U)

+#define EXTI_LINE_19                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x13U)

+#define EXTI_LINE_20                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x14U)

+#define EXTI_LINE_21                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x15U)

+#define EXTI_LINE_22                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x16U)

+#define EXTI_LINE_23                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)

+#define EXTI_LINE_24                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x18U)

+#define EXTI_LINE_25                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL     | 0x19U)

+#define EXTI_LINE_26                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU)

+#define EXTI_LINE_27                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU)

+#define EXTI_LINE_28                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1CU)

+#define EXTI_LINE_29                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1DU)

+#define EXTI_LINE_30                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1EU)

+#define EXTI_LINE_31                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG1 | EXTI_TARGET_MSK_ALL_CPU | 0x1FU)

+#define EXTI_LINE_32                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x00U)

+#define EXTI_LINE_33                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x01U)

+#define EXTI_LINE_34                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x02U)

+#define EXTI_LINE_35                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x03U)

+#define EXTI_LINE_36                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x04U)

+#define EXTI_LINE_37                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x05U)

+#define EXTI_LINE_38                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x06U)

+#define EXTI_LINE_39                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x07U)

+#define EXTI_LINE_40                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x08U)

+#define EXTI_LINE_41                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x09U)

+#define EXTI_LINE_42                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU)

+#define EXTI_LINE_43                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0BU)

+#if !defined(USB2_OTG_FS)

+#define EXTI_LINE_44                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE    | 0x0CU)

+#else

+#define EXTI_LINE_44                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU)

+#endif /* USB2_OTG_FS */

+#define EXTI_LINE_45                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE    | 0x0DU)

+#if defined(DSI)

+#define EXTI_LINE_46                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0EU)

+#else

+#define EXTI_LINE_46                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_NONE    | 0x0EU)

+#endif /* DSI */

+#define EXTI_LINE_47                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x0FU)

+#define EXTI_LINE_48                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x10U)

+#define EXTI_LINE_49                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x11U)

+#define EXTI_LINE_50                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x12U)

+#define EXTI_LINE_51                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x13U)

+#if !defined(UART9)

+#define EXTI_LINE_52                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x14U)

+#else

+#define EXTI_LINE_52                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x14U)

+#endif /* UART9 */

+#if !defined(USART10)

+#define EXTI_LINE_53                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL     | 0x15U)

+#else

+#define EXTI_LINE_53                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x15U)

+#endif /* USART10 */

+#define EXTI_LINE_54                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x16U)

+#define EXTI_LINE_55                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)

+#define EXTI_LINE_56                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x18U)

+#define EXTI_LINE_57                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x19U)

+#define EXTI_LINE_58                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1AU)

+#define EXTI_LINE_59                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1BU)

+#define EXTI_LINE_60                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1CU)

+#define EXTI_LINE_61                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1DU)

+#define EXTI_LINE_62                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1EU)

+#define EXTI_LINE_63                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG2 | EXTI_TARGET_MSK_ALL_CPU | 0x1FU)

+#define EXTI_LINE_64                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x00U)

+#define EXTI_LINE_65                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x01U)

+#define EXTI_LINE_66                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x02U)

+#define EXTI_LINE_67                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x03U)

+#define EXTI_LINE_68                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x04U)

+#define EXTI_LINE_69                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x05U)

+#define EXTI_LINE_70                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x06U)

+#define EXTI_LINE_71                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x07U)

+#define EXTI_LINE_72                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x08U)

+#define EXTI_LINE_73                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x09U)

+#define EXTI_LINE_74                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0AU)

+#if defined(ADC3)

+#define EXTI_LINE_75                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0BU)

+#else

+#define EXTI_LINE_75                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 |  EXTI_TARGET_MSK_NONE   | 0x0BU)

+#endif /* ADC3 */

+#if defined(SAI4)

+#define EXTI_LINE_76                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x0CU)

+#else

+#define EXTI_LINE_76                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 |  EXTI_TARGET_MSK_NONE   | 0x0CU)

+#endif /* SAI4 */

+#if defined (DUAL_CORE)

+#define EXTI_LINE_77                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0DU)

+#define EXTI_LINE_78                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x0EU)

+#define EXTI_LINE_79                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x0FU)

+#define EXTI_LINE_80                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x10U)

+#else

+#define EXTI_LINE_77                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0DU)

+#define EXTI_LINE_78                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0EU)

+#define EXTI_LINE_79                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x0FU)

+#define EXTI_LINE_80                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x10U)

+#endif /* DUAL_CORE */

+

+#define EXTI_LINE_81                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x11U)

+

+#if defined (DUAL_CORE)

+#define EXTI_LINE_82                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU2| 0x12U)

+#else

+#define EXTI_LINE_82                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x12U)

+#endif /* DUAL_CORE */

+

+#define EXTI_LINE_83                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x13U)

+#if defined (DUAL_CORE)

+#define EXTI_LINE_84                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_CPU1| 0x14U)

+#else

+#define EXTI_LINE_84                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x14U)

+#endif /* DUAL_CORE */

+#define EXTI_LINE_85                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x15U)

+#if defined(ETH)

+#define EXTI_LINE_86                        (EXTI_CONFIG   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x16U)

+#else

+#define EXTI_LINE_86                        (EXTI_RESERVED | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_NONE| 0x16U)

+#endif /* ETH */

+#define EXTI_LINE_87                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL_CPU | 0x17U)

+#if defined(DTS)

+#define EXTI_LINE_88                        (EXTI_DIRECT   | EXTI_EVENT | EXTI_REG3 | EXTI_TARGET_MSK_ALL | 0x18U)

+#endif /* DTS */

+

+/**

+  * @}

+  */

+

+/** @defgroup EXTI_Mode  EXTI Mode

+  * @{

+  */

+#define EXTI_MODE_NONE                      0x00000000U

+#define EXTI_MODE_INTERRUPT                 0x00000001U

+#define EXTI_MODE_EVENT                     0x00000002U

+#if defined(DUAL_CORE)

+#define EXTI_MODE_CORE1_INTERRUPT           EXTI_MODE_INTERRUPT

+#define EXTI_MODE_CORE1_EVENT               EXTI_MODE_EVENT

+#define EXTI_MODE_CORE2_INTERRUPT           0x00000010U

+#define EXTI_MODE_CORE2_EVENT               0x00000020U

+#endif /* DUAL_CORE */

+/**

+  * @}

+  */

+

+/** @defgroup EXTI_Trigger  EXTI Trigger

+  * @{

+  */

+#define EXTI_TRIGGER_NONE                   0x00000000U

+#define EXTI_TRIGGER_RISING                 0x00000001U

+#define EXTI_TRIGGER_FALLING                0x00000002U

+#define EXTI_TRIGGER_RISING_FALLING         (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)

+/**

+  * @}

+  */

+

+/** @defgroup EXTI_GPIOSel  EXTI GPIOSel

+  * @brief

+  * @{

+  */

+#define EXTI_GPIOA                          0x00000000U

+#define EXTI_GPIOB                          0x00000001U

+#define EXTI_GPIOC                          0x00000002U

+#define EXTI_GPIOD                          0x00000003U

+#define EXTI_GPIOE                          0x00000004U

+#define EXTI_GPIOF                          0x00000005U

+#define EXTI_GPIOG                          0x00000006U

+#define EXTI_GPIOH                          0x00000007U

+#define EXTI_GPIOI                          0x00000008U

+#define EXTI_GPIOJ                          0x00000009U

+#define EXTI_GPIOK                          0x0000000AU

+

+/**

+  * @}

+  */

+

+/** @defgroup EXTI_PendClear_Source  EXTI PendClear Source

+  * @brief

+  * @{

+  */

+#define EXTI_D3_PENDCLR_SRC_NONE       0x00000000U /*!< No D3 domain pendclear source , PMRx register to be set to zero  */

+#define EXTI_D3_PENDCLR_SRC_DMACH6     0x00000001U /*!< DMA ch6 event selected as D3 domain pendclear source, PMRx register to be set to 1 */

+#define EXTI_D3_PENDCLR_SRC_DMACH7     0x00000002U /*!< DMA ch7 event selected as D3 domain pendclear source, PMRx register to be set to 1*/

+#if defined (LPTIM4)

+#define EXTI_D3_PENDCLR_SRC_LPTIM4     0x00000003U /*!< LPTIM4 out selected as D3 domain pendclear source, PMRx register to be set to 1    */

+#else

+#define EXTI_D3_PENDCLR_SRC_LPTIM2     0x00000003U /*!< LPTIM2 out selected as D3 domain pendclear source, PMRx register to be set to 1    */

+#endif

+#if defined (LPTIM5)

+#define EXTI_D3_PENDCLR_SRC_LPTIM5     0x00000004U /*!< LPTIM5 out selected as D3 domain pendclear source, PMRx register to be set to 1    */

+#else

+#define EXTI_D3_PENDCLR_SRC_LPTIM3     0x00000004U /*!< LPTIM3 out selected as D3 domain pendclear source, PMRx register to be set to 1    */

+#endif

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup EXTI_Exported_Macros EXTI Exported Macros

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private constants --------------------------------------------------------*/

+/** @defgroup EXTI_Private_Constants EXTI Private Constants

+  * @{

+  */

+/**

+  * @brief  EXTI Line property definition

+  */

+#define EXTI_PROPERTY_SHIFT                 24U

+#define EXTI_DIRECT                         (0x01UL << EXTI_PROPERTY_SHIFT)

+#define EXTI_CONFIG                         (0x02UL << EXTI_PROPERTY_SHIFT)

+#define EXTI_GPIO                           ((0x04UL << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG)

+#define EXTI_RESERVED                       (0x08UL << EXTI_PROPERTY_SHIFT)

+#define EXTI_PROPERTY_MASK                  (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO)

+

+/**

+  * @brief  EXTI Event presence definition

+  */

+#define EXTI_EVENT_PRESENCE_SHIFT           28U

+#define EXTI_EVENT                          (0x01UL << EXTI_EVENT_PRESENCE_SHIFT)

+#define EXTI_EVENT_PRESENCE_MASK            (EXTI_EVENT)

+

+/**

+  * @brief  EXTI Register and bit usage

+  */

+#define EXTI_REG_SHIFT                      16U

+#define EXTI_REG1                           (0x00UL << EXTI_REG_SHIFT)

+#define EXTI_REG2                           (0x01UL << EXTI_REG_SHIFT)

+#define EXTI_REG3                           (0x02UL << EXTI_REG_SHIFT)

+#define EXTI_REG_MASK                       (EXTI_REG1 | EXTI_REG2 | EXTI_REG3)

+#define EXTI_PIN_MASK                       0x0000001FUL

+

+/**

+  * @brief  EXTI Target and bit usage

+  */

+#define EXTI_TARGET_SHIFT                   20U

+#define EXTI_TARGET_MSK_NONE                (0x00UL << EXTI_TARGET_SHIFT)

+#define EXTI_TARGET_MSK_D3SRD               (0x01UL << EXTI_TARGET_SHIFT)

+#define EXTI_TARGET_MSK_CPU1                (0x02UL << EXTI_TARGET_SHIFT)

+#if defined (DUAL_CORE)

+#define EXTI_TARGET_MSK_CPU2                (0x04UL << EXTI_TARGET_SHIFT)

+#define EXTI_TARGET_MASK                    (EXTI_TARGET_MSK_D3SRD | EXTI_TARGET_MSK_CPU1 | EXTI_TARGET_MSK_CPU2)

+#define EXTI_TARGET_MSK_ALL_CPU             (EXTI_TARGET_MSK_CPU1 | EXTI_TARGET_MSK_CPU2)

+#else

+#define EXTI_TARGET_MASK                    (EXTI_TARGET_MSK_D3SRD | EXTI_TARGET_MSK_CPU1)

+#define EXTI_TARGET_MSK_ALL_CPU              EXTI_TARGET_MSK_CPU1

+#endif /* DUAL_CORE */

+#define EXTI_TARGET_MSK_ALL                  EXTI_TARGET_MASK

+

+/**

+  * @brief  EXTI Mask for interrupt & event mode

+  */

+#if defined (DUAL_CORE)

+#define EXTI_MODE_MASK                      (EXTI_MODE_CORE1_EVENT | EXTI_MODE_CORE1_INTERRUPT | EXTI_MODE_CORE2_INTERRUPT | EXTI_MODE_CORE2_EVENT)

+#else

+#define EXTI_MODE_MASK                      (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT)

+#endif /* DUAL_CORE */

+

+/**

+  * @brief  EXTI Mask for trigger possibilities

+  */

+#define EXTI_TRIGGER_MASK                   (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING)

+

+/**

+  * @brief  EXTI Line number

+  */

+#if defined (EXTI_LINE_88)

+#define EXTI_LINE_NB                        89UL

+#else

+#define EXTI_LINE_NB                        88UL

+#endif /* EXTI_LINE_88 */

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup EXTI_Private_Macros EXTI Private Macros

+  * @{

+  */

+#define IS_EXTI_PROPERTY(__LINE__)      ((((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \

+                                         (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG)          || \

+                                         (((__LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO))

+#if defined (DUAL_CORE)

+#define IS_EXTI_TARGET(__LINE__)        ((((__LINE__) & EXTI_TARGET_MASK)   == EXTI_TARGET_MSK_CPU1)      || \

+                                         (((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU2)    || \

+                                         (((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL_CPU) || \

+                                         (((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL))

+#else

+#define IS_EXTI_TARGET(__LINE__)        ((((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_CPU1)   || \

+                                         (((__LINE__) & EXTI_TARGET_MASK) == EXTI_TARGET_MSK_ALL))

+#endif

+

+#define IS_EXTI_LINE(__LINE__)          ((((__LINE__) & ~(EXTI_PROPERTY_MASK | EXTI_EVENT_PRESENCE_MASK | EXTI_REG_MASK | EXTI_PIN_MASK | EXTI_TARGET_MASK)) == 0x00UL) && \

+                                         IS_EXTI_PROPERTY(__LINE__) && IS_EXTI_TARGET(__LINE__) && \

+                                         (((__LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK))      < \

+                                         (((EXTI_LINE_NB / 32UL) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32UL))))

+

+#define IS_EXTI_MODE(__MODE__)          (((__MODE__) & ~EXTI_MODE_MASK) == 0x00UL)

+

+#define IS_EXTI_TRIGGER(__LINE__)       (((__LINE__) & ~EXTI_TRIGGER_MASK) == 0x00UL)

+

+#define IS_EXTI_PENDING_EDGE(__LINE__)  (((__LINE__) == EXTI_TRIGGER_RISING) || \

+                                         ((__LINE__) == EXTI_TRIGGER_FALLING)|| \

+                                         ((__LINE__) == EXTI_TRIGGER_RISING_FALLING))

+

+#define IS_EXTI_CONFIG_LINE(__LINE__)   (((__LINE__) & EXTI_CONFIG) != 0x00UL)

+

+#define IS_EXTI_GPIO_PORT(__PORT__)     (((__PORT__) == EXTI_GPIOA) || \

+                                         ((__PORT__) == EXTI_GPIOB) || \

+                                         ((__PORT__) == EXTI_GPIOC) || \

+                                         ((__PORT__) == EXTI_GPIOD) || \

+                                         ((__PORT__) == EXTI_GPIOE) || \

+                                         ((__PORT__) == EXTI_GPIOF) || \

+                                         ((__PORT__) == EXTI_GPIOG) || \

+                                         ((__PORT__) == EXTI_GPIOH) || \

+                                         ((__PORT__) == EXTI_GPIOI) || \

+                                         ((__PORT__) == EXTI_GPIOJ) || \

+                                         ((__PORT__) == EXTI_GPIOK))

+

+#define IS_EXTI_GPIO_PIN(__PIN__)       ((__PIN__) < 16UL)

+#if defined (LPTIM4) && defined (LPTIM5)

+#define IS_EXTI_D3_PENDCLR_SRC(__SRC__) (((__SRC__) == EXTI_D3_PENDCLR_SRC_NONE) || \

+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH6) || \

+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH7) || \

+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM4) || \

+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM5))

+#else

+#define IS_EXTI_D3_PENDCLR_SRC(__SRC__) (((__SRC__) == EXTI_D3_PENDCLR_SRC_NONE) || \

+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH6) || \

+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_DMACH7) || \

+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM2) || \

+                                         ((__SRC__) == EXTI_D3_PENDCLR_SRC_LPTIM3))

+#endif /* LPTIM4 && LPTIM5 */

+

+/**

+  * @}

+  */

+

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup EXTI_Exported_Functions EXTI Exported Functions

+  * @brief    EXTI Exported Functions

+  * @{

+  */

+

+/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions

+  * @brief    Configuration functions

+  * @{

+  */

+/* Configuration functions ****************************************************/

+HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);

+HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig);

+HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti);

+HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void));

+HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine);

+/**

+  * @}

+  */

+

+/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions

+  * @brief    IO operation functions

+  * @{

+  */

+/* IO operation functions *****************************************************/

+void              HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti);

+uint32_t          HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);

+void              HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge);

+void              HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_EXTI_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_fdcan.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_fdcan.h
new file mode 100644
index 0000000000..cfe58cf7c9
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_fdcan.h
@@ -0,0 +1,2414 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_fdcan.h

+  * @author  MCD Application Team

+  * @brief   Header file of FDCAN HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_FDCAN_H

+#define STM32H7xx_HAL_FDCAN_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup FDCAN

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup FDCAN_Exported_Types FDCAN Exported Types

+  * @{

+  */

+

+/**

+  * @brief HAL State structures definition

+  */

+typedef enum

+{

+  HAL_FDCAN_STATE_RESET      = 0x00U, /*!< FDCAN not yet initialized or disabled */

+  HAL_FDCAN_STATE_READY      = 0x01U, /*!< FDCAN initialized and ready for use   */

+  HAL_FDCAN_STATE_BUSY       = 0x02U, /*!< FDCAN process is ongoing              */

+  HAL_FDCAN_STATE_ERROR      = 0x03U  /*!< FDCAN error state                     */

+} HAL_FDCAN_StateTypeDef;

+

+/**

+  * @brief FDCAN Init structure definition

+  */

+typedef struct

+{

+  uint32_t FrameFormat;                  /*!< Specifies the FDCAN frame format.

+                                              This parameter can be a value of @ref FDCAN_frame_format     */

+

+  uint32_t Mode;                         /*!< Specifies the FDCAN mode.

+                                              This parameter can be a value of @ref FDCAN_operating_mode   */

+

+  FunctionalState AutoRetransmission;    /*!< Enable or disable the automatic retransmission mode.

+                                              This parameter can be set to ENABLE or DISABLE               */

+

+  FunctionalState TransmitPause;         /*!< Enable or disable the Transmit Pause feature.

+                                              This parameter can be set to ENABLE or DISABLE               */

+

+  FunctionalState ProtocolException;      /*!< Enable or disable the Protocol Exception Handling.

+                                              This parameter can be set to ENABLE or DISABLE               */

+

+  uint32_t NominalPrescaler;             /*!< Specifies the value by which the oscillator frequency is

+                                              divided for generating the nominal bit time quanta.

+                                              This parameter must be a number between 1 and 512            */

+

+  uint32_t NominalSyncJumpWidth;         /*!< Specifies the maximum number of time quanta the FDCAN

+                                              hardware is allowed to lengthen or shorten a bit to perform

+                                              resynchronization.

+                                              This parameter must be a number between 1 and 128            */

+

+  uint32_t NominalTimeSeg1;              /*!< Specifies the number of time quanta in Bit Segment 1.

+                                              This parameter must be a number between 2 and 256            */

+

+  uint32_t NominalTimeSeg2;              /*!< Specifies the number of time quanta in Bit Segment 2.

+                                              This parameter must be a number between 2 and 128            */

+

+  uint32_t DataPrescaler;                /*!< Specifies the value by which the oscillator frequency is

+                                              divided for generating the data bit time quanta.

+                                              This parameter must be a number between 1 and 32             */

+

+  uint32_t DataSyncJumpWidth;            /*!< Specifies the maximum number of time quanta the FDCAN

+                                              hardware is allowed to lengthen or shorten a data bit to

+                                              perform resynchronization.

+                                              This parameter must be a number between 1 and 16             */

+

+  uint32_t DataTimeSeg1;                 /*!< Specifies the number of time quanta in Data Bit Segment 1.

+                                              This parameter must be a number between 1 and 32             */

+

+  uint32_t DataTimeSeg2;                 /*!< Specifies the number of time quanta in Data Bit Segment 2.

+                                              This parameter must be a number between 1 and 16             */

+

+  uint32_t MessageRAMOffset;             /*!< Specifies the message RAM start address.

+                                              This parameter must be a number between 0 and 2560           */

+

+  uint32_t StdFiltersNbr;                /*!< Specifies the number of standard Message ID filters.

+                                              This parameter must be a number between 0 and 128            */

+

+  uint32_t ExtFiltersNbr;                /*!< Specifies the number of extended Message ID filters.

+                                              This parameter must be a number between 0 and 64             */

+

+  uint32_t RxFifo0ElmtsNbr;              /*!< Specifies the number of Rx FIFO0 Elements.

+                                              This parameter must be a number between 0 and 64             */

+

+  uint32_t RxFifo0ElmtSize;              /*!< Specifies the Data Field Size in an Rx FIFO 0 element.

+                                              This parameter can be a value of @ref FDCAN_data_field_size  */

+

+  uint32_t RxFifo1ElmtsNbr;              /*!< Specifies the number of Rx FIFO 1 Elements.

+                                              This parameter must be a number between 0 and 64             */

+

+  uint32_t RxFifo1ElmtSize;              /*!< Specifies the Data Field Size in an Rx FIFO 1 element.

+                                              This parameter can be a value of @ref FDCAN_data_field_size  */

+

+  uint32_t RxBuffersNbr;                 /*!< Specifies the number of Dedicated Rx Buffer elements.

+                                              This parameter must be a number between 0 and 64             */

+

+  uint32_t RxBufferSize;                 /*!< Specifies the Data Field Size in an Rx Buffer element.

+                                              This parameter can be a value of @ref FDCAN_data_field_size  */

+

+  uint32_t TxEventsNbr;                  /*!< Specifies the number of Tx Event FIFO elements.

+                                              This parameter must be a number between 0 and 32             */

+

+  uint32_t TxBuffersNbr;                 /*!< Specifies the number of Dedicated Tx Buffers.

+                                              This parameter must be a number between 0 and 32             */

+

+  uint32_t TxFifoQueueElmtsNbr;          /*!< Specifies the number of Tx Buffers used for Tx FIFO/Queue.

+                                              This parameter must be a number between 0 and 32             */

+

+  uint32_t TxFifoQueueMode;              /*!< Tx FIFO/Queue Mode selection.

+                                              This parameter can be a value of @ref FDCAN_txFifoQueue_Mode */

+

+  uint32_t TxElmtSize;                   /*!< Specifies the Data Field Size in a Tx Element.

+                                              This parameter can be a value of @ref FDCAN_data_field_size  */

+

+} FDCAN_InitTypeDef;

+

+/**

+  * @brief  FDCAN clock calibration unit structure definition

+  */

+typedef struct

+{

+  uint32_t ClockCalibration;     /*!< Enable or disable the clock calibration.

+                                      This parameter can be a value of @ref FDCAN_clock_calibration.       */

+

+  uint32_t ClockDivider;         /*!< Specifies the FDCAN kernel clock divider when the clock calibration

+                                      is bypassed.

+                                      This parameter can be a value of @ref FDCAN_clock_divider            */

+

+  uint32_t MinOscClkPeriods;     /*!< Configures the minimum number of periods in two CAN bit times. The

+                                      actual configured number of periods is MinOscClkPeriods x 32.

+                                      This parameter must be a number between 0x00 and 0xFF                */

+

+  uint32_t CalFieldLength;       /*!< Specifies the calibration field length.

+                                      This parameter can be a value of @ref FDCAN_calibration_field_length */

+

+  uint32_t TimeQuantaPerBitTime; /*!< Configures the number of time quanta per bit time.

+                                      This parameter must be a number between 4 and 25                     */

+

+  uint32_t WatchdogStartValue;   /*!< Start value of the Calibration Watchdog Counter.

+                                      If set to zero the counter is disabled.

+                                      This parameter must be a number between 0x0000 and 0xFFFF            */

+

+} FDCAN_ClkCalUnitTypeDef;

+

+/**

+  * @brief  FDCAN filter structure definition

+  */

+typedef struct

+{

+  uint32_t IdType;           /*!< Specifies the identifier type.

+                                  This parameter can be a value of @ref FDCAN_id_type       */

+

+  uint32_t FilterIndex;      /*!< Specifies the filter which will be initialized.

+                                  This parameter must be a number between:

+                                   - 0 and 127, if IdType is FDCAN_STANDARD_ID

+                                   - 0 and 63, if IdType is FDCAN_EXTENDED_ID               */

+

+  uint32_t FilterType;       /*!< Specifies the filter type.

+                                  This parameter can be a value of @ref FDCAN_filter_type.

+                                  The value FDCAN_EXT_FILTER_RANGE_NO_EIDM is permitted

+                                  only when IdType is FDCAN_EXTENDED_ID.

+                                  This parameter is ignored if FilterConfig is set to

+                                  FDCAN_FILTER_TO_RXBUFFER                                  */

+

+  uint32_t FilterConfig;     /*!< Specifies the filter configuration.

+                                  This parameter can be a value of @ref FDCAN_filter_config */

+

+  uint32_t FilterID1;        /*!< Specifies the filter identification 1.

+                                  This parameter must be a number between:

+                                   - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID

+                                   - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID       */

+

+  uint32_t FilterID2;        /*!< Specifies the filter identification 2.

+                                  This parameter is ignored if FilterConfig is set to

+                                  FDCAN_FILTER_TO_RXBUFFER.

+                                  This parameter must be a number between:

+                                   - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID

+                                   - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID       */

+

+  uint32_t RxBufferIndex;    /*!< Contains the index of the Rx buffer in which the

+                                  matching message will be stored.

+                                  This parameter must be a number between 0 and 63.

+                                  This parameter is ignored if FilterConfig is different

+                                  from FDCAN_FILTER_TO_RXBUFFER                             */

+

+  uint32_t IsCalibrationMsg; /*!< Specifies whether the filter is configured for

+                                  calibration messages.

+                                  This parameter is ignored if FilterConfig is different

+                                  from FDCAN_FILTER_TO_RXBUFFER.

+                                  This parameter can be:

+                                   - 0 : ordinary message

+                                   - 1 : calibration message                                */

+

+} FDCAN_FilterTypeDef;

+

+/**

+  * @brief  FDCAN Tx header structure definition

+  */

+typedef struct

+{

+  uint32_t Identifier;          /*!< Specifies the identifier.

+                                     This parameter must be a number between:

+                                      - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID

+                                      - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */

+

+  uint32_t IdType;              /*!< Specifies the identifier type for the message that will be

+                                     transmitted.

+                                     This parameter can be a value of @ref FDCAN_id_type               */

+

+  uint32_t TxFrameType;         /*!< Specifies the frame type of the message that will be transmitted.

+                                     This parameter can be a value of @ref FDCAN_frame_type            */

+

+  uint32_t DataLength;          /*!< Specifies the length of the frame that will be transmitted.

+                                      This parameter can be a value of @ref FDCAN_data_length_code     */

+

+  uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.

+                                     This parameter can be a value of @ref FDCAN_error_state_indicator */

+

+  uint32_t BitRateSwitch;       /*!< Specifies whether the Tx frame will be transmitted with or without

+                                     bit rate switching.

+                                     This parameter can be a value of @ref FDCAN_bit_rate_switching    */

+

+  uint32_t FDFormat;            /*!< Specifies whether the Tx frame will be transmitted in classic or

+                                     FD format.

+                                     This parameter can be a value of @ref FDCAN_format                */

+

+  uint32_t TxEventFifoControl;  /*!< Specifies the event FIFO control.

+                                     This parameter can be a value of @ref FDCAN_EFC                   */

+

+  uint32_t MessageMarker;       /*!< Specifies the message marker to be copied into Tx Event FIFO

+                                     element for identification of Tx message status.

+                                     This parameter must be a number between 0 and 0xFF                */

+

+} FDCAN_TxHeaderTypeDef;

+

+/**

+  * @brief  FDCAN Rx header structure definition

+  */

+typedef struct

+{

+  uint32_t Identifier;            /*!< Specifies the identifier.

+                                       This parameter must be a number between:

+                                        - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID

+                                        - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */

+

+  uint32_t IdType;                /*!< Specifies the identifier type of the received message.

+                                       This parameter can be a value of @ref FDCAN_id_type               */

+

+  uint32_t RxFrameType;           /*!< Specifies the the received message frame type.

+                                       This parameter can be a value of @ref FDCAN_frame_type            */

+

+  uint32_t DataLength;            /*!< Specifies the received frame length.

+                                        This parameter can be a value of @ref FDCAN_data_length_code     */

+

+  uint32_t ErrorStateIndicator;   /*!< Specifies the error state indicator.

+                                       This parameter can be a value of @ref FDCAN_error_state_indicator */

+

+  uint32_t BitRateSwitch;         /*!< Specifies whether the Rx frame is received with or without bit

+                                       rate switching.

+                                       This parameter can be a value of @ref FDCAN_bit_rate_switching    */

+

+  uint32_t FDFormat;              /*!< Specifies whether the Rx frame is received in classic or FD

+                                       format.

+                                       This parameter can be a value of @ref FDCAN_format                */

+

+  uint32_t RxTimestamp;           /*!< Specifies the timestamp counter value captured on start of frame

+                                       reception.

+                                       This parameter must be a number between 0 and 0xFFFF              */

+

+  uint32_t FilterIndex;           /*!< Specifies the index of matching Rx acceptance filter element.

+                                       This parameter must be a number between:

+                                        - 0 and 127, if IdType is FDCAN_STANDARD_ID

+                                        - 0 and 63, if IdType is FDCAN_EXTENDED_ID                       */

+

+  uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter.

+                                         Acceptance of non-matching frames may be enabled via

+                                         HAL_FDCAN_ConfigGlobalFilter().

+                                         This parameter can be 0 or 1                                    */

+

+} FDCAN_RxHeaderTypeDef;

+

+/**

+  * @brief  FDCAN Tx event FIFO structure definition

+  */

+typedef struct

+{

+  uint32_t Identifier;          /*!< Specifies the identifier.

+                                     This parameter must be a number between:

+                                      - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID

+                                      - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID               */

+

+  uint32_t IdType;              /*!< Specifies the identifier type for the transmitted message.

+                                     This parameter can be a value of @ref FDCAN_id_type               */

+

+  uint32_t TxFrameType;         /*!< Specifies the frame type of the transmitted message.

+                                     This parameter can be a value of @ref FDCAN_frame_type            */

+

+  uint32_t DataLength;          /*!< Specifies the length of the transmitted frame.

+                                     This parameter can be a value of @ref FDCAN_data_length_code      */

+

+  uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.

+                                     This parameter can be a value of @ref FDCAN_error_state_indicator */

+

+  uint32_t BitRateSwitch;       /*!< Specifies whether the Tx frame is transmitted with or without bit

+                                     rate switching.

+                                     This parameter can be a value of @ref FDCAN_bit_rate_switching    */

+

+  uint32_t FDFormat;            /*!< Specifies whether the Tx frame is transmitted in classic or FD

+                                     format.

+                                     This parameter can be a value of @ref FDCAN_format                */

+

+  uint32_t TxTimestamp;         /*!< Specifies the timestamp counter value captured on start of frame

+                                     transmission.

+                                     This parameter must be a number between 0 and 0xFFFF              */

+

+  uint32_t MessageMarker;       /*!< Specifies the message marker copied into Tx Event FIFO element

+                                     for identification of Tx message status.

+                                     This parameter must be a number between 0 and 0xFF                */

+

+  uint32_t EventType;           /*!< Specifies the event type.

+                                     This parameter can be a value of @ref FDCAN_event_type            */

+

+} FDCAN_TxEventFifoTypeDef;

+

+/**

+  * @brief  FDCAN High Priority Message Status structure definition

+  */

+typedef struct

+{

+  uint32_t FilterList;     /*!< Specifies the filter list of the matching filter element.

+                                This parameter can be:

+                                 - 0 : Standard Filter List

+                                 - 1 : Extended Filter List                                */

+

+  uint32_t FilterIndex;    /*!< Specifies the index of matching filter element.

+                                This parameter can be a number between:

+                                - 0 and 127, if FilterList is 0 (Standard)

+                                - 0 and 63, if FilterList is 1 (Extended)                  */

+

+  uint32_t MessageStorage; /*!< Specifies the HP Message Storage.

+                                This parameter can be a value of @ref FDCAN_hp_msg_storage */

+

+  uint32_t MessageIndex;   /*!< Specifies the Index of Rx FIFO element to which the

+                                message was stored.

+                                This parameter is valid only when MessageStorage is:

+                                  FDCAN_HP_STORAGE_RXFIFO0

+                                 or

+                                  FDCAN_HP_STORAGE_RXFIFO1                                 */

+

+} FDCAN_HpMsgStatusTypeDef;

+

+/**

+  * @brief FDCAN Protocol Status structure definition

+  */

+typedef struct

+{

+  uint32_t LastErrorCode;     /*!< Specifies the type of the last error that occurred on the FDCAN bus.

+                                   This parameter can be a value of @ref FDCAN_protocol_error_code                           */

+

+  uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase of a CAN FD format

+                                   frame with its BRS flag set.

+                                   This parameter can be a value of @ref FDCAN_protocol_error_code                           */

+

+  uint32_t Activity;          /*!< Specifies the FDCAN module communication state.

+                                   This parameter can be a value of @ref FDCAN_communication_state                           */

+

+  uint32_t ErrorPassive;      /*!< Specifies the FDCAN module error status.

+                                   This parameter can be:

+                                    - 0 : The FDCAN is in Error_Active state

+                                    - 1 : The FDCAN is in Error_Passive state                                                */

+

+  uint32_t Warning;           /*!< Specifies the FDCAN module warning status.

+                                   This parameter can be:

+                                    - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the Error_Warning limit of 96

+                                    - 1 : at least one of error counters has reached the Error_Warning limit of 96           */

+

+  uint32_t BusOff;            /*!< Specifies the FDCAN module Bus_Off status.

+                                   This parameter can be:

+                                    - 0 : The FDCAN is not in Bus_Off state

+                                    - 1 : The FDCAN is in Bus_Off state                                                      */

+

+  uint32_t RxESIflag;         /*!< Specifies ESI flag of last received CAN FD message.

+                                   This parameter can be:

+                                    - 0 : Last received CAN FD message did not have its ESI flag set

+                                    - 1 : Last received CAN FD message had its ESI flag set                                  */

+

+  uint32_t RxBRSflag;         /*!< Specifies BRS flag of last received CAN FD message.

+                                   This parameter can be:

+                                    - 0 : Last received CAN FD message did not have its BRS flag set

+                                    - 1 : Last received CAN FD message had its BRS flag set                                  */

+

+  uint32_t RxFDFflag;         /*!< Specifies if CAN FD message (FDF flag set) has been received since last protocol status.

+                                   This parameter can be:

+                                    - 0 : no CAN FD message received

+                                    - 1 : CAN FD message received                                                            */

+

+  uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status.

+                                   This parameter can be:

+                                    - 0 : No protocol exception event occurred since last read access

+                                    - 1 : Protocol exception event occurred                                                  */

+

+  uint32_t TDCvalue;          /*!< Specifies the Transmitter Delay Compensation Value.

+                                   This parameter can be a number between 0 and 127                                          */

+

+} FDCAN_ProtocolStatusTypeDef;

+

+/**

+  * @brief FDCAN Error Counters structure definition

+  */

+typedef struct

+{

+  uint32_t TxErrorCnt;     /*!< Specifies the Transmit Error Counter Value.

+                                This parameter can be a number between 0 and 255                                         */

+

+  uint32_t RxErrorCnt;     /*!< Specifies the Receive Error Counter Value.

+                                This parameter can be a number between 0 and 127                                         */

+

+  uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status.

+                                This parameter can be:

+                                 - 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128

+                                 - 1 : The Receive Error Counter (RxErrorCnt) has reached the error passive level of 128 */

+

+  uint32_t ErrorLogging;   /*!< Specifies the Transmit/Receive error logging counter value.

+                                This parameter can be a number between 0 and 255.

+                                This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt

+                                or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of

+                                TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW           */

+

+} FDCAN_ErrorCountersTypeDef;

+

+/**

+  * @brief FDCAN TT Init structure definition

+  */

+typedef struct

+{

+  uint32_t OperationMode;     /*!< Specifies the FDCAN Operation Mode.

+                                   This parameter can be a value of @ref FDCAN_operation_mode               */

+

+  uint32_t GapEnable;         /*!< Specifies the FDCAN TT Operation.

+                                   This parameter can be a value of @ref FDCAN_TT_operation.

+                                   This parameter is ignored if OperationMode is set to

+                                   FDCAN_TT_COMMUNICATION_LEVEL0                                            */

+

+  uint32_t TimeMaster;        /*!< Specifies whether the instance is a slave or a potential master.

+                                   This parameter can be a value of @ref FDCAN_TT_time_master               */

+

+  uint32_t SyncDevLimit;      /*!< Specifies the Synchronization Deviation Limit SDL of the TUR

+                                   numerator : TUR = (Numerator ± SDL) / Denominator.

+                                   With : SDL = 2^(SyncDevLimit+5).

+                                   This parameter must be a number between 0 and 7                          */

+

+  uint32_t InitRefTrigOffset; /*!< Specifies the Initial Reference Trigger Offset.

+                                   This parameter must be a number between 0 and 127                        */

+

+  uint32_t ExternalClkSync;   /*!< Enable or disable External Clock Synchronization.

+                                   This parameter can be a value of @ref FDCAN_TT_external_clk_sync.

+                                   This parameter is ignored if OperationMode is set to

+                                   FDCAN_TT_COMMUNICATION_LEVEL1                                            */

+

+  uint32_t AppWdgLimit;       /*!< Specifies the Application Watchdog Limit : maximum time after

+                                   which the application has to serve the application watchdog.

+                                   The application watchdog is incremented once each 256 NTUs.

+                                   The application watchdog can be disabled by setting AppWdgLimit to 0.

+                                   This parameter must be a number between 0 and 255.

+                                   This parameter is ignored if OperationMode is set to

+                                   FDCAN_TT_COMMUNICATION_LEVEL0                                            */

+

+  uint32_t GlobalTimeFilter;  /*!< Enable or disable Global Time Filtering.

+                                   This parameter can be a value of @ref FDCAN_TT_global_time_filtering.

+                                   This parameter is ignored if OperationMode is set to

+                                   FDCAN_TT_COMMUNICATION_LEVEL1                                            */

+

+  uint32_t ClockCalibration;  /*!< Enable or disable Automatic Clock Calibration.

+                                   This parameter can be a value of @ref FDCAN_TT_auto_clk_calibration.

+                                   This parameter is ignored if OperationMode is set to

+                                   FDCAN_TT_COMMUNICATION_LEVEL1                                            */

+

+  uint32_t EvtTrigPolarity;   /*!< Specifies the Event Trigger Polarity.

+                                   This parameter can be a value of @ref FDCAN_TT_event_trig_polarity.

+                                   This parameter is ignored if OperationMode is set to

+                                   FDCAN_TT_COMMUNICATION_LEVEL0                                            */

+

+  uint32_t BasicCyclesNbr;    /*!< Specifies the nubmer of basic cycles in the system matrix.

+                                   This parameter can be a value of @ref FDCAN_TT_basic_cycle_number        */

+

+  uint32_t CycleStartSync;    /*!< Enable or disable synchronization pulse output at pin fdcan1_soc.

+                                   This parameter can be a value of @ref FDCAN_TT_cycle_start_sync          */

+

+  uint32_t TxEnableWindow;    /*!< Specifies the length of Tx enable window in NTUs.

+                                   This parameter must be a number between 1 and 16                         */

+

+  uint32_t ExpTxTrigNbr;      /*!< Specifies the number of expected Tx_Triggers in the system matrix.

+                                   This is the sum of Tx_Triggers for exclusive, single arbitrating and

+                                   merged arbitrating windows.

+                                   This parameter must be a number between 0 and 4095                       */

+

+  uint32_t TURNumerator;      /*!< Specifies the TUR (Time Unit Ratio) numerator.

+                                   It is adviced to set this parameter to the largest applicable value.

+                                   This parameter must be a number between 0x10000 and 0x1FFFF              */

+

+  uint32_t TURDenominator;    /*!< Specifies the TUR (Time Unit Ratio) denominator.

+                                   This parameter must be a number between 0x0001 and 0x3FFF                */

+

+  uint32_t TriggerMemoryNbr;  /*!< Specifies the number of trigger memory elements.

+                                   This parameter must be a number between 0 and 64                         */

+

+  uint32_t StopWatchTrigSel;  /*!< Specifies the input to be used as stop watch trigger.

+                                   This parameter can be a value of @ref FDCAN_TT_stop_watch_trig_selection */

+

+  uint32_t EventTrigSel;      /*!< Specifies the input to be used as event trigger.

+                                   This parameter can be a value of @ref FDCAN_TT_event_trig_selection      */

+

+} FDCAN_TT_ConfigTypeDef;

+

+/**

+  * @brief  FDCAN Trigger structure definition

+  */

+typedef struct

+{

+  uint32_t TriggerIndex;  /*!< Specifies the trigger which will be configured.

+                               This parameter must be a number between 0 and 63                                 */

+

+  uint32_t TimeMark;      /*!< Specifies the cycle time for which the trigger becomes active.

+                               This parameter must be a number between 0 and 0xFFFF                             */

+

+  uint32_t RepeatFactor;  /*!< Specifies the trigger repeat factor.

+                               This parameter can be a value of @ref FDCAN_TT_Repeat_Factor                     */

+

+  uint32_t StartCycle;    /*!< Specifies the index of the first cycle in which the trigger becomes active.

+                               This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE.

+                               This parameter must be a number between 0 and RepeatFactor                       */

+

+  uint32_t TmEventInt;    /*!< Enable or disable the internal time mark event.

+                               If enabled, FDCAN_TT_FLAG_TRIG_TIME_MARK flag is set when trigger memory element

+                               becomes active.

+                               This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_Internal          */

+

+  uint32_t TmEventExt;    /*!< Enable or disable the external time mark event.

+                               If enabled, and if TTOCN.TTIE is set, a pulse is generated at fdcan1_tmp when

+                               trigger memory element becomes active.

+                               This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_External          */

+

+  uint32_t TriggerType;   /*!< Specifies the trigger type.

+                               This parameter can be a value of @ref FDCAN_TT_Trigger_Type                      */

+

+  uint32_t FilterType;    /*!< Specifies the filter identifier type.

+                               This parameter can be a value of @ref FDCAN_id_type                              */

+

+  uint32_t TxBufferIndex; /*!< Specifies the index of the Tx buffer for which the trigger is valid.

+                               This parameter can be a value of @ref FDCAN_Tx_location.

+                               This parameter is taken in consideration only if the trigger is configured for

+                               transmission.                                                                    */

+

+  uint32_t FilterIndex;   /*!< Specifies the filter for which the trigger is valid.

+                               This parameter is taken in consideration only if the trigger is configured for

+                               reception.

+                               This parameter must be a number between:

+                                - 0 and 127, if FilterType is FDCAN_STANDARD_ID

+                                - 0 and 63, if FilterType is FDCAN_EXTENDED_ID                                  */

+

+} FDCAN_TriggerTypeDef;

+

+/**

+  * @brief  FDCAN TT Operation Status structure definition

+  */

+typedef struct

+{

+  uint32_t ErrorLevel;       /*!< Specifies the type of the TT operation error level.

+                                  This parameter can be a value of @ref FDCAN_TT_error_level                    */

+

+  uint32_t MasterState;      /*!< Specifies the type of the TT master state.

+                                  This parameter can be a value of @ref FDCAN_TT_master_state                   */

+

+  uint32_t SyncState;        /*!< Specifies the type of the TT synchronization state.

+                                  This parameter can be a value of @ref FDCAN_TT_sync_state                     */

+

+  uint32_t GTimeQuality;     /*!< Specifies the Quality of Global Time Phase.

+                                  This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 0.

+                                  This parameter can be:

+                                   - 0 : Global time not valid

+                                   - 1 : Global time in phase with Time Master                                  */

+

+  uint32_t ClockQuality;     /*!< Specifies the Quality of Clock Speed.

+                                  This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 1.

+                                  This parameter can be:

+                                   - 0 : Local clock speed not synchronized to Time Master clock speed

+                                   - 1 : Synchronization Deviation = SDL                                        */

+

+  uint32_t RefTrigOffset;    /*!< Specifies the Actual Reference Trigger Offset Value.

+                                  This parameter can be a number between 0 and 0xFF                             */

+

+  uint32_t GTimeDiscPending; /*!< Specifies the Global Time Discontinuity State.

+                                  This parameter can be:

+                                   - 0 : No global time preset pending

+                                   - 1 : Node waits for the global time preset to take effect                   */

+

+  uint32_t GapFinished;      /*!< Specifies whether a Gap is finished.

+                                  This parameter can be:

+                                   - 0 : Reset at the end of each reference message

+                                   - 1 : Gap finished                                                           */

+

+  uint32_t MasterPriority;   /*!< Specifies the Priority of actual Time Master.

+                                  This parameter can be a number between 0 and 0x7                              */

+

+  uint32_t GapStarted;       /*!< Specifies whether a Gap is started.

+                                  This parameter can be:

+                                   - 0 : No Gap in schedule

+                                   - 1 : Gap time after Basic Cycle has started                                 */

+

+  uint32_t WaitForEvt;       /*!< Specifies whether a Gap is annouced.

+                                  This parameter can be:

+                                   - 0 : No Gap announced, reset by a reference message with Next_is_Gap = 0

+                                   - 1 : Reference message with Next_is_Gap = 1 received                        */

+

+  uint32_t AppWdgEvt;        /*!< Specifies the Application Watchdog State.

+                                  This parameter can be:

+                                   - 0 : Application Watchdog served in time

+                                   - 1 : Failed to serve Application Watchdog in time                           */

+

+  uint32_t ECSPending;       /*!< Specifies the External Clock Synchronization State.

+                                  This parameter can be:

+                                   - 0 : No external clock synchronization pending

+                                   - 1 : Node waits for external clock synchronization to take effect           */

+

+  uint32_t PhaseLock;        /*!< Specifies the Phase Lock State.

+                                  This parameter can be:

+                                   - 0 : Phase outside range

+                                   - 1 : Phase inside range                                                     */

+

+} FDCAN_TTOperationStatusTypeDef;

+

+/**

+  * @brief  FDCAN Message RAM blocks

+  */

+typedef struct

+{

+  uint32_t StandardFilterSA; /*!< Specifies the Standard Filter List Start Address.

+                                  This parameter must be a 32-bit word address      */

+

+  uint32_t ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address.

+                                  This parameter must be a 32-bit word address      */

+

+  uint32_t RxFIFO0SA;        /*!< Specifies the Rx FIFO 0 Start Address.

+                                  This parameter must be a 32-bit word address      */

+

+  uint32_t RxFIFO1SA;        /*!< Specifies the Rx FIFO 1 Start Address.

+                                  This parameter must be a 32-bit word address      */

+

+  uint32_t RxBufferSA;       /*!< Specifies the Rx Buffer Start Address.

+                                  This parameter must be a 32-bit word address      */

+

+  uint32_t TxEventFIFOSA;    /*!< Specifies the Tx Event FIFO Start Address.

+                                  This parameter must be a 32-bit word address      */

+

+  uint32_t TxBufferSA;       /*!< Specifies the Tx Buffers Start Address.

+                                  This parameter must be a 32-bit word address      */

+

+  uint32_t TxFIFOQSA;        /*!< Specifies the Tx FIFO/Queue Start Address.

+                                  This parameter must be a 32-bit word address      */

+

+  uint32_t TTMemorySA;       /*!< Specifies the Trigger Memory Start Address.

+                                  This parameter must be a 32-bit word address      */

+

+  uint32_t EndAddress;       /*!< Specifies the End Address of the allocated RAM.

+                                  This parameter must be a 32-bit word address      */

+

+} FDCAN_MsgRamAddressTypeDef;

+

+/**

+  * @brief  FDCAN handle structure definition

+  */

+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1

+typedef struct __FDCAN_HandleTypeDef

+#else

+typedef struct

+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */

+{

+  FDCAN_GlobalTypeDef         *Instance;        /*!< Register base address     */

+

+  TTCAN_TypeDef               *ttcan;           /*!< TT register base address  */

+

+  FDCAN_InitTypeDef           Init;             /*!< FDCAN required parameters */

+

+  FDCAN_MsgRamAddressTypeDef  msgRam;           /*!< FDCAN Message RAM blocks  */

+

+  uint32_t                    LatestTxFifoQRequest; /*!< FDCAN Tx buffer index

+                                               of latest Tx FIFO/Queue request */

+

+  __IO HAL_FDCAN_StateTypeDef State;            /*!< FDCAN communication state */

+

+  HAL_LockTypeDef             Lock;             /*!< FDCAN locking object      */

+

+  __IO uint32_t               ErrorCode;        /*!< FDCAN Error code          */

+

+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1

+  void (* ClockCalibrationCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs);         /*!< FDCAN Clock Calibration callback          */

+  void (* TxEventFifoCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);                 /*!< FDCAN Tx Event Fifo callback              */

+  void (* RxFifo0Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);                         /*!< FDCAN Rx Fifo 0 callback                  */

+  void (* RxFifo1Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);                         /*!< FDCAN Rx Fifo 1 callback                  */

+  void (* TxFifoEmptyCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                          /*!< FDCAN Tx Fifo Empty callback              */

+  void (* TxBufferCompleteCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);             /*!< FDCAN Tx Buffer complete callback         */

+  void (* TxBufferAbortCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);                /*!< FDCAN Tx Buffer abort callback            */

+  void (* RxBufferNewMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                   /*!< FDCAN Rx Buffer New Message callback      */

+  void (* HighPriorityMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                  /*!< FDCAN High priority message callback      */

+  void (* TimestampWraparoundCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                  /*!< FDCAN Timestamp wraparound callback       */

+  void (* TimeoutOccurredCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                      /*!< FDCAN Timeout occurred callback           */

+  void (* ErrorCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                                /*!< FDCAN Error callback                      */

+  void (* ErrorStatusCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);                 /*!< FDCAN Error status callback               */

+  void (* TT_ScheduleSyncCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs);             /*!< FDCAN T Schedule Synchronization callback */

+  void (* TT_TimeMarkCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);                  /*!< FDCAN TT Time Mark callback               */

+  void (* TT_StopWatchCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); /*!< FDCAN TT Stop Watch callback              */

+  void (* TT_GlobalTimeCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);                /*!< FDCAN TT Global Time callback             */

+

+  void (* MspInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                              /*!< FDCAN Msp Init callback                   */

+  void (* MspDeInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan);                                            /*!< FDCAN Msp DeInit callback                 */

+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */

+

+} FDCAN_HandleTypeDef;

+

+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1

+/**

+  * @brief  HAL FDCAN common Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_FDCAN_TX_FIFO_EMPTY_CB_ID        = 0x00U, /*!< FDCAN Tx Fifo Empty callback ID         */

+  HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID    = 0x01U, /*!< FDCAN Rx buffer new message callback ID */

+  HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID    = 0x02U, /*!< FDCAN High priority message callback ID */

+  HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x03U, /*!< FDCAN Timestamp wraparound callback ID  */

+  HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID     = 0x04U, /*!< FDCAN Timeout occurred callback ID      */

+  HAL_FDCAN_ERROR_CALLBACK_CB_ID       = 0x05U, /*!< FDCAN Error callback ID                 */

+

+  HAL_FDCAN_MSPINIT_CB_ID              = 0x06U, /*!< FDCAN MspInit callback ID               */

+  HAL_FDCAN_MSPDEINIT_CB_ID            = 0x07U, /*!< FDCAN MspDeInit callback ID             */

+

+} HAL_FDCAN_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL FDCAN Callback pointer definition

+  */

+typedef  void (*pFDCAN_CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan);                                                     /*!< pointer to a common FDCAN callback function                    */

+typedef  void (*pFDCAN_ClockCalibrationCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs);         /*!< pointer to Clock Calibration FDCAN callback function           */

+typedef  void (*pFDCAN_TxEventFifoCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);                 /*!< pointer to Tx event Fifo FDCAN callback function               */

+typedef  void (*pFDCAN_RxFifo0CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);                         /*!< pointer to Rx Fifo 0 FDCAN callback function                   */

+typedef  void (*pFDCAN_RxFifo1CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);                         /*!< pointer to Rx Fifo 1 FDCAN callback function                   */

+typedef  void (*pFDCAN_TxBufferCompleteCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);             /*!< pointer to Tx Buffer complete FDCAN callback function          */

+typedef  void (*pFDCAN_TxBufferAbortCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);                /*!< pointer to Tx Buffer abort FDCAN callback function             */

+typedef  void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);                 /*!< pointer to Error Status callback function                      */

+typedef  void (*pFDCAN_TT_ScheduleSyncCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs);             /*!< pointer to TT Schedule Synchronization FDCAN callback function */

+typedef  void (*pFDCAN_TT_TimeMarkCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);                  /*!< pointer to TT Time Mark FDCAN callback function                */

+typedef  void (*pFDCAN_TT_StopWatchCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); /*!< pointer to TT Stop Watch FDCAN callback function               */

+typedef  void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);                /*!< pointer to TT Global Time FDCAN callback function              */

+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants

+  * @{

+  */

+

+/** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code

+  * @{

+  */

+#define HAL_FDCAN_ERROR_NONE            ((uint32_t)0x00000000U) /*!< No error                                                               */

+#define HAL_FDCAN_ERROR_TIMEOUT         ((uint32_t)0x00000001U) /*!< Timeout error                                                          */

+#define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U) /*!< Peripheral not initialized                                             */

+#define HAL_FDCAN_ERROR_NOT_READY       ((uint32_t)0x00000004U) /*!< Peripheral not ready                                                   */

+#define HAL_FDCAN_ERROR_NOT_STARTED     ((uint32_t)0x00000008U) /*!< Peripheral not started                                                 */

+#define HAL_FDCAN_ERROR_NOT_SUPPORTED   ((uint32_t)0x00000010U) /*!< Mode not supported                                                     */

+#define HAL_FDCAN_ERROR_PARAM           ((uint32_t)0x00000020U) /*!< Parameter error                                                        */

+#define HAL_FDCAN_ERROR_PENDING         ((uint32_t)0x00000040U) /*!< Pending operation                                                      */

+#define HAL_FDCAN_ERROR_RAM_ACCESS      ((uint32_t)0x00000080U) /*!< Message RAM Access Failure                                             */

+#define HAL_FDCAN_ERROR_FIFO_EMPTY      ((uint32_t)0x00000100U) /*!< Put element in full FIFO                                               */

+#define HAL_FDCAN_ERROR_FIFO_FULL       ((uint32_t)0x00000200U) /*!< Get element from empty FIFO                                            */

+#define HAL_FDCAN_ERROR_LOG_OVERFLOW    FDCAN_IR_ELO            /*!< Overflow of CAN Error Logging Counter                                  */

+#define HAL_FDCAN_ERROR_RAM_WDG         FDCAN_IR_WDI            /*!< Message RAM Watchdog event occurred                                    */

+#define HAL_FDCAN_ERROR_PROTOCOL_ARBT   FDCAN_IR_PEA            /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used)         */

+#define HAL_FDCAN_ERROR_PROTOCOL_DATA   FDCAN_IR_PED            /*!< Protocol Error in Data Phase (Data Bit Time is used)                   */

+#define HAL_FDCAN_ERROR_RESERVED_AREA   FDCAN_IR_ARA            /*!< Access to Reserved Address                                             */

+#define HAL_FDCAN_ERROR_TT_GLOBAL_TIME  FDCAN_TTIR_GTE          /*!< Global Time Error : Synchronization deviation exceeded limit           */

+#define HAL_FDCAN_ERROR_TT_TX_UNDERFLOW FDCAN_TTIR_TXU          /*!< Tx Count Underflow : Less Tx trigger than expected in one matrix cycle */

+#define HAL_FDCAN_ERROR_TT_TX_OVERFLOW  FDCAN_TTIR_TXO          /*!< Tx Count Overflow : More Tx trigger than expected in one matrix cycle  */

+#define HAL_FDCAN_ERROR_TT_SCHEDULE1    FDCAN_TTIR_SE1          /*!< Scheduling error 1                                                     */

+#define HAL_FDCAN_ERROR_TT_SCHEDULE2    FDCAN_TTIR_SE2          /*!< Scheduling error 2                                                     */

+#define HAL_FDCAN_ERROR_TT_NO_INIT_REF  FDCAN_TTIR_IWT          /*!< No system startup due to missing reference message                     */

+#define HAL_FDCAN_ERROR_TT_NO_REF       FDCAN_TTIR_WT           /*!< Missing reference message                                              */

+#define HAL_FDCAN_ERROR_TT_APPL_WDG     FDCAN_TTIR_AW           /*!< Application watchdog not served in time                                */

+#define HAL_FDCAN_ERROR_TT_CONFIG       FDCAN_TTIR_CER          /*!< Error found in trigger list                                            */

+

+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1

+#define HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U) /*!< Invalid Callback error                                                */

+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_frame_format FDCAN Frame Format

+  * @{

+  */

+#define FDCAN_FRAME_CLASSIC   ((uint32_t)0x00000000U)                         /*!< Classic mode                      */

+#define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE)                     /*!< FD mode without BitRate Switching */

+#define FDCAN_FRAME_FD_BRS    ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switching    */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_operating_mode FDCAN Operating Mode

+  * @{

+  */

+#define FDCAN_MODE_NORMAL               ((uint32_t)0x00000000U) /*!< Normal mode               */

+#define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U) /*!< Restricted Operation mode */

+#define FDCAN_MODE_BUS_MONITORING       ((uint32_t)0x00000002U) /*!< Bus Monitoring mode       */

+#define FDCAN_MODE_INTERNAL_LOOPBACK    ((uint32_t)0x00000003U) /*!< Internal LoopBack mode    */

+#define FDCAN_MODE_EXTERNAL_LOOPBACK    ((uint32_t)0x00000004U) /*!< External LoopBack mode    */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_clock_calibration FDCAN Clock Calibration

+  * @{

+  */

+#define FDCAN_CLOCK_CALIBRATION_DISABLE ((uint32_t)0x00000000U) /*!< Disable Clock Calibration */

+#define FDCAN_CLOCK_CALIBRATION_ENABLE  ((uint32_t)0x00000001U) /*!< Enable Clock Calibration  */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_clock_divider FDCAN Clock Divider

+  * @{

+  */

+#define FDCAN_CLOCK_DIV1  ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1  */

+#define FDCAN_CLOCK_DIV2  ((uint32_t)0x00010000U) /*!< Divide kernel clock by 2  */

+#define FDCAN_CLOCK_DIV4  ((uint32_t)0x00020000U) /*!< Divide kernel clock by 4  */

+#define FDCAN_CLOCK_DIV6  ((uint32_t)0x00030000U) /*!< Divide kernel clock by 6  */

+#define FDCAN_CLOCK_DIV8  ((uint32_t)0x00040000U) /*!< Divide kernel clock by 8  */

+#define FDCAN_CLOCK_DIV10 ((uint32_t)0x00050000U) /*!< Divide kernel clock by 10 */

+#define FDCAN_CLOCK_DIV12 ((uint32_t)0x00060000U) /*!< Divide kernel clock by 12 */

+#define FDCAN_CLOCK_DIV14 ((uint32_t)0x00070000U) /*!< Divide kernel clock by 14 */

+#define FDCAN_CLOCK_DIV16 ((uint32_t)0x00080000U) /*!< Divide kernel clock by 16 */

+#define FDCAN_CLOCK_DIV18 ((uint32_t)0x00090000U) /*!< Divide kernel clock by 18 */

+#define FDCAN_CLOCK_DIV20 ((uint32_t)0x000A0000U) /*!< Divide kernel clock by 20 */

+#define FDCAN_CLOCK_DIV22 ((uint32_t)0x000B0000U) /*!< Divide kernel clock by 22 */

+#define FDCAN_CLOCK_DIV24 ((uint32_t)0x000C0000U) /*!< Divide kernel clock by 24 */

+#define FDCAN_CLOCK_DIV26 ((uint32_t)0x000D0000U) /*!< Divide kernel clock by 26 */

+#define FDCAN_CLOCK_DIV28 ((uint32_t)0x000E0000U) /*!< Divide kernel clock by 28 */

+#define FDCAN_CLOCK_DIV30 ((uint32_t)0x000F0000U) /*!< Divide kernel clock by 30 */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_calibration_field_length FDCAN Calibration Field Length

+  * @{

+  */

+#define FDCAN_CALIB_FIELD_LENGTH_32 ((uint32_t)0x00000000U)       /*!< Calibration field length is 32 bits */

+#define FDCAN_CALIB_FIELD_LENGTH_64 ((uint32_t)FDCANCCU_CCFG_CFL) /*!< Calibration field length is 64 bits */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_calibration_state FDCAN Calibration State

+  * @{

+  */

+#define FDCAN_CLOCK_NOT_CALIBRATED       ((uint32_t)0x00000000U) /*!< Clock not calibrated       */

+#define FDCAN_CLOCK_BASIC_CALIBRATED     ((uint32_t)0x40000000U) /*!< Clock basic calibrated     */

+#define FDCAN_CLOCK_PRECISION_CALIBRATED ((uint32_t)0x80000000U) /*!< Clock precision calibrated */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_calibration_counter FDCAN Calibration Counter

+  * @{

+  */

+#define FDCAN_CALIB_TIME_QUANTA_COUNTER  ((uint32_t)0x00000000U) /*!< Time Quanta Counter             */

+#define FDCAN_CALIB_CLOCK_PERIOD_COUNTER ((uint32_t)0x00000001U) /*!< Oscillator Clock Period Counter */

+#define FDCAN_CALIB_WATCHDOG_COUNTER     ((uint32_t)0x00000002U) /*!< Calibration Watchdog Counter    */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_data_field_size FDCAN Data Field Size

+  * @{

+  */

+#define FDCAN_DATA_BYTES_8  ((uint32_t)0x00000004U) /*!< 8 bytes data field  */

+#define FDCAN_DATA_BYTES_12 ((uint32_t)0x00000005U) /*!< 12 bytes data field */

+#define FDCAN_DATA_BYTES_16 ((uint32_t)0x00000006U) /*!< 16 bytes data field */

+#define FDCAN_DATA_BYTES_20 ((uint32_t)0x00000007U) /*!< 20 bytes data field */

+#define FDCAN_DATA_BYTES_24 ((uint32_t)0x00000008U) /*!< 24 bytes data field */

+#define FDCAN_DATA_BYTES_32 ((uint32_t)0x0000000AU) /*!< 32 bytes data field */

+#define FDCAN_DATA_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */

+#define FDCAN_DATA_BYTES_64 ((uint32_t)0x00000012U) /*!< 64 bytes data field */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_txFifoQueue_Mode FDCAN Tx FIFO/Queue Mode

+  * @{

+  */

+#define FDCAN_TX_FIFO_OPERATION  ((uint32_t)0x00000000U)     /*!< FIFO mode  */

+#define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_id_type FDCAN ID Type

+  * @{

+  */

+#define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */

+#define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Extended ID element */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_frame_type FDCAN Frame Type

+  * @{

+  */

+#define FDCAN_DATA_FRAME   ((uint32_t)0x00000000U)  /*!< Data frame   */

+#define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U)  /*!< Remote frame */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_data_length_code FDCAN Data Length Code

+  * @{

+  */

+#define FDCAN_DLC_BYTES_0  ((uint32_t)0x00000000U) /*!< 0 bytes data field  */

+#define FDCAN_DLC_BYTES_1  ((uint32_t)0x00010000U) /*!< 1 bytes data field  */

+#define FDCAN_DLC_BYTES_2  ((uint32_t)0x00020000U) /*!< 2 bytes data field  */

+#define FDCAN_DLC_BYTES_3  ((uint32_t)0x00030000U) /*!< 3 bytes data field  */

+#define FDCAN_DLC_BYTES_4  ((uint32_t)0x00040000U) /*!< 4 bytes data field  */

+#define FDCAN_DLC_BYTES_5  ((uint32_t)0x00050000U) /*!< 5 bytes data field  */

+#define FDCAN_DLC_BYTES_6  ((uint32_t)0x00060000U) /*!< 6 bytes data field  */

+#define FDCAN_DLC_BYTES_7  ((uint32_t)0x00070000U) /*!< 7 bytes data field  */

+#define FDCAN_DLC_BYTES_8  ((uint32_t)0x00080000U) /*!< 8 bytes data field  */

+#define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */

+#define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */

+#define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */

+#define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */

+#define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */

+#define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */

+#define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator

+  * @{

+  */

+#define FDCAN_ESI_ACTIVE  ((uint32_t)0x00000000U) /*!< Transmitting node is error active  */

+#define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_bit_rate_switching FDCAN Bit Rate Switching

+  * @{

+  */

+#define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit rate switching */

+#define FDCAN_BRS_ON  ((uint32_t)0x00100000U) /*!< FDCAN frames transmitted/received with bit rate switching    */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_format FDCAN format

+  * @{

+  */

+#define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN format */

+#define FDCAN_FD_CAN      ((uint32_t)0x00200000U) /*!< Frame transmitted/received in FDCAN format       */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_EFC FDCAN Event FIFO control

+  * @{

+  */

+#define FDCAN_NO_TX_EVENTS    ((uint32_t)0x00000000U) /*!< Do not store Tx events */

+#define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U) /*!< Store Tx events        */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_filter_type FDCAN Filter Type

+  * @{

+  */

+#define FDCAN_FILTER_RANGE         ((uint32_t)0x00000000U) /*!< Range filter from FilterID1 to FilterID2                        */

+#define FDCAN_FILTER_DUAL          ((uint32_t)0x00000001U) /*!< Dual ID filter for FilterID1 or FilterID2                       */

+#define FDCAN_FILTER_MASK          ((uint32_t)0x00000002U) /*!< Classic filter: FilterID1 = filter, FilterID2 = mask            */

+#define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U) /*!< Range filter from FilterID1 to FilterID2, EIDM mask not applied */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_filter_config FDCAN Filter Configuration

+  * @{

+  */

+#define FDCAN_FILTER_DISABLE       ((uint32_t)0x00000000U) /*!< Disable filter element                                    */

+#define FDCAN_FILTER_TO_RXFIFO0    ((uint32_t)0x00000001U) /*!< Store in Rx FIFO 0 if filter matches                      */

+#define FDCAN_FILTER_TO_RXFIFO1    ((uint32_t)0x00000002U) /*!< Store in Rx FIFO 1 if filter matches                      */

+#define FDCAN_FILTER_REJECT        ((uint32_t)0x00000003U) /*!< Reject ID if filter matches                               */

+#define FDCAN_FILTER_HP            ((uint32_t)0x00000004U) /*!< Set high priority if filter matches                       */

+#define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U) /*!< Set high priority and store in FIFO 0 if filter matches   */

+#define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U) /*!< Set high priority and store in FIFO 1 if filter matches   */

+#define FDCAN_FILTER_TO_RXBUFFER   ((uint32_t)0x00000007U) /*!< Store into Rx Buffer, configuration of FilterType ignored */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_Tx_location FDCAN Tx Location

+  * @{

+  */

+#define FDCAN_TX_BUFFER0  ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0  */

+#define FDCAN_TX_BUFFER1  ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1  */

+#define FDCAN_TX_BUFFER2  ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2  */

+#define FDCAN_TX_BUFFER3  ((uint32_t)0x00000008U) /*!< Add message to Tx Buffer 3  */

+#define FDCAN_TX_BUFFER4  ((uint32_t)0x00000010U) /*!< Add message to Tx Buffer 4  */

+#define FDCAN_TX_BUFFER5  ((uint32_t)0x00000020U) /*!< Add message to Tx Buffer 5  */

+#define FDCAN_TX_BUFFER6  ((uint32_t)0x00000040U) /*!< Add message to Tx Buffer 6  */

+#define FDCAN_TX_BUFFER7  ((uint32_t)0x00000080U) /*!< Add message to Tx Buffer 7  */

+#define FDCAN_TX_BUFFER8  ((uint32_t)0x00000100U) /*!< Add message to Tx Buffer 8  */

+#define FDCAN_TX_BUFFER9  ((uint32_t)0x00000200U) /*!< Add message to Tx Buffer 9  */

+#define FDCAN_TX_BUFFER10 ((uint32_t)0x00000400U) /*!< Add message to Tx Buffer 10 */

+#define FDCAN_TX_BUFFER11 ((uint32_t)0x00000800U) /*!< Add message to Tx Buffer 11 */

+#define FDCAN_TX_BUFFER12 ((uint32_t)0x00001000U) /*!< Add message to Tx Buffer 12 */

+#define FDCAN_TX_BUFFER13 ((uint32_t)0x00002000U) /*!< Add message to Tx Buffer 13 */

+#define FDCAN_TX_BUFFER14 ((uint32_t)0x00004000U) /*!< Add message to Tx Buffer 14 */

+#define FDCAN_TX_BUFFER15 ((uint32_t)0x00008000U) /*!< Add message to Tx Buffer 15 */

+#define FDCAN_TX_BUFFER16 ((uint32_t)0x00010000U) /*!< Add message to Tx Buffer 16 */

+#define FDCAN_TX_BUFFER17 ((uint32_t)0x00020000U) /*!< Add message to Tx Buffer 17 */

+#define FDCAN_TX_BUFFER18 ((uint32_t)0x00040000U) /*!< Add message to Tx Buffer 18 */

+#define FDCAN_TX_BUFFER19 ((uint32_t)0x00080000U) /*!< Add message to Tx Buffer 19 */

+#define FDCAN_TX_BUFFER20 ((uint32_t)0x00100000U) /*!< Add message to Tx Buffer 20 */

+#define FDCAN_TX_BUFFER21 ((uint32_t)0x00200000U) /*!< Add message to Tx Buffer 21 */

+#define FDCAN_TX_BUFFER22 ((uint32_t)0x00400000U) /*!< Add message to Tx Buffer 22 */

+#define FDCAN_TX_BUFFER23 ((uint32_t)0x00800000U) /*!< Add message to Tx Buffer 23 */

+#define FDCAN_TX_BUFFER24 ((uint32_t)0x01000000U) /*!< Add message to Tx Buffer 24 */

+#define FDCAN_TX_BUFFER25 ((uint32_t)0x02000000U) /*!< Add message to Tx Buffer 25 */

+#define FDCAN_TX_BUFFER26 ((uint32_t)0x04000000U) /*!< Add message to Tx Buffer 26 */

+#define FDCAN_TX_BUFFER27 ((uint32_t)0x08000000U) /*!< Add message to Tx Buffer 27 */

+#define FDCAN_TX_BUFFER28 ((uint32_t)0x10000000U) /*!< Add message to Tx Buffer 28 */

+#define FDCAN_TX_BUFFER29 ((uint32_t)0x20000000U) /*!< Add message to Tx Buffer 29 */

+#define FDCAN_TX_BUFFER30 ((uint32_t)0x40000000U) /*!< Add message to Tx Buffer 30 */

+#define FDCAN_TX_BUFFER31 ((uint32_t)0x80000000U) /*!< Add message to Tx Buffer 31 */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_Rx_location FDCAN Rx Location

+  * @{

+  */

+#define FDCAN_RX_FIFO0    ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0    */

+#define FDCAN_RX_FIFO1    ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1    */

+#define FDCAN_RX_BUFFER0  ((uint32_t)0x00000000U) /*!< Get received message from Rx Buffer 0  */

+#define FDCAN_RX_BUFFER1  ((uint32_t)0x00000001U) /*!< Get received message from Rx Buffer 1  */

+#define FDCAN_RX_BUFFER2  ((uint32_t)0x00000002U) /*!< Get received message from Rx Buffer 2  */

+#define FDCAN_RX_BUFFER3  ((uint32_t)0x00000003U) /*!< Get received message from Rx Buffer 3  */

+#define FDCAN_RX_BUFFER4  ((uint32_t)0x00000004U) /*!< Get received message from Rx Buffer 4  */

+#define FDCAN_RX_BUFFER5  ((uint32_t)0x00000005U) /*!< Get received message from Rx Buffer 5  */

+#define FDCAN_RX_BUFFER6  ((uint32_t)0x00000006U) /*!< Get received message from Rx Buffer 6  */

+#define FDCAN_RX_BUFFER7  ((uint32_t)0x00000007U) /*!< Get received message from Rx Buffer 7  */

+#define FDCAN_RX_BUFFER8  ((uint32_t)0x00000008U) /*!< Get received message from Rx Buffer 8  */

+#define FDCAN_RX_BUFFER9  ((uint32_t)0x00000009U) /*!< Get received message from Rx Buffer 9  */

+#define FDCAN_RX_BUFFER10 ((uint32_t)0x0000000AU) /*!< Get received message from Rx Buffer 10 */

+#define FDCAN_RX_BUFFER11 ((uint32_t)0x0000000BU) /*!< Get received message from Rx Buffer 11 */

+#define FDCAN_RX_BUFFER12 ((uint32_t)0x0000000CU) /*!< Get received message from Rx Buffer 12 */

+#define FDCAN_RX_BUFFER13 ((uint32_t)0x0000000DU) /*!< Get received message from Rx Buffer 13 */

+#define FDCAN_RX_BUFFER14 ((uint32_t)0x0000000EU) /*!< Get received message from Rx Buffer 14 */

+#define FDCAN_RX_BUFFER15 ((uint32_t)0x0000000FU) /*!< Get received message from Rx Buffer 15 */

+#define FDCAN_RX_BUFFER16 ((uint32_t)0x00000010U) /*!< Get received message from Rx Buffer 16 */

+#define FDCAN_RX_BUFFER17 ((uint32_t)0x00000011U) /*!< Get received message from Rx Buffer 17 */

+#define FDCAN_RX_BUFFER18 ((uint32_t)0x00000012U) /*!< Get received message from Rx Buffer 18 */

+#define FDCAN_RX_BUFFER19 ((uint32_t)0x00000013U) /*!< Get received message from Rx Buffer 19 */

+#define FDCAN_RX_BUFFER20 ((uint32_t)0x00000014U) /*!< Get received message from Rx Buffer 20 */

+#define FDCAN_RX_BUFFER21 ((uint32_t)0x00000015U) /*!< Get received message from Rx Buffer 21 */

+#define FDCAN_RX_BUFFER22 ((uint32_t)0x00000016U) /*!< Get received message from Rx Buffer 22 */

+#define FDCAN_RX_BUFFER23 ((uint32_t)0x00000017U) /*!< Get received message from Rx Buffer 23 */

+#define FDCAN_RX_BUFFER24 ((uint32_t)0x00000018U) /*!< Get received message from Rx Buffer 24 */

+#define FDCAN_RX_BUFFER25 ((uint32_t)0x00000019U) /*!< Get received message from Rx Buffer 25 */

+#define FDCAN_RX_BUFFER26 ((uint32_t)0x0000001AU) /*!< Get received message from Rx Buffer 26 */

+#define FDCAN_RX_BUFFER27 ((uint32_t)0x0000001BU) /*!< Get received message from Rx Buffer 27 */

+#define FDCAN_RX_BUFFER28 ((uint32_t)0x0000001CU) /*!< Get received message from Rx Buffer 28 */

+#define FDCAN_RX_BUFFER29 ((uint32_t)0x0000001DU) /*!< Get received message from Rx Buffer 29 */

+#define FDCAN_RX_BUFFER30 ((uint32_t)0x0000001EU) /*!< Get received message from Rx Buffer 30 */

+#define FDCAN_RX_BUFFER31 ((uint32_t)0x0000001FU) /*!< Get received message from Rx Buffer 31 */

+#define FDCAN_RX_BUFFER32 ((uint32_t)0x00000020U) /*!< Get received message from Rx Buffer 32 */

+#define FDCAN_RX_BUFFER33 ((uint32_t)0x00000021U) /*!< Get received message from Rx Buffer 33 */

+#define FDCAN_RX_BUFFER34 ((uint32_t)0x00000022U) /*!< Get received message from Rx Buffer 34 */

+#define FDCAN_RX_BUFFER35 ((uint32_t)0x00000023U) /*!< Get received message from Rx Buffer 35 */

+#define FDCAN_RX_BUFFER36 ((uint32_t)0x00000024U) /*!< Get received message from Rx Buffer 36 */

+#define FDCAN_RX_BUFFER37 ((uint32_t)0x00000025U) /*!< Get received message from Rx Buffer 37 */

+#define FDCAN_RX_BUFFER38 ((uint32_t)0x00000026U) /*!< Get received message from Rx Buffer 38 */

+#define FDCAN_RX_BUFFER39 ((uint32_t)0x00000027U) /*!< Get received message from Rx Buffer 39 */

+#define FDCAN_RX_BUFFER40 ((uint32_t)0x00000028U) /*!< Get received message from Rx Buffer 40 */

+#define FDCAN_RX_BUFFER41 ((uint32_t)0x00000029U) /*!< Get received message from Rx Buffer 41 */

+#define FDCAN_RX_BUFFER42 ((uint32_t)0x0000002AU) /*!< Get received message from Rx Buffer 42 */

+#define FDCAN_RX_BUFFER43 ((uint32_t)0x0000002BU) /*!< Get received message from Rx Buffer 43 */

+#define FDCAN_RX_BUFFER44 ((uint32_t)0x0000002CU) /*!< Get received message from Rx Buffer 44 */

+#define FDCAN_RX_BUFFER45 ((uint32_t)0x0000002DU) /*!< Get received message from Rx Buffer 45 */

+#define FDCAN_RX_BUFFER46 ((uint32_t)0x0000002EU) /*!< Get received message from Rx Buffer 46 */

+#define FDCAN_RX_BUFFER47 ((uint32_t)0x0000002FU) /*!< Get received message from Rx Buffer 47 */

+#define FDCAN_RX_BUFFER48 ((uint32_t)0x00000030U) /*!< Get received message from Rx Buffer 48 */

+#define FDCAN_RX_BUFFER49 ((uint32_t)0x00000031U) /*!< Get received message from Rx Buffer 49 */

+#define FDCAN_RX_BUFFER50 ((uint32_t)0x00000032U) /*!< Get received message from Rx Buffer 50 */

+#define FDCAN_RX_BUFFER51 ((uint32_t)0x00000033U) /*!< Get received message from Rx Buffer 51 */

+#define FDCAN_RX_BUFFER52 ((uint32_t)0x00000034U) /*!< Get received message from Rx Buffer 52 */

+#define FDCAN_RX_BUFFER53 ((uint32_t)0x00000035U) /*!< Get received message from Rx Buffer 53 */

+#define FDCAN_RX_BUFFER54 ((uint32_t)0x00000036U) /*!< Get received message from Rx Buffer 54 */

+#define FDCAN_RX_BUFFER55 ((uint32_t)0x00000037U) /*!< Get received message from Rx Buffer 55 */

+#define FDCAN_RX_BUFFER56 ((uint32_t)0x00000038U) /*!< Get received message from Rx Buffer 56 */

+#define FDCAN_RX_BUFFER57 ((uint32_t)0x00000039U) /*!< Get received message from Rx Buffer 57 */

+#define FDCAN_RX_BUFFER58 ((uint32_t)0x0000003AU) /*!< Get received message from Rx Buffer 58 */

+#define FDCAN_RX_BUFFER59 ((uint32_t)0x0000003BU) /*!< Get received message from Rx Buffer 59 */

+#define FDCAN_RX_BUFFER60 ((uint32_t)0x0000003CU) /*!< Get received message from Rx Buffer 60 */

+#define FDCAN_RX_BUFFER61 ((uint32_t)0x0000003DU) /*!< Get received message from Rx Buffer 61 */

+#define FDCAN_RX_BUFFER62 ((uint32_t)0x0000003EU) /*!< Get received message from Rx Buffer 62 */

+#define FDCAN_RX_BUFFER63 ((uint32_t)0x0000003FU) /*!< Get received message from Rx Buffer 63 */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_event_type FDCAN Event Type

+  * @{

+  */

+#define FDCAN_TX_EVENT             ((uint32_t)0x00400000U) /*!< Tx event                              */

+#define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U) /*!< Transmission in spite of cancellation */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_hp_msg_storage FDCAN High Priority Message Storage

+  * @{

+  */

+#define FDCAN_HP_STORAGE_NO_FIFO  ((uint32_t)0x00000000U) /*!< No FIFO selected         */

+#define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U) /*!< FIFO message lost        */

+#define FDCAN_HP_STORAGE_RXFIFO0  ((uint32_t)0x00000080U) /*!< Message stored in FIFO 0 */

+#define FDCAN_HP_STORAGE_RXFIFO1  ((uint32_t)0x000000C0U) /*!< Message stored in FIFO 1 */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_protocol_error_code FDCAN protocol error code

+  * @{

+  */

+#define FDCAN_PROTOCOL_ERROR_NONE      ((uint32_t)0x00000000U) /*!< No error occurred         */

+#define FDCAN_PROTOCOL_ERROR_STUFF     ((uint32_t)0x00000001U) /*!< Stuff error               */

+#define FDCAN_PROTOCOL_ERROR_FORM      ((uint32_t)0x00000002U) /*!< Form error                */

+#define FDCAN_PROTOCOL_ERROR_ACK       ((uint32_t)0x00000003U) /*!< Acknowledge error         */

+#define FDCAN_PROTOCOL_ERROR_BIT1      ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error   */

+#define FDCAN_PROTOCOL_ERROR_BIT0      ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error    */

+#define FDCAN_PROTOCOL_ERROR_CRC       ((uint32_t)0x00000006U) /*!< CRC check sum error       */

+#define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U) /*!< No change since last read */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_communication_state FDCAN communication state

+  * @{

+  */

+#define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */

+#define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U) /*!< Node is neither receiver nor transmitter   */

+#define FDCAN_COM_STATE_RX   ((uint32_t)0x00000010U) /*!< Node is operating as receiver              */

+#define FDCAN_COM_STATE_TX   ((uint32_t)0x00000018U) /*!< Node is operating as transmitter           */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_FIFO_watermark FDCAN FIFO watermark

+  * @{

+  */

+#define FDCAN_CFG_TX_EVENT_FIFO ((uint32_t)0x00000000U) /*!< Tx event FIFO */

+#define FDCAN_CFG_RX_FIFO0      ((uint32_t)0x00000001U) /*!< Rx FIFO0      */

+#define FDCAN_CFG_RX_FIFO1      ((uint32_t)0x00000002U) /*!< Rx FIFO1      */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode

+  * @{

+  */

+#define FDCAN_RX_FIFO_BLOCKING  ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode  */

+#define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x80000000U) /*!< Rx FIFO overwrite mode */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_Non_Matching_Frames FDCAN non-matching frames

+  * @{

+  */

+#define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U) /*!< Accept in Rx FIFO 0 */

+#define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U) /*!< Accept in Rx FIFO 1 */

+#define FDCAN_REJECT             ((uint32_t)0x00000002U) /*!< Reject              */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_Reject_Remote_Frames FDCAN reject remote frames

+  * @{

+  */

+#define FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U) /*!< Filter remote frames */

+#define FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U) /*!< Reject all remote frames */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_Interrupt_Line FDCAN interrupt line

+  * @{

+  */

+#define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U) /*!< Interrupt Line 0 */

+#define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U) /*!< Interrupt Line 1 */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_Timestamp FDCAN timestamp

+  * @{

+  */

+#define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U) /*!< Timestamp counter value incremented according to TCP */

+#define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U) /*!< External timestamp counter value used                */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_Timestamp_Prescaler FDCAN timestamp prescaler

+  * @{

+  */

+#define FDCAN_TIMESTAMP_PRESC_1  ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time                 */

+#define FDCAN_TIMESTAMP_PRESC_2  ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 2  */

+#define FDCAN_TIMESTAMP_PRESC_3  ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 3  */

+#define FDCAN_TIMESTAMP_PRESC_4  ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 4  */

+#define FDCAN_TIMESTAMP_PRESC_5  ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 5  */

+#define FDCAN_TIMESTAMP_PRESC_6  ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 6  */

+#define FDCAN_TIMESTAMP_PRESC_7  ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 7  */

+#define FDCAN_TIMESTAMP_PRESC_8  ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 8  */

+#define FDCAN_TIMESTAMP_PRESC_9  ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 9  */

+#define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 10 */

+#define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 11 */

+#define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 12 */

+#define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 13 */

+#define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 14 */

+#define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 15 */

+#define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 16 */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_Timeout_Operation FDCAN timeout operation

+  * @{

+  */

+#define FDCAN_TIMEOUT_CONTINUOUS    ((uint32_t)0x00000000U) /*!< Timeout continuous operation        */

+#define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U) /*!< Timeout controlled by Tx Event FIFO */

+#define FDCAN_TIMEOUT_RX_FIFO0      ((uint32_t)0x00000004U) /*!< Timeout controlled by Rx FIFO 0     */

+#define FDCAN_TIMEOUT_RX_FIFO1      ((uint32_t)0x00000006U) /*!< Timeout controlled by Rx FIFO 1     */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_TT_Reference_Message_Payload FDCAN TT reference message payload

+  * @{

+  */

+#define FDCAN_TT_REF_MESSAGE_NO_PAYLOAD  ((uint32_t)0x00000000U)      /*!< Reference message has no additional payload  */

+#define FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD ((uint32_t)FDCAN_TTRMC_RMPS) /*!< Additional payload is taken from Tx Buffer 0 */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_TT_Repeat_Factor FDCAN TT repeat factor

+  * @{

+  */

+#define FDCAN_TT_REPEAT_EVERY_CYCLE      ((uint32_t)0x00000000U) /*!< Trigger valid for all cycles   */

+#define FDCAN_TT_REPEAT_EVERY_2ND_CYCLE  ((uint32_t)0x00000002U) /*!< Trigger valid every 2dn cycle  */

+#define FDCAN_TT_REPEAT_EVERY_4TH_CYCLE  ((uint32_t)0x00000004U) /*!< Trigger valid every 4th cycle  */

+#define FDCAN_TT_REPEAT_EVERY_8TH_CYCLE  ((uint32_t)0x00000008U) /*!< Trigger valid every 8th cycle  */

+#define FDCAN_TT_REPEAT_EVERY_16TH_CYCLE ((uint32_t)0x00000010U) /*!< Trigger valid every 16th cycle */

+#define FDCAN_TT_REPEAT_EVERY_32ND_CYCLE ((uint32_t)0x00000020U) /*!< Trigger valid every 32nd cycle */

+#define FDCAN_TT_REPEAT_EVERY_64TH_CYCLE ((uint32_t)0x00000040U) /*!< Trigger valid every 64th cycle */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_TT_Trigger_Type FDCAN TT trigger type

+  * @{

+  */

+#define FDCAN_TT_TX_REF_TRIGGER         ((uint32_t)0x00000000U) /*!< Transmit reference message in strictly time-triggered operation                                                     */

+#define FDCAN_TT_TX_REF_TRIGGER_GAP     ((uint32_t)0x00000001U) /*!< Transmit reference message in external event-synchronized time-triggered operation                                  */

+#define FDCAN_TT_TX_TRIGGER_SINGLE      ((uint32_t)0x00000002U) /*!< Start a single transmission in an exclusive time window                                                             */

+#define FDCAN_TT_TX_TRIGGER_CONTINUOUS  ((uint32_t)0x00000003U) /*!< Start a continuous transmission in an exclusive time window                                                         */

+#define FDCAN_TT_TX_TRIGGER_ARBITRATION ((uint32_t)0x00000004U) /*!< Start a transmission in an arbitration time window                                                                  */

+#define FDCAN_TT_TX_TRIGGER_MERGED      ((uint32_t)0x00000005U) /*!< Start a merged arbitration window                                                                                   */

+#define FDCAN_TT_WATCH_TRIGGER          ((uint32_t)0x00000006U) /*!< Check for missing reference messages in strictly time-triggered operation                                           */

+#define FDCAN_TT_WATCH_TRIGGER_GAP      ((uint32_t)0x00000007U) /*!< Check for missing reference messages in external event-synchronized time-triggered operation                        */

+#define FDCAN_TT_RX_TRIGGER             ((uint32_t)0x00000008U) /*!< Check for the reception of periodic messages in exclusive time windows                                              */

+#define FDCAN_TT_TIME_BASE_TRIGGER      ((uint32_t)0x00000009U) /*!< Generate internal/external events depending on TmEventInt/TmEventExt configuration                                  */

+#define FDCAN_TT_END_OF_LIST            ((uint32_t)0x0000000AU) /*!< Illegal trigger, to be assigned to the unused triggers after a FDCAN_TT_WATCH_TRIGGER or FDCAN_TT_WATCH_TRIGGER_GAP */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_TT_Time_Mark_Event_Internal FDCAN TT time mark event internal

+  * @{

+  */

+#define FDCAN_TT_TM_NO_INTERNAL_EVENT  ((uint32_t)0x00000000U) /*!< No action                                               */

+#define FDCAN_TT_TM_GEN_INTERNAL_EVENT ((uint32_t)0x00000020U) /*!< Internal event is generated when trigger becomes active */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_TT_Time_Mark_Event_External FDCAN TT time mark event external

+  * @{

+  */

+#define FDCAN_TT_TM_NO_EXTERNAL_EVENT  ((uint32_t)0x00000000U) /*!< No action                                                       */

+#define FDCAN_TT_TM_GEN_EXTERNAL_EVENT ((uint32_t)0x00000010U) /*!< External event (pulse) is generated when trigger becomes active */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_operation_mode FDCAN Operation Mode

+  * @{

+  */

+#define FDCAN_TT_COMMUNICATION_LEVEL1    ((uint32_t)0x00000001U) /*!< Time triggered communication, level 1 */

+#define FDCAN_TT_COMMUNICATION_LEVEL2    ((uint32_t)0x00000002U) /*!< Time triggered communication, level 2 */

+#define FDCAN_TT_COMMUNICATION_LEVEL0    ((uint32_t)0x00000003U) /*!< Time triggered communication, level 0 */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_TT_operation FDCAN TT Operation

+  * @{

+  */

+#define FDCAN_STRICTLY_TT_OPERATION     ((uint32_t)0x00000000U)     /*!< Strictly time-triggered operation                    */

+#define FDCAN_EXT_EVT_SYNC_TT_OPERATION ((uint32_t)FDCAN_TTOCF_GEN) /*!< External event-synchronized time-triggered operation */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_TT_time_master FDCAN TT Time Master

+  * @{

+  */

+#define FDCAN_TT_SLAVE            ((uint32_t)0x00000000U)    /*!< Time slave            */

+#define FDCAN_TT_POTENTIAL_MASTER ((uint32_t)FDCAN_TTOCF_TM) /*!< Potential time master */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_TT_external_clk_sync FDCAN TT External Clock Synchronization

+  * @{

+  */

+#define FDCAN_TT_EXT_CLK_SYNC_DISABLE ((uint32_t)0x00000000U)      /*!< External clock synchronization in Level 0,2 disabled */

+#define FDCAN_TT_EXT_CLK_SYNC_ENABLE  ((uint32_t)FDCAN_TTOCF_EECS) /*!< External clock synchronization in Level 0,2 enabled  */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_TT_global_time_filtering FDCAN TT Global Time Filtering

+  * @{

+  */

+#define FDCAN_TT_GLOB_TIME_FILT_DISABLE ((uint32_t)0x00000000U)      /*!< Global time filtering in Level 0,2 disabled */

+#define FDCAN_TT_GLOB_TIME_FILT_ENABLE  ((uint32_t)FDCAN_TTOCF_EGTF) /*!< Global time filtering in Level 0,2 enabled  */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_TT_auto_clk_calibration FDCAN TT Automatic Clock Calibration

+  * @{

+  */

+#define FDCAN_TT_AUTO_CLK_CALIB_DISABLE ((uint32_t)0x00000000U)     /*!< Automatic clock calibration in Level 0,2 disabled */

+#define FDCAN_TT_AUTO_CLK_CALIB_ENABLE  ((uint32_t)FDCAN_TTOCF_ECC) /*!< Automatic clock calibration in Level 0,2 enabled  */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_TT_event_trig_polarity FDCAN TT Event Trigger Polarity

+  * @{

+  */

+#define FDCAN_TT_EVT_TRIG_POL_RISING  ((uint32_t)0x00000000U)      /*!< Rising edge trigger  */

+#define FDCAN_TT_EVT_TRIG_POL_FALLING ((uint32_t)FDCAN_TTOCF_EVTP) /*!< Falling edge trigger */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_TT_basic_cycle_number FDCAN TT Basic Cycle Number

+  * @{

+  */

+#define FDCAN_TT_CYCLES_PER_MATRIX_1  ((uint32_t)0x00000000U) /*!< 1 Basic Cycle per Matrix   */

+#define FDCAN_TT_CYCLES_PER_MATRIX_2  ((uint32_t)0x00000001U) /*!< 2 Basic Cycles per Matrix  */

+#define FDCAN_TT_CYCLES_PER_MATRIX_4  ((uint32_t)0x00000003U) /*!< 4 Basic Cycles per Matrix  */

+#define FDCAN_TT_CYCLES_PER_MATRIX_8  ((uint32_t)0x00000007U) /*!< 8 Basic Cycles per Matrix  */

+#define FDCAN_TT_CYCLES_PER_MATRIX_16 ((uint32_t)0x0000000FU) /*!< 16 Basic Cycles per Matrix */

+#define FDCAN_TT_CYCLES_PER_MATRIX_32 ((uint32_t)0x0000001FU) /*!< 32 Basic Cycles per Matrix */

+#define FDCAN_TT_CYCLES_PER_MATRIX_64 ((uint32_t)0x0000003FU) /*!< 64 Basic Cycles per Matrix */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_TT_cycle_start_sync FDCAN TT Cycle Start Sync

+  * @{

+  */

+#define FDCAN_TT_NO_SYNC_PULSE          ((uint32_t)0x00000000U) /*!< No sync pulse                      */

+#define FDCAN_TT_SYNC_BASIC_CYCLE_START ((uint32_t)0x00000040U) /*!< Sync pulse at start of basic cycle */

+#define FDCAN_TT_SYNC_MATRIX_START      ((uint32_t)0x00000080U) /*!< Sync pulse at start of matrix      */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_TT_stop_watch_trig_selection FDCAN TT Stop Watch Trigger Selection

+  * @{

+  */

+#define FDCAN_TT_STOP_WATCH_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as stop watch trigger  */

+#define FDCAN_TT_STOP_WATCH_TRIGGER_1 ((uint32_t)0x00000001U) /*!< TIM3 selected as stop watch trigger  */

+#define FDCAN_TT_STOP_WATCH_TRIGGER_2 ((uint32_t)0x00000002U) /*!< ETH selected as stop watch trigger   */

+#define FDCAN_TT_STOP_WATCH_TRIGGER_3 ((uint32_t)0x00000003U) /*!< HRTIM selected as stop watch trigger */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_TT_event_trig_selection FDCAN TT Event Trigger Selection

+  * @{

+  */

+#define FDCAN_TT_EVENT_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as event trigger  */

+#define FDCAN_TT_EVENT_TRIGGER_1 ((uint32_t)0x00000010U) /*!< TIM3 selected as event trigger  */

+#define FDCAN_TT_EVENT_TRIGGER_2 ((uint32_t)0x00000020U) /*!< ETH selected as event trigger   */

+#define FDCAN_TT_EVENT_TRIGGER_3 ((uint32_t)0x00000030U) /*!< HRTIM selected as event trigger */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_TT_stop_watch_source FDCAN TT Stop Watch Source

+  * @{

+  */

+#define FDCAN_TT_STOP_WATCH_DISABLED    ((uint32_t)0x00000000U) /*!< Stop Watch disabled                                                        */

+#define FDCAN_TT_STOP_WATCH_CYCLE_TIME  ((uint32_t)0x00000008U) /*!< Actual value of cycle time is copied to Capture Time register (TTCPT.SWV)  */

+#define FDCAN_TT_STOP_WATCH_LOCAL_TIME  ((uint32_t)0x00000010U) /*!< Actual value of local time is copied to Capture Time register (TTCPT.SWV)  */

+#define FDCAN_TT_STOP_WATCH_GLOBAL_TIME ((uint32_t)0x00000018U) /*!< Actual value of global time is copied to Capture Time register (TTCPT.SWV) */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_TT_stop_watch_polarity FDCAN TT Stop Watch Polarity

+  * @{

+  */

+#define FDCAN_TT_STOP_WATCH_RISING  ((uint32_t)0x00000000U) /*!< Selected stop watch source is captured at rising edge of fdcan1_swt  */

+#define FDCAN_TT_STOP_WATCH_FALLING ((uint32_t)0x00000004U) /*!< Selected stop watch source is captured at falling edge of fdcan1_swt */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_TT_time_mark_source FDCAN TT Time Mark Source

+  * @{

+  */

+#define FDCAN_TT_REG_TIMEMARK_DIABLED  ((uint32_t)0x00000000U) /*!< No Register Time Mark Interrupt generated               */

+#define FDCAN_TT_REG_TIMEMARK_CYC_TIME ((uint32_t)0x00000040U) /*!< Register Time Mark Interrupt if Time Mark = cycle time  */

+#define FDCAN_TT_REG_TIMEMARK_LOC_TIME ((uint32_t)0x00000080U) /*!< Register Time Mark Interrupt if Time Mark = local time  */

+#define FDCAN_TT_REG_TIMEMARK_GLO_TIME ((uint32_t)0x000000C0U) /*!< Register Time Mark Interrupt if Time Mark = global time */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_TT_error_level FDCAN TT Error Level

+  * @{

+  */

+#define FDCAN_TT_NO_ERROR     ((uint32_t)0x00000000U) /*!< Severity 0 - No Error     */

+#define FDCAN_TT_WARNING      ((uint32_t)0x00000001U) /*!< Severity 1 - Warning      */

+#define FDCAN_TT_ERROR        ((uint32_t)0x00000002U) /*!< Severity 2 - Error        */

+#define FDCAN_TT_SEVERE_ERROR ((uint32_t)0x00000003U) /*!< Severity 3 - Severe Error */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_TT_master_state FDCAN TT Master State

+  * @{

+  */

+#define FDCAN_TT_MASTER_OFF          ((uint32_t)0x00000000U) /*!< Master_Off, no master properties relevant */

+#define FDCAN_TT_TIME_SLAVE          ((uint32_t)0x00000004U) /*!< Operating as Time Slave                   */

+#define FDCAN_TT_BACKUP_TIME_MASTER  ((uint32_t)0x00000008U) /*!< Operating as Backup Time Master           */

+#define FDCAN_TT_CURRENT_TIME_MASTER ((uint32_t)0x0000000CU) /*!< Operating as current Time Master          */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_TT_sync_state FDCAN TT Synchronization State

+  * @{

+  */

+#define FDCAN_TT_OUT_OF_SYNC   ((uint32_t)0x00000000U) /*!< Out of Synchronization         */

+#define FDCAN_TT_SYNCHRONIZING ((uint32_t)0x00000010U) /*!< Synchronizing to communication */

+#define FDCAN_TT_IN_GAP        ((uint32_t)0x00000020U) /*!< Schedule suspended by Gap      */

+#define FDCAN_TT_IN_SCHEDULE   ((uint32_t)0x00000030U) /*!< Synchronized to schedule       */

+/**

+  * @}

+  */

+

+/** @defgroup Interrupt_Masks Interrupt masks

+  * @{

+  */

+#define FDCAN_IR_MASK ((uint32_t)0x3FCFFFFFU) /*!< FDCAN interrupts mask */

+#define CCU_IR_MASK   ((uint32_t)0xC0000000U) /*!< CCU interrupts mask   */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_flags FDCAN Flags

+  * @{

+  */

+#define FDCAN_FLAG_TX_COMPLETE             FDCAN_IR_TC             /*!< Transmission Completed                                */

+#define FDCAN_FLAG_TX_ABORT_COMPLETE       FDCAN_IR_TCF            /*!< Transmission Cancellation Finished                    */

+#define FDCAN_FLAG_TX_FIFO_EMPTY           FDCAN_IR_TFE            /*!< Tx FIFO Empty                                         */

+#define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG    FDCAN_IR_HPM            /*!< High priority message received                        */

+#define FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE   FDCAN_IR_DRX            /*!< At least one received message stored into a Rx Buffer */

+#define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST    FDCAN_IR_TEFL           /*!< Tx Event FIFO element lost                            */

+#define FDCAN_FLAG_TX_EVT_FIFO_FULL        FDCAN_IR_TEFF           /*!< Tx Event FIFO full                                    */

+#define FDCAN_FLAG_TX_EVT_FIFO_WATERMARK   FDCAN_IR_TEFW           /*!< Tx Event FIFO fill level reached watermark            */

+#define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA    FDCAN_IR_TEFN           /*!< Tx Handler wrote Tx Event FIFO element                */

+#define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST   FDCAN_IR_RF0L           /*!< Rx FIFO 0 message lost                                */

+#define FDCAN_FLAG_RX_FIFO0_FULL           FDCAN_IR_RF0F           /*!< Rx FIFO 0 full                                        */

+#define FDCAN_FLAG_RX_FIFO0_WATERMARK      FDCAN_IR_RF0W           /*!< Rx FIFO 0 fill level reached watermark                */

+#define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE    FDCAN_IR_RF0N           /*!< New message written to Rx FIFO 0                      */

+#define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST   FDCAN_IR_RF1L           /*!< Rx FIFO 1 message lost                                */

+#define FDCAN_FLAG_RX_FIFO1_FULL           FDCAN_IR_RF1F           /*!< Rx FIFO 1 full                                        */

+#define FDCAN_FLAG_RX_FIFO1_WATERMARK      FDCAN_IR_RF1W           /*!< Rx FIFO 1 fill level reached watermark                */

+#define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE    FDCAN_IR_RF1N           /*!< New message written to Rx FIFO 1                      */

+#define FDCAN_FLAG_RAM_ACCESS_FAILURE      FDCAN_IR_MRAF           /*!< Message RAM access failure occurred                   */

+#define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW  FDCAN_IR_ELO            /*!< Overflow of FDCAN Error Logging Counter occurred      */

+#define FDCAN_FLAG_ERROR_PASSIVE           FDCAN_IR_EP             /*!< Error_Passive status changed                          */

+#define FDCAN_FLAG_ERROR_WARNING           FDCAN_IR_EW             /*!< Error_Warning status changed                          */

+#define FDCAN_FLAG_BUS_OFF                 FDCAN_IR_BO             /*!< Bus_Off status changed                                */

+#define FDCAN_FLAG_RAM_WATCHDOG            FDCAN_IR_WDI            /*!< Message RAM Watchdog event due to missing READY       */

+#define FDCAN_FLAG_ARB_PROTOCOL_ERROR      FDCAN_IR_PEA            /*!< Protocol error in arbitration phase detected          */

+#define FDCAN_FLAG_DATA_PROTOCOL_ERROR     FDCAN_IR_PED            /*!< Protocol error in data phase detected                 */

+#define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA            /*!< Access to reserved address occurred                   */

+#define FDCAN_FLAG_TIMESTAMP_WRAPAROUND    FDCAN_IR_TSW            /*!< Timestamp counter wrapped around                      */

+#define FDCAN_FLAG_TIMEOUT_OCCURRED        FDCAN_IR_TOO            /*!< Timeout reached                                       */

+#define FDCAN_FLAG_CALIB_STATE_CHANGED     (FDCANCCU_IR_CSC << 30) /*!< Clock calibration state changed                       */

+#define FDCAN_FLAG_CALIB_WATCHDOG_EVENT    (FDCANCCU_IR_CWE << 30) /*!< Clock calibration watchdog event occurred             */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_Interrupts FDCAN Interrupts

+  * @{

+  */

+

+/** @defgroup FDCAN_Tx_Interrupts FDCAN Tx Interrupts

+  * @{

+  */

+#define FDCAN_IT_TX_COMPLETE           FDCAN_IE_TCE   /*!< Transmission Completed                                */

+#define FDCAN_IT_TX_ABORT_COMPLETE     FDCAN_IE_TCFE  /*!< Transmission Cancellation Finished                    */

+#define FDCAN_IT_TX_FIFO_EMPTY         FDCAN_IE_TFEE  /*!< Tx FIFO Empty                                         */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_Rx_Interrupts FDCAN Rx Interrupts

+  * @{

+  */

+#define FDCAN_IT_RX_HIGH_PRIORITY_MSG  FDCAN_IE_HPME  /*!< High priority message received                        */

+#define FDCAN_IT_RX_BUFFER_NEW_MESSAGE FDCAN_IE_DRXE  /*!< At least one received message stored into a Rx Buffer */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_Counter_Interrupts FDCAN Counter Interrupts

+  * @{

+  */

+#define FDCAN_IT_TIMESTAMP_WRAPAROUND  FDCAN_IE_TSWE  /*!< Timestamp counter wrapped around                      */

+#define FDCAN_IT_TIMEOUT_OCCURRED      FDCAN_IE_TOOE  /*!< Timeout reached                                       */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_Clock_Calibration_Interrupts Clock Calibration Interrupts

+  * @{

+  */

+#define FDCAN_IT_CALIB_STATE_CHANGED  (FDCANCCU_IE_CSCE << 30) /*!< Clock calibration state changed           */

+#define FDCAN_IT_CALIB_WATCHDOG_EVENT (FDCANCCU_IE_CWEE << 30) /*!< Clock calibration watchdog event occurred */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_Tx_Event_Fifo_Interrupts FDCAN Tx Event FIFO Interrupts

+  * @{

+  */

+#define FDCAN_IT_TX_EVT_FIFO_ELT_LOST  FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost                 */

+#define FDCAN_IT_TX_EVT_FIFO_FULL      FDCAN_IE_TEFFE /*!< Tx Event FIFO full                         */

+#define FDCAN_IT_TX_EVT_FIFO_WATERMARK FDCAN_IE_TEFWE /*!< Tx Event FIFO fill level reached watermark */

+#define FDCAN_IT_TX_EVT_FIFO_NEW_DATA  FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element     */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_Rx_Fifo0_Interrupts FDCAN Rx FIFO 0 Interrupts

+  * @{

+  */

+#define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost                 */

+#define FDCAN_IT_RX_FIFO0_FULL         FDCAN_IE_RF0FE /*!< Rx FIFO 0 full                         */

+#define FDCAN_IT_RX_FIFO0_WATERMARK    FDCAN_IE_RF0WE /*!< Rx FIFO 0 fill level reached watermark */

+#define FDCAN_IT_RX_FIFO0_NEW_MESSAGE  FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0       */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_Rx_Fifo1_Interrupts FDCAN Rx FIFO 1 Interrupts

+  * @{

+  */

+#define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost                 */

+#define FDCAN_IT_RX_FIFO1_FULL         FDCAN_IE_RF1FE /*!< Rx FIFO 1 full                         */

+#define FDCAN_IT_RX_FIFO1_WATERMARK    FDCAN_IE_RF1WE /*!< Rx FIFO 1 fill level reached watermark */

+#define FDCAN_IT_RX_FIFO1_NEW_MESSAGE  FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1       */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_Error_Interrupts FDCAN Error Interrupts

+  * @{

+  */

+#define FDCAN_IT_RAM_ACCESS_FAILURE      FDCAN_IE_MRAFE /*!< Message RAM access failure occurred              */

+#define FDCAN_IT_ERROR_LOGGING_OVERFLOW  FDCAN_IE_ELOE  /*!< Overflow of FDCAN Error Logging Counter occurred */

+#define FDCAN_IT_RAM_WATCHDOG            FDCAN_IE_WDIE  /*!< Message RAM Watchdog event due to missing READY  */

+#define FDCAN_IT_ARB_PROTOCOL_ERROR      FDCAN_IE_PEAE  /*!< Protocol error in arbitration phase detected     */

+#define FDCAN_IT_DATA_PROTOCOL_ERROR     FDCAN_IE_PEDE  /*!< Protocol error in data phase detected            */

+#define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE  /*!< Access to reserved address occurred              */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts

+  * @{

+  */

+#define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */

+#define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */

+#define FDCAN_IT_BUS_OFF       FDCAN_IE_BOE /*!< Bus_Off status changed       */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_TTflags FDCAN TT Flags

+  * @{

+  */

+#define FDCAN_TT_FLAG_BASIC_CYCLE_START    FDCAN_TTIR_SBC  /*!< Start of Basic Cycle             */

+#define FDCAN_TT_FLAG_MATRIX_CYCLE_START   FDCAN_TTIR_SMC  /*!< Start of Matrix Cycle            */

+#define FDCAN_TT_FLAG_SYNC_MODE_CHANGE     FDCAN_TTIR_CSM  /*!< Change of Synchronization Mode   */

+#define FDCAN_TT_FLAG_START_OF_GAP         FDCAN_TTIR_SOG  /*!< Start of Gap                     */

+#define FDCAN_TT_FLAG_REG_TIME_MARK        FDCAN_TTIR_RTMI /*!< Register Time Mark Interrupt     */

+#define FDCAN_TT_FLAG_TRIG_TIME_MARK       FDCAN_TTIR_TTMI /*!< Trigger Time Mark Event Internal */

+#define FDCAN_TT_FLAG_STOP_WATCH           FDCAN_TTIR_SWE  /*!< Stop Watch Event                 */

+#define FDCAN_TT_FLAG_GLOBAL_TIME_WRAP     FDCAN_TTIR_GTW  /*!< Global Time Wrap                 */

+#define FDCAN_TT_FLAG_GLOBAL_TIME_DISC     FDCAN_TTIR_GTD  /*!< Global Time Discontinuity        */

+#define FDCAN_TT_FLAG_GLOBAL_TIME_ERROR    FDCAN_TTIR_GTE  /*!< Global Time Error                */

+#define FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW   FDCAN_TTIR_TXU  /*!< Tx Count Underflow               */

+#define FDCAN_TT_FLAG_TX_COUNT_OVERFLOW    FDCAN_TTIR_TXO  /*!< Tx Count Overflow                */

+#define FDCAN_TT_FLAG_SCHEDULING_ERROR_1   FDCAN_TTIR_SE1  /*!< Scheduling Error 1               */

+#define FDCAN_TT_FLAG_SCHEDULING_ERROR_2   FDCAN_TTIR_SE2  /*!< Scheduling Error 2               */

+#define FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE   FDCAN_TTIR_ELC  /*!< Error Level Changed              */

+#define FDCAN_TT_FLAG_INIT_WATCH_TRIGGER   FDCAN_TTIR_IWT  /*!< Initialization Watch Trigger     */

+#define FDCAN_TT_FLAG_WATCH_TRIGGER        FDCAN_TTIR_WT   /*!< Watch Trigger                    */

+#define FDCAN_TT_FLAG_APPLICATION_WATCHDOG FDCAN_TTIR_AW   /*!< Application Watchdog             */

+#define FDCAN_TT_FLAG_CONFIG_ERROR         FDCAN_TTIR_CER  /*!< Configuration Error              */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_TTInterrupts FDCAN TT Interrupts

+  * @{

+  */

+

+/** @defgroup FDCAN_TTScheduleSynchronization_Interrupts FDCAN TT Schedule Synchronization Interrupts

+  * @{

+  */

+#define FDCAN_TT_IT_BASIC_CYCLE_START  FDCAN_TTIE_SBCE /*!< Start of Basic Cycle           */

+#define FDCAN_TT_IT_MATRIX_CYCLE_START FDCAN_TTIE_SMCE /*!< Start of Matrix Cycle          */

+#define FDCAN_TT_IT_SYNC_MODE_CHANGE   FDCAN_TTIE_CSME /*!< Change of Synchronization Mode */

+#define FDCAN_TT_IT_START_OF_GAP       FDCAN_TTIE_SOGE /*!< Start of Gap                   */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_TTTimeMark_Interrupts FDCAN TT Time Mark Interrupts

+  * @{

+  */

+#define FDCAN_TT_IT_REG_TIME_MARK  FDCAN_TTIE_RTMIE /*!< Register Time Mark Interrupt     */

+#define FDCAN_TT_IT_TRIG_TIME_MARK FDCAN_TTIE_TTMIE /*!< Trigger Time Mark Event Internal */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_TTStopWatch_Interrupt FDCAN TT Stop Watch Interrupt

+  * @{

+  */

+#define FDCAN_TT_IT_STOP_WATCH FDCAN_TTIE_SWEE /*!< Stop Watch Event */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_TTGlobalTime_Interrupts FDCAN TT Global Time Interrupts

+  * @{

+  */

+#define FDCAN_TT_IT_GLOBAL_TIME_WRAP FDCAN_TTIE_GTWE  /*!< Global Time Wrap          */

+#define FDCAN_TT_IT_GLOBAL_TIME_DISC FDCAN_TTIE_GTDE  /*!< Global Time Discontinuity */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_TTDisturbingError_Interrupts FDCAN TT Disturbing Error Interrupts

+  * @{

+  */

+#define FDCAN_TT_IT_GLOBAL_TIME_ERROR  FDCAN_TTIE_GTEE /*!< Global Time Error   */

+#define FDCAN_TT_IT_TX_COUNT_UNDERFLOW FDCAN_TTIE_TXUE /*!< Tx Count Underflow  */

+#define FDCAN_TT_IT_TX_COUNT_OVERFLOW  FDCAN_TTIE_TXOE /*!< Tx Count Overflow   */

+#define FDCAN_TT_IT_SCHEDULING_ERROR_1 FDCAN_TTIE_SE1E /*!< Scheduling Error 1  */

+#define FDCAN_TT_IT_SCHEDULING_ERROR_2 FDCAN_TTIE_SE2E /*!< Scheduling Error 2  */

+#define FDCAN_TT_IT_ERROR_LEVEL_CHANGE FDCAN_TTIE_ELCE /*!< Error Level Changed */

+/**

+  * @}

+  */

+

+/** @defgroup FDCAN_TTFatalError_Interrupts FDCAN TT Fatal Error Interrupts

+  * @{

+  */

+#define FDCAN_TT_IT_INIT_WATCH_TRIGGER   FDCAN_TTIE_IWTE /*!< Initialization Watch Trigger */

+#define FDCAN_TT_IT_WATCH_TRIGGER        FDCAN_TTIE_WTE  /*!< Watch Trigger                */

+#define FDCAN_TT_IT_APPLICATION_WATCHDOG FDCAN_TTIE_AWE  /*!< Application Watchdog         */

+#define FDCAN_TT_IT_CONFIG_ERROR         FDCAN_TTIE_CERE /*!< Configuration Error          */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup FDCAN_Exported_Macros FDCAN Exported Macros

+  * @{

+  */

+

+/** @brief  Reset FDCAN handle state.

+  * @param  __HANDLE__ FDCAN handle.

+  * @retval None

+  */

+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1

+#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{                                                \

+                                                      (__HANDLE__)->State = HAL_FDCAN_STATE_RESET;    \

+                                                      (__HANDLE__)->MspInitCallback = NULL;           \

+                                                      (__HANDLE__)->MspDeInitCallback = NULL;         \

+                                                     } while(0)

+#else

+#define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET)

+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */

+

+/**

+  * @brief  Enable the specified FDCAN interrupts.

+  * @param  __HANDLE__ FDCAN handle.

+  * @param  __INTERRUPT__ FDCAN interrupt.

+  *         This parameter can be any combination of @arg FDCAN_Interrupts

+  * @retval None

+  */

+#define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__)             \

+  do{                                                                \

+    (__HANDLE__)->Instance->IE |= ((__INTERRUPT__) & FDCAN_IR_MASK); \

+    FDCAN_CCU->IE |= (((__INTERRUPT__) & CCU_IR_MASK) >> 30);        \

+  }while(0)

+

+

+/**

+  * @brief  Disable the specified FDCAN interrupts.

+  * @param  __HANDLE__ FDCAN handle.

+  * @param  __INTERRUPT__ FDCAN interrupt.

+  *         This parameter can be any combination of @arg FDCAN_Interrupts

+  * @retval None

+  */

+#define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__)               \

+  do{                                                                   \

+    ((__HANDLE__)->Instance->IE) &= ~((__INTERRUPT__) & FDCAN_IR_MASK); \

+    FDCAN_CCU->IE &= ~(((__INTERRUPT__) & CCU_IR_MASK) >> 30);          \

+  }while(0)

+

+/**

+  * @brief  Check whether the specified FDCAN interrupt is set or not.

+  * @param  __HANDLE__ FDCAN handle.

+  * @param  __INTERRUPT__ FDCAN interrupt.

+  *         This parameter can be one of @arg FDCAN_Interrupts

+  * @retval ITStatus

+  */

+#define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__INTERRUPT__)) : ((FDCAN_CCU->IR << 30) & (__INTERRUPT__)))

+

+/**

+  * @brief  Clear the specified FDCAN interrupts.

+  * @param  __HANDLE__ FDCAN handle.

+  * @param  __INTERRUPT__ specifies the interrupts to clear.

+  *         This parameter can be any combination of @arg FDCAN_Interrupts

+  * @retval None

+  */

+#define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__)               \

+do{                                                                   \

+    ((__HANDLE__)->Instance->IR) = ((__INTERRUPT__) & FDCAN_IR_MASK); \

+    FDCAN_CCU->IR = (((__INTERRUPT__) & CCU_IR_MASK) >> 30);          \

+  }while(0)

+

+/**

+  * @brief  Check whether the specified FDCAN flag is set or not.

+  * @param  __HANDLE__ FDCAN handle.

+  * @param  __FLAG__ FDCAN flag.

+  *         This parameter can be one of @arg FDCAN_flags

+  * @retval FlagStatus

+  */

+#define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) < FDCAN_FLAG_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__FLAG__)) : ((FDCAN_CCU->IR << 30) & (__FLAG__)))

+

+/**

+  * @brief  Clear the specified FDCAN flags.

+  * @param  __HANDLE__ FDCAN handle.

+  * @param  __FLAG__ specifies the flags to clear.

+  *         This parameter can be any combination of @arg FDCAN_flags

+  * @retval None

+  */

+#define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__)             \

+do{                                                              \

+    ((__HANDLE__)->Instance->IR) = ((__FLAG__) & FDCAN_IR_MASK); \

+    FDCAN_CCU->IR = (((__FLAG__) & CCU_IR_MASK) >> 30);          \

+  }while(0)

+

+/** @brief  Check if the specified FDCAN interrupt source is enabled or disabled.

+  * @param  __HANDLE__ FDCAN handle.

+  * @param  __INTERRUPT__ specifies the FDCAN interrupt source to check.

+  *         This parameter can be a value of @arg FDCAN_Interrupts

+  * @retval ITStatus

+  */

+#define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IE & (__INTERRUPT__)) : ((FDCAN_CCU->IE << 30) & (__INTERRUPT__)))

+

+/**

+  * @brief  Enable the specified FDCAN TT interrupts.

+  * @param  __HANDLE__ FDCAN handle.

+  * @param  __INTERRUPT__ FDCAN TT interrupt.

+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts

+  * @retval None

+  */

+#define __HAL_FDCAN_TT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) |= (__INTERRUPT__))

+

+/**

+  * @brief  Disable the specified FDCAN TT interrupts.

+  * @param  __HANDLE__ FDCAN handle.

+  * @param  __INTERRUPT__ FDCAN TT interrupt.

+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts

+  * @retval None

+  */

+#define __HAL_FDCAN_TT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) &= ~(__INTERRUPT__))

+

+/**

+  * @brief  Check whether the specified FDCAN TT interrupt is set or not.

+  * @param  __HANDLE__ FDCAN handle.

+  * @param  __INTERRUPT__ FDCAN TT interrupt.

+  *         This parameter can be one of @arg FDCAN_TTInterrupts

+  * @retval ITStatus

+  */

+#define __HAL_FDCAN_TT_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) & (__INTERRUPT__))

+

+/**

+  * @brief  Clear the specified FDCAN TT interrupts.

+  * @param  __HANDLE__ FDCAN handle.

+  * @param  __INTERRUPT__ specifies the TT interrupts to clear.

+  *         This parameter can be any combination of @arg FDCAN_TTInterrupts

+  * @retval None

+  */

+#define __HAL_FDCAN_TT_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) = (__INTERRUPT__))

+

+/**

+  * @brief  Check whether the specified FDCAN TT flag is set or not.

+  * @param  __HANDLE__ FDCAN handle.

+  * @param  __FLAG__ FDCAN TT flag.

+  *         This parameter can be one of @arg FDCAN_TTflags

+  * @retval FlagStatus

+  */

+#define __HAL_FDCAN_TT_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) & (__FLAG__))

+

+/**

+  * @brief  Clear the specified FDCAN TT flags.

+  * @param  __HANDLE__ FDCAN handle.

+  * @param  __FLAG__ specifies the TT flags to clear.

+  *         This parameter can be any combination of @arg FDCAN_TTflags

+  * @retval None

+  */

+#define __HAL_FDCAN_TT_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) = (__FLAG__))

+

+/** @brief  Check if the specified FDCAN TT interrupt source is enabled or disabled.

+  * @param  __HANDLE__ FDCAN handle.

+  * @param  __INTERRUPT__ specifies the FDCAN TT interrupt source to check.

+  *         This parameter can be a value of @arg FDCAN_TTInterrupts

+  * @retval ITStatus

+  */

+#define __HAL_FDCAN_TT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) & (__INTERRUPT__))

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup FDCAN_Exported_Functions

+  * @{

+  */

+

+/** @addtogroup FDCAN_Exported_Functions_Group1

+  * @{

+  */

+/* Initialization and de-initialization functions *****************************/

+HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan);

+void              HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan);

+void              HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan);

+

+#if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1

+/* Callbacks Register/UnRegister functions  ***********************************/

+HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, pFDCAN_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID);

+HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ClockCalibrationCallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_FDCAN_UnRegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_TimeMarkCallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_StopWatchCallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan);

+#endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/** @addtogroup FDCAN_Exported_Functions_Group2

+  * @{

+  */

+/* Configuration functions ****************************************************/

+HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig);

+uint32_t          HAL_FDCAN_GetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan);

+uint32_t          HAL_FDCAN_GetClockCalibrationCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t Counter);

+HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig);

+HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt);

+HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask);

+HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode);

+HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark);

+HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue);

+HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler);

+HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation);

+HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan);

+uint16_t          HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod);

+HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);

+uint16_t          HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter);

+HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);

+/**

+  * @}

+  */

+

+/** @addtogroup FDCAN_Exported_Functions_Group3

+  * @{

+  */

+/* Control functions **********************************************************/

+HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData);

+HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex);

+HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);

+uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);

+HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData);

+HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent);

+HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus);

+HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus);

+HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters);

+uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex);

+uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex);

+uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo);

+uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan);

+uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);

+/**

+  * @}

+  */

+

+/** @addtogroup FDCAN_Exported_Functions_Group4

+  * @{

+  */

+/* TT Configuration and control functions**************************************/

+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams);

+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload);

+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig);

+HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset);

+HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator);

+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity);

+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeMarkSource, uint32_t TimeMarkValue, uint32_t RepeatFactor, uint32_t StartCycle);

+HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase);

+HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);

+HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus);

+/**

+  * @}

+  */

+

+/** @addtogroup FDCAN_Exported_Functions_Group5

+  * @{

+  */

+/* Interrupts management ******************************************************/

+HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine);

+HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine);

+HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes);

+HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs);

+HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs);

+HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs);

+void              HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan);

+/**

+  * @}

+  */

+

+/** @addtogroup FDCAN_Exported_Functions_Group6

+  * @{

+  */

+/* Callback functions *********************************************************/

+void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs);

+void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);

+void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);

+void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);

+void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan);

+void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);

+void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);

+void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan);

+void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan);

+void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan);

+void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan);

+void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan);

+void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);

+void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs);

+void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);

+void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount);

+void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);

+/**

+  * @}

+  */

+

+/** @addtogroup FDCAN_Exported_Functions_Group7

+  * @{

+  */

+/* Peripheral State functions *************************************************/

+uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan);

+HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private types -------------------------------------------------------------*/

+/** @defgroup FDCAN_Private_Types FDCAN Private Types

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private variables ---------------------------------------------------------*/

+/** @defgroup FDCAN_Private_Variables FDCAN Private Variables

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup FDCAN_Private_Constants FDCAN Private Constants

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup FDCAN_Private_Macros FDCAN Private Macros

+  * @{

+  */

+#define IS_FDCAN_FRAME_FORMAT(FORMAT) (((FORMAT) == FDCAN_FRAME_CLASSIC  ) || \

+                                       ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \

+                                       ((FORMAT) == FDCAN_FRAME_FD_BRS   ))

+#define IS_FDCAN_MODE(MODE) (((MODE) == FDCAN_MODE_NORMAL              ) || \

+                             ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \

+                             ((MODE) == FDCAN_MODE_BUS_MONITORING      ) || \

+                             ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK   ) || \

+                             ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK   ))

+

+#define IS_FDCAN_CLOCK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_DISABLE) || \

+                                                 ((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_ENABLE ))

+

+#define IS_FDCAN_CKDIV(CKDIV) (((CKDIV) == FDCAN_CLOCK_DIV1 ) || \

+                               ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \

+                               ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \

+                               ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \

+                               ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \

+                               ((CKDIV) == FDCAN_CLOCK_DIV10) || \

+                               ((CKDIV) == FDCAN_CLOCK_DIV12) || \

+                               ((CKDIV) == FDCAN_CLOCK_DIV14) || \

+                               ((CKDIV) == FDCAN_CLOCK_DIV16) || \

+                               ((CKDIV) == FDCAN_CLOCK_DIV18) || \

+                               ((CKDIV) == FDCAN_CLOCK_DIV20) || \

+                               ((CKDIV) == FDCAN_CLOCK_DIV22) || \

+                               ((CKDIV) == FDCAN_CLOCK_DIV24) || \

+                               ((CKDIV) == FDCAN_CLOCK_DIV26) || \

+                               ((CKDIV) == FDCAN_CLOCK_DIV28) || \

+                               ((CKDIV) == FDCAN_CLOCK_DIV30))

+#define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U))

+#define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U))

+#define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U))

+#define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U))

+#define IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U))

+#define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U))

+#define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))

+#define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))

+#define IS_FDCAN_MAX_VALUE(VALUE, MAX) ((VALUE) <= (MAX))

+#define IS_FDCAN_MIN_VALUE(VALUE, MIN) ((VALUE) >= (MIN))

+#define IS_FDCAN_DATA_SIZE(SIZE) (((SIZE) == FDCAN_DATA_BYTES_8 ) || \

+                                  ((SIZE) == FDCAN_DATA_BYTES_12) || \

+                                  ((SIZE) == FDCAN_DATA_BYTES_16) || \

+                                  ((SIZE) == FDCAN_DATA_BYTES_20) || \

+                                  ((SIZE) == FDCAN_DATA_BYTES_24) || \

+                                  ((SIZE) == FDCAN_DATA_BYTES_32) || \

+                                  ((SIZE) == FDCAN_DATA_BYTES_48) || \

+                                  ((SIZE) == FDCAN_DATA_BYTES_64))

+#define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) (((MODE) == FDCAN_TX_FIFO_OPERATION ) || \

+                                           ((MODE) == FDCAN_TX_QUEUE_OPERATION))

+#define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \

+                                   ((ID_TYPE) == FDCAN_EXTENDED_ID))

+#define IS_FDCAN_FILTER_CFG(CONFIG) (((CONFIG) == FDCAN_FILTER_DISABLE      ) || \

+                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0   ) || \

+                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1   ) || \

+                                     ((CONFIG) == FDCAN_FILTER_REJECT       ) || \

+                                     ((CONFIG) == FDCAN_FILTER_HP           ) || \

+                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \

+                                     ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP) || \

+                                     ((CONFIG) == FDCAN_FILTER_TO_RXBUFFER  ))

+#define IS_FDCAN_TX_LOCATION(LOCATION) (((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \

+                                        ((LOCATION) == FDCAN_TX_BUFFER2 ) || ((LOCATION) == FDCAN_TX_BUFFER3 ) || \

+                                        ((LOCATION) == FDCAN_TX_BUFFER4 ) || ((LOCATION) == FDCAN_TX_BUFFER5 ) || \

+                                        ((LOCATION) == FDCAN_TX_BUFFER6 ) || ((LOCATION) == FDCAN_TX_BUFFER7 ) || \

+                                        ((LOCATION) == FDCAN_TX_BUFFER8 ) || ((LOCATION) == FDCAN_TX_BUFFER9 ) || \

+                                        ((LOCATION) == FDCAN_TX_BUFFER10) || ((LOCATION) == FDCAN_TX_BUFFER11) || \

+                                        ((LOCATION) == FDCAN_TX_BUFFER12) || ((LOCATION) == FDCAN_TX_BUFFER13) || \

+                                        ((LOCATION) == FDCAN_TX_BUFFER14) || ((LOCATION) == FDCAN_TX_BUFFER15) || \

+                                        ((LOCATION) == FDCAN_TX_BUFFER16) || ((LOCATION) == FDCAN_TX_BUFFER17) || \

+                                        ((LOCATION) == FDCAN_TX_BUFFER18) || ((LOCATION) == FDCAN_TX_BUFFER19) || \

+                                        ((LOCATION) == FDCAN_TX_BUFFER20) || ((LOCATION) == FDCAN_TX_BUFFER21) || \

+                                        ((LOCATION) == FDCAN_TX_BUFFER22) || ((LOCATION) == FDCAN_TX_BUFFER23) || \

+                                        ((LOCATION) == FDCAN_TX_BUFFER24) || ((LOCATION) == FDCAN_TX_BUFFER25) || \

+                                        ((LOCATION) == FDCAN_TX_BUFFER26) || ((LOCATION) == FDCAN_TX_BUFFER27) || \

+                                        ((LOCATION) == FDCAN_TX_BUFFER28) || ((LOCATION) == FDCAN_TX_BUFFER29) || \

+                                        ((LOCATION) == FDCAN_TX_BUFFER30) || ((LOCATION) == FDCAN_TX_BUFFER31))

+#define IS_FDCAN_RX_FIFO(FIFO) (((FIFO) == FDCAN_RX_FIFO0) || \

+                                ((FIFO) == FDCAN_RX_FIFO1))

+#define IS_FDCAN_RX_FIFO_MODE(MODE) (((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \

+                                     ((MODE) == FDCAN_RX_FIFO_OVERWRITE))

+#define IS_FDCAN_STD_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE) || \

+                                        ((TYPE) == FDCAN_FILTER_DUAL ) || \

+                                        ((TYPE) == FDCAN_FILTER_MASK ))

+#define IS_FDCAN_EXT_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE        ) || \

+                                        ((TYPE) == FDCAN_FILTER_DUAL         ) || \

+                                        ((TYPE) == FDCAN_FILTER_MASK         ) || \

+                                        ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM))

+#define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME  ) || \

+                                   ((TYPE) == FDCAN_REMOTE_FRAME))

+#define IS_FDCAN_DLC(DLC) (((DLC) == FDCAN_DLC_BYTES_0 ) || \

+                           ((DLC) == FDCAN_DLC_BYTES_1 ) || \

+                           ((DLC) == FDCAN_DLC_BYTES_2 ) || \

+                           ((DLC) == FDCAN_DLC_BYTES_3 ) || \

+                           ((DLC) == FDCAN_DLC_BYTES_4 ) || \

+                           ((DLC) == FDCAN_DLC_BYTES_5 ) || \

+                           ((DLC) == FDCAN_DLC_BYTES_6 ) || \

+                           ((DLC) == FDCAN_DLC_BYTES_7 ) || \

+                           ((DLC) == FDCAN_DLC_BYTES_8 ) || \

+                           ((DLC) == FDCAN_DLC_BYTES_12) || \

+                           ((DLC) == FDCAN_DLC_BYTES_16) || \

+                           ((DLC) == FDCAN_DLC_BYTES_20) || \

+                           ((DLC) == FDCAN_DLC_BYTES_24) || \

+                           ((DLC) == FDCAN_DLC_BYTES_32) || \

+                           ((DLC) == FDCAN_DLC_BYTES_48) || \

+                           ((DLC) == FDCAN_DLC_BYTES_64))

+#define IS_FDCAN_ESI(ESI) (((ESI) == FDCAN_ESI_ACTIVE ) || \

+                           ((ESI) == FDCAN_ESI_PASSIVE))

+#define IS_FDCAN_BRS(BRS) (((BRS) == FDCAN_BRS_OFF) || \

+                           ((BRS) == FDCAN_BRS_ON ))

+#define IS_FDCAN_FDF(FDF) (((FDF) == FDCAN_CLASSIC_CAN) || \

+                           ((FDF) == FDCAN_FD_CAN     ))

+#define IS_FDCAN_EFC(EFC) (((EFC) == FDCAN_NO_TX_EVENTS   ) || \

+                           ((EFC) == FDCAN_STORE_TX_EVENTS))

+#define IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK | CCU_IR_MASK)) == 0U)

+#define IS_FDCAN_TT_IT(IT) (((IT) & 0xFFF80000U) == 0U)

+#define IS_FDCAN_FIFO_WATERMARK(FIFO) (((FIFO) == FDCAN_CFG_TX_EVENT_FIFO) || \

+                                       ((FIFO) == FDCAN_CFG_RX_FIFO0     ) || \

+                                       ((FIFO) == FDCAN_CFG_RX_FIFO1     ))

+#define IS_FDCAN_NON_MATCHING(DESTINATION) (((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \

+                                            ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \

+                                            ((DESTINATION) == FDCAN_REJECT            ))

+#define IS_FDCAN_REJECT_REMOTE(DESTINATION) (((DESTINATION) == FDCAN_FILTER_REMOTE) || \

+                                             ((DESTINATION) == FDCAN_REJECT_REMOTE))

+#define IS_FDCAN_IT_LINE(IT_LINE) (((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \

+                                   ((IT_LINE) == FDCAN_INTERRUPT_LINE1))

+#define IS_FDCAN_TIMESTAMP(OPERATION) (((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \

+                                       ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL))

+#define IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER) (((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \

+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \

+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \

+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \

+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \

+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \

+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \

+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \

+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \

+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \

+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \

+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \

+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \

+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \

+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \

+                                                 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16))

+#define IS_FDCAN_TIMEOUT(OPERATION) (((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS   ) || \

+                                     ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \

+                                     ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0     ) || \

+                                     ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1     ))

+#define IS_FDCAN_CALIBRATION_FIELD_LENGTH(LENGTH) (((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_32) || \

+                                                   ((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_64))

+#define IS_FDCAN_CALIBRATION_COUNTER(COUNTER) (((COUNTER) == FDCAN_CALIB_TIME_QUANTA_COUNTER ) || \

+                                               ((COUNTER) == FDCAN_CALIB_CLOCK_PERIOD_COUNTER) || \

+                                               ((COUNTER) == FDCAN_CALIB_WATCHDOG_COUNTER    ))

+#define IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(PAYLOAD) (((PAYLOAD) == FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ) || \

+                                                        ((PAYLOAD) == FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD))

+#define IS_FDCAN_TT_REPEAT_FACTOR(FACTOR) (((FACTOR) == FDCAN_TT_REPEAT_EVERY_CYCLE     ) || \

+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ) || \

+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ) || \

+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ) || \

+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_16TH_CYCLE) || \

+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_32ND_CYCLE) || \

+                                           ((FACTOR) == FDCAN_TT_REPEAT_EVERY_64TH_CYCLE))

+#define IS_FDCAN_TT_TRIGGER_TYPE(TYPE) (((TYPE) == FDCAN_TT_TX_REF_TRIGGER        ) || \

+                                        ((TYPE) == FDCAN_TT_TX_REF_TRIGGER_GAP    ) || \

+                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_SINGLE     ) || \

+                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_CONTINUOUS ) || \

+                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_ARBITRATION) || \

+                                        ((TYPE) == FDCAN_TT_TX_TRIGGER_MERGED     ) || \

+                                        ((TYPE) == FDCAN_TT_WATCH_TRIGGER         ) || \

+                                        ((TYPE) == FDCAN_TT_WATCH_TRIGGER_GAP     ) || \

+                                        ((TYPE) == FDCAN_TT_RX_TRIGGER            ) || \

+                                        ((TYPE) == FDCAN_TT_TIME_BASE_TRIGGER     ) || \

+                                        ((TYPE) == FDCAN_TT_END_OF_LIST           ))

+#define IS_FDCAN_TT_TM_EVENT_INTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_INTERNAL_EVENT ) || \

+                                              ((EVENT) == FDCAN_TT_TM_GEN_INTERNAL_EVENT))

+#define IS_FDCAN_TT_TM_EVENT_EXTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_EXTERNAL_EVENT ) || \

+                                              ((EVENT) == FDCAN_TT_TM_GEN_EXTERNAL_EVENT))

+#define IS_FDCAN_OPERATION_MODE(MODE) (((MODE) == FDCAN_TT_COMMUNICATION_LEVEL1 ) || \

+                                       ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL2 ) || \

+                                       ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL0 ))

+#define IS_FDCAN_TT_OPERATION(OPERATION) (((OPERATION) == FDCAN_STRICTLY_TT_OPERATION      ) || \

+                                          ((OPERATION) == FDCAN_EXT_EVT_SYNC_TT_OPERATION))

+#define IS_FDCAN_TT_TIME_MASTER(FUNCTION) (((FUNCTION) == FDCAN_TT_SLAVE           ) || \

+                                           ((FUNCTION) == FDCAN_TT_POTENTIAL_MASTER))

+#define IS_FDCAN_TT_EXTERNAL_CLK_SYNC(SYNC) (((SYNC) == FDCAN_TT_EXT_CLK_SYNC_DISABLE) || \

+                                             ((SYNC) == FDCAN_TT_EXT_CLK_SYNC_ENABLE ))

+#define IS_FDCAN_TT_GLOBAL_TIME_FILTERING(FILTERING) (((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_DISABLE) || \

+                                                      ((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_ENABLE ))

+#define IS_FDCAN_TT_AUTO_CLK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_DISABLE) || \

+                                                       ((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_ENABLE ))

+#define IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_EVT_TRIG_POL_RISING ) || \

+                                                      ((POLARITY) == FDCAN_TT_EVT_TRIG_POL_FALLING))

+#define IS_FDCAN_TT_BASIC_CYCLES_NUMBER(NUMBER) (((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_1 ) || \

+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_2 ) || \

+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_4 ) || \

+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_8 ) || \

+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_16) || \

+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_32) || \

+                                                 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_64))

+#define IS_FDCAN_TT_CYCLE_START_SYNC(SYNC) (((SYNC) == FDCAN_TT_NO_SYNC_PULSE         ) || \

+                                            ((SYNC) == FDCAN_TT_SYNC_BASIC_CYCLE_START) || \

+                                            ((SYNC) == FDCAN_TT_SYNC_MATRIX_START     ))

+#define IS_FDCAN_TT_TX_ENABLE_WINDOW(NTU) (((NTU) >= 1U) && ((NTU) <= 16U))

+#define IS_FDCAN_TT_TUR_NUMERATOR(NUMERATOR) (((NUMERATOR) >= 0x10000U) && ((NUMERATOR) <= 0x1FFFFU))

+#define IS_FDCAN_TT_TUR_DENOMINATOR(DENOMINATOR) (((DENOMINATOR) >= 0x0001U) && ((DENOMINATOR) <= 0x3FFFU))

+#define IS_FDCAN_TT_TUR_LEVEL_1(NC,DC) ((NC) >= (4U * (DC)))

+#define IS_FDCAN_TT_TUR_LEVEL_0_2(NC,DC) ((NC) >= (8U * (DC)))

+#define IS_FDCAN_TT_STOP_WATCH_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_0) || \

+                                                 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_1) || \

+                                                 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_2) || \

+                                                 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_3))

+#define IS_FDCAN_TT_EVENT_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_0) || \

+                                            ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_1) || \

+                                            ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_2) || \

+                                            ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_3))

+#define IS_FDCAN_TT_TIME_PRESET(TIME) (((TIME) <= 0xFFFFU) && ((TIME) != 0x8000U))

+#define IS_FDCAN_TT_STOP_WATCH_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_STOP_WATCH_DISABLED   ) || \

+                                               ((SOURCE) == FDCAN_TT_STOP_WATCH_CYCLE_TIME ) || \

+                                               ((SOURCE) == FDCAN_TT_STOP_WATCH_LOCAL_TIME ) || \

+                                               ((SOURCE) == FDCAN_TT_STOP_WATCH_GLOBAL_TIME))

+#define IS_FDCAN_TT_STOP_WATCH_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_STOP_WATCH_RISING ) || \

+                                                   ((POLARITY) == FDCAN_TT_STOP_WATCH_FALLING))

+#define IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_REG_TIMEMARK_DIABLED ) || \

+                                                       ((SOURCE) == FDCAN_TT_REG_TIMEMARK_CYC_TIME) || \

+                                                       ((SOURCE) == FDCAN_TT_REG_TIMEMARK_LOC_TIME) || \

+                                                       ((SOURCE) == FDCAN_TT_REG_TIMEMARK_GLO_TIME))

+/**

+  * @}

+  */

+

+/* Private functions prototypes ----------------------------------------------*/

+/** @defgroup FDCAN_Private_Functions_Prototypes FDCAN Private Functions Prototypes

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private functions ---------------------------------------------------------*/

+/** @defgroup FDCAN_Private_Functions FDCAN Private Functions

+  * @{

+  */

+

+/**

+  * @}

+  */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_FDCAN_H */

+

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_flash.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_flash.h
new file mode 100644
index 0000000000..6bda249e22
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_flash.h
@@ -0,0 +1,829 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_flash.h

+  * @author  MCD Application Team

+  * @brief   Header file of FLASH HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                       opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_FLASH_H

+#define STM32H7xx_HAL_FLASH_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup FLASH

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup FLASH_Exported_Types FLASH Exported Types

+  * @{

+  */

+

+/**

+  * @brief  FLASH Procedure structure definition

+  */

+typedef enum

+{

+  FLASH_PROC_NONE = 0U,

+  FLASH_PROC_SECTERASE_BANK1,

+  FLASH_PROC_MASSERASE_BANK1,

+  FLASH_PROC_PROGRAM_BANK1,

+  FLASH_PROC_SECTERASE_BANK2,

+  FLASH_PROC_MASSERASE_BANK2,

+  FLASH_PROC_PROGRAM_BANK2,

+  FLASH_PROC_ALLBANK_MASSERASE

+} FLASH_ProcedureTypeDef;

+

+

+/**

+  * @brief  FLASH handle Structure definition

+  */

+typedef struct

+{

+  __IO FLASH_ProcedureTypeDef ProcedureOnGoing;   /*!< Internal variable to indicate which procedure is ongoing or not in IT context */

+

+  __IO uint32_t               NbSectorsToErase;   /*!< Internal variable to save the remaining sectors to erase in IT context        */

+

+  __IO uint32_t               VoltageForErase;    /*!< Internal variable to provide voltage range selected by user in IT context     */

+

+  __IO uint32_t               Sector;             /*!< Internal variable to define the current sector which is erasing               */

+

+  __IO uint32_t               Address;            /*!< Internal variable to save address selected for program                        */

+

+  HAL_LockTypeDef             Lock;               /*!< FLASH locking object                                                          */

+

+  __IO uint32_t               ErrorCode;          /*!< FLASH error code                                                              */

+

+}FLASH_ProcessTypeDef;

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup FLASH_Exported_Constants FLASH Exported Constants

+  * @{

+  */

+

+/** @defgroup FLASH_Error_Code FLASH Error Code

+  * @brief    FLASH Error Code

+  * @{

+  */

+#define HAL_FLASH_ERROR_NONE         0x00000000U               /*!< No error                              */

+

+#define HAL_FLASH_ERROR_WRP          FLASH_FLAG_WRPERR         /*!< Write Protection Error                */

+#define HAL_FLASH_ERROR_PGS          FLASH_FLAG_PGSERR         /*!< Program Sequence Error                */

+#define HAL_FLASH_ERROR_STRB         FLASH_FLAG_STRBERR        /*!< Strobe Error                          */

+#define HAL_FLASH_ERROR_INC          FLASH_FLAG_INCERR         /*!< Inconsistency Error                   */

+#if defined (FLASH_SR_OPERR)

+#define HAL_FLASH_ERROR_OPE          FLASH_FLAG_OPERR          /*!< Operation Error                       */

+#endif /* FLASH_SR_OPERR */

+#define HAL_FLASH_ERROR_RDP          FLASH_FLAG_RDPERR         /*!< Read Protection Error                 */

+#define HAL_FLASH_ERROR_RDS          FLASH_FLAG_RDSERR         /*!< Read Secured Error                    */

+#define HAL_FLASH_ERROR_SNECC        FLASH_FLAG_SNECCERR       /*!< ECC Single Correction Error           */

+#define HAL_FLASH_ERROR_DBECC        FLASH_FLAG_DBECCERR       /*!< ECC Double Detection Error            */

+#define HAL_FLASH_ERROR_CRCRD        FLASH_FLAG_CRCRDERR       /*!< CRC Read Error                        */

+

+#define HAL_FLASH_ERROR_WRP_BANK1    FLASH_FLAG_WRPERR_BANK1   /*!< Write Protection Error on Bank 1      */

+#define HAL_FLASH_ERROR_PGS_BANK1    FLASH_FLAG_PGSERR_BANK1   /*!< Program Sequence Error on Bank 1      */

+#define HAL_FLASH_ERROR_STRB_BANK1   FLASH_FLAG_STRBERR_BANK1  /*!< Strobe Error on Bank 1                */

+#define HAL_FLASH_ERROR_INC_BANK1    FLASH_FLAG_INCERR_BANK1   /*!< Inconsistency Error on Bank 1         */

+#if defined (FLASH_SR_OPERR)

+#define HAL_FLASH_ERROR_OPE_BANK1    FLASH_FLAG_OPERR_BANK1    /*!< Operation Error on Bank 1             */

+#endif /* FLASH_SR_OPERR */

+#define HAL_FLASH_ERROR_RDP_BANK1    FLASH_FLAG_RDPERR_BANK1   /*!< Read Protection Error on Bank 1       */

+#define HAL_FLASH_ERROR_RDS_BANK1    FLASH_FLAG_RDSERR_BANK1   /*!< Read Secured Error on Bank 1          */

+#define HAL_FLASH_ERROR_SNECC_BANK1  FLASH_FLAG_SNECCERR_BANK1 /*!< ECC Single Correction Error on Bank 1 */

+#define HAL_FLASH_ERROR_DBECC_BANK1  FLASH_FLAG_DBECCERR_BANK1 /*!< ECC Double Detection Error on Bank 1  */

+#define HAL_FLASH_ERROR_CRCRD_BANK1  FLASH_FLAG_CRCRDERR_BANK1 /*!< CRC Read Error on Bank1               */

+

+#define HAL_FLASH_ERROR_WRP_BANK2    FLASH_FLAG_WRPERR_BANK2    /*!< Write Protection Error on Bank 2      */

+#define HAL_FLASH_ERROR_PGS_BANK2    FLASH_FLAG_PGSERR_BANK2    /*!< Program Sequence Error on Bank 2      */

+#define HAL_FLASH_ERROR_STRB_BANK2   FLASH_FLAG_STRBERR_BANK2   /*!< Strobe Error on Bank 2                */

+#define HAL_FLASH_ERROR_INC_BANK2    FLASH_FLAG_INCERR_BANK2    /*!< Inconsistency Error on Bank 2         */

+#if defined (FLASH_SR_OPERR)

+#define HAL_FLASH_ERROR_OPE_BANK2    FLASH_FLAG_OPERR_BANK2     /*!< Operation Error on Bank 2             */

+#endif /* FLASH_SR_OPERR */

+#define HAL_FLASH_ERROR_RDP_BANK2    FLASH_FLAG_RDPERR_BANK2    /*!< Read Protection Error on Bank 2       */

+#define HAL_FLASH_ERROR_RDS_BANK2    FLASH_FLAG_RDSERR_BANK2    /*!< Read Secured Error on Bank 2          */

+#define HAL_FLASH_ERROR_SNECC_BANK2  FLASH_FLAG_SNECCERR_BANK2  /*!< ECC Single Correction Error on Bank 2 */

+#define HAL_FLASH_ERROR_DBECC_BANK2  FLASH_FLAG_DBECCERR_BANK2  /*!< ECC Double Detection Error on Bank 2  */

+#define HAL_FLASH_ERROR_CRCRD_BANK2  FLASH_FLAG_CRCRDERR_BANK2  /*!< CRC Read Error on Bank2               */

+

+#define HAL_FLASH_ERROR_OB_CHANGE    FLASH_OPTSR_OPTCHANGEERR   /*!< Option Byte Change Error              */

+/**

+  * @}

+  */

+

+/** @defgroup FLASH_Type_Program FLASH Type Program

+  * @{

+  */

+#define FLASH_TYPEPROGRAM_FLASHWORD  0x01U        /*!< Program a flash word at a specified address */

+#if defined (FLASH_OPTCR_PG_OTP)

+#define FLASH_TYPEPROGRAM_OTPWORD    0x02U        /*!< Program an OTP word at a specified address  */

+#endif /* FLASH_OPTCR_PG_OTP */

+/**

+  * @}

+  */

+

+/** @defgroup FLASH_Flag_definition FLASH Flag definition

+  * @brief Flag definition

+  * @{

+  */

+#define FLASH_FLAG_BSY                     FLASH_SR_BSY             /*!< FLASH Busy flag */

+#define FLASH_FLAG_WBNE                    FLASH_SR_WBNE            /*!< Write Buffer Not Empty flag */

+#define FLASH_FLAG_QW                      FLASH_SR_QW              /*!< Wait Queue on flag */

+#define FLASH_FLAG_CRC_BUSY                FLASH_SR_CRC_BUSY        /*!< CRC Busy flag */

+#define FLASH_FLAG_EOP                     FLASH_SR_EOP             /*!< End Of Program on flag */

+#define FLASH_FLAG_WRPERR                  FLASH_SR_WRPERR          /*!< Write Protection Error on flag */

+#define FLASH_FLAG_PGSERR                  FLASH_SR_PGSERR          /*!< Program Sequence Error on flag */

+#define FLASH_FLAG_STRBERR                 FLASH_SR_STRBERR         /*!< Strobe Error flag */

+#define FLASH_FLAG_INCERR                  FLASH_SR_INCERR          /*!< Inconsistency Error on flag */

+#if defined (FLASH_SR_OPERR)

+#define FLASH_FLAG_OPERR                   FLASH_SR_OPERR           /*!< Operation Error on flag */

+#endif /* FLASH_SR_OPERR */

+#define FLASH_FLAG_RDPERR                  FLASH_SR_RDPERR          /*!< Read Protection Error on flag */

+#define FLASH_FLAG_RDSERR                  FLASH_SR_RDSERR          /*!< Read Secured Error on flag */

+#define FLASH_FLAG_SNECCERR                FLASH_SR_SNECCERR        /*!< Single ECC Error Correction on flag */

+#define FLASH_FLAG_DBECCERR                FLASH_SR_DBECCERR        /*!< Double Detection ECC Error on flag */

+#define FLASH_FLAG_CRCEND                  FLASH_SR_CRCEND          /*!< CRC End of Calculation flag */

+#define FLASH_FLAG_CRCRDERR                FLASH_SR_CRCRDERR        /*!< CRC Read Error on bank flag */

+

+#define FLASH_FLAG_BSY_BANK1               FLASH_SR_BSY             /*!< FLASH Bank 1 Busy flag */

+#define FLASH_FLAG_WBNE_BANK1              FLASH_SR_WBNE            /*!< Write Buffer Not Empty on Bank 1 flag */

+#define FLASH_FLAG_QW_BANK1                FLASH_SR_QW              /*!< Wait Queue on Bank 1 flag */

+#define FLASH_FLAG_CRC_BUSY_BANK1          FLASH_SR_CRC_BUSY        /*!< CRC Busy on Bank 1 flag */

+#define FLASH_FLAG_EOP_BANK1               FLASH_SR_EOP             /*!< End Of Program on Bank 1 flag */

+#define FLASH_FLAG_WRPERR_BANK1            FLASH_SR_WRPERR          /*!< Write Protection Error on Bank 1 flag */

+#define FLASH_FLAG_PGSERR_BANK1            FLASH_SR_PGSERR          /*!< Program Sequence Error on Bank 1 flag */

+#define FLASH_FLAG_STRBERR_BANK1           FLASH_SR_STRBERR         /*!< Strobe Error on Bank 1 flag */

+#define FLASH_FLAG_INCERR_BANK1            FLASH_SR_INCERR          /*!< Inconsistency Error on Bank 1 flag */

+#if defined (FLASH_SR_OPERR)

+#define FLASH_FLAG_OPERR_BANK1             FLASH_SR_OPERR           /*!< Operation Error on Bank 1 flag */

+#endif /* FLASH_SR_OPERR */

+#define FLASH_FLAG_RDPERR_BANK1            FLASH_SR_RDPERR          /*!< Read Protection Error on Bank 1 flag */

+#define FLASH_FLAG_RDSERR_BANK1            FLASH_SR_RDSERR          /*!< Read Secured Error on Bank 1 flag */

+#define FLASH_FLAG_SNECCERR_BANK1          FLASH_SR_SNECCERR        /*!< Single ECC Error Correction on Bank 1 flag */

+#define FLASH_FLAG_DBECCERR_BANK1          FLASH_SR_DBECCERR        /*!< Double Detection ECC Error on Bank 1 flag */

+#define FLASH_FLAG_CRCEND_BANK1            FLASH_SR_CRCEND          /*!< CRC End of Calculation on Bank 1 flag */

+#define FLASH_FLAG_CRCRDERR_BANK1          FLASH_SR_CRCRDERR        /*!< CRC Read error on Bank 1 flag */

+

+#if defined (FLASH_SR_OPERR)

+#define FLASH_FLAG_ALL_ERRORS_BANK1       (FLASH_FLAG_WRPERR_BANK1   | FLASH_FLAG_PGSERR_BANK1   | \

+                                           FLASH_FLAG_STRBERR_BANK1  | FLASH_FLAG_INCERR_BANK1   | \

+                                           FLASH_FLAG_OPERR_BANK1    | FLASH_FLAG_RDPERR_BANK1   | \

+                                           FLASH_FLAG_RDSERR_BANK1   | FLASH_FLAG_SNECCERR_BANK1 | \

+                                           FLASH_FLAG_DBECCERR_BANK1 | FLASH_FLAG_CRCRDERR_BANK1) /*!< All Bank 1 error flags */

+#else

+#define FLASH_FLAG_ALL_ERRORS_BANK1       (FLASH_FLAG_WRPERR_BANK1   | FLASH_FLAG_PGSERR_BANK1   | \

+                                           FLASH_FLAG_STRBERR_BANK1  | FLASH_FLAG_INCERR_BANK1   | \

+                                           FLASH_FLAG_RDPERR_BANK1   | FLASH_FLAG_RDSERR_BANK1   | \

+                                           FLASH_FLAG_SNECCERR_BANK1 | FLASH_FLAG_DBECCERR_BANK1 | \

+                                           FLASH_FLAG_CRCRDERR_BANK1) /*!< All Bank 1 error flags */

+#endif /* FLASH_SR_OPERR */

+

+#define FLASH_FLAG_ALL_BANK1              (FLASH_FLAG_BSY_BANK1      | FLASH_FLAG_WBNE_BANK1     | \

+                                           FLASH_FLAG_QW_BANK1       | FLASH_FLAG_CRC_BUSY_BANK1 | \

+                                           FLASH_FLAG_EOP_BANK1      | FLASH_FLAG_CRCEND_BANK1   | \

+                                           FLASH_FLAG_ALL_ERRORS_BANK1) /*!< All Bank 1 flags */

+

+#define FLASH_FLAG_BSY_BANK2               (FLASH_SR_BSY      | 0x80000000U)        /*!< FLASH Bank 2 Busy flag */

+#define FLASH_FLAG_WBNE_BANK2              (FLASH_SR_WBNE     | 0x80000000U)        /*!< Write Buffer Not Empty on Bank 2 flag */

+#define FLASH_FLAG_QW_BANK2                (FLASH_SR_QW       | 0x80000000U)        /*!< Wait Queue on Bank 2 flag */

+#define FLASH_FLAG_CRC_BUSY_BANK2          (FLASH_SR_CRC_BUSY | 0x80000000U)        /*!< CRC Busy on Bank 2 flag */

+#define FLASH_FLAG_EOP_BANK2               (FLASH_SR_EOP      | 0x80000000U)        /*!< End Of Program on Bank 2 flag */

+#define FLASH_FLAG_WRPERR_BANK2            (FLASH_SR_WRPERR   | 0x80000000U)        /*!< Write Protection Error on Bank 2 flag */

+#define FLASH_FLAG_PGSERR_BANK2            (FLASH_SR_PGSERR   | 0x80000000U)        /*!< Program Sequence Error on Bank 2 flag */

+#define FLASH_FLAG_STRBERR_BANK2           (FLASH_SR_STRBERR  | 0x80000000U)        /*!< Strobe Error on Bank 2 flag */

+#define FLASH_FLAG_INCERR_BANK2            (FLASH_SR_INCERR   | 0x80000000U)        /*!< Inconsistency Error on Bank 2 flag */

+#if defined (FLASH_SR_OPERR)

+#define FLASH_FLAG_OPERR_BANK2             (FLASH_SR_OPERR    | 0x80000000U)        /*!< Operation Error on Bank 2 flag */

+#endif /* FLASH_SR_OPERR */

+#define FLASH_FLAG_RDPERR_BANK2            (FLASH_SR_RDPERR   | 0x80000000U)        /*!< Read Protection Error on Bank 2 flag */

+#define FLASH_FLAG_RDSERR_BANK2            (FLASH_SR_RDSERR   | 0x80000000U)        /*!< Read Secured Error on Bank 2 flag */

+#define FLASH_FLAG_SNECCERR_BANK2          (FLASH_SR_SNECCERR | 0x80000000U)        /*!< Single ECC Error Correction on Bank 2 flag */

+#define FLASH_FLAG_DBECCERR_BANK2          (FLASH_SR_DBECCERR | 0x80000000U)        /*!< Double Detection ECC Error on Bank 2 flag */

+#define FLASH_FLAG_CRCEND_BANK2            (FLASH_SR_CRCEND   | 0x80000000U)        /*!< CRC End of Calculation on Bank 2 flag */

+#define FLASH_FLAG_CRCRDERR_BANK2          (FLASH_SR_CRCRDERR | 0x80000000U)        /*!< CRC Read error on Bank 2 flag */

+

+#if defined (FLASH_SR_OPERR)

+#define FLASH_FLAG_ALL_ERRORS_BANK2       (FLASH_FLAG_WRPERR_BANK2   | FLASH_FLAG_PGSERR_BANK2   | \

+                                           FLASH_FLAG_STRBERR_BANK2  | FLASH_FLAG_INCERR_BANK2   | \

+                                           FLASH_FLAG_OPERR_BANK2    | FLASH_FLAG_RDPERR_BANK2   | \

+                                           FLASH_FLAG_RDSERR_BANK2   | FLASH_FLAG_SNECCERR_BANK2 | \

+                                           FLASH_FLAG_DBECCERR_BANK2 | FLASH_FLAG_CRCRDERR_BANK2) /*!< All Bank 2 error flags */

+#else

+#define FLASH_FLAG_ALL_ERRORS_BANK2       (FLASH_FLAG_WRPERR_BANK2   | FLASH_FLAG_PGSERR_BANK2   | \

+                                           FLASH_FLAG_STRBERR_BANK2  | FLASH_FLAG_INCERR_BANK2   | \

+                                           FLASH_FLAG_RDPERR_BANK2   | FLASH_FLAG_RDSERR_BANK2   | \

+                                           FLASH_FLAG_SNECCERR_BANK2 | FLASH_FLAG_DBECCERR_BANK2 | \

+                                           FLASH_FLAG_CRCRDERR_BANK2) /*!< All Bank 2 error flags */

+#endif /* FLASH_SR_OPERR */

+

+#define FLASH_FLAG_ALL_BANK2              (FLASH_FLAG_BSY_BANK2      | FLASH_FLAG_WBNE_BANK2     | \

+                                           FLASH_FLAG_QW_BANK2       | FLASH_FLAG_CRC_BUSY_BANK2 | \

+                                           FLASH_FLAG_EOP_BANK2      | FLASH_FLAG_CRCEND_BANK2   | \

+                                           FLASH_FLAG_ALL_ERRORS_BANK2) /*!< All Bank 2 flags */

+/**

+  * @}

+  */

+

+/** @defgroup FLASH_Interrupt_definition FLASH Interrupt definition

+  * @brief FLASH Interrupt definition

+  * @{

+  */

+#define FLASH_IT_EOP_BANK1                  FLASH_CR_EOPIE       /*!< End of FLASH Bank 1 Operation Interrupt source */

+#define FLASH_IT_WRPERR_BANK1               FLASH_CR_WRPERRIE    /*!< Write Protection Error on Bank 1 Interrupt source */

+#define FLASH_IT_PGSERR_BANK1               FLASH_CR_PGSERRIE    /*!< Program Sequence Error on Bank 1 Interrupt source */

+#define FLASH_IT_STRBERR_BANK1              FLASH_CR_STRBERRIE   /*!< Strobe Error on Bank 1 Interrupt source */

+#define FLASH_IT_INCERR_BANK1               FLASH_CR_INCERRIE    /*!< Inconsistency Error on Bank 1 Interrupt source */

+#if defined (FLASH_CR_OPERRIE)

+#define FLASH_IT_OPERR_BANK1                FLASH_CR_OPERRIE     /*!< Operation Error on Bank 1 Interrupt source */

+#endif /* FLASH_CR_OPERRIE */

+#define FLASH_IT_RDPERR_BANK1               FLASH_CR_RDPERRIE    /*!< Read protection Error on Bank 1 Interrupt source */

+#define FLASH_IT_RDSERR_BANK1               FLASH_CR_RDSERRIE    /*!< Read Secured Error on Bank 1 Interrupt source */

+#define FLASH_IT_SNECCERR_BANK1             FLASH_CR_SNECCERRIE  /*!< Single ECC Error Correction on Bank 1 Interrupt source */

+#define FLASH_IT_DBECCERR_BANK1             FLASH_CR_DBECCERRIE  /*!< Double Detection ECC Error on Bank 1 Interrupt source */

+#define FLASH_IT_CRCEND_BANK1               FLASH_CR_CRCENDIE    /*!< CRC End on Bank 1 Interrupt source */

+#define FLASH_IT_CRCRDERR_BANK1             FLASH_CR_CRCRDERRIE  /*!< CRC Read error on Bank 1 Interrupt source */

+

+#if defined (FLASH_CR_OPERRIE)

+#define FLASH_IT_ALL_BANK1                 (FLASH_IT_EOP_BANK1       | FLASH_IT_WRPERR_BANK1    | \

+                                            FLASH_IT_PGSERR_BANK1    | FLASH_IT_STRBERR_BANK1   | \

+                                            FLASH_IT_INCERR_BANK1    | FLASH_IT_OPERR_BANK1     | \

+                                            FLASH_IT_RDPERR_BANK1    | FLASH_IT_RDSERR_BANK1    | \

+                                            FLASH_IT_SNECCERR_BANK1  | FLASH_IT_DBECCERR_BANK1  | \

+                                            FLASH_IT_CRCEND_BANK1    | FLASH_IT_CRCRDERR_BANK1) /*!< All Bank 1 Interrupt sources */

+#else

+#define FLASH_IT_ALL_BANK1                 (FLASH_IT_EOP_BANK1       | FLASH_IT_WRPERR_BANK1    | \

+                                            FLASH_IT_PGSERR_BANK1    | FLASH_IT_STRBERR_BANK1   | \

+                                            FLASH_IT_INCERR_BANK1    | FLASH_IT_RDPERR_BANK1    | \

+                                            FLASH_IT_RDSERR_BANK1    | FLASH_IT_SNECCERR_BANK1  | \

+                                            FLASH_IT_DBECCERR_BANK1  | FLASH_IT_CRCEND_BANK1    | \

+                                            FLASH_IT_CRCRDERR_BANK1) /*!< All Bank 1 Interrupt sources */

+#endif /* FLASH_CR_OPERRIE */

+

+#define FLASH_IT_EOP_BANK2                 (FLASH_CR_EOPIE      | 0x80000000U)  /*!< End of FLASH Bank 2 Operation Interrupt source */

+#define FLASH_IT_WRPERR_BANK2              (FLASH_CR_WRPERRIE   | 0x80000000U)  /*!< Write Protection Error on Bank 2 Interrupt source */

+#define FLASH_IT_PGSERR_BANK2              (FLASH_CR_PGSERRIE   | 0x80000000U)  /*!< Program Sequence Error on Bank 2 Interrupt source */

+#define FLASH_IT_STRBERR_BANK2             (FLASH_CR_STRBERRIE  | 0x80000000U)  /*!< Strobe Error on Bank 2 Interrupt source */

+#define FLASH_IT_INCERR_BANK2              (FLASH_CR_INCERRIE   | 0x80000000U)  /*!< Inconsistency Error on Bank 2 Interrupt source */

+#if defined (FLASH_CR_OPERRIE)

+#define FLASH_IT_OPERR_BANK2               (FLASH_CR_OPERRIE    | 0x80000000U)  /*!< Operation Error on Bank 2 Interrupt source */

+#endif /* FLASH_CR_OPERRIE */

+#define FLASH_IT_RDPERR_BANK2              (FLASH_CR_RDPERRIE   | 0x80000000U)  /*!< Read protection Error on Bank 2 Interrupt source */

+#define FLASH_IT_RDSERR_BANK2              (FLASH_CR_RDSERRIE   | 0x80000000U)  /*!< Read Secured Error on Bank 2 Interrupt source */

+#define FLASH_IT_SNECCERR_BANK2            (FLASH_CR_SNECCERRIE | 0x80000000U)  /*!< Single ECC Error Correction on Bank 2 Interrupt source */

+#define FLASH_IT_DBECCERR_BANK2            (FLASH_CR_DBECCERRIE | 0x80000000U)  /*!< Double Detection ECC Error on Bank 2 Interrupt source */

+#define FLASH_IT_CRCEND_BANK2              (FLASH_CR_CRCENDIE   | 0x80000000U)  /*!< CRC End on Bank 2 Interrupt source */

+#define FLASH_IT_CRCRDERR_BANK2            (FLASH_CR_CRCRDERRIE | 0x80000000U)  /*!< CRC Read Error on Bank 2 Interrupt source */

+

+#if defined (FLASH_CR_OPERRIE)

+#define FLASH_IT_ALL_BANK2                 (FLASH_IT_EOP_BANK2       | FLASH_IT_WRPERR_BANK2    | \

+                                            FLASH_IT_PGSERR_BANK2    | FLASH_IT_STRBERR_BANK2   | \

+                                            FLASH_IT_INCERR_BANK2    | FLASH_IT_OPERR_BANK2     | \

+                                            FLASH_IT_RDPERR_BANK2    | FLASH_IT_RDSERR_BANK2    | \

+                                            FLASH_IT_SNECCERR_BANK2  | FLASH_IT_DBECCERR_BANK2  | \

+                                            FLASH_IT_CRCEND_BANK2    | FLASH_IT_CRCRDERR_BANK2) /*!< All Bank 2 Interrupt sources */

+#else

+#define FLASH_IT_ALL_BANK2                 (FLASH_IT_EOP_BANK2       | FLASH_IT_WRPERR_BANK2    | \

+                                            FLASH_IT_PGSERR_BANK2    | FLASH_IT_STRBERR_BANK2   | \

+                                            FLASH_IT_INCERR_BANK2    | FLASH_IT_RDPERR_BANK2    | \

+                                            FLASH_IT_RDSERR_BANK2    | FLASH_IT_SNECCERR_BANK2  | \

+                                            FLASH_IT_DBECCERR_BANK2  | FLASH_IT_CRCEND_BANK2    | \

+                                            FLASH_IT_CRCRDERR_BANK2) /*!< All Bank 2 Interrupt sources */

+#endif /* FLASH_CR_OPERRIE */

+/**

+  * @}

+  */

+

+#if defined (FLASH_CR_PSIZE)

+/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism

+  * @{

+  */

+#define FLASH_PSIZE_BYTE           0x00000000U       /*!< Flash program/erase by 8 bits  */

+#define FLASH_PSIZE_HALF_WORD      FLASH_CR_PSIZE_0  /*!< Flash program/erase by 16 bits */

+#define FLASH_PSIZE_WORD           FLASH_CR_PSIZE_1  /*!< Flash program/erase by 32 bits */

+#define FLASH_PSIZE_DOUBLE_WORD    FLASH_CR_PSIZE    /*!< Flash program/erase by 64 bits */

+/**

+  * @}

+  */

+#endif /* FLASH_CR_PSIZE */

+

+

+/** @defgroup FLASH_Keys FLASH Keys

+  * @{

+  */

+#define FLASH_KEY1                 0x45670123U

+#define FLASH_KEY2                 0xCDEF89ABU

+#define FLASH_OPT_KEY1             0x08192A3BU

+#define FLASH_OPT_KEY2             0x4C5D6E7FU

+/**

+  * @}

+  */

+

+/** @defgroup FLASH_Sectors FLASH Sectors

+  * @{

+  */

+#define FLASH_SECTOR_0             0U       /*!< Sector Number 0   */

+#define FLASH_SECTOR_1             1U       /*!< Sector Number 1   */

+#define FLASH_SECTOR_2             2U       /*!< Sector Number 2   */

+#define FLASH_SECTOR_3             3U       /*!< Sector Number 3   */

+#define FLASH_SECTOR_4             4U       /*!< Sector Number 4   */

+#define FLASH_SECTOR_5             5U       /*!< Sector Number 5   */

+#define FLASH_SECTOR_6             6U       /*!< Sector Number 6   */

+#define FLASH_SECTOR_7             7U       /*!< Sector Number 7   */

+#if (FLASH_SECTOR_TOTAL == 128)

+#define FLASH_SECTOR_8             8U       /*!< Sector Number 8   */

+#define FLASH_SECTOR_9             9U       /*!< Sector Number 9   */

+#define FLASH_SECTOR_10            10U      /*!< Sector Number 10  */

+#define FLASH_SECTOR_11            11U      /*!< Sector Number 11  */

+#define FLASH_SECTOR_12            12U      /*!< Sector Number 12  */

+#define FLASH_SECTOR_13            13U      /*!< Sector Number 13  */

+#define FLASH_SECTOR_14            14U      /*!< Sector Number 14  */

+#define FLASH_SECTOR_15            15U      /*!< Sector Number 15  */

+#define FLASH_SECTOR_16            16U      /*!< Sector Number 16  */

+#define FLASH_SECTOR_17            17U      /*!< Sector Number 17  */

+#define FLASH_SECTOR_18            18U      /*!< Sector Number 18  */

+#define FLASH_SECTOR_19            19U      /*!< Sector Number 19  */

+#define FLASH_SECTOR_20            20U      /*!< Sector Number 20  */

+#define FLASH_SECTOR_21            21U      /*!< Sector Number 21  */

+#define FLASH_SECTOR_22            22U      /*!< Sector Number 22  */

+#define FLASH_SECTOR_23            23U      /*!< Sector Number 23  */

+#define FLASH_SECTOR_24            24U      /*!< Sector Number 24  */

+#define FLASH_SECTOR_25            25U      /*!< Sector Number 25  */

+#define FLASH_SECTOR_26            26U      /*!< Sector Number 26  */

+#define FLASH_SECTOR_27            27U      /*!< Sector Number 27  */

+#define FLASH_SECTOR_28            28U      /*!< Sector Number 28  */

+#define FLASH_SECTOR_29            29U      /*!< Sector Number 29  */

+#define FLASH_SECTOR_30            30U      /*!< Sector Number 30  */

+#define FLASH_SECTOR_31            31U      /*!< Sector Number 31  */

+#define FLASH_SECTOR_32            32U      /*!< Sector Number 32  */

+#define FLASH_SECTOR_33            33U      /*!< Sector Number 33  */

+#define FLASH_SECTOR_34            34U      /*!< Sector Number 34  */

+#define FLASH_SECTOR_35            35U      /*!< Sector Number 35  */

+#define FLASH_SECTOR_36            36U      /*!< Sector Number 36  */

+#define FLASH_SECTOR_37            37U      /*!< Sector Number 37  */

+#define FLASH_SECTOR_38            38U      /*!< Sector Number 38  */

+#define FLASH_SECTOR_39            39U      /*!< Sector Number 39  */

+#define FLASH_SECTOR_40            40U      /*!< Sector Number 40  */

+#define FLASH_SECTOR_41            41U      /*!< Sector Number 41  */

+#define FLASH_SECTOR_42            42U      /*!< Sector Number 42  */

+#define FLASH_SECTOR_43            43U      /*!< Sector Number 43  */

+#define FLASH_SECTOR_44            44U      /*!< Sector Number 44  */

+#define FLASH_SECTOR_45            45U      /*!< Sector Number 45  */

+#define FLASH_SECTOR_46            46U      /*!< Sector Number 46  */

+#define FLASH_SECTOR_47            47U      /*!< Sector Number 47  */

+#define FLASH_SECTOR_48            48U      /*!< Sector Number 48  */

+#define FLASH_SECTOR_49            49U      /*!< Sector Number 49  */

+#define FLASH_SECTOR_50            50U      /*!< Sector Number 50  */

+#define FLASH_SECTOR_51            51U      /*!< Sector Number 51  */

+#define FLASH_SECTOR_52            52U      /*!< Sector Number 52  */

+#define FLASH_SECTOR_53            53U      /*!< Sector Number 53  */

+#define FLASH_SECTOR_54            54U      /*!< Sector Number 54  */

+#define FLASH_SECTOR_55            55U      /*!< Sector Number 55  */

+#define FLASH_SECTOR_56            56U      /*!< Sector Number 56  */

+#define FLASH_SECTOR_57            57U      /*!< Sector Number 57  */

+#define FLASH_SECTOR_58            58U      /*!< Sector Number 58  */

+#define FLASH_SECTOR_59            59U      /*!< Sector Number 59  */

+#define FLASH_SECTOR_60            60U      /*!< Sector Number 60  */

+#define FLASH_SECTOR_61            61U      /*!< Sector Number 61  */

+#define FLASH_SECTOR_62            62U      /*!< Sector Number 62  */

+#define FLASH_SECTOR_63            63U      /*!< Sector Number 63  */

+#define FLASH_SECTOR_64            64U      /*!< Sector Number 64  */

+#define FLASH_SECTOR_65            65U      /*!< Sector Number 65  */

+#define FLASH_SECTOR_66            66U      /*!< Sector Number 66  */

+#define FLASH_SECTOR_67            67U      /*!< Sector Number 67  */

+#define FLASH_SECTOR_68            68U      /*!< Sector Number 68  */

+#define FLASH_SECTOR_69            69U      /*!< Sector Number 69  */

+#define FLASH_SECTOR_70            70U      /*!< Sector Number 70  */

+#define FLASH_SECTOR_71            71U      /*!< Sector Number 71  */

+#define FLASH_SECTOR_72            72U      /*!< Sector Number 72  */

+#define FLASH_SECTOR_73            73U      /*!< Sector Number 73  */

+#define FLASH_SECTOR_74            74U      /*!< Sector Number 74  */

+#define FLASH_SECTOR_75            75U      /*!< Sector Number 75  */

+#define FLASH_SECTOR_76            76U      /*!< Sector Number 76  */

+#define FLASH_SECTOR_77            77U      /*!< Sector Number 77  */

+#define FLASH_SECTOR_78            78U      /*!< Sector Number 78  */

+#define FLASH_SECTOR_79            79U      /*!< Sector Number 79  */

+#define FLASH_SECTOR_80            80U      /*!< Sector Number 80  */

+#define FLASH_SECTOR_81            81U      /*!< Sector Number 81  */

+#define FLASH_SECTOR_82            82U      /*!< Sector Number 82  */

+#define FLASH_SECTOR_83            83U      /*!< Sector Number 83  */

+#define FLASH_SECTOR_84            84U      /*!< Sector Number 84  */

+#define FLASH_SECTOR_85            85U      /*!< Sector Number 85  */

+#define FLASH_SECTOR_86            86U      /*!< Sector Number 86  */

+#define FLASH_SECTOR_87            87U      /*!< Sector Number 87  */

+#define FLASH_SECTOR_88            88U      /*!< Sector Number 88  */

+#define FLASH_SECTOR_89            89U      /*!< Sector Number 89  */

+#define FLASH_SECTOR_90            90U      /*!< Sector Number 90  */

+#define FLASH_SECTOR_91            91U      /*!< Sector Number 91  */

+#define FLASH_SECTOR_92            92U      /*!< Sector Number 92  */

+#define FLASH_SECTOR_93            93U      /*!< Sector Number 93  */

+#define FLASH_SECTOR_94            94U      /*!< Sector Number 94  */

+#define FLASH_SECTOR_95            95U      /*!< Sector Number 95  */

+#define FLASH_SECTOR_96            96U      /*!< Sector Number 96  */

+#define FLASH_SECTOR_97            97U      /*!< Sector Number 97  */

+#define FLASH_SECTOR_98            98U      /*!< Sector Number 98  */

+#define FLASH_SECTOR_99            99U      /*!< Sector Number 99  */

+#define FLASH_SECTOR_100           100U     /*!< Sector Number 100 */

+#define FLASH_SECTOR_101           101U     /*!< Sector Number 101 */

+#define FLASH_SECTOR_102           102U     /*!< Sector Number 102 */

+#define FLASH_SECTOR_103           103U     /*!< Sector Number 103 */

+#define FLASH_SECTOR_104           104U     /*!< Sector Number 104 */

+#define FLASH_SECTOR_105           105U     /*!< Sector Number 105 */

+#define FLASH_SECTOR_106           106U     /*!< Sector Number 106 */

+#define FLASH_SECTOR_107           107U     /*!< Sector Number 107 */

+#define FLASH_SECTOR_108           108U     /*!< Sector Number 108 */

+#define FLASH_SECTOR_109           109U     /*!< Sector Number 109 */

+#define FLASH_SECTOR_110           110U     /*!< Sector Number 110 */

+#define FLASH_SECTOR_111           111U     /*!< Sector Number 111 */

+#define FLASH_SECTOR_112           112U     /*!< Sector Number 112 */

+#define FLASH_SECTOR_113           113U     /*!< Sector Number 113 */

+#define FLASH_SECTOR_114           114U     /*!< Sector Number 114 */

+#define FLASH_SECTOR_115           115U     /*!< Sector Number 115 */

+#define FLASH_SECTOR_116           116U     /*!< Sector Number 116 */

+#define FLASH_SECTOR_117           117U     /*!< Sector Number 117 */

+#define FLASH_SECTOR_118           118U     /*!< Sector Number 118 */

+#define FLASH_SECTOR_119           119U     /*!< Sector Number 119 */

+#define FLASH_SECTOR_120           120U     /*!< Sector Number 120 */

+#define FLASH_SECTOR_121           121U     /*!< Sector Number 121 */

+#define FLASH_SECTOR_122           122U     /*!< Sector Number 122 */

+#define FLASH_SECTOR_123           123U     /*!< Sector Number 123 */

+#define FLASH_SECTOR_124           124U     /*!< Sector Number 124 */

+#define FLASH_SECTOR_125           125U     /*!< Sector Number 125 */

+#define FLASH_SECTOR_126           126U     /*!< Sector Number 126 */

+#define FLASH_SECTOR_127           127U     /*!< Sector Number 127 */

+#endif /* FLASH_SECTOR_TOTAL == 128 */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup FLASH_Exported_Macros FLASH Exported Macros

+  * @{

+  */

+/**

+  * @brief  Set the FLASH Latency.

+  * @param  __LATENCY__: FLASH Latency

+  *         The value of this parameter depend on device used within the same series

+  * @retval none

+  */

+#define __HAL_FLASH_SET_LATENCY(__LATENCY__) \

+                  MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(__LATENCY__))

+

+/**

+  * @brief  Get the FLASH Latency.

+  * @retval FLASH Latency

+  *          The value of this parameter depend on device used within the same series

+  */

+#define __HAL_FLASH_GET_LATENCY()     (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))

+

+/**

+  * @brief  Enable the specified FLASH interrupt.

+  * @param  __INTERRUPT__ : FLASH interrupt

+  *   In case of Bank 1 This parameter can be any combination of the following values:

+  *     @arg FLASH_IT_EOP_BANK1       : End of FLASH Bank 1 Operation Interrupt source

+  *     @arg FLASH_IT_WRPERR_BANK1    : Write Protection Error on Bank 1 Interrupt source

+  *     @arg FLASH_IT_PGSERR_BANK1    : Program Sequence Error on Bank 1 Interrupt source

+  *     @arg FLASH_IT_STRBERR_BANK1   : Strobe Error on Bank 1 Interrupt source

+  *     @arg FLASH_IT_INCERR_BANK1    : Inconsistency Error on Bank 1 Interrupt source

+  *     @arg FLASH_IT_OPERR_BANK1     : Operation Error on Bank 1 Interrupt source

+  *     @arg FLASH_IT_RDPERR_BANK1    : Read protection Error on Bank 1 Interrupt source

+  *     @arg FLASH_IT_RDSERR_BANK1    : Read secure Error on Bank 1 Interrupt source

+  *     @arg FLASH_IT_SNECCERR_BANK1  : Single ECC Error Correction on Bank 1 Interrupt source

+  *     @arg FLASH_IT_DBECCERR_BANK1  : Double Detection ECC Error on Bank 1 Interrupt source

+  *     @arg FLASH_IT_CRCEND_BANK1    : CRC End on Bank 1 Interrupt source

+  *     @arg FLASH_IT_CRCRDERR_BANK1  : CRC Read error on Bank 1 Interrupt source

+  *     @arg FLASH_IT_ALL_BANK1       : All Bank 1 Interrupt sources

+  *

+  *   In case of Bank 2, this parameter can be any combination of the following values:

+  *     @arg FLASH_IT_EOP_BANK2       : End of FLASH Bank 2 Operation Interrupt source

+  *     @arg FLASH_IT_WRPERR_BANK2    : Write Protection Error on Bank 2 Interrupt source

+  *     @arg FLASH_IT_PGSERR_BANK2    : Program Sequence Error on Bank 2 Interrupt source

+  *     @arg FLASH_IT_STRBERR_BANK2   : Strobe Error on Bank 2 Interrupt source

+  *     @arg FLASH_IT_INCERR_BANK2    : Inconsistency Error on Bank 2 Interrupt source

+  *     @arg FLASH_IT_OPERR_BANK2     : Operation Error on Bank 2 Interrupt source

+  *     @arg FLASH_IT_RDPERR_BANK2    : Read protection Error on Bank 2 Interrupt source

+  *     @arg FLASH_IT_RDSERR_BANK2    : Read secure Error on Bank 2 Interrupt source

+  *     @arg FLASH_IT_SNECCERR_BANK2  : Single ECC Error Correction on Bank 2 Interrupt source

+  *     @arg FLASH_IT_DBECCERR_BANK2  : Double Detection ECC Error on Bank 2 Interrupt source

+  *     @arg FLASH_IT_CRCEND_BANK2    : CRC End on Bank 2 Interrupt source

+  *     @arg FLASH_IT_CRCRDERR_BANK2  : CRC Read error on Bank 2 Interrupt source

+  *     @arg FLASH_IT_ALL_BANK2       : All Bank 2 Interrupt sources

+  * @retval none

+  */

+

+#define __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__)      (FLASH->CR1 |= (__INTERRUPT__))

+

+#define __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__)      (FLASH->CR2 |= ((__INTERRUPT__) & 0x7FFFFFFFU))

+

+#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)    (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \

+                                                 __HAL_FLASH_ENABLE_IT_BANK1(__INTERRUPT__) : \

+                                                 __HAL_FLASH_ENABLE_IT_BANK2(__INTERRUPT__))

+

+

+/**

+  * @brief  Disable the specified FLASH interrupt.

+  * @param  __INTERRUPT__ : FLASH interrupt

+  *   In case of Bank 1 This parameter can be any combination of the following values:

+  *     @arg FLASH_IT_EOP_BANK1       : End of FLASH Bank 1 Operation Interrupt source

+  *     @arg FLASH_IT_WRPERR_BANK1    : Write Protection Error on Bank 1 Interrupt source

+  *     @arg FLASH_IT_PGSERR_BANK1    : Program Sequence Error on Bank 1 Interrupt source

+  *     @arg FLASH_IT_STRBERR_BANK1   : Strobe Error on Bank 1 Interrupt source

+  *     @arg FLASH_IT_INCERR_BANK1    : Inconsistency Error on Bank 1 Interrupt source

+  *     @arg FLASH_IT_OPERR_BANK1     : Operation Error on Bank 1 Interrupt source

+  *     @arg FLASH_IT_RDPERR_BANK1    : Read protection Error on Bank 1 Interrupt source

+  *     @arg FLASH_IT_RDSERR_BANK1    : Read secure Error on Bank 1 Interrupt source

+  *     @arg FLASH_IT_SNECCERR_BANK1  : Single ECC Error Correction on Bank 1 Interrupt source

+  *     @arg FLASH_IT_DBECCERR_BANK1  : Double Detection ECC Error on Bank 1 Interrupt source

+  *     @arg FLASH_IT_CRCEND_BANK1    : CRC End on Bank 1 Interrupt source

+  *     @arg FLASH_IT_CRCRDERR_BANK1  : CRC Read error on Bank 1 Interrupt source

+  *     @arg FLASH_IT_ALL_BANK1       : All Bank 1 Interrupt sources

+  *

+  *   In case of Bank 2, this parameter can be any combination of the following values:

+  *     @arg FLASH_IT_EOP_BANK2       : End of FLASH Bank 2 Operation Interrupt source

+  *     @arg FLASH_IT_WRPERR_BANK2    : Write Protection Error on Bank 2 Interrupt source

+  *     @arg FLASH_IT_PGSERR_BANK2    : Program Sequence Error on Bank 2 Interrupt source

+  *     @arg FLASH_IT_STRBERR_BANK2   : Strobe Error on Bank 2 Interrupt source

+  *     @arg FLASH_IT_INCERR_BANK2    : Inconsistency Error on Bank 2 Interrupt source

+  *     @arg FLASH_IT_OPERR_BANK2     : Operation Error on Bank 2 Interrupt source

+  *     @arg FLASH_IT_RDPERR_BANK2    : Read protection Error on Bank 2 Interrupt source

+  *     @arg FLASH_IT_RDSERR_BANK2    : Read secure Error on Bank 2 Interrupt source

+  *     @arg FLASH_IT_SNECCERR_BANK2  : Single ECC Error Correction on Bank 2 Interrupt source

+  *     @arg FLASH_IT_DBECCERR_BANK2  : Double Detection ECC Error on Bank 2 Interrupt source

+  *     @arg FLASH_IT_CRCEND_BANK2    : CRC End on Bank 2 Interrupt source

+  *     @arg FLASH_IT_CRCRDERR_BANK2  : CRC Read error on Bank 2 Interrupt source

+  *     @arg FLASH_IT_ALL_BANK2       : All Bank 2 Interrupt sources

+  * @retval none

+  */

+

+#define __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__)  (FLASH->CR1 &= ~(uint32_t)(__INTERRUPT__))

+

+#define __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__)  (FLASH->CR2 &= ~(uint32_t)((__INTERRUPT__) & 0x7FFFFFFFU))

+

+#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)  (IS_FLASH_IT_BANK1(__INTERRUPT__) ? \

+                                                __HAL_FLASH_DISABLE_IT_BANK1(__INTERRUPT__) : \

+                                                __HAL_FLASH_DISABLE_IT_BANK2(__INTERRUPT__))

+

+

+/**

+  * @brief  Checks whether the specified FLASH flag is set or not.

+  * @param  __FLAG__: specifies the FLASH flag to check.

+  *   In case of Bank 1 This parameter can be one of the following values :

+  *     @arg FLASH_FLAG_BSY_BANK1      : FLASH Bank 1 Busy flag

+  *     @arg FLASH_FLAG_WBNE_BANK1     : Write Buffer Not Empty on Bank 1 flag

+  *     @arg FLASH_FLAG_QW_BANK1       : Wait Queue on Bank 1 flag

+  *     @arg FLASH_FLAG_CRC_BUSY_BANK1 : CRC module is working on Bank 1 flag

+  *     @arg FLASH_FLAG_EOP_BANK1      : End Of Program on Bank 1 flag

+  *     @arg FLASH_FLAG_WRPERR_BANK1   : Write Protection Error on Bank 1 flag

+  *     @arg FLASH_FLAG_PGSERR_BANK1   : Program Sequence Error on Bank 1 flag

+  *     @arg FLASH_FLAG_STRBER_BANK1   : Program Alignment Error on Bank 1 flag

+  *     @arg FLASH_FLAG_INCERR_BANK1   : Inconsistency Error on Bank 1 flag

+  *     @arg FLASH_FLAG_OPERR_BANK1    : Operation Error on Bank 1 flag

+  *     @arg FLASH_FLAG_RDPERR_BANK1   : Read Protection Error on Bank 1 flag

+  *     @arg FLASH_FLAG_RDSERR_BANK1   : Read secure  Error on Bank 1 flag

+  *     @arg FLASH_FLAG_SNECCE_BANK1   : Single ECC Error Correction on Bank 1 flag

+  *     @arg FLASH_FLAG_DBECCE_BANK1   : Double Detection ECC Error on Bank 1 flag

+  *     @arg FLASH_FLAG_CRCEND_BANK1   : CRC End on Bank 1 flag

+  *     @arg FLASH_FLAG_CRCRDERR_BANK1 : CRC Read error on Bank 1 flag

+  *

+  *   In case of Bank 2 This parameter can be one of the following values :

+  *     @arg FLASH_FLAG_BSY_BANK2      : FLASH Bank 2 Busy flag

+  *     @arg FLASH_FLAG_WBNE_BANK2     : Write Buffer Not Empty on Bank 2 flag

+  *     @arg FLASH_FLAG_QW_BANK2       : Wait Queue on Bank 2 flag

+  *     @arg FLASH_FLAG_CRC_BUSY_BANK2 : CRC module is working on Bank 2 flag

+  *     @arg FLASH_FLAG_EOP_BANK2      : End Of Program on Bank 2 flag

+  *     @arg FLASH_FLAG_WRPERR_BANK2   : Write Protection Error on Bank 2 flag

+  *     @arg FLASH_FLAG_PGSERR_BANK2   : Program Sequence Error on Bank 2 flag

+  *     @arg FLASH_FLAG_STRBER_BANK2   : Program Alignment Error on Bank 2 flag

+  *     @arg FLASH_FLAG_INCERR_BANK2   : Inconsistency Error on Bank 2 flag

+  *     @arg FLASH_FLAG_OPERR_BANK2    : Operation Error on Bank 2 flag

+  *     @arg FLASH_FLAG_RDPERR_BANK2   : Read Protection Error on Bank 2 flag

+  *     @arg FLASH_FLAG_RDSERR_BANK2   : Read secure  Error on Bank 2 flag

+  *     @arg FLASH_FLAG_SNECCE_BANK2   : Single ECC Error Correction on Bank 2 flag

+  *     @arg FLASH_FLAG_DBECCE_BANK2   : Double Detection ECC Error on Bank 2 flag

+  *     @arg FLASH_FLAG_CRCEND_BANK2   : CRC End on Bank 2 flag

+  *     @arg FLASH_FLAG_CRCRDERR_BANK2 : CRC Read error on Bank 2 flag

+  * @retval The new state of FLASH_FLAG (SET or RESET).

+  */

+#define __HAL_FLASH_GET_FLAG_BANK1(__FLAG__)     (READ_BIT(FLASH->SR1, (__FLAG__)) == (__FLAG__))

+

+#define __HAL_FLASH_GET_FLAG_BANK2(__FLAG__)     (READ_BIT(FLASH->SR2, ((__FLAG__) & 0x7FFFFFFFU)) == (((__FLAG__) & 0x7FFFFFFFU)))

+

+#define __HAL_FLASH_GET_FLAG(__FLAG__)           (IS_FLASH_FLAG_BANK1(__FLAG__) ?  __HAL_FLASH_GET_FLAG_BANK1(__FLAG__) : \

+                                                  __HAL_FLASH_GET_FLAG_BANK2(__FLAG__))

+

+

+/**

+  * @brief  Clear the specified FLASH flag.

+  * @param  __FLAG__: specifies the FLASH flags to clear.

+  *    In case of Bank 1, this parameter can be any combination of the following values:

+  *     @arg FLASH_FLAG_EOP_BANK1        : End Of Program on Bank 1 flag

+  *     @arg FLASH_FLAG_WRPERR_BANK1     : Write Protection Error on Bank 1 flag

+  *     @arg FLASH_FLAG_PGSERR_BANK1     : Program Sequence Error on Bank 1 flag

+  *     @arg FLASH_FLAG_STRBER_BANK1     : Program Alignment Error on Bank 1 flag

+  *     @arg FLASH_FLAG_INCERR_BANK1     : Inconsistency Error on Bank 1 flag

+  *     @arg FLASH_FLAG_OPERR_BANK1      : Operation Error on Bank 1 flag

+  *     @arg FLASH_FLAG_RDPERR_BANK1     : Read Protection Error on Bank 1 flag

+  *     @arg FLASH_FLAG_RDSERR_BANK1     : Read secure  Error on Bank 1 flag

+  *     @arg FLASH_FLAG_SNECCE_BANK1     : Single ECC Error Correction on Bank 1 flag

+  *     @arg FLASH_FLAG_DBECCE_BANK1     : Double Detection ECC Error on Bank 1 flag

+  *     @arg FLASH_FLAG_CRCEND_BANK1     : CRC End on Bank 1 flag

+  *     @arg FLASH_FLAG_CRCRDERR_BANK1   : CRC Read error on Bank 1 flag

+  *     @arg FLASH_FLAG_ALL_ERRORS_BANK1 : All Bank 1 error flags

+  *     @arg FLASH_FLAG_ALL_BANK1        : All Bank 1 flags

+  *

+  *   In case of Bank 2, this parameter can be any combination of the following values :

+  *     @arg FLASH_FLAG_EOP_BANK2        : End Of Program on Bank 2 flag

+  *     @arg FLASH_FLAG_WRPERR_BANK2     : Write Protection Error on Bank 2 flag

+  *     @arg FLASH_FLAG_PGSERR_BANK2     : Program Sequence Error on Bank 2 flag

+  *     @arg FLASH_FLAG_STRBER_BANK2     : Program Alignment Error on Bank 2 flag

+  *     @arg FLASH_FLAG_INCERR_BANK2     : Inconsistency Error on Bank 2 flag

+  *     @arg FLASH_FLAG_OPERR_BANK2      : Operation Error on Bank 2 flag

+  *     @arg FLASH_FLAG_RDPERR_BANK2     : Read Protection Error on Bank 2 flag

+  *     @arg FLASH_FLAG_RDSERR_BANK2     : Read secure  Error on Bank 2 flag

+  *     @arg FLASH_FLAG_SNECCE_BANK2     : Single ECC Error Correction on Bank 2 flag

+  *     @arg FLASH_FLAG_DBECCE_BANK2     : Double Detection ECC Error on Bank 2 flag

+  *     @arg FLASH_FLAG_CRCEND_BANK2     : CRC End on Bank 2 flag

+  *     @arg FLASH_FLAG_CRCRDERR_BANK2   : CRC Read error on Bank 2 flag

+  *     @arg FLASH_FLAG_ALL_ERRORS_BANK2 : All Bank 2 error flags

+  *     @arg FLASH_FLAG_ALL_BANK2        : All Bank 2 flags

+  * @retval none

+  */

+

+#define __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__)    WRITE_REG(FLASH->CCR1, (__FLAG__))

+

+#define __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__)    WRITE_REG(FLASH->CCR2, ((__FLAG__) & 0x7FFFFFFFU))

+

+#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)         (IS_FLASH_FLAG_BANK1(__FLAG__) ?  __HAL_FLASH_CLEAR_FLAG_BANK1(__FLAG__) : \

+                                                   __HAL_FLASH_CLEAR_FLAG_BANK2(__FLAG__))

+

+/**

+  * @}

+  */

+

+/* Include FLASH HAL Extension module */

+#include "stm32h7xx_hal_flash_ex.h"

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup FLASH_Exported_Functions

+  * @{

+  */

+/** @addtogroup FLASH_Exported_Functions_Group1

+  * @{

+  */

+/* Program operation functions  ***********************************************/

+HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress);

+HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddress, uint32_t DataAddress);

+/* FLASH IRQ handler method */

+void HAL_FLASH_IRQHandler(void);

+/* Callbacks in non blocking modes */

+void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);

+void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue);

+/**

+  * @}

+  */

+

+/** @addtogroup FLASH_Exported_Functions_Group2

+  * @{

+  */

+/* Peripheral Control functions  **********************************************/

+HAL_StatusTypeDef HAL_FLASH_Unlock(void);

+HAL_StatusTypeDef HAL_FLASH_Lock(void);

+HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void);

+HAL_StatusTypeDef HAL_FLASH_OB_Lock(void);

+/* Option bytes control */

+HAL_StatusTypeDef HAL_FLASH_OB_Launch(void);

+/**

+  * @}

+  */

+

+/** @addtogroup FLASH_Exported_Functions_Group3

+  * @{

+  */

+/* Peripheral State functions  ************************************************/

+uint32_t HAL_FLASH_GetError(void);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/** @defgroup FLASH_Private_Variables FLASH Private Variables

+  * @{

+  */

+extern FLASH_ProcessTypeDef pFlash;

+/**

+  * @}

+  */

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup FLASH_Private_Constants FLASH Private Constants

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup FLASH_Private_Macros FLASH Private Macros

+  * @{

+  */

+

+#if defined (FLASH_OPTCR_PG_OTP)

+#define IS_FLASH_TYPEPROGRAM(VALUE)      (((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD) || \

+                                          ((VALUE) == FLASH_TYPEPROGRAM_OTPWORD))

+#else

+#define IS_FLASH_TYPEPROGRAM(VALUE)      ((VALUE) == FLASH_TYPEPROGRAM_FLASHWORD)

+#endif /* FLASH_OPTCR_PG_OTP */

+

+#define IS_FLASH_IT_BANK1(IT)            (((IT) & FLASH_IT_ALL_BANK1) == (IT))

+

+#define IS_FLASH_IT_BANK2(IT)            (((IT) & FLASH_IT_ALL_BANK2) == (IT))

+

+#define IS_FLASH_FLAG_BANK1(FLAG)        (((FLAG) & FLASH_FLAG_ALL_BANK1) == (FLAG))

+

+#define IS_FLASH_FLAG_BANK2(FLAG)        (((FLAG) & FLASH_FLAG_ALL_BANK2) == (FLAG))

+

+#define IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) (((ADDRESS) >= FLASH_BANK1_BASE) && ((ADDRESS) < FLASH_BANK2_BASE))

+#define IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) (((ADDRESS) >= FLASH_BANK2_BASE ) && ((ADDRESS) <= FLASH_END))

+

+#if defined (FLASH_OPTCR_PG_OTP)

+#define IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS)   (((ADDRESS) >= 0x08FFF000U) && ((ADDRESS) <= 0x08FFF3FFU))

+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)       (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \

+                                                 IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS) || \

+                                                 IS_FLASH_PROGRAM_ADDRESS_OTP(ADDRESS))

+#else

+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS)       (IS_FLASH_PROGRAM_ADDRESS_BANK1(ADDRESS) || \

+                                                 IS_FLASH_PROGRAM_ADDRESS_BANK2(ADDRESS))

+#endif /* FLASH_OPTCR_PG_OTP */

+

+#define IS_BOOT_ADDRESS(ADDRESS)           ((ADDRESS) <= (0x3FFF0000U))

+

+#define IS_FLASH_BANK(BANK)                (((BANK) == FLASH_BANK_1)  || \

+                                            ((BANK) == FLASH_BANK_2)  || \

+                                            ((BANK) == FLASH_BANK_BOTH))

+

+#define IS_FLASH_BANK_EXCLUSIVE(BANK)      (((BANK) == FLASH_BANK_1)  || \

+                                            ((BANK) == FLASH_BANK_2))

+

+

+/**

+  * @}

+  */

+/* Private functions ---------------------------------------------------------*/

+/** @defgroup FLASH_Private_Functions FLASH Private functions

+  * @{

+  */

+HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout, uint32_t Bank);

+HAL_StatusTypeDef FLASH_OB_WaitForLastOperation(uint32_t Timeout);

+HAL_StatusTypeDef FLASH_CRC_WaitForLastOperation(uint32_t Timeout, uint32_t Bank);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_FLASH_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_flash_ex.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_flash_ex.h
new file mode 100644
index 0000000000..834c5d23fb
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_flash_ex.h
@@ -0,0 +1,910 @@
+/**

+  ******************************************************************************

+  * @file    stm32H7xx_hal_flash_ex.h

+  * @author  MCD Application Team

+  * @brief   Header file of FLASH HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                       opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_FLASH_EX_H

+#define STM32H7xx_HAL_FLASH_EX_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup FLASHEx

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup FLASHEx_Exported_Types FLASH Exported Types

+  * @{

+  */

+

+/**

+  * @brief  FLASH Erase structure definition

+  */

+typedef struct

+{

+  uint32_t TypeErase;   /*!< Mass erase or sector Erase.

+                             This parameter can be a value of @ref FLASHEx_Type_Erase */

+

+  uint32_t Banks;       /*!< Select banks to erase when Mass erase is enabled.

+                             This parameter must be a value of @ref FLASHEx_Banks */

+

+  uint32_t Sector;      /*!< Initial FLASH sector to erase when Mass erase is disabled

+                             This parameter must be a value of @ref FLASH_Sectors */

+

+  uint32_t NbSectors;   /*!< Number of sectors to be erased.

+                             This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/

+

+  uint32_t VoltageRange;/*!< The device voltage range which defines the erase parallelism

+                             This parameter must be a value of @ref FLASHEx_Voltage_Range */

+

+} FLASH_EraseInitTypeDef;

+

+

+/**

+  * @brief  FLASH Option Bytes Program structure definition

+  */

+typedef struct

+{

+  uint32_t OptionType;     /*!< Option byte to be configured.

+                                This parameter can be a value of @ref FLASHEx_Option_Type */

+

+  uint32_t WRPState;       /*!< Write protection activation or deactivation.

+                                This parameter can be a value of @ref FLASHEx_WRP_State */

+

+  uint32_t WRPSector;      /*!< Specifies the sector(s) to be write protected.

+                                The value of this parameter depend on device used within the same series */

+

+  uint32_t RDPLevel;       /*!< Set the read protection level.

+                                This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */

+

+  uint32_t BORLevel;       /*!< Set the BOR Level.

+                                This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */

+

+  uint32_t USERType;       /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER).

+                                This parameter can be a combination of @ref FLASHEx_OB_USER_Type */

+

+  uint32_t USERConfig;     /*!< Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY /

+                                IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / IO_HSLV / SWAP_BANK_OPT */

+

+  uint32_t Banks;          /*!< Select banks for WRP , PCROP and secure area config .

+                                This parameter must be a value of @ref FLASHEx_Banks */

+

+  uint32_t PCROPConfig;    /*!< specifies if the PCROP area shall be erased or not

+                                when RDP level decreased from Level 1 to Level 0 or during a mass erase.

+                                This parameter must be a value of @ref FLASHEx_OB_PCROP_RDP enumeration */

+

+  uint32_t PCROPStartAddr; /*!< PCROP Start address (used for OPTIONBYTE_PCROP).

+                                This parameter must be a value between begin and end of a bank */

+

+  uint32_t PCROPEndAddr;   /*!< PCROP End address (used for OPTIONBYTE_PCROP).

+                                This parameter must be a value between PCROP Start address and end of a bank */

+

+  uint32_t BootConfig;     /*!< Specifies if the Boot Address to be configured BOOT_ADD0, BOOT_ADD1

+                                or both. This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */

+

+  uint32_t BootAddr0;      /*!< Boot Address 0.

+                                This parameter must be a value between begin and end of a bank */

+

+  uint32_t BootAddr1;      /*!< Boot Address 1.

+                                This parameter must be a value between begin and end of a bank */

+#if defined(DUAL_CORE)

+  uint32_t CM4BootConfig;  /*!< specifies if the CM4 boot Address to be configured BOOT_ADD0, BOOT_ADD1

+                                or both.

+                                This parameter must be a value of @ref FLASHEx_OB_BOOT_OPTION enumeration */

+

+  uint32_t CM4BootAddr0;   /*!< CM4 Boot Address 0.

+                                This parameter must be a value between begin and end of a bank */

+

+  uint32_t CM4BootAddr1;   /*!< CM4 Boot Address 1.

+                                This parameter must be a value between begin and end of a bank */

+#endif /*DUAL_CORE*/

+

+  uint32_t SecureAreaConfig;    /*!< specifies if the bank secured area shall be erased or not

+                                     when RDP level decreased from Level 1 to Level 0 or during a mass erase.

+                                     This parameter must be a value of @ref FLASHEx_OB_SECURE_RDP enumeration */

+

+  uint32_t SecureAreaStartAddr; /*!< Bank Secure area Start address.

+                                     This parameter must be a value between begin address and end address of bank1 */

+

+  uint32_t SecureAreaEndAddr;   /*!< Bank Secure area End address.

+                                     This parameter must be a value between Secure Area Start address and end address of a bank1 */

+

+#if defined (FLASH_OTPBL_LOCKBL)

+  uint32_t OTPBlockLock;   /*!< Specifies the OTP block(s) to be locked.

+                                This parameter must be a value of @ref FLASHEx_OTP_Blocks */

+#endif /* FLASH_OTPBL_LOCKBL */

+

+} FLASH_OBProgramInitTypeDef;

+

+/**

+  * @brief  FLASH Erase structure definition

+  */

+typedef struct

+{

+  uint32_t TypeCRC;      /*!< CRC Selection Type.

+                              This parameter can be a value of @ref FLASHEx_CRC_Selection_Type */

+

+  uint32_t BurstSize;    /*!< CRC Burst Size.

+                              This parameter can be a value of @ref FLASHEx_CRC_Burst_Size */

+

+  uint32_t Bank;         /*!< Select bank where CRC computation is enabled.

+                              This parameter must be FLASH_BANK_1 or FLASH_BANK_2 */

+

+  uint32_t Sector;       /*!< Initial FLASH sector from which starts the CRC computation

+                              This parameter must be a value of @ref FLASH_Sectors */

+

+  uint32_t NbSectors;    /*!< Number of sectors to be computed.

+                              This parameter must be a value between 1 and (max number of sectors - value of Initial sector)*/

+

+  uint32_t CRCStartAddr; /*!< CRC Start address.

+                              This parameter must be a value between begin address and end address of a bank */

+

+  uint32_t CRCEndAddr;   /*!< CRC End address.

+                              This parameter must be a value between CRC Start address and end address of a bank */

+

+} FLASH_CRCInitTypeDef;

+

+/**

+  * @}

+  */

+/* Exported constants --------------------------------------------------------*/

+

+/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants

+  * @{

+  */

+

+/** @defgroup FLASHEx_Type_Erase FLASH Type Erase

+  * @{

+  */

+#define FLASH_TYPEERASE_SECTORS      0x00U  /*!< Sectors erase only          */

+#define FLASH_TYPEERASE_MASSERASE    0x01U  /*!< Flash Mass erase activation */

+/**

+  * @}

+  */

+

+#if defined (FLASH_CR_PSIZE)

+/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range

+  * @{

+  */

+#define FLASH_VOLTAGE_RANGE_1        0x00000000U       /*!< Flash program/erase by 8 bits  */

+#define FLASH_VOLTAGE_RANGE_2        FLASH_CR_PSIZE_0  /*!< Flash program/erase by 16 bits */

+#define FLASH_VOLTAGE_RANGE_3        FLASH_CR_PSIZE_1  /*!< Flash program/erase by 32 bits */

+#define FLASH_VOLTAGE_RANGE_4        FLASH_CR_PSIZE    /*!< Flash program/erase by 64 bits */

+/**

+  * @}

+  */

+#endif /* FLASH_CR_PSIZE */

+

+/** @defgroup FLASHEx_WRP_State FLASH WRP State

+  * @{

+  */

+#define OB_WRPSTATE_DISABLE          0x00000000U  /*!< Disable the write protection of the desired bank 1 sectors */

+#define OB_WRPSTATE_ENABLE           0x00000001U  /*!< Enable the write protection of the desired bank 1 sectors  */

+/**

+  * @}

+  */

+

+/** @defgroup FLASHEx_Option_Type FLASH Option Type

+  * @{

+  */

+#define OPTIONBYTE_WRP           0x01U  /*!< WRP option byte configuration  */

+#define OPTIONBYTE_RDP           0x02U  /*!< RDP option byte configuration  */

+#define OPTIONBYTE_USER          0x04U  /*!< USER option byte configuration */

+#define OPTIONBYTE_PCROP         0x08U  /*!< PCROP option byte configuration */

+#define OPTIONBYTE_BOR           0x10U  /*!< BOR option byte configuration */

+#define OPTIONBYTE_SECURE_AREA   0x20U  /*!< secure area option byte configuration */

+#if defined (DUAL_CORE)

+#define OPTIONBYTE_CM7_BOOTADD   0x40U  /*!< CM7 BOOT ADD option byte configuration */

+#define OPTIONBYTE_CM4_BOOTADD   0x80U  /*!< CM4 BOOT ADD option byte configuration */

+#define OPTIONBYTE_BOOTADD       OPTIONBYTE_CM7_BOOTADD  /*!< BOOT ADD option byte configuration */

+#else /* Single core */

+#define OPTIONBYTE_BOOTADD       0x40U  /*!< BOOT ADD option byte configuration */

+#endif /*DUAL_CORE*/

+#if defined (FLASH_OTPBL_LOCKBL)

+#define OPTIONBYTE_OTP_LOCK      0x80U  /*!< OTP Lock option byte configuration */

+#endif /* FLASH_OTPBL_LOCKBL */

+/**

+  * @}

+  */

+

+/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection

+  * @{

+  */

+#define OB_RDP_LEVEL_0       0xAA00U

+#define OB_RDP_LEVEL_1       0x5500U

+#define OB_RDP_LEVEL_2       0xCC00U   /*!< Warning: When enabling read protection level 2

+                                            it s no more possible to go back to level 1 or 0 */

+/**

+  * @}

+  */

+

+/** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog

+  * @{

+  */

+#define OB_WWDG_SW           0x10U  /*!< Software WWDG selected */

+#define OB_WWDG_HW           0x00U  /*!< Hardware WWDG selected */

+/**

+  * @}

+  */

+

+

+/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog

+  * @{

+  */

+#define OB_IWDG_SW           0x20U  /*!< Software IWDG selected */

+#define OB_IWDG_HW           0x00U  /*!< Hardware IWDG selected */

+/**

+  * @}

+  */

+

+/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP

+  * @{

+  */

+#define OB_STOP_NO_RST       0x40U /*!< No reset generated when entering in STOP */

+#define OB_STOP_RST          0x00U /*!< Reset generated when entering in STOP    */

+/**

+  * @}

+  */

+

+/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY

+  * @{

+  */

+#define OB_STDBY_NO_RST      0x80U /*!< No reset generated when entering in STANDBY */

+#define OB_STDBY_RST         0x00U /*!< Reset generated when entering in STANDBY    */

+/**

+  * @}

+  */

+

+/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP

+  * @{

+  */

+#define OB_IWDG_STOP_FREEZE  0x00000000U /*!< Freeze IWDG counter in STOP mode */

+#define OB_IWDG_STOP_ACTIVE  FLASH_OPTSR_FZ_IWDG_STOP /*!< IWDG counter active in STOP mode */

+/**

+  * @}

+  */

+

+/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY

+  * @{

+  */

+#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Freeze IWDG counter in STANDBY mode */

+#define OB_IWDG_STDBY_ACTIVE FLASH_OPTSR_FZ_IWDG_SDBY  /*!< IWDG counter active in STANDBY mode */

+/**

+  * @}

+  */

+

+/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level

+  * @{

+  */

+#define OB_BOR_LEVEL0        0x00000000U                /*!< Reset level threshold is set to 1.6V */

+#define OB_BOR_LEVEL1        FLASH_OPTSR_BOR_LEV_0      /*!< Reset level threshold is set to 2.1V */

+#define OB_BOR_LEVEL2        FLASH_OPTSR_BOR_LEV_1      /*!< Reset level threshold is set to 2.4V */

+#define OB_BOR_LEVEL3        (FLASH_OPTSR_BOR_LEV_1 | FLASH_OPTSR_BOR_LEV_0) /*!< Reset level threshold is set to 2.7V  */

+/**

+  * @}

+  */

+

+

+

+/** @defgroup FLASHEx_Boot_Address FLASH Boot Address

+  * @{

+  */

+#define OB_BOOTADDR_ITCM_RAM     0x0000U  /*!< Boot from ITCM RAM (0x00000000)                 */

+#define OB_BOOTADDR_SYSTEM       0x0040U  /*!< Boot from System memory bootloader (0x00100000) */

+#define OB_BOOTADDR_ITCM_FLASH   0x0080U  /*!< Boot from Flash on ITCM interface (0x00200000)  */

+#define OB_BOOTADDR_AXIM_FLASH   0x2000U  /*!< Boot from Flash on AXIM interface (0x08000000)  */

+#define OB_BOOTADDR_DTCM_RAM     0x8000U  /*!< Boot from DTCM RAM (0x20000000)                 */

+#define OB_BOOTADDR_SRAM1        0x8004U  /*!< Boot from SRAM1 (0x20010000)                    */

+#define OB_BOOTADDR_SRAM2        0x8013U  /*!< Boot from SRAM2 (0x2004C000)                    */

+/**

+  * @}

+  */

+

+/** @defgroup FLASH_Latency FLASH Latency

+  * @{

+  */

+#define FLASH_LATENCY_0          FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero Latency cycle      */

+#define FLASH_LATENCY_1          FLASH_ACR_LATENCY_1WS   /*!< FLASH One Latency cycle       */

+#define FLASH_LATENCY_2          FLASH_ACR_LATENCY_2WS   /*!< FLASH Two Latency cycles      */

+#define FLASH_LATENCY_3          FLASH_ACR_LATENCY_3WS   /*!< FLASH Three Latency cycles    */

+#define FLASH_LATENCY_4          FLASH_ACR_LATENCY_4WS   /*!< FLASH Four Latency cycles     */

+#define FLASH_LATENCY_5          FLASH_ACR_LATENCY_5WS   /*!< FLASH Five Latency cycles     */

+#define FLASH_LATENCY_6          FLASH_ACR_LATENCY_6WS   /*!< FLASH Six Latency cycles      */

+#define FLASH_LATENCY_7          FLASH_ACR_LATENCY_7WS   /*!< FLASH Seven Latency cycles    */

+#define FLASH_LATENCY_8          FLASH_ACR_LATENCY_8WS   /*!< FLASH Eight Latency cycle     */

+#define FLASH_LATENCY_9          FLASH_ACR_LATENCY_9WS   /*!< FLASH Nine Latency cycle      */

+#define FLASH_LATENCY_10         FLASH_ACR_LATENCY_10WS  /*!< FLASH Ten Latency cycles      */

+#define FLASH_LATENCY_11         FLASH_ACR_LATENCY_11WS  /*!< FLASH Eleven Latency cycles   */

+#define FLASH_LATENCY_12         FLASH_ACR_LATENCY_12WS  /*!< FLASH Twelve Latency cycles   */

+#define FLASH_LATENCY_13         FLASH_ACR_LATENCY_13WS  /*!< FLASH Thirteen Latency cycles */

+#define FLASH_LATENCY_14         FLASH_ACR_LATENCY_14WS  /*!< FLASH Fourteen Latency cycles */

+#define FLASH_LATENCY_15         FLASH_ACR_LATENCY_15WS  /*!< FLASH Fifteen Latency cycles  */

+/**

+  * @}

+  */

+

+/** @defgroup FLASHEx_Banks FLASH Banks

+  * @{

+  */

+#define FLASH_BANK_1             0x01U                         /*!< Bank 1   */

+#define FLASH_BANK_2             0x02U                         /*!< Bank 2   */

+#define FLASH_BANK_BOTH          (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2  */

+/**

+  * @}

+  */

+

+/** @defgroup FLASHEx_OB_PCROP_RDP  FLASHEx OB PCROP RDP

+  * @{

+  */

+#define OB_PCROP_RDP_NOT_ERASE   0x00000000U     /*!< PCROP area is not erased when the RDP level

+                                                      is decreased from Level 1 to Level 0 or during a mass erase */

+#define OB_PCROP_RDP_ERASE       FLASH_PRAR_DMEP /*!< PCROP area is erased when the RDP level is

+                                                      decreased from Level 1 to Level 0 (full mass erase) */

+

+/**

+  * @}

+  */

+

+/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection

+  * @{

+  */

+#if (FLASH_SECTOR_TOTAL == 128)

+#define OB_WRP_SECTOR_0TO3       0x00000001U /*!< Write protection of Sector0  to Sector3    */

+#define OB_WRP_SECTOR_4TO7       0x00000002U /*!< Write protection of Sector4  to Sector7    */

+#define OB_WRP_SECTOR_8TO11      0x00000004U /*!< Write protection of Sector8  to Sector11   */

+#define OB_WRP_SECTOR_12TO15     0x00000008U /*!< Write protection of Sector12 to Sector15   */

+#define OB_WRP_SECTOR_16TO19     0x00000010U /*!< Write protection of Sector16 to Sector19   */

+#define OB_WRP_SECTOR_20TO23     0x00000020U /*!< Write protection of Sector20 to Sector23   */

+#define OB_WRP_SECTOR_24TO27     0x00000040U /*!< Write protection of Sector24 to Sector27   */

+#define OB_WRP_SECTOR_28TO31     0x00000080U /*!< Write protection of Sector28 to Sector31   */

+#define OB_WRP_SECTOR_32TO35     0x00000100U /*!< Write protection of Sector32 to Sector35   */

+#define OB_WRP_SECTOR_36TO39     0x00000200U /*!< Write protection of Sector36 to Sector39   */

+#define OB_WRP_SECTOR_40TO43     0x00000400U /*!< Write protection of Sector40 to Sector43   */

+#define OB_WRP_SECTOR_44TO47     0x00000800U /*!< Write protection of Sector44 to Sector47   */

+#define OB_WRP_SECTOR_48TO51     0x00001000U /*!< Write protection of Sector48 to Sector51   */

+#define OB_WRP_SECTOR_52TO55     0x00002000U /*!< Write protection of Sector52 to Sector55   */

+#define OB_WRP_SECTOR_56TO59     0x00004000U /*!< Write protection of Sector56 to Sector59   */

+#define OB_WRP_SECTOR_60TO63     0x00008000U /*!< Write protection of Sector60 to Sector63   */

+#define OB_WRP_SECTOR_64TO67     0x00010000U /*!< Write protection of Sector64 to Sector67   */

+#define OB_WRP_SECTOR_68TO71     0x00020000U /*!< Write protection of Sector68 to Sector71   */

+#define OB_WRP_SECTOR_72TO75     0x00040000U /*!< Write protection of Sector72 to Sector75   */

+#define OB_WRP_SECTOR_76TO79     0x00080000U /*!< Write protection of Sector76 to Sector79   */

+#define OB_WRP_SECTOR_80TO83     0x00100000U /*!< Write protection of Sector80 to Sector83   */

+#define OB_WRP_SECTOR_84TO87     0x00200000U /*!< Write protection of Sector84 to Sector87   */

+#define OB_WRP_SECTOR_88TO91     0x00400000U /*!< Write protection of Sector88 to Sector91   */

+#define OB_WRP_SECTOR_92TO95     0x00800000U /*!< Write protection of Sector92 to Sector95   */

+#define OB_WRP_SECTOR_96TO99     0x01000000U /*!< Write protection of Sector96  to Sector99  */

+#define OB_WRP_SECTOR_100TO103   0x02000000U /*!< Write protection of Sector100 to Sector103 */

+#define OB_WRP_SECTOR_104TO107   0x04000000U /*!< Write protection of Sector104 to Sector107 */

+#define OB_WRP_SECTOR_108TO111   0x08000000U /*!< Write protection of Sector108 to Sector111 */

+#define OB_WRP_SECTOR_112TO115   0x10000000U /*!< Write protection of Sector112 to Sector115 */

+#define OB_WRP_SECTOR_116TO119   0x20000000U /*!< Write protection of Sector116 to Sector119 */

+#define OB_WRP_SECTOR_120TO123   0x40000000U /*!< Write protection of Sector120 to Sector123 */

+#define OB_WRP_SECTOR_124TO127   0x80000000U /*!< Write protection of Sector124 to Sector127 */

+#define OB_WRP_SECTOR_ALL        0xFFFFFFFFU /*!< Write protection of all Sectors            */

+#else

+#define OB_WRP_SECTOR_0          0x00000001U /*!< Write protection of Sector0                */

+#define OB_WRP_SECTOR_1          0x00000002U /*!< Write protection of Sector1                */

+#define OB_WRP_SECTOR_2          0x00000004U /*!< Write protection of Sector2                */

+#define OB_WRP_SECTOR_3          0x00000008U /*!< Write protection of Sector3                */

+#define OB_WRP_SECTOR_4          0x00000010U /*!< Write protection of Sector4                */

+#define OB_WRP_SECTOR_5          0x00000020U /*!< Write protection of Sector5                */

+#define OB_WRP_SECTOR_6          0x00000040U /*!< Write protection of Sector6                */

+#define OB_WRP_SECTOR_7          0x00000080U /*!< Write protection of Sector7                */

+#define OB_WRP_SECTOR_ALL        0x000000FFU /*!< Write protection of all Sectors            */

+#endif /* FLASH_SECTOR_TOTAL == 128 */

+/**

+  * @}

+  */

+

+/** @defgroup FLASHEx_OB_SECURITY  FLASHEx OB SECURITY

+  * @{

+  */

+#define OB_SECURITY_DISABLE   0x00000000U             /*!< security enabled */

+#define OB_SECURITY_ENABLE    FLASH_OPTSR_SECURITY    /*!< security disabled */

+/**

+  * @}

+  */

+

+/** @defgroup FLASHEx_OB_ST_RAM_SIZE  FLASHEx OB ST RAM SIZE

+  * @{

+  */

+#define OB_ST_RAM_SIZE_2KB    0x00000000U               /*!< 2 Kbytes reserved to ST code */

+#define OB_ST_RAM_SIZE_4KB    FLASH_OPTSR_ST_RAM_SIZE_0 /*!< 4 Kbytes reserved to ST code */

+#define OB_ST_RAM_SIZE_8KB    FLASH_OPTSR_ST_RAM_SIZE_1 /*!< 8 Kbytes reserved to ST code */

+#define OB_ST_RAM_SIZE_16KB   FLASH_OPTSR_ST_RAM_SIZE   /*!< 16 Kbytes reserved to ST code */

+/**

+  * @}

+  */

+

+#if defined(DUAL_CORE)

+/** @defgroup FLASHEx_OB_BCM7  FLASHEx OB BCM7

+  * @{

+  */

+#define OB_BCM7_DISABLE       0x00000000U              /*!< CM7 Boot disabled */

+#define OB_BCM7_ENABLE        FLASH_OPTSR_BCM7         /*!< CM7 Boot enabled */

+

+/**

+  * @}

+  */

+

+/** @defgroup FLASHEx_OB_BCM4  FLASHEx OB BCM4

+  * @{

+  */

+#define OB_BCM4_DISABLE       0x00000000U              /*!< CM4 Boot disabled */

+#define OB_BCM4_ENABLE        FLASH_OPTSR_BCM4         /*!< CM4 Boot enabled */

+/**

+  * @}

+  */

+#endif /* DUAL_CORE */

+

+/** @defgroup FLASHEx_OB_IWDG1_SW  FLASHEx OB IWDG1 SW

+  * @{

+  */

+#define OB_IWDG1_SW            FLASH_OPTSR_IWDG1_SW /*!< Hardware independent watchdog 1 */

+#define OB_IWDG1_HW            0x00000000U          /*!< Software independent watchdog 1 */

+/**

+  * @}

+  */

+

+#if defined(DUAL_CORE)

+/** @defgroup FLASHEx_OB_IWDG2_SW  FLASHEx OB IWDG2 SW

+  * @{

+  */

+#define OB_IWDG2_SW            FLASH_OPTSR_IWDG2_SW  /*!< Hardware independent watchdog 2*/

+#define OB_IWDG2_HW            0x00000000U           /*!< Software independent watchdog 2*/

+/**

+  * @}

+  */

+#endif

+

+/** @defgroup FLASHEx_OB_NRST_STOP_D1  FLASHEx OB NRST STOP D1

+  * @{

+  */

+#define OB_STOP_RST_D1         0x00000000U              /*!< Reset generated when entering the D1 to stop mode */

+#define OB_STOP_NO_RST_D1      FLASH_OPTSR_NRST_STOP_D1 /*!< No reset generated when entering the D1 to stop mode */

+/**

+  * @}

+  */

+

+/** @defgroup FLASHEx_OB_NRST_STDBY_D1  FLASHEx OB NRST STDBY D1

+  * @{

+  */

+#define OB_STDBY_RST_D1        0x00000000U              /*!< Reset generated when entering the D1 to standby mode */

+#define OB_STDBY_NO_RST_D1     FLASH_OPTSR_NRST_STBY_D1 /*!< No reset generated when entering the D1 to standby mode */

+/**

+  * @}

+  */

+

+#if defined (DUAL_CORE)

+/** @defgroup FLASHEx_OB_NRST_STOP_D2  FLASHEx OB NRST STOP D2

+  * @{

+  */

+#define OB_STOP_RST_D2         0x00000000U              /*!< Reset generated when entering the D2 to stop mode */

+#define OB_STOP_NO_RST_D2      FLASH_OPTSR_NRST_STOP_D2 /*!< No reset generated when entering the D2 to stop mode */

+/**

+  * @}

+  */

+

+/** @defgroup FLASHEx_OB_NRST_STDBY_D2  FLASHEx OB NRST STDBY D2

+  * @{

+  */

+#define OB_STDBY_RST_D2        0x00000000U              /*!< Reset generated when entering the D2 to standby mode */

+#define OB_STDBY_NO_RST_D2     FLASH_OPTSR_NRST_STBY_D2 /*!< No reset generated when entering the D2 to standby mode */

+/**

+  * @}

+  */

+#endif /* DUAL_CORE */

+

+/** @defgroup FLASHEx_OB_SWAP_BANK  FLASHEx OB SWAP BANK

+  * @{

+  */

+#define OB_SWAP_BANK_DISABLE   0x00000000U               /*!< Bank swap disabled */

+#define OB_SWAP_BANK_ENABLE    FLASH_OPTSR_SWAP_BANK_OPT /*!< Bank swap enabled */

+/**

+  * @}

+  */

+

+/** @defgroup FLASHEx_OB_IOHSLV FLASHEx OB IOHSLV

+  * @{

+  */

+#define OB_IOHSLV_DISABLE      0x00000000U         /*!< IOHSLV disabled */

+#define OB_IOHSLV_ENABLE       FLASH_OPTSR_IO_HSLV /*!< IOHSLV enabled */

+/**

+  * @}

+  */

+

+#if defined (FLASH_OPTSR_VDDMMC_HSLV)

+/** @defgroup FLASHEx_OB_VDDMMC_HSLV FLASHEx OB VDDMMC HSLV

+  * @{

+  */

+#define OB_VDDMMC_HSLV_DISABLE 0x00000000U             /*!< VDDMMC HSLV disabled */

+#define OB_VDDMMC_HSLV_ENABLE  FLASH_OPTSR_VDDMMC_HSLV /*!< VDDMMC HSLV enabled */

+/**

+  * @}

+  */

+#endif /* FLASH_OPTSR_VDDMMC_HSLV */

+

+/** @defgroup FLASHEx_OB_BOOT_OPTION  FLASHEx OB BOOT OPTION

+  * @{

+  */

+#define OB_BOOT_ADD0           0x01U       /*!< Select Boot Address 0 */

+#define OB_BOOT_ADD1           0x02U       /*!< Select Boot Address 1 */

+#define OB_BOOT_ADD_BOTH       0x03U       /*!< Select Boot Address 0 and 1 */

+/**

+  * @}

+  */

+

+ /** @defgroup FLASHEx_OB_USER_Type  FLASHEx OB USER Type

+  * @{

+  */

+#define OB_USER_IWDG1_SW          0x0001U /*!< Independent watchdog selection */

+#define OB_USER_NRST_STOP_D1      0x0002U /*!< Reset when entering Stop mode selection*/

+#define OB_USER_NRST_STDBY_D1     0x0004U /*!< Reset when entering standby mode selection*/

+#define OB_USER_IWDG_STOP         0x0008U /*!< Independent watchdog counter freeze in stop mode */

+#define OB_USER_IWDG_STDBY        0x0010U /*!< Independent watchdog counter freeze in standby mode */

+#define OB_USER_ST_RAM_SIZE       0x0020U /*!< dedicated DTCM Ram size selection */

+#define OB_USER_SECURITY          0x0040U /*!< security selection */

+#define OB_USER_IOHSLV            0x0080U /*!< IO HSLV selection */

+#define OB_USER_SWAP_BANK         0x0100U /*!< Bank swap selection */

+#if defined (FLASH_OPTSR_VDDMMC_HSLV)

+#define OB_USER_VDDMMC_HSLV       0x0200U /*!< VDDMMC HSLV selection */

+#endif /* FLASH_OPTSR_VDDMMC_HSLV */

+#if defined (DUAL_CORE)

+#define OB_USER_IWDG2_SW          0x0200U /*!< Window watchdog selection */

+#define OB_USER_BCM4              0x0400U /*!< CM4 boot selection */

+#define OB_USER_BCM7              0x0800U /*!< CM7 boot selection */

+#define OB_USER_NRST_STOP_D2      0x1000U /*!< Reset when entering Stop mode selection*/

+#define OB_USER_NRST_STDBY_D2     0x2000U /*!< Reset when entering standby mode selection*/

+#endif /*DUAL_CORE*/

+

+/**

+  * @}

+  */

+

+/** @defgroup FLASHEx_OB_SECURE_RDP  FLASHEx OB SECURE RDP

+  * @{

+  */

+#define OB_SECURE_RDP_NOT_ERASE   0x00000000U     /*!< Secure area is not erased when the RDP level

+                                                       is decreased from Level 1 to Level 0 or during a mass erase */

+#define OB_SECURE_RDP_ERASE       FLASH_SCAR_DMES /*!< Secure area is erased when the RDP level is

+                                                       decreased from Level 1 to Level 0 (full mass erase) */

+/**

+  * @}

+  */

+

+/** @defgroup FLASHEx_CRC_Selection_Type FLASH CRC Selection Type

+  * @{

+  */

+#define FLASH_CRC_ADDR         0x00000000U              /*!< CRC selection type by address  */

+#define FLASH_CRC_SECTORS      FLASH_CRCCR_CRC_BY_SECT  /*!< CRC selection type by sectors  */

+#define FLASH_CRC_BANK         (FLASH_CRCCR_ALL_BANK | FLASH_CRCCR_CRC_BY_SECT) /*!< CRC selection type by bank */

+/**

+  * @}

+  */

+

+/** @defgroup FLASHEx_CRC_Burst_Size FLASH CRC Burst Size

+  * @{

+  */

+#define FLASH_CRC_BURST_SIZE_4    0x00000000U              /*!< Every burst has a size of 4 Flash words (256-bit)  */

+#define FLASH_CRC_BURST_SIZE_16   FLASH_CRCCR_CRC_BURST_0  /*!< Every burst has a size of 16 Flash words (256-bit)   */

+#define FLASH_CRC_BURST_SIZE_64   FLASH_CRCCR_CRC_BURST_1  /*!< Every burst has a size of 64 Flash words (256-bit)   */

+#define FLASH_CRC_BURST_SIZE_256  FLASH_CRCCR_CRC_BURST    /*!< Every burst has a size of 256 Flash words (256-bit) */

+/**

+  * @}

+  */

+

+/** @defgroup FLASHEx_Programming_Delay FLASH Programming Delay

+  * @{

+  */

+#define FLASH_PROGRAMMING_DELAY_0   0x00000000U            /*!< programming delay set for Flash running at 70 MHz or below          */

+#define FLASH_PROGRAMMING_DELAY_1   FLASH_ACR_WRHIGHFREQ_0 /*!< programming delay set for Flash running between 70 MHz and 185 MHz  */

+#define FLASH_PROGRAMMING_DELAY_2   FLASH_ACR_WRHIGHFREQ_1 /*!< programming delay set for Flash running between 185 MHz and 225 MHz */

+#define FLASH_PROGRAMMING_DELAY_3   FLASH_ACR_WRHIGHFREQ   /*!< programming delay set for Flash at startup */

+/**

+  * @}

+  */

+

+#if defined (FLASH_OTPBL_LOCKBL)

+/** @defgroup FLASHEx_OTP_Blocks FLASH OTP blocks

+  * @{

+  */

+#define FLASH_OTP_BLOCK_0          0x00000001U /*!< OTP Block0     */

+#define FLASH_OTP_BLOCK_1          0x00000002U /*!< OTP Block1     */

+#define FLASH_OTP_BLOCK_2          0x00000004U /*!< OTP Block2     */

+#define FLASH_OTP_BLOCK_3          0x00000008U /*!< OTP Block3     */

+#define FLASH_OTP_BLOCK_4          0x00000010U /*!< OTP Block4     */

+#define FLASH_OTP_BLOCK_5          0x00000020U /*!< OTP Block5     */

+#define FLASH_OTP_BLOCK_6          0x00000040U /*!< OTP Block6     */

+#define FLASH_OTP_BLOCK_7          0x00000080U /*!< OTP Block7     */

+#define FLASH_OTP_BLOCK_8          0x00000100U /*!< OTP Block8     */

+#define FLASH_OTP_BLOCK_9          0x00000200U /*!< OTP Block9     */

+#define FLASH_OTP_BLOCK_10         0x00000400U /*!< OTP Block10    */

+#define FLASH_OTP_BLOCK_11         0x00000800U /*!< OTP Block11    */

+#define FLASH_OTP_BLOCK_12         0x00001000U /*!< OTP Block12    */

+#define FLASH_OTP_BLOCK_13         0x00002000U /*!< OTP Block13    */

+#define FLASH_OTP_BLOCK_14         0x00004000U /*!< OTP Block14    */

+#define FLASH_OTP_BLOCK_15         0x00008000U /*!< OTP Block15    */

+#define FLASH_OTP_BLOCK_ALL        0x0000FFFFU /*!< OTP All Blocks */

+/**

+  * @}

+  */

+#endif /* FLASH_OTPBL_LOCKBL */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup FLASHEx_Exported_Macros FLASH Exported Macros

+  * @{

+  */

+/**

+  * @brief  Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1)

+  * @note   Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14].

+  * @param  __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB)

+  * @retval The FLASH Boot Base Adress

+  */

+#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14U)

+ /**

+  * @}

+  */

+

+#if defined (FLASH_CR_PSIZE)

+/**

+  * @brief  Set the FLASH Program/Erase parallelism.

+  * @param  __PSIZE__ FLASH Program/Erase parallelism

+  *         This parameter can be a value of @ref FLASH_Program_Parallelism

+  * @param  __BANK__: Flash bank (FLASH_BANK_1 or FLASH_BANK_2)

+  * @retval none

+  */

+#define __HAL_FLASH_SET_PSIZE(__PSIZE__, __BANK__) (((__BANK__) == FLASH_BANK_1)  ? \

+                              MODIFY_REG(FLASH->CR1, FLASH_CR_PSIZE, (__PSIZE__)) : \

+                              MODIFY_REG(FLASH->CR2, FLASH_CR_PSIZE, (__PSIZE__)))

+

+/**

+  * @brief  Get the FLASH Program/Erase parallelism.

+  * @param  __BANK__ Flash bank (FLASH_BANK_1 or FLASH_BANK_2)

+  * @retval FLASH Program/Erase parallelism

+  *         This return value can be a value of @ref FLASH_Program_Parallelism

+  */

+#define __HAL_FLASH_GET_PSIZE(__BANK__) (((__BANK__) == FLASH_BANK_1) ? \

+                              READ_BIT((FLASH->CR1), FLASH_CR_PSIZE)  : \

+                              READ_BIT((FLASH->CR2), FLASH_CR_PSIZE))

+#endif /* FLASH_CR_PSIZE */

+

+/**

+  * @brief  Set the FLASH Programming Delay.

+  * @param  __DELAY__ FLASH Programming Delay

+  *         This parameter can be a value of @ref FLASHEx_Programming_Delay

+  * @retval none

+  */

+#define __HAL_FLASH_SET_PROGRAM_DELAY(__DELAY__)  MODIFY_REG(FLASH->ACR, FLASH_ACR_WRHIGHFREQ, (__DELAY__))

+

+/**

+  * @brief  Get the FLASH Programming Delay.

+  * @retval FLASH Programming Delay

+  *         This return value can be a value of @ref FLASHEx_Programming_Delay

+  */

+#define __HAL_FLASH_GET_PROGRAM_DELAY()     READ_BIT(FLASH->ACR, FLASH_ACR_WRHIGHFREQ)

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup FLASHEx_Exported_Functions

+  * @{

+  */

+

+/** @addtogroup FLASHEx_Exported_Functions_Group1

+  * @{

+  */

+/* Extension Program operation functions  *************************************/

+HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *SectorError);

+HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);

+HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);

+void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);

+

+HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank1(void);

+HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank1(void);

+HAL_StatusTypeDef HAL_FLASHEx_Unlock_Bank2(void);

+HAL_StatusTypeDef HAL_FLASHEx_Lock_Bank2(void);

+

+HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_t *CRC_Result);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros

+  * @{

+  */

+

+/** @defgroup FLASHEx_IS_FLASH_Definitions FLASHEx Private macros to check input parameters

+  * @{

+  */

+

+#define IS_FLASH_TYPEERASE(VALUE)        (((VALUE) == FLASH_TYPEERASE_SECTORS) || \

+                                          ((VALUE) == FLASH_TYPEERASE_MASSERASE))

+

+#if defined (FLASH_CR_PSIZE)

+#define IS_VOLTAGERANGE(RANGE)           (((RANGE) == FLASH_VOLTAGE_RANGE_1) || \

+                                          ((RANGE) == FLASH_VOLTAGE_RANGE_2) || \

+                                          ((RANGE) == FLASH_VOLTAGE_RANGE_3) || \

+                                          ((RANGE) == FLASH_VOLTAGE_RANGE_4))

+#endif /* FLASH_CR_PSIZE */

+

+#define IS_WRPSTATE(VALUE)               (((VALUE) == OB_WRPSTATE_DISABLE) || \

+                                          ((VALUE) == OB_WRPSTATE_ENABLE))

+

+#if defined (FLASH_OPTSR_VDDMMC_HSLV)

+#define IS_OPTIONBYTE(VALUE)             (((VALUE) <= 0x03FFU) && ((VALUE) != 0U))

+#elif defined (DUAL_CORE)

+#define IS_OPTIONBYTE(VALUE)             (((VALUE) <= 0x3FFFU) && ((VALUE) != 0U))

+#else

+#define IS_OPTIONBYTE(VALUE)             (((VALUE) <= 0x01FFU) && ((VALUE) != 0U))

+#endif /*DUAL_CORE*/

+

+#define IS_OB_BOOT_ADDRESS(ADDRESS)      ((ADDRESS) <= 0x8013U)

+

+#define IS_OB_RDP_LEVEL(LEVEL)           (((LEVEL) == OB_RDP_LEVEL_0)   ||\

+                                          ((LEVEL) == OB_RDP_LEVEL_1)   ||\

+                                          ((LEVEL) == OB_RDP_LEVEL_2))

+

+#define IS_OB_WWDG_SOURCE(SOURCE)        (((SOURCE) == OB_WWDG_SW) || ((SOURCE) == OB_WWDG_HW))

+

+#define IS_OB_IWDG_SOURCE(SOURCE)        (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))

+

+#define IS_OB_STOP_SOURCE(SOURCE)        (((SOURCE) == OB_STOP_NO_RST) || ((SOURCE) == OB_STOP_RST))

+

+#define IS_OB_STDBY_SOURCE(SOURCE)       (((SOURCE) == OB_STDBY_NO_RST) || ((SOURCE) == OB_STDBY_RST))

+

+#define IS_OB_IWDG_STOP_FREEZE(FREEZE)   (((FREEZE) == OB_IWDG_STOP_FREEZE) || ((FREEZE) == OB_IWDG_STOP_ACTIVE))

+

+#define IS_OB_IWDG_STDBY_FREEZE(FREEZE)  (((FREEZE) == OB_IWDG_STDBY_FREEZE) || ((FREEZE) == OB_IWDG_STDBY_ACTIVE))

+

+#define IS_OB_BOR_LEVEL(LEVEL)           (((LEVEL) == OB_BOR_LEVEL0) || ((LEVEL) == OB_BOR_LEVEL1) || \

+                                          ((LEVEL) == OB_BOR_LEVEL2) || ((LEVEL) == OB_BOR_LEVEL3))

+

+#define IS_FLASH_LATENCY(LATENCY)        (((LATENCY) == FLASH_LATENCY_0)  || \

+                                          ((LATENCY) == FLASH_LATENCY_1)  || \

+                                          ((LATENCY) == FLASH_LATENCY_2)  || \

+                                          ((LATENCY) == FLASH_LATENCY_3)  || \

+                                          ((LATENCY) == FLASH_LATENCY_4)  || \

+                                          ((LATENCY) == FLASH_LATENCY_5)  || \

+                                          ((LATENCY) == FLASH_LATENCY_6)  || \

+                                          ((LATENCY) == FLASH_LATENCY_7)  || \

+                                          ((LATENCY) == FLASH_LATENCY_8)  || \

+                                          ((LATENCY) == FLASH_LATENCY_9)  || \

+                                          ((LATENCY) == FLASH_LATENCY_10) || \

+                                          ((LATENCY) == FLASH_LATENCY_11) || \

+                                          ((LATENCY) == FLASH_LATENCY_12) || \

+                                          ((LATENCY) == FLASH_LATENCY_13) || \

+                                          ((LATENCY) == FLASH_LATENCY_14) || \

+                                          ((LATENCY) == FLASH_LATENCY_15))

+

+#define IS_FLASH_SECTOR(SECTOR)          ((SECTOR) < FLASH_SECTOR_TOTAL)

+

+#if (FLASH_SECTOR_TOTAL == 8U)

+#define IS_OB_WRP_SECTOR(SECTOR)         ((((SECTOR) & 0xFFFFFF00U) == 0x00000000U) && ((SECTOR) != 0x00000000U))

+#else

+#define IS_OB_WRP_SECTOR(SECTOR)         ((SECTOR) != 0x00000000U)

+#endif /* FLASH_SECTOR_TOTAL == 8U */

+

+#define IS_OB_PCROP_RDP(CONFIG)          (((CONFIG) == OB_PCROP_RDP_NOT_ERASE) || \

+                                          ((CONFIG) == OB_PCROP_RDP_ERASE))

+

+#define IS_OB_SECURE_RDP(CONFIG)         (((CONFIG) == OB_SECURE_RDP_NOT_ERASE) || \

+                                          ((CONFIG) == OB_SECURE_RDP_ERASE))

+

+#define IS_OB_USER_SWAP_BANK(VALUE)      (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE))

+

+#define IS_OB_USER_IOHSLV(VALUE)         (((VALUE) == OB_IOHSLV_DISABLE) || ((VALUE) == OB_IOHSLV_ENABLE))

+

+#if defined (FLASH_OPTSR_VDDMMC_HSLV)

+#define IS_OB_USER_VDDMMC_HSLV(VALUE)    (((VALUE) == OB_VDDMMC_HSLV_DISABLE) || ((VALUE) == OB_VDDMMC_HSLV_ENABLE))

+#endif /* FLASH_OPTSR_VDDMMC_HSLV */

+

+#define IS_OB_IWDG1_SOURCE(SOURCE)       (((SOURCE) == OB_IWDG1_SW) || ((SOURCE) == OB_IWDG1_HW))

+#if defined (DUAL_CORE)

+#define IS_OB_IWDG2_SOURCE(SOURCE)       (((SOURCE) == OB_IWDG2_SW) || ((SOURCE) == OB_IWDG2_HW))

+#endif /* DUAL_CORE */

+#define IS_OB_STOP_D1_RESET(VALUE)       (((VALUE) == OB_STOP_NO_RST_D1) || ((VALUE) == OB_STOP_RST_D1))

+

+#define IS_OB_STDBY_D1_RESET(VALUE)      (((VALUE) == OB_STDBY_NO_RST_D1) || ((VALUE) == OB_STDBY_RST_D1))

+

+#define IS_OB_USER_IWDG_STOP(VALUE)      (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_ACTIVE))

+

+#define IS_OB_USER_IWDG_STDBY(VALUE)     (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_ACTIVE))

+

+#define IS_OB_USER_ST_RAM_SIZE(VALUE)    (((VALUE) == OB_ST_RAM_SIZE_2KB) || ((VALUE) == OB_ST_RAM_SIZE_4KB) || \

+                                          ((VALUE) == OB_ST_RAM_SIZE_8KB) || ((VALUE) == OB_ST_RAM_SIZE_16KB))

+

+#define IS_OB_USER_SECURITY(VALUE)       (((VALUE) == OB_SECURITY_ENABLE) || ((VALUE) == OB_SECURITY_DISABLE))

+

+#if defined (DUAL_CORE)

+#define IS_OB_USER_BCM4(VALUE)           (((VALUE) == OB_BCM4_DISABLE) || ((VALUE) == OB_BCM4_ENABLE))

+

+#define IS_OB_USER_BCM7(VALUE)           (((VALUE) == OB_BCM7_DISABLE) || ((VALUE) == OB_BCM7_ENABLE))

+

+#define IS_OB_STOP_D2_RESET(VALUE)       (((VALUE) == OB_STOP_NO_RST_D2) || ((VALUE) == OB_STOP_RST_D2))

+

+#define IS_OB_STDBY_D2_RESET(VALUE)      (((VALUE) == OB_STDBY_NO_RST_D2) || ((VALUE) == OB_STDBY_RST_D2))

+#endif /* DUAL_CORE */

+#if defined (DUAL_CORE)

+#define IS_OB_USER_TYPE(TYPE)            (((TYPE) <= (uint32_t)0x3FFFU) && ((TYPE) != 0U))

+#else

+#define IS_OB_USER_TYPE(TYPE)            (((TYPE) <= (uint32_t)0x73FU) && ((TYPE) != 0U))

+#endif /* DUAL_CORE */

+

+#define IS_OB_BOOT_ADD_OPTION(VALUE)     (((VALUE) == OB_BOOT_ADD0)  || \

+                                          ((VALUE) == OB_BOOT_ADD1)  || \

+                                          ((VALUE) == OB_BOOT_ADD_BOTH))

+

+#define IS_FLASH_TYPECRC(VALUE)          (((VALUE) == FLASH_CRC_ADDR)    || \

+                                          ((VALUE) == FLASH_CRC_SECTORS) || \

+                                          ((VALUE) == FLASH_CRC_BANK))

+

+#if defined (FLASH_OTPBL_LOCKBL)

+#define IS_OTP_BLOCK(VALUE)              ((((VALUE) & 0xFFFF0000U) == 0x00000000U) && ((VALUE) != 0x00000000U))

+#endif /* FLASH_OTPBL_LOCKBL */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private functions ---------------------------------------------------------*/

+/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions

+  * @{

+  */

+void FLASH_Erase_Sector(uint32_t Sector, uint32_t Banks, uint32_t VoltageRange);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_FLASH_EX_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_gfxmmu.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_gfxmmu.h
new file mode 100644
index 0000000000..2d41105dce
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_gfxmmu.h
@@ -0,0 +1,453 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_gfxmmu.h

+  * @author  MCD Application Team

+  * @brief   Header file of GFXMMU HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_GFXMMU_H

+#define STM32H7xx_HAL_GFXMMU_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+#if defined(GFXMMU)

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup GFXMMU

+  * @{

+  */ 

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup GFXMMU_Exported_Types GFXMMU Exported Types

+  * @{

+  */

+

+/** 

+  * @brief  HAL GFXMMU states definition

+  */

+typedef enum

+{

+  HAL_GFXMMU_STATE_RESET = 0x00U, /*!< GFXMMU not initialized */

+  HAL_GFXMMU_STATE_READY = 0x01U, /*!< GFXMMU initialized and ready for use */

+}HAL_GFXMMU_StateTypeDef;

+

+/** 

+  * @brief  GFXMMU buffers structure definition

+  */

+typedef struct

+{

+  uint32_t Buf0Address; /*!< Physical address of buffer 0. */

+  uint32_t Buf1Address; /*!< Physical address of buffer 1. */

+  uint32_t Buf2Address; /*!< Physical address of buffer 2. */

+  uint32_t Buf3Address; /*!< Physical address of buffer 3. */

+}GFXMMU_BuffersTypeDef;

+

+/** 

+  * @brief  GFXMMU cache and pre-fetch structure definition

+  */

+typedef struct

+{

+  FunctionalState Activation;          /*!< Cache and pre-fetch enable/disable.

+                                            @note: All following parameters are usefull only if cache and pre-fetch are enabled. */

+  uint32_t        CacheLock;           /*!< Locking the cache to a buffer.

+                                            This parameter can be a value of @ref GFXMMU_CacheLock. */

+  uint32_t        CacheLockBuffer;     /*!< Buffer on which the cache is locked.

+                                            This parameter can be a value of @ref GFXMMU_CacheLockBuffer.

+                                            @note: Usefull only when lock of the cache is enabled. */

+  uint32_t        CacheForce;          /*!< Forcing the cache regardless MPU attributes.

+                                            This parameter can be a value of @ref GFXMMU_CacheForce.

+                                            @note: Usefull only when lock of the cache is enabled. */

+  uint32_t        OutterBufferability; /*!< Bufferability of an access generated by the GFXMMU cache.

+                                            This parameter can be a value of @ref GFXMMU_OutterBufferability. */

+  uint32_t        OutterCachability;   /*!< Cachability of an access generated by the GFXMMU cache.

+                                            This parameter can be a value of @ref GFXMMU_OutterCachability. */

+  uint32_t        Prefetch;            /*!< Pre-fetch enable/disable.

+                                            This parameter can be a value of @ref GFXMMU_Prefetch. */

+}GFXMMU_CachePrefetchTypeDef;

+

+/** 

+  * @brief  GFXMMU interrupts structure definition

+  */

+typedef struct

+{

+  FunctionalState Activation;     /*!< Interrupts enable/disable */

+  uint32_t        UsedInterrupts; /*!< Interrupts used.

+                                       This parameter can be a values combination of @ref GFXMMU_Interrupts.

+                                       @note: Usefull only when interrupts are enabled. */

+}GFXMMU_InterruptsTypeDef;

+

+/** 

+  * @brief  GFXMMU init structure definition

+  */

+typedef struct

+{

+  uint32_t                    BlocksPerLine; /*!< Number of blocks of 16 bytes per line.

+                                                  This parameter can be a value of @ref GFXMMU_BlocksPerLine. */

+  uint32_t                    DefaultValue;  /*!< Value returned when virtual memory location not physically mapped. */

+  GFXMMU_BuffersTypeDef       Buffers;       /*!< Physical buffers addresses. */

+  GFXMMU_CachePrefetchTypeDef CachePrefetch; /*!< Cache and pre-fetch parameters. */

+  GFXMMU_InterruptsTypeDef    Interrupts;    /*!< Interrupts parameters. */

+}GFXMMU_InitTypeDef;

+

+/** 

+  * @brief  GFXMMU handle structure definition

+  */

+#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)

+typedef struct __GFXMMU_HandleTypeDef

+#else

+typedef struct

+#endif

+{

+  GFXMMU_TypeDef          *Instance; /*!< GFXMMU instance */

+  GFXMMU_InitTypeDef      Init;      /*!< GFXMMU init parameters */

+  HAL_GFXMMU_StateTypeDef State;     /*!< GFXMMU state */

+  __IO uint32_t           ErrorCode; /*!< GFXMMU error code */

+#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)

+  void (*ErrorCallback)     (struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU error callback */

+  void (*MspInitCallback)   (struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU MSP init callback */

+  void (*MspDeInitCallback) (struct __GFXMMU_HandleTypeDef *hgfxmmu); /*!< GFXMMU MSP de-init callback */

+#endif

+}GFXMMU_HandleTypeDef;

+

+/** 

+  * @brief  GFXMMU LUT line structure definition

+  */

+typedef struct

+{

+  uint32_t LineNumber;        /*!< LUT line number.

+                                   This parameter must be a number between Min_Data = 0 and Max_Data = 1023. */

+  uint32_t LineStatus;        /*!< LUT line enable/disable.

+                                   This parameter can be a value of @ref GFXMMU_LutLineStatus. */

+  uint32_t FirstVisibleBlock; /*!< First visible block on this line.

+                                   This parameter must be a number between Min_Data = 0 and Max_Data = 255. */

+  uint32_t LastVisibleBlock;  /*!< Last visible block on this line.

+                                   This parameter must be a number between Min_Data = 0 and Max_Data = 255. */

+  int32_t  LineOffset;        /*!< Offset of block 0 of the current line in physical buffer.

+                                   This parameter must be a number between Min_Data = -4080 and Max_Data = 4190208.

+                                   @note: Line offset has to be computed with the following formula:

+                                          LineOffset = [(Blocks already used) - (1st visible block)]*BlockSize. */

+}GFXMMU_LutLineTypeDef;

+

+#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  GFXMMU callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_GFXMMU_ERROR_CB_ID     = 0x00U, /*!< GFXMMU error callback ID */

+  HAL_GFXMMU_MSPINIT_CB_ID   = 0x01U, /*!< GFXMMU MSP init callback ID */

+  HAL_GFXMMU_MSPDEINIT_CB_ID = 0x02U  /*!< GFXMMU MSP de-init callback ID */

+}HAL_GFXMMU_CallbackIDTypeDef;

+

+/**

+  * @brief  GFXMMU callback pointer definition

+  */

+typedef void (*pGFXMMU_CallbackTypeDef)(GFXMMU_HandleTypeDef *hgfxmmu);

+#endif

+

+/**

+  * @}

+  */ 

+/* End of exported types -----------------------------------------------------*/

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup GFXMMU_Exported_Constants GFXMMU Exported Constants

+  * @{

+  */

+

+/** @defgroup GFXMMU_BlocksPerLine GFXMMU blocks per line

+  * @{

+  */

+#define GFXMMU_256BLOCKS 0x00000000U     /*!< 256 blocks of 16 bytes per line */

+#define GFXMMU_192BLOCKS GFXMMU_CR_192BM /*!< 192 blocks of 16 bytes per line */

+/**

+  * @}

+  */

+

+/** @defgroup GFXMMU_CacheLock GFXMMU cache lock

+  * @{

+  */

+#define GFXMMU_CACHE_LOCK_DISABLE 0x00000000U  /*!< Cache not locked to a buffer */

+#define GFXMMU_CACHE_LOCK_ENABLE  GFXMMU_CR_CL /*!< Cache locked to a buffer */

+/**

+  * @}

+  */

+

+/** @defgroup GFXMMU_CacheLockBuffer GFXMMU cache lock buffer

+  * @{

+  */

+#define GFXMMU_CACHE_LOCK_BUFFER0 0x00000000U     /*!< Cache locked to buffer 0 */

+#define GFXMMU_CACHE_LOCK_BUFFER1 GFXMMU_CR_CLB_0 /*!< Cache locked to buffer 1 */

+#define GFXMMU_CACHE_LOCK_BUFFER2 GFXMMU_CR_CLB_1 /*!< Cache locked to buffer 2 */

+#define GFXMMU_CACHE_LOCK_BUFFER3 GFXMMU_CR_CLB   /*!< Cache locked to buffer 3 */

+/**

+  * @}

+  */

+

+/** @defgroup GFXMMU_CacheForce GFXMMU cache force

+  * @{

+  */

+#define GFXMMU_CACHE_FORCE_DISABLE 0x00000000U  /*!< Caching not forced */

+#define GFXMMU_CACHE_FORCE_ENABLE  GFXMMU_CR_FC /*!< Caching forced */

+/**

+  * @}

+  */

+

+/** @defgroup GFXMMU_OutterBufferability GFXMMU outter bufferability

+  * @{

+  */

+#define GFXMMU_OUTTER_BUFFERABILITY_DISABLE 0x00000000U  /*!< No bufferable */

+#define GFXMMU_OUTTER_BUFFERABILITY_ENABLE  GFXMMU_CR_OB /*!< Bufferable */

+/**

+  * @}

+  */

+

+/** @defgroup GFXMMU_OutterCachability GFXMMU outter cachability

+  * @{

+  */

+#define GFXMMU_OUTTER_CACHABILITY_DISABLE 0x00000000U  /*!< No cachable */

+#define GFXMMU_OUTTER_CACHABILITY_ENABLE  GFXMMU_CR_OC /*!< Cachable */

+/**

+  * @}

+  */

+

+/** @defgroup GFXMMU_Prefetch GFXMMU pre-fetch

+  * @{

+  */

+#define GFXMMU_PREFETCH_DISABLE GFXMMU_CR_PD /*!< Pre-fetch disable */

+#define GFXMMU_PREFETCH_ENABLE  0x00000000U  /*!< Pre-fetch enable */

+/**

+  * @}

+  */

+

+/** @defgroup GFXMMU_Interrupts GFXMMU interrupts

+  * @{

+  */

+#define GFXMMU_AHB_MASTER_ERROR_IT GFXMMU_CR_AMEIE /*!< AHB master error interrupt */

+#define GFXMMU_BUFFER0_OVERFLOW_IT GFXMMU_CR_B0OIE /*!< Buffer 0 overflow interrupt */

+#define GFXMMU_BUFFER1_OVERFLOW_IT GFXMMU_CR_B1OIE /*!< Buffer 1 overflow interrupt */

+#define GFXMMU_BUFFER2_OVERFLOW_IT GFXMMU_CR_B2OIE /*!< Buffer 2 overflow interrupt */

+#define GFXMMU_BUFFER3_OVERFLOW_IT GFXMMU_CR_B3OIE /*!< Buffer 3 overflow interrupt */

+/**

+  * @}

+  */

+

+/** @defgroup GFXMMU_Error_Code GFXMMU Error Code

+  * @{

+  */

+#define GFXMMU_ERROR_NONE             0x00000000U    /*!< No error */

+#define GFXMMU_ERROR_BUFFER0_OVERFLOW GFXMMU_SR_B0OF /*!< Buffer 0 overflow */

+#define GFXMMU_ERROR_BUFFER1_OVERFLOW GFXMMU_SR_B1OF /*!< Buffer 1 overflow */

+#define GFXMMU_ERROR_BUFFER2_OVERFLOW GFXMMU_SR_B2OF /*!< Buffer 2 overflow */

+#define GFXMMU_ERROR_BUFFER3_OVERFLOW GFXMMU_SR_B3OF /*!< Buffer 3 overflow */

+#define GFXMMU_ERROR_AHB_MASTER       GFXMMU_SR_AMEF /*!< AHB master error */

+#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)

+#define GFXMMU_ERROR_INVALID_CALLBACK 0x00000100U    /*!< Invalid callback error */

+#endif

+/**

+  * @}

+  */

+

+/** @defgroup GFXMMU_LutLineStatus GFXMMU LUT line status

+  * @{

+  */

+#define GFXMMU_LUT_LINE_DISABLE 0x00000000U     /*!< LUT line disabled */

+#define GFXMMU_LUT_LINE_ENABLE  GFXMMU_LUTxL_EN /*!< LUT line enabled */

+/**

+  * @}

+  */

+

+/** @defgroup GFXMMU_CacheForceParam GFXMMU cache force parameter

+  * @{

+  */

+#define GFXMMU_CACHE_FORCE_FLUSH      GFXMMU_CCR_FF /*!< Force cache flush */

+#define GFXMMU_CACHE_FORCE_INVALIDATE GFXMMU_CCR_FI /*!< Force cache invalidate */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */ 

+/* End of exported constants -------------------------------------------------*/

+

+/* Exported macros -----------------------------------------------------------*/

+/** @defgroup GFXMMU_Exported_Macros GFXMMU Exported Macros

+ * @{

+ */

+

+/** @brief  Reset GFXMMU handle state.

+  * @param  __HANDLE__ GFXMMU handle.

+  * @retval None

+  */

+#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)

+#define __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__) do{                                               \

+                                                        (__HANDLE__)->State = HAL_GFXMMU_STATE_RESET; \

+                                                        (__HANDLE__)->MspInitCallback = NULL;         \

+                                                        (__HANDLE__)->MspDeInitCallback = NULL;       \

+                                                      } while(0)

+#else

+#define __HAL_GFXMMU_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_GFXMMU_STATE_RESET)

+#endif

+

+/**

+  * @}

+  */

+/* End of exported macros ----------------------------------------------------*/

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup GFXMMU_Exported_Functions GFXMMU Exported Functions

+  * @{

+  */

+

+/** @addtogroup GFXMMU_Exported_Functions_Group1 Initialization and de-initialization functions

+  * @{

+  */

+/* Initialization and de-initialization functions *****************************/

+HAL_StatusTypeDef HAL_GFXMMU_Init(GFXMMU_HandleTypeDef *hgfxmmu);

+HAL_StatusTypeDef HAL_GFXMMU_DeInit(GFXMMU_HandleTypeDef *hgfxmmu);

+void HAL_GFXMMU_MspInit(GFXMMU_HandleTypeDef *hgfxmmu);

+void HAL_GFXMMU_MspDeInit(GFXMMU_HandleTypeDef *hgfxmmu);

+#if (USE_HAL_GFXMMU_REGISTER_CALLBACKS == 1)

+/* GFXMMU callbacks register/unregister functions *****************************/

+HAL_StatusTypeDef HAL_GFXMMU_RegisterCallback(GFXMMU_HandleTypeDef        *hgfxmmu,

+                                              HAL_GFXMMU_CallbackIDTypeDef CallbackID,

+                                              pGFXMMU_CallbackTypeDef      pCallback);

+HAL_StatusTypeDef HAL_GFXMMU_UnRegisterCallback(GFXMMU_HandleTypeDef        *hgfxmmu,

+                                                HAL_GFXMMU_CallbackIDTypeDef CallbackID);

+#endif

+/**

+  * @}

+  */

+

+/** @addtogroup GFXMMU_Exported_Functions_Group2 Operations functions

+  * @{

+  */

+/* Operation functions ********************************************************/

+HAL_StatusTypeDef HAL_GFXMMU_ConfigLut(GFXMMU_HandleTypeDef *hgfxmmu,

+                                       uint32_t FirstLine,

+                                       uint32_t LinesNumber,

+                                       uint32_t Address);

+

+HAL_StatusTypeDef HAL_GFXMMU_DisableLutLines(GFXMMU_HandleTypeDef *hgfxmmu,

+                                             uint32_t FirstLine,

+                                             uint32_t LinesNumber);

+

+HAL_StatusTypeDef HAL_GFXMMU_ConfigLutLine(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_LutLineTypeDef *lutLine);

+

+HAL_StatusTypeDef HAL_GFXMMU_ConfigForceCache(GFXMMU_HandleTypeDef *hgfxmmu, uint32_t ForceParam);

+

+HAL_StatusTypeDef HAL_GFXMMU_ModifyBuffers(GFXMMU_HandleTypeDef *hgfxmmu, GFXMMU_BuffersTypeDef *Buffers);

+

+HAL_StatusTypeDef HAL_GFXMMU_ModifyCachePrefetch(GFXMMU_HandleTypeDef *hgfxmmu,

+                                                 GFXMMU_CachePrefetchTypeDef *CachePrefetch);

+

+void HAL_GFXMMU_IRQHandler(GFXMMU_HandleTypeDef *hgfxmmu);

+

+void HAL_GFXMMU_ErrorCallback(GFXMMU_HandleTypeDef *hgfxmmu);

+/**

+  * @}

+  */

+

+/** @defgroup GFXMMU_Exported_Functions_Group3 State functions

+  * @{

+  */

+/* State function *************************************************************/

+HAL_GFXMMU_StateTypeDef HAL_GFXMMU_GetState(GFXMMU_HandleTypeDef *hgfxmmu);

+

+uint32_t HAL_GFXMMU_GetError(GFXMMU_HandleTypeDef *hgfxmmu);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+/* End of exported functions -------------------------------------------------*/

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup GFXMMU_Private_Macros GFXMMU Private Macros

+* @{

+*/

+#define IS_GFXMMU_BLOCKS_PER_LINE(VALUE) (((VALUE) == GFXMMU_256BLOCKS) || \

+                                          ((VALUE) == GFXMMU_192BLOCKS))

+

+#define IS_GFXMMU_BUFFER_ADDRESS(VALUE) (((VALUE) & 0xFU) == 0U)

+

+#define IS_GFXMMU_CACHE_LOCK(VALUE) (((VALUE) == GFXMMU_CACHE_LOCK_DISABLE) || \

+                                     ((VALUE) == GFXMMU_CACHE_LOCK_ENABLE))

+

+#define IS_GFXMMU_CACHE_LOCK_BUFFER(VALUE) (((VALUE) == GFXMMU_CACHE_LOCK_BUFFER0) || \

+                                            ((VALUE) == GFXMMU_CACHE_LOCK_BUFFER1) || \

+                                            ((VALUE) == GFXMMU_CACHE_LOCK_BUFFER2) || \

+                                            ((VALUE) == GFXMMU_CACHE_LOCK_BUFFER3))

+

+#define IS_GFXMMU_CACHE_FORCE(VALUE) (((VALUE) == GFXMMU_CACHE_FORCE_DISABLE) || \

+                                      ((VALUE) == GFXMMU_CACHE_FORCE_ENABLE))

+

+#define IS_GFXMMU_OUTTER_BUFFERABILITY(VALUE) (((VALUE) == GFXMMU_OUTTER_BUFFERABILITY_DISABLE) || \

+                                               ((VALUE) == GFXMMU_OUTTER_BUFFERABILITY_ENABLE))

+

+#define IS_GFXMMU_OUTTER_CACHABILITY(VALUE) (((VALUE) == GFXMMU_OUTTER_CACHABILITY_DISABLE) || \

+                                             ((VALUE) == GFXMMU_OUTTER_CACHABILITY_ENABLE))

+

+#define IS_GFXMMU_PREFETCH(VALUE) (((VALUE) == GFXMMU_PREFETCH_DISABLE) || \

+                                   ((VALUE) == GFXMMU_PREFETCH_ENABLE))

+

+#define IS_GFXMMU_INTERRUPTS(VALUE) (((VALUE) & 0x1FU) != 0U)

+

+#define IS_GFXMMU_LUT_LINE(VALUE) ((VALUE) < 1024U)

+

+#define IS_GFXMMU_LUT_LINES_NUMBER(VALUE) (((VALUE) > 0U) && ((VALUE) <= 1024U))

+

+#define IS_GFXMMU_LUT_LINE_STATUS(VALUE) (((VALUE) == GFXMMU_LUT_LINE_DISABLE) || \

+                                          ((VALUE) == GFXMMU_LUT_LINE_ENABLE))

+

+#define IS_GFXMMU_LUT_BLOCK(VALUE) ((VALUE) < 256U)

+

+#define IS_GFXMMU_LUT_LINE_OFFSET(VALUE) (((VALUE) >= -4080) && ((VALUE) <= 4190208))

+

+#define IS_GFXMMU_CACHE_FORCE_ACTION(VALUE) (((VALUE) == GFXMMU_CACHE_FORCE_FLUSH) || \

+                                             ((VALUE) == GFXMMU_CACHE_FORCE_INVALIDATE) || \

+                                             ((VALUE) == (GFXMMU_CACHE_FORCE_FLUSH | GFXMMU_CACHE_FORCE_INVALIDATE)))

+/**

+  * @}

+  */ 

+/* End of private macros -----------------------------------------------------*/

+

+/**

+  * @}

+  */ 

+

+/**

+  * @}

+  */

+#endif /* GFXMMU */

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_GFXMMU_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_gpio.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_gpio.h
new file mode 100644
index 0000000000..c18556653e
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_gpio.h
@@ -0,0 +1,346 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_gpio.h

+  * @author  MCD Application Team

+  * @brief   Header file of GPIO HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_GPIO_H

+#define STM32H7xx_HAL_GPIO_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup GPIO

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup GPIO_Exported_Types GPIO Exported Types

+  * @{

+  */

+

+/**

+  * @brief   GPIO Init structure definition

+  */

+typedef struct

+{

+  uint32_t Pin;       /*!< Specifies the GPIO pins to be configured.

+                           This parameter can be any value of @ref GPIO_pins_define */

+

+  uint32_t Mode;      /*!< Specifies the operating mode for the selected pins.

+                           This parameter can be a value of @ref GPIO_mode_define */

+

+  uint32_t Pull;      /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.

+                           This parameter can be a value of @ref GPIO_pull_define */

+

+  uint32_t Speed;     /*!< Specifies the speed for the selected pins.

+                           This parameter can be a value of @ref GPIO_speed_define */

+

+  uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins.

+                            This parameter can be a value of @ref GPIO_Alternate_function_selection */

+} GPIO_InitTypeDef;

+

+/**

+  * @brief  GPIO Bit SET and Bit RESET enumeration

+  */

+typedef enum

+{

+  GPIO_PIN_RESET = 0U,

+  GPIO_PIN_SET

+} GPIO_PinState;

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+

+/** @defgroup GPIO_Exported_Constants  GPIO Exported Constants

+  * @{

+  */

+

+/** @defgroup GPIO_pins_define  GPIO pins define

+  * @{

+  */

+#define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */

+#define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */

+#define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */

+#define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */

+#define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */

+#define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */

+#define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */

+#define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */

+#define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */

+#define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */

+#define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */

+#define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */

+#define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */

+#define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */

+#define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */

+#define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */

+#define GPIO_PIN_All               ((uint16_t)0xFFFF)  /* All pins selected */

+

+#define GPIO_PIN_MASK              (0x0000FFFFU) /* PIN mask for assert test */

+/**

+  * @}

+  */

+

+/** @defgroup GPIO_mode_define  GPIO mode define

+  * @brief GPIO Configuration Mode

+  *        Elements values convention: 0xX0yz00YZ

+  *           - X  : GPIO mode or EXTI Mode

+  *           - y  : External IT or Event trigger detection

+  *           - z  : IO configuration on External IT or Event

+  *           - Y  : Output type (Push Pull or Open Drain)

+  *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)

+  * @{

+  */

+#define  GPIO_MODE_INPUT                        (0x00000000U)   /*!< Input Floating Mode                   */

+#define  GPIO_MODE_OUTPUT_PP                    (0x00000001U)   /*!< Output Push Pull Mode                 */

+#define  GPIO_MODE_OUTPUT_OD                    (0x00000011U)   /*!< Output Open Drain Mode                */

+#define  GPIO_MODE_AF_PP                        (0x00000002U)   /*!< Alternate Function Push Pull Mode     */

+#define  GPIO_MODE_AF_OD                        (0x00000012U)   /*!< Alternate Function Open Drain Mode    */

+

+#define  GPIO_MODE_ANALOG                       (0x00000003U)   /*!< Analog Mode  */

+

+#define  GPIO_MODE_IT_RISING                    (0x11110000U)   /*!< External Interrupt Mode with Rising edge trigger detection          */

+#define  GPIO_MODE_IT_FALLING                   (0x11210000U)   /*!< External Interrupt Mode with Falling edge trigger detection         */

+#define  GPIO_MODE_IT_RISING_FALLING            (0x11310000U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */

+

+#define  GPIO_MODE_EVT_RISING                   (0x11120000U)   /*!< External Event Mode with Rising edge trigger detection               */

+#define  GPIO_MODE_EVT_FALLING                  (0x11220000U)   /*!< External Event Mode with Falling edge trigger detection              */

+#define  GPIO_MODE_EVT_RISING_FALLING           (0x11320000U)   /*!< External Event Mode with Rising/Falling edge trigger detection       */

+/**

+  * @}

+  */

+

+/** @defgroup GPIO_speed_define  GPIO speed define

+  * @brief GPIO Output Maximum frequency

+  * @{

+  */

+#define  GPIO_SPEED_FREQ_LOW         (0x00000000U)  /*!< Low speed     */

+#define  GPIO_SPEED_FREQ_MEDIUM      (0x00000001U)  /*!< Medium speed  */

+#define  GPIO_SPEED_FREQ_HIGH        (0x00000002U)  /*!< Fast speed    */

+#define  GPIO_SPEED_FREQ_VERY_HIGH   (0x00000003U)  /*!< High speed    */

+/**

+  * @}

+  */

+

+/** @defgroup GPIO_pull_define  GPIO pull define

+  * @brief GPIO Pull-Up or Pull-Down Activation

+  * @{

+  */

+#define  GPIO_NOPULL        (0x00000000U)   /*!< No Pull-up or Pull-down activation  */

+#define  GPIO_PULLUP        (0x00000001U)   /*!< Pull-up activation                  */

+#define  GPIO_PULLDOWN      (0x00000002U)   /*!< Pull-down activation                */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup GPIO_Exported_Macros GPIO Exported Macros

+  * @{

+  */

+

+/**

+  * @brief  Checks whether the specified EXTI line flag is set or not.

+  * @param  __EXTI_LINE__: specifies the EXTI line flag to check.

+  *         This parameter can be GPIO_PIN_x where x can be(0..15)

+  * @retval The new state of __EXTI_LINE__ (SET or RESET).

+  */

+#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))

+

+/**

+  * @brief  Clears the EXTI's line pending flags.

+  * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.

+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)

+  * @retval None

+  */

+#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))

+

+/**

+  * @brief  Checks whether the specified EXTI line is asserted or not.

+  * @param  __EXTI_LINE__: specifies the EXTI line to check.

+  *          This parameter can be GPIO_PIN_x where x can be(0..15)

+  * @retval The new state of __EXTI_LINE__ (SET or RESET).

+  */

+#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR1 & (__EXTI_LINE__))

+

+/**

+  * @brief  Clears the EXTI's line pending bits.

+  * @param  __EXTI_LINE__: specifies the EXTI lines to clear.

+  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)

+  * @retval None

+  */

+#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR1 = (__EXTI_LINE__))

+

+#if defined(DUAL_CORE)

+/**

+  * @brief  Checks whether the specified EXTI line flag is set or not.

+  * @param  __EXTI_LINE__: specifies the EXTI line flag to check.

+  *         This parameter can be GPIO_PIN_x where x can be(0..15)

+  * @retval The new state of __EXTI_LINE__ (SET or RESET).

+  */

+#define __HAL_GPIO_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI->C2PR1 & (__EXTI_LINE__))

+

+/**

+  * @brief  Clears the EXTI's line pending flags.

+  * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.

+  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)

+  * @retval None

+  */

+#define __HAL_GPIO_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI->C2PR1 = (__EXTI_LINE__))

+

+/**

+  * @brief  Checks whether the specified EXTI line is asserted or not.

+  * @param  __EXTI_LINE__: specifies the EXTI line to check.

+  *          This parameter can be GPIO_PIN_x where x can be(0..15)

+  * @retval The new state of __EXTI_LINE__ (SET or RESET).

+  */

+#define __HAL_GPIO_EXTID2_GET_IT(__EXTI_LINE__) (EXTI->C2PR1 & (__EXTI_LINE__))

+

+/**

+  * @brief  Clears the EXTI's line pending bits.

+  * @param  __EXTI_LINE__: specifies the EXTI lines to clear.

+  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)

+  * @retval None

+  */

+#define __HAL_GPIO_EXTID2_CLEAR_IT(__EXTI_LINE__) (EXTI->C2PR1 = (__EXTI_LINE__))

+#endif

+

+/**

+  * @brief  Generates a Software interrupt on selected EXTI line.

+  * @param  __EXTI_LINE__: specifies the EXTI line to check.

+  *          This parameter can be GPIO_PIN_x where x can be(0..15)

+  * @retval None

+  */

+#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 |= (__EXTI_LINE__))

+/**

+  * @}

+  */

+

+/* Include GPIO HAL Extension module */

+#include "stm32h7xx_hal_gpio_ex.h"

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup GPIO_Exported_Functions

+  * @{

+  */

+

+/** @addtogroup GPIO_Exported_Functions_Group1

+  * @{

+  */

+/* Initialization and de-initialization functions *****************************/

+void  HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);

+void  HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);

+/**

+  * @}

+  */

+

+/** @addtogroup GPIO_Exported_Functions_Group2

+  * @{

+  */

+/* IO operation functions *****************************************************/

+GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);

+void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);

+void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);

+HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);

+void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);

+void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup GPIO_Private_Constants GPIO Private Constants

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup GPIO_Private_Macros GPIO Private Macros

+  * @{

+  */

+#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))

+#define IS_GPIO_PIN(__PIN__)        ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\

+                                     (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U))

+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT)              ||\

+                            ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\

+                            ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\

+                            ((MODE) == GPIO_MODE_AF_PP)              ||\

+                            ((MODE) == GPIO_MODE_AF_OD)              ||\

+                            ((MODE) == GPIO_MODE_IT_RISING)          ||\

+                            ((MODE) == GPIO_MODE_IT_FALLING)         ||\

+                            ((MODE) == GPIO_MODE_IT_RISING_FALLING)  ||\

+                            ((MODE) == GPIO_MODE_EVT_RISING)         ||\

+                            ((MODE) == GPIO_MODE_EVT_FALLING)        ||\

+                            ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\

+                            ((MODE) == GPIO_MODE_ANALOG))

+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_FREQ_LOW)  || ((SPEED) == GPIO_SPEED_FREQ_MEDIUM) || \

+                              ((SPEED) == GPIO_SPEED_FREQ_HIGH) || ((SPEED) == GPIO_SPEED_FREQ_VERY_HIGH))

+

+#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \

+                            ((PULL) == GPIO_PULLDOWN))

+

+/**

+  * @}

+  */

+

+/* Private functions ---------------------------------------------------------*/

+/** @defgroup GPIO_Private_Functions GPIO Private Functions

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_GPIO_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_gpio_ex.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_gpio_ex.h
new file mode 100644
index 0000000000..ff2efb3c07
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_gpio_ex.h
@@ -0,0 +1,428 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_gpio_ex.h

+  * @author  MCD Application Team

+  * @brief   Header file of GPIO HAL Extension module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_GPIO_EX_H

+#define STM32H7xx_HAL_GPIO_EX_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup GPIOEx GPIOEx

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup GPIOEx_Exported_Constants GPIO Exported Constants

+  * @{

+  */

+

+/** @defgroup GPIO_Alternate_function_selection GPIO Alternate Function Selection

+  * @{

+  */

+

+/**

+  * @brief   AF 0 selection

+  */

+#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping                                                     */

+#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping                                          */

+#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping                                           */

+#define GPIO_AF0_LCDBIAS       ((uint8_t)0x00)  /* LCDBIAS Alternate Function mapping                                                      */

+#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping                                                        */

+#if defined (PWR_CPUCR_PDDS_D2) /* PWR D1 and D2 domains exists */

+#define GPIO_AF0_C1DSLEEP      ((uint8_t)0x00)  /* Cortex-M7 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above  */

+#define GPIO_AF0_C1SLEEP       ((uint8_t)0x00)  /* Cortex-M7 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above       */

+#define GPIO_AF0_D1PWREN       ((uint8_t)0x00)  /* Domain 1 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above   */

+#define GPIO_AF0_D2PWREN       ((uint8_t)0x00)  /* Domain 2 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above   */

+#if defined(DUAL_CORE)

+#define GPIO_AF0_C2DSLEEP      ((uint8_t)0x00)  /* Cortex-M4 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above  */

+#define GPIO_AF0_C2SLEEP       ((uint8_t)0x00)  /* Cortex-M4 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above       */

+#endif /* DUAL_CORE */

+#endif /* PWR_CPUCR_PDDS_D2 */

+

+/**

+  * @brief   AF 1 selection

+  */

+#define GPIO_AF1_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping   */

+#define GPIO_AF1_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping   */

+#define GPIO_AF1_TIM16         ((uint8_t)0x01)  /* TIM16 Alternate Function mapping  */

+#define GPIO_AF1_TIM17         ((uint8_t)0x01)  /* TIM17 Alternate Function mapping  */

+#define GPIO_AF1_LPTIM1        ((uint8_t)0x01)  /* LPTIM1 Alternate Function mapping */

+#if defined(HRTIM1)

+#define GPIO_AF1_HRTIM1        ((uint8_t)0x01)  /* HRTIM1 Alternate Function mapping */

+#endif /* HRTIM1 */

+

+/**

+  * @brief   AF 2 selection

+  */

+#define GPIO_AF2_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping   */

+#define GPIO_AF2_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping   */

+#define GPIO_AF2_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping   */

+#define GPIO_AF2_TIM12         ((uint8_t)0x02)  /* TIM12 Alternate Function mapping  */

+#define GPIO_AF2_SAI1          ((uint8_t)0x02)  /* SAI1 Alternate Function mapping   */

+#if defined(HRTIM1)

+#define GPIO_AF2_HRTIM1        ((uint8_t)0x02)  /* HRTIM1 Alternate Function mapping */

+#endif /* HRTIM1 */

+#define GPIO_AF2_TIM15         ((uint8_t)0x02)  /* TIM15 Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx */

+

+/**

+  * @brief   AF 3 selection

+  */

+#define GPIO_AF3_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping   */

+#define GPIO_AF3_LPTIM2        ((uint8_t)0x03)  /* LPTIM2 Alternate Function mapping */

+#define GPIO_AF3_DFSDM1        ((uint8_t)0x03)  /* DFSDM Alternate Function mapping  */

+#define GPIO_AF3_LPTIM3        ((uint8_t)0x03)  /* LPTIM3 Alternate Function mapping */

+#define GPIO_AF3_LPTIM4        ((uint8_t)0x03)  /* LPTIM4 Alternate Function mapping */

+#define GPIO_AF3_LPTIM5        ((uint8_t)0x03)  /* LPTIM5 Alternate Function mapping */

+#define GPIO_AF3_LPUART        ((uint8_t)0x03)  /* LPUART Alternate Function mapping */

+#if defined(OCTOSPIM)

+#define GPIO_AF3_OCTOSPIM_P1   ((uint8_t)0x03)  /* OCTOSPI Manager Port 1 Alternate Function mapping */

+#define GPIO_AF3_OCTOSPIM_P2   ((uint8_t)0x03)  /* OCTOSPI Manager Port 2 Alternate Function mapping */

+#endif /* OCTOSPIM */

+#if defined(HRTIM1)

+#define GPIO_AF3_HRTIM1        ((uint8_t)0x03)  /* HRTIM1 Alternate Function mapping */

+#endif /* HRTIM1 */

+

+/**

+  * @brief   AF 4 selection

+  */

+#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping   */

+#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping   */

+#define GPIO_AF4_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping   */

+#define GPIO_AF4_I2C4          ((uint8_t)0x04)  /* I2C4 Alternate Function mapping   */

+#define GPIO_AF4_TIM15         ((uint8_t)0x04)  /* TIM15 Alternate Function mapping  */

+#define GPIO_AF4_CEC           ((uint8_t)0x04)  /* CEC Alternate Function mapping    */

+#define GPIO_AF4_LPTIM2        ((uint8_t)0x04)  /* LPTIM2 Alternate Function mapping */

+#define GPIO_AF4_USART1        ((uint8_t)0x04)  /* USART1 Alternate Function mapping */

+#define GPIO_AF4_DFSDM1        ((uint8_t)0x04)  /* DFSDM  Alternate Function mapping */

+#if defined(DFSDM2_BASE)

+#define GPIO_AF4_DFSDM2        ((uint8_t)0x04)  /* DFSDM2 Alternate Function mapping */

+#endif /* DFSDM2_BASE */

+#if defined(PSSI)

+#define GPIO_AF4_PSSI          ((uint8_t)0x04)  /* PSSI Alternate Function mapping   */

+#endif /* PSSI */

+

+/**

+  * @brief   AF 5 selection

+  */

+#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping   */

+#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2 Alternate Function mapping   */

+#define GPIO_AF5_SPI3          ((uint8_t)0x05)  /* SPI3 Alternate Function mapping   */

+#define GPIO_AF5_SPI4          ((uint8_t)0x05)  /* SPI4 Alternate Function mapping   */

+#define GPIO_AF5_SPI5          ((uint8_t)0x05)  /* SPI5 Alternate Function mapping   */

+#define GPIO_AF5_SPI6          ((uint8_t)0x05)  /* SPI6 Alternate Function mapping   */

+#define GPIO_AF5_CEC           ((uint8_t)0x05)  /* CEC  Alternate Function mapping   */

+

+/**

+  * @brief   AF 6 selection

+  */

+#define GPIO_AF6_SPI2          ((uint8_t)0x06)  /* SPI2 Alternate Function mapping   */

+#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3 Alternate Function mapping   */

+#define GPIO_AF6_SAI1          ((uint8_t)0x06)  /* SAI1 Alternate Function mapping   */

+#define GPIO_AF6_I2C4          ((uint8_t)0x06)  /* I2C4 Alternate Function mapping   */

+#define GPIO_AF6_DFSDM1        ((uint8_t)0x06)  /* DFSDM Alternate Function mapping  */

+#define GPIO_AF6_UART4         ((uint8_t)0x06)  /* UART4 Alternate Function mapping  */

+#if defined(DFSDM2_BASE)

+#define GPIO_AF6_DFSDM2        ((uint8_t)0x06)  /* DFSDM2 Alternate Function mapping */

+#endif /* DFSDM2_BASE */

+#if defined(SAI3)

+#define GPIO_AF6_SAI3          ((uint8_t)0x06)  /* SAI3 Alternate Function mapping   */

+#endif /* SAI3 */

+#if defined(OCTOSPIM)

+#define GPIO_AF6_OCTOSPIM_P1   ((uint8_t)0x06)  /* OCTOSPI Manager Port 1 Alternate Function mapping */

+#endif /* OCTOSPIM */

+

+/**

+  * @brief   AF 7 selection

+  */

+#define GPIO_AF7_SPI2          ((uint8_t)0x07)  /* SPI2 Alternate Function mapping   */

+#define GPIO_AF7_SPI3          ((uint8_t)0x07)  /* SPI3 Alternate Function mapping   */

+#define GPIO_AF7_SPI6          ((uint8_t)0x07)  /* SPI6 Alternate Function mapping   */

+#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping */

+#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping */

+#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping */

+#define GPIO_AF7_USART6        ((uint8_t)0x07)  /* USART6 Alternate Function mapping */

+#define GPIO_AF7_UART7         ((uint8_t)0x07)  /* UART7 Alternate Function mapping  */

+#define GPIO_AF7_DFSDM1        ((uint8_t)0x07)  /* DFSDM Alternate Function mapping  */

+#define GPIO_AF7_SDMMC1        ((uint8_t)0x07)  /* SDMMC1 Alternate Function mapping */

+

+/**

+  * @brief   AF 8 selection

+  */

+#define GPIO_AF8_SPI6          ((uint8_t)0x08)  /* SPI6 Alternate Function mapping   */

+#define GPIO_AF8_SAI2          ((uint8_t)0x08)  /* SAI2 Alternate Function mapping   */

+#define GPIO_AF8_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */

+#define GPIO_AF8_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */

+#define GPIO_AF8_UART8         ((uint8_t)0x08)  /* UART8 Alternate Function mapping  */

+#define GPIO_AF8_SPDIF         ((uint8_t)0x08)  /* SPDIF Alternate Function mapping  */

+#define GPIO_AF8_LPUART        ((uint8_t)0x08)  /* LPUART Alternate Function mapping */

+#define GPIO_AF8_SDMMC1        ((uint8_t)0x08)  /* SDMMC1 Alternate Function mapping */

+#if defined(SAI4)

+#define GPIO_AF8_SAI4          ((uint8_t)0x08)  /* SAI4 Alternate Function mapping   */

+#endif /* SAI4 */

+

+/**

+  * @brief   AF 9 selection

+  */

+#define GPIO_AF9_FDCAN1        ((uint8_t)0x09)  /* FDCAN1 Alternate Function mapping   */

+#define GPIO_AF9_FDCAN2        ((uint8_t)0x09)  /* FDCAN2 Alternate Function mapping   */

+#define GPIO_AF9_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping    */

+#define GPIO_AF9_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping    */

+#define GPIO_AF9_SDMMC2        ((uint8_t)0x09)  /* SDMMC2 Alternate Function mapping   */

+#define GPIO_AF9_LTDC          ((uint8_t)0x09)  /* LTDC Alternate Function mapping     */

+#define GPIO_AF9_SPDIF         ((uint8_t)0x09)  /* SPDIF Alternate Function mapping    */

+#define GPIO_AF9_FMC           ((uint8_t)0x09)  /* FMC Alternate Function mapping      */

+#if defined(QUADSPI)

+#define GPIO_AF9_QUADSPI       ((uint8_t)0x09)  /* QUADSPI Alternate Function mapping  */

+#endif /* QUADSPI */

+#if defined(SAI4)

+#define GPIO_AF9_SAI4          ((uint8_t)0x09)  /* SAI4 Alternate Function mapping     */

+#endif /* SAI4 */

+#if defined(OCTOSPIM)

+#define GPIO_AF9_OCTOSPIM_P1   ((uint8_t)0x09)  /* OCTOSPI Manager Port 1 Alternate Function mapping */

+#define GPIO_AF9_OCTOSPIM_P2   ((uint8_t)0x09)  /* OCTOSPI Manager Port 2 Alternate Function mapping */

+#endif /* OCTOSPIM */

+

+/**

+  * @brief   AF 10 selection

+  */

+#define GPIO_AF10_SAI2          ((uint8_t)0x0A)  /* SAI2 Alternate Function mapping                                             */

+#define GPIO_AF10_SDMMC2        ((uint8_t)0x0A)  /* SDMMC2 Alternate Function mapping                                           */

+#if defined(USB2_OTG_FS)

+#define GPIO_AF10_OTG2_FS       ((uint8_t)0x0A)  /* OTG2_FS Alternate Function mapping                                          */

+#endif /*USB2_OTG_FS*/

+#define GPIO_AF10_COMP1         ((uint8_t)0x0A)  /* COMP1 Alternate Function mapping                                            */

+#define GPIO_AF10_COMP2         ((uint8_t)0x0A)  /* COMP2 Alternate Function mapping                                            */

+#if defined(LTDC)

+#define GPIO_AF10_LTDC          ((uint8_t)0x0A)  /* LTDC Alternate Function mapping                                             */

+#endif /*LTDC*/

+#define GPIO_AF10_CRS_SYNC      ((uint8_t)0x0A)  /* CRS Sync Alternate Function mapping : available on STM32H7 Rev.B and above  */

+#if defined(QUADSPI)

+#define GPIO_AF10_QUADSPI       ((uint8_t)0x0A)  /* QUADSPI Alternate Function mapping                                          */

+#endif /* QUADSPI */

+#if defined(SAI4)

+#define GPIO_AF10_SAI4          ((uint8_t)0x0A)  /* SAI4 Alternate Function mapping                                             */

+#endif /* SAI4 */

+#if !defined(USB2_OTG_FS)

+#define GPIO_AF10_OTG1_FS       ((uint8_t)0x0A)  /* OTG1_FS Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx */

+#endif /* !USB2_OTG_FS */

+#define GPIO_AF10_OTG1_HS       ((uint8_t)0x0A)  /* OTG1_HS Alternate Function mapping                                          */

+#if defined(OCTOSPIM)

+#define GPIO_AF10_OCTOSPIM_P1   ((uint8_t)0x0A)  /* OCTOSPI Manager Port 1 Alternate Function mapping */

+#endif /* OCTOSPIM */

+#define GPIO_AF10_TIM8          ((uint8_t)0x0A)  /* TIM8 Alternate Function mapping                                             */

+

+/**

+  * @brief   AF 11 selection

+  */

+#define GPIO_AF11_SWP           ((uint8_t)0x0B)  /* SWP Alternate Function mapping     */

+#define GPIO_AF11_MDIOS         ((uint8_t)0x0B)  /* MDIOS Alternate Function mapping   */

+#define GPIO_AF11_UART7         ((uint8_t)0x0B)  /* UART7 Alternate Function mapping   */

+#define GPIO_AF11_SDMMC2        ((uint8_t)0x0B)  /* SDMMC2 Alternate Function mapping  */

+#define GPIO_AF11_DFSDM1        ((uint8_t)0x0B)  /* DFSDM1 Alternate Function mapping  */

+#define GPIO_AF11_COMP1         ((uint8_t)0x0B)  /* COMP1 Alternate Function mapping   */

+#define GPIO_AF11_COMP2         ((uint8_t)0x0B)  /* COMP2 Alternate Function mapping   */

+#define GPIO_AF11_TIM1          ((uint8_t)0x0B)  /* TIM1 Alternate Function mapping    */

+#define GPIO_AF11_TIM8          ((uint8_t)0x0B)  /* TIM8 Alternate Function mapping    */

+#define GPIO_AF11_I2C4          ((uint8_t)0x0B)  /* I2C4 Alternate Function mapping    */

+#if defined(DFSDM2_BASE)

+#define GPIO_AF11_DFSDM2        ((uint8_t)0x0B)  /* DFSDM2 Alternate Function mapping  */

+#endif /* DFSDM2_BASE */

+#if defined(USART10)

+#define GPIO_AF11_USART10       ((uint8_t)0x0B)  /* USART10 Alternate Function mapping */

+#endif /* USART10 */

+#if defined(UART9)

+#define GPIO_AF11_UART9         ((uint8_t)0x0B)  /* UART9 Alternate Function mapping   */

+#endif /* UART9 */

+#if defined(ETH)

+#define GPIO_AF11_ETH           ((uint8_t)0x0B)  /* ETH Alternate Function mapping     */

+#endif /* ETH */

+#if defined(LTDC)

+#define GPIO_AF11_LTDC          ((uint8_t)0x0B)  /* LTDC Alternate Function mapping : available on STM32H7A3xxx/STM32H7B3xxx/STM32H7B0xxx  */

+#endif /*LTDC*/

+#if defined(OCTOSPIM)

+#define GPIO_AF11_OCTOSPIM_P1   ((uint8_t)0x0B)  /* OCTOSPI Manager Port 1 Alternate Function mapping */

+#endif /* OCTOSPIM */

+

+/**

+  * @brief   AF 12 selection

+  */

+#define GPIO_AF12_FMC           ((uint8_t)0x0C)  /* FMC Alternate Function mapping     */

+#define GPIO_AF12_SDMMC1        ((uint8_t)0x0C)  /* SDMMC1 Alternate Function mapping  */

+#define GPIO_AF12_MDIOS         ((uint8_t)0x0C)  /* MDIOS Alternate Function mapping   */

+#define GPIO_AF12_COMP1         ((uint8_t)0x0C)  /* COMP1 Alternate Function mapping   */

+#define GPIO_AF12_COMP2         ((uint8_t)0x0C)  /* COMP2 Alternate Function mapping   */

+#define GPIO_AF12_TIM1          ((uint8_t)0x0C)  /* TIM1 Alternate Function mapping    */

+#define GPIO_AF12_TIM8          ((uint8_t)0x0C)  /* TIM8 Alternate Function mapping    */

+#if defined(LTDC)

+#define GPIO_AF12_LTDC          ((uint8_t)0x0C)  /* LTDC Alternate Function mapping    */

+#endif /*LTDC*/

+#if defined(USB2_OTG_FS)

+#define GPIO_AF12_OTG1_FS       ((uint8_t)0x0C)  /* OTG1_FS Alternate Function mapping */

+#endif /* USB2_OTG_FS */

+

+/**

+  * @brief   AF 13 selection

+  */

+#define GPIO_AF13_DCMI          ((uint8_t)0x0D)   /* DCMI Alternate Function mapping  */

+#define GPIO_AF13_COMP1         ((uint8_t)0x0D)   /* COMP1 Alternate Function mapping */

+#define GPIO_AF13_COMP2         ((uint8_t)0x0D)   /* COMP2 Alternate Function mapping */

+#if defined(LTDC)

+#define GPIO_AF13_LTDC          ((uint8_t)0x0D)   /* LTDC Alternate Function mapping  */

+#endif /*LTDC*/

+#if defined(DSI)

+#define GPIO_AF13_DSI           ((uint8_t)0x0D)   /* DSI Alternate Function mapping   */

+#endif /* DSI */

+#if defined(PSSI)

+#define GPIO_AF13_PSSI          ((uint8_t)0x0D)   /* PSSI Alternate Function mapping  */

+#endif /* PSSI */

+#define GPIO_AF13_TIM1          ((uint8_t)0x0D)    /* TIM1 Alternate Function mapping */

+

+/**

+  * @brief   AF 14 selection

+  */

+#define GPIO_AF14_LTDC         ((uint8_t)0x0E)   /* LTDC Alternate Function mapping  */

+#define GPIO_AF14_UART5        ((uint8_t)0x0E)   /* UART5 Alternate Function mapping */

+

+/**

+  * @brief   AF 15 selection

+  */

+#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */

+

+#define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)

+

+

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup GPIOEx_Exported_Macros GPIO Exported Macros

+  * @{

+  */

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup GPIOEx_Exported_Functions GPIO Exported Functions

+  * @{

+  */

+/**

+  * @}

+  */

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup GPIOEx_Private_Constants GPIO Private Constants

+  * @{

+  */

+

+/**

+  * @brief   GPIO pin available on the platform

+  */

+/* Defines the available pins per GPIOs */

+#define GPIOA_PIN_AVAILABLE  GPIO_PIN_All

+#define GPIOB_PIN_AVAILABLE  GPIO_PIN_All

+#define GPIOC_PIN_AVAILABLE  GPIO_PIN_All

+#define GPIOD_PIN_AVAILABLE  GPIO_PIN_All

+#define GPIOE_PIN_AVAILABLE  GPIO_PIN_All

+#define GPIOF_PIN_AVAILABLE  GPIO_PIN_All

+#define GPIOG_PIN_AVAILABLE  GPIO_PIN_All

+#define GPIOI_PIN_AVAILABLE  GPIO_PIN_All

+#define GPIOJ_PIN_AVAILABLE  GPIO_PIN_All

+#define GPIOH_PIN_AVAILABLE  GPIO_PIN_All

+#define GPIOK_PIN_AVAILABLE  (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | \

+                              GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup GPIOEx_Private_Macros GPIO Private Macros

+  * @{

+  */

+/** @defgroup GPIOEx_Get_Port_Index GPIO Get Port Index

+  * @{

+  */

+#define GPIO_GET_INDEX(__GPIOx__)  (((__GPIOx__) == (GPIOA))? 0UL :\

+                                    ((__GPIOx__) == (GPIOB))? 1UL :\

+                                    ((__GPIOx__) == (GPIOC))? 2UL :\

+                                    ((__GPIOx__) == (GPIOD))? 3UL :\

+                                    ((__GPIOx__) == (GPIOE))? 4UL :\

+                                    ((__GPIOx__) == (GPIOF))? 5UL :\

+                                    ((__GPIOx__) == (GPIOG))? 6UL :\

+                                    ((__GPIOx__) == (GPIOH))? 7UL :\

+                                    ((__GPIOx__) == (GPIOI))? 8UL :\

+                                    ((__GPIOx__) == (GPIOJ))? 9UL : 10UL)

+/**

+  * @}

+  */

+

+/** @defgroup GPIOEx_IS_Alternat_function_selection GPIO Check Alternate Function

+  * @{

+  */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private functions ---------------------------------------------------------*/

+/** @defgroup GPIOEx_Private_Functions GPIO Private Functions

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_GPIO_EX_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_hash.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_hash.h
new file mode 100644
index 0000000000..e1782379ac
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_hash.h
@@ -0,0 +1,621 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_hash.h

+  * @author  MCD Application Team

+  * @brief   Header file of HASH HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_HASH_H

+#define STM32H7xx_HAL_HASH_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+#if defined (HASH)

+/** @addtogroup HASH

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup HASH_Exported_Types HASH Exported Types

+  * @{

+  */

+

+/**

+  * @brief  HASH Configuration Structure definition

+  */

+typedef struct

+{

+  uint32_t DataType;    /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit data.

+                              This parameter can be a value of @ref HASH_Data_Type. */

+

+  uint32_t KeySize;     /*!< The key size is used only in HMAC operation. */

+

+  uint8_t* pKey;        /*!< The key is used only in HMAC operation. */

+

+} HASH_InitTypeDef;

+

+/**

+  * @brief HAL State structures definition

+  */

+typedef enum

+{

+  HAL_HASH_STATE_RESET             = 0x00U,    /*!< Peripheral is not initialized            */

+  HAL_HASH_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use */

+  HAL_HASH_STATE_BUSY              = 0x02U,    /*!< Processing (hashing) is ongoing          */

+  HAL_HASH_STATE_TIMEOUT           = 0x06U,    /*!< Timeout state                            */

+  HAL_HASH_STATE_ERROR             = 0x07U,    /*!< Error state                              */

+  HAL_HASH_STATE_SUSPENDED         = 0x08U     /*!< Suspended state                          */

+}HAL_HASH_StateTypeDef;

+

+/**

+  * @brief HAL phase structures definition

+  */

+typedef enum

+{

+  HAL_HASH_PHASE_READY             = 0x01U,    /*!< HASH peripheral is ready to start                    */

+  HAL_HASH_PHASE_PROCESS           = 0x02U,    /*!< HASH peripheral is in HASH processing phase          */

+  HAL_HASH_PHASE_HMAC_STEP_1       = 0x03U,    /*!< HASH peripheral is in HMAC step 1 processing phase

+                                              (step 1 consists in entering the inner hash function key) */

+  HAL_HASH_PHASE_HMAC_STEP_2       = 0x04U,    /*!< HASH peripheral is in HMAC step 2 processing phase

+                                              (step 2 consists in entering the message text) */

+  HAL_HASH_PHASE_HMAC_STEP_3       = 0x05U     /*!< HASH peripheral is in HMAC step 3 processing phase

+                                              (step 3 consists in entering the outer hash function key) */

+}HAL_HASH_PhaseTypeDef;

+

+/**

+  * @brief HAL HASH mode suspend definitions

+  */

+typedef enum

+{

+  HAL_HASH_SUSPEND_NONE            = 0x00U,    /*!< HASH peripheral suspension not requested */

+  HAL_HASH_SUSPEND                 = 0x01U     /*!< HASH peripheral suspension is requested  */

+}HAL_HASH_SuspendTypeDef;

+

+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)

+/**

+  * @brief  HAL HASH common Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_HASH_MSPINIT_CB_ID           = 0x00U,    /*!< HASH MspInit callback ID     */

+  HAL_HASH_MSPDEINIT_CB_ID         = 0x01U,    /*!< HASH MspDeInit callback ID   */

+  HAL_HASH_INPUTCPLT_CB_ID         = 0x02U,    /*!< HASH input completion callback ID */

+  HAL_HASH_DGSTCPLT_CB_ID          = 0x03U,    /*!< HASH digest computation completion callback ID */

+  HAL_HASH_ERROR_CB_ID             = 0x04U,    /*!< HASH error callback ID     */

+}HAL_HASH_CallbackIDTypeDef;

+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */

+

+

+/**

+  * @brief  HASH Handle Structure definition

+  */

+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)

+typedef struct __HASH_HandleTypeDef

+#else

+typedef struct

+#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */

+{

+  HASH_InitTypeDef           Init;             /*!< HASH required parameters */

+

+  uint8_t                    *pHashInBuffPtr;  /*!< Pointer to input buffer */

+

+  uint8_t                    *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */

+

+  uint8_t                    *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */

+

+  uint8_t                    *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */

+

+  uint32_t                   HashBuffSize;     /*!< Size of buffer to be processed */

+

+  __IO uint32_t              HashInCount;      /*!< Counter of inputted data */

+

+  __IO uint32_t              HashITCounter;    /*!< Counter of issued interrupts */

+

+  __IO uint32_t              HashKeyCount;     /*!< Counter for Key inputted data (HMAC only) */

+

+  HAL_StatusTypeDef          Status;           /*!< HASH peripheral status   */

+

+  HAL_HASH_PhaseTypeDef      Phase;            /*!< HASH peripheral phase   */

+

+  DMA_HandleTypeDef          *hdmain;          /*!< HASH In DMA Handle parameters */

+

+  HAL_LockTypeDef            Lock;             /*!< Locking object */

+

+  __IO HAL_HASH_StateTypeDef State;            /*!< HASH peripheral state */

+

+  HAL_HASH_SuspendTypeDef    SuspendRequest;   /*!< HASH peripheral suspension request flag */

+

+  FlagStatus                 DigestCalculationDisable;  /*!< Digest calculation phase skip (MDMAT bit control) for multi-buffers DMA-based HMAC computation */

+

+  __IO uint32_t              NbWordsAlreadyPushed;      /*!< Numbers of words already pushed in FIFO before inputting new block */

+

+  __IO  uint32_t             ErrorCode;        /*!< HASH Error code */

+

+  __IO  uint32_t             Accumulation;     /*!< HASH multi buffers accumulation flag */

+

+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)

+  void    (* InCpltCallback)( struct __HASH_HandleTypeDef * hhash);    /*!< HASH input completion callback */

+

+  void    (* DgstCpltCallback)( struct __HASH_HandleTypeDef * hhash);  /*!< HASH digest computation completion callback */

+

+  void    (* ErrorCallback)( struct __HASH_HandleTypeDef * hhash);     /*!< HASH error callback */

+

+  void    (* MspInitCallback)( struct __HASH_HandleTypeDef * hhash);   /*!< HASH Msp Init callback */

+

+  void    (* MspDeInitCallback)( struct __HASH_HandleTypeDef * hhash); /*!< HASH Msp DeInit callback */

+

+#endif /* (USE_HAL_HASH_REGISTER_CALLBACKS) */

+} HASH_HandleTypeDef;

+

+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)

+/**

+  * @brief  HAL HASH Callback pointer definition

+  */

+typedef  void (*pHASH_CallbackTypeDef)(HASH_HandleTypeDef * hhash); /*!< pointer to a HASH common callback functions */

+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+

+/** @defgroup HASH_Exported_Constants  HASH Exported Constants

+  * @{

+  */

+

+/** @defgroup HASH_Algo_Selection   HASH algorithm selection

+  * @{

+  */

+#define HASH_ALGOSELECTION_SHA1      0x00000000U /*!< HASH function is SHA1   */

+#define HASH_ALGOSELECTION_MD5       HASH_CR_ALGO_0     /*!< HASH function is MD5    */

+#define HASH_ALGOSELECTION_SHA224    HASH_CR_ALGO_1     /*!< HASH function is SHA224 */

+#define HASH_ALGOSELECTION_SHA256    HASH_CR_ALGO       /*!< HASH function is SHA256 */

+/**

+  * @}

+  */

+

+/** @defgroup HASH_Algorithm_Mode   HASH algorithm mode

+  * @{

+  */

+#define HASH_ALGOMODE_HASH         0x00000000U /*!< Algorithm is HASH */

+#define HASH_ALGOMODE_HMAC         HASH_CR_MODE           /*!< Algorithm is HMAC */

+/**

+  * @}

+  */

+

+/** @defgroup HASH_Data_Type      HASH input data type

+  * @{

+  */

+#define HASH_DATATYPE_32B          0x00000000U /*!< 32-bit data. No swapping                     */

+#define HASH_DATATYPE_16B          HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped       */

+#define HASH_DATATYPE_8B           HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped            */

+#define HASH_DATATYPE_1B           HASH_CR_DATATYPE   /*!< 1-bit data. In the word all bits are swapped */

+/**

+  * @}

+  */

+

+/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode   HMAC key length type

+  * @{

+  */

+#define HASH_HMAC_KEYTYPE_SHORTKEY      0x00000000U /*!< HMAC Key size is <= 64 bytes */

+#define HASH_HMAC_KEYTYPE_LONGKEY       HASH_CR_LKEY           /*!< HMAC Key size is > 64 bytes  */

+/**

+  * @}

+  */

+

+/** @defgroup HASH_flags_definition  HASH flags definitions

+  * @{

+  */

+#define HASH_FLAG_DINIS            HASH_SR_DINIS  /*!< 16 locations are free in the DIN : a new block can be entered in the Peripheral */

+#define HASH_FLAG_DCIS             HASH_SR_DCIS   /*!< Digest calculation complete                                                     */

+#define HASH_FLAG_DMAS             HASH_SR_DMAS   /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing                      */

+#define HASH_FLAG_BUSY             HASH_SR_BUSY   /*!< The hash core is Busy, processing a block of data                               */

+#define HASH_FLAG_DINNE            HASH_CR_DINNE  /*!< DIN not empty : the input buffer contains at least one word of data             */

+

+/**

+  * @}

+  */

+

+/** @defgroup HASH_interrupts_definition   HASH interrupts definitions

+  * @{

+  */

+#define HASH_IT_DINI               HASH_IMR_DINIE  /*!< A new block can be entered into the input buffer (DIN) */

+#define HASH_IT_DCI                HASH_IMR_DCIE   /*!< Digest calculation complete                            */

+

+/**

+  * @}

+  */

+/** @defgroup HASH_alias HASH API alias

+  * @{

+  */

+#define HAL_HASHEx_IRQHandler   HAL_HASH_IRQHandler  /*!< HAL_HASHEx_IRQHandler() is re-directed to HAL_HASH_IRQHandler() for compatibility with legacy code */

+/**

+  * @}

+  */

+

+/** @defgroup HASH_Error_Definition   HASH Error Definition

+  * @{

+  */

+#define  HAL_HASH_ERROR_NONE             0x00000000U   /*!< No error                */

+#define  HAL_HASH_ERROR_IT               0x00000001U   /*!< IT-based process error  */

+#define  HAL_HASH_ERROR_DMA              0x00000002U   /*!< DMA-based process error */

+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1U)

+#define  HAL_HASH_ERROR_INVALID_CALLBACK 0x00000004U   /*!< Invalid Callback error  */

+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macros -----------------------------------------------------------*/

+/** @defgroup HASH_Exported_Macros HASH Exported Macros

+  * @{

+  */

+

+/** @brief  Check whether or not the specified HASH flag is set.

+  * @param  __FLAG__ specifies the flag to check.

+  *        This parameter can be one of the following values:

+  *            @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.

+  *            @arg @ref HASH_FLAG_DCIS Digest calculation complete.

+  *            @arg @ref HASH_FLAG_DMAS DMA interface is enabled (DMAE=1) or a transfer is ongoing.

+  *            @arg @ref HASH_FLAG_BUSY The hash core is Busy : processing a block of data.

+  *            @arg @ref HASH_FLAG_DINNE DIN not empty : the input buffer contains at least one word of data.

+  * @retval The new state of __FLAG__ (TRUE or FALSE).

+  */

+#define __HAL_HASH_GET_FLAG(__FLAG__)  (((__FLAG__) > 8U)  ?                    \

+                                       ((HASH->CR & (__FLAG__)) == (__FLAG__)) :\

+                                       ((HASH->SR & (__FLAG__)) == (__FLAG__)) )

+

+

+/** @brief  Clear the specified HASH flag.

+  * @param  __FLAG__ specifies the flag to clear.

+  *        This parameter can be one of the following values:

+  *            @arg @ref HASH_FLAG_DINIS A new block can be entered into the input buffer.

+  *            @arg @ref HASH_FLAG_DCIS Digest calculation complete

+  * @retval None

+  */

+#define __HAL_HASH_CLEAR_FLAG(__FLAG__) CLEAR_BIT(HASH->SR, (__FLAG__))

+

+

+/** @brief  Enable the specified HASH interrupt.

+  * @param  __INTERRUPT__ specifies the HASH interrupt source to enable.

+  *          This parameter can be one of the following values:

+  *            @arg @ref HASH_IT_DINI  A new block can be entered into the input buffer (DIN)

+  *            @arg @ref HASH_IT_DCI   Digest calculation complete

+  * @retval None

+  */

+#define __HAL_HASH_ENABLE_IT(__INTERRUPT__)   SET_BIT(HASH->IMR, (__INTERRUPT__))

+

+/** @brief  Disable the specified HASH interrupt.

+  * @param  __INTERRUPT__ specifies the HASH interrupt source to disable.

+  *          This parameter can be one of the following values:

+  *            @arg @ref HASH_IT_DINI  A new block can be entered into the input buffer (DIN)

+  *            @arg @ref HASH_IT_DCI   Digest calculation complete

+  * @retval None

+  */

+#define __HAL_HASH_DISABLE_IT(__INTERRUPT__)   CLEAR_BIT(HASH->IMR, (__INTERRUPT__))

+

+/** @brief Reset HASH handle state.

+  * @param  __HANDLE__ HASH handle.

+  * @retval None

+  */

+

+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)

+#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) do{\

+                                                      (__HANDLE__)->State = HAL_HASH_STATE_RESET;\

+                                                      (__HANDLE__)->MspInitCallback = NULL;      \

+                                                      (__HANDLE__)->MspDeInitCallback = NULL;    \

+                                                     }while(0)

+#else

+#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)

+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */

+

+

+/** @brief Reset HASH handle status.

+  * @param  __HANDLE__ HASH handle.

+  * @retval None

+  */

+#define __HAL_HASH_RESET_HANDLE_STATUS(__HANDLE__) ((__HANDLE__)->Status = HAL_OK)

+

+/**

+  * @brief  Enable the multi-buffer DMA transfer mode.

+  * @note   This bit is set when hashing large files when multiple DMA transfers are needed.

+  * @retval None

+  */

+#define __HAL_HASH_SET_MDMAT()          SET_BIT(HASH->CR, HASH_CR_MDMAT)

+

+/**

+  * @brief  Disable the multi-buffer DMA transfer mode.

+  * @retval None

+  */

+#define __HAL_HASH_RESET_MDMAT()        CLEAR_BIT(HASH->CR, HASH_CR_MDMAT)

+

+

+/**

+  * @brief Start the digest computation.

+  * @retval None

+  */

+#define __HAL_HASH_START_DIGEST()       SET_BIT(HASH->STR, HASH_STR_DCAL)

+

+/**

+  * @brief Set the number of valid bits in the last word written in data register DIN.

+  * @param  __SIZE__ size in bytes of last data written in Data register.

+  * @retval None

+*/

+#define  __HAL_HASH_SET_NBVALIDBITS(__SIZE__)    MODIFY_REG(HASH->STR, HASH_STR_NBLW, 8U * ((__SIZE__) % 4U))

+

+/**

+  * @brief Reset the HASH core.

+  * @retval None

+  */

+#define __HAL_HASH_INIT()       SET_BIT(HASH->CR, HASH_CR_INIT)

+

+/**

+  * @}

+  */

+

+

+/* Private macros --------------------------------------------------------*/

+/** @defgroup HASH_Private_Macros   HASH Private Macros

+  * @{

+  */

+/**

+  * @brief  Return digest length in bytes.

+  * @retval Digest length

+  */

+#define HASH_DIGEST_LENGTH() ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA1)   ?  20U : \

+                             ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA224) ?  28U : \

+                             ((READ_BIT(HASH->CR, HASH_CR_ALGO) == HASH_ALGOSELECTION_SHA256) ?  32U : 16U ) ) )

+/**

+  * @brief  Return number of words already pushed in the FIFO.

+  * @retval Number of words already pushed in the FIFO

+  */

+#define HASH_NBW_PUSHED() ((READ_BIT(HASH->CR, HASH_CR_NBW)) >> 8U)

+

+/**

+  * @brief Ensure that HASH input data type is valid.

+  * @param __DATATYPE__ HASH input data type.

+  * @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)

+  */

+#define IS_HASH_DATATYPE(__DATATYPE__) (((__DATATYPE__) == HASH_DATATYPE_32B)|| \

+                                        ((__DATATYPE__) == HASH_DATATYPE_16B)|| \

+                                        ((__DATATYPE__) == HASH_DATATYPE_8B) || \

+                                        ((__DATATYPE__) == HASH_DATATYPE_1B))

+

+/**

+  * @brief Ensure that input data buffer size is valid for multi-buffer HASH

+  *        processing in DMA mode.

+  * @note  This check is valid only for multi-buffer HASH processing in DMA mode.

+  * @param __SIZE__ input data buffer size.

+  * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)

+  */

+#define IS_HASH_DMA_MULTIBUFFER_SIZE(__SIZE__)  ((READ_BIT(HASH->CR, HASH_CR_MDMAT) == 0U) || (((__SIZE__) % 4U) == 0U))

+

+/**

+  * @brief Ensure that input data buffer size is valid for multi-buffer HMAC

+  *        processing in DMA mode.

+  * @note  This check is valid only for multi-buffer HMAC processing in DMA mode.

+  * @param __HANDLE__ HASH handle.

+  * @param __SIZE__ input data buffer size.

+  * @retval SET (__SIZE__ is valid) or RESET (__SIZE__ is invalid)

+  */

+#define IS_HMAC_DMA_MULTIBUFFER_SIZE(__HANDLE__,__SIZE__)  ((((__HANDLE__)->DigestCalculationDisable) == RESET) || (((__SIZE__) % 4U) == 0U))

+/**

+  * @brief Ensure that handle phase is set to HASH processing.

+  * @param __HANDLE__ HASH handle.

+  * @retval SET (handle phase is set to HASH processing) or RESET (handle phase is not set to HASH processing)

+  */

+#define IS_HASH_PROCESSING(__HANDLE__)  ((__HANDLE__)->Phase == HAL_HASH_PHASE_PROCESS)

+

+/**

+  * @brief Ensure that handle phase is set to HMAC processing.

+  * @param __HANDLE__ HASH handle.

+  * @retval SET (handle phase is set to HMAC processing) or RESET (handle phase is not set to HMAC processing)

+  */

+#define IS_HMAC_PROCESSING(__HANDLE__)  (((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_1) || \

+                                         ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_2) || \

+                                         ((__HANDLE__)->Phase == HAL_HASH_PHASE_HMAC_STEP_3))

+

+/**

+  * @}

+  */

+

+/* Include HASH HAL Extended module */

+#include "stm32h7xx_hal_hash_ex.h"

+/* Exported functions --------------------------------------------------------*/

+

+/** @addtogroup HASH_Exported_Functions HASH Exported Functions

+  * @{

+  */

+

+/** @addtogroup HASH_Exported_Functions_Group1 Initialization and de-initialization functions

+  * @{

+  */

+

+/* Initialization/de-initialization methods  **********************************/

+HAL_StatusTypeDef HAL_HASH_Init(HASH_HandleTypeDef *hhash);

+HAL_StatusTypeDef HAL_HASH_DeInit(HASH_HandleTypeDef *hhash);

+void HAL_HASH_MspInit(HASH_HandleTypeDef *hhash);

+void HAL_HASH_MspDeInit(HASH_HandleTypeDef *hhash);

+void HAL_HASH_InCpltCallback(HASH_HandleTypeDef *hhash);

+void HAL_HASH_DgstCpltCallback(HASH_HandleTypeDef *hhash);

+void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);

+/* Callbacks Register/UnRegister functions  ***********************************/

+#if (USE_HAL_HASH_REGISTER_CALLBACKS == 1)

+HAL_StatusTypeDef HAL_HASH_RegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID, pHASH_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HASH_CallbackIDTypeDef CallbackID);

+#endif /* USE_HAL_HASH_REGISTER_CALLBACKS */

+

+

+/**

+  * @}

+  */

+

+/** @addtogroup HASH_Exported_Functions_Group2 HASH processing functions in polling mode

+  * @{

+  */

+

+

+/* HASH processing using polling  *********************************************/

+HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);

+HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);

+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);

+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);

+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);

+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);

+

+

+/**

+  * @}

+  */

+

+/** @addtogroup HASH_Exported_Functions_Group3 HASH processing functions in interrupt mode

+  * @{

+  */

+

+/* HASH processing using IT  **************************************************/

+HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);

+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);

+HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);

+HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);

+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);

+HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);

+void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash);

+/**

+  * @}

+  */

+

+/** @addtogroup HASH_Exported_Functions_Group4 HASH processing functions in DMA mode

+  * @{

+  */

+

+/* HASH processing using DMA  *************************************************/

+HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);

+HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);

+HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);

+HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);

+

+/**

+  * @}

+  */

+

+/** @addtogroup HASH_Exported_Functions_Group5 HMAC processing functions in polling mode

+  * @{

+  */

+

+/* HASH-MAC processing using polling  *****************************************/

+HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);

+HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);

+

+/**

+  * @}

+  */

+

+/** @addtogroup HASH_Exported_Functions_Group6 HMAC processing functions in interrupt mode

+  * @{

+  */

+

+HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);

+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);

+

+/**

+  * @}

+  */

+

+/** @addtogroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode

+  * @{

+  */

+

+/* HASH-HMAC processing using DMA  ********************************************/

+HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);

+HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);

+

+/**

+  * @}

+  */

+

+/** @addtogroup HASH_Exported_Functions_Group8 Peripheral states functions

+  * @{

+  */

+

+

+/* Peripheral State methods  **************************************************/

+HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash);

+HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash);

+void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);

+void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t* pMemBuffer);

+void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);

+HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash);

+uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private functions -----------------------------------------------------------*/

+

+/** @addtogroup HASH_Private_Functions HASH Private Functions

+  * @{

+  */

+

+/* Private functions */

+HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);

+HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);

+HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);

+HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);

+HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);

+HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);

+HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout, uint32_t Algorithm);

+HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Algorithm);

+HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+#endif /*  HASH*/

+/**

+  * @}

+  */

+

+

+#ifdef __cplusplus

+}

+#endif

+

+

+#endif /* STM32H7xx_HAL_HASH_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_hash_ex.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_hash_ex.h
new file mode 100644
index 0000000000..88a6cdc5c9
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_hash_ex.h
@@ -0,0 +1,165 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_hash_ex.h

+  * @author  MCD Application Team

+  * @brief   Header file of HASH HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_HASH_EX_H

+#define STM32H7xx_HAL_HASH_EX_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+#if defined (HASH)

+/** @addtogroup HASHEx

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/* Exported constants --------------------------------------------------------*/

+/* Exported macro ------------------------------------------------------------*/

+

+

+/* Exported functions --------------------------------------------------------*/

+

+/** @addtogroup HASHEx_Exported_Functions HASH Extended Exported Functions

+  * @{

+  */

+

+/** @addtogroup HASHEx_Exported_Functions_Group1 HASH extended processing functions in polling mode

+  * @{

+  */

+

+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);

+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);

+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);

+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);

+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);

+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);

+

+/**

+  * @}

+  */

+

+/** @addtogroup HASHEx_Exported_Functions_Group2 HASH extended processing functions in interrupt mode

+  * @{

+  */

+

+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);

+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);

+HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);

+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);

+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);

+HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);

+

+/**

+  * @}

+  */

+

+/** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode

+  * @{

+  */

+HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);

+HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);

+HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);

+HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout);

+

+/**

+  * @}

+  */

+

+/** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode

+  * @{

+  */

+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);

+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout);

+/**

+  * @}

+  */

+

+/** @addtogroup HASHEx_Exported_Functions_Group5 HMAC extended processing functions in interrupt mode

+  * @{

+  */

+

+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);

+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer);

+

+/**

+  * @}

+  */

+

+/** @addtogroup HASHEx_Exported_Functions_Group6 HMAC extended processing functions in DMA mode

+  * @{

+  */

+

+HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);

+HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);

+

+/**

+  * @}

+  */

+

+/** @addtogroup HASHEx_Exported_Functions_Group7 Multi-buffer HMAC extended processing functions in DMA mode

+  * @{

+  */

+

+HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);

+HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);

+HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);

+

+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);

+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);

+HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);

+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);

+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);

+HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);

+

+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);

+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);

+HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+#endif /*  HASH*/

+/**

+  * @}

+  */

+

+

+#ifdef __cplusplus

+}

+#endif

+

+

+#endif /* STM32H7xx_HAL_HASH_EX_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_hcd.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_hcd.h
new file mode 100644
index 0000000000..765f989183
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_hcd.h
@@ -0,0 +1,329 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_hcd.h

+  * @author  MCD Application Team

+  * @brief   Header file of HCD HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_HCD_H

+#define STM32H7xx_HAL_HCD_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_ll_usb.h"

+

+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup HCD

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup HCD_Exported_Types HCD Exported Types

+  * @{

+  */

+

+/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition

+  * @{

+  */

+typedef enum

+{

+  HAL_HCD_STATE_RESET    = 0x00,

+  HAL_HCD_STATE_READY    = 0x01,

+  HAL_HCD_STATE_ERROR    = 0x02,

+  HAL_HCD_STATE_BUSY     = 0x03,

+  HAL_HCD_STATE_TIMEOUT  = 0x04

+} HCD_StateTypeDef;

+

+typedef USB_OTG_GlobalTypeDef   HCD_TypeDef;

+typedef USB_OTG_CfgTypeDef      HCD_InitTypeDef;

+typedef USB_OTG_HCTypeDef       HCD_HCTypeDef;

+typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef;

+typedef USB_OTG_HCStateTypeDef  HCD_HCStateTypeDef;

+/**

+  * @}

+  */

+

+/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition

+  * @{

+  */

+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)

+typedef struct __HCD_HandleTypeDef

+#else

+typedef struct

+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */

+{

+  HCD_TypeDef               *Instance;  /*!< Register base address    */

+  HCD_InitTypeDef           Init;       /*!< HCD required parameters  */

+  HCD_HCTypeDef             hc[16];     /*!< Host channels parameters */

+  HAL_LockTypeDef           Lock;       /*!< HCD peripheral status    */

+  __IO HCD_StateTypeDef     State;      /*!< HCD communication state  */

+  __IO  uint32_t            ErrorCode;  /*!< HCD Error code           */

+  void                      *pData;     /*!< Pointer Stack Handler    */

+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)

+  void (* SOFCallback)(struct __HCD_HandleTypeDef *hhcd);                               /*!< USB OTG HCD SOF callback                */

+  void (* ConnectCallback)(struct __HCD_HandleTypeDef *hhcd);                           /*!< USB OTG HCD Connect callback            */

+  void (* DisconnectCallback)(struct __HCD_HandleTypeDef *hhcd);                        /*!< USB OTG HCD Disconnect callback         */

+  void (* PortEnabledCallback)(struct __HCD_HandleTypeDef *hhcd);                       /*!< USB OTG HCD Port Enable callback        */

+  void (* PortDisabledCallback)(struct __HCD_HandleTypeDef *hhcd);                      /*!< USB OTG HCD Port Disable callback       */

+  void (* HC_NotifyURBChangeCallback)(struct __HCD_HandleTypeDef *hhcd, uint8_t chnum,

+                                      HCD_URBStateTypeDef urb_state);                   /*!< USB OTG HCD Host Channel Notify URB Change callback  */

+

+  void (* MspInitCallback)(struct __HCD_HandleTypeDef *hhcd);                           /*!< USB OTG HCD Msp Init callback           */

+  void (* MspDeInitCallback)(struct __HCD_HandleTypeDef *hhcd);                         /*!< USB OTG HCD Msp DeInit callback         */

+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */

+} HCD_HandleTypeDef;

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup HCD_Exported_Constants HCD Exported Constants

+  * @{

+  */

+

+/** @defgroup HCD_Speed HCD Speed

+  * @{

+  */

+#define HCD_SPEED_HIGH               USBH_HS_SPEED

+#define HCD_SPEED_FULL               USBH_FS_SPEED

+#define HCD_SPEED_LOW                USBH_LS_SPEED

+

+/**

+  * @}

+  */

+

+/** @defgroup HCD_PHY_Module HCD PHY Module

+  * @{

+  */

+#define HCD_PHY_ULPI                 1U

+#define HCD_PHY_EMBEDDED             2U

+/**

+  * @}

+  */

+

+/** @defgroup HCD_Error_Code_definition HCD Error Code definition

+  * @brief  HCD Error Code definition

+  * @{

+  */

+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)

+#define  HAL_HCD_ERROR_INVALID_CALLBACK                        (0x00000010U)    /*!< Invalid Callback error  */

+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup HCD_Exported_Macros HCD Exported Macros

+ *  @brief macros to handle interrupts and specific clock configurations

+ * @{

+ */

+#define __HAL_HCD_ENABLE(__HANDLE__)                   (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)

+#define __HAL_HCD_DISABLE(__HANDLE__)                  (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)

+

+#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))

+#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))

+#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)

+

+#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__)  (USBx_HC(chnum)->HCINT = (__INTERRUPT__))

+#define __HAL_HCD_MASK_HALT_HC_INT(chnum)             (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)

+#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum)           (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)

+#define __HAL_HCD_MASK_ACK_HC_INT(chnum)              (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)

+#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum)            (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup HCD_Exported_Functions HCD Exported Functions

+  * @{

+  */

+

+/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions

+  * @{

+  */

+HAL_StatusTypeDef      HAL_HCD_Init(HCD_HandleTypeDef *hhcd);

+HAL_StatusTypeDef      HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd);

+HAL_StatusTypeDef      HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,

+                                       uint8_t ch_num,

+                                       uint8_t epnum,

+                                       uint8_t dev_address,

+                                       uint8_t speed,

+                                       uint8_t ep_type,

+                                       uint16_t mps);

+

+HAL_StatusTypeDef     HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num);

+void                  HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd);

+void                  HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd);

+

+#if (USE_HAL_HCD_REGISTER_CALLBACKS == 1U)

+/** @defgroup HAL_HCD_Callback_ID_enumeration_definition HAL USB OTG HCD Callback ID enumeration definition

+  * @brief  HAL USB OTG HCD Callback ID enumeration definition

+  * @{

+  */

+typedef enum

+{

+  HAL_HCD_SOF_CB_ID           = 0x01,       /*!< USB HCD SOF callback ID           */

+  HAL_HCD_CONNECT_CB_ID       = 0x02,       /*!< USB HCD Connect callback ID       */

+  HAL_HCD_DISCONNECT_CB_ID   = 0x03,       /*!< USB HCD Disconnect callback ID    */

+  HAL_HCD_PORT_ENABLED_CB_ID   = 0x04,      /*!< USB HCD Port Enable callback ID   */

+  HAL_HCD_PORT_DISABLED_CB_ID  = 0x05,      /*!< USB HCD Port Disable callback ID  */

+

+  HAL_HCD_MSPINIT_CB_ID       = 0x06,       /*!< USB HCD MspInit callback ID       */

+  HAL_HCD_MSPDEINIT_CB_ID     = 0x07        /*!< USB HCD MspDeInit callback ID     */

+

+} HAL_HCD_CallbackIDTypeDef;

+/**

+  * @}

+  */

+

+/** @defgroup HAL_HCD_Callback_pointer_definition HAL USB OTG HCD Callback pointer definition

+  * @brief  HAL USB OTG HCD Callback pointer definition

+  * @{

+  */

+

+typedef void (*pHCD_CallbackTypeDef)(HCD_HandleTypeDef *hhcd);                   /*!< pointer to a common USB OTG HCD callback function  */

+typedef void (*pHCD_HC_NotifyURBChangeCallbackTypeDef)(HCD_HandleTypeDef *hhcd,

+                                                       uint8_t epnum,

+                                                       HCD_URBStateTypeDef urb_state);   /*!< pointer to USB OTG HCD host channel  callback */

+/**

+  * @}

+  */

+

+HAL_StatusTypeDef HAL_HCD_RegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID, pHCD_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_HCD_UnRegisterCallback(HCD_HandleTypeDef *hhcd, HAL_HCD_CallbackIDTypeDef CallbackID);

+

+HAL_StatusTypeDef HAL_HCD_RegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd, pHCD_HC_NotifyURBChangeCallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_HCD_UnRegisterHC_NotifyURBChangeCallback(HCD_HandleTypeDef *hhcd);

+#endif /* USE_HAL_HCD_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/* I/O operation functions  ***************************************************/

+/** @addtogroup HCD_Exported_Functions_Group2 Input and Output operation functions

+  * @{

+  */

+HAL_StatusTypeDef       HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,

+                                                 uint8_t ch_num,

+                                                 uint8_t direction,

+                                                 uint8_t ep_type,

+                                                 uint8_t token,

+                                                 uint8_t *pbuff,

+                                                 uint16_t length,

+                                                 uint8_t do_ping);

+

+/* Non-Blocking mode: Interrupt */

+void             HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);

+void             HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);

+void             HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);

+void             HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);

+void             HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);

+void             HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);

+void             HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,

+                                                     uint8_t chnum,

+                                                     HCD_URBStateTypeDef urb_state);

+/**

+  * @}

+  */

+

+/* Peripheral Control functions  **********************************************/

+/** @addtogroup HCD_Exported_Functions_Group3 Peripheral Control functions

+  * @{

+  */

+HAL_StatusTypeDef       HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd);

+HAL_StatusTypeDef       HAL_HCD_Start(HCD_HandleTypeDef *hhcd);

+HAL_StatusTypeDef       HAL_HCD_Stop(HCD_HandleTypeDef *hhcd);

+/**

+  * @}

+  */

+

+/* Peripheral State functions  ************************************************/

+/** @addtogroup HCD_Exported_Functions_Group4 Peripheral State functions

+  * @{

+  */

+HCD_StateTypeDef        HAL_HCD_GetState(HCD_HandleTypeDef *hhcd);

+HCD_URBStateTypeDef     HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum);

+uint32_t                HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum);

+HCD_HCStateTypeDef      HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum);

+uint32_t                HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd);

+uint32_t                HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup HCD_Private_Macros HCD Private Macros

+ * @{

+ */

+

+/**

+  * @}

+  */

+

+/* Private functions prototypes ----------------------------------------------*/

+/** @defgroup HCD_Private_Functions_Prototypes HCD Private Functions Prototypes

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private functions ---------------------------------------------------------*/

+/** @defgroup HCD_Private_Functions HCD Private Functions

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_HCD_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_hrtim.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_hrtim.h
new file mode 100644
index 0000000000..5976853485
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_hrtim.h
@@ -0,0 +1,3646 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_hrtim.h

+  * @author  MCD Application Team

+  * @brief   Header file of HRTIM HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_HRTIM_H

+#define STM32H7xx_HAL_HRTIM_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+#if defined(HRTIM1)

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup HRTIM HRTIM

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @addtogroup HRTIM_Exported_Constants HRTIM Exported Constants

+  * @{

+  */

+/** @defgroup HRTIM_Max_Timer HRTIM Max Timer

+  * @{

+  */

+#define MAX_HRTIM_TIMER 6U

+/**

+  * @}

+  */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Exported_Types HRTIM Exported Types

+  * @{

+  */

+

+/**

+  * @brief  HRTIM Configuration Structure definition - Time base related parameters

+  */

+typedef struct

+{

+  uint32_t HRTIMInterruptResquests;  /*!< Specifies which interrupts requests must enabled for the HRTIM instance.

+                                          This parameter can be any combination of  @ref HRTIM_Common_Interrupt_Enable */

+  uint32_t SyncOptions;              /*!< Specifies how the HRTIM instance handles the external synchronization signals.

+                                          The HRTIM instance can be configured to act as a slave (waiting for a trigger

+                                          to be synchronized) or a master (generating a synchronization signal) or both.

+                                          This parameter can be a combination of @ref HRTIM_Synchronization_Options.*/

+  uint32_t SyncInputSource;          /*!< Specifies the external synchronization input source (significant only when

+                                          the HRTIM instance is configured as a slave).

+                                          This parameter can be a value of @ref HRTIM_Synchronization_Input_Source. */

+  uint32_t SyncOutputSource;         /*!< Specifies the source and event to be sent on the external synchronization outputs

+                                         (significant only when the HRTIM instance is configured as a master).

+                                          This parameter can be a value of @ref HRTIM_Synchronization_Output_Source */

+  uint32_t SyncOutputPolarity;       /*!< Specifies the conditioning of the event to be sent on the external synchronization

+                                          outputs (significant only when the HRTIM instance is configured as a master).

+                                          This parameter can be a value of @ref HRTIM_Synchronization_Output_Polarity */

+} HRTIM_InitTypeDef;

+

+/**

+  * @brief  HAL State structures definition

+  */

+typedef enum

+{

+  HAL_HRTIM_STATE_RESET            = 0x00U,    /*!< Peripheral is not yet Initialized                  */

+  HAL_HRTIM_STATE_READY            = 0x01U,    /*!< Peripheral Initialized and ready for use           */

+  HAL_HRTIM_STATE_BUSY             = 0x02U,    /*!< an internal process is ongoing                     */

+  HAL_HRTIM_STATE_TIMEOUT          = 0x06U,    /*!< Timeout state                                      */

+  HAL_HRTIM_STATE_ERROR            = 0x07U,    /*!< Error state                                        */

+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)

+  HAL_HRTIM_STATE_INVALID_CALLBACK = 0x08U    /*!< Invalid Callback error */

+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */

+} HAL_HRTIM_StateTypeDef;

+

+/**

+  * @brief HRTIM Timer Structure definition

+  */

+typedef struct

+{

+  uint32_t CaptureTrigger1;       /*!< Event(s) triggering capture unit 1.

+                                       When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.

+                                       When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */

+  uint32_t CaptureTrigger2;       /*!< Event(s) triggering capture unit 2.

+                                       When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.

+                                       When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */

+  uint32_t InterruptRequests;     /*!< Interrupts requests enabled for the timer. */

+  uint32_t DMARequests;           /*!< DMA requests enabled for the timer. */

+  uint32_t DMASrcAddress;          /*!< Address of the source address of the DMA transfer. */

+  uint32_t DMADstAddress;          /*!< Address of the destination address of the DMA transfer. */

+  uint32_t DMASize;                /*!< Size of the DMA transfer */

+} HRTIM_TimerParamTypeDef;

+

+/**

+  * @brief  HRTIM Handle Structure definition

+  */

+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)

+typedef struct __HRTIM_HandleTypeDef

+#else

+typedef struct

+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */

+{

+  HRTIM_TypeDef *              Instance;                     /*!< Register base address */

+

+  HRTIM_InitTypeDef            Init;                         /*!< HRTIM required parameters */

+

+  HRTIM_TimerParamTypeDef      TimerParam[MAX_HRTIM_TIMER];  /*!< HRTIM timers - including the master - parameters */

+

+  HAL_LockTypeDef              Lock;                         /*!< Locking object          */

+

+  __IO HAL_HRTIM_StateTypeDef  State;                        /*!< HRTIM communication state */

+

+  DMA_HandleTypeDef *          hdmaMaster;                   /*!< Master timer DMA handle parameters */

+  DMA_HandleTypeDef *          hdmaTimerA;                   /*!< Timer A DMA handle parameters */

+  DMA_HandleTypeDef *          hdmaTimerB;                   /*!< Timer B DMA handle parameters */

+  DMA_HandleTypeDef *          hdmaTimerC;                   /*!< Timer C DMA handle parameters */

+  DMA_HandleTypeDef *          hdmaTimerD;                   /*!< Timer D DMA handle parameters */

+  DMA_HandleTypeDef *          hdmaTimerE;                   /*!< Timer E DMA handle parameters */

+

+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)

+  void (* Fault1Callback)(struct __HRTIM_HandleTypeDef *hhrtim);                               /*!< Fault 1 interrupt callback function pointer                         */

+  void (* Fault2Callback)(struct __HRTIM_HandleTypeDef *hhrtim);                               /*!< Fault 2 interrupt callback function pointer                         */

+  void (* Fault3Callback)(struct __HRTIM_HandleTypeDef *hhrtim);                               /*!< Fault 3 interrupt callback function pointer                         */

+  void (* Fault4Callback)(struct __HRTIM_HandleTypeDef *hhrtim);                               /*!< Fault 4 interrupt callback function pointer                         */

+  void (* Fault5Callback)(struct __HRTIM_HandleTypeDef *hhrtim);                               /*!< Fault 5 interrupt callback function pointer                         */

+  void (* SystemFaultCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                          /*!< System fault interrupt callback function pointer                    */

+  void (* BurstModePeriodCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                      /*!< Burst mode period interrupt callback function pointer               */

+  void (* SynchronizationEventCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                 /*!< Sync Input interrupt callback function pointer                      */

+  void (* ErrorCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                                /*!< DMA error callback function pointer                                 */

+

+  void (* RegistersUpdateCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);   /*!< Timer x Update interrupt callback function pointer                  */

+  void (* RepetitionEventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);   /*!< Timer x Repetition interrupt callback function pointer              */

+  void (* Compare1EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);     /*!< Timer x Compare 1 match interrupt callback function pointer         */

+  void (* Compare2EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);     /*!< Timer x Compare 2 match interrupt callback function pointer         */

+  void (* Compare3EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);     /*!< Timer x Compare 3 match interrupt callback function pointer         */

+  void (* Compare4EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);     /*!< Timer x Compare 4 match interrupt callback function pointer         */

+  void (* Capture1EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);     /*!< Timer x Capture 1 interrupts callback function pointer              */

+  void (* Capture2EventCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);     /*!< Timer x Capture 2 interrupts callback function pointer              */

+  void (* DelayedProtectionCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx); /*!< Timer x Delayed protection interrupt callback function pointer      */

+  void (* CounterResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);      /*!< Timer x counter reset/roll-over interrupt callback function pointer */

+  void (* Output1SetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);        /*!< Timer x output 1 set interrupt callback function pointer            */

+  void (* Output1ResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);      /*!< Timer x output 1 reset interrupt callback function pointer          */

+  void (* Output2SetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);        /*!< Timer x output 2 set interrupt callback function pointer            */

+  void (* Output2ResetCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);      /*!< Timer x output 2 reset interrupt callback function pointer          */

+  void (* BurstDMATransferCallback)(struct __HRTIM_HandleTypeDef *hhrtim, uint32_t TimerIdx);  /*!< Timer x Burst DMA completed interrupt callback function pointer     */

+

+  void (* MspInitCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                              /*!< HRTIM MspInit callback function pointer                             */

+  void (* MspDeInitCallback)(struct __HRTIM_HandleTypeDef *hhrtim);                            /*!< HRTIM MspInit callback function pointer                             */

+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */

+} HRTIM_HandleTypeDef;

+

+/**

+  * @brief  Simple output compare mode configuration definition

+  */

+typedef struct

+{

+  uint32_t Period;                   /*!< Specifies the timer period.

+                                          The period value must be above 3 periods of the fHRTIM clock.

+                                          Maximum value is = 0xFFDFU */

+  uint32_t RepetitionCounter;        /*!< Specifies the timer repetition period.

+                                          This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */

+  uint32_t PrescalerRatio;           /*!< Specifies the timer clock prescaler ratio.

+                                          This parameter can be any value of @ref HRTIM_Prescaler_Ratio   */

+  uint32_t Mode;                     /*!< Specifies the counter operating mode.

+                                          This parameter can be any value of @ref HRTIM_Counter_Operating_Mode   */

+} HRTIM_TimeBaseCfgTypeDef;

+

+/**

+  * @brief  Simple output compare mode configuration definition

+  */

+typedef struct

+{

+  uint32_t Mode;       /*!< Specifies the output compare mode (toggle, active, inactive).

+                            This parameter can be any value of of @ref HRTIM_Simple_OC_Mode */

+  uint32_t Pulse;      /*!< Specifies the compare value to be loaded into the Compare Register.

+                            The compare value must be above or equal to 3 periods of the fHRTIM clock */

+  uint32_t Polarity;   /*!< Specifies the output polarity.

+                            This parameter can be any value of @ref HRTIM_Output_Polarity */

+  uint32_t IdleLevel;  /*!< Specifies whether the output level is active or inactive when in IDLE state.

+                            This parameter can be any value of @ref HRTIM_Output_IDLE_Level */

+} HRTIM_SimpleOCChannelCfgTypeDef;

+

+/**

+  * @brief  Simple PWM output mode configuration definition

+  */

+typedef struct

+{

+  uint32_t Pulse;            /*!< Specifies the compare value to be loaded into the Compare Register.

+                                  The compare value must be above or equal to 3 periods of the fHRTIM clock */

+  uint32_t Polarity;        /*!< Specifies the output polarity.

+                                 This parameter can be any value of @ref HRTIM_Output_Polarity */

+  uint32_t IdleLevel;       /*!< Specifies whether the output level is active or inactive when in IDLE state.

+                                 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */

+} HRTIM_SimplePWMChannelCfgTypeDef;

+

+/**

+  * @brief  Simple capture mode configuration definition

+  */

+typedef struct

+{

+  uint32_t Event;             /*!< Specifies the external event triggering the capture.

+                                   This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */

+  uint32_t EventPolarity;     /*!< Specifies the polarity of the external event (in case of level sensitivity).

+                                   This parameter can be a value of @ref HRTIM_External_Event_Polarity */

+  uint32_t EventSensitivity;  /*!< Specifies the sensitivity of the external event.

+                                   This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */

+  uint32_t EventFilter;       /*!< Defines the frequency used to sample the External Event and the length of the digital filter.

+                                   This parameter can be a value of @ref HRTIM_External_Event_Filter */

+} HRTIM_SimpleCaptureChannelCfgTypeDef;

+

+/**

+  * @brief  Simple One Pulse mode configuration definition

+  */

+typedef struct

+{

+  uint32_t Pulse;             /*!< Specifies the compare value to be loaded into the Compare Register.

+                                   The compare value must be above or equal to 3 periods of the fHRTIM clock */

+  uint32_t OutputPolarity;    /*!< Specifies the output polarity.

+                                   This parameter can be any value of @ref HRTIM_Output_Polarity */

+  uint32_t OutputIdleLevel;   /*!< Specifies whether the output level is active or inactive when in IDLE state.

+                                   This parameter can be any value of @ref HRTIM_Output_IDLE_Level */

+  uint32_t Event;             /*!< Specifies the external event triggering the pulse generation.

+                                   This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */

+  uint32_t EventPolarity;     /*!< Specifies the polarity of the external event (in case of level sensitivity).

+                                   This parameter can be a value of @ref HRTIM_External_Event_Polarity */

+  uint32_t EventSensitivity;  /*!< Specifies the sensitivity of the external event.

+                                   This parameter can be a value of @ref HRTIM_External_Event_Sensitivity. */

+  uint32_t EventFilter;       /*!< Defines the frequency used to sample the External Event and the length of the digital filter.

+                                   This parameter can be a value of @ref HRTIM_External_Event_Filter */

+} HRTIM_SimpleOnePulseChannelCfgTypeDef;

+

+/**

+  * @brief  Timer configuration definition

+  */

+typedef struct

+{

+  uint32_t InterruptRequests;      /*!< Relevant for all HRTIM timers, including the master.

+                                       Specifies which interrupts requests must enabled for the timer.

+                                       This parameter can be any combination of  @ref HRTIM_Master_Interrupt_Enable

+                                       or @ref HRTIM_Timing_Unit_Interrupt_Enable */

+  uint32_t DMARequests;            /*!< Relevant for all HRTIM timers, including the master.

+                                       Specifies which DMA requests must be enabled for the timer.

+                                       This parameter can be any combination of  @ref HRTIM_Master_DMA_Request_Enable

+                                       or @ref HRTIM_Timing_Unit_DMA_Request_Enable */

+  uint32_t DMASrcAddress;          /*!< Relevant for all HRTIM timers, including the master.

+                                       Specifies the address of the source address of the DMA transfer */

+  uint32_t DMADstAddress;          /*!< Relevant for all HRTIM timers, including the master.

+                                       Specifies the address of the destination address of the DMA transfer */

+  uint32_t DMASize;                /*!< Relevant for all HRTIM timers, including the master.

+                                       Specifies the size of the DMA transfer */

+  uint32_t HalfModeEnable;         /*!< Relevant for all HRTIM timers, including the master.

+                                        Specifies whether or not half mode is enabled

+                                        This parameter can be any value of @ref HRTIM_Half_Mode_Enable  */

+  uint32_t StartOnSync;            /*!< Relevant for all HRTIM timers, including the master.

+                                       Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled).

+                                        This parameter can be any value of @ref HRTIM_Start_On_Sync_Input_Event  */

+  uint32_t ResetOnSync;            /*!< Relevant for all HRTIM timers, including the master.

+                                        Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled).

+                                        This parameter can be any value of @ref HRTIM_Reset_On_Sync_Input_Event  */

+  uint32_t DACSynchro;             /*!< Relevant for all HRTIM timers, including the master.

+                                        Indicates whether or not the a DAC synchronization event is generated.

+                                        This parameter can be any value of @ref HRTIM_DAC_Synchronization   */

+  uint32_t PreloadEnable;          /*!< Relevant for all HRTIM timers, including the master.

+                                        Specifies whether or not register preload is enabled.

+                                        This parameter can be any value of @ref HRTIM_Register_Preload_Enable  */

+  uint32_t UpdateGating;           /*!< Relevant for all HRTIM timers, including the master.

+                                        Specifies how the update occurs with respect to a burst DMA transaction or

+                                        update enable inputs (Slave timers only).

+                                        This parameter can be any value of @ref HRTIM_Update_Gating   */

+  uint32_t BurstMode;              /*!< Relevant for all HRTIM timers, including the master.

+                                        Specifies how the timer behaves during a burst mode operation.

+                                        This parameter can be any value of @ref HRTIM_Timer_Burst_Mode  */

+  uint32_t RepetitionUpdate;       /*!< Relevant for all HRTIM timers, including the master.

+                                        Specifies whether or not registers update is triggered by the repetition event.

+                                        This parameter can be any value of @ref HRTIM_Timer_Repetition_Update */

+  uint32_t PushPull;               /*!< Relevant for Timer A to Timer E.

+                                        Specifies whether or not the push-pull mode is enabled.

+                                        This parameter can be any value of @ref HRTIM_Timer_Push_Pull_Mode */

+  uint32_t FaultEnable;            /*!< Relevant for Timer A to Timer E.

+                                        Specifies which fault channels are enabled for the timer.

+                                        This parameter can be a combination of @ref HRTIM_Timer_Fault_Enabling  */

+  uint32_t FaultLock;              /*!< Relevant for Timer A to Timer E.

+                                        Specifies whether or not fault enabling status is write protected.

+                                        This parameter can be a value of @ref HRTIM_Timer_Fault_Lock */

+  uint32_t DeadTimeInsertion;      /*!< Relevant for Timer A to Timer E.

+                                        Specifies whether or not dead-time insertion is enabled for the timer.

+                                        This parameter can be a value of @ref HRTIM_Timer_Deadtime_Insertion */

+  uint32_t DelayedProtectionMode;  /*!< Relevant for Timer A to Timer E.

+                                        Specifies the delayed protection mode.

+                                        This parameter can be a value of @ref HRTIM_Timer_Delayed_Protection_Mode */

+  uint32_t UpdateTrigger;          /*!< Relevant for Timer A to Timer E.

+                                        Specifies source(s) triggering the timer registers update.

+                                        This parameter can be a combination of @ref HRTIM_Timer_Update_Trigger */

+  uint32_t ResetTrigger;           /*!< Relevant for Timer A to Timer E.

+                                        Specifies source(s) triggering the timer counter reset.

+                                        This parameter can be a combination of @ref HRTIM_Timer_Reset_Trigger */

+  uint32_t ResetUpdate;           /*!<  Relevant for Timer A to Timer E.

+                                        Specifies whether or not registers update is triggered when the timer counter is reset.

+                                        This parameter can be a value of @ref HRTIM_Timer_Reset_Update */

+} HRTIM_TimerCfgTypeDef;

+

+/**

+  * @brief  Compare unit configuration definition

+  */

+typedef struct

+{

+  uint32_t CompareValue;         /*!< Specifies the compare value of the timer compare unit.

+                                      The minimum value must be greater than or equal to 3 periods of the fHRTIM clock.

+                                      The maximum value must be less than or equal to 0xFFFFU - 1 periods of the fHRTIM clock */

+  uint32_t AutoDelayedMode;      /*!< Specifies the auto delayed mode for compare unit 2 or 4.

+                                      This parameter can be a value of @ref HRTIM_Compare_Unit_Auto_Delayed_Mode */

+  uint32_t AutoDelayedTimeout;   /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected.

+                                      CompareValue +  AutoDelayedTimeout must be less than 0xFFFFU */

+} HRTIM_CompareCfgTypeDef;

+

+/**

+  * @brief  Capture unit configuration definition

+  */

+typedef struct

+{

+  uint32_t Trigger;          /*!< Specifies source(s) triggering the capture.

+                                  This parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger */

+} HRTIM_CaptureCfgTypeDef;

+

+/**

+  * @brief  Output configuration definition

+  */

+typedef struct

+{

+  uint32_t Polarity;                    /*!< Specifies the output polarity.

+                                             This parameter can be any value of @ref HRTIM_Output_Polarity */

+  uint32_t SetSource;                   /*!< Specifies the event(s) transitioning the output from its inactive level to its active level.

+                                             This parameter can be a combination of @ref HRTIM_Output_Set_Source */

+  uint32_t ResetSource;                 /*!< Specifies the event(s) transitioning the output from its active level to its inactive level.

+                                             This parameter can be a combination of @ref HRTIM_Output_Reset_Source */

+  uint32_t IdleMode;                    /*!< Specifies whether or not the output is affected by a burst mode operation.

+                                             This parameter can be any value of @ref HRTIM_Output_Idle_Mode */

+  uint32_t IdleLevel;                   /*!< Specifies whether the output level is active or inactive when in IDLE state.

+                                             This parameter can be any value of @ref HRTIM_Output_IDLE_Level */

+  uint32_t FaultLevel;                  /*!< Specifies whether the output level is active or inactive when in FAULT state.

+                                             This parameter can be any value of @ref HRTIM_Output_FAULT_Level */

+  uint32_t ChopperModeEnable;           /*!< Indicates whether or not the chopper mode is enabled

+                                             This parameter can be any value of @ref HRTIM_Output_Chopper_Mode_Enable */

+  uint32_t BurstModeEntryDelayed;       /*!< Indicates whether or not dead-time is inserted when entering the IDLE state during a burst mode operation.

+                                             This parameters can be any value of @ref HRTIM_Output_Burst_Mode_Entry_Delayed */

+} HRTIM_OutputCfgTypeDef;

+

+/**

+  * @brief  External event filtering in timing units configuration definition

+  */

+typedef struct

+{

+  uint32_t Filter;       /*!< Specifies the type of event filtering within the timing unit.

+                             This parameter can be a value of @ref HRTIM_Timer_External_Event_Filter */

+  uint32_t Latch;       /*!< Specifies whether or not the signal is latched.

+                             This parameter can be a value of @ref HRTIM_Timer_External_Event_Latch */

+} HRTIM_TimerEventFilteringCfgTypeDef;

+

+/**

+  * @brief  Dead time feature configuration definition

+  */

+typedef struct

+{

+  uint32_t Prescaler;        /*!< Specifies the dead-time prescaler.

+                                  This parameter can be a value of @ref  HRTIM_Deadtime_Prescaler_Ratio */

+  uint32_t RisingValue;      /*!< Specifies the dead-time following a rising edge.

+                                  This parameter can be a number between 0x0 and 0x1FFU */

+  uint32_t RisingSign;       /*!< Specifies whether the dead-time is positive or negative on rising edge.

+                                  This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign */

+  uint32_t RisingLock;       /*!< Specifies whether or not dead-time rising settings (value and sign) are write protected.

+                                  This parameter can be a value of @ref HRTIM_Deadtime_Rising_Lock */

+  uint32_t RisingSignLock;   /*!< Specifies whether or not dead-time rising sign is write protected.

+                                  This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign_Lock */

+  uint32_t FallingValue;     /*!< Specifies the dead-time following a falling edge.

+                                  This parameter can be a number between 0x0 and 0x1FFU */

+  uint32_t FallingSign;      /*!< Specifies whether the dead-time is positive or negative on falling edge.

+                                  This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign */

+  uint32_t FallingLock;      /*!< Specifies whether or not dead-time falling settings (value and sign) are write protected.

+                                  This parameter can be a value of @ref HRTIM_Deadtime_Falling_Lock */

+  uint32_t FallingSignLock;  /*!< Specifies whether or not dead-time falling sign is write protected.

+                                  This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign_Lock */

+} HRTIM_DeadTimeCfgTypeDef;

+

+/**

+  * @brief  Chopper mode configuration definition

+  */

+typedef struct

+{

+  uint32_t CarrierFreq;  /*!< Specifies the Timer carrier frequency value.

+                              This parameter can be a value of @ref HRTIM_Chopper_Frequency */

+  uint32_t DutyCycle;    /*!< Specifies the Timer chopper duty cycle value.

+                              This parameter can be a value of @ref HRTIM_Chopper_Duty_Cycle */

+  uint32_t StartPulse;   /*!< Specifies the Timer pulse width value.

+                              This parameter can be a value of @ref HRTIM_Chopper_Start_Pulse_Width */

+} HRTIM_ChopperModeCfgTypeDef;

+

+/**

+  * @brief  External event channel configuration definition

+  */

+typedef struct

+{

+  uint32_t Source;        /*!< Identifies the source of the external event.

+                               This parameter can be a value of @ref HRTIM_External_Event_Sources */

+  uint32_t Polarity;      /*!< Specifies the polarity of the external event (in case of level sensitivity).

+                               This parameter can be a value of @ref HRTIM_External_Event_Polarity */

+  uint32_t Sensitivity;   /*!< Specifies the sensitivity of the external event.

+                               This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */

+  uint32_t Filter;        /*!< Defines the frequency used to sample the External Event and the length of the digital filter.

+                               This parameter can be a value of @ref HRTIM_External_Event_Filter */

+  uint32_t FastMode;      /*!< Indicates whether or not low latency mode is enabled for the external event.

+                               This parameter can be a value of @ref HRTIM_External_Event_Fast_Mode */

+} HRTIM_EventCfgTypeDef;

+

+/**

+  * @brief  Fault channel configuration definition

+  */

+typedef struct

+{

+  uint32_t Source;        /*!< Identifies the source of the fault.

+                               This parameter can be a value of @ref HRTIM_Fault_Sources */

+  uint32_t Polarity;      /*!< Specifies the polarity of the fault event.

+                               This parameter can be a value of @ref HRTIM_Fault_Polarity */

+  uint32_t Filter;        /*!< Defines the frequency used to sample the Fault input and the length of the digital filter.

+                               This parameter can be a value of @ref HRTIM_Fault_Filter */

+  uint32_t Lock;          /*!< Indicates whether or not fault programming bits are write protected.

+                               This parameter can be a value of @ref HRTIM_Fault_Lock */

+} HRTIM_FaultCfgTypeDef;

+

+/**

+  * @brief  Burst mode configuration definition

+  */

+typedef struct

+{

+  uint32_t Mode;           /*!< Specifies the burst mode operating mode.

+                                This parameter can be a value of @ref HRTIM_Burst_Mode_Operating_Mode */

+  uint32_t ClockSource;    /*!< Specifies the burst mode clock source.

+                                This parameter can be a value of @ref HRTIM_Burst_Mode_Clock_Source */

+  uint32_t Prescaler;      /*!< Specifies the burst mode prescaler.

+                                This parameter can be a value of @ref HRTIM_Burst_Mode_Prescaler */

+  uint32_t PreloadEnable;  /*!< Specifies whether or not preload is enabled for burst mode related registers (HRTIM_BMCMPR and HRTIM_BMPER).

+                                This parameter can be a combination of @ref HRTIM_Burst_Mode_Register_Preload_Enable  */

+  uint32_t Trigger;        /*!< Specifies the event(s) triggering the burst operation.

+                                This parameter can be a combination of @ref HRTIM_Burst_Mode_Trigger  */

+  uint32_t IdleDuration;   /*!< Specifies number of periods during which the selected timers are in idle state.

+                                This parameter can be a number between 0x0 and 0xFFFF  */

+  uint32_t Period;         /*!< Specifies burst mode repetition period.

+                                This parameter can be a number between 0x1 and 0xFFFF  */

+} HRTIM_BurstModeCfgTypeDef;

+

+/**

+  * @brief  ADC trigger configuration definition

+  */

+typedef struct

+{

+  uint32_t UpdateSource;  /*!< Specifies the ADC trigger update source.

+                               This parameter can be a value of @ref HRTIM_ADC_Trigger_Update_Source  */

+  uint32_t Trigger;       /*!< Specifies the event(s) triggering the ADC conversion.

+                               This parameter can be a combination of @ref HRTIM_ADC_Trigger_Event  */

+} HRTIM_ADCTriggerCfgTypeDef;

+

+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  HAL HRTIM Callback ID enumeration definition

+  */

+typedef enum {

+  HAL_HRTIM_FAULT1CALLBACK_CB_ID               = 0x00U, /*!< Fault 1 interrupt callback ID                         */

+  HAL_HRTIM_FAULT2CALLBACK_CB_ID               = 0x01U, /*!< Fault 2 interrupt callback ID                         */

+  HAL_HRTIM_FAULT3CALLBACK_CB_ID               = 0x02U, /*!< Fault 3 interrupt callback ID                         */

+  HAL_HRTIM_FAULT4CALLBACK_CB_ID               = 0x03U, /*!< Fault 4 interrupt callback ID                         */

+  HAL_HRTIM_FAULT5CALLBACK_CB_ID               = 0x04U, /*!< Fault 5 interrupt callback ID                         */

+  HAL_HRTIM_SYSTEMFAULTCALLBACK_CB_ID          = 0x05U, /*!< System fault interrupt callback ID                    */

+  HAL_HRTIM_BURSTMODEPERIODCALLBACK_CB_ID      = 0x07U, /*!< Burst mode period interrupt callback ID               */

+  HAL_HRTIM_SYNCHRONIZATIONEVENTCALLBACK_CB_ID = 0x08U, /*!< Sync Input interrupt callback ID                      */

+  HAL_HRTIM_ERRORCALLBACK_CB_ID                = 0x09U, /*!< DMA error callback ID                                 */

+

+  HAL_HRTIM_REGISTERSUPDATECALLBACK_CB_ID      = 0x10U, /*!< Timer x Update interrupt callback ID                  */

+  HAL_HRTIM_REPETITIONEVENTCALLBACK_CB_ID      = 0x11U, /*!< Timer x Repetition interrupt callback ID              */

+  HAL_HRTIM_COMPARE1EVENTCALLBACK_CB_ID        = 0x12U, /*!< Timer x Compare 1 match interrupt callback ID         */

+  HAL_HRTIM_COMPARE2EVENTCALLBACK_CB_ID        = 0x13U, /*!< Timer x Compare 2 match interrupt callback ID         */

+  HAL_HRTIM_COMPARE3EVENTCALLBACK_CB_ID        = 0x14U, /*!< Timer x Compare 3 match interrupt callback ID         */

+  HAL_HRTIM_COMPARE4EVENTCALLBACK_CB_ID        = 0x15U, /*!< Timer x Compare 4 match interrupt callback ID         */

+  HAL_HRTIM_CAPTURE1EVENTCALLBACK_CB_ID        = 0x16U, /*!< Timer x Capture 1 interrupts callback ID              */

+  HAL_HRTIM_CAPTURE2EVENTCALLBACK_CB_ID        = 0x17U, /*!< Timer x Capture 2 interrupts callback ID              */

+  HAL_HRTIM_DELAYEDPROTECTIONCALLBACK_CB_ID    = 0x18U, /*!< Timer x Delayed protection interrupt callback ID      */

+  HAL_HRTIM_COUNTERRESETCALLBACK_CB_ID         = 0x19U, /*!< Timer x counter reset/roll-over interrupt callback ID */

+  HAL_HRTIM_OUTPUT1SETCALLBACK_CB_ID           = 0x1AU, /*!< Timer x output 1 set interrupt callback ID            */

+  HAL_HRTIM_OUTPUT1RESETCALLBACK_CB_ID         = 0x1BU, /*!< Timer x output 1 reset interrupt callback ID          */

+  HAL_HRTIM_OUTPUT2SETCALLBACK_CB_ID           = 0x1CU, /*!< Timer x output 2 set interrupt callback ID            */

+  HAL_HRTIM_OUTPUT2RESETCALLBACK_CB_ID         = 0x1DU, /*!< Timer x output 2 reset interrupt callback ID          */

+  HAL_HRTIM_BURSTDMATRANSFERCALLBACK_CB_ID     = 0x1EU, /*!< Timer x Burst DMA completed interrupt callback ID     */

+

+  HAL_HRTIM_MSPINIT_CB_ID                      = 0x20U, /*!< HRTIM MspInit callback ID                             */

+  HAL_HRTIM_MSPDEINIT_CB_ID                    = 0x21U, /*!< HRTIM MspInit callback ID                             */

+}HAL_HRTIM_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL HRTIM Callback function pointer definitions

+  */

+typedef void (* pHRTIM_CallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim);       /*!< HRTIM related callback function pointer         */

+

+typedef void (* pHRTIM_TIMxCallbackTypeDef)(HRTIM_HandleTypeDef *hhrtim,    /*!< HRTIM Timer x related callback function pointer */

+                                            uint32_t TimerIdx);

+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup HRTIM_Exported_Constants HRTIM Exported Constants

+  * @{

+  */

+

+/** @defgroup HRTIM_Timer_Index HRTIM Timer Index

+  * @{

+  * @brief Constants defining the timer indexes

+  */

+#define HRTIM_TIMERINDEX_TIMER_A 0x0U   /*!< Index used to access timer A registers */

+#define HRTIM_TIMERINDEX_TIMER_B 0x1U   /*!< Index used to access timer B registers */

+#define HRTIM_TIMERINDEX_TIMER_C 0x2U   /*!< Index used to access timer C registers */

+#define HRTIM_TIMERINDEX_TIMER_D 0x3U   /*!< Index used to access timer D registers */

+#define HRTIM_TIMERINDEX_TIMER_E 0x4U   /*!< Index used to access timer E registers */

+#define HRTIM_TIMERINDEX_MASTER  0x5U   /*!< Index used to access master registers  */

+#define HRTIM_TIMERINDEX_COMMON  0xFFU  /*!< Index used to access HRTIM common registers */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Timer_identifier HRTIM Timer identifier

+  * @{

+  * @brief Constants defining timer identifiers

+  */

+#define HRTIM_TIMERID_MASTER  (HRTIM_MCR_MCEN)   /*!< Master identifier  */

+#define HRTIM_TIMERID_TIMER_A (HRTIM_MCR_TACEN)  /*!< Timer A identifier */

+#define HRTIM_TIMERID_TIMER_B (HRTIM_MCR_TBCEN)  /*!< Timer B identifier */

+#define HRTIM_TIMERID_TIMER_C (HRTIM_MCR_TCCEN)  /*!< Timer C identifier */

+#define HRTIM_TIMERID_TIMER_D (HRTIM_MCR_TDCEN)  /*!< Timer D identifier */

+#define HRTIM_TIMERID_TIMER_E (HRTIM_MCR_TECEN)  /*!< Timer E identifier */

+/**

+ * @}

+ */

+

+/** @defgroup HRTIM_Compare_Unit HRTIM Compare Unit

+  * @{

+  * @brief Constants defining compare unit identifiers

+  */

+#define HRTIM_COMPAREUNIT_1 0x00000001U  /*!< Compare unit 1 identifier */

+#define HRTIM_COMPAREUNIT_2 0x00000002U  /*!< Compare unit 2 identifier */

+#define HRTIM_COMPAREUNIT_3 0x00000004U  /*!< Compare unit 3 identifier */

+#define HRTIM_COMPAREUNIT_4 0x00000008U  /*!< Compare unit 4 identifier */

+ /**

+  * @}

+  */

+

+/** @defgroup HRTIM_Capture_Unit HRTIM Capture Unit

+  * @{

+  * @brief Constants defining capture unit identifiers

+  */

+#define HRTIM_CAPTUREUNIT_1 0x00000001U  /*!< Capture unit 1 identifier */

+#define HRTIM_CAPTUREUNIT_2 0x00000002U  /*!< Capture unit 2 identifier */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Timer_Output HRTIM Timer Output

+  * @{

+  * @brief Constants defining timer output identifiers

+  */

+#define HRTIM_OUTPUT_TA1  0x00000001U  /*!< Timer A - Output 1 identifier */

+#define HRTIM_OUTPUT_TA2  0x00000002U  /*!< Timer A - Output 2 identifier */

+#define HRTIM_OUTPUT_TB1  0x00000004U  /*!< Timer B - Output 1 identifier */

+#define HRTIM_OUTPUT_TB2  0x00000008U  /*!< Timer B - Output 2 identifier */

+#define HRTIM_OUTPUT_TC1  0x00000010U  /*!< Timer C - Output 1 identifier */

+#define HRTIM_OUTPUT_TC2  0x00000020U  /*!< Timer C - Output 2 identifier */

+#define HRTIM_OUTPUT_TD1  0x00000040U  /*!< Timer D - Output 1 identifier */

+#define HRTIM_OUTPUT_TD2  0x00000080U  /*!< Timer D - Output 2 identifier */

+#define HRTIM_OUTPUT_TE1  0x00000100U  /*!< Timer E - Output 1 identifier */

+#define HRTIM_OUTPUT_TE2  0x00000200U  /*!< Timer E - Output 2 identifier */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_ADC_Trigger HRTIM ADC Trigger

+  * @{

+  * @brief Constants defining ADC triggers identifiers

+  */

+#define HRTIM_ADCTRIGGER_1  0x00000001U  /*!< ADC trigger 1 identifier */

+#define HRTIM_ADCTRIGGER_2  0x00000002U  /*!< ADC trigger 2 identifier */

+#define HRTIM_ADCTRIGGER_3  0x00000004U  /*!< ADC trigger 3 identifier */

+#define HRTIM_ADCTRIGGER_4  0x00000008U  /*!< ADC trigger 4 identifier */

+

+#define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\

+    (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1)   || \

+     ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2)   || \

+     ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3)   || \

+     ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4))

+/**

+  * @}

+  */

+/** @defgroup HRTIM_External_Event_Channels HRTIM External Event Channels

+  * @{

+  * @brief Constants defining external event channel identifiers

+  */

+#define HRTIM_EVENT_NONE    (0x00000000U)     /*!< Undefined event channel */

+#define HRTIM_EVENT_1       (0x00000001U)     /*!< External event channel 1  identifier */

+#define HRTIM_EVENT_2       (0x00000002U)     /*!< External event channel 2  identifier */

+#define HRTIM_EVENT_3       (0x00000003U)     /*!< External event channel 3  identifier */

+#define HRTIM_EVENT_4       (0x00000004U)     /*!< External event channel 4  identifier */

+#define HRTIM_EVENT_5       (0x00000005U)     /*!< External event channel 5  identifier */

+#define HRTIM_EVENT_6       (0x00000006U)     /*!< External event channel 6  identifier */

+#define HRTIM_EVENT_7       (0x00000007U)     /*!< External event channel 7  identifier */

+#define HRTIM_EVENT_8       (0x00000008U)     /*!< External event channel 8  identifier */

+#define HRTIM_EVENT_9       (0x00000009U)     /*!< External event channel 9  identifier */

+#define HRTIM_EVENT_10      (0x0000000AU)     /*!< External event channel 10 identifier */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Fault_Channel HRTIM Fault Channel

+  * @{

+  * @brief Constants defining fault channel identifiers

+  */

+#define HRTIM_FAULT_1      (0x01U)     /*!< Fault channel 1 identifier */

+#define HRTIM_FAULT_2      (0x02U)     /*!< Fault channel 2 identifier */

+#define HRTIM_FAULT_3      (0x04U)     /*!< Fault channel 3 identifier */

+#define HRTIM_FAULT_4      (0x08U)     /*!< Fault channel 4 identifier */

+#define HRTIM_FAULT_5      (0x10U)     /*!< Fault channel 5 identifier */

+/**

+  * @}

+  */

+

+

+ /** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio

+  * @{

+  * @brief Constants defining timer high-resolution clock prescaler ratio.

+  */

+#define HRTIM_PRESCALERRATIO_DIV1     (0x00000005U)  /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)         */

+#define HRTIM_PRESCALERRATIO_DIV2     (0x00000006U)  /*!< fHRCK: fHRTIM / 2U = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)     */

+#define HRTIM_PRESCALERRATIO_DIV4     (0x00000007U)  /*!< fHRCK: fHRTIM / 4U = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)        */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Counter_Operating_Mode HRTIM Counter Operating Mode

+  * @{

+  * @brief Constants defining timer counter operating mode.

+  */

+#define HRTIM_MODE_CONTINUOUS               (0x00000008U)  /*!< The timer operates in continuous (free-running) mode */

+#define HRTIM_MODE_SINGLESHOT               (0x00000000U)  /*!< The timer operates in non retriggerable single-shot mode */

+#define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE (0x00000010U)  /*!< The timer operates in retriggerable single-shot mode */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Half_Mode_Enable HRTIM Half Mode Enable

+  * @{

+  * @brief Constants defining half mode enabling status.

+  */

+#define HRTIM_HALFMODE_DISABLED (0x00000000U)  /*!< Half mode is disabled */

+#define HRTIM_HALFMODE_ENABLED  (0x00000020U)  /*!< Half mode is enabled */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Start_On_Sync_Input_Event HRTIM Start On Sync Input Event

+  * @{

+  * @brief Constants defining the timer behavior following the synchronization event

+  */

+#define HRTIM_SYNCSTART_DISABLED (0x00000000U)           /*!< Synchronization input event has effect on the timer */

+#define HRTIM_SYNCSTART_ENABLED  (HRTIM_MCR_SYNCSTRTM)   /*!< Synchronization input event starts the timer */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Reset_On_Sync_Input_Event HRTIM Reset On Sync Input Event

+  * @{

+  * @brief Constants defining the timer behavior following the synchronization event

+  */

+#define HRTIM_SYNCRESET_DISABLED (0x00000000U)           /*!< Synchronization input event has effect on the timer */

+#define HRTIM_SYNCRESET_ENABLED  (HRTIM_MCR_SYNCRSTM)    /*!< Synchronization input event resets the timer */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_DAC_Synchronization HRTIM DAC Synchronization

+  * @{

+  * @brief Constants defining on which output the DAC synchronization event is sent

+  */

+#define HRTIM_DACSYNC_NONE          0x00000000U                                 /*!< No DAC synchronization event generated */

+#define HRTIM_DACSYNC_DACTRIGOUT_1  (HRTIM_MCR_DACSYNC_0)                       /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */

+#define HRTIM_DACSYNC_DACTRIGOUT_2  (HRTIM_MCR_DACSYNC_1)                       /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */

+#define HRTIM_DACSYNC_DACTRIGOUT_3  (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC update generated on DACTrigOut3 output upon timer update */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Register_Preload_Enable HRTIM Register Preload Enable

+  * @{

+  * @brief Constants defining whether a write access into a preloadable

+  *        register is done into the active or the preload register.

+  */

+#define HRTIM_PRELOAD_DISABLED (0x00000000U)           /*!< Preload disabled: the write access is directly done into the active register */

+#define HRTIM_PRELOAD_ENABLED  (HRTIM_MCR_PREEN)       /*!< Preload enabled: the write access is done into the preload register */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Update_Gating HRTIM Update Gating

+  * @{

+  * @brief Constants defining how the update occurs relatively to the burst DMA

+  *        transaction and the external update request on update enable inputs 1 to 3.

+  */

+#define HRTIM_UPDATEGATING_INDEPENDENT     0x00000000U                                                           /*!< Update done independently from the DMA burst transfer completion */

+#define HRTIM_UPDATEGATING_DMABURST        (HRTIM_TIMCR_UPDGAT_0)                                                /*!< Update done when the DMA burst transfer is completed */

+#define HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1)                                                /*!< Update done on timer roll-over following a DMA burst transfer completion*/

+#define HRTIM_UPDATEGATING_UPDEN1          (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)                         /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1U */

+#define HRTIM_UPDATEGATING_UPDEN2          (HRTIM_TIMCR_UPDGAT_2)                                                /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2U */

+#define HRTIM_UPDATEGATING_UPDEN3          (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0)                         /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3U */

+#define HRTIM_UPDATEGATING_UPDEN1_UPDATE   (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1)                         /*!< Slave timer only -  Update done on the update event following a rising edge of HRTIM update enable input 1U */

+#define HRTIM_UPDATEGATING_UPDEN2_UPDATE   (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)  /*!< Slave timer only -  Update done on the update event following a rising edge of HRTIM update enable input 2U */

+#define HRTIM_UPDATEGATING_UPDEN3_UPDATE   (HRTIM_TIMCR_UPDGAT_3)                                                /*!< Slave timer only -  Update done on the update event following a rising edge of HRTIM update enable input 3U */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Timer_Burst_Mode HRTIM Timer Burst Mode

+  * @{

+  * @brief Constants defining how the timer behaves during a burst

+            mode operation.

+  */

+#define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK 0x00000000U           /*!< Timer counter clock is maintained and the timer operates normally */

+#define HRTIM_TIMERBURSTMODE_RESETCOUNTER  (HRTIM_BMCR_MTBM)     /*!< Timer counter clock is stopped and the counter is reset */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Timer_Repetition_Update HRTIM Timer Repetition Update

+  * @{

+  * @brief Constants defining whether registers are updated when the timer

+  *        repetition period is completed (either due to roll-over or

+  *        reset events)

+  */

+#define HRTIM_UPDATEONREPETITION_DISABLED  0x00000000U           /*!< Update on repetition disabled */

+#define HRTIM_UPDATEONREPETITION_ENABLED   (HRTIM_MCR_MREPU)     /*!< Update on repetition enabled */

+/**

+  * @}

+  */

+

+

+/** @defgroup HRTIM_Timer_Push_Pull_Mode HRTIM Timer Push Pull Mode

+  * @{

+  * @brief Constants defining whether or not the push-pull mode is enabled for

+  *        a timer.

+  */

+#define HRTIM_TIMPUSHPULLMODE_DISABLED     0x00000000U           /*!< Push-Pull mode disabled */

+#define HRTIM_TIMPUSHPULLMODE_ENABLED      (HRTIM_TIMCR_PSHPLL)  /*!< Push-Pull mode enabled */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Timer_Fault_Enabling HRTIM Timer Fault Enabling

+  * @{

+  * @brief Constants defining whether a fault channel is enabled for a timer

+  */

+#define HRTIM_TIMFAULTENABLE_NONE     0x00000000U           /*!< No fault enabled */

+#define HRTIM_TIMFAULTENABLE_FAULT1   (HRTIM_FLTR_FLT1EN)   /*!< Fault 1 enabled */

+#define HRTIM_TIMFAULTENABLE_FAULT2   (HRTIM_FLTR_FLT2EN)   /*!< Fault 2 enabled */

+#define HRTIM_TIMFAULTENABLE_FAULT3   (HRTIM_FLTR_FLT3EN)   /*!< Fault 3 enabled */

+#define HRTIM_TIMFAULTENABLE_FAULT4   (HRTIM_FLTR_FLT4EN)   /*!< Fault 4 enabled */

+#define HRTIM_TIMFAULTENABLE_FAULT5   (HRTIM_FLTR_FLT5EN)   /*!< Fault 5 enabled */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Timer_Fault_Lock HRTIM Timer Fault Lock

+  * @{

+  * @brief Constants defining whether or not fault enabling bits are write

+  *        protected for a timer

+  */

+#define HRTIM_TIMFAULTLOCK_READWRITE (0x00000000U)           /*!< Timer fault enabling bits are read/write */

+#define HRTIM_TIMFAULTLOCK_READONLY  (HRTIM_FLTR_FLTLCK)     /*!< Timer fault enabling bits are read only */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Timer_Deadtime_Insertion HRTIM Timer Dead-time Insertion

+  * @{

+  * @brief Constants defining whether or not fault the dead time insertion

+  *        feature is enabled for a timer

+  */

+#define HRTIM_TIMDEADTIMEINSERTION_DISABLED   (0x00000000U)           /*!< Output 1 and output 2 signals are independent */

+#define HRTIM_TIMDEADTIMEINSERTION_ENABLED    HRTIM_OUTR_DTEN         /*!< Dead-time is inserted between output 1 and output 2U */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Timer_Delayed_Protection_Mode HRTIM Timer Delayed Protection Mode

+  * @{

+  * @brief Constants defining all possible delayed protection modes

+  *        for a timer. Also define the source and outputs on which the delayed

+  *        protection schemes are applied

+  */

+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED          (0x00000000U)                                                                           /*!< No action */

+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6  (HRTIM_OUTR_DLYPRTEN)                                                                   /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6U */

+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6  (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                                             /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6U */

+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6  (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                                             /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6U */

+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6     (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                       /*!< Timers A, B, C: Balanced Idle on external Event 6U */

+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN)                                             /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7U */

+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                       /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7U */

+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7  (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                       /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7U */

+#define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7     (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 7U */

+

+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DISABLED            (0x00000000U)                                                                             /*!< No action */

+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_EEV8    (HRTIM_OUTR_DLYPRTEN)                                                                     /*!< Timers D, E: Output 1 delayed Idle on external Event 6U */

+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_EEV8    (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                                               /*!< Timers D, E: Output 2 delayed Idle on external Event 6U */

+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV8    (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                                               /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 6U */

+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV8       (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                         /*!< Timers D, E: Balanced Idle on external Event 6U */

+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9   (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN)                                               /*!< Timers D, E: Output 1 delayed Idle on external Event 7U */

+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9   (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)                         /*!< Timers D, E: Output 2 delayed Idle on external Event 7U */

+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV9    (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN)                         /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 7U */

+#define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV9       (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN)   /*!< Timers D, E: Balanced Idle on external Event 7U */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Timer_Update_Trigger HRTIM Timer Update Trigger

+  * @{

+  * @brief Constants defining whether the registers update is done synchronously

+  *        with any other timer or master update

+  */

+#define HRTIM_TIMUPDATETRIGGER_NONE     0x00000000U          /*!< Register update is disabled */

+#define HRTIM_TIMUPDATETRIGGER_MASTER   (HRTIM_TIMCR_MSTU)   /*!< Register update is triggered by the master timer update */

+#define HRTIM_TIMUPDATETRIGGER_TIMER_A  (HRTIM_TIMCR_TAU)    /*!< Register update is triggered by the timer A update */

+#define HRTIM_TIMUPDATETRIGGER_TIMER_B  (HRTIM_TIMCR_TBU)    /*!< Register update is triggered by the timer B update */

+#define HRTIM_TIMUPDATETRIGGER_TIMER_C  (HRTIM_TIMCR_TCU)    /*!< Register update is triggered by the timer C update*/

+#define HRTIM_TIMUPDATETRIGGER_TIMER_D  (HRTIM_TIMCR_TDU)    /*!< Register update is triggered by the timer D update */

+#define HRTIM_TIMUPDATETRIGGER_TIMER_E  (HRTIM_TIMCR_TEU)    /*!< Register update is triggered by the timer E update */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Timer_Reset_Trigger HRTIM Timer Reset Trigger

+  * @{

+  * @brief Constants defining the events that can be selected to trigger the reset

+  *        of the timer counter

+  */

+#define HRTIM_TIMRESETTRIGGER_NONE        0x00000000U            /*!< No counter reset trigger */

+#define HRTIM_TIMRESETTRIGGER_UPDATE      (HRTIM_RSTR_UPDATE)    /*!< The timer counter is reset upon update event */

+#define HRTIM_TIMRESETTRIGGER_CMP2        (HRTIM_RSTR_CMP2)      /*!< The timer counter is reset upon Timer Compare 2 event */

+#define HRTIM_TIMRESETTRIGGER_CMP4        (HRTIM_RSTR_CMP4)      /*!< The timer counter is reset upon Timer Compare 4 event */

+#define HRTIM_TIMRESETTRIGGER_MASTER_PER  (HRTIM_RSTR_MSTPER)    /*!< The timer counter is reset upon master timer period event */

+#define HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1)   /*!< The timer counter is reset upon master timer Compare 1 event */

+#define HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2)   /*!< The timer counter is reset upon master timer Compare 2 event */

+#define HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3)   /*!< The timer counter is reset upon master timer Compare 3 event */

+#define HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4)   /*!< The timer counter is reset upon master timer Compare 4 event */

+#define HRTIM_TIMRESETTRIGGER_EEV_1       (HRTIM_RSTR_EXTEVNT1)  /*!< The timer counter is reset upon external event 1U */

+#define HRTIM_TIMRESETTRIGGER_EEV_2       (HRTIM_RSTR_EXTEVNT2)  /*!< The timer counter is reset upon external event 2U */

+#define HRTIM_TIMRESETTRIGGER_EEV_3       (HRTIM_RSTR_EXTEVNT3)  /*!< The timer counter is reset upon external event 3U */

+#define HRTIM_TIMRESETTRIGGER_EEV_4       (HRTIM_RSTR_EXTEVNT4)  /*!< The timer counter is reset upon external event 4U */

+#define HRTIM_TIMRESETTRIGGER_EEV_5       (HRTIM_RSTR_EXTEVNT5)  /*!< The timer counter is reset upon external event 5U */

+#define HRTIM_TIMRESETTRIGGER_EEV_6       (HRTIM_RSTR_EXTEVNT6)  /*!< The timer counter is reset upon external event 6U */

+#define HRTIM_TIMRESETTRIGGER_EEV_7       (HRTIM_RSTR_EXTEVNT7)  /*!< The timer counter is reset upon external event 7U */

+#define HRTIM_TIMRESETTRIGGER_EEV_8       (HRTIM_RSTR_EXTEVNT8)  /*!< The timer counter is reset upon external event 8U */

+#define HRTIM_TIMRESETTRIGGER_EEV_9       (HRTIM_RSTR_EXTEVNT9)  /*!< The timer counter is reset upon external event 9U */

+#define HRTIM_TIMRESETTRIGGER_EEV_10      (HRTIM_RSTR_EXTEVNT10) /*!< The timer counter is reset upon external event 10U */

+#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1)  /*!< The timer counter is reset upon other timer Compare 1 event */

+#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2)  /*!< The timer counter is reset upon other timer Compare 2 event */

+#define HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4)  /*!< The timer counter is reset upon other timer Compare 4 event */

+#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1)  /*!< The timer counter is reset upon other timer Compare 1 event */

+#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2)  /*!< The timer counter is reset upon other timer Compare 2 event */

+#define HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4)  /*!< The timer counter is reset upon other timer Compare 4 event */

+#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1)  /*!< The timer counter is reset upon other timer Compare 1 event */

+#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2)  /*!< The timer counter is reset upon other timer Compare 2 event */

+#define HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4)  /*!< The timer counter is reset upon other timer Compare 4 event */

+#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1)  /*!< The timer counter is reset upon other timer Compare 1 event */

+#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2)  /*!< The timer counter is reset upon other timer Compare 2 event */

+#define HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4)  /*!< The timer counter is reset upon other timer Compare 4 event */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Timer_Reset_Update HRTIM Timer Reset Update

+  * @{

+  * @brief Constants defining whether the register are updated upon Timerx

+  *        counter reset or roll-over to 0 after reaching the period value

+  *        in continuous mode

+  */

+#define HRTIM_TIMUPDATEONRESET_DISABLED 0x00000000U           /*!< Update by timer x reset / roll-over disabled */

+#define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU)    /*!< Update by timer x reset / roll-over enabled */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Compare_Unit_Auto_Delayed_Mode HRTIM Compare Unit Auto Delayed Mode

+  * @{

+  * @brief Constants defining whether the compare register is behaving in

+  *        regular mode (compare match issued as soon as counter equal compare),

+  *        or in auto-delayed mode

+  */

+#define HRTIM_AUTODELAYEDMODE_REGULAR                 (0x00000000U)                                   /*!< standard compare mode */

+#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT   (HRTIM_TIMCR_DELCMP2_0)                         /*!< Compare event generated only if a capture has occurred */

+#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1)                         /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */

+#define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Simple_OC_Mode HRTIM Simple OC Mode

+  * @{

+  * @brief Constants defining the behavior of the output signal when the timer

+           operates in basic output compare mode

+  */

+#define HRTIM_BASICOCMODE_TOGGLE    (0x00000001U)  /*!< Output toggles when the timer counter reaches the compare value */

+#define HRTIM_BASICOCMODE_INACTIVE  (0x00000002U)  /*!< Output forced to active level when the timer counter reaches the compare value */

+#define HRTIM_BASICOCMODE_ACTIVE    (0x00000003U)  /*!< Output forced to inactive level when the timer counter reaches the compare value */

+

+#define IS_HRTIM_BASICOCMODE(BASICOCMODE)\

+              (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE)   || \

+               ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \

+               ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE))

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Output_Polarity HRTIM Output Polarity

+  * @{

+  * @brief Constants defining the polarity of a timer output

+  */

+#define HRTIM_OUTPUTPOLARITY_HIGH    (0x00000000U)           /*!< Output is acitve HIGH */

+#define HRTIM_OUTPUTPOLARITY_LOW     (HRTIM_OUTR_POL1)       /*!< Output is active LOW */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Output_Set_Source HRTIM Output Set Source

+  * @{

+  * @brief Constants defining the events that can be selected to configure the

+  *        set crossbar of a timer output

+  */

+#define HRTIM_OUTPUTSET_NONE       0x00000000U                      /*!< Reset the output set crossbar */

+#define HRTIM_OUTPUTSET_RESYNC     (HRTIM_SET1R_RESYNC)             /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state */

+#define HRTIM_OUTPUTSET_TIMPER     (HRTIM_SET1R_PER)                /*!< Timer period event forces the output to its active state */

+#define HRTIM_OUTPUTSET_TIMCMP1    (HRTIM_SET1R_CMP1)               /*!< Timer compare 1 event forces the output to its active state */

+#define HRTIM_OUTPUTSET_TIMCMP2    (HRTIM_SET1R_CMP2)               /*!< Timer compare 2 event forces the output to its active state */

+#define HRTIM_OUTPUTSET_TIMCMP3    (HRTIM_SET1R_CMP3)               /*!< Timer compare 3 event forces the output to its active state */

+#define HRTIM_OUTPUTSET_TIMCMP4    (HRTIM_SET1R_CMP4)               /*!< Timer compare 4 event forces the output to its active state */

+#define HRTIM_OUTPUTSET_MASTERPER  (HRTIM_SET1R_MSTPER)             /*!< The master timer period event forces the output to its active state */

+#define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1)            /*!< Master Timer compare 1 event forces the output to its active state */

+#define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2)            /*!< Master Timer compare 2 event forces the output to its active state */

+#define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3)            /*!< Master Timer compare 3 event forces the output to its active state */

+#define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4)            /*!< Master Timer compare 4 event forces the output to its active state */

+#define HRTIM_OUTPUTSET_TIMEV_1    (HRTIM_SET1R_TIMEVNT1)           /*!< Timer event 1 forces the output to its active state */

+#define HRTIM_OUTPUTSET_TIMEV_2    (HRTIM_SET1R_TIMEVNT2)           /*!< Timer event 2 forces the output to its active state */

+#define HRTIM_OUTPUTSET_TIMEV_3    (HRTIM_SET1R_TIMEVNT3)           /*!< Timer event 3 forces the output to its active state */

+#define HRTIM_OUTPUTSET_TIMEV_4    (HRTIM_SET1R_TIMEVNT4)           /*!< Timer event 4 forces the output to its active state */

+#define HRTIM_OUTPUTSET_TIMEV_5    (HRTIM_SET1R_TIMEVNT5)           /*!< Timer event 5 forces the output to its active state */

+#define HRTIM_OUTPUTSET_TIMEV_6    (HRTIM_SET1R_TIMEVNT6)           /*!< Timer event 6 forces the output to its active state */

+#define HRTIM_OUTPUTSET_TIMEV_7    (HRTIM_SET1R_TIMEVNT7)           /*!< Timer event 7 forces the output to its active state */

+#define HRTIM_OUTPUTSET_TIMEV_8    (HRTIM_SET1R_TIMEVNT8)           /*!< Timer event 8 forces the output to its active state */

+#define HRTIM_OUTPUTSET_TIMEV_9    (HRTIM_SET1R_TIMEVNT9)           /*!< Timer event 9 forces the output to its active state */

+#define HRTIM_OUTPUTSET_EEV_1      (HRTIM_SET1R_EXTVNT1)            /*!< External event 1 forces the output to its active state */

+#define HRTIM_OUTPUTSET_EEV_2      (HRTIM_SET1R_EXTVNT2)            /*!< External event 2 forces the output to its active state */

+#define HRTIM_OUTPUTSET_EEV_3      (HRTIM_SET1R_EXTVNT3)            /*!< External event 3 forces the output to its active state */

+#define HRTIM_OUTPUTSET_EEV_4      (HRTIM_SET1R_EXTVNT4)            /*!< External event 4 forces the output to its active state */

+#define HRTIM_OUTPUTSET_EEV_5      (HRTIM_SET1R_EXTVNT5)            /*!< External event 5 forces the output to its active state */

+#define HRTIM_OUTPUTSET_EEV_6      (HRTIM_SET1R_EXTVNT6)            /*!< External event 6 forces the output to its active state */

+#define HRTIM_OUTPUTSET_EEV_7      (HRTIM_SET1R_EXTVNT7)            /*!< External event 7 forces the output to its active state */

+#define HRTIM_OUTPUTSET_EEV_8      (HRTIM_SET1R_EXTVNT8)            /*!< External event 8 forces the output to its active state */

+#define HRTIM_OUTPUTSET_EEV_9      (HRTIM_SET1R_EXTVNT9)            /*!< External event 9 forces the output to its active state */

+#define HRTIM_OUTPUTSET_EEV_10     (HRTIM_SET1R_EXTVNT10)           /*!< External event 10 forces the output to its active state */

+#define HRTIM_OUTPUTSET_UPDATE     (HRTIM_SET1R_UPDATE)             /*!< Timer register update event forces the output to its active state */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source

+  * @{

+  * @brief Constants defining the events that can be selected to configure the

+  *        set crossbar of a timer output

+  */

+#define HRTIM_OUTPUTRESET_NONE       0x00000000U                      /*!< Reset the output reset crossbar */

+#define HRTIM_OUTPUTRESET_RESYNC     (HRTIM_RST1R_RESYNC)             /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */

+#define HRTIM_OUTPUTRESET_TIMPER     (HRTIM_RST1R_PER)                /*!< Timer period event forces the output to its inactive state */

+#define HRTIM_OUTPUTRESET_TIMCMP1    (HRTIM_RST1R_CMP1)               /*!< Timer compare 1 event forces the output to its inactive state */

+#define HRTIM_OUTPUTRESET_TIMCMP2    (HRTIM_RST1R_CMP2)               /*!< Timer compare 2 event forces the output to its inactive state */

+#define HRTIM_OUTPUTRESET_TIMCMP3    (HRTIM_RST1R_CMP3)               /*!< Timer compare 3 event forces the output to its inactive state */

+#define HRTIM_OUTPUTRESET_TIMCMP4    (HRTIM_RST1R_CMP4)               /*!< Timer compare 4 event forces the output to its inactive state */

+#define HRTIM_OUTPUTRESET_MASTERPER  (HRTIM_RST1R_MSTPER)             /*!< The master timer period event forces the output to its inactive state */

+#define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1)            /*!< Master Timer compare 1 event forces the output to its inactive state */

+#define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2)            /*!< Master Timer compare 2 event forces the output to its inactive state */

+#define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3)            /*!< Master Timer compare 3 event forces the output to its inactive state */

+#define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4)            /*!< Master Timer compare 4 event forces the output to its inactive state */

+#define HRTIM_OUTPUTRESET_TIMEV_1    (HRTIM_SET1R_TIMEVNT1)           /*!< Timer event 1 forces the output to its active state */

+#define HRTIM_OUTPUTRESET_TIMEV_2    (HRTIM_SET1R_TIMEVNT2)           /*!< Timer event 2 forces the output to its active state */

+#define HRTIM_OUTPUTRESET_TIMEV_3    (HRTIM_SET1R_TIMEVNT3)           /*!< Timer event 3 forces the output to its active state */

+#define HRTIM_OUTPUTRESET_TIMEV_4    (HRTIM_SET1R_TIMEVNT4)           /*!< Timer event 4 forces the output to its active state */

+#define HRTIM_OUTPUTRESET_TIMEV_5    (HRTIM_SET1R_TIMEVNT5)           /*!< Timer event 5 forces the output to its active state */

+#define HRTIM_OUTPUTRESET_TIMEV_6    (HRTIM_SET1R_TIMEVNT6)           /*!< Timer event 6 forces the output to its active state */

+#define HRTIM_OUTPUTRESET_TIMEV_7    (HRTIM_SET1R_TIMEVNT7)           /*!< Timer event 7 forces the output to its active state */

+#define HRTIM_OUTPUTRESET_TIMEV_8    (HRTIM_SET1R_TIMEVNT8)           /*!< Timer event 8 forces the output to its active state */

+#define HRTIM_OUTPUTRESET_TIMEV_9    (HRTIM_SET1R_TIMEVNT9)           /*!< Timer event 9 forces the output to its active state */

+#define HRTIM_OUTPUTRESET_EEV_1      (HRTIM_RST1R_EXTVNT1)            /*!< External event 1 forces the output to its inactive state */

+#define HRTIM_OUTPUTRESET_EEV_2      (HRTIM_RST1R_EXTVNT2)            /*!< External event 2 forces the output to its inactive state */

+#define HRTIM_OUTPUTRESET_EEV_3      (HRTIM_RST1R_EXTVNT3)            /*!< External event 3 forces the output to its inactive state */

+#define HRTIM_OUTPUTRESET_EEV_4      (HRTIM_RST1R_EXTVNT4)            /*!< External event 4 forces the output to its inactive state */

+#define HRTIM_OUTPUTRESET_EEV_5      (HRTIM_RST1R_EXTVNT5)            /*!< External event 5 forces the output to its inactive state */

+#define HRTIM_OUTPUTRESET_EEV_6      (HRTIM_RST1R_EXTVNT6)            /*!< External event 6 forces the output to its inactive state */

+#define HRTIM_OUTPUTRESET_EEV_7      (HRTIM_RST1R_EXTVNT7)            /*!< External event 7 forces the output to its inactive state */

+#define HRTIM_OUTPUTRESET_EEV_8      (HRTIM_RST1R_EXTVNT8)            /*!< External event 8 forces the output to its inactive state */

+#define HRTIM_OUTPUTRESET_EEV_9      (HRTIM_RST1R_EXTVNT9)            /*!< External event 9 forces the output to its inactive state */

+#define HRTIM_OUTPUTRESET_EEV_10     (HRTIM_RST1R_EXTVNT10)           /*!< External event 10 forces the output to its inactive state */

+#define HRTIM_OUTPUTRESET_UPDATE     (HRTIM_RST1R_UPDATE)             /*!< Timer register update event forces the output to its inactive state */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Output_Idle_Mode HRTIM Output Idle Mode

+  * @{

+  * @brief Constants defining whether or not the timer output transition to its

+           IDLE state when burst mode is entered

+  */

+#define HRTIM_OUTPUTIDLEMODE_NONE     0x00000000U           /*!< The output is not affected by the burst mode operation */

+#define HRTIM_OUTPUTIDLEMODE_IDLE     (HRTIM_OUTR_IDLM1)    /*!< The output is in idle state when requested by the burst mode controller */

+ /**

+  * @}

+  */

+

+/** @defgroup HRTIM_Output_IDLE_Level HRTIM Output IDLE Level

+  * @{

+  * @brief Constants defining the output level when output is in IDLE state

+  */

+#define HRTIM_OUTPUTIDLELEVEL_INACTIVE   0x00000000U           /*!< Output at inactive level when in IDLE state */

+#define HRTIM_OUTPUTIDLELEVEL_ACTIVE     (HRTIM_OUTR_IDLES1)   /*!< Output at active level when in IDLE state */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Output_FAULT_Level HRTIM Output FAULT Level

+  * @{

+  * @brief Constants defining the output level when output is in FAULT state

+  */

+#define HRTIM_OUTPUTFAULTLEVEL_NONE      0x00000000U                                  /*!< The output is not affected by the fault input */

+#define HRTIM_OUTPUTFAULTLEVEL_ACTIVE    (HRTIM_OUTR_FAULT1_0)                        /*!< Output at active level when in FAULT state */

+#define HRTIM_OUTPUTFAULTLEVEL_INACTIVE  (HRTIM_OUTR_FAULT1_1)                        /*!< Output at inactive level when in FAULT state */

+#define HRTIM_OUTPUTFAULTLEVEL_HIGHZ     (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0)  /*!< Output is tri-stated when in FAULT state */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Output_Chopper_Mode_Enable HRTIM Output Chopper Mode Enable

+  * @{

+  * @brief Constants defining whether or not chopper mode is enabled for a timer

+           output

+  */

+#define HRTIM_OUTPUTCHOPPERMODE_DISABLED   0x00000000U           /*!< Output signal is not altered  */

+#define HRTIM_OUTPUTCHOPPERMODE_ENABLED    (HRTIM_OUTR_CHP1)     /*!< Output signal is chopped by a carrier signal  */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Output_Burst_Mode_Entry_Delayed HRTIM Output Burst Mode Entry Delayed

+  * @{

+  * @brief Constants defining the idle mode entry is delayed by forcing a

+           dead-time insertion before switching the outputs to their idle state

+  */

+#define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR   0x00000000U           /*!< The programmed Idle state is applied immediately to the Output */

+#define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED   (HRTIM_OUTR_DIDL1)    /*!< Dead-time is inserted on output before entering the idle mode */

+/**

+  * @}

+  */

+

+

+/** @defgroup HRTIM_Capture_Unit_Trigger HRTIM Capture Unit Trigger

+  * @{

+  * @brief Constants defining the events that can be selected to trigger the

+  *        capture of the timing unit counter

+  */

+#define HRTIM_CAPTURETRIGGER_NONE         0x00000000U              /*!< Capture trigger is disabled */

+#define HRTIM_CAPTURETRIGGER_UPDATE       (HRTIM_CPT1CR_UPDCPT)    /*!< The update event triggers the Capture */

+#define HRTIM_CAPTURETRIGGER_EEV_1        (HRTIM_CPT1CR_EXEV1CPT)  /*!< The External event 1 triggers the Capture */

+#define HRTIM_CAPTURETRIGGER_EEV_2        (HRTIM_CPT1CR_EXEV2CPT)  /*!< The External event 2 triggers the Capture */

+#define HRTIM_CAPTURETRIGGER_EEV_3        (HRTIM_CPT1CR_EXEV3CPT)  /*!< The External event 3 triggers the Capture */

+#define HRTIM_CAPTURETRIGGER_EEV_4        (HRTIM_CPT1CR_EXEV4CPT)  /*!< The External event 4 triggers the Capture */

+#define HRTIM_CAPTURETRIGGER_EEV_5        (HRTIM_CPT1CR_EXEV5CPT)  /*!< The External event 5 triggers the Capture */

+#define HRTIM_CAPTURETRIGGER_EEV_6        (HRTIM_CPT1CR_EXEV6CPT)  /*!< The External event 6 triggers the Capture */

+#define HRTIM_CAPTURETRIGGER_EEV_7        (HRTIM_CPT1CR_EXEV7CPT)  /*!< The External event 7 triggers the Capture */

+#define HRTIM_CAPTURETRIGGER_EEV_8        (HRTIM_CPT1CR_EXEV8CPT)  /*!< The External event 8 triggers the Capture */

+#define HRTIM_CAPTURETRIGGER_EEV_9        (HRTIM_CPT1CR_EXEV9CPT)  /*!< The External event 9 triggers the Capture */

+#define HRTIM_CAPTURETRIGGER_EEV_10       (HRTIM_CPT1CR_EXEV10CPT) /*!< The External event 10 triggers the Capture */

+#define HRTIM_CAPTURETRIGGER_TA1_SET      (HRTIM_CPT1CR_TA1SET)    /*!< Capture is triggered by TA1 output inactive to active transition */

+#define HRTIM_CAPTURETRIGGER_TA1_RESET    (HRTIM_CPT1CR_TA1RST)    /*!< Capture is triggered by TA1 output active to inactive transition */

+#define HRTIM_CAPTURETRIGGER_TIMERA_CMP1  (HRTIM_CPT1CR_TIMACMP1)  /*!< Timer A Compare 1 triggers Capture */

+#define HRTIM_CAPTURETRIGGER_TIMERA_CMP2  (HRTIM_CPT1CR_TIMACMP2)  /*!< Timer A Compare 2 triggers Capture */

+#define HRTIM_CAPTURETRIGGER_TB1_SET      (HRTIM_CPT1CR_TB1SET)    /*!< Capture is triggered by TB1 output inactive to active transition */

+#define HRTIM_CAPTURETRIGGER_TB1_RESET    (HRTIM_CPT1CR_TB1RST)    /*!< Capture is triggered by TB1 output active to inactive transition */

+#define HRTIM_CAPTURETRIGGER_TIMERB_CMP1  (HRTIM_CPT1CR_TIMBCMP1)  /*!< Timer B Compare 1 triggers Capture */

+#define HRTIM_CAPTURETRIGGER_TIMERB_CMP2  (HRTIM_CPT1CR_TIMBCMP2)  /*!< Timer B Compare 2 triggers Capture */

+#define HRTIM_CAPTURETRIGGER_TC1_SET      (HRTIM_CPT1CR_TC1SET)    /*!< Capture is triggered by TC1 output inactive to active transition */

+#define HRTIM_CAPTURETRIGGER_TC1_RESET    (HRTIM_CPT1CR_TC1RST)    /*!< Capture is triggered by TC1 output active to inactive transition */

+#define HRTIM_CAPTURETRIGGER_TIMERC_CMP1  (HRTIM_CPT1CR_TIMCCMP1)  /*!< Timer C Compare 1 triggers Capture */

+#define HRTIM_CAPTURETRIGGER_TIMERC_CMP2  (HRTIM_CPT1CR_TIMCCMP2)  /*!< Timer C Compare 2 triggers Capture */

+#define HRTIM_CAPTURETRIGGER_TD1_SET      (HRTIM_CPT1CR_TD1SET)    /*!< Capture is triggered by TD1 output inactive to active transition */

+#define HRTIM_CAPTURETRIGGER_TD1_RESET    (HRTIM_CPT1CR_TD1RST)    /*!< Capture is triggered by TD1 output active to inactive transition */

+#define HRTIM_CAPTURETRIGGER_TIMERD_CMP1  (HRTIM_CPT1CR_TIMDCMP1)  /*!< Timer D Compare 1 triggers Capture */

+#define HRTIM_CAPTURETRIGGER_TIMERD_CMP2  (HRTIM_CPT1CR_TIMDCMP2)  /*!< Timer D Compare 2 triggers Capture */

+#define HRTIM_CAPTURETRIGGER_TE1_SET      (HRTIM_CPT1CR_TE1SET)    /*!< Capture is triggered by TE1 output inactive to active transition */

+#define HRTIM_CAPTURETRIGGER_TE1_RESET    (HRTIM_CPT1CR_TE1RST)    /*!< Capture is triggered by TE1 output active to inactive transition */

+#define HRTIM_CAPTURETRIGGER_TIMERE_CMP1  (HRTIM_CPT1CR_TIMECMP1)  /*!< Timer E Compare 1 triggers Capture */

+#define HRTIM_CAPTURETRIGGER_TIMERE_CMP2  (HRTIM_CPT1CR_TIMECMP2)  /*!< Timer E Compare 2 triggers Capture */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Timer_External_Event_Filter HRTIM Timer External Event Filter

+  * @{

+  * @brief Constants defining the event filtering applied to external events

+  *        by a timer

+  */

+#define HRTIM_TIMEVENTFILTER_NONE             (0x00000000U)

+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1     (HRTIM_EEFR1_EE1FLTR_0)                                                                                                                           /*!< Blanking from counter reset/roll-over to Compare 1U */

+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2     (HRTIM_EEFR1_EE1FLTR_1)                                                                                                                           /*!< Blanking from counter reset/roll-over to Compare 2U */

+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3     (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                                                                                                   /*!< Blanking from counter reset/roll-over to Compare 3U */

+#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4     (HRTIM_EEFR1_EE1FLTR_2)                                                                                                                           /*!< Blanking from counter reset/roll-over to Compare 4U */

+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                                                                                                   /*!< Blanking from another timing unit: TIMFLTR1 source */

+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                                                                                                   /*!< Blanking from another timing unit: TIMFLTR2 source */

+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                                                                           /*!< Blanking from another timing unit: TIMFLTR3 source */

+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4    (HRTIM_EEFR1_EE1FLTR_3)                                                                                                                           /*!< Blanking from another timing unit: TIMFLTR4 source */

+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                                                                                                   /*!< Blanking from another timing unit: TIMFLTR5 source */

+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                                                                                                   /*!< Blanking from another timing unit: TIMFLTR6 source */

+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                                                                           /*!< Blanking from another timing unit: TIMFLTR7 source */

+#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                                                                                                   /*!< Blanking from another timing unit: TIMFLTR8 source */

+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                                                                           /*!< Windowing from counter reset/roll-over to Compare 2U */

+#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                                                                           /*!< Windowing from counter reset/roll-over to Compare 3U */

+#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM     (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)  /*!< Windowing from another timing unit: TIMWIN source */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Timer_External_Event_Latch HRTIM Timer External Event Latch

+  * @{

+  * @brief Constants defining whether or not the external event is

+  *        memorized (latched) and generated as soon as the blanking period

+  *        is completed or the window ends

+  */

+#define HRTIM_TIMEVENTLATCH_DISABLED    (0x00000000U)           /*!< Event is ignored if it happens during a blank, or passed through during a window */

+#define HRTIM_TIMEVENTLATCH_ENABLED     HRTIM_EEFR1_EE1LTCH     /*!< Event is latched and delayed till the end of the blanking or windowing period */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Deadtime_Prescaler_Ratio HRTIM Dead-time Prescaler Ratio

+  * @{

+  * @brief Constants defining division ratio between the timer clock frequency

+  *        (fHRTIM) and the dead-time generator clock (fDTG)

+  */

+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8    (0x00000000U)                                                   /*!< fDTG = fHRTIM * 8U */

+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4    (HRTIM_DTR_DTPRSC_0)                                            /*!< fDTG = fHRTIM * 4U */

+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2    (HRTIM_DTR_DTPRSC_1)                                            /*!< fDTG = fHRTIM * 2U */

+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1    (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0)                       /*!< fDTG = fHRTIM */

+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2    (HRTIM_DTR_DTPRSC_2)                                            /*!< fDTG = fHRTIM / 2U */

+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4    (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0)                       /*!< fDTG = fHRTIM / 4U */

+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8    (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1)                       /*!< fDTG = fHRTIM / 8U */

+#define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16   (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0)  /*!< fDTG = fHRTIM / 16U */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Deadtime_Rising_Sign HRTIM Dead-time Rising Sign

+  * @{

+  * @brief Constants defining whether the dead-time is positive or negative

+  *        (overlapping signal) on rising edge

+  */

+#define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE    (0x00000000U)           /*!< Positive dead-time on rising edge */

+#define HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE    (HRTIM_DTR_SDTR)        /*!< Negative dead-time on rising edge */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Deadtime_Rising_Lock HRTIM Dead-time Rising Lock

+  * @{

+  * @brief Constants defining whether or not the dead-time (rising sign and

+  *        value) is write protected

+  */

+#define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE    (0x00000000U)           /*!< Dead-time rising value and sign is writeable */

+#define HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK)       /*!< Dead-time rising value and sign is read-only */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Deadtime_Rising_Sign_Lock HRTIM Dead-time Rising Sign Lock

+  * @{

+  * @brief Constants defining whether or not the dead-time rising sign is write

+  *        protected

+  */

+#define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE    (0x00000000U)           /*!< Dead-time rising sign is writeable */

+#define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK)      /*!< Dead-time rising sign is read-only */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Deadtime_Falling_Sign HRTIM Dead-time Falling Sign

+  * @{

+  * @brief Constants defining whether the dead-time is positive or negative

+  *        (overlapping signal) on falling edge

+  */

+#define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE    (0x00000000U)           /*!< Positive dead-time on falling edge */

+#define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE    (HRTIM_DTR_SDTF)        /*!< Negative dead-time on falling edge */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Deadtime_Falling_Lock HRTIM Dead-time Falling Lock

+  * @{

+  * @brief Constants defining whether or not the dead-time (falling sign and

+  *        value) is write protected

+  */

+#define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE    (0x00000000U)           /*!< Dead-time falling value and sign is writeable */

+#define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK)       /*!< Dead-time falling value and sign is read-only */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Deadtime_Falling_Sign_Lock HRTIM Dead-time Falling Sign Lock

+  * @{

+  * @brief Constants defining whether or not the dead-time falling sign is write

+  *        protected

+  */

+#define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE    (0x00000000U)           /*!< Dead-time falling sign is writeable */

+#define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK)      /*!< Dead-time falling sign is read-only */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Chopper_Frequency HRTIM Chopper Frequency

+  * @{

+  * @brief Constants defining the frequency of the generated high frequency carrier

+  */

+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV16  (0x000000U)                                                                     /*!< fCHPFRQ = fHRTIM / 16  */

+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV32  (HRTIM_CHPR_CARFRQ_0)                                                                    /*!< fCHPFRQ = fHRTIM / 32  */

+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV48  (HRTIM_CHPR_CARFRQ_1)                                                                    /*!< fCHPFRQ = fHRTIM / 48  */

+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV64  (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 64  */

+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV80  (HRTIM_CHPR_CARFRQ_2)                                                                    /*!< fCHPFRQ = fHRTIM / 80  */

+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV96  (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 96  */

+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1)                                              /*!< fCHPFRQ = fHRTIM / 112  */

+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 128  */

+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV144 (HRTIM_CHPR_CARFRQ_3)                                                                    /*!< fCHPFRQ = fHRTIM / 144  */

+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 160  */

+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1)                                              /*!< fCHPFRQ = fHRTIM / 176  */

+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 192  */

+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2)                                              /*!< fCHPFRQ = fHRTIM / 208  */

+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 224  */

+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1)                        /*!< fCHPFRQ = fHRTIM / 240  */

+#define HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)  /*!< fCHPFRQ = fHRTIM / 256  */

+ /**

+  * @}

+  */

+

+/** @defgroup HRTIM_Chopper_Duty_Cycle HRTIM Chopper Duty Cycle

+  * @{

+  * @brief Constants defining the duty cycle of the generated high frequency carrier

+  *        Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)

+  */

+#define HRTIM_CHOPPER_DUTYCYCLE_0    (0x000000U)                                                       /*!< Only 1st pulse is present */

+#define HRTIM_CHOPPER_DUTYCYCLE_125  (HRTIM_CHPR_CARDTY_0)                                             /*!< Duty cycle of the carrier signal is 12.5U % */

+#define HRTIM_CHOPPER_DUTYCYCLE_250  (HRTIM_CHPR_CARDTY_1)                                             /*!< Duty cycle of the carrier signal is 25U % */

+#define HRTIM_CHOPPER_DUTYCYCLE_375  (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0)                       /*!< Duty cycle of the carrier signal is 37.5U % */

+#define HRTIM_CHOPPER_DUTYCYCLE_500  (HRTIM_CHPR_CARDTY_2)                                             /*!< Duty cycle of the carrier signal is 50U % */

+#define HRTIM_CHOPPER_DUTYCYCLE_625  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0)                       /*!< Duty cycle of the carrier signal is 62.5U % */

+#define HRTIM_CHOPPER_DUTYCYCLE_750  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1)                       /*!< Duty cycle of the carrier signal is 75U % */

+#define HRTIM_CHOPPER_DUTYCYCLE_875  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5U % */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Chopper_Start_Pulse_Width HRTIM Chopper Start Pulse Width

+  * @{

+  * @brief Constants defining the pulse width of the first pulse of the generated

+  *        high frequency carrier

+  */

+#define HRTIM_CHOPPER_PULSEWIDTH_16   (0x000000U)                                                                          /*!< tSTPW = tHRTIM x 16  */

+#define HRTIM_CHOPPER_PULSEWIDTH_32   (HRTIM_CHPR_STRPW_0)                                                                 /*!< tSTPW = tHRTIM x 32  */

+#define HRTIM_CHOPPER_PULSEWIDTH_48   (HRTIM_CHPR_STRPW_1)                                                                 /*!< tSTPW = tHRTIM x 48  */

+#define HRTIM_CHOPPER_PULSEWIDTH_64   (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 64  */

+#define HRTIM_CHOPPER_PULSEWIDTH_80   (HRTIM_CHPR_STRPW_2)                                                                 /*!< tSTPW = tHRTIM x 80  */

+#define HRTIM_CHOPPER_PULSEWIDTH_96   (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 96  */

+#define HRTIM_CHOPPER_PULSEWIDTH_112  (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1)                                            /*!< tSTPW = tHRTIM x 112  */

+#define HRTIM_CHOPPER_PULSEWIDTH_128  (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 128  */

+#define HRTIM_CHOPPER_PULSEWIDTH_144  (HRTIM_CHPR_STRPW_3)                                                                 /*!< tSTPW = tHRTIM x 144  */

+#define HRTIM_CHOPPER_PULSEWIDTH_160  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 160  */

+#define HRTIM_CHOPPER_PULSEWIDTH_176  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1)                                            /*!< tSTPW = tHRTIM x 176  */

+#define HRTIM_CHOPPER_PULSEWIDTH_192  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 192  */

+#define HRTIM_CHOPPER_PULSEWIDTH_208  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2)                                            /*!< tSTPW = tHRTIM x 208  */

+#define HRTIM_CHOPPER_PULSEWIDTH_224  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 224  */

+#define HRTIM_CHOPPER_PULSEWIDTH_240  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1)                       /*!< tSTPW = tHRTIM x 240  */

+#define HRTIM_CHOPPER_PULSEWIDTH_256  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)  /*!< tSTPW = tHRTIM x 256  */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Synchronization_Options HRTIM Synchronization Options

+  * @{

+  * @brief Constants defining the options for synchronizing multiple HRTIM

+  *        instances, as a master unit (generating a synchronization signal)

+  *        or as a slave (waiting for a trigger to be synchronized)

+  */

+#define HRTIM_SYNCOPTION_NONE   0x00000000U   /*!< HRTIM instance doesn't handle external synchronization signals (SYNCIN, SYNCOUT) */

+#define HRTIM_SYNCOPTION_MASTER 0x00000001U   /*!< HRTIM instance acts as a MASTER, i.e. generates external synchronization output (SYNCOUT)*/

+#define HRTIM_SYNCOPTION_SLAVE  0x00000002U   /*!< HRTIM instance acts as a SLAVE, i.e. it is synchronized by external sources (SYNCIN) */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Synchronization_Input_Source HRTIM Synchronization Input Source

+  * @{

+  * @brief Constants defining defining the synchronization input source

+  */

+#define HRTIM_SYNCINPUTSOURCE_NONE           0x00000000U                                  /*!< disabled. HRTIM is not synchronized and runs in standalone mode */

+#define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT  HRTIM_MCR_SYNC_IN_1                          /*!< The HRTIM is synchronized with the on-chip timer */

+#define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT  (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0)  /*!< A positive pulse on SYNCIN input triggers the HRTIM */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Synchronization_Output_Source HRTIM Synchronization Output Source

+  * @{

+  * @brief Constants defining the source and event to be sent on the

+  *        synchronization outputs

+  */

+#define HRTIM_SYNCOUTPUTSOURCE_MASTER_START 0x00000000U                                    /*!< A pulse is sent on the SYNCOUT output upon master timer start event */

+#define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1  (HRTIM_MCR_SYNC_SRC_0)                         /*!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event*/

+#define HRTIM_SYNCOUTPUTSOURCE_TIMA_START   (HRTIM_MCR_SYNC_SRC_1)                         /*!< A pulse is sent on the SYNCOUT output upon timer A start or reset events */

+#define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1    (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0)  /*!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Synchronization_Output_Polarity HRTIM Synchronization Output Polarity

+  * @{

+  * @brief Constants defining the routing and conditioning of the synchronization output event

+  */

+#define HRTIM_SYNCOUTPUTPOLARITY_NONE      0x00000000U                                   /*!< Synchronization output event is disabled */

+#define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE  (HRTIM_MCR_SYNC_OUT_1)                        /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */

+#define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE  (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_External_Event_Sources HRTIM External Event Sources

+  * @{

+  * @brief Constants defining available sources associated to external events

+  */

+#define HRTIM_EVENTSRC_1         (0x00000000U)                                  /*!< External event source 1U */

+#define HRTIM_EVENTSRC_2         (HRTIM_EECR1_EE1SRC_0)                         /*!< External event source 2U */

+#define HRTIM_EVENTSRC_3         (HRTIM_EECR1_EE1SRC_1)                         /*!< External event source 3U */

+#define HRTIM_EVENTSRC_4         (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)  /*!< External event source 4U */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_External_Event_Polarity HRTIM External Event Polarity

+  * @{

+  * @brief Constants defining the polarity of an external event

+  */

+#define HRTIM_EVENTPOLARITY_HIGH    (0x00000000U)           /*!< External event is active high */

+#define HRTIM_EVENTPOLARITY_LOW     (HRTIM_EECR1_EE1POL)    /*!< External event is active low */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_External_Event_Sensitivity HRTIM External Event Sensitivity

+  * @{

+  * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive)

+  *        of an external event

+  */

+#define HRTIM_EVENTSENSITIVITY_LEVEL          (0x00000000U)                                  /*!< External event is active on level */

+#define HRTIM_EVENTSENSITIVITY_RISINGEDGE     (HRTIM_EECR1_EE1SNS_0)                         /*!< External event is active on Rising edge */

+#define HRTIM_EVENTSENSITIVITY_FALLINGEDGE    (HRTIM_EECR1_EE1SNS_1)                         /*!< External event is active on Falling edge */

+#define HRTIM_EVENTSENSITIVITY_BOTHEDGES      (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0)  /*!< External event is active on Rising and Falling edges */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_External_Event_Fast_Mode HRTIM External Event Fast Mode

+  * @{

+  * @brief Constants defining whether or not an external event is programmed in

+           fast mode

+  */

+#define HRTIM_EVENTFASTMODE_DISABLE    (0x00000000U)               /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */

+#define HRTIM_EVENTFASTMODE_ENABLE     (HRTIM_EECR1_EE1FAST)       /*!< External Event is acting asynchronously on outputs (low latency mode) */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_External_Event_Filter HRTIM External Event Filter

+  * @{

+  * @brief Constants defining the frequency used to sample an external event 6

+  *        input and the length (N) of the digital filter applied

+  */

+#define HRTIM_EVENTFILTER_NONE      (0x00000000U)                                                                         /*!< Filter disabled */

+#define HRTIM_EVENTFILTER_1         (HRTIM_EECR3_EE6F_0)                                                                  /*!< fSAMPLING= fHRTIM, N=2U */

+#define HRTIM_EVENTFILTER_2         (HRTIM_EECR3_EE6F_1)                                                                  /*!< fSAMPLING= fHRTIM, N=4U */

+#define HRTIM_EVENTFILTER_3         (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING= fHRTIM, N=8U */

+#define HRTIM_EVENTFILTER_4         (HRTIM_EECR3_EE6F_2)                                                                  /*!< fSAMPLING= fEEVS/2U, N=6U */

+#define HRTIM_EVENTFILTER_5         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING= fEEVS/2U, N=8U */

+#define HRTIM_EVENTFILTER_6         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1)                                             /*!< fSAMPLING= fEEVS/4U, N=6U */

+#define HRTIM_EVENTFILTER_7         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                        /*!< fSAMPLING= fEEVS/4U, N=8U */

+#define HRTIM_EVENTFILTER_8         (HRTIM_EECR3_EE6F_3)                                                                  /*!< fSAMPLING= fEEVS/8U, N=6U */

+#define HRTIM_EVENTFILTER_9         (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING= fEEVS/8U, N=8U */

+#define HRTIM_EVENTFILTER_10        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1)                                             /*!< fSAMPLING= fEEVS/16U, N=5U */

+#define HRTIM_EVENTFILTER_11        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                        /*!< fSAMPLING= fEEVS/16U, N=6U */

+#define HRTIM_EVENTFILTER_12        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2)                                             /*!< fSAMPLING= fEEVS/16U, N=8U */

+#define HRTIM_EVENTFILTER_13        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_0)                       /*!< fSAMPLING= fEEVS/32U, N=5U */

+#define HRTIM_EVENTFILTER_14        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_1)                       /*!< fSAMPLING= fEEVS/32U, N=6U */

+#define HRTIM_EVENTFILTER_15        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)  /*!< fSAMPLING= fEEVS/32U, N=8U */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_External_Event_Prescaler HRTIM External Event Prescaler

+  * @{

+  * @brief Constants defining division ratio between the timer clock frequency

+  *        fHRTIM) and the external event signal sampling clock (fEEVS)

+  *        used by the digital filters

+  */

+#define HRTIM_EVENTPRESCALER_DIV1    (0x00000000U)                                   /*!< fEEVS=fHRTIM */

+#define HRTIM_EVENTPRESCALER_DIV2    (HRTIM_EECR3_EEVSD_0)                           /*!< fEEVS=fHRTIM / 2U */

+#define HRTIM_EVENTPRESCALER_DIV4    (HRTIM_EECR3_EEVSD_1)                           /*!< fEEVS=fHRTIM / 4U */

+#define HRTIM_EVENTPRESCALER_DIV8    (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0)     /*!< fEEVS=fHRTIM / 8U */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Fault_Sources HRTIM Fault Sources

+  * @{

+  * @brief Constants defining whether a fault is triggered by any external

+  *        or internal fault source

+  */

+#define HRTIM_FAULTSOURCE_DIGITALINPUT      (0x00000000U)              /*!< Fault input is FLT input pin */

+#define HRTIM_FAULTSOURCE_INTERNAL          (HRTIM_FLTINR1_FLT1SRC)    /*!< Fault input is FLT_Int signal (e.g. internal comparator) */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Fault_Polarity HRTIM Fault Polarity

+  * @{

+  * @brief Constants defining the polarity of a fault event

+  */

+#define HRTIM_FAULTPOLARITY_LOW     (0x00000000U)            /*!< Fault input is active low */

+#define HRTIM_FAULTPOLARITY_HIGH    (HRTIM_FLTINR1_FLT1P)    /*!< Fault input is active high */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Fault_Filter HRTIM Fault Filter

+  * @{

+  * @ brief Constants defining the frequency used to sample the fault input and

+  *         the length (N) of the digital filter applied

+  */

+#define HRTIM_FAULTFILTER_NONE      (0x00000000U)                                                                                    /*!< Filter disabled */

+#define HRTIM_FAULTFILTER_1         (HRTIM_FLTINR1_FLT1F_0)                                                                          /*!< fSAMPLING= fHRTIM, N=2U */

+#define HRTIM_FAULTFILTER_2         (HRTIM_FLTINR1_FLT1F_1)                                                                          /*!< fSAMPLING= fHRTIM, N=4U */

+#define HRTIM_FAULTFILTER_3         (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fHRTIM, N=8U */

+#define HRTIM_FAULTFILTER_4         (HRTIM_FLTINR1_FLT1F_2)                                                                          /*!< fSAMPLING= fFLTS/2U, N=6U */

+#define HRTIM_FAULTFILTER_5         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fFLTS/2U, N=8U */

+#define HRTIM_FAULTFILTER_6         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)                                                  /*!< fSAMPLING= fFLTS/4U, N=6U */

+#define HRTIM_FAULTFILTER_7         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/4U, N=8U */

+#define HRTIM_FAULTFILTER_8         (HRTIM_FLTINR1_FLT1F_3)                                                                          /*!< fSAMPLING= fFLTS/8U, N=6U */

+#define HRTIM_FAULTFILTER_9         (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fFLTS/8U, N=8U */

+#define HRTIM_FAULTFILTER_10        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1)                                                  /*!< fSAMPLING= fFLTS/16U, N=5U */

+#define HRTIM_FAULTFILTER_11        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/16U, N=6U */

+#define HRTIM_FAULTFILTER_12        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2)                                                  /*!< fSAMPLING= fFLTS/16U, N=8U */

+#define HRTIM_FAULTFILTER_13        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/32U, N=5U */

+#define HRTIM_FAULTFILTER_14        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)                          /*!< fSAMPLING= fFLTS/32U, N=6U */

+#define HRTIM_FAULTFILTER_15        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)  /*!< fSAMPLING= fFLTS/32U, N=8U */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Fault_Lock HRTIM Fault Lock

+  * @{

+  * @brief Constants defining whether or not the fault programming bits are

+           write protected

+  */

+#define HRTIM_FAULTLOCK_READWRITE       (0x00000000U)               /*!< Fault settings bits are read/write */

+#define HRTIM_FAULTLOCK_READONLY        (HRTIM_FLTINR1_FLT1LCK)     /*!< Fault settings bits are read only */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_External_Fault_Prescaler HRTIM External Fault Prescaler

+  * @{

+  * @brief Constants defining the division ratio between the timer clock

+  *        frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used

+  *        by the digital filters.

+  */

+#define HRTIM_FAULTPRESCALER_DIV1    (0x00000000U)                                     /*!< fFLTS=fHRTIM */

+#define HRTIM_FAULTPRESCALER_DIV2    (HRTIM_FLTINR2_FLTSD_0)                           /*!< fFLTS=fHRTIM / 2U */

+#define HRTIM_FAULTPRESCALER_DIV4    (HRTIM_FLTINR2_FLTSD_1)                           /*!< fFLTS=fHRTIM / 4U */

+#define HRTIM_FAULTPRESCALER_DIV8    (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0)   /*!< fFLTS=fHRTIM / 8U */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Burst_Mode_Operating_Mode HRTIM Burst Mode Operating Mode

+  * @{

+  * @brief Constants defining if the burst mode is entered once or if it is

+  *        continuously operating

+  */

+#define HRTIM_BURSTMODE_SINGLESHOT (0x00000000U)           /*!< Burst mode operates in single shot mode */

+#define HRTIM_BURSTMODE_CONTINOUS   (HRTIM_BMCR_BMOM)      /*!< Burst mode operates in continuous mode */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Burst_Mode_Clock_Source HRTIM Burst Mode Clock Source

+  * @{

+  * @brief Constants defining the clock source for the burst mode counter

+  */

+#define HRTIM_BURSTMODECLOCKSOURCE_MASTER     (0x00000000U)                                                   /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */

+#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_A    (HRTIM_BMCR_BMCLK_0)                                            /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */

+#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_B    (HRTIM_BMCR_BMCLK_1)                                            /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */

+#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_C    (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)                       /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */

+#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_D    (HRTIM_BMCR_BMCLK_2)                                            /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */

+#define HRTIM_BURSTMODECLOCKSOURCE_TIMER_E    (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0)                       /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */

+#define HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC   (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1)                       /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */

+#define HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC   (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)  /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */

+#define HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO  (HRTIM_BMCR_BMCLK_3)                                            /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */

+#define HRTIM_BURSTMODECLOCKSOURCE_FHRTIM     (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1)                       /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Burst_Mode_Prescaler HRTIM Burst Mode Prescaler

+  * @{

+  * @brief Constants defining the prescaling ratio of the fHRTIM clock

+  *        for the burst mode controller

+  */

+#define HRTIM_BURSTMODEPRESCALER_DIV1     (0x00000000U)                                                                           /*!< fBRST = fHRTIM */

+#define HRTIM_BURSTMODEPRESCALER_DIV2     (HRTIM_BMCR_BMPRSC_0)                                                                   /*!< fBRST = fHRTIM/2U */

+#define HRTIM_BURSTMODEPRESCALER_DIV4     (HRTIM_BMCR_BMPRSC_1)                                                                   /*!< fBRST = fHRTIM/4U */

+#define HRTIM_BURSTMODEPRESCALER_DIV8     (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/8U */

+#define HRTIM_BURSTMODEPRESCALER_DIV16    (HRTIM_BMCR_BMPRSC_2)                                                                   /*!< fBRST = fHRTIM/16U */

+#define HRTIM_BURSTMODEPRESCALER_DIV32    (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/32U */

+#define HRTIM_BURSTMODEPRESCALER_DIV64    (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1)                                             /*!< fBRST = fHRTIM/64U */

+#define HRTIM_BURSTMODEPRESCALER_DIV128   (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/128U */

+#define HRTIM_BURSTMODEPRESCALER_DIV256   (HRTIM_BMCR_BMPRSC_3)                                                                   /*!< fBRST = fHRTIM/256U */

+#define HRTIM_BURSTMODEPRESCALER_DIV512   (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/512U */

+#define HRTIM_BURSTMODEPRESCALER_DIV1024  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1)                                             /*!< fBRST = fHRTIM/1024U */

+#define HRTIM_BURSTMODEPRESCALER_DIV2048  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/2048U*/

+#define HRTIM_BURSTMODEPRESCALER_DIV4096  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2)                                             /*!< fBRST = fHRTIM/4096U */

+#define HRTIM_BURSTMODEPRESCALER_DIV8192  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/8192U */

+#define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1)                       /*!< fBRST = fHRTIM/16384U */

+#define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768U */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Burst_Mode_Register_Preload_Enable HRTIM Burst Mode Register Preload Enable

+  * @{

+  * @brief Constants defining whether or not burst mode registers preload

+           mechanism is enabled, i.e. a write access into a preloadable register

+          (HRTIM_BMCMPR, HRTIM_BMPER) is done into the active or the preload register

+  */

+#define HRIM_BURSTMODEPRELOAD_DISABLED (0x00000000U)  /*!< Preload disabled: the write access is directly done into active registers */

+#define HRIM_BURSTMODEPRELOAD_ENABLED  (HRTIM_BMCR_BMPREN)     /*!< Preload enabled: the write access is done into preload registers */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Burst_Mode_Trigger HRTIM Burst Mode Trigger

+  * @{

+  * @brief Constants defining the events that can be used to trig the burst

+  *        mode operation

+  */

+#define HRTIM_BURSTMODETRIGGER_NONE               0x00000000U             /*!<  No trigger */

+#define HRTIM_BURSTMODETRIGGER_MASTER_RESET       (HRTIM_BMTRGR_MSTRST)   /*!<  Master reset */

+#define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION  (HRTIM_BMTRGR_MSTREP)   /*!<  Master repetition */

+#define HRTIM_BURSTMODETRIGGER_MASTER_CMP1        (HRTIM_BMTRGR_MSTCMP1)  /*!<  Master compare 1U */

+#define HRTIM_BURSTMODETRIGGER_MASTER_CMP2        (HRTIM_BMTRGR_MSTCMP2)  /*!<  Master compare 2U */

+#define HRTIM_BURSTMODETRIGGER_MASTER_CMP3        (HRTIM_BMTRGR_MSTCMP3)  /*!<  Master compare 3U */

+#define HRTIM_BURSTMODETRIGGER_MASTER_CMP4        (HRTIM_BMTRGR_MSTCMP4)  /*!<  Master compare 4U */

+#define HRTIM_BURSTMODETRIGGER_TIMERA_RESET       (HRTIM_BMTRGR_TARST)    /*!< Timer A reset  */

+#define HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION  (HRTIM_BMTRGR_TAREP)    /*!< Timer A repetition  */

+#define HRTIM_BURSTMODETRIGGER_TIMERA_CMP1        (HRTIM_BMTRGR_TACMP1)   /*!< Timer A compare 1  */

+#define HRTIM_BURSTMODETRIGGER_TIMERA_CMP2        (HRTIM_BMTRGR_TACMP2)   /*!< Timer A compare 2  */

+#define HRTIM_BURSTMODETRIGGER_TIMERB_RESET       (HRTIM_BMTRGR_TBRST)    /*!< Timer B reset  */

+#define HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION  (HRTIM_BMTRGR_TBREP)    /*!< Timer B repetition  */

+#define HRTIM_BURSTMODETRIGGER_TIMERB_CMP1        (HRTIM_BMTRGR_TBCMP1)   /*!< Timer B compare 1  */

+#define HRTIM_BURSTMODETRIGGER_TIMERB_CMP2        (HRTIM_BMTRGR_TBCMP2)   /*!< Timer B compare 2  */

+#define HRTIM_BURSTMODETRIGGER_TIMERC_RESET       (HRTIM_BMTRGR_TCRST)    /*!< Timer C reset  */

+#define HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION  (HRTIM_BMTRGR_TCREP)    /*!< Timer C repetition  */

+#define HRTIM_BURSTMODETRIGGER_TIMERC_CMP1        (HRTIM_BMTRGR_TCCMP1)   /*!< Timer C compare 1  */

+#define HRTIM_BURSTMODETRIGGER_TIMERC_CMP2        (HRTIM_BMTRGR_TCCMP2)   /*!< Timer C compare 2  */

+#define HRTIM_BURSTMODETRIGGER_TIMERD_RESET       (HRTIM_BMTRGR_TDRST)    /*!< Timer D reset  */

+#define HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION  (HRTIM_BMTRGR_TDREP)    /*!< Timer D repetition  */

+#define HRTIM_BURSTMODETRIGGER_TIMERD_CMP1        (HRTIM_BMTRGR_TDCMP1)   /*!< Timer D compare 1  */

+#define HRTIM_BURSTMODETRIGGER_TIMERD_CMP2        (HRTIM_BMTRGR_TDCMP2)   /*!< Timer D compare 2  */

+#define HRTIM_BURSTMODETRIGGER_TIMERE_RESET       (HRTIM_BMTRGR_TERST)    /*!< Timer E reset  */

+#define HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION  (HRTIM_BMTRGR_TEREP)    /*!< Timer E repetition  */

+#define HRTIM_BURSTMODETRIGGER_TIMERE_CMP1        (HRTIM_BMTRGR_TECMP1)   /*!< Timer E compare 1  */

+#define HRTIM_BURSTMODETRIGGER_TIMERE_CMP2        (HRTIM_BMTRGR_TECMP2)   /*!< Timer E compare 2  */

+#define HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7      (HRTIM_BMTRGR_TAEEV7)   /*!< Timer A period following External Event 7  */

+#define HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8      (HRTIM_BMTRGR_TDEEV8)   /*!< Timer D period following External Event 8  */

+#define HRTIM_BURSTMODETRIGGER_EVENT_7            (HRTIM_BMTRGR_EEV7)     /*!< External Event 7 (timer A filters applied) */

+#define HRTIM_BURSTMODETRIGGER_EVENT_8            (HRTIM_BMTRGR_EEV8)     /*!< External Event 8 (timer D filters applied)*/

+#define HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP       (HRTIM_BMTRGR_OCHPEV)   /*!< On-chip Event */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_ADC_Trigger_Update_Source HRTIM ADC Trigger Update Source

+  * @{

+  * @brief constants defining the source triggering the update of the

+     HRTIM_ADCxR register (transfer from preload to active register).

+  */

+#define HRTIM_ADCTRIGGERUPDATE_MASTER  0x00000000U                                   /*!< Master timer */

+#define HRTIM_ADCTRIGGERUPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0)                        /*!< Timer A */

+#define HRTIM_ADCTRIGGERUPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1)                        /*!< Timer B */

+#define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< Timer C */

+#define HRTIM_ADCTRIGGERUPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2)                        /*!< Timer D */

+#define HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< Timer E */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_ADC_Trigger_Event HRTIM ADC Trigger Event

+  * @{

+  * @brief constants defining the events triggering ADC conversion.

+  *        HRTIM_ADCTRIGGEREVENT13_*: ADC Triggers 1 and 3

+  *        HRTIM_ADCTRIGGEREVENT24_*: ADC Triggers 2 and 4

+  */

+#define HRTIM_ADCTRIGGEREVENT13_NONE           0x00000000U              /*!< No ADC trigger event */

+#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1    (HRTIM_ADC1R_AD1MC1)     /*!< ADC Trigger on master compare 1U */

+#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2    (HRTIM_ADC1R_AD1MC2)     /*!< ADC Trigger on master compare 2U */

+#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3    (HRTIM_ADC1R_AD1MC3)     /*!< ADC Trigger on master compare 3U */

+#define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4    (HRTIM_ADC1R_AD1MC4)     /*!< ADC Trigger on master compare 4U */

+#define HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD  (HRTIM_ADC1R_AD1MPER)    /*!< ADC Trigger on master period */

+#define HRTIM_ADCTRIGGEREVENT13_EVENT_1        (HRTIM_ADC1R_AD1EEV1)    /*!< ADC Trigger on external event 1U */

+#define HRTIM_ADCTRIGGEREVENT13_EVENT_2        (HRTIM_ADC1R_AD1EEV2)    /*!< ADC Trigger on external event 2U */

+#define HRTIM_ADCTRIGGEREVENT13_EVENT_3        (HRTIM_ADC1R_AD1EEV3)    /*!< ADC Trigger on external event 3U */

+#define HRTIM_ADCTRIGGEREVENT13_EVENT_4        (HRTIM_ADC1R_AD1EEV4)    /*!< ADC Trigger on external event 4U */

+#define HRTIM_ADCTRIGGEREVENT13_EVENT_5        (HRTIM_ADC1R_AD1EEV5)    /*!< ADC Trigger on external event 5U */

+#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2    (HRTIM_ADC1R_AD1TAC2)    /*!< ADC Trigger on Timer A compare 2U */

+#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3    (HRTIM_ADC1R_AD1TAC3)    /*!< ADC Trigger on Timer A compare 3U */

+#define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4    (HRTIM_ADC1R_AD1TAC4)    /*!< ADC Trigger on Timer A compare 4U */

+#define HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD  (HRTIM_ADC1R_AD1TAPER)   /*!< ADC Trigger on Timer A period */

+#define HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET   (HRTIM_ADC1R_AD1TARST)   /*!< ADC Trigger on Timer A reset */

+#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2    (HRTIM_ADC1R_AD1TBC2)    /*!< ADC Trigger on Timer B compare 2U */

+#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3    (HRTIM_ADC1R_AD1TBC3)    /*!< ADC Trigger on Timer B compare 3U */

+#define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4    (HRTIM_ADC1R_AD1TBC4)    /*!< ADC Trigger on Timer B compare 4U */

+#define HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD  (HRTIM_ADC1R_AD1TBPER)   /*!< ADC Trigger on Timer B period */

+#define HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET   (HRTIM_ADC1R_AD1TBRST)   /*!< ADC Trigger on Timer B reset */

+#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2    (HRTIM_ADC1R_AD1TCC2)    /*!< ADC Trigger on Timer C compare 2U */

+#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3    (HRTIM_ADC1R_AD1TCC3)    /*!< ADC Trigger on Timer C compare 3U */

+#define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4    (HRTIM_ADC1R_AD1TCC4)    /*!< ADC Trigger on Timer C compare 4U */

+#define HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD  (HRTIM_ADC1R_AD1TCPER)   /*!< ADC Trigger on Timer C period */

+#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2    (HRTIM_ADC1R_AD1TDC2)    /*!< ADC Trigger on Timer D compare 2U */

+#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3    (HRTIM_ADC1R_AD1TDC3)    /*!< ADC Trigger on Timer D compare 3U */

+#define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4    (HRTIM_ADC1R_AD1TDC4)    /*!< ADC Trigger on Timer D compare 4U */

+#define HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD  (HRTIM_ADC1R_AD1TDPER)   /*!< ADC Trigger on Timer D period */

+#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2    (HRTIM_ADC1R_AD1TEC2)    /*!< ADC Trigger on Timer E compare 2U */

+#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3    (HRTIM_ADC1R_AD1TEC3)    /*!< ADC Trigger on Timer E compare 3U */

+#define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4    (HRTIM_ADC1R_AD1TEC4)    /*!< ADC Trigger on Timer E compare 4U */

+#define HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD  (HRTIM_ADC1R_AD1TEPER)   /*!< ADC Trigger on Timer E period */

+

+#define HRTIM_ADCTRIGGEREVENT24_NONE           0x00000000U               /*!< No ADC trigger event */

+#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1    (HRTIM_ADC2R_AD2MC1)     /*!< ADC Trigger on master compare 1U */

+#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2    (HRTIM_ADC2R_AD2MC2)     /*!< ADC Trigger on master compare 2U */

+#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3    (HRTIM_ADC2R_AD2MC3)     /*!< ADC Trigger on master compare 3U */

+#define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4    (HRTIM_ADC2R_AD2MC4)     /*!< ADC Trigger on master compare 4U */

+#define HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD  (HRTIM_ADC2R_AD2MPER)    /*!< ADC Trigger on master period */

+#define HRTIM_ADCTRIGGEREVENT24_EVENT_6        (HRTIM_ADC2R_AD2EEV6)    /*!< ADC Trigger on external event 6U */

+#define HRTIM_ADCTRIGGEREVENT24_EVENT_7        (HRTIM_ADC2R_AD2EEV7)    /*!< ADC Trigger on external event 7U */

+#define HRTIM_ADCTRIGGEREVENT24_EVENT_8        (HRTIM_ADC2R_AD2EEV8)    /*!< ADC Trigger on external event 8U */

+#define HRTIM_ADCTRIGGEREVENT24_EVENT_9        (HRTIM_ADC2R_AD2EEV9)    /*!< ADC Trigger on external event 9U */

+#define HRTIM_ADCTRIGGEREVENT24_EVENT_10       (HRTIM_ADC2R_AD2EEV10)   /*!< ADC Trigger on external event 10U */

+#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2    (HRTIM_ADC2R_AD2TAC2)    /*!< ADC Trigger on Timer A compare 2U */

+#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3    (HRTIM_ADC2R_AD2TAC3)    /*!< ADC Trigger on Timer A compare 3U */

+#define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4    (HRTIM_ADC2R_AD2TAC4)    /*!< ADC Trigger on Timer A compare 4U */

+#define HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD  (HRTIM_ADC2R_AD2TAPER)   /*!< ADC Trigger on Timer A period */

+#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2    (HRTIM_ADC2R_AD2TBC2)    /*!< ADC Trigger on Timer B compare 2U */

+#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3    (HRTIM_ADC2R_AD2TBC3)    /*!< ADC Trigger on Timer B compare 3U */

+#define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4    (HRTIM_ADC2R_AD2TBC4)    /*!< ADC Trigger on Timer B compare 4U */

+#define HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD  (HRTIM_ADC2R_AD2TBPER)   /*!< ADC Trigger on Timer B period */

+#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2    (HRTIM_ADC2R_AD2TCC2)    /*!< ADC Trigger on Timer C compare 2U */

+#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3    (HRTIM_ADC2R_AD2TCC3)    /*!< ADC Trigger on Timer C compare 3U */

+#define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4    (HRTIM_ADC2R_AD2TCC4)    /*!< ADC Trigger on Timer C compare 4U */

+#define HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD  (HRTIM_ADC2R_AD2TCPER)   /*!< ADC Trigger on Timer C period */

+#define HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET   (HRTIM_ADC2R_AD2TCRST)   /*!< ADC Trigger on Timer C reset */

+#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2    (HRTIM_ADC2R_AD2TDC2)    /*!< ADC Trigger on Timer D compare 2U */

+#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3    (HRTIM_ADC2R_AD2TDC3)    /*!< ADC Trigger on Timer D compare 3U */

+#define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4    (HRTIM_ADC2R_AD2TDC4)    /*!< ADC Trigger on Timer D compare 4U */

+#define HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD  (HRTIM_ADC2R_AD2TDPER)   /*!< ADC Trigger on Timer D period */

+#define HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET   (HRTIM_ADC2R_AD2TDRST)   /*!< ADC Trigger on Timer D reset */

+#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2    (HRTIM_ADC2R_AD2TEC2)    /*!< ADC Trigger on Timer E compare 2U */

+#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3    (HRTIM_ADC2R_AD2TEC3)    /*!< ADC Trigger on Timer E compare 3U */

+#define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4    (HRTIM_ADC2R_AD2TEC4)    /*!< ADC Trigger on Timer E compare 4U */

+#define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET   (HRTIM_ADC2R_AD2TERST)   /*!< ADC Trigger on Timer E reset */

+

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Burst_DMA_Registers_Update HRTIM Burst DMA Registers Update

+  * @{

+  * @brief Constants defining the registers that can be written during a burst

+  *        DMA operation

+  */

+#define HRTIM_BURSTDMA_NONE  0x00000000U               /*!< No register is updated by Burst DMA accesses */

+#define HRTIM_BURSTDMA_CR    (HRTIM_BDTUPR_TIMCR)      /*!< MCR or TIMxCR register is updated by Burst DMA accesses */

+#define HRTIM_BURSTDMA_ICR   (HRTIM_BDTUPR_TIMICR)     /*!< MICR or TIMxICR register is updated by Burst DMA accesses */

+#define HRTIM_BURSTDMA_DIER  (HRTIM_BDTUPR_TIMDIER)    /*!< MDIER or TIMxDIER register is updated by Burst DMA accesses */

+#define HRTIM_BURSTDMA_CNT   (HRTIM_BDTUPR_TIMCNT)     /*!< MCNTR or CNTxCR register is updated by Burst DMA accesses */

+#define HRTIM_BURSTDMA_PER   (HRTIM_BDTUPR_TIMPER)     /*!< MPER or PERxR register is updated by Burst DMA accesses */

+#define HRTIM_BURSTDMA_REP   (HRTIM_BDTUPR_TIMREP)     /*!< MREPR or REPxR register is updated by Burst DMA accesses */

+#define HRTIM_BURSTDMA_CMP1  (HRTIM_BDTUPR_TIMCMP1)    /*!< MCMP1R or CMP1xR register is updated by Burst DMA accesses */

+#define HRTIM_BURSTDMA_CMP2  (HRTIM_BDTUPR_TIMCMP2)    /*!< MCMP2R or CMP2xR register is updated by Burst DMA accesses */

+#define HRTIM_BURSTDMA_CMP3  (HRTIM_BDTUPR_TIMCMP3)    /*!< MCMP3R or CMP3xR register is updated by Burst DMA accesses */

+#define HRTIM_BURSTDMA_CMP4  (HRTIM_BDTUPR_TIMCMP4)    /*!< MCMP4R or CMP4xR register is updated by Burst DMA accesses */

+#define HRTIM_BURSTDMA_DTR   (HRTIM_BDTUPR_TIMDTR)     /*!< TDxR register is updated by Burst DMA accesses */

+#define HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R)   /*!< SET1R register is updated by Burst DMA accesses */

+#define HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R)   /*!< RST1R register is updated by Burst DMA accesses */

+#define HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R)   /*!< SET2R register is updated by Burst DMA accesses */

+#define HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R)   /*!< RST1R register is updated by Burst DMA accesses */

+#define HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1)   /*!< EEFxR1 register is updated by Burst DMA accesses */

+#define HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2)   /*!< EEFxR2 register is updated by Burst DMA accesses */

+#define HRTIM_BURSTDMA_RSTR  (HRTIM_BDTUPR_TIMRSTR)    /*!< RSTxR register is updated by Burst DMA accesses */

+#define HRTIM_BURSTDMA_CHPR  (HRTIM_BDTUPR_TIMCHPR)    /*!< CHPxR register is updated by Burst DMA accesses */

+#define HRTIM_BURSTDMA_OUTR  (HRTIM_BDTUPR_TIMOUTR)    /*!< OUTxR register is updated by Burst DMA accesses */

+#define HRTIM_BURSTDMA_FLTR  (HRTIM_BDTUPR_TIMFLTR)    /*!< FLTxR register is updated by Burst DMA accesses */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Burst_Mode_Control HRTIM Burst Mode Control

+  * @{

+  * @brief Constants used to enable or disable the burst mode controller

+  */

+#define HRTIM_BURSTMODECTL_DISABLED 0x00000000U          /*!< Burst mode disabled */

+#define HRTIM_BURSTMODECTL_ENABLED  (HRTIM_BMCR_BME)     /*!< Burst mode enabled */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Fault_Mode_Control  HRTIM Fault Mode Control

+  * @{

+  * @brief Constants used to enable or disable a fault channel

+  */

+#define HRTIM_FAULTMODECTL_DISABLED 0x00000000U /*!< Fault channel is disabled */

+#define HRTIM_FAULTMODECTL_ENABLED  0x00000001U /*!< Fault channel is  enabled */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Software_Timer_Update HRTIM Software Timer Update

+  * @{

+  * @brief Constants used to force timer registers update

+  */

+#define HRTIM_TIMERUPDATE_MASTER    (HRTIM_CR2_MSWU)     /*!< Force an immediate transfer from the preload to the active register in the master timer */

+#define HRTIM_TIMERUPDATE_A         (HRTIM_CR2_TASWU)    /*!< Force an immediate transfer from the preload to the active register in the timer A */

+#define HRTIM_TIMERUPDATE_B         (HRTIM_CR2_TBSWU)    /*!< Force an immediate transfer from the preload to the active register in the timer B */

+#define HRTIM_TIMERUPDATE_C         (HRTIM_CR2_TCSWU)    /*!< Force an immediate transfer from the preload to the active register in the timer C */

+#define HRTIM_TIMERUPDATE_D         (HRTIM_CR2_TDSWU)    /*!< Force an immediate transfer from the preload to the active register in the timer D */

+#define HRTIM_TIMERUPDATE_E         (HRTIM_CR2_TESWU)    /*!< Force an immediate transfer from the preload to the active register in the timer E */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Software_Timer_Reset HRTIM Software Timer Reset

+  * @{

+  * @brief Constants used to force timer counter reset

+  */

+#define HRTIM_TIMERRESET_MASTER    (HRTIM_CR2_MRST)     /*!< Reset the master timer counter */

+#define HRTIM_TIMERRESET_TIMER_A   (HRTIM_CR2_TARST)    /*!< Reset the timer A counter */

+#define HRTIM_TIMERRESET_TIMER_B   (HRTIM_CR2_TBRST)    /*!< Reset the timer B counter */

+#define HRTIM_TIMERRESET_TIMER_C   (HRTIM_CR2_TCRST)    /*!< Reset the timer C counter */

+#define HRTIM_TIMERRESET_TIMER_D   (HRTIM_CR2_TDRST)    /*!< Reset the timer D counter */

+#define HRTIM_TIMERRESET_TIMER_E   (HRTIM_CR2_TERST)    /*!< Reset the timer E counter */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Output_Level HRTIM Output Level

+  * @{

+  * @brief Constants defining the level of a timer output

+  */

+#define HRTIM_OUTPUTLEVEL_ACTIVE     (0x00000001U) /*!< Force the output to its active state */

+#define HRTIM_OUTPUTLEVEL_INACTIVE   (0x00000002U) /*!< Force the output to its inactive state */

+

+#define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\

+    (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE)  || \

+     ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE))

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Output_State HRTIM Output State

+  * @{

+  * @brief Constants defining the state of a timer output

+  */

+#define HRTIM_OUTPUTSTATE_IDLE     (0x00000001U)  /*!< Main operating mode, where the output can take the active or

+                                                              inactive level as programmed in the crossbar unit */

+#define HRTIM_OUTPUTSTATE_RUN      (0x00000002U)  /*!< Default operating state (e.g. after an HRTIM reset, when the

+                                                              outputs are disabled by software or during a burst mode operation */

+#define HRTIM_OUTPUTSTATE_FAULT    (0x00000003U)  /*!< Safety state, entered in case of a shut-down request on

+                                                              FAULTx inputs */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Burst_Mode_Status HRTIM Burst Mode Status

+  * @{

+  * @brief Constants defining the operating state of the burst mode controller

+  */

+#define HRTIM_BURSTMODESTATUS_NORMAL   0x00000000U          /*!< Normal operation */

+#define HRTIM_BURSTMODESTATUS_ONGOING (HRTIM_BMCR_BMSTAT)   /*!< Burst operation on-going */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Current_Push_Pull_Status HRTIM Current Push Pull Status

+  * @{

+  * @brief Constants defining on which output the signal is currently applied

+  *        in push-pull mode

+  */

+#define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1    0x00000000U            /*!< Signal applied on output 1 and output 2 forced inactive */

+#define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2   (HRTIM_TIMISR_CPPSTAT)  /*!< Signal applied on output 2 and output 1 forced inactive */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Idle_Push_Pull_Status HRTIM Idle Push Pull Status

+  * @{

+  * @brief Constants defining on which output the signal was applied, in

+  *        push-pull mode balanced fault mode or delayed idle mode, when the

+  *        protection was triggered

+  */

+#define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1    0x00000000U               /*!< Protection occurred when the output 1 was active and output 2 forced inactive */

+#define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2   (HRTIM_TIMISR_IPPSTAT)     /*!< Protection occurred when the output 2 was active and output 1 forced inactive */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Common_Interrupt_Enable HRTIM Common Interrupt Enable

+  * @{

+  */

+#define HRTIM_IT_NONE           0x00000000U           /*!< No interrupt enabled */

+#define HRTIM_IT_FLT1           HRTIM_IER_FLT1        /*!< Fault 1 interrupt enable */

+#define HRTIM_IT_FLT2           HRTIM_IER_FLT2        /*!< Fault 2 interrupt enable */

+#define HRTIM_IT_FLT3           HRTIM_IER_FLT3        /*!< Fault 3 interrupt enable */

+#define HRTIM_IT_FLT4           HRTIM_IER_FLT4        /*!< Fault 4 interrupt enable */

+#define HRTIM_IT_FLT5           HRTIM_IER_FLT5        /*!< Fault 5 interrupt enable */

+#define HRTIM_IT_SYSFLT         HRTIM_IER_SYSFLT      /*!< System Fault interrupt enable */

+#define HRTIM_IT_BMPER          HRTIM_IER_BMPER       /*!<  Burst mode period interrupt enable */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Master_Interrupt_Enable HRTIM Master Interrupt Enable

+  * @{

+  */

+#define HRTIM_MASTER_IT_NONE         0x00000000U           /*!< No interrupt enabled */

+#define HRTIM_MASTER_IT_MCMP1        HRTIM_MDIER_MCMP1IE   /*!< Master compare 1 interrupt enable */

+#define HRTIM_MASTER_IT_MCMP2        HRTIM_MDIER_MCMP2IE   /*!< Master compare 2 interrupt enable */

+#define HRTIM_MASTER_IT_MCMP3        HRTIM_MDIER_MCMP3IE   /*!< Master compare 3 interrupt enable */

+#define HRTIM_MASTER_IT_MCMP4        HRTIM_MDIER_MCMP4IE   /*!< Master compare 4 interrupt enable */

+#define HRTIM_MASTER_IT_MREP         HRTIM_MDIER_MREPIE    /*!< Master Repetition interrupt enable */

+#define HRTIM_MASTER_IT_SYNC         HRTIM_MDIER_SYNCIE    /*!< Synchronization input interrupt enable */

+#define HRTIM_MASTER_IT_MUPD         HRTIM_MDIER_MUPDIE    /*!< Master update interrupt enable */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Timing_Unit_Interrupt_Enable HRTIM Timing Unit Interrupt Enable

+  * @{

+  */

+#define HRTIM_TIM_IT_NONE       0x00000000U               /*!< No interrupt enabled */

+#define HRTIM_TIM_IT_CMP1       HRTIM_TIMDIER_CMP1IE      /*!< Timer compare 1 interrupt enable */

+#define HRTIM_TIM_IT_CMP2       HRTIM_TIMDIER_CMP2IE      /*!< Timer compare 2 interrupt enable */

+#define HRTIM_TIM_IT_CMP3       HRTIM_TIMDIER_CMP3IE      /*!< Timer compare 3 interrupt enable */

+#define HRTIM_TIM_IT_CMP4       HRTIM_TIMDIER_CMP4IE      /*!< Timer compare 4 interrupt enable */

+#define HRTIM_TIM_IT_REP        HRTIM_TIMDIER_REPIE       /*!< Timer repetition interrupt enable */

+#define HRTIM_TIM_IT_UPD        HRTIM_TIMDIER_UPDIE       /*!< Timer update interrupt enable */

+#define HRTIM_TIM_IT_CPT1       HRTIM_TIMDIER_CPT1IE      /*!< Timer capture 1 interrupt enable */

+#define HRTIM_TIM_IT_CPT2       HRTIM_TIMDIER_CPT2IE      /*!< Timer capture 2 interrupt enable */

+#define HRTIM_TIM_IT_SET1       HRTIM_TIMDIER_SET1IE      /*!< Timer output 1 set interrupt enable */

+#define HRTIM_TIM_IT_RST1       HRTIM_TIMDIER_RST1IE      /*!< Timer output 1 reset interrupt enable */

+#define HRTIM_TIM_IT_SET2       HRTIM_TIMDIER_SET2IE      /*!< Timer output 2 set interrupt enable */

+#define HRTIM_TIM_IT_RST2       HRTIM_TIMDIER_RST2IE      /*!< Timer output 2 reset interrupt enable */

+#define HRTIM_TIM_IT_RST        HRTIM_TIMDIER_RSTIE       /*!< Timer reset interrupt enable */

+#define HRTIM_TIM_IT_DLYPRT     HRTIM_TIMDIER_DLYPRTIE    /*!< Timer delay protection interrupt enable */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Common_Interrupt_Flag HRTIM Common Interrupt Flag

+  * @{

+  */

+#define HRTIM_FLAG_FLT1           HRTIM_ISR_FLT1    /*!< Fault 1 interrupt flag */

+#define HRTIM_FLAG_FLT2           HRTIM_ISR_FLT2    /*!< Fault 2 interrupt flag */

+#define HRTIM_FLAG_FLT3           HRTIM_ISR_FLT3    /*!< Fault 3 interrupt flag */

+#define HRTIM_FLAG_FLT4           HRTIM_ISR_FLT4    /*!< Fault 4 interrupt flag */

+#define HRTIM_FLAG_FLT5           HRTIM_ISR_FLT5    /*!< Fault 5 interrupt flag */

+#define HRTIM_FLAG_SYSFLT         HRTIM_ISR_SYSFLT  /*!< System Fault interrupt flag */

+#define HRTIM_FLAG_BMPER          HRTIM_ISR_BMPER   /*!< Burst mode period interrupt flag */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Master_Interrupt_Flag HRTIM Master Interrupt Flag

+  * @{

+  */

+#define HRTIM_MASTER_FLAG_MCMP1        HRTIM_MISR_MCMP1    /*!< Master compare 1 interrupt flag */

+#define HRTIM_MASTER_FLAG_MCMP2        HRTIM_MISR_MCMP2    /*!< Master compare 2 interrupt flag */

+#define HRTIM_MASTER_FLAG_MCMP3        HRTIM_MISR_MCMP3    /*!< Master compare 3 interrupt flag */

+#define HRTIM_MASTER_FLAG_MCMP4        HRTIM_MISR_MCMP4    /*!< Master compare 4 interrupt flag */

+#define HRTIM_MASTER_FLAG_MREP         HRTIM_MISR_MREP     /*!< Master Repetition interrupt flag */

+#define HRTIM_MASTER_FLAG_SYNC         HRTIM_MISR_SYNC     /*!< Synchronization input interrupt flag */

+#define HRTIM_MASTER_FLAG_MUPD         HRTIM_MISR_MUPD     /*!< Master update interrupt flag */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Timing_Unit_Interrupt_Flag HRTIM Timing Unit Interrupt Flag

+  * @{

+  */

+#define HRTIM_TIM_FLAG_CMP1       HRTIM_TIMISR_CMP1      /*!< Timer compare 1 interrupt flag */

+#define HRTIM_TIM_FLAG_CMP2       HRTIM_TIMISR_CMP2      /*!< Timer compare 2 interrupt flag */

+#define HRTIM_TIM_FLAG_CMP3       HRTIM_TIMISR_CMP3      /*!< Timer compare 3 interrupt flag */

+#define HRTIM_TIM_FLAG_CMP4       HRTIM_TIMISR_CMP4      /*!< Timer compare 4 interrupt flag */

+#define HRTIM_TIM_FLAG_REP        HRTIM_TIMISR_REP       /*!< Timer repetition interrupt flag */

+#define HRTIM_TIM_FLAG_UPD        HRTIM_TIMISR_UPD       /*!< Timer update interrupt flag */

+#define HRTIM_TIM_FLAG_CPT1       HRTIM_TIMISR_CPT1      /*!< Timer capture 1 interrupt flag */

+#define HRTIM_TIM_FLAG_CPT2       HRTIM_TIMISR_CPT2      /*!< Timer capture 2 interrupt flag */

+#define HRTIM_TIM_FLAG_SET1       HRTIM_TIMISR_SET1      /*!< Timer output 1 set interrupt flag */

+#define HRTIM_TIM_FLAG_RST1       HRTIM_TIMISR_RST1      /*!< Timer output 1 reset interrupt flag */

+#define HRTIM_TIM_FLAG_SET2       HRTIM_TIMISR_SET2      /*!< Timer output 2 set interrupt flag */

+#define HRTIM_TIM_FLAG_RST2       HRTIM_TIMISR_RST2      /*!< Timer output 2 reset interrupt flag */

+#define HRTIM_TIM_FLAG_RST        HRTIM_TIMISR_RST       /*!< Timer reset interrupt flag */

+#define HRTIM_TIM_FLAG_DLYPRT     HRTIM_TIMISR_DLYPRT    /*!< Timer delay protection interrupt flag */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Master_DMA_Request_Enable HRTIM Master DMA Request Enable

+  * @{

+  */

+#define HRTIM_MASTER_DMA_NONE         0x00000000U            /*!< No DMA request enable */

+#define HRTIM_MASTER_DMA_MCMP1        HRTIM_MDIER_MCMP1DE    /*!< Master compare 1 DMA request enable */

+#define HRTIM_MASTER_DMA_MCMP2        HRTIM_MDIER_MCMP2DE    /*!< Master compare 2 DMA request enable */

+#define HRTIM_MASTER_DMA_MCMP3        HRTIM_MDIER_MCMP3DE    /*!< Master compare 3 DMA request enable */

+#define HRTIM_MASTER_DMA_MCMP4        HRTIM_MDIER_MCMP4DE    /*!< Master compare 4 DMA request enable */

+#define HRTIM_MASTER_DMA_MREP         HRTIM_MDIER_MREPDE     /*!< Master Repetition DMA request enable */

+#define HRTIM_MASTER_DMA_SYNC         HRTIM_MDIER_SYNCDE     /*!< Synchronization input DMA request enable */

+#define HRTIM_MASTER_DMA_MUPD         HRTIM_MDIER_MUPDDE     /*!< Master update DMA request enable */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_Timing_Unit_DMA_Request_Enable HRTIM Timing Unit DMA Request Enable

+  * @{

+  */

+#define HRTIM_TIM_DMA_NONE       0x00000000U               /*!< No DMA request enable */

+#define HRTIM_TIM_DMA_CMP1       HRTIM_TIMDIER_CMP1DE      /*!< Timer compare 1 DMA request enable */

+#define HRTIM_TIM_DMA_CMP2       HRTIM_TIMDIER_CMP2DE      /*!< Timer compare 2 DMA request enable */

+#define HRTIM_TIM_DMA_CMP3       HRTIM_TIMDIER_CMP3DE      /*!< Timer compare 3 DMA request enable */

+#define HRTIM_TIM_DMA_CMP4       HRTIM_TIMDIER_CMP4DE      /*!< Timer compare 4 DMA request enable */

+#define HRTIM_TIM_DMA_REP        HRTIM_TIMDIER_REPDE       /*!< Timer repetition DMA request enable */

+#define HRTIM_TIM_DMA_UPD        HRTIM_TIMDIER_UPDDE       /*!< Timer update DMA request enable */

+#define HRTIM_TIM_DMA_CPT1       HRTIM_TIMDIER_CPT1DE      /*!< Timer capture 1 DMA request enable */

+#define HRTIM_TIM_DMA_CPT2       HRTIM_TIMDIER_CPT2DE      /*!< Timer capture 2 DMA request enable */

+#define HRTIM_TIM_DMA_SET1       HRTIM_TIMDIER_SET1DE      /*!< Timer output 1 set DMA request enable */

+#define HRTIM_TIM_DMA_RST1       HRTIM_TIMDIER_RST1DE      /*!< Timer output 1 reset DMA request enable */

+#define HRTIM_TIM_DMA_SET2       HRTIM_TIMDIER_SET2DE      /*!< Timer output 2 set DMA request enable */

+#define HRTIM_TIM_DMA_RST2       HRTIM_TIMDIER_RST2DE      /*!< Timer output 2 reset DMA request enable */

+#define HRTIM_TIM_DMA_RST        HRTIM_TIMDIER_RSTDE       /*!< Timer reset DMA request enable */

+#define HRTIM_TIM_DMA_DLYPRT     HRTIM_TIMDIER_DLYPRTDE    /*!< Timer delay protection DMA request enable */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+  /* Private macros --------------------------------------------------------*/

+/** @addtogroup HRTIM_Private_Macros

+  * @{

+  */

+#define IS_HRTIM_TIMERINDEX(TIMERINDEX)\

+    (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER)   || \

+     ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A)  || \

+     ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B)  || \

+     ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C)  || \

+     ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D)  || \

+     ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))

+

+#define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\

+     (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A)  || \

+      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B)  || \

+      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C)  || \

+      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D)  || \

+      ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))

+

+#define IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFFC0FFFFU) == 0x00000000U)

+

+#define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\

+    (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1)  || \

+     ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2)  || \

+     ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3)  || \

+     ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4))

+

+#define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\

+    (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1)   || \

+     ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2))

+

+#define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFFC00U) == 0x00000000U)

+

+#define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\

+    ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) &&   \

+     (((OUTPUT) == HRTIM_OUTPUT_TA1) ||          \

+      ((OUTPUT) == HRTIM_OUTPUT_TA2)))           \

+    ||                                           \

+    (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) &&    \

+     (((OUTPUT) == HRTIM_OUTPUT_TB1) ||          \

+      ((OUTPUT) == HRTIM_OUTPUT_TB2)))           \

+    ||                                           \

+    (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) &&    \

+     (((OUTPUT) == HRTIM_OUTPUT_TC1) ||          \

+      ((OUTPUT) == HRTIM_OUTPUT_TC2)))           \

+    ||                                           \

+    (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) &&    \

+     (((OUTPUT) == HRTIM_OUTPUT_TD1) ||          \

+      ((OUTPUT) == HRTIM_OUTPUT_TD2)))           \

+    ||                                           \

+    (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) &&    \

+     (((OUTPUT) == HRTIM_OUTPUT_TE1) ||          \

+      ((OUTPUT) == HRTIM_OUTPUT_TE2))))

+

+#define IS_HRTIM_EVENT(EVENT)\

+      (((EVENT) == HRTIM_EVENT_NONE)|| \

+       ((EVENT) == HRTIM_EVENT_1)   || \

+       ((EVENT) == HRTIM_EVENT_2)   || \

+       ((EVENT) == HRTIM_EVENT_3)   || \

+       ((EVENT) == HRTIM_EVENT_4)   || \

+       ((EVENT) == HRTIM_EVENT_5)   || \

+       ((EVENT) == HRTIM_EVENT_6)   || \

+       ((EVENT) == HRTIM_EVENT_7)   || \

+       ((EVENT) == HRTIM_EVENT_8)   || \

+       ((EVENT) == HRTIM_EVENT_9)   || \

+       ((EVENT) == HRTIM_EVENT_10))

+

+#define IS_HRTIM_FAULT(FAULT)\

+      (((FAULT) == HRTIM_FAULT_1)   || \

+       ((FAULT) == HRTIM_FAULT_2)   || \

+       ((FAULT) == HRTIM_FAULT_3)   || \

+       ((FAULT) == HRTIM_FAULT_4)   || \

+       ((FAULT) == HRTIM_FAULT_5))

+

+#define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\

+        (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \

+         ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2)  || \

+         ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4))

+

+#define IS_HRTIM_MODE(MODE)\

+          (((MODE) == HRTIM_MODE_CONTINUOUS)  ||  \

+           ((MODE) == HRTIM_MODE_SINGLESHOT) || \

+           ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))

+

+#define IS_HRTIM_MODE_ONEPULSE(MODE)\

+          (((MODE) == HRTIM_MODE_SINGLESHOT) || \

+           ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))

+

+

+#define IS_HRTIM_HALFMODE(HALFMODE)\

+            (((HALFMODE) == HRTIM_HALFMODE_DISABLED)  ||  \

+             ((HALFMODE) == HRTIM_HALFMODE_ENABLED))

+

+#define IS_HRTIM_SYNCSTART(SYNCSTART)\

+              (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED)  ||  \

+               ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED))

+

+#define IS_HRTIM_SYNCRESET(SYNCRESET)\

+                (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED)  ||  \

+                 ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED))

+

+#define IS_HRTIM_DACSYNC(DACSYNC)\

+                (((DACSYNC) == HRTIM_DACSYNC_NONE)          ||  \

+                 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1)  ||  \

+                 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2)  ||  \

+                 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3))

+

+#define IS_HRTIM_PRELOAD(PRELOAD)\

+                (((PRELOAD) == HRTIM_PRELOAD_DISABLED)  ||  \

+                 ((PRELOAD) == HRTIM_PRELOAD_ENABLED))

+

+#define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\

+                (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT)      ||  \

+                 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST)         ||  \

+                 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE))

+

+#define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\

+                (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT)      ||  \

+                 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST)         ||  \

+                 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE)  ||  \

+                 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1)           ||  \

+                 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2)           ||  \

+                 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3)           ||  \

+                 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE)    ||  \

+                 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE)    ||  \

+                 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE))

+

+#define IS_HRTIM_TIMERBURSTMODE(MODE)                               \

+                (((MODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK)  || \

+                 ((MODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER))

+#define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION)                               \

+                (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED)  || \

+                 ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED))

+

+#define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\

+                  (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \

+                   ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED))

+#define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0U) == 0x00000000U)

+

+#define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\

+      (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \

+       ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY))

+

+#define IS_HRTIM_TIMDEADTIMEINSERTION(TIMPUSHPULLMODE, TIMDEADTIMEINSERTION)\

+    ((((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) &&               \

+        ((((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \

+          ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED))))  \

+      ||                                                                     \

+        (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) &&             \

+         ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED)))

+

+#define IS_HRTIM_TIMDELAYEDPROTECTION(TIMPUSHPULLMODE, TIMDELAYEDPROTECTION)\

+          ((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED)          || \

+            ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6)  || \

+            ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6)  || \

+            ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6)  || \

+            ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) || \

+            ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) || \

+            ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7))    \

+            ||                                                                           \

+            (((TIMPUSHPULLMODE) ==  HRTIM_TIMPUSHPULLMODE_ENABLED) &&                    \

+             (((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6)     || \

+             ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))))

+

+#define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFFU) == 0x00000000U)

+

+#define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x80000001U) == 0x00000000U)

+

+

+#define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET)                       \

+              (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \

+               ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED))

+

+#define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\

+              (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)                  || \

+               ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT)    || \

+               ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)  || \

+               ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))

+

+/* Auto delayed mode is only available for compare units 2 and 4U */

+#define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE)     \

+    ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) &&                                 \

+     (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)                 ||  \

+      ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT)   ||  \

+      ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) ||  \

+      ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)))   \

+    ||                                                                         \

+    (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) &&                                 \

+     (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR)                 ||  \

+      ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT)   ||  \

+      ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) ||  \

+      ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))))

+

+#define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\

+              (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \

+               ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW))

+

+#define IS_HRTIM_OUTPUTPULSE(OUTPUTPULSE) ((OUTPUTPULSE) <= 0x0000FFFFU)

+

+#define IS_HRTIM_OUTPUTSET(OUTPUTSET)\

+              (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE)       || \

+               ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC)     || \

+               ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER)     || \

+               ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1)    || \

+               ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2)    || \

+               ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3)    || \

+               ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4)    || \

+               ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER)  || \

+               ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \

+               ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \

+               ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \

+               ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \

+               ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1)    || \

+               ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2)    || \

+               ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3)    || \

+               ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4)    || \

+               ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5)    || \

+               ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6)    || \

+               ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7)    || \

+               ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8)    || \

+               ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9)    || \

+               ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1)      || \

+               ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2)      || \

+               ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3)      || \

+               ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4)      || \

+               ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5)      || \

+               ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6)      || \

+               ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7)      || \

+               ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8)      || \

+               ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9)      || \

+               ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10)     || \

+               ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE))

+

+#define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\

+              (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE)       || \

+               ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC)     || \

+               ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER)     || \

+               ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1)    || \

+               ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2)    || \

+               ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3)    || \

+               ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4)    || \

+               ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER)  || \

+               ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \

+               ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \

+               ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \

+               ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \

+               ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1)    || \

+               ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2)    || \

+               ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3)    || \

+               ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4)    || \

+               ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5)    || \

+               ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6)    || \

+               ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7)    || \

+               ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8)    || \

+               ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9)    || \

+               ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1)      || \

+               ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2)      || \

+               ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3)      || \

+               ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4)      || \

+               ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5)      || \

+               ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6)      || \

+               ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7)      || \

+               ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8)      || \

+               ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9)      || \

+               ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10)     || \

+               ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE))

+

+#define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\

+              (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \

+               ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE))

+

+#define IS_HRTIM_OUTPUTIDLELEVEL(OUTPUTIDLELEVEL)\

+              (((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \

+               ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE))

+

+#define IS_HRTIM_OUTPUTFAULTLEVEL(OUTPUTFAULTLEVEL)\

+              (((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE)     || \

+               ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE)   || \

+               ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \

+               ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ))

+

+#define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\

+              (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED)  || \

+               ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED))

+

+#define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\

+              (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR)  || \

+               ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED))

+

+

+#define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER)    \

+   (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE)          || \

+   ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE)         || \

+   ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1)          || \

+   ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2)          || \

+   ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_3)          || \

+   ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_4)          || \

+   ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_5)          || \

+   ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_6)          || \

+   ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_7)          || \

+   ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_8)          || \

+   ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_9)          || \

+   ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10)            \

+   ||                                                           \

+   (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) &&                    \

+     (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET)     || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET)   || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET)     || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET)   || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET)     || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET)   || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET)     || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET)   || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))  \

+    ||                                                          \

+   (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) &&                    \

+     (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET)     || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET)   || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET)     || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET)   || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET)     || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET)   || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET)     || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET)   || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))  \

+    ||                                                          \

+   (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) &&                    \

+     (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET)     || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET)   || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET)     || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET)   || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET)     || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET)   || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET)     || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET)   || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))  \

+    ||                                                          \

+   (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) &&                    \

+     (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET)     || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET)   || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET)     || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET)   || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET)     || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET)   || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET)     || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET)   || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2)))  \

+    ||                                                          \

+   (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) &&                    \

+     (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET)     || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET)   || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET)     || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET)   || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET)     || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET)   || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET)     || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET)   || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \

+      ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2))))

+

+#define IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)\

+                (((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE)           || \

+                 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1)   || \

+                 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2)   || \

+                 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3)   || \

+                 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4)   || \

+                 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1)  || \

+                 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2)  || \

+                 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3)  || \

+                 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4)  || \

+                 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5)  || \

+                 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6)  || \

+                 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7)  || \

+                 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8)  || \

+                 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2)  || \

+                 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3)  || \

+                 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM))

+

+#define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\

+              (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \

+               ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED))

+

+#define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)\

+                (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8) || \

+                 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4) || \

+                 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2) || \

+                 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \

+                 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \

+                 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \

+                 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \

+                 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16))

+

+#define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\

+                (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE)    || \

+                 ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE))

+

+#define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\

+                    (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE)    || \

+                     ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY))

+

+#define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\

+                  (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE)    || \

+                   ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY))

+

+#define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\

+                      (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE)    || \

+                       ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE))

+

+#define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\

+                          (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE)    || \

+                           ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY))

+

+#define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\

+                        (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE)    || \

+                         ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY))

+

+#define IS_HRTIM_CHOPPER_PRESCALERRATIO(PRESCALERRATIO)\

+                        (((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16)    || \

+                         ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32)    || \

+                         ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48)    || \

+                         ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64)    || \

+                         ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80)    || \

+                         ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96)    || \

+                         ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112)   || \

+                         ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128)   || \

+                         ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144)   || \

+                         ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160)   || \

+                         ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176)   || \

+                         ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192)   || \

+                         ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208)   || \

+                         ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224)   || \

+                         ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240)   || \

+                         ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256))

+

+#define IS_HRTIM_CHOPPER_DUTYCYCLE(DUTYCYCLE)\

+                        (((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0)    || \

+                         ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125)  || \

+                         ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250)  || \

+                         ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375)  || \

+                         ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500)  || \

+                         ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625)  || \

+                         ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750)  || \

+                         ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875))

+

+#define IS_HRTIM_CHOPPER_PULSEWIDTH(PULSEWIDTH)\

+                        (((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16)   || \

+                         ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32)   || \

+                         ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48)   || \

+                         ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64)   || \

+                         ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80)   || \

+                         ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96)   || \

+                         ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112)  || \

+                         ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128)  || \

+                         ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144)  || \

+                         ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160)  || \

+                         ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176)  || \

+                         ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192)  || \

+                         ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208)  || \

+                         ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224)  || \

+                         ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240)  || \

+                         ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256))

+

+#define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\

+              (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE)             || \

+               ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT)    || \

+               ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT))

+

+#define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\

+              (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START)  || \

+               ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1)   || \

+               ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START)    || \

+               ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1))

+

+#define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\

+              (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE)  || \

+               ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE)  || \

+               ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE))

+

+#define IS_HRTIM_EVENTSRC(EVENTSRC)\

+                (((EVENTSRC) == HRTIM_EVENTSRC_1)   || \

+                 ((EVENTSRC) == HRTIM_EVENTSRC_2)   || \

+                 ((EVENTSRC) == HRTIM_EVENTSRC_3)   || \

+                 ((EVENTSRC) == HRTIM_EVENTSRC_4))

+

+#define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\

+    ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL)  &&      \

+       (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH)  ||           \

+        ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW)))              \

+      ||                                                            \

+      (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \

+       ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \

+       ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)))

+

+#define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\

+                    (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL)       || \

+                     ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE)  || \

+                     ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \

+                     ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))

+

+#define IS_HRTIM_EVENTFASTMODE(EVENT, FASTMODE)\

+    (((((EVENT) == HRTIM_EVENT_1) ||                 \

+       ((EVENT) == HRTIM_EVENT_2) ||                 \

+       ((EVENT) == HRTIM_EVENT_3) ||                 \

+       ((EVENT) == HRTIM_EVENT_4) ||                 \

+       ((EVENT) == HRTIM_EVENT_5)) &&                \

+      (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \

+       ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \

+    ||                                               \

+    (((EVENT) == HRTIM_EVENT_6) ||                   \

+     ((EVENT) == HRTIM_EVENT_7) ||                   \

+     ((EVENT) == HRTIM_EVENT_8) ||                   \

+     ((EVENT) == HRTIM_EVENT_9) ||                   \

+     ((EVENT) == HRTIM_EVENT_10)))

+

+

+#define IS_HRTIM_EVENTFILTER(EVENT, FILTER)\

+      ((((EVENT) == HRTIM_EVENT_1) ||            \

+        ((EVENT) == HRTIM_EVENT_2) ||            \

+        ((EVENT) == HRTIM_EVENT_3) ||            \

+        ((EVENT) == HRTIM_EVENT_4) ||            \

+        ((EVENT) == HRTIM_EVENT_5))              \

+       ||                                        \

+      ((((EVENT) == HRTIM_EVENT_6) ||            \

+        ((EVENT) == HRTIM_EVENT_7) ||            \

+        ((EVENT) == HRTIM_EVENT_8) ||            \

+        ((EVENT) == HRTIM_EVENT_9) ||            \

+        ((EVENT) == HRTIM_EVENT_10)) &&          \

+        (((FILTER) == HRTIM_EVENTFILTER_NONE) || \

+        ((FILTER) == HRTIM_EVENTFILTER_1)     || \

+        ((FILTER) == HRTIM_EVENTFILTER_2)     || \

+        ((FILTER) == HRTIM_EVENTFILTER_3)     || \

+        ((FILTER) == HRTIM_EVENTFILTER_4)     || \

+        ((FILTER) == HRTIM_EVENTFILTER_5)     || \

+        ((FILTER) == HRTIM_EVENTFILTER_6)     || \

+        ((FILTER) == HRTIM_EVENTFILTER_7)     || \

+        ((FILTER) == HRTIM_EVENTFILTER_8)     || \

+        ((FILTER) == HRTIM_EVENTFILTER_9)     || \

+        ((FILTER) == HRTIM_EVENTFILTER_10)    || \

+        ((FILTER) == HRTIM_EVENTFILTER_11)    || \

+        ((FILTER) == HRTIM_EVENTFILTER_12)    || \

+        ((FILTER) == HRTIM_EVENTFILTER_13)    || \

+        ((FILTER) == HRTIM_EVENTFILTER_14)    || \

+        ((FILTER) == HRTIM_EVENTFILTER_15))))

+

+#define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\

+             (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1)  || \

+              ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2)   || \

+              ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4)   || \

+              ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8))

+

+#define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\

+              (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \

+              ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL))

+

+#define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\

+              (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \

+               ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH))

+

+#define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\

+    (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED)  || \

+     ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED))

+

+#define IS_HRTIM_FAULTFILTER(FAULTFILTER)\

+                (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \

+                 ((FAULTFILTER) == HRTIM_FAULTFILTER_1)    || \

+                 ((FAULTFILTER) == HRTIM_FAULTFILTER_2)    || \

+                 ((FAULTFILTER) == HRTIM_FAULTFILTER_3)    || \

+                 ((FAULTFILTER) == HRTIM_FAULTFILTER_4)    || \

+                 ((FAULTFILTER) == HRTIM_FAULTFILTER_5)    || \

+                 ((FAULTFILTER) == HRTIM_FAULTFILTER_6)    || \

+                 ((FAULTFILTER) == HRTIM_FAULTFILTER_7)    || \

+                 ((FAULTFILTER) == HRTIM_FAULTFILTER_8)    || \

+                 ((FAULTFILTER) == HRTIM_FAULTFILTER_9)    || \

+                 ((FAULTFILTER) == HRTIM_FAULTFILTER_10)   || \

+                 ((FAULTFILTER) == HRTIM_FAULTFILTER_11)   || \

+                 ((FAULTFILTER) == HRTIM_FAULTFILTER_12)   || \

+                 ((FAULTFILTER) == HRTIM_FAULTFILTER_13)   || \

+                 ((FAULTFILTER) == HRTIM_FAULTFILTER_14)   || \

+                 ((FAULTFILTER) == HRTIM_FAULTFILTER_15))

+

+#define IS_HRTIM_FAULTLOCK(FAULTLOCK)\

+              (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \

+               ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY))

+

+#define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\

+             (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1)  || \

+              ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2)   || \

+              ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4)   || \

+              ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8))

+

+#define IS_HRTIM_BURSTMODE(BURSTMODE)\

+              (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT)  || \

+               ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS))

+

+#define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\

+              (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER)      || \

+               ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A)     || \

+               ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B)     || \

+               ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C)     || \

+               ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D)     || \

+               ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E)     || \

+               ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC)    || \

+               ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC)    || \

+               ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO)   || \

+               ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM))

+

+#define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\

+              (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1)     || \

+               ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2)     || \

+               ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4)     || \

+               ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8)     || \

+               ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16)    || \

+               ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32)    || \

+               ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64)    || \

+               ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128)   || \

+               ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256)   || \

+               ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512)   || \

+               ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024)  || \

+               ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048)  || \

+               ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096)  || \

+               ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192)  || \

+               ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \

+               ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768))

+

+#define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\

+              (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED)  || \

+               ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED))

+

+#define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\

+              (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE)               || \

+               ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET)       || \

+               ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION)  || \

+               ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_MASTER_CMP1)       || \

+               ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_MASTER_CMP2)       || \

+               ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_MASTER_CMP3)       || \

+               ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_MASTER_CMP4)       || \

+               ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_RESET)      || \

+               ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \

+               ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_CMP1)       || \

+               ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_CMP2)       || \

+               ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERB_RESET)      || \

+               ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \

+               ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERB_CMP1)       || \

+               ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERB_CMP2)       || \

+               ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERC_RESET)      || \

+               ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \

+               ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERC_CMP1)       || \

+               ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERC_CMP2)       || \

+               ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_RESET)      || \

+               ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \

+               ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_CMP1)       || \

+               ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_CMP2)       || \

+               ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERE_RESET)      || \

+               ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \

+               ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERE_CMP1)       || \

+               ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERE_CMP2)       || \

+               ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7)     || \

+               ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8)     || \

+               ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_EVENT_7)           || \

+               ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_EVENT_8)           || \

+               ((BURSTMODETRIGGER) ==  HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP))

+

+#define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\

+             (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER)   || \

+              ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A)  || \

+              ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B)  || \

+              ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C)  || \

+              ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D)  || \

+              ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E))

+

+#define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\

+    (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION)   || \

+     ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) || \

+     ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910)  || \

+     ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114)  || \

+     ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14))

+

+#define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA)                                            \

+    ((((TIMER) == HRTIM_TIMERINDEX_MASTER)  && (((BURSTDMA) & 0xFFFFC000U) == 0x00000000U)) \

+  || (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \

+  || (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \

+  || (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \

+  || (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \

+  || (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)))

+

+#define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\

+    (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED)  || \

+     ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED))

+

+#define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0U) == 0x00000000U)

+

+#define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFFC0FFU) == 0x00000000U)

+

+#define IS_HRTIM_IT(IT) (((IT) & 0xFFFCFFC0U) == 0x00000000U)

+

+

+#define IS_HRTIM_MASTER_IT(MASTER_IT) (((MASTER_IT) & 0xFFFFFF80U) == 0x00000000U)

+

+

+#define IS_HRTIM_TIM_IT(TIM_IT) (((TIM_IT) & 0xFFFF8020U) == 0x00000000U)

+

+

+#define IS_HRTIM_MASTER_DMA(MASTER_DMA) (((MASTER_DMA) & 0xFF80FFFFU) == 0x00000000U)

+

+#define IS_HRTIM_TIM_DMA(TIM_DMA) (((TIM_DMA) & 0x8020FFFFU) == 0x00000000U)

+/**

+  * @}

+  */

+

+/* Exported macros -----------------------------------------------------------*/

+/** @defgroup HRTIM_Exported_Macros HRTIM Exported Macros

+  * @{

+  */

+

+/** @brief Reset HRTIM handle state

+  * @param  __HANDLE__ HRTIM handle.

+  * @retval None

+  */

+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)

+#define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__)                do{                                                       \

+                                                                    (__HANDLE__)->State             = HAL_HRTIM_STATE_RESET; \

+                                                                    (__HANDLE__)->MspInitCallback   = NULL;                  \

+                                                                    (__HANDLE__)->MspDeInitCallback = NULL;                 \

+                                                                  } while(0)

+#else

+#define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET)

+#endif

+

+/** @brief  Enables or disables the timer counter(s)

+  * @param  __HANDLE__ specifies the HRTIM Handle.

+  * @param  __TIMERS__ timers to enable/disable

+  *        This parameter can be any combinations of the following values:

+  *            @arg HRTIM_TIMERID_MASTER: Master timer identifier

+  *            @arg HRTIM_TIMERID_TIMER_A: Timer A identifier

+  *            @arg HRTIM_TIMERID_TIMER_B: Timer B identifier

+  *            @arg HRTIM_TIMERID_TIMER_C: Timer C identifier

+  *            @arg HRTIM_TIMERID_TIMER_D: Timer D identifier

+  *            @arg HRTIM_TIMERID_TIMER_E: Timer E identifier

+  * @retval None

+  */

+#define __HAL_HRTIM_ENABLE(__HANDLE__, __TIMERS__)   ((__HANDLE__)->Instance->sMasterRegs.MCR |= (__TIMERS__))

+

+/* The counter of a timing unit is disabled only if all the timer outputs */

+/* are disabled and no capture is configured                              */

+#define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN | HRTIM_OENR_TA1OEN)

+#define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN | HRTIM_OENR_TB1OEN)

+#define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN | HRTIM_OENR_TC1OEN)

+#define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN | HRTIM_OENR_TD1OEN)

+#define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN | HRTIM_OENR_TE1OEN)

+#define __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)\

+  do {\

+    if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\

+      {\

+        ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\

+      }\

+    if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\

+      {\

+        if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == (uint32_t)RESET)\

+          {\

+            ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\

+          }\

+      }\

+    if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\

+      {\

+        if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == (uint32_t)RESET)\

+          {\

+            ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\

+          }\

+      }\

+    if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\

+      {\

+        if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == (uint32_t)RESET)\

+          {\

+            ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\

+          }\

+      }\

+    if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\

+      {\

+        if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == (uint32_t)RESET)\

+          {\

+            ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\

+          }\

+      }\

+    if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\

+      {\

+        if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == (uint32_t)RESET)\

+          {\

+            ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\

+          }\

+      }\

+  } while(0U)

+

+

+/** @brief  Enables or disables the specified HRTIM common interrupts.

+  * @param  __HANDLE__ specifies the HRTIM Handle.

+  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.

+  *        This parameter can be one of the following values:

+  *            @arg HRTIM_IT_FLT1: Fault 1 interrupt enable

+  *            @arg HRTIM_IT_FLT2: Fault 2 interrupt enable

+  *            @arg HRTIM_IT_FLT3: Fault 3 interrupt enable

+  *            @arg HRTIM_IT_FLT4: Fault 4 interrupt enable

+  *            @arg HRTIM_IT_FLT5: Fault 5 interrupt enable

+  *            @arg HRTIM_IT_SYSFLT: System Fault interrupt enable

+  *            @arg HRTIM_IT_BMPER: Burst mode period interrupt enable

+  * @retval None

+  */

+#define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))

+#define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))

+

+/** @brief  Enables or disables the specified HRTIM Master timer interrupts.

+  * @param  __HANDLE__ specifies the HRTIM Handle.

+  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.

+  *        This parameter can be one of the following values:

+  *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable

+  *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable

+  *            @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable

+  *            @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable

+  *            @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable

+  *            @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable

+  *            @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable

+  * @retval None

+  */

+#define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__INTERRUPT__))

+#define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__))

+

+/** @brief  Enables or disables the specified HRTIM Timerx interrupts.

+  * @param  __HANDLE__ specifies the HRTIM Handle.

+  * @param  __TIMER__ specified the timing unit (Timer A to E)

+  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.

+  *        This parameter can be one of the following values:

+  *            @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable

+  *            @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable

+  *            @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable

+  *            @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable

+  *            @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable

+  *            @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable

+  *            @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable

+  *            @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable

+  *            @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable

+  *            @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable

+  *            @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable

+  *            @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable

+  *            @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable

+  *            @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable

+  * @retval None

+  */

+#define __HAL_HRTIM_TIMER_ENABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__)   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__INTERRUPT__))

+#define __HAL_HRTIM_TIMER_DISABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__INTERRUPT__))

+

+/** @brief  Checks if the specified HRTIM common interrupt  source  is enabled or disabled.

+  * @param  __HANDLE__ specifies the HRTIM Handle.

+  * @param  __INTERRUPT__ specifies the interrupt source to check.

+  *        This parameter can be one of the following values:

+  *            @arg HRTIM_IT_FLT1: Fault 1 interrupt enable

+  *            @arg HRTIM_IT_FLT2: Fault 2 interrupt enable

+  *            @arg HRTIM_IT_FLT3: Fault 3 enable

+  *            @arg HRTIM_IT_FLT4: Fault 4 enable

+  *            @arg HRTIM_IT_FLT5: Fault 5 enable

+  *            @arg HRTIM_IT_SYSFLT: System Fault interrupt enable

+  *            @arg HRTIM_IT_BMPER: Burst mode period interrupt enable

+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).

+  */

+#define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__)     ((((__HANDLE__)->Instance->sCommonRegs.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

+

+/** @brief  Checks if the specified HRTIM Master interrupt source  is enabled or disabled.

+  * @param  __HANDLE__ specifies the HRTIM Handle.

+  * @param  __INTERRUPT__ specifies the interrupt source to check.

+  *        This parameter can be one of the following values:

+  *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable

+  *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable

+  *            @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable

+  *            @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable

+  *            @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable

+  *            @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable

+  *            @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable

+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).

+  */

+#define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__)     ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

+

+/** @brief  Checks if the specified HRTIM Timerx interrupt source  is enabled or disabled.

+  * @param  __HANDLE__ specifies the HRTIM Handle.

+  * @param  __TIMER__ specified the timing unit (Timer A to E)

+  * @param  __INTERRUPT__ specifies the interrupt source to check.

+  *        This parameter can be one of the following values:

+  *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable

+  *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable

+  *            @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable

+  *            @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable

+  *            @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable

+  *            @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable

+  *            @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable

+  *            @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable

+  *            @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable

+  *            @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable

+  *            @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable

+  *            @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable

+  *            @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable

+  *            @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable

+  *            @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable

+  *            @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable

+  *            @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable

+  *            @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable

+  *            @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable

+  *            @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable

+  *            @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable

+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).

+  */

+#define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__)     ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

+

+/** @brief  Clears the specified HRTIM common pending flag.

+  * @param  __HANDLE__ specifies the HRTIM Handle.

+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.

+  *        This parameter can be one of the following values:

+  *            @arg HRTIM_IT_FLT1: Fault 1 interrupt clear flag

+  *            @arg HRTIM_IT_FLT2: Fault 2 interrupt clear flag

+  *            @arg HRTIM_IT_FLT3: Fault 3 clear flag

+  *            @arg HRTIM_IT_FLT4: Fault 4 clear flag

+  *            @arg HRTIM_IT_FLT5: Fault 5 clear flag

+  *            @arg HRTIM_IT_SYSFLT: System Fault interrupt clear flag

+  *            @arg HRTIM_IT_BMPER: Burst mode period interrupt clear flag

+  * @retval None

+  */

+#define __HAL_HRTIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sCommonRegs.ICR = (__INTERRUPT__))

+

+/** @brief  Clears the specified HRTIM Master pending flag.

+  * @param  __HANDLE__ specifies the HRTIM Handle.

+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.

+  *        This parameter can be one of the following values:

+  *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt clear flag

+  *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt clear flag

+  *            @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt clear flag

+  *            @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt clear flag

+  *            @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt clear flag

+  *            @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt clear flag

+  *            @arg HRTIM_MASTER_IT_MUPD: Master update interrupt clear flag

+  * @retval None

+  */

+#define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sMasterRegs.MICR = (__INTERRUPT__))

+

+/** @brief  Clears the specified HRTIM Timerx pending flag.

+  * @param  __HANDLE__ specifies the HRTIM Handle.

+  * @param  __TIMER__ specified the timing unit (Timer A to E)

+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.

+  *        This parameter can be one of the following values:

+  *            @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt clear flag

+  *            @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt clear flag

+  *            @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt clear flag

+  *            @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt clear flag

+  *            @arg HRTIM_TIM_IT_REP: Timer repetition interrupt clear flag

+  *            @arg HRTIM_TIM_IT_UPD: Timer update interrupt clear flag

+  *            @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt clear flag

+  *            @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt clear flag

+  *            @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt clear flag

+  *            @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt clear flag

+  *            @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt clear flag

+  *            @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt clear flag

+  *            @arg HRTIM_TIM_IT_RST: Timer reset interrupt clear flag

+  *            @arg HRTIM_TIM_IT_DLYPRT: Timer output 1 delay protection interrupt clear flag

+  * @retval None

+  */

+#define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__)   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__INTERRUPT__))

+

+/* DMA HANDLING */

+/** @brief  Enables or disables the specified HRTIM Master timer DMA requests.

+  * @param  __HANDLE__ specifies the HRTIM Handle.

+  * @param  __DMA__ specifies the DMA request to enable or disable.

+  *        This parameter can be one of the following values:

+  *            @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA request enable

+  *            @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA request enable

+  *            @arg HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA request enable

+  *            @arg HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA request enable

+  *            @arg HRTIM_MASTER_DMA_MREP: Master Repetition DMA request enable

+  *            @arg HRTIM_MASTER_DMA_SYNC: Synchronization input DMA request enable

+  *            @arg HRTIM_MASTER_DMA_MUPD: Master update DMA request enable

+  * @retval None

+  */

+#define __HAL_HRTIM_MASTER_ENABLE_DMA(__HANDLE__, __DMA__)   ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__DMA__))

+#define __HAL_HRTIM_MASTER_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__DMA__))

+

+/** @brief  Enables or disables the specified HRTIM Timerx DMA requests.

+  * @param  __HANDLE__ specifies the HRTIM Handle.

+  * @param  __TIMER__ specified the timing unit (Timer A to E)

+  * @param  __DMA__ specifies the DMA request to enable or disable.

+  *        This parameter can be one of the following values:

+  *            @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA request enable

+  *            @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA request enable

+  *            @arg HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA request enable

+  *            @arg HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA request enable

+  *            @arg HRTIM_TIM_DMA_REP: Timer repetition DMA request enable

+  *            @arg HRTIM_TIM_DMA_UPD: Timer update DMA request enable

+  *            @arg HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA request enable

+  *            @arg HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA request enable

+  *            @arg HRTIM_TIM_DMA_SET1: Timer output 1 set DMA request enable

+  *            @arg HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA request enable

+  *            @arg HRTIM_TIM_DMA_SET2: Timer output 2 set DMA request enable

+  *            @arg HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA request enable

+  *            @arg HRTIM_TIM_DMA_RST: Timer reset DMA request enable

+  *            @arg HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA request enable

+  * @retval None

+  */

+#define __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__)   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__DMA__))

+#define __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__))

+

+#define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__)        (((__HANDLE__)->Instance->sCommonRegs.ISR & (__FLAG__)) == (__FLAG__))

+#define __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__))

+

+#define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__)        (((__HANDLE__)->Instance->sMasterRegs.MISR & (__FLAG__)) == (__FLAG__))

+#define __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__))

+

+#define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__,  __TIMER__, __FLAG__)        (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR & (__FLAG__)) == (__FLAG__))

+#define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__,  __TIMER__, __FLAG__)      ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__FLAG__))

+

+/** @brief  Sets the HRTIM timer Counter Register value on runtime

+  * @param  __HANDLE__ HRTIM Handle.

+  * @param  __TIMER__ HRTIM timer

+  *                   This parameter can be one of the following values:

+  *                   @arg 0x5 for master timer

+  *                   @arg 0x0 to 0x4 for timers A to E

+  * @param  __COUNTER__ specifies the Counter Register new value.

+  * @retval None

+  */

+#define __HAL_HRTIM_SETCOUNTER(__HANDLE__, __TIMER__, __COUNTER__) \

+  (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR = (__COUNTER__)) :\

+   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR = (__COUNTER__)))

+

+/** @brief  Gets the HRTIM timer Counter Register value on runtime

+  * @param  __HANDLE__ HRTIM Handle.

+  * @param  __TIMER__ HRTIM timer

+  *                   This parameter can be one of the following values:

+  *                   @arg 0x5 for master timer

+  *                   @arg 0x0 to 0x4 for timers A to E

+  * @retval HRTIM timer Counter Register value

+  */

+#define __HAL_HRTIM_GETCOUNTER(__HANDLE__, __TIMER__) \

+  (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR) :\

+   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR))

+

+/** @brief  Sets the HRTIM timer Period value on runtime

+  * @param  __HANDLE__ HRTIM Handle.

+  * @param  __TIMER__ HRTIM timer

+  *                   This parameter can be one of the following values:

+  *                   @arg 0x5 for master timer

+  *                   @arg 0x0 to 0x4 for timers A to E

+  * @param  __PERIOD__ specifies the Period Register new value.

+  * @retval None

+  */

+#define __HAL_HRTIM_SETPERIOD(__HANDLE__, __TIMER__, __PERIOD__) \

+  (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER = (__PERIOD__)) :\

+   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR = (__PERIOD__)))

+

+/** @brief  Gets the HRTIM timer Period Register value on runtime

+  * @param  __HANDLE__ HRTIM Handle.

+  * @param  __TIMER__ HRTIM timer

+  *                   This parameter can be one of the following values:

+  *                   @arg 0x5 for master timer

+  *                   @arg 0x0 to 0x4 for timers A to E

+  * @retval timer Period Register

+  */

+#define __HAL_HRTIM_GETPERIOD(__HANDLE__, __TIMER__) \

+  (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER) :\

+   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR))

+

+/** @brief  Sets the HRTIM timer clock prescaler value on runtime

+  * @param  __HANDLE__ HRTIM Handle.

+  * @param  __TIMER__ HRTIM timer

+  *                   This parameter can be one of the following values:

+  *                   @arg 0x5 for master timer

+  *                   @arg 0x0 to 0x4 for timers A to E

+  * @param  __PRESCALER__ specifies the clock prescaler new value.

+  *                   This parameter can be one of the following values:

+  *                   @arg HRTIM_PRESCALERRATIO_DIV1: fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)

+  *                   @arg HRTIM_PRESCALERRATIO_DIV2: fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)

+  *                   @arg HRTIM_PRESCALERRATIO_DIV4: fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)

+  * @retval None

+  */

+#define __HAL_HRTIM_SETCLOCKPRESCALER(__HANDLE__, __TIMER__, __PRESCALER__) \

+  (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? (MODIFY_REG((__HANDLE__)->Instance->sMasterRegs.MCR, HRTIM_MCR_CK_PSC, (__PRESCALER__))) :\

+   (MODIFY_REG((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR, HRTIM_TIMCR_CK_PSC, (__PRESCALER__))))

+

+/** @brief  Gets the HRTIM timer clock prescaler value on runtime

+  * @param  __HANDLE__ HRTIM Handle.

+  * @param  __TIMER__ HRTIM timer

+  *                   This parameter can be one of the following values:

+  *                   @arg 0x5 for master timer

+  *                   @arg 0x0 to 0x4 for timers A to E

+  * @retval timer clock prescaler value

+  */

+#define __HAL_HRTIM_GETCLOCKPRESCALER(__HANDLE__, __TIMER__) \

+  (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR & HRTIM_MCR_CK_PSC) :\

+   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR  & HRTIM_TIMCR_CK_PSC))

+

+/** @brief  Sets the HRTIM timer Compare Register value on runtime

+  * @param  __HANDLE__ HRTIM Handle.

+  * @param  __TIMER__ HRTIM timer

+  *                   This parameter can be one of the following values:

+  *                   @arg 0x0 to 0x4 for timers A to E

+  * @param  __COMPAREUNIT__ timer compare unit

+  *                   This parameter can be one of the following values:

+  *                   @arg HRTIM_COMPAREUNIT_1: Compare unit 1

+  *                   @arg HRTIM_COMPAREUNIT_2: Compare unit 2

+  *                   @arg HRTIM_COMPAREUNIT_3: Compare unit 3

+  *                   @arg HRTIM_COMPAREUNIT_4: Compare unit 4

+  * @param  __COMPARE__ specifies the Compare new value.

+  * @retval None

+  */

+#define __HAL_HRTIM_SETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__) \

+      (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \

+        (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\

+         ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\

+         ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\

+         ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \

+         : \

+        (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\

+         ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\

+         ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\

+         ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__))))

+

+/** @brief  Gets the HRTIM timer Compare Register value on runtime

+  * @param  __HANDLE__ HRTIM Handle.

+  * @param  __TIMER__ HRTIM timer

+  *                   This parameter can be one of the following values:

+  *                   @arg 0x0 to 0x4 for timers A to E

+  * @param  __COMPAREUNIT__ timer compare unit

+  *                   This parameter can be one of the following values:

+  *                   @arg HRTIM_COMPAREUNIT_1: Compare unit 1

+  *                   @arg HRTIM_COMPAREUNIT_2: Compare unit 2

+  *                   @arg HRTIM_COMPAREUNIT_3: Compare unit 3

+  *                   @arg HRTIM_COMPAREUNIT_4: Compare unit 4

+  * @retval Compare value

+  */

+#define __HAL_HRTIM_GETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__) \

+      (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \

+        (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\

+         ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\

+         ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\

+         ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \

+         : \

+        (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\

+         ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\

+         ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\

+         ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR)))

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup HRTIM_Exported_Functions

+* @{

+*/

+

+/** @addtogroup HRTIM_Exported_Functions_Group1

+* @{

+*/

+

+/* Initialization and Configuration functions  ********************************/

+HAL_StatusTypeDef HAL_HRTIM_Init(HRTIM_HandleTypeDef *hhrtim);

+

+HAL_StatusTypeDef HAL_HRTIM_DeInit (HRTIM_HandleTypeDef *hhrtim);

+

+void HAL_HRTIM_MspInit(HRTIM_HandleTypeDef *hhrtim);

+

+void HAL_HRTIM_MspDeInit(HRTIM_HandleTypeDef *hhrtim);

+

+HAL_StatusTypeDef HAL_HRTIM_TimeBaseConfig(HRTIM_HandleTypeDef *hhrtim,

+                                           uint32_t TimerIdx,

+                                           HRTIM_TimeBaseCfgTypeDef * pTimeBaseCfg);

+/**

+  * @}

+  */

+

+/** @addtogroup HRTIM_Exported_Functions_Group2

+* @{

+*/

+

+/* Simple time base related functions  *****************************************/

+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart(HRTIM_HandleTypeDef *hhrtim,

+                                           uint32_t TimerIdx);

+

+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop(HRTIM_HandleTypeDef *hhrtim,

+                                          uint32_t TimerIdx);

+

+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_IT(HRTIM_HandleTypeDef *hhrtim,

+                                              uint32_t TimerIdx);

+

+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_IT(HRTIM_HandleTypeDef *hhrtim,

+                                             uint32_t TimerIdx);

+

+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStart_DMA(HRTIM_HandleTypeDef *hhrtim,

+                                               uint32_t TimerIdx,

+                                               uint32_t SrcAddr,

+                                               uint32_t DestAddr,

+                                               uint32_t Length);

+

+HAL_StatusTypeDef HAL_HRTIM_SimpleBaseStop_DMA(HRTIM_HandleTypeDef *hhrtim,

+                                              uint32_t TimerIdx);

+

+/**

+  * @}

+  */

+

+/** @addtogroup HRTIM_Exported_Functions_Group3

+* @{

+*/

+/* Simple output compare related functions  ************************************/

+HAL_StatusTypeDef HAL_HRTIM_SimpleOCChannelConfig(HRTIM_HandleTypeDef *hhrtim,

+                                                 uint32_t TimerIdx,

+                                                 uint32_t OCChannel,

+                                                 HRTIM_SimpleOCChannelCfgTypeDef* pSimpleOCChannelCfg);

+

+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart(HRTIM_HandleTypeDef *hhrtim,

+                                         uint32_t TimerIdx,

+                                         uint32_t OCChannel);

+

+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop(HRTIM_HandleTypeDef *hhrtim,

+                                        uint32_t TimerIdx,

+                                        uint32_t OCChannel);

+

+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_IT(HRTIM_HandleTypeDef *hhrtim,

+                                            uint32_t TimerIdx,

+                                            uint32_t OCChannel);

+

+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_IT(HRTIM_HandleTypeDef *hhrtim,

+                                           uint32_t TimerIdx,

+                                           uint32_t OCChannel);

+

+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStart_DMA(HRTIM_HandleTypeDef *hhrtim,

+                                             uint32_t TimerIdx,

+                                             uint32_t OCChannel,

+                                             uint32_t SrcAddr,

+                                             uint32_t DestAddr,

+                                             uint32_t Length);

+

+HAL_StatusTypeDef HAL_HRTIM_SimpleOCStop_DMA(HRTIM_HandleTypeDef *hhrtim,

+                                            uint32_t TimerIdx,

+                                            uint32_t OCChannel);

+

+/**

+  * @}

+  */

+

+/** @addtogroup HRTIM_Exported_Functions_Group4

+* @{

+*/

+/* Simple PWM output related functions  ****************************************/

+HAL_StatusTypeDef HAL_HRTIM_SimplePWMChannelConfig(HRTIM_HandleTypeDef *hhrtim,

+                                                  uint32_t TimerIdx,

+                                                  uint32_t PWMChannel,

+                                                  HRTIM_SimplePWMChannelCfgTypeDef* pSimplePWMChannelCfg);

+

+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart(HRTIM_HandleTypeDef *hhrtim,

+                                          uint32_t TimerIdx,

+                                          uint32_t PWMChannel);

+

+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop(HRTIM_HandleTypeDef *hhrtim,

+                                         uint32_t TimerIdx,

+                                         uint32_t PWMChannel);

+

+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_IT(HRTIM_HandleTypeDef *hhrtim,

+                                             uint32_t TimerIdx,

+                                             uint32_t PWMChannel);

+

+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_IT(HRTIM_HandleTypeDef *hhrtim,

+                                            uint32_t TimerIdx,

+                                            uint32_t PWMChannel);

+

+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStart_DMA(HRTIM_HandleTypeDef *hhrtim,

+                                              uint32_t TimerIdx,

+                                              uint32_t PWMChannel,

+                                              uint32_t SrcAddr,

+                                              uint32_t DestAddr,

+                                              uint32_t Length);

+

+HAL_StatusTypeDef HAL_HRTIM_SimplePWMStop_DMA(HRTIM_HandleTypeDef *hhrtim,

+                                             uint32_t TimerIdx,

+                                             uint32_t PWMChannel);

+

+/**

+  * @}

+  */

+

+/** @addtogroup HRTIM_Exported_Functions_Group5

+* @{

+*/

+/* Simple capture related functions  *******************************************/

+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureChannelConfig(HRTIM_HandleTypeDef *hhrtim,

+                                                      uint32_t TimerIdx,

+                                                      uint32_t CaptureChannel,

+                                                      HRTIM_SimpleCaptureChannelCfgTypeDef* pSimpleCaptureChannelCfg);

+

+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart(HRTIM_HandleTypeDef *hhrtim,

+                                              uint32_t TimerIdx,

+                                              uint32_t CaptureChannel);

+

+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop(HRTIM_HandleTypeDef *hhrtim,

+                                             uint32_t TimerIdx,

+                                             uint32_t CaptureChannel);

+

+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_IT(HRTIM_HandleTypeDef *hhrtim,

+                                                 uint32_t TimerIdx,

+                                                 uint32_t CaptureChannel);

+

+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_IT(HRTIM_HandleTypeDef *hhrtim,

+                                                uint32_t TimerIdx,

+                                                uint32_t CaptureChannel);

+

+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStart_DMA(HRTIM_HandleTypeDef *hhrtim,

+                                                  uint32_t TimerIdx,

+                                                  uint32_t CaptureChannel,

+                                                  uint32_t SrcAddr,

+                                                  uint32_t DestAddr,

+                                                  uint32_t Length);

+

+HAL_StatusTypeDef HAL_HRTIM_SimpleCaptureStop_DMA(HRTIM_HandleTypeDef *hhrtim,

+                                                 uint32_t TimerIdx,

+                                                 uint32_t CaptureChannel);

+

+/**

+  * @}

+  */

+

+/** @addtogroup HRTIM_Exported_Functions_Group6

+* @{

+*/

+/* Simple one pulse related functions  *****************************************/

+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseChannelConfig(HRTIM_HandleTypeDef *hhrtim,

+                                                       uint32_t TimerIdx,

+                                                       uint32_t OnePulseChannel,

+                                                       HRTIM_SimpleOnePulseChannelCfgTypeDef* pSimpleOnePulseChannelCfg);

+

+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart(HRTIM_HandleTypeDef *hhrtim,

+                                               uint32_t TimerIdx,

+                                               uint32_t OnePulseChannel);

+

+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop(HRTIM_HandleTypeDef *hhrtim,

+                                              uint32_t TimerIdx,

+                                             uint32_t OnePulseChannel);

+

+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStart_IT(HRTIM_HandleTypeDef *hhrtim,

+                                                  uint32_t TimerIdx,

+                                                  uint32_t OnePulseChannel);

+

+HAL_StatusTypeDef HAL_HRTIM_SimpleOnePulseStop_IT(HRTIM_HandleTypeDef *hhrtim,

+                                                 uint32_t TimerIdx,

+                                                 uint32_t OnePulseChannel);

+

+/**

+  * @}

+  */

+

+/** @addtogroup HRTIM_Exported_Functions_Group7

+* @{

+*/

+HAL_StatusTypeDef HAL_HRTIM_BurstModeConfig(HRTIM_HandleTypeDef *hhrtim,

+                                            HRTIM_BurstModeCfgTypeDef* pBurstModeCfg);

+

+HAL_StatusTypeDef HAL_HRTIM_EventConfig(HRTIM_HandleTypeDef *hhrtim,

+                                        uint32_t Event,

+                                        HRTIM_EventCfgTypeDef* pEventCfg);

+

+HAL_StatusTypeDef HAL_HRTIM_EventPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,

+                                                 uint32_t Prescaler);

+

+HAL_StatusTypeDef HAL_HRTIM_FaultConfig(HRTIM_HandleTypeDef *hhrtim,

+                                        uint32_t Fault,

+                                        HRTIM_FaultCfgTypeDef* pFaultCfg);

+

+HAL_StatusTypeDef HAL_HRTIM_FaultPrescalerConfig(HRTIM_HandleTypeDef *hhrtim,

+                                                 uint32_t Prescaler);

+

+void HAL_HRTIM_FaultModeCtl(HRTIM_HandleTypeDef * hhrtim,

+                            uint32_t Faults,

+                            uint32_t Enable);

+

+HAL_StatusTypeDef HAL_HRTIM_ADCTriggerConfig(HRTIM_HandleTypeDef *hhrtim,

+                                             uint32_t ADCTrigger,

+                                             HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg);

+

+/**

+  * @}

+  */

+

+/** @addtogroup HRTIM_Exported_Functions_Group8

+* @{

+*/

+/* Waveform related functions *************************************************/

+HAL_StatusTypeDef HAL_HRTIM_WaveformTimerConfig(HRTIM_HandleTypeDef *hhrtim,

+                                                uint32_t TimerIdx,

+                                                HRTIM_TimerCfgTypeDef * pTimerCfg);

+

+HAL_StatusTypeDef HAL_HRTIM_WaveformCompareConfig(HRTIM_HandleTypeDef *hhrtim,

+                                                  uint32_t TimerIdx,

+                                                  uint32_t CompareUnit,

+                                                  HRTIM_CompareCfgTypeDef* pCompareCfg);

+

+HAL_StatusTypeDef HAL_HRTIM_WaveformCaptureConfig(HRTIM_HandleTypeDef *hhrtim,

+                                                  uint32_t TimerIdx,

+                                                  uint32_t CaptureUnit,

+                                                  HRTIM_CaptureCfgTypeDef* pCaptureCfg);

+

+HAL_StatusTypeDef HAL_HRTIM_WaveformOutputConfig(HRTIM_HandleTypeDef *hhrtim,

+                                                 uint32_t TimerIdx,

+                                                 uint32_t Output,

+                                                 HRTIM_OutputCfgTypeDef * pOutputCfg);

+

+HAL_StatusTypeDef HAL_HRTIM_WaveformSetOutputLevel(HRTIM_HandleTypeDef *hhrtim,

+                                                   uint32_t TimerIdx,

+                                                   uint32_t Output,

+                                                   uint32_t OutputLevel);

+

+HAL_StatusTypeDef HAL_HRTIM_TimerEventFilteringConfig(HRTIM_HandleTypeDef *hhrtim,

+                                                      uint32_t TimerIdx,

+                                                      uint32_t Event,

+                                                      HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg);

+

+HAL_StatusTypeDef HAL_HRTIM_DeadTimeConfig(HRTIM_HandleTypeDef *hhrtim,

+                                           uint32_t TimerIdx,

+                                           HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg);

+

+HAL_StatusTypeDef HAL_HRTIM_ChopperModeConfig(HRTIM_HandleTypeDef *hhrtim,

+                                              uint32_t TimerIdx,

+                                              HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg);

+

+HAL_StatusTypeDef HAL_HRTIM_BurstDMAConfig(HRTIM_HandleTypeDef *hhrtim,

+                                           uint32_t TimerIdx,

+                                           uint32_t RegistersToUpdate);

+

+

+HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart(HRTIM_HandleTypeDef *hhrtim,

+                                                 uint32_t Timers);

+

+HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop(HRTIM_HandleTypeDef *hhrtim,

+                                                 uint32_t Timers);

+

+HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_IT(HRTIM_HandleTypeDef *hhrtim,

+                                                 uint32_t Timers);

+

+HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_IT(HRTIM_HandleTypeDef *hhrtim,

+                                                 uint32_t Timers);

+

+HAL_StatusTypeDef HAL_HRTIM_WaveformCountStart_DMA(HRTIM_HandleTypeDef *hhrtim,

+                                                     uint32_t Timers);

+

+HAL_StatusTypeDef HAL_HRTIM_WaveformCountStop_DMA(HRTIM_HandleTypeDef *hhrtim,

+                                                    uint32_t Timers);

+

+HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStart(HRTIM_HandleTypeDef *hhrtim,

+                                                uint32_t OutputsToStart);

+

+HAL_StatusTypeDef HAL_HRTIM_WaveformOutputStop(HRTIM_HandleTypeDef *hhrtim,

+                                               uint32_t OutputsToStop);

+

+HAL_StatusTypeDef HAL_HRTIM_BurstModeCtl(HRTIM_HandleTypeDef *hhrtim,

+                                         uint32_t Enable);

+

+HAL_StatusTypeDef HAL_HRTIM_BurstModeSoftwareTrigger(HRTIM_HandleTypeDef *hhrtim);

+

+HAL_StatusTypeDef HAL_HRTIM_SoftwareCapture(HRTIM_HandleTypeDef *hhrtim,

+                                            uint32_t TimerIdx,

+                                            uint32_t CaptureUnit);

+

+HAL_StatusTypeDef HAL_HRTIM_SoftwareUpdate(HRTIM_HandleTypeDef *hhrtim,

+                                           uint32_t Timers);

+

+HAL_StatusTypeDef HAL_HRTIM_SoftwareReset(HRTIM_HandleTypeDef *hhrtim,

+                                          uint32_t Timers);

+

+HAL_StatusTypeDef HAL_HRTIM_BurstDMATransfer(HRTIM_HandleTypeDef *hhrtim,

+                                             uint32_t TimerIdx,

+                                             uint32_t BurstBufferAddress,

+                                             uint32_t BurstBufferLength);

+

+HAL_StatusTypeDef HAL_HRTIM_UpdateEnable(HRTIM_HandleTypeDef *hhrtim,

+                                          uint32_t Timers);

+

+HAL_StatusTypeDef HAL_HRTIM_UpdateDisable(HRTIM_HandleTypeDef *hhrtim,

+                                          uint32_t Timers);

+

+/**

+  * @}

+  */

+

+/** @addtogroup HRTIM_Exported_Functions_Group9

+* @{

+*/

+/* HRTIM peripheral state functions */

+HAL_HRTIM_StateTypeDef HAL_HRTIM_GetState(HRTIM_HandleTypeDef* hhrtim);

+

+uint32_t HAL_HRTIM_GetCapturedValue(HRTIM_HandleTypeDef * hhrtim,

+                                    uint32_t TimerIdx,

+                                    uint32_t CaptureUnit);

+

+uint32_t HAL_HRTIM_WaveformGetOutputLevel(HRTIM_HandleTypeDef *hhrtim,

+                                          uint32_t TimerIdx,

+                                          uint32_t Output);

+

+uint32_t HAL_HRTIM_WaveformGetOutputState(HRTIM_HandleTypeDef * hhrtim,

+                                          uint32_t TimerIdx,

+                                          uint32_t Output);

+

+uint32_t HAL_HRTIM_GetDelayedProtectionStatus(HRTIM_HandleTypeDef *hhrtim,

+                                              uint32_t TimerIdx,

+                                              uint32_t Output);

+

+uint32_t HAL_HRTIM_GetBurstStatus(HRTIM_HandleTypeDef *hhrtim);

+

+uint32_t HAL_HRTIM_GetCurrentPushPullStatus(HRTIM_HandleTypeDef *hhrtim,

+                                            uint32_t TimerIdx);

+

+uint32_t HAL_HRTIM_GetIdlePushPullStatus(HRTIM_HandleTypeDef *hhrtim,

+                                         uint32_t TimerIdx);

+

+/**

+  * @}

+  */

+

+/** @addtogroup HRTIM_Exported_Functions_Group10

+* @{

+*/

+/* IRQ handler */

+void HAL_HRTIM_IRQHandler(HRTIM_HandleTypeDef *hhrtim,

+                          uint32_t TimerIdx);

+

+/* HRTIM events related callback functions */

+void HAL_HRTIM_Fault1Callback(HRTIM_HandleTypeDef *hhrtim);

+void HAL_HRTIM_Fault2Callback(HRTIM_HandleTypeDef *hhrtim);

+void HAL_HRTIM_Fault3Callback(HRTIM_HandleTypeDef *hhrtim);

+void HAL_HRTIM_Fault4Callback(HRTIM_HandleTypeDef *hhrtim);

+void HAL_HRTIM_Fault5Callback(HRTIM_HandleTypeDef *hhrtim);

+void HAL_HRTIM_SystemFaultCallback(HRTIM_HandleTypeDef *hhrtim);

+void HAL_HRTIM_BurstModePeriodCallback(HRTIM_HandleTypeDef *hhrtim);

+void HAL_HRTIM_SynchronizationEventCallback(HRTIM_HandleTypeDef *hhrtim);

+

+/* Timer events related callback functions */

+void HAL_HRTIM_RegistersUpdateCallback(HRTIM_HandleTypeDef *hhrtim,

+                                              uint32_t TimerIdx);

+void HAL_HRTIM_RepetitionEventCallback(HRTIM_HandleTypeDef *hhrtim,

+                                              uint32_t TimerIdx);

+void HAL_HRTIM_Compare1EventCallback(HRTIM_HandleTypeDef *hhrtim,

+                                            uint32_t TimerIdx);

+void HAL_HRTIM_Compare2EventCallback(HRTIM_HandleTypeDef *hhrtim,

+                                            uint32_t TimerIdx);

+void HAL_HRTIM_Compare3EventCallback(HRTIM_HandleTypeDef *hhrtim,

+                                            uint32_t TimerIdx);

+void HAL_HRTIM_Compare4EventCallback(HRTIM_HandleTypeDef *hhrtim,

+                                            uint32_t TimerIdx);

+void HAL_HRTIM_Capture1EventCallback(HRTIM_HandleTypeDef *hhrtim,

+                                            uint32_t TimerIdx);

+void HAL_HRTIM_Capture2EventCallback(HRTIM_HandleTypeDef *hhrtim,

+                                            uint32_t TimerIdx);

+void HAL_HRTIM_DelayedProtectionCallback(HRTIM_HandleTypeDef *hhrtim,

+                                                uint32_t TimerIdx);

+void HAL_HRTIM_CounterResetCallback(HRTIM_HandleTypeDef *hhrtim,

+                                           uint32_t TimerIdx);

+void HAL_HRTIM_Output1SetCallback(HRTIM_HandleTypeDef *hhrtim,

+                                         uint32_t TimerIdx);

+void HAL_HRTIM_Output1ResetCallback(HRTIM_HandleTypeDef *hhrtim,

+                                           uint32_t TimerIdx);

+void HAL_HRTIM_Output2SetCallback(HRTIM_HandleTypeDef *hhrtim,

+                                         uint32_t TimerIdx);

+void HAL_HRTIM_Output2ResetCallback(HRTIM_HandleTypeDef *hhrtim,

+                                           uint32_t TimerIdx);

+void HAL_HRTIM_BurstDMATransferCallback(HRTIM_HandleTypeDef *hhrtim,

+                                               uint32_t TimerIdx);

+void HAL_HRTIM_ErrorCallback(HRTIM_HandleTypeDef *hhrtim);

+

+#if (USE_HAL_HRTIM_REGISTER_CALLBACKS == 1)

+HAL_StatusTypeDef HAL_HRTIM_RegisterCallback(HRTIM_HandleTypeDef *       hhrtim,

+                                             HAL_HRTIM_CallbackIDTypeDef CallbackID,

+                                             pHRTIM_CallbackTypeDef      pCallback);

+

+HAL_StatusTypeDef HAL_HRTIM_UnRegisterCallback(HRTIM_HandleTypeDef *       hhrtim,

+                                               HAL_HRTIM_CallbackIDTypeDef CallbackID);

+

+HAL_StatusTypeDef HAL_HRTIM_TIMxRegisterCallback(HRTIM_HandleTypeDef *        hhrtim,

+                                                 HAL_HRTIM_CallbackIDTypeDef  CallbackID,

+                                                 pHRTIM_TIMxCallbackTypeDef   pCallback);

+

+HAL_StatusTypeDef HAL_HRTIM_TIMxUnRegisterCallback(HRTIM_HandleTypeDef *       hhrtim,

+                                                   HAL_HRTIM_CallbackIDTypeDef CallbackID);

+#endif /* USE_HAL_HRTIM_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* HRTIM1 */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_HRTIM_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_hsem.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_hsem.h
new file mode 100644
index 0000000000..1ef97f3d47
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_hsem.h
@@ -0,0 +1,214 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_hsem.h

+  * @author  MCD Application Team

+  * @brief   Header file of HSEM HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_HSEM_H

+#define STM32H7xx_HAL_HSEM_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+   * @{

+   */

+

+/** @addtogroup HSEM

+   * @{

+   */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup HSEM_Exported_Macros HSEM Exported Macros

+  * @{

+  */

+

+/**

+  * @brief  SemID to mask helper Macro.

+  * @param  __SEMID__: semaphore ID from 0 to 31

+  * @retval Semaphore Mask.

+  */

+#define __HAL_HSEM_SEMID_TO_MASK(__SEMID__) (1 << (__SEMID__))

+

+/**

+  * @brief  Enables the specified HSEM interrupts.

+  * @param  __SEM_MASK__: semaphores Mask

+  * @retval None.

+  */

+#if defined(DUAL_CORE)

+#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \

+                                            (HSEM->C1IER |= (__SEM_MASK__)) : \

+                                            (HSEM->C2IER |= (__SEM_MASK__)))

+#else

+#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER |= (__SEM_MASK__))

+#endif /* DUAL_CORE */

+/**

+  * @brief  Disables the specified HSEM interrupts.

+  * @param  __SEM_MASK__: semaphores Mask

+  * @retval None.

+  */

+#if defined(DUAL_CORE)

+#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \

+                                             (HSEM->C1IER &= ~(__SEM_MASK__)) :       \

+                                             (HSEM->C2IER &= ~(__SEM_MASK__)))

+#else

+#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER &= ~(__SEM_MASK__))

+#endif /* DUAL_CORE */

+

+/**

+  * @brief  Checks whether interrupt has occurred or not for semaphores specified by a mask.

+  * @param  __SEM_MASK__: semaphores Mask

+  * @retval semaphores Mask : Semaphores where an interrupt occurred.

+  */

+#if defined(DUAL_CORE)

+#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \

+                                         ((__SEM_MASK__) & HSEM->C1MISR) :        \

+                                         ((__SEM_MASK__) & HSEM->C2MISR1))

+#else

+#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR)

+#endif /* DUAL_CORE */

+

+/**

+  * @brief  Get the semaphores release status flags.

+  * @param  __SEM_MASK__: semaphores Mask

+  * @retval semaphores Mask : Semaphores where Release flags rise.

+  */

+#if defined(DUAL_CORE)

+#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \

+                                           (__SEM_MASK__) & HSEM->C1ISR :           \

+                                           (__SEM_MASK__) & HSEM->C2ISR)

+#else

+#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR)

+#endif /* DUAL_CORE */

+

+/**

+  * @brief  Clears the HSEM Interrupt flags.

+  * @param  __SEM_MASK__: semaphores Mask

+  * @retval None.

+  */

+#if defined(DUAL_CORE)

+#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \

+                                             (HSEM->C1ICR |= (__SEM_MASK__)) :        \

+                                             (HSEM->C2ICR |= (__SEM_MASK__)))

+#else

+#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR |= (__SEM_MASK__))

+#endif /* DUAL_CORE */

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup HSEM_Exported_Functions HSEM Exported Functions

+  * @{

+  */

+

+/** @addtogroup HSEM_Exported_Functions_Group1 Take and Release functions

+  * @brief    HSEM Take and Release functions

+  * @{

+  */

+

+/* HSEM semaphore take (lock) using 2-Step  method ****************************/

+HAL_StatusTypeDef  HAL_HSEM_Take(uint32_t SemID, uint32_t ProcessID);

+/* HSEM semaphore fast take (lock) using 1-Step  method ***********************/

+HAL_StatusTypeDef  HAL_HSEM_FastTake(uint32_t SemID);

+/* HSEM Check semaphore state Taken or not   **********************************/

+uint32_t HAL_HSEM_IsSemTaken(uint32_t SemID);

+/* HSEM Release  **************************************************************/

+void  HAL_HSEM_Release(uint32_t SemID, uint32_t ProcessID);

+/* HSEM Release All************************************************************/

+void HAL_HSEM_ReleaseAll(uint32_t Key, uint32_t CoreID);

+

+/**

+  * @}

+  */

+

+/** @addtogroup HSEM_Exported_Functions_Group2 HSEM Set and Get Key functions

+  * @brief    HSEM Set and Get Key functions.

+  * @{

+  */

+/* HSEM Set Clear Key *********************************************************/

+void  HAL_HSEM_SetClearKey(uint32_t Key);

+/* HSEM Get Clear Key *********************************************************/

+uint32_t HAL_HSEM_GetClearKey(void);

+/**

+  * @}

+  */

+

+/** @addtogroup HSEM_Exported_Functions_Group3

+  * @brief   HSEM Notification functions

+  * @{

+  */

+/* HSEM Activate HSEM Notification (When a semaphore is released) ) *****************/

+void HAL_HSEM_ActivateNotification(uint32_t SemMask);

+/* HSEM Deactivate HSEM Notification (When a semaphore is released)  ****************/

+void HAL_HSEM_DeactivateNotification(uint32_t SemMask);

+/* HSEM Free Callback (When a semaphore is released)  *******************************/

+void HAL_HSEM_FreeCallback(uint32_t SemMask);

+/* HSEM IRQ Handler  **********************************************************/

+void HAL_HSEM_IRQHandler(void);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup HSEM_Private_Macros HSEM Private Macros

+  * @{

+  */

+

+#define IS_HSEM_SEMID(__SEMID__) ((__SEMID__) <= HSEM_SEMID_MAX )

+

+#define IS_HSEM_PROCESSID(__PROCESSID__) ((__PROCESSID__) <= HSEM_PROCESSID_MAX )

+

+#define IS_HSEM_KEY(__KEY__) ((__KEY__) <= HSEM_CLEAR_KEY_MAX )

+

+#if defined(DUAL_CORE)

+#define IS_HSEM_COREID(__COREID__) (((__COREID__) == HSEM_CPU1_COREID) || \

+                                    ((__COREID__) == HSEM_CPU2_COREID))

+#else

+#define IS_HSEM_COREID(__COREID__) ((__COREID__) == HSEM_CPU1_COREID)

+#endif

+

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_HSEM_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_i2c.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_i2c.h
new file mode 100644
index 0000000000..ea2cd88558
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_i2c.h
@@ -0,0 +1,782 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_i2c.h

+  * @author  MCD Application Team

+  * @brief   Header file of I2C HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_I2C_H

+#define STM32H7xx_HAL_I2C_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup I2C

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup I2C_Exported_Types I2C Exported Types

+  * @{

+  */

+

+/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition

+  * @brief  I2C Configuration Structure definition

+  * @{

+  */

+typedef struct

+{

+  uint32_t Timing;              /*!< Specifies the I2C_TIMINGR_register value.

+                                  This parameter calculated by referring to I2C initialization

+                                         section in Reference manual */

+

+  uint32_t OwnAddress1;         /*!< Specifies the first device own address.

+                                  This parameter can be a 7-bit or 10-bit address. */

+

+  uint32_t AddressingMode;      /*!< Specifies if 7-bit or 10-bit addressing mode is selected.

+                                  This parameter can be a value of @ref I2C_ADDRESSING_MODE */

+

+  uint32_t DualAddressMode;     /*!< Specifies if dual addressing mode is selected.

+                                  This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */

+

+  uint32_t OwnAddress2;         /*!< Specifies the second device own address if dual addressing mode is selected

+                                  This parameter can be a 7-bit address. */

+

+  uint32_t OwnAddress2Masks;    /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected

+                                  This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */

+

+  uint32_t GeneralCallMode;     /*!< Specifies if general call mode is selected.

+                                  This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */

+

+  uint32_t NoStretchMode;       /*!< Specifies if nostretch mode is selected.

+                                  This parameter can be a value of @ref I2C_NOSTRETCH_MODE */

+

+} I2C_InitTypeDef;

+

+/**

+  * @}

+  */

+

+/** @defgroup HAL_state_structure_definition HAL state structure definition

+  * @brief  HAL State structure definition

+  * @note  HAL I2C State value coding follow below described bitmap :\n

+  *          b7-b6  Error information\n

+  *             00 : No Error\n

+  *             01 : Abort (Abort user request on going)\n

+  *             10 : Timeout\n

+  *             11 : Error\n

+  *          b5     Peripheral initialization status\n

+  *             0  : Reset (peripheral not initialized)\n

+  *             1  : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n

+  *          b4     (not used)\n

+  *             x  : Should be set to 0\n

+  *          b3\n

+  *             0  : Ready or Busy (No Listen mode ongoing)\n

+  *             1  : Listen (peripheral in Address Listen Mode)\n

+  *          b2     Intrinsic process state\n

+  *             0  : Ready\n

+  *             1  : Busy (peripheral busy with some configuration or internal operations)\n

+  *          b1     Rx state\n

+  *             0  : Ready (no Rx operation ongoing)\n

+  *             1  : Busy (Rx operation ongoing)\n

+  *          b0     Tx state\n

+  *             0  : Ready (no Tx operation ongoing)\n

+  *             1  : Busy (Tx operation ongoing)

+  * @{

+  */

+typedef enum

+{

+  HAL_I2C_STATE_RESET             = 0x00U,   /*!< Peripheral is not yet Initialized         */

+  HAL_I2C_STATE_READY             = 0x20U,   /*!< Peripheral Initialized and ready for use  */

+  HAL_I2C_STATE_BUSY              = 0x24U,   /*!< An internal process is ongoing            */

+  HAL_I2C_STATE_BUSY_TX           = 0x21U,   /*!< Data Transmission process is ongoing      */

+  HAL_I2C_STATE_BUSY_RX           = 0x22U,   /*!< Data Reception process is ongoing         */

+  HAL_I2C_STATE_LISTEN            = 0x28U,   /*!< Address Listen Mode is ongoing            */

+  HAL_I2C_STATE_BUSY_TX_LISTEN    = 0x29U,   /*!< Address Listen Mode and Data Transmission

+                                                 process is ongoing                         */

+  HAL_I2C_STATE_BUSY_RX_LISTEN    = 0x2AU,   /*!< Address Listen Mode and Data Reception

+                                                 process is ongoing                         */

+  HAL_I2C_STATE_ABORT             = 0x60U,   /*!< Abort user request ongoing                */

+  HAL_I2C_STATE_TIMEOUT           = 0xA0U,   /*!< Timeout state                             */

+  HAL_I2C_STATE_ERROR             = 0xE0U    /*!< Error                                     */

+

+} HAL_I2C_StateTypeDef;

+

+/**

+  * @}

+  */

+

+/** @defgroup HAL_mode_structure_definition HAL mode structure definition

+  * @brief  HAL Mode structure definition

+  * @note  HAL I2C Mode value coding follow below described bitmap :\n

+  *          b7     (not used)\n

+  *             x  : Should be set to 0\n

+  *          b6\n

+  *             0  : None\n

+  *             1  : Memory (HAL I2C communication is in Memory Mode)\n

+  *          b5\n

+  *             0  : None\n

+  *             1  : Slave (HAL I2C communication is in Slave Mode)\n

+  *          b4\n

+  *             0  : None\n

+  *             1  : Master (HAL I2C communication is in Master Mode)\n

+  *          b3-b2-b1-b0  (not used)\n

+  *             xxxx : Should be set to 0000

+  * @{

+  */

+typedef enum

+{

+  HAL_I2C_MODE_NONE               = 0x00U,   /*!< No I2C communication on going             */

+  HAL_I2C_MODE_MASTER             = 0x10U,   /*!< I2C communication is in Master Mode       */

+  HAL_I2C_MODE_SLAVE              = 0x20U,   /*!< I2C communication is in Slave Mode        */

+  HAL_I2C_MODE_MEM                = 0x40U    /*!< I2C communication is in Memory Mode       */

+

+} HAL_I2C_ModeTypeDef;

+

+/**

+  * @}

+  */

+

+/** @defgroup I2C_Error_Code_definition I2C Error Code definition

+  * @brief  I2C Error Code definition

+  * @{

+  */

+#define HAL_I2C_ERROR_NONE      (0x00000000U)    /*!< No error              */

+#define HAL_I2C_ERROR_BERR      (0x00000001U)    /*!< BERR error            */

+#define HAL_I2C_ERROR_ARLO      (0x00000002U)    /*!< ARLO error            */

+#define HAL_I2C_ERROR_AF        (0x00000004U)    /*!< ACKF error            */

+#define HAL_I2C_ERROR_OVR       (0x00000008U)    /*!< OVR error             */

+#define HAL_I2C_ERROR_DMA       (0x00000010U)    /*!< DMA transfer error    */

+#define HAL_I2C_ERROR_TIMEOUT   (0x00000020U)    /*!< Timeout error         */

+#define HAL_I2C_ERROR_SIZE      (0x00000040U)    /*!< Size Management error */

+#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U)    /*!< DMA Parameter Error   */

+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)

+#define HAL_I2C_ERROR_INVALID_CALLBACK  (0x00000100U)    /*!< Invalid Callback error */

+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */

+#define HAL_I2C_ERROR_INVALID_PARAM     (0x00000200U)    /*!< Invalid Parameters error  */

+/**

+  * @}

+  */

+

+/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition

+  * @brief  I2C handle Structure definition

+  * @{

+  */

+typedef struct __I2C_HandleTypeDef

+{

+  I2C_TypeDef                *Instance;      /*!< I2C registers base address                */

+

+  I2C_InitTypeDef            Init;           /*!< I2C communication parameters              */

+

+  uint8_t                    *pBuffPtr;      /*!< Pointer to I2C transfer buffer            */

+

+  uint16_t                   XferSize;       /*!< I2C transfer size                         */

+

+  __IO uint16_t              XferCount;      /*!< I2C transfer counter                      */

+

+  __IO uint32_t              XferOptions;    /*!< I2C sequantial transfer options, this parameter can

+                                                  be a value of @ref I2C_XFEROPTIONS */

+

+  __IO uint32_t              PreviousState;  /*!< I2C communication Previous state          */

+

+  HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);  /*!< I2C transfer IRQ handler function pointer */

+

+  DMA_HandleTypeDef          *hdmatx;        /*!< I2C Tx DMA handle parameters              */

+

+  DMA_HandleTypeDef          *hdmarx;        /*!< I2C Rx DMA handle parameters              */

+

+  HAL_LockTypeDef            Lock;           /*!< I2C locking object                        */

+

+  __IO HAL_I2C_StateTypeDef  State;          /*!< I2C communication state                   */

+

+  __IO HAL_I2C_ModeTypeDef   Mode;           /*!< I2C communication mode                    */

+

+  __IO uint32_t              ErrorCode;      /*!< I2C Error code                            */

+

+  __IO uint32_t              AddrEventCount; /*!< I2C Address Event counter                 */

+

+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)

+  void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Tx Transfer completed callback */

+  void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);           /*!< I2C Master Rx Transfer completed callback */

+  void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Tx Transfer completed callback  */

+  void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);            /*!< I2C Slave Rx Transfer completed callback  */

+  void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c);             /*!< I2C Listen Complete callback              */

+  void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Tx Transfer completed callback */

+  void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Memory Rx Transfer completed callback */

+  void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c);                  /*!< I2C Error callback                        */

+  void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Abort callback                        */

+

+  void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);  /*!< I2C Slave Address Match callback */

+

+  void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c);                /*!< I2C Msp Init callback                     */

+  void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c);              /*!< I2C Msp DeInit callback                   */

+

+#endif  /* USE_HAL_I2C_REGISTER_CALLBACKS */

+} I2C_HandleTypeDef;

+

+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  HAL I2C Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_I2C_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< I2C Master Tx Transfer completed callback ID  */

+  HAL_I2C_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< I2C Master Rx Transfer completed callback ID  */

+  HAL_I2C_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< I2C Slave Tx Transfer completed callback ID   */

+  HAL_I2C_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< I2C Slave Rx Transfer completed callback ID   */

+  HAL_I2C_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< I2C Listen Complete callback ID               */

+  HAL_I2C_MEM_TX_COMPLETE_CB_ID         = 0x05U,    /*!< I2C Memory Tx Transfer callback ID            */

+  HAL_I2C_MEM_RX_COMPLETE_CB_ID         = 0x06U,    /*!< I2C Memory Rx Transfer completed callback ID  */

+  HAL_I2C_ERROR_CB_ID                   = 0x07U,    /*!< I2C Error callback ID                         */

+  HAL_I2C_ABORT_CB_ID                   = 0x08U,    /*!< I2C Abort callback ID                         */

+

+  HAL_I2C_MSPINIT_CB_ID                 = 0x09U,    /*!< I2C Msp Init callback ID                      */

+  HAL_I2C_MSPDEINIT_CB_ID               = 0x0AU     /*!< I2C Msp DeInit callback ID                    */

+

+} HAL_I2C_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL I2C Callback pointer definition

+  */

+typedef  void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); /*!< pointer to an I2C callback function */

+typedef  void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an I2C Address Match callback function */

+

+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+/* Exported constants --------------------------------------------------------*/

+

+/** @defgroup I2C_Exported_Constants I2C Exported Constants

+  * @{

+  */

+

+/** @defgroup I2C_XFEROPTIONS  I2C Sequential Transfer Options

+  * @{

+  */

+#define I2C_FIRST_FRAME                 ((uint32_t)I2C_SOFTEND_MODE)

+#define I2C_FIRST_AND_NEXT_FRAME        ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))

+#define I2C_NEXT_FRAME                  ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))

+#define I2C_FIRST_AND_LAST_FRAME        ((uint32_t)I2C_AUTOEND_MODE)

+#define I2C_LAST_FRAME                  ((uint32_t)I2C_AUTOEND_MODE)

+#define I2C_LAST_FRAME_NO_STOP          ((uint32_t)I2C_SOFTEND_MODE)

+

+/* List of XferOptions in usage of :

+ * 1- Restart condition in all use cases (direction change or not)

+ */

+#define  I2C_OTHER_FRAME                (0x000000AAU)

+#define  I2C_OTHER_AND_LAST_FRAME       (0x0000AA00U)

+/**

+  * @}

+  */

+

+/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode

+  * @{

+  */

+#define I2C_ADDRESSINGMODE_7BIT         (0x00000001U)

+#define I2C_ADDRESSINGMODE_10BIT        (0x00000002U)

+/**

+  * @}

+  */

+

+/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode

+  * @{

+  */

+#define I2C_DUALADDRESS_DISABLE         (0x00000000U)

+#define I2C_DUALADDRESS_ENABLE          I2C_OAR2_OA2EN

+/**

+  * @}

+  */

+

+/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks

+  * @{

+  */

+#define I2C_OA2_NOMASK                  ((uint8_t)0x00U)

+#define I2C_OA2_MASK01                  ((uint8_t)0x01U)

+#define I2C_OA2_MASK02                  ((uint8_t)0x02U)

+#define I2C_OA2_MASK03                  ((uint8_t)0x03U)

+#define I2C_OA2_MASK04                  ((uint8_t)0x04U)

+#define I2C_OA2_MASK05                  ((uint8_t)0x05U)

+#define I2C_OA2_MASK06                  ((uint8_t)0x06U)

+#define I2C_OA2_MASK07                  ((uint8_t)0x07U)

+/**

+  * @}

+  */

+

+/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode

+  * @{

+  */

+#define I2C_GENERALCALL_DISABLE         (0x00000000U)

+#define I2C_GENERALCALL_ENABLE          I2C_CR1_GCEN

+/**

+  * @}

+  */

+

+/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode

+  * @{

+  */

+#define I2C_NOSTRETCH_DISABLE           (0x00000000U)

+#define I2C_NOSTRETCH_ENABLE            I2C_CR1_NOSTRETCH

+/**

+  * @}

+  */

+

+/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size

+  * @{

+  */

+#define I2C_MEMADD_SIZE_8BIT            (0x00000001U)

+#define I2C_MEMADD_SIZE_16BIT           (0x00000002U)

+/**

+  * @}

+  */

+

+/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View

+  * @{

+  */

+#define I2C_DIRECTION_TRANSMIT          (0x00000000U)

+#define I2C_DIRECTION_RECEIVE           (0x00000001U)

+/**

+  * @}

+  */

+

+/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode

+  * @{

+  */

+#define  I2C_RELOAD_MODE                I2C_CR2_RELOAD

+#define  I2C_AUTOEND_MODE               I2C_CR2_AUTOEND

+#define  I2C_SOFTEND_MODE               (0x00000000U)

+/**

+  * @}

+  */

+

+/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode

+  * @{

+  */

+#define  I2C_NO_STARTSTOP               (0x00000000U)

+#define  I2C_GENERATE_STOP              (uint32_t)(0x80000000U | I2C_CR2_STOP)

+#define  I2C_GENERATE_START_READ        (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)

+#define  I2C_GENERATE_START_WRITE       (uint32_t)(0x80000000U | I2C_CR2_START)

+/**

+  * @}

+  */

+

+/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition

+  * @brief I2C Interrupt definition

+  *        Elements values convention: 0xXXXXXXXX

+  *           - XXXXXXXX  : Interrupt control mask

+  * @{

+  */

+#define I2C_IT_ERRI                     I2C_CR1_ERRIE

+#define I2C_IT_TCI                      I2C_CR1_TCIE

+#define I2C_IT_STOPI                    I2C_CR1_STOPIE

+#define I2C_IT_NACKI                    I2C_CR1_NACKIE

+#define I2C_IT_ADDRI                    I2C_CR1_ADDRIE

+#define I2C_IT_RXI                      I2C_CR1_RXIE

+#define I2C_IT_TXI                      I2C_CR1_TXIE

+/**

+  * @}

+  */

+

+/** @defgroup I2C_Flag_definition I2C Flag definition

+  * @{

+  */

+#define I2C_FLAG_TXE                    I2C_ISR_TXE

+#define I2C_FLAG_TXIS                   I2C_ISR_TXIS

+#define I2C_FLAG_RXNE                   I2C_ISR_RXNE

+#define I2C_FLAG_ADDR                   I2C_ISR_ADDR

+#define I2C_FLAG_AF                     I2C_ISR_NACKF

+#define I2C_FLAG_STOPF                  I2C_ISR_STOPF

+#define I2C_FLAG_TC                     I2C_ISR_TC

+#define I2C_FLAG_TCR                    I2C_ISR_TCR

+#define I2C_FLAG_BERR                   I2C_ISR_BERR

+#define I2C_FLAG_ARLO                   I2C_ISR_ARLO

+#define I2C_FLAG_OVR                    I2C_ISR_OVR

+#define I2C_FLAG_PECERR                 I2C_ISR_PECERR

+#define I2C_FLAG_TIMEOUT                I2C_ISR_TIMEOUT

+#define I2C_FLAG_ALERT                  I2C_ISR_ALERT

+#define I2C_FLAG_BUSY                   I2C_ISR_BUSY

+#define I2C_FLAG_DIR                    I2C_ISR_DIR

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macros -----------------------------------------------------------*/

+

+/** @defgroup I2C_Exported_Macros I2C Exported Macros

+  * @{

+  */

+

+/** @brief Reset I2C handle state.

+  * @param  __HANDLE__ specifies the I2C Handle.

+  * @retval None

+  */

+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)

+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                do{                                                   \

+                                                                    (__HANDLE__)->State = HAL_I2C_STATE_RESET;       \

+                                                                    (__HANDLE__)->MspInitCallback = NULL;            \

+                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \

+                                                                  } while(0)

+#else

+#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__)                ((__HANDLE__)->State = HAL_I2C_STATE_RESET)

+#endif

+

+/** @brief  Enable the specified I2C interrupt.

+  * @param  __HANDLE__ specifies the I2C Handle.

+  * @param  __INTERRUPT__ specifies the interrupt source to enable.

+  *        This parameter can be one of the following values:

+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable

+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable

+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable

+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable

+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable

+  *            @arg @ref I2C_IT_RXI   RX interrupt enable

+  *            @arg @ref I2C_IT_TXI   TX interrupt enable

+  *

+  * @retval None

+  */

+#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))

+

+/** @brief  Disable the specified I2C interrupt.

+  * @param  __HANDLE__ specifies the I2C Handle.

+  * @param  __INTERRUPT__ specifies the interrupt source to disable.

+  *        This parameter can be one of the following values:

+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable

+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable

+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable

+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable

+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable

+  *            @arg @ref I2C_IT_RXI   RX interrupt enable

+  *            @arg @ref I2C_IT_TXI   TX interrupt enable

+  *

+  * @retval None

+  */

+#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))

+

+/** @brief  Check whether the specified I2C interrupt source is enabled or not.

+  * @param  __HANDLE__ specifies the I2C Handle.

+  * @param  __INTERRUPT__ specifies the I2C interrupt source to check.

+  *          This parameter can be one of the following values:

+  *            @arg @ref I2C_IT_ERRI  Errors interrupt enable

+  *            @arg @ref I2C_IT_TCI   Transfer complete interrupt enable

+  *            @arg @ref I2C_IT_STOPI STOP detection interrupt enable

+  *            @arg @ref I2C_IT_NACKI NACK received interrupt enable

+  *            @arg @ref I2C_IT_ADDRI Address match interrupt enable

+  *            @arg @ref I2C_IT_RXI   RX interrupt enable

+  *            @arg @ref I2C_IT_TXI   TX interrupt enable

+  *

+  * @retval The new state of __INTERRUPT__ (SET or RESET).

+  */

+#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

+

+/** @brief  Check whether the specified I2C flag is set or not.

+  * @param  __HANDLE__ specifies the I2C Handle.

+  * @param  __FLAG__ specifies the flag to check.

+  *        This parameter can be one of the following values:

+  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty

+  *            @arg @ref I2C_FLAG_TXIS    Transmit interrupt status

+  *            @arg @ref I2C_FLAG_RXNE    Receive data register not empty

+  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)

+  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag

+  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag

+  *            @arg @ref I2C_FLAG_TC      Transfer complete (master mode)

+  *            @arg @ref I2C_FLAG_TCR     Transfer complete reload

+  *            @arg @ref I2C_FLAG_BERR    Bus error

+  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost

+  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun

+  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception

+  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag

+  *            @arg @ref I2C_FLAG_ALERT   SMBus alert

+  *            @arg @ref I2C_FLAG_BUSY    Bus busy

+  *            @arg @ref I2C_FLAG_DIR     Transfer direction (slave mode)

+  *

+  * @retval The new state of __FLAG__ (SET or RESET).

+  */

+#define I2C_FLAG_MASK  (0x0001FFFFU)

+#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)

+

+/** @brief  Clear the I2C pending flags which are cleared by writing 1 in a specific bit.

+  * @param  __HANDLE__ specifies the I2C Handle.

+  * @param  __FLAG__ specifies the flag to clear.

+  *          This parameter can be any combination of the following values:

+  *            @arg @ref I2C_FLAG_TXE     Transmit data register empty

+  *            @arg @ref I2C_FLAG_ADDR    Address matched (slave mode)

+  *            @arg @ref I2C_FLAG_AF      Acknowledge failure received flag

+  *            @arg @ref I2C_FLAG_STOPF   STOP detection flag

+  *            @arg @ref I2C_FLAG_BERR    Bus error

+  *            @arg @ref I2C_FLAG_ARLO    Arbitration lost

+  *            @arg @ref I2C_FLAG_OVR     Overrun/Underrun

+  *            @arg @ref I2C_FLAG_PECERR  PEC error in reception

+  *            @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag

+  *            @arg @ref I2C_FLAG_ALERT   SMBus alert

+  *

+  * @retval None

+  */

+#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \

+                                                                                 : ((__HANDLE__)->Instance->ICR = (__FLAG__)))

+

+/** @brief  Enable the specified I2C peripheral.

+  * @param  __HANDLE__ specifies the I2C Handle.

+  * @retval None

+  */

+#define __HAL_I2C_ENABLE(__HANDLE__)                            (SET_BIT((__HANDLE__)->Instance->CR1,  I2C_CR1_PE))

+

+/** @brief  Disable the specified I2C peripheral.

+  * @param  __HANDLE__ specifies the I2C Handle.

+  * @retval None

+  */

+#define __HAL_I2C_DISABLE(__HANDLE__)                           (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

+

+/** @brief  Generate a Non-Acknowledge I2C peripheral in Slave mode.

+  * @param  __HANDLE__ specifies the I2C Handle.

+  * @retval None

+  */

+#define __HAL_I2C_GENERATE_NACK(__HANDLE__)                     (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))

+/**

+  * @}

+  */

+

+/* Include I2C HAL Extended module */

+#include "stm32h7xx_hal_i2c_ex.h"

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup I2C_Exported_Functions

+  * @{

+  */

+

+/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions

+  * @{

+  */

+/* Initialization and de-initialization functions******************************/

+HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);

+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);

+void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);

+void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);

+

+/* Callbacks Register/UnRegister functions  ***********************************/

+#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1)

+HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, pI2C_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID);

+

+HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c);

+#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions

+  * @{

+  */

+/* IO operation functions  ****************************************************/

+/******* Blocking mode: Polling */

+HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);

+HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);

+HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);

+HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);

+HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);

+HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);

+HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);

+

+/******* Non-Blocking mode: Interrupt */

+HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);

+

+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);

+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);

+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);

+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);

+HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);

+HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);

+HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);

+

+/******* Non-Blocking mode: DMA */

+HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);

+

+HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);

+HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);

+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);

+HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);

+/**

+  * @}

+  */

+

+/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks

+ * @{

+ */

+/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */

+void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);

+void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);

+void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);

+void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);

+void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);

+void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);

+void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);

+void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);

+void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);

+void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);

+void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);

+void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);

+/**

+  * @}

+  */

+

+/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions

+  * @{

+  */

+/* Peripheral State, Mode and Error functions  *********************************/

+HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);

+HAL_I2C_ModeTypeDef  HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);

+uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup I2C_Private_Constants I2C Private Constants

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup I2C_Private_Macro I2C Private Macros

+  * @{

+  */

+

+#define IS_I2C_ADDRESSING_MODE(MODE)    (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \

+                                         ((MODE) == I2C_ADDRESSINGMODE_10BIT))

+

+#define IS_I2C_DUAL_ADDRESS(ADDRESS)    (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \

+                                         ((ADDRESS) == I2C_DUALADDRESS_ENABLE))

+

+#define IS_I2C_OWN_ADDRESS2_MASK(MASK)  (((MASK) == I2C_OA2_NOMASK)  || \

+                                         ((MASK) == I2C_OA2_MASK01) || \

+                                         ((MASK) == I2C_OA2_MASK02) || \

+                                         ((MASK) == I2C_OA2_MASK03) || \

+                                         ((MASK) == I2C_OA2_MASK04) || \

+                                         ((MASK) == I2C_OA2_MASK05) || \

+                                         ((MASK) == I2C_OA2_MASK06) || \

+                                         ((MASK) == I2C_OA2_MASK07))

+

+#define IS_I2C_GENERAL_CALL(CALL)       (((CALL) == I2C_GENERALCALL_DISABLE) || \

+                                         ((CALL) == I2C_GENERALCALL_ENABLE))

+

+#define IS_I2C_NO_STRETCH(STRETCH)      (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \

+                                         ((STRETCH) == I2C_NOSTRETCH_ENABLE))

+

+#define IS_I2C_MEMADD_SIZE(SIZE)        (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \

+                                         ((SIZE) == I2C_MEMADD_SIZE_16BIT))

+

+#define IS_TRANSFER_MODE(MODE)          (((MODE) == I2C_RELOAD_MODE)   || \

+                                         ((MODE) == I2C_AUTOEND_MODE) || \

+                                         ((MODE) == I2C_SOFTEND_MODE))

+

+#define IS_TRANSFER_REQUEST(REQUEST)    (((REQUEST) == I2C_GENERATE_STOP)        || \

+                                         ((REQUEST) == I2C_GENERATE_START_READ)  || \

+                                         ((REQUEST) == I2C_GENERATE_START_WRITE) || \

+                                         ((REQUEST) == I2C_NO_STARTSTOP))

+

+#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST)  (((REQUEST) == I2C_FIRST_FRAME)          || \

+                                                   ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \

+                                                   ((REQUEST) == I2C_NEXT_FRAME)           || \

+                                                   ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \

+                                                   ((REQUEST) == I2C_LAST_FRAME)           || \

+                                                   ((REQUEST) == I2C_LAST_FRAME_NO_STOP)   || \

+                                                   IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))

+

+#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME)     || \

+                                                        ((REQUEST) == I2C_OTHER_AND_LAST_FRAME))

+

+#define I2C_RESET_CR2(__HANDLE__)                 ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))

+

+#define I2C_GET_ADDR_MATCH(__HANDLE__)            ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16U))

+#define I2C_GET_DIR(__HANDLE__)                   ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U))

+#define I2C_GET_STOP_MODE(__HANDLE__)             ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)

+#define I2C_GET_OWN_ADDRESS1(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1))

+#define I2C_GET_OWN_ADDRESS2(__HANDLE__)          ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2))

+

+#define IS_I2C_OWN_ADDRESS1(ADDRESS1)             ((ADDRESS1) <= 0x000003FFU)

+#define IS_I2C_OWN_ADDRESS2(ADDRESS2)             ((ADDRESS2) <= (uint16_t)0x00FFU)

+

+#define I2C_MEM_ADD_MSB(__ADDRESS__)              ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00U))) >> 8U)))

+#define I2C_MEM_ADD_LSB(__ADDRESS__)              ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU))))

+

+#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \

+                                                          (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))

+

+#define I2C_CHECK_FLAG(__ISR__, __FLAG__)         ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)

+#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__)      ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)

+/**

+  * @}

+  */

+

+/* Private Functions ---------------------------------------------------------*/

+/** @defgroup I2C_Private_Functions I2C Private Functions

+  * @{

+  */

+/* Private functions are defined in stm32h7xx_hal_i2c.c file */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+

+#endif /* STM32H7xx_HAL_I2C_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_i2c_ex.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_i2c_ex.h
new file mode 100644
index 0000000000..bf89420b99
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_i2c_ex.h
@@ -0,0 +1,181 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_i2c_ex.h

+  * @author  MCD Application Team

+  * @brief   Header file of I2C HAL Extended module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_I2C_EX_H

+#define STM32H7xx_HAL_I2C_EX_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup I2CEx

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/* Exported constants --------------------------------------------------------*/

+

+/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants

+  * @{

+  */

+

+/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter

+  * @{

+  */

+#define I2C_ANALOGFILTER_ENABLE         0x00000000U

+#define I2C_ANALOGFILTER_DISABLE        I2C_CR1_ANFOFF

+/**

+  * @}

+  */

+

+/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus

+  * @{

+  */

+#define I2C_FASTMODEPLUS_PB6            SYSCFG_PMCR_I2C_PB6_FMP                        /*!< Enable Fast Mode Plus on PB6       */

+#define I2C_FASTMODEPLUS_PB7            SYSCFG_PMCR_I2C_PB7_FMP                        /*!< Enable Fast Mode Plus on PB7       */

+#define I2C_FASTMODEPLUS_PB8            SYSCFG_PMCR_I2C_PB8_FMP                        /*!< Enable Fast Mode Plus on PB8       */

+#define I2C_FASTMODEPLUS_PB9            SYSCFG_PMCR_I2C_PB9_FMP                        /*!< Enable Fast Mode Plus on PB9       */

+#define I2C_FASTMODEPLUS_I2C1           SYSCFG_PMCR_I2C1_FMP                           /*!< Enable Fast Mode Plus on I2C1 pins */

+#define I2C_FASTMODEPLUS_I2C2           SYSCFG_PMCR_I2C2_FMP                           /*!< Enable Fast Mode Plus on I2C2 pins */

+#define I2C_FASTMODEPLUS_I2C3           SYSCFG_PMCR_I2C3_FMP                           /*!< Enable Fast Mode Plus on I2C3 pins */

+#define I2C_FASTMODEPLUS_I2C4           SYSCFG_PMCR_I2C4_FMP                           /*!< Enable Fast Mode Plus on I2C4 pins */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/* Exported functions --------------------------------------------------------*/

+

+/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions

+  * @{

+  */

+

+/** @addtogroup I2CEx_Exported_Functions_Group1 Extended features functions

+  * @brief    Extended features functions

+  * @{

+  */

+

+/* Peripheral Control functions  ************************************************/

+HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);

+HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);

+HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c);

+HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c);

+void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);

+void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);

+

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros

+  * @{

+  */

+#define IS_I2C_ANALOG_FILTER(FILTER)    (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \

+                                          ((FILTER) == I2C_ANALOGFILTER_DISABLE))

+

+#define IS_I2C_DIGITAL_FILTER(FILTER)   ((FILTER) <= 0x0000000FU)

+

+#if (defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) && defined(SYSCFG_PMCR_I2C3_FMP) && defined(SYSCFG_PMCR_I2C4_FMP))

+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \

+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \

+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \

+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \

+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \

+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \

+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \

+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4))

+#elif defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP) && defined(SYSCFG_PMCR_I2C3_FMP)

+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \

+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \

+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \

+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \

+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \

+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \

+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3))

+#elif defined(SYSCFG_PMCR_I2C1_FMP) && defined(SYSCFG_PMCR_I2C2_FMP)

+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \

+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \

+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \

+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \

+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \

+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2))

+#elif defined(SYSCFG_PMCR_I2C1_FMP)

+#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6)  == I2C_FASTMODEPLUS_PB6)  || \

+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB7)  == I2C_FASTMODEPLUS_PB7)  || \

+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB8)  == I2C_FASTMODEPLUS_PB8)  || \

+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_PB9)  == I2C_FASTMODEPLUS_PB9)  || \

+                                         (((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1))

+#endif /* SYSCFG_PMCR_I2C1_FMP && SYSCFG_PMCR_I2C2_FMP && SYSCFG_PMCR_I2C3_FMP && SYSCFG_PMCR_I2C4_FMP */

+

+

+

+/**

+  * @}

+  */

+

+/* Private Functions ---------------------------------------------------------*/

+/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions

+  * @{

+  */

+/* Private functions are defined in stm32h7xx_hal_i2c_ex.c file */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_I2C_EX_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_i2s.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_i2s.h
new file mode 100644
index 0000000000..de19b9f6c5
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_i2s.h
@@ -0,0 +1,631 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_i2s.h

+  * @author  MCD Application Team

+  * @brief   Header file of I2S HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_I2S_H

+#define STM32H7xx_HAL_I2S_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup I2S

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup I2S_Exported_Types I2S Exported Types

+  * @{

+  */

+

+/**

+  * @brief I2S Init structure definition

+  */

+typedef struct

+{

+  uint32_t Mode;                /*!< Specifies the I2S operating mode.

+                                     This parameter can be a value of @ref I2S_Mode */

+

+  uint32_t Standard;            /*!< Specifies the standard used for the I2S communication.

+                                     This parameter can be a value of @ref I2S_Standard */

+

+  uint32_t DataFormat;          /*!< Specifies the data format for the I2S communication.

+                                     This parameter can be a value of @ref I2S_Data_Format */

+

+  uint32_t MCLKOutput;          /*!< Specifies whether the I2S MCLK output is enabled or not.

+                                     This parameter can be a value of @ref I2S_MCLK_Output */

+

+  uint32_t AudioFreq;           /*!< Specifies the frequency selected for the I2S communication.

+                                     This parameter can be a value of @ref I2S_Audio_Frequency */

+

+  uint32_t CPOL;                /*!< Specifies the idle state of the I2S clock.

+                                     This parameter can be a value of @ref I2S_Clock_Polarity */

+

+  uint32_t FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.

+                                     This parameter can be a value of @ref I2S_MSB_LSB_transmission       */

+

+  uint32_t WSInversion;         /*!< Control the Word Select Inversion.

+                                     This parameter can be a value of @ref I2S_WSInversion                */

+

+  uint32_t Data24BitAlignment;  /*!< Specifies the Data Padding for 24 bits data length

+                                      This parameter can be a value of @ref I2S_Data_24Bit_Alignment       */

+

+  uint32_t MasterKeepIOState;   /*!< Control of Alternate function GPIOs state

+                                     This parameter can be a value of @ref SPI_Master_Keep_IO_State */

+

+} I2S_InitTypeDef;

+

+/**

+  * @brief  HAL State structures definition

+  */

+typedef enum

+{

+  HAL_I2S_STATE_RESET      = 0x00UL,  /*!< I2S not yet initialized or disabled                */

+  HAL_I2S_STATE_READY      = 0x01UL,  /*!< I2S initialized and ready for use                  */

+  HAL_I2S_STATE_BUSY       = 0x02UL,  /*!< I2S internal process is ongoing                    */

+  HAL_I2S_STATE_BUSY_TX    = 0x03UL,  /*!< Data Transmission process is ongoing               */

+  HAL_I2S_STATE_BUSY_RX    = 0x04UL,  /*!< Data Reception process is ongoing                  */

+  HAL_I2S_STATE_TIMEOUT    = 0x06UL,  /*!< I2S timeout state                                  */

+  HAL_I2S_STATE_ERROR      = 0x07UL   /*!< I2S error state                                    */

+} HAL_I2S_StateTypeDef;

+

+/**

+  * @brief I2S handle Structure definition

+  */

+typedef struct __I2S_HandleTypeDef

+{

+  SPI_TypeDef                *Instance;            /*!< I2S registers base address */

+                                                   

+  I2S_InitTypeDef            Init;                 /*!< I2S communication parameters */

+                                                   

+  uint16_t                   *pTxBuffPtr;          /*!< Pointer to I2S Tx transfer buffer */

+                                                   

+  __IO uint16_t              TxXferSize;           /*!< I2S Tx transfer size */

+                                                   

+  __IO uint16_t              TxXferCount;          /*!< I2S Tx transfer Counter */

+                                                   

+  uint16_t                   *pRxBuffPtr;          /*!< Pointer to I2S Rx transfer buffer */

+                                                   

+  __IO uint16_t              RxXferSize;           /*!< I2S Rx transfer size */

+                                                   

+  __IO uint16_t              RxXferCount;          /*!< I2S Rx transfer counter

+                                                      (This field is initialized at the

+                                                       same value as transfer size at the

+                                                       beginning of the transfer and

+                                                       decremented when a sample is received

+                                                       NbSamplesReceived = RxBufferSize-RxBufferCount) */

+                                                       

+  void (*RxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Rx ISR */

+

+  void (*TxISR)(struct __I2S_HandleTypeDef *hi2s); /*!< function pointer on Tx ISR */

+  

+  DMA_HandleTypeDef          *hdmatx;              /*!< I2S Tx DMA handle parameters */

+                                                   

+  DMA_HandleTypeDef          *hdmarx;              /*!< I2S Rx DMA handle parameters */

+                                                   

+  __IO HAL_LockTypeDef       Lock;                 /*!< I2S locking object */

+                                                   

+  __IO HAL_I2S_StateTypeDef  State;                /*!< I2S communication state */

+                                                   

+  __IO uint32_t              ErrorCode;            /*!< I2S Error code

+                                                        This parameter can be a value of @ref I2S_Error */

+

+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1U)

+  void (* TxCpltCallback)(struct __I2S_HandleTypeDef *hi2s);             /*!< I2S Tx Completed callback          */

+  void (* RxCpltCallback)(struct __I2S_HandleTypeDef *hi2s);             /*!< I2S Rx Completed callback          */

+  void (* TxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s);         /*!< I2S Tx Half Completed callback     */

+  void (* RxHalfCpltCallback)(struct __I2S_HandleTypeDef *hi2s);         /*!< I2S Rx Half Completed callback     */

+  void (* ErrorCallback)(struct __I2S_HandleTypeDef *hi2s);              /*!< I2S Error callback                 */

+  void (* MspInitCallback)(struct __I2S_HandleTypeDef *hi2s);            /*!< I2S Msp Init callback              */

+  void (* MspDeInitCallback)(struct __I2S_HandleTypeDef *hi2s);          /*!< I2S Msp DeInit callback            */

+

+#endif  /* USE_HAL_I2S_REGISTER_CALLBACKS */

+} I2S_HandleTypeDef;

+

+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)

+/**

+

+  * @brief  HAL I2S Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_I2S_TX_COMPLETE_CB_ID             = 0x00UL,    /*!< I2S Tx Completed callback ID         */

+  HAL_I2S_RX_COMPLETE_CB_ID             = 0x01UL,    /*!< I2S Rx Completed callback ID         */

+  HAL_I2S_TX_HALF_COMPLETE_CB_ID        = 0x03UL,    /*!< I2S Tx Half Completed callback ID    */

+  HAL_I2S_RX_HALF_COMPLETE_CB_ID        = 0x04UL,    /*!< I2S Rx Half Completed callback ID    */

+  HAL_I2S_ERROR_CB_ID                   = 0x06UL,    /*!< I2S Error callback ID                */

+  HAL_I2S_MSPINIT_CB_ID                 = 0x07UL,    /*!< I2S Msp Init callback ID             */

+  HAL_I2S_MSPDEINIT_CB_ID               = 0x08UL     /*!< I2S Msp DeInit callback ID           */

+

+} HAL_I2S_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL I2S Callback pointer definition

+  */

+typedef  void (*pI2S_CallbackTypeDef)(I2S_HandleTypeDef *hi2s); /*!< pointer to an I2S callback function */

+

+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup I2S_Exported_Constants I2S Exported Constants

+  * @{

+  */

+/** @defgroup I2S_Error I2S Error

+  * @{

+  */ 

+#define HAL_I2S_ERROR_NONE               (0x00000000UL)  /*!< No error                          */

+#define HAL_I2S_ERROR_TIMEOUT            (0x00000001UL)  /*!< Timeout error                     */

+#define HAL_I2S_ERROR_OVR                (0x00000002UL)  /*!< OVR error                         */

+#define HAL_I2S_ERROR_UDR                (0x00000004UL)  /*!< UDR error                         */

+#define HAL_I2S_ERROR_DMA                (0x00000008UL)  /*!< DMA transfer error                */

+#define HAL_I2S_ERROR_PRESCALER          (0x00000010UL)  /*!< Prescaler Calculation error       */

+#define HAL_I2S_ERROR_FRE                (0x00000020UL)  /*!< FRE error                         */

+#define HAL_I2S_ERROR_NO_OGT             (0x00000040UL)  /*!< No On Going Transfer error        */

+#define HAL_I2S_ERROR_NOT_SUPPORTED      (0x00000080UL)  /*!< Requested operation not supported */

+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)

+#define HAL_I2S_ERROR_INVALID_CALLBACK   (0x00000100UL)  /*!< Invalid Callback error      */

+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/** @defgroup I2S_Mode I2S Mode

+  * @{

+  */

+#define I2S_MODE_SLAVE_TX                (0x00000000UL)

+#define I2S_MODE_SLAVE_RX                (SPI_I2SCFGR_I2SCFG_0)

+#define I2S_MODE_MASTER_TX               (SPI_I2SCFGR_I2SCFG_1)

+#define I2S_MODE_MASTER_RX               (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1)

+#define I2S_MODE_SLAVE_FULLDUPLEX        (SPI_I2SCFGR_I2SCFG_2)

+#define I2S_MODE_MASTER_FULLDUPLEX       (SPI_I2SCFGR_I2SCFG_2 | SPI_I2SCFGR_I2SCFG_0)

+/**

+  * @}

+  */

+

+/** @defgroup I2S_Standard I2S Standard

+  * @{

+  */

+#define I2S_STANDARD_PHILIPS             (0x00000000UL)

+#define I2S_STANDARD_MSB                 (SPI_I2SCFGR_I2SSTD_0)

+#define I2S_STANDARD_LSB                 (SPI_I2SCFGR_I2SSTD_1)

+#define I2S_STANDARD_PCM_SHORT           (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)

+#define I2S_STANDARD_PCM_LONG            (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)

+/**

+  * @}

+  */

+

+/** @defgroup I2S_Data_Format I2S Data Format

+  * @{

+  */

+#define I2S_DATAFORMAT_16B               (0x00000000UL)

+#define I2S_DATAFORMAT_16B_EXTENDED      (SPI_I2SCFGR_CHLEN)

+#define I2S_DATAFORMAT_24B               (SPI_I2SCFGR_DATLEN_0)

+#define I2S_DATAFORMAT_32B               (SPI_I2SCFGR_DATLEN_1)

+/**

+  * @}

+  */

+

+/** @defgroup I2S_MCLK_Output I2S MCLK Output

+  * @{

+  */

+#define I2S_MCLKOUTPUT_ENABLE            (SPI_I2SCFGR_MCKOE)

+#define I2S_MCLKOUTPUT_DISABLE           (0x00000000UL)

+/**

+  * @}

+  */

+

+/** @defgroup I2S_Audio_Frequency I2S Audio Frequency

+  * @{

+  */

+#define I2S_AUDIOFREQ_192K               (192000UL)

+#define I2S_AUDIOFREQ_96K                (96000UL)

+#define I2S_AUDIOFREQ_48K                (48000UL)

+#define I2S_AUDIOFREQ_44K                (44100UL)

+#define I2S_AUDIOFREQ_32K                (32000UL)

+#define I2S_AUDIOFREQ_22K                (22050UL)

+#define I2S_AUDIOFREQ_16K                (16000UL)

+#define I2S_AUDIOFREQ_11K                (11025UL)

+#define I2S_AUDIOFREQ_8K                 (8000UL)

+#define I2S_AUDIOFREQ_DEFAULT            (2UL)

+/**

+  * @}

+  */

+

+/** @defgroup I2S_FullDuplex_Mode I2S FullDuplex Mode

+  * @{

+  */

+#define I2S_CPOL_LOW                     (0x00000000UL)

+#define I2S_CPOL_HIGH                    (SPI_I2SCFGR_CKPOL)

+/**

+  * @}

+  */

+

+/** @defgroup I2S_MSB_LSB_Transmission I2S MSB LSB Transmission

+  * @{

+  */

+#define I2S_FIRSTBIT_MSB                 (0x00000000UL)

+#define I2S_FIRSTBIT_LSB                 SPI_CFG2_LSBFRST

+/**

+  * @}

+  */

+

+/** @defgroup I2S_WSInversion I2S Word Select Inversion

+  * @{

+  */

+#define I2S_WS_INVERSION_DISABLE         (0x00000000UL)

+#define I2S_WS_INVERSION_ENABLE          SPI_I2SCFGR_WSINV

+/**

+  * @}

+  */

+

+/** @defgroup I2S_Data_24Bit_Alignment Data Padding 24Bit

+  * @{

+  */

+#define I2S_DATA_24BIT_ALIGNMENT_RIGHT   (0x00000000UL)

+#define I2S_DATA_24BIT_ALIGNMENT_LEFT    SPI_I2SCFGR_DATFMT

+/**

+  * @}

+  */

+

+/** @defgroup I2S_Master_Keep_IO_State Keep IO State

+  * @{

+  */

+#define I2S_MASTER_KEEP_IO_STATE_DISABLE (0x00000000U)

+#define I2S_MASTER_KEEP_IO_STATE_ENABLE  SPI_CFG2_AFCNTR

+/**

+  * @}

+  */

+

+/** @defgroup I2S_Interrupts_Definition I2S Interrupts Definition

+  * @{

+  */

+#define I2S_IT_RXP                       SPI_IER_RXPIE

+#define I2S_IT_TXP                       SPI_IER_TXPIE

+#define I2S_IT_UDR                       SPI_IER_UDRIE

+#define I2S_IT_OVR                       SPI_IER_OVRIE

+#define I2S_IT_FRE                       SPI_IER_TIFREIE

+#define I2S_IT_ERR                       (SPI_IER_UDRIE | SPI_IER_OVRIE | SPI_IER_TIFREIE)

+/**

+  * @}

+  */

+

+/** @defgroup I2S_Flags_Definition I2S Flags Definition

+  * @{

+  */

+#define I2S_FLAG_RXP                     SPI_SR_RXP       /* I2S status flag : Rx-Packet available flag                 */

+#define I2S_FLAG_TXP                     SPI_SR_TXP       /* I2S status flag : Tx-Packet space available flag           */

+#define I2S_FLAG_UDR                     SPI_SR_UDR       /* I2S Error flag  : Underrun flag                            */

+#define I2S_FLAG_OVR                     SPI_SR_OVR       /* I2S Error flag  : Overrun flag                             */

+#define I2S_FLAG_FRE                     SPI_SR_TIFRE     /* I2S Error flag  : TI mode frame format error flag          */

+

+#define I2S_FLAG_MASK                    (SPI_SR_RXP | SPI_SR_TXP | SPI_SR_UDR | SPI_SR_OVR | SPI_SR_TIFRE)

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macros -----------------------------------------------------------*/

+/** @defgroup I2S_Exported_macros I2S Exported Macros

+  * @{

+  */

+

+/** @brief  Reset I2S handle state

+  * @param  __HANDLE__ specifies the I2S Handle.

+  * @retval None

+  */

+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)

+#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__)                do{                                                  \

+                                                                    (__HANDLE__)->State = HAL_I2S_STATE_RESET;       \

+                                                                    (__HANDLE__)->MspInitCallback = NULL;            \

+                                                                    (__HANDLE__)->MspDeInitCallback = NULL;          \

+                                                                  } while(0)

+#else

+#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)

+#endif

+

+/** @brief  Enable the specified SPI peripheral (in I2S mode).

+  * @param  __HANDLE__ specifies the I2S Handle.

+  * @retval None

+  */

+#define __HAL_I2S_ENABLE(__HANDLE__)    (SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE))

+

+/** @brief  Disable the specified SPI peripheral (in I2S mode).

+  * @param  __HANDLE__ specifies the I2S Handle.

+  * @retval None

+  */

+#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE))

+

+/** @brief  Enable the specified I2S interrupts.

+  * @param  __HANDLE__ specifies the I2S Handle.

+  *        This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.

+  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.

+  *         This parameter can be one of the following values:

+  *            @arg I2S_IT_RXP : Rx-Packet available interrupt

+  *            @arg I2S_IT_TXP : Tx-Packet space available interrupt

+  *            @arg I2S_IT_UDR : Underrun interrupt

+  *            @arg I2S_IT_OVR : Overrun interrupt

+  *            @arg I2S_IT_FRE : TI mode frame format error interrupt

+  *            @arg I2S_IT_ERR : Error interrupt enable

+  * @retval None

+  */

+#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))

+

+/** @brief  Disable the specified I2S interrupts.

+  * @param  __HANDLE__ specifies the I2S Handle.

+  *         This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.

+  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.

+  *         This parameter can be one of the following values:

+  *            @arg I2S_IT_RXP : Rx-Packet available interrupt

+  *            @arg I2S_IT_TXP : Tx-Packet space available interrupt

+  *            @arg I2S_IT_UDR : Underrun interrupt

+  *            @arg I2S_IT_OVR : Overrun interrupt

+  *            @arg I2S_IT_FRE : TI mode frame format error interrupt

+  *            @arg I2S_IT_ERR : Error interrupt enable

+  * @retval None

+  */

+#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))

+

+/** @brief  Check if the specified I2S interrupt source is enabled or disabled.

+  * @param  __HANDLE__ specifies the I2S Handle.

+  *         This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.

+  * @param  __INTERRUPT__ specifies the I2S interrupt source to check.

+  *          This parameter can be one of the following values:

+  *            @arg I2S_IT_RXP : Rx-Packet available interrupt

+  *            @arg I2S_IT_TXP : Tx-Packet space available interrupt

+  *            @arg I2S_IT_UDR : Underrun interrupt

+  *            @arg I2S_IT_OVR : Overrun interrupt

+  *            @arg I2S_IT_FRE : TI mode frame format error interrupt

+  *            @arg I2S_IT_ERR : Error interrupt enable

+  * @retval The new state of __IT__ (TRUE or FALSE).

+  */

+#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

+

+/** @brief  Check whether the specified I2S flag is set or not.

+  * @param  __HANDLE__ specifies the I2S Handle.

+  *         This parameter can be I2S where x: 1, 2 or 3 to select the I2S peripheral.

+  * @param  __FLAG__ specifies the flag to check.

+  *         This parameter can be one of the following values:

+  *            @arg I2S_FLAG_RXP : Rx-Packet available flag

+  *            @arg I2S_FLAG_TXP : Tx-Packet space available flag

+  *            @arg I2S_FLAG_UDR : Underrun flag

+  *            @arg I2S_FLAG_OVR : Overrun flag

+  *            @arg I2S_FLAG_FRE : TI mode frame format error flag

+  * @retval The new state of __FLAG__ (TRUE or FALSE).

+  */

+#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

+

+/** @brief Clear the I2S OVR pending flag.

+  * @param  __HANDLE__ specifies the I2S Handle.

+  * @retval None

+  */

+#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)

+

+/** @brief Clear the I2S UDR pending flag.

+  * @param  __HANDLE__ specifies the I2S Handle.

+  * @retval None

+  */

+#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)

+

+/** @brief  Clear the I2S FRE pending flag.

+  * @param  __HANDLE__: specifies the I2S Handle.

+  * @retval None

+  */

+#define __HAL_I2S_CLEAR_TIFREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup I2S_Exported_Functions

+  * @{

+  */

+

+/** @addtogroup I2S_Exported_Functions_Group1

+  * @{

+  */

+/* Initialization/de-initialization functions  ********************************/

+HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);

+HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s);

+void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);

+void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);

+

+/* Callbacks Register/UnRegister functions  ***********************************/

+#if (USE_HAL_I2S_REGISTER_CALLBACKS == 1UL)

+HAL_StatusTypeDef HAL_I2S_RegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID, pI2S_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_I2S_UnRegisterCallback(I2S_HandleTypeDef *hi2s, HAL_I2S_CallbackIDTypeDef CallbackID);

+#endif /* USE_HAL_I2S_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/** @addtogroup I2S_Exported_Functions_Group2

+  * @{

+  */

+/* I/O operation functions  ***************************************************/

+/* Blocking mode: Polling */

+HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);

+HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);

+

+/* Non-Blocking mode: Interrupt */

+HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);

+void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);

+

+/* Non-Blocking mode: DMA */

+HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);

+

+HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);

+HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);

+HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);

+

+/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/

+void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);

+void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);

+void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);

+void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);

+void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);

+/**

+  * @}

+  */

+

+/** @addtogroup I2S_Exported_Functions_Group3

+  * @{

+  */

+/* Peripheral Control and State functions  ************************************/

+HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);

+uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup I2S_Private_Constants I2S Private Constants

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup I2S_Private_Macros I2S Private Macros

+  * @{

+  */

+

+/** @brief  Check whether the specified SPI flag is set or not.

+  * @param  __SR__  copy of I2S SR register.

+  * @param  __FLAG__ specifies the flag to check.

+  *         This parameter can be one of the following values:

+  *            @arg I2S_FLAG_RXP : Rx-Packet available flag

+  *            @arg I2S_FLAG_TXP : Tx-Packet space available flag

+  *            @arg I2S_FLAG_UDR : Underrun flag

+  *            @arg I2S_FLAG_OVR : Overrun flag

+  *            @arg I2S_FLAG_FRE : TI mode frame format error flag

+  * @retval SET or RESET.

+  */

+#define I2S_CHECK_FLAG(__SR__, __FLAG__)         ((((__SR__) & ((__FLAG__) & I2S_FLAG_MASK)) == ((__FLAG__) & I2S_FLAG_MASK)) ? SET : RESET)

+

+/** @brief  Check whether the specified SPI Interrupt is set or not.

+  * @param  __IER__  copy of I2S IER register.

+  * @param  __INTERRUPT__ specifies the SPI interrupt source to check.

+  *         This parameter can be one of the following values:

+  *            @arg I2S_IT_RXP : Rx-Packet available interrupt

+  *            @arg I2S_IT_TXP : Tx-Packet space available interrupt

+  *            @arg I2S_IT_UDR : Underrun interrupt

+  *            @arg I2S_IT_OVR : Overrun interrupt

+  *            @arg I2S_IT_FRE : TI mode frame format error interrupt

+  *            @arg I2S_IT_ERR : Error interrupt enable

+  * @retval SET or RESET.

+  */

+#define I2S_CHECK_IT_SOURCE(__IER__, __INTERRUPT__)      ((((__IER__) & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

+

+/** @brief  Checks if I2S Mode parameter is in allowed range.

+  * @param  __MODE__ specifies the I2S Mode.

+  *         This parameter can be a value of @ref I2S_Mode

+  * @retval None

+  */

+#define IS_I2S_MODE(__MODE__)                       (((__MODE__) == I2S_MODE_SLAVE_TX)                   || \

+                                                     ((__MODE__) == I2S_MODE_SLAVE_RX)                   || \

+                                                     ((__MODE__) == I2S_MODE_MASTER_TX)                  || \

+                                                     ((__MODE__) == I2S_MODE_MASTER_RX)                  || \

+                                                     ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX)           || \

+                                                     ((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX))

+

+#define IS_I2S_MASTER(__MODE__)                     (((__MODE__) == I2S_MODE_MASTER_TX)                  || \

+                                                     ((__MODE__) == I2S_MODE_MASTER_RX)                  || \

+                                                     ((__MODE__) == I2S_MODE_MASTER_FULLDUPLEX))

+

+#define IS_I2S_SLAVE(__MODE__)                      (((__MODE__) == I2S_MODE_SLAVE_TX)                  || \

+                                                     ((__MODE__) == I2S_MODE_SLAVE_RX)                  || \

+                                                     ((__MODE__) == I2S_MODE_SLAVE_FULLDUPLEX))

+

+#define IS_I2S_STANDARD(__STANDARD__)               (((__STANDARD__) == I2S_STANDARD_PHILIPS)            || \

+                                                     ((__STANDARD__) == I2S_STANDARD_MSB)                || \

+                                                     ((__STANDARD__) == I2S_STANDARD_LSB)                || \

+                                                     ((__STANDARD__) == I2S_STANDARD_PCM_SHORT)          || \

+                                                     ((__STANDARD__) == I2S_STANDARD_PCM_LONG))

+

+#define IS_I2S_DATA_FORMAT(__FORMAT__)              (((__FORMAT__) == I2S_DATAFORMAT_16B)                || \

+                                                     ((__FORMAT__) == I2S_DATAFORMAT_16B_EXTENDED)       || \

+                                                     ((__FORMAT__) == I2S_DATAFORMAT_24B)                || \

+                                                     ((__FORMAT__) == I2S_DATAFORMAT_32B))

+

+#define IS_I2S_MCLK_OUTPUT(__OUTPUT__)              (((__OUTPUT__) == I2S_MCLKOUTPUT_ENABLE)             || \

+                                                     ((__OUTPUT__) == I2S_MCLKOUTPUT_DISABLE))

+

+#define IS_I2S_AUDIO_FREQ(__FREQ__)                ((((__FREQ__) >= I2S_AUDIOFREQ_8K)                    && \

+                                                     ((__FREQ__) <= I2S_AUDIOFREQ_192K))                 || \

+                                                     ((__FREQ__) == I2S_AUDIOFREQ_DEFAULT))

+

+#define IS_I2S_CPOL(__CPOL__)                       (((__CPOL__) == I2S_CPOL_LOW)                        || \

+                                                     ((__CPOL__) == I2S_CPOL_HIGH))

+

+#define IS_I2S_FIRST_BIT(__BIT__)                   (((__BIT__) == I2S_FIRSTBIT_MSB)                     || \

+                                                     ((__BIT__) == I2S_FIRSTBIT_LSB))

+

+#define IS_I2S_WS_INVERSION(__WSINV__)              (((__WSINV__) == I2S_WS_INVERSION_DISABLE)           || \

+                                                     ((__WSINV__) == I2S_WS_INVERSION_ENABLE))

+

+#define IS_I2S_DATA_24BIT_ALIGNMENT(__ALIGNMENT__)  (((__ALIGNMENT__) == I2S_DATA_24BIT_ALIGNMENT_RIGHT) || \

+                                                     ((__ALIGNMENT__) == I2S_DATA_24BIT_ALIGNMENT_LEFT))

+

+#define IS_I2S_MASTER_KEEP_IO_STATE(__AFCNTR__)     (((__AFCNTR__) == I2S_MASTER_KEEP_IO_STATE_DISABLE)  || \

+                                                     ((__AFCNTR__) == I2S_MASTER_KEEP_IO_STATE_ENABLE))

+

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_I2S_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_i2s_ex.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_i2s_ex.h
new file mode 100644
index 0000000000..c868dd0b02
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_i2s_ex.h
@@ -0,0 +1,20 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_i2s_ex.h

+  * @author  MCD Application Team

+  * @brief   Header file of I2S HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+  /* The I2S Full duplex feature is not supported by this HAL Driver          */

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_irda.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_irda.h
new file mode 100644
index 0000000000..ea0750f492
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_irda.h
@@ -0,0 +1,884 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_irda.h

+  * @author  MCD Application Team

+  * @brief   Header file of IRDA HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_IRDA_H

+#define STM32H7xx_HAL_IRDA_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup IRDA

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup IRDA_Exported_Types IRDA Exported Types

+  * @{

+  */

+

+/**

+  * @brief IRDA Init Structure definition

+  */

+typedef struct

+{

+  uint32_t BaudRate;                  /*!< This member configures the IRDA communication baud rate.

+                                           The baud rate register is computed using the following formula:

+                                              Baud Rate Register = ((usart_ker_ckpres) / ((hirda->Init.BaudRate)))

+                                           where usart_ker_ckpres is the IRDA input clock divided by a prescaler */

+

+  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.

+                                           This parameter can be a value of @ref IRDAEx_Word_Length */

+

+  uint32_t Parity;                    /*!< Specifies the parity mode.

+                                           This parameter can be a value of @ref IRDA_Parity

+                                           @note When parity is enabled, the computed parity is inserted

+                                                 at the MSB position of the transmitted data (9th bit when

+                                                 the word length is set to 9 data bits; 8th bit when the

+                                                 word length is set to 8 data bits). */

+

+  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.

+                                           This parameter can be a value of @ref IRDA_Transfer_Mode */

+

+  uint8_t  Prescaler;                 /*!< Specifies the Prescaler value for dividing the UART/USART source clock

+                                           to achieve low-power frequency.

+                                           @note Prescaler value 0 is forbidden */

+

+  uint16_t PowerMode;                 /*!< Specifies the IRDA power mode.

+                                           This parameter can be a value of @ref IRDA_Low_Power */

+

+  uint32_t ClockPrescaler;            /*!< Specifies the prescaler value used to divide the IRDA clock source.

+                                           This parameter can be a value of @ref IRDA_ClockPrescaler. */

+

+} IRDA_InitTypeDef;

+

+/**

+  * @brief HAL IRDA State definition

+  * @note  HAL IRDA State value is a combination of 2 different substates: gState and RxState (see @ref IRDA_State_Definition).

+  *        - gState contains IRDA state information related to global Handle management

+  *          and also information related to Tx operations.

+  *          gState value coding follow below described bitmap :

+  *          b7-b6  Error information

+  *             00 : No Error

+  *             01 : (Not Used)

+  *             10 : Timeout

+  *             11 : Error

+  *          b5     Peripheral initialization status

+  *             0  : Reset (Peripheral not initialized)

+  *             1  : Init done (Peripheral not initialized. HAL IRDA Init function already called)

+  *          b4-b3  (not used)

+  *             xx : Should be set to 00

+  *          b2     Intrinsic process state

+  *             0  : Ready

+  *             1  : Busy (Peripheral busy with some configuration or internal operations)

+  *          b1     (not used)

+  *             x  : Should be set to 0

+  *          b0     Tx state

+  *             0  : Ready (no Tx operation ongoing)

+  *             1  : Busy (Tx operation ongoing)

+  *        - RxState contains information related to Rx operations.

+  *          RxState value coding follow below described bitmap :

+  *          b7-b6  (not used)

+  *             xx : Should be set to 00

+  *          b5     Peripheral initialization status

+  *             0  : Reset (Peripheral not initialized)

+  *             1  : Init done (Peripheral not initialized)

+  *          b4-b2  (not used)

+  *            xxx : Should be set to 000

+  *          b1     Rx state

+  *             0  : Ready (no Rx operation ongoing)

+  *             1  : Busy (Rx operation ongoing)

+  *          b0     (not used)

+  *             x  : Should be set to 0.

+  */

+typedef uint32_t HAL_IRDA_StateTypeDef;

+

+/**

+  * @brief IRDA clock sources definition

+  */

+typedef enum

+{

+  IRDA_CLOCKSOURCE_D2PCLK1    = 0x11U,    /*!< Domain2 PCLK1 clock source */

+  IRDA_CLOCKSOURCE_D2PCLK2    = 0x12U,    /*!< Domain2 PCLK2 clock source */

+  IRDA_CLOCKSOURCE_PLL2Q      = 0x14U,    /*!< PLL2Q clock source         */

+  IRDA_CLOCKSOURCE_PLL3Q      = 0x18U,    /*!< PCLK2 clock source         */

+  IRDA_CLOCKSOURCE_HSI        = 0x02U,    /*!< HSI clock source           */

+  IRDA_CLOCKSOURCE_CSI        = 0x08U,    /*!< CSI clock source           */

+  IRDA_CLOCKSOURCE_LSE        = 0x10U,    /*!< LSE clock source           */

+  IRDA_CLOCKSOURCE_UNDEFINED  = 0x20U     /*!< Undefined clock source     */

+} IRDA_ClockSourceTypeDef;

+

+/**

+  * @brief  IRDA handle Structure definition

+  */

+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)

+typedef struct __IRDA_HandleTypeDef

+#else

+typedef struct

+#endif  /* USE_HAL_IRDA_REGISTER_CALLBACKS */

+{

+  USART_TypeDef            *Instance;        /*!< USART registers base address       */

+

+  IRDA_InitTypeDef         Init;             /*!< IRDA communication parameters      */

+

+  uint8_t                  *pTxBuffPtr;      /*!< Pointer to IRDA Tx transfer Buffer */

+

+  uint16_t                 TxXferSize;       /*!< IRDA Tx Transfer size              */

+

+  __IO uint16_t            TxXferCount;      /*!< IRDA Tx Transfer Counter           */

+

+  uint8_t                  *pRxBuffPtr;      /*!< Pointer to IRDA Rx transfer Buffer */

+

+  uint16_t                 RxXferSize;       /*!< IRDA Rx Transfer size              */

+

+  __IO uint16_t            RxXferCount;      /*!< IRDA Rx Transfer Counter           */

+

+  uint16_t                 Mask;             /*!< USART RX RDR register mask         */

+

+  DMA_HandleTypeDef        *hdmatx;          /*!< IRDA Tx DMA Handle parameters      */

+

+  DMA_HandleTypeDef        *hdmarx;          /*!< IRDA Rx DMA Handle parameters      */

+

+  HAL_LockTypeDef          Lock;             /*!< Locking object                     */

+

+  __IO HAL_IRDA_StateTypeDef    gState;      /*!< IRDA state information related to global Handle management

+                                                  and also related to Tx operations.

+                                                  This parameter can be a value of @ref HAL_IRDA_StateTypeDef */

+

+  __IO HAL_IRDA_StateTypeDef    RxState;     /*!< IRDA state information related to Rx operations.

+                                                  This parameter can be a value of @ref HAL_IRDA_StateTypeDef */

+

+  __IO uint32_t            ErrorCode;        /*!< IRDA Error code                    */

+

+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)

+  void (* TxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda);        /*!< IRDA Tx Half Complete Callback        */

+

+  void (* TxCpltCallback)(struct __IRDA_HandleTypeDef *hirda);            /*!< IRDA Tx Complete Callback             */

+

+  void (* RxHalfCpltCallback)(struct __IRDA_HandleTypeDef *hirda);        /*!< IRDA Rx Half Complete Callback        */

+

+  void (* RxCpltCallback)(struct __IRDA_HandleTypeDef *hirda);            /*!< IRDA Rx Complete Callback             */

+

+  void (* ErrorCallback)(struct __IRDA_HandleTypeDef *hirda);             /*!< IRDA Error Callback                   */

+

+  void (* AbortCpltCallback)(struct __IRDA_HandleTypeDef *hirda);         /*!< IRDA Abort Complete Callback          */

+

+  void (* AbortTransmitCpltCallback)(struct __IRDA_HandleTypeDef *hirda); /*!< IRDA Abort Transmit Complete Callback */

+

+  void (* AbortReceiveCpltCallback)(struct __IRDA_HandleTypeDef *hirda);  /*!< IRDA Abort Receive Complete Callback  */

+

+

+  void (* MspInitCallback)(struct __IRDA_HandleTypeDef *hirda);           /*!< IRDA Msp Init callback                */

+

+  void (* MspDeInitCallback)(struct __IRDA_HandleTypeDef *hirda);         /*!< IRDA Msp DeInit callback              */

+#endif  /* USE_HAL_IRDA_REGISTER_CALLBACKS */

+

+} IRDA_HandleTypeDef;

+

+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  HAL IRDA Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_IRDA_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< IRDA Tx Half Complete Callback ID        */

+  HAL_IRDA_TX_COMPLETE_CB_ID             = 0x01U,    /*!< IRDA Tx Complete Callback ID             */

+  HAL_IRDA_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< IRDA Rx Half Complete Callback ID        */

+  HAL_IRDA_RX_COMPLETE_CB_ID             = 0x03U,    /*!< IRDA Rx Complete Callback ID             */

+  HAL_IRDA_ERROR_CB_ID                   = 0x04U,    /*!< IRDA Error Callback ID                   */

+  HAL_IRDA_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< IRDA Abort Complete Callback ID          */

+  HAL_IRDA_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< IRDA Abort Transmit Complete Callback ID */

+  HAL_IRDA_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< IRDA Abort Receive Complete Callback ID  */

+

+  HAL_IRDA_MSPINIT_CB_ID                 = 0x08U,    /*!< IRDA MspInit callback ID                 */

+  HAL_IRDA_MSPDEINIT_CB_ID               = 0x09U     /*!< IRDA MspDeInit callback ID               */

+

+} HAL_IRDA_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL IRDA Callback pointer definition

+  */

+typedef  void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda);  /*!< pointer to an IRDA callback function */

+

+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup IRDA_Exported_Constants IRDA Exported Constants

+  * @{

+  */

+

+/** @defgroup IRDA_State_Definition IRDA State Code Definition

+  * @{

+  */

+#define HAL_IRDA_STATE_RESET                0x00000000U   /*!< Peripheral is not initialized

+                                                               Value is allowed for gState and RxState */

+#define HAL_IRDA_STATE_READY                0x00000020U   /*!< Peripheral Initialized and ready for use

+                                                               Value is allowed for gState and RxState */

+#define HAL_IRDA_STATE_BUSY                 0x00000024U   /*!< An internal process is ongoing

+                                                               Value is allowed for gState only */

+#define HAL_IRDA_STATE_BUSY_TX              0x00000021U   /*!< Data Transmission process is ongoing

+                                                               Value is allowed for gState only */

+#define HAL_IRDA_STATE_BUSY_RX              0x00000022U   /*!< Data Reception process is ongoing

+                                                               Value is allowed for RxState only */

+#define HAL_IRDA_STATE_BUSY_TX_RX           0x00000023U   /*!< Data Transmission and Reception process is ongoing

+                                                               Not to be used for neither gState nor RxState.

+                                                               Value is result of combination (Or) between gState and RxState values */

+#define HAL_IRDA_STATE_TIMEOUT              0x000000A0U   /*!< Timeout state

+                                                               Value is allowed for gState only */

+#define HAL_IRDA_STATE_ERROR                0x000000E0U   /*!< Error

+                                                               Value is allowed for gState only */

+/**

+  * @}

+  */

+

+/** @defgroup IRDA_Error_Definition IRDA Error Code Definition

+  * @{

+  */

+#define HAL_IRDA_ERROR_NONE                 ((uint32_t)0x00000000U)          /*!< No error                */

+#define HAL_IRDA_ERROR_PE                   ((uint32_t)0x00000001U)          /*!< Parity error            */

+#define HAL_IRDA_ERROR_NE                   ((uint32_t)0x00000002U)          /*!< Noise error             */

+#define HAL_IRDA_ERROR_FE                   ((uint32_t)0x00000004U)          /*!< frame error             */

+#define HAL_IRDA_ERROR_ORE                  ((uint32_t)0x00000008U)          /*!< Overrun error           */

+#define HAL_IRDA_ERROR_DMA                  ((uint32_t)0x00000010U)          /*!< DMA transfer error      */

+#define HAL_IRDA_ERROR_BUSY                 ((uint32_t)0x00000020U)          /*!< Busy Error              */

+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)

+#define HAL_IRDA_ERROR_INVALID_CALLBACK     ((uint32_t)0x00000040U)          /*!< Invalid Callback error  */

+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/** @defgroup IRDA_Parity IRDA Parity

+  * @{

+  */

+#define IRDA_PARITY_NONE                    0x00000000U                      /*!< No parity   */

+#define IRDA_PARITY_EVEN                    USART_CR1_PCE                    /*!< Even parity */

+#define IRDA_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)   /*!< Odd parity  */

+/**

+  * @}

+  */

+

+/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode

+  * @{

+  */

+#define IRDA_MODE_RX                        USART_CR1_RE                   /*!< RX mode        */

+#define IRDA_MODE_TX                        USART_CR1_TE                   /*!< TX mode        */

+#define IRDA_MODE_TX_RX                     (USART_CR1_TE |USART_CR1_RE)   /*!< RX and TX mode */

+/**

+  * @}

+  */

+

+/** @defgroup IRDA_Low_Power IRDA Low Power

+  * @{

+  */

+#define IRDA_POWERMODE_NORMAL               0x00000000U       /*!< IRDA normal power mode */

+#define IRDA_POWERMODE_LOWPOWER             USART_CR3_IRLP    /*!< IRDA low power mode    */

+/**

+  * @}

+  */

+

+/** @defgroup IRDA_ClockPrescaler IRDA Clock Prescaler

+  * @{

+  */

+#define IRDA_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */

+#define IRDA_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */

+#define IRDA_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */

+#define IRDA_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */

+#define IRDA_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */

+#define IRDA_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */

+#define IRDA_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */

+#define IRDA_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */

+#define IRDA_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */

+#define IRDA_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */

+#define IRDA_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */

+#define IRDA_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */

+/**

+  * @}

+  */

+

+/** @defgroup IRDA_State IRDA State

+  * @{

+  */

+#define IRDA_STATE_DISABLE                  0x00000000U     /*!< IRDA disabled  */

+#define IRDA_STATE_ENABLE                   USART_CR1_UE    /*!< IRDA enabled   */

+/**

+  * @}

+  */

+

+/** @defgroup IRDA_Mode IRDA Mode

+  * @{

+  */

+#define IRDA_MODE_DISABLE                   0x00000000U      /*!< Associated UART disabled in IRDA mode */

+#define IRDA_MODE_ENABLE                    USART_CR3_IREN   /*!< Associated UART enabled in IRDA mode  */

+/**

+  * @}

+  */

+

+/** @defgroup IRDA_One_Bit IRDA One Bit Sampling

+  * @{

+  */

+#define IRDA_ONE_BIT_SAMPLE_DISABLE         0x00000000U       /*!< One-bit sampling disabled */

+#define IRDA_ONE_BIT_SAMPLE_ENABLE          USART_CR3_ONEBIT  /*!< One-bit sampling enabled  */

+/**

+  * @}

+  */

+

+/** @defgroup IRDA_DMA_Tx IRDA DMA Tx

+  * @{

+  */

+#define IRDA_DMA_TX_DISABLE                 0x00000000U       /*!< IRDA DMA TX disabled */

+#define IRDA_DMA_TX_ENABLE                  USART_CR3_DMAT    /*!< IRDA DMA TX enabled  */

+/**

+  * @}

+  */

+

+/** @defgroup IRDA_DMA_Rx IRDA DMA Rx

+  * @{

+  */

+#define IRDA_DMA_RX_DISABLE                 0x00000000U       /*!< IRDA DMA RX disabled */

+#define IRDA_DMA_RX_ENABLE                  USART_CR3_DMAR    /*!< IRDA DMA RX enabled  */

+/**

+  * @}

+  */

+

+/** @defgroup IRDA_Request_Parameters IRDA Request Parameters

+  * @{

+  */

+#define IRDA_AUTOBAUD_REQUEST            USART_RQR_ABRRQ        /*!< Auto-Baud Rate Request      */

+#define IRDA_RXDATA_FLUSH_REQUEST        USART_RQR_RXFRQ        /*!< Receive Data flush Request  */

+#define IRDA_TXDATA_FLUSH_REQUEST        USART_RQR_TXFRQ        /*!< Transmit data flush Request */

+/**

+  * @}

+  */

+

+/** @defgroup IRDA_Flags IRDA Flags

+  *        Elements values convention: 0xXXXX

+  *           - 0xXXXX  : Flag mask in the ISR register

+  * @{

+  */

+#define IRDA_FLAG_REACK                     USART_ISR_REACK         /*!< IRDA receive enable acknowledge flag      */

+#define IRDA_FLAG_TEACK                     USART_ISR_TEACK         /*!< IRDA transmit enable acknowledge flag     */

+#define IRDA_FLAG_BUSY                      USART_ISR_BUSY          /*!< IRDA busy flag                            */

+#define IRDA_FLAG_ABRF                      USART_ISR_ABRF          /*!< IRDA auto Baud rate flag                  */

+#define IRDA_FLAG_ABRE                      USART_ISR_ABRE          /*!< IRDA auto Baud rate error                 */

+#define IRDA_FLAG_TXE                       USART_ISR_TXE_TXFNF     /*!< IRDA transmit data register empty         */

+#define IRDA_FLAG_TC                        USART_ISR_TC            /*!< IRDA transmission complete                */

+#define IRDA_FLAG_RXNE                      USART_ISR_RXNE_RXFNE    /*!< IRDA read data register not empty         */

+#define IRDA_FLAG_ORE                       USART_ISR_ORE           /*!< IRDA overrun error                        */

+#define IRDA_FLAG_NE                        USART_ISR_NE            /*!< IRDA noise error                          */

+#define IRDA_FLAG_FE                        USART_ISR_FE            /*!< IRDA frame error                          */

+#define IRDA_FLAG_PE                        USART_ISR_PE            /*!< IRDA parity error                         */

+/**

+  * @}

+  */

+

+/** @defgroup IRDA_Interrupt_definition IRDA Interrupts Definition

+  *        Elements values convention: 0000ZZZZ0XXYYYYYb

+  *           - YYYYY  : Interrupt source position in the XX register (5bits)

+  *           - XX  : Interrupt source register (2bits)

+  *                 - 01: CR1 register

+  *                 - 10: CR2 register

+  *                 - 11: CR3 register

+  *           - ZZZZ  : Flag position in the ISR register(4bits)

+  * @{

+  */

+#define IRDA_IT_PE                          0x0028U     /*!< IRDA Parity error interruption                 */

+#define IRDA_IT_TXE                         0x0727U     /*!< IRDA Transmit data register empty interruption */

+#define IRDA_IT_TC                          0x0626U     /*!< IRDA Transmission complete interruption        */

+#define IRDA_IT_RXNE                        0x0525U     /*!< IRDA Read data register not empty interruption */

+#define IRDA_IT_IDLE                        0x0424U     /*!< IRDA Idle interruption                         */

+

+/*       Elements values convention: 000000000XXYYYYYb

+             - YYYYY  : Interrupt source position in the XX register (5bits)

+             - XX  : Interrupt source register (2bits)

+                   - 01: CR1 register

+                   - 10: CR2 register

+                   - 11: CR3 register */

+#define IRDA_IT_ERR                         0x0060U       /*!< IRDA Error interruption        */

+

+/*       Elements values convention: 0000ZZZZ00000000b

+             - ZZZZ  : Flag position in the ISR register(4bits) */

+#define IRDA_IT_ORE                         0x0300U      /*!< IRDA Overrun error interruption */

+#define IRDA_IT_NE                          0x0200U      /*!< IRDA Noise error interruption   */

+#define IRDA_IT_FE                          0x0100U      /*!< IRDA Frame error interruption   */

+/**

+  * @}

+  */

+

+/** @defgroup IRDA_IT_CLEAR_Flags IRDA Interruption Clear Flags

+  * @{

+  */

+#define IRDA_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag          */

+#define IRDA_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag         */

+#define IRDA_CLEAR_NEF                       USART_ICR_NECF            /*!< Noise Error detected Clear Flag  */

+#define IRDA_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag         */

+#define IRDA_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag    */

+#define IRDA_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag */

+/**

+  * @}

+  */

+

+/** @defgroup IRDA_Interruption_Mask IRDA interruptions flags mask

+  * @{

+  */

+#define IRDA_IT_MASK  0x001FU  /*!< IRDA Interruptions flags mask  */

+#define IRDA_CR_MASK  0x00E0U  /*!< IRDA control register mask     */

+#define IRDA_CR_POS   5U       /*!< IRDA control register position */

+#define IRDA_ISR_MASK 0x1F00U  /*!< IRDA ISR register mask         */

+#define IRDA_ISR_POS  8U       /*!< IRDA ISR register position     */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macros -----------------------------------------------------------*/

+/** @defgroup IRDA_Exported_Macros IRDA Exported Macros

+  * @{

+  */

+

+/** @brief  Reset IRDA handle state.

+  * @param  __HANDLE__ IRDA handle.

+  * @retval None

+  */

+#if USE_HAL_IRDA_REGISTER_CALLBACKS == 1

+#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \

+                                                       (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \

+                                                       (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \

+                                                       (__HANDLE__)->MspInitCallback = NULL;             \

+                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \

+                                                     } while(0U)

+#else

+#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \

+                                                       (__HANDLE__)->gState = HAL_IRDA_STATE_RESET;      \

+                                                       (__HANDLE__)->RxState = HAL_IRDA_STATE_RESET;     \

+                                                     } while(0U)

+#endif /*USE_HAL_IRDA_REGISTER_CALLBACKS  */

+

+/** @brief  Flush the IRDA DR register.

+  * @param  __HANDLE__ specifies the IRDA Handle.

+  * @retval None

+  */

+#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)                            \

+  do{                                                                    \

+    SET_BIT((__HANDLE__)->Instance->RQR, IRDA_RXDATA_FLUSH_REQUEST); \

+    SET_BIT((__HANDLE__)->Instance->RQR, IRDA_TXDATA_FLUSH_REQUEST); \

+  } while(0U)

+

+/** @brief  Clear the specified IRDA pending flag.

+  * @param  __HANDLE__ specifies the IRDA Handle.

+  * @param  __FLAG__ specifies the flag to check.

+  *          This parameter can be any combination of the following values:

+  *            @arg @ref IRDA_CLEAR_PEF

+  *            @arg @ref IRDA_CLEAR_FEF

+  *            @arg @ref IRDA_CLEAR_NEF

+  *            @arg @ref IRDA_CLEAR_OREF

+  *            @arg @ref IRDA_CLEAR_TCF

+  *            @arg @ref IRDA_CLEAR_IDLEF

+  * @retval None

+  */

+#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))

+

+/** @brief  Clear the IRDA PE pending flag.

+  * @param  __HANDLE__ specifies the IRDA Handle.

+  * @retval None

+  */

+#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)

+

+

+/** @brief  Clear the IRDA FE pending flag.

+  * @param  __HANDLE__ specifies the IRDA Handle.

+  * @retval None

+  */

+#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)

+

+/** @brief  Clear the IRDA NE pending flag.

+  * @param  __HANDLE__ specifies the IRDA Handle.

+  * @retval None

+  */

+#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)

+

+/** @brief  Clear the IRDA ORE pending flag.

+  * @param  __HANDLE__ specifies the IRDA Handle.

+  * @retval None

+  */

+#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)

+

+/** @brief  Clear the IRDA IDLE pending flag.

+  * @param  __HANDLE__ specifies the IRDA Handle.

+  * @retval None

+  */

+#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)

+

+/** @brief  Check whether the specified IRDA flag is set or not.

+  * @param  __HANDLE__ specifies the IRDA Handle.

+  * @param  __FLAG__ specifies the flag to check.

+  *        This parameter can be one of the following values:

+  *            @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag

+  *            @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag

+  *            @arg @ref IRDA_FLAG_BUSY  Busy flag

+  *            @arg @ref IRDA_FLAG_ABRF  Auto Baud rate detection flag

+  *            @arg @ref IRDA_FLAG_ABRE  Auto Baud rate detection error flag

+  *            @arg @ref IRDA_FLAG_TXE   Transmit data register empty flag

+  *            @arg @ref IRDA_FLAG_TC    Transmission Complete flag

+  *            @arg @ref IRDA_FLAG_RXNE  Receive data register not empty flag

+  *            @arg @ref IRDA_FLAG_ORE   OverRun Error flag

+  *            @arg @ref IRDA_FLAG_NE    Noise Error flag

+  *            @arg @ref IRDA_FLAG_FE    Framing Error flag

+  *            @arg @ref IRDA_FLAG_PE    Parity Error flag

+  * @retval The new state of __FLAG__ (TRUE or FALSE).

+  */

+#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

+

+

+/** @brief  Enable the specified IRDA interrupt.

+  * @param  __HANDLE__ specifies the IRDA Handle.

+  * @param  __INTERRUPT__ specifies the IRDA interrupt source to enable.

+  *          This parameter can be one of the following values:

+  *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt

+  *            @arg @ref IRDA_IT_TC   Transmission complete interrupt

+  *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt

+  *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt

+  *            @arg @ref IRDA_IT_PE   Parity Error interrupt

+  *            @arg @ref IRDA_IT_ERR  Error interrupt(Frame error, noise error, overrun error)

+  * @retval None

+  */

+#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \

+                                                           ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \

+                                                           ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))

+

+/** @brief  Disable the specified IRDA interrupt.

+  * @param  __HANDLE__ specifies the IRDA Handle.

+  * @param  __INTERRUPT__ specifies the IRDA interrupt source to disable.

+  *          This parameter can be one of the following values:

+  *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt

+  *            @arg @ref IRDA_IT_TC   Transmission complete interrupt

+  *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt

+  *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt

+  *            @arg @ref IRDA_IT_PE   Parity Error interrupt

+  *            @arg @ref IRDA_IT_ERR  Error interrupt(Frame error, noise error, overrun error)

+  * @retval None

+  */

+#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \

+                                                           ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \

+                                                           ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))))

+

+

+/** @brief  Check whether the specified IRDA interrupt has occurred or not.

+  * @param  __HANDLE__ specifies the IRDA Handle.

+  * @param  __INTERRUPT__ specifies the IRDA interrupt source to check.

+  *          This parameter can be one of the following values:

+  *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt

+  *            @arg @ref IRDA_IT_TC  Transmission complete interrupt

+  *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt

+  *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt

+  *            @arg @ref IRDA_IT_ORE OverRun Error interrupt

+  *            @arg @ref IRDA_IT_NE Noise Error interrupt

+  *            @arg @ref IRDA_IT_FE Framing Error interrupt

+  *            @arg @ref IRDA_IT_PE Parity Error interrupt

+  * @retval The new state of __IT__ (SET or RESET).

+  */

+#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\

+                                                        & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET)

+

+/** @brief  Check whether the specified IRDA interrupt source is enabled or not.

+  * @param  __HANDLE__ specifies the IRDA Handle.

+  * @param  __INTERRUPT__ specifies the IRDA interrupt source to check.

+  *          This parameter can be one of the following values:

+  *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt

+  *            @arg @ref IRDA_IT_TC  Transmission complete interrupt

+  *            @arg @ref IRDA_IT_RXNE Receive Data register not empty interrupt

+  *            @arg @ref IRDA_IT_IDLE Idle line detection interrupt

+  *            @arg @ref IRDA_IT_ERR Framing, overrun or noise error interrupt

+  *            @arg @ref IRDA_IT_PE Parity Error interrupt

+  * @retval The new state of __IT__ (SET or RESET).

+  */

+#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \

+                                                                (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \

+                                                                 (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET)

+

+/** @brief  Clear the specified IRDA ISR flag, in setting the proper ICR register flag.

+  * @param  __HANDLE__ specifies the IRDA Handle.

+  * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set

+  *                       to clear the corresponding interrupt

+  *          This parameter can be one of the following values:

+  *            @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag

+  *            @arg @ref IRDA_CLEAR_FEF Framing Error Clear Flag

+  *            @arg @ref IRDA_CLEAR_NEF Noise detected Clear Flag

+  *            @arg @ref IRDA_CLEAR_OREF OverRun Error Clear Flag

+  *            @arg @ref IRDA_CLEAR_TCF Transmission Complete Clear Flag

+  * @retval None

+  */

+#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))

+

+

+/** @brief  Set a specific IRDA request flag.

+  * @param  __HANDLE__ specifies the IRDA Handle.

+  * @param  __REQ__ specifies the request flag to set

+  *          This parameter can be one of the following values:

+  *            @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request

+  *            @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request

+  *            @arg @ref IRDA_TXDATA_FLUSH_REQUEST Transmit data flush Request

+  * @retval None

+  */

+#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))

+

+/** @brief  Enable the IRDA one bit sample method.

+  * @param  __HANDLE__ specifies the IRDA Handle.

+  * @retval None

+  */

+#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

+

+/** @brief  Disable the IRDA one bit sample method.

+  * @param  __HANDLE__ specifies the IRDA Handle.

+  * @retval None

+  */

+#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\

+                                                       &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))

+

+/** @brief  Enable UART/USART associated to IRDA Handle.

+  * @param  __HANDLE__ specifies the IRDA Handle.

+  * @retval None

+  */

+#define __HAL_IRDA_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)

+

+/** @brief  Disable UART/USART associated to IRDA Handle.

+  * @param  __HANDLE__ specifies the IRDA Handle.

+  * @retval None

+  */

+#define __HAL_IRDA_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)

+

+/**

+  * @}

+  */

+

+/* Private macros --------------------------------------------------------*/

+/** @addtogroup IRDA_Private_Macros

+  * @{

+  */

+

+/** @brief  Ensure that IRDA Baud rate is less or equal to maximum value.

+  * @param  __BAUDRATE__ specifies the IRDA Baudrate set by the user.

+  * @retval True or False

+  */

+#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)

+

+/** @brief  Ensure that IRDA prescaler value is strictly larger than 0.

+  * @param  __PRESCALER__ specifies the IRDA prescaler value set by the user.

+  * @retval True or False

+  */

+#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)

+

+/** @brief Ensure that IRDA frame parity is valid.

+  * @param __PARITY__ IRDA frame parity.

+  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

+  */

+#define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \

+                                    ((__PARITY__) == IRDA_PARITY_EVEN) || \

+                                    ((__PARITY__) == IRDA_PARITY_ODD))

+

+/** @brief Ensure that IRDA communication mode is valid.

+  * @param __MODE__ IRDA communication mode.

+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

+  */

+#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__)\

+                                        & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))

+

+/** @brief Ensure that IRDA power mode is valid.

+  * @param __MODE__ IRDA power mode.

+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

+  */

+#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \

+                                     ((__MODE__) == IRDA_POWERMODE_NORMAL))

+

+/** @brief Ensure that IRDA clock Prescaler is valid.

+  * @param __CLOCKPRESCALER__ IRDA clock Prescaler value.

+  * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)

+  */

+#define IS_IRDA_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV1) || \

+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV2)   || \

+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV4)   || \

+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV6)   || \

+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV8)   || \

+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV10)  || \

+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV12)  || \

+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV16)  || \

+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV32)  || \

+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV64)  || \

+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV128) || \

+                                                    ((__CLOCKPRESCALER__) == IRDA_PRESCALER_DIV256))

+

+/** @brief Ensure that IRDA state is valid.

+  * @param __STATE__ IRDA state mode.

+  * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

+  */

+#define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \

+                                  ((__STATE__) == IRDA_STATE_ENABLE))

+

+/** @brief Ensure that IRDA associated UART/USART mode is valid.

+  * @param __MODE__ IRDA associated UART/USART mode.

+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

+  */

+#define IS_IRDA_MODE(__MODE__)  (((__MODE__) == IRDA_MODE_DISABLE) || \

+                                 ((__MODE__) == IRDA_MODE_ENABLE))

+

+/** @brief Ensure that IRDA sampling rate is valid.

+  * @param __ONEBIT__ IRDA sampling rate.

+  * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)

+  */

+#define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)      (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \

+                                                 ((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_ENABLE))

+

+/** @brief Ensure that IRDA DMA TX mode is valid.

+  * @param __DMATX__ IRDA DMA TX mode.

+  * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)

+  */

+#define IS_IRDA_DMA_TX(__DMATX__)     (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \

+                                       ((__DMATX__) == IRDA_DMA_TX_ENABLE))

+

+/** @brief Ensure that IRDA DMA RX mode is valid.

+  * @param __DMARX__ IRDA DMA RX mode.

+  * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)

+  */

+#define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \

+                                   ((__DMARX__) == IRDA_DMA_RX_ENABLE))

+

+/** @brief Ensure that IRDA request is valid.

+  * @param __PARAM__ IRDA request.

+  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

+  */

+#define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \

+                                              ((__PARAM__) == IRDA_RXDATA_FLUSH_REQUEST) || \

+                                              ((__PARAM__) == IRDA_TXDATA_FLUSH_REQUEST))

+/**

+  * @}

+  */

+

+/* Include IRDA HAL Extended module */

+#include "stm32h7xx_hal_irda_ex.h"

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions

+  * @{

+  */

+

+/** @addtogroup IRDA_Exported_Functions_Group1 Initialization and de-initialization functions

+  * @{

+  */

+

+/* Initialization and de-initialization functions  ****************************/

+HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);

+HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);

+void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);

+void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);

+

+#if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1)

+/* Callbacks Register/UnRegister functions  ***********************************/

+HAL_StatusTypeDef HAL_IRDA_RegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID,

+                                            pIRDA_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRDA_CallbackIDTypeDef CallbackID);

+#endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions

+  * @{

+  */

+

+/* IO operation functions *****************************************************/

+HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);

+HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);

+HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);

+HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);

+HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);

+/* Transfer Abort functions */

+HAL_StatusTypeDef HAL_IRDA_Abort(IRDA_HandleTypeDef *hirda);

+HAL_StatusTypeDef HAL_IRDA_AbortTransmit(IRDA_HandleTypeDef *hirda);

+HAL_StatusTypeDef HAL_IRDA_AbortReceive(IRDA_HandleTypeDef *hirda);

+HAL_StatusTypeDef HAL_IRDA_Abort_IT(IRDA_HandleTypeDef *hirda);

+HAL_StatusTypeDef HAL_IRDA_AbortTransmit_IT(IRDA_HandleTypeDef *hirda);

+HAL_StatusTypeDef HAL_IRDA_AbortReceive_IT(IRDA_HandleTypeDef *hirda);

+

+void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);

+void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);

+void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);

+void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);

+void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);

+void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);

+void HAL_IRDA_AbortCpltCallback(IRDA_HandleTypeDef *hirda);

+void HAL_IRDA_AbortTransmitCpltCallback(IRDA_HandleTypeDef *hirda);

+void HAL_IRDA_AbortReceiveCpltCallback(IRDA_HandleTypeDef *hirda);

+

+/**

+  * @}

+  */

+

+/* Peripheral Control functions  ************************************************/

+

+/** @addtogroup IRDA_Exported_Functions_Group4 Peripheral State and Error functions

+  * @{

+  */

+

+/* Peripheral State and Error functions ***************************************/

+HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);

+uint32_t              HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_IRDA_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_irda_ex.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_irda_ex.h
new file mode 100644
index 0000000000..95b1e7eaa2
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_irda_ex.h
@@ -0,0 +1,650 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_irda_ex.h

+  * @author  MCD Application Team

+  * @brief   Header file of IRDA HAL Extended module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_IRDA_EX_H

+#define STM32H7xx_HAL_IRDA_EX_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @defgroup IRDAEx IRDAEx

+  * @brief IRDA Extended HAL module driver

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup IRDAEx_Extended_Exported_Constants IRDAEx Extended Exported Constants

+  * @{

+  */

+

+/** @defgroup IRDAEx_Word_Length IRDAEx Word Length

+  * @{

+  */

+#define IRDA_WORDLENGTH_7B                  USART_CR1_M1   /*!< 7-bit long frame */

+#define IRDA_WORDLENGTH_8B                  0x00000000U    /*!< 8-bit long frame */

+#define IRDA_WORDLENGTH_9B                  USART_CR1_M0   /*!< 9-bit long frame */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macros -----------------------------------------------------------*/

+

+/* Private macros ------------------------------------------------------------*/

+

+/** @defgroup IRDAEx_Private_Macros IRDAEx Private Macros

+  * @{

+  */

+

+/** @brief  Report the IRDA clock source.

+  * @param  __HANDLE__ specifies the IRDA Handle.

+  * @param  __CLOCKSOURCE__ output variable.

+  * @retval IRDA clocking source, written in __CLOCKSOURCE__.

+  */

+#if defined(UART9) && defined(USART10)

+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \

+  do {                                                        \

+    if((__HANDLE__)->Instance == USART1)                      \

+    {                                                         \

+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \

+      {                                                       \

+        case RCC_USART1CLKSOURCE_D2PCLK2:                     \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2;       \

+          break;                                              \

+        case RCC_USART1CLKSOURCE_PLL2:                        \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \

+          break;                                              \

+        case RCC_USART1CLKSOURCE_PLL3:                        \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \

+          break;                                              \

+        case RCC_USART1CLKSOURCE_HSI:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_USART1CLKSOURCE_CSI:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_USART1CLKSOURCE_LSE:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if((__HANDLE__)->Instance == USART2)                 \

+    {                                                         \

+      switch(__HAL_RCC_GET_USART2_SOURCE())                   \

+      {                                                       \

+        case RCC_USART2CLKSOURCE_D2PCLK1:                     \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \

+          break;                                              \

+        case RCC_USART2CLKSOURCE_PLL2:                        \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \

+          break;                                              \

+        case RCC_USART2CLKSOURCE_PLL3:                        \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \

+          break;                                              \

+        case RCC_USART2CLKSOURCE_HSI:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_USART2CLKSOURCE_CSI:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_USART2CLKSOURCE_LSE:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if((__HANDLE__)->Instance == USART3)                 \

+    {                                                         \

+      switch(__HAL_RCC_GET_USART3_SOURCE())                   \

+      {                                                       \

+        case RCC_USART3CLKSOURCE_D2PCLK1:                     \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \

+          break;                                              \

+        case RCC_USART3CLKSOURCE_PLL2:                        \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \

+          break;                                              \

+        case RCC_USART3CLKSOURCE_PLL3:                        \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \

+          break;                                              \

+        case RCC_USART3CLKSOURCE_HSI:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_USART3CLKSOURCE_CSI:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_USART3CLKSOURCE_LSE:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if((__HANDLE__)->Instance == UART4)                  \

+    {                                                         \

+      switch(__HAL_RCC_GET_UART4_SOURCE())                    \

+      {                                                       \

+        case RCC_UART4CLKSOURCE_D2PCLK1:                      \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \

+          break;                                              \

+        case RCC_UART4CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \

+          break;                                              \

+        case RCC_UART4CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \

+          break;                                              \

+        case RCC_UART4CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_UART4CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_UART4CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if ((__HANDLE__)->Instance == UART5)                 \

+    {                                                         \

+      switch(__HAL_RCC_GET_UART5_SOURCE())                    \

+      {                                                       \

+        case RCC_UART5CLKSOURCE_D2PCLK1:                      \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \

+          break;                                              \

+        case RCC_UART5CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \

+          break;                                              \

+        case RCC_UART5CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \

+          break;                                              \

+        case RCC_UART5CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_UART5CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_UART5CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if((__HANDLE__)->Instance == USART6)                 \

+    {                                                         \

+      switch(__HAL_RCC_GET_USART6_SOURCE())                   \

+      {                                                       \

+        case RCC_USART6CLKSOURCE_D2PCLK2:                     \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2;       \

+          break;                                              \

+        case RCC_USART6CLKSOURCE_PLL2:                        \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \

+          break;                                              \

+        case RCC_USART6CLKSOURCE_PLL3:                        \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \

+          break;                                              \

+        case RCC_USART6CLKSOURCE_HSI:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_USART6CLKSOURCE_CSI:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_USART6CLKSOURCE_LSE:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if((__HANDLE__)->Instance == UART7)                  \

+    {                                                         \

+      switch(__HAL_RCC_GET_UART7_SOURCE())                    \

+      {                                                       \

+        case RCC_UART7CLKSOURCE_D2PCLK1:                      \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \

+          break;                                              \

+        case RCC_UART7CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \

+          break;                                              \

+        case RCC_UART7CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \

+          break;                                              \

+        case RCC_UART7CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_UART7CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_UART7CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if((__HANDLE__)->Instance == UART8)                  \

+    {                                                         \

+      switch(__HAL_RCC_GET_UART8_SOURCE())                    \

+      {                                                       \

+        case RCC_UART8CLKSOURCE_D2PCLK1:                      \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \

+          break;                                              \

+        case RCC_UART8CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \

+          break;                                              \

+        case RCC_UART8CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \

+          break;                                              \

+        case RCC_UART8CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_UART8CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_UART8CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if((__HANDLE__)->Instance == UART9)                  \

+    {                                                         \

+      switch(__HAL_RCC_GET_UART9_SOURCE())                    \

+      {                                                       \

+        case RCC_UART9CLKSOURCE_D2PCLK2:                      \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2;       \

+          break;                                              \

+        case RCC_UART9CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \

+          break;                                              \

+        case RCC_UART9CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \

+          break;                                              \

+        case RCC_UART9CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_UART9CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_UART9CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if((__HANDLE__)->Instance == USART10)                \

+    {                                                         \

+      switch(__HAL_RCC_GET_USART10_SOURCE())                  \

+      {                                                       \

+        case RCC_USART10CLKSOURCE_D2PCLK2:                    \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2;       \

+          break;                                              \

+        case RCC_USART10CLKSOURCE_PLL2:                       \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \

+          break;                                              \

+        case RCC_USART10CLKSOURCE_PLL3:                       \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \

+          break;                                              \

+        case RCC_USART10CLKSOURCE_HSI:                        \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_USART10CLKSOURCE_CSI:                        \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_USART10CLKSOURCE_LSE:                        \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else                                                      \

+    {                                                         \

+      (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;         \

+    }                                                         \

+  } while(0U)

+#else

+#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \

+  do {                                                        \

+    if((__HANDLE__)->Instance == USART1)                      \

+    {                                                         \

+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \

+      {                                                       \

+        case RCC_USART1CLKSOURCE_D2PCLK2:                     \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2;       \

+          break;                                              \

+        case RCC_USART1CLKSOURCE_PLL2:                        \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \

+          break;                                              \

+        case RCC_USART1CLKSOURCE_PLL3:                        \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \

+          break;                                              \

+        case RCC_USART1CLKSOURCE_HSI:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_USART1CLKSOURCE_CSI:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_USART1CLKSOURCE_LSE:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if((__HANDLE__)->Instance == USART2)                 \

+    {                                                         \

+      switch(__HAL_RCC_GET_USART2_SOURCE())                   \

+      {                                                       \

+        case RCC_USART2CLKSOURCE_D2PCLK1:                     \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \

+          break;                                              \

+        case RCC_USART2CLKSOURCE_PLL2:                        \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \

+          break;                                              \

+        case RCC_USART2CLKSOURCE_PLL3:                        \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \

+          break;                                              \

+        case RCC_USART2CLKSOURCE_HSI:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_USART2CLKSOURCE_CSI:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_USART2CLKSOURCE_LSE:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if((__HANDLE__)->Instance == USART3)                 \

+    {                                                         \

+      switch(__HAL_RCC_GET_USART3_SOURCE())                   \

+      {                                                       \

+        case RCC_USART3CLKSOURCE_D2PCLK1:                     \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \

+          break;                                              \

+        case RCC_USART3CLKSOURCE_PLL2:                        \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \

+          break;                                              \

+        case RCC_USART3CLKSOURCE_PLL3:                        \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \

+          break;                                              \

+        case RCC_USART3CLKSOURCE_HSI:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_USART3CLKSOURCE_CSI:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_USART3CLKSOURCE_LSE:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if((__HANDLE__)->Instance == UART4)                  \

+    {                                                         \

+      switch(__HAL_RCC_GET_UART4_SOURCE())                    \

+      {                                                       \

+        case RCC_UART4CLKSOURCE_D2PCLK1:                      \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \

+          break;                                              \

+        case RCC_UART4CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \

+          break;                                              \

+        case RCC_UART4CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \

+          break;                                              \

+        case RCC_UART4CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_UART4CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_UART4CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if ((__HANDLE__)->Instance == UART5)                 \

+    {                                                         \

+      switch(__HAL_RCC_GET_UART5_SOURCE())                    \

+      {                                                       \

+        case RCC_UART5CLKSOURCE_D2PCLK1:                      \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \

+          break;                                              \

+        case RCC_UART5CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \

+          break;                                              \

+        case RCC_UART5CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \

+          break;                                              \

+        case RCC_UART5CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_UART5CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_UART5CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if((__HANDLE__)->Instance == USART6)                 \

+    {                                                         \

+      switch(__HAL_RCC_GET_USART6_SOURCE())                   \

+      {                                                       \

+        case RCC_USART6CLKSOURCE_D2PCLK2:                     \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK2;       \

+          break;                                              \

+        case RCC_USART6CLKSOURCE_PLL2:                        \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \

+          break;                                              \

+        case RCC_USART6CLKSOURCE_PLL3:                        \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \

+          break;                                              \

+        case RCC_USART6CLKSOURCE_HSI:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_USART6CLKSOURCE_CSI:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_USART6CLKSOURCE_LSE:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if((__HANDLE__)->Instance == UART7)                  \

+    {                                                         \

+      switch(__HAL_RCC_GET_UART7_SOURCE())                    \

+      {                                                       \

+        case RCC_UART7CLKSOURCE_D2PCLK1:                      \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \

+          break;                                              \

+        case RCC_UART7CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \

+          break;                                              \

+        case RCC_UART7CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \

+          break;                                              \

+        case RCC_UART7CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_UART7CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_UART7CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if((__HANDLE__)->Instance == UART8)                  \

+    {                                                         \

+      switch(__HAL_RCC_GET_UART8_SOURCE())                    \

+      {                                                       \

+        case RCC_UART8CLKSOURCE_D2PCLK1:                      \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_D2PCLK1;       \

+          break;                                              \

+        case RCC_UART8CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL2Q;         \

+          break;                                              \

+        case RCC_UART8CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_PLL3Q;         \

+          break;                                              \

+        case RCC_UART8CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_UART8CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_UART8CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else                                                      \

+    {                                                         \

+      (__CLOCKSOURCE__) = IRDA_CLOCKSOURCE_UNDEFINED;         \

+    }                                                         \

+  } while(0U)

+#endif /* UART9 && USART10 */

+

+/** @brief  Compute the mask to apply to retrieve the received data

+  *         according to the word length and to the parity bits activation.

+  * @param  __HANDLE__ specifies the IRDA Handle.

+  * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.

+  */

+#define IRDA_MASK_COMPUTATION(__HANDLE__)                             \

+  do {                                                                \

+    if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_9B)          \

+    {                                                                 \

+      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)              \

+      {                                                               \

+        (__HANDLE__)->Mask = 0x01FFU ;                                \

+      }                                                               \

+      else                                                            \

+      {                                                               \

+        (__HANDLE__)->Mask = 0x00FFU ;                                \

+      }                                                               \

+    }                                                                 \

+    else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_8B)     \

+    {                                                                 \

+      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)              \

+      {                                                               \

+        (__HANDLE__)->Mask = 0x00FFU ;                                \

+      }                                                               \

+      else                                                            \

+      {                                                               \

+        (__HANDLE__)->Mask = 0x007FU ;                                \

+      }                                                               \

+    }                                                                 \

+    else if ((__HANDLE__)->Init.WordLength == IRDA_WORDLENGTH_7B)     \

+    {                                                                 \

+      if ((__HANDLE__)->Init.Parity == IRDA_PARITY_NONE)              \

+      {                                                               \

+        (__HANDLE__)->Mask = 0x007FU ;                                \

+      }                                                               \

+      else                                                            \

+      {                                                               \

+        (__HANDLE__)->Mask = 0x003FU ;                                \

+      }                                                               \

+    }                                                                 \

+    else                                                              \

+    {                                                                 \

+      (__HANDLE__)->Mask = 0x0000U;                                   \

+    }                                                                 \

+  } while(0U)

+

+/** @brief Ensure that IRDA frame length is valid.

+  * @param __LENGTH__ IRDA frame length.

+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

+  */

+#define IS_IRDA_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == IRDA_WORDLENGTH_7B) || \

+                                         ((__LENGTH__) == IRDA_WORDLENGTH_8B) || \

+                                         ((__LENGTH__) == IRDA_WORDLENGTH_9B))

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_IRDA_EX_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_iwdg.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_iwdg.h
new file mode 100644
index 0000000000..a5c7b9f913
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_iwdg.h
@@ -0,0 +1,242 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_iwdg.h

+  * @author  MCD Application Team

+  * @brief   Header file of IWDG HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_IWDG_H

+#define STM32H7xx_HAL_IWDG_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @defgroup IWDG IWDG

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup IWDG_Exported_Types IWDG Exported Types

+  * @{

+  */

+

+/**

+  * @brief  IWDG Init structure definition

+  */

+typedef struct

+{

+  uint32_t Prescaler;  /*!< Select the prescaler of the IWDG.

+                            This parameter can be a value of @ref IWDG_Prescaler */

+

+  uint32_t Reload;     /*!< Specifies the IWDG down-counter reload value.

+                            This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */

+

+  uint32_t Window;     /*!< Specifies the window value to be compared to the down-counter.

+                            This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */

+

+} IWDG_InitTypeDef;

+

+/**

+  * @brief  IWDG Handle Structure definition

+  */

+typedef struct

+{

+  IWDG_TypeDef                 *Instance;  /*!< Register base address    */

+

+  IWDG_InitTypeDef             Init;       /*!< IWDG required parameters */

+} IWDG_HandleTypeDef;

+

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup IWDG_Exported_Constants IWDG Exported Constants

+  * @{

+  */

+

+/** @defgroup IWDG_Prescaler IWDG Prescaler

+  * @{

+  */

+#define IWDG_PRESCALER_4                0x00000000u                                     /*!< IWDG prescaler set to 4   */

+#define IWDG_PRESCALER_8                IWDG_PR_PR_0                                    /*!< IWDG prescaler set to 8   */

+#define IWDG_PRESCALER_16               IWDG_PR_PR_1                                    /*!< IWDG prescaler set to 16  */

+#define IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0)                   /*!< IWDG prescaler set to 32  */

+#define IWDG_PRESCALER_64               IWDG_PR_PR_2                                    /*!< IWDG prescaler set to 64  */

+#define IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0)                   /*!< IWDG prescaler set to 128 */

+#define IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1)                   /*!< IWDG prescaler set to 256 */

+

+/**

+  * @}

+  */

+

+/** @defgroup IWDG_Window_option IWDG Window option

+  * @{

+  */

+#define IWDG_WINDOW_DISABLE             IWDG_WINR_WIN

+/**

+  * @}

+  */

+

+

+/**

+  * @}

+  */

+

+/* Exported macros -----------------------------------------------------------*/

+/** @defgroup IWDG_Exported_Macros IWDG Exported Macros

+  * @{

+  */

+

+/**

+  * @brief  Enable the IWDG peripheral.

+  * @param  __HANDLE__  IWDG handle

+  * @retval None

+  */

+#define __HAL_IWDG_START(__HANDLE__)                WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)

+

+/**

+  * @brief  Reload IWDG counter with value defined in the reload register

+  *         (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).

+  * @param  __HANDLE__  IWDG handle

+  * @retval None

+  */

+#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__)       WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup IWDG_Exported_Functions  IWDG Exported Functions

+  * @{

+  */

+

+/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions

+  * @{

+  */

+/* Initialization/Start functions  ********************************************/

+HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);

+/**

+  * @}

+  */

+

+/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions

+  * @{

+  */

+/* I/O operation functions ****************************************************/

+HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup IWDG_Private_Constants IWDG Private Constants

+  * @{

+  */

+

+/**

+  * @brief  IWDG Key Register BitMask

+  */

+#define IWDG_KEY_RELOAD                 0x0000AAAAu  /*!< IWDG Reload Counter Enable   */

+#define IWDG_KEY_ENABLE                 0x0000CCCCu  /*!< IWDG Peripheral Enable       */

+#define IWDG_KEY_WRITE_ACCESS_ENABLE    0x00005555u  /*!< IWDG KR Write Access Enable  */

+#define IWDG_KEY_WRITE_ACCESS_DISABLE   0x00000000u  /*!< IWDG KR Write Access Disable */

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup IWDG_Private_Macros IWDG Private Macros

+  * @{

+  */

+

+/**

+  * @brief  Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

+  * @param  __HANDLE__  IWDG handle

+  * @retval None

+  */

+#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__)  WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)

+

+/**

+  * @brief  Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.

+  * @param  __HANDLE__  IWDG handle

+  * @retval None

+  */

+#define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)

+

+/**

+  * @brief  Check IWDG prescaler value.

+  * @param  __PRESCALER__  IWDG prescaler value

+  * @retval None

+  */

+#define IS_IWDG_PRESCALER(__PRESCALER__)      (((__PRESCALER__) == IWDG_PRESCALER_4)  || \

+                                               ((__PRESCALER__) == IWDG_PRESCALER_8)  || \

+                                               ((__PRESCALER__) == IWDG_PRESCALER_16) || \

+                                               ((__PRESCALER__) == IWDG_PRESCALER_32) || \

+                                               ((__PRESCALER__) == IWDG_PRESCALER_64) || \

+                                               ((__PRESCALER__) == IWDG_PRESCALER_128)|| \

+                                               ((__PRESCALER__) == IWDG_PRESCALER_256))

+

+/**

+  * @brief  Check IWDG reload value.

+  * @param  __RELOAD__  IWDG reload value

+  * @retval None

+  */

+#define IS_IWDG_RELOAD(__RELOAD__)            ((__RELOAD__) <= IWDG_RLR_RL)

+

+/**

+  * @brief  Check IWDG window value.

+  * @param  __WINDOW__  IWDG window value

+  * @retval None

+  */

+#define IS_IWDG_WINDOW(__WINDOW__)            ((__WINDOW__) <= IWDG_WINR_WIN)

+

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_IWDG_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_jpeg.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_jpeg.h
new file mode 100644
index 0000000000..419c435d23
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_jpeg.h
@@ -0,0 +1,655 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_jpeg.h

+  * @author  MCD Application Team

+  * @brief   Header file of JPEG HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_JPEG_H

+#define STM32H7xx_HAL_JPEG_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+#if defined (JPEG)

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup JPEG

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup JPEG_Exported_Types JPEG Exported Types

+  * @{

+  */

+

+/** @defgroup JPEG_Configuration_Structure_definition JPEG Configuration for encoding Structure definition

+  * @brief  JPEG encoding configuration Structure definition

+  * @{

+  */

+typedef struct

+{

+  uint32_t ColorSpace;               /*!< Image Color space : gray-scale, YCBCR, RGB or CMYK

+                                           This parameter can be a value of @ref JPEG_ColorSpace */

+

+  uint32_t ChromaSubsampling;        /*!< Chroma Subsampling in case of YCBCR or CMYK color space, 0-> 4:4:4 , 1-> 4:2:2, 2 -> 4:1:1, 3 -> 4:2:0

+                                           This parameter can be a value of @ref JPEG_ChromaSubsampling */

+

+  uint32_t ImageHeight;              /*!< Image height : number of lines */

+

+  uint32_t ImageWidth;               /*!< Image width : number of pixels per line */

+

+  uint32_t ImageQuality;             /*!< Quality of the JPEG encoding : from 1 to 100 */

+

+} JPEG_ConfTypeDef;

+/**

+  * @}

+  */

+

+/** @defgroup HAL_JPEG_state_structure_definition HAL JPEG state structure definition

+  * @brief  HAL JPEG State structure definition

+  * @{

+  */

+typedef enum

+{

+  HAL_JPEG_STATE_RESET              = 0x00U,  /*!< JPEG not yet initialized or disabled  */

+  HAL_JPEG_STATE_READY              = 0x01U,  /*!< JPEG initialized and ready for use    */

+  HAL_JPEG_STATE_BUSY               = 0x02U,  /*!< JPEG internal processing is ongoing   */

+  HAL_JPEG_STATE_BUSY_ENCODING      = 0x03U,  /*!< JPEG encoding processing is ongoing   */

+  HAL_JPEG_STATE_BUSY_DECODING      = 0x04U,  /*!< JPEG decoding processing is ongoing   */

+  HAL_JPEG_STATE_TIMEOUT            = 0x05U,  /*!< JPEG timeout state                    */

+  HAL_JPEG_STATE_ERROR              = 0x06U   /*!< JPEG error state                      */

+} HAL_JPEG_STATETypeDef;

+

+/**

+  * @}

+  */

+

+

+/** @defgroup JPEG_handle_Structure_definition JPEG handle Structure definition

+  * @brief  JPEG handle Structure definition

+  * @{

+  */

+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)

+typedef struct __JPEG_HandleTypeDef

+#else

+typedef struct

+#endif /* (USE_HAL_JPEG_REGISTER_CALLBACKS) */

+{

+  JPEG_TypeDef             *Instance;        /*!< JPEG peripheral register base address */

+

+  JPEG_ConfTypeDef         Conf;             /*!< Current JPEG encoding/decoding parameters */

+

+  uint8_t                  *pJpegInBuffPtr;  /*!< Pointer to JPEG processing (encoding, decoding,...) input buffer */

+

+  uint8_t                  *pJpegOutBuffPtr; /*!< Pointer to JPEG processing (encoding, decoding,...) output buffer */

+

+  __IO uint32_t            JpegInCount;      /*!< Internal Counter of input data */

+

+  __IO uint32_t            JpegOutCount;     /*!< Internal Counter of output data */

+

+  uint32_t                 InDataLength;     /*!< Input Buffer Length in Bytes */

+

+  uint32_t                 OutDataLength;    /*!< Output Buffer Length in Bytes */

+

+  MDMA_HandleTypeDef        *hdmain;          /*!< JPEG In MDMA handle parameters */

+

+  MDMA_HandleTypeDef        *hdmaout;         /*!< JPEG Out MDMA handle parameters */

+

+  uint8_t                  CustomQuanTable;  /*!< If set to 1 specify that user customized quantization tables are used */

+

+  uint8_t                  *QuantTable0;     /*!< Basic Quantization Table for component 0 */

+

+  uint8_t                  *QuantTable1;     /*!< Basic Quantization Table for component 1 */

+

+  uint8_t                  *QuantTable2;     /*!< Basic Quantization Table for component 2 */

+

+  uint8_t                  *QuantTable3;     /*!< Basic Quantization Table for component 3 */

+

+  HAL_LockTypeDef          Lock;             /*!< JPEG locking object */

+

+  __IO  HAL_JPEG_STATETypeDef State;         /*!< JPEG peripheral state */

+

+  __IO  uint32_t           ErrorCode;        /*!< JPEG Error code */

+

+  __IO uint32_t Context;                     /*!< JPEG Internal context */

+

+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)

+  void (*InfoReadyCallback)(struct __JPEG_HandleTypeDef *hjpeg,

+                            JPEG_ConfTypeDef *pInfo);  /*!< JPEG Info ready callback      */

+  void (*EncodeCpltCallback)(struct __JPEG_HandleTypeDef

+                             *hjpeg);                          /*!< JPEG Encode complete callback */

+  void (*DecodeCpltCallback)(struct __JPEG_HandleTypeDef

+                             *hjpeg);                          /*!< JPEG Decode complete callback */

+  void (*ErrorCallback)(struct __JPEG_HandleTypeDef

+                        *hjpeg);                               /*!< JPEG Error callback           */

+  void (*GetDataCallback)(struct __JPEG_HandleTypeDef *hjpeg,

+                          uint32_t NbDecodedData);     /*!< JPEG Get Data callback        */

+  void (*DataReadyCallback)(struct __JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut,

+                            uint32_t OutDataLength);   /*!< JPEG Data ready callback */

+

+  void (* MspInitCallback)(struct __JPEG_HandleTypeDef *hjpeg);                            /*!< JPEG Msp Init callback  */

+  void (* MspDeInitCallback)(struct __JPEG_HandleTypeDef

+                             *hjpeg);                          /*!< JPEG Msp DeInit callback  */

+

+

+#endif /* (USE_HAL_JPEG_REGISTER_CALLBACKS) */

+

+

+} JPEG_HandleTypeDef;

+/**

+  * @}

+  */

+

+

+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)

+/** @defgroup HAL_JPEG_Callback_ID_enumeration_definition HAL JPEG Callback ID enumeration definition

+  * @brief  HAL JPEG Callback ID enumeration definition

+  * @{

+  */

+typedef enum

+{

+  HAL_JPEG_ENCODE_CPLT_CB_ID    = 0x01U,    /*!< JPEG Encode Complete callback ID */

+  HAL_JPEG_DECODE_CPLT_CB_ID    = 0x02U,    /*!< JPEG Decode Complete callback ID */

+  HAL_JPEG_ERROR_CB_ID          = 0x03U,    /*!< JPEG Error callback ID           */

+

+  HAL_JPEG_MSPINIT_CB_ID        = 0x04U,    /*!< JPEG MspInit callback ID         */

+  HAL_JPEG_MSPDEINIT_CB_ID      = 0x05U     /*!< JPEG MspDeInit callback ID       */

+

+} HAL_JPEG_CallbackIDTypeDef;

+/**

+  * @}

+  */

+

+/** @defgroup HAL_JPEG_Callback_pointer_definition HAL JPEG Callback pointer definition

+  * @brief  HAL JPEG Callback pointer definition

+  * @{

+  */

+typedef  void (*pJPEG_CallbackTypeDef)(JPEG_HandleTypeDef *hjpeg);    /*!< pointer to a common JPEG callback function */

+typedef  void (*pJPEG_InfoReadyCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg,

+                                                JPEG_ConfTypeDef *pInfo);  /*!< pointer to an Info ready JPEG callback function */

+typedef  void (*pJPEG_GetDataCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg,

+                                              uint32_t NbDecodedData);     /*!< pointer to a Get data JPEG callback function */

+typedef  void (*pJPEG_DataReadyCallbackTypeDef)(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut,

+                                                uint32_t OutDataLength);  /*!< pointer to a Data ready JPEG callback function */

+/**

+  * @}

+  */

+

+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+

+/** @defgroup JPEG_Exported_Constants JPEG Exported Constants

+  * @{

+  */

+

+/** @defgroup JPEG_Error_Code_definition JPEG Error Code definition

+  * @brief  JPEG Error Code definition

+  * @{

+  */

+

+#define  HAL_JPEG_ERROR_NONE        ((uint32_t)0x00000000U)    /*!< No error             */

+#define  HAL_JPEG_ERROR_HUFF_TABLE  ((uint32_t)0x00000001U)    /*!< HUffman Table programming error */

+#define  HAL_JPEG_ERROR_QUANT_TABLE ((uint32_t)0x00000002U)    /*!< Quantization Table programming error */

+#define  HAL_JPEG_ERROR_DMA         ((uint32_t)0x00000004U)    /*!< DMA transfer error   */

+#define  HAL_JPEG_ERROR_TIMEOUT     ((uint32_t)0x00000008U)    /*!< Timeout error        */

+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)

+#define  HAL_JPEG_ERROR_INVALID_CALLBACK ((uint32_t)0x00000010U)    /*!< Invalid Callback error  */

+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/** @defgroup JPEG_Quantization_Table_Size JPEG Quantization Table Size

+  * @brief  JPEG Quantization Table Size

+  * @{

+  */

+#define JPEG_QUANT_TABLE_SIZE  ((uint32_t)64U) /*!< JPEG Quantization Table Size in bytes  */

+/**

+  * @}

+  */

+

+

+/** @defgroup JPEG_ColorSpace JPEG ColorSpace

+  * @brief  JPEG Color Space

+  * @{

+  */

+#define JPEG_GRAYSCALE_COLORSPACE     ((uint32_t)0x00000000U)

+#define JPEG_YCBCR_COLORSPACE         JPEG_CONFR1_COLORSPACE_0

+#define JPEG_CMYK_COLORSPACE          JPEG_CONFR1_COLORSPACE

+

+

+/**

+  * @}

+  */

+

+

+/** @defgroup JPEG_ChromaSubsampling JPEG Chrominance Sampling

+  * @brief  JPEG Chrominance Sampling

+  * @{

+  */

+#define JPEG_444_SUBSAMPLING     ((uint32_t)0x00000000U)   /*!< Chroma Subsampling 4:4:4 */

+#define JPEG_420_SUBSAMPLING     ((uint32_t)0x00000001U)   /*!< Chroma Subsampling 4:2:0 */

+#define JPEG_422_SUBSAMPLING     ((uint32_t)0x00000002U)   /*!< Chroma Subsampling 4:2:2 */

+

+/**

+  * @}

+  */

+

+/** @defgroup JPEG_ImageQuality JPEG Image Quality

+  * @brief  JPEG Min and Max Image Quality

+  * @{

+  */

+#define JPEG_IMAGE_QUALITY_MIN     ((uint32_t)1U)     /*!< Minimum JPEG quality */

+#define JPEG_IMAGE_QUALITY_MAX     ((uint32_t)100U)   /*!< Maximum JPEG quality */

+

+/**

+  * @}

+  */

+

+/** @defgroup JPEG_Interrupt_configuration_definition JPEG Interrupt configuration definition

+  * @brief JPEG Interrupt definition

+  * @{

+  */

+#define JPEG_IT_IFT     ((uint32_t)JPEG_CR_IFTIE)   /*!< Input FIFO Threshold Interrupt */

+#define JPEG_IT_IFNF    ((uint32_t)JPEG_CR_IFNFIE)  /*!< Input FIFO Not Full Interrupt */

+#define JPEG_IT_OFT     ((uint32_t)JPEG_CR_OFTIE)   /*!< Output FIFO Threshold Interrupt */

+#define JPEG_IT_OFNE    ((uint32_t)JPEG_CR_OFTIE)   /*!< Output FIFO Not Empty Interrupt */

+#define JPEG_IT_EOC     ((uint32_t)JPEG_CR_EOCIE)   /*!< End of Conversion Interrupt */

+#define JPEG_IT_HPD     ((uint32_t)JPEG_CR_HPDIE)   /*!< Header Parsing Done Interrupt */

+/**

+  * @}

+  */

+

+/** @defgroup JPEG_Flag_definition JPEG Flag definition

+  * @brief JPEG Flags definition

+  * @{

+  */

+#define JPEG_FLAG_IFTF     ((uint32_t)JPEG_SR_IFTF)   /*!< Input FIFO is not full and is bellow its threshold flag */

+#define JPEG_FLAG_IFNFF    ((uint32_t)JPEG_SR_IFNFF)  /*!< Input FIFO Not Full Flag, a data can be written */

+#define JPEG_FLAG_OFTF     ((uint32_t)JPEG_SR_OFTF)   /*!< Output FIFO is not empty and has reach its threshold */

+#define JPEG_FLAG_OFNEF    ((uint32_t)JPEG_SR_OFNEF)  /*!< Output FIFO is not empty, a data is available  */

+#define JPEG_FLAG_EOCF     ((uint32_t)JPEG_SR_EOCF)   /*!< JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO  */

+#define JPEG_FLAG_HPDF     ((uint32_t)JPEG_SR_HPDF)   /*!< JPEG Codec has finished the parsing of the headers and the internal registers have been updated  */

+#define JPEG_FLAG_COF      ((uint32_t)JPEG_SR_COF)    /*!< JPEG Codec operation on going  flag*/

+

+#define JPEG_FLAG_ALL      ((uint32_t)0x000000FEU)     /*!< JPEG Codec All previous flag*/

+/**

+  * @}

+  */

+

+/** @defgroup JPEG_PROCESS_PAUSE_RESUME_definition JPEG Process Pause Resume definition

+  * @brief JPEG process pause, resume definition

+  * @{

+  */

+#define JPEG_PAUSE_RESUME_INPUT          ((uint32_t)0x00000001U)     /*!< Pause/Resume Input FIFO Xfer*/

+#define JPEG_PAUSE_RESUME_OUTPUT         ((uint32_t)0x00000002U)     /*!< Pause/Resume Output FIFO Xfer*/

+#define JPEG_PAUSE_RESUME_INPUT_OUTPUT   ((uint32_t)0x00000003U)     /*!< Pause/Resume Input and Output FIFO Xfer*/

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+/* Exported macro ------------------------------------------------------------*/

+

+/** @defgroup JPEG_Exported_Macros JPEG Exported Macros

+  * @{

+  */

+

+/** @brief Reset JPEG handle state

+  * @param  __HANDLE__ specifies the JPEG handle.

+  * @retval None

+  */

+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)

+#define __HAL_JPEG_RESET_HANDLE_STATE(__HANDLE__) do{\

+                                                      (__HANDLE__)->State = HAL_JPEG_STATE_RESET;\

+                                                      (__HANDLE__)->MspInitCallback = NULL;\

+                                                      (__HANDLE__)->MspDeInitCallback = NULL;\

+                                                      }while(0)

+#else

+#define __HAL_JPEG_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_JPEG_STATE_RESET)

+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */

+

+

+/**

+  * @brief  Enable the JPEG peripheral.

+  * @param  __HANDLE__ specifies the JPEG handle.

+  * @retval None

+  */

+#define __HAL_JPEG_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  JPEG_CR_JCEN)

+

+/**

+  * @brief Disable the JPEG peripheral.

+  * @param  __HANDLE__ specifies the JPEG handle.

+  * @retval None

+  */

+#define __HAL_JPEG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &=  ~JPEG_CR_JCEN)

+

+

+/**

+  * @brief  Check the specified JPEG status flag.

+  * @param  __HANDLE__ specifies the JPEG handle.

+  * @param  __FLAG__  specifies the flag to check

+  *         This parameter can be one of the following values:

+  *         @arg JPEG_FLAG_IFTF  : The input FIFO is not full and is bellow its threshold flag

+  *         @arg JPEG_FLAG_IFNFF : The input FIFO Not Full Flag, a data can be written

+  *         @arg JPEG_FLAG_OFTF  : The output FIFO is not empty and has reach its threshold

+  *         @arg JPEG_FLAG_OFNEF : The output FIFO is not empty, a data is available

+  *         @arg JPEG_FLAG_EOCF  : JPEG Codec core has finished the encoding or the decoding process

+  *                                and than last data has been sent to the output FIFO

+  *         @arg JPEG_FLAG_HPDF  : JPEG Codec has finished the parsing of the headers

+  *                                and the internal registers have been updated

+  *         @arg JPEG_FLAG_COF   : JPEG Codec operation on going  flag

+  *

+  * @retval __HAL_JPEG_GET_FLAG : returns The new state of __FLAG__ (TRUE or FALSE)

+  */

+

+#define __HAL_JPEG_GET_FLAG(__HANDLE__,__FLAG__)  (((__HANDLE__)->Instance->SR & (__FLAG__)))

+

+/**

+  * @brief  Clear the specified JPEG status flag.

+  * @param  __HANDLE__ specifies the JPEG handle.

+  * @param  __FLAG__  specifies the flag to clear

+  *         This parameter can be one of the following values:

+  *         @arg JPEG_FLAG_EOCF  : JPEG Codec core has finished the encoding or the decoding process

+  *                                and than last data has been sent to the output FIFO

+  *         @arg JPEG_FLAG_HPDF  : JPEG Codec has finished the parsing of the headers

+  * @retval None

+  */

+

+#define __HAL_JPEG_CLEAR_FLAG(__HANDLE__,__FLAG__)  (((__HANDLE__)->Instance->CFR |= ((__FLAG__) & (JPEG_FLAG_EOCF | JPEG_FLAG_HPDF))))

+

+

+/**

+  * @brief  Enable Interrupt.

+  * @param   __HANDLE__ specifies the JPEG handle.

+  * @param  __INTERRUPT__  specifies the interrupt to enable

+  *         This parameter can be one of the following values:

+  *         @arg JPEG_IT_IFT   : Input FIFO Threshold Interrupt

+  *         @arg JPEG_IT_IFNF  : Input FIFO Not Full Interrupt

+  *         @arg JPEG_IT_OFT   : Output FIFO Threshold Interrupt

+  *         @arg JPEG_IT_OFNE  : Output FIFO Not empty Interrupt

+  *         @arg JPEG_IT_EOC   : End of Conversion Interrupt

+  *         @arg JPEG_IT_HPD   : Header Parsing Done Interrupt

+  *

+  * @retval No retrun

+  */

+#define __HAL_JPEG_ENABLE_IT(__HANDLE__,__INTERRUPT__)  ((__HANDLE__)->Instance->CR |= (__INTERRUPT__) )

+

+/**

+  * @brief  Disable Interrupt.

+  * @param   __HANDLE__ specifies the JPEG handle.

+  * @param  __INTERRUPT__ specifies the interrupt to disable

+  *         This parameter can be one of the following values:

+  *         @arg JPEG_IT_IFT   : Input FIFO Threshold Interrupt

+  *         @arg JPEG_IT_IFNF  : Input FIFO Not Full Interrupt

+  *         @arg JPEG_IT_OFT   : Output FIFO Threshold Interrupt

+  *         @arg JPEG_IT_OFNE  : Output FIFO Not empty Interrupt

+  *         @arg JPEG_IT_EOC   : End of Conversion Interrupt

+  *         @arg JPEG_IT_HPD   : Header Parsing Done Interrupt

+  *

+  * @note    To disable an IT we must use MODIFY_REG macro to avoid writing "1" to the FIFO flush bits

+  *          located in the same IT enable register (CR register).

+  * @retval  No retrun

+  */

+#define __HAL_JPEG_DISABLE_IT(__HANDLE__,__INTERRUPT__) MODIFY_REG((__HANDLE__)->Instance->CR, (__INTERRUPT__), 0UL)

+

+

+/**

+  * @brief  Get Interrupt state.

+  * @param   __HANDLE__ specifies the JPEG handle.

+  * @param  __INTERRUPT__  specifies the interrupt to check

+  *         This parameter can be one of the following values:

+  *         @arg JPEG_IT_IFT   : Input FIFO Threshold Interrupt

+  *         @arg JPEG_IT_IFNF  : Input FIFO Not Full Interrupt

+  *         @arg JPEG_IT_OFT   : Output FIFO Threshold Interrupt

+  *         @arg JPEG_IT_OFNE  : Output FIFO Not empty Interrupt

+  *         @arg JPEG_IT_EOC   : End of Conversion Interrupt

+  *         @arg JPEG_IT_HPD   : Header Parsing Done Interrupt

+  *

+  * @retval returns The new state of __INTERRUPT__ (Enabled or disabled)

+  */

+#define __HAL_JPEG_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__)     ((__HANDLE__)->Instance->CR & (__INTERRUPT__))

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup JPEG_Exported_Functions

+  * @{

+  */

+

+/** @addtogroup JPEG_Exported_Functions_Group1

+  * @{

+  */

+/* Initialization/de-initialization functions  ********************************/

+HAL_StatusTypeDef HAL_JPEG_Init(JPEG_HandleTypeDef *hjpeg);

+HAL_StatusTypeDef HAL_JPEG_DeInit(JPEG_HandleTypeDef *hjpeg);

+void HAL_JPEG_MspInit(JPEG_HandleTypeDef *hjpeg);

+void HAL_JPEG_MspDeInit(JPEG_HandleTypeDef *hjpeg);

+

+#if (USE_HAL_JPEG_REGISTER_CALLBACKS == 1)

+HAL_StatusTypeDef HAL_JPEG_RegisterCallback(JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID,

+                                            pJPEG_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_JPEG_UnRegisterCallback(JPEG_HandleTypeDef *hjpeg, HAL_JPEG_CallbackIDTypeDef CallbackID);

+

+HAL_StatusTypeDef HAL_JPEG_RegisterInfoReadyCallback(JPEG_HandleTypeDef *hjpeg,

+                                                     pJPEG_InfoReadyCallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_JPEG_UnRegisterInfoReadyCallback(JPEG_HandleTypeDef *hjpeg);

+

+HAL_StatusTypeDef HAL_JPEG_RegisterGetDataCallback(JPEG_HandleTypeDef *hjpeg, pJPEG_GetDataCallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_JPEG_UnRegisterGetDataCallback(JPEG_HandleTypeDef *hjpeg);

+

+HAL_StatusTypeDef HAL_JPEG_RegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg,

+                                                     pJPEG_DataReadyCallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_JPEG_UnRegisterDataReadyCallback(JPEG_HandleTypeDef *hjpeg);

+

+#endif /* USE_HAL_JPEG_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+/** @addtogroup JPEG_Exported_Functions_Group2

+  * @{

+  */

+/* Encoding/Decoding Configuration functions  ********************************/

+HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf);

+HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo);

+HAL_StatusTypeDef HAL_JPEG_EnableHeaderParsing(JPEG_HandleTypeDef *hjpeg);

+HAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing(JPEG_HandleTypeDef *hjpeg);

+HAL_StatusTypeDef HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1,

+                                              uint8_t *QTable2, uint8_t *QTable3);

+

+/**

+  * @}

+  */

+

+/** @addtogroup JPEG_Exported_Functions_Group3

+  * @{

+  */

+/* JPEG processing functions  **************************************/

+HAL_StatusTypeDef  HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength,

+                                   uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout);

+HAL_StatusTypeDef  HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength,

+                                   uint8_t *pDataOutMCU, uint32_t OutDataLength, uint32_t Timeout);

+HAL_StatusTypeDef  HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength,

+                                      uint8_t *pDataOut, uint32_t OutDataLength);

+HAL_StatusTypeDef  HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength,

+                                      uint8_t *pDataOutMCU, uint32_t OutDataLength);

+HAL_StatusTypeDef  HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength,

+                                       uint8_t *pDataOut, uint32_t OutDataLength);

+HAL_StatusTypeDef  HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataIn, uint32_t InDataLength,

+                                       uint8_t *pDataOutMCU, uint32_t OutDataLength);

+HAL_StatusTypeDef  HAL_JPEG_Pause(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection);

+HAL_StatusTypeDef  HAL_JPEG_Resume(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection);

+void HAL_JPEG_ConfigInputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength);

+void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength);

+HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg);

+

+/**

+  * @}

+  */

+

+/** @addtogroup JPEG_Exported_Functions_Group4

+  * @{

+  */

+/* JPEG Decode/Encode callback functions  ********************************************************/

+void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo);

+void HAL_JPEG_EncodeCpltCallback(JPEG_HandleTypeDef *hjpeg);

+void HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg);

+void HAL_JPEG_ErrorCallback(JPEG_HandleTypeDef *hjpeg);

+void HAL_JPEG_GetDataCallback(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData);

+void HAL_JPEG_DataReadyCallback(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength);

+

+/**

+  * @}

+  */

+

+/** @addtogroup JPEG_Exported_Functions_Group5

+  * @{

+  */

+/* JPEG IRQ handler management  ******************************************************/

+void HAL_JPEG_IRQHandler(JPEG_HandleTypeDef *hjpeg);

+

+/**

+  * @}

+  */

+

+/** @addtogroup JPEG_Exported_Functions_Group6

+  * @{

+  */

+/* Peripheral State and Error functions  ************************************************/

+HAL_JPEG_STATETypeDef  HAL_JPEG_GetState(JPEG_HandleTypeDef *hjpeg);

+uint32_t               HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private types -------------------------------------------------------------*/

+/** @defgroup JPEG_Private_Types JPEG Private Types

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private defines -----------------------------------------------------------*/

+/** @defgroup JPEG_Private_Defines JPEG Private Defines

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private variables ---------------------------------------------------------*/

+/** @defgroup JPEG_Private_Variables JPEG Private Variables

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup JPEG_Private_Constants JPEG Private Constants

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup JPEG_Private_Macros JPEG Private Macros

+  * @{

+  */

+

+#define IS_JPEG_CHROMASUBSAMPLING(SUBSAMPLING) (((SUBSAMPLING) == JPEG_444_SUBSAMPLING) || \

+                                                ((SUBSAMPLING) == JPEG_420_SUBSAMPLING) || \

+                                                ((SUBSAMPLING) == JPEG_422_SUBSAMPLING))

+

+#define IS_JPEG_IMAGE_QUALITY(NUMBER) (((NUMBER) >= JPEG_IMAGE_QUALITY_MIN) && ((NUMBER) <= JPEG_IMAGE_QUALITY_MAX))

+

+#define IS_JPEG_COLORSPACE(COLORSPACE) (((COLORSPACE) == JPEG_GRAYSCALE_COLORSPACE) || \

+                                        ((COLORSPACE) == JPEG_YCBCR_COLORSPACE)     || \

+                                        ((COLORSPACE) == JPEG_CMYK_COLORSPACE))

+

+#define IS_JPEG_PAUSE_RESUME_STATE(VALUE) (((VALUE) == JPEG_PAUSE_RESUME_INPUT) || \

+                                           ((VALUE) == JPEG_PAUSE_RESUME_OUTPUT)|| \

+                                           ((VALUE) == JPEG_PAUSE_RESUME_INPUT_OUTPUT))

+

+/**

+  * @}

+  */

+

+/* Private functions prototypes ----------------------------------------------*/

+/** @defgroup JPEG_Private_Functions_Prototypes JPEG Private Functions Prototypes

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private functions ---------------------------------------------------------*/

+/** @defgroup JPEG_Private_Functions JPEG Private Functions

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* JPEG */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_JPEG_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_lptim.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_lptim.h
new file mode 100644
index 0000000000..e2c70be4a3
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_lptim.h
@@ -0,0 +1,810 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_lptim.h

+  * @author  MCD Application Team

+  * @brief   Header file of LPTIM HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_LPTIM_H

+#define STM32H7xx_HAL_LPTIM_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+#if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4) || defined (LPTIM5)

+

+/** @addtogroup LPTIM

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup LPTIM_Exported_Types LPTIM Exported Types

+  * @{

+  */

+

+/**

+  * @brief  LPTIM Clock configuration definition

+  */

+typedef struct

+{

+  uint32_t Source;         /*!< Selects the clock source.

+                           This parameter can be a value of @ref LPTIM_Clock_Source   */

+

+  uint32_t Prescaler;      /*!< Specifies the counter clock Prescaler.

+                           This parameter can be a value of @ref LPTIM_Clock_Prescaler */

+

+} LPTIM_ClockConfigTypeDef;

+

+/**

+  * @brief  LPTIM Clock configuration definition

+  */

+typedef struct

+{

+  uint32_t Polarity;      /*!< Selects the polarity of the active edge for the counter unit

+                           if the ULPTIM input is selected.

+                           Note: This parameter is used only when Ultra low power clock source is used.

+                           Note: If the polarity is configured on 'both edges', an auxiliary clock

+                           (one of the Low power oscillator) must be active.

+                           This parameter can be a value of @ref LPTIM_Clock_Polarity */

+

+  uint32_t SampleTime;     /*!< Selects the clock sampling time to configure the clock glitch filter.

+                           Note: This parameter is used only when Ultra low power clock source is used.

+                           This parameter can be a value of @ref LPTIM_Clock_Sample_Time */

+

+} LPTIM_ULPClockConfigTypeDef;

+

+/**

+  * @brief  LPTIM Trigger configuration definition

+  */

+typedef struct

+{

+  uint32_t Source;        /*!< Selects the Trigger source.

+                          This parameter can be a value of @ref LPTIM_Trigger_Source */

+

+  uint32_t ActiveEdge;    /*!< Selects the Trigger active edge.

+                          Note: This parameter is used only when an external trigger is used.

+                          This parameter can be a value of @ref LPTIM_External_Trigger_Polarity */

+

+  uint32_t SampleTime;    /*!< Selects the trigger sampling time to configure the clock glitch filter.

+                          Note: This parameter is used only when an external trigger is used.

+                          This parameter can be a value of @ref LPTIM_Trigger_Sample_Time  */

+} LPTIM_TriggerConfigTypeDef;

+

+/**

+  * @brief  LPTIM Initialization Structure definition

+  */

+typedef struct

+{

+  LPTIM_ClockConfigTypeDef     Clock;               /*!< Specifies the clock parameters */

+

+  LPTIM_ULPClockConfigTypeDef  UltraLowPowerClock;  /*!< Specifies the Ultra Low Power clock parameters */

+

+  LPTIM_TriggerConfigTypeDef   Trigger;             /*!< Specifies the Trigger parameters */

+

+  uint32_t                     OutputPolarity;      /*!< Specifies the Output polarity.

+                                                    This parameter can be a value of @ref LPTIM_Output_Polarity */

+

+  uint32_t                     UpdateMode;          /*!< Specifies whether the update of the autoreload and the compare

+                                                    values is done immediately or after the end of current period.

+                                                    This parameter can be a value of @ref LPTIM_Updating_Mode */

+

+  uint32_t                     CounterSource;       /*!< Specifies whether the counter is incremented each internal event

+                                                    or each external event.

+                                                    This parameter can be a value of @ref LPTIM_Counter_Source */

+

+  uint32_t                     Input1Source;        /*!< Specifies source selected for input1 (GPIO or comparator output).

+                                                    This parameter can be a value of @ref LPTIM_Input1_Source */

+

+  uint32_t                     Input2Source;        /*!< Specifies source selected for input2 (GPIO or comparator output).

+                                                    Note: This parameter is used only for encoder feature so is used only

+                                                    for LPTIM1 instance.

+                                                    This parameter can be a value of @ref LPTIM_Input2_Source */

+} LPTIM_InitTypeDef;

+

+/**

+  * @brief  HAL LPTIM State structure definition

+  */

+typedef enum

+{

+  HAL_LPTIM_STATE_RESET            = 0x00U,    /*!< Peripheral not yet initialized or disabled  */

+  HAL_LPTIM_STATE_READY            = 0x01U,    /*!< Peripheral Initialized and ready for use    */

+  HAL_LPTIM_STATE_BUSY             = 0x02U,    /*!< An internal process is ongoing              */

+  HAL_LPTIM_STATE_TIMEOUT          = 0x03U,    /*!< Timeout state                               */

+  HAL_LPTIM_STATE_ERROR            = 0x04U     /*!< Internal Process is ongoing                 */

+} HAL_LPTIM_StateTypeDef;

+

+/**

+  * @brief  LPTIM handle Structure definition

+  */

+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)

+typedef struct __LPTIM_HandleTypeDef

+#else

+typedef struct

+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */

+{

+  LPTIM_TypeDef                 *Instance;         /*!< Register base address     */

+

+  LPTIM_InitTypeDef              Init;             /*!< LPTIM required parameters */

+

+  HAL_StatusTypeDef              Status;           /*!< LPTIM peripheral status   */

+

+  HAL_LockTypeDef                Lock;             /*!< LPTIM locking object      */

+

+  __IO  HAL_LPTIM_StateTypeDef   State;            /*!< LPTIM peripheral state    */

+

+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)

+  void (* MspInitCallback)(struct __LPTIM_HandleTypeDef *hlptim);            /*!< LPTIM Base Msp Init Callback                 */

+  void (* MspDeInitCallback)(struct __LPTIM_HandleTypeDef *hlptim);          /*!< LPTIM Base Msp DeInit Callback               */

+  void (* CompareMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim);       /*!< Compare match Callback                       */

+  void (* AutoReloadMatchCallback)(struct __LPTIM_HandleTypeDef *hlptim);    /*!< Auto-reload match Callback                   */

+  void (* TriggerCallback)(struct __LPTIM_HandleTypeDef *hlptim);            /*!< External trigger event detection Callback    */

+  void (* CompareWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim);       /*!< Compare register write complete Callback     */

+  void (* AutoReloadWriteCallback)(struct __LPTIM_HandleTypeDef *hlptim);    /*!< Auto-reload register write complete Callback */

+  void (* DirectionUpCallback)(struct __LPTIM_HandleTypeDef *hlptim);        /*!< Up-counting direction change Callback        */

+  void (* DirectionDownCallback)(struct __LPTIM_HandleTypeDef *hlptim);      /*!< Down-counting direction change Callback      */

+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */

+} LPTIM_HandleTypeDef;

+

+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  HAL LPTIM Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_LPTIM_MSPINIT_CB_ID          = 0x00U,    /*!< LPTIM Base Msp Init Callback ID                  */

+  HAL_LPTIM_MSPDEINIT_CB_ID        = 0x01U,    /*!< LPTIM Base Msp DeInit Callback ID                */

+  HAL_LPTIM_COMPARE_MATCH_CB_ID    = 0x02U,    /*!< Compare match Callback ID                        */

+  HAL_LPTIM_AUTORELOAD_MATCH_CB_ID = 0x03U,    /*!< Auto-reload match Callback ID                    */

+  HAL_LPTIM_TRIGGER_CB_ID          = 0x04U,    /*!< External trigger event detection Callback ID     */

+  HAL_LPTIM_COMPARE_WRITE_CB_ID    = 0x05U,    /*!< Compare register write complete Callback ID      */

+  HAL_LPTIM_AUTORELOAD_WRITE_CB_ID = 0x06U,    /*!< Auto-reload register write complete Callback ID  */

+  HAL_LPTIM_DIRECTION_UP_CB_ID     = 0x07U,    /*!< Up-counting direction change Callback ID         */

+  HAL_LPTIM_DIRECTION_DOWN_CB_ID   = 0x08U,    /*!< Down-counting direction change Callback ID       */

+} HAL_LPTIM_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL TIM Callback pointer definition

+  */

+typedef  void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim);  /*!< pointer to the LPTIM callback function */

+

+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup LPTIM_Exported_Constants LPTIM Exported Constants

+  * @{

+  */

+

+/** @defgroup LPTIM_Clock_Source LPTIM Clock Source

+  * @{

+  */

+#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC        0x00000000U

+#define LPTIM_CLOCKSOURCE_ULPTIM                LPTIM_CFGR_CKSEL

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler

+  * @{

+  */

+#define LPTIM_PRESCALER_DIV1                    0x00000000U

+#define LPTIM_PRESCALER_DIV2                    LPTIM_CFGR_PRESC_0

+#define LPTIM_PRESCALER_DIV4                    LPTIM_CFGR_PRESC_1

+#define LPTIM_PRESCALER_DIV8                    (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1)

+#define LPTIM_PRESCALER_DIV16                   LPTIM_CFGR_PRESC_2

+#define LPTIM_PRESCALER_DIV32                   (LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_2)

+#define LPTIM_PRESCALER_DIV64                   (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_2)

+#define LPTIM_PRESCALER_DIV128                  LPTIM_CFGR_PRESC

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_Output_Polarity LPTIM Output Polarity

+  * @{

+  */

+

+#define LPTIM_OUTPUTPOLARITY_HIGH               0x00000000U

+#define LPTIM_OUTPUTPOLARITY_LOW                LPTIM_CFGR_WAVPOL

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time

+  * @{

+  */

+#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION  0x00000000U

+#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS      LPTIM_CFGR_CKFLT_0

+#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS      LPTIM_CFGR_CKFLT_1

+#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS      LPTIM_CFGR_CKFLT

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_Clock_Polarity LPTIM Clock Polarity

+  * @{

+  */

+#define LPTIM_CLOCKPOLARITY_RISING              0x00000000U

+#define LPTIM_CLOCKPOLARITY_FALLING             LPTIM_CFGR_CKPOL_0

+#define LPTIM_CLOCKPOLARITY_RISING_FALLING      LPTIM_CFGR_CKPOL_1

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source

+  * @{

+  */

+#define LPTIM_TRIGSOURCE_SOFTWARE               0x0000FFFFU

+#define LPTIM_TRIGSOURCE_0                      0x00000000U

+#define LPTIM_TRIGSOURCE_1                      LPTIM_CFGR_TRIGSEL_0

+#define LPTIM_TRIGSOURCE_2                      LPTIM_CFGR_TRIGSEL_1

+#define LPTIM_TRIGSOURCE_3                      (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)

+#define LPTIM_TRIGSOURCE_4                      LPTIM_CFGR_TRIGSEL_2

+#define LPTIM_TRIGSOURCE_5                      (LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_2)

+#define LPTIM_TRIGSOURCE_6                      (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_2)

+#define LPTIM_TRIGSOURCE_7                      LPTIM_CFGR_TRIGSEL

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_External_Trigger_Polarity LPTIM External Trigger Polarity

+  * @{

+  */

+#define LPTIM_ACTIVEEDGE_RISING                LPTIM_CFGR_TRIGEN_0

+#define LPTIM_ACTIVEEDGE_FALLING               LPTIM_CFGR_TRIGEN_1

+#define LPTIM_ACTIVEEDGE_RISING_FALLING        LPTIM_CFGR_TRIGEN

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time

+  * @{

+  */

+#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION  0x00000000U

+#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS      LPTIM_CFGR_TRGFLT_0

+#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS      LPTIM_CFGR_TRGFLT_1

+#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS      LPTIM_CFGR_TRGFLT

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_Updating_Mode LPTIM Updating Mode

+  * @{

+  */

+

+#define LPTIM_UPDATE_IMMEDIATE                  0x00000000U

+#define LPTIM_UPDATE_ENDOFPERIOD                LPTIM_CFGR_PRELOAD

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_Counter_Source LPTIM Counter Source

+  * @{

+  */

+

+#define LPTIM_COUNTERSOURCE_INTERNAL            0x00000000U

+#define LPTIM_COUNTERSOURCE_EXTERNAL            LPTIM_CFGR_COUNTMODE

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_Input1_Source LPTIM Input1 Source

+  * @{

+  */

+

+#define LPTIM_INPUT1SOURCE_GPIO          0x00000000U                                   /*!< For LPTIM1 and LPTIM2 */

+#define LPTIM_INPUT1SOURCE_COMP1         LPTIM_CFGR2_IN1SEL_0                          /*!< For LPTIM1 and LPTIM2 */

+#define LPTIM_INPUT1SOURCE_COMP2         LPTIM_CFGR2_IN1SEL_1                          /*!< For LPTIM2 */

+#define LPTIM_INPUT1SOURCE_COMP1_COMP2   (LPTIM_CFGR2_IN1SEL_1 | LPTIM_CFGR2_IN1SEL_0) /*!< For LPTIM2 */

+#define LPTIM_INPUT1SOURCE_NOT_CONNECTED 0x00000000U                                   /*!< For LPTIM3 */

+#define LPTIM_INPUT1SOURCE_SAI4_FSA      LPTIM_CFGR2_IN1SEL_0                          /*!< For LPTIM3 */

+#define LPTIM_INPUT1SOURCE_SAI4_FSB      LPTIM_CFGR2_IN1SEL_1                          /*!< For LPTIM3 */

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_Input2_Source LPTIM Input2 Source

+  * @{

+  */

+

+#define LPTIM_INPUT2SOURCE_GPIO         0x00000000U                    /*!< For LPTIM1 */

+#define LPTIM_INPUT2SOURCE_COMP2        LPTIM_CFGR2_IN2SEL_0           /*!< For LPTIM1 */

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_Flag_Definition LPTIM Flags Definition

+  * @{

+  */

+

+#define LPTIM_FLAG_DOWN                          LPTIM_ISR_DOWN

+#define LPTIM_FLAG_UP                            LPTIM_ISR_UP

+#define LPTIM_FLAG_ARROK                         LPTIM_ISR_ARROK

+#define LPTIM_FLAG_CMPOK                         LPTIM_ISR_CMPOK

+#define LPTIM_FLAG_EXTTRIG                       LPTIM_ISR_EXTTRIG

+#define LPTIM_FLAG_ARRM                          LPTIM_ISR_ARRM

+#define LPTIM_FLAG_CMPM                          LPTIM_ISR_CMPM

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_Interrupts_Definition LPTIM Interrupts Definition

+  * @{

+  */

+#define LPTIM_IT_DOWN                            LPTIM_IER_DOWNIE

+#define LPTIM_IT_UP                              LPTIM_IER_UPIE

+#define LPTIM_IT_ARROK                           LPTIM_IER_ARROKIE

+#define LPTIM_IT_CMPOK                           LPTIM_IER_CMPOKIE

+#define LPTIM_IT_EXTTRIG                         LPTIM_IER_EXTTRIGIE

+#define LPTIM_IT_ARRM                            LPTIM_IER_ARRMIE

+#define LPTIM_IT_CMPM                            LPTIM_IER_CMPMIE

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macros -----------------------------------------------------------*/

+/** @defgroup LPTIM_Exported_Macros LPTIM Exported Macros

+  * @{

+  */

+

+/** @brief Reset LPTIM handle state.

+  * @param  __HANDLE__ LPTIM handle

+  * @retval None

+  */

+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)

+#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                        \

+                                                      (__HANDLE__)->State             = HAL_LPTIM_STATE_RESET; \

+                                                      (__HANDLE__)->MspInitCallback   = NULL;                  \

+                                                      (__HANDLE__)->MspDeInitCallback = NULL;                  \

+                                                     } while(0)

+#else

+#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)

+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */

+

+/**

+  * @brief  Enable the LPTIM peripheral.

+  * @param  __HANDLE__ LPTIM handle

+  * @retval None

+  */

+#define __HAL_LPTIM_ENABLE(__HANDLE__)   ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))

+

+/**

+  * @brief  Disable the LPTIM peripheral.

+  * @param  __HANDLE__ LPTIM handle

+  * @note   The following sequence is required to solve LPTIM disable HW limitation.

+  *         Please check Errata Sheet ES0335 for more details under "MCU may remain

+  *         stuck in LPTIM interrupt when entering Stop mode" section.

+  * @note   Please call @ref HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to

+  *         check for TIMEOUT.

+  * @retval None

+  */

+#define __HAL_LPTIM_DISABLE(__HANDLE__)   LPTIM_Disable(__HANDLE__)

+

+/**

+  * @brief  Start the LPTIM peripheral in Continuous mode.

+  * @param  __HANDLE__ LPTIM handle

+  * @retval None

+  */

+#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__)  ((__HANDLE__)->Instance->CR |=  LPTIM_CR_CNTSTRT)

+/**

+  * @brief  Start the LPTIM peripheral in single mode.

+  * @param  __HANDLE__ LPTIM handle

+  * @retval None

+  */

+#define __HAL_LPTIM_START_SINGLE(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_SNGSTRT)

+

+/**

+  * @brief  Reset the LPTIM Counter register in synchronous mode.

+  * @param  __HANDLE__ LPTIM handle

+  * @retval None

+  */

+#define __HAL_LPTIM_RESET_COUNTER(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_COUNTRST)

+

+/**

+  * @brief  Reset after read of the LPTIM Counter register in asynchronous mode.

+  * @param  __HANDLE__ LPTIM handle

+  * @retval None

+  */

+#define __HAL_LPTIM_RESET_COUNTER_AFTERREAD(__HANDLE__)      ((__HANDLE__)->Instance->CR |=  LPTIM_CR_RSTARE)

+

+/**

+  * @brief  Write the passed parameter in the Autoreload register.

+  * @param  __HANDLE__ LPTIM handle

+  * @param  __VALUE__ Autoreload value

+  * @retval None

+  * @note   The ARR register can only be modified when the LPTIM instance is enabled.

+  */

+#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__)  ((__HANDLE__)->Instance->ARR =  (__VALUE__))

+

+/**

+  * @brief  Write the passed parameter in the Compare register.

+  * @param  __HANDLE__ LPTIM handle

+  * @param  __VALUE__ Compare value

+  * @retval None

+  * @note   The CMP register can only be modified when the LPTIM instance is enabled.

+  */

+#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__)     ((__HANDLE__)->Instance->CMP =  (__VALUE__))

+

+/**

+  * @brief  Check whether the specified LPTIM flag is set or not.

+  * @param  __HANDLE__ LPTIM handle

+  * @param  __FLAG__ LPTIM flag to check

+  *            This parameter can be a value of:

+  *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.

+  *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.

+  *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.

+  *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.

+  *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.

+  *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.

+  *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.

+  * @retval The state of the specified flag (SET or RESET).

+  */

+#define __HAL_LPTIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->ISR &(__FLAG__)) == (__FLAG__))

+

+/**

+  * @brief  Clear the specified LPTIM flag.

+  * @param  __HANDLE__ LPTIM handle.

+  * @param  __FLAG__ LPTIM flag to clear.

+  *            This parameter can be a value of:

+  *            @arg LPTIM_FLAG_DOWN    : Counter direction change up Flag.

+  *            @arg LPTIM_FLAG_UP      : Counter direction change down to up Flag.

+  *            @arg LPTIM_FLAG_ARROK   : Autoreload register update OK Flag.

+  *            @arg LPTIM_FLAG_CMPOK   : Compare register update OK Flag.

+  *            @arg LPTIM_FLAG_EXTTRIG : External trigger edge event Flag.

+  *            @arg LPTIM_FLAG_ARRM    : Autoreload match Flag.

+  *            @arg LPTIM_FLAG_CMPM    : Compare match Flag.

+  * @retval None.

+  */

+#define __HAL_LPTIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->ICR  = (__FLAG__))

+

+/**

+  * @brief  Enable the specified LPTIM interrupt.

+  * @param  __HANDLE__ LPTIM handle.

+  * @param  __INTERRUPT__ LPTIM interrupt to set.

+  *            This parameter can be a value of:

+  *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.

+  *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.

+  *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.

+  *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.

+  *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.

+  *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.

+  *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.

+  * @retval None.

+  * @note   The LPTIM interrupts can only be enabled when the LPTIM instance is disabled.

+  */

+#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->IER  |= (__INTERRUPT__))

+

+/**

+  * @brief  Disable the specified LPTIM interrupt.

+  * @param  __HANDLE__ LPTIM handle.

+  * @param  __INTERRUPT__ LPTIM interrupt to set.

+  *            This parameter can be a value of:

+  *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.

+  *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.

+  *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.

+  *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.

+  *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.

+  *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.

+  *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.

+  * @retval None.

+  * @note   The LPTIM interrupts can only be disabled when the LPTIM instance is disabled.

+  */

+#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IER  &= (~(__INTERRUPT__)))

+

+/**

+  * @brief  Check whether the specified LPTIM interrupt source is enabled or not.

+  * @param  __HANDLE__ LPTIM handle.

+  * @param  __INTERRUPT__ LPTIM interrupt to check.

+  *            This parameter can be a value of:

+  *            @arg LPTIM_IT_DOWN    : Counter direction change up Interrupt.

+  *            @arg LPTIM_IT_UP      : Counter direction change down to up Interrupt.

+  *            @arg LPTIM_IT_ARROK   : Autoreload register update OK Interrupt.

+  *            @arg LPTIM_IT_CMPOK   : Compare register update OK Interrupt.

+  *            @arg LPTIM_IT_EXTTRIG : External trigger edge event Interrupt.

+  *            @arg LPTIM_IT_ARRM    : Autoreload match Interrupt.

+  *            @arg LPTIM_IT_CMPM    : Compare match Interrupt.

+  * @retval Interrupt status.

+  */

+

+#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup LPTIM_Exported_Functions LPTIM Exported Functions

+  * @{

+  */

+

+/** @addtogroup LPTIM_Exported_Functions_Group1

+ *  @brief    Initialization and Configuration functions.

+ * @{

+ */

+/* Initialization/de-initialization functions  ********************************/

+HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);

+HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);

+

+/* MSP functions  *************************************************************/

+void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);

+void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);

+/**

+  * @}

+  */

+

+/** @addtogroup LPTIM_Exported_Functions_Group2

+ *  @brief   Start-Stop operation functions.

+ * @{

+ */

+/* Start/Stop operation functions  *********************************************/

+/* ################################# PWM Mode ################################*/

+/* Blocking mode: Polling */

+HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);

+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim);

+/* Non-Blocking mode: Interrupt */

+HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);

+HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim);

+

+/* ############################# One Pulse Mode ##############################*/

+/* Blocking mode: Polling */

+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);

+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim);

+/* Non-Blocking mode: Interrupt */

+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);

+HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim);

+

+/* ############################## Set once Mode ##############################*/

+/* Blocking mode: Polling */

+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);

+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim);

+/* Non-Blocking mode: Interrupt */

+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Pulse);

+HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim);

+

+/* ############################### Encoder Mode ##############################*/

+/* Blocking mode: Polling */

+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);

+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim);

+/* Non-Blocking mode: Interrupt */

+HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);

+HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim);

+

+/* ############################# Time out  Mode ##############################*/

+/* Blocking mode: Polling */

+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);

+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim);

+/* Non-Blocking mode: Interrupt */

+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period, uint32_t Timeout);

+HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim);

+

+/* ############################## Counter Mode ###############################*/

+/* Blocking mode: Polling */

+HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Period);

+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);

+/* Non-Blocking mode: Interrupt */

+HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);

+HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);

+/**

+  * @}

+  */

+

+/** @addtogroup LPTIM_Exported_Functions_Group3

+ *  @brief  Read operation functions.

+ * @{

+ */

+/* Reading operation functions ************************************************/

+uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);

+uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);

+uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);

+/**

+  * @}

+  */

+

+/** @addtogroup LPTIM_Exported_Functions_Group4

+ *  @brief  LPTIM IRQ handler and callback functions.

+ * @{

+ */

+/* LPTIM IRQ functions  *******************************************************/

+void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);

+

+/* CallBack functions  ********************************************************/

+void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim);

+void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim);

+void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim);

+void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim);

+void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim);

+void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);

+void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);

+

+/* Callbacks Register/UnRegister functions  ***********************************/

+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)

+HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);

+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/** @addtogroup LPTIM_Group5

+ *  @brief   Peripheral State functions.

+ * @{

+ */

+/* Peripheral State functions  ************************************************/

+HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private types -------------------------------------------------------------*/

+/** @defgroup LPTIM_Private_Types LPTIM Private Types

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private variables ---------------------------------------------------------*/

+/** @defgroup LPTIM_Private_Variables LPTIM Private Variables

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup LPTIM_Private_Constants LPTIM Private Constants

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup LPTIM_Private_Macros LPTIM Private Macros

+  * @{

+  */

+

+#define IS_LPTIM_CLOCK_SOURCE(__SOURCE__)       (((__SOURCE__) == LPTIM_CLOCKSOURCE_ULPTIM) || \

+                                                 ((__SOURCE__) == LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC))

+

+

+#define IS_LPTIM_CLOCK_PRESCALER(__PRESCALER__) (((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1  ) || \

+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV2  ) || \

+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV4  ) || \

+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV8  ) || \

+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV16 ) || \

+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV32 ) || \

+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV64 ) || \

+                                                 ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV128))

+

+#define IS_LPTIM_CLOCK_PRESCALERDIV1(__PRESCALER__) ((__PRESCALER__) ==  LPTIM_PRESCALER_DIV1)

+

+#define IS_LPTIM_OUTPUT_POLARITY(__POLARITY__)  (((__POLARITY__) == LPTIM_OUTPUTPOLARITY_LOW ) || \

+                                                 ((__POLARITY__) == LPTIM_OUTPUTPOLARITY_HIGH))

+

+#define IS_LPTIM_CLOCK_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION) || \

+                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_2TRANSITIONS)     || \

+                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_4TRANSITIONS)     || \

+                                                    ((__SAMPLETIME__) == LPTIM_CLOCKSAMPLETIME_8TRANSITIONS))

+

+#define IS_LPTIM_CLOCK_POLARITY(__POLARITY__)   (((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING)  || \

+                                                 ((__POLARITY__) == LPTIM_CLOCKPOLARITY_FALLING) || \

+                                                 ((__POLARITY__) == LPTIM_CLOCKPOLARITY_RISING_FALLING))

+

+#define IS_LPTIM_TRG_SOURCE(__TRIG__)           (((__TRIG__) == LPTIM_TRIGSOURCE_SOFTWARE) || \

+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_0) || \

+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_1) || \

+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_2) || \

+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_3) || \

+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_4) || \

+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_5) || \

+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_6) || \

+                                                 ((__TRIG__) == LPTIM_TRIGSOURCE_7))

+

+#define IS_LPTIM_EXT_TRG_POLARITY(__POLARITY__) (((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING         ) || \

+                                                 ((__POLARITY__) == LPTIM_ACTIVEEDGE_FALLING        ) || \

+                                                 ((__POLARITY__) == LPTIM_ACTIVEEDGE_RISING_FALLING ))

+

+#define IS_LPTIM_TRIG_SAMPLE_TIME(__SAMPLETIME__) (((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION) || \

+                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_2TRANSITIONS    ) || \

+                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_4TRANSITIONS    ) || \

+                                                   ((__SAMPLETIME__) == LPTIM_TRIGSAMPLETIME_8TRANSITIONS    ))

+

+#define IS_LPTIM_UPDATE_MODE(__MODE__)          (((__MODE__) == LPTIM_UPDATE_IMMEDIATE) || \

+                                                 ((__MODE__) == LPTIM_UPDATE_ENDOFPERIOD))

+

+#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__)     (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \

+                                                 ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))

+

+#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__)     ((__AUTORELOAD__) <= 0x0000FFFFUL)

+

+#define IS_LPTIM_COMPARE(__COMPARE__)           ((__COMPARE__) <= 0x0000FFFFUL)

+

+#define IS_LPTIM_PERIOD(__PERIOD__)             ((__PERIOD__) <= 0x0000FFFFUL)

+

+#define IS_LPTIM_PULSE(__PULSE__)               ((__PULSE__) <= 0x0000FFFFUL)

+

+#define IS_LPTIM_INPUT1_SOURCE(__INSTANCE__, __SOURCE__)     \

+    ((((__INSTANCE__) == LPTIM1) &&                          \

+     (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||           \

+      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1)))           \

+     ||                                                      \

+     (((__INSTANCE__) == LPTIM2) &&                          \

+     (((__SOURCE__) == LPTIM_INPUT1SOURCE_GPIO) ||           \

+      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1) ||          \

+      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP2) ||          \

+      ((__SOURCE__) == LPTIM_INPUT1SOURCE_COMP1_COMP2)))     \

+     ||                                                      \

+     (((__INSTANCE__) == LPTIM3) &&                          \

+     (((__SOURCE__) == LPTIM_INPUT1SOURCE_NOT_CONNECTED) ||  \

+      ((__SOURCE__) == LPTIM_INPUT1SOURCE_SAI4_FSA) ||       \

+      ((__SOURCE__) == LPTIM_INPUT1SOURCE_SAI4_FSB))))

+

+#define IS_LPTIM_INPUT2_SOURCE(__INSTANCE__, __SOURCE__)  \

+     ((((__INSTANCE__) == LPTIM1) ||                      \

+       ((__INSTANCE__) == LPTIM2)) &&                     \

+     (((__SOURCE__) == LPTIM_INPUT2SOURCE_GPIO) ||        \

+      ((__SOURCE__) == LPTIM_INPUT2SOURCE_COMP2)))

+

+/**

+  * @}

+  */

+

+/* Private functions ---------------------------------------------------------*/

+/** @defgroup LPTIM_Private_Functions LPTIM Private Functions

+  * @{

+  */

+void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* LPTIM1 || LPTIM2 ||  LPTIM3 || LPTIM4 || LPTIM5 */

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_LPTIM_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_ltdc.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_ltdc.h
new file mode 100644
index 0000000000..319068c27a
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_ltdc.h
@@ -0,0 +1,688 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_ltdc.h

+  * @author  MCD Application Team

+  * @brief   Header file of LTDC HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_LTDC_H

+#define STM32H7xx_HAL_LTDC_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+#if defined (LTDC)

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @defgroup LTDC LTDC

+  * @brief LTDC HAL module driver

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup LTDC_Exported_Types LTDC Exported Types

+  * @{

+  */

+#define MAX_LAYER  2U

+

+/**

+  * @brief  LTDC color structure definition

+  */

+typedef struct

+{

+  uint8_t Blue;                    /*!< Configures the blue value.

+                                        This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */

+

+  uint8_t Green;                   /*!< Configures the green value.

+                                        This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */

+

+  uint8_t Red;                     /*!< Configures the red value.

+                                        This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */

+

+  uint8_t Reserved;                /*!< Reserved 0xFF */

+} LTDC_ColorTypeDef;

+

+/**

+  * @brief  LTDC Init structure definition

+  */

+typedef struct

+{

+  uint32_t            HSPolarity;                /*!< configures the horizontal synchronization polarity.

+                                                      This parameter can be one value of @ref LTDC_HS_POLARITY */

+

+  uint32_t            VSPolarity;                /*!< configures the vertical synchronization polarity.

+                                                      This parameter can be one value of @ref LTDC_VS_POLARITY */

+

+  uint32_t            DEPolarity;                /*!< configures the data enable polarity.

+                                                      This parameter can be one of value of @ref LTDC_DE_POLARITY */

+

+  uint32_t            PCPolarity;                /*!< configures the pixel clock polarity.

+                                                      This parameter can be one of value of @ref LTDC_PC_POLARITY */

+

+  uint32_t            HorizontalSync;            /*!< configures the number of Horizontal synchronization width.

+                                                      This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */

+

+  uint32_t            VerticalSync;              /*!< configures the number of Vertical synchronization height.

+                                                      This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */

+

+  uint32_t            AccumulatedHBP;            /*!< configures the accumulated horizontal back porch width.

+                                                      This parameter must be a number between Min_Data = LTDC_HorizontalSync and Max_Data = 0xFFF. */

+

+  uint32_t            AccumulatedVBP;            /*!< configures the accumulated vertical back porch height.

+                                                      This parameter must be a number between Min_Data = LTDC_VerticalSync and Max_Data = 0x7FF. */

+

+  uint32_t            AccumulatedActiveW;        /*!< configures the accumulated active width.

+                                                      This parameter must be a number between Min_Data = LTDC_AccumulatedHBP and Max_Data = 0xFFF. */

+

+  uint32_t            AccumulatedActiveH;        /*!< configures the accumulated active height.

+                                                      This parameter must be a number between Min_Data = LTDC_AccumulatedVBP and Max_Data = 0x7FF. */

+

+  uint32_t            TotalWidth;                /*!< configures the total width.

+                                                      This parameter must be a number between Min_Data = LTDC_AccumulatedActiveW and Max_Data = 0xFFF. */

+

+  uint32_t            TotalHeigh;                /*!< configures the total height.

+                                                      This parameter must be a number between Min_Data = LTDC_AccumulatedActiveH and Max_Data = 0x7FF. */

+

+  LTDC_ColorTypeDef   Backcolor;                 /*!< Configures the background color. */

+} LTDC_InitTypeDef;

+

+/**

+  * @brief  LTDC Layer structure definition

+  */

+typedef struct

+{

+  uint32_t WindowX0;                   /*!< Configures the Window Horizontal Start Position.

+                                            This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */

+

+  uint32_t WindowX1;                   /*!< Configures the Window Horizontal Stop Position.

+                                            This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */

+

+  uint32_t WindowY0;                   /*!< Configures the Window vertical Start Position.

+                                            This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */

+

+  uint32_t WindowY1;                   /*!< Configures the Window vertical Stop Position.

+                                            This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x7FF. */

+

+  uint32_t PixelFormat;                /*!< Specifies the pixel format.

+                                            This parameter can be one of value of @ref LTDC_Pixelformat */

+

+  uint32_t Alpha;                      /*!< Specifies the constant alpha used for blending.

+                                            This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */

+

+  uint32_t Alpha0;                     /*!< Configures the default alpha value.

+                                            This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */

+

+  uint32_t BlendingFactor1;            /*!< Select the blending factor 1.

+                                            This parameter can be one of value of @ref LTDC_BlendingFactor1 */

+

+  uint32_t BlendingFactor2;            /*!< Select the blending factor 2.

+                                            This parameter can be one of value of @ref LTDC_BlendingFactor2 */

+

+  uint32_t FBStartAdress;              /*!< Configures the color frame buffer address */

+

+  uint32_t ImageWidth;                 /*!< Configures the color frame buffer line length.

+                                            This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x1FFF. */

+

+  uint32_t ImageHeight;                /*!< Specifies the number of line in frame buffer.

+                                            This parameter must be a number between Min_Data = 0x000 and Max_Data = 0x7FF. */

+

+  LTDC_ColorTypeDef   Backcolor;       /*!< Configures the layer background color. */

+} LTDC_LayerCfgTypeDef;

+

+/**

+  * @brief  HAL LTDC State structures definition

+  */

+typedef enum

+{

+  HAL_LTDC_STATE_RESET             = 0x00U,    /*!< LTDC not yet initialized or disabled */

+  HAL_LTDC_STATE_READY             = 0x01U,    /*!< LTDC initialized and ready for use   */

+  HAL_LTDC_STATE_BUSY              = 0x02U,    /*!< LTDC internal process is ongoing     */

+  HAL_LTDC_STATE_TIMEOUT           = 0x03U,    /*!< LTDC Timeout state                   */

+  HAL_LTDC_STATE_ERROR             = 0x04U     /*!< LTDC state error                     */

+} HAL_LTDC_StateTypeDef;

+

+/**

+  * @brief  LTDC handle Structure definition

+  */

+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)

+typedef struct __LTDC_HandleTypeDef

+#else

+typedef struct

+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */

+{

+  LTDC_TypeDef                *Instance;                /*!< LTDC Register base address                */

+

+  LTDC_InitTypeDef            Init;                     /*!< LTDC parameters                           */

+

+  LTDC_LayerCfgTypeDef        LayerCfg[MAX_LAYER];      /*!< LTDC Layers parameters                    */

+

+  HAL_LockTypeDef             Lock;                     /*!< LTDC Lock                                 */

+

+  __IO HAL_LTDC_StateTypeDef  State;                    /*!< LTDC state                                */

+

+  __IO uint32_t               ErrorCode;                /*!< LTDC Error code                           */

+

+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)

+  void (* LineEventCallback)(struct __LTDC_HandleTypeDef *hltdc);     /*!< LTDC Line Event Callback    */

+  void (* ReloadEventCallback)(struct __LTDC_HandleTypeDef *hltdc);   /*!< LTDC Reload Event Callback  */

+  void (* ErrorCallback)(struct __LTDC_HandleTypeDef *hltdc);         /*!< LTDC Error Callback         */

+

+  void (* MspInitCallback)(struct __LTDC_HandleTypeDef *hltdc);       /*!< LTDC Msp Init callback      */

+  void (* MspDeInitCallback)(struct __LTDC_HandleTypeDef *hltdc);     /*!< LTDC Msp DeInit callback    */

+

+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */

+

+

+} LTDC_HandleTypeDef;

+

+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  HAL LTDC Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_LTDC_MSPINIT_CB_ID            = 0x00U,    /*!< LTDC MspInit callback ID       */

+  HAL_LTDC_MSPDEINIT_CB_ID          = 0x01U,    /*!< LTDC MspDeInit callback ID     */

+

+  HAL_LTDC_LINE_EVENT_CB_ID         = 0x02U,    /*!< LTDC Line Event Callback ID    */

+  HAL_LTDC_RELOAD_EVENT_CB_ID       = 0x03U,    /*!< LTDC Reload Callback ID        */

+  HAL_LTDC_ERROR_CB_ID              = 0x04U     /*!< LTDC Error Callback ID         */

+

+} HAL_LTDC_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL LTDC Callback pointer definition

+  */

+typedef  void (*pLTDC_CallbackTypeDef)(LTDC_HandleTypeDef *hltdc);  /*!< pointer to an LTDC callback function */

+

+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup LTDC_Exported_Constants LTDC Exported Constants

+  * @{

+  */

+

+/** @defgroup LTDC_Error_Code LTDC Error Code

+  * @{

+  */

+#define HAL_LTDC_ERROR_NONE               0x00000000U   /*!< LTDC No error             */

+#define HAL_LTDC_ERROR_TE                 0x00000001U   /*!< LTDC Transfer error       */

+#define HAL_LTDC_ERROR_FU                 0x00000002U   /*!< LTDC FIFO Underrun        */

+#define HAL_LTDC_ERROR_TIMEOUT            0x00000020U   /*!< LTDC Timeout error        */

+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)

+#define  HAL_LTDC_ERROR_INVALID_CALLBACK  0x00000040U   /*!< LTDC Invalid Callback error  */

+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/** @defgroup LTDC_Layer LTDC Layer

+  * @{

+  */

+#define LTDC_LAYER_1                      0x00000000U   /*!< LTDC Layer 1 */

+#define LTDC_LAYER_2                      0x00000001U   /*!< LTDC Layer 2 */

+/**

+  * @}

+  */

+

+/** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY

+  * @{

+  */

+#define LTDC_HSPOLARITY_AL                0x00000000U   /*!< Horizontal Synchronization is active low. */

+#define LTDC_HSPOLARITY_AH                LTDC_GCR_HSPOL            /*!< Horizontal Synchronization is active high. */

+/**

+  * @}

+  */

+

+/** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY

+  * @{

+  */

+#define LTDC_VSPOLARITY_AL                0x00000000U   /*!< Vertical Synchronization is active low. */

+#define LTDC_VSPOLARITY_AH                LTDC_GCR_VSPOL            /*!< Vertical Synchronization is active high. */

+/**

+  * @}

+  */

+

+/** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY

+  * @{

+  */

+#define LTDC_DEPOLARITY_AL                0x00000000U   /*!< Data Enable, is active low. */

+#define LTDC_DEPOLARITY_AH                LTDC_GCR_DEPOL            /*!< Data Enable, is active high. */

+/**

+  * @}

+  */

+

+/** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY

+  * @{

+  */

+#define LTDC_PCPOLARITY_IPC               0x00000000U   /*!< input pixel clock. */

+#define LTDC_PCPOLARITY_IIPC              LTDC_GCR_PCPOL            /*!< inverted input pixel clock. */

+/**

+  * @}

+  */

+

+/** @defgroup LTDC_SYNC LTDC SYNC

+  * @{

+  */

+#define LTDC_HORIZONTALSYNC               (LTDC_SSCR_HSW >> 16U)    /*!< Horizontal synchronization width. */

+#define LTDC_VERTICALSYNC                 LTDC_SSCR_VSH             /*!< Vertical synchronization height. */

+/**

+  * @}

+  */

+

+/** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR

+  * @{

+  */

+#define LTDC_COLOR                        0x000000FFU   /*!< Color mask */

+/**

+  * @}

+  */

+

+/** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1

+  * @{

+  */

+#define LTDC_BLENDING_FACTOR1_CA          0x00000400U   /*!< Blending factor : Cte Alpha */

+#define LTDC_BLENDING_FACTOR1_PAxCA       0x00000600U   /*!< Blending factor : Cte Alpha x Pixel Alpha*/

+/**

+  * @}

+  */

+

+/** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2

+  * @{

+  */

+#define LTDC_BLENDING_FACTOR2_CA          0x00000005U   /*!< Blending factor : Cte Alpha */

+#define LTDC_BLENDING_FACTOR2_PAxCA       0x00000007U   /*!< Blending factor : Cte Alpha x Pixel Alpha*/

+/**

+  * @}

+  */

+

+/** @defgroup LTDC_Pixelformat LTDC Pixel format

+  * @{

+  */

+#define LTDC_PIXEL_FORMAT_ARGB8888        0x00000000U   /*!< ARGB8888 LTDC pixel format */

+#define LTDC_PIXEL_FORMAT_RGB888          0x00000001U   /*!< RGB888 LTDC pixel format   */

+#define LTDC_PIXEL_FORMAT_RGB565          0x00000002U   /*!< RGB565 LTDC pixel format   */

+#define LTDC_PIXEL_FORMAT_ARGB1555        0x00000003U   /*!< ARGB1555 LTDC pixel format */

+#define LTDC_PIXEL_FORMAT_ARGB4444        0x00000004U   /*!< ARGB4444 LTDC pixel format */

+#define LTDC_PIXEL_FORMAT_L8              0x00000005U   /*!< L8 LTDC pixel format       */

+#define LTDC_PIXEL_FORMAT_AL44            0x00000006U   /*!< AL44 LTDC pixel format     */

+#define LTDC_PIXEL_FORMAT_AL88            0x00000007U   /*!< AL88 LTDC pixel format     */

+/**

+  * @}

+  */

+

+/** @defgroup LTDC_Alpha LTDC Alpha

+  * @{

+  */

+#define LTDC_ALPHA                        LTDC_LxCACR_CONSTA        /*!< LTDC Constant Alpha mask */

+/**

+  * @}

+  */

+

+/** @defgroup LTDC_LAYER_Config LTDC LAYER Config

+  * @{

+  */

+#define LTDC_STOPPOSITION                 (LTDC_LxWHPCR_WHSPPOS >> 16U) /*!< LTDC Layer stop position  */

+#define LTDC_STARTPOSITION                LTDC_LxWHPCR_WHSTPOS          /*!< LTDC Layer start position */

+

+#define LTDC_COLOR_FRAME_BUFFER           LTDC_LxCFBLR_CFBLL            /*!< LTDC Layer Line length    */

+#define LTDC_LINE_NUMBER                  LTDC_LxCFBLNR_CFBLNBR         /*!< LTDC Layer Line number    */

+/**

+  * @}

+  */

+

+/** @defgroup LTDC_Interrupts LTDC Interrupts

+  * @{

+  */

+#define LTDC_IT_LI                        LTDC_IER_LIE              /*!< LTDC Line Interrupt            */

+#define LTDC_IT_FU                        LTDC_IER_FUIE             /*!< LTDC FIFO Underrun Interrupt   */

+#define LTDC_IT_TE                        LTDC_IER_TERRIE           /*!< LTDC Transfer Error Interrupt  */

+#define LTDC_IT_RR                        LTDC_IER_RRIE             /*!< LTDC Register Reload Interrupt */

+/**

+  * @}

+  */

+

+/** @defgroup LTDC_Flags LTDC Flags

+  * @{

+  */

+#define LTDC_FLAG_LI                      LTDC_ISR_LIF              /*!< LTDC Line Interrupt Flag            */

+#define LTDC_FLAG_FU                      LTDC_ISR_FUIF             /*!< LTDC FIFO Underrun interrupt Flag   */

+#define LTDC_FLAG_TE                      LTDC_ISR_TERRIF           /*!< LTDC Transfer Error interrupt Flag  */

+#define LTDC_FLAG_RR                      LTDC_ISR_RRIF             /*!< LTDC Register Reload interrupt Flag */

+/**

+  * @}

+  */

+

+/** @defgroup LTDC_Reload_Type LTDC Reload Type

+  * @{

+  */

+#define LTDC_RELOAD_IMMEDIATE             LTDC_SRCR_IMR             /*!< Immediate Reload */

+#define LTDC_RELOAD_VERTICAL_BLANKING     LTDC_SRCR_VBR             /*!< Vertical Blanking Reload */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup LTDC_Exported_Macros LTDC Exported Macros

+  * @{

+  */

+

+/** @brief Reset LTDC handle state.

+  * @param  __HANDLE__  LTDC handle

+  * @retval None

+  */

+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)

+#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) do{                                                  \

+                                                      (__HANDLE__)->State = HAL_LTDC_STATE_RESET;     \

+                                                      (__HANDLE__)->MspInitCallback = NULL;           \

+                                                      (__HANDLE__)->MspDeInitCallback = NULL;         \

+                                                    } while(0)

+#else

+#define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET)

+#endif /*USE_HAL_LTDC_REGISTER_CALLBACKS */

+

+/**

+  * @brief  Enable the LTDC.

+  * @param  __HANDLE__  LTDC handle

+  * @retval None.

+  */

+#define __HAL_LTDC_ENABLE(__HANDLE__)    ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN)

+

+/**

+  * @brief  Disable the LTDC.

+  * @param  __HANDLE__  LTDC handle

+  * @retval None.

+  */

+#define __HAL_LTDC_DISABLE(__HANDLE__)   ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN))

+

+/**

+  * @brief  Enable the LTDC Layer.

+  * @param  __HANDLE__  LTDC handle

+  * @param  __LAYER__   Specify the layer to be enabled.

+  *                     This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).

+  * @retval None.

+  */

+#define __HAL_LTDC_LAYER_ENABLE(__HANDLE__, __LAYER__)  ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR |= (uint32_t)LTDC_LxCR_LEN)

+

+/**

+  * @brief  Disable the LTDC Layer.

+  * @param  __HANDLE__  LTDC handle

+  * @param  __LAYER__   Specify the layer to be disabled.

+  *                     This parameter can be LTDC_LAYER_1 (0) or LTDC_LAYER_2 (1).

+  * @retval None.

+  */

+#define __HAL_LTDC_LAYER_DISABLE(__HANDLE__, __LAYER__) ((LTDC_LAYER((__HANDLE__), (__LAYER__)))->CR &= ~(uint32_t)LTDC_LxCR_LEN)

+

+/**

+  * @brief  Reload immediately all LTDC Layers.

+  * @param  __HANDLE__  LTDC handle

+  * @retval None.

+  */

+#define __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG(__HANDLE__)  ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR)

+

+/**

+  * @brief  Reload during vertical blanking period all LTDC Layers.

+  * @param  __HANDLE__  LTDC handle

+  * @retval None.

+  */

+#define __HAL_LTDC_VERTICAL_BLANKING_RELOAD_CONFIG(__HANDLE__)  ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_VBR)

+

+/* Interrupt & Flag management */

+/**

+  * @brief  Get the LTDC pending flags.

+  * @param  __HANDLE__  LTDC handle

+  * @param  __FLAG__    Get the specified flag.

+  *          This parameter can be any combination of the following values:

+  *            @arg LTDC_FLAG_LI: Line Interrupt flag

+  *            @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag

+  *            @arg LTDC_FLAG_TE: Transfer Error interrupt flag

+  *            @arg LTDC_FLAG_RR: Register Reload Interrupt Flag

+  * @retval The state of FLAG (SET or RESET).

+  */

+#define __HAL_LTDC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))

+

+/**

+  * @brief  Clears the LTDC pending flags.

+  * @param  __HANDLE__  LTDC handle

+  * @param  __FLAG__    Specify the flag to clear.

+  *          This parameter can be any combination of the following values:

+  *            @arg LTDC_FLAG_LI: Line Interrupt flag

+  *            @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag

+  *            @arg LTDC_FLAG_TE: Transfer Error interrupt flag

+  *            @arg LTDC_FLAG_RR: Register Reload Interrupt Flag

+  * @retval None

+  */

+#define __HAL_LTDC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))

+

+/**

+  * @brief  Enables the specified LTDC interrupts.

+  * @param  __HANDLE__  LTDC handle

+  * @param __INTERRUPT__ Specify the LTDC interrupt sources to be enabled.

+  *          This parameter can be any combination of the following values:

+  *            @arg LTDC_IT_LI: Line Interrupt flag

+  *            @arg LTDC_IT_FU: FIFO Underrun Interrupt flag

+  *            @arg LTDC_IT_TE: Transfer Error interrupt flag

+  *            @arg LTDC_IT_RR: Register Reload Interrupt Flag

+  * @retval None

+  */

+#define __HAL_LTDC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))

+

+/**

+  * @brief  Disables the specified LTDC interrupts.

+  * @param  __HANDLE__  LTDC handle

+  * @param __INTERRUPT__ Specify the LTDC interrupt sources to be disabled.

+  *          This parameter can be any combination of the following values:

+  *            @arg LTDC_IT_LI: Line Interrupt flag

+  *            @arg LTDC_IT_FU: FIFO Underrun Interrupt flag

+  *            @arg LTDC_IT_TE: Transfer Error interrupt flag

+  *            @arg LTDC_IT_RR: Register Reload Interrupt Flag

+  * @retval None

+  */

+#define __HAL_LTDC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))

+

+/**

+  * @brief  Check whether the specified LTDC interrupt has occurred or not.

+  * @param  __HANDLE__  LTDC handle

+  * @param __INTERRUPT__ Specify the LTDC interrupt source to check.

+  *          This parameter can be one of the following values:

+  *            @arg LTDC_IT_LI: Line Interrupt flag

+  *            @arg LTDC_IT_FU: FIFO Underrun Interrupt flag

+  *            @arg LTDC_IT_TE: Transfer Error interrupt flag

+  *            @arg LTDC_IT_RR: Register Reload Interrupt Flag

+  * @retval The state of INTERRUPT (SET or RESET).

+  */

+#define __HAL_LTDC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))

+/**

+  * @}

+  */

+

+/* Include LTDC HAL Extension module */

+#include "stm32h7xx_hal_ltdc_ex.h"

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup LTDC_Exported_Functions

+  * @{

+  */

+/** @addtogroup LTDC_Exported_Functions_Group1

+  * @{

+  */

+/* Initialization and de-initialization functions *****************************/

+HAL_StatusTypeDef HAL_LTDC_Init(LTDC_HandleTypeDef *hltdc);

+HAL_StatusTypeDef HAL_LTDC_DeInit(LTDC_HandleTypeDef *hltdc);

+void HAL_LTDC_MspInit(LTDC_HandleTypeDef *hltdc);

+void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef *hltdc);

+void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc);

+void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc);

+void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc);

+

+/* Callbacks Register/UnRegister functions  ***********************************/

+#if (USE_HAL_LTDC_REGISTER_CALLBACKS == 1)

+HAL_StatusTypeDef HAL_LTDC_RegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID, pLTDC_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_LTDC_UnRegisterCallback(LTDC_HandleTypeDef *hltdc, HAL_LTDC_CallbackIDTypeDef CallbackID);

+#endif /* USE_HAL_LTDC_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+/** @addtogroup LTDC_Exported_Functions_Group2

+  * @{

+  */

+/* IO operation functions *****************************************************/

+void  HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc);

+/**

+  * @}

+  */

+

+/** @addtogroup LTDC_Exported_Functions_Group3

+  * @{

+  */

+/* Peripheral Control functions ***********************************************/

+HAL_StatusTypeDef HAL_LTDC_ConfigLayer(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_LTDC_SetWindowSize(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_LTDC_DisableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_LTDC_EnableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line);

+HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc);

+HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc);

+HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType);

+HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);

+HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);

+

+/**

+  * @}

+  */

+

+/** @addtogroup LTDC_Exported_Functions_Group4

+  * @{

+  */

+/* Peripheral State functions *************************************************/

+HAL_LTDC_StateTypeDef HAL_LTDC_GetState(LTDC_HandleTypeDef *hltdc);

+uint32_t              HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup LTDC_Private_Macros LTDC Private Macros

+  * @{

+  */

+#define LTDC_LAYER(__HANDLE__, __LAYER__)              ((LTDC_Layer_TypeDef *)((uint32_t)(((uint32_t)((__HANDLE__)->Instance)) + 0x84U + (0x80U*(__LAYER__)))))

+#define IS_LTDC_LAYER(__LAYER__)                       ((__LAYER__) < MAX_LAYER)

+#define IS_LTDC_HSPOL(__HSPOL__)                       (((__HSPOL__) == LTDC_HSPOLARITY_AL) || ((__HSPOL__) == LTDC_HSPOLARITY_AH))

+#define IS_LTDC_VSPOL(__VSPOL__)                       (((__VSPOL__) == LTDC_VSPOLARITY_AL) || ((__VSPOL__) == LTDC_VSPOLARITY_AH))

+#define IS_LTDC_DEPOL(__DEPOL__)                       (((__DEPOL__) == LTDC_DEPOLARITY_AL) || ((__DEPOL__) ==  LTDC_DEPOLARITY_AH))

+#define IS_LTDC_PCPOL(__PCPOL__)                       (((__PCPOL__) == LTDC_PCPOLARITY_IPC) || ((__PCPOL__) ==  LTDC_PCPOLARITY_IIPC))

+#define IS_LTDC_HSYNC(__HSYNC__)                       ((__HSYNC__)  <= LTDC_HORIZONTALSYNC)

+#define IS_LTDC_VSYNC(__VSYNC__)                       ((__VSYNC__)  <= LTDC_VERTICALSYNC)

+#define IS_LTDC_AHBP(__AHBP__)                         ((__AHBP__)   <= LTDC_HORIZONTALSYNC)

+#define IS_LTDC_AVBP(__AVBP__)                         ((__AVBP__)   <= LTDC_VERTICALSYNC)

+#define IS_LTDC_AAW(__AAW__)                           ((__AAW__)    <= LTDC_HORIZONTALSYNC)

+#define IS_LTDC_AAH(__AAH__)                           ((__AAH__)    <= LTDC_VERTICALSYNC)

+#define IS_LTDC_TOTALW(__TOTALW__)                     ((__TOTALW__) <= LTDC_HORIZONTALSYNC)

+#define IS_LTDC_TOTALH(__TOTALH__)                     ((__TOTALH__) <= LTDC_VERTICALSYNC)

+#define IS_LTDC_BLUEVALUE(__BBLUE__)                   ((__BBLUE__)  <= LTDC_COLOR)

+#define IS_LTDC_GREENVALUE(__BGREEN__)                 ((__BGREEN__) <= LTDC_COLOR)

+#define IS_LTDC_REDVALUE(__BRED__)                     ((__BRED__)   <= LTDC_COLOR)

+#define IS_LTDC_BLENDING_FACTOR1(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_CA) || \

+                                                        ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR1_PAxCA))

+#define IS_LTDC_BLENDING_FACTOR2(__BLENDING_FACTOR1__) (((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_CA) || \

+                                                        ((__BLENDING_FACTOR1__) == LTDC_BLENDING_FACTOR2_PAxCA))

+#define IS_LTDC_PIXEL_FORMAT(__PIXEL_FORMAT__)         (((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB8888) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB888)   || \

+                                                        ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_RGB565)   || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB1555) || \

+                                                        ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_ARGB4444) || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_L8)       || \

+                                                        ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL44)     || ((__PIXEL_FORMAT__) == LTDC_PIXEL_FORMAT_AL88))

+#define IS_LTDC_ALPHA(__ALPHA__)                       ((__ALPHA__) <= LTDC_ALPHA)

+#define IS_LTDC_HCONFIGST(__HCONFIGST__)               ((__HCONFIGST__) <= LTDC_STARTPOSITION)

+#define IS_LTDC_HCONFIGSP(__HCONFIGSP__)               ((__HCONFIGSP__) <= LTDC_STOPPOSITION)

+#define IS_LTDC_VCONFIGST(__VCONFIGST__)               ((__VCONFIGST__) <= LTDC_STARTPOSITION)

+#define IS_LTDC_VCONFIGSP(__VCONFIGSP__)               ((__VCONFIGSP__) <= LTDC_STOPPOSITION)

+#define IS_LTDC_CFBP(__CFBP__)                         ((__CFBP__) <= LTDC_COLOR_FRAME_BUFFER)

+#define IS_LTDC_CFBLL(__CFBLL__)                       ((__CFBLL__) <= LTDC_COLOR_FRAME_BUFFER)

+#define IS_LTDC_CFBLNBR(__CFBLNBR__)                   ((__CFBLNBR__) <= LTDC_LINE_NUMBER)

+#define IS_LTDC_LIPOS(__LIPOS__)                       ((__LIPOS__) <= 0x7FFU)

+#define IS_LTDC_RELOAD(__RELOADTYPE__)                 (((__RELOADTYPE__) == LTDC_RELOAD_IMMEDIATE) || ((__RELOADTYPE__) == LTDC_RELOAD_VERTICAL_BLANKING))

+/**

+  * @}

+  */

+

+/* Private functions ---------------------------------------------------------*/

+/** @defgroup LTDC_Private_Functions LTDC Private Functions

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* LTDC */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_LTDC_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_ltdc_ex.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_ltdc_ex.h
new file mode 100644
index 0000000000..328aab24d0
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_ltdc_ex.h
@@ -0,0 +1,86 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_ltdc_ex.h

+  * @author  MCD Application Team

+  * @brief   Header file of LTDC HAL Extension module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_LTDC_EX_H

+#define STM32H7xx_HAL_LTDC_EX_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+#if defined (LTDC) && defined (DSI)

+

+#include "stm32h7xx_hal_dsi.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup LTDCEx

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/* Exported constants --------------------------------------------------------*/

+/* Exported macro ------------------------------------------------------------*/

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup LTDCEx_Exported_Functions

+  * @{

+  */

+

+/** @addtogroup LTDCEx_Exported_Functions_Group1

+  * @{

+  */

+HAL_StatusTypeDef HAL_LTDCEx_StructInitFromVideoConfig(LTDC_HandleTypeDef *hltdc, DSI_VidCfgTypeDef *VidCfg);

+HAL_StatusTypeDef HAL_LTDCEx_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef *hltdc, DSI_CmdCfgTypeDef *CmdCfg);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/* Private macros ------------------------------------------------------------*/

+/* Private functions ---------------------------------------------------------*/

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* LTDC && DSI */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_LTDC_EX_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_mdios.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_mdios.h
new file mode 100644
index 0000000000..cd68360faf
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_mdios.h
@@ -0,0 +1,610 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_mdios.h

+  * @author  MCD Application Team

+  * @brief   Header file of MDIOS HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_MDIOS_H

+#define STM32H7xx_HAL_MDIOS_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+#if defined (MDIOS)

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup MDIOS

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup MDIOS_Exported_Types MDIOS Exported Types

+  * @{

+  */

+

+/** @defgroup MDIOS_Exported_Types_Group1 MDIOS State structures definition

+  * @{

+  */

+

+typedef enum

+{

+  HAL_MDIOS_STATE_RESET             = 0x00U,    /*!< Peripheral not yet Initialized or disabled         */

+  HAL_MDIOS_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use           */

+  HAL_MDIOS_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing                     */

+  HAL_MDIOS_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                       */

+}HAL_MDIOS_StateTypeDef;

+

+/**

+  * @}

+  */

+

+/** @defgroup MDIOS_Exported_Types_Group2 MDIOS Init Structure definition

+  * @{

+  */

+

+typedef struct

+{

+  uint32_t PortAddress;           /*!< Specifies the MDIOS port address.

+                                       This parameter can be a value from 0 to 31 */

+  uint32_t PreambleCheck;         /*!< Specifies whether the preamble check is enabled or disabled.

+                                       This parameter can be a value of @ref MDIOS_Preamble_Check */

+}MDIOS_InitTypeDef;

+

+/**

+  * @}

+  */

+

+/** @defgroup MDIOS_Exported_Types_Group4 MDIOS handle Structure definition

+  * @{

+  */

+

+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)

+typedef struct __MDIOS_HandleTypeDef

+#else

+typedef struct

+#endif

+{

+  MDIOS_TypeDef                *Instance;     /*!< Register base address       */

+

+  MDIOS_InitTypeDef            Init;          /*!< MDIOS Init Structure        */

+

+  __IO HAL_MDIOS_StateTypeDef  State;         /*!< MDIOS communication state

+                                                   This parameter can be a value of of @ref HAL_MDIOS_StateTypeDef */

+

+  __IO uint32_t                ErrorCode;     /*!< Holds the global Error code of the MDIOS HAL status machine

+                                                   This parameter can be a value of of @ref MDIOS_Error_Code */

+

+  HAL_LockTypeDef              Lock;          /*!< MDIOS Lock                  */

+

+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)

+

+  void    (* WriteCpltCallback)  ( struct __MDIOS_HandleTypeDef * hmdios);   /*!< MDIOS Write Complete Callback */

+  void    (* ReadCpltCallback)   ( struct __MDIOS_HandleTypeDef * hmdios);  /*!< MDIOS Read  Complete Callback     */

+  void    (* ErrorCallback)      ( struct __MDIOS_HandleTypeDef * hmdios);  /*!< MDIOS Error Callback   */

+  void    (* WakeUpCallback)     ( struct __MDIOS_HandleTypeDef * hmdios);  /*!< MDIOS Wake UP Callback   */

+

+  void    (* MspInitCallback)    ( struct __MDIOS_HandleTypeDef * hmdios);    /*!< MDIOS Msp Init callback              */

+  void    (* MspDeInitCallback)  ( struct __MDIOS_HandleTypeDef * hmdios);    /*!< MDIOS Msp DeInit callback            */

+

+#endif  /* USE_HAL_MDIOS_REGISTER_CALLBACKS */

+}MDIOS_HandleTypeDef;

+

+/**

+  * @}

+  */

+

+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  HAL MDIOS Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_MDIOS_MSPINIT_CB_ID            = 0x00U,    /*!< MDIOS MspInit callback ID           */

+  HAL_MDIOS_MSPDEINIT_CB_ID          = 0x01U,    /*!< MDIOS MspDeInit callback ID         */

+

+  HAL_MDIOS_WRITE_COMPLETE_CB_ID     = 0x02U,    /*!< MDIOS Write Complete Callback ID       */

+  HAL_MDIOS_READ_COMPLETE_CB_ID      = 0x03U,    /*!< MDIOS Read Complete Callback ID       */

+  HAL_MDIOS_ERROR_CB_ID              = 0x04U,    /*!< MDIOS Error Callback ID         */

+  HAL_MDIOS_WAKEUP_CB_ID             = 0x05U     /*!< MDIOS Wake UP Callback ID           */

+}HAL_MDIOS_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL MDIOS Callback pointer definition

+  */

+typedef  void (*pMDIOS_CallbackTypeDef)(MDIOS_HandleTypeDef * hmdios); /*!< pointer to an MDIOS callback function */

+

+#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup MDIOS_Exported_Constants MDIOS Exported Constants

+  * @{

+  */

+

+/** @defgroup MDIOS_Preamble_Check  MDIOS Preamble Check

+  * @{

+  */

+#define MDIOS_PREAMBLE_CHECK_ENABLE      ((uint32_t)0x00000000U)

+#define MDIOS_PREAMBLE_CHECK_DISABLE     MDIOS_CR_DPC

+/**

+  * @}

+  */

+

+/** @defgroup MDIOS_Input_Output_Registers_Definitions MDIOS Input Output Registers Definitions

+  * @{

+  */

+#define MDIOS_REG0                      ((uint32_t)0x00000000U)

+#define MDIOS_REG1                      ((uint32_t)0x00000001U)

+#define MDIOS_REG2                      ((uint32_t)0x00000002U)

+#define MDIOS_REG3                      ((uint32_t)0x00000003U)

+#define MDIOS_REG4                      ((uint32_t)0x00000004U)

+#define MDIOS_REG5                      ((uint32_t)0x00000005U)

+#define MDIOS_REG6                      ((uint32_t)0x00000006U)

+#define MDIOS_REG7                      ((uint32_t)0x00000007U)

+#define MDIOS_REG8                      ((uint32_t)0x00000008U)

+#define MDIOS_REG9                      ((uint32_t)0x00000009U)

+#define MDIOS_REG10                     ((uint32_t)0x0000000AU)

+#define MDIOS_REG11                     ((uint32_t)0x0000000BU)

+#define MDIOS_REG12                     ((uint32_t)0x0000000CU)

+#define MDIOS_REG13                     ((uint32_t)0x0000000DU)

+#define MDIOS_REG14                     ((uint32_t)0x0000000EU)

+#define MDIOS_REG15                     ((uint32_t)0x0000000FU)

+#define MDIOS_REG16                     ((uint32_t)0x00000010U)

+#define MDIOS_REG17                     ((uint32_t)0x00000011U)

+#define MDIOS_REG18                     ((uint32_t)0x00000012U)

+#define MDIOS_REG19                     ((uint32_t)0x00000013U)

+#define MDIOS_REG20                     ((uint32_t)0x00000014U)

+#define MDIOS_REG21                     ((uint32_t)0x00000015U)

+#define MDIOS_REG22                     ((uint32_t)0x00000016U)

+#define MDIOS_REG23                     ((uint32_t)0x00000017U)

+#define MDIOS_REG24                     ((uint32_t)0x00000018U)

+#define MDIOS_REG25                     ((uint32_t)0x00000019U)

+#define MDIOS_REG26                     ((uint32_t)0x0000001AU)

+#define MDIOS_REG27                     ((uint32_t)0x0000001BU)

+#define MDIOS_REG28                     ((uint32_t)0x0000001CU)

+#define MDIOS_REG29                     ((uint32_t)0x0000001DU)

+#define MDIOS_REG30                     ((uint32_t)0x0000001EU)

+#define MDIOS_REG31                     ((uint32_t)0x0000001FU)

+/**

+  * @}

+  */

+

+/** @defgroup MDIOS_Registers_Flags  MDIOS Registers Flags

+  * @{

+  */

+#define MDIOS_REG0_FLAG			((uint32_t)0x00000001U)

+#define	MDIOS_REG1_FLAG			((uint32_t)0x00000002U)

+#define	MDIOS_REG2_FLAG			((uint32_t)0x00000004U)

+#define	MDIOS_REG3_FLAG			((uint32_t)0x00000008U)

+#define	MDIOS_REG4_FLAG			((uint32_t)0x00000010U)

+#define	MDIOS_REG5_FLAG			((uint32_t)0x00000020U)

+#define	MDIOS_REG6_FLAG			((uint32_t)0x00000040U)

+#define	MDIOS_REG7_FLAG			((uint32_t)0x00000080U)

+#define	MDIOS_REG8_FLAG			((uint32_t)0x00000100U)

+#define	MDIOS_REG9_FLAG			((uint32_t)0x00000200U)

+#define	MDIOS_REG10_FLAG		((uint32_t)0x00000400U)

+#define	MDIOS_REG11_FLAG		((uint32_t)0x00000800U)

+#define	MDIOS_REG12_FLAG		((uint32_t)0x00001000U)

+#define	MDIOS_REG13_FLAG		((uint32_t)0x00002000U)

+#define	MDIOS_REG14_FLAG		((uint32_t)0x00004000U)

+#define	MDIOS_REG15_FLAG		((uint32_t)0x00008000U)

+#define	MDIOS_REG16_FLAG		((uint32_t)0x00010000U)

+#define	MDIOS_REG17_FLAG		((uint32_t)0x00020000U)

+#define	MDIOS_REG18_FLAG		((uint32_t)0x00040000U)

+#define	MDIOS_REG19_FLAG		((uint32_t)0x00080000U)

+#define	MDIOS_REG20_FLAG		((uint32_t)0x00100000U)

+#define	MDIOS_REG21_FLAG		((uint32_t)0x00200000U)

+#define	MDIOS_REG22_FLAG		((uint32_t)0x00400000U)

+#define	MDIOS_REG23_FLAG		((uint32_t)0x00800000U)

+#define	MDIOS_REG24_FLAG		((uint32_t)0x01000000U)

+#define	MDIOS_REG25_FLAG		((uint32_t)0x02000000U)

+#define	MDIOS_REG26_FLAG		((uint32_t)0x04000000U)

+#define	MDIOS_REG27_FLAG		((uint32_t)0x08000000U)

+#define	MDIOS_REG28_FLAG		((uint32_t)0x10000000U)

+#define	MDIOS_REG29_FLAG		((uint32_t)0x20000000U)

+#define	MDIOS_REG30_FLAG		((uint32_t)0x40000000U)

+#define	MDIOS_REG31_FLAG		((uint32_t)0x80000000U)

+#define	MDIOS_ALLREG_FLAG		((uint32_t)0xFFFFFFFFU)

+/**

+  * @}

+  */

+

+/** @defgroup MDIOS_Interrupt_sources Interrupt Sources

+  * @{

+  */

+#define MDIOS_IT_WRITE                   MDIOS_CR_WRIE

+#define MDIOS_IT_READ                    MDIOS_CR_RDIE

+#define MDIOS_IT_ERROR                   MDIOS_CR_EIE

+/**

+  * @}

+  */

+

+/** @defgroup MDIOS_Interrupt_Flags  MDIOS Interrupt Flags

+  * @{

+  */

+#define	MDIOS_TURNAROUND_ERROR_FLAG       MDIOS_SR_TERF

+#define	MDIOS_START_ERROR_FLAG            MDIOS_SR_SERF

+#define	MDIOS_PREAMBLE_ERROR_FLAG         MDIOS_SR_PERF

+/**

+  * @}

+  */

+

+/** @defgroup MDIOS_Error_Code MDIOS Error Code

+  * @{

+  */

+#define HAL_MDIOS_ERROR_NONE         ((uint32_t)0x00000000U)   /*!< No error            */

+#define HAL_MDIOS_ERROR_PARAM        ((uint32_t)0x00000001U)   /*!< Busy error          */

+#define HAL_MDIOS_ERROR_BUSY         ((uint32_t)0x00000002U)   /*!< Parameter error     */

+#define HAL_MDIOS_ERROR_TIMEOUT      ((uint32_t)0x00000004U)   /*!< Timeout error       */

+#define HAL_MDIOS_ERROR_DATA         ((uint32_t)0x00000010U)   /*!< Data transfer error       */

+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)

+#define HAL_MDIOS_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U)    /*!< Invalid Callback error  */

+#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+ /** @defgroup MDIOS_Wakeup_Line  MDIOS Wakeup Line

+  * @{

+  */

+#define MDIOS_WAKEUP_EXTI_LINE  ((uint32_t)0x00000400)  /* !<  42 - 32 = 10 */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+/* Exported macros -----------------------------------------------------------*/

+/** @defgroup MDIOS_Exported_Macros MDIOS Exported Macros

+  * @{

+  */

+

+/** @brief Reset MDIOS handle state

+  * @param  __HANDLE__: MDIOS handle.

+  * @retval None

+  */

+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)

+#define __HAL_MDIOS_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \

+                                                       (__HANDLE__)->State = HAL_MDIOS_STATE_RESET;      \

+                                                       (__HANDLE__)->MspInitCallback = NULL;             \

+                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \

+                                                     } while(0)

+#else

+#define __HAL_MDIOS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MDIOS_STATE_RESET)

+#endif /*USE_HAL_MDIOS_REGISTER_CALLBACKS */

+

+/**

+  * @brief  Enable/Disable the MDIOS peripheral.

+  * @param  __HANDLE__: specifies the MDIOS handle.

+  * @retval None

+  */

+#define __HAL_MDIOS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= MDIOS_CR_EN)

+#define __HAL_MDIOS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~MDIOS_CR_EN)

+

+

+/**

+  * @brief  Enable the MDIOS device interrupt.

+  * @param  __HANDLE__: specifies the MDIOS handle.

+  * @param  __INTERRUPT__ : specifies the MDIOS interrupt sources to be enabled.

+  *         This parameter can be one or a combination of the following values:

+  *            @arg MDIOS_IT_WRITE: Register write interrupt

+  *            @arg MDIOS_IT_READ: Register read interrupt

+  *            @arg MDIOS_IT_ERROR: Error interrupt

+  * @retval None

+  */

+#define __HAL_MDIOS_ENABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

+

+/**

+  * @brief  Disable the MDIOS device interrupt.

+  * @param  __HANDLE__: specifies the MDIOS handle.

+  * @param  __INTERRUPT__ : specifies the MDIOS interrupt sources to be disabled.

+  *         This parameter can be one or a combination of the following values:

+  *            @arg MDIOS_IT_WRITE: Register write interrupt

+  *            @arg MDIOS_IT_READ: Register read interrupt

+  *            @arg MDIOS_IT_ERROR: Error interrupt

+  * @retval None

+  */

+#define __HAL_MDIOS_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

+

+/** @brief Set MDIOS slave get write register flag

+  * @param  __HANDLE__: specifies the MDIOS handle.

+  * @param  __FLAG__: specifies the write register flag

+  * @retval The state of write flag

+  */

+#define __HAL_MDIOS_GET_WRITE_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->WRFR &  (__FLAG__))

+

+/** @brief MDIOS slave get read register flag

+  * @param  __HANDLE__: specifies the MDIOS handle.

+  * @param  __FLAG__: specifies the read register flag

+  * @retval The state of read flag

+  */

+#define __HAL_MDIOS_GET_READ_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->RDFR &  (__FLAG__))

+

+/** @brief MDIOS slave get interrupt

+  * @param  __HANDLE__: specifies the MDIOS handle.

+  * @param  __FLAG__ : specifies the Error flag.

+  *         This parameter can be one or a combination of the following values:

+  *            @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt

+  *            @arg MDIOS_START_ERROR_FLAG: Register read interrupt

+  *            @arg MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt

+  * @retval The state of the error flag

+  */

+#define __HAL_MDIOS_GET_ERROR_FLAG(__HANDLE__, __FLAG__)       ((__HANDLE__)->Instance->SR &  (__FLAG__))

+

+/** @brief  MDIOS slave clear interrupt

+  * @param  __HANDLE__: specifies the MDIOS handle.

+  * @param  __FLAG__ : specifies the Error flag.

+  *         This parameter can be one or a combination of the following values:

+  *            @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt

+  *            @arg MDIOS_START_ERROR_FLAG: Register read interrupt

+  *            @arg MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt

+  * @retval none

+  */

+#define __HAL_MDIOS_CLEAR_ERROR_FLAG(__HANDLE__, __FLAG__)       ((__HANDLE__)->Instance->CLRFR) |= (__FLAG__)

+

+/**

+  * @brief  Checks whether the specified MDIOS interrupt is set or not.

+  * @param  __HANDLE__: specifies the MDIOS handle.

+  * @param  __INTERRUPT__ : specifies the MDIOS interrupt sources

+  *            This parameter can be one or a combination of the following values:

+  *            @arg MDIOS_IT_WRITE: Register write interrupt

+  *            @arg MDIOS_IT_READ: Register read interrupt

+  *            @arg MDIOS_IT_ERROR: Error interrupt

+  * @retval The state of the interrupt source

+  */

+#define __HAL_MDIOS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))

+

+/**

+  * @brief Enable the MDIOS WAKEUP Exti Line.

+  * @param  __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be enabled.

+  * This parameter can be:

+  *   @arg MDIOS_WAKEUP_EXTI_LINE

+  * @retval None.

+  */

+#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__)   (EXTI->IMR2 |= (__EXTI_LINE__))

+

+#if defined(DUAL_CORE)

+/**

+  * @brief Enable the MDIOS WAKEUP Exti Line by Domain2.

+  * @param  __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be enabled.

+  * This parameter can be:

+  *   @arg MDIOS_WAKEUP_EXTI_LINE

+  * @retval None.

+  */

+#define __HAL_MDIOS_WAKEUP_EXTID2_ENABLE_IT(__EXTI_LINE__)   (EXTI->C2IMR2 |= (__EXTI_LINE__))

+

+#endif

+/**

+  * @brief checks whether the specified MDIOS WAKEUP Exti interrupt flag is set or not.

+  * @param  __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be cleared.

+  * This parameter can be:

+  *   @arg MDIOS_WAKEUP_EXTI_LINE

+  * @retval EXTI MDIOS WAKEUP Line Status.

+  */

+#define __HAL_MDIOS_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__)  (EXTI->PR2 & (__EXTI_LINE__))

+

+#if defined(DUAL_CORE)

+/**

+  * @brief checks whether the specified MDIOS WAKEUP Exti interrupt flag is set or not.

+  * @param  __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be cleared.

+  * This parameter can be:

+  *   @arg MDIOS_WAKEUP_EXTI_LINE

+  * @retval EXTI MDIOS WAKEUP Line Status.

+  */

+#define __HAL_MDIOS_WAKEUP_EXTID2_GET_FLAG(__EXTI_LINE__)  (EXTI->C2PR2 & (__EXTI_LINE__))

+#endif

+/**

+  * @brief Clear the MDIOS WAKEUP Exti flag.

+  * @param  __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be cleared.

+  * This parameter can be:

+  *   @arg MDIOS_WAKEUP_EXTI_LINE

+  * @retval None.

+  */

+#define __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR2 = (__EXTI_LINE__))

+

+#if defined(DUAL_CORE)

+/**

+  * @brief Clear the MDIOS WAKEUP Exti flag.

+  * @param  __EXTI_LINE__: specifies the MDIOS WAKEUP Exti sources to be cleared.

+  * This parameter can be:

+  *   @arg MDIOS_WAKEUP_EXTI_LINE

+  * @retval None.

+  */

+#define __HAL_MDIOS_WAKEUP_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI->C2PR2 = (__EXTI_LINE__))

+

+#endif

+/**

+  * @brief  enable rising edge interrupt on selected EXTI line.

+  * @param  __EXTI_LINE__: specifies the MDIOS WAKEUP EXTI sources to be disabled.

+  * This parameter can be:

+  *  @arg MDIOS_WAKEUP_EXTI_LINE

+  * @retval None

+  */

+#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR2 &= ~(__EXTI_LINE__)); \

+                                                                   (EXTI->RTSR2 |= (__EXTI_LINE__))

+

+/**

+  * @brief  enable falling edge interrupt on selected EXTI line.

+  * @param  __EXTI_LINE__: specifies the MDIOS WAKEUP EXTI sources to be disabled.

+  * This parameter can be:

+  *  @arg MDIOS_WAKEUP_EXTI_LINE

+  * @retval None

+  */

+#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR2 &= ~(__EXTI_LINE__));\

+                                                                 (EXTI->FTSR2 |= (__EXTI_LINE__))

+

+/**

+  * @brief  enable falling edge interrupt on selected EXTI line.

+  * @param  __EXTI_LINE__: specifies the MDIOS WAKEUP EXTI sources to be disabled.

+  * This parameter can be:

+  *  @arg MDIOS_WAKEUP_EXTI_LINE

+  * @retval None

+  */

+#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR2 |= (__EXTI_LINE__));\

+                                                                          (EXTI->FTSR2 |= (__EXTI_LINE__))

+

+/**

+  * @brief  Generates a Software interrupt on selected EXTI line.

+  * @param  __EXTI_LINE__: specifies the MDIOS WAKEUP EXTI sources to be disabled.

+  * This parameter can be:

+  *  @arg MDIOS_WAKEUP_EXTI_LINE

+  * @retval None

+  */

+#define __HAL_MDIOS_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER2 |= (__EXTI_LINE__))

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup MDIOS_Exported_Functions MDIOS Exported Functions

+  * @{

+  */

+

+/** @addtogroup MDIOS_Exported_Functions_Group1

+  * @{

+  */

+HAL_StatusTypeDef HAL_MDIOS_Init(MDIOS_HandleTypeDef *hmdios);

+HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios);

+void HAL_MDIOS_MspInit(MDIOS_HandleTypeDef *hmdios);

+void  HAL_MDIOS_MspDeInit(MDIOS_HandleTypeDef *hmdios);

+

+/* Callbacks Register/UnRegister functions  ***********************************/

+#if (USE_HAL_MDIOS_REGISTER_CALLBACKS == 1)

+HAL_StatusTypeDef HAL_MDIOS_RegisterCallback(MDIOS_HandleTypeDef *hmdios, HAL_MDIOS_CallbackIDTypeDef CallbackID, pMDIOS_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_MDIOS_UnRegisterCallback(MDIOS_HandleTypeDef *hmdios, HAL_MDIOS_CallbackIDTypeDef CallbackID);

+#endif /* USE_HAL_MDIOS_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/** @addtogroup MDIOS_Exported_Functions_Group2

+  * @{

+  */

+HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios,  uint32_t RegNum, uint16_t Data);

+HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios,  uint32_t RegNum, uint16_t *pData);

+

+uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios);

+uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios);

+HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum);

+HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum);

+

+HAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios);

+void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios);

+void HAL_MDIOS_WriteCpltCallback(MDIOS_HandleTypeDef *hmdios);

+void HAL_MDIOS_ReadCpltCallback(MDIOS_HandleTypeDef *hmdios);

+void HAL_MDIOS_ErrorCallback(MDIOS_HandleTypeDef *hmdios);

+void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios);

+/**

+  * @}

+  */

+

+/** @addtogroup MDIOS_Exported_Functions_Group3

+  * @{

+  */

+uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios);

+HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private types -------------------------------------------------------------*/

+/** @defgroup MDIOS_Private_Types MDIOS Private Types

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private variables ---------------------------------------------------------*/

+/** @defgroup MDIOS_Private_Variables MDIOS Private Variables

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup MDIOS_Private_Constants MDIOS Private Constants

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup MDIOS_Private_Macros MDIOS Private Macros

+  * @{

+  */

+

+#define IS_MDIOS_PORTADDRESS(__ADDR__) ((__ADDR__) < 32U)

+

+#define IS_MDIOS_REGISTER(__REGISTER__) ((__REGISTER__) < 32U)

+

+#define IS_MDIOS_PREAMBLECHECK(__PREAMBLECHECK__) (((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_ENABLE) || \

+                                                   ((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_DISABLE))

+

+ /**

+  * @}

+  */

+

+/* Private functions ---------------------------------------------------------*/

+/** @defgroup MDIOS_Private_Functions MDIOS Private Functions

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* MDIOS */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_MDIOS_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_mdma.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_mdma.h
new file mode 100644
index 0000000000..6c1d9b714f
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_mdma.h
@@ -0,0 +1,855 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_mdma.h

+  * @author  MCD Application Team

+  * @brief   Header file of DMA HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_MDMA_H

+#define STM32H7xx_HAL_MDMA_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup MDMA

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+

+/** @defgroup MDMA_Exported_Types MDMA Exported Types

+  * @brief    MDMA Exported Types

+  * @{

+  */

+

+/**

+  * @brief  MDMA Configuration Structure definition

+  */

+typedef struct

+{

+

+  uint32_t Request;                 /*!< Specifies the MDMA request.

+                                        This parameter can be a value of @ref MDMA_Request_selection*/

+

+  uint32_t TransferTriggerMode;     /*!< Specifies the Trigger Transfer mode : each request triggers a :

+                                         a buffer transfer, a block transfer, a repeated block transfer or a linked list transfer

+                                         This parameter can be a value of @ref MDMA_Transfer_TriggerMode  */

+

+  uint32_t Priority;                 /*!< Specifies the software priority for the MDMAy channelx.

+                                         This parameter can be a value of @ref MDMA_Priority_level */

+

+  uint32_t Endianness;                /*!< Specifies if the MDMA transactions preserve the Little endianness.

+                                         This parameter can be a value of @ref MDMA_Endianness */

+

+  uint32_t SourceInc;                /*!< Specifies if the Source increment mode .

+                                         This parameter can be a value of @ref MDMA_Source_increment_mode */

+

+  uint32_t DestinationInc;           /*!< Specifies if the Destination increment mode .

+                                         This parameter can be a value of @ref MDMA_Destination_increment_mode */

+

+  uint32_t SourceDataSize;           /*!< Specifies the source data size.

+                                         This parameter can be a value of @ref MDMA_Source_data_size */

+

+  uint32_t DestDataSize;             /*!< Specifies the destination data size.

+                                          This parameter can be a value of @ref MDMA_Destination_data_size */

+

+

+  uint32_t DataAlignment;            /*!< Specifies the source to destination Memory data packing/padding mode.

+                                            This parameter can be a value of @ref MDMA_data_Alignment */

+

+  uint32_t BufferTransferLength;      /*!< Specifies the buffer Transfer Length (number of bytes),

+                                          this is the number of bytes to be transferred in a single transfer (1 byte to 128 bytes)*/

+

+  uint32_t SourceBurst;              /*!< Specifies the Burst transfer configuration for the source memory transfers.

+                                         It specifies the amount of data to be transferred in a single non interruptable

+                                         transaction.

+                                         This parameter can be a value of @ref MDMA_Source_burst

+                                         @note : the burst may be FIXED/INCR based on SourceInc value ,

+                                         the BURST must be programmed as to ensure that the burst size will be lower than than

+                                         BufferTransferLength */

+

+  uint32_t DestBurst;                 /*!< Specifies the Burst transfer configuration for the destination memory transfers.

+                                           It specifies the amount of data to be transferred in a single non interruptable

+                                           transaction.

+                                           This parameter can be a value of @ref MDMA_Destination_burst

+                                           @note : the burst may be FIXED/INCR based on DestinationInc value ,

+                                           the BURST must be programmed as to ensure that the burst size will be lower than than

+                                           BufferTransferLength */

+

+  int32_t SourceBlockAddressOffset;   /*!< this field specifies the Next block source address offset

+                                           signed value : if > 0 then  increment the next block source Address by offset from where the last block ends

+                                                          if < 0 then  decrement the next block source Address by offset from where the last block ends

+                                                          if == 0, the next block source address starts from where the last block ends

+                                       */

+

+

+  int32_t DestBlockAddressOffset;      /*!< this field specifies the Next block destination address offset

+                                           signed value : if > 0 then  increment the next block destination Address by offset from where the last block ends

+                                                          if < 0 then  decrement the next block destination Address by offset from where the last block ends

+                                                          if == 0, the next block destination address starts from where the last block ends

+                                       */

+

+}MDMA_InitTypeDef;

+

+/**

+  * @brief  HAL MDMA linked list node structure definition

+  * @note   The Linked list node allows to define a new MDMA configuration

+  *         (CTCR ,CBNDTR ,CSAR ,CDAR ,CBRUR, CLAR, CTBR, CMAR and CMDR registers).

+  *         When CLAR register is configured to a non NULL value , each time a transfer ends,

+  *         a new configuration (linked list node) is automatically loaded from the address given in CLAR register.

+  */

+typedef struct

+{

+  __IO uint32_t CTCR;     /*!< New CTCR register configuration for the given MDMA linked list node   */

+  __IO uint32_t CBNDTR;   /*!< New CBNDTR register configuration for the given MDMA linked list node */

+  __IO uint32_t CSAR;     /*!< New CSAR register configuration for the given MDMA linked list node   */

+  __IO uint32_t CDAR;     /*!< New CDAR register configuration for the given MDMA linked list node   */

+  __IO uint32_t CBRUR;    /*!< New CBRUR register configuration for the given MDMA linked list node  */

+  __IO uint32_t CLAR;     /*!< New CLAR register configuration for the given MDMA linked list node   */

+  __IO uint32_t CTBR;     /*!< New CTBR register configuration for the given MDMA linked list node   */

+  __IO uint32_t Reserved; /*!< Reserved register                                                     */

+  __IO uint32_t CMAR;     /*!< New CMAR register configuration for the given MDMA linked list node   */

+  __IO uint32_t CMDR;     /*!< New CMDR register configuration for the given MDMA linked list node   */

+

+}MDMA_LinkNodeTypeDef;

+

+/**

+  * @brief  HAL MDMA linked list node configuration structure definition

+  * @note   used with HAL_MDMA_LinkedList_CreateNode function

+  */

+typedef struct

+{

+  MDMA_InitTypeDef Init;            /*!< configuration of the specified MDMA Linked List Node    */

+  uint32_t         SrcAddress;      /*!< The source memory address for the Linked list Node      */

+  uint32_t         DstAddress;      /*!< The destination memory address for the Linked list Node */

+  uint32_t         BlockDataLength; /*!< The data length of a block in bytes                     */

+  uint32_t         BlockCount;      /*!< The number of blocks to be transferred                  */

+

+  uint32_t PostRequestMaskAddress;  /*!< specifies the address to be updated (written) with PostRequestMaskData after a request is served.

+                                         PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served  */

+

+  uint32_t PostRequestMaskData;     /*!< specifies the value to be written to PostRequestMaskAddress after a request is served.

+                                         PostRequestMaskAddress and PostRequestMaskData could be used to automatically clear a peripheral flag when the request is served  */

+

+

+}MDMA_LinkNodeConfTypeDef;

+

+

+/**

+  * @brief  HAL MDMA State structure definition

+  */

+typedef enum

+{

+  HAL_MDMA_STATE_RESET               = 0x00U,  /*!< MDMA not yet initialized or disabled */

+  HAL_MDMA_STATE_READY               = 0x01U,  /*!< MDMA initialized and ready for use   */

+  HAL_MDMA_STATE_BUSY                = 0x02U,  /*!< MDMA process is ongoing              */

+  HAL_MDMA_STATE_ERROR               = 0x03U,  /*!< MDMA error state                     */

+  HAL_MDMA_STATE_ABORT               = 0x04U,  /*!< MDMA Abort state                     */

+

+}HAL_MDMA_StateTypeDef;

+

+/**

+  * @brief  HAL MDMA Level Complete structure definition

+  */

+typedef enum

+{

+  HAL_MDMA_FULL_TRANSFER         = 0x00U,   /*!< Full transfer         */

+  HAL_MDMA_BUFFER_TRANSFER       = 0x01U,   /*!< Buffer Transfer       */

+  HAL_MDMA_BLOCK_TRANSFER        = 0x02U,   /*!< Block Transfer        */

+  HAL_MDMA_REPEAT_BLOCK_TRANSFER = 0x03U    /*!< repeat block Transfer */

+

+}HAL_MDMA_LevelCompleteTypeDef;

+

+/**

+  * @brief  HAL MDMA Callbacks IDs structure definition

+  */

+typedef enum

+{

+  HAL_MDMA_XFER_CPLT_CB_ID          = 0x00U,    /*!< Full transfer           */

+  HAL_MDMA_XFER_BUFFERCPLT_CB_ID    = 0x01U,    /*!< Buffer Transfer         */

+  HAL_MDMA_XFER_BLOCKCPLT_CB_ID     = 0x02U,    /*!< Block Transfer          */

+  HAL_MDMA_XFER_REPBLOCKCPLT_CB_ID  = 0x03U,    /*!< Repeated Block Transfer */

+  HAL_MDMA_XFER_ERROR_CB_ID         = 0x04U,    /*!< Error                   */

+  HAL_MDMA_XFER_ABORT_CB_ID         = 0x05U,    /*!< Abort                   */

+  HAL_MDMA_XFER_ALL_CB_ID           = 0x06U     /*!< All                     */

+

+}HAL_MDMA_CallbackIDTypeDef;

+

+

+/**

+  * @brief  MDMA handle Structure definition

+  */

+typedef struct __MDMA_HandleTypeDef

+{

+  MDMA_Channel_TypeDef *Instance;                                                              /*!< Register base address                  */

+

+  MDMA_InitTypeDef      Init;                                                                  /*!< MDMA communication parameters          */

+

+  HAL_LockTypeDef       Lock;                                                                  /*!< MDMA locking object                    */

+

+  __IO HAL_MDMA_StateTypeDef  State;                                                           /*!< MDMA transfer state                    */

+

+  void                  *Parent;                                                               /*!< Parent object state                    */

+

+  void                  (* XferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma);            /*!< MDMA transfer complete callback        */

+

+  void                  (* XferBufferCpltCallback)( struct __MDMA_HandleTypeDef * hmdma);      /*!< MDMA buffer transfer complete callback */

+

+  void                  (* XferBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma);       /*!< MDMA block transfer complete callback  */

+

+  void                  (* XferRepeatBlockCpltCallback)( struct __MDMA_HandleTypeDef * hmdma); /*!< MDMA block transfer repeat callback    */

+

+  void                  (* XferErrorCallback)( struct __MDMA_HandleTypeDef * hmdma);           /*!< MDMA transfer error callback           */

+

+  void                  (* XferAbortCallback)( struct __MDMA_HandleTypeDef * hmdma);           /*!< MDMA transfer Abort callback           */

+

+

+  MDMA_LinkNodeTypeDef *FirstLinkedListNodeAddress;                                             /*!< specifies the first node address of the transfer list

+                                                                                                     (after the initial node defined by the Init struct)

+                                                                                                     this parameter is used internally by the MDMA driver

+                                                                                                     to construct the linked list node

+                                                                                                */

+

+  MDMA_LinkNodeTypeDef *LastLinkedListNodeAddress;                                             /*!< specifies the last node address of the transfer list

+                                                                                                    this parameter is used internally by the MDMA driver

+                                                                                                    to construct the linked list node

+                                                                                                */

+  uint32_t LinkedListNodeCounter;                                                               /*!< Number of nodes in the MDMA linked list */

+

+  __IO uint32_t          ErrorCode;                                                            /*!< MDMA Error code                        */

+

+} MDMA_HandleTypeDef;

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+

+/** @defgroup MDMA_Exported_Constants MDMA Exported Constants

+  * @brief    MDMA Exported constants

+  * @{

+  */

+

+/** @defgroup MDMA_Error_Codes MDMA Error Codes

+  * @brief    MDMA Error Codes

+  * @{

+  */

+#define HAL_MDMA_ERROR_NONE        ((uint32_t)0x00000000U)   /*!< No error                               */

+#define HAL_MDMA_ERROR_READ_XFER   ((uint32_t)0x00000001U)   /*!< Read Transfer error                    */

+#define HAL_MDMA_ERROR_WRITE_XFER  ((uint32_t)0x00000002U)   /*!< Write Transfer error                   */

+#define HAL_MDMA_ERROR_MASK_DATA   ((uint32_t)0x00000004U)   /*!< Error Mask Data error                  */

+#define HAL_MDMA_ERROR_LINKED_LIST ((uint32_t)0x00000008U)   /*!< Linked list Data error                 */

+#define HAL_MDMA_ERROR_ALIGNMENT   ((uint32_t)0x00000010U)   /*!< Address/Size alignment  error          */

+#define HAL_MDMA_ERROR_BLOCK_SIZE  ((uint32_t)0x00000020U)   /*!< Block Size error                       */

+#define HAL_MDMA_ERROR_TIMEOUT     ((uint32_t)0x00000040U)   /*!< Timeout error                          */

+#define HAL_MDMA_ERROR_NO_XFER     ((uint32_t)0x00000080U)   /*!< Abort or SW trigger requested with no Xfer ongoing   */

+#define HAL_MDMA_ERROR_BUSY        ((uint32_t)0x00000100U)   /*!< DeInit or SW trigger requested with Xfer ongoing   */

+

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_Request_selection MDMA Request selection

+  * @brief    MDMA_Request_selection

+  * @{

+  */

+

+#define MDMA_REQUEST_DMA1_Stream0_TC      ((uint32_t)0x00000000U)  /*!< MDMA HW request is DMA1 Stream 0 Transfer Complete Flag   */

+#define MDMA_REQUEST_DMA1_Stream1_TC      ((uint32_t)0x00000001U)  /*!< MDMA HW request is DMA1 Stream 1 Transfer Complete Flag   */

+#define MDMA_REQUEST_DMA1_Stream2_TC      ((uint32_t)0x00000002U)  /*!< MDMA HW request is DMA1 Stream 2 Transfer Complete Flag   */

+#define MDMA_REQUEST_DMA1_Stream3_TC      ((uint32_t)0x00000003U)  /*!< MDMA HW request is DMA1 Stream 3 Transfer Complete Flag   */

+#define MDMA_REQUEST_DMA1_Stream4_TC      ((uint32_t)0x00000004U)  /*!< MDMA HW request is DMA1 Stream 4 Transfer Complete Flag   */

+#define MDMA_REQUEST_DMA1_Stream5_TC      ((uint32_t)0x00000005U)  /*!< MDMA HW request is DMA1 Stream 5 Transfer Complete Flag   */

+#define MDMA_REQUEST_DMA1_Stream6_TC      ((uint32_t)0x00000006U)  /*!< MDMA HW request is DMA1 Stream 6 Transfer Complete Flag   */

+#define MDMA_REQUEST_DMA1_Stream7_TC      ((uint32_t)0x00000007U)  /*!< MDMA HW request is DMA1 Stream 7 Transfer Complete Flag   */

+#define MDMA_REQUEST_DMA2_Stream0_TC      ((uint32_t)0x00000008U)  /*!< MDMA HW request is DMA2 Stream 0 Transfer Complete Flag   */

+#define MDMA_REQUEST_DMA2_Stream1_TC      ((uint32_t)0x00000009U)  /*!< MDMA HW request is DMA2 Stream 1 Transfer Complete Flag   */

+#define MDMA_REQUEST_DMA2_Stream2_TC      ((uint32_t)0x0000000AU)  /*!< MDMA HW request is DMA2 Stream 2 Transfer Complete Flag   */

+#define MDMA_REQUEST_DMA2_Stream3_TC      ((uint32_t)0x0000000BU)  /*!< MDMA HW request is DMA2 Stream 3 Transfer Complete Flag   */

+#define MDMA_REQUEST_DMA2_Stream4_TC      ((uint32_t)0x0000000CU)  /*!< MDMA HW request is DMA2 Stream 4 Transfer Complete Flag   */

+#define MDMA_REQUEST_DMA2_Stream5_TC      ((uint32_t)0x0000000DU)  /*!< MDMA HW request is DMA2 Stream 5 Transfer Complete Flag   */

+#define MDMA_REQUEST_DMA2_Stream6_TC      ((uint32_t)0x0000000EU)  /*!< MDMA HW request is DMA2 Stream 6 Transfer Complete Flag   */

+#define MDMA_REQUEST_DMA2_Stream7_TC      ((uint32_t)0x0000000FU)  /*!< MDMA HW request is DMA2 Stream 7 Transfer Complete Flag   */

+#if defined (LTDC)

+#define MDMA_REQUEST_LTDC_LINE_IT         ((uint32_t)0x00000010U)  /*!< MDMA HW request is LTDC Line interrupt Flag               */

+#endif /* LTDC */

+#if defined (JPEG)

+#define MDMA_REQUEST_JPEG_INFIFO_TH       ((uint32_t)0x00000011U)  /*!< MDMA HW request is JPEG Input FIFO threshold Flag         */

+#define MDMA_REQUEST_JPEG_INFIFO_NF       ((uint32_t)0x00000012U)  /*!< MDMA HW request is JPEG Input FIFO not full Flag          */

+#define MDMA_REQUEST_JPEG_OUTFIFO_TH      ((uint32_t)0x00000013U)  /*!< MDMA HW request is JPEG Output FIFO threshold Flag        */

+#define MDMA_REQUEST_JPEG_OUTFIFO_NE      ((uint32_t)0x00000014U)  /*!< MDMA HW request is JPEG Output FIFO not empty Flag        */

+#define MDMA_REQUEST_JPEG_END_CONVERSION  ((uint32_t)0x00000015U)  /*!< MDMA HW request is JPEG End of conversion Flag            */

+#endif /* JPEG */

+#if defined (OCTOSPI1)

+#define MDMA_REQUEST_OCTOSPI1_FIFO_TH     ((uint32_t)0x00000016U)  /*!< MDMA HW request is OCTOSPI1 FIFO threshold Flag           */

+#define MDMA_REQUEST_OCTOSPI1_TC          ((uint32_t)0x00000017U)  /*!< MDMA HW request is OCTOSPI1 Transfer complete Flag        */

+#endif /* OCTOSPI1 */

+#if defined (QUADSPI)

+#define MDMA_REQUEST_QUADSPI_FIFO_TH      ((uint32_t)0x00000016U)  /*!< MDMA HW request is QSPI FIFO threshold Flag               */

+#define MDMA_REQUEST_QUADSPI_TC           ((uint32_t)0x00000017U)  /*!< MDMA HW request is QSPI Transfer complete Flag            */

+#endif /* QUADSPI */

+#define MDMA_REQUEST_DMA2D_CLUT_TC        ((uint32_t)0x00000018U)  /*!< MDMA HW request is DMA2D CLUT Transfer Complete Flag      */

+#define MDMA_REQUEST_DMA2D_TC             ((uint32_t)0x00000019U)  /*!< MDMA HW request is DMA2D Transfer Complete Flag           */

+#define MDMA_REQUEST_DMA2D_TW             ((uint32_t)0x0000001AU)  /*!< MDMA HW request is DMA2D Transfer Watermark Flag          */

+

+#if defined (DSI)

+#define MDMA_REQUEST_DSI_TEARING_EFFECT   ((uint32_t)0x0000001BU)  /*!< MDMA HW request is DSI Tearing Effect Flag                */

+#define MDMA_REQUEST_DSI_END_REFRESH      ((uint32_t)0x0000001CU)  /*!< MDMA HW request is DSI End of refresh  Flag               */

+#endif /* DSI */

+

+#define MDMA_REQUEST_SDMMC1_END_DATA      ((uint32_t)0x0000001DU)  /*!< MDMA HW request is SDMMC1 End of Data Flag                */

+

+#define MDMA_REQUEST_SDMMC1_DMA_ENDBUFFER ((uint32_t)0x0000001EU)  /*!< MDMA HW request is SDMMC1 Internal DMA buffer End Flag    */

+#define MDMA_REQUEST_SDMMC1_COMMAND_END   ((uint32_t)0x0000001FU)  /*!< MDMA HW request is SDMMC1 Command End Flag                */

+

+#if defined (OCTOSPI2)

+#define MDMA_REQUEST_OCTOSPI2_FIFO_TH     ((uint32_t)0x00000020U)  /*!< MDMA HW request is OCTOSPI2 FIFO threshold Flag           */

+#define MDMA_REQUEST_OCTOSPI2_TC          ((uint32_t)0x00000021U)  /*!< MDMA HW request is OCTOSPI2 Transfer complete Flag        */

+#endif /* OCTOSPI2 */

+

+#define MDMA_REQUEST_SW                   ((uint32_t)0x40000000U) /*!< MDMA SW request                                            */

+

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_Transfer_TriggerMode MDMA Transfer Trigger  Mode

+  * @brief    MDMA Transfer Trigger Mode

+  * @{

+  */

+#define MDMA_BUFFER_TRANSFER          ((uint32_t)0x00000000U)        /*!< Each MDMA request (SW or HW) triggers a buffer transfer                                */

+#define MDMA_BLOCK_TRANSFER           ((uint32_t)MDMA_CTCR_TRGM_0)   /*!< Each MDMA request (SW or HW) triggers a block transfer                                 */

+#define MDMA_REPEAT_BLOCK_TRANSFER    ((uint32_t)MDMA_CTCR_TRGM_1)   /*!< Each MDMA request (SW or HW) triggers a repeated block transfer                        */

+#define MDMA_FULL_TRANSFER            ((uint32_t)MDMA_CTCR_TRGM)     /*!< Each MDMA request (SW or HW) triggers a Full transfer or a linked list transfer if any */

+

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_Priority_level MDMA Priority level

+  * @brief    MDMA Priority level

+  * @{

+  */

+#define MDMA_PRIORITY_LOW             ((uint32_t)0x00000000U)     /*!< Priority level: Low      */

+#define MDMA_PRIORITY_MEDIUM          ((uint32_t)MDMA_CCR_PL_0)  /*!< Priority level: Medium    */

+#define MDMA_PRIORITY_HIGH            ((uint32_t)MDMA_CCR_PL_1)  /*!< Priority level: High      */

+#define MDMA_PRIORITY_VERY_HIGH       ((uint32_t)MDMA_CCR_PL)    /*!< Priority level: Very High */

+

+/**

+  * @}

+  */

+

+

+/** @defgroup MDMA_Endianness MDMA Endianness

+  * @brief    MDMA Endianness

+  * @{

+  */

+#define MDMA_LITTLE_ENDIANNESS_PRESERVE          ((uint32_t)0x00000000U)   /*!< little endianness preserve                                               */

+#define MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE     ((uint32_t)MDMA_CCR_BEX)  /*!< BYTEs endianness exchange when destination data size is > Byte           */

+#define MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE ((uint32_t)MDMA_CCR_HEX)  /*!< HALF WORDs endianness exchange when destination data size is > HALF WORD */

+#define MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE     ((uint32_t)MDMA_CCR_WEX)  /*!< WORDs endianness exchange  when destination data size is > DOUBLE WORD   */

+

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_Source_increment_mode MDMA Source increment mode

+  * @brief    MDMA Source increment mode

+  * @{

+  */

+#define MDMA_SRC_INC_DISABLE      ((uint32_t)0x00000000U)                                     /*!< Source address pointer is fixed                                   */

+#define MDMA_SRC_INC_BYTE         ((uint32_t)MDMA_CTCR_SINC_1)                                /*!< Source address pointer is incremented by a BYTE (8 bits)          */

+#define MDMA_SRC_INC_HALFWORD     ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits)    */

+#define MDMA_SRC_INC_WORD         ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)         */

+#define MDMA_SRC_INC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_SINC_1 | (uint32_t)MDMA_CTCR_SINCOS)   /*!< Source address pointer is incremented by a double Word (64 bits)) */

+#define MDMA_SRC_DEC_BYTE         ((uint32_t)MDMA_CTCR_SINC)                                  /*!< Source address pointer is decremented by a BYTE (8 bits)          */

+#define MDMA_SRC_DEC_HALFWORD     ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_0)   /*!< Source address pointer is decremented by a half Word (16 bits)    */

+#define MDMA_SRC_DEC_WORD         ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS_1)   /*!< Source address pointer is decremented by a Word (32 bits)         */

+#define MDMA_SRC_DEC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_SINC | (uint32_t)MDMA_CTCR_SINCOS)     /*!< Source address pointer is decremented by a double Word (64 bits)) */

+

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_Destination_increment_mode MDMA Destination increment mode

+  * @brief    MDMA Destination increment mode

+  * @{

+  */

+#define MDMA_DEST_INC_DISABLE      ((uint32_t)0x00000000U)                                     /*!< Source address pointer is fixed                                   */

+#define MDMA_DEST_INC_BYTE         ((uint32_t)MDMA_CTCR_DINC_1)                                /*!< Source address pointer is incremented by a BYTE (8 bits)          */

+#define MDMA_DEST_INC_HALFWORD     ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_0) /*!< Source address pointer is incremented by a half Word (16 bits)    */

+#define MDMA_DEST_INC_WORD         ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS_1) /*!< Source address pointer is incremented by a Word (32 bits)         */

+#define MDMA_DEST_INC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_DINC_1 | (uint32_t)MDMA_CTCR_DINCOS)   /*!< Source address pointer is incremented by a double Word (64 bits)) */

+#define MDMA_DEST_DEC_BYTE         ((uint32_t)MDMA_CTCR_DINC)                                  /*!< Source address pointer is decremented by a BYTE (8 bits)          */

+#define MDMA_DEST_DEC_HALFWORD     ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_0)   /*!< Source address pointer is decremented by a half Word (16 bits)    */

+#define MDMA_DEST_DEC_WORD         ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS_1)   /*!< Source address pointer is decremented by a Word (32 bits)         */

+#define MDMA_DEST_DEC_DOUBLEWORD   ((uint32_t)MDMA_CTCR_DINC | (uint32_t)MDMA_CTCR_DINCOS)     /*!< Source address pointer is decremented by a double Word (64 bits)) */

+

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_Source_data_size MDMA Source data size

+  * @brief    MDMA Source data size

+  * @{

+  */

+#define MDMA_SRC_DATASIZE_BYTE        ((uint32_t)0x00000000U)         /*!< Source data size is Byte        */

+#define MDMA_SRC_DATASIZE_HALFWORD    ((uint32_t)MDMA_CTCR_SSIZE_0)   /*!< Source data size is half word   */

+#define MDMA_SRC_DATASIZE_WORD        ((uint32_t)MDMA_CTCR_SSIZE_1)   /*!< Source data size is word        */

+#define MDMA_SRC_DATASIZE_DOUBLEWORD  ((uint32_t)MDMA_CTCR_SSIZE)     /*!< Source data size is double word */

+

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_Destination_data_size MDMA Destination data size

+  * @brief    MDMA Destination data size

+  * @{

+  */

+#define MDMA_DEST_DATASIZE_BYTE        ((uint32_t)0x00000000U)         /*!< Destination data size is Byte        */

+#define MDMA_DEST_DATASIZE_HALFWORD    ((uint32_t)MDMA_CTCR_DSIZE_0)   /*!< Destination data size is half word   */

+#define MDMA_DEST_DATASIZE_WORD        ((uint32_t)MDMA_CTCR_DSIZE_1)   /*!< Destination data size is word        */

+#define MDMA_DEST_DATASIZE_DOUBLEWORD  ((uint32_t)MDMA_CTCR_DSIZE)     /*!< Destination data size is double word */

+

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_data_Alignment MDMA data alignment

+  * @brief    MDMA data alignment

+  * @{

+  */

+#define MDMA_DATAALIGN_PACKENABLE        ((uint32_t)MDMA_CTCR_PKE)     /*!< The source data is packed/un-packed into the destination data size

+                                                                            All data are right aligned, in Little Endien mode.                                              */

+#define MDMA_DATAALIGN_RIGHT            ((uint32_t)0x00000000U)        /*!< Right Aligned, padded w/ 0s (default)                                                           */

+#define MDMA_DATAALIGN_RIGHT_SIGNED     ((uint32_t)MDMA_CTCR_PAM_0)    /*!< Right Aligned, Sign extended ,

+                                                                            Note : this mode is allowed only if the Source data size is smaller than Destination data size  */

+#define MDMA_DATAALIGN_LEFT             ((uint32_t)MDMA_CTCR_PAM_1)    /*!< Left Aligned (padded with 0s)                                                                   */

+

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_Source_burst MDMA Source burst

+  * @brief    MDMA Source burst

+  * @{

+  */

+#define MDMA_SOURCE_BURST_SINGLE        ((uint32_t)0x00000000U)                                       /*!< single transfer */

+#define MDMA_SOURCE_BURST_2BEATS        ((uint32_t)MDMA_CTCR_SBURST_0)                                /*!< Burst 2 beats   */

+#define MDMA_SOURCE_BURST_4BEATS        ((uint32_t)MDMA_CTCR_SBURST_1)                                /*!< Burst 4 beats   */

+#define MDMA_SOURCE_BURST_8BEATS        ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_1) /*!< Burst 8 beats   */

+#define MDMA_SOURCE_BURST_16BEATS       ((uint32_t)MDMA_CTCR_SBURST_2)                                /*!< Burst 16 beats  */

+#define MDMA_SOURCE_BURST_32BEATS       ((uint32_t)MDMA_CTCR_SBURST_0 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 32 beats  */

+#define MDMA_SOURCE_BURST_64BEATS       ((uint32_t)MDMA_CTCR_SBURST_1 | (uint32_t)MDMA_CTCR_SBURST_2) /*!< Burst 64 beats  */

+#define MDMA_SOURCE_BURST_128BEATS      ((uint32_t)MDMA_CTCR_SBURST)                                  /*!< Burst 128 beats */

+

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_Destination_burst MDMA Destination burst

+  * @brief    MDMA Destination burst

+  * @{

+  */

+#define MDMA_DEST_BURST_SINGLE        ((uint32_t)0x00000000U)                                        /*!< single transfer */

+#define MDMA_DEST_BURST_2BEATS        ((uint32_t)MDMA_CTCR_DBURST_0)                                 /*!< Burst 2 beats   */

+#define MDMA_DEST_BURST_4BEATS        ((uint32_t)MDMA_CTCR_DBURST_1)                                 /*!< Burst 4 beats   */

+#define MDMA_DEST_BURST_8BEATS        ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_1)  /*!< Burst 8 beats   */

+#define MDMA_DEST_BURST_16BEATS       ((uint32_t)MDMA_CTCR_DBURST_2)                                 /*!< Burst 16 beats  */

+#define MDMA_DEST_BURST_32BEATS       ((uint32_t)MDMA_CTCR_DBURST_0 | (uint32_t)MDMA_CTCR_DBURST_2)  /*!< Burst 32 beats  */

+#define MDMA_DEST_BURST_64BEATS       ((uint32_t)MDMA_CTCR_DBURST_1 | (uint32_t)MDMA_CTCR_DBURST_2)  /*!< Burst 64 beats  */

+#define MDMA_DEST_BURST_128BEATS      ((uint32_t)MDMA_CTCR_DBURST)                                   /*!< Burst 128 beats */

+

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_interrupt_enable_definitions MDMA interrupt enable definitions

+  * @brief    MDMA interrupt enable definitions

+  * @{

+  */

+#define MDMA_IT_TE   ((uint32_t)MDMA_CCR_TEIE)   /*!< Transfer Error interrupt            */

+#define MDMA_IT_CTC  ((uint32_t)MDMA_CCR_CTCIE)  /*!< Channel Transfer Complete interrupt */

+#define MDMA_IT_BRT  ((uint32_t)MDMA_CCR_BRTIE)  /*!< Block Repeat Transfer interrupt     */

+#define MDMA_IT_BT   ((uint32_t)MDMA_CCR_BTIE)   /*!< Block Transfer interrupt            */

+#define MDMA_IT_BFTC ((uint32_t)MDMA_CCR_TCIE)   /*!< Buffer Transfer Complete interrupt  */

+

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_flag_definitions MDMA flag definitions

+  * @brief    MDMA flag definitions

+  * @{

+  */

+#define MDMA_FLAG_TE    ((uint32_t)MDMA_CISR_TEIF)  /*!< Transfer Error flag                 */

+#define MDMA_FLAG_CTC   ((uint32_t)MDMA_CISR_CTCIF) /*!< Channel Transfer Complete flag      */

+#define MDMA_FLAG_BRT   ((uint32_t)MDMA_CISR_BRTIF) /*!< Block Repeat Transfer complete flag */

+#define MDMA_FLAG_BT    ((uint32_t)MDMA_CISR_BTIF)  /*!< Block Transfer complete flag        */

+#define MDMA_FLAG_BFTC  ((uint32_t)MDMA_CISR_TCIF)  /*!< BuFfer Transfer complete flag       */

+#define MDMA_FLAG_CRQA  ((uint32_t)MDMA_CISR_CRQA)  /*!< Channel ReQest Active flag          */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+

+/** @defgroup MDMA_Exported_Macros MDMA Exported Macros

+  * @{

+  */

+

+/**

+  * @brief  Enable the specified MDMA Channel.

+  * @param  __HANDLE__: MDMA handle

+  * @retval None

+  */

+#define __HAL_MDMA_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CCR |=  MDMA_CCR_EN)

+

+/**

+  * @brief  Disable the specified MDMA Channel.

+  * @param  __HANDLE__: MDMA handle

+  * @retval None

+  */

+#define __HAL_MDMA_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CCR &=  ~MDMA_CCR_EN)

+

+/**

+  * @brief  Get the MDMA Channel pending flags.

+  * @param  __HANDLE__: MDMA handle

+  * @param  __FLAG__: Get the specified flag.

+  *          This parameter can be any combination of the following values:

+  *            @arg MDMA_FLAG_TE   : Transfer Error flag.

+  *            @arg MDMA_FLAG_CTC  : Channel Transfer Complete flag.

+  *            @arg MDMA_FLAG_BRT  : Block Repeat Transfer flag.

+  *            @arg MDMA_FLAG_BT   : Block Transfer complete flag.

+  *            @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.

+  *            @arg MDMA_FLAG_CRQA : Channel ReQest Active flag.

+  * @retval The state of FLAG (SET or RESET).

+  */

+#define __HAL_MDMA_GET_FLAG(__HANDLE__, __FLAG__)  ((__HANDLE__)->Instance->CISR & (__FLAG__))

+

+/**

+  * @brief  Clear the MDMA Stream pending flags.

+  * @param  __HANDLE__: MDMA handle

+  * @param  __FLAG__: specifies the flag to clear.

+  *          This parameter can be any combination of the following values:

+  *            @arg MDMA_FLAG_TE   : Transfer Error flag.

+  *            @arg MDMA_FLAG_CTC  : Channel Transfer Complete flag.

+  *            @arg MDMA_FLAG_BRT  : Block Repeat Transfer flag.

+  *            @arg MDMA_FLAG_BT   : Block Transfer complete flag.

+  *            @arg MDMA_FLAG_BFTC : BuFfer Transfer Complete flag.

+  * @retval None

+  */

+#define __HAL_MDMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CIFCR = (__FLAG__))

+

+/**

+  * @brief  Enables the specified MDMA Channel interrupts.

+  * @param  __HANDLE__: MDMA handle

+  * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.

+  *          This parameter can be any combination of the following values:

+  *            @arg MDMA_IT_TE   :  Transfer Error interrupt mask

+  *            @arg MDMA_IT_CTC  :  Channel Transfer Complete interrupt mask

+  *            @arg MDMA_IT_BRT  :  Block Repeat Transfer interrupt mask

+  *            @arg MDMA_IT_BT   :  Block Transfer interrupt mask

+  *            @arg MDMA_IT_BFTC :  BuFfer Transfer Complete interrupt mask

+  * @retval None

+  */

+#define __HAL_MDMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))

+

+/**

+  * @brief  Disables the specified MDMA Channel interrupts.

+  * @param  __HANDLE__: MDMA handle

+  * @param __INTERRUPT__: specifies the MDMA interrupt sources to be enabled or disabled.

+  *          This parameter can be any combination of the following values:

+  *            @arg MDMA_IT_TE   :  Transfer Error interrupt mask

+  *            @arg MDMA_IT_CTC  :  Channel Transfer Complete interrupt mask

+  *            @arg MDMA_IT_BRT  :  Block Repeat Transfer interrupt mask

+  *            @arg MDMA_IT_BT   :  Block Transfer interrupt mask

+  *            @arg MDMA_IT_BFTC :  BuFfer Transfer Complete interrupt mask

+  * @retval None

+  */

+#define __HAL_MDMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))

+

+/**

+  * @brief  Checks whether the specified MDMA Channel interrupt is enabled or not.

+  * @param  __HANDLE__: DMA handle

+  * @param  __INTERRUPT__: specifies the DMA interrupt source to check.

+  *            @arg MDMA_IT_TE   :  Transfer Error interrupt mask

+  *            @arg MDMA_IT_CTC  :  Channel Transfer Complete interrupt mask

+  *            @arg MDMA_IT_BRT  :  Block Repeat Transfer interrupt mask

+  *            @arg MDMA_IT_BT   :  Block Transfer interrupt mask

+  *            @arg MDMA_IT_BFTC :  BuFfer Transfer Complete interrupt mask

+  * @retval The state of MDMA_IT (SET or RESET).

+  */

+#define __HAL_MDMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup MDMA_Exported_Functions  MDMA Exported Functions

+  * @{

+  */

+

+/* Initialization and de-initialization functions *****************************/

+/** @defgroup MDMA_Exported_Functions_Group1 Initialization and de-initialization functions

+  * @brief   Initialization and de-initialization functions

+  * @{

+  */

+HAL_StatusTypeDef HAL_MDMA_Init(MDMA_HandleTypeDef *hmdma);

+HAL_StatusTypeDef HAL_MDMA_DeInit (MDMA_HandleTypeDef *hmdma);

+HAL_StatusTypeDef HAL_MDMA_ConfigPostRequestMask(MDMA_HandleTypeDef *hmdma, uint32_t MaskAddress, uint32_t MaskData);

+

+HAL_StatusTypeDef HAL_MDMA_RegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID, void (* pCallback)(MDMA_HandleTypeDef *_hmdma));

+HAL_StatusTypeDef HAL_MDMA_UnRegisterCallback(MDMA_HandleTypeDef *hmdma, HAL_MDMA_CallbackIDTypeDef CallbackID);

+

+/**

+  * @}

+  */

+

+/* Linked list operation functions ********************************************/

+/** @defgroup MDMA_Exported_Functions_Group2 Linked List operation functions

+  * @brief   Linked list operation functions

+  * @{

+  */

+

+HAL_StatusTypeDef HAL_MDMA_LinkedList_CreateNode(MDMA_LinkNodeTypeDef *pNode, MDMA_LinkNodeConfTypeDef *pNodeConfig);

+HAL_StatusTypeDef HAL_MDMA_LinkedList_AddNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNewNode, MDMA_LinkNodeTypeDef *pPrevNode);

+HAL_StatusTypeDef HAL_MDMA_LinkedList_RemoveNode(MDMA_HandleTypeDef *hmdma, MDMA_LinkNodeTypeDef *pNode);

+HAL_StatusTypeDef HAL_MDMA_LinkedList_EnableCircularMode(MDMA_HandleTypeDef *hmdma);

+HAL_StatusTypeDef HAL_MDMA_LinkedList_DisableCircularMode(MDMA_HandleTypeDef *hmdma);

+

+

+/**

+  * @}

+  */

+

+/* IO operation functions *****************************************************/

+/** @defgroup MDMA_Exported_Functions_Group3 I/O operation functions

+  * @brief   I/O operation functions

+  * @{

+  */

+HAL_StatusTypeDef HAL_MDMA_Start (MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);

+HAL_StatusTypeDef HAL_MDMA_Start_IT(MDMA_HandleTypeDef *hmdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t BlockDataLength, uint32_t BlockCount);

+HAL_StatusTypeDef HAL_MDMA_Abort(MDMA_HandleTypeDef *hmdma);

+HAL_StatusTypeDef HAL_MDMA_Abort_IT(MDMA_HandleTypeDef *hmdma);

+HAL_StatusTypeDef HAL_MDMA_PollForTransfer(MDMA_HandleTypeDef *hmdma, HAL_MDMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);

+HAL_StatusTypeDef HAL_MDMA_GenerateSWRequest(MDMA_HandleTypeDef *hmdma);

+void HAL_MDMA_IRQHandler(MDMA_HandleTypeDef *hmdma);

+

+/**

+  * @}

+  */

+

+/* Peripheral State and Error functions ***************************************/

+/** @defgroup MDMA_Exported_Functions_Group4 Peripheral State functions

+  * @brief    Peripheral State functions

+  * @{

+  */

+HAL_MDMA_StateTypeDef HAL_MDMA_GetState(MDMA_HandleTypeDef *hmdma);

+uint32_t              HAL_MDMA_GetError(MDMA_HandleTypeDef *hmdma);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private types -------------------------------------------------------------*/

+/** @defgroup MDMA_Private_Types MDMA Private Types

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private defines -----------------------------------------------------------*/

+/** @defgroup MDMA_Private_Defines MDMA Private Defines

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private variables ---------------------------------------------------------*/

+/** @defgroup MDMA_Private_Variables MDMA Private Variables

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup MDMA_Private_Constants MDMA Private Constants

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup MDMA_Private_Macros MDMA Private Macros

+  * @{

+  */

+

+#define IS_MDMA_LEVEL_COMPLETE(__LEVEL__) (((__LEVEL__) == HAL_MDMA_FULL_TRANSFER )  || \

+                                           ((__LEVEL__) == HAL_MDMA_BUFFER_TRANSFER )|| \

+                                           ((__LEVEL__) == HAL_MDMA_BLOCK_TRANSFER ) || \

+                                           ((__LEVEL__) == HAL_MDMA_REPEAT_BLOCK_TRANSFER ))

+

+

+#define IS_MDMA_PRIORITY(__PRIORITY__) (((__PRIORITY__) == MDMA_PRIORITY_LOW )   || \

+                                        ((__PRIORITY__) == MDMA_PRIORITY_MEDIUM) || \

+                                        ((__PRIORITY__) == MDMA_PRIORITY_HIGH)   || \

+                                        ((__PRIORITY__) == MDMA_PRIORITY_VERY_HIGH))

+

+#define IS_MDMA_ENDIANNESS_MODE(__ENDIANNESS__) (((__ENDIANNESS__) == MDMA_LITTLE_ENDIANNESS_PRESERVE )         || \

+                                                 ((__ENDIANNESS__) == MDMA_LITTLE_BYTE_ENDIANNESS_EXCHANGE)     || \

+                                                 ((__ENDIANNESS__) == MDMA_LITTLE_HALFWORD_ENDIANNESS_EXCHANGE) || \

+                                                 ((__ENDIANNESS__) == MDMA_LITTLE_WORD_ENDIANNESS_EXCHANGE))

+

+

+#if defined (OCTOSPI2)

+#define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_OCTOSPI2_TC))

+#else

+#define IS_MDMA_REQUEST(__REQUEST__) (((__REQUEST__) == MDMA_REQUEST_SW ) || ((__REQUEST__) <= MDMA_REQUEST_SDMMC1_COMMAND_END))

+#endif /* OCTOSPI2 */

+

+#define IS_MDMA_SOURCE_INC(__INC__) (((__INC__) == MDMA_SRC_INC_DISABLE )   || \

+                                     ((__INC__) == MDMA_SRC_INC_BYTE )      || \

+                                     ((__INC__) == MDMA_SRC_INC_HALFWORD )  || \

+                                     ((__INC__) == MDMA_SRC_INC_WORD )      || \

+                                     ((__INC__) == MDMA_SRC_INC_DOUBLEWORD) || \

+                                     ((__INC__) == MDMA_SRC_DEC_BYTE)       || \

+                                     ((__INC__) == MDMA_SRC_DEC_HALFWORD)   || \

+                                     ((__INC__) == MDMA_SRC_DEC_WORD)       || \

+                                     ((__INC__) == MDMA_SRC_DEC_DOUBLEWORD))

+

+#define IS_MDMA_DESTINATION_INC(__INC__) (((__INC__) == MDMA_DEST_INC_DISABLE )   || \

+                                          ((__INC__) == MDMA_DEST_INC_BYTE )      || \

+                                          ((__INC__) == MDMA_DEST_INC_HALFWORD )  || \

+                                          ((__INC__) == MDMA_DEST_INC_WORD )      || \

+                                          ((__INC__) == MDMA_DEST_INC_DOUBLEWORD) || \

+                                          ((__INC__) == MDMA_DEST_DEC_BYTE)       || \

+                                          ((__INC__) == MDMA_DEST_DEC_HALFWORD)   || \

+                                          ((__INC__) == MDMA_DEST_DEC_WORD)       || \

+                                          ((__INC__) == MDMA_DEST_DEC_DOUBLEWORD))

+

+#define IS_MDMA_SOURCE_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_SRC_DATASIZE_BYTE )     || \

+                                           ((__SIZE__) == MDMA_SRC_DATASIZE_HALFWORD ) || \

+                                           ((__SIZE__) == MDMA_SRC_DATASIZE_WORD )     || \

+                                           ((__SIZE__) == MDMA_SRC_DATASIZE_DOUBLEWORD))

+

+#define IS_MDMA_DESTINATION_DATASIZE(__SIZE__) (((__SIZE__) == MDMA_DEST_DATASIZE_BYTE )     || \

+                                                ((__SIZE__) == MDMA_DEST_DATASIZE_HALFWORD ) || \

+                                                ((__SIZE__) == MDMA_DEST_DATASIZE_WORD )     || \

+                                                ((__SIZE__) == MDMA_DEST_DATASIZE_DOUBLEWORD))

+

+#define IS_MDMA_DATA_ALIGNMENT(__ALIGNMENT__) (((__ALIGNMENT__) == MDMA_DATAALIGN_PACKENABLE )    || \

+                                               ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT )         || \

+                                               ((__ALIGNMENT__) == MDMA_DATAALIGN_RIGHT_SIGNED )  || \

+                                               ((__ALIGNMENT__) == MDMA_DATAALIGN_LEFT))

+

+

+#define IS_MDMA_SOURCE_BURST(__BURST__) (((__BURST__) == MDMA_SOURCE_BURST_SINGLE ) || \

+                                         ((__BURST__) == MDMA_SOURCE_BURST_2BEATS ) || \

+                                         ((__BURST__) == MDMA_SOURCE_BURST_4BEATS ) || \

+                                         ((__BURST__) == MDMA_SOURCE_BURST_8BEATS)  || \

+                                         ((__BURST__) == MDMA_SOURCE_BURST_16BEATS) || \

+                                         ((__BURST__) == MDMA_SOURCE_BURST_32BEATS) || \

+                                         ((__BURST__) == MDMA_SOURCE_BURST_64BEATS) || \

+                                         ((__BURST__) == MDMA_SOURCE_BURST_128BEATS))

+

+

+#define IS_MDMA_DESTINATION_BURST(__BURST__) (((__BURST__) == MDMA_DEST_BURST_SINGLE ) || \

+                                              ((__BURST__) == MDMA_DEST_BURST_2BEATS ) || \

+                                              ((__BURST__) == MDMA_DEST_BURST_4BEATS ) || \

+                                              ((__BURST__) == MDMA_DEST_BURST_8BEATS)  || \

+                                              ((__BURST__) == MDMA_DEST_BURST_16BEATS) || \

+                                              ((__BURST__) == MDMA_DEST_BURST_32BEATS) || \

+                                              ((__BURST__) == MDMA_DEST_BURST_64BEATS) || \

+                                              ((__BURST__) == MDMA_DEST_BURST_128BEATS))

+

+ #define IS_MDMA_TRANSFER_TRIGGER_MODE(__MODE__) (((__MODE__) == MDMA_BUFFER_TRANSFER )      || \

+                                                  ((__MODE__) == MDMA_BLOCK_TRANSFER )        || \

+                                                  ((__MODE__) == MDMA_REPEAT_BLOCK_TRANSFER ) || \

+                                                  ((__MODE__) == MDMA_FULL_TRANSFER))

+

+#define IS_MDMA_BUFFER_TRANSFER_LENGTH(__LENGTH__) (((__LENGTH__) >= 0x00000001U) && ((__LENGTH__) < 0x000000FFU))

+

+#define IS_MDMA_BLOCK_COUNT(__COUNT__) (((__COUNT__) > 0U ) && ((__COUNT__) <= 4096U))

+

+#define IS_MDMA_TRANSFER_LENGTH(SIZE) (((SIZE) > 0U) && ((SIZE) <= 65536U))

+

+#define IS_MDMA_BLOCK_ADDR_OFFSET(__BLOCK_ADD_OFFSET__) (((__BLOCK_ADD_OFFSET__) > (-65536)) && ((__BLOCK_ADD_OFFSET__) < 65536))

+

+/**

+  * @}

+  */

+

+/* Private functions prototypes ----------------------------------------------*/

+/** @defgroup MDMA_Private_Functions_Prototypes MDMA Private Functions Prototypes

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private functions ---------------------------------------------------------*/

+/** @defgroup MDMA_Private_Functions MDMA Private Functions

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_MDMA_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_mmc.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_mmc.h
new file mode 100644
index 0000000000..c8679bba32
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_mmc.h
@@ -0,0 +1,756 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_mmc.h

+  * @author  MCD Application Team

+  * @brief   Header file of MMC HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                       opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */ 

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_MMC_H

+#define STM32H7xx_HAL_MMC_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_ll_sdmmc.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup MMC

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup MMC_Exported_Types MMC Exported Types

+  * @{

+  */

+

+/** @defgroup MMC_Exported_Types_Group1 MMC State enumeration structure

+  * @{

+  */

+typedef enum

+{

+  HAL_MMC_STATE_RESET                  = ((uint32_t)0x00000000U),  /*!< MMC not yet initialized or disabled  */

+  HAL_MMC_STATE_READY                  = ((uint32_t)0x00000001U),  /*!< MMC initialized and ready for use    */

+  HAL_MMC_STATE_TIMEOUT                = ((uint32_t)0x00000002U),  /*!< MMC Timeout state                    */

+  HAL_MMC_STATE_BUSY                   = ((uint32_t)0x00000003U),  /*!< MMC process ongoing                  */

+  HAL_MMC_STATE_PROGRAMMING            = ((uint32_t)0x00000004U),  /*!< MMC Programming State                */

+  HAL_MMC_STATE_RECEIVING              = ((uint32_t)0x00000005U),  /*!< MMC Receinving State                 */

+  HAL_MMC_STATE_TRANSFER               = ((uint32_t)0x00000006U),  /*!< MMC Transfert State                  */

+  HAL_MMC_STATE_ERROR                  = ((uint32_t)0x0000000FU)   /*!< MMC is in error state                */

+}HAL_MMC_StateTypeDef;

+/**

+  * @}

+  */

+

+/** @defgroup MMC_Exported_Types_Group2 MMC Card State enumeration structure

+  * @{

+  */

+typedef uint32_t HAL_MMC_CardStateTypeDef;

+

+#define HAL_MMC_CARD_READY          0x00000001U  /*!< Card state is ready                     */

+#define HAL_MMC_CARD_IDENTIFICATION 0x00000002U  /*!< Card is in identification state         */

+#define HAL_MMC_CARD_STANDBY        0x00000003U  /*!< Card is in standby state                */

+#define HAL_MMC_CARD_TRANSFER       0x00000004U  /*!< Card is in transfer state               */

+#define HAL_MMC_CARD_SENDING        0x00000005U  /*!< Card is sending an operation            */

+#define HAL_MMC_CARD_RECEIVING      0x00000006U  /*!< Card is receiving operation information */

+#define HAL_MMC_CARD_PROGRAMMING    0x00000007U  /*!< Card is in programming state            */

+#define HAL_MMC_CARD_DISCONNECTED   0x00000008U  /*!< Card is disconnected                    */

+#define HAL_MMC_CARD_ERROR          0x000000FFU  /*!< Card response Error                     */

+/**

+  * @}

+  */

+

+/** @defgroup MMC_Exported_Types_Group3 MMC Handle Structure definition

+  * @{

+  */

+#define MMC_InitTypeDef      SDMMC_InitTypeDef

+#define MMC_TypeDef          SDMMC_TypeDef

+

+/**

+  * @brief  MMC Card Information Structure definition

+  */

+typedef struct

+{

+  uint32_t CardType;                     /*!< Specifies the card Type                         */

+

+  uint32_t Class;                        /*!< Specifies the class of the card class           */

+

+  uint32_t RelCardAdd;                   /*!< Specifies the Relative Card Address             */

+

+  uint32_t BlockNbr;                     /*!< Specifies the Card Capacity in blocks           */

+

+  uint32_t BlockSize;                    /*!< Specifies one block size in bytes               */

+

+  uint32_t LogBlockNbr;                  /*!< Specifies the Card logical Capacity in blocks   */

+

+  uint32_t LogBlockSize;                 /*!< Specifies logical block size in bytes           */

+

+}HAL_MMC_CardInfoTypeDef;

+

+/**

+  * @brief  MMC handle Structure definition

+  */

+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)

+typedef struct __MMC_HandleTypeDef

+#else

+typedef struct

+#endif /* USE_HAL_MMC_REGISTER_CALLBACKS */

+{

+  MMC_TypeDef                  *Instance;        /*!< MMC registers base address           */

+

+  MMC_InitTypeDef              Init;             /*!< MMC required parameters              */

+

+  HAL_LockTypeDef              Lock;             /*!< MMC locking object                   */

+

+  uint8_t                      *pTxBuffPtr;      /*!< Pointer to MMC Tx transfer Buffer    */

+

+  uint32_t                     TxXferSize;       /*!< MMC Tx Transfer size                 */

+

+  uint8_t                      *pRxBuffPtr;      /*!< Pointer to MMC Rx transfer Buffer    */

+

+  uint32_t                     RxXferSize;       /*!< MMC Rx Transfer size                 */

+

+  __IO uint32_t                Context;          /*!< MMC transfer context                 */

+

+  __IO HAL_MMC_StateTypeDef    State;            /*!< MMC card State                       */

+

+  __IO uint32_t                ErrorCode;        /*!< MMC Card Error codes                 */

+

+  HAL_MMC_CardInfoTypeDef      MmcCard;          /*!< MMC Card information                 */

+

+  uint32_t                     CSD[4U];          /*!< MMC card specific data table         */

+

+  uint32_t                     CID[4U];          /*!< MMC card identification number table */

+

+  uint32_t                     Ext_CSD[128];

+

+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)

+  void (* TxCpltCallback)                 (struct __MMC_HandleTypeDef *hmmc);

+  void (* RxCpltCallback)                 (struct __MMC_HandleTypeDef *hmmc);

+  void (* ErrorCallback)                  (struct __MMC_HandleTypeDef *hmmc);

+  void (* AbortCpltCallback)              (struct __MMC_HandleTypeDef *hmmc);

+  void (* Read_DMADblBuf0CpltCallback)    (struct __MMC_HandleTypeDef *hmmc);

+  void (* Read_DMADblBuf1CpltCallback)    (struct __MMC_HandleTypeDef *hmmc);

+  void (* Write_DMADblBuf0CpltCallback)   (struct __MMC_HandleTypeDef *hmmc);

+  void (* Write_DMADblBuf1CpltCallback)   (struct __MMC_HandleTypeDef *hmmc);

+

+  void (* MspInitCallback)                (struct __MMC_HandleTypeDef *hmmc);

+  void (* MspDeInitCallback)              (struct __MMC_HandleTypeDef *hmmc);

+#endif

+}MMC_HandleTypeDef;

+

+

+/**

+  * @}

+  */

+

+/** @defgroup MMC_Exported_Types_Group4 Card Specific Data: CSD Register

+  * @{

+  */

+typedef struct

+{

+  __IO uint8_t  CSDStruct;            /*!< CSD structure                         */

+  __IO uint8_t  SysSpecVersion;       /*!< System specification version          */

+  __IO uint8_t  Reserved1;            /*!< Reserved                              */

+  __IO uint8_t  TAAC;                 /*!< Data read access time 1               */

+  __IO uint8_t  NSAC;                 /*!< Data read access time 2 in CLK cycles */

+  __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency              */

+  __IO uint16_t CardComdClasses;      /*!< Card command classes                  */

+  __IO uint8_t  RdBlockLen;           /*!< Max. read data block length           */

+  __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed       */

+  __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment              */

+  __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment               */

+  __IO uint8_t  DSRImpl;              /*!< DSR implemented                       */

+  __IO uint8_t  Reserved2;            /*!< Reserved                              */

+  __IO uint32_t DeviceSize;           /*!< Device Size                           */

+  __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min           */

+  __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max           */

+  __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min          */

+  __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max          */

+  __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier                */

+  __IO uint8_t  EraseGrSize;          /*!< Erase group size                      */

+  __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier           */

+  __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size              */

+  __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable            */

+  __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC              */

+  __IO uint8_t  WrSpeedFact;          /*!< Write speed factor                    */

+  __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length          */

+  __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed      */

+  __IO uint8_t  Reserved3;            /*!< Reserved                              */

+  __IO uint8_t  ContentProtectAppli;  /*!< Content protection application        */

+  __IO uint8_t  FileFormatGroup;      /*!< File format group                     */

+  __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP)                       */

+  __IO uint8_t  PermWrProtect;        /*!< Permanent write protection            */

+  __IO uint8_t  TempWrProtect;        /*!< Temporary write protection            */

+  __IO uint8_t  FileFormat;           /*!< File format                           */

+  __IO uint8_t  ECC;                  /*!< ECC code                              */

+  __IO uint8_t  CSD_CRC;              /*!< CSD CRC                               */

+  __IO uint8_t  Reserved4;            /*!< Always 1                              */

+

+}HAL_MMC_CardCSDTypeDef;

+/**

+  * @}

+  */

+

+/** @defgroup MMC_Exported_Types_Group5 Card Identification Data: CID Register

+  * @{

+  */

+typedef struct

+{

+  __IO uint8_t  ManufacturerID;  /*!< Manufacturer ID       */

+  __IO uint16_t OEM_AppliID;     /*!< OEM/Application ID    */

+  __IO uint32_t ProdName1;       /*!< Product Name part1    */

+  __IO uint8_t  ProdName2;       /*!< Product Name part2    */

+  __IO uint8_t  ProdRev;         /*!< Product Revision      */

+  __IO uint32_t ProdSN;          /*!< Product Serial Number */

+  __IO uint8_t  Reserved1;       /*!< Reserved1             */

+  __IO uint16_t ManufactDate;    /*!< Manufacturing Date    */

+  __IO uint8_t  CID_CRC;         /*!< CID CRC               */

+  __IO uint8_t  Reserved2;       /*!< Always 1              */

+

+}HAL_MMC_CardCIDTypeDef;

+/**

+  * @}

+  */

+

+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)

+/** @defgroup MMC_Exported_Types_Group6 MMC Callback ID enumeration definition

+  * @{

+  */

+typedef enum

+{

+  HAL_MMC_TX_CPLT_CB_ID                 = 0x00U,  /*!< MMC Tx Complete Callback ID                     */

+  HAL_MMC_RX_CPLT_CB_ID                 = 0x01U,  /*!< MMC Rx Complete Callback ID                     */

+  HAL_MMC_ERROR_CB_ID                   = 0x02U,  /*!< MMC Error Callback ID                           */

+  HAL_MMC_ABORT_CB_ID                   = 0x03U,  /*!< MMC Abort Callback ID                           */

+  HAL_MMC_READ_DMA_DBL_BUF0_CPLT_CB_ID  = 0x04U,  /*!< MMC Rx DMA Double Buffer 0 Complete Callback ID */

+  HAL_MMC_READ_DMA_DBL_BUF1_CPLT_CB_ID  = 0x05U,  /*!< MMC Rx DMA Double Buffer 1 Complete Callback ID */

+  HAL_MMC_WRITE_DMA_DBL_BUF0_CPLT_CB_ID = 0x06U,  /*!< MMC Tx DMA Double Buffer 0 Complete Callback ID */

+  HAL_MMC_WRITE_DMA_DBL_BUF1_CPLT_CB_ID = 0x07U,  /*!< MMC Tx DMA Double Buffer 1 Complete Callback ID */

+

+  HAL_MMC_MSP_INIT_CB_ID                = 0x10U,  /*!< MMC MspInit Callback ID                         */

+  HAL_MMC_MSP_DEINIT_CB_ID              = 0x11U   /*!< MMC MspDeInit Callback ID                       */

+}HAL_MMC_CallbackIDTypeDef;

+/**

+  * @}

+  */

+

+/** @defgroup MMC_Exported_Types_Group7 MMC Callback pointer definition

+  * @{

+  */

+typedef void (*pMMC_CallbackTypeDef)           (MMC_HandleTypeDef *hmmc);

+/**

+  * @}

+  */

+#endif

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup MMC_Exported_Constants Exported Constants

+  * @{

+  */

+

+#define MMC_BLOCKSIZE   ((uint32_t)512U) /*!< Block size is 512 bytes */

+

+/** @defgroup MMC_Exported_Constansts_Group1 MMC Error status enumeration Structure definition

+  * @{

+  */

+#define HAL_MMC_ERROR_NONE                     SDMMC_ERROR_NONE                    /*!< No error                                                      */

+#define HAL_MMC_ERROR_CMD_CRC_FAIL             SDMMC_ERROR_CMD_CRC_FAIL            /*!< Command response received (but CRC check failed)              */

+#define HAL_MMC_ERROR_DATA_CRC_FAIL            SDMMC_ERROR_DATA_CRC_FAIL           /*!< Data block sent/received (CRC check failed)                   */

+#define HAL_MMC_ERROR_CMD_RSP_TIMEOUT          SDMMC_ERROR_CMD_RSP_TIMEOUT         /*!< Command response timeout                                      */

+#define HAL_MMC_ERROR_DATA_TIMEOUT             SDMMC_ERROR_DATA_TIMEOUT            /*!< Data timeout                                                  */

+#define HAL_MMC_ERROR_TX_UNDERRUN              SDMMC_ERROR_TX_UNDERRUN             /*!< Transmit FIFO underrun                                        */

+#define HAL_MMC_ERROR_RX_OVERRUN               SDMMC_ERROR_RX_OVERRUN              /*!< Receive FIFO overrun                                          */

+#define HAL_MMC_ERROR_ADDR_MISALIGNED          SDMMC_ERROR_ADDR_MISALIGNED         /*!< Misaligned address                                            */

+#define HAL_MMC_ERROR_BLOCK_LEN_ERR            SDMMC_ERROR_BLOCK_LEN_ERR           /*!< Transferred block length is not allowed for the card or the

+                                                                                        number of transferred bytes does not match the block length   */

+#define HAL_MMC_ERROR_ERASE_SEQ_ERR            SDMMC_ERROR_ERASE_SEQ_ERR           /*!< An error in the sequence of erase command occurs              */

+#define HAL_MMC_ERROR_BAD_ERASE_PARAM          SDMMC_ERROR_BAD_ERASE_PARAM         /*!< An invalid selection for erase groups                         */

+#define HAL_MMC_ERROR_WRITE_PROT_VIOLATION     SDMMC_ERROR_WRITE_PROT_VIOLATION    /*!< Attempt to program a write protect block                      */

+#define HAL_MMC_ERROR_LOCK_UNLOCK_FAILED       SDMMC_ERROR_LOCK_UNLOCK_FAILED      /*!< Sequence or password error has been detected in unlock

+                                                                                        command or if there was an attempt to access a locked card    */

+#define HAL_MMC_ERROR_COM_CRC_FAILED           SDMMC_ERROR_COM_CRC_FAILED          /*!< CRC check of the previous command failed                      */

+#define HAL_MMC_ERROR_ILLEGAL_CMD              SDMMC_ERROR_ILLEGAL_CMD             /*!< Command is not legal for the card state                       */

+#define HAL_MMC_ERROR_CARD_ECC_FAILED          SDMMC_ERROR_CARD_ECC_FAILED         /*!< Card internal ECC was applied but failed to correct the data  */

+#define HAL_MMC_ERROR_CC_ERR                   SDMMC_ERROR_CC_ERR                  /*!< Internal card controller error                                */

+#define HAL_MMC_ERROR_GENERAL_UNKNOWN_ERR      SDMMC_ERROR_GENERAL_UNKNOWN_ERR     /*!< General or unknown error                                      */

+#define HAL_MMC_ERROR_STREAM_READ_UNDERRUN     SDMMC_ERROR_STREAM_READ_UNDERRUN    /*!< The card could not sustain data reading in stream rmode       */

+#define HAL_MMC_ERROR_STREAM_WRITE_OVERRUN     SDMMC_ERROR_STREAM_WRITE_OVERRUN    /*!< The card could not sustain data programming in stream mode    */

+#define HAL_MMC_ERROR_CID_CSD_OVERWRITE        SDMMC_ERROR_CID_CSD_OVERWRITE       /*!< CID/CSD overwrite error                                       */

+#define HAL_MMC_ERROR_WP_ERASE_SKIP            SDMMC_ERROR_WP_ERASE_SKIP           /*!< Only partial address space was erased                         */

+#define HAL_MMC_ERROR_CARD_ECC_DISABLED        SDMMC_ERROR_CARD_ECC_DISABLED       /*!< Command has been executed without using internal ECC          */

+#define HAL_MMC_ERROR_ERASE_RESET              SDMMC_ERROR_ERASE_RESET             /*!< Erase sequence was cleared before executing because an out

+                                                                                        of erase sequence command was received                        */

+#define HAL_MMC_ERROR_AKE_SEQ_ERR              SDMMC_ERROR_AKE_SEQ_ERR             /*!< Error in sequence of authentication                           */

+#define HAL_MMC_ERROR_INVALID_VOLTRANGE        SDMMC_ERROR_INVALID_VOLTRANGE       /*!< Error in case of invalid voltage range                        */

+#define HAL_MMC_ERROR_ADDR_OUT_OF_RANGE        SDMMC_ERROR_ADDR_OUT_OF_RANGE       /*!< Error when addressed block is out of range                    */

+#define HAL_MMC_ERROR_REQUEST_NOT_APPLICABLE   SDMMC_ERROR_REQUEST_NOT_APPLICABLE  /*!< Error when command request is not applicable                  */

+#define HAL_MMC_ERROR_PARAM                    SDMMC_ERROR_INVALID_PARAMETER       /*!< the used parameter is not valid                               */

+#define HAL_MMC_ERROR_UNSUPPORTED_FEATURE      SDMMC_ERROR_UNSUPPORTED_FEATURE     /*!< Error when feature is not insupported                         */

+#define HAL_MMC_ERROR_BUSY                     SDMMC_ERROR_BUSY                    /*!< Error when transfer process is busy                           */

+#define HAL_MMC_ERROR_DMA                      SDMMC_ERROR_DMA                     /*!< Error while DMA transfer                                      */

+#define HAL_MMC_ERROR_TIMEOUT                  SDMMC_ERROR_TIMEOUT                 /*!< Timeout error                                                 */

+

+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)

+#define HAL_MMC_ERROR_INVALID_CALLBACK         SDMMC_ERROR_INVALID_PARAMETER       /*!< Invalid callback error                                        */

+#endif

+/**

+  * @}

+  */

+

+/** @defgroup MMC_Exported_Constansts_Group2 MMC context enumeration

+  * @{

+  */

+#define   MMC_CONTEXT_NONE                 ((uint32_t)0x00000000U)  /*!< None                             */

+#define   MMC_CONTEXT_READ_SINGLE_BLOCK    ((uint32_t)0x00000001U)  /*!< Read single block operation      */

+#define   MMC_CONTEXT_READ_MULTIPLE_BLOCK  ((uint32_t)0x00000002U)  /*!< Read multiple blocks operation   */

+#define   MMC_CONTEXT_WRITE_SINGLE_BLOCK   ((uint32_t)0x00000010U)  /*!< Write single block operation     */

+#define   MMC_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U)  /*!< Write multiple blocks operation  */

+#define   MMC_CONTEXT_IT                   ((uint32_t)0x00000008U)  /*!< Process in Interrupt mode        */

+#define   MMC_CONTEXT_DMA                  ((uint32_t)0x00000080U)  /*!< Process in DMA mode              */

+

+/**

+  * @}

+  */

+

+/** @defgroup MMC_Exported_Constansts_Group3 MMC Voltage mode

+  * @{

+  */

+/**

+  * @brief

+  */

+#define MMC_HIGH_VOLTAGE_RANGE         0x80FF8000U  /*!< VALUE OF ARGUMENT            */

+#define MMC_DUAL_VOLTAGE_RANGE         0x80FF8080U  /*!< VALUE OF ARGUMENT            */

+#define eMMC_HIGH_VOLTAGE_RANGE        0xC0FF8000U  /*!< for eMMC > 2Gb sector mode   */

+#define eMMC_DUAL_VOLTAGE_RANGE        0xC0FF8080U  /*!< for eMMC > 2Gb sector mode   */

+#define MMC_INVALID_VOLTAGE_RANGE      0x0001FF01U

+/**

+  * @}

+  */

+

+/** @defgroup MMC_Exported_Constansts_Group4 MMC Memory Cards

+  * @{

+  */

+#define  MMC_LOW_CAPACITY_CARD     ((uint32_t)0x00000000U)   /*!< MMC Card Capacity <=2Gbytes   */

+#define  MMC_HIGH_CAPACITY_CARD    ((uint32_t)0x00000001U)   /*!< MMC Card Capacity >2Gbytes and <2Tbytes   */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup MMC_Exported_macros MMC Exported Macros

+ *  @brief macros to handle interrupts and specific clock configurations

+ * @{

+ */

+/** @brief Reset MMC handle state.

+  * @param  __HANDLE__ MMC Handle.

+  * @retval None

+  */

+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)

+#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__)           do {                                              \

+                                                               (__HANDLE__)->State = HAL_MMC_STATE_RESET; \

+                                                               (__HANDLE__)->MspInitCallback = NULL;       \

+                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \

+                                                             } while(0)

+#else

+#define __HAL_MMC_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_MMC_STATE_RESET)

+#endif

+

+/**

+  * @brief  Enable the MMC device interrupt.

+  * @param  __HANDLE__ MMC Handle.

+  * @param  __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.

+  *         This parameter can be one or a combination of the following values:

+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt

+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt

+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt

+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt

+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt

+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt

+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt

+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt

+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt

+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt

+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt

+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt

+  *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt

+  *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt

+  *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt

+  *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt

+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt

+  *            @arg SDMMC_IT_SDIOIT:     SD I/O interrupt received interrupt

+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt

+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt

+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt

+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt

+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt

+  * @retval None

+  */

+#define __HAL_MMC_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))

+

+/**

+  * @brief  Disable the MMC device interrupt.

+  * @param  __HANDLE__ MMC Handle.

+  * @param  __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.

+  *          This parameter can be one or a combination of the following values:

+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt

+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt

+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt

+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt

+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt

+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt

+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt

+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt

+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt

+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt

+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt

+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt

+  *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt

+  *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt

+  *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt

+  *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt

+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt

+  *            @arg SDMMC_IT_SDIOIT:     SD I/O interrupt received interrupt

+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt

+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt

+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt

+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt

+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt

+  * @retval None

+  */

+#define __HAL_MMC_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))

+

+/**

+  * @brief  Check whether the specified MMC flag is set or not.

+  * @param  __HANDLE__ MMC Handle.

+  * @param  __FLAG__ specifies the flag to check.

+  *          This parameter can be one of the following values:

+  *            @arg SDMMC_FLAG_CCRCFAIL:   Command response received (CRC check failed)

+  *            @arg SDMMC_FLAG_DCRCFAIL:   Data block sent/received (CRC check failed)

+  *            @arg SDMMC_FLAG_CTIMEOUT:   Command response timeout

+  *            @arg SDMMC_FLAG_DTIMEOUT:   Data timeout

+  *            @arg SDMMC_FLAG_TXUNDERR:   Transmit FIFO underrun error

+  *            @arg SDMMC_FLAG_RXOVERR:    Received FIFO overrun error

+  *            @arg SDMMC_FLAG_CMDREND:    Command response received (CRC check passed)

+  *            @arg SDMMC_FLAG_CMDSENT:    Command sent (no response required)

+  *            @arg SDMMC_FLAG_DATAEND:    Data end (data counter, DATACOUNT, is zero)

+  *            @arg SDMMC_FLAG_DHOLD:      Data transfer Hold

+  *            @arg SDMMC_FLAG_DBCKEND:    Data block sent/received (CRC check passed)

+  *            @arg SDMMC_FLAG_DABORT:     Data transfer aborted by CMD12

+  *            @arg SDMMC_FLAG_DPSMACT:    Data path state machine active

+  *            @arg SDMMC_FLAG_CPSMACT:    Command path state machine active

+  *            @arg SDMMC_FLAG_TXFIFOHE:   Transmit FIFO Half Empty

+  *            @arg SDMMC_FLAG_RXFIFOHF:   Receive FIFO Half Full

+  *            @arg SDMMC_FLAG_TXFIFOF:    Transmit FIFO full

+  *            @arg SDMMC_FLAG_RXFIFOF:    Receive FIFO full

+  *            @arg SDMMC_FLAG_TXFIFOE:    Transmit FIFO empty

+  *            @arg SDMMC_FLAG_RXFIFOE:    Receive FIFO empty

+  *            @arg SDMMC_FLAG_BUSYD0:     Inverted value of SDMMC_D0 line (Busy)

+  *            @arg SDMMC_FLAG_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected

+  *            @arg SDMMC_FLAG_SDIOIT:     SD I/O interrupt received

+  *            @arg SDMMC_FLAG_ACKFAIL:    Boot Acknowledgment received

+  *            @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout

+  *            @arg SDMMC_FLAG_VSWEND:     Voltage switch critical timing section completion

+  *            @arg SDMMC_FLAG_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure

+  *            @arg SDMMC_FLAG_IDMATE:     IDMA transfer error

+  *            @arg SDMMC_FLAG_IDMABTC:    IDMA buffer transfer complete

+  * @retval The new state of MMC FLAG (SET or RESET).

+  */

+#define __HAL_MMC_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))

+

+/**

+  * @brief  Clear the MMC's pending flags.

+  * @param  __HANDLE__ MMC Handle.

+  * @param  __FLAG__ specifies the flag to clear.

+  *          This parameter can be one or a combination of the following values:

+  *            @arg SDMMC_FLAG_CCRCFAIL:   Command response received (CRC check failed)

+  *            @arg SDMMC_FLAG_DCRCFAIL:   Data block sent/received (CRC check failed)

+  *            @arg SDMMC_FLAG_CTIMEOUT:   Command response timeout

+  *            @arg SDMMC_FLAG_DTIMEOUT:   Data timeout

+  *            @arg SDMMC_FLAG_TXUNDERR:   Transmit FIFO underrun error

+  *            @arg SDMMC_FLAG_RXOVERR:    Received FIFO overrun error

+  *            @arg SDMMC_FLAG_CMDREND:    Command response received (CRC check passed)

+  *            @arg SDMMC_FLAG_CMDSENT:    Command sent (no response required)

+  *            @arg SDMMC_FLAG_DATAEND:    Data end (data counter, DATACOUNT, is zero)

+  *            @arg SDMMC_FLAG_DHOLD:      Data transfer Hold

+  *            @arg SDMMC_FLAG_DBCKEND:    Data block sent/received (CRC check passed)

+  *            @arg SDMMC_FLAG_DABORT:     Data transfer aborted by CMD12

+  *            @arg SDMMC_FLAG_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected

+  *            @arg SDMMC_FLAG_SDIOIT:     SD I/O interrupt received

+  *            @arg SDMMC_FLAG_ACKFAIL:    Boot Acknowledgment received

+  *            @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout

+  *            @arg SDMMC_FLAG_VSWEND:     Voltage switch critical timing section completion

+  *            @arg SDMMC_FLAG_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure

+  *            @arg SDMMC_FLAG_IDMATE:     IDMA transfer error

+  *            @arg SDMMC_FLAG_IDMABTC:    IDMA buffer transfer complete

+  * @retval None

+  */

+#define __HAL_MMC_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))

+

+/**

+  * @brief  Check whether the specified MMC interrupt has occurred or not.

+  * @param  __HANDLE__ MMC Handle.

+  * @param  __INTERRUPT__ specifies the SDMMC interrupt source to check.

+  *          This parameter can be one of the following values:

+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt

+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt

+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt

+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt

+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt

+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt

+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt

+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt

+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt

+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt

+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt

+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt

+  *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt

+  *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt

+  *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt

+  *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt

+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt

+  *            @arg SDMMC_IT_SDIOIT:     SD I/O interrupt received interrupt

+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt

+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt

+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt

+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt

+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt

+  * @retval The new state of MMC IT (SET or RESET).

+  */

+#define __HAL_MMC_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))

+

+/**

+  * @brief  Clear the MMC's interrupt pending bits.

+  * @param  __HANDLE__ MMC Handle.

+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.

+  *          This parameter can be one or a combination of the following values:

+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt

+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt

+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt

+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt

+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt

+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt

+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt

+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt

+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt

+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt

+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt

+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt

+  *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt

+  *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt

+  *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt

+  *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt

+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt

+  *            @arg SDMMC_IT_SDIOIT:     SD I/O interrupt received interrupt

+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt

+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt

+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt

+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt

+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt

+  * @retval None

+  */

+#define __HAL_MMC_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))

+

+/**

+  * @}

+  */

+

+/* Include MMC HAL Extension module */

+#include "stm32h7xx_hal_mmc_ex.h"

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup MMC_Exported_Functions MMC Exported Functions

+  * @{

+  */

+

+/** @defgroup MMC_Exported_Functions_Group1 Initialization and de-initialization functions

+  * @{

+  */

+HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc);

+HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc);

+HAL_StatusTypeDef HAL_MMC_DeInit (MMC_HandleTypeDef *hmmc);

+void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc);

+void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc);

+

+/**

+  * @}

+  */

+

+/** @defgroup MMC_Exported_Functions_Group2 Input and Output operation functions

+  * @{

+  */

+/* Blocking mode: Polling */

+HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);

+HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);

+HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd);

+/* Non-Blocking mode: IT */

+HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);

+HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);

+/* Non-Blocking mode: DMA */

+HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);

+HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);

+

+void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc);

+

+/* Callback in non blocking modes (DMA) */

+void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc);

+void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc);

+void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc);

+void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc);

+

+#if defined (USE_HAL_MMC_REGISTER_CALLBACKS) && (USE_HAL_MMC_REGISTER_CALLBACKS == 1U)

+/* MMC callback registering/unregistering */

+HAL_StatusTypeDef HAL_MMC_RegisterCallback  (MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId, pMMC_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_CallbackIDTypeDef CallbackId);

+#endif

+/**

+  * @}

+  */

+

+/** @defgroup MMC_Exported_Functions_Group3 Peripheral Control functions

+  * @{

+  */

+HAL_StatusTypeDef HAL_MMC_ConfigWideBusOperation(MMC_HandleTypeDef *hmmc, uint32_t WideMode);

+HAL_StatusTypeDef HAL_MMC_ConfigSpeedBusOperation(MMC_HandleTypeDef *hmmc, uint32_t SpeedMode);

+/**

+  * @}

+  */

+

+/** @defgroup MMC_Exported_Functions_Group4 MMC card related functions

+  * @{

+  */

+HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc);

+HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID);

+HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD);

+HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo);

+/**

+  * @}

+  */

+

+/** @defgroup MMC_Exported_Functions_Group5 Peripheral State and Errors functions

+  * @{

+  */

+HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc);

+uint32_t HAL_MMC_GetError(MMC_HandleTypeDef *hmmc);

+/**

+  * @}

+  */

+

+/** @defgroup MMC_Exported_Functions_Group6 Perioheral Abort management

+  * @{

+  */

+HAL_StatusTypeDef HAL_MMC_Abort(MMC_HandleTypeDef *hmmc);

+HAL_StatusTypeDef HAL_MMC_Abort_IT(MMC_HandleTypeDef *hmmc);

+/**

+  * @}

+  */

+

+/* Private types -------------------------------------------------------------*/

+/** @defgroup MMC_Private_Types MMC Private Types

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private defines -----------------------------------------------------------*/

+/** @defgroup MMC_Private_Defines MMC Private Defines

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private variables ---------------------------------------------------------*/

+/** @defgroup MMC_Private_Variables MMC Private Variables

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup MMC_Private_Constants MMC Private Constants

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup MMC_Private_Macros MMC Private Macros

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private functions prototypes ----------------------------------------------*/

+/** @defgroup MMC_Private_Functions_Prototypes MMC Private Functions Prototypes

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private functions ---------------------------------------------------------*/

+/** @defgroup MMC_Private_Functions MMC Private Functions

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+

+#endif /* STM32H7xx_HAL_MMC_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_mmc_ex.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_mmc_ex.h
new file mode 100644
index 0000000000..38f8838a29
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_mmc_ex.h
@@ -0,0 +1,113 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_mmc_ex.h

+  * @author  MCD Application Team

+  * @brief   Header file of SD HAL extended module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                       opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */ 

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_MMC_EX_H

+#define STM32H7xx_HAL_MMC_EX_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup MMCEx

+  * @brief SD HAL extended module driver

+  * @{

+  */ 

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup MMCEx_Exported_Types MMCEx Exported Types

+  * @{

+  */

+

+/** @defgroup MMCEx_Exported_Types_Group1 MMC Internal DMA Buffer structure

+  * @{

+  */ 

+typedef enum

+{

+  MMC_DMA_BUFFER0      = 0x00U,    /*!< selects MMC internal DMA Buffer 0     */

+  MMC_DMA_BUFFER1      = 0x01U,    /*!< selects MMC internal DMA Buffer 1     */

+

+}HAL_MMCEx_DMABuffer_MemoryTypeDef;

+

+

+/** 

+  * @}

+  */

+  

+/** 

+  * @}

+  */  

+/* Exported constants --------------------------------------------------------*/

+/* Exported macro ------------------------------------------------------------*/

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup MMCEx_Exported_Functions MMCEx Exported Functions

+  * @{

+  */

+  

+/** @defgroup MMCEx_Exported_Functions_Group1 MultiBuffer functions

+  * @{

+  */

+HAL_StatusTypeDef HAL_MMCEx_ConfigDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize);

+HAL_StatusTypeDef HAL_MMCEx_ReadBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks);

+HAL_StatusTypeDef HAL_MMCEx_WriteBlocksDMAMultiBuffer(MMC_HandleTypeDef *hmmc, uint32_t BlockAdd, uint32_t NumberOfBlocks);

+HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer);

+

+void HAL_MMCEx_Read_DMADoubleBuf0CpltCallback(MMC_HandleTypeDef *hmmc);

+void HAL_MMCEx_Read_DMADoubleBuf1CpltCallback(MMC_HandleTypeDef *hmmc);

+void HAL_MMCEx_Write_DMADoubleBuf0CpltCallback(MMC_HandleTypeDef *hmmc);

+void HAL_MMCEx_Write_DMADoubleBuf1CpltCallback(MMC_HandleTypeDef *hmmc);

+

+/**

+  * @}

+  */

+  

+/**

+  * @}

+  */

+  

+/* Private types -------------------------------------------------------------*/

+/* Private defines -----------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/* Private macros ------------------------------------------------------------*/

+/* Private functions prototypes ----------------------------------------------*/

+/* Private functions ---------------------------------------------------------*/

+  

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+#ifdef __cplusplus

+}

+#endif

+

+

+#endif /* STM32H7xx_HAL_MMCEx_H */ 

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_nand.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_nand.h
new file mode 100644
index 0000000000..1f5fd6ee48
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_nand.h
@@ -0,0 +1,367 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_nand.h

+  * @author  MCD Application Team

+  * @brief   Header file of NAND HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                       opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_NAND_H

+#define STM32H7xx_HAL_NAND_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_ll_fmc.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup NAND

+  * @{

+  */

+

+/* Exported typedef ----------------------------------------------------------*/

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup NAND_Exported_Types NAND Exported Types

+  * @{

+  */

+

+/**

+  * @brief  HAL NAND State structures definition

+  */

+typedef enum

+{

+  HAL_NAND_STATE_RESET     = 0x00U,  /*!< NAND not yet initialized or disabled */

+  HAL_NAND_STATE_READY     = 0x01U,  /*!< NAND initialized and ready for use   */

+  HAL_NAND_STATE_BUSY      = 0x02U,  /*!< NAND internal process is ongoing     */

+  HAL_NAND_STATE_ERROR     = 0x03U   /*!< NAND error state                     */

+} HAL_NAND_StateTypeDef;

+

+/**

+  * @brief  NAND Memory electronic signature Structure definition

+  */

+typedef struct

+{

+  /*<! NAND memory electronic signature maker and device IDs */

+

+  uint8_t Maker_Id;

+

+  uint8_t Device_Id;

+

+  uint8_t Third_Id;

+

+  uint8_t Fourth_Id;

+} NAND_IDTypeDef;

+

+/**

+  * @brief  NAND Memory address Structure definition

+  */

+typedef struct

+{

+  uint16_t Page;   /*!< NAND memory Page address  */

+

+  uint16_t Plane;   /*!< NAND memory Zone address  */

+

+  uint16_t Block;  /*!< NAND memory Block address */

+

+} NAND_AddressTypeDef;

+

+/**

+  * @brief  NAND Memory info Structure definition

+  */

+typedef struct

+{

+  uint32_t        PageSize;              /*!< NAND memory page (without spare area) size measured in bytes

+                                              for 8 bits adressing or words for 16 bits addressing             */

+

+  uint32_t        SpareAreaSize;         /*!< NAND memory spare area size measured in bytes

+                                              for 8 bits adressing or words for 16 bits addressing             */

+

+  uint32_t        BlockSize;             /*!< NAND memory block size measured in number of pages               */

+

+  uint32_t        BlockNbr;              /*!< NAND memory number of total blocks                               */

+

+  uint32_t        PlaneNbr;              /*!< NAND memory number of planes                                     */

+

+  uint32_t        PlaneSize;             /*!< NAND memory zone size measured in number of blocks               */

+

+  FunctionalState ExtraCommandEnable;    /*!< NAND extra command needed for Page reading mode. This

+                                              parameter is mandatory for some NAND parts after the read

+                                              command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.

+                                              Example: Toshiba THTH58BYG3S0HBAI6.

+                                              This parameter could be ENABLE or DISABLE

+                                              Please check the Read Mode sequnece in the NAND device datasheet */

+} NAND_DeviceConfigTypeDef;

+

+/**

+  * @brief  NAND handle Structure definition

+  */

+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)

+typedef struct __NAND_HandleTypeDef

+#else

+typedef struct

+#endif /* USE_HAL_NAND_REGISTER_CALLBACKS  */

+{

+  FMC_NAND_TypeDef               *Instance;  /*!< Register base address                                 */

+

+  FMC_NAND_InitTypeDef           Init;       /*!< NAND device control configuration parameters          */

+

+  HAL_LockTypeDef                Lock;       /*!< NAND locking object                                   */

+

+  __IO HAL_NAND_StateTypeDef     State;      /*!< NAND device access state                              */

+

+  NAND_DeviceConfigTypeDef       Config;     /*!< NAND phusical characteristic information structure    */

+

+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)

+  void  (* MspInitCallback)        ( struct __NAND_HandleTypeDef * hnand);    /*!< NAND Msp Init callback              */

+  void  (* MspDeInitCallback)      ( struct __NAND_HandleTypeDef * hnand);    /*!< NAND Msp DeInit callback            */

+  void  (* ItCallback)             ( struct __NAND_HandleTypeDef * hnand);    /*!< NAND IT callback                    */

+#endif

+} NAND_HandleTypeDef;

+

+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  HAL NAND Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_NAND_MSP_INIT_CB_ID       = 0x00U,  /*!< NAND MspInit Callback ID          */

+  HAL_NAND_MSP_DEINIT_CB_ID     = 0x01U,  /*!< NAND MspDeInit Callback ID        */

+  HAL_NAND_IT_CB_ID             = 0x02U   /*!< NAND IT Callback ID               */

+}HAL_NAND_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL NAND Callback pointer definition

+  */

+typedef void (*pNAND_CallbackTypeDef)(NAND_HandleTypeDef *hnand);

+#endif

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup NAND_Exported_Macros NAND Exported Macros

+ * @{

+ */

+

+/** @brief Reset NAND handle state

+  * @param  __HANDLE__ specifies the NAND handle.

+  * @retval None

+  */

+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)

+#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__)         do {                                             \

+                                                               (__HANDLE__)->State = HAL_NAND_STATE_RESET; \

+                                                               (__HANDLE__)->MspInitCallback = NULL;       \

+                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \

+                                                             } while(0)

+#else

+#define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)

+#endif

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup NAND_Exported_Functions NAND Exported Functions

+  * @{

+  */

+

+/** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions

+  * @{

+  */

+

+/* Initialization/de-initialization functions  ********************************/

+HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);

+HAL_StatusTypeDef  HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);

+

+HAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);

+

+HAL_StatusTypeDef  HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);

+

+void               HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);

+void               HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);

+void               HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);

+void               HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);

+

+/**

+  * @}

+  */

+

+/** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions

+  * @{

+  */

+

+/* IO operation functions  ****************************************************/

+HAL_StatusTypeDef  HAL_NAND_Reset(NAND_HandleTypeDef *hnand);

+

+HAL_StatusTypeDef  HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);

+HAL_StatusTypeDef  HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);

+HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);

+HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);

+

+HAL_StatusTypeDef  HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);

+HAL_StatusTypeDef  HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);

+HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);

+HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);

+

+HAL_StatusTypeDef  HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);

+

+uint32_t           HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);

+

+#if (USE_HAL_NAND_REGISTER_CALLBACKS == 1)

+/* NAND callback registering/unregistering */

+HAL_StatusTypeDef  HAL_NAND_RegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId, pNAND_CallbackTypeDef pCallback);

+HAL_StatusTypeDef  HAL_NAND_UnRegisterCallback(NAND_HandleTypeDef *hnand, HAL_NAND_CallbackIDTypeDef CallbackId);

+#endif

+

+/**

+  * @}

+  */

+

+/** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions

+  * @{

+  */

+

+/* NAND Control functions  ****************************************************/

+HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);

+HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);

+HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);

+

+/**

+  * @}

+  */

+

+/** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions

+  * @{

+  */

+/* NAND State functions *******************************************************/

+HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);

+uint32_t              HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup NAND_Private_Constants NAND Private Constants

+  * @{

+  */

+#define NAND_DEVICE                0x80000000UL

+#define NAND_WRITE_TIMEOUT         0x01000000UL

+

+#define CMD_AREA                   (1UL<<16U)  /* A16 = CLE high */

+#define ADDR_AREA                  (1UL<<17U)  /* A17 = ALE high */

+

+#define NAND_CMD_AREA_A            0x00U

+#define NAND_CMD_AREA_B            0x01U

+#define NAND_CMD_AREA_C            0x50U

+#define NAND_CMD_AREA_TRUE1        0x30U

+

+#define NAND_CMD_WRITE0            0x80U

+#define NAND_CMD_WRITE_TRUE1       0x10U

+#define NAND_CMD_ERASE0            0x60U

+#define NAND_CMD_ERASE1            0xD0U

+#define NAND_CMD_READID            0x90U

+#define NAND_CMD_STATUS            0x70U

+#define NAND_CMD_LOCK_STATUS       0x7AU

+#define NAND_CMD_RESET             0xFFU

+

+/* NAND memory status */

+#define NAND_VALID_ADDRESS         0x00000100UL

+#define NAND_INVALID_ADDRESS       0x00000200UL

+#define NAND_TIMEOUT_ERROR         0x00000400UL

+#define NAND_BUSY                  0x00000000UL

+#define NAND_ERROR                 0x00000001UL

+#define NAND_READY                 0x00000040UL

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup NAND_Private_Macros NAND Private Macros

+  * @{

+  */

+

+/**

+  * @brief  NAND memory address computation.

+  * @param  __ADDRESS__ NAND memory address.

+  * @param  __HANDLE__  NAND handle.

+  * @retval NAND Raw address value

+  */

+#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \

+                         (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))

+

+/**

+  * @brief  NAND memory Column address computation.

+  * @param  __HANDLE__ NAND handle.

+  * @retval NAND Raw address value

+  */

+#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)

+

+/**

+  * @brief  NAND memory address cycling.

+  * @param  __ADDRESS__ NAND memory address.

+  * @retval NAND address cycling value.

+  */

+#define ADDR_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st addressing cycle */

+#define ADDR_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd addressing cycle */

+#define ADDR_3RD_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 16)      /* 3rd addressing cycle */

+#define ADDR_4TH_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 24)      /* 4th addressing cycle */

+

+/**

+  * @brief  NAND memory Columns cycling.

+  * @param  __ADDRESS__ NAND memory address.

+  * @retval NAND Column address cycling value.

+  */

+#define COLUMN_1ST_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) & 0xFFU)    /* 1st Column addressing cycle */

+#define COLUMN_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd Column addressing cycle */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_NAND_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_nor.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_nor.h
new file mode 100644
index 0000000000..51c65884c1
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_nor.h
@@ -0,0 +1,321 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_nor.h

+  * @author  MCD Application Team

+  * @brief   Header file of NOR HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                       opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_NOR_H

+#define STM32H7xx_HAL_NOR_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_ll_fmc.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup NOR

+  * @{

+  */

+

+/* Exported typedef ----------------------------------------------------------*/

+/** @defgroup NOR_Exported_Types NOR Exported Types

+  * @{

+  */

+

+/**

+  * @brief  HAL SRAM State structures definition

+  */

+typedef enum

+{

+  HAL_NOR_STATE_RESET             = 0x00U,  /*!< NOR not yet initialized or disabled  */

+  HAL_NOR_STATE_READY             = 0x01U,  /*!< NOR initialized and ready for use    */

+  HAL_NOR_STATE_BUSY              = 0x02U,  /*!< NOR internal processing is ongoing   */

+  HAL_NOR_STATE_ERROR             = 0x03U,  /*!< NOR error state                      */

+  HAL_NOR_STATE_PROTECTED         = 0x04U   /*!< NOR NORSRAM device write protected   */

+} HAL_NOR_StateTypeDef;

+

+/**

+  * @brief  FMC NOR Status typedef

+  */

+typedef enum

+{

+  HAL_NOR_STATUS_SUCCESS  = 0U,

+  HAL_NOR_STATUS_ONGOING,

+  HAL_NOR_STATUS_ERROR,

+  HAL_NOR_STATUS_TIMEOUT

+} HAL_NOR_StatusTypeDef;

+

+/**

+  * @brief  FMC NOR ID typedef

+  */

+typedef struct

+{

+  uint16_t Manufacturer_Code;  /*!< Defines the device's manufacturer code used to identify the memory       */

+

+  uint16_t Device_Code1;

+

+  uint16_t Device_Code2;

+

+  uint16_t Device_Code3;       /*!< Defines the device's codes used to identify the memory.

+                                    These codes can be accessed by performing read operations with specific

+                                    control signals and addresses set.They can also be accessed by issuing

+                                    an Auto Select command                                                   */

+} NOR_IDTypeDef;

+

+/**

+  * @brief  FMC NOR CFI typedef

+  */

+typedef struct

+{

+  /*!< Defines the information stored in the memory's Common flash interface

+       which contains a description of various electrical and timing parameters,

+       density information and functions supported by the memory                   */

+

+  uint16_t CFI_1;

+

+  uint16_t CFI_2;

+

+  uint16_t CFI_3;

+

+  uint16_t CFI_4;

+} NOR_CFITypeDef;

+

+/**

+  * @brief  NOR handle Structure definition

+  */

+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)

+typedef struct __NOR_HandleTypeDef

+#else

+typedef struct

+#endif /* USE_HAL_NOR_REGISTER_CALLBACKS  */

+

+{

+  FMC_NORSRAM_TypeDef           *Instance;    /*!< Register base address                        */

+

+  FMC_NORSRAM_EXTENDED_TypeDef  *Extended;    /*!< Extended mode register base address          */

+

+  FMC_NORSRAM_InitTypeDef       Init;         /*!< NOR device control configuration parameters  */

+

+  HAL_LockTypeDef               Lock;         /*!< NOR locking object                           */

+

+  __IO HAL_NOR_StateTypeDef     State;        /*!< NOR device access state                      */

+

+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)

+  void  (* MspInitCallback)        ( struct __NOR_HandleTypeDef * hnor);    /*!< NOR Msp Init callback              */

+  void  (* MspDeInitCallback)      ( struct __NOR_HandleTypeDef * hnor);    /*!< NOR Msp DeInit callback            */

+#endif

+} NOR_HandleTypeDef;

+

+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  HAL NOR Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_NOR_MSP_INIT_CB_ID       = 0x00U,  /*!< NOR MspInit Callback ID          */

+  HAL_NOR_MSP_DEINIT_CB_ID     = 0x01U   /*!< NOR MspDeInit Callback ID        */

+}HAL_NOR_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL NOR Callback pointer definition

+  */

+typedef void (*pNOR_CallbackTypeDef)(NOR_HandleTypeDef *hnor);

+#endif

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup NOR_Exported_Macros NOR Exported Macros

+  * @{

+  */

+/** @brief Reset NOR handle state

+  * @param  __HANDLE__ specifies the NOR handle.

+  * @retval None

+  */

+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)

+#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__)          do {                                             \

+                                                               (__HANDLE__)->State = HAL_NOR_STATE_RESET;  \

+                                                               (__HANDLE__)->MspInitCallback = NULL;       \

+                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \

+                                                             } while(0)

+#else

+#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)

+#endif

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup NOR_Exported_Functions NOR Exported Functions

+  * @{

+  */

+

+/** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions

+  * @{

+  */

+

+/* Initialization/de-initialization functions  ********************************/

+HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);

+HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);

+void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);

+void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);

+void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);

+/**

+  * @}

+  */

+

+/** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions

+  * @{

+  */

+

+/* I/O operation functions  ***************************************************/

+HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);

+HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);

+HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);

+HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);

+

+HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);

+HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);

+

+HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);

+HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);

+HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);

+

+#if (USE_HAL_NOR_REGISTER_CALLBACKS == 1)

+/* NOR callback registering/unregistering */

+HAL_StatusTypeDef HAL_NOR_RegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId, pNOR_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_NOR_UnRegisterCallback(NOR_HandleTypeDef *hnor, HAL_NOR_CallbackIDTypeDef CallbackId);

+#endif

+/**

+  * @}

+  */

+

+/** @addtogroup NOR_Exported_Functions_Group3 NOR Control functions

+  * @{

+  */

+

+/* NOR Control functions  *****************************************************/

+HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);

+HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);

+/**

+  * @}

+  */

+

+/** @addtogroup NOR_Exported_Functions_Group4 NOR State functions

+  * @{

+  */

+

+/* NOR State functions ********************************************************/

+HAL_NOR_StateTypeDef  HAL_NOR_GetState(NOR_HandleTypeDef *hnor);

+HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup NOR_Private_Constants NOR Private Constants

+  * @{

+  */

+/* NOR device IDs addresses */

+#define MC_ADDRESS               ((uint16_t)0x0000)

+#define DEVICE_CODE1_ADDR        ((uint16_t)0x0001)

+#define DEVICE_CODE2_ADDR        ((uint16_t)0x000E)

+#define DEVICE_CODE3_ADDR        ((uint16_t)0x000F)

+

+/* NOR CFI IDs addresses */

+#define CFI1_ADDRESS             ((uint16_t)0x61)

+#define CFI2_ADDRESS             ((uint16_t)0x62)

+#define CFI3_ADDRESS             ((uint16_t)0x63)

+#define CFI4_ADDRESS             ((uint16_t)0x64)

+

+/* NOR operation wait timeout */

+#define NOR_TMEOUT               ((uint16_t)0xFFFF)

+

+/* NOR memory data width */

+#define NOR_MEMORY_8B            ((uint8_t)0x0)

+#define NOR_MEMORY_16B           ((uint8_t)0x1)

+

+/* NOR memory device read/write start address */

+#define NOR_MEMORY_ADRESS1       ((uint32_t)0x60000000)

+#define NOR_MEMORY_ADRESS2       ((uint32_t)0x64000000)

+#define NOR_MEMORY_ADRESS3       ((uint32_t)0x68000000)

+#define NOR_MEMORY_ADRESS4       ((uint32_t)0x6C000000)

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup NOR_Private_Macros NOR Private Macros

+  * @{

+  */

+/**

+  * @brief  NOR memory address shifting.

+  * @param  __NOR_ADDRESS NOR base address

+  * @param  __NOR_MEMORY_WIDTH_ NOR memory width

+  * @param  __ADDRESS__ NOR memory address

+  * @retval NOR shifted address value

+  */

+#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)         \

+              ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)?            \

+              ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))):              \

+              ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))

+

+/**

+  * @brief  NOR memory write data to specified address.

+  * @param  __ADDRESS__ NOR memory address

+  * @param  __DATA__ Data to write

+  * @retval None

+  */

+#define NOR_WRITE(__ADDRESS__, __DATA__)   do{                                                             \

+                                               (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__)); \

+                                               __DSB();                                                    \

+                                             } while(0)

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_NOR_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_opamp.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_opamp.h
new file mode 100644
index 0000000000..31660157da
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_opamp.h
@@ -0,0 +1,458 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_opamp.h

+  * @author  MCD Application Team

+  * @brief   Header file of OPAMP HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_OPAMP_H

+#define STM32H7xx_HAL_OPAMP_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+                  

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup OPAMP

+  * @{

+  */ 

+

+/* Exported types ------------------------------------------------------------*/ 

+

+/** @defgroup OPAMP_Exported_Types OPAMP Exported Types

+  * @{

+  */

+

+/** 

+  * @brief  OPAMP Init structure definition  

+  */

+  

+typedef struct

+{

+

+  uint32_t PowerMode;                   /*!< Specifies the power mode Normal or High Speed.

+                                             This parameter must be a value of @ref OPAMP_PowerMode */

+

+  uint32_t Mode;                        /*!< Specifies the OPAMP mode

+                                             This parameter must be a value of @ref OPAMP_Mode 

+                                             mode is either Standalone, - Follower or PGA */

+

+  uint32_t InvertingInput;              /*!< Specifies the inverting input in Standalone & PGA modes

+                                             - In Standalone mode i.e when mode is OPAMP_STANDALONE_MODE

+                                                 This parameter must be a value of @ref OPAMP_InvertingInput 

+                                             - In Follower mode i.e when mode is OPAMP_FOLLOWER_MODE

+                                           & In PGA mode i.e when mode is OPAMP_PGA_MODE 

+                                                 This parameter is Not Applicable */

+

+  uint32_t NonInvertingInput;           /*!< Specifies the non inverting input of the opamp:

+                                             This parameter must be a value of @ref OPAMP_NonInvertingInput */

+

+  uint32_t PgaGain;                     /*!< Specifies the gain in PGA mode 

+                                             i.e. when mode is OPAMP_PGA_MODE. 

+                                             This parameter must be a value of @ref OPAMP_PgaGain */

+

+  uint32_t PgaConnect;                  /*!< Specifies the inverting pin in PGA mode 

+                                             i.e. when mode is OPAMP_PGA_MODE 

+                                             This parameter must be a value of @ref OPAMP_PgaConnect 

+                                             Either: not connected, connected to VINM0, connected to VINM1

+                                             (VINM0 or VINM1 are typically used for external filtering) */

+

+  uint32_t UserTrimming;                /*!< Specifies the trimming mode 

+                                             This parameter must be a value of @ref OPAMP_UserTrimming 

+                                             UserTrimming is either factory or user trimming.*/

+

+  uint32_t TrimmingValueP;              /*!< Specifies the offset trimming value (PMOS) in Normal Mode

+                                             i.e. when UserTrimming is OPAMP_TRIMMING_USER. 

+                                             This parameter must be a number between Min_Data = 0 and Max_Data = 31.

+                                             16 is typical default value */

+

+  uint32_t TrimmingValueN;              /*!< Specifies the offset trimming value (NMOS) in Normal Mode

+                                             i.e. when UserTrimming is OPAMP_TRIMMING_USER. 

+                                             This parameter must be a number between Min_Data = 0 and Max_Data = 31.

+                                             16 is typical default value */

+

+  uint32_t TrimmingValuePHighSpeed;      /*!< Specifies the offset trimming value (PMOS) in High Speed Mode

+                                             i.e. when UserTrimming is OPAMP_TRIMMING_USER.

+                                             This parameter must be a number between Min_Data = 0 and Max_Data = 31.

+                                             16 is typical default value */

+

+  uint32_t TrimmingValueNHighSpeed;      /*!< Specifies the offset trimming value (NMOS) in High Speed Mode

+                                             i.e. when UserTrimming is OPAMP_TRIMMING_USER. 

+                                             This parameter must be a number between Min_Data = 0 and Max_Data = 31.

+                                             16 is typical default value */

+

+}OPAMP_InitTypeDef;

+

+/** 

+  * @brief  HAL State structures definition  

+  */ 

+

+typedef enum

+{

+  HAL_OPAMP_STATE_RESET               = 0x00000000U, /*!< OPAMP is not yet Initialized          */

+

+  HAL_OPAMP_STATE_READY               = 0x00000001U, /*!< OPAMP is initialized and ready for use */

+  HAL_OPAMP_STATE_CALIBBUSY           = 0x00000002U, /*!< OPAMP is enabled in auto calibration mode */

+

+  HAL_OPAMP_STATE_BUSY                = 0x00000004U, /*!< OPAMP is enabled and running in normal mode */

+  HAL_OPAMP_STATE_BUSYLOCKED          = 0x00000005U  /*!< OPAMP is locked

+                                                         only system reset allows reconfiguring the opamp. */

+

+}HAL_OPAMP_StateTypeDef;

+

+/** 

+  * @brief OPAMP Handle Structure definition

+  */ 

+#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)

+typedef struct __OPAMP_HandleTypeDef

+#else

+typedef struct

+#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */

+{

+  OPAMP_TypeDef                 *Instance;                    /*!< OPAMP instance's registers base address */

+  OPAMP_InitTypeDef              Init;                         /*!< OPAMP required parameters */

+  HAL_StatusTypeDef              Status;                       /*!< OPAMP peripheral status   */

+  HAL_LockTypeDef                Lock;                         /*!< Locking object          */

+  __IO HAL_OPAMP_StateTypeDef    State;                        /*!< OPAMP communication state */

+

+#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)

+void (* MspInitCallback)                (struct __OPAMP_HandleTypeDef *hopamp);

+void (* MspDeInitCallback)              (struct __OPAMP_HandleTypeDef *hopamp); 

+#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */ 

+} OPAMP_HandleTypeDef;

+

+/** 

+  * @brief HAl_OPAMP_TrimmingValueTypeDef definition 

+  */ 

+

+typedef  uint32_t HAL_OPAMP_TrimmingValueTypeDef;

+

+/**

+  * @}

+  */

+

+#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  HAL OPAMP Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_OPAMP_MSPINIT_CB_ID                     = 0x01U,  /*!< OPAMP MspInit Callback ID           */

+  HAL_OPAMP_MSPDEINIT_CB_ID                   = 0x02U,  /*!< OPAMP MspDeInit Callback ID         */

+  HAL_OPAMP_ALL_CB_ID                         = 0x03U   /*!< OPAMP All ID                        */

+}HAL_OPAMP_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL OPAMP Callback pointer definition

+  */

+typedef void (*pOPAMP_CallbackTypeDef)(OPAMP_HandleTypeDef *hopamp);

+#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */

+    

+    

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup OPAMP_Exported_Constants OPAMP Exported Constants

+  * @{

+  */

+

+/** @defgroup OPAMP_Mode OPAMP Mode

+  * @{

+  */

+#define OPAMP_STANDALONE_MODE             0x00000000U                                  /*!< standalone mode */

+#define OPAMP_PGA_MODE                    OPAMP_CSR_VMSEL_1                            /*!< PGA mode */

+#define OPAMP_FOLLOWER_MODE               (OPAMP_CSR_VMSEL_1 | OPAMP_CSR_VMSEL_0)      /*!< follower mode */

+    

+/**

+  * @}

+  */

+

+/** @defgroup OPAMP_NonInvertingInput OPAMP Non Inverting Input

+  * @{

+  */

+

+#define OPAMP_NONINVERTINGINPUT_IO0         0x00000000U                /*!< OPAMP non-inverting input connected to dedicated IO pin */

+#define OPAMP_NONINVERTINGINPUT_DAC_CH      OPAMP_CSR_VPSEL_0          /*!< OPAMP non-inverting input connected internally to DAC channel */

+#if defined(DAC2)

+#define OPAMP_NONINVERTINGINPUT_DAC2_CH     OPAMP_CSR_VPSEL_1         /*!< Only OPAMP2 non-inverting input connected internally to DAC2 channel */

+#endif /* DAC2 */

+

+/**

+  * @}

+  */

+

+/** @defgroup OPAMP_InvertingInput OPAMP Inverting Input

+  * @{

+  */

+

+#define OPAMP_INVERTINGINPUT_IO0               0x00000000U                            /*!< OPAMP inverting input connected to dedicated IO pin */

+#define OPAMP_INVERTINGINPUT_IO1               OPAMP_CSR_VMSEL_0                      /*!< OPAMP inverting input connected to dedicated IO pin */

+

+/**

+  * @}

+  */

+

+/** @defgroup OPAMP_PgaConnect OPAMP Pga Connect

+  * @{

+  */

+

+#define OPAMP_PGA_CONNECT_INVERTINGINPUT_NO                0x00000000U                                /*!< In PGA mode, the inverting input is not connected */

+#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0               OPAMP_CSR_PGGAIN_2                         /*!< In PGA mode, the inverting input is connected to VINM0 */

+#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS          OPAMP_CSR_PGGAIN_3                         /*!< In PGA mode, the inverting input is connected to VINM0 or bias */

+#define OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS      (OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_PGGAIN_3)  /*!< In PGA mode, the inverting input is connected to VINM0 or bias , VINM1 connected for filtering */

+

+

+/**

+  * @}

+  */

+

+/** @defgroup OPAMP_PgaGain OPAMP Pga Gain

+  * @{

+  */

+

+#define OPAMP_PGA_GAIN_2_OR_MINUS_1               0x00000000U                                 /*!< PGA gain could be 2 or -1   */

+#define OPAMP_PGA_GAIN_4_OR_MINUS_3               OPAMP_CSR_PGGAIN_0                          /*!< PGA gain could be 4 or -3   */

+#define OPAMP_PGA_GAIN_8_OR_MINUS_7               OPAMP_CSR_PGGAIN_1                          /*!< PGA gain could be 8 or -7   */

+#define OPAMP_PGA_GAIN_16_OR_MINUS_15             (OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1)   /*!< PGA gain could be 16 or -15 */

+

+/**

+  * @}

+  */

+

+/** @defgroup OPAMP_PowerMode OPAMP PowerMode

+  * @{

+  */

+#define OPAMP_POWERMODE_NORMAL         0x00000000U

+#define OPAMP_POWERMODE_HIGHSPEED      OPAMP_CSR_OPAHSM

+

+/**

+  * @}

+  */

+

+

+/** @defgroup OPAMP_VREF OPAMP VREF

+  * @{

+  */

+

+#define OPAMP_VREF_3VDDA                     0x00000000U                 /*!< OPAMP Vref = 3.3% VDDA */

+#define OPAMP_VREF_10VDDA                    OPAMP_CSR_CALSEL_0          /*!< OPAMP Vref = 10% VDDA  */

+#define OPAMP_VREF_50VDDA                    OPAMP_CSR_CALSEL_1          /*!< OPAMP Vref = 50% VDDA  */

+#define OPAMP_VREF_90VDDA                    OPAMP_CSR_CALSEL            /*!< OPAMP Vref = 90% VDDA  */

+

+/**

+  * @}

+  */ 

+

+/** @defgroup OPAMP_UserTrimming OPAMP User Trimming

+  * @{

+  */

+#define OPAMP_TRIMMING_FACTORY         0x00000000U                             /*!< Factory trimming */

+#define OPAMP_TRIMMING_USER            OPAMP_CSR_USERTRIM                      /*!< User trimming */

+

+

+/**

+  * @}

+  */

+

+/** @defgroup OPAMP_FactoryTrimming OPAMP Factory Trimming

+  * @{

+  */

+#define OPAMP_FACTORYTRIMMING_DUMMY    0xFFFFFFFFU                          /*!< Dummy value if trimming value could not be retrieved */

+

+#define OPAMP_FACTORYTRIMMING_N        0x00000000U                          /*!< Offset trimming N */

+#define OPAMP_FACTORYTRIMMING_P        0x00000001U                          /*!< Offset trimming P */

+

+/**

+  * @}

+  */

+

+ /**

+  * @}

+  */ 

+

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup OPAMP_Private_Constants OPAMP Private Constants

+  * @brief   OPAMP Private constants and defines

+  * @{

+  */

+

+/* NONINVERTING bit position in OTR & HSOTR */

+#define OPAMP_INPUT_NONINVERTING           (8U)  /*!< Non inverting input */  

+

+/* Offset trimming time: during calibration, minimum time needed between two  */

+/* steps to have 1 mV accuracy.                                               */

+/* Refer to datasheet, electrical characteristics: parameter tOFFTRIM Typ=2ms.*/

+/* Unit: ms.                                                                  */

+#define OPAMP_TRIMMING_DELAY               (2U)

+

+/**

+  * @}

+  */

+

+/* Exported macros -----------------------------------------------------------*/

+/** @defgroup OPAMP_Exported_Macros OPAMP Exported Macros

+  * @{

+  */

+

+/** @brief Reset OPAMP handle state.

+  * @param  __HANDLE__: OPAMP handle.

+  * @retval None

+  */

+#define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)

+

+/**

+  * @}

+  */ 

+

+/* Private macro -------------------------------------------------------------*/

+

+/** @defgroup OPAMP_Private_Macros OPAMP Private Macros

+  * @{

+  */

+

+#define IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT) (((INPUT) == OPAMP_STANDALONE_MODE) || \

+                                               ((INPUT) == OPAMP_PGA_MODE) || \

+                                               ((INPUT) == OPAMP_FOLLOWER_MODE))

+

+#define IS_OPAMP_INVERTING_INPUT_STANDALONE(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_IO0) || \

+                                                    ((INPUT) == OPAMP_INVERTINGINPUT_IO1))

+

+#if defined(DAC2)

+#define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \

+                                            ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH) || \

+                                            ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC2_CH))

+#else 

+#define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_IO0) || \

+                                            ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH))

+#endif /* DAC2 */

+

+#define IS_OPAMP_PGACONNECT(CONNECT) (((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_NO)  || \

+                                      ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0) || \

+                                      ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_BIAS) || \

+                                      ((CONNECT) == OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0_IO1_BIAS))

+

+#define IS_OPAMP_PGA_GAIN(GAIN) (((GAIN) == OPAMP_PGA_GAIN_2_OR_MINUS_1) || \

+                                 ((GAIN) == OPAMP_PGA_GAIN_4_OR_MINUS_3) || \

+                                 ((GAIN) == OPAMP_PGA_GAIN_8_OR_MINUS_7) || \

+                                 ((GAIN) == OPAMP_PGA_GAIN_16_OR_MINUS_15))

+

+

+#define IS_OPAMP_VREF(VREF) (((VREF) == OPAMP_VREF_3VDDA)  || \

+                             ((VREF) == OPAMP_VREF_10VDDA) || \

+                             ((VREF) == OPAMP_VREF_50VDDA) || \

+                             ((VREF) == OPAMP_VREF_90VDDA))

+

+#define IS_OPAMP_POWERMODE(TRIMMING) (((TRIMMING) == OPAMP_POWERMODE_NORMAL) || \

+                                      ((TRIMMING) == OPAMP_POWERMODE_HIGHSPEED) )

+

+

+#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \

+                                     ((TRIMMING) == OPAMP_TRIMMING_USER))

+

+

+#define IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1FU)

+

+#define IS_OPAMP_FACTORYTRIMMING(TRIMMING) (((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \

+                                             ((TRIMMING) == OPAMP_FACTORYTRIMMING_P))

+

+/**

+  * @}

+  */ 

+

+/* Include OPAMP HAL Extended module */

+#include "stm32h7xx_hal_opamp_ex.h"

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup OPAMP_Exported_Functions

+  * @{

+  */

+

+/** @addtogroup OPAMP_Exported_Functions_Group1

+  * @{

+  */

+/* Initialization/de-initialization functions  **********************************/

+HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp);

+HAL_StatusTypeDef HAL_OPAMP_DeInit (OPAMP_HandleTypeDef *hopamp);

+void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp);

+void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp);

+/**

+  * @}

+  */

+

+/** @addtogroup OPAMP_Exported_Functions_Group2

+  * @{

+  */

+

+/* I/O operation functions  *****************************************************/

+HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp);

+HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp);

+HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp); 

+

+/**

+  * @}

+  */

+

+/** @addtogroup OPAMP_Exported_Functions_Group3

+  * @{

+  */

+

+/* Peripheral Control functions  ************************************************/

+#if (USE_HAL_OPAMP_REGISTER_CALLBACKS == 1)

+/* OPAMP callback registering/unregistering */

+HAL_StatusTypeDef HAL_OPAMP_RegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId, pOPAMP_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_OPAMP_UnRegisterCallback (OPAMP_HandleTypeDef *hopamp, HAL_OPAMP_CallbackIDTypeDef CallbackId);

+#endif /* USE_HAL_OPAMP_REGISTER_CALLBACKS */

+HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp);

+HAL_OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset);

+

+/**

+  * @}

+  */

+

+/** @addtogroup OPAMP_Exported_Functions_Group4

+  * @{

+  */

+

+/* Peripheral State functions  **************************************************/

+HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */ 

+

+/**

+  * @}

+  */ 

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_OPAMP_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_opamp_ex.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_opamp_ex.h
new file mode 100644
index 0000000000..41e661db42
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_opamp_ex.h
@@ -0,0 +1,83 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_opamp_ex.h

+  * @author  MCD Application Team

+  * @brief   Header file of OPAMP HAL Extended module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_OPAMP_EX_H

+#define STM32H7xx_HAL_OPAMP_EX_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup OPAMPEx

+  * @{

+  */

+/* Exported types ------------------------------------------------------------*/

+/* Exported constants --------------------------------------------------------*/

+/* Exported macro ------------------------------------------------------------*/

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup OPAMPEx_Exported_Functions OPAMPEx Exported Functions

+  * @{

+  */

+

+/* Extended IO operation functions  *****************************************************/

+/** @addtogroup OPAMPEx_Exported_Functions_Group1 

+  * @{

+  */

+HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2); 

+

+/**

+  * @}

+  */

+/* Peripheral Control functions  ************************************************/

+/** @addtogroup OPAMPEx_Exported_Functions_Group2

+  * @{

+  */

+HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef *hopamp); 

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+

+#endif /* STM32H7xx_HAL_OPAMP_EX_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_ospi.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_ospi.h
new file mode 100644
index 0000000000..99ddf222c9
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_ospi.h
@@ -0,0 +1,1076 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_ospi.h

+  * @author  MCD Application Team

+  * @brief   Header file of OSPI HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                       opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_OSPI_H

+#define STM32H7xx_HAL_OSPI_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+#if defined(OCTOSPI) || defined(OCTOSPI1) || defined(OCTOSPI2)

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup OSPI

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup OSPI_Exported_Types OSPI Exported Types

+  * @{

+  */

+

+/**

+  * @brief OSPI Init structure definition

+  */

+typedef struct

+{

+  uint32_t FifoThreshold;             /* This is the threshold used by the Peripheral to generate the interrupt

+                                         indicating that data are available in reception or free place

+                                         is available in transmission.

+                                         This parameter can be a value between 1 and 32 */

+  uint32_t DualQuad;                  /* It enables or not the dual-quad mode which allow to access up to

+                                         quad mode on two different devices to increase the throughput.

+                                         This parameter can be a value of @ref OSPI_DualQuad */

+  uint32_t MemoryType;                /* It indicates the external device type connected to the OSPI.

+                                         This parameter can be a value of @ref OSPI_MemoryType */

+  uint32_t DeviceSize;                /* It defines the size of the external device connected to the OSPI,

+                                         it corresponds to the number of address bits required to access

+                                         the external device.

+                                         This parameter can be a value between 1 and 32 */

+  uint32_t ChipSelectHighTime;        /* It defines the minimun number of clocks which the chip select

+                                         must remain high between commands.

+                                         This parameter can be a value between 1 and 8 */

+  uint32_t FreeRunningClock;          /* It enables or not the free running clock.

+                                         This parameter can be a value of @ref OSPI_FreeRunningClock */

+  uint32_t ClockMode;                 /* It indicates the level of clock when the chip select is released.

+                                         This parameter can be a value of @ref OSPI_ClockMode */

+  uint32_t WrapSize;                  /* It indicates the wrap-size corresponding the external device configuration.

+                                         This parameter can be a value of @ref OSPI_WrapSize */

+  uint32_t ClockPrescaler;            /* It specifies the prescaler factor used for generating

+                                         the external clock based on the AHB clock.

+                                         This parameter can be a value between 1 and 256 */

+  uint32_t SampleShifting;            /* It allows to delay to 1/2 cycle the data sampling in order

+                                         to take in account external signal delays.

+                                         This parameter can be a value of @ref OSPI_SampleShifting */

+  uint32_t DelayHoldQuarterCycle;     /* It allows to hold to 1/4 cycle the data.

+                                         This parameter can be a value of @ref OSPI_DelayHoldQuarterCycle */

+  uint32_t ChipSelectBoundary;        /* It enables the transaction boundary feature and

+                                         defines the boundary of bytes to release the chip select.

+                                         This parameter can be a value between 0 and 31 */

+  uint32_t ClkChipSelectHighTime;     /* It defines the number of clocks provided on the CLK/nCLK pins when

+                                         the chip select is set to high at the end of a transaction.

+                                         This parameter can be a value between 0 and 7 */

+  uint32_t DelayBlockBypass;          /* It enables the delay block bypass, so the sampling is not affected

+                                         by the delay block.

+                                         This parameter can be a value of @ref OSPI_DelayBlockBypass */

+  uint32_t MaxTran;                   /* It enables the communication regulation feature. The chip select is

+                                         released every MaxTran+1 bytes when the other OctoSPI request the access

+                                         to the bus.

+                                         This parameter can be a value between 0 and 255 */

+  uint32_t Refresh;                   /* It enables the refresh rate feature. The chip select is released every

+                                         Refresh+1 clock cycles.

+                                         This parameter can be a value between 0 and 0xFFFFFFFF */

+}OSPI_InitTypeDef;

+

+/**

+  * @brief  HAL OSPI Handle Structure definition

+  */

+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)

+typedef struct __OSPI_HandleTypeDef

+#else

+typedef struct

+#endif

+{

+  OCTOSPI_TypeDef            *Instance;     /* OSPI registers base address                      */

+  OSPI_InitTypeDef           Init;          /* OSPI initialization parameters                   */

+  uint8_t                    *pBuffPtr;     /* Address of the OSPI buffer for transfer          */

+  __IO uint32_t              XferSize;      /* Number of data to transfer                       */

+  __IO uint32_t              XferCount;     /* Counter of data transferred                      */

+  MDMA_HandleTypeDef     *hmdma;    /* Handle of the MDMA channel used for the transfer  */

+  __IO uint32_t              State;         /* Internal state of the OSPI HAL driver            */

+  __IO uint32_t              ErrorCode;     /* Error code in case of HAL driver internal error  */

+  uint32_t                   Timeout;       /* Timeout used for the OSPI external device access */

+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)

+  void (* ErrorCallback)        (struct __OSPI_HandleTypeDef *hospi);

+  void (* AbortCpltCallback)    (struct __OSPI_HandleTypeDef *hospi);

+  void (* FifoThresholdCallback)(struct __OSPI_HandleTypeDef *hospi);

+  void (* CmdCpltCallback)      (struct __OSPI_HandleTypeDef *hospi);

+  void (* RxCpltCallback)       (struct __OSPI_HandleTypeDef *hospi);

+  void (* TxCpltCallback)       (struct __OSPI_HandleTypeDef *hospi);

+  void (* RxHalfCpltCallback)   (struct __OSPI_HandleTypeDef *hospi);

+  void (* TxHalfCpltCallback)   (struct __OSPI_HandleTypeDef *hospi);

+  void (* StatusMatchCallback)  (struct __OSPI_HandleTypeDef *hospi);

+  void (* TimeOutCallback)      (struct __OSPI_HandleTypeDef *hospi);

+

+  void (* MspInitCallback)      (struct __OSPI_HandleTypeDef *hospi);

+  void (* MspDeInitCallback)    (struct __OSPI_HandleTypeDef *hospi);

+#endif

+}OSPI_HandleTypeDef;

+

+/**

+  * @brief  HAL OSPI Regular Command Structure definition

+  */

+typedef struct

+{

+  uint32_t OperationType;             /* It indicates if the configuration applies to the common regsiters or

+                                         to the registers for the write operation (these registers are only

+                                         used for memory-mapped mode).

+                                         This parameter can be a value of @ref OSPI_OperationType */

+  uint32_t FlashId;                   /* It indicates which external device is selected for this command (it

+                                         applies only if Dualquad is disabled in the initialization structure).

+                                         This parameter can be a value of @ref OSPI_FlashId */

+  uint32_t Instruction;               /* It contains the instruction to be sent to the device.

+                                         This parameter can be a value between 0 and 0xFFFFFFFF */

+  uint32_t InstructionMode;           /* It indicates the mode of the instruction.

+                                         This parameter can be a value of @ref OSPI_InstructionMode */

+  uint32_t InstructionSize;           /* It indicates the size of the instruction.

+                                         This parameter can be a value of @ref OSPI_InstructionSize */

+  uint32_t InstructionDtrMode;        /* It enables or not the DTR mode for the instruction phase.

+                                         This parameter can be a value of @ref OSPI_InstructionDtrMode */

+  uint32_t Address;                   /* It contains the address to be sent to the device.

+                                         This parameter can be a value between 0 and 0xFFFFFFFF */

+  uint32_t AddressMode;               /* It indicates the mode of the address.

+                                         This parameter can be a value of @ref OSPI_AddressMode */

+  uint32_t AddressSize;               /* It indicates the size of the address.

+                                         This parameter can be a value of @ref OSPI_AddressSize */

+  uint32_t AddressDtrMode;            /* It enables or not the DTR mode for the address phase.

+                                         This parameter can be a value of @ref OSPI_AddressDtrMode */

+  uint32_t AlternateBytes;            /* It contains the alternate bytes to be sent to the device.

+                                         This parameter can be a value between 0 and 0xFFFFFFFF */

+  uint32_t AlternateBytesMode;        /* It indicates the mode of the alternate bytes.

+                                         This parameter can be a value of @ref OSPI_AlternateBytesMode */

+  uint32_t AlternateBytesSize;        /* It indicates the size of the alternate bytes.

+                                         This parameter can be a value of @ref OSPI_AlternateBytesSize */

+  uint32_t AlternateBytesDtrMode;     /* It enables or not the DTR mode for the alternate bytes phase.

+                                         This parameter can be a value of @ref OSPI_AlternateBytesDtrMode */

+  uint32_t DataMode;                  /* It indicates the mode of the data.

+                                         This parameter can be a value of @ref OSPI_DataMode */

+  uint32_t NbData;                    /* It indicates the number of data transferred with this command.

+                                         This field is only used for indirect mode.

+                                         This parameter can be a value between 1 and 0xFFFFFFFF */

+  uint32_t DataDtrMode;               /* It enables or not the DTR mode for the data phase.

+                                         This parameter can be a value of @ref OSPI_DataDtrMode */

+  uint32_t DummyCycles;               /* It indicates the number of dummy cycles inserted before data phase.

+                                         This parameter can be a value between 0 and 31 */

+  uint32_t DQSMode;                   /* It enables or not the data strobe management.

+                                         This parameter can be a value of @ref OSPI_DQSMode */

+  uint32_t SIOOMode;                  /* It enables or not the SIOO mode.

+                                         This parameter can be a value of @ref OSPI_SIOOMode */

+}OSPI_RegularCmdTypeDef;

+

+/**

+  * @brief  HAL OSPI Hyperbus Configuration Structure definition

+  */

+typedef struct

+{

+  uint32_t RWRecoveryTime;       /* It indicates the number of cycles for the device read write recovery time.

+                                    This parameter can be a value between 0 and 255 */

+  uint32_t AccessTime;           /* It indicates the number of cycles for the device acces time.

+                                    This parameter can be a value between 0 and 255 */

+  uint32_t WriteZeroLatency;     /* It enables or not the latency for the write access.

+                                    This parameter can be a value of @ref OSPI_WriteZeroLatency */

+  uint32_t LatencyMode;          /* It configures the latency mode.

+                                    This parameter can be a value of @ref OSPI_LatencyMode */

+}OSPI_HyperbusCfgTypeDef;

+

+/**

+  * @brief  HAL OSPI Hyperbus Command Structure definition

+  */

+typedef struct

+{

+  uint32_t AddressSpace;     /* It indicates the address space accessed by the command.

+                                This parameter can be a value of @ref OSPI_AddressSpace */

+  uint32_t Address;          /* It contains the address to be sent tot he device.

+                                This parameter can be a value between 0 and 0xFFFFFFFF */

+  uint32_t AddressSize;      /* It indicates the size of the address.

+                                This parameter can be a value of @ref OSPI_AddressSize */

+  uint32_t NbData;           /* It indicates the number of data transferred with this command.

+                                This field is only used for indirect mode.

+                                This parameter can be a value between 1 and 0xFFFFFFFF

+                                In case of autopolling mode, this parameter can be any value between 1 and 4 */

+  uint32_t DQSMode;          /* It enables or not the data strobe management.

+                                This parameter can be a value of @ref OSPI_DQSMode */

+}OSPI_HyperbusCmdTypeDef;

+

+/**

+  * @brief  HAL OSPI Auto Polling mode configuration structure definition

+  */

+typedef struct

+{

+  uint32_t Match;              /* Specifies the value to be compared with the masked status register to get a match.

+                                  This parameter can be any value between 0 and 0xFFFFFFFF */

+  uint32_t Mask;               /* Specifies the mask to be applied to the status bytes received.

+                                  This parameter can be any value between 0 and 0xFFFFFFFF */

+  uint32_t MatchMode;          /* Specifies the method used for determining a match.

+                                  This parameter can be a value of @ref OSPI_MatchMode */

+  uint32_t AutomaticStop;      /* Specifies if automatic polling is stopped after a match.

+                                  This parameter can be a value of @ref OSPI_AutomaticStop */

+  uint32_t Interval;           /* Specifies the number of clock cycles between two read during automatic polling phases.

+                                  This parameter can be any value between 0 and 0xFFFF */

+}OSPI_AutoPollingTypeDef;

+

+/**

+  * @brief  HAL OSPI Memory Mapped mode configuration structure definition

+  */

+typedef struct

+{

+  uint32_t TimeOutActivation;  /* Specifies if the timeout counter is enabled to release the chip select.

+                                  This parameter can be a value of @ref OSPI_TimeOutActivation */

+  uint32_t TimeOutPeriod;      /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.

+                                  This parameter can be any value between 0 and 0xFFFF */

+}OSPI_MemoryMappedTypeDef;

+

+/**

+  * @brief HAL OSPI IO Manager Configuration structure definition

+  */

+typedef struct

+{

+  uint32_t ClkPort;                /* It indicates which port of the OSPI IO Manager is used for the CLK pins.

+                                      This parameter can be a value between 1 and 8 */

+  uint32_t DQSPort;                /* It indicates which port of the OSPI IO Manager is used for the DQS pin.

+                                      This parameter can be a value between 1 and 8 */

+  uint32_t NCSPort;                /* It indicates which port of the OSPI IO Manager is used for the NCS pin.

+                                      This parameter can be a value between 1 and 8 */

+  uint32_t IOLowPort;              /* It indicates which port of the OSPI IO Manager is used for the IO[3:0] pins.

+                                      This parameter can be a value of @ref OSPIM_IOPort */

+  uint32_t IOHighPort;             /* It indicates which port of the OSPI IO Manager is used for the IO[7:4] pins.

+                                      This parameter can be a value of @ref OSPIM_IOPort */

+  uint32_t Req2AckTime;            /* It indicates the minimum switching duration (in number of clock cycles) expected 

+                                      if some signals are multiplexed in the OSPI IO Manager with the other OSPI.

+                                      This parameter can be a value between 1 and 256 */

+}OSPIM_CfgTypeDef;

+

+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)

+/**

+  * @brief  HAL OSPI Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_OSPI_ERROR_CB_ID          = 0x00U,  /*!< OSPI Error Callback ID            */

+  HAL_OSPI_ABORT_CB_ID          = 0x01U,  /*!< OSPI Abort Callback ID            */

+  HAL_OSPI_FIFO_THRESHOLD_CB_ID = 0x02U,  /*!< OSPI FIFO Threshold Callback ID   */

+  HAL_OSPI_CMD_CPLT_CB_ID       = 0x03U,  /*!< OSPI Command Complete Callback ID */

+  HAL_OSPI_RX_CPLT_CB_ID        = 0x04U,  /*!< OSPI Rx Complete Callback ID      */

+  HAL_OSPI_TX_CPLT_CB_ID        = 0x05U,  /*!< OSPI Tx Complete Callback ID      */

+  HAL_OSPI_RX_HALF_CPLT_CB_ID   = 0x06U,  /*!< OSPI Rx Half Complete Callback ID */

+  HAL_OSPI_TX_HALF_CPLT_CB_ID   = 0x07U,  /*!< OSPI Tx Half Complete Callback ID */

+  HAL_OSPI_STATUS_MATCH_CB_ID   = 0x08U,  /*!< OSPI Status Match Callback ID     */

+  HAL_OSPI_TIMEOUT_CB_ID        = 0x09U,  /*!< OSPI Timeout Callback ID          */

+

+  HAL_OSPI_MSP_INIT_CB_ID       = 0x0AU,  /*!< OSPI MspInit Callback ID          */

+  HAL_OSPI_MSP_DEINIT_CB_ID     = 0x0BU   /*!< OSPI MspDeInit Callback ID        */

+}HAL_OSPI_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL OSPI Callback pointer definition

+  */

+typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi);

+#endif

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup OSPI_Exported_Constants OSPI Exported Constants

+  * @{

+  */

+

+/** @defgroup OSPI_State OSPI State

+  * @{

+  */

+#define HAL_OSPI_STATE_RESET                 ((uint32_t)0x00000000U)      /*!< Initial state                                                          */

+#define HAL_OSPI_STATE_HYPERBUS_INIT         ((uint32_t)0x00000001U)      /*!< Initialization done in hyperbus mode but timing configuration not done */

+#define HAL_OSPI_STATE_READY                 ((uint32_t)0x00000002U)      /*!< Driver ready to be used                                                */

+#define HAL_OSPI_STATE_CMD_CFG               ((uint32_t)0x00000004U)      /*!< Command (regular or hyperbus) configured, ready for an action          */

+#define HAL_OSPI_STATE_READ_CMD_CFG          ((uint32_t)0x00000014U)      /*!< Read command configuration done, not the write command configuration   */

+#define HAL_OSPI_STATE_WRITE_CMD_CFG         ((uint32_t)0x00000024U)      /*!< Write command configuration done, not the read command configuration   */

+#define HAL_OSPI_STATE_BUSY_CMD              ((uint32_t)0x00000008U)      /*!< Command without data on-going                                          */

+#define HAL_OSPI_STATE_BUSY_TX               ((uint32_t)0x00000018U)      /*!< Indirect Tx on-going                                                   */

+#define HAL_OSPI_STATE_BUSY_RX               ((uint32_t)0x00000028U)      /*!< Indirect Rx on-going                                                   */

+#define HAL_OSPI_STATE_BUSY_AUTO_POLLING     ((uint32_t)0x00000048U)      /*!< Auto-polling on-going                                                  */

+#define HAL_OSPI_STATE_BUSY_MEM_MAPPED       ((uint32_t)0x00000088U)      /*!< Memory-mapped on-going                                                 */

+#define HAL_OSPI_STATE_ABORT                 ((uint32_t)0x00000100U)      /*!< Abort on-going                                                         */

+#define HAL_OSPI_STATE_ERROR                 ((uint32_t)0x00000200U)      /*!< Blocking error, driver should be re-initialized                        */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_ErrorCode OSPI Error Code

+  * @{

+  */

+#define HAL_OSPI_ERROR_NONE                  ((uint32_t)0x00000000U)                                         /*!< No error                                   */

+#define HAL_OSPI_ERROR_TIMEOUT               ((uint32_t)0x00000001U)                                         /*!< Timeout error                              */

+#define HAL_OSPI_ERROR_TRANSFER              ((uint32_t)0x00000002U)                                         /*!< Transfer error                             */

+#define HAL_OSPI_ERROR_DMA                   ((uint32_t)0x00000004U)                                         /*!< DMA transfer error                         */

+#define HAL_OSPI_ERROR_INVALID_PARAM         ((uint32_t)0x00000008U)                                         /*!< Invalid parameters error                   */

+#define HAL_OSPI_ERROR_INVALID_SEQUENCE      ((uint32_t)0x00000010U)                                         /*!< Sequence of the state machine is incorrect */

+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)

+#define HAL_OSPI_ERROR_INVALID_CALLBACK      ((uint32_t)0x00000020U)                                         /*!< Invalid callback error                     */

+#endif

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_DualQuad OSPI Dual-Quad

+  * @{

+  */

+#define HAL_OSPI_DUALQUAD_DISABLE            ((uint32_t)0x00000000U)                                         /*!< Dual-Quad mode disabled */

+#define HAL_OSPI_DUALQUAD_ENABLE             ((uint32_t)OCTOSPI_CR_DQM)                                      /*!< Dual-Quad mode enabled  */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_MemoryType OSPI Memory Type

+  * @{

+  */

+#define HAL_OSPI_MEMTYPE_MICRON              ((uint32_t)0x00000000U)                                         /*!< Micron mode       */

+#define HAL_OSPI_MEMTYPE_MACRONIX            ((uint32_t)OCTOSPI_DCR1_MTYP_0)                                 /*!< Macronix mode     */

+#define HAL_OSPI_MEMTYPE_APMEMORY            ((uint32_t)OCTOSPI_DCR1_MTYP_1)                                 /*!< AP Memory mode    */

+#define HAL_OSPI_MEMTYPE_MACRONIX_RAM        ((uint32_t)(OCTOSPI_DCR1_MTYP_1 | OCTOSPI_DCR1_MTYP_0))         /*!< Macronix RAM mode */

+#define HAL_OSPI_MEMTYPE_HYPERBUS            ((uint32_t)OCTOSPI_DCR1_MTYP_2)                                 /*!< Hyperbus mode     */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_FreeRunningClock OSPI Free Running Clock

+  * @{

+  */

+#define HAL_OSPI_FREERUNCLK_DISABLE          ((uint32_t)0x00000000U)                                         /*!< CLK is not free running               */

+#define HAL_OSPI_FREERUNCLK_ENABLE           ((uint32_t)OCTOSPI_DCR1_FRCK)                                   /*!< CLK is free running (always provided) */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_ClockMode OSPI Clock Mode

+  * @{

+  */

+#define HAL_OSPI_CLOCK_MODE_0                ((uint32_t)0x00000000U)                                         /*!< CLK must stay low while nCS is high  */

+#define HAL_OSPI_CLOCK_MODE_3                ((uint32_t)OCTOSPI_DCR1_CKMODE)                                 /*!< CLK must stay high while nCS is high */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_WrapSize OSPI Wrap-Size

+  * @{

+  */

+#define HAL_OSPI_WRAP_NOT_SUPPORTED          ((uint32_t)0x00000000U)                                         /*!< wrapped reads are not supported by the memory   */

+#define HAL_OSPI_WRAP_16_BYTES               ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_1)                             /*!< external memory supports wrap size of 16 bytes  */

+#define HAL_OSPI_WRAP_32_BYTES               ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_1)) /*!< external memory supports wrap size of 32 bytes  */

+#define HAL_OSPI_WRAP_64_BYTES               ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_2)                             /*!< external memory supports wrap size of 64 bytes  */

+#define HAL_OSPI_WRAP_128_BYTES              ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_2)) /*!< external memory supports wrap size of 128 bytes */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_SampleShifting OSPI Sample Shifting

+  * @{

+  */

+#define HAL_OSPI_SAMPLE_SHIFTING_NONE        ((uint32_t)0x00000000U)                                         /*!< No shift        */

+#define HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE   ((uint32_t)OCTOSPI_TCR_SSHIFT)                                  /*!< 1/2 cycle shift */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_DelayHoldQuarterCycle OSPI Delay Hold Quarter Cycle

+  * @{

+  */

+#define HAL_OSPI_DHQC_DISABLE                ((uint32_t)0x00000000U)                                         /*!< No Delay             */

+#define HAL_OSPI_DHQC_ENABLE                 ((uint32_t)OCTOSPI_TCR_DHQC)                                    /*!< Delay Hold 1/4 cycle */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_DelayBlockBypass OSPI Delay Block Bypaas

+  * @{

+  */

+#define HAL_OSPI_DELAY_BLOCK_USED            ((uint32_t)0x00000000U)                                         /*!< Sampling clock is delayed by the delay block */

+#define HAL_OSPI_DELAY_BLOCK_BYPASSED        ((uint32_t)OCTOSPI_DCR1_DLYBYP)                                 /*!< Delay block is bypassed                      */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_OperationType OSPI Operation Type

+  * @{

+  */

+#define HAL_OSPI_OPTYPE_COMMON_CFG           ((uint32_t)0x00000000U)                                         /*!< Common configuration (indirect or auto-polling mode) */

+#define HAL_OSPI_OPTYPE_READ_CFG             ((uint32_t)0x00000001U)                                         /*!< Read configuration (memory-mapped mode)              */

+#define HAL_OSPI_OPTYPE_WRITE_CFG            ((uint32_t)0x00000002U)                                         /*!< Write configuration (memory-mapped mode)             */

+#define HAL_OSPI_OPTYPE_WRAP_CFG             ((uint32_t)0x00000003U)                                         /*!< Wrap configuration (memory-mapped mode)              */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_FlashID OSPI Flash Id

+  * @{

+  */

+#define HAL_OSPI_FLASH_ID_1                  ((uint32_t)0x00000000U)                                         /*!< FLASH 1 selected */

+#define HAL_OSPI_FLASH_ID_2                  ((uint32_t)OCTOSPI_CR_FSEL)                                     /*!< FLASH 2 selected */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_InstructionMode OSPI Instruction Mode

+  * @{

+  */

+#define HAL_OSPI_INSTRUCTION_NONE            ((uint32_t)0x00000000U)                                         /*!< No instruction               */

+#define HAL_OSPI_INSTRUCTION_1_LINE          ((uint32_t)OCTOSPI_CCR_IMODE_0)                                 /*!< Instruction on a single line */

+#define HAL_OSPI_INSTRUCTION_2_LINES         ((uint32_t)OCTOSPI_CCR_IMODE_1)                                 /*!< Instruction on two lines     */

+#define HAL_OSPI_INSTRUCTION_4_LINES         ((uint32_t)(OCTOSPI_CCR_IMODE_0 | OCTOSPI_CCR_IMODE_1))         /*!< Instruction on four lines    */

+#define HAL_OSPI_INSTRUCTION_8_LINES         ((uint32_t)OCTOSPI_CCR_IMODE_2)                                 /*!< Instruction on eight lines   */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_InstructionSize OSPI Instruction Size

+  * @{

+  */

+#define HAL_OSPI_INSTRUCTION_8_BITS          ((uint32_t)0x00000000U)                                         /*!< 8-bit instruction  */

+#define HAL_OSPI_INSTRUCTION_16_BITS         ((uint32_t)OCTOSPI_CCR_ISIZE_0)                                 /*!< 16-bit instruction */

+#define HAL_OSPI_INSTRUCTION_24_BITS         ((uint32_t)OCTOSPI_CCR_ISIZE_1)                                 /*!< 24-bit instruction */

+#define HAL_OSPI_INSTRUCTION_32_BITS         ((uint32_t)OCTOSPI_CCR_ISIZE)                                   /*!< 32-bit instruction */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_InstructionDtrMode OSPI Instruction DTR Mode

+  * @{

+  */

+#define HAL_OSPI_INSTRUCTION_DTR_DISABLE     ((uint32_t)0x00000000U)                                         /*!< DTR mode disabled for instruction phase */

+#define HAL_OSPI_INSTRUCTION_DTR_ENABLE      ((uint32_t)OCTOSPI_CCR_IDTR)                                    /*!< DTR mode enabled for instruction phase  */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_AddressMode OSPI Address Mode

+  * @{

+  */

+#define HAL_OSPI_ADDRESS_NONE                ((uint32_t)0x00000000U)                                         /*!< No address               */

+#define HAL_OSPI_ADDRESS_1_LINE              ((uint32_t)OCTOSPI_CCR_ADMODE_0)                                /*!< Address on a single line */

+#define HAL_OSPI_ADDRESS_2_LINES             ((uint32_t)OCTOSPI_CCR_ADMODE_1)                                /*!< Address on two lines     */

+#define HAL_OSPI_ADDRESS_4_LINES             ((uint32_t)(OCTOSPI_CCR_ADMODE_0 | OCTOSPI_CCR_ADMODE_1))       /*!< Address on four lines    */

+#define HAL_OSPI_ADDRESS_8_LINES             ((uint32_t)OCTOSPI_CCR_ADMODE_2)                                /*!< Address on eight lines   */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_AddressSize OSPI Address Size

+  * @{

+  */

+#define HAL_OSPI_ADDRESS_8_BITS              ((uint32_t)0x00000000U)                                         /*!< 8-bit address  */

+#define HAL_OSPI_ADDRESS_16_BITS             ((uint32_t)OCTOSPI_CCR_ADSIZE_0)                                /*!< 16-bit address */

+#define HAL_OSPI_ADDRESS_24_BITS             ((uint32_t)OCTOSPI_CCR_ADSIZE_1)                                /*!< 24-bit address */

+#define HAL_OSPI_ADDRESS_32_BITS             ((uint32_t)OCTOSPI_CCR_ADSIZE)                                  /*!< 32-bit address */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_AddressDtrMode OSPI Address DTR Mode

+  * @{

+  */

+#define HAL_OSPI_ADDRESS_DTR_DISABLE         ((uint32_t)0x00000000U)                                         /*!< DTR mode disabled for address phase */

+#define HAL_OSPI_ADDRESS_DTR_ENABLE          ((uint32_t)OCTOSPI_CCR_ADDTR)                                   /*!< DTR mode enabled for address phase  */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_AlternateBytesMode OSPI Alternate Bytes Mode

+  * @{

+  */

+#define HAL_OSPI_ALTERNATE_BYTES_NONE        ((uint32_t)0x00000000U)                                         /*!< No alternate bytes               */

+#define HAL_OSPI_ALTERNATE_BYTES_1_LINE      ((uint32_t)OCTOSPI_CCR_ABMODE_0)                                /*!< Alternate bytes on a single line */

+#define HAL_OSPI_ALTERNATE_BYTES_2_LINES     ((uint32_t)OCTOSPI_CCR_ABMODE_1)                                /*!< Alternate bytes on two lines     */

+#define HAL_OSPI_ALTERNATE_BYTES_4_LINES     ((uint32_t)(OCTOSPI_CCR_ABMODE_0 | OCTOSPI_CCR_ABMODE_1))       /*!< Alternate bytes on four lines    */

+#define HAL_OSPI_ALTERNATE_BYTES_8_LINES     ((uint32_t)OCTOSPI_CCR_ABMODE_2)                                /*!< Alternate bytes on eight lines   */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_AlternateBytesSize OSPI Alternate Bytes Size

+  * @{

+  */

+#define HAL_OSPI_ALTERNATE_BYTES_8_BITS      ((uint32_t)0x00000000U)                                         /*!< 8-bit alternate bytes  */

+#define HAL_OSPI_ALTERNATE_BYTES_16_BITS     ((uint32_t)OCTOSPI_CCR_ABSIZE_0)                                /*!< 16-bit alternate bytes */

+#define HAL_OSPI_ALTERNATE_BYTES_24_BITS     ((uint32_t)OCTOSPI_CCR_ABSIZE_1)                                /*!< 24-bit alternate bytes */

+#define HAL_OSPI_ALTERNATE_BYTES_32_BITS     ((uint32_t)OCTOSPI_CCR_ABSIZE)                                  /*!< 32-bit alternate bytes */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_AlternateBytesDtrMode OSPI Alternate Bytes DTR Mode

+  * @{

+  */

+#define HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE ((uint32_t)0x00000000U)                                         /*!< DTR mode disabled for alternate bytes phase */

+#define HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE  ((uint32_t)OCTOSPI_CCR_ABDTR)                                   /*!< DTR mode enabled for alternate bytes phase  */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_DataMode OSPI Data Mode

+  * @{

+  */

+#define HAL_OSPI_DATA_NONE                   ((uint32_t)0x00000000U)                                         /*!< No data               */

+#define HAL_OSPI_DATA_1_LINE                 ((uint32_t)OCTOSPI_CCR_DMODE_0)                                 /*!< Data on a single line */

+#define HAL_OSPI_DATA_2_LINES                ((uint32_t)OCTOSPI_CCR_DMODE_1)                                 /*!< Data on two lines     */

+#define HAL_OSPI_DATA_4_LINES                ((uint32_t)(OCTOSPI_CCR_DMODE_0 | OCTOSPI_CCR_DMODE_1))         /*!< Data on four lines    */

+#define HAL_OSPI_DATA_8_LINES                ((uint32_t)OCTOSPI_CCR_DMODE_2)                                 /*!< Data on eight lines   */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_DataDtrMode OSPI Data DTR Mode

+  * @{

+  */

+#define HAL_OSPI_DATA_DTR_DISABLE            ((uint32_t)0x00000000U)                                         /*!< DTR mode disabled for data phase */

+#define HAL_OSPI_DATA_DTR_ENABLE             ((uint32_t)OCTOSPI_CCR_DDTR)                                    /*!< DTR mode enabled for data phase  */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_DQSMode OSPI DQS Mode

+  * @{

+  */

+#define HAL_OSPI_DQS_DISABLE                 ((uint32_t)0x00000000U)                                         /*!< DQS disabled */

+#define HAL_OSPI_DQS_ENABLE                  ((uint32_t)OCTOSPI_CCR_DQSE)                                    /*!< DQS enabled  */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_SIOOMode OSPI SIOO Mode

+  * @{

+  */

+#define HAL_OSPI_SIOO_INST_EVERY_CMD         ((uint32_t)0x00000000U)                                         /*!< Send instruction on every transaction       */

+#define HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD    ((uint32_t)OCTOSPI_CCR_SIOO)                                    /*!< Send instruction only for the first command */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_WriteZeroLatency OSPI Hyperbus Write Zero Latency Activation

+  * @{

+  */

+#define HAL_OSPI_LATENCY_ON_WRITE            ((uint32_t)0x00000000U)                                         /*!< Latency on write accesses    */

+#define HAL_OSPI_NO_LATENCY_ON_WRITE         ((uint32_t)OCTOSPI_HLCR_WZL)                                    /*!< No latency on write accesses */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_LatencyMode OSPI Hyperbus Latency Mode

+  * @{

+  */

+#define HAL_OSPI_VARIABLE_LATENCY            ((uint32_t)0x00000000U)                                         /*!< Variable initial latency */

+#define HAL_OSPI_FIXED_LATENCY               ((uint32_t)OCTOSPI_HLCR_LM)                                     /*!< Fixed latency            */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_AddressSpace OSPI Hyperbus Address Space

+  * @{

+  */

+#define HAL_OSPI_MEMORY_ADDRESS_SPACE        ((uint32_t)0x00000000U)                                         /*!< HyperBus memory mode   */

+#define HAL_OSPI_REGISTER_ADDRESS_SPACE      ((uint32_t)OCTOSPI_DCR1_MTYP_0)                                 /*!< HyperBus register mode */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_MatchMode OSPI Match Mode

+  * @{

+  */

+#define HAL_OSPI_MATCH_MODE_AND              ((uint32_t)0x00000000U)                                         /*!< AND match mode between unmasked bits */

+#define HAL_OSPI_MATCH_MODE_OR               ((uint32_t)OCTOSPI_CR_PMM)                                      /*!< OR match mode between unmasked bits  */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_AutomaticStop OSPI Automatic Stop

+  * @{

+  */

+#define HAL_OSPI_AUTOMATIC_STOP_DISABLE      ((uint32_t)0x00000000U)                                         /*!< AutoPolling stops only with abort or OSPI disabling */

+#define HAL_OSPI_AUTOMATIC_STOP_ENABLE       ((uint32_t)OCTOSPI_CR_APMS)                                     /*!< AutoPolling stops as soon as there is a match       */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_TimeOutActivation OSPI Timeout Activation

+  * @{

+  */

+#define HAL_OSPI_TIMEOUT_COUNTER_DISABLE     ((uint32_t)0x00000000U)                                         /*!< Timeout counter disabled, nCS remains active               */

+#define HAL_OSPI_TIMEOUT_COUNTER_ENABLE      ((uint32_t)OCTOSPI_CR_TCEN)                                     /*!< Timeout counter enabled, nCS released when timeout expires */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_Flags OSPI Flags

+  * @{

+  */

+#define HAL_OSPI_FLAG_BUSY                   OCTOSPI_SR_BUSY                                                 /*!< Busy flag: operation is ongoing                                                                          */

+#define HAL_OSPI_FLAG_TO                     OCTOSPI_SR_TOF                                                  /*!< Timeout flag: timeout occurs in memory-mapped mode                                                       */

+#define HAL_OSPI_FLAG_SM                     OCTOSPI_SR_SMF                                                  /*!< Status match flag: received data matches in autopolling mode                                             */

+#define HAL_OSPI_FLAG_FT                     OCTOSPI_SR_FTF                                                  /*!< Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete              */

+#define HAL_OSPI_FLAG_TC                     OCTOSPI_SR_TCF                                                  /*!< Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted */

+#define HAL_OSPI_FLAG_TE                     OCTOSPI_SR_TEF                                                  /*!< Transfer error flag: invalid address is being accessed                                                   */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_Interrupts OSPI Interrupts

+  * @{

+  */

+#define HAL_OSPI_IT_TO                       OCTOSPI_CR_TOIE                                                 /*!< Interrupt on the timeout flag           */

+#define HAL_OSPI_IT_SM                       OCTOSPI_CR_SMIE                                                 /*!< Interrupt on the status match flag      */

+#define HAL_OSPI_IT_FT                       OCTOSPI_CR_FTIE                                                 /*!< Interrupt on the fifo threshold flag    */

+#define HAL_OSPI_IT_TC                       OCTOSPI_CR_TCIE                                                 /*!< Interrupt on the transfer complete flag */

+#define HAL_OSPI_IT_TE                       OCTOSPI_CR_TEIE                                                 /*!< Interrupt on the transfer error flag    */

+/**

+  * @}

+  */

+

+/** @defgroup OSPI_Timeout_definition OSPI Timeout definition

+  * @{

+  */

+#define HAL_OSPI_TIMEOUT_DEFAULT_VALUE       ((uint32_t)5000U)                                               /* 5 s */

+/**

+  * @}

+  */

+

+/** @defgroup OSPIM_IOPort OSPI IO Manager IO Port

+  * @{

+  */

+#define HAL_OSPIM_IOPORT_1_LOW             ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x1U))                          /*!< Port 1 - IO[3:0] */

+#define HAL_OSPIM_IOPORT_1_HIGH            ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1U))                          /*!< Port 1 - IO[7:4] */

+#define HAL_OSPIM_IOPORT_2_LOW             ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2U))                          /*!< Port 2 - IO[3:0] */

+#define HAL_OSPIM_IOPORT_2_HIGH            ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x2U))                          /*!< Port 2 - IO[7:4] */

+#define HAL_OSPIM_IOPORT_3_LOW             ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x3U))                          /*!< Port 3 - IO[3:0] */

+#define HAL_OSPIM_IOPORT_3_HIGH            ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x3U))                          /*!< Port 3 - IO[7:4] */

+#define HAL_OSPIM_IOPORT_4_LOW             ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x4U))                          /*!< Port 4 - IO[3:0] */

+#define HAL_OSPIM_IOPORT_4_HIGH            ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x4U))                          /*!< Port 4 - IO[7:4] */

+#define HAL_OSPIM_IOPORT_5_LOW             ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x5U))                          /*!< Port 5 - IO[3:0] */

+#define HAL_OSPIM_IOPORT_5_HIGH            ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x5U))                          /*!< Port 5 - IO[7:4] */

+#define HAL_OSPIM_IOPORT_6_LOW             ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x6U))                          /*!< Port 6 - IO[3:0] */

+#define HAL_OSPIM_IOPORT_6_HIGH            ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x6U))                          /*!< Port 6 - IO[7:4] */

+#define HAL_OSPIM_IOPORT_7_LOW             ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x7U))                          /*!< Port 7 - IO[3:0] */

+#define HAL_OSPIM_IOPORT_7_HIGH            ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x7U))                          /*!< Port 7 - IO[7:4] */

+#define HAL_OSPIM_IOPORT_8_LOW             ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x8U))                          /*!< Port 8 - IO[3:0] */

+#define HAL_OSPIM_IOPORT_8_HIGH            ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x8U))                          /*!< Port 8 - IO[7:4] */

+/**

+  * @}

+  */

+/**

+  * @}

+  */

+

+/* Exported macros -----------------------------------------------------------*/

+/** @defgroup OSPI_Exported_Macros OSPI Exported Macros

+  * @{

+  */

+/** @brief Reset OSPI handle state.

+  * @param  __HANDLE__ specifies the OSPI Handle.

+  * @retval None

+  */

+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)

+#define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__)           do {                                              \

+                                                                  (__HANDLE__)->State = HAL_OSPI_STATE_RESET; \

+                                                                  (__HANDLE__)->MspInitCallback = NULL;       \

+                                                                  (__HANDLE__)->MspDeInitCallback = NULL;     \

+                                                               } while(0)

+#else

+#define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_OSPI_STATE_RESET)

+#endif

+

+/** @brief  Enable the OSPI peripheral.

+  * @param  __HANDLE__ specifies the OSPI Handle.

+  * @retval None

+  */

+#define __HAL_OSPI_ENABLE(__HANDLE__)                       SET_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN)

+

+/** @brief  Disable the OSPI peripheral.

+  * @param  __HANDLE__ specifies the OSPI Handle.

+  * @retval None

+  */

+#define __HAL_OSPI_DISABLE(__HANDLE__)                      CLEAR_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN)

+

+/** @brief  Enable the specified OSPI interrupt.

+  * @param  __HANDLE__ specifies the OSPI Handle.

+  * @param  __INTERRUPT__ specifies the OSPI interrupt source to enable.

+  *          This parameter can be one of the following values:

+  *            @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt

+  *            @arg HAL_OSPI_IT_SM: OSPI Status match interrupt

+  *            @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt

+  *            @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt

+  *            @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt

+  * @retval None

+  */

+#define __HAL_OSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)     SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))

+

+

+/** @brief  Disable the specified OSPI interrupt.

+  * @param  __HANDLE__ specifies the OSPI Handle.

+  * @param  __INTERRUPT__ specifies the OSPI interrupt source to disable.

+  *          This parameter can be one of the following values:

+  *            @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt

+  *            @arg HAL_OSPI_IT_SM: OSPI Status match interrupt

+  *            @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt

+  *            @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt

+  *            @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt

+  * @retval None

+  */

+#define __HAL_OSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)    CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))

+

+/** @brief  Check whether the specified OSPI interrupt source is enabled or not.

+  * @param  __HANDLE__ specifies the OSPI Handle.

+  * @param  __INTERRUPT__ specifies the OSPI interrupt source to check.

+  *          This parameter can be one of the following values:

+  *            @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt

+  *            @arg HAL_OSPI_IT_SM: OSPI Status match interrupt

+  *            @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt

+  *            @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt

+  *            @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt

+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).

+  */

+#define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))

+

+/**

+  * @brief  Check whether the selected OSPI flag is set or not.

+  * @param  __HANDLE__ specifies the OSPI Handle.

+  * @param  __FLAG__ specifies the OSPI flag to check.

+  *          This parameter can be one of the following values:

+  *            @arg HAL_OSPI_FLAG_BUSY: OSPI Busy flag

+  *            @arg HAL_OSPI_FLAG_TO:   OSPI Timeout flag

+  *            @arg HAL_OSPI_FLAG_SM:   OSPI Status match flag

+  *            @arg HAL_OSPI_FLAG_FT:   OSPI FIFO threshold flag

+  *            @arg HAL_OSPI_FLAG_TC:   OSPI Transfer complete flag

+  *            @arg HAL_OSPI_FLAG_TE:   OSPI Transfer error flag

+  * @retval None

+  */

+#define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__)           ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)

+

+/** @brief  Clears the specified OSPI's flag status.

+  * @param  __HANDLE__ specifies the OSPI Handle.

+  * @param  __FLAG__ specifies the OSPI clear register flag that needs to be set

+  *          This parameter can be one of the following values:

+  *            @arg HAL_OSPI_FLAG_TO:   OSPI Timeout flag

+  *            @arg HAL_OSPI_FLAG_SM:   OSPI Status match flag

+  *            @arg HAL_OSPI_FLAG_TC:   OSPI Transfer complete flag

+  *            @arg HAL_OSPI_FLAG_TE:   OSPI Transfer error flag

+  * @retval None

+  */

+#define __HAL_OSPI_CLEAR_FLAG(__HANDLE__, __FLAG__)         WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup OSPI_Exported_Functions

+  * @{

+  */

+

+/* Initialization/de-initialization functions  ********************************/

+/** @addtogroup OSPI_Exported_Functions_Group1

+  * @{

+  */

+HAL_StatusTypeDef     HAL_OSPI_Init                 (OSPI_HandleTypeDef *hospi);

+void                  HAL_OSPI_MspInit              (OSPI_HandleTypeDef *hospi);

+HAL_StatusTypeDef     HAL_OSPI_DeInit               (OSPI_HandleTypeDef *hospi);

+void                  HAL_OSPI_MspDeInit            (OSPI_HandleTypeDef *hospi);

+

+/**

+  * @}

+  */

+

+/* IO operation functions *****************************************************/

+/** @addtogroup OSPI_Exported_Functions_Group2

+  * @{

+  */

+/* OSPI IRQ handler function */

+void                  HAL_OSPI_IRQHandler           (OSPI_HandleTypeDef *hospi);

+

+/* OSPI command configuration functions */

+HAL_StatusTypeDef     HAL_OSPI_Command              (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout);

+HAL_StatusTypeDef     HAL_OSPI_Command_IT           (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd);

+HAL_StatusTypeDef     HAL_OSPI_HyperbusCfg          (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout);

+HAL_StatusTypeDef     HAL_OSPI_HyperbusCmd          (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout);

+

+/* OSPI indirect mode functions */

+HAL_StatusTypeDef     HAL_OSPI_Transmit             (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout);

+HAL_StatusTypeDef     HAL_OSPI_Receive              (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout);

+HAL_StatusTypeDef     HAL_OSPI_Transmit_IT          (OSPI_HandleTypeDef *hospi, uint8_t *pData);

+HAL_StatusTypeDef     HAL_OSPI_Receive_IT           (OSPI_HandleTypeDef *hospi, uint8_t *pData);

+HAL_StatusTypeDef     HAL_OSPI_Transmit_DMA         (OSPI_HandleTypeDef *hospi, uint8_t *pData);

+HAL_StatusTypeDef     HAL_OSPI_Receive_DMA          (OSPI_HandleTypeDef *hospi, uint8_t *pData);

+

+/* OSPI status flag polling mode functions */

+HAL_StatusTypeDef     HAL_OSPI_AutoPolling          (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);

+HAL_StatusTypeDef     HAL_OSPI_AutoPolling_IT       (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg);

+

+/* OSPI memory-mapped mode functions */

+HAL_StatusTypeDef     HAL_OSPI_MemoryMapped         (OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg);

+

+/* Callback functions in non-blocking modes ***********************************/

+void                  HAL_OSPI_ErrorCallback        (OSPI_HandleTypeDef *hospi);

+void                  HAL_OSPI_AbortCpltCallback    (OSPI_HandleTypeDef *hospi);

+void                  HAL_OSPI_FifoThresholdCallback(OSPI_HandleTypeDef *hospi);

+

+/* OSPI indirect mode functions */

+void                  HAL_OSPI_CmdCpltCallback      (OSPI_HandleTypeDef *hospi);

+void                  HAL_OSPI_RxCpltCallback       (OSPI_HandleTypeDef *hospi);

+void                  HAL_OSPI_TxCpltCallback       (OSPI_HandleTypeDef *hospi);

+void                  HAL_OSPI_RxHalfCpltCallback   (OSPI_HandleTypeDef *hospi);

+void                  HAL_OSPI_TxHalfCpltCallback   (OSPI_HandleTypeDef *hospi);

+

+/* OSPI status flag polling mode functions */

+void                  HAL_OSPI_StatusMatchCallback  (OSPI_HandleTypeDef *hospi);

+

+/* OSPI memory-mapped mode functions */

+void                  HAL_OSPI_TimeOutCallback      (OSPI_HandleTypeDef *hospi);

+

+#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)

+/* OSPI callback registering/unregistering */

+HAL_StatusTypeDef     HAL_OSPI_RegisterCallback     (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, pOSPI_CallbackTypeDef pCallback);

+HAL_StatusTypeDef     HAL_OSPI_UnRegisterCallback   (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID);

+#endif

+/**

+  * @}

+  */

+

+/* Peripheral Control and State functions  ************************************/

+/** @addtogroup OSPI_Exported_Functions_Group3

+  * @{

+  */

+HAL_StatusTypeDef     HAL_OSPI_Abort                (OSPI_HandleTypeDef *hospi);

+HAL_StatusTypeDef     HAL_OSPI_Abort_IT             (OSPI_HandleTypeDef *hospi);

+HAL_StatusTypeDef     HAL_OSPI_SetFifoThreshold     (OSPI_HandleTypeDef *hospi, uint32_t Threshold);

+uint32_t              HAL_OSPI_GetFifoThreshold     (OSPI_HandleTypeDef *hospi);

+HAL_StatusTypeDef     HAL_OSPI_SetTimeout           (OSPI_HandleTypeDef *hospi, uint32_t Timeout);

+uint32_t              HAL_OSPI_GetError             (OSPI_HandleTypeDef *hospi);

+uint32_t              HAL_OSPI_GetState             (OSPI_HandleTypeDef *hospi);

+

+/**

+  * @}

+  */

+

+/* OSPI IO Manager configuration function  ************************************/

+/** @addtogroup OSPI_Exported_Functions_Group4

+  * @{

+  */

+HAL_StatusTypeDef     HAL_OSPIM_Config              (OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+/* End of exported functions -------------------------------------------------*/

+

+/* Private macros ------------------------------------------------------------*/

+/**

+  @cond 0

+  */

+#define IS_OSPI_FIFO_THRESHOLD(THRESHOLD)  (((THRESHOLD) >= 1U) && ((THRESHOLD) <= 32U))

+

+#define IS_OSPI_DUALQUAD_MODE(MODE)        (((MODE) == HAL_OSPI_DUALQUAD_DISABLE) || \

+                                            ((MODE) == HAL_OSPI_DUALQUAD_ENABLE))

+

+#define IS_OSPI_MEMORY_TYPE(TYPE)          (((TYPE) == HAL_OSPI_MEMTYPE_MICRON)       || \

+                                            ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX)     || \

+                                            ((TYPE) == HAL_OSPI_MEMTYPE_APMEMORY)     || \

+                                            ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX_RAM) || \

+                                            ((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS))

+

+#define IS_OSPI_DEVICE_SIZE(SIZE)          (((SIZE) >= 1U) && ((SIZE) <= 32U))

+

+#define IS_OSPI_CS_HIGH_TIME(TIME)         (((TIME) >= 1U) && ((TIME) <= 8U))

+

+#define IS_OSPI_FREE_RUN_CLK(CLK)          (((CLK) == HAL_OSPI_FREERUNCLK_DISABLE) || \

+                                            ((CLK) == HAL_OSPI_FREERUNCLK_ENABLE))

+

+#define IS_OSPI_CLOCK_MODE(MODE)           (((MODE) == HAL_OSPI_CLOCK_MODE_0) || \

+                                            ((MODE) == HAL_OSPI_CLOCK_MODE_3))

+

+#define IS_OSPI_WRAP_SIZE(SIZE)            (((SIZE) == HAL_OSPI_WRAP_NOT_SUPPORTED) || \

+                                            ((SIZE) == HAL_OSPI_WRAP_16_BYTES)      || \

+                                            ((SIZE) == HAL_OSPI_WRAP_32_BYTES)      || \

+                                            ((SIZE) == HAL_OSPI_WRAP_64_BYTES)      || \

+                                            ((SIZE) == HAL_OSPI_WRAP_128_BYTES))

+

+#define IS_OSPI_CLK_PRESCALER(PRESCALER)   (((PRESCALER) >= 1U) && ((PRESCALER) <= 256U))

+

+#define IS_OSPI_SAMPLE_SHIFTING(CYCLE)     (((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_NONE)      || \

+                                            ((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE))

+

+#define IS_OSPI_DHQC(CYCLE)                (((CYCLE) == HAL_OSPI_DHQC_DISABLE) || \

+                                            ((CYCLE) == HAL_OSPI_DHQC_ENABLE))

+

+#define IS_OSPI_OPERATION_TYPE(TYPE)       (((TYPE) == HAL_OSPI_OPTYPE_COMMON_CFG) || \

+                                            ((TYPE) == HAL_OSPI_OPTYPE_READ_CFG)   || \

+                                            ((TYPE) == HAL_OSPI_OPTYPE_WRITE_CFG)  || \

+                                            ((TYPE) == HAL_OSPI_OPTYPE_WRAP_CFG))

+

+#define IS_OSPI_FLASH_ID(FLASHID)          (((FLASHID) == HAL_OSPI_FLASH_ID_1) || \

+                                            ((FLASHID) == HAL_OSPI_FLASH_ID_2))

+

+#define IS_OSPI_INSTRUCTION_MODE(MODE)     (((MODE) == HAL_OSPI_INSTRUCTION_NONE)    || \

+                                            ((MODE) == HAL_OSPI_INSTRUCTION_1_LINE)  || \

+                                            ((MODE) == HAL_OSPI_INSTRUCTION_2_LINES) || \

+                                            ((MODE) == HAL_OSPI_INSTRUCTION_4_LINES) || \

+                                            ((MODE) == HAL_OSPI_INSTRUCTION_8_LINES))

+

+#define IS_OSPI_INSTRUCTION_SIZE(SIZE)     (((SIZE) == HAL_OSPI_INSTRUCTION_8_BITS)  || \

+                                            ((SIZE) == HAL_OSPI_INSTRUCTION_16_BITS) || \

+                                            ((SIZE) == HAL_OSPI_INSTRUCTION_24_BITS) || \

+                                            ((SIZE) == HAL_OSPI_INSTRUCTION_32_BITS))

+

+#define IS_OSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_DTR_DISABLE) || \

+                                            ((MODE) == HAL_OSPI_INSTRUCTION_DTR_ENABLE))

+

+#define IS_OSPI_ADDRESS_MODE(MODE)         (((MODE) == HAL_OSPI_ADDRESS_NONE)    || \

+                                            ((MODE) == HAL_OSPI_ADDRESS_1_LINE)  || \

+                                            ((MODE) == HAL_OSPI_ADDRESS_2_LINES) || \

+                                            ((MODE) == HAL_OSPI_ADDRESS_4_LINES) || \

+                                            ((MODE) == HAL_OSPI_ADDRESS_8_LINES))

+

+#define IS_OSPI_ADDRESS_SIZE(SIZE)         (((SIZE) == HAL_OSPI_ADDRESS_8_BITS)  || \

+                                            ((SIZE) == HAL_OSPI_ADDRESS_16_BITS) || \

+                                            ((SIZE) == HAL_OSPI_ADDRESS_24_BITS) || \

+                                            ((SIZE) == HAL_OSPI_ADDRESS_32_BITS))

+

+#define IS_OSPI_ADDRESS_DTR_MODE(MODE)     (((MODE) == HAL_OSPI_ADDRESS_DTR_DISABLE) || \

+                                            ((MODE) == HAL_OSPI_ADDRESS_DTR_ENABLE))

+

+#define IS_OSPI_ALT_BYTES_MODE(MODE)       (((MODE) == HAL_OSPI_ALTERNATE_BYTES_NONE)    || \

+                                            ((MODE) == HAL_OSPI_ALTERNATE_BYTES_1_LINE)  || \

+                                            ((MODE) == HAL_OSPI_ALTERNATE_BYTES_2_LINES) || \

+                                            ((MODE) == HAL_OSPI_ALTERNATE_BYTES_4_LINES) || \

+                                            ((MODE) == HAL_OSPI_ALTERNATE_BYTES_8_LINES))

+

+#define IS_OSPI_ALT_BYTES_SIZE(SIZE)       (((SIZE) == HAL_OSPI_ALTERNATE_BYTES_8_BITS)  || \

+                                            ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_16_BITS) || \

+                                            ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_24_BITS) || \

+                                            ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_32_BITS))

+

+#define IS_OSPI_ALT_BYTES_DTR_MODE(MODE)   (((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE) || \

+                                            ((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE))

+

+#define IS_OSPI_DATA_MODE(MODE)            (((MODE) == HAL_OSPI_DATA_NONE)    || \

+                                            ((MODE) == HAL_OSPI_DATA_1_LINE)  || \

+                                            ((MODE) == HAL_OSPI_DATA_2_LINES) || \

+                                            ((MODE) == HAL_OSPI_DATA_4_LINES) || \

+                                            ((MODE) == HAL_OSPI_DATA_8_LINES))

+

+#define IS_OSPI_NUMBER_DATA(NUMBER)        ((NUMBER) >= 1U)

+

+#define IS_OSPI_DATA_DTR_MODE(MODE)        (((MODE) == HAL_OSPI_DATA_DTR_DISABLE) || \

+                                            ((MODE) == HAL_OSPI_DATA_DTR_ENABLE))

+

+#define IS_OSPI_DUMMY_CYCLES(NUMBER)       ((NUMBER) <= 31U)

+

+#define IS_OSPI_DQS_MODE(MODE)             (((MODE) == HAL_OSPI_DQS_DISABLE) || \

+                                            ((MODE) == HAL_OSPI_DQS_ENABLE))

+

+#define IS_OSPI_SIOO_MODE(MODE)            (((MODE) == HAL_OSPI_SIOO_INST_EVERY_CMD) || \

+                                            ((MODE) == HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD))

+

+#define IS_OSPI_RW_RECOVERY_TIME(NUMBER)   ((NUMBER) <= 255U)

+

+#define IS_OSPI_ACCESS_TIME(NUMBER)        ((NUMBER) <= 255U)

+

+#define IS_OSPI_WRITE_ZERO_LATENCY(MODE)   (((MODE) == HAL_OSPI_LATENCY_ON_WRITE) || \

+                                            ((MODE) == HAL_OSPI_NO_LATENCY_ON_WRITE))

+

+#define IS_OSPI_LATENCY_MODE(MODE)         (((MODE) == HAL_OSPI_VARIABLE_LATENCY) || \

+                                            ((MODE) == HAL_OSPI_FIXED_LATENCY))

+

+#define IS_OSPI_ADDRESS_SPACE(SPACE)       (((SPACE) == HAL_OSPI_MEMORY_ADDRESS_SPACE) || \

+                                            ((SPACE) == HAL_OSPI_REGISTER_ADDRESS_SPACE))

+

+#define IS_OSPI_MATCH_MODE(MODE)           (((MODE) == HAL_OSPI_MATCH_MODE_AND) || \

+                                            ((MODE) == HAL_OSPI_MATCH_MODE_OR))

+

+#define IS_OSPI_AUTOMATIC_STOP(MODE)       (((MODE) == HAL_OSPI_AUTOMATIC_STOP_ENABLE) || \

+                                            ((MODE) == HAL_OSPI_AUTOMATIC_STOP_DISABLE))

+

+#define IS_OSPI_INTERVAL(INTERVAL)         ((INTERVAL) <= 0xFFFFU)

+

+#define IS_OSPI_STATUS_BYTES_SIZE(SIZE)    (((SIZE) >= 1U) && ((SIZE) <= 4U))

+

+#define IS_OSPI_TIMEOUT_ACTIVATION(MODE)   (((MODE) == HAL_OSPI_TIMEOUT_COUNTER_DISABLE) || \

+                                            ((MODE) == HAL_OSPI_TIMEOUT_COUNTER_ENABLE))

+

+#define IS_OSPI_TIMEOUT_PERIOD(PERIOD)     ((PERIOD) <= 0xFFFFU)

+

+#define IS_OSPI_CS_BOUNDARY(BOUNDARY)      ((BOUNDARY) <= 31U)

+

+#define IS_OSPI_CKCSHT(CLK_NB)             ((CLK_NB) <= 7U)

+

+#define IS_OSPI_DLYBYP(MODE)               (((MODE) == HAL_OSPI_DELAY_BLOCK_USED) || \

+                                            ((MODE) == HAL_OSPI_DELAY_BLOCK_BYPASSED))

+

+#define IS_OSPI_MAXTRAN(NB_BYTES)          ((NB_BYTES) <= 255U)

+

+#define IS_OSPIM_PORT(NUMBER)              (((NUMBER) >= 1U) && ((NUMBER) <= 8U))

+

+#define IS_OSPIM_IO_PORT(PORT)             (((PORT) == HAL_OSPIM_IOPORT_1_LOW)  || \

+                                            ((PORT) == HAL_OSPIM_IOPORT_1_HIGH) || \

+                                            ((PORT) == HAL_OSPIM_IOPORT_2_LOW)  || \

+                                            ((PORT) == HAL_OSPIM_IOPORT_2_HIGH) || \

+                                            ((PORT) == HAL_OSPIM_IOPORT_3_LOW)  || \

+                                            ((PORT) == HAL_OSPIM_IOPORT_3_HIGH) || \

+                                            ((PORT) == HAL_OSPIM_IOPORT_4_LOW)  || \

+                                            ((PORT) == HAL_OSPIM_IOPORT_4_HIGH) || \

+                                            ((PORT) == HAL_OSPIM_IOPORT_5_LOW)  || \

+                                            ((PORT) == HAL_OSPIM_IOPORT_5_HIGH) || \

+                                            ((PORT) == HAL_OSPIM_IOPORT_6_LOW)  || \

+                                            ((PORT) == HAL_OSPIM_IOPORT_6_HIGH) || \

+                                            ((PORT) == HAL_OSPIM_IOPORT_7_LOW)  || \

+                                            ((PORT) == HAL_OSPIM_IOPORT_7_HIGH) || \

+                                            ((PORT) == HAL_OSPIM_IOPORT_8_LOW)  || \

+                                            ((PORT) == HAL_OSPIM_IOPORT_8_HIGH))

+

+#define IS_OSPIM_REQ2ACKTIME(TIME)          (((TIME) >= 1U) && ((TIME) <= 256U))

+/**

+  @endcond

+  */

+

+/* End of private macros -----------------------------------------------------*/

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_OSPI_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_otfdec.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_otfdec.h
new file mode 100644
index 0000000000..70a9c15d40
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_otfdec.h
@@ -0,0 +1,444 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_otfdec.h

+  * @author  MCD Application Team

+  * @brief   Header file of OTFDEC HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2018 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef __STM32H7xx_HAL_OTFDEC_H

+#define __STM32H7xx_HAL_OTFDEC_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+#if defined(OTFDEC1)

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup OTFDEC

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+

+/** @defgroup OTFDEC_Exported_Types OTFDEC Exported Types

+  * @{

+  */

+

+/** @defgroup OTFDEC_Exported_Types_Group1 OTFDEC region configuration definitions

+  * @{

+  */

+

+/**

+  * @brief OTFDEC region configuration structure definition

+  */

+typedef struct

+{

+  uint32_t          Nonce[2];        /*!< OTFDEC region nonce */

+

+  uint32_t          StartAddress;    /*!< OTFDEC region start address */

+

+  uint32_t          EndAddress;      /*!< OTFDEC region end address */

+

+  uint16_t          Version;         /*!< OTFDEC region firmware version */

+

+}OTFDEC_RegionConfigTypeDef;

+

+/**

+  * @}

+  */

+

+/** @defgroup OTFDEC_Exported_Types_Group2 OTFDEC Peripheral handle definitions

+  * @{

+  */

+

+/**

+  * @brief OTFDEC states structure definition

+  */

+typedef enum

+{

+  HAL_OTFDEC_STATE_RESET             = 0x00U,  /*!< OTFDEC not yet initialized or disabled */

+  HAL_OTFDEC_STATE_READY             = 0x01U,  /*!< OTFDEC initialized and ready for use   */

+  HAL_OTFDEC_STATE_BUSY              = 0x02U,  /*!< OTFDEC internal processing is ongoing  */

+}HAL_OTFDEC_StateTypeDef;

+

+/**

+  * @brief OTFDEC handle structure definition

+  */

+#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)

+typedef struct __OTFDEC_HandleTypeDef

+#else

+typedef struct

+#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */

+{

+  OTFDEC_TypeDef             *Instance;  /*!< OTFDEC registers base address */

+

+  HAL_OTFDEC_StateTypeDef    State;      /*!< OTFDEC state */

+

+  HAL_LockTypeDef            Lock;       /*!< OTFDEC locking object */

+

+  __IO uint32_t              ErrorCode;  /*!< OTFDEC error code */

+

+#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)

+  void (* ErrorCallback)(struct __OTFDEC_HandleTypeDef *hotfdec);     /*!< OTFDEC error callback */

+

+  void (* MspInitCallback)(struct __OTFDEC_HandleTypeDef *hotfdec);   /*!< OTFDEC Msp Init callback */

+

+  void (* MspDeInitCallback)(struct __OTFDEC_HandleTypeDef *hotfdec); /*!< OTFDEC Msp DeInit callback */

+#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */

+

+}OTFDEC_HandleTypeDef;

+

+#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  HAL OTFDEC Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_OTFDEC_ERROR_CB_ID       = 0x00U,  /*!< OTFDEC error callback ID      */

+  HAL_OTFDEC_MSPINIT_CB_ID     = 0x01U,  /*!< OTFDEC Msp DeInit callback ID */

+  HAL_OTFDEC_MSPDEINIT_CB_ID   = 0x02U   /*!< OTFDEC Msp DeInit callback ID */

+} HAL_OTFDEC_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL OTFDEC Callback pointer definition

+  */

+typedef  void (*pOTFDEC_CallbackTypeDef)(OTFDEC_HandleTypeDef *hotfdec); /*!< pointer to a OTFDEC callback function */

+

+#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup OTFDEC_Exported_Constants OTFDEC Exported Constants

+  * @{

+  */

+

+/** @defgroup OTFDEC_Interrupts    OTFDEC Interrupts

+  * @{

+  */

+#define OTFDEC_SEC_ERROR_INT     (OTFDEC_IER_SEIE                                  )  /*!< OTFDEC security error interrupt                  */

+#define OTFDEC_EXE_ERROR_INT     (               OTFDEC_IER_XONEIE                 )  /*!< OTFDEC execution error interrupt                 */

+#define OTFDEC_KEY_ERROR_INT     (                                  OTFDEC_IER_KEIE)  /*!< OTFDEC key error interrupt                       */

+#define OTFDEC_SEC_EXE_ERROR_INT (OTFDEC_IER_SEIE|OTFDEC_IER_XONEIE                )  /*!< OTFDEC security and execution errors interrupts  */

+#define OTFDEC_SEC_KEY_ERROR_INT (OTFDEC_IER_SEIE|                  OTFDEC_IER_KEIE)  /*!< OTFDEC security and key errors interrupts        */

+#define OTFDEC_EXE_KEY_ERROR_INT (                OTFDEC_IER_XONEIE|OTFDEC_IER_KEIE)  /*!< OTFDEC execution and key errors interrupts       */

+#define OTFDEC_ALL_INT           (OTFDEC_IER_SEIE|OTFDEC_IER_XONEIE|OTFDEC_IER_KEIE)  /*!< OTFDEC all interrupts                            */

+/**

+  * @}

+  */

+

+/** @defgroup OTFDEC_Region_Enable   OTFDEC Region Enable

+  * @{

+  */

+#define OTFDEC_REG_CONFIGR_REG_DISABLE   0x00000000U                /*!< OTFDEC region encryption or on-the-fly decryption disable */

+#define OTFDEC_REG_CONFIGR_REG_ENABLE    OTFDEC_REG_CONFIGR_REG_EN  /*!< OTFDEC region encryption or on-the-fly decryption enable  */

+/**

+  * @}

+  */

+

+/** @defgroup OTFDEC_Region_Configuration_Lock    OTFDEC Region Configuration Lock

+  * @{

+  */

+#define OTFDEC_REG_CONFIGR_LOCK_DISABLE   0x00000000U                     /*!< OTFDEC region configuration lock disable */

+#define OTFDEC_REG_CONFIGR_LOCK_ENABLE    OTFDEC_REG_CONFIGR_CONFIGLOCK   /*!< OTFDEC region configuration lock enable  */

+/**

+  * @}

+  */

+

+/** @defgroup OTFDEC_Region_Operating_Mode    OTFDEC Region Operating Mode

+  * @{

+  */

+#define OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY              0x00000000U                /*!< Only instruction accesses are decrypted                                   */

+#define OTFDEC_REG_MODE_DATA_ACCESSES_ONLY                     OTFDEC_REG_CONFIGR_MODE_0  /*!< Only data accesses are decrypted                                          */

+#define OTFDEC_REG_MODE_INSTRUCTION_OR_DATA_ACCESSES           OTFDEC_REG_CONFIGR_MODE_1  /*!< All read accesses are decrypted                                           */

+#define OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY_WITH_CIPHER  OTFDEC_REG_CONFIGR_MODE    /*!< Only instruction accesses are decrypted with proprietary cipher activated */

+/**

+  * @}

+  */

+

+/** @defgroup OTFDEC_Error_Definition   OTFDEC Error Definition

+  * @{

+  */

+#define  HAL_OTFDEC_ERROR_NONE             ((uint32_t)0x00000000U)    /*!< No error                         */

+#define  HAL_OTFDEC_SECURITY_ERROR         ((uint32_t)0x00000001U)    /*!< Security error                   */

+#define  HAL_OTFDEC_EXECUTE_ERROR          ((uint32_t)0x00000002U)    /*!< Execute-only Execute-Never error */

+#define  HAL_OTFDEC_KEY_ERROR              ((uint32_t)0x00000004U)    /*!< Key error                        */

+#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)

+#define HAL_OTFDEC_ERROR_INVALID_CALLBACK  ((uint32_t)0x00000008U)   /*!< Invalid Callback error            */

+#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/** @defgroup OTFDEC_Regions_Index   OTFDEC Regions Index

+  * @{

+  */

+#define  OTFDEC_REGION1            ((uint32_t)0x00000000U)    /*!< OTFDEC region 1 */

+#define  OTFDEC_REGION2            ((uint32_t)0x00000001U)    /*!< OTFDEC region 2 */

+#define  OTFDEC_REGION3            ((uint32_t)0x00000002U)    /*!< OTFDEC region 3 */

+#define  OTFDEC_REGION4            ((uint32_t)0x00000003U)    /*!< OTFDEC region 4 */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup OTFDEC_Exported_Macros OTFDEC Exported Macros

+  * @{

+  */

+

+/** @brief  Reset OTFDEC handle state.

+  * @param  __HANDLE__ pointer to an OTFDEC_HandleTypeDef structure that contains

+  *         the configuration information for OTFDEC module

+  * @retval None

+  */

+#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)

+#define __HAL_OTFDEC_RESET_HANDLE_STATE(__HANDLE__)                            \

+  do{                                                                          \

+    (__HANDLE__)->State = HAL_OTFDEC_STATE_RESET;                              \

+    (__HANDLE__)->MspInitCallback = NULL;                                      \

+    (__HANDLE__)->MspDeInitCallback = NULL;                                    \

+  } while(0)

+#else

+#define __HAL_OTFDEC_RESET_HANDLE_STATE(__HANDLE__)                            \

+  ((__HANDLE__)->State = HAL_OTFDEC_STATE_RESET)

+#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */

+

+/**

+  * @brief  Enable OTFDEC peripheral interrupts combination

+  * @param  __HANDLE__ pointer to an OTFDEC_HandleTypeDef structure that contains

+  *         the configuration information for OTFDEC module

+  * @param  __INTERRUPT__ mask on enabled interrupts

+  *          This parameter can be one of the following values:

+  *            @arg @ref OTFDEC_SEC_ERROR_INT        OTFDEC security error interrupt

+  *            @arg @ref OTFDEC_EXE_ERROR_INT        OTFDEC execution error interrupt

+  *            @arg @ref OTFDEC_KEY_ERROR_INT        OTFDEC key error interrupt

+  *            @arg @ref OTFDEC_SEC_EXE_ERROR_INT    OTFDEC security and execution errors interrupts

+  *            @arg @ref OTFDEC_SEC_KEY_ERROR_INT    OTFDEC security and key errors interrupts

+  *            @arg @ref OTFDEC_EXE_KEY_ERROR_INT    OTFDEC execution and key errors interrupts

+  *            @arg @ref OTFDEC_ALL_INT              OTFDEC all interrupts

+  * @retval None

+  */

+#define __HAL_OTFDEC_ENABLE_IT(__HANDLE__, __INTERRUPT__)  SET_BIT(((__HANDLE__)->Instance->IER), (__INTERRUPT__))

+

+/**

+  * @brief  Disable OTFDEC peripheral interrupts combination

+  * @param  __HANDLE__ pointer to an OTFDEC_HandleTypeDef structure that contains

+  *         the configuration information for OTFDEC module

+  * @param  __INTERRUPT__ mask on disabled interrupts

+  *          This parameter can be one of the following values:

+  *            @arg @ref OTFDEC_SEC_ERROR_INT        OTFDEC security error interrupt

+  *            @arg @ref OTFDEC_EXE_ERROR_INT        OTFDEC execution error interrupt

+  *            @arg @ref OTFDEC_KEY_ERROR_INT        OTFDEC key error interrupt

+  *            @arg @ref OTFDEC_SEC_EXE_ERROR_INT    OTFDEC security and execution errors interrupts

+  *            @arg @ref OTFDEC_SEC_KEY_ERROR_INT    OTFDEC security and key errors interrupts

+  *            @arg @ref OTFDEC_EXE_KEY_ERROR_INT    OTFDEC execution and key errors interrupts

+  *            @arg @ref OTFDEC_ALL_INT              OTFDEC all interrupts

+  * @retval None

+  */

+#define __HAL_OTFDEC_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT(((__HANDLE__)->Instance->IER), (__INTERRUPT__))

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup OTFDEC_Exported_Functions OTFDEC Exported Functions

+  * @{

+  */

+

+/** @addtogroup OTFDEC_Exported_Functions_Group1 Initialization and de-initialization functions

+  * @{

+  */

+HAL_StatusTypeDef HAL_OTFDEC_Init(OTFDEC_HandleTypeDef *hotfdec);

+HAL_StatusTypeDef HAL_OTFDEC_DeInit(OTFDEC_HandleTypeDef *hotfdec);

+void HAL_OTFDEC_MspInit(OTFDEC_HandleTypeDef *hotfdec);

+void HAL_OTFDEC_MspDeInit(OTFDEC_HandleTypeDef *hotfdec);

+

+#if (USE_HAL_OTFDEC_REGISTER_CALLBACKS == 1)

+/* Callbacks Register/UnRegister functions  ***********************************/

+HAL_StatusTypeDef HAL_OTFDEC_RegisterCallback(OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID,

+                                           pOTFDEC_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_OTFDEC_UnRegisterCallback(OTFDEC_HandleTypeDef *hotfdec, HAL_OTFDEC_CallbackIDTypeDef CallbackID);

+#endif /* USE_HAL_OTFDEC_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+

+/** @addtogroup OTFDEC_Exported_Functions_Group2 OTFDEC IRQ handler management

+  * @{

+  */

+void HAL_OTFDEC_IRQHandler(OTFDEC_HandleTypeDef *hotfdec);

+void HAL_OTFDEC_ErrorCallback(OTFDEC_HandleTypeDef *hotfdec);

+/**

+  * @}

+  */

+

+/** @addtogroup OTFDEC_Exported_Functions_Group3 Peripheral Control functions

+  * @{

+  */

+HAL_StatusTypeDef HAL_OTFDEC_RegionKeyLock(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex);

+HAL_StatusTypeDef HAL_OTFDEC_RegionSetKey(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t *pKey);

+HAL_StatusTypeDef HAL_OTFDEC_RegionSetMode(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, uint32_t mode);

+HAL_StatusTypeDef HAL_OTFDEC_RegionConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, OTFDEC_RegionConfigTypeDef *Config, uint32_t lock);

+uint32_t HAL_OTFDEC_KeyCRCComputation(uint32_t *pKey);

+HAL_StatusTypeDef HAL_OTFDEC_RegionEnable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex);

+HAL_StatusTypeDef HAL_OTFDEC_RegionDisable(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex);

+/**

+  * @}

+  */

+

+/** @addtogroup @addtogroup OTFDEC_Exported_Functions_Group4 Peripheral State and Status functions

+  * @{

+  */

+HAL_OTFDEC_StateTypeDef HAL_OTFDEC_GetState(OTFDEC_HandleTypeDef *hotfdec);

+uint32_t HAL_OTFDEC_RegionGetKeyCRC(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex);

+HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint32_t RegionIndex, OTFDEC_RegionConfigTypeDef *Config);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private types -------------------------------------------------------------*/

+/** @defgroup OTFDEC_Private_Types OTFDEC Private Types

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private variables ---------------------------------------------------------*/

+/** @defgroup OTFDEC_Private_Variables OTFDEC Private Variables

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup OTFDEC_Private_Constants OTFDEC Private Constants

+  * @{

+  */

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup OTFDEC_Private_Macros OTFDEC Private Macros

+  * @{

+  */

+

+/**

+  * @brief Verify the OTFDEC peripheral interrupts parameter.

+  * @param __INT__ OTFDEC peripheral set of interrupts parameter

+  * @retval SET (__INT__ is valid) or RESET (__INT__ is invalid)

+  */

+#define IS_OTFDEC_INTERRUPTS(__INT__) (((__INT__) == OTFDEC_SEC_ERROR_INT)     || \

+                                       ((__INT__) == OTFDEC_EXE_ERROR_INT)     || \

+                                       ((__INT__) == OTFDEC_KEY_ERROR_INT)     || \

+                                       ((__INT__) == OTFDEC_SEC_EXE_ERROR_INT) || \

+                                       ((__INT__) == OTFDEC_SEC_KEY_ERROR_INT) || \

+                                       ((__INT__) == OTFDEC_EXE_KEY_ERROR_INT) || \

+                                       ((__INT__) == OTFDEC_ALL_INT)  )

+

+/**

+  * @brief Verify the OTFDEC region configuration lock parameter.

+  * @param __LOCK__ OTFDEC region lock parameter.

+  * @retval SET (__LOCK__ is valid) or RESET (__LOCK__ is invalid)

+  */

+#define IS_OTFDEC_REGION_CONFIG_LOCK(__LOCK__) (((__LOCK__) == OTFDEC_REG_CONFIGR_LOCK_DISABLE) || \

+                                                ((__LOCK__) == OTFDEC_REG_CONFIGR_LOCK_ENABLE)  )

+

+/**

+  * @brief Verify the OTFDEC region operating mode.

+  * @param __MODE__ OTFDEC region operating mode parameter.

+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

+  */

+#define IS_OTFDEC_REGION_OPERATING_MODE(__MODE__) (((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY)    || \

+                                                   ((__MODE__) == OTFDEC_REG_MODE_DATA_ACCESSES_ONLY)           || \

+                                                   ((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_OR_DATA_ACCESSES) || \

+                                                   ((__MODE__) == OTFDEC_REG_MODE_INSTRUCTION_ACCESSES_ONLY_WITH_CIPHER))

+

+/**

+  * @brief Verify the OTFDEC region index.

+  * @param __INDEX__ OTFDEC region index

+  * @retval SET (__INDEX__ is valid) or RESET (__INDEX__ is invalid)

+  */

+#define IS_OTFDEC_REGIONINDEX(__INDEX__) (((__INDEX__) == OTFDEC_REGION1)     || \

+                                          ((__INDEX__) == OTFDEC_REGION2)     || \

+                                          ((__INDEX__) == OTFDEC_REGION3)     || \

+                                          ((__INDEX__) == OTFDEC_REGION4)  )

+

+/**

+  * @brief Verify the OTFDEC configuration attributes.

+  * @param __ATTRIBUTE__ OTFDEC region index

+  * @retval SET (__ATTRIBUTE__ is valid) or RESET (__ATTRIBUTE__ is invalid)

+  */

+#define IS_OTFDEC_ATTRIBUTE(__ATTRIBUTE__) (((__ATTRIBUTE__) == OTFDEC_ATTRIBUTE_PRIV)   || \

+                                            ((__ATTRIBUTE__) == OTFDEC_ATTRIBUTE_NPRIV)  )

+

+/**

+  * @}

+  */

+

+/* Private functions ---------------------------------------------------------*/

+/** @defgroup OTFDEC_Private_Functions OTFDEC Private Functions

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+

+/**

+  * @}

+  */

+#endif /* OTFDEC1 */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* __STM32H7xx_HAL_OTFDEC_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_pcd.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_pcd.h
new file mode 100644
index 0000000000..a47aaaef8f
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_pcd.h
@@ -0,0 +1,436 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_pcd.h

+  * @author  MCD Application Team

+  * @brief   Header file of PCD HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_PCD_H

+#define STM32H7xx_HAL_PCD_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_ll_usb.h"

+

+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup PCD

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup PCD_Exported_Types PCD Exported Types

+  * @{

+  */

+

+/**

+  * @brief  PCD State structure definition

+  */

+typedef enum

+{

+  HAL_PCD_STATE_RESET   = 0x00,

+  HAL_PCD_STATE_READY   = 0x01,

+  HAL_PCD_STATE_ERROR   = 0x02,

+  HAL_PCD_STATE_BUSY    = 0x03,

+  HAL_PCD_STATE_TIMEOUT = 0x04

+} PCD_StateTypeDef;

+

+/* Device LPM suspend state */

+typedef enum

+{

+  LPM_L0 = 0x00, /* on */

+  LPM_L1 = 0x01, /* LPM L1 sleep */

+  LPM_L2 = 0x02, /* suspend */

+  LPM_L3 = 0x03, /* off */

+} PCD_LPM_StateTypeDef;

+

+typedef enum

+{

+  PCD_LPM_L0_ACTIVE = 0x00, /* on */

+  PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */

+} PCD_LPM_MsgTypeDef;

+

+typedef enum

+{

+  PCD_BCD_ERROR                     = 0xFF,

+  PCD_BCD_CONTACT_DETECTION         = 0xFE,

+  PCD_BCD_STD_DOWNSTREAM_PORT       = 0xFD,

+  PCD_BCD_CHARGING_DOWNSTREAM_PORT  = 0xFC,

+  PCD_BCD_DEDICATED_CHARGING_PORT   = 0xFB,

+  PCD_BCD_DISCOVERY_COMPLETED       = 0x00,

+

+} PCD_BCD_MsgTypeDef;

+

+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)

+typedef USB_OTG_GlobalTypeDef  PCD_TypeDef;

+typedef USB_OTG_CfgTypeDef     PCD_InitTypeDef;

+typedef USB_OTG_EPTypeDef      PCD_EPTypeDef;

+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */

+

+/**

+  * @brief  PCD Handle Structure definition

+  */

+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)

+typedef struct __PCD_HandleTypeDef

+#else

+typedef struct

+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */

+{

+  PCD_TypeDef             *Instance;   /*!< Register base address              */

+  PCD_InitTypeDef         Init;        /*!< PCD required parameters            */

+  __IO uint8_t            USB_Address; /*!< USB Address                        */

+  PCD_EPTypeDef           IN_ep[16];   /*!< IN endpoint parameters             */

+  PCD_EPTypeDef           OUT_ep[16];  /*!< OUT endpoint parameters            */

+  HAL_LockTypeDef         Lock;        /*!< PCD peripheral status              */

+  __IO PCD_StateTypeDef   State;       /*!< PCD communication state            */

+  __IO  uint32_t          ErrorCode;   /*!< PCD Error code                     */

+  uint32_t                Setup[12];   /*!< Setup packet buffer                */

+  PCD_LPM_StateTypeDef    LPM_State;   /*!< LPM State                          */

+  uint32_t                BESL;

+

+

+  uint32_t lpm_active;                 /*!< Enable or disable the Link Power Management .

+                                       This parameter can be set to ENABLE or DISABLE        */

+

+  uint32_t battery_charging_active;    /*!< Enable or disable Battery charging.

+                                       This parameter can be set to ENABLE or DISABLE        */

+  void                    *pData;      /*!< Pointer to upper stack Handler */

+

+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)

+  void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd);                              /*!< USB OTG PCD SOF callback                */

+  void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Setup Stage callback        */

+  void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd);                            /*!< USB OTG PCD Reset callback              */

+  void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Suspend callback            */

+  void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd);                           /*!< USB OTG PCD Resume callback             */

+  void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Connect callback            */

+  void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd);                       /*!< USB OTG PCD Disconnect callback         */

+

+  void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);      /*!< USB OTG PCD Data OUT Stage callback     */

+  void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);       /*!< USB OTG PCD Data IN Stage callback      */

+  void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);  /*!< USB OTG PCD ISO OUT Incomplete callback */

+  void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum);   /*!< USB OTG PCD ISO IN Incomplete callback  */

+  void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);      /*!< USB OTG PCD BCD callback                */

+  void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);      /*!< USB OTG PCD LPM callback                */

+

+  void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd);                          /*!< USB OTG PCD Msp Init callback           */

+  void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd);                        /*!< USB OTG PCD Msp DeInit callback         */

+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */

+} PCD_HandleTypeDef;

+

+/**

+  * @}

+  */

+

+/* Include PCD HAL Extended module */

+#include "stm32h7xx_hal_pcd_ex.h"

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup PCD_Exported_Constants PCD Exported Constants

+  * @{

+  */

+

+/** @defgroup PCD_Speed PCD Speed

+  * @{

+  */

+#define PCD_SPEED_HIGH               USBD_HS_SPEED

+#define PCD_SPEED_HIGH_IN_FULL       USBD_HSINFS_SPEED

+#define PCD_SPEED_FULL               USBD_FS_SPEED

+/**

+  * @}

+  */

+

+/** @defgroup PCD_PHY_Module PCD PHY Module

+  * @{

+  */

+#define PCD_PHY_ULPI                 1U

+#define PCD_PHY_EMBEDDED             2U

+#define PCD_PHY_UTMI                 3U

+/**

+  * @}

+  */

+

+/** @defgroup PCD_Error_Code_definition PCD Error Code definition

+  * @brief  PCD Error Code definition

+  * @{

+  */

+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)

+#define  HAL_PCD_ERROR_INVALID_CALLBACK                        (0x00000010U)    /*!< Invalid Callback error  */

+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macros -----------------------------------------------------------*/

+/** @defgroup PCD_Exported_Macros PCD Exported Macros

+ *  @brief macros to handle interrupts and specific clock configurations

+ * @{

+ */

+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)

+#define __HAL_PCD_ENABLE(__HANDLE__)                       (void)USB_EnableGlobalInt ((__HANDLE__)->Instance)

+#define __HAL_PCD_DISABLE(__HANDLE__)                      (void)USB_DisableGlobalInt ((__HANDLE__)->Instance)

+

+#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))

+#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->GINTSTS) &=  (__INTERRUPT__))

+#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__)         (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)

+

+

+#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)             *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= \

+                                                          ~(USB_OTG_PCGCCTL_STOPCLK)

+

+#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)               *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK

+

+#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__)            ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U)

+

+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT()    EXTI_D1->IMR2 |= (USB_OTG_HS_WAKEUP_EXTI_LINE)

+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT()   EXTI_D1->IMR2 &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)

+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT()    EXTI_D1->IMR2 |= (USB_OTG_FS_WAKEUP_EXTI_LINE)

+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT()   EXTI_D1->IMR2 &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)

+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */

+

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup PCD_Exported_Functions PCD Exported Functions

+  * @{

+  */

+

+/* Initialization/de-initialization functions  ********************************/

+/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions

+  * @{

+  */

+HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);

+HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd);

+void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);

+void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);

+

+#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)

+/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition

+  * @brief  HAL USB OTG PCD Callback ID enumeration definition

+  * @{

+  */

+typedef enum

+{

+  HAL_PCD_SOF_CB_ID          = 0x01,      /*!< USB PCD SOF callback ID          */

+  HAL_PCD_SETUPSTAGE_CB_ID   = 0x02,      /*!< USB PCD Setup Stage callback ID  */

+  HAL_PCD_RESET_CB_ID        = 0x03,      /*!< USB PCD Reset callback ID        */

+  HAL_PCD_SUSPEND_CB_ID      = 0x04,      /*!< USB PCD Suspend callback ID      */

+  HAL_PCD_RESUME_CB_ID       = 0x05,      /*!< USB PCD Resume callback ID       */

+  HAL_PCD_CONNECT_CB_ID      = 0x06,      /*!< USB PCD Connect callback ID      */

+  HAL_PCD_DISCONNECT_CB_ID  = 0x07,      /*!< USB PCD Disconnect callback ID   */

+

+  HAL_PCD_MSPINIT_CB_ID      = 0x08,      /*!< USB PCD MspInit callback ID      */

+  HAL_PCD_MSPDEINIT_CB_ID    = 0x09       /*!< USB PCD MspDeInit callback ID    */

+

+} HAL_PCD_CallbackIDTypeDef;

+/**

+  * @}

+  */

+

+/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition

+  * @brief  HAL USB OTG PCD Callback pointer definition

+  * @{

+  */

+

+typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd);                                   /*!< pointer to a common USB OTG PCD callback function  */

+typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD Data OUT Stage callback     */

+typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD Data IN Stage callback      */

+typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);        /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */

+typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum);         /*!< pointer to USB OTG PCD ISO IN Incomplete callback  */

+typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);        /*!< pointer to USB OTG PCD LPM callback                */

+typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);        /*!< pointer to USB OTG PCD BCD callback                */

+

+/**

+  * @}

+  */

+

+HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, pPCD_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID);

+

+HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataOutStageCallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd);

+

+HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, pPCD_DataInStageCallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd);

+

+HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoOutIncpltCallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd);

+

+HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, pPCD_IsoInIncpltCallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd);

+

+HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd);

+

+HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd);

+#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/* I/O operation functions  ***************************************************/

+/* Non-Blocking mode: Interrupt */

+/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions

+  * @{

+  */

+HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);

+HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);

+void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);

+

+void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);

+void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);

+void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);

+void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);

+void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);

+void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);

+void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);

+

+void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);

+void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);

+void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);

+void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);

+/**

+  * @}

+  */

+

+/* Peripheral Control functions  **********************************************/

+/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions

+  * @{

+  */

+HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);

+HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);

+HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);

+HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);

+HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);

+HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);

+HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);

+uint32_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);

+HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);

+HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);

+HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);

+HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);

+HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd);

+/**

+  * @}

+  */

+

+/* Peripheral State functions  ************************************************/

+/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions

+  * @{

+  */

+PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup PCD_Private_Constants PCD Private Constants

+  * @{

+  */

+/** @defgroup USB_EXTI_Line_Interrupt USB EXTI line interrupt

+  * @{

+  */

+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)

+#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE                            0x08U

+#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE                           0x0CU

+#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE                    0x10U

+

+#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE                            0x08U

+#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE                           0x0CU

+#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE                    0x10U

+

+#define USB_OTG_FS_WAKEUP_EXTI_LINE                                   (0x1U << 12)  /*!< USB FS EXTI Line WakeUp Interrupt */

+#define USB_OTG_HS_WAKEUP_EXTI_LINE                                   (0x1U << 11)  /*!< USB HS EXTI Line WakeUp Interrupt */

+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */

+

+

+/**

+  * @}

+  */

+/**

+  * @}

+  */

+

+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)

+#ifndef USB_OTG_DOEPINT_OTEPSPR

+#define USB_OTG_DOEPINT_OTEPSPR                (0x1UL << 5)      /*!< Status Phase Received interrupt */

+#endif

+

+#ifndef USB_OTG_DOEPMSK_OTEPSPRM

+#define USB_OTG_DOEPMSK_OTEPSPRM               (0x1UL << 5)      /*!< Setup Packet Received interrupt mask */

+#endif

+

+#ifndef USB_OTG_DOEPINT_NAK

+#define USB_OTG_DOEPINT_NAK                    (0x1UL << 13)      /*!< NAK interrupt */

+#endif

+

+#ifndef USB_OTG_DOEPMSK_NAKM

+#define USB_OTG_DOEPMSK_NAKM                   (0x1UL << 13)      /*!< OUT Packet NAK interrupt mask */

+#endif

+

+#ifndef USB_OTG_DOEPINT_STPKTRX

+#define USB_OTG_DOEPINT_STPKTRX                (0x1UL << 15)      /*!< Setup Packet Received interrupt */

+#endif

+

+#ifndef USB_OTG_DOEPMSK_NYETM

+#define USB_OTG_DOEPMSK_NYETM                  (0x1UL << 14)      /*!< Setup Packet Received interrupt mask */

+#endif

+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup PCD_Private_Macros PCD Private Macros

+ * @{

+ */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_PCD_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_pcd_ex.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_pcd_ex.h
new file mode 100644
index 0000000000..21d5b92ffc
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_pcd_ex.h
@@ -0,0 +1,91 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_pcd_ex.h

+  * @author  MCD Application Team

+  * @brief   Header file of PCD HAL Extension module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_PCD_EX_H

+#define STM32H7xx_HAL_PCD_EX_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup PCDEx

+  * @{

+  */

+/* Exported types ------------------------------------------------------------*/

+/* Exported constants --------------------------------------------------------*/

+/* Exported macros -----------------------------------------------------------*/

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions

+  * @{

+  */

+/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions

+  * @{

+  */

+

+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)

+HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size);

+HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size);

+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */

+

+

+HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd);

+HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd);

+

+

+HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd);

+HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd);

+void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd);

+

+void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg);

+void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */

+

+#ifdef __cplusplus

+}

+#endif

+

+

+#endif /* STM32H7xx_HAL_PCD_EX_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_pssi.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_pssi.h
new file mode 100644
index 0000000000..b890f5832c
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_pssi.h
@@ -0,0 +1,506 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_pssi.h

+  * @author  MCD Application Team

+  * @brief   Header file of PSSI HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_PSSI_H

+#define STM32H7xx_HAL_PSSI_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+#if defined(PSSI)

+/** @addtogroup PSSI PSSI

+  * @brief PSSI HAL module driver

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup PSSI_Exported_Types PSSI Exported Types

+  * @{

+  */

+

+

+/**

+  * @brief PSSI Init structure definition

+  */

+typedef struct

+{

+  uint32_t  DataWidth;          /* !< Configures the parallel bus width 8 lines or 16 lines */

+  uint32_t  BusWidth;           /* !< Configures the parallel bus width 8 lines or 16 lines */

+  uint32_t  ControlSignal;      /* !< Configures Data enable and Data ready */

+  uint32_t  ClockPolarity;      /* !< Configures the PSSI Input Clock polarity */

+  uint32_t  DataEnablePolarity; /* !< Configures the PSSI Data Enable polarity */

+  uint32_t  ReadyPolarity;      /* !< Configures the PSSI Ready polarity */

+

+} PSSI_InitTypeDef;

+

+

+/**

+  * @brief  HAL PSSI State structures definition

+  */

+typedef enum

+{

+  HAL_PSSI_STATE_RESET   = 0x00U, /* !< PSSI not yet initialized or disabled     */

+  HAL_PSSI_STATE_READY   = 0x01U, /* !< Peripheral initialized and ready for use */

+  HAL_PSSI_STATE_BUSY    = 0x02U, /* !< An internal process is ongoing           */

+  HAL_PSSI_STATE_BUSY_TX = 0x03U, /* !< Transmit process is ongoing              */

+  HAL_PSSI_STATE_BUSY_RX = 0x04U, /* !< Receive process is ongoing               */

+  HAL_PSSI_STATE_TIMEOUT = 0x05U, /* !< Timeout state                            */

+  HAL_PSSI_STATE_ERROR   = 0x06U, /* !< PSSI state error                         */

+  HAL_PSSI_STATE_ABORT   = 0x07U, /* !< PSSI process is aborted                  */

+

+} HAL_PSSI_StateTypeDef;

+

+/**

+  * @brief  PSSI handle Structure definition

+  */

+typedef struct __PSSI_HandleTypeDef

+{

+  PSSI_TypeDef         *Instance;    /*!< PSSI register base address.    */

+  PSSI_InitTypeDef      Init;        /*!< PSSI Initialization Structure. */

+  uint32_t             *pBuffPtr;    /*!< PSSI Data buffer.              */

+  uint32_t              XferCount;   /*!< PSSI transfer count            */

+  uint32_t              XferSize;    /*!< PSSI  transfer size            */

+  DMA_HandleTypeDef    *hdmatx;      /*!< PSSI Tx DMA Handle parameters  */

+  DMA_HandleTypeDef    *hdmarx;      /*!< PSSI Rx DMA Handle parameters  */

+

+  void (* TxCpltCallback)(struct __PSSI_HandleTypeDef *hpssi);    /*!< PSSI transfer complete callback. */

+  void (* RxCpltCallback)(struct __PSSI_HandleTypeDef *hpssi);    /*!< PSSI transfer complete callback. */

+  void (* ErrorCallback)(struct __PSSI_HandleTypeDef *hpssi);     /*!< PSSI transfer complete callback. */

+  void (* AbortCpltCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI transfer error callback.    */

+

+  void (* MspInitCallback)(struct __PSSI_HandleTypeDef *hpssi);   /*!< PSSI Msp Init callback.          */

+  void (* MspDeInitCallback)(struct __PSSI_HandleTypeDef *hpssi); /*!< PSSI Msp DeInit callback.        */

+

+  HAL_LockTypeDef             Lock;                               /*!< PSSI lock.                       */

+  __IO HAL_PSSI_StateTypeDef State;                               /*!< PSSI transfer state.             */

+  __IO uint32_t               ErrorCode;                          /*!< PSSI error code.                 */

+

+} PSSI_HandleTypeDef;

+

+

+/**

+  * @brief  HAL PSSI Callback pointer definition

+  */

+typedef  void (*pPSSI_CallbackTypeDef)(PSSI_HandleTypeDef *hpssi);  /*!< Pointer to a PSSI common callback function */

+

+/**

+  * @}

+  */

+/**

+  * @brief  HAL PSSI Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_PSSI_TX_COMPLETE_CB_ID = 0x00U, /*!< PSSI Tx Transfer completed callback ID  */

+  HAL_PSSI_RX_COMPLETE_CB_ID = 0x01U, /*!< PSSI Rx Transfer completed callback ID  */

+  HAL_PSSI_ERROR_CB_ID       = 0x03U, /*!< PSSI Error callback ID                  */

+  HAL_PSSI_ABORT_CB_ID       = 0x04U, /*!< PSSI Abort callback ID                  */

+

+  HAL_PSSI_MSPINIT_CB_ID     = 0x05U, /*!< PSSI Msp Init callback ID               */

+  HAL_PSSI_MSPDEINIT_CB_ID   = 0x06U  /*!< PSSI Msp DeInit callback ID             */

+

+} HAL_PSSI_CallbackIDTypeDef;

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup PSSI_Exported_Constants PSSI Exported Constants

+  * @{

+  */

+

+/** @defgroup PSSI_Error_Code PSSI Error Code

+  * @{

+  */

+#define HAL_PSSI_ERROR_NONE             0x00000000U /*!< No error                */

+#define HAL_PSSI_ERROR_NOT_SUPPORTED    0x00000001U /*!< Not supported operation */

+#define HAL_PSSI_ERROR_UNDER_RUN        0x00000002U /*!< FIFO Under-run error    */

+#define HAL_PSSI_ERROR_OVER_RUN         0x00000004U /*!< FIFO Over-run  error    */

+#define HAL_PSSI_ERROR_DMA              0x00000008U /*!< Dma     error           */

+#define HAL_PSSI_ERROR_TIMEOUT          0x00000010U /*!< Timeout error           */

+#define HAL_PSSI_ERROR_INVALID_CALLBACK 0x00000020U /*!< Invalid callback error  */

+

+

+/**

+  * @}

+  */

+

+/** @defgroup PSSI_DATA_WIDTH PSSI Data Width

+  * @{

+  */

+

+#define HAL_PSSI_8BITS                  0x00000000U   /*!<  8 Bits  */

+#define HAL_PSSI_16BITS                 0x00000001U   /*!< 16 Bits  */

+#define HAL_PSSI_32BITS                 0x00000002U   /*!< 32 Bits  */

+/**

+  * @}

+  */

+

+/** @defgroup PSSI_BUS_WIDTH PSSI Bus Width

+  * @{

+  */

+

+#define HAL_PSSI_8LINES                 0x00000000U   /*!< 8 data lines  */

+#define HAL_PSSI_16LINES                PSSI_CR_EDM   /*!< 16 data lines */

+/**

+  * @}

+  */

+/** @defgroup PSSI_MODE PSSI mode

+  * @{

+  */

+#define HAL_PSSI_UNIDIRECTIONAL         0x00000000U /*!< Uni-directional mode */

+#define HAL_PSSI_BIDIRECTIONAL          0x00000001U /*!< Bi-directional mode  */

+/**

+  * @}

+  */

+

+/** @defgroup PSSI_ControlSignal Configuration

+  * @{

+  */

+#define HAL_PSSI_DE_RDY_DISABLE           (0x0U << PSSI_CR_DERDYCFG_Pos) /*!< Neither DE nor RDY are enabled */

+#define HAL_PSSI_RDY_ENABLE               (0x1U << PSSI_CR_DERDYCFG_Pos) /*!< Only RDY enabled */

+#define HAL_PSSI_DE_ENABLE                (0x2U << PSSI_CR_DERDYCFG_Pos) /*!< Only DE enabled */

+#define HAL_PSSI_DE_RDY_ALT_ENABLE        (0x3U << PSSI_CR_DERDYCFG_Pos) /*!< Both RDY and DE alternate functions enabled */

+#define HAL_PSSI_MAP_RDY_BIDIR_ENABLE     (0x4U << PSSI_CR_DERDYCFG_Pos) /*!< Bi-directional on RDY pin */

+#define HAL_PSSI_RDY_MAP_ENABLE           (0x5U << PSSI_CR_DERDYCFG_Pos) /*!< Only RDY enabled, mapped to DE pin */

+#define HAL_PSSI_DE_MAP_ENABLE            (0x6U << PSSI_CR_DERDYCFG_Pos) /*!< Only DE enabled, mapped to RDY pin */

+#define HAL_PSSI_MAP_DE_BIDIR_ENABLE      (0x7U << PSSI_CR_DERDYCFG_Pos) /*!< Bi-directional on DE pin */

+

+/**

+  * @}

+  */

+

+

+/** @defgroup PSSI_Data_Enable_Polarity Data Enable Polarity

+  * @{

+  */

+#define HAL_PSSI_DEPOL_ACTIVE_LOW         0x0U            /*!< Active Low */

+#define HAL_PSSI_DEPOL_ACTIVE_HIGH        PSSI_CR_DEPOL   /*!< Active High */

+/**

+  * @}

+  */

+/** @defgroup PSSI_Reday_Polarity Reday Polarity

+  * @{

+  */

+#define HAL_PSSI_RDYPOL_ACTIVE_LOW        0x0U            /*!< Active Low */

+#define HAL_PSSI_RDYPOL_ACTIVE_HIGH       PSSI_CR_RDYPOL  /*!< Active High */

+/**

+  * @}

+  */

+

+/** @defgroup PSSI_Clock_Polarity Clock Polarity

+  * @{

+  */

+#define HAL_PSSI_FALLING_EDGE             0x0U            /*!< Fallling Edge */

+#define HAL_PSSI_RISING_EDGE              0x1U            /*!< Rising Edge */

+

+

+/**

+  * @}

+  */

+

+

+/** @defgroup PSSI_DEFINITION PSSI definitions

+  * @{

+  */

+

+#define PSSI_MAX_NBYTE_SIZE         0x10000U         /* 64 KB */

+#define PSSI_TIMEOUT_TRANSMIT       0x0000FFFFU      /*!< Timeout Value   */

+

+#define PSSI_CR_OUTEN_INPUT         0x00000000U      /*!< Input Mode      */

+#define PSSI_CR_OUTEN_OUTPUT        PSSI_CR_OUTEN    /*!< Output Mode     */

+

+#define PSSI_CR_DMA_ENABLE          PSSI_CR_DMAEN    /*!< DMA Mode Enable */

+#define PSSI_CR_DMA_DISABLE         (~PSSI_CR_DMAEN) /*!< DMA Mode Disble */

+

+#define PSSI_CR_16BITS              PSSI_CR_EDM      /*!< 16 Lines Mode   */

+#define PSSI_CR_8BITS               (~PSSI_CR_EDM)   /*!< 8 Lines Mode    */

+

+#define PSSI_FLAG_RTT1B             PSSI_SR_RTT1B    /*!< 1 Byte Fifo Flag*/

+#define PSSI_FLAG_RTT4B             PSSI_SR_RTT4B    /*!< 4 Bytes Fifo Flag*/

+

+

+

+/**

+  * @}

+  */

+

+/** @defgroup PSSI_Interrupts PSSI Interrupts

+  * @{

+  */

+

+#define PSSI_FLAG_OVR_RIS            PSSI_RIS_OVR_RIS     /*!< Overrun, Underrun errors flag */

+#define PSSI_FLAG_MASK               PSSI_RIS_OVR_RIS_Msk /*!< Overrun, Underrun errors Mask */

+#define PSSI_FLAG_OVR_MIS            PSSI_MIS_OVR_MIS     /*!< Overrun, Underrun masked errors flag */

+/**

+  * @}

+  */

+

+

+

+/**

+  * @}

+  */

+/* Exported macros ------------------------------------------------------------*/

+/** @defgroup PSSI_Exported_Macros PSSI Exported Macros

+  * @{

+  */

+

+/** @brief Reset PSSI handle state

+  * @param  __HANDLE__ specifies the PSSI handle.

+  * @retval None

+  */

+

+#define HAL_PSSI_RESET_HANDLE_STATE(__HANDLE__) do{                                            \

+                                                      (__HANDLE__)->State = HAL_PSSI_STATE_RESET;\

+                                                      (__HANDLE__)->MspInitCallback = NULL;       \

+                                                      (__HANDLE__)->MspDeInitCallback = NULL;     \

+                                                     }while(0)

+

+

+/**

+  * @brief  Enable the PSSI.

+  * @param  __HANDLE__ PSSI handle

+  * @retval None.

+  */

+#define HAL_PSSI_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CR |= PSSI_CR_ENABLE)

+/**

+  * @brief  Disable the PSSI.

+  * @param  __HANDLE__ PSSI handle

+  * @retval None.

+  */

+#define HAL_PSSI_DISABLE(__HANDLE__)        ((__HANDLE__)->Instance->CR &= (~PSSI_CR_ENABLE))

+

+/* PSSI pripheral STATUS */

+/**

+  * @brief  Get the PSSI pending flags.

+  * @param  __HANDLE__ PSSI handle

+  * @param  __FLAG__ flag to check.

+  *          This parameter can be any combination of the following values:

+  *            @arg PSSI_FLAG_RTT1B:  FIFO is ready to transfer one byte

+  *            @arg PSSI_FLAG_RTT4B: FIFO is ready to transfer four bytes

+  * @retval The state of FLAG.

+  */

+

+#define HAL_PSSI_GET_STATUS(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR & (__FLAG__))

+

+

+

+/* Interrupt & Flag management */

+/**

+  * @brief  Get the PSSI pending flags.

+  * @param  __HANDLE__ PSSI handle

+  * @param  __FLAG__ flag to check.

+  *          This parameter can be any combination of the following values:

+  *            @arg PSSI_FLAG_OVR_RIS: Data Buffer overrun/underrun error flag

+  * @retval The state of FLAG.

+  */

+#define HAL_PSSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->RIS & (__FLAG__))

+

+/**

+  * @brief  Clear the PSSI pending flags.

+  * @param  __HANDLE__ PSSI handle

+  * @param  __FLAG__ specifies the flag to clear.

+  *          This parameter can be any combination of the following values:

+  *            @arg PSSI_FLAG_OVR_RIS: Data Buffer overrun/underrun error flag

+  * @retval None

+  */

+#define HAL_PSSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))

+

+/**

+  * @brief  Enable the specified PSSI interrupts.

+  * @param  __HANDLE__ PSSI handle

+  * @param __INTERRUPT__ specifies the PSSI interrupt sources to be enabled.

+  *          This parameter can be any combination of the following values:

+  *            @arg PSSI_FLAG_OVR_RIS: Configuration error mask

+  * @retval None

+  */

+#define HAL_PSSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))

+

+/**

+  * @brief  Disable the specified PSSI interrupts.

+  * @param  __HANDLE__ PSSI handle

+  * @param __INTERRUPT__ specifies the PSSI interrupt sources to be disabled.

+  *          This parameter can be any combination of the following values:

+  *            @arg PSSI_IT_OVR_IE: Configuration error mask

+  * @retval None

+  */

+#define HAL_PSSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= ~(__INTERRUPT__))

+

+/**

+  * @brief  Check whether the specified PSSI interrupt source is enabled or not.

+  * @param  __HANDLE__ PSSI handle

+  * @param  __INTERRUPT__ specifies the PSSI interrupt source to check.

+  *          This parameter can be one of the following values:

+  *            @arg PSSI_IT_OVR_IE: Data Buffer overrun/underrun error interrupt mask

+  * @retval The state of INTERRUPT source.

+  */

+#define HAL_PSSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))

+

+/**

+  * @brief  Check whether the PSSI Control signal is valid.

+  * @param  __CONTROL__ Control signals configuration

+  * @retval Valid or not.

+  */

+

+#define IS_PSSI_CONTROL_SIGNAL(__CONTROL__) (((__CONTROL__) == HAL_PSSI_DE_RDY_DISABLE        ) || \

+                                             ((__CONTROL__) == HAL_PSSI_RDY_ENABLE            ) || \

+                                             ((__CONTROL__) == HAL_PSSI_DE_ENABLE             ) || \

+                                             ((__CONTROL__) == HAL_PSSI_DE_RDY_ALT_ENABLE     ) || \

+                                             ((__CONTROL__) == HAL_PSSI_MAP_RDY_BIDIR_ENABLE  ) || \

+                                             ((__CONTROL__) == HAL_PSSI_RDY_MAP_ENABLE        ) || \

+                                             ((__CONTROL__) == HAL_PSSI_DE_MAP_ENABLE         ) || \

+                                             ((__CONTROL__) == HAL_PSSI_MAP_DE_BIDIR_ENABLE   ))

+/**

+  * @brief  Check whether the PSSI Bus Width is valid.

+  * @param  __BUSWIDTH__ PSSI Bush width

+  * @retval Valid or not.

+  */

+

+#define IS_PSSI_BUSWIDTH(__BUSWIDTH__) (((__BUSWIDTH__) == HAL_PSSI_8LINES    ) || \

+                                        ((__BUSWIDTH__) == HAL_PSSI_16LINES   ))

+

+/**

+  * @brief  Check whether the PSSI Clock Polarity is valid.

+  * @param  __CLOCKPOL__ PSSI Clock Polarity

+  * @retval Valid or not.

+  */

+

+#define IS_PSSI_CLOCK_POLARITY(__CLOCKPOL__) (((__CLOCKPOL__) == HAL_PSSI_FALLING_EDGE   ) || \

+                                              ((__CLOCKPOL__) == HAL_PSSI_RISING_EDGE    ))

+/**

+  * @brief  Check whether the PSSI Data Enable Polarity is valid.

+  * @param  __DEPOL__ PSSI DE Polarity

+  * @retval Valid or not.

+  */

+

+#define IS_PSSI_DE_POLARITY(__DEPOL__) (((__DEPOL__) == HAL_PSSI_DEPOL_ACTIVE_LOW    ) || \

+                                        ((__DEPOL__) == HAL_PSSI_DEPOL_ACTIVE_HIGH   ))

+/**

+  * @brief  Check whether the PSSI Ready Polarity is valid.

+  * @param  __RDYPOL__ PSSI RDY Polarity

+  * @retval Valid or not.

+  */

+

+#define IS_PSSI_RDY_POLARITY(__RDYPOL__) (((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_LOW   ) || \

+                                         ((__RDYPOL__) == HAL_PSSI_RDYPOL_ACTIVE_HIGH   ))

+/**

+  * @}

+  */

+

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup PSSI_Exported_Functions

+  * @{

+  */

+

+/** @addtogroup PSSI_Exported_Functions_Group1

+  * @{

+  */

+

+/* Initialization and de-initialization functions *******************************/

+HAL_StatusTypeDef HAL_PSSI_Init(PSSI_HandleTypeDef *hpssi);

+HAL_StatusTypeDef HAL_PSSI_DeInit(PSSI_HandleTypeDef *hpssi);

+void              HAL_PSSI_MspInit(PSSI_HandleTypeDef *hpssi);

+void              HAL_PSSI_MspDeInit(PSSI_HandleTypeDef *hpssi);

+/* Callbacks Register/UnRegister functions  ***********************************/

+

+HAL_StatusTypeDef HAL_PSSI_RegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID, pPSSI_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_PSSI_UnRegisterCallback(PSSI_HandleTypeDef *hpssi, HAL_PSSI_CallbackIDTypeDef CallbackID);

+

+

+/**

+  * @}

+  */

+

+/** @addtogroup PSSI_Exported_Functions_Group2

+  * @{

+  */

+

+/* IO operation functions *******************************************************/

+HAL_StatusTypeDef HAL_PSSI_Transmit(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout);

+HAL_StatusTypeDef HAL_PSSI_Receive(PSSI_HandleTypeDef *hpssi, uint8_t *pData, uint32_t Size, uint32_t Timeout);

+HAL_StatusTypeDef HAL_PSSI_Transmit_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size);

+HAL_StatusTypeDef HAL_PSSI_Receive_DMA(PSSI_HandleTypeDef *hpssi, uint32_t *pData, uint32_t Size);

+HAL_StatusTypeDef HAL_PSSI_Abort_DMA(PSSI_HandleTypeDef *hpssi);

+void HAL_PSSI_IRQHandler(PSSI_HandleTypeDef *hpssi);

+

+/**

+  * @}

+  */

+

+/** @addtogroup PSSI_Exported_Functions_Group3

+  * @{

+  */

+

+void HAL_PSSI_TxCpltCallback(PSSI_HandleTypeDef *hpssi);

+void HAL_PSSI_RxCpltCallback(PSSI_HandleTypeDef *hpssi);

+void HAL_PSSI_ErrorCallback(PSSI_HandleTypeDef *hpssi);

+void HAL_PSSI_AbortCpltCallback(PSSI_HandleTypeDef *hpssi);

+

+

+/**

+  * @}

+  */

+

+/** @addtogroup PSSI_Exported_Functions_Group4

+  * @{

+  */

+

+/* Peripheral State functions ***************************************************/

+HAL_PSSI_StateTypeDef HAL_PSSI_GetState(PSSI_HandleTypeDef *hpssi);

+uint32_t               HAL_PSSI_GetError(PSSI_HandleTypeDef *hpssi);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private constants ---------------------------------------------------------*/

+

+

+/* Private macros ------------------------------------------------------------*/

+

+

+/**

+  * @}

+  */

+#endif /* PSSI */

+

+/**

+  * @}

+  */

+

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_PSSI_H */

+

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_pwr.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_pwr.h
new file mode 100644
index 0000000000..0d4624022c
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_pwr.h
@@ -0,0 +1,774 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_pwr.h

+  * @author  MCD Application Team

+  * @brief   Header file of PWR HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_PWR_H

+#define STM32H7xx_HAL_PWR_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif /* __cplusplus */

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup PWR

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+

+/** @defgroup PWR_Exported_Types PWR Exported Types

+  * @{

+  */

+

+/**

+  * @brief  PWR PVD configuration structure definition

+  */

+typedef struct

+{

+  uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. This

+                                    parameter can be a value of @ref

+                                    PWR_PVD_detection_level.

+                     */

+

+  uint32_t Mode;     /*!< Mode: Specifies the EXTI operating mode for the PVD

+                                event. This parameter can be a value of @ref

+                                PWR_PVD_Mode.

+                     */

+}PWR_PVDTypeDef;

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup PWR_Exported_Constants PWR Exported Constants

+  * @{

+  */

+

+/** @defgroup PWR_PVD_detection_level PWR PVD detection level

+  * @{

+  */

+#define PWR_PVDLEVEL_0  PWR_CR1_PLS_LEV0  /*!< Programmable voltage detector

+                                               level 0 selection : 1V95       */

+#define PWR_PVDLEVEL_1  PWR_CR1_PLS_LEV1  /*!< Programmable voltage detector

+                                               level 1 selection : 2V1        */

+#define PWR_PVDLEVEL_2  PWR_CR1_PLS_LEV2  /*!< Programmable voltage detector

+                                               level 2 selection : 2V25       */

+#define PWR_PVDLEVEL_3  PWR_CR1_PLS_LEV3  /*!< Programmable voltage detector

+                                               level 3 selection : 2V4        */

+#define PWR_PVDLEVEL_4  PWR_CR1_PLS_LEV4  /*!< Programmable voltage detector

+                                               level 4 selection : 2V55       */

+#define PWR_PVDLEVEL_5  PWR_CR1_PLS_LEV5  /*!< Programmable voltage detector

+                                               level 5 selection : 2V7        */

+#define PWR_PVDLEVEL_6  PWR_CR1_PLS_LEV6  /*!< Programmable voltage detector

+                                               level 6 selection : 2V85       */

+#define PWR_PVDLEVEL_7  PWR_CR1_PLS_LEV7  /*!< External input analog voltage

+                                               (Compare internally to VREF)   */

+/**

+  * @}

+  */

+

+/** @defgroup PWR_PVD_Mode PWR PVD Mode

+  * @{

+  */

+#define PWR_PVD_MODE_NORMAL               (0x00000000U) /*!< Basic mode is used                                        */

+#define PWR_PVD_MODE_IT_RISING            (0x00010001U) /*!< Interrupt Mode with Rising edge trigger detection         */

+#define PWR_PVD_MODE_IT_FALLING           (0x00010002U) /*!< Interrupt Mode with Falling edge trigger detection        */

+#define PWR_PVD_MODE_IT_RISING_FALLING    (0x00010003U) /*!< Interrupt Mode with Rising/Falling edge trigger detection */

+#define PWR_PVD_MODE_EVENT_RISING         (0x00020001U) /*!< Event Mode with Rising edge trigger detection             */

+#define PWR_PVD_MODE_EVENT_FALLING        (0x00020002U) /*!< Event Mode with Falling edge trigger detection            */

+#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection     */

+/**

+  * @}

+  */

+

+/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode

+  * @{

+  */

+#define PWR_MAINREGULATOR_ON      (0U)

+#define PWR_LOWPOWERREGULATOR_ON  PWR_CR1_LPDS

+/**

+  * @}

+  */

+

+/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry

+  * @{

+  */

+#define PWR_SLEEPENTRY_WFI  (0x01U)

+#define PWR_SLEEPENTRY_WFE  (0x02U)

+/**

+  * @}

+  */

+

+/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry

+  * @{

+  */

+#define PWR_STOPENTRY_WFI  (0x01U)

+#define PWR_STOPENTRY_WFE  (0x02U)

+/**

+  * @}

+  */

+

+/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale

+  * @{

+  */

+#if defined(PWR_SRDCR_VOS)

+#define PWR_REGULATOR_VOLTAGE_SCALE0  (PWR_SRDCR_VOS_1 | PWR_SRDCR_VOS_0)

+#define PWR_REGULATOR_VOLTAGE_SCALE1  (PWR_SRDCR_VOS_1)

+#define PWR_REGULATOR_VOLTAGE_SCALE2  (PWR_SRDCR_VOS_0)

+#define PWR_REGULATOR_VOLTAGE_SCALE3  (0U)

+#else

+#define PWR_REGULATOR_VOLTAGE_SCALE0  (0U)

+#define PWR_REGULATOR_VOLTAGE_SCALE1  (PWR_D3CR_VOS_1 | PWR_D3CR_VOS_0)

+#define PWR_REGULATOR_VOLTAGE_SCALE2  (PWR_D3CR_VOS_1)

+#define PWR_REGULATOR_VOLTAGE_SCALE3  (PWR_D3CR_VOS_0)

+#endif /* PWR_SRDCR_VOS */

+/**

+  * @}

+  */

+

+/** @defgroup PWR_Flag PWR Flag

+  * @{

+  */

+/* PWR CPU flag */

+#define PWR_FLAG_STOP       (0x01U)

+#if defined (PWR_CPUCR_SBF_D2)

+#define PWR_FLAG_SB_D1      (0x02U)

+#define PWR_FLAG_SB_D2      (0x03U)

+#endif /* defined (PWR_CPUCR_SBF_D2) */

+#define PWR_FLAG_SB         (0x04U)

+#if defined (DUAL_CORE)

+#define PWR_FLAG_CPU_HOLD   (0x05U)

+#define PWR_FLAG_CPU2_HOLD  (0x06U)

+#define PWR_FLAG2_STOP      (0x07U)

+#define PWR_FLAG2_SB_D1     (0x08U)

+#define PWR_FLAG2_SB_D2     (0x09U)

+#define PWR_FLAG2_SB        (0x0AU)

+#endif /* defined (DUAL_CORE) */

+#define PWR_FLAG_PVDO       (0x0BU)

+#define PWR_FLAG_AVDO       (0x0CU)

+#define PWR_FLAG_ACTVOSRDY  (0x0DU)

+#define PWR_FLAG_ACTVOS     (0x0EU)

+#define PWR_FLAG_BRR        (0x0FU)

+#define PWR_FLAG_VOSRDY     (0x10U)

+#if defined (SMPS)

+#define PWR_FLAG_SMPSEXTRDY (0x11U)

+#else

+#define PWR_FLAG_SCUEN      (0x11U)

+#endif /* defined (SMPS) */

+#if defined (PWR_CSR1_MMCVDO)

+#define PWR_FLAG_MMCVDO     (0x12U)

+#endif /* defined (PWR_CSR1_MMCVDO) */

+#define PWR_FLAG_USB33RDY   (0x13U)

+#define PWR_FLAG_TEMPH      (0x14U)

+#define PWR_FLAG_TEMPL      (0x15U)

+#define PWR_FLAG_VBATH      (0x16U)

+#define PWR_FLAG_VBATL      (0x17U)

+

+/* PWR Wake up flag */

+#define PWR_FLAG_WKUP1 PWR_WKUPCR_WKUPC1

+#define PWR_FLAG_WKUP2 PWR_WKUPCR_WKUPC2

+#define PWR_FLAG_WKUP3 PWR_WKUPCR_WKUPC3

+#define PWR_FLAG_WKUP4 PWR_WKUPCR_WKUPC4

+#define PWR_FLAG_WKUP5 PWR_WKUPCR_WKUPC5

+#define PWR_FLAG_WKUP6 PWR_WKUPCR_WKUPC6

+/**

+  * @}

+  */

+

+/** @defgroup PWR_ENABLE_WUP_Mask PWR Enable WUP Mask

+  * @{

+  */

+#define  PWR_EWUP_MASK  (0x0FFF3F3FU)

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup PWR_Exported_Macro PWR Exported Macro

+  * @{

+  */

+

+/** @brief  Configure the main internal regulator output voltage.

+  * @param  __REGULATOR__ : Specifies the regulator output voltage to achieve a

+  *                         trade-off between performance and power consumption

+  *                         when the device does not operate at the maximum

+  *                         frequency (refer to the datasheet for more details).

+  *          This parameter can be one of the following values:

+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE0 : Regulator voltage output

+  *                                                Scale 0 mode.

+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output

+  *                                                Scale 1 mode.

+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output

+  *                                                Scale 2 mode.

+  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output

+  *                                                Scale 3 mode.

+  * @note   For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines,

+  *         configuring Voltage Scale 0 is only possible when Vcore is supplied

+  *         from LDO (Low DropOut). The SYSCFG Clock must be enabled through

+  *         __HAL_RCC_SYSCFG_CLK_ENABLE() macro before configuring Voltage Scale

+  *         0 using __HAL_PWR_VOLTAGESCALING_CONFIG().

+  *         Transition to Voltage Scale 0 is only possible when the system is

+  *         already in Voltage Scale 1.

+  *         Transition from Voltage Scale 0 is only possible to Voltage Scale 1

+  *         then once in Voltage Scale 1 it is possible to switch to another

+  *         voltage scale.

+  *         After each regulator voltage setting, wait on VOSRDY flag to be set

+  *         using macro __HAL_PWR_GET_FLAG().

+  *         To enter low power mode , and if current regulator voltage is

+  *         Voltage Scale 0 then first switch to Voltage Scale 1 before entering

+  *         low power mode.

+  * @retval None.

+  */

+#if defined(PWR_SRDCR_VOS) /* STM32H7Axxx and STM32H7Bxxx lines */

+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)                         \

+do {                                                                           \

+      __IO uint32_t tmpreg = 0x00;                                             \

+      MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, (__REGULATOR__));                  \

+      /* Delay after setting the voltage scaling */                            \

+      tmpreg = READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS);                            \

+      UNUSED(tmpreg);                                                          \

+} while(0)

+#else /* All H7 lines except STM32H7Axxx and STM32H7Bxxx lines */

+#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__)                         \

+do {                                                                           \

+      __IO uint32_t tmpreg = 0x00;                                             \

+      /* Check the voltage scaling to be configured */                         \

+      if((__REGULATOR__) == PWR_REGULATOR_VOLTAGE_SCALE0)                      \

+      {                                                                        \

+        /* Configure the Voltage Scaling 1 */                                  \

+        MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, PWR_REGULATOR_VOLTAGE_SCALE1);     \

+        /* Delay after setting the voltage scaling */                          \

+        tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS);                            \

+        /* Enable the PWR overdrive */                                         \

+        SET_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                             \

+        /* Delay after setting the syscfg boost setting */                     \

+        tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                   \

+      }                                                                        \

+      else                                                                     \

+      {                                                                        \

+        /* Disable the PWR overdrive */                                        \

+        CLEAR_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                           \

+        /* Delay after setting the syscfg boost setting */                     \

+        tmpreg = READ_BIT(SYSCFG->PWRCR, SYSCFG_PWRCR_ODEN);                   \

+        /* Configure the Voltage Scaling x */                                  \

+        MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, (__REGULATOR__));                  \

+        /* Delay after setting the voltage scaling */                          \

+        tmpreg = READ_BIT(PWR->D3CR, PWR_D3CR_VOS);                            \

+      }                                                                        \

+      UNUSED(tmpreg);                                                          \

+} while(0)

+#endif /* PWR_SRDCR_VOS */

+

+/** @brief  Check PWR flags are set or not.

+  * @param  __FLAG__ : Specifies the flag to check.

+  *           This parameter can be one of the following values:

+  *            @arg PWR_FLAG_PVDO : PVD Output. This flag is valid only if PVD

+  *                                 is enabled by the HAL_PWR_EnablePVD()

+  *                                 function.

+  *                                 The PVD is stopped by STANDBY mode. For this

+  *                                 reason, this bit is equal to 0 after STANDBY

+  *                                 or reset until the PVDE bit is set.

+  *            @arg PWR_FLAG_AVDO : AVD Output. This flag is valid only if AVD

+  *                                 is enabled by the HAL_PWREx_EnableAVD()

+  *                                 function. The AVD is stopped by STANDBY mode.

+  *                                 For this reason, this bit is equal to 0

+  *                                 after STANDBY or reset until the AVDE bit

+  *                                 is set.

+  *            @arg PWR_FLAG_ACTVOSRDY : This flag indicates that the Regulator

+  *                                      voltage scaling output selection is

+  *                                      ready.

+  *            @arg PWR_FLAG_BRR : Backup regulator ready flag. This bit is not

+  *                                reset when the device wakes up from STANDBY

+  *                                mode or by a system reset or power-on reset.

+  *            @arg PWR_FLAG_VOSRDY : This flag indicates that the Regulator

+  *                                   voltage scaling output selection is ready.

+  *                                mode or by a system reset or power-on reset.

+  *            @arg PWR_FLAG_USB33RDY : This flag indicates that the USB supply

+  *                                     from regulator is ready.

+  *            @arg PWR_FLAG_TEMPH : This flag indicates that the temperature

+  *                                  equal or above high threshold level.

+  *            @arg PWR_FLAG_TEMPL : This flag indicates that the temperature

+  *                                  equal or below low threshold level.

+  *            @arg PWR_FLAG_VBATH : This flag indicates that VBAT level equal

+  *                                  or above high threshold level.

+  *            @arg PWR_FLAG_VBATL : This flag indicates that VBAT level equal

+  *                                  or below low threshold level.

+  *            @arg PWR_FLAG_STOP : This flag indicates that the system entered

+  *                                 in STOP mode.

+  *            @arg PWR_FLAG_SB : This flag indicates that the system entered in

+  *                               STANDBY mode.

+  *            @arg PWR_FLAG_SB_D1 : This flag indicates that the D1 domain

+  *                                  entered in STANDBY mode.

+  *            @arg PWR_FLAG_SB_D2 : This flag indicates that the D2 domain

+  *                                  entered in STANDBY mode.

+  *            @arg PWR_FLAG2_STOP : This flag indicates that the system entered

+  *                                 in STOP mode.

+  *            @arg PWR_FLAG2_SB : This flag indicates that the system entered

+  *                                in STANDBY mode.

+  *            @arg PWR_FLAG2_SB_D1 : This flag indicates that the D1 domain

+  *                                   entered in STANDBY mode.

+  *            @arg PWR_FLAG2_SB_D2 : This flag indicates that the D2 domain

+  *                                   entered in STANDBY mode.

+  *            @arg PWR_FLAG_CPU_HOLD : This flag indicates that the CPU1 wakes

+  *                                     up with hold.

+  *            @arg PWR_FLAG_CPU2_HOLD : This flag indicates that the CPU2 wakes

+  *                                      up with hold.

+  *            @arg PWR_FLAG_SMPSEXTRDY : This flag indicates that the SMPS

+  *                                       External supply is sready.

+  *            @arg PWR_FLAG_SCUEN : This flag indicates that the supply

+  *                                  configuration update is enabled.

+  *            @arg PWR_FLAG_MMCVDO : This flag indicates that the VDDMMC is

+  *                                   above or equal to 1.2 V.

+  * @note   The PWR_FLAG_PVDO, PWR_FLAG_AVDO, PWR_FLAG_ACTVOSRDY, PWR_FLAG_BRR,

+  *         PWR_FLAG_VOSRDY, PWR_FLAG_USB33RDY, PWR_FLAG_TEMPH, PWR_FLAG_TEMPL,

+  *         PWR_FLAG_VBATH, PWR_FLAG_VBATL, PWR_FLAG_STOP and PWR_FLAG_SB flags

+  *         are used for all H7 family lines.

+  *         The PWR_FLAG2_STOP, PWR_FLAG2_SB, PWR_FLAG2_SB_D1, PWR_FLAG2_SB_D2,

+  *         PWR_FLAG_CPU_HOLD and PWR_FLAG_CPU2_HOLD flags are used only for H7

+  *         dual core lines.

+  *         The PWR_FLAG_SB_D1 and PWR_FLAG_SB_D2 flags are used for all H7

+  *         family except STM32H7Axxx and STM32H7Bxxx lines.

+  *         The PWR_FLAG_MMCVDO flag is used only for STM32H7Axxx and

+  *         STM32H7Bxxx lines.

+  *         The PWR_FLAG_SCUEN flag is used for STM32H743, STM32H753, STM32H742,

+  *         STM32H750, STM32H7Axx and STM32H7Bxx lines.

+  *         The PWR_FLAG_SMPSEXTRDY flag is used for dual core and STM32H7AxxQ,

+  *         STM32H7BxxQ lines.

+  * @retval The (__FLAG__) state (TRUE or FALSE).

+  */

+#if defined (DUAL_CORE) /* Dual core lines */

+#define __HAL_PWR_GET_FLAG(__FLAG__)                                                              \

+(((__FLAG__) == PWR_FLAG_PVDO)       ? ((PWR->CSR1 & PWR_CSR1_PVDO)       == PWR_CSR1_PVDO)      :\

+ ((__FLAG__) == PWR_FLAG_AVDO)       ? ((PWR->CSR1 & PWR_CSR1_AVDO)       == PWR_CSR1_AVDO)      :\

+ ((__FLAG__) == PWR_FLAG_ACTVOSRDY)  ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY)  == PWR_CSR1_ACTVOSRDY) :\

+ ((__FLAG__) == PWR_FLAG_VOSRDY)     ? ((PWR->D3CR & PWR_D3CR_VOSRDY)     == PWR_D3CR_VOSRDY)    :\

+ ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY)   == PWR_CR3_SMPSEXTRDY) :\

+ ((__FLAG__) == PWR_FLAG_BRR)        ? ((PWR->CR2 & PWR_CR2_BRRDY)        == PWR_CR2_BRRDY)      :\

+ ((__FLAG__) == PWR_FLAG_CPU_HOLD)   ? ((PWR->CPU2CR & PWR_CPU2CR_HOLD1F) == PWR_CPU2CR_HOLD1F)  :\

+ ((__FLAG__) == PWR_FLAG_CPU2_HOLD)  ? ((PWR->CPUCR & PWR_CPUCR_HOLD2F)   == PWR_CPUCR_HOLD2F)   :\

+ ((__FLAG__) == PWR_FLAG_SB)         ? ((PWR->CPUCR & PWR_CPUCR_SBF)      == PWR_CPUCR_SBF)      :\

+ ((__FLAG__) == PWR_FLAG2_SB)        ? ((PWR->CPU2CR & PWR_CPU2CR_SBF)    == PWR_CPU2CR_SBF)     :\

+ ((__FLAG__) == PWR_FLAG_STOP)       ? ((PWR->CPUCR & PWR_CPUCR_STOPF)    == PWR_CPUCR_STOPF)    :\

+ ((__FLAG__) == PWR_FLAG2_STOP)      ? ((PWR->CPU2CR & PWR_CPU2CR_STOPF)  == PWR_CPU2CR_STOPF)   :\

+ ((__FLAG__) == PWR_FLAG_SB_D1)      ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1)   == PWR_CPUCR_SBF_D1)   :\

+ ((__FLAG__) == PWR_FLAG2_SB_D1)     ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D1) == PWR_CPU2CR_SBF_D1)  :\

+ ((__FLAG__) == PWR_FLAG_SB_D2)      ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2)   == PWR_CPUCR_SBF_D2)   :\

+ ((__FLAG__) == PWR_FLAG2_SB_D2)     ? ((PWR->CPU2CR & PWR_CPU2CR_SBF_D2) == PWR_CPU2CR_SBF_D2)  :\

+ ((__FLAG__) == PWR_FLAG_USB33RDY)   ? ((PWR->CR3 & PWR_CR3_USB33RDY)     == PWR_CR3_USB33RDY)   :\

+ ((__FLAG__) == PWR_FLAG_TEMPH)      ? ((PWR->CR2 & PWR_CR2_TEMPH)        == PWR_CR2_TEMPH)      :\

+ ((__FLAG__) == PWR_FLAG_TEMPL)      ? ((PWR->CR2 & PWR_CR2_TEMPL)        == PWR_CR2_TEMPL)      :\

+ ((__FLAG__) == PWR_FLAG_VBATH)      ? ((PWR->CR2 & PWR_CR2_VBATH)        == PWR_CR2_VBATH)      :\

+ ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))

+#else /* Single core lines */

+#if defined (PWR_CPUCR_SBF_D2) /* STM32H743, STM32H753, STM32H742 and STM32H750 lines */

+#define __HAL_PWR_GET_FLAG(__FLAG__)                                                            \

+(((__FLAG__) == PWR_FLAG_PVDO)      ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\

+ ((__FLAG__) == PWR_FLAG_AVDO)      ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\

+ ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\

+ ((__FLAG__) == PWR_FLAG_VOSRDY)    ? ((PWR->D3CR & PWR_D3CR_VOSRDY)    == PWR_D3CR_VOSRDY)    :\

+ ((__FLAG__) == PWR_FLAG_SCUEN)     ? ((PWR->CR3 & PWR_CR3_SCUEN)       == PWR_CR3_SCUEN)      :\

+ ((__FLAG__) == PWR_FLAG_BRR)       ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\

+ ((__FLAG__) == PWR_FLAG_SB)        ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\

+ ((__FLAG__) == PWR_FLAG_STOP)      ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\

+ ((__FLAG__) == PWR_FLAG_SB_D1)     ? ((PWR->CPUCR & PWR_CPUCR_SBF_D1)  == PWR_CPUCR_SBF_D1)   :\

+ ((__FLAG__) == PWR_FLAG_SB_D2)     ? ((PWR->CPUCR & PWR_CPUCR_SBF_D2)  == PWR_CPUCR_SBF_D2)   :\

+ ((__FLAG__) == PWR_FLAG_USB33RDY)  ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\

+ ((__FLAG__) == PWR_FLAG_TEMPH)     ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\

+ ((__FLAG__) == PWR_FLAG_TEMPL)     ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\

+ ((__FLAG__) == PWR_FLAG_VBATH)     ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\

+ ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))

+#else /* STM32H7Axxx and STM32H7Bxxx lines */

+#if defined (SMPS) /* STM32H7AxxQ and STM32H7BxxQ SMPS lines */

+#define __HAL_PWR_GET_FLAG(__FLAG__)                                                            \

+(((__FLAG__) == PWR_FLAG_PVDO)       ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\

+ ((__FLAG__) == PWR_FLAG_AVDO)       ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\

+ ((__FLAG__) == PWR_FLAG_ACTVOSRDY)  ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\

+ ((__FLAG__) == PWR_FLAG_BRR)        ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\

+ ((__FLAG__) == PWR_FLAG_VOSRDY)     ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY)  == PWR_SRDCR_VOSRDY)   :\

+ ((__FLAG__) == PWR_FLAG_STOP)       ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\

+ ((__FLAG__) == PWR_FLAG_SB)         ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\

+ ((__FLAG__) == PWR_FLAG_MMCVDO)     ? ((PWR->CSR1 & PWR_CSR1_MMCVDO)    == PWR_CSR1_MMCVDO)    :\

+ ((__FLAG__) == PWR_FLAG_SMPSEXTRDY) ? ((PWR->CR3 & PWR_CR3_SMPSEXTRDY)  == PWR_CR3_SMPSEXTRDY) :\

+ ((__FLAG__) == PWR_FLAG_USB33RDY)   ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\

+ ((__FLAG__) == PWR_FLAG_TEMPH)      ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\

+ ((__FLAG__) == PWR_FLAG_TEMPL)      ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\

+ ((__FLAG__) == PWR_FLAG_VBATH)      ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\

+ ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))

+#else /* STM32H7Axx and STM32H7Bxx LDO lines */

+#define __HAL_PWR_GET_FLAG(__FLAG__)                                    \

+(((__FLAG__) == PWR_FLAG_PVDO)      ? ((PWR->CSR1 & PWR_CSR1_PVDO)      == PWR_CSR1_PVDO)      :\

+ ((__FLAG__) == PWR_FLAG_AVDO)      ? ((PWR->CSR1 & PWR_CSR1_AVDO)      == PWR_CSR1_AVDO)      :\

+ ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == PWR_CSR1_ACTVOSRDY) :\

+ ((__FLAG__) == PWR_FLAG_BRR)       ? ((PWR->CR2 & PWR_CR2_BRRDY)       == PWR_CR2_BRRDY)      :\

+ ((__FLAG__) == PWR_FLAG_VOSRDY)    ? ((PWR->SRDCR & PWR_SRDCR_VOSRDY)  == PWR_SRDCR_VOSRDY)   :\

+ ((__FLAG__) == PWR_FLAG_SCUEN)     ? ((PWR->CR3 & PWR_CR3_SCUEN)       == PWR_CR3_SCUEN)      :\

+ ((__FLAG__) == PWR_FLAG_STOP)      ? ((PWR->CPUCR & PWR_CPUCR_STOPF)   == PWR_CPUCR_STOPF)    :\

+ ((__FLAG__) == PWR_FLAG_SB)        ? ((PWR->CPUCR & PWR_CPUCR_SBF)     == PWR_CPUCR_SBF)      :\

+ ((__FLAG__) == PWR_FLAG_MMCVDO)    ? ((PWR->CSR1 & PWR_CSR1_MMCVDO)    == PWR_CSR1_MMCVDO)    :\

+ ((__FLAG__) == PWR_FLAG_USB33RDY)  ? ((PWR->CR3 & PWR_CR3_USB33RDY)    == PWR_CR3_USB33RDY)   :\

+ ((__FLAG__) == PWR_FLAG_TEMPH)     ? ((PWR->CR2 & PWR_CR2_TEMPH)       == PWR_CR2_TEMPH)      :\

+ ((__FLAG__) == PWR_FLAG_TEMPL)     ? ((PWR->CR2 & PWR_CR2_TEMPL)       == PWR_CR2_TEMPL)      :\

+ ((__FLAG__) == PWR_FLAG_VBATH)     ? ((PWR->CR2 & PWR_CR2_VBATH)       == PWR_CR2_VBATH)      :\

+ ((PWR->CR2 & PWR_CR2_VBATL) == PWR_CR2_VBATL))

+#endif /* SMPS */

+#endif /* PWR_CPUCR_SBF_D2 */

+#endif /* DUAL_CORE */

+

+/** @brief  Check PWR wake up flags are set or not.

+  * @param  __FLAG__: specifies the wake up flag to check.

+  *           This parameter can be one of the following values:

+  *            @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag.

+  *            @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag.

+  *            @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag.

+  *            @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag.

+  *            @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag.

+  *            @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag.

+  * @retval The (__FLAG__) state (TRUE or FALSE).

+  */

+#define __HAL_PWR_GET_WAKEUPFLAG(__FLAG__) ((PWR->WKUPFR & (__FLAG__)) ? 0 : 1)

+

+#if defined (DUAL_CORE)

+/** @brief  Clear CPU PWR flags.

+  * @param  __FLAG__ : Specifies the flag to clear.

+  * @note   This parameter is not used for the STM32H7 family and is kept as

+  *         parameter just to maintain compatibility with other families.

+  * @note   This macro clear all CPU flags STOPF, SBF, SBF_D1, and SBF_D2.

+  *           This parameter can be one of the following values :

+  *            @arg PWR_CPU_FLAGS : Clear HOLD2F, STOPF, SBF, SBF_D1, and SBF_D2

+  *                                 CPU flags.

+  * @retval None.

+  */

+#define __HAL_PWR_CLEAR_FLAG(__FLAG__)      \

+do {                                        \

+     SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF);   \

+     SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF); \

+} while(0)

+#else

+/** @brief  Clear CPU PWR flags.

+  * @param  __FLAG__ : Specifies the flag to clear.

+  * @note   This parameter is not used for the STM32H7 family and is kept as

+  *         parameter just to maintain compatibility with other families.

+  * @note   This macro clear all CPU flags.

+  *         For STM32H7Axxx and STM32H7Bxxx lines CPU flags are STOPF and SBF.

+  *         For dual core lines flags are HOLDxF, STOPF, SBF and SBF_Dx.

+  * @retval None.

+  */

+#define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF)

+#endif /* defined (DUAL_CORE) */

+

+/** @brief  Clear PWR wake up flags.

+  * @param  __FLAG__ : Specifies the wake up flag to be cleared.

+  *           This parameter can be one of the following values :

+  *            @arg PWR_FLAG_WKUP1 : This parameter clear Wake up line 1 flag.

+  *            @arg PWR_FLAG_WKUP2 : This parameter clear Wake up line 2 flag.

+  *            @arg PWR_FLAG_WKUP3 : This parameter clear Wake up line 3 flag.

+  *            @arg PWR_FLAG_WKUP4 : This parameter clear Wake up line 4 flag.

+  *            @arg PWR_FLAG_WKUP5 : This parameter clear Wake up line 5 flag.

+  *            @arg PWR_FLAG_WKUP6 : This parameter clear Wake up line 6 flag.

+  * @retval None.

+  */

+#define __HAL_PWR_CLEAR_WAKEUPFLAG(__FLAG__) SET_BIT(PWR->WKUPCR, (__FLAG__))

+

+/**

+  * @brief Enable the PVD EXTI Line 16.

+  * @retval None.

+  */

+#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)

+

+#if defined (DUAL_CORE)

+/**

+  * @brief Enable the PVD EXTI D2 Line 16.

+  * @retval None.

+  */

+#define __HAL_PWR_PVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)

+#endif /* defined (DUAL_CORE) */

+

+/**

+  * @brief Disable the PVD EXTI Line 16.

+  * @retval None.

+  */

+#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD)

+

+#if defined (DUAL_CORE)

+/**

+  * @brief Disable the PVD EXTI D2 Line 16.

+  * @retval None.

+  */

+#define __HAL_PWR_PVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_PVD)

+#endif /* defined (DUAL_CORE) */

+

+/**

+  * @brief   Enable event on PVD EXTI Line 16.

+  * @retval None.

+  */

+#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)

+

+#if defined (DUAL_CORE)

+/**

+  * @brief Enable event on PVD EXTI D2 Line.

+  * @retval None.

+  */

+#define __HAL_PWR_PVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)

+#endif /* defined (DUAL_CORE) */

+

+/**

+  * @brief   Disable event on PVD EXTI Line 16.

+  * @retval None.

+  */

+#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD)

+

+#if defined (DUAL_CORE)

+/**

+  * @brief Disable event on PVD EXTI D2 Line.

+  * @retval None.

+  */

+#define __HAL_PWR_PVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_PVD)

+#endif /* defined (DUAL_CORE) */

+

+/**

+  * @brief Enable the PVD Rising Interrupt Trigger.

+  * @retval None.

+  */

+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)

+

+/**

+  * @brief Disable the PVD Rising Interrupt Trigger.

+  * @retval None.

+  */

+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD)

+

+/**

+  * @brief Enable the PVD Falling Interrupt Trigger.

+  * @retval None.

+  */

+#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)

+

+/**

+  * @brief Disable the PVD Falling Interrupt Trigger.

+  * @retval None.

+  */

+#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD)

+

+/**

+  * @brief Enable the PVD Rising & Falling Interrupt Trigger.

+  * @retval None.

+  */

+#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \

+do {                                                    \

+      __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();          \

+      __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();         \

+} while(0);

+

+/**

+  * @brief Disable the PVD Rising & Falling Interrupt Trigger.

+  * @retval None.

+  */

+#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \

+do {                                                     \

+      __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();          \

+      __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();         \

+} while(0);

+

+/**

+  * @brief Check whether the specified PVD EXTI interrupt flag is set or not.

+  * @retval EXTI PVD Line Status.

+  */

+#define __HAL_PWR_PVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)

+

+#if defined (DUAL_CORE)

+/**

+  * @brief Checks whether the specified PVD EXTI interrupt flag is set or not.

+  * @retval EXTI D2 PVD Line Status.

+  */

+#define __HAL_PWR_PVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD) == PWR_EXTI_LINE_PVD) ? 1UL : 0UL)

+#endif /* defined (DUAL_CORE) */

+

+/**

+  * @brief Clear the PVD EXTI flag.

+  * @retval None.

+  */

+#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_PVD)

+

+#if defined (DUAL_CORE)

+/**

+  * @brief Clear the PVD EXTI D2 flag.

+  * @retval None.

+  */

+#define __HAL_PWR_PVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_PVD)

+#endif /* defined (DUAL_CORE) */

+

+/**

+  * @brief  Generates a Software interrupt on PVD EXTI line.

+  * @retval None.

+  */

+#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD)

+/**

+  * @}

+  */

+

+/* Include PWR HAL Extension module */

+#include "stm32h7xx_hal_pwr_ex.h"

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup PWR_Exported_Functions PWR Exported Functions

+  * @{

+  */

+

+/** @addtogroup PWR_Exported_Functions_Group1 Initialization and De-Initialization functions

+  * @{

+  */

+/* Initialization and de-initialization functions *****************************/

+void HAL_PWR_DeInit(void);

+void HAL_PWR_EnableBkUpAccess(void);

+void HAL_PWR_DisableBkUpAccess(void);

+/**

+  * @}

+  */

+

+/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions

+  * @{

+  */

+/* Peripheral Control functions  **********************************************/

+/* PVD configuration */

+void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);

+void HAL_PWR_EnablePVD(void);

+void HAL_PWR_DisablePVD(void);

+

+/* WakeUp pins configuration */

+void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity);

+void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);

+

+/* Low Power modes entry */

+void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);

+void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);

+void HAL_PWR_EnterSTANDBYMode(void);

+

+/* Power PVD IRQ Handler */

+void HAL_PWR_PVD_IRQHandler(void);

+void HAL_PWR_PVDCallback(void);

+

+/* Cortex System Control functions  *******************************************/

+void HAL_PWR_EnableSleepOnExit(void);

+void HAL_PWR_DisableSleepOnExit(void);

+void HAL_PWR_EnableSEVOnPend(void);

+void HAL_PWR_DisableSEVOnPend(void);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup PWR_Private_Constants PWR Private Constants

+  * @{

+  */

+

+/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line

+  * @{

+  */

+#define PWR_EXTI_LINE_PVD  EXTI_IMR1_IM16 /*!< External interrupt line 16

+                                               Connected to the PVD EXTI Line */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup PWR_Private_Macros PWR Private Macros

+  * @{

+  */

+

+/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters

+  * @{

+  */

+/* Check PVD level parameter */

+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) ||\

+                                 ((LEVEL) == PWR_PVDLEVEL_1) ||\

+                                 ((LEVEL) == PWR_PVDLEVEL_2) ||\

+                                 ((LEVEL) == PWR_PVDLEVEL_3) ||\

+                                 ((LEVEL) == PWR_PVDLEVEL_4) ||\

+                                 ((LEVEL) == PWR_PVDLEVEL_5) ||\

+                                 ((LEVEL) == PWR_PVDLEVEL_6) ||\

+                                 ((LEVEL) == PWR_PVDLEVEL_7))

+

+/* Check PVD mode parameter */

+#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)            ||\

+                               ((MODE) == PWR_PVD_MODE_IT_FALLING)           ||\

+                               ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING)    ||\

+                               ((MODE) == PWR_PVD_MODE_EVENT_RISING)         ||\

+                               ((MODE) == PWR_PVD_MODE_EVENT_FALLING)        ||\

+                               ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) ||\

+                               ((MODE) == PWR_PVD_MODE_NORMAL))

+

+/* Check low power regulator parameter */

+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON)   ||\

+                                     ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))

+

+/* Check low power mode entry parameter */

+#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) ||\

+                                   ((ENTRY) == PWR_SLEEPENTRY_WFE))

+

+/* Check low power mode entry parameter */

+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) ||\

+                                  ((ENTRY) == PWR_STOPENTRY_WFE))

+

+/* Check voltage scale level parameter */

+#define IS_PWR_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE0) || \

+                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \

+                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \

+                                           ((VOLTAGE) == PWR_REGULATOR_VOLTAGE_SCALE3))

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif /* __cplusplus */

+

+#endif /* STM32H7xx_HAL_PWR_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_pwr_ex.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_pwr_ex.h
new file mode 100644
index 0000000000..ebad73c54c
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_pwr_ex.h
@@ -0,0 +1,743 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_pwr_ex.h

+  * @author  MCD Application Team

+  * @brief   Header file of PWR HAL Extension module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_PWR_EX_H

+#define STM32H7xx_HAL_PWR_EX_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif /* __cplusplus */

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup PWREx

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup PWREx_Exported_Types PWREx Exported Types

+  * @{

+  */

+/**

+  * @brief  PWREx AVD configuration structure definition

+  */

+typedef struct

+{

+  uint32_t AVDLevel; /*!< AVDLevel : Specifies the AVD detection level. This

+                          parameter can be a value of @ref

+                          PWREx_AVD_detection_level

+                     */

+

+  uint32_t Mode;     /*!< Mode : Specifies the EXTI operating mode for the AVD

+                                 event. This parameter can be a value of @ref

+                                 PWREx_AVD_Mode.

+                     */

+}PWREx_AVDTypeDef;

+

+/**

+  * @brief  PWREx Wakeup pin configuration structure definition

+  */

+typedef struct

+{

+  uint32_t WakeUpPin;   /*!< WakeUpPin: Specifies the Wake-Up pin to be enabled.

+                                        This parameter can be a value of @ref

+                                        PWREx_WakeUp_Pins

+                        */

+

+  uint32_t PinPolarity; /*!< PinPolarity: Specifies the Wake-Up pin polarity.

+                                          This parameter can be a value of @ref

+                                          PWREx_PIN_Polarity

+                        */

+

+  uint32_t PinPull;     /*!< PinPull: Specifies the Wake-Up pin pull. This

+                                      parameter can be a value of @ref

+                                      PWREx_PIN_Pull

+                        */

+}PWREx_WakeupPinTypeDef;

+

+#if defined (PWR_CSR1_MMCVDO)

+/**

+  * @brief  PWR VDDMMC voltage level enum definition

+  */

+typedef enum

+{

+  PWR_MMC_VOLTAGE_BELOW_1V2,      /*!< VDDMMC is below 1V2          */

+  PWR_MMC_VOLTAGE_EQUAL_ABOVE_1V2 /*!< VDDMMC is above or equal 1V2 */

+} PWREx_MMC_VoltageLevel;

+#endif /* defined (PWR_CSR1_MMCVDO) */

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+

+/** @defgroup PWREx_Exported_Constants PWREx Exported Constants

+  * @{

+  */

+/** @defgroup PWREx_WakeUp_Pins PWREx Wake-Up Pins

+  * @{

+  */

+/* High level and No pull (default configuration) */

+#define PWR_WAKEUP_PIN6      PWR_WKUPEPR_WKUPEN6

+#define PWR_WAKEUP_PIN5      PWR_WKUPEPR_WKUPEN5

+#define PWR_WAKEUP_PIN4      PWR_WKUPEPR_WKUPEN4

+#define PWR_WAKEUP_PIN3      PWR_WKUPEPR_WKUPEN3

+#define PWR_WAKEUP_PIN2      PWR_WKUPEPR_WKUPEN2

+#define PWR_WAKEUP_PIN1      PWR_WKUPEPR_WKUPEN1

+

+/* High level and No pull */

+#define PWR_WAKEUP_PIN6_HIGH PWR_WKUPEPR_WKUPEN6

+#define PWR_WAKEUP_PIN5_HIGH PWR_WKUPEPR_WKUPEN5

+#define PWR_WAKEUP_PIN4_HIGH PWR_WKUPEPR_WKUPEN4

+#define PWR_WAKEUP_PIN3_HIGH PWR_WKUPEPR_WKUPEN3

+#define PWR_WAKEUP_PIN2_HIGH PWR_WKUPEPR_WKUPEN2

+#define PWR_WAKEUP_PIN1_HIGH PWR_WKUPEPR_WKUPEN1

+

+/* Low level and No pull */

+#define PWR_WAKEUP_PIN6_LOW  (PWR_WKUPEPR_WKUPP6 | PWR_WKUPEPR_WKUPEN6)

+#define PWR_WAKEUP_PIN5_LOW  (PWR_WKUPEPR_WKUPP5 | PWR_WKUPEPR_WKUPEN5)

+#define PWR_WAKEUP_PIN4_LOW  (PWR_WKUPEPR_WKUPP4 | PWR_WKUPEPR_WKUPEN4)

+#define PWR_WAKEUP_PIN3_LOW  (PWR_WKUPEPR_WKUPP3 | PWR_WKUPEPR_WKUPEN3)

+#define PWR_WAKEUP_PIN2_LOW  (PWR_WKUPEPR_WKUPP2 | PWR_WKUPEPR_WKUPEN2)

+#define PWR_WAKEUP_PIN1_LOW  (PWR_WKUPEPR_WKUPP1 | PWR_WKUPEPR_WKUPEN1)

+/**

+  * @}

+  */

+

+/** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration

+  * @{

+  */

+#define PWR_PIN_POLARITY_HIGH (0x00000000U)

+#define PWR_PIN_POLARITY_LOW  (0x00000001U)

+/**

+  * @}

+  */

+

+/** @defgroup PWREx_PIN_Pull PWREx Pin Pull configuration

+  * @{

+  */

+#define PWR_PIN_NO_PULL   (0x00000000U)

+#define PWR_PIN_PULL_UP   (0x00000001U)

+#define PWR_PIN_PULL_DOWN (0x00000002U)

+/**

+  * @}

+  */

+

+/** @defgroup PWREx_Wakeup_Pins_Flags PWREx Wakeup Pins Flags.

+  * @{

+  */

+#define PWR_WAKEUP_FLAG1 PWR_WKUPFR_WKUPF1 /*!< Wakeup flag on PA0  */

+#define PWR_WAKEUP_FLAG2 PWR_WKUPFR_WKUPF2 /*!< Wakeup flag on PA2  */

+#define PWR_WAKEUP_FLAG3 PWR_WKUPFR_WKUPF3 /*!< Wakeup flag on PI8  */

+#define PWR_WAKEUP_FLAG4 PWR_WKUPFR_WKUPF4 /*!< Wakeup flag on PC13 */

+#define PWR_WAKEUP_FLAG5 PWR_WKUPFR_WKUPF5 /*!< Wakeup flag on PI11 */

+#define PWR_WAKEUP_FLAG6 PWR_WKUPFR_WKUPF6 /*!< Wakeup flag on PC1  */

+#define PWR_WAKEUP_FLAG_ALL (PWR_WKUPFR_WKUPF1 | PWR_WKUPFR_WKUPF2 |\

+                             PWR_WKUPFR_WKUPF3 | PWR_WKUPFR_WKUPF4 |\

+                             PWR_WKUPFR_WKUPF5 | PWR_WKUPFR_WKUPF6)

+/**

+  * @}

+  */

+

+#if defined (DUAL_CORE)

+/** @defgroup PWREx_Core_Select PWREx Core definition

+  * @{

+  */

+#define PWR_CORE_CPU1 (0x00000000U)

+#define PWR_CORE_CPU2 (0x00000001U)

+/**

+  * @}

+  */

+#endif /* defined (DUAL_CORE) */

+

+/** @defgroup PWREx_Domains PWREx Domains definition

+  * @{

+  */

+#define PWR_D1_DOMAIN (0x00000000U)

+#if defined (PWR_CPUCR_PDDS_D2)

+#define PWR_D2_DOMAIN (0x00000001U)

+#endif /* defined (PWR_CPUCR_PDDS_D2) */

+#define PWR_D3_DOMAIN (0x00000002U)

+/**

+  * @}

+  */

+

+/** @defgroup PWREx_Domain_Flags PWREx Domain Flags definition

+  * @{

+  */

+#if defined (DUAL_CORE)

+#define PWR_D1_DOMAIN_FLAGS  (0x00000000U)

+#define PWR_D2_DOMAIN_FLAGS  (0x00000001U)

+#define PWR_ALL_DOMAIN_FLAGS (0x00000002U)

+#else

+#define PWR_CPU_FLAGS       (0x00000000U)

+#endif /* defined (DUAL_CORE) */

+/**

+  * @}

+  */

+

+/** @defgroup PWREx_D3_State PWREx D3 Domain State

+  * @{

+  */

+#define PWR_D3_DOMAIN_STOP (0x00000000U)

+#define PWR_D3_DOMAIN_RUN  (0x00000800U)

+

+/**

+  * @}

+  */

+

+/** @defgroup PWREx_Supply_configuration PWREx Supply configuration

+  * @{

+  */

+#define PWR_LDO_SUPPLY                      PWR_CR3_LDOEN                                                               /*!< Core domains are suppplied from the LDO                                                                     */

+#if defined (SMPS)

+#define PWR_DIRECT_SMPS_SUPPLY              PWR_CR3_SMPSEN                                                              /*!< Core domains are suppplied from the SMPS only                                                               */

+#define PWR_SMPS_1V8_SUPPLIES_LDO           (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN    | PWR_CR3_LDOEN)                   /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains                                       */

+#define PWR_SMPS_2V5_SUPPLIES_LDO           (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN    | PWR_CR3_LDOEN)                   /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains                                       */

+#define PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO   (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */

+#define PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO   (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */

+#define PWR_SMPS_1V8_SUPPLIES_EXT           (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains                            */

+#define PWR_SMPS_2V5_SUPPLIES_EXT           (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains                            */

+#endif /* defined (SMPS) */

+#define PWR_EXTERNAL_SOURCE_SUPPLY          PWR_CR3_BYPASS                                                              /*!< The SMPS disabled and the LDO Bypass. The Core domains are supplied from an external source                 */

+

+#if defined (SMPS)

+#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | \

+                                PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)

+#else

+#define PWR_SUPPLY_CONFIG_MASK (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)

+#endif /* defined (SMPS) */

+/**

+  * @}

+  */

+

+

+/** @defgroup PWREx_AVD_detection_level PWREx AVD detection level

+  * @{

+  */

+#define PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0 /*!< Analog voltage detector level 0

+                                             selection : 1V7                 */

+#define PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1 /*!< Analog voltage detector level 1

+                                             selection : 2V1                 */

+#define PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2 /*!< Analog voltage detector level 2

+                                             selection : 2V5                 */

+#define PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3 /*!< Analog voltage detector level 3

+                                             selection : 2V8                 */

+/**

+  * @}

+  */

+

+/** @defgroup PWREx_AVD_Mode PWREx AVD Mode

+  * @{

+  */

+#define PWR_AVD_MODE_NORMAL               (0x00000000U)   /*!< Basic mode is used                                                 */

+#define PWR_AVD_MODE_IT_RISING            (0x00010001U)   /*!< External Interrupt Mode with Rising edge trigger detection         */

+#define PWR_AVD_MODE_IT_FALLING           (0x00010002U)   /*!< External Interrupt Mode with Falling edge trigger detection        */

+#define PWR_AVD_MODE_IT_RISING_FALLING    (0x00010003U)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */

+#define PWR_AVD_MODE_EVENT_RISING         (0x00020001U)   /*!< Event Mode with Rising edge trigger detection                      */

+#define PWR_AVD_MODE_EVENT_FALLING        (0x00020002U)   /*!< Event Mode with Falling edge trigger detection                     */

+#define PWR_AVD_MODE_EVENT_RISING_FALLING (0x00020003U)   /*!< Event Mode with Rising/Falling edge trigger detection              */

+/**

+  * @}

+  */

+

+/** @defgroup PWREx_Regulator_Voltage_Scale PWREx Regulator Voltage Scale

+  * @{

+  */

+#define PWR_REGULATOR_SVOS_SCALE5 (PWR_CR1_SVOS_0)

+#define PWR_REGULATOR_SVOS_SCALE4 (PWR_CR1_SVOS_1)

+#define PWR_REGULATOR_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1)

+/**

+  * @}

+  */

+

+/** @defgroup PWREx_VBAT_Battery_Charging_Resistor PWR battery charging resistor selection

+  * @{

+  */

+#define PWR_BATTERY_CHARGING_RESISTOR_5    (0x00000000U) /*!< VBAT charging through a 5 kOhms resistor   */

+#define PWR_BATTERY_CHARGING_RESISTOR_1_5  PWR_CR3_VBRS  /*!< VBAT charging through a 1.5 kOhms resistor */

+/**

+  * @}

+  */

+

+/** @defgroup PWREx_VBAT_Thresholds PWREx VBAT Thresholds

+  * @{

+  */

+#define PWR_VBAT_BETWEEN_HIGH_LOW_THRESHOLD  (0x00000000U)

+#define PWR_VBAT_BELOW_LOW_THRESHOLD         PWR_CR2_VBATL

+#define PWR_VBAT_ABOVE_HIGH_THRESHOLD        PWR_CR2_VBATH

+/**

+  * @}

+  */

+

+/** @defgroup PWREx_TEMP_Thresholds PWREx Temperature Thresholds

+  * @{

+  */

+#define PWR_TEMP_BETWEEN_HIGH_LOW_THRESHOLD  (0x00000000U)

+#define PWR_TEMP_BELOW_LOW_THRESHOLD         PWR_CR2_TEMPL

+#define PWR_TEMP_ABOVE_HIGH_THRESHOLD        PWR_CR2_TEMPH

+/**

+  * @}

+  */

+/** @defgroup PWREx_AVD_EXTI_Line PWREx AVD EXTI Line 16

+  * @{

+  */

+#define PWR_EXTI_LINE_AVD EXTI_IMR1_IM16 /*!< External interrupt line 16

+                                              Connected to the AVD EXTI Line */

+/**

+  * @}

+  */

+

+#if defined (PWR_CR1_SRDRAMSO)

+/** @defgroup PWREx_Memory_Shut_Off Memory shut-off block selection

+  * @{

+  */

+#define PWR_SRD_AHB_MEMORY_BLOCK        PWR_CR1_SRDRAMSO    /*!< SmartRun domain AHB memory shut-off in DStop/DStop2 low-power mode         */

+#define PWR_USB_FDCAN_MEMORY_BLOCK      PWR_CR1_HSITFSO     /*!< High-speed interfaces USB and FDCAN memories shut-off in DStop/DStop2 mode */

+#define PWR_GFXMMU_JPEG_MEMORY_BLOCK    PWR_CR1_GFXSO       /*!< GFXMMU and JPEG memories shut-off in DStop/DStop2 mode                     */

+#define PWR_TCM_ECM_MEMORY_BLOCK        PWR_CR1_ITCMSO      /*!< Instruction TCM and ETM memories shut-off in DStop/DStop2 mode             */

+#define PWR_RAM1_AHB_MEMORY_BLOCK       PWR_CR1_AHBRAM1SO   /*!< AHB RAM1 shut-off in DStop/DStop2 mode                                     */

+#define PWR_RAM2_AHB_MEMORY_BLOCK       PWR_CR1_AHBRAM2SO   /*!< AHB RAM2 shut-off in DStop/DStop2 mode                                     */

+#define PWR_RAM1_AXI_MEMORY_BLOCK       PWR_CR1_AXIRAM1SO   /*!< AXI RAM1 shut-off in DStop/DStop2 mode                                     */

+#define PWR_RAM2_AXI_MEMORY_BLOCK       PWR_CR1_AXIRAM2SO   /*!< AXI RAM2 shut-off in DStop/DStop2 mode                                     */

+#define PWR_RAM3_AXI_MEMORY_BLOCK       PWR_CR1_AXIRAM3SO   /*!< AXI RAM3 shut-off in DStop/DStop2 mode                                     */

+#define PWR_MEMORY_BLOCK_KEEP_ON        0U                  /*!< Memory content is kept in DStop or DStop2 mode                             */

+#define PWR_MEMORY_BLOCK_SHUT_OFF       1U                  /*!< Memory content is lost in DStop or DStop2 mode                             */

+/**

+  * @}

+  */

+#endif /* defined (PWR_CR1_SRDRAMSO) */

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+

+/** @defgroup PWREx_Exported_Macro PWREx Exported Macro

+  *  @{

+  */

+

+/**

+  * @brief Enable the AVD EXTI Line 16.

+  * @retval None.

+  */

+#define __HAL_PWR_AVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)

+

+#if defined (DUAL_CORE)

+/**

+  * @brief Enable the AVD EXTI D2 Line 16.

+  * @retval None.

+  */

+#define __HAL_PWR_AVD_EXTID2_ENABLE_IT() SET_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD)

+#endif /* defined (DUAL_CORE) */

+

+/**

+  * @brief Disable the AVD EXTI Line 16

+  * @retval None.

+  */

+#define __HAL_PWR_AVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVD)

+

+#if defined (DUAL_CORE)

+/**

+  * @brief Disable the AVD EXTI D2 Line 16.

+  * @retval None.

+  */

+#define __HAL_PWR_AVD_EXTID2_DISABLE_IT() CLEAR_BIT(EXTI_D2->IMR1, PWR_EXTI_LINE_AVD)

+#endif /* defined (DUAL_CORE) */

+

+/**

+  * @brief Enable event on AVD EXTI Line 16.

+  * @retval None.

+  */

+#define __HAL_PWR_AVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)

+

+#if defined (DUAL_CORE)

+/**

+  * @brief Enable event on AVD EXTI D2 Line 16.

+  * @retval None.

+  */

+#define __HAL_PWR_AVD_EXTID2_ENABLE_EVENT() SET_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD)

+#endif /* defined (DUAL_CORE) */

+

+/**

+  * @brief Disable event on AVD EXTI Line 16.

+  * @retval None.

+  */

+#define __HAL_PWR_AVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVD)

+

+#if defined (DUAL_CORE)

+/**

+  * @brief Disable event on AVD EXTI D2 Line 16.

+  * @retval None.

+  */

+#define __HAL_PWR_AVD_EXTID2_DISABLE_EVENT() CLEAR_BIT(EXTI_D2->EMR1, PWR_EXTI_LINE_AVD)

+#endif /* defined (DUAL_CORE) */

+

+/**

+  * @brief Enable the AVD Extended Interrupt Rising Trigger.

+  * @retval None.

+  */

+#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)

+

+/**

+  * @brief Disable the AVD Extended Interrupt Rising Trigger.

+  * @retval None.

+  */

+#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVD)

+

+/**

+  * @brief Enable the AVD Extended Interrupt Falling Trigger.

+  * @retval None.

+  */

+#define __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)

+

+/**

+  * @brief Disable the AVD Extended Interrupt Falling Trigger.

+  * @retval None.

+  */

+#define __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVD)

+

+/**

+  * @brief Enable the AVD Extended Interrupt Rising and Falling Trigger.

+  * @retval None.

+  */

+#define __HAL_PWR_AVD_EXTI_ENABLE_RISING_FALLING_EDGE() \

+do {                                                    \

+     __HAL_PWR_AVD_EXTI_ENABLE_RISING_EDGE();           \

+     __HAL_PWR_AVD_EXTI_ENABLE_FALLING_EDGE();          \

+} while(0);

+

+/**

+  * @brief Disable the AVD Extended Interrupt Rising & Falling Trigger.

+  * @retval None.

+  */

+#define __HAL_PWR_AVD_EXTI_DISABLE_RISING_FALLING_EDGE() \

+do {                                                     \

+     __HAL_PWR_AVD_EXTI_DISABLE_RISING_EDGE();           \

+     __HAL_PWR_AVD_EXTI_DISABLE_FALLING_EDGE();          \

+} while(0);

+

+/**

+  * @brief Check whether the specified AVD EXTI interrupt flag is set or not.

+  * @retval EXTI AVD Line Status.

+  */

+#define __HAL_PWR_AVD_EXTI_GET_FLAG() ((READ_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL)

+

+#if defined (DUAL_CORE)

+/**

+  * @brief Check whether the specified AVD EXTI D2 interrupt flag is set or not.

+  * @retval EXTI D2 AVD Line Status.

+  */

+#define __HAL_PWR_AVD_EXTID2_GET_FLAG() ((READ_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD) == PWR_EXTI_LINE_AVD) ? 1UL : 0UL)

+#endif /* defined (DUAL_CORE) */

+

+/**

+  * @brief  Clear the AVD EXTI flag.

+  * @retval None.

+  */

+#define __HAL_PWR_AVD_EXTI_CLEAR_FLAG() SET_BIT(EXTI->PR1, PWR_EXTI_LINE_AVD)

+

+#if defined (DUAL_CORE)

+/**

+  * @brief  Clear the AVD EXTI D2 flag.

+  * @retval None.

+  */

+#define __HAL_PWR_AVD_EXTID2_CLEAR_FLAG() SET_BIT(EXTI_D2->PR1, PWR_EXTI_LINE_AVD)

+#endif /* defined (DUAL_CORE) */

+

+/**

+  * @brief  Generates a Software interrupt on AVD EXTI line.

+  * @retval None.

+  */

+#define __HAL_PWR_AVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVD)

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+

+/** @addtogroup PWREx_Exported_Functions PWREx Exported Functions

+  * @{

+  */

+

+/** @addtogroup PWREx_Exported_Functions_Group1 Power Supply Control Functions

+  * @{

+  */

+HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource);

+uint32_t HAL_PWREx_GetSupplyConfig(void);

+HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);

+uint32_t HAL_PWREx_GetVoltageRange(void);

+HAL_StatusTypeDef HAL_PWREx_ControlStopModeVoltageScaling(uint32_t VoltageScaling);

+uint32_t HAL_PWREx_GetStopModeVoltageRange(void);

+/**

+  * @}

+  */

+

+/** @addtogroup PWREx_Exported_Functions_Group2 Low Power Control Functions

+  * @{

+  */

+/* System low power control functions */

+#if defined (PWR_CPUCR_RETDS_CD)

+void HAL_PWREx_EnterSTOP2Mode(uint32_t Regulator, uint8_t STOPEntry);

+#endif /* defined (PWR_CPUCR_RETDS_CD) */

+void HAL_PWREx_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry, uint32_t Domain);

+void HAL_PWREx_EnterSTANDBYMode(uint32_t Domain);

+void HAL_PWREx_ConfigD3Domain(uint32_t D3State);

+/* Clear Cortex-Mx pending flag */

+void HAL_PWREx_ClearPendingEvent(void);

+#if defined (DUAL_CORE)

+/* Clear domain flags */

+void HAL_PWREx_ClearDomainFlags(uint32_t DomainFlags);

+/* Core Hold/Release functions */

+HAL_StatusTypeDef HAL_PWREx_HoldCore(uint32_t CPU);

+void HAL_PWREx_ReleaseCore(uint32_t CPU);

+#endif /* defined (DUAL_CORE) */

+/* Flash low power control functions */

+void HAL_PWREx_EnableFlashPowerDown(void);

+void HAL_PWREx_DisableFlashPowerDown(void);

+#if defined (PWR_CR1_SRDRAMSO)

+/* Memory shut-off functions */

+void HAL_PWREx_EnableMemoryShutOff(uint32_t MemoryBlock);

+void HAL_PWREx_DisableMemoryShutOff(uint32_t MemoryBlock);

+#endif /* defined(PWR_CR1_SRDRAMSO) */

+/* Wakeup Pins control functions */

+void HAL_PWREx_EnableWakeUpPin(PWREx_WakeupPinTypeDef *sPinParams);

+void HAL_PWREx_DisableWakeUpPin(uint32_t WakeUpPin);

+uint32_t HAL_PWREx_GetWakeupFlag(uint32_t WakeUpFlag);

+HAL_StatusTypeDef HAL_PWREx_ClearWakeupFlag(uint32_t WakeUpFlag);

+/* Power Wakeup PIN IRQ Handler */

+void HAL_PWREx_WAKEUP_PIN_IRQHandler(void);

+void HAL_PWREx_WKUP1_Callback(void);

+void HAL_PWREx_WKUP2_Callback(void);

+void HAL_PWREx_WKUP3_Callback(void);

+void HAL_PWREx_WKUP4_Callback(void);

+void HAL_PWREx_WKUP5_Callback(void);

+void HAL_PWREx_WKUP6_Callback(void);

+/**

+  * @}

+  */

+

+/** @addtogroup PWREx_Exported_Functions_Group3 Peripherals Control Functions

+  * @{

+  */

+/* Backup regulator control functions */

+HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);

+HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);

+/* USB regulator control functions */

+HAL_StatusTypeDef HAL_PWREx_EnableUSBReg(void);

+HAL_StatusTypeDef HAL_PWREx_DisableUSBReg(void);

+void HAL_PWREx_EnableUSBVoltageDetector(void);

+void HAL_PWREx_DisableUSBVoltageDetector(void);

+/* Battery control functions */

+void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue);

+void HAL_PWREx_DisableBatteryCharging(void);

+#if defined(PWR_CR1_BOOSTE)

+/* Analog Booster functions */

+void HAL_PWREx_EnableAnalogBooster(void);

+void HAL_PWREx_DisableAnalogBooster(void);

+#endif /* PWR_CR1_BOOSTE */

+/**

+  * @}

+  */

+

+/** @addtogroup PWREx_Exported_Functions_Group4 Power Monitoring functions

+  * @{

+  */

+/* Power VBAT/Temperature monitoring functions */

+void HAL_PWREx_EnableMonitoring(void);

+void HAL_PWREx_DisableMonitoring(void);

+uint32_t HAL_PWREx_GetTemperatureLevel(void);

+uint32_t HAL_PWREx_GetVBATLevel(void);

+#if defined(PWR_CSR1_MMCVDO)

+PWREx_MMC_VoltageLevel HAL_PWREx_GetMMCVoltage(void);

+#endif /* PWR_CSR1_MMCVDO */

+/* Power AVD configuration functions */

+void HAL_PWREx_ConfigAVD(PWREx_AVDTypeDef *sConfigAVD);

+void HAL_PWREx_EnableAVD(void);

+void HAL_PWREx_DisableAVD(void);

+/* Power PVD/AVD IRQ Handler */

+void HAL_PWREx_PVD_AVD_IRQHandler(void);

+void HAL_PWREx_AVDCallback(void);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup PWREx_Private_Macros PWREx Private Macros

+  * @{

+  */

+

+/** @defgroup PWREx_IS_PWR_Definitions PWREx Private macros to check input parameters

+  * @{

+  */

+/* Check PWR regulator configuration parameter */

+#if defined (SMPS)

+#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY)                    ||\

+                                   ((PWR_SOURCE) == PWR_DIRECT_SMPS_SUPPLY)            ||\

+                                   ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_LDO)         ||\

+                                   ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_LDO)         ||\

+                                   ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) ||\

+                                   ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) ||\

+                                   ((PWR_SOURCE) == PWR_SMPS_1V8_SUPPLIES_EXT)         ||\

+                                   ((PWR_SOURCE) == PWR_SMPS_2V5_SUPPLIES_EXT)         ||\

+                                   ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))

+

+#else

+#define IS_PWR_SUPPLY(PWR_SOURCE) (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\

+                                   ((PWR_SOURCE) == PWR_EXTERNAL_SOURCE_SUPPLY))

+#endif /* defined (SMPS) */

+

+/* Check PWR regulator configuration in STOP mode parameter */

+#define IS_PWR_STOP_MODE_REGULATOR_VOLTAGE(VOLTAGE) (((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE3)  ||\

+                                                     ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE4)  ||\

+                                                     ((VOLTAGE) == PWR_REGULATOR_SVOS_SCALE5))

+

+/* Check PWR domain parameter */

+#if defined (PWR_CPUCR_PDDS_D2)

+#define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\

+                               ((DOMAIN) == PWR_D2_DOMAIN) ||\

+                               ((DOMAIN) == PWR_D3_DOMAIN))

+#else

+#define IS_PWR_DOMAIN(DOMAIN) (((DOMAIN) == PWR_D1_DOMAIN) ||\

+                               ((DOMAIN) == PWR_D3_DOMAIN))

+#endif /* defined (PWR_CPUCR_PDDS_D2) */

+

+/* Check D3/SRD domain state parameter */

+#define IS_D3_STATE(STATE) (((STATE) == PWR_D3_DOMAIN_STOP) ||\

+                            ((STATE) == PWR_D3_DOMAIN_RUN))

+

+/* Check wake up pin parameter */

+#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1)      ||\

+                                ((PIN) == PWR_WAKEUP_PIN2)      ||\

+                                ((PIN) == PWR_WAKEUP_PIN3)      ||\

+                                ((PIN) == PWR_WAKEUP_PIN4)      ||\

+                                ((PIN) == PWR_WAKEUP_PIN5)      ||\

+                                ((PIN) == PWR_WAKEUP_PIN6)      ||\

+                                ((PIN) == PWR_WAKEUP_PIN1_HIGH) ||\

+                                ((PIN) == PWR_WAKEUP_PIN2_HIGH) ||\

+                                ((PIN) == PWR_WAKEUP_PIN3_HIGH) ||\

+                                ((PIN) == PWR_WAKEUP_PIN4_HIGH) ||\

+                                ((PIN) == PWR_WAKEUP_PIN5_HIGH) ||\

+                                ((PIN) == PWR_WAKEUP_PIN6_HIGH) ||\

+                                ((PIN) == PWR_WAKEUP_PIN1_LOW)  ||\

+                                ((PIN) == PWR_WAKEUP_PIN2_LOW)  ||\

+                                ((PIN) == PWR_WAKEUP_PIN3_LOW)  ||\

+                                ((PIN) == PWR_WAKEUP_PIN4_LOW)  ||\

+                                ((PIN) == PWR_WAKEUP_PIN5_LOW)  ||\

+                                ((PIN) == PWR_WAKEUP_PIN6_LOW))

+

+/* Check wake up pin polarity parameter */

+#define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) ||\

+                                              ((POLARITY) == PWR_PIN_POLARITY_LOW))

+

+/* Check wake up pin pull configuration parameter */

+#define IS_PWR_WAKEUP_PIN_PULL(PULL) (((PULL) == PWR_PIN_NO_PULL) ||\

+                                      ((PULL) == PWR_PIN_PULL_UP) ||\

+                                      ((PULL) == PWR_PIN_PULL_DOWN))

+

+/* Check wake up flag parameter */

+#define IS_PWR_WAKEUP_FLAG(FLAG) (((FLAG) == PWR_WAKEUP_FLAG1) ||\

+                                  ((FLAG) == PWR_WAKEUP_FLAG2) ||\

+                                  ((FLAG) == PWR_WAKEUP_FLAG3) ||\

+                                  ((FLAG) == PWR_WAKEUP_FLAG4) ||\

+                                  ((FLAG) == PWR_WAKEUP_FLAG5) ||\

+                                  ((FLAG) == PWR_WAKEUP_FLAG6) ||\

+                                  ((FLAG) == PWR_WAKEUP_FLAG_ALL))

+

+/* Check wake up flag parameter */

+#define IS_PWR_AVD_LEVEL(LEVEL) (((LEVEL) == PWR_AVDLEVEL_0) ||\

+                                 ((LEVEL) == PWR_AVDLEVEL_1) ||\

+                                 ((LEVEL) == PWR_AVDLEVEL_2) ||\

+                                 ((LEVEL) == PWR_AVDLEVEL_3))

+

+/* Check AVD mode parameter */

+#define IS_PWR_AVD_MODE(MODE) (((MODE) == PWR_AVD_MODE_IT_RISING)         ||\

+                               ((MODE) == PWR_AVD_MODE_IT_FALLING)        ||\

+                               ((MODE) == PWR_AVD_MODE_IT_RISING_FALLING) ||\

+                               ((MODE) == PWR_AVD_MODE_EVENT_RISING)      ||\

+                               ((MODE) == PWR_AVD_MODE_EVENT_FALLING)     ||\

+                               ((MODE) == PWR_AVD_MODE_NORMAL)            ||\

+                               ((MODE) == PWR_AVD_MODE_EVENT_RISING_FALLING))

+

+/* Check resistor battery parameter */

+#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\

+                                                  ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))

+/* Check D1/CD CPU ID parameter */

+#define IS_PWR_D1_CPU(CPU) ((CPU) == CM7_CPUID)

+

+#if defined (DUAL_CORE)

+/* Check CPU parameter */

+#define IS_PWR_CORE(CPU)  (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2))

+

+/* Check D2 CPU ID parameter */

+#define IS_PWR_D2_CPU(CPU) ((CPU) == CM4_CPUID)

+

+/* Check PWR domain flag parameter */

+#define IS_PWR_DOMAIN_FLAG(FLAG)  (((FLAG) == PWR_D1_DOMAIN_FLAGS) || \

+                                   ((FLAG) == PWR_D2_DOMAIN_FLAGS) || \

+                                   ((FLAG) == PWR_ALL_DOMAIN_FLAGS))

+#endif /* defined (DUAL_CORE) */

+

+#if defined (PWR_CR1_SRDRAMSO)

+/* Check memory block parameter */

+#define IS_PWR_MEMORY_BLOCK(BLOCK) (((BLOCK) == PWR_SRD_AHB_MEMORY_BLOCK)     || \

+                                    ((BLOCK) == PWR_USB_FDCAN_MEMORY_BLOCK)   || \

+                                    ((BLOCK) == PWR_GFXMMU_JPEG_MEMORY_BLOCK) || \

+                                    ((BLOCK) == PWR_TCM_ECM_MEMORY_BLOCK)     || \

+                                    ((BLOCK) == PWR_RAM1_AHB_MEMORY_BLOCK)    || \

+                                    ((BLOCK) == PWR_RAM2_AHB_MEMORY_BLOCK)    || \

+                                    ((BLOCK) == PWR_RAM1_AXI_MEMORY_BLOCK)    || \

+                                    ((BLOCK) == PWR_RAM2_AXI_MEMORY_BLOCK)    || \

+                                    ((BLOCK) == PWR_RAM3_AXI_MEMORY_BLOCK))

+#endif /* defined (PWR_CR1_SRDRAMSO) */

+/**

+  * @}

+  */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+#ifdef __cplusplus

+}

+#endif /* __cplusplus */

+

+

+#endif /* STM32H7xx_HAL_PWR_EX_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_qspi.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_qspi.h
new file mode 100644
index 0000000000..d7d955c1c5
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_qspi.h
@@ -0,0 +1,747 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_qspi.h

+  * @author  MCD Application Team

+  * @brief   Header file of QSPI HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                       opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_QSPI_H

+#define STM32H7xx_HAL_QSPI_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+#if defined(QUADSPI)

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup QSPI

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup QSPI_Exported_Types QSPI Exported Types

+  * @{

+  */

+

+/**

+  * @brief  QSPI Init structure definition

+  */

+typedef struct

+{

+  uint32_t ClockPrescaler;     /* Specifies the prescaler factor for generating clock based on the AHB clock.

+                                  This parameter can be a number between 0 and 255 */

+  uint32_t FifoThreshold;      /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode)

+                                  This parameter can be a value between 1 and 32 */

+  uint32_t SampleShifting;     /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to

+                                  take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode)

+                                  This parameter can be a value of @ref QSPI_SampleShifting */

+  uint32_t FlashSize;          /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits

+                                  required to address the flash memory. The flash capacity can be up to 4GB

+                                  (addressed using 32 bits) in indirect mode, but the addressable space in

+                                  memory-mapped mode is limited to 256MB

+                                  This parameter can be a number between 0 and 31 */

+  uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number

+                                  of clock cycles which the chip select must remain high between commands.

+                                  This parameter can be a value of @ref QSPI_ChipSelectHighTime */

+  uint32_t ClockMode;          /* Specifies the Clock Mode. It indicates the level that clock takes between commands.

+                                  This parameter can be a value of @ref QSPI_ClockMode */

+  uint32_t FlashID;            /* Specifies the Flash which will be used,

+                                  This parameter can be a value of @ref QSPI_Flash_Select */

+  uint32_t DualFlash;          /* Specifies the Dual Flash Mode State

+                                  This parameter can be a value of @ref QSPI_DualFlash_Mode */

+}QSPI_InitTypeDef;

+

+/**

+  * @brief HAL QSPI State structures definition

+  */

+typedef enum

+{

+  HAL_QSPI_STATE_RESET             = 0x00U,    /*!< Peripheral not initialized                            */

+  HAL_QSPI_STATE_READY             = 0x01U,    /*!< Peripheral initialized and ready for use              */

+  HAL_QSPI_STATE_BUSY              = 0x02U,    /*!< Peripheral in indirect mode and busy                  */

+  HAL_QSPI_STATE_BUSY_INDIRECT_TX  = 0x12U,    /*!< Peripheral in indirect mode with transmission ongoing */

+  HAL_QSPI_STATE_BUSY_INDIRECT_RX  = 0x22U,    /*!< Peripheral in indirect mode with reception ongoing    */

+  HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U,    /*!< Peripheral in auto polling mode ongoing               */

+  HAL_QSPI_STATE_BUSY_MEM_MAPPED   = 0x82U,    /*!< Peripheral in memory mapped mode ongoing              */

+  HAL_QSPI_STATE_ABORT             = 0x08U,    /*!< Peripheral with abort request ongoing                 */

+  HAL_QSPI_STATE_ERROR             = 0x04U     /*!< Peripheral in error                                   */

+}HAL_QSPI_StateTypeDef;

+

+/**

+  * @brief  QSPI Handle Structure definition

+  */

+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)

+typedef struct __QSPI_HandleTypeDef

+#else

+typedef struct

+#endif

+{

+  QUADSPI_TypeDef            *Instance;        /* QSPI registers base address        */

+  QSPI_InitTypeDef           Init;             /* QSPI communication parameters      */

+  uint8_t                    *pTxBuffPtr;      /* Pointer to QSPI Tx transfer Buffer */

+  __IO uint32_t              TxXferSize;       /* QSPI Tx Transfer size              */

+  __IO uint32_t              TxXferCount;      /* QSPI Tx Transfer Counter           */

+  uint8_t                    *pRxBuffPtr;      /* Pointer to QSPI Rx transfer Buffer */

+  __IO uint32_t              RxXferSize;       /* QSPI Rx Transfer size              */

+  __IO uint32_t              RxXferCount;      /* QSPI Rx Transfer Counter           */

+  MDMA_HandleTypeDef          *hmdma;            /* QSPI Rx/Tx MDMA Handle parameters   */

+  __IO HAL_LockTypeDef       Lock;             /* Locking object                     */

+  __IO HAL_QSPI_StateTypeDef State;            /* QSPI communication state           */

+  __IO uint32_t              ErrorCode;        /* QSPI Error code                    */

+  uint32_t                   Timeout;          /* Timeout for the QSPI memory access */

+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)

+  void (* ErrorCallback)        (struct __QSPI_HandleTypeDef *hqspi);

+  void (* AbortCpltCallback)    (struct __QSPI_HandleTypeDef *hqspi);

+  void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi);

+  void (* CmdCpltCallback)      (struct __QSPI_HandleTypeDef *hqspi);

+  void (* RxCpltCallback)       (struct __QSPI_HandleTypeDef *hqspi);

+  void (* TxCpltCallback)       (struct __QSPI_HandleTypeDef *hqspi);

+  void (* StatusMatchCallback)  (struct __QSPI_HandleTypeDef *hqspi);

+  void (* TimeOutCallback)      (struct __QSPI_HandleTypeDef *hqspi);

+

+  void (* MspInitCallback)      (struct __QSPI_HandleTypeDef *hqspi);

+  void (* MspDeInitCallback)    (struct __QSPI_HandleTypeDef *hqspi);

+#endif

+}QSPI_HandleTypeDef;

+

+/**

+  * @brief  QSPI Command structure definition

+  */

+typedef struct

+{

+  uint32_t Instruction;        /* Specifies the Instruction to be sent

+                                  This parameter can be a value (8-bit) between 0x00 and 0xFF */

+  uint32_t Address;            /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize)

+                                  This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */

+  uint32_t AlternateBytes;     /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize)

+                                  This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */

+  uint32_t AddressSize;        /* Specifies the Address Size

+                                  This parameter can be a value of @ref QSPI_AddressSize */

+  uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size

+                                  This parameter can be a value of @ref QSPI_AlternateBytesSize */

+  uint32_t DummyCycles;        /* Specifies the Number of Dummy Cycles.

+                                  This parameter can be a number between 0 and 31 */

+  uint32_t InstructionMode;    /* Specifies the Instruction Mode

+                                  This parameter can be a value of @ref QSPI_InstructionMode */

+  uint32_t AddressMode;        /* Specifies the Address Mode

+                                  This parameter can be a value of @ref QSPI_AddressMode */

+  uint32_t AlternateByteMode;  /* Specifies the Alternate Bytes Mode

+                                  This parameter can be a value of @ref QSPI_AlternateBytesMode */

+  uint32_t DataMode;           /* Specifies the Data Mode (used for dummy cycles and data phases)

+                                  This parameter can be a value of @ref QSPI_DataMode */

+  uint32_t NbData;             /* Specifies the number of data to transfer. (This is the number of bytes)

+                                  This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length

+                                  until end of memory)*/

+  uint32_t DdrMode;            /* Specifies the double data rate mode for address, alternate byte and data phase

+                                  This parameter can be a value of @ref QSPI_DdrMode */

+  uint32_t DdrHoldHalfCycle;   /* Specifies if the DDR hold is enabled. When enabled it delays the data

+                                  output by one half of system clock in DDR mode.

+                                  This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */

+  uint32_t SIOOMode;           /* Specifies the send instruction only once mode

+                                  This parameter can be a value of @ref QSPI_SIOOMode */

+}QSPI_CommandTypeDef;

+

+/**

+  * @brief  QSPI Auto Polling mode configuration structure definition

+  */

+typedef struct

+{

+  uint32_t Match;              /* Specifies the value to be compared with the masked status register to get a match.

+                                  This parameter can be any value between 0 and 0xFFFFFFFF */

+  uint32_t Mask;               /* Specifies the mask to be applied to the status bytes received.

+                                  This parameter can be any value between 0 and 0xFFFFFFFF */

+  uint32_t Interval;           /* Specifies the number of clock cycles between two read during automatic polling phases.

+                                  This parameter can be any value between 0 and 0xFFFF */

+  uint32_t StatusBytesSize;    /* Specifies the size of the status bytes received.

+                                  This parameter can be any value between 1 and 4 */

+  uint32_t MatchMode;          /* Specifies the method used for determining a match.

+                                  This parameter can be a value of @ref QSPI_MatchMode */

+  uint32_t AutomaticStop;      /* Specifies if automatic polling is stopped after a match.

+                                  This parameter can be a value of @ref QSPI_AutomaticStop */

+}QSPI_AutoPollingTypeDef;

+

+/**

+  * @brief  QSPI Memory Mapped mode configuration structure definition

+  */

+typedef struct

+{

+  uint32_t TimeOutPeriod;      /* Specifies the number of clock to wait when the FIFO is full before to release the chip select.

+                                  This parameter can be any value between 0 and 0xFFFF */

+  uint32_t TimeOutActivation;  /* Specifies if the timeout counter is enabled to release the chip select.

+                                  This parameter can be a value of @ref QSPI_TimeOutActivation */

+}QSPI_MemoryMappedTypeDef;

+

+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  HAL QSPI Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_QSPI_ERROR_CB_ID          = 0x00U,  /*!< QSPI Error Callback ID            */

+  HAL_QSPI_ABORT_CB_ID          = 0x01U,  /*!< QSPI Abort Callback ID            */

+  HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U,  /*!< QSPI FIFO Threshold Callback ID   */

+  HAL_QSPI_CMD_CPLT_CB_ID       = 0x03U,  /*!< QSPI Command Complete Callback ID */

+  HAL_QSPI_RX_CPLT_CB_ID        = 0x04U,  /*!< QSPI Rx Complete Callback ID      */

+  HAL_QSPI_TX_CPLT_CB_ID        = 0x05U,  /*!< QSPI Tx Complete Callback ID      */

+  HAL_QSPI_STATUS_MATCH_CB_ID   = 0x08U,  /*!< QSPI Status Match Callback ID     */

+  HAL_QSPI_TIMEOUT_CB_ID        = 0x09U,  /*!< QSPI Timeout Callback ID          */

+

+  HAL_QSPI_MSP_INIT_CB_ID       = 0x0AU,  /*!< QSPI MspInit Callback ID          */

+  HAL_QSPI_MSP_DEINIT_CB_ID     = 0x0B0   /*!< QSPI MspDeInit Callback ID        */

+}HAL_QSPI_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL QSPI Callback pointer definition

+  */

+typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);

+#endif

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup QSPI_Exported_Constants QSPI Exported Constants

+  * @{

+  */

+

+/** @defgroup QSPI_ErrorCode QSPI Error Code

+  * @{

+  */

+#define HAL_QSPI_ERROR_NONE             0x00000000U /*!< No error                 */

+#define HAL_QSPI_ERROR_TIMEOUT          0x00000001U /*!< Timeout error            */

+#define HAL_QSPI_ERROR_TRANSFER         0x00000002U /*!< Transfer error           */

+#define HAL_QSPI_ERROR_DMA              0x00000004U /*!< DMA transfer error       */

+#define HAL_QSPI_ERROR_INVALID_PARAM    0x00000008U /*!< Invalid parameters error */

+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)

+#define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error   */

+#endif

+/**

+  * @}

+  */

+

+/** @defgroup QSPI_SampleShifting QSPI Sample Shifting

+  * @{

+  */

+#define QSPI_SAMPLE_SHIFTING_NONE      0x00000000U                   /*!<No clock cycle shift to sample data*/

+#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/

+/**

+  * @}

+  */

+

+/** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time

+  * @{

+  */

+#define QSPI_CS_HIGH_TIME_1_CYCLE      0x00000000U                                         /*!<nCS stay high for at least 1 clock cycle between commands*/

+#define QSPI_CS_HIGH_TIME_2_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_0)                      /*!<nCS stay high for at least 2 clock cycles between commands*/

+#define QSPI_CS_HIGH_TIME_3_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_1)                      /*!<nCS stay high for at least 3 clock cycles between commands*/

+#define QSPI_CS_HIGH_TIME_4_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/

+#define QSPI_CS_HIGH_TIME_5_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2)                      /*!<nCS stay high for at least 5 clock cycles between commands*/

+#define QSPI_CS_HIGH_TIME_6_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/

+#define QSPI_CS_HIGH_TIME_7_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/

+#define QSPI_CS_HIGH_TIME_8_CYCLE      ((uint32_t)QUADSPI_DCR_CSHT)                        /*!<nCS stay high for at least 8 clock cycles between commands*/

+/**

+  * @}

+  */

+

+/** @defgroup QSPI_ClockMode QSPI Clock Mode

+  * @{

+  */

+#define QSPI_CLOCK_MODE_0              0x00000000U                    /*!<Clk stays low while nCS is released*/

+#define QSPI_CLOCK_MODE_3              ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/

+/**

+  * @}

+  */

+

+/** @defgroup QSPI_Flash_Select QSPI Flash Select

+  * @{

+  */

+#define QSPI_FLASH_ID_1                0x00000000U                 /*!<FLASH 1 selected*/

+#define QSPI_FLASH_ID_2                ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/

+/**

+  * @}

+  */

+

+  /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode

+  * @{

+  */

+#define QSPI_DUALFLASH_ENABLE          ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/

+#define QSPI_DUALFLASH_DISABLE         0x00000000U                /*!<Dual-flash mode disabled*/

+/**

+  * @}

+  */

+

+/** @defgroup QSPI_AddressSize QSPI Address Size

+  * @{

+  */

+#define QSPI_ADDRESS_8_BITS            0x00000000U                      /*!<8-bit address*/

+#define QSPI_ADDRESS_16_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/

+#define QSPI_ADDRESS_24_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/

+#define QSPI_ADDRESS_32_BITS           ((uint32_t)QUADSPI_CCR_ADSIZE)   /*!<32-bit address*/

+/**

+  * @}

+  */

+

+/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size

+  * @{

+  */

+#define QSPI_ALTERNATE_BYTES_8_BITS    0x00000000U                      /*!<8-bit alternate bytes*/

+#define QSPI_ALTERNATE_BYTES_16_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/

+#define QSPI_ALTERNATE_BYTES_24_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/

+#define QSPI_ALTERNATE_BYTES_32_BITS   ((uint32_t)QUADSPI_CCR_ABSIZE)   /*!<32-bit alternate bytes*/

+/**

+  * @}

+  */

+

+/** @defgroup QSPI_InstructionMode QSPI Instruction Mode

+* @{

+*/

+#define QSPI_INSTRUCTION_NONE          0x00000000U                     /*!<No instruction*/

+#define QSPI_INSTRUCTION_1_LINE        ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/

+#define QSPI_INSTRUCTION_2_LINES       ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/

+#define QSPI_INSTRUCTION_4_LINES       ((uint32_t)QUADSPI_CCR_IMODE)   /*!<Instruction on four lines*/

+/**

+  * @}

+  */

+

+/** @defgroup QSPI_AddressMode QSPI Address Mode

+* @{

+*/

+#define QSPI_ADDRESS_NONE              0x00000000U                      /*!<No address*/

+#define QSPI_ADDRESS_1_LINE            ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/

+#define QSPI_ADDRESS_2_LINES           ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/

+#define QSPI_ADDRESS_4_LINES           ((uint32_t)QUADSPI_CCR_ADMODE)   /*!<Address on four lines*/

+/**

+  * @}

+  */

+

+/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode

+* @{

+*/

+#define QSPI_ALTERNATE_BYTES_NONE      0x00000000U                      /*!<No alternate bytes*/

+#define QSPI_ALTERNATE_BYTES_1_LINE    ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/

+#define QSPI_ALTERNATE_BYTES_2_LINES   ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/

+#define QSPI_ALTERNATE_BYTES_4_LINES   ((uint32_t)QUADSPI_CCR_ABMODE)   /*!<Alternate bytes on four lines*/

+/**

+  * @}

+  */

+

+/** @defgroup QSPI_DataMode QSPI Data Mode

+  * @{

+  */

+#define QSPI_DATA_NONE                 0x00000000U                     /*!<No data*/

+#define QSPI_DATA_1_LINE               ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/

+#define QSPI_DATA_2_LINES              ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/

+#define QSPI_DATA_4_LINES              ((uint32_t)QUADSPI_CCR_DMODE)   /*!<Data on four lines*/

+/**

+  * @}

+  */

+

+/** @defgroup QSPI_DdrMode QSPI DDR Mode

+  * @{

+  */

+#define QSPI_DDR_MODE_DISABLE          0x00000000U                  /*!<Double data rate mode disabled*/

+#define QSPI_DDR_MODE_ENABLE           ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/

+/**

+  * @}

+  */

+

+/** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay

+  * @{

+  */

+#define QSPI_DDR_HHC_ANALOG_DELAY      0x00000000U                  /*!<Delay the data output using analog delay in DDR mode*/

+#define QSPI_DDR_HHC_HALF_CLK_DELAY    ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by one half of system clock in DDR mode*/

+/**

+  * @}

+  */

+

+/** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode

+  * @{

+  */

+#define QSPI_SIOO_INST_EVERY_CMD       0x00000000U                  /*!<Send instruction on every transaction*/

+#define QSPI_SIOO_INST_ONLY_FIRST_CMD  ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/

+/**

+  * @}

+  */

+

+/** @defgroup QSPI_MatchMode QSPI Match Mode

+  * @{

+  */

+#define QSPI_MATCH_MODE_AND            0x00000000U                /*!<AND match mode between unmasked bits*/

+#define QSPI_MATCH_MODE_OR             ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/

+/**

+  * @}

+  */

+

+/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop

+  * @{

+  */

+#define QSPI_AUTOMATIC_STOP_DISABLE    0x00000000U                 /*!<AutoPolling stops only with abort or QSPI disabling*/

+#define QSPI_AUTOMATIC_STOP_ENABLE     ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/

+/**

+  * @}

+  */

+

+/** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation

+  * @{

+  */

+#define QSPI_TIMEOUT_COUNTER_DISABLE   0x00000000U                 /*!<Timeout counter disabled, nCS remains active*/

+#define QSPI_TIMEOUT_COUNTER_ENABLE    ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/

+/**

+  * @}

+  */

+

+/** @defgroup QSPI_Flags QSPI Flags

+  * @{

+  */

+#define QSPI_FLAG_BUSY                 QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/

+#define QSPI_FLAG_TO                   QUADSPI_SR_TOF  /*!<Timeout flag: timeout occurs in memory-mapped mode*/

+#define QSPI_FLAG_SM                   QUADSPI_SR_SMF  /*!<Status match flag: received data matches in autopolling mode*/

+#define QSPI_FLAG_FT                   QUADSPI_SR_FTF  /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/

+#define QSPI_FLAG_TC                   QUADSPI_SR_TCF  /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/

+#define QSPI_FLAG_TE                   QUADSPI_SR_TEF  /*!<Transfer error flag: invalid address is being accessed*/

+/**

+  * @}

+  */

+

+/** @defgroup QSPI_Interrupts QSPI Interrupts

+  * @{

+  */

+#define QSPI_IT_TO                     QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/

+#define QSPI_IT_SM                     QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/

+#define QSPI_IT_FT                     QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/

+#define QSPI_IT_TC                     QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/

+#define QSPI_IT_TE                     QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/

+/**

+  * @}

+  */

+

+/** @defgroup QSPI_Timeout_definition QSPI Timeout definition

+  * @brief QSPI Timeout definition

+  * @{

+  */

+#define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macros -----------------------------------------------------------*/

+/** @defgroup QSPI_Exported_Macros QSPI Exported Macros

+  * @{

+  */

+/** @brief Reset QSPI handle state.

+  * @param  __HANDLE__ : QSPI handle.

+  * @retval None

+  */

+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)

+#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__)           do {                                              \

+                                                                  (__HANDLE__)->State = HAL_QSPI_STATE_RESET; \

+                                                                  (__HANDLE__)->MspInitCallback = NULL;       \

+                                                                  (__HANDLE__)->MspDeInitCallback = NULL;     \

+                                                               } while(0)

+#else

+#define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_QSPI_STATE_RESET)

+#endif

+

+/** @brief  Enable the QSPI peripheral.

+  * @param  __HANDLE__ : specifies the QSPI Handle.

+  * @retval None

+  */

+#define __HAL_QSPI_ENABLE(__HANDLE__)                       SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)

+

+/** @brief  Disable the QSPI peripheral.

+  * @param  __HANDLE__ : specifies the QSPI Handle.

+  * @retval None

+  */

+#define __HAL_QSPI_DISABLE(__HANDLE__)                      CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN)

+

+/** @brief  Enable the specified QSPI interrupt.

+  * @param  __HANDLE__ : specifies the QSPI Handle.

+  * @param  __INTERRUPT__ : specifies the QSPI interrupt source to enable.

+  *          This parameter can be one of the following values:

+  *            @arg QSPI_IT_TO: QSPI Timeout interrupt

+  *            @arg QSPI_IT_SM: QSPI Status match interrupt

+  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt

+  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt

+  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt

+  * @retval None

+  */

+#define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)     SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))

+

+

+/** @brief  Disable the specified QSPI interrupt.

+  * @param  __HANDLE__ : specifies the QSPI Handle.

+  * @param  __INTERRUPT__ : specifies the QSPI interrupt source to disable.

+  *          This parameter can be one of the following values:

+  *            @arg QSPI_IT_TO: QSPI Timeout interrupt

+  *            @arg QSPI_IT_SM: QSPI Status match interrupt

+  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt

+  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt

+  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt

+  * @retval None

+  */

+#define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)    CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))

+

+/** @brief  Check whether the specified QSPI interrupt source is enabled or not.

+  * @param  __HANDLE__ : specifies the QSPI Handle.

+  * @param  __INTERRUPT__ : specifies the QSPI interrupt source to check.

+  *          This parameter can be one of the following values:

+  *            @arg QSPI_IT_TO: QSPI Timeout interrupt

+  *            @arg QSPI_IT_SM: QSPI Status match interrupt

+  *            @arg QSPI_IT_FT: QSPI FIFO threshold interrupt

+  *            @arg QSPI_IT_TC: QSPI Transfer complete interrupt

+  *            @arg QSPI_IT_TE: QSPI Transfer error interrupt

+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).

+  */

+#define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__))

+

+/**

+  * @brief  Check whether the selected QSPI flag is set or not.

+  * @param  __HANDLE__ : specifies the QSPI Handle.

+  * @param  __FLAG__ : specifies the QSPI flag to check.

+  *          This parameter can be one of the following values:

+  *            @arg QSPI_FLAG_BUSY: QSPI Busy flag

+  *            @arg QSPI_FLAG_TO:   QSPI Timeout flag

+  *            @arg QSPI_FLAG_SM:   QSPI Status match flag

+  *            @arg QSPI_FLAG_FT:   QSPI FIFO threshold flag

+  *            @arg QSPI_FLAG_TC:   QSPI Transfer complete flag

+  *            @arg QSPI_FLAG_TE:   QSPI Transfer error flag

+  * @retval None

+  */

+#define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__)           ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET)

+

+/** @brief  Clears the specified QSPI's flag status.

+  * @param  __HANDLE__ : specifies the QSPI Handle.

+  * @param  __FLAG__ : specifies the QSPI clear register flag that needs to be set

+  *          This parameter can be one of the following values:

+  *            @arg QSPI_FLAG_TO: QSPI Timeout flag

+  *            @arg QSPI_FLAG_SM: QSPI Status match flag

+  *            @arg QSPI_FLAG_TC: QSPI Transfer complete flag

+  *            @arg QSPI_FLAG_TE: QSPI Transfer error flag

+  * @retval None

+  */

+#define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__)         WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__))

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup QSPI_Exported_Functions

+  * @{

+  */

+

+/** @addtogroup QSPI_Exported_Functions_Group1

+  * @{

+  */

+/* Initialization/de-initialization functions  ********************************/

+HAL_StatusTypeDef     HAL_QSPI_Init     (QSPI_HandleTypeDef *hqspi);

+HAL_StatusTypeDef     HAL_QSPI_DeInit   (QSPI_HandleTypeDef *hqspi);

+void                  HAL_QSPI_MspInit  (QSPI_HandleTypeDef *hqspi);

+void                  HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi);

+/**

+  * @}

+  */

+

+/** @addtogroup QSPI_Exported_Functions_Group2

+  * @{

+  */

+/* IO operation functions *****************************************************/

+/* QSPI IRQ handler method */

+void                  HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi);

+

+/* QSPI indirect mode */

+HAL_StatusTypeDef     HAL_QSPI_Command      (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout);

+HAL_StatusTypeDef     HAL_QSPI_Transmit     (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);

+HAL_StatusTypeDef     HAL_QSPI_Receive      (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout);

+HAL_StatusTypeDef     HAL_QSPI_Command_IT   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd);

+HAL_StatusTypeDef     HAL_QSPI_Transmit_IT  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);

+HAL_StatusTypeDef     HAL_QSPI_Receive_IT   (QSPI_HandleTypeDef *hqspi, uint8_t *pData);

+HAL_StatusTypeDef     HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData);

+HAL_StatusTypeDef     HAL_QSPI_Receive_DMA  (QSPI_HandleTypeDef *hqspi, uint8_t *pData);

+

+/* QSPI status flag polling mode */

+HAL_StatusTypeDef     HAL_QSPI_AutoPolling   (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout);

+HAL_StatusTypeDef     HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg);

+

+/* QSPI memory-mapped mode */

+HAL_StatusTypeDef     HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg);

+

+/* Callback functions in non-blocking modes ***********************************/

+void                  HAL_QSPI_ErrorCallback        (QSPI_HandleTypeDef *hqspi);

+void                  HAL_QSPI_AbortCpltCallback    (QSPI_HandleTypeDef *hqspi);

+void                  HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);

+

+/* QSPI indirect mode */

+void                  HAL_QSPI_CmdCpltCallback      (QSPI_HandleTypeDef *hqspi);

+void                  HAL_QSPI_RxCpltCallback       (QSPI_HandleTypeDef *hqspi);

+void                  HAL_QSPI_TxCpltCallback       (QSPI_HandleTypeDef *hqspi);

+

+/* QSPI status flag polling mode */

+void                  HAL_QSPI_StatusMatchCallback  (QSPI_HandleTypeDef *hqspi);

+

+/* QSPI memory-mapped mode */

+void                  HAL_QSPI_TimeOutCallback      (QSPI_HandleTypeDef *hqspi);

+

+#if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1)

+/* QSPI callback registering/unregistering */

+HAL_StatusTypeDef     HAL_QSPI_RegisterCallback     (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId, pQSPI_CallbackTypeDef pCallback);

+HAL_StatusTypeDef     HAL_QSPI_UnRegisterCallback   (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackId);

+#endif

+/**

+  * @}

+  */

+

+/** @addtogroup QSPI_Exported_Functions_Group3

+  * @{

+  */

+/* Peripheral Control and State functions  ************************************/

+HAL_QSPI_StateTypeDef HAL_QSPI_GetState        (QSPI_HandleTypeDef *hqspi);

+uint32_t              HAL_QSPI_GetError        (QSPI_HandleTypeDef *hqspi);

+HAL_StatusTypeDef     HAL_QSPI_Abort           (QSPI_HandleTypeDef *hqspi);

+HAL_StatusTypeDef     HAL_QSPI_Abort_IT        (QSPI_HandleTypeDef *hqspi);

+void                  HAL_QSPI_SetTimeout      (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);

+HAL_StatusTypeDef     HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);

+uint32_t              HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);

+HAL_StatusTypeDef     HAL_QSPI_SetFlashID      (QSPI_HandleTypeDef *hqspi, uint32_t FlashID);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+/* End of exported functions -------------------------------------------------*/

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup QSPI_Private_Macros QSPI Private Macros

+  * @{

+  */

+#define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU)

+

+#define IS_QSPI_FIFO_THRESHOLD(THR)        (((THR) > 0U) && ((THR) <= 32U))

+

+#define IS_QSPI_SSHIFT(SSHIFT)             (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \

+                                            ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE))

+

+#define IS_QSPI_FLASH_SIZE(FSIZE)          (((FSIZE) <= 31U))

+

+#define IS_QSPI_CS_HIGH_TIME(CSHTIME)      (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \

+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \

+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \

+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \

+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \

+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \

+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \

+                                            ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE))

+

+#define IS_QSPI_CLOCK_MODE(CLKMODE)        (((CLKMODE) == QSPI_CLOCK_MODE_0) || \

+                                            ((CLKMODE) == QSPI_CLOCK_MODE_3))

+

+#define IS_QSPI_FLASH_ID(FLASH_ID)         (((FLASH_ID) == QSPI_FLASH_ID_1) || \

+                                            ((FLASH_ID) == QSPI_FLASH_ID_2))

+

+#define IS_QSPI_DUAL_FLASH_MODE(MODE)      (((MODE) == QSPI_DUALFLASH_ENABLE) || \

+                                            ((MODE) == QSPI_DUALFLASH_DISABLE))

+

+#define IS_QSPI_INSTRUCTION(INSTRUCTION)   ((INSTRUCTION) <= 0xFFU)

+

+#define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE)    (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS)  || \

+                                            ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \

+                                            ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \

+                                            ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS))

+

+#define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS)  || \

+                                            ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \

+                                            ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \

+                                            ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS))

+

+#define IS_QSPI_DUMMY_CYCLES(DCY)          ((DCY) <= 31U)

+

+#define IS_QSPI_INSTRUCTION_MODE(MODE)     (((MODE) == QSPI_INSTRUCTION_NONE)    || \

+                                            ((MODE) == QSPI_INSTRUCTION_1_LINE)  || \

+                                            ((MODE) == QSPI_INSTRUCTION_2_LINES) || \

+                                            ((MODE) == QSPI_INSTRUCTION_4_LINES))

+

+#define IS_QSPI_ADDRESS_MODE(MODE)         (((MODE) == QSPI_ADDRESS_NONE)    || \

+                                            ((MODE) == QSPI_ADDRESS_1_LINE)  || \

+                                            ((MODE) == QSPI_ADDRESS_2_LINES) || \

+                                            ((MODE) == QSPI_ADDRESS_4_LINES))

+

+#define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE)    || \

+                                            ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE)  || \

+                                            ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \

+                                            ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES))

+

+#define IS_QSPI_DATA_MODE(MODE)            (((MODE) == QSPI_DATA_NONE)    || \

+                                            ((MODE) == QSPI_DATA_1_LINE)  || \

+                                            ((MODE) == QSPI_DATA_2_LINES) || \

+                                            ((MODE) == QSPI_DATA_4_LINES))

+

+#define IS_QSPI_DDR_MODE(DDR_MODE)         (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \

+                                            ((DDR_MODE) == QSPI_DDR_MODE_ENABLE))

+

+#define IS_QSPI_DDR_HHC(DDR_HHC)           (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \

+                                            ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY))

+

+#define IS_QSPI_SIOO_MODE(SIOO_MODE)       (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \

+                                            ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD))

+

+#define IS_QSPI_INTERVAL(INTERVAL)         ((INTERVAL) <= QUADSPI_PIR_INTERVAL)

+

+#define IS_QSPI_STATUS_BYTES_SIZE(SIZE)    (((SIZE) >= 1U) && ((SIZE) <= 4U))

+

+#define IS_QSPI_MATCH_MODE(MODE)           (((MODE) == QSPI_MATCH_MODE_AND) || \

+                                            ((MODE) == QSPI_MATCH_MODE_OR))

+

+#define IS_QSPI_AUTOMATIC_STOP(APMS)       (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \

+                                            ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE))

+

+#define IS_QSPI_TIMEOUT_ACTIVATION(TCEN)   (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \

+                                            ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE))

+

+#define IS_QSPI_TIMEOUT_PERIOD(PERIOD)     ((PERIOD) <= 0xFFFFU)

+/**

+* @}

+*/

+/* End of private macros -----------------------------------------------------*/

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_QSPI_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_ramecc.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_ramecc.h
new file mode 100644
index 0000000000..0627d39807
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_ramecc.h
@@ -0,0 +1,358 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_ramecc.h

+  * @author  MCD Application Team

+  * @brief   Header file of RAMECC HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_RAMECC_H

+#define STM32H7xx_HAL_RAMECC_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup RAMECC

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+

+/** @defgroup RAMECC_Exported_Types RAMECC Exported Types

+  * @brief    RAMECC Exported Types

+  * @{

+  */

+

+/**

+  * @brief  HAL RAMECC State structures definition

+  */

+typedef enum

+{

+  HAL_RAMECC_STATE_RESET             = 0x00U,  /*!< RAMECC not yet initialized or disabled */

+  HAL_RAMECC_STATE_READY             = 0x01U,  /*!< RAMECC initialized and ready for use   */

+  HAL_RAMECC_STATE_BUSY              = 0x02U,  /*!< RAMECC process is ongoing              */

+  HAL_RAMECC_STATE_ERROR             = 0x03U,  /*!< RAMECC error state                     */

+}HAL_RAMECC_StateTypeDef;

+

+

+/**

+  * @brief  RAMECC handle Structure definition

+  */

+

+typedef struct __RAMECC_HandleTypeDef

+{

+  RAMECC_MonitorTypeDef           *Instance;                                                            /*!< Register base address        */

+  __IO HAL_RAMECC_StateTypeDef    State;                                                                /*!< RAMECC state                 */

+  __IO uint32_t                   ErrorCode;                                                            /*!< RAMECC Error Code            */

+  void                            (* DetectErrorCallback)( struct __RAMECC_HandleTypeDef *hramecc);     /*!< RAMECC error detect callback */

+}RAMECC_HandleTypeDef;

+

+/**

+  * @}

+  */

+

+

+/* Exported constants --------------------------------------------------------*/

+

+/** @defgroup RAMECC_Error_Codes RAMECC Error Codes

+  * @{

+  */

+#define HAL_RAMECC_ERROR_NONE              0x00000000U  /*!< RAMECC No Error         */

+#define HAL_RAMECC_ERROR_TIMEOUT           0x00000001U  /*!< RAMECC Timeout Error    */

+#define HAL_RAMECC_ERROR_BUSY              0x00000002U  /*!< RAMECC Busy Error       */

+#define HAL_RAMECC_ERROR_INVALID_CALLBACK  0x00000003U  /*!< Invalid Callback error  */

+/**

+  * @}

+  */

+

+/** @defgroup RAMECC_Interrupt RAMECC interrupts

+  * @{

+  */

+#define RAMECC_IT_GLOBAL_ID                0x10000000UL

+#define RAMECC_IT_MONITOR_ID               0x20000000UL

+

+#define RAMECC_IT_GLOBAL_ENABLE            (RAMECC_IT_GLOBAL_ID | RAMECC_IER_GIE)

+#define RAMECC_IT_GLOBAL_SINGLEERR_R       (RAMECC_IT_GLOBAL_ID | RAMECC_IER_GECCSEIE)

+#define RAMECC_IT_GLOBAL_DOUBLEERR_R       (RAMECC_IT_GLOBAL_ID | RAMECC_IER_GECCDEIE)

+#define RAMECC_IT_GLOBAL_DOUBLEERR_W       (RAMECC_IT_GLOBAL_ID | RAMECC_IER_GECCDEBWIE)

+#define RAMECC_IT_GLOBAL_ALL               (RAMECC_IT_GLOBAL_ID | RAMECC_IER_GIE | RAMECC_IER_GECCSEIE | RAMECC_IER_GECCDEIE | RAMECC_IER_GECCDEBWIE)

+

+

+#define RAMECC_IT_MONITOR_SINGLEERR_R      (RAMECC_IT_MONITOR_ID | RAMECC_CR_ECCSEIE)

+#define RAMECC_IT_MONITOR_DOUBLEERR_R      (RAMECC_IT_MONITOR_ID | RAMECC_CR_ECCDEIE)

+#define RAMECC_IT_MONITOR_DOUBLEERR_W      (RAMECC_IT_MONITOR_ID | RAMECC_CR_ECCDEBWIE)

+#define RAMECC_IT_MONITOR_ALL              (RAMECC_IT_MONITOR_ID | RAMECC_CR_ECCDEBWIE | RAMECC_CR_ECCDEIE | RAMECC_CR_ECCSEIE)

+/**

+  * @}

+  */

+

+/** @defgroup RAMECC_FLAG RAMECC Monitor flags

+  * @{

+  */

+#define RAMECC_FLAG_SINGLEERR_R            RAMECC_SR_SEDCF

+#define RAMECC_FLAG_DOUBLEERR_R            RAMECC_SR_DEDF

+#define RAMECC_FLAG_DOUBLEERR_W            RAMECC_SR_DEBWDF

+#define RAMECC_FLAGS_ALL                   (RAMECC_SR_SEDCF | RAMECC_SR_DEDF | RAMECC_SR_DEBWDF)

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup RAMECC_Exported_Macros RAMECC Exported Macros

+  * @{

+  */

+

+#define __HAL_RAMECC_ENABLE_GLOBAL_IT(__HANDLE__, __INTERRUPT__) ((((RAMECC_TypeDef *)((uint32_t)(__HANDLE__)->Instance & 0xFFFFFF00U))->IER) |= ((__INTERRUPT__) & ~RAMECC_IT_GLOBAL_ID))

+#define __HAL_RAMECC_ENABLE_MONITOR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= ((__INTERRUPT__) & ~RAMECC_IT_MONITOR_ID))

+

+/**

+  * @brief  Enable the specified RAMECC interrupts.

+  * @param  __HANDLE__   : RAMECC handle.

+  * @param  __INTERRUPT__: specifies the RAMECC interrupt sources to be enabled or disabled.

+  *        This parameter can be one of the following values:

+  *           @arg RAMECC_IT_GLOBAL_E      : Global interrupt enable mask.

+  *           @arg RAMECC_IT_GLOBAL_SEE    : Global ECC single error interrupt enable.

+  *           @arg RAMECC_IT_GLOBAL_DEE    : Global ECC double error interrupt enable.

+  *           @arg RAMECC_IT_GLOBAL_DEBWE  : Global ECC double error on byte write (BW) interrupt enable.

+  *           @arg RAMECC_IT_GLOBAL_ALL    : All Global ECC interrupts enable mask.

+  *           @arg RAMECC_IT_MONITOR_SEE   : Monitor ECC single error interrupt enable.

+  *           @arg RAMECC_IT_MONITOR_DEE   : Monitor ECC double error interrupt enable.

+  *           @arg RAMECC_IT_MONITOR_DEBWE : Monitor ECC double error on byte write (BW) interrupt enable.

+  *           @arg RAMECC_IT_MONITOR_ALL   : All Monitor ECC interrupts enable mask.

+  * @retval None

+  */

+#define __HAL_RAMECC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ( \

+(IS_RAMECC_GLOBAL_INTERRUPT(__INTERRUPT__)) ? (__HAL_RAMECC_ENABLE_GLOBAL_IT((__HANDLE__), (__INTERRUPT__))) :\

+(__HAL_RAMECC_ENABLE_MONITOR_IT((__HANDLE__), (__INTERRUPT__))))

+

+

+#define __HAL_RAMECC_DISABLE_GLOBAL_IT(__HANDLE__, __INTERRUPT__) ((((RAMECC_TypeDef *)((uint32_t)(__HANDLE__)->Instance & 0xFFFFFF00U))->IER) &= ~((__INTERRUPT__) & ~RAMECC_IT_GLOBAL_ID))

+#define __HAL_RAMECC_DISABLE_MONITOR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~((__INTERRUPT__) & ~RAMECC_IT_MONITOR_ID))

+

+/**

+  * @brief  Disable the specified RAMECC interrupts.

+  * @param  __HANDLE__   : RAMECC handle.

+  * @param  __INTERRUPT__: specifies the RAMECC interrupt sources to be enabled or disabled.

+  *        This parameter can be one of the following values:

+  *           @arg RAMECC_IT_GLOBAL_E      : Global interrupt enable mask.

+  *           @arg RAMECC_IT_GLOBAL_SEE    : Global ECC single error interrupt enable.

+  *           @arg RAMECC_IT_GLOBAL_DEE    : Global ECC double error interrupt enable.

+  *           @arg RAMECC_IT_GLOBAL_DEBWE  : Global ECC double error on byte write (BW) interrupt enable.

+  *           @arg RAMECC_IT_GLOBAL_ALL    : All Global ECC interrupts enable mask.

+  *           @arg RAMECC_IT_MONITOR_SEE   : Monitor ECC single error interrupt enable.

+  *           @arg RAMECC_IT_MONITOR_DEE   : Monitor ECC double error interrupt enable.

+  *           @arg RAMECC_IT_MONITOR_DEBWE : Monitor ECC double error on byte write (BW) interrupt enable.

+  *           @arg RAMECC_IT_MONITOR_ALL   : All Monitor ECC interrupts enable mask.

+  * @retval None

+  */

+#define __HAL_RAMECC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ( \

+(IS_RAMECC_GLOBAL_INTERRUPT(__INTERRUPT__)) ? (__HAL_RAMECC_DISABLE_GLOBAL_IT((__HANDLE__), (__INTERRUPT__))) :\

+(__HAL_RAMECC_DISABLE_MONITOR_IT((__HANDLE__), (__INTERRUPT__))))

+

+

+#define __HAL_RAMECC_GET_GLOBAL_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((RAMECC_TypeDef *)((uint32_t)(__HANDLE__)->Instance & 0xFFFFFF00U))->IER) & ((__INTERRUPT__) & ~RAMECC_IT_GLOBAL_ID)) ? SET : RESET)

+#define __HAL_RAMECC_GET_MONITOR_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR) & ((__INTERRUPT__) & ~RAMECC_IT_GLOBAL_ID)) ? SET : RESET)

+

+/**

+  * @brief  Check whether the specified RAMECC interrupt source is enabled or not.

+  * @param  __HANDLE__    : Specifies the RAMECC Handle.

+  * @param  __INTERRUPT__ : Specifies the RAMECC interrupt source to check.

+  *          This parameter can be one of the following values:

+  *           @arg RAMECC_IT_GLOBAL_E      : Global interrupt enable mask.

+  *           @arg RAMECC_IT_GLOBAL_SEE    : Global ECC single error interrupt enable.

+  *           @arg RAMECC_IT_GLOBAL_DEE    : Global ECC double error interrupt enable.

+  *           @arg RAMECC_IT_GLOBAL_DEBWE  : Global ECC double error on byte write (BW) interrupt enable.

+  *           @arg RAMECC_IT_GLOBAL_ALL    : All Global ECC interrupts enable mask.

+  *           @arg RAMECC_IT_MONITOR_SEE   : Monitor ECC single error interrupt enable.

+  *           @arg RAMECC_IT_MONITOR_DEE   : Monitor ECC double error interrupt enable.

+  *           @arg RAMECC_IT_MONITOR_DEBWE : Monitor ECC double error on byte write (BW) interrupt enable.

+  *           @arg RAMECC_IT_MONITOR_ALL   : All Monitor ECC interrupts enable mask.

+  * @retval The new state of __INTERRUPT__ (SET or RESET).

+  */

+#define __HAL_RAMECC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (  \

+(IS_RAMECC_GLOBAL_INTERRUPT(__INTERRUPT__)) ? (__HAL_RAMECC_GET_GLOBAL_IT_SOURCE((__HANDLE__), (__INTERRUPT__))) :\

+(__HAL_RAMECC_GET_MONITOR_IT_SOURCE((__HANDLE__), (__INTERRUPT__))))

+

+

+/**

+  * @brief  Get the RAMECC pending flags.

+  * @param  __HANDLE__   : RAMECC handle.

+  * @param  __FLAG__     : specifies the flag to clear.

+  *          This parameter can be any combination of the following values:

+  *            @arg RAMECC_FLAG_SEDCF  : RAMECC instance ECC single error detected and corrected flag.

+  *            @arg RAMECC_FLAG_DEDF   : RAMECC instance ECC double error detected flag.

+  *            @arg RAMECC_FLAG_DEBWDF : RAMECC instance ECC double error on byte write (BW) detected flag.

+  *            @arg RAMECC_FLAGS_ALL   : RAMECC instance all flag.

+  * @retval The state of __FLAG__ (SET or RESET).

+  */

+#define __HAL_RAMECC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= (__FLAG__))

+

+

+/**

+  * @brief  Clear the RAMECC pending flags.

+  * @param  __HANDLE__   : RAMECC handle.

+  * @param  __FLAG__     : specifies the flag to clear.

+  *          This parameter can be any combination of the following values:

+  *            @arg RAMECC_FLAG_SEDCF  : RAMECC instance ECC single error detected and corrected flag.

+  *            @arg RAMECC_FLAG_DEDF   : RAMECC instance ECC double error detected flag.

+  *            @arg RAMECC_FLAG_DEBWDF : RAMECC instance ECC double error on byte write (BW) detected flag.

+  *            @arg RAMECC_FLAGS_ALL   : RAMECC instance all flag.

+  * @retval None.

+  */

+#define __HAL_RAMECC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR &= ~(__FLAG__))

+

+/**

+  * @brief  Reset the RAMECC handle state.

+  * @param  __HANDLE__    : Specifies the RAMECC Handle.

+  * @retval None.

+  */

+#define __HAL_RAMECC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RAMECC_STATE_RESET)

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+

+/** @defgroup RAMECC_Exported_Functions RAMECC Exported Functions

+  * @brief    RAMECC Exported functions

+  * @{

+  */

+

+/** @defgroup RAMECC_Exported_Functions_Group1 Initialization and de-initialization functions

+  * @brief    Initialization and de-initialization functions

+  * @{

+  */

+HAL_StatusTypeDef HAL_RAMECC_Init   (RAMECC_HandleTypeDef *hramecc);

+HAL_StatusTypeDef HAL_RAMECC_DeInit (RAMECC_HandleTypeDef *hramecc);

+/**

+  * @}

+  */

+

+/** @defgroup RAMECC_Exported_Functions_Group2 monitoring operation functions

+  * @brief    monitoring operation functions

+  * @{

+  */

+HAL_StatusTypeDef HAL_RAMECC_StartMonitor        (RAMECC_HandleTypeDef *hramecc);

+HAL_StatusTypeDef HAL_RAMECC_StopMonitor         (RAMECC_HandleTypeDef *hramecc);

+HAL_StatusTypeDef HAL_RAMECC_EnableNotification  (RAMECC_HandleTypeDef *hramecc, uint32_t Notifications);

+HAL_StatusTypeDef HAL_RAMECC_DisableNotification (RAMECC_HandleTypeDef *hramecc, uint32_t Notifications);

+void              HAL_RAMECC_IRQHandler          (RAMECC_HandleTypeDef *hramecc);

+HAL_StatusTypeDef HAL_RAMECC_RegisterCallback    (RAMECC_HandleTypeDef *hramecc, void (* pCallback)(RAMECC_HandleTypeDef *_hramecc));

+HAL_StatusTypeDef HAL_RAMECC_UnRegisterCallback  (RAMECC_HandleTypeDef *hramecc);

+/**

+  * @}

+  */

+

+/** @defgroup RAMECC_Exported_Functions_Group3 Error informations functions

+  * @brief    Error informations functions

+  * @{

+  */

+uint32_t HAL_RAMECC_GetFailingAddress        (RAMECC_HandleTypeDef *hramecc);

+uint32_t HAL_RAMECC_GetFailingDataLow        (RAMECC_HandleTypeDef *hramecc);

+uint32_t HAL_RAMECC_GetFailingDataHigh       (RAMECC_HandleTypeDef *hramecc);

+uint32_t HAL_RAMECC_GetHammingErrorCode      (RAMECC_HandleTypeDef *hramecc);

+uint32_t HAL_RAMECC_IsECCSingleErrorDetected (RAMECC_HandleTypeDef *hramecc);

+uint32_t HAL_RAMECC_IsECCDoubleErrorDetected (RAMECC_HandleTypeDef *hramecc);

+/**

+  * @}

+  */

+

+/** @defgroup RAMECC_Exported_Functions_Group3 Error informations functions

+  * @brief    Error informations functions

+  * @{

+  */

+HAL_RAMECC_StateTypeDef HAL_RAMECC_GetState (RAMECC_HandleTypeDef *hramecc);

+uint32_t                HAL_RAMECC_GetError (RAMECC_HandleTypeDef *hramecc);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+/* Private Constants -------------------------------------------------------------*/

+/** @defgroup RAMECC_Private_Constants RAMECC Private Constants

+  * @brief    RAMECC private defines and constants

+  * @{

+  */

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup RAMECC_Private_Macros RAMECC Private Macros

+  * @brief    RAMECC private macros

+  * @{

+  */

+

+#define IS_RAMECC_GLOBAL_INTERRUPT(INTERRUPT) (((INTERRUPT) == RAMECC_IT_GLOBAL_ENABLE)      || \

+                                               ((INTERRUPT) == RAMECC_IT_GLOBAL_SINGLEERR_R) || \

+                                               ((INTERRUPT) == RAMECC_IT_GLOBAL_DOUBLEERR_R) || \

+                                               ((INTERRUPT) == RAMECC_IT_GLOBAL_DOUBLEERR_W) || \

+                                               ((INTERRUPT) == RAMECC_IT_GLOBAL_ALL))

+

+

+#define IS_RAMECC_MONITOR_INTERRUPT(INTERRUPT) (((INTERRUPT) == RAMECC_IT_MONITOR_SINGLEERR_R) || \

+                                                ((INTERRUPT) == RAMECC_IT_MONITOR_DOUBLEERR_R) || \

+                                                ((INTERRUPT) == RAMECC_IT_MONITOR_DOUBLEERR_W) || \

+                                                ((INTERRUPT) == RAMECC_IT_MONITOR_ALL))

+

+#define IS_RAMECC_INTERRUPT(INTERRUPT) ((IS_RAMECC_GLOBAL_INTERRUPT(INTERRUPT)) || \

+                                        (IS_RAMECC_MONITOR_INTERRUPT(INTERRUPT)))

+

+/**

+  * @}

+  */

+

+/** @defgroup RAMECC_FLAG RAMECC Monitor flags

+  * @{

+  */

+

+/* Private functions ---------------------------------------------------------*/

+/** @defgroup RAMECC_Private_Functions RAMECC Private Functions

+  * @brief    RAMECC private  functions

+  * @{

+  */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_RAMECC_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_rcc.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_rcc.h
new file mode 100644
index 0000000000..ceb86440a2
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_rcc.h
@@ -0,0 +1,7973 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_rcc.h

+  * @author  MCD Application Team

+  * @brief   Header file of RCC HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_RCC_H

+#define STM32H7xx_HAL_RCC_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup RCC

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+

+/** @defgroup RCC_Exported_Types RCC Exported Types

+  * @{

+  */

+

+/**

+  * @brief  RCC PLL configuration structure definition

+  */

+typedef struct

+{

+  uint32_t PLLState;   /*!< The new state of the PLL.

+                            This parameter can be a value of @ref RCC_PLL_Config                      */

+

+  uint32_t PLLSource;  /*!< RCC_PLLSource: PLL entry clock source.

+                            This parameter must be a value of @ref RCC_PLL_Clock_Source               */

+

+  uint32_t PLLM;       /*!< PLLM: Division factor for PLL VCO input clock.

+                            This parameter must be a number between Min_Data = 1 and Max_Data = 63    */

+

+  uint32_t PLLN;       /*!< PLLN: Multiplication factor for PLL VCO output clock.

+                            This parameter must be a number between Min_Data = 4 and Max_Data = 512 

+                            or between Min_Data = 8 and Max_Data = 420(*)

+                            (*) : For stm32h7a3xx and stm32h7b3xx family lines.                       */                        

+

+  uint32_t PLLP;       /*!< PLLP: Division factor for system clock.

+                            This parameter must be a number between Min_Data = 2 and Max_Data = 128

+                          odd division factors are not allowed                                        */

+

+  uint32_t PLLQ;       /*!< PLLQ: Division factor for peripheral clocks.

+                            This parameter must be a number between Min_Data = 1 and Max_Data = 128   */

+

+  uint32_t PLLR;       /*!< PLLR: Division factor for peripheral clocks.

+                            This parameter must be a number between Min_Data = 1 and Max_Data = 128   */

+  uint32_t PLLRGE;     /*!<PLLRGE: PLL1 clock Input range

+                         This parameter must be a value of @ref RCC_PLL1_VCI_Range                    */

+  uint32_t PLLVCOSEL;  /*!<PLLVCOSEL: PLL1 clock Output range

+                         This parameter must be a value of @ref RCC_PLL1_VCO_Range                    */

+

+  uint32_t PLLFRACN;   /*!<PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for

+                        PLL1 VCO It should be a value between 0 and 8191                              */

+

+}RCC_PLLInitTypeDef;

+

+/**

+  * @brief  RCC Internal/External Oscillator (HSE, HSI, CSI, LSE and LSI) configuration structure definition

+  */

+typedef struct

+{

+  uint32_t OscillatorType;       /*!< The oscillators to be configured.

+                                      This parameter can be a value of @ref RCC_Oscillator_Type                   */

+

+  uint32_t HSEState;             /*!< The new state of the HSE.

+                                      This parameter can be a value of @ref RCC_HSE_Config                        */

+

+  uint32_t LSEState;             /*!< The new state of the LSE.

+                                      This parameter can be a value of @ref RCC_LSE_Config                        */

+

+  uint32_t HSIState;             /*!< The new state of the HSI.

+                                      This parameter can be a value of @ref RCC_HSI_Config                        */

+

+  uint32_t HSICalibrationValue;  /*!< The calibration trimming value.

+                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F for STM32H7 rev.Y

+                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F for STM32H7 rev.B and above */

+

+  uint32_t LSIState;             /*!< The new state of the LSI.

+                                      This parameter can be a value of @ref RCC_LSI_Config                        */

+

+ uint32_t HSI48State;            /*!< The new state of the HSI48.

+                                      This parameter can be a value of @ref RCC_HSI48_Config                      */

+

+  uint32_t CSIState;             /*!< The new state of the CSI.

+                                      This parameter can be a value of @ref RCC_CSI_Config */

+

+  uint32_t CSICalibrationValue;  /*!< The calibration trimming value.

+                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F for STM32H7 rev.Y

+                                      This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F for STM32H7 rev.B and above */

+

+  RCC_PLLInitTypeDef PLL;        /*!< PLL structure parameters                                                    */

+

+}RCC_OscInitTypeDef;

+

+/**

+  * @brief  RCC System, AHB and APB busses clock configuration structure definition

+  */

+typedef struct

+{

+  uint32_t ClockType;             /*!< The clock to be configured.

+                                       This parameter can be a value of @ref RCC_System_Clock_Type                          */

+

+  uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.

+                                       This parameter can be a value of @ref RCC_System_Clock_Source                        */

+

+  uint32_t SYSCLKDivider;         /*!< The system clock  divider. This parameter can be

+                                       a value of @ref RCC_SYS_Clock_Source                                                 */

+

+  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).

+                                       This parameter can be a value of @ref RCC_HCLK_Clock_Source                          */

+

+  uint32_t APB3CLKDivider;        /*!< The APB3 clock (D1PCLK1) divider. This clock is derived from the AHB clock (HCLK).

+                                       This parameter can be a value of @ref RCC_APB3_Clock_Source                        */

+

+  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).

+                                       This parameter can be a value of @ref RCC_APB1_Clock_Source                        */

+  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).

+                                       This parameter can be a value of @ref RCC_APB2_Clock_Source                        */

+  uint32_t APB4CLKDivider;      /*!< The APB4 clock (D3PCLK1) divider. This clock is derived from the AHB clock (HCLK).

+                                       This parameter can be a value of @ref RCC_APB4_Clock_Source                        */

+}RCC_ClkInitTypeDef;

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+

+/** @defgroup RCC_Exported_Constants RCC Exported Constants

+  * @{

+  */

+

+/** @defgroup RCC_Oscillator_Type  RCC Oscillator Type

+  * @{

+  */

+#define RCC_OSCILLATORTYPE_NONE        (0x00000000U)

+#define RCC_OSCILLATORTYPE_HSE         (0x00000001U)

+#define RCC_OSCILLATORTYPE_HSI         (0x00000002U)

+#define RCC_OSCILLATORTYPE_LSE         (0x00000004U)

+#define RCC_OSCILLATORTYPE_LSI         (0x00000008U)

+#define RCC_OSCILLATORTYPE_CSI         (0x00000010U)

+#define RCC_OSCILLATORTYPE_HSI48       (0x00000020U)

+

+/**

+  * @}

+  */

+

+/** @defgroup RCC_HSE_Config  RCC HSE Config

+  * @{

+  */

+#define RCC_HSE_OFF                    (0x00000000U)

+#define RCC_HSE_ON                     RCC_CR_HSEON

+#define RCC_HSE_BYPASS                 ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))

+#if defined(RCC_CR_HSEEXT)

+#define RCC_HSE_BYPASS_DIGITAL         ((uint32_t)(RCC_CR_HSEEXT | RCC_CR_HSEBYP | RCC_CR_HSEON))

+#endif /* RCC_CR_HSEEXT */

+

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LSE_Config  RCC LSE Config

+  * @{

+  */

+#define RCC_LSE_OFF                    (0x00000000U)

+#define RCC_LSE_ON                     RCC_BDCR_LSEON

+#define RCC_LSE_BYPASS                 ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))

+#if defined(RCC_BDCR_LSEEXT)

+#define RCC_LSE_BYPASS_DIGITAL         ((uint32_t)(RCC_BDCR_LSEEXT | RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))

+#endif /* RCC_BDCR_LSEEXT */

+

+/**

+  * @}

+  */

+

+/** @defgroup RCC_HSI_Config  RCC HSI Config

+  * @{

+  */

+#define RCC_HSI_OFF                      (0x00000000U)           /*!< HSI clock deactivation */

+#define RCC_HSI_ON                       RCC_CR_HSION                     /*!< HSI clock activation */

+

+#define RCC_HSI_DIV1                     (RCC_CR_HSIDIV_1 | RCC_CR_HSION) /*!< HSI_DIV1 clock activation */

+#define RCC_HSI_DIV2                     (RCC_CR_HSIDIV_2 | RCC_CR_HSION) /*!< HSI_DIV2 clock activation */

+#define RCC_HSI_DIV4                     (RCC_CR_HSIDIV_4 | RCC_CR_HSION) /*!< HSI_DIV4 clock activation */

+#define RCC_HSI_DIV8                     (RCC_CR_HSIDIV | RCC_CR_HSION)   /*!< HSI_DIV8 clock activation */

+

+

+#if defined(RCC_HSICFGR_HSITRIM_6)

+#define RCC_HSICALIBRATION_DEFAULT     (0x40U)         /* Default HSI calibration trimming value, for STM32H7 rev.V and above  */

+#else

+#define RCC_HSICALIBRATION_DEFAULT     (0x20U)         /* Default HSI calibration trimming value, for STM32H7 rev.Y */

+#endif

+/**

+  * @}

+  */

+

+/** @defgroup RCC_HSI48_Config  RCC HSI48 Config

+  * @{

+  */

+#define RCC_HSI48_OFF                      ((uint8_t)0x00)

+#define RCC_HSI48_ON                       ((uint8_t)0x01)

+

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LSI_Config  RCC LSI Config

+  * @{

+  */

+#define RCC_LSI_OFF                    (0x00000000U)

+#define RCC_LSI_ON                     RCC_CSR_LSION

+

+/**

+  * @}

+  */

+

+/** @defgroup RCC_CSI_Config  RCC CSI Config

+  * @{

+  */

+#define RCC_CSI_OFF                    (0x00000000U)

+#define RCC_CSI_ON                     RCC_CR_CSION

+

+#if defined(RCC_CSICFGR_CSITRIM_5)

+#define RCC_CSICALIBRATION_DEFAULT     (0x20U)         /* Default CSI calibration trimming value */

+#else

+#define RCC_CSICALIBRATION_DEFAULT     (0x10U)         /* Default CSI calibration trimming value */

+#endif /* RCC_CSICFGR_CSITRIM_5 */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_PLL_Config  RCC PLL Config

+  * @{

+  */

+#define RCC_PLL_NONE                   (0x00000000U)

+#define RCC_PLL_OFF                    (0x00000001U)

+#define RCC_PLL_ON                     (0x00000002U)

+

+/**

+  * @}

+  */

+

+

+/** @defgroup RCC_PLL_Clock_Source  RCC PLL Clock Source

+  * @{

+  */

+#define RCC_PLLSOURCE_HSI              (0x00000000U)

+#define RCC_PLLSOURCE_CSI              (0x00000001U)

+#define RCC_PLLSOURCE_HSE              (0x00000002U)

+#define RCC_PLLSOURCE_NONE             (0x00000003U)

+/**

+  * @}

+  */

+

+/** @defgroup RCC_PLL_Clock_Output  RCC PLL Clock Output

+  * @{

+  */

+#define RCC_PLL1_DIVP                RCC_PLLCFGR_DIVP1EN

+#define RCC_PLL1_DIVQ                RCC_PLLCFGR_DIVQ1EN

+#define RCC_PLL1_DIVR                RCC_PLLCFGR_DIVR1EN

+

+/**

+  * @}

+  */

+

+

+

+/** @defgroup RCC_PLL1_VCI_Range  RCC PLL1 VCI Range

+  * @{

+  */

+#define RCC_PLL1VCIRANGE_0                RCC_PLLCFGR_PLL1RGE_0       /*!< Clock range frequency between 1 and 2 MHz  */

+#define RCC_PLL1VCIRANGE_1                RCC_PLLCFGR_PLL1RGE_1       /*!< Clock range frequency between 2 and 4 MHz  */

+#define RCC_PLL1VCIRANGE_2                RCC_PLLCFGR_PLL1RGE_2       /*!< Clock range frequency between 4 and 8 MHz  */

+#define RCC_PLL1VCIRANGE_3                RCC_PLLCFGR_PLL1RGE_3       /*!< Clock range frequency between 8 and 16 MHz */

+

+

+/**

+  * @}

+  */

+

+

+/** @defgroup RCC_PLL1_VCO_Range  RCC PLL1 VCO Range

+  * @{

+  */

+#define RCC_PLL1VCOWIDE                 (0x00000000U)

+#define RCC_PLL1VCOMEDIUM               RCC_PLLCFGR_PLL1VCOSEL

+

+/**

+  * @}

+  */

+

+

+/** @defgroup RCC_System_Clock_Type  RCC System Clock Type

+  * @{

+  */

+#define RCC_CLOCKTYPE_SYSCLK           (0x00000001U)

+#define RCC_CLOCKTYPE_HCLK             (0x00000002U)

+#define RCC_CLOCKTYPE_D1PCLK1          (0x00000004U)

+#define RCC_CLOCKTYPE_PCLK1            (0x00000008U)

+#define RCC_CLOCKTYPE_PCLK2            (0x00000010U)

+#define RCC_CLOCKTYPE_D3PCLK1          (0x00000020U)

+

+/**

+  * @}

+  */

+

+/** @defgroup RCC_System_Clock_Source  RCC System Clock Source

+  * @{

+  */

+#define RCC_SYSCLKSOURCE_CSI           RCC_CFGR_SW_CSI

+#define RCC_SYSCLKSOURCE_HSI           RCC_CFGR_SW_HSI

+#define RCC_SYSCLKSOURCE_HSE           RCC_CFGR_SW_HSE

+#define RCC_SYSCLKSOURCE_PLLCLK        RCC_CFGR_SW_PLL1

+

+/**

+  * @}

+  */

+

+/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status

+  * @{

+  */

+#define RCC_SYSCLKSOURCE_STATUS_CSI    RCC_CFGR_SWS_CSI   /*!< CSI used as system clock */

+#define RCC_SYSCLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */

+#define RCC_SYSCLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */

+#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL1  /*!< PLL1 used as system clock */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_SYS_Clock_Source  RCC SYS Clock Source

+  * @{

+  */

+#if defined(RCC_D1CFGR_D1CPRE_DIV1)

+#define RCC_SYSCLK_DIV1                RCC_D1CFGR_D1CPRE_DIV1

+#define RCC_SYSCLK_DIV2                RCC_D1CFGR_D1CPRE_DIV2

+#define RCC_SYSCLK_DIV4                RCC_D1CFGR_D1CPRE_DIV4

+#define RCC_SYSCLK_DIV8                RCC_D1CFGR_D1CPRE_DIV8

+#define RCC_SYSCLK_DIV16               RCC_D1CFGR_D1CPRE_DIV16

+#define RCC_SYSCLK_DIV64               RCC_D1CFGR_D1CPRE_DIV64

+#define RCC_SYSCLK_DIV128              RCC_D1CFGR_D1CPRE_DIV128

+#define RCC_SYSCLK_DIV256              RCC_D1CFGR_D1CPRE_DIV256

+#define RCC_SYSCLK_DIV512              RCC_D1CFGR_D1CPRE_DIV512

+#else

+#define RCC_SYSCLK_DIV1                RCC_CDCFGR1_CDCPRE_DIV1

+#define RCC_SYSCLK_DIV2                RCC_CDCFGR1_CDCPRE_DIV2

+#define RCC_SYSCLK_DIV4                RCC_CDCFGR1_CDCPRE_DIV4

+#define RCC_SYSCLK_DIV8                RCC_CDCFGR1_CDCPRE_DIV8

+#define RCC_SYSCLK_DIV16               RCC_CDCFGR1_CDCPRE_DIV16

+#define RCC_SYSCLK_DIV64               RCC_CDCFGR1_CDCPRE_DIV64

+#define RCC_SYSCLK_DIV128              RCC_CDCFGR1_CDCPRE_DIV128

+#define RCC_SYSCLK_DIV256              RCC_CDCFGR1_CDCPRE_DIV256

+#define RCC_SYSCLK_DIV512              RCC_CDCFGR1_CDCPRE_DIV512

+#endif

+/**

+  * @}

+  */

+

+

+/** @defgroup RCC_HCLK_Clock_Source  RCC HCLK Clock Source

+  * @{

+  */

+#if defined(RCC_D1CFGR_HPRE_DIV1)

+#define RCC_HCLK_DIV1                RCC_D1CFGR_HPRE_DIV1

+#define RCC_HCLK_DIV2                RCC_D1CFGR_HPRE_DIV2

+#define RCC_HCLK_DIV4                RCC_D1CFGR_HPRE_DIV4

+#define RCC_HCLK_DIV8                RCC_D1CFGR_HPRE_DIV8

+#define RCC_HCLK_DIV16               RCC_D1CFGR_HPRE_DIV16

+#define RCC_HCLK_DIV64               RCC_D1CFGR_HPRE_DIV64

+#define RCC_HCLK_DIV128              RCC_D1CFGR_HPRE_DIV128

+#define RCC_HCLK_DIV256              RCC_D1CFGR_HPRE_DIV256

+#define RCC_HCLK_DIV512              RCC_D1CFGR_HPRE_DIV512

+#else

+#define RCC_HCLK_DIV1                RCC_CDCFGR1_HPRE_DIV1

+#define RCC_HCLK_DIV2                RCC_CDCFGR1_HPRE_DIV2

+#define RCC_HCLK_DIV4                RCC_CDCFGR1_HPRE_DIV4

+#define RCC_HCLK_DIV8                RCC_CDCFGR1_HPRE_DIV8

+#define RCC_HCLK_DIV16               RCC_CDCFGR1_HPRE_DIV16

+#define RCC_HCLK_DIV64               RCC_CDCFGR1_HPRE_DIV64

+#define RCC_HCLK_DIV128              RCC_CDCFGR1_HPRE_DIV128

+#define RCC_HCLK_DIV256              RCC_CDCFGR1_HPRE_DIV256

+#define RCC_HCLK_DIV512              RCC_CDCFGR1_HPRE_DIV512

+#endif

+/**

+  * @}

+  */

+

+/** @defgroup RCC_APB3_Clock_Source  RCC APB3 Clock Source

+  * @{

+  */

+#if defined (RCC_D1CFGR_D1PPRE_DIV1)

+#define RCC_APB3_DIV1                  RCC_D1CFGR_D1PPRE_DIV1

+#define RCC_APB3_DIV2                  RCC_D1CFGR_D1PPRE_DIV2

+#define RCC_APB3_DIV4                  RCC_D1CFGR_D1PPRE_DIV4

+#define RCC_APB3_DIV8                  RCC_D1CFGR_D1PPRE_DIV8

+#define RCC_APB3_DIV16                 RCC_D1CFGR_D1PPRE_DIV16

+#else

+#define RCC_APB3_DIV1                  RCC_CDCFGR1_CDPPRE_DIV1

+#define RCC_APB3_DIV2                  RCC_CDCFGR1_CDPPRE_DIV2

+#define RCC_APB3_DIV4                  RCC_CDCFGR1_CDPPRE_DIV4

+#define RCC_APB3_DIV8                  RCC_CDCFGR1_CDPPRE_DIV8

+#define RCC_APB3_DIV16                 RCC_CDCFGR1_CDPPRE_DIV16

+#endif

+/**

+  * @}

+  */

+

+/** @defgroup RCC_APB1_Clock_Source  RCC APB1 Clock Source

+  * @{

+  */

+#if defined (RCC_D2CFGR_D2PPRE1_DIV1)

+#define RCC_APB1_DIV1                  RCC_D2CFGR_D2PPRE1_DIV1

+#define RCC_APB1_DIV2                  RCC_D2CFGR_D2PPRE1_DIV2

+#define RCC_APB1_DIV4                  RCC_D2CFGR_D2PPRE1_DIV4

+#define RCC_APB1_DIV8                  RCC_D2CFGR_D2PPRE1_DIV8

+#define RCC_APB1_DIV16                 RCC_D2CFGR_D2PPRE1_DIV16

+#else

+#define RCC_APB1_DIV1                  RCC_CDCFGR2_CDPPRE1_DIV1

+#define RCC_APB1_DIV2                  RCC_CDCFGR2_CDPPRE1_DIV2

+#define RCC_APB1_DIV4                  RCC_CDCFGR2_CDPPRE1_DIV4

+#define RCC_APB1_DIV8                  RCC_CDCFGR2_CDPPRE1_DIV8

+#define RCC_APB1_DIV16                 RCC_CDCFGR2_CDPPRE1_DIV16

+#endif

+

+/**

+  * @}

+  */

+

+/** @defgroup RCC_APB2_Clock_Source  RCC APB2 Clock Source

+  * @{

+  */

+#if defined (RCC_D2CFGR_D2PPRE2_DIV1)

+#define RCC_APB2_DIV1                  RCC_D2CFGR_D2PPRE2_DIV1

+#define RCC_APB2_DIV2                  RCC_D2CFGR_D2PPRE2_DIV2

+#define RCC_APB2_DIV4                  RCC_D2CFGR_D2PPRE2_DIV4

+#define RCC_APB2_DIV8                  RCC_D2CFGR_D2PPRE2_DIV8

+#define RCC_APB2_DIV16                 RCC_D2CFGR_D2PPRE2_DIV16

+#else

+#define RCC_APB2_DIV1                  RCC_CDCFGR2_CDPPRE2_DIV1

+#define RCC_APB2_DIV2                  RCC_CDCFGR2_CDPPRE2_DIV2

+#define RCC_APB2_DIV4                  RCC_CDCFGR2_CDPPRE2_DIV4

+#define RCC_APB2_DIV8                  RCC_CDCFGR2_CDPPRE2_DIV8

+#define RCC_APB2_DIV16                 RCC_CDCFGR2_CDPPRE2_DIV16

+#endif

+/**

+  * @}

+  */

+

+/** @defgroup RCC_APB4_Clock_Source  RCC APB4 Clock Source

+  * @{

+  */

+#if defined(RCC_D3CFGR_D3PPRE_DIV1)

+#define RCC_APB4_DIV1                  RCC_D3CFGR_D3PPRE_DIV1

+#define RCC_APB4_DIV2                  RCC_D3CFGR_D3PPRE_DIV2

+#define RCC_APB4_DIV4                  RCC_D3CFGR_D3PPRE_DIV4

+#define RCC_APB4_DIV8                  RCC_D3CFGR_D3PPRE_DIV8

+#define RCC_APB4_DIV16                 RCC_D3CFGR_D3PPRE_DIV16

+#else

+#define RCC_APB4_DIV1                  RCC_SRDCFGR_SRDPPRE_DIV1

+#define RCC_APB4_DIV2                  RCC_SRDCFGR_SRDPPRE_DIV2

+#define RCC_APB4_DIV4                  RCC_SRDCFGR_SRDPPRE_DIV4

+#define RCC_APB4_DIV8                  RCC_SRDCFGR_SRDPPRE_DIV8

+#define RCC_APB4_DIV16                 RCC_SRDCFGR_SRDPPRE_DIV16

+#endif

+/**

+  * @}

+  */

+

+/** @defgroup RCC_RTC_Clock_Source  RCC RTC Clock Source

+  * @{

+  */

+#define RCC_RTCCLKSOURCE_NO_CLK          (0x00000000U)

+#define RCC_RTCCLKSOURCE_LSE             (0x00000100U)

+#define RCC_RTCCLKSOURCE_LSI             (0x00000200U)

+#define RCC_RTCCLKSOURCE_HSE_DIV2        (0x00002300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV3        (0x00003300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV4        (0x00004300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV5        (0x00005300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV6        (0x00006300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV7        (0x00007300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV8        (0x00008300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV9        (0x00009300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV10       (0x0000A300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV11       (0x0000B300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV12       (0x0000C300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV13       (0x0000D300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV14       (0x0000E300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV15       (0x0000F300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV16       (0x00010300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV17       (0x00011300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV18       (0x00012300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV19       (0x00013300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV20       (0x00014300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV21       (0x00015300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV22       (0x00016300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV23       (0x00017300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV24       (0x00018300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV25       (0x00019300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV26       (0x0001A300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV27       (0x0001B300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV28       (0x0001C300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV29       (0x0001D300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV30       (0x0001E300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV31       (0x0001F300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV32       (0x00020300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV33       (0x00021300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV34       (0x00022300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV35       (0x00023300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV36       (0x00024300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV37       (0x00025300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV38       (0x00026300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV39       (0x00027300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV40       (0x00028300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV41       (0x00029300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV42       (0x0002A300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV43       (0x0002B300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV44       (0x0002C300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV45       (0x0002D300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV46       (0x0002E300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV47       (0x0002F300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV48       (0x00030300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV49       (0x00031300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV50       (0x00032300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV51       (0x00033300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV52       (0x00034300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV53       (0x00035300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV54       (0x00036300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV55       (0x00037300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV56       (0x00038300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV57       (0x00039300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV58       (0x0003A300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV59       (0x0003B300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV60       (0x0003C300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV61       (0x0003D300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV62       (0x0003E300U)

+#define RCC_RTCCLKSOURCE_HSE_DIV63       (0x0003F300U)

+

+

+/**

+  * @}

+  */

+

+

+/** @defgroup RCC_MCO_Index  RCC MCO Index

+  * @{

+  */

+#define RCC_MCO1                         (0x00000000U)

+#define RCC_MCO2                         (0x00000001U)

+

+/**

+  * @}

+  */

+

+/** @defgroup RCC_MCO1_Clock_Source  RCC MCO1 Clock Source

+  * @{

+  */

+#define RCC_MCO1SOURCE_HSI               (0x00000000U)

+#define RCC_MCO1SOURCE_LSE               RCC_CFGR_MCO1_0

+#define RCC_MCO1SOURCE_HSE               RCC_CFGR_MCO1_1

+#define RCC_MCO1SOURCE_PLL1QCLK          ((uint32_t)RCC_CFGR_MCO1_0 | RCC_CFGR_MCO1_1)

+#define RCC_MCO1SOURCE_HSI48              RCC_CFGR_MCO1_2

+

+/**

+  * @}

+  */

+

+/** @defgroup RCC_MCO2_Clock_Source  RCC MCO2 Clock Source

+  * @{

+  */

+#define RCC_MCO2SOURCE_SYSCLK            (0x00000000U)

+#define RCC_MCO2SOURCE_PLL2PCLK          RCC_CFGR_MCO2_0

+#define RCC_MCO2SOURCE_HSE               RCC_CFGR_MCO2_1

+#define RCC_MCO2SOURCE_PLLCLK            ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_1)

+#define RCC_MCO2SOURCE_CSICLK            RCC_CFGR_MCO2_2

+#define RCC_MCO2SOURCE_LSICLK            ((uint32_t)RCC_CFGR_MCO2_0 | RCC_CFGR_MCO2_2)

+

+/**

+  * @}

+  */

+

+/** @defgroup RCC_MCOx_Clock_Prescaler  RCC MCOx Clock Prescaler

+  * @{

+  */

+#define RCC_MCODIV_1                    RCC_CFGR_MCO1PRE_0

+#define RCC_MCODIV_2                    RCC_CFGR_MCO1PRE_1

+#define RCC_MCODIV_3                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)

+#define RCC_MCODIV_4                    RCC_CFGR_MCO1PRE_2

+#define RCC_MCODIV_5                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)

+#define RCC_MCODIV_6                    ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)

+#define RCC_MCODIV_7                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)

+#define RCC_MCODIV_8                    RCC_CFGR_MCO1PRE_3

+#define RCC_MCODIV_9                    ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)

+#define RCC_MCODIV_10                   ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)

+#define RCC_MCODIV_11                   ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)

+#define RCC_MCODIV_12                   ((uint32_t)RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)

+#define RCC_MCODIV_13                   ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)

+#define RCC_MCODIV_14                   ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)

+#define RCC_MCODIV_15                   RCC_CFGR_MCO1PRE

+

+

+/**

+  * @}

+  */

+

+/** @defgroup RCC_Interrupt  RCC Interrupt

+  * @{

+  */

+#define RCC_IT_LSIRDY                  (0x00000001U)

+#define RCC_IT_LSERDY                  (0x00000002U)

+#define RCC_IT_HSIRDY                  (0x00000004U)

+#define RCC_IT_HSERDY                  (0x00000008U)

+#define RCC_IT_CSIRDY                  (0x00000010U)

+#define RCC_IT_HSI48RDY                (0x00000020U)

+#define RCC_IT_PLLRDY                  (0x00000040U)

+#define RCC_IT_PLL2RDY                 (0x00000080U)

+#define RCC_IT_PLL3RDY                 (0x00000100U)

+#define RCC_IT_LSECSS                  (0x00000200U)

+#define RCC_IT_CSS                     (0x00000400U)

+/**

+  * @}

+  */

+

+/** @defgroup RCC_Flag  RCC Flag

+  *        Elements values convention: XXXYYYYYb

+  *           - YYYYY  : Flag position in the register

+  *           - XXX  : Register index

+  *                 - 001: CR register

+  *                 - 010: BDCR register

+  *                 - 011: CSR register

+  *                 - 100: RSR register

+  * @{

+  */

+/* Flags in the CR register */

+#define RCC_FLAG_HSIRDY                ((uint8_t)0x22)

+#define RCC_FLAG_HSIDIV                ((uint8_t)0x25)

+#define RCC_FLAG_CSIRDY                ((uint8_t)0x28)

+#define RCC_FLAG_HSI48RDY              ((uint8_t)0x2D)

+#if defined(RCC_CR_D1CKRDY)

+#define RCC_FLAG_D1CKRDY               ((uint8_t)0x2E)

+#else

+#define RCC_FLAG_CPUCKRDY              ((uint8_t)0x2E)

+#define RCC_FLAG_D1CKRDY               RCC_FLAG_CPUCKRDY   /* alias */

+#endif /* RCC_CR_D1CKRDY */

+#if defined(RCC_CR_D2CKRDY)

+#define RCC_FLAG_D2CKRDY               ((uint8_t)0x2F)

+#else

+#define RCC_FLAG_CDCKRDY               ((uint8_t)0x2F)

+#define RCC_FLAG_D2CKRDY               RCC_FLAG_CDCKRDY    /* alias */

+#endif /* RCC_CR_D2CKRDY */

+#define RCC_FLAG_HSERDY                ((uint8_t)0x31)

+#define RCC_FLAG_PLLRDY                ((uint8_t)0x39)

+#define RCC_FLAG_PLL2RDY               ((uint8_t)0x3B)

+#define RCC_FLAG_PLL3RDY               ((uint8_t)0x3D)

+/* Flags in the BDCR register */

+#define RCC_FLAG_LSERDY                ((uint8_t)0x41)

+

+/* Flags in the CSR register */

+#define RCC_FLAG_LSIRDY                ((uint8_t)0x61)

+

+/* Flags in the RSR register */

+#if defined(RCC_RSR_CPURSTF)

+#define RCC_FLAG_CPURST                ((uint8_t)0x91)

+#endif /* RCC_RSR_CPURSTF */

+

+#if defined(RCC_RSR_D1RSTF)

+#define RCC_FLAG_D1RST                 ((uint8_t)0x93)

+#else

+#define RCC_FLAG_CDRST                 ((uint8_t)0x93)

+#endif /* RCC_RSR_D1RSTF */

+#if defined(RCC_RSR_D2RSTF)

+#define RCC_FLAG_D2RST                 ((uint8_t)0x94)

+#endif /* RCC_RSR_D2RSTF */

+#define RCC_FLAG_BORRST                ((uint8_t)0x95)

+#define RCC_FLAG_PINRST                ((uint8_t)0x96)

+#define RCC_FLAG_PORRST                ((uint8_t)0x97)

+#define RCC_FLAG_SFTRST                ((uint8_t)0x98)

+#define RCC_FLAG_IWDG1RST              ((uint8_t)0x9A)

+#define RCC_FLAG_WWDG1RST              ((uint8_t)0x9C)

+#define RCC_FLAG_LPWR1RST              ((uint8_t)0x9E)

+#define RCC_FLAG_LPWR2RST              ((uint8_t)0x9F)

+

+#if defined(DUAL_CORE)

+#define RCC_FLAG_C1RST                 (RCC_FLAG_CPURST)

+#define RCC_FLAG_C2RST                 ((uint8_t)0x92)

+#define RCC_FLAG_SFTR1ST               (RCC_FLAG_SFTRST)

+#define RCC_FLAG_SFTR2ST               ((uint8_t)0x99)

+#define RCC_FLAG_WWDG2RST              ((uint8_t)0x9D)

+#define RCC_FLAG_IWDG2RST              ((uint8_t)0x9B)

+#endif /*DUAL_CORE*/

+

+

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LSEDrive_Config LSE Drive Config

+  * @{

+  */

+#define RCC_LSEDRIVE_LOW                 (0x00000000U) /*!< LSE low drive capability */

+#define RCC_LSEDRIVE_MEDIUMLOW           RCC_BDCR_LSEDRV_0      /*!< LSE medium low drive capability */

+#define RCC_LSEDRIVE_MEDIUMHIGH          RCC_BDCR_LSEDRV_1      /*!< LSE medium high drive capability */

+#define RCC_LSEDRIVE_HIGH                RCC_BDCR_LSEDRV        /*!< LSE high drive capability */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_Stop_WakeUpClock  RCC Stop WakeUpClock

+  * @{

+  */

+#define RCC_STOP_WAKEUPCLOCK_HSI       (0x00000000U)

+#define RCC_STOP_WAKEUPCLOCK_CSI       RCC_CFGR_STOPWUCK

+

+/**

+  * @}

+  */

+

+/** @defgroup RCC_Stop_KernelWakeUpClock  RCC Stop KernelWakeUpClock

+  * @{

+  */

+#define RCC_STOP_KERWAKEUPCLOCK_HSI       (0x00000000U)

+#define RCC_STOP_KERWAKEUPCLOCK_CSI        RCC_CFGR_STOPKERWUCK

+

+

+/**

+  * @}

+  */

+

+#if defined(RCC_VER_X)

+#define HAL_RCC_REV_Y_HSITRIM_Pos  (12U)

+#define HAL_RCC_REV_Y_HSITRIM_Msk  (0x3F000U)

+#define HAL_RCC_REV_Y_CSITRIM_Pos  (26U)

+#define HAL_RCC_REV_Y_CSITRIM_Msk  (0x7C000000U)

+#endif /* RCC_VER_X */

+

+/**

+  * @}

+  */

+

+/* Exported macros -----------------------------------------------------------*/

+

+/** @defgroup RCC_Exported_Macros RCC Exported Macros

+  * @{

+  */

+

+/** @brief  Enable or disable the AHB3 peripheral clock.

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+#define __HAL_RCC_MDMA_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_MDMAEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_DMA2D_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#if defined(JPEG)

+#define __HAL_RCC_JPGDECEN_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /* JPEG */

+

+#define __HAL_RCC_FMC_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#if defined(QUADSPI)

+#define __HAL_RCC_QSPI_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /* QUADSPI */

+#if defined(OCTOSPI1)

+#define __HAL_RCC_OSPI1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /* OCTOSPI1 */

+#if defined(OCTOSPI2)

+#define __HAL_RCC_OSPI2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OSPI2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /* OCTOSPI2 */

+#if defined(OCTOSPIM)

+#define __HAL_RCC_OCTOSPIM_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_IOMNGREN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /* OCTOSPIM */

+#if defined(OTFDEC1)

+#define __HAL_RCC_OTFDEC1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /* OTFDEC1 */

+#if defined(OTFDEC2)

+#define __HAL_RCC_OTFDEC2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_OTFDEC2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /* OTFDEC2 */

+#if defined(GFXMMU)

+#define __HAL_RCC_GFXMMU_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GFXMMUEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /* GFXMMU */

+#define __HAL_RCC_SDMMC1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+

+#define __HAL_RCC_MDMA_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))

+#define __HAL_RCC_DMA2D_CLK_DISABLE()           (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))

+#if defined(JPEG)

+#define __HAL_RCC_JPGDECEN_CLK_DISABLE()        (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))

+#endif /* JPEG */

+#define __HAL_RCC_FMC_CLK_DISABLE()             (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))

+

+#if defined(QUADSPI)

+#define __HAL_RCC_QSPI_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))

+#endif /* QUADSPI */

+#if defined(OCTOSPI1)

+#define __HAL_RCC_OSPI1_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI1EN))

+#endif /* OCTOSPII */

+#if defined(OCTOSPI2)

+#define __HAL_RCC_OSPI2_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OSPI2EN))

+#endif /* OCTOSPI2 */

+#define __HAL_RCC_SDMMC1_CLK_DISABLE()          (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))

+#if defined(OCTOSPIM)

+#define __HAL_RCC_OCTOSPIM_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_IOMNGREN))

+#endif /* OCTOSPIM */

+#if defined(OTFDEC1)

+#define __HAL_RCC_OTFDEC1_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC1EN))

+#endif /* OTOFDEC1 */

+#if defined(OTFDEC2)

+#define __HAL_RCC_OTFDEC2_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_OTFDEC2EN))

+#endif /* OTOFDEC2 */

+#if defined(GFXMMU)

+#define __HAL_RCC_GFXMMU_CLK_DISABLE()            (RCC->AHB3ENR &= ~ (RCC_AHB3ENR_GFXMMUEN))

+#endif /* GFXMMU */

+

+/** @brief  Get the enable or disable status of the AHB3 peripheral clock

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+

+#define __HAL_RCC_MDMA_IS_CLK_ENABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN)   != 0U)

+#define __HAL_RCC_DMA2D_IS_CLK_ENABLED()         ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN)  != 0U)

+#if defined(JPEG)

+#define __HAL_RCC_JPGDECEN_IS_CLK_ENABLED()      ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) != 0U)

+#endif /* JPEG */

+#define __HAL_RCC_FMC_IS_CLK_ENABLED()           ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN)    != 0U)

+#if defined (QUADSPI)

+#define __HAL_RCC_QSPI_IS_CLK_ENABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN)   != 0U)

+#endif /* QUADSPI */

+#if defined(OCTOSPI1)

+#define __HAL_RCC_OSPI1_IS_CLK_ENABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN)   != 0U)

+#endif /* OCTOSPII */

+#if defined(OCTOSPI2)

+#define __HAL_RCC_OSPI2_IS_CLK_ENABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN)   != 0U)

+#endif /* OCTOSPI2 */

+#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) != 0U)

+#if defined(OCTOSPIM)

+#define __HAL_RCC_OCTOSPIM_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) != 0U)

+#endif /* OCTOSPIM */

+#if defined(OTFDEC1)

+#define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) != 0U)

+#endif /* OTOFDEC1 */

+#if defined(OTFDEC2)

+#define __HAL_RCC_OTFDEC2_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) != 0U)

+#endif /* OTOFDEC2 */

+#if defined(GFXMMU)

+#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) != 0U)

+#endif /* GFXMMU */

+

+#define __HAL_RCC_MDMA_IS_CLK_DISABLED()         ((RCC->AHB3ENR & RCC_AHB3ENR_MDMAEN)   == 0U)

+#define __HAL_RCC_DMA2D_IS_CLK_DISABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_DMA2DEN)  == 0U)

+#if defined(JPEG)

+#define __HAL_RCC_JPGDECEN_IS_CLK_DISABLED()     ((RCC->AHB3ENR & RCC_AHB3ENR_JPGDECEN) == 0U)

+#endif /* JPEG */

+#define __HAL_RCC_FMC_IS_CLK_DISABLED()          ((RCC->AHB3ENR & RCC_AHB3ENR_FMCEN)    == 0U)

+#if defined (QUADSPI)

+#define __HAL_RCC_QSPI_IS_CLK_DISABLED()         ((RCC->AHB3ENR & RCC_AHB3ENR_QSPIEN)   == 0U)

+#endif /* QUADSPI */

+#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED()       ((RCC->AHB3ENR & RCC_AHB3ENR_SDMMC1EN) == 0U)

+#if defined(OCTOSPI1)

+#define __HAL_RCC_OSPI1_IS_CLK_DISABLED()        ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI1EN) == 0U)

+#endif

+#if defined(OCTOSPI2)

+#define __HAL_RCC_OSPI2_IS_CLK_DISABLED()     ((RCC->AHB3ENR & RCC_AHB3ENR_OSPI2EN) == 0U)

+#endif

+#if defined(OCTOSPIM)

+#define __HAL_RCC_OCTOSPIM_IS_CLK_DISABLED()     ((RCC->AHB3ENR & RCC_AHB3ENR_IOMNGREN) == 0U)

+#endif

+#if defined(OTFDEC1)

+#define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED()      ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC1EN) == 0U)

+#endif

+#if defined(OTFDEC2)

+#define __HAL_RCC_OTFDEC2_IS_CLK_DISABLED()      ((RCC->AHB3ENR & RCC_AHB3ENR_OTFDEC2EN) == 0U)

+#endif

+#if defined(GFXMMU)

+#define __HAL_RCC_GFXMMU_IS_CLK_DISABLED()       ((RCC->AHB3ENR & RCC_AHB3ENR_GFXMMUEN) == 0U)

+#endif

+/** @brief  Enable or disable the AHB1 peripheral clock.

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+

+#define __HAL_RCC_DMA1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_DMA2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_ADC12_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ADC12EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#if defined(DUAL_CORE)

+#define __HAL_RCC_ART_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ARTEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /*DUAL_CORE*/

+

+#if defined(RCC_AHB1ENR_CRCEN)

+#define __HAL_RCC_CRC_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif

+

+#if defined(ETH)

+#define __HAL_RCC_ETH1MAC_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_ETH1TX_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_ETH1RX_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif

+

+#define __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#if defined(USB2_OTG_FS)

+#define __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif

+

+#define __HAL_RCC_DMA1_CLK_DISABLE()             (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))

+#define __HAL_RCC_DMA2_CLK_DISABLE()             (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))

+#define __HAL_RCC_ADC12_CLK_DISABLE()            (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))

+#if defined(DUAL_CORE)

+#define __HAL_RCC_ART_CLK_DISABLE()              (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))

+#endif /*DUAL_CORE*/

+#if defined(RCC_AHB1ENR_CRCEN)

+#define __HAL_RCC_CRC_CLK_DISABLE()              (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_CRCEN))

+#endif

+#if defined(ETH)

+#define __HAL_RCC_ETH1MAC_CLK_DISABLE()          (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))

+#define __HAL_RCC_ETH1TX_CLK_DISABLE()           (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))

+#define __HAL_RCC_ETH1RX_CLK_DISABLE()           (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))

+#endif

+#define __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()      (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))

+#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))

+#if defined(USB2_OTG_FS)

+#define __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()      (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))

+#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))

+#endif /* USB2_OTG_FS */

+

+/** @brief  Get the enable or disable status of the AHB1 peripheral clock

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+

+#define __HAL_RCC_DMA1_IS_CLK_ENABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN)          != 0U)

+#define __HAL_RCC_DMA2_IS_CLK_ENABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN)          != 0U)

+#define __HAL_RCC_ADC12_IS_CLK_ENABLED()             ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN)         != 0U)

+#if defined(DUAL_CORE)

+#define __HAL_RCC_ART_IS_CLK_ENABLED()               ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN)           != 0U)

+#endif /*DUAL_CORE*/

+#if defined(RCC_AHB1ENR_CRCEN)

+#define __HAL_RCC_CRC_IS_CLK_ENABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN)       != 0U)

+#endif

+#if defined(ETH)

+#define __HAL_RCC_ETH1MAC_IS_CLK_ENABLED()           ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN)       != 0U)

+#define __HAL_RCC_ETH1TX_IS_CLK_ENABLED()            ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN)        != 0U)

+#define __HAL_RCC_ETH1RX_IS_CLK_ENABLED()            ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN)        != 0U)

+#endif

+#define __HAL_RCC_USB1_OTG_HS_IS_CLK_ENABLED()       ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN)     != 0U)

+#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_ENABLED()  ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) != 0U)

+#if defined(USB2_OTG_FS)

+#define __HAL_RCC_USB2_OTG_FS_IS_CLK_ENABLED()       ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN)     != 0U)

+#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_ENABLED()  ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) != 0U)

+#endif /* USB2_OTG_FS */

+

+#define __HAL_RCC_DMA1_IS_CLK_DISABLED()             ((RCC->AHB1ENR & RCC_AHB1ENR_DMA1EN)          == 0U)

+#define __HAL_RCC_DMA2_IS_CLK_DISABLED()             ((RCC->AHB1ENR & RCC_AHB1ENR_DMA2EN)          == 0U)

+#define __HAL_RCC_ADC12_IS_CLK_DISABLED()            ((RCC->AHB1ENR & RCC_AHB1ENR_ADC12EN)         == 0U)

+#if defined(DUAL_CORE)

+#define __HAL_RCC_ART_IS_CLK_DISABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_ARTEN)           == 0U)

+#endif /*DUAL_CORE*/

+#if defined(RCC_AHB1ENR_CRCEN)

+#define __HAL_RCC_CRC_IS_CLK_DISABLED()              ((RCC->AHB1ENR & RCC_AHB1ENR_CRCEN)           == 0U)

+#endif

+#if defined(ETH)

+#define __HAL_RCC_ETH1MAC_IS_CLK_DISABLED()          ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1MACEN)       == 0U)

+#define __HAL_RCC_ETH1TX_IS_CLK_DISABLED()           ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1TXEN)        == 0U)

+#define __HAL_RCC_ETH1RX_IS_CLK_DISABLED()           ((RCC->AHB1ENR & RCC_AHB1ENR_ETH1RXEN)        == 0U)

+#endif

+#define __HAL_RCC_USB1_OTG_HS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSEN)     == 0U)

+#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB1OTGHSULPIEN) == 0U)

+#if defined(USB2_OTG_FS)

+#define __HAL_RCC_USB2_OTG_FS_IS_CLK_DISABLED()      ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSEN)     == 0U)

+#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & RCC_AHB1ENR_USB2OTGHSULPIEN) == 0U)

+#endif /* USB2_OTG_FS */

+

+/** @brief  Enable or disable the AHB2 peripheral clock.

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+

+#if defined(DCMI) && defined(PSSI)

+#define __HAL_RCC_DCMI_PSSI_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMI_PSSIEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_DCMI_CLK_ENABLE()  __HAL_RCC_DCMI_PSSI_CLK_ENABLE()  /* for API backward compatibility*/

+#else

+#define __HAL_RCC_DCMI_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /* DCMI && PSSI */

+

+#if defined(CRYP)

+#define __HAL_RCC_CRYP_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /* CRYP */

+

+#if defined(HASH)

+#define __HAL_RCC_HASH_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /* HASH */

+

+#define __HAL_RCC_RNG_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_SDMMC2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#if defined(RCC_AHB2ENR_D2SRAM1EN)

+#define __HAL_RCC_D2SRAM1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#else

+#define __HAL_RCC_AHBSRAM1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /* RCC_AHB2ENR_D2SRAM1EN */

+

+#if defined(RCC_AHB2ENR_D2SRAM2EN)

+#define __HAL_RCC_D2SRAM2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#else

+#define __HAL_RCC_AHBSRAM2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_AHBSRAM2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /* RCC_AHB2ENR_D2SRAM2EN */

+

+#if defined(RCC_AHB2ENR_D2SRAM3EN)

+#define __HAL_RCC_D2SRAM3_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif

+

+#if defined(RCC_AHB2ENR_HSEMEN)

+#define __HAL_RCC_HSEM_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HSEMEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /* RCC_AHB2ENR_HSEMEN */

+

+#if defined(BDMA1)

+#define __HAL_RCC_BDMA1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_BDMA1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /* BDMA1 */

+

+#if defined(DCMI) && defined(PSSI)

+#define __HAL_RCC_DCMI_PSSI_CLK_DISABLE()         (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMI_PSSIEN))

+#define __HAL_RCC_DCMI_CLK_DISABLE()              __HAL_RCC_DCMI_PSSI_CLK_DISABLE()  /* for API backward compatibility*/

+#else

+#define __HAL_RCC_DCMI_CLK_DISABLE()             (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))

+#endif /* DCMI && PSSI */

+#if defined(CRYP)

+#define __HAL_RCC_CRYP_CLK_DISABLE()             (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))

+#endif /* CRYP */

+#if defined(HASH)

+#define __HAL_RCC_HASH_CLK_DISABLE()             (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))

+#endif /* HASH */

+#define __HAL_RCC_RNG_CLK_DISABLE()              (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))

+#define __HAL_RCC_SDMMC2_CLK_DISABLE()           (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))

+#if defined(RCC_AHB2ENR_D2SRAM1EN)

+#define __HAL_RCC_D2SRAM1_CLK_DISABLE()          (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))

+#else

+#define __HAL_RCC_AHBSRAM1_CLK_DISABLE()         (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM1EN))

+#endif /* RCC_AHB2ENR_D2SRAM1EN */

+#if defined(RCC_AHB2ENR_D2SRAM2EN)

+#define __HAL_RCC_D2SRAM2_CLK_DISABLE()          (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))

+#else

+#define __HAL_RCC_AHBSRAM2_CLK_DISABLE()         (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_AHBSRAM2EN))

+#endif /* RCC_AHB2ENR_D2SRAM2EN */

+#if defined(RCC_AHB2ENR_D2SRAM3EN)

+#define __HAL_RCC_D2SRAM3_CLK_DISABLE()          (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))

+#endif

+#if defined(RCC_AHB2ENR_HSEMEN)

+#define __HAL_RCC_HSEM_CLK_DISABLE()             (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_HSEMEN))

+#endif

+#if defined(BDMA1)

+#define __HAL_RCC_BDMA1_CLK_DISABLE()            (RCC->AHB2ENR &= ~ (RCC_AHB2ENR_BDMA1EN))

+#endif

+

+/** @brief  Get the enable or disable status of the AHB2 peripheral clock

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+

+#if defined(DCMI) && defined(PSSI)

+#define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED()         ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN)    != 0U)

+#define __HAL_RCC_DCMI_IS_CLK_ENABLED()              __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED()  /* for API backward compatibility*/

+#else

+#define __HAL_RCC_DCMI_IS_CLK_ENABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN)    != 0U)

+#endif /* DCMI && PSSI */

+#if defined(CRYP)

+#define __HAL_RCC_CRYP_IS_CLK_ENABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN)    != 0U)

+#endif /* CRYP */

+#if defined(HASH)

+#define __HAL_RCC_HASH_IS_CLK_ENABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN)    != 0U)

+#endif /* HASH */

+#define __HAL_RCC_RNG_IS_CLK_ENABLED()               ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN)     != 0U)

+#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED()            ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN)  != 0U)

+#if defined(RCC_AHB2ENR_D2SRAM1EN)

+#define __HAL_RCC_D2SRAM1_IS_CLK_ENABLED()           ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) != 0U)

+#else

+#define __HAL_RCC_AHBSRAM1_IS_CLK_ENABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) != 0U)

+#endif /* RCC_AHB2ENR_D2SRAM1EN */

+#if defined(RCC_AHB2ENR_D2SRAM2EN)

+#define __HAL_RCC_D2SRAM2_IS_CLK_ENABLED()           ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) != 0U)

+#else

+#define __HAL_RCC_AHBSRAM2_IS_CLK_ENABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) != 0U)

+#endif /* RCC_AHB2ENR_D2SRAM2EN */

+#if defined(RCC_AHB2ENR_D2SRAM3EN)

+#define __HAL_RCC_D2SRAM3_IS_CLK_ENABLED()           ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) != 0U)

+#endif

+#if defined(RCC_AHB2ENR_HSEMEN)

+#define __HAL_RCC_HSEM_IS_CLK_ENABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN)    != 0U)

+#endif

+#if defined(BDMA1)

+#define __HAL_RCC_BDMA1_IS_CLK_ENABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN)  != 0U)

+#endif

+

+#if defined(DCMI) && defined(PSSI)

+#define __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED()        ((RCC->AHB2ENR & RCC_AHB2ENR_DCMI_PSSIEN)    == 0U)

+#define __HAL_RCC_DCMI_IS_CLK_DISABLED()             __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED()  /* for API backward compatibility*/

+#else

+#define __HAL_RCC_DCMI_IS_CLK_DISABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_DCMIEN)    == 0U)

+#endif /* DCMI && PSSI */

+#if defined(CRYP)

+#define __HAL_RCC_CRYP_IS_CLK_DISABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_CRYPEN)    == 0U)

+#endif /* CRYP */

+#if defined(HASH)

+#define __HAL_RCC_HASH_IS_CLK_DISABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_HASHEN)    == 0U)

+#endif /* HASH */

+#define __HAL_RCC_RNG_IS_CLK_DISABLED()              ((RCC->AHB2ENR & RCC_AHB2ENR_RNGEN)     == 0U)

+#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED()           ((RCC->AHB2ENR & RCC_AHB2ENR_SDMMC2EN)  == 0U)

+#if defined(RCC_AHB2ENR_D2SRAM1EN)

+#define __HAL_RCC_D2SRAM1_IS_CLK_DISABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM1EN) == 0U)

+#else

+#define __HAL_RCC_AHBSRAM1_IS_CLK_DISABLED()         ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM1EN) == 0U)

+#endif /* RCC_AHB2ENR_D2SRAM1EN */

+#if defined(RCC_AHB2ENR_D2SRAM2EN)

+#define __HAL_RCC_D2SRAM2_IS_CLK_DISABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM2EN) == 0U)

+#else

+#define __HAL_RCC_AHBSRAM2_IS_CLK_DISABLED()         ((RCC->AHB2ENR & RCC_AHB2ENR_AHBSRAM2EN) == 0U)

+#endif /* RCC_AHB2ENR_D2SRAM2EN */

+#if defined(RCC_AHB2ENR_D2SRAM3EN)

+#define __HAL_RCC_D2SRAM3_IS_CLK_DISABLED()          ((RCC->AHB2ENR & RCC_AHB2ENR_D2SRAM3EN) == 0U)

+#endif

+#if defined(RCC_AHB2ENR_HSEMEN)

+#define __HAL_RCC_HSEM_IS_CLK_DISABLED()             ((RCC->AHB2ENR & RCC_AHB2ENR_HSEMEN)    == 0U)

+#endif

+#if defined(BDMA1)

+#define __HAL_RCC_BDMA1_IS_CLK_DISABLED()            ((RCC->AHB2ENR & RCC_AHB2ENR_BDMA1EN)   == 0U)

+#endif

+

+/** @brief  Enable or disable the AHB4 peripheral clock.

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+

+#define __HAL_RCC_GPIOA_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_GPIOB_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_GPIOC_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_GPIOD_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIODEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_GPIOE_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_GPIOF_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_GPIOG_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_GPIOH_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_GPIOI_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_GPIOJ_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_GPIOK_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#if defined(RCC_AHB4ENR_CRCEN)

+#define __HAL_RCC_CRC_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_CRCEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif

+

+#if defined(BDMA2)

+#define __HAL_RCC_BDMA2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMA2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_BDMA_CLK_ENABLE()  __HAL_RCC_BDMA2_CLK_ENABLE()  /* for API backward compatibility*/

+#else

+#define __HAL_RCC_BDMA_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BDMAEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif

+

+#if defined(ADC3)

+#define __HAL_RCC_ADC3_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_ADC3EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif

+

+#if defined(RCC_AHB4ENR_HSEMEN)

+#define __HAL_RCC_HSEM_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_HSEMEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif

+

+#if defined(RCC_AHB4ENR_SRDSRAMEN)

+#define __HAL_RCC_SRDSRAM_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_SRDSRAMEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif

+

+#define __HAL_RCC_BKPRAM_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+

+#define __HAL_RCC_GPIOA_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)

+#define __HAL_RCC_GPIOB_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)

+#define __HAL_RCC_GPIOC_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)

+#define __HAL_RCC_GPIOD_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)

+#define __HAL_RCC_GPIOE_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)

+#define __HAL_RCC_GPIOF_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)

+#define __HAL_RCC_GPIOG_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)

+#define __HAL_RCC_GPIOH_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)

+#define __HAL_RCC_GPIOI_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)

+#define __HAL_RCC_GPIOJ_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)

+#define __HAL_RCC_GPIOK_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)

+#if defined(RCC_AHB4ENR_CRCEN)

+#define __HAL_RCC_CRC_CLK_DISABLE()             (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)

+#endif

+#if defined(BDMA2)

+#define __HAL_RCC_BDMA2_CLK_DISABLE()           (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMA2EN)

+#define __HAL_RCC_BDMA_CLK_DISABLE()            __HAL_RCC_BDMA2_CLK_DISABLE()  /* for API backward compatibility*/

+#else

+#define __HAL_RCC_BDMA_CLK_DISABLE()            (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)

+#endif

+#if defined(ADC3)

+#define __HAL_RCC_ADC3_CLK_DISABLE()            (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)

+#endif

+#if defined(RCC_AHB4ENR_HSEMEN)

+#define __HAL_RCC_HSEM_CLK_DISABLE()            (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)

+#endif

+#if defined(RCC_AHB4ENR_SRDSRAMEN)

+#define __HAL_RCC_SRDSRAM_CLK_DISABLE()         (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_SRDSRAMEN)

+#endif

+#define __HAL_RCC_BKPRAM_CLK_DISABLE()          (RCC->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)

+

+

+/** @brief  Get the enable or disable status of the AHB4 peripheral clock

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+

+#define __HAL_RCC_GPIOA_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN)  != 0U)

+#define __HAL_RCC_GPIOB_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN)  != 0U)

+#define __HAL_RCC_GPIOC_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN)  != 0U)

+#define __HAL_RCC_GPIOD_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN)  != 0U)

+#define __HAL_RCC_GPIOE_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN)  != 0U)

+#define __HAL_RCC_GPIOF_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN)  != 0U)

+#define __HAL_RCC_GPIOG_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN)  != 0U)

+#define __HAL_RCC_GPIOH_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN)  != 0U)

+#define __HAL_RCC_GPIOI_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN)  != 0U)

+#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN)  != 0U)

+#define __HAL_RCC_GPIOK_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN)  != 0U)

+#if defined(RCC_AHB4ENR_CRCEN)

+#define __HAL_RCC_CRC_IS_CLK_ENABLED()              ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN)    != 0U)

+#endif

+#if defined(BDMA2)

+#define __HAL_RCC_BDMA2_IS_CLK_ENABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN)   != 0U)

+#define __HAL_RCC_BDMA_IS_CLK_ENABLED()  __HAL_RCC_BDMA2_IS_CLK_ENABLED()            /* for API backward compatibility*/

+#else

+#define __HAL_RCC_BDMA_IS_CLK_ENABLED()             ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN)   != 0U)

+#endif

+#if defined(ADC3)

+#define __HAL_RCC_ADC3_IS_CLK_ENABLED()             ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN)   != 0U)

+#endif

+#if defined(RCC_AHB4ENR_HSEMEN)

+#define __HAL_RCC_HSEM_IS_CLK_ENABLED()             ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN)   != 0U)

+#endif

+#if defined(RCC_AHB4ENR_SRDSRAMEN)

+#define __HAL_RCC_SRDSRAM_IS_CLK_ENABLED()          ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN) != 0U)

+#endif

+#define __HAL_RCC_BKPRAM_IS_CLK_ENABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) != 0U)

+

+#define __HAL_RCC_GPIOA_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOAEN)  == 0U)

+#define __HAL_RCC_GPIOB_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOBEN)  == 0U)

+#define __HAL_RCC_GPIOC_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOCEN)  == 0U)

+#define __HAL_RCC_GPIOD_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIODEN)  == 0U)

+#define __HAL_RCC_GPIOE_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOEEN)  == 0U)

+#define __HAL_RCC_GPIOF_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOFEN)  == 0U)

+#define __HAL_RCC_GPIOG_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOGEN)  == 0U)

+#define __HAL_RCC_GPIOH_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOHEN)  == 0U)

+#define __HAL_RCC_GPIOI_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOIEN)  == 0U)

+#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOJEN)  == 0U)

+#define __HAL_RCC_GPIOK_IS_CLK_DISABLED()           ((RCC->AHB4ENR & RCC_AHB4ENR_GPIOKEN)  == 0U)

+

+#if defined(RCC_AHB4ENR_CRCEN)

+#define __HAL_RCC_CRC_IS_CLK_DISABLED()             ((RCC->AHB4ENR & RCC_AHB4ENR_CRCEN)    == 0U)

+#endif

+#if defined(BDMA2)

+#define __HAL_RCC_BDMA2_IS_CLK_DISABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_BDMA2EN)   == 0U)

+#define __HAL_RCC_BDMA_IS_CLK_DISABLED()  __HAL_RCC_BDMA2_IS_CLK_DISABLED()           /* for API backward compatibility*/

+#else

+#define __HAL_RCC_BDMA_IS_CLK_DISABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_BDMAEN)   == 0U)

+#endif

+#if defined(ADC3)

+#define __HAL_RCC_ADC3_IS_CLK_DISABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_ADC3EN)   == 0U)

+#endif

+#if defined(RCC_AHB4ENR_HSEMEN)

+#define __HAL_RCC_HSEM_IS_CLK_DISABLED()            ((RCC->AHB4ENR & RCC_AHB4ENR_HSEMEN)   == 0U)

+#endif

+#if defined(RCC_AHB4ENR_SRDSRAMEN)

+#define __HAL_RCC_SRDSRAM_IS_CLK_DISABLED()         ((RCC->AHB4ENR & RCC_AHB4ENR_SRDSRAMEN)   == 0U)

+#endif

+#define __HAL_RCC_BKPRAM_IS_CLK_DISABLED()          ((RCC->AHB4ENR & RCC_AHB4ENR_BKPRAMEN) == 0U)

+

+

+/** @brief  Enable or disable the APB3 peripheral clock.

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+

+#if defined(LTDC)

+#define __HAL_RCC_LTDC_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LTDCEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /* LTDC */

+

+#if defined(DSI)

+#define __HAL_RCC_DSI_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_DSIEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /*DSI*/

+

+#define __HAL_RCC_WWDG1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_WWDG1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#if defined(LTDC)

+#define __HAL_RCC_LTDC_CLK_DISABLE()           (RCC->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)

+#endif /* LTDC */

+#if defined(DSI)

+#define __HAL_RCC_DSI_CLK_DISABLE()            (RCC->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)

+#endif /*DSI*/

+#define __HAL_RCC_WWDG1_CLK_DISABLE()          (RCC->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)

+

+/** @brief  Get the enable or disable status of the APB3 peripheral clock

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+

+#if defined(LTDC)

+#define __HAL_RCC_LTDC_IS_CLK_ENABLED()            ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN)  != 0U)

+#endif /* LTDC */

+#if defined(DSI)

+#define __HAL_RCC_DSI_IS_CLK_ENABLED()             ((RCC->APB3ENR & RCC_APB3ENR_DSIEN)   != 0U)

+#endif /*DSI*/

+#define __HAL_RCC_WWDG1_IS_CLK_ENABLED()           ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) != 0U)

+#if defined(LTDC)

+#define __HAL_RCC_LTDC_IS_CLK_DISABLED()           ((RCC->APB3ENR & RCC_APB3ENR_LTDCEN)  == 0U)

+#endif /* LTDC */

+#if defined(DSI)

+#define __HAL_RCC_DSI_IS_CLK_DISABLED()            ((RCC->APB3ENR & RCC_APB3ENR_DSIEN)   == 0U)

+#endif /*DSI*/

+#define __HAL_RCC_WWDG1_IS_CLK_DISABLED()          ((RCC->APB3ENR & RCC_APB3ENR_WWDG1EN) == 0U)

+

+

+/** @brief  Enable or disable the APB1 peripheral clock.

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+

+#define __HAL_RCC_TIM2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_TIM3_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM3EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_TIM4_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM4EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_TIM5_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM5EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_TIM6_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM6EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_TIM7_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM7EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_TIM12_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM12EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_TIM13_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM13EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_TIM14_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_TIM14EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_LPTIM1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_LPTIM1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#if defined(DUAL_CORE)

+#define __HAL_RCC_WWDG2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_WWDG2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /*DUAL_CORE*/

+

+#define __HAL_RCC_SPI2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_SPI3_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPI3EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_SPDIFRX_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_USART2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_USART3_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_USART3EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_UART4_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART4EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_UART5_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART5EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_I2C1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_I2C2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_I2C3_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_I2C3EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_CEC_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_CECEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_DAC12_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_DAC12EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_UART7_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART7EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_UART8_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB1LENR, RCC_APB1LENR_UART8EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_CRS_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_CRSEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_SWPMI1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_SWPMIEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_OPAMP_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_OPAMPEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_MDIOS_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_MDIOSEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_FDCAN_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB1HENR, RCC_APB1HENR_FDCANEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+

+#define __HAL_RCC_TIM2_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)

+#define __HAL_RCC_TIM3_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)

+#define __HAL_RCC_TIM4_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)

+#define __HAL_RCC_TIM5_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)

+#define __HAL_RCC_TIM6_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)

+#define __HAL_RCC_TIM7_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)

+#define __HAL_RCC_TIM12_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)

+#define __HAL_RCC_TIM13_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)

+#define __HAL_RCC_TIM14_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)

+#define __HAL_RCC_LPTIM1_CLK_DISABLE()         (RCC->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)

+

+#if defined(DUAL_CORE)

+#define __HAL_RCC_WWDG2_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)

+#endif /*DUAL_CORE*/

+

+#define __HAL_RCC_SPI2_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)

+#define __HAL_RCC_SPI3_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)

+#define __HAL_RCC_SPDIFRX_CLK_DISABLE()        (RCC->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)

+#define __HAL_RCC_USART2_CLK_DISABLE()         (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)

+#define __HAL_RCC_USART3_CLK_DISABLE()         (RCC->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)

+#define __HAL_RCC_UART4_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)

+#define __HAL_RCC_UART5_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)

+#define __HAL_RCC_I2C1_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)

+#define __HAL_RCC_I2C2_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)

+#define __HAL_RCC_I2C3_CLK_DISABLE()           (RCC->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)

+#define __HAL_RCC_CEC_CLK_DISABLE()            (RCC->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)

+#define __HAL_RCC_DAC12_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)

+#define __HAL_RCC_UART7_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)

+#define __HAL_RCC_UART8_CLK_DISABLE()          (RCC->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)

+#define __HAL_RCC_CRS_CLK_DISABLE()            (RCC->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)

+#define __HAL_RCC_SWPMI1_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)

+#define __HAL_RCC_OPAMP_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)

+#define __HAL_RCC_MDIOS_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)

+#define __HAL_RCC_FDCAN_CLK_DISABLE()          (RCC->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)

+

+

+/** @brief  Get the enable or disable status of the APB1 peripheral clock

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+

+#define __HAL_RCC_TIM2_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN)    != 0U)

+#define __HAL_RCC_TIM3_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN)    != 0U)

+#define __HAL_RCC_TIM4_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN)    != 0U)

+#define __HAL_RCC_TIM5_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN)    != 0U)

+#define __HAL_RCC_TIM6_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN)    != 0U)

+#define __HAL_RCC_TIM7_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN)    != 0U)

+#define __HAL_RCC_TIM12_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN)   != 0U)

+#define __HAL_RCC_TIM13_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN)   != 0U)

+#define __HAL_RCC_TIM14_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN)   != 0U)

+#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED()          ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN)  != 0U)

+#if defined(DUAL_CORE)

+#define __HAL_RCC_WWDG2_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN)   != 0U)

+#endif /*DUAL_CORE*/

+#define __HAL_RCC_SPI2_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN)    != 0U)

+#define __HAL_RCC_SPI3_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN)    != 0U)

+#define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED()         ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) != 0U)

+#define __HAL_RCC_USART2_IS_CLK_ENABLED()          ((RCC->APB1LENR & RCC_APB1LENR_USART2EN)  != 0U)

+#define __HAL_RCC_USART3_IS_CLK_ENABLED()          ((RCC->APB1LENR & RCC_APB1LENR_USART3EN)  != 0U)

+#define __HAL_RCC_UART4_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_UART4EN)   != 0U)

+#define __HAL_RCC_UART5_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_UART5EN)   != 0U)

+#define __HAL_RCC_I2C1_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN)    != 0U)

+#define __HAL_RCC_I2C2_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN)    != 0U)

+#define __HAL_RCC_I2C3_IS_CLK_ENABLED()            ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN)    != 0U)

+#define __HAL_RCC_CEC_IS_CLK_ENABLED()             ((RCC->APB1LENR & RCC_APB1LENR_CECEN)     != 0U)

+#define __HAL_RCC_DAC12_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN)   != 0U)

+#define __HAL_RCC_UART7_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_UART7EN)   != 0U)

+#define __HAL_RCC_UART8_IS_CLK_ENABLED()           ((RCC->APB1LENR & RCC_APB1LENR_UART8EN)   != 0U)

+#define __HAL_RCC_CRS_IS_CLK_ENABLED()             ((RCC->APB1HENR & RCC_APB1HENR_CRSEN)     != 0U)

+#define __HAL_RCC_SWPMI1_IS_CLK_ENABLED()          ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN)   != 0U)

+#define __HAL_RCC_OPAMP_IS_CLK_ENABLED()           ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN)   != 0U)

+#define __HAL_RCC_MDIOS_IS_CLK_ENABLED()           ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN)   != 0U)

+#define __HAL_RCC_FDCAN_IS_CLK_ENABLED()           ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN)   != 0U)

+

+#define __HAL_RCC_TIM2_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM2EN)    == 0U)

+#define __HAL_RCC_TIM3_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM3EN)    == 0U)

+#define __HAL_RCC_TIM4_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM4EN)    == 0U)

+#define __HAL_RCC_TIM5_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM5EN)    == 0U)

+#define __HAL_RCC_TIM6_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM6EN)    == 0U)

+#define __HAL_RCC_TIM7_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_TIM7EN)    == 0U)

+#define __HAL_RCC_TIM12_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_TIM12EN)   == 0U)

+#define __HAL_RCC_TIM13_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_TIM13EN)   == 0U)

+#define __HAL_RCC_TIM14_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_TIM14EN)   == 0U)

+#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED()         ((RCC->APB1LENR & RCC_APB1LENR_LPTIM1EN)  == 0U)

+#if defined(DUAL_CORE)

+#define __HAL_RCC_WWDG2_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_WWDG2EN)   == 0U)

+#endif /*DUAL_CORE*/

+#define __HAL_RCC_SPI2_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_SPI2EN)    == 0U)

+#define __HAL_RCC_SPI3_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_SPI3EN)    == 0U)

+#define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()        ((RCC->APB1LENR & RCC_APB1LENR_SPDIFRXEN) == 0U)

+#define __HAL_RCC_USART2_IS_CLK_DISABLED()         ((RCC->APB1LENR & RCC_APB1LENR_USART2EN)  == 0U)

+#define __HAL_RCC_USART3_IS_CLK_DISABLED()         ((RCC->APB1LENR & RCC_APB1LENR_USART3EN)  == 0U)

+#define __HAL_RCC_UART4_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_UART4EN)   == 0U)

+#define __HAL_RCC_UART5_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_UART5EN)   == 0U)

+#define __HAL_RCC_I2C1_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_I2C1EN)    == 0U)

+#define __HAL_RCC_I2C2_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_I2C2EN)    == 0U)

+#define __HAL_RCC_I2C3_IS_CLK_DISABLED()           ((RCC->APB1LENR & RCC_APB1LENR_I2C3EN)    == 0U)

+#define __HAL_RCC_CEC_IS_CLK_DISABLED()            ((RCC->APB1LENR & RCC_APB1LENR_CECEN)     == 0U)

+#define __HAL_RCC_DAC12_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_DAC12EN)   == 0U)

+#define __HAL_RCC_UART7_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_UART7EN)   == 0U)

+#define __HAL_RCC_UART8_IS_CLK_DISABLED()          ((RCC->APB1LENR & RCC_APB1LENR_UART8EN)   == 0U)

+#define __HAL_RCC_CRS_IS_CLK_DISABLED()            ((RCC->APB1HENR & RCC_APB1HENR_CRSEN)     == 0U)

+#define __HAL_RCC_SWPMI1_IS_CLK_DISABLED()         ((RCC->APB1HENR & RCC_APB1HENR_SWPMIEN)   == 0U)

+#define __HAL_RCC_OPAMP_IS_CLK_DISABLED()          ((RCC->APB1HENR & RCC_APB1HENR_OPAMPEN)   == 0U)

+#define __HAL_RCC_MDIOS_IS_CLK_DISABLED()          ((RCC->APB1HENR & RCC_APB1HENR_MDIOSEN)   == 0U)

+#define __HAL_RCC_FDCAN_IS_CLK_DISABLED()          ((RCC->APB1HENR & RCC_APB1HENR_FDCANEN)   == 0U)

+

+

+/** @brief  Enable or disable the APB2 peripheral clock.

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+

+#define __HAL_RCC_TIM1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_TIM8_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_USART1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_USART6_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#if defined(UART9)

+#define __HAL_RCC_UART9_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_UART9EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /*UART9*/

+

+#if defined(USART10)

+#define __HAL_RCC_USART10_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART10EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /*USART10*/

+

+#define __HAL_RCC_SPI1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_SPI4_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_TIM15_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_TIM16_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_TIM17_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_SPI5_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_SAI1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_SAI2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#if defined(SAI3)

+#define __HAL_RCC_SAI3_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI3EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /*SAI3*/

+

+#define __HAL_RCC_DFSDM1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DFSDM1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#if defined(HRTIM1)

+#define __HAL_RCC_HRTIM1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_HRTIMEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /*HRTIM1*/

+

+#define __HAL_RCC_TIM1_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)

+#define __HAL_RCC_TIM8_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)

+#define __HAL_RCC_USART1_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)

+#define __HAL_RCC_USART6_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)

+#if defined(UART9)

+#define __HAL_RCC_UART9_CLK_DISABLE()          (RCC->APB2ENR) &= ~ (RCC_APB2ENR_UART9EN)

+#endif /*UART9*/

+#if defined(USART10)

+#define __HAL_RCC_USART10_CLK_DISABLE()        (RCC->APB2ENR) &= ~ (RCC_APB2ENR_USART10EN)

+#endif /*USART10*/

+#define __HAL_RCC_SPI1_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)

+#define __HAL_RCC_SPI4_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)

+#define __HAL_RCC_TIM15_CLK_DISABLE()          (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)

+#define __HAL_RCC_TIM16_CLK_DISABLE()          (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)

+#define __HAL_RCC_TIM17_CLK_DISABLE()          (RCC->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)

+#define __HAL_RCC_SPI5_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)

+#define __HAL_RCC_SAI1_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)

+#define __HAL_RCC_SAI2_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)

+#if defined(SAI3)

+#define __HAL_RCC_SAI3_CLK_DISABLE()           (RCC->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)

+#endif /*SAI3*/

+#define __HAL_RCC_DFSDM1_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)

+#if defined(HRTIM1)

+#define __HAL_RCC_HRTIM1_CLK_DISABLE()         (RCC->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)

+#endif /*HRTIM*/

+

+/** @brief  Get the enable or disable status of the APB2 peripheral clock

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+

+#define __HAL_RCC_TIM1_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN)   != 0U)

+#define __HAL_RCC_TIM8_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN)   != 0U)

+#define __HAL_RCC_USART1_IS_CLK_ENABLED()          ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) != 0U)

+#define __HAL_RCC_USART6_IS_CLK_ENABLED()          ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) != 0U)

+#if defined(UART9)

+#define __HAL_RCC_UART9_IS_CLK_ENABLED()           ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) != 0U)

+#endif /*UART9*/

+#if defined(USART10)

+#define __HAL_RCC_USART10_IS_CLK_ENABLED()         ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) != 0U)

+#endif /*USART10*/

+#define __HAL_RCC_SPI1_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN)   != 0U)

+#define __HAL_RCC_SPI4_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN)   != 0U)

+#define __HAL_RCC_TIM15_IS_CLK_ENABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN)  != 0U)

+#define __HAL_RCC_TIM16_IS_CLK_ENABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN)  != 0U)

+#define __HAL_RCC_TIM17_IS_CLK_ENABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN)  != 0U)

+#define __HAL_RCC_SPI5_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN)   != 0U)

+#define __HAL_RCC_SAI1_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN)   != 0U)

+#define __HAL_RCC_SAI2_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN)   != 0U)

+#if defined(SAI3)

+#define __HAL_RCC_SAI3_IS_CLK_ENABLED()            ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN)   != 0U)

+#endif /* SAI3 */

+#define __HAL_RCC_DFSDM1_IS_CLK_ENABLED()          ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) != 0U)

+#if defined(HRTIM1)

+#define __HAL_RCC_HRTIM1_IS_CLK_ENABLED()          ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN)  != 0U)

+#endif /*HRTIM1*/

+

+#define __HAL_RCC_TIM1_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM1EN)   == 0U)

+#define __HAL_RCC_TIM8_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_TIM8EN)   == 0U)

+#define __HAL_RCC_USART1_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_USART1EN) == 0U)

+#define __HAL_RCC_USART6_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_USART6EN) == 0U)

+#if defined(UART9)

+#define __HAL_RCC_UART9_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_UART9EN) == 0U)

+#endif /*UART9*/

+#if defined(USART10)

+#define __HAL_RCC_USART10_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_USART10EN) == 0U)

+#endif /*USART10*/

+#define __HAL_RCC_SPI1_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SPI1EN)   == 0U)

+#define __HAL_RCC_SPI4_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SPI4EN)   == 0U)

+#define __HAL_RCC_TIM15_IS_CLK_DISABLED()          ((RCC->APB2ENR & RCC_APB2ENR_TIM15EN)  == 0U)

+#define __HAL_RCC_TIM16_IS_CLK_DISABLED()          ((RCC->APB2ENR & RCC_APB2ENR_TIM16EN)  == 0U)

+#define __HAL_RCC_TIM17_IS_CLK_DISABLED()          ((RCC->APB2ENR & RCC_APB2ENR_TIM17EN)  == 0U)

+#define __HAL_RCC_SPI5_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SPI5EN)   == 0U)

+#define __HAL_RCC_SAI1_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SAI1EN)   == 0U)

+#define __HAL_RCC_SAI2_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SAI2EN)   == 0U)

+#if defined(SAI3)

+#define __HAL_RCC_SAI3_IS_CLK_DISABLED()           ((RCC->APB2ENR & RCC_APB2ENR_SAI3EN)   == 0U)

+#endif /*SAI3*/

+#define __HAL_RCC_DFSDM1_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_DFSDM1EN) == 0U)

+#if defined(HRTIM1)

+#define __HAL_RCC_HRTIM1_IS_CLK_DISABLED()         ((RCC->APB2ENR & RCC_APB2ENR_HRTIMEN)  == 0U)

+#endif /*HRTIM1*/

+

+/** @brief  Enable or disable the APB4 peripheral clock.

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+

+#define __HAL_RCC_SYSCFG_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SYSCFGEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_LPUART1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPUART1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_SPI6_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SPI6EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_I2C4_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_I2C4EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_LPTIM2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_LPTIM3_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM3EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#if defined(LPTIM4)

+#define __HAL_RCC_LPTIM4_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM4EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /* LPTIM4 */

+

+#if defined(LPTIM5)

+#define __HAL_RCC_LPTIM5_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_LPTIM5EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /* LPTIM5 */

+

+#if defined(DAC2)

+#define __HAL_RCC_DAC2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DAC2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /*  DAC2 */

+

+#define __HAL_RCC_COMP12_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_COMP12EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_VREF_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_VREFEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#if defined(SAI4)

+#define __HAL_RCC_SAI4_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_SAI4EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /* SAI4 */

+

+#define __HAL_RCC_RTC_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_RTCAPBEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#if defined(DTS)

+#define __HAL_RCC_DTS_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DTSEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /*DTS*/

+

+#if defined(DFSDM2_BASE)

+#define __HAL_RCC_DFSDM2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC->APB4ENR, RCC_APB4ENR_DFSDM2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /*DFSDM2*/

+

+#define __HAL_RCC_SYSCFG_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)

+#define __HAL_RCC_LPUART1_CLK_DISABLE()          (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)

+#define __HAL_RCC_SPI6_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)

+#define __HAL_RCC_I2C4_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)

+#define __HAL_RCC_LPTIM2_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)

+#define __HAL_RCC_LPTIM3_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)

+#if defined(LPTIM4)

+#define __HAL_RCC_LPTIM4_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)

+#endif /*LPTIM4*/

+#if defined(LPTIM5)

+#define __HAL_RCC_LPTIM5_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)

+#endif /*LPTIM5*/

+#if defined(DAC2)

+#define __HAL_RCC_DAC2_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DAC2EN)

+#endif /*DAC2*/

+#define __HAL_RCC_COMP12_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)

+#define __HAL_RCC_VREF_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)

+#define __HAL_RCC_RTC_CLK_DISABLE()              (RCC->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)

+#if defined(SAI4)

+#define __HAL_RCC_SAI4_CLK_DISABLE()             (RCC->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)

+#endif /*SAI4*/

+#if defined(DTS)

+#define __HAL_RCC_DTS_CLK_DISABLE()              (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DTSEN)

+#endif /*DTS*/

+#if defined(DFSDM2_BASE)

+#define __HAL_RCC_DFSDM2_CLK_DISABLE()           (RCC->APB4ENR) &= ~ (RCC_APB4ENR_DFSDM2EN)

+#endif /*DFSDM2*/

+

+/** @brief  Get the enable or disable status of the APB4 peripheral clock

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+

+#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN)  != 0U)

+#define __HAL_RCC_LPUART1_IS_CLK_ENABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) != 0U)

+#define __HAL_RCC_SPI6_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN)    != 0U)

+#define __HAL_RCC_I2C4_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN)    != 0U)

+#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN)  != 0U)

+#define __HAL_RCC_LPTIM3_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN)  != 0U)

+#if defined(LPTIM4)

+#define __HAL_RCC_LPTIM4_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN)  != 0U)

+#endif /*LPTIM4*/

+#if defined(LPTIM5)

+#define __HAL_RCC_LPTIM5_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN)  != 0U)

+#endif /*LPTIM5*/

+#if defined(DAC2)

+#define __HAL_RCC_DAC2_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN)  != 0U)

+#endif /*DAC2*/

+#define __HAL_RCC_COMP12_IS_CLK_ENABLED()            ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN)  != 0U)

+#define __HAL_RCC_VREF_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_VREFEN)    != 0U)

+#define __HAL_RCC_RTC_IS_CLK_ENABLED()               ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN)  != 0U)

+#if defined(SAI4)

+#define __HAL_RCC_SAI4_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN)    != 0U)

+#endif /*SAI4*/

+#if defined(DTS)

+#define __HAL_RCC_DTS_IS_CLK_ENABLED()               ((RCC->APB4ENR & RCC_APB4ENR_DTSEN)    != 0U)

+#endif /*DTS*/

+#if defined(DFSDM2_BASE)

+#define __HAL_RCC_DFSDM2_IS_CLK_ENABLED()              ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN)    != 0U)

+#endif /*DFSDM2*/

+

+#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_SYSCFGEN)  == 0U)

+#define __HAL_RCC_LPUART1_IS_CLK_DISABLED()          ((RCC->APB4ENR & RCC_APB4ENR_LPUART1EN) == 0U)

+#define __HAL_RCC_SPI6_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_SPI6EN)    == 0U)

+#define __HAL_RCC_I2C4_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_I2C4EN)    == 0U)

+#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPTIM2EN)  == 0U)

+#define __HAL_RCC_LPTIM3_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPTIM3EN)  == 0U)

+#if defined(LPTIM4)

+#define __HAL_RCC_LPTIM4_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPTIM4EN)  == 0U)

+#endif /*LPTIM4*/

+#if defined(LPTIM5)

+#define __HAL_RCC_LPTIM5_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_LPTIM5EN)  == 0U)

+#endif /*LPTIM5*/

+#if defined(DAC2)

+#define __HAL_RCC_DAC2_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_DAC2EN)  == 0U)

+#endif /*DAC2*/

+#define __HAL_RCC_COMP12_IS_CLK_DISABLED()           ((RCC->APB4ENR & RCC_APB4ENR_COMP12EN)  == 0U)

+#define __HAL_RCC_VREF_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_VREFEN)    == 0U)

+#define __HAL_RCC_RTC_IS_CLK_DISABLED()              ((RCC->APB4ENR & RCC_APB4ENR_RTCAPBEN)  == 0U)

+#if defined(SAI4)

+#define __HAL_RCC_SAI4_IS_CLK_DISABLED()             ((RCC->APB4ENR & RCC_APB4ENR_SAI4EN)    == 0U)

+#endif /*SAI4*/

+#if defined(DTS)

+#define __HAL_RCC_DTS_IS_CLK_DISABLED()              ((RCC->APB4ENR & RCC_APB4ENR_DTSEN)    == 0U)

+#endif /*DTS*/

+#if defined(DFSDM2_BASE)

+#define __HAL_RCC_DFSDM2_IS_CLK_DISABLED()          ((RCC->APB4ENR & RCC_APB4ENR_DFSDM2EN)    == 0U)

+#endif /*DFSDM2*/

+

+#if defined(DUAL_CORE)

+

+/* Exported macros for RCC_C1 -------------------------------------------------*/

+

+/** @brief  Enable or disable the AHB3 peripheral clock.

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+

+#define __HAL_RCC_C1_MDMA_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_MDMAEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_DMA2D_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_JPGDECEN_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+

+#define __HAL_RCC_C1_FMC_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_FMCEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_QSPI_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_QSPIEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_SDMMC1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+

+

+

+#define __HAL_RCC_C1_MDMA_CLK_DISABLE()            (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))

+#define __HAL_RCC_C1_DMA2D_CLK_DISABLE()           (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))

+#define __HAL_RCC_C1_JPGDECEN_CLK_DISABLE()        (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))

+#define __HAL_RCC_C1_FMC_CLK_DISABLE()             (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))

+#define __HAL_RCC_C1_QSPI_CLK_DISABLE()            (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))

+#define __HAL_RCC_C1_SDMMC1_CLK_DISABLE()          (RCC_C1->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))

+

+

+

+

+/** @brief  Enable or disable the AHB1 peripheral clock.

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+

+#define __HAL_RCC_C1_DMA1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_DMA2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_DMA2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_ADC12_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ADC12EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_ART_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ARTEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_ETH1MAC_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_ETH1TX_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_ETH1RX_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+

+#define __HAL_RCC_C1_USB1_OTG_HS_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_USB2_OTG_FS_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_DMA1_CLK_DISABLE()             (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))

+#define __HAL_RCC_C1_DMA2_CLK_DISABLE()             (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))

+#define __HAL_RCC_C1_ADC12_CLK_DISABLE()            (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))

+#define __HAL_RCC_C1_ART_CLK_DISABLE()              (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))

+#define __HAL_RCC_C1_ETH1MAC_CLK_DISABLE()          (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))

+#define __HAL_RCC_C1_ETH1TX_CLK_DISABLE()           (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))

+#define __HAL_RCC_C1_ETH1RX_CLK_DISABLE()           (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))

+#define __HAL_RCC_C1_USB1_OTG_HS_CLK_DISABLE()      (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))

+#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))

+#define __HAL_RCC_C1_USB2_OTG_FS_CLK_DISABLE()      (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))

+#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C1->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))

+

+/** @brief  Enable or disable the AHB2 peripheral clock.

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+

+#define __HAL_RCC_C1_DCMI_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_DCMIEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#if defined(CRYP)

+#define __HAL_RCC_C1_CRYP_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_CRYPEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /* CRYP */

+

+#if defined(HASH)

+#define __HAL_RCC_C1_HASH_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_HASHEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /* HASH */

+

+#define __HAL_RCC_C1_RNG_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_RNGEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_SDMMC2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_D2SRAM1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_D2SRAM2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_D2SRAM3_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_DCMI_CLK_DISABLE()             (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))

+#if defined(CRYP)

+#define __HAL_RCC_C1_CRYP_CLK_DISABLE()             (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))

+#endif /* CRYP */

+#if defined(HASH)

+#define __HAL_RCC_C1_HASH_CLK_DISABLE()             (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))

+#endif /* HASH */

+#define __HAL_RCC_C1_RNG_CLK_DISABLE()              (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))

+#define __HAL_RCC_C1_SDMMC2_CLK_DISABLE()           (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))

+#define __HAL_RCC_C1_D2SRAM1_CLK_DISABLE()          (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))

+#define __HAL_RCC_C1_D2SRAM2_CLK_DISABLE()          (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))

+#define __HAL_RCC_C1_D2SRAM3_CLK_DISABLE()          (RCC_C1->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))

+

+/** @brief  Enable or disable the AHB4 peripheral clock.

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+

+#define __HAL_RCC_C1_GPIOA_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_GPIOB_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_GPIOC_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_GPIOD_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIODEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_GPIOE_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_GPIOF_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_GPIOG_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_GPIOH_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_GPIOI_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_GPIOJ_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_GPIOK_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_CRC_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_CRCEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_BDMA_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BDMAEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_ADC3_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_ADC3EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_HSEM_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_HSEMEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_BKPRAM_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+

+#define __HAL_RCC_C1_GPIOA_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)

+#define __HAL_RCC_C1_GPIOB_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)

+#define __HAL_RCC_C1_GPIOC_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)

+#define __HAL_RCC_C1_GPIOD_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)

+#define __HAL_RCC_C1_GPIOE_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)

+#define __HAL_RCC_C1_GPIOF_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)

+#define __HAL_RCC_C1_GPIOG_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)

+#define __HAL_RCC_C1_GPIOH_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)

+#define __HAL_RCC_C1_GPIOI_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)

+#define __HAL_RCC_C1_GPIOJ_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)

+#define __HAL_RCC_C1_GPIOK_CLK_DISABLE()           (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)

+#define __HAL_RCC_C1_CRC_CLK_DISABLE()             (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)

+#define __HAL_RCC_C1_BDMA_CLK_DISABLE()            (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)

+#define __HAL_RCC_C1_ADC3_CLK_DISABLE()            (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)

+#define __HAL_RCC_C1_HSEM_CLK_DISABLE()            (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)

+#define __HAL_RCC_C1_BKPRAM_CLK_DISABLE()          (RCC_C1->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)

+

+

+/** @brief  Enable or disable the APB3 peripheral clock.

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+

+#define __HAL_RCC_C1_LTDC_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_LTDCEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_DSI_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_DSIEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_WWDG1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB3ENR, RCC_APB3ENR_WWDG1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_LTDC_CLK_DISABLE()           (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)

+#define __HAL_RCC_C1_DSI_CLK_DISABLE()            (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)

+#define __HAL_RCC_C1_WWDG1_CLK_DISABLE()          (RCC_C1->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)

+

+/** @brief  Enable or disable the APB1 peripheral clock.

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+

+#define __HAL_RCC_C1_TIM2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_TIM3_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM3EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_TIM4_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM4EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_TIM5_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM5EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_TIM6_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM6EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_TIM7_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM7EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_TIM12_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM12EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_TIM13_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM13EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_TIM14_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_TIM14EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_LPTIM1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_LPTIM1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_WWDG2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_WWDG2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_SPI2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_SPI3_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPI3EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_SPDIFRX_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_USART2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_USART3_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_USART3EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_UART4_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART4EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_UART5_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART5EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_I2C1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_I2C2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_I2C3_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_I2C3EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_CEC_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_CECEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_DAC12_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_DAC12EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_UART7_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART7EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_UART8_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB1LENR, RCC_APB1LENR_UART8EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_CRS_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_CRSEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_SWPMI_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_SWPMIEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_OPAMP_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_OPAMPEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_MDIOS_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_MDIOSEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_FDCAN_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB1HENR, RCC_APB1HENR_FDCANEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+

+#define __HAL_RCC_C1_TIM2_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)

+#define __HAL_RCC_C1_TIM3_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)

+#define __HAL_RCC_C1_TIM4_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)

+#define __HAL_RCC_C1_TIM5_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)

+#define __HAL_RCC_C1_TIM6_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)

+#define __HAL_RCC_C1_TIM7_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)

+#define __HAL_RCC_C1_TIM12_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)

+#define __HAL_RCC_C1_TIM13_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)

+#define __HAL_RCC_C1_TIM14_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)

+#define __HAL_RCC_C1_LPTIM1_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)

+#define __HAL_RCC_C1_WWDG2_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)

+#define __HAL_RCC_C1_SPI2_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)

+#define __HAL_RCC_C1_SPI3_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)

+#define __HAL_RCC_C1_SPDIFRX_CLK_DISABLE()        (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)

+#define __HAL_RCC_C1_USART2_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)

+#define __HAL_RCC_C1_USART3_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)

+#define __HAL_RCC_C1_UART4_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)

+#define __HAL_RCC_C1_UART5_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)

+#define __HAL_RCC_C1_I2C1_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)

+#define __HAL_RCC_C1_I2C2_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)

+#define __HAL_RCC_C1_I2C3_CLK_DISABLE()           (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)

+#define __HAL_RCC_C1_CEC_CLK_DISABLE()            (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)

+#define __HAL_RCC_C1_DAC12_CLK_DISABLE()          (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)

+#define __HAL_RCC_C1_UART7_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)

+#define __HAL_RCC_C1_UART8_CLK_DISABLE()         (RCC_C1->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)

+#define __HAL_RCC_C1_CRS_CLK_DISABLE()            (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)

+#define __HAL_RCC_C1_SWPMI_CLK_DISABLE()          (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)

+#define __HAL_RCC_C1_OPAMP_CLK_DISABLE()          (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)

+#define __HAL_RCC_C1_MDIOS_CLK_DISABLE()          (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)

+#define __HAL_RCC_C1_FDCAN_CLK_DISABLE()          (RCC_C1->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)

+

+/** @brief  Enable or disable the APB2 peripheral clock.

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+

+#define __HAL_RCC_C1_TIM1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_TIM8_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM8EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_USART1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_USART6_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_USART6EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_SPI1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_SPI4_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI4EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_TIM15_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM15EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_TIM16_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM16EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_TIM17_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_TIM17EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_SPI5_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SPI5EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_SAI1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_SAI2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_SAI3_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_SAI3EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_DFSDM1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_DFSDM1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_HRTIM1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB2ENR, RCC_APB2ENR_HRTIMEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_TIM1_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)

+#define __HAL_RCC_C1_TIM8_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)

+#define __HAL_RCC_C1_USART1_CLK_DISABLE()         (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)

+#define __HAL_RCC_C1_USART6_CLK_DISABLE()         (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)

+#define __HAL_RCC_C1_SPI1_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)

+#define __HAL_RCC_C1_SPI4_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)

+#define __HAL_RCC_C1_TIM15_CLK_DISABLE()          (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)

+#define __HAL_RCC_C1_TIM16_CLK_DISABLE()          (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)

+#define __HAL_RCC_C1_TIM17_CLK_DISABLE()          (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)

+#define __HAL_RCC_C1_SPI5_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)

+#define __HAL_RCC_C1_SAI1_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)

+#define __HAL_RCC_C1_SAI2_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)

+#define __HAL_RCC_C1_SAI3_CLK_DISABLE()           (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)

+#define __HAL_RCC_C1_DFSDM1_CLK_DISABLE()         (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)

+#define __HAL_RCC_C1_HRTIM1_CLK_DISABLE()         (RCC_C1->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)

+

+/** @brief  Enable or disable the APB4 peripheral clock.

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+

+#define __HAL_RCC_C1_SYSCFG_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SYSCFGEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_LPUART1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPUART1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_SPI6_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SPI6EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_I2C4_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_I2C4EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_LPTIM2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_LPTIM3_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM3EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_LPTIM4_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM4EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_LPTIM5_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_LPTIM5EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_COMP12_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_COMP12EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+

+#define __HAL_RCC_C1_VREF_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_VREFEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_RTC_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_RTCAPBEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C1_SAI4_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C1->APB4ENR, RCC_APB4ENR_SAI4EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+

+#define __HAL_RCC_C1_SYSCFG_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)

+#define __HAL_RCC_C1_LPUART1_CLK_DISABLE()          (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)

+#define __HAL_RCC_C1_SPI6_CLK_DISABLE()             (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)

+#define __HAL_RCC_C1_I2C4_CLK_DISABLE()             (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)

+#define __HAL_RCC_C1_LPTIM2_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)

+#define __HAL_RCC_C1_LPTIM3_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)

+#define __HAL_RCC_C1_LPTIM4_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)

+#define __HAL_RCC_C1_LPTIM5_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)

+#define __HAL_RCC_C1_COMP12_CLK_DISABLE()           (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)

+#define __HAL_RCC_C1_VREF_CLK_DISABLE()             (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)

+#define __HAL_RCC_C1_RTC_CLK_DISABLE()              (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)

+#define __HAL_RCC_C1_SAI4_CLK_DISABLE()             (RCC_C1->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)

+

+/* Exported macros for RCC_C2 -------------------------------------------------*/

+

+/** @brief  Enable or disable the AHB3 peripheral clock.

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+

+

+#define __HAL_RCC_C2_MDMA_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_MDMAEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_DMA2D_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DMA2DEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_JPGDECEN_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_JPGDECEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_FLASH_C2_ALLOCATE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FLASHEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_DTCM1_C2_ALLOCATE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_DTCM2_C2_ALLOCATE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_DTCM2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_ITCM_C2_ALLOCATE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_ITCMEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_D1SRAM1_C2_ALLOCATE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_AXISRAMEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_FMC_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_FMCEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_QSPI_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_QSPIEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_SDMMC1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB3ENR, RCC_AHB3ENR_SDMMC1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+

+

+

+#define __HAL_RCC_C2_MDMA_CLK_DISABLE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_MDMAEN))

+#define __HAL_RCC_C2_DMA2D_CLK_DISABLE()           (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DMA2DEN))

+#define __HAL_RCC_C2_JPGDECEN_CLK_DISABLE()        (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_JPGDECEN))

+#define __HAL_RCC_C2_FMC_CLK_DISABLE()             (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FMCEN))

+#define __HAL_RCC_C2_QSPI_CLK_DISABLE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_QSPIEN))

+#define __HAL_RCC_C2_SDMMC1_CLK_DISABLE()          (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_SDMMC1EN))

+#define __HAL_RCC_FLASH_C2_DEALLOCATE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_FLASHEN))

+#define __HAL_RCC_DTCM1_C2_DEALLOCATE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM1EN))

+#define __HAL_RCC_DTCM2_C2_DEALLOCATE()            (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_DTCM2EN))

+#define __HAL_RCC_ITCM_C2_DEALLOCATE()             (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_ITCMEN))

+#define __HAL_RCC_D1SRAM1_C2_DEALLOCATE()          (RCC_C2->AHB3ENR &= ~ (RCC_AHB3ENR_AXISRAMEN))

+

+/** @brief  Enable or disable the AHB1 peripheral clock.

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+

+#define __HAL_RCC_C2_DMA1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_DMA2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_DMA2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_ADC12_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ADC12EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_ART_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ARTEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_ETH1MAC_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1MACEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_ETH1TX_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1TXEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_ETH1RX_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_ETH1RXEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_USB1_OTG_HS_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB1OTGHSULPIEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_USB2_OTG_FS_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB1ENR, RCC_AHB1ENR_USB2OTGHSULPIEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+

+#define __HAL_RCC_C2_DMA1_CLK_DISABLE()             (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA1EN))

+#define __HAL_RCC_C2_DMA2_CLK_DISABLE()             (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_DMA2EN))

+#define __HAL_RCC_C2_ADC12_CLK_DISABLE()            (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ADC12EN))

+#define __HAL_RCC_C2_ART_CLK_DISABLE()              (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ARTEN))

+#define __HAL_RCC_C2_ETH1MAC_CLK_DISABLE()          (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1MACEN))

+#define __HAL_RCC_C2_ETH1TX_CLK_DISABLE()           (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1TXEN))

+#define __HAL_RCC_C2_ETH1RX_CLK_DISABLE()           (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_ETH1RXEN))

+#define __HAL_RCC_C2_USB1_OTG_HS_CLK_DISABLE()      (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSEN))

+#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB1OTGHSULPIEN))

+#define __HAL_RCC_C2_USB2_OTG_FS_CLK_DISABLE()      (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSEN))

+#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_DISABLE() (RCC_C2->AHB1ENR &= ~ (RCC_AHB1ENR_USB2OTGHSULPIEN))

+

+/** @brief  Enable or disable the AHB2 peripheral clock.

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+

+#define __HAL_RCC_C2_DCMI_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_DCMIEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#if defined(CRYP)

+#define __HAL_RCC_C2_CRYP_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_CRYPEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /* CRYP */

+

+#if defined(HASH)

+#define __HAL_RCC_C2_HASH_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_HASHEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+#endif /* HASH */

+

+#define __HAL_RCC_C2_RNG_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_RNGEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_SDMMC2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_SDMMC2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_D2SRAM1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_D2SRAM2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_D2SRAM3_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB2ENR, RCC_AHB2ENR_D2SRAM3EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_DCMI_CLK_DISABLE()             (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_DCMIEN))

+#if defined(CRYP)

+#define __HAL_RCC_C2_CRYP_CLK_DISABLE()             (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_CRYPEN))

+#endif /* CRYP */

+#if defined(HASH)

+#define __HAL_RCC_C2_HASH_CLK_DISABLE()             (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_HASHEN))

+#endif /* HASH */

+#define __HAL_RCC_C2_RNG_CLK_DISABLE()              (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_RNGEN))

+#define __HAL_RCC_C2_SDMMC2_CLK_DISABLE()           (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_SDMMC2EN))

+#define __HAL_RCC_C2_D2SRAM1_CLK_DISABLE()          (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM1EN))

+#define __HAL_RCC_C2_D2SRAM2_CLK_DISABLE()          (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM2EN))

+#define __HAL_RCC_C2_D2SRAM3_CLK_DISABLE()          (RCC_C2->AHB2ENR &= ~ (RCC_AHB2ENR_D2SRAM3EN))

+

+/** @brief  Enable or disable the AHB4 peripheral clock.

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+

+#define __HAL_RCC_C2_GPIOA_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOAEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_GPIOB_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOBEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_GPIOC_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOCEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_GPIOD_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIODEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_GPIOE_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOEEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_GPIOF_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOFEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_GPIOG_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOGEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_GPIOH_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOHEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_GPIOI_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOIEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_GPIOJ_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOJEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_GPIOK_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_GPIOKEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_CRC_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_CRCEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_BDMA_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BDMAEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_ADC3_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_ADC3EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_HSEM_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_HSEMEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_BKPRAM_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->AHB4ENR, RCC_AHB4ENR_BKPRAMEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+

+#define __HAL_RCC_C2_GPIOA_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOAEN)

+#define __HAL_RCC_C2_GPIOB_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOBEN)

+#define __HAL_RCC_C2_GPIOC_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOCEN)

+#define __HAL_RCC_C2_GPIOD_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIODEN)

+#define __HAL_RCC_C2_GPIOE_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOEEN)

+#define __HAL_RCC_C2_GPIOF_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOFEN)

+#define __HAL_RCC_C2_GPIOG_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOGEN)

+#define __HAL_RCC_C2_GPIOH_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOHEN)

+#define __HAL_RCC_C2_GPIOI_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOIEN)

+#define __HAL_RCC_C2_GPIOJ_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOJEN)

+#define __HAL_RCC_C2_GPIOK_CLK_DISABLE()           (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_GPIOKEN)

+#define __HAL_RCC_C2_CRC_CLK_DISABLE()             (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_CRCEN)

+#define __HAL_RCC_C2_BDMA_CLK_DISABLE()            (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BDMAEN)

+#define __HAL_RCC_C2_ADC3_CLK_DISABLE()            (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_ADC3EN)

+#define __HAL_RCC_C2_HSEM_CLK_DISABLE()            (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_HSEMEN)

+#define __HAL_RCC_C2_BKPRAM_CLK_DISABLE()          (RCC_C2->AHB4ENR) &= ~ (RCC_AHB4ENR_BKPRAMEN)

+

+

+/** @brief  Enable or disable the APB3 peripheral clock.

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+

+#define __HAL_RCC_C2_LTDC_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_LTDCEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_DSI_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_DSIEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_WWDG1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB3ENR, RCC_APB3ENR_WWDG1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_LTDC_CLK_DISABLE()           (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_LTDCEN)

+#define __HAL_RCC_C2_DSI_CLK_DISABLE()            (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_DSIEN)

+#define __HAL_RCC_C2_WWDG1_CLK_DISABLE()          (RCC_C2->APB3ENR) &= ~ (RCC_APB3ENR_WWDG1EN)

+

+/** @brief  Enable or disable the APB1 peripheral clock.

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+

+#define __HAL_RCC_C2_TIM2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_TIM3_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM3EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_TIM4_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM4EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_TIM5_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM5EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_TIM6_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM6EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_TIM7_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM7EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_TIM12_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM12EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_TIM13_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM13EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_TIM14_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_TIM14EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_LPTIM1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_LPTIM1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_WWDG2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_WWDG2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_SPI2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_SPI3_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPI3EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_SPDIFRX_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_SPDIFRXEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_USART2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_USART3_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_USART3EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_UART4_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART4EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_UART5_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART5EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_I2C1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_I2C2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_I2C3_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_I2C3EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_CEC_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_CECEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_DAC12_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_DAC12EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_UART7_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART7EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_UART8_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB1LENR, RCC_APB1LENR_UART8EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_CRS_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_CRSEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_SWPMI_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_SWPMIEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_OPAMP_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_OPAMPEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_MDIOS_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_MDIOSEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_FDCAN_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB1HENR, RCC_APB1HENR_FDCANEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+

+#define __HAL_RCC_C2_TIM2_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM2EN)

+#define __HAL_RCC_C2_TIM3_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM3EN)

+#define __HAL_RCC_C2_TIM4_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM4EN)

+#define __HAL_RCC_C2_TIM5_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM5EN)

+#define __HAL_RCC_C2_TIM6_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM6EN)

+#define __HAL_RCC_C2_TIM7_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM7EN)

+#define __HAL_RCC_C2_TIM12_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM12EN)

+#define __HAL_RCC_C2_TIM13_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM13EN)

+#define __HAL_RCC_C2_TIM14_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_TIM14EN)

+#define __HAL_RCC_C2_LPTIM1_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_LPTIM1EN)

+#define __HAL_RCC_C2_WWDG2_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_WWDG2EN)

+#define __HAL_RCC_C2_SPI2_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI2EN)

+#define __HAL_RCC_C2_SPI3_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPI3EN)

+#define __HAL_RCC_C2_SPDIFRX_CLK_DISABLE()        (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_SPDIFRXEN)

+#define __HAL_RCC_C2_USART2_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART2EN)

+#define __HAL_RCC_C2_USART3_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_USART3EN)

+#define __HAL_RCC_C2_UART4_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART4EN)

+#define __HAL_RCC_C2_UART5_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART5EN)

+#define __HAL_RCC_C2_I2C1_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C1EN)

+#define __HAL_RCC_C2_I2C2_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C2EN)

+#define __HAL_RCC_C2_I2C3_CLK_DISABLE()           (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_I2C3EN)

+#define __HAL_RCC_C2_CEC_CLK_DISABLE()            (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_CECEN)

+#define __HAL_RCC_C2_DAC12_CLK_DISABLE()          (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_DAC12EN)

+#define __HAL_RCC_C2_UART7_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART7EN)

+#define __HAL_RCC_C2_UART8_CLK_DISABLE()         (RCC_C2->APB1LENR) &= ~ (RCC_APB1LENR_UART8EN)

+#define __HAL_RCC_C2_CRS_CLK_DISABLE()            (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_CRSEN)

+#define __HAL_RCC_C2_SWPMI_CLK_DISABLE()          (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_SWPMIEN)

+#define __HAL_RCC_C2_OPAMP_CLK_DISABLE()          (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_OPAMPEN)

+#define __HAL_RCC_C2_MDIOS_CLK_DISABLE()          (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_MDIOSEN)

+#define __HAL_RCC_C2_FDCAN_CLK_DISABLE()          (RCC_C2->APB1HENR) &= ~ (RCC_APB1HENR_FDCANEN)

+

+/** @brief  Enable or disable the APB2 peripheral clock.

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+

+#define __HAL_RCC_C2_TIM1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_TIM8_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM8EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_USART1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_USART6_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_USART6EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_SPI1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_SPI4_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI4EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_TIM15_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM15EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_TIM16_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM16EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_TIM17_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_TIM17EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_SPI5_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SPI5EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_SAI1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_SAI2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_SAI3_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_SAI3EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_DFSDM1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_DFSDM1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_HRTIM1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB2ENR, RCC_APB2ENR_HRTIMEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_TIM1_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM1EN)

+#define __HAL_RCC_C2_TIM8_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM8EN)

+#define __HAL_RCC_C2_USART1_CLK_DISABLE()         (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART1EN)

+#define __HAL_RCC_C2_USART6_CLK_DISABLE()         (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_USART6EN)

+#define __HAL_RCC_C2_SPI1_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI1EN)

+#define __HAL_RCC_C2_SPI4_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI4EN)

+#define __HAL_RCC_C2_TIM15_CLK_DISABLE()          (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM15EN)

+#define __HAL_RCC_C2_TIM16_CLK_DISABLE()          (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM16EN)

+#define __HAL_RCC_C2_TIM17_CLK_DISABLE()          (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_TIM17EN)

+#define __HAL_RCC_C2_SPI5_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SPI5EN)

+#define __HAL_RCC_C2_SAI1_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI1EN)

+#define __HAL_RCC_C2_SAI2_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI2EN)

+#define __HAL_RCC_C2_SAI3_CLK_DISABLE()           (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_SAI3EN)

+#define __HAL_RCC_C2_DFSDM1_CLK_DISABLE()         (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_DFSDM1EN)

+#define __HAL_RCC_C2_HRTIM1_CLK_DISABLE()         (RCC_C2->APB2ENR) &= ~ (RCC_APB2ENR_HRTIMEN)

+

+/** @brief  Enable or disable the APB4 peripheral clock.

+  * @note   After reset, the peripheral clock (used for registers read/write access)

+  *         is disabled and the application software has to enable this clock before

+  *         using it.

+  */

+

+#define __HAL_RCC_C2_SYSCFG_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SYSCFGEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_LPUART1_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPUART1EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_SPI6_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SPI6EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_I2C4_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_I2C4EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_LPTIM2_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM2EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_LPTIM3_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM3EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_LPTIM4_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM4EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_LPTIM5_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_LPTIM5EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_COMP12_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_COMP12EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_VREF_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_VREFEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_RTC_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_RTCAPBEN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+#define __HAL_RCC_C2_SAI4_CLK_ENABLE()   do { \

+                                        __IO uint32_t tmpreg; \

+                                        SET_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\

+                                        /* Delay after an RCC peripheral clock enabling */ \

+                                        tmpreg = READ_BIT(RCC_C2->APB4ENR, RCC_APB4ENR_SAI4EN);\

+                                        UNUSED(tmpreg); \

+                                       } while(0)

+

+

+

+#define __HAL_RCC_C2_SYSCFG_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SYSCFGEN)

+#define __HAL_RCC_C2_LPUART1_CLK_DISABLE()          (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPUART1EN)

+#define __HAL_RCC_C2_SPI6_CLK_DISABLE()             (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SPI6EN)

+#define __HAL_RCC_C2_I2C4_CLK_DISABLE()             (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_I2C4EN)

+#define __HAL_RCC_C2_LPTIM2_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM2EN)

+#define __HAL_RCC_C2_LPTIM3_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM3EN)

+#define __HAL_RCC_C2_LPTIM4_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM4EN)

+#define __HAL_RCC_C2_LPTIM5_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_LPTIM5EN)

+#define __HAL_RCC_C2_COMP12_CLK_DISABLE()           (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_COMP12EN)

+#define __HAL_RCC_C2_VREF_CLK_DISABLE()             (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_VREFEN)

+#define __HAL_RCC_C2_RTC_CLK_DISABLE()              (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_RTCAPBEN)

+#define __HAL_RCC_C2_SAI4_CLK_DISABLE()             (RCC_C2->APB4ENR) &= ~ (RCC_APB4ENR_SAI4EN)

+

+#endif /*DUAL_CORE*/

+

+/** @brief  Enable or disable the AHB3 peripheral reset.

+  */

+

+#define __HAL_RCC_AHB3_FORCE_RESET()          (RCC->AHB3RSTR = 0x7FFFFFFFU)

+#define __HAL_RCC_MDMA_FORCE_RESET()          (RCC->AHB3RSTR |= (RCC_AHB3RSTR_MDMARST))

+#define __HAL_RCC_DMA2D_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_DMA2DRST))

+#if defined(JPEG)

+#define __HAL_RCC_JPGDECRST_FORCE_RESET()     (RCC->AHB3RSTR |= (RCC_AHB3RSTR_JPGDECRST))

+#endif /* JPEG */

+#define __HAL_RCC_FMC_FORCE_RESET()           (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))

+#if defined(QUADSPI)

+#define __HAL_RCC_QSPI_FORCE_RESET()          (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))

+#endif /*QUADSPI*/

+#if defined(OCTOSPI1)

+#define __HAL_RCC_OSPI1_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI1RST))

+#endif /*OCTOSPI1*/

+#define __HAL_RCC_SDMMC1_FORCE_RESET()        (RCC->AHB3RSTR |= (RCC_AHB3RSTR_SDMMC1RST))

+#if defined(OCTOSPI2)

+#define __HAL_RCC_OSPI2_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OSPI2RST))

+#endif /*OCTOSPI2*/

+#if defined(OCTOSPIM)

+#define __HAL_RCC_IOMNGR_FORCE_RESET()      (RCC->AHB3RSTR |= (RCC_AHB3RSTR_IOMNGRRST))

+#endif /*OCTOSPIM*/

+#if defined(OTFDEC1)

+#define __HAL_RCC_OTFDEC1_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC1RST))

+#endif /*OTFDEC1*/

+#if defined(OTFDEC2)

+#define __HAL_RCC_OTFDEC2_FORCE_RESET()         (RCC->AHB3RSTR |= (RCC_AHB3RSTR_OTFDEC2RST))

+#endif /*OTFDEC2*/

+#if defined(GFXMMU)

+#define __HAL_RCC_GFXMMU_FORCE_RESET()        (RCC->AHB3RSTR |= (RCC_AHB3RSTR_GFXMMURST))

+#endif /*GFXMMU*/

+

+#define __HAL_RCC_AHB3_RELEASE_RESET()        (RCC->AHB3RSTR = 0x00)

+#define __HAL_RCC_MDMA_RELEASE_RESET()        (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_MDMARST))

+#define __HAL_RCC_DMA2D_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_DMA2DRST))

+#if defined(JPEG)

+#define __HAL_RCC_JPGDECRST_RELEASE_RESET()   (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_JPGDECRST))

+#endif /* JPEG */

+#define __HAL_RCC_FMC_RELEASE_RESET()         (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_FMCRST))

+#if defined(QUADSPI)

+#define __HAL_RCC_QSPI_RELEASE_RESET()        (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_QSPIRST))

+#endif /*QUADSPI*/

+#if defined(OCTOSPI1)

+#define __HAL_RCC_OSPI1_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI1RST))

+#endif /*OCTOSPI1*/

+#define __HAL_RCC_SDMMC1_RELEASE_RESET()      (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_SDMMC1RST))

+#if defined(OCTOSPI2)

+#define __HAL_RCC_OSPI2_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OSPI2RST))

+#endif /*OCTOSPI2*/

+#if defined(OCTOSPIM)

+#define __HAL_RCC_IOMNGR_RELEASE_RESET()      (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_IOMNGRRST))

+#endif /*OCTOSPIM*/

+#if defined(OTFDEC1)

+#define __HAL_RCC_OTFDEC1_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC1RST))

+#endif /*OTFDEC1*/

+#if defined(OTFDEC2)

+#define __HAL_RCC_OTFDEC2_RELEASE_RESET()       (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_OTFDEC2RST))

+#endif /*OTFDEC2*/

+#if defined(GFXMMU)

+#define __HAL_RCC_GFXMMU_RELEASE_RESET()      (RCC->AHB3RSTR &= ~ (RCC_AHB3RSTR_GFXMMURST))

+#endif /*GFXMMU*/

+

+

+

+/** @brief  Force or release the AHB1 peripheral reset.

+  */

+#define __HAL_RCC_AHB1_FORCE_RESET()             (RCC->AHB1RSTR = 0xFFFFFFFFU)

+#define __HAL_RCC_DMA1_FORCE_RESET()             (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))

+#define __HAL_RCC_DMA2_FORCE_RESET()             (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))

+#define __HAL_RCC_ADC12_FORCE_RESET()            (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ADC12RST))

+#if defined(DUAL_CORE)

+#define __HAL_RCC_ART_FORCE_RESET()              (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ARTRST))

+#endif /*DUAL_CORE*/

+#if defined(RCC_AHB1RSTR_CRCRST)

+#define __HAL_RCC_CRC_FORCE_RESET()            (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))

+#endif

+#if defined(ETH)

+#define __HAL_RCC_ETH1MAC_FORCE_RESET()          (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETH1MACRST))

+#endif /*ETH*/

+#define __HAL_RCC_USB1_OTG_HS_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB1OTGHSRST))

+#if defined(USB2_OTG_FS)

+#define __HAL_RCC_USB2_OTG_FS_FORCE_RESET()      (RCC->AHB1RSTR |= (RCC_AHB1RSTR_USB2OTGHSRST))

+#endif /*USB2_OTG_FS*/

+

+#define __HAL_RCC_AHB1_RELEASE_RESET()           (RCC->AHB1RSTR = 0x00U)

+#define __HAL_RCC_DMA1_RELEASE_RESET()             (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA1RST))

+#define __HAL_RCC_DMA2_RELEASE_RESET()             (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_DMA2RST))

+#define __HAL_RCC_ADC12_RELEASE_RESET()            (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ADC12RST))

+#if defined(DUAL_CORE)

+#define __HAL_RCC_ART_RELEASE_RESET()              (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ARTRST))

+#endif /*DUAL_CORE*/

+#if defined(RCC_AHB1RSTR_CRCRST)

+#define __HAL_RCC_CRC_RELEASE_RESET()                (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_CRCRST))

+#endif

+#if defined(ETH)

+#define __HAL_RCC_ETH1MAC_RELEASE_RESET()          (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_ETH1MACRST))

+#endif /*ETH*/

+#define __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()      (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB1OTGHSRST))

+#if defined(USB2_OTG_FS)

+#define __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()      (RCC->AHB1RSTR &= ~ (RCC_AHB1RSTR_USB2OTGHSRST))

+#endif /*USB2_OTG_FS*/

+

+/** @brief  Force or release the AHB2 peripheral reset.

+  */

+#define __HAL_RCC_AHB2_FORCE_RESET()           (RCC->AHB2RSTR = 0xFFFFFFFFU)

+#if defined(DCMI) && defined(PSSI)

+#define __HAL_RCC_DCMI_PSSI_FORCE_RESET()        (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMI_PSSIRST))

+#define __HAL_RCC_DCMI_FORCE_RESET()             __HAL_RCC_DCMI_PSSI_FORCE_RESET()  /* for API backward compatibility*/

+#else

+#define __HAL_RCC_DCMI_FORCE_RESET()             (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))

+#endif /* DCMI && PSSI */

+#if defined(CRYP)

+#define __HAL_RCC_CRYP_FORCE_RESET()             (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))

+#endif /* CRYP */

+#if defined(HASH)

+#define __HAL_RCC_HASH_FORCE_RESET()             (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))

+#endif /* HASH */

+#define __HAL_RCC_RNG_FORCE_RESET()              (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))

+#define __HAL_RCC_SDMMC2_FORCE_RESET()           (RCC->AHB2RSTR |= (RCC_AHB2RSTR_SDMMC2RST))

+#if defined(RCC_AHB2RSTR_HSEMRST)

+#define __HAL_RCC_HSEM_FORCE_RESET()             (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HSEMRST))

+#endif

+#if defined(BDMA1)

+#define __HAL_RCC_BDMA1_FORCE_RESET()           (RCC->AHB2RSTR |= (RCC_AHB2RSTR_BDMA1RST))

+#endif /*BDMA1*/

+

+#define __HAL_RCC_AHB2_RELEASE_RESET()           (RCC->AHB2RSTR = 0x00U)

+#if defined(DCMI) && defined(PSSI)

+#define __HAL_RCC_DCMI_PSSI_RELEASE_RESET()        (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMI_PSSIRST))

+#define __HAL_RCC_DCMI_RELEASE_RESET()             __HAL_RCC_DCMI_PSSI_RELEASE_RESET()  /* for API backward compatibility*/

+#else

+#define __HAL_RCC_DCMI_RELEASE_RESET()             (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_DCMIRST))

+#endif /* DCMI && PSSI */

+#if defined(CRYP)

+#define __HAL_RCC_CRYP_RELEASE_RESET()             (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_CRYPRST))

+#endif /* CRYP */

+#if defined(HASH)

+#define __HAL_RCC_HASH_RELEASE_RESET()             (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HASHRST))

+#endif /* HASH */

+#define __HAL_RCC_RNG_RELEASE_RESET()              (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_RNGRST))

+#define __HAL_RCC_SDMMC2_RELEASE_RESET()           (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_SDMMC2RST))

+#if defined(RCC_AHB2RSTR_HSEMRST)

+#define __HAL_RCC_HSEM_RELEASE_RESET()             (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_HSEMRST))

+#endif

+#if defined(BDMA1)

+#define __HAL_RCC_BDMA1_RELEASE_RESET()           (RCC->AHB2RSTR &= ~ (RCC_AHB2RSTR_BDMA1RST))

+#endif /*BDMA1*/

+

+

+/** @brief  Force or release the AHB4 peripheral reset.

+  */

+

+#define __HAL_RCC_AHB4_FORCE_RESET()            (RCC->AHB4RSTR = 0xFFFFFFFFU)

+#define __HAL_RCC_GPIOA_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOARST)

+#define __HAL_RCC_GPIOB_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOBRST)

+#define __HAL_RCC_GPIOC_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOCRST)

+#define __HAL_RCC_GPIOD_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIODRST)

+#define __HAL_RCC_GPIOE_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOERST)

+#define __HAL_RCC_GPIOF_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOFRST)

+#define __HAL_RCC_GPIOG_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOGRST)

+#define __HAL_RCC_GPIOH_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOHRST)

+#define __HAL_RCC_GPIOI_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOIRST)

+#define __HAL_RCC_GPIOJ_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOJRST)

+#define __HAL_RCC_GPIOK_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_GPIOKRST)

+#if defined(RCC_AHB4RSTR_CRCRST)

+#define __HAL_RCC_CRC_FORCE_RESET()             (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_CRCRST)

+#endif

+#if defined(BDMA2)

+#define __HAL_RCC_BDMA2_FORCE_RESET()           (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMA2RST)

+#define __HAL_RCC_BDMA_FORCE_RESET()            __HAL_RCC_BDMA2_FORCE_RESET()         /* for API backward compatibility*/

+#else

+#define __HAL_RCC_BDMA_FORCE_RESET()            (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_BDMARST)

+#endif /*BDMA2*/

+#if defined(ADC3)

+#define __HAL_RCC_ADC3_FORCE_RESET()            (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_ADC3RST)

+#endif /*ADC3*/

+#if defined(RCC_AHB4RSTR_HSEMRST)

+#define __HAL_RCC_HSEM_FORCE_RESET()            (RCC->AHB4RSTR) |= (RCC_AHB4RSTR_HSEMRST)

+#endif

+

+#define __HAL_RCC_AHB4_RELEASE_RESET()          (RCC->AHB4RSTR = 0x00U)

+#define __HAL_RCC_GPIOA_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOARST)

+#define __HAL_RCC_GPIOB_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOBRST)

+#define __HAL_RCC_GPIOC_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOCRST)

+#define __HAL_RCC_GPIOD_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIODRST)

+#define __HAL_RCC_GPIOE_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOERST)

+#define __HAL_RCC_GPIOF_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOFRST)

+#define __HAL_RCC_GPIOG_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOGRST)

+#define __HAL_RCC_GPIOH_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOHRST)

+#define __HAL_RCC_GPIOI_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOIRST)

+#define __HAL_RCC_GPIOJ_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOJRST)

+#define __HAL_RCC_GPIOK_RELEASE_RESET()           (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_GPIOKRST)

+#if defined(RCC_AHB4RSTR_CRCRST)

+#define __HAL_RCC_CRC_RELEASE_RESET()             (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_CRCRST)

+#endif

+#if defined(BDMA2)

+#define __HAL_RCC_BDMA2_RELEASE_RESET()            (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMA2RST)

+#define __HAL_RCC_BDMA_RELEASE_RESET()   __HAL_RCC_BDMA2_RELEASE_RESET()      /* for API backward compatibility*/

+#else

+#define __HAL_RCC_BDMA_RELEASE_RESET()            (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_BDMARST)

+#endif /*BDMA2*/

+#if defined(ADC3)

+#define __HAL_RCC_ADC3_RELEASE_RESET()            (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_ADC3RST)

+#endif /*ADC3*/

+#if defined(RCC_AHB4RSTR_HSEMRST)

+#define __HAL_RCC_HSEM_RELEASE_RESET()            (RCC->AHB4RSTR) &= ~ (RCC_AHB4RSTR_HSEMRST)

+#endif

+

+/** @brief  Force or release the APB3 peripheral reset.

+  */

+#define __HAL_RCC_APB3_FORCE_RESET()         (RCC->APB3RSTR = 0xFFFFFFFFU)

+#if defined(LTDC)

+#define __HAL_RCC_LTDC_FORCE_RESET()           (RCC->APB3RSTR) |= (RCC_APB3RSTR_LTDCRST)

+#endif /* LTDC */

+#if defined(DSI)

+#define __HAL_RCC_DSI_FORCE_RESET()            (RCC->APB3RSTR) |= (RCC_APB3RSTR_DSIRST)

+#endif /*DSI*/

+

+#define __HAL_RCC_APB3_RELEASE_RESET()         (RCC->APB3RSTR = 0x00U)

+#if defined(LTDC)

+#define __HAL_RCC_LTDC_RELEASE_RESET()           (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_LTDCRST)

+#endif /* LTDC */

+#if defined(DSI)

+#define __HAL_RCC_DSI_RELEASE_RESET()            (RCC->APB3RSTR) &= ~ (RCC_APB3RSTR_DSIRST)

+#endif /*DSI*/

+

+/** @brief  Force or release the APB1 peripheral reset.

+  */

+#define __HAL_RCC_APB1L_FORCE_RESET()        (RCC->APB1LRSTR = 0xFFFFFFFFU)

+#define __HAL_RCC_APB1H_FORCE_RESET()        (RCC->APB1HRSTR = 0xFFFFFFFFU)

+#define __HAL_RCC_TIM2_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM2RST)

+#define __HAL_RCC_TIM3_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM3RST)

+#define __HAL_RCC_TIM4_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM4RST)

+#define __HAL_RCC_TIM5_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM5RST)

+#define __HAL_RCC_TIM6_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM6RST)

+#define __HAL_RCC_TIM7_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM7RST)

+#define __HAL_RCC_TIM12_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM12RST)

+#define __HAL_RCC_TIM13_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM13RST)

+#define __HAL_RCC_TIM14_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_TIM14RST)

+#define __HAL_RCC_LPTIM1_FORCE_RESET()         (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_LPTIM1RST)

+#define __HAL_RCC_SPI2_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI2RST)

+#define __HAL_RCC_SPI3_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPI3RST)

+#define __HAL_RCC_SPDIFRX_FORCE_RESET()        (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_SPDIFRXRST)

+#define __HAL_RCC_USART2_FORCE_RESET()         (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART2RST)

+#define __HAL_RCC_USART3_FORCE_RESET()         (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_USART3RST)

+#define __HAL_RCC_UART4_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART4RST)

+#define __HAL_RCC_UART5_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART5RST)

+#define __HAL_RCC_I2C1_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C1RST)

+#define __HAL_RCC_I2C2_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C2RST)

+#define __HAL_RCC_I2C3_FORCE_RESET()           (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_I2C3RST)

+#define __HAL_RCC_CEC_FORCE_RESET()            (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_CECRST)

+#define __HAL_RCC_DAC12_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_DAC12RST)

+#define __HAL_RCC_UART7_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART7RST)

+#define __HAL_RCC_UART8_FORCE_RESET()          (RCC->APB1LRSTR) |= (RCC_APB1LRSTR_UART8RST)

+#define __HAL_RCC_CRS_FORCE_RESET()            (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_CRSRST)

+#define __HAL_RCC_SWPMI1_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_SWPMIRST)

+#define __HAL_RCC_OPAMP_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_OPAMPRST)

+#define __HAL_RCC_MDIOS_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_MDIOSRST)

+#define __HAL_RCC_FDCAN_FORCE_RESET()          (RCC->APB1HRSTR) |= (RCC_APB1HRSTR_FDCANRST)

+

+#define __HAL_RCC_APB1L_RELEASE_RESET()       (RCC->APB1LRSTR = 0x00U)

+#define __HAL_RCC_APB1H_RELEASE_RESET()       (RCC->APB1HRSTR = 0x00U)

+#define __HAL_RCC_TIM2_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM2RST)

+#define __HAL_RCC_TIM3_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM3RST)

+#define __HAL_RCC_TIM4_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM4RST)

+#define __HAL_RCC_TIM5_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM5RST)

+#define __HAL_RCC_TIM6_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM6RST)

+#define __HAL_RCC_TIM7_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM7RST)

+#define __HAL_RCC_TIM12_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM12RST)

+#define __HAL_RCC_TIM13_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM13RST)

+#define __HAL_RCC_TIM14_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_TIM14RST)

+#define __HAL_RCC_LPTIM1_RELEASE_RESET()         (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_LPTIM1RST)

+#define __HAL_RCC_SPI2_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI2RST)

+#define __HAL_RCC_SPI3_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPI3RST)

+#define __HAL_RCC_SPDIFRX_RELEASE_RESET()        (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_SPDIFRXRST)

+#define __HAL_RCC_USART2_RELEASE_RESET()         (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART2RST)

+#define __HAL_RCC_USART3_RELEASE_RESET()         (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_USART3RST)

+#define __HAL_RCC_UART4_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART4RST)

+#define __HAL_RCC_UART5_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART5RST)

+#define __HAL_RCC_I2C1_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C1RST)

+#define __HAL_RCC_I2C2_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C2RST)

+#define __HAL_RCC_I2C3_RELEASE_RESET()           (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_I2C3RST)

+#define __HAL_RCC_CEC_RELEASE_RESET()            (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_CECRST)

+#define __HAL_RCC_DAC12_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_DAC12RST)

+#define __HAL_RCC_UART7_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART7RST)

+#define __HAL_RCC_UART8_RELEASE_RESET()          (RCC->APB1LRSTR) &= ~ (RCC_APB1LRSTR_UART8RST)

+#define __HAL_RCC_CRS_RELEASE_RESET()            (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_CRSRST)

+#define __HAL_RCC_SWPMI1_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_SWPMIRST)

+#define __HAL_RCC_OPAMP_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_OPAMPRST)

+#define __HAL_RCC_MDIOS_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_MDIOSRST)

+#define __HAL_RCC_FDCAN_RELEASE_RESET()          (RCC->APB1HRSTR) &= ~ (RCC_APB1HRSTR_FDCANRST)

+

+/** @brief  Force or release the APB2 peripheral reset.

+  */

+#define __HAL_RCC_APB2_FORCE_RESET()         (RCC->APB2RSTR = 0xFFFFFFFFU)

+#define __HAL_RCC_TIM1_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM1RST)

+#define __HAL_RCC_TIM8_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM8RST)

+#define __HAL_RCC_USART1_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART1RST)

+#define __HAL_RCC_USART6_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART6RST)

+#if defined(UART9)

+#define __HAL_RCC_UART9_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_UART9RST)

+#endif /*UART9*/

+#if defined(USART10)

+#define __HAL_RCC_USART10_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_USART10RST)

+#endif /*USART10*/

+#define __HAL_RCC_SPI1_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI1RST)

+#define __HAL_RCC_SPI4_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI4RST)

+#define __HAL_RCC_TIM15_FORCE_RESET()          (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM15RST)

+#define __HAL_RCC_TIM16_FORCE_RESET()          (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM16RST)

+#define __HAL_RCC_TIM17_FORCE_RESET()          (RCC->APB2RSTR) |= (RCC_APB2RSTR_TIM17RST)

+#define __HAL_RCC_SPI5_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SPI5RST)

+#define __HAL_RCC_SAI1_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI1RST)

+#define __HAL_RCC_SAI2_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI2RST)

+#if defined(SAI3)

+#define __HAL_RCC_SAI3_FORCE_RESET()           (RCC->APB2RSTR) |= (RCC_APB2RSTR_SAI3RST)

+#endif /*SAI3*/

+#define __HAL_RCC_DFSDM1_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_DFSDM1RST)

+#if defined(HRTIM1)

+#define __HAL_RCC_HRTIM1_FORCE_RESET()         (RCC->APB2RSTR) |= (RCC_APB2RSTR_HRTIMRST)

+#endif /*HRTIM1*/

+

+#define __HAL_RCC_APB2_RELEASE_RESET()         (RCC->APB2RSTR = 0x00U)

+#define __HAL_RCC_TIM1_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM1RST)

+#define __HAL_RCC_TIM8_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM8RST)

+#define __HAL_RCC_USART1_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART1RST)

+#define __HAL_RCC_USART6_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART6RST)

+#if defined(UART9)

+#define __HAL_RCC_UART9_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_UART9RST)

+#endif /*UART9*/

+#if defined(USART10)

+#define __HAL_RCC_USART10_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_USART10RST)

+#endif /*USART10*/

+#define __HAL_RCC_SPI1_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI1RST)

+#define __HAL_RCC_SPI4_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI4RST)

+#define __HAL_RCC_TIM15_RELEASE_RESET()          (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM15RST)

+#define __HAL_RCC_TIM16_RELEASE_RESET()          (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM16RST)

+#define __HAL_RCC_TIM17_RELEASE_RESET()          (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_TIM17RST)

+#define __HAL_RCC_SPI5_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SPI5RST)

+#define __HAL_RCC_SAI1_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI1RST)

+#define __HAL_RCC_SAI2_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI2RST)

+#if defined(SAI3)

+#define __HAL_RCC_SAI3_RELEASE_RESET()           (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_SAI3RST)

+#endif /*SAI3*/

+#define __HAL_RCC_DFSDM1_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_DFSDM1RST)

+#if defined(HRTIM1)

+#define __HAL_RCC_HRTIM1_RELEASE_RESET()         (RCC->APB2RSTR) &= ~ (RCC_APB2RSTR_HRTIMRST)

+#endif /*HRTIM1*/

+

+/** @brief  Force or release the APB4 peripheral reset.

+  */

+

+#define __HAL_RCC_APB4_FORCE_RESET()           (RCC->APB4RSTR = 0xFFFFFFFFU)

+#define __HAL_RCC_SYSCFG_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_SYSCFGRST)

+#define __HAL_RCC_LPUART1_FORCE_RESET()          (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPUART1RST)

+#define __HAL_RCC_SPI6_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_SPI6RST)

+#define __HAL_RCC_I2C4_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_I2C4RST)

+#define __HAL_RCC_LPTIM2_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM2RST)

+#define __HAL_RCC_LPTIM3_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM3RST)

+#if defined(LPTIM4)

+#define __HAL_RCC_LPTIM4_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM4RST)

+#endif /*LPTIM4*/

+#if defined(LPTIM5)

+#define __HAL_RCC_LPTIM5_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_LPTIM5RST)

+#endif /*LPTIM5*/

+#if defined(DAC2)

+#define __HAL_RCC_DAC2_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_DAC2RST)

+#endif /*DAC2*/

+#define __HAL_RCC_COMP12_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_COMP12RST)

+#define __HAL_RCC_VREF_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_VREFRST)

+#if defined(SAI4)

+#define __HAL_RCC_SAI4_FORCE_RESET()             (RCC->APB4RSTR) |= (RCC_APB4RSTR_SAI4RST)

+#endif /*SAI4*/

+#if defined(DTS)

+#define __HAL_RCC_DTS_FORCE_RESET()              (RCC->APB4RSTR) |= (RCC_APB4RSTR_DTSRST)

+#endif /*DTS*/

+#if defined(DFSDM2_BASE)

+#define __HAL_RCC_DFSDM2_FORCE_RESET()           (RCC->APB4RSTR) |= (RCC_APB4RSTR_DFSDM2RST)

+#endif /*DFSDM2*/

+

+#define __HAL_RCC_APB4_RELEASE_RESET()           (RCC->APB4RSTR = 0x00U)

+#define __HAL_RCC_SYSCFG_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SYSCFGRST)

+#define __HAL_RCC_LPUART1_RELEASE_RESET()          (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPUART1RST)

+#define __HAL_RCC_SPI6_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SPI6RST)

+#define __HAL_RCC_I2C4_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_I2C4RST)

+#define __HAL_RCC_LPTIM2_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM2RST)

+#define __HAL_RCC_LPTIM3_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM3RST)

+#if defined(LPTIM4)

+#define __HAL_RCC_LPTIM4_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM4RST)

+#endif /*LPTIM4*/

+#if defined(LPTIM5)

+#define __HAL_RCC_LPTIM5_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_LPTIM5RST)

+#endif /*LPTIM5*/

+#if defined(RCC_APB4RSTR_DAC2RST)

+#define __HAL_RCC_DAC2_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DAC2RST)

+#endif

+#define __HAL_RCC_COMP12_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_COMP12RST)

+#define __HAL_RCC_VREF_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_VREFRST)

+#if defined(SAI4)

+#define __HAL_RCC_SAI4_RELEASE_RESET()             (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_SAI4RST)

+#endif /*SAI4*/

+#if defined(DTS)

+#define __HAL_RCC_DTS_RELEASE_RESET()              (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DTSRST)

+#endif /*DTS*/

+#if defined(DFSDM2_BASE)

+#define __HAL_RCC_DFSDM2_RELEASE_RESET()           (RCC->APB4RSTR) &= ~ (RCC_APB4RSTR_DFSDM2RST)

+#endif /*DFSDM2*/

+

+/** @brief  Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.

+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.

+  */

+

+

+#define __HAL_RCC_MDMA_CLK_SLEEP_ENABLE()            (RCC->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))

+#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))

+#if defined(JPEG)

+#define __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))

+#endif /* JPEG */

+#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))

+#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE()             (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))

+#if defined(QUADSPI)

+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE()            (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))

+#endif /*QUADSPI*/

+#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))

+#if defined(OCTOSPI1)

+#define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI1LPEN))

+#endif /*OCTOSPI1*/

+#if defined(OCTOSPI2)

+#define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OSPI2LPEN))

+#endif /*OCTOSPI2*/

+#if defined(OCTOSPIM)

+#define __HAL_RCC_IOMNGR_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_IOMNGRLPEN))

+#endif /*OCTOSPIM*/

+#if defined(OTFDEC1)

+#define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC1LPEN))

+#endif /*OTFDEC1*/

+#if defined(OTFDEC2)

+#define __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_OTFDEC2LPEN))

+#endif /*OTFDEC2*/

+#if defined(GFXMMU)

+#define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_GFXMMULPEN))

+#endif /*GFXMMU*/

+#if defined(CD_AXISRAM2_BASE)

+#define __HAL_RCC_AXISRAM2_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM2LPEN))

+#endif

+#if defined(CD_AXISRAM3_BASE)

+#define __HAL_RCC_AXISRAM3_CLK_SLEEP_ENABLE()          (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM3LPEN))

+#endif

+#define __HAL_RCC_DTCM1_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))

+#define __HAL_RCC_DTCM2_CLK_SLEEP_ENABLE()           (RCC->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))

+#define __HAL_RCC_ITCM_CLK_SLEEP_ENABLE()            (RCC->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))

+#if defined(RCC_AHB3LPENR_AXISRAMLPEN)

+#define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE()         (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))

+#define __HAL_RCC_AXISRAM_CLK_SLEEP_ENABLE           __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE

+#else

+#define __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE()        (RCC->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAM1LPEN))

+#define __HAL_RCC_D1SRAM1_CLK_SLEEP_ENABLE           __HAL_RCC_AXISRAM1_CLK_SLEEP_ENABLE  /* For backward compatibility */

+#endif /* RCC_AHB3LPENR_AXISRAMLPEN */

+

+#define __HAL_RCC_MDMA_CLK_SLEEP_DISABLE()            (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))

+#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))

+#if defined(JPEG)

+#define __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE()          (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))

+#endif /* JPEG */

+#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))

+#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE()             (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))

+#if defined(QUADSPI)

+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE()            (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))

+#endif /*QUADSPI*/

+#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE()          (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))

+#if defined(OCTOSPI1)

+#define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI1LPEN))

+#endif /*OCTOSPI1*/

+#if defined(OCTOSPI2)

+#define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OSPI2LPEN))

+#endif /*OCTOSPI2*/

+#if defined(OCTOSPIM)

+#define __HAL_RCC_IOMNGR_CLK_SLEEP_DISABLE()          (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_IOMNGRLPEN))

+#endif /*OCTOSPIM*/

+#if defined(OTFDEC1)

+#define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC1LPEN))

+#endif /*OTFDEC1*/

+#if defined(OTFDEC2)

+#define __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_OTFDEC2LPEN))

+#endif /*OTFDEC2*/

+#if defined(GFXMMU)

+#define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_GFXMMULPEN))

+#endif /*GFXMMU*/

+#if defined(CD_AXISRAM2_BASE)

+#define __HAL_RCC_AXISRAM2_CLK_SLEEP_DISABLE()         (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM2LPEN))

+#endif

+#if defined(CD_AXISRAM3_BASE)

+#define __HAL_RCC_AXISRAM3_CLK_SLEEP_DISABLE()         (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM3LPEN))

+#endif

+#define __HAL_RCC_DTCM1_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))

+#define __HAL_RCC_DTCM2_CLK_SLEEP_DISABLE()           (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))

+#define __HAL_RCC_ITCM_CLK_SLEEP_DISABLE()            (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))

+#if defined(RCC_AHB3LPENR_AXISRAMLPEN)

+#define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE()         (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))

+#define __HAL_RCC_AXISRAM_CLK_SLEEP_DISABLE           __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE

+#else

+#define __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE()        (RCC->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAM1LPEN))

+#define __HAL_RCC_D1SRAM1_CLK_SLEEP_DISABLE          __HAL_RCC_AXISRAM1_CLK_SLEEP_DISABLE      /* For backward compatibility */

+#endif  /* RCC_AHB3LPENR_AXISRAMLPEN */

+

+/** @brief  Get the enable or disable status of the AHB3 peripheral clock during Low Poser (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.

+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.

+  */

+

+#define __HAL_RCC_MDMA_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN)    != 0U)

+#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN)   != 0U)

+#if defined(JPEG)

+#define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN)  != 0U)

+#endif /* JPEG */

+#define __HAL_RCC_FLASH_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN)   != 0U)

+#define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN)     != 0U)

+#if defined(QUADSPI)

+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN)    != 0U)

+#endif /*QUADSPI*/

+#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN)  != 0U)

+#if defined(OCTOSPI1)

+#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN)    != 0U)

+#endif /*OCTOSPI1*/

+#if defined(OCTOSPI2)

+#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN)    != 0U)

+#endif /*OCTOSPI2*/

+#if defined(OCTOSPIM)

+#define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN)   != 0U)

+#endif /*OCTOSPIM*/

+#if defined(OTFDEC1)

+#define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN) != 0U)

+#endif /*OTFDEC1*/

+#if defined(OTFDEC2)

+#define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN) != 0U)

+#endif /*OTFDEC2*/

+#if defined(GFXMMU)

+#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN)    != 0U)

+#endif /*GFXMMU*/

+#if defined(CD_AXISRAM2_BASE)

+#define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN)   != 0U)

+#endif

+#if defined(CD_AXISRAM3_BASE)

+#define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN)   != 0U)

+#endif

+#define __HAL_RCC_DTCM1_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN)   != 0U)

+#define __HAL_RCC_DTCM2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN)   != 0U)

+#define __HAL_RCC_ITCM_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN)    != 0U)

+#if defined(RCC_AHB3LPENR_AXISRAMLPEN)

+#define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) != 0U)

+#else

+#define __HAL_RCC_AXISRAM1_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM1LPEN) != 0U)

+#endif

+

+#define __HAL_RCC_MDMA_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_MDMALPEN)    == 0U)

+#define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_DMA2DLPEN)   == 0U)

+#if defined(JPEG)

+#define __HAL_RCC_JPGDEC_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB3LPENR & RCC_AHB3LPENR_JPGDECLPEN)  == 0U)

+#endif /* JPEG */

+#define __HAL_RCC_FLASH_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_FLASHLPEN)   == 0U)

+#define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB3LPENR & RCC_AHB3LPENR_FMCLPEN)     == 0U)

+#if defined(QUADSPI)

+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_QSPILPEN)    == 0U)

+#endif /*QUADSPI*/

+#define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB3LPENR & RCC_AHB3LPENR_SDMMC1LPEN)  == 0U)

+#if defined(OCTOSPI1)

+#define __HAL_RCC_OSPI1_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI1LPEN)  == 0U)

+#endif /*OCTOSPI1*/

+#if defined(OCTOSPI2)

+#define __HAL_RCC_OSPI2_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OSPI2LPEN)  == 0U)

+#endif /*OCTOSPI2*/

+#if defined(OCTOSPIM)

+#define __HAL_RCC_IOMNGR_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_IOMNGRLPEN) == 0U)

+#endif /*OCTOSPIM*/

+#if defined(OTFDEC1)

+#define __HAL_RCC_OTFDEC1_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC1LPEN)  == 0U)

+#endif /*OTFDEC1*/

+#if defined(OTFDEC2)

+#define __HAL_RCC_OTFDEC2_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_OTFDEC2LPEN)  == 0U)

+#endif /*OTFDEC2*/

+#if defined(GFXMMU)

+#define __HAL_RCC_GFXMMU_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_GFXMMULPEN)  == 0U)

+#endif /*GFXMMU*/

+#if defined(CD_AXISRAM2_BASE)

+#define __HAL_RCC_AXISRAM2_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM2LPEN)  == 0U)

+#endif

+#if defined(CD_AXISRAM3_BASE)

+#define __HAL_RCC_AXISRAM3_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAM3LPEN)  == 0U)

+#endif

+#define __HAL_RCC_DTCM1_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM1LPEN)   == 0U)

+#define __HAL_RCC_DTCM2_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB3LPENR & RCC_AHB3LPENR_DTCM2LPEN)   == 0U)

+#define __HAL_RCC_ITCM_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB3LPENR & RCC_AHB3LPENR_ITCMLPEN)    == 0U)

+#if defined(RCC_AHB3LPENR_AXISRAMLPEN)

+#define __HAL_RCC_D1SRAM1_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAMLPEN) == 0U)

+#else

+#define __HAL_RCC_AXISRAM1_IS_CLK_SLEEP_DISABLED()        ((RCC->AHB3LPENR & RCC_AHB3LPENR_AXISRAML1PEN) == 0U)

+#endif /* RCC_AHB3LPENR_AXISRAMLPEN */

+

+/** @brief  ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

+  */

+

+#define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE()             (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))

+#define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE()             (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))

+#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE()            (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))

+#if defined(RCC_AHB1LPENR_CRCLPEN)

+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()              (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))

+#endif

+#if defined(ETH)

+#define __HAL_RCC_ETH1MAC_CLK_SLEEP_ENABLE()          (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))

+#endif /*ETH*/

+#if defined(DUAL_CORE)

+#define __HAL_RCC_ART_CLK_SLEEP_ENABLE()              (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ARTLPEN))

+#endif /*DUAL_CORE*/

+#if defined(ETH)

+#define __HAL_RCC_ETH1TX_CLK_SLEEP_ENABLE()           (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))

+#define __HAL_RCC_ETH1RX_CLK_SLEEP_ENABLE()           (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))

+#endif /*ETH*/

+#define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))

+#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))

+#if defined(USB2_OTG_FS)

+#define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()      (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))

+#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))

+#endif /* USB2_OTG_FS */

+

+#define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE()             (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))

+#define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE()             (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))

+#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE()            (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))

+#if defined(RCC_AHB1LPENR_CRCLPEN)

+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()              (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_CRCLPEN))

+#endif

+#if defined(ETH)

+#define __HAL_RCC_ETH1MAC_CLK_SLEEP_DISABLE()          (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))

+#endif  /*ETH*/

+#if defined(DUAL_CORE)

+#define __HAL_RCC_ART_CLK_SLEEP_DISABLE()              (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ARTLPEN))

+#endif /*DUAL_CORE*/

+#if defined(ETH)

+#define __HAL_RCC_ETH1TX_CLK_SLEEP_DISABLE()           (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))

+#define __HAL_RCC_ETH1RX_CLK_SLEEP_DISABLE()           (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))

+#endif  /*ETH*/

+#define __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()      (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))

+#define __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))

+#if defined(USB2_OTG_FS)

+#define __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()      (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))

+#define __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))

+#endif /* USB2_OTG_FS */

+

+/** @brief  Get the enable or disable status of the AHB1 peripheral clock during Low Poser (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.

+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.

+  */

+

+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN))          != 0U)

+#define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN))          != 0U)

+#define __HAL_RCC_ADC12_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN))         != 0U)

+#if defined(RCC_AHB1LPENR_CRCLPEN)

+#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()                ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN))         != 0U)

+#endif

+#if defined(ETH)

+#define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN))       != 0U)

+#endif  /*ETH*/

+#if defined(DUAL_CORE)

+#define __HAL_RCC_ART_IS_CLK_SLEEP_ENABLED()               ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN))       != 0U)

+#endif /*DUAL_CORE*/

+#if defined(ETH)

+#define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN))        != 0U)

+#define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN))        != 0U)

+#endif  /*ETH*/

+#define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_ENABLED()       ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN))     != 0U)

+#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) != 0U)

+#if defined(USB2_OTG_FS)

+#define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_ENABLED()       ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN))     != 0U)

+#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_ENABLED()  ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) != 0U)

+#endif /* USB2_OTG_FS */

+

+#define __HAL_RCC_DMA1_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA1LPEN))          == 0U)

+#define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN))          == 0U)

+#define __HAL_RCC_ADC12_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ADC12LPEN))         == 0U)

+#if defined(RCC_AHB1LPENR_CRCLPEN)

+#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()              ((RCC->AHB1LPENR & (RCC_AHB1LPENR_CRCLPEN))           == 0U)

+#endif

+#if defined(ETH)

+#define __HAL_RCC_ETH1MAC_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1MACLPEN))       == 0U)

+#endif /* ETH */

+#if defined(DUAL_CORE)

+#define __HAL_RCC_ART_IS_CLK_SLEEP_DISABLED()              ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ARTLPEN))           == 0U)

+#endif /*DUAL_CORE*/

+#if defined(ETH)

+#define __HAL_RCC_ETH1TX_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1TXLPEN))        == 0U)

+#define __HAL_RCC_ETH1RX_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETH1RXLPEN))        == 0U)

+#endif /* ETH */

+#define __HAL_RCC_USB1_OTG_HS_IS_CLK_SLEEP_DISABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSLPEN))     == 0U)

+#define __HAL_RCC_USB1_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB1OTGHSULPILPEN)) == 0U)

+#if defined(USB2_OTG_FS)

+#define __HAL_RCC_USB2_OTG_FS_IS_CLK_SLEEP_DISABLED()      ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSLPEN))     == 0U)

+#define __HAL_RCC_USB2_OTG_FS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_USB2OTGHSULPILPEN)) == 0U)

+#endif /* USB2_OTG_FS */

+

+

+/** @brief  ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

+  */

+

+#if defined(DCMI) && defined(PSSI)

+#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE()        (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMI_PSSILPEN))

+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()             __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE()  /* for API backward compatibility*/

+#else

+#define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE()             (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))

+#endif /* DCMI && PSSI */

+#if defined(CRYP)

+#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE()             (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))

+#endif /* CRYP */

+#if defined(HASH)

+#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE()             (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))

+#endif /* HASH */

+#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE()              (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))

+#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE()           (RCC->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))

+#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)

+#define __HAL_RCC_DFSDMDMA_CLK_SLEEP_ENABLE()         (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DFSDMDMALPEN))

+#endif

+#if defined(RCC_AHB2LPENR_D2SRAM1LPEN)

+#define __HAL_RCC_D2SRAM1_CLK_SLEEP_ENABLE()          (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))

+#else

+#define __HAL_RCC_AHBSRAM1_CLK_SLEEP_ENABLE()         (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM1LPEN))

+#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */

+#if defined(RCC_AHB2LPENR_D2SRAM2LPEN)

+#define __HAL_RCC_D2SRAM2_CLK_SLEEP_ENABLE()          (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))

+#else

+#define __HAL_RCC_AHBSRAM2_CLK_SLEEP_ENABLE()         (RCC->AHB2LPENR |= (RCC_AHB2LPENR_AHBSRAM2LPEN))

+#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */

+#if defined(RCC_AHB2LPENR_D2SRAM3LPEN)

+#define __HAL_RCC_D2SRAM3_CLK_SLEEP_ENABLE()          (RCC->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))

+#endif

+

+#if defined(DCMI) && defined(PSSI)

+#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE()        (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMI_PSSILPEN))

+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE()             __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE()  /* for API backward compatibility*/

+#else

+#define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE()             (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))

+#endif /* DCMI && PSSI */

+#if defined(CRYP)

+#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE()             (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))

+#endif /* CRYP */

+#if defined(HASH)

+#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE()             (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))

+#endif /* HASH */

+#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE()              (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))

+#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE()           (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))

+#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)

+#define __HAL_RCC_DFSDMDMA_CLK_SLEEP_DISABLE()         (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_DFSDMDMALPEN))

+#endif

+#if defined(RCC_AHB2LPENR_D2SRAM1LPEN)

+#define __HAL_RCC_D2SRAM1_CLK_SLEEP_DISABLE()          (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))

+#else

+#define __HAL_RCC_AHBSRAM1_CLK_SLEEP_DISABLE()         (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM1LPEN))

+#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */

+#if defined(RCC_AHB2LPENR_D2SRAM2LPEN)

+#define __HAL_RCC_D2SRAM2_CLK_SLEEP_DISABLE()          (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))

+#else

+#define __HAL_RCC_AHBSRAM2_CLK_SLEEP_DISABLE()          (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_AHBSRAM2LPEN))

+#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */

+#if defined(RCC_AHB2LPENR_D2SRAM3LPEN)

+#define __HAL_RCC_D2SRAM3_CLK_SLEEP_DISABLE()          (RCC->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))

+#endif

+

+/** @brief  Get the enable or disable status of the AHB2 peripheral clock during Low Poser (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.

+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.

+  */

+

+#if defined(DCMI) && defined(PSSI)

+#define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN))    != 0U)

+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED()              __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_ENABLED()  /* for API backward compatibility*/

+#else

+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN))    != 0U)

+#endif /* DCMI && PSSI */

+#if defined(CRYP)

+#define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN))    != 0U)

+#endif /* CRYP */

+#if defined(HASH)

+#define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN))    != 0U)

+#endif /* HASH */

+#define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED()               ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN))     != 0U)

+#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN))  != 0U)

+#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)

+#define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) != 0U)

+#endif

+#if defined(RCC_AHB2LPENR_D2SRAM1LPEN)

+#define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) != 0U)

+#else

+#define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) != 0U)

+#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */

+#if defined(RCC_AHB2LPENR_D2SRAM2LPEN)

+#define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) != 0U)

+#else

+#define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) != 0U)

+#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */

+#if defined(RCC_AHB2LPENR_D2SRAM3LPEN)

+#define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) != 0U)

+#endif /* RCC_AHB2LPENR_D2SRAM3LPEN */

+

+#if defined(DCMI) && defined(PSSI)

+#define __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED()        ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMI_PSSILPEN))    == 0U)

+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED()             __HAL_RCC_DCMI_PSSI_IS_CLK_SLEEP_DISABLED()  /* for API backward compatibility*/

+#else

+#define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN))    == 0U)

+#endif /* DCMI && PSSI */

+#if defined(CRYP)

+#define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN))    == 0U)

+#endif /* CRYP */

+#if defined(HASH)

+#define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN))    == 0U)

+#endif /* HASH */

+#define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED()              ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN))     == 0U)

+#if defined(RCC_AHB2LPENR_DFSDMDMALPEN)

+#define __HAL_RCC_DFSDMDMA_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DFSDMDMALPEN)) == 0U)

+#endif

+#define __HAL_RCC_SDMMC2_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB2LPENR & (RCC_AHB2LPENR_SDMMC2LPEN))  == 0U)

+#if defined(RCC_AHB2LPENR_D2SRAM1LPEN)

+#define __HAL_RCC_D2SRAM1_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM1LPEN)) == 0U)

+#else

+#define __HAL_RCC_AHBSRAM1_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM1LPEN)) == 0U)

+#endif /* RCC_AHB2LPENR_D2SRAM1LPEN */

+#if defined(RCC_AHB2LPENR_D2SRAM2LPEN)

+#define __HAL_RCC_D2SRAM2_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM2LPEN)) == 0U)

+#else

+#define __HAL_RCC_AHBSRAM2_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB2LPENR & (RCC_AHB2LPENR_AHBSRAM2LPEN)) == 0U)

+#endif /* RCC_AHB2LPENR_D2SRAM2LPEN */

+#if defined(RCC_AHB2LPENR_D2SRAM3LPEN)

+#define __HAL_RCC_D2SRAM3_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB2LPENR & (RCC_AHB2LPENR_D2SRAM3LPEN)) == 0U)

+#endif /* RCC_AHB2LPENR_D2SRAM1LPEN*/

+

+

+/** @brief  ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

+  */

+

+#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)

+#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)

+#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)

+#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)

+#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)

+#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)

+#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)

+#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)

+#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)

+#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)

+#define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE()           (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)

+#if defined(RCC_AHB4LPENR_CRCLPEN)

+#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE()             (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)

+#endif

+#if defined(BDMA2)

+#define __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE()            (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMA2LPEN)

+#define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE  __HAL_RCC_BDMA2_CLK_SLEEP_ENABLE /* for API backward compatibility*/

+#else

+#define __HAL_RCC_BDMA_CLK_SLEEP_ENABLE()            (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)

+#endif /* BDMA2 */

+#if defined(ADC3)

+#define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE()            (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)

+#endif /* ADC3 */

+#define __HAL_RCC_BKPRAM_CLK_SLEEP_ENABLE()          (RCC->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)

+#if defined(RCC_AHB4LPENR_SRDSRAMLPEN)

+#define __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE()         (RCC->AHB4LPENR  |= (RCC_AHB4LPENR_SRDSRAMLPEN))

+#define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE  __HAL_RCC_SRDSRAM_CLK_SLEEP_ENABLE /* for API backward compatibility*/

+#else

+#define __HAL_RCC_D3SRAM1_CLK_SLEEP_ENABLE()         (RCC->AHB4LPENR  |= (RCC_AHB4LPENR_D3SRAM1LPEN))

+#endif /* RCC_AHB4LPENR_SRDSRAMLPEN */

+

+#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)

+#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)

+#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)

+#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)

+#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)

+#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)

+#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)

+#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)

+#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)

+#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)

+#define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE()           (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)

+#if defined(RCC_AHB4LPENR_CRCLPEN)

+#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE()             (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)

+#endif

+#if defined(BDMA2)

+#define __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE()            (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMA2LPEN)

+#define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE  __HAL_RCC_BDMA2_CLK_SLEEP_DISABLE  /* For API backward compatibility*/

+#else

+#define __HAL_RCC_BDMA_CLK_SLEEP_DISABLE()            (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)

+#endif /*BDMA2*/

+#if defined(ADC3)

+#define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE()            (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)

+#endif /*ADC3*/

+#define __HAL_RCC_BKPRAM_CLK_SLEEP_DISABLE()          (RCC->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)

+#if defined(RCC_AHB4LPENR_SRDSRAMLPEN)

+#define __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE()         (RCC->AHB4LPENR  &= ~ (RCC_AHB4LPENR_SRDSRAMLPEN))

+#define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE  __HAL_RCC_SRDSRAM_CLK_SLEEP_DISABLE

+#else

+#define __HAL_RCC_D3SRAM1_CLK_SLEEP_DISABLE()         (RCC->AHB4LPENR  &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))

+#endif

+

+

+/** @brief  Get the enable or disable status of the AHB4 peripheral clock during Low Poser (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.

+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.

+  */

+

+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN))   != 0U)

+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN))   != 0U)

+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN))   != 0U)

+#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN))   != 0U)

+#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN))   != 0U)

+#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN))   != 0U)

+#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN))   != 0U)

+#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN))   != 0U)

+#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN))   != 0U)

+#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN))   != 0U)

+#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN))   != 0U)

+#if defined(RCC_AHB4LPENR_CRCLPEN)

+#define __HAL_RCC_CRC_IS_CLK_SLEEP_ENABLED()              ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN))     != 0U)

+#endif

+#if defined(BDMA2)

+#define __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN))    != 0U)

+#define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_ENABLED  /* For API backward compatibility*/

+#else

+#define __HAL_RCC_BDMA_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN))    != 0U)

+#endif /*BDMA2*/

+#if defined(ADC3)

+#define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED()             ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN))    != 0U)

+#endif /*ADC3*/

+#define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_ENABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN))  != 0U)

+#if defined(RCC_AHB4LPENR_SRDSRAMLPEN)

+#define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) != 0U)

+#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED  __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_ENABLED  /* For API backward compatibility*/

+#else

+#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_ENABLED()          ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) != 0U)

+#endif

+

+#define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOALPEN))   == 0U)

+#define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOBLPEN))   == 0U)

+#define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOCLPEN))   == 0U)

+#define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIODLPEN))   == 0U)

+#define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOELPEN))   == 0U)

+#define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOFLPEN))   == 0U)

+#define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOGLPEN))   == 0U)

+#define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOHLPEN))   == 0U)

+#define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOILPEN))   == 0U)

+#define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOJLPEN))   == 0U)

+#define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_GPIOKLPEN))   == 0U)

+#if defined(RCC_AHB4LPENR_CRCLPEN)

+#define __HAL_RCC_CRC_IS_CLK_SLEEP_DISABLED()             ((RCC->AHB4LPENR & (RCC_AHB4LPENR_CRCLPEN))     == 0U)

+#endif

+#if defined(BDMA2)

+#define __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED()           ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMA2LPEN))  == 0U)

+#define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED __HAL_RCC_BDMA2_IS_CLK_SLEEP_DISABLED  /* For API backward compatibility*/

+#else

+#define __HAL_RCC_BDMA_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BDMALPEN))    == 0U)

+#endif /*BDMA2*/

+#if defined(ADC3)

+#define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED()            ((RCC->AHB4LPENR & (RCC_AHB4LPENR_ADC3LPEN))    == 0U)

+#endif /*ADC3*/

+#define __HAL_RCC_BKPRAM_IS_CLK_SLEEP_DISABLED()          ((RCC->AHB4LPENR & (RCC_AHB4LPENR_BKPRAMLPEN))  == 0U)

+#if defined(RCC_AHB4LPENR_SRDSRAMLPEN)

+#define __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB4LPENR & (RCC_AHB4LPENR_SRDSRAMLPEN)) == 0U)

+#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED  __HAL_RCC_SRDSRAM_IS_CLK_SLEEP_DISABLED  /* For API backward compatibility*/

+#else

+#define __HAL_RCC_D3SRAM1_IS_CLK_SLEEP_DISABLED()         ((RCC->AHB4LPENR & (RCC_AHB4LPENR_D3SRAM1LPEN)) == 0U)

+#endif

+

+

+/** @brief  ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

+  */

+

+#if defined(LTDC)

+#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE()           (RCC->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)

+#endif /* LTDC */

+#if defined(DSI)

+#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE()            (RCC->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)

+#endif /*DSI*/

+#define __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE()          (RCC->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)

+

+#if defined(LTDC)

+#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE()           (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)

+#endif /* LTDC */

+#if defined(DSI)

+#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE()            (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)

+#endif /*DSI*/

+#define __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE()          (RCC->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)

+

+

+/** @brief  Get the enable or disable status of the APB3 peripheral clock during Low Poser (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.

+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.

+  */

+

+#if defined(LTDC)

+#define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED()            ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN))  != 0U)

+#endif /* LTDC */

+#if defined(DSI)

+#define __HAL_RCC_DSI_IS_CLK_SLEEP_ENABLED()             ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN))   != 0U)

+#endif /*DSI*/

+#define __HAL_RCC_WWDG1_IS_CLK_SLEEP_ENABLED()           ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) != 0U)

+

+#if defined(LTDC)

+#define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED()           ((RCC->APB3LPENR & (RCC_APB3LPENR_LTDCLPEN))  == 0U)

+#endif /* LTDC */

+#if defined(DSI)

+#define __HAL_RCC_DSI_IS_CLK_SLEEP_DISABLED()            ((RCC->APB3LPENR & (RCC_APB3LPENR_DSILPEN))   == 0U)

+#endif /*DSI*/

+#define __HAL_RCC_WWDG1_IS_CLK_SLEEP_DISABLED()          ((RCC->APB3LPENR & (RCC_APB3LPENR_WWDG1LPEN)) == 0U)

+

+

+/** @brief  ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

+  */

+

+#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)

+#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)

+#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)

+#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)

+#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)

+#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)

+#define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)

+#define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)

+#define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)

+#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE()         (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)

+

+#if defined(DUAL_CORE)

+#define __HAL_RCC_WWDG2_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)

+#endif /*DUAL_CORE*/

+

+#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)

+#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)

+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE()        (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)

+#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE()         (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)

+#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE()         (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)

+#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)

+#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)

+#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)

+#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)

+#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE()           (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)

+#define __HAL_RCC_CEC_CLK_SLEEP_ENABLE()            (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)

+#define __HAL_RCC_DAC12_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)

+#define __HAL_RCC_UART7_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)

+#define __HAL_RCC_UART8_CLK_SLEEP_ENABLE()          (RCC->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)

+#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE()            (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)

+#define __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)

+#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)

+#define __HAL_RCC_MDIOS_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)

+#define __HAL_RCC_FDCAN_CLK_SLEEP_ENABLE()          (RCC->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)

+

+

+#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)

+#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)

+#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)

+#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)

+#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)

+#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)

+#define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)

+#define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)

+#define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)

+#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE()         (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)

+

+#if defined(DUAL_CORE)

+#define __HAL_RCC_WWDG2_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)

+#endif /*DUAL_CORE*/

+

+#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)

+#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)

+#define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()        (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)

+#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE()         (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)

+#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE()         (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)

+#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)

+#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)

+#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)

+#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)

+#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE()           (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)

+#define __HAL_RCC_CEC_CLK_SLEEP_DISABLE()            (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)

+#define __HAL_RCC_DAC12_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)

+#define __HAL_RCC_UART7_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)

+#define __HAL_RCC_UART8_CLK_SLEEP_DISABLE()          (RCC->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)

+#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE()            (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)

+#define __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)

+#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)

+#define __HAL_RCC_MDIOS_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)

+#define __HAL_RCC_FDCAN_CLK_SLEEP_DISABLE()          (RCC->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)

+

+

+/** @brief  Get the enable or disable status of the APB1 peripheral clock during Low Poser (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.

+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.

+  */

+

+#define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN))    != 0U)

+#define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN))    != 0U)

+#define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN))    != 0U)

+#define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN))    != 0U)

+#define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN))    != 0U)

+#define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN))    != 0U)

+#define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN))   != 0U)

+#define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN))   != 0U)

+#define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN))   != 0U)

+#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN))  != 0U)

+#if defined(DUAL_CORE)

+#define __HAL_RCC_WWDG2_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN))   != 0U)

+#endif /*DUAL_CORE*/

+#define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN))    != 0U)

+#define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN))    != 0U)

+#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED()         ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) != 0U)

+#define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN))  != 0U)

+#define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN))  != 0U)

+#define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN))   != 0U)

+#define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN))   != 0U)

+#define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN))    != 0U)

+#define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN))    != 0U)

+#define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN))    != 0U)

+#define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED()             ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN))     != 0U)

+#define __HAL_RCC_DAC12_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN))   != 0U)

+#define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN))   != 0U)

+#define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN))   != 0U)

+#define __HAL_RCC_CRS_IS_CLK_SLEEP_ENABLED()             ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN))     != 0U)

+#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN))   != 0U)

+#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN))   != 0U)

+#define __HAL_RCC_MDIOS_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN))   != 0U)

+#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_ENABLED()           ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN))   != 0U)

+

+#define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM2LPEN))    == 0U)

+#define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM3LPEN))    == 0U)

+#define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM4LPEN))    == 0U)

+#define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM5LPEN))    == 0U)

+#define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM6LPEN))    == 0U)

+#define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM7LPEN))    == 0U)

+#define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM12LPEN))   == 0U)

+#define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM13LPEN))   == 0U)

+#define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_TIM14LPEN))   == 0U)

+#define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB1LLPENR & (RCC_APB1LLPENR_LPTIM1LPEN))  == 0U)

+#if defined(DUAL_CORE)

+#define __HAL_RCC_WWDG2_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_WWDG2LPEN))   == 0U)

+#endif /*DUAL_CORE*/

+#define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI2LPEN))    == 0U)

+#define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPI3LPEN))    == 0U)

+#define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()        ((RCC->APB1LLPENR & (RCC_APB1LLPENR_SPDIFRXLPEN)) == 0U)

+#define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED()         ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART2LPEN))  == 0U)

+#define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED()         ((RCC->APB1LLPENR & (RCC_APB1LLPENR_USART3LPEN))  == 0U)

+#define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART4LPEN))   == 0U)

+#define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART5LPEN))   == 0U)

+#define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C1LPEN))    == 0U)

+#define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C2LPEN))    == 0U)

+#define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB1LLPENR & (RCC_APB1LLPENR_I2C3LPEN))    == 0U)

+#define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED()            ((RCC->APB1LLPENR & (RCC_APB1LLPENR_CECLPEN))     == 0U)

+#define __HAL_RCC_DAC12_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_DAC12LPEN))   == 0U)

+#define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART7LPEN))   == 0U)

+#define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1LLPENR & (RCC_APB1LLPENR_UART8LPEN))   == 0U)

+#define __HAL_RCC_CRS_IS_CLK_SLEEP_DISABLED()            ((RCC->APB1HLPENR & (RCC_APB1HLPENR_CRSLPEN))     == 0U)

+#define __HAL_RCC_SWPMI1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB1HLPENR & (RCC_APB1HLPENR_SWPMILPEN))   == 0U)

+#define __HAL_RCC_OPAMP_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1HLPENR & (RCC_APB1HLPENR_OPAMPLPEN))   == 0U)

+#define __HAL_RCC_MDIOS_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1HLPENR & (RCC_APB1HLPENR_MDIOSLPEN))   == 0U)

+#define __HAL_RCC_FDCAN_IS_CLK_SLEEP_DISABLED()          ((RCC->APB1HLPENR & (RCC_APB1HLPENR_FDCANLPEN))   == 0U)

+

+

+/** @brief  ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

+  */

+

+#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)

+#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)

+#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)

+#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)

+#if defined(UART9)

+#define __HAL_RCC_UART9_CLK_SLEEP_ENABLE()          (RCC->APB2LPENR) |= (RCC_APB2LPENR_UART9LPEN)

+#endif /*UART9*/

+#if defined(USART10)

+#define __HAL_RCC_USART10_CLK_SLEEP_ENABLE()        (RCC->APB2LPENR) |= (RCC_APB2LPENR_USART10LPEN)

+#endif /*USART10*/

+#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)

+#define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)

+#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE()          (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)

+#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE()          (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)

+#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE()          (RCC->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)

+#define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)

+#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)

+#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)

+#if defined(SAI3)

+#define __HAL_RCC_SAI3_CLK_SLEEP_ENABLE()           (RCC->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)

+#endif /*SAI3*/

+#define __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)

+#if defined(HRTIM1)

+#define __HAL_RCC_HRTIM1_CLK_SLEEP_ENABLE()         (RCC->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)

+#endif /*HRTIM1*/

+

+#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)

+#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)

+#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)

+#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)

+#if defined(UART9)

+#define __HAL_RCC_UART9_CLK_SLEEP_DISABLE()          (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_UART9LPEN)

+#endif /*UART9*/

+#if defined(USART10)

+#define __HAL_RCC_USART10_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_USART10LPEN)

+#endif /*USART10*/

+#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)

+#define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)

+#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE()          (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)

+#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE()          (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)

+#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE()          (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)

+#define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)

+#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)

+#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)

+#if defined(SAI3)

+#define __HAL_RCC_SAI3_CLK_SLEEP_DISABLE()           (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)

+#endif /*SAI3*/

+#define __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)

+#if defined(HRTIM1)

+#define __HAL_RCC_HRTIM1_CLK_SLEEP_DISABLE()         (RCC->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)

+#endif /*HRTIM1*/

+

+

+/** @brief  Get the enable or disable status of the APB2 peripheral clock during Low Poser (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.

+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.

+  */

+

+#define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN))   != 0U)

+#define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN))   != 0U)

+#define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != 0U)

+#define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != 0U)

+#if defined(UART9)

+#define __HAL_RCC_UART9_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_UART9LPEN)) != 0U)

+#endif /*UART9*/

+#if defined(USART10)

+#define __HAL_RCC_USART10_IS_CLK_SLEEP_ENABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) != 0U)

+#endif /*USART10*/

+#define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN))   != 0U)

+#define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN))   != 0U)

+#define __HAL_RCC_TIM15_IS_CLK_SLEEP_ENABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN))  != 0U)

+#define __HAL_RCC_TIM16_IS_CLK_SLEEP_ENABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN))  != 0U)

+#define __HAL_RCC_TIM17_IS_CLK_SLEEP_ENABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN))  != 0U)

+#define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN))   != 0U)

+#define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN))   != 0U)

+#define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN))   != 0U)

+#if defined(SAI3)

+#define __HAL_RCC_SAI3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN))   != 0U)

+#endif /*SAI3*/

+#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) != 0U)

+#if defined(HRTIM1)

+#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_ENABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN))  != 0U)

+#endif /*HRTIM1*/

+

+#define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN))   == 0U)

+#define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN))   == 0U)

+#define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == 0U)

+#define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == 0U)

+#if defined(UART9)

+#define __HAL_RCC_USART9_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_USART9LPEN)) == 0U)

+#endif /*UART9*/

+#if defined(USART10)

+#define __HAL_RCC_USART10_IS_CLK_SLEEP_DISABLED()        ((RCC->APB2LPENR & (RCC_APB2LPENR_USART10LPEN)) == 0U)

+#endif /*USART10*/

+#define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN))   == 0U)

+#define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN))   == 0U)

+#define __HAL_RCC_TIM15_IS_CLK_SLEEP_DISABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM15LPEN))  == 0U)

+#define __HAL_RCC_TIM16_IS_CLK_SLEEP_DISABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM16LPEN))  == 0U)

+#define __HAL_RCC_TIM17_IS_CLK_SLEEP_DISABLED()          ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM17LPEN))  == 0U)

+#define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN))   == 0U)

+#define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN))   == 0U)

+#define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN))   == 0U)

+#if defined(SAI3)

+#define __HAL_RCC_SAI3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI3LPEN))   == 0U)

+#endif /*SAI3*/

+#define __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_DFSDM1LPEN)) == 0U)

+#if defined(HRTIM1)

+#define __HAL_RCC_HRTIM1_IS_CLK_SLEEP_DISABLED()         ((RCC->APB2LPENR & (RCC_APB2LPENR_HRTIMLPEN))  == 0U)

+#endif /*HRTIM1*/

+

+/** @brief  ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

+  */

+

+#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)

+#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE()          (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)

+#define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)

+#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)

+#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)

+#define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)

+#if defined(LPTIM4)

+#define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)

+#endif /*LPTIM4*/

+#if defined(LPTIM5)

+#define __HAL_RCC_LPTIM5_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)

+#endif /*LPTIM5*/

+#if defined(DAC2)

+#define __HAL_RCC_DAC2_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_DAC2LPEN)

+#endif /*DAC2*/

+#define __HAL_RCC_COMP12_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)

+#define __HAL_RCC_VREF_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)

+#define __HAL_RCC_RTC_CLK_SLEEP_ENABLE()              (RCC->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)

+#if defined(SAI4)

+#define __HAL_RCC_SAI4_CLK_SLEEP_ENABLE()             (RCC->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)

+#endif /*SAI4*/

+#if defined(DTS)

+#define __HAL_RCC_DTS_CLK_SLEEP_ENABLE()              (RCC->APB4LPENR) |= (RCC_APB4LPENR_DTSLPEN)

+#endif /*DTS*/

+#if defined(DFSDM2_BASE)

+#define __HAL_RCC_DFSDM2_CLK_SLEEP_ENABLE()           (RCC->APB4LPENR) |= (RCC_APB4LPENR_DFSDM2LPEN)

+#endif /*DFSDM2*/

+

+#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)

+#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE()          (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)

+#define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)

+#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)

+#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)

+#define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)

+#if defined(LPTIM4)

+#define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)

+#endif /*LPTIM4*/

+#if defined(LPTIM5)

+#define __HAL_RCC_LPTIM5_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)

+#endif /*LPTIM5*/

+#if defined(DAC2)

+#define __HAL_RCC_DAC2_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DAC2LPEN)

+#endif /*DAC2*/

+#define __HAL_RCC_COMP12_CLK_SLEEP_DISABLE()           (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)

+#define __HAL_RCC_VREF_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)

+#define __HAL_RCC_RTC_CLK_SLEEP_DISABLE()              (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)

+#if defined(SAI4)

+#define __HAL_RCC_SAI4_CLK_SLEEP_DISABLE()             (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)

+#endif /*SAI4*/

+#if defined(DTS)

+#define __HAL_RCC_DTS_CLK_SLEEP_DISABLE()              (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DTSLPEN)

+#endif /*DTS*/

+#if defined(DFSDM2_BASE)

+#define __HAL_RCC_DFSDM2_CLK_SLEEP_DISABLE()          (RCC->APB4LPENR) &= ~ (RCC_APB4LPENR_DFSDM2LPEN)

+#endif /*DFSDM2*/

+

+

+/** @brief  Get the enable or disable status of the APB4 peripheral clock during Low Poser (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.

+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.

+  */

+

+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN))  != 0U)

+#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_ENABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) != 0U)

+#define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN))    != 0U)

+#define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN))    != 0U)

+#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN))  != 0U)

+#define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN))  != 0U)

+#if defined(LPTIM4)

+#define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN))  != 0U)

+#endif /*LPTIM4*/

+#if defined(LPTIM5)

+#define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN))  != 0U)

+#endif /*LPTIM5*/

+#if defined(DAC2)

+#define __HAL_RCC_DAC2_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN))  != 0U)

+#endif /*DAC2*/

+#define __HAL_RCC_COMP12_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN))  != 0U)

+#define __HAL_RCC_VREF_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN))    != 0U)

+#define __HAL_RCC_RTC_IS_CLK_SLEEP_ENABLED()               ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN))  != 0U)

+#if defined(SAI4)

+#define __HAL_RCC_SAI4_IS_CLK_SLEEP_ENABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN))    != 0U)

+#endif /*SAI4*/

+#if defined(DTS)

+#define __HAL_RCC_DTS_IS_CLK_SLEEP_ENABLED()               ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN))    != 0U)

+#endif /*DTS*/

+#if defined(DFSDM2_BASE)

+#define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_ENABLED()            ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) != 0U)

+#endif /*DFSDM2*/

+

+#define __HAL_RCC_SYSCFG_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_SYSCFGLPEN))  == 0U)

+#define __HAL_RCC_LPUART1_IS_CLK_SLEEP_DISABLED()          ((RCC->APB4LPENR & (RCC_APB4LPENR_LPUART1LPEN)) == 0U)

+#define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_SPI6LPEN))    == 0U)

+#define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_I2C4LPEN))    == 0U)

+#define __HAL_RCC_LPTIM2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM2LPEN))  == 0U)

+#define __HAL_RCC_LPTIM3_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM3LPEN))  == 0U)

+#if defined(LPTIM4)

+#define __HAL_RCC_LPTIM4_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM4LPEN))  == 0U)

+#endif /*LPTIM4*/

+#if defined(LPTIM5)

+#define __HAL_RCC_LPTIM5_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_LPTIM5LPEN))  == 0U)

+#endif /*LPTIM5*/

+#if defined(DAC2)

+#define __HAL_RCC_DAC2_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_DAC2LPEN))  == 0U)

+#endif /*DAC2*/

+#define __HAL_RCC_COMP12_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_COMP12LPEN))  == 0U)

+#define __HAL_RCC_VREF_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_VREFLPEN))    == 0U)

+#define __HAL_RCC_RTC_IS_CLK_SLEEP_DISABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_RTCAPBLPEN))  == 0U)

+#if defined(SAI4)

+#define __HAL_RCC_SAI4_IS_CLK_SLEEP_DISABLED()             ((RCC->APB4LPENR & (RCC_APB4LPENR_SAI4LPEN))    == 0U)

+#endif /*SAI4*/

+#if defined(DTS)

+#define __HAL_RCC_DTS_IS_CLK_SLEEP_DISABLED()              ((RCC->APB4LPENR & (RCC_APB4LPENR_DTSLPEN))    == 0U)

+#endif /*DTS*/

+#if defined(DFSDM2_BASE)

+#define __HAL_RCC_DFSDM2_IS_CLK_SLEEP_DISABLED()           ((RCC->APB4LPENR & (RCC_APB4LPENR_DFSDM2LPEN)) == 0U)

+#endif /*DFSDM2*/

+

+

+#if defined(DUAL_CORE)

+

+/** @brief  Enable or disable the RCC_C1 AHB3 peripheral clock during Low Power (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.

+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.

+  */

+#define __HAL_RCC_C1_MDMA_CLK_SLEEP_ENABLE()            (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))

+#define __HAL_RCC_C1_DMA2D_CLK_SLEEP_ENABLE()           (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))

+#define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_ENABLE()          (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))

+#define __HAL_RCC_C1_FLASH_CLK_SLEEP_ENABLE()           (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))

+#define __HAL_RCC_C1_FMC_CLK_SLEEP_ENABLE()             (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))

+#define __HAL_RCC_C1_QSPI_CLK_SLEEP_ENABLE()            (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))

+#define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_ENABLE()          (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))

+#define __HAL_RCC_C1_DTCM1_CLK_SLEEP_ENABLE()           (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))

+#define __HAL_RCC_C1_DTCM2_CLK_SLEEP_ENABLE()           (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))

+#define __HAL_RCC_C1_ITCM_CLK_SLEEP_ENABLE()            (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))

+#define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_ENABLE()         (RCC_C1->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))

+

+

+#define __HAL_RCC_C1_MDMA_CLK_SLEEP_DISABLE()            (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))

+#define __HAL_RCC_C1_DMA2D_CLK_SLEEP_DISABLE()           (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))

+#define __HAL_RCC_C1_JPGDEC_CLK_SLEEP_DISABLE()          (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))

+#define __HAL_RCC_C1_FLASH_CLK_SLEEP_DISABLE()           (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))

+#define __HAL_RCC_C1_FMC_CLK_SLEEP_DISABLE()             (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))

+#define __HAL_RCC_C1_QSPI_CLK_SLEEP_DISABLE()            (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))

+#define __HAL_RCC_C1_SDMMC1_CLK_SLEEP_DISABLE()          (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))

+#define __HAL_RCC_C1_DTCM1_CLK_SLEEP_DISABLE()           (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))

+#define __HAL_RCC_C1_DTCM2_CLK_SLEEP_DISABLE()           (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))

+#define __HAL_RCC_C1_ITCM_CLK_SLEEP_DISABLE()            (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))

+#define __HAL_RCC_C1_D1SRAM1_CLK_SLEEP_DISABLE()         (RCC_C1->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))

+

+

+

+/** @brief  ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

+  */

+

+#define __HAL_RCC_C1_DMA1_CLK_SLEEP_ENABLE()             (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))

+#define __HAL_RCC_C1_DMA2_CLK_SLEEP_ENABLE()             (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))

+#define __HAL_RCC_C1_ADC12_CLK_SLEEP_ENABLE()            (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))

+#define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_ENABLE()          (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))

+#define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_ENABLE()           (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))

+#define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_ENABLE()           (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))

+#define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_ENABLE()      (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))

+#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))

+#define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_ENABLE()      (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))

+#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C1->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))

+

+#define __HAL_RCC_C1_DMA1_CLK_SLEEP_DISABLE()             (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))

+#define __HAL_RCC_C1_DMA2_CLK_SLEEP_DISABLE()             (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))

+#define __HAL_RCC_C1_ADC12_CLK_SLEEP_DISABLE()            (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))

+#define __HAL_RCC_C1_ETH1MAC_CLK_SLEEP_DISABLE()          (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))

+#define __HAL_RCC_C1_ETH1TX_CLK_SLEEP_DISABLE()           (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))

+#define __HAL_RCC_C1_ETH1RX_CLK_SLEEP_DISABLE()           (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))

+#define __HAL_RCC_C1_USB1_OTG_HS_CLK_SLEEP_DISABLE()      (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))

+#define __HAL_RCC_C1_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))

+#define __HAL_RCC_C1_USB2_OTG_FS_CLK_SLEEP_DISABLE()      (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))

+#define __HAL_RCC_C1_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C1->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))

+

+/** @brief  ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

+  */

+

+#define __HAL_RCC_C1_DCMI_CLK_SLEEP_ENABLE()             (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))

+#if defined(CRYP)

+#define __HAL_RCC_C1_CRYP_CLK_SLEEP_ENABLE()             (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))

+#endif /* CRYP */

+#if defined(HASH)

+#define __HAL_RCC_C1_HASH_CLK_SLEEP_ENABLE()             (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))

+#endif /* HASH */

+#define __HAL_RCC_C1_RNG_CLK_SLEEP_ENABLE()              (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))

+#define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_ENABLE()           (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))

+#define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_ENABLE()          (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))

+#define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_ENABLE()          (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))

+#define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_ENABLE()          (RCC_C1->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))

+

+#define __HAL_RCC_C1_DCMI_CLK_SLEEP_DISABLE()             (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))

+#if defined(CRYP)

+#define __HAL_RCC_C1_CRYP_CLK_SLEEP_DISABLE()             (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))

+#endif /* CRYP */

+#if defined(HASH)

+#define __HAL_RCC_C1_HASH_CLK_SLEEP_DISABLE()             (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))

+#endif /* HASH */

+#define __HAL_RCC_C1_RNG_CLK_SLEEP_DISABLE()              (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))

+#define __HAL_RCC_C1_SDMMC2_CLK_SLEEP_DISABLE()           (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))

+#define __HAL_RCC_C1_D2SRAM1_CLK_SLEEP_DISABLE()          (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))

+#define __HAL_RCC_C1_D2SRAM2_CLK_SLEEP_DISABLE()          (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))

+#define __HAL_RCC_C1_D2SRAM3_CLK_SLEEP_DISABLE()          (RCC_C1->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))

+

+/** @brief  ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

+  */

+

+#define __HAL_RCC_C1_GPIOA_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)

+#define __HAL_RCC_C1_GPIOB_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)

+#define __HAL_RCC_C1_GPIOC_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)

+#define __HAL_RCC_C1_GPIOD_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)

+#define __HAL_RCC_C1_GPIOE_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)

+#define __HAL_RCC_C1_GPIOF_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)

+#define __HAL_RCC_C1_GPIOG_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)

+#define __HAL_RCC_C1_GPIOH_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)

+#define __HAL_RCC_C1_GPIOI_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)

+#define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)

+#define __HAL_RCC_C1_GPIOK_CLK_SLEEP_ENABLE()           (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)

+#define __HAL_RCC_C1_CRC_CLK_SLEEP_ENABLE()             (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)

+#define __HAL_RCC_C1_BDMA_CLK_SLEEP_ENABLE()            (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)

+#define __HAL_RCC_C1_ADC3_CLK_SLEEP_ENABLE()            (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)

+#define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_ENABLE()          (RCC_C1->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)

+#define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_ENABLE()         (RCC_C1->AHB4LPENR  |= (RCC_AHB4LPENR_D3SRAM1LPEN))

+

+#define __HAL_RCC_C1_GPIOA_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)

+#define __HAL_RCC_C1_GPIOB_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)

+#define __HAL_RCC_C1_GPIOC_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)

+#define __HAL_RCC_C1_GPIOD_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)

+#define __HAL_RCC_C1_GPIOE_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)

+#define __HAL_RCC_C1_GPIOF_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)

+#define __HAL_RCC_C1_GPIOG_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)

+#define __HAL_RCC_C1_GPIOH_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)

+#define __HAL_RCC_C1_GPIOI_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)

+#define __HAL_RCC_C1_GPIOJ_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)

+#define __HAL_RCC_C1_GPIOK_CLK_SLEEP_DISABLE()           (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)

+#define __HAL_RCC_C1_CRC_CLK_SLEEP_DISABLE()             (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)

+#define __HAL_RCC_C1_BDMA_CLK_SLEEP_DISABLE()            (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)

+#define __HAL_RCC_C1_ADC3_CLK_SLEEP_DISABLE()            (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)

+#define __HAL_RCC_C1_BKPRAM_CLK_SLEEP_DISABLE()          (RCC_C1->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)

+#define __HAL_RCC_C1_D3SRAM1_CLK_SLEEP_DISABLE()         (RCC_C1->AHB4LPENR  &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))

+

+/** @brief  ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

+  */

+

+#define __HAL_RCC_C1_LTDC_CLK_SLEEP_ENABLE()           (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)

+#define __HAL_RCC_C1_DSI_CLK_SLEEP_ENABLE()            (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)

+#define __HAL_RCC_C1_WWDG1_CLK_SLEEP_ENABLE()          (RCC_C1->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)

+

+#define __HAL_RCC_C1_LTDC_CLK_SLEEP_DISABLE()           (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)

+#define __HAL_RCC_C1_DSI_CLK_SLEEP_DISABLE()            (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)

+#define __HAL_RCC_C1_WWDG1_CLK_SLEEP_DISABLE()          (RCC_C1->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)

+

+/** @brief  ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

+  */

+

+#define __HAL_RCC_C1_TIM2_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)

+#define __HAL_RCC_C1_TIM3_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)

+#define __HAL_RCC_C1_TIM4_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)

+#define __HAL_RCC_C1_TIM5_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)

+#define __HAL_RCC_C1_TIM6_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)

+#define __HAL_RCC_C1_TIM7_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)

+#define __HAL_RCC_C1_TIM12_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)

+#define __HAL_RCC_C1_TIM13_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)

+#define __HAL_RCC_C1_TIM14_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)

+#define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_ENABLE()         (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)

+#define __HAL_RCC_C1_WWDG2_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)

+#define __HAL_RCC_C1_SPI2_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)

+#define __HAL_RCC_C1_SPI3_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)

+#define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_ENABLE()        (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)

+#define __HAL_RCC_C1_USART2_CLK_SLEEP_ENABLE()         (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)

+#define __HAL_RCC_C1_USART3_CLK_SLEEP_ENABLE()         (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)

+#define __HAL_RCC_C1_UART4_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)

+#define __HAL_RCC_C1_UART5_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)

+#define __HAL_RCC_C1_I2C1_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)

+#define __HAL_RCC_C1_I2C2_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)

+#define __HAL_RCC_C1_I2C3_CLK_SLEEP_ENABLE()           (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)

+#define __HAL_RCC_C1_CEC_CLK_SLEEP_ENABLE()            (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)

+#define __HAL_RCC_C1_DAC12_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)

+#define __HAL_RCC_C1_UART7_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)

+#define __HAL_RCC_C1_UART8_CLK_SLEEP_ENABLE()          (RCC_C1->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)

+#define __HAL_RCC_C1_CRS_CLK_SLEEP_ENABLE()            (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)

+#define __HAL_RCC_C1_SWPMI_CLK_SLEEP_ENABLE()          (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)

+#define __HAL_RCC_C1_OPAMP_CLK_SLEEP_ENABLE()          (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)

+#define __HAL_RCC_C1_MDIOS_CLK_SLEEP_ENABLE()          (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)

+#define __HAL_RCC_C1_FDCAN_CLK_SLEEP_ENABLE()          (RCC_C1->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)

+

+

+#define __HAL_RCC_C1_TIM2_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)

+#define __HAL_RCC_C1_TIM3_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)

+#define __HAL_RCC_C1_TIM4_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)

+#define __HAL_RCC_C1_TIM5_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)

+#define __HAL_RCC_C1_TIM6_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)

+#define __HAL_RCC_C1_TIM7_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)

+#define __HAL_RCC_C1_TIM12_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)

+#define __HAL_RCC_C1_TIM13_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)

+#define __HAL_RCC_C1_TIM14_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)

+#define __HAL_RCC_C1_LPTIM1_CLK_SLEEP_DISABLE()         (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)

+#define __HAL_RCC_C1_WWDG2_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)

+#define __HAL_RCC_C1_SPI2_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)

+#define __HAL_RCC_C1_SPI3_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)

+#define __HAL_RCC_C1_SPDIFRX_CLK_SLEEP_DISABLE()        (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)

+#define __HAL_RCC_C1_USART2_CLK_SLEEP_DISABLE()         (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)

+#define __HAL_RCC_C1_USART3_CLK_SLEEP_DISABLE()         (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)

+#define __HAL_RCC_C1_UART4_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)

+#define __HAL_RCC_C1_UART5_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)

+#define __HAL_RCC_C1_I2C1_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)

+#define __HAL_RCC_C1_I2C2_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)

+#define __HAL_RCC_C1_I2C3_CLK_SLEEP_DISABLE()           (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)

+#define __HAL_RCC_C1_CEC_CLK_SLEEP_DISABLE()            (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)

+#define __HAL_RCC_C1_DAC12_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)

+#define __HAL_RCC_C1_UART7_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)

+#define __HAL_RCC_C1_UART8_CLK_SLEEP_DISABLE()          (RCC_C1->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)

+#define __HAL_RCC_C1_CRS_CLK_SLEEP_DISABLE()            (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)

+#define __HAL_RCC_C1_SWPMI_CLK_SLEEP_DISABLE()          (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)

+#define __HAL_RCC_C1_OPAMP_CLK_SLEEP_DISABLE()          (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)

+#define __HAL_RCC_C1_MDIOS_CLK_SLEEP_DISABLE()          (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)

+#define __HAL_RCC_C1_FDCAN_CLK_SLEEP_DISABLE()          (RCC_C1->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)

+

+/** @brief  ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

+  */

+

+#define __HAL_RCC_C1_TIM1_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)

+#define __HAL_RCC_C1_TIM8_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)

+#define __HAL_RCC_C1_USART1_CLK_SLEEP_ENABLE()         (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)

+#define __HAL_RCC_C1_USART6_CLK_SLEEP_ENABLE()         (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)

+#define __HAL_RCC_C1_SPI1_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)

+#define __HAL_RCC_C1_SPI4_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)

+#define __HAL_RCC_C1_TIM15_CLK_SLEEP_ENABLE()          (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)

+#define __HAL_RCC_C1_TIM16_CLK_SLEEP_ENABLE()          (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)

+#define __HAL_RCC_C1_TIM17_CLK_SLEEP_ENABLE()          (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)

+#define __HAL_RCC_C1_SPI5_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)

+#define __HAL_RCC_C1_SAI1_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)

+#define __HAL_RCC_C1_SAI2_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)

+#define __HAL_RCC_C1_SAI3_CLK_SLEEP_ENABLE()           (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)

+#define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_ENABLE()         (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)

+#define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_ENABLE()         (RCC_C1->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)

+

+#define __HAL_RCC_C1_TIM1_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)

+#define __HAL_RCC_C1_TIM8_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)

+#define __HAL_RCC_C1_USART1_CLK_SLEEP_DISABLE()         (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)

+#define __HAL_RCC_C1_USART6_CLK_SLEEP_DISABLE()         (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)

+#define __HAL_RCC_C1_SPI1_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)

+#define __HAL_RCC_C1_SPI4_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)

+#define __HAL_RCC_C1_TIM15_CLK_SLEEP_DISABLE()          (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)

+#define __HAL_RCC_C1_TIM16_CLK_SLEEP_DISABLE()          (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)

+#define __HAL_RCC_C1_TIM17_CLK_SLEEP_DISABLE()          (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)

+#define __HAL_RCC_C1_SPI5_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)

+#define __HAL_RCC_C1_SAI1_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)

+#define __HAL_RCC_C1_SAI2_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)

+#define __HAL_RCC_C1_SAI3_CLK_SLEEP_DISABLE()           (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)

+#define __HAL_RCC_C1_DFSDM1_CLK_SLEEP_DISABLE()         (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)

+#define __HAL_RCC_C1_HRTIM1_CLK_SLEEP_DISABLE()         (RCC_C1->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)

+

+/** @brief  ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

+  */

+

+#define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)

+#define __HAL_RCC_C1_LPUART1_CLK_SLEEP_ENABLE()          (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)

+#define __HAL_RCC_C1_SPI6_CLK_SLEEP_ENABLE()             (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)

+#define __HAL_RCC_C1_I2C4_CLK_SLEEP_ENABLE()             (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)

+#define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)

+#define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)

+#define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)

+#define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)

+#define __HAL_RCC_C1_COMP12_CLK_SLEEP_ENABLE()           (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)

+#define __HAL_RCC_C1_VREF_CLK_SLEEP_ENABLE()             (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)

+#define __HAL_RCC_C1_SAI4_CLK_SLEEP_ENABLE()             (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)

+#define __HAL_RCC_C1_RTC_CLK_SLEEP_ENABLE()              (RCC_C1->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)

+

+

+#define __HAL_RCC_C1_SYSCFG_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)

+#define __HAL_RCC_C1_LPUART1_CLK_SLEEP_DISABLE()          (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)

+#define __HAL_RCC_C1_SPI6_CLK_SLEEP_DISABLE()             (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)

+#define __HAL_RCC_C1_I2C4_CLK_SLEEP_DISABLE()             (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)

+#define __HAL_RCC_C1_LPTIM2_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)

+#define __HAL_RCC_C1_LPTIM3_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)

+#define __HAL_RCC_C1_LPTIM4_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)

+#define __HAL_RCC_C1_LPTIM5_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)

+#define __HAL_RCC_C1_COMP12_CLK_SLEEP_DISABLE()           (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)

+#define __HAL_RCC_C1_VREF_CLK_SLEEP_DISABLE()             (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)

+#define __HAL_RCC_C1_SAI4_CLK_SLEEP_DISABLE()             (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)

+#define __HAL_RCC_C1_RTC_CLK_SLEEP_DISABLE()              (RCC_C1->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)

+

+/** @brief  Enable or disable the RCC_C2 AHB3 peripheral clock during Low Power (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.

+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.

+  */

+

+

+#define __HAL_RCC_C2_MDMA_CLK_SLEEP_ENABLE()            (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_MDMALPEN))

+#define __HAL_RCC_C2_DMA2D_CLK_SLEEP_ENABLE()           (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DMA2DLPEN))

+#define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_ENABLE()          (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_JPGDECLPEN))

+#define __HAL_RCC_C2_FLASH_CLK_SLEEP_ENABLE()           (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FLASHLPEN))

+#define __HAL_RCC_C2_FMC_CLK_SLEEP_ENABLE()             (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))

+#define __HAL_RCC_C2_QSPI_CLK_SLEEP_ENABLE()            (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))

+#define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_ENABLE()          (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_SDMMC1LPEN))

+#define __HAL_RCC_C2_DTCM1_CLK_SLEEP_ENABLE()           (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM1LPEN))

+#define __HAL_RCC_C2_DTCM2_CLK_SLEEP_ENABLE()           (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_DTCM2LPEN))

+#define __HAL_RCC_C2_ITCM_CLK_SLEEP_ENABLE()            (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_ITCMLPEN))

+#define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_ENABLE()         (RCC_C2->AHB3LPENR |= (RCC_AHB3LPENR_AXISRAMLPEN))

+

+

+#define __HAL_RCC_C2_MDMA_CLK_SLEEP_DISABLE()            (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_MDMALPEN))

+#define __HAL_RCC_C2_DMA2D_CLK_SLEEP_DISABLE()           (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DMA2DLPEN))

+#define __HAL_RCC_C2_JPGDEC_CLK_SLEEP_DISABLE()          (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_JPGDECLPEN))

+#define __HAL_RCC_C2_FLASH_CLK_SLEEP_DISABLE()           (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FLASHLPEN))

+#define __HAL_RCC_C2_FMC_CLK_SLEEP_DISABLE()             (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_FMCLPEN))

+#define __HAL_RCC_C2_QSPI_CLK_SLEEP_DISABLE()            (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_QSPILPEN))

+#define __HAL_RCC_C2_SDMMC1_CLK_SLEEP_DISABLE()          (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_SDMMC1LPEN))

+#define __HAL_RCC_C2_DTCM1_CLK_SLEEP_DISABLE()           (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM1LPEN))

+#define __HAL_RCC_C2_DTCM2_CLK_SLEEP_DISABLE()           (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_DTCM2LPEN))

+#define __HAL_RCC_C2_ITCM_CLK_SLEEP_DISABLE()            (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_ITCMLPEN))

+#define __HAL_RCC_C2_D1SRAM1_CLK_SLEEP_DISABLE()         (RCC_C2->AHB3LPENR &= ~ (RCC_AHB3LPENR_AXISRAMLPEN))

+

+

+

+/** @brief  ENABLE or disable the AHB1 peripheral clock during Low Power (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

+  */

+

+#define __HAL_RCC_C2_DMA1_CLK_SLEEP_ENABLE()             (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))

+#define __HAL_RCC_C2_DMA2_CLK_SLEEP_ENABLE()             (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))

+#define __HAL_RCC_C2_ADC12_CLK_SLEEP_ENABLE()            (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ADC12LPEN))

+#define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_ENABLE()          (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1MACLPEN))

+#define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_ENABLE()           (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1TXLPEN))

+#define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_ENABLE()           (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_ETH1RXLPEN))

+#define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_ENABLE()      (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSLPEN))

+#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB1OTGHSULPILPEN))

+#define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_ENABLE()      (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSLPEN))

+#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() (RCC_C2->AHB1LPENR |= (RCC_AHB1LPENR_USB2OTGHSULPILPEN))

+

+#define __HAL_RCC_C2_DMA1_CLK_SLEEP_DISABLE()             (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA1LPEN))

+#define __HAL_RCC_C2_DMA2_CLK_SLEEP_DISABLE()             (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_DMA2LPEN))

+#define __HAL_RCC_C2_ADC12_CLK_SLEEP_DISABLE()            (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ADC12LPEN))

+#define __HAL_RCC_C2_ETH1MAC_CLK_SLEEP_DISABLE()          (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1MACLPEN))

+#define __HAL_RCC_C2_ETH1TX_CLK_SLEEP_DISABLE()           (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1TXLPEN))

+#define __HAL_RCC_C2_ETH1RX_CLK_SLEEP_DISABLE()           (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_ETH1RXLPEN))

+#define __HAL_RCC_C2_USB1_OTG_HS_CLK_SLEEP_DISABLE()      (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSLPEN))

+#define __HAL_RCC_C2_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB1OTGHSULPILPEN))

+#define __HAL_RCC_C2_USB2_OTG_FS_CLK_SLEEP_DISABLE()      (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSLPEN))

+#define __HAL_RCC_C2_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() (RCC_C2->AHB1LPENR &= ~ (RCC_AHB1LPENR_USB2OTGHSULPILPEN))

+

+/** @brief  ENABLE or disable the AHB2 peripheral clock during Low Power (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

+  */

+

+#define __HAL_RCC_C2_DCMI_CLK_SLEEP_ENABLE()             (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))

+#if defined(CRYP)

+#define __HAL_RCC_C2_CRYP_CLK_SLEEP_ENABLE()             (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))

+#endif /* CRYP */

+#if defined(HASH)

+#define __HAL_RCC_C2_HASH_CLK_SLEEP_ENABLE()             (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))

+#endif /* HASH */

+#define __HAL_RCC_C2_RNG_CLK_SLEEP_ENABLE()              (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))

+#define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_ENABLE()           (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_SDMMC2LPEN))

+#define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_ENABLE()          (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM1LPEN))

+#define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_ENABLE()          (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM2LPEN))

+#define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_ENABLE()          (RCC_C2->AHB2LPENR |= (RCC_AHB2LPENR_D2SRAM3LPEN))

+

+#define __HAL_RCC_C2_DCMI_CLK_SLEEP_DISABLE()             (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_DCMILPEN))

+#if defined(CRYP)

+#define __HAL_RCC_C2_CRYP_CLK_SLEEP_DISABLE()             (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_CRYPLPEN))

+#endif /* CRYP */

+#if defined(HASH)

+#define __HAL_RCC_C2_HASH_CLK_SLEEP_DISABLE()             (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_HASHLPEN))

+#endif /* HASH */

+#define __HAL_RCC_C2_RNG_CLK_SLEEP_DISABLE()              (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_RNGLPEN))

+#define __HAL_RCC_C2_SDMMC2_CLK_SLEEP_DISABLE()           (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_SDMMC2LPEN))

+#define __HAL_RCC_C2_D2SRAM1_CLK_SLEEP_DISABLE()          (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM1LPEN))

+#define __HAL_RCC_C2_D2SRAM2_CLK_SLEEP_DISABLE()          (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM2LPEN))

+#define __HAL_RCC_C2_D2SRAM3_CLK_SLEEP_DISABLE()          (RCC_C2->AHB2LPENR &= ~ (RCC_AHB2LPENR_D2SRAM3LPEN))

+

+/** @brief  ENABLE or disable the AHB4 peripheral clock during Low Power (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

+  */

+

+#define __HAL_RCC_C2_GPIOA_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOALPEN)

+#define __HAL_RCC_C2_GPIOB_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOBLPEN)

+#define __HAL_RCC_C2_GPIOC_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOCLPEN)

+#define __HAL_RCC_C2_GPIOD_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIODLPEN)

+#define __HAL_RCC_C2_GPIOE_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOELPEN)

+#define __HAL_RCC_C2_GPIOF_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOFLPEN)

+#define __HAL_RCC_C2_GPIOG_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOGLPEN)

+#define __HAL_RCC_C2_GPIOH_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOHLPEN)

+#define __HAL_RCC_C2_GPIOI_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOILPEN)

+#define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOJLPEN)

+#define __HAL_RCC_C2_GPIOK_CLK_SLEEP_ENABLE()           (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_GPIOKLPEN)

+#define __HAL_RCC_C2_CRC_CLK_SLEEP_ENABLE()             (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_CRCLPEN)

+#define __HAL_RCC_C2_BDMA_CLK_SLEEP_ENABLE()            (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BDMALPEN)

+#define __HAL_RCC_C2_ADC3_CLK_SLEEP_ENABLE()            (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_ADC3LPEN)

+#define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_ENABLE()          (RCC_C2->AHB4LPENR) |= (RCC_AHB4LPENR_BKPRAMLPEN)

+#define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_ENABLE()         (RCC_C2->AHB4LPENR  |= (RCC_AHB4LPENR_D3SRAM1LPEN))

+

+#define __HAL_RCC_C2_GPIOA_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOALPEN)

+#define __HAL_RCC_C2_GPIOB_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOBLPEN)

+#define __HAL_RCC_C2_GPIOC_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOCLPEN)

+#define __HAL_RCC_C2_GPIOD_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIODLPEN)

+#define __HAL_RCC_C2_GPIOE_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOELPEN)

+#define __HAL_RCC_C2_GPIOF_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOFLPEN)

+#define __HAL_RCC_C2_GPIOG_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOGLPEN)

+#define __HAL_RCC_C2_GPIOH_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOHLPEN)

+#define __HAL_RCC_C2_GPIOI_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOILPEN)

+#define __HAL_RCC_C2_GPIOJ_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOJLPEN)

+#define __HAL_RCC_C2_GPIOK_CLK_SLEEP_DISABLE()           (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_GPIOKLPEN)

+#define __HAL_RCC_C2_CRC_CLK_SLEEP_DISABLE()             (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_CRCLPEN)

+#define __HAL_RCC_C2_BDMA_CLK_SLEEP_DISABLE()            (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BDMALPEN)

+#define __HAL_RCC_C2_ADC3_CLK_SLEEP_DISABLE()            (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_ADC3LPEN)

+#define __HAL_RCC_C2_BKPRAM_CLK_SLEEP_DISABLE()          (RCC_C2->AHB4LPENR) &= ~ (RCC_AHB4LPENR_BKPRAMLPEN)

+#define __HAL_RCC_C2_D3SRAM1_CLK_SLEEP_DISABLE()         (RCC_C2->AHB4LPENR  &= ~ (RCC_AHB4LPENR_D3SRAM1LPEN))

+

+/** @brief  ENABLE or disable the APB3 peripheral clock during Low Power (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

+  */

+

+#define __HAL_RCC_C2_LTDC_CLK_SLEEP_ENABLE()           (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_LTDCLPEN)

+#define __HAL_RCC_C2_DSI_CLK_SLEEP_ENABLE()            (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_DSILPEN)

+#define __HAL_RCC_C2_WWDG1_CLK_SLEEP_ENABLE()          (RCC_C2->APB3LPENR) |= (RCC_APB3LPENR_WWDG1LPEN)

+

+#define __HAL_RCC_C2_LTDC_CLK_SLEEP_DISABLE()           (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_LTDCLPEN)

+#define __HAL_RCC_C2_DSI_CLK_SLEEP_DISABLE()            (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_DSILPEN)

+#define __HAL_RCC_C2_WWDG1_CLK_SLEEP_DISABLE()          (RCC_C2->APB3LPENR) &= ~ (RCC_APB3LPENR_WWDG1LPEN)

+

+/** @brief  ENABLE or disable the APB1 peripheral clock during Low Power (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

+  */

+

+#define __HAL_RCC_C2_TIM2_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM2LPEN)

+#define __HAL_RCC_C2_TIM3_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM3LPEN)

+#define __HAL_RCC_C2_TIM4_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM4LPEN)

+#define __HAL_RCC_C2_TIM5_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM5LPEN)

+#define __HAL_RCC_C2_TIM6_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM6LPEN)

+#define __HAL_RCC_C2_TIM7_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM7LPEN)

+#define __HAL_RCC_C2_TIM12_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM12LPEN)

+#define __HAL_RCC_C2_TIM13_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM13LPEN)

+#define __HAL_RCC_C2_TIM14_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_TIM14LPEN)

+#define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_ENABLE()         (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_LPTIM1LPEN)

+#define __HAL_RCC_C2_WWDG2_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_WWDG2LPEN)

+#define __HAL_RCC_C2_SPI2_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI2LPEN)

+#define __HAL_RCC_C2_SPI3_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPI3LPEN)

+#define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_ENABLE()        (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_SPDIFRXLPEN)

+#define __HAL_RCC_C2_USART2_CLK_SLEEP_ENABLE()         (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART2LPEN)

+#define __HAL_RCC_C2_USART3_CLK_SLEEP_ENABLE()         (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_USART3LPEN)

+#define __HAL_RCC_C2_UART4_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART4LPEN)

+#define __HAL_RCC_C2_UART5_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART5LPEN)

+#define __HAL_RCC_C2_I2C1_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C1LPEN)

+#define __HAL_RCC_C2_I2C2_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C2LPEN)

+#define __HAL_RCC_C2_I2C3_CLK_SLEEP_ENABLE()           (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_I2C3LPEN)

+#define __HAL_RCC_C2_CEC_CLK_SLEEP_ENABLE()            (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_CECLPEN)

+#define __HAL_RCC_C2_DAC12_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_DAC12LPEN)

+#define __HAL_RCC_C2_UART7_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART7LPEN)

+#define __HAL_RCC_C2_UART8_CLK_SLEEP_ENABLE()          (RCC_C2->APB1LLPENR) |= (RCC_APB1LLPENR_UART8LPEN)

+#define __HAL_RCC_C2_CRS_CLK_SLEEP_ENABLE()            (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_CRSLPEN)

+#define __HAL_RCC_C2_SWPMI_CLK_SLEEP_ENABLE()          (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_SWPMILPEN)

+#define __HAL_RCC_C2_OPAMP_CLK_SLEEP_ENABLE()          (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_OPAMPLPEN)

+#define __HAL_RCC_C2_MDIOS_CLK_SLEEP_ENABLE()          (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_MDIOSLPEN)

+#define __HAL_RCC_C2_FDCAN_CLK_SLEEP_ENABLE()          (RCC_C2->APB1HLPENR) |= (RCC_APB1HLPENR_FDCANLPEN)

+

+

+#define __HAL_RCC_C2_TIM2_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM2LPEN)

+#define __HAL_RCC_C2_TIM3_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM3LPEN)

+#define __HAL_RCC_C2_TIM4_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM4LPEN)

+#define __HAL_RCC_C2_TIM5_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM5LPEN)

+#define __HAL_RCC_C2_TIM6_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM6LPEN)

+#define __HAL_RCC_C2_TIM7_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM7LPEN)

+#define __HAL_RCC_C2_TIM12_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM12LPEN)

+#define __HAL_RCC_C2_TIM13_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM13LPEN)

+#define __HAL_RCC_C2_TIM14_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_TIM14LPEN)

+#define __HAL_RCC_C2_LPTIM1_CLK_SLEEP_DISABLE()         (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_LPTIM1LPEN)

+#define __HAL_RCC_C2_WWDG2_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_WWDG2LPEN)

+#define __HAL_RCC_C2_SPI2_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI2LPEN)

+#define __HAL_RCC_C2_SPI3_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPI3LPEN)

+#define __HAL_RCC_C2_SPDIFRX_CLK_SLEEP_DISABLE()        (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_SPDIFRXLPEN)

+#define __HAL_RCC_C2_USART2_CLK_SLEEP_DISABLE()         (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART2LPEN)

+#define __HAL_RCC_C2_USART3_CLK_SLEEP_DISABLE()         (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_USART3LPEN)

+#define __HAL_RCC_C2_UART4_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART4LPEN)

+#define __HAL_RCC_C2_UART5_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART5LPEN)

+#define __HAL_RCC_C2_I2C1_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C1LPEN)

+#define __HAL_RCC_C2_I2C2_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C2LPEN)

+#define __HAL_RCC_C2_I2C3_CLK_SLEEP_DISABLE()           (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_I2C3LPEN)

+#define __HAL_RCC_C2_CEC_CLK_SLEEP_DISABLE()            (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_CECLPEN)

+#define __HAL_RCC_C2_DAC12_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_DAC12LPEN)

+#define __HAL_RCC_C2_UART7_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART7LPEN)

+#define __HAL_RCC_C2_UART8_CLK_SLEEP_DISABLE()          (RCC_C2->APB1LLPENR) &= ~ (RCC_APB1LLPENR_UART8LPEN)

+#define __HAL_RCC_C2_CRS_CLK_SLEEP_DISABLE()            (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_CRSLPEN)

+#define __HAL_RCC_C2_SWPMI_CLK_SLEEP_DISABLE()          (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_SWPMILPEN)

+#define __HAL_RCC_C2_OPAMP_CLK_SLEEP_DISABLE()          (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_OPAMPLPEN)

+#define __HAL_RCC_C2_MDIOS_CLK_SLEEP_DISABLE()          (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_MDIOSLPEN)

+#define __HAL_RCC_C2_FDCAN_CLK_SLEEP_DISABLE()          (RCC_C2->APB1HLPENR) &= ~ (RCC_APB1HLPENR_FDCANLPEN)

+

+/** @brief  ENABLE or disable the APB2 peripheral clock during Low Power (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

+  */

+

+#define __HAL_RCC_C2_TIM1_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM1LPEN)

+#define __HAL_RCC_C2_TIM8_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM8LPEN)

+#define __HAL_RCC_C2_USART1_CLK_SLEEP_ENABLE()         (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART1LPEN)

+#define __HAL_RCC_C2_USART6_CLK_SLEEP_ENABLE()         (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_USART6LPEN)

+#define __HAL_RCC_C2_SPI1_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI1LPEN)

+#define __HAL_RCC_C2_SPI4_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI4LPEN)

+#define __HAL_RCC_C2_TIM15_CLK_SLEEP_ENABLE()          (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM15LPEN)

+#define __HAL_RCC_C2_TIM16_CLK_SLEEP_ENABLE()          (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM16LPEN)

+#define __HAL_RCC_C2_TIM17_CLK_SLEEP_ENABLE()          (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_TIM17LPEN)

+#define __HAL_RCC_C2_SPI5_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SPI5LPEN)

+#define __HAL_RCC_C2_SAI1_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI1LPEN)

+#define __HAL_RCC_C2_SAI2_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI2LPEN)

+#define __HAL_RCC_C2_SAI3_CLK_SLEEP_ENABLE()           (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_SAI3LPEN)

+#define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_ENABLE()         (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_DFSDM1LPEN)

+#define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_ENABLE()         (RCC_C2->APB2LPENR) |= (RCC_APB2LPENR_HRTIMLPEN)

+

+#define __HAL_RCC_C2_TIM1_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM1LPEN)

+#define __HAL_RCC_C2_TIM8_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM8LPEN)

+#define __HAL_RCC_C2_USART1_CLK_SLEEP_DISABLE()         (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART1LPEN)

+#define __HAL_RCC_C2_USART6_CLK_SLEEP_DISABLE()         (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_USART6LPEN)

+#define __HAL_RCC_C2_SPI1_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI1LPEN)

+#define __HAL_RCC_C2_SPI4_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI4LPEN)

+#define __HAL_RCC_C2_TIM15_CLK_SLEEP_DISABLE()          (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM15LPEN)

+#define __HAL_RCC_C2_TIM16_CLK_SLEEP_DISABLE()          (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM16LPEN)

+#define __HAL_RCC_C2_TIM17_CLK_SLEEP_DISABLE()          (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_TIM17LPEN)

+#define __HAL_RCC_C2_SPI5_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SPI5LPEN)

+#define __HAL_RCC_C2_SAI1_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI1LPEN)

+#define __HAL_RCC_C2_SAI2_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI2LPEN)

+#define __HAL_RCC_C2_SAI3_CLK_SLEEP_DISABLE()           (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_SAI3LPEN)

+#define __HAL_RCC_C2_DFSDM1_CLK_SLEEP_DISABLE()         (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_DFSDM1LPEN)

+#define __HAL_RCC_C2_HRTIM1_CLK_SLEEP_DISABLE()         (RCC_C2->APB2LPENR) &= ~ (RCC_APB2LPENR_HRTIMLPEN)

+

+/** @brief  ENABLE or disable the APB4 peripheral clock during Low Power (Sleep) mode.

+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce

+  *         power consumption.

+  * @note   After wakeup from SLEEP mode, the peripheral clock is ENABLEd again.

+  * @note   By default, all peripheral clocks are ENABLEd during SLEEP mode.

+  */

+

+#define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SYSCFGLPEN)

+#define __HAL_RCC_C2_LPUART1_CLK_SLEEP_ENABLE()          (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPUART1LPEN)

+#define __HAL_RCC_C2_SPI6_CLK_SLEEP_ENABLE()             (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SPI6LPEN)

+#define __HAL_RCC_C2_I2C4_CLK_SLEEP_ENABLE()             (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_I2C4LPEN)

+#define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM2LPEN)

+#define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM3LPEN)

+#define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM4LPEN)

+#define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_LPTIM5LPEN)

+#define __HAL_RCC_C2_COMP12_CLK_SLEEP_ENABLE()           (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_COMP12LPEN)

+#define __HAL_RCC_C2_VREF_CLK_SLEEP_ENABLE()             (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_VREFLPEN)

+#define __HAL_RCC_C2_SAI4_CLK_SLEEP_ENABLE()             (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_SAI4LPEN)

+#define __HAL_RCC_C2_RTC_CLK_SLEEP_ENABLE()              (RCC_C2->APB4LPENR) |= (RCC_APB4LPENR_RTCAPBLPEN)

+

+#define __HAL_RCC_C2_SYSCFG_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SYSCFGLPEN)

+#define __HAL_RCC_C2_LPUART1_CLK_SLEEP_DISABLE()          (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPUART1LPEN)

+#define __HAL_RCC_C2_SPI6_CLK_SLEEP_DISABLE()             (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SPI6LPEN)

+#define __HAL_RCC_C2_I2C4_CLK_SLEEP_DISABLE()             (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_I2C4LPEN)

+#define __HAL_RCC_C2_LPTIM2_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM2LPEN)

+#define __HAL_RCC_C2_LPTIM3_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM3LPEN)

+#define __HAL_RCC_C2_LPTIM4_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM4LPEN)

+#define __HAL_RCC_C2_LPTIM5_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_LPTIM5LPEN)

+#define __HAL_RCC_C2_COMP12_CLK_SLEEP_DISABLE()           (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_COMP12LPEN)

+#define __HAL_RCC_C2_VREF_CLK_SLEEP_DISABLE()             (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_VREFLPEN)

+#define __HAL_RCC_C2_SAI4_CLK_SLEEP_DISABLE()             (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_SAI4LPEN)

+#define __HAL_RCC_C2_RTC_CLK_SLEEP_DISABLE()              (RCC_C2->APB4LPENR) &= ~ (RCC_APB4LPENR_RTCAPBLPEN)

+

+#endif /*DUAL_CORE*/

+

+#if defined(DUAL_CORE)

+/** @brief  Enable or disable peripheral bus clock  when D3 domain is in DRUN

+  * @note   After reset (default config), peripheral clock is disabled when both CPUs are in CSTOP

+  */

+#else

+/** @brief  Enable or disable peripheral bus clock  when D3 domain is in DRUN

+  * @note   After reset (default config), peripheral clock is disabled when CPU is in CSTOP

+  */

+#endif /*DUAL_CORE*/

+

+#if defined(RCC_D3AMR_BDMAAMEN)

+#define __HAL_RCC_BDMA_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_BDMAAMEN)

+#endif

+#if defined(RCC_D3AMR_LPUART1AMEN)

+#define __HAL_RCC_LPUART1_CLKAM_ENABLE()          (RCC->D3AMR) |= (RCC_D3AMR_LPUART1AMEN)

+#endif

+#if defined(RCC_D3AMR_SPI6AMEN)

+#define __HAL_RCC_SPI6_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_SPI6AMEN)

+#endif

+#if defined(RCC_D3AMR_I2C4AMEN)

+#define __HAL_RCC_I2C4_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_I2C4AMEN)

+#endif

+#if defined(RCC_D3AMR_LPTIM2AMEN)

+#define __HAL_RCC_LPTIM2_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM2AMEN)

+#endif

+#if defined(RCC_D3AMR_LPTIM3AMEN)

+#define __HAL_RCC_LPTIM3_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM3AMEN)

+#endif

+#if defined(LPTIM4)

+#define __HAL_RCC_LPTIM4_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM4AMEN)

+#endif

+#if defined(LPTIM5)

+#define __HAL_RCC_LPTIM5_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_LPTIM5AMEN)

+#endif

+#if defined(RCC_D3AMR_COMP12AMEN)

+#define __HAL_RCC_COMP12_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_COMP12AMEN)

+#endif

+#if defined(RCC_D3AMR_VREFAMEN)

+#define __HAL_RCC_VREF_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_VREFAMEN)

+#endif

+#if defined(RCC_D3AMR_RTCAMEN)

+#define __HAL_RCC_RTC_CLKAM_ENABLE()              (RCC->D3AMR) |= (RCC_D3AMR_RTCAMEN)

+#endif

+#if defined(RCC_D3AMR_CRCAMEN)

+#define __HAL_RCC_CRC_CLKAM_ENABLE()              (RCC->D3AMR) |= (RCC_D3AMR_CRCAMEN)

+#endif

+#if defined(SAI4)

+#define __HAL_RCC_SAI4_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_SAI4AMEN)

+#endif

+#if defined(ADC3)

+#define __HAL_RCC_ADC3_CLKAM_ENABLE()             (RCC->D3AMR) |= (RCC_D3AMR_ADC3AMEN)

+#endif

+#if defined(RCC_D3AMR_BKPRAMAMEN)

+#define __HAL_RCC_BKPRAM_CLKAM_ENABLE()           (RCC->D3AMR) |= (RCC_D3AMR_BKPRAMAMEN)

+#endif

+#if defined(RCC_D3AMR_SRAM4AMEN)

+#define __HAL_RCC_D3SRAM1_CLKAM_ENABLE()          (RCC->D3AMR) |= (RCC_D3AMR_SRAM4AMEN)

+#endif

+

+#if defined(BDMA2)

+#define __HAL_RCC_BDMA2_CLKAM_ENABLE()            (RCC->SRDAMR) |= (RCC_SRDAMR_BDMA2AMEN)

+#endif

+#if defined(RCC_SRDAMR_GPIOAMEN)

+#define __HAL_RCC_GPIO_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_GPIOAMEN)

+#endif

+#if defined(RCC_SRDAMR_LPUART1AMEN)

+#define __HAL_RCC_LPUART1_CLKAM_ENABLE()          (RCC->SRDAMR) |= (RCC_SRDAMR_LPUART1AMEN)

+#endif

+#if defined(RCC_SRDAMR_SPI6AMEN)

+#define __HAL_RCC_SPI6_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_SPI6AMEN)

+#endif

+#if defined(RCC_SRDAMR_I2C4AMEN)

+#define __HAL_RCC_I2C4_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_I2C4AMEN)

+#endif

+#if defined(RCC_SRDAMR_LPTIM2AMEN)

+#define __HAL_RCC_LPTIM2_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM2AMEN)

+#endif

+#if defined(RCC_SRDAMR_LPTIM3AMEN)

+#define __HAL_RCC_LPTIM3_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_LPTIM3AMEN)

+#endif

+#if defined(DAC2)

+#define __HAL_RCC_DAC2_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_DAC2AMEN)

+#endif

+#if defined(RCC_SRDAMR_COMP12AMEN)

+#define __HAL_RCC_COMP12_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_COMP12AMEN)

+#endif

+#if defined(RCC_SRDAMR_VREFAMEN)

+#define __HAL_RCC_VREF_CLKAM_ENABLE()             (RCC->SRDAMR) |= (RCC_SRDAMR_VREFAMEN)

+#endif

+#if defined(RCC_SRDAMR_RTCAMEN)

+#define __HAL_RCC_RTC_CLKAM_ENABLE()              (RCC->SRDAMR) |= (RCC_SRDAMR_RTCAMEN)

+#endif

+#if defined(RCC_SRDAMR_DTSAMEN)

+#define __HAL_RCC_DTS_CLKAM_ENABLE()              (RCC->SRDAMR) |= (RCC_SRDAMR_DTSAMEN)

+#endif

+#if defined(DFSDM2_BASE)

+#define __HAL_RCC_DFSDM2_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_DFSDM2AMEN)

+#endif

+#if defined(RCC_SRDAMR_BKPRAMAMEN)

+#define __HAL_RCC_BKPRAM_CLKAM_ENABLE()           (RCC->SRDAMR) |= (RCC_SRDAMR_BKPRAMAMEN)

+#endif

+#if defined(RCC_SRDAMR_SRDSRAMAMEN)

+#define __HAL_RCC_SRDSRAM_CLKAM_ENABLE()          (RCC->SRDAMR) |= (RCC_SRDAMR_SRDSRAMAMEN)

+#endif

+

+#if defined(RCC_D3AMR_BDMAAMEN)

+#define __HAL_RCC_BDMA_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_BDMAAMEN)

+#endif

+#if defined(RCC_D3AMR_LPUART1AMEN)

+#define __HAL_RCC_LPUART1_CLKAM_DISABLE()          (RCC->D3AMR) &= ~ (RCC_D3AMR_LPUART1AMEN)

+#endif

+#if defined(RCC_D3AMR_SPI6AMEN)

+#define __HAL_RCC_SPI6_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_SPI6AMEN)

+#endif

+#if defined(RCC_D3AMR_I2C4AMEN)

+#define __HAL_RCC_I2C4_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_I2C4AMEN)

+#endif

+#if defined(RCC_D3AMR_LPTIM2AMEN)

+#define __HAL_RCC_LPTIM2_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM2AMEN)

+#endif

+#if defined(RCC_D3AMR_LPTIM3AMEN)

+#define __HAL_RCC_LPTIM3_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM3AMEN)

+#endif

+#if defined(LPTIM4)

+#define __HAL_RCC_LPTIM4_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM4AMEN)

+#endif

+#if defined(LPTIM5)

+#define __HAL_RCC_LPTIM5_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_LPTIM5AMEN)

+#endif

+#if defined(RCC_D3AMR_COMP12AMEN)

+#define __HAL_RCC_COMP12_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_COMP12AMEN)

+#endif

+#if defined(RCC_D3AMR_VREFAMEN)

+#define __HAL_RCC_VREF_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_VREFAMEN)

+#endif

+#if defined(RCC_D3AMR_RTCAMEN)

+#define __HAL_RCC_RTC_CLKAM_DISABLE()              (RCC->D3AMR) &= ~ (RCC_D3AMR_RTCAMEN)

+#endif

+#if defined(RCC_D3AMR_CRCAMEN)

+#define __HAL_RCC_CRC_CLKAM_DISABLE()              (RCC->D3AMR) &= ~ (RCC_D3AMR_CRCAMEN)

+#endif

+#if defined(SAI4)

+#define __HAL_RCC_SAI4_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_SAI4AMEN)

+#endif

+#if defined(ADC3)

+#define __HAL_RCC_ADC3_CLKAM_DISABLE()             (RCC->D3AMR) &= ~ (RCC_D3AMR_ADC3AMEN)

+#endif

+#if defined(RCC_D3AMR_BKPRAMAMEN)

+#define __HAL_RCC_BKPRAM_CLKAM_DISABLE()           (RCC->D3AMR) &= ~ (RCC_D3AMR_BKPRAMAMEN)

+#endif

+#if defined(RCC_D3AMR_SRAM4AMEN)

+#define __HAL_RCC_D3SRAM1_CLKAM_DISABLE()          (RCC->D3AMR)&= ~ (RCC_D3AMR_SRAM4AMEN)

+#endif

+

+#if defined(BDMA2)

+#define __HAL_RCC_BDMA2_CLKAM_DISABLE()            (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BDMA2AMEN)

+#endif

+#if defined(RCC_SRDAMR_GPIOAMEN)

+#define __HAL_RCC_GPIO_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_GPIOAMEN)

+#endif

+#if defined(RCC_SRDAMR_LPUART1AMEN)

+#define __HAL_RCC_LPUART1_CLKAM_DISABLE()          (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPUART1AMEN)

+#endif

+#if defined(RCC_SRDAMR_SPI6AMEN)

+#define __HAL_RCC_SPI6_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SPI6AMEN)

+#endif

+#if defined(RCC_SRDAMR_I2C4AMEN)

+#define __HAL_RCC_I2C4_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_I2C4AMEN)

+#endif

+#if defined(RCC_SRDAMR_LPTIM2AMEN)

+#define __HAL_RCC_LPTIM2_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM2AMEN)

+#endif

+#if defined(RCC_SRDAMR_LPTIM3AMEN)

+#define __HAL_RCC_LPTIM3_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~ (RCC_SRDAMR_LPTIM3AMEN)

+#endif

+#if defined(RCC_SRDAMR_DAC2AMEN)

+#define __HAL_RCC_DAC2_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_DAC2AMEN)

+#endif

+#if defined(RCC_SRDAMR_COMP12AMEN)

+#define __HAL_RCC_COMP12_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~ (RCC_SRDAMR_COMP12AMEN)

+#endif

+#if defined(RCC_SRDAMR_VREFAMEN)

+#define __HAL_RCC_VREF_CLKAM_DISABLE()             (RCC->SRDAMR) &= ~ (RCC_SRDAMR_VREFAMEN)

+#endif

+#if defined(RCC_SRDAMR_RTCAMEN)

+#define __HAL_RCC_RTC_CLKAM_DISABLE()              (RCC->SRDAMR) &= ~(RCC_SRDAMR_RTCAMEN)

+#endif

+#if defined(RCC_SRDAMR_DTSAMEN)

+#define __HAL_RCC_DTS_CLKAM_DISABLE()              (RCC->SRDAMR) &= ~(RCC_SRDAMR_DTSAMEN)

+#endif

+#if defined(DFSDM2_BASE)

+#define __HAL_RCC_DFSDM2_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~(RCC_SRDAMR_DFSDM2AMEN)

+#endif

+#if defined(RCC_SRDAMR_BKPRAMAMEN)

+#define __HAL_RCC_BKPRAM_CLKAM_DISABLE()           (RCC->SRDAMR) &= ~ (RCC_SRDAMR_BKPRAMAMEN)

+#endif

+#if defined(RCC_SRDAMR_SRDSRAMAMEN)

+#define __HAL_RCC_SRDSRAM_CLKAM_DISABLE()          (RCC->SRDAMR) &= ~ (RCC_SRDAMR_SRDSRAMAMEN)

+#endif

+

+

+#if defined(RCC_CKGAENR_AXICKG)

+    /** @brief  Macro to enable or disable the RCC_CKGAENR bits (AXI clocks gating enable register).

+  * @note

+  * @note

+  * @note

+  * @param

+  * @note

+  */

+

+#define __HAL_RCC_AXI_CLKGA_ENABLE()             (RCC->CKGAENR) |= (RCC_CKGAENR_AXICKG)

+#define __HAL_RCC_AHB_CLKGA_ENABLE()             (RCC->CKGAENR) |= (RCC_CKGAENR_AHBCKG)

+#define __HAL_RCC_CPU_CLKGA_ENABLE()             (RCC->CKGAENR) |= (RCC_CKGAENR_CPUCKG)

+#define __HAL_RCC_SDMMC_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_SDMMCCKG)

+#define __HAL_RCC_MDMA_CLKGA_ENABLE()            (RCC->CKGAENR) |= (RCC_CKGAENR_MDMACKG)

+#define __HAL_RCC_DMA2D_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_DMA2DCKG)

+#define __HAL_RCC_LTDC_CLKGA_ENABLE()            (RCC->CKGAENR) |= (RCC_CKGAENR_LTDCCKG)

+#define __HAL_RCC_GFXMMUM_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUMCKG)

+#define __HAL_RCC_AHB12_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_AHB12CKG)

+#define __HAL_RCC_AHB34_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_AHB34CKG)

+#define __HAL_RCC_FLIFT_CLKGA_ENABLE()           (RCC->CKGAENR) |= (RCC_CKGAENR_FLIFTCKG)

+#define __HAL_RCC_OCTOSPI2_CLKGA_ENABLE()        (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI2CKG)

+#define __HAL_RCC_FMC_CLKGA_ENABLE()             (RCC->CKGAENR) |= (RCC_CKGAENR_FMCCKG)

+#define __HAL_RCC_OCTOSPI1_CLKGA_ENABLE()        (RCC->CKGAENR) |= (RCC_CKGAENR_OCTOSPI1CKG)

+#define __HAL_RCC_AXIRAM1_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM1CKG)

+#define __HAL_RCC_AXIRAM2_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM2CKG)

+#define __HAL_RCC_AXIRAM3_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_AXIRAM3CKG)

+#define __HAL_RCC_GFXMMUS_CLKGA_ENABLE()         (RCC->CKGAENR) |= (RCC_CKGAENR_GFXMMUSCKG)

+#define __HAL_RCC_ECCRAM_CLKGA_ENABLE()          (RCC->CKGAENR) |= (RCC_CKGAENR_ECCRAMCKG)

+#define __HAL_RCC_EXTI_CLKGA_ENABLE()            (RCC->CKGAENR) |= (RCC_CKGAENR_EXTICKG)

+#define __HAL_RCC_JTAG_CLKGA_ENABLE()            (RCC->CKGAENR) |= (RCC_CKGAENR_JTAGCKG)

+

+

+#define __HAL_RCC_AXI_CLKGA_DISABLE()             (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXICKG)

+#define __HAL_RCC_AHB_CLKGA_DISABLE()             (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHBCKG)

+#define __HAL_RCC_CPU_CLKGA_DISABLE()             (RCC->CKGAENR) &= ~ (RCC_CKGAENR_CPUCKG)

+#define __HAL_RCC_SDMMC_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_SDMMCCKG)

+#define __HAL_RCC_MDMA_CLKGA_DISABLE()            (RCC->CKGAENR) &= ~ (RCC_CKGAENR_MDMACKG)

+#define __HAL_RCC_DMA2D_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_DMA2DCKG)

+#define __HAL_RCC_LTDC_CLKGA_DISABLE()            (RCC->CKGAENR) &= ~ (RCC_CKGAENR_LTDCCKG)

+#define __HAL_RCC_GFXMMUM_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUMCKG)

+#define __HAL_RCC_AHB12_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB12CKG)

+#define __HAL_RCC_AHB34_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AHB34CKG)

+#define __HAL_RCC_FLIFT_CLKGA_DISABLE()           (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FLIFTCKG)

+#define __HAL_RCC_OCTOSPI2_CLKGA_DISABLE()        (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI2CKG)

+#define __HAL_RCC_FMC_CLKGA_DISABLE()             (RCC->CKGAENR) &= ~ (RCC_CKGAENR_FMCCKG)

+#define __HAL_RCC_OCTOSPI1_CLKGA_DISABLE()        (RCC->CKGAENR) &= ~ (RCC_CKGAENR_OCTOSPI1CKG)

+#define __HAL_RCC_AXIRAM1_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM1CKG)

+#define __HAL_RCC_AXIRAM2_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM2CKG)

+#define __HAL_RCC_AXIRAM3_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_AXIRAM3CKG)

+#define __HAL_RCC_GFXMMUS_CLKGA_DISABLE()         (RCC->CKGAENR) &= ~ (RCC_CKGAENR_GFXMMUSCKG)

+#define __HAL_RCC_ECCRAM_CLKGA_DISABLE()          (RCC->CKGAENR) &= ~ (RCC_CKGAENR_ECCRAMCKG)

+#define __HAL_RCC_EXTI_CLKGA_DISABLE()            (RCC->CKGAENR) &= ~ (RCC_CKGAENR_EXTICKG)

+#define __HAL_RCC_JTAG_CLKGA_DISABLE()            (RCC->CKGAENR) &= ~ (RCC_CKGAENR_JTAGCKG)

+

+#endif /* RCC_CKGAENR_AXICKG */

+

+

+

+

+/** @brief  Macro to enable or disable the Internal High Speed oscillator (HSI).

+  * @note     After enabling the HSI, the application software should wait on

+  *           HSIRDY flag to be set indicating that HSI clock is stable and can

+  *           be used to clock the PLL and/or system clock.

+  * @note     HSI can not be stopped if it is used directly or through the PLL

+  *           as system clock. In this case, you have to select another source

+  *           of the system clock then stop the HSI.

+  * @note     The HSI is stopped by hardware when entering STOP and STANDBY modes.

+  * @param    __STATE__ specifies the new state of the HSI.

+  *           This parameter can be one of the following values:

+  *            @arg RCC_HSI_OFF turn OFF the HSI oscillator

+  *            @arg RCC_HSI_ON turn ON the HSI oscillator

+  *            @arg RCC_HSI_DIV1 turn ON the HSI oscillator and divide it by 1 (default after reset)

+  *            @arg RCC_HSI_DIV2 turn ON the HSI oscillator and divide it by 2

+  *            @arg RCC_HSI_DIV4 turn ON the HSI oscillator and divide it by 4

+  *            @arg RCC_HSI_DIV8 turn ON the HSI oscillator and divide it by 8

+  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator

+  *         clock cycles.

+  */

+#define __HAL_RCC_HSI_CONFIG(__STATE__) \

+                  MODIFY_REG(RCC->CR, RCC_CR_HSION | RCC_CR_HSIDIV , (uint32_t)(__STATE__))

+

+

+/** @brief  Macro to get the HSI divider.

+  * @retval The HSI divider. The returned value can be one

+  *         of the following:

+  *            - RCC_CR_HSIDIV_1  HSI oscillator divided by 1 (default after reset)

+  *            - RCC_CR_HSIDIV_2  HSI oscillator divided by 2

+  *            - RCC_CR_HSIDIV_4  HSI oscillator divided by 4

+  *            - RCC_CR_HSIDIV_8  HSI oscillator divided by 8

+  */

+#define __HAL_RCC_GET_HSI_DIVIDER() ((uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV)))

+

+/** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).

+  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.

+  *         It is used (enabled by hardware) as system clock source after start-up

+  *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure

+  *         of the HSE used directly or indirectly as system clock (if the Clock

+  *         Security System CSS is enabled).

+  * @note   HSI can not be stopped if it is used as system clock source. In this case,

+  *         you have to select another source of the system clock then stop the HSI.

+  * @note   After enabling the HSI, the application software should wait on HSIRDY

+  *         flag to be set indicating that HSI clock is stable and can be used as

+  *         system clock source.

+  *         This parameter can be: ENABLE or DISABLE.

+  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator

+  *         clock cycles.

+  */

+#define __HAL_RCC_HSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_HSION)

+#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)

+

+

+/** @brief  Macro to adjust the Internal High Speed oscillator (HSI) calibration value.

+  * @note   The calibration is used to compensate for the variations in voltage

+  *         and temperature that influence the frequency of the internal HSI RC.

+  * @param  __HSICalibrationValue__: specifies the calibration trimming value.

+  *         This parameter must be a number between 0 and 0x7F (3F for Rev Y device).

+  */

+#if defined(RCC_VER_X)

+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__)                                                                   \

+           do {                                                                                                                          \

+              if(HAL_GetREVID() <= REV_ID_Y)                                                                                             \

+             {                                                                                                                           \

+               MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_HSITRIM_Msk, (uint32_t)(__HSICalibrationValue__) << HAL_RCC_REV_Y_HSITRIM_Pos);    \

+             }                                                                                                                           \

+             else                                                                                                                        \

+             {                                                                                                                           \

+               MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos);            \

+             }                                                                                                                           \

+           } while(0)

+

+#else

+#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__)                                                                   \

+               MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_HSICFGR_HSITRIM_Pos);

+#endif /*RCC_VER_X*/

+/**

+  * @brief    Macros to enable or disable the force of the Internal High Speed oscillator (HSI)

+  *           in STOP mode to be quickly available as kernel clock for some peripherals.

+  * @note     Keeping the HSI ON in STOP mode allows to avoid slowing down the communication

+  *           speed because of the HSI start-up time.

+  * @note     The enable of this function has not effect on the HSION bit.

+  *           This parameter can be: ENABLE or DISABLE.

+  * @retval None

+  */

+#define __HAL_RCC_HSISTOP_ENABLE()     SET_BIT(RCC->CR, RCC_CR_HSIKERON)

+#define __HAL_RCC_HSISTOP_DISABLE()    CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)

+

+

+/**

+  * @brief  Macro to enable or disable the Internal High Speed oscillator for USB (HSI48).

+  * @note   After enabling the HSI48, the application software should wait on

+  *         HSI48RDY flag to be set indicating that HSI48 clock is stable and can

+  *         be used to clock the USB.

+  * @note   The HSI48 is stopped by hardware when entering STOP and STANDBY modes.

+  */

+#define __HAL_RCC_HSI48_ENABLE()    SET_BIT(RCC->CR, RCC_CR_HSI48ON);

+

+#define __HAL_RCC_HSI48_DISABLE()   CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);

+

+/**

+  * @brief  Macros to enable or disable the Internal  oscillator (CSI).

+  * @note     The CSI is stopped by hardware when entering STOP and STANDBY modes.

+  *           It is used (enabled by hardware) as system clock source after

+  *           start-up from Reset, wakeup from STOP and STANDBY mode, or in case

+  *           of failure of the HSE used directly or indirectly as system clock

+  *           (if the Clock Security System CSS is enabled).

+  * @note     CSI can not be stopped if it is used as system clock source.

+  *           In this case, you have to select another source of the system

+  *           clock then stop the CSI.

+  * @note     After enabling the CSI, the application software should wait on

+  *           CSIRDY flag to be set indicating that CSI clock is stable and can

+  *           be used as system clock source.

+  * @note     When the CSI is stopped, CSIRDY flag goes low after 6 CSI oscillator

+  *           clock cycles.

+  */

+#define __HAL_RCC_CSI_ENABLE()  SET_BIT(RCC->CR, RCC_CR_CSION)

+#define __HAL_RCC_CSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_CSION)

+

+/** @brief  Macro Adjusts the Internal  oscillator (CSI) calibration value.

+  * @note   The calibration is used to compensate for the variations in voltage

+  *         and temperature that influence the frequency of the internal CSI RC.

+  * @param  __CSICalibrationValue__: specifies the calibration trimming value.

+  *         This parameter must be a number between 0 and 0x1F.

+  */

+#if defined(RCC_VER_X)

+#define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__)                                                                   \

+           do {                                                                                                                          \

+             if(HAL_GetREVID() <= REV_ID_Y)                                                                                              \

+             {                                                                                                                           \

+               MODIFY_REG(RCC->HSICFGR, HAL_RCC_REV_Y_CSITRIM_Msk, (uint32_t)(__CSICalibrationValue__) << HAL_RCC_REV_Y_CSITRIM_Pos);    \

+             }                                                                                                                           \

+             else                                                                                                                        \

+             {                                                                                                                           \

+               MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos);            \

+             }                                                                                                                           \

+           } while(0)

+

+#else

+#define __HAL_RCC_CSI_CALIBRATIONVALUE_ADJUST(__CSICalibrationValue__)                                                                   \

+           do {                                                                                                                          \

+               MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, (uint32_t)(__CSICalibrationValue__) << RCC_CSICFGR_CSITRIM_Pos);            \

+               } while(0)

+

+#endif /*RCC_VER_X*/

+/**

+  * @brief    Macros to enable or disable the force of the Low-power Internal oscillator (CSI)

+  *           in STOP mode to be quickly available as kernel clock for USARTs and I2Cs.

+  * @note     Keeping the CSI ON in STOP mode allows to avoid slowing down the communication

+  *           speed because of the CSI start-up time.

+  * @note     The enable of this function has not effect on the CSION bit.

+  *           This parameter can be: ENABLE or DISABLE.

+  * @retval None

+  */

+#define __HAL_RCC_CSISTOP_ENABLE()     SET_BIT(RCC->CR, RCC_CR_CSIKERON)

+#define __HAL_RCC_CSISTOP_DISABLE()    CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON)

+

+

+/** @brief  Macros to enable or disable the Internal Low Speed oscillator (LSI).

+  * @note   After enabling the LSI, the application software should wait on

+  *         LSIRDY flag to be set indicating that LSI clock is stable and can

+  *         be used to clock the IWDG and/or the RTC.

+  * @note   LSI can not be disabled if the IWDG is running.

+  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator

+  *         clock cycles.

+  */

+#define __HAL_RCC_LSI_ENABLE()         SET_BIT(RCC->CSR, RCC_CSR_LSION)

+#define __HAL_RCC_LSI_DISABLE()        CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)

+

+/**

+  * @brief  Macro to configure the External High Speed oscillator (__HSE__).

+  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application

+  *         software should wait on HSERDY flag to be set indicating that HSE clock

+  *         is stable and can be used to clock the PLL and/or system clock.

+  * @note   HSE state can not be changed if it is used directly or through the

+  *         PLL as system clock. In this case, you have to select another source

+  *         of the system clock then change the HSE state (ex. disable it).

+  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.

+  * @note   This function reset the CSSON bit, so if the clock security system(CSS)

+  *         was previously enabled you have to enable it again after calling this

+  *         function.

+  * @param  __STATE__: specifies the new state of the HSE.

+  *         This parameter can be one of the following values:

+  *            @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after

+  *                              6 HSE oscillator clock cycles.

+  *            @arg RCC_HSE_ON: turn ON the HSE oscillator.

+  *            @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.

+  */

+#if defined(RCC_CR_HSEEXT)

+#define __HAL_RCC_HSE_CONFIG(__STATE__)                                \

+                    do {                                               \

+                      if ((__STATE__) == RCC_HSE_ON)                   \

+                      {                                                \

+                        SET_BIT(RCC->CR, RCC_CR_HSEON);                \

+                      }                                                \

+                      else if ((__STATE__) == RCC_HSE_OFF)             \

+                      {                                                \

+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);              \

+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);             \

+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);             \

+                      }                                                \

+                      else if ((__STATE__) == RCC_HSE_BYPASS)          \

+                      {                                                \

+                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);               \

+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);             \

+                        SET_BIT(RCC->CR, RCC_CR_HSEON);                \

+                      }                                                \

+                      else if((__STATE__) == RCC_HSE_BYPASS_DIGITAL)   \

+                      {                                                \

+                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);               \

+                        SET_BIT(RCC->CR, RCC_CR_HSEEXT);               \

+                        SET_BIT(RCC->CR, RCC_CR_HSEON);                \

+                      }                                                \

+                      else                                             \

+                      {                                                \

+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);              \

+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);             \

+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);             \

+                      }                                                \

+                    } while(0)

+#else

+#define __HAL_RCC_HSE_CONFIG(__STATE__)                         \

+                    do {                                        \

+                      if ((__STATE__) == RCC_HSE_ON)            \

+                      {                                         \

+                        SET_BIT(RCC->CR, RCC_CR_HSEON);         \

+                      }                                         \

+                      else if ((__STATE__) == RCC_HSE_OFF)      \

+                      {                                         \

+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \

+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \

+                      }                                         \

+                      else if ((__STATE__) == RCC_HSE_BYPASS)   \

+                      {                                         \

+                        SET_BIT(RCC->CR, RCC_CR_HSEBYP);        \

+                        SET_BIT(RCC->CR, RCC_CR_HSEON);         \

+                      }                                         \

+                      else                                      \

+                      {                                         \

+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEON);       \

+                        CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);      \

+                      }                                         \

+                    } while(0)

+#endif /* RCC_CR_HSEEXT */

+

+/** @defgroup RCC_LSE_Configuration LSE Configuration

+  * @{

+  */

+

+/**

+  * @brief  Macro to configure the External Low Speed oscillator (LSE).

+  * @note   Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.

+  *         User should request a transition to LSE Off first and then LSE On or LSE Bypass.

+  * @note   The external input clock can have a frequency up to 1 MHz and be low swing (analog) or digital(*).

+            A duty cycle close to 50% is recommended.

+  * @note   As the LSE is in the Backup domain and write access is denied to

+  *         this domain after reset, you have to enable write access using

+  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE

+  *         (to be done once after reset).

+  * @note   After enabling the LSE (RCC_LSE_ON, RCC_LSE_BYPASS or RCC_LSE_BYPASS_DIGITAL*), the application

+  *         software should wait on LSERDY flag to be set indicating that LSE clock

+  *         is stable and can be used to clock the RTC.

+  * @note   If the RTC is used, the LSE bypass must not be configured in digital mode but in low swing analog mode (*)

+  * @param  __STATE__: specifies the new state of the LSE.

+  *         This parameter can be one of the following values:

+  *            @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after

+  *                              6 LSE oscillator clock cycles.

+  *            @arg RCC_LSE_ON: turn ON the LSE oscillator.

+  *            @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.

+  *            @arg RCC_LSE_BYPASS_DIGITAL: LSE oscillator bypassed with external digital clock. (*)

+  *

+  *         (*) Available on some STM32H7 lines only.

+  */

+#if defined(RCC_BDCR_LSEEXT)

+#define __HAL_RCC_LSE_CONFIG(__STATE__) \

+                    do {                                               \

+                      if((__STATE__) == RCC_LSE_ON)                    \

+                      {                                                \

+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);            \

+                      }                                                \

+                      else if((__STATE__) == RCC_LSE_OFF)              \

+                      {                                                \

+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);          \

+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);         \

+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);         \

+                      }                                                \

+                      else if((__STATE__) == RCC_LSE_BYPASS)           \

+                      {                                                \

+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);           \

+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);         \

+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);            \

+                      }                                                \

+                      else if((__STATE__) == RCC_LSE_BYPASS_DIGITAL)   \

+                      {                                                \

+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);           \

+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);           \

+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);            \

+                      }                                                \

+                      else                                             \

+                      {                                                \

+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);          \

+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);         \

+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);         \

+                      }                                                \

+                    } while(0)

+#else

+

+#define __HAL_RCC_LSE_CONFIG(__STATE__) \

+                    do {                                       \

+                      if((__STATE__) == RCC_LSE_ON)            \

+                      {                                        \

+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \

+                      }                                        \

+                      else if((__STATE__) == RCC_LSE_OFF)      \

+                      {                                        \

+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \

+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \

+                      }                                        \

+                      else if((__STATE__) == RCC_LSE_BYPASS)   \

+                      {                                        \

+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);   \

+                        SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);    \

+                      }                                        \

+                      else                                     \

+                      {                                        \

+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);  \

+                        CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \

+                      }                                        \

+                    } while(0)

+

+#endif /* RCC_BDCR_LSEEXT */

+/**

+  * @}

+  */

+

+/** @brief  Macros to enable or disable the the RTC clock.

+  * @note   These macros must be used only after the RTC clock source was selected.

+  */

+#define __HAL_RCC_RTC_ENABLE()         SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)

+#define __HAL_RCC_RTC_DISABLE()        CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)

+

+/** @brief  Macros to configure the RTC clock (RTCCLK).

+  * @note   As the RTC clock configuration bits are in the Backup domain and write

+  *         access is denied to this domain after reset, you have to enable write

+  *         access using the Power Backup Access macro before to configure

+  *         the RTC clock source (to be done once after reset).

+  * @note   Once the RTC clock is configured it can't be changed unless the

+  *         Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by

+  *         a Power On Reset (POR).

+  * @param  __RTCCLKSource__: specifies the RTC clock source.

+  *         This parameter can be one of the following values:

+  *            @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.

+  *            @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.

+  *            @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected

+  *                                            as RTC clock, where x:[2,31]

+  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to

+  *         work in STOP and STANDBY modes, and can be used as wakeup source.

+  *         However, when the HSE clock is used as RTC clock source, the RTC

+  *         cannot be used in STOP and STANDBY modes.

+  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as

+  *         RTC clock source).

+  */

+#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ?    \

+                                                 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, (((__RTCCLKSource__) & 0xFFFFCFFU) >> 4)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)

+

+#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__);    \

+                                                    RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU);  \

+                                                   } while (0)

+

+#define  __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))

+

+

+/** @brief  Macros to force or release the Backup domain reset.

+  * @note   This function resets the RTC peripheral (including the backup registers)

+  *         and the RTC clock source selection in RCC_BDCR register.

+  * @note   The BKPSRAM is not affected by this reset.

+  */

+#define __HAL_RCC_BACKUPRESET_FORCE()   SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)

+#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)

+

+/** @brief  Macros to enable or disable the main PLL.

+  * @note   After enabling the main PLL, the application software should wait on

+  *         PLLRDY flag to be set indicating that PLL clock is stable and can

+  *         be used as system clock source.

+  * @note   The main PLL can not be disabled if it is used as system clock source

+  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.

+  */

+#define __HAL_RCC_PLL_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLL1ON)

+#define __HAL_RCC_PLL_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON)

+

+/**

+  * @brief  Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK)

+  * @note   Enabling/disabling  those Clocks can be done only when the PLL is disabled.

+  *         This is mainly used to save Power.

+  *        (The ck_pll_p of the System PLL cannot be stopped if used as System Clock).

+  * @param  __RCC_PLL1ClockOut__: specifies the PLL clock to be outputted

+  *          This parameter can be one of the following values:

+  *            @arg RCC_PLL1_DIVP: This clock is used to generate system clock up to 400MHZ or 280MHZ(*)

+  *            @arg RCC_PLL1_DIVQ: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)

+  *            @arg RCC_PLL1_DIVR: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)

+  *

+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.

+  *

+  * @retval None

+  */

+#define __HAL_RCC_PLLCLKOUT_ENABLE(__RCC_PLL1ClockOut__)   SET_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))

+

+#define __HAL_RCC_PLLCLKOUT_DISABLE(__RCC_PLL1ClockOut__)  CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL1ClockOut__))

+

+

+/**

+  * @brief  Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO

+  * @note   Enabling/disabling  Fractional Part can be any time  without the need to stop the PLL1

+  * @retval None

+  */

+#define __HAL_RCC_PLLFRACN_ENABLE()   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)

+

+#define __HAL_RCC_PLLFRACN_DISABLE()  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN)

+

+

+/**

+  * @brief  Macro to configures the main PLL clock source, multiplication and division factors.

+  * @note   This function must be used only when the main PLL is disabled.

+  *

+  * @param  __RCC_PLLSOURCE__: specifies the PLL entry clock source.

+  *          This parameter can be one of the following values:

+  *            @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry

+  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry

+  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry

+  * @note   This clock source (__RCC_PLLSource__) is common for the main PLL1 (main PLL) and PLL2 & PLL3 .

+  *

+  * @param  __PLLM1__: specifies the division factor for PLL VCO input clock

+  *          This parameter must be a number between 1 and 63.

+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input

+  *         frequency ranges from 1 to 16 MHz.

+  *

+  * @param  __PLLN1__: specifies the multiplication factor for PLL VCO output clock

+  *          This parameter must be a number between 4 and 512 or between 8 and 420(*).

+  * @note   You have to set the PLLN parameter correctly to ensure that the VCO

+  *         output frequency is between 150 and 420 MHz (when in medium VCO range) or

+  *         between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)

+  *

+  * @param  __PLLP1__: specifies the division factor for system  clock.

+  *          This parameter must be a number between 2 and 128 (where odd numbers are not allowed)

+  *

+  * @param  __PLLQ1__: specifies the division factor for peripheral kernel clocks

+  *          This parameter must be a number between 1 and 128

+  *

+  * @param  __PLLR1__: specifies the division factor for peripheral kernel clocks

+  *          This parameter must be a number between 1 and 128

+  *

+  * @note   To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR)

+  *         is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible 

+  *         value to  __PLL1P__, __PLL1Q__ or __PLL1R__ parameters.

+  * @retval None

+  *

+  *  (*) : For stm32h7a3xx and stm32h7b3xx family lines.

+  */

+

+

+#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLM1__, __PLLN1__, __PLLP1__, __PLLQ1__,__PLLR1__ ) \

+                  do{ MODIFY_REG(RCC->PLLCKSELR, (RCC_PLLCKSELR_PLLSRC | RCC_PLLCKSELR_DIVM1) , ((__RCC_PLLSOURCE__) | ( (__PLLM1__) <<4U)));  \

+                      WRITE_REG (RCC->PLL1DIVR , ( (((__PLLN1__) - 1U )& RCC_PLL1DIVR_N1) | ((((__PLLP1__) -1U ) << 9U) & RCC_PLL1DIVR_P1) | \

+                                ((((__PLLQ1__) -1U) << 16U)& RCC_PLL1DIVR_Q1) | ((((__PLLR1__) - 1U) << 24U)& RCC_PLL1DIVR_R1))); \

+                    } while(0)

+

+

+/** @brief  Macro to configure the PLLs clock source.

+  * @note   This function must be used only when all PLLs are disabled.

+  * @param  __PLLSOURCE__: specifies the PLLs entry clock source.

+  *         This parameter can be one of the following values:

+  *            @arg RCC_PLLSOURCE_CSI: CSI oscillator clock selected as PLL clock entry

+  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry

+  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry

+  *

+  */

+#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, (__PLLSOURCE__))

+

+

+/**

+  * @brief  Macro to configures the main PLL clock Fractional Part Of The Multiplication Factor

+  *

+  * @note   These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO

+  *

+  * @param  __RCC_PLL1FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL1 VCO

+  *                            It should be a value between 0 and 8191

+  * @note   Warning: The software has to set correctly these bits to insure that the VCO

+  *                  output frequency is between its valid frequency range, which is:

+  *                   192 to 836 MHz or 128 to 560 MHz(*) if PLL1VCOSEL = 0

+  *                   150 to 420 MHz if PLL1VCOSEL = 1.

+  *

+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.

+  *

+  * @retval None

+  */

+ #define  __HAL_RCC_PLLFRACN_CONFIG(__RCC_PLL1FRACN__) MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, (uint32_t)(__RCC_PLL1FRACN__) << RCC_PLL1FRACR_FRACN1_Pos)

+

+

+/** @brief  Macro to select  the PLL1  reference frequency range.

+  * @param  __RCC_PLL1VCIRange__: specifies the PLL1 input frequency range

+  *         This parameter can be one of the following values:

+  *            @arg RCC_PLL1VCIRANGE_0: Range frequency is between 1 and 2 MHz

+  *            @arg RCC_PLL1VCIRANGE_1: Range frequency is between 2 and 4 MHz

+  *            @arg RCC_PLL1VCIRANGE_2: Range frequency is between 4 and 8 MHz

+  *            @arg RCC_PLL1VCIRANGE_3: Range frequency is between 8 and 16 MHz

+  * @retval None

+  */

+#define __HAL_RCC_PLL_VCIRANGE(__RCC_PLL1VCIRange__) \

+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, (__RCC_PLL1VCIRange__))

+

+

+/** @brief  Macro to select  the PLL1  reference frequency range.

+  * @param  __RCC_PLL1VCORange__: specifies the PLL1 input frequency range

+  *         This parameter can be one of the following values:

+  *            @arg RCC_PLL1VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*)

+  *            @arg RCC_PLL1VCOMEDIUM: Range frequency is between 150 and 420 MHz

+  *

+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.

+  *

+  * @retval None

+  */

+#define __HAL_RCC_PLL_VCORANGE(__RCC_PLL1VCORange__) \

+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, (__RCC_PLL1VCORange__))

+

+

+

+/** @brief  Macro to get the clock source used as system clock.

+  * @retval The clock source used as system clock. The returned value can be one

+  *         of the following:

+  *              - RCC_CFGR_SWS_CSI: CSI used as system clock.

+  *              - RCC_CFGR_SWS_HSI: HSI used as system clock.

+  *              - RCC_CFGR_SWS_HSE: HSE used as system clock.

+  *              - RCC_CFGR_SWS_PLL: PLL used as system clock.

+  */

+#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))

+

+

+/**

+  * @brief Macro to configure the system clock source.

+  * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.

+  * This parameter can be one of the following values:

+  *              - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.

+  *              - RCC_SYSCLKSOURCE_CSI: CSI oscillator is used as system clock source.

+  *              - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.

+  *              - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.

+  */

+#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))

+

+/** @brief  Macro to get the oscillator used as PLL clock source.

+  * @retval The oscillator used as PLL clock source. The returned value can be one

+  *         of the following:

+  *              - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source.

+  *              - RCC_PLLSOURCE_CSI: CSI oscillator is used as PLL clock source.

+  *              - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.

+  *              - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.

+  */

+#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC))

+

+/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config

+  * @{

+  */

+

+/** @brief  Macro to configure the MCO1 clock.

+  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.

+  *          This parameter can be one of the following values:

+  *            @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source

+  *            @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source

+  *            @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source

+  *            @arg RCC_MCO1SOURCE_PLL1QCLK:  PLL1Q clock selected as MCO1 source

+  *            @arg RCC_MCO1SOURCE_HSI48: HSI48 (48MHZ) selected as MCO1 source

+  * @param  __MCODIV__ specifies the MCO clock prescaler.

+  *          This parameter can be one of the following values:

+  *            @arg RCC_MCODIV_1 up to RCC_MCODIV_15  : divider applied to MCO1 clock

+  */

+#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \

+                 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), ((__MCOCLKSOURCE__) | (__MCODIV__)))

+

+/** @brief  Macro to configure the MCO2 clock.

+  * @param  __MCOCLKSOURCE__ specifies the MCO clock source.

+  *          This parameter can be one of the following values:

+  *            @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source

+  *            @arg RCC_MCO2SOURCE_PLL2PCLK: PLL2P clock selected as MCO2 source

+  *            @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source

+  *            @arg RCC_MCO2SOURCE_PLLCLK:  PLL1P clock selected as MCO2 source

+  *            @arg RCC_MCO2SOURCE_CSICLK:  CSI clock selected as MCO2 source

+  *            @arg RCC_MCO2SOURCE_LSICLK:  LSI clock selected as MCO2 source

+  * @param  __MCODIV__ specifies the MCO clock prescaler.

+  *          This parameter can be one of the following values:

+  *            @arg RCC_MCODIV_1 up to RCC_MCODIV_15  : divider applied to MCO2 clock

+  */

+#define __HAL_RCC_MCO2_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \

+    MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), ((__MCOCLKSOURCE__) | ((__MCODIV__) << 7)));

+

+/**

+  * @}

+  */

+

+/**

+  * @brief  Macro to configure the External Low Speed oscillator (LSE) drive capability.

+  * @note   As the LSE is in the Backup domain and write access is denied to

+  *         this domain after reset, you have to enable write access using

+  *         HAL_PWR_EnableBkUpAccess() function before to configure the LSE

+  *         (to be done once after reset).

+  * @note   On STM32H7 Rev.B and above devices this can't be updated while LSE is ON.

+  * @param  __LSEDRIVE__: specifies the new state of the LSE drive capability.

+  *          This parameter can be one of the following values:

+  *            @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.

+  *            @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.

+  *            @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.

+  *            @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.

+  * @retval None

+  */

+#if defined(RCC_VER_X)

+#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \

+           do{                                                                                                                                \

+             if((HAL_GetREVID() <= REV_ID_Y) && (((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || ((__LSEDRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH)))  \

+             {                                                                                                                                \

+              MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (~(uint32_t)(__LSEDRIVE__)) & RCC_BDCR_LSEDRV_Msk);                                      \

+             }                                                                                                                                \

+             else                                                                                                                             \

+             {                                                                                                                                \

+               MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__));                                                              \

+             }                                                                                                                                \

+           } while(0)

+#else

+#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \

+               MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__));

+#endif /*RCC_VER_X*/

+/**

+  * @brief  Macro to configure the wake up from stop clock.

+  * @param  __RCC_STOPWUCLK__: specifies the clock source used after wake up from stop

+  *         This parameter can be one of the following values:

+  *            @arg RCC_STOP_WAKEUPCLOCK_CSI: CSI selected as system clock source

+  *            @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source

+  * @retval None

+  */

+#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) \

+                  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, (__RCC_STOPWUCLK__))

+

+/**

+  * @brief  Macro to configure the Kernel wake up from stop clock.

+  * @param  __RCC_STOPKERWUCLK__: specifies the Kernel clock source used after wake up from stop

+  *         This parameter can be one of the following values:

+  *            @arg RCC_STOP_KERWAKEUPCLOCK_CSI: CSI selected as Kernel clock source

+  *            @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI selected as Kernel clock source

+  * @retval None

+  */

+#define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) \

+                  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, (__RCC_STOPKERWUCLK__))

+

+/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management

+  * @brief macros to manage the specified RCC Flags and interrupts.

+  * @{

+  */

+/** @brief  Enable RCC interrupt.

+  * @param  __INTERRUPT__: specifies the RCC interrupt sources to be enabled.

+  *         This parameter can be any combination of the following values:

+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt

+  *            @arg RCC_IT_LSERDY: LSE ready interrupt

+  *            @arg RCC_IT_CSIRDY: HSI ready interrupt

+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt

+  *            @arg RCC_IT_HSERDY: HSE ready interrupt

+  *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt

+  *            @arg RCC_IT_PLLRDY: main PLL ready interrupt

+  *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt

+  *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt

+  *            @arg RCC_IT_LSECSS: Clock security system interrupt

+  */

+#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__))

+

+/** @brief Disable RCC interrupt

+  * @param  __INTERRUPT__: specifies the RCC interrupt sources to be disabled.

+  *         This parameter can be any combination of the following values:

+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt

+  *            @arg RCC_IT_LSERDY: LSE ready interrupt

+  *            @arg RCC_IT_CSIRDY: HSI ready interrupt

+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt

+  *            @arg RCC_IT_HSERDY: HSE ready interrupt

+  *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt

+  *            @arg RCC_IT_PLLRDY: main PLL ready interrupt

+  *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt

+  *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt

+  *            @arg RCC_IT_LSECSS: Clock security system interrupt

+  */

+#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__))

+

+/** @brief  Clear the RCC's interrupt pending bits

+  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.

+  *         This parameter can be any combination of the following values:

+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt

+  *            @arg RCC_IT_LSERDY: LSE ready interrupt

+  *            @arg RCC_IT_CSIRDY: CSI ready interrupt

+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt

+  *            @arg RCC_IT_HSERDY: HSE ready interrupt

+  *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt

+  *            @arg RCC_IT_PLLRDY: main PLL ready interrupt

+  *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt

+  *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt

+  *            @arg RCC_IT_HSECSS: HSE Clock Security interrupt

+  *            @arg RCC_IT_LSECSS: Clock security system interrupt

+  */

+#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (RCC->CICR = (__INTERRUPT__))

+

+/** @brief  Check the RCC's interrupt has occurred or not.

+  * @param  __INTERRUPT__: specifies the RCC interrupt source to check.

+  *         This parameter can be any combination of the following values:

+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt

+  *            @arg RCC_IT_LSERDY: LSE ready interrupt

+  *            @arg RCC_IT_CSIRDY: CSI ready interrupt

+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt

+  *            @arg RCC_IT_HSERDY: HSE ready interrupt

+  *            @arg RCC_IT_HSI48RDY: HSI48 ready interrupt

+  *            @arg RCC_IT_PLLRDY: main PLL ready interrupt

+  *            @arg RCC_IT_PLL2RDY: PLL2 ready interrupt

+  *            @arg RCC_IT_PLL3RDY: PLL3 ready interrupt

+  *            @arg RCC_IT_HSECSS: HSE Clock Security interrupt

+  *            @arg RCC_IT_LSECSS: Clock security system interrupt

+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).

+  */

+#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__))

+

+/** @brief Set RMVF bit to clear the reset flags.

+  */

+#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->RSR |= RCC_RSR_RMVF)

+

+#if defined(DUAL_CORE)

+#define __HAL_RCC_C1_CLEAR_RESET_FLAGS() (RCC_C1->RSR |= RCC_RSR_RMVF)

+

+#define __HAL_RCC_C2_CLEAR_RESET_FLAGS() (RCC_C2->RSR |= RCC_RSR_RMVF)

+#endif /*DUAL_CORE*/

+

+#if defined(DUAL_CORE)

+/** @brief  Check RCC flag is set or not.

+  * @param  __FLAG__: specifies the flag to check.

+  *         This parameter can be one of the following values:

+  *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready

+  *            @arg RCC_FLAG_HSIDIV: HSI divider flag

+  *            @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready

+  *            @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready

+  *            @arg RCC_FLAG_HSERDY:  HSE oscillator clock ready

+  *            @arg RCC_FLAG_D1CKRDY:  Domain1 clock ready

+  *            @arg RCC_FLAG_D2CKRDY:  Domain2 clock ready

+  *            @arg RCC_FLAG_PLLRDY:  PLL1 clock ready

+  *            @arg RCC_FLAG_PLL2RDY: PLL2 clock ready

+  *            @arg RCC_FLAG_PLL3RDY: PLL3 clock ready

+  *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready

+  *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready

+  *            @arg RCC_FLAG_C1RST:  CPU reset flag

+  *            @arg RCC_FLAG_C2RST:  CPU2 reset flag

+  *            @arg RCC_FLAG_D1RST:  D1 domain power switch reset flag

+  *            @arg RCC_FLAG_D2RST:  D2 domain power switch reset flag

+  *            @arg RCC_FLAG_BORRST: BOR reset flag

+  *            @arg RCC_FLAG_PINRST: Pin reset

+  *            @arg RCC_FLAG_PORRST: POR/PDR  reset

+  *            @arg RCC_FLAG_SFTR1ST: System reset from CPU reset flag

+  *            @arg RCC_FLAG_SFTR2ST: System reset from CPU2 reset flag

+  *            @arg RCC_FLAG_BORRST:   D2 domain power switch reset flag

+  *            @arg RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset

+  *            @arg RCC_FLAG_IWDG2RST: CPU2 Independent Watchdog reset

+  *            @arg RCC_FLAG_WWDG2RST: Window Watchdog2 reset

+  *            @arg RCC_FLAG_WWDG1RST: Window Watchdog1 reset

+  *            @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag

+  *            @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY or CPU2 CSTOP flag

+  * @retval The new state of __FLAG__ (TRUE or FALSE).

+  */

+#define RCC_FLAG_MASK  ((uint8_t)0x1F)

+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \

+((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR))))  & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)

+

+#define __HAL_RCC_C1_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \

+((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C1->RSR :RCC->CIFR))))  & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)

+

+#define __HAL_RCC_C2_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \

+((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC_C2->RSR :RCC->CIFR))))  & (1U << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)

+

+#else

+

+/** @brief  Check RCC flag is set or not.

+  * @param  __FLAG__: specifies the flag to check.

+  *         This parameter can be one of the following values:

+  *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready

+  *            @arg RCC_FLAG_HSIDIV: HSI divider flag

+  *            @arg RCC_FLAG_CSIRDY: CSI oscillator clock ready

+  *            @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready

+  *            @arg RCC_FLAG_HSERDY:  HSE oscillator clock ready

+  *            @arg RCC_FLAG_D1CKRDY:  Domain1 clock ready (*)

+  *            @arg RCC_FLAG_D2CKRDY:  Domain2 clock ready (*)

+  *            @arg RCC_FLAG_CPUCKRDY: CPU Domain clock ready (CPU, APB3, bus matrix1 and related memories) (*)

+  *            @arg RCC_FLAG_CDCKRDY:  CPU Domain clock ready (*)

+  *            @arg RCC_FLAG_PLLRDY:  PLL1 clock ready

+  *            @arg RCC_FLAG_PLL2RDY: PLL2 clock ready

+  *            @arg RCC_FLAG_PLL3RDY: PLL3 clock ready

+  *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready

+  *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready

+  *            @arg RCC_FLAG_CPURST: CPU reset flag

+  *            @arg RCC_FLAG_D1RST:  D1 domain power switch reset flag (*)

+  *            @arg RCC_FLAG_D2RST:  D2 domain power switch reset flag (*)

+  *            @arg RCC_FLAG_CDRST:  CD domain power switch reset flag (*)

+  *            @arg RCC_FLAG_BORRST: BOR reset flag

+  *            @arg RCC_FLAG_PINRST: Pin reset

+  *            @arg RCC_FLAG_PORRST: POR/PDR  reset

+  *            @arg RCC_FLAG_SFTRST: System reset from CPU reset flag

+  *            @arg RCC_FLAG_BORRST:   D2 domain power switch reset flag

+  *            @arg RCC_FLAG_IWDG1RST: CPU Independent Watchdog reset

+  *            @arg RCC_FLAG_WWDG1RST: Window Watchdog1 reset

+  *            @arg RCC_FLAG_LPWR1RST: Reset due to illegal D1 DSTANDBY or CPU CSTOP flag

+  *            @arg RCC_FLAG_LPWR2RST: Reset due to illegal D2 DSTANDBY flag

+  * @retval The new state of __FLAG__ (TRUE or FALSE).

+  *

+  *  (*) Available on some STM32H7 lines only.

+  */

+#define RCC_FLAG_MASK  ((uint8_t)0x1F)

+#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5U) == 1U)? RCC->CR :((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \

+((((__FLAG__) >> 5U) == 3U)? RCC->CSR : ((((__FLAG__) >> 5U) == 4U)? RCC->RSR :RCC->CIFR))))  & (1UL << ((__FLAG__) & RCC_FLAG_MASK)))!= 0U)? 1U : 0U)

+#endif /*DUAL_CORE*/

+

+/**

+  * @}

+  */

+

+#define RCC_GET_PLL_OSCSOURCE() ((RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC) >> RCC_PLLCKSELR_PLLSRC_Pos)

+

+/**

+  * @}

+  */

+

+/* Include RCC HAL Extension module */

+#include "stm32h7xx_hal_rcc_ex.h"

+

+/* Exported functions --------------------------------------------------------*/

+ /** @addtogroup RCC_Exported_Functions

+  * @{

+  */

+

+/** @addtogroup RCC_Exported_Functions_Group1

+  * @{

+  */

+/* Initialization and de-initialization functions  ******************************/

+HAL_StatusTypeDef HAL_RCC_DeInit(void);

+HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);

+HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);

+

+/**

+  * @}

+  */

+

+/** @addtogroup RCC_Exported_Functions_Group2

+  * @{

+  */

+/* Peripheral Control functions  ************************************************/

+void     HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);

+void     HAL_RCC_EnableCSS(void);

+void     HAL_RCC_DisableCSS(void);

+uint32_t HAL_RCC_GetSysClockFreq(void);

+uint32_t HAL_RCC_GetHCLKFreq(void);

+uint32_t HAL_RCC_GetPCLK1Freq(void);

+uint32_t HAL_RCC_GetPCLK2Freq(void);

+void     HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);

+void     HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);

+/* CSS NMI IRQ handler */

+void     HAL_RCC_NMI_IRQHandler(void);

+/* User Callbacks in non blocking mode (IT mode) */

+void     HAL_RCC_CCSCallback(void);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup RCC_Private_Constants RCC Private Constants

+  * @{

+  */

+

+#define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT

+#define HSI_TIMEOUT_VALUE          (2U)    /* 2 ms */

+#define HSI48_TIMEOUT_VALUE        (2U)    /* 2 ms */

+#define CSI_TIMEOUT_VALUE          (2U)    /* 2 ms */

+#define LSI_TIMEOUT_VALUE          (2U)    /* 2 ms */

+#define PLL_TIMEOUT_VALUE          (2U)    /* 2 ms */

+#define CLOCKSWITCH_TIMEOUT_VALUE  (5000U) /* 5 s  */

+#define RCC_DBP_TIMEOUT_VALUE      (100U)

+#define RCC_LSE_TIMEOUT_VALUE      LSE_STARTUP_TIMEOUT

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @addtogroup RCC_Private_Macros RCC Private Macros

+  * @{

+  */

+

+/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters

+  * @{

+  */

+

+#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE)                           || \

+                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \

+                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \

+                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_CSI) == RCC_OSCILLATORTYPE_CSI) || \

+                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \

+                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \

+                                           (((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))

+

+#if defined(RCC_CR_HSEEXT)

+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \

+                         ((HSE) == RCC_HSE_BYPASS) || ((HSE) == RCC_HSE_BYPASS_DIGITAL))

+#else

+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \

+                         ((HSE) == RCC_HSE_BYPASS))

+#endif /* RCC_CR_HSEEXT */

+

+#if defined(RCC_BDCR_LSEEXT)

+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \

+                         ((LSE) == RCC_LSE_BYPASS) || ((LSE) == RCC_LSE_BYPASS_DIGITAL))

+#else

+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \

+                         ((LSE) == RCC_LSE_BYPASS))

+#endif /* RCC_BDCR_LSEEXT */

+

+#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON)    || \

+                         ((HSI) == RCC_HSI_DIV1) || ((HSI) == RCC_HSI_DIV2) || \

+                         ((HSI) == RCC_HSI_DIV4) || ((HSI) == RCC_HSI_DIV8))

+

+#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))

+

+#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))

+

+#define IS_RCC_CSI(CSI) (((CSI) == RCC_CSI_OFF) || ((CSI) == RCC_CSI_ON))

+

+#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \

+                         ((PLL) == RCC_PLL_ON))

+

+#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_CSI)  || \

+                                  ((SOURCE) == RCC_PLLSOURCE_HSI)  || \

+                                  ((SOURCE) == RCC_PLLSOURCE_NONE) || \

+                                  ((SOURCE) == RCC_PLLSOURCE_HSE))

+#define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))

+#if !defined(RCC_VER_2_0)

+#define IS_RCC_PLLN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))

+#else

+#define IS_RCC_PLLN_VALUE(VALUE) ((8U <= (VALUE)) && ((VALUE) <= 420U))

+#endif /* !RCC_VER_2_0 */

+#define IS_RCC_PLLP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))

+#define IS_RCC_PLLQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))

+#define IS_RCC_PLLR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))

+

+#define IS_RCC_PLLCLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || \

+                                         ((VALUE) == RCC_PLL1_DIVQ) || \

+                                         ((VALUE) == RCC_PLL1_DIVR))

+

+#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x3FU))

+

+#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_CSI) || \

+                                     ((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \

+                                     ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \

+                                     ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))

+

+#define IS_RCC_SYSCLK(SYSCLK) (((SYSCLK) == RCC_SYSCLK_DIV1)   || ((SYSCLK) == RCC_SYSCLK_DIV2)   || \

+                               ((SYSCLK) == RCC_SYSCLK_DIV4)   || ((SYSCLK) == RCC_SYSCLK_DIV8)   || \

+                               ((SYSCLK) == RCC_SYSCLK_DIV16)  || ((SYSCLK) == RCC_SYSCLK_DIV64)  || \

+                               ((SYSCLK) == RCC_SYSCLK_DIV128) || ((SYSCLK) == RCC_SYSCLK_DIV256) || \

+                               ((SYSCLK) == RCC_SYSCLK_DIV512))

+

+

+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_HCLK_DIV1)   || ((HCLK) == RCC_HCLK_DIV2)   || \

+                           ((HCLK) == RCC_HCLK_DIV4)   || ((HCLK) == RCC_HCLK_DIV8)   || \

+                           ((HCLK) == RCC_HCLK_DIV16)  || ((HCLK) == RCC_HCLK_DIV64)  || \

+                           ((HCLK) == RCC_HCLK_DIV128) || ((HCLK) == RCC_HCLK_DIV256) || \

+                           ((HCLK) == RCC_HCLK_DIV512))

+

+#define IS_RCC_CDPCLK1(CDPCLK1) (((CDPCLK1) == RCC_APB3_DIV1) || ((CDPCLK1) == RCC_APB3_DIV2) || \

+                                 ((CDPCLK1) == RCC_APB3_DIV4) || ((CDPCLK1) == RCC_APB3_DIV8) || \

+                                 ((CDPCLK1) == RCC_APB3_DIV16))

+

+#define IS_RCC_D1PCLK1 IS_RCC_CDPCLK1  /* for legacy compatibility between H7 lines */

+

+#define IS_RCC_PCLK1(PCLK1) (((PCLK1) == RCC_APB1_DIV1) || ((PCLK1) == RCC_APB1_DIV2) || \

+                             ((PCLK1) == RCC_APB1_DIV4) || ((PCLK1) == RCC_APB1_DIV8) || \

+                            ((PCLK1) == RCC_APB1_DIV16))

+

+#define IS_RCC_PCLK2(PCLK2) (((PCLK2) == RCC_APB2_DIV1) || ((PCLK2) == RCC_APB2_DIV2) || \

+                             ((PCLK2) == RCC_APB2_DIV4) || ((PCLK2) == RCC_APB2_DIV8) || \

+                             ((PCLK2) == RCC_APB2_DIV16))

+

+#define IS_RCC_SRDPCLK1(SRDPCLK1) (((SRDPCLK1) == RCC_APB4_DIV1) || ((SRDPCLK1) == RCC_APB4_DIV2) || \

+                                  ((SRDPCLK1) == RCC_APB4_DIV4)  || ((SRDPCLK1) == RCC_APB4_DIV8) || \

+                                  ((SRDPCLK1) == RCC_APB4_DIV16))

+

+#define IS_RCC_D3PCLK1 IS_RCC_SRDPCLK1 /* for legacy compatibility between H7 lines*/

+

+#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_LSE)       || ((SOURCE) == RCC_RTCCLKSOURCE_LSI)       || \

+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV2)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV3)  || \

+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV4)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV5)  || \

+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV6)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV7)  || \

+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV8)  || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV9)  || \

+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV10) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV11) || \

+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV12) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV13) || \

+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV14) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV15) || \

+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV16) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV17) || \

+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV18) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV19) || \

+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV20) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV21) || \

+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV22) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV23) || \

+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV24) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV25) || \

+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV26) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV27) || \

+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV28) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV29) || \

+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV30) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV31) || \

+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV33) || \

+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV34) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV35) || \

+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV36) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV37) || \

+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV38) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV39) || \

+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV40) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV41) || \

+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV42) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV43) || \

+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV44) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV45) || \

+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV46) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV47) || \

+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV48) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV49) || \

+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV50) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV51) || \

+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV52) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV53) || \

+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV54) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV55) || \

+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV56) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV57) || \

+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV58) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV59) || \

+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV60) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV61) || \

+                                     ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV62) || ((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV63))

+

+#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))

+

+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE)       || \

+                                   ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLL1QCLK)  || \

+                                   ((SOURCE) == RCC_MCO1SOURCE_HSI48))

+

+#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK)    || ((SOURCE) == RCC_MCO2SOURCE_PLL2PCLK) || \

+                                   ((SOURCE) == RCC_MCO2SOURCE_HSE)       || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK)   || \

+                                   ((SOURCE) == RCC_MCO2SOURCE_CSICLK)    || ((SOURCE) == RCC_MCO2SOURCE_LSICLK))

+

+#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1)  || ((DIV) == RCC_MCODIV_2)   || \

+                            ((DIV) == RCC_MCODIV_3)  || ((DIV) == RCC_MCODIV_4)   || \

+                            ((DIV) == RCC_MCODIV_5)  || ((DIV) == RCC_MCODIV_6)   || \

+                            ((DIV) == RCC_MCODIV_7)  || ((DIV) == RCC_MCODIV_8)   || \

+                            ((DIV) == RCC_MCODIV_9)  || ((DIV) == RCC_MCODIV_10)  || \

+                            ((DIV) == RCC_MCODIV_11) || ((DIV) == RCC_MCODIV_12)  || \

+                            ((DIV) == RCC_MCODIV_13) || ((DIV) == RCC_MCODIV_14)  || \

+                            ((DIV) == RCC_MCODIV_15))

+

+#if defined(DUAL_CORE)

+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY)    || ((FLAG) == RCC_FLAG_CSIRDY)  || \

+                           ((FLAG) == RCC_FLAG_HSI48RDY)  || ((FLAG) == RCC_FLAG_HSERDY)  || \

+                           ((FLAG) == RCC_FLAG_D1CKRDY)   || ((FLAG) == RCC_FLAG_D2CKRDY) || \

+                           ((FLAG) == RCC_FLAG_PLLRDY)    || ((FLAG) == RCC_FLAG_PLL2RDY) || \

+                           ((FLAG) == RCC_FLAG_PLL3RDY)   || ((FLAG) == RCC_FLAG_LSERDY)  || \

+                           ((FLAG) == RCC_FLAG_LSIRDY)    || \

+                           ((FLAG) == RCC_FLAG_C1RST)     || ((FLAG) == RCC_FLAG_C2RST)   || \

+                           ((FLAG) == RCC_FLAG_SFTR2ST)   || ((FLAG) == RCC_FLAG_WWDG2RST)|| \

+                           ((FLAG) == RCC_FLAG_IWDG2RST)  || ((FLAG) == RCC_FLAG_D1RST)   || \

+                           ((FLAG) == RCC_FLAG_D2RST)     || ((FLAG) == RCC_FLAG_BORRST)  || \

+                           ((FLAG) == RCC_FLAG_PINRST)    || ((FLAG) == RCC_FLAG_PORRST)  || \

+                           ((FLAG) == RCC_FLAG_SFTR1ST)   || ((FLAG) == RCC_FLAG_IWDG1RST)|| \

+                           ((FLAG) == RCC_FLAG_WWDG1RST)  || ((FLAG) == RCC_FLAG_LPWR1RST)|| \

+                           ((FLAG) == RCC_FLAG_LPWR2RST)  || ((FLAG) == RCC_FLAG_HSIDIV))

+

+#else

+

+#if defined(RCC_CR_D2CKRDY)

+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY)    || ((FLAG) == RCC_FLAG_CSIRDY)  || \

+                           ((FLAG) == RCC_FLAG_HSI48RDY)  || ((FLAG) == RCC_FLAG_HSERDY)  || \

+                           ((FLAG) == RCC_FLAG_D1CKRDY)   || ((FLAG) == RCC_FLAG_D2CKRDY) || \

+                           ((FLAG) == RCC_FLAG_PLLRDY)    || ((FLAG) == RCC_FLAG_PLL2RDY) || \

+                           ((FLAG) == RCC_FLAG_PLL3RDY)   || ((FLAG) == RCC_FLAG_LSERDY)  || \

+                           ((FLAG) == RCC_FLAG_LSIRDY)    || \

+                           ((FLAG) == RCC_FLAG_CPURST)    || ((FLAG) == RCC_FLAG_D1RST)   || \

+                           ((FLAG) == RCC_FLAG_D2RST)     || ((FLAG) == RCC_FLAG_BORRST)  || \

+                           ((FLAG) == RCC_FLAG_PINRST)    || ((FLAG) == RCC_FLAG_PORRST)  || \

+                           ((FLAG) == RCC_FLAG_SFTRST)    || ((FLAG) == RCC_FLAG_IWDG1RST)|| \

+                           ((FLAG) == RCC_FLAG_WWDG1RST)  || ((FLAG) == RCC_FLAG_LPWR1RST)|| \

+                           ((FLAG) == RCC_FLAG_LPWR2RST)  || ((FLAG) == RCC_FLAG_HSIDIV ))

+#else

+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY)    || ((FLAG) == RCC_FLAG_CSIRDY)  || \

+                           ((FLAG) == RCC_FLAG_HSI48RDY)  || ((FLAG) == RCC_FLAG_HSERDY)  || \

+                           ((FLAG) == RCC_FLAG_CPUCKRDY)  || ((FLAG) == RCC_FLAG_CDCKRDY) || \

+                           ((FLAG) == RCC_FLAG_PLLRDY)    || ((FLAG) == RCC_FLAG_PLL2RDY) || \

+                           ((FLAG) == RCC_FLAG_PLL3RDY)   || ((FLAG) == RCC_FLAG_LSERDY)  || \

+                           ((FLAG) == RCC_FLAG_LSIRDY)    || \

+                           ((FLAG) == RCC_FLAG_CDRST)     || ((FLAG) == RCC_FLAG_BORRST)  || \

+                           ((FLAG) == RCC_FLAG_PINRST)    || ((FLAG) == RCC_FLAG_PORRST)  || \

+                           ((FLAG) == RCC_FLAG_SFTRST)    || ((FLAG) == RCC_FLAG_IWDG1RST)|| \

+                           ((FLAG) == RCC_FLAG_WWDG1RST)  || ((FLAG) == RCC_FLAG_LPWR1RST)|| \

+                           ((FLAG) == RCC_FLAG_LPWR2RST)  || ((FLAG) == RCC_FLAG_HSIDIV ))

+#endif /* RCC_CR_D2CKRDY */

+

+#endif /*DUAL_CORE*/

+

+#define IS_RCC_HSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x7FU)

+#define IS_RCC_CSICALIBRATION_VALUE(VALUE) ((VALUE) <= 0x3FU)

+

+#define IS_RCC_STOP_WAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_WAKEUPCLOCK_CSI) || \

+                                         ((SOURCE) == RCC_STOP_WAKEUPCLOCK_HSI))

+

+#define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_CSI) || \

+                                          ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI))

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_RCC_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_rcc_ex.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_rcc_ex.h
new file mode 100644
index 0000000000..42beccc86a
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_rcc_ex.h
@@ -0,0 +1,4262 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_rcc_ex.h

+  * @author  MCD Application Team

+  * @brief   Header file of RCC HAL Extension module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_RCC_EX_H

+#define STM32H7xx_HAL_RCC_EX_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup RCCEx

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup RCCEx_Exported_Types RCCEx Exported Types

+  * @{

+  */

+

+/**

+  * @brief  PLL2 Clock structure definition

+  */

+typedef struct

+{

+

+  uint32_t PLL2M;       /*!< PLL2M: Division factor for PLL2 VCO input clock.

+                             This parameter must be a number between Min_Data = 1 and Max_Data = 63    */

+

+  uint32_t PLL2N;       /*!< PLL2N: Multiplication factor for PLL2 VCO output clock.

+                             This parameter must be a number between Min_Data = 4 and Max_Data = 512

+                             or between Min_Data = 8 and Max_Data = 420(*)

+                             (*) : For stm32h7a3xx and stm32h7b3xx family lines.                       */   

+

+  uint32_t PLL2P;       /*!< PLL2P: Division factor for system clock.

+                             This parameter must be a number between Min_Data = 2 and Max_Data = 128

+                             odd division factors are not allowed                                      */

+

+  uint32_t PLL2Q;        /*!< PLL2Q: Division factor for peripheral clocks.

+                             This parameter must be a number between Min_Data = 1 and Max_Data = 128   */

+

+  uint32_t PLL2R;        /*!< PLL2R: Division factor for peripheral clocks.

+                             This parameter must be a number between Min_Data = 1 and Max_Data = 128   */

+  uint32_t PLL2RGE;      /*!<PLL2RGE: PLL2 clock Input range

+                          This parameter must be a value of @ref RCC_PLL2_VCI_Range                    */

+  uint32_t PLL2VCOSEL;   /*!<PLL2VCOSEL: PLL2 clock Output range

+                          This parameter must be a value of @ref RCC_PLL2_VCO_Range                    */

+

+  uint32_t PLL2FRACN;    /*!<PLL2FRACN: Specifies Fractional Part Of The Multiplication Factor for

+                            PLL2 VCO It should be a value between 0 and 8191                           */

+}RCC_PLL2InitTypeDef;

+

+/**

+  * @brief  PLL3 Clock structure definition

+  */

+typedef struct

+{

+

+  uint32_t PLL3M;       /*!< PLL3M: Division factor for PLL3 VCO input clock.

+                             This parameter must be a number between Min_Data = 1 and Max_Data = 63    */

+

+  uint32_t PLL3N;       /*!< PLL3N: Multiplication factor for PLL3 VCO output clock.

+                             This parameter must be a number between Min_Data = 4 and Max_Data = 512

+                             or between Min_Data = 8 and Max_Data = 420(*)

+                             (*) : For stm32h7a3xx and stm32h7b3xx family lines.                       */  

+

+  uint32_t PLL3P;       /*!< PLL3P: Division factor for system clock.

+                             This parameter must be a number between Min_Data = 2 and Max_Data = 128

+                             odd division factors are not allowed                                      */

+

+  uint32_t PLL3Q;        /*!< PLL3Q: Division factor for peripheral clocks.

+                             This parameter must be a number between Min_Data = 1 and Max_Data = 128   */

+

+  uint32_t PLL3R;        /*!< PLL3R: Division factor for peripheral clocks.

+                             This parameter must be a number between Min_Data = 1 and Max_Data = 128   */

+  uint32_t PLL3RGE;      /*!<PLL3RGE: PLL3 clock Input range

+                          This parameter must be a value of @ref RCC_PLL3_VCI_Range                    */

+  uint32_t PLL3VCOSEL;   /*!<PLL3VCOSEL: PLL3 clock Output range

+                          This parameter must be a value of @ref RCC_PLL3_VCO_Range                    */

+

+  uint32_t PLL3FRACN;    /*!<PLL3FRACN: Specifies Fractional Part Of The Multiplication Factor for

+                            PLL3 VCO It should be a value between 0 and 8191                           */

+}RCC_PLL3InitTypeDef;

+

+/**

+  * @brief  RCC PLL1 Clocks structure definition

+  */

+typedef struct

+{

+  uint32_t PLL1_P_Frequency;

+  uint32_t PLL1_Q_Frequency;

+  uint32_t PLL1_R_Frequency;

+}PLL1_ClocksTypeDef;

+

+/**

+  * @brief  RCC PLL2 Clocks structure definition

+  */

+typedef struct

+{

+  uint32_t PLL2_P_Frequency;

+  uint32_t PLL2_Q_Frequency;

+  uint32_t PLL2_R_Frequency;

+}PLL2_ClocksTypeDef;

+

+/**

+  * @brief  RCC PLL3 Clocks structure definition

+  */

+typedef struct

+{

+  uint32_t PLL3_P_Frequency;

+  uint32_t PLL3_Q_Frequency;

+  uint32_t PLL3_R_Frequency;

+}PLL3_ClocksTypeDef;

+

+

+/**

+  * @brief  RCC extended clocks structure definition

+  */

+typedef struct

+{

+  uint32_t PeriphClockSelection;   /*!< The Extended Clock to be configured.

+                                        This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */

+

+  RCC_PLL2InitTypeDef PLL2;        /*!< PLL2structure parameters.

+                                        This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals */

+

+  RCC_PLL3InitTypeDef PLL3;        /*!< PLL3 structure parameters.

+                                        This parameter will be used only when PLL2 is selected as kernel clock Source for some peripherals */

+

+  uint32_t FmcClockSelection;     /*!< Specifies FMC clock source

+                                        This parameter can be a value of @ref RCCEx_FMC_Clock_Source     */

+

+#if defined(QUADSPI)

+  uint32_t QspiClockSelection;    /*!< Specifies QSPI clock source

+                                        This parameter can be a value of @ref RCCEx_QSPI_Clock_Source    */

+#endif /* QUADSPI */

+

+#if defined(OCTOSPI1) || defined(OCTOSPI2)

+  uint32_t OspiClockSelection;    /*!< Specifies OSPI clock source

+                                        This parameter can be a value of @ref RCCEx_OSPI_Clock_Source    */

+#endif /*(OCTOSPI1) || (OCTOSPI2)*/

+

+

+#if defined(DSI)

+  uint32_t DsiClockSelection;     /*!< Specifies DSI clock source

+                                     This parameter can be a value of @ref RCCEx_DSI_Clock_Source        */

+#endif /* DSI */

+

+  uint32_t SdmmcClockSelection;    /*!< Specifies SDMMC clock source

+                                        This parameter can be a value of @ref RCCEx_SDMMC_Clock_Source   */

+

+  uint32_t CkperClockSelection;   /*!< Specifies CKPER clock source

+                                        This parameter can be a value of @ref RCCEx_CLKP_Clock_Source   */

+

+  uint32_t Sai1ClockSelection;     /*!< Specifies SAI1 clock source

+                                        This parameter can be a value of @ref RCCEx_SAI1_Clock_Source    */

+

+#if defined(SAI3)

+  uint32_t Sai23ClockSelection;     /*!< Specifies SAI2/3 clock source

+                                         This parameter can be a value of @ref RCCEx_SAI23_Clock_Source  */

+#endif /* SAI3 */

+

+#if defined(RCC_CDCCIP1R_SAI2ASEL)

+  uint32_t Sai2AClockSelection;     /*!< Specifies SAI2A clock source

+                                        This parameter can be a value of @ref RCCEx_SAI2A_Clock_Source  */

+#endif /* RCC_CDCCIP1R_SAI2ASEL */

+

+#if defined(RCC_CDCCIP1R_SAI2BSEL)

+  uint32_t Sai2BClockSelection;     /*!< Specifies SAI2B clock source

+                                         This parameter can be a value of @ref RCCEx_SAI2B_Clock_Source    */

+#endif /* RCC_CDCCIP1R_SAI2BSEL */

+

+  uint32_t Spi123ClockSelection;     /*!< Specifies SPI1/2/3 clock source

+                                          This parameter can be a value of @ref RCCEx_SPI123_Clock_Source    */

+

+  uint32_t Spi45ClockSelection;     /*!< Specifies SPI4/5 clock source

+                                         This parameter can be a value of @ref RCCEx_SPI45_Clock_Source    */

+

+  uint32_t SpdifrxClockSelection;   /*!< Specifies SPDIFRX Clock clock source

+                                        This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */

+

+  uint32_t Dfsdm1ClockSelection;    /*!< Specifies DFSDM1 Clock clock source

+                                        This parameter can be a value of @ref RCCEx_DFSDM1_Clock_Source  */

+

+#if defined(DFSDM2_BASE)

+  uint32_t Dfsdm2ClockSelection;    /*!< Specifies DFSDM2 Clock clock source

+                                        This parameter can be a value of @ref RCCEx_DFSDM2_Clock_Source  */

+#endif /* DFSDM2_BASE */

+

+#if defined(FDCAN1) || defined(FDCAN2)

+  uint32_t FdcanClockSelection;   /*!< Specifies FDCAN Clock clock source

+                                        This parameter can be a value of @ref RCCEx_FDCAN_Clock_Source   */

+#endif /*FDCAN1 || FDCAN2*/

+

+  uint32_t Swpmi1ClockSelection;   /*!< Specifies SWPMI1 Clock clock source

+                                        This parameter can be a value of @ref RCCEx_SWPMI1_Clock_Source  */

+

+  uint32_t Usart234578ClockSelection;   /*!< Specifies USART2/3/4/5/7/8 clock source

+                                             This parameter can be a value of @ref RCCEx_USART234578_Clock_Source  */

+

+  uint32_t Usart16ClockSelection;  /*!< Specifies USART1/6 clock source

+                                        This parameter can be a value of @ref RCCEx_USART16_Clock_Source  */

+

+   uint32_t RngClockSelection;      /*!< Specifies RNG clock source

+                                        This parameter can be a value of @ref RCCEx_RNG_Clock_Source     */

+

+   uint32_t I2c123ClockSelection;   /*!< Specifies I2C1/2/3 clock source

+                                        This parameter can be a value of @ref RCCEx_I2C123_Clock_Source    */

+

+  uint32_t UsbClockSelection;      /*!< Specifies USB clock source

+                                        This parameter can be a value of @ref RCCEx_USB_Clock_Source     */

+

+  uint32_t CecClockSelection;     /*!< Specifies CEC clock source

+                                        This parameter can be a value of @ref RCCEx_CEC_Clock_Source     */

+

+  uint32_t Lptim1ClockSelection;   /*!< Specifies LPTIM1 clock source

+                                        This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source  */

+

+  uint32_t Lpuart1ClockSelection;  /*!< Specifies LPUART1 clock source

+                                        This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */

+

+  uint32_t I2c4ClockSelection;     /*!< Specifies I2C4 clock source

+                                        This parameter can be a value of @ref RCCEx_I2C4_Clock_Source    */

+

+  uint32_t Lptim2ClockSelection;   /*!< Specifies LPTIM2 clock source

+                                        This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source  */

+

+  uint32_t Lptim345ClockSelection;   /*!< Specifies LPTIM3/4/5 clock source

+                                          This parameter can be a value of @ref RCCEx_LPTIM345_Clock_Source  */

+

+  uint32_t AdcClockSelection;      /*!< Specifies ADC interface clock source

+                                        This parameter can be a value of @ref RCCEx_ADC_Clock_Source     */

+#if defined(SAI4)

+  uint32_t Sai4AClockSelection;     /*!< Specifies SAI4A clock source

+                                        This parameter can be a value of @ref RCCEx_SAI4A_Clock_Source   */

+

+  uint32_t Sai4BClockSelection;     /*!< Specifies SAI4B clock source

+                                        This parameter can be a value of @ref RCCEx_SAI4B_Clock_Source   */

+#endif /* SAI4 */

+

+  uint32_t Spi6ClockSelection;     /*!< Specifies SPI6 clock source

+                                        This parameter can be a value of @ref RCCEx_SPI6_Clock_Source    */

+

+  uint32_t RTCClockSelection;      /*!< Specifies RTC Clock clock source

+                                        This parameter can be a value of @ref RCC_RTC_Clock_Source       */

+

+#if defined(HRTIM1)

+  uint32_t Hrtim1ClockSelection;      /*!< Specifies HRTIM1 Clock clock source

+                                        This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source   */

+#endif /* HRTIM1 */

+

+  uint32_t TIMPresSelection;       /*!< Specifies TIM Clock Prescalers Selection.

+                                       This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */

+}RCC_PeriphCLKInitTypeDef;

+

+

+/**

+  * @brief RCC_CRS Init structure definition

+  */

+typedef struct

+{

+  uint32_t Prescaler;             /*!< Specifies the division factor of the SYNC signal.

+                                     This parameter can be a value of @ref RCCEx_CRS_SynchroDivider  */

+

+  uint32_t Source;                /*!< Specifies the SYNC signal source.

+                                     This parameter can be a value of @ref RCCEx_CRS_SynchroSource   */

+

+  uint32_t Polarity;              /*!< Specifies the input polarity for the SYNC signal source.

+                                     This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */

+

+  uint32_t ReloadValue;           /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.

+                                      It can be calculated in using macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)

+                                     This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/

+

+  uint32_t ErrorLimitValue;       /*!< Specifies the value to be used to evaluate the captured frequency error value.

+                                     This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */

+

+  uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.

+                                     This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */

+

+}RCC_CRSInitTypeDef;

+

+/**

+  * @brief RCC_CRS Synchronization structure definition

+  */

+typedef struct

+{

+  uint32_t ReloadValue;           /*!< Specifies the value loaded in the Counter reload value.

+                                     This parameter must be a number between 0 and 0xFFFF */

+

+  uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.

+                                     This parameter must be a number between 0 and 0x3F */

+

+  uint32_t FreqErrorCapture;      /*!< Specifies the value loaded in the .FECAP, the frequency error counter

+                                                                    value latched in the time of the last SYNC event.

+                                    This parameter must be a number between 0 and 0xFFFF */

+

+  uint32_t FreqErrorDirection;    /*!< Specifies the value loaded in the .FEDIR, the counting direction of the

+                                                                    frequency error counter latched in the time of the last SYNC event.

+                                                                    It shows whether the actual frequency is below or above the target.

+                                    This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/

+

+}RCC_CRSSynchroInfoTypeDef;

+

+/**

+  * @}

+  */

+

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup RCCEx_Exported_Constants  RCCEx Exported Constants

+  * @{

+  */

+

+/** @defgroup RCCEx_Periph_Clock_Selection  RCCEx Periph Clock Selection

+  * @{

+  */

+

+#if defined(UART9) && defined(USART10)

+#define RCC_PERIPHCLK_USART16910       (0x00000001U)

+#define RCC_PERIPHCLK_USART1           RCC_PERIPHCLK_USART16910

+#define RCC_PERIPHCLK_USART6           RCC_PERIPHCLK_USART16910

+#define RCC_PERIPHCLK_UART9            RCC_PERIPHCLK_USART16910

+#define RCC_PERIPHCLK_USART10          RCC_PERIPHCLK_USART16910

+/*alias*/

+#define RCC_PERIPHCLK_USART16          RCC_PERIPHCLK_USART16910

+#else

+#define RCC_PERIPHCLK_USART16          (0x00000001U)

+#define RCC_PERIPHCLK_USART1           RCC_PERIPHCLK_USART16

+#define RCC_PERIPHCLK_USART6           RCC_PERIPHCLK_USART16

+/* alias */

+#define RCC_PERIPHCLK_USART16910       RCC_PERIPHCLK_USART16

+#endif /* UART9 && USART10*/

+#define RCC_PERIPHCLK_USART234578      (0x00000002U)

+#define RCC_PERIPHCLK_USART2           RCC_PERIPHCLK_USART234578

+#define RCC_PERIPHCLK_USART3           RCC_PERIPHCLK_USART234578

+#define RCC_PERIPHCLK_UART4            RCC_PERIPHCLK_USART234578

+#define RCC_PERIPHCLK_UART5            RCC_PERIPHCLK_USART234578

+#define RCC_PERIPHCLK_UART7            RCC_PERIPHCLK_USART234578

+#define RCC_PERIPHCLK_UART8            RCC_PERIPHCLK_USART234578

+#define RCC_PERIPHCLK_LPUART1          (0x00000004U)

+#define RCC_PERIPHCLK_I2C123           (0x00000008U)

+#define RCC_PERIPHCLK_I2C1             RCC_PERIPHCLK_I2C123

+#define RCC_PERIPHCLK_I2C2             RCC_PERIPHCLK_I2C123

+#define RCC_PERIPHCLK_I2C3             RCC_PERIPHCLK_I2C123

+#define RCC_PERIPHCLK_I2C4             (0x00000010U)

+#define RCC_PERIPHCLK_LPTIM1           (0x00000020U)

+#define RCC_PERIPHCLK_LPTIM2           (0x00000040U)

+#define RCC_PERIPHCLK_LPTIM345         (0x00000080U)

+#define RCC_PERIPHCLK_LPTIM3           RCC_PERIPHCLK_LPTIM345

+#if defined(LPTIM4)

+#define RCC_PERIPHCLK_LPTIM4           RCC_PERIPHCLK_LPTIM345

+#endif /*LPTIM4*/

+#if defined(LPTIM5)

+#define RCC_PERIPHCLK_LPTIM5           RCC_PERIPHCLK_LPTIM345

+#endif /*LPTIM5*/

+#define RCC_PERIPHCLK_SAI1             (0x00000100U)

+#if defined(SAI3)

+#define RCC_PERIPHCLK_SAI23            (0x00000200U)

+#define RCC_PERIPHCLK_SAI2             RCC_PERIPHCLK_SAI23

+#define RCC_PERIPHCLK_SAI3             RCC_PERIPHCLK_SAI23

+#endif /* SAI3 */

+#if defined(RCC_CDCCIP1R_SAI2ASEL_0)

+#define RCC_PERIPHCLK_SAI2A            (0x00000200U)

+#endif /* RCC_CDCCIP1R_SAI2ASEL_0 */

+#if defined(RCC_CDCCIP1R_SAI2BSEL_0)

+#define RCC_PERIPHCLK_SAI2B            (0x00000400U)

+#endif /* RCC_CDCCIP1R_SAI2BSEL_0 */

+#if defined(SAI4)

+#define RCC_PERIPHCLK_SAI4A            (0x00000400U)

+#define RCC_PERIPHCLK_SAI4B            (0x00000800U)

+#endif /* SAI4 */

+#define RCC_PERIPHCLK_SPI123           (0x00001000U)

+#define RCC_PERIPHCLK_SPI1             RCC_PERIPHCLK_SPI123

+#define RCC_PERIPHCLK_SPI2             RCC_PERIPHCLK_SPI123

+#define RCC_PERIPHCLK_SPI3             RCC_PERIPHCLK_SPI123

+#define RCC_PERIPHCLK_SPI45            (0x00002000U)

+#define RCC_PERIPHCLK_SPI4             RCC_PERIPHCLK_SPI45

+#define RCC_PERIPHCLK_SPI5             RCC_PERIPHCLK_SPI45

+#define RCC_PERIPHCLK_SPI6             (0x00004000U)

+#define RCC_PERIPHCLK_FDCAN            (0x00008000U)

+#define RCC_PERIPHCLK_SDMMC            (0x00010000U)

+#define RCC_PERIPHCLK_RNG              (0x00020000U)

+#define RCC_PERIPHCLK_USB              (0x00040000U)

+#define RCC_PERIPHCLK_ADC              (0x00080000U)

+#define RCC_PERIPHCLK_SWPMI1           (0x00100000U)

+#define RCC_PERIPHCLK_DFSDM1           (0x00200000U)

+#if defined(DFSDM2_BASE)

+#define RCC_PERIPHCLK_DFSDM2           (0x00000800U)

+#endif /* DFSDM2 */

+#define RCC_PERIPHCLK_RTC              (0x00400000U)

+#define RCC_PERIPHCLK_CEC              (0x00800000U)

+#define RCC_PERIPHCLK_FMC              (0x01000000U)

+#if defined(QUADSPI)

+#define RCC_PERIPHCLK_QSPI             (0x02000000U)

+#endif /* QUADSPI */

+#if defined(OCTOSPI1) || defined(OCTOSPI2)

+#define RCC_PERIPHCLK_OSPI             (0x02000000U)

+#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */

+#define RCC_PERIPHCLK_DSI              (0x04000000U)

+#define RCC_PERIPHCLK_SPDIFRX          (0x08000000U)

+#if defined(HRTIM1)

+#define RCC_PERIPHCLK_HRTIM1           (0x10000000U)

+#endif /* HRTIM1 */

+#if defined(LTDC)

+#define RCC_PERIPHCLK_LTDC             (0x20000000U)

+#endif /* LTDC */

+#define RCC_PERIPHCLK_TIM              (0x40000000U)

+#define RCC_PERIPHCLK_CKPER            (0x80000000U)

+

+/**

+  * @}

+  */

+

+

+/** @defgroup RCC_PLL2_Clock_Output  RCC PLL2 Clock Output

+  * @{

+  */

+#define RCC_PLL2_DIVP                RCC_PLLCFGR_DIVP2EN

+#define RCC_PLL2_DIVQ                RCC_PLLCFGR_DIVQ2EN

+#define RCC_PLL2_DIVR                RCC_PLLCFGR_DIVR2EN

+

+/**

+  * @}

+  */

+

+/** @defgroup RCC_PLL3_Clock_Output  RCC PLL3 Clock Output

+  * @{

+  */

+#define RCC_PLL3_DIVP                RCC_PLLCFGR_DIVP3EN

+#define RCC_PLL3_DIVQ                RCC_PLLCFGR_DIVQ3EN

+#define RCC_PLL3_DIVR                RCC_PLLCFGR_DIVR3EN

+

+/**

+  * @}

+  */

+

+/** @defgroup RCC_PLL2_VCI_Range  RCC PLL2 VCI Range

+  * @{

+  */

+#define RCC_PLL2VCIRANGE_0                RCC_PLLCFGR_PLL2RGE_0        /*!< Clock range frequency between 1 and 2 MHz  */

+#define RCC_PLL2VCIRANGE_1                RCC_PLLCFGR_PLL2RGE_1        /*!< Clock range frequency between 2 and 4 MHz  */

+#define RCC_PLL2VCIRANGE_2                RCC_PLLCFGR_PLL2RGE_2        /*!< Clock range frequency between 4 and 8 MHz  */

+#define RCC_PLL2VCIRANGE_3                RCC_PLLCFGR_PLL2RGE_3        /*!< Clock range frequency between 8 and 16 MHz */

+

+/**

+  * @}

+  */

+

+

+/** @defgroup RCC_PLL2_VCO_Range  RCC PLL2 VCO Range

+  * @{

+  */

+#define RCC_PLL2VCOWIDE                 (0x00000000U)

+#define RCC_PLL2VCOMEDIUM               RCC_PLLCFGR_PLL2VCOSEL

+

+/**

+  * @}

+  */

+

+/** @defgroup RCC_PLL3_VCI_Range  RCC PLL3 VCI Range

+  * @{

+  */

+#define RCC_PLL3VCIRANGE_0                RCC_PLLCFGR_PLL3RGE_0         /*!< Clock range frequency between 1 and 2 MHz  */

+#define RCC_PLL3VCIRANGE_1                RCC_PLLCFGR_PLL3RGE_1         /*!< Clock range frequency between 2 and 4 MHz  */

+#define RCC_PLL3VCIRANGE_2                RCC_PLLCFGR_PLL3RGE_2         /*!< Clock range frequency between 4 and 8 MHz  */

+#define RCC_PLL3VCIRANGE_3                RCC_PLLCFGR_PLL3RGE_3         /*!< Clock range frequency between 8 and 16 MHz */

+

+/**

+  * @}

+  */

+

+

+/** @defgroup RCC_PLL3_VCO_Range  RCC PLL3 VCO Range

+  * @{

+  */

+#define RCC_PLL3VCOWIDE                 (0x00000000U)

+#define RCC_PLL3VCOMEDIUM               RCC_PLLCFGR_PLL3VCOSEL

+

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_USART16_Clock_Source  RCCEx USART1/6 Clock Source

+  * @{

+  */

+#if defined(RCC_D2CCIP2R_USART16SEL)

+#define RCC_USART16CLKSOURCE_D2PCLK2    (0x00000000U)

+/* alias */

+#define RCC_USART16CLKSOURCE_PCLK2        RCC_USART16CLKSOURCE_D2PCLK2

+#define RCC_USART16CLKSOURCE_PLL2         RCC_D2CCIP2R_USART16SEL_0

+#define RCC_USART16CLKSOURCE_PLL3         RCC_D2CCIP2R_USART16SEL_1

+#define RCC_USART16CLKSOURCE_HSI         (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)

+#define RCC_USART16CLKSOURCE_CSI          RCC_D2CCIP2R_USART16SEL_2

+#define RCC_USART16CLKSOURCE_LSE         (RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)

+

+#else

+#define RCC_USART16910CLKSOURCE_CDPCLK2   (0x00000000U)

+/* alias */

+#define RCC_USART16910CLKSOURCE_D2PCLK2   RCC_USART16910CLKSOURCE_CDPCLK2

+#define RCC_USART16910CLKSOURCE_PLL2      RCC_CDCCIP2R_USART16910SEL_0

+#define RCC_USART16910CLKSOURCE_PLL3      RCC_CDCCIP2R_USART16910SEL_1

+#define RCC_USART16910CLKSOURCE_HSI      (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1)

+#define RCC_USART16910CLKSOURCE_CSI       RCC_CDCCIP2R_USART16910SEL_2

+#define RCC_USART16910CLKSOURCE_LSE      (RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2)

+

+/*  Aliases */

+#define RCC_USART16CLKSOURCE_CDPCLK2     RCC_USART16910CLKSOURCE_CDPCLK2

+#define RCC_USART16CLKSOURCE_PCLK2       RCC_USART16CLKSOURCE_CDPCLK2

+#define RCC_USART16CLKSOURCE_D2PCLK2     RCC_USART16CLKSOURCE_CDPCLK2

+#define RCC_USART16CLKSOURCE_PLL2        RCC_USART16910CLKSOURCE_PLL2

+#define RCC_USART16CLKSOURCE_PLL3        RCC_USART16910CLKSOURCE_PLL3

+#define RCC_USART16CLKSOURCE_HSI         RCC_USART16910CLKSOURCE_HSI

+#define RCC_USART16CLKSOURCE_CSI         RCC_USART16910CLKSOURCE_CSI

+#define RCC_USART16CLKSOURCE_LSE         RCC_USART16910CLKSOURCE_LSE

+#endif /* RCC_D2CCIP2R_USART16SEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_USART1_Clock_Source  RCCEx USART1 Clock Source

+  * @{

+  */

+#define RCC_USART1CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2

+#define RCC_USART1CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2

+#define RCC_USART1CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3

+#define RCC_USART1CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI

+#define RCC_USART1CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI

+#define RCC_USART1CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_USART6_Clock_Source  RCCEx USART6 Clock Source

+  * @{

+  */

+#define RCC_USART6CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2

+#define RCC_USART6CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2

+#define RCC_USART6CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3

+#define RCC_USART6CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI

+#define RCC_USART6CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI

+#define RCC_USART6CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE

+

+/**

+  * @}

+  */

+

+#if defined(UART9)

+/** @defgroup RCCEx_UART9_Clock_Source  RCCEx UART9 Clock Source

+  * @{

+  */

+#define RCC_UART9CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2

+#define RCC_UART9CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2

+#define RCC_UART9CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3

+#define RCC_UART9CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI

+#define RCC_UART9CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI

+#define RCC_UART9CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE

+/**

+  * @}

+  */

+#endif /* UART9 */

+

+#if defined(USART10)

+/** @defgroup RCCEx_USART10_Clock_Source  RCCEx USART10 Clock Source

+  * @{

+  */

+#define RCC_USART10CLKSOURCE_D2PCLK2   RCC_USART16CLKSOURCE_D2PCLK2

+#define RCC_USART10CLKSOURCE_PLL2      RCC_USART16CLKSOURCE_PLL2

+#define RCC_USART10CLKSOURCE_PLL3      RCC_USART16CLKSOURCE_PLL3

+#define RCC_USART10CLKSOURCE_HSI       RCC_USART16CLKSOURCE_HSI

+#define RCC_USART10CLKSOURCE_CSI       RCC_USART16CLKSOURCE_CSI

+#define RCC_USART10CLKSOURCE_LSE       RCC_USART16CLKSOURCE_LSE

+/**

+  * @}

+  */

+#endif /* USART10 */

+

+/** @defgroup RCCEx_USART234578_Clock_Source  RCCEx USART2/3/4/5/7/8 Clock Source

+  * @{

+  */

+#if defined(RCC_D2CCIP2R_USART28SEL)

+#define RCC_USART234578CLKSOURCE_D2PCLK1    (0x00000000U)

+/* alias */

+#define RCC_USART234578CLKSOURCE_PCLK1      RCC_USART234578CLKSOURCE_D2PCLK1

+#define RCC_USART234578CLKSOURCE_PLL2       RCC_D2CCIP2R_USART28SEL_0

+#define RCC_USART234578CLKSOURCE_PLL3       RCC_D2CCIP2R_USART28SEL_1

+#define RCC_USART234578CLKSOURCE_HSI        (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)

+#define RCC_USART234578CLKSOURCE_CSI        RCC_D2CCIP2R_USART28SEL_2

+#define RCC_USART234578CLKSOURCE_LSE        (RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)

+#else

+#define RCC_USART234578CLKSOURCE_CDPCLK1   (0x00000000U)

+/* alias */

+#define RCC_USART234578CLKSOURCE_PCLK1     RCC_USART234578CLKSOURCE_CDPCLK1

+#define RCC_USART234578CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_CDPCLK1

+#define RCC_USART234578CLKSOURCE_PLL2      RCC_CDCCIP2R_USART234578SEL_0

+#define RCC_USART234578CLKSOURCE_PLL3      RCC_CDCCIP2R_USART234578SEL_1

+#define RCC_USART234578CLKSOURCE_HSI      (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1)

+#define RCC_USART234578CLKSOURCE_CSI       RCC_CDCCIP2R_USART234578SEL_2

+#define RCC_USART234578CLKSOURCE_LSE      (RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2)

+#endif /* RCC_D2CCIP2R_USART28SEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_USART2_Clock_Source  RCCEx USART2 Clock Source

+  * @{

+  */

+#define RCC_USART2CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1

+#define RCC_USART2CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2

+#define RCC_USART2CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3

+#define RCC_USART2CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI

+#define RCC_USART2CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI

+#define RCC_USART2CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE

+

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_USART3_Clock_Source  RCCEx USART3 Clock Source

+  * @{

+  */

+#define RCC_USART3CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1

+#define RCC_USART3CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2

+#define RCC_USART3CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3

+#define RCC_USART3CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI

+#define RCC_USART3CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI

+#define RCC_USART3CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE

+

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_UART4_Clock_Source  RCCEx UART4 Clock Source

+  * @{

+  */

+#define RCC_UART4CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1

+#define RCC_UART4CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2

+#define RCC_UART4CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3

+#define RCC_UART4CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI

+#define RCC_UART4CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI

+#define RCC_UART4CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE

+

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_UART5_Clock_Source  RCCEx UART5 Clock Source

+  * @{

+  */

+#define RCC_UART5CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1

+#define RCC_UART5CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2

+#define RCC_UART5CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3

+#define RCC_UART5CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI

+#define RCC_UART5CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI

+#define RCC_UART5CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE

+

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_UART7_Clock_Source  RCCEx UART7 Clock Source

+  * @{

+  */

+#define RCC_UART7CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1

+#define RCC_UART7CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2

+#define RCC_UART7CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3

+#define RCC_UART7CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI

+#define RCC_UART7CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI

+#define RCC_UART7CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE

+

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_UART8_Clock_Source  RCCEx UART8 Clock Source

+  * @{

+  */

+#define RCC_UART8CLKSOURCE_D2PCLK1   RCC_USART234578CLKSOURCE_D2PCLK1

+#define RCC_UART8CLKSOURCE_PLL2      RCC_USART234578CLKSOURCE_PLL2

+#define RCC_UART8CLKSOURCE_PLL3      RCC_USART234578CLKSOURCE_PLL3

+#define RCC_UART8CLKSOURCE_HSI       RCC_USART234578CLKSOURCE_HSI

+#define RCC_UART8CLKSOURCE_CSI       RCC_USART234578CLKSOURCE_CSI

+#define RCC_UART8CLKSOURCE_LSE       RCC_USART234578CLKSOURCE_LSE

+

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_LPUART1_Clock_Source  RCCEx LPUART1 Clock Source

+  * @{

+  */

+#if defined(RCC_D3CCIPR_LPUART1SEL)

+#define RCC_LPUART1CLKSOURCE_D3PCLK1    (0x00000000U)

+/* alias */

+#define RCC_LPUART1CLKSOURCE_PCLK4     RCC_LPUART1CLKSOURCE_D3PCLK1

+#define RCC_LPUART1CLKSOURCE_PLL2      RCC_D3CCIPR_LPUART1SEL_0

+#define RCC_LPUART1CLKSOURCE_PLL3      RCC_D3CCIPR_LPUART1SEL_1

+#define RCC_LPUART1CLKSOURCE_HSI       (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1)

+#define RCC_LPUART1CLKSOURCE_CSI        RCC_D3CCIPR_LPUART1SEL_2

+#define RCC_LPUART1CLKSOURCE_LSE       (RCC_D3CCIPR_LPUART1SEL_2 | RCC_D3CCIPR_LPUART1SEL_0)

+#else

+#define RCC_LPUART1CLKSOURCE_SRDPCLK4   (0x00000000U)

+/* alias*/

+#define RCC_LPUART1CLKSOURCE_PCLK4     RCC_LPUART1CLKSOURCE_SRDPCLK4

+#define RCC_LPUART1CLKSOURCE_D3PCLK1   RCC_LPUART1CLKSOURCE_SRDPCLK4

+#define RCC_LPUART1CLKSOURCE_PLL2      RCC_SRDCCIPR_LPUART1SEL_0

+#define RCC_LPUART1CLKSOURCE_PLL3      RCC_SRDCCIPR_LPUART1SEL_1

+#define RCC_LPUART1CLKSOURCE_HSI       (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1)

+#define RCC_LPUART1CLKSOURCE_CSI        RCC_SRDCCIPR_LPUART1SEL_2

+#define RCC_LPUART1CLKSOURCE_LSE       (RCC_SRDCCIPR_LPUART1SEL_2 | RCC_SRDCCIPR_LPUART1SEL_0)

+#endif /* RCC_D3CCIPR_LPUART1SEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_I2C123_Clock_Source  RCCEx I2C1/2/3 Clock Source

+  * @{

+  */

+#if defined (RCC_D2CCIP2R_I2C123SEL)

+#define RCC_I2C123CLKSOURCE_D2PCLK1      (0x00000000U)

+#define RCC_I2C123CLKSOURCE_PLL3         RCC_D2CCIP2R_I2C123SEL_0

+#define RCC_I2C123CLKSOURCE_HSI          RCC_D2CCIP2R_I2C123SEL_1

+#define RCC_I2C123CLKSOURCE_CSI         (RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)

+#else

+#define RCC_I2C123CLKSOURCE_CDPCLK1      (0x00000000U)

+/* alias */

+#define RCC_I2C123CLKSOURCE_D2PCLK1      RCC_I2C123CLKSOURCE_CDPCLK1

+#define RCC_I2C123CLKSOURCE_PLL3         RCC_CDCCIP2R_I2C123SEL_0

+#define RCC_I2C123CLKSOURCE_HSI          RCC_CDCCIP2R_I2C123SEL_1

+#define RCC_I2C123CLKSOURCE_CSI         (RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1)

+#endif /* RCC_D2CCIP2R_I2C123SEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_I2C1_Clock_Source  RCCEx I2C1 Clock Source

+  * @{

+  */

+#define RCC_I2C1CLKSOURCE_D2PCLK1     RCC_I2C123CLKSOURCE_D2PCLK1

+#define RCC_I2C1CLKSOURCE_PLL3        RCC_I2C123CLKSOURCE_PLL3

+#define RCC_I2C1CLKSOURCE_HSI         RCC_I2C123CLKSOURCE_HSI

+#define RCC_I2C1CLKSOURCE_CSI         RCC_I2C123CLKSOURCE_CSI

+

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_I2C2_Clock_Source  RCCEx I2C2 Clock Source

+  * @{

+  */

+#define RCC_I2C2CLKSOURCE_D2PCLK1     RCC_I2C123CLKSOURCE_D2PCLK1

+#define RCC_I2C2CLKSOURCE_PLL3        RCC_I2C123CLKSOURCE_PLL3

+#define RCC_I2C2CLKSOURCE_HSI         RCC_I2C123CLKSOURCE_HSI

+#define RCC_I2C2CLKSOURCE_CSI         RCC_I2C123CLKSOURCE_CSI

+

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_I2C3_Clock_Source  RCCEx I2C3 Clock Source

+  * @{

+  */

+#define RCC_I2C3CLKSOURCE_D2PCLK1     RCC_I2C123CLKSOURCE_D2PCLK1

+#define RCC_I2C3CLKSOURCE_PLL3        RCC_I2C123CLKSOURCE_PLL3

+#define RCC_I2C3CLKSOURCE_HSI         RCC_I2C123CLKSOURCE_HSI

+#define RCC_I2C3CLKSOURCE_CSI         RCC_I2C123CLKSOURCE_CSI

+

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_I2C4_Clock_Source  RCCEx I2C4 Clock Source

+  * @{

+  */

+#if defined(RCC_D3CCIPR_I2C4SEL)

+#define RCC_I2C4CLKSOURCE_D3PCLK1      (0x00000000U)

+#define RCC_I2C4CLKSOURCE_PLL3         RCC_D3CCIPR_I2C4SEL_0

+#define RCC_I2C4CLKSOURCE_HSI          RCC_D3CCIPR_I2C4SEL_1

+#define RCC_I2C4CLKSOURCE_CSI         (RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1)

+#else

+#define RCC_I2C4CLKSOURCE_SRDPCLK4     (0x00000000U)

+/* alias */

+#define RCC_I2C4CLKSOURCE_D3PCLK1     RCC_I2C4CLKSOURCE_SRDPCLK4

+#define RCC_I2C4CLKSOURCE_PLL3         RCC_SRDCCIPR_I2C4SEL_0

+#define RCC_I2C4CLKSOURCE_HSI          RCC_SRDCCIPR_I2C4SEL_1

+#define RCC_I2C4CLKSOURCE_CSI         (RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1)

+#endif /* RCC_D3CCIPR_I2C4SEL */

+

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_RNG_Clock_Source  RCCEx RNG Clock Source

+  * @{

+  */

+#if defined(RCC_D2CCIP2R_RNGSEL)

+#define RCC_RNGCLKSOURCE_HSI48        (0x00000000U)

+#define RCC_RNGCLKSOURCE_PLL           RCC_D2CCIP2R_RNGSEL_0

+#define RCC_RNGCLKSOURCE_LSE           RCC_D2CCIP2R_RNGSEL_1

+#define RCC_RNGCLKSOURCE_LSI           RCC_D2CCIP2R_RNGSEL

+#else

+#define RCC_RNGCLKSOURCE_HSI48        (0x00000000U)

+#define RCC_RNGCLKSOURCE_PLL           RCC_CDCCIP2R_RNGSEL_0

+#define RCC_RNGCLKSOURCE_LSE           RCC_CDCCIP2R_RNGSEL_1

+#define RCC_RNGCLKSOURCE_LSI           RCC_CDCCIP2R_RNGSEL

+#endif /* RCC_D2CCIP2R_RNGSEL */

+

+/**

+  * @}

+  */

+#if defined(HRTIM1)

+

+/** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source

+  * @{

+  */

+#define RCC_HRTIM1CLK_TIMCLK                (0x00000000U)

+#define RCC_HRTIM1CLK_CPUCLK                RCC_CFGR_HRTIMSEL

+

+/**

+  * @}

+  */

+#endif /*HRTIM1*/

+

+/** @defgroup RCCEx_USB_Clock_Source  RCCEx USB Clock Source

+  * @{

+  */

+#if defined(RCC_D2CCIP2R_USBSEL)

+#define RCC_USBCLKSOURCE_PLL                  RCC_D2CCIP2R_USBSEL_0

+#define RCC_USBCLKSOURCE_PLL3                 RCC_D2CCIP2R_USBSEL_1

+#define RCC_USBCLKSOURCE_HSI48                RCC_D2CCIP2R_USBSEL

+#else

+#define RCC_USBCLKSOURCE_PLL                  RCC_CDCCIP2R_USBSEL_0

+#define RCC_USBCLKSOURCE_PLL3                 RCC_CDCCIP2R_USBSEL_1

+#define RCC_USBCLKSOURCE_HSI48                RCC_CDCCIP2R_USBSEL

+#endif /* RCC_D2CCIP2R_USBSEL */

+

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source

+  * @{

+  */

+#if defined(RCC_D2CCIP1R_SAI1SEL)

+#define RCC_SAI1CLKSOURCE_PLL         (0x00000000U)

+#define RCC_SAI1CLKSOURCE_PLL2         RCC_D2CCIP1R_SAI1SEL_0

+#define RCC_SAI1CLKSOURCE_PLL3         RCC_D2CCIP1R_SAI1SEL_1

+#define RCC_SAI1CLKSOURCE_PIN         (RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1)

+#define RCC_SAI1CLKSOURCE_CLKP         RCC_D2CCIP1R_SAI1SEL_2

+#else

+#define RCC_SAI1CLKSOURCE_PLL         (0x00000000U)

+#define RCC_SAI1CLKSOURCE_PLL2         RCC_CDCCIP1R_SAI1SEL_0

+#define RCC_SAI1CLKSOURCE_PLL3         RCC_CDCCIP1R_SAI1SEL_1

+#define RCC_SAI1CLKSOURCE_PIN         (RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1)

+#define RCC_SAI1CLKSOURCE_CLKP         RCC_CDCCIP1R_SAI1SEL_2

+#endif /* RCC_D2CCIP1R_SAI1SEL */

+/**

+  * @}

+  */

+

+#if defined(SAI3)

+/** @defgroup RCCEx_SAI23_Clock_Source SAI2/3 Clock Source

+  * @{

+  */

+#define RCC_SAI23CLKSOURCE_PLL         (0x00000000U)

+#define RCC_SAI23CLKSOURCE_PLL2         RCC_D2CCIP1R_SAI23SEL_0

+#define RCC_SAI23CLKSOURCE_PLL3         RCC_D2CCIP1R_SAI23SEL_1

+#define RCC_SAI23CLKSOURCE_PIN         (RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1)

+#define RCC_SAI23CLKSOURCE_CLKP         RCC_D2CCIP1R_SAI23SEL_2

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source

+  * @{

+  */

+#define RCC_SAI2CLKSOURCE_PLL         RCC_SAI23CLKSOURCE_PLL

+#define RCC_SAI2CLKSOURCE_PLL2        RCC_SAI23CLKSOURCE_PLL2

+#define RCC_SAI2CLKSOURCE_PLL3        RCC_SAI23CLKSOURCE_PLL3

+#define RCC_SAI2CLKSOURCE_PIN         RCC_SAI23CLKSOURCE_PIN

+#define RCC_SAI2CLKSOURCE_CLKP        RCC_SAI23CLKSOURCE_CLKP

+

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_SAI3_Clock_Source SAI3 Clock Source

+  * @{

+  */

+#define RCC_SAI3CLKSOURCE_PLL         RCC_SAI23CLKSOURCE_PLL

+#define RCC_SAI3CLKSOURCE_PLL2        RCC_SAI23CLKSOURCE_PLL2

+#define RCC_SAI3CLKSOURCE_PLL3        RCC_SAI23CLKSOURCE_PLL3

+#define RCC_SAI3CLKSOURCE_PIN         RCC_SAI23CLKSOURCE_PIN

+#define RCC_SAI3CLKSOURCE_CLKP        RCC_SAI23CLKSOURCE_CLKP

+/**

+  * @}

+  */

+#endif /* SAI3 */

+

+#if defined(RCC_CDCCIP1R_SAI2ASEL)

+/** @defgroup RCCEx_SAI2_Clock_A Source SAI2A Clock Source

+  * @{

+  */

+#define RCC_SAI2ACLKSOURCE_PLL         (0x00000000U)

+#define RCC_SAI2ACLKSOURCE_PLL2         RCC_CDCCIP1R_SAI2ASEL_0

+#define RCC_SAI2ACLKSOURCE_PLL3         RCC_CDCCIP1R_SAI2ASEL_1

+#define RCC_SAI2ACLKSOURCE_PIN         (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1)

+#define RCC_SAI2ACLKSOURCE_CLKP         RCC_CDCCIP1R_SAI2ASEL_2

+#define RCC_SAI2ACLKSOURCE_SPDIF       (RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2)

+ /**

+  * @}

+  */

+#endif /* RCC_CDCCIP1R_SAI2ASEL */

+

+#if defined(RCC_CDCCIP1R_SAI2BSEL)

+/** @defgroup RCCEx_SAI2_Block_B Clock_Source SAI2B Clock Source

+  * @{

+  */

+#define RCC_SAI2BCLKSOURCE_PLL         (0x00000000U)

+#define RCC_SAI2BCLKSOURCE_PLL2         RCC_CDCCIP1R_SAI2BSEL_0

+#define RCC_SAI2BCLKSOURCE_PLL3         RCC_CDCCIP1R_SAI2BSEL_1

+#define RCC_SAI2BCLKSOURCE_PIN         (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1)

+#define RCC_SAI2BCLKSOURCE_CLKP         RCC_CDCCIP1R_SAI2BSEL_2

+#define RCC_SAI2BCLKSOURCE_SPDIF       (RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2)

+/**

+  * @}

+  */

+#endif /* RCC_CDCCIP1R_SAI2BSEL */

+

+

+/** @defgroup RCCEx_SPI123_Clock_Source SPI1/2/3 Clock Source

+  * @{

+  */

+#if defined(RCC_D2CCIP1R_SPI123SEL)

+#define RCC_SPI123CLKSOURCE_PLL         (0x00000000U)

+#define RCC_SPI123CLKSOURCE_PLL2         RCC_D2CCIP1R_SPI123SEL_0

+#define RCC_SPI123CLKSOURCE_PLL3         RCC_D2CCIP1R_SPI123SEL_1

+#define RCC_SPI123CLKSOURCE_PIN         (RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)

+#define RCC_SPI123CLKSOURCE_CLKP         RCC_D2CCIP1R_SPI123SEL_2

+#else

+#define RCC_SPI123CLKSOURCE_PLL         (0x00000000U)

+#define RCC_SPI123CLKSOURCE_PLL2         RCC_CDCCIP1R_SPI123SEL_0

+#define RCC_SPI123CLKSOURCE_PLL3         RCC_CDCCIP1R_SPI123SEL_1

+#define RCC_SPI123CLKSOURCE_PIN         (RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1)

+#define RCC_SPI123CLKSOURCE_CLKP         RCC_CDCCIP1R_SPI123SEL_2

+#endif /* RCC_D2CCIP1R_SPI123SEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_SPI1_Clock_Source SPI1 Clock Source

+  * @{

+  */

+#define RCC_SPI1CLKSOURCE_PLL         RCC_SPI123CLKSOURCE_PLL

+#define RCC_SPI1CLKSOURCE_PLL2        RCC_SPI123CLKSOURCE_PLL2

+#define RCC_SPI1CLKSOURCE_PLL3        RCC_SPI123CLKSOURCE_PLL3

+#define RCC_SPI1CLKSOURCE_PIN         RCC_SPI123CLKSOURCE_PIN

+#define RCC_SPI1CLKSOURCE_CLKP        RCC_SPI123CLKSOURCE_CLKP

+

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_SPI2_Clock_Source SPI2 Clock Source

+  * @{

+  */

+#define RCC_SPI2CLKSOURCE_PLL         RCC_SPI123CLKSOURCE_PLL

+#define RCC_SPI2CLKSOURCE_PLL2        RCC_SPI123CLKSOURCE_PLL2

+#define RCC_SPI2CLKSOURCE_PLL3        RCC_SPI123CLKSOURCE_PLL3

+#define RCC_SPI2CLKSOURCE_PIN         RCC_SPI123CLKSOURCE_PIN

+#define RCC_SPI2CLKSOURCE_CLKP        RCC_SPI123CLKSOURCE_CLKP

+

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_SPI3_Clock_Source SPI3 Clock Source

+  * @{

+  */

+#define RCC_SPI3CLKSOURCE_PLL         RCC_SPI123CLKSOURCE_PLL

+#define RCC_SPI3CLKSOURCE_PLL2        RCC_SPI123CLKSOURCE_PLL2

+#define RCC_SPI3CLKSOURCE_PLL3        RCC_SPI123CLKSOURCE_PLL3

+#define RCC_SPI3CLKSOURCE_PIN         RCC_SPI123CLKSOURCE_PIN

+#define RCC_SPI3CLKSOURCE_CLKP        RCC_SPI123CLKSOURCE_CLKP

+

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_SPI45_Clock_Source SPI4/5 Clock Source

+  * @{

+  */

+#if defined(RCC_D2CCIP1R_SPI45SEL)

+#define RCC_SPI45CLKSOURCE_D2PCLK1     (0x00000000U)

+#define RCC_SPI45CLKSOURCE_PCLK1        RCC_SPI45CLKSOURCE_D2PCLK1

+#define RCC_SPI45CLKSOURCE_PLL2         RCC_D2CCIP1R_SPI45SEL_0

+#define RCC_SPI45CLKSOURCE_PLL3         RCC_D2CCIP1R_SPI45SEL_1

+#define RCC_SPI45CLKSOURCE_HSI         (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)

+#define RCC_SPI45CLKSOURCE_CSI          RCC_D2CCIP1R_SPI45SEL_2

+#define RCC_SPI45CLKSOURCE_HSE         (RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)

+#else

+#define RCC_SPI45CLKSOURCE_CDPCLK1     (0x00000000U)

+/* aliases */

+#define RCC_SPI45CLKSOURCE_D2PCLK1      RCC_SPI45CLKSOURCE_CDPCLK1  /* D2PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */

+#define RCC_SPI45CLKSOURCE_PCLK1        RCC_SPI45CLKSOURCE_CDPCLK1

+#define RCC_SPI45CLKSOURCE_PLL2         RCC_CDCCIP1R_SPI45SEL_0

+#define RCC_SPI45CLKSOURCE_PLL3         RCC_CDCCIP1R_SPI45SEL_1

+#define RCC_SPI45CLKSOURCE_HSI         (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1)

+#define RCC_SPI45CLKSOURCE_CSI          RCC_CDCCIP1R_SPI45SEL_2

+#define RCC_SPI45CLKSOURCE_HSE         (RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2)

+#endif /* RCC_D2CCIP1R_SPI45SEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_SPI4_Clock_Source SPI4 Clock Source

+  * @{

+  */

+#define RCC_SPI4CLKSOURCE_D2PCLK1     RCC_SPI45CLKSOURCE_D2PCLK1

+#define RCC_SPI4CLKSOURCE_PLL2        RCC_SPI45CLKSOURCE_PLL2

+#define RCC_SPI4CLKSOURCE_PLL3        RCC_SPI45CLKSOURCE_PLL3

+#define RCC_SPI4CLKSOURCE_HSI         RCC_SPI45CLKSOURCE_HSI

+#define RCC_SPI4CLKSOURCE_CSI         RCC_SPI45CLKSOURCE_CSI

+#define RCC_SPI4CLKSOURCE_HSE         RCC_SPI45CLKSOURCE_HSE

+

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_SPI5_Clock_Source SPI5 Clock Source

+  * @{

+  */

+#define RCC_SPI5CLKSOURCE_D2PCLK1     RCC_SPI45CLKSOURCE_D2PCLK1

+#define RCC_SPI5CLKSOURCE_PLL2        RCC_SPI45CLKSOURCE_PLL2

+#define RCC_SPI5CLKSOURCE_PLL3        RCC_SPI45CLKSOURCE_PLL3

+#define RCC_SPI5CLKSOURCE_HSI         RCC_SPI45CLKSOURCE_HSI

+#define RCC_SPI5CLKSOURCE_CSI         RCC_SPI45CLKSOURCE_CSI

+#define RCC_SPI5CLKSOURCE_HSE         RCC_SPI45CLKSOURCE_HSE

+

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_SPI6_Clock_Source SPI6 Clock Source

+  * @{

+  */

+#if defined(RCC_D3CCIPR_SPI6SEL)

+#define RCC_SPI6CLKSOURCE_D3PCLK1     (0x00000000U)

+#define RCC_SPI6CLKSOURCE_PCLK4        RCC_SPI6CLKSOURCE_D3PCLK1

+#define RCC_SPI6CLKSOURCE_PLL2         RCC_D3CCIPR_SPI6SEL_0

+#define RCC_SPI6CLKSOURCE_PLL3         RCC_D3CCIPR_SPI6SEL_1

+#define RCC_SPI6CLKSOURCE_HSI         (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1)

+#define RCC_SPI6CLKSOURCE_CSI          RCC_D3CCIPR_SPI6SEL_2

+#define RCC_SPI6CLKSOURCE_HSE         (RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2)

+#else

+#define RCC_SPI6CLKSOURCE_SRDPCLK4    (0x00000000U)

+/* alias */

+#define RCC_SPI6CLKSOURCE_D3PCLK1      RCC_SPI6CLKSOURCE_SRDPCLK4  /* D3PCLK1 is used in STM32H74xxx, STM32H75xxx, STM32H72xxx and STM32H73xxx family lines */

+#define RCC_SPI6CLKSOURCE_PCLK4        RCC_SPI6CLKSOURCE_SRDPCLK4

+#define RCC_SPI6CLKSOURCE_PLL2         RCC_SRDCCIPR_SPI6SEL_0

+#define RCC_SPI6CLKSOURCE_PLL3         RCC_SRDCCIPR_SPI6SEL_1

+#define RCC_SPI6CLKSOURCE_HSI         (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)

+#define RCC_SPI6CLKSOURCE_CSI          RCC_SRDCCIPR_SPI6SEL_2

+#define RCC_SPI6CLKSOURCE_HSE         (RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)

+#define RCC_SPI6CLKSOURCE_PIN         (RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)

+#endif /* RCC_D3CCIPR_SPI6SEL */

+

+/**

+  * @}

+  */

+

+

+#if defined(SAI4_Block_A)

+/** @defgroup RCCEx_SAI4A_Clock_Source SAI4A Clock Source

+  * @{

+  */

+#define RCC_SAI4ACLKSOURCE_PLL         (0x00000000U)

+#define RCC_SAI4ACLKSOURCE_PLL2         RCC_D3CCIPR_SAI4ASEL_0

+#define RCC_SAI4ACLKSOURCE_PLL3         RCC_D3CCIPR_SAI4ASEL_1

+#define RCC_SAI4ACLKSOURCE_PIN         (RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1)

+#define RCC_SAI4ACLKSOURCE_CLKP         RCC_D3CCIPR_SAI4ASEL_2

+

+/**

+  * @}

+  */

+#endif /* SAI4_Block_A */

+

+

+

+#if defined(SAI4_Block_B)

+/** @defgroup RCCEx_SAI4B_Clock_Source SAI4B Clock Source

+  * @{

+  */

+#define RCC_SAI4BCLKSOURCE_PLL         (0x00000000U)

+#define RCC_SAI4BCLKSOURCE_PLL2         RCC_D3CCIPR_SAI4BSEL_0

+#define RCC_SAI4BCLKSOURCE_PLL3         RCC_D3CCIPR_SAI4BSEL_1

+#define RCC_SAI4BCLKSOURCE_PIN         (RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1)

+#define RCC_SAI4BCLKSOURCE_CLKP         RCC_D3CCIPR_SAI4BSEL_2

+

+/**

+  * @}

+  */

+#endif /* SAI4_Block_B */

+

+

+/** @defgroup RCCEx_LPTIM1_Clock_Source  RCCEx LPTIM1 Clock Source

+  * @{

+  */

+#if defined(RCC_D2CCIP2R_LPTIM1SEL)

+#define RCC_LPTIM1CLKSOURCE_D2PCLK1        (0x00000000U)

+/* alias */

+#define RCC_LPTIM1CLKSOURCE_PCLK1         RCC_LPTIM1CLKSOURCE_D2PCLK1

+#define RCC_LPTIM1CLKSOURCE_PLL2          RCC_D2CCIP2R_LPTIM1SEL_0

+#define RCC_LPTIM1CLKSOURCE_PLL3          RCC_D2CCIP2R_LPTIM1SEL_1

+#define RCC_LPTIM1CLKSOURCE_LSE          (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1)

+#define RCC_LPTIM1CLKSOURCE_LSI           RCC_D2CCIP2R_LPTIM1SEL_2

+#define RCC_LPTIM1CLKSOURCE_CLKP         (RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2)

+#else

+#define RCC_LPTIM1CLKSOURCE_CDPCLK1        (0x00000000U)

+/* alias */

+#define RCC_LPTIM1CLKSOURCE_PCLK1         RCC_LPTIM1CLKSOURCE_CDPCLK1

+#define RCC_LPTIM1CLKSOURCE_D2PCLK1       RCC_LPTIM1CLKSOURCE_CDPCLK1

+#define RCC_LPTIM1CLKSOURCE_PLL2          RCC_CDCCIP2R_LPTIM1SEL_0

+#define RCC_LPTIM1CLKSOURCE_PLL3          RCC_CDCCIP2R_LPTIM1SEL_1

+#define RCC_LPTIM1CLKSOURCE_LSE          (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1)

+#define RCC_LPTIM1CLKSOURCE_LSI           RCC_CDCCIP2R_LPTIM1SEL_2

+#define RCC_LPTIM1CLKSOURCE_CLKP         (RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2)

+#endif /* RCC_D2CCIP2R_LPTIM1SEL */

+

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_LPTIM2_Clock_Source  RCCEx LPTIM2 Clock Source

+  * @{

+  */

+#if defined(RCC_D3CCIPR_LPTIM2SEL)

+#define RCC_LPTIM2CLKSOURCE_D3PCLK1       (0x00000000U)

+/* alias */

+#define RCC_LPTIM2CLKSOURCE_PCLK4         RCC_LPTIM2CLKSOURCE_D3PCLK1

+#define RCC_LPTIM2CLKSOURCE_PLL2          RCC_D3CCIPR_LPTIM2SEL_0

+#define RCC_LPTIM2CLKSOURCE_PLL3          RCC_D3CCIPR_LPTIM2SEL_1

+#define RCC_LPTIM2CLKSOURCE_LSE          (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1)

+#define RCC_LPTIM2CLKSOURCE_LSI           RCC_D3CCIPR_LPTIM2SEL_2

+#define RCC_LPTIM2CLKSOURCE_CLKP         (RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2)

+#else

+#define RCC_LPTIM2CLKSOURCE_SRDPCLK4       (0x00000000U)

+/*alias*/

+#define RCC_LPTIM2CLKSOURCE_PCLK4         RCC_LPTIM2CLKSOURCE_SRDPCLK4

+#define RCC_LPTIM2CLKSOURCE_D3PCLK1       RCC_LPTIM2CLKSOURCE_SRDPCLK4

+#define RCC_LPTIM2CLKSOURCE_PLL2          RCC_SRDCCIPR_LPTIM2SEL_0

+#define RCC_LPTIM2CLKSOURCE_PLL3          RCC_SRDCCIPR_LPTIM2SEL_1

+#define RCC_LPTIM2CLKSOURCE_LSE          (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1)

+#define RCC_LPTIM2CLKSOURCE_LSI           RCC_SRDCCIPR_LPTIM2SEL_2

+#define RCC_LPTIM2CLKSOURCE_CLKP         (RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2)

+#endif /* RCC_D3CCIPR_LPTIM2SEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_LPTIM345_Clock_Source  RCCEx LPTIM3/4/5 Clock Source

+  * @{

+  */

+#if defined(RCC_D3CCIPR_LPTIM345SEL)

+#define RCC_LPTIM345CLKSOURCE_D3PCLK1        (0x00000000U)

+/* alias*/

+#define RCC_LPTIM345CLKSOURCE_PCLK4         RCC_LPTIM345CLKSOURCE_D3PCLK1

+#define RCC_LPTIM345CLKSOURCE_PLL2          RCC_D3CCIPR_LPTIM345SEL_0

+#define RCC_LPTIM345CLKSOURCE_PLL3          RCC_D3CCIPR_LPTIM345SEL_1

+#define RCC_LPTIM345CLKSOURCE_LSE          (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)

+#define RCC_LPTIM345CLKSOURCE_LSI           RCC_D3CCIPR_LPTIM345SEL_2

+#define RCC_LPTIM345CLKSOURCE_CLKP         (RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)

+#else

+#define RCC_LPTIM345CLKSOURCE_SRDPCLK4      (0x00000000U)

+/* alias */

+#define RCC_LPTIM345CLKSOURCE_PCLK4         RCC_LPTIM345CLKSOURCE_SRDPCLK4

+#define RCC_LPTIM345CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_SRDPCLK4

+#define RCC_LPTIM345CLKSOURCE_PLL2          RCC_SRDCCIPR_LPTIM3SEL_0

+#define RCC_LPTIM345CLKSOURCE_PLL3          RCC_SRDCCIPR_LPTIM3SEL_1

+#define RCC_LPTIM345CLKSOURCE_LSE          (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1)

+#define RCC_LPTIM345CLKSOURCE_LSI           RCC_SRDCCIPR_LPTIM3SEL_2

+#define RCC_LPTIM345CLKSOURCE_CLKP         (RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2)

+#endif /* RCC_D3CCIPR_LPTIM345SEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_LPTIM3_Clock_Source  RCCEx LPTIM3 Clock Source

+  * @{

+  */

+#define RCC_LPTIM3CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_D3PCLK1

+#define RCC_LPTIM3CLKSOURCE_PLL2          RCC_LPTIM345CLKSOURCE_PLL2

+#define RCC_LPTIM3CLKSOURCE_PLL3          RCC_LPTIM345CLKSOURCE_PLL3

+#define RCC_LPTIM3CLKSOURCE_LSE           RCC_LPTIM345CLKSOURCE_LSE

+#define RCC_LPTIM3CLKSOURCE_LSI           RCC_LPTIM345CLKSOURCE_LSI

+#define RCC_LPTIM3CLKSOURCE_CLKP          RCC_LPTIM345CLKSOURCE_CLKP

+

+/**

+  * @}

+  */

+#if defined(LPTIM4)

+/** @defgroup RCCEx_LPTIM4_Clock_Source  RCCEx LPTIM4 Clock Source

+  * @{

+  */

+#define RCC_LPTIM4CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_D3PCLK1

+#define RCC_LPTIM4CLKSOURCE_PLL2          RCC_LPTIM345CLKSOURCE_PLL2

+#define RCC_LPTIM4CLKSOURCE_PLL3          RCC_LPTIM345CLKSOURCE_PLL3

+#define RCC_LPTIM4CLKSOURCE_LSE           RCC_LPTIM345CLKSOURCE_LSE

+#define RCC_LPTIM4CLKSOURCE_LSI           RCC_LPTIM345CLKSOURCE_LSI

+#define RCC_LPTIM4CLKSOURCE_CLKP          RCC_LPTIM345CLKSOURCE_CLKP

+/**

+  * @}

+  */

+#endif /* LPTIM4 */

+

+#if defined(LPTIM5)

+/** @defgroup RCCEx_LPTIM5_Clock_Source  RCCEx LPTIM5 Clock Source

+  * @{

+  */

+#define RCC_LPTIM5CLKSOURCE_D3PCLK1       RCC_LPTIM345CLKSOURCE_D3PCLK1

+#define RCC_LPTIM5CLKSOURCE_PLL2          RCC_LPTIM345CLKSOURCE_PLL2

+#define RCC_LPTIM5CLKSOURCE_PLL3          RCC_LPTIM345CLKSOURCE_PLL3

+#define RCC_LPTIM5CLKSOURCE_LSE           RCC_LPTIM345CLKSOURCE_LSE

+#define RCC_LPTIM5CLKSOURCE_LSI           RCC_LPTIM345CLKSOURCE_LSI

+#define RCC_LPTIM5CLKSOURCE_CLKP          RCC_LPTIM345CLKSOURCE_CLKP

+

+/**

+  * @}

+  */

+#endif /* LPTIM5 */

+

+#if defined(QUADSPI)

+/** @defgroup RCCEx_QSPI_Clock_Source  RCCEx QSPI Clock Source

+  * @{

+  */

+#define RCC_QSPICLKSOURCE_D1HCLK       (0x00000000U)

+#define RCC_QSPICLKSOURCE_PLL          RCC_D1CCIPR_QSPISEL_0

+#define RCC_QSPICLKSOURCE_PLL2         RCC_D1CCIPR_QSPISEL_1

+#define RCC_QSPICLKSOURCE_CLKP         RCC_D1CCIPR_QSPISEL

+

+/**

+  * @}

+  */

+#endif /* QUADSPI */

+

+

+#if defined(OCTOSPI1) || defined(OCTOSPI2)

+/** @defgroup RCCEx_OSPI_Clock_Source  RCCEx OSPI Clock Source

+  * @{

+  */

+#define RCC_OSPICLKSOURCE_CDHCLK       (0x00000000U)

+/*aliases*/

+#define RCC_OSPICLKSOURCE_D1HCLK       RCC_OSPICLKSOURCE_CDHCLK

+#define RCC_OSPICLKSOURCE_HCLK         RCC_OSPICLKSOURCE_CDHCLK

+#define RCC_OSPICLKSOURCE_PLL          RCC_CDCCIPR_OCTOSPISEL_0

+#define RCC_OSPICLKSOURCE_PLL2         RCC_CDCCIPR_OCTOSPISEL_1

+#define RCC_OSPICLKSOURCE_CLKP         RCC_CDCCIPR_OCTOSPISEL

+

+/**

+  * @}

+  */

+#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */

+

+#if defined(DSI)

+/** @defgroup RCCEx_DSI_Clock_Source  RCCEx DSI Clock Source

+  * @{

+  */

+#define RCC_DSICLKSOURCE_PHY       (0x00000000U)

+#define RCC_DSICLKSOURCE_PLL2       RCC_D1CCIPR_DSISEL

+

+/**

+  * @}

+  */

+#endif /* DSI */

+

+/** @defgroup RCCEx_FMC_Clock_Source  RCCEx FMC Clock Source

+  * @{

+  */

+#if defined(RCC_D1CCIPR_FMCSEL)

+#define RCC_FMCCLKSOURCE_D1HCLK       (0x00000000U)

+#define RCC_FMCCLKSOURCE_HCLK         RCC_FMCCLKSOURCE_D1HCLK

+#define RCC_FMCCLKSOURCE_PLL          RCC_D1CCIPR_FMCSEL_0

+#define RCC_FMCCLKSOURCE_PLL2         RCC_D1CCIPR_FMCSEL_1

+#define RCC_FMCCLKSOURCE_CLKP         RCC_D1CCIPR_FMCSEL

+#else

+#define RCC_FMCCLKSOURCE_CDHCLK       (0x00000000U)

+#define RCC_FMCCLKSOURCE_HCLK         RCC_FMCCLKSOURCE_CDHCLK

+/*alias*/

+#define RCC_FMCCLKSOURCE_D1HCLK       RCC_FMCCLKSOURCE_CDHCLK

+#define RCC_FMCCLKSOURCE_PLL          RCC_CDCCIPR_FMCSEL_0

+#define RCC_FMCCLKSOURCE_PLL2         RCC_CDCCIPR_FMCSEL_1

+#define RCC_FMCCLKSOURCE_CLKP         RCC_CDCCIPR_FMCSEL

+#endif /* RCC_D1CCIPR_FMCSEL */

+/**

+  * @}

+  */

+

+#if defined(FDCAN1) || defined(FDCAN2)

+/** @defgroup RCCEx_FDCAN_Clock_Source  RCCEx FDCAN Clock Source

+  * @{

+  */

+#if defined(RCC_D2CCIP1R_FDCANSEL)

+#define RCC_FDCANCLKSOURCE_HSE         (0x00000000U)

+#define RCC_FDCANCLKSOURCE_PLL          RCC_D2CCIP1R_FDCANSEL_0

+#define RCC_FDCANCLKSOURCE_PLL2         RCC_D2CCIP1R_FDCANSEL_1

+#else

+#define RCC_FDCANCLKSOURCE_HSE         (0x00000000U)

+#define RCC_FDCANCLKSOURCE_PLL          RCC_CDCCIP1R_FDCANSEL_0

+#define RCC_FDCANCLKSOURCE_PLL2         RCC_CDCCIP1R_FDCANSEL_1

+#endif /* D3_SRAM_BASE */

+/**

+  * @}

+  */

+#endif /*FDCAN1 || FDCAN2*/

+

+

+/** @defgroup RCCEx_SDMMC_Clock_Source  RCCEx SDMMC Clock Source

+  * @{

+  */

+#if defined(RCC_D1CCIPR_SDMMCSEL)

+#define RCC_SDMMCCLKSOURCE_PLL           (0x00000000U)

+#define RCC_SDMMCCLKSOURCE_PLL2           RCC_D1CCIPR_SDMMCSEL

+#else

+#define RCC_SDMMCCLKSOURCE_PLL           (0x00000000U)

+#define RCC_SDMMCCLKSOURCE_PLL2           RCC_CDCCIPR_SDMMCSEL

+#endif /* RCC_D1CCIPR_SDMMCSEL */

+/**

+  * @}

+  */

+

+

+/** @defgroup RCCEx_ADC_Clock_Source  RCCEx ADC Clock Source

+  * @{

+  */

+#if defined(RCC_D3CCIPR_ADCSEL_0)

+#define RCC_ADCCLKSOURCE_PLL2       (0x00000000U)

+#define RCC_ADCCLKSOURCE_PLL3       RCC_D3CCIPR_ADCSEL_0

+#define RCC_ADCCLKSOURCE_CLKP       RCC_D3CCIPR_ADCSEL_1

+#else

+#define RCC_ADCCLKSOURCE_PLL2       (0x00000000U)

+#define RCC_ADCCLKSOURCE_PLL3       RCC_SRDCCIPR_ADCSEL_0

+#define RCC_ADCCLKSOURCE_CLKP       RCC_SRDCCIPR_ADCSEL_1

+#endif /* RCC_D3CCIPR_ADCSEL_0  */

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_SWPMI1_Clock_Source  RCCEx SWPMI1 Clock Source

+  * @{

+  */

+#if defined(RCC_D2CCIP1R_SWPSEL)

+#define RCC_SWPMI1CLKSOURCE_D2PCLK1       (0x00000000U)

+#define RCC_SWPMI1CLKSOURCE_HSI            RCC_D2CCIP1R_SWPSEL

+#else

+#define RCC_SWPMI1CLKSOURCE_CDPCLK1       (0x00000000U)

+/* alias */

+#define RCC_SWPMI1CLKSOURCE_D2PCLK1        RCC_SWPMI1CLKSOURCE_CDPCLK1

+#define RCC_SWPMI1CLKSOURCE_HSI            RCC_CDCCIP1R_SWPSEL

+#endif /* RCC_D2CCIP1R_SWPSEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_DFSDM1_Clock_Source  RCCEx DFSDM1 Clock Source

+  * @{

+  */

+#if defined(RCC_D2CCIP1R_DFSDM1SEL)

+#define RCC_DFSDM1CLKSOURCE_D2PCLK1        (0x00000000U)

+#define RCC_DFSDM1CLKSOURCE_SYS            RCC_D2CCIP1R_DFSDM1SEL

+#else

+#define RCC_DFSDM1CLKSOURCE_CDPCLK1        (0x00000000U)

+/* alias */

+#define RCC_DFSDM1CLKSOURCE_D2PCLK1        RCC_DFSDM1CLKSOURCE_CDPCLK1

+#define RCC_DFSDM1CLKSOURCE_SYS            RCC_CDCCIP1R_DFSDM1SEL

+#endif /* RCC_D2CCIP1R_DFSDM1SEL */

+/**

+  * @}

+  */

+

+#if defined(DFSDM2_BASE)

+/** @defgroup RCCEx_DFSDM2_Clock_Source  RCCEx DFSDM2 Clock Source

+  * @{

+  */

+#define RCC_DFSDM2CLKSOURCE_SRDPCLK4       (0x00000000U)

+/* alias */

+#define RCC_DFSDM2CLKSOURCE_SRDPCLK1       RCC_DFSDM2CLKSOURCE_SRDPCLK4

+#define RCC_DFSDM2CLKSOURCE_SYS            RCC_SRDCCIPR_DFSDM2SEL

+/**

+  * @}

+  */

+#endif /* DFSDM2 */

+

+/** @defgroup RCCEx_SPDIFRX_Clock_Source  RCCEx SPDIFRX Clock Source

+  * @{

+  */

+#if defined(RCC_D2CCIP1R_SPDIFSEL_0)

+#define RCC_SPDIFRXCLKSOURCE_PLL        (0x00000000U)

+#define RCC_SPDIFRXCLKSOURCE_PLL2       RCC_D2CCIP1R_SPDIFSEL_0

+#define RCC_SPDIFRXCLKSOURCE_PLL3       RCC_D2CCIP1R_SPDIFSEL_1

+#define RCC_SPDIFRXCLKSOURCE_HSI        RCC_D2CCIP1R_SPDIFSEL

+#else

+#define RCC_SPDIFRXCLKSOURCE_PLL        (0x00000000U)

+#define RCC_SPDIFRXCLKSOURCE_PLL2       RCC_CDCCIP1R_SPDIFSEL_0

+#define RCC_SPDIFRXCLKSOURCE_PLL3       RCC_CDCCIP1R_SPDIFSEL_1

+#define RCC_SPDIFRXCLKSOURCE_HSI        RCC_CDCCIP1R_SPDIFSEL

+#endif /* RCC_D2CCIP1R_SPDIFSEL_0 */

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_CEC_Clock_Source  RCCEx CEC Clock Source

+  * @{

+  */

+#if defined(RCC_D2CCIP2R_CECSEL_0)

+#define RCC_CECCLKSOURCE_LSE        (0x00000000U)

+#define RCC_CECCLKSOURCE_LSI         RCC_D2CCIP2R_CECSEL_0

+#define RCC_CECCLKSOURCE_CSI         RCC_D2CCIP2R_CECSEL_1

+#else

+#define RCC_CECCLKSOURCE_LSE        (0x00000000U)

+#define RCC_CECCLKSOURCE_LSI         RCC_CDCCIP2R_CECSEL_0

+#define RCC_CECCLKSOURCE_CSI         RCC_CDCCIP2R_CECSEL_1

+#endif /* RCC_D2CCIP2R_CECSEL_0 */

+/**

+  * @}

+  */

+

+

+/** @defgroup RCCEx_CLKP_Clock_Source  RCCEx CLKP Clock Source

+  * @{

+  */

+#if defined(RCC_D1CCIPR_CKPERSEL_0)

+#define RCC_CLKPSOURCE_HSI        (0x00000000U)

+#define RCC_CLKPSOURCE_CSI         RCC_D1CCIPR_CKPERSEL_0

+#define RCC_CLKPSOURCE_HSE         RCC_D1CCIPR_CKPERSEL_1

+#else

+#define RCC_CLKPSOURCE_HSI        (0x00000000U)

+#define RCC_CLKPSOURCE_CSI         RCC_CDCCIPR_CKPERSEL_0

+#define RCC_CLKPSOURCE_HSE         RCC_CDCCIPR_CKPERSEL_1

+#endif /* RCC_D1CCIPR_CKPERSEL_0 */

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection

+  * @{

+  */

+#define RCC_TIMPRES_DESACTIVATED        (0x00000000U)

+#define RCC_TIMPRES_ACTIVATED            RCC_CFGR_TIMPRE

+

+/**

+  * @}

+  */

+

+#if defined(DUAL_CORE)

+

+/** @defgroup RCCEx_RCC_BootCx RCCEx RCC BootCx

+  * @{

+  */

+#define RCC_BOOT_C1        RCC_GCR_BOOT_C1

+#define RCC_BOOT_C2        RCC_GCR_BOOT_C2

+

+/**

+  * @}

+  */

+#endif /*DUAL_CORE*/

+

+#if defined(DUAL_CORE)

+/** @defgroup RCCEx_RCC_WWDGx  RCCEx RCC WWDGx

+  * @{

+  */

+#define RCC_WWDG1        RCC_GCR_WW1RSC

+#define RCC_WWDG2        RCC_GCR_WW2RSC

+

+/**

+  * @}

+  */

+

+#else

+

+/** @defgroup RCCEx_RCC_WWDGx  RCCEx RCC WWDGx

+  * @{

+  */

+#define RCC_WWDG1        RCC_GCR_WW1RSC

+

+/**

+  * @}

+  */

+

+#endif /*DUAL_CORE*/

+

+/** @defgroup RCCEx_EXTI_LINE_LSECSS  RCC LSE CSS external interrupt line

+  * @{

+  */

+#define RCC_EXTI_LINE_LSECSS           EXTI_IMR1_IM18        /*!< External interrupt line 19 connected to the LSE CSS EXTI Line */

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_CRS_Status RCCEx CRS Status

+  * @{

+  */

+#define RCC_CRS_NONE                   (0x00000000U)

+#define RCC_CRS_TIMEOUT                (0x00000001U)

+#define RCC_CRS_SYNCOK                 (0x00000002U)

+#define RCC_CRS_SYNCWARN               (0x00000004U)

+#define RCC_CRS_SYNCERR                (0x00000008U)

+#define RCC_CRS_SYNCMISS               (0x00000010U)

+#define RCC_CRS_TRIMOVF                (0x00000020U)

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource

+  * @{

+  */

+#define RCC_CRS_SYNC_SOURCE_PIN       (0x00000000U)                            /*!< Synchro Signal source external pin, Available on STM32H7 Rev.B and above devices only */

+#define RCC_CRS_SYNC_SOURCE_LSE        CRS_CFGR_SYNCSRC_0                      /*!< Synchro Signal source LSE */

+#define RCC_CRS_SYNC_SOURCE_USB1       CRS_CFGR_SYNCSRC_1                      /*!< Synchro Signal source USB1 SOF (default) */

+#define RCC_CRS_SYNC_SOURCE_USB2      (CRS_CFGR_SYNCSRC_1|CRS_CFGR_SYNCSRC_0)  /*!< Synchro Signal source USB2 SOF */

+

+

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider

+  * @{

+  */

+#define RCC_CRS_SYNC_DIV1        (0x00000000U)           /*!< Synchro Signal not divided (default) */

+#define RCC_CRS_SYNC_DIV2        CRS_CFGR_SYNCDIV_0                         /*!< Synchro Signal divided by 2 */

+#define RCC_CRS_SYNC_DIV4        CRS_CFGR_SYNCDIV_1                         /*!< Synchro Signal divided by 4 */

+#define RCC_CRS_SYNC_DIV8        (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0)  /*!< Synchro Signal divided by 8 */

+#define RCC_CRS_SYNC_DIV16       CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */

+#define RCC_CRS_SYNC_DIV32       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */

+#define RCC_CRS_SYNC_DIV64       (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */

+#define RCC_CRS_SYNC_DIV128      CRS_CFGR_SYNCDIV                         /*!< Synchro Signal divided by 128 */

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity

+  * @{

+  */

+#define RCC_CRS_SYNC_POLARITY_RISING   (0x00000000U) /*!< Synchro Active on rising edge (default) */

+#define RCC_CRS_SYNC_POLARITY_FALLING  CRS_CFGR_SYNCPOL        /*!< Synchro Active on falling edge */

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault

+  * @{

+  */

+#define RCC_CRS_RELOADVALUE_DEFAULT    (0x0000BB7FU) /*!< The reset value of the RELOAD field corresponds

+                                                                    to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault

+  * @{

+  */

+#define RCC_CRS_ERRORLIMIT_DEFAULT     (0x00000022U) /*!< Default Frequency error limit */

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault

+  * @{

+  */

+#define RCC_CRS_HSI48CALIBRATION_DEFAULT (0x00000020U) /*!< The default value is 32, which corresponds to the middle of the trimming interval.

+                                                                      The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value

+                                                                      corresponds to a higher output frequency */

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection

+  * @{

+  */

+#define RCC_CRS_FREQERRORDIR_UP        (0x00000000U)   /*!< Upcounting direction, the actual frequency is above the target */

+#define RCC_CRS_FREQERRORDIR_DOWN      (CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources

+  * @{

+  */

+#define RCC_CRS_IT_SYNCOK              CRS_CR_SYNCOKIE       /*!< SYNC event OK */

+#define RCC_CRS_IT_SYNCWARN            CRS_CR_SYNCWARNIE     /*!< SYNC warning */

+#define RCC_CRS_IT_ERR                 CRS_CR_ERRIE          /*!< Error */

+#define RCC_CRS_IT_ESYNC               CRS_CR_ESYNCIE        /*!< Expected SYNC */

+#define RCC_CRS_IT_SYNCERR             CRS_CR_ERRIE          /*!< SYNC error */

+#define RCC_CRS_IT_SYNCMISS            CRS_CR_ERRIE          /*!< SYNC missed */

+#define RCC_CRS_IT_TRIMOVF             CRS_CR_ERRIE          /*!< Trimming overflow or underflow */

+

+/**

+  * @}

+  */

+

+/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags

+  * @{

+  */

+#define RCC_CRS_FLAG_SYNCOK            CRS_ISR_SYNCOKF       /*!< SYNC event OK flag     */

+#define RCC_CRS_FLAG_SYNCWARN          CRS_ISR_SYNCWARNF     /*!< SYNC warning flag      */

+#define RCC_CRS_FLAG_ERR               CRS_ISR_ERRF          /*!< Error flag        */

+#define RCC_CRS_FLAG_ESYNC             CRS_ISR_ESYNCF        /*!< Expected SYNC flag     */

+#define RCC_CRS_FLAG_SYNCERR           CRS_ISR_SYNCERR       /*!< SYNC error */

+#define RCC_CRS_FLAG_SYNCMISS          CRS_ISR_SYNCMISS      /*!< SYNC missed*/

+#define RCC_CRS_FLAG_TRIMOVF           CRS_ISR_TRIMOVF       /*!< Trimming overflow or underflow */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros

+  * @{

+  */

+

+/** @brief  Macros to enable or disable PLL2.

+  * @note   After enabling PLL2, the application software should wait on

+  *         PLL2RDY flag to be set indicating that PLL2 clock is stable and can

+  *         be used as kernel clock source.

+  * @note   PLL2 is disabled by hardware when entering STOP and STANDBY modes.

+  */

+#define __HAL_RCC_PLL2_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLL2ON)

+#define __HAL_RCC_PLL2_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON)

+

+/**

+  * @brief  Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK)

+  * @note   Enabling/disabling  those Clocks can be done only when the PLL2 is disabled,

+  *         This is mainly used to save Power.

+  * @param  __RCC_PLL2ClockOut__ Specifies the PLL2 clock to be outputted

+  *          This parameter can be one of the following values:

+  *            @arg RCC_PLL2_DIVP: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)

+  *            @arg RCC_PLL2_DIVQ: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)

+  *            @arg RCC_PLL2_DIVR: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)

+  *

+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.

+  *

+  * @retval None

+  */

+#define __HAL_RCC_PLL2CLKOUT_ENABLE(__RCC_PLL2ClockOut__)   SET_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))

+

+#define __HAL_RCC_PLL2CLKOUT_DISABLE(__RCC_PLL2ClockOut__)  CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL2ClockOut__))

+

+/**

+  * @brief  Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO

+  * @note   Enabling/disabling  Fractional Part can be any time  without the need to stop the PLL2

+  * @retval None

+  */

+#define __HAL_RCC_PLL2FRACN_ENABLE()   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)

+

+#define __HAL_RCC_PLL2FRACN_DISABLE()  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN)

+

+/**

+  * @brief  Macro to configures the PLL2  multiplication and division factors.

+  * @note   This function must be used only when PLL2 is disabled.

+  *

+  * @param  __PLL2M__ specifies the division factor for PLL2 VCO input clock

+  *          This parameter must be a number between 1 and 63.

+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input

+  *         frequency ranges from 1 to 16 MHz.

+  *

+  * @param  __PLL2N__ specifies the multiplication factor for PLL2 VCO output clock

+  *          This parameter must be a number between 4 and 512 or between 8 and 420(*).

+  * @note   You have to set the PLL2N parameter correctly to ensure that the VCO

+  *         output frequency is between 150 and 420 MHz (when in medium VCO range) or

+  *         between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)

+  *

+  * @param  __PLL2P__ specifies the division factor for peripheral kernel clocks

+  *          This parameter must be a number between 1 and 128.

+  *

+  * @param  __PLL2Q__ specifies the division factor for peripheral kernel clocks

+  *          This parameter must be a number between 1 and 128.

+  *

+  * @param  __PLL2R__ specifies the division factor for peripheral kernel clocks

+  *          This parameter must be a number between 1 and 128.

+  *

+  * @note   To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR)

+  *         is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible

+  *         value to  __PLL2P__, __PLL2Q__ or __PLL2R__ parameters.

+  * @retval None

+  *

+  *  (*) : For stm32h7a3xx and stm32h7b3xx family lines.

+  */

+

+#define __HAL_RCC_PLL2_CONFIG(__PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__,__PLL2R__ ) \

+                  do{ \

+                       MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM2) , ( (__PLL2M__) <<12U));  \

+                       WRITE_REG (RCC->PLL2DIVR , ( (((__PLL2N__) - 1U ) & RCC_PLL2DIVR_N2) | ((((__PLL2P__) -1U ) << 9U) & RCC_PLL2DIVR_P2) | \

+                       ((((__PLL2Q__) -1U) << 16U) & RCC_PLL2DIVR_Q2) | ((((__PLL2R__)- 1U) << 24U) & RCC_PLL2DIVR_R2))); \

+                    } while(0)

+

+/**

+  * @brief  Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor

+  *

+  * @note   These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO

+  *

+  * @param  __RCC_PLL2FRACN__ Specifies Fractional Part Of The Multiplication factor for PLL2 VCO

+  *                           It should be a value between 0 and 8191

+  * @note   Warning: the software has to set correctly these bits to insure that the VCO

+  *                  output frequency is between its valid frequency range, which is:

+  *                  192 to 836 MHz or 128 to 560 MHz(*) if PLL2VCOSEL = 0

+  *                  150 to 420 MHz if PLL2VCOSEL = 1.

+  *

+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.

+  *

+  * @retval None

+  */

+#define  __HAL_RCC_PLL2FRACN_CONFIG(__RCC_PLL2FRACN__) \

+                 MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2,((uint32_t)(__RCC_PLL2FRACN__) << RCC_PLL2FRACR_FRACN2_Pos))

+

+/** @brief  Macro to select  the PLL2  reference frequency range.

+  * @param  __RCC_PLL2VCIRange__ specifies the PLL2 input frequency range

+  *         This parameter can be one of the following values:

+  *            @arg RCC_PLL2VCIRANGE_0: Range frequency is between 1 and 2 MHz

+  *            @arg RCC_PLL2VCIRANGE_1: Range frequency is between 2 and 4 MHz

+  *            @arg RCC_PLL2VCIRANGE_2: Range frequency is between 4 and 8 MHz

+  *            @arg RCC_PLL2VCIRANGE_3: Range frequency is between 8 and 16 MHz

+  * @retval None

+  */

+#define __HAL_RCC_PLL2_VCIRANGE(__RCC_PLL2VCIRange__) \

+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, (__RCC_PLL2VCIRange__))

+

+

+/** @brief  Macro to select  the PLL2  reference frequency range.

+  * @param  __RCC_PLL2VCORange__ Specifies the PLL2 input frequency range

+  *         This parameter can be one of the following values:

+  *            @arg RCC_PLL2VCOWIDE: Range frequency is between 192 and 836 MHz or between 128 to 560 MHz(*)

+  *            @arg RCC_PLL2VCOMEDIUM: Range frequency is between 150 and 420 MHz

+  *

+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.

+  *

+  * @retval None

+  */

+#define __HAL_RCC_PLL2_VCORANGE(__RCC_PLL2VCORange__) \

+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, (__RCC_PLL2VCORange__))

+

+/** @brief  Macros to enable or disable the main PLL3.

+  * @note   After enabling  PLL3, the application software should wait on

+  *         PLL3RDY flag to be set indicating that PLL3 clock is stable and can

+  *         be used as kernel clock source.

+  * @note   PLL3 is disabled by hardware when entering STOP and STANDBY modes.

+  */

+#define __HAL_RCC_PLL3_ENABLE()         SET_BIT(RCC->CR, RCC_CR_PLL3ON)

+#define __HAL_RCC_PLL3_DISABLE()        CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON)

+

+/**

+  * @brief  Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO

+  * @note   Enabling/disabling  Fractional Part can be any time  without the need to stop the PLL3

+  * @retval None

+  */

+#define __HAL_RCC_PLL3FRACN_ENABLE()   SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)

+

+#define __HAL_RCC_PLL3FRACN_DISABLE()  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN)

+

+/**

+  * @brief  Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK)

+  * @note   Enabling/disabling  those Clocks can be done only when the PLL3 is disabled,

+  *         This is mainly used to save Power.

+  * @param  __RCC_PLL3ClockOut__ specifies the PLL3 clock to be outputted

+  *          This parameter can be one of the following values:

+  *            @arg RCC_PLL3_DIVP: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)

+  *            @arg RCC_PLL3_DIVQ: This clock is used to generate peripherals clock  up to 400MHZ or 280MHZ(*)

+  *            @arg RCC_PLL3_DIVR: This clock is used to generate peripherals clock up to 400MHZ or 280MHZ(*)

+  *

+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.

+  *

+  * @retval None

+  */

+#define __HAL_RCC_PLL3CLKOUT_ENABLE(__RCC_PLL3ClockOut__)   SET_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))

+

+#define __HAL_RCC_PLL3CLKOUT_DISABLE(__RCC_PLL3ClockOut__)  CLEAR_BIT(RCC->PLLCFGR, (__RCC_PLL3ClockOut__))

+

+/**

+  * @brief  Macro to configures the PLL3  multiplication and division factors.

+  * @note   This function must be used only when PLL3 is disabled.

+  *

+  * @param  __PLL3M__ specifies the division factor for PLL3 VCO input clock

+  *          This parameter must be a number between 1 and 63.

+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input

+  *         frequency ranges from 1 to 16 MHz.

+  *

+  * @param  __PLL3N__ specifies the multiplication factor for PLL3 VCO output clock

+  *          This parameter must be a number between 4 and 512.

+  * @note   You have to set the PLL3N parameter correctly to ensure that the VCO

+  *         output frequency is between 150 and 420 MHz (when in medium VCO range) or

+  *         between 192 and 836 MHZ or between 128 and 560 MHZ(*) (when in wide VCO range)

+  *

+  * @param  __PLL3P__ specifies the division factor for peripheral kernel clocks

+  *          This parameter must be a number between 2 and 128 (where odd numbers not allowed)

+  *

+  * @param  __PLL3Q__ specifies the division factor for peripheral kernel clocks

+  *          This parameter must be a number between 1 and 128

+  *

+  * @param  __PLL3R__ specifies the division factor for peripheral kernel clocks

+  *          This parameter must be a number between 1 and 128

+  *

+  * @note   To insure an optimal behavior of the PLL when one of the post-divider (DIVP, DIVQ or DIVR)

+  *         is not used, application shall clear the enable bit (DIVyEN) and assign lowest possible

+  *         value to  __PLL3P__, __PLL3Q__ or __PLL3R__ parameters.

+  * @retval None

+  *

+  *  (*) : For stm32h7a3xx and stm32h7b3xx family lines.

+  */

+

+#define __HAL_RCC_PLL3_CONFIG(__PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__,__PLL3R__ ) \

+                  do{ MODIFY_REG(RCC->PLLCKSELR, ( RCC_PLLCKSELR_DIVM3) , ( (__PLL3M__) <<20U));  \

+                         WRITE_REG (RCC->PLL3DIVR , ( (((__PLL3N__) - 1U ) & RCC_PLL3DIVR_N3) | ((((__PLL3P__) -1U ) << 9U) & RCC_PLL3DIVR_P3) | \

+                                   ((((__PLL3Q__) -1U) << 16U) & RCC_PLL3DIVR_Q3) | ((((__PLL3R__) - 1U) << 24U) & RCC_PLL3DIVR_R3))); \

+                       } while(0)

+

+

+

+/**

+  * @brief  Macro to configures  PLL3 clock Fractional Part of The Multiplication Factor

+  *

+  * @note   These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO

+  *

+  * @param  __RCC_PLL3FRACN__ specifies Fractional Part Of The Multiplication Factor for PLL3 VCO

+  *                            It should be a value between 0 and 8191

+  * @note   Warning: the software has to set correctly these bits to insure that the VCO

+  *                  output frequency is between its valid frequency range, which is:

+  *                  192 to 836 MHz or 128 to 560 MHz(*) if PLL3VCOSEL = 0

+  *                  150 to 420 MHz if PLL3VCOSEL = 1.

+  *

+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.

+  *

+  * @retval None

+  */

+ #define  __HAL_RCC_PLL3FRACN_CONFIG(__RCC_PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, (uint32_t)(__RCC_PLL3FRACN__) << RCC_PLL3FRACR_FRACN3_Pos)

+

+/** @brief  Macro to select  the PLL3  reference frequency range.

+  * @param  __RCC_PLL3VCIRange__ specifies the PLL1 input frequency range

+  *         This parameter can be one of the following values:

+  *            @arg RCC_PLL3VCIRANGE_0: Range frequency is between 1 and 2 MHz

+  *            @arg RCC_PLL3VCIRANGE_1: Range frequency is between 2 and 4 MHz

+  *            @arg RCC_PLL3VCIRANGE_2: Range frequency is between 4 and 8 MHz

+  *            @arg RCC_PLL3VCIRANGE_3: Range frequency is between 8 and 16 MHz

+  * @retval None

+  */

+#define __HAL_RCC_PLL3_VCIRANGE(__RCC_PLL3VCIRange__) \

+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, (__RCC_PLL3VCIRange__))

+

+

+/** @brief  Macro to select  the PLL3  reference frequency range.

+  * @param  __RCC_PLL3VCORange__ specifies the PLL1 input frequency range

+  *         This parameter can be one of the following values:

+  *            @arg RCC_PLL3VCOWIDE: Range frequency is between 192 and 836 MHz  or between 128 to 560 MHz(*)

+  *            @arg RCC_PLL3VCOMEDIUM: Range frequency is between 150 and 420 MHz

+  *

+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.

+  *

+  * @retval None

+  */

+#define __HAL_RCC_PLL3_VCORANGE(__RCC_PLL3VCORange__) \

+                  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, (__RCC_PLL3VCORange__))

+/**

+  * @brief  Macro to Configure the SAI1 clock source.

+  * @param  __RCC_SAI1CLKSource__ defines the SAI1 clock source. This clock is derived

+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)

+  *          This parameter can be one of the following values:

+  *             @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL

+  *             @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2

+  *             @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3

+  *             @arg RCC_SAI1CLKSOURCE_OSC: SAI1 clock  = OSC

+  *             @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock

+  * @retval None

+  */

+#if defined(RCC_D2CCIP1R_SAI1SEL)

+#define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\

+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))

+#else

+#define __HAL_RCC_SAI1_CONFIG(__RCC_SAI1CLKSource__ )\

+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL, (__RCC_SAI1CLKSource__))

+#endif /* RCC_D2CCIP1R_SAI1SEL */

+

+/** @brief  Macro to get the SAI1 clock source.

+  * @retval The clock source can be one of the following values:

+  *             @arg RCC_SAI1CLKSOURCE_PLL: SAI1 clock = PLL

+  *             @arg RCC_SAI1CLKSOURCE_PLL2: SAI1 clock = PLL2

+  *             @arg RCC_SAI1CLKSOURCE_PLL3: SAI1 clock = PLL3

+  *             @arg RCC_SAI1CLKSOURCE_CLKP: SAI1 clock  = CLKP

+  *             @arg RCC_SAI1CLKSOURCE_PIN: SAI1 clock = External Clock

+  */

+#if defined(RCC_D2CCIP1R_SAI1SEL)

+#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI1SEL)))

+#else

+#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI1SEL)))

+#endif /* RCC_D2CCIP1R_SAI1SEL */

+

+/**

+  * @brief  Macro to Configure the SPDIFRX clock source.

+  * @param  __RCC_SPDIFCLKSource__ defines the SPDIFRX clock source. This clock is derived

+  *         from system PLL, PLL2, PLL3,  or internal OSC clock

+  *          This parameter can be one of the following values:

+  *             @arg RCC_SPDIFRXCLKSOURCE_PLL:  SPDIFRX clock = PLL

+  *             @arg RCC_SPDIFRXCLKSOURCE_PLL2: SPDIFRX clock = PLL2

+  *             @arg RCC_SPDIFRXCLKSOURCE_PLL3: SPDIFRX clock = PLL3

+  *             @arg RCC_SPDIFRXCLKSOURCE_HSI:  SPDIFRX clock  = HSI

+  * @retval None

+  */

+#if defined(RCC_D2CCIP1R_SPDIFSEL)

+#define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\

+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))

+#else

+#define __HAL_RCC_SPDIFRX_CONFIG(__RCC_SPDIFCLKSource__ )\

+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, (__RCC_SPDIFCLKSource__))

+#endif /* RCC_D2CCIP1R_SPDIFSEL */

+

+/**

+  * @brief  Macro to get the SPDIFRX clock source.

+  * @retval None

+  */

+#if defined(RCC_D2CCIP1R_SPDIFSEL)

+#define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL)))

+#else

+#define __HAL_RCC_GET_SPDIFRX_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL)))

+#endif /* RCC_D2CCIP1R_SPDIFSEL */

+

+#if defined(SAI3)

+/**

+  * @brief  Macro to Configure the SAI2/3 clock source.

+  * @param  __RCC_SAI23CLKSource__ defines the SAI2/3 clock source. This clock is derived

+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)

+  *          This parameter can be one of the following values:

+  *             @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL

+  *             @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2

+  *             @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3

+  *             @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock  = CLKP

+  *             @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock

+  * @retval None

+  */

+#define __HAL_RCC_SAI23_CONFIG(__RCC_SAI23CLKSource__ )\

+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL, (__RCC_SAI23CLKSource__))

+

+/** @brief  Macro to get the SAI2/3 clock source.

+  * @retval The clock source can be one of the following values:

+  *             @arg RCC_SAI23CLKSOURCE_PLL: SAI2/3 clock = PLL

+  *             @arg RCC_SAI23CLKSOURCE_PLL2: SAI2/3 clock = PLL2

+  *             @arg RCC_SAI23CLKSOURCE_PLL3: SAI2/3 clock = PLL3

+  *             @arg RCC_SAI23CLKSOURCE_CLKP: SAI2/3 clock  = CLKP

+  *             @arg RCC_SAI23CLKSOURCE_PIN: SAI2/3 clock = External Clock

+  */

+#define __HAL_RCC_GET_SAI23_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SAI23SEL)))

+

+/**

+  * @brief  Macro to Configure the SAI2 clock source.

+  * @param  __RCC_SAI2CLKSource__ defines the SAI2 clock source. This clock is derived

+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)

+  *          This parameter can be one of the following values:

+  *             @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL

+  *             @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2

+  *             @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3

+  *             @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock  = CLKP

+  *             @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock

+  * @retval None

+  */

+#define __HAL_RCC_SAI2_CONFIG  __HAL_RCC_SAI23_CONFIG

+

+/** @brief  Macro to get the SAI2 clock source.

+  * @retval The clock source can be one of the following values:

+  *             @arg RCC_SAI2CLKSOURCE_PLL: SAI2 clock = PLL

+  *             @arg RCC_SAI2CLKSOURCE_PLL2: SAI2 clock = PLL2

+  *             @arg RCC_SAI2CLKSOURCE_PLL3: SAI2 clock = PLL3

+  *             @arg RCC_SAI2CLKSOURCE_CLKP: SAI2 clock  = CLKP

+  *             @arg RCC_SAI2CLKSOURCE_PIN: SAI2 clock = External Clock

+  */

+#define __HAL_RCC_GET_SAI2_SOURCE  __HAL_RCC_GET_SAI23_SOURCE

+

+/**

+  * @brief  Macro to Configure the SAI3 clock source.

+  * @param  __RCC_SAI3CLKSource__ defines the SAI3 clock source. This clock is derived

+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)

+  *          This parameter can be one of the following values:

+  *             @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL

+  *             @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2

+  *             @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3

+  *             @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock  = CLKP

+  *             @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock

+  * @retval None

+  */

+#define __HAL_RCC_SAI3_CONFIG __HAL_RCC_SAI23_CONFIG

+

+/** @brief  Macro to get the SAI3 clock source.

+  * @retval The clock source can be one of the following values:

+  *             @arg RCC_SAI3CLKSOURCE_PLL: SAI3 clock = PLL

+  *             @arg RCC_SAI3CLKSOURCE_PLL2: SAI3 clock = PLL2

+  *             @arg RCC_SAI3CLKSOURCE_PLL3: SAI3 clock = PLL3

+  *             @arg RCC_SAI3CLKSOURCE_CLKP: SAI3 clock  = CLKP

+  *             @arg RCC_SAI3CLKSOURCE_PIN: SAI3 clock = External Clock

+  */

+#define __HAL_RCC_GET_SAI3_SOURCE  __HAL_RCC_GET_SAI23_SOURCE

+#endif /* SAI3 */

+

+#if defined(RCC_CDCCIP1R_SAI2ASEL)

+/**

+  * @brief  Macro to Configure the SAI2A clock source.

+  * @param  __RCC_SAI2ACLKSource__ defines the SAI2A clock source. This clock is derived

+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)

+  *          This parameter can be one of the following values:

+  *             @arg RCC_SAI2ACLKSOURCE_PLL: SAI2A clock = PLL

+  *             @arg RCC_SAI2ACLKSOURCE_PLL2: SAI2A clock = PLL2

+  *             @arg RCC_SAI2ACLKSOURCE_PLL3: SAI2A clock = PLL3

+  *             @arg RCC_SAI2ACLKSOURCE_CLKP: SAI2A clock  = CLKP

+  *             @arg RCC_SAI2ACLKSOURCE_PIN: SAI2A clock = External Clock

+  *             @arg RCC_SAI2ACLKSOURCE_SPDIF: SAI2A clock = SPDIF Clock

+  * @retval None

+  */

+#define __HAL_RCC_SAI2A_CONFIG(__RCC_SAI2ACLKSource__ )\

+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL, (__RCC_SAI2ACLKSource__))

+

+/** @brief  Macro to get the SAI2A clock source.

+  * @retval The clock source can be one of the following values:

+  *             @arg RCC_SAI2CLKSOURCE_PLL: SAI2A clock = PLL

+  *             @arg RCC_SAI2CLKSOURCE_PLL2: SAI2A clock = PLL2

+  *             @arg RCC_SAI2CLKSOURCE_PLL3: SAI2A clock = PLL3

+  *             @arg RCC_SAI2CLKSOURCE_CLKP: SAI2A clock  = CLKP

+  *             @arg RCC_SAI2CLKSOURCE_PIN: SAI2A clock = External Clock

+  *             @arg RCC_SAI2ACLKSOURCE_SPDIF: SAI2A clock = SPDIF Clock

+  */

+#define __HAL_RCC_GET_SAI2A_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2ASEL)))

+#endif /* defined(RCC_CDCCIP1R_SAI2ASEL) */

+

+#if defined(RCC_CDCCIP1R_SAI2BSEL)

+/**

+  * @brief  Macro to Configure the SAI2B clock source.

+  * @param  __RCC_SAI2BCLKSource__ defines the SAI2B clock source. This clock is derived

+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)

+  *          This parameter can be one of the following values:

+  *             @arg RCC_SAI2BCLKSOURCE_PLL: SAI2B clock = PLL

+  *             @arg RCC_SAI2BCLKSOURCE_PLL2: SAI2B clock = PLL2

+  *             @arg RCC_SAI2BCLKSOURCE_PLL3: SAI2B clock = PLL3

+  *             @arg RCC_SAI2BCLKSOURCE_CLKP: SAI2B clock  = CLKP

+  *             @arg RCC_SAI2BCLKSOURCE_PIN: SAI2B clock = External Clock

+  *             @arg RCC_SAI2BCLKSOURCE_SPDIF: SAI2B clock = SPDIF Clock

+  * @retval None

+  */

+#define __HAL_RCC_SAI2B_CONFIG(__RCC_SAI2BCLKSource__ )\

+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL, (__RCC_SAI2BCLKSource__))

+

+/** @brief  Macro to get the SAI2B clock source.

+  * @retval The clock source can be one of the following values:

+  *             @arg RCC_SAI2BCLKSOURCE_PLL: SAI2B clock = PLL

+  *             @arg RCC_SAI2BCLKSOURCE_PLL2: SAI2B clock = PLL2

+  *             @arg RCC_SAI2BCLKSOURCE_PLL3: SAI2B clock = PLL3

+  *             @arg RCC_SAI2BCLKSOURCE_CLKP: SAI2B clock  = CLKP

+  *             @arg RCC_SAI2BCLKSOURCE_PIN: SAI2B clock = External Clock

+  *             @arg RCC_SAI2BCLKSOURCE_SPDIF: SAI2B clock = SPDIF Clock

+  */

+#define __HAL_RCC_GET_SAI2B_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SAI2BSEL)))

+#endif /* defined(RCC_CDCCIP1R_SAI2BSEL) */

+

+

+#if defined(SAI4_Block_A)

+/**

+  * @brief  Macro to Configure the SAI4A clock source.

+  * @param  __RCC_SAI4ACLKSource__ defines the SAI4A clock source. This clock is derived

+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)

+  *          This parameter can be one of the following values:

+  *             @arg RCC_SAI4ACLKSOURCE_PLL: SAI4A clock = PLL

+  *             @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4A clock = PLL2

+  *             @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4A clock = PLL3

+  *             @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4A clock  = CLKP

+  *             @arg RCC_SAI4ACLKSOURCE_PIN: SAI4A clock = External Clock

+  * @retval None

+  */

+#define __HAL_RCC_SAI4A_CONFIG(__RCC_SAI4ACLKSource__ )\

+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL, (__RCC_SAI4ACLKSource__))

+

+/** @brief  Macro to get the SAI4A clock source.

+  * @retval The clock source can be one of the following values:

+  *             @arg RCC_SAI4ACLKSOURCE_PLL: SAI4B clock = PLL

+  *             @arg RCC_SAI4ACLKSOURCE_PLL2: SAI4B clock = PLL2

+  *             @arg RCC_SAI4ACLKSOURCE_PLL3: SAI4B clock = PLL3

+  *             @arg RCC_SAI4ACLKSOURCE_CLKP: SAI4B clock  = CLKP

+  *             @arg RCC_SAI4ACLKSOURCE_PIN: SAI4B clock = External Clock

+  */

+#define __HAL_RCC_GET_SAI4A_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4ASEL)))

+#endif /* SAI4_Block_A */

+

+#if defined(SAI4_Block_B)

+/**

+  * @brief  Macro to Configure the SAI4B clock source.

+  * @param  __RCC_SAI4BCLKSource__ defines the SAI4B clock source. This clock is derived

+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)

+  *          This parameter can be one of the following values:

+  *             @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL

+  *             @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2

+  *             @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3

+  *             @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock  = CLKP

+  *             @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock

+  * @retval None

+  */

+#define __HAL_RCC_SAI4B_CONFIG(__RCC_SAI4BCLKSource__ )\

+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL, (__RCC_SAI4BCLKSource__))

+

+/** @brief  Macro to get the SAI4B clock source.

+  * @retval The clock source can be one of the following values:

+  *             @arg RCC_SAI4BCLKSOURCE_PLL: SAI4B clock = PLL

+  *             @arg RCC_SAI4BCLKSOURCE_PLL2: SAI4B clock = PLL2

+  *             @arg RCC_SAI4BCLKSOURCE_PLL3: SAI4B clock = PLL3

+  *             @arg RCC_SAI4BCLKSOURCE_CLKP: SAI4B clock  = CLKP

+  *             @arg RCC_SAI4BCLKSOURCE_PIN: SAI4B clock = External Clock

+  */

+#define __HAL_RCC_GET_SAI4B_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SAI4BSEL)))

+#endif /* SAI4_Block_B */

+

+/** @brief macro to configure the I2C1/2/3 clock (I2C123CLK).

+  *

+  * @param  __I2C123CLKSource__ specifies the I2C1/2/3 clock source.

+  *          This parameter can be one of the following values:

+  *            @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3 clock

+  *            @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3 clock

+  *            @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3 clock

+  *            @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3 clock

+  */

+#if defined(RCC_D2CCIP2R_I2C123SEL)

+#define __HAL_RCC_I2C123_CONFIG(__I2C123CLKSource__) \

+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL, (uint32_t)(__I2C123CLKSource__))

+#else

+#define __HAL_RCC_I2C123_CONFIG(__I2C123CLKSource__) \

+                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL, (uint32_t)(__I2C123CLKSource__))

+#endif /* RCC_D2CCIP2R_I2C123SEL */

+

+/** @brief  macro to get the I2C1/2/3 clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_I2C123CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1/2/3 clock

+  *            @arg RCC_I2C123CLKSOURCE_PLL3: PLL3 selected as I2C1/2/3 clock

+  *            @arg RCC_I2C123CLKSOURCE_HSI: HSI selected as I2C1/2/3 clock

+  *            @arg RCC_I2C123CLKSOURCE_CSI: CSI selected as I2C1/2/3 clock

+  */

+#if defined(RCC_D2CCIP2R_I2C123SEL)

+#define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_I2C123SEL)))

+#else

+#define __HAL_RCC_GET_I2C123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_I2C123SEL)))

+#endif /* RCC_D2CCIP2R_I2C123SEL */

+

+/** @brief macro to configure the I2C1 clock (I2C1CLK).

+  *

+  * @param  __I2C1CLKSource__ specifies the I2C1 clock source.

+  *          This parameter can be one of the following values:

+  *            @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock

+  *            @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock

+  *            @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock

+  *            @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock

+  */

+#define __HAL_RCC_I2C1_CONFIG  __HAL_RCC_I2C123_CONFIG

+

+/** @brief  macro to get the I2C1 clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_I2C1CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C1 clock

+  *            @arg RCC_I2C1CLKSOURCE_PLL3: PLL3 selected as I2C1 clock

+  *            @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock

+  *            @arg RCC_I2C1CLKSOURCE_CSI: CSI selected as I2C1 clock

+  */

+#define __HAL_RCC_GET_I2C1_SOURCE __HAL_RCC_GET_I2C123_SOURCE

+

+/** @brief macro to configure the I2C2 clock (I2C2CLK).

+  *

+  * @param  __I2C2CLKSource__ specifies the I2C2 clock source.

+  *          This parameter can be one of the following values:

+  *            @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock

+  *            @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock

+  *            @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock

+  *            @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock

+  */

+#define __HAL_RCC_I2C2_CONFIG __HAL_RCC_I2C123_CONFIG

+

+/** @brief  macro to get the I2C2 clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_I2C2CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C2 clock

+  *            @arg RCC_I2C2CLKSOURCE_PLL3: PLL3 selected as I2C2 clock

+  *            @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock

+  *            @arg RCC_I2C2CLKSOURCE_CSI: CSI selected as I2C2 clock

+  */

+#define __HAL_RCC_GET_I2C2_SOURCE __HAL_RCC_GET_I2C123_SOURCE

+

+/** @brief macro to configure the I2C3 clock (I2C3CLK).

+  *

+  * @param  __I2C3CLKSource__ specifies the I2C3 clock source.

+  *          This parameter can be one of the following values:

+  *            @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock

+  *            @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock

+  *            @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock

+  *            @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock

+  */

+#define __HAL_RCC_I2C3_CONFIG __HAL_RCC_I2C123_CONFIG

+

+/** @brief  macro to get the I2C3 clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_I2C3CLKSOURCE_D2PCLK1: D2PCLK1 selected as I2C3 clock

+  *            @arg RCC_I2C3CLKSOURCE_PLL3: PLL3 selected as I2C3 clock

+  *            @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock

+  *            @arg RCC_I2C3CLKSOURCE_CSI: CSI selected as I2C3 clock

+  */

+#define __HAL_RCC_GET_I2C3_SOURCE __HAL_RCC_GET_I2C123_SOURCE

+

+/** @brief macro to configure the I2C4 clock (I2C4CLK).

+  *

+  * @param  __I2C4CLKSource__ specifies the I2C4 clock source.

+  *          This parameter can be one of the following values:

+  *            @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock

+  *            @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock

+  *            @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock

+  *            @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock

+  */

+#if defined(RCC_D3CCIPR_I2C4SEL)

+#define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \

+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))

+#else

+#define __HAL_RCC_I2C4_CONFIG(__I2C4CLKSource__) \

+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_I2C4SEL, (uint32_t)(__I2C4CLKSource__))

+#endif /* RCC_D3CCIPR_I2C4SEL */

+

+/** @brief  macro to get the I2C4 clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_I2C4CLKSOURCE_D3PCLK1: D3PCLK1 selected as I2C4 clock

+  *            @arg RCC_I2C4CLKSOURCE_PLL3: PLL3 selected as I2C4 clock

+  *            @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock

+  *            @arg RCC_I2C4CLKSOURCE_CSI: CSI selected as I2C4 clock

+  */

+#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_I2C4SEL)))

+

+/** @brief macro to configure the USART1/6/9* /10* clock (USART16CLK).

+  *

+  * @param  __USART16CLKSource__ specifies the USART1/6/9* /10* clock source.

+  *          This parameter can be one of the following values:

+  *            @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock

+  *            @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock

+  *            @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock

+  *            @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock

+  *            @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock

+  *            @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock

+  *

+  * (*) : Available on some STM32H7 lines only.

+  */

+#if defined(RCC_D2CCIP2R_USART16SEL)

+#define __HAL_RCC_USART16_CONFIG(__USART16CLKSource__) \

+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL, (uint32_t)(__USART16CLKSource__))

+#else

+#define __HAL_RCC_USART16910_CONFIG(__USART16910CLKSource__) \

+                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL, (uint32_t)(__USART16910CLKSource__))

+/* alias */

+#define __HAL_RCC_USART16_CONFIG  __HAL_RCC_USART16910_CONFIG

+#endif /* RCC_D2CCIP2R_USART16SEL */

+

+/** @brief  macro to get the USART1/6/9* /10* clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_USART16CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1/6/9* /10* clock

+  *            @arg RCC_USART16CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1/6/9* /10* clock

+  *            @arg RCC_USART16CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1/6/9* /10* clock

+  *            @arg RCC_USART16CLKSOURCE_HSI: HSI selected as USART1/6/9* /10* clock

+  *            @arg RCC_USART16CLKSOURCE_CSI: CSI Clock selected as USART1/6/9* /10* clock

+  *            @arg RCC_USART16CLKSOURCE_LSE: LSE selected as USART1/6/9* /10* clock

+  *

+  * (*) : Available on some STM32H7 lines only.

+  */

+#if defined(RCC_D2CCIP2R_USART16SEL)

+#define __HAL_RCC_GET_USART16_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART16SEL)))

+#else

+#define __HAL_RCC_GET_USART16910_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART16910SEL)))

+/* alias*/

+#define  __HAL_RCC_GET_USART16_SOURCE  __HAL_RCC_GET_USART16910_SOURCE

+#endif /* RCC_D2CCIP2R_USART16SEL */

+

+/** @brief macro to configure the USART234578 clock (USART234578CLK).

+  *

+  * @param  __USART234578CLKSource__ specifies the USART2/3/4/5/7/8 clock source.

+  *          This parameter can be one of the following values:

+  *            @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock

+  *            @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock

+  *            @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock

+  *            @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock

+  *            @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock

+  *            @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock

+  */

+#if defined(RCC_D2CCIP2R_USART28SEL)

+#define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \

+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL, (uint32_t)(__USART234578CLKSource__))

+#else

+#define __HAL_RCC_USART234578_CONFIG(__USART234578CLKSource__) \

+                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL, (uint32_t)(__USART234578CLKSource__))

+#endif /* RCC_D2CCIP2R_USART28SEL */

+

+/** @brief  macro to get the USART2/3/4/5/7/8 clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_USART234578CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2/3/4/5/7/8 clock

+  *            @arg RCC_USART234578CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2/3/4/5/7/8 clock

+  *            @arg RCC_USART234578CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2/3/4/5/7/8 clock

+  *            @arg RCC_USART234578CLKSOURCE_HSI: HSI selected as USART2/3/4/5/7/8 clock

+  *            @arg RCC_USART234578CLKSOURCE_CSI: CSI Clock selected as USART2/3/4/5/7/8 clock

+  *            @arg RCC_USART234578CLKSOURCE_LSE: LSE selected as USART2/3/4/5/7/8 clock

+  */

+#if defined(RCC_D2CCIP2R_USART28SEL)

+#define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USART28SEL)))

+#else

+#define __HAL_RCC_GET_USART234578_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USART234578SEL)))

+#endif /* RCC_D2CCIP2R_USART28SEL */

+

+/** @brief macro to configure the USART1 clock (USART1CLK).

+  *

+  * @param  __USART1CLKSource__ specifies the USART1 clock source.

+  *          This parameter can be one of the following values:

+  *            @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock

+  *            @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock

+  *            @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock

+  *            @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock

+  *            @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock

+  *            @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock

+  */

+#define __HAL_RCC_USART1_CONFIG  __HAL_RCC_USART16_CONFIG

+

+/** @brief  macro to get the USART1 clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_USART1CLKSOURCE_D2PCLK2: APB2 Clock selected as USART1 clock

+  *            @arg RCC_USART1CLKSOURCE_PLL2: PLL2_Q Clock selected as USART1 clock

+  *            @arg RCC_USART1CLKSOURCE_PLL3: PLL3_Q Clock selected as USART1 clock

+  *            @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock

+  *            @arg RCC_USART1CLKSOURCE_CSI: CSI Clock selected as USART1 clock

+  *            @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock

+  */

+#define __HAL_RCC_GET_USART1_SOURCE  __HAL_RCC_GET_USART16_SOURCE

+

+/** @brief macro to configure the USART2 clock (USART2CLK).

+  *

+  * @param  __USART2CLKSource__ specifies the USART2 clock source.

+  *          This parameter can be one of the following values:

+  *            @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock

+  *            @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock

+  *            @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock

+  *            @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock

+  *            @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock

+  *            @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock

+  */

+#define __HAL_RCC_USART2_CONFIG  __HAL_RCC_USART234578_CONFIG

+

+/** @brief  macro to get the USART2 clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART2 clock

+  *            @arg RCC_USART2CLKSOURCE_PLL2: PLL2_Q Clock selected as USART2 clock

+  *            @arg RCC_USART2CLKSOURCE_PLL3: PLL3_Q Clock selected as USART2 clock

+  *            @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock

+  *            @arg RCC_USART2CLKSOURCE_CSI: CSI Clock selected as USART2 clock

+  *            @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock

+  */

+#define __HAL_RCC_GET_USART2_SOURCE __HAL_RCC_GET_USART234578_SOURCE

+

+/** @brief macro to configure the USART3 clock (USART3CLK).

+  *

+  * @param  __USART3CLKSource__ specifies the USART3 clock source.

+  *          This parameter can be one of the following values:

+  *            @arg RCC_USART3CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock

+  *            @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock

+  *            @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock

+  *            @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock

+  *            @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock

+  *            @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock

+  */

+#define __HAL_RCC_USART3_CONFIG  __HAL_RCC_USART234578_CONFIG

+

+/** @brief  macro to get the USART3 clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_USART2CLKSOURCE_D2PCLK1: APB1 Clock selected as USART3 clock

+  *            @arg RCC_USART3CLKSOURCE_PLL2: PLL2_Q Clock selected as USART3 clock

+  *            @arg RCC_USART3CLKSOURCE_PLL3: PLL3_Q Clock selected as USART3 clock

+  *            @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock

+  *            @arg RCC_USART3CLKSOURCE_CSI: CSI Clock selected as USART3 clock

+  *            @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock

+  */

+#define __HAL_RCC_GET_USART3_SOURCE  __HAL_RCC_GET_USART234578_SOURCE

+

+/** @brief macro to configure the UART4 clock (UART4CLK).

+  *

+  * @param  __UART4CLKSource__ specifies the UART4 clock source.

+  *          This parameter can be one of the following values:

+  *            @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock

+  *            @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock

+  *            @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock

+  *            @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock

+  *            @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock

+  *            @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock

+  */

+#define __HAL_RCC_UART4_CONFIG  __HAL_RCC_USART234578_CONFIG

+

+/** @brief  macro to get the UART4 clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_UART4CLKSOURCE_D2PCLK1: APB1 Clock selected as UART4 clock

+  *            @arg RCC_UART4CLKSOURCE_PLL2: PLL2_Q Clock selected as UART4 clock

+  *            @arg RCC_UART4CLKSOURCE_PLL3: PLL3_Q Clock selected as UART4 clock

+  *            @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock

+  *            @arg RCC_UART4CLKSOURCE_CSI: CSI Clock selected as UART4 clock

+  *            @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock

+  */

+#define __HAL_RCC_GET_UART4_SOURCE  __HAL_RCC_GET_USART234578_SOURCE

+

+/** @brief macro to configure the UART5 clock (UART5CLK).

+  *

+  * @param  __UART5CLKSource__ specifies the UART5 clock source.

+  *          This parameter can be one of the following values:

+  *            @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock

+  *            @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock

+  *            @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock

+  *            @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock

+  *            @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock

+  *            @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock

+  */

+#define __HAL_RCC_UART5_CONFIG  __HAL_RCC_USART234578_CONFIG

+

+/** @brief  macro to get the UART5 clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_UART5CLKSOURCE_D2PCLK1: APB1 Clock selected as UART5 clock

+  *            @arg RCC_UART5CLKSOURCE_PLL2: PLL2_Q Clock selected as UART5 clock

+  *            @arg RCC_UART5CLKSOURCE_PLL3: PLL3_Q Clock selected as UART5 clock

+  *            @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock

+  *            @arg RCC_UART5CLKSOURCE_CSI: CSI Clock selected as UART5 clock

+  *            @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock

+  */

+#define __HAL_RCC_GET_UART5_SOURCE  __HAL_RCC_GET_USART234578_SOURCE

+

+/** @brief macro to configure the USART6 clock (USART6CLK).

+  *

+  * @param  __USART6CLKSource__ specifies the USART6 clock source.

+  *          This parameter can be one of the following values:

+  *            @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock

+  *            @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock

+  *            @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock

+  *            @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock

+  *            @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock

+  *            @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock

+  */

+#define __HAL_RCC_USART6_CONFIG  __HAL_RCC_USART16_CONFIG

+

+/** @brief  macro to get the USART6 clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_USART6CLKSOURCE_D2PCLK2: APB2 Clock selected as USART6 clock

+  *            @arg RCC_USART6CLKSOURCE_PLL2: PLL2_Q Clock selected as USART6 clock

+  *            @arg RCC_USART6CLKSOURCE_PLL3: PLL3_Q Clock selected as USART6 clock

+  *            @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock

+  *            @arg RCC_USART6CLKSOURCE_CSI: CSI Clock selected as USART6 clock

+  *            @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock

+  */

+#define __HAL_RCC_GET_USART6_SOURCE  __HAL_RCC_GET_USART16_SOURCE

+

+/** @brief macro to configure the UART5 clock (UART7CLK).

+  *

+  * @param  __UART7CLKSource__ specifies the UART7 clock source.

+  *          This parameter can be one of the following values:

+  *            @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock

+  *            @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock

+  *            @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock

+  *            @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock

+  *            @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock

+  *            @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock

+  */

+#define __HAL_RCC_UART7_CONFIG  __HAL_RCC_USART234578_CONFIG

+

+/** @brief  macro to get the UART7 clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_UART7CLKSOURCE_D2PCLK1: APB1 Clock selected as UART7 clock

+  *            @arg RCC_UART7CLKSOURCE_PLL2: PLL2_Q Clock selected as UART7 clock

+  *            @arg RCC_UART7CLKSOURCE_PLL3: PLL3_Q Clock selected as UART7 clock

+  *            @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock

+  *            @arg RCC_UART7CLKSOURCE_CSI: CSI Clock selected as UART7 clock

+  *            @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock

+  */

+#define __HAL_RCC_GET_UART7_SOURCE  __HAL_RCC_GET_USART234578_SOURCE

+

+/** @brief macro to configure the UART8 clock (UART8CLK).

+  *

+  * @param  __UART8CLKSource__ specifies the UART8 clock source.

+  *          This parameter can be one of the following values:

+  *            @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock

+  *            @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock

+  *            @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock

+  *            @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock

+  *            @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock

+  *            @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock

+  */

+#define __HAL_RCC_UART8_CONFIG  __HAL_RCC_USART234578_CONFIG

+

+/** @brief  macro to get the UART8 clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_UART8CLKSOURCE_D2PCLK1: APB1 Clock selected as UART8 clock

+  *            @arg RCC_UART8CLKSOURCE_PLL2: PLL2_Q Clock selected as UART8 clock

+  *            @arg RCC_UART8CLKSOURCE_PLL3: PLL3_Q Clock selected as UART8 clock

+  *            @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock

+  *            @arg RCC_UART8CLKSOURCE_CSI: CSI Clock selected as UART8 clock

+  *            @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock

+  */

+#define __HAL_RCC_GET_UART8_SOURCE  __HAL_RCC_GET_USART234578_SOURCE

+

+#if defined(UART9)

+/** @brief macro to configure the UART9 clock (UART9CLK).

+  *

+  * @param  __UART8CLKSource__ specifies the UART8 clock source.

+  *          This parameter can be one of the following values:

+  *            @arg RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART9 clock

+  *            @arg RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART9 clock

+  *            @arg RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART9 clock

+  *            @arg RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock

+  *            @arg RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock

+  *            @arg RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock

+  */

+#define __HAL_RCC_UART9_CONFIG  __HAL_RCC_USART16_CONFIG

+

+/** @brief  macro to get the UART9 clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_UART9CLKSOURCE_D2PCLK1: APB1 Clock selected as UART99 clock

+  *            @arg RCC_UART9CLKSOURCE_PLL2: PLL2_Q Clock selected as UART99 clock

+  *            @arg RCC_UART9CLKSOURCE_PLL3: PLL3_Q Clock selected as UART99 clock

+  *            @arg RCC_UART9CLKSOURCE_HSI: HSI selected as UART9 clock

+  *            @arg RCC_UART9CLKSOURCE_CSI: CSI Clock selected as UART9 clock

+  *            @arg RCC_UART9CLKSOURCE_LSE: LSE selected as UART9 clock

+  */

+#define __HAL_RCC_GET_UART9_SOURCE  __HAL_RCC_GET_USART16_SOURCE

+#endif /* UART9 */

+

+#if defined(USART10)

+/** @brief macro to configure the USART10 clock (USART10CLK).

+  *

+  * @param  __UART8CLKSource__ specifies the UART8 clock source.

+  *          This parameter can be one of the following values:

+  *            @arg RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock

+  *            @arg RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock

+  *            @arg RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock

+  *            @arg RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock

+  *            @arg RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock

+  *            @arg RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock

+  */

+#define __HAL_RCC_USART10_CONFIG  __HAL_RCC_USART16_CONFIG

+

+/** @brief  macro to get the USART10 clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_USART10CLKSOURCE_D2PCLK1: APB1 Clock selected as USART10 clock

+  *            @arg RCC_USART10CLKSOURCE_PLL2: PLL2_Q Clock selected as USART10 clock

+  *            @arg RCC_USART10CLKSOURCE_PLL3: PLL3_Q Clock selected as USART10 clock

+  *            @arg RCC_USART10CLKSOURCE_HSI: HSI selected as USART10 clock

+  *            @arg RCC_USART10CLKSOURCE_CSI: CSI Clock selected as USART10 clock

+  *            @arg RCC_USART10CLKSOURCE_LSE: LSE selected as USART10 clock

+  */

+#define __HAL_RCC_GET_USART10_SOURCE  __HAL_RCC_GET_USART16_SOURCE

+#endif /* USART10 */

+

+/** @brief macro to configure the LPUART1 clock (LPUART1CLK).

+  *

+  * @param  __LPUART1CLKSource__ specifies the LPUART1 clock source.

+  *          This parameter can be one of the following values:

+  *            @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock

+  *            @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock

+  *            @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock

+  *            @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock

+  *            @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock

+  *            @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock

+  */

+#if defined (RCC_D3CCIPR_LPUART1SEL)

+#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \

+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))

+#else

+#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \

+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))

+#endif /* RCC_D3CCIPR_LPUART1SEL */

+

+/** @brief  macro to get the LPUART1 clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_LPUART1CLKSOURCE_D3PCLK1: APB4 Clock selected as LPUART1 clock

+  *            @arg RCC_LPUART1CLKSOURCE_PLL2: PLL2_Q Clock selected as LPUART1 clock

+  *            @arg RCC_LPUART1CLKSOURCE_PLL3: PLL3_Q Clock selected as LPUART1 clock

+  *            @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock

+  *            @arg RCC_LPUART1CLKSOURCE_CSI: CSI Clock selected as LPUART1 clock

+  *            @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock

+  */

+#if defined (RCC_D3CCIPR_LPUART1SEL)

+#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL)))

+#else

+#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL)))

+#endif /* RCC_D3CCIPR_LPUART1SEL */

+

+/** @brief  macro to configure the LPTIM1 clock source.

+  *

+  * @param  __LPTIM1CLKSource__ specifies the LPTIM1 clock source.

+  *          This parameter can be one of the following values:

+  *            @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock

+  *            @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock

+  *            @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock

+  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock

+  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock

+  *            @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock

+  */

+#if defined(RCC_D2CCIP2R_LPTIM1SEL)

+#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \

+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))

+#else

+#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \

+                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))

+#endif /* RCC_D2CCIP2R_LPTIM1SEL */

+

+/** @brief  macro to get the LPTIM1 clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_LPTIM1CLKSOURCE_D2PCLK1: APB1 Clock selected as LPTIM1 clock

+  *            @arg RCC_LPTIM1CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM1 clock

+  *            @arg RCC_LPTIM1CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM1 clock

+  *            @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock

+  *            @arg RCC_LPTIM1CLKSOURCE_LSI: LSI Clock selected as LPTIM1 clock

+  *            @arg RCC_LPTIM1CLKSOURCE_CLKP: CLKP selected as LPTIM1 clock

+  */

+#if defined(RCC_D2CCIP2R_LPTIM1SEL)

+#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_LPTIM1SEL)))

+#else

+#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_LPTIM1SEL)))

+#endif /* RCC_D2CCIP2R_LPTIM1SEL */

+

+/** @brief  macro to configure the LPTIM2 clock source.

+  *

+  * @param  __LPTIM2CLKSource__ specifies the LPTIM2 clock source.

+  *          This parameter can be one of the following values:

+  *            @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock

+  *            @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock

+  *            @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock

+  *            @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock

+  *            @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock

+  *            @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock

+  */

+#if defined(RCC_D3CCIPR_LPTIM2SEL)

+#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \

+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))

+#else

+#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2CLKSource__) \

+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL, (uint32_t)(__LPTIM2CLKSource__))

+#endif /* RCC_D3CCIPR_LPTIM2SEL */

+

+/** @brief  macro to get the LPTIM2 clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_LPTIM2CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM2 clock

+  *            @arg RCC_LPTIM2CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM2 clock

+  *            @arg RCC_LPTIM2CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM2 clock

+  *            @arg RCC_LPTIM2CLKSOURCE_LSE: LSE selected as LPTIM2 clock

+  *            @arg RCC_LPTIM2CLKSOURCE_LSI: LSI Clock selected as LPTIM2 clock

+  *            @arg RCC_LPTIM2CLKSOURCE_CLKP: CLKP selected as LPTIM2 clock

+  */

+#if defined(RCC_D3CCIPR_LPTIM2SEL)

+#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM2SEL)))

+#else

+#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM2SEL)))

+#endif /* RCC_D3CCIPR_LPTIM2SEL */

+

+/** @brief  macro to configure the LPTIM3/4/5 clock source.

+  *

+  * @param  __LPTIM345CLKSource__ specifies the LPTIM3/4/5 clock source.

+  *            @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock

+  *            @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock

+  *            @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock

+  *            @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock

+  *            @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock

+  *            @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock

+  */

+#if defined(RCC_D3CCIPR_LPTIM345SEL)

+#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM345CLKSource__) \

+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL, (uint32_t)(__LPTIM345CLKSource__))

+#else

+#define __HAL_RCC_LPTIM345_CONFIG(__LPTIM3CLKSource__) \

+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL, (uint32_t)(__LPTIM3CLKSource__))

+#endif /* RCC_D3CCIPR_LPTIM345SEL */

+

+/** @brief  macro to get the LPTIM3/4/5 clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_LPTIM345CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3/4/5 clock

+  *            @arg RCC_LPTIM345CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3/4/5 clock

+  *            @arg RCC_LPTIM345CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3/4/5 clock

+  *            @arg RCC_LPTIM345CLKSOURCE_LSE: LSE selected as LPTIM3/4/5 clock

+  *            @arg RCC_LPTIM345CLKSOURCE_LSI: LSI Clock selected as LPTIM3/4/5 clock

+  *            @arg RCC_LPTIM345CLKSOURCE_CLKP: CLKP selected as LPTIM3/4/5 clock

+  */

+#if defined(RCC_D3CCIPR_LPTIM345SEL)

+#define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPTIM345SEL)))

+#else

+#define __HAL_RCC_GET_LPTIM345_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPTIM3SEL)))

+#endif /* RCC_D3CCIPR_LPTIM345SEL */

+

+/** @brief  macro to configure the LPTIM3 clock source.

+  *

+  * @param  __LPTIM3CLKSource__ specifies the LPTIM3 clock source.

+  *            @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock

+  *            @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock

+  *            @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock

+  *            @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock

+  *            @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock

+  *            @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock

+  */

+#define __HAL_RCC_LPTIM3_CONFIG  __HAL_RCC_LPTIM345_CONFIG

+

+/** @brief  macro to get the LPTIM3 clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_LPTIM3CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM3 clock

+  *            @arg RCC_LPTIM3CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM3 clock

+  *            @arg RCC_LPTIM3CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM3 clock

+  *            @arg RCC_LPTIM3CLKSOURCE_LSE: LSE selected as LPTIM3 clock

+  *            @arg RCC_LPTIM3CLKSOURCE_LSI: LSI Clock selected as LPTIM3 clock

+  *            @arg RCC_LPTIM3CLKSOURCE_CLKP: CLKP selected as LPTIM3 clock

+  */

+#define __HAL_RCC_GET_LPTIM3_SOURCE  __HAL_RCC_GET_LPTIM345_SOURCE

+

+#if defined(LPTIM4)

+/** @brief  macro to configure the LPTIM4 clock source.

+  *

+  * @param  __LPTIM4CLKSource__ specifies the LPTIM4 clock source.

+  *            @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock

+  *            @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock

+  *            @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock

+  *            @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock

+  *            @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock

+  *            @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock

+  */

+#define __HAL_RCC_LPTIM4_CONFIG  __HAL_RCC_LPTIM345_CONFIG

+

+

+/** @brief  macro to get the LPTIM4 clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_LPTIM4CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM4 clock

+  *            @arg RCC_LPTIM4CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM4 clock

+  *            @arg RCC_LPTIM4CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM4 clock

+  *            @arg RCC_LPTIM4CLKSOURCE_LSE: LSE selected as LPTIM4 clock

+  *            @arg RCC_LPTIM4CLKSOURCE_LSI: LSI Clock selected as LPTIM4 clock

+  *            @arg RCC_LPTIM4CLKSOURCE_CLKP: CLKP selected as LPTIM4 clock

+  */

+#define __HAL_RCC_GET_LPTIM4_SOURCE  __HAL_RCC_GET_LPTIM345_SOURCE

+#endif /* LPTIM4 */

+

+#if defined(LPTIM5)

+/** @brief  macro to configure the LPTIM5 clock source.

+  *

+  * @param  __LPTIM5CLKSource__ specifies the LPTIM5 clock source.

+  *            @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock

+  *            @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock

+  *            @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock

+  *            @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock

+  *            @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock

+  *            @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock

+  */

+#define __HAL_RCC_LPTIM5_CONFIG  __HAL_RCC_LPTIM345_CONFIG

+

+

+/** @brief  macro to get the LPTIM5 clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_LPTIM5CLKSOURCE_D3PCLK1: APB4 Clock selected as LPTIM5 clock

+  *            @arg RCC_LPTIM5CLKSOURCE_PLL2: PLL2_P Clock selected as LPTIM5 clock

+  *            @arg RCC_LPTIM5CLKSOURCE_PLL3: PLL3_R Clock selected as LPTIM5 clock

+  *            @arg RCC_LPTIM5CLKSOURCE_LSE: LSE selected as LPTIM5 clock

+  *            @arg RCC_LPTIM5CLKSOURCE_LSI: LSI Clock selected as LPTIM5 clock

+  *            @arg RCC_LPTIM5CLKSOURCE_CLKP: CLKP selected as LPTIM5 clock

+  */

+#define __HAL_RCC_GET_LPTIM5_SOURCE  __HAL_RCC_GET_LPTIM345_SOURCE

+#endif /* LPTIM5 */

+

+#if defined(QUADSPI)

+/** @brief  macro to configure the QSPI clock source.

+  *

+  * @param  __QSPICLKSource__ specifies the QSPI clock source.

+  *            @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock

+  *            @arg RCC_RCC_QSPICLKSOURCE_PLL   : PLL1_Q Clock selected as QSPI clock

+  *            @arg RCC_RCC_QSPICLKSOURCE_PLL2  : PLL2_R Clock selected as QSPI clock

+  *            @arg RCC_RCC_QSPICLKSOURCE_CLKP    CLKP selected as QSPI clock

+  */

+#define __HAL_RCC_QSPI_CONFIG(__QSPICLKSource__) \

+                  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, (uint32_t)(__QSPICLKSource__))

+

+

+/** @brief  macro to get the QSPI clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_RCC_QSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as QSPI clock

+  *            @arg RCC_RCC_QSPICLKSOURCE_PLL   : PLL1_Q Clock selected as QSPI clock

+  *            @arg RCC_RCC_QSPICLKSOURCE_PLL2  : PLL2_R Clock selected as QSPI clock

+  *            @arg RCC_RCC_QSPICLKSOURCE_CLKP    CLKP selected as QSPI clock

+  */

+#define __HAL_RCC_GET_QSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL)))

+#endif /* QUADSPI */

+

+#if defined(OCTOSPI1) || defined(OCTOSPI2)

+/** @brief  macro to configure the OSPI clock source.

+  *

+  * @param  __OSPICLKSource__ specifies the OSPI clock source.

+  *            @arg RCC_RCC_OSPICLKSOURCE_CDHCLK: Domain1 HCLK Clock selected as OSPI clock

+  *            @arg RCC_RCC_OSPICLKSOURCE_PLL   : PLL1_Q Clock selected as OSPI clock

+  *            @arg RCC_RCC_OSPICLKSOURCE_PLL2  : PLL2_R Clock selected as OSPI clock

+  *            @arg RCC_RCC_OSPICLKSOURCE_CLKP    CLKP selected as OSPI clock

+  */

+#define __HAL_RCC_OSPI_CONFIG(__OSPICLKSource__) \

+                  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, (uint32_t)(__OSPICLKSource__))

+

+

+/** @brief  macro to get the OSPI clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_RCC_OSPICLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as OSPI clock

+  *            @arg RCC_RCC_OSPICLKSOURCE_PLL   : PLL1_Q Clock selected as OSPI clock

+  *            @arg RCC_RCC_OSPICLKSOURCE_PLL2  : PLL2_R Clock selected as OSPI clock

+  *            @arg RCC_RCC_OSPICLKSOURCE_CLKP    CLKP selected as OSPI clock

+  */

+#define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL)))

+#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */

+

+

+#if defined(DSI)

+/** @brief  macro to configure the DSI clock source.

+  *

+  * @param  __DSICLKSource__ specifies the DSI clock source.

+  *            @arg RCC_RCC_DSICLKSOURCE_PHY:DSI clock from PHY is selected as DSI byte lane clock

+  *            @arg RCC_RCC_DSICLKSOURCE_PLL2   : PLL2_Q Clock clock is selected as DSI byte lane clock

+  */

+#define __HAL_RCC_DSI_CONFIG(__DSICLKSource__) \

+                  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, (uint32_t)(__DSICLKSource__))

+

+

+/** @brief  macro to get the DSI clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_RCC_DSICLKSOURCE_PHY: DSI clock from PHY is selected as DSI byte lane clock

+  *            @arg RCC_RCC_DSICLKSOURCE_PLL2: PLL2_Q Clock clock is selected as DSI byte lane clock

+  */

+#define __HAL_RCC_GET_DSI_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL)))

+#endif /*DSI*/

+

+/** @brief  macro to configure the FMC clock source.

+  *

+  * @param  __FMCCLKSource__ specifies the FMC clock source.

+  *            @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock

+  *            @arg RCC_RCC_FMCCLKSOURCE_PLL   : PLL1_Q Clock selected as FMC clock

+  *            @arg RCC_RCC_FMCCLKSOURCE_PLL2  : PLL2_R Clock selected as FMC clock

+  *            @arg RCC_RCC_FMCCLKSOURCE_CLKP    CLKP selected as FMC clock

+  */

+#if defined(RCC_D1CCIPR_FMCSEL)

+#define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \

+                  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))

+#else

+#define __HAL_RCC_FMC_CONFIG(__FMCCLKSource__) \

+                  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, (uint32_t)(__FMCCLKSource__))

+#endif /* RCC_D1CCIPR_FMCSEL */

+

+/** @brief  macro to get the FMC clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_RCC_FMCCLKSOURCE_D1HCLK: Domain1 HCLK Clock selected as FMC clock

+  *            @arg RCC_RCC_FMCCLKSOURCE_PLL   : PLL1_Q Clock selected as FMC clock

+  *            @arg RCC_RCC_FMCCLKSOURCE_PLL2  : PLL2_R Clock selected as FMC clock

+  *            @arg RCC_RCC_FMCCLKSOURCE_CLKP    CLKP selected as FMC clock

+  */

+#if defined(RCC_D1CCIPR_FMCSEL)

+#define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL)))

+#else

+#define __HAL_RCC_GET_FMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL)))

+#endif /* RCC_D1CCIPR_FMCSEL */

+

+/** @brief  Macro to configure the USB clock (USBCLK).

+  * @param  __USBCLKSource__ specifies the USB clock source.

+  *         This parameter can be one of the following values:

+  *            @arg RCC_USBCLKSOURCE_PLL:   PLL1Q selected as USB clock

+  *            @arg RCC_USBCLKSOURCE_PLL3:  PLL3Q Clock selected as USB clock

+  *            @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock

+  */

+#if defined(RCC_D2CCIP2R_USBSEL)

+#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \

+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))

+#else

+#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \

+                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, (uint32_t)(__USBCLKSource__))

+#endif /* RCC_D2CCIP2R_USBSEL */

+

+/** @brief  Macro to get the USB clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_USBCLKSOURCE_PLL:   PLL1Q selected as USB clock

+  *            @arg RCC_USBCLKSOURCE_PLL3:  PLL3Q Clock selected as USB clock

+  *            @arg RCC_USBCLKSOURCE_HSI48: RC48 MHZ Clock selected as USB clock

+  */

+#if defined(RCC_D2CCIP2R_USBSEL)

+#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL)))

+#else

+#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL)))

+#endif /* RCC_D2CCIP2R_USBSEL */

+

+/** @brief  Macro to configure the ADC clock

+  * @param  __ADCCLKSource__ specifies the ADC digital interface clock source.

+  *         This parameter can be one of the following values:

+  *            @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock

+  *            @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock

+  *            @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock

+  */

+#if defined(RCC_D3CCIPR_ADCSEL)

+#define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \

+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))

+#else

+#define __HAL_RCC_ADC_CONFIG(__ADCCLKSource__) \

+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, (uint32_t)(__ADCCLKSource__))

+#endif /* RCC_D3CCIPR_ADCSEL */

+

+/** @brief  Macro to get the ADC clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_ADCCLKSOURCE_PLL2: PLL2_P Clock selected as ADC clock

+  *            @arg RCC_ADCCLKSOURCE_PLL3: PLL3_R Clock selected as ADC clock

+  *            @arg RCC_ADCCLKSOURCE_CLKP: CLKP Clock selected as ADC clock

+  */

+#if defined(RCC_D3CCIPR_ADCSEL)

+#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL)))

+#else

+#define __HAL_RCC_GET_ADC_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL)))

+#endif /* RCC_D3CCIPR_ADCSEL */

+

+ /** @brief  Macro to configure the SWPMI1 clock

+  * @param  __SWPMI1CLKSource__ specifies the SWPMI1  clock source.

+  *         This parameter can be one of the following values:

+  *            @arg RCC_SWPMI1CLKSOURCE_D2PCLK1:  D2PCLK1 Clock selected as SWPMI1 clock

+  *            @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock

+  */

+#if defined(RCC_D2CCIP1R_SWPSEL)

+#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \

+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))

+#else

+#define __HAL_RCC_SWPMI1_CONFIG(__SWPMI1CLKSource__) \

+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, (uint32_t)(__SWPMI1CLKSource__))

+#endif /* RCC_D2CCIP1R_SWPSEL */

+

+/** @brief  Macro to get the SWPMI1 clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_SWPMI1CLKSOURCE_D2PCLK1:  D2PCLK1 Clock selected as SWPMI1 clock

+  *            @arg RCC_SWPMI1CLKSOURCE_HSI: HSI Clock selected as SWPMI1 clock

+  */

+#if defined(RCC_D2CCIP1R_SWPSEL)

+#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL)))

+#else

+#define __HAL_RCC_GET_SWPMI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL)))

+#endif /* RCC_D2CCIP1R_SWPSEL */

+

+ /** @brief  Macro to configure the DFSDM1 clock

+  * @param  __DFSDM1CLKSource__ specifies the DFSDM1  clock source.

+  *         This parameter can be one of the following values:

+  *            @arg RCC_DFSDM1CLKSOURCE_D2PCLK:  D2PCLK Clock selected as DFSDM1 clock

+  *            @arg RCC_DFSDM1CLKSOURCE_SYS:     System Clock selected as DFSDM1 clock

+  */

+#if defined(RCC_D2CCIP1R_DFSDM1SEL)

+#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \

+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))

+#else

+#define __HAL_RCC_DFSDM1_CONFIG(__DFSDM1CLKSource__) \

+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, (uint32_t)(__DFSDM1CLKSource__))

+#endif /* RCC_D2CCIP1R_DFSDM1SEL */

+

+/** @brief  Macro to get the DFSDM1 clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_DFSDM1CLKSOURCE_D2PCLK:  D2PCLK Clock selected as DFSDM1 clock

+  *            @arg RCC_DFSDM1CLKSOURCE_SYS:   System Clock selected as DFSDM1 clock

+  */

+#if defined (RCC_D2CCIP1R_DFSDM1SEL)

+#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL)))

+#else

+#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL)))

+#endif /* RCC_D2CCIP1R_DFSDM1SEL */

+

+#if defined(DFSDM2_BASE)

+ /** @brief  Macro to configure the DFSDM2 clock

+  * @param  __DFSDM2CLKSource__ specifies the DFSDM2  clock source.

+  *         This parameter can be one of the following values:

+  *            @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1:  SRDPCLK1 (APB4) selected as DFSDM2 clock

+  *            @arg RCC_DFSDM2CLKSOURCE_SYS:   System Clock selected as DFSDM2 clock

+  */

+#define __HAL_RCC_DFSDM2_CONFIG(__DFSDM2CLKSource__) \

+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, (uint32_t)(__DFSDM2CLKSource__))

+

+/** @brief  Macro to get the DFSDM2 clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_DFSDM2CLKSOURCE_SRDPCLK1:  SRDPCLK1 (APB4) Clock selected as DFSDM2 clock

+  *            @arg RCC_DFSDM2CLKSOURCE_SYS:   System Clock selected as DFSDM2 clock

+  */

+#define __HAL_RCC_GET_DFSDM2_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL)))

+#endif /* DFSDM2 */

+

+/** @brief macro to configure the CEC clock (CECCLK).

+  *

+  * @param  __CECCLKSource__ specifies the CEC clock source.

+  *          This parameter can be one of the following values:

+  *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock

+  *            @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock

+  *            @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock

+  */

+#if defined(RCC_D2CCIP2R_CECSEL)

+#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \

+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))

+#else

+#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \

+                  MODIFY_REG(RCC->D2CCIP2R, RCC_CDCCIP2R_CECSEL, (uint32_t)(__CECCLKSource__))

+#endif /* RCC_D2CCIP2R_CECSEL */

+

+/** @brief  macro to get the CEC clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock

+  *            @arg RCC_CECCLKSOURCE_LSI: LSI selected as CEC clock

+  *            @arg RCC_CECCLKSOURCE_CSI: CSI Clock selected as CEC clock

+  */

+#if defined(RCC_D2CCIP2R_CECSEL)

+#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL)))

+#else

+#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL)))

+#endif /* RCC_D2CCIP2R_CECSEL */

+

+/** @brief  Macro to configure the CLKP : Oscillator clock for peripheral

+  * @param  __CLKPSource__ specifies Oscillator clock for peripheral

+  *         This parameter can be one of the following values:

+  *            @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral

+  *            @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral

+  *            @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral

+  */

+#if defined(RCC_D1CCIPR_CKPERSEL)

+#define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \

+                  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))

+#else

+#define __HAL_RCC_CLKP_CONFIG(__CLKPSource__) \

+                  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, (uint32_t)(__CLKPSource__))

+#endif /* RCC_D1CCIPR_CKPERSEL */

+

+/** @brief  Macro to get the Oscillator clock for peripheral  source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_CLKPSOURCE_HSI: HSI selected Oscillator clock for peripheral

+  *            @arg RCC_CLKPSOURCE_CSI: CSI selected Oscillator clock for peripheral

+  *            @arg RCC_CLKPSOURCE_HSE: HSE selected Oscillator clock for peripheral

+  */

+#if defined(RCC_D1CCIPR_CKPERSEL)

+#define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL)))

+#else

+#define __HAL_RCC_GET_CLKP_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL)))

+#endif /* RCC_D1CCIPR_CKPERSEL */

+

+#if defined(FDCAN1) || defined(FDCAN2)

+/** @brief  Macro to configure the FDCAN clock

+  * @param  __FDCANCLKSource__ specifies  clock source  for FDCAN

+  *         This parameter can be one of the following values:

+  *            @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock

+  *            @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock

+  *            @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock

+  */

+#if defined(RCC_D2CCIP1R_FDCANSEL)

+#define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \

+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))

+#else

+#define __HAL_RCC_FDCAN_CONFIG(__FDCANCLKSource__) \

+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, (uint32_t)(__FDCANCLKSource__))

+#endif /* RCC_D2CCIP1R_FDCANSEL */

+

+/** @brief  Macro to get the FDCAN clock

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_FDCANCLKSOURCE_HSE: HSE selected as FDCAN clock

+  *            @arg RCC_FDCANCLKSOURCE_PLL: PLL selected as FDCAN clock

+  *            @arg RCC_FDCANCLKSOURCE_PLL2: PLL2 selected as FDCAN clock

+  */

+#if defined(RCC_D2CCIP1R_FDCANSEL)

+#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL)))

+#else

+#define __HAL_RCC_GET_FDCAN_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL)))

+#endif /* RCC_D2CCIP1R_FDCANSEL */

+

+#endif /*FDCAN1 || FDCAN2*/

+

+/**

+  * @brief  Macro to Configure the SPI1/2/3 clock source.

+  * @param  __RCC_SPI123CLKSource__ defines the SPI1/2/3 clock source. This clock is derived

+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)

+  *          This parameter can be one of the following values:

+  *             @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL

+  *             @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2

+  *             @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3

+  *             @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock  = CLKP

+  *             @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock

+  * @retval None

+  */

+#if defined(RCC_D2CCIP1R_SPI123SEL)

+#define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\

+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))

+#else

+#define __HAL_RCC_SPI123_CONFIG(__RCC_SPI123CLKSource__ )\

+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL, (__RCC_SPI123CLKSource__))

+#endif /* RCC_D2CCIP1R_SPI123SEL */

+

+/** @brief  Macro to get the SPI1/2/3 clock source.

+  * @retval The clock source can be one of the following values:

+  *             @arg RCC_SPI123CLKSOURCE_PLL: SPI1/2/3 clock = PLL

+  *             @arg RCC_SPI123CLKSOURCE_PLL2: SPI1/2/3 clock = PLL2

+  *             @arg RCC_SPI123CLKSOURCE_PLL3: SPI1/2/3 clock = PLL3

+  *             @arg RCC_SPI123CLKSOURCE_CLKP: SPI1/2/3 clock  = CLKP

+  *             @arg RCC_SPI123CLKSOURCE_PIN: SPI1/2/3 clock = External Clock

+  */

+#if defined(RCC_D2CCIP1R_SPI123SEL)

+#define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI123SEL)))

+#else

+#define __HAL_RCC_GET_SPI123_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI123SEL)))

+#endif /* RCC_D2CCIP1R_SPI123SEL */

+

+/**

+  * @brief  Macro to Configure the SPI1 clock source.

+  * @param  __RCC_SPI1CLKSource__ defines the SPI1 clock source. This clock is derived

+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)

+  *          This parameter can be one of the following values:

+  *             @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL

+  *             @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2

+  *             @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3

+  *             @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock  = CLKP

+  *             @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock

+  * @retval None

+  */

+#define __HAL_RCC_SPI1_CONFIG  __HAL_RCC_SPI123_CONFIG

+

+/** @brief  Macro to get the SPI1 clock source.

+  * @retval The clock source can be one of the following values:

+  *             @arg RCC_SPI1CLKSOURCE_PLL: SPI1 clock = PLL

+  *             @arg RCC_SPI1CLKSOURCE_PLL2: SPI1 clock = PLL2

+  *             @arg RCC_SPI1CLKSOURCE_PLL3: SPI1 clock = PLL3

+  *             @arg RCC_SPI1CLKSOURCE_CLKP: SPI1 clock  = CLKP

+  *             @arg RCC_SPI1CLKSOURCE_PIN: SPI1 clock = External Clock

+  */

+#define __HAL_RCC_GET_SPI1_SOURCE  __HAL_RCC_GET_SPI123_SOURCE

+

+/**

+  * @brief  Macro to Configure the SPI2 clock source.

+  * @param  __RCC_SPI2CLKSource__ defines the SPI2 clock source. This clock is derived

+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)

+  *          This parameter can be one of the following values:

+  *             @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL

+  *             @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2

+  *             @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3

+  *             @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock  = CLKP

+  *             @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock

+  * @retval None

+  */

+#define __HAL_RCC_SPI2_CONFIG  __HAL_RCC_SPI123_CONFIG

+

+/** @brief  Macro to get the SPI2 clock source.

+  * @retval The clock source can be one of the following values:

+  *             @arg RCC_SPI2CLKSOURCE_PLL: SPI2 clock = PLL

+  *             @arg RCC_SPI2CLKSOURCE_PLL2: SPI2 clock = PLL2

+  *             @arg RCC_SPI2CLKSOURCE_PLL3: SPI2 clock = PLL3

+  *             @arg RCC_SPI2CLKSOURCE_CLKP: SPI2 clock  = CLKP

+  *             @arg RCC_SPI2CLKSOURCE_PIN: SPI2 clock = External Clock

+  */

+#define __HAL_RCC_GET_SPI2_SOURCE  __HAL_RCC_GET_SPI123_SOURCE

+

+/**

+  * @brief  Macro to Configure the SPI3 clock source.

+  * @param  __RCC_SPI3CLKSource__ defines the SPI3 clock source. This clock is derived

+  *         from system PLL, PLL2, PLL3, OSC or external clock (through a dedicated PIN)

+  *          This parameter can be one of the following values:

+  *             @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL

+  *             @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2

+  *             @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3

+  *             @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock  = CLKP

+  *             @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock

+  * @retval None

+  */

+#define __HAL_RCC_SPI3_CONFIG  __HAL_RCC_SPI123_CONFIG

+

+/** @brief  Macro to get the SPI3 clock source.

+  * @retval The clock source can be one of the following values:

+  *             @arg RCC_SPI3CLKSOURCE_PLL: SPI3 clock = PLL

+  *             @arg RCC_SPI3CLKSOURCE_PLL2: SPI3 clock = PLL2

+  *             @arg RCC_SPI3CLKSOURCE_PLL3: SPI3 clock = PLL3

+  *             @arg RCC_SPI3CLKSOURCE_CLKP: SPI3 clock  = CLKP

+  *             @arg RCC_SPI3CLKSOURCE_PIN: SPI3 clock = External Clock

+  */

+#define __HAL_RCC_GET_SPI3_SOURCE  __HAL_RCC_GET_SPI123_SOURCE

+

+/**

+  * @brief  Macro to Configure the SPI4/5 clock source.

+  * @param  __RCC_SPI45CLKSource__ defines the SPI4/5 clock source. This clock is derived

+  *         from system PCLK, PLL2, PLL3, OSC

+  *          This parameter can be one of the following values:

+  *             @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1

+  *             @arg RCC_SPI45CLKSOURCE_PLL2:   SPI4/5 clock = PLL2

+  *             @arg RCC_SPI45CLKSOURCE_PLL3:   SPI4/5 clock = PLL3

+  *             @arg RCC_SPI45CLKSOURCE_HSI:    SPI4/5 clock = HSI

+  *             @arg RCC_SPI45CLKSOURCE_CSI:    SPI4/5 clock = CSI

+  *             @arg RCC_SPI45CLKSOURCE_HSE:    SPI4/5 clock = HSE

+  * @retval None

+  */

+#if defined(RCC_D2CCIP1R_SPI45SEL)

+#define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\

+                  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))

+#else

+#define __HAL_RCC_SPI45_CONFIG(__RCC_SPI45CLKSource__ )\

+                  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL, (__RCC_SPI45CLKSource__))

+#endif /* RCC_D2CCIP1R_SPI45SEL */

+

+/** @brief  Macro to get the SPI4/5 clock source.

+  * @retval The clock source can be one of the following values:

+  *             @arg RCC_SPI45CLKSOURCE_D2PCLK1:SPI4/5 clock = D2PCLK1

+  *             @arg RCC_SPI45CLKSOURCE_PLL2:   SPI4/5 clock = PLL2

+  *             @arg RCC_SPI45CLKSOURCE_PLL3:   SPI4/5 clock = PLL3

+  *             @arg RCC_SPI45CLKSOURCE_HSI:    SPI4/5 clock = HSI

+  *             @arg RCC_SPI45CLKSOURCE_CSI:    SPI4/5 clock = CSI

+  *             @arg RCC_SPI45CLKSOURCE_HSE:    SPI4/5 clock = HSE

+*/

+#if defined(RCC_D2CCIP1R_SPI45SEL)

+#define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPI45SEL)))

+#else

+#define __HAL_RCC_GET_SPI45_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPI45SEL)))

+#endif /* RCC_D2CCIP1R_SPI45SEL */

+

+/**

+  * @brief  Macro to Configure the SPI4 clock source.

+  * @param  __RCC_SPI4CLKSource__ defines the SPI4 clock source. This clock is derived

+  *         from system PCLK, PLL2, PLL3, OSC

+  *          This parameter can be one of the following values:

+  *             @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1

+  *             @arg RCC_SPI4CLKSOURCE_PLL2:   SPI4 clock = PLL2

+  *             @arg RCC_SPI4CLKSOURCE_PLL3:   SPI4 clock = PLL3

+  *             @arg RCC_SPI4CLKSOURCE_HSI:    SPI4 clock = HSI

+  *             @arg RCC_SPI4CLKSOURCE_CSI:    SPI4 clock = CSI

+  *             @arg RCC_SPI4CLKSOURCE_HSE:    SPI4 clock = HSE

+  * @retval None

+  */

+#define __HAL_RCC_SPI4_CONFIG  __HAL_RCC_SPI45_CONFIG

+

+/** @brief  Macro to get the SPI4 clock source.

+  * @retval The clock source can be one of the following values:

+  *             @arg RCC_SPI4CLKSOURCE_D2PCLK1:SPI4 clock = D2PCLK1

+  *             @arg RCC_SPI4CLKSOURCE_PLL2:   SPI4 clock = PLL2

+  *             @arg RCC_SPI4CLKSOURCE_PLL3:   SPI4 clock = PLL3

+  *             @arg RCC_SPI4CLKSOURCE_HSI:    SPI4 clock = HSI

+  *             @arg RCC_SPI4CLKSOURCE_CSI:    SPI4 clock = CSI

+  *             @arg RCC_SPI4CLKSOURCE_HSE:    SPI4 clock = HSE

+*/

+#define __HAL_RCC_GET_SPI4_SOURCE  __HAL_RCC_GET_SPI45_SOURCE

+

+/**

+  * @brief  Macro to Configure the SPI5 clock source.

+  * @param  __RCC_SPI5CLKSource__ defines the SPI5 clock source. This clock is derived

+  *         from system PCLK, PLL2, PLL3, OSC

+  *          This parameter can be one of the following values:

+  *             @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1

+  *             @arg RCC_SPI5CLKSOURCE_PLL2:   SPI5 clock = PLL2

+  *             @arg RCC_SPI5CLKSOURCE_PLL3:   SPI5 clock = PLL3

+  *             @arg RCC_SPI5CLKSOURCE_HSI:    SPI5 clock = HSI

+  *             @arg RCC_SPI5CLKSOURCE_CSI:    SPI5 clock = CSI

+  *             @arg RCC_SPI5CLKSOURCE_HSE:    SPI5 clock = HSE

+  * @retval None

+  */

+#define __HAL_RCC_SPI5_CONFIG  __HAL_RCC_SPI45_CONFIG

+

+/** @brief  Macro to get the SPI5 clock source.

+  * @retval The clock source can be one of the following values:

+  *             @arg RCC_SPI5CLKSOURCE_D2PCLK1:SPI5 clock = D2PCLK1

+  *             @arg RCC_SPI5CLKSOURCE_PLL2:   SPI5 clock = PLL2

+  *             @arg RCC_SPI5CLKSOURCE_PLL3:   SPI5 clock = PLL3

+  *             @arg RCC_SPI5CLKSOURCE_HSI:    SPI5 clock = HSI

+  *             @arg RCC_SPI5CLKSOURCE_CSI:    SPI5 clock = CSI

+  *             @arg RCC_SPI5CLKSOURCE_HSE:    SPI5 clock = HSE

+*/

+#define __HAL_RCC_GET_SPI5_SOURCE  __HAL_RCC_GET_SPI45_SOURCE

+

+/**

+  * @brief  Macro to Configure the SPI6 clock source.

+  * @param  __RCC_SPI6CLKSource__ defines the SPI6 clock source. This clock is derived

+  *         from system PCLK, PLL2, PLL3, OSC

+  *          This parameter can be one of the following values:

+  *             @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1

+  *             @arg RCC_SPI6CLKSOURCE_PLL2:   SPI6 clock = PLL2

+  *             @arg RCC_SPI6CLKSOURCE_PLL3:   SPI6 clock = PLL3

+  *             @arg RCC_SPI6CLKSOURCE_HSI:    SPI6 clock = HSI

+  *             @arg RCC_SPI6CLKSOURCE_CSI:    SPI6 clock = CSI

+  *             @arg RCC_SPI6CLKSOURCE_HSE:    SPI6 clock = HSE

+  *             @arg RCC_SPI6CLKSOURCE_PIN:    SPI6 clock = I2S_CKIN (*)

+  *

+  * @retval None

+  *

+  * (*) : Available on stm32h7a3xx and stm32h7b3xx family lines.

+  *

+  */

+#if defined(RCC_D3CCIPR_SPI6SEL)

+#define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\

+                  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))

+#else

+#define __HAL_RCC_SPI6_CONFIG(__RCC_SPI6CLKSource__ )\

+                  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL, (__RCC_SPI6CLKSource__))

+#endif /* RCC_D3CCIPR_SPI6SEL */

+

+/** @brief  Macro to get the SPI6 clock source.

+  * @retval The clock source can be one of the following values:

+  *             @arg RCC_SPI6CLKSOURCE_D3PCLK1:SPI6 clock = D2PCLK1

+  *             @arg RCC_SPI6CLKSOURCE_PLL2:   SPI6 clock = PLL2

+  *             @arg RCC_SPI6CLKSOURCE_PLL3:   SPI6 clock = PLL3

+  *             @arg RCC_SPI6CLKSOURCE_HSI:    SPI6 clock = HSI

+  *             @arg RCC_SPI6CLKSOURCE_CSI:    SPI6 clock = CSI

+  *             @arg RCC_SPI6CLKSOURCE_HSE:    SPI6 clock = HSE

+  *                @arg RCC_SPI6CLKSOURCE_PIN:    SPI6 clock = I2S_CKIN

+*/

+#if defined(RCC_D3CCIPR_SPI6SEL)

+#define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_SPI6SEL)))

+#else

+#define __HAL_RCC_GET_SPI6_SOURCE() ((uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_SPI6SEL)))

+#endif /* RCC_D3CCIPR_SPI6SEL */

+

+/** @brief  Macro to configure the SDMMC clock

+  * @param  __SDMMCCLKSource__ specifies  clock source  for SDMMC

+  *         This parameter can be one of the following values:

+  *            @arg RCC_SDMMCCLKSOURCE_PLL:  PLLQ selected as SDMMC clock

+  *            @arg RCC_SDMMCCLKSOURCE_PLL2: PLL2R selected as SDMMC clock

+  */

+#if defined(RCC_D1CCIPR_SDMMCSEL)

+#define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \

+                  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))

+#else

+#define __HAL_RCC_SDMMC_CONFIG(__SDMMCCLKSource__) \

+                  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, (uint32_t)(__SDMMCCLKSource__))

+#endif /* RCC_D1CCIPR_SDMMCSEL */

+

+/** @brief  Macro to get the SDMMC clock

+  */

+#if defined(RCC_D1CCIPR_SDMMCSEL)

+#define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL)))

+#else

+#define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL)))

+#endif /* RCC_D1CCIPR_SDMMCSEL */

+

+/** @brief macro to configure the RNG clock (RNGCLK).

+  *

+  * @param  __RNGCLKSource__ specifies the RNG clock source.

+  *          This parameter can be one of the following values:

+  *            @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock

+  *            @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock

+  *            @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock

+  *            @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock

+  */

+#if defined(RCC_D2CCIP2R_RNGSEL)

+#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \

+                  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))

+#else

+#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \

+                  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, (uint32_t)(__RNGCLKSource__))

+#endif /* RCC_D2CCIP2R_RNGSEL */

+

+/** @brief  macro to get the RNG clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock

+  *            @arg RCC_RNGCLKSOURCE_PLL: PLL1Q selected as RNG clock

+  *            @arg RCC_RNGCLKSOURCE_LSE: LSE selected as RNG clock

+  *            @arg RCC_RNGCLKSOURCE_LSI: LSI selected as RNG clock

+  */

+#if defined(RCC_D2CCIP2R_RNGSEL)

+#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL)))

+#else

+#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL)))

+#endif /* RCC_D2CCIP2R_RNGSEL */

+

+#if defined(HRTIM1)

+/** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config

+  * @{

+  */

+/** @brief  Macro to configure the HRTIM1 prescaler clock source.

+  * @param  __HRTIM1CLKSource__ specifies the HRTIM1 prescaler clock source.

+  *         This parameter can be one of the following values:

+  *            @arg @ref RCC_HRTIM1CLK_TIMCLK    Timers  clock  selected as HRTIM1 prescaler clock

+  *            @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock

+  */

+#define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \

+                  MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, (uint32_t)(__HRTIM1CLKSource__))

+

+/** @brief  Macro to get the HRTIM1 clock source.

+  * @retval The clock source can be one of the following values:

+  *            @arg @ref RCC_HRTIM1CLK_TIMCLK   Timers  clock  selected as HRTIM1 prescaler clock

+  *            @arg @ref RCC_HRTIM1CLK_CPUCLK CPU Clock selected as HRTIM1 clock

+  */

+#define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL)))

+#endif /* HRTIM1 */

+

+/** @brief  Macro to configure the Timers clocks prescalers

+  * @param  __PRESC__  specifies the Timers clocks prescalers selection

+  *         This parameter can be one of the following values:

+  *            @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is

+  *                 equal to rcc_hclk1 if D2PPREx is corresponding to division by 1 or 2,

+  *                 else it is equal to 2 x Frcc_pclkx_d2 (default after reset)

+  *            @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is

+  *                 equal to rcc_hclk1 if D2PPREx is corresponding to division by 1, 2 or 4,

+  *                 else it is equal to 4 x Frcc_pclkx_d2

+  */

+#define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->CFGR &= ~(RCC_CFGR_TIMPRE);\

+                                                 RCC->CFGR |= (__PRESC__);       \

+                                                }while(0)

+

+/**

+  * @}

+  */

+    

+/**

+  * @brief Enable the RCC LSE CSS Extended Interrupt Line.

+  * @retval None

+  */

+#define __HAL_RCC_LSECSS_EXTI_ENABLE_IT()      SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)

+

+/**

+  * @brief Disable the RCC LSE CSS Extended Interrupt Line.

+  * @retval None

+  */

+#define __HAL_RCC_LSECSS_EXTI_DISABLE_IT()     CLEAR_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS)

+

+/**

+  * @brief Enable the RCC LSE CSS Event Line.

+  * @retval None.

+  */

+#define __HAL_RCC_LSECSS_EXTI_ENABLE_EVENT()   SET_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)

+

+/**

+  * @brief Disable the RCC LSE CSS Event Line.

+  * @retval None.

+  */

+#define __HAL_RCC_LSECSS_EXTI_DISABLE_EVENT()  CLEAR_BIT(EXTI->EMR1, RCC_EXTI_LINE_LSECSS)

+

+#if defined(DUAL_CORE)

+/**

+  * @brief Enable the RCC LSE CSS Extended Interrupt Line for CM4.

+  * @retval None

+  */

+#define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_IT()       SET_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS)

+

+/**

+  * @brief Disable the RCC LSE CSS Extended Interrupt Line for CM4.

+  * @retval None

+  */

+#define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_IT()      CLEAR_BIT(EXTI->C2IMR1, RCC_EXTI_LINE_LSECSS)

+

+/**

+  * @brief Enable the RCC LSE CSS Event Line for CM4.

+  * @retval None.

+  */

+#define __HAL_RCC_C2_LSECSS_EXTI_ENABLE_EVENT()    SET_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS)

+

+/**

+  * @brief Disable the RCC LSE CSS Event Line for CM4.

+  * @retval None.

+  */

+#define __HAL_RCC_C2_LSECSS_EXTI_DISABLE_EVENT()   CLEAR_BIT(EXTI->C2EMR1, RCC_EXTI_LINE_LSECSS)

+#endif /* DUAL_CORE */

+

+/**

+  * @brief  Enable the RCC LSE CSS Extended Interrupt Falling Trigger.

+  * @retval None.

+  */

+#define __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE()  SET_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)

+

+

+/**

+  * @brief Disable the RCC LSE CSS Extended Interrupt Falling Trigger.

+  * @retval None.

+  */

+#define __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE()  CLEAR_BIT(EXTI->FTSR1, RCC_EXTI_LINE_LSECSS)

+

+

+/**

+  * @brief  Enable the RCC LSE CSS Extended Interrupt Rising Trigger.

+  * @retval None.

+  */

+#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE()   SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)

+

+/**

+  * @brief Disable the RCC LSE CSS Extended Interrupt Rising Trigger.

+  * @retval None.

+  */

+#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE()  CLEAR_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS)

+

+/**

+  * @brief Enable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.

+  * @retval None.

+  */

+#define __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_FALLING_EDGE()  \

+  do {                                                      \

+    __HAL_RCC_LSECSS_EXTI_ENABLE_RISING_EDGE();             \

+    __HAL_RCC_LSECSS_EXTI_ENABLE_FALLING_EDGE();            \

+  } while(0)

+

+/**

+  * @brief Disable the RCC LSE CSS Extended Interrupt Rising & Falling Trigger.

+  * @retval None.

+  */

+#define __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_FALLING_EDGE()  \

+  do {                                                       \

+    __HAL_RCC_LSECSS_EXTI_DISABLE_RISING_EDGE();             \

+    __HAL_RCC_LSECSS_EXTI_DISABLE_FALLING_EDGE();            \

+  } while(0)

+

+/**

+  * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not.

+  * @retval EXTI RCC LSE CSS Line Status.

+  */

+#define __HAL_RCC_LSECSS_EXTI_GET_FLAG()       (READ_BIT(EXTI->PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)

+

+/**

+  * @brief Clear the RCC LSE CSS EXTI flag.

+  * @retval None.

+  */

+#define __HAL_RCC_LSECSS_EXTI_CLEAR_FLAG()     WRITE_REG(EXTI->PR1, RCC_EXTI_LINE_LSECSS)

+

+#if defined(DUAL_CORE)

+/**

+  * @brief Check whether the specified RCC LSE CSS EXTI interrupt flag is set or not for CM4.

+  * @retval EXTI RCC LSE CSS Line Status.

+  */

+#define __HAL_RCC_C2_LSECSS_EXTI_GET_FLAG()       (READ_BIT(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS) == RCC_EXTI_LINE_LSECSS)

+

+/**

+  * @brief Clear the RCC LSE CSS EXTI flag or not for CM4.

+  * @retval None.

+  */

+#define __HAL_RCC_C2_LSECSS_EXTI_CLEAR_FLAG()     WRITE_REG(EXTI->C2PR1, RCC_EXTI_LINE_LSECSS)

+#endif /* DUAL_CORE */

+/**

+  * @brief Generate a Software interrupt on the RCC LSE CSS EXTI line.

+  * @retval None.

+  */

+#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT()  SET_BIT(EXTI->SWIER1, RCC_EXTI_LINE_LSECSS)

+ 

+/**

+  * @brief  Enable the specified CRS interrupts.

+  * @param  __INTERRUPT__ specifies the CRS interrupt sources to be enabled.

+  *          This parameter can be any combination of the following values:

+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt

+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt

+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt

+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt

+  * @retval None

+  */

+#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__)   SET_BIT(CRS->CR, (__INTERRUPT__))

+

+/**

+  * @brief  Disable the specified CRS interrupts.

+  * @param  __INTERRUPT__ specifies the CRS interrupt sources to be disabled.

+  *          This parameter can be any combination of the following values:

+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt

+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt

+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt

+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt

+  * @retval None

+  */

+#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__)  CLEAR_BIT(CRS->CR, (__INTERRUPT__))

+

+/** @brief  Check whether the CRS interrupt has occurred or not.

+  * @param  __INTERRUPT__ specifies the CRS interrupt source to check.

+  *         This parameter can be one of the following values:

+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt

+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt

+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt

+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt

+  * @retval The new state of __INTERRUPT__ (SET or RESET).

+  */

+#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__)  ((READ_BIT(CRS->CR, (__INTERRUPT__)) != 0U) ? SET : RESET)

+

+/** @brief  Clear the CRS interrupt pending bits

+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.

+  *         This parameter can be any combination of the following values:

+  *              @arg @ref RCC_CRS_IT_SYNCOK  SYNC event OK interrupt

+  *              @arg @ref RCC_CRS_IT_SYNCWARN  SYNC warning interrupt

+  *              @arg @ref RCC_CRS_IT_ERR  Synchronization or trimming error interrupt

+  *              @arg @ref RCC_CRS_IT_ESYNC  Expected SYNC interrupt

+  *              @arg @ref RCC_CRS_IT_TRIMOVF  Trimming overflow or underflow interrupt

+  *              @arg @ref RCC_CRS_IT_SYNCERR  SYNC error interrupt

+  *              @arg @ref RCC_CRS_IT_SYNCMISS  SYNC missed interrupt

+  */

+/* CRS IT Error Mask */

+#define  RCC_CRS_IT_ERROR_MASK                 ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))

+

+#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__)  do { \

+                                                 if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \

+                                                 { \

+                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \

+                                                 } \

+                                                 else \

+                                                 { \

+                                                   WRITE_REG(CRS->ICR, (__INTERRUPT__)); \

+                                                 } \

+                                               } while(0)

+

+/**

+  * @brief  Check whether the specified CRS flag is set or not.

+  * @param  __FLAG__ specifies the flag to check.

+  *          This parameter can be one of the following values:

+  *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK

+  *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning

+  *              @arg @ref RCC_CRS_FLAG_ERR  Error

+  *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC

+  *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow

+  *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error

+  *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed

+  * @retval The new state of _FLAG_ (TRUE or FALSE).

+  */

+#define __HAL_RCC_CRS_GET_FLAG(__FLAG__)  (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__))

+

+/**

+  * @brief  Clear the CRS specified FLAG.

+  * @param __FLAG__ specifies the flag to clear.

+  *          This parameter can be one of the following values:

+  *              @arg @ref RCC_CRS_FLAG_SYNCOK  SYNC event OK

+  *              @arg @ref RCC_CRS_FLAG_SYNCWARN  SYNC warning

+  *              @arg @ref RCC_CRS_FLAG_ERR  Error

+  *              @arg @ref RCC_CRS_FLAG_ESYNC  Expected SYNC

+  *              @arg @ref RCC_CRS_FLAG_TRIMOVF  Trimming overflow or underflow

+  *              @arg @ref RCC_CRS_FLAG_SYNCERR  SYNC error

+  *              @arg @ref RCC_CRS_FLAG_SYNCMISS  SYNC missed

+  * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently RCC_CRS_FLAG_ERR

+  * @retval None

+  */

+

+/* CRS Flag Error Mask */

+#define RCC_CRS_FLAG_ERROR_MASK                ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))

+

+#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__)     do { \

+                                                 if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \

+                                                 { \

+                                                   WRITE_REG(CRS->ICR, CRS_ICR_ERRC | ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \

+                                                 } \

+                                                 else \

+                                                 { \

+                                                   WRITE_REG(CRS->ICR, (__FLAG__)); \

+                                                 } \

+                                               } while(0)

+

+ /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features

+  * @{

+  */

+/**

+  * @brief  Enable the oscillator clock for frequency error counter.

+  * @note   when the CEN bit is set the CRS_CFGR register becomes write-protected.

+  * @retval None

+  */

+#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE()  SET_BIT(CRS->CR, CRS_CR_CEN)

+

+/**

+  * @brief  Disable the oscillator clock for frequency error counter.

+  * @retval None

+  */

+#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN)

+

+/**

+  * @brief  Enable the automatic hardware adjustment of TRIM bits.

+  * @note   When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.

+  * @retval None

+  */

+#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE()     SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)

+

+/**

+  * @brief  Enable or disable the automatic hardware adjustment of TRIM bits.

+  * @retval None

+  */

+#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE()    CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN)

+

+/**

+  * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies

+  * @note   The RELOAD value should be selected according to the ratio between the target frequency and the frequency

+  *             of the synchronization source after pre-scaling. It is then decreased by one in order to

+  *             reach the expected synchronization on the zero value. The formula is the following:

+  *             RELOAD = (fTARGET / fSYNC) -1

+  * @param  __FTARGET__ Target frequency (value in Hz)

+  * @param  __FSYNC__ Synchronization signal frequency (value in Hz)

+  * @retval None

+  */

+#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__)  (((__FTARGET__) / (__FSYNC__)) - 1U)

+

+

+/**

+  * @}

+  */

+

+

+/**

+  * @}

+  */

+

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup RCCEx_Exported_Functions_Group1

+  * @{

+  */

+HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);

+void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);

+uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);

+uint32_t HAL_RCCEx_GetD1PCLK1Freq(void);

+uint32_t HAL_RCCEx_GetD3PCLK1Freq(void);

+uint32_t HAL_RCCEx_GetD1SysClockFreq(void);

+void     HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef* PLL1_Clocks);

+void     HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef* PLL2_Clocks);

+void     HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef* PLL3_Clocks);

+/**

+  * @}

+  */

+

+/** @addtogroup RCCEx_Exported_Functions_Group2

+  * @{

+  */

+void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);

+void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk);

+void HAL_RCCEx_EnableLSECSS(void);

+void HAL_RCCEx_DisableLSECSS(void);

+void HAL_RCCEx_EnableLSECSS_IT(void);

+void HAL_RCCEx_LSECSS_IRQHandler(void);

+void HAL_RCCEx_LSECSS_Callback(void);

+#if defined(DUAL_CORE)

+void HAL_RCCEx_EnableBootCore(uint32_t RCC_BootCx);

+#endif /*DUAL_CORE*/

+#if defined(RCC_GCR_WW1RSC)

+void HAL_RCCEx_WWDGxSysResetConfig(uint32_t RCC_WWDGx);

+#endif /*RCC_GCR_WW1RSC*/

+/**

+  * @}

+  */

+

+

+/** @addtogroup RCCEx_Exported_Functions_Group3

+  * @{

+  */

+

+void     HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);

+void     HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);

+void     HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);

+uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);

+void     HAL_RCCEx_CRS_IRQHandler(void);

+void     HAL_RCCEx_CRS_SyncOkCallback(void);

+void     HAL_RCCEx_CRS_SyncWarnCallback(void);

+void     HAL_RCCEx_CRS_ExpectedSyncCallback(void);

+void     HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);

+

+/**

+  * @}

+  */

+

+ /* Private macros ------------------------------------------------------------*/

+/** @addtogroup RCCEx_Private_Macros RCCEx Private Macros

+  * @{

+  */

+/** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters

+  * @{

+  */

+

+#define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL2_DIVP) || \

+                                         ((VALUE) == RCC_PLL2_DIVQ)  || \

+                                         ((VALUE) == RCC_PLL2_DIVR))

+

+#define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL3_DIVP) || \

+                                          ((VALUE) == RCC_PLL3_DIVQ) || \

+                                          ((VALUE) == RCC_PLL3_DIVR))

+

+#if defined(RCC_D2CCIP2R_USART16SEL)

+#define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \

+                                         ((SOURCE) == RCC_USART16CLKSOURCE_PLL2)   || \

+                                         ((SOURCE) == RCC_USART16CLKSOURCE_PLL3)   || \

+                                         ((SOURCE) == RCC_USART16CLKSOURCE_CSI)    || \

+                                         ((SOURCE) == RCC_USART16CLKSOURCE_LSE)    || \

+                                         ((SOURCE) == RCC_USART16CLKSOURCE_HSI))

+#else

+#define IS_RCC_USART16CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART16CLKSOURCE_D2PCLK2)|| \

+                                         ((SOURCE) == RCC_USART16CLKSOURCE_CDPCLK2)|| \

+                                         ((SOURCE) == RCC_USART16CLKSOURCE_PLL2)   || \

+                                         ((SOURCE) == RCC_USART16CLKSOURCE_PLL3)   || \

+                                         ((SOURCE) == RCC_USART16CLKSOURCE_CSI)    || \

+                                         ((SOURCE) == RCC_USART16CLKSOURCE_LSE)    || \

+                                         ((SOURCE) == RCC_USART16CLKSOURCE_HSI))

+/* alias*/

+#define IS_RCC_USART16910CLKSOURCE    IS_RCC_USART16CLKSOURCE

+#endif /* RCC_D2CCIP2R_USART16SEL */

+

+#if defined(RCC_D2CCIP2R_USART28SEL)

+#define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \

+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2)   || \

+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3)   || \

+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_CSI)    || \

+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_LSE)    || \

+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_HSI))

+#else

+#define IS_RCC_USART234578CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART234578CLKSOURCE_D2PCLK1)|| \

+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_CDPCLK1)|| \

+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_PLL2)   || \

+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_PLL3)   || \

+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_CSI)    || \

+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_LSE)    || \

+                                             ((SOURCE) == RCC_USART234578CLKSOURCE_HSI))

+#endif /* RCC_D2CCIP2R_USART28SEL */

+

+#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_D2PCLK2)|| \

+                                        ((SOURCE) == RCC_USART1CLKSOURCE_PLL2)   || \

+                                        ((SOURCE) == RCC_USART1CLKSOURCE_PLL3)   || \

+                                        ((SOURCE) == RCC_USART1CLKSOURCE_CSI)    || \

+                                        ((SOURCE) == RCC_USART1CLKSOURCE_LSE)    || \

+                                        ((SOURCE) == RCC_USART1CLKSOURCE_HSI))

+

+#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_D2PCLK1)|| \

+                                        ((SOURCE) == RCC_USART2CLKSOURCE_PLL2)   || \

+                                        ((SOURCE) == RCC_USART2CLKSOURCE_PLL3)   || \

+                                        ((SOURCE) == RCC_USART2CLKSOURCE_CSI)    || \

+                                        ((SOURCE) == RCC_USART2CLKSOURCE_LSE)    || \

+                                        ((SOURCE) == RCC_USART2CLKSOURCE_HSI))

+

+#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_D2PCLK1)|| \

+                                        ((SOURCE) == RCC_USART3CLKSOURCE_PLL2)   || \

+                                        ((SOURCE) == RCC_USART3CLKSOURCE_PLL3)   || \

+                                        ((SOURCE) == RCC_USART3CLKSOURCE_CSI)    || \

+                                        ((SOURCE) == RCC_USART3CLKSOURCE_LSE)    || \

+                                        ((SOURCE) == RCC_USART3CLKSOURCE_HSI))

+

+#define IS_RCC_UART4CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART4CLKSOURCE_D2PCLK1) || \

+                                        ((SOURCE) == RCC_UART4CLKSOURCE_PLL2)    || \

+                                        ((SOURCE) == RCC_UART4CLKSOURCE_PLL3)    || \

+                                        ((SOURCE) == RCC_UART4CLKSOURCE_CSI)     || \

+                                        ((SOURCE) == RCC_UART4CLKSOURCE_LSE)     || \

+                                        ((SOURCE) == RCC_UART4CLKSOURCE_HSI))

+

+#define IS_RCC_UART5CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART5CLKSOURCE_D2PCLK1) || \

+                                        ((SOURCE) == RCC_UART5CLKSOURCE_PLL2)    || \

+                                        ((SOURCE) == RCC_UART5CLKSOURCE_PLL3)    || \

+                                        ((SOURCE) == RCC_UART5CLKSOURCE_CSI)     || \

+                                        ((SOURCE) == RCC_UART5CLKSOURCE_LSE)     || \

+                                        ((SOURCE) == RCC_UART5CLKSOURCE_HSI))

+

+#define IS_RCC_USART6CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART6CLKSOURCE_D2PCLK2)|| \

+                                        ((SOURCE) == RCC_USART6CLKSOURCE_PLL2)   || \

+                                        ((SOURCE) == RCC_USART6CLKSOURCE_PLL3)   || \

+                                        ((SOURCE) == RCC_USART6CLKSOURCE_CSI)    || \

+                                        ((SOURCE) == RCC_USART6CLKSOURCE_LSE)    || \

+                                        ((SOURCE) == RCC_USART6CLKSOURCE_HSI))

+

+#define IS_RCC_UART7CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART7CLKSOURCE_D2PCLK1) || \

+                                        ((SOURCE) == RCC_UART7CLKSOURCE_PLL2)    || \

+                                        ((SOURCE) == RCC_UART7CLKSOURCE_PLL3)    || \

+                                        ((SOURCE) == RCC_UART7CLKSOURCE_CSI)     || \

+                                        ((SOURCE) == RCC_UART7CLKSOURCE_LSE)     || \

+                                        ((SOURCE) == RCC_UART7CLKSOURCE_HSI))

+

+#define IS_RCC_UART8CLKSOURCE(SOURCE)  (((SOURCE) == RCC_UART8CLKSOURCE_D2PCLK1) || \

+                                        ((SOURCE) == RCC_UART8CLKSOURCE_PLL2)    || \

+                                        ((SOURCE) == RCC_UART8CLKSOURCE_PLL3)    || \

+                                        ((SOURCE) == RCC_UART8CLKSOURCE_CSI)     || \

+                                        ((SOURCE) == RCC_UART8CLKSOURCE_LSE)     || \

+                                        ((SOURCE) == RCC_UART8CLKSOURCE_HSI))

+

+#if defined(UART9)

+#define IS_RCC_UART9CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART9CLKSOURCE_D2PCLK2)|| \

+                                        ((SOURCE) == RCC_UART9CLKSOURCE_PLL2)  || \

+                                        ((SOURCE) == RCC_UART9CLKSOURCE_PLL3)  || \

+                                        ((SOURCE) == RCC_UART9CLKSOURCE_CSI)   || \

+                                        ((SOURCE) == RCC_UART9CLKSOURCE_LSE)   || \

+                                        ((SOURCE) == RCC_UART9CLKSOURCE_HSI))

+#endif

+

+#if defined(USART10)

+#define IS_RCC_USART10CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART10CLKSOURCE_D2PCLK2)|| \

+                                        ((SOURCE) == RCC_USART10CLKSOURCE_PLL2)    || \

+                                        ((SOURCE) == RCC_USART10CLKSOURCE_PLL3)    || \

+                                        ((SOURCE) == RCC_USART10CLKSOURCE_CSI)     || \

+                                        ((SOURCE) == RCC_USART10CLKSOURCE_LSE)     || \

+                                        ((SOURCE) == RCC_USART10CLKSOURCE_HSI))

+#endif

+

+#define IS_RCC_LPUART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_LPUART1CLKSOURCE_D3PCLK1) || \

+                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL2)    || \

+                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_PLL3)    || \

+                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_CSI)     || \

+                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_LSE)     || \

+                                         ((SOURCE) == RCC_LPUART1CLKSOURCE_HSI))

+

+#define IS_RCC_I2C123CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C123CLKSOURCE_PLL3)   || \

+                                          ((SOURCE) == RCC_I2C123CLKSOURCE_HSI)    || \

+                                          ((SOURCE) == RCC_I2C123CLKSOURCE_D2PCLK1)|| \

+                                          ((SOURCE) == RCC_I2C123CLKSOURCE_CSI))

+

+#define IS_RCC_I2C1CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C1CLKSOURCE_PLL3)   || \

+                                        ((SOURCE) == RCC_I2C1CLKSOURCE_HSI)    || \

+                                        ((SOURCE) == RCC_I2C1CLKSOURCE_D2PCLK1)|| \

+                                        ((SOURCE) == RCC_I2C1CLKSOURCE_CSI))

+

+#define IS_RCC_I2C2CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C2CLKSOURCE_PLL3)   || \

+                                        ((SOURCE) == RCC_I2C2CLKSOURCE_HSI)    || \

+                                        ((SOURCE) == RCC_I2C2CLKSOURCE_D2PCLK1)|| \

+                                        ((SOURCE) == RCC_I2C2CLKSOURCE_CSI))

+

+#define IS_RCC_I2C3CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C3CLKSOURCE_PLL3)   || \

+                                        ((SOURCE) == RCC_I2C3CLKSOURCE_HSI)    || \

+                                        ((SOURCE) == RCC_I2C3CLKSOURCE_D2PCLK1)|| \

+                                        ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))

+

+#define IS_RCC_I2C4CLKSOURCE(SOURCE)   (((SOURCE) == RCC_I2C4CLKSOURCE_PLL3)   || \

+                                        ((SOURCE) == RCC_I2C4CLKSOURCE_HSI)    || \

+                                        ((SOURCE) == RCC_I2C4CLKSOURCE_D3PCLK1)|| \

+                                        ((SOURCE) == RCC_I2C3CLKSOURCE_CSI))

+

+#define IS_RCC_RNGCLKSOURCE(SOURCE)    (((SOURCE) == RCC_RNGCLKSOURCE_HSI48)|| \

+                                        ((SOURCE) == RCC_RNGCLKSOURCE_PLL)  || \

+                                        ((SOURCE) == RCC_RNGCLKSOURCE_LSE)  || \

+                                        ((SOURCE) == RCC_RNGCLKSOURCE_LSI))

+

+#if defined(HRTIM1)

+#define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_TIMCLK) || \

+                                        ((SOURCE) == RCC_HRTIM1CLK_CPUCLK))

+#endif

+

+#define IS_RCC_USBCLKSOURCE(SOURCE)    (((SOURCE) == RCC_USBCLKSOURCE_PLL)  || \

+                                        ((SOURCE) == RCC_USBCLKSOURCE_PLL3) || \

+                                        ((SOURCE) == RCC_USBCLKSOURCE_HSI48))

+

+#define IS_RCC_SAI1CLK(__SOURCE__)   \

+               (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL)  || \

+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \

+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \

+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_CLKP) || \

+                ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))

+

+#if defined(SAI3)

+#define IS_RCC_SAI23CLK(__SOURCE__)   \

+               (((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL)  || \

+                ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL2) || \

+                ((__SOURCE__) == RCC_SAI23CLKSOURCE_PLL3) || \

+                ((__SOURCE__) == RCC_SAI23CLKSOURCE_CLKP) || \

+                ((__SOURCE__) == RCC_SAI23CLKSOURCE_PIN))

+

+#define IS_RCC_SAI2CLK(__SOURCE__)   \

+               (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL)  || \

+                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || \

+                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || \

+                ((__SOURCE__) == RCC_SAI2CLKSOURCE_CLKP) || \

+                ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN))

+

+

+#define IS_RCC_SAI3CLK(__SOURCE__)   \

+               (((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL)  || \

+                ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL2) || \

+                ((__SOURCE__) == RCC_SAI3CLKSOURCE_PLL3) || \

+                ((__SOURCE__) == RCC_SAI3CLKSOURCE_CLKP) || \

+                ((__SOURCE__) == RCC_SAI3CLKSOURCE_PIN))

+#endif

+

+#if defined(RCC_CDCCIP1R_SAI2ASEL)

+#define IS_RCC_SAI2ACLK(__SOURCE__)   \

+               (((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL)  || \

+                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL2) || \

+                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PLL3) || \

+                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_CLKP) || \

+                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_PIN) || \

+                ((__SOURCE__) == RCC_SAI2ACLKSOURCE_SPDIF))

+#endif

+

+#if defined(RCC_CDCCIP1R_SAI2BSEL)

+#define IS_RCC_SAI2BCLK(__SOURCE__)   \

+               (((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL)  || \

+                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL2) || \

+                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PLL3) || \

+                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_CLKP) || \

+                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_PIN) || \

+                ((__SOURCE__) == RCC_SAI2BCLKSOURCE_SPDIF))

+#endif

+

+#define IS_RCC_SPI123CLK(__SOURCE__)   \

+               (((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL)  || \

+                ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL2) || \

+                ((__SOURCE__) == RCC_SPI123CLKSOURCE_PLL3) || \

+                ((__SOURCE__) == RCC_SPI123CLKSOURCE_CLKP) || \

+                ((__SOURCE__) == RCC_SPI123CLKSOURCE_PIN))

+

+#define IS_RCC_SPI1CLK(__SOURCE__)   \

+               (((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL)  || \

+                ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL2) || \

+                ((__SOURCE__) == RCC_SPI1CLKSOURCE_PLL3) || \

+                ((__SOURCE__) == RCC_SPI1CLKSOURCE_CLKP) || \

+                ((__SOURCE__) == RCC_SPI1CLKSOURCE_PIN))

+

+#define IS_RCC_SPI2CLK(__SOURCE__)   \

+               (((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL)  || \

+                ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL2) || \

+                ((__SOURCE__) == RCC_SPI2CLKSOURCE_PLL3) || \

+                ((__SOURCE__) == RCC_SPI2CLKSOURCE_CLKP) || \

+                ((__SOURCE__) == RCC_SPI2CLKSOURCE_PIN))

+

+#define IS_RCC_SPI3CLK(__SOURCE__)   \

+               (((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL)  || \

+                ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL2) || \

+                ((__SOURCE__) == RCC_SPI3CLKSOURCE_PLL3) || \

+                ((__SOURCE__) == RCC_SPI3CLKSOURCE_CLKP) || \

+                ((__SOURCE__) == RCC_SPI3CLKSOURCE_PIN))

+

+#define IS_RCC_SPI45CLK(__SOURCE__)   \

+               (((__SOURCE__) == RCC_SPI45CLKSOURCE_D2PCLK1)  || \

+                ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL2)     || \

+                ((__SOURCE__) == RCC_SPI45CLKSOURCE_PLL3)     || \

+                ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSI)      || \

+                ((__SOURCE__) == RCC_SPI45CLKSOURCE_CSI)      || \

+                ((__SOURCE__) == RCC_SPI45CLKSOURCE_HSE))

+

+#define IS_RCC_SPI4CLK(__SOURCE__)   \

+               (((__SOURCE__) == RCC_SPI4CLKSOURCE_D2PCLK1)  || \

+                ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL2)     || \

+                ((__SOURCE__) == RCC_SPI4CLKSOURCE_PLL3)     || \

+                ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSI)      || \

+                ((__SOURCE__) == RCC_SPI4CLKSOURCE_CSI)      || \

+                ((__SOURCE__) == RCC_SPI4CLKSOURCE_HSE))

+

+#define IS_RCC_SPI5CLK(__SOURCE__)   \

+               (((__SOURCE__) == RCC_SPI5CLKSOURCE_D2PCLK1)|| \

+                ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL2)   || \

+                ((__SOURCE__) == RCC_SPI5CLKSOURCE_PLL3)   || \

+                ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSI)    || \

+                ((__SOURCE__) == RCC_SPI5CLKSOURCE_CSI)    || \

+                ((__SOURCE__) == RCC_SPI5CLKSOURCE_HSE))

+

+#if defined(RCC_D3CCIPR_SPI6SEL)

+#define IS_RCC_SPI6CLK(__SOURCE__)   \

+               (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \

+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2)    || \

+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3)    || \

+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI)     || \

+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI)     || \

+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE))

+#else

+#define IS_RCC_SPI6CLK(__SOURCE__)   \

+               (((__SOURCE__) == RCC_SPI6CLKSOURCE_D3PCLK1) || \

+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL2)    || \

+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PLL3)    || \

+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSI)     || \

+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_CSI)     || \

+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_HSE)     || \

+                ((__SOURCE__) == RCC_SPI6CLKSOURCE_PIN))

+#endif /* RCC_D3CCIPR_SPI6SEL */

+

+#if defined(SAI4)

+#define IS_RCC_SAI4ACLK(__SOURCE__)   \

+               (((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL)  || \

+                ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL2) || \

+                ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PLL3) || \

+                ((__SOURCE__) == RCC_SAI4ACLKSOURCE_CLKP) || \

+                ((__SOURCE__) == RCC_SAI4ACLKSOURCE_PIN))

+

+#define IS_RCC_SAI4BCLK(__SOURCE__)   \

+               (((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL)  || \

+                ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL2) || \

+                ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PLL3) || \

+                ((__SOURCE__) == RCC_SAI4BCLKSOURCE_CLKP) || \

+                ((__SOURCE__) == RCC_SAI4BCLKSOURCE_PIN))

+#endif /*SAI4*/

+

+#define IS_RCC_PLL3M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))

+#define IS_RCC_PLL3N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))

+#define IS_RCC_PLL3P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))

+#define IS_RCC_PLL3Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))

+#define IS_RCC_PLL3R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))

+

+#define IS_RCC_PLL2M_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 63U))

+#define IS_RCC_PLL2N_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U))

+#define IS_RCC_PLL2P_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))

+#define IS_RCC_PLL2Q_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))

+#define IS_RCC_PLL2R_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U))

+

+#define IS_RCC_PLL2RGE_VALUE(VALUE) (((VALUE) == RCC_PLL2VCIRANGE_0)  || \

+                                    ((VALUE) == RCC_PLL2VCIRANGE_1)   || \

+                                    ((VALUE) == RCC_PLL2VCIRANGE_2)   || \

+                                    ((VALUE) == RCC_PLL2VCIRANGE_3))

+

+#define IS_RCC_PLL3RGE_VALUE(VALUE) (((VALUE) == RCC_PLL3VCIRANGE_0)  || \

+                                    ((VALUE) == RCC_PLL3VCIRANGE_1)   || \

+                                    ((VALUE) == RCC_PLL3VCIRANGE_2)   || \

+                                    ((VALUE) == RCC_PLL3VCIRANGE_3))

+

+#define IS_RCC_PLL2VCO_VALUE(VALUE) (((VALUE) == RCC_PLL2VCOWIDE)  || \

+                                    ((VALUE) == RCC_PLL2VCOMEDIUM))

+

+#define IS_RCC_PLL3VCO_VALUE(VALUE) (((VALUE) == RCC_PLL3VCOWIDE)  || \

+                                    ((VALUE) == RCC_PLL3VCOMEDIUM))

+

+#define IS_RCC_PLLFRACN_VALUE(VALUE) ((VALUE) <=8191U)

+

+#define IS_RCC_LPTIM1CLK(SOURCE)       (((SOURCE) == RCC_LPTIM1CLKSOURCE_D2PCLK1)|| \

+                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL2)   || \

+                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_PLL3)   || \

+                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE)    || \

+                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI)    || \

+                                        ((SOURCE) == RCC_LPTIM1CLKSOURCE_CLKP))

+

+#define IS_RCC_LPTIM2CLK(SOURCE)       (((SOURCE) == RCC_LPTIM2CLKSOURCE_D3PCLK1)|| \

+                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL2)   || \

+                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_PLL3)   || \

+                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSE)    || \

+                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_LSI)    || \

+                                        ((SOURCE) == RCC_LPTIM2CLKSOURCE_CLKP))

+

+#define IS_RCC_LPTIM345CLK(SOURCE)     (((SOURCE) == RCC_LPTIM345CLKSOURCE_D3PCLK1)|| \

+                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL2)   || \

+                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_PLL3)   || \

+                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSE)    || \

+                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_LSI)    || \

+                                        ((SOURCE) == RCC_LPTIM345CLKSOURCE_CLKP))

+

+#define IS_RCC_LPTIM3CLK(SOURCE)       (((SOURCE) == RCC_LPTIM3CLKSOURCE_D3PCLK1)  || \

+                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL2)     || \

+                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_PLL3)     || \

+                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSE)      || \

+                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_LSI)      || \

+                                        ((SOURCE) == RCC_LPTIM3CLKSOURCE_CLKP))

+

+#if defined(LPTIM4)

+#define IS_RCC_LPTIM4CLK(SOURCE)       (((SOURCE) == RCC_LPTIM4CLKSOURCE_D3PCLK1)|| \

+                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL2)   || \

+                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_PLL3)   || \

+                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSE)    || \

+                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_LSI)    || \

+                                        ((SOURCE) == RCC_LPTIM4CLKSOURCE_CLKP))

+#endif /* LPTIM4*/

+

+#if defined(LPTIM5)

+#define IS_RCC_LPTIM5CLK(SOURCE)       (((SOURCE) == RCC_LPTIM5CLKSOURCE_D3PCLK1)|| \

+                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL2)   || \

+                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_PLL3)   || \

+                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSE)    || \

+                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_LSI)    || \

+                                        ((SOURCE) == RCC_LPTIM5CLKSOURCE_CLKP))

+#endif /*LPTIM5*/

+

+#if defined(QUADSPI)

+#define IS_RCC_QSPICLK(__SOURCE__)   \

+               (((__SOURCE__) == RCC_QSPICLKSOURCE_D1HCLK)  || \

+                ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL)     || \

+                ((__SOURCE__) == RCC_QSPICLKSOURCE_PLL2)    || \

+                ((__SOURCE__) == RCC_QSPICLKSOURCE_CLKP))

+#endif /*QUADSPI*/

+

+#if defined(OCTOSPI1) || defined(OCTOSPI1)

+#define IS_RCC_OSPICLK(__SOURCE__)   \

+               (((__SOURCE__) == RCC_OSPICLKSOURCE_D1HCLK)  || \

+                ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL)     || \

+                ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2)    || \

+                ((__SOURCE__) == RCC_OSPICLKSOURCE_CLKP))

+#endif /*OCTOSPI1 || OCTOSPI1*/

+

+#if defined(DSI)

+#define IS_RCC_DSICLK(__SOURCE__)   \

+               (((__SOURCE__) == RCC_DSICLKSOURCE_PHY)  || \

+                ((__SOURCE__) == RCC_DSICLKSOURCE_PLL2))

+#endif /*DSI*/

+

+#define IS_RCC_FMCCLK(__SOURCE__)   \

+               (((__SOURCE__) == RCC_FMCCLKSOURCE_D1HCLK)  || \

+                ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL)     || \

+                ((__SOURCE__) == RCC_FMCCLKSOURCE_PLL2)    || \

+                ((__SOURCE__) == RCC_FMCCLKSOURCE_CLKP))

+

+#if defined(FDCAN1) || defined(FDCAN2)

+#define IS_RCC_FDCANCLK(__SOURCE__)   \

+               (((__SOURCE__) == RCC_FDCANCLKSOURCE_HSE)  || \

+                ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL)  || \

+                ((__SOURCE__) == RCC_FDCANCLKSOURCE_PLL2))

+#endif /*FDCAN1 || FDCAN2*/

+

+#define IS_RCC_SDMMC(__SOURCE__)   \

+                (((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL)  || \

+                ((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL2))

+

+#define IS_RCC_ADCCLKSOURCE(SOURCE)    (((SOURCE) == RCC_ADCCLKSOURCE_PLL2) || \

+                                        ((SOURCE) == RCC_ADCCLKSOURCE_PLL3) || \

+                                        ((SOURCE) == RCC_ADCCLKSOURCE_CLKP))

+

+#define IS_RCC_SWPMI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SWPMI1CLKSOURCE_D2PCLK1) || \

+                                        ((SOURCE) == RCC_SWPMI1CLKSOURCE_HSI))

+

+#define IS_RCC_DFSDM1CLKSOURCE(SOURCE)  (((SOURCE) == RCC_DFSDM1CLKSOURCE_D2PCLK1) || \

+                                         ((SOURCE) == RCC_DFSDM1CLKSOURCE_SYS))

+

+#if defined(DFSDM2_BASE)

+#define IS_RCC_DFSDM2CLKSOURCE(SOURCE)  (((SOURCE) == RCC_DFSDM2CLKSOURCE_SRDPCLK1) || \

+                                        ((SOURCE) == RCC_DFSDM2CLKSOURCE_SYS))

+#endif /*DFSDM2*/

+

+#define IS_RCC_SPDIFRXCLKSOURCE(SOURCE)(((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL)  || \

+                                        ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL2) || \

+                                        ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLL3) || \

+                                        ((SOURCE) == RCC_SPDIFRXCLKSOURCE_HSI))

+

+#define IS_RCC_CECCLKSOURCE(SOURCE)  (((SOURCE) == RCC_CECCLKSOURCE_LSE) || \

+                                      ((SOURCE) == RCC_CECCLKSOURCE_LSI) || \

+                                      ((SOURCE) == RCC_CECCLKSOURCE_CSI))

+

+#define IS_RCC_CLKPSOURCE(SOURCE)   (((SOURCE) == RCC_CLKPSOURCE_HSI)  || \

+                                      ((SOURCE) == RCC_CLKPSOURCE_CSI) || \

+                                      ((SOURCE) == RCC_CLKPSOURCE_HSE))

+#define IS_RCC_TIMPRES(VALUE)  \

+               (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \

+                ((VALUE) == RCC_TIMPRES_ACTIVATED))

+

+#if defined(DUAL_CORE)

+#define IS_RCC_BOOT_CORE(CORE)   (((CORE) == RCC_BOOT_C1)  || \

+                                  ((CORE) == RCC_BOOT_C2))

+#endif /*DUAL_CORE*/

+

+#if defined(DUAL_CORE)

+#define IS_RCC_SCOPE_WWDG(WWDG)   (((WWDG) == RCC_WWDG1)  || \

+                                  ((WWDG) == RCC_WWDG2))

+#else

+#define IS_RCC_SCOPE_WWDG(WWDG)   ((WWDG) == RCC_WWDG1)

+

+#endif /*DUAL_CORE*/

+

+#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB2) || \

+                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE)  || \

+                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB1) || \

+                                            ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_PIN))

+

+#define IS_RCC_CRS_SYNC_DIV(__DIV__)       (((__DIV__) == RCC_CRS_SYNC_DIV1)  || ((__DIV__) == RCC_CRS_SYNC_DIV2)  || \

+                                            ((__DIV__) == RCC_CRS_SYNC_DIV4)  || ((__DIV__) == RCC_CRS_SYNC_DIV8)  || \

+                                            ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \

+                                            ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))

+

+#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \

+                                                ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))

+

+#define IS_RCC_CRS_RELOADVALUE(__VALUE__)  (((__VALUE__) <= 0xFFFFU))

+

+#define IS_RCC_CRS_ERRORLIMIT(__VALUE__)   (((__VALUE__) <= 0xFFU))

+

+#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3FU))

+

+#define IS_RCC_CRS_FREQERRORDIR(__DIR__)   (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \

+                                            ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_RCC_EX_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_rng.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_rng.h
new file mode 100644
index 0000000000..2419609332
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_rng.h
@@ -0,0 +1,384 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_rng.h

+  * @author  MCD Application Team

+  * @brief   Header file of RNG HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_RNG_H

+#define STM32H7xx_HAL_RNG_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+#if defined (RNG)

+

+/** @defgroup RNG RNG

+  * @brief RNG HAL module driver

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+

+/** @defgroup RNG_Exported_Types RNG Exported Types

+  * @{

+  */

+

+/** @defgroup RNG_Exported_Types_Group1 RNG Init Structure definition

+  * @{

+  */

+typedef struct

+{

+  uint32_t                    ClockErrorDetection; /*!< CED Clock error detection */

+} RNG_InitTypeDef;

+

+/**

+  * @}

+  */

+

+/** @defgroup RNG_Exported_Types_Group2 RNG State Structure definition

+  * @{

+  */

+typedef enum

+{

+  HAL_RNG_STATE_RESET     = 0x00U,  /*!< RNG not yet initialized or disabled */

+  HAL_RNG_STATE_READY     = 0x01U,  /*!< RNG initialized and ready for use   */

+  HAL_RNG_STATE_BUSY      = 0x02U,  /*!< RNG internal process is ongoing     */

+  HAL_RNG_STATE_TIMEOUT   = 0x03U,  /*!< RNG timeout state                   */

+  HAL_RNG_STATE_ERROR     = 0x04U   /*!< RNG error state                     */

+

+} HAL_RNG_StateTypeDef;

+

+/**

+  * @}

+  */

+

+/** @defgroup RNG_Exported_Types_Group3 RNG Handle Structure definition

+  * @{

+  */

+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)

+typedef struct  __RNG_HandleTypeDef

+#else

+typedef struct

+#endif /* (USE_HAL_RNG_REGISTER_CALLBACKS) */

+{

+  RNG_TypeDef                 *Instance;    /*!< Register base address   */

+

+  RNG_InitTypeDef             Init;         /*!< RNG configuration parameters */

+

+  HAL_LockTypeDef             Lock;         /*!< RNG locking object      */

+

+  __IO HAL_RNG_StateTypeDef   State;        /*!< RNG communication state */

+

+  __IO  uint32_t              ErrorCode;     /*!< RNG Error code               */

+

+  uint32_t                    RandomNumber; /*!< Last Generated RNG Data */

+

+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)

+  void (* ReadyDataCallback)(struct __RNG_HandleTypeDef *hrng, uint32_t random32bit);  /*!< RNG Data Ready Callback    */

+  void (* ErrorCallback)(struct __RNG_HandleTypeDef *hrng);                            /*!< RNG Error Callback         */

+

+  void (* MspInitCallback)(struct __RNG_HandleTypeDef *hrng);                          /*!< RNG Msp Init callback      */

+  void (* MspDeInitCallback)(struct __RNG_HandleTypeDef *hrng);                        /*!< RNG Msp DeInit callback    */

+#endif  /* USE_HAL_RNG_REGISTER_CALLBACKS */

+

+} RNG_HandleTypeDef;

+

+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  HAL RNG Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_RNG_ERROR_CB_ID                   = 0x00U,     /*!< RNG Error Callback ID          */

+

+  HAL_RNG_MSPINIT_CB_ID                 = 0x01U,     /*!< RNG MspInit callback ID        */

+  HAL_RNG_MSPDEINIT_CB_ID               = 0x02U      /*!< RNG MspDeInit callback ID      */

+

+} HAL_RNG_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL RNG Callback pointer definition

+  */

+typedef  void (*pRNG_CallbackTypeDef)(RNG_HandleTypeDef *hrng);                                  /*!< pointer to a common RNG callback function */

+typedef  void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t random32bit);   /*!< pointer to an RNG Data Ready specific callback function */

+

+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup RNG_Exported_Constants RNG Exported Constants

+  * @{

+  */

+

+/** @defgroup RNG_Exported_Constants_Group1 RNG Interrupt definition

+  * @{

+  */

+#define RNG_IT_DRDY  RNG_SR_DRDY  /*!< Data Ready interrupt  */

+#define RNG_IT_CEI   RNG_SR_CEIS  /*!< Clock error interrupt */

+#define RNG_IT_SEI   RNG_SR_SEIS  /*!< Seed error interrupt  */

+/**

+  * @}

+  */

+

+/** @defgroup RNG_Exported_Constants_Group2 RNG Flag definition

+  * @{

+  */

+#define RNG_FLAG_DRDY   RNG_SR_DRDY  /*!< Data ready                 */

+#define RNG_FLAG_CECS   RNG_SR_CECS  /*!< Clock error current status */

+#define RNG_FLAG_SECS   RNG_SR_SECS  /*!< Seed error current status  */

+/**

+  * @}

+  */

+

+/** @defgroup RNG_Exported_Constants_Group3 RNG Clock Error Detection

+  * @{

+  */

+#define RNG_CED_ENABLE          0x00000000U /*!< Clock error detection Enabled  */

+#define RNG_CED_DISABLE         RNG_CR_CED  /*!< Clock error detection Disabled */

+/**

+  * @}

+  */

+

+/** @defgroup RNG_Error_Definition   RNG Error Definition

+  * @{

+  */

+#define  HAL_RNG_ERROR_NONE             0x00000000U    /*!< No error             */

+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)

+#define  HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U    /*!< Invalid Callback error  */

+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */

+#define  HAL_RNG_ERROR_TIMEOUT          0x00000002U    /*!< Timeout error        */

+#define  HAL_RNG_ERROR_BUSY             0x00000004U    /*!< Busy error        */

+#define  HAL_RNG_ERROR_SEED             0x00000008U    /*!< Seed error        */

+#define  HAL_RNG_ERROR_CLOCK            0x00000010U   /*!< Clock error        */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macros -----------------------------------------------------------*/

+/** @defgroup RNG_Exported_Macros RNG Exported Macros

+  * @{

+  */

+

+/** @brief Reset RNG handle state

+  * @param  __HANDLE__ RNG Handle

+  * @retval None

+  */

+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)

+#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \

+                                                       (__HANDLE__)->State = HAL_RNG_STATE_RESET;       \

+                                                       (__HANDLE__)->MspInitCallback = NULL;            \

+                                                       (__HANDLE__)->MspDeInitCallback = NULL;          \

+                                                    } while(0U)

+#else

+#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)

+#endif /*USE_HAL_RNG_REGISTER_CALLBACKS */

+

+/**

+  * @brief  Enables the RNG peripheral.

+  * @param  __HANDLE__ RNG Handle

+  * @retval None

+  */

+#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_RNGEN)

+

+/**

+  * @brief  Disables the RNG peripheral.

+  * @param  __HANDLE__ RNG Handle

+  * @retval None

+  */

+#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)

+

+/**

+  * @brief  Check the selected RNG flag status.

+  * @param  __HANDLE__ RNG Handle

+  * @param  __FLAG__ RNG flag

+  *          This parameter can be one of the following values:

+  *            @arg RNG_FLAG_DRDY:  Data ready

+  *            @arg RNG_FLAG_CECS:  Clock error current status

+  *            @arg RNG_FLAG_SECS:  Seed error current status

+  * @retval The new state of __FLAG__ (SET or RESET).

+  */

+#define __HAL_RNG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

+

+/**

+  * @brief  Clears the selected RNG flag status.

+  * @param  __HANDLE__ RNG handle

+  * @param  __FLAG__ RNG flag to clear

+  * @note   WARNING: This is a dummy macro for HAL code alignment,

+  *         flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.

+  * @retval None

+  */

+#define __HAL_RNG_CLEAR_FLAG(__HANDLE__, __FLAG__)                      /* dummy  macro */

+

+/**

+  * @brief  Enables the RNG interrupts.

+  * @param  __HANDLE__ RNG Handle

+  * @retval None

+  */

+#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |=  RNG_CR_IE)

+

+/**

+  * @brief  Disables the RNG interrupts.

+  * @param  __HANDLE__ RNG Handle

+  * @retval None

+  */

+#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)

+

+/**

+  * @brief  Checks whether the specified RNG interrupt has occurred or not.

+  * @param  __HANDLE__ RNG Handle

+  * @param  __INTERRUPT__ specifies the RNG interrupt status flag to check.

+  *         This parameter can be one of the following values:

+  *            @arg RNG_IT_DRDY: Data ready interrupt

+  *            @arg RNG_IT_CEI: Clock error interrupt

+  *            @arg RNG_IT_SEI: Seed error interrupt

+  * @retval The new state of __INTERRUPT__ (SET or RESET).

+  */

+#define __HAL_RNG_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR & (__INTERRUPT__)) == (__INTERRUPT__))

+

+/**

+  * @brief  Clear the RNG interrupt status flags.

+  * @param  __HANDLE__ RNG Handle

+  * @param  __INTERRUPT__ specifies the RNG interrupt status flag to clear.

+  *          This parameter can be one of the following values:

+  *            @arg RNG_IT_CEI: Clock error interrupt

+  *            @arg RNG_IT_SEI: Seed error interrupt

+  * @note   RNG_IT_DRDY flag is read-only, reading RNG_DR register automatically clears RNG_IT_DRDY.

+  * @retval None

+  */

+#define __HAL_RNG_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->SR) = ~(__INTERRUPT__))

+

+/**

+  * @}

+  */

+

+#if defined (RNG_CR_CONDRST)

+/* Include HASH HAL Extended module */

+#include "stm32h7xx_hal_rng_ex.h"

+#endif  /* CONDRST */

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup RNG_Exported_Functions RNG Exported Functions

+  * @{

+  */

+

+/** @defgroup RNG_Exported_Functions_Group1 Initialization and configuration functions

+  * @{

+  */

+HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng);

+HAL_StatusTypeDef HAL_RNG_DeInit(RNG_HandleTypeDef *hrng);

+void HAL_RNG_MspInit(RNG_HandleTypeDef *hrng);

+void HAL_RNG_MspDeInit(RNG_HandleTypeDef *hrng);

+

+/* Callbacks Register/UnRegister functions  ***********************************/

+#if (USE_HAL_RNG_REGISTER_CALLBACKS == 1)

+HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID, pRNG_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_CallbackIDTypeDef CallbackID);

+

+HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRNG_ReadyDataCallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng);

+#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+/** @defgroup RNG_Exported_Functions_Group2 Peripheral Control functions

+  * @{

+  */

+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit);

+HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng);

+uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng);

+

+void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng);

+void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng);

+void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit);

+

+/**

+  * @}

+  */

+

+/** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions

+  * @{

+  */

+HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng);

+uint32_t             HAL_RNG_GetError(RNG_HandleTypeDef *hrng);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup RNG_Private_Macros RNG Private Macros

+  * @{

+  */

+#define IS_RNG_IT(IT) (((IT) == RNG_IT_CEI) || \

+                       ((IT) == RNG_IT_SEI))

+

+#define IS_RNG_FLAG(FLAG) (((FLAG) == RNG_FLAG_DRDY) || \

+                            ((FLAG) == RNG_FLAG_CECS) || \

+                            ((FLAG) == RNG_FLAG_SECS))

+

+/**

+  * @brief Verify the RNG Clock Error Detection mode.

+  * @param __MODE__ RNG Clock Error Detection mode

+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

+  */

+#define IS_RNG_CED(__MODE__)   (((__MODE__) == RNG_CED_ENABLE) || \

+                                ((__MODE__) == RNG_CED_DISABLE))

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* RNG */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+

+#endif /* STM32H7xx_HAL_RNG_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_rng_ex.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_rng_ex.h
new file mode 100644
index 0000000000..69a97d4cba
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_rng_ex.h
@@ -0,0 +1,241 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_rng_ex.h

+  * @author  MCD Application Team

+  * @brief   Header file of RNG HAL Extension module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_RNG_EX_H

+#define STM32H7xx_HAL_RNG_EX_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+#if defined (RNG)

+#if defined (RNG_CR_CONDRST)

+

+/** @defgroup RNGEx RNGEx

+  * @brief RNG Extension HAL module driver

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup RNGEx_Exported_Types RNGEx Exported Types

+  * @brief RNGEx Exported types

+  * @{

+  */

+

+/**

+  * @brief RNGEX Configuration Structure definition

+  */

+

+typedef struct

+{

+  uint32_t        Config1;           /*!< Config1 must be a value between 0 and 0x3F */

+  uint32_t        Config2;           /*!< Config2 must be a value between 0 and 0x7 */

+  uint32_t        Config3;           /*!< Config3 must be a value between 0 and 0xF */

+  uint32_t        ClockDivider;      /*!< Clock Divider factor.This parameter can

+                                          be a value of @ref RNGEX_Clock_Divider_Factor   */

+  uint32_t        NistCompliance;    /*!< NIST compliance.This parameter can be a

+                                          value of @ref RNGEX_NIST_Compliance   */

+} RNG_ConfigTypeDef;

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup RNGEX_Exported_Constants RNGEX Exported Constants

+  * @{

+  */

+

+/** @defgroup RNGEX_Clock_Divider_Factor  Value used to configure an internal

+ *            programmable divider acting on the incoming RNG clock

+  * @{

+  */

+#define RNG_CLKDIV_BY_1       (0x00000000UL)      /*!< No clock division  */

+#define RNG_CLKDIV_BY_2       (RNG_CR_CLKDIV_0)

+/*!< 2 RNG clock cycles per internal RNG clock    */

+#define RNG_CLKDIV_BY_4       (RNG_CR_CLKDIV_1)

+/*!< 4 RNG clock cycles per internal RNG clock    */

+#define RNG_CLKDIV_BY_8       (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)

+/*!< 8 RNG clock cycles per internal RNG clock    */

+#define RNG_CLKDIV_BY_16      (RNG_CR_CLKDIV_2)

+/*!< 16 RNG clock cycles per internal RNG clock   */

+#define RNG_CLKDIV_BY_32      (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)

+/*!< 32 RNG clock cycles per internal RNG clock   */

+#define RNG_CLKDIV_BY_64      (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)

+/*!< 64 RNG clock cycles per internal RNG clock   */

+#define RNG_CLKDIV_BY_128     (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)

+/*!< 128 RNG clock cycles per internal RNG clock  */

+#define RNG_CLKDIV_BY_256     (RNG_CR_CLKDIV_3)

+/*!< 256 RNG clock cycles per internal RNG clock  */

+#define RNG_CLKDIV_BY_512     (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0)

+/*!< 512 RNG clock cycles per internal RNG clock  */

+#define RNG_CLKDIV_BY_1024    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1)

+/*!< 1024 RNG clock cycles per internal RNG clock */

+#define RNG_CLKDIV_BY_2048    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)

+/*!< 2048 RNG clock cycles per internal RNG clock  */

+#define RNG_CLKDIV_BY_4096    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2)

+/*!< 4096 RNG clock cycles per internal RNG clock  */

+#define RNG_CLKDIV_BY_8192    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)

+/*!< 8192 RNG clock cycles per internal RNG clock  */

+#define RNG_CLKDIV_BY_16384   (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)

+/*!< 16384 RNG clock cycles per internal RNG clock */

+#define RNG_CLKDIV_BY_32768   (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)

+/*!< 32768 RNG clock cycles per internal RNG clock */

+/**

+  * @}

+  */

+

+/** @defgroup RNGEX_NIST_Compliance  NIST Compliance configuration

+  * @{

+  */

+#define RNG_NIST_COMPLIANT     (0x00000000UL) /*!< NIST compliant configuration*/

+#define RNG_CUSTOM_NIST        (RNG_CR_NISTC) /*!< Custom NIST configuration */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private types -------------------------------------------------------------*/

+/** @defgroup RNGEx_Private_Types RNGEx Private Types

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private variables ---------------------------------------------------------*/

+/** @defgroup RNGEx_Private_Variables RNGEx Private Variables

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup RNGEx_Private_Constants RNGEx Private Constants

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup RNGEx_Private_Macros RNGEx Private Macros

+  * @{

+  */

+

+#define IS_RNG_CLOCK_DIVIDER(__CLOCK_DIV__) (((__CLOCK_DIV__) == RNG_CLKDIV_BY_1)     || \

+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_2)     || \

+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_4)     || \

+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_8)     || \

+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_16)    || \

+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_32)    || \

+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_64)    || \

+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_128)   || \

+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_256)   || \

+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_512)   || \

+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_1024)  || \

+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_2048)  || \

+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_4096)  || \

+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_8192)  || \

+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_16384) || \

+                                             ((__CLOCK_DIV__) == RNG_CLKDIV_BY_32768))

+

+

+#define IS_RNG_NIST_COMPLIANCE(__NIST_COMPLIANCE__) (((__NIST_COMPLIANCE__) == RNG_NIST_COMPLIANT) || \

+                                                     ((__NIST_COMPLIANCE__) == RNG_CUSTOM_NIST))

+

+#define IS_RNG_CONFIG1(__CONFIG1__) ((__CONFIG1__) <= 0x3FUL)

+

+#define IS_RNG_CONFIG2(__CONFIG2__) ((__CONFIG2__) <= 0x07UL)

+

+#define IS_RNG_CONFIG3(__CONFIG3__) ((__CONFIG3__) <= 0xFUL)

+

+

+/**

+ * @}

+ */

+

+/* Private functions ---------------------------------------------------------*/

+/** @defgroup RNGEx_Private_Functions RNGEx Private Functions

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup RNGEx_Exported_Functions RNGEx Exported Functions

+  * @{

+  */

+

+/** @addtogroup RNGEx_Exported_Functions_Group1

+  * @{

+  */

+HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf);

+HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf);

+HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif  /* CONDRST */

+#endif /* RNG */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+

+#endif /* STM32H7xx_HAL_RNGEX_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_rtc.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_rtc.h
new file mode 100644
index 0000000000..ddc3eab005
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_rtc.h
@@ -0,0 +1,1241 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_rtc.h

+  * @author  MCD Application Team

+  * @brief   Header file of RTC HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_RTC_H

+#define STM32H7xx_HAL_RTC_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @defgroup RTC RTC

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup RTC_Exported_Types RTC Exported Types

+  * @{

+  */

+

+/**

+  * @brief  HAL State structures definition

+  */

+typedef enum

+{

+  HAL_RTC_STATE_RESET             = 0x00U,  /*!< RTC not yet initialized or disabled */

+  HAL_RTC_STATE_READY             = 0x01U,  /*!< RTC initialized and ready for use   */

+  HAL_RTC_STATE_BUSY              = 0x02U,  /*!< RTC process is ongoing              */

+  HAL_RTC_STATE_TIMEOUT           = 0x03U,  /*!< RTC timeout state                   */

+  HAL_RTC_STATE_ERROR             = 0x04U   /*!< RTC error state                     */

+

+} HAL_RTCStateTypeDef;

+

+/**

+  * @brief  RTC Configuration Structure definition

+  */

+typedef struct

+{

+  uint32_t HourFormat;      /*!< Specifies the RTC Hour Format.

+                                 This parameter can be a value of @ref RTC_Hour_Formats */

+

+  uint32_t AsynchPrediv;    /*!< Specifies the RTC Asynchronous Predivider value.

+                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */

+

+  uint32_t SynchPrediv;     /*!< Specifies the RTC Synchronous Predivider value.

+                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */

+

+  uint32_t OutPut;          /*!< Specifies which signal will be routed to the RTC output.

+                                 This parameter can be a value of @ref RTCEx_Output_selection_Definitions */

+

+  uint32_t OutPutRemap;     /*!< Specifies the remap for RTC output.

+                                 This parameter can be a value of @ref  RTC_Output_ALARM_OUT_Remap */

+

+  uint32_t OutPutPolarity;  /*!< Specifies the polarity of the output signal.

+                                 This parameter can be a value of @ref RTC_Output_Polarity_Definitions */

+

+  uint32_t OutPutType;      /*!< Specifies the RTC Output Pin mode.

+                                 This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */

+#if defined(RTC_CR_TAMPALRM_PU)

+  uint32_t OutPutPullUp;    /*!< Specifies the RTC Output Pull-Up mode.

+                                 This parameter can be a value of @ref RTC_Output_PullUp_ALARM_OUT */

+#endif /* RTC_CR_TAMPALRM_PU */

+} RTC_InitTypeDef;

+

+/**

+  * @brief  RTC Time structure definition

+  */

+typedef struct

+{

+  uint8_t Hours;            /*!< Specifies the RTC Time Hour.

+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected.

+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected */

+

+  uint8_t Minutes;          /*!< Specifies the RTC Time Minutes.

+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */

+

+  uint8_t Seconds;          /*!< Specifies the RTC Time Seconds.

+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */

+

+  uint8_t TimeFormat;       /*!< Specifies the RTC AM/PM Time.

+                                 This parameter can be a value of @ref RTC_AM_PM_Definitions */

+

+  uint32_t SubSeconds;     /*!< Specifies the RTC_SSR RTC Sub Second register content.

+                                 This parameter corresponds to a time unit range between [0-1] Second

+                                 with [1 Sec / SecondFraction +1] granularity */

+

+  uint32_t SecondFraction;  /*!< Specifies the range or granularity of Sub Second register content

+                                 corresponding to Synchronous pre-scaler factor value (PREDIV_S)

+                                 This parameter corresponds to a time unit range between [0-1] Second

+                                 with [1 Sec / SecondFraction +1] granularity.

+                                 This field will be used only by HAL_RTC_GetTime function */

+

+  uint32_t DayLightSaving;  /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment.

+                                 This parameter can be a value of @ref RTC_DayLightSaving_Definitions */

+

+  uint32_t StoreOperation;  /*!< Specifies RTC_StoreOperation value to be written in the BKP bit

+                                 in CR register to store the operation.

+                                 This parameter can be a value of @ref RTC_StoreOperation_Definitions */

+} RTC_TimeTypeDef;

+

+/**

+  * @brief  RTC Date structure definition

+  */

+typedef struct

+{

+  uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.

+                         This parameter can be a value of @ref RTC_WeekDay_Definitions */

+

+  uint8_t Month;    /*!< Specifies the RTC Date Month (in BCD format).

+                         This parameter can be a value of @ref RTC_Month_Date_Definitions */

+

+  uint8_t Date;     /*!< Specifies the RTC Date.

+                         This parameter must be a number between Min_Data = 1 and Max_Data = 31 */

+

+  uint8_t Year;     /*!< Specifies the RTC Date Year.

+                         This parameter must be a number between Min_Data = 0 and Max_Data = 99 */

+

+} RTC_DateTypeDef;

+

+/**

+  * @brief  RTC Alarm structure definition

+  */

+typedef struct

+{

+  RTC_TimeTypeDef AlarmTime;     /*!< Specifies the RTC Alarm Time members */

+

+  uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.

+                                      This parameter can be a value of @ref RTC_AlarmMask_Definitions */

+

+  uint32_t AlarmSubSecondMask;   /*!< Specifies the RTC Alarm SubSeconds Masks.

+                                      This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */

+

+  uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.

+                                     This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */

+

+  uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.

+                                      If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.

+                                      If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */

+

+  uint32_t Alarm;                /*!< Specifies the alarm .

+                                      This parameter can be a value of @ref RTC_Alarms_Definitions */

+} RTC_AlarmTypeDef;

+

+/**

+  * @brief  RTC Handle Structure definition

+  */

+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)

+typedef struct __RTC_HandleTypeDef

+#else

+typedef struct

+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */

+{

+  RTC_TypeDef               *Instance;  /*!< Register base address    */

+

+  RTC_InitTypeDef           Init;       /*!< RTC required parameters  */

+

+  HAL_LockTypeDef           Lock;       /*!< RTC locking object       */

+

+  __IO HAL_RTCStateTypeDef  State;      /*!< Time communication state */

+

+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)

+  void (* AlarmAEventCallback)(struct __RTC_HandleTypeDef *hrtc);            /*!< RTC Alarm A Event callback         */

+

+  void (* AlarmBEventCallback)(struct __RTC_HandleTypeDef *hrtc);            /*!< RTC Alarm B Event callback         */

+

+  void (* TimeStampEventCallback)(struct __RTC_HandleTypeDef *hrtc);         /*!< RTC TimeStamp Event callback       */

+

+  void (* WakeUpTimerEventCallback)(struct __RTC_HandleTypeDef *hrtc);       /*!< RTC WakeUpTimer Event callback     */

+

+  void (* Tamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc);         /*!< RTC Tamper 1 Event callback        */

+

+  void (* Tamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc);         /*!< RTC Tamper 2 Event callback        */

+

+  void (* Tamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc);         /*!< RTC Tamper 3 Event callback        */

+

+#if defined(TAMP_CR1_ITAMP1E)

+  void (* InternalTamper1EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 1 Event callback  */

+#endif /* TAMP_CR1_ITAMP1E */

+

+#if defined(TAMP_CR1_ITAMP2E)

+  void (* InternalTamper2EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 2 Event callback  */

+#endif /* TAMP_CR1_ITAMP2E */

+

+#if defined(TAMP_CR1_ITAMP3E)

+  void (* InternalTamper3EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 3 Event callback  */

+#endif /* TAMP_CR1_ITAMP3E */

+

+#if defined(TAMP_CR1_ITAMP4E)

+  void (* InternalTamper4EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 4 Event callback  */

+#endif /* TAMP_CR1_ITAMP4E */

+

+#if defined(TAMP_CR1_ITAMP5E)

+  void (* InternalTamper5EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 5 Event callback  */

+#endif /* TAMP_CR1_ITAMP5E */

+

+#if defined(TAMP_CR1_ITAMP6E)

+  void (* InternalTamper6EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 6 Event callback  */

+#endif /* TAMP_CR1_ITAMP6E */

+

+#if defined(TAMP_CR1_ITAMP8E)

+  void (* InternalTamper8EventCallback)(struct __RTC_HandleTypeDef *hrtc);           /*!< RTC Internal Tamper 8 Event callback  */

+#endif /* TAMP_CR1_ITAMP8E */

+

+  void (* MspInitCallback)(struct __RTC_HandleTypeDef *hrtc);                /*!< RTC Msp Init callback              */

+

+  void (* MspDeInitCallback)(struct __RTC_HandleTypeDef *hrtc);              /*!< RTC Msp DeInit callback            */

+

+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */

+

+} RTC_HandleTypeDef;

+

+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  HAL RTC Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_RTC_ALARM_A_EVENT_CB_ID           = 0u,    /*!< RTC Alarm A Event Callback ID      */

+  HAL_RTC_ALARM_B_EVENT_CB_ID           = 1u,    /*!< RTC Alarm B Event Callback ID      */

+  HAL_RTC_TIMESTAMP_EVENT_CB_ID         = 2u,    /*!< RTC TimeStamp Event Callback ID    */

+  HAL_RTC_WAKEUPTIMER_EVENT_CB_ID       = 3u,    /*!< RTC WakeUp Timer Event Callback ID */

+  HAL_RTC_TAMPER1_EVENT_CB_ID           = 4u,    /*!< RTC Tamper 1 Callback ID           */

+  HAL_RTC_TAMPER2_EVENT_CB_ID           = 5u,    /*!< RTC Tamper 2 Callback ID           */

+  HAL_RTC_TAMPER3_EVENT_CB_ID           = 6u,    /*!< RTC Tamper 3 Callback ID           */

+

+#if defined(TAMP_CR1_ITAMP1E)

+  HAL_RTC_INTERNAL_TAMPER1_EVENT_CB_ID  = 12u,   /*!< RTC Internal Tamper 1 Callback ID  */

+#endif /* TAMP_CR1_ITAMP1E */

+#if defined(TAMP_CR1_ITAMP2E)

+  HAL_RTC_INTERNAL_TAMPER2_EVENT_CB_ID  = 13u,   /*!< RTC Internal Tamper 2 Callback ID  */

+#endif /* TAMP_CR1_ITAMP2E */

+#if defined(TAMP_CR1_ITAMP3E)

+  HAL_RTC_INTERNAL_TAMPER3_EVENT_CB_ID  = 14u,   /*!< RTC Internal Tamper 3 Callback ID  */

+#endif /* TAMP_CR1_ITAMP3E */

+#if defined(TAMP_CR1_ITAMP4E)

+  HAL_RTC_INTERNAL_TAMPER4_EVENT_CB_ID  = 15u,   /*!< RTC Internal Tamper 4 Callback ID  */

+#endif /* TAMP_CR1_ITAMP4E */

+#if defined(TAMP_CR1_ITAMP5E)

+  HAL_RTC_INTERNAL_TAMPER5_EVENT_CB_ID  = 16u,   /*!< RTC Internal Tamper 5 Callback ID  */

+#endif /* TAMP_CR1_ITAMP5E */

+#if defined(TAMP_CR1_ITAMP6E)

+  HAL_RTC_INTERNAL_TAMPER6_EVENT_CB_ID  = 17u,   /*!< RTC Internal Tamper 6 Callback ID  */

+#endif /* TAMP_CR1_ITAMP6E */

+#if defined(TAMP_CR1_ITAMP8E)

+  HAL_RTC_INTERNAL_TAMPER8_EVENT_CB_ID  = 19u,   /*!< RTC Internal Tamper 8 Callback ID  */

+#endif /* TAMP_CR1_ITAMP8E */

+  HAL_RTC_MSPINIT_CB_ID                 = 20u,   /*!< RTC Msp Init callback ID           */

+  HAL_RTC_MSPDEINIT_CB_ID               = 21u    /*!< RTC Msp DeInit callback ID         */

+} HAL_RTC_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL RTC Callback pointer definition

+  */

+typedef  void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc);  /*!< pointer to an RTC callback function */

+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup RTC_Exported_Constants RTC Exported Constants

+  * @{

+  */

+

+/** @defgroup RTC_Hour_Formats_Definitions RTC Hour Formats Definitions

+  * @{

+  */

+#define RTC_HOURFORMAT_24              0x00000000u

+#define RTC_HOURFORMAT_12              RTC_CR_FMT

+/**

+  * @}

+  */

+

+/** @defgroup RTC_Output_selection_Definitions RTC Output Selection Definitions

+  * @{

+  */

+#define RTC_OUTPUT_DISABLE             0x00000000u

+#define RTC_OUTPUT_ALARMA              RTC_CR_OSEL_0

+#define RTC_OUTPUT_ALARMB              RTC_CR_OSEL_1

+#define RTC_OUTPUT_WAKEUP              RTC_CR_OSEL

+#if defined(RTC_CR_TAMPOE)

+#define RTC_OUTPUT_TAMPER              RTC_CR_TAMPOE

+#endif /* RTC_CR_TAMPOE */

+/**

+  * @}

+  */

+

+/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions

+  * @{

+  */

+#define RTC_OUTPUT_POLARITY_HIGH       0x00000000u

+#define RTC_OUTPUT_POLARITY_LOW        RTC_CR_POL

+/**

+  * @}

+  */

+

+/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT

+  * @{

+  */

+#if defined(RTC_CR_TAMPALRM_TYPE)

+#define RTC_OUTPUT_TYPE_PUSHPULL       0x00000000u

+#define RTC_OUTPUT_TYPE_OPENDRAIN      RTC_CR_TAMPALRM_TYPE

+#define RTC_ALARM_OUTPUT_TYPE          RTC_CR_TAMPALRM_TYPE

+#endif /* RTC_CR_TAMPALRM_TYPE */

+

+#if defined(RTC_OR_ALARMOUTTYPE)

+#define RTC_OUTPUT_TYPE_PUSHPULL       RTC_OR_ALARMOUTTYPE

+#define RTC_OUTPUT_TYPE_OPENDRAIN      0x00000000u

+#define RTC_ALARM_OUTPUT_TYPE          RTC_OR_ALARMOUTTYPE

+#endif /* RTC_OR_ALARMOUTTYPE */

+/**

+  * @}

+  */

+

+/** @defgroup RTC_Output_PullUp_ALARM_OUT RTC Output Pull-Up ALARM OUT

+  * @{

+  */

+#if defined(RTC_CR_TAMPALRM_PU)

+#define RTC_OUTPUT_PULLUP_NONE         0x00000000u

+#define RTC_OUTPUT_PULLUP_ON           RTC_CR_TAMPALRM_PU

+#endif /* RTC_CR_TAMPALRM_PU */

+/**

+  * @}

+  */

+

+/** @defgroup RTC_Output_ALARM_OUT_Remap RTC Output ALARM OUT Remap

+  * @{

+  */

+#if defined(RTC_CR_OUT2EN)

+#define RTC_OUTPUT_REMAP_NONE          0x00000000u

+#define RTC_OUTPUT_REMAP_POS1          RTC_CR_OUT2EN

+#endif /* RTC_CR_OUT2EN */

+

+#if defined(RTC_OR_OUT_RMP)

+#define RTC_OUTPUT_REMAP_NONE          0x00000000u

+#define RTC_OUTPUT_REMAP_POS1          RTC_OR_OUT_RMP

+#endif /* RTC_OR_OUT_RMP */

+/**

+  * @}

+  */

+

+/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions

+  * @{

+  */

+#define RTC_HOURFORMAT12_AM            ((uint8_t)0x00)

+#define RTC_HOURFORMAT12_PM            ((uint8_t)0x01)

+/**

+  * @}

+  */

+

+/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions

+  * @{

+  */

+#define RTC_DAYLIGHTSAVING_SUB1H       RTC_CR_SUB1H

+#define RTC_DAYLIGHTSAVING_ADD1H       RTC_CR_ADD1H

+#define RTC_DAYLIGHTSAVING_NONE        0x00000000u

+/**

+  * @}

+  */

+

+/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions

+  * @{

+  */

+#define RTC_STOREOPERATION_RESET        0x00000000u

+#define RTC_STOREOPERATION_SET          RTC_CR_BKP

+/**

+  * @}

+  */

+

+/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions

+  * @{

+  */

+#define RTC_FORMAT_BIN                  0x00000000u

+#define RTC_FORMAT_BCD                  0x00000001u

+/**

+  * @}

+  */

+

+/** @defgroup RTC_Month_Date_Definitions RTC Month Date Definitions (in BCD format)

+  * @{

+  */

+#define RTC_MONTH_JANUARY                   ((uint8_t)0x01)

+#define RTC_MONTH_FEBRUARY                  ((uint8_t)0x02)

+#define RTC_MONTH_MARCH                     ((uint8_t)0x03)

+#define RTC_MONTH_APRIL                     ((uint8_t)0x04)

+#define RTC_MONTH_MAY                       ((uint8_t)0x05)

+#define RTC_MONTH_JUNE                      ((uint8_t)0x06)

+#define RTC_MONTH_JULY                      ((uint8_t)0x07)

+#define RTC_MONTH_AUGUST                    ((uint8_t)0x08)

+#define RTC_MONTH_SEPTEMBER                 ((uint8_t)0x09)

+#define RTC_MONTH_OCTOBER                   ((uint8_t)0x10)

+#define RTC_MONTH_NOVEMBER                  ((uint8_t)0x11)

+#define RTC_MONTH_DECEMBER                  ((uint8_t)0x12)

+

+/**

+  * @}

+  */

+

+/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions

+  * @{

+  */

+#define RTC_WEEKDAY_MONDAY                  ((uint8_t)0x01)

+#define RTC_WEEKDAY_TUESDAY                 ((uint8_t)0x02)

+#define RTC_WEEKDAY_WEDNESDAY               ((uint8_t)0x03)

+#define RTC_WEEKDAY_THURSDAY                ((uint8_t)0x04)

+#define RTC_WEEKDAY_FRIDAY                  ((uint8_t)0x05)

+#define RTC_WEEKDAY_SATURDAY                ((uint8_t)0x06)

+#define RTC_WEEKDAY_SUNDAY                  ((uint8_t)0x07)

+

+/**

+  * @}

+  */

+

+/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions

+  * @{

+  */

+#define RTC_ALARMDATEWEEKDAYSEL_DATE      0x00000000u

+#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY   RTC_ALRMAR_WDSEL

+

+/**

+  * @}

+  */

+

+/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions

+  * @{

+  */

+#define RTC_ALARMMASK_NONE                0x00000000u

+#define RTC_ALARMMASK_DATEWEEKDAY         RTC_ALRMAR_MSK4

+#define RTC_ALARMMASK_HOURS               RTC_ALRMAR_MSK3

+#define RTC_ALARMMASK_MINUTES             RTC_ALRMAR_MSK2

+#define RTC_ALARMMASK_SECONDS             RTC_ALRMAR_MSK1

+#define RTC_ALARMMASK_ALL                 (RTC_ALARMMASK_DATEWEEKDAY | \

+                                           RTC_ALARMMASK_HOURS       | \

+                                           RTC_ALARMMASK_MINUTES     | \

+                                           RTC_ALARMMASK_SECONDS)

+/**

+  * @}

+  */

+

+/** @defgroup RTC_Alarms_Definitions RTC Alarms Definitions

+  * @{

+  */

+#define RTC_ALARM_A                       RTC_CR_ALRAE

+#define RTC_ALARM_B                       RTC_CR_ALRBE

+/**

+  * @}

+  */

+

+/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions

+  * @{

+  */

+/*!< All Alarm SS fields are masked. There is no comparison on sub seconds for Alarm */

+#define RTC_ALARMSUBSECONDMASK_ALL         0x00000000u

+/*!< SS[14:1] are don't care in Alarm comparison. Only SS[0] is compared.     */

+#define RTC_ALARMSUBSECONDMASK_SS14_1      RTC_ALRMASSR_MASKSS_0

+/*!< SS[14:2] are don't care in Alarm comparison. Only SS[1:0] are compared.  */

+#define RTC_ALARMSUBSECONDMASK_SS14_2      RTC_ALRMASSR_MASKSS_1

+/*!< SS[14:3] are don't care in Alarm comparison. Only SS[2:0] are compared.  */

+#define RTC_ALARMSUBSECONDMASK_SS14_3      (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1)

+/*!< SS[14:4] are don't care in Alarm comparison. Only SS[3:0] are compared.  */

+#define RTC_ALARMSUBSECONDMASK_SS14_4      RTC_ALRMASSR_MASKSS_2

+/*!< SS[14:5] are don't care in Alarm comparison. Only SS[4:0] are compared.  */

+#define RTC_ALARMSUBSECONDMASK_SS14_5      (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2)

+/*!< SS[14:6] are don't care in Alarm comparison. Only SS[5:0] are compared.  */

+#define RTC_ALARMSUBSECONDMASK_SS14_6      (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)

+/*!< SS[14:7] are don't care in Alarm comparison. Only SS[6:0] are compared.  */

+#define RTC_ALARMSUBSECONDMASK_SS14_7      (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2)

+/*!< SS[14:8] are don't care in Alarm comparison. Only SS[7:0] are compared.  */

+#define RTC_ALARMSUBSECONDMASK_SS14_8      RTC_ALRMASSR_MASKSS_3

+/*!< SS[14:9] are don't care in Alarm comparison. Only SS[8:0] are compared.  */

+#define RTC_ALARMSUBSECONDMASK_SS14_9      (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_3)

+/*!< SS[14:10] are don't care in Alarm comparison. Only SS[9:0] are compared. */

+#define RTC_ALARMSUBSECONDMASK_SS14_10     (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)

+/*!< SS[14:11] are don't care in Alarm comparison. Only SS[10:0] are compared. */

+#define RTC_ALARMSUBSECONDMASK_SS14_11     (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_3)

+/*!< SS[14:12] are don't care in Alarm comparison. Only SS[11:0] are compared. */

+#define RTC_ALARMSUBSECONDMASK_SS14_12     (RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)

+/*!< SS[14:13] are don't care in Alarm comparison. Only SS[12:0] are compared. */

+#define RTC_ALARMSUBSECONDMASK_SS14_13     (RTC_ALRMASSR_MASKSS_0 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)

+/*!< SS[14] is don't care in Alarm comparison. Only SS[13:0] are compared. */

+#define RTC_ALARMSUBSECONDMASK_SS14        (RTC_ALRMASSR_MASKSS_1 | RTC_ALRMASSR_MASKSS_2 | RTC_ALRMASSR_MASKSS_3)

+/*!< SS[14:0] are compared and must match to activate alarm. */

+#define RTC_ALARMSUBSECONDMASK_NONE        RTC_ALRMASSR_MASKSS

+

+/**

+  * @}

+  */

+

+/** @defgroup RTC_Interrupts_Definitions RTC Interrupts Definitions

+  * @{

+  */

+#define RTC_IT_TS                         RTC_CR_TSIE         /*!< Enable Timestamp Interrupt               */

+#define RTC_IT_WUT                        RTC_CR_WUTIE        /*!< Enable Wakeup timer Interrupt            */

+#define RTC_IT_ALRA                       RTC_CR_ALRAIE       /*!< Enable Alarm A Interrupt                 */

+#define RTC_IT_ALRB                       RTC_CR_ALRBIE       /*!< Enable Alarm B Interrupt                 */

+/**

+  * @}

+  */

+

+/** @defgroup RTC_Flags_Definitions RTC Flags Definitions

+  * @{

+  */

+#if defined(RTC_ICSR_RECALPF)

+#define RTC_FLAG_RECALPF                  RTC_ICSR_RECALPF  /*!< Recalibration pending Flag */

+#endif /* RTC_ICSR_RECALPF */

+#if defined(RTC_ICSR_INITF)

+#define RTC_FLAG_INITF                    RTC_ICSR_INITF    /*!< Initialization pending flag */

+#endif /* RTC_ICSR_INITF */

+#if defined(RTC_ICSR_RSF)

+#define RTC_FLAG_RSF                      RTC_ICSR_RSF      /*!< Registers synchronization flag */

+#endif /* RTC_ICSR_RSF */

+#if defined(RTC_ICSR_INITS)

+#define RTC_FLAG_INITS                    RTC_ICSR_INITS    /*!< Initialization status flag */

+#endif /* RTC_ICSR_INITS */

+#if defined(RTC_ICSR_SHPF)

+#define RTC_FLAG_SHPF                     RTC_ICSR_SHPF     /*!< Shift operation pending flag */

+#endif /* RTC_ICSR_SHPF */

+#if defined(RTC_ICSR_WUTWF)

+#define RTC_FLAG_WUTWF                    RTC_ICSR_WUTWF    /*!< Wakeup timer write operation pending flag */

+#endif /* RTC_ICSR_WUTWF */

+#if defined(RTC_ICSR_ALRBWF)

+#define RTC_FLAG_ALRBWF                   RTC_ICSR_ALRBWF   /*!< Alarm B write operation pending flag */

+#endif /* RTC_ICSR_ALRBWF */

+#if defined(RTC_ICSR_ALRAWF)

+#define RTC_FLAG_ALRAWF                   RTC_ICSR_ALRAWF   /*!< Alarm A write operation pending flag */

+#endif /* RTC_ICSR_ALRAWF */

+#if defined(RTC_SR_ITSF)

+#define RTC_FLAG_ITSF                     RTC_SR_ITSF       /*!< Internal Time-stamp flag */

+#endif /* RTC_SR_ITSF */

+#if defined(RTC_SR_TSOVF)

+#define RTC_FLAG_TSOVF                    RTC_SR_TSOVF      /*!< Time-stamp overflow flag */

+#endif /* RTC_SR_TSOVF */

+#if defined(RTC_SR_TSF)

+#define RTC_FLAG_TSF                      RTC_SR_TSF        /*!< Time-stamp flag */

+#endif /* RTC_SR_TSF */

+#if defined(RTC_SR_WUTF)

+#define RTC_FLAG_WUTF                     RTC_SR_WUTF       /*!< Wakeup timer flag */

+#endif /* RTC_SR_WUTF */

+#if defined(RTC_SR_ALRBF)

+#define RTC_FLAG_ALRBF                    RTC_SR_ALRBF      /*!< Alarm B flag */

+#endif /* RTC_SR_ALRBF */

+#if defined(RTC_SR_ALRAF)

+#define RTC_FLAG_ALRAF                    RTC_SR_ALRAF      /*!< Alarm A flag */

+#endif /* RTC_SR_ALRAF */

+/**

+  * @}

+  */

+

+/** @defgroup RTC_Clear_Flags_Definitions RTC Clear Flags Definitions

+  * @{

+  */

+#if defined(RTC_SCR_CITSF)

+#define RTC_CLEAR_ITSF                      RTC_SCR_CITSF    /*!< Clear Internal Time-stamp flag */

+#endif /* RTC_SCR_CITSF */

+#if defined(RTC_SCR_CTSOVF)

+#define RTC_CLEAR_TSOVF                     RTC_SCR_CTSOVF   /*!< Clear Time-stamp overflow flag */

+#endif /* RTC_SCR_CTSOVF */

+#if defined(RTC_SCR_CTSF)

+#define RTC_CLEAR_TSF                       RTC_SCR_CTSF     /*!< Clear Time-stamp flag */

+#endif /* RTC_SCR_CTSF */

+#if defined(RTC_SCR_CWUTF)

+#define RTC_CLEAR_WUTF                      RTC_SCR_CWUTF    /*!< Clear Wakeup timer flag */

+#endif /* RTC_SCR_CWUTF */

+#if defined(RTC_SCR_CALRBF)

+#define RTC_CLEAR_ALRBF                     RTC_SCR_CALRBF   /*!< Clear Alarm B flag */

+#endif /* RTC_SCR_CALRBF */

+#if defined(RTC_SCR_CALRAF)

+#define RTC_CLEAR_ALRAF                     RTC_SCR_CALRAF   /*!< Clear Alarm A flag */

+#endif /* RTC_SCR_CALRAF */

+/**

+  * @}

+  */

+

+/** @defgroup RTC_Flags_Definitions RTC Flags Definitions

+  * @{

+  */

+#if defined(RTC_ISR_RECALPF)

+#define RTC_FLAG_RECALPF                  RTC_ISR_RECALPF

+#endif /* RTC_ISR_RECALPF */

+#if defined(RTC_ISR_TSOVF)

+#define RTC_FLAG_TSOVF                    RTC_ISR_TSOVF

+#endif /* RTC_ISR_TSOVF */

+#if defined(RTC_ISR_TSF)

+#define RTC_FLAG_TSF                      RTC_ISR_TSF

+#endif /* RTC_ISR_TSF */

+#if defined(RTC_ISR_ITSF)

+#define RTC_FLAG_ITSF                     RTC_ISR_ITSF

+#endif /* RTC_ISR_ITSF */

+#if defined(RTC_ISR_WUTF)

+#define RTC_FLAG_WUTF                     RTC_ISR_WUTF

+#endif /* RTC_ISR_WUTF */

+#if defined(RTC_ISR_ALRBF)

+#define RTC_FLAG_ALRBF                    RTC_ISR_ALRBF

+#endif /* RTC_ISR_ALRBF */

+#if defined(RTC_ISR_ALRAF)

+#define RTC_FLAG_ALRAF                    RTC_ISR_ALRAF

+#endif /* RTC_ISR_ALRAF */

+#if defined(RTC_ISR_INITF)

+#define RTC_FLAG_INITF                    RTC_ISR_INITF

+#endif /* RTC_ISR_INITF */

+#if defined(RTC_ISR_RSF)

+#define RTC_FLAG_RSF                      RTC_ISR_RSF

+#endif /* RTC_ISR_RSF */

+#if defined(RTC_ISR_INITS)

+#define RTC_FLAG_INITS                    RTC_ISR_INITS

+#endif /* RTC_ISR_INITS */

+#if defined(RTC_ISR_SHPF)

+#define RTC_FLAG_SHPF                     RTC_ISR_SHPF

+#endif /* RTC_ISR_SHPF */

+#if defined(RTC_ISR_WUTWF)

+#define RTC_FLAG_WUTWF                    RTC_ISR_WUTWF

+#endif /* RTC_ISR_WUTWF */

+#if defined(RTC_ISR_ALRBWF)

+#define RTC_FLAG_ALRBWF                   RTC_ISR_ALRBWF

+#endif /* RTC_ISR_ALRBWF */

+#if defined(RTC_ISR_ALRAWF)

+#define RTC_FLAG_ALRAWF                   RTC_ISR_ALRAWF

+#endif /* RTC_ISR_ALRAWF */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macros -----------------------------------------------------------*/

+/** @defgroup RTC_Exported_Macros RTC Exported Macros

+  * @{

+  */

+

+/** @brief Reset RTC handle state

+  * @param  __HANDLE__ RTC handle.

+  * @retval None

+  */

+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)

+#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) do{                                              \

+                                                      (__HANDLE__)->State = HAL_RTC_STATE_RESET;  \

+                                                      (__HANDLE__)->MspInitCallback = NULL;       \

+                                                      (__HANDLE__)->MspDeInitCallback = NULL;     \

+                                                     }while(0u)

+#else

+#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)

+#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */

+

+/**

+  * @brief  Disable the write protection for RTC registers.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @retval None

+  */

+#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)              \

+                        do{                                        \

+                            (__HANDLE__)->Instance->WPR = 0xCAU;   \

+                            (__HANDLE__)->Instance->WPR = 0x53U;   \

+                          } while(0u)

+

+/**

+  * @brief  Enable the write protection for RTC registers.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @retval None

+  */

+#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)               \

+                        do{                                        \

+                            (__HANDLE__)->Instance->WPR = 0xFFU;   \

+                          } while(0u)

+

+/**

+  * @brief  Add 1 hour (summer time change).

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @param  __BKP__ Backup

+  *         This parameter can be:

+  *            @arg @ref RTC_STOREOPERATION_RESET

+  *            @arg @ref RTC_STOREOPERATION_SET

+  * @retval None

+  */

+#define __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H(__HANDLE__, __BKP__)                           \

+                        do {                                                                \

+                            __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__);                  \

+                            SET_BIT((__HANDLE__)->Instance->CR, RTC_CR_ADD1H);              \

+                            MODIFY_REG((__HANDLE__)->Instance->CR, RTC_CR_BKP , (__BKP__)); \

+                            __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__);                   \

+                        } while(0u);

+

+/**

+  * @brief  Subtract 1 hour (winter time change).

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @param  __BKP__ Backup

+  *         This parameter can be:

+  *            @arg @ref RTC_STOREOPERATION_RESET

+  *            @arg @ref RTC_STOREOPERATION_SET

+  * @retval None

+  */

+#define __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H(__HANDLE__, __BKP__)                           \

+                        do {                                                                \

+                            __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__);                  \

+                            SET_BIT((__HANDLE__)->Instance->CR, RTC_CR_SUB1H);              \

+                            MODIFY_REG((__HANDLE__)->Instance->CR, RTC_CR_BKP , (__BKP__)); \

+                            __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__);                   \

+                        } while(0u);

+

+/**

+  * @brief  Enable the RTC ALARMA peripheral.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @retval None

+  */

+#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))

+

+/**

+  * @brief  Disable the RTC ALARMA peripheral.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @retval None

+  */

+#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__)                         ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))

+

+/**

+  * @brief  Enable the RTC ALARMB peripheral.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @retval None

+  */

+#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))

+

+/**

+  * @brief  Disable the RTC ALARMB peripheral.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @retval None

+  */

+#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__)                         ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))

+

+/**

+  * @brief  Enable the RTC Alarm interrupt.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.

+  *          This parameter can be any combination of the following values:

+  *             @arg @ref RTC_IT_ALRA Alarm A interrupt

+  *             @arg @ref RTC_IT_ALRB Alarm B interrupt

+  * @retval None

+  */

+#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

+

+/**

+  * @brief  Disable the RTC Alarm interrupt.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.

+  *         This parameter can be any combination of the following values:

+  *            @arg @ref RTC_IT_ALRA Alarm A interrupt

+  *            @arg @ref RTC_IT_ALRB Alarm B interrupt

+  * @retval None

+  */

+#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__)        ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

+

+/**

+  * @brief  Check whether the specified RTC Alarm interrupt has occurred or not.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.

+  *         This parameter can be:

+  *            @arg @ref RTC_IT_ALRA Alarm A interrupt

+  *            @arg @ref RTC_IT_ALRB Alarm B interrupt

+  * @retval None

+  */

+#if defined(RTC_MISR_ALRAMF)

+#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->MISR)& (__INTERRUPT__ >> 12)) != 0U)? 1U : 0U)

+#endif /* RTC_MISR_ALRAMF */

+#if defined(RTC_ISR_ALRAF)

+#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->ISR)& (__INTERRUPT__ >> 4)) != 0U)? 1U : 0U)

+#endif /* RTC_ISR_ALRAF */

+

+/**

+  * @brief  Check whether the specified RTC Alarm interrupt has been enabled or not.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @param  __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.

+  *         This parameter can be:

+  *            @arg @ref RTC_IT_ALRA Alarm A interrupt

+  *            @arg @ref RTC_IT_ALRB Alarm B interrupt

+  * @retval None

+  */

+#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)

+

+#if defined(RTC_SR_ALRAF)

+/**

+  * @brief  Get the selected RTC Alarm's flag status.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @param  __FLAG__ specifies the RTC Alarm Flag sources to check.

+  *         This parameter can be:

+  *            @arg @ref RTC_FLAG_ALRAF

+  *            @arg @ref RTC_FLAG_ALRBF

+  * @retval None

+  */

+#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)               (((((__HANDLE__)->Instance->SR)  & (__FLAG__)) != 0U) ? 1U : 0U)

+#endif /* RTC_SR_ALRAF */

+#if defined(RTC_ISR_ALRAF)

+/**

+  * @brief  Get the selected RTC Alarm's flag status.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @param  __FLAG__ specifies the RTC Alarm Flag sources to check.

+  *         This parameter can be:

+  *            @arg @ref RTC_FLAG_ALRAF

+  *            @arg @ref RTC_FLAG_ALRBF

+  *            @arg @ref RTC_FLAG_ALRAWF

+  *            @arg @ref RTC_FLAG_ALRBWF

+  * @retval None

+  */

+#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)               (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)

+#endif /* RTC_ISR_ALRAF */

+

+/**

+  * @brief  Clear the RTC Alarm's pending flags.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @param  __FLAG__ specifies the RTC Alarm Flag sources to clear.

+  *          This parameter can be:

+  *             @arg @ref RTC_FLAG_ALRAF

+  *             @arg @ref RTC_FLAG_ALRBF

+  * @retval None

+  */

+#if defined(RTC_SCR_CALRAF)

+#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)             ((__HANDLE__)->Instance->SCR |= __FLAG__)

+#endif /* RTC_SCR_CALRAF */

+#if defined(RTC_ISR_ALRAF)

+#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)             ((__HANDLE__)->Instance->ISR = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)))

+#endif /* RTC_ISR_ALRAF */

+

+

+/**

+  * @brief  Enable interrupt on the RTC Alarm associated Exti line.

+  * @retval None

+  */

+#if defined(EXTI_D1)

+#define __HAL_RTC_ALARM_EXTI_ENABLE_IT()            (EXTI_D1->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)

+#else  /* EXTI */

+#define __HAL_RTC_ALARM_EXTI_ENABLE_IT()            (EXTI->IMR1    |= RTC_EXTI_LINE_ALARM_EVENT)

+#endif /* EXTI_D1 */

+

+/**

+  * @brief  Disable interrupt on the RTC Alarm associated Exti line.

+  * @retval None

+  */

+#if defined(EXTI_D1)

+#define __HAL_RTC_ALARM_EXTI_DISABLE_IT()           (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))

+#else  /* EXTI */

+#define __HAL_RTC_ALARM_EXTI_DISABLE_IT()           (EXTI->IMR1    &= ~(RTC_EXTI_LINE_ALARM_EVENT))

+#endif /* EXTI_D1 */

+

+/**

+  * @brief  Enable event on the RTC Alarm associated Exti line.

+  * @retval None.

+  */

+#if defined(EXTI_D1)

+#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT()         (EXTI_D1->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)

+#else  /* EXTI */

+#define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT()         (EXTI->EMR1    |= RTC_EXTI_LINE_ALARM_EVENT)

+#endif /* EXTI_D1 */

+

+/**

+  * @brief  Disable event on the RTC Alarm associated Exti line.

+  * @retval None.

+  */

+#if defined(EXTI_D1)

+#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT()         (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))

+#else  /* EXTI */

+#define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT()         (EXTI->EMR1    &= ~(RTC_EXTI_LINE_ALARM_EVENT))

+#endif /* EXTI_D1 */

+

+#if defined(DUAL_CORE)

+/**

+  * @brief  Enable interrupt on the RTC Alarm associated D2 Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_ALARM_EXTID2_ENABLE_IT()          (EXTI_D2->IMR1 |= RTC_EXTI_LINE_ALARM_EVENT)

+

+/**

+  * @brief  Disable interrupt on the RTC Alarm associated D2 Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_ALARM_EXTID2_DISABLE_IT()         (EXTI_D2->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))

+

+/**

+  * @brief  Enable event on the RTC Alarm associated D2 Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_ALARM_EXTID2_ENABLE_EVENT()        (EXTI_D2->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT)

+

+/**

+  * @brief  Disable event on the RTC Alarm associated D2 Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_ALARM_EXTID2_DISABLE_EVENT()       (EXTI_D2->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))

+

+#endif

+/**

+  * @brief  Enable falling edge trigger on the RTC Alarm associated Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)

+

+/**

+  * @brief  Disable falling edge trigger on the RTC Alarm associated Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))

+

+/**

+  * @brief  Enable rising edge trigger on the RTC Alarm associated Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR1 |= RTC_EXTI_LINE_ALARM_EVENT)

+

+/**

+  * @brief  Disable rising edge trigger on the RTC Alarm associated Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT))

+

+/**

+  * @brief  Enable rising & falling edge trigger on the RTC Alarm associated Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_ALARM_EXTI_ENABLE_RISING_FALLING_EDGE()  do { \

+                                                             __HAL_RTC_ALARM_EXTI_ENABLE_RISING_EDGE();  \

+                                                             __HAL_RTC_ALARM_EXTI_ENABLE_FALLING_EDGE(); \

+                                                           } while(0u)

+

+/**

+  * @brief  Disable rising & falling edge trigger on the RTC Alarm associated Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_ALARM_EXTI_DISABLE_RISING_FALLING_EDGE() do { \

+                                                             __HAL_RTC_ALARM_EXTI_DISABLE_RISING_EDGE();  \

+                                                             __HAL_RTC_ALARM_EXTI_DISABLE_FALLING_EDGE(); \

+                                                           } while(0u)

+

+/**

+  * @brief Check whether the RTC Alarm associated Exti line interrupt flag is set or not.

+  * @retval Line Status.

+  */

+#if defined(EXTI_D1)

+#define __HAL_RTC_ALARM_EXTI_GET_FLAG()              (EXTI_D1->PR1 & RTC_EXTI_LINE_ALARM_EVENT)

+#else  /* EXTI */

+#define __HAL_RTC_ALARM_EXTI_GET_FLAG()              (EXTI->PR1    & RTC_EXTI_LINE_ALARM_EVENT)

+#endif /* EXTI_D1 */

+

+/**

+  * @brief Clear the RTC Alarm associated Exti line flag.

+  * @retval None.

+  */

+#if defined(EXTI_D1)

+#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()            (EXTI_D1->PR1 = (RTC_EXTI_LINE_ALARM_EVENT))

+#else  /* EXTI */

+#define __HAL_RTC_ALARM_EXTI_CLEAR_FLAG()            (EXTI->PR1    = (RTC_EXTI_LINE_ALARM_EVENT))

+#endif /* EXTI_D1 */

+

+#if defined(DUAL_CORE)

+/**

+  * @brief Check whether the RTC Alarm associated D2 Exti line interrupt flag is set or not.

+  * @retval Line Status

+  */

+#define __HAL_RTC_ALARM_EXTID2_GET_FLAG()            (EXTI_D2->PR1 & RTC_EXTI_LINE_ALARM_EVENT)

+

+/**

+  * @brief Clear the RTC Alarm associated D2 Exti line flag.

+  * @retval None

+  */

+#define __HAL_RTC_ALARM_EXTID2_CLEAR_FLAG()          (EXTI_D2->PR1 = (RTC_EXTI_LINE_ALARM_EVENT))

+#endif

+/**

+  * @brief Generate a Software interrupt on RTC Alarm associated Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_ALARM_EXTI_GENERATE_SWIT()         (EXTI->SWIER1 |= RTC_EXTI_LINE_ALARM_EVENT)

+

+/**

+  * @}

+  */

+

+/* Include RTC HAL Extended module */

+#include "stm32h7xx_hal_rtc_ex.h"

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup RTC_Exported_Functions RTC Exported Functions

+  * @{

+  */

+

+/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions

+  * @{

+  */

+/* Initialization and de-initialization functions  ****************************/

+HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);

+HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);

+

+void              HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);

+void              HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);

+

+/* Callbacks Register/UnRegister functions  ***********************************/

+#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1)

+HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID);

+#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS == 1) */

+/**

+  * @}

+  */

+

+/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions

+  * @{

+  */

+/* RTC Time and Date functions ************************************************/

+HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);

+HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);

+HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);

+HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);

+/**

+  * @}

+  */

+

+/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions

+  * @{

+  */

+/* RTC Alarm functions ********************************************************/

+HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);

+HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);

+HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);

+HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);

+void              HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);

+void              HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);

+HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);

+/**

+  * @}

+  */

+

+/** @defgroup  RTC_Exported_Functions_Group4 Peripheral Control functions

+  * @{

+  */

+/* Peripheral Control functions ***********************************************/

+HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc);

+/**

+  * @}

+  */

+

+/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions

+  * @{

+  */

+/* Peripheral State functions *************************************************/

+HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup RTC_Private_Constants RTC Private Constants

+  * @{

+  */

+/* Masks Definition */

+#define RTC_TR_RESERVED_MASK    (RTC_TR_PM  | RTC_TR_HT | RTC_TR_HU | \

+                                 RTC_TR_MNT | RTC_TR_MNU| RTC_TR_ST | \

+                                 RTC_TR_SU)

+

+#define RTC_DR_RESERVED_MASK    (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \

+                                 RTC_DR_MT | RTC_DR_MU | RTC_DR_DT  | \

+                                 RTC_DR_DU)

+

+#define RTC_INIT_MASK           0xFFFFFFFFu

+

+#if defined(RTC_ICSR_INIT) && defined(RTC_ICSR_RSF)

+#define RTC_RSF_MASK                        (~(RTC_ICSR_INIT | RTC_ICSR_RSF))

+#endif /* RTC_ICSR_INIT && RTC_ICSR_RSF */

+

+#if defined(RTC_ISR_INIT) && defined(RTC_ISR_RSF)

+#define RTC_RSF_MASK                        (~(RTC_ISR_INIT | RTC_ISR_RSF))

+#endif /* RTC_ISR_INIT && RTC_ISR_RSF */

+

+#define RTC_TIMEOUT_VALUE  1000u

+

+#define RTC_EXTI_LINE_ALARM_EVENT    EXTI_IMR1_IM17  /*!< External interrupt line 17 Connected to the RTC Alarm event */

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup RTC_Private_Macros RTC Private Macros

+  * @{

+  */

+

+/** @defgroup RTC_IS_RTC_Definitions RTC Private macros to check input parameters

+  * @{

+  */

+

+#if defined(RTC_CR_TAMPOE)

+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE)     || \

+                               ((OUTPUT) == RTC_OUTPUT_ALARMA)      || \

+                               ((OUTPUT) == RTC_OUTPUT_ALARMB)      || \

+                               ((OUTPUT) == RTC_OUTPUT_WAKEUP)      || \

+                               ((OUTPUT) == RTC_OUTPUT_TAMPER))

+#else  /* RTC_CR_TAMPOE not defined */

+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE)     || \

+                               ((OUTPUT) == RTC_OUTPUT_ALARMA)      || \

+                               ((OUTPUT) == RTC_OUTPUT_ALARMB)      || \

+                               ((OUTPUT) == RTC_OUTPUT_WAKEUP))

+#endif /* RTC_CR_TAMPOE */

+

+#define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HOURFORMAT_12) || \

+                                        ((FORMAT) == RTC_HOURFORMAT_24))

+

+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \

+                                ((POL) == RTC_OUTPUT_POLARITY_LOW))

+

+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \

+                                  ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))

+

+#if defined(RTC_CR_TAMPALRM_PU)

+#define IS_RTC_OUTPUT_PULLUP(TYPE) (((TYPE) == RTC_OUTPUT_PULLUP_NONE) || \

+                                    ((TYPE) == RTC_OUTPUT_PULLUP_ON))

+#endif /* RTC_CR_TAMPALRM_PU */

+

+#define IS_RTC_OUTPUT_REMAP(REMAP)     (((REMAP) == RTC_OUTPUT_REMAP_NONE) || \

+                                        ((REMAP) == RTC_OUTPUT_REMAP_POS1))

+

+#define IS_RTC_HOURFORMAT12(PM)  (((PM) == RTC_HOURFORMAT12_AM) || \

+                                  ((PM) == RTC_HOURFORMAT12_PM))

+

+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \

+                                      ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \

+                                      ((SAVE) == RTC_DAYLIGHTSAVING_NONE))

+

+#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \

+                                           ((OPERATION) == RTC_STOREOPERATION_SET))

+

+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_FORMAT_BIN) || \

+                               ((FORMAT) == RTC_FORMAT_BCD))

+

+#define IS_RTC_YEAR(YEAR)              ((YEAR)   <= 99u)

+

+#define IS_RTC_MONTH(MONTH)            (((MONTH) >= 1u) && ((MONTH) <= 12u))

+

+#define IS_RTC_DATE(DATE)              (((DATE)  >= 1u) && ((DATE)  <= 31u))

+

+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \

+                                 ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \

+                                 ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \

+                                 ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \

+                                 ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \

+                                 ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \

+                                 ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))

+

+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0u) && ((DATE) <= 31u))

+

+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \

+                                                    ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \

+                                                    ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \

+                                                    ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \

+                                                    ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \

+                                                    ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \

+                                                    ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))

+

+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \

+                                            ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))

+

+#define IS_RTC_ALARM_MASK(MASK)  (((MASK) & ~(RTC_ALARMMASK_ALL)) == 0u)

+

+#define IS_RTC_ALARM(ALARM)      (((ALARM) == RTC_ALARM_A) || \

+                                  ((ALARM) == RTC_ALARM_B))

+

+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS)

+

+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)          (((MASK) == 0u) || \

+                                                    (((MASK) >= RTC_ALARMSUBSECONDMASK_SS14_1) && ((MASK) <= RTC_ALARMSUBSECONDMASK_NONE)))

+

+#define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= (RTC_PRER_PREDIV_A >> RTC_PRER_PREDIV_A_Pos))

+

+#define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= (RTC_PRER_PREDIV_S >> RTC_PRER_PREDIV_S_Pos))

+

+#define IS_RTC_HOUR12(HOUR)            (((HOUR) >  0u) && ((HOUR) <= 12u))

+

+#define IS_RTC_HOUR24(HOUR)            ((HOUR)    <= 23u)

+

+#define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= 59u)

+

+#define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= 59u)

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private functions -------------------------------------------------------------*/

+/** @defgroup RTC_Private_Functions RTC Private Functions

+  * @{

+  */

+HAL_StatusTypeDef  RTC_EnterInitMode(RTC_HandleTypeDef *hrtc);

+uint8_t            RTC_ByteToBcd2(uint8_t Value);

+uint8_t            RTC_Bcd2ToByte(uint8_t Value);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_RTC_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_rtc_ex.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_rtc_ex.h
new file mode 100644
index 0000000000..a9159c55f1
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_rtc_ex.h
@@ -0,0 +1,2089 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_rtc_ex.h

+  * @author  MCD Application Team

+  * @brief   Header file of RTC HAL Extension module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_RTC_EX_H

+#define STM32H7xx_HAL_RTC_EX_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif /* __cplusplus */

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @defgroup RTCEx RTCEx

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+

+/** @defgroup RTCEx_Exported_Types RTCEx Exported Types

+  * @{

+  */

+

+/** @defgroup RTCEx_Tamper_structure_definition RTC Tamper structure definition

+  * @{

+  */

+typedef struct

+{

+  uint32_t Tamper;                      /*!< Specifies the Tamper Pin.

+                                             This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions */

+

+  uint32_t Interrupt;                   /*!< Specifies the Tamper Interrupt.

+                                             This parameter can be a value of @ref  RTCEx_Tamper_Interrupt_Definitions */

+

+  uint32_t Trigger;                     /*!< Specifies the Tamper Trigger.

+                                             This parameter can be a value of @ref RTCEx_Tamper_Trigger_Definitions */

+

+  uint32_t NoErase;                     /*!< Specifies the Tamper no erase mode.

+                                             This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp_Definitions */

+

+  uint32_t MaskFlag;                     /*!< Specifies the Tamper Flag masking.

+                                             This parameter can be a value of @ref RTCEx_Tamper_MaskFlag_Definitions   */

+

+  uint32_t Filter;                      /*!< Specifies the TAMP Filter Tamper.

+                                             This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */

+

+  uint32_t SamplingFrequency;           /*!< Specifies the sampling frequency.

+                                             This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */

+

+  uint32_t PrechargeDuration;           /*!< Specifies the Precharge Duration .

+                                             This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */

+

+  uint32_t TamperPullUp;                /*!< Specifies the Tamper PullUp .

+                                             This parameter can be a value of @ref RTCEx_Tamper_Pull_UP_Definitions */

+

+  uint32_t TimeStampOnTamperDetection;  /*!< Specifies the TimeStampOnTamperDetection.

+                                             This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */

+} RTC_TamperTypeDef;

+/**

+  * @}

+  */

+

+#if defined(TAMP_CR1_ITAMP1E)

+/** @defgroup RTCEx_Internal_Tamper_structure_definition RTCEx Internal Tamper structure definition

+  * @{

+  */

+typedef struct

+{

+  uint32_t IntTamper;                   /*!< Specifies the Internal Tamper Pin.

+                                             This parameter can be a value of @ref RTCEx_Internal_Tamper_Pins */

+

+  uint32_t TimeStampOnTamperDetection;  /*!< Specifies the TimeStampOnTamperDetection.

+                                             This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection */

+} RTC_InternalTamperTypeDef;

+/**

+  * @}

+  */

+#endif /* TAMP_CR1_ITAMP1E */

+

+#if defined(TAMP_ATCR1_TAMP1AM)

+/** @defgroup RTCEx_Active_Seed_Size Seed size Definitions

+  * @{

+  */

+#define RTC_ATAMP_SEED_NB_UINT32        4U

+/**

+  * @}

+  */

+

+/** @defgroup RTCEx_Active_Tampers_Number Active Tampers number Definitions

+  * @{

+  */

+#define RTC_TAMP_NB                     3u

+/**

+  * @}

+  */

+

+/** @defgroup RTCEx_ActiveTamper_structures_definition RTC Active Tamper structures definitions

+  * @{

+  */

+typedef struct

+{

+  uint32_t Enable;                      /*!< Specifies the Tamper input is active.

+                                             This parameter can be a value of @ref RTCEx_ActiveTamper_Enable */

+

+  uint32_t Interrupt;                    /*!< Specifies the interrupt mode

+                                             This parameter can be a value of @ref RTCEx_ActiveTamper_Interrupt */

+

+  uint32_t Output;                      /*!< Specifies the TAMP output to be compared with.

+                                             The same output can be used for several tamper inputs.

+                                             This parameter can be a value of @ref RTCEx_ActiveTamper_Sel */

+

+  uint32_t NoErase;                     /*!< Specifies the Tamper no erase mode.

+                                             This parameter can be a value of @ref RTCEx_Tamper_EraseBackUp */

+

+  uint32_t MaskFlag;                    /*!< Specifies the Tamper Flag masking.

+                                             This parameter can be a value of @ref RTCEx_Tamper_MaskFlag */

+

+} RTC_ATampInputTypeDef;

+

+

+typedef struct

+{

+  uint32_t ActiveFilter;                /*!< Specifies the Active tamper filter enable.

+                                             This parameter can be a value of @ref RTCEx_ActiveTamper_Filter */

+

+  uint32_t ActiveAsyncPrescaler;        /*!< Specifies the Active Tamper asynchronous Prescaler clock.

+                                             This parameter can be a value of @ref RTCEx_ActiveTamper_Async_prescaler */

+

+  uint32_t TimeStampOnTamperDetection;  /*!< Specifies the timeStamp on tamper detection.

+                                             This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection */

+

+  uint32_t ActiveOutputChangePeriod;    /*!< Specifies the Active Tamper output change period .

+                                             This parameter can be a value from 0 to 7. */

+

+  uint32_t Seed[RTC_ATAMP_SEED_NB_UINT32];

+  /*!< Specifies the Active Tamper RNG Seed value .

+       This parameter can be a value from 0 to (2^32-1) */

+

+  RTC_ATampInputTypeDef TampInput[RTC_TAMP_NB];

+  /*!< Specifies configuration of all active tampers.

+       The index of TampInput[RTC_TAMP_NB] can be a value of RTCEx_ActiveTamper_Sel */

+} RTC_ActiveTampersTypeDef;

+

+/**

+  * @}

+  */

+#endif /* TAMP_ATCR1_TAMP1AM */

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+

+/** @defgroup RTCEx_Exported_Constants RTC Exported Constants

+  * @{

+  */

+

+/* ========================================================================== */

+/*         ##### Extended RTC Backup registers exported constants #####       */

+/* ========================================================================== */

+

+/** @defgroup RTCEx_Backup_Registers_Number_Definitions RTC Backup Registers Number Definitions

+  * @{

+  */

+#if defined(RTC_BKP_NUMBER)

+#define BKP_REG_NUMBER                       RTC_BKP_NUMBER

+#endif /* RTC_BKP_NUMBER */

+#if defined(TAMP_BKP_NUMBER)

+#define BKP_REG_NUMBER                       TAMP_BKP_NUMBER

+#endif /* TAMP_BKP_NUMBER */

+/**

+  * @}

+  */

+

+/** @defgroup RTCEx_Backup_Registers_Definitions RTC Backup Registers Definitions

+  * @{

+  */

+#define RTC_BKP_DR0                       0x00u

+#define RTC_BKP_DR1                       0x01u

+#define RTC_BKP_DR2                       0x02u

+#define RTC_BKP_DR3                       0x03u

+#define RTC_BKP_DR4                       0x04u

+#define RTC_BKP_DR5                       0x05u

+#define RTC_BKP_DR6                       0x06u

+#define RTC_BKP_DR7                       0x07u

+#define RTC_BKP_DR8                       0x08u

+#define RTC_BKP_DR9                       0x09u

+#define RTC_BKP_DR10                      0x0Au

+#define RTC_BKP_DR11                      0x0Bu

+#define RTC_BKP_DR12                      0x0Cu

+#define RTC_BKP_DR13                      0x0Du

+#define RTC_BKP_DR14                      0x0Eu

+#define RTC_BKP_DR15                      0x0Fu

+#define RTC_BKP_DR16                      0x10u

+#define RTC_BKP_DR17                      0x11u

+#define RTC_BKP_DR18                      0x12u

+#define RTC_BKP_DR19                      0x13u

+#define RTC_BKP_DR20                      0x14u

+#define RTC_BKP_DR21                      0x15u

+#define RTC_BKP_DR22                      0x16u

+#define RTC_BKP_DR23                      0x17u

+#define RTC_BKP_DR24                      0x18u

+#define RTC_BKP_DR25                      0x19u

+#define RTC_BKP_DR26                      0x1Au

+#define RTC_BKP_DR27                      0x1Bu

+#define RTC_BKP_DR28                      0x1Cu

+#define RTC_BKP_DR29                      0x1Du

+#define RTC_BKP_DR30                      0x1Eu

+#define RTC_BKP_DR31                      0x1Fu

+/**

+  * @}

+  */

+

+/* ========================================================================== */

+/*                 ##### RTC TimeStamp exported constants #####               */

+/* ========================================================================== */

+

+/** @defgroup RTCEx_TimeStamp_Edges_definitions RTC TimeStamp Edges Definitions

+  *

+  * @{

+  */

+#define RTC_TIMESTAMPEDGE_RISING            0x00000000u

+#define RTC_TIMESTAMPEDGE_FALLING           RTC_CR_TSEDGE

+/**

+  * @}

+  */

+

+/** @defgroup RTCEx_TimeStamp_Pin_Selection RTC TimeStamp Pin Selection

+  * @{

+  */

+#define RTC_TIMESTAMPPIN_DEFAULT              0x00000000u

+/**

+  * @}

+  */

+

+

+/* ========================================================================== */

+/*                    ##### RTC Tamper exported constants #####               */

+/* ========================================================================== */

+

+/** @defgroup RTCEx_Tamper_Pins_Definitions RTC Tamper Pins Definitions

+  * @{

+  */

+#if defined(TAMP_CR1_TAMP1E)

+#define RTC_TAMPER_1                        TAMP_CR1_TAMP1E

+#endif /* TAMP_CR1_TAMP1E */

+#if defined(TAMP_CR1_TAMP2E)

+#define RTC_TAMPER_2                        TAMP_CR1_TAMP2E

+#endif /* TAMP_CR1_TAMP2E */

+#if defined(TAMP_CR1_TAMP3E)

+#define RTC_TAMPER_3                        TAMP_CR1_TAMP3E

+#endif /* TAMP_CR1_TAMP3E */

+

+#if defined(RTC_TAMPCR_TAMP1E)

+#define RTC_TAMPER_1                       RTC_TAMPCR_TAMP1E

+#endif /* RTC_TAMPCR_TAMP1E */

+#if defined(RTC_TAMPCR_TAMP2E)

+#define RTC_TAMPER_2                       RTC_TAMPCR_TAMP2E

+#endif /* RTC_TAMPCR_TAMP2E */

+#if defined(RTC_TAMPCR_TAMP3E)

+#define RTC_TAMPER_3                       RTC_TAMPCR_TAMP3E

+#endif /* RTC_TAMPCR_TAMP3E */

+

+#define RTC_TAMPER_ALL                     (RTC_TAMPER_1 | RTC_TAMPER_2 | RTC_TAMPER_3)

+/**

+  * @}

+  */

+

+/** @defgroup RTCEx_Tamper_Interrupt_Definitions RTC Tamper Interrupts Definitions

+  * @{

+  */

+#if defined(TAMP_IER_TAMP1IE)

+#define RTC_IT_TAMP1                      TAMP_IER_TAMP1IE    /*!< Enable Tamper 1 Interrupt                */

+#endif /* TAMP_IER_TAMP1IE */

+#if defined(TAMP_IER_TAMP2IE)

+#define RTC_IT_TAMP2                      TAMP_IER_TAMP2IE    /*!< Enable Tamper 2 Interrupt                */

+#endif /* TAMP_IER_TAMP2IE */

+#if defined(TAMP_IER_TAMP3IE)

+#define RTC_IT_TAMP3                      TAMP_IER_TAMP3IE    /*!< Enable Tamper 3 Interrupt                */

+#endif /* TAMP_IER_TAMP3IE */

+

+#if defined(RTC_TAMPCR_TAMP1IE)

+#define RTC_IT_TAMP1                      RTC_TAMPCR_TAMP1IE  /*!< Enable Tamper 1 Interrupt                */

+#endif /* RTC_TAMPCR_TAMP1IE */

+#if defined(RTC_TAMPCR_TAMP2IE)

+#define RTC_IT_TAMP2                      RTC_TAMPCR_TAMP2IE  /*!< Enable Tamper 2 Interrupt                */

+#endif /* RTC_TAMPCR_TAMP2IE */

+#if defined(RTC_TAMPCR_TAMP3IE)

+#define RTC_IT_TAMP3                      RTC_TAMPCR_TAMP3IE  /*!< Enable Tamper 3 Interrupt                */

+#endif /* RTC_TAMPCR_TAMP3IE */

+

+#if defined(RTC_TAMPCR_TAMPIE)

+#define RTC_IT_TAMP                       RTC_TAMPCR_TAMPIE   /*!< Enable all Tamper Interrupts              */

+#define RTC_IT_TAMPALL                    RTC_IT_TAMP

+#else /* RTC_TAMPCR_TAMPIE not defined */

+#define RTC_IT_TAMP                       0x00000000u         /*!< No such feature in RTC3                   */

+#define RTC_IT_TAMPALL                    (RTC_IT_TAMP1 | RTC_IT_TAMP2 | RTC_IT_TAMP3)

+#endif /* RTC_TAMPCR_TAMPIE */

+/**

+  * @}

+  */

+

+/** @defgroup RTCEx_Internal_Tamper_Pins_Definitions  RTCEx Internal Tamper Pins Definition

+  * @{

+  */

+#if defined(TAMP_CR1_ITAMP1E)

+#define RTC_INT_TAMPER_1                    TAMP_CR1_ITAMP1E

+#endif /* TAMP_CR1_ITAMP1E */

+#if defined(TAMP_CR1_ITAMP2E)

+#define RTC_INT_TAMPER_2                    TAMP_CR1_ITAMP2E

+#endif /* TAMP_CR1_ITAMP2E */

+#if defined(TAMP_CR1_ITAMP3E)

+#define RTC_INT_TAMPER_3                    TAMP_CR1_ITAMP3E

+#endif /* TAMP_CR1_ITAMP3E */

+#if defined(TAMP_CR1_ITAMP4E)

+#define RTC_INT_TAMPER_4                    TAMP_CR1_ITAMP4E

+#endif /* TAMP_CR1_ITAMP4E */

+#if defined(TAMP_CR1_ITAMP5E)

+#define RTC_INT_TAMPER_5                    TAMP_CR1_ITAMP5E

+#endif /* TAMP_CR1_ITAMP5E */

+#if defined(TAMP_CR1_ITAMP6E)

+#define RTC_INT_TAMPER_6                    TAMP_CR1_ITAMP6E

+#endif /* TAMP_CR1_ITAMP6E */

+#if defined(TAMP_CR1_ITAMP8E)

+#define RTC_INT_TAMPER_8                    TAMP_CR1_ITAMP8E

+#define RTC_INT_TAMPER_ALL                  (RTC_INT_TAMPER_1 | RTC_INT_TAMPER_2 |\

+                                             RTC_INT_TAMPER_3 | RTC_INT_TAMPER_4 |\

+                                             RTC_INT_TAMPER_5 | RTC_INT_TAMPER_6 |\

+                                             RTC_INT_TAMPER_8)

+#endif /* TAMP_CR1_ITAMP8E */

+/**

+  * @}

+  */

+

+/** @defgroup RTCEx_Internal_Tamper_Interrupt_Definitions  RTC Internal Tamper Interrupt

+  * @{

+  */

+#if defined(TAMP_IER_ITAMP1IE)

+#define RTC_INTERNAL_TAMPER1_INTERRUPT     TAMP_IER_ITAMP1IE  /*!< Enable Internal Tamper 1 Interrupt   */

+#endif /* TAMP_IER_ITAMP1IE */

+#if defined(TAMP_IER_ITAMP2IE)

+#define RTC_INTERNAL_TAMPER2_INTERRUPT     TAMP_IER_ITAMP2IE  /*!< Enable Internal Tamper 2 Interrupt   */

+#endif /* TAMP_IER_ITAMP2IE */

+#if defined(TAMP_IER_ITAMP3IE)

+#define RTC_INTERNAL_TAMPER3_INTERRUPT     TAMP_IER_ITAMP3IE  /*!< Enable Internal Tamper 3 Interrupt   */

+#endif /* TAMP_IER_ITAMP3IE */

+#if defined(TAMP_IER_ITAMP4IE)

+#define RTC_INTERNAL_TAMPER4_INTERRUPT     TAMP_IER_ITAMP4IE  /*!< Enable Internal Tamper 4 Interrupt   */

+#endif /* TAMP_IER_ITAMP4IE */

+#if defined(TAMP_IER_ITAMP5IE)

+#define RTC_INTERNAL_TAMPER5_INTERRUPT     TAMP_IER_ITAMP5IE  /*!< Enable Internal Tamper 5 Interrupt   */

+#endif /* TAMP_IER_ITAMP5IE */

+#if defined(TAMP_IER_ITAMP6IE)

+#define RTC_INTERNAL_TAMPER6_INTERRUPT     TAMP_IER_ITAMP6IE  /*!< Enable Internal Tamper 6 Interrupt   */

+#endif /* TAMP_IER_ITAMP6IE */

+#if defined(TAMP_IER_ITAMP8IE)

+#define RTC_INTERNAL_TAMPER8_INTERRUPT     TAMP_IER_ITAMP8IE  /*!< Enable Internal Tamper 8 Interrupt   */

+#endif /* TAMP_IER_ITAMP8IE */

+/**

+  * @}

+  */

+

+/** @defgroup RTCEx_Tamper_Trigger_Definitions RTC Tamper Triggers Definitions

+  * @{

+  */

+#define RTC_TAMPERTRIGGER_RISINGEDGE        0x01u  /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */

+#define RTC_TAMPERTRIGGER_FALLINGEDGE       0x02u  /*!< Warning : Filter must be RTC_TAMPERFILTER_DISABLE */

+#define RTC_TAMPERTRIGGER_LOWLEVEL          0x04u  /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */

+#define RTC_TAMPERTRIGGER_HIGHLEVEL         0x08u  /*!< Warning : Filter must not be RTC_TAMPERFILTER_DISABLE */

+

+#if defined(TAMP_CR2_TAMP1TRG)

+#define RTC_TAMPER_1_TRIGGER                TAMP_CR2_TAMP1TRG

+#endif /* TAMP_CR2_TAMP1TRG */

+#if defined(TAMP_CR2_TAMP2TRG)

+#define RTC_TAMPER_2_TRIGGER                TAMP_CR2_TAMP2TRG

+#endif /* TAMP_CR2_TAMP2TRG */

+#if defined(TAMP_CR2_TAMP3TRG)

+#define RTC_TAMPER_3_TRIGGER                TAMP_CR2_TAMP3TRG

+#endif /* TAMP_CR2_TAMP3TRG */

+

+#if defined(RTC_TAMPCR_TAMP1TRG)

+#define RTC_TAMPER_1_TRIGGER                RTC_TAMPCR_TAMP1TRG

+#endif /* RTC_TAMPCR_TAMP1TRG */

+#if defined(RTC_TAMPCR_TAMP2TRG)

+#define RTC_TAMPER_2_TRIGGER                RTC_TAMPCR_TAMP2TRG

+#endif /* RTC_TAMPCR_TAMP2TRG */

+#if defined(RTC_TAMPCR_TAMP3TRG)

+#define RTC_TAMPER_3_TRIGGER                RTC_TAMPCR_TAMP3TRG

+#endif /* RTC_TAMPCR_TAMP3TRG */

+

+#define RTC_TAMPER_X_TRIGGER                (RTC_TAMPER_1_TRIGGER |\

+                                             RTC_TAMPER_2_TRIGGER |\

+                                             RTC_TAMPER_3_TRIGGER)

+/**

+  * @}

+  */

+

+/** @defgroup RTCEx_Tamper_EraseBackUp_Definitions RTC Tamper EraseBackUp Definitions

+* @{

+*/

+#if defined(TAMP_CR2_TAMP1NOERASE)

+#define RTC_TAMPER_ERASE_BACKUP_ENABLE      0x00u

+#define RTC_TAMPER_ERASE_BACKUP_DISABLE     0x01u

+#endif /* TAMP_CR2_TAMP1NOERASE */

+#if defined(RTC_TAMPCR_TAMP1NOERASE)

+#define RTC_TAMPER_ERASE_BACKUP_ENABLE     0x00000000u

+#define RTC_TAMPER_ERASE_BACKUP_DISABLE    RTC_TAMPCR_TAMP1NOERASE

+#endif /* RTC_TAMPCR_TAMP1NOERASE */

+

+#if defined(TAMP_CR2_TAMP1NOERASE)

+#define RTC_DISABLE_BKP_ERASE_ON_TAMPER_1  TAMP_CR2_TAMP1NOERASE

+#endif /* TAMP_CR2_TAMP1NOERASE */

+#if defined(TAMP_CR2_TAMP2NOERASE)

+#define RTC_DISABLE_BKP_ERASE_ON_TAMPER_2  TAMP_CR2_TAMP2NOERASE

+#endif /* TAMP_CR2_TAMP2NOERASE */

+#if defined(TAMP_CR2_TAMP3NOERASE)

+#define RTC_DISABLE_BKP_ERASE_ON_TAMPER_3  TAMP_CR2_TAMP3NOERASE

+#endif /* TAMP_CR2_TAMP3NOERASE */

+

+#if defined(RTC_TAMPCR_TAMP1NOERASE)

+#define RTC_DISABLE_BKP_ERASE_ON_TAMPER_1  RTC_TAMPCR_TAMP1NOERASE

+#endif /* RTC_TAMPCR_TAMP1NOERASE */

+#if defined(RTC_TAMPCR_TAMP2NOERASE)

+#define RTC_DISABLE_BKP_ERASE_ON_TAMPER_2  RTC_TAMPCR_TAMP2NOERASE

+#endif /* RTC_TAMPCR_TAMP2NOERASE */

+#if defined(RTC_TAMPCR_TAMP3NOERASE)

+#define RTC_DISABLE_BKP_ERASE_ON_TAMPER_3  RTC_TAMPCR_TAMP3NOERASE

+#endif /* RTC_TAMPCR_TAMP3NOERASE */

+

+#define RTC_DISABLE_BKP_ERASE_ON_TAMPER_MASK (RTC_DISABLE_BKP_ERASE_ON_TAMPER_1 |\

+                                              RTC_DISABLE_BKP_ERASE_ON_TAMPER_2 |\

+                                              RTC_DISABLE_BKP_ERASE_ON_TAMPER_3)

+/**

+  * @}

+  */

+

+/** @defgroup RTCEx_Tamper_MaskFlag_Definitions RTC Tamper Mask Flag Definitions

+* @{

+*/

+#if defined(TAMP_CR2_TAMP1MSK)

+#define RTC_TAMPERMASK_FLAG_DISABLE         0x00u

+#define RTC_TAMPERMASK_FLAG_ENABLE          0x01u

+#endif /* TAMP_CR2_TAMP1MSK */

+#if defined(RTC_TAMPCR_TAMP1MF)

+#define RTC_TAMPERMASK_FLAG_DISABLE        0x00000000u

+#define RTC_TAMPERMASK_FLAG_ENABLE         RTC_TAMPCR_TAMP1MF

+#endif /* RTC_TAMPCR_TAMP1MF */

+

+#if defined(TAMP_CR2_TAMP1MSK)

+#define RTC_TAMPER_1_MASK_FLAG             TAMP_CR2_TAMP1MSK

+#endif /* TAMP_CR2_TAMP1MSK */

+#if defined(TAMP_CR2_TAMP2MSK)

+#define RTC_TAMPER_2_MASK_FLAG             TAMP_CR2_TAMP2MSK

+#endif /* TAMP_CR2_TAMP2MSK */

+#if defined(TAMP_CR2_TAMP3MSK)

+#define RTC_TAMPER_3_MASK_FLAG             TAMP_CR2_TAMP3MSK

+#endif /* TAMP_CR2_TAMP3MSK */

+

+#if defined(RTC_TAMPCR_TAMP1MF)

+#define RTC_TAMPER_1_MASK_FLAG             RTC_TAMPCR_TAMP1MF

+#endif /* RTC_TAMPCR_TAMP1MF */

+#if defined(RTC_TAMPCR_TAMP2MF)

+#define RTC_TAMPER_2_MASK_FLAG             RTC_TAMPCR_TAMP2MF

+#endif /* RTC_TAMPCR_TAMP2MF */

+#if defined(RTC_TAMPCR_TAMP3MF)

+#define RTC_TAMPER_3_MASK_FLAG             RTC_TAMPCR_TAMP3MF

+#endif /* RTC_TAMPCR_TAMP3MF */

+

+#define RTC_TAMPER_X_MASK_FLAG             (RTC_TAMPER_1_MASK_FLAG |\

+                                            RTC_TAMPER_2_MASK_FLAG |\

+                                            RTC_TAMPER_3_MASK_FLAG)

+/**

+  * @}

+  */

+

+/** @defgroup RTCEx_Tamper_Filter_Definitions RTC Tamper Filter Definitions

+  * @{

+  */

+#if defined(TAMP_FLTCR_TAMPFLT)

+#define RTC_TAMPERFILTER_DISABLE   0x00000000U             /*!< Tamper filter is disabled */

+

+#define RTC_TAMPERFILTER_2SAMPLE   TAMP_FLTCR_TAMPFLT_0    /*!< Tamper is activated after 2

+                                                                 consecutive samples at the active level */

+#define RTC_TAMPERFILTER_4SAMPLE   TAMP_FLTCR_TAMPFLT_1    /*!< Tamper is activated after 4

+                                                                 consecutive samples at the active level */

+#define RTC_TAMPERFILTER_8SAMPLE   TAMP_FLTCR_TAMPFLT      /*!< Tamper is activated after 8

+                                                                 consecutive samples at the active level */

+#define RTC_TAMPERFILTER_MASK      TAMP_FLTCR_TAMPFLT      /*!< Masking all bits except those of

+                                                                 field TAMPFLT[1:0]. */

+#endif /* TAMP_FLTCR_TAMPFLT */

+#if defined(RTC_TAMPCR_TAMPFLT)

+#define RTC_TAMPERFILTER_DISABLE   0x00000000u             /*!< Tamper filter is disabled */

+

+#define RTC_TAMPERFILTER_2SAMPLE   RTC_TAMPCR_TAMPFLT_0    /*!< Tamper is activated after 2

+                                                                 consecutive samples at the active level */

+#define RTC_TAMPERFILTER_4SAMPLE   RTC_TAMPCR_TAMPFLT_1    /*!< Tamper is activated after 4

+                                                                 consecutive samples at the active level */

+#define RTC_TAMPERFILTER_8SAMPLE   RTC_TAMPCR_TAMPFLT      /*!< Tamper is activated after 8

+                                                                 consecutive samples at the active level. */

+#define RTC_TAMPERFILTER_MASK      RTC_TAMPCR_TAMPFLT      /*!< Masking all bits except those of

+                                                                 field TAMPFLT[1:0]. */

+#endif /* RTC_TAMPCR_TAMPFLT */

+/**

+  * @}

+  */

+

+/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions RTC Tamper Sampling Frequencies Definitions

+  * @{

+  */

+#if defined(TAMP_FLTCR_TAMPFREQ)

+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768  0x00000000U                                     /*!< Each of the tamper inputs are sampled

+                                                                                                      with a frequency =  RTCCLK / 32768 */

+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384  TAMP_FLTCR_TAMPFREQ_0                           /*!< Each of the tamper inputs are sampled

+                                                                                                      with a frequency =  RTCCLK / 16384 */

+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192   TAMP_FLTCR_TAMPFREQ_1                           /*!< Each of the tamper inputs are sampled

+                                                                                                      with a frequency =  RTCCLK / 8192  */

+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096   (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled

+                                                                                                      with a frequency =  RTCCLK / 4096  */

+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048   TAMP_FLTCR_TAMPFREQ_2                           /*!< Each of the tamper inputs are sampled

+                                                                                                      with a frequency =  RTCCLK / 2048  */

+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024   (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled

+                                                                                                      with a frequency =  RTCCLK / 1024  */

+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512    (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled

+                                                                                                      with a frequency =  RTCCLK / 512   */

+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256    TAMP_FLTCR_TAMPFREQ                             /*!< Each of the tamper inputs are sampled

+                                                                                                      with a frequency =  RTCCLK / 256   */

+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK      TAMP_FLTCR_TAMPFREQ                             /*!< Masking all bits except those of

+                                                                                                      field TAMPFREQ[2:0]*/

+#endif /* TAMP_FLTCR_TAMPFREQ */

+#if defined(RTC_TAMPCR_TAMPFREQ)

+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768  0x00000000u                                     /*!< Each of the tamper inputs are sampled

+                                                                                                      with a frequency =  RTCCLK / 32768 */

+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384  RTC_TAMPCR_TAMPFREQ_0                           /*!< Each of the tamper inputs are sampled

+                                                                                                      with a frequency =  RTCCLK / 16384 */

+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192   RTC_TAMPCR_TAMPFREQ_1                           /*!< Each of the tamper inputs are sampled

+                                                                                                      with a frequency =  RTCCLK / 8192  */

+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096   (RTC_TAMPCR_TAMPFREQ_0 | RTC_TAMPCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled

+                                                                                                      with a frequency =  RTCCLK / 4096  */

+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048   RTC_TAMPCR_TAMPFREQ_2                           /*!< Each of the tamper inputs are sampled

+                                                                                                      with a frequency =  RTCCLK / 2048  */

+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024   (RTC_TAMPCR_TAMPFREQ_0 | RTC_TAMPCR_TAMPFREQ_2)  /*!< Each of the tamper inputs are sampled

+                                                                                                      with a frequency =  RTCCLK / 1024  */

+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512    (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_2)  /*!< Each of the tamper inputs are sampled

+                                                                                                      with a frequency =  RTCCLK / 512   */

+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256    RTC_TAMPCR_TAMPFREQ                              /*!< Each of the tamper inputs are sampled

+                                                                                                      with a frequency =  RTCCLK / 256   */

+#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK      RTC_TAMPCR_TAMPFREQ                             /*!< Masking all bits except those of

+                                                                                                      field TAMPFREQ[2:0]*/

+#endif /* RTC_TAMPCR_TAMPFREQ */

+/**

+  * @}

+  */

+

+/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions RTC Tamper Pin Precharge Duration Definitions

+  * @{

+  */

+#if defined(TAMP_FLTCR_TAMPPRCH)

+#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK     0x00000000U             /*!< Tamper pins are pre-charged before

+                                                                              sampling during 1 RTCCLK cycle  */

+#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK     TAMP_FLTCR_TAMPPRCH_0   /*!< Tamper pins are pre-charged before

+                                                                              sampling during 2 RTCCLK cycles */

+#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK     TAMP_FLTCR_TAMPPRCH_1   /*!< Tamper pins are pre-charged before

+                                                                              sampling during 4 RTCCLK cycles */

+#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK     TAMP_FLTCR_TAMPPRCH     /*!< Tamper pins are pre-charged before

+                                                                              sampling during 8 RTCCLK cycles */

+#define RTC_TAMPERPRECHARGEDURATION_MASK        TAMP_FLTCR_TAMPPRCH     /*!< Masking all bits except those of

+                                                                              field TAMPPRCH[1:0] */

+#endif /* TAMP_FLTCR_TAMPPRCH */

+#if defined(RTC_TAMPCR_TAMPPRCH)

+#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK     0x00000000u             /*!< Tamper pins are pre-charged before

+                                                                              sampling during 1 RTCCLK cycle  */

+#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK     RTC_TAMPCR_TAMPPRCH_0   /*!< Tamper pins are pre-charged before

+                                                                              sampling during 2 RTCCLK cycles */

+#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK     RTC_TAMPCR_TAMPPRCH_1   /*!< Tamper pins are pre-charged before

+                                                                              sampling during 4 RTCCLK cycles */

+#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK     RTC_TAMPCR_TAMPPRCH     /*!< Tamper pins are pre-charged before

+                                                                              sampling during 8 RTCCLK cycles */

+#define RTC_TAMPERPRECHARGEDURATION_MASK        RTC_TAMPCR_TAMPPRCH     /*!< Masking all bits except those of

+                                                                              field TAMPPRCH[1:0] */

+#endif /* RTC_TAMPCR_TAMPPRCH */

+/**

+  * @}

+  */

+

+/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions RTC Tamper TimeStamp On Tamper Detection Definitions

+  * @{

+  */

+#if defined(RTC_CR_TAMPTS)

+#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE  0x00000000u                   /*!< TimeStamp on Tamper Detection event is not saved */

+#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE   RTC_CR_TAMPTS                 /*!< TimeStamp on Tamper Detection event saved        */

+#define RTC_TIMESTAMPONTAMPERDETECTION_MASK     RTC_CR_TAMPTS                 /*!< Masking all bits except bit TAMPTS               */

+#endif  /* RTC_CR_TAMPTS */

+#if defined(RTC_TAMPCR_TAMPTS)

+#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE  0x00000000u                   /*!< TimeStamp on Tamper Detection event is not saved */

+#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE   RTC_TAMPCR_TAMPTS             /*!< TimeStamp on Tamper Detection event saved        */

+#define RTC_TIMESTAMPONTAMPERDETECTION_MASK     RTC_TAMPCR_TAMPTS             /*!< Masking all bits except bit TAMPTS               */

+#endif /* RTC_TAMPCR_TAMPTS */

+/**

+  * @}

+  */

+

+/** @defgroup RTCEx_Tamper_Pull_UP_Definitions RTC Tamper Pull Up Definitions

+  * @{

+  */

+#if defined(TAMP_FLTCR_TAMPPUDIS)

+#define RTC_TAMPER_PULLUP_ENABLE           0x00000000u              /*!< Tamper pins are pre-charged before sampling */

+#define RTC_TAMPER_PULLUP_DISABLE          TAMP_FLTCR_TAMPPUDIS     /*!< Tamper pins pre-charge is disabled          */

+#define RTC_TAMPER_PULLUP_MASK             TAMP_FLTCR_TAMPPUDIS     /*!< Maskin all bits except bit TAMPPUDIS        */

+#endif /* TAMP_FLTCR_TAMPPUDIS */

+#if defined(RTC_TAMPCR_TAMPPUDIS)

+#define RTC_TAMPER_PULLUP_ENABLE           0x00000000u              /*!< TimeStamp on Tamper Detection event saved        */

+#define RTC_TAMPER_PULLUP_DISABLE          RTC_TAMPCR_TAMPPUDIS     /*!< TimeStamp on Tamper Detection event is not saved */

+#define RTC_TAMPER_PULLUP_MASK             RTC_TAMPCR_TAMPPUDIS     /*!< Maskin all bits except bit TAMPPUDIS        */

+#endif /* RTC_TAMPCR_TAMPPUDIS */

+/**

+  * @}

+  */

+

+/** @defgroup RTCEx_Tamper_DetectionOutput_Definitions RTC Tamper Detection Ouput Definitions

+  * @{

+  */

+#if defined(RTC_CR_TAMPOE)

+#define RTC_TAMPERDETECTIONOUTPUT_DISABLE  0x00000000u                   /*!< The tamper flag is not routed on TAMPALRM */

+#define RTC_TAMPERDETECTIONOUTPUT_ENABLE   RTC_CR_TAMPOE                 /*!< The tamper flag is routed on TAMPALRM combined with the signal

+                                                                               provided by OSEL and with the polarity provided by POL */

+#endif  /* RTC_CR_TAMPOE */

+/**

+  * @}

+  */

+

+/** @defgroup RTC_Tamper_Flags_Definitions RTC Tamper Flags Definitions

+  * @{

+  */

+#if defined(TAMP_SR_TAMP1F)

+#define RTC_FLAG_TAMP1F                   TAMP_SR_TAMP1F

+#endif /* TAMP_SR_TAMP1F */

+#if defined(TAMP_SR_TAMP2F)

+#define RTC_FLAG_TAMP2F                   TAMP_SR_TAMP2F

+#endif /* TAMP_SR_TAMP2F */

+#if defined(TAMP_SR_TAMP3F)

+#define RTC_FLAG_TAMP3F                   TAMP_SR_TAMP3F

+#endif /* TAMP_SR_TAMP3F */

+

+#if defined(RTC_ISR_TAMP1F)

+#define RTC_FLAG_TAMP1F                   RTC_ISR_TAMP1F

+#endif /* RTC_ISR_TAMP1F */

+#if defined(RTC_ISR_TAMP2F)

+#define RTC_FLAG_TAMP2F                   RTC_ISR_TAMP2F

+#endif /* RTC_ISR_TAMP2F */

+#if defined(RTC_ISR_TAMP3F)

+#define RTC_FLAG_TAMP3F                   RTC_ISR_TAMP3F

+#endif /* RTC_ISR_TAMP3F */

+/**

+  * @}

+  */

+

+/** @defgroup RTCEx_ActiveTamper_Enable RTCEx_ActiveTamper_Enable Definitions

+  * @{

+  */

+#define RTC_ATAMP_ENABLE                   1u

+#define RTC_ATAMP_DISABLE                  0u

+/**

+  * @}

+  */

+

+/** @defgroup RTCEx_ActiveTamper_Interrupt RTCEx_ActiveTamper_Interrupt Definitions

+  * @{

+  */

+#define RTC_ATAMP_INTERRUPT_ENABLE        1u

+#define RTC_ATAMP_INTERRUPT_DISABLE       0u

+/**

+  * @}

+  */

+

+/** @defgroup RTCEx_ActiveTamper_Filter RTCEx_ActiveTamper_Filter Definitions

+  * @{

+  */

+#define RTC_ATAMP_FILTER_ENABLE           TAMP_ATCR1_FLTEN

+#define RTC_ATAMP_FILTER_DISABLE          0u

+/**

+  * @}

+  */

+

+/** @defgroup RTCEx_ActiveTamper_Async_prescaler RTC Active_Tamper_Asynchronous_Prescaler clock Definitions

+  * @{

+  */

+#define RTC_ATAMP_ASYNCPRES_RTCCLK        0u                                                                      /*!< RTCCLK */

+#define RTC_ATAMP_ASYNCPRES_RTCCLK_2      TAMP_ATCR1_ATCKSEL_0                                                    /*!< RTCCLK/2 */

+#define RTC_ATAMP_ASYNCPRES_RTCCLK_4      TAMP_ATCR1_ATCKSEL_1                                                    /*!< RTCCLK/4 */

+#define RTC_ATAMP_ASYNCPRES_RTCCLK_8     (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)                            /*!< RTCCLK/8 */

+#define RTC_ATAMP_ASYNCPRES_RTCCLK_16     TAMP_ATCR1_ATCKSEL_2                                                    /*!< RTCCLK/16 */

+#define RTC_ATAMP_ASYNCPRES_RTCCLK_32    (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0)                            /*!< RTCCLK/32 */

+#define RTC_ATAMP_ASYNCPRES_RTCCLK_64    (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1)                            /*!< RTCCLK/64 */

+#define RTC_ATAMP_ASYNCPRES_RTCCLK_128   (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)     /*!< RTCCLK/128 */

+/**

+  * @}

+  */

+

+/** @defgroup RTCEx_ActiveTamper_Sel  RTC Active Tamper selection Definition

+  * @{

+  */

+#define RTC_ATAMP_1                       0u   /*!< Tamper 1 */

+#define RTC_ATAMP_2                       1u   /*!< Tamper 2 */

+#define RTC_ATAMP_3                       2u   /*!< Tamper 3 */

+#define RTC_ATAMP_4                       3u   /*!< Tamper 4 */

+#define RTC_ATAMP_5                       4u   /*!< Tamper 5 */

+#define RTC_ATAMP_6                       5u   /*!< Tamper 6 */

+#define RTC_ATAMP_7                       6u   /*!< Tamper 7 */

+#define RTC_ATAMP_8                       7u   /*!< Tamper 8 */

+/**

+  * @}

+  */

+

+/** @defgroup RTCEx_Tamper_Registers_Offset  RTC Tamper Registers Offset

+  * @{

+  */

+#if defined (TAMP_CR1_TAMP1E)

+/* Add this offset to RTC registers base address to reach TAMP registers base address. */

+#define TAMP_OFFSET (TAMP_BASE - RTC_BASE)

+#endif /* TAMP_CR1_TAMP1E */

+/**

+  * @}

+  */

+

+/* ========================================================================== */

+/*                   ##### RTC Wake-up exported constants #####               */

+/* ========================================================================== */

+

+/** @defgroup RTCEx_Wakeup_Timer_Definitions RTC Wakeup Timer Definitions

+  * @{

+  */

+#define RTC_WAKEUPCLOCK_RTCCLK_DIV16        0x00000000u

+#define RTC_WAKEUPCLOCK_RTCCLK_DIV8         RTC_CR_WUCKSEL_0

+#define RTC_WAKEUPCLOCK_RTCCLK_DIV4         RTC_CR_WUCKSEL_1

+#define RTC_WAKEUPCLOCK_RTCCLK_DIV2         (RTC_CR_WUCKSEL_0 | RTC_CR_WUCKSEL_1)

+#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS      RTC_CR_WUCKSEL_2

+#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS      (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_2)

+/**

+  * @}

+  */

+

+/* ========================================================================== */

+/*        ##### Extended RTC Peripheral Control exported constants #####      */

+/* ========================================================================== */

+

+/** @defgroup RTCEx_Smooth_calib_period_Definitions RTC Smooth Calib Period Definitions

+  * @{

+  */

+#define RTC_SMOOTHCALIB_PERIOD_32SEC   0x00000000u             /*!< If RTCCLK = 32768 Hz, Smooth calibration

+                                                                    period is 32s,  else 2exp20 RTCCLK pulses */

+#define RTC_SMOOTHCALIB_PERIOD_16SEC   RTC_CALR_CALW16         /*!< If RTCCLK = 32768 Hz, Smooth calibration

+                                                                    period is 16s, else 2exp19 RTCCLK pulses */

+#define RTC_SMOOTHCALIB_PERIOD_8SEC    RTC_CALR_CALW8          /*!< If RTCCLK = 32768 Hz, Smooth calibration

+                                                                    period is 8s, else 2exp18 RTCCLK pulses */

+/**

+  * @}

+  */

+

+/** @defgroup RTCEx_Smooth_calib_Plus_pulses_Definitions RTC Smooth Calib Plus pulses Definitions

+  * @{

+  */

+#define RTC_SMOOTHCALIB_PLUSPULSES_SET    RTC_CALR_CALP           /*!< The number of RTCCLK pulses added

+                                                                       during a X -second window = Y - CALM[8:0]

+                                                                       with Y = 512, 256, 128 when X = 32, 16, 8 */

+#define RTC_SMOOTHCALIB_PLUSPULSES_RESET  0x00000000u             /*!< The number of RTCCLK pulses subbstited

+                                                                       during a 32-second window = CALM[8:0] */

+/**

+  * @}

+  */

+

+/** @defgroup RTCEx_Calib_Output_selection_Definitions RTC Calib Output Selection Definitions

+  * @{

+  */

+#define RTC_CALIBOUTPUT_512HZ            0x00000000u

+#define RTC_CALIBOUTPUT_1HZ              RTC_CR_COSEL

+/**

+  * @}

+  */

+

+/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions RTC Add 1 Second Parameter Definitions

+  * @{

+  */

+#define RTC_SHIFTADD1S_RESET      0x00000000u

+#define RTC_SHIFTADD1S_SET        RTC_SHIFTR_ADD1S

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macros -----------------------------------------------------------*/

+

+/** @defgroup RTCEx_Exported_Macros RTC Exported Macros

+  * @{

+  */

+

+/* ========================================================================== */

+/*                    ##### RTC Wake-up exported macros #####                 */

+/* ========================================================================== */

+

+/**

+  * @brief  Enable the RTC WakeUp Timer peripheral.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @retval None

+  */

+#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__)                     ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))

+

+/**

+  * @brief  Disable the RTC WakeUp Timer peripheral.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @retval None

+  */

+#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__)                    ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))

+

+/**

+  * @brief  Enable the RTC WakeUpTimer interrupt.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled.

+  *         This parameter can be:

+  *            @arg @ref RTC_IT_WUT WakeUpTimer interrupt

+  * @retval None

+  */

+#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

+

+/**

+  * @brief  Disable the RTC WakeUpTimer interrupt.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be disabled.

+  *         This parameter can be:

+  *            @arg @ref RTC_IT_WUT WakeUpTimer interrupt

+  * @retval None

+  */

+#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

+

+/**

+  * @brief  Check whether the specified RTC WakeUpTimer interrupt has occurred or not.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @param  __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to check.

+  *         This parameter can be:

+  *            @arg RTC_FLAG_WUTF WakeUpTimer interrupt flag

+  * @retval None

+  */

+#if defined(RTC_SR_WUTF)

+#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->SR)  & (__INTERRUPT__)) != 0U) ? 1U : 0U)

+#endif /* RTC_SR_WUTF */

+#if defined(RTC_ISR_WUTF)

+#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->ISR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)

+#endif /* RTC_ISR_WUTF */

+

+/**

+  * @brief  Check whether the specified RTC Wake Up timer interrupt has been enabled or not.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @param  __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check.

+  *         This parameter can be:

+  *            @arg @ref RTC_IT_WUT  WakeUpTimer interrupt

+  * @retval None

+  */

+#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)   (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)

+

+#if defined(RTC_SR_WUTF)

+/**

+  * @brief  Get the selected RTC WakeUpTimer's flag status.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @param  __FLAG__ specifies the RTC WakeUpTimer Flag sources to check.

+  *          This parameter can be:

+  *             @arg @ref RTC_FLAG_WUTF

+  * @retval Flag status

+  */

+#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)   (((((__HANDLE__)->Instance->SR)  & (__FLAG__)) != 0U) ? 1U : 0U)

+#endif /* RTC_SR_WUTF */

+#if defined(RTC_ISR_WUTF)

+/**

+  * @brief  Get the selected RTC WakeUpTimer's flag status.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @param  __FLAG__ specifies the RTC WakeUpTimer Flag sources to check.

+  *          This parameter can be:

+  *             @arg @ref RTC_FLAG_WUTF

+  *             @arg @ref RTC_FLAG_WUTWF

+  * @retval Flag status

+  */

+#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)   (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)

+#endif /* RTC_ISR_WUTF */

+

+/**

+  * @brief  Clear the RTC Wake Up timer's pending flags.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @param  __FLAG__ specifies the RTC WakeUpTimer Flag to clear.

+  *         This parameter can be:

+  *            @arg @ref RTC_FLAG_WUTF

+  * @retval None

+  */

+#if defined(RTC_SCR_CWUTF)

+#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SCR |= __FLAG__)

+#endif /* RTC_SCR_CWUTF */

+#if defined(RTC_ISR_WUTF)

+#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))

+#endif /* RTC_ISR_WUTF */

+

+/* ========================================================================== */

+/*                     ##### RTC Tamper exported macros #####                 */

+/* ========================================================================== */

+

+/**

+  * @brief  Enable the RTC Tamper1 input detection.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @retval None

+  */

+#if defined(TAMP_CR1_TAMP1E)

+#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__)           (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 |= (TAMP_CR1_TAMP1E))

+#endif /* TAMP_CR1_TAMP1E */

+#if defined(RTC_TAMPCR_TAMP1E)

+#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__)           ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E))

+#endif /* RTC_TAMPCR_TAMP1E */

+

+/**

+  * @brief  Disable the RTC Tamper1 input detection.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @retval None

+  */

+#if defined(TAMP_CR1_TAMP1E)

+#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__)          (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 &= ~(RTC_TAMPCR_TAMP1E))

+#endif /* TAMP_CR1_TAMP1E */

+#if defined(RTC_TAMPCR_TAMP1E)

+#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__)          ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E))

+#endif /* RTC_TAMPCR_TAMP1E */

+

+/**

+  * @brief  Enable the RTC Tamper2 input detection.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @retval None

+  */

+#if defined(TAMP_CR1_TAMP2E)

+#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__)           (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 |= (TAMP_CR1_TAMP2E))

+#endif /* TAMP_CR1_TAMP2E */

+#if defined(RTC_TAMPCR_TAMP2E)

+#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__)           ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E))

+#endif /* RTC_TAMPCR_TAMP2E */

+

+/**

+  * @brief  Disable the RTC Tamper2 input detection.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @retval None

+  */

+#if defined(TAMP_CR1_TAMP2E)

+#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__)          (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + (TAMP_OFFSET))->CR1 &= ~(RTC_TAMPCR_TAMP2E))

+#endif /* TAMP_CR1_TAMP2E */

+#if defined(RTC_TAMPCR_TAMP2E)

+#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__)          ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E))

+#endif /* RTC_TAMPCR_TAMP2E */

+

+/**

+  * @brief  Enable the RTC Tamper3 input detection.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @retval None

+  */

+#if defined(TAMP_CR1_TAMP3E)

+#define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__)          (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 |= (TAMP_CR1_TAMP3E))

+#endif /* TAMP_CR1_TAMP3E */

+#if defined(RTC_TAMPCR_TAMP3E)

+#define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__)          ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E))

+#endif /* RTC_TAMPCR_TAMP3E */

+

+/**

+  * @brief  Disable the RTC Tamper3 input detection.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @retval None

+  */

+#if defined(TAMP_CR1_TAMP3E)

+#define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__)          (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->CR1 &= ~(RTC_TAMPCR_TAMP3E))

+#endif /* TAMP_CR1_TAMP3E */

+#if defined(RTC_TAMPCR_TAMP3E)

+#define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__)          ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E))

+#endif /* RTC_TAMPCR_TAMP3E */

+

+/**

+  * @brief  Enable the RTC Tamper interrupt.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled.

+  *          This parameter can be any combination of the following values:

+  *             @arg  RTC_IT_TAMPALL: All tampers interrupts

+  *             @arg  RTC_IT_TAMP1: Tamper1 interrupt

+  *             @arg  RTC_IT_TAMP2: Tamper2 interrupt

+  *             @arg  RTC_IT_TAMP3: Tamper3 interrupt

+  * @retval None

+  */

+#if defined(TAMP_IER_TAMP1IE)

+#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__)        (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->IER |= (__INTERRUPT__))

+#endif /* TAMP_IER_TAMP1IE */

+#if defined(RTC_TAMPCR_TAMP1IE)

+#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__)        ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__))

+#endif /* RTC_TAMPCR_TAMP1IE */

+

+/**

+  * @brief  Disable the RTC Tamper interrupt.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled.

+  *         This parameter can be any combination of the following values:

+  *            @arg  RTC_IT_TAMP: All tampers interrupts

+  *            @arg  RTC_IT_TAMP1: Tamper1 interrupt

+  *            @arg  RTC_IT_TAMP2: Tamper2 interrupt

+  *            @arg  RTC_IT_TAMP3: Tamper3 interrupt

+  * @retval None

+  */

+#if defined(TAMP_IER_TAMP1IE)

+#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__)       (((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->IER &= ~(__INTERRUPT__))

+#endif /* TAMP_IER_TAMP1IE */

+#if defined(RTC_TAMPCR_TAMP1IE)

+#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__)       ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__))

+#endif /* RTC_TAMPCR_TAMP1IE */

+

+/**

+  * @brief  Check whether the specified RTC Tamper interrupt has occurred or not.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt to check.

+  *         This parameter can be:

+  *            @arg  RTC_FLAG_TAMP1F: Tamper1 interrupt flag

+  *            @arg  RTC_FLAG_TAMP2F: Tamper2 interrupt flag

+  *            @arg  RTC_FLAG_TAMP3F: Tamper3 interrupt flag

+  * @retval Flag status

+  */

+#if defined(TAMP_SR_TAMP1F)

+#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)     ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->SR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)

+#endif /* TAMP_SR_TAMP1F */

+#if defined(RTC_ISR_TAMP1F)

+#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->ISR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)

+#endif /* RTC_ISR_TAMP1F */

+

+/**

+  * @brief  Check whether the specified RTC Tamper interrupt has been enabled or not.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @param  __INTERRUPT__ specifies the RTC Tamper interrupt source to check.

+  *         This parameter can be:

+  *            @arg  RTC_IT_TAMPALL: All tampers interrupts

+  *            @arg  RTC_IT_TAMP1: Tamper1 interrupt

+  *            @arg  RTC_IT_TAMP2: Tamper2 interrupt

+  *            @arg  RTC_IT_TAMP3: Tamper3 interrupt

+  * @retval Flag status

+  */

+#if defined(TAMP_IER_TAMP1IE)

+#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)    ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->IER) & (__INTERRUPT__)) != 0U) ? 1U : 0U)

+#endif /* TAMP_IER_TAMP1IE */

+#if defined(RTC_TAMPCR_TAMP1IE)

+#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)    (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)

+#endif /* RTC_TAMPCR_TAMP1IE */

+

+/**

+  * @brief  Get the selected RTC Tamper's flag status.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @param  __FLAG__ specifies the RTC Tamper Flag is pending or not.

+  *          This parameter can be:

+  *             @arg RTC_FLAG_TAMP1F: Tamper1 flag

+  *             @arg RTC_FLAG_TAMP2F: Tamper2 flag

+  *             @arg RTC_FLAG_TAMP3F: Tamper3 flag

+  * @retval Flag status

+  */

+#if defined(TAMP_SR_TAMP1F)

+#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)   ((((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->SR) & (__FLAG__)) != 0U) ? 1U : 0U)

+#endif /* TAMP_SR_TAMP1F */

+#if defined(RTC_ISR_TAMP1F)

+#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)                               (((((__HANDLE__)->Instance->ISR)                  & (__FLAG__)) != 0U) ? 1U : 0U)

+#endif /* RTC_ISR_TAMP1F */

+

+/**

+  * @brief  Clear the RTC Tamper's pending flags.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @param  __FLAG__ specifies the RTC Tamper Flag to clear.

+  *          This parameter can be:

+  *             @arg RTC_FLAG_TAMP1F: Tamper1 flag

+  *             @arg RTC_FLAG_TAMP2F: Tamper2 flag

+  *             @arg RTC_FLAG_TAMP3F: Tamper3 flag

+  * @retval None

+  */

+#if defined(TAMP_SCR_CTAMP1F)

+#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->SCR) |= (__FLAG__))

+#endif /* TAMP_SCR_CTAMP1F */

+#if defined(RTC_ISR_TAMP1F)

+#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__)      ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))

+#endif /* RTC_ISR_TAMP1F */

+

+/**

+  * @brief  Get the frequency at which each of the Tamper inputs are sampled.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @retval Sampling frequency

+  *         This value can be:

+  *            @arg RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768

+  *            @arg RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384

+  *            @arg RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192

+  *            @arg RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096

+  *            @arg RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048

+  *            @arg RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512

+  *            @arg RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256

+  */

+#if defined(TAMP_FLTCR_TAMPFREQ)

+#define __HAL_RTC_TAMPER_GET_SAMPLING_FREQ(__HANDLE__)   ((uint32_t)((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->FLTCR) & (RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK)))

+#endif /* TAMP_FLTCR_TAMPFREQ */

+#if defined(RTC_TAMPCR_TAMPFREQ)

+#define __HAL_RTC_TAMPER_GET_SAMPLING_FREQ(__HANDLE__)   ((uint32_t)(((__HANDLE__)->Instance->TAMPCR) & (RTC_TAMPERSAMPLINGFREQ_RTCCLK_MASK)))

+#endif /* RTC_TAMPCR_TAMPFREQ */

+

+/**

+  * @brief  Get the number of consecutive samples at the specified level needed

+  *         to activate a Tamper event.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @retval Number of consecutive samples

+  *         This value can be:

+  *            @arg RTC_TAMPERFILTER_DISABLE

+  *            @arg RTC_TAMPERFILTER_2SAMPLE

+  *            @arg RTC_TAMPERFILTER_4SAMPLE

+  *            @arg RTC_TAMPERFILTER_8SAMPLE

+  */

+#if defined(TAMP_FLTCR_TAMPFLT)

+#define __HAL_RTC_TAMPER_GET_SAMPLES_COUNT(__HANDLE__)   ((uint32_t)((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->FLTCR) & (RTC_TAMPERFILTER_MASK)))

+#endif /* TAMP_FLTCR_TAMPFLT */

+#if defined(RTC_TAMPCR_TAMPFLT)

+#define __HAL_RTC_TAMPER_GET_SAMPLES_COUNT(__HANDLE__)   ((uint32_t)(((__HANDLE__)->Instance->TAMPCR) & (RTC_TAMPERFILTER_MASK)))

+#endif /* RTC_TAMPCR_TAMPFLT */

+

+/**

+  * @brief  Get the pull-up resistors precharge duration.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @retval Number of consecutive samples

+  *         This value can be:

+  *            @arg RTC_TAMPERPRECHARGEDURATION_1RTCCLK

+  *            @arg RTC_TAMPERPRECHARGEDURATION_2RTCCLK

+  *            @arg RTC_TAMPERPRECHARGEDURATION_4RTCCLK

+  *            @arg RTC_TAMPERPRECHARGEDURATION_8RTCCLK

+  */

+#if defined(TAMP_FLTCR_TAMPPRCH)

+#define __HAL_RTC_TAMPER_GET_PRCHRG_DURATION(__HANDLE__)   ((uint32_t)((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->FLTCR) & (RTC_TAMPERPRECHARGEDURATION_MASK)))

+#endif /* TAMP_FLTCR_TAMPPRCH */

+#if defined(RTC_TAMPCR_TAMPPRCH)

+#define __HAL_RTC_TAMPER_GET_PRCHRG_DURATION(__HANDLE__)   ((uint32_t)(((__HANDLE__)->Instance->TAMPCR) & (RTC_TAMPERPRECHARGEDURATION_MASK)))

+#endif /* RTC_TAMPCR_TAMPPRCH */

+

+/**

+  * @brief  Get the pull-up resistors status.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @retval Pull-up resistors status

+  *         This value can be:

+  *            @arg RTC_TAMPER_PULLUP_ENABLE

+  *            @arg RTC_TAMPER_PULLUP_DISABLE

+  */

+#if defined(TAMP_FLTCR_TAMPPUDIS)

+#define __HAL_RTC_TAMPER_GET_PULLUP_STATUS(__HANDLE__)   ((uint32_t)((((TAMP_TypeDef *)((uint32_t)((__HANDLE__)->Instance) + TAMP_OFFSET))->FLTCR) & (RTC_TAMPER_PULLUP_MASK)))

+#endif /* TAMP_FLTCR_TAMPPUDIS */

+#if defined(RTC_TAMPCR_TAMPPUDIS)

+#define __HAL_RTC_TAMPER_GET_PULLUP_STATUS(__HANDLE__)   ((uint32_t)(((__HANDLE__)->Instance->TAMPCR) & (RTC_TAMPER_PULLUP_MASK)))

+#endif /* RTC_TAMPCR_TAMPPUDIS */

+

+/* ========================================================================== */

+/*                  ##### RTC TimeStamp exported macros #####                 */

+/* ========================================================================== */

+

+/**

+  * @brief  Enable the RTC TimeStamp peripheral.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @retval None

+  */

+#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))

+

+/**

+  * @brief  Disable the RTC TimeStamp peripheral.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @retval None

+  */

+#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))

+

+/**

+  * @brief  Enable the RTC TimeStamp interrupt.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be enabled.

+  *         This parameter can be:

+  *            @arg @ref RTC_IT_TS TimeStamp interrupt

+  * @retval None

+  */

+#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))

+

+/**

+  * @brief  Disable the RTC TimeStamp interrupt.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt source to be disabled.

+  *         This parameter can be:

+  *            @arg @ref RTC_IT_TS TimeStamp interrupt

+  * @retval None

+  */

+#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))

+

+/**

+  * @brief  Check whether the specified RTC TimeStamp interrupt has occurred or not.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @param  __INTERRUPT__ specifies the RTC TimeStamp interrupt source to check.

+  *         This parameter can be:

+  *            @arg @ref RTC_IT_TS TimeStamp interrupt

+  * @retval None

+  */

+#if defined(RTC_SR_TSF)

+#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__)        (((((__HANDLE__)->Instance->MISR) & ((__INTERRUPT__) >> 12)) != 0U) ? 1U : 0U)

+#endif /* RTC_SR_TSF */

+#if defined(RTC_ISR_TSF)

+#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__)        (((((__HANDLE__)->Instance->ISR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)

+#endif /* RTC_ISR_TSF */

+/**

+  * @brief  Check whether the specified RTC Time Stamp interrupt has been enabled or not.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @param  __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check.

+  *         This parameter can be:

+  *            @arg @ref RTC_IT_TS TimeStamp interrupt

+  * @retval None

+  */

+#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)     (((((__HANDLE__)->Instance->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)

+

+/**

+  * @brief  Get the selected RTC TimeStamp's flag status.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @param  __FLAG__ specifies the RTC TimeStamp Flag is pending or not.

+  *         This parameter can be:

+  *            @arg RTC_FLAG_TSF

+  *            @arg RTC_FLAG_TSOVF

+  * @retval Flag status

+  */

+#if defined(RTC_SR_TSF)

+#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)     (((((__HANDLE__)->Instance->SR)  & (__FLAG__)) != 0U) ? 1U : 0U)

+#endif /* RTC_SR_TSF */

+#if defined(RTC_ISR_TSF)

+#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)     (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)

+#endif /* RTC_ISR_TSF */

+

+/**

+  * @brief  Clear the RTC Time Stamp's pending flags.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @param  __FLAG__ specifies the RTC Alarm Flag sources to clear.

+  *          This parameter can be:

+  *             @arg RTC_FLAG_TSF

+  *             @arg RTC_FLAG_TSOVF

+  * @retval None

+  */

+#if defined(RTC_SCR_CTSF)

+#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)   ((__HANDLE__)->Instance->SCR |= __FLAG__)

+#endif /* RTC_SCR_CTSF */

+#if defined(RTC_ISR_TSF)

+#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)   ((__HANDLE__)->Instance->ISR = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)))

+#endif /* RTC_ISR_TSF */

+

+/**

+  * @brief  Enable the RTC internal TimeStamp peripheral.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @retval None

+  */

+#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE))

+

+/**

+  * @brief  Disable the RTC internal TimeStamp peripheral.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @retval None

+  */

+#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE))

+

+/**

+  * @brief  Get the selected RTC Internal Time Stamp's flag status.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @param  __FLAG__ specifies the RTC Internal Time Stamp Flag is pending or not.

+  *         This parameter can be:

+  *            @arg RTC_FLAG_ITSF

+  * @retval Flag status

+  */

+#if defined(RTC_SR_ITSF)

+#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)    (((((__HANDLE__)->Instance->SR)  & (__FLAG__)) != 0U) ? 1U : 0U)

+#endif /* RTC_SR_ITSF */

+#if defined(RTC_ISR_ITSF)

+#define __HAL_RTC_INTERNAL_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)    (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)

+#endif /* RTC_ISR_ITSF */

+

+/**

+  * @brief  Clear the RTC Internal Time Stamp's pending flags.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @param  __FLAG__ specifies the RTC Internal Time Stamp Flag source to clear.

+  *          This parameter can be:

+  *             @arg RTC_FLAG_ITSF

+  * @note   This flag must be cleared together with TSF flag.

+  * @retval None

+  */

+#if defined(RTC_SCR_CITSF)

+#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)  ((__HANDLE__)->Instance->SCR |= __FLAG__)

+#endif /* RTC_SCR_CITSF */

+#if defined(RTC_ISR_ITSF)

+#define __HAL_RTC_INTERNAL_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)  ((__HANDLE__)->Instance->ISR = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)))

+#endif /* RTC_ISR_ITSF */

+

+/**

+  * @brief  Enable the RTC TimeStamp on Tamper detection.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @retval None

+  */

+#if defined(RTC_CR_TAMPTS)

+#define __HAL_RTC_TAMPTS_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR |= (RTC_TIMESTAMPONTAMPERDETECTION_MASK))

+#endif /* RTC_CR_TAMPTS */

+#if defined(RTC_TAMPCR_TAMPTS)

+#define __HAL_RTC_TAMPTS_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->TAMPCR |= (RTC_TIMESTAMPONTAMPERDETECTION_MASK))

+#endif /* RTC_TAMPCR_TAMPTS */

+

+/**

+  * @brief  Disable the RTC TimeStamp on Tamper detection.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @retval None

+  */

+#if defined(RTC_CR_TAMPTS)

+#define __HAL_RTC_TAMPTS_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR &= ~(RTC_TIMESTAMPONTAMPERDETECTION_MASK))

+#endif /* RTC_CR_TAMPTS */

+#if defined(RTC_TAMPCR_TAMPTS)

+#define __HAL_RTC_TAMPTS_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TIMESTAMPONTAMPERDETECTION_MASK))

+#endif /* RTC_TAMPCR_TAMPTS */

+

+/**

+  * @brief  Get activation status of the RTC TimeStamp on Tamper detection.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @retval Activation status of TimeStamp on Tamper detection

+  *         This value can be:

+  *            @arg RTC_TIMESTAMPONTAMPERDETECTION_ENABLE

+  *            @arg RTC_TIMESTAMPONTAMPERDETECTION_DISABLE

+  */

+#if defined(RTC_CR_TAMPTS)

+#define __HAL_RTC_TAMPTS_GET_STATUS(__HANDLE__)                   ((__HANDLE__)->Instance->CR &= RTC_TIMESTAMPONTAMPERDETECTION_MASK)

+#endif /* RTC_CR_TAMPTS */

+#if defined(RTC_TAMPCR_TAMPTS)

+#define __HAL_RTC_TAMPTS_GET_STATUS(__HANDLE__)                   ((__HANDLE__)->Instance->TAMPCR &= RTC_TIMESTAMPONTAMPERDETECTION_MASK)

+#endif /* RTC_TAMPCR_TAMPTS */

+

+#if defined(RTC_CR_TAMPOE)

+/**

+  * @brief  Enable the RTC Tamper detection output.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @retval None

+  */

+#define __HAL_RTC_TAMPOE_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR |= (RTC_CR_TAMPOE))

+

+/**

+  * @brief  Disable the RTC Tamper detection output.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @retval None

+  */

+#define __HAL_RTC_TAMPOE_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TAMPOE))

+#endif /* RTC_CR_TAMPOE */

+

+/* ========================================================================== */

+/*         ##### Extended RTC Peripheral Control exported macros #####        */

+/* ========================================================================== */

+

+/**

+  * @brief  Enable the RTC calibration output.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @retval None

+  */

+#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))

+

+/**

+  * @brief  Disable the calibration output.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @retval None

+  */

+#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))

+

+/**

+  * @brief  Enable the clock reference detection.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @retval None

+  */

+#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))

+

+/**

+  * @brief  Disable the clock reference detection.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @retval None

+  */

+#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))

+

+/**

+  * @brief  Get the selected RTC shift operation's flag status.

+  * @param  __HANDLE__ specifies the RTC handle.

+  * @param  __FLAG__ specifies the RTC shift operation Flag is pending or not.

+  *          This parameter can be:

+  *             @arg RTC_FLAG_SHPF

+  * @retval Flag status

+  */

+#if defined(RTC_ICSR_SHPF)

+#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__)         (((((__HANDLE__)->Instance->ICSR) & (__FLAG__)) != 0U) ? 1U : 0U)

+#endif /* RTC_ICSR_SHPF */

+#if defined(RTC_ISR_SHPF)

+#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__)         (((((__HANDLE__)->Instance->ISR)  & (__FLAG__)) != 0U) ? 1U : 0U)

+#endif /* RTC_ISR_SHPF */

+

+/**

+  * @}

+  */

+

+/* ========================================================================== */

+/*               ##### RTC Wake-up Interrupt exported macros #####            */

+/* ========================================================================== */

+

+/**

+  * @brief  Enable interrupt on the RTC WakeUp Timer associated Exti line.

+  * @retval None

+  */

+#if defined(EXTI_D1)

+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT()       (EXTI_D1->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

+#else  /* EXTI */

+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT()       (EXTI->IMR1    |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

+#endif /* EXTI_D1 */

+/**

+  * @brief  Disable interrupt on the RTC WakeUp Timer associated Exti line.

+  * @retval None

+  */

+#if defined(EXTI_D1)

+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT()      (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

+#else  /* EXTI */

+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT()      (EXTI->IMR1    &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

+#endif /* EXTI_D1 */

+

+/**

+  * @brief  Enable event on the RTC WakeUp Timer associated Exti line.

+  * @retval None

+  */

+#if defined(EXTI_D1)

+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT()    (EXTI_D1->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

+#else  /* EXTI */

+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT()    (EXTI->EMR1    |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

+#endif /* EXTI_D1 */

+

+/**

+  * @brief  Disable event on the RTC WakeUp Timer associated Exti line.

+  * @retval None

+  */

+#if defined(EXTI_D1)

+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

+#else  /* EXTI */

+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT()   (EXTI->EMR1    &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

+#endif /* EXTI_D1 */

+

+/**

+  * @brief  Enable event on the RTC WakeUp Timer associated D3 Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_WAKEUPTIMER_EXTID3_ENABLE_EVENT()    (EXTI->D3PMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

+

+/**

+  * @brief  Disable event on the RTC WakeUp Timer associated D3 Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_WAKEUPTIMER_EXTID3_DISABLE_EVENT()   (EXTI->D3PMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

+

+#if defined(DUAL_CORE)

+/**

+  * @brief  Enable interrupt on the RTC WakeUp Timer associated D2 Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_WAKEUPTIMER_EXTID2_ENABLE_IT()       (EXTI_D2->IMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

+

+/**

+  * @brief  Disable interrupt on the RTC WakeUp Timer associated D2 Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_WAKEUPTIMER_EXTID2_DISABLE_IT()      (EXTI_D2->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

+

+/**

+  * @brief  Enable event on the RTC WakeUp Timer associated D2 Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_WAKEUPTIMER_EXTID2_ENABLE_EVENT()    (EXTI_D2->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

+

+/**

+  * @brief  Disable event on the RTC WakeUp Timer associated D2 Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_WAKEUPTIMER_EXTID2_DISABLE_EVENT()   (EXTI_D2->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

+

+#endif /* DUAL_CORE */

+

+/**

+  * @brief  Enable falling edge trigger on the RTC WakeUp Timer associated Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

+

+/**

+  * @brief  Disable falling edge trigger on the RTC WakeUp Timer associated Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

+

+/**

+  * @brief  Enable rising edge trigger on the RTC WakeUp Timer associated Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

+

+/**

+  * @brief  Disable rising edge trigger on the RTC WakeUp Timer associated Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT))

+

+/**

+  * @brief  Enable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE()  do { \

+                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();  \

+                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE(); \

+                                                                 } while(0)

+

+/**

+  * @brief  Disable rising & falling edge trigger on the RTC WakeUp Timer associated Exti line.

+  * This parameter can be:

+  * @retval None

+  */

+#define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \

+                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();  \

+                                                                   __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE(); \

+                                                                  } while(0)

+

+/**

+  * @brief Check whether the RTC WakeUp Timer associated Exti line interrupt flag is set or not.

+  * @retval Line Status.

+  */

+#if defined(EXTI_D1)

+#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG()              (EXTI_D1->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

+#else  /* EXTI */

+#define __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG()              (EXTI->PR1    & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

+#endif /* EXTI_D1 */

+

+/**

+  * @brief Clear the RTC WakeUp Timer associated Exti line flag.

+  * @retval None

+  */

+#if defined(EXTI_D1)

+#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG()            (EXTI_D1->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

+#else  /* EXTI */

+#define __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG()            (EXTI->PR1    = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

+#endif /* EXTI_D1 */

+

+/**

+  * @brief Check whether the RTC WakeUp Timer associated D3 Exti line interrupt flag is set or not.

+  * @retval Line Status

+  */

+#define __HAL_RTC_WAKEUPTIMER_EXTID3_GET_FLAG()            (EXTI_D3->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

+

+/**

+  * @brief Clear the RTC WakeUp Timer associated D3 Exti line flag.

+  * @retval None.

+  */

+#define __HAL_RTC_WAKEUPTIMER_EXTID3_CLEAR_FLAG()          (EXTI_D3->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

+

+/**

+  * @brief Generate a Software interrupt on the RTC WakeUp Timer associated Exti line.

+  * @retval None.

+  */

+#define __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT()         (EXTI->SWIER1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

+

+#if defined(DUAL_CORE)

+

+/**

+  * @brief Check whether the RTC WakeUp Timer associated D2 Exti line interrupt flag is set or not.

+  * @retval Line Status.

+  */

+#define __HAL_RTC_WAKEUPTIMER_EXTID2_GET_FLAG()            (EXTI_D2->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

+

+/**

+  * @brief Clear the RTC WakeUp Timer associated D2 Exti line flag.

+  * @retval None.

+  */

+#define __HAL_RTC_WAKEUPTIMER_EXTID2_CLEAR_FLAG()          (EXTI_D2->PR1 = RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

+

+#endif /* DUAL_CORE */

+

+/* ========================================================================== */

+/*       ##### RTC TimeStamp and Tamper Interrupt exported macros #####       */

+/* ========================================================================== */

+

+/**

+  * @brief  Enable interrupt on the RTC Tamper and Timestamp associated Exti line.

+  * @retval None

+  */

+#if defined(EXTI_D1)

+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()        (EXTI_D1->IMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

+#else  /* EXTI */

+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT()        (EXTI->IMR1    |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

+#endif /* EXTI_D1 */

+

+/**

+  * @brief  Disable interrupt on the RTC Tamper and Timestamp associated Exti line.

+  * @retval None

+  */

+#if defined(EXTI_D1)

+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()       (EXTI_D1->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

+#else  /* EXTI */

+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT()       (EXTI->IMR1    &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

+#endif /* EXTI_D1 */

+

+/**

+  * @brief  Enable event on the RTC Tamper and Timestamp associated Exti line.

+  * @retval None

+  */

+#if defined(EXTI_D1)

+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT()    (EXTI_D1->EMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

+#else  /* EXTI */

+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_EVENT()    (EXTI->EMR1    |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

+#endif /* EXTI_D1 */

+

+/**

+  * @brief  Disable event on the RTC Tamper and Timestamp associated Exti line.

+  * @retval None

+  */

+#if defined(EXTI_D1)

+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT()   (EXTI_D1->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

+#else  /* EXTI */

+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_EVENT()   (EXTI->EMR1    &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

+#endif /* EXTI_D1 */

+

+/**

+  * @}

+  */

+

+#if defined(DUAL_CORE)

+/**

+  * @brief  Enable interrupt on the RTC Tamper and Timestamp associated D2 Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTID2_ENABLE_IT()      (EXTI_D2->IMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

+

+/**

+  * @brief  Disable interrupt on the RTC Tamper and Timestamp associated D2 Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTID2_DISABLE_IT()     (EXTI_D2->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

+

+

+/**

+  * @brief  Enable event on the RTC Tamper and Timestamp associated D2 Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTID2_ENABLE_EVENT()  (EXTI_D2->EMR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

+

+

+/**

+  * @brief  Disable event on the RTC Tamper and Timestamp associated D2 Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTID2_DISABLE_EVENT() (EXTI_D2->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

+

+#endif /* DUAL_CORE */

+

+/**

+  * @brief  Enable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE()   (EXTI->FTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

+

+/**

+  * @brief  Disable falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE()  (EXTI->FTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

+

+/**

+  * @brief  Enable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE()    (EXTI->RTSR1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

+

+/**

+  * @brief  Disable rising edge trigger on the RTC Tamper and Timestamp associated Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE()   (EXTI->RTSR1 &= ~(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT))

+

+/**

+  * @brief  Enable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_FALLING_EDGE()  do { \

+                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_RISING_EDGE();  \

+                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_FALLING_EDGE(); \

+                                                                      } while(0)

+

+/**

+  * @brief  Disable rising & falling edge trigger on the RTC Tamper and Timestamp associated Exti line.

+  * @retval None

+  */

+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_FALLING_EDGE()  do { \

+                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_RISING_EDGE();  \

+                                                                        __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_FALLING_EDGE(); \

+                                                                       } while(0)

+

+/**

+  * @brief Check whether the RTC Tamper and Timestamp associated Exti line interrupt flag is set or not.

+  * @retval Line Status

+  */

+#if defined(EXTI_D1)

+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()         (EXTI_D1->PR1 & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

+#else  /* EXTI */

+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG()         (EXTI->PR1    & RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

+#endif /* EXTI_D1 */

+

+/**

+  * @brief Clear the RTC Tamper and Timestamp associated Exti line flag.

+  * @retval None

+  */

+#if defined(EXTI_D1)

+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()       (EXTI_D1->PR1 = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

+#else  /* EXTI */

+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG()       (EXTI->PR1    = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

+#endif /* EXTI_D1 */

+

+#if defined(DUAL_CORE)

+/**

+  * @brief Check whether the RTC Tamper and Timestamp associated D2 Exti line interrupt flag is set or not.

+  * @retval Line Status

+  */

+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTID2_GET_FLAG()       (EXTI_D2->PR1 & RTC_EXTI_LINE_WAKEUPTIMER_EVENT)

+

+/**

+  * @brief Clear the RTC Tamper and Timestamp associated D2 Exti line flag.

+  * @retval None

+  */

+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTID2_CLEAR_FLAG()     (EXTI_D2->PR1 = RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

+

+#endif  /* DUAL_CORE */

+

+/**

+  * @brief Generate a Software interrupt on the RTC Tamper and Timestamp associated Exti line

+  * @retval None

+  */

+#define __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()    (EXTI->SWIER1 |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT)

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+

+/** @defgroup RTCEx_Exported_Functions RTC Exported Functions

+  * @{

+  */

+

+/* ========================================================================== */

+/*                  ##### RTC TimeStamp exported functions #####              */

+/* ========================================================================== */

+

+/* RTC TimeStamp functions ****************************************************/

+

+/** @defgroup RTCEx_Exported_Functions_Group1 Extended RTC TimeStamp functions

+  * @{

+  */

+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);

+HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge, uint32_t RTC_TimeStampPin);

+HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);

+HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc);

+HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc);

+HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);

+void              HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);

+void              HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);

+HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);

+/**

+  * @}

+  */

+

+/* ========================================================================== */

+/*                    ##### RTC Tamper exported functions #####               */

+/* ========================================================================== */

+

+/* RTC Tamper functions *******************************************************/

+

+/** @defgroup RTCEx_Exported_Functions_Group5 Extended RTC Tamper functions

+  * @{

+  */

+HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);

+HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper);

+HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);

+#if defined(RTC_TAMPER_1)

+HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);

+#endif /* RTC_TAMPER_1 */

+#if defined(RTC_TAMPER_2)

+HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);

+#endif /* RTC_TAMPER_2 */

+#if defined(RTC_TAMPER_3)

+HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);

+#endif /* RTC_TAMPER_3 */

+#if defined(RTC_TAMPER_1)

+void              HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);

+#endif /* RTC_TAMPER_1 */

+#if defined(RTC_TAMPER_2)

+void              HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);

+#endif /* RTC_TAMPER_2 */

+#if defined(RTC_TAMPER_3)

+void              HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);

+#endif /* RTC_TAMPER_3 */

+#if defined(TAMP_CR1_ITAMP1E)

+HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper);

+HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper);

+HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, uint32_t IntTamper);

+HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout);

+#endif /* TAMP_CR1_ITAMP1E */

+void              HAL_RTCEx_InternalTamper1EventCallback(RTC_HandleTypeDef *hrtc);

+void              HAL_RTCEx_InternalTamper2EventCallback(RTC_HandleTypeDef *hrtc);

+void              HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc);

+void              HAL_RTCEx_InternalTamper4EventCallback(RTC_HandleTypeDef *hrtc);

+void              HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc);

+void              HAL_RTCEx_InternalTamper6EventCallback(RTC_HandleTypeDef *hrtc);

+void              HAL_RTCEx_InternalTamper8EventCallback(RTC_HandleTypeDef *hrtc);

+#if defined(TAMP_ATCR1_TAMP1AM)

+HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_ActiveTampersTypeDef *sAllTamper);

+#endif /* TAMP_ATCR1_TAMP1AM */

+#if defined(TAMP_ATSEEDR_SEED)

+HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, uint32_t *pSeed);

+#endif /* TAMP_ATSEEDR_SEED */

+#if defined(TAMP_ATCR1_TAMP1AM)

+HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(RTC_HandleTypeDef *hrtc);

+#endif /* TAMP_ATCR1_TAMP1AM */

+

+/* ========================================================================== */

+/*                   ##### RTC Wake-up exported functions #####               */

+/* ========================================================================== */

+

+/* RTC Wake-up functions ******************************************************/

+

+/** @defgroup RTCEx_Exported_Functions_Group2 Extended RTC Wake-up functions

+  * @{

+  */

+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);

+HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);

+HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);

+uint32_t          HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);

+void              HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);

+void              HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);

+HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);

+/**

+  * @}

+  */

+

+/* ========================================================================== */

+/*         ##### Extended RTC Backup registers exported functions #####       */

+/* ========================================================================== */

+

+/* Extended RTC Backup registers functions ************************************/

+

+/** @defgroup RTCEx_Exported_Functions_Group6 Extended RTC Backup register functions

+  * @{

+  */

+void     HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);

+uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);

+/**

+  * @}

+  */

+

+/* ========================================================================== */

+/*        ##### Extended RTC Peripheral Control exported functions #####      */

+/* ========================================================================== */

+

+/* Extended RTC Peripheral Control functions **********************************/

+

+/** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions

+  * @{

+  */

+HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue);

+HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);

+HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);

+HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);

+HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);

+HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);

+HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);

+HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);

+#if defined(TAMP_COUNTR)

+HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef *hrtc);

+HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef *hrtc, uint32_t *Counter);

+#endif /* TAMP_COUNTR */

+/**

+  * @}

+  */

+

+/* Extended RTC features functions *******************************************/

+

+/** @defgroup RTCEx_Exported_Functions_Group4 Extended features functions

+  * @{

+  */

+

+void              HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc);

+HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup RTCEx_Private_Constants RTC Private Constants

+  * @{

+  */

+#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT  EXTI_IMR1_IM18  /*!< External interrupt line 18 Connected to the RTC Tamper and Time Stamp events */

+#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT       EXTI_IMR1_IM19  /*!< External interrupt line 19 Connected to the RTC Wakeup event */

+

+/* Masks Definition */

+#define RTC_TAMPER_X             ((uint32_t) (RTC_TAMPER_1 | RTC_TAMPER_2 | RTC_TAMPER_3))

+#define RTC_TAMPER_X_INTERRUPT   ((uint32_t) (RTC_IT_TAMP1 | RTC_IT_TAMP2 | RTC_IT_TAMP3))

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup RTCEx_Private_Macros RTC Private Macros

+  * @{

+  */

+

+/** @defgroup RTCEx_IS_RTC_Definitions Private macros to check input parameters

+  * @{

+  */

+

+/* ========================================================================== */

+/*          ##### Extended RTC Backup registers private macros #####          */

+/* ========================================================================== */

+

+#define IS_RTC_BKP(__BKP__)                   ((__BKP__) < BKP_REG_NUMBER)

+

+/* ========================================================================== */

+/*                  ##### RTC TimeStamp private macros #####                  */

+/* ========================================================================== */

+

+#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \

+                                 ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))

+

+#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TIMESTAMPPIN_DEFAULT))

+

+/* ========================================================================== */

+/*                    ##### RTC Wake-up private macros #####                  */

+/* ========================================================================== */

+

+#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16)       || \

+                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8)    || \

+                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4)    || \

+                                    ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2)    || \

+                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \

+                                    ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))

+

+#define IS_RTC_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= RTC_WUTR_WUT)

+

+/* ========================================================================== */

+/*               ##### RTC Smooth Calibration private macros #####            */

+/* ========================================================================== */

+

+#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \

+                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \

+                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))

+

+#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \

+                                        ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))

+

+#define  IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= RTC_CALR_CALM)

+

+/* ========================================================================== */

+/*          ##### Extended RTC Peripheral Control private macros #####        */

+/* ========================================================================== */

+

+#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \

+                                 ((SEL) == RTC_SHIFTADD1S_SET))

+

+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= RTC_SHIFTR_SUBFS)

+

+#define IS_RTC_CALIB_OUTPUT(OUTPUT)  (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \

+                                      ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))

+

+/* ========================================================================== */

+/*                    ##### RTC Tamper private macros #####                   */

+/* ========================================================================== */

+

+#define IS_RTC_TAMPER(__TAMPER__)  ((((__TAMPER__) &  RTC_TAMPER_X) != 0x00U) &&  \

+                                    (((__TAMPER__) & ~RTC_TAMPER_X) == 0x00U))

+

+#if defined(RTC_ALL_TAMPER_INTERRUPT)

+#define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__)                                                           \

+              ((((__INTERRUPT__) & (  RTC_TAMPER_X_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT )) != 0x00U) &&  \

+               (((__INTERRUPT__) & (~(RTC_TAMPER_X_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT))) == 0x00U))

+#else  /* RTC_ALL_TAMPER_INTERRUPT not defined */

+#define IS_RTC_TAMPER_INTERRUPT(__INTERRUPT__)                              \

+              ((((__INTERRUPT__) &   RTC_TAMPER_X_INTERRUPT ) != 0x00U) &&  \

+               (((__INTERRUPT__) & (~RTC_TAMPER_X_INTERRUPT)) == 0x00U))

+#endif /* RTC_ALL_TAMPER_INTERRUPT */

+

+#define IS_RTC_TAMPER_TRIGGER(__TRIGGER__) (((__TRIGGER__) == RTC_TAMPERTRIGGER_RISINGEDGE)    || \

+                                            ((__TRIGGER__) == RTC_TAMPERTRIGGER_FALLINGEDGE)   || \

+                                            ((__TRIGGER__) == RTC_TAMPERTRIGGER_LOWLEVEL)      || \

+                                            ((__TRIGGER__) == RTC_TAMPERTRIGGER_HIGHLEVEL))

+

+#define IS_RTC_TAMPER_ERASE_MODE(__MODE__)             (((__MODE__) == RTC_TAMPER_ERASE_BACKUP_ENABLE) || \

+                                                        ((__MODE__) == RTC_TAMPER_ERASE_BACKUP_DISABLE))

+

+#define IS_RTC_TAMPER_MASKFLAG_STATE(__STATE__)        (((__STATE__) == RTC_TAMPERMASK_FLAG_ENABLE) || \

+                                                        ((__STATE__) == RTC_TAMPERMASK_FLAG_DISABLE))

+

+#define IS_RTC_TAMPER_FILTER(__FILTER__)  (((__FILTER__) == RTC_TAMPERFILTER_DISABLE) || \

+                                           ((__FILTER__) == RTC_TAMPERFILTER_2SAMPLE) || \

+                                           ((__FILTER__) == RTC_TAMPERFILTER_4SAMPLE) || \

+                                           ((__FILTER__) == RTC_TAMPERFILTER_8SAMPLE))

+

+#define IS_RTC_TAMPER_SAMPLING_FREQ(__FREQ__) (((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \

+                                               ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \

+                                               ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \

+                                               ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \

+                                               ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \

+                                               ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \

+                                               ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512)  || \

+                                               ((__FREQ__) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))

+

+#define IS_RTC_TAMPER_PRECHARGE_DURATION(__DURATION__) (((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \

+                                                        ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \

+                                                        ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \

+                                                        ((__DURATION__) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))

+

+#define IS_RTC_TAMPER_PULLUP_STATE(__STATE__) (((__STATE__) == RTC_TAMPER_PULLUP_ENABLE) || \

+                                               ((__STATE__) == RTC_TAMPER_PULLUP_DISABLE))

+

+#define IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION(__DETECTION__) (((__DETECTION__) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \

+                                                                  ((__DETECTION__) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))

+

+#if defined(RTC_CR_TAMPOE)

+#define IS_RTC_TAMPER_TAMPERDETECTIONOUTPUT(__MODE__) (((__MODE__) == RTC_TAMPERDETECTIONOUTPUT_ENABLE) || \

+                                                       ((__MODE__) == RTC_TAMPERDETECTIONOUTPUT_DISABLE))

+#endif /* RTC_CR_TAMPOE */

+

+#define IS_RTC_TAMPER_FILTER_CONFIG_CORRECT(FILTER, TRIGGER)            \

+                  (  (  ((FILTER) != RTC_TAMPERFILTER_DISABLE)          \

+                     && (  ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL)    \

+                        || ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL))) \

+                  || (  ((FILTER) == RTC_TAMPERFILTER_DISABLE)          \

+                     && (  ((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE)  \

+                        || ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE))))

+

+#define IS_RTC_INTERNAL_TAMPER(__INT_TAMPER__)   ((((__INT_TAMPER__) &  RTC_INT_TAMPER_ALL) != 0x00U) && \

+                                                  (((__INT_TAMPER__) & ~RTC_INT_TAMPER_ALL) == 0x00U))

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif /* __cplusplus */

+

+#endif /* STM32H7xx_HAL_RTC_EX_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_sai.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_sai.h
new file mode 100644
index 0000000000..a8dd6d5680
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_sai.h
@@ -0,0 +1,983 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_sai.h

+  * @author  MCD Application Team

+  * @brief   Header file of SAI HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_SAI_H

+#define STM32H7xx_HAL_SAI_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup SAI

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup SAI_Exported_Types SAI Exported Types

+  * @{

+  */

+

+/**

+  * @brief  HAL State structures definition

+  */

+typedef enum

+{

+  HAL_SAI_STATE_RESET   = 0x00U, /*!< SAI not yet initialized or disabled  */

+  HAL_SAI_STATE_READY   = 0x01U, /*!< SAI initialized and ready for use    */

+  HAL_SAI_STATE_BUSY    = 0x02U, /*!< SAI internal process is ongoing      */

+  HAL_SAI_STATE_BUSY_TX = 0x12U, /*!< Data transmission process is ongoing */

+  HAL_SAI_STATE_BUSY_RX = 0x22U, /*!< Data reception process is ongoing    */

+} HAL_SAI_StateTypeDef;

+

+/**

+  * @brief  SAI Callback prototype

+  */

+typedef void (*SAIcallback)(void);

+

+/** @defgroup SAI_PDM_Structure_definition SAI PDM Structure definition

+  * @brief  SAI PDM Init structure definition

+  * @{

+  */

+typedef struct

+{

+  FunctionalState  Activation;  /*!< Enable/disable PDM interface */

+  uint32_t         MicPairsNbr; /*!< Specifies the number of microphone pairs used.

+                                     This parameter must be a number between Min_Data = 1 and Max_Data = 3. */

+  uint32_t         ClockEnable; /*!< Specifies which clock must be enabled.

+                                     This parameter can be a values combination of @ref SAI_PDM_ClockEnable */

+} SAI_PdmInitTypeDef;

+/**

+  * @}

+  */

+

+/** @defgroup SAI_Init_Structure_definition SAI Init Structure definition

+  * @brief  SAI Init Structure definition

+  * @{

+  */

+typedef struct

+{

+  uint32_t AudioMode;           /*!< Specifies the SAI Block audio Mode.

+                                     This parameter can be a value of @ref SAI_Block_Mode */

+

+  uint32_t Synchro;             /*!< Specifies SAI Block synchronization

+                                     This parameter can be a value of @ref SAI_Block_Synchronization */

+

+  uint32_t SynchroExt;          /*!< Specifies SAI external output synchronization, this setup is common

+                                     for BlockA and BlockB

+                                     This parameter can be a value of @ref SAI_Block_SyncExt

+                                     @note If both audio blocks of same SAI are used, this parameter has

+                                           to be set to the same value for each audio block */

+

+  uint32_t MckOutput;           /*!< Specifies whether master clock output will be generated or not.

+                                     This parameter can be a value of @ref SAI_Block_MckOutput

+                                     @note This feature is only available on STM32H7xx Rev.B and above */

+

+  uint32_t OutputDrive;         /*!< Specifies when SAI Block outputs are driven.

+                                     This parameter can be a value of @ref SAI_Block_Output_Drive

+                                     @note This value has to be set before enabling the audio block

+                                           but after the audio block configuration. */

+

+  uint32_t NoDivider;           /*!< Specifies whether master clock will be divided or not.

+                                     This parameter can be a value of @ref SAI_Block_NoDivider

+                                     @note If bit NODIV in the SAI_xCR1 register is cleared, the frame length

+                                           should be aligned to a number equal to a power of 2, from 8 to 256.

+                                           If bit NODIV in the SAI_xCR1 register is set, the frame length can

+                                           take any of the values from 8 to 256.

+                                     @note The NODIV bit is the same as NOMCK bit in STM32H7xx rev.Y */

+

+  uint32_t FIFOThreshold;       /*!< Specifies SAI Block FIFO threshold.

+                                     This parameter can be a value of @ref SAI_Block_Fifo_Threshold */

+

+  uint32_t AudioFrequency;      /*!< Specifies the audio frequency sampling.

+                                     This parameter can be a value of @ref SAI_Audio_Frequency */

+

+  uint32_t Mckdiv;              /*!< Specifies the master clock divider, the parameter will be used if for

+                                     AudioFrequency the user choice

+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 63. */

+

+  uint32_t MckOverSampling;     /*!< Specifies the master clock oversampling.

+                                     This parameter can be a value of @ref SAI_Block_Mck_OverSampling */

+

+  uint32_t MonoStereoMode;      /*!< Specifies if the mono or stereo mode is selected.

+                                     This parameter can be a value of @ref SAI_Mono_Stereo_Mode */

+

+  uint32_t CompandingMode;      /*!< Specifies the companding mode type.

+                                     This parameter can be a value of @ref SAI_Block_Companding_Mode */

+

+  uint32_t TriState;            /*!< Specifies the companding mode type.

+                                     This parameter can be a value of @ref SAI_TRIState_Management */

+

+  SAI_PdmInitTypeDef PdmInit;   /*!< Specifies the PDM configuration. */

+

+  /* This part of the structure is automatically filled if your are using the high level initialisation

+     function HAL_SAI_InitProtocol */

+

+  uint32_t Protocol;        /*!< Specifies the SAI Block protocol.

+                                 This parameter can be a value of @ref SAI_Block_Protocol */

+

+  uint32_t DataSize;        /*!< Specifies the SAI Block data size.

+                                 This parameter can be a value of @ref SAI_Block_Data_Size */

+

+  uint32_t FirstBit;        /*!< Specifies whether data transfers start from MSB or LSB bit.

+                                 This parameter can be a value of @ref SAI_Block_MSB_LSB_transmission */

+

+  uint32_t ClockStrobing;   /*!< Specifies the SAI Block clock strobing edge sensitivity.

+                                 This parameter can be a value of @ref SAI_Block_Clock_Strobing */

+} SAI_InitTypeDef;

+/**

+  * @}

+  */

+

+/** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition

+  * @brief  SAI Frame Init structure definition

+  * @{

+  */

+typedef struct

+{

+

+  uint32_t FrameLength;        /*!< Specifies the Frame length, the number of SCK clocks for each audio frame.

+                                    This parameter must be a number between Min_Data = 8 and Max_Data = 256.

+                                    @note If master clock MCLK_x pin is declared as an output, the frame length

+                                          should be aligned to a number equal to power of 2 in order to keep

+                                          in an audio frame, an integer number of MCLK pulses by bit Clock. */

+

+  uint32_t ActiveFrameLength;  /*!< Specifies the Frame synchronization active level length.

+                                    This Parameter specifies the length in number of bit clock (SCK + 1)

+                                    of the active level of FS signal in audio frame.

+                                    This parameter must be a number between Min_Data = 1 and Max_Data = 128 */

+

+  uint32_t FSDefinition;       /*!< Specifies the Frame synchronization definition.

+                                    This parameter can be a value of @ref SAI_Block_FS_Definition */

+

+  uint32_t FSPolarity;         /*!< Specifies the Frame synchronization Polarity.

+                                    This parameter can be a value of @ref SAI_Block_FS_Polarity */

+

+  uint32_t FSOffset;           /*!< Specifies the Frame synchronization Offset.

+                                    This parameter can be a value of @ref SAI_Block_FS_Offset */

+

+} SAI_FrameInitTypeDef;

+/**

+  * @}

+  */

+

+/** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition

+  * @brief   SAI Block Slot Init Structure definition

+  * @{

+  */

+typedef struct

+{

+  uint32_t FirstBitOffset;  /*!< Specifies the position of first data transfer bit in the slot.

+                                 This parameter must be a number between Min_Data = 0 and Max_Data = 24 */

+

+  uint32_t SlotSize;        /*!< Specifies the Slot Size.

+                                 This parameter can be a value of @ref SAI_Block_Slot_Size */

+

+  uint32_t SlotNumber;      /*!< Specifies the number of slot in the audio frame.

+                                 This parameter must be a number between Min_Data = 1 and Max_Data = 16 */

+

+  uint32_t SlotActive;      /*!< Specifies the slots in audio frame that will be activated.

+                                 This parameter can be a value of @ref SAI_Block_Slot_Active */

+} SAI_SlotInitTypeDef;

+/**

+  * @}

+  */

+

+/** @defgroup SAI_Handle_Structure_definition SAI Handle Structure definition

+  * @brief  SAI handle Structure definition

+  * @{

+  */

+typedef struct __SAI_HandleTypeDef

+{

+  SAI_Block_TypeDef         *Instance;    /*!< SAI Blockx registers base address */

+

+  SAI_InitTypeDef           Init;         /*!< SAI communication parameters */

+

+  SAI_FrameInitTypeDef      FrameInit;    /*!< SAI Frame configuration parameters */

+

+  SAI_SlotInitTypeDef       SlotInit;     /*!< SAI Slot configuration parameters */

+

+  uint8_t                  *pBuffPtr;     /*!< Pointer to SAI transfer Buffer */

+

+  uint16_t                  XferSize;     /*!< SAI transfer size */

+

+  uint16_t                  XferCount;    /*!< SAI transfer counter */

+

+  DMA_HandleTypeDef         *hdmatx;      /*!< SAI Tx DMA handle parameters */

+

+  DMA_HandleTypeDef         *hdmarx;      /*!< SAI Rx DMA handle parameters */

+

+  SAIcallback               mutecallback; /*!< SAI mute callback */

+

+  void (*InterruptServiceRoutine)(struct __SAI_HandleTypeDef *hsai); /* function pointer for IRQ handler */

+

+  HAL_LockTypeDef           Lock;         /*!< SAI locking object */

+

+  __IO HAL_SAI_StateTypeDef State;        /*!< SAI communication state */

+

+  __IO uint32_t             ErrorCode;    /*!< SAI Error code */

+

+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)

+  void (*RxCpltCallback)(struct __SAI_HandleTypeDef *hsai);      /*!< SAI receive complete callback */

+  void (*RxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai);  /*!< SAI receive half complete callback */

+  void (*TxCpltCallback)(struct __SAI_HandleTypeDef *hsai);      /*!< SAI transmit complete callback */

+  void (*TxHalfCpltCallback)(struct __SAI_HandleTypeDef *hsai);  /*!< SAI transmit half complete callback */

+  void (*ErrorCallback)(struct __SAI_HandleTypeDef *hsai);       /*!< SAI error callback */

+  void (*MspInitCallback)(struct __SAI_HandleTypeDef *hsai);     /*!< SAI MSP init callback */

+  void (*MspDeInitCallback)(struct __SAI_HandleTypeDef *hsai);   /*!< SAI MSP de-init callback */

+#endif

+} SAI_HandleTypeDef;

+/**

+  * @}

+  */

+

+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  SAI callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_SAI_RX_COMPLETE_CB_ID       = 0x00U, /*!< SAI receive complete callback ID */

+  HAL_SAI_RX_HALFCOMPLETE_CB_ID   = 0x01U, /*!< SAI receive half complete callback ID */

+  HAL_SAI_TX_COMPLETE_CB_ID       = 0x02U, /*!< SAI transmit complete callback ID */

+  HAL_SAI_TX_HALFCOMPLETE_CB_ID   = 0x03U, /*!< SAI transmit half complete callback ID */

+  HAL_SAI_ERROR_CB_ID             = 0x04U, /*!< SAI error callback ID */

+  HAL_SAI_MSPINIT_CB_ID           = 0x05U, /*!< SAI MSP init callback ID */

+  HAL_SAI_MSPDEINIT_CB_ID         = 0x06U  /*!< SAI MSP de-init callback ID */

+} HAL_SAI_CallbackIDTypeDef;

+

+/**

+  * @brief  SAI callback pointer definition

+  */

+typedef void (*pSAI_CallbackTypeDef)(SAI_HandleTypeDef *hsai);

+#endif

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup SAI_Exported_Constants SAI Exported Constants

+  * @{

+  */

+

+/** @defgroup SAI_Error_Code SAI Error Code

+  * @{

+  */

+#define HAL_SAI_ERROR_NONE          0x00000000U  /*!< No error */

+#define HAL_SAI_ERROR_OVR           0x00000001U  /*!< Overrun Error */

+#define HAL_SAI_ERROR_UDR           0x00000002U  /*!< Underrun error */

+#define HAL_SAI_ERROR_AFSDET        0x00000004U  /*!< Anticipated Frame synchronisation detection */

+#define HAL_SAI_ERROR_LFSDET        0x00000008U  /*!< Late Frame synchronisation detection */

+#define HAL_SAI_ERROR_CNREADY       0x00000010U  /*!< codec not ready */

+#define HAL_SAI_ERROR_WCKCFG        0x00000020U  /*!< Wrong clock configuration */

+#define HAL_SAI_ERROR_TIMEOUT       0x00000040U  /*!< Timeout error */

+#define HAL_SAI_ERROR_DMA           0x00000080U  /*!< DMA error */

+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)

+#define HAL_SAI_ERROR_INVALID_CALLBACK   0x00000100U  /*!< Invalid callback error */

+#endif

+/**

+  * @}

+  */

+

+/** @defgroup SAI_Block_SyncExt SAI External synchronisation

+  * @{

+  */

+#define SAI_SYNCEXT_DISABLE           0U

+#define SAI_SYNCEXT_OUTBLOCKA_ENABLE  1U

+#define SAI_SYNCEXT_OUTBLOCKB_ENABLE  2U

+/**

+  * @}

+  */

+

+/** @defgroup SAI_Block_MckOutput SAI Block Master Clock Output

+  * @{

+  */

+#define SAI_MCK_OUTPUT_DISABLE      0x00000000U

+#define SAI_MCK_OUTPUT_ENABLE       SAI_xCR1_MCKEN

+/**

+  * @}

+  */

+

+/** @defgroup SAI_Protocol SAI Supported protocol

+  * @{

+  */

+#define SAI_I2S_STANDARD         0U

+#define SAI_I2S_MSBJUSTIFIED     1U

+#define SAI_I2S_LSBJUSTIFIED     2U

+#define SAI_PCM_LONG             3U

+#define SAI_PCM_SHORT            4U

+/**

+  * @}

+  */

+

+/** @defgroup SAI_Protocol_DataSize SAI protocol data size

+  * @{

+  */

+#define SAI_PROTOCOL_DATASIZE_16BIT         0U

+#define SAI_PROTOCOL_DATASIZE_16BITEXTENDED 1U

+#define SAI_PROTOCOL_DATASIZE_24BIT         2U

+#define SAI_PROTOCOL_DATASIZE_32BIT         3U

+/**

+  * @}

+  */

+

+/** @defgroup SAI_Audio_Frequency SAI Audio Frequency

+  * @{

+  */

+#define SAI_AUDIO_FREQUENCY_192K      192000U

+#define SAI_AUDIO_FREQUENCY_96K        96000U

+#define SAI_AUDIO_FREQUENCY_48K        48000U

+#define SAI_AUDIO_FREQUENCY_44K        44100U

+#define SAI_AUDIO_FREQUENCY_32K        32000U

+#define SAI_AUDIO_FREQUENCY_22K        22050U

+#define SAI_AUDIO_FREQUENCY_16K        16000U

+#define SAI_AUDIO_FREQUENCY_11K        11025U

+#define SAI_AUDIO_FREQUENCY_8K          8000U

+#define SAI_AUDIO_FREQUENCY_MCKDIV         0U

+/**

+  * @}

+  */

+

+/** @defgroup SAI_Block_Mck_OverSampling SAI Block Master Clock OverSampling

+  * @{

+  */

+#define SAI_MCK_OVERSAMPLING_DISABLE  0x00000000U

+#define SAI_MCK_OVERSAMPLING_ENABLE   SAI_xCR1_OSR

+/**

+  * @}

+  */

+

+/** @defgroup SAI_PDM_ClockEnable SAI PDM Clock Enable

+  * @{

+  */

+#define SAI_PDM_CLOCK1_ENABLE         SAI_PDMCR_CKEN1

+#define SAI_PDM_CLOCK2_ENABLE         SAI_PDMCR_CKEN2

+/**

+  * @}

+  */

+

+/** @defgroup SAI_Block_Mode SAI Block Mode

+  * @{

+  */

+#define SAI_MODEMASTER_TX             0x00000000U

+#define SAI_MODEMASTER_RX             SAI_xCR1_MODE_0

+#define SAI_MODESLAVE_TX              SAI_xCR1_MODE_1

+#define SAI_MODESLAVE_RX              (SAI_xCR1_MODE_1 | SAI_xCR1_MODE_0)

+

+/**

+  * @}

+  */

+

+/** @defgroup SAI_Block_Protocol SAI Block Protocol

+  * @{

+  */

+#define SAI_FREE_PROTOCOL             0x00000000U

+#define SAI_SPDIF_PROTOCOL            SAI_xCR1_PRTCFG_0

+#define SAI_AC97_PROTOCOL             SAI_xCR1_PRTCFG_1

+/**

+  * @}

+  */

+

+/** @defgroup SAI_Block_Data_Size SAI Block Data Size

+  * @{

+  */

+#define SAI_DATASIZE_8                SAI_xCR1_DS_1

+#define SAI_DATASIZE_10               (SAI_xCR1_DS_1 | SAI_xCR1_DS_0)

+#define SAI_DATASIZE_16               SAI_xCR1_DS_2

+#define SAI_DATASIZE_20               (SAI_xCR1_DS_2 | SAI_xCR1_DS_0)

+#define SAI_DATASIZE_24               (SAI_xCR1_DS_2 | SAI_xCR1_DS_1)

+#define SAI_DATASIZE_32               (SAI_xCR1_DS_2 | SAI_xCR1_DS_1 | SAI_xCR1_DS_0)

+/**

+  * @}

+  */

+

+/** @defgroup SAI_Block_MSB_LSB_transmission SAI Block MSB LSB transmission

+  * @{

+  */

+#define SAI_FIRSTBIT_MSB              0x00000000U

+#define SAI_FIRSTBIT_LSB              SAI_xCR1_LSBFIRST

+/**

+  * @}

+  */

+

+/** @defgroup SAI_Block_Clock_Strobing SAI Block Clock Strobing

+  * @{

+  */

+#define SAI_CLOCKSTROBING_FALLINGEDGE  0U

+#define SAI_CLOCKSTROBING_RISINGEDGE   1U

+/**

+  * @}

+  */

+

+/** @defgroup SAI_Block_Synchronization SAI Block Synchronization

+  * @{

+  */

+#define SAI_ASYNCHRONOUS                  0U /*!< Asynchronous */

+#define SAI_SYNCHRONOUS                   1U /*!< Synchronous with other block of same SAI */

+#define SAI_SYNCHRONOUS_EXT_SAI1          2U /*!< Synchronous with other SAI, SAI1 */

+#if defined(SAI2)

+#define SAI_SYNCHRONOUS_EXT_SAI2          3U /*!< Synchronous with other SAI, SAI2 */

+#endif /* SAI2 */

+#if defined(SAI3)

+#define SAI_SYNCHRONOUS_EXT_SAI3          4U /*!< Synchronous with other SAI, SAI3 */

+#endif /* SAI3 */

+#if defined(SAI4)

+#define SAI_SYNCHRONOUS_EXT_SAI4          5U /*!< Synchronous with other SAI, SAI4 */

+#endif /* SAI4 */

+/**

+  * @}

+  */

+

+/** @defgroup SAI_Block_Output_Drive SAI Block Output Drive

+  * @{

+  */

+#define SAI_OUTPUTDRIVE_DISABLE     0x00000000U

+#define SAI_OUTPUTDRIVE_ENABLE      SAI_xCR1_OUTDRIV

+/**

+  * @}

+  */

+

+/** @defgroup SAI_Block_NoDivider SAI Block NoDivider

+  * @{

+  */

+#define SAI_MASTERDIVIDER_ENABLE    0x00000000U

+#define SAI_MASTERDIVIDER_DISABLE   SAI_xCR1_NODIV

+/**

+  * @}

+  */

+

+/** @defgroup SAI_Block_FS_Definition SAI Block FS Definition

+  * @{

+  */

+#define SAI_FS_STARTFRAME               0x00000000U

+#define SAI_FS_CHANNEL_IDENTIFICATION   SAI_xFRCR_FSDEF

+/**

+  * @}

+  */

+

+/** @defgroup SAI_Block_FS_Polarity SAI Block FS Polarity

+  * @{

+  */

+#define SAI_FS_ACTIVE_LOW           0x00000000U

+#define SAI_FS_ACTIVE_HIGH          SAI_xFRCR_FSPOL

+/**

+  * @}

+  */

+

+/** @defgroup SAI_Block_FS_Offset SAI Block FS Offset

+  * @{

+  */

+#define SAI_FS_FIRSTBIT             0x00000000U

+#define SAI_FS_BEFOREFIRSTBIT       SAI_xFRCR_FSOFF

+/**

+  * @}

+  */

+

+/** @defgroup SAI_Block_Slot_Size SAI Block Slot Size

+  * @{

+  */

+#define SAI_SLOTSIZE_DATASIZE       0x00000000U

+#define SAI_SLOTSIZE_16B            SAI_xSLOTR_SLOTSZ_0

+#define SAI_SLOTSIZE_32B            SAI_xSLOTR_SLOTSZ_1

+/**

+  * @}

+  */

+

+/** @defgroup SAI_Block_Slot_Active SAI Block Slot Active

+  * @{

+  */

+#define SAI_SLOT_NOTACTIVE          0x00000000U

+#define SAI_SLOTACTIVE_0            0x00000001U

+#define SAI_SLOTACTIVE_1            0x00000002U

+#define SAI_SLOTACTIVE_2            0x00000004U

+#define SAI_SLOTACTIVE_3            0x00000008U

+#define SAI_SLOTACTIVE_4            0x00000010U

+#define SAI_SLOTACTIVE_5            0x00000020U

+#define SAI_SLOTACTIVE_6            0x00000040U

+#define SAI_SLOTACTIVE_7            0x00000080U

+#define SAI_SLOTACTIVE_8            0x00000100U

+#define SAI_SLOTACTIVE_9            0x00000200U

+#define SAI_SLOTACTIVE_10           0x00000400U

+#define SAI_SLOTACTIVE_11           0x00000800U

+#define SAI_SLOTACTIVE_12           0x00001000U

+#define SAI_SLOTACTIVE_13           0x00002000U

+#define SAI_SLOTACTIVE_14           0x00004000U

+#define SAI_SLOTACTIVE_15           0x00008000U

+#define SAI_SLOTACTIVE_ALL          0x0000FFFFU

+/**

+  * @}

+  */

+

+/** @defgroup SAI_Mono_Stereo_Mode SAI Mono Stereo Mode

+  * @{

+  */

+#define SAI_STEREOMODE              0x00000000U

+#define SAI_MONOMODE                SAI_xCR1_MONO

+/**

+  * @}

+  */

+

+/** @defgroup SAI_TRIState_Management SAI TRIState Management

+  * @{

+  */

+#define SAI_OUTPUT_NOTRELEASED      0x00000000U

+#define SAI_OUTPUT_RELEASED         SAI_xCR2_TRIS

+/**

+  * @}

+  */

+

+/** @defgroup SAI_Block_Fifo_Threshold SAI Block Fifo Threshold

+  * @{

+  */

+#define SAI_FIFOTHRESHOLD_EMPTY     0x00000000U

+#define SAI_FIFOTHRESHOLD_1QF       SAI_xCR2_FTH_0

+#define SAI_FIFOTHRESHOLD_HF        SAI_xCR2_FTH_1

+#define SAI_FIFOTHRESHOLD_3QF       (SAI_xCR2_FTH_1 | SAI_xCR2_FTH_0)

+#define SAI_FIFOTHRESHOLD_FULL      SAI_xCR2_FTH_2

+/**

+  * @}

+  */

+

+/** @defgroup SAI_Block_Companding_Mode SAI Block Companding Mode

+  * @{

+  */

+#define SAI_NOCOMPANDING            0x00000000U

+#define SAI_ULAW_1CPL_COMPANDING    SAI_xCR2_COMP_1

+#define SAI_ALAW_1CPL_COMPANDING    (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0)

+#define SAI_ULAW_2CPL_COMPANDING    (SAI_xCR2_COMP_1 | SAI_xCR2_CPL)

+#define SAI_ALAW_2CPL_COMPANDING    (SAI_xCR2_COMP_1 | SAI_xCR2_COMP_0 | SAI_xCR2_CPL)

+/**

+  * @}

+  */

+

+/** @defgroup SAI_Block_Mute_Value SAI Block Mute Value

+  * @{

+  */

+#define SAI_ZERO_VALUE              0x00000000U

+#define SAI_LAST_SENT_VALUE         SAI_xCR2_MUTEVAL

+/**

+  * @}

+  */

+

+/** @defgroup SAI_Block_Interrupts_Definition SAI Block Interrupts Definition

+  * @{

+  */

+#define SAI_IT_OVRUDR               SAI_xIMR_OVRUDRIE

+#define SAI_IT_MUTEDET              SAI_xIMR_MUTEDETIE

+#define SAI_IT_WCKCFG               SAI_xIMR_WCKCFGIE

+#define SAI_IT_FREQ                 SAI_xIMR_FREQIE

+#define SAI_IT_CNRDY                SAI_xIMR_CNRDYIE

+#define SAI_IT_AFSDET               SAI_xIMR_AFSDETIE

+#define SAI_IT_LFSDET               SAI_xIMR_LFSDETIE

+/**

+  * @}

+  */

+

+/** @defgroup SAI_Block_Flags_Definition  SAI Block Flags Definition

+  * @{

+  */

+#define SAI_FLAG_OVRUDR             SAI_xSR_OVRUDR

+#define SAI_FLAG_MUTEDET            SAI_xSR_MUTEDET

+#define SAI_FLAG_WCKCFG             SAI_xSR_WCKCFG

+#define SAI_FLAG_FREQ               SAI_xSR_FREQ

+#define SAI_FLAG_CNRDY              SAI_xSR_CNRDY

+#define SAI_FLAG_AFSDET             SAI_xSR_AFSDET

+#define SAI_FLAG_LFSDET             SAI_xSR_LFSDET

+/**

+  * @}

+  */

+

+/** @defgroup SAI_Block_Fifo_Status_Level   SAI Block Fifo Status Level

+  * @{

+  */

+#define SAI_FIFOSTATUS_EMPTY              0x00000000U

+#define SAI_FIFOSTATUS_LESS1QUARTERFULL   0x00010000U

+#define SAI_FIFOSTATUS_1QUARTERFULL       0x00020000U

+#define SAI_FIFOSTATUS_HALFFULL           0x00030000U

+#define SAI_FIFOSTATUS_3QUARTERFULL       0x00040000U

+#define SAI_FIFOSTATUS_FULL               0x00050000U

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup SAI_Exported_Macros SAI Exported Macros

+  * @brief macros to handle interrupts and specific configurations

+  * @{

+  */

+

+/** @brief Reset SAI handle state.

+  * @param  __HANDLE__ specifies the SAI Handle.

+  * @retval None

+  */

+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)

+#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) do{                                            \

+                                                     (__HANDLE__)->State = HAL_SAI_STATE_RESET; \

+                                                     (__HANDLE__)->MspInitCallback = NULL;      \

+                                                     (__HANDLE__)->MspDeInitCallback = NULL;    \

+                                                   } while(0U)

+#else

+#define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET)

+#endif

+

+/** @brief  Enable the specified SAI interrupts.

+  * @param  __HANDLE__ specifies the SAI Handle.

+  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.

+  *         This parameter can be one of the following values:

+  *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable

+  *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable

+  *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable

+  *            @arg SAI_IT_FREQ: FIFO request interrupt enable

+  *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable

+  *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable

+  *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable

+  * @retval None

+  */

+#define __HAL_SAI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))

+

+/** @brief  Disable the specified SAI interrupts.

+  * @param  __HANDLE__ specifies the SAI Handle.

+  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.

+  *         This parameter can be one of the following values:

+  *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable

+  *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable

+  *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable

+  *            @arg SAI_IT_FREQ: FIFO request interrupt enable

+  *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable

+  *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable

+  *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable

+  * @retval None

+  */

+#define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__)))

+

+/** @brief  Check whether the specified SAI interrupt source is enabled or not.

+  * @param  __HANDLE__ specifies the SAI Handle.

+  * @param  __INTERRUPT__ specifies the SAI interrupt source to check.

+  *         This parameter can be one of the following values:

+  *            @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable

+  *            @arg SAI_IT_MUTEDET: Mute detection interrupt enable

+  *            @arg SAI_IT_WCKCFG: Wrong Clock Configuration interrupt enable

+  *            @arg SAI_IT_FREQ: FIFO request interrupt enable

+  *            @arg SAI_IT_CNRDY: Codec not ready interrupt enable

+  *            @arg SAI_IT_AFSDET: Anticipated frame synchronization detection interrupt enable

+  *            @arg SAI_IT_LFSDET: Late frame synchronization detection interrupt enable

+  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).

+  */

+#define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

+

+/** @brief  Check whether the specified SAI flag is set or not.

+  * @param  __HANDLE__ specifies the SAI Handle.

+  * @param  __FLAG__ specifies the flag to check.

+  *         This parameter can be one of the following values:

+  *            @arg SAI_FLAG_OVRUDR: Overrun underrun flag.

+  *            @arg SAI_FLAG_MUTEDET: Mute detection flag.

+  *            @arg SAI_FLAG_WCKCFG: Wrong Clock Configuration flag.

+  *            @arg SAI_FLAG_FREQ: FIFO request flag.

+  *            @arg SAI_FLAG_CNRDY: Codec not ready flag.

+  *            @arg SAI_FLAG_AFSDET: Anticipated frame synchronization detection flag.

+  *            @arg SAI_FLAG_LFSDET: Late frame synchronization detection flag.

+  * @retval The new state of __FLAG__ (TRUE or FALSE).

+  */

+#define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

+

+/** @brief  Clear the specified SAI pending flag.

+  * @param  __HANDLE__ specifies the SAI Handle.

+  * @param  __FLAG__ specifies the flag to check.

+  *          This parameter can be any combination of the following values:

+  *            @arg SAI_FLAG_OVRUDR: Clear Overrun underrun

+  *            @arg SAI_FLAG_MUTEDET: Clear Mute detection

+  *            @arg SAI_FLAG_WCKCFG: Clear Wrong Clock Configuration

+  *            @arg SAI_FLAG_FREQ: Clear FIFO request

+  *            @arg SAI_FLAG_CNRDY: Clear Codec not ready

+  *            @arg SAI_FLAG_AFSDET: Clear Anticipated frame synchronization detection

+  *            @arg SAI_FLAG_LFSDET: Clear Late frame synchronization detection

+  *

+  * @retval None

+  */

+#define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__))

+

+/** @brief  Enable SAI.

+  * @param  __HANDLE__ specifies the SAI Handle.

+  * @retval None

+  */

+#define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SAI_xCR1_SAIEN)

+

+/** @brief  Disable SAI.

+  * @param  __HANDLE__ specifies the SAI Handle.

+  * @retval None

+  */

+#define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &=  ~SAI_xCR1_SAIEN)

+

+/**

+  * @}

+  */

+

+/* Include SAI HAL Extension module */

+#include "stm32h7xx_hal_sai_ex.h"

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup SAI_Exported_Functions

+  * @{

+  */

+

+/* Initialization/de-initialization functions  ********************************/

+/** @addtogroup SAI_Exported_Functions_Group1

+  * @{

+  */

+HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot);

+HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai);

+HAL_StatusTypeDef HAL_SAI_DeInit(SAI_HandleTypeDef *hsai);

+void HAL_SAI_MspInit(SAI_HandleTypeDef *hsai);

+void HAL_SAI_MspDeInit(SAI_HandleTypeDef *hsai);

+

+#if (USE_HAL_SAI_REGISTER_CALLBACKS == 1)

+/* SAI callbacks register/unregister functions ********************************/

+HAL_StatusTypeDef HAL_SAI_RegisterCallback(SAI_HandleTypeDef        *hsai,

+                                           HAL_SAI_CallbackIDTypeDef CallbackID,

+                                           pSAI_CallbackTypeDef      pCallback);

+HAL_StatusTypeDef HAL_SAI_UnRegisterCallback(SAI_HandleTypeDef        *hsai,

+                                             HAL_SAI_CallbackIDTypeDef CallbackID);

+#endif

+/**

+  * @}

+  */

+

+/* I/O operation functions  ***************************************************/

+/** @addtogroup SAI_Exported_Functions_Group2

+  * @{

+  */

+/* Blocking mode: Polling */

+HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);

+HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout);

+

+/* Non-Blocking mode: Interrupt */

+HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);

+

+/* Non-Blocking mode: DMA */

+HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_SAI_DMAPause(SAI_HandleTypeDef *hsai);

+HAL_StatusTypeDef HAL_SAI_DMAResume(SAI_HandleTypeDef *hsai);

+HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai);

+

+/* Abort function */

+HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai);

+

+/* Mute management */

+HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val);

+HAL_StatusTypeDef HAL_SAI_DisableTxMuteMode(SAI_HandleTypeDef *hsai);

+HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter);

+HAL_StatusTypeDef HAL_SAI_DisableRxMuteMode(SAI_HandleTypeDef *hsai);

+

+/* SAI IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */

+void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai);

+void HAL_SAI_TxHalfCpltCallback(SAI_HandleTypeDef *hsai);

+void HAL_SAI_TxCpltCallback(SAI_HandleTypeDef *hsai);

+void HAL_SAI_RxHalfCpltCallback(SAI_HandleTypeDef *hsai);

+void HAL_SAI_RxCpltCallback(SAI_HandleTypeDef *hsai);

+void HAL_SAI_ErrorCallback(SAI_HandleTypeDef *hsai);

+/**

+  * @}

+  */

+

+/** @addtogroup SAI_Exported_Functions_Group3

+  * @{

+  */

+/* Peripheral State functions  ************************************************/

+HAL_SAI_StateTypeDef HAL_SAI_GetState(SAI_HandleTypeDef *hsai);

+uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @addtogroup SAI_Private_Macros

+  * @{

+  */

+#define IS_SAI_BLOCK_SYNCEXT(STATE) (((STATE) == SAI_SYNCEXT_DISABLE) ||\

+                                     ((STATE) == SAI_SYNCEXT_OUTBLOCKA_ENABLE) ||\

+                                     ((STATE) == SAI_SYNCEXT_OUTBLOCKB_ENABLE))

+

+#define IS_SAI_SUPPORTED_PROTOCOL(PROTOCOL)   (((PROTOCOL) == SAI_I2S_STANDARD)     ||\

+                                               ((PROTOCOL) == SAI_I2S_MSBJUSTIFIED) ||\

+                                               ((PROTOCOL) == SAI_I2S_LSBJUSTIFIED) ||\

+                                               ((PROTOCOL) == SAI_PCM_LONG)         ||\

+                                               ((PROTOCOL) == SAI_PCM_SHORT))

+

+#define IS_SAI_PROTOCOL_DATASIZE(DATASIZE)   (((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BIT)         ||\

+                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_16BITEXTENDED) ||\

+                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_24BIT)         ||\

+                                              ((DATASIZE) == SAI_PROTOCOL_DATASIZE_32BIT))

+

+#define IS_SAI_AUDIO_FREQUENCY(AUDIO) (((AUDIO) == SAI_AUDIO_FREQUENCY_192K) || ((AUDIO) == SAI_AUDIO_FREQUENCY_96K) || \

+                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_48K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_44K) || \

+                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_32K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_22K) || \

+                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_16K)  || ((AUDIO) == SAI_AUDIO_FREQUENCY_11K) || \

+                                       ((AUDIO) == SAI_AUDIO_FREQUENCY_8K)   || ((AUDIO) == SAI_AUDIO_FREQUENCY_MCKDIV))

+

+#define IS_SAI_BLOCK_MCK_OVERSAMPLING(VALUE) (((VALUE) == SAI_MCK_OVERSAMPLING_DISABLE) || \

+                                              ((VALUE) == SAI_MCK_OVERSAMPLING_ENABLE))

+

+#define IS_SAI_PDM_MIC_PAIRS_NUMBER(VALUE)   ((1U <= (VALUE)) && ((VALUE) <= 3U))

+

+#define IS_SAI_PDM_CLOCK_ENABLE(CLOCK) (((CLOCK) != 0U) && \

+                                       (((CLOCK) & ~(SAI_PDM_CLOCK1_ENABLE | SAI_PDM_CLOCK2_ENABLE)) == 0U))

+

+#define IS_SAI_BLOCK_MODE(MODE)  (((MODE) == SAI_MODEMASTER_TX) || \

+                                  ((MODE) == SAI_MODEMASTER_RX) || \

+                                  ((MODE) == SAI_MODESLAVE_TX)  || \

+                                  ((MODE) == SAI_MODESLAVE_RX))

+

+#define IS_SAI_BLOCK_PROTOCOL(PROTOCOL) (((PROTOCOL) == SAI_FREE_PROTOCOL)  || \

+                                         ((PROTOCOL) == SAI_AC97_PROTOCOL)  || \

+                                         ((PROTOCOL) == SAI_SPDIF_PROTOCOL))

+

+#define IS_SAI_BLOCK_DATASIZE(DATASIZE) (((DATASIZE) == SAI_DATASIZE_8)  || \

+                                         ((DATASIZE) == SAI_DATASIZE_10) || \

+                                         ((DATASIZE) == SAI_DATASIZE_16) || \

+                                         ((DATASIZE) == SAI_DATASIZE_20) || \

+                                         ((DATASIZE) == SAI_DATASIZE_24) || \

+                                         ((DATASIZE) == SAI_DATASIZE_32))

+

+#define IS_SAI_BLOCK_FIRST_BIT(BIT) (((BIT) == SAI_FIRSTBIT_MSB) || \

+                                     ((BIT) == SAI_FIRSTBIT_LSB))

+

+#define IS_SAI_BLOCK_CLOCK_STROBING(CLOCK) (((CLOCK) == SAI_CLOCKSTROBING_FALLINGEDGE) || \

+                                            ((CLOCK) == SAI_CLOCKSTROBING_RISINGEDGE))

+#if defined(SAI2) && defined(SAI3) && defined(SAI4)

+#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS)          || \

+                                       ((SYNCHRO) == SAI_SYNCHRONOUS)           || \

+                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1)  || \

+                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2)  || \

+                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI3)  || \

+                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI4))

+#elif defined(SAI2)

+#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS)          || \

+                                       ((SYNCHRO) == SAI_SYNCHRONOUS)           || \

+                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1)  || \

+                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI2))

+#else

+#define IS_SAI_BLOCK_SYNCHRO(SYNCHRO) (((SYNCHRO) == SAI_ASYNCHRONOUS)          || \

+                                       ((SYNCHRO) == SAI_SYNCHRONOUS)           || \

+                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI1)  || \

+                                       ((SYNCHRO) == SAI_SYNCHRONOUS_EXT_SAI4))

+#endif

+

+#define IS_SAI_BLOCK_MCK_OUTPUT(VALUE) (((VALUE) == SAI_MCK_OUTPUT_ENABLE) || \

+                                        ((VALUE) == SAI_MCK_OUTPUT_DISABLE))

+

+#define IS_SAI_BLOCK_OUTPUT_DRIVE(DRIVE) (((DRIVE) == SAI_OUTPUTDRIVE_DISABLE) || \

+                                          ((DRIVE) == SAI_OUTPUTDRIVE_ENABLE))

+

+#define IS_SAI_BLOCK_NODIVIDER(NODIVIDER) (((NODIVIDER) == SAI_MASTERDIVIDER_ENABLE) || \

+                                           ((NODIVIDER) == SAI_MASTERDIVIDER_DISABLE))

+

+#define IS_SAI_BLOCK_MUTE_COUNTER(COUNTER) ((COUNTER) <= 63U)

+

+#define IS_SAI_BLOCK_MUTE_VALUE(VALUE)    (((VALUE) == SAI_ZERO_VALUE)     || \

+                                           ((VALUE) == SAI_LAST_SENT_VALUE))

+

+#define IS_SAI_BLOCK_COMPANDING_MODE(MODE)    (((MODE) == SAI_NOCOMPANDING)         || \

+                                               ((MODE) == SAI_ULAW_1CPL_COMPANDING) || \

+                                               ((MODE) == SAI_ALAW_1CPL_COMPANDING) || \

+                                               ((MODE) == SAI_ULAW_2CPL_COMPANDING) || \

+                                               ((MODE) == SAI_ALAW_2CPL_COMPANDING))

+

+#define IS_SAI_BLOCK_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == SAI_FIFOTHRESHOLD_EMPTY)   || \

+                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_1QF)     || \

+                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_HF)      || \

+                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_3QF)     || \

+                                                ((THRESHOLD) == SAI_FIFOTHRESHOLD_FULL))

+

+#define IS_SAI_BLOCK_TRISTATE_MANAGEMENT(STATE) (((STATE) == SAI_OUTPUT_NOTRELEASED) ||\

+                                                 ((STATE) == SAI_OUTPUT_RELEASED))

+

+#define IS_SAI_MONO_STEREO_MODE(MODE) (((MODE) == SAI_MONOMODE) ||\

+                                       ((MODE) == SAI_STEREOMODE))

+

+#define IS_SAI_SLOT_ACTIVE(ACTIVE)  ((ACTIVE) <= SAI_SLOTACTIVE_ALL)

+

+#define IS_SAI_BLOCK_SLOT_NUMBER(NUMBER) ((1U <= (NUMBER)) && ((NUMBER) <= 16U))

+

+#define IS_SAI_BLOCK_SLOT_SIZE(SIZE) (((SIZE) == SAI_SLOTSIZE_DATASIZE) || \

+                                      ((SIZE) == SAI_SLOTSIZE_16B)      || \

+                                      ((SIZE) == SAI_SLOTSIZE_32B))

+

+#define IS_SAI_BLOCK_FIRSTBIT_OFFSET(OFFSET) ((OFFSET) <= 24U)

+

+#define IS_SAI_BLOCK_FS_OFFSET(OFFSET) (((OFFSET) == SAI_FS_FIRSTBIT) || \

+                                        ((OFFSET) == SAI_FS_BEFOREFIRSTBIT))

+

+#define IS_SAI_BLOCK_FS_POLARITY(POLARITY) (((POLARITY) == SAI_FS_ACTIVE_LOW) || \

+                                            ((POLARITY) == SAI_FS_ACTIVE_HIGH))

+

+#define IS_SAI_BLOCK_FS_DEFINITION(DEFINITION) (((DEFINITION) == SAI_FS_STARTFRAME) || \

+                                                ((DEFINITION) == SAI_FS_CHANNEL_IDENTIFICATION))

+

+#define IS_SAI_BLOCK_MASTER_DIVIDER(DIVIDER) ((DIVIDER) <= 63U)

+

+#define IS_SAI_BLOCK_FRAME_LENGTH(LENGTH) ((8U <= (LENGTH)) && ((LENGTH) <= 256U))

+

+#define IS_SAI_BLOCK_ACTIVE_FRAME(LENGTH) ((1U <= (LENGTH)) && ((LENGTH) <= 128U))

+

+/**

+  * @}

+  */

+

+/* Private functions ---------------------------------------------------------*/

+/** @defgroup SAI_Private_Functions SAI Private Functions

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_SAI_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_sai_ex.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_sai_ex.h
new file mode 100644
index 0000000000..40245731d1
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_sai_ex.h
@@ -0,0 +1,105 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_sai_ex.h

+  * @author  MCD Application Team

+  * @brief   Header file of SAI HAL extended module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_SAI_EX_H

+#define STM32H7xx_HAL_SAI_EX_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup SAIEx

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup SAIEx_Exported_Types SAIEx Exported Types

+  * @{

+  */

+

+/**

+  * @brief  PDM microphone delay structure definition

+  */

+typedef struct

+{

+  uint32_t MicPair;     /*!< Specifies which pair of microphones is selected.

+                             This parameter must be a number between Min_Data = 1 and Max_Data = 3. */

+

+  uint32_t LeftDelay;   /*!< Specifies the delay in PDM clock unit to apply on left microphone.

+                             This parameter must be a number between Min_Data = 0 and Max_Data = 7. */

+

+  uint32_t RightDelay;  /*!< Specifies the delay in PDM clock unit to apply on right microphone.

+                             This parameter must be a number between Min_Data = 0 and Max_Data = 7. */

+} SAIEx_PdmMicDelayParamTypeDef;

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/* Exported macros -----------------------------------------------------------*/

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup SAIEx_Exported_Functions SAIEx Extended Exported Functions

+  * @{

+  */

+

+/** @addtogroup SAIEx_Exported_Functions_Group1 Peripheral Control functions

+  * @{

+  */

+HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_PdmMicDelayParamTypeDef *pdmMicDelay);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @addtogroup SAIEx_Private_Macros SAIEx Extended Private Macros

+  * @{

+  */

+#define IS_SAI_PDM_MIC_DELAY(VALUE)   ((VALUE) <= 7U)

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_SAI_EX_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_sd.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_sd.h
new file mode 100644
index 0000000000..b69533120f
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_sd.h
@@ -0,0 +1,797 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_sd.h

+  * @author  MCD Application Team

+  * @brief   Header file of SD HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                       opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_SD_H

+#define STM32H7xx_HAL_SD_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_ll_sdmmc.h"

+#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) || defined (DLYB_SDMMC3)

+#include "stm32h7xx_ll_delayblock.h"

+#endif /* (DLYB_SDMMC1) || (DLYB_SDMMC2) */

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @defgroup SD SD

+  * @brief SD HAL module driver

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup SD_Exported_Types SD Exported Types

+  * @{

+  */

+

+/** @defgroup SD_Exported_Types_Group1 SD State enumeration structure

+  * @{

+  */

+typedef enum

+{

+  HAL_SD_STATE_RESET                  = ((uint32_t)0x00000000U),  /*!< SD not yet initialized or disabled  */

+  HAL_SD_STATE_READY                  = ((uint32_t)0x00000001U),  /*!< SD initialized and ready for use    */

+  HAL_SD_STATE_TIMEOUT                = ((uint32_t)0x00000002U),  /*!< SD Timeout state                    */

+  HAL_SD_STATE_BUSY                   = ((uint32_t)0x00000003U),  /*!< SD process ongoing                  */

+  HAL_SD_STATE_PROGRAMMING            = ((uint32_t)0x00000004U),  /*!< SD Programming State                */

+  HAL_SD_STATE_RECEIVING              = ((uint32_t)0x00000005U),  /*!< SD Receiving State                  */

+  HAL_SD_STATE_TRANSFER               = ((uint32_t)0x00000006U),  /*!< SD Transfert State                  */

+  HAL_SD_STATE_ERROR                  = ((uint32_t)0x0000000FU)   /*!< SD is in error state                */

+}HAL_SD_StateTypeDef;

+/**

+  * @}

+  */

+

+/** @defgroup SD_Exported_Types_Group2 SD Card State enumeration structure

+  * @{

+  */

+typedef uint32_t HAL_SD_CardStateTypeDef;

+

+#define HAL_SD_CARD_READY          0x00000001U  /*!< Card state is ready                     */

+#define HAL_SD_CARD_IDENTIFICATION 0x00000002U  /*!< Card is in identification state         */

+#define HAL_SD_CARD_STANDBY        0x00000003U  /*!< Card is in standby state                */

+#define HAL_SD_CARD_TRANSFER       0x00000004U  /*!< Card is in transfer state               */

+#define HAL_SD_CARD_SENDING        0x00000005U  /*!< Card is sending an operation            */

+#define HAL_SD_CARD_RECEIVING      0x00000006U  /*!< Card is receiving operation information */

+#define HAL_SD_CARD_PROGRAMMING    0x00000007U  /*!< Card is in programming state            */

+#define HAL_SD_CARD_DISCONNECTED   0x00000008U  /*!< Card is disconnected                    */

+#define HAL_SD_CARD_ERROR          0x000000FFU  /*!< Card response Error                     */

+/**

+  * @}

+  */

+

+/** @defgroup SD_Exported_Types_Group3 SD Handle Structure definition

+  * @{

+  */

+#define SD_InitTypeDef      SDMMC_InitTypeDef

+#define SD_TypeDef          SDMMC_TypeDef

+

+/**

+  * @brief  SD Card Information Structure definition

+  */

+typedef struct

+{

+  uint32_t CardType;                     /*!< Specifies the card Type                         */

+

+  uint32_t CardVersion;                  /*!< Specifies the card version                      */

+

+  uint32_t Class;                        /*!< Specifies the class of the card class           */

+

+  uint32_t RelCardAdd;                   /*!< Specifies the Relative Card Address             */

+

+  uint32_t BlockNbr;                     /*!< Specifies the Card Capacity in blocks           */

+

+  uint32_t BlockSize;                    /*!< Specifies one block size in bytes               */

+

+  uint32_t LogBlockNbr;                  /*!< Specifies the Card logical Capacity in blocks   */

+

+  uint32_t LogBlockSize;                 /*!< Specifies logical block size in bytes           */

+

+  uint32_t CardSpeed;                    /*!< Specifies the card Speed                        */

+

+}HAL_SD_CardInfoTypeDef;

+

+/**

+  * @brief  SD handle Structure definition

+  */

+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)

+typedef struct __SD_HandleTypeDef

+#else

+typedef struct

+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */

+{

+  SD_TypeDef                   *Instance;        /*!< SD registers base address           */

+

+  SD_InitTypeDef               Init;             /*!< SD required parameters              */

+

+  HAL_LockTypeDef              Lock;             /*!< SD locking object                   */

+

+  uint8_t                      *pTxBuffPtr;      /*!< Pointer to SD Tx transfer Buffer    */

+

+  uint32_t                     TxXferSize;       /*!< SD Tx Transfer size                 */

+

+  uint8_t                      *pRxBuffPtr;      /*!< Pointer to SD Rx transfer Buffer    */

+

+  uint32_t                     RxXferSize;       /*!< SD Rx Transfer size                 */

+

+  __IO uint32_t                Context;          /*!< SD transfer context                 */

+

+  __IO HAL_SD_StateTypeDef     State;            /*!< SD card State                       */

+

+  __IO uint32_t                ErrorCode;        /*!< SD Card Error codes                 */

+

+  HAL_SD_CardInfoTypeDef       SdCard;           /*!< SD Card information                 */

+

+  uint32_t                     CSD[4];           /*!< SD card specific data table         */

+

+  uint32_t                     CID[4];           /*!< SD card identification number table */

+

+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)

+  void (* TxCpltCallback)                 (struct __SD_HandleTypeDef *hsd);

+  void (* RxCpltCallback)                 (struct __SD_HandleTypeDef *hsd);

+  void (* ErrorCallback)                  (struct __SD_HandleTypeDef *hsd);

+  void (* AbortCpltCallback)              (struct __SD_HandleTypeDef *hsd);

+  void (* Read_DMADblBuf0CpltCallback)    (struct __SD_HandleTypeDef *hsd);

+  void (* Read_DMADblBuf1CpltCallback)    (struct __SD_HandleTypeDef *hsd);

+  void (* Write_DMADblBuf0CpltCallback)   (struct __SD_HandleTypeDef *hsd);

+  void (* Write_DMADblBuf1CpltCallback)   (struct __SD_HandleTypeDef *hsd);

+

+#if (USE_SD_TRANSCEIVER != 0U)

+  void (* DriveTransceiver_1_8V_Callback) (FlagStatus status);

+#endif /* USE_SD_TRANSCEIVER */

+

+  void (* MspInitCallback)                (struct __SD_HandleTypeDef *hsd);

+  void (* MspDeInitCallback)              (struct __SD_HandleTypeDef *hsd);

+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */

+}SD_HandleTypeDef;

+

+/**

+  * @}

+  */

+

+/** @defgroup SD_Exported_Types_Group4 Card Specific Data: CSD Register

+  * @{

+  */

+typedef struct

+{

+  __IO uint8_t  CSDStruct;            /*!< CSD structure                         */

+  __IO uint8_t  SysSpecVersion;       /*!< System specification version          */

+  __IO uint8_t  Reserved1;            /*!< Reserved                              */

+  __IO uint8_t  TAAC;                 /*!< Data read access time 1               */

+  __IO uint8_t  NSAC;                 /*!< Data read access time 2 in CLK cycles */

+  __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency              */

+  __IO uint16_t CardComdClasses;      /*!< Card command classes                  */

+  __IO uint8_t  RdBlockLen;           /*!< Max. read data block length           */

+  __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed       */

+  __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment              */

+  __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment               */

+  __IO uint8_t  DSRImpl;              /*!< DSR implemented                       */

+  __IO uint8_t  Reserved2;            /*!< Reserved                              */

+  __IO uint32_t DeviceSize;           /*!< Device Size                           */

+  __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min           */

+  __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max           */

+  __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min          */

+  __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max          */

+  __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier                */

+  __IO uint8_t  EraseGrSize;          /*!< Erase group size                      */

+  __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier           */

+  __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size              */

+  __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable            */

+  __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC              */

+  __IO uint8_t  WrSpeedFact;          /*!< Write speed factor                    */

+  __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length          */

+  __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed      */

+  __IO uint8_t  Reserved3;            /*!< Reserved                              */

+  __IO uint8_t  ContentProtectAppli;  /*!< Content protection application        */

+  __IO uint8_t  FileFormatGroup;      /*!< File format group                     */

+  __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP)                       */

+  __IO uint8_t  PermWrProtect;        /*!< Permanent write protection            */

+  __IO uint8_t  TempWrProtect;        /*!< Temporary write protection            */

+  __IO uint8_t  FileFormat;           /*!< File format                           */

+  __IO uint8_t  ECC;                  /*!< ECC code                              */

+  __IO uint8_t  CSD_CRC;              /*!< CSD CRC                               */

+  __IO uint8_t  Reserved4;            /*!< Always 1                              */

+}HAL_SD_CardCSDTypeDef;

+/**

+  * @}

+  */

+

+/** @defgroup SD_Exported_Types_Group5 Card Identification Data: CID Register

+  * @{

+  */

+typedef struct

+{

+  __IO uint8_t  ManufacturerID;  /*!< Manufacturer ID       */

+  __IO uint16_t OEM_AppliID;     /*!< OEM/Application ID    */

+  __IO uint32_t ProdName1;       /*!< Product Name part1    */

+  __IO uint8_t  ProdName2;       /*!< Product Name part2    */

+  __IO uint8_t  ProdRev;         /*!< Product Revision      */

+  __IO uint32_t ProdSN;          /*!< Product Serial Number */

+  __IO uint8_t  Reserved1;       /*!< Reserved1             */

+  __IO uint16_t ManufactDate;    /*!< Manufacturing Date    */

+  __IO uint8_t  CID_CRC;         /*!< CID CRC               */

+  __IO uint8_t  Reserved2;       /*!< Always 1              */

+

+}HAL_SD_CardCIDTypeDef;

+/**

+  * @}

+  */

+

+/** @defgroup SD_Exported_Types_Group6 SD Card Status returned by ACMD13

+  * @{

+  */

+typedef struct

+{

+  __IO uint8_t  DataBusWidth;           /*!< Shows the currently defined data bus width                 */

+  __IO uint8_t  SecuredMode;            /*!< Card is in secured mode of operation                       */

+  __IO uint16_t CardType;               /*!< Carries information about card type                        */

+  __IO uint32_t ProtectedAreaSize;      /*!< Carries information about the capacity of protected area   */

+  __IO uint8_t  SpeedClass;             /*!< Carries information about the speed class of the card      */

+  __IO uint8_t  PerformanceMove;        /*!< Carries information about the card's performance move      */

+  __IO uint8_t  AllocationUnitSize;     /*!< Carries information about the card's allocation unit size  */

+  __IO uint16_t EraseSize;              /*!< Determines the number of AUs to be erased in one operation */

+  __IO uint8_t  EraseTimeout;           /*!< Determines the timeout for any number of AU erase          */

+  __IO uint8_t  EraseOffset;            /*!< Carries information about the erase offset                 */

+  __IO uint8_t  UhsSpeedGrade;          /*!< Carries information about the speed grade of UHS card      */

+  __IO uint8_t  UhsAllocationUnitSize;  /*!< Carries information about the UHS card's allocation unit size  */

+  __IO uint8_t  VideoSpeedClass;        /*!< Carries information about the Video Speed Class of UHS card    */

+}HAL_SD_CardStatusTypeDef;

+/**

+  * @}

+  */

+

+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)

+/** @defgroup SD_Exported_Types_Group7 SD Callback ID enumeration definition

+  * @{

+  */

+typedef enum

+{

+  HAL_SD_TX_CPLT_CB_ID                 = 0x00U,  /*!< SD Tx Complete Callback ID                     */

+  HAL_SD_RX_CPLT_CB_ID                 = 0x01U,  /*!< SD Rx Complete Callback ID                     */

+  HAL_SD_ERROR_CB_ID                   = 0x02U,  /*!< SD Error Callback ID                           */

+  HAL_SD_ABORT_CB_ID                   = 0x03U,  /*!< SD Abort Callback ID                           */

+  HAL_SD_READ_DMA_DBL_BUF0_CPLT_CB_ID  = 0x04U,  /*!< SD Rx DMA Double Buffer 0 Complete Callback ID */

+  HAL_SD_READ_DMA_DBL_BUF1_CPLT_CB_ID  = 0x05U,  /*!< SD Rx DMA Double Buffer 1 Complete Callback ID */

+  HAL_SD_WRITE_DMA_DBL_BUF0_CPLT_CB_ID = 0x06U,  /*!< SD Tx DMA Double Buffer 0 Complete Callback ID */

+  HAL_SD_WRITE_DMA_DBL_BUF1_CPLT_CB_ID = 0x07U,  /*!< SD Tx DMA Double Buffer 1 Complete Callback ID */

+

+  HAL_SD_MSP_INIT_CB_ID                = 0x10U,  /*!< SD MspInit Callback ID                         */

+  HAL_SD_MSP_DEINIT_CB_ID              = 0x11U   /*!< SD MspDeInit Callback ID                       */

+}HAL_SD_CallbackIDTypeDef;

+/**

+  * @}

+  */

+

+/** @defgroup SD_Exported_Types_Group8 SD Callback pointer definition

+  * @{

+  */

+typedef void (*pSD_CallbackTypeDef)           (SD_HandleTypeDef *hsd);

+#if (USE_SD_TRANSCEIVER != 0U)

+typedef void (*pSD_TransceiverCallbackTypeDef)(FlagStatus status);

+#endif /* USE_SD_TRANSCEIVER */

+/**

+  * @}

+  */

+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup SD_Exported_Constants Exported Constants

+  * @{

+  */

+

+#define BLOCKSIZE   ((uint32_t)512U) /*!< Block size is 512 bytes */

+

+/** @defgroup SD_Exported_Constansts_Group1 SD Error status enumeration Structure definition

+  * @{

+  */

+#define HAL_SD_ERROR_NONE                     SDMMC_ERROR_NONE                        /*!< No error                                                     */

+#define HAL_SD_ERROR_CMD_CRC_FAIL             SDMMC_ERROR_CMD_CRC_FAIL                /*!< Command response received (but CRC check failed)             */

+#define HAL_SD_ERROR_DATA_CRC_FAIL            SDMMC_ERROR_DATA_CRC_FAIL               /*!< Data block sent/received (CRC check failed)                  */

+#define HAL_SD_ERROR_CMD_RSP_TIMEOUT          SDMMC_ERROR_CMD_RSP_TIMEOUT             /*!< Command response timeout                                     */

+#define HAL_SD_ERROR_DATA_TIMEOUT             SDMMC_ERROR_DATA_TIMEOUT                /*!< Data timeout                                                 */

+#define HAL_SD_ERROR_TX_UNDERRUN              SDMMC_ERROR_TX_UNDERRUN                 /*!< Transmit FIFO underrun                                       */

+#define HAL_SD_ERROR_RX_OVERRUN               SDMMC_ERROR_RX_OVERRUN                  /*!< Receive FIFO overrun                                         */

+#define HAL_SD_ERROR_ADDR_MISALIGNED          SDMMC_ERROR_ADDR_MISALIGNED             /*!< Misaligned address                                           */

+#define HAL_SD_ERROR_BLOCK_LEN_ERR            SDMMC_ERROR_BLOCK_LEN_ERR               /*!< Transferred block length is not allowed for the card or the

+                                                                                          number of transferred bytes does not match the block length   */

+#define HAL_SD_ERROR_ERASE_SEQ_ERR            SDMMC_ERROR_ERASE_SEQ_ERR               /*!< An error in the sequence of erase command occurs             */

+#define HAL_SD_ERROR_BAD_ERASE_PARAM          SDMMC_ERROR_BAD_ERASE_PARAM             /*!< An invalid selection for erase groups                        */

+#define HAL_SD_ERROR_WRITE_PROT_VIOLATION     SDMMC_ERROR_WRITE_PROT_VIOLATION        /*!< Attempt to program a write protect block                     */

+#define HAL_SD_ERROR_LOCK_UNLOCK_FAILED       SDMMC_ERROR_LOCK_UNLOCK_FAILED          /*!< Sequence or password error has been detected in unlock

+                                                                                           command or if there was an attempt to access a locked card   */

+#define HAL_SD_ERROR_COM_CRC_FAILED           SDMMC_ERROR_COM_CRC_FAILED              /*!< CRC check of the previous command failed                     */

+#define HAL_SD_ERROR_ILLEGAL_CMD              SDMMC_ERROR_ILLEGAL_CMD                 /*!< Command is not legal for the card state                      */

+#define HAL_SD_ERROR_CARD_ECC_FAILED          SDMMC_ERROR_CARD_ECC_FAILED             /*!< Card internal ECC was applied but failed to correct the data */

+#define HAL_SD_ERROR_CC_ERR                   SDMMC_ERROR_CC_ERR                      /*!< Internal card controller error                               */

+#define HAL_SD_ERROR_GENERAL_UNKNOWN_ERR      SDMMC_ERROR_GENERAL_UNKNOWN_ERR         /*!< General or unknown error                                     */

+#define HAL_SD_ERROR_STREAM_READ_UNDERRUN     SDMMC_ERROR_STREAM_READ_UNDERRUN        /*!< The card could not sustain data reading in stream rmode      */

+#define HAL_SD_ERROR_STREAM_WRITE_OVERRUN     SDMMC_ERROR_STREAM_WRITE_OVERRUN        /*!< The card could not sustain data programming in stream mode   */

+#define HAL_SD_ERROR_CID_CSD_OVERWRITE        SDMMC_ERROR_CID_CSD_OVERWRITE           /*!< CID/CSD overwrite error                                      */

+#define HAL_SD_ERROR_WP_ERASE_SKIP            SDMMC_ERROR_WP_ERASE_SKIP               /*!< Only partial address space was erased                        */

+#define HAL_SD_ERROR_CARD_ECC_DISABLED        SDMMC_ERROR_CARD_ECC_DISABLED           /*!< Command has been executed without using internal ECC         */

+#define HAL_SD_ERROR_ERASE_RESET              SDMMC_ERROR_ERASE_RESET                 /*!< Erase sequence was cleared before executing because an out

+                                                                                           of erase sequence command was received                       */

+#define HAL_SD_ERROR_AKE_SEQ_ERR              SDMMC_ERROR_AKE_SEQ_ERR                 /*!< Error in sequence of authentication                          */

+#define HAL_SD_ERROR_INVALID_VOLTRANGE        SDMMC_ERROR_INVALID_VOLTRANGE           /*!< Error in case of invalid voltage range                       */

+#define HAL_SD_ERROR_ADDR_OUT_OF_RANGE        SDMMC_ERROR_ADDR_OUT_OF_RANGE           /*!< Error when addressed block is out of range                   */

+#define HAL_SD_ERROR_REQUEST_NOT_APPLICABLE   SDMMC_ERROR_REQUEST_NOT_APPLICABLE      /*!< Error when command request is not applicable                 */

+#define HAL_SD_ERROR_PARAM                    SDMMC_ERROR_INVALID_PARAMETER           /*!< the used parameter is not valid                              */

+#define HAL_SD_ERROR_UNSUPPORTED_FEATURE      SDMMC_ERROR_UNSUPPORTED_FEATURE         /*!< Error when feature is not insupported                        */

+#define HAL_SD_ERROR_BUSY                     SDMMC_ERROR_BUSY                        /*!< Error when transfer process is busy                          */

+#define HAL_SD_ERROR_DMA                      SDMMC_ERROR_DMA                         /*!< Error while DMA transfer                                     */

+#define HAL_SD_ERROR_TIMEOUT                  SDMMC_ERROR_TIMEOUT                     /*!< Timeout error                                                 */

+

+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)

+#define HAL_SD_ERROR_INVALID_CALLBACK         SDMMC_ERROR_INVALID_PARAMETER       /*!< Invalid callback error                                        */

+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/** @defgroup SD_Exported_Constansts_Group2 SD context enumeration

+  * @{

+  */

+#define   SD_CONTEXT_NONE                 ((uint32_t)0x00000000U)  /*!< None                             */

+#define   SD_CONTEXT_READ_SINGLE_BLOCK    ((uint32_t)0x00000001U)  /*!< Read single block operation      */

+#define   SD_CONTEXT_READ_MULTIPLE_BLOCK  ((uint32_t)0x00000002U)  /*!< Read multiple blocks operation   */

+#define   SD_CONTEXT_WRITE_SINGLE_BLOCK   ((uint32_t)0x00000010U)  /*!< Write single block operation     */

+#define   SD_CONTEXT_WRITE_MULTIPLE_BLOCK ((uint32_t)0x00000020U)  /*!< Write multiple blocks operation  */

+#define   SD_CONTEXT_IT                   ((uint32_t)0x00000008U)  /*!< Process in Interrupt mode        */

+#define   SD_CONTEXT_DMA                  ((uint32_t)0x00000080U)  /*!< Process in DMA mode              */

+

+/**

+  * @}

+  */

+

+/** @defgroup SD_Exported_Constansts_Group3 SD Supported Memory Cards

+  * @{

+  */

+#define CARD_NORMAL_SPEED        ((uint32_t)0x00000000U)    /*!< Normal Speed Card <12.5Mo/s , Spec Version 1.01    */

+#define CARD_HIGH_SPEED          ((uint32_t)0x00000100U)    /*!< High Speed Card <25Mo/s , Spec version 2.00        */

+#define CARD_ULTRA_HIGH_SPEED    ((uint32_t)0x00000200U)    /*!< UHS-I SD Card <50Mo/s for SDR50, DDR5 Cards

+                                                                 and <104Mo/s for SDR104, Spec version 3.01          */

+

+#define CARD_SDSC                  ((uint32_t)0x00000000U)  /*!< SD Standard Capacity <2Go                          */

+#define CARD_SDHC_SDXC             ((uint32_t)0x00000001U)  /*!< SD High Capacity <32Go, SD Extended Capacity <2To  */

+#define CARD_SECURED               ((uint32_t)0x00000003U)

+

+/**

+  * @}

+  */

+

+/** @defgroup SD_Exported_Constansts_Group4 SD Supported Version

+  * @{

+  */

+#define CARD_V1_X                  ((uint32_t)0x00000000U)

+#define CARD_V2_X                  ((uint32_t)0x00000001U)

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup SD_Exported_macros SD Exported Macros

+ *  @brief macros to handle interrupts and specific clock configurations

+ * @{

+ */

+/** @brief Reset SD handle state.

+  * @param  __HANDLE__ SD Handle.

+  * @retval None

+  */

+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)

+#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__)           do {                                              \

+                                                               (__HANDLE__)->State = HAL_SD_STATE_RESET; \

+                                                               (__HANDLE__)->MspInitCallback = NULL;       \

+                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \

+                                                             } while(0)

+#else

+#define __HAL_SD_RESET_HANDLE_STATE(__HANDLE__)           ((__HANDLE__)->State = HAL_SD_STATE_RESET)

+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */

+

+/**

+  * @brief  Enable the SD device interrupt.

+  * @param  __HANDLE__ SD Handle.

+  * @param  __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.

+  *         This parameter can be one or a combination of the following values:

+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt

+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt

+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt

+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt

+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt

+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt

+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt

+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt

+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt

+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt

+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt

+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt

+  *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt

+  *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt

+  *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt

+  *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt

+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt

+  *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt

+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt

+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt

+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt

+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt

+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt

+  * @retval None

+  */

+#define __HAL_SD_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))

+

+/**

+  * @brief  Disable the SD device interrupt.

+  * @param  __HANDLE__ SD Handle.

+  * @param  __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.

+  *          This parameter can be one or a combination of the following values:

+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt

+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt

+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt

+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt

+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt

+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt

+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt

+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt

+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt

+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt

+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt

+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt

+  *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt

+  *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt

+  *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt

+  *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt

+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt

+  *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt

+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt

+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt

+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt

+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt

+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt

+  * @retval None

+  */

+#define __HAL_SD_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDMMC_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))

+

+/**

+  * @brief  Check whether the specified SD flag is set or not.

+  * @param  __HANDLE__ SD Handle.

+  * @param  __FLAG__ specifies the flag to check.

+  *          This parameter can be one of the following values:

+  *            @arg SDMMC_FLAG_CCRCFAIL:   Command response received (CRC check failed)

+  *            @arg SDMMC_FLAG_DCRCFAIL:   Data block sent/received (CRC check failed)

+  *            @arg SDMMC_FLAG_CTIMEOUT:   Command response timeout

+  *            @arg SDMMC_FLAG_DTIMEOUT:   Data timeout

+  *            @arg SDMMC_FLAG_TXUNDERR:   Transmit FIFO underrun error

+  *            @arg SDMMC_FLAG_RXOVERR:    Received FIFO overrun error

+  *            @arg SDMMC_FLAG_CMDREND:    Command response received (CRC check passed)

+  *            @arg SDMMC_FLAG_CMDSENT:    Command sent (no response required)

+  *            @arg SDMMC_FLAG_DATAEND:    Data end (data counter, DATACOUNT, is zero)

+  *            @arg SDMMC_FLAG_DHOLD:      Data transfer Hold

+  *            @arg SDMMC_FLAG_DBCKEND:    Data block sent/received (CRC check passed)

+  *            @arg SDMMC_FLAG_DABORT:     Data transfer aborted by CMD12

+  *            @arg SDMMC_FLAG_DPSMACT:    Data path state machine active

+  *            @arg SDMMC_FLAG_CPSMACT:    Command path state machine active

+  *            @arg SDMMC_FLAG_TXFIFOHE:   Transmit FIFO Half Empty

+  *            @arg SDMMC_FLAG_RXFIFOHF:   Receive FIFO Half Full

+  *            @arg SDMMC_FLAG_TXFIFOF:    Transmit FIFO full

+  *            @arg SDMMC_FLAG_RXFIFOF:    Receive FIFO full

+  *            @arg SDMMC_FLAG_TXFIFOE:    Transmit FIFO empty

+  *            @arg SDMMC_FLAG_RXFIFOE:    Receive FIFO empty

+  *            @arg SDMMC_FLAG_BUSYD0:     Inverted value of SDMMC_D0 line (Busy)

+  *            @arg SDMMC_FLAG_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected

+  *            @arg SDMMC_FLAG_SDIOIT:     SDIO interrupt received

+  *            @arg SDMMC_FLAG_ACKFAIL:    Boot Acknowledgment received

+  *            @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout

+  *            @arg SDMMC_FLAG_VSWEND:     Voltage switch critical timing section completion

+  *            @arg SDMMC_FLAG_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure

+  *            @arg SDMMC_FLAG_IDMATE:     IDMA transfer error

+  *            @arg SDMMC_FLAG_IDMABTC:    IDMA buffer transfer complete

+  * @retval The new state of SD FLAG (SET or RESET).

+  */

+#define __HAL_SD_GET_FLAG(__HANDLE__, __FLAG__) __SDMMC_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))

+

+/**

+  * @brief  Clear the SD's pending flags.

+  * @param  __HANDLE__ SD Handle.

+  * @param  __FLAG__ specifies the flag to clear.

+  *          This parameter can be one or a combination of the following values:

+  *            @arg SDMMC_FLAG_CCRCFAIL:   Command response received (CRC check failed)

+  *            @arg SDMMC_FLAG_DCRCFAIL:   Data block sent/received (CRC check failed)

+  *            @arg SDMMC_FLAG_CTIMEOUT:   Command response timeout

+  *            @arg SDMMC_FLAG_DTIMEOUT:   Data timeout

+  *            @arg SDMMC_FLAG_TXUNDERR:   Transmit FIFO underrun error

+  *            @arg SDMMC_FLAG_RXOVERR:    Received FIFO overrun error

+  *            @arg SDMMC_FLAG_CMDREND:    Command response received (CRC check passed)

+  *            @arg SDMMC_FLAG_CMDSENT:    Command sent (no response required)

+  *            @arg SDMMC_FLAG_DATAEND:    Data end (data counter, DATACOUNT, is zero)

+  *            @arg SDMMC_FLAG_DHOLD:      Data transfer Hold

+  *            @arg SDMMC_FLAG_DBCKEND:    Data block sent/received (CRC check passed)

+  *            @arg SDMMC_FLAG_DABORT:     Data transfer aborted by CMD12

+  *            @arg SDMMC_FLAG_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected

+  *            @arg SDMMC_FLAG_SDIOIT:     SDIO interrupt received

+  *            @arg SDMMC_FLAG_ACKFAIL:    Boot Acknowledgment received

+  *            @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout

+  *            @arg SDMMC_FLAG_VSWEND:     Voltage switch critical timing section completion

+  *            @arg SDMMC_FLAG_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure

+  *            @arg SDMMC_FLAG_IDMATE:     IDMA transfer error

+  *            @arg SDMMC_FLAG_IDMABTC:    IDMA buffer transfer complete

+  * @retval None

+  */

+#define __HAL_SD_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDMMC_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))

+

+/**

+  * @brief  Check whether the specified SD interrupt has occurred or not.

+  * @param  __HANDLE__ SD Handle.

+  * @param  __INTERRUPT__ specifies the SDMMC interrupt source to check.

+  *          This parameter can be one of the following values:

+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt

+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt

+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt

+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt

+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt

+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt

+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt

+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt

+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt

+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt

+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt

+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt

+  *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt

+  *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt

+  *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt

+  *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt

+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt

+  *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt

+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt

+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt

+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt

+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt

+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt

+  * @retval The new state of SD IT (SET or RESET).

+  */

+#define __HAL_SD_GET_IT(__HANDLE__, __INTERRUPT__) __SDMMC_GET_IT((__HANDLE__)->Instance, (__INTERRUPT__))

+

+/**

+  * @brief  Clear the SD's interrupt pending bits.

+  * @param  __HANDLE__ SD Handle.

+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.

+  *          This parameter can be one or a combination of the following values:

+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt

+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt

+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt

+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt

+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt

+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt

+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt

+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt

+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt

+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt

+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt

+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt

+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt

+  *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt

+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt

+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt

+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt

+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt

+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt

+  * @retval None

+  */

+#define __HAL_SD_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDMMC_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))

+

+/**

+  * @}

+  */

+

+/* Include SD HAL Extension module */

+#include "stm32h7xx_hal_sd_ex.h"

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup SD_Exported_Functions SD Exported Functions

+  * @{

+  */

+

+/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions

+  * @{

+  */

+HAL_StatusTypeDef HAL_SD_Init     (SD_HandleTypeDef *hsd);

+HAL_StatusTypeDef HAL_SD_InitCard (SD_HandleTypeDef *hsd);

+HAL_StatusTypeDef HAL_SD_DeInit   (SD_HandleTypeDef *hsd);

+void              HAL_SD_MspInit  (SD_HandleTypeDef *hsd);

+void              HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);

+/**

+  * @}

+  */

+

+/** @defgroup SD_Exported_Functions_Group2 Input and Output operation functions

+  * @{

+  */

+/* Blocking mode: Polling */

+HAL_StatusTypeDef HAL_SD_ReadBlocks     (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);

+HAL_StatusTypeDef HAL_SD_WriteBlocks    (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout);

+HAL_StatusTypeDef HAL_SD_Erase          (SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd);

+/* Non-Blocking mode: IT */

+HAL_StatusTypeDef HAL_SD_ReadBlocks_IT  (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);

+HAL_StatusTypeDef HAL_SD_WriteBlocks_IT (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);

+/* Non-Blocking mode: DMA */

+HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA (SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);

+HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks);

+

+void              HAL_SD_IRQHandler     (SD_HandleTypeDef *hsd);

+

+/* Callback in non blocking modes (DMA) */

+void              HAL_SD_TxCpltCallback (SD_HandleTypeDef *hsd);

+void              HAL_SD_RxCpltCallback (SD_HandleTypeDef *hsd);

+void              HAL_SD_ErrorCallback  (SD_HandleTypeDef *hsd);

+void              HAL_SD_AbortCallback  (SD_HandleTypeDef *hsd);

+

+#if (USE_SD_TRANSCEIVER != 0U)

+/* Callback to switch in 1.8V mode */

+void              HAL_SD_DriveTransceiver_1_8V_Callback(FlagStatus status);

+#endif /* USE_SD_TRANSCEIVER */

+

+#if defined (USE_HAL_SD_REGISTER_CALLBACKS) && (USE_HAL_SD_REGISTER_CALLBACKS == 1U)

+/* SD callback registering/unregistering */

+HAL_StatusTypeDef HAL_SD_RegisterCallback  (SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID, pSD_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_SD_UnRegisterCallback(SD_HandleTypeDef *hsd, HAL_SD_CallbackIDTypeDef CallbackID);

+

+#if (USE_SD_TRANSCEIVER != 0U)

+HAL_StatusTypeDef HAL_SD_RegisterTransceiverCallback  (SD_HandleTypeDef *hsd, pSD_TransceiverCallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd);

+#endif /* USE_SD_TRANSCEIVER */

+#endif /* USE_HAL_SD_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions

+  * @{

+  */

+HAL_StatusTypeDef HAL_SD_ConfigWideBusOperation(SD_HandleTypeDef *hsd, uint32_t WideMode);

+HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t SpeedMode);

+/**

+  * @}

+  */

+

+/** @defgroup SD_Exported_Functions_Group4 SD card related functions

+  * @{

+  */

+HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd);

+HAL_StatusTypeDef       HAL_SD_GetCardCID   (SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID);

+HAL_StatusTypeDef       HAL_SD_GetCardCSD   (SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD);

+HAL_StatusTypeDef       HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus);

+HAL_StatusTypeDef       HAL_SD_GetCardInfo  (SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo);

+/**

+  * @}

+  */

+

+/** @defgroup SD_Exported_Functions_Group5 Peripheral State and Errors functions

+  * @{

+  */

+HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd);

+uint32_t            HAL_SD_GetError(SD_HandleTypeDef *hsd);

+/**

+  * @}

+  */

+

+/** @defgroup SD_Exported_Functions_Group6 Perioheral Abort management

+  * @{

+  */

+HAL_StatusTypeDef HAL_SD_Abort   (SD_HandleTypeDef *hsd);

+HAL_StatusTypeDef HAL_SD_Abort_IT(SD_HandleTypeDef *hsd);

+/**

+  * @}

+  */

+

+/* Private types -------------------------------------------------------------*/

+/** @defgroup SD_Private_Types SD Private Types

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private defines -----------------------------------------------------------*/

+/** @defgroup SD_Private_Defines SD Private Defines

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private variables ---------------------------------------------------------*/

+/** @defgroup SD_Private_Variables SD Private Variables

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup SD_Private_Constants SD Private Constants

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup SD_Private_Macros SD Private Macros

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private functions prototypes ----------------------------------------------*/

+/** @defgroup SD_Private_Functions_Prototypes SD Private Functions Prototypes

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private functions ---------------------------------------------------------*/

+/** @defgroup SD_Private_Functions SD Private Functions

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+

+#endif /* STM32H7xx_HAL_SD_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_sd_ex.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_sd_ex.h
new file mode 100644
index 0000000000..4a5ff5ba8e
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_sd_ex.h
@@ -0,0 +1,113 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_sd_ex.h

+  * @author  MCD Application Team

+  * @brief   Header file of SD HAL extended module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                       opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */ 

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_SD_EX_H

+#define STM32H7xx_HAL_SD_EX_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup SDEx

+  * @brief SD HAL extended module driver

+  * @{

+  */ 

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup SDEx_Exported_Types SDEx Exported Types

+  * @{

+  */

+

+/** @defgroup SDEx_Exported_Types_Group1 SD Card Internal DMA Buffer structure

+  * @{

+  */ 

+typedef enum

+{

+  SD_DMA_BUFFER0      = 0x00U,    /*!< selects SD internal DMA Buffer 0     */

+  SD_DMA_BUFFER1      = 0x01U,    /*!< selects SD internal DMA Buffer 1     */

+

+}HAL_SDEx_DMABuffer_MemoryTypeDef;

+

+

+/** 

+  * @}

+  */

+  

+/** 

+  * @}

+  */  

+/* Exported constants --------------------------------------------------------*/

+/* Exported macro ------------------------------------------------------------*/

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup SDEx_Exported_Functions SDEx Exported Functions

+  * @{

+  */

+  

+/** @defgroup SDEx_Exported_Functions_Group1 MultiBuffer functions

+  * @{

+  */

+HAL_StatusTypeDef HAL_SDEx_ConfigDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t * pDataBuffer0, uint32_t * pDataBuffer1, uint32_t BufferSize);

+HAL_StatusTypeDef HAL_SDEx_ReadBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks);

+HAL_StatusTypeDef HAL_SDEx_WriteBlocksDMAMultiBuffer(SD_HandleTypeDef *hsd, uint32_t BlockAdd, uint32_t NumberOfBlocks);

+HAL_StatusTypeDef HAL_SDEx_ChangeDMABuffer(SD_HandleTypeDef *hsd, HAL_SDEx_DMABuffer_MemoryTypeDef Buffer, uint32_t *pDataBuffer);

+

+void HAL_SDEx_Read_DMADoubleBuf0CpltCallback(SD_HandleTypeDef *hsd);

+void HAL_SDEx_Read_DMADoubleBuf1CpltCallback(SD_HandleTypeDef *hsd);

+void HAL_SDEx_Write_DMADoubleBuf0CpltCallback(SD_HandleTypeDef *hsd);

+void HAL_SDEx_Write_DMADoubleBuf1CpltCallback(SD_HandleTypeDef *hsd);

+

+/**

+  * @}

+  */

+  

+/**

+  * @}

+  */

+  

+/* Private types -------------------------------------------------------------*/

+/* Private defines -----------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/* Private macros ------------------------------------------------------------*/

+/* Private functions prototypes ----------------------------------------------*/

+/* Private functions ---------------------------------------------------------*/

+  

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+#ifdef __cplusplus

+}

+#endif

+

+

+#endif /* stm32h7xx_HAL_SD_EX_H */ 

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_sdram.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_sdram.h
new file mode 100644
index 0000000000..5bde520dc8
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_sdram.h
@@ -0,0 +1,228 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_sdram.h

+  * @author  MCD Application Team

+  * @brief   Header file of SDRAM HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                       opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_SDRAM_H

+#define STM32H7xx_HAL_SDRAM_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_ll_fmc.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup SDRAM

+  * @{

+  */

+

+/* Exported typedef ----------------------------------------------------------*/

+

+/** @defgroup SDRAM_Exported_Types SDRAM Exported Types

+  * @{

+  */

+

+/**

+  * @brief  HAL SDRAM State structure definition

+  */

+typedef enum

+{

+  HAL_SDRAM_STATE_RESET             = 0x00U,  /*!< SDRAM not yet initialized or disabled */

+  HAL_SDRAM_STATE_READY             = 0x01U,  /*!< SDRAM initialized and ready for use   */

+  HAL_SDRAM_STATE_BUSY              = 0x02U,  /*!< SDRAM internal process is ongoing     */

+  HAL_SDRAM_STATE_ERROR             = 0x03U,  /*!< SDRAM error state                     */

+  HAL_SDRAM_STATE_WRITE_PROTECTED   = 0x04U,  /*!< SDRAM device write protected          */

+  HAL_SDRAM_STATE_PRECHARGED        = 0x05U   /*!< SDRAM device precharged               */

+

+} HAL_SDRAM_StateTypeDef;

+

+/**

+  * @brief  SDRAM handle Structure definition

+  */

+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)

+typedef struct __SDRAM_HandleTypeDef

+#else

+typedef struct

+#endif /* USE_HAL_SDRAM_REGISTER_CALLBACKS  */

+{

+  FMC_SDRAM_TypeDef             *Instance;  /*!< Register base address                 */

+

+  FMC_SDRAM_InitTypeDef         Init;       /*!< SDRAM device configuration parameters */

+

+  __IO HAL_SDRAM_StateTypeDef   State;      /*!< SDRAM access state                    */

+

+  HAL_LockTypeDef               Lock;       /*!< SDRAM locking object                  */

+

+  MDMA_HandleTypeDef             *hmdma;      /*!< Pointer DMA handler                   */

+

+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)

+  void  (* MspInitCallback)        ( struct __SDRAM_HandleTypeDef * hsdram);    /*!< SDRAM Msp Init callback              */

+  void  (* MspDeInitCallback)      ( struct __SDRAM_HandleTypeDef * hsdram);    /*!< SDRAM Msp DeInit callback            */

+  void  (* RefreshErrorCallback)   ( struct __SDRAM_HandleTypeDef * hsdram);    /*!< SDRAM Refresh Error callback         */

+  void  (* DmaXferCpltCallback)    ( MDMA_HandleTypeDef * hmdma);                 /*!< SDRAM DMA Xfer Complete callback     */

+  void  (* DmaXferErrorCallback)   ( MDMA_HandleTypeDef * hmdma);                 /*!< SDRAM DMA Xfer Error callback        */

+#endif

+} SDRAM_HandleTypeDef;

+

+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  HAL SDRAM Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_SDRAM_MSP_INIT_CB_ID       = 0x00U,  /*!< SDRAM MspInit Callback ID           */

+  HAL_SDRAM_MSP_DEINIT_CB_ID     = 0x01U,  /*!< SDRAM MspDeInit Callback ID         */

+  HAL_SDRAM_REFRESH_ERR_CB_ID    = 0x02U,  /*!< SDRAM Refresh Error Callback ID     */

+  HAL_SDRAM_DMA_XFER_CPLT_CB_ID  = 0x03U,  /*!< SDRAM DMA Xfer Complete Callback ID */

+  HAL_SDRAM_DMA_XFER_ERR_CB_ID   = 0x04U   /*!< SDRAM DMA Xfer Error Callback ID    */

+}HAL_SDRAM_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL SDRAM Callback pointer definition

+  */

+typedef void (*pSDRAM_CallbackTypeDef)(SDRAM_HandleTypeDef *hsdram);

+typedef void (*pSDRAM_DmaCallbackTypeDef)(MDMA_HandleTypeDef *hmdma);

+#endif

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/* Exported macro ------------------------------------------------------------*/

+

+/** @defgroup SDRAM_Exported_Macros SDRAM Exported Macros

+  * @{

+  */

+

+/** @brief Reset SDRAM handle state

+  * @param  __HANDLE__ specifies the SDRAM handle.

+  * @retval None

+  */

+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)

+#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__)        do {                                               \

+                                                               (__HANDLE__)->State = HAL_SDRAM_STATE_RESET;  \

+                                                               (__HANDLE__)->MspInitCallback = NULL;         \

+                                                               (__HANDLE__)->MspDeInitCallback = NULL;       \

+                                                             } while(0)

+#else

+#define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)

+#endif

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+

+/** @addtogroup SDRAM_Exported_Functions SDRAM Exported Functions

+  * @{

+  */

+

+/** @addtogroup SDRAM_Exported_Functions_Group1

+  * @{

+  */

+

+/* Initialization/de-initialization functions *********************************/

+HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing);

+HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram);

+void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram);

+void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram);

+

+void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram);

+void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram);

+void HAL_SDRAM_DMA_XferCpltCallback(MDMA_HandleTypeDef *hmdma);

+void HAL_SDRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma);

+

+/**

+  * @}

+  */

+

+/** @addtogroup SDRAM_Exported_Functions_Group2

+  * @{

+  */

+/* I/O operation functions ****************************************************/

+HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);

+HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);

+HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);

+HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);

+HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);

+HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);

+

+HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);

+HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);

+

+#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)

+/* SDRAM callback registering/unregistering */

+HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId);

+HAL_StatusTypeDef HAL_SDRAM_RegisterDmaCallback(SDRAM_HandleTypeDef *hsdram, HAL_SDRAM_CallbackIDTypeDef CallbackId, pSDRAM_DmaCallbackTypeDef pCallback);

+#endif

+

+/**

+  * @}

+  */

+

+/** @addtogroup SDRAM_Exported_Functions_Group3

+  * @{

+  */

+/* SDRAM Control functions  *****************************************************/

+HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram);

+HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram);

+HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);

+HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate);

+HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber);

+uint32_t          HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram);

+

+/**

+  * @}

+  */

+

+/** @addtogroup SDRAM_Exported_Functions_Group4

+  * @{

+  */

+/* SDRAM State functions ********************************************************/

+HAL_SDRAM_StateTypeDef  HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_SDRAM_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_smartcard.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_smartcard.h
new file mode 100644
index 0000000000..0fc2c6a70e
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_smartcard.h
@@ -0,0 +1,1368 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_smartcard.h

+  * @author  MCD Application Team

+  * @brief   Header file of SMARTCARD HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_SMARTCARD_H

+#define STM32H7xx_HAL_SMARTCARD_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup SMARTCARD

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types

+  * @{

+  */

+

+/**

+  * @brief SMARTCARD Init Structure definition

+  */

+typedef struct

+{

+  uint32_t BaudRate;                  /*!< Configures the SmartCard communication baud rate.

+                                           The baud rate register is computed using the following formula:

+                                              Baud Rate Register = ((usart_ker_ckpres) / ((hsmartcard->Init.BaudRate)))

+                                           where usart_ker_ckpres is the USART input clock divided by a prescaler */

+

+  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.

+                                           This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */

+

+  uint32_t StopBits;                  /*!< Specifies the number of stop bits.

+                                           This parameter can be a value of @ref SMARTCARD_Stop_Bits. */

+

+  uint16_t Parity;                    /*!< Specifies the parity mode.

+                                           This parameter can be a value of @ref SMARTCARD_Parity

+                                           @note The parity is enabled by default (PCE is forced to 1).

+                                                 Since the WordLength is forced to 8 bits + parity, M is

+                                                 forced to 1 and the parity bit is the 9th bit. */

+

+  uint16_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.

+                                           This parameter can be a value of @ref SMARTCARD_Mode */

+

+  uint16_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.

+                                           This parameter can be a value of @ref SMARTCARD_Clock_Polarity */

+

+  uint16_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.

+                                           This parameter can be a value of @ref SMARTCARD_Clock_Phase */

+

+  uint16_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted

+                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.

+                                           This parameter can be a value of @ref SMARTCARD_Last_Bit */

+

+  uint16_t OneBitSampling;            /*!< Specifies whether a single sample or three samples' majority vote is selected.

+                                           Selecting the single sample method increases the receiver tolerance to clock

+                                           deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */

+

+  uint8_t  Prescaler;                 /*!< Specifies the SmartCard Prescaler.

+                                           This parameter can be any value from 0x01 to 0x1F. Prescaler value is multiplied

+                                           by 2 to give the division factor of the source clock frequency */

+

+  uint8_t  GuardTime;                 /*!< Specifies the SmartCard Guard Time applied after stop bits. */

+

+  uint16_t NACKEnable;                /*!< Specifies whether the SmartCard NACK transmission is enabled

+                                           in case of parity error.

+                                           This parameter can be a value of @ref SMARTCARD_NACK_Enable */

+

+  uint32_t TimeOutEnable;             /*!< Specifies whether the receiver timeout is enabled.

+                                            This parameter can be a value of @ref SMARTCARD_Timeout_Enable*/

+

+  uint32_t TimeOutValue;              /*!< Specifies the receiver time out value in number of baud blocks:

+                                           it is used to implement the Character Wait Time (CWT) and

+                                           Block Wait Time (BWT). It is coded over 24 bits. */

+

+  uint8_t BlockLength;                /*!< Specifies the SmartCard Block Length in T=1 Reception mode.

+                                           This parameter can be any value from 0x0 to 0xFF */

+

+  uint8_t AutoRetryCount;             /*!< Specifies the SmartCard auto-retry count (number of retries in

+                                            receive and transmit mode). When set to 0, retransmission is

+                                            disabled. Otherwise, its maximum value is 7 (before signalling

+                                            an error) */

+

+  uint32_t ClockPrescaler;            /*!< Specifies the prescaler value used to divide the USART clock source.

+                                           This parameter can be a value of @ref SMARTCARD_ClockPrescaler. */

+

+} SMARTCARD_InitTypeDef;

+

+/**

+  * @brief  SMARTCARD advanced features initalization structure definition

+  */

+typedef struct

+{

+  uint32_t AdvFeatureInit;            /*!< Specifies which advanced SMARTCARD features is initialized. Several

+                                           advanced features may be initialized at the same time. This parameter

+                                           can be a value of @ref SMARTCARDEx_Advanced_Features_Initialization_Type */

+

+  uint32_t TxPinLevelInvert;          /*!< Specifies whether the TX pin active level is inverted.

+                                           This parameter can be a value of @ref SMARTCARD_Tx_Inv  */

+

+  uint32_t RxPinLevelInvert;          /*!< Specifies whether the RX pin active level is inverted.

+                                           This parameter can be a value of @ref SMARTCARD_Rx_Inv  */

+

+  uint32_t DataInvert;                /*!< Specifies whether data are inverted (positive/direct logic

+                                           vs negative/inverted logic).

+                                           This parameter can be a value of @ref SMARTCARD_Data_Inv */

+

+  uint32_t Swap;                      /*!< Specifies whether TX and RX pins are swapped.

+                                           This parameter can be a value of @ref SMARTCARD_Rx_Tx_Swap */

+

+  uint32_t OverrunDisable;            /*!< Specifies whether the reception overrun detection is disabled.

+                                           This parameter can be a value of @ref SMARTCARD_Overrun_Disable */

+

+  uint32_t DMADisableonRxError;       /*!< Specifies whether the DMA is disabled in case of reception error.

+                                           This parameter can be a value of @ref SMARTCARD_DMA_Disable_on_Rx_Error */

+

+  uint32_t MSBFirst;                  /*!< Specifies whether MSB is sent first on UART line.

+                                           This parameter can be a value of @ref SMARTCARD_MSB_First */

+

+  uint16_t TxCompletionIndication;     /*!< Specifies which transmission completion indication is used: before (when

+                                            relevant flag is available) or once guard time period has elapsed.

+                                           This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */

+} SMARTCARD_AdvFeatureInitTypeDef;

+

+/**

+  * @brief HAL SMARTCARD State definition

+  * @note  HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState (see @ref SMARTCARD_State_Definition).

+  *        - gState contains SMARTCARD state information related to global Handle management

+  *          and also information related to Tx operations.

+  *          gState value coding follow below described bitmap :

+  *          b7-b6  Error information

+  *             00 : No Error

+  *             01 : (Not Used)

+  *             10 : Timeout

+  *             11 : Error

+  *          b5     Peripheral initialization status

+  *             0  : Reset (Peripheral not initialized)

+  *             1  : Init done (Peripheral not initialized. HAL SMARTCARD Init function already called)

+  *          b4-b3  (not used)

+  *             xx : Should be set to 00

+  *          b2     Intrinsic process state

+  *             0  : Ready

+  *             1  : Busy (Peripheral busy with some configuration or internal operations)

+  *          b1     (not used)

+  *             x  : Should be set to 0

+  *          b0     Tx state

+  *             0  : Ready (no Tx operation ongoing)

+  *             1  : Busy (Tx operation ongoing)

+  *        - RxState contains information related to Rx operations.

+  *          RxState value coding follow below described bitmap :

+  *          b7-b6  (not used)

+  *             xx : Should be set to 00

+  *          b5     Peripheral initialization status

+  *             0  : Reset (Peripheral not initialized)

+  *             1  : Init done (Peripheral not initialized)

+  *          b4-b2  (not used)

+  *            xxx : Should be set to 000

+  *          b1     Rx state

+  *             0  : Ready (no Rx operation ongoing)

+  *             1  : Busy (Rx operation ongoing)

+  *          b0     (not used)

+  *             x  : Should be set to 0.

+  */

+typedef uint32_t HAL_SMARTCARD_StateTypeDef;

+

+/**

+  * @brief  SMARTCARD handle Structure definition

+  */

+typedef struct __SMARTCARD_HandleTypeDef

+{

+  USART_TypeDef                     *Instance;             /*!< USART registers base address                          */

+

+  SMARTCARD_InitTypeDef             Init;                  /*!< SmartCard communication parameters                    */

+

+  SMARTCARD_AdvFeatureInitTypeDef   AdvancedInit;          /*!< SmartCard advanced features initialization parameters */

+

+  uint8_t                           *pTxBuffPtr;           /*!< Pointer to SmartCard Tx transfer Buffer               */

+

+  uint16_t                          TxXferSize;            /*!< SmartCard Tx Transfer size                            */

+

+  __IO uint16_t                     TxXferCount;           /*!< SmartCard Tx Transfer Counter                         */

+

+  uint8_t                           *pRxBuffPtr;           /*!< Pointer to SmartCard Rx transfer Buffer               */

+

+  uint16_t                          RxXferSize;            /*!< SmartCard Rx Transfer size                            */

+

+  __IO uint16_t                     RxXferCount;           /*!< SmartCard Rx Transfer Counter                         */

+

+  uint16_t                          NbRxDataToProcess;     /*!< Number of data to process during RX ISR execution     */

+

+  uint16_t                          NbTxDataToProcess;     /*!< Number of data to process during TX ISR execution     */

+

+  uint32_t                          FifoMode;              /*!< Specifies if the FIFO mode will be used.

+                                                                This parameter can be a value of @ref SMARTCARDEx_FIFO_mode. */

+

+  void (*RxISR)(struct __SMARTCARD_HandleTypeDef *huart);  /*!< Function pointer on Rx IRQ handler                    */

+

+  void (*TxISR)(struct __SMARTCARD_HandleTypeDef *huart);  /*!< Function pointer on Tx IRQ handler                    */

+

+  DMA_HandleTypeDef                 *hdmatx;               /*!< SmartCard Tx DMA Handle parameters                    */

+

+  DMA_HandleTypeDef                 *hdmarx;               /*!< SmartCard Rx DMA Handle parameters                    */

+

+  HAL_LockTypeDef                   Lock;                  /*!< Locking object                                        */

+

+  __IO HAL_SMARTCARD_StateTypeDef   gState;                /*!< SmartCard state information related to global Handle management

+                                                                and also related to Tx operations.

+                                                                This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */

+

+  __IO HAL_SMARTCARD_StateTypeDef   RxState;               /*!< SmartCard state information related to Rx operations.

+                                                                This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */

+

+  __IO uint32_t                     ErrorCode;             /*!< SmartCard Error code                                  */

+

+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)

+  void (* TxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);            /*!< SMARTCARD Tx Complete Callback             */

+

+  void (* RxCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);            /*!< SMARTCARD Rx Complete Callback             */

+

+  void (* ErrorCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);             /*!< SMARTCARD Error Callback                   */

+

+  void (* AbortCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);         /*!< SMARTCARD Abort Complete Callback          */

+

+  void (* AbortTransmitCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard); /*!< SMARTCARD Abort Transmit Complete Callback */

+

+  void (* AbortReceiveCpltCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);  /*!< SMARTCARD Abort Receive Complete Callback  */

+

+  void (* RxFifoFullCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);        /*!< SMARTCARD Rx Fifo Full Callback            */

+

+  void (* TxFifoEmptyCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);       /*!< SMARTCARD Tx Fifo Empty Callback           */

+

+  void (* MspInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);           /*!< SMARTCARD Msp Init callback                */

+

+  void (* MspDeInitCallback)(struct __SMARTCARD_HandleTypeDef *hsmartcard);         /*!< SMARTCARD Msp DeInit callback              */

+#endif  /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */

+

+} SMARTCARD_HandleTypeDef;

+

+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  HAL SMARTCARD Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_SMARTCARD_TX_COMPLETE_CB_ID             = 0x00U,    /*!< SMARTCARD Tx Complete Callback ID             */

+  HAL_SMARTCARD_RX_COMPLETE_CB_ID             = 0x01U,    /*!< SMARTCARD Rx Complete Callback ID             */

+  HAL_SMARTCARD_ERROR_CB_ID                   = 0x02U,    /*!< SMARTCARD Error Callback ID                   */

+  HAL_SMARTCARD_ABORT_COMPLETE_CB_ID          = 0x03U,    /*!< SMARTCARD Abort Complete Callback ID          */

+  HAL_SMARTCARD_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x04U,    /*!< SMARTCARD Abort Transmit Complete Callback ID */

+  HAL_SMARTCARD_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x05U,    /*!< SMARTCARD Abort Receive Complete Callback ID  */

+  HAL_SMARTCARD_RX_FIFO_FULL_CB_ID            = 0x06U,    /*!< SMARTCARD Rx Fifo Full Callback ID            */

+  HAL_SMARTCARD_TX_FIFO_EMPTY_CB_ID           = 0x07U,    /*!< SMARTCARD Tx Fifo Empty Callback ID           */

+

+  HAL_SMARTCARD_MSPINIT_CB_ID                 = 0x08U,    /*!< SMARTCARD MspInit callback ID                 */

+  HAL_SMARTCARD_MSPDEINIT_CB_ID               = 0x09U     /*!< SMARTCARD MspDeInit callback ID               */

+

+} HAL_SMARTCARD_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL SMARTCARD Callback pointer definition

+  */

+typedef  void (*pSMARTCARD_CallbackTypeDef)(SMARTCARD_HandleTypeDef *hsmartcard);  /*!< pointer to an SMARTCARD callback function */

+

+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */

+

+/**

+  * @brief  SMARTCARD clock sources

+  */

+typedef enum

+{

+  SMARTCARD_CLOCKSOURCE_D2PCLK1   = 0x00U, /*!< Domain2 PCLK1 clock source */

+  SMARTCARD_CLOCKSOURCE_D2PCLK2   = 0x01U, /*!< Domain2 PCLK2 clock source */

+  SMARTCARD_CLOCKSOURCE_HSI       = 0x04U, /*!< HSI clock source           */

+  SMARTCARD_CLOCKSOURCE_CSI       = 0x08U, /*!< CSI clock source           */

+  SMARTCARD_CLOCKSOURCE_LSE       = 0x20U, /*!< LSE clock source           */

+  SMARTCARD_CLOCKSOURCE_PLL2Q     = 0x40U, /*!< PLL2Q clock source         */

+  SMARTCARD_CLOCKSOURCE_PLL3Q     = 0x80U, /*!< PLL3Q clock source         */

+  SMARTCARD_CLOCKSOURCE_UNDEFINED = 0x10U  /*!< undefined clock source     */

+} SMARTCARD_ClockSourceTypeDef;

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup SMARTCARD_Exported_Constants  SMARTCARD Exported Constants

+  * @{

+  */

+

+/** @defgroup SMARTCARD_State_Definition SMARTCARD State Code Definition

+  * @{

+  */

+#define HAL_SMARTCARD_STATE_RESET            0x00000000U                     /*!< Peripheral is not initialized

+                                                                                  Value is allowed for gState and RxState */

+#define HAL_SMARTCARD_STATE_READY            0x00000020U                     /*!< Peripheral Initialized and ready for use

+                                                                                  Value is allowed for gState and RxState */

+#define HAL_SMARTCARD_STATE_BUSY             0x00000024U                     /*!< an internal process is ongoing

+                                                                                  Value is allowed for gState only */

+#define HAL_SMARTCARD_STATE_BUSY_TX          0x00000021U                     /*!< Data Transmission process is ongoing

+                                                                                  Value is allowed for gState only */

+#define HAL_SMARTCARD_STATE_BUSY_RX          0x00000022U                     /*!< Data Reception process is ongoing

+                                                                                  Value is allowed for RxState only */

+#define HAL_SMARTCARD_STATE_BUSY_TX_RX       0x00000023U                     /*!< Data Transmission and Reception process is ongoing

+                                                                                  Not to be used for neither gState nor RxState.

+                                                                                  Value is result of combination (Or) between gState and RxState values */

+#define HAL_SMARTCARD_STATE_TIMEOUT          0x000000A0U                     /*!< Timeout state

+                                                                                  Value is allowed for gState only */

+#define HAL_SMARTCARD_STATE_ERROR            0x000000E0U                     /*!< Error

+                                                                                  Value is allowed for gState only */

+/**

+  * @}

+  */

+

+/** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition

+  * @{

+  */

+#define HAL_SMARTCARD_ERROR_NONE             ((uint32_t)0x00000000U)         /*!< No error                */

+#define HAL_SMARTCARD_ERROR_PE               ((uint32_t)0x00000001U)         /*!< Parity error            */

+#define HAL_SMARTCARD_ERROR_NE               ((uint32_t)0x00000002U)         /*!< Noise error             */

+#define HAL_SMARTCARD_ERROR_FE               ((uint32_t)0x00000004U)         /*!< frame error             */

+#define HAL_SMARTCARD_ERROR_ORE              ((uint32_t)0x00000008U)         /*!< Overrun error           */

+#define HAL_SMARTCARD_ERROR_DMA              ((uint32_t)0x00000010U)         /*!< DMA transfer error      */

+#define HAL_SMARTCARD_ERROR_RTO              ((uint32_t)0x00000020U)         /*!< Receiver TimeOut error  */

+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)

+#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)         /*!< Invalid Callback error  */

+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length

+  * @{

+  */

+#define SMARTCARD_WORDLENGTH_9B             USART_CR1_M0                    /*!< SMARTCARD frame length */

+/**

+  * @}

+  */

+

+/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits

+  * @{

+  */

+#define SMARTCARD_STOPBITS_0_5              USART_CR2_STOP_0                /*!< SMARTCARD frame with 0.5 stop bit  */

+#define SMARTCARD_STOPBITS_1_5              USART_CR2_STOP                  /*!< SMARTCARD frame with 1.5 stop bits */

+/**

+  * @}

+  */

+

+/** @defgroup SMARTCARD_Parity SMARTCARD Parity

+  * @{

+  */

+#define SMARTCARD_PARITY_EVEN               USART_CR1_PCE                   /*!< SMARTCARD frame even parity */

+#define SMARTCARD_PARITY_ODD                (USART_CR1_PCE | USART_CR1_PS)  /*!< SMARTCARD frame odd parity  */

+/**

+  * @}

+  */

+

+/** @defgroup SMARTCARD_Mode SMARTCARD Transfer Mode

+  * @{

+  */

+#define SMARTCARD_MODE_RX                   USART_CR1_RE                    /*!< SMARTCARD RX mode        */

+#define SMARTCARD_MODE_TX                   USART_CR1_TE                    /*!< SMARTCARD TX mode        */

+#define SMARTCARD_MODE_TX_RX                (USART_CR1_TE |USART_CR1_RE)    /*!< SMARTCARD RX and TX mode */

+/**

+  * @}

+  */

+

+/** @defgroup SMARTCARD_Clock_Polarity SMARTCARD Clock Polarity

+  * @{

+  */

+#define SMARTCARD_POLARITY_LOW              0x00000000U                     /*!< SMARTCARD frame low polarity  */

+#define SMARTCARD_POLARITY_HIGH             USART_CR2_CPOL                  /*!< SMARTCARD frame high polarity */

+/**

+  * @}

+  */

+

+/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase

+  * @{

+  */

+#define SMARTCARD_PHASE_1EDGE               0x00000000U                     /*!< SMARTCARD frame phase on first clock transition  */

+#define SMARTCARD_PHASE_2EDGE               USART_CR2_CPHA                  /*!< SMARTCARD frame phase on second clock transition */

+/**

+  * @}

+  */

+

+/** @defgroup SMARTCARD_Last_Bit SMARTCARD Last Bit

+  * @{

+  */

+#define SMARTCARD_LASTBIT_DISABLE           0x00000000U                     /*!< SMARTCARD frame last data bit clock pulse not output to SCLK pin */

+#define SMARTCARD_LASTBIT_ENABLE            USART_CR2_LBCL                  /*!< SMARTCARD frame last data bit clock pulse output to SCLK pin     */

+/**

+  * @}

+  */

+

+/** @defgroup SMARTCARD_OneBit_Sampling SMARTCARD One Bit Sampling Method

+  * @{

+  */

+#define SMARTCARD_ONE_BIT_SAMPLE_DISABLE    0x00000000U                     /*!< SMARTCARD frame one-bit sample disabled */

+#define SMARTCARD_ONE_BIT_SAMPLE_ENABLE     USART_CR3_ONEBIT                /*!< SMARTCARD frame one-bit sample enabled  */

+/**

+  * @}

+  */

+

+/** @defgroup SMARTCARD_NACK_Enable SMARTCARD NACK Enable

+  * @{

+  */

+#define SMARTCARD_NACK_DISABLE              0x00000000U                     /*!< SMARTCARD NACK transmission disabled  */

+#define SMARTCARD_NACK_ENABLE               USART_CR3_NACK                  /*!< SMARTCARD NACK transmission enabled */

+/**

+  * @}

+  */

+

+/** @defgroup SMARTCARD_Timeout_Enable SMARTCARD Timeout Enable

+  * @{

+  */

+#define SMARTCARD_TIMEOUT_DISABLE           0x00000000U                     /*!< SMARTCARD receiver timeout disabled */

+#define SMARTCARD_TIMEOUT_ENABLE            USART_CR2_RTOEN                 /*!< SMARTCARD receiver timeout enabled  */

+/**

+  * @}

+  */

+

+/** @defgroup SMARTCARD_ClockPrescaler  SMARTCARD Clock Prescaler

+  * @{

+  */

+#define SMARTCARD_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */

+#define SMARTCARD_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */

+#define SMARTCARD_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */

+#define SMARTCARD_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */

+#define SMARTCARD_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */

+#define SMARTCARD_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */

+#define SMARTCARD_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */

+#define SMARTCARD_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */

+#define SMARTCARD_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */

+#define SMARTCARD_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */

+#define SMARTCARD_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */

+#define SMARTCARD_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */

+/**

+  * @}

+  */

+

+/** @defgroup SMARTCARD_Tx_Inv SMARTCARD advanced feature TX pin active level inversion

+  * @{

+  */

+#define SMARTCARD_ADVFEATURE_TXINV_DISABLE  0x00000000U                  /*!< TX pin active level inversion disable */

+#define SMARTCARD_ADVFEATURE_TXINV_ENABLE   USART_CR2_TXINV              /*!< TX pin active level inversion enable  */

+/**

+  * @}

+  */

+

+/** @defgroup SMARTCARD_Rx_Inv SMARTCARD advanced feature RX pin active level inversion

+  * @{

+  */

+#define SMARTCARD_ADVFEATURE_RXINV_DISABLE  0x00000000U                  /*!< RX pin active level inversion disable */

+#define SMARTCARD_ADVFEATURE_RXINV_ENABLE   USART_CR2_RXINV              /*!< RX pin active level inversion enable  */

+/**

+  * @}

+  */

+

+/** @defgroup SMARTCARD_Data_Inv SMARTCARD advanced feature Binary Data inversion

+  * @{

+  */

+#define SMARTCARD_ADVFEATURE_DATAINV_DISABLE  0x00000000U                /*!< Binary data inversion disable */

+#define SMARTCARD_ADVFEATURE_DATAINV_ENABLE   USART_CR2_DATAINV          /*!< Binary data inversion enable  */

+/**

+  * @}

+  */

+

+/** @defgroup SMARTCARD_Rx_Tx_Swap SMARTCARD advanced feature RX TX pins swap

+  * @{

+  */

+#define SMARTCARD_ADVFEATURE_SWAP_DISABLE   0x00000000U                  /*!< TX/RX pins swap disable */

+#define SMARTCARD_ADVFEATURE_SWAP_ENABLE    USART_CR2_SWAP               /*!< TX/RX pins swap enable  */

+/**

+  * @}

+  */

+

+/** @defgroup SMARTCARD_Overrun_Disable SMARTCARD advanced feature Overrun Disable

+  * @{

+  */

+#define SMARTCARD_ADVFEATURE_OVERRUN_ENABLE   0x00000000U                /*!< RX overrun enable  */

+#define SMARTCARD_ADVFEATURE_OVERRUN_DISABLE  USART_CR3_OVRDIS           /*!< RX overrun disable */

+/**

+  * @}

+  */

+

+/** @defgroup SMARTCARD_DMA_Disable_on_Rx_Error SMARTCARD advanced feature DMA Disable on Rx Error

+  * @{

+  */

+#define SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR   0x00000000U           /*!< DMA enable on Reception Error  */

+#define SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR  USART_CR3_DDRE        /*!< DMA disable on Reception Error */

+/**

+  * @}

+  */

+

+/** @defgroup SMARTCARD_MSB_First   SMARTCARD advanced feature MSB first

+  * @{

+  */

+#define SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE      0x00000000U           /*!< Most significant bit sent/received first disable */

+#define SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE       USART_CR2_MSBFIRST    /*!< Most significant bit sent/received first enable  */

+/**

+  * @}

+  */

+

+/** @defgroup SMARTCARD_Request_Parameters SMARTCARD Request Parameters

+  * @{

+  */

+#define SMARTCARD_RXDATA_FLUSH_REQUEST      USART_RQR_RXFRQ              /*!< Receive data flush request */

+#define SMARTCARD_TXDATA_FLUSH_REQUEST      USART_RQR_TXFRQ              /*!< Transmit data flush request */

+/**

+  * @}

+  */

+

+/** @defgroup SMARTCARD_Interruption_Mask SMARTCARD interruptions flags mask

+  * @{

+  */

+#define SMARTCARD_IT_MASK                   0x001FU   /*!< SMARTCARD interruptions flags mask  */

+#define SMARTCARD_CR_MASK                   0x00E0U   /*!< SMARTCARD control register mask     */

+#define SMARTCARD_CR_POS                    5U        /*!< SMARTCARD control register position */

+#define SMARTCARD_ISR_MASK                  0x1F00U   /*!< SMARTCARD ISR register mask         */

+#define SMARTCARD_ISR_POS                   8U        /*!< SMARTCARD ISR register position     */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macros -----------------------------------------------------------*/

+/** @defgroup SMARTCARD_Exported_Macros  SMARTCARD Exported Macros

+  * @{

+  */

+

+/** @brief  Reset SMARTCARD handle states.

+  * @param  __HANDLE__ SMARTCARD handle.

+  * @retval None

+  */

+#if USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1

+#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                       \

+                                                            (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;     \

+                                                            (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;    \

+                                                            (__HANDLE__)->MspInitCallback = NULL;                 \

+                                                            (__HANDLE__)->MspDeInitCallback = NULL;               \

+                                                          } while(0U)

+#else

+#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__)  do{                                                       \

+                                                            (__HANDLE__)->gState = HAL_SMARTCARD_STATE_RESET;     \

+                                                            (__HANDLE__)->RxState = HAL_SMARTCARD_STATE_RESET;    \

+                                                          } while(0U)

+#endif /*USE_HAL_SMARTCARD_REGISTER_CALLBACKS  */

+

+/** @brief  Flush the Smartcard Data registers.

+  * @param  __HANDLE__ specifies the SMARTCARD Handle.

+  * @retval None

+  */

+#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__)                      \

+  do{                                                                     \

+    SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_RXDATA_FLUSH_REQUEST); \

+    SET_BIT((__HANDLE__)->Instance->RQR, SMARTCARD_TXDATA_FLUSH_REQUEST); \

+  } while(0U)

+

+/** @brief  Clear the specified SMARTCARD pending flag.

+  * @param  __HANDLE__ specifies the SMARTCARD Handle.

+  * @param  __FLAG__ specifies the flag to check.

+  *          This parameter can be any combination of the following values:

+  *            @arg @ref SMARTCARD_CLEAR_PEF    Parity error clear flag

+  *            @arg @ref SMARTCARD_CLEAR_FEF    Framing error clear flag

+  *            @arg @ref SMARTCARD_CLEAR_NEF    Noise detected clear flag

+  *            @arg @ref SMARTCARD_CLEAR_OREF   OverRun error clear flag

+  *            @arg @ref SMARTCARD_CLEAR_IDLEF  Idle line detected clear flag

+  *            @arg @ref SMARTCARD_CLEAR_TCF    Transmission complete clear flag

+  *            @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag

+  *            @arg @ref SMARTCARD_CLEAR_RTOF   Receiver timeout clear flag

+  *            @arg @ref SMARTCARD_CLEAR_EOBF   End of block clear flag

+  *            @arg @ref SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear flag

+  * @retval None

+  */

+#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))

+

+/** @brief  Clear the SMARTCARD PE pending flag.

+  * @param  __HANDLE__ specifies the SMARTCARD Handle.

+  * @retval None

+  */

+#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)

+

+/** @brief  Clear the SMARTCARD FE pending flag.

+  * @param  __HANDLE__ specifies the SMARTCARD Handle.

+  * @retval None

+  */

+#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)

+

+/** @brief  Clear the SMARTCARD NE pending flag.

+  * @param  __HANDLE__ specifies the SMARTCARD Handle.

+  * @retval None

+  */

+#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)

+

+/** @brief  Clear the SMARTCARD ORE pending flag.

+  * @param  __HANDLE__ specifies the SMARTCARD Handle.

+  * @retval None

+  */

+#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)

+

+/** @brief  Clear the SMARTCARD IDLE pending flag.

+  * @param  __HANDLE__ specifies the SMARTCARD Handle.

+  * @retval None

+  */

+#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)

+

+/** @brief  Check whether the specified Smartcard flag is set or not.

+  * @param  __HANDLE__ specifies the SMARTCARD Handle.

+  * @param  __FLAG__ specifies the flag to check.

+  *        This parameter can be one of the following values:

+  *            @arg @ref SMARTCARD_FLAG_TCBGT Transmission complete before guard time flag (when flag available)

+  *            @arg @ref SMARTCARD_FLAG_REACK Receive enable acknowledge flag

+  *            @arg @ref SMARTCARD_FLAG_TEACK Transmit enable acknowledge flag

+  *            @arg @ref SMARTCARD_FLAG_BUSY  Busy flag

+  *            @arg @ref SMARTCARD_FLAG_EOBF  End of block flag

+  *            @arg @ref SMARTCARD_FLAG_RTOF  Receiver timeout flag

+  *            @arg @ref SMARTCARD_FLAG_TXE   Transmit data register empty flag

+  *            @arg @ref SMARTCARD_FLAG_TC    Transmission complete flag

+  *            @arg @ref SMARTCARD_FLAG_RXNE  Receive data register not empty flag

+  *            @arg @ref SMARTCARD_FLAG_IDLE  Idle line detection flag

+  *            @arg @ref SMARTCARD_FLAG_ORE   Overrun error flag

+  *            @arg @ref SMARTCARD_FLAG_NE    Noise error flag

+  *            @arg @ref SMARTCARD_FLAG_FE    Framing error flag

+  *            @arg @ref SMARTCARD_FLAG_PE    Parity error flag

+  *            @arg @ref SMARTCARD_FLAG_TXFNF TXFIFO not full flag

+  *            @arg @ref SMARTCARD_FLAG_RXFNE RXFIFO not empty flag

+  *            @arg @ref SMARTCARD_FLAG_TXFE  TXFIFO Empty flag

+  *            @arg @ref SMARTCARD_FLAG_RXFF  RXFIFO Full flag

+  *            @arg @ref SMARTCARD_FLAG_RXFT  SMARTCARD RXFIFO threshold flag

+  *            @arg @ref SMARTCARD_FLAG_TXFT  SMARTCARD TXFIFO threshold flag

+  * @retval The new state of __FLAG__ (TRUE or FALSE).

+  */

+#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

+

+/** @brief  Enable the specified SmartCard interrupt.

+  * @param  __HANDLE__ specifies the SMARTCARD Handle.

+  * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to enable.

+  *          This parameter can be one of the following values:

+  *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt

+  *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt

+  *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt

+  *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt

+  *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before guard time interrupt (when interruption available)

+  *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt

+  *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt

+  *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt

+  *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)

+  *            @arg @ref SMARTCARD_IT_TXFNF  TX FIFO not full interruption

+  *            @arg @ref SMARTCARD_IT_RXFNE  RXFIFO not empty interruption

+  *            @arg @ref SMARTCARD_IT_RXFF   RXFIFO full interruption

+  *            @arg @ref SMARTCARD_IT_TXFE   TXFIFO empty interruption

+  *            @arg @ref SMARTCARD_IT_RXFT   RXFIFO threshold reached interruption

+  *            @arg @ref SMARTCARD_IT_TXFT   TXFIFO threshold reached interruption

+  * @retval None

+  */

+#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \

+                                                                ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \

+                                                                ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))

+

+/** @brief  Disable the specified SmartCard interrupt.

+  * @param  __HANDLE__ specifies the SMARTCARD Handle.

+  * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to disable.

+  *          This parameter can be one of the following values:

+  *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt

+  *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt

+  *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt

+  *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt

+  *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before guard time interrupt (when interruption available)

+  *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt

+  *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt

+  *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt

+  *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)

+  *            @arg @ref SMARTCARD_IT_TXFNF  TX FIFO not full interruption

+  *            @arg @ref SMARTCARD_IT_RXFNE  RXFIFO not empty interruption

+  *            @arg @ref SMARTCARD_IT_RXFF   RXFIFO full interruption

+  *            @arg @ref SMARTCARD_IT_TXFE   TXFIFO empty interruption

+  *            @arg @ref SMARTCARD_IT_RXFT   RXFIFO threshold reached interruption

+  *            @arg @ref SMARTCARD_IT_TXFT   TXFIFO threshold reached interruption

+  * @retval None

+  */

+#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \

+                                                                ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \

+                                                                ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))

+

+/** @brief  Check whether the specified SmartCard interrupt has occurred or not.

+  * @param  __HANDLE__ specifies the SMARTCARD Handle.

+  * @param  __INTERRUPT__ specifies the SMARTCARD interrupt to check.

+  *          This parameter can be one of the following values:

+  *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt

+  *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt

+  *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt

+  *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt

+  *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before guard time interrupt (when interruption available)

+  *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt

+  *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt

+  *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt

+  *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)

+  *            @arg @ref SMARTCARD_IT_TXFNF  TX FIFO not full interruption

+  *            @arg @ref SMARTCARD_IT_RXFNE  RXFIFO not empty interruption

+  *            @arg @ref SMARTCARD_IT_RXFF   RXFIFO full interruption

+  *            @arg @ref SMARTCARD_IT_TXFE   TXFIFO empty interruption

+  *            @arg @ref SMARTCARD_IT_RXFT   RXFIFO threshold reached interruption

+  *            @arg @ref SMARTCARD_IT_TXFT   TXFIFO threshold reached interruption

+  * @retval The new state of __INTERRUPT__ (SET or RESET).

+  */

+#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\

+                                                             & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET)

+

+/** @brief  Check whether the specified SmartCard interrupt source is enabled or not.

+  * @param  __HANDLE__ specifies the SMARTCARD Handle.

+  * @param  __INTERRUPT__ specifies the SMARTCARD interrupt source to check.

+  *          This parameter can be one of the following values:

+  *            @arg @ref SMARTCARD_IT_EOB    End of block interrupt

+  *            @arg @ref SMARTCARD_IT_RTO    Receive timeout interrupt

+  *            @arg @ref SMARTCARD_IT_TXE    Transmit data register empty interrupt

+  *            @arg @ref SMARTCARD_IT_TC     Transmission complete interrupt

+  *            @arg @ref SMARTCARD_IT_TCBGT  Transmission complete before guard time interrupt (when interruption available)

+  *            @arg @ref SMARTCARD_IT_RXNE   Receive data register not empty interrupt

+  *            @arg @ref SMARTCARD_IT_IDLE   Idle line detection interrupt

+  *            @arg @ref SMARTCARD_IT_PE     Parity error interrupt

+  *            @arg @ref SMARTCARD_IT_ERR    Error interrupt(frame error, noise error, overrun error)

+  *            @arg @ref SMARTCARD_IT_TXFNF  TX FIFO not full interruption

+  *            @arg @ref SMARTCARD_IT_RXFNE  RXFIFO not empty interruption

+  *            @arg @ref SMARTCARD_IT_RXFF   RXFIFO full interruption

+  *            @arg @ref SMARTCARD_IT_TXFE   TXFIFO empty interruption

+  *            @arg @ref SMARTCARD_IT_RXFT   RXFIFO threshold reached interruption

+  *            @arg @ref SMARTCARD_IT_TXFT   TXFIFO threshold reached interruption

+  * @retval The new state of __INTERRUPT__ (SET or RESET).

+  */

+#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \

+                                                                     (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \

+                                                                      (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK)))  != 0U) ? SET : RESET)

+

+/** @brief  Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag.

+  * @param  __HANDLE__ specifies the SMARTCARD Handle.

+  * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set

+  *                       to clear the corresponding interrupt.

+  *          This parameter can be one of the following values:

+  *            @arg @ref SMARTCARD_CLEAR_PEF    Parity error clear flag

+  *            @arg @ref SMARTCARD_CLEAR_FEF    Framing error clear flag

+  *            @arg @ref SMARTCARD_CLEAR_NEF    Noise detected clear flag

+  *            @arg @ref SMARTCARD_CLEAR_OREF   OverRun error clear flag

+  *            @arg @ref SMARTCARD_CLEAR_IDLEF  Idle line detection clear flag

+  *            @arg @ref SMARTCARD_CLEAR_TXFECF TXFIFO empty Clear Flag

+  *            @arg @ref SMARTCARD_CLEAR_TCF    Transmission complete clear flag

+  *            @arg @ref SMARTCARD_CLEAR_TCBGTF Transmission complete before guard time clear flag (when flag available)

+  *            @arg @ref SMARTCARD_CLEAR_RTOF   Receiver timeout clear flag

+  *            @arg @ref SMARTCARD_CLEAR_EOBF   End of block clear flag

+  * @retval None

+  */

+#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))

+

+/** @brief  Set a specific SMARTCARD request flag.

+  * @param  __HANDLE__ specifies the SMARTCARD Handle.

+  * @param  __REQ__ specifies the request flag to set

+  *          This parameter can be one of the following values:

+  *            @arg @ref SMARTCARD_RXDATA_FLUSH_REQUEST Receive data flush Request

+  *            @arg @ref SMARTCARD_TXDATA_FLUSH_REQUEST Transmit data flush Request

+  * @retval None

+  */

+#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))

+

+/** @brief  Enable the SMARTCARD one bit sample method.

+  * @param  __HANDLE__ specifies the SMARTCARD Handle.

+  * @retval None

+  */

+#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

+

+/** @brief  Disable the SMARTCARD one bit sample method.

+  * @param  __HANDLE__ specifies the SMARTCARD Handle.

+  * @retval None

+  */

+#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3\

+                                                            &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))

+

+/** @brief  Enable the USART associated to the SMARTCARD Handle.

+  * @param  __HANDLE__ specifies the SMARTCARD Handle.

+  * @retval None

+  */

+#define __HAL_SMARTCARD_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)

+

+/** @brief  Disable the USART associated to the SMARTCARD Handle

+  * @param  __HANDLE__ specifies the SMARTCARD Handle.

+  * @retval None

+  */

+#define __HAL_SMARTCARD_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)

+

+/**

+  * @}

+  */

+

+/* Private macros -------------------------------------------------------------*/

+/** @defgroup SMARTCARD_Private_Macros SMARTCARD Private Macros

+  * @{

+  */

+

+/** @brief  Report the SMARTCARD clock source.

+  * @param  __HANDLE__ specifies the SMARTCARD Handle.

+  * @param  __CLOCKSOURCE__ output variable.

+  * @retval the SMARTCARD clocking source, written in __CLOCKSOURCE__.

+  */

+#if defined(UART9) && defined(USART10)

+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)   \

+  do {                                                         \

+    if ((__HANDLE__)->Instance == USART1)                      \

+    {                                                          \

+      switch (__HAL_RCC_GET_USART1_SOURCE())                   \

+      {                                                        \

+        case RCC_USART1CLKSOURCE_D2PCLK2:                      \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK2;   \

+          break;                                               \

+        case RCC_USART1CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q;     \

+          break;                                               \

+        case RCC_USART1CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q;     \

+          break;                                               \

+        case RCC_USART1CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \

+          break;                                               \

+        case RCC_USART1CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI;       \

+          break;                                               \

+        case RCC_USART1CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \

+          break;                                               \

+        default:                                               \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \

+          break;                                               \

+      }                                                        \

+    }                                                          \

+    else if ((__HANDLE__)->Instance == USART2)                 \

+    {                                                          \

+      switch (__HAL_RCC_GET_USART2_SOURCE())                   \

+      {                                                        \

+        case RCC_USART2CLKSOURCE_D2PCLK1:                      \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK1;   \

+          break;                                               \

+        case RCC_USART2CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q;     \

+          break;                                               \

+        case RCC_USART2CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q;     \

+          break;                                               \

+        case RCC_USART2CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \

+          break;                                               \

+        case RCC_USART2CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI;       \

+          break;                                               \

+        case RCC_USART2CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \

+          break;                                               \

+        default:                                               \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \

+          break;                                               \

+      }                                                        \

+    }                                                          \

+    else if ((__HANDLE__)->Instance == USART3)                 \

+    {                                                          \

+      switch (__HAL_RCC_GET_USART3_SOURCE())                   \

+      {                                                        \

+        case RCC_USART3CLKSOURCE_D2PCLK1:                      \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK1;   \

+          break;                                               \

+        case RCC_USART3CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q;     \

+          break;                                               \

+        case RCC_USART3CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q;     \

+          break;                                               \

+        case RCC_USART3CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \

+          break;                                               \

+        case RCC_USART3CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI;       \

+          break;                                               \

+        case RCC_USART3CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \

+          break;                                               \

+        default:                                               \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \

+          break;                                               \

+      }                                                        \

+    }                                                          \

+    else if ((__HANDLE__)->Instance == USART6)                 \

+    {                                                          \

+      switch (__HAL_RCC_GET_USART6_SOURCE())                   \

+      {                                                        \

+        case RCC_USART6CLKSOURCE_D2PCLK2:                      \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK2;   \

+          break;                                               \

+        case RCC_USART6CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q;     \

+          break;                                               \

+        case RCC_USART6CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q;     \

+          break;                                               \

+        case RCC_USART6CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \

+          break;                                               \

+        case RCC_USART6CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI;       \

+          break;                                               \

+        case RCC_USART6CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \

+          break;                                               \

+        default:                                               \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \

+          break;                                               \

+      }                                                        \

+    }                                                          \

+    else if ((__HANDLE__)->Instance == USART10)                \

+    {                                                          \

+      switch (__HAL_RCC_GET_USART10_SOURCE())                  \

+      {                                                        \

+        case RCC_USART10CLKSOURCE_D2PCLK2:                     \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK2;   \

+          break;                                               \

+        case RCC_USART10CLKSOURCE_PLL2:                        \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q;     \

+          break;                                               \

+        case RCC_USART10CLKSOURCE_PLL3:                        \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q;     \

+          break;                                               \

+        case RCC_USART10CLKSOURCE_HSI:                         \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \

+          break;                                               \

+        case RCC_USART10CLKSOURCE_CSI:                         \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI;       \

+          break;                                               \

+        case RCC_USART10CLKSOURCE_LSE:                         \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \

+          break;                                               \

+        default:                                               \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \

+          break;                                               \

+      }                                                        \

+    }                                                          \

+    else                                                       \

+    {                                                          \

+      (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED;     \

+    }                                                          \

+  } while(0U)

+#else

+#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)   \

+  do {                                                         \

+    if ((__HANDLE__)->Instance == USART1)                      \

+    {                                                          \

+      switch (__HAL_RCC_GET_USART1_SOURCE())                   \

+      {                                                        \

+        case RCC_USART1CLKSOURCE_D2PCLK2:                      \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK2;   \

+          break;                                               \

+        case RCC_USART1CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q;     \

+          break;                                               \

+        case RCC_USART1CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q;     \

+          break;                                               \

+        case RCC_USART1CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \

+          break;                                               \

+        case RCC_USART1CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI;       \

+          break;                                               \

+        case RCC_USART1CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \

+          break;                                               \

+        default:                                               \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \

+          break;                                               \

+      }                                                        \

+    }                                                          \

+    else if ((__HANDLE__)->Instance == USART2)                 \

+    {                                                          \

+      switch (__HAL_RCC_GET_USART2_SOURCE())                   \

+      {                                                        \

+        case RCC_USART2CLKSOURCE_D2PCLK1:                      \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK1;   \

+          break;                                               \

+        case RCC_USART2CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q;    \

+          break;                                               \

+        case RCC_USART2CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q;     \

+          break;                                               \

+        case RCC_USART2CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \

+          break;                                               \

+        case RCC_USART2CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI;       \

+          break;                                               \

+        case RCC_USART2CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \

+          break;                                               \

+        default:                                               \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \

+          break;                                               \

+      }                                                        \

+    }                                                          \

+    else if ((__HANDLE__)->Instance == USART3)                 \

+    {                                                          \

+      switch (__HAL_RCC_GET_USART3_SOURCE())                   \

+      {                                                        \

+        case RCC_USART3CLKSOURCE_D2PCLK1:                      \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK1;   \

+          break;                                               \

+        case RCC_USART3CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q;     \

+          break;                                               \

+        case RCC_USART3CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q;     \

+          break;                                               \

+        case RCC_USART3CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \

+          break;                                               \

+        case RCC_USART3CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI;       \

+          break;                                               \

+        case RCC_USART3CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \

+          break;                                               \

+        default:                                               \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \

+          break;                                               \

+      }                                                        \

+    }                                                          \

+    else if ((__HANDLE__)->Instance == USART6)                 \

+    {                                                          \

+      switch (__HAL_RCC_GET_USART6_SOURCE())                   \

+      {                                                        \

+        case RCC_USART6CLKSOURCE_D2PCLK2:                      \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_D2PCLK2;   \

+          break;                                               \

+        case RCC_USART6CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL2Q;     \

+          break;                                               \

+        case RCC_USART6CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_PLL3Q;     \

+          break;                                               \

+        case RCC_USART6CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_HSI;       \

+          break;                                               \

+        case RCC_USART6CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_CSI;       \

+          break;                                               \

+        case RCC_USART6CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_LSE;       \

+          break;                                               \

+        default:                                               \

+          (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED; \

+          break;                                               \

+      }                                                        \

+    }                                                          \

+    else                                                       \

+    {                                                          \

+      (__CLOCKSOURCE__) = SMARTCARD_CLOCKSOURCE_UNDEFINED;     \

+    }                                                          \

+  } while(0U)

+#endif /* UART9 && USART10 */

+

+/** @brief  Check the Baud rate range.

+  * @note   The maximum Baud Rate is derived from the maximum clock on H7 (100 MHz)

+  *         divided by the oversampling used on the SMARTCARD (i.e. 16).

+  * @param  __BAUDRATE__ Baud rate set by the configuration function.

+  * @retval Test result (TRUE or FALSE)

+  */

+#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 6250001U)

+

+/** @brief  Check the block length range.

+  * @note   The maximum SMARTCARD block length is 0xFF.

+  * @param  __LENGTH__ block length.

+  * @retval Test result (TRUE or FALSE)

+  */

+#define IS_SMARTCARD_BLOCKLENGTH(__LENGTH__) ((__LENGTH__) <= 0xFFU)

+

+/** @brief  Check the receiver timeout value.

+  * @note   The maximum SMARTCARD receiver timeout value is 0xFFFFFF.

+  * @param  __TIMEOUTVALUE__ receiver timeout value.

+  * @retval Test result (TRUE or FALSE)

+  */

+#define IS_SMARTCARD_TIMEOUT_VALUE(__TIMEOUTVALUE__)    ((__TIMEOUTVALUE__) <= 0xFFFFFFU)

+

+/** @brief  Check the SMARTCARD autoretry counter value.

+  * @note   The maximum number of retransmissions is 0x7.

+  * @param  __COUNT__ number of retransmissions.

+  * @retval Test result (TRUE or FALSE)

+  */

+#define IS_SMARTCARD_AUTORETRY_COUNT(__COUNT__)         ((__COUNT__) <= 0x7U)

+

+/** @brief Ensure that SMARTCARD frame length is valid.

+  * @param __LENGTH__ SMARTCARD frame length.

+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

+  */

+#define IS_SMARTCARD_WORD_LENGTH(__LENGTH__) ((__LENGTH__) == SMARTCARD_WORDLENGTH_9B)

+

+/** @brief Ensure that SMARTCARD frame number of stop bits is valid.

+  * @param __STOPBITS__ SMARTCARD frame number of stop bits.

+  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)

+  */

+#define IS_SMARTCARD_STOPBITS(__STOPBITS__) (((__STOPBITS__) == SMARTCARD_STOPBITS_0_5) ||\

+                                             ((__STOPBITS__) == SMARTCARD_STOPBITS_1_5))

+

+/** @brief Ensure that SMARTCARD frame parity is valid.

+  * @param __PARITY__ SMARTCARD frame parity.

+  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

+  */

+#define IS_SMARTCARD_PARITY(__PARITY__) (((__PARITY__) == SMARTCARD_PARITY_EVEN) || \

+                                         ((__PARITY__) == SMARTCARD_PARITY_ODD))

+

+/** @brief Ensure that SMARTCARD communication mode is valid.

+  * @param __MODE__ SMARTCARD communication mode.

+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

+  */

+#define IS_SMARTCARD_MODE(__MODE__) ((((__MODE__) & 0xFFF3U) == 0x00U) && ((__MODE__) != 0x00U))

+

+/** @brief Ensure that SMARTCARD frame polarity is valid.

+  * @param __CPOL__ SMARTCARD frame polarity.

+  * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)

+  */

+#define IS_SMARTCARD_POLARITY(__CPOL__) (((__CPOL__) == SMARTCARD_POLARITY_LOW)\

+                                         || ((__CPOL__) == SMARTCARD_POLARITY_HIGH))

+

+/** @brief Ensure that SMARTCARD frame phase is valid.

+  * @param __CPHA__ SMARTCARD frame phase.

+  * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)

+  */

+#define IS_SMARTCARD_PHASE(__CPHA__) (((__CPHA__) == SMARTCARD_PHASE_1EDGE) || ((__CPHA__) == SMARTCARD_PHASE_2EDGE))

+

+/** @brief Ensure that SMARTCARD frame last bit clock pulse setting is valid.

+  * @param __LASTBIT__ SMARTCARD frame last bit clock pulse setting.

+  * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)

+  */

+#define IS_SMARTCARD_LASTBIT(__LASTBIT__) (((__LASTBIT__) == SMARTCARD_LASTBIT_DISABLE) || \

+                                           ((__LASTBIT__) == SMARTCARD_LASTBIT_ENABLE))

+

+/** @brief Ensure that SMARTCARD frame sampling is valid.

+  * @param __ONEBIT__ SMARTCARD frame sampling.

+  * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)

+  */

+#define IS_SMARTCARD_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_DISABLE) || \

+                                                 ((__ONEBIT__) == SMARTCARD_ONE_BIT_SAMPLE_ENABLE))

+

+/** @brief Ensure that SMARTCARD NACK transmission setting is valid.

+  * @param __NACK__ SMARTCARD NACK transmission setting.

+  * @retval SET (__NACK__ is valid) or RESET (__NACK__ is invalid)

+  */

+#define IS_SMARTCARD_NACK(__NACK__) (((__NACK__) == SMARTCARD_NACK_ENABLE) || \

+                                     ((__NACK__) == SMARTCARD_NACK_DISABLE))

+

+/** @brief Ensure that SMARTCARD receiver timeout setting is valid.

+  * @param __TIMEOUT__ SMARTCARD receiver timeout setting.

+  * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)

+  */

+#define IS_SMARTCARD_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == SMARTCARD_TIMEOUT_DISABLE) || \

+                                           ((__TIMEOUT__) == SMARTCARD_TIMEOUT_ENABLE))

+

+/** @brief Ensure that SMARTCARD clock Prescaler is valid.

+  * @param __CLOCKPRESCALER__ SMARTCARD clock Prescaler value.

+  * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)

+  */

+#define IS_SMARTCARD_CLOCKPRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV1)   || \

+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV2)   || \

+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV4)   || \

+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV6)   || \

+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV8)   || \

+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV10)  || \

+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV12)  || \

+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV16)  || \

+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV32)  || \

+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV64)  || \

+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV128) || \

+                                                         ((__CLOCKPRESCALER__) == SMARTCARD_PRESCALER_DIV256))

+

+/** @brief Ensure that SMARTCARD advanced features initialization is valid.

+  * @param __INIT__ SMARTCARD advanced features initialization.

+  * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)

+  */

+#define IS_SMARTCARD_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (SMARTCARD_ADVFEATURE_NO_INIT                | \

+                                                               SMARTCARD_ADVFEATURE_TXINVERT_INIT          | \

+                                                               SMARTCARD_ADVFEATURE_RXINVERT_INIT          | \

+                                                               SMARTCARD_ADVFEATURE_DATAINVERT_INIT        | \

+                                                               SMARTCARD_ADVFEATURE_SWAP_INIT              | \

+                                                               SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \

+                                                               SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT | \

+                                                               SMARTCARD_ADVFEATURE_MSBFIRST_INIT))

+

+/** @brief Ensure that SMARTCARD frame TX inversion setting is valid.

+  * @param __TXINV__ SMARTCARD frame TX inversion setting.

+  * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)

+  */

+#define IS_SMARTCARD_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_DISABLE) || \

+                                                  ((__TXINV__) == SMARTCARD_ADVFEATURE_TXINV_ENABLE))

+

+/** @brief Ensure that SMARTCARD frame RX inversion setting is valid.

+  * @param __RXINV__ SMARTCARD frame RX inversion setting.

+  * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)

+  */

+#define IS_SMARTCARD_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_DISABLE) || \

+                                                  ((__RXINV__) == SMARTCARD_ADVFEATURE_RXINV_ENABLE))

+

+/** @brief Ensure that SMARTCARD frame data inversion setting is valid.

+  * @param __DATAINV__ SMARTCARD frame data inversion setting.

+  * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)

+  */

+#define IS_SMARTCARD_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_DISABLE) || \

+                                                      ((__DATAINV__) == SMARTCARD_ADVFEATURE_DATAINV_ENABLE))

+

+/** @brief Ensure that SMARTCARD frame RX/TX pins swap setting is valid.

+  * @param __SWAP__ SMARTCARD frame RX/TX pins swap setting.

+  * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)

+  */

+#define IS_SMARTCARD_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_DISABLE) || \

+                                                ((__SWAP__) == SMARTCARD_ADVFEATURE_SWAP_ENABLE))

+

+/** @brief Ensure that SMARTCARD frame overrun setting is valid.

+  * @param __OVERRUN__ SMARTCARD frame overrun setting.

+  * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)

+  */

+#define IS_SMARTCARD_OVERRUN(__OVERRUN__) (((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_ENABLE) || \

+                                           ((__OVERRUN__) == SMARTCARD_ADVFEATURE_OVERRUN_DISABLE))

+

+/** @brief Ensure that SMARTCARD DMA enabling or disabling on error setting is valid.

+  * @param __DMA__ SMARTCARD DMA enabling or disabling on error setting.

+  * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)

+  */

+#define IS_SMARTCARD_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == SMARTCARD_ADVFEATURE_DMA_ENABLEONRXERROR) || \

+                                                       ((__DMA__) == SMARTCARD_ADVFEATURE_DMA_DISABLEONRXERROR))

+

+/** @brief Ensure that SMARTCARD frame MSB first setting is valid.

+  * @param __MSBFIRST__ SMARTCARD frame MSB first setting.

+  * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)

+  */

+#define IS_SMARTCARD_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_DISABLE) || \

+                                                        ((__MSBFIRST__) == SMARTCARD_ADVFEATURE_MSBFIRST_ENABLE))

+

+/** @brief Ensure that SMARTCARD request parameter is valid.

+  * @param __PARAM__ SMARTCARD request parameter.

+  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

+  */

+#define IS_SMARTCARD_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == SMARTCARD_RXDATA_FLUSH_REQUEST) || \

+                                                   ((__PARAM__) == SMARTCARD_TXDATA_FLUSH_REQUEST))

+

+/**

+  * @}

+  */

+

+/* Include SMARTCARD HAL Extended module */

+#include "stm32h7xx_hal_smartcard_ex.h"

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup SMARTCARD_Exported_Functions

+  * @{

+  */

+

+/* Initialization and de-initialization functions  ****************************/

+/** @addtogroup SMARTCARD_Exported_Functions_Group1

+  * @{

+  */

+

+HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsmartcard);

+HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsmartcard);

+void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsmartcard);

+void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard);

+

+#if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1)

+/* Callbacks Register/UnRegister functions  ***********************************/

+HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,

+                                                 HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard,

+                                                   HAL_SMARTCARD_CallbackIDTypeDef CallbackID);

+#endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+/* IO operation functions *****************************************************/

+/** @addtogroup SMARTCARD_Exported_Functions_Group2

+  * @{

+  */

+

+HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,

+                                         uint32_t Timeout);

+HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size,

+                                        uint32_t Timeout);

+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t *pData, uint16_t Size);

+/* Transfer Abort functions */

+HAL_StatusTypeDef HAL_SMARTCARD_Abort(SMARTCARD_HandleTypeDef *hsmartcard);

+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit(SMARTCARD_HandleTypeDef *hsmartcard);

+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive(SMARTCARD_HandleTypeDef *hsmartcard);

+HAL_StatusTypeDef HAL_SMARTCARD_Abort_IT(SMARTCARD_HandleTypeDef *hsmartcard);

+HAL_StatusTypeDef HAL_SMARTCARD_AbortTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);

+HAL_StatusTypeDef HAL_SMARTCARD_AbortReceive_IT(SMARTCARD_HandleTypeDef *hsmartcard);

+

+void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsmartcard);

+void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);

+void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);

+void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsmartcard);

+void HAL_SMARTCARD_AbortCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);

+void HAL_SMARTCARD_AbortTransmitCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);

+void HAL_SMARTCARD_AbortReceiveCpltCallback(SMARTCARD_HandleTypeDef *hsmartcard);

+

+/**

+  * @}

+  */

+

+/* Peripheral State and Error functions ***************************************/

+/** @addtogroup SMARTCARD_Exported_Functions_Group4

+  * @{

+  */

+

+HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsmartcard);

+uint32_t                   HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsmartcard);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_SMARTCARD_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_smartcard_ex.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_smartcard_ex.h
new file mode 100644
index 0000000000..3b408ff52e
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_smartcard_ex.h
@@ -0,0 +1,338 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_smartcard_ex.h

+  * @author  MCD Application Team

+  * @brief   Header file of SMARTCARD HAL Extended module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_SMARTCARD_EX_H

+#define STM32H7xx_HAL_SMARTCARD_EX_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup SMARTCARDEx

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/* Exported constants --------------------------------------------------------*/

+

+/** @addtogroup SMARTCARDEx_Exported_Constants  SMARTCARD Extended Exported Constants

+  * @{

+  */

+

+/** @defgroup SMARTCARDEx_Transmission_Completion_Indication SMARTCARD Transmission Completion Indication

+  * @{

+  */

+#define SMARTCARD_TCBGT      SMARTCARD_IT_TCBGT /*!< SMARTCARD transmission complete before guard time */

+#define SMARTCARD_TC         SMARTCARD_IT_TC    /*!< SMARTCARD transmission complete (flag raised when guard time has elapsed) */

+/**

+  * @}

+  */

+

+/** @defgroup SMARTCARDEx_Advanced_Features_Initialization_Type SMARTCARD advanced feature initialization type

+  * @{

+  */

+#define SMARTCARD_ADVFEATURE_NO_INIT                 0x00000000U    /*!< No advanced feature initialization                  */

+#define SMARTCARD_ADVFEATURE_TXINVERT_INIT           0x00000001U    /*!< TX pin active level inversion                       */

+#define SMARTCARD_ADVFEATURE_RXINVERT_INIT           0x00000002U    /*!< RX pin active level inversion                       */

+#define SMARTCARD_ADVFEATURE_DATAINVERT_INIT         0x00000004U    /*!< Binary data inversion                               */

+#define SMARTCARD_ADVFEATURE_SWAP_INIT               0x00000008U    /*!< TX/RX pins swap                                     */

+#define SMARTCARD_ADVFEATURE_RXOVERRUNDISABLE_INIT   0x00000010U    /*!< RX overrun disable                                  */

+#define SMARTCARD_ADVFEATURE_DMADISABLEONERROR_INIT  0x00000020U    /*!< DMA disable on Reception Error                      */

+#define SMARTCARD_ADVFEATURE_MSBFIRST_INIT           0x00000080U    /*!< Most significant bit sent/received first            */

+#define SMARTCARD_ADVFEATURE_TXCOMPLETION            0x00000100U    /*!< TX completion indication before of after guard time */

+/**

+  * @}

+  */

+

+/** @defgroup SMARTCARDEx_FIFO_mode SMARTCARD FIFO mode

+  * @brief    SMARTCARD FIFO mode

+  * @{

+  */

+#define SMARTCARD_FIFOMODE_DISABLE        0x00000000U                   /*!< FIFO mode disable */

+#define SMARTCARD_FIFOMODE_ENABLE         USART_CR1_FIFOEN              /*!< FIFO mode enable  */

+/**

+  * @}

+  */

+

+/** @defgroup SMARTCARDEx_TXFIFO_threshold_level SMARTCARD TXFIFO threshold level

+  * @brief    SMARTCARD TXFIFO level

+  * @{

+  */

+#define SMARTCARD_TXFIFO_THRESHOLD_1_8    0x00000000U                               /*!< TXFIFO reaches 1/8 of its depth */

+#define SMARTCARD_TXFIFO_THRESHOLD_1_4   USART_CR3_TXFTCFG_0                        /*!< TXFIFO reaches 1/4 of its depth */

+#define SMARTCARD_TXFIFO_THRESHOLD_1_2   USART_CR3_TXFTCFG_1                        /*!< TXFIFO reaches 1/2 of its depth */

+#define SMARTCARD_TXFIFO_THRESHOLD_3_4   (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1)  /*!< TXFIFO reaches 3/4 of its depth */

+#define SMARTCARD_TXFIFO_THRESHOLD_7_8   USART_CR3_TXFTCFG_2                        /*!< TXFIFO reaches 7/8 of its depth */

+#define SMARTCARD_TXFIFO_THRESHOLD_8_8   (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0)  /*!< TXFIFO becomes empty            */

+/**

+  * @}

+  */

+

+/** @defgroup SMARTCARDEx_RXFIFO_threshold_level SMARTCARD RXFIFO threshold level

+  * @brief    SMARTCARD RXFIFO level

+  * @{

+  */

+#define SMARTCARD_RXFIFO_THRESHOLD_1_8   0x00000000U                                /*!< RXFIFO FIFO reaches 1/8 of its depth */

+#define SMARTCARD_RXFIFO_THRESHOLD_1_4   USART_CR3_RXFTCFG_0                        /*!< RXFIFO FIFO reaches 1/4 of its depth */

+#define SMARTCARD_RXFIFO_THRESHOLD_1_2   USART_CR3_RXFTCFG_1                        /*!< RXFIFO FIFO reaches 1/2 of its depth */

+#define SMARTCARD_RXFIFO_THRESHOLD_3_4   (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1)  /*!< RXFIFO FIFO reaches 3/4 of its depth */

+#define SMARTCARD_RXFIFO_THRESHOLD_7_8   USART_CR3_RXFTCFG_2                        /*!< RXFIFO FIFO reaches 7/8 of its depth */

+#define SMARTCARD_RXFIFO_THRESHOLD_8_8   (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0)  /*!< RXFIFO FIFO becomes full             */

+/**

+  * @}

+  */

+

+/** @defgroup SMARTCARDEx_Flags SMARTCARD Flags

+  *        Elements values convention: 0xXXXX

+  *           - 0xXXXX  : Flag mask in the ISR register

+  * @{

+  */

+#define SMARTCARD_FLAG_TCBGT          USART_ISR_TCBGT         /*!< SMARTCARD transmission complete before guard time completion */

+#define SMARTCARD_FLAG_REACK          USART_ISR_REACK         /*!< SMARTCARD receive enable acknowledge flag  */

+#define SMARTCARD_FLAG_TEACK          USART_ISR_TEACK         /*!< SMARTCARD transmit enable acknowledge flag */

+#define SMARTCARD_FLAG_BUSY           USART_ISR_BUSY          /*!< SMARTCARD busy flag                        */

+#define SMARTCARD_FLAG_EOBF           USART_ISR_EOBF          /*!< SMARTCARD end of block flag                */

+#define SMARTCARD_FLAG_RTOF           USART_ISR_RTOF          /*!< SMARTCARD receiver timeout flag            */

+#define SMARTCARD_FLAG_TXE            USART_ISR_TXE_TXFNF     /*!< SMARTCARD transmit data register empty     */

+#define SMARTCARD_FLAG_TXFNF          USART_ISR_TXE_TXFNF     /*!< SMARTCARD TXFIFO not full                  */

+#define SMARTCARD_FLAG_TC             USART_ISR_TC            /*!< SMARTCARD transmission complete            */

+#define SMARTCARD_FLAG_RXNE           USART_ISR_RXNE_RXFNE    /*!< SMARTCARD read data register not empty     */

+#define SMARTCARD_FLAG_RXFNE          USART_ISR_RXNE_RXFNE    /*!< SMARTCARD RXFIFO not empty                 */

+#define SMARTCARD_FLAG_IDLE           USART_ISR_IDLE          /*!< SMARTCARD idle line detection              */

+#define SMARTCARD_FLAG_ORE            USART_ISR_ORE           /*!< SMARTCARD overrun error                    */

+#define SMARTCARD_FLAG_NE             USART_ISR_NE            /*!< SMARTCARD noise error                      */

+#define SMARTCARD_FLAG_FE             USART_ISR_FE            /*!< SMARTCARD frame error                      */

+#define SMARTCARD_FLAG_PE             USART_ISR_PE            /*!< SMARTCARD parity error                     */

+#define SMARTCARD_FLAG_TXFE           USART_ISR_TXFE          /*!< SMARTCARD TXFIFO Empty flag                */

+#define SMARTCARD_FLAG_RXFF           USART_ISR_RXFF          /*!< SMARTCARD RXFIFO Full flag                 */

+#define SMARTCARD_FLAG_RXFT           USART_ISR_RXFT          /*!< SMARTCARD RXFIFO threshold flag            */

+#define SMARTCARD_FLAG_TXFT           USART_ISR_TXFT          /*!< SMARTCARD TXFIFO threshold flag            */

+/**

+  * @}

+  */

+

+/** @defgroup SMARTCARDEx_Interrupt_definition SMARTCARD Interrupts Definition

+  *        Elements values convention: 000ZZZZZ0XXYYYYYb

+  *           - YYYYY  : Interrupt source position in the XX register (5 bits)

+  *           - XX  : Interrupt source register (2 bits)

+  *                 - 01: CR1 register

+  *                 - 10: CR2 register

+  *                 - 11: CR3 register

+  *           - ZZZZZ  : Flag position in the ISR register(5 bits)

+  * @{

+  */

+#define SMARTCARD_IT_PE                     0x0028U           /*!< SMARTCARD parity error interruption                 */

+#define SMARTCARD_IT_TXE                    0x0727U           /*!< SMARTCARD transmit data register empty interruption */

+#define SMARTCARD_IT_TXFNF                  0x0727U           /*!< SMARTCARD TX FIFO not full interruption             */

+#define SMARTCARD_IT_TC                     0x0626U           /*!< SMARTCARD transmission complete interruption        */

+#define SMARTCARD_IT_RXNE                   0x0525U           /*!< SMARTCARD read data register not empty interruption */

+#define SMARTCARD_IT_RXFNE                  0x0525U           /*!< SMARTCARD RXFIFO not empty interruption             */

+#define SMARTCARD_IT_IDLE                   0x0424U           /*!< SMARTCARD idle line detection interruption          */

+

+#define SMARTCARD_IT_ERR                    0x0060U           /*!< SMARTCARD error interruption         */

+#define SMARTCARD_IT_ORE                    0x0300U           /*!< SMARTCARD overrun error interruption */

+#define SMARTCARD_IT_NE                     0x0200U           /*!< SMARTCARD noise error interruption   */

+#define SMARTCARD_IT_FE                     0x0100U           /*!< SMARTCARD frame error interruption   */

+

+#define SMARTCARD_IT_EOB                    0x0C3BU           /*!< SMARTCARD end of block interruption     */

+#define SMARTCARD_IT_RTO                    0x0B3AU           /*!< SMARTCARD receiver timeout interruption */

+#define SMARTCARD_IT_TCBGT                  0x1978U           /*!< SMARTCARD transmission complete before guard time completion interruption */

+

+#define SMARTCARD_IT_RXFF                    0x183FU          /*!< SMARTCARD RXFIFO full interruption                  */

+#define SMARTCARD_IT_TXFE                    0x173EU          /*!< SMARTCARD TXFIFO empty interruption                 */

+#define SMARTCARD_IT_RXFT                    0x1A7CU          /*!< SMARTCARD RXFIFO threshold reached interruption     */

+#define SMARTCARD_IT_TXFT                    0x1B77U          /*!< SMARTCARD TXFIFO threshold reached interruption     */

+/**

+  * @}

+  */

+

+/** @defgroup SMARTCARDEx_IT_CLEAR_Flags SMARTCARD Interruption Clear Flags

+  * @{

+  */

+#define SMARTCARD_CLEAR_PEF                 USART_ICR_PECF    /*!< SMARTCARD parity error clear flag          */

+#define SMARTCARD_CLEAR_FEF                 USART_ICR_FECF    /*!< SMARTCARD framing error clear flag         */

+#define SMARTCARD_CLEAR_NEF                 USART_ICR_NECF    /*!< SMARTCARD noise error detected clear flag  */

+#define SMARTCARD_CLEAR_OREF                USART_ICR_ORECF   /*!< SMARTCARD overrun error clear flag         */

+#define SMARTCARD_CLEAR_IDLEF               USART_ICR_IDLECF  /*!< SMARTCARD idle line detected clear flag    */

+#define SMARTCARD_CLEAR_TXFECF              USART_ICR_TXFECF  /*!< TXFIFO empty Clear Flag                    */

+#define SMARTCARD_CLEAR_TCF                 USART_ICR_TCCF    /*!< SMARTCARD transmission complete clear flag */

+#define SMARTCARD_CLEAR_TCBGTF              USART_ICR_TCBGTCF /*!< SMARTCARD transmission complete before guard time completion clear flag */

+#define SMARTCARD_CLEAR_RTOF                USART_ICR_RTOCF   /*!< SMARTCARD receiver time out clear flag     */

+#define SMARTCARD_CLEAR_EOBF                USART_ICR_EOBCF   /*!< SMARTCARD end of block clear flag          */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+/* Exported macros -----------------------------------------------------------*/

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup SMARTCARDEx_Private_Macros SMARTCARD Extended Private Macros

+  * @{

+  */

+

+/** @brief  Set the Transmission Completion flag

+  * @param  __HANDLE__ specifies the SMARTCARD Handle.

+  * @note  If TCBGT (Transmission Complete Before Guard Time) flag is not available or if

+  *        AdvancedInit.TxCompletionIndication is not already filled, the latter is forced

+  *        to SMARTCARD_TC (transmission completion indication when guard time has elapsed).

+  * @retval None

+  */

+#define SMARTCARD_TRANSMISSION_COMPLETION_SETTING(__HANDLE__)                                                \

+  do {                                                                                                       \

+    if (HAL_IS_BIT_CLR((__HANDLE__)->AdvancedInit.AdvFeatureInit, SMARTCARD_ADVFEATURE_TXCOMPLETION))        \

+    {                                                                                                        \

+      (__HANDLE__)->AdvancedInit.TxCompletionIndication = SMARTCARD_TC;                                      \

+    }                                                                                                        \

+    else                                                                                                     \

+    {                                                                                                        \

+      assert_param(IS_SMARTCARD_TRANSMISSION_COMPLETION((__HANDLE__)->AdvancedInit.TxCompletionIndication)); \

+    }                                                                                                        \

+  } while(0U)

+

+/** @brief  Return the transmission completion flag.

+  * @param  __HANDLE__ specifies the SMARTCARD Handle.

+  * @note  Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag.

+  *        When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is

+  *        reported.

+  * @retval Transmission completion flag

+  */

+#define SMARTCARD_TRANSMISSION_COMPLETION_FLAG(__HANDLE__)  \

+  (((__HANDLE__)->AdvancedInit.TxCompletionIndication == SMARTCARD_TC) ? (SMARTCARD_FLAG_TC) :  (SMARTCARD_FLAG_TCBGT))

+

+

+/** @brief Ensure that SMARTCARD frame transmission completion used flag is valid.

+  * @param __TXCOMPLETE__ SMARTCARD frame transmission completion used flag.

+  * @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)

+  */

+#define IS_SMARTCARD_TRANSMISSION_COMPLETION(__TXCOMPLETE__) (((__TXCOMPLETE__) == SMARTCARD_TCBGT) || \

+                                                              ((__TXCOMPLETE__) == SMARTCARD_TC))

+

+/** @brief Ensure that SMARTCARD FIFO mode is valid.

+  * @param __STATE__ SMARTCARD FIFO mode.

+  * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

+  */

+#define IS_SMARTCARD_FIFOMODE_STATE(__STATE__) (((__STATE__) == SMARTCARD_FIFOMODE_DISABLE ) || \

+                                                ((__STATE__) == SMARTCARD_FIFOMODE_ENABLE))

+

+/** @brief Ensure that SMARTCARD TXFIFO threshold level is valid.

+  * @param __THRESHOLD__ SMARTCARD TXFIFO threshold level.

+  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

+  */

+#define IS_SMARTCARD_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_8) || \

+                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_4) || \

+                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_1_2) || \

+                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_3_4) || \

+                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_7_8) || \

+                                                      ((__THRESHOLD__) == SMARTCARD_TXFIFO_THRESHOLD_8_8))

+

+/** @brief Ensure that SMARTCARD RXFIFO threshold level is valid.

+  * @param __THRESHOLD__ SMARTCARD RXFIFO threshold level.

+  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

+  */

+#define IS_SMARTCARD_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_8) || \

+                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_4) || \

+                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_1_2) || \

+                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_3_4) || \

+                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_7_8) || \

+                                                      ((__THRESHOLD__) == SMARTCARD_RXFIFO_THRESHOLD_8_8))

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup SMARTCARDEx_Exported_Functions

+  * @{

+  */

+

+/* Initialization and de-initialization functions  ****************************/

+/* IO operation methods *******************************************************/

+

+/** @addtogroup SMARTCARDEx_Exported_Functions_Group1

+  * @{

+  */

+

+/* Peripheral Control functions ***********************************************/

+void              HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint8_t BlockLength);

+void              HAL_SMARTCARDEx_TimeOut_Config(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t TimeOutValue);

+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);

+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsmartcard);

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup SMARTCARDEx_Exported_Functions_Group2

+  * @{

+  */

+

+/* IO operation functions *****************************************************/

+void HAL_SMARTCARDEx_RxFifoFullCallback(SMARTCARD_HandleTypeDef *hsmartcard);

+void HAL_SMARTCARDEx_TxFifoEmptyCallback(SMARTCARD_HandleTypeDef *hsmartcard);

+

+/**

+  * @}

+  */

+

+/** @addtogroup SMARTCARDEx_Exported_Functions_Group3

+  * @{

+  */

+

+/* Peripheral Control functions ***********************************************/

+HAL_StatusTypeDef HAL_SMARTCARDEx_EnableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard);

+HAL_StatusTypeDef HAL_SMARTCARDEx_DisableFifoMode(SMARTCARD_HandleTypeDef *hsmartcard);

+HAL_StatusTypeDef HAL_SMARTCARDEx_SetTxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold);

+HAL_StatusTypeDef HAL_SMARTCARDEx_SetRxFifoThreshold(SMARTCARD_HandleTypeDef *hsmartcard, uint32_t Threshold);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private functions ---------------------------------------------------------*/

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_SMARTCARD_EX_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_smbus.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_smbus.h
new file mode 100644
index 0000000000..283f66f974
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_smbus.h
@@ -0,0 +1,743 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_smbus.h

+  * @author  MCD Application Team

+  * @brief   Header file of SMBUS HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_SMBUS_H

+#define STM32H7xx_HAL_SMBUS_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup SMBUS

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup SMBUS_Exported_Types SMBUS Exported Types

+  * @{

+  */

+

+/** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition

+  * @brief  SMBUS Configuration Structure definition

+  * @{

+  */

+typedef struct

+{

+  uint32_t Timing;                 /*!< Specifies the SMBUS_TIMINGR_register value.

+                                     This parameter calculated by referring to SMBUS initialization

+                                            section in Reference manual */

+  uint32_t AnalogFilter;           /*!< Specifies if Analog Filter is enable or not.

+                                     This parameter can be a value of @ref SMBUS_Analog_Filter */

+

+  uint32_t OwnAddress1;            /*!< Specifies the first device own address.

+                                     This parameter can be a 7-bit or 10-bit address. */

+

+  uint32_t AddressingMode;         /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.

+                                     This parameter can be a value of @ref SMBUS_addressing_mode */

+

+  uint32_t DualAddressMode;        /*!< Specifies if dual addressing mode is selected.

+                                     This parameter can be a value of @ref SMBUS_dual_addressing_mode */

+

+  uint32_t OwnAddress2;            /*!< Specifies the second device own address if dual addressing mode is selected

+                                     This parameter can be a 7-bit address. */

+

+  uint32_t OwnAddress2Masks;       /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected

+                                     This parameter can be a value of @ref SMBUS_own_address2_masks. */

+

+  uint32_t GeneralCallMode;        /*!< Specifies if general call mode is selected.

+                                     This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */

+

+  uint32_t NoStretchMode;          /*!< Specifies if nostretch mode is selected.

+                                     This parameter can be a value of @ref SMBUS_nostretch_mode */

+

+  uint32_t PacketErrorCheckMode;   /*!< Specifies if Packet Error Check mode is selected.

+                                     This parameter can be a value of @ref SMBUS_packet_error_check_mode */

+

+  uint32_t PeripheralMode;         /*!< Specifies which mode of Periphal is selected.

+                                     This parameter can be a value of @ref SMBUS_peripheral_mode */

+

+  uint32_t SMBusTimeout;           /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.

+                                      (Enable bits and different timeout values)

+                                     This parameter calculated by referring to SMBUS initialization

+                                         section in Reference manual */

+} SMBUS_InitTypeDef;

+/**

+  * @}

+  */

+

+/** @defgroup HAL_state_definition HAL state definition

+  * @brief  HAL State definition

+  * @{

+  */

+#define HAL_SMBUS_STATE_RESET           (0x00000000U)  /*!< SMBUS not yet initialized or disabled         */

+#define HAL_SMBUS_STATE_READY           (0x00000001U)  /*!< SMBUS initialized and ready for use           */

+#define HAL_SMBUS_STATE_BUSY            (0x00000002U)  /*!< SMBUS internal process is ongoing             */

+#define HAL_SMBUS_STATE_MASTER_BUSY_TX  (0x00000012U)  /*!< Master Data Transmission process is ongoing   */

+#define HAL_SMBUS_STATE_MASTER_BUSY_RX  (0x00000022U)  /*!< Master Data Reception process is ongoing      */

+#define HAL_SMBUS_STATE_SLAVE_BUSY_TX   (0x00000032U)  /*!< Slave Data Transmission process is ongoing    */

+#define HAL_SMBUS_STATE_SLAVE_BUSY_RX   (0x00000042U)  /*!< Slave Data Reception process is ongoing       */

+#define HAL_SMBUS_STATE_TIMEOUT         (0x00000003U)  /*!< Timeout state                                 */

+#define HAL_SMBUS_STATE_ERROR           (0x00000004U)  /*!< Reception process is ongoing                  */

+#define HAL_SMBUS_STATE_LISTEN          (0x00000008U)   /*!< Address Listen Mode is ongoing                */

+/**

+  * @}

+  */

+

+/** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition

+  * @brief  SMBUS Error Code definition

+  * @{

+  */

+#define HAL_SMBUS_ERROR_NONE            (0x00000000U)    /*!< No error             */

+#define HAL_SMBUS_ERROR_BERR            (0x00000001U)    /*!< BERR error           */

+#define HAL_SMBUS_ERROR_ARLO            (0x00000002U)    /*!< ARLO error           */

+#define HAL_SMBUS_ERROR_ACKF            (0x00000004U)    /*!< ACKF error           */

+#define HAL_SMBUS_ERROR_OVR             (0x00000008U)    /*!< OVR error            */

+#define HAL_SMBUS_ERROR_HALTIMEOUT      (0x00000010U)    /*!< Timeout error        */

+#define HAL_SMBUS_ERROR_BUSTIMEOUT      (0x00000020U)    /*!< Bus Timeout error    */

+#define HAL_SMBUS_ERROR_ALERT           (0x00000040U)    /*!< Alert error          */

+#define HAL_SMBUS_ERROR_PECERR          (0x00000080U)    /*!< PEC error            */

+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)

+#define HAL_SMBUS_ERROR_INVALID_CALLBACK  (0x00000100U)    /*!< Invalid Callback error */

+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */

+#define HAL_SMBUS_ERROR_INVALID_PARAM    (0x00000200U)   /*!< Invalid Parameters error */

+/**

+  * @}

+  */

+

+/** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition

+  * @brief  SMBUS handle Structure definition

+  * @{

+  */

+typedef struct __SMBUS_HandleTypeDef

+{

+  I2C_TypeDef                  *Instance;       /*!< SMBUS registers base address       */

+

+  SMBUS_InitTypeDef            Init;            /*!< SMBUS communication parameters     */

+

+  uint8_t                      *pBuffPtr;       /*!< Pointer to SMBUS transfer buffer   */

+

+  uint16_t                     XferSize;        /*!< SMBUS transfer size                */

+

+  __IO uint16_t                XferCount;       /*!< SMBUS transfer counter             */

+

+  __IO uint32_t                XferOptions;     /*!< SMBUS transfer options             */

+

+  __IO uint32_t                PreviousState;   /*!< SMBUS communication Previous state */

+

+  HAL_LockTypeDef              Lock;            /*!< SMBUS locking object               */

+

+  __IO uint32_t                State;           /*!< SMBUS communication state          */

+

+  __IO uint32_t                ErrorCode;       /*!< SMBUS Error code                   */

+

+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)

+  void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);           /*!< SMBUS Master Tx Transfer completed callback */

+  void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);           /*!< SMBUS Master Rx Transfer completed callback */

+  void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);            /*!< SMBUS Slave Tx Transfer completed callback  */

+  void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);            /*!< SMBUS Slave Rx Transfer completed callback  */

+  void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus);             /*!< SMBUS Listen Complete callback              */

+  void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus);                  /*!< SMBUS Error callback                        */

+

+  void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);  /*!< SMBUS Slave Address Match callback */

+

+  void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);                /*!< SMBUS Msp Init callback                     */

+  void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus);              /*!< SMBUS Msp DeInit callback                   */

+

+#endif  /* USE_HAL_SMBUS_REGISTER_CALLBACKS */

+} SMBUS_HandleTypeDef;

+

+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  HAL SMBUS Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID      = 0x00U,    /*!< SMBUS Master Tx Transfer completed callback ID  */

+  HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID      = 0x01U,    /*!< SMBUS Master Rx Transfer completed callback ID  */

+  HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID       = 0x02U,    /*!< SMBUS Slave Tx Transfer completed callback ID   */

+  HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID       = 0x03U,    /*!< SMBUS Slave Rx Transfer completed callback ID   */

+  HAL_SMBUS_LISTEN_COMPLETE_CB_ID         = 0x04U,    /*!< SMBUS Listen Complete callback ID               */

+  HAL_SMBUS_ERROR_CB_ID                   = 0x05U,    /*!< SMBUS Error callback ID                         */

+

+  HAL_SMBUS_MSPINIT_CB_ID                 = 0x06U,    /*!< SMBUS Msp Init callback ID                      */

+  HAL_SMBUS_MSPDEINIT_CB_ID               = 0x07U     /*!< SMBUS Msp DeInit callback ID                    */

+

+} HAL_SMBUS_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL SMBUS Callback pointer definition

+  */

+typedef  void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); /*!< pointer to an SMBUS callback function */

+typedef  void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an SMBUS Address Match callback function */

+

+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+/* Exported constants --------------------------------------------------------*/

+

+/** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants

+  * @{

+  */

+

+/** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter

+  * @{

+  */

+#define SMBUS_ANALOGFILTER_ENABLE               (0x00000000U)

+#define SMBUS_ANALOGFILTER_DISABLE              I2C_CR1_ANFOFF

+/**

+  * @}

+  */

+

+/** @defgroup SMBUS_addressing_mode SMBUS addressing mode

+  * @{

+  */

+#define SMBUS_ADDRESSINGMODE_7BIT               (0x00000001U)

+#define SMBUS_ADDRESSINGMODE_10BIT              (0x00000002U)

+/**

+  * @}

+  */

+

+/** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode

+  * @{

+  */

+

+#define SMBUS_DUALADDRESS_DISABLE               (0x00000000U)

+#define SMBUS_DUALADDRESS_ENABLE                I2C_OAR2_OA2EN

+/**

+  * @}

+  */

+

+/** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks

+  * @{

+  */

+

+#define SMBUS_OA2_NOMASK                        ((uint8_t)0x00U)

+#define SMBUS_OA2_MASK01                        ((uint8_t)0x01U)

+#define SMBUS_OA2_MASK02                        ((uint8_t)0x02U)

+#define SMBUS_OA2_MASK03                        ((uint8_t)0x03U)

+#define SMBUS_OA2_MASK04                        ((uint8_t)0x04U)

+#define SMBUS_OA2_MASK05                        ((uint8_t)0x05U)

+#define SMBUS_OA2_MASK06                        ((uint8_t)0x06U)

+#define SMBUS_OA2_MASK07                        ((uint8_t)0x07U)

+/**

+  * @}

+  */

+

+

+/** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode

+  * @{

+  */

+#define SMBUS_GENERALCALL_DISABLE               (0x00000000U)

+#define SMBUS_GENERALCALL_ENABLE                I2C_CR1_GCEN

+/**

+  * @}

+  */

+

+/** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode

+  * @{

+  */

+#define SMBUS_NOSTRETCH_DISABLE                 (0x00000000U)

+#define SMBUS_NOSTRETCH_ENABLE                  I2C_CR1_NOSTRETCH

+/**

+  * @}

+  */

+

+/** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode

+  * @{

+  */

+#define SMBUS_PEC_DISABLE                       (0x00000000U)

+#define SMBUS_PEC_ENABLE                        I2C_CR1_PECEN

+/**

+  * @}

+  */

+

+/** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode

+  * @{

+  */

+#define SMBUS_PERIPHERAL_MODE_SMBUS_HOST        I2C_CR1_SMBHEN

+#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE       (0x00000000U)

+#define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP   I2C_CR1_SMBDEN

+/**

+  * @}

+  */

+

+/** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition

+  * @{

+  */

+

+#define  SMBUS_SOFTEND_MODE                     (0x00000000U)

+#define  SMBUS_RELOAD_MODE                      I2C_CR2_RELOAD

+#define  SMBUS_AUTOEND_MODE                     I2C_CR2_AUTOEND

+#define  SMBUS_SENDPEC_MODE                     I2C_CR2_PECBYTE

+/**

+  * @}

+  */

+

+/** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition

+  * @{

+  */

+

+#define  SMBUS_NO_STARTSTOP                     (0x00000000U)

+#define  SMBUS_GENERATE_STOP                    (uint32_t)(0x80000000U | I2C_CR2_STOP)

+#define  SMBUS_GENERATE_START_READ              (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)

+#define  SMBUS_GENERATE_START_WRITE             (uint32_t)(0x80000000U | I2C_CR2_START)

+/**

+  * @}

+  */

+

+/** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition

+  * @{

+  */

+

+/* List of XferOptions in usage of :

+ * 1- Restart condition when direction change

+ * 2- No Restart condition in other use cases

+ */

+#define  SMBUS_FIRST_FRAME                      SMBUS_SOFTEND_MODE

+#define  SMBUS_NEXT_FRAME                       ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))

+#define  SMBUS_FIRST_AND_LAST_FRAME_NO_PEC      SMBUS_AUTOEND_MODE

+#define  SMBUS_LAST_FRAME_NO_PEC                SMBUS_AUTOEND_MODE

+#define  SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC    ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))

+#define  SMBUS_LAST_FRAME_WITH_PEC              ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))

+

+/* List of XferOptions in usage of :

+ * 1- Restart condition in all use cases (direction change or not)

+ */

+#define  SMBUS_OTHER_FRAME_NO_PEC               (0x000000AAU)

+#define  SMBUS_OTHER_FRAME_WITH_PEC             (0x0000AA00U)

+#define  SMBUS_OTHER_AND_LAST_FRAME_NO_PEC      (0x00AA0000U)

+#define  SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC    (0xAA000000U)

+/**

+  * @}

+  */

+

+/** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition

+  * @brief SMBUS Interrupt definition

+  *        Elements values convention: 0xXXXXXXXX

+  *           - XXXXXXXX  : Interrupt control mask

+  * @{

+  */

+#define SMBUS_IT_ERRI                           I2C_CR1_ERRIE

+#define SMBUS_IT_TCI                            I2C_CR1_TCIE

+#define SMBUS_IT_STOPI                          I2C_CR1_STOPIE

+#define SMBUS_IT_NACKI                          I2C_CR1_NACKIE

+#define SMBUS_IT_ADDRI                          I2C_CR1_ADDRIE

+#define SMBUS_IT_RXI                            I2C_CR1_RXIE

+#define SMBUS_IT_TXI                            I2C_CR1_TXIE

+#define SMBUS_IT_TX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)

+#define SMBUS_IT_RX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)

+#define SMBUS_IT_ALERT                          (SMBUS_IT_ERRI)

+#define SMBUS_IT_ADDR                           (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)

+/**

+  * @}

+  */

+

+/** @defgroup SMBUS_Flag_definition SMBUS Flag definition

+  * @brief Flag definition

+  *        Elements values convention: 0xXXXXYYYY

+  *           - XXXXXXXX  : Flag mask

+  * @{

+  */

+

+#define  SMBUS_FLAG_TXE                         I2C_ISR_TXE

+#define  SMBUS_FLAG_TXIS                        I2C_ISR_TXIS

+#define  SMBUS_FLAG_RXNE                        I2C_ISR_RXNE

+#define  SMBUS_FLAG_ADDR                        I2C_ISR_ADDR

+#define  SMBUS_FLAG_AF                          I2C_ISR_NACKF

+#define  SMBUS_FLAG_STOPF                       I2C_ISR_STOPF

+#define  SMBUS_FLAG_TC                          I2C_ISR_TC

+#define  SMBUS_FLAG_TCR                         I2C_ISR_TCR

+#define  SMBUS_FLAG_BERR                        I2C_ISR_BERR

+#define  SMBUS_FLAG_ARLO                        I2C_ISR_ARLO

+#define  SMBUS_FLAG_OVR                         I2C_ISR_OVR

+#define  SMBUS_FLAG_PECERR                      I2C_ISR_PECERR

+#define  SMBUS_FLAG_TIMEOUT                     I2C_ISR_TIMEOUT

+#define  SMBUS_FLAG_ALERT                       I2C_ISR_ALERT

+#define  SMBUS_FLAG_BUSY                        I2C_ISR_BUSY

+#define  SMBUS_FLAG_DIR                         I2C_ISR_DIR

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macros ------------------------------------------------------------*/

+/** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros

+  * @{

+  */

+

+/** @brief  Reset SMBUS handle state.

+  * @param  __HANDLE__ specifies the SMBUS Handle.

+  * @retval None

+  */

+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)

+#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__)           do{                                                   \

+                                                                (__HANDLE__)->State = HAL_SMBUS_STATE_RESET;       \

+                                                                (__HANDLE__)->MspInitCallback = NULL;            \

+                                                                (__HANDLE__)->MspDeInitCallback = NULL;          \

+                                                             } while(0)

+#else

+#define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__)         ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)

+#endif

+

+/** @brief  Enable the specified SMBUS interrupts.

+  * @param  __HANDLE__ specifies the SMBUS Handle.

+  * @param  __INTERRUPT__ specifies the interrupt source to enable.

+  *        This parameter can be one of the following values:

+  *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable

+  *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable

+  *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable

+  *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable

+  *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable

+  *            @arg @ref SMBUS_IT_RXI   RX interrupt enable

+  *            @arg @ref SMBUS_IT_TXI   TX interrupt enable

+  *

+  * @retval None

+  */

+#define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))

+

+/** @brief  Disable the specified SMBUS interrupts.

+  * @param  __HANDLE__ specifies the SMBUS Handle.

+  * @param  __INTERRUPT__ specifies the interrupt source to disable.

+  *        This parameter can be one of the following values:

+  *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable

+  *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable

+  *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable

+  *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable

+  *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable

+  *            @arg @ref SMBUS_IT_RXI   RX interrupt enable

+  *            @arg @ref SMBUS_IT_TXI   TX interrupt enable

+  *

+  * @retval None

+  */

+#define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))

+

+/** @brief  Check whether the specified SMBUS interrupt source is enabled or not.

+  * @param  __HANDLE__ specifies the SMBUS Handle.

+  * @param  __INTERRUPT__ specifies the SMBUS interrupt source to check.

+  *          This parameter can be one of the following values:

+  *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable

+  *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable

+  *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable

+  *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable

+  *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable

+  *            @arg @ref SMBUS_IT_RXI   RX interrupt enable

+  *            @arg @ref SMBUS_IT_TXI   TX interrupt enable

+  *

+  * @retval The new state of __IT__ (SET or RESET).

+  */

+#define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

+

+/** @brief  Check whether the specified SMBUS flag is set or not.

+  * @param  __HANDLE__ specifies the SMBUS Handle.

+  * @param  __FLAG__ specifies the flag to check.

+  *        This parameter can be one of the following values:

+  *            @arg @ref SMBUS_FLAG_TXE     Transmit data register empty

+  *            @arg @ref SMBUS_FLAG_TXIS    Transmit interrupt status

+  *            @arg @ref SMBUS_FLAG_RXNE    Receive data register not empty

+  *            @arg @ref SMBUS_FLAG_ADDR    Address matched (slave mode)

+  *            @arg @ref SMBUS_FLAG_AF      NACK received flag

+  *            @arg @ref SMBUS_FLAG_STOPF   STOP detection flag

+  *            @arg @ref SMBUS_FLAG_TC      Transfer complete (master mode)

+  *            @arg @ref SMBUS_FLAG_TCR     Transfer complete reload

+  *            @arg @ref SMBUS_FLAG_BERR    Bus error

+  *            @arg @ref SMBUS_FLAG_ARLO    Arbitration lost

+  *            @arg @ref SMBUS_FLAG_OVR     Overrun/Underrun

+  *            @arg @ref SMBUS_FLAG_PECERR  PEC error in reception

+  *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag

+  *            @arg @ref SMBUS_FLAG_ALERT   SMBus alert

+  *            @arg @ref SMBUS_FLAG_BUSY    Bus busy

+  *            @arg @ref SMBUS_FLAG_DIR     Transfer direction (slave mode)

+  *

+  * @retval The new state of __FLAG__ (SET or RESET).

+  */

+#define SMBUS_FLAG_MASK  (0x0001FFFFU)

+#define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)

+

+/** @brief  Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.

+  * @param  __HANDLE__ specifies the SMBUS Handle.

+  * @param  __FLAG__ specifies the flag to clear.

+  *          This parameter can be any combination of the following values:

+  *            @arg @ref SMBUS_FLAG_ADDR    Address matched (slave mode)

+  *            @arg @ref SMBUS_FLAG_AF      NACK received flag

+  *            @arg @ref SMBUS_FLAG_STOPF   STOP detection flag

+  *            @arg @ref SMBUS_FLAG_BERR    Bus error

+  *            @arg @ref SMBUS_FLAG_ARLO    Arbitration lost

+  *            @arg @ref SMBUS_FLAG_OVR     Overrun/Underrun

+  *            @arg @ref SMBUS_FLAG_PECERR  PEC error in reception

+  *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag

+  *            @arg @ref SMBUS_FLAG_ALERT   SMBus alert

+  *

+  * @retval None

+  */

+#define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))

+

+/** @brief  Enable the specified SMBUS peripheral.

+  * @param  __HANDLE__ specifies the SMBUS Handle.

+  * @retval None

+  */

+#define __HAL_SMBUS_ENABLE(__HANDLE__)                  (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

+

+/** @brief  Disable the specified SMBUS peripheral.

+  * @param  __HANDLE__ specifies the SMBUS Handle.

+  * @retval None

+  */

+#define __HAL_SMBUS_DISABLE(__HANDLE__)                 (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))

+

+/** @brief  Generate a Non-Acknowledge SMBUS peripheral in Slave mode.

+  * @param  __HANDLE__ specifies the SMBUS Handle.

+  * @retval None

+  */

+#define __HAL_SMBUS_GENERATE_NACK(__HANDLE__)           (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))

+

+/**

+  * @}

+  */

+

+

+/* Private constants ---------------------------------------------------------*/

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup SMBUS_Private_Macro SMBUS Private Macros

+  * @{

+  */

+

+#define IS_SMBUS_ANALOG_FILTER(FILTER)                  (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \

+                                                          ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))

+

+#define IS_SMBUS_DIGITAL_FILTER(FILTER)                 ((FILTER) <= 0x0000000FU)

+

+#define IS_SMBUS_ADDRESSING_MODE(MODE)                  (((MODE) == SMBUS_ADDRESSINGMODE_7BIT)  || \

+                                                          ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))

+

+#define IS_SMBUS_DUAL_ADDRESS(ADDRESS)                  (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \

+                                                          ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))

+

+#define IS_SMBUS_OWN_ADDRESS2_MASK(MASK)                (((MASK) == SMBUS_OA2_NOMASK)    || \

+                                                         ((MASK) == SMBUS_OA2_MASK01)    || \

+                                                         ((MASK) == SMBUS_OA2_MASK02)    || \

+                                                         ((MASK) == SMBUS_OA2_MASK03)    || \

+                                                         ((MASK) == SMBUS_OA2_MASK04)    || \

+                                                         ((MASK) == SMBUS_OA2_MASK05)    || \

+                                                         ((MASK) == SMBUS_OA2_MASK06)    || \

+                                                         ((MASK) == SMBUS_OA2_MASK07))

+

+#define IS_SMBUS_GENERAL_CALL(CALL)                     (((CALL) == SMBUS_GENERALCALL_DISABLE) || \

+                                                         ((CALL) == SMBUS_GENERALCALL_ENABLE))

+

+#define IS_SMBUS_NO_STRETCH(STRETCH)                    (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \

+                                                         ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))

+

+#define IS_SMBUS_PEC(PEC)                               (((PEC) == SMBUS_PEC_DISABLE) || \

+                                                          ((PEC) == SMBUS_PEC_ENABLE))

+

+#define IS_SMBUS_PERIPHERAL_MODE(MODE)                  (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST)    || \

+                                                          ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE)  || \

+                                                          ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))

+

+#define IS_SMBUS_TRANSFER_MODE(MODE)                    (((MODE) == SMBUS_RELOAD_MODE)                           || \

+                                                          ((MODE) == SMBUS_AUTOEND_MODE)                         || \

+                                                          ((MODE) == SMBUS_SOFTEND_MODE)                         || \

+                                                          ((MODE) == SMBUS_SENDPEC_MODE)                         || \

+                                                          ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE))   || \

+                                                          ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))  || \

+                                                          ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE))   || \

+                                                          ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))

+

+

+#define IS_SMBUS_TRANSFER_REQUEST(REQUEST)              (((REQUEST) == SMBUS_GENERATE_STOP)              || \

+                                                          ((REQUEST) == SMBUS_GENERATE_START_READ)       || \

+                                                          ((REQUEST) == SMBUS_GENERATE_START_WRITE)      || \

+                                                          ((REQUEST) == SMBUS_NO_STARTSTOP))

+

+

+#define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)      (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)       || \

+                                                          ((REQUEST) == SMBUS_FIRST_FRAME)                       || \

+                                                          ((REQUEST) == SMBUS_NEXT_FRAME)                        || \

+                                                          ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC)       || \

+                                                          ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC)                 || \

+                                                          ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)     || \

+                                                          ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC))

+

+#define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC)                || \

+                                                          ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)       || \

+                                                          ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC)              || \

+                                                          ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))

+

+#define SMBUS_RESET_CR1(__HANDLE__)                       ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))

+#define SMBUS_RESET_CR2(__HANDLE__)                       ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))

+

+#define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__)     (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \

+                                                                  (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))

+

+#define SMBUS_GET_ADDR_MATCH(__HANDLE__)                  (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)

+#define SMBUS_GET_DIR(__HANDLE__)                         (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)

+#define SMBUS_GET_STOP_MODE(__HANDLE__)                   ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)

+#define SMBUS_GET_PEC_MODE(__HANDLE__)                    ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)

+#define SMBUS_GET_ALERT_ENABLED(__HANDLE__)                ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)

+

+#define SMBUS_CHECK_FLAG(__ISR__, __FLAG__)             ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)) ? SET : RESET)

+#define SMBUS_CHECK_IT_SOURCE(__CR1__, __IT__)          ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET)

+

+#define IS_SMBUS_OWN_ADDRESS1(ADDRESS1)                         ((ADDRESS1) <= 0x000003FFU)

+#define IS_SMBUS_OWN_ADDRESS2(ADDRESS2)                         ((ADDRESS2) <= (uint16_t)0x00FFU)

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions

+  * @{

+  */

+

+/** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions

+ * @{

+ */

+

+/* Initialization and de-initialization functions  ****************************/

+HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);

+HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus);

+void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);

+void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);

+HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter);

+HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);

+

+/* Callbacks Register/UnRegister functions  ***********************************/

+#if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1)

+HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID);

+

+HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus);

+#endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions

+ * @{

+ */

+

+/* IO operation functions  *****************************************************/

+/** @addtogroup Blocking_mode_Polling Blocking mode Polling

+ * @{

+ */

+/******* Blocking mode: Polling */

+HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);

+/**

+  * @}

+  */

+

+/** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt

+ * @{

+ */

+/******* Non-Blocking mode: Interrupt */

+HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);

+HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);

+HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);

+HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);

+HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);

+

+HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);

+HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);

+HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);

+HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);

+/**

+  * @}

+  */

+

+/** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks

+ * @{

+ */

+/******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */

+void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);

+void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);

+void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);

+void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);

+void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);

+void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);

+void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);

+void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);

+void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);

+

+/**

+  * @}

+  */

+

+/** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions

+ *  @{

+ */

+

+/* Peripheral State and Errors functions  **************************************************/

+uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);

+uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private Functions ---------------------------------------------------------*/

+/** @defgroup SMBUS_Private_Functions SMBUS Private Functions

+  * @{

+  */

+/* Private functions are defined in stm32h7xx_hal_smbus.c file */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+

+#endif /* STM32H7xx_HAL_SMBUS_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_spdifrx.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_spdifrx.h
new file mode 100644
index 0000000000..92bdf67fba
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_spdifrx.h
@@ -0,0 +1,606 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_spdifrx.h

+  * @author  MCD Application Team

+  * @brief   Header file of SPDIFRX HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_SPDIFRX_H

+#define STM32H7xx_HAL_SPDIFRX_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+#if defined (SPDIFRX)

+

+/** @addtogroup SPDIFRX

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup SPDIFRX_Exported_Types SPDIFRX Exported Types

+  * @{

+  */

+

+/**

+  * @brief SPDIFRX Init structure definition

+  */

+typedef struct

+{

+  uint32_t InputSelection;           /*!< Specifies the SPDIF input selection.

+                                          This parameter can be a value of @ref SPDIFRX_Input_Selection */

+

+  uint32_t Retries;                  /*!< Specifies the Maximum allowed re-tries during synchronization phase.

+                                          This parameter can be a value of @ref SPDIFRX_Max_Retries */

+

+  uint32_t WaitForActivity;          /*!< Specifies the wait for activity on SPDIF selected input.

+                                          This parameter can be a value of @ref SPDIFRX_Wait_For_Activity. */

+

+  uint32_t ChannelSelection;         /*!< Specifies whether the control flow will take the channel status from channel A or B.

+                                          This parameter can be a value of @ref SPDIFRX_Channel_Selection */

+

+  uint32_t DataFormat;               /*!< Specifies the Data samples format (LSB, MSB, ...).

+                                          This parameter can be a value of @ref SPDIFRX_Data_Format */

+

+  uint32_t StereoMode;               /*!< Specifies whether the peripheral is in stereo or mono mode.

+                                          This parameter can be a value of @ref SPDIFRX_Stereo_Mode */

+

+  uint32_t PreambleTypeMask;          /*!< Specifies whether The preamble type bits are copied or not into the received frame.

+                                           This parameter can be a value of @ref SPDIFRX_PT_Mask */

+

+  uint32_t ChannelStatusMask;        /*!< Specifies whether the channel status and user bits are copied or not into the received frame.

+                                          This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */

+

+  uint32_t ValidityBitMask;          /*!< Specifies whether the validity bit is copied or not into the received frame.

+                                          This parameter can be a value of @ref SPDIFRX_V_Mask */

+

+  uint32_t ParityErrorMask;          /*!< Specifies whether the parity error bit is copied or not into the received frame.

+                                          This parameter can be a value of @ref SPDIFRX_PE_Mask */

+  FunctionalState SymbolClockGen;     /*!< Enable/Disable the SPDIFRX Symbol Clock generation.

+                                          This parameter can be set to Enable or Disable */

+

+  FunctionalState BackupSymbolClockGen; /*!< Enable/Disable the SPDIFRX Backup Symbol Clock generation.

+                                          This parameter can be set to Enable or Disable */

+} SPDIFRX_InitTypeDef;

+

+/**

+  * @brief SPDIFRX SetDataFormat structure definition

+  */

+typedef struct

+{

+  uint32_t DataFormat;               /*!< Specifies the Data samples format (LSB, MSB, ...).

+                                          This parameter can be a value of @ref SPDIFRX_Data_Format */

+

+  uint32_t StereoMode;               /*!< Specifies whether the peripheral is in stereo or mono mode.

+                                          This parameter can be a value of @ref SPDIFRX_Stereo_Mode */

+

+  uint32_t PreambleTypeMask;          /*!< Specifies whether The preamble type bits are copied or not into the received frame.

+                                                                                   This parameter can be a value of @ref SPDIFRX_PT_Mask */

+

+  uint32_t ChannelStatusMask;        /*!< Specifies whether the channel status and user bits are copied or not into the received frame.

+                                                                                  This parameter can be a value of @ref SPDIFRX_ChannelStatus_Mask */

+

+  uint32_t ValidityBitMask;          /*!< Specifies whether the validity bit is copied or not into the received frame.

+                                                                                  This parameter can be a value of @ref SPDIFRX_V_Mask */

+

+  uint32_t ParityErrorMask;          /*!< Specifies whether the parity error bit is copied or not into the received frame.

+                                                                                  This parameter can be a value of @ref SPDIFRX_PE_Mask */

+

+} SPDIFRX_SetDataFormatTypeDef;

+

+/**

+  * @brief  HAL State structures definition

+  */

+typedef enum

+{

+  HAL_SPDIFRX_STATE_RESET      = 0x00U,  /*!< SPDIFRX not yet initialized or disabled                */

+  HAL_SPDIFRX_STATE_READY      = 0x01U,  /*!< SPDIFRX initialized and ready for use                  */

+  HAL_SPDIFRX_STATE_BUSY       = 0x02U,  /*!< SPDIFRX internal process is ongoing                    */

+  HAL_SPDIFRX_STATE_BUSY_RX    = 0x03U,  /*!< SPDIFRX internal Data Flow RX process is ongoing       */

+  HAL_SPDIFRX_STATE_BUSY_CX    = 0x04U,  /*!< SPDIFRX internal Control Flow RX process is ongoing    */

+  HAL_SPDIFRX_STATE_ERROR      = 0x07U   /*!< SPDIFRX error state                                    */

+} HAL_SPDIFRX_StateTypeDef;

+

+/**

+  * @brief SPDIFRX handle Structure definition

+  */

+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)

+typedef struct __SPDIFRX_HandleTypeDef

+#else

+typedef struct

+#endif

+{

+  SPDIFRX_TypeDef            *Instance;    /* SPDIFRX registers base address */

+

+  SPDIFRX_InitTypeDef        Init;         /* SPDIFRX communication parameters */

+

+  uint32_t                   *pRxBuffPtr;  /* Pointer to SPDIFRX Rx transfer buffer */

+

+  uint32_t                   *pCsBuffPtr;  /* Pointer to SPDIFRX Cx transfer buffer */

+

+  __IO uint16_t              RxXferSize;   /* SPDIFRX Rx transfer size */

+

+  __IO uint16_t              RxXferCount;  /* SPDIFRX Rx transfer counter

+                                              (This field is initialized at the

+                                               same value as transfer size at the

+                                               beginning of the transfer and

+                                               decremented when a sample is received.

+                                               NbSamplesReceived = RxBufferSize-RxBufferCount) */

+

+  __IO uint16_t              CsXferSize;   /* SPDIFRX Rx transfer size */

+

+  __IO uint16_t              CsXferCount;  /* SPDIFRX Rx transfer counter

+                                              (This field is initialized at the

+                                               same value as transfer size at the

+                                               beginning of the transfer and

+                                               decremented when a sample is received.

+                                               NbSamplesReceived = RxBufferSize-RxBufferCount) */

+

+  DMA_HandleTypeDef          *hdmaCsRx;    /* SPDIFRX EC60958_channel_status and user_information DMA handle parameters */

+

+  DMA_HandleTypeDef          *hdmaDrRx;    /* SPDIFRX Rx DMA handle parameters */

+

+  __IO HAL_LockTypeDef       Lock;         /* SPDIFRX locking object */

+

+  __IO HAL_SPDIFRX_StateTypeDef  State;    /* SPDIFRX communication state */

+

+  __IO uint32_t  ErrorCode;                /* SPDIFRX Error code */

+

+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)

+  void (*RxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);   /*!< SPDIFRX Data flow half completed callback */

+  void (*RxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);       /*!< SPDIFRX Data flow completed callback */

+  void (*CxHalfCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);   /*!< SPDIFRX Control flow half completed callback */

+  void (*CxCpltCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);       /*!< SPDIFRX Control flow completed callback */

+  void (*ErrorCallback)(struct __SPDIFRX_HandleTypeDef *hspdif);        /*!< SPDIFRX error callback */

+  void (* MspInitCallback)( struct __SPDIFRX_HandleTypeDef * hspdif);   /*!< SPDIFRX Msp Init callback  */

+  void (* MspDeInitCallback)( struct __SPDIFRX_HandleTypeDef * hspdif); /*!< SPDIFRX Msp DeInit callback  */

+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */

+

+} SPDIFRX_HandleTypeDef;

+/**

+  * @}

+  */

+

+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  HAL SPDIFRX Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_SPDIFRX_RX_HALF_CB_ID   = 0x00U,    /*!< SPDIFRX Data flow half completed callback ID */

+  HAL_SPDIFRX_RX_CPLT_CB_ID   = 0x01U,    /*!< SPDIFRX Data flow completed callback */

+  HAL_SPDIFRX_CX_HALF_CB_ID   = 0x02U,    /*!< SPDIFRX Control flow half completed callback */

+  HAL_SPDIFRX_CX_CPLT_CB_ID   = 0x03U,    /*!< SPDIFRX Control flow completed callback */

+  HAL_SPDIFRX_ERROR_CB_ID     = 0x04U,    /*!< SPDIFRX error callback */

+  HAL_SPDIFRX_MSPINIT_CB_ID   = 0x05U,    /*!< SPDIFRX Msp Init callback ID     */

+  HAL_SPDIFRX_MSPDEINIT_CB_ID = 0x06U     /*!< SPDIFRX Msp DeInit callback ID   */

+}HAL_SPDIFRX_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL SPDIFRX Callback pointer definition

+  */

+typedef  void (*pSPDIFRX_CallbackTypeDef)(SPDIFRX_HandleTypeDef * hspdif); /*!< pointer to an SPDIFRX callback function */

+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup SPDIFRX_Exported_Constants SPDIFRX Exported Constants

+  * @{

+  */

+/** @defgroup SPDIFRX_ErrorCode SPDIFRX Error Code

+  * @{

+  */

+#define HAL_SPDIFRX_ERROR_NONE      ((uint32_t)0x00000000U)  /*!< No error           */

+#define HAL_SPDIFRX_ERROR_TIMEOUT   ((uint32_t)0x00000001U)  /*!< Timeout error      */

+#define HAL_SPDIFRX_ERROR_OVR       ((uint32_t)0x00000002U)  /*!< OVR error          */

+#define HAL_SPDIFRX_ERROR_PE        ((uint32_t)0x00000004U)  /*!< Parity error       */

+#define HAL_SPDIFRX_ERROR_DMA       ((uint32_t)0x00000008U)  /*!< DMA transfer error */

+#define HAL_SPDIFRX_ERROR_UNKNOWN   ((uint32_t)0x00000010U)  /*!< Unknown Error error */

+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)

+#define  HAL_SPDIFRX_ERROR_INVALID_CALLBACK   ((uint32_t)0x00000020U)    /*!< Invalid Callback error  */

+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/** @defgroup SPDIFRX_Input_Selection SPDIFRX Input Selection

+  * @{

+  */

+#define SPDIFRX_INPUT_IN0   ((uint32_t)0x00000000U)

+#define SPDIFRX_INPUT_IN1   ((uint32_t)0x00010000U)

+#define SPDIFRX_INPUT_IN2   ((uint32_t)0x00020000U)

+#define SPDIFRX_INPUT_IN3   ((uint32_t)0x00030000U)

+/**

+  * @}

+  */

+

+/** @defgroup SPDIFRX_Max_Retries SPDIFRX Maximum Retries

+  * @{

+  */

+#define SPDIFRX_MAXRETRIES_NONE   ((uint32_t)0x00000000U)

+#define SPDIFRX_MAXRETRIES_3      ((uint32_t)0x00001000U)

+#define SPDIFRX_MAXRETRIES_15     ((uint32_t)0x00002000U)

+#define SPDIFRX_MAXRETRIES_63     ((uint32_t)0x00003000U)

+/**

+  * @}

+  */

+

+/** @defgroup SPDIFRX_Wait_For_Activity SPDIFRX Wait For Activity

+  * @{

+  */

+#define SPDIFRX_WAITFORACTIVITY_OFF   ((uint32_t)0x00000000U)

+#define SPDIFRX_WAITFORACTIVITY_ON    ((uint32_t)SPDIFRX_CR_WFA)

+/**

+  * @}

+  */

+

+/** @defgroup SPDIFRX_PT_Mask SPDIFRX Preamble Type Mask

+  * @{

+  */

+#define SPDIFRX_PREAMBLETYPEMASK_OFF    ((uint32_t)0x00000000U)

+#define SPDIFRX_PREAMBLETYPEMASK_ON     ((uint32_t)SPDIFRX_CR_PTMSK)

+/**

+  * @}

+  */

+

+/** @defgroup SPDIFRX_ChannelStatus_Mask  SPDIFRX Channel Status Mask

+  * @{

+  */

+#define SPDIFRX_CHANNELSTATUS_OFF   ((uint32_t)0x00000000U)        /* The channel status and user bits are copied into the SPDIF_DR */

+#define SPDIFRX_CHANNELSTATUS_ON    ((uint32_t)SPDIFRX_CR_CUMSK)  /* The channel status and user bits are not copied into the SPDIF_DR, zeros are written instead*/

+/**

+  * @}

+  */

+

+/** @defgroup SPDIFRX_V_Mask SPDIFRX Validity Mask

+* @{

+*/

+#define SPDIFRX_VALIDITYMASK_OFF    ((uint32_t)0x00000000U)

+#define SPDIFRX_VALIDITYMASK_ON     ((uint32_t)SPDIFRX_CR_VMSK)

+/**

+  * @}

+  */

+

+/** @defgroup SPDIFRX_PE_Mask  SPDIFRX Parity Error Mask

+  * @{

+  */

+#define SPDIFRX_PARITYERRORMASK_OFF   ((uint32_t)0x00000000U)

+#define SPDIFRX_PARITYERRORMASK_ON    ((uint32_t)SPDIFRX_CR_PMSK)

+/**

+  * @}

+  */

+

+/** @defgroup SPDIFRX_Channel_Selection  SPDIFRX Channel Selection

+  * @{

+  */

+#define SPDIFRX_CHANNEL_A   ((uint32_t)0x00000000U)

+#define SPDIFRX_CHANNEL_B   ((uint32_t)SPDIFRX_CR_CHSEL)

+/**

+  * @}

+  */

+

+/** @defgroup SPDIFRX_Data_Format SPDIFRX Data Format

+  * @{

+  */

+#define SPDIFRX_DATAFORMAT_LSB      ((uint32_t)0x00000000U)

+#define SPDIFRX_DATAFORMAT_MSB      ((uint32_t)0x00000010U)

+#define SPDIFRX_DATAFORMAT_32BITS   ((uint32_t)0x00000020U)

+/**

+  * @}

+  */

+

+/** @defgroup SPDIFRX_Stereo_Mode SPDIFRX Stereo Mode

+  * @{

+  */

+#define SPDIFRX_STEREOMODE_DISABLE    ((uint32_t)0x00000000U)

+#define SPDIFRX_STEREOMODE_ENABLE     ((uint32_t)SPDIFRX_CR_RXSTEO)

+/**

+  * @}

+  */

+

+/** @defgroup SPDIFRX_State SPDIFRX State

+  * @{

+  */

+

+#define SPDIFRX_STATE_IDLE    ((uint32_t)0xFFFFFFFCU)

+#define SPDIFRX_STATE_SYNC    ((uint32_t)0x00000001U)

+#define SPDIFRX_STATE_RCV     ((uint32_t)SPDIFRX_CR_SPDIFEN)

+/**

+  * @}

+  */

+

+/** @defgroup SPDIFRX_Interrupts_Definition SPDIFRX Interrupts Definition

+  * @{

+  */

+#define SPDIFRX_IT_RXNE       ((uint32_t)SPDIFRX_IMR_RXNEIE)

+#define SPDIFRX_IT_CSRNE      ((uint32_t)SPDIFRX_IMR_CSRNEIE)

+#define SPDIFRX_IT_PERRIE     ((uint32_t)SPDIFRX_IMR_PERRIE)

+#define SPDIFRX_IT_OVRIE      ((uint32_t)SPDIFRX_IMR_OVRIE)

+#define SPDIFRX_IT_SBLKIE     ((uint32_t)SPDIFRX_IMR_SBLKIE)

+#define SPDIFRX_IT_SYNCDIE    ((uint32_t)SPDIFRX_IMR_SYNCDIE)

+#define SPDIFRX_IT_IFEIE      ((uint32_t)SPDIFRX_IMR_IFEIE )

+/**

+  * @}

+  */

+

+/** @defgroup SPDIFRX_Flags_Definition SPDIFRX Flags Definition

+  * @{

+  */

+#define SPDIFRX_FLAG_RXNE     ((uint32_t)SPDIFRX_SR_RXNE)

+#define SPDIFRX_FLAG_CSRNE    ((uint32_t)SPDIFRX_SR_CSRNE)

+#define SPDIFRX_FLAG_PERR     ((uint32_t)SPDIFRX_SR_PERR)

+#define SPDIFRX_FLAG_OVR      ((uint32_t)SPDIFRX_SR_OVR)

+#define SPDIFRX_FLAG_SBD      ((uint32_t)SPDIFRX_SR_SBD)

+#define SPDIFRX_FLAG_SYNCD    ((uint32_t)SPDIFRX_SR_SYNCD)

+#define SPDIFRX_FLAG_FERR     ((uint32_t)SPDIFRX_SR_FERR)

+#define SPDIFRX_FLAG_SERR     ((uint32_t)SPDIFRX_SR_SERR)

+#define SPDIFRX_FLAG_TERR     ((uint32_t)SPDIFRX_SR_TERR)

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macros -----------------------------------------------------------*/

+/** @defgroup SPDIFRX_Exported_macros SPDIFRX Exported Macros

+  * @{

+  */

+

+/** @brief  Reset SPDIFRX handle state

+  * @param  __HANDLE__ SPDIFRX handle.

+  * @retval None

+  */

+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)

+#define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) do{\

+                                                      (__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET;\

+                                                      (__HANDLE__)->MspInitCallback = NULL;\

+                                                      (__HANDLE__)->MspDeInitCallback = NULL;\

+                                                     }while(0)

+#else

+#define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPDIFRX_STATE_RESET)

+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */

+

+/** @brief  Disable the specified SPDIFRX peripheral (IDLE State).

+  * @param  __HANDLE__ specifies the SPDIFRX Handle.

+  * @retval None

+  */

+#define __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE)

+

+/** @brief  Enable the specified SPDIFRX peripheral (SYNC State).

+  * @param  __HANDLE__ specifies the SPDIFRX Handle.

+  * @retval None

+  */

+#define __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC)

+

+

+/** @brief  Enable the specified SPDIFRX peripheral (RCV State).

+  * @param  __HANDLE__ specifies the SPDIFRX Handle.

+  * @retval None

+  */

+#define __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV)

+

+

+/** @brief  Enable or disable the specified SPDIFRX interrupts.

+  * @param  __HANDLE__    specifies the SPDIFRX Handle.

+  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.

+  *        This parameter can be one of the following values:

+  *            @arg SPDIFRX_IT_RXNE

+  *            @arg SPDIFRX_IT_CSRNE

+  *            @arg SPDIFRX_IT_PERRIE

+  *            @arg SPDIFRX_IT_OVRIE

+  *            @arg SPDIFRX_IT_SBLKIE

+  *            @arg SPDIFRX_IT_SYNCDIE

+  *            @arg SPDIFRX_IT_IFEIE

+  * @retval None

+  */

+#define __HAL_SPDIFRX_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR |= (__INTERRUPT__))

+#define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__)))

+

+/** @brief  Checks if the specified SPDIFRX interrupt source is enabled or disabled.

+  * @param  __HANDLE__    specifies the SPDIFRX Handle.

+  * @param  __INTERRUPT__ specifies the SPDIFRX interrupt source to check.

+  *          This parameter can be one of the following values:

+  *            @arg SPDIFRX_IT_RXNE

+  *            @arg SPDIFRX_IT_CSRNE

+  *            @arg SPDIFRX_IT_PERRIE

+  *            @arg SPDIFRX_IT_OVRIE

+  *            @arg SPDIFRX_IT_SBLKIE

+  *            @arg SPDIFRX_IT_SYNCDIE

+  *            @arg SPDIFRX_IT_IFEIE

+  * @retval The new state of __IT__ (TRUE or FALSE).

+  */

+#define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

+

+/** @brief  Checks whether the specified SPDIFRX flag is set or not.

+  * @param  __HANDLE__  specifies the SPDIFRX Handle.

+  * @param  __FLAG__    specifies the flag to check.

+  *        This parameter can be one of the following values:

+  *            @arg SPDIFRX_FLAG_RXNE

+  *            @arg SPDIFRX_FLAG_CSRNE

+  *            @arg SPDIFRX_FLAG_PERR

+  *            @arg SPDIFRX_FLAG_OVR

+  *            @arg SPDIFRX_FLAG_SBD

+  *            @arg SPDIFRX_FLAG_SYNCD

+  *            @arg SPDIFRX_FLAG_FERR

+  *            @arg SPDIFRX_FLAG_SERR

+  *            @arg SPDIFRX_FLAG_TERR

+  * @retval The new state of __FLAG__ (TRUE or FALSE).

+  */

+#define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)

+

+/** @brief  Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit.

+  * @param  __HANDLE__    specifies the USART Handle.

+  * @param  __IT_CLEAR__  specifies the interrupt clear register flag that needs to be set

+  *                       to clear the corresponding interrupt

+  *          This parameter can be one of the following values:

+  *            @arg SPDIFRX_FLAG_PERR

+  *            @arg SPDIFRX_FLAG_OVR

+  *            @arg SPDIFRX_SR_SBD

+  *            @arg SPDIFRX_SR_SYNCD

+  * @retval None

+  */

+#define __HAL_SPDIFRX_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->IFCR = (uint32_t)(__IT_CLEAR__))

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup SPDIFRX_Exported_Functions

+  * @{

+  */

+

+/** @addtogroup SPDIFRX_Exported_Functions_Group1

+  * @{

+  */

+/* Initialization/de-initialization functions  **********************************/

+HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif);

+HAL_StatusTypeDef HAL_SPDIFRX_DeInit (SPDIFRX_HandleTypeDef *hspdif);

+void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif);

+void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif);

+HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef  sDataFormat);

+

+/* Callbacks Register/UnRegister functions  ***********************************/

+#if (USE_HAL_SPDIFRX_REGISTER_CALLBACKS == 1)

+HAL_StatusTypeDef HAL_SPDIFRX_RegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID, pSPDIFRX_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_SPDIFRX_UnRegisterCallback(SPDIFRX_HandleTypeDef *hspdif, HAL_SPDIFRX_CallbackIDTypeDef CallbackID);

+#endif /* USE_HAL_SPDIFRX_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/** @addtogroup SPDIFRX_Exported_Functions_Group2

+  * @{

+  */

+/* I/O operation functions  ***************************************************/

+ /* Blocking mode: Polling */

+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);

+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout);

+

+/* Non-Blocking mode: Interrupt */

+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);

+void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif);

+

+/* Non-Blocking mode: DMA */

+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveCtrlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif);

+

+/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/

+void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);

+void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);

+void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif);

+void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif);

+void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif);

+/**

+  * @}

+  */

+

+/** @addtogroup SPDIFRX_Exported_Functions_Group3

+  * @{

+  */

+/* Peripheral Control and State functions  ************************************/

+HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef const * const hspdif);

+uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef const * const hspdif);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup SPDIFRX_Private_Macros SPDIFRX Private Macros

+  * @{

+  */

+#define IS_SPDIFRX_INPUT_SELECT(INPUT)      (((INPUT) == SPDIFRX_INPUT_IN1) || \

+                                            ((INPUT) == SPDIFRX_INPUT_IN2)  || \

+                                            ((INPUT) == SPDIFRX_INPUT_IN3)  || \

+                                            ((INPUT) == SPDIFRX_INPUT_IN0))

+

+#define IS_SPDIFRX_MAX_RETRIES(RET)         (((RET) == SPDIFRX_MAXRETRIES_NONE) || \

+                                            ((RET) == SPDIFRX_MAXRETRIES_3)     || \

+                                            ((RET) == SPDIFRX_MAXRETRIES_15)    || \

+                                            ((RET) == SPDIFRX_MAXRETRIES_63))

+

+#define IS_SPDIFRX_WAIT_FOR_ACTIVITY(VAL)   (((VAL) == SPDIFRX_WAITFORACTIVITY_ON) || \

+                                            ((VAL) == SPDIFRX_WAITFORACTIVITY_OFF))

+

+#define IS_PREAMBLE_TYPE_MASK(VAL)          (((VAL) == SPDIFRX_PREAMBLETYPEMASK_ON) || \

+                                            ((VAL) == SPDIFRX_PREAMBLETYPEMASK_OFF))

+

+#define IS_VALIDITY_MASK(VAL)               (((VAL) == SPDIFRX_VALIDITYMASK_OFF) || \

+                                            ((VAL) == SPDIFRX_VALIDITYMASK_ON))

+

+#define IS_PARITY_ERROR_MASK(VAL)           (((VAL) == SPDIFRX_PARITYERRORMASK_OFF) || \

+                                            ((VAL) == SPDIFRX_PARITYERRORMASK_ON))

+

+#define IS_SPDIFRX_CHANNEL(CHANNEL)         (((CHANNEL) == SPDIFRX_CHANNEL_A) || \

+                                            ((CHANNEL) == SPDIFRX_CHANNEL_B))

+

+#define IS_SPDIFRX_DATA_FORMAT(FORMAT)      (((FORMAT) == SPDIFRX_DATAFORMAT_LSB) || \

+                                            ((FORMAT) == SPDIFRX_DATAFORMAT_MSB)  || \

+                                            ((FORMAT) == SPDIFRX_DATAFORMAT_32BITS))

+

+#define IS_STEREO_MODE(MODE)                (((MODE) == SPDIFRX_STEREOMODE_DISABLE) || \

+                                            ((MODE) == SPDIFRX_STEREOMODE_ENABLE))

+

+#define IS_CHANNEL_STATUS_MASK(VAL)         (((VAL) == SPDIFRX_CHANNELSTATUS_ON) || \

+                                            ((VAL) == SPDIFRX_CHANNELSTATUS_OFF))

+

+#define IS_SYMBOL_CLOCK_GEN(VAL)            (((VAL) == ENABLE) || ((VAL) == DISABLE))

+/**

+  * @}

+  */

+

+/* Private functions ---------------------------------------------------------*/

+/** @defgroup SPDIFRX_Private_Functions SPDIFRX Private Functions

+  * @{

+  */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+#endif /* SPDIFRX */

+/**

+  * @}

+  */

+

+

+#ifdef __cplusplus

+}

+#endif

+

+

+#endif /* __STM32H7xx_HAL_SPDIFRX_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_spi.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_spi.h
new file mode 100644
index 0000000000..3b5dab5806
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_spi.h
@@ -0,0 +1,1092 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_spi.h

+  * @author  MCD Application Team

+  * @brief   Header file of SPI HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_SPI_H

+#define STM32H7xx_HAL_SPI_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup SPI

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup SPI_Exported_Types SPI Exported Types

+  * @{

+  */

+

+/**

+  * @brief  SPI Configuration Structure definition

+  */

+typedef struct

+{

+  uint32_t Mode;                              /*!< Specifies the SPI operating mode.

+                                                     This parameter can be a value of @ref SPI_Mode */

+

+  uint32_t Direction;                         /*!< Specifies the SPI bidirectional mode state.

+                                                     This parameter can be a value of @ref SPI_Direction */

+

+  uint32_t DataSize;                          /*!< Specifies the SPI data size.

+                                                     This parameter can be a value of @ref SPI_Data_Size */

+

+  uint32_t CLKPolarity;                       /*!< Specifies the serial clock steady state.

+                                                     This parameter can be a value of @ref SPI_Clock_Polarity */

+

+  uint32_t CLKPhase;                          /*!< Specifies the clock active edge for the bit capture.

+                                                     This parameter can be a value of @ref SPI_Clock_Phase */

+

+  uint32_t NSS;                               /*!< Specifies whether the NSS signal is managed by

+                                                     hardware (NSS pin) or by software using the SSI bit.

+                                                     This parameter can be a value of @ref SPI_Slave_Select_Management */

+

+  uint32_t BaudRatePrescaler;                 /*!< Specifies the Baud Rate prescaler value which will be

+                                                     used to configure the transmit and receive SCK clock.

+                                                     This parameter can be a value of @ref SPI_BaudRate_Prescaler

+                                                     @note The communication clock is derived from the master

+                                                     clock. The slave clock does not need to be set. */

+

+  uint32_t FirstBit;                          /*!< Specifies whether data transfers start from MSB or LSB bit.

+                                                     This parameter can be a value of @ref SPI_MSB_LSB_Transmission */

+

+  uint32_t TIMode;                            /*!< Specifies if the TI mode is enabled or not.

+                                                     This parameter can be a value of @ref SPI_TI_Mode */

+

+  uint32_t CRCCalculation;                    /*!< Specifies if the CRC calculation is enabled or not.

+                                                     This parameter can be a value of @ref SPI_CRC_Calculation */

+

+  uint32_t CRCPolynomial;                     /*!< Specifies the polynomial used for the CRC calculation.

+                                                     This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535 */

+

+  uint32_t CRCLength;                         /*!< Specifies the CRC Length used for the CRC calculation.

+                                                     This parameter can be a value of @ref SPI_CRC_length */

+

+  uint32_t NSSPMode;                          /*!< Specifies whether the NSSP signal is enabled or not .

+                                                     This parameter can be a value of @ref SPI_NSSP_Mode

+                                                     This mode is activated by the SSOM bit in the SPIx_CR2 register and

+                                                     it takes effect only if the SPI interface is configured as Motorola SPI

+                                                     master (FRF=0). */

+

+  uint32_t NSSPolarity;                       /*!< Specifies which level of SS input/output external signal (present on SS pin) is

+                                                     considered as active one.

+                                                     This parameter can be a value of @ref SPI_NSS_Polarity */

+

+  uint32_t FifoThreshold;                     /*!< Specifies the FIFO threshold level.

+                                                     This parameter can be a value of @ref SPI_Fifo_Threshold */

+

+  uint32_t TxCRCInitializationPattern;        /*!< Specifies the transmitter CRC initialization Pattern used for the CRC calculation.

+                                                     This parameter can be a value of @ref SPI_CRC_Calculation_Initialization_Pattern */

+

+  uint32_t RxCRCInitializationPattern;        /*!< Specifies the receiver CRC initialization Pattern used for the CRC calculation.

+                                                     This parameter can be a value of @ref SPI_CRC_Calculation_Initialization_Pattern */

+

+  uint32_t MasterSSIdleness;                  /*!< Specifies an extra delay, expressed in number of SPI clock cycle periods, inserted

+                                                     additionally between active edge of SS and first data transaction start in master mode.

+                                                     This parameter can be a value of @ref SPI_Master_SS_Idleness */

+

+  uint32_t MasterInterDataIdleness;           /*!< Specifies minimum time delay (expressed in SPI clock cycles periods) inserted between

+                                                     two consecutive data frames in master mode

+                                                     This parameter can be a value of @ref SPI_Master_InterData_Idleness */

+

+  uint32_t MasterReceiverAutoSusp;            /*!< Control continuous SPI transfer in master receiver mode and automatic management

+                                                     in order to avoid overrun condition.

+                                                     This parameter can be a value of @ref SPI_Master_RX_AutoSuspend*/

+

+  uint32_t MasterKeepIOState;                 /*!< Control of Alternate function GPIOs state

+                                                     This parameter can be a value of @ref SPI_Master_Keep_IO_State */

+

+  uint32_t IOSwap;                            /*!< Invert MISO/MOSI alternate functions

+                                                     This parameter can be a value of @ref SPI_IO_Swap */

+

+} SPI_InitTypeDef;

+

+/**

+  * @brief  HAL SPI State structure definition

+  */

+typedef enum

+{

+  HAL_SPI_STATE_RESET      = 0x00UL,    /*!< Peripheral not Initialized                         */

+  HAL_SPI_STATE_READY      = 0x01UL,    /*!< Peripheral Initialized and ready for use           */

+  HAL_SPI_STATE_BUSY       = 0x02UL,    /*!< an internal process is ongoing                     */

+  HAL_SPI_STATE_BUSY_TX    = 0x03UL,    /*!< Data Transmission process is ongoing               */

+  HAL_SPI_STATE_BUSY_RX    = 0x04UL,    /*!< Data Reception process is ongoing                  */

+  HAL_SPI_STATE_BUSY_TX_RX = 0x05UL,    /*!< Data Transmission and Reception process is ongoing */

+  HAL_SPI_STATE_ERROR      = 0x06UL,    /*!< SPI error state                                    */

+  HAL_SPI_STATE_ABORT      = 0x07UL     /*!< SPI abort is ongoing                               */

+} HAL_SPI_StateTypeDef;

+

+#if defined(USE_SPI_RELOAD_TRANSFER)

+/**

+  * @brief  SPI Reload Structure definition

+  */

+typedef struct

+{

+  uint8_t                    *pTxBuffPtr;                  /*!< Pointer to SPI Tx transfer Buffer        */

+

+  uint16_t                   TxXferSize;                   /*!< SPI Tx Transfer size to reload           */

+

+  uint8_t                    *pRxBuffPtr;                  /*!< Pointer to SPI Rx transfer Buffer        */

+

+  uint16_t                   RxXferSize;                   /*!< SPI Rx Transfer size to reload           */

+

+  uint32_t                   Requested;                    /*!< SPI reload request                       */

+

+} SPI_ReloadTypeDef;

+#endif /* USE_HSPI_RELOAD_TRANSFER */

+

+/**

+  * @brief  SPI handle Structure definition

+  */

+typedef struct __SPI_HandleTypeDef

+{

+  SPI_TypeDef                *Instance;                    /*!< SPI registers base address               */

+

+  SPI_InitTypeDef            Init;                         /*!< SPI communication parameters             */

+

+  uint8_t                    *pTxBuffPtr;                  /*!< Pointer to SPI Tx transfer Buffer        */

+

+  uint16_t                   TxXferSize;                   /*!< SPI Tx Transfer size                     */

+

+  __IO uint16_t              TxXferCount;                  /*!< SPI Tx Transfer Counter                  */

+

+  uint8_t                    *pRxBuffPtr;                  /*!< Pointer to SPI Rx transfer Buffer        */

+

+  uint16_t                   RxXferSize;                   /*!< SPI Rx Transfer size                     */

+

+  __IO uint16_t              RxXferCount;                  /*!< SPI Rx Transfer Counter                  */

+

+  uint32_t                   CRCSize;                      /*!< SPI CRC size used for the transfer       */

+

+  void (*RxISR)(struct __SPI_HandleTypeDef *hspi);         /*!< function pointer on Rx ISR               */

+

+  void (*TxISR)(struct __SPI_HandleTypeDef *hspi);         /*!< function pointer on Tx ISR               */

+

+  DMA_HandleTypeDef          *hdmatx;                      /*!< SPI Tx DMA Handle parameters             */

+

+  DMA_HandleTypeDef          *hdmarx;                      /*!< SPI Rx DMA Handle parameters             */

+

+  HAL_LockTypeDef            Lock;                         /*!< Locking object                           */

+

+  __IO HAL_SPI_StateTypeDef  State;                        /*!< SPI communication state                  */

+

+  __IO uint32_t              ErrorCode;                    /*!< SPI Error code                           */

+  

+#if defined(USE_SPI_RELOAD_TRANSFER)

+

+  SPI_ReloadTypeDef          Reload;                       /*!< SPI reload parameters                    */

+  

+#endif /* USE_HSPI_RELOAD_TRANSFER */

+

+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)

+  void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi);       /*!< SPI Tx Completed callback          */

+  void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi);       /*!< SPI Rx Completed callback          */

+  void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi);     /*!< SPI TxRx Completed callback        */

+  void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);   /*!< SPI Tx Half Completed callback     */

+  void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi);   /*!< SPI Rx Half Completed callback     */

+  void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback   */

+  void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi);        /*!< SPI Error callback                 */

+  void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi);    /*!< SPI Abort callback                 */

+  void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi);      /*!< SPI Msp Init callback              */

+  void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi);    /*!< SPI Msp DeInit callback            */

+

+#endif  /* USE_HAL_SPI_REGISTER_CALLBACKS */

+} SPI_HandleTypeDef;

+

+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)

+/**

+  * @brief  HAL SPI Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_SPI_TX_COMPLETE_CB_ID             = 0x00UL,    /*!< SPI Tx Completed callback ID         */

+  HAL_SPI_RX_COMPLETE_CB_ID             = 0x01UL,    /*!< SPI Rx Completed callback ID         */

+  HAL_SPI_TX_RX_COMPLETE_CB_ID          = 0x02UL,    /*!< SPI TxRx Completed callback ID       */

+  HAL_SPI_TX_HALF_COMPLETE_CB_ID        = 0x03UL,    /*!< SPI Tx Half Completed callback ID    */

+  HAL_SPI_RX_HALF_COMPLETE_CB_ID        = 0x04UL,    /*!< SPI Rx Half Completed callback ID    */

+  HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID     = 0x05UL,    /*!< SPI TxRx Half Completed callback ID  */

+  HAL_SPI_ERROR_CB_ID                   = 0x06UL,    /*!< SPI Error callback ID                */

+  HAL_SPI_ABORT_CB_ID                   = 0x07UL,    /*!< SPI Abort callback ID                */

+  HAL_SPI_MSPINIT_CB_ID                 = 0x08UL,    /*!< SPI Msp Init callback ID             */

+  HAL_SPI_MSPDEINIT_CB_ID               = 0x09UL     /*!< SPI Msp DeInit callback ID           */

+

+} HAL_SPI_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL SPI Callback pointer definition

+  */

+typedef  void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */

+

+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+

+/** @defgroup SPI_Exported_Constants SPI Exported Constants

+  * @{

+  */

+

+/** @defgroup SPI_FIFO_Type SPI FIFO Type

+  * @{

+  */

+#define SPI_LOWEND_FIFO_SIZE                          8UL

+#define SPI_HIGHEND_FIFO_SIZE                         16UL

+/**

+  * @}

+  */

+

+/** @defgroup SPI_Error_Code SPI Error Codes

+  * @{

+  */

+#define HAL_SPI_ERROR_NONE                            (0x00000000UL)   /*!< No error                               */

+#define HAL_SPI_ERROR_MODF                            (0x00000001UL)   /*!< MODF error                             */

+#define HAL_SPI_ERROR_CRC                             (0x00000002UL)   /*!< CRC error                              */

+#define HAL_SPI_ERROR_OVR                             (0x00000004UL)   /*!< OVR error                              */

+#define HAL_SPI_ERROR_FRE                             (0x00000008UL)   /*!< FRE error                              */

+#define HAL_SPI_ERROR_DMA                             (0x00000010UL)   /*!< DMA transfer error                     */

+#define HAL_SPI_ERROR_FLAG                            (0x00000020UL)   /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */

+#define HAL_SPI_ERROR_ABORT                           (0x00000040UL)   /*!< Error during SPI Abort procedure       */

+#define HAL_SPI_ERROR_UDR                             (0x00000080UL)   /*!< Underrun error                         */

+#define HAL_SPI_ERROR_TIMEOUT                         (0x00000100UL)   /*!< Timeout error                          */

+#define HAL_SPI_ERROR_UNKNOW                          (0x00000200UL)   /*!< Unknow error                           */

+#define HAL_SPI_ERROR_NOT_SUPPORTED                   (0x00000400UL)   /*!< Requested operation not supported      */

+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)

+#define HAL_SPI_ERROR_INVALID_CALLBACK                (0x00000800UL)   /*!< Invalid Callback error                 */

+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/** @defgroup SPI_Mode SPI Mode

+  * @{

+  */

+#define SPI_MODE_SLAVE                                (0x00000000UL)

+#define SPI_MODE_MASTER                               SPI_CFG2_MASTER

+/**

+  * @}

+  */

+

+/** @defgroup SPI_Direction SPI Direction Mode

+  * @{

+  */

+#define SPI_DIRECTION_2LINES                          (0x00000000UL)

+#define SPI_DIRECTION_2LINES_TXONLY                   SPI_CFG2_COMM_0

+#define SPI_DIRECTION_2LINES_RXONLY                   SPI_CFG2_COMM_1

+#define SPI_DIRECTION_1LINE                           SPI_CFG2_COMM

+/**

+  * @}

+  */

+

+/** @defgroup SPI_Data_Size SPI Data Size

+  * @{

+  */

+#define SPI_DATASIZE_4BIT                             (0x00000003UL)

+#define SPI_DATASIZE_5BIT                             (0x00000004UL)

+#define SPI_DATASIZE_6BIT                             (0x00000005UL)

+#define SPI_DATASIZE_7BIT                             (0x00000006UL)

+#define SPI_DATASIZE_8BIT                             (0x00000007UL)

+#define SPI_DATASIZE_9BIT                             (0x00000008UL)

+#define SPI_DATASIZE_10BIT                            (0x00000009UL)

+#define SPI_DATASIZE_11BIT                            (0x0000000AUL)

+#define SPI_DATASIZE_12BIT                            (0x0000000BUL)

+#define SPI_DATASIZE_13BIT                            (0x0000000CUL)

+#define SPI_DATASIZE_14BIT                            (0x0000000DUL)

+#define SPI_DATASIZE_15BIT                            (0x0000000EUL)

+#define SPI_DATASIZE_16BIT                            (0x0000000FUL)

+#define SPI_DATASIZE_17BIT                            (0x00000010UL)

+#define SPI_DATASIZE_18BIT                            (0x00000011UL)

+#define SPI_DATASIZE_19BIT                            (0x00000012UL)

+#define SPI_DATASIZE_20BIT                            (0x00000013UL)

+#define SPI_DATASIZE_21BIT                            (0x00000014UL)

+#define SPI_DATASIZE_22BIT                            (0x00000015UL)

+#define SPI_DATASIZE_23BIT                            (0x00000016UL)

+#define SPI_DATASIZE_24BIT                            (0x00000017UL)

+#define SPI_DATASIZE_25BIT                            (0x00000018UL)

+#define SPI_DATASIZE_26BIT                            (0x00000019UL)

+#define SPI_DATASIZE_27BIT                            (0x0000001AUL)

+#define SPI_DATASIZE_28BIT                            (0x0000001BUL)

+#define SPI_DATASIZE_29BIT                            (0x0000001CUL)

+#define SPI_DATASIZE_30BIT                            (0x0000001DUL)

+#define SPI_DATASIZE_31BIT                            (0x0000001EUL)

+#define SPI_DATASIZE_32BIT                            (0x0000001FUL)

+/**

+  * @}

+  */

+

+/** @defgroup SPI_Clock_Polarity SPI Clock Polarity

+  * @{

+  */

+#define SPI_POLARITY_LOW                              (0x00000000UL)

+#define SPI_POLARITY_HIGH                             SPI_CFG2_CPOL

+/**

+  * @}

+  */

+

+/** @defgroup SPI_Clock_Phase SPI Clock Phase

+  * @{

+  */

+#define SPI_PHASE_1EDGE                               (0x00000000UL)

+#define SPI_PHASE_2EDGE                               SPI_CFG2_CPHA

+/**

+  * @}

+  */

+

+/** @defgroup SPI_Slave_Select_Management SPI Slave Select Management

+  * @{

+  */

+#define SPI_NSS_SOFT                                  SPI_CFG2_SSM

+#define SPI_NSS_HARD_INPUT                            (0x00000000UL)

+#define SPI_NSS_HARD_OUTPUT                           SPI_CFG2_SSOE

+/**

+  * @}

+  */

+

+/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode

+  * @{

+  */

+#define SPI_NSS_PULSE_DISABLE                         (0x00000000UL)

+#define SPI_NSS_PULSE_ENABLE                          SPI_CFG2_SSOM

+/**

+  * @}

+  */

+

+/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler

+  * @{

+  */

+#define SPI_BAUDRATEPRESCALER_2                       (0x00000000UL)

+#define SPI_BAUDRATEPRESCALER_4                       (0x10000000UL)

+#define SPI_BAUDRATEPRESCALER_8                       (0x20000000UL)

+#define SPI_BAUDRATEPRESCALER_16                      (0x30000000UL)

+#define SPI_BAUDRATEPRESCALER_32                      (0x40000000UL)

+#define SPI_BAUDRATEPRESCALER_64                      (0x50000000UL)

+#define SPI_BAUDRATEPRESCALER_128                     (0x60000000UL)

+#define SPI_BAUDRATEPRESCALER_256                     (0x70000000UL)

+/**

+  * @}

+  */

+

+/** @defgroup SPI_MSB_LSB_Transmission SPI MSB LSB Transmission

+  * @{

+  */

+#define SPI_FIRSTBIT_MSB                              (0x00000000UL)

+#define SPI_FIRSTBIT_LSB                              SPI_CFG2_LSBFRST

+/**

+  * @}

+  */

+

+/** @defgroup SPI_TI_Mode SPI TI Mode

+  * @{

+  */

+#define SPI_TIMODE_DISABLE                            (0x00000000UL)

+#define SPI_TIMODE_ENABLE                             SPI_CFG2_SP_0

+/**

+  * @}

+  */

+

+/** @defgroup SPI_CRC_Calculation SPI CRC Calculation

+  * @{

+  */

+#define SPI_CRCCALCULATION_DISABLE                    (0x00000000UL)

+#define SPI_CRCCALCULATION_ENABLE                     SPI_CFG1_CRCEN

+/**

+  * @}

+  */

+

+/** @defgroup SPI_CRC_length SPI CRC Length

+  * @{

+  */

+#define SPI_CRC_LENGTH_DATASIZE                       (0x00000000UL)

+#define SPI_CRC_LENGTH_4BIT                           (0x00030000UL)

+#define SPI_CRC_LENGTH_5BIT                           (0x00040000UL)

+#define SPI_CRC_LENGTH_6BIT                           (0x00050000UL)

+#define SPI_CRC_LENGTH_7BIT                           (0x00060000UL)

+#define SPI_CRC_LENGTH_8BIT                           (0x00070000UL)

+#define SPI_CRC_LENGTH_9BIT                           (0x00080000UL)

+#define SPI_CRC_LENGTH_10BIT                          (0x00090000UL)

+#define SPI_CRC_LENGTH_11BIT                          (0x000A0000UL)

+#define SPI_CRC_LENGTH_12BIT                          (0x000B0000UL)

+#define SPI_CRC_LENGTH_13BIT                          (0x000C0000UL)

+#define SPI_CRC_LENGTH_14BIT                          (0x000D0000UL)

+#define SPI_CRC_LENGTH_15BIT                          (0x000E0000UL)

+#define SPI_CRC_LENGTH_16BIT                          (0x000F0000UL)

+#define SPI_CRC_LENGTH_17BIT                          (0x00100000UL)

+#define SPI_CRC_LENGTH_18BIT                          (0x00110000UL)

+#define SPI_CRC_LENGTH_19BIT                          (0x00120000UL)

+#define SPI_CRC_LENGTH_20BIT                          (0x00130000UL)

+#define SPI_CRC_LENGTH_21BIT                          (0x00140000UL)

+#define SPI_CRC_LENGTH_22BIT                          (0x00150000UL)

+#define SPI_CRC_LENGTH_23BIT                          (0x00160000UL)

+#define SPI_CRC_LENGTH_24BIT                          (0x00170000UL)

+#define SPI_CRC_LENGTH_25BIT                          (0x00180000UL)

+#define SPI_CRC_LENGTH_26BIT                          (0x00190000UL)

+#define SPI_CRC_LENGTH_27BIT                          (0x001A0000UL)

+#define SPI_CRC_LENGTH_28BIT                          (0x001B0000UL)

+#define SPI_CRC_LENGTH_29BIT                          (0x001C0000UL)

+#define SPI_CRC_LENGTH_30BIT                          (0x001D0000UL)

+#define SPI_CRC_LENGTH_31BIT                          (0x001E0000UL)

+#define SPI_CRC_LENGTH_32BIT                          (0x001F0000UL)

+/**

+  * @}

+  */

+

+/** @defgroup SPI_Fifo_Threshold SPI Fifo Threshold

+  * @{

+  */

+#define SPI_FIFO_THRESHOLD_01DATA                     (0x00000000UL)

+#define SPI_FIFO_THRESHOLD_02DATA                     (0x00000020UL)

+#define SPI_FIFO_THRESHOLD_03DATA                     (0x00000040UL)

+#define SPI_FIFO_THRESHOLD_04DATA                     (0x00000060UL)

+#define SPI_FIFO_THRESHOLD_05DATA                     (0x00000080UL)

+#define SPI_FIFO_THRESHOLD_06DATA                     (0x000000A0UL)

+#define SPI_FIFO_THRESHOLD_07DATA                     (0x000000C0UL)

+#define SPI_FIFO_THRESHOLD_08DATA                     (0x000000E0UL)

+#define SPI_FIFO_THRESHOLD_09DATA                     (0x00000100UL)

+#define SPI_FIFO_THRESHOLD_10DATA                     (0x00000120UL)

+#define SPI_FIFO_THRESHOLD_11DATA                     (0x00000140UL)

+#define SPI_FIFO_THRESHOLD_12DATA                     (0x00000160UL)

+#define SPI_FIFO_THRESHOLD_13DATA                     (0x00000180UL)

+#define SPI_FIFO_THRESHOLD_14DATA                     (0x000001A0UL)

+#define SPI_FIFO_THRESHOLD_15DATA                     (0x000001C0UL)

+#define SPI_FIFO_THRESHOLD_16DATA                     (0x000001E0UL)

+/**

+  * @}

+  */

+

+/** @defgroup SPI_CRC_Calculation_Initialization_Pattern SPI CRC Calculation Initialization Pattern

+  * @{

+  */

+#define SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN       (0x00000000UL)

+#define SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN        (0x00000001UL)

+/**

+  * @}

+  */

+

+/** @defgroup SPI_NSS_Polarity SPI NSS Polarity

+  * @{

+  */

+#define SPI_NSS_POLARITY_LOW                          (0x00000000UL)

+#define SPI_NSS_POLARITY_HIGH                          SPI_CFG2_SSIOP

+/**

+  * @}

+  */

+

+/** @defgroup SPI_Master_Keep_IO_State Keep IO State

+  * @{

+  */

+#define SPI_MASTER_KEEP_IO_STATE_DISABLE              (0x00000000UL)

+#define SPI_MASTER_KEEP_IO_STATE_ENABLE               SPI_CFG2_AFCNTR

+/**

+  * @}

+  */

+

+/** @defgroup SPI_IO_Swap Control SPI IO Swap

+  * @{

+  */

+#define SPI_IO_SWAP_DISABLE                           (0x00000000UL)

+#define SPI_IO_SWAP_ENABLE                            SPI_CFG2_IOSWP

+/**

+  * @}

+  */

+

+/** @defgroup SPI_Master_SS_Idleness SPI Master SS Idleness

+  * @{

+  */

+#define SPI_MASTER_SS_IDLENESS_00CYCLE                (0x00000000UL)

+#define SPI_MASTER_SS_IDLENESS_01CYCLE                (0x00000001UL)

+#define SPI_MASTER_SS_IDLENESS_02CYCLE                (0x00000002UL)

+#define SPI_MASTER_SS_IDLENESS_03CYCLE                (0x00000003UL)

+#define SPI_MASTER_SS_IDLENESS_04CYCLE                (0x00000004UL)

+#define SPI_MASTER_SS_IDLENESS_05CYCLE                (0x00000005UL)

+#define SPI_MASTER_SS_IDLENESS_06CYCLE                (0x00000006UL)

+#define SPI_MASTER_SS_IDLENESS_07CYCLE                (0x00000007UL)

+#define SPI_MASTER_SS_IDLENESS_08CYCLE                (0x00000008UL)

+#define SPI_MASTER_SS_IDLENESS_09CYCLE                (0x00000009UL)

+#define SPI_MASTER_SS_IDLENESS_10CYCLE                (0x0000000AUL)

+#define SPI_MASTER_SS_IDLENESS_11CYCLE                (0x0000000BUL)

+#define SPI_MASTER_SS_IDLENESS_12CYCLE                (0x0000000CUL)

+#define SPI_MASTER_SS_IDLENESS_13CYCLE                (0x0000000DUL)

+#define SPI_MASTER_SS_IDLENESS_14CYCLE                (0x0000000EUL)

+#define SPI_MASTER_SS_IDLENESS_15CYCLE                (0x0000000FUL)

+/**

+  * @}

+  */

+

+/** @defgroup SPI_Master_InterData_Idleness SPI Master Inter-Data Idleness

+  * @{

+  */

+#define SPI_MASTER_INTERDATA_IDLENESS_00CYCLE         (0x00000000UL)

+#define SPI_MASTER_INTERDATA_IDLENESS_01CYCLE         (0x00000010UL)

+#define SPI_MASTER_INTERDATA_IDLENESS_02CYCLE         (0x00000020UL)

+#define SPI_MASTER_INTERDATA_IDLENESS_03CYCLE         (0x00000030UL)

+#define SPI_MASTER_INTERDATA_IDLENESS_04CYCLE         (0x00000040UL)

+#define SPI_MASTER_INTERDATA_IDLENESS_05CYCLE         (0x00000050UL)

+#define SPI_MASTER_INTERDATA_IDLENESS_06CYCLE         (0x00000060UL)

+#define SPI_MASTER_INTERDATA_IDLENESS_07CYCLE         (0x00000070UL)

+#define SPI_MASTER_INTERDATA_IDLENESS_08CYCLE         (0x00000080UL)

+#define SPI_MASTER_INTERDATA_IDLENESS_09CYCLE         (0x00000090UL)

+#define SPI_MASTER_INTERDATA_IDLENESS_10CYCLE         (0x000000A0UL)

+#define SPI_MASTER_INTERDATA_IDLENESS_11CYCLE         (0x000000B0UL)

+#define SPI_MASTER_INTERDATA_IDLENESS_12CYCLE         (0x000000C0UL)

+#define SPI_MASTER_INTERDATA_IDLENESS_13CYCLE         (0x000000D0UL)

+#define SPI_MASTER_INTERDATA_IDLENESS_14CYCLE         (0x000000E0UL)

+#define SPI_MASTER_INTERDATA_IDLENESS_15CYCLE         (0x000000F0UL)

+/**

+  * @}

+  */

+

+/** @defgroup SPI_Master_RX_AutoSuspend SPI Master Receiver AutoSuspend

+  * @{

+  */

+#define SPI_MASTER_RX_AUTOSUSP_DISABLE                (0x00000000UL)

+#define SPI_MASTER_RX_AUTOSUSP_ENABLE                 SPI_CR1_MASRX

+/**

+  * @}

+  */

+

+/** @defgroup SPI_Underrun_Detection SPI Underrun Detection

+  * @{

+  */

+#define SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME          (0x00000000UL)

+#define SPI_UNDERRUN_DETECT_END_DATA_FRAME            SPI_CFG1_UDRDET_0

+#define SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS          SPI_CFG1_UDRDET_1

+/**

+  * @}

+  */

+

+/** @defgroup SPI_Underrun_Behaviour SPI Underrun Behavior

+  * @{

+  */

+#define SPI_UNDERRUN_BEHAV_REGISTER_PATTERN           (0x00000000UL)

+#define SPI_UNDERRUN_BEHAV_LAST_RECEIVED              SPI_CFG1_UDRCFG_0

+#define SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED           SPI_CFG1_UDRCFG_1

+/**

+  * @}

+  */

+

+/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition

+  * @{

+  */

+#define SPI_IT_RXP                      SPI_IER_RXPIE

+#define SPI_IT_TXP                      SPI_IER_TXPIE

+#define SPI_IT_DXP                      SPI_IER_DXPIE

+#define SPI_IT_EOT                      SPI_IER_EOTIE

+#define SPI_IT_TXTF                     SPI_IER_TXTFIE

+#define SPI_IT_UDR                      SPI_IER_UDRIE

+#define SPI_IT_OVR                      SPI_IER_OVRIE

+#define SPI_IT_CRCERR                   SPI_IER_CRCEIE

+#define SPI_IT_FRE                      SPI_IER_TIFREIE

+#define SPI_IT_MODF                     SPI_IER_MODFIE

+#define SPI_IT_TSERF                    SPI_IER_TSERFIE

+#define SPI_IT_ERR                      (SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_CRCERR)

+/**

+  * @}

+  */

+

+/** @defgroup SPI_Flags_definition SPI Flags Definition

+  * @{

+  */

+#define SPI_FLAG_RXP                    SPI_SR_RXP     /* SPI status flag : Rx-Packet available flag                 */

+#define SPI_FLAG_TXP                    SPI_SR_TXP     /* SPI status flag : Tx-Packet space available flag           */

+#define SPI_FLAG_DXP                    SPI_SR_DXP     /* SPI status flag : Duplex Packet flag                       */

+#define SPI_FLAG_EOT                    SPI_SR_EOT     /* SPI status flag : End of transfer flag                     */

+#define SPI_FLAG_TXTF                   SPI_SR_TXTF    /* SPI status flag : Transmission Transfer Filled flag        */

+#define SPI_FLAG_UDR                    SPI_SR_UDR     /* SPI Error flag  : Underrun flag                            */

+#define SPI_FLAG_OVR                    SPI_SR_OVR     /* SPI Error flag  : Overrun flag                             */

+#define SPI_FLAG_CRCERR                 SPI_SR_CRCE    /* SPI Error flag  : CRC error flag                           */

+#define SPI_FLAG_FRE                    SPI_SR_TIFRE   /* SPI Error flag  : TI mode frame format error flag          */

+#define SPI_FLAG_MODF                   SPI_SR_MODF    /* SPI Error flag  : Mode fault flag                          */

+#define SPI_FLAG_TSERF                  SPI_SR_TSERF   /* SPI status flag : Additional number of data reloaded flag  */

+#define SPI_FLAG_SUSP                   SPI_SR_SUSP    /* SPI status flag : Transfer suspend complete flag           */

+#define SPI_FLAG_TXC                    SPI_SR_TXC     /* SPI status flag : TxFIFO transmission complete flag        */

+#define SPI_FLAG_FRLVL                  SPI_SR_RXPLVL  /* SPI status flag : Fifo reception level flag                */

+#define SPI_FLAG_RXWNE                  SPI_SR_RXWNE   /* SPI status flag : RxFIFO word not empty flag               */

+/**

+  * @}

+  */

+

+/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level

+  * @{

+  */

+#define SPI_RX_FIFO_0PACKET                           (0x00000000UL)                      /* 0 or multiple of 4 packets available in the RxFIFO */

+#define SPI_RX_FIFO_1PACKET                           (SPI_SR_RXPLVL_0)

+#define SPI_RX_FIFO_2PACKET                           (SPI_SR_RXPLVL_1)

+#define SPI_RX_FIFO_3PACKET                           (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macros -----------------------------------------------------------*/

+/** @defgroup SPI_Exported_Macros SPI Exported Macros

+  * @{

+  */

+

+/** @brief  Reset SPI handle state.

+  * @param  __HANDLE__: specifies the SPI Handle.

+  *         This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.

+  * @retval None

+  */

+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL)

+#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__)   do{                                                  \

+                                                       (__HANDLE__)->State = HAL_SPI_STATE_RESET;       \

+                                                       (__HANDLE__)->MspInitCallback = NULL;            \

+                                                       (__HANDLE__)->MspDeInitCallback = NULL;          \

+                                                     } while(0)

+#else

+#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)

+#endif

+

+/** @brief  Enable the specified SPI interrupts.

+  * @param  __HANDLE__: specifies the SPI Handle.

+  *         This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.

+  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.

+  *         This parameter can be one of the following values:

+  *            @arg SPI_IT_RXP    : Rx-Packet available interrupt

+  *            @arg SPI_IT_TXP    : Tx-Packet space available interrupt

+  *            @arg SPI_IT_DXP    : Duplex Packet interrupt

+  *            @arg SPI_IT_EOT    : End of transfer interrupt

+  *            @arg SPI_IT_TXTF   : Transmission Transfer Filled interrupt

+  *            @arg SPI_IT_UDR    : Underrun interrupt

+  *            @arg SPI_IT_OVR    : Overrun  interrupt

+  *            @arg SPI_IT_CRCERR : CRC error interrupt

+  *            @arg SPI_IT_FRE    : TI mode frame format error interrupt

+  *            @arg SPI_IT_MODF   : Mode fault interrupt

+  *            @arg SPI_IT_TSERF  : Additional number of data reloaded interrupt

+  *            @arg SPI_IT_ERR    : Error interrupt

+  * @retval None

+  */

+#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))

+

+/** @brief  Disable the specified SPI interrupts.

+  * @param  __HANDLE__: specifies the SPI Handle.

+  *         This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.

+  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.

+  *         This parameter can be one of the following values:

+  *            @arg SPI_IT_RXP    : Rx-Packet available interrupt

+  *            @arg SPI_IT_TXP    : Tx-Packet space available interrupt

+  *            @arg SPI_IT_DXP    : Duplex Packet interrupt

+  *            @arg SPI_IT_EOT    : End of transfer interrupt

+  *            @arg SPI_IT_TXTF   : Transmission Transfer Filled interrupt

+  *            @arg SPI_IT_UDR    : Underrun interrupt

+  *            @arg SPI_IT_OVR    : Overrun  interrupt

+  *            @arg SPI_IT_CRCERR : CRC error interrupt

+  *            @arg SPI_IT_FRE    : TI mode frame format error interrupt

+  *            @arg SPI_IT_MODF   : Mode fault interrupt

+  *            @arg SPI_IT_TSERF  : Additional number of data reloaded interrupt

+  *            @arg SPI_IT_ERR    : Error interrupt

+  * @retval None

+  */

+#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))

+

+/** @brief  Check whether the specified SPI interrupt source is enabled or not.

+  * @param  __HANDLE__: specifies the SPI Handle.

+  *         This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.

+  * @param  __INTERRUPT__: specifies the SPI interrupt source to check.

+  *          This parameter can be one of the following values:

+  *            @arg SPI_IT_RXP    : Rx-Packet available interrupt

+  *            @arg SPI_IT_TXP    : Tx-Packet space available interrupt

+  *            @arg SPI_IT_DXP    : Duplex Packet interrupt

+  *            @arg SPI_IT_EOT    : End of transfer interrupt

+  *            @arg SPI_IT_TXTF   : Transmission Transfer Filled interrupt

+  *            @arg SPI_IT_UDR    : Underrun interrupt

+  *            @arg SPI_IT_OVR    : Overrun  interrupt

+  *            @arg SPI_IT_CRCERR : CRC error interrupt

+  *            @arg SPI_IT_FRE    : TI mode frame format error interrupt

+  *            @arg SPI_IT_MODF   : Mode fault interrupt

+  *            @arg SPI_IT_TSERF  : Additional number of data reloaded interrupt

+  *            @arg SPI_IT_ERR    : Error interrupt

+  * @retval The new state of __IT__ (TRUE or FALSE).

+  */

+#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)

+

+/** @brief  Check whether the specified SPI flag is set or not.

+  * @param  __HANDLE__: specifies the SPI Handle.

+  *         This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral.

+  * @param  __FLAG__: specifies the flag to check.

+  *         This parameter can be one of the following values:

+  *            @arg SPI_FLAG_RXP    : Rx-Packet available flag

+  *            @arg SPI_FLAG_TXP    : Tx-Packet space available flag

+  *            @arg SPI_FLAG_DXP    : Duplex Packet flag

+  *            @arg SPI_FLAG_EOT    : End of transfer flag

+  *            @arg SPI_FLAG_TXTF   : Transmission Transfer Filled flag

+  *            @arg SPI_FLAG_UDR    : Underrun flag

+  *            @arg SPI_FLAG_OVR    : Overrun flag

+  *            @arg SPI_FLAG_CRCERR : CRC error flag

+  *            @arg SPI_FLAG_FRE    : TI mode frame format error flag

+  *            @arg SPI_FLAG_MODF   : Mode fault flag

+  *            @arg SPI_FLAG_TSERF  : Additional number of data reloaded flag

+  *            @arg SPI_FLAG_SUSP   : Transfer suspend complete flag

+  *            @arg SPI_FLAG_TXC    : TxFIFO transmission complete flag

+  *            @arg SPI_FLAG_FRLVL  : Fifo reception level flag

+  *            @arg SPI_FLAG_RXWNE  : RxFIFO word not empty flag

+  * @retval The new state of __FLAG__ (TRUE or FALSE).

+  */

+#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))

+

+/** @brief  Clear the SPI CRCERR pending flag.

+  * @param  __HANDLE__: specifies the SPI Handle.

+  * @retval None

+  */

+#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_CRCEC)

+

+/** @brief  Clear the SPI MODF pending flag.

+  * @param  __HANDLE__: specifies the SPI Handle.

+  * @retval None

+  */

+#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->IFCR , (uint32_t)(SPI_IFCR_MODFC));

+

+/** @brief  Clear the SPI OVR pending flag.

+  * @param  __HANDLE__: specifies the SPI Handle.

+  * @retval None

+  */

+#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC)

+

+/** @brief  Clear the SPI FRE pending flag.

+  * @param  __HANDLE__: specifies the SPI Handle.

+  * @retval None

+  */

+#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC)

+

+/** @brief  Clear the SPI UDR pending flag.

+  * @param  __HANDLE__: specifies the SPI Handle.

+  * @retval None

+  */

+#define __HAL_SPI_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC)

+

+/** @brief  Clear the SPI EOT pending flag.

+  * @param  __HANDLE__: specifies the SPI Handle.

+  * @retval None

+  */

+#define __HAL_SPI_CLEAR_EOTFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_EOTC)

+

+/** @brief  Clear the SPI UDR pending flag.

+  * @param  __HANDLE__: specifies the SPI Handle.

+  * @retval None

+  */

+#define __HAL_SPI_CLEAR_TXTFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TXTFC)

+

+/** @brief  Clear the SPI SUSP pending flag.

+  * @param  __HANDLE__: specifies the SPI Handle.

+  * @retval None

+  */

+#define __HAL_SPI_CLEAR_SUSPFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_SUSPC)

+

+/** @brief  Clear the SPI TSERF pending flag.

+  * @param  __HANDLE__: specifies the SPI Handle.

+  * @retval None

+  */

+#define __HAL_SPI_CLEAR_TSERFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TSERFC)

+

+/** @brief  Enable the SPI peripheral.

+  * @param  __HANDLE__: specifies the SPI Handle.

+  * @retval None

+  */

+#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)

+

+/** @brief  Disable the SPI peripheral.

+  * @param  __HANDLE__: specifies the SPI Handle.

+  * @retval None

+  */

+#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE)

+/**

+  * @}

+  */

+

+

+/* Include SPI HAL Extension module */

+#include "stm32h7xx_hal_spi_ex.h"

+

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup SPI_Exported_Functions

+  * @{

+  */

+

+/** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions

+  * @{

+  */

+/* Initialization/de-initialization functions  ********************************/

+HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);

+HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);

+void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);

+void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);

+

+/* Callbacks Register/UnRegister functions  ***********************************/

+#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U)

+HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID);

+#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/** @addtogroup SPI_Exported_Functions_Group2 IO operation functions

+  * @{

+  */

+/* I/O operation functions  ***************************************************/

+HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);

+HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);

+HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,

+                                          uint32_t Timeout);

+HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);

+

+HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);

+

+#if defined(USE_SPI_RELOAD_TRANSFER)

+HAL_StatusTypeDef HAL_SPI_Reload_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_SPI_Reload_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_SPI_Reload_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);

+#endif /* USE_HSPI_RELOAD_TRANSFER */

+

+HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);

+HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);

+HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);

+

+/* Transfer Abort functions */

+HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);

+HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);

+

+void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);

+void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);

+void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);

+void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);

+void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);

+void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);

+void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);

+void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);

+void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);

+/**

+  * @}

+  */

+

+/** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions

+  * @{

+  */

+

+/* Peripheral State and Error functions ***************************************/

+HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);

+uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup SPI_Private_Macros SPI Private Macros

+  * @{

+  */

+

+/** @brief  Set the SPI transmit-only mode.

+  * @param  __HANDLE__: specifies the SPI Handle.

+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.

+  * @retval None

+  */

+#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_HDDIR)

+

+/** @brief  Set the SPI receive-only mode.

+  * @param  __HANDLE__: specifies the SPI Handle.

+  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.

+  * @retval None

+  */

+#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 ,SPI_CR1_HDDIR)

+

+#define IS_SPI_MODE(MODE)                          (((MODE) == SPI_MODE_SLAVE) || \

+                                                    ((MODE) == SPI_MODE_MASTER))

+

+#define IS_SPI_DIRECTION(MODE)                     (((MODE) == SPI_DIRECTION_2LINES)        || \

+                                                    ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \

+                                                    ((MODE) == SPI_DIRECTION_1LINE)         || \

+                                                    ((MODE) == SPI_DIRECTION_2LINES_TXONLY))

+

+#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)

+

+#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE) (                         \

+                                                    ((MODE) == SPI_DIRECTION_2LINES)|| \

+                                                    ((MODE) == SPI_DIRECTION_1LINE) || \

+                                                    ((MODE) == SPI_DIRECTION_2LINES_TXONLY))

+

+#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE) (                         \

+                                                    ((MODE) == SPI_DIRECTION_2LINES)|| \

+                                                    ((MODE) == SPI_DIRECTION_1LINE) || \

+                                                    ((MODE) == SPI_DIRECTION_2LINES_RXONLY))

+

+#define IS_SPI_DATASIZE(DATASIZE)                  (((DATASIZE) == SPI_DATASIZE_32BIT) || \

+                                                    ((DATASIZE) == SPI_DATASIZE_31BIT) || \

+                                                    ((DATASIZE) == SPI_DATASIZE_30BIT) || \

+                                                    ((DATASIZE) == SPI_DATASIZE_29BIT) || \

+                                                    ((DATASIZE) == SPI_DATASIZE_28BIT) || \

+                                                    ((DATASIZE) == SPI_DATASIZE_27BIT) || \

+                                                    ((DATASIZE) == SPI_DATASIZE_26BIT) || \

+                                                    ((DATASIZE) == SPI_DATASIZE_25BIT) || \

+                                                    ((DATASIZE) == SPI_DATASIZE_24BIT) || \

+                                                    ((DATASIZE) == SPI_DATASIZE_23BIT) || \

+                                                    ((DATASIZE) == SPI_DATASIZE_22BIT) || \

+                                                    ((DATASIZE) == SPI_DATASIZE_21BIT) || \

+                                                    ((DATASIZE) == SPI_DATASIZE_20BIT) || \

+                                                    ((DATASIZE) == SPI_DATASIZE_22BIT) || \

+                                                    ((DATASIZE) == SPI_DATASIZE_19BIT) || \

+                                                    ((DATASIZE) == SPI_DATASIZE_18BIT) || \

+                                                    ((DATASIZE) == SPI_DATASIZE_17BIT) || \

+                                                    ((DATASIZE) == SPI_DATASIZE_16BIT) || \

+                                                    ((DATASIZE) == SPI_DATASIZE_15BIT) || \

+                                                    ((DATASIZE) == SPI_DATASIZE_14BIT) || \

+                                                    ((DATASIZE) == SPI_DATASIZE_13BIT) || \

+                                                    ((DATASIZE) == SPI_DATASIZE_12BIT) || \

+                                                    ((DATASIZE) == SPI_DATASIZE_11BIT) || \

+                                                    ((DATASIZE) == SPI_DATASIZE_10BIT) || \

+                                                    ((DATASIZE) == SPI_DATASIZE_9BIT)  || \

+                                                    ((DATASIZE) == SPI_DATASIZE_8BIT)  || \

+                                                    ((DATASIZE) == SPI_DATASIZE_7BIT)  || \

+                                                    ((DATASIZE) == SPI_DATASIZE_6BIT)  || \

+                                                    ((DATASIZE) == SPI_DATASIZE_5BIT)  || \

+                                                    ((DATASIZE) == SPI_DATASIZE_4BIT))

+

+#define IS_SPI_FIFOTHRESHOLD(THRESHOLD)            (((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \

+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \

+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \

+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \

+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \

+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \

+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \

+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA) || \

+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_09DATA) || \

+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_10DATA) || \

+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_11DATA) || \

+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_12DATA) || \

+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_13DATA) || \

+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_14DATA) || \

+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_15DATA) || \

+                                                    ((THRESHOLD) == SPI_FIFO_THRESHOLD_16DATA))

+

+#define IS_SPI_CPOL(CPOL)                          (((CPOL) == SPI_POLARITY_LOW) || \

+                                                    ((CPOL) == SPI_POLARITY_HIGH))

+

+#define IS_SPI_CPHA(CPHA)                          (((CPHA) == SPI_PHASE_1EDGE) || \

+                                                    ((CPHA) == SPI_PHASE_2EDGE))

+

+#define IS_SPI_NSS(NSS)                            (((NSS) == SPI_NSS_SOFT)       || \

+                                                    ((NSS) == SPI_NSS_HARD_INPUT) || \

+                                                    ((NSS) == SPI_NSS_HARD_OUTPUT))

+

+#define IS_SPI_NSSP(NSSP)                          (((NSSP) == SPI_NSS_PULSE_ENABLE) || \

+                                                    ((NSSP) == SPI_NSS_PULSE_DISABLE))

+

+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER)       (((PRESCALER) == SPI_BAUDRATEPRESCALER_2)   || \

+                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_4)   || \

+                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_8)   || \

+                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_16)  || \

+                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_32)  || \

+                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_64)  || \

+                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \

+                                                    ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))

+

+#define IS_SPI_FIRST_BIT(BIT)                      (((BIT) == SPI_FIRSTBIT_MSB) || \

+                                                    ((BIT) == SPI_FIRSTBIT_LSB))

+

+#define IS_SPI_TIMODE(MODE)                        (((MODE) == SPI_TIMODE_DISABLE) || \

+                                                    ((MODE) == SPI_TIMODE_ENABLE))

+

+#define IS_SPI_CRC_CALCULATION(CALCULATION)        (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \

+                                                    ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))

+

+#define IS_SPI_CRC_INITIALIZATION_PATTERN(PATTERN) (((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN) || \

+                                                    ((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN))

+

+#define IS_SPI_CRC_LENGTH(LENGTH)                  (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) || \

+                                                    ((LENGTH) == SPI_CRC_LENGTH_32BIT)    || \

+                                                    ((LENGTH) == SPI_CRC_LENGTH_31BIT)    || \

+                                                    ((LENGTH) == SPI_CRC_LENGTH_30BIT)    || \

+                                                    ((LENGTH) == SPI_CRC_LENGTH_29BIT)    || \

+                                                    ((LENGTH) == SPI_CRC_LENGTH_28BIT)    || \

+                                                    ((LENGTH) == SPI_CRC_LENGTH_27BIT)    || \

+                                                    ((LENGTH) == SPI_CRC_LENGTH_26BIT)    || \

+                                                    ((LENGTH) == SPI_CRC_LENGTH_25BIT)    || \

+                                                    ((LENGTH) == SPI_CRC_LENGTH_24BIT)    || \

+                                                    ((LENGTH) == SPI_CRC_LENGTH_23BIT)    || \

+                                                    ((LENGTH) == SPI_CRC_LENGTH_22BIT)    || \

+                                                    ((LENGTH) == SPI_CRC_LENGTH_21BIT)    || \

+                                                    ((LENGTH) == SPI_CRC_LENGTH_20BIT)    || \

+                                                    ((LENGTH) == SPI_CRC_LENGTH_19BIT)    || \

+                                                    ((LENGTH) == SPI_CRC_LENGTH_18BIT)    || \

+                                                    ((LENGTH) == SPI_CRC_LENGTH_17BIT)    || \

+                                                    ((LENGTH) == SPI_CRC_LENGTH_16BIT)    || \

+                                                    ((LENGTH) == SPI_CRC_LENGTH_15BIT)    || \

+                                                    ((LENGTH) == SPI_CRC_LENGTH_14BIT)    || \

+                                                    ((LENGTH) == SPI_CRC_LENGTH_13BIT)    || \

+                                                    ((LENGTH) == SPI_CRC_LENGTH_12BIT)    || \

+                                                    ((LENGTH) == SPI_CRC_LENGTH_11BIT)    || \

+                                                    ((LENGTH) == SPI_CRC_LENGTH_10BIT)    || \

+                                                    ((LENGTH) == SPI_CRC_LENGTH_9BIT)     || \

+                                                    ((LENGTH) == SPI_CRC_LENGTH_8BIT)     || \

+                                                    ((LENGTH) == SPI_CRC_LENGTH_7BIT)     || \

+                                                    ((LENGTH) == SPI_CRC_LENGTH_6BIT)     || \

+                                                    ((LENGTH) == SPI_CRC_LENGTH_5BIT)     || \

+                                                    ((LENGTH) == SPI_CRC_LENGTH_4BIT))

+

+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL)           ((POLYNOMIAL) >= 0x1UL)

+

+#define IS_SPI_UNDERRUN_DETECTION(MODE)            (((MODE) == SPI_UNDERRUN_DETECT_BEGIN_DATA_FRAME) || \

+                                                    ((MODE) == SPI_UNDERRUN_DETECT_END_DATA_FRAME)   || \

+                                                    ((MODE) == SPI_UNDERRUN_DETECT_BEGIN_ACTIVE_NSS))

+

+#define IS_SPI_UNDERRUN_BEHAVIOUR(MODE)            (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \

+                                                    ((MODE) == SPI_UNDERRUN_BEHAV_LAST_RECEIVED)    || \

+                                                    ((MODE) == SPI_UNDERRUN_BEHAV_LAST_TRANSMITTED))

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_SPI_H */

+

+/**

+  * @}

+  */

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_spi_ex.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_spi_ex.h
new file mode 100644
index 0000000000..32e743fd56
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_spi_ex.h
@@ -0,0 +1,77 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_spi_ex.h

+  * @author  MCD Application Team

+  * @brief   Header file of SPI HAL Extended module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_SPI_EX_H

+#define STM32H7xx_HAL_SPI_EX_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup SPIEx

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/* Exported constants --------------------------------------------------------*/

+/* Exported macros -----------------------------------------------------------*/

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup SPIEx_Exported_Functions

+  * @{

+  */

+

+/* Initialization and de-initialization functions  ****************************/

+/* IO operation functions *****************************************************/

+/** @addtogroup SPIEx_Exported_Functions_Group1

+  * @{

+  */

+HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi);

+HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi);

+HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, uint32_t UnderrunBehaviour);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_SPI_EX_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_sram.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_sram.h
new file mode 100644
index 0000000000..33aaf83907
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_sram.h
@@ -0,0 +1,222 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_sram.h

+  * @author  MCD Application Team

+  * @brief   Header file of SRAM HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                       opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_SRAM_H

+#define STM32H7xx_HAL_SRAM_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_ll_fmc.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+/** @addtogroup SRAM

+  * @{

+  */

+

+/* Exported typedef ----------------------------------------------------------*/

+

+/** @defgroup SRAM_Exported_Types SRAM Exported Types

+  * @{

+  */

+/**

+  * @brief  HAL SRAM State structures definition

+  */

+typedef enum

+{

+  HAL_SRAM_STATE_RESET     = 0x00U,  /*!< SRAM not yet initialized or disabled           */

+  HAL_SRAM_STATE_READY     = 0x01U,  /*!< SRAM initialized and ready for use             */

+  HAL_SRAM_STATE_BUSY      = 0x02U,  /*!< SRAM internal process is ongoing               */

+  HAL_SRAM_STATE_ERROR     = 0x03U,  /*!< SRAM error state                               */

+  HAL_SRAM_STATE_PROTECTED = 0x04U   /*!< SRAM peripheral NORSRAM device write protected */

+

+} HAL_SRAM_StateTypeDef;

+

+/**

+  * @brief  SRAM handle Structure definition

+  */

+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)

+typedef struct __SRAM_HandleTypeDef

+#else

+typedef struct

+#endif /* USE_HAL_SRAM_REGISTER_CALLBACKS  */	

+{

+  FMC_NORSRAM_TypeDef           *Instance;  /*!< Register base address                        */

+

+  FMC_NORSRAM_EXTENDED_TypeDef  *Extended;  /*!< Extended mode register base address          */

+

+  FMC_NORSRAM_InitTypeDef       Init;       /*!< SRAM device control configuration parameters */

+

+  HAL_LockTypeDef               Lock;       /*!< SRAM locking object                          */

+

+  __IO HAL_SRAM_StateTypeDef    State;      /*!< SRAM device access state                     */

+

+  MDMA_HandleTypeDef             *hmdma;      /*!< Pointer DMA handler                          */

+

+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)

+  void  (* MspInitCallback)        ( struct __SRAM_HandleTypeDef * hsram);    /*!< SRAM Msp Init callback              */

+  void  (* MspDeInitCallback)      ( struct __SRAM_HandleTypeDef * hsram);    /*!< SRAM Msp DeInit callback            */

+  void  (* DmaXferCpltCallback)    ( MDMA_HandleTypeDef * hmdma);               /*!< SRAM DMA Xfer Complete callback     */

+  void  (* DmaXferErrorCallback)   ( MDMA_HandleTypeDef * hmdma);               /*!< SRAM DMA Xfer Error callback        */

+#endif

+} SRAM_HandleTypeDef;

+

+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  HAL SRAM Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_SRAM_MSP_INIT_CB_ID       = 0x00U,  /*!< SRAM MspInit Callback ID           */

+  HAL_SRAM_MSP_DEINIT_CB_ID     = 0x01U,  /*!< SRAM MspDeInit Callback ID         */

+  HAL_SRAM_DMA_XFER_CPLT_CB_ID  = 0x02U,  /*!< SRAM DMA Xfer Complete Callback ID */

+  HAL_SRAM_DMA_XFER_ERR_CB_ID   = 0x03U   /*!< SRAM DMA Xfer Complete Callback ID */

+}HAL_SRAM_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL SRAM Callback pointer definition

+  */

+typedef void (*pSRAM_CallbackTypeDef)(SRAM_HandleTypeDef *hsram);

+typedef void (*pSRAM_DmaCallbackTypeDef)(MDMA_HandleTypeDef *hmdma);

+#endif

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/* Exported macro ------------------------------------------------------------*/

+

+/** @defgroup SRAM_Exported_Macros SRAM Exported Macros

+ * @{

+ */

+

+/** @brief Reset SRAM handle state

+  * @param  __HANDLE__ SRAM handle

+  * @retval None

+  */

+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)

+#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__)         do {                                             \

+                                                               (__HANDLE__)->State = HAL_SRAM_STATE_RESET; \

+                                                               (__HANDLE__)->MspInitCallback = NULL;       \

+                                                               (__HANDLE__)->MspDeInitCallback = NULL;     \

+                                                             } while(0)

+#else

+#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)

+#endif

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup SRAM_Exported_Functions SRAM Exported Functions

+  * @{

+  */

+

+/** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions

+ * @{

+ */

+

+/* Initialization/de-initialization functions  ********************************/

+HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);

+HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);

+void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);

+void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);

+

+/**

+  * @}

+  */

+

+/** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions

+ * @{

+ */

+

+/* I/O operation functions  ***************************************************/

+HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);

+HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);

+HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);

+HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);

+HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);

+HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);

+HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);

+HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);

+

+void HAL_SRAM_DMA_XferCpltCallback(MDMA_HandleTypeDef *hmdma);

+void HAL_SRAM_DMA_XferErrorCallback(MDMA_HandleTypeDef *hmdma);

+

+#if (USE_HAL_SRAM_REGISTER_CALLBACKS == 1)

+/* SRAM callback registering/unregistering */

+HAL_StatusTypeDef HAL_SRAM_RegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_SRAM_UnRegisterCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId);

+HAL_StatusTypeDef HAL_SRAM_RegisterDmaCallback(SRAM_HandleTypeDef *hsram, HAL_SRAM_CallbackIDTypeDef CallbackId, pSRAM_DmaCallbackTypeDef pCallback);

+#endif

+

+/**

+  * @}

+  */

+

+/** @addtogroup SRAM_Exported_Functions_Group3 Control functions

+ * @{

+ */

+

+/* SRAM Control functions  ****************************************************/

+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);

+HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);

+

+/**

+  * @}

+  */

+

+/** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions

+ * @{

+ */

+

+/* SRAM  State functions ******************************************************/

+HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_SRAM_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_swpmi.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_swpmi.h
new file mode 100644
index 0000000000..0c34032988
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_swpmi.h
@@ -0,0 +1,520 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_swpmi.h

+  * @author  MCD Application Team

+  * @brief   Header file of SWPMI HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_SWPMI_H

+#define STM32H7xx_HAL_SWPMI_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+

+/** @addtogroup SWPMI

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup SWPMI_Exported_Types SWPMI Exported Types

+  * @{

+  */

+

+/**

+  * @brief SWPMI Init Structure definition

+  */

+typedef struct

+{

+  uint32_t VoltageClass;             /*!< Specifies the SWP Voltage Class.

+                                          This parameter can be a value of @ref SWPMI_Voltage_Class */

+

+  uint32_t BitRate;                  /*!< Specifies the SWPMI Bitrate.

+                                          This parameter must be a number between 0 and 255U.

+                                          The Bitrate is computed using the following formula:

+                                          SWPMI_freq = SWPMI_clk / (((BitRate) + 1)  * 4)

+                                          */

+

+  uint32_t TxBufferingMode;          /*!< Specifies the transmission buffering mode.

+                                          This parameter can be a value of @ref SWPMI_Tx_Buffering_Mode */

+

+  uint32_t RxBufferingMode;          /*!< Specifies the reception buffering mode.

+                                          This parameter can be a value of @ref SWPMI_Rx_Buffering_Mode */

+

+}SWPMI_InitTypeDef;

+

+

+/**

+  * @brief HAL SWPMI State structures definition

+  */

+typedef enum

+{

+  HAL_SWPMI_STATE_RESET             = 0x00,    /*!< Peripheral Reset state                             */

+  HAL_SWPMI_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use           */

+  HAL_SWPMI_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing                     */

+  HAL_SWPMI_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing               */

+  HAL_SWPMI_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing                  */

+  HAL_SWPMI_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */

+  HAL_SWPMI_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                                      */

+  HAL_SWPMI_STATE_ERROR             = 0x04     /*!< Error                                              */

+}HAL_SWPMI_StateTypeDef;

+

+/**

+  * @brief  SWPMI handle Structure definition

+  */

+#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)

+typedef struct __SWPMI_HandleTypeDef

+#else

+typedef struct

+#endif /* USE_HAL_SWPMI_REGISTER_CALLBACKS */

+{

+  SWPMI_TypeDef                  *Instance;     /*!< SWPMI registers base address         */

+

+  SWPMI_InitTypeDef              Init;          /*!< SWPMI communication parameters       */

+

+  uint32_t                       *pTxBuffPtr;   /*!< Pointer to SWPMI Tx transfer Buffer  */

+

+  uint32_t                       TxXferSize;    /*!< SWPMI Tx Transfer size               */

+

+  uint32_t                       TxXferCount;   /*!< SWPMI Tx Transfer Counter            */

+

+  uint32_t                       *pRxBuffPtr;   /*!< Pointer to SWPMI Rx transfer Buffer  */

+

+  uint32_t                       RxXferSize;    /*!< SWPMI Rx Transfer size               */

+

+  uint32_t                       RxXferCount;   /*!< SWPMI Rx Transfer Counter            */

+

+  DMA_HandleTypeDef              *hdmatx;       /*!< SWPMI Tx DMA Handle parameters       */

+

+  DMA_HandleTypeDef              *hdmarx;       /*!< SWPMI Rx DMA Handle parameters       */

+

+  HAL_LockTypeDef                Lock;          /*!< SWPMI object                         */

+

+  __IO HAL_SWPMI_StateTypeDef    State;         /*!< SWPMI communication state            */

+

+  __IO uint32_t                  ErrorCode;     /*!< SWPMI Error code                     */

+

+#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)

+  void (*RxCpltCallback)     (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI receive complete callback */

+  void (*RxHalfCpltCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI receive half complete callback */

+  void (*TxCpltCallback)     (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI transmit complete callback */

+  void (*TxHalfCpltCallback) (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI transmit half complete callback */

+  void (*ErrorCallback)      (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI error callback */

+  void (*MspInitCallback)    (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP init callback */

+  void (*MspDeInitCallback)  (struct __SWPMI_HandleTypeDef *hswpmi); /*!< SWPMI MSP de-init callback */

+#endif

+

+}SWPMI_HandleTypeDef;

+

+#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  SWPMI callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_SWPMI_RX_COMPLETE_CB_ID     = 0x00U, /*!< SWPMI receive complete callback ID */

+  HAL_SWPMI_RX_HALFCOMPLETE_CB_ID = 0x01U, /*!< SWPMI receive half complete callback ID */

+  HAL_SWPMI_TX_COMPLETE_CB_ID     = 0x02U, /*!< SWPMI transmit complete callback ID */

+  HAL_SWPMI_TX_HALFCOMPLETE_CB_ID = 0x03U, /*!< SWPMI transmit half complete callback ID */

+  HAL_SWPMI_ERROR_CB_ID           = 0x04U, /*!< SWPMI error callback ID */

+  HAL_SWPMI_MSPINIT_CB_ID         = 0x05U, /*!< SWPMI MSP init callback ID */

+  HAL_SWPMI_MSPDEINIT_CB_ID       = 0x06U  /*!< SWPMI MSP de-init callback ID */

+}HAL_SWPMI_CallbackIDTypeDef;

+

+/**

+  * @brief  SWPMI callback pointer definition

+  */

+typedef void (*pSWPMI_CallbackTypeDef)(SWPMI_HandleTypeDef *hswpmi);

+#endif

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup SWPMI_Exported_Constants SWPMI Exported Constants

+  * @{

+  */

+

+/**

+  * @defgroup SWPMI_Error_Code SWPMI Error Code Bitmap

+  * @{

+  */

+#define HAL_SWPMI_ERROR_NONE                  ((uint32_t)0x00000000) /*!< No error              */

+#define HAL_SWPMI_ERROR_CRC                   ((uint32_t)0x00000004) /*!< frame error           */

+#define HAL_SWPMI_ERROR_OVR                   ((uint32_t)0x00000008) /*!< Overrun error         */

+#define HAL_SWPMI_ERROR_UDR                   ((uint32_t)0x0000000C) /*!< Underrun error        */

+#define HAL_SWPMI_ERROR_DMA                   ((uint32_t)0x00000010) /*!< DMA transfer error    */

+#define HAL_SWPMI_ERROR_TIMEOUT               ((uint32_t)0x00000020) /*!< Transfer timeout      */

+#define HAL_SWPMI_ERROR_TXBEF_TIMEOUT         ((uint32_t)0x00000040) /*!< End Tx buffer timeout */

+#define HAL_SWPMI_ERROR_TRANSCEIVER_NOT_READY ((uint32_t)0x00000080) /*!< Transceiver not ready */

+#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)

+#define HAL_SWPMI_ERROR_INVALID_CALLBACK      ((uint32_t)0x00000100) /*!< Invalid callback error */

+#endif

+/**

+  * @}

+  */

+

+/** @defgroup SWPMI_Voltage_Class SWPMI Voltage Class

+  * @{

+  */

+#define SWPMI_VOLTAGE_CLASS_C                ((uint32_t)0x00000000)

+#define SWPMI_VOLTAGE_CLASS_B                SWPMI_OR_CLASS

+/**

+  * @}

+  */

+

+/** @defgroup SWPMI_Tx_Buffering_Mode SWPMI Tx Buffering Mode

+  * @{

+  */

+#define SWPMI_TX_NO_SOFTWAREBUFFER           ((uint32_t)0x00000000)

+#define SWPMI_TX_SINGLE_SOFTWAREBUFFER       ((uint32_t)0x00000000)

+#define SWPMI_TX_MULTI_SOFTWAREBUFFER        SWPMI_CR_TXMODE

+/**

+  * @}

+  */

+

+/** @defgroup SWPMI_Rx_Buffering_Mode SWPMI Rx Buffering Mode

+  * @{

+  */

+#define SWPMI_RX_NO_SOFTWAREBUFFER           ((uint32_t)0x00000000)

+#define SWPMI_RX_SINGLE_SOFTWAREBUFFER       ((uint32_t)0x00000000)

+#define SWPMI_RX_MULTI_SOFTWAREBUFFER        SWPMI_CR_RXMODE

+/**

+  * @}

+  */

+

+/** @defgroup SWPMI_Flags SWPMI Status Flags

+  *        Elements values convention: 0xXXXXXXXX

+  *           - 0xXXXXXXXX  : Flag mask in the ISR register

+  * @{

+  */

+#define SWPMI_FLAG_RXBFF                 SWPMI_ISR_RXBFF

+#define SWPMI_FLAG_TXBEF                 SWPMI_ISR_TXBEF

+#define SWPMI_FLAG_RXBERF                SWPMI_ISR_RXBERF

+#define SWPMI_FLAG_RXOVRF                SWPMI_ISR_RXOVRF

+#define SWPMI_FLAG_TXUNRF                SWPMI_ISR_TXUNRF

+#define SWPMI_FLAG_RXNE                  SWPMI_ISR_RXNE

+#define SWPMI_FLAG_TXE                   SWPMI_ISR_TXE

+#define SWPMI_FLAG_TCF                   SWPMI_ISR_TCF

+#define SWPMI_FLAG_SRF                   SWPMI_ISR_SRF

+#define SWPMI_FLAG_SUSP                  SWPMI_ISR_SUSP

+#define SWPMI_FLAG_DEACTF                SWPMI_ISR_DEACTF

+#define SWPMI_FLAG_RDYF                  SWPMI_ISR_RDYF

+/**

+  * @}

+  */

+

+/** @defgroup SWPMI_Interrupt_definition SWPMI Interrupts Definition

+  *        Elements values convention: 0xXXXX

+  *           - 0xXXXX  : Flag mask in the IER register

+  * @{

+  */

+#define SWPMI_IT_RDYIE                   SWPMI_IER_RDYIE

+#define SWPMI_IT_SRIE                    SWPMI_IER_SRIE

+#define SWPMI_IT_TCIE                    SWPMI_IER_TCIE

+#define SWPMI_IT_TIE                     SWPMI_IER_TIE

+#define SWPMI_IT_RIE                     SWPMI_IER_RIE

+#define SWPMI_IT_TXUNRIE                 SWPMI_IER_TXUNRIE

+#define SWPMI_IT_RXOVRIE                 SWPMI_IER_RXOVRIE

+#define SWPMI_IT_RXBERIE                 SWPMI_IER_RXBERIE

+#define SWPMI_IT_TXBEIE                  SWPMI_IER_TXBEIE

+#define SWPMI_IT_RXBFIE                  SWPMI_IER_RXBFIE

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macros -----------------------------------------------------------*/

+/** @defgroup SWPMI_Exported_Macros SWPMI Exported Macros

+  * @{

+  */

+

+/** @brief Reset SWPMI handle state.

+  * @param  __HANDLE__ specifies the SWPMI Handle.

+  * @retval None

+  */

+#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)

+#define __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) do{                                            \

+                                                     (__HANDLE__)->State = HAL_SWPMI_STATE_RESET; \

+                                                     (__HANDLE__)->MspInitCallback = NULL;        \

+                                                     (__HANDLE__)->MspDeInitCallback = NULL;      \

+                                                   } while(0)

+#else

+#define __HAL_SWPMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SWPMI_STATE_RESET)

+#endif

+

+/**

+  * @brief  Enable the SWPMI peripheral.

+  * @param  __HANDLE__ SWPMI handle

+  * @retval None

+  */

+#define __HAL_SWPMI_ENABLE(__HANDLE__)   SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)

+

+/**

+  * @brief  Disable the SWPMI peripheral.

+  * @param  __HANDLE__ SWPMI handle

+  * @retval None

+  */

+#define __HAL_SWPMI_DISABLE(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPACT)

+

+/**

+  * @brief  Enable the SWPMI transceiver.

+  * @param  __HANDLE__ SWPMI handle

+  * @retval None

+  */

+#define __HAL_SWPMI_TRANSCEIVER_ENABLE(__HANDLE__)   SET_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPEN)

+

+/**

+  * @brief  Disable the SWPMI transceiver.

+  * @param  __HANDLE__ SWPMI handle

+  * @retval None

+  */

+#define __HAL_SWPMI_TRANSCEIVER_DISABLE(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR, SWPMI_CR_SWPEN)

+

+/** @brief  Check whether the specified SWPMI flag is set or not.

+  * @param  __HANDLE__ specifies the SWPMI Handle.

+  * @param  __FLAG__: specifies the flag to check.

+  *        This parameter can be one of the following values:

+  *            @arg SWPMI_FLAG_RXBFF  Receive buffer full flag.

+  *            @arg SWPMI_FLAG_TXBEF  Transmit buffer empty flag.

+  *            @arg SWPMI_FLAG_RXBERF  Receive CRC error flag.

+  *            @arg SWPMI_FLAG_RXOVRF  Receive overrun error flag.

+  *            @arg SWPMI_FLAG_TXUNRF  Transmit underrun error flag.

+  *            @arg SWPMI_FLAG_RXNE  Receive data register not empty.

+  *            @arg SWPMI_FLAG_TXE  Transmit data register empty.

+  *            @arg SWPMI_FLAG_TCF  Transfer complete flag.

+  *            @arg SWPMI_FLAG_SRF  Slave resume flag.

+  *            @arg SWPMI_FLAG_SUSP  SUSPEND flag.

+  *            @arg SWPMI_FLAG_DEACTF  DEACTIVATED flag.

+  *            @arg SWPMI_FLAG_RDYF  Transceiver ready flag.

+  * @retval The new state of __FLAG__ (TRUE or FALSE).

+  */

+#define __HAL_SWPMI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)) == (__FLAG__))

+

+/** @brief  Clear the specified SWPMI ISR flag.

+  * @param  __HANDLE__ specifies the SWPMI Handle.

+  * @param  __FLAG__: specifies the flag to clear.

+  *        This parameter can be one of the following values:

+  *            @arg SWPMI_FLAG_RXBFF  Receive buffer full flag.

+  *            @arg SWPMI_FLAG_TXBEF  Transmit buffer empty flag.

+  *            @arg SWPMI_FLAG_RXBERF  Receive CRC error flag.

+  *            @arg SWPMI_FLAG_RXOVRF  Receive overrun error flag.

+  *            @arg SWPMI_FLAG_TXUNRF  Transmit underrun error flag.

+  *            @arg SWPMI_FLAG_TCF  Transfer complete flag.

+  *            @arg SWPMI_FLAG_SRF  Slave resume flag.

+  *            @arg SWPMI_FLAG_RDYF  Transceiver ready flag.

+  * @retval None

+  */

+#define __HAL_SWPMI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->ICR, (__FLAG__))

+

+/** @brief  Enable the specified SWPMI interrupt.

+  * @param  __HANDLE__ specifies the SWPMI Handle.

+  * @param  __INTERRUPT__ specifies the SWPMI interrupt source to enable.

+  *          This parameter can be one of the following values:

+  *            @arg SWPMI_IT_RDYIE  Transceiver ready interrupt.

+  *            @arg SWPMI_IT_SRIE  Slave resume interrupt.

+  *            @arg SWPMI_IT_TCIE  Transmit complete interrupt.

+  *            @arg SWPMI_IT_TIE   Transmit interrupt.

+  *            @arg SWPMI_IT_RIE   Receive interrupt.

+  *            @arg SWPMI_IT_TXUNRIE  Transmit underrun error interrupt.

+  *            @arg SWPMI_IT_RXOVRIE  Receive overrun error interrupt.

+  *            @arg SWPMI_IT_RXBEIE  Receive CRC error interrupt.

+  *            @arg SWPMI_IT_TXBEIE   Transmit buffer empty interrupt.

+  *            @arg SWPMI_IT_RXBFIE   Receive buffer full interrupt.

+  * @retval None

+  */

+#define __HAL_SWPMI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))

+

+/** @brief  Disable the specified SWPMI interrupt.

+  * @param  __HANDLE__ specifies the SWPMI Handle.

+  * @param  __INTERRUPT__ specifies the SWPMI interrupt source to disable.

+  *          This parameter can be one of the following values:

+  *            @arg SWPMI_IT_RDYIE  Transceiver ready interrupt.

+  *            @arg SWPMI_IT_SRIE  Slave resume interrupt.

+  *            @arg SWPMI_IT_TCIE  Transmit complete interrupt.

+  *            @arg SWPMI_IT_TIE   Transmit interrupt.

+  *            @arg SWPMI_IT_RIE   Receive interrupt.

+  *            @arg SWPMI_IT_TXUNRIE  Transmit underrun error interrupt.

+  *            @arg SWPMI_IT_RXOVRIE  Receive overrun error interrupt.

+  *            @arg SWPMI_IT_RXBEIE  Receive CRC error interrupt.

+  *            @arg SWPMI_IT_TXBEIE   Transmit buffer empty interrupt.

+  *            @arg SWPMI_IT_RXBFIE   Receive buffer full interrupt.

+  * @retval None

+  */

+#define __HAL_SWPMI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__))

+

+/** @brief  Check whether the specified SWPMI interrupt has occurred or not.

+  * @param  __HANDLE__ specifies the SWPMI Handle.

+  * @param  __IT__ specifies the SWPMI interrupt to check.

+  *          This parameter can be one of the following values:

+  *            @arg SWPMI_IT_RDYIE  Transceiver ready interrupt.

+  *            @arg SWPMI_IT_SRIE  Slave resume interrupt.

+  *            @arg SWPMI_IT_TCIE  Transmit complete interrupt.

+  *            @arg SWPMI_IT_TIE   Transmit interrupt.

+  *            @arg SWPMI_IT_RIE   Receive interrupt.

+  *            @arg SWPMI_IT_TXUNRIE  Transmit underrun error interrupt.

+  *            @arg SWPMI_IT_RXOVRIE  Receive overrun error interrupt.

+  *            @arg SWPMI_IT_RXBERIE  Receive CRC error interrupt.

+  *            @arg SWPMI_IT_TXBEIE   Transmit buffer empty interrupt.

+  *            @arg SWPMI_IT_RXBFIE   Receive buffer full interrupt.

+  * @retval The new state of __IT__ (TRUE or FALSE).

+  */

+#define __HAL_SWPMI_GET_IT(__HANDLE__, __IT__)  (READ_BIT((__HANDLE__)->Instance->ISR,(__IT__)) == (__IT__))

+

+/** @brief  Check whether the specified SWPMI interrupt source is enabled or not.

+  * @param  __HANDLE__ specifies the SWPMI Handle.

+  * @param  __IT__ specifies the SWPMI interrupt source to check.

+  *          This parameter can be one of the following values:

+  *            @arg SWPMI_IT_RDYIE  Transceiver ready interrupt.

+  *            @arg SWPMI_IT_SRIE  Slave resume interrupt.

+  *            @arg SWPMI_IT_TCIE  Transmit complete interrupt.

+  *            @arg SWPMI_IT_TIE   Transmit interrupt.

+  *            @arg SWPMI_IT_RIE   Receive interrupt.

+  *            @arg SWPMI_IT_TXUNRIE  Transmit underrun error interrupt.

+  *            @arg SWPMI_IT_RXOVRIE  Receive overrun error interrupt.

+  *            @arg SWPMI_IT_RXBERIE  Receive CRC error interrupt.

+  *            @arg SWPMI_IT_TXBEIE   Transmit buffer empty interrupt.

+  *            @arg SWPMI_IT_RXBFIE   Receive buffer full interrupt.

+  * @retval The new state of __IT__ (TRUE or FALSE).

+  */

+#define __HAL_SWPMI_GET_IT_SOURCE(__HANDLE__, __IT__) ((READ_BIT((__HANDLE__)->Instance->IER, (__IT__)) == (__IT__)) ? SET : RESET)

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup SWPMI_Exported_Functions SWPMI Exported Functions

+  * @{

+  */

+/* Initialization/de-initialization functions  ********************************/

+HAL_StatusTypeDef HAL_SWPMI_Init(SWPMI_HandleTypeDef *hswpmi);

+HAL_StatusTypeDef HAL_SWPMI_DeInit(SWPMI_HandleTypeDef *hswpmi);

+void              HAL_SWPMI_MspInit(SWPMI_HandleTypeDef *hswpmi);

+void              HAL_SWPMI_MspDeInit(SWPMI_HandleTypeDef *hswpmi);

+

+#if (USE_HAL_SWPMI_REGISTER_CALLBACKS == 1)

+/* SWPMI callbacks register/unregister functions ********************************/

+HAL_StatusTypeDef HAL_SWPMI_RegisterCallback(SWPMI_HandleTypeDef        *hswpmi,

+                                             HAL_SWPMI_CallbackIDTypeDef CallbackID,

+                                             pSWPMI_CallbackTypeDef      pCallback);

+HAL_StatusTypeDef HAL_SWPMI_UnRegisterCallback(SWPMI_HandleTypeDef        *hswpmi,

+                                               HAL_SWPMI_CallbackIDTypeDef CallbackID);

+#endif

+

+/* IO operation functions *****************************************************/

+HAL_StatusTypeDef HAL_SWPMI_Transmit(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout);

+HAL_StatusTypeDef HAL_SWPMI_Receive(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size, uint32_t Timeout);

+HAL_StatusTypeDef HAL_SWPMI_Transmit_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_SWPMI_Receive_IT(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_SWPMI_Transmit_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_SWPMI_Receive_DMA(SWPMI_HandleTypeDef *hswpmi, uint32_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_SWPMI_DMAStop(SWPMI_HandleTypeDef *hswpmi);

+HAL_StatusTypeDef HAL_SWPMI_EnableLoopback(SWPMI_HandleTypeDef *hswpmi);

+HAL_StatusTypeDef HAL_SWPMI_DisableLoopback(SWPMI_HandleTypeDef *hswpmi);

+void              HAL_SWPMI_IRQHandler(SWPMI_HandleTypeDef *hswpmi);

+void              HAL_SWPMI_TxCpltCallback(SWPMI_HandleTypeDef *hswpmi);

+void              HAL_SWPMI_TxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi);

+void              HAL_SWPMI_RxCpltCallback(SWPMI_HandleTypeDef *hswpmi);

+void              HAL_SWPMI_RxHalfCpltCallback(SWPMI_HandleTypeDef *hswpmi);

+void              HAL_SWPMI_ErrorCallback(SWPMI_HandleTypeDef *hswpmi);

+

+/* Peripheral Control and State functions  ************************************/

+HAL_SWPMI_StateTypeDef HAL_SWPMI_GetState(SWPMI_HandleTypeDef *hswpmi);

+uint32_t               HAL_SWPMI_GetError(SWPMI_HandleTypeDef *hswpmi);

+

+/**

+  * @}

+  */

+

+/* Private types -------------------------------------------------------------*/

+/** @defgroup SWPMI_Private_Types SWPMI Private Types

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private variables ---------------------------------------------------------*/

+/** @defgroup SWPMI_Private_Variables SWPMI Private Variables

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup SWPMI_Private_Constants SWPMI Private Constants

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup SWPMI_Private_Macros SWPMI Private Macros

+  * @{

+  */

+

+

+#define IS_SWPMI_VOLTAGE_CLASS(__CLASS__)    (((__CLASS__) == SWPMI_VOLTAGE_CLASS_C) || \

+                                              ((__CLASS__) == SWPMI_VOLTAGE_CLASS_B))

+

+#define IS_SWPMI_BITRATE_VALUE(__VALUE__)    (((__VALUE__) <= 255U))

+

+

+#define IS_SWPMI_TX_BUFFERING_MODE(__MODE__) (((__MODE__) == SWPMI_TX_NO_SOFTWAREBUFFER) || \

+                                              ((__MODE__) == SWPMI_TX_MULTI_SOFTWAREBUFFER))

+

+

+#define IS_SWPMI_RX_BUFFERING_MODE(__MODE__) (((__MODE__) == SWPMI_RX_NO_SOFTWAREBUFFER) || \

+                                              ((__MODE__) == SWPMI_RX_MULTI_SOFTWAREBUFFER))

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_SWPMI_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_tim.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_tim.h
new file mode 100644
index 0000000000..37a7ada848
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_tim.h
@@ -0,0 +1,2285 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_tim.h

+  * @author  MCD Application Team

+  * @brief   Header file of TIM HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_TIM_H

+#define STM32H7xx_HAL_TIM_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup TIM

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup TIM_Exported_Types TIM Exported Types

+  * @{

+  */

+

+/**

+  * @brief  TIM Time base Configuration Structure definition

+  */

+typedef struct

+{

+  uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.

+                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */

+

+  uint32_t CounterMode;       /*!< Specifies the counter mode.

+                                   This parameter can be a value of @ref TIM_Counter_Mode */

+

+  uint32_t Period;            /*!< Specifies the period value to be loaded into the active

+                                   Auto-Reload Register at the next update event.

+                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */

+

+  uint32_t ClockDivision;     /*!< Specifies the clock division.

+                                   This parameter can be a value of @ref TIM_ClockDivision */

+

+  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter

+                                    reaches zero, an update event is generated and counting restarts

+                                    from the RCR value (N).

+                                    This means in PWM mode that (N+1) corresponds to:

+                                        - the number of PWM periods in edge-aligned mode

+                                        - the number of half PWM period in center-aligned mode

+                                     GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

+                                     Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */

+

+  uint32_t AutoReloadPreload;  /*!< Specifies the auto-reload preload.

+                                   This parameter can be a value of @ref TIM_AutoReloadPreload */

+} TIM_Base_InitTypeDef;

+

+/**

+  * @brief  TIM Output Compare Configuration Structure definition

+  */

+typedef struct

+{

+  uint32_t OCMode;        /*!< Specifies the TIM mode.

+                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */

+

+  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.

+                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */

+

+  uint32_t OCPolarity;    /*!< Specifies the output polarity.

+                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */

+

+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.

+                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity

+                               @note This parameter is valid only for timer instances supporting break feature. */

+

+  uint32_t OCFastMode;    /*!< Specifies the Fast mode state.

+                               This parameter can be a value of @ref TIM_Output_Fast_State

+                               @note This parameter is valid only in PWM1 and PWM2 mode. */

+

+

+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.

+                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State

+                               @note This parameter is valid only for timer instances supporting break feature. */

+

+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.

+                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State

+                               @note This parameter is valid only for timer instances supporting break feature. */

+} TIM_OC_InitTypeDef;

+

+/**

+  * @brief  TIM One Pulse Mode Configuration Structure definition

+  */

+typedef struct

+{

+  uint32_t OCMode;        /*!< Specifies the TIM mode.

+                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */

+

+  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.

+                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */

+

+  uint32_t OCPolarity;    /*!< Specifies the output polarity.

+                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */

+

+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.

+                               This parameter can be a value of @ref TIM_Output_Compare_N_Polarity

+                               @note This parameter is valid only for timer instances supporting break feature. */

+

+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.

+                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State

+                               @note This parameter is valid only for timer instances supporting break feature. */

+

+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.

+                               This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State

+                               @note This parameter is valid only for timer instances supporting break feature. */

+

+  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.

+                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */

+

+  uint32_t ICSelection;   /*!< Specifies the input.

+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */

+

+  uint32_t ICFilter;      /*!< Specifies the input capture filter.

+                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */

+} TIM_OnePulse_InitTypeDef;

+

+/**

+  * @brief  TIM Input Capture Configuration Structure definition

+  */

+typedef struct

+{

+  uint32_t  ICPolarity;  /*!< Specifies the active edge of the input signal.

+                              This parameter can be a value of @ref TIM_Input_Capture_Polarity */

+

+  uint32_t ICSelection;  /*!< Specifies the input.

+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */

+

+  uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.

+                              This parameter can be a value of @ref TIM_Input_Capture_Prescaler */

+

+  uint32_t ICFilter;     /*!< Specifies the input capture filter.

+                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */

+} TIM_IC_InitTypeDef;

+

+/**

+  * @brief  TIM Encoder Configuration Structure definition

+  */

+typedef struct

+{

+  uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.

+                               This parameter can be a value of @ref TIM_Encoder_Mode */

+

+  uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.

+                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */

+

+  uint32_t IC1Selection;  /*!< Specifies the input.

+                               This parameter can be a value of @ref TIM_Input_Capture_Selection */

+

+  uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.

+                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */

+

+  uint32_t IC1Filter;     /*!< Specifies the input capture filter.

+                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */

+

+  uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.

+                               This parameter can be a value of @ref TIM_Encoder_Input_Polarity */

+

+  uint32_t IC2Selection;  /*!< Specifies the input.

+                              This parameter can be a value of @ref TIM_Input_Capture_Selection */

+

+  uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.

+                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */

+

+  uint32_t IC2Filter;     /*!< Specifies the input capture filter.

+                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */

+} TIM_Encoder_InitTypeDef;

+

+/**

+  * @brief  Clock Configuration Handle Structure definition

+  */

+typedef struct

+{

+  uint32_t ClockSource;     /*!< TIM clock sources

+                                 This parameter can be a value of @ref TIM_Clock_Source */

+  uint32_t ClockPolarity;   /*!< TIM clock polarity

+                                 This parameter can be a value of @ref TIM_Clock_Polarity */

+  uint32_t ClockPrescaler;  /*!< TIM clock prescaler

+                                 This parameter can be a value of @ref TIM_Clock_Prescaler */

+  uint32_t ClockFilter;     /*!< TIM clock filter

+                                 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */

+} TIM_ClockConfigTypeDef;

+

+/**

+  * @brief  TIM Clear Input Configuration Handle Structure definition

+  */

+typedef struct

+{

+  uint32_t ClearInputState;      /*!< TIM clear Input state

+                                      This parameter can be ENABLE or DISABLE */

+  uint32_t ClearInputSource;     /*!< TIM clear Input sources

+                                      This parameter can be a value of @ref TIM_ClearInput_Source */

+  uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity

+                                      This parameter can be a value of @ref TIM_ClearInput_Polarity */

+  uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler

+                                      This parameter must be 0: When OCRef clear feature is used with ETR source, ETR prescaler must be off */

+  uint32_t ClearInputFilter;     /*!< TIM Clear Input filter

+                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */

+} TIM_ClearInputConfigTypeDef;

+

+/**

+  * @brief  TIM Master configuration Structure definition

+  * @note   Advanced timers provide TRGO2 internal line which is redirected

+  *         to the ADC

+  */

+typedef struct

+{

+  uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection

+                                        This parameter can be a value of @ref TIM_Master_Mode_Selection */

+  uint32_t  MasterOutputTrigger2;  /*!< Trigger output2 (TRGO2) selection

+                                        This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */

+  uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection

+                                        This parameter can be a value of @ref TIM_Master_Slave_Mode

+                                        @note When the Master/slave mode is enabled, the effect of

+                                        an event on the trigger input (TRGI) is delayed to allow a

+                                        perfect synchronization between the current timer and its

+                                        slaves (through TRGO). It is not mandatory in case of timer

+                                        synchronization mode. */

+} TIM_MasterConfigTypeDef;

+

+/**

+  * @brief  TIM Slave configuration Structure definition

+  */

+typedef struct

+{

+  uint32_t  SlaveMode;         /*!< Slave mode selection

+                                    This parameter can be a value of @ref TIM_Slave_Mode */

+  uint32_t  InputTrigger;      /*!< Input Trigger source

+                                    This parameter can be a value of @ref TIM_Trigger_Selection */

+  uint32_t  TriggerPolarity;   /*!< Input Trigger polarity

+                                    This parameter can be a value of @ref TIM_Trigger_Polarity */

+  uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler

+                                    This parameter can be a value of @ref TIM_Trigger_Prescaler */

+  uint32_t  TriggerFilter;     /*!< Input trigger filter

+                                    This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF  */

+

+} TIM_SlaveConfigTypeDef;

+

+/**

+  * @brief  TIM Break input(s) and Dead time configuration Structure definition

+  * @note   2 break inputs can be configured (BKIN and BKIN2) with configurable

+  *        filter and polarity.

+  */

+typedef struct

+{

+  uint32_t OffStateRunMode;      /*!< TIM off state in run mode

+                                      This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */

+  uint32_t OffStateIDLEMode;     /*!< TIM off state in IDLE mode

+                                      This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */

+  uint32_t LockLevel;            /*!< TIM Lock level

+                                      This parameter can be a value of @ref TIM_Lock_level */

+  uint32_t DeadTime;             /*!< TIM dead Time

+                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */

+  uint32_t BreakState;           /*!< TIM Break State

+                                      This parameter can be a value of @ref TIM_Break_Input_enable_disable */

+  uint32_t BreakPolarity;        /*!< TIM Break input polarity

+                                      This parameter can be a value of @ref TIM_Break_Polarity */

+  uint32_t BreakFilter;          /*!< Specifies the break input filter.

+                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */

+  uint32_t Break2State;          /*!< TIM Break2 State

+                                      This parameter can be a value of @ref TIM_Break2_Input_enable_disable */

+  uint32_t Break2Polarity;       /*!< TIM Break2 input polarity

+                                      This parameter can be a value of @ref TIM_Break2_Polarity */

+  uint32_t Break2Filter;         /*!< TIM break2 input filter.

+                                      This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */

+  uint32_t AutomaticOutput;      /*!< TIM Automatic Output Enable state

+                                      This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */

+} TIM_BreakDeadTimeConfigTypeDef;

+

+/**

+  * @brief  HAL State structures definition

+  */

+typedef enum

+{

+  HAL_TIM_STATE_RESET             = 0x00U,    /*!< Peripheral not yet initialized or disabled  */

+  HAL_TIM_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */

+  HAL_TIM_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */

+  HAL_TIM_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */

+  HAL_TIM_STATE_ERROR             = 0x04U     /*!< Reception process is ongoing                */

+} HAL_TIM_StateTypeDef;

+

+/**

+  * @brief  HAL Active channel structures definition

+  */

+typedef enum

+{

+  HAL_TIM_ACTIVE_CHANNEL_1        = 0x01U,    /*!< The active channel is 1     */

+  HAL_TIM_ACTIVE_CHANNEL_2        = 0x02U,    /*!< The active channel is 2     */

+  HAL_TIM_ACTIVE_CHANNEL_3        = 0x04U,    /*!< The active channel is 3     */

+  HAL_TIM_ACTIVE_CHANNEL_4        = 0x08U,    /*!< The active channel is 4     */

+  HAL_TIM_ACTIVE_CHANNEL_5        = 0x10U,    /*!< The active channel is 5     */

+  HAL_TIM_ACTIVE_CHANNEL_6        = 0x20U,    /*!< The active channel is 6     */

+  HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00U     /*!< All active channels cleared */

+} HAL_TIM_ActiveChannel;

+

+/**

+  * @brief  TIM Time Base Handle Structure definition

+  */

+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)

+typedef struct __TIM_HandleTypeDef

+#else

+typedef struct

+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

+{

+  TIM_TypeDef                 *Instance;     /*!< Register base address             */

+  TIM_Base_InitTypeDef        Init;          /*!< TIM Time Base required parameters */

+  HAL_TIM_ActiveChannel       Channel;       /*!< Active channel                    */

+  DMA_HandleTypeDef           *hdma[7];      /*!< DMA Handlers array

+                                                  This array is accessed by a @ref DMA_Handle_index */

+  HAL_LockTypeDef             Lock;          /*!< Locking object                    */

+  __IO HAL_TIM_StateTypeDef   State;         /*!< TIM operation state               */

+

+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)

+  void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM Base Msp Init Callback                              */

+  void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);            /*!< TIM Base Msp DeInit Callback                            */

+  void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM IC Msp Init Callback                                */

+  void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM IC Msp DeInit Callback                              */

+  void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM OC Msp Init Callback                                */

+  void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);              /*!< TIM OC Msp DeInit Callback                              */

+  void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM PWM Msp Init Callback                               */

+  void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM PWM Msp DeInit Callback                             */

+  void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim);          /*!< TIM One Pulse Msp Init Callback                         */

+  void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM One Pulse Msp DeInit Callback                       */

+  void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Encoder Msp Init Callback                           */

+  void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM Encoder Msp DeInit Callback                         */

+  void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Hall Sensor Msp Init Callback                       */

+  void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim);      /*!< TIM Hall Sensor Msp DeInit Callback                     */

+  void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim);             /*!< TIM Period Elapsed Callback                             */

+  void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);     /*!< TIM Period Elapsed half complete Callback               */

+  void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim);                   /*!< TIM Trigger Callback                                    */

+  void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Trigger half complete Callback                      */

+  void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim);                /*!< TIM Input Capture Callback                              */

+  void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);        /*!< TIM Input Capture half complete Callback                */

+  void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim);           /*!< TIM Output Compare Delay Elapsed Callback               */

+  void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim);         /*!< TIM PWM Pulse Finished Callback                         */

+  void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback           */

+  void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Error Callback                                      */

+  void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim);               /*!< TIM Commutation Callback                                */

+  void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim);       /*!< TIM Commutation half complete Callback                  */

+  void (* BreakCallback)(struct __TIM_HandleTypeDef *htim);                     /*!< TIM Break Callback                                      */

+  void (* Break2Callback)(struct __TIM_HandleTypeDef *htim);                    /*!< TIM Break2 Callback                                     */

+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

+} TIM_HandleTypeDef;

+

+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  HAL TIM Callback ID enumeration definition

+  */

+typedef enum

+{

+   HAL_TIM_BASE_MSPINIT_CB_ID            = 0x00U    /*!< TIM Base MspInit Callback ID                              */

+  ,HAL_TIM_BASE_MSPDEINIT_CB_ID          = 0x01U    /*!< TIM Base MspDeInit Callback ID                            */

+  ,HAL_TIM_IC_MSPINIT_CB_ID              = 0x02U    /*!< TIM IC MspInit Callback ID                                */

+  ,HAL_TIM_IC_MSPDEINIT_CB_ID            = 0x03U    /*!< TIM IC MspDeInit Callback ID                              */

+  ,HAL_TIM_OC_MSPINIT_CB_ID              = 0x04U    /*!< TIM OC MspInit Callback ID                                */

+  ,HAL_TIM_OC_MSPDEINIT_CB_ID            = 0x05U    /*!< TIM OC MspDeInit Callback ID                              */

+  ,HAL_TIM_PWM_MSPINIT_CB_ID             = 0x06U    /*!< TIM PWM MspInit Callback ID                               */

+  ,HAL_TIM_PWM_MSPDEINIT_CB_ID           = 0x07U    /*!< TIM PWM MspDeInit Callback ID                             */

+  ,HAL_TIM_ONE_PULSE_MSPINIT_CB_ID       = 0x08U    /*!< TIM One Pulse MspInit Callback ID                         */

+  ,HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID     = 0x09U    /*!< TIM One Pulse MspDeInit Callback ID                       */

+  ,HAL_TIM_ENCODER_MSPINIT_CB_ID         = 0x0AU    /*!< TIM Encoder MspInit Callback ID                           */

+  ,HAL_TIM_ENCODER_MSPDEINIT_CB_ID       = 0x0BU    /*!< TIM Encoder MspDeInit Callback ID                         */

+  ,HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID     = 0x0CU    /*!< TIM Hall Sensor MspDeInit Callback ID                     */

+  ,HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID   = 0x0DU    /*!< TIM Hall Sensor MspDeInit Callback ID                     */

+  ,HAL_TIM_PERIOD_ELAPSED_CB_ID          = 0x0EU    /*!< TIM Period Elapsed Callback ID                             */

+  ,HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID     = 0x0FU    /*!< TIM Period Elapsed half complete Callback ID               */

+  ,HAL_TIM_TRIGGER_CB_ID                 = 0x10U    /*!< TIM Trigger Callback ID                                    */

+  ,HAL_TIM_TRIGGER_HALF_CB_ID            = 0x11U    /*!< TIM Trigger half complete Callback ID                      */

+

+  ,HAL_TIM_IC_CAPTURE_CB_ID              = 0x12U    /*!< TIM Input Capture Callback ID                              */

+  ,HAL_TIM_IC_CAPTURE_HALF_CB_ID         = 0x13U    /*!< TIM Input Capture half complete Callback ID                */

+  ,HAL_TIM_OC_DELAY_ELAPSED_CB_ID        = 0x14U    /*!< TIM Output Compare Delay Elapsed Callback ID               */

+  ,HAL_TIM_PWM_PULSE_FINISHED_CB_ID      = 0x15U    /*!< TIM PWM Pulse Finished Callback ID           */

+  ,HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U    /*!< TIM PWM Pulse Finished half complete Callback ID           */

+  ,HAL_TIM_ERROR_CB_ID                   = 0x17U    /*!< TIM Error Callback ID                                      */

+  ,HAL_TIM_COMMUTATION_CB_ID             = 0x18U    /*!< TIM Commutation Callback ID                                */

+  ,HAL_TIM_COMMUTATION_HALF_CB_ID        = 0x19U    /*!< TIM Commutation half complete Callback ID                  */

+  ,HAL_TIM_BREAK_CB_ID                   = 0x1AU    /*!< TIM Break Callback ID                                      */

+  ,HAL_TIM_BREAK2_CB_ID                  = 0x1BU    /*!< TIM Break2 Callback ID                                     */

+} HAL_TIM_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL TIM Callback pointer definition

+  */

+typedef  void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim);  /*!< pointer to the TIM callback function */

+

+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+/* End of exported types -----------------------------------------------------*/

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup TIM_Exported_Constants TIM Exported Constants

+  * @{

+  */

+

+/** @defgroup TIM_ClearInput_Source TIM Clear Input Source

+  * @{

+  */

+#define TIM_CLEARINPUTSOURCE_NONE           0x00000000U   /*!< OCREF_CLR is disabled */

+#define TIM_CLEARINPUTSOURCE_ETR            0x00000001U   /*!< OCREF_CLR is connected to ETRF input */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_DMA_Base_address TIM DMA Base Address

+  * @{

+  */

+#define TIM_DMABASE_CR1                    0x00000000U

+#define TIM_DMABASE_CR2                    0x00000001U

+#define TIM_DMABASE_SMCR                   0x00000002U

+#define TIM_DMABASE_DIER                   0x00000003U

+#define TIM_DMABASE_SR                     0x00000004U

+#define TIM_DMABASE_EGR                    0x00000005U

+#define TIM_DMABASE_CCMR1                  0x00000006U

+#define TIM_DMABASE_CCMR2                  0x00000007U

+#define TIM_DMABASE_CCER                   0x00000008U

+#define TIM_DMABASE_CNT                    0x00000009U

+#define TIM_DMABASE_PSC                    0x0000000AU

+#define TIM_DMABASE_ARR                    0x0000000BU

+#define TIM_DMABASE_RCR                    0x0000000CU

+#define TIM_DMABASE_CCR1                   0x0000000DU

+#define TIM_DMABASE_CCR2                   0x0000000EU

+#define TIM_DMABASE_CCR3                   0x0000000FU

+#define TIM_DMABASE_CCR4                   0x00000010U

+#define TIM_DMABASE_BDTR                   0x00000011U

+#define TIM_DMABASE_DCR                    0x00000012U

+#define TIM_DMABASE_DMAR                   0x00000013U

+#define TIM_DMABASE_CCMR3                  0x00000015U

+#define TIM_DMABASE_CCR5                   0x00000016U

+#define TIM_DMABASE_CCR6                   0x00000017U

+#if   defined(TIM_BREAK_INPUT_SUPPORT)

+#define TIM_DMABASE_AF1                    0x00000018U

+#define TIM_DMABASE_AF2                    0x00000019U

+#endif /* TIM_BREAK_INPUT_SUPPORT */

+#define TIM_DMABASE_TISEL                  0x0000001AU

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Event_Source TIM Event Source

+  * @{

+  */

+#define TIM_EVENTSOURCE_UPDATE              TIM_EGR_UG     /*!< Reinitialize the counter and generates an update of the registers */

+#define TIM_EVENTSOURCE_CC1                 TIM_EGR_CC1G   /*!< A capture/compare event is generated on channel 1 */

+#define TIM_EVENTSOURCE_CC2                 TIM_EGR_CC2G   /*!< A capture/compare event is generated on channel 2 */

+#define TIM_EVENTSOURCE_CC3                 TIM_EGR_CC3G   /*!< A capture/compare event is generated on channel 3 */

+#define TIM_EVENTSOURCE_CC4                 TIM_EGR_CC4G   /*!< A capture/compare event is generated on channel 4 */

+#define TIM_EVENTSOURCE_COM                 TIM_EGR_COMG   /*!< A commutation event is generated */

+#define TIM_EVENTSOURCE_TRIGGER             TIM_EGR_TG     /*!< A trigger event is generated */

+#define TIM_EVENTSOURCE_BREAK               TIM_EGR_BG     /*!< A break event is generated */

+#define TIM_EVENTSOURCE_BREAK2              TIM_EGR_B2G    /*!< A break 2 event is generated */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity

+  * @{

+  */

+#define  TIM_INPUTCHANNELPOLARITY_RISING      0x00000000U                       /*!< Polarity for TIx source */

+#define  TIM_INPUTCHANNELPOLARITY_FALLING     TIM_CCER_CC1P                     /*!< Polarity for TIx source */

+#define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_ETR_Polarity TIM ETR Polarity

+  * @{

+  */

+#define TIM_ETRPOLARITY_INVERTED              TIM_SMCR_ETP                      /*!< Polarity for ETR source */

+#define TIM_ETRPOLARITY_NONINVERTED           0x00000000U                       /*!< Polarity for ETR source */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler

+  * @{

+  */

+#define TIM_ETRPRESCALER_DIV1                 0x00000000U                       /*!< No prescaler is used */

+#define TIM_ETRPRESCALER_DIV2                 TIM_SMCR_ETPS_0                   /*!< ETR input source is divided by 2 */

+#define TIM_ETRPRESCALER_DIV4                 TIM_SMCR_ETPS_1                   /*!< ETR input source is divided by 4 */

+#define TIM_ETRPRESCALER_DIV8                 TIM_SMCR_ETPS                     /*!< ETR input source is divided by 8 */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Counter_Mode TIM Counter Mode

+  * @{

+  */

+#define TIM_COUNTERMODE_UP                 0x00000000U                          /*!< Counter used as up-counter   */

+#define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR                          /*!< Counter used as down-counter */

+#define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0                        /*!< Center-aligned mode 1        */

+#define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1                        /*!< Center-aligned mode 2        */

+#define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS                          /*!< Center-aligned mode 3        */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap

+  * @{

+  */

+#define TIM_UIFREMAP_DISABLE               0x00000000U                          /*!< Update interrupt flag remap disabled */

+#define TIM_UIFREMAP_ENABLE                TIM_CR1_UIFREMAP                     /*!< Update interrupt flag remap enabled */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_ClockDivision TIM Clock Division

+  * @{

+  */

+#define TIM_CLOCKDIVISION_DIV1             0x00000000U                          /*!< Clock division: tDTS=tCK_INT   */

+#define TIM_CLOCKDIVISION_DIV2             TIM_CR1_CKD_0                        /*!< Clock division: tDTS=2*tCK_INT */

+#define TIM_CLOCKDIVISION_DIV4             TIM_CR1_CKD_1                        /*!< Clock division: tDTS=4*tCK_INT */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Output_Compare_State TIM Output Compare State

+  * @{

+  */

+#define TIM_OUTPUTSTATE_DISABLE            0x00000000U                          /*!< Capture/Compare 1 output disabled */

+#define TIM_OUTPUTSTATE_ENABLE             TIM_CCER_CC1E                        /*!< Capture/Compare 1 output enabled */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload

+  * @{

+  */

+#define TIM_AUTORELOAD_PRELOAD_DISABLE                0x00000000U               /*!< TIMx_ARR register is not buffered */

+#define TIM_AUTORELOAD_PRELOAD_ENABLE                 TIM_CR1_ARPE              /*!< TIMx_ARR register is buffered */

+

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Output_Fast_State TIM Output Fast State

+  * @{

+  */

+#define TIM_OCFAST_DISABLE                 0x00000000U                          /*!< Output Compare fast disable */

+#define TIM_OCFAST_ENABLE                  TIM_CCMR1_OC1FE                      /*!< Output Compare fast enable  */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State

+  * @{

+  */

+#define TIM_OUTPUTNSTATE_DISABLE           0x00000000U                          /*!< OCxN is disabled  */

+#define TIM_OUTPUTNSTATE_ENABLE            TIM_CCER_CC1NE                       /*!< OCxN is enabled   */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity

+  * @{

+  */

+#define TIM_OCPOLARITY_HIGH                0x00000000U                          /*!< Capture/Compare output polarity  */

+#define TIM_OCPOLARITY_LOW                 TIM_CCER_CC1P                        /*!< Capture/Compare output polarity  */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity

+  * @{

+  */

+#define TIM_OCNPOLARITY_HIGH               0x00000000U                          /*!< Capture/Compare complementary output polarity */

+#define TIM_OCNPOLARITY_LOW                TIM_CCER_CC1NP                       /*!< Capture/Compare complementary output polarity */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State

+  * @{

+  */

+#define TIM_OCIDLESTATE_SET                TIM_CR2_OIS1                         /*!< Output Idle state: OCx=1 when MOE=0 */

+#define TIM_OCIDLESTATE_RESET              0x00000000U                          /*!< Output Idle state: OCx=0 when MOE=0 */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State

+  * @{

+  */

+#define TIM_OCNIDLESTATE_SET               TIM_CR2_OIS1N                        /*!< Complementary output Idle state: OCxN=1 when MOE=0 */

+#define TIM_OCNIDLESTATE_RESET             0x00000000U                          /*!< Complementary output Idle state: OCxN=0 when MOE=0 */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity

+  * @{

+  */

+#define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING      /*!< Capture triggered by rising edge on timer input                  */

+#define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Capture triggered by falling edge on timer input                 */

+#define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE    /*!< Capture triggered by both rising and falling edges on timer input*/

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity

+  * @{

+  */

+#define  TIM_ENCODERINPUTPOLARITY_RISING   TIM_INPUTCHANNELPOLARITY_RISING      /*!< Encoder input with rising edge polarity  */

+#define  TIM_ENCODERINPUTPOLARITY_FALLING  TIM_INPUTCHANNELPOLARITY_FALLING     /*!< Encoder input with falling edge polarity */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection

+  * @{

+  */

+#define TIM_ICSELECTION_DIRECTTI           TIM_CCMR1_CC1S_0                     /*!< TIM Input 1, 2, 3 or 4 is selected to be

+                                                                                     connected to IC1, IC2, IC3 or IC4, respectively */

+#define TIM_ICSELECTION_INDIRECTTI         TIM_CCMR1_CC1S_1                     /*!< TIM Input 1, 2, 3 or 4 is selected to be

+                                                                                     connected to IC2, IC1, IC4 or IC3, respectively */

+#define TIM_ICSELECTION_TRC                TIM_CCMR1_CC1S                       /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler

+  * @{

+  */

+#define TIM_ICPSC_DIV1                     0x00000000U                          /*!< Capture performed each time an edge is detected on the capture input */

+#define TIM_ICPSC_DIV2                     TIM_CCMR1_IC1PSC_0                   /*!< Capture performed once every 2 events                                */

+#define TIM_ICPSC_DIV4                     TIM_CCMR1_IC1PSC_1                   /*!< Capture performed once every 4 events                                */

+#define TIM_ICPSC_DIV8                     TIM_CCMR1_IC1PSC                     /*!< Capture performed once every 8 events                                */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode

+  * @{

+  */

+#define TIM_OPMODE_SINGLE                  TIM_CR1_OPM                          /*!< Counter stops counting at the next update event */

+#define TIM_OPMODE_REPETITIVE              0x00000000U                          /*!< Counter is not stopped at update event          */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Encoder_Mode TIM Encoder Mode

+  * @{

+  */

+#define TIM_ENCODERMODE_TI1                      TIM_SMCR_SMS_0                                                      /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level  */

+#define TIM_ENCODERMODE_TI2                      TIM_SMCR_SMS_1                                                      /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */

+#define TIM_ENCODERMODE_TI12                     (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Interrupt_definition TIM interrupt Definition

+  * @{

+  */

+#define TIM_IT_UPDATE                      TIM_DIER_UIE                         /*!< Update interrupt            */

+#define TIM_IT_CC1                         TIM_DIER_CC1IE                       /*!< Capture/Compare 1 interrupt */

+#define TIM_IT_CC2                         TIM_DIER_CC2IE                       /*!< Capture/Compare 2 interrupt */

+#define TIM_IT_CC3                         TIM_DIER_CC3IE                       /*!< Capture/Compare 3 interrupt */

+#define TIM_IT_CC4                         TIM_DIER_CC4IE                       /*!< Capture/Compare 4 interrupt */

+#define TIM_IT_COM                         TIM_DIER_COMIE                       /*!< Commutation interrupt       */

+#define TIM_IT_TRIGGER                     TIM_DIER_TIE                         /*!< Trigger interrupt           */

+#define TIM_IT_BREAK                       TIM_DIER_BIE                         /*!< Break interrupt             */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Commutation_Source  TIM Commutation Source

+  * @{

+  */

+#define TIM_COMMUTATION_TRGI              TIM_CR2_CCUS                          /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */

+#define TIM_COMMUTATION_SOFTWARE          0x00000000U                           /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_DMA_sources TIM DMA Sources

+  * @{

+  */

+#define TIM_DMA_UPDATE                     TIM_DIER_UDE                         /*!< DMA request is triggered by the update event */

+#define TIM_DMA_CC1                        TIM_DIER_CC1DE                       /*!< DMA request is triggered by the capture/compare macth 1 event */

+#define TIM_DMA_CC2                        TIM_DIER_CC2DE                       /*!< DMA request is triggered by the capture/compare macth 2 event event */

+#define TIM_DMA_CC3                        TIM_DIER_CC3DE                       /*!< DMA request is triggered by the capture/compare macth 3 event event */

+#define TIM_DMA_CC4                        TIM_DIER_CC4DE                       /*!< DMA request is triggered by the capture/compare macth 4 event event */

+#define TIM_DMA_COM                        TIM_DIER_COMDE                       /*!< DMA request is triggered by the commutation event */

+#define TIM_DMA_TRIGGER                    TIM_DIER_TDE                         /*!< DMA request is triggered by the trigger event */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Flag_definition TIM Flag Definition

+  * @{

+  */

+#define TIM_FLAG_UPDATE                    TIM_SR_UIF                           /*!< Update interrupt flag         */

+#define TIM_FLAG_CC1                       TIM_SR_CC1IF                         /*!< Capture/Compare 1 interrupt flag */

+#define TIM_FLAG_CC2                       TIM_SR_CC2IF                         /*!< Capture/Compare 2 interrupt flag */

+#define TIM_FLAG_CC3                       TIM_SR_CC3IF                         /*!< Capture/Compare 3 interrupt flag */

+#define TIM_FLAG_CC4                       TIM_SR_CC4IF                         /*!< Capture/Compare 4 interrupt flag */

+#define TIM_FLAG_CC5                       TIM_SR_CC5IF                         /*!< Capture/Compare 5 interrupt flag */

+#define TIM_FLAG_CC6                       TIM_SR_CC6IF                         /*!< Capture/Compare 6 interrupt flag */

+#define TIM_FLAG_COM                       TIM_SR_COMIF                         /*!< Commutation interrupt flag    */

+#define TIM_FLAG_TRIGGER                   TIM_SR_TIF                           /*!< Trigger interrupt flag        */

+#define TIM_FLAG_BREAK                     TIM_SR_BIF                           /*!< Break interrupt flag          */

+#define TIM_FLAG_BREAK2                    TIM_SR_B2IF                          /*!< Break 2 interrupt flag        */

+#define TIM_FLAG_SYSTEM_BREAK              TIM_SR_SBIF                          /*!< System Break interrupt flag   */

+#define TIM_FLAG_CC1OF                     TIM_SR_CC1OF                         /*!< Capture 1 overcapture flag    */

+#define TIM_FLAG_CC2OF                     TIM_SR_CC2OF                         /*!< Capture 2 overcapture flag    */

+#define TIM_FLAG_CC3OF                     TIM_SR_CC3OF                         /*!< Capture 3 overcapture flag    */

+#define TIM_FLAG_CC4OF                     TIM_SR_CC4OF                         /*!< Capture 4 overcapture flag    */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Channel TIM Channel

+  * @{

+  */

+#define TIM_CHANNEL_1                      0x00000000U                          /*!< Capture/compare channel 1 identifier      */

+#define TIM_CHANNEL_2                      0x00000004U                          /*!< Capture/compare channel 2 identifier      */

+#define TIM_CHANNEL_3                      0x00000008U                          /*!< Capture/compare channel 3 identifier      */

+#define TIM_CHANNEL_4                      0x0000000CU                          /*!< Capture/compare channel 4 identifier      */

+#define TIM_CHANNEL_5                      0x00000010U                          /*!< Compare channel 5 identifier              */

+#define TIM_CHANNEL_6                      0x00000014U                          /*!< Compare channel 6 identifier              */

+#define TIM_CHANNEL_ALL                    0x0000003CU                          /*!< Global Capture/compare channel identifier  */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Clock_Source TIM Clock Source

+  * @{

+  */

+#define TIM_CLOCKSOURCE_ETRMODE2    TIM_SMCR_ETPS_1      /*!< External clock source mode 2                          */

+#define TIM_CLOCKSOURCE_INTERNAL    TIM_SMCR_ETPS_0      /*!< Internal clock source                                 */

+#define TIM_CLOCKSOURCE_ITR0        TIM_TS_ITR0          /*!< External clock source mode 1 (ITR0)                   */

+#define TIM_CLOCKSOURCE_ITR1        TIM_TS_ITR1          /*!< External clock source mode 1 (ITR1)                   */

+#define TIM_CLOCKSOURCE_ITR2        TIM_TS_ITR2          /*!< External clock source mode 1 (ITR2)                   */

+#define TIM_CLOCKSOURCE_ITR3        TIM_TS_ITR3          /*!< External clock source mode 1 (ITR3)                   */

+#define TIM_CLOCKSOURCE_TI1ED       TIM_TS_TI1F_ED       /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */

+#define TIM_CLOCKSOURCE_TI1         TIM_TS_TI1FP1        /*!< External clock source mode 1 (TTI1FP1)                */

+#define TIM_CLOCKSOURCE_TI2         TIM_TS_TI2FP2        /*!< External clock source mode 1 (TTI2FP2)                */

+#define TIM_CLOCKSOURCE_ETRMODE1    TIM_TS_ETRF          /*!< External clock source mode 1 (ETRF)                   */

+#define TIM_CLOCKSOURCE_ITR4        TIM_TS_ITR4          /*!< External clock source mode 1 (ITR4)                   */

+#define TIM_CLOCKSOURCE_ITR5        TIM_TS_ITR5          /*!< External clock source mode 1 (ITR5)                   */

+#define TIM_CLOCKSOURCE_ITR6        TIM_TS_ITR6          /*!< External clock source mode 1 (ITR6)                   */

+#define TIM_CLOCKSOURCE_ITR7        TIM_TS_ITR7          /*!< External clock source mode 1 (ITR7)                   */

+#define TIM_CLOCKSOURCE_ITR8        TIM_TS_ITR8          /*!< External clock source mode 1 (ITR8)                   */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Clock_Polarity TIM Clock Polarity

+  * @{

+  */

+#define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED           /*!< Polarity for ETRx clock sources */

+#define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED        /*!< Polarity for ETRx clock sources */

+#define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING    /*!< Polarity for TIx clock sources */

+#define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */

+#define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler

+  * @{

+  */

+#define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1           /*!< No prescaler is used                                                     */

+#define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2           /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */

+#define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4           /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */

+#define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8           /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity

+  * @{

+  */

+#define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED      /*!< Polarity for ETRx pin */

+#define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED   /*!< Polarity for ETRx pin */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler

+  * @{

+  */

+#define TIM_CLEARINPUTPRESCALER_DIV1              TIM_ETRPRESCALER_DIV1         /*!< No prescaler is used                                                   */

+#define TIM_CLEARINPUTPRESCALER_DIV2              TIM_ETRPRESCALER_DIV2         /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */

+#define TIM_CLEARINPUTPRESCALER_DIV4              TIM_ETRPRESCALER_DIV4         /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */

+#define TIM_CLEARINPUTPRESCALER_DIV8              TIM_ETRPRESCALER_DIV8         /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state

+  * @{

+  */

+#define TIM_OSSR_ENABLE                          TIM_BDTR_OSSR                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */

+#define TIM_OSSR_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state

+  * @{

+  */

+#define TIM_OSSI_ENABLE                          TIM_BDTR_OSSI                  /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer)           */

+#define TIM_OSSI_DISABLE                         0x00000000U                    /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */

+/**

+  * @}

+  */

+/** @defgroup TIM_Lock_level  TIM Lock level

+  * @{

+  */

+#define TIM_LOCKLEVEL_OFF                  0x00000000U                          /*!< LOCK OFF     */

+#define TIM_LOCKLEVEL_1                    TIM_BDTR_LOCK_0                      /*!< LOCK Level 1 */

+#define TIM_LOCKLEVEL_2                    TIM_BDTR_LOCK_1                      /*!< LOCK Level 2 */

+#define TIM_LOCKLEVEL_3                    TIM_BDTR_LOCK                        /*!< LOCK Level 3 */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable

+  * @{

+  */

+#define TIM_BREAK_ENABLE                   TIM_BDTR_BKE                         /*!< Break input BRK is enabled  */

+#define TIM_BREAK_DISABLE                  0x00000000U                          /*!< Break input BRK is disabled */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Break_Polarity TIM Break Input Polarity

+  * @{

+  */

+#define TIM_BREAKPOLARITY_LOW              0x00000000U                          /*!< Break input BRK is active low  */

+#define TIM_BREAKPOLARITY_HIGH             TIM_BDTR_BKP                         /*!< Break input BRK is active high */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable

+  * @{

+  */

+#define TIM_BREAK2_DISABLE                 0x00000000U                          /*!< Break input BRK2 is disabled  */

+#define TIM_BREAK2_ENABLE                  TIM_BDTR_BK2E                        /*!< Break input BRK2 is enabled  */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity

+  * @{

+  */

+#define TIM_BREAK2POLARITY_LOW             0x00000000U                          /*!< Break input BRK2 is active low   */

+#define TIM_BREAK2POLARITY_HIGH            TIM_BDTR_BK2P                        /*!< Break input BRK2 is active high  */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable

+  * @{

+  */

+#define TIM_AUTOMATICOUTPUT_DISABLE        0x00000000U                          /*!< MOE can be set only by software */

+#define TIM_AUTOMATICOUTPUT_ENABLE         TIM_BDTR_AOE                         /*!< MOE can be set by software or automatically at the next update event 

+                                                                                    (if none of the break inputs BRK and BRK2 is active) */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Group_Channel5 Group Channel 5 and Channel 1, 2 or 3

+  * @{

+  */

+#define TIM_GROUPCH5_NONE                  0x00000000U                          /* !< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */

+#define TIM_GROUPCH5_OC1REFC               TIM_CCR5_GC5C1                       /* !< OC1REFC is the logical AND of OC1REFC and OC5REF    */

+#define TIM_GROUPCH5_OC2REFC               TIM_CCR5_GC5C2                       /* !< OC2REFC is the logical AND of OC2REFC and OC5REF    */

+#define TIM_GROUPCH5_OC3REFC               TIM_CCR5_GC5C3                       /* !< OC3REFC is the logical AND of OC3REFC and OC5REF    */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection

+  * @{

+  */

+#define TIM_TRGO_RESET            0x00000000U                                      /*!< TIMx_EGR.UG bit is used as trigger output (TRGO)              */

+#define TIM_TRGO_ENABLE           TIM_CR2_MMS_0                                    /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO)             */

+#define TIM_TRGO_UPDATE           TIM_CR2_MMS_1                                    /*!< Update event is used as trigger output (TRGO)                 */

+#define TIM_TRGO_OC1              (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                  /*!< Capture or a compare match 1 is used as trigger output (TRGO) */

+#define TIM_TRGO_OC1REF           TIM_CR2_MMS_2                                    /*!< OC1REF signal is used as trigger output (TRGO)                */

+#define TIM_TRGO_OC2REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                  /*!< OC2REF signal is used as trigger output(TRGO)                 */

+#define TIM_TRGO_OC3REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                  /*!< OC3REF signal is used as trigger output(TRGO)                 */

+#define TIM_TRGO_OC4REF           (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)  /*!< OC4REF signal is used as trigger output(TRGO)                 */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2)

+  * @{

+  */

+#define TIM_TRGO2_RESET                          0x00000000U                                                         /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2)              */

+#define TIM_TRGO2_ENABLE                         TIM_CR2_MMS2_0                                                      /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2)             */

+#define TIM_TRGO2_UPDATE                         TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output (TRGO2)                 */

+#define TIM_TRGO2_OC1                            (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */

+#define TIM_TRGO2_OC1REF                         TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output (TRGO2)                */

+#define TIM_TRGO2_OC2REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output (TRGO2)                */

+#define TIM_TRGO2_OC3REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output (TRGO2)                */

+#define TIM_TRGO2_OC4REF                         (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output (TRGO2)                */

+#define TIM_TRGO2_OC5REF                         TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output (TRGO2)                */

+#define TIM_TRGO2_OC6REF                         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output (TRGO2)                */

+#define TIM_TRGO2_OC4REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges generate pulses on TRGO2        */

+#define TIM_TRGO2_OC6REF_RISINGFALLING           (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges generate pulses on TRGO2        */

+#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2         */

+#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */

+#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */

+#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING   (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2         */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode

+  * @{

+  */

+#define TIM_MASTERSLAVEMODE_ENABLE         TIM_SMCR_MSM                         /*!< No action */

+#define TIM_MASTERSLAVEMODE_DISABLE        0x00000000U                          /*!< Master/slave mode is selected */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Slave_Mode TIM Slave mode

+  * @{

+  */

+#define TIM_SLAVEMODE_DISABLE                0x00000000U                                        /*!< Slave mode disabled           */

+#define TIM_SLAVEMODE_RESET                  TIM_SMCR_SMS_2                                     /*!< Reset Mode                    */

+#define TIM_SLAVEMODE_GATED                  (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)                  /*!< Gated Mode                    */

+#define TIM_SLAVEMODE_TRIGGER                (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)                  /*!< Trigger Mode                  */

+#define TIM_SLAVEMODE_EXTERNAL1              (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1         */

+#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER  TIM_SMCR_SMS_3                                     /*!< Combined reset + trigger mode */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes

+  * @{

+  */

+#define TIM_OCMODE_TIMING                   0x00000000U                                              /*!< Frozen                                 */

+#define TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!< Set channel to active level on match   */

+#define TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!< Set channel to inactive level on match */

+#define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!< Toggle                                 */

+#define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!< PWM mode 1                             */

+#define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2                             */

+#define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!< Force active level                     */

+#define TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!< Force inactive level                   */

+#define TIM_OCMODE_RETRIGERRABLE_OPM1      TIM_CCMR1_OC1M_3                                          /*!< Retrigerrable OPM mode 1               */

+#define TIM_OCMODE_RETRIGERRABLE_OPM2      (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                     /*!< Retrigerrable OPM mode 2               */

+#define TIM_OCMODE_COMBINED_PWM1           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                     /*!< Combined PWM mode 1                    */

+#define TIM_OCMODE_COMBINED_PWM2           (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)  /*!< Combined PWM mode 2                    */

+#define TIM_OCMODE_ASSYMETRIC_PWM1         (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)  /*!< Asymmetric PWM mode 1                  */

+#define TIM_OCMODE_ASSYMETRIC_PWM2         TIM_CCMR1_OC1M                                            /*!< Asymmetric PWM mode 2                  */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Trigger_Selection TIM Trigger Selection

+  * @{

+  */

+#define TIM_TS_ITR0          0x00000000U                                                       /*!< Internal Trigger 0 (ITR0)              */

+#define TIM_TS_ITR1          TIM_SMCR_TS_0                                                     /*!< Internal Trigger 1 (ITR1)              */

+#define TIM_TS_ITR2          TIM_SMCR_TS_1                                                     /*!< Internal Trigger 2 (ITR2)              */

+#define TIM_TS_ITR3          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                   /*!< Internal Trigger 3 (ITR3)              */

+#define TIM_TS_TI1F_ED       TIM_SMCR_TS_2                                                     /*!< TI1 Edge Detector (TI1F_ED)            */

+#define TIM_TS_TI1FP1        (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 1 (TI1FP1)        */

+#define TIM_TS_TI2FP2        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                                   /*!< Filtered Timer Input 2 (TI2FP2)        */

+#define TIM_TS_ETRF          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2)                   /*!< Filtered External Trigger input (ETRF) */

+#define TIM_TS_ITR4          (TIM_SMCR_TS_3)                                                   /*!< Internal Trigger 4 (ITR4)              */

+#define TIM_TS_ITR5          (TIM_SMCR_TS_0 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 5 (ITR5)              */

+#define TIM_TS_ITR6          (TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 6 (ITR6)              */

+#define TIM_TS_ITR7          (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 7 (ITR7)              */

+#define TIM_TS_ITR8          (TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                                   /*!< Internal Trigger 8 (ITR8)              */

+#define TIM_TS_ITR9          (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 9 (ITR9)              */

+#define TIM_TS_ITR10         (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                   /*!< Internal Trigger 10 (ITR10)            */

+#define TIM_TS_ITR11         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)   /*!< Internal Trigger 11 (ITR11)            */

+#define TIM_TS_ITR12         (TIM_SMCR_TS_4)                                                   /*!< Internal Trigger 12 (ITR12)            */

+#define TIM_TS_ITR13         (TIM_SMCR_TS_0 | TIM_SMCR_TS_4)                                   /*!< Internal Trigger 13 (ITR13)            */

+#define TIM_TS_NONE          0x0000FFFFU                                                       /*!< No trigger selected                    */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity

+  * @{

+  */

+#define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED               /*!< Polarity for ETRx trigger sources             */

+#define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED            /*!< Polarity for ETRx trigger sources             */

+#define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING        /*!< Polarity for TIxFPx or TI1_ED trigger sources */

+#define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING       /*!< Polarity for TIxFPx or TI1_ED trigger sources */

+#define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE      /*!< Polarity for TIxFPx or TI1_ED trigger sources */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler

+  * @{

+  */

+#define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1             /*!< No prescaler is used                                                       */

+#define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2             /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */

+#define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4             /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */

+#define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8             /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection

+  * @{

+  */

+#define TIM_TI1SELECTION_CH1               0x00000000U                          /*!< The TIMx_CH1 pin is connected to TI1 input */

+#define TIM_TI1SELECTION_XORCOMBINATION    TIM_CR2_TI1S                         /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length

+  * @{

+  */

+#define TIM_DMABURSTLENGTH_1TRANSFER       0x00000000U                          /*!< The transfer is done to 1 register starting trom TIMx_CR1 + TIMx_DCR.DBA   */

+#define TIM_DMABURSTLENGTH_2TRANSFERS      0x00000100U                          /*!< The transfer is done to 2 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */

+#define TIM_DMABURSTLENGTH_3TRANSFERS      0x00000200U                          /*!< The transfer is done to 3 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */

+#define TIM_DMABURSTLENGTH_4TRANSFERS      0x00000300U                          /*!< The transfer is done to 4 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */

+#define TIM_DMABURSTLENGTH_5TRANSFERS      0x00000400U                          /*!< The transfer is done to 5 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */

+#define TIM_DMABURSTLENGTH_6TRANSFERS      0x00000500U                          /*!< The transfer is done to 6 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */

+#define TIM_DMABURSTLENGTH_7TRANSFERS      0x00000600U                          /*!< The transfer is done to 7 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */

+#define TIM_DMABURSTLENGTH_8TRANSFERS      0x00000700U                          /*!< The transfer is done to 8 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */

+#define TIM_DMABURSTLENGTH_9TRANSFERS      0x00000800U                          /*!< The transfer is done to 9 registers starting trom TIMx_CR1 + TIMx_DCR.DBA  */

+#define TIM_DMABURSTLENGTH_10TRANSFERS     0x00000900U                          /*!< The transfer is done to 10 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */

+#define TIM_DMABURSTLENGTH_11TRANSFERS     0x00000A00U                          /*!< The transfer is done to 11 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */

+#define TIM_DMABURSTLENGTH_12TRANSFERS     0x00000B00U                          /*!< The transfer is done to 12 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */

+#define TIM_DMABURSTLENGTH_13TRANSFERS     0x00000C00U                          /*!< The transfer is done to 13 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */

+#define TIM_DMABURSTLENGTH_14TRANSFERS     0x00000D00U                          /*!< The transfer is done to 14 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */

+#define TIM_DMABURSTLENGTH_15TRANSFERS     0x00000E00U                          /*!< The transfer is done to 15 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */

+#define TIM_DMABURSTLENGTH_16TRANSFERS     0x00000F00U                          /*!< The transfer is done to 16 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */

+#define TIM_DMABURSTLENGTH_17TRANSFERS     0x00001000U                          /*!< The transfer is done to 17 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */

+#define TIM_DMABURSTLENGTH_18TRANSFERS     0x00001100U                          /*!< The transfer is done to 18 registers starting trom TIMx_CR1 + TIMx_DCR.DBA */

+/**

+  * @}

+  */

+

+/** @defgroup DMA_Handle_index TIM DMA Handle Index

+  * @{

+  */

+#define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0000)       /*!< Index of the DMA handle used for Update DMA requests */

+#define TIM_DMA_ID_CC1                   ((uint16_t) 0x0001)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */

+#define TIM_DMA_ID_CC2                   ((uint16_t) 0x0002)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */

+#define TIM_DMA_ID_CC3                   ((uint16_t) 0x0003)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */

+#define TIM_DMA_ID_CC4                   ((uint16_t) 0x0004)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */

+#define TIM_DMA_ID_COMMUTATION           ((uint16_t) 0x0005)       /*!< Index of the DMA handle used for Commutation DMA requests */

+#define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x0006)       /*!< Index of the DMA handle used for Trigger DMA requests */

+/**

+  * @}

+  */

+

+/** @defgroup Channel_CC_State TIM Capture/Compare Channel State

+  * @{

+  */

+#define TIM_CCx_ENABLE                   0x00000001U                            /*!< Input or output channel is enabled */

+#define TIM_CCx_DISABLE                  0x00000000U                            /*!< Input or output channel is disabled */

+#define TIM_CCxN_ENABLE                  0x00000004U                            /*!< Complementary output channel is enabled */

+#define TIM_CCxN_DISABLE                 0x00000000U                            /*!< Complementary output channel is enabled */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Break_System TIM Break System

+  * @{

+  */

+#define TIM_BREAK_SYSTEM_ECC                 SYSCFG_CFGR2_ECCL   /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17 */

+#define TIM_BREAK_SYSTEM_PVD                 SYSCFG_CFGR2_PVDL   /*!< Enables and locks the PVD connection with TIM1/8/15/16/17 Break Input and also the PVDE and PLS bits of the Power Control Interface */

+#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR   SYSCFG_CFGR2_SPL    /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17 */

+#define TIM_BREAK_SYSTEM_LOCKUP              SYSCFG_CFGR2_CLL    /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17 */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+/* End of exported constants -------------------------------------------------*/

+

+/* Exported macros -----------------------------------------------------------*/

+/** @defgroup TIM_Exported_Macros TIM Exported Macros

+  * @{

+  */

+

+/** @brief  Reset TIM handle state.

+  * @param  __HANDLE__ TIM handle.

+  * @retval None

+  */

+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)

+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do {                                                        \

+                                                      (__HANDLE__)->State             = HAL_TIM_STATE_RESET; \

+                                                      (__HANDLE__)->Base_MspInitCallback         = NULL;     \

+                                                      (__HANDLE__)->Base_MspDeInitCallback       = NULL;     \

+                                                      (__HANDLE__)->IC_MspInitCallback           = NULL;     \

+                                                      (__HANDLE__)->IC_MspDeInitCallback         = NULL;     \

+                                                      (__HANDLE__)->OC_MspInitCallback           = NULL;     \

+                                                      (__HANDLE__)->OC_MspDeInitCallback         = NULL;     \

+                                                      (__HANDLE__)->PWM_MspInitCallback          = NULL;     \

+                                                      (__HANDLE__)->PWM_MspDeInitCallback        = NULL;     \

+                                                      (__HANDLE__)->OnePulse_MspInitCallback     = NULL;     \

+                                                      (__HANDLE__)->OnePulse_MspDeInitCallback   = NULL;     \

+                                                      (__HANDLE__)->Encoder_MspInitCallback      = NULL;     \

+                                                      (__HANDLE__)->Encoder_MspDeInitCallback    = NULL;     \

+                                                      (__HANDLE__)->HallSensor_MspInitCallback   = NULL;     \

+                                                      (__HANDLE__)->HallSensor_MspDeInitCallback = NULL;     \

+                                                     } while(0)

+#else

+#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)

+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

+

+/**

+  * @brief  Enable the TIM peripheral.

+  * @param  __HANDLE__ TIM handle

+  * @retval None

+  */

+#define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))

+

+/**

+  * @brief  Enable the TIM main Output.

+  * @param  __HANDLE__ TIM handle

+  * @retval None

+  */

+#define __HAL_TIM_MOE_ENABLE(__HANDLE__)             ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))

+

+/**

+  * @brief  Disable the TIM peripheral.

+  * @param  __HANDLE__ TIM handle

+  * @retval None

+  */

+#define __HAL_TIM_DISABLE(__HANDLE__) \

+  do { \

+    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \

+    { \

+      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \

+      { \

+        (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \

+      } \

+    } \

+  } while(0)

+

+/**

+  * @brief  Disable the TIM main Output.

+  * @param  __HANDLE__ TIM handle

+  * @retval None

+  * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled

+  */

+#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \

+  do { \

+    if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \

+    { \

+      if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \

+      { \

+        (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \

+      } \

+    } \

+  } while(0)

+

+/**

+  * @brief  Disable the TIM main Output.

+  * @param  __HANDLE__ TIM handle

+  * @retval None

+  * @note The Main Output Enable of a timer instance is disabled unconditionally

+  */

+#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__)  (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)

+

+/** @brief  Enable the specified TIM interrupt.

+  * @param  __HANDLE__ specifies the TIM Handle.

+  * @param  __INTERRUPT__ specifies the TIM interrupt source to enable.

+  *          This parameter can be one of the following values:

+  *            @arg TIM_IT_UPDATE: Update interrupt

+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt

+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt

+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt

+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt

+  *            @arg TIM_IT_COM:   Commutation interrupt

+  *            @arg TIM_IT_TRIGGER: Trigger interrupt

+  *            @arg TIM_IT_BREAK: Break interrupt

+  * @retval None

+  */

+#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))

+

+/** @brief  Disable the specified TIM interrupt.

+  * @param  __HANDLE__ specifies the TIM Handle.

+  * @param  __INTERRUPT__ specifies the TIM interrupt source to disable.

+  *          This parameter can be one of the following values:

+  *            @arg TIM_IT_UPDATE: Update interrupt

+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt

+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt

+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt

+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt

+  *            @arg TIM_IT_COM:   Commutation interrupt

+  *            @arg TIM_IT_TRIGGER: Trigger interrupt

+  *            @arg TIM_IT_BREAK: Break interrupt

+  * @retval None

+  */

+#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))

+

+/** @brief  Enable the specified DMA request.

+  * @param  __HANDLE__ specifies the TIM Handle.

+  * @param  __DMA__ specifies the TIM DMA request to enable.

+  *          This parameter can be one of the following values:

+  *            @arg TIM_DMA_UPDATE: Update DMA request

+  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request

+  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request

+  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request

+  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request

+  *            @arg TIM_DMA_COM:   Commutation DMA request

+  *            @arg TIM_DMA_TRIGGER: Trigger DMA request

+  * @retval None

+  */

+#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))

+

+/** @brief  Disable the specified DMA request.

+  * @param  __HANDLE__ specifies the TIM Handle.

+  * @param  __DMA__ specifies the TIM DMA request to disable.

+  *          This parameter can be one of the following values:

+  *            @arg TIM_DMA_UPDATE: Update DMA request

+  *            @arg TIM_DMA_CC1:   Capture/Compare 1 DMA request

+  *            @arg TIM_DMA_CC2:  Capture/Compare 2 DMA request

+  *            @arg TIM_DMA_CC3:  Capture/Compare 3 DMA request

+  *            @arg TIM_DMA_CC4:  Capture/Compare 4 DMA request

+  *            @arg TIM_DMA_COM:   Commutation DMA request

+  *            @arg TIM_DMA_TRIGGER: Trigger DMA request

+  * @retval None

+  */

+#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))

+

+/** @brief  Check whether the specified TIM interrupt flag is set or not.

+  * @param  __HANDLE__ specifies the TIM Handle.

+  * @param  __FLAG__ specifies the TIM interrupt flag to check.

+  *        This parameter can be one of the following values:

+  *            @arg TIM_FLAG_UPDATE: Update interrupt flag

+  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag

+  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag

+  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag

+  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag

+  *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag

+  *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag

+  *            @arg TIM_FLAG_COM:  Commutation interrupt flag

+  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag

+  *            @arg TIM_FLAG_BREAK: Break interrupt flag

+  *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag

+  *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag

+  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag

+  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag

+  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag

+  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag

+  * @retval The new state of __FLAG__ (TRUE or FALSE).

+  */

+#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))

+

+/** @brief  Clear the specified TIM interrupt flag.

+  * @param  __HANDLE__ specifies the TIM Handle.

+  * @param  __FLAG__ specifies the TIM interrupt flag to clear.

+  *        This parameter can be one of the following values:

+  *            @arg TIM_FLAG_UPDATE: Update interrupt flag

+  *            @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag

+  *            @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag

+  *            @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag

+  *            @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag

+  *            @arg TIM_FLAG_CC5: Compare 5 interrupt flag

+  *            @arg TIM_FLAG_CC6: Compare 6 interrupt flag

+  *            @arg TIM_FLAG_COM:  Commutation interrupt flag

+  *            @arg TIM_FLAG_TRIGGER: Trigger interrupt flag

+  *            @arg TIM_FLAG_BREAK: Break interrupt flag

+  *            @arg TIM_FLAG_BREAK2: Break 2 interrupt flag

+  *            @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag

+  *            @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag

+  *            @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag

+  *            @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag

+  *            @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag

+  * @retval The new state of __FLAG__ (TRUE or FALSE).

+  */

+#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))

+

+/**

+  * @brief  Check whether the specified TIM interrupt source is enabled or not.

+  * @param  __HANDLE__ TIM handle

+  * @param  __INTERRUPT__ specifies the TIM interrupt source to check.

+  *          This parameter can be one of the following values:

+  *            @arg TIM_IT_UPDATE: Update interrupt

+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt

+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt

+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt

+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt

+  *            @arg TIM_IT_COM:   Commutation interrupt

+  *            @arg TIM_IT_TRIGGER: Trigger interrupt

+  *            @arg TIM_IT_BREAK: Break interrupt

+  * @retval The state of TIM_IT (SET or RESET).

+  */

+#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \

+                                                             == (__INTERRUPT__)) ? SET : RESET)

+

+/** @brief Clear the TIM interrupt pending bits.

+  * @param  __HANDLE__ TIM handle

+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.

+  *          This parameter can be one of the following values:

+  *            @arg TIM_IT_UPDATE: Update interrupt

+  *            @arg TIM_IT_CC1:   Capture/Compare 1 interrupt

+  *            @arg TIM_IT_CC2:  Capture/Compare 2 interrupt

+  *            @arg TIM_IT_CC3:  Capture/Compare 3 interrupt

+  *            @arg TIM_IT_CC4:  Capture/Compare 4 interrupt

+  *            @arg TIM_IT_COM:   Commutation interrupt

+  *            @arg TIM_IT_TRIGGER: Trigger interrupt

+  *            @arg TIM_IT_BREAK: Break interrupt

+  * @retval None

+  */

+#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))

+

+/**

+  * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).

+  * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.

+  * @param  __HANDLE__ TIM handle.

+  * @retval None

+mode.

+  */

+#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__)    (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP))

+

+/**

+  * @brief  Disable update interrupt flag (UIF) remapping.

+  * @param  __HANDLE__ TIM handle.

+  * @retval None

+mode.

+  */

+#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP))

+

+/**

+  * @brief  Get update interrupt flag (UIF) copy status.

+  * @param  __COUNTER__ Counter value.

+  * @retval The state of UIFCPY (TRUE or FALSE).

+mode.

+  */

+#define __HAL_TIM_GET_UIFCPY(__COUNTER__)    (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY))

+

+/**

+  * @brief  Indicates whether or not the TIM Counter is used as downcounter.

+  * @param  __HANDLE__ TIM handle.

+  * @retval False (Counter used as upcounter) or True (Counter used as downcounter)

+  * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder

+mode.

+  */

+#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__)    (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))

+

+/**

+  * @brief  Set the TIM Prescaler on runtime.

+  * @param  __HANDLE__ TIM handle.

+  * @param  __PRESC__ specifies the Prescaler new value.

+  * @retval None

+  */

+#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__)       ((__HANDLE__)->Instance->PSC = (__PRESC__))

+

+/**

+  * @brief  Set the TIM Counter Register value on runtime.

+  * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in case of 32 bits counter TIM instance.

+  *      Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros.

+  * @param  __HANDLE__ TIM handle.

+  * @param  __COUNTER__ specifies the Counter register new value.

+  * @retval None

+  */

+#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))

+

+/**

+  * @brief  Get the TIM Counter Register value on runtime.

+  * @param  __HANDLE__ TIM handle.

+  * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)

+  */

+#define __HAL_TIM_GET_COUNTER(__HANDLE__)  ((__HANDLE__)->Instance->CNT)

+

+/**

+  * @brief  Set the TIM Autoreload Register value on runtime without calling another time any Init function.

+  * @param  __HANDLE__ TIM handle.

+  * @param  __AUTORELOAD__ specifies the Counter register new value.

+  * @retval None

+  */

+#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \

+  do{                                                    \

+    (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \

+    (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \

+  } while(0)

+

+/**

+  * @brief  Get the TIM Autoreload Register value on runtime.

+  * @param  __HANDLE__ TIM handle.

+  * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)

+  */

+#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__)  ((__HANDLE__)->Instance->ARR)

+

+/**

+  * @brief  Set the TIM Clock Division value on runtime without calling another time any Init function.

+  * @param  __HANDLE__ TIM handle.

+  * @param  __CKD__ specifies the clock division value.

+  *          This parameter can be one of the following value:

+  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT

+  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT

+  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT

+  * @retval None

+  */

+#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \

+  do{                                                   \

+    (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD);  \

+    (__HANDLE__)->Instance->CR1 |= (__CKD__);       \

+    (__HANDLE__)->Init.ClockDivision = (__CKD__);   \

+  } while(0)

+

+/**

+  * @brief  Get the TIM Clock Division value on runtime.

+  * @param  __HANDLE__ TIM handle.

+  * @retval The clock division can be one of the following values:

+  *            @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT

+  *            @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT

+  *            @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT

+  */

+#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__)  ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)

+

+/**

+  * @brief  Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.

+  * @param  __HANDLE__ TIM handle.

+  * @param  __CHANNEL__ TIM Channels to be configured.

+  *          This parameter can be one of the following values:

+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected

+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected

+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected

+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected

+  * @param  __ICPSC__ specifies the Input Capture4 prescaler new value.

+  *          This parameter can be one of the following values:

+  *            @arg TIM_ICPSC_DIV1: no prescaler

+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events

+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events

+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events

+  * @retval None

+  */

+#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \

+  do{                                                    \

+    TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__));  \

+    TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \

+  } while(0)

+

+/**

+  * @brief  Get the TIM Input Capture prescaler on runtime.

+  * @param  __HANDLE__ TIM handle.

+  * @param  __CHANNEL__ TIM Channels to be configured.

+  *          This parameter can be one of the following values:

+  *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value

+  *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value

+  *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value

+  *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value

+  * @retval The input capture prescaler can be one of the following values:

+  *            @arg TIM_ICPSC_DIV1: no prescaler

+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events

+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events

+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events

+  */

+#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__)  \

+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\

+   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\

+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\

+   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U)

+

+/**

+  * @brief  Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function.

+  * @param  __HANDLE__ TIM handle.

+  * @param  __CHANNEL__ TIM Channels to be configured.

+  *          This parameter can be one of the following values:

+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected

+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected

+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected

+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected

+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected

+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected

+  * @param  __COMPARE__ specifies the Capture Compare register new value.

+  * @retval None

+  */

+#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \

+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\

+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\

+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\

+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\

+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\

+   ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))

+

+/**

+  * @brief  Get the TIM Capture Compare Register value on runtime.

+  * @param  __HANDLE__ TIM handle.

+  * @param  __CHANNEL__ TIM Channel associated with the capture compare register

+  *          This parameter can be one of the following values:

+  *            @arg TIM_CHANNEL_1: get capture/compare 1 register value

+  *            @arg TIM_CHANNEL_2: get capture/compare 2 register value

+  *            @arg TIM_CHANNEL_3: get capture/compare 3 register value

+  *            @arg TIM_CHANNEL_4: get capture/compare 4 register value

+  *            @arg TIM_CHANNEL_5: get capture/compare 5 register value

+  *            @arg TIM_CHANNEL_6: get capture/compare 6 register value

+  * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)

+  */

+#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \

+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\

+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\

+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\

+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\

+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\

+   ((__HANDLE__)->Instance->CCR6))

+

+/**

+  * @brief  Set the TIM Output compare preload.

+  * @param  __HANDLE__ TIM handle.

+  * @param  __CHANNEL__ TIM Channels to be configured.

+  *          This parameter can be one of the following values:

+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected

+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected

+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected

+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected

+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected

+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected

+  * @retval None

+  */

+#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \

+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\

+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\

+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\

+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\

+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\

+   ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))

+

+/**

+  * @brief  Reset the TIM Output compare preload.

+  * @param  __HANDLE__ TIM handle.

+  * @param  __CHANNEL__ TIM Channels to be configured.

+  *          This parameter can be one of the following values:

+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected

+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected

+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected

+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected

+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected

+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected

+  * @retval None

+  */

+#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__)    \

+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\

+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\

+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\

+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\

+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\

+   ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))

+

+/**

+  * @brief  Enable fast mode for a given channel.

+  * @param  __HANDLE__ TIM handle.

+  * @param  __CHANNEL__ TIM Channels to be configured.

+  *          This parameter can be one of the following values:

+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected

+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected

+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected

+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected

+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected

+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected

+  * @note  When fast mode is enabled an active edge on the trigger input acts

+  *        like a compare match on CCx output. Delay to sample the trigger

+  *        input and to activate CCx output is reduced to 3 clock cycles.

+  * @note  Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.

+  * @retval None

+  */

+#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \

+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\

+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\

+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\

+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\

+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\

+   ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))

+

+/**

+  * @brief  Disable fast mode for a given channel.

+  * @param  __HANDLE__ TIM handle.

+  * @param  __CHANNEL__ TIM Channels to be configured.

+  *          This parameter can be one of the following values:

+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected

+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected

+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected

+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected

+  *            @arg TIM_CHANNEL_5: TIM Channel 5 selected

+  *            @arg TIM_CHANNEL_6: TIM Channel 6 selected

+  * @note  When fast mode is disabled CCx output behaves normally depending

+  *        on counter and CCRx values even when the trigger is ON. The minimum

+  *        delay to activate CCx output when an active edge occurs on the

+  *        trigger input is 5 clock cycles.

+  * @retval None

+  */

+#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__)    \

+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\

+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\

+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\

+   ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\

+   ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\

+   ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))

+

+/**

+  * @brief  Set the Update Request Source (URS) bit of the TIMx_CR1 register.

+  * @param  __HANDLE__ TIM handle.

+  * @note  When the URS bit of the TIMx_CR1 register is set, only counter

+  *        overflow/underflow generates an update interrupt or DMA request (if

+  *        enabled)

+  * @retval None

+  */

+#define __HAL_TIM_URS_ENABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)

+

+/**

+  * @brief  Reset the Update Request Source (URS) bit of the TIMx_CR1 register.

+  * @param  __HANDLE__ TIM handle.

+  * @note  When the URS bit of the TIMx_CR1 register is reset, any of the

+  *        following events generate an update interrupt or DMA request (if

+  *        enabled):

+  *           _ Counter overflow underflow

+  *           _ Setting the UG bit

+  *           _ Update generation through the slave mode controller

+  * @retval None

+  */

+#define __HAL_TIM_URS_DISABLE(__HANDLE__)  ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)

+

+/**

+  * @brief  Set the TIM Capture x input polarity on runtime.

+  * @param  __HANDLE__ TIM handle.

+  * @param  __CHANNEL__ TIM Channels to be configured.

+  *          This parameter can be one of the following values:

+  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected

+  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected

+  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected

+  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected

+  * @param  __POLARITY__ Polarity for TIx source

+  *            @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge

+  *            @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge

+  *            @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge

+  * @retval None

+  */

+#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__)    \

+  do{                                                                     \

+    TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__));               \

+    TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \

+  }while(0)

+

+/**

+  * @}

+  */

+/* End of exported macros ----------------------------------------------------*/

+

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup TIM_Private_Constants TIM Private Constants

+  * @{

+  */

+/* The counter of a timer instance is disabled only if all the CCx and CCxN

+   channels have been disabled */

+#define TIM_CCER_CCxE_MASK  ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))

+#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))

+/**

+  * @}

+  */

+/* End of private constants --------------------------------------------------*/

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup TIM_Private_Macros TIM Private Macros

+  * @{

+  */

+#define IS_TIM_CLEARINPUT_SOURCE(__MODE__)  (((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)      || \

+                                             ((__MODE__) == TIM_CLEARINPUTSOURCE_ETR))

+

+#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1)   || \

+                                   ((__BASE__) == TIM_DMABASE_CR2)   || \

+                                   ((__BASE__) == TIM_DMABASE_SMCR)  || \

+                                   ((__BASE__) == TIM_DMABASE_DIER)  || \

+                                   ((__BASE__) == TIM_DMABASE_SR)    || \

+                                   ((__BASE__) == TIM_DMABASE_EGR)   || \

+                                   ((__BASE__) == TIM_DMABASE_CCMR1) || \

+                                   ((__BASE__) == TIM_DMABASE_CCMR2) || \

+                                   ((__BASE__) == TIM_DMABASE_CCER)  || \

+                                   ((__BASE__) == TIM_DMABASE_CNT)   || \

+                                   ((__BASE__) == TIM_DMABASE_PSC)   || \

+                                   ((__BASE__) == TIM_DMABASE_ARR)   || \

+                                   ((__BASE__) == TIM_DMABASE_RCR)   || \

+                                   ((__BASE__) == TIM_DMABASE_CCR1)  || \

+                                   ((__BASE__) == TIM_DMABASE_CCR2)  || \

+                                   ((__BASE__) == TIM_DMABASE_CCR3)  || \

+                                   ((__BASE__) == TIM_DMABASE_CCR4)  || \

+                                   ((__BASE__) == TIM_DMABASE_BDTR)  || \

+                                   ((__BASE__) == TIM_DMABASE_CCMR3) || \

+                                   ((__BASE__) == TIM_DMABASE_CCR5)  || \

+                                   ((__BASE__) == TIM_DMABASE_CCR6)  || \

+                                   ((__BASE__) == TIM_DMABASE_AF1)   || \

+                                   ((__BASE__) == TIM_DMABASE_AF2)   || \

+                                   ((__BASE__) == TIM_DMABASE_TISEL))

+

+

+#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))

+

+#define IS_TIM_COUNTER_MODE(__MODE__)      (((__MODE__) == TIM_COUNTERMODE_UP)              || \

+                                            ((__MODE__) == TIM_COUNTERMODE_DOWN)            || \

+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1)  || \

+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2)  || \

+                                            ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))

+

+#define IS_TIM_UIFREMAP_MODE(__MODE__)     (((__MODE__) == TIM_UIFREMAP_DISABLE) || \

+                                            ((__MODE__) == TIM_UIFREMAP_ENALE))

+

+#define IS_TIM_CLOCKDIVISION_DIV(__DIV__)  (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \

+                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \

+                                            ((__DIV__) == TIM_CLOCKDIVISION_DIV4))

+

+#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \

+                                            ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))

+

+#define IS_TIM_FAST_STATE(__STATE__)       (((__STATE__) == TIM_OCFAST_DISABLE) || \

+                                            ((__STATE__) == TIM_OCFAST_ENABLE))

+

+#define IS_TIM_OC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \

+                                            ((__POLARITY__) == TIM_OCPOLARITY_LOW))

+

+#define IS_TIM_OCN_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \

+                                            ((__POLARITY__) == TIM_OCNPOLARITY_LOW))

+

+#define IS_TIM_OCIDLE_STATE(__STATE__)     (((__STATE__) == TIM_OCIDLESTATE_SET) || \

+                                            ((__STATE__) == TIM_OCIDLESTATE_RESET))

+

+#define IS_TIM_OCNIDLE_STATE(__STATE__)    (((__STATE__) == TIM_OCNIDLESTATE_SET) || \

+                                            ((__STATE__) == TIM_OCNIDLESTATE_RESET))

+

+#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING)   || \

+                                                      ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))

+

+#define IS_TIM_IC_POLARITY(__POLARITY__)   (((__POLARITY__) == TIM_ICPOLARITY_RISING)   || \

+                                            ((__POLARITY__) == TIM_ICPOLARITY_FALLING)  || \

+                                            ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))

+

+#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \

+                                            ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \

+                                            ((__SELECTION__) == TIM_ICSELECTION_TRC))

+

+#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \

+                                            ((__PRESCALER__) == TIM_ICPSC_DIV2) || \

+                                            ((__PRESCALER__) == TIM_ICPSC_DIV4) || \

+                                            ((__PRESCALER__) == TIM_ICPSC_DIV8))

+

+#define IS_TIM_OPM_MODE(__MODE__)          (((__MODE__) == TIM_OPMODE_SINGLE) || \

+                                            ((__MODE__) == TIM_OPMODE_REPETITIVE))

+

+#define IS_TIM_ENCODER_MODE(__MODE__)      (((__MODE__) == TIM_ENCODERMODE_TI1) || \

+                                            ((__MODE__) == TIM_ENCODERMODE_TI2) || \

+                                            ((__MODE__) == TIM_ENCODERMODE_TI12))

+

+#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))

+

+#define IS_TIM_CHANNELS(__CHANNEL__)       (((__CHANNEL__) == TIM_CHANNEL_1) || \

+                                            ((__CHANNEL__) == TIM_CHANNEL_2) || \

+                                            ((__CHANNEL__) == TIM_CHANNEL_3) || \

+                                            ((__CHANNEL__) == TIM_CHANNEL_4) || \

+                                            ((__CHANNEL__) == TIM_CHANNEL_5) || \

+                                            ((__CHANNEL__) == TIM_CHANNEL_6) || \

+                                            ((__CHANNEL__) == TIM_CHANNEL_ALL))

+

+#define IS_TIM_OPM_CHANNELS(__CHANNEL__)   (((__CHANNEL__) == TIM_CHANNEL_1) || \

+                                            ((__CHANNEL__) == TIM_CHANNEL_2))

+

+#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \

+                                                    ((__CHANNEL__) == TIM_CHANNEL_2) || \

+                                                    ((__CHANNEL__) == TIM_CHANNEL_3))

+

+#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \

+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \

+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0)     || \

+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1)     || \

+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2)     || \

+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3)     || \

+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED)    || \

+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI1)      || \

+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_TI2)      || \

+                                       ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))

+

+#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED)    || \

+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \

+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING)      || \

+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING)     || \

+                                            ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))

+

+#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \

+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \

+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \

+                                              ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))

+

+#define IS_TIM_CLOCKFILTER(__ICFILTER__)      ((__ICFILTER__) <= 0xFU)

+

+#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \

+                                                  ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))

+

+#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \

+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \

+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \

+                                                    ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))

+

+#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)

+

+#define IS_TIM_OSSR_STATE(__STATE__)       (((__STATE__) == TIM_OSSR_ENABLE) || \

+                                            ((__STATE__) == TIM_OSSR_DISABLE))

+

+#define IS_TIM_OSSI_STATE(__STATE__)       (((__STATE__) == TIM_OSSI_ENABLE) || \

+                                            ((__STATE__) == TIM_OSSI_DISABLE))

+

+#define IS_TIM_LOCK_LEVEL(__LEVEL__)       (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \

+                                            ((__LEVEL__) == TIM_LOCKLEVEL_1)   || \

+                                            ((__LEVEL__) == TIM_LOCKLEVEL_2)   || \

+                                            ((__LEVEL__) == TIM_LOCKLEVEL_3))

+

+#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)

+

+

+#define IS_TIM_BREAK_STATE(__STATE__)      (((__STATE__) == TIM_BREAK_ENABLE) || \

+                                            ((__STATE__) == TIM_BREAK_DISABLE))

+

+#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \

+                                             ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))

+

+#define IS_TIM_BREAK2_STATE(__STATE__)     (((__STATE__) == TIM_BREAK2_ENABLE) || \

+                                            ((__STATE__) == TIM_BREAK2_DISABLE))

+

+#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \

+                                              ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH))

+

+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \

+                                                  ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))

+

+#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U))

+

+#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET)  || \

+                                        ((__SOURCE__) == TIM_TRGO_ENABLE) || \

+                                        ((__SOURCE__) == TIM_TRGO_UPDATE) || \

+                                        ((__SOURCE__) == TIM_TRGO_OC1)    || \

+                                        ((__SOURCE__) == TIM_TRGO_OC1REF) || \

+                                        ((__SOURCE__) == TIM_TRGO_OC2REF) || \

+                                        ((__SOURCE__) == TIM_TRGO_OC3REF) || \

+                                        ((__SOURCE__) == TIM_TRGO_OC4REF))

+

+#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET)                        || \

+                                         ((__SOURCE__) == TIM_TRGO2_ENABLE)                       || \

+                                         ((__SOURCE__) == TIM_TRGO2_UPDATE)                       || \

+                                         ((__SOURCE__) == TIM_TRGO2_OC1)                          || \

+                                         ((__SOURCE__) == TIM_TRGO2_OC1REF)                       || \

+                                         ((__SOURCE__) == TIM_TRGO2_OC2REF)                       || \

+                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \

+                                         ((__SOURCE__) == TIM_TRGO2_OC3REF)                       || \

+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF)                       || \

+                                         ((__SOURCE__) == TIM_TRGO2_OC5REF)                       || \

+                                         ((__SOURCE__) == TIM_TRGO2_OC6REF)                       || \

+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING)         || \

+                                         ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING)         || \

+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING)  || \

+                                         ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \

+                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING)  || \

+                                         ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING))

+

+#define IS_TIM_MSM_STATE(__STATE__)      (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \

+                                          ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))

+

+#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE)   || \

+                                     ((__MODE__) == TIM_SLAVEMODE_RESET)     || \

+                                     ((__MODE__) == TIM_SLAVEMODE_GATED)     || \

+                                     ((__MODE__) == TIM_SLAVEMODE_TRIGGER)   || \

+                                     ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \

+                                     ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))

+

+#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1)               || \

+                                   ((__MODE__) == TIM_OCMODE_PWM2)               || \

+                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM1)      || \

+                                   ((__MODE__) == TIM_OCMODE_COMBINED_PWM2)      || \

+                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1)    || \

+                                   ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))

+

+#define IS_TIM_OC_MODE(__MODE__)  (((__MODE__) == TIM_OCMODE_TIMING)             || \

+                                   ((__MODE__) == TIM_OCMODE_ACTIVE)             || \

+                                   ((__MODE__) == TIM_OCMODE_INACTIVE)           || \

+                                   ((__MODE__) == TIM_OCMODE_TOGGLE)             || \

+                                   ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE)      || \

+                                   ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)    || \

+                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \

+                                   ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2))

+

+#define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \

+                                                 ((__SELECTION__) == TIM_TS_ITR1) || \

+                                                 ((__SELECTION__) == TIM_TS_ITR2) || \

+                                                 ((__SELECTION__) == TIM_TS_ITR3) || \

+                                                 ((__SELECTION__) == TIM_TS_TI1F_ED) || \

+                                                 ((__SELECTION__) == TIM_TS_TI1FP1) || \

+                                                 ((__SELECTION__) == TIM_TS_TI2FP2) || \

+                                                 ((__SELECTION__) == TIM_TS_ETRF) || \

+                                                 ((__SELECTION__) == TIM_TS_ITR4) || \

+                                                 ((__SELECTION__) == TIM_TS_ITR5) || \

+                                                 ((__SELECTION__) == TIM_TS_ITR6) || \

+                                                 ((__SELECTION__) == TIM_TS_ITR7) || \

+                                                 ((__SELECTION__) == TIM_TS_ITR8) || \

+                                                 ((__SELECTION__) == TIM_TS_ITR12) || \

+                                                 ((__SELECTION__) == TIM_TS_ITR13))

+

+#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \

+                                                               ((__SELECTION__) == TIM_TS_ITR1) || \

+                                                               ((__SELECTION__) == TIM_TS_ITR2) || \

+                                                               ((__SELECTION__) == TIM_TS_ITR3) || \

+                                                               ((__SELECTION__) == TIM_TS_ITR4) || \

+                                                               ((__SELECTION__) == TIM_TS_ITR5) || \

+                                                               ((__SELECTION__) == TIM_TS_ITR6) || \

+                                                               ((__SELECTION__) == TIM_TS_ITR7) || \

+                                                               ((__SELECTION__) == TIM_TS_ITR8) || \

+                                                               ((__SELECTION__) == TIM_TS_ITR12) || \

+                                                               ((__SELECTION__) == TIM_TS_ITR13) || \

+                                                               ((__SELECTION__) == TIM_TS_NONE))

+

+#define IS_TIM_TRIGGERPOLARITY(__POLARITY__)   (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED   ) || \

+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \

+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING     ) || \

+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING    ) || \

+                                                ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))

+

+#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \

+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \

+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \

+                                                ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))

+

+#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU)

+

+#define IS_TIM_TI1SELECTION(__TI1SELECTION__)  (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \

+                                                ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))

+

+#define IS_TIM_DMA_LENGTH(__LENGTH__)      (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \

+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \

+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \

+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \

+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \

+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \

+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \

+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \

+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \

+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \

+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \

+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \

+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \

+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \

+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \

+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \

+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \

+                                            ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))

+

+#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U))

+

+#define IS_TIM_IC_FILTER(__ICFILTER__)   ((__ICFILTER__) <= 0xFU)

+

+#define IS_TIM_DEADTIME(__DEADTIME__)    ((__DEADTIME__) <= 0xFFU)

+

+#define IS_TIM_BREAK_SYSTEM(__CONFIG__)    (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC)                  || \

+                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD)                  || \

+                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR)    || \

+                                            ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP))

+

+#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \

+                                                       ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))

+

+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \

+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\

+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\

+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\

+   ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))

+

+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \

+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\

+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\

+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\

+   ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))

+

+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \

+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\

+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\

+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\

+   ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))

+

+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \

+  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\

+   ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\

+   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\

+   ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))

+

+/**

+  * @}

+  */

+/* End of private macros -----------------------------------------------------*/

+

+/* Include TIM HAL Extended module */

+#include "stm32h7xx_hal_tim_ex.h"

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup TIM_Exported_Functions TIM Exported Functions

+  * @{

+  */

+

+/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions

+  *  @brief   Time Base functions

+  * @{

+  */

+/* Time Base functions ********************************************************/

+HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);

+HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);

+void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);

+void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);

+/* Blocking mode: Polling */

+HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);

+HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);

+/* Non-Blocking mode: Interrupt */

+HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);

+HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);

+/* Non-Blocking mode: DMA */

+HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);

+HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);

+/**

+  * @}

+  */

+

+/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions

+  *  @brief   TIM Output Compare functions

+  * @{

+  */

+/* Timer Output Compare functions *********************************************/

+HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);

+HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);

+void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);

+void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);

+/* Blocking mode: Polling */

+HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);

+HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);

+/* Non-Blocking mode: Interrupt */

+HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);

+HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);

+/* Non-Blocking mode: DMA */

+HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);

+HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);

+/**

+  * @}

+  */

+

+/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions

+  *  @brief   TIM PWM functions

+  * @{

+  */

+/* Timer PWM functions ********************************************************/

+HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);

+HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);

+void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);

+void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);

+/* Blocking mode: Polling */

+HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);

+HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);

+/* Non-Blocking mode: Interrupt */

+HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);

+HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);

+/* Non-Blocking mode: DMA */

+HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);

+HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);

+/**

+  * @}

+  */

+

+/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions

+  *  @brief   TIM Input Capture functions

+  * @{

+  */

+/* Timer Input Capture functions **********************************************/

+HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);

+HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);

+void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);

+void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);

+/* Blocking mode: Polling */

+HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);

+HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);

+/* Non-Blocking mode: Interrupt */

+HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);

+HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);

+/* Non-Blocking mode: DMA */

+HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);

+HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);

+/**

+  * @}

+  */

+

+/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions

+  *  @brief   TIM One Pulse functions

+  * @{

+  */

+/* Timer One Pulse functions **************************************************/

+HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);

+HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);

+void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);

+void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);

+/* Blocking mode: Polling */

+HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);

+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);

+/* Non-Blocking mode: Interrupt */

+HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);

+HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);

+/**

+  * @}

+  */

+

+/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions

+  *  @brief   TIM Encoder functions

+  * @{

+  */

+/* Timer Encoder functions ****************************************************/

+HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef *sConfig);

+HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);

+void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);

+void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);

+/* Blocking mode: Polling */

+HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);

+HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);

+/* Non-Blocking mode: Interrupt */

+HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);

+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);

+/* Non-Blocking mode: DMA */

+HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,

+                                            uint32_t *pData2, uint16_t Length);

+HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);

+/**

+  * @}

+  */

+

+/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management

+  *  @brief   IRQ handler management

+  * @{

+  */

+/* Interrupt Handler functions  ***********************************************/

+void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions

+  *  @brief   Peripheral Control functions

+  * @{

+  */

+/* Control functions  *********************************************************/

+HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);

+HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);

+HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);

+HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,

+                                                 uint32_t OutputChannel,  uint32_t InputChannel);

+HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,

+                                           uint32_t Channel);

+HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);

+HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);

+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);

+HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);

+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,

+                                              uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);

+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,

+                                                   uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength,

+                                                   uint32_t DataLength);

+HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);

+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,

+                                             uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength);

+HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,

+                                                  uint32_t BurstRequestSrc, uint32_t  *BurstBuffer, uint32_t  BurstLength,

+                                                  uint32_t  DataLength);

+HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);

+HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);

+uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions

+  *  @brief   TIM Callbacks functions

+  * @{

+  */

+/* Callback in non blocking modes (Interrupt and DMA) *************************/

+void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);

+void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim);

+void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);

+void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);

+void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim);

+void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);

+void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim);

+void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);

+void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim);

+void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);

+

+/* Callbacks Register/UnRegister functions  ***********************************/

+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)

+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,

+                                           pTIM_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);

+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions

+  *  @brief  Peripheral State functions

+  * @{

+  */

+/* Peripheral State functions  ************************************************/

+HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);

+HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);

+HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);

+HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);

+HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);

+HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+/* End of exported functions -------------------------------------------------*/

+

+/* Private functions----------------------------------------------------------*/

+/** @defgroup TIM_Private_Functions TIM Private Functions

+  * @{

+  */

+void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);

+void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);

+void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);

+void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,

+                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);

+

+void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);

+void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma);

+void TIM_DMAError(DMA_HandleTypeDef *hdma);

+void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);

+void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma);

+void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState);

+

+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)

+void TIM_ResetCallback(TIM_HandleTypeDef *htim);

+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+/* End of private functions --------------------------------------------------*/

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_TIM_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_tim_ex.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_tim_ex.h
new file mode 100644
index 0000000000..0a7ef48a78
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_tim_ex.h
@@ -0,0 +1,529 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_tim_ex.h

+  * @author  MCD Application Team

+  * @brief   Header file of TIM HAL Extended module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_TIM_EX_H

+#define STM32H7xx_HAL_TIM_EX_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup TIMEx

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types

+  * @{

+  */

+

+/**

+  * @brief  TIM Hall sensor Configuration Structure definition

+  */

+

+typedef struct

+{

+  uint32_t IC1Polarity;         /*!< Specifies the active edge of the input signal.

+                                     This parameter can be a value of @ref TIM_Input_Capture_Polarity */

+

+  uint32_t IC1Prescaler;        /*!< Specifies the Input Capture Prescaler.

+                                     This parameter can be a value of @ref TIM_Input_Capture_Prescaler */

+

+  uint32_t IC1Filter;           /*!< Specifies the input capture filter.

+                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */

+

+  uint32_t Commutation_Delay;   /*!< Specifies the pulse value to be loaded into the Capture Compare Register.

+                                     This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */

+} TIM_HallSensor_InitTypeDef;

+#if defined(TIM_BREAK_INPUT_SUPPORT)

+

+/**

+  * @brief  TIM Break/Break2 input configuration

+  */

+typedef struct

+{

+  uint32_t Source;         /*!< Specifies the source of the timer break input.

+                                This parameter can be a value of @ref TIMEx_Break_Input_Source */

+  uint32_t Enable;         /*!< Specifies whether or not the break input source is enabled.

+                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */

+  uint32_t Polarity;       /*!< Specifies the break input source polarity.

+                                This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity

+                                Not relevant when analog watchdog output of the DFSDM1 used as break input source */

+}

+TIMEx_BreakInputConfigTypeDef;

+

+#endif /* TIM_BREAK_INPUT_SUPPORT */

+/**

+  * @}

+  */

+/* End of exported types -----------------------------------------------------*/

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants

+  * @{

+  */

+

+/** @defgroup TIMEx_Remap TIM Extended Remapping

+  * @{

+  */

+#define TIM_TIM1_ETR_GPIO        0x00000000U                                                 /* !< TIM1_ETR is connected to GPIO */

+#define TIM_TIM1_ETR_COMP1       TIM1_AF1_ETRSEL_0                                           /* !< TIM1_ETR is connected to COMP1 OUT */

+#define TIM_TIM1_ETR_COMP2       TIM1_AF1_ETRSEL_1                                           /* !< TIM1_ETR is connected to COMP2 OUT */

+#define TIM_TIM1_ETR_ADC1_AWD1   (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /* !< TIM1_ETR is connected to ADC1 AWD1 */

+#define TIM_TIM1_ETR_ADC1_AWD2   (TIM1_AF1_ETRSEL_2)                                         /* !< TIM1_ETR is connected to ADC1 AWD2 */

+#define TIM_TIM1_ETR_ADC1_AWD3   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /* !< TIM1_ETR is connected to ADC1 AWD3 */

+#define TIM_TIM1_ETR_ADC3_AWD1   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /* !< TIM1_ETR is connected to ADC3 AWD1 */

+#define TIM_TIM1_ETR_ADC3_AWD2   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */

+#define TIM_TIM1_ETR_ADC3_AWD3   TIM1_AF1_ETRSEL_3                                           /* !< TIM1_ETR is connected to ADC3 AWD3 */

+

+#define TIM_TIM8_ETR_GPIO        0x00000000U                                                 /* !< TIM8_ETR is connected to GPIO */

+#define TIM_TIM8_ETR_COMP1       TIM8_AF1_ETRSEL_0                                           /* !< TIM8_ETR is connected to COMP1 OUT */

+#define TIM_TIM8_ETR_COMP2       TIM8_AF1_ETRSEL_1                                           /* !< TIM8_ETR is connected to COMP2 OUT */

+#define TIM_TIM8_ETR_ADC2_AWD1   (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                     /* !< TIM8_ETR is connected to ADC2 AWD1 */

+#define TIM_TIM8_ETR_ADC2_AWD2   (TIM8_AF1_ETRSEL_2)                                         /* !< TIM8_ETR is connected to ADC2 AWD2 */

+#define TIM_TIM8_ETR_ADC2_AWD3   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)                     /* !< TIM8_ETR is connected to ADC2 AWD3 */

+#define TIM_TIM8_ETR_ADC3_AWD1   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1)                     /* !< TIM8_ETR is connected to ADC3 AWD1 */

+#define TIM_TIM8_ETR_ADC3_AWD2   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */

+#define TIM_TIM8_ETR_ADC3_AWD3   TIM8_AF1_ETRSEL_3                                           /* !< TIM8_ETR is connected to ADC3 AWD3 */

+

+#define TIM_TIM2_ETR_GPIO        0x00000000U                             /* !< TIM2_ETR is connected to GPIO */

+#define TIM_TIM2_ETR_COMP1       (TIM2_AF1_ETRSEL_0)                     /* !< TIM2_ETR is connected to COMP1 OUT */

+#define TIM_TIM2_ETR_COMP2       (TIM2_AF1_ETRSEL_1)                     /* !< TIM2_ETR is connected to COMP2 OUT */

+#define TIM_TIM2_ETR_RCC_LSE     (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to RCC LSE */

+#define TIM_TIM2_ETR_SAI1_FSA    TIM2_AF1_ETRSEL_2                       /* !< TIM2_ETR is connected to SAI1 FS_A */

+#define TIM_TIM2_ETR_SAI1_FSB    (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0) /* !< TIM2_ETR is connected to SAI1 FS_B */

+

+#define TIM_TIM3_ETR_GPIO        0x00000000U          /* !< TIM3_ETR is connected to GPIO */

+#define TIM_TIM3_ETR_COMP1       TIM3_AF1_ETRSEL_0    /* !< TIM3_ETR is connected to COMP1 OUT */

+

+#define TIM_TIM5_ETR_GPIO        0x00000000U          /* !< TIM5_ETR is connected to GPIO */

+#define TIM_TIM5_ETR_SAI2_FSA    TIM5_AF1_ETRSEL_0    /* !< TIM5_ETR is connected to SAI2 FS_A */

+#define TIM_TIM5_ETR_SAI2_FSB    TIM5_AF1_ETRSEL_1    /* !< TIM5_ETR is connected to SAI2 FS_B */

+#define TIM_TIM5_ETR_SAI4_FSA    TIM5_AF1_ETRSEL_0    /* !< TIM5_ETR is connected to SAI4 FS_A */

+#define TIM_TIM5_ETR_SAI4_FSB    TIM5_AF1_ETRSEL_1    /* !< TIM5_ETR is connected to SAI4 FS_B */

+

+#define TIM_TIM23_ETR_GPIO       0x00000000U          /* !< TIM23_ETR is connected to GPIO */

+#define TIM_TIM23_ETR_COMP1      (TIM2_AF1_ETRSEL_0)  /* !< TIM23_ETR is connected to COMP1 OUT */

+#define TIM_TIM23_ETR_COMP2      (TIM2_AF1_ETRSEL_1)  /* !< TIM23_ETR is connected to COMP2 OUT */

+

+#define TIM_TIM24_ETR_GPIO        0x00000000U                                /* !< TIM24_ETR is connected to GPIO */

+#define TIM_TIM24_ETR_SAI4_FSA    TIM5_AF1_ETRSEL_0                          /* !< TIM24_ETR is connected to SAI4 FS_A */

+#define TIM_TIM24_ETR_SAI4_FSB    TIM5_AF1_ETRSEL_1                          /* !< TIM24_ETR is connected to SAI4 FS_B */

+#define TIM_TIM24_ETR_SAI1_FSA    (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)    /* !< TIM24_ETR is connected to SAI1 FS_A */

+#define TIM_TIM24_ETR_SAI1_FSB    TIM2_AF1_ETRSEL_2                          /* !< TIM24_ETR is connected to SAI1 FS_B */

+/**

+  * @}

+  */

+#if defined(TIM_BREAK_INPUT_SUPPORT)

+

+/** @defgroup TIMEx_Break_Input TIM Extended Break input

+  * @{

+  */

+#define TIM_BREAKINPUT_BRK     0x00000001U                                      /* !< Timer break input  */

+#define TIM_BREAKINPUT_BRK2    0x00000002U                                      /* !< Timer break2 input */

+/**

+  * @}

+  */

+

+/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source

+  * @{

+  */

+#define TIM_BREAKINPUTSOURCE_BKIN     0x00000001U                               /* !< An external source (GPIO) is connected to the BKIN pin  */

+#define TIM_BREAKINPUTSOURCE_COMP1    0x00000002U                               /* !< The COMP1 output is connected to the break input */

+#define TIM_BREAKINPUTSOURCE_COMP2    0x00000004U                               /* !< The COMP2 output is connected to the break input */

+#define TIM_BREAKINPUTSOURCE_DFSDM1   0x00000008U                               /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */

+/**

+  * @}

+  */

+

+/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling

+  * @{

+  */

+#define TIM_BREAKINPUTSOURCE_DISABLE     0x00000000U                            /* !< Break input source is disabled */

+#define TIM_BREAKINPUTSOURCE_ENABLE      0x00000001U                            /* !< Break input source is enabled */

+/**

+  * @}

+  */

+

+/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity

+  * @{

+  */

+#define TIM_BREAKINPUTSOURCE_POLARITY_LOW     0x00000001U                       /* !< Break input source is active low */

+#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH    0x00000000U                       /* !< Break input source is active_high */

+/**

+  * @}

+  */

+#endif /* TIM_BREAK_INPUT_SUPPORT */

+

+/** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection

+  * @{

+  */

+#define TIM_TIM1_TI1_GPIO                          0x00000000U                               /* !< TIM1_TI1 is connected to GPIO */

+#define TIM_TIM1_TI1_COMP1                         TIM_TISEL_TI1SEL_0                        /* !< TIM1_TI1 is connected to COMP1 OUT */

+

+#define TIM_TIM8_TI1_GPIO                          0x00000000U                               /* !< TIM8_TI1 is connected to GPIO */

+#define TIM_TIM8_TI1_COMP2                         TIM_TISEL_TI1SEL_0                        /* !< TIM8_TI1 is connected to COMP2 OUT */

+

+#define TIM_TIM2_TI4_GPIO                          0x00000000U                               /* !< TIM2_TI4 is connected to GPIO */

+#define TIM_TIM2_TI4_COMP1                         TIM_TISEL_TI4SEL_0                        /* !< TIM2_TI4 is connected to COMP1 OUT */

+#define TIM_TIM2_TI4_COMP2                         TIM_TISEL_TI4SEL_1                        /* !< TIM2_TI4 is connected to COMP2 OUT */

+#define TIM_TIM2_TI4_COMP1_COMP2                   (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM2_TI4 is connected to COMP2 OUT OR COMP2 OUT */

+

+#define TIM_TIM3_TI1_GPIO                          0x00000000U                               /* !< TIM3_TI1 is connected to GPIO */

+#define TIM_TIM3_TI1_COMP1                         TIM_TISEL_TI1SEL_0                        /* !< TIM3_TI1 is connected to COMP1 OUT */

+#define TIM_TIM3_TI1_COMP2                         TIM_TISEL_TI1SEL_1                        /* !< TIM3_TI1 is connected to COMP2 OUT */

+#define TIM_TIM3_TI1_COMP1_COMP2                   (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3_TI1 is connected to COMP1 OUT or COMP2 OUT */

+

+#define TIM_TIM5_TI1_GPIO                          0x00000000U                               /* !< TIM5_TI1 is connected to GPIO */

+#define TIM_TIM5_TI1_CAN_TMP                       TIM_TISEL_TI1SEL_0                        /* !< TIM5_TI1 is connected to CAN TMP */

+#define TIM_TIM5_TI1_CAN_RTP                       TIM_TISEL_TI1SEL_1                        /* !< TIM5_TI1 is connected to CAN RTP */

+

+#define TIM_TIM12_TI1_GPIO                         0x00000000U                               /* !< TIM12 TI1 is connected to GPIO */

+#define TIM_TIM12_TI1_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /* !< TIM12 TI1 is connected to SPDIF FS */

+

+#define TIM_TIM15_TI1_GPIO                         0x00000000U                               /* !< TIM15_TI1 is connected to GPIO */

+#define TIM_TIM15_TI1_TIM2_CH1                     TIM_TISEL_TI1SEL_0                        /* !< TIM15_TI1 is connected to TIM2 CH1 */

+#define TIM_TIM15_TI1_TIM3_CH1                     TIM_TISEL_TI1SEL_1                        /* !< TIM15_TI1 is connected to TIM3 CH1 */

+#define TIM_TIM15_TI1_TIM4_CH1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to TIM4 CH1 */

+#define TIM_TIM15_TI1_RCC_LSE                      (TIM_TISEL_TI1SEL_2)                      /* !< TIM15_TI1 is connected to RCC LSE  */

+#define TIM_TIM15_TI1_RCC_CSI                      (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM15_TI1 is connected to RCC CSI  */

+#define TIM_TIM15_TI1_RCC_MCO2                     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM15_TI1 is connected to RCC MCO2 */

+

+#define TIM_TIM15_TI2_GPIO                         0x00000000U                               /* !< TIM15_TI2 is connected to GPIO */

+#define TIM_TIM15_TI2_TIM2_CH2                     (TIM_TISEL_TI2SEL_0)                      /* !< TIM15_TI2 is connected to TIM2 CH2 */

+#define TIM_TIM15_TI2_TIM3_CH2                     (TIM_TISEL_TI2SEL_1)                      /* !< TIM15_TI2 is connected to TIM3 CH2 */

+#define TIM_TIM15_TI2_TIM4_CH2                     (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /* !< TIM15_TI2 is connected to TIM4 CH2 */

+

+#define TIM_TIM16_TI1_GPIO                         0x00000000U                               /* !< TIM16 TI1 is connected to GPIO */

+#define TIM_TIM16_TI1_RCC_LSI                      TIM_TISEL_TI1SEL_0                        /* !< TIM16 TI1 is connected to RCC LSI */

+#define TIM_TIM16_TI1_RCC_LSE                      TIM_TISEL_TI1SEL_1                        /* !< TIM16 TI1 is connected to RCC LSE */

+#define TIM_TIM16_TI1_WKUP_IT                      (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 TI1 is connected to WKUP_IT */

+

+#define TIM_TIM17_TI1_GPIO                         0x00000000U                               /* !< TIM17 TI1 is connected to GPIO */

+#define TIM_TIM17_TI1_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /* !< TIM17 TI1 is connected to SPDIF FS */

+#define TIM_TIM17_TI1_RCC_HSE1MHZ                  TIM_TISEL_TI1SEL_1                        /* !< TIM17 TI1 is connected to RCC HSE 1Mhz */

+#define TIM_TIM17_TI1_RCC_MCO1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 TI1 is connected to RCC MCO1 */

+

+#define TIM_TIM23_TI4_GPIO                         0x00000000U                               /* !< TIM23_TI4 is connected to GPIO */

+#define TIM_TIM23_TI4_COMP1                        TIM_TISEL_TI4SEL_0                        /* !< TIM23_TI4 is connected to COMP1 OUT */

+#define TIM_TIM23_TI4_COMP2                        TIM_TISEL_TI4SEL_1                        /* !< TIM23_TI4 is connected to COMP2 OUT */

+#define TIM_TIM23_TI4_COMP1_COMP2                  (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM23_TI4 is connected to COMP1 OUT or COMP2 OUT */

+

+#define TIM_TIM24_TI1_GPIO                         0x00000000U                               /* !< TIM24_TI1 is connected to GPIO */

+#define TIM_TIM24_TI1_CAN_TMP                      TIM_TISEL_TI1SEL_0                        /* !< TIM24_TI1 is connected to CAN TMP  */

+#define TIM_TIM24_TI1_CAN_RTP                      TIM_TISEL_TI1SEL_1                        /* !< TIM24_TI1 is connected to CAN RTP  */

+#define TIM_TIM24_TI1_CAN_SOC                      (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24_TI1 is connected to CAN SOC */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+/* End of exported constants -------------------------------------------------*/

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros

+  * @{

+  */

+

+/**

+  * @}

+  */

+/* End of exported macro -----------------------------------------------------*/

+

+/* Private macro -------------------------------------------------------------*/

+/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros

+  * @{

+  */

+#define IS_TIM_BREAKINPUT(__BREAKINPUT__)  (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK)  || \

+                                            ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))

+

+#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__)  (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN)  || \

+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \

+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \

+                                              ((__SOURCE__) == TIM_BREAKINPUTSOURCE_DFSDM1))

+

+#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__)  (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE)  || \

+                                                   ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))

+

+#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__)  (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW)  || \

+                                                         ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))

+

+#define IS_TIM_TISEL(__TISEL__)  (((__TISEL__) == TIM_TIM1_TI1_GPIO)         ||\

+                                  ((__TISEL__) == TIM_TIM1_TI1_COMP1)        ||\

+                                  ((__TISEL__) == TIM_TIM8_TI1_GPIO)         ||\

+                                  ((__TISEL__) == TIM_TIM8_TI1_COMP2)        ||\

+                                  ((__TISEL__) == TIM_TIM2_TI4_GPIO)         ||\

+                                  ((__TISEL__) == TIM_TIM2_TI4_COMP1)        ||\

+                                  ((__TISEL__) == TIM_TIM2_TI4_COMP2)        ||\

+                                  ((__TISEL__) == TIM_TIM2_TI4_COMP1_COMP2)  ||\

+                                  ((__TISEL__) == TIM_TIM3_TI1_GPIO)         ||\

+                                  ((__TISEL__) == TIM_TIM3_TI1_COMP1)        ||\

+                                  ((__TISEL__) == TIM_TIM3_TI1_COMP2)        ||\

+                                  ((__TISEL__) == TIM_TIM3_TI1_COMP1_COMP2)  ||\

+                                  ((__TISEL__) == TIM_TIM5_TI1_GPIO)         ||\

+                                  ((__TISEL__) == TIM_TIM5_TI1_CAN_TMP)      ||\

+                                  ((__TISEL__) == TIM_TIM5_TI1_CAN_RTP)      ||\

+                                  ((__TISEL__) == TIM_TIM12_TI1_SPDIF_FS)    ||\

+                                  ((__TISEL__) == TIM_TIM12_TI1_GPIO)        ||\

+                                  ((__TISEL__) == TIM_TIM15_TI1_GPIO)        ||\

+                                  ((__TISEL__) == TIM_TIM15_TI1_TIM2_CH1)    ||\

+                                  ((__TISEL__) == TIM_TIM15_TI1_TIM3_CH1)    ||\

+                                  ((__TISEL__) == TIM_TIM15_TI1_TIM4_CH1)    ||\

+                                  ((__TISEL__) == TIM_TIM15_TI1_RCC_LSE)     ||\

+                                  ((__TISEL__) == TIM_TIM15_TI1_RCC_CSI)     ||\

+                                  ((__TISEL__) == TIM_TIM15_TI1_RCC_MCO2)    ||\

+                                  ((__TISEL__) == TIM_TIM15_TI2_GPIO)        ||\

+                                  ((__TISEL__) == TIM_TIM15_TI2_TIM2_CH2)    ||\

+                                  ((__TISEL__) == TIM_TIM15_TI2_TIM3_CH2)    ||\

+                                  ((__TISEL__) == TIM_TIM15_TI2_TIM4_CH2)    ||\

+                                  ((__TISEL__) == TIM_TIM16_TI1_GPIO)        ||\

+                                  ((__TISEL__) == TIM_TIM16_TI1_RCC_LSI)     ||\

+                                  ((__TISEL__) == TIM_TIM16_TI1_RCC_LSE)     ||\

+                                  ((__TISEL__) == TIM_TIM16_TI1_WKUP_IT)     ||\

+                                  ((__TISEL__) == TIM_TIM17_TI1_GPIO)        ||\

+                                  ((__TISEL__) == TIM_TIM17_TI1_SPDIF_FS)    ||\

+                                  ((__TISEL__) == TIM_TIM17_TI1_RCC_HSE1MHZ) ||\

+                                  ((__TISEL__) == TIM_TIM17_TI1_RCC_MCO1)    ||\

+                                  ((__TISEL__) == TIM_TIM23_TI4_GPIO)        ||\

+                                  ((__TISEL__) == TIM_TIM23_TI4_COMP1)       ||\

+                                  ((__TISEL__) == TIM_TIM23_TI4_COMP2)       ||\

+                                  ((__TISEL__) == TIM_TIM23_TI4_COMP1_COMP2) ||\

+                                  ((__TISEL__) == TIM_TIM24_TI1_GPIO)        ||\

+                                  ((__TISEL__) == TIM_TIM24_TI1_CAN_TMP)     ||\

+                                  ((__TISEL__) == TIM_TIM24_TI1_CAN_RTP)     ||\

+                                  ((__TISEL__) == TIM_TIM24_TI1_CAN_SOC))

+

+#define IS_TIM_REMAP(__RREMAP__)     (((__RREMAP__) == TIM_TIM1_ETR_GPIO)      ||\

+                                      ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD1) ||\

+                                      ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD2) ||\

+                                      ((__RREMAP__) == TIM_TIM1_ETR_ADC1_AWD3) ||\

+                                      ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD1) ||\

+                                      ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD2) ||\

+                                      ((__RREMAP__) == TIM_TIM1_ETR_ADC3_AWD3) ||\

+                                      ((__RREMAP__) == TIM_TIM1_ETR_COMP1)     ||\

+                                      ((__RREMAP__) == TIM_TIM1_ETR_COMP2)     ||\

+                                      ((__RREMAP__) == TIM_TIM8_ETR_GPIO)      ||\

+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD1) ||\

+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD2) ||\

+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC2_AWD3) ||\

+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD1) ||\

+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD2) ||\

+                                      ((__RREMAP__) == TIM_TIM8_ETR_ADC3_AWD3) ||\

+                                      ((__RREMAP__) == TIM_TIM8_ETR_COMP1)     ||\

+                                      ((__RREMAP__) == TIM_TIM8_ETR_COMP2)     ||\

+                                      ((__RREMAP__) == TIM_TIM2_ETR_GPIO)      ||\

+                                      ((__RREMAP__) == TIM_TIM2_ETR_COMP1)     ||\

+                                      ((__RREMAP__) == TIM_TIM2_ETR_COMP2)     ||\

+                                      ((__RREMAP__) == TIM_TIM2_ETR_RCC_LSE)   ||\

+                                      ((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSA)  ||\

+                                      ((__RREMAP__) == TIM_TIM2_ETR_SAI1_FSB)  ||\

+                                      ((__RREMAP__) == TIM_TIM3_ETR_GPIO)      ||\

+                                      ((__RREMAP__) == TIM_TIM3_ETR_COMP1)     ||\

+                                      ((__RREMAP__) == TIM_TIM5_ETR_GPIO)      ||\

+                                      ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSA)  ||\

+                                      ((__RREMAP__) == TIM_TIM5_ETR_SAI2_FSB)  ||\

+                                      ((__RREMAP__) == TIM_TIM23_ETR_GPIO)     ||\

+                                      ((__RREMAP__) == TIM_TIM23_ETR_COMP1)    ||\

+                                      ((__RREMAP__) == TIM_TIM23_ETR_COMP2)    ||\

+                                      ((__RREMAP__) == TIM_TIM24_ETR_GPIO)     ||\

+                                      ((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSA) ||\

+                                      ((__RREMAP__) == TIM_TIM24_ETR_SAI4_FSB) ||\

+                                      ((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSA) ||\

+                                      ((__RREMAP__) == TIM_TIM24_ETR_SAI1_FSB))

+

+/**

+  * @}

+  */

+/* End of private macro ------------------------------------------------------*/

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions

+  * @{

+  */

+

+/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions

+  *  @brief    Timer Hall Sensor functions

+  * @{

+  */

+/*  Timer Hall Sensor functions  **********************************************/

+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);

+HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);

+

+void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim);

+void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim);

+

+/* Blocking mode: Polling */

+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim);

+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim);

+/* Non-Blocking mode: Interrupt */

+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim);

+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim);

+/* Non-Blocking mode: DMA */

+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);

+HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);

+/**

+  * @}

+  */

+

+/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions

+  *  @brief   Timer Complementary Output Compare functions

+  * @{

+  */

+/*  Timer Complementary Output Compare functions  *****************************/

+/* Blocking mode: Polling */

+HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);

+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);

+

+/* Non-Blocking mode: Interrupt */

+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);

+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);

+

+/* Non-Blocking mode: DMA */

+HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);

+HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);

+/**

+  * @}

+  */

+

+/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions

+  *  @brief    Timer Complementary PWM functions

+  * @{

+  */

+/*  Timer Complementary PWM functions  ****************************************/

+/* Blocking mode: Polling */

+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);

+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);

+

+/* Non-Blocking mode: Interrupt */

+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);

+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);

+/* Non-Blocking mode: DMA */

+HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);

+HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);

+/**

+  * @}

+  */

+

+/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions

+  *  @brief    Timer Complementary One Pulse functions

+  * @{

+  */

+/*  Timer Complementary One Pulse functions  **********************************/

+/* Blocking mode: Polling */

+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);

+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);

+

+/* Non-Blocking mode: Interrupt */

+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);

+HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);

+/**

+  * @}

+  */

+

+/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions

+  *  @brief    Peripheral Control functions

+  * @{

+  */

+/* Extended Control functions  ************************************************/

+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,

+                                              uint32_t  CommutationSource);

+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,

+                                                 uint32_t  CommutationSource);

+HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t  InputTrigger,

+                                                  uint32_t  CommutationSource);

+HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,

+                                                        TIM_MasterConfigTypeDef *sMasterConfig);

+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,

+                                                TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);

+#if defined(TIM_BREAK_INPUT_SUPPORT)

+HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,

+                                             TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);

+#endif /* TIM_BREAK_INPUT_SUPPORT */

+HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);

+HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);

+HAL_StatusTypeDef  HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel);

+/**

+  * @}

+  */

+

+/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions

+  * @brief    Extended Callbacks functions

+  * @{

+  */

+/* Extended Callback **********************************************************/

+void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim);

+void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim);

+void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim);

+void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim);

+/**

+  * @}

+  */

+

+/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions

+  * @brief    Extended Peripheral State functions

+  * @{

+  */

+/* Extended Peripheral State functions  ***************************************/

+HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+/* End of exported functions -------------------------------------------------*/

+

+/* Private functions----------------------------------------------------------*/

+/** @addtogroup TIMEx_Private_Functions TIMEx Private Functions

+  * @{

+  */

+void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);

+void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma);

+/**

+  * @}

+  */

+/* End of private functions --------------------------------------------------*/

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+

+#endif /* STM32H7xx_HAL_TIM_EX_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_uart.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_uart.h
new file mode 100644
index 0000000000..48eb8db373
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_uart.h
@@ -0,0 +1,1649 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_uart.h

+  * @author  MCD Application Team

+  * @brief   Header file of UART HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_UART_H

+#define STM32H7xx_HAL_UART_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup UART

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup UART_Exported_Types UART Exported Types

+  * @{

+  */

+

+/**

+  * @brief UART Init Structure definition

+  */

+typedef struct

+{

+  uint32_t BaudRate;                  /*!< This member configures the UART communication baud rate.

+                                           The baud rate register is computed using the following formula:

+                                           LPUART:

+                                           =======

+                                              Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate)))

+                                           where lpuart_ker_ck_pres is the UART input clock divided by a prescaler

+                                           UART:

+                                           =====

+                                           - If oversampling is 16 or in LIN mode,

+                                              Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate)))

+                                           - If oversampling is 8,

+                                              Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[15:4]

+                                              Baud Rate Register[3] =  0

+                                              Baud Rate Register[2:0] =  (((2 * uart_ker_ckpres) / ((huart->Init.BaudRate)))[3:0]) >> 1

+                                           where uart_ker_ck_pres is the UART input clock divided by a prescaler */

+

+  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.

+                                           This parameter can be a value of @ref UARTEx_Word_Length. */

+

+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.

+                                           This parameter can be a value of @ref UART_Stop_Bits. */

+

+  uint32_t Parity;                    /*!< Specifies the parity mode.

+                                           This parameter can be a value of @ref UART_Parity

+                                           @note When parity is enabled, the computed parity is inserted

+                                                 at the MSB position of the transmitted data (9th bit when

+                                                 the word length is set to 9 data bits; 8th bit when the

+                                                 word length is set to 8 data bits). */

+

+  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.

+                                           This parameter can be a value of @ref UART_Mode. */

+

+  uint32_t HwFlowCtl;                 /*!< Specifies whether the hardware flow control mode is enabled

+                                           or disabled.

+                                           This parameter can be a value of @ref UART_Hardware_Flow_Control. */

+

+  uint32_t OverSampling;              /*!< Specifies whether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to f_PCLK/8).

+                                           This parameter can be a value of @ref UART_Over_Sampling. */

+

+  uint32_t OneBitSampling;            /*!< Specifies whether a single sample or three samples' majority vote is selected.

+                                           Selecting the single sample method increases the receiver tolerance to clock

+                                           deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */

+

+  uint32_t ClockPrescaler;            /*!< Specifies the prescaler value used to divide the UART clock source.

+                                           This parameter can be a value of @ref UART_ClockPrescaler. */

+

+} UART_InitTypeDef;

+

+/**

+  * @brief  UART Advanced Features initialization structure definition

+  */

+typedef struct

+{

+  uint32_t AdvFeatureInit;        /*!< Specifies which advanced UART features is initialized. Several

+                                       Advanced Features may be initialized at the same time .

+                                       This parameter can be a value of @ref UART_Advanced_Features_Initialization_Type. */

+

+  uint32_t TxPinLevelInvert;      /*!< Specifies whether the TX pin active level is inverted.

+                                       This parameter can be a value of @ref UART_Tx_Inv. */

+

+  uint32_t RxPinLevelInvert;      /*!< Specifies whether the RX pin active level is inverted.

+                                       This parameter can be a value of @ref UART_Rx_Inv. */

+

+  uint32_t DataInvert;            /*!< Specifies whether data are inverted (positive/direct logic

+                                       vs negative/inverted logic).

+                                       This parameter can be a value of @ref UART_Data_Inv. */

+

+  uint32_t Swap;                  /*!< Specifies whether TX and RX pins are swapped.

+                                       This parameter can be a value of @ref UART_Rx_Tx_Swap. */

+

+  uint32_t OverrunDisable;        /*!< Specifies whether the reception overrun detection is disabled.

+                                       This parameter can be a value of @ref UART_Overrun_Disable. */

+

+  uint32_t DMADisableonRxError;   /*!< Specifies whether the DMA is disabled in case of reception error.

+                                       This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */

+

+  uint32_t AutoBaudRateEnable;    /*!< Specifies whether auto Baud rate detection is enabled.

+                                       This parameter can be a value of @ref UART_AutoBaudRate_Enable. */

+

+  uint32_t AutoBaudRateMode;      /*!< If auto Baud rate detection is enabled, specifies how the rate

+                                       detection is carried out.

+                                       This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */

+

+  uint32_t MSBFirst;              /*!< Specifies whether MSB is sent first on UART line.

+                                       This parameter can be a value of @ref UART_MSB_First. */

+} UART_AdvFeatureInitTypeDef;

+

+/**

+  * @brief HAL UART State definition

+  * @note  HAL UART State value is a combination of 2 different substates: gState and RxState (see @ref UART_State_Definition).

+  *        - gState contains UART state information related to global Handle management

+  *          and also information related to Tx operations.

+  *          gState value coding follow below described bitmap :

+  *          b7-b6  Error information

+  *             00 : No Error

+  *             01 : (Not Used)

+  *             10 : Timeout

+  *             11 : Error

+  *          b5     Peripheral initialization status

+  *             0  : Reset (Peripheral not initialized)

+  *             1  : Init done (Peripheral not initialized. HAL UART Init function already called)

+  *          b4-b3  (not used)

+  *             xx : Should be set to 00

+  *          b2     Intrinsic process state

+  *             0  : Ready

+  *             1  : Busy (Peripheral busy with some configuration or internal operations)

+  *          b1     (not used)

+  *             x  : Should be set to 0

+  *          b0     Tx state

+  *             0  : Ready (no Tx operation ongoing)

+  *             1  : Busy (Tx operation ongoing)

+  *        - RxState contains information related to Rx operations.

+  *          RxState value coding follow below described bitmap :

+  *          b7-b6  (not used)

+  *             xx : Should be set to 00

+  *          b5     Peripheral initialization status

+  *             0  : Reset (Peripheral not initialized)

+  *             1  : Init done (Peripheral not initialized)

+  *          b4-b2  (not used)

+  *            xxx : Should be set to 000

+  *          b1     Rx state

+  *             0  : Ready (no Rx operation ongoing)

+  *             1  : Busy (Rx operation ongoing)

+  *          b0     (not used)

+  *             x  : Should be set to 0.

+  */

+typedef uint32_t HAL_UART_StateTypeDef;

+

+/**

+  * @brief UART clock sources definition

+  */

+typedef enum

+{

+  UART_CLOCKSOURCE_D2PCLK1    = 0x00U,    /*!< Domain2 PCLK1 clock source */

+  UART_CLOCKSOURCE_D2PCLK2    = 0x01U,    /*!< Domain2 PCLK2 clock source */

+  UART_CLOCKSOURCE_D3PCLK1    = 0x02U,    /*!< Domain3 PCLK1 clock source */

+  UART_CLOCKSOURCE_PLL2       = 0x04U,    /*!< PLL2Q clock source         */

+  UART_CLOCKSOURCE_PLL3       = 0x08U,    /*!< PLL3Q clock source         */

+  UART_CLOCKSOURCE_HSI        = 0x10U,    /*!< HSI clock source           */

+  UART_CLOCKSOURCE_CSI        = 0x20U,    /*!< CSI clock source           */

+  UART_CLOCKSOURCE_LSE        = 0x40U,    /*!< LSE clock source           */

+  UART_CLOCKSOURCE_UNDEFINED  = 0x80U     /*!< Undefined clock source     */

+} UART_ClockSourceTypeDef;

+

+/**

+  * @brief  UART handle Structure definition

+  */

+typedef struct __UART_HandleTypeDef

+{

+  USART_TypeDef            *Instance;                /*!< UART registers base address        */

+

+  UART_InitTypeDef         Init;                     /*!< UART communication parameters      */

+

+  UART_AdvFeatureInitTypeDef AdvancedInit;           /*!< UART Advanced Features initialization parameters */

+

+  uint8_t                  *pTxBuffPtr;              /*!< Pointer to UART Tx transfer Buffer */

+

+  uint16_t                 TxXferSize;               /*!< UART Tx Transfer size              */

+

+  __IO uint16_t            TxXferCount;              /*!< UART Tx Transfer Counter           */

+

+  uint8_t                  *pRxBuffPtr;              /*!< Pointer to UART Rx transfer Buffer */

+

+  uint16_t                 RxXferSize;               /*!< UART Rx Transfer size              */

+

+  __IO uint16_t            RxXferCount;              /*!< UART Rx Transfer Counter           */

+

+  uint16_t                 Mask;                     /*!< UART Rx RDR register mask          */

+

+  uint32_t                 FifoMode;                 /*!< Specifies if the FIFO mode is being used.

+                                                          This parameter can be a value of @ref UARTEx_FIFO_mode. */

+

+  uint16_t                 NbRxDataToProcess;        /*!< Number of data to process during RX ISR execution */

+

+  uint16_t                 NbTxDataToProcess;        /*!< Number of data to process during TX ISR execution */

+

+  void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */

+

+  void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */

+

+  DMA_HandleTypeDef        *hdmatx;                  /*!< UART Tx DMA Handle parameters      */

+

+  DMA_HandleTypeDef        *hdmarx;                  /*!< UART Rx DMA Handle parameters      */

+

+  HAL_LockTypeDef           Lock;                    /*!< Locking object                     */

+

+  __IO HAL_UART_StateTypeDef    gState;              /*!< UART state information related to global Handle management

+                                                          and also related to Tx operations.

+                                                          This parameter can be a value of @ref HAL_UART_StateTypeDef */

+

+  __IO HAL_UART_StateTypeDef    RxState;             /*!< UART state information related to Rx operations.

+                                                          This parameter can be a value of @ref HAL_UART_StateTypeDef */

+

+  __IO uint32_t                 ErrorCode;           /*!< UART Error code                    */

+

+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)

+  void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Tx Half Complete Callback        */

+  void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Tx Complete Callback             */

+  void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Half Complete Callback        */

+  void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Rx Complete Callback             */

+  void (* ErrorCallback)(struct __UART_HandleTypeDef *huart);             /*!< UART Error Callback                   */

+  void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Abort Complete Callback          */

+  void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */

+  void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart);  /*!< UART Abort Receive Complete Callback  */

+  void (* WakeupCallback)(struct __UART_HandleTypeDef *huart);            /*!< UART Wakeup Callback                  */

+  void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart);        /*!< UART Rx Fifo Full Callback            */

+  void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart);       /*!< UART Tx Fifo Empty Callback           */

+

+  void (* MspInitCallback)(struct __UART_HandleTypeDef *huart);           /*!< UART Msp Init callback                */

+  void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart);         /*!< UART Msp DeInit callback              */

+#endif  /* USE_HAL_UART_REGISTER_CALLBACKS */

+

+} UART_HandleTypeDef;

+

+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  HAL UART Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_UART_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< UART Tx Half Complete Callback ID        */

+  HAL_UART_TX_COMPLETE_CB_ID             = 0x01U,    /*!< UART Tx Complete Callback ID             */

+  HAL_UART_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< UART Rx Half Complete Callback ID        */

+  HAL_UART_RX_COMPLETE_CB_ID             = 0x03U,    /*!< UART Rx Complete Callback ID             */

+  HAL_UART_ERROR_CB_ID                   = 0x04U,    /*!< UART Error Callback ID                   */

+  HAL_UART_ABORT_COMPLETE_CB_ID          = 0x05U,    /*!< UART Abort Complete Callback ID          */

+  HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U,    /*!< UART Abort Transmit Complete Callback ID */

+  HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID  = 0x07U,    /*!< UART Abort Receive Complete Callback ID  */

+  HAL_UART_WAKEUP_CB_ID                  = 0x08U,    /*!< UART Wakeup Callback ID                  */

+  HAL_UART_RX_FIFO_FULL_CB_ID            = 0x09U,    /*!< UART Rx Fifo Full Callback ID            */

+  HAL_UART_TX_FIFO_EMPTY_CB_ID           = 0x0AU,    /*!< UART Tx Fifo Empty Callback ID           */

+

+  HAL_UART_MSPINIT_CB_ID                 = 0x0BU,    /*!< UART MspInit callback ID                 */

+  HAL_UART_MSPDEINIT_CB_ID               = 0x0CU     /*!< UART MspDeInit callback ID               */

+

+} HAL_UART_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL UART Callback pointer definition

+  */

+typedef  void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart);  /*!< pointer to an UART callback function */

+

+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup UART_Exported_Constants UART Exported Constants

+  * @{

+  */

+

+/** @defgroup UART_State_Definition UART State Code Definition

+  * @{

+  */

+#define  HAL_UART_STATE_RESET         0x00000000U    /*!< Peripheral is not initialized

+                                                          Value is allowed for gState and RxState */

+#define  HAL_UART_STATE_READY         0x00000020U    /*!< Peripheral Initialized and ready for use

+                                                          Value is allowed for gState and RxState */

+#define  HAL_UART_STATE_BUSY          0x00000024U    /*!< an internal process is ongoing

+                                                          Value is allowed for gState only */

+#define  HAL_UART_STATE_BUSY_TX       0x00000021U    /*!< Data Transmission process is ongoing

+                                                          Value is allowed for gState only */

+#define  HAL_UART_STATE_BUSY_RX       0x00000022U    /*!< Data Reception process is ongoing

+                                                          Value is allowed for RxState only */

+#define  HAL_UART_STATE_BUSY_TX_RX    0x00000023U    /*!< Data Transmission and Reception process is ongoing

+                                                          Not to be used for neither gState nor RxState.

+                                                          Value is result of combination (Or) between gState and RxState values */

+#define  HAL_UART_STATE_TIMEOUT       0x000000A0U    /*!< Timeout state

+                                                          Value is allowed for gState only */

+#define  HAL_UART_STATE_ERROR         0x000000E0U    /*!< Error

+                                                          Value is allowed for gState only */

+/**

+  * @}

+  */

+

+/** @defgroup UART_Error_Definition   UART Error Definition

+  * @{

+  */

+#define  HAL_UART_ERROR_NONE             ((uint32_t)0x00000000U)    /*!< No error                */

+#define  HAL_UART_ERROR_PE               ((uint32_t)0x00000001U)    /*!< Parity error            */

+#define  HAL_UART_ERROR_NE               ((uint32_t)0x00000002U)    /*!< Noise error             */

+#define  HAL_UART_ERROR_FE               ((uint32_t)0x00000004U)    /*!< Frame error             */

+#define  HAL_UART_ERROR_ORE              ((uint32_t)0x00000008U)    /*!< Overrun error           */

+#define  HAL_UART_ERROR_DMA              ((uint32_t)0x00000010U)    /*!< DMA transfer error      */

+#define  HAL_UART_ERROR_RTO              ((uint32_t)0x00000020U)    /*!< Receiver Timeout error  */

+

+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)

+#define  HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)    /*!< Invalid Callback error  */

+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */

+/**

+  * @}

+  */

+

+/** @defgroup UART_Stop_Bits   UART Number of Stop Bits

+  * @{

+  */

+#define UART_STOPBITS_0_5                    USART_CR2_STOP_0                     /*!< UART frame with 0.5 stop bit  */

+#define UART_STOPBITS_1                     0x00000000U                           /*!< UART frame with 1 stop bit    */

+#define UART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */

+#define UART_STOPBITS_2                      USART_CR2_STOP_1                     /*!< UART frame with 2 stop bits   */

+/**

+  * @}

+  */

+

+/** @defgroup UART_Parity  UART Parity

+  * @{

+  */

+#define UART_PARITY_NONE                    0x00000000U                        /*!< No parity   */

+#define UART_PARITY_EVEN                    USART_CR1_PCE                      /*!< Even parity */

+#define UART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)     /*!< Odd parity  */

+/**

+  * @}

+  */

+

+/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control

+  * @{

+  */

+#define UART_HWCONTROL_NONE                  0x00000000U                          /*!< No hardware control       */

+#define UART_HWCONTROL_RTS                   USART_CR3_RTSE                       /*!< Request To Send           */

+#define UART_HWCONTROL_CTS                   USART_CR3_CTSE                       /*!< Clear To Send             */

+#define UART_HWCONTROL_RTS_CTS               (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< Request and Clear To Send */

+/**

+  * @}

+  */

+

+/** @defgroup UART_Mode UART Transfer Mode

+  * @{

+  */

+#define UART_MODE_RX                        USART_CR1_RE                    /*!< RX mode        */

+#define UART_MODE_TX                        USART_CR1_TE                    /*!< TX mode        */

+#define UART_MODE_TX_RX                     (USART_CR1_TE |USART_CR1_RE)    /*!< RX and TX mode */

+/**

+  * @}

+  */

+

+/** @defgroup UART_State  UART State

+  * @{

+  */

+#define UART_STATE_DISABLE                  0x00000000U         /*!< UART disabled  */

+#define UART_STATE_ENABLE                   USART_CR1_UE        /*!< UART enabled   */

+/**

+  * @}

+  */

+

+/** @defgroup UART_Over_Sampling UART Over Sampling

+  * @{

+  */

+#define UART_OVERSAMPLING_16                0x00000000U         /*!< Oversampling by 16 */

+#define UART_OVERSAMPLING_8                 USART_CR1_OVER8     /*!< Oversampling by 8  */

+/**

+  * @}

+  */

+

+/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method

+  * @{

+  */

+#define UART_ONE_BIT_SAMPLE_DISABLE         0x00000000U         /*!< One-bit sampling disable */

+#define UART_ONE_BIT_SAMPLE_ENABLE          USART_CR3_ONEBIT    /*!< One-bit sampling enable  */

+/**

+  * @}

+  */

+

+/** @defgroup UART_ClockPrescaler  UART Clock Prescaler

+  * @{

+  */

+#define UART_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */

+#define UART_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */

+#define UART_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */

+#define UART_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */

+#define UART_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */

+#define UART_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */

+#define UART_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */

+#define UART_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */

+#define UART_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */

+#define UART_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */

+#define UART_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */

+#define UART_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */

+/**

+  * @}

+  */

+

+/** @defgroup UART_AutoBaud_Rate_Mode    UART Advanced Feature AutoBaud Rate Mode

+  * @{

+  */

+#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT    0x00000000U           /*!< Auto Baud rate detection on start bit            */

+#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0   /*!< Auto Baud rate detection on falling edge         */

+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME   USART_CR2_ABRMODE_1   /*!< Auto Baud rate detection on 0x7F frame detection */

+#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME   USART_CR2_ABRMODE     /*!< Auto Baud rate detection on 0x55 frame detection */

+/**

+  * @}

+  */

+

+/** @defgroup UART_Receiver_Timeout UART Receiver Timeout

+  * @{

+  */

+#define UART_RECEIVER_TIMEOUT_DISABLE       0x00000000U                /*!< UART Receiver Timeout disable */

+#define UART_RECEIVER_TIMEOUT_ENABLE        USART_CR2_RTOEN            /*!< UART Receiver Timeout enable  */

+/**

+  * @}

+  */

+

+/** @defgroup UART_LIN    UART Local Interconnection Network mode

+  * @{

+  */

+#define UART_LIN_DISABLE                    0x00000000U                /*!< Local Interconnect Network disable */

+#define UART_LIN_ENABLE                     USART_CR2_LINEN            /*!< Local Interconnect Network enable  */

+/**

+  * @}

+  */

+

+/** @defgroup UART_LIN_Break_Detection  UART LIN Break Detection

+  * @{

+  */

+#define UART_LINBREAKDETECTLENGTH_10B       0x00000000U                /*!< LIN 10-bit break detection length */

+#define UART_LINBREAKDETECTLENGTH_11B       USART_CR2_LBDL             /*!< LIN 11-bit break detection length  */

+/**

+  * @}

+  */

+

+/** @defgroup UART_DMA_Tx    UART DMA Tx

+  * @{

+  */

+#define UART_DMA_TX_DISABLE                 0x00000000U                /*!< UART DMA TX disabled */

+#define UART_DMA_TX_ENABLE                  USART_CR3_DMAT             /*!< UART DMA TX enabled  */

+/**

+  * @}

+  */

+

+/** @defgroup UART_DMA_Rx   UART DMA Rx

+  * @{

+  */

+#define UART_DMA_RX_DISABLE                 0x00000000U                 /*!< UART DMA RX disabled */

+#define UART_DMA_RX_ENABLE                  USART_CR3_DMAR              /*!< UART DMA RX enabled  */

+/**

+  * @}

+  */

+

+/** @defgroup UART_Half_Duplex_Selection  UART Half Duplex Selection

+  * @{

+  */

+#define UART_HALF_DUPLEX_DISABLE            0x00000000U                 /*!< UART half-duplex disabled */

+#define UART_HALF_DUPLEX_ENABLE             USART_CR3_HDSEL             /*!< UART half-duplex enabled  */

+/**

+  * @}

+  */

+

+/** @defgroup UART_WakeUp_Methods   UART WakeUp Methods

+  * @{

+  */

+#define UART_WAKEUPMETHOD_IDLELINE          0x00000000U                 /*!< UART wake-up on idle line    */

+#define UART_WAKEUPMETHOD_ADDRESSMARK       USART_CR1_WAKE              /*!< UART wake-up on address mark */

+/**

+  * @}

+  */

+

+/** @defgroup UART_Request_Parameters UART Request Parameters

+  * @{

+  */

+#define UART_AUTOBAUD_REQUEST               USART_RQR_ABRRQ        /*!< Auto-Baud Rate Request      */

+#define UART_SENDBREAK_REQUEST              USART_RQR_SBKRQ        /*!< Send Break Request          */

+#define UART_MUTE_MODE_REQUEST              USART_RQR_MMRQ         /*!< Mute Mode Request           */

+#define UART_RXDATA_FLUSH_REQUEST           USART_RQR_RXFRQ        /*!< Receive Data flush Request  */

+#define UART_TXDATA_FLUSH_REQUEST           USART_RQR_TXFRQ        /*!< Transmit data flush Request */

+/**

+  * @}

+  */

+

+/** @defgroup UART_Advanced_Features_Initialization_Type  UART Advanced Feature Initialization Type

+  * @{

+  */

+#define UART_ADVFEATURE_NO_INIT                 0x00000000U          /*!< No advanced feature initialization       */

+#define UART_ADVFEATURE_TXINVERT_INIT           0x00000001U          /*!< TX pin active level inversion            */

+#define UART_ADVFEATURE_RXINVERT_INIT           0x00000002U          /*!< RX pin active level inversion            */

+#define UART_ADVFEATURE_DATAINVERT_INIT         0x00000004U          /*!< Binary data inversion                    */

+#define UART_ADVFEATURE_SWAP_INIT               0x00000008U          /*!< TX/RX pins swap                          */

+#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT   0x00000010U          /*!< RX overrun disable                       */

+#define UART_ADVFEATURE_DMADISABLEONERROR_INIT  0x00000020U          /*!< DMA disable on Reception Error           */

+#define UART_ADVFEATURE_AUTOBAUDRATE_INIT       0x00000040U          /*!< Auto Baud rate detection initialization  */

+#define UART_ADVFEATURE_MSBFIRST_INIT           0x00000080U          /*!< Most significant bit sent/received first */

+/**

+  * @}

+  */

+

+/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion

+  * @{

+  */

+#define UART_ADVFEATURE_TXINV_DISABLE       0x00000000U             /*!< TX pin active level inversion disable */

+#define UART_ADVFEATURE_TXINV_ENABLE        USART_CR2_TXINV         /*!< TX pin active level inversion enable  */

+/**

+  * @}

+  */

+

+/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion

+  * @{

+  */

+#define UART_ADVFEATURE_RXINV_DISABLE       0x00000000U             /*!< RX pin active level inversion disable */

+#define UART_ADVFEATURE_RXINV_ENABLE        USART_CR2_RXINV         /*!< RX pin active level inversion enable  */

+/**

+  * @}

+  */

+

+/** @defgroup UART_Data_Inv  UART Advanced Feature Binary Data Inversion

+  * @{

+  */

+#define UART_ADVFEATURE_DATAINV_DISABLE     0x00000000U             /*!< Binary data inversion disable */

+#define UART_ADVFEATURE_DATAINV_ENABLE      USART_CR2_DATAINV       /*!< Binary data inversion enable  */

+/**

+  * @}

+  */

+

+/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap

+  * @{

+  */

+#define UART_ADVFEATURE_SWAP_DISABLE        0x00000000U             /*!< TX/RX pins swap disable */

+#define UART_ADVFEATURE_SWAP_ENABLE         USART_CR2_SWAP          /*!< TX/RX pins swap enable  */

+/**

+  * @}

+  */

+

+/** @defgroup UART_Overrun_Disable  UART Advanced Feature Overrun Disable

+  * @{

+  */

+#define UART_ADVFEATURE_OVERRUN_ENABLE      0x00000000U             /*!< RX overrun enable  */

+#define UART_ADVFEATURE_OVERRUN_DISABLE     USART_CR3_OVRDIS        /*!< RX overrun disable */

+/**

+  * @}

+  */

+

+/** @defgroup UART_AutoBaudRate_Enable  UART Advanced Feature Auto BaudRate Enable

+  * @{

+  */

+#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE   0x00000000U          /*!< RX Auto Baud rate detection enable  */

+#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE    USART_CR2_ABREN      /*!< RX Auto Baud rate detection disable */

+/**

+  * @}

+  */

+

+/** @defgroup UART_DMA_Disable_on_Rx_Error   UART Advanced Feature DMA Disable On Rx Error

+  * @{

+  */

+#define UART_ADVFEATURE_DMA_ENABLEONRXERROR    0x00000000U          /*!< DMA enable on Reception Error  */

+#define UART_ADVFEATURE_DMA_DISABLEONRXERROR   USART_CR3_DDRE       /*!< DMA disable on Reception Error */

+/**

+  * @}

+  */

+

+/** @defgroup UART_MSB_First   UART Advanced Feature MSB First

+  * @{

+  */

+#define UART_ADVFEATURE_MSBFIRST_DISABLE    0x00000000U             /*!< Most significant bit sent/received first disable */

+#define UART_ADVFEATURE_MSBFIRST_ENABLE     USART_CR2_MSBFIRST      /*!< Most significant bit sent/received first enable  */

+/**

+  * @}

+  */

+

+/** @defgroup UART_Stop_Mode_Enable   UART Advanced Feature Stop Mode Enable

+  * @{

+  */

+#define UART_ADVFEATURE_STOPMODE_DISABLE    0x00000000U             /*!< UART stop mode disable */

+#define UART_ADVFEATURE_STOPMODE_ENABLE     USART_CR1_UESM          /*!< UART stop mode enable  */

+/**

+  * @}

+  */

+

+/** @defgroup UART_Mute_Mode   UART Advanced Feature Mute Mode Enable

+  * @{

+  */

+#define UART_ADVFEATURE_MUTEMODE_DISABLE    0x00000000U             /*!< UART mute mode disable */

+#define UART_ADVFEATURE_MUTEMODE_ENABLE     USART_CR1_MME           /*!< UART mute mode enable  */

+/**

+  * @}

+  */

+

+/** @defgroup UART_CR2_ADDRESS_LSB_POS    UART Address-matching LSB Position In CR2 Register

+  * @{

+  */

+#define UART_CR2_ADDRESS_LSB_POS             24U                                /*!< UART address-matching LSB position in CR2 register */

+/**

+  * @}

+  */

+

+/** @defgroup UART_WakeUp_from_Stop_Selection   UART WakeUp From Stop Selection

+  * @{

+  */

+#define UART_WAKEUP_ON_ADDRESS              0x00000000U             /*!< UART wake-up on address                         */

+#define UART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1         /*!< UART wake-up on start bit                       */

+#define UART_WAKEUP_ON_READDATA_NONEMPTY    USART_CR3_WUS           /*!< UART wake-up on receive data register not empty or RXFIFO is not empty */

+/**

+  * @}

+  */

+

+/** @defgroup UART_DriverEnable_Polarity      UART DriverEnable Polarity

+  * @{

+  */

+#define UART_DE_POLARITY_HIGH               0x00000000U             /*!< Driver enable signal is active high */

+#define UART_DE_POLARITY_LOW                USART_CR3_DEP           /*!< Driver enable signal is active low  */

+/**

+  * @}

+  */

+

+/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS    UART Driver Enable Assertion Time LSB Position In CR1 Register

+  * @{

+  */

+#define UART_CR1_DEAT_ADDRESS_LSB_POS       21U      /*!< UART Driver Enable assertion time LSB position in CR1 register */

+/**

+  * @}

+  */

+

+/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS    UART Driver Enable DeAssertion Time LSB Position In CR1 Register

+  * @{

+  */

+#define UART_CR1_DEDT_ADDRESS_LSB_POS       16U      /*!< UART Driver Enable de-assertion time LSB position in CR1 register */

+/**

+  * @}

+  */

+

+/** @defgroup UART_Interruption_Mask    UART Interruptions Flag Mask

+  * @{

+  */

+#define UART_IT_MASK                        0x001FU  /*!< UART interruptions flags mask */

+/**

+  * @}

+  */

+

+/** @defgroup UART_TimeOut_Value    UART polling-based communications time-out value

+  * @{

+  */

+#define HAL_UART_TIMEOUT_VALUE              0x1FFFFFFU  /*!< UART polling-based communications time-out value */

+/**

+  * @}

+  */

+

+/** @defgroup UART_Flags     UART Status Flags

+  *        Elements values convention: 0xXXXX

+  *           - 0xXXXX  : Flag mask in the ISR register

+  * @{

+  */

+#define UART_FLAG_TXFT                      USART_ISR_TXFT          /*!< UART TXFIFO threshold flag                */

+#define UART_FLAG_RXFT                      USART_ISR_RXFT          /*!< UART RXFIFO threshold flag                */

+#define UART_FLAG_RXFF                      USART_ISR_RXFF          /*!< UART RXFIFO Full flag                     */

+#define UART_FLAG_TXFE                      USART_ISR_TXFE          /*!< UART TXFIFO Empty flag                    */

+#define UART_FLAG_REACK                     USART_ISR_REACK         /*!< UART receive enable acknowledge flag      */

+#define UART_FLAG_TEACK                     USART_ISR_TEACK         /*!< UART transmit enable acknowledge flag     */

+#define UART_FLAG_WUF                       USART_ISR_WUF           /*!< UART wake-up from stop mode flag          */

+#define UART_FLAG_RWU                       USART_ISR_RWU           /*!< UART receiver wake-up from mute mode flag */

+#define UART_FLAG_SBKF                      USART_ISR_SBKF          /*!< UART send break flag                      */

+#define UART_FLAG_CMF                       USART_ISR_CMF           /*!< UART character match flag                 */

+#define UART_FLAG_BUSY                      USART_ISR_BUSY          /*!< UART busy flag                            */

+#define UART_FLAG_ABRF                      USART_ISR_ABRF          /*!< UART auto Baud rate flag                  */

+#define UART_FLAG_ABRE                      USART_ISR_ABRE          /*!< UART auto Baud rate error                 */

+#define UART_FLAG_RTOF                      USART_ISR_RTOF          /*!< UART receiver timeout flag                */

+#define UART_FLAG_CTS                       USART_ISR_CTS           /*!< UART clear to send flag                   */

+#define UART_FLAG_CTSIF                     USART_ISR_CTSIF         /*!< UART clear to send interrupt flag         */

+#define UART_FLAG_LBDF                      USART_ISR_LBDF          /*!< UART LIN break detection flag             */

+#define UART_FLAG_TXE                       USART_ISR_TXE_TXFNF     /*!< UART transmit data register empty         */

+#define UART_FLAG_TXFNF                     USART_ISR_TXE_TXFNF     /*!< UART TXFIFO not full                      */

+#define UART_FLAG_TC                        USART_ISR_TC            /*!< UART transmission complete                */

+#define UART_FLAG_RXNE                      USART_ISR_RXNE_RXFNE    /*!< UART read data register not empty         */

+#define UART_FLAG_RXFNE                     USART_ISR_RXNE_RXFNE    /*!< UART RXFIFO not empty                     */

+#define UART_FLAG_IDLE                      USART_ISR_IDLE          /*!< UART idle flag                            */

+#define UART_FLAG_ORE                       USART_ISR_ORE           /*!< UART overrun error                        */

+#define UART_FLAG_NE                        USART_ISR_NE            /*!< UART noise error                          */

+#define UART_FLAG_FE                        USART_ISR_FE            /*!< UART frame error                          */

+#define UART_FLAG_PE                        USART_ISR_PE            /*!< UART parity error                         */

+/**

+  * @}

+  */

+

+/** @defgroup UART_Interrupt_definition   UART Interrupts Definition

+  *        Elements values convention: 000ZZZZZ0XXYYYYYb

+  *           - YYYYY  : Interrupt source position in the XX register (5bits)

+  *           - XX  : Interrupt source register (2bits)

+  *                 - 01: CR1 register

+  *                 - 10: CR2 register

+  *                 - 11: CR3 register

+  *           - ZZZZZ  : Flag position in the ISR register(5bits)

+  *        Elements values convention: 000000000XXYYYYYb

+  *           - YYYYY  : Interrupt source position in the XX register (5bits)

+  *           - XX  : Interrupt source register (2bits)

+  *                 - 01: CR1 register

+  *                 - 10: CR2 register

+  *                 - 11: CR3 register

+  *        Elements values convention: 0000ZZZZ00000000b

+  *           - ZZZZ  : Flag position in the ISR register(4bits)

+  * @{

+  */

+#define UART_IT_PE                          0x0028U                  /*!< UART parity error interruption                 */

+#define UART_IT_TXE                         0x0727U                  /*!< UART transmit data register empty interruption */

+#define UART_IT_TXFNF                       0x0727U                  /*!< UART TX FIFO not full interruption             */

+#define UART_IT_TC                          0x0626U                  /*!< UART transmission complete interruption        */

+#define UART_IT_RXNE                        0x0525U                  /*!< UART read data register not empty interruption */

+#define UART_IT_RXFNE                       0x0525U                  /*!< UART RXFIFO not empty interruption             */

+#define UART_IT_IDLE                        0x0424U                  /*!< UART idle interruption                         */

+#define UART_IT_LBD                         0x0846U                  /*!< UART LIN break detection interruption          */

+#define UART_IT_CTS                         0x096AU                  /*!< UART CTS interruption                          */

+#define UART_IT_CM                          0x112EU                  /*!< UART character match interruption              */

+#define UART_IT_WUF                         0x1476U                  /*!< UART wake-up from stop mode interruption       */

+#define UART_IT_RXFF                        0x183FU                  /*!< UART RXFIFO full interruption                  */

+#define UART_IT_TXFE                        0x173EU                  /*!< UART TXFIFO empty interruption                 */

+#define UART_IT_RXFT                        0x1A7CU                  /*!< UART RXFIFO threshold reached interruption     */

+#define UART_IT_TXFT                        0x1B77U                  /*!< UART TXFIFO threshold reached interruption     */

+#define UART_IT_RTO                         0x0B3AU                  /*!< UART receiver timeout interruption             */

+

+#define UART_IT_ERR                         0x0060U                  /*!< UART error interruption         */

+

+#define UART_IT_ORE                         0x0300U                  /*!< UART overrun error interruption */

+#define UART_IT_NE                          0x0200U                  /*!< UART noise error interruption   */

+#define UART_IT_FE                          0x0100U                  /*!< UART frame error interruption   */

+/**

+  * @}

+  */

+

+/** @defgroup UART_IT_CLEAR_Flags  UART Interruption Clear Flags

+  * @{

+  */

+#define UART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag           */

+#define UART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag          */

+#define UART_CLEAR_NEF                       USART_ICR_NECF            /*!< Noise Error detected Clear Flag   */

+#define UART_CLEAR_OREF                      USART_ICR_ORECF           /*!< Overrun Error Clear Flag          */

+#define UART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag     */

+#define UART_CLEAR_TXFECF                    USART_ICR_TXFECF          /*!< TXFIFO empty clear flag           */

+#define UART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag  */

+#define UART_CLEAR_LBDF                      USART_ICR_LBDCF           /*!< LIN Break Detection Clear Flag    */

+#define UART_CLEAR_CTSF                      USART_ICR_CTSCF           /*!< CTS Interrupt Clear Flag          */

+#define UART_CLEAR_CMF                       USART_ICR_CMCF            /*!< Character Match Clear Flag        */

+#define UART_CLEAR_WUF                       USART_ICR_WUCF            /*!< Wake Up from stop mode Clear Flag */

+#define UART_CLEAR_RTOF                      USART_ICR_RTOCF           /*!< UART receiver timeout clear flag  */

+/**

+  * @}

+  */

+

+

+/**

+  * @}

+  */

+

+/* Exported macros -----------------------------------------------------------*/

+/** @defgroup UART_Exported_Macros UART Exported Macros

+  * @{

+  */

+

+/** @brief  Reset UART handle states.

+  * @param  __HANDLE__ UART handle.

+  * @retval None

+  */

+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)

+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \

+                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \

+                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \

+                                                       (__HANDLE__)->MspInitCallback = NULL;             \

+                                                       (__HANDLE__)->MspDeInitCallback = NULL;           \

+                                                     } while(0U)

+#else

+#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \

+                                                       (__HANDLE__)->gState = HAL_UART_STATE_RESET;      \

+                                                       (__HANDLE__)->RxState = HAL_UART_STATE_RESET;     \

+                                                     } while(0U)

+#endif /*USE_HAL_UART_REGISTER_CALLBACKS */

+

+/** @brief  Flush the UART Data registers.

+  * @param  __HANDLE__ specifies the UART Handle.

+  * @retval None

+  */

+#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__)  \

+  do{                \

+    SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \

+    SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \

+  }  while(0U)

+

+/** @brief  Clear the specified UART pending flag.

+  * @param  __HANDLE__ specifies the UART Handle.

+  * @param  __FLAG__ specifies the flag to check.

+  *          This parameter can be any combination of the following values:

+  *            @arg @ref UART_CLEAR_PEF      Parity Error Clear Flag

+  *            @arg @ref UART_CLEAR_FEF      Framing Error Clear Flag

+  *            @arg @ref UART_CLEAR_NEF      Noise detected Clear Flag

+  *            @arg @ref UART_CLEAR_OREF     Overrun Error Clear Flag

+  *            @arg @ref UART_CLEAR_IDLEF    IDLE line detected Clear Flag

+  *            @arg @ref UART_CLEAR_TXFECF   TXFIFO empty clear Flag

+  *            @arg @ref UART_CLEAR_TCF      Transmission Complete Clear Flag

+  *            @arg @ref UART_CLEAR_RTOF     Receiver Timeout clear flag

+  *            @arg @ref UART_CLEAR_LBDF     LIN Break Detection Clear Flag

+  *            @arg @ref UART_CLEAR_CTSF     CTS Interrupt Clear Flag

+  *            @arg @ref UART_CLEAR_CMF      Character Match Clear Flag

+  *            @arg @ref UART_CLEAR_WUF      Wake Up from stop mode Clear Flag

+  * @retval None

+  */

+#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))

+

+/** @brief  Clear the UART PE pending flag.

+  * @param  __HANDLE__ specifies the UART Handle.

+  * @retval None

+  */

+#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF)

+

+/** @brief  Clear the UART FE pending flag.

+  * @param  __HANDLE__ specifies the UART Handle.

+  * @retval None

+  */

+#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF)

+

+/** @brief  Clear the UART NE pending flag.

+  * @param  __HANDLE__ specifies the UART Handle.

+  * @retval None

+  */

+#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__)  __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF)

+

+/** @brief  Clear the UART ORE pending flag.

+  * @param  __HANDLE__ specifies the UART Handle.

+  * @retval None

+  */

+#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF)

+

+/** @brief  Clear the UART IDLE pending flag.

+  * @param  __HANDLE__ specifies the UART Handle.

+  * @retval None

+  */

+#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF)

+

+/** @brief  Clear the UART TX FIFO empty clear flag.

+  * @param  __HANDLE__ specifies the UART Handle.

+  * @retval None

+  */

+#define __HAL_UART_CLEAR_TXFECF(__HANDLE__)   __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF)

+

+/** @brief  Check whether the specified UART flag is set or not.

+  * @param  __HANDLE__ specifies the UART Handle.

+  * @param  __FLAG__ specifies the flag to check.

+  *        This parameter can be one of the following values:

+  *            @arg @ref UART_FLAG_TXFT  TXFIFO threshold flag

+  *            @arg @ref UART_FLAG_RXFT  RXFIFO threshold flag

+  *            @arg @ref UART_FLAG_RXFF  RXFIFO Full flag

+  *            @arg @ref UART_FLAG_TXFE  TXFIFO Empty flag

+  *            @arg @ref UART_FLAG_REACK Receive enable acknowledge flag

+  *            @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag

+  *            @arg @ref UART_FLAG_WUF   Wake up from stop mode flag

+  *            @arg @ref UART_FLAG_RWU   Receiver wake up flag (if the UART in mute mode)

+  *            @arg @ref UART_FLAG_SBKF  Send Break flag

+  *            @arg @ref UART_FLAG_CMF   Character match flag

+  *            @arg @ref UART_FLAG_BUSY  Busy flag

+  *            @arg @ref UART_FLAG_ABRF  Auto Baud rate detection flag

+  *            @arg @ref UART_FLAG_ABRE  Auto Baud rate detection error flag

+  *            @arg @ref UART_FLAG_CTS   CTS Change flag

+  *            @arg @ref UART_FLAG_LBDF  LIN Break detection flag

+  *            @arg @ref UART_FLAG_TXE   Transmit data register empty flag

+  *            @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag

+  *            @arg @ref UART_FLAG_TC    Transmission Complete flag

+  *            @arg @ref UART_FLAG_RXNE  Receive data register not empty flag

+  *            @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag

+  *            @arg @ref UART_FLAG_RTOF  Receiver Timeout flag

+  *            @arg @ref UART_FLAG_IDLE  Idle Line detection flag

+  *            @arg @ref UART_FLAG_ORE   Overrun Error flag

+  *            @arg @ref UART_FLAG_NE    Noise Error flag

+  *            @arg @ref UART_FLAG_FE    Framing Error flag

+  *            @arg @ref UART_FLAG_PE    Parity Error flag

+  * @retval The new state of __FLAG__ (TRUE or FALSE).

+  */

+#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

+

+/** @brief  Enable the specified UART interrupt.

+  * @param  __HANDLE__ specifies the UART Handle.

+  * @param  __INTERRUPT__ specifies the UART interrupt source to enable.

+  *          This parameter can be one of the following values:

+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt

+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt

+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt

+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt

+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt

+  *            @arg @ref UART_IT_CM    Character match interrupt

+  *            @arg @ref UART_IT_CTS   CTS change interrupt

+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt

+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt

+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt

+  *            @arg @ref UART_IT_TC    Transmission complete interrupt

+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt

+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt

+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt

+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt

+  *            @arg @ref UART_IT_PE    Parity Error interrupt

+  *            @arg @ref UART_IT_ERR   Error interrupt (frame error, noise error, overrun error)

+  * @retval None

+  */

+#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \

+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))): \

+                                                           ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & UART_IT_MASK))))

+

+

+/** @brief  Disable the specified UART interrupt.

+  * @param  __HANDLE__ specifies the UART Handle.

+  * @param  __INTERRUPT__ specifies the UART interrupt source to disable.

+  *          This parameter can be one of the following values:

+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt

+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt

+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt

+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt

+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt

+  *            @arg @ref UART_IT_CM    Character match interrupt

+  *            @arg @ref UART_IT_CTS   CTS change interrupt

+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt

+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt

+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt

+  *            @arg @ref UART_IT_TC    Transmission complete interrupt

+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt

+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt

+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt

+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt

+  *            @arg @ref UART_IT_PE    Parity Error interrupt

+  *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)

+  * @retval None

+  */

+#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \

+                                                           ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))): \

+                                                           ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))

+

+/** @brief  Check whether the specified UART interrupt has occurred or not.

+  * @param  __HANDLE__ specifies the UART Handle.

+  * @param  __INTERRUPT__ specifies the UART interrupt to check.

+  *          This parameter can be one of the following values:

+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt

+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt

+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt

+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt

+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt

+  *            @arg @ref UART_IT_CM    Character match interrupt

+  *            @arg @ref UART_IT_CTS   CTS change interrupt

+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt

+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt

+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt

+  *            @arg @ref UART_IT_TC    Transmission complete interrupt

+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt

+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt

+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt

+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt

+  *            @arg @ref UART_IT_PE    Parity Error interrupt

+  *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)

+  * @retval The new state of __INTERRUPT__ (SET or RESET).

+  */

+#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\

+                                                        & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET)

+

+/** @brief  Check whether the specified UART interrupt source is enabled or not.

+  * @param  __HANDLE__ specifies the UART Handle.

+  * @param  __INTERRUPT__ specifies the UART interrupt source to check.

+  *          This parameter can be one of the following values:

+  *            @arg @ref UART_IT_RXFF  RXFIFO Full interrupt

+  *            @arg @ref UART_IT_TXFE  TXFIFO Empty interrupt

+  *            @arg @ref UART_IT_RXFT  RXFIFO threshold interrupt

+  *            @arg @ref UART_IT_TXFT  TXFIFO threshold interrupt

+  *            @arg @ref UART_IT_WUF   Wakeup from stop mode interrupt

+  *            @arg @ref UART_IT_CM    Character match interrupt

+  *            @arg @ref UART_IT_CTS   CTS change interrupt

+  *            @arg @ref UART_IT_LBD   LIN Break detection interrupt

+  *            @arg @ref UART_IT_TXE   Transmit Data Register empty interrupt

+  *            @arg @ref UART_IT_TXFNF TX FIFO not full interrupt

+  *            @arg @ref UART_IT_TC    Transmission complete interrupt

+  *            @arg @ref UART_IT_RXNE  Receive Data register not empty interrupt

+  *            @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt

+  *            @arg @ref UART_IT_RTO   Receive Timeout interrupt

+  *            @arg @ref UART_IT_IDLE  Idle line detection interrupt

+  *            @arg @ref UART_IT_PE    Parity Error interrupt

+  *            @arg @ref UART_IT_ERR   Error interrupt (Frame error, noise error, overrun error)

+  * @retval The new state of __INTERRUPT__ (SET or RESET).

+  */

+#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ? (__HANDLE__)->Instance->CR1 : \

+                                                                (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ? (__HANDLE__)->Instance->CR2 : \

+                                                                 (__HANDLE__)->Instance->CR3)) & (1U << (((uint16_t)(__INTERRUPT__)) & UART_IT_MASK)))  != RESET) ? SET : RESET)

+

+/** @brief  Clear the specified UART ISR flag, in setting the proper ICR register flag.

+  * @param  __HANDLE__ specifies the UART Handle.

+  * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set

+  *                       to clear the corresponding interrupt

+  *          This parameter can be one of the following values:

+  *            @arg @ref UART_CLEAR_PEF    Parity Error Clear Flag

+  *            @arg @ref UART_CLEAR_FEF    Framing Error Clear Flag

+  *            @arg @ref UART_CLEAR_NEF    Noise detected Clear Flag

+  *            @arg @ref UART_CLEAR_OREF   Overrun Error Clear Flag

+  *            @arg @ref UART_CLEAR_IDLEF  IDLE line detected Clear Flag

+  *            @arg @ref UART_CLEAR_RTOF   Receiver timeout clear flag

+  *            @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag

+  *            @arg @ref UART_CLEAR_TCF    Transmission Complete Clear Flag

+  *            @arg @ref UART_CLEAR_LBDF   LIN Break Detection Clear Flag

+  *            @arg @ref UART_CLEAR_CTSF   CTS Interrupt Clear Flag

+  *            @arg @ref UART_CLEAR_CMF    Character Match Clear Flag

+  *            @arg @ref UART_CLEAR_WUF    Wake Up from stop mode Clear Flag

+  * @retval None

+  */

+#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))

+

+/** @brief  Set a specific UART request flag.

+  * @param  __HANDLE__ specifies the UART Handle.

+  * @param  __REQ__ specifies the request flag to set

+  *          This parameter can be one of the following values:

+  *            @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request

+  *            @arg @ref UART_SENDBREAK_REQUEST Send Break Request

+  *            @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request

+  *            @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request

+  *            @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request

+  * @retval None

+  */

+#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))

+

+/** @brief  Enable the UART one bit sample method.

+  * @param  __HANDLE__ specifies the UART Handle.

+  * @retval None

+  */

+#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

+

+/** @brief  Disable the UART one bit sample method.

+  * @param  __HANDLE__ specifies the UART Handle.

+  * @retval None

+  */

+#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)

+

+/** @brief  Enable UART.

+  * @param  __HANDLE__ specifies the UART Handle.

+  * @retval None

+  */

+#define __HAL_UART_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

+

+/** @brief  Disable UART.

+  * @param  __HANDLE__ specifies the UART Handle.

+  * @retval None

+  */

+#define __HAL_UART_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

+

+/** @brief  Enable CTS flow control.

+  * @note   This macro allows to enable CTS hardware flow control for a given UART instance,

+  *         without need to call HAL_UART_Init() function.

+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.

+  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need

+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :

+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )

+  *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))

+  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).

+  * @param  __HANDLE__ specifies the UART Handle.

+  * @retval None

+  */

+#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__)        \

+  do{                                                      \

+    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE);  \

+    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE;        \

+  } while(0U)

+

+/** @brief  Disable CTS flow control.

+  * @note   This macro allows to disable CTS hardware flow control for a given UART instance,

+  *         without need to call HAL_UART_Init() function.

+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.

+  * @note   As macro is expected to be used for modifying CTS Hw flow control feature activation, without need

+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :

+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )

+  *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))

+  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).

+  * @param  __HANDLE__ specifies the UART Handle.

+  * @retval None

+  */

+#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__)        \

+  do{                                                       \

+    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \

+    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE);      \

+  } while(0U)

+

+/** @brief  Enable RTS flow control.

+  * @note   This macro allows to enable RTS hardware flow control for a given UART instance,

+  *         without need to call HAL_UART_Init() function.

+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.

+  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need

+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :

+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )

+  *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))

+  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).

+  * @param  __HANDLE__ specifies the UART Handle.

+  * @retval None

+  */

+#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__)       \

+  do{                                                     \

+    SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \

+    (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE;       \

+  } while(0U)

+

+/** @brief  Disable RTS flow control.

+  * @note   This macro allows to disable RTS hardware flow control for a given UART instance,

+  *         without need to call HAL_UART_Init() function.

+  *         As involving direct access to UART registers, usage of this macro should be fully endorsed by user.

+  * @note   As macro is expected to be used for modifying RTS Hw flow control feature activation, without need

+  *         for USART instance Deinit/Init, following conditions for macro call should be fulfilled :

+  *           - UART instance should have already been initialised (through call of HAL_UART_Init() )

+  *           - macro could only be called when corresponding UART instance is disabled (i.e. __HAL_UART_DISABLE(__HANDLE__))

+  *             and should be followed by an Enable macro (i.e. __HAL_UART_ENABLE(__HANDLE__)).

+  * @param  __HANDLE__ specifies the UART Handle.

+  * @retval None

+  */

+#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__)       \

+  do{                                                      \

+    CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\

+    (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE);     \

+  } while(0U)

+/**

+  * @}

+  */

+

+/* Private macros --------------------------------------------------------*/

+/** @defgroup UART_Private_Macros   UART Private Macros

+  * @{

+  */

+/** @brief  Get UART clok division factor from clock prescaler value.

+  * @param  __CLOCKPRESCALER__ UART prescaler value.

+  * @retval UART clock division factor

+  */

+#define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \

+  (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   ? 1U :       \

+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   ? 2U :       \

+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   ? 4U :       \

+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   ? 6U :       \

+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   ? 8U :       \

+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  ? 10U :      \

+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  ? 12U :      \

+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  ? 16U :      \

+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  ? 32U :      \

+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  ? 64U :      \

+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U :     \

+   ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U)

+

+/** @brief  BRR division operation to set BRR register with LPUART.

+  * @param  __PCLK__ LPUART clock.

+  * @param  __BAUD__ Baud rate set by the user.

+  * @param  __CLOCKPRESCALER__ UART prescaler value.

+  * @retval Division result

+  */

+#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__)      ((uint32_t)(((((uint64_t)(__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*256U)\

+                                                                      + (uint32_t)((__BAUD__)/2U)) / (__BAUD__)))

+

+/** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.

+  * @param  __PCLK__ UART clock.

+  * @param  __BAUD__ Baud rate set by the user.

+  * @param  __CLOCKPRESCALER__ UART prescaler value.

+  * @retval Division result

+  */

+#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)   (((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))*2U)\

+                                                                       + ((__BAUD__)/2U)) / (__BAUD__))

+

+/** @brief  BRR division operation to set BRR register in 16-bit oversampling mode.

+  * @param  __PCLK__ UART clock.

+  * @param  __BAUD__ Baud rate set by the user.

+  * @param  __CLOCKPRESCALER__ UART prescaler value.

+  * @retval Division result

+  */

+#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__)  ((((__PCLK__)/UART_GET_DIV_FACTOR((__CLOCKPRESCALER__)))\

+                                                                       + ((__BAUD__)/2U)) / (__BAUD__))

+

+/** @brief  Check whether or not UART instance is Low Power UART.

+  * @param  __HANDLE__ specifies the UART Handle.

+  * @retval SET (instance is LPUART) or RESET (instance isn't LPUART)

+  */

+#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance))

+

+/** @brief  Check UART Baud rate.

+  * @param  __BAUDRATE__ Baudrate specified by the user.

+  *         The maximum Baud Rate is derived from the maximum clock on H7 (i.e. 100 MHz)

+  *         divided by the smallest oversampling used on the USART (i.e. 8)

+  * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)

+  */

+#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 12500001U)

+

+/** @brief  Check UART assertion time.

+  * @param  __TIME__ 5-bit value assertion time.

+  * @retval Test result (TRUE or FALSE).

+  */

+#define IS_UART_ASSERTIONTIME(__TIME__)    ((__TIME__) <= 0x1FU)

+

+/** @brief  Check UART deassertion time.

+  * @param  __TIME__ 5-bit value deassertion time.

+  * @retval Test result (TRUE or FALSE).

+  */

+#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU)

+

+/**

+  * @brief Ensure that UART frame number of stop bits is valid.

+  * @param __STOPBITS__ UART frame number of stop bits.

+  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)

+  */

+#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \

+                                        ((__STOPBITS__) == UART_STOPBITS_1)   || \

+                                        ((__STOPBITS__) == UART_STOPBITS_1_5) || \

+                                        ((__STOPBITS__) == UART_STOPBITS_2))

+

+/**

+  * @brief Ensure that LPUART frame number of stop bits is valid.

+  * @param __STOPBITS__ LPUART frame number of stop bits.

+  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)

+  */

+#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \

+                                          ((__STOPBITS__) == UART_STOPBITS_2))

+

+/**

+  * @brief Ensure that UART frame parity is valid.

+  * @param __PARITY__ UART frame parity.

+  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

+  */

+#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \

+                                    ((__PARITY__) == UART_PARITY_EVEN) || \

+                                    ((__PARITY__) == UART_PARITY_ODD))

+

+/**

+  * @brief Ensure that UART hardware flow control is valid.

+  * @param __CONTROL__ UART hardware flow control.

+  * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid)

+  */

+#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\

+  (((__CONTROL__) == UART_HWCONTROL_NONE) || \

+   ((__CONTROL__) == UART_HWCONTROL_RTS)  || \

+   ((__CONTROL__) == UART_HWCONTROL_CTS)  || \

+   ((__CONTROL__) == UART_HWCONTROL_RTS_CTS))

+

+/**

+  * @brief Ensure that UART communication mode is valid.

+  * @param __MODE__ UART communication mode.

+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

+  */

+#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))

+

+/**

+  * @brief Ensure that UART state is valid.

+  * @param __STATE__ UART state.

+  * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

+  */

+#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \

+                                  ((__STATE__) == UART_STATE_ENABLE))

+

+/**

+  * @brief Ensure that UART oversampling is valid.

+  * @param __SAMPLING__ UART oversampling.

+  * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)

+  */

+#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \

+                                            ((__SAMPLING__) == UART_OVERSAMPLING_8))

+

+/**

+  * @brief Ensure that UART frame sampling is valid.

+  * @param __ONEBIT__ UART frame sampling.

+  * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)

+  */

+#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \

+                                            ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE))

+

+/**

+  * @brief Ensure that UART auto Baud rate detection mode is valid.

+  * @param __MODE__ UART auto Baud rate detection mode.

+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

+  */

+#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__)  (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT)    || \

+                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \

+                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME)   || \

+                                                        ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME))

+

+/**

+  * @brief Ensure that UART receiver timeout setting is valid.

+  * @param __TIMEOUT__ UART receiver timeout setting.

+  * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid)

+  */

+#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__)  (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \

+                                                ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE))

+

+/** @brief  Check the receiver timeout value.

+  * @note   The maximum UART receiver timeout value is 0xFFFFFF.

+  * @param  __TIMEOUTVALUE__ receiver timeout value.

+  * @retval Test result (TRUE or FALSE)

+  */

+#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__)  ((__TIMEOUTVALUE__) <= 0xFFFFFFU)

+

+/**

+  * @brief Ensure that UART LIN state is valid.

+  * @param __LIN__ UART LIN state.

+  * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid)

+  */

+#define IS_UART_LIN(__LIN__)        (((__LIN__) == UART_LIN_DISABLE) || \

+                                     ((__LIN__) == UART_LIN_ENABLE))

+

+/**

+  * @brief Ensure that UART LIN break detection length is valid.

+  * @param __LENGTH__ UART LIN break detection length.

+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

+  */

+#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \

+                                                     ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B))

+

+/**

+  * @brief Ensure that UART DMA TX state is valid.

+  * @param __DMATX__ UART DMA TX state.

+  * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)

+  */

+#define IS_UART_DMA_TX(__DMATX__)     (((__DMATX__) == UART_DMA_TX_DISABLE) || \

+                                       ((__DMATX__) == UART_DMA_TX_ENABLE))

+

+/**

+  * @brief Ensure that UART DMA RX state is valid.

+  * @param __DMARX__ UART DMA RX state.

+  * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)

+  */

+#define IS_UART_DMA_RX(__DMARX__)     (((__DMARX__) == UART_DMA_RX_DISABLE) || \

+                                       ((__DMARX__) == UART_DMA_RX_ENABLE))

+

+/**

+  * @brief Ensure that UART half-duplex state is valid.

+  * @param __HDSEL__ UART half-duplex state.

+  * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid)

+  */

+#define IS_UART_HALF_DUPLEX(__HDSEL__)     (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \

+                                            ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE))

+

+/**

+  * @brief Ensure that UART wake-up method is valid.

+  * @param __WAKEUP__ UART wake-up method .

+  * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid)

+  */

+#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \

+                                          ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK))

+

+/**

+  * @brief Ensure that UART request parameter is valid.

+  * @param __PARAM__ UART request parameter.

+  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

+  */

+#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST)     || \

+                                              ((__PARAM__) == UART_SENDBREAK_REQUEST)    || \

+                                              ((__PARAM__) == UART_MUTE_MODE_REQUEST)    || \

+                                              ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \

+                                              ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST))

+

+/**

+  * @brief Ensure that UART advanced features initialization is valid.

+  * @param __INIT__ UART advanced features initialization.

+  * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid)

+  */

+#define IS_UART_ADVFEATURE_INIT(__INIT__)   ((__INIT__) <= (UART_ADVFEATURE_NO_INIT                | \

+                                                            UART_ADVFEATURE_TXINVERT_INIT          | \

+                                                            UART_ADVFEATURE_RXINVERT_INIT          | \

+                                                            UART_ADVFEATURE_DATAINVERT_INIT        | \

+                                                            UART_ADVFEATURE_SWAP_INIT              | \

+                                                            UART_ADVFEATURE_RXOVERRUNDISABLE_INIT  | \

+                                                            UART_ADVFEATURE_DMADISABLEONERROR_INIT | \

+                                                            UART_ADVFEATURE_AUTOBAUDRATE_INIT      | \

+                                                            UART_ADVFEATURE_MSBFIRST_INIT))

+

+/**

+  * @brief Ensure that UART frame TX inversion setting is valid.

+  * @param __TXINV__ UART frame TX inversion setting.

+  * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid)

+  */

+#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \

+                                             ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE))

+

+/**

+  * @brief Ensure that UART frame RX inversion setting is valid.

+  * @param __RXINV__ UART frame RX inversion setting.

+  * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid)

+  */

+#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \

+                                             ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE))

+

+/**

+  * @brief Ensure that UART frame data inversion setting is valid.

+  * @param __DATAINV__ UART frame data inversion setting.

+  * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid)

+  */

+#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \

+                                                 ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE))

+

+/**

+  * @brief Ensure that UART frame RX/TX pins swap setting is valid.

+  * @param __SWAP__ UART frame RX/TX pins swap setting.

+  * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid)

+  */

+#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \

+                                           ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE))

+

+/**

+  * @brief Ensure that UART frame overrun setting is valid.

+  * @param __OVERRUN__ UART frame overrun setting.

+  * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid)

+  */

+#define IS_UART_OVERRUN(__OVERRUN__)     (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \

+                                          ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE))

+

+/**

+  * @brief Ensure that UART auto Baud rate state is valid.

+  * @param __AUTOBAUDRATE__ UART auto Baud rate state.

+  * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid)

+  */

+#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__)  (((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \

+                                                            ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE))

+

+/**

+  * @brief Ensure that UART DMA enabling or disabling on error setting is valid.

+  * @param __DMA__ UART DMA enabling or disabling on error setting.

+  * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid)

+  */

+#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__)  (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \

+                                                   ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR))

+

+/**

+  * @brief Ensure that UART frame MSB first setting is valid.

+  * @param __MSBFIRST__ UART frame MSB first setting.

+  * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid)

+  */

+#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \

+                                                   ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE))

+

+/**

+  * @brief Ensure that UART stop mode state is valid.

+  * @param __STOPMODE__ UART stop mode state.

+  * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid)

+  */

+#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \

+                                                   ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE))

+

+/**

+  * @brief Ensure that UART mute mode state is valid.

+  * @param __MUTE__ UART mute mode state.

+  * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid)

+  */

+#define IS_UART_MUTE_MODE(__MUTE__)       (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \

+                                           ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE))

+

+/**

+  * @brief Ensure that UART wake-up selection is valid.

+  * @param __WAKE__ UART wake-up selection.

+  * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid)

+  */

+#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS)           || \

+                                            ((__WAKE__) == UART_WAKEUP_ON_STARTBIT)          || \

+                                            ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY))

+

+/**

+  * @brief Ensure that UART driver enable polarity is valid.

+  * @param __POLARITY__ UART driver enable polarity.

+  * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid)

+  */

+#define IS_UART_DE_POLARITY(__POLARITY__)    (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \

+                                              ((__POLARITY__) == UART_DE_POLARITY_LOW))

+

+/**

+  * @brief Ensure that UART Prescaler is valid.

+  * @param __CLOCKPRESCALER__ UART Prescaler value.

+  * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)

+  */

+#define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1)   || \

+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2)   || \

+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4)   || \

+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6)   || \

+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8)   || \

+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10)  || \

+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12)  || \

+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16)  || \

+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32)  || \

+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64)  || \

+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \

+                                               ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256))

+

+/**

+  * @}

+  */

+

+/* Include UART HAL Extended module */

+#include "stm32h7xx_hal_uart_ex.h"

+

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup UART_Exported_Functions UART Exported Functions

+  * @{

+  */

+

+/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions

+  * @{

+  */

+

+/* Initialization and de-initialization functions  ****************************/

+HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);

+HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);

+HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);

+HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);

+HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart);

+void HAL_UART_MspInit(UART_HandleTypeDef *huart);

+void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);

+

+/* Callbacks Register/UnRegister functions  ***********************************/

+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)

+HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID,

+                                            pUART_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID);

+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+/** @addtogroup UART_Exported_Functions_Group2 IO operation functions

+  * @{

+  */

+

+/* IO operation functions *****************************************************/

+HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);

+HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);

+HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);

+HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);

+HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);

+HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);

+/* Transfer Abort functions */

+HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart);

+HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart);

+HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart);

+HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart);

+HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart);

+HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart);

+

+void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);

+void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);

+void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);

+void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);

+void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);

+void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);

+void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart);

+void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart);

+void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart);

+

+/**

+  * @}

+  */

+

+/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions

+  * @{

+  */

+

+/* Peripheral Control functions  ************************************************/

+void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue);

+HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart);

+HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart);

+

+HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);

+HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart);

+HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart);

+void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);

+HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);

+HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);

+

+/**

+  * @}

+  */

+

+/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions

+  * @{

+  */

+

+/* Peripheral State and Errors functions  **************************************************/

+HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);

+uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private functions -----------------------------------------------------------*/

+/** @addtogroup UART_Private_Functions UART Private Functions

+  * @{

+  */

+#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)

+void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart);

+#endif /* USE_HAL_UART_REGISTER_CALLBACKS */

+HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart);

+HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart);

+HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status,

+                                              uint32_t Tickstart, uint32_t Timeout);

+void UART_AdvFeatureConfig(UART_HandleTypeDef *huart);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_UART_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_uart_ex.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_uart_ex.h
new file mode 100644
index 0000000000..bad4a66762
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_uart_ex.h
@@ -0,0 +1,864 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_uart_ex.h

+  * @author  MCD Application Team

+  * @brief   Header file of UART HAL Extended module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_UART_EX_H

+#define STM32H7xx_HAL_UART_EX_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup UARTEx

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup UARTEx_Exported_Types UARTEx Exported Types

+  * @{

+  */

+

+/**

+  * @brief  UART wake up from stop mode parameters

+  */

+typedef struct

+{

+  uint32_t WakeUpEvent;        /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF).

+                                    This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection.

+                                    If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must

+                                    be filled up. */

+

+  uint16_t AddressLength;      /*!< Specifies whether the address is 4 or 7-bit long.

+                                    This parameter can be a value of @ref UARTEx_WakeUp_Address_Length.  */

+

+  uint8_t Address;             /*!< UART/USART node address (7-bit long max). */

+} UART_WakeUpTypeDef;

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants

+  * @{

+  */

+

+/** @defgroup UARTEx_Word_Length UARTEx Word Length

+  * @{

+  */

+#define UART_WORDLENGTH_7B          USART_CR1_M1   /*!< 7-bit long UART frame */

+#define UART_WORDLENGTH_8B          0x00000000U    /*!< 8-bit long UART frame */

+#define UART_WORDLENGTH_9B          USART_CR1_M0   /*!< 9-bit long UART frame */

+/**

+  * @}

+  */

+

+/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length

+  * @{

+  */

+#define UART_ADDRESS_DETECT_4B      0x00000000U      /*!< 4-bit long wake-up address */

+#define UART_ADDRESS_DETECT_7B      USART_CR2_ADDM7  /*!< 7-bit long wake-up address */

+/**

+  * @}

+  */

+

+/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode

+  * @brief    UART FIFO mode

+  * @{

+  */

+#define UART_FIFOMODE_DISABLE       0x00000000U       /*!< FIFO mode disable */

+#define UART_FIFOMODE_ENABLE        USART_CR1_FIFOEN  /*!< FIFO mode enable  */

+/**

+  * @}

+  */

+

+/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level

+  * @brief    UART TXFIFO threshold level

+  * @{

+  */

+#define UART_TXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< TXFIFO reaches 1/8 of its depth */

+#define UART_TXFIFO_THRESHOLD_1_4   USART_CR3_TXFTCFG_0                       /*!< TXFIFO reaches 1/4 of its depth */

+#define UART_TXFIFO_THRESHOLD_1_2   USART_CR3_TXFTCFG_1                       /*!< TXFIFO reaches 1/2 of its depth */

+#define UART_TXFIFO_THRESHOLD_3_4   (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */

+#define UART_TXFIFO_THRESHOLD_7_8   USART_CR3_TXFTCFG_2                       /*!< TXFIFO reaches 7/8 of its depth */

+#define UART_TXFIFO_THRESHOLD_8_8   (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty            */

+/**

+  * @}

+  */

+

+/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level

+  * @brief    UART RXFIFO threshold level

+  * @{

+  */

+#define UART_RXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< RXFIFO FIFO reaches 1/8 of its depth */

+#define UART_RXFIFO_THRESHOLD_1_4   USART_CR3_RXFTCFG_0                       /*!< RXFIFO FIFO reaches 1/4 of its depth */

+#define UART_RXFIFO_THRESHOLD_1_2   USART_CR3_RXFTCFG_1                       /*!< RXFIFO FIFO reaches 1/2 of its depth */

+#define UART_RXFIFO_THRESHOLD_3_4   (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */

+#define UART_RXFIFO_THRESHOLD_7_8   USART_CR3_RXFTCFG_2                       /*!< RXFIFO FIFO reaches 7/8 of its depth */

+#define UART_RXFIFO_THRESHOLD_8_8   (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full             */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macros -----------------------------------------------------------*/

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup UARTEx_Exported_Functions

+  * @{

+  */

+

+/** @addtogroup UARTEx_Exported_Functions_Group1

+  * @{

+  */

+

+/* Initialization and de-initialization functions  ****************************/

+HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime,

+                                   uint32_t DeassertionTime);

+

+/**

+  * @}

+  */

+

+/** @addtogroup UARTEx_Exported_Functions_Group2

+  * @{

+  */

+

+void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart);

+

+void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart);

+void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart);

+

+/**

+  * @}

+  */

+

+/** @addtogroup UARTEx_Exported_Functions_Group3

+  * @{

+  */

+

+/* Peripheral Control functions  **********************************************/

+HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection);

+HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart);

+HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart);

+

+HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength);

+

+HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart);

+HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart);

+HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);

+HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup UARTEx_Private_Macros UARTEx Private Macros

+  * @{

+  */

+

+/** @brief  Report the UART clock source.

+  * @param  __HANDLE__ specifies the UART Handle.

+  * @param  __CLOCKSOURCE__ output variable.

+  * @retval UART clocking source, written in __CLOCKSOURCE__.

+  */

+#if defined(UART9) && defined(USART10)

+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \

+  do {                                                        \

+    if((__HANDLE__)->Instance == USART1)                      \

+    {                                                         \

+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \

+      {                                                       \

+        case RCC_USART1CLKSOURCE_D2PCLK2:                     \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \

+          break;                                              \

+        case RCC_USART1CLKSOURCE_PLL2:                        \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \

+          break;                                              \

+        case RCC_USART1CLKSOURCE_PLL3:                        \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \

+          break;                                              \

+        case RCC_USART1CLKSOURCE_HSI:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_USART1CLKSOURCE_CSI:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_USART1CLKSOURCE_LSE:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if((__HANDLE__)->Instance == USART2)                 \

+    {                                                         \

+      switch(__HAL_RCC_GET_USART2_SOURCE())                   \

+      {                                                       \

+        case RCC_USART2CLKSOURCE_D2PCLK1:                     \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \

+          break;                                              \

+        case RCC_USART2CLKSOURCE_PLL2:                        \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \

+          break;                                              \

+        case RCC_USART2CLKSOURCE_PLL3:                        \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \

+          break;                                              \

+        case RCC_USART2CLKSOURCE_HSI:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_USART2CLKSOURCE_CSI:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_USART2CLKSOURCE_LSE:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if((__HANDLE__)->Instance == USART3)                 \

+    {                                                         \

+      switch(__HAL_RCC_GET_USART3_SOURCE())                   \

+      {                                                       \

+        case RCC_USART3CLKSOURCE_D2PCLK1:                     \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \

+          break;                                              \

+        case RCC_USART3CLKSOURCE_PLL2:                        \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \

+          break;                                              \

+        case RCC_USART3CLKSOURCE_PLL3:                        \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \

+          break;                                              \

+        case RCC_USART3CLKSOURCE_HSI:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_USART3CLKSOURCE_CSI:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_USART3CLKSOURCE_LSE:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if((__HANDLE__)->Instance == UART4)                  \

+    {                                                         \

+      switch(__HAL_RCC_GET_UART4_SOURCE())                    \

+      {                                                       \

+        case RCC_UART4CLKSOURCE_D2PCLK1:                      \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \

+          break;                                              \

+        case RCC_UART4CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \

+          break;                                              \

+        case RCC_UART4CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \

+          break;                                              \

+        case RCC_UART4CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_UART4CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_UART4CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if ((__HANDLE__)->Instance == UART5)                 \

+    {                                                         \

+      switch(__HAL_RCC_GET_UART5_SOURCE())                    \

+      {                                                       \

+        case RCC_UART5CLKSOURCE_D2PCLK1:                      \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \

+          break;                                              \

+        case RCC_UART5CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \

+          break;                                              \

+        case RCC_UART5CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \

+          break;                                              \

+        case RCC_UART5CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_UART5CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_UART5CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if((__HANDLE__)->Instance == USART6)                 \

+    {                                                         \

+      switch(__HAL_RCC_GET_USART6_SOURCE())                   \

+      {                                                       \

+        case RCC_USART6CLKSOURCE_D2PCLK2:                     \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \

+          break;                                              \

+        case RCC_USART6CLKSOURCE_PLL2:                        \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \

+          break;                                              \

+        case RCC_USART6CLKSOURCE_PLL3:                        \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \

+          break;                                              \

+        case RCC_USART6CLKSOURCE_HSI:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_USART6CLKSOURCE_CSI:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_USART6CLKSOURCE_LSE:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if((__HANDLE__)->Instance == UART7)                  \

+    {                                                         \

+      switch(__HAL_RCC_GET_UART7_SOURCE())                    \

+      {                                                       \

+        case RCC_UART7CLKSOURCE_D2PCLK1:                      \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \

+          break;                                              \

+        case RCC_UART7CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \

+          break;                                              \

+        case RCC_UART7CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \

+          break;                                              \

+        case RCC_UART7CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_UART7CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_UART7CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if((__HANDLE__)->Instance == UART8)                  \

+    {                                                         \

+      switch(__HAL_RCC_GET_UART8_SOURCE())                    \

+      {                                                       \

+        case RCC_UART8CLKSOURCE_D2PCLK1:                      \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \

+          break;                                              \

+        case RCC_UART8CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \

+          break;                                              \

+        case RCC_UART8CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \

+          break;                                              \

+        case RCC_UART8CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_UART8CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_UART8CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if((__HANDLE__)->Instance == UART9)                  \

+    {                                                         \

+      switch(__HAL_RCC_GET_UART9_SOURCE())                    \

+      {                                                       \

+        case RCC_UART9CLKSOURCE_D2PCLK2:                      \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \

+          break;                                              \

+        case RCC_UART9CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \

+          break;                                              \

+        case RCC_UART9CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \

+          break;                                              \

+        case RCC_UART9CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_UART9CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_UART9CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if((__HANDLE__)->Instance == USART10)                \

+    {                                                         \

+      switch(__HAL_RCC_GET_USART10_SOURCE())                  \

+      {                                                       \

+        case RCC_USART10CLKSOURCE_D2PCLK2:                    \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \

+          break;                                              \

+        case RCC_USART10CLKSOURCE_PLL2:                       \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \

+          break;                                              \

+        case RCC_USART10CLKSOURCE_PLL3:                       \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \

+          break;                                              \

+        case RCC_USART10CLKSOURCE_HSI:                        \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_USART10CLKSOURCE_CSI:                        \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_USART10CLKSOURCE_LSE:                        \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if((__HANDLE__)->Instance == LPUART1)                \

+    {                                                         \

+      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \

+      {                                                       \

+        case RCC_LPUART1CLKSOURCE_D3PCLK1:                    \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D3PCLK1;       \

+          break;                                              \

+        case RCC_LPUART1CLKSOURCE_PLL2:                       \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \

+          break;                                              \

+        case RCC_LPUART1CLKSOURCE_PLL3:                       \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \

+          break;                                              \

+        case RCC_LPUART1CLKSOURCE_HSI:                        \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_LPUART1CLKSOURCE_CSI:                        \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_LPUART1CLKSOURCE_LSE:                        \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else                                                      \

+    {                                                         \

+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \

+    }                                                         \

+  } while(0U)

+#else

+#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \

+  do {                                                        \

+    if((__HANDLE__)->Instance == USART1)                      \

+    {                                                         \

+      switch(__HAL_RCC_GET_USART1_SOURCE())                   \

+      {                                                       \

+        case RCC_USART1CLKSOURCE_D2PCLK2:                     \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \

+          break;                                              \

+        case RCC_USART1CLKSOURCE_PLL2:                        \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \

+          break;                                              \

+        case RCC_USART1CLKSOURCE_PLL3:                        \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \

+          break;                                              \

+        case RCC_USART1CLKSOURCE_HSI:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_USART1CLKSOURCE_CSI:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_USART1CLKSOURCE_LSE:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if((__HANDLE__)->Instance == USART2)                 \

+    {                                                         \

+      switch(__HAL_RCC_GET_USART2_SOURCE())                   \

+      {                                                       \

+        case RCC_USART2CLKSOURCE_D2PCLK1:                     \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \

+          break;                                              \

+        case RCC_USART2CLKSOURCE_PLL2:                        \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \

+          break;                                              \

+        case RCC_USART2CLKSOURCE_PLL3:                        \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \

+          break;                                              \

+        case RCC_USART2CLKSOURCE_HSI:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_USART2CLKSOURCE_CSI:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_USART2CLKSOURCE_LSE:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if((__HANDLE__)->Instance == USART3)                 \

+    {                                                         \

+      switch(__HAL_RCC_GET_USART3_SOURCE())                   \

+      {                                                       \

+        case RCC_USART3CLKSOURCE_D2PCLK1:                     \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \

+          break;                                              \

+        case RCC_USART3CLKSOURCE_PLL2:                        \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \

+          break;                                              \

+        case RCC_USART3CLKSOURCE_PLL3:                        \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \

+          break;                                              \

+        case RCC_USART3CLKSOURCE_HSI:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_USART3CLKSOURCE_CSI:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_USART3CLKSOURCE_LSE:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if((__HANDLE__)->Instance == UART4)                  \

+    {                                                         \

+      switch(__HAL_RCC_GET_UART4_SOURCE())                    \

+      {                                                       \

+        case RCC_UART4CLKSOURCE_D2PCLK1:                      \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \

+          break;                                              \

+        case RCC_UART4CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \

+          break;                                              \

+        case RCC_UART4CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \

+          break;                                              \

+        case RCC_UART4CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_UART4CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_UART4CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if ((__HANDLE__)->Instance == UART5)                 \

+    {                                                         \

+      switch(__HAL_RCC_GET_UART5_SOURCE())                    \

+      {                                                       \

+        case RCC_UART5CLKSOURCE_D2PCLK1:                      \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \

+          break;                                              \

+        case RCC_UART5CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \

+          break;                                              \

+        case RCC_UART5CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \

+          break;                                              \

+        case RCC_UART5CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_UART5CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_UART5CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if((__HANDLE__)->Instance == USART6)                 \

+    {                                                         \

+      switch(__HAL_RCC_GET_USART6_SOURCE())                   \

+      {                                                       \

+        case RCC_USART6CLKSOURCE_D2PCLK2:                     \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK2;       \

+          break;                                              \

+        case RCC_USART6CLKSOURCE_PLL2:                        \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \

+          break;                                              \

+        case RCC_USART6CLKSOURCE_PLL3:                        \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \

+          break;                                              \

+        case RCC_USART6CLKSOURCE_HSI:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_USART6CLKSOURCE_CSI:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_USART6CLKSOURCE_LSE:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if((__HANDLE__)->Instance == UART7)                  \

+    {                                                         \

+      switch(__HAL_RCC_GET_UART7_SOURCE())                    \

+      {                                                       \

+        case RCC_UART7CLKSOURCE_D2PCLK1:                      \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \

+          break;                                              \

+        case RCC_UART7CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \

+          break;                                              \

+        case RCC_UART7CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \

+          break;                                              \

+        case RCC_UART7CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_UART7CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_UART7CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if((__HANDLE__)->Instance == UART8)                  \

+    {                                                         \

+      switch(__HAL_RCC_GET_UART8_SOURCE())                    \

+      {                                                       \

+        case RCC_UART8CLKSOURCE_D2PCLK1:                      \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D2PCLK1;       \

+          break;                                              \

+        case RCC_UART8CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \

+          break;                                              \

+        case RCC_UART8CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \

+          break;                                              \

+        case RCC_UART8CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_UART8CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_UART8CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else if((__HANDLE__)->Instance == LPUART1)                \

+    {                                                         \

+      switch(__HAL_RCC_GET_LPUART1_SOURCE())                  \

+      {                                                       \

+        case RCC_LPUART1CLKSOURCE_D3PCLK1:                    \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_D3PCLK1;       \

+          break;                                              \

+        case RCC_LPUART1CLKSOURCE_PLL2:                       \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL2;          \

+          break;                                              \

+        case RCC_LPUART1CLKSOURCE_PLL3:                       \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_PLL3;          \

+          break;                                              \

+        case RCC_LPUART1CLKSOURCE_HSI:                        \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_HSI;           \

+          break;                                              \

+        case RCC_LPUART1CLKSOURCE_CSI:                        \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_CSI;           \

+          break;                                              \

+        case RCC_LPUART1CLKSOURCE_LSE:                        \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_LSE;           \

+          break;                                              \

+        default:                                              \

+          (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;     \

+          break;                                              \

+      }                                                       \

+    }                                                         \

+    else                                                      \

+    {                                                         \

+      (__CLOCKSOURCE__) = UART_CLOCKSOURCE_UNDEFINED;         \

+    }                                                         \

+  } while(0U)

+#endif  /* UART9 && USART10 */

+

+/** @brief  Report the UART mask to apply to retrieve the received data

+  *         according to the word length and to the parity bits activation.

+  * @note   If PCE = 1, the parity bit is not included in the data extracted

+  *         by the reception API().

+  *         This masking operation is not carried out in the case of

+  *         DMA transfers.

+  * @param  __HANDLE__ specifies the UART Handle.

+  * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field.

+  */

+#define UART_MASK_COMPUTATION(__HANDLE__)                             \

+  do {                                                                \

+    if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B)          \

+    {                                                                 \

+      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \

+      {                                                               \

+        (__HANDLE__)->Mask = 0x01FFU ;                                \

+      }                                                               \

+      else                                                            \

+      {                                                               \

+        (__HANDLE__)->Mask = 0x00FFU ;                                \

+      }                                                               \

+    }                                                                 \

+    else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B)     \

+    {                                                                 \

+      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \

+      {                                                               \

+        (__HANDLE__)->Mask = 0x00FFU ;                                \

+      }                                                               \

+      else                                                            \

+      {                                                               \

+        (__HANDLE__)->Mask = 0x007FU ;                                \

+      }                                                               \

+    }                                                                 \

+    else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B)     \

+    {                                                                 \

+      if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE)              \

+      {                                                               \

+        (__HANDLE__)->Mask = 0x007FU ;                                \

+      }                                                               \

+      else                                                            \

+      {                                                               \

+        (__HANDLE__)->Mask = 0x003FU ;                                \

+      }                                                               \

+    }                                                                 \

+    else                                                              \

+    {                                                                 \

+      (__HANDLE__)->Mask = 0x0000U;                                   \

+    }                                                                 \

+  } while(0U)

+

+/**

+  * @brief Ensure that UART frame length is valid.

+  * @param __LENGTH__ UART frame length.

+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

+  */

+#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \

+                                         ((__LENGTH__) == UART_WORDLENGTH_8B) || \

+                                         ((__LENGTH__) == UART_WORDLENGTH_9B))

+

+/**

+  * @brief Ensure that UART wake-up address length is valid.

+  * @param __ADDRESS__ UART wake-up address length.

+  * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid)

+  */

+#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \

+                                                   ((__ADDRESS__) == UART_ADDRESS_DETECT_7B))

+

+/**

+  * @brief Ensure that UART TXFIFO threshold level is valid.

+  * @param __THRESHOLD__ UART TXFIFO threshold level.

+  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

+  */

+#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \

+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \

+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \

+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \

+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \

+                                                 ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8))

+

+/**

+  * @brief Ensure that UART RXFIFO threshold level is valid.

+  * @param __THRESHOLD__ UART RXFIFO threshold level.

+  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

+  */

+#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \

+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \

+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \

+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \

+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \

+                                                 ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8))

+

+/**

+  * @}

+  */

+

+/* Private functions ---------------------------------------------------------*/

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_UART_EX_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_usart.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_usart.h
new file mode 100644
index 0000000000..2a5682a0f2
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_usart.h
@@ -0,0 +1,1181 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_usart.h

+  * @author  MCD Application Team

+  * @brief   Header file of USART HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_USART_H

+#define STM32H7xx_HAL_USART_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup USART

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup USART_Exported_Types USART Exported Types

+  * @{

+  */

+

+/**

+  * @brief USART Init Structure definition

+  */

+typedef struct

+{

+  uint32_t BaudRate;                  /*!< This member configures the Usart communication baud rate.

+                                           The baud rate is computed using the following formula:

+                                              Baud Rate Register[15:4] = ((2 * fclk_pres) / ((huart->Init.BaudRate)))[15:4]

+                                              Baud Rate Register[3]    = 0

+                                              Baud Rate Register[2:0]  =  (((2 * fclk_pres) / ((huart->Init.BaudRate)))[3:0]) >> 1

+                                              where fclk_pres is the USART input clock frequency (fclk) divided by a prescaler.

+                                           @note  Oversampling by 8 is systematically applied to achieve high baud rates. */

+

+  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.

+                                           This parameter can be a value of @ref USARTEx_Word_Length. */

+

+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.

+                                           This parameter can be a value of @ref USART_Stop_Bits. */

+

+  uint32_t Parity;                   /*!< Specifies the parity mode.

+                                           This parameter can be a value of @ref USART_Parity

+                                           @note When parity is enabled, the computed parity is inserted

+                                                 at the MSB position of the transmitted data (9th bit when

+                                                 the word length is set to 9 data bits; 8th bit when the

+                                                 word length is set to 8 data bits). */

+

+  uint32_t Mode;                      /*!< Specifies whether the Receive or Transmit mode is enabled or disabled.

+                                           This parameter can be a value of @ref USART_Mode. */

+

+  uint32_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.

+                                           This parameter can be a value of @ref USART_Clock_Polarity. */

+

+  uint32_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.

+                                           This parameter can be a value of @ref USART_Clock_Phase. */

+

+  uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted

+                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.

+                                           This parameter can be a value of @ref USART_Last_Bit. */

+

+  uint32_t ClockPrescaler;            /*!< Specifies the prescaler value used to divide the USART clock source.

+                                           This parameter can be a value of @ref USART_ClockPrescaler. */

+} USART_InitTypeDef;

+

+/**

+  * @brief HAL USART State structures definition

+  */

+typedef enum

+{

+  HAL_USART_STATE_RESET             = 0x00U,    /*!< Peripheral is not initialized                  */

+  HAL_USART_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use       */

+  HAL_USART_STATE_BUSY              = 0x02U,    /*!< an internal process is ongoing                 */

+  HAL_USART_STATE_BUSY_TX           = 0x12U,    /*!< Data Transmission process is ongoing           */

+  HAL_USART_STATE_BUSY_RX           = 0x22U,    /*!< Data Reception process is ongoing              */

+  HAL_USART_STATE_BUSY_TX_RX        = 0x32U,    /*!< Data Transmission Reception process is ongoing */

+  HAL_USART_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                                  */

+  HAL_USART_STATE_ERROR             = 0x04U     /*!< Error                                          */

+} HAL_USART_StateTypeDef;

+

+/**

+  * @brief  USART clock sources definitions

+  */

+typedef enum

+{

+  USART_CLOCKSOURCE_D2PCLK1    = 0x00U,    /*!< Domain2 PCLK1 clock source */

+  USART_CLOCKSOURCE_D2PCLK2    = 0x01U,    /*!< Domain2 PCLK2 clock source */

+  USART_CLOCKSOURCE_PLL2       = 0x02U,    /*!< PLL2Q clock source         */

+  USART_CLOCKSOURCE_PLL3       = 0x04U,    /*!< PLL3Q clock source         */

+  USART_CLOCKSOURCE_HSI        = 0x08U,    /*!< HSI clock source           */

+  USART_CLOCKSOURCE_CSI        = 0x10U,    /*!< CSI clock source           */

+  USART_CLOCKSOURCE_LSE        = 0x20U,    /*!< LSE clock source           */

+  USART_CLOCKSOURCE_UNDEFINED  = 0x40U     /*!< Undefined clock source     */

+} USART_ClockSourceTypeDef;

+

+/**

+  * @brief  USART handle Structure definition

+  */

+typedef struct __USART_HandleTypeDef

+{

+  USART_TypeDef                 *Instance;               /*!< USART registers base address        */

+

+  USART_InitTypeDef             Init;                    /*!< USART communication parameters      */

+

+  uint8_t                       *pTxBuffPtr;             /*!< Pointer to USART Tx transfer Buffer */

+

+  uint16_t                      TxXferSize;              /*!< USART Tx Transfer size              */

+

+  __IO uint16_t                 TxXferCount;             /*!< USART Tx Transfer Counter           */

+

+  uint8_t                       *pRxBuffPtr;             /*!< Pointer to USART Rx transfer Buffer */

+

+  uint16_t                      RxXferSize;              /*!< USART Rx Transfer size              */

+

+  __IO uint16_t                 RxXferCount;             /*!< USART Rx Transfer Counter           */

+

+  uint16_t                      Mask;                    /*!< USART Rx RDR register mask          */

+

+  uint16_t                      NbRxDataToProcess;       /*!< Number of data to process during RX ISR execution */

+

+  uint16_t                      NbTxDataToProcess;       /*!< Number of data to process during TX ISR execution */

+

+  uint32_t                      SlaveMode;               /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value

+                                                              of @ref USARTEx_Slave_Mode */

+

+  uint32_t                      FifoMode;                /*!< Specifies if the FIFO mode will be used. This parameter can be a value

+                                                              of @ref USARTEx_FIFO_mode. */

+

+  void (*RxISR)(struct __USART_HandleTypeDef *husart);   /*!< Function pointer on Rx IRQ handler  */

+

+  void (*TxISR)(struct __USART_HandleTypeDef *husart);   /*!< Function pointer on Tx IRQ handler  */

+

+  DMA_HandleTypeDef             *hdmatx;                 /*!< USART Tx DMA Handle parameters      */

+

+  DMA_HandleTypeDef             *hdmarx;                 /*!< USART Rx DMA Handle parameters      */

+

+  HAL_LockTypeDef               Lock;                    /*!< Locking object                      */

+

+  __IO HAL_USART_StateTypeDef   State;                   /*!< USART communication state           */

+

+  __IO uint32_t                 ErrorCode;               /*!< USART Error code                    */

+

+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)

+  void (* TxHalfCpltCallback)(struct __USART_HandleTypeDef *husart);        /*!< USART Tx Half Complete Callback        */

+  void (* TxCpltCallback)(struct __USART_HandleTypeDef *husart);            /*!< USART Tx Complete Callback             */

+  void (* RxHalfCpltCallback)(struct __USART_HandleTypeDef *husart);        /*!< USART Rx Half Complete Callback        */

+  void (* RxCpltCallback)(struct __USART_HandleTypeDef *husart);            /*!< USART Rx Complete Callback             */

+  void (* TxRxCpltCallback)(struct __USART_HandleTypeDef *husart);          /*!< USART Tx Rx Complete Callback          */

+  void (* ErrorCallback)(struct __USART_HandleTypeDef *husart);             /*!< USART Error Callback                   */

+  void (* AbortCpltCallback)(struct __USART_HandleTypeDef *husart);         /*!< USART Abort Complete Callback          */

+  void (* RxFifoFullCallback)(struct __USART_HandleTypeDef *husart);        /*!< USART Rx Fifo Full Callback            */

+  void (* TxFifoEmptyCallback)(struct __USART_HandleTypeDef *husart);       /*!< USART Tx Fifo Empty Callback           */

+

+  void (* MspInitCallback)(struct __USART_HandleTypeDef *husart);           /*!< USART Msp Init callback                */

+  void (* MspDeInitCallback)(struct __USART_HandleTypeDef *husart);         /*!< USART Msp DeInit callback              */

+#endif  /* USE_HAL_USART_REGISTER_CALLBACKS */

+

+} USART_HandleTypeDef;

+

+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  HAL USART Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_USART_TX_HALFCOMPLETE_CB_ID         = 0x00U,    /*!< USART Tx Half Complete Callback ID        */

+  HAL_USART_TX_COMPLETE_CB_ID             = 0x01U,    /*!< USART Tx Complete Callback ID             */

+  HAL_USART_RX_HALFCOMPLETE_CB_ID         = 0x02U,    /*!< USART Rx Half Complete Callback ID        */

+  HAL_USART_RX_COMPLETE_CB_ID             = 0x03U,    /*!< USART Rx Complete Callback ID             */

+  HAL_USART_TX_RX_COMPLETE_CB_ID          = 0x04U,    /*!< USART Tx Rx Complete Callback ID          */

+  HAL_USART_ERROR_CB_ID                   = 0x05U,    /*!< USART Error Callback ID                   */

+  HAL_USART_ABORT_COMPLETE_CB_ID          = 0x06U,    /*!< USART Abort Complete Callback ID          */

+  HAL_USART_RX_FIFO_FULL_CB_ID            = 0x07U,    /*!< USART Rx Fifo Full Callback ID            */

+  HAL_USART_TX_FIFO_EMPTY_CB_ID           = 0x08U,    /*!< USART Tx Fifo Empty Callback ID           */

+

+  HAL_USART_MSPINIT_CB_ID                 = 0x09U,    /*!< USART MspInit callback ID                 */

+  HAL_USART_MSPDEINIT_CB_ID               = 0x0AU     /*!< USART MspDeInit callback ID               */

+

+} HAL_USART_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL USART Callback pointer definition

+  */

+typedef  void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart);  /*!< pointer to an USART callback function */

+

+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup USART_Exported_Constants USART Exported Constants

+  * @{

+  */

+

+/** @defgroup USART_Error_Definition   USART Error Definition

+  * @{

+  */

+#define HAL_USART_ERROR_NONE             ((uint32_t)0x00000000U)    /*!< No error                  */

+#define HAL_USART_ERROR_PE               ((uint32_t)0x00000001U)    /*!< Parity error              */

+#define HAL_USART_ERROR_NE               ((uint32_t)0x00000002U)    /*!< Noise error               */

+#define HAL_USART_ERROR_FE               ((uint32_t)0x00000004U)    /*!< Frame error               */

+#define HAL_USART_ERROR_ORE              ((uint32_t)0x00000008U)    /*!< Overrun error             */

+#define HAL_USART_ERROR_DMA              ((uint32_t)0x00000010U)    /*!< DMA transfer error        */

+#define HAL_USART_ERROR_UDR              ((uint32_t)0x00000020U)    /*!< SPI slave underrun error  */

+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)

+#define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U)    /*!< Invalid Callback error    */

+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */

+#define  HAL_USART_ERROR_RTO              ((uint32_t)0x00000080U)    /*!< Receiver Timeout error  */

+/**

+  * @}

+  */

+

+/** @defgroup USART_Stop_Bits  USART Number of Stop Bits

+  * @{

+  */

+#define USART_STOPBITS_0_5                   USART_CR2_STOP_0                     /*!< USART frame with 0.5 stop bit  */

+#define USART_STOPBITS_1                     0x00000000U                          /*!< USART frame with 1 stop bit    */

+#define USART_STOPBITS_1_5                  (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< USART frame with 1.5 stop bits */

+#define USART_STOPBITS_2                     USART_CR2_STOP_1                     /*!< USART frame with 2 stop bits   */

+/**

+  * @}

+  */

+

+/** @defgroup USART_Parity    USART Parity

+  * @{

+  */

+#define USART_PARITY_NONE                   0x00000000U                      /*!< No parity   */

+#define USART_PARITY_EVEN                   USART_CR1_PCE                    /*!< Even parity */

+#define USART_PARITY_ODD                    (USART_CR1_PCE | USART_CR1_PS)   /*!< Odd parity  */

+/**

+  * @}

+  */

+

+/** @defgroup USART_Mode   USART Mode

+  * @{

+  */

+#define USART_MODE_RX                       USART_CR1_RE                    /*!< RX mode        */

+#define USART_MODE_TX                       USART_CR1_TE                    /*!< TX mode        */

+#define USART_MODE_TX_RX                    (USART_CR1_TE |USART_CR1_RE)    /*!< RX and TX mode */

+/**

+  * @}

+  */

+

+/** @defgroup USART_Over_Sampling USART Over Sampling

+  * @{

+  */

+#define USART_OVERSAMPLING_16               0x00000000U         /*!< Oversampling by 16 */

+#define USART_OVERSAMPLING_8                USART_CR1_OVER8     /*!< Oversampling by 8  */

+/**

+  * @}

+  */

+

+/** @defgroup USART_Clock  USART Clock

+  * @{

+  */

+#define USART_CLOCK_DISABLE                 0x00000000U       /*!< USART clock disable */

+#define USART_CLOCK_ENABLE                  USART_CR2_CLKEN   /*!< USART clock enable  */

+/**

+  * @}

+  */

+

+/** @defgroup USART_Clock_Polarity  USART Clock Polarity

+  * @{

+  */

+#define USART_POLARITY_LOW                  0x00000000U      /*!< Driver enable signal is active high */

+#define USART_POLARITY_HIGH                 USART_CR2_CPOL   /*!< Driver enable signal is active low  */

+/**

+  * @}

+  */

+

+/** @defgroup USART_Clock_Phase   USART Clock Phase

+  * @{

+  */

+#define USART_PHASE_1EDGE                   0x00000000U      /*!< USART frame phase on first clock transition  */

+#define USART_PHASE_2EDGE                   USART_CR2_CPHA   /*!< USART frame phase on second clock transition */

+/**

+  * @}

+  */

+

+/** @defgroup USART_Last_Bit  USART Last Bit

+  * @{

+  */

+#define USART_LASTBIT_DISABLE               0x00000000U      /*!< USART frame last data bit clock pulse not output to SCLK pin */

+#define USART_LASTBIT_ENABLE                USART_CR2_LBCL   /*!< USART frame last data bit clock pulse output to SCLK pin     */

+/**

+  * @}

+  */

+

+/** @defgroup USART_ClockPrescaler  USART Clock Prescaler

+  * @{

+  */

+#define USART_PRESCALER_DIV1    0x00000000U  /*!< fclk_pres = fclk     */

+#define USART_PRESCALER_DIV2    0x00000001U  /*!< fclk_pres = fclk/2   */

+#define USART_PRESCALER_DIV4    0x00000002U  /*!< fclk_pres = fclk/4   */

+#define USART_PRESCALER_DIV6    0x00000003U  /*!< fclk_pres = fclk/6   */

+#define USART_PRESCALER_DIV8    0x00000004U  /*!< fclk_pres = fclk/8   */

+#define USART_PRESCALER_DIV10   0x00000005U  /*!< fclk_pres = fclk/10  */

+#define USART_PRESCALER_DIV12   0x00000006U  /*!< fclk_pres = fclk/12  */

+#define USART_PRESCALER_DIV16   0x00000007U  /*!< fclk_pres = fclk/16  */

+#define USART_PRESCALER_DIV32   0x00000008U  /*!< fclk_pres = fclk/32  */

+#define USART_PRESCALER_DIV64   0x00000009U  /*!< fclk_pres = fclk/64  */

+#define USART_PRESCALER_DIV128  0x0000000AU  /*!< fclk_pres = fclk/128 */

+#define USART_PRESCALER_DIV256  0x0000000BU  /*!< fclk_pres = fclk/256 */

+

+/**

+  * @}

+  */

+

+/** @defgroup USART_Request_Parameters  USART Request Parameters

+  * @{

+  */

+#define USART_RXDATA_FLUSH_REQUEST        USART_RQR_RXFRQ        /*!< Receive Data flush Request  */

+#define USART_TXDATA_FLUSH_REQUEST        USART_RQR_TXFRQ        /*!< Transmit data flush Request */

+/**

+  * @}

+  */

+

+/** @defgroup USART_Flags      USART Flags

+  *        Elements values convention: 0xXXXX

+  *           - 0xXXXX  : Flag mask in the ISR register

+  * @{

+  */

+#define USART_FLAG_TXFT                     USART_ISR_TXFT          /*!< USART TXFIFO threshold flag                */

+#define USART_FLAG_RXFT                     USART_ISR_RXFT          /*!< USART RXFIFO threshold flag                */

+#define USART_FLAG_RXFF                     USART_ISR_RXFF          /*!< USART RXFIFO Full flag                     */

+#define USART_FLAG_TXFE                     USART_ISR_TXFE          /*!< USART TXFIFO Empty flag                    */

+#define USART_FLAG_REACK                    USART_ISR_REACK         /*!< USART receive enable acknowledge flag      */

+#define USART_FLAG_TEACK                    USART_ISR_TEACK         /*!< USART transmit enable acknowledge flag     */

+#define USART_FLAG_BUSY                     USART_ISR_BUSY          /*!< USART busy flag                            */

+#define USART_FLAG_UDR                      USART_ISR_UDR           /*!< SPI slave underrun error flag              */

+#define USART_FLAG_TXE                      USART_ISR_TXE_TXFNF     /*!< USART transmit data register empty         */

+#define USART_FLAG_TXFNF                    USART_ISR_TXE_TXFNF     /*!< USART TXFIFO not full                      */

+#define USART_FLAG_RTOF                     USART_ISR_RTOF          /*!< USART receiver timeout flag                */

+#define USART_FLAG_TC                       USART_ISR_TC            /*!< USART transmission complete                */

+#define USART_FLAG_RXNE                     USART_ISR_RXNE_RXFNE    /*!< USART read data register not empty         */

+#define USART_FLAG_RXFNE                    USART_ISR_RXNE_RXFNE    /*!< USART RXFIFO not empty                     */

+#define USART_FLAG_IDLE                     USART_ISR_IDLE          /*!< USART idle flag                            */

+#define USART_FLAG_ORE                      USART_ISR_ORE           /*!< USART overrun error                        */

+#define USART_FLAG_NE                       USART_ISR_NE            /*!< USART noise error                          */

+#define USART_FLAG_FE                       USART_ISR_FE            /*!< USART frame error                          */

+#define USART_FLAG_PE                       USART_ISR_PE            /*!< USART parity error                         */

+/**

+  * @}

+  */

+

+/** @defgroup USART_Interrupt_definition USART Interrupts Definition

+  *        Elements values convention: 0000ZZZZ0XXYYYYYb

+  *           - YYYYY  : Interrupt source position in the XX register (5bits)

+  *           - XX  : Interrupt source register (2bits)

+  *                 - 01: CR1 register

+  *                 - 10: CR2 register

+  *                 - 11: CR3 register

+  *           - ZZZZ  : Flag position in the ISR register(4bits)

+  * @{

+  */

+

+#define USART_IT_PE                          0x0028U     /*!< USART parity error interruption                 */

+#define USART_IT_TXE                         0x0727U     /*!< USART transmit data register empty interruption */

+#define USART_IT_TXFNF                       0x0727U     /*!< USART TX FIFO not full interruption             */

+#define USART_IT_TC                          0x0626U     /*!< USART transmission complete interruption        */

+#define USART_IT_RXNE                        0x0525U     /*!< USART read data register not empty interruption */

+#define USART_IT_RXFNE                       0x0525U     /*!< USART RXFIFO not empty interruption             */

+#define USART_IT_IDLE                        0x0424U     /*!< USART idle interruption                         */

+#define USART_IT_ERR                         0x0060U     /*!< USART error interruption                        */

+#define USART_IT_ORE                         0x0300U     /*!< USART overrun error interruption                */

+#define USART_IT_NE                          0x0200U     /*!< USART noise error interruption                  */

+#define USART_IT_FE                          0x0100U     /*!< USART frame error interruption                  */

+#define USART_IT_RXFF                        0x183FU     /*!< USART RXFIFO full interruption                  */

+#define USART_IT_TXFE                        0x173EU     /*!< USART TXFIFO empty interruption                 */

+#define USART_IT_RXFT                        0x1A7CU     /*!< USART RXFIFO threshold reached interruption     */

+#define USART_IT_TXFT                        0x1B77U     /*!< USART TXFIFO threshold reached interruption     */

+

+/**

+  * @}

+  */

+

+/** @defgroup USART_IT_CLEAR_Flags    USART Interruption Clear Flags

+  * @{

+  */

+#define USART_CLEAR_PEF                       USART_ICR_PECF            /*!< Parity Error Clear Flag             */

+#define USART_CLEAR_FEF                       USART_ICR_FECF            /*!< Framing Error Clear Flag            */

+#define USART_CLEAR_NEF                       USART_ICR_NECF            /*!< Noise Error detected Clear Flag     */

+#define USART_CLEAR_OREF                      USART_ICR_ORECF           /*!< OverRun Error Clear Flag            */

+#define USART_CLEAR_IDLEF                     USART_ICR_IDLECF          /*!< IDLE line detected Clear Flag       */

+#define USART_CLEAR_TCF                       USART_ICR_TCCF            /*!< Transmission Complete Clear Flag    */

+#define USART_CLEAR_UDRF                      USART_ICR_UDRCF           /*!< SPI slave underrun error Clear Flag */

+#define USART_CLEAR_TXFECF                    USART_ICR_TXFECF          /*!< TXFIFO Empty Clear Flag             */

+#define USART_CLEAR_RTOF                      USART_ICR_RTOCF           /*!< USART receiver timeout clear flag  */

+/**

+  * @}

+  */

+

+/** @defgroup USART_Interruption_Mask    USART Interruption Flags Mask

+  * @{

+  */

+#define USART_IT_MASK                             0x001FU     /*!< USART interruptions flags mask */

+#define USART_CR_MASK                             0x00E0U     /*!< USART control register mask */

+#define USART_CR_POS                              5U          /*!< USART control register position */

+#define USART_ISR_MASK                            0x1F00U     /*!< USART ISR register mask         */

+#define USART_ISR_POS                             8U          /*!< USART ISR register position     */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macros -----------------------------------------------------------*/

+/** @defgroup USART_Exported_Macros USART Exported Macros

+  * @{

+  */

+

+/** @brief Reset USART handle state.

+  * @param  __HANDLE__ USART handle.

+  * @retval None

+  */

+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)

+#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  do{                                            \

+                                                        (__HANDLE__)->State = HAL_USART_STATE_RESET; \

+                                                        (__HANDLE__)->MspInitCallback = NULL;        \

+                                                        (__HANDLE__)->MspDeInitCallback = NULL;      \

+                                                      } while(0U)

+#else

+#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_USART_STATE_RESET)

+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */

+

+/** @brief  Check whether the specified USART flag is set or not.

+  * @param  __HANDLE__ specifies the USART Handle

+  * @param  __FLAG__ specifies the flag to check.

+  *        This parameter can be one of the following values:

+  *            @arg @ref USART_FLAG_TXFT  TXFIFO threshold flag

+  *            @arg @ref USART_FLAG_RXFT  RXFIFO threshold flag

+  *            @arg @ref USART_FLAG_RXFF  RXFIFO Full flag

+  *            @arg @ref USART_FLAG_TXFE  TXFIFO Empty flag

+  *            @arg @ref USART_FLAG_REACK Receive enable acknowledge flag

+  *            @arg @ref USART_FLAG_TEACK Transmit enable acknowledge flag

+  *            @arg @ref USART_FLAG_BUSY  Busy flag

+  *            @arg @ref USART_FLAG_UDR   SPI slave underrun error flag

+  *            @arg @ref USART_FLAG_TXE   Transmit data register empty flag

+  *            @arg @ref USART_FLAG_TXFNF TXFIFO not full flag

+  *            @arg @ref USART_FLAG_TC    Transmission Complete flag

+  *            @arg @ref USART_FLAG_RXNE  Receive data register not empty flag

+  *            @arg @ref USART_FLAG_RXFNE RXFIFO not empty flag

+  *            @arg @ref USART_FLAG_RTOF  Receiver Timeout flag

+  *            @arg @ref USART_FLAG_IDLE  Idle Line detection flag

+  *            @arg @ref USART_FLAG_ORE   OverRun Error flag

+  *            @arg @ref USART_FLAG_NE    Noise Error flag

+  *            @arg @ref USART_FLAG_FE    Framing Error flag

+  *            @arg @ref USART_FLAG_PE    Parity Error flag

+  * @retval The new state of __FLAG__ (TRUE or FALSE).

+  */

+#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))

+

+/** @brief  Clear the specified USART pending flag.

+  * @param  __HANDLE__ specifies the USART Handle.

+  * @param  __FLAG__ specifies the flag to check.

+  *          This parameter can be any combination of the following values:

+  *            @arg @ref USART_CLEAR_PEF      Parity Error Clear Flag

+  *            @arg @ref USART_CLEAR_FEF      Framing Error Clear Flag

+  *            @arg @ref USART_CLEAR_NEF      Noise detected Clear Flag

+  *            @arg @ref USART_CLEAR_OREF     Overrun Error Clear Flag

+  *            @arg @ref USART_CLEAR_IDLEF    IDLE line detected Clear Flag

+  *            @arg @ref USART_CLEAR_TXFECF   TXFIFO empty clear Flag

+  *            @arg @ref USART_CLEAR_TCF      Transmission Complete Clear Flag

+  *            @arg @ref USART_CLEAR_RTOF     Receiver Timeout clear flag

+  *            @arg @ref USART_CLEAR_UDRF     SPI slave underrun error Clear Flag

+  * @retval None

+  */

+#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))

+

+/** @brief  Clear the USART PE pending flag.

+  * @param  __HANDLE__ specifies the USART Handle.

+  * @retval None

+  */

+#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_PEF)

+

+/** @brief  Clear the USART FE pending flag.

+  * @param  __HANDLE__ specifies the USART Handle.

+  * @retval None

+  */

+#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_FEF)

+

+/** @brief  Clear the USART NE pending flag.

+  * @param  __HANDLE__ specifies the USART Handle.

+  * @retval None

+  */

+#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__)  __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_NEF)

+

+/** @brief  Clear the USART ORE pending flag.

+  * @param  __HANDLE__ specifies the USART Handle.

+  * @retval None

+  */

+#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_OREF)

+

+/** @brief  Clear the USART IDLE pending flag.

+  * @param  __HANDLE__ specifies the USART Handle.

+  * @retval None

+  */

+#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_IDLEF)

+

+/** @brief  Clear the USART TX FIFO empty clear flag.

+  * @param  __HANDLE__ specifies the USART Handle.

+  * @retval None

+  */

+#define __HAL_USART_CLEAR_TXFECF(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_TXFECF)

+

+/** @brief  Clear SPI slave underrun error flag.

+  * @param  __HANDLE__ specifies the USART Handle.

+  * @retval None

+  */

+#define __HAL_USART_CLEAR_UDRFLAG(__HANDLE__)   __HAL_USART_CLEAR_FLAG((__HANDLE__), USART_CLEAR_UDRF)

+

+/** @brief  Enable the specified USART interrupt.

+  * @param  __HANDLE__ specifies the USART Handle.

+  * @param  __INTERRUPT__ specifies the USART interrupt source to enable.

+  *          This parameter can be one of the following values:

+  *            @arg @ref USART_IT_RXFF  RXFIFO Full interrupt

+  *            @arg @ref USART_IT_TXFE  TXFIFO Empty interrupt

+  *            @arg @ref USART_IT_RXFT  RXFIFO threshold interrupt

+  *            @arg @ref USART_IT_TXFT  TXFIFO threshold interrupt

+  *            @arg @ref USART_IT_TXE   Transmit Data Register empty interrupt

+  *            @arg @ref USART_IT_TXFNF TX FIFO not full interrupt

+  *            @arg @ref USART_IT_TC    Transmission complete interrupt

+  *            @arg @ref USART_IT_RXNE  Receive Data register not empty interrupt

+  *            @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt

+  *            @arg @ref USART_IT_IDLE  Idle line detection interrupt

+  *            @arg @ref USART_IT_PE    Parity Error interrupt

+  *            @arg @ref USART_IT_ERR   Error interrupt(Frame error, noise error, overrun error)

+  * @retval None

+  */

+#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \

+                                                            ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \

+                                                            ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))))

+

+/** @brief  Disable the specified USART interrupt.

+  * @param  __HANDLE__ specifies the USART Handle.

+  * @param  __INTERRUPT__ specifies the USART interrupt source to disable.

+  *          This parameter can be one of the following values:

+  *            @arg @ref USART_IT_RXFF  RXFIFO Full interrupt

+  *            @arg @ref USART_IT_TXFE  TXFIFO Empty interrupt

+  *            @arg @ref USART_IT_RXFT  RXFIFO threshold interrupt

+  *            @arg @ref USART_IT_TXFT  TXFIFO threshold interrupt

+  *            @arg @ref USART_IT_TXE   Transmit Data Register empty interrupt

+  *            @arg @ref USART_IT_TXFNF TX FIFO not full interrupt

+  *            @arg @ref USART_IT_TC    Transmission complete interrupt

+  *            @arg @ref USART_IT_RXNE  Receive Data register not empty interrupt

+  *            @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt

+  *            @arg @ref USART_IT_IDLE  Idle line detection interrupt

+  *            @arg @ref USART_IT_PE    Parity Error interrupt

+  *            @arg @ref USART_IT_ERR   Error interrupt(Frame error, noise error, overrun error)

+  * @retval None

+  */

+#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \

+                                                            ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \

+                                                            ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))))

+

+

+/** @brief  Check whether the specified USART interrupt has occurred or not.

+  * @param  __HANDLE__ specifies the USART Handle.

+  * @param  __INTERRUPT__ specifies the USART interrupt source to check.

+  *          This parameter can be one of the following values:

+  *            @arg @ref USART_IT_RXFF  RXFIFO Full interrupt

+  *            @arg @ref USART_IT_TXFE  TXFIFO Empty interrupt

+  *            @arg @ref USART_IT_RXFT  RXFIFO threshold interrupt

+  *            @arg @ref USART_IT_TXFT  TXFIFO threshold interrupt

+  *            @arg @ref USART_IT_TXE   Transmit Data Register empty interrupt

+  *            @arg @ref USART_IT_TXFNF TX FIFO not full interrupt

+  *            @arg @ref USART_IT_TC    Transmission complete interrupt

+  *            @arg @ref USART_IT_RXNE  Receive Data register not empty interrupt

+  *            @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt

+  *            @arg @ref USART_IT_IDLE  Idle line detection interrupt

+  *            @arg @ref USART_IT_ORE   OverRun Error interrupt

+  *            @arg @ref USART_IT_NE    Noise Error interrupt

+  *            @arg @ref USART_IT_FE    Framing Error interrupt

+  *            @arg @ref USART_IT_PE    Parity Error interrupt

+  * @retval The new state of __INTERRUPT__ (SET or RESET).

+  */

+#define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\

+                                                         & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET)

+

+/** @brief  Check whether the specified USART interrupt source is enabled or not.

+  * @param  __HANDLE__ specifies the USART Handle.

+  * @param  __INTERRUPT__ specifies the USART interrupt source to check.

+  *          This parameter can be one of the following values:

+  *            @arg @ref USART_IT_RXFF  RXFIFO Full interrupt

+  *            @arg @ref USART_IT_TXFE  TXFIFO Empty interrupt

+  *            @arg @ref USART_IT_RXFT  RXFIFO threshold interrupt

+  *            @arg @ref USART_IT_TXFT  TXFIFO threshold interrupt

+  *            @arg @ref USART_IT_TXE   Transmit Data Register empty interrupt

+  *            @arg @ref USART_IT_TXFNF TX FIFO not full interrupt

+  *            @arg @ref USART_IT_TC    Transmission complete interrupt

+  *            @arg @ref USART_IT_RXNE  Receive Data register not empty interrupt

+  *            @arg @ref USART_IT_RXFNE RXFIFO not empty interrupt

+  *            @arg @ref USART_IT_IDLE  Idle line detection interrupt

+  *            @arg @ref USART_IT_ORE   OverRun Error interrupt

+  *            @arg @ref USART_IT_NE    Noise Error interrupt

+  *            @arg @ref USART_IT_FE    Framing Error interrupt

+  *            @arg @ref USART_IT_PE    Parity Error interrupt

+  * @retval The new state of __INTERRUPT__ (SET or RESET).

+  */

+#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \

+                                                                 (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \

+                                                                  (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK)))  != 0U) ? SET : RESET)

+

+

+/** @brief  Clear the specified USART ISR flag, in setting the proper ICR register flag.

+  * @param  __HANDLE__ specifies the USART Handle.

+  * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set

+  *                       to clear the corresponding interrupt.

+  *          This parameter can be one of the following values:

+  *            @arg @ref USART_CLEAR_PEF      Parity Error Clear Flag

+  *            @arg @ref USART_CLEAR_FEF      Framing Error Clear Flag

+  *            @arg @ref USART_CLEAR_NEF      Noise detected Clear Flag

+  *            @arg @ref USART_CLEAR_OREF     Overrun Error Clear Flag

+  *            @arg @ref USART_CLEAR_IDLEF    IDLE line detected Clear Flag

+  *            @arg @ref USART_CLEAR_RTOF     Receiver timeout clear flag

+  *            @arg @ref USART_CLEAR_TXFECF   TXFIFO empty clear Flag

+  *            @arg @ref USART_CLEAR_TCF      Transmission Complete Clear Flag

+  * @retval None

+  */

+#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))

+

+/** @brief  Set a specific USART request flag.

+  * @param  __HANDLE__ specifies the USART Handle.

+  * @param  __REQ__ specifies the request flag to set.

+  *          This parameter can be one of the following values:

+  *            @arg @ref USART_RXDATA_FLUSH_REQUEST Receive Data flush Request

+  *            @arg @ref USART_TXDATA_FLUSH_REQUEST Transmit data flush Request

+  *

+  * @retval None

+  */

+#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__)      ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))

+

+/** @brief  Enable the USART one bit sample method.

+  * @param  __HANDLE__ specifies the USART Handle.

+  * @retval None

+  */

+#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)

+

+/** @brief  Disable the USART one bit sample method.

+  * @param  __HANDLE__ specifies the USART Handle.

+  * @retval None

+  */

+#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT)

+

+/** @brief  Enable USART.

+  * @param  __HANDLE__ specifies the USART Handle.

+  * @retval None

+  */

+#define __HAL_USART_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)

+

+/** @brief  Disable USART.

+  * @param  __HANDLE__ specifies the USART Handle.

+  * @retval None

+  */

+#define __HAL_USART_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)

+

+/**

+  * @}

+  */

+

+/* Private macros --------------------------------------------------------*/

+/** @defgroup USART_Private_Macros   USART Private Macros

+  * @{

+  */

+

+/** @brief  Get USART clock division factor from clock prescaler value.

+  * @param  __CLOCKPRESCALER__ USART prescaler value.

+  * @retval USART clock division factor

+  */

+#define USART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \

+  (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1)   ? 1U :       \

+   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2)   ? 2U :       \

+   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4)   ? 4U :       \

+   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6)   ? 6U :       \

+   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8)   ? 8U :       \

+   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10)  ? 10U :      \

+   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12)  ? 12U :      \

+   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16)  ? 16U :      \

+   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32)  ? 32U :      \

+   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64)  ? 64U :      \

+   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U :     \

+   ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U)

+

+/** @brief  BRR division operation to set BRR register in 8-bit oversampling mode.

+  * @param  __PCLK__ USART clock.

+  * @param  __BAUD__ Baud rate set by the user.

+  * @param  __CLOCKPRESCALER__ UART prescaler value.

+  * @retval Division result

+  */

+#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)   (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\

+                                                                        + ((__BAUD__)/2U)) / (__BAUD__))

+

+/** @brief  Report the USART clock source.

+  * @param  __HANDLE__ specifies the USART Handle.

+  * @param  __CLOCKSOURCE__ output variable.

+  * @retval the USART clocking source, written in __CLOCKSOURCE__.

+  */

+#if defined(UART9) && defined(USART10)

+#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \

+  do {                                                         \

+    if((__HANDLE__)->Instance == USART1)                       \

+    {                                                          \

+      switch(__HAL_RCC_GET_USART1_SOURCE())                    \

+      {                                                        \

+        case RCC_USART1CLKSOURCE_D2PCLK2:                      \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK2;       \

+          break;                                               \

+        case RCC_USART1CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2;          \

+          break;                                               \

+        case RCC_USART1CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3;          \

+          break;                                               \

+        case RCC_USART1CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \

+          break;                                               \

+        case RCC_USART1CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI;           \

+          break;                                               \

+        case RCC_USART1CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \

+          break;                                               \

+        default:                                               \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \

+          break;                                               \

+      }                                                        \

+    }                                                          \

+    else if((__HANDLE__)->Instance == USART2)                  \

+    {                                                          \

+      switch(__HAL_RCC_GET_USART2_SOURCE())                    \

+      {                                                        \

+        case RCC_USART2CLKSOURCE_D2PCLK1:                      \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK1;       \

+          break;                                               \

+        case RCC_USART2CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2;          \

+          break;                                               \

+        case RCC_USART2CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3;          \

+          break;                                               \

+        case RCC_USART2CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \

+          break;                                               \

+        case RCC_USART2CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI;           \

+          break;                                               \

+        case RCC_USART2CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \

+          break;                                               \

+        default:                                               \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \

+          break;                                               \

+      }                                                        \

+    }                                                          \

+    else if((__HANDLE__)->Instance == USART3)                  \

+    {                                                          \

+      switch(__HAL_RCC_GET_USART3_SOURCE())                    \

+      {                                                        \

+        case RCC_USART3CLKSOURCE_D2PCLK1:                      \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK1;       \

+          break;                                               \

+        case RCC_USART3CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2;          \

+          break;                                               \

+        case RCC_USART3CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3;          \

+          break;                                               \

+        case RCC_USART3CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \

+          break;                                               \

+        case RCC_USART3CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI;           \

+          break;                                               \

+        case RCC_USART3CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \

+          break;                                               \

+        default:                                               \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \

+          break;                                               \

+      }                                                        \

+    }                                                          \

+    else if((__HANDLE__)->Instance == USART6)                  \

+    {                                                          \

+      switch(__HAL_RCC_GET_USART6_SOURCE())                    \

+      {                                                        \

+        case RCC_USART6CLKSOURCE_D2PCLK2:                      \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK2;       \

+          break;                                               \

+        case RCC_USART6CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2;          \

+          break;                                               \

+        case RCC_USART6CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3;          \

+          break;                                               \

+        case RCC_USART6CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \

+          break;                                               \

+        case RCC_USART6CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI;           \

+          break;                                               \

+        case RCC_USART6CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \

+          break;                                               \

+        default:                                               \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \

+          break;                                               \

+      }                                                        \

+    }                                                          \

+    else if((__HANDLE__)->Instance == USART10)                 \

+    {                                                          \

+      switch(__HAL_RCC_GET_USART10_SOURCE())                   \

+      {                                                        \

+        case RCC_USART10CLKSOURCE_D2PCLK2:                     \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK2;       \

+          break;                                               \

+        case RCC_USART10CLKSOURCE_PLL2:                        \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2;          \

+          break;                                               \

+        case RCC_USART10CLKSOURCE_PLL3:                        \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3;          \

+          break;                                               \

+        case RCC_USART10CLKSOURCE_HSI:                         \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \

+          break;                                               \

+        case RCC_USART10CLKSOURCE_CSI:                         \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI;           \

+          break;                                               \

+        case RCC_USART10CLKSOURCE_LSE:                         \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \

+          break;                                               \

+        default:                                               \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \

+          break;                                               \

+      }                                                        \

+    }                                                          \

+    else                                                       \

+    {                                                          \

+      (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;         \

+    }                                                          \

+  } while(0U)

+#else

+#define USART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__)       \

+  do {                                                         \

+    if((__HANDLE__)->Instance == USART1)                       \

+    {                                                          \

+      switch(__HAL_RCC_GET_USART1_SOURCE())                    \

+      {                                                        \

+        case RCC_USART1CLKSOURCE_D2PCLK2:                      \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK2;       \

+          break;                                               \

+        case RCC_USART1CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2;          \

+          break;                                               \

+        case RCC_USART1CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3;          \

+          break;                                               \

+        case RCC_USART1CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \

+          break;                                               \

+        case RCC_USART1CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI;           \

+          break;                                               \

+        case RCC_USART1CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \

+          break;                                               \

+        default:                                               \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \

+          break;                                               \

+      }                                                        \

+    }                                                          \

+    else if((__HANDLE__)->Instance == USART2)                  \

+    {                                                          \

+      switch(__HAL_RCC_GET_USART2_SOURCE())                    \

+      {                                                        \

+        case RCC_USART2CLKSOURCE_D2PCLK1:                      \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK1;       \

+          break;                                               \

+        case RCC_USART2CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2;          \

+          break;                                               \

+        case RCC_USART2CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3;          \

+          break;                                               \

+        case RCC_USART2CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \

+          break;                                               \

+        case RCC_USART2CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI;           \

+          break;                                               \

+        case RCC_USART2CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \

+          break;                                               \

+        default:                                               \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \

+          break;                                               \

+      }                                                        \

+    }                                                          \

+    else if((__HANDLE__)->Instance == USART3)                  \

+    {                                                          \

+      switch(__HAL_RCC_GET_USART3_SOURCE())                    \

+      {                                                        \

+        case RCC_USART3CLKSOURCE_D2PCLK1:                      \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK1;       \

+          break;                                               \

+        case RCC_USART3CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2;          \

+          break;                                               \

+        case RCC_USART3CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3;          \

+          break;                                               \

+        case RCC_USART3CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \

+          break;                                               \

+        case RCC_USART3CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI;           \

+          break;                                               \

+        case RCC_USART3CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \

+          break;                                               \

+        default:                                               \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \

+          break;                                               \

+      }                                                        \

+    }                                                          \

+    else if((__HANDLE__)->Instance == USART6)                  \

+    {                                                          \

+      switch(__HAL_RCC_GET_USART6_SOURCE())                    \

+      {                                                        \

+        case RCC_USART6CLKSOURCE_D2PCLK2:                      \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_D2PCLK2;       \

+          break;                                               \

+        case RCC_USART6CLKSOURCE_PLL2:                         \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL2;          \

+          break;                                               \

+        case RCC_USART6CLKSOURCE_PLL3:                         \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_PLL3;          \

+          break;                                               \

+        case RCC_USART6CLKSOURCE_HSI:                          \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_HSI;           \

+          break;                                               \

+        case RCC_USART6CLKSOURCE_CSI:                          \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_CSI;           \

+          break;                                               \

+        case RCC_USART6CLKSOURCE_LSE:                          \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_LSE;           \

+          break;                                               \

+        default:                                               \

+          (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;     \

+          break;                                               \

+      }                                                        \

+    }                                                          \

+    else                                                       \

+    {                                                          \

+      (__CLOCKSOURCE__) = USART_CLOCKSOURCE_UNDEFINED;         \

+    }                                                          \

+  } while(0U)

+#endif  /* UART9 && USART10 */

+

+/** @brief  Check USART Baud rate.

+  * @param  __BAUDRATE__ Baudrate specified by the user.

+  *         The maximum Baud Rate is derived from the maximum clock on H7 (i.e. 100 MHz)

+  *         divided by the smallest oversampling used on the USART (i.e. 8)

+  * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid)  */

+#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 12500000U)

+

+/**

+  * @brief Ensure that USART frame number of stop bits is valid.

+  * @param __STOPBITS__ USART frame number of stop bits.

+  * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid)

+  */

+#define IS_USART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == USART_STOPBITS_0_5) || \

+                                         ((__STOPBITS__) == USART_STOPBITS_1)   || \

+                                         ((__STOPBITS__) == USART_STOPBITS_1_5) || \

+                                         ((__STOPBITS__) == USART_STOPBITS_2))

+

+/**

+  * @brief Ensure that USART frame parity is valid.

+  * @param __PARITY__ USART frame parity.

+  * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)

+  */

+#define IS_USART_PARITY(__PARITY__) (((__PARITY__) == USART_PARITY_NONE) || \

+                                     ((__PARITY__) == USART_PARITY_EVEN) || \

+                                     ((__PARITY__) == USART_PARITY_ODD))

+

+/**

+  * @brief Ensure that USART communication mode is valid.

+  * @param __MODE__ USART communication mode.

+  * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)

+  */

+#define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U))

+

+/**

+  * @brief Ensure that USART oversampling is valid.

+  * @param __SAMPLING__ USART oversampling.

+  * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid)

+  */

+#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \

+                                             ((__SAMPLING__) == USART_OVERSAMPLING_8))

+

+/**

+  * @brief Ensure that USART clock state is valid.

+  * @param __CLOCK__ USART clock state.

+  * @retval SET (__CLOCK__ is valid) or RESET (__CLOCK__ is invalid)

+  */

+#define IS_USART_CLOCK(__CLOCK__) (((__CLOCK__) == USART_CLOCK_DISABLE) || \

+                                   ((__CLOCK__) == USART_CLOCK_ENABLE))

+

+/**

+  * @brief Ensure that USART frame polarity is valid.

+  * @param __CPOL__ USART frame polarity.

+  * @retval SET (__CPOL__ is valid) or RESET (__CPOL__ is invalid)

+  */

+#define IS_USART_POLARITY(__CPOL__) (((__CPOL__) == USART_POLARITY_LOW) || ((__CPOL__) == USART_POLARITY_HIGH))

+

+/**

+  * @brief Ensure that USART frame phase is valid.

+  * @param __CPHA__ USART frame phase.

+  * @retval SET (__CPHA__ is valid) or RESET (__CPHA__ is invalid)

+  */

+#define IS_USART_PHASE(__CPHA__) (((__CPHA__) == USART_PHASE_1EDGE) || ((__CPHA__) == USART_PHASE_2EDGE))

+

+/**

+  * @brief Ensure that USART frame last bit clock pulse setting is valid.

+  * @param __LASTBIT__ USART frame last bit clock pulse setting.

+  * @retval SET (__LASTBIT__ is valid) or RESET (__LASTBIT__ is invalid)

+  */

+#define IS_USART_LASTBIT(__LASTBIT__) (((__LASTBIT__) == USART_LASTBIT_DISABLE) || \

+                                       ((__LASTBIT__) == USART_LASTBIT_ENABLE))

+

+/**

+  * @brief Ensure that USART request parameter is valid.

+  * @param __PARAM__ USART request parameter.

+  * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)

+  */

+#define IS_USART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == USART_RXDATA_FLUSH_REQUEST) || \

+                                               ((__PARAM__) == USART_TXDATA_FLUSH_REQUEST))

+

+/**

+  * @brief Ensure that USART Prescaler is valid.

+  * @param __CLOCKPRESCALER__ USART Prescaler value.

+  * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid)

+  */

+#define IS_USART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == USART_PRESCALER_DIV1) || \

+                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV2) || \

+                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV4) || \

+                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV6) || \

+                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV8) || \

+                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV10) || \

+                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV12) || \

+                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) || \

+                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) || \

+                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) || \

+                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) || \

+                                                ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256))

+

+/**

+  * @}

+  */

+

+/* Include USART HAL Extended module */

+#include "stm32h7xx_hal_usart_ex.h"

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup USART_Exported_Functions USART Exported Functions

+  * @{

+  */

+

+/** @addtogroup USART_Exported_Functions_Group1 Initialization and de-initialization functions

+  * @{

+  */

+

+/* Initialization and de-initialization functions  ****************************/

+HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);

+HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);

+void HAL_USART_MspInit(USART_HandleTypeDef *husart);

+void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);

+

+/* Callbacks Register/UnRegister functions  ***********************************/

+#if (USE_HAL_USART_REGISTER_CALLBACKS == 1)

+HAL_StatusTypeDef HAL_USART_RegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID,

+                                             pUSART_CallbackTypeDef pCallback);

+HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_USART_CallbackIDTypeDef CallbackID);

+#endif /* USE_HAL_USART_REGISTER_CALLBACKS */

+

+/**

+  * @}

+  */

+

+/** @addtogroup USART_Exported_Functions_Group2 IO operation functions

+  * @{

+  */

+

+/* IO operation functions *****************************************************/

+HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);

+HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);

+HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,

+                                            uint16_t Size, uint32_t Timeout);

+HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);

+HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);

+HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,

+                                               uint16_t Size);

+HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);

+HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);

+HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,

+                                                uint16_t Size);

+HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);

+HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);

+HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);

+/* Transfer Abort functions */

+HAL_StatusTypeDef HAL_USART_Abort(USART_HandleTypeDef *husart);

+HAL_StatusTypeDef HAL_USART_Abort_IT(USART_HandleTypeDef *husart);

+

+void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);

+void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);

+void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);

+void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);

+void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);

+void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);

+void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);

+void HAL_USART_AbortCpltCallback(USART_HandleTypeDef *husart);

+

+/**

+  * @}

+  */

+

+/** @addtogroup USART_Exported_Functions_Group4 Peripheral State and Error functions

+  * @{

+  */

+

+/* Peripheral State and Error functions ***************************************/

+HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);

+uint32_t               HAL_USART_GetError(USART_HandleTypeDef *husart);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_USART_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_usart_ex.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_usart_ex.h
new file mode 100644
index 0000000000..2fa4390af8
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_usart_ex.h
@@ -0,0 +1,284 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_usart_ex.h

+  * @author  MCD Application Team

+  * @brief   Header file of USART HAL Extended module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_USART_EX_H

+#define STM32H7xx_HAL_USART_EX_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup USARTEx

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup USARTEx_Exported_Constants USARTEx Exported Constants

+  * @{

+  */

+

+/** @defgroup USARTEx_Word_Length USARTEx Word Length

+  * @{

+  */

+#define USART_WORDLENGTH_7B                  ((uint32_t)USART_CR1_M1)   /*!< 7-bit long USART frame */

+#define USART_WORDLENGTH_8B                  (0x00000000U)              /*!< 8-bit long USART frame */

+#define USART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M0)   /*!< 9-bit long USART frame */

+/**

+  * @}

+  */

+

+/** @defgroup USARTEx_Slave_Select_management USARTEx Slave Select Management

+  * @{

+  */

+#define USART_NSS_HARD                        0x00000000U          /*!< SPI slave selection depends on NSS input pin              */

+#define USART_NSS_SOFT                        USART_CR2_DIS_NSS    /*!< SPI slave is always selected and NSS input pin is ignored */

+/**

+  * @}

+  */

+

+

+/** @defgroup USARTEx_Slave_Mode USARTEx Synchronous Slave mode enable

+  * @brief    USART SLAVE mode

+  * @{

+  */

+#define USART_SLAVEMODE_DISABLE   0x00000000U     /*!< USART SPI Slave Mode Enable  */

+#define USART_SLAVEMODE_ENABLE    USART_CR2_SLVEN /*!< USART SPI Slave Mode Disable */

+/**

+  * @}

+  */

+

+/** @defgroup USARTEx_FIFO_mode USARTEx FIFO  mode

+  * @brief    USART FIFO  mode

+  * @{

+  */

+#define USART_FIFOMODE_DISABLE        0x00000000U                   /*!< FIFO mode disable */

+#define USART_FIFOMODE_ENABLE         USART_CR1_FIFOEN              /*!< FIFO mode enable  */

+/**

+  * @}

+  */

+

+/** @defgroup USARTEx_TXFIFO_threshold_level USARTEx TXFIFO threshold level

+  * @brief    USART TXFIFO level

+  * @{

+  */

+#define USART_TXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< TXFIFO reaches 1/8 of its depth */

+#define USART_TXFIFO_THRESHOLD_1_4   USART_CR3_TXFTCFG_0                       /*!< TXFIFO reaches 1/4 of its depth */

+#define USART_TXFIFO_THRESHOLD_1_2   USART_CR3_TXFTCFG_1                       /*!< TXFIFO reaches 1/2 of its depth */

+#define USART_TXFIFO_THRESHOLD_3_4   (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */

+#define USART_TXFIFO_THRESHOLD_7_8   USART_CR3_TXFTCFG_2                       /*!< TXFIFO reaches 7/8 of its depth */

+#define USART_TXFIFO_THRESHOLD_8_8   (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty            */

+/**

+  * @}

+  */

+

+/** @defgroup USARTEx_RXFIFO_threshold_level USARTEx RXFIFO threshold level

+  * @brief    USART RXFIFO level

+  * @{

+  */

+#define USART_RXFIFO_THRESHOLD_1_8   0x00000000U                               /*!< RXFIFO FIFO reaches 1/8 of its depth */

+#define USART_RXFIFO_THRESHOLD_1_4   USART_CR3_RXFTCFG_0                       /*!< RXFIFO FIFO reaches 1/4 of its depth */

+#define USART_RXFIFO_THRESHOLD_1_2   USART_CR3_RXFTCFG_1                       /*!< RXFIFO FIFO reaches 1/2 of its depth */

+#define USART_RXFIFO_THRESHOLD_3_4   (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */

+#define USART_RXFIFO_THRESHOLD_7_8   USART_CR3_RXFTCFG_2                       /*!< RXFIFO FIFO reaches 7/8 of its depth */

+#define USART_RXFIFO_THRESHOLD_8_8   (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full             */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup USARTEx_Private_Macros USARTEx Private Macros

+  * @{

+  */

+

+/** @brief  Compute the USART mask to apply to retrieve the received data

+  *         according to the word length and to the parity bits activation.

+  * @note   If PCE = 1, the parity bit is not included in the data extracted

+  *         by the reception API().

+  *         This masking operation is not carried out in the case of

+  *         DMA transfers.

+  * @param  __HANDLE__ specifies the USART Handle.

+  * @retval None, the mask to apply to USART RDR register is stored in (__HANDLE__)->Mask field.

+  */

+#define USART_MASK_COMPUTATION(__HANDLE__)                            \

+  do {                                                                \

+    if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_9B)         \

+    {                                                                 \

+      if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)             \

+      {                                                               \

+        (__HANDLE__)->Mask = 0x01FFU;                                 \

+      }                                                               \

+      else                                                            \

+      {                                                               \

+        (__HANDLE__)->Mask = 0x00FFU;                                 \

+      }                                                               \

+    }                                                                 \

+    else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_8B)    \

+    {                                                                 \

+      if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)             \

+      {                                                               \

+        (__HANDLE__)->Mask = 0x00FFU;                                 \

+      }                                                               \

+      else                                                            \

+      {                                                               \

+        (__HANDLE__)->Mask = 0x007FU;                                 \

+      }                                                               \

+    }                                                                 \

+    else if ((__HANDLE__)->Init.WordLength == USART_WORDLENGTH_7B)    \

+    {                                                                 \

+      if ((__HANDLE__)->Init.Parity == USART_PARITY_NONE)             \

+      {                                                               \

+        (__HANDLE__)->Mask = 0x007FU;                                 \

+      }                                                               \

+      else                                                            \

+      {                                                               \

+        (__HANDLE__)->Mask = 0x003FU;                                 \

+      }                                                               \

+    }                                                                 \

+    else                                                              \

+    {                                                                 \

+      (__HANDLE__)->Mask = 0x0000U;                                   \

+    }                                                                 \

+  } while(0U)

+

+/**

+  * @brief Ensure that USART frame length is valid.

+  * @param __LENGTH__ USART frame length.

+  * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)

+  */

+#define IS_USART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == USART_WORDLENGTH_7B) || \

+                                          ((__LENGTH__) == USART_WORDLENGTH_8B) || \

+                                          ((__LENGTH__) == USART_WORDLENGTH_9B))

+

+/**

+  * @brief Ensure that USART Negative Slave Select (NSS) pin management is valid.

+  * @param __NSS__ USART Negative Slave Select pin management.

+  * @retval SET (__NSS__ is valid) or RESET (__NSS__ is invalid)

+  */

+#define IS_USART_NSS(__NSS__) (((__NSS__) == USART_NSS_HARD) || \

+                               ((__NSS__) == USART_NSS_SOFT))

+

+/**

+  * @brief Ensure that USART Slave Mode is valid.

+  * @param __STATE__ USART Slave Mode.

+  * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

+  */

+#define IS_USART_SLAVEMODE(__STATE__)   (((__STATE__) == USART_SLAVEMODE_DISABLE ) || \

+                                         ((__STATE__) == USART_SLAVEMODE_ENABLE))

+

+/**

+  * @brief Ensure that USART FIFO mode is valid.

+  * @param __STATE__ USART FIFO mode.

+  * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)

+  */

+#define IS_USART_FIFO_MODE_STATE(__STATE__) (((__STATE__) == USART_FIFOMODE_DISABLE ) || \

+                                             ((__STATE__) == USART_FIFOMODE_ENABLE))

+

+/**

+  * @brief Ensure that USART TXFIFO threshold level is valid.

+  * @param __THRESHOLD__ USART TXFIFO threshold level.

+  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

+  */

+#define IS_USART_TXFIFO_THRESHOLD(__THRESHOLD__)  (((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_8)  || \

+                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_4)  || \

+                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_1_2)  || \

+                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_3_4)  || \

+                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_7_8)  || \

+                                                   ((__THRESHOLD__) == USART_TXFIFO_THRESHOLD_8_8))

+

+/**

+  * @brief Ensure that USART RXFIFO threshold level is valid.

+  * @param __THRESHOLD__ USART RXFIFO threshold level.

+  * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid)

+  */

+#define IS_USART_RXFIFO_THRESHOLD(__THRESHOLD__)  (((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_8)  || \

+                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_4)  || \

+                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_1_2)  || \

+                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_3_4)  || \

+                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_7_8)  || \

+                                                   ((__THRESHOLD__) == USART_RXFIFO_THRESHOLD_8_8))

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup USARTEx_Exported_Functions

+  * @{

+  */

+

+/** @addtogroup USARTEx_Exported_Functions_Group1

+  * @{

+  */

+

+/* IO operation functions *****************************************************/

+void HAL_USARTEx_RxFifoFullCallback(USART_HandleTypeDef *husart);

+void HAL_USARTEx_TxFifoEmptyCallback(USART_HandleTypeDef *husart);

+

+/**

+  * @}

+  */

+

+/** @addtogroup USARTEx_Exported_Functions_Group2

+  * @{

+  */

+

+/* Peripheral Control functions ***********************************************/

+HAL_StatusTypeDef HAL_USARTEx_EnableSlaveMode(USART_HandleTypeDef *husart);

+HAL_StatusTypeDef HAL_USARTEx_DisableSlaveMode(USART_HandleTypeDef *husart);

+HAL_StatusTypeDef HAL_USARTEx_ConfigNSS(USART_HandleTypeDef *husart, uint32_t NSSConfig);

+HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart);

+HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart);

+HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold);

+HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_USART_EX_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_hal_wwdg.h b/bsps/arm/stm32h7/include/stm32h7xx_hal_wwdg.h
new file mode 100644
index 0000000000..32e6379208
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_hal_wwdg.h
@@ -0,0 +1,308 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_hal_wwdg.h

+  * @author  MCD Application Team

+  * @brief   Header file of WWDG HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_HAL_WWDG_H

+#define STM32H7xx_HAL_WWDG_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup WWDG

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+

+/** @defgroup WWDG_Exported_Types WWDG Exported Types

+  * @{

+  */

+

+/**

+  * @brief  WWDG Init structure definition

+  */

+typedef struct

+{

+  uint32_t Prescaler;     /*!< Specifies the prescaler value of the WWDG.

+                               This parameter can be a value of @ref WWDG_Prescaler */

+

+  uint32_t Window;        /*!< Specifies the WWDG window value to be compared to the downcounter.

+                               This parameter must be a number Min_Data = 0x40 and Max_Data = 0x7F */

+

+  uint32_t Counter;       /*!< Specifies the WWDG free-running downcounter  value.

+                               This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */

+

+  uint32_t EWIMode ;      /*!< Specifies if WWDG Early Wakeup Interupt is enable or not.

+                               This parameter can be a value of @ref WWDG_EWI_Mode */

+

+} WWDG_InitTypeDef;

+

+/**

+  * @brief  WWDG handle Structure definition

+  */

+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)

+typedef struct __WWDG_HandleTypeDef

+#else

+typedef struct

+#endif

+{

+  WWDG_TypeDef      *Instance;  /*!< Register base address */

+

+  WWDG_InitTypeDef  Init;       /*!< WWDG required parameters */

+

+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)

+  void              (* EwiCallback)(struct __WWDG_HandleTypeDef *hwwdg);     /*!< WWDG Early WakeUp Interrupt callback */

+

+  void              (* MspInitCallback)(struct __WWDG_HandleTypeDef *hwwdg); /*!< WWDG Msp Init callback */

+#endif

+} WWDG_HandleTypeDef;

+

+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)

+/**

+  * @brief  HAL WWDG common Callback ID enumeration definition

+  */

+typedef enum

+{

+  HAL_WWDG_EWI_CB_ID          = 0x00u,    /*!< WWDG EWI callback ID */

+  HAL_WWDG_MSPINIT_CB_ID      = 0x01u,    /*!< WWDG MspInit callback ID */

+} HAL_WWDG_CallbackIDTypeDef;

+

+/**

+  * @brief  HAL WWDG Callback pointer definition

+  */

+typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp);  /*!< pointer to a WWDG common callback functions */

+

+#endif

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+

+/** @defgroup WWDG_Exported_Constants WWDG Exported Constants

+  * @{

+  */

+

+/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition

+  * @{

+  */

+#define WWDG_IT_EWI                         WWDG_CFR_EWI  /*!< Early wakeup interrupt */

+/**

+  * @}

+  */

+

+/** @defgroup WWDG_Flag_definition WWDG Flag definition

+  * @brief WWDG Flag definition

+  * @{

+  */

+#define WWDG_FLAG_EWIF                      WWDG_SR_EWIF  /*!< Early wakeup interrupt flag */

+/**

+  * @}

+  */

+

+/** @defgroup WWDG_Prescaler WWDG Prescaler

+  * @{

+  */

+#define WWDG_PRESCALER_1                    0x00000000u                              /*!< WWDG counter clock = (PCLK1/4096)/1 */

+#define WWDG_PRESCALER_2                    WWDG_CFR_WDGTB_0                         /*!< WWDG counter clock = (PCLK1/4096)/2 */

+#define WWDG_PRESCALER_4                    WWDG_CFR_WDGTB_1                         /*!< WWDG counter clock = (PCLK1/4096)/4 */

+#define WWDG_PRESCALER_8                    (WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)    /*!< WWDG counter clock = (PCLK1/4096)/8 */

+#define WWDG_PRESCALER_16                   WWDG_CFR_WDGTB_2                         /*!< WWDG counter clock = (PCLK1/4096)/16 */

+#define WWDG_PRESCALER_32                   (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)    /*!< WWDG counter clock = (PCLK1/4096)/32 */

+#define WWDG_PRESCALER_64                   (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)    /*!< WWDG counter clock = (PCLK1/4096)/64 */

+#define WWDG_PRESCALER_128                  WWDG_CFR_WDGTB                           /*!< WWDG counter clock = (PCLK1/4096)/128 */

+/**

+  * @}

+  */

+

+/** @defgroup WWDG_EWI_Mode WWDG Early Wakeup Interrupt Mode

+  * @{

+  */

+#define WWDG_EWI_DISABLE                    0x00000000u       /*!< EWI Disable */

+#define WWDG_EWI_ENABLE                     WWDG_CFR_EWI      /*!< EWI Enable */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+

+/** @defgroup WWDG_Private_Macros WWDG Private Macros

+  * @{

+  */

+#define IS_WWDG_PRESCALER(__PRESCALER__)    (((__PRESCALER__) == WWDG_PRESCALER_1)  || \

+                                             ((__PRESCALER__) == WWDG_PRESCALER_2)  || \

+                                             ((__PRESCALER__) == WWDG_PRESCALER_4)  || \

+                                             ((__PRESCALER__) == WWDG_PRESCALER_8)  || \

+                                             ((__PRESCALER__) == WWDG_PRESCALER_16) || \

+                                             ((__PRESCALER__) == WWDG_PRESCALER_32) || \

+                                             ((__PRESCALER__) == WWDG_PRESCALER_64) || \

+                                             ((__PRESCALER__) == WWDG_PRESCALER_128))

+

+#define IS_WWDG_WINDOW(__WINDOW__)          (((__WINDOW__) >= WWDG_CFR_W_6) && ((__WINDOW__) <= WWDG_CFR_W))

+

+#define IS_WWDG_COUNTER(__COUNTER__)        (((__COUNTER__) >= WWDG_CR_T_6) && ((__COUNTER__) <= WWDG_CR_T))

+

+#define IS_WWDG_EWI_MODE(__MODE__)          (((__MODE__) == WWDG_EWI_ENABLE) || \

+                                             ((__MODE__) == WWDG_EWI_DISABLE))

+/**

+  * @}

+  */

+

+

+/* Exported macros ------------------------------------------------------------*/

+

+/** @defgroup WWDG_Exported_Macros WWDG Exported Macros

+  * @{

+  */

+

+/**

+  * @brief  Enable the WWDG peripheral.

+  * @param  __HANDLE__  WWDG handle

+  * @retval None

+  */

+#define __HAL_WWDG_ENABLE(__HANDLE__)                         SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)

+

+/**

+  * @brief  Enable the WWDG early wakeup interrupt.

+  * @param  __HANDLE__: WWDG handle

+  * @param  __INTERRUPT__  specifies the interrupt to enable.

+  *         This parameter can be one of the following values:

+  *            @arg WWDG_IT_EWI: Early wakeup interrupt

+  * @note   Once enabled this interrupt cannot be disabled except by a system reset.

+  * @retval None

+  */

+#define __HAL_WWDG_ENABLE_IT(__HANDLE__, __INTERRUPT__)       SET_BIT((__HANDLE__)->Instance->CFR, (__INTERRUPT__))

+

+/**

+  * @brief  Check whether the selected WWDG interrupt has occurred or not.

+  * @param  __HANDLE__  WWDG handle

+  * @param  __INTERRUPT__  specifies the it to check.

+  *        This parameter can be one of the following values:

+  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt IT

+  * @retval The new state of WWDG_FLAG (SET or RESET).

+  */

+#define __HAL_WWDG_GET_IT(__HANDLE__, __INTERRUPT__)        __HAL_WWDG_GET_FLAG((__HANDLE__),(__INTERRUPT__))

+

+/** @brief  Clear the WWDG interrupt pending bits.

+  *         bits to clear the selected interrupt pending bits.

+  * @param  __HANDLE__  WWDG handle

+  * @param  __INTERRUPT__  specifies the interrupt pending bit to clear.

+  *         This parameter can be one of the following values:

+  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag

+  */

+#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__)      __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))

+

+/**

+  * @brief  Check whether the specified WWDG flag is set or not.

+  * @param  __HANDLE__  WWDG handle

+  * @param  __FLAG__  specifies the flag to check.

+  *         This parameter can be one of the following values:

+  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag

+  * @retval The new state of WWDG_FLAG (SET or RESET).

+  */

+#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__)           (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))

+

+/**

+  * @brief  Clear the WWDG's pending flags.

+  * @param  __HANDLE__  WWDG handle

+  * @param  __FLAG__  specifies the flag to clear.

+  *         This parameter can be one of the following values:

+  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag

+  * @retval None

+  */

+#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->SR = ~(__FLAG__))

+

+/** @brief  Check whether the specified WWDG interrupt source is enabled or not.

+  * @param  __HANDLE__  WWDG Handle.

+  * @param  __INTERRUPT__  specifies the WWDG interrupt source to check.

+  *         This parameter can be one of the following values:

+  *            @arg WWDG_IT_EWI: Early Wakeup Interrupt

+  * @retval state of __INTERRUPT__ (TRUE or FALSE).

+  */

+#define __HAL_WWDG_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CFR\

+                                                              & (__INTERRUPT__)) == (__INTERRUPT__))

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+

+/** @addtogroup WWDG_Exported_Functions

+  * @{

+  */

+

+/** @addtogroup WWDG_Exported_Functions_Group1

+  * @{

+  */

+/* Initialization/de-initialization functions  **********************************/

+HAL_StatusTypeDef     HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);

+void                  HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);

+/* Callbacks Register/UnRegister functions  ***********************************/

+#if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1)

+HAL_StatusTypeDef     HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID, pWWDG_CallbackTypeDef pCallback);

+HAL_StatusTypeDef     HAL_WWDG_UnRegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_CallbackIDTypeDef CallbackID);

+#endif

+

+/**

+  * @}

+  */

+

+/** @addtogroup WWDG_Exported_Functions_Group2

+  * @{

+  */

+/* I/O operation functions ******************************************************/

+HAL_StatusTypeDef     HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg);

+void                  HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);

+void                  HAL_WWDG_EarlyWakeupCallback(WWDG_HandleTypeDef *hwwdg);

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_HAL_WWDG_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_adc.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_adc.h
new file mode 100644
index 0000000000..d13bbeac59
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_adc.h
@@ -0,0 +1,7222 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_adc.h

+  * @author  MCD Application Team

+  * @brief   Header file of ADC LL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_LL_ADC_H

+#define STM32H7xx_LL_ADC_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+#if defined (ADC1) || defined (ADC2) || defined (ADC3)

+

+/** @defgroup ADC_LL ADC

+  * @{

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup ADC_LL_Private_Constants ADC Private Constants

+  * @{

+  */

+

+/* Internal mask for ADC calibration:                                         */

+/* Internal register offset for ADC calibration factors configuration */

+

+/* To select into literals LL_ADC_CALIB_OFFSET, LL_ADC_CALIB_LINEARITY, ...   */

+/* the relevant bits for:                                                     */

+/* (concatenation of multiple bits used in different registers)               */

+/* - ADC calibration configuration: configuration before calibration start    */

+/* - ADC calibration factors: register offset                                 */

+#define ADC_CALIB_FACTOR_OFFSET_REGOFFSET    (0x00000000UL) /* Register CALFACT defined as reference register */

+#define ADC_CALIB_FACTOR_LINEARITY_REGOFFSET (0x00000001UL) /* Register CALFACT2 offset vs register CALFACT */

+#define ADC_CALIB_FACTOR_REGOFFSET_MASK      (ADC_CALIB_FACTOR_OFFSET_REGOFFSET | ADC_CALIB_FACTOR_LINEARITY_REGOFFSET)

+#define ADC_CALIB_MODE_MASK                  (ADC_CR_ADCALLIN)

+#define ADC_CALIB_MODE_BINARY_MASK           (ADC_CALIB_FACTOR_REGOFFSET_MASK) /* Mask to get binary value of calibration mode: 0 for offset, 1 for linearity */

+

+

+/* Internal mask for ADC group regular sequencer:                             */

+/* To select into literal LL_ADC_REG_RANK_x the relevant bits for:            */

+/* - sequencer register offset                                                */

+/* - sequencer rank bits position into the selected register                  */

+

+/* Internal register offset for ADC group regular sequencer configuration */

+/* (offset placed into a spare area of literal definition) */

+#define ADC_SQR1_REGOFFSET                 (0x00000000UL)

+#define ADC_SQR2_REGOFFSET                 (0x00000100UL)

+#define ADC_SQR3_REGOFFSET                 (0x00000200UL)

+#define ADC_SQR4_REGOFFSET                 (0x00000300UL)

+

+#define ADC_REG_SQRX_REGOFFSET_MASK        (ADC_SQR1_REGOFFSET | ADC_SQR2_REGOFFSET | ADC_SQR3_REGOFFSET | ADC_SQR4_REGOFFSET)

+#define ADC_SQRX_REGOFFSET_POS             (8UL) /* Position of bits ADC_SQRx_REGOFFSET in ADC_REG_SQRX_REGOFFSET_MASK */

+#define ADC_REG_RANK_ID_SQRX_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)

+

+/* Definition of ADC group regular sequencer bits information to be inserted  */

+/* into ADC group regular sequencer ranks literals definition.                */

+#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS  ( 6UL) /* Value equivalent to bitfield "ADC_SQR1_SQ1" position in register */

+#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS  (12UL) /* Value equivalent to bitfield "ADC_SQR1_SQ2" position in register */

+#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS  (18UL) /* Value equivalent to bitfield "ADC_SQR1_SQ3" position in register */

+#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS  (24UL) /* Value equivalent to bitfield "ADC_SQR1_SQ4" position in register */

+#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS  ( 0UL) /* Value equivalent to bitfield "ADC_SQR2_SQ5" position in register */

+#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS  ( 6UL) /* Value equivalent to bitfield "ADC_SQR2_SQ6" position in register */

+#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS  (12UL) /* Value equivalent to bitfield "ADC_SQR2_SQ7" position in register */

+#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS  (18UL) /* Value equivalent to bitfield "ADC_SQR2_SQ8" position in register */

+#define ADC_REG_RANK_9_SQRX_BITOFFSET_POS  (24UL) /* Value equivalent to bitfield "ADC_SQR2_SQ9" position in register */

+#define ADC_REG_RANK_10_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR3_SQ10" position in register */

+#define ADC_REG_RANK_11_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR3_SQ11" position in register */

+#define ADC_REG_RANK_12_SQRX_BITOFFSET_POS (12UL) /* Value equivalent to bitfield "ADC_SQR3_SQ12" position in register */

+#define ADC_REG_RANK_13_SQRX_BITOFFSET_POS (18UL) /* Value equivalent to bitfield "ADC_SQR3_SQ13" position in register */

+#define ADC_REG_RANK_14_SQRX_BITOFFSET_POS (24UL) /* Value equivalent to bitfield "ADC_SQR3_SQ14" position in register */

+#define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Value equivalent to bitfield "ADC_SQR4_SQ15" position in register */

+#define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Value equivalent to bitfield "ADC_SQR4_SQ16" position in register */

+

+

+

+/* Internal mask for ADC group injected sequencer:                            */

+/* To select into literal LL_ADC_INJ_RANK_x the relevant bits for:            */

+/* - data register offset                                                     */

+/* - sequencer rank bits position into the selected register                  */

+

+/* Internal register offset for ADC group injected data register */

+/* (offset placed into a spare area of literal definition) */

+#define ADC_JDR1_REGOFFSET                 (0x00000000UL)

+#define ADC_JDR2_REGOFFSET                 (0x00000100UL)

+#define ADC_JDR3_REGOFFSET                 (0x00000200UL)

+#define ADC_JDR4_REGOFFSET                 (0x00000300UL)

+

+#define ADC_INJ_JDRX_REGOFFSET_MASK        (ADC_JDR1_REGOFFSET | ADC_JDR2_REGOFFSET | ADC_JDR3_REGOFFSET | ADC_JDR4_REGOFFSET)

+#define ADC_INJ_RANK_ID_JSQR_MASK          (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0)

+#define ADC_JDRX_REGOFFSET_POS             (8UL) /* Position of bits ADC_JDRx_REGOFFSET in ADC_INJ_JDRX_REGOFFSET_MASK */

+

+/* Definition of ADC group injected sequencer bits information to be inserted */

+/* into ADC group injected sequencer ranks literals definition.               */

+#define ADC_INJ_RANK_1_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ1_Pos)

+#define ADC_INJ_RANK_2_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ2_Pos)

+#define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ3_Pos)

+#define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS  (ADC_JSQR_JSQ4_Pos)

+

+

+

+/* Internal mask for ADC group regular trigger:                               */

+/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for:            */

+/* - regular trigger source                                                   */

+/* - regular trigger edge                                                     */

+#define ADC_REG_TRIG_EXT_EDGE_DEFAULT       (ADC_CFGR_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */

+

+/* Mask containing trigger source masks for each of possible                  */

+/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */

+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */

+#define ADC_REG_TRIG_SOURCE_MASK            (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTSEL) << (4U * 0UL)) | \

+                                             ((ADC_CFGR_EXTSEL)                            << (4U * 1UL)) | \

+                                             ((ADC_CFGR_EXTSEL)                            << (4U * 2UL)) | \

+                                             ((ADC_CFGR_EXTSEL)                            << (4U * 3UL))  )

+

+/* Mask containing trigger edge masks for each of possible                    */

+/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */

+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */

+#define ADC_REG_TRIG_EDGE_MASK              (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN) << (4U * 0UL)) | \

+                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 1UL)) | \

+                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 2UL)) | \

+                                             ((ADC_REG_TRIG_EXT_EDGE_DEFAULT)             << (4U * 3UL))  )

+

+/* Definition of ADC group regular trigger bits information.                  */

+#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS  ( 6UL) /* Value equivalent to bitfield "ADC_CFGR_EXTSEL" position in register */

+#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS   (10UL) /* Value equivalent to bitfield "ADC_CFGR_EXTEN" position in register */

+

+

+

+/* Internal mask for ADC group injected trigger:                              */

+/* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for:            */

+/* - injected trigger source                                                  */

+/* - injected trigger edge                                                    */

+#define ADC_INJ_TRIG_EXT_EDGE_DEFAULT      (ADC_JSQR_JEXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value) */

+

+/* Mask containing trigger source masks for each of possible                  */

+/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */

+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */

+#define ADC_INJ_TRIG_SOURCE_MASK            (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTSEL)  << (4U * 0UL)) | \

+                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 1UL)) | \

+                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 2UL)) | \

+                                             ((ADC_JSQR_JEXTSEL)                             << (4U * 3UL))  )

+

+/* Mask containing trigger edge masks for each of possible                    */

+/* trigger edge selection duplicated with shifts [0; 4; 8; 12]                */

+/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}.        */

+#define ADC_INJ_TRIG_EDGE_MASK              (((LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN) << (4U * 0UL)) | \

+                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 1UL)) | \

+                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 2UL)) | \

+                                             ((ADC_INJ_TRIG_EXT_EDGE_DEFAULT)              << (4U * 3UL))  )

+

+/* Definition of ADC group injected trigger bits information.                 */

+#define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS  ( 2UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTSEL" position in register */

+#define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS   ( 6UL) /* Value equivalent to bitfield "ADC_JSQR_JEXTEN" position in register */

+

+

+

+

+

+

+/* Internal mask for ADC channel:                                             */

+/* To select into literal LL_ADC_CHANNEL_x the relevant bits for:             */

+/* - channel identifier defined by number                                     */

+/* - channel identifier defined by bitfield                                   */

+/* - channel differentiation between external channels (connected to          */

+/*   GPIO pins) and internal channels (connected to internal paths)           */

+/* - channel sampling time defined by SMPRx register offset                   */

+/*   and SMPx bits positions into SMPRx register                              */

+#define ADC_CHANNEL_ID_NUMBER_MASK         (ADC_CFGR_AWD1CH)

+#define ADC_CHANNEL_ID_BITFIELD_MASK       (ADC_AWD2CR_AWD2CH)

+#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL)/* Value equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" position in register */

+#define ADC_CHANNEL_ID_MASK                (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK)

+/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */

+#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (ADC_SQR2_SQ5) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */

+

+/* Channel differentiation between external and internal channels */

+#define ADC_CHANNEL_ID_INTERNAL_CH         (0x80000000UL) /* Marker of internal channel */

+#define ADC_CHANNEL_ID_INTERNAL_CH_MASK    (ADC_CHANNEL_ID_INTERNAL_CH)

+

+/* Internal register offset for ADC channel sampling time configuration */

+/* (offset placed into a spare area of literal definition) */

+#define ADC_SMPR1_REGOFFSET                (0x00000000UL)

+#define ADC_SMPR2_REGOFFSET                (0x02000000UL)

+#define ADC_CHANNEL_SMPRX_REGOFFSET_MASK   (ADC_SMPR1_REGOFFSET | ADC_SMPR2_REGOFFSET)

+#define ADC_SMPRX_REGOFFSET_POS            (25UL) /* Position of bits ADC_SMPRx_REGOFFSET in ADC_CHANNEL_SMPRX_REGOFFSET_MASK */

+

+#define ADC_CHANNEL_SMPx_BITOFFSET_MASK    (0x01F00000UL)

+#define ADC_CHANNEL_SMPx_BITOFFSET_POS     (20UL)           /* Value equivalent to bitfield "ADC_CHANNEL_SMPx_BITOFFSET_MASK" position in register */

+

+/* Definition of channels ID number information to be inserted into           */

+/* channels literals definition.                                              */

+#define ADC_CHANNEL_0_NUMBER               (0x00000000UL)

+#define ADC_CHANNEL_1_NUMBER               (                                                                                ADC_CFGR_AWD1CH_0)

+#define ADC_CHANNEL_2_NUMBER               (                                                            ADC_CFGR_AWD1CH_1                    )

+#define ADC_CHANNEL_3_NUMBER               (                                                            ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

+#define ADC_CHANNEL_4_NUMBER               (                                        ADC_CFGR_AWD1CH_2                                        )

+#define ADC_CHANNEL_5_NUMBER               (                                        ADC_CFGR_AWD1CH_2                     | ADC_CFGR_AWD1CH_0)

+#define ADC_CHANNEL_6_NUMBER               (                                        ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1                    )

+#define ADC_CHANNEL_7_NUMBER               (                                        ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

+#define ADC_CHANNEL_8_NUMBER               (                    ADC_CFGR_AWD1CH_3                                                            )

+#define ADC_CHANNEL_9_NUMBER               (                    ADC_CFGR_AWD1CH_3                                         | ADC_CFGR_AWD1CH_0)

+#define ADC_CHANNEL_10_NUMBER              (                    ADC_CFGR_AWD1CH_3                     | ADC_CFGR_AWD1CH_1                    )

+#define ADC_CHANNEL_11_NUMBER              (                    ADC_CFGR_AWD1CH_3                     | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

+#define ADC_CHANNEL_12_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2                                        )

+#define ADC_CHANNEL_13_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2                     | ADC_CFGR_AWD1CH_0)

+#define ADC_CHANNEL_14_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1                    )

+#define ADC_CHANNEL_15_NUMBER              (                    ADC_CFGR_AWD1CH_3 | ADC_CFGR_AWD1CH_2 | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

+#define ADC_CHANNEL_16_NUMBER              (ADC_CFGR_AWD1CH_4                                                                                )

+#define ADC_CHANNEL_17_NUMBER              (ADC_CFGR_AWD1CH_4                                                             | ADC_CFGR_AWD1CH_0)

+#define ADC_CHANNEL_18_NUMBER              (ADC_CFGR_AWD1CH_4                                         | ADC_CFGR_AWD1CH_1                    )

+#define ADC_CHANNEL_19_NUMBER              (ADC_CFGR_AWD1CH_4                                         | ADC_CFGR_AWD1CH_1 | ADC_CFGR_AWD1CH_0)

+

+/* Definition of channels ID bitfield information to be inserted into         */

+/* channels literals definition.                                              */

+#define ADC_CHANNEL_0_BITFIELD             (ADC_AWD2CR_AWD2CH_0)

+#define ADC_CHANNEL_1_BITFIELD             (ADC_AWD2CR_AWD2CH_1)

+#define ADC_CHANNEL_2_BITFIELD             (ADC_AWD2CR_AWD2CH_2)

+#define ADC_CHANNEL_3_BITFIELD             (ADC_AWD2CR_AWD2CH_3)

+#define ADC_CHANNEL_4_BITFIELD             (ADC_AWD2CR_AWD2CH_4)

+#define ADC_CHANNEL_5_BITFIELD             (ADC_AWD2CR_AWD2CH_5)

+#define ADC_CHANNEL_6_BITFIELD             (ADC_AWD2CR_AWD2CH_6)

+#define ADC_CHANNEL_7_BITFIELD             (ADC_AWD2CR_AWD2CH_7)

+#define ADC_CHANNEL_8_BITFIELD             (ADC_AWD2CR_AWD2CH_8)

+#define ADC_CHANNEL_9_BITFIELD             (ADC_AWD2CR_AWD2CH_9)

+#define ADC_CHANNEL_10_BITFIELD            (ADC_AWD2CR_AWD2CH_10)

+#define ADC_CHANNEL_11_BITFIELD            (ADC_AWD2CR_AWD2CH_11)

+#define ADC_CHANNEL_12_BITFIELD            (ADC_AWD2CR_AWD2CH_12)

+#define ADC_CHANNEL_13_BITFIELD            (ADC_AWD2CR_AWD2CH_13)

+#define ADC_CHANNEL_14_BITFIELD            (ADC_AWD2CR_AWD2CH_14)

+#define ADC_CHANNEL_15_BITFIELD            (ADC_AWD2CR_AWD2CH_15)

+#define ADC_CHANNEL_16_BITFIELD            (ADC_AWD2CR_AWD2CH_16)

+#define ADC_CHANNEL_17_BITFIELD            (ADC_AWD2CR_AWD2CH_17)

+#define ADC_CHANNEL_18_BITFIELD            (ADC_AWD2CR_AWD2CH_18)

+#define ADC_CHANNEL_19_BITFIELD            (ADC_AWD2CR_AWD2CH_19)

+

+/* Definition of channels sampling time information to be inserted into       */

+/* channels literals definition.                                              */

+#define ADC_CHANNEL_0_SMP                  (ADC_SMPR1_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP0" position in register */

+#define ADC_CHANNEL_1_SMP                  (ADC_SMPR1_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP1" position in register */

+#define ADC_CHANNEL_2_SMP                  (ADC_SMPR1_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP2" position in register */

+#define ADC_CHANNEL_3_SMP                  (ADC_SMPR1_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP3" position in register */

+#define ADC_CHANNEL_4_SMP                  (ADC_SMPR1_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP4" position in register */

+#define ADC_CHANNEL_5_SMP                  (ADC_SMPR1_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP5" position in register */

+#define ADC_CHANNEL_6_SMP                  (ADC_SMPR1_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP6" position in register */

+#define ADC_CHANNEL_7_SMP                  (ADC_SMPR1_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP7" position in register */

+#define ADC_CHANNEL_8_SMP                  (ADC_SMPR1_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP8" position in register */

+#define ADC_CHANNEL_9_SMP                  (ADC_SMPR1_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR1_SMP9" position in register */

+#define ADC_CHANNEL_10_SMP                 (ADC_SMPR2_REGOFFSET | (( 0UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP10" position in register */

+#define ADC_CHANNEL_11_SMP                 (ADC_SMPR2_REGOFFSET | (( 3UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP11" position in register */

+#define ADC_CHANNEL_12_SMP                 (ADC_SMPR2_REGOFFSET | (( 6UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP12" position in register */

+#define ADC_CHANNEL_13_SMP                 (ADC_SMPR2_REGOFFSET | (( 9UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP13" position in register */

+#define ADC_CHANNEL_14_SMP                 (ADC_SMPR2_REGOFFSET | ((12UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP14" position in register */

+#define ADC_CHANNEL_15_SMP                 (ADC_SMPR2_REGOFFSET | ((15UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP15" position in register */

+#define ADC_CHANNEL_16_SMP                 (ADC_SMPR2_REGOFFSET | ((18UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP16" position in register */

+#define ADC_CHANNEL_17_SMP                 (ADC_SMPR2_REGOFFSET | ((21UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP17" position in register */

+#define ADC_CHANNEL_18_SMP                 (ADC_SMPR2_REGOFFSET | ((24UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP18" position in register */

+#define ADC_CHANNEL_19_SMP                 (ADC_SMPR2_REGOFFSET | ((27UL) << ADC_CHANNEL_SMPx_BITOFFSET_POS)) /* Value shifted is equivalent to bitfield "ADC_SMPR2_SMP19" position in register */

+

+

+/* Internal mask for ADC mode single or differential ended:                   */

+/* To select into literals LL_ADC_SINGLE_ENDED or LL_ADC_SINGLE_DIFFERENTIAL  */

+/* the relevant bits for:                                                     */

+/* (concatenation of multiple bits used in different registers)               */

+/* - ADC calibration: calibration start, calibration factor get or set        */

+/* - ADC channels: set each ADC channel ending mode                           */

+#define ADC_SINGLEDIFF_CALIB_START_MASK    (ADC_CR_ADCALDIF)

+#define ADC_SINGLEDIFF_CALIB_FACTOR_MASK   (ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S)

+#define ADC_SINGLEDIFF_CHANNEL_MASK        (ADC_CHANNEL_ID_BITFIELD_MASK) /* Equivalent to ADC_DIFSEL_DIFSEL */

+#define ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK  (ADC_CALFACT_CALFACT_S_4 | ADC_CALFACT_CALFACT_S_3) /* Bits chosen to perform of shift when single mode is selected, shift value out of channels bits range. */

+#define ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK   (0x00010000UL)                           /* Selection of 1 bit to discriminate differential mode: mask of bit */

+#define ADC_SINGLEDIFF_CALIB_F_BIT_D_POS    (16UL)                                   /* Selection of 1 bit to discriminate differential mode: position of bit */

+#define ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4 (ADC_SINGLEDIFF_CALIB_F_BIT_D_POS - 4UL) /* Shift of bit ADC_SINGLEDIFF_CALIB_F_BIT_D to position to perform a shift of 4 ranks */

+

+/* Internal mask for ADC analog watchdog:                                     */

+/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for:     */

+/* (concatenation of multiple bits used in different analog watchdogs,        */

+/* (feature of several watchdogs not available on all STM32 families)).       */

+/* - analog watchdog 1: monitored channel defined by number,                  */

+/*   selection of ADC group (ADC groups regular and-or injected).             */

+/* - analog watchdog 2 and 3: monitored channel defined by bitfield, no       */

+/*   selection on groups.                                                     */

+

+/* Internal register offset for ADC analog watchdog channel configuration */

+#define ADC_AWD_CR1_REGOFFSET              (0x00000000UL)

+#define ADC_AWD_CR2_REGOFFSET              (0x00100000UL)

+#define ADC_AWD_CR3_REGOFFSET              (0x00200000UL)

+

+/* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */

+/* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */

+#define ADC_AWD_CR12_REGOFFSETGAP_MASK     (ADC_AWD2CR_AWD2CH_0)

+#define ADC_AWD_CR12_REGOFFSETGAP_VAL      (0x00000024UL)

+

+#define ADC_AWD_CRX_REGOFFSET_MASK         (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET)

+

+#define ADC_AWD_CR1_CHANNEL_MASK           (ADC_CFGR_AWD1CH | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

+#define ADC_AWD_CR23_CHANNEL_MASK          (ADC_AWD2CR_AWD2CH)

+#define ADC_AWD_CR_ALL_CHANNEL_MASK        (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK)

+

+#define ADC_AWD_CRX_REGOFFSET_POS          (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET in ADC_AWD_CRX_REGOFFSET_MASK */

+

+/* Internal register offset for ADC analog watchdog threshold configuration */

+#define ADC_AWD_TR1_REGOFFSET              (ADC_AWD_CR1_REGOFFSET)

+#define ADC_AWD_TR2_REGOFFSET              (ADC_AWD_CR2_REGOFFSET)

+#define ADC_AWD_TR3_REGOFFSET              (ADC_AWD_CR3_REGOFFSET)

+#define ADC_AWD_TRX_REGOFFSET_MASK         (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET)

+#define ADC_AWD_TRX_REGOFFSET_POS          (ADC_AWD_CRX_REGOFFSET_POS)     /* Position of bits ADC_TRx_REGOFFSET in ADC_AWD_TRX_REGOFFSET_MASK */

+

+/* Register offset gap between AWD1 and AWD2-AWD3 thresholds registers */

+/* (Set separately as ADC_AWD_TRX_REGOFFSET to spare 32 bits space */

+#define ADC_AWD_TR12_REGOFFSETGAP_MASK     (ADC_AWD2CR_AWD2CH_0)

+#define ADC_AWD_TR12_REGOFFSETGAP_VAL      (0x00000022UL)

+

+/* Legacy literals */

+#define LL_ADC_AWD1_TR                      LL_ADC_AWD1

+#define LL_ADC_AWD2_TR                      LL_ADC_AWD2

+#define LL_ADC_AWD3_TR                      LL_ADC_AWD3

+

+/* Internal mask for ADC offset:                                              */

+/* Internal register offset for ADC offset number configuration */

+#define ADC_OFR1_REGOFFSET                 (0x00000000UL)

+#define ADC_OFR2_REGOFFSET                 (0x00000001UL)

+#define ADC_OFR3_REGOFFSET                 (0x00000002UL)

+#define ADC_OFR4_REGOFFSET                 (0x00000003UL)

+#define ADC_OFRx_REGOFFSET_MASK            (ADC_OFR1_REGOFFSET | ADC_OFR2_REGOFFSET | ADC_OFR3_REGOFFSET | ADC_OFR4_REGOFFSET)

+

+

+/* ADC registers bits positions */

+#define ADC_CFGR_RES_BITOFFSET_POS         (ADC_CFGR_RES_Pos)

+#define ADC_CFGR_AWD1SGL_BITOFFSET_POS     (ADC_CFGR_AWD1SGL_Pos)

+#define ADC_CFGR_AWD1EN_BITOFFSET_POS      (ADC_CFGR_AWD1EN_Pos)

+#define ADC_CFGR_JAWD1EN_BITOFFSET_POS     (ADC_CFGR_JAWD1EN_Pos)

+

+

+/* ADC registers bits groups */

+#define ADC_CR_BITS_PROPERTY_RS            (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */

+

+

+/* ADC internal channels related definitions */

+/* Internal voltage reference VrefInt */

+#define VREFINT_CAL_ADDR                   ((uint16_t*) (0x1FF1E860UL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */

+#define VREFINT_CAL_VREF                   (3300UL)                     /* Analog voltage reference (Vref+) value with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */

+/* Temperature sensor */

+#define TEMPSENSOR_CAL1_ADDR               ((uint16_t*) (0x1FF1E820UL)) /* Internal temperature sensor, address of parameter TS_CAL1: On STM32H7, temperature sensor ADC raw data acquired at temperature  30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */

+#define TEMPSENSOR_CAL2_ADDR               ((uint16_t*) (0x1FF1E840UL)) /* Internal temperature sensor, address of parameter TS_CAL2: On STM32H7, temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */

+#define TEMPSENSOR_CAL1_TEMP               (30L)                        /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */

+#define TEMPSENSOR_CAL2_TEMP               (110L)                       /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */

+#define TEMPSENSOR_CAL_VREFANALOG          (3300UL)                     /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */

+

+

+/* Registers addresses with ADC linearity calibration content (programmed during device production, specific to each device) */

+#define ADC_LINEAR_CALIB_REG_1_ADDR ((uint32_t*) (0x1FF1EC00UL))

+#define ADC_LINEAR_CALIB_REG_2_ADDR ((uint32_t*) (0x1FF1EC04UL))

+#define ADC_LINEAR_CALIB_REG_3_ADDR ((uint32_t*) (0x1FF1EC08UL))

+#define ADC_LINEAR_CALIB_REG_4_ADDR ((uint32_t*) (0x1FF1EC0CUL))

+#define ADC_LINEAR_CALIB_REG_5_ADDR ((uint32_t*) (0x1FF1EC10UL))

+#define ADC_LINEAR_CALIB_REG_6_ADDR ((uint32_t*) (0x1FF1EC14UL))

+#define ADC_LINEAR_CALIB_REG_COUNT  (6UL)

+/**

+  * @}

+  */

+

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup ADC_LL_Private_Macros ADC Private Macros

+  * @{

+  */

+

+/**

+  * @brief  Driver macro reserved for internal use: set a pointer to

+  *         a register from a register basis from which an offset

+  *         is applied.

+  * @param  __REG__ Register basis from which the offset is applied.

+  * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).

+  * @retval Pointer to register address

+  */

+#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \

+  ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))

+

+/**

+  * @}

+  */

+

+

+/* Exported types ------------------------------------------------------------*/

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure

+  * @{

+  */

+

+/**

+  * @brief  Structure definition of some features of ADC common parameters

+  *         and multimode

+  *         (all ADC instances belonging to the same ADC common instance).

+  * @note   The setting of these parameters by function @ref LL_ADC_CommonInit()

+  *         is conditioned to ADC instances state (all ADC instances

+  *         sharing the same ADC common instance):

+  *         All ADC instances sharing the same ADC common instance must be

+  *         disabled.

+  */

+typedef struct

+{

+  uint32_t CommonClock;                 /*!< Set parameter common to several ADC: Clock source and prescaler.

+                                             This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE

+                                             @note On this STM32 serie, if ADC group injected is used, some

+                                                   clock ratio constraints between ADC clock and AHB clock

+                                                   must be respected. Refer to reference manual.

+

+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetCommonClock(). */

+

+  uint32_t Multimode;                   /*!< Set ADC multimode configuration to operate in independent mode or multimode (for devices with several ADC instances).

+                                             This parameter can be a value of @ref ADC_LL_EC_MULTI_MODE

+

+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultimode(). */

+

+  uint32_t MultiDMATransfer;            /*!< Set ADC dual ADC mode DMA transfer data format: Each DMA, 32 down to 10-bits or 8-bits resolution.

+                                             This parameter can be a value of @ref ADC_LL_EC_MULTI_DMA_TRANSFER

+

+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiDMATransfer(). */

+

+  uint32_t MultiTwoSamplingDelay;       /*!< Set ADC multimode delay between 2 sampling phases.

+                                             This parameter can be a value of @ref ADC_LL_EC_MULTI_TWOSMP_DELAY

+

+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetMultiTwoSamplingDelay(). */

+

+} LL_ADC_CommonInitTypeDef;

+

+/**

+  * @brief  Structure definition of some features of ADC instance.

+  * @note   These parameters have an impact on ADC scope: ADC instance.

+  *         Affects both group regular and group injected (availability

+  *         of ADC group injected depends on STM32 families).

+  *         Refer to corresponding unitary functions into

+  *         @ref ADC_LL_EF_Configuration_ADC_Instance .

+  * @note   The setting of these parameters by function @ref LL_ADC_Init()

+  *         is conditioned to ADC state:

+  *         ADC instance must be disabled.

+  *         This condition is applied to all ADC features, for efficiency

+  *         and compatibility over all STM32 families. However, the different

+  *         features can be set under different ADC state conditions

+  *         (setting possible with ADC enabled without conversion on going,

+  *         ADC enabled with conversion on going, ...)

+  *         Each feature can be updated afterwards with a unitary function

+  *         and potentially with ADC in a different state than disabled,

+  *         refer to description of each function for setting

+  *         conditioned to ADC state.

+  */

+typedef struct

+{

+  uint32_t Resolution;                  /*!< Set ADC resolution.

+                                             This parameter can be a value of @ref ADC_LL_EC_RESOLUTION

+

+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */

+

+  uint32_t LeftBitShift;                /*!< Configures the left shifting applied to the final result with or without oversampling.

+                                             This parameter can be a value of @ref ADC_LL_EC_LEFT_BIT_SHIFT. */

+

+  uint32_t LowPowerMode;                /*!< Set ADC low power mode.

+                                             This parameter can be a value of @ref ADC_LL_EC_LP_MODE

+

+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */

+

+} LL_ADC_InitTypeDef;

+

+/**

+  * @brief  Structure definition of some features of ADC group regular.

+  * @note   These parameters have an impact on ADC scope: ADC group regular.

+  *         Refer to corresponding unitary functions into

+  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular

+  *         (functions with prefix "REG").

+  * @note   The setting of these parameters by function @ref LL_ADC_REG_Init()

+  *         is conditioned to ADC state:

+  *         ADC instance must be disabled.

+  *         This condition is applied to all ADC features, for efficiency

+  *         and compatibility over all STM32 families. However, the different

+  *         features can be set under different ADC state conditions

+  *         (setting possible with ADC enabled without conversion on going,

+  *         ADC enabled with conversion on going, ...)

+  *         Each feature can be updated afterwards with a unitary function

+  *         and potentially with ADC in a different state than disabled,

+  *         refer to description of each function for setting

+  *         conditioned to ADC state.

+  */

+typedef struct

+{

+  uint32_t TriggerSource;               /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).

+                                             This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE

+                                             @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge

+                                                   (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).

+                                                   In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge().

+

+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */

+

+  uint32_t SequencerLength;             /*!< Set ADC group regular sequencer length.

+                                             This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH

+

+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerLength(). */

+

+  uint32_t SequencerDiscont;            /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

+                                             This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE

+                                             @note This parameter has an effect only if group regular sequencer is enabled

+                                                   (scan length of 2 ranks or more).

+

+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */

+

+  uint32_t ContinuousMode;              /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically).

+                                             This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE

+                                             Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode.

+

+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */

+

+  uint32_t DataTransferMode;            /*!< Set ADC group regular conversion data transfer mode: no transfer, transfer by DMA (Limited/Unlimited) or DFSDM.

+                                             This parameter can be a value of @ref ADC_LL_EC_REG_DATA_TRANSFER_MODE

+

+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDataTransferMode(). */

+

+  uint32_t Overrun;                     /*!< Set ADC group regular behavior in case of overrun:

+                                             data preserved or overwritten.

+                                             This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR

+

+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */

+

+} LL_ADC_REG_InitTypeDef;

+

+/**

+  * @brief  Structure definition of some features of ADC group injected.

+  * @note   These parameters have an impact on ADC scope: ADC group injected.

+  *         Refer to corresponding unitary functions into

+  *         @ref ADC_LL_EF_Configuration_ADC_Group_Regular

+  *         (functions with prefix "INJ").

+  * @note   The setting of these parameters by function @ref LL_ADC_INJ_Init()

+  *         is conditioned to ADC state:

+  *         ADC instance must be disabled.

+  *         This condition is applied to all ADC features, for efficiency

+  *         and compatibility over all STM32 families. However, the different

+  *         features can be set under different ADC state conditions

+  *         (setting possible with ADC enabled without conversion on going,

+  *         ADC enabled with conversion on going, ...)

+  *         Each feature can be updated afterwards with a unitary function

+  *         and potentially with ADC in a different state than disabled,

+  *         refer to description of each function for setting

+  *         conditioned to ADC state.

+  */

+typedef struct

+{

+  uint32_t TriggerSource;               /*!< Set ADC group injected conversion trigger source: internal (SW start) or from external peripheral (timer event, external interrupt line).

+                                             This parameter can be a value of @ref ADC_LL_EC_INJ_TRIGGER_SOURCE

+                                             @note On this STM32 serie, setting trigger source to external trigger also set trigger polarity to rising edge

+                                                   (default setting for compatibility with some ADC on other STM32 families having this setting set by HW default value).

+                                                   In case of need to modify trigger edge, use function @ref LL_ADC_INJ_SetTriggerEdge().

+

+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTriggerSource(). */

+

+  uint32_t SequencerLength;             /*!< Set ADC group injected sequencer length.

+                                             This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_SCAN_LENGTH

+

+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerLength(). */

+

+  uint32_t SequencerDiscont;            /*!< Set ADC group injected sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks.

+                                             This parameter can be a value of @ref ADC_LL_EC_INJ_SEQ_DISCONT_MODE

+                                             @note This parameter has an effect only if group injected sequencer is enabled

+                                                   (scan length of 2 ranks or more).

+

+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetSequencerDiscont(). */

+

+  uint32_t TrigAuto;                    /*!< Set ADC group injected conversion trigger: independent or from ADC group regular.

+                                             This parameter can be a value of @ref ADC_LL_EC_INJ_TRIG_AUTO

+                                             Note: This parameter must be set to set to independent trigger if injected trigger source is set to an external trigger.

+

+                                             This feature can be modified afterwards using unitary function @ref LL_ADC_INJ_SetTrigAuto(). */

+

+} LL_ADC_INJ_InitTypeDef;

+

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants

+  * @{

+  */

+

+/** @defgroup ADC_LL_EC_FLAG ADC flags

+  * @brief    Flags defines which can be used with LL_ADC_ReadReg function

+  * @{

+  */

+#define LL_ADC_FLAG_ADRDY                  ADC_ISR_ADRDY      /*!< ADC flag ADC instance ready */

+#define LL_ADC_FLAG_EOC                    ADC_ISR_EOC        /*!< ADC flag ADC group regular end of unitary conversion */

+#define LL_ADC_FLAG_EOS                    ADC_ISR_EOS        /*!< ADC flag ADC group regular end of sequence conversions */

+#define LL_ADC_FLAG_OVR                    ADC_ISR_OVR        /*!< ADC flag ADC group regular overrun */

+#define LL_ADC_FLAG_EOSMP                  ADC_ISR_EOSMP      /*!< ADC flag ADC group regular end of sampling phase */

+#define LL_ADC_FLAG_JEOC                   ADC_ISR_JEOC       /*!< ADC flag ADC group injected end of unitary conversion */

+#define LL_ADC_FLAG_JEOS                   ADC_ISR_JEOS       /*!< ADC flag ADC group injected end of sequence conversions */

+#define LL_ADC_FLAG_JQOVF                  ADC_ISR_JQOVF      /*!< ADC flag ADC group injected contexts queue overflow */

+#define LL_ADC_FLAG_AWD1                   ADC_ISR_AWD1       /*!< ADC flag ADC analog watchdog 1 */

+#define LL_ADC_FLAG_AWD2                   ADC_ISR_AWD2       /*!< ADC flag ADC analog watchdog 2 */

+#define LL_ADC_FLAG_AWD3                   ADC_ISR_AWD3       /*!< ADC flag ADC analog watchdog 3 */

+#define LL_ADC_FLAG_ADRDY_MST              ADC_CSR_ADRDY_MST  /*!< ADC flag ADC multimode master instance ready */

+#define LL_ADC_FLAG_ADRDY_SLV              ADC_CSR_ADRDY_SLV  /*!< ADC flag ADC multimode slave instance ready */

+#define LL_ADC_FLAG_EOC_MST                ADC_CSR_EOC_MST    /*!< ADC flag ADC multimode master group regular end of unitary conversion */

+#define LL_ADC_FLAG_EOC_SLV                ADC_CSR_EOC_SLV    /*!< ADC flag ADC multimode slave group regular end of unitary conversion */

+#define LL_ADC_FLAG_EOS_MST                ADC_CSR_EOS_MST    /*!< ADC flag ADC multimode master group regular end of sequence conversions */

+#define LL_ADC_FLAG_EOS_SLV                ADC_CSR_EOS_SLV    /*!< ADC flag ADC multimode slave group regular end of sequence conversions */

+#define LL_ADC_FLAG_OVR_MST                ADC_CSR_OVR_MST    /*!< ADC flag ADC multimode master group regular overrun */

+#define LL_ADC_FLAG_OVR_SLV                ADC_CSR_OVR_SLV    /*!< ADC flag ADC multimode slave group regular overrun */

+#define LL_ADC_FLAG_EOSMP_MST              ADC_CSR_EOSMP_MST  /*!< ADC flag ADC multimode master group regular end of sampling phase */

+#define LL_ADC_FLAG_EOSMP_SLV              ADC_CSR_EOSMP_SLV  /*!< ADC flag ADC multimode slave group regular end of sampling phase */

+#define LL_ADC_FLAG_JEOC_MST               ADC_CSR_JEOC_MST   /*!< ADC flag ADC multimode master group injected end of unitary conversion */

+#define LL_ADC_FLAG_JEOC_SLV               ADC_CSR_JEOC_SLV   /*!< ADC flag ADC multimode slave group injected end of unitary conversion */

+#define LL_ADC_FLAG_JEOS_MST               ADC_CSR_JEOS_MST   /*!< ADC flag ADC multimode master group injected end of sequence conversions */

+#define LL_ADC_FLAG_JEOS_SLV               ADC_CSR_JEOS_SLV   /*!< ADC flag ADC multimode slave group injected end of sequence conversions */

+#define LL_ADC_FLAG_JQOVF_MST              ADC_CSR_JQOVF_MST  /*!< ADC flag ADC multimode master group injected contexts queue overflow */

+#define LL_ADC_FLAG_JQOVF_SLV              ADC_CSR_JQOVF_SLV  /*!< ADC flag ADC multimode slave group injected contexts queue overflow */

+#define LL_ADC_FLAG_AWD1_MST               ADC_CSR_AWD1_MST   /*!< ADC flag ADC multimode master analog watchdog 1 of the ADC master */

+#define LL_ADC_FLAG_AWD1_SLV               ADC_CSR_AWD1_SLV   /*!< ADC flag ADC multimode slave analog watchdog 1 of the ADC slave */

+#define LL_ADC_FLAG_AWD2_MST               ADC_CSR_AWD2_MST   /*!< ADC flag ADC multimode master analog watchdog 2 of the ADC master */

+#define LL_ADC_FLAG_AWD2_SLV               ADC_CSR_AWD2_SLV   /*!< ADC flag ADC multimode slave analog watchdog 2 of the ADC slave */

+#define LL_ADC_FLAG_AWD3_MST               ADC_CSR_AWD3_MST   /*!< ADC flag ADC multimode master analog watchdog 3 of the ADC master */

+#define LL_ADC_FLAG_AWD3_SLV               ADC_CSR_AWD3_SLV   /*!< ADC flag ADC multimode slave analog watchdog 3 of the ADC slave */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable)

+  * @brief    IT defines which can be used with LL_ADC_ReadReg and  LL_ADC_WriteReg functions

+  * @{

+  */

+#define LL_ADC_IT_ADRDY                    ADC_IER_ADRDYIE    /*!< ADC interruption ADC instance ready */

+#define LL_ADC_IT_EOC                      ADC_IER_EOCIE      /*!< ADC interruption ADC group regular end of unitary conversion */

+#define LL_ADC_IT_EOS                      ADC_IER_EOSIE      /*!< ADC interruption ADC group regular end of sequence conversions */

+#define LL_ADC_IT_OVR                      ADC_IER_OVRIE      /*!< ADC interruption ADC group regular overrun */

+#define LL_ADC_IT_EOSMP                    ADC_IER_EOSMPIE    /*!< ADC interruption ADC group regular end of sampling phase */

+#define LL_ADC_IT_JEOC                     ADC_IER_JEOCIE     /*!< ADC interruption ADC group injected end of unitary conversion */

+#define LL_ADC_IT_JEOS                     ADC_IER_JEOSIE     /*!< ADC interruption ADC group injected end of sequence conversions */

+#define LL_ADC_IT_JQOVF                    ADC_IER_JQOVFIE    /*!< ADC interruption ADC group injected contexts queue overflow */

+#define LL_ADC_IT_AWD1                     ADC_IER_AWD1IE     /*!< ADC interruption ADC analog watchdog 1 */

+#define LL_ADC_IT_AWD2                     ADC_IER_AWD2IE     /*!< ADC interruption ADC analog watchdog 2 */

+#define LL_ADC_IT_AWD3                     ADC_IER_AWD3IE     /*!< ADC interruption ADC analog watchdog 3 */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_REGISTERS  ADC registers compliant with specific purpose

+  * @{

+  */

+/* List of ADC registers intended to be used (most commonly) with             */

+/* DMA transfer.                                                              */

+/* Refer to function @ref LL_ADC_DMA_GetRegAddr().                            */

+#define LL_ADC_DMA_REG_REGULAR_DATA          (0x00000000UL) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */

+#define LL_ADC_DMA_REG_REGULAR_DATA_MULTI    (0x00000001UL) /* ADC group regular conversion data register (corresponding to register CDR) to be used with ADC configured in multimode (available on STM32 devices with several ADC instances). Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadMultiConversionData32() */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE  ADC common - Clock source

+  * @{

+  */

+#define LL_ADC_CLOCK_SYNC_PCLK_DIV1        (ADC_CCR_CKMODE_0)                                    /*!< ADC synchronous clock derived from AHB clock without prescaler */

+#define LL_ADC_CLOCK_SYNC_PCLK_DIV2        (ADC_CCR_CKMODE_1                   )                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */

+#define LL_ADC_CLOCK_SYNC_PCLK_DIV4        (ADC_CCR_CKMODE_1 | ADC_CCR_CKMODE_0)                 /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */

+#define LL_ADC_CLOCK_ASYNC_DIV1            (0x00000000UL)                                        /*!< ADC asynchronous clock without prescaler */

+#define LL_ADC_CLOCK_ASYNC_DIV2            (ADC_CCR_PRESC_0)                                     /*!< ADC asynchronous clock with prescaler division by 2   */

+#define LL_ADC_CLOCK_ASYNC_DIV4            (ADC_CCR_PRESC_1                  )                   /*!< ADC asynchronous clock with prescaler division by 4   */

+#define LL_ADC_CLOCK_ASYNC_DIV6            (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0)                   /*!< ADC asynchronous clock with prescaler division by 6   */

+#define LL_ADC_CLOCK_ASYNC_DIV8            (ADC_CCR_PRESC_2                                    ) /*!< ADC asynchronous clock with prescaler division by 8   */

+#define LL_ADC_CLOCK_ASYNC_DIV10           (ADC_CCR_PRESC_2                   | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10  */

+#define LL_ADC_CLOCK_ASYNC_DIV12           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1                  ) /*!< ADC asynchronous clock with prescaler division by 12  */

+#define LL_ADC_CLOCK_ASYNC_DIV16           (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16  */

+#define LL_ADC_CLOCK_ASYNC_DIV32           (ADC_CCR_PRESC_3)                                     /*!< ADC asynchronous clock with prescaler division by 32  */

+#define LL_ADC_CLOCK_ASYNC_DIV64           (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0)                   /*!< ADC asynchronous clock with prescaler division by 64  */

+#define LL_ADC_CLOCK_ASYNC_DIV128          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1)                   /*!< ADC asynchronous clock with prescaler division by 128 */

+#define LL_ADC_CLOCK_ASYNC_DIV256          (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256 */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL  ADC common - Measurement path to internal channels

+  * @{

+  */

+/* Note: Other measurement paths to internal channels may be available        */

+/*       (connections to other peripherals).                                  */

+/*       If they are not listed below, they do not require any specific       */

+/*       path enable. In this case, Access to measurement path is done        */

+/*       only by selecting the corresponding ADC internal channel.            */

+#define LL_ADC_PATH_INTERNAL_NONE          (0x00000000UL)         /*!< ADC measurement pathes all disabled */

+#define LL_ADC_PATH_INTERNAL_VREFINT       (ADC_CCR_VREFEN)       /*!< ADC measurement path to internal channel VrefInt */

+#define LL_ADC_PATH_INTERNAL_TEMPSENSOR    (ADC_CCR_TSEN)         /*!< ADC measurement path to internal channel temperature sensor */

+#define LL_ADC_PATH_INTERNAL_VBAT          (ADC_CCR_VBATEN)       /*!< ADC measurement path to internal channel Vbat */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_BOOST_MODE ADC instance - Boost mode

+  * @{

+  */

+#define LL_ADC_BOOST_MODE_6MHZ25   (0x00000000UL)                                            /*!< Boost mode is configured for frequency <= 6.25Mhz           */

+#define LL_ADC_BOOST_MODE_12MHZ5   (                                        ADC_CR_BOOST_0)  /*!< Boost mode is configured for 6.25Mhz < frequency <= 12.5Mhz */

+#define LL_ADC_BOOST_MODE_20MHZ    (                       ADC_CR_BOOST_1                 )  /*!< Boost mode is configured for 12.5Mhz < frequency <= 20Mhz   */

+#define LL_ADC_BOOST_MODE_25MHZ    ((ADC_CR_BOOST_0 <<2) | ADC_CR_BOOST_1                 )  /*!< Boost mode is configured for 20Mhz   < frequency <= 25Mhz   */

+#define LL_ADC_BOOST_MODE_50MHZ    ((ADC_CR_BOOST_0 <<2) | ADC_CR_BOOST_1 | ADC_CR_BOOST_0)  /*!< Boost mode is configured for frequency > 25Mhz              */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_CALIBRATION_OFFSET_LINEARITY  ADC instance - Calibration mode for offset and linearity

+  * @{

+  */

+#define LL_ADC_CALIB_OFFSET                (ADC_CALIB_FACTOR_OFFSET_REGOFFSET)                      /*!< Calibration of ADC offset. Duration of calibration of offset duration: 1280 ADC clock cycles. For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes. */

+#define LL_ADC_CALIB_LINEARITY             (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET)                   /*!< Calibration of ADC linearity. Duration of calibration of linearity: 15104 ADC clock cycles. For devices with differential mode available: Calibration of linearity is common to both single-ended and differential modes. */

+#define LL_ADC_CALIB_OFFSET_LINEARITY      (ADC_CALIB_FACTOR_LINEARITY_REGOFFSET | ADC_CR_ADCALLIN) /*!< Calibration of ADC offset and linearity. Duration of calibration of offset and linearity: 16384 ADC clock cycles. For devices with differential mode available: Calibration of offset is specific to each of single-ended and differential modes, calibration of linearity is common to both single-ended and differential modes. */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_CALIBRATION_LINEARITY_WORD  ADC instance - Calibration linearity words

+  * @{

+  */

+#define LL_ADC_CALIB_LINEARITY_WORD1       (ADC_CR_LINCALRDYW1)    /*!< ADC calibration linearity word 1 */

+#define LL_ADC_CALIB_LINEARITY_WORD2       (ADC_CR_LINCALRDYW2)    /*!< ADC calibration linearity word 2 */

+#define LL_ADC_CALIB_LINEARITY_WORD3       (ADC_CR_LINCALRDYW3)    /*!< ADC calibration linearity word 3 */

+#define LL_ADC_CALIB_LINEARITY_WORD4       (ADC_CR_LINCALRDYW4)    /*!< ADC calibration linearity word 4 */

+#define LL_ADC_CALIB_LINEARITY_WORD5       (ADC_CR_LINCALRDYW5)    /*!< ADC calibration linearity word 5 */

+#define LL_ADC_CALIB_LINEARITY_WORD6       (ADC_CR_LINCALRDYW6)    /*!< ADC calibration linearity word 6 */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_RESOLUTION  ADC instance - Resolution

+  * @{

+  */

+#define LL_ADC_RESOLUTION_16B              (0x00000000UL)                                   /*!< ADC resolution 16 bits */

+#define LL_ADC_RESOLUTION_14B              (                                ADC_CFGR_RES_0) /*!< ADC resolution 12 bits */

+#define LL_ADC_RESOLUTION_12B              (               ADC_CFGR_RES_1                 ) /*!< ADC resolution 12 bits */

+#define LL_ADC_RESOLUTION_10B              (               ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution 10 bits */

+#if defined (ADC_VER_V5_3)

+#define LL_ADC_RESOLUTION_8B               (ADC_CFGR_RES_2|ADC_CFGR_RES_1 | ADC_CFGR_RES_0) /*!< ADC resolution  8 bits */

+#else

+#define LL_ADC_RESOLUTION_8B               (ADC_CFGR_RES_2                                ) /*!< ADC resolution  8 bits */

+#endif

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_LEFT_BIT_SHIFT   ADC left Shift

+  * @{

+  */

+#define LL_ADC_LEFT_BIT_SHIFT_NONE  (0x00000000UL)                                                                       /*!< ADC no bit shift left applied on the final ADC convesion data */

+#define LL_ADC_LEFT_BIT_SHIFT_1     (ADC_CFGR2_LSHIFT_0)                                                                 /*!< ADC 1 bit shift left applied on the final ADC convesion data */

+#define LL_ADC_LEFT_BIT_SHIFT_2     (ADC_CFGR2_LSHIFT_1)                                                                 /*!< ADC 2 bits shift left applied on the final ADC convesion data */

+#define LL_ADC_LEFT_BIT_SHIFT_3     (ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)                                            /*!< ADC 3 bits shift left applied on the final ADC convesion data */

+#define LL_ADC_LEFT_BIT_SHIFT_4     (ADC_CFGR2_LSHIFT_2)                                                                 /*!< ADC 4 bits shift left applied on the final ADC convesion data */

+#define LL_ADC_LEFT_BIT_SHIFT_5     (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0)                                            /*!< ADC 5 bits shift left applied on the final ADC convesion data */

+#define LL_ADC_LEFT_BIT_SHIFT_6     (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1)                                            /*!< ADC 6 bits shift left applied on the final ADC convesion data */

+#define LL_ADC_LEFT_BIT_SHIFT_7     (ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)                       /*!< ADC 7 bits shift left applied on the final ADC convesion data */

+#define LL_ADC_LEFT_BIT_SHIFT_8     (ADC_CFGR2_LSHIFT_3)                                                                 /*!< ADC 8 bits shift left applied on the final ADC convesion data */

+#define LL_ADC_LEFT_BIT_SHIFT_9     (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_0)                                            /*!< ADC 9 bits shift left applied on the final ADC convesion data */

+#define LL_ADC_LEFT_BIT_SHIFT_10    (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1)                                            /*!< ADC 10 bits shift left applied on the final ADC convesion data */

+#define LL_ADC_LEFT_BIT_SHIFT_11    (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)                       /*!< ADC 11 bits shift left applied on the final ADC convesion data */

+#define LL_ADC_LEFT_BIT_SHIFT_12    (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2)                                            /*!< ADC 12 bits shift left applied on the final ADC convesion data */

+#define LL_ADC_LEFT_BIT_SHIFT_13    (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_0)                       /*!< ADC 13 bits shift left applied on the final ADC convesion data */

+#define LL_ADC_LEFT_BIT_SHIFT_14    (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1)                       /*!< ADC 14 bits shift left applied on the final ADC convesion data */

+#define LL_ADC_LEFT_BIT_SHIFT_15    (ADC_CFGR2_LSHIFT_3 | ADC_CFGR2_LSHIFT_2 | ADC_CFGR2_LSHIFT_1 | ADC_CFGR2_LSHIFT_0)  /*!< ADC 15 bits shift left applied on the final ADC convesion data */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_LP_MODE  ADC instance - Low power mode

+  * @{

+  */

+#define LL_ADC_LP_MODE_NONE                (0x00000000UL)                      /*!< No ADC low power mode activated */

+#define LL_ADC_LP_AUTOWAIT                 (ADC_CFGR_AUTDLY)                   /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_OFFSET_NB  ADC instance - Offset number

+  * @{

+  */

+#define LL_ADC_OFFSET_1                    ADC_OFR1_REGOFFSET /*!< ADC offset number 1: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */

+#define LL_ADC_OFFSET_2                    ADC_OFR2_REGOFFSET /*!< ADC offset number 2: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */

+#define LL_ADC_OFFSET_3                    ADC_OFR3_REGOFFSET /*!< ADC offset number 3: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */

+#define LL_ADC_OFFSET_4                    ADC_OFR4_REGOFFSET /*!< ADC offset number 4: ADC channel and offset level to which the offset programmed will be applied (independently of channel mapped on ADC group regular or group injected) */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_OFFSET_SIGNED_SATURATION ADC instance - Offset signed saturation mode

+  * @{

+  */

+#define LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE   (0x00000000UL)   /*!< ADC offset signed saturation is disabled (among ADC selected offset number 1, 2, 3 or 4) */

+#define LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE    (ADC_OFR1_SSATE) /*!< ADC offset signed saturation is enabled (among ADC selected offset number 1, 2, 3 or 4) */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_OFFSET_RSHIFT ADC instance - Offset right shift

+  * @{

+  */

+#define LL_ADC_OFFSET_RSHIFT_DISABLE   (0x00000000UL)      /*!< ADC offset right shift is disabled (among ADC selected offset number 1, 2, 3 or 4) */

+#define LL_ADC_OFFSET_RSHIFT_ENABLE    (ADC_CFGR2_RSHIFT1) /*!< ADC offset right shif is enabled (among ADC selected offset number 1, 2, 3 or 4) */

+/**

+  * @}

+  */

+/** @defgroup ADC_LL_EC_GROUPS  ADC instance - Groups

+  * @{

+  */

+#define LL_ADC_GROUP_REGULAR               (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */

+#define LL_ADC_GROUP_INJECTED              (0x00000002UL) /*!< ADC group injected (not available on all STM32 devices)*/

+#define LL_ADC_GROUP_REGULAR_INJECTED      (0x00000003UL) /*!< ADC both groups regular and injected */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_CHANNEL  ADC instance - Channel number

+  * @{

+  */

+#define LL_ADC_CHANNEL_0                   (ADC_CHANNEL_0_NUMBER  | ADC_CHANNEL_0_SMP  | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0  */

+#define LL_ADC_CHANNEL_1                   (ADC_CHANNEL_1_NUMBER  | ADC_CHANNEL_1_SMP  | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1  */

+#define LL_ADC_CHANNEL_2                   (ADC_CHANNEL_2_NUMBER  | ADC_CHANNEL_2_SMP  | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2  */

+#define LL_ADC_CHANNEL_3                   (ADC_CHANNEL_3_NUMBER  | ADC_CHANNEL_3_SMP  | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3  */

+#define LL_ADC_CHANNEL_4                   (ADC_CHANNEL_4_NUMBER  | ADC_CHANNEL_4_SMP  | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4  */

+#define LL_ADC_CHANNEL_5                   (ADC_CHANNEL_5_NUMBER  | ADC_CHANNEL_5_SMP  | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5  */

+#define LL_ADC_CHANNEL_6                   (ADC_CHANNEL_6_NUMBER  | ADC_CHANNEL_6_SMP  | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6  */

+#define LL_ADC_CHANNEL_7                   (ADC_CHANNEL_7_NUMBER  | ADC_CHANNEL_7_SMP  | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7  */

+#define LL_ADC_CHANNEL_8                   (ADC_CHANNEL_8_NUMBER  | ADC_CHANNEL_8_SMP  | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8  */

+#define LL_ADC_CHANNEL_9                   (ADC_CHANNEL_9_NUMBER  | ADC_CHANNEL_9_SMP  | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9  */

+#define LL_ADC_CHANNEL_10                  (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_SMP | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */

+#define LL_ADC_CHANNEL_11                  (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_SMP | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */

+#define LL_ADC_CHANNEL_12                  (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_SMP | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */

+#define LL_ADC_CHANNEL_13                  (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_SMP | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */

+#define LL_ADC_CHANNEL_14                  (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_SMP | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */

+#define LL_ADC_CHANNEL_15                  (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_SMP | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */

+#define LL_ADC_CHANNEL_16                  (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_SMP | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */

+#define LL_ADC_CHANNEL_17                  (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_SMP | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */

+#define LL_ADC_CHANNEL_18                  (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP | ADC_CHANNEL_18_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */

+#define LL_ADC_CHANNEL_19                  (ADC_CHANNEL_19_NUMBER | ADC_CHANNEL_19_SMP | ADC_CHANNEL_19_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN19 */

+#if defined(ADC3)

+/*!< ADC3 is defined only in the case of STM32H7XX */

+#define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32H7, ADC channel available only on ADC instance: ADC3. */

+#define LL_ADC_CHANNEL_TEMPSENSOR          (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32H7, ADC channel available only on ADC instance: ADC3. */

+#define LL_ADC_CHANNEL_VBAT                (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. On STM32H7, ADC channel available only on ADC instance: ADC3. */

+#else

+/*!< Specific define for STM32H7A3xx and STM32HB3xx varieties of STM32H7XXX */

+#define LL_ADC_CHANNEL_VREFINT             (LL_ADC_CHANNEL_19 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32H7, ADC channel available only on ADC instance: ADC2. */

+#define LL_ADC_CHANNEL_TEMPSENSOR          (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32H7, ADC channel available only on ADC instance: ADC2. */

+#define LL_ADC_CHANNEL_VBAT                (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda. On STM32H7, ADC channel available only on ADC instance: ADC2. */

+#endif

+#define LL_ADC_CHANNEL_DAC1CH1_ADC2        (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */

+#define LL_ADC_CHANNEL_DAC1CH2_ADC2        (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */

+#if defined(DAC2)

+/*!< Specific define for STM32H7A3xx and STM32HB3xx varieties of STM32H7XXX */

+#define LL_ADC_CHANNEL_DAC2CH1_ADC2        (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC2 channel 1, channel specific to ADC2 */

+#endif

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE  ADC group regular - Trigger source

+  * @{

+  */

+#define LL_ADC_REG_TRIG_SOFTWARE          (0x00000000UL)                                                                                                    /*!< ADC group regular conversion trigger internal: SW start. */

+#define LL_ADC_REG_TRIG_EXT_TIM1_CH1      (ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                                                   /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

+#define LL_ADC_REG_TRIG_EXT_TIM1_CH2      (ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                               /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

+#define LL_ADC_REG_TRIG_EXT_TIM1_CH3      (ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                               /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

+#define LL_ADC_REG_TRIG_EXT_TIM2_CH2      (ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

+#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO     (ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                               /*!< ADC group regular conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */

+#define LL_ADC_REG_TRIG_EXT_TIM4_CH4      (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

+#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11   (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11 event. Trigger edge set to rising edge (default setting). */

+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO     (ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                       /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */

+#define LL_ADC_REG_TRIG_EXT_TIM8_TRGO2    (ADC_CFGR_EXTSEL_3 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                               /*!< ADC group regular conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */

+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */

+#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2    (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */

+#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                       /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */

+#define LL_ADC_REG_TRIG_EXT_TIM4_TRGO     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */

+#define LL_ADC_REG_TRIG_EXT_TIM6_TRGO     (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                       /*!< ADC group regular conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */

+#define LL_ADC_REG_TRIG_EXT_TIM15_TRGO    (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                       /*!< ADC group regular conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */

+#define LL_ADC_REG_TRIG_EXT_TIM3_CH4      (ADC_CFGR_EXTSEL_3 | ADC_CFGR_EXTSEL_2 | ADC_CFGR_EXTSEL_1 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)   /*!< ADC group regular conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG1    (ADC_CFGR_EXTSEL_4 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                                               /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG1 event. Trigger edge set to rising edge (default setting). */

+#define LL_ADC_REG_TRIG_EXT_HRTIM_TRG3    (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: HRTIM TRG2 event. Trigger edge set to rising edge (default setting). */

+#define LL_ADC_REG_TRIG_EXT_LPTIM1_OUT    (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */

+#define LL_ADC_REG_TRIG_EXT_LPTIM2_OUT    (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_1| ADC_CFGR_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                        /*!< ADC group regular conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */

+#define LL_ADC_REG_TRIG_EXT_LPTIM3_OUT    (ADC_CFGR_EXTSEL_4 | ADC_CFGR_EXTSEL_2 | ADC_REG_TRIG_EXT_EDGE_DEFAULT)                                           /*!< ADC group regular conversion trigger from external peripheral: LPTIM3 event OUT. Trigger edge set to rising edge (default setting). */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE  ADC group regular - Trigger edge

+  * @{

+  */

+#define LL_ADC_REG_TRIG_EXT_RISING         (                   ADC_CFGR_EXTEN_0)   /*!< ADC group regular conversion trigger polarity set to rising edge */

+#define LL_ADC_REG_TRIG_EXT_FALLING        (ADC_CFGR_EXTEN_1                   )   /*!< ADC group regular conversion trigger polarity set to falling edge */

+#define LL_ADC_REG_TRIG_EXT_RISINGFALLING  (ADC_CFGR_EXTEN_1 | ADC_CFGR_EXTEN_0)   /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE  ADC group regular - Continuous mode

+  * @{

+  */

+#define LL_ADC_REG_CONV_SINGLE             (0x00000000UL)          /*!< ADC conversions are performed in single mode: one conversion per trigger */

+#define LL_ADC_REG_CONV_CONTINUOUS         (ADC_CFGR_CONT)         /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_REG_DATA_TRANSFER_MODE  ADC group regular - Data transfer mode of ADC conversion data

+  * @{

+  */

+#define LL_ADC_REG_DR_TRANSFER             (0x00000000UL)                        /*!< ADC conversions are transferred to DR rigister */

+#define LL_ADC_REG_DMA_TRANSFER_LIMITED    (                   ADC_CFGR_DMNGT_0) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */

+#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED  (ADC_CFGR_DMNGT_1 | ADC_CFGR_DMNGT_0) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */

+#define LL_ADC_REG_DFSDM_TRANSFER          (ADC_CFGR_DMNGT_1                   ) /*!< ADC conversion data are transferred to DFSDM */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR  ADC group regular - Overrun behavior on conversion data

+  * @{

+  */

+#define LL_ADC_REG_OVR_DATA_PRESERVED      (0x00000000UL)         /*!< ADC group regular behavior in case of overrun: data preserved */

+#define LL_ADC_REG_OVR_DATA_OVERWRITTEN    (ADC_CFGR_OVRMOD)      /*!< ADC group regular behavior in case of overrun: data overwritten */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH  ADC group regular - Sequencer scan length

+  * @{

+  */

+#define LL_ADC_REG_SEQ_SCAN_DISABLE        (0x00000000UL)                                              /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */

+#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS  (                                             ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */

+#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS  (                              ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */

+#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS  (                              ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */

+#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS  (               ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */

+#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS  (               ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */

+#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */

+#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS  (               ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */

+#define LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS  (ADC_SQR1_L_3                                             ) /*!< ADC group regular sequencer enable with 9 ranks in the sequence */

+#define LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS (ADC_SQR1_L_3                               | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 10 ranks in the sequence */

+#define LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 11 ranks in the sequence */

+#define LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS (ADC_SQR1_L_3                | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 12 ranks in the sequence */

+#define LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                              ) /*!< ADC group regular sequencer enable with 13 ranks in the sequence */

+#define LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2                | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 14 ranks in the sequence */

+#define LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1               ) /*!< ADC group regular sequencer enable with 15 ranks in the sequence */

+#define LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS (ADC_SQR1_L_3 | ADC_SQR1_L_2 | ADC_SQR1_L_1 | ADC_SQR1_L_0) /*!< ADC group regular sequencer enable with 16 ranks in the sequence */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE  ADC group regular - Sequencer discontinuous mode

+  * @{

+  */

+#define LL_ADC_REG_SEQ_DISCONT_DISABLE     (0x00000000UL)                                                               /*!< ADC group regular sequencer discontinuous mode disable */

+#define LL_ADC_REG_SEQ_DISCONT_1RANK       (                                                               ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */

+#define LL_ADC_REG_SEQ_DISCONT_2RANKS      (                                          ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enabled with sequence interruption every 2 ranks */

+#define LL_ADC_REG_SEQ_DISCONT_3RANKS      (                     ADC_CFGR_DISCNUM_1                      | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 3 ranks */

+#define LL_ADC_REG_SEQ_DISCONT_4RANKS      (                     ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 4 ranks */

+#define LL_ADC_REG_SEQ_DISCONT_5RANKS      (ADC_CFGR_DISCNUM_2                                           | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 5 ranks */

+#define LL_ADC_REG_SEQ_DISCONT_6RANKS      (ADC_CFGR_DISCNUM_2                      | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 6 ranks */

+#define LL_ADC_REG_SEQ_DISCONT_7RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1                      | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 7 ranks */

+#define LL_ADC_REG_SEQ_DISCONT_8RANKS      (ADC_CFGR_DISCNUM_2 | ADC_CFGR_DISCNUM_1 | ADC_CFGR_DISCNUM_0 | ADC_CFGR_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every 8 ranks */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_REG_SEQ_RANKS  ADC group regular - Sequencer ranks

+  * @{

+  */

+#define LL_ADC_REG_RANK_1                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_1_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 1 */

+#define LL_ADC_REG_RANK_2                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_2_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 2 */

+#define LL_ADC_REG_RANK_3                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_3_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 3 */

+#define LL_ADC_REG_RANK_4                  (ADC_SQR1_REGOFFSET | ADC_REG_RANK_4_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 4 */

+#define LL_ADC_REG_RANK_5                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_5_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 5 */

+#define LL_ADC_REG_RANK_6                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_6_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 6 */

+#define LL_ADC_REG_RANK_7                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_7_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 7 */

+#define LL_ADC_REG_RANK_8                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_8_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 8 */

+#define LL_ADC_REG_RANK_9                  (ADC_SQR2_REGOFFSET | ADC_REG_RANK_9_SQRX_BITOFFSET_POS)  /*!< ADC group regular sequencer rank 9 */

+#define LL_ADC_REG_RANK_10                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_10_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 10 */

+#define LL_ADC_REG_RANK_11                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_11_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 11 */

+#define LL_ADC_REG_RANK_12                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_12_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 12 */

+#define LL_ADC_REG_RANK_13                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_13_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 13 */

+#define LL_ADC_REG_RANK_14                 (ADC_SQR3_REGOFFSET | ADC_REG_RANK_14_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 14 */

+#define LL_ADC_REG_RANK_15                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_15_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 15 */

+#define LL_ADC_REG_RANK_16                 (ADC_SQR4_REGOFFSET | ADC_REG_RANK_16_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 16 */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_INJ_TRIGGER_SOURCE  ADC group injected - Trigger source

+  * @{

+  */

+#define LL_ADC_INJ_TRIG_SOFTWARE           (0x00000000UL)                                                                                                         /*!< ADC group injected conversion trigger internal: SW start. */

+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO      (ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                                        /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO event. Trigger edge set to rising edge (default setting). */

+#define LL_ADC_INJ_TRIG_EXT_TIM1_CH4       (ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                   /*!< ADC group injected conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

+#define LL_ADC_INJ_TRIG_EXT_TIM2_TRGO      (ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                   /*!< ADC group injected conversion trigger from external peripheral: TIM2 TRGO event. Trigger edge set to rising edge (default setting). */

+#define LL_ADC_INJ_TRIG_EXT_TIM2_CH1       (ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                              /*!< ADC group injected conversion trigger from external peripheral: TIM2 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH4       (ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                   /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

+#define LL_ADC_INJ_TRIG_EXT_TIM4_TRGO      (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                              /*!< ADC group injected conversion trigger from external peripheral: TIM4 TRGO event. Trigger edge set to rising edge (default setting). */

+#define LL_ADC_INJ_TRIG_EXT_EXTI_LINE15    (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                              /*!< ADC group injected conversion trigger from external peripheral: external interrupt line 15. Trigger edge set to rising edge (default setting). */

+#define LL_ADC_INJ_TRIG_EXT_TIM8_CH4       (ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                         /*!< ADC group injected conversion trigger from external peripheral: TIM8 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

+#define LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2     (ADC_JSQR_JEXTSEL_3 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                   /*!< ADC group injected conversion trigger from external peripheral: TIM1 TRGO2 event. Trigger edge set to rising edge (default setting). */

+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                              /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO event. Trigger edge set to rising edge (default setting). */

+#define LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                              /*!< ADC group injected conversion trigger from external peripheral: TIM8 TRGO2 event. Trigger edge set to rising edge (default setting). */

+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH3       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                         /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

+#define LL_ADC_INJ_TRIG_EXT_TIM3_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                            /*!< ADC group injected conversion trigger from external peripheral: TIM3 TRGO event. Trigger edge set to rising edge (default setting). */

+#define LL_ADC_INJ_TRIG_EXT_TIM3_CH1       (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                         /*!< ADC group injected conversion trigger from external peripheral: TIM3 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

+#define LL_ADC_INJ_TRIG_EXT_TIM6_TRGO      (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                         /*!< ADC group injected conversion trigger from external peripheral: TIM6 TRGO event. Trigger edge set to rising edge (default setting). */

+#define LL_ADC_INJ_TRIG_EXT_TIM15_TRGO     (ADC_JSQR_JEXTSEL_3 | ADC_JSQR_JEXTSEL_2 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)    /*!< ADC group injected conversion trigger from external peripheral: TIM15 TRGO event. Trigger edge set to rising edge (default setting). */

+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2     (ADC_JSQR_JEXTSEL_4 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                                                   /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG2 event. Trigger edge set to rising edge (default setting). */

+#define LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                              /*!< ADC group injected conversion trigger from external peripheral: HRTIM1 TRG4 event. Trigger edge set to rising edge (default setting). */

+#define LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                                                              /*!< ADC group injected conversion trigger from external peripheral: LPTIM1 OUT event. Trigger edge set to rising edge (default setting). */

+#define LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_1 | ADC_JSQR_JEXTSEL_0 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                         /*!< ADC group injected conversion trigger from external peripheral: LPTIM2 OUT event. Trigger edge set to rising edge (default setting). */

+#define LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT     (ADC_JSQR_JEXTSEL_4 | ADC_JSQR_JEXTSEL_2 | ADC_INJ_TRIG_EXT_EDGE_DEFAULT)                                              /*!< ADC group injected conversion trigger from external peripheral: LPTIM3 OUT event. 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_INJ_TRIGGER_EDGE  ADC group injected - Trigger edge

+  * @{

+  */

+#define LL_ADC_INJ_TRIG_EXT_RISING         (                    ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to rising edge */

+#define LL_ADC_INJ_TRIG_EXT_FALLING        (ADC_JSQR_JEXTEN_1                    ) /*!< ADC group injected conversion trigger polarity set to falling edge */

+#define LL_ADC_INJ_TRIG_EXT_RISINGFALLING  (ADC_JSQR_JEXTEN_1 | ADC_JSQR_JEXTEN_0) /*!< ADC group injected conversion trigger polarity set to both rising and falling edges */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_INJ_TRIG_AUTO  ADC group injected - Automatic trigger mode

+  * @{

+  */

+#define LL_ADC_INJ_TRIG_INDEPENDENT        (0x00000000UL)         /*!< ADC group injected conversion trigger independent. Setting mandatory if ADC group injected injected trigger source is set to an external trigger. */

+#define LL_ADC_INJ_TRIG_FROM_GRP_REGULAR   (ADC_CFGR_JAUTO)       /*!< ADC group injected conversion trigger from ADC group regular. Setting compliant only with group injected trigger source set to SW start, without any further action on  ADC group injected conversion start or stop: in this case, ADC group injected is controlled only from ADC group regular. */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_INJ_CONTEXT_QUEUE  ADC group injected - Context queue mode

+  * @{

+  */

+#define LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE (0x00000000UL)         /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue maintains the last context active perpetually. */

+#define LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY   (ADC_CFGR_JQM)         /* Group injected sequence context queue is enabled and can contain up to 2 contexts. When all contexts have been processed, the queue is empty and injected group triggers are disabled. */

+#define LL_ADC_INJ_QUEUE_DISABLE               (ADC_CFGR_JQDIS)       /* Group injected sequence context queue is disabled: only 1 sequence can be configured and is active perpetually. */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_INJ_SEQ_SCAN_LENGTH  ADC group injected - Sequencer scan length

+  * @{

+  */

+#define LL_ADC_INJ_SEQ_SCAN_DISABLE        (0x00000000UL)                  /*!< ADC group injected sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */

+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS  (                ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 2 ranks in the sequence */

+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS  (ADC_JSQR_JL_1                ) /*!< ADC group injected sequencer enable with 3 ranks in the sequence */

+#define LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS  (ADC_JSQR_JL_1 | ADC_JSQR_JL_0) /*!< ADC group injected sequencer enable with 4 ranks in the sequence */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_INJ_SEQ_DISCONT_MODE  ADC group injected - Sequencer discontinuous mode

+  * @{

+  */

+#define LL_ADC_INJ_SEQ_DISCONT_DISABLE     (0x00000000UL)         /*!< ADC group injected sequencer discontinuous mode disable */

+#define LL_ADC_INJ_SEQ_DISCONT_1RANK       (ADC_CFGR_JDISCEN)     /*!< ADC group injected sequencer discontinuous mode enable with sequence interruption every rank */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_INJ_SEQ_RANKS  ADC group injected - Sequencer ranks

+  * @{

+  */

+#define LL_ADC_INJ_RANK_1                  (ADC_JDR1_REGOFFSET | ADC_INJ_RANK_1_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 1 */

+#define LL_ADC_INJ_RANK_2                  (ADC_JDR2_REGOFFSET | ADC_INJ_RANK_2_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 2 */

+#define LL_ADC_INJ_RANK_3                  (ADC_JDR3_REGOFFSET | ADC_INJ_RANK_3_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 3 */

+#define LL_ADC_INJ_RANK_4                  (ADC_JDR4_REGOFFSET | ADC_INJ_RANK_4_JSQR_BITOFFSET_POS) /*!< ADC group injected sequencer rank 4 */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME  Channel - Sampling time

+  * @{

+  */

+#define LL_ADC_SAMPLINGTIME_1CYCLE_5       (0x00000000UL)                                              /*!< Sampling time 1.5 ADC clock cycles */

+#define LL_ADC_SAMPLINGTIME_2CYCLES_5      (                                        ADC_SMPR2_SMP10_0) /*!< Sampling time 2.5 ADC clock cycles */

+#define LL_ADC_SAMPLINGTIME_8CYCLES_5      (                    ADC_SMPR2_SMP10_1                    ) /*!< Sampling time 8.5 ADC clock cycles */

+#define LL_ADC_SAMPLINGTIME_16CYCLES_5     (                    ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 16.5 ADC clock cycles */

+#define LL_ADC_SAMPLINGTIME_32CYCLES_5     (ADC_SMPR2_SMP10_2                                        ) /*!< Sampling time 32.5 ADC clock cycles */

+#define LL_ADC_SAMPLINGTIME_64CYCLES_5     (ADC_SMPR2_SMP10_2                     | ADC_SMPR2_SMP10_0) /*!< Sampling time 64.5 ADC clock cycles */

+#define LL_ADC_SAMPLINGTIME_387CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1                    ) /*!< Sampling time 387.5 ADC clock cycles */

+#define LL_ADC_SAMPLINGTIME_810CYCLES_5    (ADC_SMPR2_SMP10_2 | ADC_SMPR2_SMP10_1 | ADC_SMPR2_SMP10_0) /*!< Sampling time 810.5 ADC clock cycles */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_CHANNEL_SINGLE_DIFF_ENDING  Channel - Single or differential ending

+  * @{

+  */

+#define LL_ADC_SINGLE_ENDED                (                  ADC_CALFACT_CALFACT_S)         /*!< ADC channel ending set to single ended (literal also used to set calibration mode) */

+#define LL_ADC_DIFFERENTIAL_ENDED          (ADC_CR_ADCALDIF | ADC_CALFACT_CALFACT_D)         /*!< ADC channel ending set to differential (literal also used to set calibration mode) */

+#define LL_ADC_BOTH_SINGLE_DIFF_ENDED      (LL_ADC_SINGLE_ENDED | LL_ADC_DIFFERENTIAL_ENDED) /*!< ADC channel ending set to both single ended and differential (literal used only to set calibration factors) */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number

+  * @{

+  */

+#define LL_ADC_AWD1                        (ADC_AWD_CR1_CHANNEL_MASK  | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */

+#define LL_ADC_AWD2                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */

+#define LL_ADC_AWD3                        (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_AWD_CHANNELS  Analog watchdog - Monitored channels

+  * @{

+  */

+#define LL_ADC_AWD_DISABLE                 (0x00000000UL)                                                                                      /*!< ADC analog watchdog monitoring disabled */

+#define LL_ADC_AWD_ALL_CHANNELS_REG        (ADC_AWD_CR23_CHANNEL_MASK                                    | ADC_CFGR_AWD1EN                   ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */

+#define LL_ADC_AWD_ALL_CHANNELS_INJ        (ADC_AWD_CR23_CHANNEL_MASK                 | ADC_CFGR_JAWD1EN                                     ) /*!< ADC analog watchdog monitoring of all channels, converted by group injected only */

+#define LL_ADC_AWD_ALL_CHANNELS_REG_INJ    (ADC_AWD_CR23_CHANNEL_MASK                 | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN                   ) /*!< ADC analog watchdog monitoring of all channels, converted by either group regular or injected */

+#define LL_ADC_AWD_CHANNEL_0_REG           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */

+#define LL_ADC_AWD_CHANNEL_0_INJ           ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group injected only */

+#define LL_ADC_AWD_CHANNEL_0_REG_INJ       ((LL_ADC_CHANNEL_0  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by either group regular or injected */

+#define LL_ADC_AWD_CHANNEL_1_REG           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */

+#define LL_ADC_AWD_CHANNEL_1_INJ           ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group injected only */

+#define LL_ADC_AWD_CHANNEL_1_REG_INJ       ((LL_ADC_CHANNEL_1  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by either group regular or injected */

+#define LL_ADC_AWD_CHANNEL_2_REG           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */

+#define LL_ADC_AWD_CHANNEL_2_INJ           ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group injected only */

+#define LL_ADC_AWD_CHANNEL_2_REG_INJ       ((LL_ADC_CHANNEL_2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by either group regular or injected */

+#define LL_ADC_AWD_CHANNEL_3_REG           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */

+#define LL_ADC_AWD_CHANNEL_3_INJ           ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group injected only */

+#define LL_ADC_AWD_CHANNEL_3_REG_INJ       ((LL_ADC_CHANNEL_3  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by either group regular or injected */

+#define LL_ADC_AWD_CHANNEL_4_REG           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */

+#define LL_ADC_AWD_CHANNEL_4_INJ           ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group injected only */

+#define LL_ADC_AWD_CHANNEL_4_REG_INJ       ((LL_ADC_CHANNEL_4  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by either group regular or injected */

+#define LL_ADC_AWD_CHANNEL_5_REG           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */

+#define LL_ADC_AWD_CHANNEL_5_INJ           ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group injected only */

+#define LL_ADC_AWD_CHANNEL_5_REG_INJ       ((LL_ADC_CHANNEL_5  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by either group regular or injected */

+#define LL_ADC_AWD_CHANNEL_6_REG           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */

+#define LL_ADC_AWD_CHANNEL_6_INJ           ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group injected only */

+#define LL_ADC_AWD_CHANNEL_6_REG_INJ       ((LL_ADC_CHANNEL_6  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by either group regular or injected */

+#define LL_ADC_AWD_CHANNEL_7_REG           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */

+#define LL_ADC_AWD_CHANNEL_7_INJ           ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group injected only */

+#define LL_ADC_AWD_CHANNEL_7_REG_INJ       ((LL_ADC_CHANNEL_7  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by either group regular or injected */

+#define LL_ADC_AWD_CHANNEL_8_REG           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */

+#define LL_ADC_AWD_CHANNEL_8_INJ           ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group injected only */

+#define LL_ADC_AWD_CHANNEL_8_REG_INJ       ((LL_ADC_CHANNEL_8  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by either group regular or injected */

+#define LL_ADC_AWD_CHANNEL_9_REG           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */

+#define LL_ADC_AWD_CHANNEL_9_INJ           ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group injected only */

+#define LL_ADC_AWD_CHANNEL_9_REG_INJ       ((LL_ADC_CHANNEL_9  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by either group regular or injected */

+#define LL_ADC_AWD_CHANNEL_10_REG          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */

+#define LL_ADC_AWD_CHANNEL_10_INJ          ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group injected only */

+#define LL_ADC_AWD_CHANNEL_10_REG_INJ      ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by either group regular or injected */

+#define LL_ADC_AWD_CHANNEL_11_REG          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */

+#define LL_ADC_AWD_CHANNEL_11_INJ          ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group injected only */

+#define LL_ADC_AWD_CHANNEL_11_REG_INJ      ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by either group regular or injected */

+#define LL_ADC_AWD_CHANNEL_12_REG          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */

+#define LL_ADC_AWD_CHANNEL_12_INJ          ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group injected only */

+#define LL_ADC_AWD_CHANNEL_12_REG_INJ      ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by either group regular or injected */

+#define LL_ADC_AWD_CHANNEL_13_REG          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */

+#define LL_ADC_AWD_CHANNEL_13_INJ          ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group injected only */

+#define LL_ADC_AWD_CHANNEL_13_REG_INJ      ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by either group regular or injected */

+#define LL_ADC_AWD_CHANNEL_14_REG          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */

+#define LL_ADC_AWD_CHANNEL_14_INJ          ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group injected only */

+#define LL_ADC_AWD_CHANNEL_14_REG_INJ      ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by either group regular or injected */

+#define LL_ADC_AWD_CHANNEL_15_REG          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */

+#define LL_ADC_AWD_CHANNEL_15_INJ          ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group injected only */

+#define LL_ADC_AWD_CHANNEL_15_REG_INJ      ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by either group regular or injected */

+#define LL_ADC_AWD_CHANNEL_16_REG          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */

+#define LL_ADC_AWD_CHANNEL_16_INJ          ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group injected only */

+#define LL_ADC_AWD_CHANNEL_16_REG_INJ      ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by either group regular or injected */

+#define LL_ADC_AWD_CHANNEL_17_REG          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */

+#define LL_ADC_AWD_CHANNEL_17_INJ          ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group injected only */

+#define LL_ADC_AWD_CHANNEL_17_REG_INJ      ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by either group regular or injected */

+#define LL_ADC_AWD_CHANNEL_18_REG          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group regular only */

+#define LL_ADC_AWD_CHANNEL_18_INJ          ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by group injected only */

+#define LL_ADC_AWD_CHANNEL_18_REG_INJ      ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN18, converted by either group regular or injected */

+#define LL_ADC_AWD_CHANNEL_19_REG          ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group regular only */

+#define LL_ADC_AWD_CHANNEL_19_INJ          ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by group injected only */

+#define LL_ADC_AWD_CHANNEL_19_REG_INJ      ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN19, converted by either group regular or injected */

+#define LL_ADC_AWD_CH_VREFINT_REG          ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */

+#define LL_ADC_AWD_CH_VREFINT_INJ          ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group injected only */

+#define LL_ADC_AWD_CH_VREFINT_REG_INJ      ((LL_ADC_CHANNEL_VREFINT       & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by either group regular or injected */

+#define LL_ADC_AWD_CH_TEMPSENSOR_REG       ((LL_ADC_CHANNEL_TEMPSENSOR    & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */

+#define LL_ADC_AWD_CH_TEMPSENSOR_INJ       ((LL_ADC_CHANNEL_TEMPSENSOR    & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */

+#define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ   ((LL_ADC_CHANNEL_TEMPSENSOR    & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */

+#define LL_ADC_AWD_CH_VBAT_REG             ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, converted by group regular only */

+#define LL_ADC_AWD_CH_VBAT_INJ             ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda, converted by group injected only */

+#define LL_ADC_AWD_CH_VBAT_REG_INJ         ((LL_ADC_CHANNEL_VBAT          & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/4: Vbat voltage through a divider ladder of factor 1/4 to have Vbat always below Vdda */

+#define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG     ((LL_ADC_CHANNEL_DAC1CH1_ADC2  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */

+#define LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ     ((LL_ADC_CHANNEL_DAC1CH1_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */

+#define LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH1_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */

+#define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG     ((LL_ADC_CHANNEL_DAC1CH2_ADC2  & ADC_CHANNEL_ID_MASK)                    | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group regular only */

+#define LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ     ((LL_ADC_CHANNEL_DAC1CH2_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN                   | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by group injected only */

+#define LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ ((LL_ADC_CHANNEL_DAC1CH2_ADC2  & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC1 channel 1, channel specific to ADC2, converted by either group regular or injected */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_AWD_THRESHOLDS  Analog watchdog - Thresholds

+  * @{

+  */

+#define LL_ADC_AWD_THRESHOLD_HIGH          (0x1UL)                     /*!< ADC analog watchdog threshold high */

+#define LL_ADC_AWD_THRESHOLD_LOW           (0x0UL)                     /*!< ADC analog watchdog threshold low */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_OVS_SCOPE  Oversampling - Oversampling scope

+  * @{

+  */

+#define LL_ADC_OVS_DISABLE                 (0x00000000UL)                                        /*!< ADC oversampling disabled. */

+#define LL_ADC_OVS_GRP_REGULAR_CONTINUED   (                                    ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is temporary stopped and continued afterwards. */

+#define LL_ADC_OVS_GRP_REGULAR_RESUMED     (ADC_CFGR2_ROVSM |                   ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of ADC group regular. If group injected interrupts group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */

+#define LL_ADC_OVS_GRP_INJECTED            (                  ADC_CFGR2_JOVSE                  ) /*!< ADC oversampling on conversions of ADC group injected. */

+#define LL_ADC_OVS_GRP_INJ_REG_RESUMED     (                  ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE) /*!< ADC oversampling on conversions of both ADC groups regular and injected. If group injected interrupting group regular: when ADC group injected is triggered, the oversampling on ADC group regular is resumed from start (oversampler buffer reset). */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_OVS_DISCONT_MODE  Oversampling - Discontinuous mode

+  * @{

+  */

+#define LL_ADC_OVS_REG_CONT                (0x00000000UL)         /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */

+#define LL_ADC_OVS_REG_DISCONT             (ADC_CFGR2_TROVS)      /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_OVS_SHIFT  Oversampling - Data shift

+  * @{

+  */

+#define LL_ADC_OVS_SHIFT_NONE              (0x00000000UL)                                                              /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */

+#define LL_ADC_OVS_SHIFT_RIGHT_1           (                                                         ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */

+#define LL_ADC_OVS_SHIFT_RIGHT_2           (                                      ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */

+#define LL_ADC_OVS_SHIFT_RIGHT_3           (                                      ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */

+#define LL_ADC_OVS_SHIFT_RIGHT_4           (                   ADC_CFGR2_OVSS_2                                      ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */

+#define LL_ADC_OVS_SHIFT_RIGHT_5           (                   ADC_CFGR2_OVSS_2                    | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */

+#define LL_ADC_OVS_SHIFT_RIGHT_6           (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */

+#define LL_ADC_OVS_SHIFT_RIGHT_7           (                   ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */

+#define LL_ADC_OVS_SHIFT_RIGHT_8           (ADC_CFGR2_OVSS_3                                                         ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */

+#define LL_ADC_OVS_SHIFT_RIGHT_9           (ADC_CFGR2_OVSS_3                                       | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 9 (sum of the ADC conversions data is divided by 512 to result as the ADC oversampling conversion data) */

+#define LL_ADC_OVS_SHIFT_RIGHT_10          (ADC_CFGR2_OVSS_3                    | ADC_CFGR2_OVSS_1                   ) /*!< ADC oversampling shift of 10 (sum of the ADC conversions data is divided by 1024 to result as the ADC oversampling conversion data) */

+#define LL_ADC_OVS_SHIFT_RIGHT_11          (ADC_CFGR2_OVSS_3                    | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 11 (sum of the ADC conversions data is divided by 2048 to result as the ADC oversampling conversion data) */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_MULTI_MODE  Multimode - Mode

+  * @{

+  */

+#define LL_ADC_MULTI_INDEPENDENT           (0x00000000UL)                                                      /*!< ADC dual mode disabled (ADC independent mode) */

+#define LL_ADC_MULTI_DUAL_REG_SIMULT       (                 ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1                 ) /*!< ADC dual mode enabled: group regular simultaneous */

+#define LL_ADC_MULTI_DUAL_REG_INTERL       (                 ADC_CCR_DUAL_2 | ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved */

+#define LL_ADC_MULTI_DUAL_INJ_SIMULT       (                 ADC_CCR_DUAL_2                  | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected simultaneous */

+#define LL_ADC_MULTI_DUAL_INJ_ALTERN       (ADC_CCR_DUAL_3                                   | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: group injected alternate trigger. Works only with external triggers (not internal SW start) */

+#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM  (                                                   ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected simultaneous */

+#define LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT  (                                  ADC_CCR_DUAL_1                 ) /*!< ADC dual mode enabled: Combined group regular simultaneous + group injected alternate trigger */

+#define LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM  (                                  ADC_CCR_DUAL_1 | ADC_CCR_DUAL_0) /*!< ADC dual mode enabled: Combined group regular interleaved + group injected simultaneous */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_MULTI_DMA_TRANSFER  Multimode - DMA transfer

+  * @{

+  */

+#define LL_ADC_MULTI_REG_DMA_EACH_ADC        (0x00000000UL)                      /*!< ADC multimode group regular conversions are transferred by DMA: each ADC uses its own DMA channel, with its individual DMA transfer settings */

+#define LL_ADC_MULTI_REG_DMA_RES_32_10B      (ADC_CCR_DAMDF_1                  ) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master). Setting for ADC resolution of 32 (16x2) down to 10 bits */

+#define LL_ADC_MULTI_REG_DMA_RES_8B          (ADC_CCR_DAMDF_1 | ADC_CCR_DAMDF_0) /*!< ADC multimode group regular conversions are transferred by DMA, one DMA channel for both ADC (DMA of ADC master). Setting for ADC resolution of 8 bits */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_MULTI_TWOSMP_DELAY  Multimode - Delay between two sampling phases

+  * @{

+  */

+#define LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5           (0x00000000UL)                                                          /*!< ADC multimode delay between two sampling phases: 1.5 ADC clock cycle for all resolution                    */

+#define LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5          (                                                      ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 2.5 ADC clock cycles for all resolution                   */

+#define LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5          (                                    ADC_CCR_DELAY_1                  ) /*!< ADC multimode delay between two sampling phases: 3.5 ADC clock cycles for all resolution                   */

+#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5          (                                    ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4.5 ADC clock cycles for 16, 14, 12 or 10 bits resolution */

+#define LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS   (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 4.5 ADC clock cycles  for 8 bits resolution               */

+#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5          (                  ADC_CCR_DELAY_2                                    ) /*!< ADC multimode delay between two sampling phases: 5.5 ADC clock cycles for 16, 14, 12 bits resolution       */

+#define LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS  (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 5.5 ADC clock cycles for 10 bits resolution               */

+#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES            (ADC_CCR_DELAY_3                                                      ) /*!< ADC multimode delay between two sampling phases: 6 ADC clock cycles for 10 or 8 bits resolution            */

+#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5          (                  ADC_CCR_DELAY_2                   | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6.5 ADC clock cycles for 16 or 14 bits resolution         */

+#define LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS  (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 6.5 ADC clock cycles for 12 bits resolution               */

+#define LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5          (                  ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0) /*!< ADC multimode delay between two sampling phases: 7.5 ADC clock cycles for 16 bits resolution               */

+#define LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES            (ADC_CCR_DELAY_3                                                      ) /*!< ADC multimode delay between two sampling phases: 8 ADC clock cycles for 12 bits resolution                 */

+#define LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES            (ADC_CCR_DELAY_3                                                      ) /*!< ADC multimode delay between two sampling phases: 9 ADC clock cycles for 16 or 14 bits resolution           */

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EC_MULTI_MASTER_SLAVE  Multimode - ADC master or slave

+  * @{

+  */

+#define LL_ADC_MULTI_MASTER                (                    ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: ADC master */

+#define LL_ADC_MULTI_SLAVE                 (ADC_CDR_RDATA_SLV                    ) /*!< In multimode, selection among several ADC instances: ADC slave */

+#define LL_ADC_MULTI_MASTER_SLAVE          (ADC_CDR_RDATA_SLV | ADC_CDR_RDATA_MST) /*!< In multimode, selection among several ADC instances: both ADC master and ADC slave */

+/**

+  * @}

+  */

+

+

+

+/** @defgroup ADC_LL_EC_HW_DELAYS  Definitions of ADC hardware constraints delays

+  * @note   Only ADC peripheral HW delays are defined in ADC LL driver driver,

+  *         not timeout values.

+  *         For details on delays values, refer to descriptions in source code

+  *         above each literal definition.

+  * @{

+  */

+

+/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver,   */

+/*       not timeout values.                                                  */

+/*       Timeout values for ADC operations are dependent to device clock      */

+/*       configuration (system clock versus ADC clock),                       */

+/*       and therefore must be defined in user application.                   */

+/*       Indications for estimation of ADC timeout delays, for this           */

+/*       STM32 serie:                                                         */

+/*       - ADC calibration time: maximum delay is 16384/fADC.                   */

+/*         (refer to device datasheet, parameter "tCAL")                      */

+/*       - ADC enable time: maximum delay is 1 conversion cycle.              */

+/*         (refer to device datasheet, parameter "tSTAB")                     */

+/*       - ADC disable time: maximum delay should be a few ADC clock cycles   */

+/*       - ADC stop conversion time: maximum delay should be a few ADC clock  */

+/*         cycles                                                             */

+/*       - ADC conversion time: duration depending on ADC clock and ADC       */

+/*         configuration.                                                     */

+/*         (refer to device reference manual, section "Timing")               */

+

+/* Delay for ADC stabilization time (ADC voltage regulator start-up time)     */

+/* Delay set to maximum value (refer to device datasheet,                     */

+/* parameter "tADCVREG_STUP").                                                */

+/* Unit: us                                                                   */

+#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 10UL)  /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */

+

+/* Delay for internal voltage reference stabilization time.                   */

+/* Delay set to maximum value (refer to device datasheet,                     */

+/* parameter "ts_vrefint").                                                   */

+/* Unit: us                                                                   */

+#define LL_ADC_DELAY_VREFINT_STAB_US       (5UL)  /*!< Delay for internal voltage reference stabilization time */

+

+/* Delay for temperature sensor stabilization time.                           */

+/* Literal set to maximum value (refer to device datasheet,                   */

+/* parameter "tSTART_RUN").                                                   */

+/* Unit: us                                                                   */

+#define LL_ADC_DELAY_TEMPSENSOR_STAB_US    ( 26UL)  /*!< Delay for temperature sensor stabilization time */

+

+/* Delay required between ADC end of calibration and ADC enable.              */

+/* Note: On this STM32 serie, a minimum number of ADC clock cycles            */

+/*       are required between ADC end of calibration and ADC enable.          */

+/*       Wait time can be computed in user application by waiting for the     */

+/*       equivalent number of CPU cycles, by taking into account              */

+/*       ratio of CPU clock versus ADC clock prescalers.                      */

+/* Unit: ADC clock cycles.                                                    */

+#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES (  4UL)  /*!< Delay required between ADC end of calibration and ADC enable */

+

+/* Fixed timeout value for ADC linearity word bit set/clear delay.                         */

+/* Values defined to be higher than worst cases: low clock frequency,                      */

+/* maximum prescalers.                                                                     */

+/* Ex of profile low frequency : f_ADC at 4,577 Khz (minimum value                         */

+/* according to Data sheet), linearity set/clear bit delay MAX = 6 / f_ADC + 3 cycles AHB  */

+/*           6 / 4577 = 1,311ms                                                            */

+/* At maximum CPU speed (400 MHz), this means                                              */

+/*    3.58 * 400 MHz = 524400 CPU cycles                                                   */

+#define ADC_LINEARITY_BIT_TOGGLE_TIMEOUT         (524400UL)      /*!< ADC linearity set/clear bit delay */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros

+  * @{

+  */

+

+/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros

+  * @{

+  */

+

+/**

+  * @brief  Write a value in ADC register

+  * @param  __INSTANCE__ ADC Instance

+  * @param  __REG__ Register to be written

+  * @param  __VALUE__ Value to be written in the register

+  * @retval None

+  */

+#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

+

+/**

+  * @brief  Read a value in ADC register

+  * @param  __INSTANCE__ ADC Instance

+  * @param  __REG__ Register to be read

+  * @retval Register value

+  */

+#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro

+  * @{

+  */

+

+/**

+  * @brief  Helper macro to get ADC channel number in decimal format

+  *         from literals LL_ADC_CHANNEL_x.

+  * @note   Example:

+  *           __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4)

+  *           will return decimal number "4".

+  * @note   The input can be a value from functions where a channel

+  *         number is returned, either defined with number

+  *         or with bitfield (only one bit must be set).

+  * @param  __CHANNEL__ This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_CHANNEL_0           (3)

+  *         @arg @ref LL_ADC_CHANNEL_1           (3)

+  *         @arg @ref LL_ADC_CHANNEL_2           (3)

+  *         @arg @ref LL_ADC_CHANNEL_3           (3)

+  *         @arg @ref LL_ADC_CHANNEL_4           (3)

+  *         @arg @ref LL_ADC_CHANNEL_5           (3)

+  *         @arg @ref LL_ADC_CHANNEL_6

+  *         @arg @ref LL_ADC_CHANNEL_7

+  *         @arg @ref LL_ADC_CHANNEL_8

+  *         @arg @ref LL_ADC_CHANNEL_9

+  *         @arg @ref LL_ADC_CHANNEL_10

+  *         @arg @ref LL_ADC_CHANNEL_11

+  *         @arg @ref LL_ADC_CHANNEL_12

+  *         @arg @ref LL_ADC_CHANNEL_13

+  *         @arg @ref LL_ADC_CHANNEL_14

+  *         @arg @ref LL_ADC_CHANNEL_15

+  *         @arg @ref LL_ADC_CHANNEL_16

+  *         @arg @ref LL_ADC_CHANNEL_17

+  *         @arg @ref LL_ADC_CHANNEL_18

+  *         @arg @ref LL_ADC_CHANNEL_19

+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

+  *

+  *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

+  *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

+  *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

+  *             Other channels are slow channels (conversion rate: refer to reference manual).

+  * @retval Value between Min_Data=0 and Max_Data=18

+  */

+#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                                        \

+  ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL)                                 \

+   ? (                                                                                     \

+       ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \

+     )                                                                                     \

+   :                                                                                       \

+   (                                                                                       \

+       (uint32_t)POSITION_VAL((__CHANNEL__))                                               \

+   )                                                                                       \

+  )

+

+/**

+  * @brief  Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x

+  *         from number in decimal format.

+  * @note   Example:

+  *           __LL_ADC_DECIMAL_NB_TO_CHANNEL(4)

+  *           will return a data equivalent to "LL_ADC_CHANNEL_4".

+  * @param  __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_ADC_CHANNEL_0           (3)

+  *         @arg @ref LL_ADC_CHANNEL_1           (3)

+  *         @arg @ref LL_ADC_CHANNEL_2           (3)

+  *         @arg @ref LL_ADC_CHANNEL_3           (3)

+  *         @arg @ref LL_ADC_CHANNEL_4           (3)

+  *         @arg @ref LL_ADC_CHANNEL_5           (3)

+  *         @arg @ref LL_ADC_CHANNEL_6

+  *         @arg @ref LL_ADC_CHANNEL_7

+  *         @arg @ref LL_ADC_CHANNEL_8

+  *         @arg @ref LL_ADC_CHANNEL_9

+  *         @arg @ref LL_ADC_CHANNEL_10

+  *         @arg @ref LL_ADC_CHANNEL_11

+  *         @arg @ref LL_ADC_CHANNEL_12

+  *         @arg @ref LL_ADC_CHANNEL_13

+  *         @arg @ref LL_ADC_CHANNEL_14

+  *         @arg @ref LL_ADC_CHANNEL_15

+  *         @arg @ref LL_ADC_CHANNEL_16

+  *         @arg @ref LL_ADC_CHANNEL_17

+  *         @arg @ref LL_ADC_CHANNEL_18

+  *         @arg @ref LL_ADC_CHANNEL_19

+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

+  *

+  *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

+  *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

+  *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

+  *             Other channels are slow channels (conversion rate: refer to reference manual).\n

+  *         (1, 2) For ADC channel read back from ADC register,

+  *                comparison with internal channel parameter to be done

+  *                using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

+  */

+#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                                                  \

+  (((__DECIMAL_NB__) <= 9UL)                                                                            \

+   ? (                                                                                                  \

+       ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                             |          \

+       (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                             |          \

+       (ADC_SMPR1_REGOFFSET | (((3UL * (__DECIMAL_NB__))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))           \

+     )                                                                                                  \

+   :                                                                                                    \

+   (                                                                                                    \

+       ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)                                      | \

+       (ADC_AWD2CR_AWD2CH_0 << (__DECIMAL_NB__))                                                      | \

+       (ADC_SMPR2_REGOFFSET | (((3UL * ((__DECIMAL_NB__) - 10UL))) << ADC_CHANNEL_SMPx_BITOFFSET_POS))  \

+   )                                                                                                    \

+  )

+

+/**

+  * @brief  Helper macro to determine whether the selected channel

+  *         corresponds to literal definitions of driver.

+  * @note   The different literal definitions of ADC channels are:

+  *         - ADC internal channel:

+  *           LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...

+  *         - ADC external channel (channel connected to a GPIO pin):

+  *           LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...

+  * @note   The channel parameter must be a value defined from literal

+  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,

+  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),

+  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...),

+  *         must not be a value from functions where a channel number is

+  *         returned from ADC registers,

+  *         because internal and external channels share the same channel

+  *         number in ADC registers. The differentiation is made only with

+  *         parameters definitions of driver.

+  * @param  __CHANNEL__ This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_CHANNEL_0           (3)

+  *         @arg @ref LL_ADC_CHANNEL_1           (3)

+  *         @arg @ref LL_ADC_CHANNEL_2           (3)

+  *         @arg @ref LL_ADC_CHANNEL_3           (3)

+  *         @arg @ref LL_ADC_CHANNEL_4           (3)

+  *         @arg @ref LL_ADC_CHANNEL_5           (3)

+  *         @arg @ref LL_ADC_CHANNEL_6

+  *         @arg @ref LL_ADC_CHANNEL_7

+  *         @arg @ref LL_ADC_CHANNEL_8

+  *         @arg @ref LL_ADC_CHANNEL_9

+  *         @arg @ref LL_ADC_CHANNEL_10

+  *         @arg @ref LL_ADC_CHANNEL_11

+  *         @arg @ref LL_ADC_CHANNEL_12

+  *         @arg @ref LL_ADC_CHANNEL_13

+  *         @arg @ref LL_ADC_CHANNEL_14

+  *         @arg @ref LL_ADC_CHANNEL_15

+  *         @arg @ref LL_ADC_CHANNEL_16

+  *         @arg @ref LL_ADC_CHANNEL_17

+  *         @arg @ref LL_ADC_CHANNEL_18

+  *         @arg @ref LL_ADC_CHANNEL_19

+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

+  *

+  *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

+  *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

+  *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

+  *             Other channels are slow channels (conversion rate: refer to reference manual).

+  * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin).

+  *         Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.

+  */

+#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__)                              \

+  (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL)

+

+/**

+  * @brief  Helper macro to convert a channel defined from parameter

+  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,

+  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),

+  *         to its equivalent parameter definition of a ADC external channel

+  *         (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...).

+  * @note   The channel parameter can be, additionally to a value

+  *         defined from parameter definition of a ADC internal channel

+  *         (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...),

+  *         a value defined from parameter definition of

+  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)

+  *         or a value from functions where a channel number is returned

+  *         from ADC registers.

+  * @param  __CHANNEL__ This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_CHANNEL_0           (3)

+  *         @arg @ref LL_ADC_CHANNEL_1           (3)

+  *         @arg @ref LL_ADC_CHANNEL_2           (3)

+  *         @arg @ref LL_ADC_CHANNEL_3           (3)

+  *         @arg @ref LL_ADC_CHANNEL_4           (3)

+  *         @arg @ref LL_ADC_CHANNEL_5           (3)

+  *         @arg @ref LL_ADC_CHANNEL_6

+  *         @arg @ref LL_ADC_CHANNEL_7

+  *         @arg @ref LL_ADC_CHANNEL_8

+  *         @arg @ref LL_ADC_CHANNEL_9

+  *         @arg @ref LL_ADC_CHANNEL_10

+  *         @arg @ref LL_ADC_CHANNEL_11

+  *         @arg @ref LL_ADC_CHANNEL_12

+  *         @arg @ref LL_ADC_CHANNEL_13

+  *         @arg @ref LL_ADC_CHANNEL_14

+  *         @arg @ref LL_ADC_CHANNEL_15

+  *         @arg @ref LL_ADC_CHANNEL_16

+  *         @arg @ref LL_ADC_CHANNEL_17

+  *         @arg @ref LL_ADC_CHANNEL_18

+  *         @arg @ref LL_ADC_CHANNEL_19

+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

+  *

+  *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

+  *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

+  *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

+  *             Other channels are slow channels (conversion rate: refer to reference manual).

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_ADC_CHANNEL_0

+  *         @arg @ref LL_ADC_CHANNEL_1

+  *         @arg @ref LL_ADC_CHANNEL_2

+  *         @arg @ref LL_ADC_CHANNEL_3

+  *         @arg @ref LL_ADC_CHANNEL_4

+  *         @arg @ref LL_ADC_CHANNEL_5

+  *         @arg @ref LL_ADC_CHANNEL_6

+  *         @arg @ref LL_ADC_CHANNEL_7

+  *         @arg @ref LL_ADC_CHANNEL_8

+  *         @arg @ref LL_ADC_CHANNEL_9

+  *         @arg @ref LL_ADC_CHANNEL_10

+  *         @arg @ref LL_ADC_CHANNEL_11

+  *         @arg @ref LL_ADC_CHANNEL_12

+  *         @arg @ref LL_ADC_CHANNEL_13

+  *         @arg @ref LL_ADC_CHANNEL_14

+  *         @arg @ref LL_ADC_CHANNEL_15

+  *         @arg @ref LL_ADC_CHANNEL_16

+  *         @arg @ref LL_ADC_CHANNEL_17

+  *         @arg @ref LL_ADC_CHANNEL_18

+  *         @arg @ref LL_ADC_CHANNEL_19

+  */

+#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__)                     \

+  ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK)

+

+/**

+  * @brief  Helper macro to determine whether the internal channel

+  *         selected is available on the ADC instance selected.

+  * @note   The channel parameter must be a value defined from parameter

+  *         definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT,

+  *         LL_ADC_CHANNEL_TEMPSENSOR, ...),

+  *         must not be a value defined from parameter definition of

+  *         ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...)

+  *         or a value from functions where a channel number is

+  *         returned from ADC registers,

+  *         because internal and external channels share the same channel

+  *         number in ADC registers. The differentiation is made only with

+  *         parameters definitions of driver.

+  * @param  __ADC_INSTANCE__ ADC instance

+  * @param  __CHANNEL__ This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

+  *

+  *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

+  *         (2) On STM32H7, parameter available only on ADC instance: ADC2.

+  * @retval Value "0" if the internal channel selected is not available on the ADC instance selected.

+  *         Value "1" if the internal channel selected is available on the ADC instance selected.

+  */

+#if defined(ADC3)

+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \

+  ((((__ADC_INSTANCE__) == ADC2)                                               \

+    &&(                                                                        \

+       ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) ||                       \

+       ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2)                          \

+      )                                                                        \

+   )                                                                           \

+   ||                                                                          \

+   (((__ADC_INSTANCE__) == ADC3)                                               \

+    &&(                                                                        \

+       ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR)   ||                       \

+       ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)         ||                       \

+       ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \

+      )                                                                        \

+   )                                                                           \

+  )

+#else

+#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__)  \

+  ((((__ADC_INSTANCE__) == ADC2)                                               \

+    &&(                                                                        \

+       ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH1_ADC2) ||                       \

+       ((__CHANNEL__) == LL_ADC_CHANNEL_DAC1CH2_ADC2) ||                       \

+       ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR)   ||                       \

+       ((__CHANNEL__) == LL_ADC_CHANNEL_VBAT)         ||                       \

+       ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT)                               \

+      )                                                                        \

+   )                                                                           \

+  )

+#endif

+

+/**

+  * @brief  Helper macro to define ADC analog watchdog parameter:

+  *         define a single channel to monitor with analog watchdog

+  *         from sequencer channel and groups definition.

+  * @note   To be used with function @ref LL_ADC_SetAnalogWDMonitChannels().

+  *         Example:

+  *           LL_ADC_SetAnalogWDMonitChannels(

+  *             ADC1, LL_ADC_AWD1,

+  *             __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR))

+  * @param  __CHANNEL__ This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_CHANNEL_0           (3)

+  *         @arg @ref LL_ADC_CHANNEL_1           (3)

+  *         @arg @ref LL_ADC_CHANNEL_2           (3)

+  *         @arg @ref LL_ADC_CHANNEL_3           (3)

+  *         @arg @ref LL_ADC_CHANNEL_4           (3)

+  *         @arg @ref LL_ADC_CHANNEL_5           (3)

+  *         @arg @ref LL_ADC_CHANNEL_6

+  *         @arg @ref LL_ADC_CHANNEL_7

+  *         @arg @ref LL_ADC_CHANNEL_8

+  *         @arg @ref LL_ADC_CHANNEL_9

+  *         @arg @ref LL_ADC_CHANNEL_10

+  *         @arg @ref LL_ADC_CHANNEL_11

+  *         @arg @ref LL_ADC_CHANNEL_12

+  *         @arg @ref LL_ADC_CHANNEL_13

+  *         @arg @ref LL_ADC_CHANNEL_14

+  *         @arg @ref LL_ADC_CHANNEL_15

+  *         @arg @ref LL_ADC_CHANNEL_16

+  *         @arg @ref LL_ADC_CHANNEL_17

+  *         @arg @ref LL_ADC_CHANNEL_18

+  *         @arg @ref LL_ADC_CHANNEL_19

+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

+  *

+  *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

+  *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

+  *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

+  *             Other channels are slow channels (conversion rate: refer to reference manual).\n

+  *         (1, 2) For ADC channel read back from ADC register,

+  *                comparison with internal channel parameter to be done

+  *                using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

+  * @param  __GROUP__ This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_GROUP_REGULAR

+  *         @arg @ref LL_ADC_GROUP_INJECTED

+  *         @arg @ref LL_ADC_GROUP_REGULAR_INJECTED

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_ADC_AWD_DISABLE

+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)

+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)

+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_19_INJ          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)(1)

+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)(1)

+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ         (1)

+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (0)(1)

+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (0)(1)

+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ      (1)

+  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)(1)

+  *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(1)

+  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (1)

+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG     (0)(2)

+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ     (0)(2)

+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ    (2)

+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG     (0)(2)

+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ     (0)(2)

+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ    (2)

+  *

+  *         (0) On STM32H7, parameter available only on analog watchdog number: AWD1.\n

+  *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

+  *         (2) On STM32H7, parameter available only on ADC instance: ADC2.

+  */

+#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)                                           \

+  (((__GROUP__) == LL_ADC_GROUP_REGULAR)                                                                  \

+   ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)                         \

+   :                                                                                                      \

+   ((__GROUP__) == LL_ADC_GROUP_INJECTED)                                                                 \

+   ? (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1SGL)                        \

+   :                                                                                                      \

+   (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)        \

+  )

+

+/**

+  * @brief  Helper macro to set the value of ADC analog watchdog threshold high

+  *         or low in function of ADC resolution, when ADC resolution is

+  *         different of 16 bits.

+  * @note   To be used with function @ref LL_ADC_SetAnalogWDThresholds().

+  *         Example, with a ADC resolution of 8 bits, to set the value of

+  *         analog watchdog threshold high (on 18 bits):

+  *           LL_ADC_SetAnalogWDThresholds

+  *            (< ADCx param >,

+  *             __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, <threshold_value_18_bits>)

+  *            );

+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_RESOLUTION_16B

+  *         @arg @ref LL_ADC_RESOLUTION_14B

+  *         @arg @ref LL_ADC_RESOLUTION_12B

+  *         @arg @ref LL_ADC_RESOLUTION_10B

+  *         @arg @ref LL_ADC_RESOLUTION_8B

+  * @param  __AWD_THRESHOLD__ Value between Min_Data=0x000000 and Max_Data=0xFFFFFF

+  * @retval Value between Min_Data=0x000000 and Max_Data=0xFFFFFF

+  */

+#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \

+  ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))

+

+/**

+  * @brief  Helper macro to get the value of ADC analog watchdog threshold high

+  *         or low in function of ADC resolution, when ADC resolution is

+  *         different of 16 bits.

+  * @note   To be used with function @ref LL_ADC_GetAnalogWDThresholds().

+  *         Example, with a ADC resolution of 8 bits, to get the value of

+  *         analog watchdog threshold high (on 18 bits):

+  *           < threshold_value_18_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION

+  *            (LL_ADC_RESOLUTION_8B,

+  *             LL_ADC_GetAnalogWDThresholds(<ADCx param>, LL_ADC_AWD_THRESHOLD_HIGH)

+  *            );

+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_RESOLUTION_16B

+  *         @arg @ref LL_ADC_RESOLUTION_14B

+  *         @arg @ref LL_ADC_RESOLUTION_12B

+  *         @arg @ref LL_ADC_RESOLUTION_10B

+  *         @arg @ref LL_ADC_RESOLUTION_8B

+  * @param  __AWD_THRESHOLD_16_BITS__ Value between Min_Data=0x000000 and Max_Data=0xFFFFFF

+  * @retval Value between Min_Data=0x000000 and Max_Data=0xFFFFFF

+  */

+#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_16_BITS__) \

+  ((__AWD_THRESHOLD_16_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1U )))

+

+/**

+  * @brief  Helper macro to set the ADC calibration value with both single ended

+  *         and differential modes calibration factors concatenated.

+  * @note   To be used with function @ref LL_ADC_SetCalibrationOffsetFactor().

+  *         Example, to set calibration factors single ended to 0x55

+  *         and differential ended to 0x2A:

+  *           LL_ADC_SetCalibrationOffsetFactor(

+  *             ADC1,

+  *             __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(0x55, 0x2A))

+  * @param  __CALIB_FACTOR_SINGLE_ENDED__ Value between Min_Data=0x00 and Max_Data=0x7F

+  * @param  __CALIB_FACTOR_DIFFERENTIAL__ Value between Min_Data=0x00 and Max_Data=0x7F

+  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

+  */

+#define __LL_ADC_CALIB_FACTOR_SINGLE_DIFF(__CALIB_FACTOR_SINGLE_ENDED__, __CALIB_FACTOR_DIFFERENTIAL__)        \

+  (((__CALIB_FACTOR_DIFFERENTIAL__) << ADC_CALFACT_CALFACT_D_Pos) | (__CALIB_FACTOR_SINGLE_ENDED__))

+

+/**

+  * @brief  Helper macro to get the ADC multimode conversion data of ADC master

+  *         or ADC slave from raw value with both ADC conversion data concatenated.

+  * @note   This macro is intended to be used when multimode transfer by DMA

+  *         is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer().

+  *         In this case the transferred data need to processed with this macro

+  *         to separate the conversion data of ADC master and ADC slave.

+  * @param  __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_MULTI_MASTER

+  *         @arg @ref LL_ADC_MULTI_SLAVE

+  * @param  __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF

+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF

+  */

+#define __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \

+  (((__ADC_MULTI_CONV_DATA__) >> ((ADC_CDR_RDATA_SLV_Pos) & ~(__ADC_MULTI_MASTER_SLAVE__))) & ADC_CDR_RDATA_MST)

+

+/**

+  * @brief  Helper macro to select, from a ADC instance, to which ADC instance

+  *         it has a dependence in multimode (ADC master of the corresponding

+  *         ADC common instance).

+  * @note   In case of device with multimode available and a mix of

+  *         ADC instances compliant and not compliant with multimode feature,

+  *         ADC instances not compliant with multimode feature are

+  *         considered as master instances (do not depend to

+  *         any other ADC instance).

+  * @param  __ADCx__ ADC instance

+  * @retval __ADCx__ ADC instance master of the corresponding ADC common instance

+  */

+#define __LL_ADC_MULTI_INSTANCE_MASTER(__ADCx__) \

+  ( ( ((__ADCx__) == ADC2)                                                     \

+    )?                                                                         \

+     (ADC1)                                                                    \

+     :                                                                         \

+     (__ADCx__)                                                                \

+  )

+

+/**

+  * @brief  Helper macro to select the ADC common instance

+  *         to which is belonging the selected ADC instance.

+  * @note   ADC common register instance can be used for:

+  *         - Set parameters common to several ADC instances

+  *         - Multimode (for devices with several ADC instances)

+  *         Refer to functions having argument "ADCxy_COMMON" as parameter.

+  * @param  __ADCx__ ADC instance

+  * @retval ADC common register instance

+  */

+#if defined(ADC3_COMMON)

+#define __LL_ADC_COMMON_INSTANCE(__ADCx__)                                     \

+  ((((__ADCx__) == ADC1) || ((__ADCx__) == ADC2))                              \

+    ? (                                                                        \

+       (ADC12_COMMON)                                                          \

+      )                                                                        \

+      :                                                                        \

+      (                                                                        \

+       (ADC3_COMMON)                                                           \

+      )                                                                        \

+  )

+#else

+#define __LL_ADC_COMMON_INSTANCE(__ADCx__)   (ADC12_COMMON)

+#endif

+

+/**

+  * @brief  Helper macro to check if all ADC instances sharing the same

+  *         ADC common instance are disabled.

+  * @note   This check is required by functions with setting conditioned to

+  *         ADC state:

+  *         All ADC instances of the ADC common group must be disabled.

+  *         Refer to functions having argument "ADCxy_COMMON" as parameter.

+  * @note   On devices with only 1 ADC common instance, parameter of this macro

+  *         is useless and can be ignored (parameter kept for compatibility

+  *         with devices featuring several ADC common instances).

+  * @param  __ADCXY_COMMON__ ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @retval Value "0" if all ADC instances sharing the same ADC common instance

+  *         are disabled.

+  *         Value "1" if at least one ADC instance sharing the same ADC common instance

+  *         is enabled.

+  */

+#if defined(ADC3_COMMON)

+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \

+  (((__ADCXY_COMMON__) == ADC12_COMMON)                                        \

+    ? (                                                                        \

+       (LL_ADC_IsEnabled(ADC1) |                                               \

+        LL_ADC_IsEnabled(ADC2)  )                                              \

+      )                                                                        \

+      :                                                                        \

+      (                                                                        \

+       (LL_ADC_IsEnabled(ADC3))                                                \

+      )                                                                        \

+  )

+#else

+#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__)              \

+                        (LL_ADC_IsEnabled(ADC1) | LL_ADC_IsEnabled(ADC2))

+#endif

+

+/**

+  * @brief  Helper macro to define the ADC conversion data full-scale digital

+  *         value corresponding to the selected ADC resolution.

+  * @note   ADC conversion data full-scale corresponds to voltage range

+  *         determined by analog voltage references Vref+ and Vref-

+  *         (refer to reference manual).

+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_RESOLUTION_16B

+  *         @arg @ref LL_ADC_RESOLUTION_14B

+  *         @arg @ref LL_ADC_RESOLUTION_12B

+  *         @arg @ref LL_ADC_RESOLUTION_10B

+  *         @arg @ref LL_ADC_RESOLUTION_8B

+  * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data)

+  */

+#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                             \

+  (0xFFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))

+

+/**

+  * @brief  Helper macro to convert the ADC conversion data from

+  *         a resolution to another resolution.

+  * @param  __DATA__ ADC conversion data to be converted

+  * @param  __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted

+  *         This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_RESOLUTION_16B

+  *         @arg @ref LL_ADC_RESOLUTION_14B

+  *         @arg @ref LL_ADC_RESOLUTION_12B

+  *         @arg @ref LL_ADC_RESOLUTION_10B

+  *         @arg @ref LL_ADC_RESOLUTION_8B

+  * @param  __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion

+  *         This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_RESOLUTION_16B

+  *         @arg @ref LL_ADC_RESOLUTION_14B

+  *         @arg @ref LL_ADC_RESOLUTION_12B

+  *         @arg @ref LL_ADC_RESOLUTION_10B

+  *         @arg @ref LL_ADC_RESOLUTION_8B

+  * @retval ADC conversion data to the requested resolution

+  */

+#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\

+                                         __ADC_RESOLUTION_CURRENT__,\

+                                         __ADC_RESOLUTION_TARGET__)            \

+  (((__DATA__)                                                                 \

+    << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL)))   \

+   >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR_RES_BITOFFSET_POS - 1UL))      \

+  )

+

+/**

+  * @brief  Helper macro to calculate the voltage (unit: mVolt)

+  *         corresponding to a ADC conversion data (unit: digital value).

+  * @note   Analog reference voltage (Vref+) must be either known from

+  *         user board environment or can be calculated using ADC measurement

+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().

+  * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)

+  * @param  __ADC_DATA__ ADC conversion data (resolution 16 bits)

+  *                       (unit: digital value).

+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_RESOLUTION_16B

+  *         @arg @ref LL_ADC_RESOLUTION_14B

+  *         @arg @ref LL_ADC_RESOLUTION_12B

+  *         @arg @ref LL_ADC_RESOLUTION_10B

+  *         @arg @ref LL_ADC_RESOLUTION_8B

+  * @retval ADC conversion data equivalent voltage value (unit: mVolt)

+  */

+#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\

+                                      __ADC_DATA__,\

+                                      __ADC_RESOLUTION__)                      \

+  ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)                                   \

+   / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)                                \

+  )

+

+/**

+  * @brief  Helper macro to calculate analog reference voltage (Vref+)

+  *         (unit: mVolt) from ADC conversion data of internal voltage

+  *         reference VrefInt.

+  * @note   Computation is using VrefInt calibration value

+  *         stored in system memory for each device during production.

+  * @note   This voltage depends on user board environment: voltage level

+  *         connected to pin Vref+.

+  *         On devices with small package, the pin Vref+ is not present

+  *         and internally bonded to pin Vdda.

+  * @note   On this STM32 serie, calibration data of internal voltage reference

+  *         VrefInt corresponds to a resolution of 16 bits,

+  *         this is the recommended ADC resolution to convert voltage of

+  *         internal voltage reference VrefInt.

+  *         Otherwise, this macro performs the processing to scale

+  *         ADC conversion data to 16 bits.

+  * @param  __VREFINT_ADC_DATA__ ADC conversion data (resolution 16 bits)

+  *         of internal voltage reference VrefInt (unit: digital value).

+  * @param  __ADC_RESOLUTION__ This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_RESOLUTION_16B

+  *         @arg @ref LL_ADC_RESOLUTION_14B

+  *         @arg @ref LL_ADC_RESOLUTION_12B

+  *         @arg @ref LL_ADC_RESOLUTION_10B

+  *         @arg @ref LL_ADC_RESOLUTION_8B

+  * @retval Analog reference voltage (unit: mV)

+  */

+#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\

+                                         __ADC_RESOLUTION__)                   \

+  (((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF)                          \

+   / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),                  \

+                                      (__ADC_RESOLUTION__),                    \

+                                      LL_ADC_RESOLUTION_16B))

+

+/**

+  * @brief  Helper macro to calculate the temperature (unit: degree Celsius)

+  *         from ADC conversion data of internal temperature sensor.

+  * @note   Computation is using temperature sensor calibration values

+  *         stored in system memory for each device during production.

+  * @note   Calculation formula:

+  *           Temperature = ((TS_ADC_DATA - TS_CAL1)

+  *                           * (TS_CAL2_TEMP - TS_CAL1_TEMP))

+  *                         / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP

+  *           with TS_ADC_DATA = temperature sensor raw data measured by ADC

+  *                Avg_Slope = (TS_CAL2 - TS_CAL1)

+  *                            / (TS_CAL2_TEMP - TS_CAL1_TEMP)

+  *                TS_CAL1   = equivalent TS_ADC_DATA at temperature

+  *                            TEMP_DEGC_CAL1 (calibrated in factory)

+  *                TS_CAL2   = equivalent TS_ADC_DATA at temperature

+  *                            TEMP_DEGC_CAL2 (calibrated in factory)

+  *         Caution: Calculation relevancy under reserve that calibration

+  *                  parameters are correct (address and data).

+  *                  To calculate temperature using temperature sensor

+  *                  datasheet typical values (generic values less, therefore

+  *                  less accurate than calibrated values),

+  *                  use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS().

+  * @note   As calculation input, the analog reference voltage (Vref+) must be

+  *         defined as it impacts the ADC LSB equivalent voltage.

+  * @note   Analog reference voltage (Vref+) must be either known from

+  *         user board environment or can be calculated using ADC measurement

+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().

+  * @note   On this STM32 serie, calibration data of temperature sensor

+  *         corresponds to a resolution of 16 bits,

+  *         this is the recommended ADC resolution to convert voltage of

+  *         temperature sensor.

+  *         Otherwise, this macro performs the processing to scale

+  *         ADC conversion data to 16 bits.

+  * @param  __VREFANALOG_VOLTAGE__  Analog reference voltage (unit: mV)

+  * @param  __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal

+  *                                 temperature sensor (unit: digital value).

+  * @param  __ADC_RESOLUTION__      ADC resolution at which internal temperature

+  *                                 sensor voltage has been measured.

+  *         This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_RESOLUTION_16B

+  *         @arg @ref LL_ADC_RESOLUTION_14B

+  *         @arg @ref LL_ADC_RESOLUTION_12B

+  *         @arg @ref LL_ADC_RESOLUTION_10B

+  *         @arg @ref LL_ADC_RESOLUTION_8B

+  * @retval Temperature (unit: degree Celsius)

+  */

+#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\

+                                  __TEMPSENSOR_ADC_DATA__,\

+                                  __ADC_RESOLUTION__)                              \

+  (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__),     \

+                                                    (__ADC_RESOLUTION__),          \

+                                                    LL_ADC_RESOLUTION_16B)         \

+                   * (__VREFANALOG_VOLTAGE__))                                     \

+                  / TEMPSENSOR_CAL_VREFANALOG)                                     \

+        - (int32_t) *TEMPSENSOR_CAL1_ADDR)                                         \

+     ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP)                    \

+    ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \

+   ) + TEMPSENSOR_CAL1_TEMP                                                        \

+  )

+

+/**

+  * @brief  Helper macro to calculate the temperature (unit: degree Celsius)

+  *         from ADC conversion data of internal temperature sensor.

+  * @note   Computation is using temperature sensor typical values

+  *         (refer to device datasheet).

+  * @note   Calculation formula:

+  *           Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV)

+  *                         / Avg_Slope + CALx_TEMP

+  *           with TS_ADC_DATA      = temperature sensor raw data measured by ADC

+  *                                   (unit: digital value)

+  *                Avg_Slope        = temperature sensor slope

+  *                                   (unit: uV/Degree Celsius)

+  *                TS_TYP_CALx_VOLT = temperature sensor digital value at

+  *                                   temperature CALx_TEMP (unit: mV)

+  *         Caution: Calculation relevancy under reserve the temperature sensor

+  *                  of the current device has characteristics in line with

+  *                  datasheet typical values.

+  *                  If temperature sensor calibration values are available on

+  *                  on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()),

+  *                  temperature calculation will be more accurate using

+  *                  helper macro @ref __LL_ADC_CALC_TEMPERATURE().

+  * @note   As calculation input, the analog reference voltage (Vref+) must be

+  *         defined as it impacts the ADC LSB equivalent voltage.

+  * @note   Analog reference voltage (Vref+) must be either known from

+  *         user board environment or can be calculated using ADC measurement

+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().

+  * @note   ADC measurement data must correspond to a resolution of 16 bits

+  *         (full scale digital value 4095). If not the case, the data must be

+  *         preliminarily rescaled to an equivalent resolution of 16 bits.

+  * @param  __TEMPSENSOR_TYP_AVGSLOPE__   Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius).

+  *                                       On STM32H7, refer to device datasheet parameter "Avg_Slope".

+  * @param  __TEMPSENSOR_TYP_CALX_V__     Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV).

+  *                                       On STM32H7, refer to device datasheet parameter "V30" (corresponding to TS_CAL1).

+  * @param  __TEMPSENSOR_CALX_TEMP__      Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV)

+  * @param  __VREFANALOG_VOLTAGE__        Analog voltage reference (Vref+) voltage (unit: mV)

+  * @param  __TEMPSENSOR_ADC_DATA__       ADC conversion data of internal temperature sensor (unit: digital value).

+  * @param  __ADC_RESOLUTION__            ADC resolution at which internal temperature sensor voltage has been measured.

+  *         This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_RESOLUTION_16B

+  *         @arg @ref LL_ADC_RESOLUTION_14B

+  *         @arg @ref LL_ADC_RESOLUTION_12B

+  *         @arg @ref LL_ADC_RESOLUTION_10B

+  *         @arg @ref LL_ADC_RESOLUTION_8B

+  * @retval Temperature (unit: degree Celsius)

+  */

+#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\

+                                             __TEMPSENSOR_TYP_CALX_V__,\

+                                             __TEMPSENSOR_CALX_TEMP__,\

+                                             __VREFANALOG_VOLTAGE__,\

+                                             __TEMPSENSOR_ADC_DATA__,\

+                                             __ADC_RESOLUTION__)               \

+  ((( (                                                                        \

+       (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__))       \

+                  / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__))                \

+                 * 1000UL)                                                     \

+       -                                                                       \

+       (int32_t)(((__TEMPSENSOR_TYP_CALX_V__))                                 \

+                 * 1000UL)                                                     \

+      )                                                                        \

+    ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__)                                 \

+   ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__)                                     \

+  )

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions

+  * @{

+  */

+

+/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management

+  * @{

+  */

+

+/**

+  * @brief  Function to help to configure DMA transfer from ADC: retrieve the

+  *         ADC register address from ADC instance and a list of ADC registers

+  *         intended to be used (most commonly) with DMA transfer.

+  * @note   These ADC registers are data registers:

+  *         when ADC conversion data is available in ADC data registers,

+  *         ADC generates a DMA transfer request.

+  * @note   This macro is intended to be used with LL DMA driver, refer to

+  *         function "LL_DMA_ConfigAddresses()".

+  *         Example:

+  *           LL_DMA_ConfigAddresses(DMA1,

+  *                                  LL_DMA_CHANNEL_1,

+  *                                  LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA),

+  *                                  (uint32_t)&< array or variable >,

+  *                                  LL_DMA_DIRECTION_PERIPH_TO_MEMORY);

+  * @note   For devices with several ADC: in multimode, some devices

+  *         use a different data register outside of ADC instance scope

+  *         (common data register). This macro manages this register difference,

+  *         only ADC instance has to be set as parameter.

+  * @rmtoll DR       RDATA          LL_ADC_DMA_GetRegAddr\n

+  *         CDR      RDATA_MST      LL_ADC_DMA_GetRegAddr\n

+  *         CDR      RDATA_SLV      LL_ADC_DMA_GetRegAddr

+  * @param  ADCx ADC instance

+  * @param  Register This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA

+  *         @arg @ref LL_ADC_DMA_REG_REGULAR_DATA_MULTI (1)

+  *

+  *         (1) Available on devices with several ADC instances.

+  * @retval ADC register address

+  */

+__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register)

+{

+  register uint32_t data_reg_addr;

+

+  if (Register == LL_ADC_DMA_REG_REGULAR_DATA)

+  {

+    /* Retrieve address of register DR */

+    data_reg_addr = (uint32_t) &(ADCx->DR);

+  }

+  else /* (Register == LL_ADC_DMA_REG_REGULAR_DATA_MULTI) */

+  {

+    /* Retrieve address of register CDR */

+    data_reg_addr = (uint32_t) &((__LL_ADC_COMMON_INSTANCE(ADCx))->CDR);

+  }

+

+  return data_reg_addr;

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances

+  * @{

+  */

+

+/**

+  * @brief  Set parameter common to several ADC: Clock source and prescaler.

+  * @note   On this STM32 serie, if ADC group injected is used, some

+  *         clock ratio constraints between ADC clock and AHB clock

+  *         must be respected.

+  *         Refer to reference manual.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         All ADC instances of the ADC common group must be disabled.

+  *         This check can be done with function @ref LL_ADC_IsEnabled() for each

+  *         ADC instance or by using helper macro helper macro

+  *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().

+  * @rmtoll CCR      CKMODE         LL_ADC_SetCommonClock\n

+  *         CCR      PRESC          LL_ADC_SetCommonClock

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @param  CommonClock This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1

+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2

+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4

+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1

+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2

+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4

+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6

+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8

+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10

+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12

+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16

+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32

+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64

+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128

+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock)

+{

+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC, CommonClock);

+}

+

+/**

+  * @brief  Get parameter common to several ADC: Clock source and prescaler.

+  * @rmtoll CCR      CKMODE         LL_ADC_GetCommonClock\n

+  *         CCR      PRESC          LL_ADC_GetCommonClock

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1

+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2

+  *         @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4

+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV1

+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV2

+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV4

+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV6

+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV8

+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV10

+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV12

+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV16

+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV32

+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV64

+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV128

+  *         @arg @ref LL_ADC_CLOCK_ASYNC_DIV256

+  */

+__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON)

+{

+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_CKMODE | ADC_CCR_PRESC));

+}

+

+/**

+  * @brief  Set parameter common to several ADC: measurement path to internal

+  *         channels (VrefInt, temperature sensor, ...).

+  * @note   One or several values can be selected.

+  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |

+  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)

+  * @note   Stabilization time of measurement path to internal channel:

+  *         After enabling internal paths, before starting ADC conversion,

+  *         a delay is required for internal voltage reference and

+  *         temperature sensor stabilization time.

+  *         Refer to device datasheet.

+  *         Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US.

+  *         Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US.

+  * @note   ADC internal channel sampling time constraint:

+  *         For ADC conversion of internal channels,

+  *         a sampling time minimum value is required.

+  *         Refer to device datasheet.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         All ADC instances of the ADC common group must be disabled.

+  *         This check can be done with function @ref LL_ADC_IsEnabled() for each

+  *         ADC instance or by using helper macro helper macro

+  *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().

+  * @rmtoll CCR      VREFEN         LL_ADC_SetCommonPathInternalCh\n

+  *         CCR      TSEN           LL_ADC_SetCommonPathInternalCh\n

+  *         CCR      VBATEN         LL_ADC_SetCommonPathInternalCh

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @param  PathInternal This parameter can be a combination of the following values:

+  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE

+  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT

+  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR

+  *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal)

+{

+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN, PathInternal);

+}

+

+/**

+  * @brief  Get parameter common to several ADC: measurement path to internal

+  *         channels (VrefInt, temperature sensor, ...).

+  * @note   One or several values can be selected.

+  *         Example: (LL_ADC_PATH_INTERNAL_VREFINT |

+  *                   LL_ADC_PATH_INTERNAL_TEMPSENSOR)

+  * @rmtoll CCR      VREFEN         LL_ADC_GetCommonPathInternalCh\n

+  *         CCR      TSEN           LL_ADC_GetCommonPathInternalCh\n

+  *         CCR      VBATEN         LL_ADC_GetCommonPathInternalCh

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @retval Returned value can be a combination of the following values:

+  *         @arg @ref LL_ADC_PATH_INTERNAL_NONE

+  *         @arg @ref LL_ADC_PATH_INTERNAL_VREFINT

+  *         @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR

+  *         @arg @ref LL_ADC_PATH_INTERNAL_VBAT

+  */

+__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON)

+{

+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance

+  * @{

+  */

+

+/**

+  * @brief  Set ADC calibration factor in the mode single-ended

+  *         or differential (for devices with differential mode available).

+  * @note   This function is intended to set calibration parameters

+  *         without having to perform a new calibration using

+  *         @ref LL_ADC_StartCalibration().

+  * @note   For devices with differential mode available:

+  *         Calibration of offset is specific to each of

+  *         single-ended and differential modes

+  *         (calibration factor must be specified for each of these

+  *         differential modes, if used afterwards and if the application

+  *         requires their calibration).

+  *         Calibration of linearity is common to both

+  *         single-ended and differential modes

+  *         (calibration factor can be specified only once).

+  * @note   In case of setting calibration factors of both modes single ended

+  *         and differential (parameter LL_ADC_BOTH_SINGLE_DIFF_ENDED):

+  *         both calibration factors must be concatenated.

+  *         To perform this processing, use helper macro

+  *         @ref __LL_ADC_CALIB_FACTOR_SINGLE_DIFF().

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be enabled, without calibration on going, without conversion

+  *         on going on group regular.

+  * @rmtoll CALFACT  CALFACT_S      LL_ADC_SetCalibrationOffsetFactor\n

+  *         CALFACT  CALFACT_D      LL_ADC_SetCalibrationOffsetFactor

+  * @param  ADCx ADC instance

+  * @param  SingleDiff This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_SINGLE_ENDED

+  *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED

+  *         @arg @ref LL_ADC_BOTH_SINGLE_DIFF_ENDED

+  * @param  CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_SetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff, uint32_t CalibrationFactor)

+{

+  MODIFY_REG(ADCx->CALFACT,

+             SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK,

+             CalibrationFactor << (((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4) & ~(SingleDiff & ADC_CALFACT_CALFACT_S)));

+}

+

+/**

+  * @brief  Get ADC calibration factor in the mode single-ended

+  *         or differential (for devices with differential mode available).

+  * @note   Calibration factors are set by hardware after performing

+  *         a calibration run using function @ref LL_ADC_StartCalibration().

+  * @note   For devices with differential mode available:

+  *         Calibration of offset is specific to each of

+  *         single-ended and differential modes

+  *         Calibration of linearity is common to both

+  *         single-ended and differential modes

+  * @rmtoll CALFACT  CALFACT_S      LL_ADC_GetCalibrationOffsetFactor\n

+  *         CALFACT  CALFACT_D      LL_ADC_GetCalibrationOffsetFactor

+  * @param  ADCx ADC instance

+  * @param  SingleDiff This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_SINGLE_ENDED

+  *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED

+  * @retval Value between Min_Data=0x00 and Max_Data=0x7F

+  */

+__STATIC_INLINE uint32_t LL_ADC_GetCalibrationOffsetFactor(ADC_TypeDef *ADCx, uint32_t SingleDiff)

+{

+  /* Retrieve bits with position in register depending on parameter           */

+  /* "SingleDiff".                                                            */

+  /* Parameter used with mask "ADC_SINGLEDIFF_CALIB_FACTOR_MASK" because      */

+  /* containing other bits reserved for other purpose.                        */

+  return (uint32_t)(READ_BIT(ADCx->CALFACT, (SingleDiff & ADC_SINGLEDIFF_CALIB_FACTOR_MASK)) >> ((SingleDiff & ADC_SINGLEDIFF_CALIB_F_BIT_D_MASK) >> ADC_SINGLEDIFF_CALIB_F_BIT_D_SHIFT4));

+}

+

+/**

+  * @brief  Set ADC Linear calibration factor in the mode single-ended.

+  * @note   This function is intended to set linear calibration parameters

+  *         without having to perform a new calibration using

+  *         @ref LL_ADC_StartCalibration().

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be enabled, without calibration on going, without conversion

+  *         on going on group regular.

+  * @rmtoll CALFACT2  LINCALFACT      LL_ADC_SetCalibrationLinearFactor\n

+  *         CALFACT2  LINCALFACT      LL_ADC_SetCalibrationLinearFactor

+  * @param  ADCx ADC instance

+  * @param  LinearityWord This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD1

+  *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD2

+  *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD3

+  *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD4

+  *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD5

+  *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD6

+  * @param  CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x3FFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_SetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord, uint32_t CalibrationFactor)

+{

+  register uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;

+  MODIFY_REG(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT, CalibrationFactor);

+  MODIFY_REG(ADCx->CR, ADC_CR_ADCALLIN, LinearityWord);

+  while ((READ_BIT(ADCx->CR, LinearityWord)==0UL) && (timeout_cpu_cycles > 0UL))

+  {

+    timeout_cpu_cycles--;

+  }

+}

+

+/**

+  * @brief  Get ADC Linear calibration factor in the mode single-ended.

+  * @note   Calibration factors are set by hardware after performing

+  *         a calibration run using function @ref LL_ADC_StartCalibration().

+  * @rmtoll CALFACT2  LINCALFACT      LL_ADC_GetCalibrationLinearFactor\n

+  *         CALFACT2  LINCALFACT      LL_ADC_GetCalibrationLinearFactor

+  * @param  ADCx ADC instance

+  * @param  LinearityWord This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD1

+  *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD2

+  *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD3

+  *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD4

+  *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD5

+  *         @arg @ref LL_ADC_CALIB_LINEARITY_WORD6

+  * @retval Value between Min_Data=0x00 and Max_Data=0x3FFFFFFF

+  */

+__STATIC_INLINE uint32_t LL_ADC_GetCalibrationLinearFactor(ADC_TypeDef *ADCx, uint32_t LinearityWord)

+{

+  register uint32_t timeout_cpu_cycles = ADC_LINEARITY_BIT_TOGGLE_TIMEOUT;

+  CLEAR_BIT(ADCx->CR, LinearityWord);

+  while ((READ_BIT(ADCx->CR, LinearityWord)!=0UL) && (timeout_cpu_cycles > 0UL))

+  {

+    timeout_cpu_cycles--;

+  }

+  return (uint32_t)(READ_BIT(ADCx->CALFACT2, ADC_CALFACT2_LINCALFACT));

+}

+/**

+  * @brief  Set ADC resolution.

+  *         Refer to reference manual for alignments formats

+  *         dependencies to ADC resolutions.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be disabled or enabled without conversion on going

+  *         on either groups regular or injected.

+  * @rmtoll CFGR     RES            LL_ADC_SetResolution

+  * @param  ADCx ADC instance

+  * @param  Resolution This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_RESOLUTION_16B

+  *         @arg @ref LL_ADC_RESOLUTION_14B

+  *         @arg @ref LL_ADC_RESOLUTION_12B

+  *         @arg @ref LL_ADC_RESOLUTION_10B

+  *         @arg @ref LL_ADC_RESOLUTION_8B

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution)

+{

+#if defined (ADC_VER_V5_3)

+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);

+#else

+  if((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Rev.Y */

+  {

+    MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);

+  }

+  else /* Rev.V */

+  {

+    if(LL_ADC_RESOLUTION_8B == Resolution)

+    {

+      MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution | 0x0000000CUL);

+    }

+    else

+    {

+      MODIFY_REG(ADCx->CFGR, ADC_CFGR_RES, Resolution);

+    }

+  }

+#endif /* ADC_VER_V5_3*/

+}

+

+/**

+  * @brief  Get ADC resolution.

+  *         Refer to reference manual for alignments formats

+  *         dependencies to ADC resolutions.

+  * @rmtoll CFGR     RES            LL_ADC_GetResolution

+  * @param  ADCx ADC instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_ADC_RESOLUTION_16B

+  *         @arg @ref LL_ADC_RESOLUTION_14B

+  *         @arg @ref LL_ADC_RESOLUTION_12B

+  *         @arg @ref LL_ADC_RESOLUTION_10B

+  *         @arg @ref LL_ADC_RESOLUTION_8B

+  */

+__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx)

+{

+#if defined (ADC_VER_V5_3)

+    return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));

+#else

+  if((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Rev.Y */

+  {

+    return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));

+  }

+  else /* Rev.V */

+  {

+    if ((uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES)) == 0x0000001CUL)

+    {

+      return (LL_ADC_RESOLUTION_8B);

+    }

+    else

+    {

+      return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_RES));

+    }

+  }

+#endif /* ADC_VER_V5_3 */

+}

+

+/**

+  * @brief  Set ADC low power mode.

+  * @note   Description of ADC low power modes:

+  *         - ADC low power mode "auto wait": Dynamic low power mode,

+  *           ADC conversions occurrences are limited to the minimum necessary

+  *           in order to reduce power consumption.

+  *           New ADC conversion starts only when the previous

+  *           unitary conversion data (for ADC group regular)

+  *           or previous sequence conversions data (for ADC group injected)

+  *           has been retrieved by user software.

+  *           In the meantime, ADC remains idle: does not performs any

+  *           other conversion.

+  *           This mode allows to automatically adapt the ADC conversions

+  *           triggers to the speed of the software that reads the data.

+  *           Moreover, this avoids risk of overrun for low frequency

+  *           applications.

+  *           How to use this low power mode:

+  *           - Do not use with interruption or DMA since these modes

+  *             have to clear immediately the EOC flag to free the

+  *             IRQ vector sequencer.

+  *           - Do use with polling: 1. Start conversion,

+  *             2. Later on, when conversion data is needed: poll for end of

+  *             conversion  to ensure that conversion is completed and

+  *             retrieve ADC conversion data. This will trig another

+  *             ADC conversion start.

+  *         - ADC low power mode "auto power-off" (feature available on

+  *           this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):

+  *           the ADC automatically powers-off after a conversion and

+  *           automatically wakes up when a new conversion is triggered

+  *           (with startup time between trigger and start of sampling).

+  *           This feature can be combined with low power mode "auto wait".

+  * @note   With ADC low power mode "auto wait", the ADC conversion data read

+  *         is corresponding to previous ADC conversion start, independently

+  *         of delay during which ADC was idle.

+  *         Therefore, the ADC conversion data may be outdated: does not

+  *         correspond to the current voltage level on the selected

+  *         ADC channel.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be disabled or enabled without conversion on going

+  *         on either groups regular or injected.

+  * @rmtoll CFGR     AUTDLY         LL_ADC_SetLowPowerMode

+  * @param  ADCx ADC instance

+  * @param  LowPowerMode This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_LP_MODE_NONE

+  *         @arg @ref LL_ADC_LP_AUTOWAIT

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode)

+{

+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_AUTDLY, LowPowerMode);

+}

+

+/**

+  * @brief  Get ADC low power mode:

+  * @note   Description of ADC low power modes:

+  *         - ADC low power mode "auto wait": Dynamic low power mode,

+  *           ADC conversions occurrences are limited to the minimum necessary

+  *           in order to reduce power consumption.

+  *           New ADC conversion starts only when the previous

+  *           unitary conversion data (for ADC group regular)

+  *           or previous sequence conversions data (for ADC group injected)

+  *           has been retrieved by user software.

+  *           In the meantime, ADC remains idle: does not performs any

+  *           other conversion.

+  *           This mode allows to automatically adapt the ADC conversions

+  *           triggers to the speed of the software that reads the data.

+  *           Moreover, this avoids risk of overrun for low frequency

+  *           applications.

+  *           How to use this low power mode:

+  *           - Do not use with interruption or DMA since these modes

+  *             have to clear immediately the EOC flag to free the

+  *             IRQ vector sequencer.

+  *           - Do use with polling: 1. Start conversion,

+  *             2. Later on, when conversion data is needed: poll for end of

+  *             conversion  to ensure that conversion is completed and

+  *             retrieve ADC conversion data. This will trig another

+  *             ADC conversion start.

+  *         - ADC low power mode "auto power-off" (feature available on

+  *           this device if parameter LL_ADC_LP_AUTOPOWEROFF is available):

+  *           the ADC automatically powers-off after a conversion and

+  *           automatically wakes up when a new conversion is triggered

+  *           (with startup time between trigger and start of sampling).

+  *           This feature can be combined with low power mode "auto wait".

+  * @note   With ADC low power mode "auto wait", the ADC conversion data read

+  *         is corresponding to previous ADC conversion start, independently

+  *         of delay during which ADC was idle.

+  *         Therefore, the ADC conversion data may be outdated: does not

+  *         correspond to the current voltage level on the selected

+  *         ADC channel.

+  * @rmtoll CFGR     AUTDLY         LL_ADC_GetLowPowerMode

+  * @param  ADCx ADC instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_ADC_LP_MODE_NONE

+  *         @arg @ref LL_ADC_LP_AUTOWAIT

+  */

+__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx)

+{

+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_AUTDLY));

+}

+

+/**

+  * @brief  Set ADC selected offset number 1, 2, 3 or 4.

+  * @note   This function set the 2 items of offset configuration:

+  *         - ADC channel to which the offset programmed will be applied

+  *           (independently of channel mapped on ADC group regular

+  *           or group injected)

+  *         - Offset level (offset to be subtracted from the raw

+  *           converted data).

+  * @note   Caution: Offset format is dependent to ADC resolution:

+  *         offset has to be left-aligned on bit 11, the LSB (right bits)

+  *         are set to 0.

+  * @note   This function enables the offset, by default. It can be forced

+  *         to disable state using function LL_ADC_SetOffsetState().

+  * @note   If a channel is mapped on several offsets numbers, only the offset

+  *         with the lowest value is considered for the subtraction.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be disabled or enabled without conversion on going

+  *         on either groups regular or injected.

+  * @note   On STM32H7, some fast channels are available: fast analog inputs

+  *         coming from GPIO pads (ADC_IN0..5).

+  * @rmtoll OFR1     OFFSET1_CH     LL_ADC_SetOffset\n

+  *         OFR1     OFFSET1        LL_ADC_SetOffset\n

+  *         OFR1     OFFSET1_EN     LL_ADC_SetOffset\n

+  *         OFR2     OFFSET2_CH     LL_ADC_SetOffset\n

+  *         OFR2     OFFSET2        LL_ADC_SetOffset\n

+  *         OFR2     OFFSET2_EN     LL_ADC_SetOffset\n

+  *         OFR3     OFFSET3_CH     LL_ADC_SetOffset\n

+  *         OFR3     OFFSET3        LL_ADC_SetOffset\n

+  *         OFR3     OFFSET3_EN     LL_ADC_SetOffset\n

+  *         OFR4     OFFSET4_CH     LL_ADC_SetOffset\n

+  *         OFR4     OFFSET4        LL_ADC_SetOffset\n

+  *         OFR4     OFFSET4_EN     LL_ADC_SetOffset

+  * @param  ADCx ADC instance

+  * @param  Offsety This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_OFFSET_1

+  *         @arg @ref LL_ADC_OFFSET_2

+  *         @arg @ref LL_ADC_OFFSET_3

+  *         @arg @ref LL_ADC_OFFSET_4

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_CHANNEL_0           (3)

+  *         @arg @ref LL_ADC_CHANNEL_1           (3)

+  *         @arg @ref LL_ADC_CHANNEL_2           (3)

+  *         @arg @ref LL_ADC_CHANNEL_3           (3)

+  *         @arg @ref LL_ADC_CHANNEL_4           (3)

+  *         @arg @ref LL_ADC_CHANNEL_5           (3)

+  *         @arg @ref LL_ADC_CHANNEL_6

+  *         @arg @ref LL_ADC_CHANNEL_7

+  *         @arg @ref LL_ADC_CHANNEL_8

+  *         @arg @ref LL_ADC_CHANNEL_9

+  *         @arg @ref LL_ADC_CHANNEL_10

+  *         @arg @ref LL_ADC_CHANNEL_11

+  *         @arg @ref LL_ADC_CHANNEL_12

+  *         @arg @ref LL_ADC_CHANNEL_13

+  *         @arg @ref LL_ADC_CHANNEL_14

+  *         @arg @ref LL_ADC_CHANNEL_15

+  *         @arg @ref LL_ADC_CHANNEL_16

+  *         @arg @ref LL_ADC_CHANNEL_17

+  *         @arg @ref LL_ADC_CHANNEL_18

+  *         @arg @ref LL_ADC_CHANNEL_19

+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

+  *

+  *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

+  *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

+  *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

+  *             Other channels are slow channels (conversion rate: refer to reference manual).

+  * @param  OffsetLevel Value between Min_Data=0x000 and Max_Data=0x1FFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_SetOffset(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t Channel, uint32_t OffsetLevel)

+{

+  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);

+

+  MODIFY_REG(*preg,

+             ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1,

+             (Channel & ADC_CHANNEL_ID_NUMBER_MASK) | OffsetLevel);

+}

+

+/**

+  * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:

+  *         Channel to which the offset programmed will be applied

+  *         (independently of channel mapped on ADC group regular

+  *         or group injected)

+  * @note   Usage of the returned channel number:

+  *         - To reinject this channel into another function LL_ADC_xxx:

+  *           the returned channel number is only partly formatted on definition

+  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared

+  *           with parts of literals LL_ADC_CHANNEL_x or using

+  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

+  *           Then the selected literal LL_ADC_CHANNEL_x can be used

+  *           as parameter for another function.

+  *         - To get the channel number in decimal format:

+  *           process the returned value with the helper macro

+  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

+  * @note   On STM32H7, some fast channels are available: fast analog inputs

+  *         coming from GPIO pads (ADC_IN0..5).

+  * @rmtoll OFR1     OFFSET1_CH     LL_ADC_GetOffsetChannel\n

+  *         OFR2     OFFSET2_CH     LL_ADC_GetOffsetChannel\n

+  *         OFR3     OFFSET3_CH     LL_ADC_GetOffsetChannel\n

+  *         OFR4     OFFSET4_CH     LL_ADC_GetOffsetChannel

+  * @param  ADCx ADC instance

+  * @param  Offsety This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_OFFSET_1

+  *         @arg @ref LL_ADC_OFFSET_2

+  *         @arg @ref LL_ADC_OFFSET_3

+  *         @arg @ref LL_ADC_OFFSET_4

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_ADC_CHANNEL_0           (3)

+  *         @arg @ref LL_ADC_CHANNEL_1           (3)

+  *         @arg @ref LL_ADC_CHANNEL_2           (3)

+  *         @arg @ref LL_ADC_CHANNEL_3           (3)

+  *         @arg @ref LL_ADC_CHANNEL_4           (3)

+  *         @arg @ref LL_ADC_CHANNEL_5           (3)

+  *         @arg @ref LL_ADC_CHANNEL_6

+  *         @arg @ref LL_ADC_CHANNEL_7

+  *         @arg @ref LL_ADC_CHANNEL_8

+  *         @arg @ref LL_ADC_CHANNEL_9

+  *         @arg @ref LL_ADC_CHANNEL_10

+  *         @arg @ref LL_ADC_CHANNEL_11

+  *         @arg @ref LL_ADC_CHANNEL_12

+  *         @arg @ref LL_ADC_CHANNEL_13

+  *         @arg @ref LL_ADC_CHANNEL_14

+  *         @arg @ref LL_ADC_CHANNEL_15

+  *         @arg @ref LL_ADC_CHANNEL_16

+  *         @arg @ref LL_ADC_CHANNEL_17

+  *         @arg @ref LL_ADC_CHANNEL_18

+  *         @arg @ref LL_ADC_CHANNEL_19

+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

+  *

+  *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

+  *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

+  *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

+  *             Other channels are slow channels (conversion rate: refer to reference manual).\n

+  *         (1, 2) For ADC channel read back from ADC register,

+  *                comparison with internal channel parameter to be done

+  *                using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

+  */

+__STATIC_INLINE uint32_t LL_ADC_GetOffsetChannel(ADC_TypeDef *ADCx, uint32_t Offsety)

+{

+  register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);

+

+  return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1_CH);

+}

+

+/**

+  * @brief  Get for the ADC selected offset number 1, 2, 3 or 4:

+  *         Offset level (offset to be subtracted from the raw

+  *         converted data).

+  * @note   Caution: Offset format is dependent to ADC resolution:

+  *         offset has to be left-aligned on bit 11, the LSB (right bits)

+  *         are set to 0.

+  * @rmtoll OFR1     OFFSET1        LL_ADC_GetOffsetLevel\n

+  *         OFR2     OFFSET2        LL_ADC_GetOffsetLevel\n

+  *         OFR3     OFFSET3        LL_ADC_GetOffsetLevel\n

+  *         OFR4     OFFSET4        LL_ADC_GetOffsetLevel

+  * @param  ADCx ADC instance

+  * @param  Offsety This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_OFFSET_1

+  *         @arg @ref LL_ADC_OFFSET_2

+  *         @arg @ref LL_ADC_OFFSET_3

+  *         @arg @ref LL_ADC_OFFSET_4

+  * @retval Value between Min_Data=0x000 and Max_Data=0x1FFFFFF

+  */

+__STATIC_INLINE uint32_t LL_ADC_GetOffsetLevel(ADC_TypeDef *ADCx, uint32_t Offsety)

+{

+  register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);

+

+  return (uint32_t) READ_BIT(*preg, ADC_OFR1_OFFSET1);

+}

+

+

+/**

+  * @brief  Set data right shift for the ADC selected offset number 1, 2, 3 or 4:

+  *         signed offset saturation if enabled or disabled.

+  * @rmtoll CFGR2    RSHIFT          LL_ADC_SetDataRightShift\n

+  * @param  ADCx ADC instance

+  * @param  Offsety This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_OFFSET_1

+  *         @arg @ref LL_ADC_OFFSET_2

+  *         @arg @ref LL_ADC_OFFSET_3

+  *         @arg @ref LL_ADC_OFFSET_4

+  * @param  RigthShift This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE

+  *         @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE

+  * @retval Returned None

+  */

+__STATIC_INLINE void LL_ADC_SetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t RigthShift)

+{

+  MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 | ADC_CFGR2_RSHIFT2 | ADC_CFGR2_RSHIFT3 | ADC_CFGR2_RSHIFT4), RigthShift << (Offsety & 0x1FUL));

+}

+

+/**

+  * @brief  Get data right shift for the ADC selected offset number 1, 2, 3 or 4:

+  *         signed offset saturation if enabled or disabled.

+  * @rmtoll CFGR2    RSHIFT          LL_ADC_GetDataRightShift\n

+  * @param  ADCx ADC instance

+  * @param  Offsety This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_OFFSET_1

+  *         @arg @ref LL_ADC_OFFSET_2

+  *         @arg @ref LL_ADC_OFFSET_3

+  *         @arg @ref LL_ADC_OFFSET_4

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_ADC_OFFSET_RSHIFT_ENABLE

+  *         @arg @ref LL_ADC_OFFSET_RSHIFT_DISABLE

+  */

+__STATIC_INLINE uint32_t LL_ADC_GetDataRightShift(ADC_TypeDef *ADCx, uint32_t Offsety)

+{

+  return (uint32_t) ((READ_BIT(ADCx->CFGR2, (ADC_CFGR2_RSHIFT1 << (Offsety & 0x1FUL)))) >> (Offsety & 0x1FUL));

+}

+

+/**

+  * @brief  Set signed saturation for the ADC selected offset number 1, 2, 3 or 4:

+  *         signed offset saturation if enabled or disabled.

+  * @rmtoll OFR1     SSATE          LL_ADC_SetOffsetSignedSaturation\n

+  *         OFR2     SSATE          LL_ADC_SetOffsetSignedSaturation\n

+  *         OFR3     SSATE          LL_ADC_SetOffsetSignedSaturation\n

+  *         OFR4     SSATE          LL_ADC_SetOffsetSignedSaturation

+  * @param  ADCx ADC instance

+  * @param  Offsety This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_OFFSET_1

+  *         @arg @ref LL_ADC_OFFSET_2

+  *         @arg @ref LL_ADC_OFFSET_3

+  *         @arg @ref LL_ADC_OFFSET_4

+  * @param  OffsetSignedSaturation This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE

+  *         @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE

+  * @retval Returned None

+  */

+__STATIC_INLINE void LL_ADC_SetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety, uint32_t OffsetSignedSaturation)

+{

+   register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);

+   MODIFY_REG(*preg, ADC_OFR1_SSATE, OffsetSignedSaturation);

+}

+

+/**

+  * @brief  Get signed saturation for the ADC selected offset number 1, 2, 3 or 4:

+  *         signed offset saturation if enabled or disabled.

+  * @rmtoll OFR1     SSATE          LL_ADC_GetOffsetSignedSaturation\n

+  *         OFR2     SSATE          LL_ADC_GetOffsetSignedSaturation\n

+  *         OFR3     SSATE          LL_ADC_GetOffsetSignedSaturation\n

+  *         OFR4     SSATE          LL_ADC_GetOffsetSignedSaturation

+  * @param  ADCx ADC instance

+  * @param  Offsety This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_OFFSET_1

+  *         @arg @ref LL_ADC_OFFSET_2

+  *         @arg @ref LL_ADC_OFFSET_3

+  *         @arg @ref LL_ADC_OFFSET_4

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE

+  *         @arg @ref LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE

+  */

+__STATIC_INLINE uint32_t LL_ADC_GetOffsetSignedSaturation(ADC_TypeDef *ADCx, uint32_t Offsety)

+{

+  register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->OFR1, Offsety);

+  return (uint32_t) READ_BIT(*preg, ADC_OFR1_SSATE);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular

+  * @{

+  */

+

+/**

+  * @brief  Set ADC group regular conversion trigger source:

+  *         internal (SW start) or from external peripheral (timer event,

+  *         external interrupt line).

+  * @note   On this STM32 serie, setting trigger source to external trigger

+  *         also set trigger polarity to rising edge

+  *         (default setting for compatibility with some ADC on other

+  *         STM32 families having this setting set by HW default value).

+  *         In case of need to modify trigger edge, use

+  *         function @ref LL_ADC_REG_SetTriggerEdge().

+  * @note   Availability of parameters of trigger sources from timer

+  *         depends on timers availability on the selected device.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be disabled or enabled without conversion on going

+  *         on group regular.

+  * @rmtoll CFGR     EXTSEL         LL_ADC_REG_SetTriggerSource\n

+  *         CFGR     EXTEN          LL_ADC_REG_SetTriggerSource

+  * @param  ADCx ADC instance

+  * @param  TriggerSource This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_OUT

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_OUT

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_OUT

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)

+{

+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL, TriggerSource);

+}

+

+/**

+  * @brief  Get ADC group regular conversion trigger source:

+  *         internal (SW start) or from external peripheral (timer event,

+  *         external interrupt line).

+  * @note   To determine whether group regular trigger source is

+  *         internal (SW start) or external, without detail

+  *         of which peripheral is selected as external trigger,

+  *         (equivalent to

+  *         "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)")

+  *         use function @ref LL_ADC_REG_IsTriggerSourceSWStart.

+  * @note   Availability of parameters of trigger sources from timer

+  *         depends on timers availability on the selected device.

+  * @rmtoll CFGR     EXTSEL         LL_ADC_REG_GetTriggerSource\n

+  *         CFGR     EXTEN          LL_ADC_REG_GetTriggerSource

+  * @param  ADCx ADC instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_ADC_REG_TRIG_SOFTWARE

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH1

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH2

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH3

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH2

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_CH4

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM8_TRGO2

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM4_TRGO

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM6_TRGO

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM15_TRGO

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_CH4

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG1

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_HRTIM_TRG3

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM1_OUT

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM2_OUT

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_LPTIM3_OUT

+  */

+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx)

+{

+  register __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR, ADC_CFGR_EXTSEL | ADC_CFGR_EXTEN);

+

+  /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */

+  /* corresponding to ADC_CFGR_EXTEN {0; 1; 2; 3}.                            */

+  register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL));

+

+  /* Set bitfield corresponding to ADC_CFGR_EXTEN and ADC_CFGR_EXTSEL         */

+  /* to match with triggers literals definition.                              */

+  return ((TriggerSource

+           & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR_EXTSEL)

+          | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR_EXTEN)

+         );

+}

+

+/**

+  * @brief  Get ADC group regular conversion trigger source internal (SW start)

+  *         or external.

+  * @note   In case of group regular trigger source set to external trigger,

+  *         to determine which peripheral is selected as external trigger,

+  *         use function @ref LL_ADC_REG_GetTriggerSource().

+  * @rmtoll CFGR     EXTEN          LL_ADC_REG_IsTriggerSourceSWStart

+  * @param  ADCx ADC instance

+  * @retval Value "0" if trigger source external trigger

+  *         Value "1" if trigger source SW start.

+  */

+__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR_EXTEN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set ADC group regular conversion trigger polarity.

+  * @note   Applicable only for trigger source set to external trigger.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be disabled or enabled without conversion on going

+  *         on group regular.

+  * @rmtoll CFGR     EXTEN          LL_ADC_REG_SetTriggerEdge

+  * @param  ADCx ADC instance

+  * @param  ExternalTriggerEdge This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)

+{

+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_EXTEN, ExternalTriggerEdge);

+}

+

+/**

+  * @brief  Get ADC group regular conversion trigger polarity.

+  * @note   Applicable only for trigger source set to external trigger.

+  * @rmtoll CFGR     EXTEN          LL_ADC_REG_GetTriggerEdge

+  * @param  ADCx ADC instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISING

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_FALLING

+  *         @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING

+  */

+__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx)

+{

+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_EXTEN));

+}

+

+/**

+  * @brief  Set ADC group regular sequencer length and scan direction.

+  * @note   Description of ADC group regular sequencer features:

+  *         - For devices with sequencer fully configurable

+  *           (function "LL_ADC_REG_SetSequencerRanks()" available):

+  *           sequencer length and each rank affectation to a channel

+  *           are configurable.

+  *           This function performs configuration of:

+  *           - Sequence length: Number of ranks in the scan sequence.

+  *           - Sequence direction: Unless specified in parameters, sequencer

+  *             scan direction is forward (from rank 1 to rank n).

+  *           Sequencer ranks are selected using

+  *           function "LL_ADC_REG_SetSequencerRanks()".

+  *         - For devices with sequencer not fully configurable

+  *           (function "LL_ADC_REG_SetSequencerChannels()" available):

+  *           sequencer length and each rank affectation to a channel

+  *           are defined by channel number.

+  *           This function performs configuration of:

+  *           - Sequence length: Number of ranks in the scan sequence is

+  *             defined by number of channels set in the sequence,

+  *             rank of each channel is fixed by channel HW number.

+  *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).

+  *           - Sequence direction: Unless specified in parameters, sequencer

+  *             scan direction is forward (from lowest channel number to

+  *             highest channel number).

+  *           Sequencer ranks are selected using

+  *           function "LL_ADC_REG_SetSequencerChannels()".

+  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:

+  *         ADC conversion on only 1 channel.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be disabled or enabled without conversion on going

+  *         on group regular.

+  * @rmtoll SQR1     L              LL_ADC_REG_SetSequencerLength

+  * @param  ADCx ADC instance

+  * @param  SequencerNbRanks This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)

+{

+  MODIFY_REG(ADCx->SQR1, ADC_SQR1_L, SequencerNbRanks);

+}

+

+/**

+  * @brief  Get ADC group regular sequencer length and scan direction.

+  * @note   Description of ADC group regular sequencer features:

+  *         - For devices with sequencer fully configurable

+  *           (function "LL_ADC_REG_SetSequencerRanks()" available):

+  *           sequencer length and each rank affectation to a channel

+  *           are configurable.

+  *           This function retrieves:

+  *           - Sequence length: Number of ranks in the scan sequence.

+  *           - Sequence direction: Unless specified in parameters, sequencer

+  *             scan direction is forward (from rank 1 to rank n).

+  *           Sequencer ranks are selected using

+  *           function "LL_ADC_REG_SetSequencerRanks()".

+  *         - For devices with sequencer not fully configurable

+  *           (function "LL_ADC_REG_SetSequencerChannels()" available):

+  *           sequencer length and each rank affectation to a channel

+  *           are defined by channel number.

+  *           This function retrieves:

+  *           - Sequence length: Number of ranks in the scan sequence is

+  *             defined by number of channels set in the sequence,

+  *             rank of each channel is fixed by channel HW number.

+  *             (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...).

+  *           - Sequence direction: Unless specified in parameters, sequencer

+  *             scan direction is forward (from lowest channel number to

+  *             highest channel number).

+  *           Sequencer ranks are selected using

+  *           function "LL_ADC_REG_SetSequencerChannels()".

+  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:

+  *         ADC conversion on only 1 channel.

+  * @rmtoll SQR1     L              LL_ADC_REG_GetSequencerLength

+  * @param  ADCx ADC instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS

+  */

+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx)

+{

+  return (uint32_t)(READ_BIT(ADCx->SQR1, ADC_SQR1_L));

+}

+

+/**

+  * @brief  Set ADC group regular sequencer discontinuous mode:

+  *         sequence subdivided and scan conversions interrupted every selected

+  *         number of ranks.

+  * @note   It is not possible to enable both ADC group regular

+  *         continuous mode and sequencer discontinuous mode.

+  * @note   It is not possible to enable both ADC auto-injected mode

+  *         and ADC group regular sequencer discontinuous mode.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be disabled or enabled without conversion on going

+  *         on group regular.

+  * @rmtoll CFGR     DISCEN         LL_ADC_REG_SetSequencerDiscont\n

+  *         CFGR     DISCNUM        LL_ADC_REG_SetSequencerDiscont

+  * @param  ADCx ADC instance

+  * @param  SeqDiscont This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE

+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK

+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)

+{

+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM, SeqDiscont);

+}

+

+/**

+  * @brief  Get ADC group regular sequencer discontinuous mode:

+  *         sequence subdivided and scan conversions interrupted every selected

+  *         number of ranks.

+  * @rmtoll CFGR     DISCEN         LL_ADC_REG_GetSequencerDiscont\n

+  *         CFGR     DISCNUM        LL_ADC_REG_GetSequencerDiscont

+  * @param  ADCx ADC instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE

+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK

+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_2RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_3RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_4RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_5RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_6RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_7RANKS

+  *         @arg @ref LL_ADC_REG_SEQ_DISCONT_8RANKS

+  */

+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx)

+{

+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM));

+}

+

+/**

+  * @brief  Set ADC group regular sequence: channel on the selected

+  *         scan sequence rank.

+  * @note   This function performs configuration of:

+  *         - Channels ordering into each rank of scan sequence:

+  *           whatever channel can be placed into whatever rank.

+  * @note   On this STM32 serie, ADC group regular sequencer is

+  *         fully configurable: sequencer length and each rank

+  *         affectation to a channel are configurable.

+  *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().

+  * @note   Depending on devices and packages, some channels may not be available.

+  *         Refer to device datasheet for channels availability.

+  * @note   On this STM32 serie, to measure internal channels (VrefInt,

+  *         TempSensor, ...), measurement paths to internal channels must be

+  *         enabled separately.

+  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be disabled or enabled without conversion on going

+  *         on group regular.

+  * @rmtoll SQR1     SQ1            LL_ADC_REG_SetSequencerRanks\n

+  *         SQR1     SQ2            LL_ADC_REG_SetSequencerRanks\n

+  *         SQR1     SQ3            LL_ADC_REG_SetSequencerRanks\n

+  *         SQR1     SQ4            LL_ADC_REG_SetSequencerRanks\n

+  *         SQR2     SQ5            LL_ADC_REG_SetSequencerRanks\n

+  *         SQR2     SQ6            LL_ADC_REG_SetSequencerRanks\n

+  *         SQR2     SQ7            LL_ADC_REG_SetSequencerRanks\n

+  *         SQR2     SQ8            LL_ADC_REG_SetSequencerRanks\n

+  *         SQR2     SQ9            LL_ADC_REG_SetSequencerRanks\n

+  *         SQR3     SQ10           LL_ADC_REG_SetSequencerRanks\n

+  *         SQR3     SQ11           LL_ADC_REG_SetSequencerRanks\n

+  *         SQR3     SQ12           LL_ADC_REG_SetSequencerRanks\n

+  *         SQR3     SQ13           LL_ADC_REG_SetSequencerRanks\n

+  *         SQR3     SQ14           LL_ADC_REG_SetSequencerRanks\n

+  *         SQR4     SQ15           LL_ADC_REG_SetSequencerRanks\n

+  *         SQR4     SQ16           LL_ADC_REG_SetSequencerRanks

+  * @param  ADCx ADC instance

+  * @param  Rank This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_REG_RANK_1

+  *         @arg @ref LL_ADC_REG_RANK_2

+  *         @arg @ref LL_ADC_REG_RANK_3

+  *         @arg @ref LL_ADC_REG_RANK_4

+  *         @arg @ref LL_ADC_REG_RANK_5

+  *         @arg @ref LL_ADC_REG_RANK_6

+  *         @arg @ref LL_ADC_REG_RANK_7

+  *         @arg @ref LL_ADC_REG_RANK_8

+  *         @arg @ref LL_ADC_REG_RANK_9

+  *         @arg @ref LL_ADC_REG_RANK_10

+  *         @arg @ref LL_ADC_REG_RANK_11

+  *         @arg @ref LL_ADC_REG_RANK_12

+  *         @arg @ref LL_ADC_REG_RANK_13

+  *         @arg @ref LL_ADC_REG_RANK_14

+  *         @arg @ref LL_ADC_REG_RANK_15

+  *         @arg @ref LL_ADC_REG_RANK_16

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_CHANNEL_0           (3)

+  *         @arg @ref LL_ADC_CHANNEL_1           (3)

+  *         @arg @ref LL_ADC_CHANNEL_2           (3)

+  *         @arg @ref LL_ADC_CHANNEL_3           (3)

+  *         @arg @ref LL_ADC_CHANNEL_4           (3)

+  *         @arg @ref LL_ADC_CHANNEL_5           (3)

+  *         @arg @ref LL_ADC_CHANNEL_6

+  *         @arg @ref LL_ADC_CHANNEL_7

+  *         @arg @ref LL_ADC_CHANNEL_8

+  *         @arg @ref LL_ADC_CHANNEL_9

+  *         @arg @ref LL_ADC_CHANNEL_10

+  *         @arg @ref LL_ADC_CHANNEL_11

+  *         @arg @ref LL_ADC_CHANNEL_12

+  *         @arg @ref LL_ADC_CHANNEL_13

+  *         @arg @ref LL_ADC_CHANNEL_14

+  *         @arg @ref LL_ADC_CHANNEL_15

+  *         @arg @ref LL_ADC_CHANNEL_16

+  *         @arg @ref LL_ADC_CHANNEL_17

+  *         @arg @ref LL_ADC_CHANNEL_18

+  *         @arg @ref LL_ADC_CHANNEL_19

+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

+  *

+  *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

+  *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

+  *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

+  *             Other channels are slow channels (conversion rate: refer to reference manual).

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)

+{

+  /* Set bits with content of parameter "Channel" with bits position          */

+  /* in register and register position depending on parameter "Rank".         */

+  /* Parameters "Rank" and "Channel" are used with masks because containing   */

+  /* other bits reserved for other purpose.                                   */

+  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));

+

+  MODIFY_REG(*preg,

+             ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK),

+             ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_REG_RANK_ID_SQRX_MASK));

+}

+

+/**

+  * @brief  Get ADC group regular sequence: channel on the selected

+  *         scan sequence rank.

+  * @note   On this STM32 serie, ADC group regular sequencer is

+  *         fully configurable: sequencer length and each rank

+  *         affectation to a channel are configurable.

+  *         Refer to description of function @ref LL_ADC_REG_SetSequencerLength().

+  * @note   Depending on devices and packages, some channels may not be available.

+  *         Refer to device datasheet for channels availability.

+  * @note   Usage of the returned channel number:

+  *         - To reinject this channel into another function LL_ADC_xxx:

+  *           the returned channel number is only partly formatted on definition

+  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared

+  *           with parts of literals LL_ADC_CHANNEL_x or using

+  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

+  *           Then the selected literal LL_ADC_CHANNEL_x can be used

+  *           as parameter for another function.

+  *         - To get the channel number in decimal format:

+  *           process the returned value with the helper macro

+  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

+  * @rmtoll SQR1     SQ1            LL_ADC_REG_GetSequencerRanks\n

+  *         SQR1     SQ2            LL_ADC_REG_GetSequencerRanks\n

+  *         SQR1     SQ3            LL_ADC_REG_GetSequencerRanks\n

+  *         SQR1     SQ4            LL_ADC_REG_GetSequencerRanks\n

+  *         SQR2     SQ5            LL_ADC_REG_GetSequencerRanks\n

+  *         SQR2     SQ6            LL_ADC_REG_GetSequencerRanks\n

+  *         SQR2     SQ7            LL_ADC_REG_GetSequencerRanks\n

+  *         SQR2     SQ8            LL_ADC_REG_GetSequencerRanks\n

+  *         SQR2     SQ9            LL_ADC_REG_GetSequencerRanks\n

+  *         SQR3     SQ10           LL_ADC_REG_GetSequencerRanks\n

+  *         SQR3     SQ11           LL_ADC_REG_GetSequencerRanks\n

+  *         SQR3     SQ12           LL_ADC_REG_GetSequencerRanks\n

+  *         SQR3     SQ13           LL_ADC_REG_GetSequencerRanks\n

+  *         SQR3     SQ14           LL_ADC_REG_GetSequencerRanks\n

+  *         SQR4     SQ15           LL_ADC_REG_GetSequencerRanks\n

+  *         SQR4     SQ16           LL_ADC_REG_GetSequencerRanks

+  * @param  ADCx ADC instance

+  * @param  Rank This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_REG_RANK_1

+  *         @arg @ref LL_ADC_REG_RANK_2

+  *         @arg @ref LL_ADC_REG_RANK_3

+  *         @arg @ref LL_ADC_REG_RANK_4

+  *         @arg @ref LL_ADC_REG_RANK_5

+  *         @arg @ref LL_ADC_REG_RANK_6

+  *         @arg @ref LL_ADC_REG_RANK_7

+  *         @arg @ref LL_ADC_REG_RANK_8

+  *         @arg @ref LL_ADC_REG_RANK_9

+  *         @arg @ref LL_ADC_REG_RANK_10

+  *         @arg @ref LL_ADC_REG_RANK_11

+  *         @arg @ref LL_ADC_REG_RANK_12

+  *         @arg @ref LL_ADC_REG_RANK_13

+  *         @arg @ref LL_ADC_REG_RANK_14

+  *         @arg @ref LL_ADC_REG_RANK_15

+  *         @arg @ref LL_ADC_REG_RANK_16

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_ADC_CHANNEL_0           (3)

+  *         @arg @ref LL_ADC_CHANNEL_1           (3)

+  *         @arg @ref LL_ADC_CHANNEL_2           (3)

+  *         @arg @ref LL_ADC_CHANNEL_3           (3)

+  *         @arg @ref LL_ADC_CHANNEL_4           (3)

+  *         @arg @ref LL_ADC_CHANNEL_5           (3)

+  *         @arg @ref LL_ADC_CHANNEL_6

+  *         @arg @ref LL_ADC_CHANNEL_7

+  *         @arg @ref LL_ADC_CHANNEL_8

+  *         @arg @ref LL_ADC_CHANNEL_9

+  *         @arg @ref LL_ADC_CHANNEL_10

+  *         @arg @ref LL_ADC_CHANNEL_11

+  *         @arg @ref LL_ADC_CHANNEL_12

+  *         @arg @ref LL_ADC_CHANNEL_13

+  *         @arg @ref LL_ADC_CHANNEL_14

+  *         @arg @ref LL_ADC_CHANNEL_15

+  *         @arg @ref LL_ADC_CHANNEL_16

+  *         @arg @ref LL_ADC_CHANNEL_17

+  *         @arg @ref LL_ADC_CHANNEL_18

+  *         @arg @ref LL_ADC_CHANNEL_19

+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

+  *

+  *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

+  *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

+  *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

+  *             Other channels are slow channels (conversion rate: refer to reference manual).\n

+  *         (1, 2) For ADC channel read back from ADC register,

+  *                comparison with internal channel parameter to be done

+  *                using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

+  */

+__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)

+{

+  register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SQR1, ((Rank & ADC_REG_SQRX_REGOFFSET_MASK) >> ADC_SQRX_REGOFFSET_POS));

+

+  return (uint32_t)((READ_BIT(*preg,

+                              ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 << (Rank & ADC_REG_RANK_ID_SQRX_MASK))

+                     >> (Rank & ADC_REG_RANK_ID_SQRX_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS

+                   );

+}

+

+/**

+  * @brief  Set ADC continuous conversion mode on ADC group regular.

+  * @note   Description of ADC continuous conversion mode:

+  *         - single mode: one conversion per trigger

+  *         - continuous mode: after the first trigger, following

+  *           conversions launched successively automatically.

+  * @note   It is not possible to enable both ADC group regular

+  *         continuous mode and sequencer discontinuous mode.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be disabled or enabled without conversion on going

+  *         on group regular.

+  * @rmtoll CFGR     CONT           LL_ADC_REG_SetContinuousMode

+  * @param  ADCx ADC instance

+  * @param  Continuous This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_REG_CONV_SINGLE

+  *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous)

+{

+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_CONT, Continuous);

+}

+

+/**

+  * @brief  Get ADC continuous conversion mode on ADC group regular.

+  * @note   Description of ADC continuous conversion mode:

+  *         - single mode: one conversion per trigger

+  *         - continuous mode: after the first trigger, following

+  *           conversions launched successively automatically.

+  * @rmtoll CFGR     CONT           LL_ADC_REG_GetContinuousMode

+  * @param  ADCx ADC instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_ADC_REG_CONV_SINGLE

+  *         @arg @ref LL_ADC_REG_CONV_CONTINUOUS

+  */

+__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx)

+{

+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_CONT));

+}

+/**

+  * @brief  Set ADC data transfer mode

+  * @note   Conversion data can be either:

+  *            - Available in Data Register

+  *            - Transfered by DMA in one shot mode

+  *            - Transfered by DMA in circular mode

+  *            - Transfered to DFSDM data register

+  * @rmtoll CFGR     DMNGT           LL_ADC_REG_SetDataTransferMode

+  * @param  ADCx ADC instance

+  * @param  DataTransferMode This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_REG_DR_TRANSFER

+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED

+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED

+  *         @arg @ref LL_ADC_REG_DFSDM_TRANSFER

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_REG_SetDataTransferMode(ADC_TypeDef *ADCx, uint32_t DataTransferMode)

+{

+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_DMNGT, DataTransferMode);

+}

+

+

+/**

+  * @brief  Get ADC data transfer mode

+  * @note   Conversion data can be either:

+  *            - Available in Data Register

+  *            - Transfered by DMA in one shot mode

+  *            - Transfered by DMA in circular mode

+  *            - Transfered to DFSDM data register

+  * @rmtoll CFGR     DMNGT           LL_ADC_REG_GetDataTransferMode

+  * @param  ADCx ADC instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_ADC_REG_DR_TRANSFER

+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED

+  *         @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED

+  *         @arg @ref LL_ADC_REG_DFSDM_TRANSFER

+  */

+__STATIC_INLINE uint32_t LL_ADC_REG_GetDataTransferMode(ADC_TypeDef *ADCx)

+{

+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_DMNGT));

+}

+

+

+/**

+  * @brief  Set ADC group regular behavior in case of overrun:

+  *         data preserved or overwritten.

+  * @note   Compatibility with devices without feature overrun:

+  *         other devices without this feature have a behavior

+  *         equivalent to data overwritten.

+  *         The default setting of overrun is data preserved.

+  *         Therefore, for compatibility with all devices, parameter

+  *         overrun should be set to data overwritten.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be disabled or enabled without conversion on going

+  *         on group regular.

+  * @rmtoll CFGR     OVRMOD         LL_ADC_REG_SetOverrun

+  * @param  ADCx ADC instance

+  * @param  Overrun This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED

+  *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun)

+{

+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_OVRMOD, Overrun);

+}

+

+/**

+  * @brief  Get ADC group regular behavior in case of overrun:

+  *         data preserved or overwritten.

+  * @rmtoll CFGR     OVRMOD         LL_ADC_REG_GetOverrun

+  * @param  ADCx ADC instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED

+  *         @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN

+  */

+__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx)

+{

+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_OVRMOD));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Injected Configuration of ADC hierarchical scope: group injected

+  * @{

+  */

+

+/**

+  * @brief  Set ADC group injected conversion trigger source:

+  *         internal (SW start) or from external peripheral (timer event,

+  *         external interrupt line).

+  * @note   On this STM32 serie, setting trigger source to external trigger

+  *         also set trigger polarity to rising edge

+  *         (default setting for compatibility with some ADC on other

+  *         STM32 families having this setting set by HW default value).

+  *         In case of need to modify trigger edge, use

+  *         function @ref LL_ADC_INJ_SetTriggerEdge().

+  * @note   Availability of parameters of trigger sources from timer

+  *         depends on timers availability on the selected device.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must not be disabled. Can be enabled with or without conversion

+  *         on going on either groups regular or injected.

+  * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_SetTriggerSource\n

+  *         JSQR     JEXTEN         LL_ADC_INJ_SetTriggerSource

+  * @param  ADCx ADC instance

+  * @param  TriggerSource This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_INJ_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource)

+{

+  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN, TriggerSource);

+}

+

+/**

+  * @brief  Get ADC group injected conversion trigger source:

+  *         internal (SW start) or from external peripheral (timer event,

+  *         external interrupt line).

+  * @note   To determine whether group injected trigger source is

+  *         internal (SW start) or external, without detail

+  *         of which peripheral is selected as external trigger,

+  *         (equivalent to

+  *         "if(LL_ADC_INJ_GetTriggerSource(ADC1) == LL_ADC_INJ_TRIG_SOFTWARE)")

+  *         use function @ref LL_ADC_INJ_IsTriggerSourceSWStart.

+  * @note   Availability of parameters of trigger sources from timer

+  *         depends on timers availability on the selected device.

+  * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_GetTriggerSource\n

+  *         JSQR     JEXTEN         LL_ADC_INJ_GetTriggerSource

+  * @param  ADCx ADC instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT

+  */

+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerSource(ADC_TypeDef *ADCx)

+{

+  register __IO uint32_t TriggerSource = READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN);

+

+  /* Value for shift of {0; 4; 8; 12} depending on value of bitfield          */

+  /* corresponding to ADC_JSQR_JEXTEN {0; 1; 2; 3}.                           */

+  register uint32_t ShiftJexten = ((TriggerSource & ADC_JSQR_JEXTEN) >> (ADC_INJ_TRIG_EXTEN_BITOFFSET_POS - 2UL));

+

+  /* Set bitfield corresponding to ADC_JSQR_JEXTEN and ADC_JSQR_JEXTSEL       */

+  /* to match with triggers literals definition.                              */

+  return ((TriggerSource

+           & (ADC_INJ_TRIG_SOURCE_MASK >> ShiftJexten) & ADC_JSQR_JEXTSEL)

+          | ((ADC_INJ_TRIG_EDGE_MASK >> ShiftJexten) & ADC_JSQR_JEXTEN)

+         );

+}

+

+/**

+  * @brief  Get ADC group injected conversion trigger source internal (SW start)

+            or external

+  * @note   In case of group injected trigger source set to external trigger,

+  *         to determine which peripheral is selected as external trigger,

+  *         use function @ref LL_ADC_INJ_GetTriggerSource.

+  * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_IsTriggerSourceSWStart

+  * @param  ADCx ADC instance

+  * @retval Value "0" if trigger source external trigger

+  *         Value "1" if trigger source SW start.

+  */

+__STATIC_INLINE uint32_t LL_ADC_INJ_IsTriggerSourceSWStart(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN) == (LL_ADC_INJ_TRIG_SOFTWARE & ADC_JSQR_JEXTEN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set ADC group injected conversion trigger polarity.

+  *         Applicable only for trigger source set to external trigger.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must not be disabled. Can be enabled with or without conversion

+  *         on going on either groups regular or injected.

+  * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_SetTriggerEdge

+  * @param  ADCx ADC instance

+  * @param  ExternalTriggerEdge This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_INJ_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge)

+{

+  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JEXTEN, ExternalTriggerEdge);

+}

+

+/**

+  * @brief  Get ADC group injected conversion trigger polarity.

+  *         Applicable only for trigger source set to external trigger.

+  * @rmtoll JSQR     JEXTEN         LL_ADC_INJ_GetTriggerEdge

+  * @param  ADCx ADC instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING

+  */

+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTriggerEdge(ADC_TypeDef *ADCx)

+{

+  return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JEXTEN));

+}

+

+/**

+  * @brief  Set ADC group injected sequencer length and scan direction.

+  * @note   This function performs configuration of:

+  *         - Sequence length: Number of ranks in the scan sequence.

+  *         - Sequence direction: Unless specified in parameters, sequencer

+  *           scan direction is forward (from rank 1 to rank n).

+  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:

+  *         ADC conversion on only 1 channel.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must not be disabled. Can be enabled with or without conversion

+  *         on going on either groups regular or injected.

+  * @rmtoll JSQR     JL             LL_ADC_INJ_SetSequencerLength

+  * @param  ADCx ADC instance

+  * @param  SequencerNbRanks This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE

+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS

+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS

+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_INJ_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks)

+{

+  MODIFY_REG(ADCx->JSQR, ADC_JSQR_JL, SequencerNbRanks);

+}

+

+/**

+  * @brief  Get ADC group injected sequencer length and scan direction.

+  * @note   This function retrieves:

+  *         - Sequence length: Number of ranks in the scan sequence.

+  *         - Sequence direction: Unless specified in parameters, sequencer

+  *           scan direction is forward (from rank 1 to rank n).

+  * @note   Sequencer disabled is equivalent to sequencer of 1 rank:

+  *         ADC conversion on only 1 channel.

+  * @rmtoll JSQR     JL             LL_ADC_INJ_GetSequencerLength

+  * @param  ADCx ADC instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE

+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS

+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS

+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS

+  */

+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerLength(ADC_TypeDef *ADCx)

+{

+  return (uint32_t)(READ_BIT(ADCx->JSQR, ADC_JSQR_JL));

+}

+

+/**

+  * @brief  Set ADC group injected sequencer discontinuous mode:

+  *         sequence subdivided and scan conversions interrupted every selected

+  *         number of ranks.

+  * @note   It is not possible to enable both ADC group injected

+  *         auto-injected mode and sequencer discontinuous mode.

+  * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_SetSequencerDiscont

+  * @param  ADCx ADC instance

+  * @param  SeqDiscont This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE

+  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_INJ_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont)

+{

+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_JDISCEN, SeqDiscont);

+}

+

+/**

+  * @brief  Get ADC group injected sequencer discontinuous mode:

+  *         sequence subdivided and scan conversions interrupted every selected

+  *         number of ranks.

+  * @rmtoll CFGR     JDISCEN        LL_ADC_INJ_GetSequencerDiscont

+  * @param  ADCx ADC instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_DISABLE

+  *         @arg @ref LL_ADC_INJ_SEQ_DISCONT_1RANK

+  */

+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerDiscont(ADC_TypeDef *ADCx)

+{

+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JDISCEN));

+}

+

+/**

+  * @brief  Set ADC group injected sequence: channel on the selected

+  *         sequence rank.

+  * @note   Depending on devices and packages, some channels may not be available.

+  *         Refer to device datasheet for channels availability.

+  * @note   On this STM32 serie, to measure internal channels (VrefInt,

+  *         TempSensor, ...), measurement paths to internal channels must be

+  *         enabled separately.

+  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().

+  * @note   On STM32H7, some fast channels are available: fast analog inputs

+  *         coming from GPIO pads (ADC_IN0..5).

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must not be disabled. Can be enabled with or without conversion

+  *         on going on either groups regular or injected.

+  * @rmtoll JSQR     JSQ1           LL_ADC_INJ_SetSequencerRanks\n

+  *         JSQR     JSQ2           LL_ADC_INJ_SetSequencerRanks\n

+  *         JSQR     JSQ3           LL_ADC_INJ_SetSequencerRanks\n

+  *         JSQR     JSQ4           LL_ADC_INJ_SetSequencerRanks

+  * @param  ADCx ADC instance

+  * @param  Rank This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_INJ_RANK_1

+  *         @arg @ref LL_ADC_INJ_RANK_2

+  *         @arg @ref LL_ADC_INJ_RANK_3

+  *         @arg @ref LL_ADC_INJ_RANK_4

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_CHANNEL_0           (3)

+  *         @arg @ref LL_ADC_CHANNEL_1           (3)

+  *         @arg @ref LL_ADC_CHANNEL_2           (3)

+  *         @arg @ref LL_ADC_CHANNEL_3           (3)

+  *         @arg @ref LL_ADC_CHANNEL_4           (3)

+  *         @arg @ref LL_ADC_CHANNEL_5           (3)

+  *         @arg @ref LL_ADC_CHANNEL_6

+  *         @arg @ref LL_ADC_CHANNEL_7

+  *         @arg @ref LL_ADC_CHANNEL_8

+  *         @arg @ref LL_ADC_CHANNEL_9

+  *         @arg @ref LL_ADC_CHANNEL_10

+  *         @arg @ref LL_ADC_CHANNEL_11

+  *         @arg @ref LL_ADC_CHANNEL_12

+  *         @arg @ref LL_ADC_CHANNEL_13

+  *         @arg @ref LL_ADC_CHANNEL_14

+  *         @arg @ref LL_ADC_CHANNEL_15

+  *         @arg @ref LL_ADC_CHANNEL_16

+  *         @arg @ref LL_ADC_CHANNEL_17

+  *         @arg @ref LL_ADC_CHANNEL_18

+  *         @arg @ref LL_ADC_CHANNEL_19

+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

+  *

+  *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

+  *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

+  *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

+  *             Other channels are slow channels (conversion rate: refer to reference manual).

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_INJ_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel)

+{

+  /* Set bits with content of parameter "Channel" with bits position          */

+  /* in register depending on parameter "Rank".                               */

+  /* Parameters "Rank" and "Channel" are used with masks because containing   */

+  /* other bits reserved for other purpose.                                   */

+  MODIFY_REG(ADCx->JSQR,

+             (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK),

+             ((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK));

+}

+

+/**

+  * @brief  Get ADC group injected sequence: channel on the selected

+  *         sequence rank.

+  * @note   Depending on devices and packages, some channels may not be available.

+  *         Refer to device datasheet for channels availability.

+  * @note   Usage of the returned channel number:

+  *         - To reinject this channel into another function LL_ADC_xxx:

+  *           the returned channel number is only partly formatted on definition

+  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared

+  *           with parts of literals LL_ADC_CHANNEL_x or using

+  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

+  *           Then the selected literal LL_ADC_CHANNEL_x can be used

+  *           as parameter for another function.

+  *         - To get the channel number in decimal format:

+  *           process the returned value with the helper macro

+  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

+  * @rmtoll JSQR     JSQ1           LL_ADC_INJ_GetSequencerRanks\n

+  *         JSQR     JSQ2           LL_ADC_INJ_GetSequencerRanks\n

+  *         JSQR     JSQ3           LL_ADC_INJ_GetSequencerRanks\n

+  *         JSQR     JSQ4           LL_ADC_INJ_GetSequencerRanks

+  * @param  ADCx ADC instance

+  * @param  Rank This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_INJ_RANK_1

+  *         @arg @ref LL_ADC_INJ_RANK_2

+  *         @arg @ref LL_ADC_INJ_RANK_3

+  *         @arg @ref LL_ADC_INJ_RANK_4

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_ADC_CHANNEL_0           (3)

+  *         @arg @ref LL_ADC_CHANNEL_1           (3)

+  *         @arg @ref LL_ADC_CHANNEL_2           (3)

+  *         @arg @ref LL_ADC_CHANNEL_3           (3)

+  *         @arg @ref LL_ADC_CHANNEL_4           (3)

+  *         @arg @ref LL_ADC_CHANNEL_5           (3)

+  *         @arg @ref LL_ADC_CHANNEL_6

+  *         @arg @ref LL_ADC_CHANNEL_7

+  *         @arg @ref LL_ADC_CHANNEL_8

+  *         @arg @ref LL_ADC_CHANNEL_9

+  *         @arg @ref LL_ADC_CHANNEL_10

+  *         @arg @ref LL_ADC_CHANNEL_11

+  *         @arg @ref LL_ADC_CHANNEL_12

+  *         @arg @ref LL_ADC_CHANNEL_13

+  *         @arg @ref LL_ADC_CHANNEL_14

+  *         @arg @ref LL_ADC_CHANNEL_15

+  *         @arg @ref LL_ADC_CHANNEL_16

+  *         @arg @ref LL_ADC_CHANNEL_17

+  *         @arg @ref LL_ADC_CHANNEL_18

+  *         @arg @ref LL_ADC_CHANNEL_19

+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

+  *

+  *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

+  *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

+  *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

+  *             Other channels are slow channels (conversion rate: refer to reference manual).\n

+  *         (1, 2) For ADC channel read back from ADC register,

+  *                comparison with internal channel parameter to be done

+  *                using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().

+  */

+__STATIC_INLINE uint32_t LL_ADC_INJ_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank)

+{

+  return (uint32_t)((READ_BIT(ADCx->JSQR,

+                              (ADC_CHANNEL_ID_NUMBER_MASK >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (Rank & ADC_INJ_RANK_ID_JSQR_MASK))

+                     >> (Rank & ADC_INJ_RANK_ID_JSQR_MASK)) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS

+                   );

+}

+

+/**

+  * @brief  Set ADC group injected conversion trigger:

+  *         independent or from ADC group regular.

+  * @note   This mode can be used to extend number of data registers

+  *         updated after one ADC conversion trigger and with data

+  *         permanently kept (not erased by successive conversions of scan of

+  *         ADC sequencer ranks), up to 5 data registers:

+  *         1 data register on ADC group regular, 4 data registers

+  *         on ADC group injected.

+  * @note   If ADC group injected injected trigger source is set to an

+  *         external trigger, this feature must be must be set to

+  *         independent trigger.

+  *         ADC group injected automatic trigger is compliant only with

+  *         group injected trigger source set to SW start, without any

+  *         further action on  ADC group injected conversion start or stop:

+  *         in this case, ADC group injected is controlled only

+  *         from ADC group regular.

+  * @note   It is not possible to enable both ADC group injected

+  *         auto-injected mode and sequencer discontinuous mode.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be disabled or enabled without conversion on going

+  *         on either groups regular or injected.

+  * @rmtoll CFGR     JAUTO          LL_ADC_INJ_SetTrigAuto

+  * @param  ADCx ADC instance

+  * @param  TrigAuto This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT

+  *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_INJ_SetTrigAuto(ADC_TypeDef *ADCx, uint32_t TrigAuto)

+{

+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_JAUTO, TrigAuto);

+}

+

+/**

+  * @brief  Get ADC group injected conversion trigger:

+  *         independent or from ADC group regular.

+  * @rmtoll CFGR     JAUTO          LL_ADC_INJ_GetTrigAuto

+  * @param  ADCx ADC instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_ADC_INJ_TRIG_INDEPENDENT

+  *         @arg @ref LL_ADC_INJ_TRIG_FROM_GRP_REGULAR

+  */

+__STATIC_INLINE uint32_t LL_ADC_INJ_GetTrigAuto(ADC_TypeDef *ADCx)

+{

+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JAUTO));

+}

+

+/**

+  * @brief  Set ADC group injected contexts queue mode.

+  * @note   A context is a setting of group injected sequencer:

+  *         - group injected trigger

+  *         - sequencer length

+  *         - sequencer ranks

+  *         If contexts queue is disabled:

+  *         - only 1 sequence can be configured

+  *           and is active perpetually.

+  *         If contexts queue is enabled:

+  *         - up to 2 contexts can be queued

+  *           and are checked in and out as a FIFO stack (first-in, first-out).

+  *         - If a new context is set when queues is full, error is triggered

+  *           by interruption "Injected Queue Overflow".

+  *         - Two behaviors are possible when all contexts have been processed:

+  *           the contexts queue can maintain the last context active perpetually

+  *           or can be empty and injected group triggers are disabled.

+  *         - Triggers can be only external (not internal SW start)

+  *         - Caution: The sequence must be fully configured in one time

+  *           (one write of register JSQR makes a check-in of a new context

+  *           into the queue).

+  *           Therefore functions to set separately injected trigger and

+  *           sequencer channels cannot be used, register JSQR must be set

+  *           using function @ref LL_ADC_INJ_ConfigQueueContext().

+  * @note   This parameter can be modified only when no conversion is on going

+  *         on either groups regular or injected.

+  * @note   A modification of the context mode (bit JQDIS) causes the contexts

+  *         queue to be flushed and the register JSQR is cleared.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be disabled or enabled without conversion on going

+  *         on either groups regular or injected.

+  * @rmtoll CFGR     JQM            LL_ADC_INJ_SetQueueMode\n

+  *         CFGR     JQDIS          LL_ADC_INJ_SetQueueMode

+  * @param  ADCx ADC instance

+  * @param  QueueMode This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_INJ_QUEUE_DISABLE

+  *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE

+  *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_INJ_SetQueueMode(ADC_TypeDef *ADCx, uint32_t QueueMode)

+{

+  MODIFY_REG(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS, QueueMode);

+}

+

+/**

+  * @brief  Get ADC group injected context queue mode.

+  * @rmtoll CFGR     JQM            LL_ADC_INJ_GetQueueMode\n

+  *         CFGR     JQDIS          LL_ADC_INJ_GetQueueMode

+  * @param  ADCx ADC instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_ADC_INJ_QUEUE_DISABLE

+  *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_LAST_ACTIVE

+  *         @arg @ref LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY

+  */

+__STATIC_INLINE uint32_t LL_ADC_INJ_GetQueueMode(ADC_TypeDef *ADCx)

+{

+  return (uint32_t)(READ_BIT(ADCx->CFGR, ADC_CFGR_JQM | ADC_CFGR_JQDIS));

+}

+

+/**

+  * @brief  Set one context on ADC group injected that will be checked in

+  *         contexts queue.

+  * @note   A context is a setting of group injected sequencer:

+  *         - group injected trigger

+  *         - sequencer length

+  *         - sequencer ranks

+  *         This function is intended to be used when contexts queue is enabled,

+  *         because the sequence must be fully configured in one time

+  *         (functions to set separately injected trigger and sequencer channels

+  *         cannot be used):

+  *         Refer to function @ref LL_ADC_INJ_SetQueueMode().

+  * @note   In the contexts queue, only the active context can be read.

+  *         The parameters of this function can be read using functions:

+  *         @arg @ref LL_ADC_INJ_GetTriggerSource()

+  *         @arg @ref LL_ADC_INJ_GetTriggerEdge()

+  *         @arg @ref LL_ADC_INJ_GetSequencerRanks()

+  * @note   On this STM32 serie, to measure internal channels (VrefInt,

+  *         TempSensor, ...), measurement paths to internal channels must be

+  *         enabled separately.

+  *         This can be done using function @ref LL_ADC_SetCommonPathInternalCh().

+  * @note   On STM32H7, some fast channels are available: fast analog inputs

+  *         coming from GPIO pads (ADC_IN0..5).

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must not be disabled. Can be enabled with or without conversion

+  *         on going on either groups regular or injected.

+  * @rmtoll JSQR     JEXTSEL        LL_ADC_INJ_ConfigQueueContext\n

+  *         JSQR     JEXTEN         LL_ADC_INJ_ConfigQueueContext\n

+  *         JSQR     JL             LL_ADC_INJ_ConfigQueueContext\n

+  *         JSQR     JSQ1           LL_ADC_INJ_ConfigQueueContext\n

+  *         JSQR     JSQ2           LL_ADC_INJ_ConfigQueueContext\n

+  *         JSQR     JSQ3           LL_ADC_INJ_ConfigQueueContext\n

+  *         JSQR     JSQ4           LL_ADC_INJ_ConfigQueueContext

+  * @param  ADCx ADC instance

+  * @param  TriggerSource This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_INJ_TRIG_SOFTWARE

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_CH4

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_TRGO

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM2_CH1

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH4

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM4_TRGO

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_EXTI_LINE15

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_CH4

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH3

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_TRGO

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM3_CH1

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM6_TRGO

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_TIM15_TRGO

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM1_OUT

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM2_OUT

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_LPTIM3_OUT

+  * @param  ExternalTriggerEdge This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISING

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_FALLING

+  *         @arg @ref LL_ADC_INJ_TRIG_EXT_RISINGFALLING

+  *

+  *         Note: This parameter is discarded in case of SW start:

+  *               parameter "TriggerSource" set to "LL_ADC_INJ_TRIG_SOFTWARE".

+  * @param  SequencerNbRanks This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_DISABLE

+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS

+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS

+  *         @arg @ref LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS

+  * @param  Rank1_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_CHANNEL_0           (3)

+  *         @arg @ref LL_ADC_CHANNEL_1           (3)

+  *         @arg @ref LL_ADC_CHANNEL_2           (3)

+  *         @arg @ref LL_ADC_CHANNEL_3           (3)

+  *         @arg @ref LL_ADC_CHANNEL_4           (3)

+  *         @arg @ref LL_ADC_CHANNEL_5           (3)

+  *         @arg @ref LL_ADC_CHANNEL_6

+  *         @arg @ref LL_ADC_CHANNEL_7

+  *         @arg @ref LL_ADC_CHANNEL_8

+  *         @arg @ref LL_ADC_CHANNEL_9

+  *         @arg @ref LL_ADC_CHANNEL_10

+  *         @arg @ref LL_ADC_CHANNEL_11

+  *         @arg @ref LL_ADC_CHANNEL_12

+  *         @arg @ref LL_ADC_CHANNEL_13

+  *         @arg @ref LL_ADC_CHANNEL_14

+  *         @arg @ref LL_ADC_CHANNEL_15

+  *         @arg @ref LL_ADC_CHANNEL_16

+  *         @arg @ref LL_ADC_CHANNEL_17

+  *         @arg @ref LL_ADC_CHANNEL_18

+  *         @arg @ref LL_ADC_CHANNEL_19

+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

+  *

+  *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

+  *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

+  *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

+  *             Other channels are slow channels (conversion rate: refer to reference manual).

+  * @param  Rank2_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_CHANNEL_0           (3)

+  *         @arg @ref LL_ADC_CHANNEL_1           (3)

+  *         @arg @ref LL_ADC_CHANNEL_2           (3)

+  *         @arg @ref LL_ADC_CHANNEL_3           (3)

+  *         @arg @ref LL_ADC_CHANNEL_4           (3)

+  *         @arg @ref LL_ADC_CHANNEL_5           (3)

+  *         @arg @ref LL_ADC_CHANNEL_6

+  *         @arg @ref LL_ADC_CHANNEL_7

+  *         @arg @ref LL_ADC_CHANNEL_8

+  *         @arg @ref LL_ADC_CHANNEL_9

+  *         @arg @ref LL_ADC_CHANNEL_10

+  *         @arg @ref LL_ADC_CHANNEL_11

+  *         @arg @ref LL_ADC_CHANNEL_12

+  *         @arg @ref LL_ADC_CHANNEL_13

+  *         @arg @ref LL_ADC_CHANNEL_14

+  *         @arg @ref LL_ADC_CHANNEL_15

+  *         @arg @ref LL_ADC_CHANNEL_16

+  *         @arg @ref LL_ADC_CHANNEL_17

+  *         @arg @ref LL_ADC_CHANNEL_18

+  *         @arg @ref LL_ADC_CHANNEL_19

+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

+  *

+  *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

+  *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

+  *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

+  *             Other channels are slow channels (conversion rate: refer to reference manual).

+  * @param  Rank3_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_CHANNEL_0           (3)

+  *         @arg @ref LL_ADC_CHANNEL_1           (3)

+  *         @arg @ref LL_ADC_CHANNEL_2           (3)

+  *         @arg @ref LL_ADC_CHANNEL_3           (3)

+  *         @arg @ref LL_ADC_CHANNEL_4           (3)

+  *         @arg @ref LL_ADC_CHANNEL_5           (3)

+  *         @arg @ref LL_ADC_CHANNEL_6

+  *         @arg @ref LL_ADC_CHANNEL_7

+  *         @arg @ref LL_ADC_CHANNEL_8

+  *         @arg @ref LL_ADC_CHANNEL_9

+  *         @arg @ref LL_ADC_CHANNEL_10

+  *         @arg @ref LL_ADC_CHANNEL_11

+  *         @arg @ref LL_ADC_CHANNEL_12

+  *         @arg @ref LL_ADC_CHANNEL_13

+  *         @arg @ref LL_ADC_CHANNEL_14

+  *         @arg @ref LL_ADC_CHANNEL_15

+  *         @arg @ref LL_ADC_CHANNEL_16

+  *         @arg @ref LL_ADC_CHANNEL_17

+  *         @arg @ref LL_ADC_CHANNEL_18

+  *         @arg @ref LL_ADC_CHANNEL_19

+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

+  *

+  *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

+  *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

+  *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

+  *             Other channels are slow channels (conversion rate: refer to reference manual).

+  * @param  Rank4_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_CHANNEL_0           (3)

+  *         @arg @ref LL_ADC_CHANNEL_1           (3)

+  *         @arg @ref LL_ADC_CHANNEL_2           (3)

+  *         @arg @ref LL_ADC_CHANNEL_3           (3)

+  *         @arg @ref LL_ADC_CHANNEL_4           (3)

+  *         @arg @ref LL_ADC_CHANNEL_5           (3)

+  *         @arg @ref LL_ADC_CHANNEL_6

+  *         @arg @ref LL_ADC_CHANNEL_7

+  *         @arg @ref LL_ADC_CHANNEL_8

+  *         @arg @ref LL_ADC_CHANNEL_9

+  *         @arg @ref LL_ADC_CHANNEL_10

+  *         @arg @ref LL_ADC_CHANNEL_11

+  *         @arg @ref LL_ADC_CHANNEL_12

+  *         @arg @ref LL_ADC_CHANNEL_13

+  *         @arg @ref LL_ADC_CHANNEL_14

+  *         @arg @ref LL_ADC_CHANNEL_15

+  *         @arg @ref LL_ADC_CHANNEL_16

+  *         @arg @ref LL_ADC_CHANNEL_17

+  *         @arg @ref LL_ADC_CHANNEL_18

+  *         @arg @ref LL_ADC_CHANNEL_19

+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

+  *

+  *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

+  *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

+  *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

+  *             Other channels are slow channels (conversion rate: refer to reference manual).

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_INJ_ConfigQueueContext(ADC_TypeDef *ADCx,

+                                                   uint32_t TriggerSource,

+                                                   uint32_t ExternalTriggerEdge,

+                                                   uint32_t SequencerNbRanks,

+                                                   uint32_t Rank1_Channel,

+                                                   uint32_t Rank2_Channel,

+                                                   uint32_t Rank3_Channel,

+                                                   uint32_t Rank4_Channel)

+{

+  /* Set bits with content of parameter "Rankx_Channel" with bits position    */

+  /* in register depending on literal "LL_ADC_INJ_RANK_x".                    */

+  /* Parameters "Rankx_Channel" and "LL_ADC_INJ_RANK_x" are used with masks   */

+  /* because containing other bits reserved for other purpose.                */

+  /* If parameter "TriggerSource" is set to SW start, then parameter          */

+  /* "ExternalTriggerEdge" is discarded.                                      */

+  register uint32_t is_trigger_not_sw = (uint32_t)((TriggerSource != LL_ADC_INJ_TRIG_SOFTWARE) ? 1UL : 0UL);

+  MODIFY_REG(ADCx->JSQR,

+             ADC_JSQR_JEXTSEL |

+             ADC_JSQR_JEXTEN  |

+             ADC_JSQR_JSQ4    |

+             ADC_JSQR_JSQ3    |

+             ADC_JSQR_JSQ2    |

+             ADC_JSQR_JSQ1    |

+             ADC_JSQR_JL,

+             (TriggerSource & ADC_JSQR_JEXTSEL)          |

+             (ExternalTriggerEdge * (is_trigger_not_sw)) |

+             (((Rank4_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_4 & ADC_INJ_RANK_ID_JSQR_MASK)) |

+             (((Rank3_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_3 & ADC_INJ_RANK_ID_JSQR_MASK)) |

+             (((Rank2_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_2 & ADC_INJ_RANK_ID_JSQR_MASK)) |

+             (((Rank1_Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) << (LL_ADC_INJ_RANK_1 & ADC_INJ_RANK_ID_JSQR_MASK)) |

+             SequencerNbRanks

+            );

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels

+  * @{

+  */

+

+/**

+  * @brief  Set sampling time of the selected ADC channel

+  *         Unit: ADC clock cycles.

+  * @note   On this device, sampling time is on channel scope: independently

+  *         of channel mapped on ADC group regular or injected.

+  * @note   In case of internal channel (VrefInt, TempSensor, ...) to be

+  *         converted:

+  *         sampling time constraints must be respected (sampling time can be

+  *         adjusted in function of ADC clock frequency and sampling time

+  *         setting).

+  *         Refer to device datasheet for timings values (parameters TS_vrefint,

+  *         TS_temp, ...).

+  * @note   Conversion time is the addition of sampling time and processing time.

+  *         On this STM32 serie, ADC processing time is:

+  *         - 12.5 ADC clock cycles at ADC resolution 12 bits

+  *         - 10.5 ADC clock cycles at ADC resolution 10 bits

+  *         - 8.5 ADC clock cycles at ADC resolution 8 bits

+  *         - 6.5 ADC clock cycles at ADC resolution 6 bits

+  * @note   In case of ADC conversion of internal channel (VrefInt,

+  *         temperature sensor, ...), a sampling time minimum value

+  *         is required.

+  *         Refer to device datasheet.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be disabled or enabled without conversion on going

+  *         on either groups regular or injected.

+  * @rmtoll SMPR1    SMP0           LL_ADC_SetChannelSamplingTime\n

+  *         SMPR1    SMP1           LL_ADC_SetChannelSamplingTime\n

+  *         SMPR1    SMP2           LL_ADC_SetChannelSamplingTime\n

+  *         SMPR1    SMP3           LL_ADC_SetChannelSamplingTime\n

+  *         SMPR1    SMP4           LL_ADC_SetChannelSamplingTime\n

+  *         SMPR1    SMP5           LL_ADC_SetChannelSamplingTime\n

+  *         SMPR1    SMP6           LL_ADC_SetChannelSamplingTime\n

+  *         SMPR1    SMP7           LL_ADC_SetChannelSamplingTime\n

+  *         SMPR1    SMP8           LL_ADC_SetChannelSamplingTime\n

+  *         SMPR1    SMP9           LL_ADC_SetChannelSamplingTime\n

+  *         SMPR2    SMP10          LL_ADC_SetChannelSamplingTime\n

+  *         SMPR2    SMP11          LL_ADC_SetChannelSamplingTime\n

+  *         SMPR2    SMP12          LL_ADC_SetChannelSamplingTime\n

+  *         SMPR2    SMP13          LL_ADC_SetChannelSamplingTime\n

+  *         SMPR2    SMP14          LL_ADC_SetChannelSamplingTime\n

+  *         SMPR2    SMP15          LL_ADC_SetChannelSamplingTime\n

+  *         SMPR2    SMP16          LL_ADC_SetChannelSamplingTime\n

+  *         SMPR2    SMP17          LL_ADC_SetChannelSamplingTime\n

+  *         SMPR2    SMP18          LL_ADC_SetChannelSamplingTime

+  * @param  ADCx ADC instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_CHANNEL_0           (3)

+  *         @arg @ref LL_ADC_CHANNEL_1           (3)

+  *         @arg @ref LL_ADC_CHANNEL_2           (3)

+  *         @arg @ref LL_ADC_CHANNEL_3           (3)

+  *         @arg @ref LL_ADC_CHANNEL_4           (3)

+  *         @arg @ref LL_ADC_CHANNEL_5           (3)

+  *         @arg @ref LL_ADC_CHANNEL_6

+  *         @arg @ref LL_ADC_CHANNEL_7

+  *         @arg @ref LL_ADC_CHANNEL_8

+  *         @arg @ref LL_ADC_CHANNEL_9

+  *         @arg @ref LL_ADC_CHANNEL_10

+  *         @arg @ref LL_ADC_CHANNEL_11

+  *         @arg @ref LL_ADC_CHANNEL_12

+  *         @arg @ref LL_ADC_CHANNEL_13

+  *         @arg @ref LL_ADC_CHANNEL_14

+  *         @arg @ref LL_ADC_CHANNEL_15

+  *         @arg @ref LL_ADC_CHANNEL_16

+  *         @arg @ref LL_ADC_CHANNEL_17

+  *         @arg @ref LL_ADC_CHANNEL_18

+  *         @arg @ref LL_ADC_CHANNEL_19

+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

+  *

+  *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

+  *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

+  *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

+  *             Other channels are slow channels (conversion rate: refer to reference manual).

+  * @param  SamplingTime This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5

+  *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5

+  *         @arg @ref LL_ADC_SAMPLINGTIME_8CYCLES_5

+  *         @arg @ref LL_ADC_SAMPLINGTIME_16CYCLES_5

+  *         @arg @ref LL_ADC_SAMPLINGTIME_32CYCLES_5

+  *         @arg @ref LL_ADC_SAMPLINGTIME_64CYCLES_5

+  *         @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5

+  *         @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTime)

+{

+  /* Set bits with content of parameter "SamplingTime" with bits position     */

+  /* in register and register position depending on parameter "Channel".      */

+  /* Parameter "Channel" is used with masks because containing                */

+  /* other bits reserved for other purpose.                                   */

+  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));

+

+  MODIFY_REG(*preg,

+             ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS),

+             SamplingTime   << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS));

+}

+

+/**

+  * @brief  Get sampling time of the selected ADC channel

+  *         Unit: ADC clock cycles.

+  * @note   On this device, sampling time is on channel scope: independently

+  *         of channel mapped on ADC group regular or injected.

+  * @note   Conversion time is the addition of sampling time and processing time.

+  *         On this STM32 serie, ADC processing time is:

+  *         - 12.5 ADC clock cycles at ADC resolution 12 bits

+  *         - 10.5 ADC clock cycles at ADC resolution 10 bits

+  *         - 8.5 ADC clock cycles at ADC resolution 8 bits

+  *         - 6.5 ADC clock cycles at ADC resolution 6 bits

+  * @rmtoll SMPR1    SMP0           LL_ADC_GetChannelSamplingTime\n

+  *         SMPR1    SMP1           LL_ADC_GetChannelSamplingTime\n

+  *         SMPR1    SMP2           LL_ADC_GetChannelSamplingTime\n

+  *         SMPR1    SMP3           LL_ADC_GetChannelSamplingTime\n

+  *         SMPR1    SMP4           LL_ADC_GetChannelSamplingTime\n

+  *         SMPR1    SMP5           LL_ADC_GetChannelSamplingTime\n

+  *         SMPR1    SMP6           LL_ADC_GetChannelSamplingTime\n

+  *         SMPR1    SMP7           LL_ADC_GetChannelSamplingTime\n

+  *         SMPR1    SMP8           LL_ADC_GetChannelSamplingTime\n

+  *         SMPR1    SMP9           LL_ADC_GetChannelSamplingTime\n

+  *         SMPR2    SMP10          LL_ADC_GetChannelSamplingTime\n

+  *         SMPR2    SMP11          LL_ADC_GetChannelSamplingTime\n

+  *         SMPR2    SMP12          LL_ADC_GetChannelSamplingTime\n

+  *         SMPR2    SMP13          LL_ADC_GetChannelSamplingTime\n

+  *         SMPR2    SMP14          LL_ADC_GetChannelSamplingTime\n

+  *         SMPR2    SMP15          LL_ADC_GetChannelSamplingTime\n

+  *         SMPR2    SMP16          LL_ADC_GetChannelSamplingTime\n

+  *         SMPR2    SMP17          LL_ADC_GetChannelSamplingTime\n

+  *         SMPR2    SMP18          LL_ADC_GetChannelSamplingTime

+  * @param  ADCx ADC instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_CHANNEL_0           (3)

+  *         @arg @ref LL_ADC_CHANNEL_1           (3)

+  *         @arg @ref LL_ADC_CHANNEL_2           (3)

+  *         @arg @ref LL_ADC_CHANNEL_3           (3)

+  *         @arg @ref LL_ADC_CHANNEL_4           (3)

+  *         @arg @ref LL_ADC_CHANNEL_5           (3)

+  *         @arg @ref LL_ADC_CHANNEL_6

+  *         @arg @ref LL_ADC_CHANNEL_7

+  *         @arg @ref LL_ADC_CHANNEL_8

+  *         @arg @ref LL_ADC_CHANNEL_9

+  *         @arg @ref LL_ADC_CHANNEL_10

+  *         @arg @ref LL_ADC_CHANNEL_11

+  *         @arg @ref LL_ADC_CHANNEL_12

+  *         @arg @ref LL_ADC_CHANNEL_13

+  *         @arg @ref LL_ADC_CHANNEL_14

+  *         @arg @ref LL_ADC_CHANNEL_15

+  *         @arg @ref LL_ADC_CHANNEL_16

+  *         @arg @ref LL_ADC_CHANNEL_17

+  *         @arg @ref LL_ADC_CHANNEL_18

+  *         @arg @ref LL_ADC_CHANNEL_19

+  *         @arg @ref LL_ADC_CHANNEL_VREFINT      (1)

+  *         @arg @ref LL_ADC_CHANNEL_TEMPSENSOR   (1)

+  *         @arg @ref LL_ADC_CHANNEL_VBAT         (1)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH1_ADC2 (2)

+  *         @arg @ref LL_ADC_CHANNEL_DAC1CH2_ADC2 (2)

+  *

+  *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

+  *         (2) On STM32H7, parameter available only on ADC instance: ADC2.\n

+  *         (3) On STM32H7, fast channel (0.125 us for 14-bit resolution (ADC conversion rate up to 8 Ms/s)).

+  *             Other channels are slow channels (conversion rate: refer to reference manual).

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5

+  *         @arg @ref LL_ADC_SAMPLINGTIME_2CYCLES_5

+  *         @arg @ref LL_ADC_SAMPLINGTIME_8CYCLES_5

+  *         @arg @ref LL_ADC_SAMPLINGTIME_16CYCLES_5

+  *         @arg @ref LL_ADC_SAMPLINGTIME_32CYCLES_5

+  *         @arg @ref LL_ADC_SAMPLINGTIME_64CYCLES_5

+  *         @arg @ref LL_ADC_SAMPLINGTIME_387CYCLES_5

+  *         @arg @ref LL_ADC_SAMPLINGTIME_810CYCLES_5

+  */

+__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel)

+{

+  register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->SMPR1, ((Channel & ADC_CHANNEL_SMPRX_REGOFFSET_MASK) >> ADC_SMPRX_REGOFFSET_POS));

+

+  return (uint32_t)(READ_BIT(*preg,

+                             ADC_SMPR1_SMP0 << ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS))

+                    >> ((Channel & ADC_CHANNEL_SMPx_BITOFFSET_MASK) >> ADC_CHANNEL_SMPx_BITOFFSET_POS)

+                   );

+}

+

+/**

+  * @brief  Set mode single-ended or differential input of the selected

+  *         ADC channel.

+  * @note   Channel ending is on channel scope: independently of channel mapped

+  *         on ADC group regular or injected.

+  *         In differential mode: Differential measurement is carried out

+  *         between the selected channel 'i' (positive input) and

+  *         channel 'i+1' (negative input). Only channel 'i' has to be

+  *         configured, channel 'i+1' is configured automatically.

+  * @note   Refer to Reference Manual to ensure the selected channel is

+  *         available in differential mode.

+  *         For example, internal channels (VrefInt, TempSensor, ...) are

+  *         not available in differential mode.

+  * @note   When configuring a channel 'i' in differential mode,

+  *         the channel 'i+1' is not usable separately.

+  * @note   On STM32H7, some channels are internally fixed to single-ended inputs

+  *         configuration:

+  *         - ADC1: Channels 0, 6, 7, 8, 9, 13, 14, 15, 17, and 19

+  *         - ADC2: Channels 0, 6, 7, 8, 9, 13, 14, 15 and 19

+  *         - ADC3: Channels 0, 6, 7, 8, 9, 12, 16, 17, and 19

+  * @note   For ADC channels configured in differential mode, both inputs

+  *         should be biased at (Vref+)/2 +/-200mV.

+  *         (Vref+ is the analog voltage reference)

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be ADC disabled.

+  * @note   One or several values can be selected.

+  *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)

+  * @rmtoll DIFSEL   DIFSEL         LL_ADC_SetChannelSingleDiff

+  * @param  ADCx ADC instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_CHANNEL_1

+  *         @arg @ref LL_ADC_CHANNEL_2

+  *         @arg @ref LL_ADC_CHANNEL_3

+  *         @arg @ref LL_ADC_CHANNEL_4

+  *         @arg @ref LL_ADC_CHANNEL_5

+  *         @arg @ref LL_ADC_CHANNEL_10

+  *         @arg @ref LL_ADC_CHANNEL_11

+  *         @arg @ref LL_ADC_CHANNEL_12

+  *         @arg @ref LL_ADC_CHANNEL_13

+  *         @arg @ref LL_ADC_CHANNEL_14

+  *         @arg @ref LL_ADC_CHANNEL_15

+  *         @arg @ref LL_ADC_CHANNEL_16

+  *         @arg @ref LL_ADC_CHANNEL_17

+  *         @arg @ref LL_ADC_CHANNEL_18

+  *         @arg @ref LL_ADC_CHANNEL_19

+  * @param  SingleDiff This parameter can be a combination of the following values:

+  *         @arg @ref LL_ADC_SINGLE_ENDED

+  *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_SetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SingleDiff)

+{

+  /* Bits of channels in single or differential mode are set only for         */

+  /* differential mode (for single mode, mask of bits allowed to be set is    */

+  /* shifted out of range of bits of channels in single or differential mode. */

+  MODIFY_REG(ADCx->DIFSEL,

+             Channel & ADC_SINGLEDIFF_CHANNEL_MASK,

+             (Channel & ADC_SINGLEDIFF_CHANNEL_MASK) & (ADC_DIFSEL_DIFSEL >> (SingleDiff & ADC_SINGLEDIFF_CHANNEL_SHIFT_MASK)));

+}

+

+/**

+  * @brief  Get mode single-ended or differential input of the selected

+  *         ADC channel.

+  * @note   When configuring a channel 'i' in differential mode,

+  *         the channel 'i+1' is not usable separately.

+  *         Therefore, to ensure a channel is configured in single-ended mode,

+  *         the configuration of channel itself and the channel 'i-1' must be

+  *         read back (to ensure that the selected channel channel has not been

+  *         configured in differential mode by the previous channel).

+  * @note   Refer to Reference Manual to ensure the selected channel is

+  *         available in differential mode.

+  *         For example, internal channels (VrefInt, TempSensor, ...) are

+  *         not available in differential mode.

+  * @note   When configuring a channel 'i' in differential mode,

+  *         the channel 'i+1' is not usable separately.

+  * @note   On STM32H7, some channels are internally fixed to single-ended inputs

+  *         configuration:

+  *         - ADC1: Channels 0, 6, 7, 8, 9, 13, 14, 15, 17, and 19

+  *         - ADC2: Channels 0, 6, 7, 8, 9, 13, 14, 15 and 19

+  *         - ADC3: Channels 0, 6, 7, 8, 9, 12, 16, 17, and 19

+  * @note   One or several values can be selected. In this case, the value

+  *         returned is null if all channels are in single ended-mode.

+  *         Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...)

+  * @rmtoll DIFSEL   DIFSEL         LL_ADC_GetChannelSingleDiff

+  * @param  ADCx ADC instance

+  * @param  Channel This parameter can be a combination of the following values:

+  *         @arg @ref LL_ADC_CHANNEL_1

+  *         @arg @ref LL_ADC_CHANNEL_2

+  *         @arg @ref LL_ADC_CHANNEL_3

+  *         @arg @ref LL_ADC_CHANNEL_4

+  *         @arg @ref LL_ADC_CHANNEL_5

+  *         @arg @ref LL_ADC_CHANNEL_10

+  *         @arg @ref LL_ADC_CHANNEL_11

+  *         @arg @ref LL_ADC_CHANNEL_12

+  *         @arg @ref LL_ADC_CHANNEL_13

+  *         @arg @ref LL_ADC_CHANNEL_14

+  *         @arg @ref LL_ADC_CHANNEL_15

+  *         @arg @ref LL_ADC_CHANNEL_16

+  *         @arg @ref LL_ADC_CHANNEL_17

+  *         @arg @ref LL_ADC_CHANNEL_18

+  *         @arg @ref LL_ADC_CHANNEL_19

+  * @retval 0: channel in single-ended mode, else: channel in differential mode

+  */

+__STATIC_INLINE uint32_t LL_ADC_GetChannelSingleDiff(ADC_TypeDef *ADCx, uint32_t Channel)

+{

+  return (uint32_t)(READ_BIT(ADCx->DIFSEL, (Channel & ADC_SINGLEDIFF_CHANNEL_MASK)));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog

+  * @{

+  */

+

+/**

+  * @brief  Set ADC analog watchdog monitored channels:

+  *         a single channel, multiple channels or all channels,

+  *         on ADC groups regular and-or injected.

+  * @note   Once monitored channels are selected, analog watchdog

+  *         is enabled.

+  * @note   In case of need to define a single channel to monitor

+  *         with analog watchdog from sequencer channel definition,

+  *         use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP().

+  * @note   On this STM32 serie, there are 2 kinds of analog watchdog

+  *         instance:

+  *         - AWD standard (instance AWD1):

+  *           - channels monitored: can monitor 1 channel or all channels.

+  *           - groups monitored: ADC groups regular and-or injected.

+  *           - resolution: resolution is not limited (corresponds to

+  *             ADC resolution configured).

+  *         - AWD flexible (instances AWD2, AWD3):

+  *           - channels monitored: flexible on channels monitored, selection is

+  *             channel wise, from from 1 to all channels.

+  *             Specificity of this analog watchdog: Multiple channels can

+  *             be selected. For example:

+  *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)

+  *           - groups monitored: not selection possible (monitoring on both

+  *             groups regular and injected).

+  *             Channels selected are monitored on groups regular and injected:

+  *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters

+  *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)

+  *           - resolution: resolution is limited to 8 bits: if ADC resolution is

+  *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits

+  *             the 2 LSB are ignored.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be disabled or enabled without conversion on going

+  *         on either groups regular or injected.

+  * @rmtoll CFGR     AWD1CH         LL_ADC_SetAnalogWDMonitChannels\n

+  *         CFGR     AWD1SGL        LL_ADC_SetAnalogWDMonitChannels\n

+  *         CFGR     AWD1EN         LL_ADC_SetAnalogWDMonitChannels\n

+  *         CFGR     JAWD1EN        LL_ADC_SetAnalogWDMonitChannels\n

+  *         AWD2CR   AWD2CH         LL_ADC_SetAnalogWDMonitChannels\n

+  *         AWD3CR   AWD3CH         LL_ADC_SetAnalogWDMonitChannels

+  * @param  ADCx ADC instance

+  * @param  AWDy This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_AWD1

+  *         @arg @ref LL_ADC_AWD2

+  *         @arg @ref LL_ADC_AWD3

+  * @param  AWDChannelGroup This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_AWD_DISABLE

+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)

+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)

+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_19_INJ          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG          (0)(1)

+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_INJ          (0)(1)

+  *         @arg @ref LL_ADC_AWD_CH_VREFINT_REG_INJ         (1)

+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG       (0)(1)

+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_INJ       (0)(1)

+  *         @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ      (1)

+  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG             (0)(1)

+  *         @arg @ref LL_ADC_AWD_CH_VBAT_INJ             (0)(1)

+  *         @arg @ref LL_ADC_AWD_CH_VBAT_REG_INJ            (1)

+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG     (0)(2)

+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_INJ     (0)(2)

+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH1_ADC2_REG_INJ    (2)

+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG     (0)(2)

+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_INJ     (0)(2)

+  *         @arg @ref LL_ADC_AWD_CH_DAC1CH2_ADC2_REG_INJ    (2)

+  *

+  *         (0) On STM32H7, parameter available only on analog watchdog number: AWD1.\n

+  *         (1) On STM32H7, parameter available only on ADC instance: ADC3.\n

+  *         (2) On STM32H7, parameter available only on ADC instance: ADC2.

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup)

+{

+  /* Set bits with content of parameter "AWDChannelGroup" with bits position  */

+  /* in register and register position depending on parameter "AWDy".         */

+  /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because      */

+  /* containing other bits reserved for other purpose.                        */

+  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)

+                                                      + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));

+

+  MODIFY_REG(*preg,

+             (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK),

+             AWDChannelGroup & AWDy);

+}

+

+/**

+  * @brief  Get ADC analog watchdog monitored channel.

+  * @note   Usage of the returned channel number:

+  *         - To reinject this channel into another function LL_ADC_xxx:

+  *           the returned channel number is only partly formatted on definition

+  *           of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared

+  *           with parts of literals LL_ADC_CHANNEL_x or using

+  *           helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

+  *           Then the selected literal LL_ADC_CHANNEL_x can be used

+  *           as parameter for another function.

+  *         - To get the channel number in decimal format:

+  *           process the returned value with the helper macro

+  *           @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB().

+  *           Applicable only when the analog watchdog is set to monitor

+  *           one channel.

+  * @note   On this STM32 serie, there are 2 kinds of analog watchdog

+  *         instance:

+  *         - AWD standard (instance AWD1):

+  *           - channels monitored: can monitor 1 channel or all channels.

+  *           - groups monitored: ADC groups regular and-or injected.

+  *           - resolution: resolution is not limited (corresponds to

+  *             ADC resolution configured).

+  *         - AWD flexible (instances AWD2, AWD3):

+  *           - channels monitored: flexible on channels monitored, selection is

+  *             channel wise, from from 1 to all channels.

+  *             Specificity of this analog watchdog: Multiple channels can

+  *             be selected. For example:

+  *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)

+  *           - groups monitored: not selection possible (monitoring on both

+  *             groups regular and injected).

+  *             Channels selected are monitored on groups regular and injected:

+  *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters

+  *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)

+  *           - resolution: resolution is limited to 8 bits: if ADC resolution is

+  *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits

+  *             the 2 LSB are ignored.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be disabled or enabled without conversion on going

+  *         on either groups regular or injected.

+  * @rmtoll CFGR     AWD1CH         LL_ADC_GetAnalogWDMonitChannels\n

+  *         CFGR     AWD1SGL        LL_ADC_GetAnalogWDMonitChannels\n

+  *         CFGR     AWD1EN         LL_ADC_GetAnalogWDMonitChannels\n

+  *         CFGR     JAWD1EN        LL_ADC_GetAnalogWDMonitChannels\n

+  *         AWD2CR   AWD2CH         LL_ADC_GetAnalogWDMonitChannels\n

+  *         AWD3CR   AWD3CH         LL_ADC_GetAnalogWDMonitChannels

+  * @param  ADCx ADC instance

+  * @param  AWDy This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_AWD1

+  *         @arg @ref LL_ADC_AWD2 (1)

+  *         @arg @ref LL_ADC_AWD3 (1)

+  *

+  *         (1) On this AWD number, monitored channel can be retrieved

+  *             if only 1 channel is programmed (or none or all channels).

+  *             This function cannot retrieve monitored channel if

+  *             multiple channels are programmed simultaneously

+  *             by bitfield.

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_ADC_AWD_DISABLE

+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG        (0)

+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_INJ        (0)

+  *         @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_INJ           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_0_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_INJ           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_1_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_INJ           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_2_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_INJ           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_3_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_INJ           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_4_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_INJ           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_5_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_INJ           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_6_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_INJ           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_7_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_INJ           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_8_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_INJ           (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_9_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_INJ          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_10_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_INJ          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_11_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_INJ          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_12_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_INJ          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_13_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_INJ          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_14_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_INJ          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_15_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_INJ          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_16_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_INJ          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_17_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_INJ          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_18_REG_INJ

+  *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_19_INJ          (0)

+  *         @arg @ref LL_ADC_AWD_CHANNEL_19_REG_INJ

+  *

+  *         (0) On STM32H7, parameter available only on analog watchdog number: AWD1.

+  */

+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy)

+{

+  register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR, ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS)

+                                                            + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) * ADC_AWD_CR12_REGOFFSETGAP_VAL));

+

+  register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK);

+

+  /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled       */

+  /* (parameter value LL_ADC_AWD_DISABLE).                                    */

+  /* Else, the selected AWD is enabled and is monitoring a group of channels  */

+  /* or a single channel.                                                     */

+  if (AnalogWDMonitChannels != 0UL)

+  {

+    if (AWDy == LL_ADC_AWD1)

+    {

+      if ((AnalogWDMonitChannels & ADC_CFGR_AWD1SGL) == 0UL)

+      {

+        /* AWD monitoring a group of channels */

+        AnalogWDMonitChannels = ((AnalogWDMonitChannels

+                                  | (ADC_AWD_CR23_CHANNEL_MASK)

+                                 )

+                                 & (~(ADC_CFGR_AWD1CH))

+                                );

+      }

+      else

+      {

+        /* AWD monitoring a single channel */

+        AnalogWDMonitChannels = (AnalogWDMonitChannels

+                                 | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR_AWD1CH_Pos))

+                                );

+      }

+    }

+    else

+    {

+      if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK)

+      {

+        /* AWD monitoring a group of channels */

+        AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK

+                                 | ((ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN))

+                                );

+      }

+      else

+      {

+        /* AWD monitoring a single channel */

+        /* AWD monitoring a group of channels */

+        AnalogWDMonitChannels = (AnalogWDMonitChannels

+                                 | (ADC_CFGR_JAWD1EN | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL)

+                                 | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR_AWD1CH_Pos)

+                                );

+      }

+    }

+  }

+

+  return AnalogWDMonitChannels;

+}

+

+/**

+  * @brief  Set ADC analog watchdog threshold value of threshold

+  *         high or low.

+  * @note   In case of ADC resolution different of 12 bits,

+  *         analog watchdog thresholds data require a specific shift.

+  *         Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION().

+  * @note   On this STM32 serie, there are 2 kinds of analog watchdog

+  *         instance:

+  *         - AWD standard (instance AWD1):

+  *           - channels monitored: can monitor 1 channel or all channels.

+  *           - groups monitored: ADC groups regular and-or injected.

+  *           - resolution: resolution is not limited (corresponds to

+  *             ADC resolution configured).

+  *         - AWD flexible (instances AWD2, AWD3):

+  *           - channels monitored: flexible on channels monitored, selection is

+  *             channel wise, from from 1 to all channels.

+  *             Specificity of this analog watchdog: Multiple channels can

+  *             be selected. For example:

+  *             (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...)

+  *           - groups monitored: not selection possible (monitoring on both

+  *             groups regular and injected).

+  *             Channels selected are monitored on groups regular and injected:

+  *             LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters

+  *             LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ)

+  *           - resolution: resolution is limited to 8 bits: if ADC resolution is

+  *             12 bits the 4 LSB are ignored, if ADC resolution is 10 bits

+  *             the 2 LSB are ignored.

+  * @note   If ADC oversampling is enabled, ADC analog watchdog thresholds are

+  *         impacted: the comparison of analog watchdog thresholds is done

+  *         on oversampling intermediate computation (after ratio, before shift

+  *         application): intermediate register bitfield [32:7]

+  *         (26 most significant bits).

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be disabled or enabled without conversion on going

+  *         on either ADC groups regular or injected.

+  * @rmtoll TR1      HT1            LL_ADC_SetAnalogWDThresholds\n

+  *         TR2      HT2            LL_ADC_SetAnalogWDThresholds\n

+  *         TR3      HT3            LL_ADC_SetAnalogWDThresholds\n

+  *         TR1      LT1            LL_ADC_SetAnalogWDThresholds\n

+  *         TR2      LT2            LL_ADC_SetAnalogWDThresholds\n

+  *         TR3      LT3            LL_ADC_SetAnalogWDThresholds

+  * @param  ADCx ADC instance

+  * @param  AWDy This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_AWD1

+  *         @arg @ref LL_ADC_AWD2

+  *         @arg @ref LL_ADC_AWD3

+  * @param  AWDThresholdsHighLow This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH

+  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW

+  * @param  AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow,

+                                                  uint32_t AWDThresholdValue)

+{

+  /* Set bits with content of parameter "AWDThresholdValue" with bits         */

+  /* position in register and register position depending on parameters       */

+  /* "AWDThresholdsHighLow" and "AWDy".                                       */

+  /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because    */

+  /* containing other bits reserved for other purpose.                        */

+  register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)

+                                                             + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)

+                                                             + (AWDThresholdsHighLow));

+

+  MODIFY_REG(*preg, ADC_LTR_LT, AWDThresholdValue);

+}

+

+/**

+  * @brief  Get ADC analog watchdog threshold value of threshold high,

+  *         threshold low or raw data with ADC thresholds high and low

+  *         concatenated.

+  * @note   In case of ADC resolution different of 12 bits,

+  *         analog watchdog thresholds data require a specific shift.

+  *         Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION().

+  * @rmtoll TR1      HT1            LL_ADC_GetAnalogWDThresholds\n

+  *         TR2      HT2            LL_ADC_GetAnalogWDThresholds\n

+  *         TR3      HT3            LL_ADC_GetAnalogWDThresholds\n

+  *         TR1      LT1            LL_ADC_GetAnalogWDThresholds\n

+  *         TR2      LT2            LL_ADC_GetAnalogWDThresholds\n

+  *         TR3      LT3            LL_ADC_GetAnalogWDThresholds

+  * @param  ADCx ADC instance

+  * @param  AWDy This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_AWD1

+  *         @arg @ref LL_ADC_AWD2

+  *         @arg @ref LL_ADC_AWD3

+  * @param  AWDThresholdsHighLow This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_AWD_THRESHOLD_HIGH

+  *         @arg @ref LL_ADC_AWD_THRESHOLD_LOW

+  * @retval Value between Min_Data=0x000 and Max_Data=0x3FFFFFF

+  */

+__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow)

+{

+  register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->LTR1, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK) >> ADC_AWD_TRX_REGOFFSET_POS) * 2UL)

+                                                                   + ((AWDy & ADC_AWD_TR12_REGOFFSETGAP_MASK) * ADC_AWD_TR12_REGOFFSETGAP_VAL)

+                                                                   + (AWDThresholdsHighLow));

+

+  return (uint32_t)(READ_BIT(*preg, ADC_LTR_LT));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling

+  * @{

+  */

+

+/**

+  * @brief  Set ADC oversampling scope: ADC groups regular and-or injected

+  *         (availability of ADC group injected depends on STM32 families).

+  * @note   If both groups regular and injected are selected,

+  *         specify behavior of ADC group injected interrupting

+  *         group regular: when ADC group injected is triggered,

+  *         the oversampling on ADC group regular is either

+  *         temporary stopped and continued, or resumed from start

+  *         (oversampler buffer reset).

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be disabled or enabled without conversion on going

+  *         on either groups regular or injected.

+  * @rmtoll CFGR2    ROVSE          LL_ADC_SetOverSamplingScope\n

+  *         CFGR2    JOVSE          LL_ADC_SetOverSamplingScope\n

+  *         CFGR2    ROVSM          LL_ADC_SetOverSamplingScope

+  * @param  ADCx ADC instance

+  * @param  OvsScope This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_OVS_DISABLE

+  *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED

+  *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED

+  *         @arg @ref LL_ADC_OVS_GRP_INJECTED

+  *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope)

+{

+  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM, OvsScope);

+}

+

+/**

+  * @brief  Get ADC oversampling scope: ADC groups regular and-or injected

+  *         (availability of ADC group injected depends on STM32 families).

+  * @note   If both groups regular and injected are selected,

+  *         specify behavior of ADC group injected interrupting

+  *         group regular: when ADC group injected is triggered,

+  *         the oversampling on ADC group regular is either

+  *         temporary stopped and continued, or resumed from start

+  *         (oversampler buffer reset).

+  * @rmtoll CFGR2    ROVSE          LL_ADC_GetOverSamplingScope\n

+  *         CFGR2    JOVSE          LL_ADC_GetOverSamplingScope\n

+  *         CFGR2    ROVSM          LL_ADC_GetOverSamplingScope

+  * @param  ADCx ADC instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_ADC_OVS_DISABLE

+  *         @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED

+  *         @arg @ref LL_ADC_OVS_GRP_REGULAR_RESUMED

+  *         @arg @ref LL_ADC_OVS_GRP_INJECTED

+  *         @arg @ref LL_ADC_OVS_GRP_INJ_REG_RESUMED

+  */

+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx)

+{

+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_ROVSE | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSM));

+}

+

+/**

+  * @brief  Set ADC oversampling discontinuous mode (triggered mode)

+  *         on the selected ADC group.

+  * @note   Number of oversampled conversions are done either in:

+  *         - continuous mode (all conversions of oversampling ratio

+  *           are done from 1 trigger)

+  *         - discontinuous mode (each conversion of oversampling ratio

+  *           needs a trigger)

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be disabled or enabled without conversion on going

+  *         on group regular.

+  * @note   On this STM32 serie, oversampling discontinuous mode

+  *         (triggered mode) can be used only when oversampling is

+  *         set on group regular only and in resumed mode.

+  * @rmtoll CFGR2    TROVS          LL_ADC_SetOverSamplingDiscont

+  * @param  ADCx ADC instance

+  * @param  OverSamplingDiscont This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_OVS_REG_CONT

+  *         @arg @ref LL_ADC_OVS_REG_DISCONT

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont)

+{

+  MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TROVS, OverSamplingDiscont);

+}

+

+/**

+  * @brief  Get ADC oversampling discontinuous mode (triggered mode)

+  *         on the selected ADC group.

+  * @note   Number of oversampled conversions are done either in:

+  *         - continuous mode (all conversions of oversampling ratio

+  *           are done from 1 trigger)

+  *         - discontinuous mode (each conversion of oversampling ratio

+  *           needs a trigger)

+  * @rmtoll CFGR2    TROVS          LL_ADC_GetOverSamplingDiscont

+  * @param  ADCx ADC instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_ADC_OVS_REG_CONT

+  *         @arg @ref LL_ADC_OVS_REG_DISCONT

+  */

+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx)

+{

+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TROVS));

+}

+

+/**

+  * @brief  Set ADC oversampling

+  *         (impacting both ADC groups regular and injected)

+  * @note   This function set the 2 items of oversampling configuration:

+  *         - ratio

+  *         - shift

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be disabled or enabled without conversion on going

+  *         on either groups regular or injected.

+  * @rmtoll CFGR2    OVSS           LL_ADC_ConfigOverSamplingRatioShift\n

+  *         CFGR2    OVSR           LL_ADC_ConfigOverSamplingRatioShift

+  * @param  ADCx ADC instance

+  * @param  Ratio This parameter can be in the range from 1 to 1024.

+  * @param  Shift This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_OVS_SHIFT_NONE

+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1

+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2

+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3

+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4

+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5

+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6

+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7

+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8

+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9

+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10

+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift)

+{

+  MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | (((Ratio - 1UL) << ADC_CFGR2_OVSR_Pos))));

+}

+

+/**

+  * @brief  Get ADC oversampling ratio

+  *        (impacting both ADC groups regular and injected)

+  * @rmtoll CFGR2    OVSR           LL_ADC_GetOverSamplingRatio

+  * @param  ADCx ADC instance

+  * @retval Ratio This parameter can be in the from 1 to 1024.

+  */

+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx)

+{

+  return (((uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR))+(1UL << ADC_CFGR2_OVSR_Pos)) >> ADC_CFGR2_OVSR_Pos);

+}

+

+/**

+  * @brief  Get ADC oversampling shift

+  *        (impacting both ADC groups regular and injected)

+  * @rmtoll CFGR2    OVSS           LL_ADC_GetOverSamplingShift

+  * @param  ADCx ADC instance

+  * @retval Shift This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_OVS_SHIFT_NONE

+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1

+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2

+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3

+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4

+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5

+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6

+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7

+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8

+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_9

+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_10

+  *         @arg @ref LL_ADC_OVS_SHIFT_RIGHT_11

+  */

+__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx)

+{

+  return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EF_Configuration_ADC_Multimode Configuration of ADC hierarchical scope: multimode

+  * @{

+  */

+/**

+  * @brief  Set ADC boost mode.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC boost must be configured, without calibration on going, without conversion

+  *         on going on group regular.

+  * @rmtoll CR  BOOST      LL_ADC_SetBoostMode

+  * @param  ADCx ADC instance

+  * @param  BoostMode This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_BOOST_MODE_6MHZ25

+  *         @arg @ref LL_ADC_BOOST_MODE_12MHZ5

+  *         @arg @ref LL_ADC_BOOST_MODE_20MHZ

+  *         @arg @ref LL_ADC_BOOST_MODE_25MHZ

+  *         @arg @ref LL_ADC_BOOST_MODE_50MHZ

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_SetBoostMode(ADC_TypeDef *ADCx, uint32_t BoostMode)

+{

+  if((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Cut 1.x */

+  {

+    MODIFY_REG(ADCx->CR, ADC_CR_BOOST_0, (BoostMode >> 2UL));

+  }

+  else /* Cut 2.x */

+  {

+    MODIFY_REG(ADCx->CR, ADC_CR_BOOST, (BoostMode & ADC_CR_BOOST));

+  }

+}

+

+/**

+  * @brief  Get ADC boost mode.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC boost must be configured, without calibration on going, without conversion

+  *         on going on group regular.

+  * @rmtoll CR  BOOST      LL_ADC_GetBoostMode

+  * @param  ADCx ADC instance

+  * @retval 0: Boost disabled 1: Boost enabled

+  */

+__STATIC_INLINE uint32_t LL_ADC_GetBoostMode(ADC_TypeDef *ADCx)

+{

+  if((DBGMCU->IDCODE & 0x30000000UL) == 0x10000000UL) /* Cut 1.x */

+  {

+    return (uint32_t)READ_BIT(ADCx->CR, ADC_CR_BOOST_0);

+  }

+  else /* Cut 2.x */

+  {

+    return ((READ_BIT(ADCx->CR, ADC_CR_BOOST) == (ADC_CR_BOOST)) ? 1UL : 0UL);

+  }

+}

+

+/**

+  * @brief  Set ADC multimode configuration to operate in independent mode

+  *         or multimode (for devices with several ADC instances).

+  * @note   If multimode configuration: the selected ADC instance is

+  *         either master or slave depending on hardware.

+  *         Refer to reference manual.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         All ADC instances of the ADC common group must be disabled.

+  *         This check can be done with function @ref LL_ADC_IsEnabled() for each

+  *         ADC instance or by using helper macro

+  *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().

+  * @rmtoll CCR      DUAL           LL_ADC_SetMultimode

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @param  Multimode This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_MULTI_INDEPENDENT

+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT

+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL

+  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT

+  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN

+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM

+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT

+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_SetMultimode(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t Multimode)

+{

+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DUAL, Multimode);

+}

+

+/**

+  * @brief  Get ADC multimode configuration to operate in independent mode

+  *         or multimode (for devices with several ADC instances).

+  * @note   If multimode configuration: the selected ADC instance is

+  *         either master or slave depending on hardware.

+  *         Refer to reference manual.

+  * @rmtoll CCR      DUAL           LL_ADC_GetMultimode

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_ADC_MULTI_INDEPENDENT

+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIMULT

+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INTERL

+  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_SIMULT

+  *         @arg @ref LL_ADC_MULTI_DUAL_INJ_ALTERN

+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM

+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT

+  *         @arg @ref LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM

+  */

+__STATIC_INLINE uint32_t LL_ADC_GetMultimode(ADC_Common_TypeDef *ADCxy_COMMON)

+{

+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DUAL));

+}

+

+/**

+  * @brief  Set ADC multimode conversion data transfer: no transfer

+  *         or transfer by DMA.

+  * @note   If ADC multimode transfer by DMA is not selected:

+  *         each ADC uses its own DMA channel, with its individual

+  *         DMA transfer settings.

+  *         If ADC multimode transfer by DMA is selected:

+  *         One DMA channel is used for both ADC (DMA of ADC master)

+  *         Specifies the DMA requests mode:

+  *         - Limited mode (One shot mode): DMA transfer requests are stopped

+  *           when number of DMA data transfers (number of

+  *           ADC conversions) is reached.

+  *           This ADC mode is intended to be used with DMA mode non-circular.

+  *         - Unlimited mode: DMA transfer requests are unlimited,

+  *           whatever number of DMA data transfers (number of

+  *           ADC conversions).

+  *           This ADC mode is intended to be used with DMA mode circular.

+  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to

+  *         mode non-circular:

+  *         when DMA transfers size will be reached, DMA will stop transfers of

+  *         ADC conversions data ADC will raise an overrun error

+  *         (overrun flag and interruption if enabled).

+  * @note   How to retrieve multimode conversion data:

+  *         Whatever multimode transfer by DMA setting: using function

+  *         @ref LL_ADC_REG_ReadMultiConversionData32().

+  *         If ADC multimode transfer by DMA is selected: conversion data

+  *         is a raw data with ADC master and slave concatenated.

+  *         A macro is available to get the conversion data of

+  *         ADC master or ADC slave: see helper macro

+  *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         All ADC instances of the ADC common group must be disabled

+  *         or enabled without conversion on going on group regular.

+  * @rmtoll CCR      DAMDF          LL_ADC_GetMultiDMATransfer\n

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @param  MultiDMATransfer This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC

+  *         @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_10B

+  *         @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_SetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiDMATransfer)

+{

+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DAMDF, MultiDMATransfer);

+}

+

+/**

+  * @brief  Get ADC multimode conversion data transfer: no transfer

+  *         or transfer by DMA.

+  * @note   If ADC multimode transfer by DMA is not selected:

+  *         each ADC uses its own DMA channel, with its individual

+  *         DMA transfer settings.

+  *         If ADC multimode transfer by DMA is selected:

+  *         One DMA channel is used for both ADC (DMA of ADC master)

+  *         Specifies the DMA requests mode:

+  *         - Limited mode (One shot mode): DMA transfer requests are stopped

+  *           when number of DMA data transfers (number of

+  *           ADC conversions) is reached.

+  *           This ADC mode is intended to be used with DMA mode non-circular.

+  *         - Unlimited mode: DMA transfer requests are unlimited,

+  *           whatever number of DMA data transfers (number of

+  *           ADC conversions).

+  *           This ADC mode is intended to be used with DMA mode circular.

+  * @note   If ADC DMA requests mode is set to unlimited and DMA is set to

+  *         mode non-circular:

+  *         when DMA transfers size will be reached, DMA will stop transfers of

+  *         ADC conversions data ADC will raise an overrun error

+  *         (overrun flag and interruption if enabled).

+  * @note   How to retrieve multimode conversion data:

+  *         Whatever multimode transfer by DMA setting: using function

+  *         @ref LL_ADC_REG_ReadMultiConversionData32().

+  *         If ADC multimode transfer by DMA is selected: conversion data

+  *         is a raw data with ADC master and slave concatenated.

+  *         A macro is available to get the conversion data of

+  *         ADC master or ADC slave: see helper macro

+  *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().

+  * @rmtoll CCR      DAMDF          LL_ADC_GetMultiDMATransfer\n

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_ADC_MULTI_REG_DMA_EACH_ADC

+  *         @arg @ref LL_ADC_MULTI_REG_DMA_RES_32_10B

+  *         @arg @ref LL_ADC_MULTI_REG_DMA_RES_8B

+  */

+__STATIC_INLINE uint32_t LL_ADC_GetMultiDMATransfer(ADC_Common_TypeDef *ADCxy_COMMON)

+{

+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DAMDF));

+}

+

+/**

+  * @brief  Set ADC multimode delay between 2 sampling phases.

+  * @note   The sampling delay range depends on ADC resolution:

+  *         - ADC resolution 12 bits can have maximum delay of 12 cycles.

+  *         - ADC resolution 10 bits can have maximum delay of 10 cycles.

+  *         - ADC resolution  8 bits can have maximum delay of  8 cycles.

+  *         - ADC resolution  6 bits can have maximum delay of  6 cycles.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         All ADC instances of the ADC common group must be disabled.

+  *         This check can be done with function @ref LL_ADC_IsEnabled() for each

+  *         ADC instance or by using helper macro helper macro

+  *         @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE().

+  * @rmtoll CCR      DELAY          LL_ADC_SetMultiTwoSamplingDelay

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @param  MultiTwoSamplingDelay This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5

+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5

+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5

+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 (1)

+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS

+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 (2)

+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS

+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (3)

+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 (4)

+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS

+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 (5)

+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (6)

+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (7)

+  *

+  *         (1) Parameter available only if ADC resolution is 16, 14, 12 or 10 bits.

+  *         (2) Parameter available only if ADC resolution is 16, 14 or 12  bits.

+  *         (3) Parameter available only if ADC resolution is 10 or 8 bits.

+  *         (4) Parameter available only if ADC resolution is 16 or 14 bits.

+  *         (5) Parameter available only if ADC resolution is 16 bits.

+  *         (6) Parameter available only if ADC resolution is 12 bits.

+  *         (7) Parameter available only if ADC resolution is 16 or 14 bits.

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_SetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t MultiTwoSamplingDelay)

+{

+  MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_DELAY, MultiTwoSamplingDelay);

+}

+

+/**

+  * @brief  Get ADC multimode delay between 2 sampling phases.

+  * @rmtoll CCR      DELAY          LL_ADC_GetMultiTwoSamplingDelay

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE_5

+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES_5

+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES_5

+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5 (1)

+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES_5_8_BITS

+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5 (2)

+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES_5_10_BITS

+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES  (3)

+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5 (4)

+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES_5_12_BITS

+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES_5 (5)

+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES  (6)

+  *         @arg @ref LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES  (7)

+  *

+  *         (1) Parameter available only if ADC resolution is 16, 14, 12 or 10 bits.

+  *         (2) Parameter available only if ADC resolution is 16, 14 or 12  bits.

+  *         (3) Parameter available only if ADC resolution is 10 or 8 bits.

+  *         (4) Parameter available only if ADC resolution is 16 or 14 bits.

+  *         (5) Parameter available only if ADC resolution is 16 bits.

+  *         (6) Parameter available only if ADC resolution is 12 bits.

+  *         (7) Parameter available only if ADC resolution is 16 or 14 bits.

+  */

+__STATIC_INLINE uint32_t LL_ADC_GetMultiTwoSamplingDelay(ADC_Common_TypeDef *ADCxy_COMMON)

+{

+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_DELAY));

+}

+

+/**

+  * @}

+  */

+/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance

+  * @{

+  */

+

+/**

+  * @brief  Put ADC instance in deep power down state.

+  * @note   In case of ADC calibration necessary: When ADC is in deep-power-down

+  *         state, the internal analog calibration is lost. After exiting from

+  *         deep power down, calibration must be relaunched or calibration factor

+  *         (preliminarily saved) must be set back into calibration register.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be ADC disabled.

+  * @rmtoll CR       DEEPPWD        LL_ADC_EnableDeepPowerDown

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_EnableDeepPowerDown(ADC_TypeDef *ADCx)

+{

+  /* Note: Write register with some additional bits forced to state reset     */

+  /*       instead of modifying only the selected bit for this function,      */

+  /*       to not interfere with bits with HW property "rs".                  */

+  MODIFY_REG(ADCx->CR,

+             ADC_CR_BITS_PROPERTY_RS,

+             ADC_CR_DEEPPWD);

+}

+

+/**

+  * @brief  Disable ADC deep power down mode.

+  * @note   In case of ADC calibration necessary: When ADC is in deep-power-down

+  *         state, the internal analog calibration is lost. After exiting from

+  *         deep power down, calibration must be relaunched or calibration factor

+  *         (preliminarily saved) must be set back into calibration register.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be ADC disabled.

+  * @rmtoll CR       DEEPPWD        LL_ADC_DisableDeepPowerDown

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_DisableDeepPowerDown(ADC_TypeDef *ADCx)

+{

+  /* Note: Write register with some additional bits forced to state reset     */

+  /*       instead of modifying only the selected bit for this function,      */

+  /*       to not interfere with bits with HW property "rs".                  */

+  CLEAR_BIT(ADCx->CR, (ADC_CR_DEEPPWD | ADC_CR_BITS_PROPERTY_RS));

+}

+

+/**

+  * @brief  Get the selected ADC instance deep power down state.

+  * @rmtoll CR       DEEPPWD        LL_ADC_IsDeepPowerDownEnabled

+  * @param  ADCx ADC instance

+  * @retval 0: deep power down is disabled, 1: deep power down is enabled.

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsDeepPowerDownEnabled(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->CR, ADC_CR_DEEPPWD) == (ADC_CR_DEEPPWD)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable ADC instance internal voltage regulator.

+  * @note   On this STM32 serie, after ADC internal voltage regulator enable,

+  *         a delay for ADC internal voltage regulator stabilization

+  *         is required before performing a ADC calibration or ADC enable.

+  *         Refer to device datasheet, parameter tADCVREG_STUP.

+  *         Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be ADC disabled.

+  * @rmtoll CR       ADVREGEN       LL_ADC_EnableInternalRegulator

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx)

+{

+  /* Note: Write register with some additional bits forced to state reset     */

+  /*       instead of modifying only the selected bit for this function,      */

+  /*       to not interfere with bits with HW property "rs".                  */

+  MODIFY_REG(ADCx->CR,

+             ADC_CR_BITS_PROPERTY_RS,

+             ADC_CR_ADVREGEN);

+}

+

+/**

+  * @brief  Disable ADC internal voltage regulator.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be ADC disabled.

+  * @rmtoll CR       ADVREGEN       LL_ADC_DisableInternalRegulator

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx)

+{

+  CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS));

+}

+

+/**

+  * @brief  Get the selected ADC instance internal voltage regulator state.

+  * @rmtoll CR       ADVREGEN       LL_ADC_IsInternalRegulatorEnabled

+  * @param  ADCx ADC instance

+  * @retval 0: internal regulator is disabled, 1: internal regulator is enabled.

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the selected ADC instance.

+  * @note   On this STM32 serie, after ADC enable, a delay for

+  *         ADC internal analog stabilization is required before performing a

+  *         ADC conversion start.

+  *         Refer to device datasheet, parameter tSTAB.

+  * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC

+  *         is enabled and when conversion clock is active.

+  *         (not only core clock: this ADC has a dual clock domain)

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be ADC disabled and ADC internal voltage regulator enabled.

+  * @rmtoll CR       ADEN           LL_ADC_Enable

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx)

+{

+  /* Note: Write register with some additional bits forced to state reset     */

+  /*       instead of modifying only the selected bit for this function,      */

+  /*       to not interfere with bits with HW property "rs".                  */

+  MODIFY_REG(ADCx->CR,

+             ADC_CR_BITS_PROPERTY_RS,

+             ADC_CR_ADEN);

+}

+

+/**

+  * @brief  Disable the selected ADC instance.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be not disabled. Must be enabled without conversion on going

+  *         on either groups regular or injected.

+  * @rmtoll CR       ADDIS          LL_ADC_Disable

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx)

+{

+  /* Note: Write register with some additional bits forced to state reset     */

+  /*       instead of modifying only the selected bit for this function,      */

+  /*       to not interfere with bits with HW property "rs".                  */

+  MODIFY_REG(ADCx->CR,

+             ADC_CR_BITS_PROPERTY_RS,

+             ADC_CR_ADDIS);

+}

+

+/**

+  * @brief  Get the selected ADC instance enable state.

+  * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC

+  *         is enabled and when conversion clock is active.

+  *         (not only core clock: this ADC has a dual clock domain)

+  * @rmtoll CR       ADEN           LL_ADC_IsEnabled

+  * @param  ADCx ADC instance

+  * @retval 0: ADC is disabled, 1: ADC is enabled.

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get the selected ADC instance disable state.

+  * @rmtoll CR       ADDIS          LL_ADC_IsDisableOngoing

+  * @param  ADCx ADC instance

+  * @retval 0: no ADC disable command on going.

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Start ADC calibration in the mode single-ended

+  *         or differential (for devices with differential mode available).

+  * @note   On this STM32 serie, a minimum number of ADC clock cycles

+  *         are required between ADC end of calibration and ADC enable.

+  *         Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES.

+  * @note   Calibration duration:

+  *         - Calibration of offset: 520 ADC clock cycles

+  *         - Calibration of linearity: 131072 ADC clock cycles

+  * @note   For devices with differential mode available:

+  *         Calibration of offset is specific to each of

+  *         single-ended and differential modes

+  *         (calibration run must be performed for each of these

+  *         differential modes, if used afterwards and if the application

+  *         requires their calibration).

+  *         Calibration of linearity is common to both

+  *         single-ended and differential modes

+  *         (calibration run can be performed only once).

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be ADC disabled.

+  * @rmtoll CR       ADCAL          LL_ADC_StartCalibration\n

+  *         CR       ADCALDIF       LL_ADC_StartCalibration\n

+  *         CR       ADCALLIN       LL_ADC_StartCalibration

+  * @param  ADCx ADC instance

+  * @param  CalibrationMode This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_CALIB_OFFSET

+  *         @arg @ref LL_ADC_CALIB_OFFSET_LINEARITY

+  * @param  SingleDiff This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_SINGLE_ENDED

+  *         @arg @ref LL_ADC_DIFFERENTIAL_ENDED

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx, uint32_t CalibrationMode, uint32_t SingleDiff)

+{

+  /* Note: Write register with some additional bits forced to state reset     */

+  /*       instead of modifying only the selected bit for this function,      */

+  /*       to not interfere with bits with HW property "rs".                  */

+  MODIFY_REG(ADCx->CR,

+             ADC_CR_ADCALLIN | ADC_CR_ADCALDIF | ADC_CR_BITS_PROPERTY_RS,

+             ADC_CR_ADCAL | (CalibrationMode & ADC_CALIB_MODE_MASK) | (SingleDiff & ADC_SINGLEDIFF_CALIB_START_MASK));

+}

+

+/**

+  * @brief  Get ADC calibration state.

+  * @rmtoll CR       ADCAL          LL_ADC_IsCalibrationOnGoing

+  * @param  ADCx ADC instance

+  * @retval 0: calibration complete, 1: calibration in progress.

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular

+  * @{

+  */

+

+/**

+  * @brief  Start ADC group regular conversion.

+  * @note   On this STM32 serie, this function is relevant for both

+  *         internal trigger (SW start) and external trigger:

+  *         - If ADC trigger has been set to software start, ADC conversion

+  *           starts immediately.

+  *         - If ADC trigger has been set to external trigger, ADC conversion

+  *           will start at next trigger event (on the selected trigger edge)

+  *           following the ADC start conversion command.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be enabled without conversion on going on group regular,

+  *         without conversion stop command on going on group regular,

+  *         without ADC disable command on going.

+  * @rmtoll CR       ADSTART        LL_ADC_REG_StartConversion

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx)

+{

+  /* Note: Write register with some additional bits forced to state reset     */

+  /*       instead of modifying only the selected bit for this function,      */

+  /*       to not interfere with bits with HW property "rs".                  */

+  MODIFY_REG(ADCx->CR,

+             ADC_CR_BITS_PROPERTY_RS,

+             ADC_CR_ADSTART);

+}

+

+/**

+  * @brief  Stop ADC group regular conversion.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be enabled with conversion on going on group regular,

+  *         without ADC disable command on going.

+  * @rmtoll CR       ADSTP          LL_ADC_REG_StopConversion

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx)

+{

+  /* Note: Write register with some additional bits forced to state reset     */

+  /*       instead of modifying only the selected bit for this function,      */

+  /*       to not interfere with bits with HW property "rs".                  */

+  MODIFY_REG(ADCx->CR,

+             ADC_CR_BITS_PROPERTY_RS,

+             ADC_CR_ADSTP);

+}

+

+/**

+  * @brief  Get ADC group regular conversion state.

+  * @rmtoll CR       ADSTART        LL_ADC_REG_IsConversionOngoing

+  * @param  ADCx ADC instance

+  * @retval 0: no conversion is on going on ADC group regular.

+  */

+__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get ADC group regular command of conversion stop state

+  * @rmtoll CR       ADSTP          LL_ADC_REG_IsStopConversionOngoing

+  * @param  ADCx ADC instance

+  * @retval 0: no command of conversion stop is on going on ADC group regular.

+  */

+__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get ADC group regular conversion data, range fit for

+  *         all ADC configurations: all ADC resolutions and

+  *         all oversampling increased data width (for devices

+  *         with feature oversampling).

+  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData32

+  * @param  ADCx ADC instance

+  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

+  */

+__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx)

+{

+  return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));

+}

+

+/**

+  * @brief  Get ADC group regular conversion data, range fit for

+  *         ADC resolution 16 bits.

+  * @note   For devices with feature oversampling: Oversampling

+  *         can increase data width, function for extended range

+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.

+  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData16

+  * @param  ADCx ADC instance

+  * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF

+  */

+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData16(ADC_TypeDef *ADCx)

+{

+  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));

+}

+

+/**

+  * @brief  Get ADC group regular conversion data, range fit for

+  *         ADC resolution 14 bits.

+  * @note   For devices with feature oversampling: Oversampling

+  *         can increase data width, function for extended range

+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.

+  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData14

+  * @param  ADCx ADC instance

+  * @retval Value between Min_Data=0x00 and Max_Data=0x3FF

+  */

+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData14(ADC_TypeDef *ADCx)

+{

+  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));

+}

+

+/**

+  * @brief  Get ADC group regular conversion data, range fit for

+  *         ADC resolution 12 bits.

+  * @note   For devices with feature oversampling: Oversampling

+  *         can increase data width, function for extended range

+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.

+  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData12

+  * @param  ADCx ADC instance

+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF

+  */

+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx)

+{

+  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));

+}

+

+/**

+  * @brief  Get ADC group regular conversion data, range fit for

+  *         ADC resolution 10 bits.

+  * @note   For devices with feature oversampling: Oversampling

+  *         can increase data width, function for extended range

+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.

+  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData10

+  * @param  ADCx ADC instance

+  * @retval Value between Min_Data=0x000 and Max_Data=0x3FF

+  */

+__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx)

+{

+  return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));

+}

+

+/**

+  * @brief  Get ADC group regular conversion data, range fit for

+  *         ADC resolution 8 bits.

+  * @note   For devices with feature oversampling: Oversampling

+  *         can increase data width, function for extended range

+  *         may be needed: @ref LL_ADC_REG_ReadConversionData32.

+  * @rmtoll DR       RDATA          LL_ADC_REG_ReadConversionData8

+  * @param  ADCx ADC instance

+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF

+  */

+__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx)

+{

+  return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_RDATA));

+}

+/**

+  * @brief  Get ADC multimode conversion data of ADC master, ADC slave

+  *         or raw data with ADC master and slave concatenated.

+  * @note   If raw data with ADC master and slave concatenated is retrieved,

+  *         a macro is available to get the conversion data of

+  *         ADC master or ADC slave: see helper macro

+  *         @ref __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE().

+  *         (however this macro is mainly intended for multimode

+  *         transfer by DMA, because this function can do the same

+  *         by getting multimode conversion data of ADC master or ADC slave

+  *         separately).

+  * @rmtoll CDR      RDATA_MST      LL_ADC_REG_ReadMultiConversionData32\n

+  *         CDR      RDATA_SLV      LL_ADC_REG_ReadMultiConversionData32

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @param  ConversionData This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_MULTI_MASTER

+  *         @arg @ref LL_ADC_MULTI_SLAVE

+  *         @arg @ref LL_ADC_MULTI_MASTER_SLAVE

+  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

+  */

+__STATIC_INLINE uint32_t LL_ADC_REG_ReadMultiConversionData32(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t ConversionData)

+{

+  return (uint32_t)(READ_BIT(ADCxy_COMMON->CDR,

+                             ConversionData)

+                    >> (POSITION_VAL(ConversionData) & 0x1FUL)

+                   );

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EF_Operation_ADC_Group_Injected Operation on ADC hierarchical scope: group injected

+  * @{

+  */

+

+/**

+  * @brief  Start ADC group injected conversion.

+  * @note   On this STM32 serie, this function is relevant for both

+  *         internal trigger (SW start) and external trigger:

+  *         - If ADC trigger has been set to software start, ADC conversion

+  *           starts immediately.

+  *         - If ADC trigger has been set to external trigger, ADC conversion

+  *           will start at next trigger event (on the selected trigger edge)

+  *           following the ADC start conversion command.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be enabled without conversion on going on group injected,

+  *         without conversion stop command on going on group injected,

+  *         without ADC disable command on going.

+  * @rmtoll CR       JADSTART       LL_ADC_INJ_StartConversion

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_INJ_StartConversion(ADC_TypeDef *ADCx)

+{

+  /* Note: Write register with some additional bits forced to state reset     */

+  /*       instead of modifying only the selected bit for this function,      */

+  /*       to not interfere with bits with HW property "rs".                  */

+  MODIFY_REG(ADCx->CR,

+             ADC_CR_BITS_PROPERTY_RS,

+             ADC_CR_JADSTART);

+}

+

+/**

+  * @brief  Stop ADC group injected conversion.

+  * @note   On this STM32 serie, setting of this feature is conditioned to

+  *         ADC state:

+  *         ADC must be enabled with conversion on going on group injected,

+  *         without ADC disable command on going.

+  * @rmtoll CR       JADSTP         LL_ADC_INJ_StopConversion

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_INJ_StopConversion(ADC_TypeDef *ADCx)

+{

+  /* Note: Write register with some additional bits forced to state reset     */

+  /*       instead of modifying only the selected bit for this function,      */

+  /*       to not interfere with bits with HW property "rs".                  */

+  MODIFY_REG(ADCx->CR,

+             ADC_CR_BITS_PROPERTY_RS,

+             ADC_CR_JADSTP);

+}

+

+/**

+  * @brief  Get ADC group injected conversion state.

+  * @rmtoll CR       JADSTART       LL_ADC_INJ_IsConversionOngoing

+  * @param  ADCx ADC instance

+  * @retval 0: no conversion is on going on ADC group injected.

+  */

+__STATIC_INLINE uint32_t LL_ADC_INJ_IsConversionOngoing(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->CR, ADC_CR_JADSTART) == (ADC_CR_JADSTART)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get ADC group injected command of conversion stop state

+  * @rmtoll CR       JADSTP         LL_ADC_INJ_IsStopConversionOngoing

+  * @param  ADCx ADC instance

+  * @retval 0: no command of conversion stop is on going on ADC group injected.

+  */

+__STATIC_INLINE uint32_t LL_ADC_INJ_IsStopConversionOngoing(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->CR, ADC_CR_JADSTP) == (ADC_CR_JADSTP)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get ADC group injected conversion data, range fit for

+  *         all ADC configurations: all ADC resolutions and

+  *         all oversampling increased data width (for devices

+  *         with feature oversampling).

+  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData32\n

+  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData32\n

+  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData32\n

+  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData32

+  * @param  ADCx ADC instance

+  * @param  Rank This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_INJ_RANK_1

+  *         @arg @ref LL_ADC_INJ_RANK_2

+  *         @arg @ref LL_ADC_INJ_RANK_3

+  *         @arg @ref LL_ADC_INJ_RANK_4

+  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

+  */

+__STATIC_INLINE uint32_t LL_ADC_INJ_ReadConversionData32(ADC_TypeDef *ADCx, uint32_t Rank)

+{

+  register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));

+

+  return (uint32_t)(READ_BIT(*preg,

+                             ADC_JDR1_JDATA)

+                   );

+}

+

+/**

+  * @brief  Get ADC group injected conversion data, range fit for

+  *         ADC resolution 16 bits.

+  * @note   For devices with feature oversampling: Oversampling

+  *         can increase data width, function for extended range

+  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.

+  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData16\n

+  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData16\n

+  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData16\n

+  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData16

+  * @param  ADCx ADC instance

+  * @param  Rank This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_INJ_RANK_1

+  *         @arg @ref LL_ADC_INJ_RANK_2

+  *         @arg @ref LL_ADC_INJ_RANK_3

+  *         @arg @ref LL_ADC_INJ_RANK_4

+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFFF

+  */

+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData16(ADC_TypeDef *ADCx, uint32_t Rank)

+{

+  register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));

+

+  return (uint16_t)(READ_BIT(*preg,

+                             ADC_JDR1_JDATA)

+                   );

+}

+

+/**

+  * @brief  Get ADC group injected conversion data, range fit for

+  *         ADC resolution 14 bits.

+  * @note   For devices with feature oversampling: Oversampling

+  *         can increase data width, function for extended range

+  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.

+  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData14\n

+  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData14\n

+  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData14\n

+  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData14

+  * @param  ADCx ADC instance

+  * @param  Rank This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_INJ_RANK_1

+  *         @arg @ref LL_ADC_INJ_RANK_2

+  *         @arg @ref LL_ADC_INJ_RANK_3

+  *         @arg @ref LL_ADC_INJ_RANK_4

+  * @retval Value between Min_Data=0x000 and Max_Data=0x3FFF

+  */

+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData14(ADC_TypeDef *ADCx, uint32_t Rank)

+{

+  register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));

+

+  return (uint16_t)(READ_BIT(*preg,

+                             ADC_JDR1_JDATA)

+                   );

+}

+

+/**

+  * @brief  Get ADC group injected conversion data, range fit for

+  *         ADC resolution 12 bits.

+  * @note   For devices with feature oversampling: Oversampling

+  *         can increase data width, function for extended range

+  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.

+  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData12\n

+  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData12\n

+  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData12\n

+  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData12

+  * @param  ADCx ADC instance

+  * @param  Rank This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_INJ_RANK_1

+  *         @arg @ref LL_ADC_INJ_RANK_2

+  *         @arg @ref LL_ADC_INJ_RANK_3

+  *         @arg @ref LL_ADC_INJ_RANK_4

+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF

+  */

+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData12(ADC_TypeDef *ADCx, uint32_t Rank)

+{

+  register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));

+

+  return (uint16_t)(READ_BIT(*preg,

+                             ADC_JDR1_JDATA)

+                   );

+}

+

+/**

+  * @brief  Get ADC group injected conversion data, range fit for

+  *         ADC resolution 10 bits.

+  * @note   For devices with feature oversampling: Oversampling

+  *         can increase data width, function for extended range

+  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.

+  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData10\n

+  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData10\n

+  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData10\n

+  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData10

+  * @param  ADCx ADC instance

+  * @param  Rank This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_INJ_RANK_1

+  *         @arg @ref LL_ADC_INJ_RANK_2

+  *         @arg @ref LL_ADC_INJ_RANK_3

+  *         @arg @ref LL_ADC_INJ_RANK_4

+  * @retval Value between Min_Data=0x000 and Max_Data=0x3FF

+  */

+__STATIC_INLINE uint16_t LL_ADC_INJ_ReadConversionData10(ADC_TypeDef *ADCx, uint32_t Rank)

+{

+  register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));

+

+  return (uint16_t)(READ_BIT(*preg,

+                             ADC_JDR1_JDATA)

+                   );

+}

+

+/**

+  * @brief  Get ADC group injected conversion data, range fit for

+  *         ADC resolution 8 bits.

+  * @note   For devices with feature oversampling: Oversampling

+  *         can increase data width, function for extended range

+  *         may be needed: @ref LL_ADC_INJ_ReadConversionData32.

+  * @rmtoll JDR1     JDATA          LL_ADC_INJ_ReadConversionData8\n

+  *         JDR2     JDATA          LL_ADC_INJ_ReadConversionData8\n

+  *         JDR3     JDATA          LL_ADC_INJ_ReadConversionData8\n

+  *         JDR4     JDATA          LL_ADC_INJ_ReadConversionData8

+  * @param  ADCx ADC instance

+  * @param  Rank This parameter can be one of the following values:

+  *         @arg @ref LL_ADC_INJ_RANK_1

+  *         @arg @ref LL_ADC_INJ_RANK_2

+  *         @arg @ref LL_ADC_INJ_RANK_3

+  *         @arg @ref LL_ADC_INJ_RANK_4

+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF

+  */

+__STATIC_INLINE uint8_t LL_ADC_INJ_ReadConversionData8(ADC_TypeDef *ADCx, uint32_t Rank)

+{

+  register const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->JDR1, ((Rank & ADC_INJ_JDRX_REGOFFSET_MASK) >> ADC_JDRX_REGOFFSET_POS));

+

+  return (uint8_t)(READ_BIT(*preg,

+                            ADC_JDR1_JDATA)

+                  );

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management

+  * @{

+  */

+

+/**

+  * @brief  Get flag ADC ready.

+  * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC

+  *         is enabled and when conversion clock is active.

+  *         (not only core clock: this ADC has a dual clock domain)

+  * @rmtoll ISR      ADRDY          LL_ADC_IsActiveFlag_ADRDY

+  * @param  ADCx ADC instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get flag ADC group regular end of unitary conversion.

+  * @rmtoll ISR      EOC            LL_ADC_IsActiveFlag_EOC

+  * @param  ADCx ADC instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get flag ADC group regular end of sequence conversions.

+  * @rmtoll ISR      EOS            LL_ADC_IsActiveFlag_EOS

+  * @param  ADCx ADC instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get flag ADC group regular overrun.

+  * @rmtoll ISR      OVR            LL_ADC_IsActiveFlag_OVR

+  * @param  ADCx ADC instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get flag ADC group regular end of sampling phase.

+  * @rmtoll ISR      EOSMP          LL_ADC_IsActiveFlag_EOSMP

+  * @param  ADCx ADC instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get flag ADC group injected end of unitary conversion.

+  * @rmtoll ISR      JEOC           LL_ADC_IsActiveFlag_JEOC

+  * @param  ADCx ADC instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOC(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOC) == (LL_ADC_FLAG_JEOC)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get flag ADC group injected end of sequence conversions.

+  * @rmtoll ISR      JEOS           LL_ADC_IsActiveFlag_JEOS

+  * @param  ADCx ADC instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JEOS(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JEOS) == (LL_ADC_FLAG_JEOS)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get flag ADC group injected contexts queue overflow.

+  * @rmtoll ISR      JQOVF          LL_ADC_IsActiveFlag_JQOVF

+  * @param  ADCx ADC instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_JQOVF(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF) == (LL_ADC_FLAG_JQOVF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get flag ADC analog watchdog 1 flag

+  * @rmtoll ISR      AWD1           LL_ADC_IsActiveFlag_AWD1

+  * @param  ADCx ADC instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get flag ADC analog watchdog 2.

+  * @rmtoll ISR      AWD2           LL_ADC_IsActiveFlag_AWD2

+  * @param  ADCx ADC instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get flag ADC analog watchdog 3.

+  * @rmtoll ISR      AWD3           LL_ADC_IsActiveFlag_AWD3

+  * @param  ADCx ADC instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear flag ADC ready.

+  * @note   On this STM32 serie, flag LL_ADC_FLAG_ADRDY is raised when the ADC

+  *         is enabled and when conversion clock is active.

+  *         (not only core clock: this ADC has a dual clock domain)

+  * @rmtoll ISR      ADRDY          LL_ADC_ClearFlag_ADRDY

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx)

+{

+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY);

+}

+

+/**

+  * @brief  Clear flag ADC group regular end of unitary conversion.

+  * @rmtoll ISR      EOC            LL_ADC_ClearFlag_EOC

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx)

+{

+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC);

+}

+

+/**

+  * @brief  Clear flag ADC group regular end of sequence conversions.

+  * @rmtoll ISR      EOS            LL_ADC_ClearFlag_EOS

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx)

+{

+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS);

+}

+

+/**

+  * @brief  Clear flag ADC group regular overrun.

+  * @rmtoll ISR      OVR            LL_ADC_ClearFlag_OVR

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx)

+{

+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR);

+}

+

+/**

+  * @brief  Clear flag ADC group regular end of sampling phase.

+  * @rmtoll ISR      EOSMP          LL_ADC_ClearFlag_EOSMP

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx)

+{

+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP);

+}

+

+/**

+  * @brief  Clear flag ADC group injected end of unitary conversion.

+  * @rmtoll ISR      JEOC           LL_ADC_ClearFlag_JEOC

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_ClearFlag_JEOC(ADC_TypeDef *ADCx)

+{

+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOC);

+}

+

+/**

+  * @brief  Clear flag ADC group injected end of sequence conversions.

+  * @rmtoll ISR      JEOS           LL_ADC_ClearFlag_JEOS

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_ClearFlag_JEOS(ADC_TypeDef *ADCx)

+{

+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JEOS);

+}

+

+/**

+  * @brief  Clear flag ADC group injected contexts queue overflow.

+  * @rmtoll ISR      JQOVF          LL_ADC_ClearFlag_JQOVF

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_ClearFlag_JQOVF(ADC_TypeDef *ADCx)

+{

+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_JQOVF);

+}

+

+/**

+  * @brief  Clear flag ADC analog watchdog 1.

+  * @rmtoll ISR      AWD1           LL_ADC_ClearFlag_AWD1

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx)

+{

+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1);

+}

+

+/**

+  * @brief  Clear flag ADC analog watchdog 2.

+  * @rmtoll ISR      AWD2           LL_ADC_ClearFlag_AWD2

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx)

+{

+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2);

+}

+

+/**

+  * @brief  Clear flag ADC analog watchdog 3.

+  * @rmtoll ISR      AWD3           LL_ADC_ClearFlag_AWD3

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx)

+{

+  WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3);

+}

+

+/**

+  * @brief  Get flag multimode ADC ready of the ADC master.

+  * @rmtoll CSR      ADRDY_MST      LL_ADC_IsActiveFlag_MST_ADRDY

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)

+{

+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_MST) == (LL_ADC_FLAG_ADRDY_MST)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get flag multimode ADC ready of the ADC slave.

+  * @rmtoll CSR      ADRDY_SLV      LL_ADC_IsActiveFlag_SLV_ADRDY

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_ADRDY(ADC_Common_TypeDef *ADCxy_COMMON)

+{

+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_ADRDY_SLV) == (LL_ADC_FLAG_ADRDY_SLV)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get flag multimode ADC group regular end of unitary conversion of the ADC master.

+  * @rmtoll CSR      EOC_MST        LL_ADC_IsActiveFlag_MST_EOC

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOC(ADC_Common_TypeDef *ADCxy_COMMON)

+{

+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get flag multimode ADC group regular end of unitary conversion of the ADC slave.

+  * @rmtoll CSR      EOC_SLV        LL_ADC_IsActiveFlag_SLV_EOC

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOC(ADC_Common_TypeDef *ADCxy_COMMON)

+{

+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOC_SLV) == (LL_ADC_FLAG_EOC_SLV)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get flag multimode ADC group regular end of sequence conversions of the ADC master.

+  * @rmtoll CSR      EOS_MST        LL_ADC_IsActiveFlag_MST_EOS

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOS(ADC_Common_TypeDef *ADCxy_COMMON)

+{

+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_MST) == (LL_ADC_FLAG_EOS_MST)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get flag multimode ADC group regular end of sequence conversions of the ADC slave.

+  * @rmtoll CSR      EOS_SLV        LL_ADC_IsActiveFlag_SLV_EOS

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOS(ADC_Common_TypeDef *ADCxy_COMMON)

+{

+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOS_SLV) == (LL_ADC_FLAG_EOS_SLV)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get flag multimode ADC group regular overrun of the ADC master.

+  * @rmtoll CSR      OVR_MST        LL_ADC_IsActiveFlag_MST_OVR

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_OVR(ADC_Common_TypeDef *ADCxy_COMMON)

+{

+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_MST) == (LL_ADC_FLAG_OVR_MST)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get flag multimode ADC group regular overrun of the ADC slave.

+  * @rmtoll CSR      OVR_SLV        LL_ADC_IsActiveFlag_SLV_OVR

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_OVR(ADC_Common_TypeDef *ADCxy_COMMON)

+{

+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_OVR_SLV) == (LL_ADC_FLAG_OVR_SLV)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get flag multimode ADC group regular end of sampling of the ADC master.

+  * @rmtoll CSR      EOSMP_MST      LL_ADC_IsActiveFlag_MST_EOSMP

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)

+{

+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_MST) == (LL_ADC_FLAG_EOSMP_MST)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get flag multimode ADC group regular end of sampling of the ADC slave.

+  * @rmtoll CSR      EOSMP_SLV      LL_ADC_IsActiveFlag_SLV_EOSMP

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_EOSMP(ADC_Common_TypeDef *ADCxy_COMMON)

+{

+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_EOSMP_SLV) == (LL_ADC_FLAG_EOSMP_SLV)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get flag multimode ADC group injected end of unitary conversion of the ADC master.

+  * @rmtoll CSR      JEOC_MST       LL_ADC_IsActiveFlag_MST_JEOC

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)

+{

+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_MST) == (LL_ADC_FLAG_JEOC_MST)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get flag multimode ADC group injected end of unitary conversion of the ADC slave.

+  * @rmtoll CSR      JEOC_SLV       LL_ADC_IsActiveFlag_SLV_JEOC

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOC(ADC_Common_TypeDef *ADCxy_COMMON)

+{

+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOC_SLV) == (LL_ADC_FLAG_JEOC_SLV)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC master.

+  * @rmtoll CSR      JEOS_MST       LL_ADC_IsActiveFlag_MST_JEOS

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)

+{

+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_MST) == (LL_ADC_FLAG_JEOS_MST)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get flag multimode ADC group injected end of sequence conversions of the ADC slave.

+  * @rmtoll CSR      JEOS_SLV       LL_ADC_IsActiveFlag_SLV_JEOS

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JEOS(ADC_Common_TypeDef *ADCxy_COMMON)

+{

+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JEOS_SLV) == (LL_ADC_FLAG_JEOS_SLV)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get flag multimode ADC group injected context queue overflow of the ADC master.

+  * @rmtoll CSR      JQOVF_MST      LL_ADC_IsActiveFlag_MST_JQOVF

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)

+{

+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_MST) == (LL_ADC_FLAG_JQOVF_MST)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get flag multimode ADC group injected context queue overflow of the ADC slave.

+  * @rmtoll CSR      JQOVF_SLV      LL_ADC_IsActiveFlag_SLV_JQOVF

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_JQOVF(ADC_Common_TypeDef *ADCxy_COMMON)

+{

+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_JQOVF_SLV) == (LL_ADC_FLAG_JQOVF_SLV)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get flag multimode ADC analog watchdog 1 of the ADC master.

+  * @rmtoll CSR      AWD1_MST       LL_ADC_IsActiveFlag_MST_AWD1

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)

+{

+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_MST) == (LL_ADC_FLAG_AWD1_MST)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get flag multimode analog watchdog 1 of the ADC slave.

+  * @rmtoll CSR      AWD1_SLV       LL_ADC_IsActiveFlag_SLV_AWD1

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD1(ADC_Common_TypeDef *ADCxy_COMMON)

+{

+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD1_SLV) == (LL_ADC_FLAG_AWD1_SLV)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get flag multimode ADC analog watchdog 2 of the ADC master.

+  * @rmtoll CSR      AWD2_MST       LL_ADC_IsActiveFlag_MST_AWD2

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)

+{

+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_MST) == (LL_ADC_FLAG_AWD2_MST)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get flag multimode ADC analog watchdog 2 of the ADC slave.

+  * @rmtoll CSR      AWD2_SLV       LL_ADC_IsActiveFlag_SLV_AWD2

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD2(ADC_Common_TypeDef *ADCxy_COMMON)

+{

+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD2_SLV) == (LL_ADC_FLAG_AWD2_SLV)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get flag multimode ADC analog watchdog 3 of the ADC master.

+  * @rmtoll CSR      AWD3_MST       LL_ADC_IsActiveFlag_MST_AWD3

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_MST_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)

+{

+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_MST) == (LL_ADC_FLAG_AWD3_MST)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get flag multimode ADC analog watchdog 3 of the ADC slave.

+  * @rmtoll CSR      AWD3_SLV       LL_ADC_IsActiveFlag_SLV_AWD3

+  * @param  ADCxy_COMMON ADC common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_SLV_AWD3(ADC_Common_TypeDef *ADCxy_COMMON)

+{

+  return ((READ_BIT(ADCxy_COMMON->CSR, LL_ADC_FLAG_AWD3_SLV) == (LL_ADC_FLAG_AWD3_SLV)) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup ADC_LL_EF_IT_Management ADC IT management

+  * @{

+  */

+

+/**

+  * @brief  Enable ADC ready.

+  * @rmtoll IER      ADRDYIE        LL_ADC_EnableIT_ADRDY

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx)

+{

+  SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY);

+}

+

+/**

+  * @brief  Enable interruption ADC group regular end of unitary conversion.

+  * @rmtoll IER      EOCIE          LL_ADC_EnableIT_EOC

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx)

+{

+  SET_BIT(ADCx->IER, LL_ADC_IT_EOC);

+}

+

+/**

+  * @brief  Enable interruption ADC group regular end of sequence conversions.

+  * @rmtoll IER      EOSIE          LL_ADC_EnableIT_EOS

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx)

+{

+  SET_BIT(ADCx->IER, LL_ADC_IT_EOS);

+}

+

+/**

+  * @brief  Enable ADC group regular interruption overrun.

+  * @rmtoll IER      OVRIE          LL_ADC_EnableIT_OVR

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx)

+{

+  SET_BIT(ADCx->IER, LL_ADC_IT_OVR);

+}

+

+/**

+  * @brief  Enable interruption ADC group regular end of sampling.

+  * @rmtoll IER      EOSMPIE        LL_ADC_EnableIT_EOSMP

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx)

+{

+  SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP);

+}

+

+/**

+  * @brief  Enable interruption ADC group injected end of unitary conversion.

+  * @rmtoll IER      JEOCIE         LL_ADC_EnableIT_JEOC

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_EnableIT_JEOC(ADC_TypeDef *ADCx)

+{

+  SET_BIT(ADCx->IER, LL_ADC_IT_JEOC);

+}

+

+/**

+  * @brief  Enable interruption ADC group injected end of sequence conversions.

+  * @rmtoll IER      JEOSIE         LL_ADC_EnableIT_JEOS

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_EnableIT_JEOS(ADC_TypeDef *ADCx)

+{

+  SET_BIT(ADCx->IER, LL_ADC_IT_JEOS);

+}

+

+/**

+  * @brief  Enable interruption ADC group injected context queue overflow.

+  * @rmtoll IER      JQOVFIE        LL_ADC_EnableIT_JQOVF

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_EnableIT_JQOVF(ADC_TypeDef *ADCx)

+{

+  SET_BIT(ADCx->IER, LL_ADC_IT_JQOVF);

+}

+

+/**

+  * @brief  Enable interruption ADC analog watchdog 1.

+  * @rmtoll IER      AWD1IE         LL_ADC_EnableIT_AWD1

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx)

+{

+  SET_BIT(ADCx->IER, LL_ADC_IT_AWD1);

+}

+

+/**

+  * @brief  Enable interruption ADC analog watchdog 2.

+  * @rmtoll IER      AWD2IE         LL_ADC_EnableIT_AWD2

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx)

+{

+  SET_BIT(ADCx->IER, LL_ADC_IT_AWD2);

+}

+

+/**

+  * @brief  Enable interruption ADC analog watchdog 3.

+  * @rmtoll IER      AWD3IE         LL_ADC_EnableIT_AWD3

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx)

+{

+  SET_BIT(ADCx->IER, LL_ADC_IT_AWD3);

+}

+

+/**

+  * @brief  Disable interruption ADC ready.

+  * @rmtoll IER      ADRDYIE        LL_ADC_DisableIT_ADRDY

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx)

+{

+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY);

+}

+

+/**

+  * @brief  Disable interruption ADC group regular end of unitary conversion.

+  * @rmtoll IER      EOCIE          LL_ADC_DisableIT_EOC

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx)

+{

+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC);

+}

+

+/**

+  * @brief  Disable interruption ADC group regular end of sequence conversions.

+  * @rmtoll IER      EOSIE          LL_ADC_DisableIT_EOS

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx)

+{

+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS);

+}

+

+/**

+  * @brief  Disable interruption ADC group regular overrun.

+  * @rmtoll IER      OVRIE          LL_ADC_DisableIT_OVR

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx)

+{

+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR);

+}

+

+/**

+  * @brief  Disable interruption ADC group regular end of sampling.

+  * @rmtoll IER      EOSMPIE        LL_ADC_DisableIT_EOSMP

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx)

+{

+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP);

+}

+

+/**

+  * @brief  Disable interruption ADC group regular end of unitary conversion.

+  * @rmtoll IER      JEOCIE         LL_ADC_DisableIT_JEOC

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_DisableIT_JEOC(ADC_TypeDef *ADCx)

+{

+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOC);

+}

+

+/**

+  * @brief  Disable interruption ADC group injected end of sequence conversions.

+  * @rmtoll IER      JEOSIE         LL_ADC_DisableIT_JEOS

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_DisableIT_JEOS(ADC_TypeDef *ADCx)

+{

+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_JEOS);

+}

+

+/**

+  * @brief  Disable interruption ADC group injected context queue overflow.

+  * @rmtoll IER      JQOVFIE        LL_ADC_DisableIT_JQOVF

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_DisableIT_JQOVF(ADC_TypeDef *ADCx)

+{

+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_JQOVF);

+}

+

+/**

+  * @brief  Disable interruption ADC analog watchdog 1.

+  * @rmtoll IER      AWD1IE         LL_ADC_DisableIT_AWD1

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx)

+{

+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1);

+}

+

+/**

+  * @brief  Disable interruption ADC analog watchdog 2.

+  * @rmtoll IER      AWD2IE         LL_ADC_DisableIT_AWD2

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx)

+{

+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2);

+}

+

+/**

+  * @brief  Disable interruption ADC analog watchdog 3.

+  * @rmtoll IER      AWD3IE         LL_ADC_DisableIT_AWD3

+  * @param  ADCx ADC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx)

+{

+  CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3);

+}

+

+/**

+  * @brief  Get state of interruption ADC ready

+  *         (0: interrupt disabled, 1: interrupt enabled).

+  * @rmtoll IER      ADRDYIE        LL_ADC_IsEnabledIT_ADRDY

+  * @param  ADCx ADC instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get state of interruption ADC group regular end of unitary conversion

+  *         (0: interrupt disabled, 1: interrupt enabled).

+  * @rmtoll IER      EOCIE          LL_ADC_IsEnabledIT_EOC

+  * @param  ADCx ADC instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get state of interruption ADC group regular end of sequence conversions

+  *         (0: interrupt disabled, 1: interrupt enabled).

+  * @rmtoll IER      EOSIE          LL_ADC_IsEnabledIT_EOS

+  * @param  ADCx ADC instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get state of interruption ADC group regular overrun

+  *         (0: interrupt disabled, 1: interrupt enabled).

+  * @rmtoll IER      OVRIE          LL_ADC_IsEnabledIT_OVR

+  * @param  ADCx ADC instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get state of interruption ADC group regular end of sampling

+  *         (0: interrupt disabled, 1: interrupt enabled).

+  * @rmtoll IER      EOSMPIE        LL_ADC_IsEnabledIT_EOSMP

+  * @param  ADCx ADC instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get state of interruption ADC group injected end of unitary conversion

+  *         (0: interrupt disabled, 1: interrupt enabled).

+  * @rmtoll IER      JEOCIE         LL_ADC_IsEnabledIT_JEOC

+  * @param  ADCx ADC instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOC(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOC) == (LL_ADC_IT_JEOC)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get state of interruption ADC group injected end of sequence conversions

+  *         (0: interrupt disabled, 1: interrupt enabled).

+  * @rmtoll IER      JEOSIE         LL_ADC_IsEnabledIT_JEOS

+  * @param  ADCx ADC instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JEOS(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_JEOS) == (LL_ADC_IT_JEOS)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get state of interruption ADC group injected context queue overflow interrupt state

+  *         (0: interrupt disabled, 1: interrupt enabled).

+  * @rmtoll IER      JQOVFIE        LL_ADC_IsEnabledIT_JQOVF

+  * @param  ADCx ADC instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_JQOVF(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_JQOVF) == (LL_ADC_IT_JQOVF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get state of interruption ADC analog watchdog 1

+  *         (0: interrupt disabled, 1: interrupt enabled).

+  * @rmtoll IER      AWD1IE         LL_ADC_IsEnabledIT_AWD1

+  * @param  ADCx ADC instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get state of interruption Get ADC analog watchdog 2

+  *         (0: interrupt disabled, 1: interrupt enabled).

+  * @rmtoll IER      AWD2IE         LL_ADC_IsEnabledIT_AWD2

+  * @param  ADCx ADC instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get state of interruption Get ADC analog watchdog 3

+  *         (0: interrupt disabled, 1: interrupt enabled).

+  * @rmtoll IER      AWD3IE         LL_ADC_IsEnabledIT_AWD3

+  * @param  ADCx ADC instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx)

+{

+  return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions

+  * @{

+  */

+

+/* Initialization of some features of ADC common parameters and multimode */

+ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON);

+ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);

+void        LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct);

+

+/* De-initialization of ADC instance, ADC group regular and ADC group injected */

+/* (availability of ADC group injected depends on STM32 families) */

+ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx);

+

+/* Initialization of some features of ADC instance */

+ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct);

+void        LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct);

+

+/* Initialization of some features of ADC instance and ADC group regular */

+ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);

+void        LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct);

+

+/* Initialization of some features of ADC instance and ADC group injected */

+ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);

+void        LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct);

+

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* ADC1 || ADC2 || ADC3 */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_LL_ADC_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_bdma.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_bdma.h
new file mode 100644
index 0000000000..122e2dcc90
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_bdma.h
@@ -0,0 +1,2415 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_bdma.h

+  * @author  MCD Application Team

+  * @brief   Header file of BDMA LL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_LL_BDMA_H

+#define STM32H7xx_LL_BDMA_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+#include "stm32h7xx_ll_dmamux.h"

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+#if defined (BDMA) || defined (BDMA1) || defined (BDMA2)

+

+/** @defgroup BDMA_LL BDMA

+  * @{

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/** @defgroup BDMA_LL_Private_Variables BDMA Private Variables

+  * @{

+  */

+/* Array used to get the BDMA channel register offset versus channel index LL_BDMA_CHANNEL_x */

+static const uint8_t LL_BDMA_CH_OFFSET_TAB[] =

+{

+  (uint8_t)(BDMA_Channel0_BASE - BDMA_BASE),

+  (uint8_t)(BDMA_Channel1_BASE - BDMA_BASE),

+  (uint8_t)(BDMA_Channel2_BASE - BDMA_BASE),

+  (uint8_t)(BDMA_Channel3_BASE - BDMA_BASE),

+  (uint8_t)(BDMA_Channel4_BASE - BDMA_BASE),

+  (uint8_t)(BDMA_Channel5_BASE - BDMA_BASE),

+  (uint8_t)(BDMA_Channel6_BASE - BDMA_BASE),

+  (uint8_t)(BDMA_Channel7_BASE - BDMA_BASE)

+};

+/**

+  * @}

+  */

+

+/* Private constants ---------------------------------------------------------*/

+/* Private macros ------------------------------------------------------------*/

+#if !defined(UNUSED)

+#define UNUSED(x) ((void)(x))

+#endif

+

+/* Exported types ------------------------------------------------------------*/

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup BDMA_LL_ES_INIT BDMA Exported Init structure

+  * @{

+  */

+typedef struct

+{

+  uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for BDMA transfer

+                                        or as Source base address in case of memory to memory transfer direction.

+

+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */

+

+  uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer

+                                        or as Destination base address in case of memory to memory transfer direction.

+

+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */

+

+  uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to peripheral,

+                                        from memory to memory or from peripheral to memory.

+                                        This parameter can be a value of @ref BDMA_LL_EC_DIRECTION

+

+                                        This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataTransferDirection(). */

+

+  uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.

+                                        This parameter can be a value of @ref BDMA_LL_EC_MODE

+                                        @note: The circular buffer mode cannot be used if the memory to memory

+                                               data transfer direction is configured on the selected Channel

+

+                                        This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMode(). */

+

+  uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction

+                                        is incremented or not.

+                                        This parameter can be a value of @ref BDMA_LL_EC_PERIPH

+

+                                        This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphIncMode(). */

+

+  uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction

+                                        is incremented or not.

+                                        This parameter can be a value of @ref BDMA_LL_EC_MEMORY

+

+                                        This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMemoryIncMode(). */

+

+  uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)

+                                        in case of memory to memory transfer direction.

+                                        This parameter can be a value of @ref BDMA_LL_EC_PDATAALIGN

+

+                                        This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphSize(). */

+

+  uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)

+                                        in case of memory to memory transfer direction.

+                                        This parameter can be a value of @ref BDMA_LL_EC_MDATAALIGN

+

+                                        This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMemorySize(). */

+

+  uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.

+                                        The data unit is equal to the source buffer configuration set in PeripheralSize

+                                        or MemorySize parameters depending in the transfer direction.

+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF

+

+                                        This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataLength(). */

+

+  uint32_t PeriphRequest;          /*!< Specifies the peripheral request.

+                                        This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST

+

+                                        This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphRequest(). */

+

+  uint32_t Priority;               /*!< Specifies the channel priority level.

+                                        This parameter can be a value of @ref BDMA_LL_EC_PRIORITY

+

+                                        This feature can be modified afterwards using unitary function @ref LL_BDMA_SetChannelPriorityLevel(). */

+

+} LL_BDMA_InitTypeDef;

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup BDMA_LL_Exported_Constants BDMA Exported Constants

+  * @{

+  */

+/** @defgroup BDMA_LL_EC_CLEAR_FLAG Clear Flags Defines

+  * @brief    Flags defines which can be used with LL_BDMA_WriteReg function

+  * @{

+  */

+#define LL_BDMA_IFCR_CGIF1                 BDMA_IFCR_CGIF1        /*!< Channel 1 global flag            */

+#define LL_BDMA_IFCR_CTCIF1                BDMA_IFCR_CTCIF1       /*!< Channel 1 transfer complete flag */

+#define LL_BDMA_IFCR_CHTIF1                BDMA_IFCR_CHTIF1       /*!< Channel 1 half transfer flag     */

+#define LL_BDMA_IFCR_CTEIF1                BDMA_IFCR_CTEIF1       /*!< Channel 1 transfer error flag    */

+#define LL_BDMA_IFCR_CGIF2                 BDMA_IFCR_CGIF2        /*!< Channel 2 global flag            */

+#define LL_BDMA_IFCR_CTCIF2                BDMA_IFCR_CTCIF2       /*!< Channel 2 transfer complete flag */

+#define LL_BDMA_IFCR_CHTIF2                BDMA_IFCR_CHTIF2       /*!< Channel 2 half transfer flag     */

+#define LL_BDMA_IFCR_CTEIF2                BDMA_IFCR_CTEIF2       /*!< Channel 2 transfer error flag    */

+#define LL_BDMA_IFCR_CGIF3                 BDMA_IFCR_CGIF3        /*!< Channel 3 global flag            */

+#define LL_BDMA_IFCR_CTCIF3                BDMA_IFCR_CTCIF3       /*!< Channel 3 transfer complete flag */

+#define LL_BDMA_IFCR_CHTIF3                BDMA_IFCR_CHTIF3       /*!< Channel 3 half transfer flag     */

+#define LL_BDMA_IFCR_CTEIF3                BDMA_IFCR_CTEIF3       /*!< Channel 3 transfer error flag    */

+#define LL_BDMA_IFCR_CGIF4                 BDMA_IFCR_CGIF4        /*!< Channel 4 global flag            */

+#define LL_BDMA_IFCR_CTCIF4                BDMA_IFCR_CTCIF4       /*!< Channel 4 transfer complete flag */

+#define LL_BDMA_IFCR_CHTIF4                BDMA_IFCR_CHTIF4       /*!< Channel 4 half transfer flag     */

+#define LL_BDMA_IFCR_CTEIF4                BDMA_IFCR_CTEIF4       /*!< Channel 4 transfer error flag    */

+#define LL_BDMA_IFCR_CGIF5                 BDMA_IFCR_CGIF5        /*!< Channel 5 global flag            */

+#define LL_BDMA_IFCR_CTCIF5                BDMA_IFCR_CTCIF5       /*!< Channel 5 transfer complete flag */

+#define LL_BDMA_IFCR_CHTIF5                BDMA_IFCR_CHTIF5       /*!< Channel 5 half transfer flag     */

+#define LL_BDMA_IFCR_CTEIF5                BDMA_IFCR_CTEIF5       /*!< Channel 5 transfer error flag    */

+#define LL_BDMA_IFCR_CGIF6                 BDMA_IFCR_CGIF6        /*!< Channel 6 global flag            */

+#define LL_BDMA_IFCR_CTCIF6                BDMA_IFCR_CTCIF6       /*!< Channel 6 transfer complete flag */

+#define LL_BDMA_IFCR_CHTIF6                BDMA_IFCR_CHTIF6       /*!< Channel 6 half transfer flag     */

+#define LL_BDMA_IFCR_CTEIF6                BDMA_IFCR_CTEIF6       /*!< Channel 6 transfer error flag    */

+#define LL_BDMA_IFCR_CGIF7                 BDMA_IFCR_CGIF7        /*!< Channel 7 global flag            */

+#define LL_BDMA_IFCR_CTCIF7                BDMA_IFCR_CTCIF7       /*!< Channel 7 transfer complete flag */

+#define LL_BDMA_IFCR_CHTIF7                BDMA_IFCR_CHTIF7       /*!< Channel 7 half transfer flag     */

+#define LL_BDMA_IFCR_CTEIF7                BDMA_IFCR_CTEIF7       /*!< Channel 7 transfer error flag    */

+/**

+  * @}

+  */

+

+/** @defgroup BDMA_LL_EC_GET_FLAG Get Flags Defines

+  * @brief    Flags defines which can be used with LL_BDMA_ReadReg function

+  * @{

+  */

+#define LL_BDMA_ISR_GIF0                   BDMA_ISR_GIF0          /*!< Channel 1 global flag            */

+#define LL_BDMA_ISR_TCIF0                  BDMA_ISR_TCIF0         /*!< Channel 1 transfer complete flag */

+#define LL_BDMA_ISR_HTIF0                  BDMA_ISR_HTIF0         /*!< Channel 1 half transfer flag     */

+#define LL_BDMA_ISR_TEIF0                  BDMA_ISR_TEIF0         /*!< Channel 1 transfer error flag    */

+#define LL_BDMA_ISR_GIF1                   BDMA_ISR_GIF1          /*!< Channel 1 global flag            */

+#define LL_BDMA_ISR_TCIF1                  BDMA_ISR_TCIF1         /*!< Channel 1 transfer complete flag */

+#define LL_BDMA_ISR_HTIF1                  BDMA_ISR_HTIF1         /*!< Channel 1 half transfer flag     */

+#define LL_BDMA_ISR_TEIF1                  BDMA_ISR_TEIF1         /*!< Channel 1 transfer error flag    */

+#define LL_BDMA_ISR_GIF2                   BDMA_ISR_GIF2          /*!< Channel 2 global flag            */

+#define LL_BDMA_ISR_TCIF2                  BDMA_ISR_TCIF2         /*!< Channel 2 transfer complete flag */

+#define LL_BDMA_ISR_HTIF2                  BDMA_ISR_HTIF2         /*!< Channel 2 half transfer flag     */

+#define LL_BDMA_ISR_TEIF2                  BDMA_ISR_TEIF2         /*!< Channel 2 transfer error flag    */

+#define LL_BDMA_ISR_GIF3                   BDMA_ISR_GIF3          /*!< Channel 3 global flag            */

+#define LL_BDMA_ISR_TCIF3                  BDMA_ISR_TCIF3         /*!< Channel 3 transfer complete flag */

+#define LL_BDMA_ISR_HTIF3                  BDMA_ISR_HTIF3         /*!< Channel 3 half transfer flag     */

+#define LL_BDMA_ISR_TEIF3                  BDMA_ISR_TEIF3         /*!< Channel 3 transfer error flag    */

+#define LL_BDMA_ISR_GIF4                   BDMA_ISR_GIF4          /*!< Channel 4 global flag            */

+#define LL_BDMA_ISR_TCIF4                  BDMA_ISR_TCIF4         /*!< Channel 4 transfer complete flag */

+#define LL_BDMA_ISR_HTIF4                  BDMA_ISR_HTIF4         /*!< Channel 4 half transfer flag     */

+#define LL_BDMA_ISR_TEIF4                  BDMA_ISR_TEIF4         /*!< Channel 4 transfer error flag    */

+#define LL_BDMA_ISR_GIF5                   BDMA_ISR_GIF5          /*!< Channel 5 global flag            */

+#define LL_BDMA_ISR_TCIF5                  BDMA_ISR_TCIF5         /*!< Channel 5 transfer complete flag */

+#define LL_BDMA_ISR_HTIF5                  BDMA_ISR_HTIF5         /*!< Channel 5 half transfer flag     */

+#define LL_BDMA_ISR_TEIF5                  BDMA_ISR_TEIF5         /*!< Channel 5 transfer error flag    */

+#define LL_BDMA_ISR_GIF6                   BDMA_ISR_GIF6          /*!< Channel 6 global flag            */

+#define LL_BDMA_ISR_TCIF6                  BDMA_ISR_TCIF6         /*!< Channel 6 transfer complete flag */

+#define LL_BDMA_ISR_HTIF6                  BDMA_ISR_HTIF6         /*!< Channel 6 half transfer flag     */

+#define LL_BDMA_ISR_TEIF6                  BDMA_ISR_TEIF6         /*!< Channel 6 transfer error flag    */

+#define LL_BDMA_ISR_GIF7                   BDMA_ISR_GIF7          /*!< Channel 7 global flag            */

+#define LL_BDMA_ISR_TCIF7                  BDMA_ISR_TCIF7         /*!< Channel 7 transfer complete flag */

+#define LL_BDMA_ISR_HTIF7                  BDMA_ISR_HTIF7         /*!< Channel 7 half transfer flag     */

+#define LL_BDMA_ISR_TEIF7                  BDMA_ISR_TEIF7         /*!< Channel 7 transfer error flag    */

+/**

+  * @}

+  */

+

+/** @defgroup BDMA_LL_EC_IT IT Defines

+  * @brief    IT defines which can be used with LL_BDMA_ReadReg and  LL_BDMA_WriteReg functions

+  * @{

+  */

+#define LL_BDMA_CCR_TCIE                   BDMA_CCR_TCIE          /*!< Transfer complete interrupt */

+#define LL_BDMA_CCR_HTIE                   BDMA_CCR_HTIE          /*!< Half Transfer interrupt     */

+#define LL_BDMA_CCR_TEIE                   BDMA_CCR_TEIE          /*!< Transfer error interrupt    */

+/**

+  * @}

+  */

+

+/** @defgroup BDMA_LL_EC_CHANNEL CHANNEL

+  * @{

+  */

+#define LL_BDMA_CHANNEL_0                  0x00000000U /*!< DMA Channel 0  */

+#define LL_BDMA_CHANNEL_1                  0x00000001U /*!< BDMA Channel 1 */

+#define LL_BDMA_CHANNEL_2                  0x00000002U /*!< BDMA Channel 2 */

+#define LL_BDMA_CHANNEL_3                  0x00000003U /*!< BDMA Channel 3 */

+#define LL_BDMA_CHANNEL_4                  0x00000004U /*!< BDMA Channel 4 */

+#define LL_BDMA_CHANNEL_5                  0x00000005U /*!< BDMA Channel 5 */

+#define LL_BDMA_CHANNEL_6                  0x00000006U /*!< BDMA Channel 6 */

+#define LL_BDMA_CHANNEL_7                  0x00000007U /*!< BDMA Channel 7 */

+#if defined(USE_FULL_LL_DRIVER)

+#define LL_BDMA_CHANNEL_ALL                0xFFFF0000U /*!< BDMA Channel all (used only for function @ref LL_BDMA_DeInit(). */

+#endif /*USE_FULL_LL_DRIVER*/

+/**

+  * @}

+  */

+

+/** @defgroup BDMA_LL_EC_DIRECTION Transfer Direction

+  * @{

+  */

+#define LL_BDMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U              /*!< Peripheral to memory direction       */

+#define LL_BDMA_DIRECTION_MEMORY_TO_PERIPH BDMA_CCR_DIR             /*!< Memory to peripheral direction       */

+#define LL_BDMA_DIRECTION_MEMORY_TO_MEMORY BDMA_CCR_MEM2MEM         /*!< Memory to memory direction           */

+/**

+  * @}

+  */

+

+/** @defgroup BDMA_LL_EC_MODE Transfer mode

+  * @{

+  */

+#define LL_BDMA_MODE_NORMAL                0x00000000U              /*!< Normal Mode                          */

+#define LL_BDMA_MODE_CIRCULAR              BDMA_CCR_CIRC            /*!< Circular Mode                        */

+/**

+  * @}

+  */

+

+/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE

+  * @{

+  */

+#define LL_BDMA_DOUBLEBUFFER_MODE_DISABLE  0x00000000U              /*!< Disable double buffering mode        */

+#define LL_BDMA_DOUBLEBUFFER_MODE_ENABLE   BDMA_CCR_DBM             /*!< Enable double buffering mode         */

+/**

+  * @}

+  */

+

+/** @defgroup BDMA_LL_EC_PERIPH Peripheral increment mode

+  * @{

+  */

+#define LL_BDMA_PERIPH_INCREMENT           BDMA_CCR_PINC            /*!< Peripheral increment mode Enable     */

+#define LL_BDMA_PERIPH_NOINCREMENT         0x00000000U              /*!< Peripheral increment mode Disable    */

+/**

+  * @}

+  */

+

+/** @defgroup BDMA_LL_EC_MEMORY Memory increment mode

+  * @{

+  */

+#define LL_BDMA_MEMORY_INCREMENT           BDMA_CCR_MINC            /*!< Memory increment mode Enable         */

+#define LL_BDMA_MEMORY_NOINCREMENT         0x00000000U              /*!< Memory increment mode Disable        */

+/**

+  * @}

+  */

+

+/** @defgroup BDMA_LL_EC_PDATAALIGN Peripheral data alignment

+  * @{

+  */

+#define LL_BDMA_PDATAALIGN_BYTE            0x00000000U              /*!< Peripheral data alignment : Byte     */

+#define LL_BDMA_PDATAALIGN_HALFWORD        BDMA_CCR_PSIZE_0         /*!< Peripheral data alignment : HalfWord */

+#define LL_BDMA_PDATAALIGN_WORD            BDMA_CCR_PSIZE_1         /*!< Peripheral data alignment : Word     */

+/**

+  * @}

+  */

+

+/** @defgroup BDMA_LL_EC_MDATAALIGN Memory data alignment

+  * @{

+  */

+#define LL_BDMA_MDATAALIGN_BYTE            0x00000000U              /*!< Memory data alignment : Byte         */

+#define LL_BDMA_MDATAALIGN_HALFWORD        BDMA_CCR_MSIZE_0         /*!< Memory data alignment : HalfWord     */

+#define LL_BDMA_MDATAALIGN_WORD            BDMA_CCR_MSIZE_1         /*!< Memory data alignment : Word         */

+/**

+  * @}

+  */

+

+/** @defgroup BDMA_LL_EC_PRIORITY Transfer Priority level

+  * @{

+  */

+#define LL_BDMA_PRIORITY_LOW               0x00000000U              /*!< Priority level : Low                 */

+#define LL_BDMA_PRIORITY_MEDIUM            BDMA_CCR_PL_0            /*!< Priority level : Medium              */

+#define LL_BDMA_PRIORITY_HIGH              BDMA_CCR_PL_1            /*!< Priority level : High                */

+#define LL_BDMA_PRIORITY_VERYHIGH          BDMA_CCR_PL              /*!< Priority level : Very_High           */

+/**

+  * @}

+  */

+

+/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM

+  * @{

+  */

+#define LL_BDMA_CURRENTTARGETMEM0          0x00000000U              /*!< Set CurrentTarget Memory to Memory 0 */

+#define LL_BDMA_CURRENTTARGETMEM1          BDMA_CCR_CT              /*!< Set CurrentTarget Memory to Memory 1 */

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup BDMA_LL_Exported_Macros BDMA Exported Macros

+  * @{

+  */

+

+/** @defgroup BDMA_LL_EM_WRITE_READ Common Write and read registers macros

+  * @{

+  */

+/**

+  * @brief  Write a value in BDMA register

+  * @param  __INSTANCE__ BDMA Instance

+  * @param  __REG__ Register to be written

+  * @param  __VALUE__ Value to be written in the register

+  * @retval None

+  */

+#define LL_BDMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))

+

+/**

+  * @brief  Read a value in BDMA register

+  * @param  __INSTANCE__ BDMA Instance

+  * @param  __REG__ Register to be read

+  * @retval Register value

+  */

+#define LL_BDMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)

+/**

+  * @}

+  */

+

+/** @defgroup BDMA_LL_EM_CONVERT_DMAxCHANNELy Convert BDMAxChannely

+  * @{

+  */

+/**

+  * @brief  Convert BDMAx_Channely into BDMAx

+  * @param  __CHANNEL_INSTANCE__ BDMAx_Channely

+  * @retval BDMAx

+  */

+#if defined (BDMA1)

+#define __LL_BDMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \

+(((uint32_t)(__CHANNEL_INSTANCE__) < LL_BDMA_CHANNEL_0) ? BDMA1 : BDMA)

+#else

+#define __LL_BDMA_GET_INSTANCE(__CHANNEL_INSTANCE__)  (BDMA)

+#endif /* BDMA1 */

+

+/**

+  * @brief  Convert BDMAx_Channely into LL_BDMA_CHANNEL_y

+  * @param  __CHANNEL_INSTANCE__ BDMAx_Channely

+  * @retval LL_BDMA_CHANNEL_y

+  */

+#if defined (BDMA1)

+#define __LL_BDMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \

+(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel0))  ? LL_BDMA_CHANNEL_0 : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel0)) ? LL_BDMA_CHANNEL_0 : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel1))  ? LL_BDMA_CHANNEL_1 : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel1)) ? LL_BDMA_CHANNEL_1 : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel2))  ? LL_BDMA_CHANNEL_2 : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel2)) ? LL_BDMA_CHANNEL_2 : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel3))  ? LL_BDMA_CHANNEL_3 : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel3)) ? LL_BDMA_CHANNEL_3 : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel4))  ? LL_BDMA_CHANNEL_4 : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel4)) ? LL_BDMA_CHANNEL_4 : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel5))  ? LL_BDMA_CHANNEL_5 : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel5)) ? LL_BDMA_CHANNEL_5 : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel6))  ? LL_BDMA_CHANNEL_6 : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel6)) ? LL_BDMA_CHANNEL_6 : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel7))  ? LL_BDMA_CHANNEL_7 : \

+LL_BDMA_CHANNEL_7)

+#else

+#define __LL_BDMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \

+(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel0)) ? LL_BDMA_CHANNEL_0 : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel1)) ? LL_BDMA_CHANNEL_1 : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel2)) ? LL_BDMA_CHANNEL_2 : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel3)) ? LL_BDMA_CHANNEL_3 : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel4)) ? LL_BDMA_CHANNEL_4 : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel5)) ? LL_BDMA_CHANNEL_5 : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel6)) ? LL_BDMA_CHANNEL_6 : \

+ LL_BDMA_CHANNEL_7)

+#endif /* BDMA1 */

+

+/**

+  * @brief  Convert BDMA Instance BDMAx and LL_BDMA_CHANNEL_y into BDMAx_Channely

+  * @param  __BDMA_INSTANCE__ BDMAx

+  * @param  __CHANNEL__ LL_BDMA_CHANNEL_y

+  * @retval BDMAx_Channely

+  */

+#if defined (BDMA1)

+#define __LL_BDMA_GET_CHANNEL_INSTANCE(__BDMA_INSTANCE__, __CHANNEL__)   \

+((((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA))  && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA_Channel0  : \

+ (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA1_Channel0 : \

+ (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA))  && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA_Channel1  : \

+ (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA1_Channel1 : \

+ (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA))  && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA_Channel2  : \

+ (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA1_Channel2 : \

+ (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA))  && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA_Channel3  : \

+ (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA1_Channel3 : \

+ (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA))  && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA_Channel4  : \

+ (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA1_Channel4 : \

+ (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA))  && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA_Channel5  : \

+ (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA1_Channel5 : \

+ (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA))  && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA_Channel6  : \

+ (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA1_Channel6 : \

+ (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA))  && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_7))) ? BDMA_Channel7  : \

+ BDMA1_Channel7)

+#else

+#define __LL_BDMA_GET_CHANNEL_INSTANCE(__BDMA_INSTANCE__, __CHANNEL__)   \

+((((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA_Channel0 : \

+ (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA_Channel1 : \

+ (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA_Channel2 : \

+ (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA_Channel3 : \

+ (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA_Channel4 : \

+ (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA_Channel5 : \

+ (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA_Channel6 : \

+ BDMA_Channel7)

+#endif /* BDMA1 */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup BDMA_LL_Exported_Functions BDMA Exported Functions

+ * @{

+ */

+

+/** @defgroup BDMA_LL_EF_Configuration Configuration

+  * @{

+  */

+/**

+  * @brief  Enable BDMA channel.

+  * @rmtoll CCR          EN            LL_BDMA_EnableChannel

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_EnableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN);

+}

+

+/**

+  * @brief  Disable BDMA channel.

+  * @rmtoll CCR          EN            LL_BDMA_DisableChannel

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_DisableChannel(BDMA_TypeDef *BDMAx, uint32_t Channel)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN);

+}

+

+/**

+  * @brief  Check if BDMA channel is enabled or disabled.

+  * @rmtoll CCR          EN            LL_BDMA_IsEnabledChannel

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsEnabledChannel(BDMA_TypeDef *BDMAx, uint32_t Channel)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN) == (BDMA_CCR_EN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Configure all parameters link to BDMA transfer.

+  * @rmtoll CCR          DIR           LL_BDMA_ConfigTransfer\n

+  *         CCR          MEM2MEM       LL_BDMA_ConfigTransfer\n

+  *         CCR          CIRC          LL_BDMA_ConfigTransfer\n

+  *         CCR          PINC          LL_BDMA_ConfigTransfer\n

+  *         CCR          MINC          LL_BDMA_ConfigTransfer\n

+  *         CCR          PSIZE         LL_BDMA_ConfigTransfer\n

+  *         CCR          MSIZE         LL_BDMA_ConfigTransfer\n

+  *         CCR          PL            LL_BDMA_ConfigTransfer

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @param  Configuration This parameter must be a combination of all the following values:

+  *         @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY

+  *         @arg @ref LL_BDMA_MODE_NORMAL or @ref LL_BDMA_MODE_CIRCULAR

+  *         @arg @ref LL_BDMA_PERIPH_INCREMENT or @ref LL_BDMA_PERIPH_NOINCREMENT

+  *         @arg @ref LL_BDMA_MEMORY_INCREMENT or @ref LL_BDMA_MEMORY_NOINCREMENT

+  *         @arg @ref LL_BDMA_PDATAALIGN_BYTE or @ref LL_BDMA_PDATAALIGN_HALFWORD or @ref LL_BDMA_PDATAALIGN_WORD

+  *         @arg @ref LL_BDMA_MDATAALIGN_BYTE or @ref LL_BDMA_MDATAALIGN_HALFWORD or @ref LL_BDMA_MDATAALIGN_WORD

+  *         @arg @ref LL_BDMA_PRIORITY_LOW or @ref LL_BDMA_PRIORITY_MEDIUM or @ref LL_BDMA_PRIORITY_HIGH or @ref LL_BDMA_PRIORITY_VERYHIGH

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ConfigTransfer(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Configuration)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,

+             BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_CIRC | BDMA_CCR_PINC | BDMA_CCR_MINC | BDMA_CCR_PSIZE | BDMA_CCR_MSIZE | BDMA_CCR_PL,

+             Configuration);

+}

+

+/**

+  * @brief  Set Data transfer direction (read from peripheral or from memory).

+  * @rmtoll CCR          DIR           LL_BDMA_SetDataTransferDirection\n

+  *         CCR          MEM2MEM       LL_BDMA_SetDataTransferDirection

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @param  Direction This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY

+  *         @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH

+  *         @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_SetDataTransferDirection(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Direction)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,

+             BDMA_CCR_DIR | BDMA_CCR_MEM2MEM, Direction);

+}

+

+/**

+  * @brief  Get Data transfer direction (read from peripheral or from memory).

+  * @rmtoll CCR          DIR           LL_BDMA_GetDataTransferDirection\n

+  *         CCR          MEM2MEM       LL_BDMA_GetDataTransferDirection

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY

+  *         @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH

+  *         @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY

+  */

+__STATIC_INLINE uint32_t LL_BDMA_GetDataTransferDirection(BDMA_TypeDef *BDMAx, uint32_t Channel)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,

+                   BDMA_CCR_DIR | BDMA_CCR_MEM2MEM));

+}

+

+/**

+  * @brief  Set BDMA mode circular or normal.

+  * @note The circular buffer mode cannot be used if the memory-to-memory

+  * data transfer is configured on the selected Channel.

+  * @rmtoll CCR          CIRC          LL_BDMA_SetMode

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @param  Mode This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_MODE_NORMAL

+  *         @arg @ref LL_BDMA_MODE_CIRCULAR

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_SetMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Mode)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CIRC,

+             Mode);

+}

+

+/**

+  * @brief  Get BDMA mode circular or normal.

+  * @rmtoll CCR          CIRC          LL_BDMA_GetMode

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_BDMA_MODE_NORMAL

+  *         @arg @ref LL_BDMA_MODE_CIRCULAR

+  */

+__STATIC_INLINE uint32_t LL_BDMA_GetMode(BDMA_TypeDef *BDMAx, uint32_t Channel)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,

+                   BDMA_CCR_CIRC));

+}

+

+/**

+  * @brief  Set Peripheral increment mode.

+  * @rmtoll CCR          PINC          LL_BDMA_SetPeriphIncMode

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @param  PeriphOrM2MSrcIncMode This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_PERIPH_INCREMENT

+  *         @arg @ref LL_BDMA_PERIPH_NOINCREMENT

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_SetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PINC,

+             PeriphOrM2MSrcIncMode);

+}

+

+/**

+  * @brief  Get Peripheral increment mode.

+  * @rmtoll CCR          PINC          LL_BDMA_GetPeriphIncMode

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_BDMA_PERIPH_INCREMENT

+  *         @arg @ref LL_BDMA_PERIPH_NOINCREMENT

+  */

+__STATIC_INLINE uint32_t LL_BDMA_GetPeriphIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,

+                   BDMA_CCR_PINC));

+}

+

+/**

+  * @brief  Set Memory increment mode.

+  * @rmtoll CCR          MINC          LL_BDMA_SetMemoryIncMode

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @param  MemoryOrM2MDstIncMode This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_MEMORY_INCREMENT

+  *         @arg @ref LL_BDMA_MEMORY_NOINCREMENT

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_SetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_MINC,

+             MemoryOrM2MDstIncMode);

+}

+

+/**

+  * @brief  Get Memory increment mode.

+  * @rmtoll CCR          MINC          LL_BDMA_GetMemoryIncMode

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_BDMA_MEMORY_INCREMENT

+  *         @arg @ref LL_BDMA_MEMORY_NOINCREMENT

+  */

+__STATIC_INLINE uint32_t LL_BDMA_GetMemoryIncMode(BDMA_TypeDef *BDMAx, uint32_t Channel)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,

+                   BDMA_CCR_MINC));

+}

+

+/**

+  * @brief  Set Peripheral size.

+  * @rmtoll CCR          PSIZE         LL_BDMA_SetPeriphSize

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @param  PeriphOrM2MSrcDataSize This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_PDATAALIGN_BYTE

+  *         @arg @ref LL_BDMA_PDATAALIGN_HALFWORD

+  *         @arg @ref LL_BDMA_PDATAALIGN_WORD

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_SetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PSIZE,

+             PeriphOrM2MSrcDataSize);

+}

+

+/**

+  * @brief  Get Peripheral size.

+  * @rmtoll CCR          PSIZE         LL_BDMA_GetPeriphSize

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_BDMA_PDATAALIGN_BYTE

+  *         @arg @ref LL_BDMA_PDATAALIGN_HALFWORD

+  *         @arg @ref LL_BDMA_PDATAALIGN_WORD

+  */

+__STATIC_INLINE uint32_t LL_BDMA_GetPeriphSize(BDMA_TypeDef *BDMAx, uint32_t Channel)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,

+                   BDMA_CCR_PSIZE));

+}

+

+/**

+  * @brief  Set Memory size.

+  * @rmtoll CCR          MSIZE         LL_BDMA_SetMemorySize

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @param  MemoryOrM2MDstDataSize This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_MDATAALIGN_BYTE

+  *         @arg @ref LL_BDMA_MDATAALIGN_HALFWORD

+  *         @arg @ref LL_BDMA_MDATAALIGN_WORD

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_SetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_MSIZE,

+             MemoryOrM2MDstDataSize);

+}

+

+/**

+  * @brief  Get Memory size.

+  * @rmtoll CCR          MSIZE         LL_BDMA_GetMemorySize

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_BDMA_MDATAALIGN_BYTE

+  *         @arg @ref LL_BDMA_MDATAALIGN_HALFWORD

+  *         @arg @ref LL_BDMA_MDATAALIGN_WORD

+  */

+__STATIC_INLINE uint32_t LL_BDMA_GetMemorySize(BDMA_TypeDef *BDMAx, uint32_t Channel)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,

+                   BDMA_CCR_MSIZE));

+}

+

+/**

+  * @brief  Set Channel priority level.

+  * @rmtoll CCR          PL            LL_BDMA_SetChannelPriorityLevel

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @param  Priority This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_PRIORITY_LOW

+  *         @arg @ref LL_BDMA_PRIORITY_MEDIUM

+  *         @arg @ref LL_BDMA_PRIORITY_HIGH

+  *         @arg @ref LL_BDMA_PRIORITY_VERYHIGH

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_SetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Priority)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PL,

+             Priority);

+}

+

+/**

+  * @brief  Get Channel priority level.

+  * @rmtoll CCR          PL            LL_BDMA_GetChannelPriorityLevel

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_BDMA_PRIORITY_LOW

+  *         @arg @ref LL_BDMA_PRIORITY_MEDIUM

+  *         @arg @ref LL_BDMA_PRIORITY_HIGH

+  *         @arg @ref LL_BDMA_PRIORITY_VERYHIGH

+  */

+__STATIC_INLINE uint32_t LL_BDMA_GetChannelPriorityLevel(BDMA_TypeDef *BDMAx, uint32_t Channel)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,

+                   BDMA_CCR_PL));

+}

+

+/**

+  * @brief  Set Number of data to transfer.

+  * @note   This action has no effect if

+  *         channel is enabled.

+  * @rmtoll CNDTR        NDT           LL_BDMA_SetDataLength

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @param  NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_SetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t NbData)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CNDTR,

+             BDMA_CNDTR_NDT, NbData);

+}

+

+/**

+  * @brief  Get Number of data to transfer.

+  * @note   Once the channel is enabled, the return value indicate the

+  *         remaining bytes to be transmitted.

+  * @rmtoll CNDTR        NDT           LL_BDMA_GetDataLength

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

+  */

+__STATIC_INLINE uint32_t LL_BDMA_GetDataLength(BDMA_TypeDef *BDMAx, uint32_t Channel)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CNDTR,

+                   BDMA_CNDTR_NDT));

+}

+

+/**

+  * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.

+  * @rmtoll CR          CT           LL_BDMA_SetCurrentTargetMem

+  * @param  BDMAx BDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @param CurrentMemory This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CURRENTTARGETMEM0

+  *         @arg @ref LL_BDMA_CURRENTTARGETMEM1

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_SetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t CurrentMemory)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CT, CurrentMemory);

+}

+

+/**

+  * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.

+  * @rmtoll CR          CT           LL_BDMA_GetCurrentTargetMem

+  * @param  BDMAx BDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_BDMA_CURRENTTARGETMEM0

+  *         @arg @ref LL_BDMA_CURRENTTARGETMEM1

+  */

+__STATIC_INLINE uint32_t LL_BDMA_GetCurrentTargetMem(BDMA_TypeDef *BDMAx, uint32_t Channel)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CT));

+}

+

+/**

+  * @brief Enable the double buffer mode.

+  * @rmtoll CR          DBM           LL_BDMA_EnableDoubleBufferMode

+  * @param  BDMAx BDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_EnableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_DBM);

+}

+

+/**

+  * @brief Disable the double buffer mode.

+  * @rmtoll CR          DBM           LL_BDMA_DisableDoubleBufferMode

+  * @param  BDMAx BDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_DisableDoubleBufferMode(BDMA_TypeDef *BDMAx, uint32_t Channel)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_DBM);

+}

+

+/**

+  * @brief  Configure the Source and Destination addresses.

+  * @note   This API must not be called when the BDMA channel is enabled.

+  * @note   Each IP using BDMA provides an API to get directly the register adress (LL_PPP_BDMA_GetRegAddr).

+  * @rmtoll CPAR         PA            LL_BDMA_ConfigAddresses\n

+  *         CMAR         MA            LL_BDMA_ConfigAddresses

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @param  SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

+  * @param  DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

+  * @param  Direction This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY

+  *         @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH

+  *         @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ConfigAddresses(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t SrcAddress,

+                                             uint32_t DstAddress, uint32_t Direction)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  /* Direction Memory to Periph */

+  if (Direction == LL_BDMA_DIRECTION_MEMORY_TO_PERIPH)

+  {

+    WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, SrcAddress);

+    WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, DstAddress);

+  }

+  /* Direction Periph to Memory and Memory to Memory */

+  else

+  {

+    WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, SrcAddress);

+    WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, DstAddress);

+  }

+}

+

+/**

+  * @brief  Set the Memory address.

+  * @note   Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only.

+  * @note   This API must not be called when the BDMA channel is enabled.

+  * @rmtoll CMAR         MA            LL_BDMA_SetMemoryAddress

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_SetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, MemoryAddress);

+}

+

+/**

+  * @brief  Set the Peripheral address.

+  * @note   Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only.

+  * @note   This API must not be called when the BDMA channel is enabled.

+  * @rmtoll CPAR         PA            LL_BDMA_SetPeriphAddress

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @param  PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_SetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphAddress)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, PeriphAddress);

+}

+

+/**

+  * @brief  Get Memory address.

+  * @note   Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only.

+  * @rmtoll CMAR         MA            LL_BDMA_GetMemoryAddress

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

+  */

+__STATIC_INLINE uint32_t LL_BDMA_GetMemoryAddress(BDMA_TypeDef *BDMAx, uint32_t Channel)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR));

+}

+

+/**

+  * @brief  Get Peripheral address.

+  * @note   Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only.

+  * @rmtoll CPAR         PA            LL_BDMA_GetPeriphAddress

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

+  */

+__STATIC_INLINE uint32_t LL_BDMA_GetPeriphAddress(BDMA_TypeDef *BDMAx, uint32_t Channel)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR));

+}

+

+/**

+  * @brief  Set the Memory to Memory Source address.

+  * @note   Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only.

+  * @note   This API must not be called when the BDMA channel is enabled.

+  * @rmtoll CPAR         PA            LL_BDMA_SetM2MSrcAddress

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_SetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, MemoryAddress);

+}

+

+/**

+  * @brief  Set the Memory to Memory Destination address.

+  * @note   Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only.

+  * @note   This API must not be called when the BDMA channel is enabled.

+  * @rmtoll CMAR         MA            LL_BDMA_SetM2MDstAddress

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @param  MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_SetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, MemoryAddress);

+}

+

+/**

+  * @brief  Get the Memory to Memory Source address.

+  * @note   Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only.

+  * @rmtoll CPAR         PA            LL_BDMA_GetM2MSrcAddress

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

+  */

+__STATIC_INLINE uint32_t LL_BDMA_GetM2MSrcAddress(BDMA_TypeDef *BDMAx, uint32_t Channel)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR));

+}

+

+/**

+  * @brief  Get the Memory to Memory Destination address.

+  * @note   Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only.

+  * @rmtoll CMAR         MA            LL_BDMA_GetM2MDstAddress

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

+  */

+__STATIC_INLINE uint32_t LL_BDMA_GetM2MDstAddress(BDMA_TypeDef *BDMAx, uint32_t Channel)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR));

+}

+

+/**

+  * @brief Set Memory 1 address (used in case of Double buffer mode).

+  * @rmtoll M1AR        M1A         LL_BDMA_SetMemory1Address

+  * @param  BDMAx BDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @param  Address Between 0 to 0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_SetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Address)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM1AR, BDMA_CM1AR_MA, Address);

+}

+

+/**

+  * @brief Get Memory 1 address (used in case of Double buffer mode).

+  * @rmtoll M1AR        M1A         LL_BDMA_GetMemory1Address

+  * @param  BDMAx BDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @retval Between 0 to 0xFFFFFFFF

+  */

+__STATIC_INLINE uint32_t LL_BDMA_GetMemory1Address(BDMA_TypeDef *BDMAx, uint32_t Channel)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  return (((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM1AR);

+}

+

+/**

+  * @brief  Set BDMA request for BDMA Channels on DMAMUX Channel x.

+  * @note   DMAMUX2 channel 0 to 7 are mapped to BDMA channel 0 to 7.

+  * @rmtoll CxCR         DMAREQ_ID     LL_BDMA_SetPeriphRequest

+  * @param  BDMAx BDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @param  Request This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX2_REQ_MEM2MEM

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR0

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR1

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR2

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR3

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR4

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR5

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR6

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR7

+  *         @arg @ref LL_DMAMUX2_REQ_LPUART1_RX

+  *         @arg @ref LL_DMAMUX2_REQ_LPUART1_TX

+  *         @arg @ref LL_DMAMUX2_REQ_SPI6_RX

+  *         @arg @ref LL_DMAMUX2_REQ_SPI6_TX

+  *         @arg @ref LL_DMAMUX2_REQ_I2C4_RX

+  *         @arg @ref LL_DMAMUX2_REQ_I2C4_TX

+  *         @arg @ref LL_DMAMUX2_REQ_SAI4_A (*)

+  *         @arg @ref LL_DMAMUX2_REQ_SAI4_B (*)

+  *         @arg @ref LL_DMAMUX2_REQ_ADC3 (*)

+  *         @arg @ref LL_DMAMUX2_REQ_DAC3 (*)

+  *         @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*)

+  * @note   (*) Availability depends on devices.

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_SetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Request)

+{

+  UNUSED(BDMAx);

+  MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX2_Channel0 + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);

+}

+

+/**

+  * @brief  Get BDMA request for BDMA Channels on DMAMUX Channel x.

+  * @note   DMAMUX channel 0 to 7 are mapped to BDMA channel 0 to 7.

+  * @rmtoll CxCR         DMAREQ_ID     LL_BDMA_GetPeriphRequest

+  * @param  BDMAx BDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMAMUX2_REQ_MEM2MEM

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR0

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR1

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR2

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR3

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR4

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR5

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR6

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR7

+  *         @arg @ref LL_DMAMUX2_REQ_LPUART1_RX

+  *         @arg @ref LL_DMAMUX2_REQ_LPUART1_TX

+  *         @arg @ref LL_DMAMUX2_REQ_SPI6_RX

+  *         @arg @ref LL_DMAMUX2_REQ_SPI6_TX

+  *         @arg @ref LL_DMAMUX2_REQ_I2C4_RX

+  *         @arg @ref LL_DMAMUX2_REQ_I2C4_TX

+  *         @arg @ref LL_DMAMUX2_REQ_SAI4_A (*)

+  *         @arg @ref LL_DMAMUX2_REQ_SAI4_B (*)

+  *         @arg @ref LL_DMAMUX2_REQ_ADC3 (*)

+  *         @arg @ref LL_DMAMUX2_REQ_DAC3 (*)

+  *         @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*)

+  * @note   (*) Availability depends on devices.

+  */

+__STATIC_INLINE uint32_t LL_BDMA_GetPeriphRequest(BDMA_TypeDef *BDMAx, uint32_t Channel)

+{

+  UNUSED(BDMAx);

+  return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX2_Channel0 + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_DMAREQ_ID));

+}

+

+/**

+  * @}

+  */

+

+

+/** @defgroup BDMA_LL_EF_FLAG_Management FLAG_Management

+  * @{

+  */

+/**

+  * @brief  Get Channel 0 global interrupt flag.

+  * @rmtoll ISR          GIF0          LL_BDMA_IsActiveFlag_GI0

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI0(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF0) == (BDMA_ISR_GIF0)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Channel 1 global interrupt flag.

+  * @rmtoll ISR          GIF1          LL_BDMA_IsActiveFlag_GI1

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI1(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF1) == (BDMA_ISR_GIF1)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Channel 2 global interrupt flag.

+  * @rmtoll ISR          GIF2          LL_BDMA_IsActiveFlag_GI2

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI2(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF2) == (BDMA_ISR_GIF2)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Channel 3 global interrupt flag.

+  * @rmtoll ISR          GIF3          LL_BDMA_IsActiveFlag_GI3

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI3(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF3) == (BDMA_ISR_GIF3)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Channel 4 global interrupt flag.

+  * @rmtoll ISR          GIF4          LL_BDMA_IsActiveFlag_GI4

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI4(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF4) == (BDMA_ISR_GIF4)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Channel 5 global interrupt flag.

+  * @rmtoll ISR          GIF5          LL_BDMA_IsActiveFlag_GI5

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI5(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF5) == (BDMA_ISR_GIF5)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Channel 6 global interrupt flag.

+  * @rmtoll ISR          GIF6          LL_BDMA_IsActiveFlag_GI6

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI6(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF6) == (BDMA_ISR_GIF6)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Channel 7 global interrupt flag.

+  * @rmtoll ISR          GIF7          LL_BDMA_IsActiveFlag_GI7

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI7(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF7) == (BDMA_ISR_GIF7)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Channel 0 transfer complete flag.

+  * @rmtoll ISR          TCIF0         LL_BDMA_IsActiveFlag_TC0

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC0(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF0) == (BDMA_ISR_TCIF0)) ? 1UL : 0UL);

+}

+/**

+  * @brief  Get Channel 1 transfer complete flag.

+  * @rmtoll ISR          TCIF1         LL_BDMA_IsActiveFlag_TC1

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC1(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF1) == (BDMA_ISR_TCIF1)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Channel 2 transfer complete flag.

+  * @rmtoll ISR          TCIF2         LL_BDMA_IsActiveFlag_TC2

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC2(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF2) == (BDMA_ISR_TCIF2)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Channel 3 transfer complete flag.

+  * @rmtoll ISR          TCIF3         LL_BDMA_IsActiveFlag_TC3

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC3(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF3) == (BDMA_ISR_TCIF3)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Channel 4 transfer complete flag.

+  * @rmtoll ISR          TCIF4         LL_BDMA_IsActiveFlag_TC4

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC4(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF4) == (BDMA_ISR_TCIF4)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Channel 5 transfer complete flag.

+  * @rmtoll ISR          TCIF5         LL_BDMA_IsActiveFlag_TC5

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC5(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF5) == (BDMA_ISR_TCIF5)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Channel 6 transfer complete flag.

+  * @rmtoll ISR          TCIF6         LL_BDMA_IsActiveFlag_TC6

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC6(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF6) == (BDMA_ISR_TCIF6)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Channel 7 transfer complete flag.

+  * @rmtoll ISR          TCIF7         LL_BDMA_IsActiveFlag_TC7

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC7(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF7) == (BDMA_ISR_TCIF7)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Channel 0 half transfer flag.

+  * @rmtoll ISR          HTIF0         LL_BDMA_IsActiveFlag_HT0

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT0(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF0) == (BDMA_ISR_HTIF0)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Channel 1 half transfer flag.

+  * @rmtoll ISR          HTIF1         LL_BDMA_IsActiveFlag_HT1

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT1(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF1) == (BDMA_ISR_HTIF1)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Channel 2 half transfer flag.

+  * @rmtoll ISR          HTIF2         LL_BDMA_IsActiveFlag_HT2

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT2(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF2) == (BDMA_ISR_HTIF2)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Channel 3 half transfer flag.

+  * @rmtoll ISR          HTIF3         LL_BDMA_IsActiveFlag_HT3

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT3(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF3) == (BDMA_ISR_HTIF3)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Channel 4 half transfer flag.

+  * @rmtoll ISR          HTIF4         LL_BDMA_IsActiveFlag_HT4

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT4(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF4) == (BDMA_ISR_HTIF4)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Channel 5 half transfer flag.

+  * @rmtoll ISR          HTIF5         LL_BDMA_IsActiveFlag_HT5

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT5(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF5) == (BDMA_ISR_HTIF5)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Channel 6 half transfer flag.

+  * @rmtoll ISR          HTIF6         LL_BDMA_IsActiveFlag_HT6

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT6(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF6) == (BDMA_ISR_HTIF6)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Channel 7 half transfer flag.

+  * @rmtoll ISR          HTIF7         LL_BDMA_IsActiveFlag_HT7

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT7(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF7) == (BDMA_ISR_HTIF7)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Channel 0 transfer error flag.

+  * @rmtoll ISR          TEIF0         LL_BDMA_IsActiveFlag_TE0

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE0(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF0) == (BDMA_ISR_TEIF0)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Channel 1 transfer error flag.

+  * @rmtoll ISR          TEIF1         LL_BDMA_IsActiveFlag_TE1

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE1(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF1) == (BDMA_ISR_TEIF1)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Channel 2 transfer error flag.

+  * @rmtoll ISR          TEIF2         LL_BDMA_IsActiveFlag_TE2

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE2(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF2) == (BDMA_ISR_TEIF2)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Channel 3 transfer error flag.

+  * @rmtoll ISR          TEIF3         LL_BDMA_IsActiveFlag_TE3

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE3(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF3) == (BDMA_ISR_TEIF3)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Channel 4 transfer error flag.

+  * @rmtoll ISR          TEIF4         LL_BDMA_IsActiveFlag_TE4

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE4(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF4) == (BDMA_ISR_TEIF4)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Channel 5 transfer error flag.

+  * @rmtoll ISR          TEIF5         LL_BDMA_IsActiveFlag_TE5

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE5(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF5) == (BDMA_ISR_TEIF5)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Channel 6 transfer error flag.

+  * @rmtoll ISR          TEIF6         LL_BDMA_IsActiveFlag_TE6

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE6(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF6) == (BDMA_ISR_TEIF6)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Channel 7 transfer error flag.

+  * @rmtoll ISR          TEIF7         LL_BDMA_IsActiveFlag_TE7

+  * @param  BDMAx BDMA Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE7(BDMA_TypeDef *BDMAx)

+{

+  return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF7) == (BDMA_ISR_TEIF7)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear Channel 0 global interrupt flag.

+  * @rmtoll IFCR         CGIF0         LL_BDMA_ClearFlag_GI0

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_GI0(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF0);

+}

+

+/**

+  * @brief  Clear Channel 1 global interrupt flag.

+  * @rmtoll IFCR         CGIF1         LL_BDMA_ClearFlag_GI1

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_GI1(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF1);

+}

+

+/**

+  * @brief  Clear Channel 2 global interrupt flag.

+  * @rmtoll IFCR         CGIF2         LL_BDMA_ClearFlag_GI2

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_GI2(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF2);

+}

+

+/**

+  * @brief  Clear Channel 3 global interrupt flag.

+  * @rmtoll IFCR         CGIF3         LL_BDMA_ClearFlag_GI3

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_GI3(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF3);

+}

+

+/**

+  * @brief  Clear Channel 4 global interrupt flag.

+  * @rmtoll IFCR         CGIF4         LL_BDMA_ClearFlag_GI4

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_GI4(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF4);

+}

+

+/**

+  * @brief  Clear Channel 5 global interrupt flag.

+  * @rmtoll IFCR         CGIF5         LL_BDMA_ClearFlag_GI5

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_GI5(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF5);

+}

+

+/**

+  * @brief  Clear Channel 6 global interrupt flag.

+  * @rmtoll IFCR         CGIF6         LL_BDMA_ClearFlag_GI6

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_GI6(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF6);

+}

+

+/**

+  * @brief  Clear Channel 7 global interrupt flag.

+  * @rmtoll IFCR         CGIF7         LL_BDMA_ClearFlag_GI7

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_GI7(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF7);

+}

+

+/**

+  * @brief  Clear Channel 0  transfer complete flag.

+  * @rmtoll IFCR         CTCIF0        LL_BDMA_ClearFlag_TC0

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_TC0(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF0);

+}

+

+/**

+  * @brief  Clear Channel 1  transfer complete flag.

+  * @rmtoll IFCR         CTCIF1        LL_BDMA_ClearFlag_TC1

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_TC1(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF1);

+}

+

+/**

+  * @brief  Clear Channel 2  transfer complete flag.

+  * @rmtoll IFCR         CTCIF2        LL_BDMA_ClearFlag_TC2

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_TC2(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF2);

+}

+

+/**

+  * @brief  Clear Channel 3  transfer complete flag.

+  * @rmtoll IFCR         CTCIF3        LL_BDMA_ClearFlag_TC3

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_TC3(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF3);

+}

+

+/**

+  * @brief  Clear Channel 4  transfer complete flag.

+  * @rmtoll IFCR         CTCIF4        LL_BDMA_ClearFlag_TC4

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_TC4(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF4);

+}

+

+/**

+  * @brief  Clear Channel 5  transfer complete flag.

+  * @rmtoll IFCR         CTCIF5        LL_BDMA_ClearFlag_TC5

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_TC5(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF5);

+}

+

+/**

+  * @brief  Clear Channel 6  transfer complete flag.

+  * @rmtoll IFCR         CTCIF6        LL_BDMA_ClearFlag_TC6

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_TC6(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF6);

+}

+

+/**

+  * @brief  Clear Channel 7  transfer complete flag.

+  * @rmtoll IFCR         CTCIF7        LL_BDMA_ClearFlag_TC7

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_TC7(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF7);

+}

+

+/**

+  * @brief  Clear Channel 0  half transfer flag.

+  * @rmtoll IFCR         CHTIF0        LL_BDMA_ClearFlag_HT0

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_HT0(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF0);

+}

+

+/**

+  * @brief  Clear Channel 1  half transfer flag.

+  * @rmtoll IFCR         CHTIF1        LL_BDMA_ClearFlag_HT1

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_HT1(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF1);

+}

+

+/**

+  * @brief  Clear Channel 2  half transfer flag.

+  * @rmtoll IFCR         CHTIF2        LL_BDMA_ClearFlag_HT2

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_HT2(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF2);

+}

+

+/**

+  * @brief  Clear Channel 3  half transfer flag.

+  * @rmtoll IFCR         CHTIF3        LL_BDMA_ClearFlag_HT3

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_HT3(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF3);

+}

+

+/**

+  * @brief  Clear Channel 4  half transfer flag.

+  * @rmtoll IFCR         CHTIF4        LL_BDMA_ClearFlag_HT4

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_HT4(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF4);

+}

+

+/**

+  * @brief  Clear Channel 5  half transfer flag.

+  * @rmtoll IFCR         CHTIF5        LL_BDMA_ClearFlag_HT5

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_HT5(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF5);

+}

+

+/**

+  * @brief  Clear Channel 6  half transfer flag.

+  * @rmtoll IFCR         CHTIF6        LL_BDMA_ClearFlag_HT6

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_HT6(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF6);

+}

+

+/**

+  * @brief  Clear Channel 7  half transfer flag.

+  * @rmtoll IFCR         CHTIF7        LL_BDMA_ClearFlag_HT7

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_HT7(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF7);

+}

+

+/**

+  * @brief  Clear Channel 0 transfer error flag.

+  * @rmtoll IFCR         CTEIF0        LL_BDMA_ClearFlag_TE0

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_TE0(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF0);

+}

+

+/**

+  * @brief  Clear Channel 1 transfer error flag.

+  * @rmtoll IFCR         CTEIF1        LL_BDMA_ClearFlag_TE1

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_TE1(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF1);

+}

+

+/**

+  * @brief  Clear Channel 2 transfer error flag.

+  * @rmtoll IFCR         CTEIF2        LL_BDMA_ClearFlag_TE2

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_TE2(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF2);

+}

+

+/**

+  * @brief  Clear Channel 3 transfer error flag.

+  * @rmtoll IFCR         CTEIF3        LL_BDMA_ClearFlag_TE3

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_TE3(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF3);

+}

+

+/**

+  * @brief  Clear Channel 4 transfer error flag.

+  * @rmtoll IFCR         CTEIF4        LL_BDMA_ClearFlag_TE4

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_TE4(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF4);

+}

+

+/**

+  * @brief  Clear Channel 5 transfer error flag.

+  * @rmtoll IFCR         CTEIF5        LL_BDMA_ClearFlag_TE5

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_TE5(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF5);

+}

+

+/**

+  * @brief  Clear Channel 6 transfer error flag.

+  * @rmtoll IFCR         CTEIF6        LL_BDMA_ClearFlag_TE6

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_TE6(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF6);

+}

+

+/**

+  * @brief  Clear Channel 7 transfer error flag.

+  * @rmtoll IFCR         CTEIF7        LL_BDMA_ClearFlag_TE7

+  * @param  BDMAx BDMA Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_ClearFlag_TE7(BDMA_TypeDef *BDMAx)

+{

+  WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF7);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup BDMA_LL_EF_IT_Management IT_Management

+  * @{

+  */

+/**

+  * @brief  Enable Transfer complete interrupt.

+  * @rmtoll CCR          TCIE          LL_BDMA_EnableIT_TC

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_EnableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE);

+}

+

+/**

+  * @brief  Enable Half transfer interrupt.

+  * @rmtoll CCR          HTIE          LL_BDMA_EnableIT_HT

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_EnableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE);

+}

+

+/**

+  * @brief  Enable Transfer error interrupt.

+  * @rmtoll CCR          TEIE          LL_BDMA_EnableIT_TE

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_EnableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE);

+}

+

+/**

+  * @brief  Disable Transfer complete interrupt.

+  * @rmtoll CCR          TCIE          LL_BDMA_DisableIT_TC

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_DisableIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE);

+}

+

+/**

+  * @brief  Disable Half transfer interrupt.

+  * @rmtoll CCR          HTIE          LL_BDMA_DisableIT_HT

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_DisableIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE);

+}

+

+/**

+  * @brief  Disable Transfer error interrupt.

+  * @rmtoll CCR          TEIE          LL_BDMA_DisableIT_TE

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_BDMA_DisableIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE);

+}

+

+/**

+  * @brief  Check if Transfer complete Interrupt is enabled.

+  * @rmtoll CCR          TCIE          LL_BDMA_IsEnabledIT_TC

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TC(BDMA_TypeDef *BDMAx, uint32_t Channel)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE) == (BDMA_CCR_TCIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if Half transfer Interrupt is enabled.

+  * @rmtoll CCR          HTIE          LL_BDMA_IsEnabledIT_HT

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_HT(BDMA_TypeDef *BDMAx, uint32_t Channel)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE) == (BDMA_CCR_HTIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if Transfer error Interrupt is enabled.

+  * @rmtoll CCR          TEIE          LL_BDMA_IsEnabledIT_TE

+  * @param  BDMAx BDMA Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_BDMA_CHANNEL_0

+  *         @arg @ref LL_BDMA_CHANNEL_1

+  *         @arg @ref LL_BDMA_CHANNEL_2

+  *         @arg @ref LL_BDMA_CHANNEL_3

+  *         @arg @ref LL_BDMA_CHANNEL_4

+  *         @arg @ref LL_BDMA_CHANNEL_5

+  *         @arg @ref LL_BDMA_CHANNEL_6

+  *         @arg @ref LL_BDMA_CHANNEL_7

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TE(BDMA_TypeDef *BDMAx, uint32_t Channel)

+{

+  register uint32_t bdma_base_addr = (uint32_t)BDMAx;

+

+  return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE) == (BDMA_CCR_TEIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup BDMA_LL_EF_Init Initialization and de-initialization functions

+  * @{

+  */

+

+uint32_t LL_BDMA_Init(BDMA_TypeDef *BDMAx, uint32_t Channel, LL_BDMA_InitTypeDef *BDMA_InitStruct);

+uint32_t LL_BDMA_DeInit(BDMA_TypeDef *BDMAx, uint32_t Channel);

+void LL_BDMA_StructInit(LL_BDMA_InitTypeDef *BDMA_InitStruct);

+

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* BDMA || BDMA1 || BDMA2 */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_LL_BDMA_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_bus.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_bus.h
new file mode 100644
index 0000000000..6ee1528aab
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_bus.h
@@ -0,0 +1,6635 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_bus.h

+  * @author  MCD Application Team

+  * @version $VERSION$

+  * @date    $DATE$

+  * @brief   Header file of BUS LL module.

+

+  @verbatim

+                      ##### RCC Limitations #####

+  ==============================================================================

+    [..]

+      A delay between an RCC peripheral clock enable and the effective peripheral

+      enabling should be taken into account in order to manage the peripheral read/write

+      from/to registers.

+      (+) This delay depends on the peripheral mapping.

+        (++) AHB & APB peripherals, 1 dummy read is necessary

+

+    [..]

+      Workarounds:

+      (#) For AHB & APB peripherals, a dummy read to the peripheral register has been

+          inserted in each LL_{BUS}_GRP{x}_EnableClock() function.

+

+  @endverbatim

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_LL_BUS_H

+#define STM32H7xx_LL_BUS_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+#if defined(RCC)

+

+/** @defgroup BUS_LL BUS

+  * @{

+  */

+

+/* Private variables ---------------------------------------------------------*/

+

+/* Private constants ---------------------------------------------------------*/

+

+/* Private macros ------------------------------------------------------------*/

+

+/* Exported types ------------------------------------------------------------*/

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants

+  * @{

+  */

+

+/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH  AHB3 GRP1 PERIPH

+  * @{

+  */

+#define LL_AHB3_GRP1_PERIPH_MDMA           RCC_AHB3ENR_MDMAEN

+#define LL_AHB3_GRP1_PERIPH_DMA2D          RCC_AHB3ENR_DMA2DEN

+

+#if defined(JPEG)

+#define LL_AHB3_GRP1_PERIPH_JPGDEC         RCC_AHB3ENR_JPGDECEN

+#endif /* JPEG */

+

+#define LL_AHB3_GRP1_PERIPH_FMC            RCC_AHB3ENR_FMCEN

+#if defined(QUADSPI)

+#define LL_AHB3_GRP1_PERIPH_QSPI           RCC_AHB3ENR_QSPIEN

+#endif /* QUADSPI */

+#if defined(OCTOSPI1) || defined(OCTOSPI2)

+#define LL_AHB3_GRP1_PERIPH_OSPI1          RCC_AHB3ENR_OSPI1EN

+#define LL_AHB3_GRP1_PERIPH_OSPI2          RCC_AHB3ENR_OSPI2EN

+#endif /*(OCTOSPI1) || (OCTOSPI2)*/

+#if defined(OCTOSPIM)

+#define LL_AHB3_GRP1_PERIPH_OCTOSPIM       RCC_AHB3ENR_IOMNGREN

+#endif /* OCTOSPIM */

+#if defined(OTFDEC1) || defined(OTFDEC2)

+#define LL_AHB3_GRP1_PERIPH_OTFDEC1        RCC_AHB3ENR_OTFDEC1EN

+#define LL_AHB3_GRP1_PERIPH_OTFDEC2        RCC_AHB3ENR_OTFDEC2EN

+#endif /* (OTFDEC1) || (OTFDEC2) */

+#if defined(GFXMMU)

+#define LL_AHB3_GRP1_PERIPH_GFXMMU         RCC_AHB3ENR_GFXMMUEN

+#endif /* GFXMMU */

+#define LL_AHB3_GRP1_PERIPH_SDMMC1         RCC_AHB3ENR_SDMMC1EN

+#define LL_AHB3_GRP1_PERIPH_FLASH          RCC_AHB3LPENR_FLASHLPEN

+#define LL_AHB3_GRP1_PERIPH_DTCM1          RCC_AHB3LPENR_DTCM1LPEN

+#define LL_AHB3_GRP1_PERIPH_DTCM2          RCC_AHB3LPENR_DTCM2LPEN

+#define LL_AHB3_GRP1_PERIPH_ITCM           RCC_AHB3LPENR_ITCMLPEN

+#if defined(RCC_AHB3LPENR_AXISRAMLPEN)

+#define LL_AHB3_GRP1_PERIPH_AXISRAM        RCC_AHB3LPENR_AXISRAMLPEN

+#else

+#define LL_AHB3_GRP1_PERIPH_AXISRAM1       RCC_AHB3LPENR_AXISRAM1LPEN

+#define LL_AHB3_GRP1_PERIPH_AXISRAM        LL_AHB3_GRP1_PERIPH_AXISRAM1   /* for backward compatibility*/

+#endif /* RCC_AHB3LPENR_AXISRAMLPEN */

+#if defined(CD_AXISRAM2_BASE)

+#define LL_AHB3_GRP1_PERIPH_AXISRAM2       RCC_AHB3LPENR_AXISRAM2LPEN

+#endif /* CD_AXISRAM2_BASE */

+#if defined(CD_AXISRAM3_BASE)

+#define LL_AHB3_GRP1_PERIPH_AXISRAM3       RCC_AHB3LPENR_AXISRAM3LPEN

+#endif /* CD_AXISRAM3_BASE */

+/**

+  * @}

+  */

+

+

+/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH  AHB1 GRP1 PERIPH

+  * @{

+  */

+#define LL_AHB1_GRP1_PERIPH_DMA1           RCC_AHB1ENR_DMA1EN

+#define LL_AHB1_GRP1_PERIPH_DMA2           RCC_AHB1ENR_DMA2EN

+#define LL_AHB1_GRP1_PERIPH_ADC12          RCC_AHB1ENR_ADC12EN

+#if defined(DUAL_CORE)

+#define LL_AHB1_GRP1_PERIPH_ART            RCC_AHB1ENR_ARTEN

+#endif /* DUAL_CORE */

+#if defined(RCC_AHB1ENR_CRCEN)

+#define LL_AHB1_GRP1_PERIPH_CRC            RCC_AHB1ENR_CRCEN

+#endif /* RCC_AHB1ENR_CRCEN */

+#if defined(ETH)

+#define LL_AHB1_GRP1_PERIPH_ETH1MAC        RCC_AHB1ENR_ETH1MACEN

+#define LL_AHB1_GRP1_PERIPH_ETH1TX         RCC_AHB1ENR_ETH1TXEN

+#define LL_AHB1_GRP1_PERIPH_ETH1RX         RCC_AHB1ENR_ETH1RXEN

+#endif /* ETH */

+#define LL_AHB1_GRP1_PERIPH_USB1OTGHS      RCC_AHB1ENR_USB1OTGHSEN

+#define LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI  RCC_AHB1ENR_USB1OTGHSULPIEN

+#if defined(USB2_OTG_FS)

+#define LL_AHB1_GRP1_PERIPH_USB2OTGHS      RCC_AHB1ENR_USB2OTGHSEN

+#define LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI  RCC_AHB1ENR_USB2OTGHSULPIEN

+#endif /* USB2_OTG_FS */

+/**

+  * @}

+  */

+

+

+/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH  AHB2 GRP1 PERIPH

+  * @{

+  */

+#define LL_AHB2_GRP1_PERIPH_DCMI           RCC_AHB2ENR_DCMIEN

+#if defined(HSEM) && defined(RCC_AHB2ENR_HSEMEN)

+#define LL_AHB2_GRP1_PERIPH_HSEM           RCC_AHB2ENR_HSEMEN

+#endif /* HSEM && RCC_AHB2ENR_HSEMEN */

+#if defined(CRYP)

+#define LL_AHB2_GRP1_PERIPH_CRYP           RCC_AHB2ENR_CRYPEN

+#endif /* CRYP */

+#if defined(HASH)

+#define LL_AHB2_GRP1_PERIPH_HASH           RCC_AHB2ENR_HASHEN

+#endif /* HASH */

+#define LL_AHB2_GRP1_PERIPH_RNG            RCC_AHB2ENR_RNGEN

+#define LL_AHB2_GRP1_PERIPH_SDMMC2         RCC_AHB2ENR_SDMMC2EN

+#if defined(BDMA1)

+#define LL_AHB2_GRP1_PERIPH_BDMA1          RCC_AHB2ENR_BDMA1EN

+#endif /* BDMA1 */

+#if defined(RCC_AHB2ENR_D2SRAM1EN)

+#define LL_AHB2_GRP1_PERIPH_D2SRAM1        RCC_AHB2ENR_D2SRAM1EN

+#else

+#define LL_AHB2_GRP1_PERIPH_AHBSRAM1       RCC_AHB2ENR_AHBSRAM1EN

+#define LL_AHB2_GRP1_PERIPH_D2SRAM1        LL_AHB2_GRP1_PERIPH_AHBSRAM1    /* for backward compatibility*/

+#endif /* RCC_AHB2ENR_D2SRAM1EN */

+#if defined(RCC_AHB2ENR_D2SRAM2EN)

+#define LL_AHB2_GRP1_PERIPH_D2SRAM2        RCC_AHB2ENR_D2SRAM2EN

+#else

+#define LL_AHB2_GRP1_PERIPH_AHBSRAM2       RCC_AHB2ENR_AHBSRAM2EN

+#define LL_AHB2_GRP1_PERIPH_D2SRAM2        LL_AHB2_GRP1_PERIPH_AHBSRAM2    /* for backward compatibility*/

+#endif /* RCC_AHB2ENR_D2SRAM2EN */

+#if defined(RCC_AHB2ENR_D2SRAM3EN)

+#define LL_AHB2_GRP1_PERIPH_D2SRAM3        RCC_AHB2ENR_D2SRAM3EN

+#endif /* RCC_AHB2ENR_D2SRAM3EN */

+/**

+  * @}

+  */

+

+

+/** @defgroup BUS_LL_EC_AHB4_GRP1_PERIPH  AHB4 GRP1 PERIPH

+  * @{

+  */

+#define LL_AHB4_GRP1_PERIPH_GPIOA          RCC_AHB4ENR_GPIOAEN

+#define LL_AHB4_GRP1_PERIPH_GPIOB          RCC_AHB4ENR_GPIOBEN

+#define LL_AHB4_GRP1_PERIPH_GPIOC          RCC_AHB4ENR_GPIOCEN

+#define LL_AHB4_GRP1_PERIPH_GPIOD          RCC_AHB4ENR_GPIODEN

+#define LL_AHB4_GRP1_PERIPH_GPIOE          RCC_AHB4ENR_GPIOEEN

+#define LL_AHB4_GRP1_PERIPH_GPIOF          RCC_AHB4ENR_GPIOFEN

+#define LL_AHB4_GRP1_PERIPH_GPIOG          RCC_AHB4ENR_GPIOGEN

+#define LL_AHB4_GRP1_PERIPH_GPIOH          RCC_AHB4ENR_GPIOHEN

+#define LL_AHB4_GRP1_PERIPH_GPIOI          RCC_AHB4ENR_GPIOIEN

+#define LL_AHB4_GRP1_PERIPH_GPIOJ          RCC_AHB4ENR_GPIOJEN

+#define LL_AHB4_GRP1_PERIPH_GPIOK          RCC_AHB4ENR_GPIOKEN

+#if defined(RCC_AHB4ENR_CRCEN)

+#define LL_AHB4_GRP1_PERIPH_CRC            RCC_AHB4ENR_CRCEN

+#endif /* RCC_AHB4ENR_CRCEN */

+#if defined(BDMA2)

+#define LL_AHB4_GRP1_PERIPH_BDMA2          RCC_AHB4ENR_BDMA2EN

+#define LL_AHB4_GRP1_PERIPH_BDMA           LL_AHB4_GRP1_PERIPH_BDMA2  /* for backward compatibility*/

+#else

+#define LL_AHB4_GRP1_PERIPH_BDMA           RCC_AHB4ENR_BDMAEN

+#endif /* BDMA2 */

+#if defined(ADC3)

+#define LL_AHB4_GRP1_PERIPH_ADC3           RCC_AHB4ENR_ADC3EN

+#endif /* ADC3 */

+#if defined(HSEM) && defined(RCC_AHB4ENR_HSEMEN)

+#define LL_AHB4_GRP1_PERIPH_HSEM           RCC_AHB4ENR_HSEMEN

+#endif /* HSEM && RCC_AHB4ENR_HSEMEN*/

+#define LL_AHB4_GRP1_PERIPH_BKPRAM         RCC_AHB4ENR_BKPRAMEN

+#if defined(RCC_AHB4LPENR_SRAM4LPEN)

+#define LL_AHB4_GRP1_PERIPH_SRAM4          RCC_AHB4LPENR_SRAM4LPEN

+#define LL_AHB4_GRP1_PERIPH_D3SRAM1        LL_AHB4_GRP1_PERIPH_SRAM4

+#else

+#define LL_AHB4_GRP1_PERIPH_SRDSRAM        RCC_AHB4ENR_SRDSRAMEN

+#define LL_AHB4_GRP1_PERIPH_SRAM4          LL_AHB4_GRP1_PERIPH_SRDSRAM  /* for backward compatibility*/

+#define LL_AHB4_GRP1_PERIPH_D3SRAM1        LL_AHB4_GRP1_PERIPH_SRDSRAM  /* for backward compatibility*/

+#endif /* RCC_AHB4ENR_D3SRAM1EN */

+/**

+  * @}

+  */

+

+

+/** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH  APB3 GRP1 PERIPH

+  * @{

+  */

+#define LL_APB3_GRP1_PERIPH_LTDC           RCC_APB3ENR_LTDCEN

+#if defined(DSI)

+#define LL_APB3_GRP1_PERIPH_DSI            RCC_APB3ENR_DSIEN

+#endif /* DSI */

+#define LL_APB3_GRP1_PERIPH_WWDG1          RCC_APB3ENR_WWDG1EN

+#if defined(RCC_APB3ENR_WWDGEN)

+#define LL_APB3_GRP1_PERIPH_WWDG           LL_APB3_GRP1_PERIPH_WWDG1   /* for backward compatibility*/

+#endif

+/**

+  * @}

+  */

+

+

+/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH  APB1 GRP1 PERIPH

+  * @{

+  */

+#define LL_APB1_GRP1_PERIPH_TIM2           RCC_APB1LENR_TIM2EN

+#define LL_APB1_GRP1_PERIPH_TIM3           RCC_APB1LENR_TIM3EN

+#define LL_APB1_GRP1_PERIPH_TIM4           RCC_APB1LENR_TIM4EN

+#define LL_APB1_GRP1_PERIPH_TIM5           RCC_APB1LENR_TIM5EN

+#define LL_APB1_GRP1_PERIPH_TIM6           RCC_APB1LENR_TIM6EN

+#define LL_APB1_GRP1_PERIPH_TIM7           RCC_APB1LENR_TIM7EN

+#define LL_APB1_GRP1_PERIPH_TIM12          RCC_APB1LENR_TIM12EN

+#define LL_APB1_GRP1_PERIPH_TIM13          RCC_APB1LENR_TIM13EN

+#define LL_APB1_GRP1_PERIPH_TIM14          RCC_APB1LENR_TIM14EN

+#define LL_APB1_GRP1_PERIPH_LPTIM1         RCC_APB1LENR_LPTIM1EN

+#if defined(DUAL_CORE)

+#define LL_APB1_GRP1_PERIPH_WWDG2          RCC_APB1LENR_WWDG2EN

+#endif /*DUAL_CORE*/

+#define LL_APB1_GRP1_PERIPH_SPI2           RCC_APB1LENR_SPI2EN

+#define LL_APB1_GRP1_PERIPH_SPI3           RCC_APB1LENR_SPI3EN

+#define LL_APB1_GRP1_PERIPH_SPDIFRX        RCC_APB1LENR_SPDIFRXEN

+#define LL_APB1_GRP1_PERIPH_USART2         RCC_APB1LENR_USART2EN

+#define LL_APB1_GRP1_PERIPH_USART3         RCC_APB1LENR_USART3EN

+#define LL_APB1_GRP1_PERIPH_UART4          RCC_APB1LENR_UART4EN

+#define LL_APB1_GRP1_PERIPH_UART5          RCC_APB1LENR_UART5EN

+#define LL_APB1_GRP1_PERIPH_I2C1           RCC_APB1LENR_I2C1EN

+#define LL_APB1_GRP1_PERIPH_I2C2           RCC_APB1LENR_I2C2EN

+#define LL_APB1_GRP1_PERIPH_I2C3           RCC_APB1LENR_I2C3EN

+#define LL_APB1_GRP1_PERIPH_CEC            RCC_APB1LENR_CECEN

+#define LL_APB1_GRP1_PERIPH_DAC12          RCC_APB1LENR_DAC12EN

+#define LL_APB1_GRP1_PERIPH_UART7          RCC_APB1LENR_UART7EN

+#define LL_APB1_GRP1_PERIPH_UART8          RCC_APB1LENR_UART8EN

+/**

+  * @}

+  */

+

+

+/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH  APB1 GRP2 PERIPH

+  * @{

+  */

+#define LL_APB1_GRP2_PERIPH_CRS            RCC_APB1HENR_CRSEN

+#define LL_APB1_GRP2_PERIPH_SWPMI1         RCC_APB1HENR_SWPMIEN

+#define LL_APB1_GRP2_PERIPH_OPAMP          RCC_APB1HENR_OPAMPEN

+#define LL_APB1_GRP2_PERIPH_MDIOS          RCC_APB1HENR_MDIOSEN

+#define LL_APB1_GRP2_PERIPH_FDCAN          RCC_APB1HENR_FDCANEN

+/**

+  * @}

+  */

+

+

+/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH  APB2 GRP1 PERIPH

+  * @{

+  */

+#define LL_APB2_GRP1_PERIPH_TIM1           RCC_APB2ENR_TIM1EN

+#define LL_APB2_GRP1_PERIPH_TIM8           RCC_APB2ENR_TIM8EN

+#define LL_APB2_GRP1_PERIPH_USART1         RCC_APB2ENR_USART1EN

+#define LL_APB2_GRP1_PERIPH_USART6         RCC_APB2ENR_USART6EN

+#if defined(UART9)

+#define LL_APB2_GRP1_PERIPH_UART9          RCC_APB2ENR_UART9EN

+#endif /* UART9 */

+#if defined(USART10)

+#define LL_APB2_GRP1_PERIPH_USART10        RCC_APB2ENR_USART10EN

+#endif /* USART10 */

+#define LL_APB2_GRP1_PERIPH_SPI1           RCC_APB2ENR_SPI1EN

+#define LL_APB2_GRP1_PERIPH_SPI4           RCC_APB2ENR_SPI4EN

+#define LL_APB2_GRP1_PERIPH_TIM15          RCC_APB2ENR_TIM15EN

+#define LL_APB2_GRP1_PERIPH_TIM16          RCC_APB2ENR_TIM16EN

+#define LL_APB2_GRP1_PERIPH_TIM17          RCC_APB2ENR_TIM17EN

+#define LL_APB2_GRP1_PERIPH_SPI5           RCC_APB2ENR_SPI5EN

+#define LL_APB2_GRP1_PERIPH_SAI1           RCC_APB2ENR_SAI1EN

+#define LL_APB2_GRP1_PERIPH_SAI2           RCC_APB2ENR_SAI2EN

+#if defined(SAI3)

+#define LL_APB2_GRP1_PERIPH_SAI3           RCC_APB2ENR_SAI3EN

+#endif /* SAI3 */

+#define LL_APB2_GRP1_PERIPH_DFSDM1         RCC_APB2ENR_DFSDM1EN

+#if defined(HRTIM1)

+#define LL_APB2_GRP1_PERIPH_HRTIM          RCC_APB2ENR_HRTIMEN

+#endif /* HRTIM1 */

+/**

+  * @}

+  */

+

+

+/** @defgroup BUS_LL_EC_APB4_GRP1_PERIPH  APB4 GRP1 PERIPH

+  * @{

+  */

+#define LL_APB4_GRP1_PERIPH_SYSCFG         RCC_APB4ENR_SYSCFGEN

+#define LL_APB4_GRP1_PERIPH_LPUART1        RCC_APB4ENR_LPUART1EN

+#define LL_APB4_GRP1_PERIPH_SPI6           RCC_APB4ENR_SPI6EN

+#define LL_APB4_GRP1_PERIPH_I2C4           RCC_APB4ENR_I2C4EN

+#define LL_APB4_GRP1_PERIPH_LPTIM2         RCC_APB4ENR_LPTIM2EN

+#define LL_APB4_GRP1_PERIPH_LPTIM3         RCC_APB4ENR_LPTIM3EN

+#if defined(LPTIM4)

+#define LL_APB4_GRP1_PERIPH_LPTIM4         RCC_APB4ENR_LPTIM4EN

+#endif /* LPTIM4 */

+#if defined(LPTIM5)

+#define LL_APB4_GRP1_PERIPH_LPTIM5         RCC_APB4ENR_LPTIM5EN

+#endif /* LPTIM5 */

+#if defined(DAC2)

+#define LL_APB4_GRP1_PERIPH_DAC2           RCC_APB4ENR_DAC2EN

+#endif /* DAC2 */

+#define LL_APB4_GRP1_PERIPH_COMP12         RCC_APB4ENR_COMP12EN

+#define LL_APB4_GRP1_PERIPH_VREF           RCC_APB4ENR_VREFEN

+#define LL_APB4_GRP1_PERIPH_RTCAPB         RCC_APB4ENR_RTCAPBEN

+#if defined(SAI4)

+#define LL_APB4_GRP1_PERIPH_SAI4           RCC_APB4ENR_SAI4EN

+#endif /* SAI4 */

+#if defined(DTS)

+#define LL_APB4_GRP1_PERIPH_DTS            RCC_APB4ENR_DTSEN

+#endif /*DTS*/

+#if defined(DFSDM2_BASE)

+#define LL_APB4_GRP1_PERIPH_DFSDM2         RCC_APB4ENR_DFSDM2EN

+#endif /* DFSDM2_BASE */

+/**

+  * @}

+  */

+

+/** @defgroup BUS_LL_EC_CLKAM_PERIPH  CLKAM PERIPH

+  * @{

+  */

+#if defined(RCC_D3AMR_BDMAAMEN)

+#define LL_CLKAM_PERIPH_BDMA          RCC_D3AMR_BDMAAMEN

+#else

+#define LL_CLKAM_PERIPH_BDMA2         RCC_SRDAMR_BDMA2AMEN

+#define LL_CLKAM_PERIPH_BDMA          LL_CLKAM_PERIPH_BDMA2 /* for backward compatibility*/

+#endif /* RCC_D3AMR_BDMAAMEN */

+#if defined(RCC_SRDAMR_GPIOAMEN)

+#define LL_CLKAM_PERIPH_GPIO          RCC_SRDAMR_GPIOAMEN

+#endif /* RCC_SRDAMR_GPIOAMEN */

+#if defined(RCC_D3AMR_LPUART1AMEN)

+#define LL_CLKAM_PERIPH_LPUART1       RCC_D3AMR_LPUART1AMEN

+#else

+#define LL_CLKAM_PERIPH_LPUART1       RCC_SRDAMR_LPUART1AMEN

+#endif /* RCC_D3AMR_LPUART1AMEN */

+#if defined(RCC_D3AMR_SPI6AMEN)

+#define LL_CLKAM_PERIPH_SPI6          RCC_D3AMR_SPI6AMEN

+#else

+#define LL_CLKAM_PERIPH_SPI6          RCC_SRDAMR_SPI6AMEN

+#endif /* RCC_D3AMR_SPI6AMEN */

+#if defined(RCC_D3AMR_I2C4AMEN)

+#define LL_CLKAM_PERIPH_I2C4          RCC_D3AMR_I2C4AMEN

+#else

+#define LL_CLKAM_PERIPH_I2C4          RCC_SRDAMR_I2C4AMEN

+#endif /* RCC_D3AMR_I2C4AMEN */

+#if defined(RCC_D3AMR_LPTIM2AMEN)

+#define LL_CLKAM_PERIPH_LPTIM2        RCC_D3AMR_LPTIM2AMEN

+#else

+#define LL_CLKAM_PERIPH_LPTIM2        RCC_SRDAMR_LPTIM2AMEN

+#endif /* RCC_D3AMR_LPTIM2AMEN */

+#if defined(RCC_D3AMR_LPTIM3AMEN)

+#define LL_CLKAM_PERIPH_LPTIM3        RCC_D3AMR_LPTIM3AMEN

+#else

+#define LL_CLKAM_PERIPH_LPTIM3        RCC_SRDAMR_LPTIM3AMEN

+#endif /* RCC_D3AMR_LPTIM3AMEN */

+#if defined(RCC_D3AMR_LPTIM4AMEN)

+#define LL_CLKAM_PERIPH_LPTIM4        RCC_D3AMR_LPTIM4AMEN

+#endif /* RCC_D3AMR_LPTIM4AMEN */

+#if defined(RCC_D3AMR_LPTIM5AMEN)

+#define LL_CLKAM_PERIPH_LPTIM5        RCC_D3AMR_LPTIM5AMEN

+#endif /* RCC_D3AMR_LPTIM5AMEN */

+#if defined(DAC2)

+#define LL_CLKAM_PERIPH_DAC2          RCC_SRDAMR_DAC2AMEN

+#endif /* DAC2 */

+#if defined(RCC_D3AMR_COMP12AMEN)

+#define LL_CLKAM_PERIPH_COMP12        RCC_D3AMR_COMP12AMEN

+#else

+#define LL_CLKAM_PERIPH_COMP12        RCC_SRDAMR_COMP12AMEN

+#endif /* RCC_D3AMR_COMP12AMEN */

+#if defined(RCC_D3AMR_VREFAMEN)

+#define LL_CLKAM_PERIPH_VREF          RCC_D3AMR_VREFAMEN

+#else

+#define LL_CLKAM_PERIPH_VREF          RCC_SRDAMR_VREFAMEN

+#endif /* RCC_D3AMR_VREFAMEN */

+#if defined(RCC_D3AMR_RTCAMEN)

+#define LL_CLKAM_PERIPH_RTC           RCC_D3AMR_RTCAMEN

+#else

+#define LL_CLKAM_PERIPH_RTC           RCC_SRDAMR_RTCAMEN

+#endif /* RCC_D3AMR_RTCAMEN */

+#if defined(RCC_D3AMR_CRCAMEN)

+#define LL_CLKAM_PERIPH_CRC           RCC_D3AMR_CRCAMEN

+#endif /* RCC_D3AMR_CRCAMEN */

+#if defined(SAI4)

+#define LL_CLKAM_PERIPH_SAI4          RCC_D3AMR_SAI4AMEN

+#endif /* SAI4 */

+#if defined(ADC3)

+#define LL_CLKAM_PERIPH_ADC3          RCC_D3AMR_ADC3AMEN

+#endif /* ADC3 */

+#if defined(DTS)

+#define LL_CLKAM_PERIPH_DTS           RCC_SRDAMR_DTSAMEN

+#endif /* DTS */

+#if defined(DFSDM2_BASE)

+#define LL_CLKAM_PERIPH_DFSDM2        RCC_SRDAMR_DFSDM2AMEN

+#endif /* DFSDM2_BASE */

+#if defined(RCC_D3AMR_BKPRAMAMEN)

+#define LL_CLKAM_PERIPH_BKPRAM        RCC_D3AMR_BKPRAMAMEN

+#else

+#define LL_CLKAM_PERIPH_BKPRAM        RCC_SRDAMR_BKPRAMAMEN

+#endif /* RCC_D3AMR_BKPRAMAMEN */

+#if defined(RCC_D3AMR_SRAM4AMEN)

+#define LL_CLKAM_PERIPH_SRAM4         RCC_D3AMR_SRAM4AMEN

+#else

+#define LL_CLKAM_PERIPH_SRDSRAM       RCC_SRDAMR_SRDSRAMAMEN

+#define LL_CLKAM_PERIPH_SRAM4         LL_CLKAM_PERIPH_SRDSRAM

+#endif /* RCC_D3AMR_SRAM4AMEN */

+/**

+  * @}

+  */

+

+#if defined(RCC_CKGAENR_AXICKG)

+/** @defgroup BUS_LL_EC_CKGA_PERIPH  CKGA (AXI Clocks Gating) PERIPH

+  * @{

+  */

+#define LL_CKGA_PERIPH_AXI            RCC_CKGAENR_AXICKG

+#define LL_CKGA_PERIPH_AHB            RCC_CKGAENR_AHBCKG

+#define LL_CKGA_PERIPH_CPU            RCC_CKGAENR_CPUCKG

+#define LL_CKGA_PERIPH_SDMMC          RCC_CKGAENR_SDMMCCKG

+#define LL_CKGA_PERIPH_MDMA           RCC_CKGAENR_MDMACKG

+#define LL_CKGA_PERIPH_DMA2D          RCC_CKGAENR_DMA2DCKG

+#define LL_CKGA_PERIPH_LTDC           RCC_CKGAENR_LTDCCKG

+#define LL_CKGA_PERIPH_GFXMMUM        RCC_CKGAENR_GFXMMUMCKG

+#define LL_CKGA_PERIPH_AHB12          RCC_CKGAENR_AHB12CKG

+#define LL_CKGA_PERIPH_AHB34          RCC_CKGAENR_AHB34CKG

+#define LL_CKGA_PERIPH_FLIFT          RCC_CKGAENR_FLIFTCKG

+#define LL_CKGA_PERIPH_OCTOSPI2       RCC_CKGAENR_OCTOSPI2CKG

+#define LL_CKGA_PERIPH_FMC            RCC_CKGAENR_FMCCKG

+#define LL_CKGA_PERIPH_OCTOSPI1       RCC_CKGAENR_OCTOSPI1CKG

+#define LL_CKGA_PERIPH_AXIRAM1        RCC_CKGAENR_AXIRAM1CKG

+#define LL_CKGA_PERIPH_AXIRAM2        RCC_CKGAENR_AXIRAM2CKG

+#define LL_CKGA_PERIPH_AXIRAM3        RCC_CKGAENR_AXIRAM3CKG

+#define LL_CKGA_PERIPH_GFXMMUS        RCC_CKGAENR_GFXMMUSCKG

+#define LL_CKGA_PERIPH_ECCRAM         RCC_CKGAENR_ECCRAMCKG

+#define LL_CKGA_PERIPH_EXTI           RCC_CKGAENR_EXTICKG

+#define LL_CKGA_PERIPH_JTAG           RCC_CKGAENR_JTAGCKG

+/**

+  * @}

+  */

+#endif /* RCC_CKGAENR_AXICKG */

+

+/* Exported macro ------------------------------------------------------------*/

+

+/* Exported functions --------------------------------------------------------*/

+

+/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions

+  * @{

+  */

+

+/** @defgroup BUS_LL_EF_AHB3 AHB3

+  * @{

+  */

+

+/**

+  * @brief  Enable AHB3 peripherals clock.

+  * @rmtoll AHB3ENR      MDMAEN        LL_AHB3_GRP1_EnableClock\n

+  *         AHB3ENR      DMA2DEN       LL_AHB3_GRP1_EnableClock\n

+  *         AHB3ENR      JPGDECEN      LL_AHB3_GRP1_EnableClock\n

+  *         AHB3ENR      FMCEN         LL_AHB3_GRP1_EnableClock\n

+  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_EnableClock\n  (*)

+  *         AHB3ENR      OSPI1EN       LL_AHB3_GRP1_EnableClock\n  (*)

+  *         AHB3ENR      OSPI2EN       LL_AHB3_GRP1_EnableClock\n  (*)

+  *         AHB3ENR      IOMNGREN      LL_AHB3_GRP1_EnableClock\n  (*)

+  *         AHB3ENR      OTFDEC1EN     LL_AHB3_GRP1_EnableClock\n  (*)

+  *         AHB3ENR      OTFDEC2EN     LL_AHB3_GRP1_EnableClock\n  (*)

+  *         AHB3ENR      GFXMMU        LL_AHB3_GRP1_EnableClock\n  (*)

+  *         AHB3ENR      SDMMC1EN      LL_AHB3_GRP1_EnableClock\n

+  *         AHB3ENR      FLASHEN       LL_AHB3_GRP1_EnableClock\n  (*)

+  *         AHB3ENR      DTCM1EN       LL_AHB3_GRP1_EnableClock\n  (*)

+  *         AHB3ENR      DTCM2EN       LL_AHB3_GRP1_EnableClock\n  (*)

+  *         AHB3ENR      ITCMEN        LL_AHB3_GRP1_EnableClock\n  (*)

+  *         AHB3ENR      AXISRAMEN     LL_AHB3_GRP1_EnableClock    (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC->AHB3ENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Check if AHB3 peripheral clock is enabled or not

+  * @rmtoll AHB3ENR      MDMAEN        LL_AHB3_GRP1_IsEnabledClock\n

+  *         AHB3ENR      DMA2DEN       LL_AHB3_GRP1_IsEnabledClock\n

+  *         AHB3ENR      JPGDECEN      LL_AHB3_GRP1_IsEnabledClock\n

+  *         AHB3ENR      FMCEN         LL_AHB3_GRP1_IsEnabledClock\n

+  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_IsEnabledClock\n (*)

+  *         AHB3ENR      OSPI1EN       LL_AHB3_GRP1_IsEnabledClock\n (*)

+  *         AHB3ENR      OSPI2EN       LL_AHB3_GRP1_IsEnabledClock\n (*)

+  *         AHB3ENR      IOMNGREN      LL_AHB3_GRP1_IsEnabledClock\n (*)

+  *         AHB3ENR      OTFDEC1EN     LL_AHB3_GRP1_IsEnabledClock\n (*)

+  *         AHB3ENR      OTFDEC2EN     LL_AHB3_GRP1_IsEnabledClock\n (*)

+  *         AHB3ENR      GFXMMU        LL_AHB3_GRP1_IsEnabledClock\n (*)

+  *         AHB3ENR      SDMMC1EN      LL_AHB3_GRP1_IsEnabledClock\n

+  *         AHB3ENR      FLASHEN       LL_AHB3_GRP1_IsEnabledClock\n (*)

+  *         AHB3ENR      DTCM1EN       LL_AHB3_GRP1_IsEnabledClock\n (*)

+  *         AHB3ENR      DTCM2EN       LL_AHB3_GRP1_IsEnabledClock\n (*)

+  *         AHB3ENR      ITCMEN        LL_AHB3_GRP1_IsEnabledClock\n (*)

+  *         AHB3ENR      AXISRAMEN     LL_AHB3_GRP1_IsEnabledClock   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI    (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1   (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2   (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_IOMNGR  (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval uint32_t

+*/

+__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)

+{

+  return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs)?1U:0U);

+}

+

+/**

+  * @brief  Disable AHB3 peripherals clock.

+  * @rmtoll AHB3ENR      MDMAEN        LL_AHB3_GRP1_DisableClock\n

+  *         AHB3ENR      DMA2DEN       LL_AHB3_GRP1_DisableClock\n

+  *         AHB3ENR      JPGDECEN      LL_AHB3_GRP1_DisableClock\n

+  *         AHB3ENR      FMCEN         LL_AHB3_GRP1_DisableClock\n

+  *         AHB3ENR      QSPIEN        LL_AHB3_GRP1_DisableClock\n (*)

+  *         AHB3ENR      OSPI1EN       LL_AHB3_GRP1_DisableClock\n (*)

+  *         AHB3ENR      OSPI2EN       LL_AHB3_GRP1_DisableClock\n (*)

+  *         AHB3ENR      IOMNGREN      LL_AHB3_GRP1_DisableClock\n (*)

+  *         AHB3ENR      OTFDEC1EN     LL_AHB3_GRP1_DisableClock\n (*)

+  *         AHB3ENR      OTFDEC2EN     LL_AHB3_GRP1_DisableClock\n (*)

+  *         AHB3ENR      GFXMMU        LL_AHB3_GRP1_DisableClock\n (*)

+  *         AHB3ENR      SDMMC1EN      LL_AHB3_GRP1_DisableClock\n (*)

+  *         AHB3ENR      FLASHEN       LL_AHB3_GRP1_DisableClock\n (*)

+  *         AHB3ENR      DTCM1EN       LL_AHB3_GRP1_DisableClock\n (*)

+  *         AHB3ENR      DTCM2EN       LL_AHB3_GRP1_DisableClock\n (*)

+  *         AHB3ENR      ITCMEN        LL_AHB3_GRP1_DisableClock\n (*)

+  *         AHB3ENR      AXISRAMEN     LL_AHB3_GRP1_DisableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI    (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1   (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2   (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_IOMNGR  (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1 (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2 (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC->AHB3ENR, Periphs);

+}

+

+/**

+  * @brief  Force AHB3 peripherals reset.

+  * @rmtoll AHB3RSTR     MDMARST       LL_AHB3_GRP1_ForceReset\n

+  *         AHB3RSTR     DMA2DRST      LL_AHB3_GRP1_ForceReset\n

+  *         AHB3RSTR     JPGDECRST     LL_AHB3_GRP1_ForceReset\n

+  *         AHB3RSTR     FMCRST        LL_AHB3_GRP1_ForceReset\n

+  *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ForceReset\n (*)

+  *         AHB3RSTR     OSPI1RST      LL_AHB3_GRP1_ForceReset\n (*)

+  *         AHB3RSTR     OSPI2RST      LL_AHB3_GRP1_ForceReset\n (*)

+  *         AHB3RSTR     IOMNGRRST     LL_AHB3_GRP1_ForceReset\n (*)

+  *         AHB3RSTR     OTFDEC1RST    LL_AHB3_GRP1_ForceReset\n (*)

+  *         AHB3RSTR     OTFDEC2RST    LL_AHB3_GRP1_ForceReset\n (*)

+  *         AHB3RSTR     GFXMMURST     LL_AHB3_GRP1_ForceReset\n (*)

+  *         AHB3RSTR     SDMMC1RST     LL_AHB3_GRP1_ForceReset

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1  (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2  (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU   (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)

+{

+  SET_BIT(RCC->AHB3RSTR, Periphs);

+}

+

+/**

+  * @brief  Release AHB3 peripherals reset.

+  * @rmtoll AHB3RSTR     MDMARST       LL_AHB3_GRP1_ReleaseReset\n

+  *         AHB3RSTR     DMA2DRST      LL_AHB3_GRP1_ReleaseReset\n

+  *         AHB3RSTR     JPGDECRST     LL_AHB3_GRP1_ReleaseReset\n

+  *         AHB3RSTR     FMCRST        LL_AHB3_GRP1_ReleaseReset\n

+  *         AHB3RSTR     QSPIRST       LL_AHB3_GRP1_ReleaseReset\n

+  *         AHB3RSTR     OSPI1RST      LL_AHB3_GRP1_ReleaseReset\n (*)

+  *         AHB3RSTR     OSPI2RST      LL_AHB3_GRP1_ReleaseReset\n (*)

+  *         AHB3RSTR     IOMNGRRST     LL_AHB3_GRP1_ReleaseReset\n (*)

+  *         AHB3RSTR     OTFDEC1RST    LL_AHB3_GRP1_ReleaseReset\n (*)

+  *         AHB3RSTR     OTFDEC2RST    LL_AHB3_GRP1_ReleaseReset\n (*)

+  *         AHB3RSTR     GFXMMURST     LL_AHB3_GRP1_ReleaseReset\n (*)

+  *         AHB3RSTR     SDMMC1RST     LL_AHB3_GRP1_ReleaseReset

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1  (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2  (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU   (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC->AHB3RSTR, Periphs);

+}

+

+/**

+  * @brief  Enable AHB3 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll AHB3LPENR    MDMALPEN      LL_AHB3_GRP1_EnableClockSleep\n

+  *         AHB3LPENR    DMA2DLPEN     LL_AHB3_GRP1_EnableClockSleep\n

+  *         AHB3LPENR    JPGDECLPEN    LL_AHB3_GRP1_EnableClockSleep\n

+  *         AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_EnableClockSleep\n

+  *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_EnableClockSleep\n  (*)

+  *         AHB3LPENR    OSPI1LPEN     LL_AHB3_GRP1_EnableClockSleep\n  (*)

+  *         AHB3LPENR    OSPI2LPEN     LL_AHB3_GRP1_EnableClockSleep\n  (*)

+  *         AHB3LPENR    IOMNGRLPEN    LL_AHB3_GRP1_EnableClockSleep\n  (*)

+  *         AHB3LPENR    OTFDEC1LPEN   LL_AHB3_GRP1_EnableClockSleep\n  (*)

+  *         AHB3LPENR    OTFDEC1LPEN   LL_AHB3_GRP1_EnableClockSleep\n  (*)

+  *         AHB3LPENR    GFXMMULPEN    LL_AHB3_GRP1_EnableClockSleep\n  (*)

+  *         AHB3LPENR    SDMMC1LPEN    LL_AHB3_GRP1_EnableClockSleep\n

+  *         AHB3LPENR    FLASHLPEN     LL_AHB3_GRP1_EnableClockSleep\n

+  *         AHB3LPENR    DTCM1LPEN     LL_AHB3_GRP1_EnableClockSleep\n

+  *         AHB3LPENR    DTCM2LPEN     LL_AHB3_GRP1_EnableClockSleep\n

+  *         AHB3LPENR    ITCMLPEN      LL_AHB3_GRP1_EnableClockSleep\n

+  *         AHB3LPENR    AXISRAMLPEN   LL_AHB3_GRP1_EnableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1  (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2  (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU   (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC->AHB3LPENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Disable AHB3 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll AHB3LPENR    MDMALPEN      LL_AHB3_GRP1_DisableClockSleep\n

+  *         AHB3LPENR    DMA2DLPEN     LL_AHB3_GRP1_DisableClockSleep\n

+  *         AHB3LPENR    JPGDECLPEN    LL_AHB3_GRP1_DisableClockSleep\n

+  *         AHB3LPENR    FMCLPEN       LL_AHB3_GRP1_DisableClockSleep\n

+  *         AHB3LPENR    QSPILPEN      LL_AHB3_GRP1_DisableClockSleep\n

+  *         AHB3LPENR    OSPI1LPEN     LL_AHB3_GRP1_DisableClockSleep\n  (*)

+  *         AHB3LPENR    OSPI2LPEN     LL_AHB3_GRP1_DisableClockSleep\n  (*)

+  *         AHB3LPENR    IOMNGRLPEN    LL_AHB3_GRP1_DisableClockSleep\n  (*)

+  *         AHB3LPENR    OTFDEC1LPEN   LL_AHB3_GRP1_DisableClockSleep\n  (*)

+  *         AHB3LPENR    OTFDEC1LPEN   LL_AHB3_GRP1_DisableClockSleep\n  (*)

+  *         AHB3LPENR    GFXMMULPEN    LL_AHB3_GRP1_DisableClockSleep\n  (*)

+  *         AHB3LPENR    SDMMC1LPEN    LL_AHB3_GRP1_DisableClockSleep\n

+  *         AHB3LPENR    FLASHLPEN     LL_AHB3_GRP1_DisableClockSleep\n

+  *         AHB3LPENR    DTCM1LPEN     LL_AHB3_GRP1_DisableClockSleep\n

+  *         AHB3LPENR    DTCM2LPEN     LL_AHB3_GRP1_DisableClockSleep\n

+  *         AHB3LPENR    ITCMLPEN      LL_AHB3_GRP1_DisableClockSleep\n

+  *         AHB3LPENR    AXISRAMLPEN   LL_AHB3_GRP1_DisableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1  (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2  (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU   (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC->AHB3LPENR, Periphs);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup BUS_LL_EF_AHB1 AHB1

+  * @{

+  */

+

+/**

+  * @brief  Enable AHB1 peripherals clock.

+  * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_EnableClock\n

+  *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_EnableClock\n

+  *         AHB1ENR      ADC12EN       LL_AHB1_GRP1_EnableClock\n

+  *         AHB1ENR      ARTEN         LL_AHB1_GRP1_EnableClock\n

+  *         AHB1ENR      ETH1MACEN     LL_AHB1_GRP1_EnableClock\n (*)

+  *         AHB1ENR      ETH1TXEN      LL_AHB1_GRP1_EnableClock\n (*)

+  *         AHB1ENR      ETH1RXEN      LL_AHB1_GRP1_EnableClock\n (*)

+  *         AHB1ENR      USB1OTGHSEN   LL_AHB1_GRP1_EnableClock\n

+  *         AHB1ENR      USB1OTGHSULPIEN  LL_AHB1_GRP1_EnableClock\n

+  *         AHB1ENR      USB2OTGHSEN   LL_AHB1_GRP1_EnableClock\n  (*)

+  *         AHB1ENR      USB2OTGHSULPIEN  LL_AHB1_GRP1_EnableClock (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS  (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC->AHB1ENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Check if AHB1 peripheral clock is enabled or not

+  * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_IsEnabledClock\n

+  *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_IsEnabledClock\n

+  *         AHB1ENR      ADC12EN       LL_AHB1_GRP1_IsEnabledClock\n

+  *         AHB1ENR      ARTEN         LL_AHB1_GRP1_IsEnabledClock\n (*)

+  *         AHB1ENR      CRCEN         LL_AHB1_GRP1_IsEnabledClock\n (*)

+  *         AHB1ENR      ETH1MACEN     LL_AHB1_GRP1_IsEnabledClock\n (*)

+  *         AHB1ENR      ETH1TXEN      LL_AHB1_GRP1_IsEnabledClock\n (*)

+  *         AHB1ENR      ETH1RXEN      LL_AHB1_GRP1_IsEnabledClock\n (*)

+  *         AHB1ENR      USB1OTGHSEN   LL_AHB1_GRP1_IsEnabledClock\n

+  *         AHB1ENR      USB1OTGHSULPIEN  LL_AHB1_GRP1_IsEnabledClock\n

+  *         AHB1ENR      USB2OTGHSEN   LL_AHB1_GRP1_IsEnabledClock\n  (*)

+  *         AHB1ENR      USB2OTGHSULPIEN  LL_AHB1_GRP1_IsEnabledClock (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX  (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX  (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval uint32_t

+*/

+__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)

+{

+  return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs)?1U:0U);

+}

+

+/**

+  * @brief  Disable AHB1 peripherals clock.

+  * @rmtoll AHB1ENR      DMA1EN        LL_AHB1_GRP1_DisableClock\n

+  *         AHB1ENR      DMA2EN        LL_AHB1_GRP1_DisableClock\n

+  *         AHB1ENR      ADC12EN       LL_AHB1_GRP1_DisableClock\n

+  *         AHB1ENR      ARTEN         LL_AHB1_GRP1_DisableClock\n (*)

+  *         AHB1ENR      ETH1MACEN     LL_AHB1_GRP1_DisableClock\n (*)

+  *         AHB1ENR      ETH1TXEN      LL_AHB1_GRP1_DisableClock\n (*)

+  *         AHB1ENR      ETH1RXEN      LL_AHB1_GRP1_DisableClock\n (*)

+  *         AHB1ENR      USB1OTGHSEN   LL_AHB1_GRP1_DisableClock\n

+  *         AHB1ENR      USB1OTGHSULPIEN  LL_AHB1_GRP1_DisableClock\n

+  *         AHB1ENR      USB2OTGHSEN   LL_AHB1_GRP1_DisableClock\n  (*)

+  *         AHB1ENR      USB2OTGHSULPIEN  LL_AHB1_GRP1_DisableClock (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX  (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX  (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC->AHB1ENR, Periphs);

+}

+

+/**

+  * @brief  Force AHB1 peripherals reset.

+  * @rmtoll AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ForceReset\n

+  *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ForceReset\n

+  *         AHB1RSTR     ADC12RST      LL_AHB1_GRP1_ForceReset\n

+  *         AHB1RSTR     ARTRST        LL_AHB1_GRP1_ForceReset\n (*)

+  *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ForceReset\n (*)

+  *         AHB1RSTR     ETH1MACRST    LL_AHB1_GRP1_ForceReset\n (*)

+  *         AHB1RSTR     USB1OTGHSRST  LL_AHB1_GRP1_ForceReset\n

+  *         AHB1RSTR     USB2OTGHSRST  LL_AHB1_GRP1_ForceReset   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)

+{

+  SET_BIT(RCC->AHB1RSTR, Periphs);

+}

+

+/**

+  * @brief  Release AHB1 peripherals reset.

+  * @rmtoll AHB1RSTR     DMA1RST       LL_AHB1_GRP1_ReleaseReset\n

+  *         AHB1RSTR     DMA2RST       LL_AHB1_GRP1_ReleaseReset\n

+  *         AHB1RSTR     ADC12RST      LL_AHB1_GRP1_ReleaseReset\n

+  *         AHB1RSTR     ARTRST        LL_AHB1_GRP1_ReleaseReset\n (*)

+  *         AHB1RSTR     CRCRST        LL_AHB1_GRP1_ReleaseReset\n (*)

+  *         AHB1RSTR     ETH1MACRST    LL_AHB1_GRP1_ReleaseReset\n (*)

+  *         AHB1RSTR     USB1OTGHSRST  LL_AHB1_GRP1_ReleaseReset\n

+  *         AHB1RSTR     USB2OTGHSRST  LL_AHB1_GRP1_ReleaseReset   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC->AHB1RSTR, Periphs);

+}

+

+/**

+  * @brief  Enable AHB1 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll AHB1LPENR    DMA1LPEN      LL_AHB1_GRP1_EnableClockSleep\n

+  *         AHB1LPENR    DMA2LPEN      LL_AHB1_GRP1_EnableClockSleep\n

+  *         AHB1LPENR    ADC12LPEN     LL_AHB1_GRP1_EnableClockSleep\n

+  *         AHB1LPENR    ARTLPEN       LL_AHB1_GRP1_EnableClockSleep\n (*)

+  *         AHB1LPENR    CRCLPEN       LL_AHB1_GRP1_EnableClockSleep\n (*)

+  *         AHB1LPENR    ETH1MACLPEN   LL_AHB1_GRP1_EnableClockSleep\n (*)

+  *         AHB1LPENR    ETH1TXLPEN    LL_AHB1_GRP1_EnableClockSleep\n (*)

+  *         AHB1LPENR    ETH1RXLPEN    LL_AHB1_GRP1_EnableClockSleep\n

+  *         AHB1LPENR    USB1OTGHSLPEN  LL_AHB1_GRP1_EnableClockSleep\n

+  *         AHB1LPENR    USB1OTGHSULPILPEN  LL_AHB1_GRP1_EnableClockSleep\n

+  *         AHB1LPENR    USB2OTGHSLPEN  LL_AHB1_GRP1_EnableClockSleep\n   (*)

+  *         AHB1LPENR    USB2OTGHSULPILPEN  LL_AHB1_GRP1_EnableClockSleep (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX  (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX  (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC->AHB1LPENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Disable AHB1 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll AHB1LPENR    DMA1LPEN      LL_AHB1_GRP1_DisableClockSleep\n

+  *         AHB1LPENR    DMA2LPEN      LL_AHB1_GRP1_DisableClockSleep\n

+  *         AHB1LPENR    ADC12LPEN     LL_AHB1_GRP1_DisableClockSleep\n

+  *         AHB1LPENR    ARTLPEN       LL_AHB1_GRP1_DisableClockSleep\n (*)

+  *         AHB1LPENR    CRCLPEN       LL_AHB1_GRP1_DisableClockSleep\n (*)

+  *         AHB1LPENR    ETH1MACLPEN   LL_AHB1_GRP1_DisableClockSleep\n (*)

+  *         AHB1LPENR    ETH1TXLPEN    LL_AHB1_GRP1_DisableClockSleep\n (*)

+  *         AHB1LPENR    ETH1RXLPEN    LL_AHB1_GRP1_DisableClockSleep\n (*)

+  *         AHB1LPENR    USB1OTGHSLPEN  LL_AHB1_GRP1_DisableClockSleep\n

+  *         AHB1LPENR    USB1OTGHSULPILPEN  LL_AHB1_GRP1_DisableClockSleep\n

+  *         AHB1LPENR    USB2OTGHSLPEN  LL_AHB1_GRP1_DisableClockSleep\n   (*)

+  *         AHB1LPENR    USB2OTGHSULPILPEN  LL_AHB1_GRP1_DisableClockSleep (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX  (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX  (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC->AHB1LPENR, Periphs);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup BUS_LL_EF_AHB2 AHB2

+  * @{

+  */

+

+/**

+  * @brief  Enable AHB2 peripherals clock.

+  * @rmtoll AHB2ENR      DCMIEN        LL_AHB2_GRP1_EnableClock\n

+  *         AHB2ENR      HSEMEN        LL_AHB2_GRP1_EnableClock\n (*)

+  *         AHB2ENR      CRYPEN        LL_AHB2_GRP1_EnableClock\n (*)

+  *         AHB2ENR      HASHEN        LL_AHB2_GRP1_EnableClock\n (*)

+  *         AHB2ENR      RNGEN         LL_AHB2_GRP1_EnableClock\n

+  *         AHB2ENR      SDMMC2EN      LL_AHB2_GRP1_EnableClock\n

+  *         AHB2ENR      BDMA1EN       LL_AHB2_GRP1_EnableClock\n (*)

+  *         AHB2ENR      D2SRAM1EN     LL_AHB2_GRP1_EnableClock\n

+  *         AHB2ENR      D2SRAM2EN     LL_AHB2_GRP1_EnableClock\n

+  *         AHB2ENR      D2SRAM3EN     LL_AHB2_GRP1_EnableClock   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1   (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC->AHB2ENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Check if AHB2 peripheral clock is enabled or not

+  * @rmtoll AHB2ENR      DCMIEN        LL_AHB2_GRP1_IsEnabledClock\n

+  *         AHB2ENR      HSEMEN        LL_AHB2_GRP1_IsEnabledClock\n (*)

+  *         AHB2ENR      CRYPEN        LL_AHB2_GRP1_IsEnabledClock\n (*)

+  *         AHB2ENR      HASHEN        LL_AHB2_GRP1_IsEnabledClock\n (*)

+  *         AHB2ENR      RNGEN         LL_AHB2_GRP1_IsEnabledClock\n

+  *         AHB2ENR      SDMMC2EN      LL_AHB2_GRP1_IsEnabledClock\n

+  *         AHB2ENR      BDMA1EN       LL_AHB2_GRP1_IsEnabledClock\n (*)

+  *         AHB2ENR      D2SRAM1EN     LL_AHB2_GRP1_IsEnabledClock\n

+  *         AHB2ENR      D2SRAM2EN     LL_AHB2_GRP1_IsEnabledClock\n

+  *         AHB2ENR      D2SRAM3EN     LL_AHB2_GRP1_IsEnabledClock   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEMEN (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1   (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval uint32_t

+*/

+__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)

+{

+  return ((READ_BIT(RCC->AHB2ENR, Periphs) == Periphs)?1U:0U);

+}

+

+/**

+  * @brief  Disable AHB2 peripherals clock.

+  * @rmtoll AHB2ENR      DCMIEN        LL_AHB2_GRP1_DisableClock\n

+  *         AHB2ENR      HSEMEN        LL_AHB2_GRP1_DisableClock\n (*)

+  *         AHB2ENR      CRYPEN        LL_AHB2_GRP1_DisableClock\n (*)

+  *         AHB2ENR      HASHEN        LL_AHB2_GRP1_DisableClock\n (*)

+  *         AHB2ENR      RNGEN         LL_AHB2_GRP1_DisableClock\n

+  *         AHB2ENR      SDMMC2EN      LL_AHB2_GRP1_DisableClock\n

+  *         AHB2ENR      BDMA1EN       LL_AHB2_GRP1_DisableClock\n (*)

+  *         AHB2ENR      D2SRAM1EN     LL_AHB2_GRP1_DisableClock\n

+  *         AHB2ENR      D2SRAM2EN     LL_AHB2_GRP1_DisableClock\n

+  *         AHB2ENR      D2SRAM3EN     LL_AHB2_GRP1_DisableClock   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEMEN (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1   (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC->AHB2ENR, Periphs);

+}

+

+/**

+  * @brief  Force AHB2 peripherals reset.

+  * @rmtoll AHB2RSTR     DCMIRST       LL_AHB2_GRP1_ForceReset\n

+  *         AHB2RSTR     HSEMRST       LL_AHB2_GRP1_ForceReset\n (*)

+  *         AHB2RSTR     CRYPRST       LL_AHB2_GRP1_ForceReset\n (*)

+  *         AHB2RSTR     HASHRST       LL_AHB2_GRP1_ForceReset\n (*)

+  *         AHB2RSTR     RNGRST        LL_AHB2_GRP1_ForceReset\n

+  *         AHB2RSTR     SDMMC2RST     LL_AHB2_GRP1_ForceReset\n

+  *         AHB2RSTR     BDMA1RST      LL_AHB2_GRP1_ForceReset   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)

+{

+  SET_BIT(RCC->AHB2RSTR, Periphs);

+}

+

+/**

+  * @brief  Release AHB2 peripherals reset.

+  * @rmtoll AHB2RSTR     DCMIRST       LL_AHB2_GRP1_ReleaseReset\n

+  *         AHB2RSTR     HSEMRST       LL_AHB2_GRP1_ReleaseReset\n (*)

+  *         AHB2RSTR     CRYPRST       LL_AHB2_GRP1_ReleaseReset\n (*)

+  *         AHB2RSTR     HASHRST       LL_AHB2_GRP1_ReleaseReset\n (*)

+  *         AHB2RSTR     RNGRST        LL_AHB2_GRP1_ReleaseReset\n

+  *         AHB2RSTR     SDMMC2RST     LL_AHB2_GRP1_ReleaseReset\n

+  *         AHB2RSTR     BDMA1RST      LL_AHB2_GRP1_ReleaseReset   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC->AHB2RSTR, Periphs);

+}

+

+/**

+  * @brief  Enable AHB2 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll AHB2LPENR    DCMILPEN      LL_AHB2_GRP1_EnableClockSleep\n

+  *         AHB2LPENR    CRYPLPEN      LL_AHB2_GRP1_EnableClockSleep\n (*)

+  *         AHB2LPENR    HASHLPEN      LL_AHB2_GRP1_EnableClockSleep\n (*)

+  *         AHB2LPENR    RNGLPEN       LL_AHB2_GRP1_EnableClockSleep\n

+  *         AHB2LPENR    SDMMC2LPEN    LL_AHB2_GRP1_EnableClockSleep\n

+  *         AHB2LPENR    BDMA1LPEN     LL_AHB2_GRP1_EnableClockSleep\n (*)

+  *         AHB2LPENR    D2SRAM1LPEN   LL_AHB2_GRP1_EnableClockSleep\n

+  *         AHB2LPENR    D2SRAM2LPEN   LL_AHB2_GRP1_EnableClockSleep\n

+  *         AHB2LPENR    D2SRAM3LPEN   LL_AHB2_GRP1_EnableClockSleep   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1   (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC->AHB2LPENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Disable AHB2 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll AHB2LPENR    DCMILPEN      LL_AHB2_GRP1_DisableClockSleep\n

+  *         AHB2LPENR    CRYPLPEN      LL_AHB2_GRP1_DisableClockSleep\n (*)

+  *         AHB2LPENR    HASHLPEN      LL_AHB2_GRP1_DisableClockSleep\n (*)

+  *         AHB2LPENR    RNGLPEN       LL_AHB2_GRP1_DisableClockSleep\n

+  *         AHB2LPENR    SDMMC2LPEN    LL_AHB2_GRP1_DisableClockSleep\n

+  *         AHB2LPENR    BDMA1LPEN     LL_AHB2_GRP1_DisableClockSleep\n (*)

+  *         AHB2LPENR    D2SRAM1LPEN   LL_AHB2_GRP1_DisableClockSleep\n

+  *         AHB2LPENR    D2SRAM2LPEN   LL_AHB2_GRP1_DisableClockSleep\n

+  *         AHB2LPENR    D2SRAM3LPEN   LL_AHB2_GRP1_DisableClockSleep   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC->AHB2LPENR, Periphs);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup BUS_LL_EF_AHB4 AHB4

+  * @{

+  */

+

+/**

+  * @brief  Enable AHB4 peripherals clock.

+  * @rmtoll AHB4ENR      GPIOAEN       LL_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      GPIOBEN       LL_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      GPIOCEN       LL_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      GPIODEN       LL_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      GPIOEEN       LL_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      GPIOFEN       LL_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      GPIOGEN       LL_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      GPIOHEN       LL_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      GPIOIEN       LL_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      GPIOJEN       LL_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      GPIOKEN       LL_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      CRCEN         LL_AHB4_GRP1_EnableClock\n (*)

+  *         AHB4ENR      BDMAEN        LL_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      ADC3EN        LL_AHB4_GRP1_EnableClock\n (*)

+  *         AHB4ENR      HSEMEN        LL_AHB4_GRP1_EnableClock\n (*)

+  *         AHB4ENR      BKPRAMEN      LL_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      SRAM4EN       LL_AHB4_GRP1_EnableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC   (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3  (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM  (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_AHB4_GRP1_EnableClock(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC->AHB4ENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC->AHB4ENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Check if AHB4 peripheral clock is enabled or not

+  * @rmtoll AHB4ENR      GPIOAEN       LL_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      GPIOBEN       LL_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      GPIOCEN       LL_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      GPIODEN       LL_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      GPIOEEN       LL_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      GPIOFEN       LL_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      GPIOGEN       LL_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      GPIOHEN       LL_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      GPIOIEN       LL_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      GPIOJEN       LL_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      GPIOKEN       LL_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      CRCEN         LL_AHB4_GRP1_IsEnabledClock\n (*)

+  *         AHB4ENR      BDMAEN        LL_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      ADC3EN        LL_AHB4_GRP1_IsEnabledClock\n (*)

+  *         AHB4ENR      HSEMEN        LL_AHB4_GRP1_IsEnabledClock\n (*)

+  *         AHB4ENR      BKPRAMEN      LL_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      SRAM4EN       LL_AHB4_GRP1_IsEnabledClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4

+  *

+  *         (*) value not defined in all devices.

+  * @retval uint32_t

+*/

+__STATIC_INLINE uint32_t LL_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)

+{

+  return ((READ_BIT(RCC->AHB4ENR, Periphs) == Periphs)?1U:0U);

+}

+

+/**

+  * @brief  Disable AHB4 peripherals clock.

+  * @rmtoll AHB4ENR      GPIOAEN       LL_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      GPIOBEN       LL_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      GPIOCEN       LL_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      GPIODEN       LL_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      GPIOEEN       LL_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      GPIOFEN       LL_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      GPIOGEN       LL_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      GPIOHEN       LL_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      GPIOIEN       LL_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      GPIOJEN       LL_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      GPIOKEN       LL_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      CRCEN         LL_AHB4_GRP1_DisableClock\n (*)

+  *         AHB4ENR      BDMAEN        LL_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      ADC3EN        LL_AHB4_GRP1_DisableClock\n (*)

+  *         AHB4ENR      HSEMEN        LL_AHB4_GRP1_DisableClock\n (*)

+  *         AHB4ENR      BKPRAMEN      LL_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      SRAM4EN       LL_AHB4_GRP1_DisableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_AHB4_GRP1_DisableClock(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC->AHB4ENR, Periphs);

+}

+

+/**

+  * @brief  Force AHB4 peripherals reset.

+  * @rmtoll AHB4RSTR     GPIOARST      LL_AHB4_GRP1_ForceReset\n

+  *         AHB4RSTR     GPIOBRST      LL_AHB4_GRP1_ForceReset\n

+  *         AHB4RSTR     GPIOCRST      LL_AHB4_GRP1_ForceReset\n

+  *         AHB4RSTR     GPIODRST      LL_AHB4_GRP1_ForceReset\n

+  *         AHB4RSTR     GPIOERST      LL_AHB4_GRP1_ForceReset\n

+  *         AHB4RSTR     GPIOFRST      LL_AHB4_GRP1_ForceReset\n

+  *         AHB4RSTR     GPIOGRST      LL_AHB4_GRP1_ForceReset\n

+  *         AHB4RSTR     GPIOHRST      LL_AHB4_GRP1_ForceReset\n

+  *         AHB4RSTR     GPIOIRST      LL_AHB4_GRP1_ForceReset\n

+  *         AHB4RSTR     GPIOJRST      LL_AHB4_GRP1_ForceReset\n

+  *         AHB4RSTR     GPIOKRST      LL_AHB4_GRP1_ForceReset\n

+  *         AHB4RSTR     CRCRST        LL_AHB4_GRP1_ForceReset\n (*)

+  *         AHB4RSTR     BDMARST       LL_AHB4_GRP1_ForceReset\n

+  *         AHB4RSTR     ADC3RST       LL_AHB4_GRP1_ForceReset\n (*)

+  *         AHB4RSTR     HSEMRST       LL_AHB4_GRP1_ForceReset   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_AHB4_GRP1_ForceReset(uint32_t Periphs)

+{

+  SET_BIT(RCC->AHB4RSTR, Periphs);

+}

+

+/**

+  * @brief  Release AHB4 peripherals reset.

+  * @rmtoll AHB4RSTR     GPIOARST      LL_AHB4_GRP1_ReleaseReset\n

+  *         AHB4RSTR     GPIOBRST      LL_AHB4_GRP1_ReleaseReset\n

+  *         AHB4RSTR     GPIOCRST      LL_AHB4_GRP1_ReleaseReset\n

+  *         AHB4RSTR     GPIODRST      LL_AHB4_GRP1_ReleaseReset\n

+  *         AHB4RSTR     GPIOERST      LL_AHB4_GRP1_ReleaseReset\n

+  *         AHB4RSTR     GPIOFRST      LL_AHB4_GRP1_ReleaseReset\n

+  *         AHB4RSTR     GPIOGRST      LL_AHB4_GRP1_ReleaseReset\n

+  *         AHB4RSTR     GPIOHRST      LL_AHB4_GRP1_ReleaseReset\n

+  *         AHB4RSTR     GPIOIRST      LL_AHB4_GRP1_ReleaseReset\n

+  *         AHB4RSTR     GPIOJRST      LL_AHB4_GRP1_ReleaseReset\n

+  *         AHB4RSTR     GPIOKRST      LL_AHB4_GRP1_ReleaseReset\n

+  *         AHB4RSTR     CRCRST        LL_AHB4_GRP1_ReleaseReset\n (*)

+  *         AHB4RSTR     BDMARST       LL_AHB4_GRP1_ReleaseReset\n

+  *         AHB4RSTR     ADC3RST       LL_AHB4_GRP1_ReleaseReset\n (*)

+  *         AHB4RSTR     HSEMRST       LL_AHB4_GRP1_ReleaseReset   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_AHB4_GRP1_ReleaseReset(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC->AHB4RSTR, Periphs);

+}

+

+/**

+  * @brief  Enable AHB4 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll AHB4LPENR    GPIOALPEN     LL_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    GPIOBLPEN     LL_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    GPIOCLPEN     LL_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    GPIODLPEN     LL_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    GPIOELPEN     LL_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    GPIOFLPEN     LL_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    GPIOGLPEN     LL_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    GPIOHLPEN     LL_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    GPIOILPEN     LL_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    GPIOJLPEN     LL_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    GPIOKLPEN     LL_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    CRCLPEN       LL_AHB4_GRP1_EnableClockSleep\n (*)

+  *         AHB4LPENR    BDMALPEN      LL_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    ADC3LPEN      LL_AHB4_GRP1_EnableClockSleep\n (*)

+  *         AHB4LPENR    BKPRAMLPEN    LL_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    SRAM4LPEN     LL_AHB4_GRP1_EnableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4

+  * @retval None

+*/

+__STATIC_INLINE void LL_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC->AHB4LPENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC->AHB4LPENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Disable AHB4 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll AHB4LPENR    GPIOALPEN     LL_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    GPIOBLPEN     LL_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    GPIOCLPEN     LL_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    GPIODLPEN     LL_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    GPIOELPEN     LL_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    GPIOFLPEN     LL_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    GPIOGLPEN     LL_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    GPIOHLPEN     LL_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    GPIOILPEN     LL_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    GPIOJLPEN     LL_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    GPIOKLPEN     LL_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    CRCLPEN       LL_AHB4_GRP1_DisableClockSleep\n (*)

+  *         AHB4LPENR    BDMALPEN      LL_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    ADC3LPEN      LL_AHB4_GRP1_DisableClockSleep\n (*)

+  *         AHB4LPENR    BKPRAMLPEN    LL_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    SRAM4LPEN   LL_AHB4_GRP1_DisableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4

+  * @retval None

+*/

+__STATIC_INLINE void LL_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC->AHB4LPENR, Periphs);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup BUS_LL_EF_APB3 APB3

+  * @{

+  */

+

+/**

+  * @brief  Enable APB3 peripherals clock.

+  * @rmtoll APB3ENR      LTDCEN        LL_APB3_GRP1_EnableClock\n (*)

+  *         APB3ENR      DSIEN         LL_APB3_GRP1_EnableClock\n (*)

+  *         APB3ENR      WWDG1EN       LL_APB3_GRP1_EnableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)

+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)

+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC->APB3ENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC->APB3ENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Check if APB3 peripheral clock is enabled or not

+  * @rmtoll APB3ENR      LTDCEN        LL_APB3_GRP1_IsEnabledClock\n (*)

+  *         APB3ENR      DSIEN         LL_APB3_GRP1_IsEnabledClock\n (*)

+  *         APB3ENR      WWDG1EN       LL_APB3_GRP1_IsEnabledClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)

+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)

+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1

+  *

+  *         (*) value not defined in all devices.

+  * @retval uint32_t

+*/

+__STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs)

+{

+  return ((READ_BIT(RCC->APB3ENR, Periphs) == Periphs)?1U:0U);

+}

+

+/**

+  * @brief  Disable APB3 peripherals clock.

+  * @rmtoll APB3ENR      LTDCEN        LL_APB3_GRP1_DisableClock\n

+  *         APB3ENR      DSIEN         LL_APB3_GRP1_DisableClock\n

+  *         APB3ENR      WWDG1EN       LL_APB3_GRP1_DisableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)

+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)

+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC->APB3ENR, Periphs);

+}

+

+/**

+  * @brief  Force APB3 peripherals reset.

+  * @rmtoll APB3RSTR     LTDCRST       LL_APB3_GRP1_ForceReset\n (*)

+  *         APB3RSTR     DSIRST        LL_APB3_GRP1_ForceReset   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)

+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs)

+{

+  SET_BIT(RCC->APB3RSTR, Periphs);

+}

+

+/**

+  * @brief  Release APB3 peripherals reset.

+  * @rmtoll APB3RSTR     LTDCRST       LL_APB3_GRP1_ReleaseReset\n

+  *         APB3RSTR     DSIRST        LL_APB3_GRP1_ReleaseReset

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)

+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC->APB3RSTR, Periphs);

+}

+

+/**

+  * @brief  Enable APB3 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll APB3LPENR    LTDCLPEN      LL_APB3_GRP1_EnableClockSleep\n (*)

+  *         APB3LPENR    DSILPEN       LL_APB3_GRP1_EnableClockSleep\n (*)

+  *         APB3LPENR    WWDG1LPEN     LL_APB3_GRP1_EnableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)

+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)

+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_APB3_GRP1_EnableClockSleep(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC->APB3LPENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC->APB3LPENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Disable APB3 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll APB3LPENR    LTDCLPEN      LL_APB3_GRP1_DisableClockSleep\n (*)

+  *         APB3LPENR    DSILPEN       LL_APB3_GRP1_DisableClockSleep\n (*)

+  *         APB3LPENR    WWDG1LPEN     LL_APB3_GRP1_DisableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)

+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)

+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_APB3_GRP1_DisableClockSleep(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC->APB3LPENR, Periphs);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup BUS_LL_EF_APB1 APB1

+  * @{

+  */

+

+/**

+  * @brief  Enable APB1 peripherals clock.

+  * @rmtoll APB1LENR     TIM2EN        LL_APB1_GRP1_EnableClock\n

+  *         APB1LENR     TIM3EN        LL_APB1_GRP1_EnableClock\n

+  *         APB1LENR     TIM4EN        LL_APB1_GRP1_EnableClock\n

+  *         APB1LENR     TIM5EN        LL_APB1_GRP1_EnableClock\n

+  *         APB1LENR     TIM6EN        LL_APB1_GRP1_EnableClock\n

+  *         APB1LENR     TIM7EN        LL_APB1_GRP1_EnableClock\n

+  *         APB1LENR     TIM12EN       LL_APB1_GRP1_EnableClock\n

+  *         APB1LENR     TIM13EN       LL_APB1_GRP1_EnableClock\n

+  *         APB1LENR     TIM14EN       LL_APB1_GRP1_EnableClock\n

+  *         APB1LENR     LPTIM1EN      LL_APB1_GRP1_EnableClock\n

+  *         APB1LENR     WWDG2EN       LL_APB1_GRP1_EnableClock\n (*)

+  *         APB1LENR     SPI2EN        LL_APB1_GRP1_EnableClock\n

+  *         APB1LENR     SPI3EN        LL_APB1_GRP1_EnableClock\n

+  *         APB1LENR     SPDIFRXEN     LL_APB1_GRP1_EnableClock\n

+  *         APB1LENR     USART2EN      LL_APB1_GRP1_EnableClock\n

+  *         APB1LENR     USART3EN      LL_APB1_GRP1_EnableClock\n

+  *         APB1LENR     UART4EN       LL_APB1_GRP1_EnableClock\n

+  *         APB1LENR     UART5EN       LL_APB1_GRP1_EnableClock\n

+  *         APB1LENR     I2C1EN        LL_APB1_GRP1_EnableClock\n

+  *         APB1LENR     I2C2EN        LL_APB1_GRP1_EnableClock\n

+  *         APB1LENR     I2C3EN        LL_APB1_GRP1_EnableClock\n

+  *         APB1LENR     CECEN         LL_APB1_GRP1_EnableClock\n

+  *         APB1LENR     DAC12EN       LL_APB1_GRP1_EnableClock\n

+  *         APB1LENR     UART7EN       LL_APB1_GRP1_EnableClock\n

+  *         APB1LENR     UART8EN       LL_APB1_GRP1_EnableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC->APB1LENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC->APB1LENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Check if APB1 peripheral clock is enabled or not

+  * @rmtoll APB1LENR     TIM2EN        LL_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     TIM3EN        LL_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     TIM4EN        LL_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     TIM5EN        LL_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     TIM6EN        LL_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     TIM7EN        LL_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     TIM12EN       LL_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     TIM13EN       LL_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     TIM14EN       LL_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     LPTIM1EN      LL_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     WWDG2EN       LL_APB1_GRP1_IsEnabledClock\n (*)

+  *         APB1LENR     SPI2EN        LL_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     SPI3EN        LL_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     SPDIFRXEN     LL_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     USART2EN      LL_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     USART3EN      LL_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     UART4EN       LL_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     UART5EN       LL_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     I2C1EN        LL_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     I2C2EN        LL_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     I2C3EN        LL_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     CECEN         LL_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     DAC12EN       LL_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     UART7EN       LL_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     UART8EN       LL_APB1_GRP1_IsEnabledClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

+  *

+  *         (*) value not defined in all devices.

+  * @retval uint32_t

+*/

+__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)

+{

+  return ((READ_BIT(RCC->APB1LENR, Periphs) == Periphs)?1U:0U);

+}

+

+/**

+  * @brief  Disable APB1 peripherals clock.

+  * @rmtoll APB1LENR     TIM2EN        LL_APB1_GRP1_DisableClock\n

+  *         APB1LENR     TIM3EN        LL_APB1_GRP1_DisableClock\n

+  *         APB1LENR     TIM4EN        LL_APB1_GRP1_DisableClock\n

+  *         APB1LENR     TIM5EN        LL_APB1_GRP1_DisableClock\n

+  *         APB1LENR     TIM6EN        LL_APB1_GRP1_DisableClock\n

+  *         APB1LENR     TIM7EN        LL_APB1_GRP1_DisableClock\n

+  *         APB1LENR     TIM12EN       LL_APB1_GRP1_DisableClock\n

+  *         APB1LENR     TIM13EN       LL_APB1_GRP1_DisableClock\n

+  *         APB1LENR     TIM14EN       LL_APB1_GRP1_DisableClock\n

+  *         APB1LENR     LPTIM1EN      LL_APB1_GRP1_DisableClock\n

+  *         APB1LENR     WWDG2EN       LL_APB1_GRP1_DisableClock\n (*)

+  *         APB1LENR     SPI2EN        LL_APB1_GRP1_DisableClock\n

+  *         APB1LENR     SPI3EN        LL_APB1_GRP1_DisableClock\n

+  *         APB1LENR     SPDIFRXEN     LL_APB1_GRP1_DisableClock\n

+  *         APB1LENR     USART2EN      LL_APB1_GRP1_DisableClock\n

+  *         APB1LENR     USART3EN      LL_APB1_GRP1_DisableClock\n

+  *         APB1LENR     UART4EN       LL_APB1_GRP1_DisableClock\n

+  *         APB1LENR     UART5EN       LL_APB1_GRP1_DisableClock\n

+  *         APB1LENR     I2C1EN        LL_APB1_GRP1_DisableClock\n

+  *         APB1LENR     I2C2EN        LL_APB1_GRP1_DisableClock\n

+  *         APB1LENR     I2C3EN        LL_APB1_GRP1_DisableClock\n

+  *         APB1LENR     CECEN         LL_APB1_GRP1_DisableClock\n

+  *         APB1LENR     DAC12EN       LL_APB1_GRP1_DisableClock\n

+  *         APB1LENR     UART7EN       LL_APB1_GRP1_DisableClock\n

+  *         APB1LENR     UART8EN       LL_APB1_GRP1_DisableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC->APB1LENR, Periphs);

+}

+

+/**

+  * @brief  Force APB1 peripherals reset.

+  * @rmtoll APB1LRSTR    TIM2RST       LL_APB1_GRP1_ForceReset\n

+  *         APB1LRSTR    TIM3RST       LL_APB1_GRP1_ForceReset\n

+  *         APB1LRSTR    TIM4RST       LL_APB1_GRP1_ForceReset\n

+  *         APB1LRSTR    TIM5RST       LL_APB1_GRP1_ForceReset\n

+  *         APB1LRSTR    TIM6RST       LL_APB1_GRP1_ForceReset\n

+  *         APB1LRSTR    TIM7RST       LL_APB1_GRP1_ForceReset\n

+  *         APB1LRSTR    TIM12RST      LL_APB1_GRP1_ForceReset\n

+  *         APB1LRSTR    TIM13RST      LL_APB1_GRP1_ForceReset\n

+  *         APB1LRSTR    TIM14RST      LL_APB1_GRP1_ForceReset\n

+  *         APB1LRSTR    LPTIM1RST     LL_APB1_GRP1_ForceReset\n

+  *         APB1LRSTR    SPI2RST       LL_APB1_GRP1_ForceReset\n

+  *         APB1LRSTR    SPI3RST       LL_APB1_GRP1_ForceReset\n

+  *         APB1LRSTR    SPDIFRXRST    LL_APB1_GRP1_ForceReset\n

+  *         APB1LRSTR    USART2RST     LL_APB1_GRP1_ForceReset\n

+  *         APB1LRSTR    USART3RST     LL_APB1_GRP1_ForceReset\n

+  *         APB1LRSTR    UART4RST      LL_APB1_GRP1_ForceReset\n

+  *         APB1LRSTR    UART5RST      LL_APB1_GRP1_ForceReset\n

+  *         APB1LRSTR    I2C1RST       LL_APB1_GRP1_ForceReset\n

+  *         APB1LRSTR    I2C2RST       LL_APB1_GRP1_ForceReset\n

+  *         APB1LRSTR    I2C3RST       LL_APB1_GRP1_ForceReset\n

+  *         APB1LRSTR    CECRST        LL_APB1_GRP1_ForceReset\n

+  *         APB1LRSTR    DAC12RST      LL_APB1_GRP1_ForceReset\n

+  *         APB1LRSTR    UART7RST      LL_APB1_GRP1_ForceReset\n

+  *         APB1LRSTR    UART8RST      LL_APB1_GRP1_ForceReset

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

+  * @retval None

+*/

+__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)

+{

+  SET_BIT(RCC->APB1LRSTR, Periphs);

+}

+

+/**

+  * @brief  Release APB1 peripherals reset.

+  * @rmtoll APB1LRSTR    TIM2RST       LL_APB1_GRP1_ReleaseReset\n

+  *         APB1LRSTR    TIM3RST       LL_APB1_GRP1_ReleaseReset\n

+  *         APB1LRSTR    TIM4RST       LL_APB1_GRP1_ReleaseReset\n

+  *         APB1LRSTR    TIM5RST       LL_APB1_GRP1_ReleaseReset\n

+  *         APB1LRSTR    TIM6RST       LL_APB1_GRP1_ReleaseReset\n

+  *         APB1LRSTR    TIM7RST       LL_APB1_GRP1_ReleaseReset\n

+  *         APB1LRSTR    TIM12RST      LL_APB1_GRP1_ReleaseReset\n

+  *         APB1LRSTR    TIM13RST      LL_APB1_GRP1_ReleaseReset\n

+  *         APB1LRSTR    TIM14RST      LL_APB1_GRP1_ReleaseReset\n

+  *         APB1LRSTR    LPTIM1RST     LL_APB1_GRP1_ReleaseReset\n

+  *         APB1LRSTR    SPI2RST       LL_APB1_GRP1_ReleaseReset\n

+  *         APB1LRSTR    SPI3RST       LL_APB1_GRP1_ReleaseReset\n

+  *         APB1LRSTR    SPDIFRXRST    LL_APB1_GRP1_ReleaseReset\n

+  *         APB1LRSTR    USART2RST     LL_APB1_GRP1_ReleaseReset\n

+  *         APB1LRSTR    USART3RST     LL_APB1_GRP1_ReleaseReset\n

+  *         APB1LRSTR    UART4RST      LL_APB1_GRP1_ReleaseReset\n

+  *         APB1LRSTR    UART5RST      LL_APB1_GRP1_ReleaseReset\n

+  *         APB1LRSTR    I2C1RST       LL_APB1_GRP1_ReleaseReset\n

+  *         APB1LRSTR    I2C2RST       LL_APB1_GRP1_ReleaseReset\n

+  *         APB1LRSTR    I2C3RST       LL_APB1_GRP1_ReleaseReset\n

+  *         APB1LRSTR    CECRST        LL_APB1_GRP1_ReleaseReset\n

+  *         APB1LRSTR    DAC12RST      LL_APB1_GRP1_ReleaseReset\n

+  *         APB1LRSTR    UART7RST      LL_APB1_GRP1_ReleaseReset\n

+  *         APB1LRSTR    UART8RST      LL_APB1_GRP1_ReleaseReset

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

+  * @retval None

+*/

+__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC->APB1LRSTR, Periphs);

+}

+

+/**

+  * @brief  Enable APB1 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll APB1LLPENR   TIM2LPEN      LL_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   TIM3LPEN      LL_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   TIM4LPEN      LL_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   TIM5LPEN      LL_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   TIM6LPEN      LL_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   TIM7LPEN      LL_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   TIM12LPEN     LL_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   TIM13LPEN     LL_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   TIM14LPEN     LL_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   LPTIM1LPEN    LL_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   WWDG2LPEN     LL_APB1_GRP1_EnableClockSleep\n (*)

+  *         APB1LLPENR   SPI2LPEN      LL_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   SPI3LPEN      LL_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   SPDIFRXLPEN   LL_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   USART2LPEN    LL_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   USART3LPEN    LL_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   UART4LPEN     LL_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   UART5LPEN     LL_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   I2C1LPEN      LL_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   I2C2LPEN      LL_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   I2C3LPEN      LL_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   CECLPEN       LL_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   DAC12LPEN     LL_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   UART7LPEN     LL_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   UART8LPEN     LL_APB1_GRP1_EnableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_APB1_GRP1_EnableClockSleep(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC->APB1LLPENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC->APB1LLPENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Disable APB1 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll APB1LLPENR   TIM2LPEN      LL_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   TIM3LPEN      LL_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   TIM4LPEN      LL_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   TIM5LPEN      LL_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   TIM6LPEN      LL_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   TIM7LPEN      LL_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   TIM12LPEN     LL_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   TIM13LPEN     LL_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   TIM14LPEN     LL_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   LPTIM1LPEN    LL_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   WWDG2LPEN     LL_APB1_GRP1_DisableClockSleep\n (*)

+  *         APB1LLPENR   SPI2LPEN      LL_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   SPI3LPEN      LL_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   SPDIFRXLPEN   LL_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   USART2LPEN    LL_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   USART3LPEN    LL_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   UART4LPEN     LL_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   UART5LPEN     LL_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   I2C1LPEN      LL_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   I2C2LPEN      LL_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   I2C3LPEN      LL_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   CECLPEN       LL_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   DAC12LPEN     LL_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   UART7LPEN     LL_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   UART8LPEN     LL_APB1_GRP1_DisableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_APB1_GRP1_DisableClockSleep(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC->APB1LLPENR, Periphs);

+}

+

+/**

+  * @brief  Enable APB1 peripherals clock.

+  * @rmtoll APB1HENR     CRSEN         LL_APB1_GRP2_EnableClock\n

+  *         APB1HENR     SWPMIEN       LL_APB1_GRP2_EnableClock\n

+  *         APB1HENR     OPAMPEN       LL_APB1_GRP2_EnableClock\n

+  *         APB1HENR     MDIOSEN       LL_APB1_GRP2_EnableClock\n

+  *         APB1HENR     FDCANEN       LL_APB1_GRP2_EnableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

+  * @retval None

+*/

+__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC->APB1HENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC->APB1HENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Check if APB1 peripheral clock is enabled or not

+  * @rmtoll APB1HENR     CRSEN         LL_APB1_GRP2_IsEnabledClock\n

+  *         APB1HENR     SWPMIEN       LL_APB1_GRP2_IsEnabledClock\n

+  *         APB1HENR     OPAMPEN       LL_APB1_GRP2_IsEnabledClock\n

+  *         APB1HENR     MDIOSEN       LL_APB1_GRP2_IsEnabledClock\n

+  *         APB1HENR     FDCANEN       LL_APB1_GRP2_IsEnabledClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

+  * @retval uint32_t

+*/

+__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)

+{

+  return ((READ_BIT(RCC->APB1HENR, Periphs) == Periphs)?1U:0U);

+}

+

+/**

+  * @brief  Disable APB1 peripherals clock.

+  * @rmtoll APB1HENR     CRSEN         LL_APB1_GRP2_DisableClock\n

+  *         APB1HENR     SWPMIEN       LL_APB1_GRP2_DisableClock\n

+  *         APB1HENR     OPAMPEN       LL_APB1_GRP2_DisableClock\n

+  *         APB1HENR     MDIOSEN       LL_APB1_GRP2_DisableClock\n

+  *         APB1HENR     FDCANEN       LL_APB1_GRP2_DisableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

+  * @retval None

+*/

+__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC->APB1HENR, Periphs);

+}

+

+/**

+  * @brief  Force APB1 peripherals reset.

+  * @rmtoll APB1HRSTR    CRSRST        LL_APB1_GRP2_ForceReset\n

+  *         APB1HRSTR    SWPMIRST      LL_APB1_GRP2_ForceReset\n

+  *         APB1HRSTR    OPAMPRST      LL_APB1_GRP2_ForceReset\n

+  *         APB1HRSTR    MDIOSRST      LL_APB1_GRP2_ForceReset\n

+  *         APB1HRSTR    FDCANRST      LL_APB1_GRP2_ForceReset

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

+  * @retval None

+*/

+__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)

+{

+  SET_BIT(RCC->APB1HRSTR, Periphs);

+}

+

+/**

+  * @brief  Release APB1 peripherals reset.

+  * @rmtoll APB1HRSTR    CRSRST        LL_APB1_GRP2_ReleaseReset\n

+  *         APB1HRSTR    SWPMIRST      LL_APB1_GRP2_ReleaseReset\n

+  *         APB1HRSTR    OPAMPRST      LL_APB1_GRP2_ReleaseReset\n

+  *         APB1HRSTR    MDIOSRST      LL_APB1_GRP2_ReleaseReset\n

+  *         APB1HRSTR    FDCANRST      LL_APB1_GRP2_ReleaseReset

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

+  * @retval None

+*/

+__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC->APB1HRSTR, Periphs);

+}

+

+/**

+  * @brief  Enable APB1 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll APB1HLPENR   CRSLPEN       LL_APB1_GRP2_EnableClockSleep\n

+  *         APB1HLPENR   SWPMILPEN     LL_APB1_GRP2_EnableClockSleep\n

+  *         APB1HLPENR   OPAMPLPEN     LL_APB1_GRP2_EnableClockSleep\n

+  *         APB1HLPENR   MDIOSLPEN     LL_APB1_GRP2_EnableClockSleep\n

+  *         APB1HLPENR   FDCANLPEN     LL_APB1_GRP2_EnableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

+  * @retval None

+*/

+__STATIC_INLINE void LL_APB1_GRP2_EnableClockSleep(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC->APB1HLPENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC->APB1HLPENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Disable APB1 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll APB1HLPENR   CRSLPEN       LL_APB1_GRP2_DisableClockSleep\n

+  *         APB1HLPENR   SWPMILPEN     LL_APB1_GRP2_DisableClockSleep\n

+  *         APB1HLPENR   OPAMPLPEN     LL_APB1_GRP2_DisableClockSleep\n

+  *         APB1HLPENR   MDIOSLPEN     LL_APB1_GRP2_DisableClockSleep\n

+  *         APB1HLPENR   FDCANLPEN     LL_APB1_GRP2_DisableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

+  * @retval None

+*/

+__STATIC_INLINE void LL_APB1_GRP2_DisableClockSleep(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC->APB1HLPENR, Periphs);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup BUS_LL_EF_APB2 APB2

+  * @{

+  */

+

+/**

+  * @brief  Enable APB2 peripherals clock.

+  * @rmtoll APB2ENR      TIM1EN        LL_APB2_GRP1_EnableClock\n

+  *         APB2ENR      TIM8EN        LL_APB2_GRP1_EnableClock\n

+  *         APB2ENR      USART1EN      LL_APB2_GRP1_EnableClock\n

+  *         APB2ENR      USART6EN      LL_APB2_GRP1_EnableClock\n

+  *         APB2ENR      UART9EN       LL_APB2_GRP1_EnableClock\n (*)

+  *         APB2ENR      USART10EN     LL_APB2_GRP1_EnableClock\n (*)

+  *         APB2ENR      SPI1EN        LL_APB2_GRP1_EnableClock\n

+  *         APB2ENR      SPI4EN        LL_APB2_GRP1_EnableClock\n

+  *         APB2ENR      TIM15EN       LL_APB2_GRP1_EnableClock\n

+  *         APB2ENR      TIM16EN       LL_APB2_GRP1_EnableClock\n

+  *         APB2ENR      TIM17EN       LL_APB2_GRP1_EnableClock\n

+  *         APB2ENR      SPI5EN        LL_APB2_GRP1_EnableClock\n

+  *         APB2ENR      SAI1EN        LL_APB2_GRP1_EnableClock\n

+  *         APB2ENR      SAI2EN        LL_APB2_GRP1_EnableClock\n

+  *         APB2ENR      SAI3EN        LL_APB2_GRP1_EnableClock\n (*)

+  *         APB2ENR      DFSDM1EN      LL_APB2_GRP1_EnableClock\n

+  *         APB2ENR      HRTIMEN       LL_APB2_GRP1_EnableClock   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6

+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3 (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC->APB2ENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC->APB2ENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Check if APB2 peripheral clock is enabled or not

+  * @rmtoll APB2ENR      TIM1EN        LL_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      TIM8EN        LL_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      USART1EN      LL_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      USART6EN      LL_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      UART9EN       LL_APB2_GRP1_IsEnabledClock\n (*)

+  *         APB2ENR      USART10EN     LL_APB2_GRP1_IsEnabledClock\n (*)

+  *         APB2ENR      SPI1EN        LL_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      SPI4EN        LL_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      TIM15EN       LL_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      TIM16EN       LL_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      TIM17EN       LL_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      SPI5EN        LL_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      SAI1EN        LL_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      SAI2EN        LL_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      SAI3EN        LL_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      DFSDM1EN      LL_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      HRTIMEN       LL_APB2_GRP1_IsEnabledClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6

+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval uint32_t

+*/

+__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)

+{

+  return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs)?1U:0U);

+}

+

+/**

+  * @brief  Disable APB2 peripherals clock.

+  * @rmtoll APB2ENR      TIM1EN        LL_APB2_GRP1_DisableClock\n

+  *         APB2ENR      TIM8EN        LL_APB2_GRP1_DisableClock\n

+  *         APB2ENR      USART1EN      LL_APB2_GRP1_DisableClock\n

+  *         APB2ENR      USART6EN      LL_APB2_GRP1_DisableClock\n

+  *         APB2ENR      UART9EN       LL_APB2_GRP1_DisableClock\n (*)

+  *         APB2ENR      USART10EN     LL_APB2_GRP1_DisableClock\n (*)

+  *         APB2ENR      SPI1EN        LL_APB2_GRP1_DisableClock\n

+  *         APB2ENR      SPI4EN        LL_APB2_GRP1_DisableClock\n

+  *         APB2ENR      TIM15EN       LL_APB2_GRP1_DisableClock\n

+  *         APB2ENR      TIM16EN       LL_APB2_GRP1_DisableClock\n

+  *         APB2ENR      TIM17EN       LL_APB2_GRP1_DisableClock\n

+  *         APB2ENR      SPI5EN        LL_APB2_GRP1_DisableClock\n

+  *         APB2ENR      SAI1EN        LL_APB2_GRP1_DisableClock\n

+  *         APB2ENR      SAI2EN        LL_APB2_GRP1_DisableClock\n

+  *         APB2ENR      SAI3EN        LL_APB2_GRP1_DisableClock\n (*)

+  *         APB2ENR      DFSDM1EN      LL_APB2_GRP1_DisableClock\n

+  *         APB2ENR      HRTIMEN       LL_APB2_GRP1_DisableClock   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6

+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC->APB2ENR, Periphs);

+}

+

+/**

+  * @brief  Force APB2 peripherals reset.

+  * @rmtoll APB2RSTR     TIM1RST       LL_APB2_GRP1_ForceReset\n

+  *         APB2RSTR     TIM8RST       LL_APB2_GRP1_ForceReset\n

+  *         APB2RSTR     USART1RST     LL_APB2_GRP1_ForceReset\n

+  *         APB2RSTR     USART6RST     LL_APB2_GRP1_ForceReset\n

+  *         APB2ENR      UART9RST      LL_APB2_GRP1_ForceReset\n (*)

+  *         APB2ENR      USART10RST    LL_APB2_GRP1_ForceReset\n (*)

+  *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ForceReset\n

+  *         APB2RSTR     SPI4RST       LL_APB2_GRP1_ForceReset\n

+  *         APB2RSTR     TIM15RST      LL_APB2_GRP1_ForceReset\n

+  *         APB2RSTR     TIM16RST      LL_APB2_GRP1_ForceReset\n

+  *         APB2RSTR     TIM17RST      LL_APB2_GRP1_ForceReset\n

+  *         APB2RSTR     SPI5RST       LL_APB2_GRP1_ForceReset\n

+  *         APB2RSTR     SAI1RST       LL_APB2_GRP1_ForceReset\n

+  *         APB2RSTR     SAI2RST       LL_APB2_GRP1_ForceReset\n

+  *         APB2RSTR     SAI3RST       LL_APB2_GRP1_ForceReset\n (*)

+  *         APB2RSTR     DFSDM1RST     LL_APB2_GRP1_ForceReset\n

+  *         APB2RSTR     HRTIMRST      LL_APB2_GRP1_ForceReset   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6

+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3   (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM  (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)

+{

+  SET_BIT(RCC->APB2RSTR, Periphs);

+}

+

+/**

+  * @brief  Release APB2 peripherals reset.

+  * @rmtoll APB2RSTR     TIM1RST       LL_APB2_GRP1_ReleaseReset\n

+  *         APB2RSTR     TIM8RST       LL_APB2_GRP1_ReleaseReset\n

+  *         APB2RSTR     USART1RST     LL_APB2_GRP1_ReleaseReset\n

+  *         APB2RSTR     USART6RST     LL_APB2_GRP1_ReleaseReset\n

+  *         APB2ENR      UART9RST      LL_APB2_GRP1_ReleaseReset\n (*)

+  *         APB2ENR      USART10RST    LL_APB2_GRP1_ReleaseReset\n (*)

+  *         APB2RSTR     SPI1RST       LL_APB2_GRP1_ReleaseReset\n

+  *         APB2RSTR     SPI4RST       LL_APB2_GRP1_ReleaseReset\n

+  *         APB2RSTR     TIM15RST      LL_APB2_GRP1_ReleaseReset\n

+  *         APB2RSTR     TIM16RST      LL_APB2_GRP1_ReleaseReset\n

+  *         APB2RSTR     TIM17RST      LL_APB2_GRP1_ReleaseReset\n

+  *         APB2RSTR     SPI5RST       LL_APB2_GRP1_ReleaseReset\n

+  *         APB2RSTR     SAI1RST       LL_APB2_GRP1_ReleaseReset\n

+  *         APB2RSTR     SAI2RST       LL_APB2_GRP1_ReleaseReset\n

+  *         APB2RSTR     SAI3RST       LL_APB2_GRP1_ReleaseReset\n (*)

+  *         APB2RSTR     DFSDM1RST     LL_APB2_GRP1_ReleaseReset\n

+  *         APB2RSTR     HRTIMRST      LL_APB2_GRP1_ReleaseReset   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6

+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3   (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM  (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC->APB2RSTR, Periphs);

+}

+

+/**

+  * @brief  Enable APB2 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll APB2LPENR    TIM1LPEN      LL_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    TIM8LPEN      LL_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    USART1LPEN    LL_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    USART6LPEN    LL_APB2_GRP1_EnableClockSleep\n

+  *         APB2ENR      UART9LPEN     LL_APB2_GRP1_EnableClockSleep\n (*)

+  *         APB2ENR      USART10LPEN   LL_APB2_GRP1_EnableClockSleep\n (*)

+  *         APB2LPENR    SPI1LPEN      LL_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    SPI4LPEN      LL_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    TIM15LPEN     LL_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    TIM16LPEN     LL_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    TIM17LPEN     LL_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    SPI5LPEN      LL_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    SAI1LPEN      LL_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    SAI2LPEN      LL_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    SAI3LPEN      LL_APB2_GRP1_EnableClockSleep\n (*)

+  *         APB2LPENR    DFSDM1LPEN    LL_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    HRTIMLPEN     LL_APB2_GRP1_EnableClockSleep   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6

+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)

+  * @retval None

+*/

+__STATIC_INLINE void LL_APB2_GRP1_EnableClockSleep(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC->APB2LPENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Disable APB2 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll APB2LPENR    TIM1LPEN      LL_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    TIM8LPEN      LL_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    USART1LPEN    LL_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    USART6LPEN    LL_APB2_GRP1_DisableClockSleep\n

+  *         APB2ENR      UART9LPEN     LL_APB2_GRP1_DisableClockSleep\n (*)

+  *         APB2ENR      USART10LPEN   LL_APB2_GRP1_DisableClockSleep\n (*)

+  *         APB2LPENR    SPI1LPEN      LL_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    SPI4LPEN      LL_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    TIM15LPEN     LL_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    TIM16LPEN     LL_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    TIM17LPEN     LL_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    SPI5LPEN      LL_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    SAI1LPEN      LL_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    SAI2LPEN      LL_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    SAI3LPEN      LL_APB2_GRP1_DisableClockSleep\n (*)

+  *         APB2LPENR    DFSDM1LPEN    LL_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    HRTIMLPEN     LL_APB2_GRP1_DisableClockSleep   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6

+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)

+  * @retval None

+*/

+__STATIC_INLINE void LL_APB2_GRP1_DisableClockSleep(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC->APB2LPENR, Periphs);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup BUS_LL_EF_APB4 APB4

+  * @{

+  */

+

+/**

+  * @brief  Enable APB4 peripherals clock.

+  * @rmtoll APB4ENR      SYSCFGEN      LL_APB4_GRP1_EnableClock\n

+  *         APB4ENR      LPUART1EN     LL_APB4_GRP1_EnableClock\n

+  *         APB4ENR      SPI6EN        LL_APB4_GRP1_EnableClock\n

+  *         APB4ENR      I2C4EN        LL_APB4_GRP1_EnableClock\n

+  *         APB4ENR      LPTIM2EN      LL_APB4_GRP1_EnableClock\n

+  *         APB4ENR      LPTIM3EN      LL_APB4_GRP1_EnableClock\n

+  *         APB4ENR      LPTIM4EN      LL_APB4_GRP1_EnableClock\n  (*)

+  *         APB4ENR      LPTIM5EN      LL_APB4_GRP1_EnableClock\n  (*)

+  *         APB4ENR      DAC2EN        LL_APB4_GRP1_EnableClock\n  (*)

+  *         APB4ENR      COMP12EN      LL_APB4_GRP1_EnableClock\n

+  *         APB4ENR      VREFEN        LL_APB4_GRP1_EnableClock\n

+  *         APB4ENR      RTCAPBEN      LL_APB4_GRP1_EnableClock\n

+  *         APB4ENR      SAI4EN        LL_APB4_GRP1_EnableClock\n  (*)

+  *         APB4ENR      DTSEN         LL_APB4_GRP1_EnableClock\n  (*)

+  *         APB4ENR      DFSDM2EN      LL_APB4_GRP1_EnableClock    (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_APB4_GRP1_EnableClock(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC->APB4ENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC->APB4ENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Check if APB4 peripheral clock is enabled or not

+  * @rmtoll APB4ENR      SYSCFGEN      LL_APB4_GRP1_IsEnabledClock\n

+  *         APB4ENR      LPUART1EN     LL_APB4_GRP1_IsEnabledClock\n

+  *         APB4ENR      SPI6EN        LL_APB4_GRP1_IsEnabledClock\n

+  *         APB4ENR      I2C4EN        LL_APB4_GRP1_IsEnabledClock\n

+  *         APB4ENR      LPTIM2EN      LL_APB4_GRP1_IsEnabledClock\n

+  *         APB4ENR      LPTIM3EN      LL_APB4_GRP1_IsEnabledClock\n

+  *         APB4ENR      LPTIM4EN      LL_APB4_GRP1_IsEnabledClock\n (*)

+  *         APB4ENR      LPTIM5EN      LL_APB4_GRP1_IsEnabledClock\n (*)

+  *         APB4ENR      DAC2EN        LL_APB4_GRP1_IsEnabledClock\n (*)

+  *         APB4ENR      COMP12EN      LL_APB4_GRP1_IsEnabledClock\n

+  *         APB4ENR      VREFEN        LL_APB4_GRP1_IsEnabledClock\n

+  *         APB4ENR      RTCAPBEN      LL_APB4_GRP1_IsEnabledClock\n

+  *         APB4ENR      SAI4EN        LL_APB4_GRP1_IsEnabledClock\n (*)

+  *         APB4ENR      DTSEN         LL_APB4_GRP1_IsEnabledClock\n (*)

+  *         APB4ENR      DFSDM2EN      LL_APB4_GRP1_IsEnabledClock   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval uint32_t

+*/

+__STATIC_INLINE uint32_t LL_APB4_GRP1_IsEnabledClock(uint32_t Periphs)

+{

+  return ((READ_BIT(RCC->APB4ENR, Periphs) == Periphs)?1U:0U);

+}

+

+/**

+  * @brief  Disable APB4 peripherals clock.

+  * @rmtoll APB4ENR      SYSCFGEN      LL_APB4_GRP1_DisableClock\n

+  *         APB4ENR      LPUART1EN     LL_APB4_GRP1_DisableClock\n

+  *         APB4ENR      SPI6EN        LL_APB4_GRP1_DisableClock\n

+  *         APB4ENR      I2C4EN        LL_APB4_GRP1_DisableClock\n

+  *         APB4ENR      LPTIM2EN      LL_APB4_GRP1_DisableClock\n

+  *         APB4ENR      LPTIM3EN      LL_APB4_GRP1_DisableClock\n

+  *         APB4ENR      LPTIM4EN      LL_APB4_GRP1_DisableClock\n  (*)

+  *         APB4ENR      LPTIM5EN      LL_APB4_GRP1_DisableClock\n  (*)

+  *         APB4ENR      DAC2EN        LL_APB4_GRP1_DisableClock\n  (*)

+  *         APB4ENR      COMP12EN      LL_APB4_GRP1_DisableClock\n

+  *         APB4ENR      VREFEN        LL_APB4_GRP1_DisableClock\n

+  *         APB4ENR      RTCAPBEN      LL_APB4_GRP1_DisableClock\n

+  *         APB4ENR      SAI4EN        LL_APB4_GRP1_DisableClock\n  (*)

+  *         APB4ENR      DTSEN         LL_APB4_GRP1_DisableClock\n  (*)

+  *         APB4ENR      DFSDM2EN      LL_APB4_GRP1_DisableClock    (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_APB4_GRP1_DisableClock(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC->APB4ENR, Periphs);

+}

+

+/**

+  * @brief  Force APB4 peripherals reset.

+  * @rmtoll APB4RSTR     SYSCFGRST     LL_APB4_GRP1_ForceReset\n

+  *         APB4RSTR     LPUART1RST    LL_APB4_GRP1_ForceReset\n

+  *         APB4RSTR     SPI6RST       LL_APB4_GRP1_ForceReset\n

+  *         APB4RSTR     I2C4RST       LL_APB4_GRP1_ForceReset\n

+  *         APB4RSTR     LPTIM2RST     LL_APB4_GRP1_ForceReset\n

+  *         APB4RSTR     LPTIM3RST     LL_APB4_GRP1_ForceReset\n

+  *         APB4RSTR     LPTIM4RST     LL_APB4_GRP1_ForceReset\n  (*)

+  *         APB4RSTR     LPTIM5RST     LL_APB4_GRP1_ForceReset\n  (*)

+  *         APB4RSTR     DAC2EN        LL_APB4_GRP1_ForceReset\n  (*)

+  *         APB4RSTR     COMP12RST     LL_APB4_GRP1_ForceReset\n

+  *         APB4RSTR     VREFRST       LL_APB4_GRP1_ForceReset\n

+  *         APB4RSTR     SAI4RST       LL_APB4_GRP1_ForceReset\n  (*)

+  *         APB4RSTR     DTSRST        LL_APB4_GRP1_ForceReset\n  (*)

+  *         APB4RSTR      DFSDM2RST    LL_APB4_GRP1_ForceReset    (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_APB4_GRP1_ForceReset(uint32_t Periphs)

+{

+  SET_BIT(RCC->APB4RSTR, Periphs);

+}

+

+/**

+  * @brief  Release APB4 peripherals reset.

+  * @rmtoll APB4RSTR     SYSCFGRST     LL_APB4_GRP1_ReleaseReset\n

+  *         APB4RSTR     LPUART1RST    LL_APB4_GRP1_ReleaseReset\n

+  *         APB4RSTR     SPI6RST       LL_APB4_GRP1_ReleaseReset\n

+  *         APB4RSTR     I2C4RST       LL_APB4_GRP1_ReleaseReset\n

+  *         APB4RSTR     LPTIM2RST     LL_APB4_GRP1_ReleaseReset\n

+  *         APB4RSTR     LPTIM3RST     LL_APB4_GRP1_ReleaseReset\n

+  *         APB4RSTR     LPTIM4RST     LL_APB4_GRP1_ReleaseReset\n  (*)

+  *         APB4RSTR     LPTIM5RST     LL_APB4_GRP1_ReleaseReset\n  (*)

+  *         APB4RSTR     DAC2RST       LL_APB4_GRP1_ReleaseReset\n  (*)

+  *         APB4RSTR     COMP12RST     LL_APB4_GRP1_ReleaseReset\n

+  *         APB4RSTR     VREFRST       LL_APB4_GRP1_ReleaseReset\n

+  *         APB4RSTR     SAI4RST       LL_APB4_GRP1_ReleaseReset\n

+  *         APB4RSTR     DTSRST        LL_APB4_GRP1_ReleaseReset\n  (*)

+  *         APB4RSTR     DFSDM2RST     LL_APB4_GRP1_ReleaseReset    (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_APB4_GRP1_ReleaseReset(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC->APB4RSTR, Periphs);

+}

+

+/**

+  * @brief  Enable APB4 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll APB4LPENR    SYSCFGLPEN    LL_APB4_GRP1_EnableClockSleep\n

+  *         APB4LPENR    LPUART1LPEN   LL_APB4_GRP1_EnableClockSleep\n

+  *         APB4LPENR    SPI6LPEN      LL_APB4_GRP1_EnableClockSleep\n

+  *         APB4LPENR    I2C4LPEN      LL_APB4_GRP1_EnableClockSleep\n

+  *         APB4LPENR    LPTIM2LPEN    LL_APB4_GRP1_EnableClockSleep\n

+  *         APB4LPENR    LPTIM3LPEN    LL_APB4_GRP1_EnableClockSleep\n

+  *         APB4LPENR    LPTIM4LPEN    LL_APB4_GRP1_EnableClockSleep\n (*)

+  *         APB4LPENR    LPTIM5LPEN    LL_APB4_GRP1_EnableClockSleep\n (*)

+  *         APB4LPENR    DAC2LPEN      LL_APB4_GRP1_EnableClockSleep\n (*)

+  *         APB4LPENR    COMP12LPEN    LL_APB4_GRP1_EnableClockSleep\n

+  *         APB4LPENR    VREFLPEN      LL_APB4_GRP1_EnableClockSleep\n

+  *         APB4LPENR    RTCAPBLPEN    LL_APB4_GRP1_EnableClockSleep\n

+  *         APB4LPENR    SAI4LPEN      LL_APB4_GRP1_EnableClockSleep\n (*)

+  *         APB4LPENR    DTSLPEN       LL_APB4_GRP1_EnableClockSleep\n (*)

+  *         APB4LPENR    DFSDM2LPEN    LL_APB4_GRP1_EnableClockSleep   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_APB4_GRP1_EnableClockSleep(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC->APB4LPENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC->APB4LPENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Disable APB4 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll APB4LPENR    SYSCFGLPEN    LL_APB4_GRP1_DisableClockSleep\n

+  *         APB4LPENR    LPUART1LPEN   LL_APB4_GRP1_DisableClockSleep\n

+  *         APB4LPENR    SPI6LPEN      LL_APB4_GRP1_DisableClockSleep\n

+  *         APB4LPENR    I2C4LPEN      LL_APB4_GRP1_DisableClockSleep\n

+  *         APB4LPENR    LPTIM2LPEN    LL_APB4_GRP1_DisableClockSleep\n

+  *         APB4LPENR    LPTIM3LPEN    LL_APB4_GRP1_DisableClockSleep\n

+  *         APB4LPENR    LPTIM4LPEN    LL_APB4_GRP1_DisableClockSleep\n (*)

+  *         APB4LPENR    LPTIM5LPEN    LL_APB4_GRP1_DisableClockSleep\n (*)

+  *         APB4LPENR    DAC2LPEN      LL_APB4_GRP1_DisableClockSleep\n (*)

+  *         APB4LPENR    COMP12LPEN    LL_APB4_GRP1_DisableClockSleep\n

+  *         APB4LPENR    VREFLPEN      LL_APB4_GRP1_DisableClockSleep\n

+  *         APB4LPENR    RTCAPBLPEN    LL_APB4_GRP1_DisableClockSleep\n

+  *         APB4LPENR    SAI4LPEN      LL_APB4_GRP1_DisableClockSleep\n (*)

+  *         APB4LPENR    DTSLPEN       LL_APB4_GRP1_DisableClockSleep\n (*)

+  *         APB4LPENR    DFSDM2LPEN    LL_APB4_GRP1_DisableClockSleep   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_DAC2   (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_APB4_GRP1_DisableClockSleep(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC->APB4LPENR, Periphs);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup BUS_LL_EF_CLKAM

+  * @{

+  */

+

+/**

+  * @brief  Enable peripherals clock for CLKAM Mode.

+  * @rmtoll D3AMR / SRDAMR         BDMA          LL_CLKAM_Enable\n

+  *         D3AMR / SRDAMR         LPUART1       LL_CLKAM_Enable\n

+  *         D3AMR / SRDAMR         SPI6          LL_CLKAM_Enable\n

+  *         D3AMR / SRDAMR         I2C4          LL_CLKAM_Enable\n

+  *         D3AMR / SRDAMR         LPTIM2        LL_CLKAM_Enable\n

+  *         D3AMR / SRDAMR         LPTIM3        LL_CLKAM_Enable\n

+  *         D3AMR / SRDAMR         LPTIM4        LL_CLKAM_Enable\n  (*)

+  *         D3AMR / SRDAMR         LPTIM5        LL_CLKAM_Enable\n  (*)

+  *         D3AMR / SRDAMR         DAC2          LL_CLKAM_Enable\n  (*)

+  *         D3AMR / SRDAMR         COMP12        LL_CLKAM_Enable\n

+  *         D3AMR / SRDAMR         VREF          LL_CLKAM_Enable\n

+  *         D3AMR / SRDAMR         RTC           LL_CLKAM_Enable\n

+  *         D3AMR / SRDAMR         CRC           LL_CLKAM_Enable\n

+  *         D3AMR / SRDAMR         SAI4          LL_CLKAM_Enable\n  (*)

+  *         D3AMR / SRDAMR         ADC3          LL_CLKAM_Enable\n  (*)

+  *         D3AMR / SRDAMR         DTS           LL_CLKAM_Enable\n  (*)

+  *         D3AMR / SRDAMR         DFSDM2        LL_CLKAM_Enable\n  (*)

+  *         D3AMR / SRDAMR         BKPRAM        LL_CLKAM_Enable\n

+  *         D3AMR / SRDAMR         SRAM4         LL_CLKAM_Enable

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_CLKAM_PERIPH_BDMA

+  *         @arg @ref LL_CLKAM_PERIPH_LPUART1

+  *         @arg @ref LL_CLKAM_PERIPH_SPI6

+  *         @arg @ref LL_CLKAM_PERIPH_I2C4

+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM2

+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM3

+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM4 (*)

+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM5 (*)

+  *         @arg @ref LL_CLKAM_PERIPH_DAC2   (*)

+  *         @arg @ref LL_CLKAM_PERIPH_COMP12

+  *         @arg @ref LL_CLKAM_PERIPH_VREF

+  *         @arg @ref LL_CLKAM_PERIPH_RTC

+  *         @arg @ref LL_CLKAM_PERIPH_CRC

+  *         @arg @ref LL_CLKAM_PERIPH_SAI4   (*)

+  *         @arg @ref LL_CLKAM_PERIPH_ADC3   (*)

+  *         @arg @ref LL_CLKAM_PERIPH_DTS    (*)

+  *         @arg @ref LL_CLKAM_PERIPH_DFSDM2 (*)

+  *         @arg @ref LL_CLKAM_PERIPH_BKPRAM

+  *         @arg @ref LL_CLKAM_PERIPH_SRAM4

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_CLKAM_Enable(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+

+#if defined(RCC_D3AMR_BDMAAMEN)

+  SET_BIT(RCC->D3AMR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC->D3AMR, Periphs);

+#else

+  SET_BIT(RCC->SRDAMR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC->SRDAMR, Periphs);

+#endif /* RCC_D3AMR_BDMAAMEN */

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Disable peripherals clock for CLKAM Mode.

+  * @rmtoll D3AMR / SRDAMR        BDMA          LL_CLKAM_Disable\n

+  *         D3AMR / SRDAMR        LPUART1       LL_CLKAM_Disable\n

+  *         D3AMR / SRDAMR        SPI6          LL_CLKAM_Disable\n

+  *         D3AMR / SRDAMR        I2C4          LL_CLKAM_Disable\n

+  *         D3AMR / SRDAMR        LPTIM2        LL_CLKAM_Disable\n

+  *         D3AMR / SRDAMR        LPTIM3        LL_CLKAM_Disable\n

+  *         D3AMR / SRDAMR        LPTIM4        LL_CLKAM_Disable\n (*)

+  *         D3AMR / SRDAMR        LPTIM5        LL_CLKAM_Disable\n (*)

+  *         D3AMR / SRDAMR        DAC2          LL_CLKAM_Disable\n (*)

+  *         D3AMR / SRDAMR        COMP12        LL_CLKAM_Disable\n

+  *         D3AMR / SRDAMR        VREF          LL_CLKAM_Disable\n

+  *         D3AMR / SRDAMR        RTC           LL_CLKAM_Disable\n

+  *         D3AMR / SRDAMR        CRC           LL_CLKAM_Disable\n

+  *         D3AMR / SRDAMR        SAI4          LL_CLKAM_Disable\n (*)

+  *         D3AMR / SRDAMR        ADC3          LL_CLKAM_Disable\n (*)

+  *         D3AMR / SRDAMR        DTS           LL_CLKAM_Disable\n (*)

+  *         D3AMR / SRDAMR        DFSDM2        LL_CLKAM_Disable\n (*)

+  *         D3AMR / SRDAMR        BKPRAM        LL_CLKAM_Disable\n

+  *         D3AMR / SRDAMR        SRAM4         LL_CLKAM_Disable

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_CLKAM_PERIPH_BDMA

+  *         @arg @ref LL_CLKAM_PERIPH_LPUART1

+  *         @arg @ref LL_CLKAM_PERIPH_SPI6

+  *         @arg @ref LL_CLKAM_PERIPH_I2C4

+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM2

+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM3

+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM4 (*)

+  *         @arg @ref LL_CLKAM_PERIPH_LPTIM5 (*)

+  *         @arg @ref LL_CLKAM_PERIPH_DAC2   (*)

+  *         @arg @ref LL_CLKAM_PERIPH_COMP12

+  *         @arg @ref LL_CLKAM_PERIPH_VREF

+  *         @arg @ref LL_CLKAM_PERIPH_RTC

+  *         @arg @ref LL_CLKAM_PERIPH_CRC

+  *         @arg @ref LL_CLKAM_PERIPH_SAI4 (*)

+  *         @arg @ref LL_CLKAM_PERIPH_ADC3 (*)

+  *         @arg @ref LL_CLKAM_PERIPH_DTS  (*)

+  *         @arg @ref LL_CLKAM_PERIPH_DFSDM2  (*)

+  *         @arg @ref LL_CLKAM_PERIPH_BKPRAM

+  *         @arg @ref LL_CLKAM_PERIPH_SRAM4

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_CLKAM_Disable(uint32_t Periphs)

+{

+#if defined(RCC_D3AMR_BDMAAMEN)

+  CLEAR_BIT(RCC->D3AMR, Periphs);

+#else

+  CLEAR_BIT(RCC->SRDAMR, Periphs);

+#endif /* RCC_D3AMR_BDMAAMEN */

+}

+

+#if defined(RCC_CKGAENR_AXICKG)

+/**

+  * @}

+  */

+

+/**

+  * @brief  Enable clock gating for AXI bus peripherals.

+  * @rmtoll

+  * @param :

+  * @retval None

+*/

+__STATIC_INLINE void LL_CKGA_Enable(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC->CKGAENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC->CKGAENR, Periphs);

+  (void)tmpreg;

+}

+/**

+  * @}

+  */

+#endif /* RCC_CKGAENR_AXICKG */

+

+#if defined(RCC_CKGAENR_AXICKG)

+/**

+  * @}

+  */

+

+/**

+  * @brief  Disable  clock gating for AXI bus peripherals.

+  * @rmtoll

+  * @param :

+  * @retval None

+*/

+__STATIC_INLINE void LL_CKGA_Disable(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC->CKGAENR, Periphs);

+}

+/**

+  * @}

+  */

+#endif /* RCC_CKGAENR_AXICKG */

+

+

+#if defined(DUAL_CORE)

+/** @defgroup BUS_LL_EF_AHB3 AHB3

+  * @{

+  */

+

+/**

+  * @brief  Enable C1 AHB3 peripherals clock.

+  * @rmtoll AHB3ENR      MDMAEN        LL_C1_AHB3_GRP1_EnableClock\n

+  *         AHB3ENR      DMA2DEN       LL_C1_AHB3_GRP1_EnableClock\n

+  *         AHB3ENR      JPGDECEN      LL_C1_AHB3_GRP1_EnableClock\n

+  *         AHB3ENR      FMCEN         LL_C1_AHB3_GRP1_EnableClock\n

+  *         AHB3ENR      QSPIEN        LL_C1_AHB3_GRP1_EnableClock\n (*)

+  *         AHB3ENR      OSPI1EN       LL_C1_AHB3_GRP1_EnableClock\n (*)

+  *         AHB3ENR      OSPI2EN       LL_C1_AHB3_GRP1_EnableClock\n (*)

+  *         AHB3ENR      IOMNGREN      LL_C1_AHB3_GRP1_EnableClock\n (*)

+  *         AHB3ENR      OTFDEC1EN     LL_C1_AHB3_GRP1_EnableClock\n (*)

+  *         AHB3ENR      OTFDEC2EN     LL_C1_AHB3_GRP1_EnableClock\n (*)

+  *         AHB3ENR      GFXMMU        LL_C1_AHB3_GRP1_EnableClock\n (*)

+  *         AHB3ENR      SDMMC1EN      LL_C1_AHB3_GRP1_EnableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI    (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1   (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2   (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_IOMNGR  (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClock(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C1->AHB3ENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C1->AHB3ENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Check if C1 AHB3 peripheral clock is enabled or not

+  * @rmtoll AHB3ENR      MDMAEN        LL_C1_AHB3_GRP1_IsEnabledClock\n

+  *         AHB3ENR      DMA2DEN       LL_C1_AHB3_GRP1_IsEnabledClock\n

+  *         AHB3ENR      JPGDECEN      LL_C1_AHB3_GRP1_IsEnabledClock\n

+  *         AHB3ENR      FMCEN         LL_C1_AHB3_GRP1_IsEnabledClock\n

+  *         AHB3ENR      QSPIEN        LL_C1_AHB3_GRP1_IsEnabledClock\n (*)

+  *         AHB3ENR      OSPI1EN       LL_C1_AHB3_GRP1_IsEnabledClock\n (*)

+  *         AHB3ENR      OSPI2EN       LL_C1_AHB3_GRP1_IsEnabledClock\n (*)

+  *         AHB3ENR      IOMNGREN      LL_C1_AHB3_GRP1_IsEnabledClock\n (*)

+  *         AHB3ENR      OTFDEC1EN     LL_C1_AHB3_GRP1_IsEnabledClock\n (*)

+  *         AHB3ENR      OTFDEC2EN     LL_C1_AHB3_GRP1_IsEnabledClock\n (*)

+  *         AHB3ENR      GFXMMU        LL_C1_AHB3_GRP1_IsEnabledClock\n (*)

+  *         AHB3ENR      SDMMC1EN      LL_C1_AHB3_GRP1_IsEnabledClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI    (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1   (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2   (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_IOMNGR  (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

+  *

+  *         (*) value not defined in all devices.

+  * @retval uint32_t

+*/

+__STATIC_INLINE uint32_t LL_C1_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)

+{

+  return ((READ_BIT(RCC_C1->AHB3ENR, Periphs) == Periphs)?1U:0U);

+}

+

+/**

+  * @brief  Disable C1 AHB3 peripherals clock.

+  * @rmtoll AHB3ENR      MDMAEN        LL_C1_AHB3_GRP1_DisableClock\n

+  *         AHB3ENR      DMA2DEN       LL_C1_AHB3_GRP1_DisableClock\n

+  *         AHB3ENR      JPGDECEN      LL_C1_AHB3_GRP1_DisableClock\n

+  *         AHB3ENR      FMCEN         LL_C1_AHB3_GRP1_DisableClock\n

+  *         AHB3ENR      QSPIEN        LL_C1_AHB3_GRP1_DisableClock\n (*)

+  *         AHB3ENR      OSPI1EN       LL_C1_AHB3_GRP1_DisableClock\n (*)

+  *         AHB3ENR      OSPI2EN       LL_C1_AHB3_GRP1_DisableClock\n (*)

+  *         AHB3ENR      IOMNGREN      LL_C1_AHB3_GRP1_DisableClock\n (*)

+  *         AHB3ENR      OTFDEC1EN     LL_C1_AHB3_GRP1_DisableClock\n (*)

+  *         AHB3ENR      OTFDEC2EN     LL_C1_AHB3_GRP1_DisableClock\n (*)

+  *         AHB3ENR      GFXMMU        LL_C1_AHB3_GRP1_DisableClock\n (*)

+  *         AHB3ENR      SDMMC1EN      LL_C1_AHB3_GRP1_DisableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI    (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1   (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2   (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_IOMNGR  (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1 (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2 (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU  (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClock(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C1->AHB3ENR, Periphs);

+}

+

+/**

+  * @brief  Enable C1 AHB3 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll AHB3LPENR    MDMALPEN      LL_C1_AHB3_GRP1_EnableClockSleep\n

+  *         AHB3LPENR    DMA2DLPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n

+  *         AHB3LPENR    JPGDECLPEN    LL_C1_AHB3_GRP1_EnableClockSleep\n

+  *         AHB3LPENR    FMCLPEN       LL_C1_AHB3_GRP1_EnableClockSleep\n

+  *         AHB3LPENR    QSPILPEN      LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)

+  *         AHB3LPENR    OSPI1LPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)

+  *         AHB3LPENR    OSPI2LPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)

+  *         AHB3LPENR    IOMNGRLPEN    LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)

+  *         AHB3LPENR    OTFDEC1LPEN   LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)

+  *         AHB3LPENR    OTFDEC1LPEN   LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)

+  *         AHB3LPENR    GFXMMULPEN    LL_C1_AHB3_GRP1_EnableClockSleep\n  (*)

+  *         AHB3LPENR    SDMMC1LPEN    LL_C1_AHB3_GRP1_EnableClockSleep\n

+  *         AHB3LPENR    FLASHLPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n

+  *         AHB3LPENR    DTCM1LPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n

+  *         AHB3LPENR    DTCM2LPEN     LL_C1_AHB3_GRP1_EnableClockSleep\n

+  *         AHB3LPENR    ITCMLPEN      LL_C1_AHB3_GRP1_EnableClockSleep\n

+  *         AHB3LPENR    AXISRAMLPEN   LL_C1_AHB3_GRP1_EnableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1  (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2  (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU   (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C1->AHB3LPENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C1->AHB3LPENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Disable C1 AHB3 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll AHB3LPENR    MDMALPEN      LL_C1_AHB3_GRP1_DisableClockSleep\n

+  *         AHB3LPENR    DMA2DLPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n

+  *         AHB3LPENR    JPGDECLPEN    LL_C1_AHB3_GRP1_DisableClockSleep\n

+  *         AHB3LPENR    FMCLPEN       LL_C1_AHB3_GRP1_DisableClockSleep\n

+  *         AHB3LPENR    QSPILPEN      LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)

+  *         AHB3LPENR    OSPI1LPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)

+  *         AHB3LPENR    OSPI2LPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)

+  *         AHB3LPENR    IOMNGRLPEN    LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)

+  *         AHB3LPENR    OTFDEC1LPEN   LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)

+  *         AHB3LPENR    OTFDEC1LPEN   LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)

+  *         AHB3LPENR    GFXMMULPEN    LL_C1_AHB3_GRP1_DisableClockSleep\n  (*)

+  *         AHB3LPENR    SDMMC1LPEN    LL_C1_AHB3_GRP1_DisableClockSleep\n

+  *         AHB3LPENR    FLASHLPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n

+  *         AHB3LPENR    DTCM1LPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n

+  *         AHB3LPENR    DTCM2LPEN     LL_C1_AHB3_GRP1_DisableClockSleep\n

+  *         AHB3LPENR    ITCMLPEN      LL_C1_AHB3_GRP1_DisableClockSleep\n

+  *         AHB3LPENR    AXISRAMLPEN   LL_C1_AHB3_GRP1_DisableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI     (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1    (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2    (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OCTOSPIM (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC1  (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_OTFDEC2  (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_GFXMMU   (*)

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C1->AHB3LPENR, Periphs);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup BUS_LL_EF_AHB1 AHB1

+  * @{

+  */

+

+/**

+  * @brief  Enable C1 AHB1 peripherals clock.

+  * @rmtoll AHB1ENR      DMA1EN        LL_C1_AHB1_GRP1_EnableClock\n

+  *         AHB1ENR      DMA2EN        LL_C1_AHB1_GRP1_EnableClock\n

+  *         AHB1ENR      ADC12EN       LL_C1_AHB1_GRP1_EnableClock\n

+  *         AHB1ENR      CRCEN         LL_C1_AHB1_GRP1_EnableClock\n  (*)

+  *         AHB1ENR      ARTEN         LL_C1_AHB1_GRP1_EnableClock\n  (*)

+  *         AHB1ENR      ETH1MACEN     LL_C1_AHB1_GRP1_EnableClock\n  (*)

+  *         AHB1ENR      ETH1TXEN      LL_C1_AHB1_GRP1_EnableClock\n  (*)

+  *         AHB1ENR      ETH1RXEN      LL_C1_AHB1_GRP1_EnableClock\n  (*)

+  *         AHB1ENR      USB1OTGHSEN   LL_C1_AHB1_GRP1_EnableClock\n

+  *         AHB1ENR      USB1OTGHSULPIEN  LL_C1_AHB1_GRP1_EnableClock\n

+  *         AHB1ENR      USB2OTGHSEN   LL_C1_AHB1_GRP1_EnableClock\n   (*)

+  *         AHB1ENR      USB2OTGHSULPIEN  LL_C1_AHB1_GRP1_EnableClock  (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC  (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART  (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClock(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C1->AHB1ENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C1->AHB1ENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Check if C1 AHB1 peripheral clock is enabled or not

+  * @rmtoll AHB1ENR      DMA1EN        LL_C1_AHB1_GRP1_IsEnabledClock\n

+  *         AHB1ENR      DMA2EN        LL_C1_AHB1_GRP1_IsEnabledClock\n

+  *         AHB1ENR      ADC12EN       LL_C1_AHB1_GRP1_IsEnabledClock\n

+  *         AHB1ENR      CRCEN         LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)

+  *         AHB1ENR      ARTEN         LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)

+  *         AHB1ENR      ETH1MACEN     LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)

+  *         AHB1ENR      ETH1TXEN      LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)

+  *         AHB1ENR      ETH1RXEN      LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)

+  *         AHB1ENR      USB1OTGHSEN   LL_C1_AHB1_GRP1_IsEnabledClock\n

+  *         AHB1ENR      USB1OTGHSULPIEN  LL_C1_AHB1_GRP1_IsEnabledClock\n

+  *         AHB1ENR      USB2OTGHSEN   LL_C1_AHB1_GRP1_IsEnabledClock\n  (*)

+  *         AHB1ENR      USB2OTGHSULPIEN  LL_C1_AHB1_GRP1_IsEnabledClock (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC  (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART  (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval uint32_t

+*/

+__STATIC_INLINE uint32_t LL_C1_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)

+{

+  return ((READ_BIT(RCC_C1->AHB1ENR, Periphs) == Periphs)?1U:0U);

+}

+

+/**

+  * @brief  Disable C1 AHB1 peripherals clock.

+  * @rmtoll AHB1ENR      DMA1EN        LL_C1_AHB1_GRP1_DisableClock\n

+  *         AHB1ENR      DMA2EN        LL_C1_AHB1_GRP1_DisableClock\n

+  *         AHB1ENR      ADC12EN       LL_C1_AHB1_GRP1_DisableClock\n

+  *         AHB1ENR      CRCEN         LL_C1_AHB1_GRP1_DisableClock\n (*)

+  *         AHB1ENR      ARTEN         LL_C1_AHB1_GRP1_DisableClock\n (*)

+  *         AHB1ENR      ETH1MACEN     LL_C1_AHB1_GRP1_DisableClock\n (*)

+  *         AHB1ENR      ETH1TXEN      LL_C1_AHB1_GRP1_DisableClock\n (*)

+  *         AHB1ENR      ETH1RXEN      LL_C1_AHB1_GRP1_DisableClock\n (*)

+  *         AHB1ENR      USB1OTGHSEN   LL_C1_AHB1_GRP1_DisableClock\n

+  *         AHB1ENR      USB1OTGHSULPIEN  LL_C1_AHB1_GRP1_DisableClock\n

+  *         AHB1ENR      USB2OTGHSEN   LL_C1_AHB1_GRP1_DisableClock\n (*)

+  *         AHB1ENR      USB2OTGHSULPIEN  LL_C1_AHB1_GRP1_DisableClock (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC  (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART  (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClock(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C1->AHB1ENR, Periphs);

+}

+

+/**

+  * @brief  Enable C1 AHB1 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll AHB1LPENR    DMA1LPEN      LL_C1_AHB1_GRP1_EnableClockSleep\n

+  *         AHB1LPENR    DMA2LPEN      LL_C1_AHB1_GRP1_EnableClockSleep\n

+  *         AHB1LPENR    ADC12LPEN     LL_C1_AHB1_GRP1_EnableClockSleep\n

+  *         AHB1LPENR    CRCLPEN       LL_C1_AHB1_GRP1_EnableClockSleep\n (*)

+  *         AHB1LPENR    ARTLPEN       LL_C1_AHB1_GRP1_EnableClockSleep\n (*)

+  *         AHB1LPENR    ETH1MACLPEN   LL_C1_AHB1_GRP1_EnableClockSleep\n (*)

+  *         AHB1LPENR    ETH1TXLPEN    LL_C1_AHB1_GRP1_EnableClockSleep\n (*)

+  *         AHB1LPENR    ETH1RXLPEN    LL_C1_AHB1_GRP1_EnableClockSleep\n (*)

+  *         AHB1LPENR    USB1OTGHSLPEN  LL_C1_AHB1_GRP1_EnableClockSleep\n

+  *         AHB1LPENR    USB1OTGHSULPILPEN  LL_C1_AHB1_GRP1_EnableClockSleep\n

+  *         AHB1LPENR    USB2OTGHSLPEN  LL_C1_AHB1_GRP1_EnableClockSleep\n   (*)

+  *         AHB1LPENR    USB2OTGHSULPILPEN  LL_C1_AHB1_GRP1_EnableClockSleep (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC  (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART  (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C1->AHB1LPENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C1->AHB1LPENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Disable C1 AHB1 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll AHB1LPENR    DMA1LPEN      LL_C1_AHB1_GRP1_DisableClockSleep\n

+  *         AHB1LPENR    DMA2LPEN      LL_C1_AHB1_GRP1_DisableClockSleep\n

+  *         AHB1LPENR    ADC12LPEN     LL_C1_AHB1_GRP1_DisableClockSleep\n

+  *         AHB1LPENR    CRCLPEN       LL_C1_AHB1_GRP1_DisableClockSleep\n (*)

+  *         AHB1LPENR    ARTLPEN       LL_C1_AHB1_GRP1_DisableClockSleep\n (*)

+  *         AHB1LPENR    ETH1MACLPEN   LL_C1_AHB1_GRP1_DisableClockSleep\n (*)

+  *         AHB1LPENR    ETH1TXLPEN    LL_C1_AHB1_GRP1_DisableClockSleep\n (*)

+  *         AHB1LPENR    ETH1RXLPEN    LL_C1_AHB1_GRP1_DisableClockSleep\n (*)

+  *         AHB1LPENR    USB1OTGHSLPEN  LL_C1_AHB1_GRP1_DisableClockSleep\n

+  *         AHB1LPENR    USB1OTGHSULPILPEN  LL_C1_AHB1_GRP1_DisableClockSleep\n

+  *         AHB1LPENR    USB2OTGHSLPEN  LL_C1_AHB1_GRP1_DisableClockSleep\n   (*)

+  *         AHB1LPENR    USB2OTGHSULPILPEN  LL_C1_AHB1_GRP1_DisableClockSleep (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_CRC  (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART  (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC  (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX   (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX   (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS     (*)

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C1->AHB1LPENR, Periphs);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup BUS_LL_EF_AHB2 AHB2

+  * @{

+  */

+

+/**

+  * @brief  Enable C1 AHB2 peripherals clock.

+  * @rmtoll AHB2ENR      DCMIEN        LL_C1_AHB2_GRP1_EnableClock\n

+  *         AHB2ENR      HSEMEN        LL_C1_AHB2_GRP1_EnableClock\n (*)

+  *         AHB2ENR      CRYPEN        LL_C1_AHB2_GRP1_EnableClock\n (*)

+  *         AHB2ENR      HASHEN        LL_C1_AHB2_GRP1_EnableClock\n (*)

+  *         AHB2ENR      RNGEN         LL_C1_AHB2_GRP1_EnableClock\n

+  *         AHB2ENR      SDMMC2EN      LL_C1_AHB2_GRP1_EnableClock\n

+  *         AHB2ENR      BDMA1EN       LL_C1_AHB2_GRP1_EnableClock\n (*)

+  *         AHB2ENR      D2SRAM1EN     LL_C1_AHB2_GRP1_EnableClock\n

+  *         AHB2ENR      D2SRAM2EN     LL_C1_AHB2_GRP1_EnableClock\n

+  *         AHB2ENR      D2SRAM3EN     LL_C1_AHB2_GRP1_EnableClock   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClock(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C1->AHB2ENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C1->AHB2ENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Check if C1 AHB2 peripheral clock is enabled or not

+  * @rmtoll AHB2ENR      DCMIEN        LL_C1_AHB2_GRP1_IsEnabledClock\n

+  *         AHB2ENR      HSEMEN        LL_C1_AHB2_GRP1_IsEnabledClock\n (*)

+  *         AHB2ENR      CRYPEN        LL_C1_AHB2_GRP1_IsEnabledClock\n (*)

+  *         AHB2ENR      HASHEN        LL_C1_AHB2_GRP1_IsEnabledClock\n (*)

+  *         AHB2ENR      RNGEN         LL_C1_AHB2_GRP1_IsEnabledClock\n

+  *         AHB2ENR      SDMMC2EN      LL_C1_AHB2_GRP1_IsEnabledClock\n

+  *         AHB2ENR      BDMA1EN       LL_C1_AHB2_GRP1_IsEnabledClock\n (*)

+  *         AHB2ENR      D2SRAM1EN     LL_C1_AHB2_GRP1_IsEnabledClock\n

+  *         AHB2ENR      D2SRAM2EN     LL_C1_AHB2_GRP1_IsEnabledClock\n

+  *         AHB2ENR      D2SRAM3EN     LL_C1_AHB2_GRP1_IsEnabledClock   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval uint32_t

+*/

+__STATIC_INLINE uint32_t LL_C1_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)

+{

+  return ((READ_BIT(RCC_C1->AHB2ENR, Periphs) == Periphs)?1U:0U);

+}

+

+/**

+  * @brief  Disable C1 AHB2 peripherals clock.

+  * @rmtoll AHB2ENR      DCMIEN        LL_C1_AHB2_GRP1_DisableClock\n

+  *         AHB2ENR      HSEMEN        LL_C1_AHB2_GRP1_DisableClock\n (*)

+  *         AHB2ENR      CRYPEN        LL_C1_AHB2_GRP1_DisableClock\n (*)

+  *         AHB2ENR      HASHEN        LL_C1_AHB2_GRP1_DisableClock\n (*)

+  *         AHB2ENR      RNGEN         LL_C1_AHB2_GRP1_DisableClock\n

+  *         AHB2ENR      SDMMC2EN      LL_C1_AHB2_GRP1_DisableClock\n

+  *         AHB2ENR      BDMA1EN       LL_C1_AHB2_GRP1_DisableClock\n (*)

+  *         AHB2ENR      D2SRAM1EN     LL_C1_AHB2_GRP1_DisableClock\n

+  *         AHB2ENR      D2SRAM2EN     LL_C1_AHB2_GRP1_DisableClock\n

+  *         AHB2ENR      D2SRAM3EN     LL_C1_AHB2_GRP1_DisableClock   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HSEM (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDMA1 (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClock(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C1->AHB2ENR, Periphs);

+}

+

+/**

+  * @brief  Enable C1 AHB2 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll AHB2LPENR    DCMILPEN      LL_C1_AHB2_GRP1_EnableClockSleep\n

+  *         AHB2LPENR    CRYPLPEN      LL_C1_AHB2_GRP1_EnableClockSleep\n (*)

+  *         AHB2LPENR    HASHLPEN      LL_C1_AHB2_GRP1_EnableClockSleep\n (*)

+  *         AHB2LPENR    RNGLPEN       LL_C1_AHB2_GRP1_EnableClockSleep\n

+  *         AHB2LPENR    SDMMC2LPEN    LL_C1_AHB2_GRP1_EnableClockSleep\n

+  *         AHB2LPENR    SDMMC2LPEN    LL_C1_AHB2_GRP1_EnableClockSleep\n

+  *         AHB2LPENR    BDAM1LPEN     LL_C1_AHB2_GRP1_EnableClockSleep\n (*)

+  *         AHB2LPENR    D2SRAM2LPEN   LL_C1_AHB2_GRP1_EnableClockSleep\n

+  *         AHB2LPENR    D2SRAM3LPEN   LL_C1_AHB2_GRP1_EnableClockSleep   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDAM1 (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C1->AHB2LPENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C1->AHB2LPENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Disable C1 AHB2 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll AHB2LPENR    DCMILPEN      LL_C1_AHB2_GRP1_DisableClockSleep\n

+  *         AHB2LPENR    CRYPLPEN      LL_C1_AHB2_GRP1_DisableClockSleep\n (*)

+  *         AHB2LPENR    HASHLPEN      LL_C1_AHB2_GRP1_DisableClockSleep\n (*)

+  *         AHB2LPENR    RNGLPEN       LL_C1_AHB2_GRP1_DisableClockSleep\n

+  *         AHB2LPENR    SDMMC2LPEN    LL_C1_AHB2_GRP1_DisableClockSleep\n

+  *         AHB2LPENR    BDAM1LPEN     LL_C1_AHB2_GRP1_DisableClockSleep\n (*)

+  *         AHB2LPENR    D2SRAM1LPEN   LL_C1_AHB2_GRP1_DisableClockSleep\n

+  *         AHB2LPENR    D2SRAM2LPEN   LL_C1_AHB2_GRP1_DisableClockSleep\n

+  *         AHB2LPENR    D2SRAM3LPEN   LL_C1_AHB2_GRP1_DisableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_BDAM1 (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3 (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C1->AHB2LPENR, Periphs);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup BUS_LL_EF_AHB4 AHB4

+  * @{

+  */

+

+/**

+  * @brief  Enable C1 AHB4 peripherals clock.

+  * @rmtoll AHB4ENR      GPIOAEN       LL_C1_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      GPIOBEN       LL_C1_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      GPIOCEN       LL_C1_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      GPIODEN       LL_C1_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      GPIOEEN       LL_C1_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      GPIOFEN       LL_C1_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      GPIOGEN       LL_C1_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      GPIOHEN       LL_C1_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      GPIOIEN       LL_C1_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      GPIOJEN       LL_C1_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      GPIOKEN       LL_C1_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      CRCEN         LL_C1_AHB4_GRP1_EnableClock\n (*)

+  *         AHB4ENR      BDMAEN        LL_C1_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      ADC3EN        LL_C1_AHB4_GRP1_EnableClock\n (*)

+  *         AHB4ENR      HSEMEN        LL_C1_AHB4_GRP1_EnableClock\n (*)

+  *         AHB4ENR      BKPRAMEN      LL_C1_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      SRAM4EN       LL_C1_AHB4_GRP1_EnableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClock(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C1->AHB4ENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C1->AHB4ENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Check if C1 AHB4 peripheral clock is enabled or not

+  * @rmtoll AHB4ENR      GPIOAEN       LL_C1_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      GPIOBEN       LL_C1_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      GPIOCEN       LL_C1_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      GPIODEN       LL_C1_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      GPIOEEN       LL_C1_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      GPIOFEN       LL_C1_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      GPIOGEN       LL_C1_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      GPIOHEN       LL_C1_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      GPIOIEN       LL_C1_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      GPIOJEN       LL_C1_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      GPIOKEN       LL_C1_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      CRCEN         LL_C1_AHB4_GRP1_IsEnabledClock\n (*)

+  *         AHB4ENR      BDMAEN        LL_C1_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      ADC3EN        LL_C1_AHB4_GRP1_IsEnabledClock\n (*)

+  *         AHB4ENR      HSEMEN        LL_C1_AHB4_GRP1_IsEnabledClock\n (*)

+  *         AHB4ENR      BKPRAMEN      LL_C1_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      SRAM4EN       LL_C1_AHB4_GRP1_IsEnabledClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4

+  *

+  *         (*) value not defined in all devices.

+  * @retval uint32_t

+*/

+__STATIC_INLINE uint32_t LL_C1_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)

+{

+  return ((READ_BIT(RCC_C1->AHB4ENR, Periphs) == Periphs)?1U:0U);

+}

+

+/**

+  * @brief  Disable C1 AHB4 peripherals clock.

+  * @rmtoll AHB4ENR      GPIOAEN       LL_C1_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      GPIOBEN       LL_C1_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      GPIOCEN       LL_C1_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      GPIODEN       LL_C1_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      GPIOEEN       LL_C1_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      GPIOFEN       LL_C1_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      GPIOGEN       LL_C1_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      GPIOHEN       LL_C1_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      GPIOIEN       LL_C1_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      GPIOJEN       LL_C1_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      GPIOKEN       LL_C1_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      CRCEN         LL_C1_AHB4_GRP1_DisableClock\n (*)

+  *         AHB4ENR      BDMAEN        LL_C1_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      ADC3EN        LL_C1_AHB4_GRP1_DisableClock\n (*)

+  *         AHB4ENR      HSEMEN        LL_C1_AHB4_GRP1_DisableClock\n (*)

+  *         AHB4ENR      BKPRAMEN      LL_C1_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      SRAM4EN       LL_C1_AHB4_GRP1_DisableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClock(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C1->AHB4ENR, Periphs);

+}

+

+/**

+  * @brief  Enable C1 AHB4 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll AHB4LPENR    GPIOALPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    GPIOBLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    GPIOCLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    GPIODLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    GPIOELPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    GPIOFLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    GPIOGLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    GPIOHLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    GPIOILPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    GPIOJLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    GPIOKLPEN     LL_C1_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    CRCLPEN       LL_C1_AHB4_GRP1_EnableClockSleep\n (*)

+  *         AHB4LPENR    BDMALPEN      LL_C1_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    ADC3LPEN      LL_C1_AHB4_GRP1_EnableClockSleep\n (*)

+  *         AHB4LPENR    BKPRAMLPEN    LL_C1_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    SRAM4LPEN     LL_C1_AHB4_GRP1_EnableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C1->AHB4LPENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C1->AHB4LPENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Disable C1 AHB4 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll AHB4LPENR    GPIOALPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    GPIOBLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    GPIOCLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    GPIODLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    GPIOELPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    GPIOFLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    GPIOGLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    GPIOHLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    GPIOILPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    GPIOJLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    GPIOKLPEN     LL_C1_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    CRCLPEN       LL_C1_AHB4_GRP1_DisableClockSleep\n (*)

+  *         AHB4LPENR    BDMALPEN      LL_C1_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    ADC3LPEN      LL_C1_AHB4_GRP1_DisableClockSleep\n (*)

+  *         AHB4LPENR    BKPRAMLPEN    LL_C1_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    SRAM4LPEN     LL_C1_AHB4_GRP1_DisableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC  (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3 (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C1->AHB4LPENR, Periphs);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup BUS_LL_EF_APB3 APB3

+  * @{

+  */

+

+/**

+  * @brief  Enable C1 APB3 peripherals clock.

+  * @rmtoll APB3ENR      LTDCEN        LL_C1_APB3_GRP1_EnableClock\n (*)

+  *         APB3ENR      DSIEN         LL_C1_APB3_GRP1_EnableClock\n (*)

+  *         APB3ENR      WWDG1EN       LL_C1_APB3_GRP1_EnableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)

+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI  (*)

+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_APB3_GRP1_EnableClock(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C1->APB3ENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C1->APB3ENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Check if C1 APB3 peripheral clock is enabled or not

+  * @rmtoll APB3ENR      LTDCEN        LL_C1_APB3_GRP1_IsEnabledClock\n (*)

+  *         APB3ENR      DSIEN         LL_C1_APB3_GRP1_IsEnabledClock\n (*)

+  *         APB3ENR      WWDG1EN       LL_C1_APB3_GRP1_IsEnabledClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)

+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI  (*)

+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1

+  *

+  *         (*) value not defined in all devices.

+  * @retval uint32_t

+*/

+__STATIC_INLINE uint32_t LL_C1_APB3_GRP1_IsEnabledClock(uint32_t Periphs)

+{

+  return ((READ_BIT(RCC_C1->APB3ENR, Periphs) == Periphs)?1U:0U);

+}

+

+/**

+  * @brief  Disable C1 APB3 peripherals clock.

+  * @rmtoll APB3ENR      LTDCEN        LL_C1_APB3_GRP1_DisableClock\n (*)

+  *         APB3ENR      DSIEN         LL_C1_APB3_GRP1_DisableClock\n (*)

+  *         APB3ENR      WWDG1EN       LL_C1_APB3_GRP1_DisableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)

+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI  (*)

+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_APB3_GRP1_DisableClock(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C1->APB3ENR, Periphs);

+}

+

+/**

+  * @brief  Enable C1 APB3 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll APB3LPENR    LTDCLPEN      LL_C1_APB3_GRP1_EnableClockSleep\n (*)

+  *         APB3LPENR    DSILPEN       LL_C1_APB3_GRP1_EnableClockSleep\n (*)

+  *         APB3LPENR    WWDG1LPEN     LL_C1_APB3_GRP1_EnableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)

+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI  (*)

+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_APB3_GRP1_EnableClockSleep(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C1->APB3LPENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C1->APB3LPENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Disable C1 APB3 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll APB3LPENR    LTDCLPEN      LL_C1_APB3_GRP1_DisableClockSleep\n (*)

+  *         APB3LPENR    DSILPEN       LL_C1_APB3_GRP1_DisableClockSleep\n (*)

+  *         APB3LPENR    WWDG1LPEN     LL_C1_APB3_GRP1_DisableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC (*)

+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI  (*)

+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_APB3_GRP1_DisableClockSleep(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C1->APB3LPENR, Periphs);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup BUS_LL_EF_APB1 APB1

+  * @{

+  */

+

+/**

+  * @brief  Enable C1 APB1 peripherals clock.

+  * @rmtoll APB1LENR     TIM2EN        LL_C1_APB1_GRP1_EnableClock\n

+  *         APB1LENR     TIM3EN        LL_C1_APB1_GRP1_EnableClock\n

+  *         APB1LENR     TIM4EN        LL_C1_APB1_GRP1_EnableClock\n

+  *         APB1LENR     TIM5EN        LL_C1_APB1_GRP1_EnableClock\n

+  *         APB1LENR     TIM6EN        LL_C1_APB1_GRP1_EnableClock\n

+  *         APB1LENR     TIM7EN        LL_C1_APB1_GRP1_EnableClock\n

+  *         APB1LENR     TIM12EN       LL_C1_APB1_GRP1_EnableClock\n

+  *         APB1LENR     TIM13EN       LL_C1_APB1_GRP1_EnableClock\n

+  *         APB1LENR     TIM14EN       LL_C1_APB1_GRP1_EnableClock\n

+  *         APB1LENR     LPTIM1EN      LL_C1_APB1_GRP1_EnableClock\n

+  *         APB1LENR     WWDG2EN       LL_C1_APB1_GRP1_EnableClock\n (*)

+  *         APB1LENR     SPI2EN        LL_C1_APB1_GRP1_EnableClock\n

+  *         APB1LENR     SPI3EN        LL_C1_APB1_GRP1_EnableClock\n

+  *         APB1LENR     SPDIFRXEN     LL_C1_APB1_GRP1_EnableClock\n

+  *         APB1LENR     USART2EN      LL_C1_APB1_GRP1_EnableClock\n

+  *         APB1LENR     USART3EN      LL_C1_APB1_GRP1_EnableClock\n

+  *         APB1LENR     UART4EN       LL_C1_APB1_GRP1_EnableClock\n

+  *         APB1LENR     UART5EN       LL_C1_APB1_GRP1_EnableClock\n

+  *         APB1LENR     I2C1EN        LL_C1_APB1_GRP1_EnableClock\n

+  *         APB1LENR     I2C2EN        LL_C1_APB1_GRP1_EnableClock\n

+  *         APB1LENR     I2C3EN        LL_C1_APB1_GRP1_EnableClock\n

+  *         APB1LENR     CECEN         LL_C1_APB1_GRP1_EnableClock\n

+  *         APB1LENR     DAC12EN       LL_C1_APB1_GRP1_EnableClock\n

+  *         APB1LENR     UART7EN       LL_C1_APB1_GRP1_EnableClock\n

+  *         APB1LENR     UART8EN       LL_C1_APB1_GRP1_EnableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_APB1_GRP1_EnableClock(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C1->APB1LENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C1->APB1LENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Check if C1 APB1 peripheral clock is enabled or not

+  * @rmtoll APB1LENR     TIM2EN        LL_C1_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     TIM3EN        LL_C1_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     TIM4EN        LL_C1_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     TIM5EN        LL_C1_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     TIM6EN        LL_C1_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     TIM7EN        LL_C1_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     TIM12EN       LL_C1_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     TIM13EN       LL_C1_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     TIM14EN       LL_C1_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     LPTIM1EN      LL_C1_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     WWDG2EN       LL_C1_APB1_GRP1_IsEnabledClock\n (*)

+  *         APB1LENR     SPI2EN        LL_C1_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     SPI3EN        LL_C1_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     SPDIFRXEN     LL_C1_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     USART2EN      LL_C1_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     USART3EN      LL_C1_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     UART4EN       LL_C1_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     UART5EN       LL_C1_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     I2C1EN        LL_C1_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     I2C2EN        LL_C1_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     I2C3EN        LL_C1_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     CECEN         LL_C1_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     DAC12EN       LL_C1_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     UART7EN       LL_C1_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     UART8EN       LL_C1_APB1_GRP1_IsEnabledClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

+  *

+  *         (*) value not defined in all devices.

+  * @retval uint32_t

+*/

+__STATIC_INLINE uint32_t LL_C1_APB1_GRP1_IsEnabledClock(uint32_t Periphs)

+{

+  return ((READ_BIT(RCC_C1->APB1LENR, Periphs) == Periphs)?1U:0U);

+}

+

+/**

+  * @brief  Disable C1 APB1 peripherals clock.

+  * @rmtoll APB1LENR     TIM2EN        LL_C1_APB1_GRP1_DisableClock\n

+  *         APB1LENR     TIM3EN        LL_C1_APB1_GRP1_DisableClock\n

+  *         APB1LENR     TIM4EN        LL_C1_APB1_GRP1_DisableClock\n

+  *         APB1LENR     TIM5EN        LL_C1_APB1_GRP1_DisableClock\n

+  *         APB1LENR     TIM6EN        LL_C1_APB1_GRP1_DisableClock\n

+  *         APB1LENR     TIM7EN        LL_C1_APB1_GRP1_DisableClock\n

+  *         APB1LENR     TIM12EN       LL_C1_APB1_GRP1_DisableClock\n

+  *         APB1LENR     TIM13EN       LL_C1_APB1_GRP1_DisableClock\n

+  *         APB1LENR     TIM14EN       LL_C1_APB1_GRP1_DisableClock\n

+  *         APB1LENR     LPTIM1EN      LL_C1_APB1_GRP1_DisableClock\n

+  *         APB1LENR     WWDG2EN       LL_C1_APB1_GRP1_DisableClock\n (*)

+  *         APB1LENR     SPI2EN        LL_C1_APB1_GRP1_DisableClock\n

+  *         APB1LENR     SPI3EN        LL_C1_APB1_GRP1_DisableClock\n

+  *         APB1LENR     SPDIFRXEN     LL_C1_APB1_GRP1_DisableClock\n

+  *         APB1LENR     USART2EN      LL_C1_APB1_GRP1_DisableClock\n

+  *         APB1LENR     USART3EN      LL_C1_APB1_GRP1_DisableClock\n

+  *         APB1LENR     UART4EN       LL_C1_APB1_GRP1_DisableClock\n

+  *         APB1LENR     UART5EN       LL_C1_APB1_GRP1_DisableClock\n

+  *         APB1LENR     I2C1EN        LL_C1_APB1_GRP1_DisableClock\n

+  *         APB1LENR     I2C2EN        LL_C1_APB1_GRP1_DisableClock\n

+  *         APB1LENR     I2C3EN        LL_C1_APB1_GRP1_DisableClock\n

+  *         APB1LENR     CECEN         LL_C1_APB1_GRP1_DisableClock\n

+  *         APB1LENR     DAC12EN       LL_C1_APB1_GRP1_DisableClock\n

+  *         APB1LENR     UART7EN       LL_C1_APB1_GRP1_DisableClock\n

+  *         APB1LENR     UART8EN       LL_C1_APB1_GRP1_DisableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

+  *

+  *         (*) value not defined in all devices.

+  * @retval uint32_t

+*/

+__STATIC_INLINE void LL_C1_APB1_GRP1_DisableClock(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C1->APB1LENR, Periphs);

+}

+

+/**

+  * @brief  Enable C1 APB1 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll APB1LLPENR   TIM2LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   TIM3LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   TIM4LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   TIM5LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   TIM6LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   TIM7LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   TIM12LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   TIM13LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   TIM14LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   LPTIM1LPEN    LL_C1_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   WWDG2LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n (*)

+  *         APB1LLPENR   SPI2LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   SPI3LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   SPDIFRXLPEN   LL_C1_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   USART2LPEN    LL_C1_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   USART3LPEN    LL_C1_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   UART4LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   UART5LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   I2C1LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   I2C2LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   I2C3LPEN      LL_C1_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   CECLPEN       LL_C1_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   DAC12LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   UART7LPEN     LL_C1_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   UART8LPEN     LL_C1_APB1_GRP1_EnableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_APB1_GRP1_EnableClockSleep(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C1->APB1LLPENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C1->APB1LLPENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Disable C1 APB1 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll APB1LLPENR   TIM2LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   TIM3LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   TIM4LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   TIM5LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   TIM6LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   TIM7LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   TIM12LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   TIM13LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   TIM14LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   LPTIM1LPEN    LL_C1_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   WWDG2LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n (*)

+  *         APB1LLPENR   SPI2LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   SPI3LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   SPDIFRXLPEN   LL_C1_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   USART2LPEN    LL_C1_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   USART3LPEN    LL_C1_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   UART4LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   UART5LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   I2C1LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   I2C2LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   I2C3LPEN      LL_C1_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   CECLPEN       LL_C1_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   DAC12LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   UART7LPEN     LL_C1_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   UART8LPEN     LL_C1_APB1_GRP1_DisableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2 (*)

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_APB1_GRP1_DisableClockSleep(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C1->APB1LLPENR, Periphs);

+}

+

+/**

+  * @brief  Enable C1 APB1 peripherals clock.

+  * @rmtoll APB1HENR     CRSEN         LL_C1_APB1_GRP2_EnableClock\n

+  *         APB1HENR     SWPMIEN       LL_C1_APB1_GRP2_EnableClock\n

+  *         APB1HENR     OPAMPEN       LL_C1_APB1_GRP2_EnableClock\n

+  *         APB1HENR     MDIOSEN       LL_C1_APB1_GRP2_EnableClock\n

+  *         APB1HENR     FDCANEN       LL_C1_APB1_GRP2_EnableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_APB1_GRP2_EnableClock(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C1->APB1HENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C1->APB1HENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Check if C1 APB1 peripheral clock is enabled or not

+  * @rmtoll APB1HENR     CRSEN         LL_C1_APB1_GRP2_IsEnabledClock\n

+  *         APB1HENR     SWPMIEN       LL_C1_APB1_GRP2_IsEnabledClock\n

+  *         APB1HENR     OPAMPEN       LL_C1_APB1_GRP2_IsEnabledClock\n

+  *         APB1HENR     MDIOSEN       LL_C1_APB1_GRP2_IsEnabledClock\n

+  *         APB1HENR     FDCANEN       LL_C1_APB1_GRP2_IsEnabledClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

+  * @retval uint32_t

+*/

+__STATIC_INLINE uint32_t LL_C1_APB1_GRP2_IsEnabledClock(uint32_t Periphs)

+{

+  return ((READ_BIT(RCC_C1->APB1HENR, Periphs) == Periphs)?1U:0U);

+}

+

+/**

+  * @brief  Disable C1 APB1 peripherals clock.

+  * @rmtoll APB1HENR     CRSEN         LL_C1_APB1_GRP2_DisableClock\n

+  *         APB1HENR     SWPMIEN       LL_C1_APB1_GRP2_DisableClock\n

+  *         APB1HENR     OPAMPEN       LL_C1_APB1_GRP2_DisableClock\n

+  *         APB1HENR     MDIOSEN       LL_C1_APB1_GRP2_DisableClock\n

+  *         APB1HENR     FDCANEN       LL_C1_APB1_GRP2_DisableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_APB1_GRP2_DisableClock(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C1->APB1HENR, Periphs);

+}

+

+/**

+  * @brief  Enable C1 APB1 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll APB1HLPENR   CRSLPEN       LL_C1_APB1_GRP2_EnableClockSleep\n

+  *         APB1HLPENR   SWPMILPEN     LL_C1_APB1_GRP2_EnableClockSleep\n

+  *         APB1HLPENR   OPAMPLPEN     LL_C1_APB1_GRP2_EnableClockSleep\n

+  *         APB1HLPENR   MDIOSLPEN     LL_C1_APB1_GRP2_EnableClockSleep\n

+  *         APB1HLPENR   FDCANLPEN     LL_C1_APB1_GRP2_EnableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_APB1_GRP2_EnableClockSleep(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C1->APB1HLPENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C1->APB1HLPENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Disable C1 APB1 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll APB1HLPENR   CRSLPEN       LL_C1_APB1_GRP2_DisableClockSleep\n

+  *         APB1HLPENR   SWPMILPEN     LL_C1_APB1_GRP2_DisableClockSleep\n

+  *         APB1HLPENR   OPAMPLPEN     LL_C1_APB1_GRP2_DisableClockSleep\n

+  *         APB1HLPENR   MDIOSLPEN     LL_C1_APB1_GRP2_DisableClockSleep\n

+  *         APB1HLPENR   FDCANLPEN     LL_C1_APB1_GRP2_DisableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_APB1_GRP2_DisableClockSleep(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C1->APB1HLPENR, Periphs);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup BUS_LL_EF_APB2 APB2

+  * @{

+  */

+

+/**

+  * @brief  Enable C1 APB2 peripherals clock.

+  * @rmtoll APB2ENR      TIM1EN        LL_C1_APB2_GRP1_EnableClock\n

+  *         APB2ENR      TIM8EN        LL_C1_APB2_GRP1_EnableClock\n

+  *         APB2ENR      USART1EN      LL_C1_APB2_GRP1_EnableClock\n

+  *         APB2ENR      USART6EN      LL_C1_APB2_GRP1_EnableClock\n

+  *         APB2ENR      UART9EN       LL_C1_APB2_GRP1_EnableClock\n (*)

+  *         APB2ENR      USART10EN     LL_C1_APB2_GRP1_EnableClock\n (*)

+  *         APB2ENR      SPI1EN        LL_C1_APB2_GRP1_EnableClock\n

+  *         APB2ENR      SPI4EN        LL_C1_APB2_GRP1_EnableClock\n

+  *         APB2ENR      TIM15EN       LL_C1_APB2_GRP1_EnableClock\n

+  *         APB2ENR      TIM16EN       LL_C1_APB2_GRP1_EnableClock\n

+  *         APB2ENR      TIM17EN       LL_C1_APB2_GRP1_EnableClock\n

+  *         APB2ENR      SPI5EN        LL_C1_APB2_GRP1_EnableClock\n

+  *         APB2ENR      SAI1EN        LL_C1_APB2_GRP1_EnableClock\n

+  *         APB2ENR      SAI2EN        LL_C1_APB2_GRP1_EnableClock\n

+  *         APB2ENR      SAI3EN        LL_C1_APB2_GRP1_EnableClock\n (*)

+  *         APB2ENR      DFSDM1EN      LL_C1_APB2_GRP1_EnableClock\n

+  *         APB2ENR      HRTIMEN       LL_C1_APB2_GRP1_EnableClock   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6

+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_APB2_GRP1_EnableClock(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C1->APB2ENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C1->APB2ENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Check if C1 APB2 peripheral clock is enabled or not

+  * @rmtoll APB2ENR      TIM1EN        LL_C1_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      TIM8EN        LL_C1_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      USART1EN      LL_C1_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      USART6EN      LL_C1_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      UART9EN       LL_C1_APB2_GRP1_IsEnabledClock\n (*)

+  *         APB2ENR      USART10EN     LL_C1_APB2_GRP1_IsEnabledClock\n (*)

+  *         APB2ENR      SPI1EN        LL_C1_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      SPI4EN        LL_C1_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      TIM15EN       LL_C1_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      TIM16EN       LL_C1_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      TIM17EN       LL_C1_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      SPI5EN        LL_C1_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      SAI1EN        LL_C1_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      SAI2EN        LL_C1_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      SAI3EN        LL_C1_APB2_GRP1_IsEnabledClock\n (*)

+  *         APB2ENR      DFSDM1EN      LL_C1_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      HRTIMEN       LL_C1_APB2_GRP1_IsEnabledClock   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6

+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE uint32_t LL_C1_APB2_GRP1_IsEnabledClock(uint32_t Periphs)

+{

+  return ((READ_BIT(RCC_C1->APB2ENR, Periphs) == Periphs)?1U:0U);

+}

+

+/**

+  * @brief  Disable C1 APB2 peripherals clock.

+  * @rmtoll APB2ENR      TIM1EN        LL_C1_APB2_GRP1_DisableClock\n

+  *         APB2ENR      TIM8EN        LL_C1_APB2_GRP1_DisableClock\n

+  *         APB2ENR      USART1EN      LL_C1_APB2_GRP1_DisableClock\n

+  *         APB2ENR      USART6EN      LL_C1_APB2_GRP1_DisableClock\n

+  *         APB2ENR      UART9EN       LL_C1_APB2_GRP1_DisableClock\n (*)

+  *         APB2ENR      USART10EN     LL_C1_APB2_GRP1_DisableClock\n (*)

+  *         APB2ENR      SPI1EN        LL_C1_APB2_GRP1_DisableClock\n

+  *         APB2ENR      SPI4EN        LL_C1_APB2_GRP1_DisableClock\n

+  *         APB2ENR      TIM15EN       LL_C1_APB2_GRP1_DisableClock\n

+  *         APB2ENR      TIM16EN       LL_C1_APB2_GRP1_DisableClock\n

+  *         APB2ENR      TIM17EN       LL_C1_APB2_GRP1_DisableClock\n

+  *         APB2ENR      SPI5EN        LL_C1_APB2_GRP1_DisableClock\n

+  *         APB2ENR      SAI1EN        LL_C1_APB2_GRP1_DisableClock\n

+  *         APB2ENR      SAI2EN        LL_C1_APB2_GRP1_DisableClock\n

+  *         APB2ENR      SAI3EN        LL_C1_APB2_GRP1_DisableClock\n  (*)

+  *         APB2ENR      DFSDM1EN      LL_C1_APB2_GRP1_DisableClock\n

+  *         APB2ENR      HRTIMEN       LL_C1_APB2_GRP1_DisableClock    (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_APB2_GRP1_DisableClock(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C1->APB2ENR, Periphs);

+}

+

+/**

+  * @brief  Enable C1 APB2 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll APB2LPENR    TIM1LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    TIM8LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    USART1LPEN    LL_C1_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    USART6LPEN    LL_C1_APB2_GRP1_EnableClockSleep\n

+  *         APB2ENR      UART9EN       LL_C1_APB2_GRP1_EnableClockSleep\n (*)

+  *         APB2ENR      USART10EN     LL_C1_APB2_GRP1_EnableClockSleep\n (*)

+  *         APB2LPENR    SPI1LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    SPI4LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    TIM15LPEN     LL_C1_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    TIM16LPEN     LL_C1_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    TIM17LPEN     LL_C1_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    SPI5LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    SAI1LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    SAI2LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    SAI3LPEN      LL_C1_APB2_GRP1_EnableClockSleep\n (*)

+  *         APB2LPENR    DFSDM1LPEN    LL_C1_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    HRTIMLPEN     LL_C1_APB2_GRP1_EnableClockSleep   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_APB2_GRP1_EnableClockSleep(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C1->APB2LPENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C1->APB2LPENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Disable C1 APB2 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll APB2LPENR    TIM1LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    TIM8LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    USART1LPEN    LL_C1_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    UART9LPEN     LL_C1_APB2_GRP1_DisableClockSleep\n (*)

+  *         APB2LPENR    USART10LPEN   LL_C1_APB2_GRP1_DisableClockSleep\n (*)

+  *         APB2LPENR    USART6LPEN    LL_C1_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    SPI1LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    SPI4LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    TIM15LPEN     LL_C1_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    TIM16LPEN     LL_C1_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    TIM17LPEN     LL_C1_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    SPI5LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    SAI1LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    SAI2LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    SAI3LPEN      LL_C1_APB2_GRP1_DisableClockSleep\n (*)

+  *         APB2LPENR    DFSDM1LPEN    LL_C1_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    HRTIMLPEN     LL_C1_APB2_GRP1_DisableClockSleep   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_UART9   (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART10 (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3  (*)

+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_APB2_GRP1_DisableClockSleep(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C1->APB2LPENR, Periphs);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup BUS_LL_EF_APB4 APB4

+  * @{

+  */

+

+/**

+  * @brief  Enable C1 APB4 peripherals clock.

+  * @rmtoll APB4ENR      SYSCFGEN      LL_C1_APB4_GRP1_EnableClock\n

+  *         APB4ENR      LPUART1EN     LL_C1_APB4_GRP1_EnableClock\n

+  *         APB4ENR      SPI6EN        LL_C1_APB4_GRP1_EnableClock\n

+  *         APB4ENR      I2C4EN        LL_C1_APB4_GRP1_EnableClock\n

+  *         APB4ENR      LPTIM2EN      LL_C1_APB4_GRP1_EnableClock\n

+  *         APB4ENR      LPTIM3EN      LL_C1_APB4_GRP1_EnableClock\n

+  *         APB4ENR      LPTIM4EN      LL_C1_APB4_GRP1_EnableClock\n (*)

+  *         APB4ENR      LPTIM5EN      LL_C1_APB4_GRP1_EnableClock\n (*)

+  *         APB4ENR      DAC2EN        LL_C1_APB4_GRP1_EnableClock\n (*)

+  *         APB4ENR      COMP12EN      LL_C1_APB4_GRP1_EnableClock\n

+  *         APB4ENR      VREFEN        LL_C1_APB4_GRP1_EnableClock\n

+  *         APB4ENR      RTCAPBEN      LL_C1_APB4_GRP1_EnableClock\n

+  *         APB4ENR      SAI4EN        LL_C1_APB4_GRP1_EnableClock\n (*)

+  *         APB4ENR      DTSEN         LL_C1_APB4_GRP1_EnableClock\n (*)

+  *         APB4ENR      DFSDM2EN      LL_C1_APB4_GRP1_EnableClock   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_APB4_GRP1_EnableClock(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C1->APB4ENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C1->APB4ENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Check if C1 APB4 peripheral clock is enabled or not

+  * @rmtoll APB4ENR      SYSCFGEN      LL_C1_APB4_GRP1_IsEnabledClock\n

+  *         APB4ENR      LPUART1EN     LL_C1_APB4_GRP1_IsEnabledClock\n

+  *         APB4ENR      SPI6EN        LL_C1_APB4_GRP1_IsEnabledClock\n

+  *         APB4ENR      I2C4EN        LL_C1_APB4_GRP1_IsEnabledClock\n

+  *         APB4ENR      LPTIM2EN      LL_C1_APB4_GRP1_IsEnabledClock\n

+  *         APB4ENR      LPTIM3EN      LL_C1_APB4_GRP1_IsEnabledClock\n

+  *         APB4ENR      LPTIM4EN      LL_C1_APB4_GRP1_IsEnabledClock\n (*)

+  *         APB4ENR      LPTIM5EN      LL_C1_APB4_GRP1_IsEnabledClock\n (*)

+  *         APB4ENR      COMP12EN      LL_C1_APB4_GRP1_IsEnabledClock\n

+  *         APB4ENR      VREFEN        LL_C1_APB4_GRP1_IsEnabledClock\n

+  *         APB4ENR      RTCAPBEN      LL_C1_APB4_GRP1_IsEnabledClock\n

+  *         APB4ENR      SAI4EN        LL_C1_APB4_GRP1_IsEnabledClock\n (*)

+  *         APB4ENR      DTSEN         LL_C1_APB4_GRP1_IsEnabledClock\n (*)

+  *         APB4ENR      DFSDM2EN      LL_C1_APB4_GRP1_IsEnabledClock   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval uint32_t

+*/

+__STATIC_INLINE uint32_t LL_C1_APB4_GRP1_IsEnabledClock(uint32_t Periphs)

+{

+  return ((READ_BIT(RCC_C1->APB4ENR, Periphs) == Periphs)?1U:0U);

+}

+

+/**

+  * @brief  Disable C1 APB4 peripherals clock.

+  * @rmtoll APB4ENR      SYSCFGEN      LL_C1_APB4_GRP1_DisableClock\n

+  *         APB4ENR      LPUART1EN     LL_C1_APB4_GRP1_DisableClock\n

+  *         APB4ENR      SPI6EN        LL_C1_APB4_GRP1_DisableClock\n

+  *         APB4ENR      I2C4EN        LL_C1_APB4_GRP1_DisableClock\n

+  *         APB4ENR      LPTIM2EN      LL_C1_APB4_GRP1_DisableClock\n

+  *         APB4ENR      LPTIM3EN      LL_C1_APB4_GRP1_DisableClock\n

+  *         APB4ENR      LPTIM4EN      LL_C1_APB4_GRP1_DisableClock\n (*)

+  *         APB4ENR      LPTIM5EN      LL_C1_APB4_GRP1_DisableClock\n (*)

+  *         APB4ENR      COMP12EN      LL_C1_APB4_GRP1_DisableClock\n

+  *         APB4ENR      VREFEN        LL_C1_APB4_GRP1_DisableClock\n

+  *         APB4ENR      RTCAPBEN      LL_C1_APB4_GRP1_DisableClock\n

+  *         APB4ENR      SAI4EN        LL_C1_APB4_GRP1_DisableClock\n (*)

+  *         APB4ENR      DTSEN         LL_C1_APB4_GRP1_DisableClock\n (*)

+  *         APB4ENR      DFSDM2EN      LL_C1_APB4_GRP1_DisableClock   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_APB4_GRP1_DisableClock(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C1->APB4ENR, Periphs);

+}

+

+/**

+  * @brief  Enable C1 APB4 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll APB4LPENR    SYSCFGLPEN    LL_C1_APB4_GRP1_EnableClockSleep\n

+  *         APB4LPENR    LPUART1LPEN   LL_C1_APB4_GRP1_EnableClockSleep\n

+  *         APB4LPENR    SPI6LPEN      LL_C1_APB4_GRP1_EnableClockSleep\n

+  *         APB4LPENR    I2C4LPEN      LL_C1_APB4_GRP1_EnableClockSleep\n

+  *         APB4LPENR    LPTIM2LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n

+  *         APB4LPENR    LPTIM3LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n (*)

+  *         APB4LPENR    LPTIM4LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n (*)

+  *         APB4LPENR    LPTIM5LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n

+  *         APB4LPENR    COMP12LPEN    LL_C1_APB4_GRP1_EnableClockSleep\n

+  *         APB4LPENR    VREFLPEN      LL_C1_APB4_GRP1_EnableClockSleep\n

+  *         APB4LPENR    RTCAPBLPEN    LL_C1_APB4_GRP1_EnableClockSleep\n

+  *         APB4ENR      SAI4EN        LL_C1_APB4_GRP1_EnableClockSleep\n (*)

+  *         APB4ENR      DTSEN         LL_C1_APB4_GRP1_EnableClockSleep\n (*)

+  *         APB4ENR      DFSDM2EN      LL_C1_APB4_GRP1_EnableClockSleep   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_APB4_GRP1_EnableClockSleep(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C1->APB4LPENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C1->APB4LPENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Disable C1 APB4 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll APB4LPENR    SYSCFGLPEN    LL_C1_APB4_GRP1_DisableClockSleep\n

+  *         APB4LPENR    LPUART1LPEN   LL_C1_APB4_GRP1_DisableClockSleep\n

+  *         APB4LPENR    SPI6LPEN      LL_C1_APB4_GRP1_DisableClockSleep\n

+  *         APB4LPENR    I2C4LPEN      LL_C1_APB4_GRP1_DisableClockSleep\n

+  *         APB4LPENR    LPTIM2LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n

+  *         APB4LPENR    LPTIM3LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n

+  *         APB4LPENR    LPTIM4LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n

+  *         APB4LPENR    LPTIM5LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n

+  *         APB4LPENR    COMP12LPEN    LL_C1_APB4_GRP1_DisableClockSleep\n

+  *         APB4LPENR    VREFLPEN      LL_C1_APB4_GRP1_DisableClockSleep\n

+  *         APB4LPENR    RTCAPBLPEN    LL_C1_APB4_GRP1_DisableClockSleep\n

+  *         APB4ENR      SAI4EN        LL_C1_APB4_GRP1_DisableClockSleep\n (*)

+  *         APB4ENR      DTSEN         LL_C1_APB4_GRP1_DisableClockSleep\n (*)

+  *         APB4ENR      DFSDM2EN      LL_C1_APB4_GRP1_DisableClockSleep   (*)

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4 (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5 (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4   (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_DTS    (*)

+  *         @arg @ref LL_APB4_GRP1_PERIPH_DFSDM2 (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C1_APB4_GRP1_DisableClockSleep(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C1->APB4LPENR, Periphs);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup BUS_LL_EF_AHB3 AHB3

+  * @{

+  */

+

+/**

+  * @brief  Enable C2 AHB3 peripherals clock.

+  * @rmtoll AHB3ENR      MDMAEN        LL_C2_AHB3_GRP1_EnableClock\n

+  *         AHB3ENR      DMA2DEN       LL_C2_AHB3_GRP1_EnableClock\n

+  *         AHB3ENR      JPGDECEN      LL_C2_AHB3_GRP1_EnableClock\n

+  *         AHB3ENR      FMCEN         LL_C2_AHB3_GRP1_EnableClock\n

+  *         AHB3ENR      QSPIEN        LL_C2_AHB3_GRP1_EnableClock\n

+  *         AHB3ENR      SDMMC1EN      LL_C2_AHB3_GRP1_EnableClock\n

+  *         AHB3ENR      FLASHEN       LL_C2_AHB3_GRP1_EnableClock\n

+  *         AHB3ENR      DTCM1EN       LL_C2_AHB3_GRP1_EnableClock\n

+  *         AHB3ENR      DTCM2EN       LL_C2_AHB3_GRP1_EnableClock\n

+  *         AHB3ENR      ITCMEN        LL_C2_AHB3_GRP1_EnableClock\n

+  *         AHB3ENR      AXISRAMEN     LL_C2_AHB3_GRP1_EnableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClock(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C2->AHB3ENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C2->AHB3ENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Check if C2 AHB3 peripheral clock is enabled or not

+  * @rmtoll AHB3ENR      MDMAEN        LL_C2_AHB3_GRP1_IsEnabledClock\n

+  *         AHB3ENR      DMA2DEN       LL_C2_AHB3_GRP1_IsEnabledClock\n

+  *         AHB3ENR      JPGDECEN      LL_C2_AHB3_GRP1_IsEnabledClock\n

+  *         AHB3ENR      FMCEN         LL_C2_AHB3_GRP1_IsEnabledClock\n

+  *         AHB3ENR      QSPIEN        LL_C2_AHB3_GRP1_IsEnabledClock\n

+  *         AHB3ENR      SDMMC1EN      LL_C2_AHB3_GRP1_IsEnabledClock\n

+  *         AHB3ENR      FLASHEN       LL_C2_AHB3_GRP1_IsEnabledClock\n

+  *         AHB3ENR      DTCM1EN       LL_C2_AHB3_GRP1_IsEnabledClock\n

+  *         AHB3ENR      DTCM2EN       LL_C2_AHB3_GRP1_IsEnabledClock\n

+  *         AHB3ENR      ITCMEN        LL_C2_AHB3_GRP1_IsEnabledClock\n

+  *         AHB3ENR      AXISRAMEN     LL_C2_AHB3_GRP1_IsEnabledClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM

+  * @retval uint32_t

+*/

+__STATIC_INLINE uint32_t LL_C2_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)

+{

+  return ((READ_BIT(RCC_C2->AHB3ENR, Periphs) == Periphs)?1U:0U);

+}

+

+/**

+  * @brief  Disable C2 AHB3 peripherals clock.

+  * @rmtoll AHB3ENR      MDMAEN        LL_C2_AHB3_GRP1_DisableClock\n

+  *         AHB3ENR      DMA2DEN       LL_C2_AHB3_GRP1_DisableClock\n

+  *         AHB3ENR      JPGDECEN      LL_C2_AHB3_GRP1_DisableClock\n

+  *         AHB3ENR      FMCEN         LL_C2_AHB3_GRP1_DisableClock\n

+  *         AHB3ENR      QSPIEN        LL_C2_AHB3_GRP1_DisableClock\n

+  *         AHB3ENR      SDMMC1EN      LL_C2_AHB3_GRP1_DisableClock\n

+  *         AHB3ENR      FLASHEN       LL_C2_AHB3_GRP1_DisableClock\n

+  *         AHB3ENR      DTCM1EN       LL_C2_AHB3_GRP1_DisableClock\n

+  *         AHB3ENR      DTCM2EN       LL_C2_AHB3_GRP1_DisableClock\n

+  *         AHB3ENR      ITCMEN        LL_C2_AHB3_GRP1_DisableClock\n

+  *         AHB3ENR      AXISRAMEN     LL_C2_AHB3_GRP1_DisableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_MDMA

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClock(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C2->AHB3ENR, Periphs);

+}

+

+/**

+  * @brief  Enable C2 AHB3 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll AHB3LPENR    MDMALPEN      LL_C2_AHB3_GRP1_EnableClockSleep\n

+  *         AHB3LPENR    DMA2DLPEN     LL_C2_AHB3_GRP1_EnableClockSleep\n

+  *         AHB3LPENR    JPGDECLPEN    LL_C2_AHB3_GRP1_EnableClockSleep\n

+  *         AHB3LPENR    FMCLPEN       LL_C2_AHB3_GRP1_EnableClockSleep\n

+  *         AHB3LPENR    QSPILPEN      LL_C2_AHB3_GRP1_EnableClockSleep\n

+  *         AHB3LPENR    SDMMC1LPEN    LL_C2_AHB3_GRP1_EnableClockSleep\n

+  *         AHB3LPENR    FLASHLPEN     LL_C2_AHB3_GRP1_EnableClockSleep\n

+  *         AHB3LPENR    DTCM1LPEN     LL_C2_AHB3_GRP1_EnableClockSleep\n

+  *         AHB3LPENR    DTCM2LPEN     LL_C2_AHB3_GRP1_EnableClockSleep\n

+  *         AHB3LPENR    ITCMLPEN      LL_C2_AHB3_GRP1_EnableClockSleep\n

+  *         AHB3LPENR    AXISRAMLPEN   LL_C2_AHB3_GRP1_EnableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_AHB3_GRP1_EnableClockSleep(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C2->AHB3LPENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C2->AHB3LPENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Disable C2 AHB3 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll AHB3LPENR    MDMALPEN      LL_C2_AHB3_GRP1_DisableClockSleep\n

+  *         AHB3LPENR    DMA2DLPEN     LL_C2_AHB3_GRP1_DisableClockSleep\n

+  *         AHB3LPENR    JPGDECLPEN    LL_C2_AHB3_GRP1_DisableClockSleep\n

+  *         AHB3LPENR    FMCLPEN       LL_C2_AHB3_GRP1_DisableClockSleep\n

+  *         AHB3LPENR    QSPILPEN      LL_C2_AHB3_GRP1_DisableClockSleep\n

+  *         AHB3LPENR    SDMMC1LPEN    LL_C2_AHB3_GRP1_DisableClockSleep\n

+  *         AHB3LPENR    FLASHLPEN     LL_C2_AHB3_GRP1_DisableClockSleep\n

+  *         AHB3LPENR    DTCM1LPEN     LL_C2_AHB3_GRP1_DisableClockSleep\n

+  *         AHB3LPENR    DTCM2LPEN     LL_C2_AHB3_GRP1_DisableClockSleep\n

+  *         AHB3LPENR    ITCMLPEN      LL_C2_AHB3_GRP1_DisableClockSleep\n

+  *         AHB3LPENR    AXISRAMLPEN   LL_C2_AHB3_GRP1_DisableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DMA2D

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_JPGDEC

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FMC

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_QSPI

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_SDMMC1

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_FLASH

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM1

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_DTCM2

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_ITCM

+  *         @arg @ref LL_AHB3_GRP1_PERIPH_AXISRAM

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_AHB3_GRP1_DisableClockSleep(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C2->AHB3LPENR, Periphs);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup BUS_LL_EF_AHB1 AHB1

+  * @{

+  */

+

+/**

+  * @brief  Enable C2 AHB1 peripherals clock.

+  * @rmtoll AHB1ENR      DMA1EN        LL_C2_AHB1_GRP1_EnableClock\n

+  *         AHB1ENR      DMA2EN        LL_C2_AHB1_GRP1_EnableClock\n

+  *         AHB1ENR      ADC12EN       LL_C2_AHB1_GRP1_EnableClock\n

+  *         AHB1ENR      ARTEN         LL_C2_AHB1_GRP1_EnableClock\n

+  *         AHB1ENR      ETH1MACEN     LL_C2_AHB1_GRP1_EnableClock\n

+  *         AHB1ENR      ETH1TXEN      LL_C2_AHB1_GRP1_EnableClock\n

+  *         AHB1ENR      ETH1RXEN      LL_C2_AHB1_GRP1_EnableClock\n

+  *         AHB1ENR      USB1OTGHSEN   LL_C2_AHB1_GRP1_EnableClock\n

+  *         AHB1ENR      USB1OTGHSULPIEN  LL_C2_AHB1_GRP1_EnableClock\n

+  *         AHB1ENR      USB2OTGHSEN   LL_C2_AHB1_GRP1_EnableClock\n

+  *         AHB1ENR      USB2OTGHSULPIEN  LL_C2_AHB1_GRP1_EnableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClock(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C2->AHB1ENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C2->AHB1ENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Check if C2 AHB1 peripheral clock is enabled or not

+  * @rmtoll AHB1ENR      DMA1EN        LL_C2_AHB1_GRP1_IsEnabledClock\n

+  *         AHB1ENR      DMA2EN        LL_C2_AHB1_GRP1_IsEnabledClock\n

+  *         AHB1ENR      ADC12EN       LL_C2_AHB1_GRP1_IsEnabledClock\n

+  *         AHB1ENR      ARTEN         LL_C2_AHB1_GRP1_IsEnabledClock\n

+  *         AHB1ENR      ETH1MACEN     LL_C2_AHB1_GRP1_IsEnabledClock\n

+  *         AHB1ENR      ETH1TXEN      LL_C2_AHB1_GRP1_IsEnabledClock\n

+  *         AHB1ENR      ETH1RXEN      LL_C2_AHB1_GRP1_IsEnabledClock\n

+  *         AHB1ENR      USB1OTGHSEN   LL_C2_AHB1_GRP1_IsEnabledClock\n

+  *         AHB1ENR      USB1OTGHSULPIEN  LL_C2_AHB1_GRP1_IsEnabledClock\n

+  *         AHB1ENR      USB2OTGHSEN   LL_C2_AHB1_GRP1_IsEnabledClock\n

+  *         AHB1ENR      USB2OTGHSULPIEN  LL_C2_AHB1_GRP1_IsEnabledClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI

+  * @retval uint32_t

+*/

+__STATIC_INLINE uint32_t LL_C2_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)

+{

+  return ((READ_BIT(RCC_C2->AHB1ENR, Periphs) == Periphs)?1U:0U);

+}

+

+/**

+  * @brief  Disable C2 AHB1 peripherals clock.

+  * @rmtoll AHB1ENR      DMA1EN        LL_C2_AHB1_GRP1_DisableClock\n

+  *         AHB1ENR      DMA2EN        LL_C2_AHB1_GRP1_DisableClock\n

+  *         AHB1ENR      ADC12EN       LL_C2_AHB1_GRP1_DisableClock\n

+  *         AHB1ENR      ARTEN         LL_C2_AHB1_GRP1_DisableClock\n

+  *         AHB1ENR      ETH1MACEN     LL_C2_AHB1_GRP1_DisableClock\n

+  *         AHB1ENR      ETH1TXEN      LL_C2_AHB1_GRP1_DisableClock\n

+  *         AHB1ENR      ETH1RXEN      LL_C2_AHB1_GRP1_DisableClock\n

+  *         AHB1ENR      USB1OTGHSEN   LL_C2_AHB1_GRP1_DisableClock\n

+  *         AHB1ENR      USB1OTGHSULPIEN  LL_C2_AHB1_GRP1_DisableClock\n

+  *         AHB1ENR      USB2OTGHSEN   LL_C2_AHB1_GRP1_DisableClock\n

+  *         AHB1ENR      USB2OTGHSULPIEN  LL_C2_AHB1_GRP1_DisableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClock(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C2->AHB1ENR, Periphs);

+}

+

+/**

+  * @brief  Enable C2 AHB1 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll AHB1LPENR    DMA1LPEN      LL_C2_AHB1_GRP1_EnableClockSleep\n

+  *         AHB1LPENR    DMA2LPEN      LL_C2_AHB1_GRP1_EnableClockSleep\n

+  *         AHB1LPENR    ADC12LPEN     LL_C2_AHB1_GRP1_EnableClockSleep\n

+  *         AHB1LPENR    ARTLPEN       LL_C2_AHB1_GRP1_EnableClockSleep\n

+  *         AHB1LPENR    ETH1MACLPEN   LL_C2_AHB1_GRP1_EnableClockSleep\n

+  *         AHB1LPENR    ETH1TXLPEN    LL_C2_AHB1_GRP1_EnableClockSleep\n

+  *         AHB1LPENR    ETH1RXLPEN    LL_C2_AHB1_GRP1_EnableClockSleep\n

+  *         AHB1LPENR    USB1OTGHSLPEN  LL_C2_AHB1_GRP1_EnableClockSleep\n

+  *         AHB1LPENR    USB1OTGHSULPILPEN  LL_C2_AHB1_GRP1_EnableClockSleep\n

+  *         AHB1LPENR    USB2OTGHSLPEN  LL_C2_AHB1_GRP1_EnableClockSleep\n

+  *         AHB1LPENR    USB2OTGHSULPILPEN  LL_C2_AHB1_GRP1_EnableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_AHB1_GRP1_EnableClockSleep(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C2->AHB1LPENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C2->AHB1LPENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Disable C2 AHB1 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll AHB1LPENR    DMA1LPEN      LL_C2_AHB1_GRP1_DisableClockSleep\n

+  *         AHB1LPENR    DMA2LPEN      LL_C2_AHB1_GRP1_DisableClockSleep\n

+  *         AHB1LPENR    ADC12LPEN     LL_C2_AHB1_GRP1_DisableClockSleep\n

+  *         AHB1LPENR    ARTLPEN       LL_C2_AHB1_GRP1_DisableClockSleep\n

+  *         AHB1LPENR    ETH1MACLPEN   LL_C2_AHB1_GRP1_DisableClockSleep\n

+  *         AHB1LPENR    ETH1TXLPEN    LL_C2_AHB1_GRP1_DisableClockSleep\n

+  *         AHB1LPENR    ETH1RXLPEN    LL_C2_AHB1_GRP1_DisableClockSleep\n

+  *         AHB1LPENR    USB1OTGHSLPEN  LL_C2_AHB1_GRP1_DisableClockSleep\n

+  *         AHB1LPENR    USB1OTGHSULPILPEN  LL_C2_AHB1_GRP1_DisableClockSleep\n

+  *         AHB1LPENR    USB2OTGHSLPEN  LL_C2_AHB1_GRP1_DisableClockSleep\n

+  *         AHB1LPENR    USB2OTGHSULPILPEN  LL_C2_AHB1_GRP1_DisableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA1

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_DMA2

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ADC12

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ART

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1MAC

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1TX

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_ETH1RX

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHS

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB1OTGHSULPI

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHS

+  *         @arg @ref LL_AHB1_GRP1_PERIPH_USB2OTGHSULPI

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_AHB1_GRP1_DisableClockSleep(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C2->AHB1LPENR, Periphs);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup BUS_LL_EF_AHB2 AHB2

+  * @{

+  */

+

+/**

+  * @brief  Enable C2 AHB2 peripherals clock.

+  * @rmtoll AHB2ENR      DCMIEN        LL_C2_AHB2_GRP1_EnableClock\n

+  *         AHB2ENR      CRYPEN        LL_C2_AHB2_GRP1_EnableClock\n

+  *         AHB2ENR      HASHEN        LL_C2_AHB2_GRP1_EnableClock\n

+  *         AHB2ENR      RNGEN         LL_C2_AHB2_GRP1_EnableClock\n

+  *         AHB2ENR      SDMMC2EN      LL_C2_AHB2_GRP1_EnableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClock(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C2->AHB2ENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C2->AHB2ENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Check if C2 AHB2 peripheral clock is enabled or not

+  * @rmtoll AHB2ENR      DCMIEN        LL_C2_AHB2_GRP1_IsEnabledClock\n

+  *         AHB2ENR      CRYPEN        LL_C2_AHB2_GRP1_IsEnabledClock\n

+  *         AHB2ENR      HASHEN        LL_C2_AHB2_GRP1_IsEnabledClock\n

+  *         AHB2ENR      RNGEN         LL_C2_AHB2_GRP1_IsEnabledClock\n

+  *         AHB2ENR      SDMMC2EN      LL_C2_AHB2_GRP1_IsEnabledClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

+  *

+  *         (*) value not defined in all devices.

+  * @retval uint32_t

+*/

+__STATIC_INLINE uint32_t LL_C2_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)

+{

+  return ((READ_BIT(RCC_C2->AHB2ENR, Periphs) == Periphs)?1U:0U);

+}

+

+/**

+  * @brief  Disable C2 AHB2 peripherals clock.

+  * @rmtoll AHB2ENR      DCMIEN        LL_C2_AHB2_GRP1_DisableClock\n

+  *         AHB2ENR      CRYPEN        LL_C2_AHB2_GRP1_DisableClock\n

+  *         AHB2ENR      HASHEN        LL_C2_AHB2_GRP1_DisableClock\n

+  *         AHB2ENR      RNGEN         LL_C2_AHB2_GRP1_DisableClock\n

+  *         AHB2ENR      SDMMC2EN      LL_C2_AHB2_GRP1_DisableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClock(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C2->AHB2ENR, Periphs);

+}

+

+/**

+  * @brief  Enable C2 AHB2 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll AHB2LPENR    DCMILPEN      LL_C2_AHB2_GRP1_EnableClockSleep\n

+  *         AHB2LPENR    CRYPLPEN      LL_C2_AHB2_GRP1_EnableClockSleep\n

+  *         AHB2LPENR    HASHLPEN      LL_C2_AHB2_GRP1_EnableClockSleep\n

+  *         AHB2LPENR    RNGLPEN       LL_C2_AHB2_GRP1_EnableClockSleep\n

+  *         AHB2LPENR    SDMMC2LPEN    LL_C2_AHB2_GRP1_EnableClockSleep\n

+  *         AHB2LPENR    D2SRAM1LPEN   LL_C2_AHB2_GRP1_EnableClockSleep\n

+  *         AHB2LPENR    D2SRAM2LPEN   LL_C2_AHB2_GRP1_EnableClockSleep\n

+  *         AHB2LPENR    D2SRAM3LPEN   LL_C2_AHB2_GRP1_EnableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_AHB2_GRP1_EnableClockSleep(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C2->AHB2LPENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C2->AHB2LPENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Disable C2 AHB2 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll AHB2LPENR    DCMILPEN      LL_C2_AHB2_GRP1_DisableClockSleep\n

+  *         AHB2LPENR    CRYPLPEN      LL_C2_AHB2_GRP1_DisableClockSleep\n

+  *         AHB2LPENR    HASHLPEN      LL_C2_AHB2_GRP1_DisableClockSleep\n

+  *         AHB2LPENR    RNGLPEN       LL_C2_AHB2_GRP1_DisableClockSleep\n

+  *         AHB2LPENR    SDMMC2LPEN    LL_C2_AHB2_GRP1_DisableClockSleep\n

+  *         AHB2LPENR    D2SRAM1LPEN   LL_C2_AHB2_GRP1_DisableClockSleep\n

+  *         AHB2LPENR    D2SRAM2LPEN   LL_C2_AHB2_GRP1_DisableClockSleep\n

+  *         AHB2LPENR    D2SRAM3LPEN   LL_C2_AHB2_GRP1_DisableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_DCMI

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_RNG

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM1

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM2

+  *         @arg @ref LL_AHB2_GRP1_PERIPH_D2SRAM3

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_AHB2_GRP1_DisableClockSleep(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C2->AHB2LPENR, Periphs);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup BUS_LL_EF_AHB4 AHB4

+  * @{

+  */

+

+/**

+  * @brief  Enable C2 AHB4 peripherals clock.

+  * @rmtoll AHB4ENR      GPIOAEN       LL_C2_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      GPIOBEN       LL_C2_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      GPIOCEN       LL_C2_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      GPIODEN       LL_C2_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      GPIOEEN       LL_C2_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      GPIOFEN       LL_C2_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      GPIOGEN       LL_C2_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      GPIOHEN       LL_C2_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      GPIOIEN       LL_C2_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      GPIOJEN       LL_C2_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      GPIOKEN       LL_C2_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      CRCEN         LL_C2_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      BDMAEN        LL_C2_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      ADC3EN        LL_C2_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      HSEMEN        LL_C2_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      BKPRAMEN      LL_C2_AHB4_GRP1_EnableClock\n

+  *         AHB4ENR      SRAM4EN     LL_C2_AHB4_GRP1_EnableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClock(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C2->AHB4ENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C2->AHB4ENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Check if C2 AHB4 peripheral clock is enabled or not

+  * @rmtoll AHB4ENR      GPIOAEN       LL_C2_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      GPIOBEN       LL_C2_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      GPIOCEN       LL_C2_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      GPIODEN       LL_C2_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      GPIOEEN       LL_C2_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      GPIOFEN       LL_C2_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      GPIOGEN       LL_C2_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      GPIOHEN       LL_C2_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      GPIOIEN       LL_C2_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      GPIOJEN       LL_C2_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      GPIOKEN       LL_C2_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      CRCEN         LL_C2_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      BDMAEN        LL_C2_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      ADC3EN        LL_C2_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      HSEMEN        LL_C2_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      BKPRAMEN      LL_C2_AHB4_GRP1_IsEnabledClock\n

+  *         AHB4ENR      SRAM4EN       LL_C2_AHB4_GRP1_IsEnabledClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4

+  *

+  *         (*) value not defined in all devices.

+  * @retval uint32_t

+*/

+__STATIC_INLINE uint32_t LL_C2_AHB4_GRP1_IsEnabledClock(uint32_t Periphs)

+{

+  return ((READ_BIT(RCC_C2->AHB4ENR, Periphs) == Periphs)?1U:0U);

+}

+

+/**

+  * @brief  Disable C2 AHB4 peripherals clock.

+  * @rmtoll AHB4ENR      GPIOAEN       LL_C2_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      GPIOBEN       LL_C2_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      GPIOCEN       LL_C2_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      GPIODEN       LL_C2_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      GPIOEEN       LL_C2_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      GPIOFEN       LL_C2_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      GPIOGEN       LL_C2_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      GPIOHEN       LL_C2_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      GPIOIEN       LL_C2_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      GPIOJEN       LL_C2_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      GPIOKEN       LL_C2_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      CRCEN         LL_C2_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      BDMAEN        LL_C2_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      ADC3EN        LL_C2_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      HSEMEN        LL_C2_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      BKPRAMEN      LL_C2_AHB4_GRP1_DisableClock\n

+  *         AHB4ENR      SRAM4EN       LL_C2_AHB4_GRP1_DisableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_HSEM (*)

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClock(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C2->AHB4ENR, Periphs);

+}

+

+/**

+  * @brief  Enable C2 AHB4 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll AHB4LPENR    GPIOALPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    GPIOBLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    GPIOCLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    GPIODLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    GPIOELPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    GPIOFLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    GPIOGLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    GPIOHLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    GPIOILPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    GPIOJLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    GPIOKLPEN     LL_C2_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    CRCLPEN       LL_C2_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    BDMALPEN      LL_C2_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    ADC3LPEN      LL_C2_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    BKPRAMLPEN    LL_C2_AHB4_GRP1_EnableClockSleep\n

+  *         AHB4LPENR    SRAM4LPEN     LL_C2_AHB4_GRP1_EnableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_AHB4_GRP1_EnableClockSleep(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C2->AHB4LPENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C2->AHB4LPENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Disable C2 AHB4 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll AHB4LPENR    GPIOALPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    GPIOBLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    GPIOCLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    GPIODLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    GPIOELPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    GPIOFLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    GPIOGLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    GPIOHLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    GPIOILPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    GPIOJLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    GPIOKLPEN     LL_C2_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    CRCLPEN       LL_C2_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    BDMALPEN      LL_C2_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    ADC3LPEN      LL_C2_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    BKPRAMLPEN    LL_C2_AHB4_GRP1_DisableClockSleep\n

+  *         AHB4LPENR    SRAM4LPEN     LL_C2_AHB4_GRP1_DisableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOB

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOC

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOD

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOE

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOF

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOG

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOH

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOI

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOJ

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_GPIOK

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_CRC

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BDMA

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_ADC3

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_BKPRAM

+  *         @arg @ref LL_AHB4_GRP1_PERIPH_SRAM4

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_AHB4_GRP1_DisableClockSleep(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C2->AHB4LPENR, Periphs);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup BUS_LL_EF_APB3 APB3

+  * @{

+  */

+

+/**

+  * @brief  Enable C2 APB3 peripherals clock.

+  * @rmtoll APB3ENR      LTDCEN        LL_C2_APB3_GRP1_EnableClock\n

+  *         APB3ENR      DSIEN         LL_C2_APB3_GRP1_EnableClock\n

+  *         APB3ENR      WWDG1EN       LL_C2_APB3_GRP1_EnableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC

+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)

+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_APB3_GRP1_EnableClock(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C2->APB3ENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C2->APB3ENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Check if C2 APB3 peripheral clock is enabled or not

+  * @rmtoll APB3ENR      LTDCEN        LL_C2_APB3_GRP1_IsEnabledClock\n

+  *         APB3ENR      DSIEN         LL_C2_APB3_GRP1_IsEnabledClock\n

+  *         APB3ENR      WWDG1EN       LL_C2_APB3_GRP1_IsEnabledClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC

+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)

+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1

+  *

+  *         (*) value not defined in all devices.

+  * @retval uint32_t

+*/

+__STATIC_INLINE uint32_t LL_C2_APB3_GRP1_IsEnabledClock(uint32_t Periphs)

+{

+  return ((READ_BIT(RCC_C2->APB3ENR, Periphs) == Periphs)?1U:0U);

+}

+

+/**

+  * @brief  Disable C2 APB3 peripherals clock.

+  * @rmtoll APB3ENR      LTDCEN        LL_C2_APB3_GRP1_DisableClock\n

+  *         APB3ENR      DSIEN         LL_C2_APB3_GRP1_DisableClock\n

+  *         APB3ENR      WWDG1EN       LL_C2_APB3_GRP1_DisableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC

+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)

+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_APB3_GRP1_DisableClock(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C2->APB3ENR, Periphs);

+}

+

+/**

+  * @brief  Enable C2 APB3 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll APB3LPENR    LTDCLPEN      LL_C2_APB3_GRP1_EnableClockSleep\n

+  *         APB3LPENR    DSILPEN       LL_C2_APB3_GRP1_EnableClockSleep\n

+  *         APB3LPENR    WWDG1LPEN     LL_C2_APB3_GRP1_EnableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC

+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)

+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_APB3_GRP1_EnableClockSleep(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C2->APB3LPENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C2->APB3LPENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Disable C2 APB3 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll APB3LPENR    LTDCLPEN      LL_C2_APB3_GRP1_DisableClockSleep\n

+  *         APB3LPENR    DSILPEN       LL_C2_APB3_GRP1_DisableClockSleep\n

+  *         APB3LPENR    WWDG1LPEN     LL_C2_APB3_GRP1_DisableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB3_GRP1_PERIPH_LTDC

+  *         @arg @ref LL_APB3_GRP1_PERIPH_DSI (*)

+  *         @arg @ref LL_APB3_GRP1_PERIPH_WWDG1

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_APB3_GRP1_DisableClockSleep(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C2->APB3LPENR, Periphs);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup BUS_LL_EF_APB1 APB1

+  * @{

+  */

+

+/**

+  * @brief  Enable C2 APB1 peripherals clock.

+  * @rmtoll APB1LENR     TIM2EN        LL_C2_APB1_GRP1_EnableClock\n

+  *         APB1LENR     TIM3EN        LL_C2_APB1_GRP1_EnableClock\n

+  *         APB1LENR     TIM4EN        LL_C2_APB1_GRP1_EnableClock\n

+  *         APB1LENR     TIM5EN        LL_C2_APB1_GRP1_EnableClock\n

+  *         APB1LENR     TIM6EN        LL_C2_APB1_GRP1_EnableClock\n

+  *         APB1LENR     TIM7EN        LL_C2_APB1_GRP1_EnableClock\n

+  *         APB1LENR     TIM12EN       LL_C2_APB1_GRP1_EnableClock\n

+  *         APB1LENR     TIM13EN       LL_C2_APB1_GRP1_EnableClock\n

+  *         APB1LENR     TIM14EN       LL_C2_APB1_GRP1_EnableClock\n

+  *         APB1LENR     LPTIM1EN      LL_C2_APB1_GRP1_EnableClock\n

+  *         APB1LENR     WWDG2EN       LL_C2_APB1_GRP1_EnableClock\n

+  *         APB1LENR     SPI2EN        LL_C2_APB1_GRP1_EnableClock\n

+  *         APB1LENR     SPI3EN        LL_C2_APB1_GRP1_EnableClock\n

+  *         APB1LENR     SPDIFRXEN     LL_C2_APB1_GRP1_EnableClock\n

+  *         APB1LENR     USART2EN      LL_C2_APB1_GRP1_EnableClock\n

+  *         APB1LENR     USART3EN      LL_C2_APB1_GRP1_EnableClock\n

+  *         APB1LENR     UART4EN       LL_C2_APB1_GRP1_EnableClock\n

+  *         APB1LENR     UART5EN       LL_C2_APB1_GRP1_EnableClock\n

+  *         APB1LENR     I2C1EN        LL_C2_APB1_GRP1_EnableClock\n

+  *         APB1LENR     I2C2EN        LL_C2_APB1_GRP1_EnableClock\n

+  *         APB1LENR     I2C3EN        LL_C2_APB1_GRP1_EnableClock\n

+  *         APB1LENR     CECEN         LL_C2_APB1_GRP1_EnableClock\n

+  *         APB1LENR     DAC12EN       LL_C2_APB1_GRP1_EnableClock\n

+  *         APB1LENR     UART7EN       LL_C2_APB1_GRP1_EnableClock\n

+  *         APB1LENR     UART8EN       LL_C2_APB1_GRP1_EnableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_APB1_GRP1_EnableClock(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C2->APB1LENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C2->APB1LENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Check if C2 APB1 peripheral clock is enabled or not

+  * @rmtoll APB1LENR     TIM2EN        LL_C2_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     TIM3EN        LL_C2_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     TIM4EN        LL_C2_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     TIM5EN        LL_C2_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     TIM6EN        LL_C2_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     TIM7EN        LL_C2_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     TIM12EN       LL_C2_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     TIM13EN       LL_C2_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     TIM14EN       LL_C2_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     LPTIM1EN      LL_C2_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     WWDG2EN       LL_C2_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     SPI2EN        LL_C2_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     SPI3EN        LL_C2_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     SPDIFRXEN     LL_C2_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     USART2EN      LL_C2_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     USART3EN      LL_C2_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     UART4EN       LL_C2_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     UART5EN       LL_C2_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     I2C1EN        LL_C2_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     I2C2EN        LL_C2_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     I2C3EN        LL_C2_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     CECEN         LL_C2_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     DAC12EN       LL_C2_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     UART7EN       LL_C2_APB1_GRP1_IsEnabledClock\n

+  *         APB1LENR     UART8EN       LL_C2_APB1_GRP1_IsEnabledClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

+  * @retval uint32_t

+*/

+__STATIC_INLINE uint32_t LL_C2_APB1_GRP1_IsEnabledClock(uint32_t Periphs)

+{

+  return ((READ_BIT(RCC_C2->APB1LENR, Periphs) == Periphs)?1U:0U);

+}

+

+/**

+  * @brief  Disable C2 APB1 peripherals clock.

+  * @rmtoll APB1LENR     TIM2EN        LL_C2_APB1_GRP1_DisableClock\n

+  *         APB1LENR     TIM3EN        LL_C2_APB1_GRP1_DisableClock\n

+  *         APB1LENR     TIM4EN        LL_C2_APB1_GRP1_DisableClock\n

+  *         APB1LENR     TIM5EN        LL_C2_APB1_GRP1_DisableClock\n

+  *         APB1LENR     TIM6EN        LL_C2_APB1_GRP1_DisableClock\n

+  *         APB1LENR     TIM7EN        LL_C2_APB1_GRP1_DisableClock\n

+  *         APB1LENR     TIM12EN       LL_C2_APB1_GRP1_DisableClock\n

+  *         APB1LENR     TIM13EN       LL_C2_APB1_GRP1_DisableClock\n

+  *         APB1LENR     TIM14EN       LL_C2_APB1_GRP1_DisableClock\n

+  *         APB1LENR     LPTIM1EN      LL_C2_APB1_GRP1_DisableClock\n

+  *         APB1LENR     WWDG2EN       LL_C2_APB1_GRP1_DisableClock\n

+  *         APB1LENR     SPI2EN        LL_C2_APB1_GRP1_DisableClock\n

+  *         APB1LENR     SPI3EN        LL_C2_APB1_GRP1_DisableClock\n

+  *         APB1LENR     SPDIFRXEN     LL_C2_APB1_GRP1_DisableClock\n

+  *         APB1LENR     USART2EN      LL_C2_APB1_GRP1_DisableClock\n

+  *         APB1LENR     USART3EN      LL_C2_APB1_GRP1_DisableClock\n

+  *         APB1LENR     UART4EN       LL_C2_APB1_GRP1_DisableClock\n

+  *         APB1LENR     UART5EN       LL_C2_APB1_GRP1_DisableClock\n

+  *         APB1LENR     I2C1EN        LL_C2_APB1_GRP1_DisableClock\n

+  *         APB1LENR     I2C2EN        LL_C2_APB1_GRP1_DisableClock\n

+  *         APB1LENR     I2C3EN        LL_C2_APB1_GRP1_DisableClock\n

+  *         APB1LENR     CECEN         LL_C2_APB1_GRP1_DisableClock\n

+  *         APB1LENR     DAC12EN       LL_C2_APB1_GRP1_DisableClock\n

+  *         APB1LENR     UART7EN       LL_C2_APB1_GRP1_DisableClock\n

+  *         APB1LENR     UART8EN       LL_C2_APB1_GRP1_DisableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_APB1_GRP1_DisableClock(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C2->APB1LENR, Periphs);

+}

+

+/**

+  * @brief  Enable C2 APB1 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll APB1LLPENR   TIM2LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   TIM3LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   TIM4LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   TIM5LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   TIM6LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   TIM7LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   TIM12LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   TIM13LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   TIM14LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   LPTIM1LPEN    LL_C2_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   WWDG2LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   SPI2LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   SPI3LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   SPDIFRXLPEN   LL_C2_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   USART2LPEN    LL_C2_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   USART3LPEN    LL_C2_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   UART4LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   UART5LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   I2C1LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   I2C2LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   I2C3LPEN      LL_C2_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   CECLPEN       LL_C2_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   DAC12LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   UART7LPEN     LL_C2_APB1_GRP1_EnableClockSleep\n

+  *         APB1LLPENR   UART8LPEN     LL_C2_APB1_GRP1_EnableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_APB1_GRP1_EnableClockSleep(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C2->APB1LLPENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C2->APB1LLPENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Disable C2 APB1 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll APB1LLPENR   TIM2LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   TIM3LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   TIM4LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   TIM5LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   TIM6LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   TIM7LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   TIM12LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   TIM13LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   TIM14LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   LPTIM1LPEN    LL_C2_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   WWDG2LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   SPI2LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   SPI3LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   SPDIFRXLPEN   LL_C2_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   USART2LPEN    LL_C2_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   USART3LPEN    LL_C2_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   UART4LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   UART5LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   I2C1LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   I2C2LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   I2C3LPEN      LL_C2_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   CECLPEN       LL_C2_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   DAC12LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   UART7LPEN     LL_C2_APB1_GRP1_DisableClockSleep\n

+  *         APB1LLPENR   UART8LPEN     LL_C2_APB1_GRP1_DisableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM6

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM13

+  *         @arg @ref LL_APB1_GRP1_PERIPH_TIM14

+  *         @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_WWDG2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPI3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_USART3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART4

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART5

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C1

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C2

+  *         @arg @ref LL_APB1_GRP1_PERIPH_I2C3

+  *         @arg @ref LL_APB1_GRP1_PERIPH_CEC

+  *         @arg @ref LL_APB1_GRP1_PERIPH_DAC12

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART7

+  *         @arg @ref LL_APB1_GRP1_PERIPH_UART8

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_APB1_GRP1_DisableClockSleep(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C2->APB1LLPENR, Periphs);

+}

+

+/**

+  * @brief  Enable C2 APB1 peripherals clock.

+  * @rmtoll APB1HENR     CRSEN         LL_C2_APB1_GRP2_EnableClock\n

+  *         APB1HENR     SWPMIEN       LL_C2_APB1_GRP2_EnableClock\n

+  *         APB1HENR     OPAMPEN       LL_C2_APB1_GRP2_EnableClock\n

+  *         APB1HENR     MDIOSEN       LL_C2_APB1_GRP2_EnableClock\n

+  *         APB1HENR     FDCANEN       LL_C2_APB1_GRP2_EnableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_APB1_GRP2_EnableClock(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C2->APB1HENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C2->APB1HENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Check if C2 APB1 peripheral clock is enabled or not

+  * @rmtoll APB1HENR     CRSEN         LL_C2_APB1_GRP2_IsEnabledClock\n

+  *         APB1HENR     SWPMIEN       LL_C2_APB1_GRP2_IsEnabledClock\n

+  *         APB1HENR     OPAMPEN       LL_C2_APB1_GRP2_IsEnabledClock\n

+  *         APB1HENR     MDIOSEN       LL_C2_APB1_GRP2_IsEnabledClock\n

+  *         APB1HENR     FDCANEN       LL_C2_APB1_GRP2_IsEnabledClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

+  * @retval uint32_t

+*/

+__STATIC_INLINE uint32_t LL_C2_APB1_GRP2_IsEnabledClock(uint32_t Periphs)

+{

+  return ((READ_BIT(RCC_C2->APB1HENR, Periphs) == Periphs)?1U:0U);

+}

+

+/**

+  * @brief  Disable C2 APB1 peripherals clock.

+  * @rmtoll APB1HENR     CRSEN         LL_C2_APB1_GRP2_DisableClock\n

+  *         APB1HENR     SWPMIEN       LL_C2_APB1_GRP2_DisableClock\n

+  *         APB1HENR     OPAMPEN       LL_C2_APB1_GRP2_DisableClock\n

+  *         APB1HENR     MDIOSEN       LL_C2_APB1_GRP2_DisableClock\n

+  *         APB1HENR     FDCANEN       LL_C2_APB1_GRP2_DisableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_APB1_GRP2_DisableClock(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C2->APB1HENR, Periphs);

+}

+

+/**

+  * @brief  Enable C2 APB1 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll APB1HLPENR   CRSLPEN       LL_C2_APB1_GRP2_EnableClockSleep\n

+  *         APB1HLPENR   SWPMILPEN     LL_C2_APB1_GRP2_EnableClockSleep\n

+  *         APB1HLPENR   OPAMPLPEN     LL_C2_APB1_GRP2_EnableClockSleep\n

+  *         APB1HLPENR   MDIOSLPEN     LL_C2_APB1_GRP2_EnableClockSleep\n

+  *         APB1HLPENR   FDCANLPEN     LL_C2_APB1_GRP2_EnableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_APB1_GRP2_EnableClockSleep(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C2->APB1HLPENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C2->APB1HLPENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Disable C2 APB1 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll APB1HLPENR   CRSLPEN       LL_C2_APB1_GRP2_DisableClockSleep\n

+  *         APB1HLPENR   SWPMILPEN     LL_C2_APB1_GRP2_DisableClockSleep\n

+  *         APB1HLPENR   OPAMPLPEN     LL_C2_APB1_GRP2_DisableClockSleep\n

+  *         APB1HLPENR   MDIOSLPEN     LL_C2_APB1_GRP2_DisableClockSleep\n

+  *         APB1HLPENR   FDCANLPEN     LL_C2_APB1_GRP2_DisableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB1_GRP2_PERIPH_CRS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1

+  *         @arg @ref LL_APB1_GRP2_PERIPH_OPAMP

+  *         @arg @ref LL_APB1_GRP2_PERIPH_MDIOS

+  *         @arg @ref LL_APB1_GRP2_PERIPH_FDCAN

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_APB1_GRP2_DisableClockSleep(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C2->APB1HLPENR, Periphs);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup BUS_LL_EF_APB2 APB2

+  * @{

+  */

+

+/**

+  * @brief  Enable C2 APB2 peripherals clock.

+  * @rmtoll APB2ENR      TIM1EN        LL_C2_APB2_GRP1_EnableClock\n

+  *         APB2ENR      TIM8EN        LL_C2_APB2_GRP1_EnableClock\n

+  *         APB2ENR      USART1EN      LL_C2_APB2_GRP1_EnableClock\n

+  *         APB2ENR      USART6EN      LL_C2_APB2_GRP1_EnableClock\n

+  *         APB2ENR      SPI1EN        LL_C2_APB2_GRP1_EnableClock\n

+  *         APB2ENR      SPI4EN        LL_C2_APB2_GRP1_EnableClock\n

+  *         APB2ENR      TIM15EN       LL_C2_APB2_GRP1_EnableClock\n

+  *         APB2ENR      TIM16EN       LL_C2_APB2_GRP1_EnableClock\n

+  *         APB2ENR      TIM17EN       LL_C2_APB2_GRP1_EnableClock\n

+  *         APB2ENR      SPI5EN        LL_C2_APB2_GRP1_EnableClock\n

+  *         APB2ENR      SAI1EN        LL_C2_APB2_GRP1_EnableClock\n

+  *         APB2ENR      SAI2EN        LL_C2_APB2_GRP1_EnableClock\n

+  *         APB2ENR      SAI3EN        LL_C2_APB2_GRP1_EnableClock\n

+  *         APB2ENR      DFSDM1EN      LL_C2_APB2_GRP1_EnableClock\n

+  *         APB2ENR      HRTIMEN       LL_C2_APB2_GRP1_EnableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3

+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_APB2_GRP1_EnableClock(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C2->APB2ENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C2->APB2ENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Check if C2 APB2 peripheral clock is enabled or not

+  * @rmtoll APB2ENR      TIM1EN        LL_C2_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      TIM8EN        LL_C2_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      USART1EN      LL_C2_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      USART6EN      LL_C2_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      SPI1EN        LL_C2_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      SPI4EN        LL_C2_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      TIM15EN       LL_C2_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      TIM16EN       LL_C2_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      TIM17EN       LL_C2_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      SPI5EN        LL_C2_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      SAI1EN        LL_C2_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      SAI2EN        LL_C2_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      SAI3EN        LL_C2_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      DFSDM1EN      LL_C2_APB2_GRP1_IsEnabledClock\n

+  *         APB2ENR      HRTIMEN       LL_C2_APB2_GRP1_IsEnabledClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3

+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM

+  * @retval uint32_t

+*/

+__STATIC_INLINE uint32_t LL_C2_APB2_GRP1_IsEnabledClock(uint32_t Periphs)

+{

+  return ((READ_BIT(RCC_C2->APB2ENR, Periphs) == Periphs)?1U:0U);

+}

+

+/**

+  * @brief  Disable C2 APB2 peripherals clock.

+  * @rmtoll APB2ENR      TIM1EN        LL_C2_APB2_GRP1_DisableClock\n

+  *         APB2ENR      TIM8EN        LL_C2_APB2_GRP1_DisableClock\n

+  *         APB2ENR      USART1EN      LL_C2_APB2_GRP1_DisableClock\n

+  *         APB2ENR      USART6EN      LL_C2_APB2_GRP1_DisableClock\n

+  *         APB2ENR      SPI1EN        LL_C2_APB2_GRP1_DisableClock\n

+  *         APB2ENR      SPI4EN        LL_C2_APB2_GRP1_DisableClock\n

+  *         APB2ENR      TIM15EN       LL_C2_APB2_GRP1_DisableClock\n

+  *         APB2ENR      TIM16EN       LL_C2_APB2_GRP1_DisableClock\n

+  *         APB2ENR      TIM17EN       LL_C2_APB2_GRP1_DisableClock\n

+  *         APB2ENR      SPI5EN        LL_C2_APB2_GRP1_DisableClock\n

+  *         APB2ENR      SAI1EN        LL_C2_APB2_GRP1_DisableClock\n

+  *         APB2ENR      SAI2EN        LL_C2_APB2_GRP1_DisableClock\n

+  *         APB2ENR      SAI3EN        LL_C2_APB2_GRP1_DisableClock\n

+  *         APB2ENR      DFSDM1EN      LL_C2_APB2_GRP1_DisableClock\n

+  *         APB2ENR      HRTIMEN       LL_C2_APB2_GRP1_DisableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3

+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_APB2_GRP1_DisableClock(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C2->APB2ENR, Periphs);

+}

+

+/**

+  * @brief  Enable C2 APB2 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll APB2LPENR    TIM1LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    TIM8LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    USART1LPEN    LL_C2_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    USART6LPEN    LL_C2_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    SPI1LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    SPI4LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    TIM15LPEN     LL_C2_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    TIM16LPEN     LL_C2_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    TIM17LPEN     LL_C2_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    SPI5LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    SAI1LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    SAI2LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    SAI3LPEN      LL_C2_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    DFSDM1LPEN    LL_C2_APB2_GRP1_EnableClockSleep\n

+  *         APB2LPENR    HRTIMLPEN     LL_C2_APB2_GRP1_EnableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3

+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_APB2_GRP1_EnableClockSleep(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C2->APB2LPENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C2->APB2LPENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Disable C2 APB2 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll APB2LPENR    TIM1LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    TIM8LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    USART1LPEN    LL_C2_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    USART6LPEN    LL_C2_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    SPI1LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    SPI4LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    TIM15LPEN     LL_C2_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    TIM16LPEN     LL_C2_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    TIM17LPEN     LL_C2_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    SPI5LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    SAI1LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    SAI2LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    SAI3LPEN      LL_C2_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    DFSDM1LPEN    LL_C2_APB2_GRP1_DisableClockSleep\n

+  *         APB2LPENR    HRTIMLPEN     LL_C2_APB2_GRP1_DisableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM8

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_USART6

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI4

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM15

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM16

+  *         @arg @ref LL_APB2_GRP1_PERIPH_TIM17

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SPI5

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI2

+  *         @arg @ref LL_APB2_GRP1_PERIPH_SAI3

+  *         @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1

+  *         @arg @ref LL_APB2_GRP1_PERIPH_HRTIM

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_APB2_GRP1_DisableClockSleep(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C2->APB2LPENR, Periphs);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup BUS_LL_EF_APB4 APB4

+  * @{

+  */

+

+/**

+  * @brief  Enable C2 APB4 peripherals clock.

+  * @rmtoll APB4ENR      SYSCFGEN      LL_C2_APB4_GRP1_EnableClock\n

+  *         APB4ENR      LPUART1EN     LL_C2_APB4_GRP1_EnableClock\n

+  *         APB4ENR      SPI6EN        LL_C2_APB4_GRP1_EnableClock\n

+  *         APB4ENR      I2C4EN        LL_C2_APB4_GRP1_EnableClock\n

+  *         APB4ENR      LPTIM2EN      LL_C2_APB4_GRP1_EnableClock\n

+  *         APB4ENR      LPTIM3EN      LL_C2_APB4_GRP1_EnableClock\n

+  *         APB4ENR      LPTIM4EN      LL_C2_APB4_GRP1_EnableClock\n

+  *         APB4ENR      LPTIM5EN      LL_C2_APB4_GRP1_EnableClock\n

+  *         APB4ENR      COMP12EN      LL_C2_APB4_GRP1_EnableClock\n

+  *         APB4ENR      VREFEN        LL_C2_APB4_GRP1_EnableClock\n

+  *         APB4ENR      RTCAPBEN      LL_C2_APB4_GRP1_EnableClock\n

+  *         APB4ENR      SAI4EN        LL_C2_APB4_GRP1_EnableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5

+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_APB4_GRP1_EnableClock(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C2->APB4ENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C2->APB4ENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Check if C2 APB4 peripheral clock is enabled or not

+  * @rmtoll APB4ENR      SYSCFGEN      LL_C2_APB4_GRP1_IsEnabledClock\n

+  *         APB4ENR      LPUART1EN     LL_C2_APB4_GRP1_IsEnabledClock\n

+  *         APB4ENR      SPI6EN        LL_C2_APB4_GRP1_IsEnabledClock\n

+  *         APB4ENR      I2C4EN        LL_C2_APB4_GRP1_IsEnabledClock\n

+  *         APB4ENR      LPTIM2EN      LL_C2_APB4_GRP1_IsEnabledClock\n

+  *         APB4ENR      LPTIM3EN      LL_C2_APB4_GRP1_IsEnabledClock\n

+  *         APB4ENR      LPTIM4EN      LL_C2_APB4_GRP1_IsEnabledClock\n

+  *         APB4ENR      LPTIM5EN      LL_C2_APB4_GRP1_IsEnabledClock\n

+  *         APB4ENR      COMP12EN      LL_C2_APB4_GRP1_IsEnabledClock\n

+  *         APB4ENR      VREFEN        LL_C2_APB4_GRP1_IsEnabledClock\n

+  *         APB4ENR      RTCAPBEN      LL_C2_APB4_GRP1_IsEnabledClock\n

+  *         APB4ENR      SAI4EN        LL_C2_APB4_GRP1_IsEnabledClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5

+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4

+  * @retval uint32_t

+*/

+__STATIC_INLINE uint32_t LL_C2_APB4_GRP1_IsEnabledClock(uint32_t Periphs)

+{

+  return ((READ_BIT(RCC_C2->APB4ENR, Periphs) == Periphs)?1U:0U);

+}

+

+/**

+  * @brief  Disable C2 APB4 peripherals clock.

+  * @rmtoll APB4ENR      SYSCFGEN      LL_C2_APB4_GRP1_DisableClock\n

+  *         APB4ENR      LPUART1EN     LL_C2_APB4_GRP1_DisableClock\n

+  *         APB4ENR      SPI6EN        LL_C2_APB4_GRP1_DisableClock\n

+  *         APB4ENR      I2C4EN        LL_C2_APB4_GRP1_DisableClock\n

+  *         APB4ENR      LPTIM2EN      LL_C2_APB4_GRP1_DisableClock\n

+  *         APB4ENR      LPTIM3EN      LL_C2_APB4_GRP1_DisableClock\n

+  *         APB4ENR      LPTIM4EN      LL_C2_APB4_GRP1_DisableClock\n

+  *         APB4ENR      LPTIM5EN      LL_C2_APB4_GRP1_DisableClock\n

+  *         APB4ENR      COMP12EN      LL_C2_APB4_GRP1_DisableClock\n

+  *         APB4ENR      VREFEN        LL_C2_APB4_GRP1_DisableClock\n

+  *         APB4ENR      RTCAPBEN      LL_C2_APB4_GRP1_DisableClock\n

+  *         APB4ENR      SAI4EN        LL_C2_APB4_GRP1_DisableClock

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5

+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_APB4_GRP1_DisableClock(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C2->APB4ENR, Periphs);

+}

+

+/**

+  * @brief  Enable C2 APB4 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll APB4LPENR    SYSCFGLPEN    LL_C2_APB4_GRP1_EnableClockSleep\n

+  *         APB4LPENR    LPUART1LPEN   LL_C2_APB4_GRP1_EnableClockSleep\n

+  *         APB4LPENR    SPI6LPEN      LL_C2_APB4_GRP1_EnableClockSleep\n

+  *         APB4LPENR    I2C4LPEN      LL_C2_APB4_GRP1_EnableClockSleep\n

+  *         APB4LPENR    LPTIM2LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n

+  *         APB4LPENR    LPTIM3LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n

+  *         APB4LPENR    LPTIM4LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n

+  *         APB4LPENR    LPTIM5LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n

+  *         APB4LPENR    COMP12LPEN    LL_C2_APB4_GRP1_EnableClockSleep\n

+  *         APB4LPENR    VREFLPEN      LL_C2_APB4_GRP1_EnableClockSleep\n

+  *         APB4LPENR    RTCAPBLPEN    LL_C2_APB4_GRP1_EnableClockSleep\n

+  *         APB4LPENR    SAI4LPEN      LL_C2_APB4_GRP1_EnableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5

+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_APB4_GRP1_EnableClockSleep(uint32_t Periphs)

+{

+  __IO uint32_t tmpreg;

+  SET_BIT(RCC_C2->APB4LPENR, Periphs);

+  /* Delay after an RCC peripheral clock enabling */

+  tmpreg = READ_BIT(RCC_C2->APB4LPENR, Periphs);

+  (void)tmpreg;

+}

+

+/**

+  * @brief  Disable C2 APB4 peripherals clock during Low Power (Sleep) mode.

+  * @rmtoll APB4LPENR    SYSCFGLPEN    LL_C2_APB4_GRP1_DisableClockSleep\n

+  *         APB4LPENR    LPUART1LPEN   LL_C2_APB4_GRP1_DisableClockSleep\n

+  *         APB4LPENR    SPI6LPEN      LL_C2_APB4_GRP1_DisableClockSleep\n

+  *         APB4LPENR    I2C4LPEN      LL_C2_APB4_GRP1_DisableClockSleep\n

+  *         APB4LPENR    LPTIM2LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n

+  *         APB4LPENR    LPTIM3LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n

+  *         APB4LPENR    LPTIM4LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n

+  *         APB4LPENR    LPTIM5LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n

+  *         APB4LPENR    COMP12LPEN    LL_C2_APB4_GRP1_DisableClockSleep\n

+  *         APB4LPENR    VREFLPEN      LL_C2_APB4_GRP1_DisableClockSleep\n

+  *         APB4LPENR    RTCAPBLPEN    LL_C2_APB4_GRP1_DisableClockSleep\n

+  *         APB4LPENR    SAI4LPEN      LL_C2_APB4_GRP1_DisableClockSleep

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SYSCFG

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPUART1

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SPI6

+  *         @arg @ref LL_APB4_GRP1_PERIPH_I2C4

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM2

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM3

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM4

+  *         @arg @ref LL_APB4_GRP1_PERIPH_LPTIM5

+  *         @arg @ref LL_APB4_GRP1_PERIPH_COMP12

+  *         @arg @ref LL_APB4_GRP1_PERIPH_VREF

+  *         @arg @ref LL_APB4_GRP1_PERIPH_RTCAPB

+  *         @arg @ref LL_APB4_GRP1_PERIPH_SAI4

+  * @retval None

+*/

+__STATIC_INLINE void LL_C2_APB4_GRP1_DisableClockSleep(uint32_t Periphs)

+{

+  CLEAR_BIT(RCC_C2->APB4LPENR, Periphs);

+}

+

+/**

+  * @}

+  */

+

+#endif /*DUAL_CORE*/

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* defined(RCC) */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_LL_BUS_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_comp.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_comp.h
new file mode 100644
index 0000000000..87acde6caf
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_comp.h
@@ -0,0 +1,863 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_comp.h

+  * @author  MCD Application Team

+  * @brief   Header file of COMP LL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef __STM32H7xx_LL_COMP_H

+#define __STM32H7xx_LL_COMP_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+#if defined (COMP1) || defined (COMP2)

+

+/** @defgroup COMP_LL COMP

+  * @{

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup COMP_LL_Private_Constants COMP Private Constants

+  * @{

+  */

+

+/* COMP registers bits positions */

+#define LL_COMP_OUTPUT_LEVEL_BITOFFSET_POS (30U) /* Value equivalent to POSITION_VAL(COMP_CSR_VALUE) */

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/* Exported types ------------------------------------------------------------*/

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup COMP_LL_ES_INIT COMP Exported Init structure

+  * @{

+  */

+

+/**

+  * @brief  Structure definition of some features of COMP instance.

+  */

+typedef struct

+{

+  uint32_t PowerMode;                   /*!< Set comparator operating mode to adjust power and speed.

+                                             This parameter can be a value of @ref COMP_LL_EC_POWERMODE

+                                             

+                                             This feature can be modified afterwards using unitary function @ref LL_COMP_SetPowerMode(). */

+

+  uint32_t InputPlus;                   /*!< Set comparator input plus (non-inverting input).

+                                             This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS

+                                             

+                                             This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputPlus(). */

+

+  uint32_t InputMinus;                  /*!< Set comparator input minus (inverting input).

+                                             This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS

+                                             

+                                             This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputMinus(). */

+

+  uint32_t InputHysteresis;             /*!< Set comparator hysteresis mode of the input minus.

+                                             This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS

+                                             

+                                             This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputHysteresis(). */

+

+  uint32_t OutputPolarity;              /*!< Set comparator output polarity.

+                                             This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY

+                                             

+                                             This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputPolarity(). */

+

+  uint32_t OutputBlankingSource;        /*!< Set comparator blanking source.

+                                             This parameter can be a value of @ref COMP_LL_EC_OUTPUT_BLANKING_SOURCE

+                                             

+                                             This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputBlankingSource(). */

+

+} LL_COMP_InitTypeDef;

+

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup COMP_LL_Exported_Constants COMP Exported Constants

+  * @{

+  */

+

+/** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode

+  * @{

+  */

+#define LL_COMP_WINDOWMODE_DISABLE                 (0x00000000UL)          /*!< Window mode disable: Comparators 1 and 2 are independent */

+#define LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CFGRx_WINMODE)    /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */

+/**

+  * @}

+  */

+

+/** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode

+  * @{

+  */

+#define LL_COMP_POWERMODE_HIGHSPEED     (0x00000000UL)                                /*!< COMP power mode to high speed */

+#define LL_COMP_POWERMODE_MEDIUMSPEED   (COMP_CFGRx_PWRMODE_0)                        /*!< COMP power mode to medium speed */

+#define LL_COMP_POWERMODE_ULTRALOWPOWER (COMP_CFGRx_PWRMODE_1 | COMP_CFGRx_PWRMODE_0) /*!< COMP power mode to ultra-low power */

+/**

+  * @}

+  */

+

+/** @defgroup COMP_LL_EC_INPUT_PLUS Comparator inputs - Input plus (input non-inverting) selection

+  * @{

+  */

+#define LL_COMP_INPUT_PLUS_IO1          (0x00000000UL)                           /*!< Comparator input plus connected to IO1 (pin PB0 for COMP1, pin PE9 for COMP2) */

+#define LL_COMP_INPUT_PLUS_IO2          (COMP_CFGRx_INPSEL)                      /*!< Comparator input plus connected to IO2 (pin PB2 for COMP1, pin PE11 for COMP2) */

+#if defined (COMP_CFGRx_INP2SEL)

+#define LL_COMP_INPUT_PLUS_DAC2_CH1     (COMP_CFGRx_INP2SEL)                     /*!< Comparator input plus 2 connected to (DAC2_CH1 for COMP1)                      */

+#endif

+/**

+  * @}

+  */

+

+/** @defgroup COMP_LL_EC_INPUT_MINUS Comparator inputs - Input minus (input inverting) selection

+  * @{

+  */

+#define LL_COMP_INPUT_MINUS_1_4VREFINT      (                                                                                        COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)   /*!< Comparator input minus connected to 1/4 VrefInt  */

+#define LL_COMP_INPUT_MINUS_1_2VREFINT      (                                                                  COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)   /*!< Comparator input minus connected to 1/2 VrefInt  */

+#define LL_COMP_INPUT_MINUS_3_4VREFINT      (                                            COMP_CFGRx_INMSEL_1                       | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN)   /*!< Comparator input minus connected to 3/4 VrefInt  */

+#define LL_COMP_INPUT_MINUS_VREFINT         (                                            COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0 | COMP_CFGRx_SCALEN                   )   /*!< Comparator input minus connected to VrefInt */

+#define LL_COMP_INPUT_MINUS_DAC1_CH1        (                      COMP_CFGRx_INMSEL_2                                                                                   )   /*!< Comparator input minus connected to DAC1 channel 1 (DAC_OUT1)  */

+#define LL_COMP_INPUT_MINUS_DAC1_CH2        (                      COMP_CFGRx_INMSEL_2                       | COMP_CFGRx_INMSEL_0                                       )   /*!< Comparator input minus connected to DAC1 channel 2 (DAC_OUT2)  */

+#define LL_COMP_INPUT_MINUS_IO1             (                      COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1                                                             )   /*!< Comparator input minus connected to IO1 (pin PB1 for COMP1, pin PE10 for COMP2) */

+#define LL_COMP_INPUT_MINUS_IO2             (                      COMP_CFGRx_INMSEL_2 | COMP_CFGRx_INMSEL_1 | COMP_CFGRx_INMSEL_0                                       )   /*!< Comparator input minus connected to IO2 (pin PC4 for COMP1, pin PE7 for COMP2) */

+#if defined (COMP_CFGRx_INMSEL_3)

+#define LL_COMP_INPUT_MINUS_TPSENS_DAC2CH1  (COMP_CFGRx_INMSEL_3                                                                                                         )   /*!< Comparator input minus connected to  (temp sensor which is exist in ADC for COMP1, DAC2_CH1 for COMP2) */

+#define LL_COMP_INPUT_MINUS_VBAT_VDDAP      (COMP_CFGRx_INMSEL_3                                             | COMP_CFGRx_INMSEL_0                                       )   /*!< Comparator input minus connected to  (VBAT/4 for COMP1, VDDAP for COMP2) */

+#endif

+/**

+  * @}

+  */

+

+/** @defgroup COMP_LL_EC_INPUT_HYSTERESIS Comparator input - Hysteresis

+  * @{

+  */

+#define LL_COMP_HYSTERESIS_NONE         (0x00000000UL)                            /*!< No hysteresis */

+#define LL_COMP_HYSTERESIS_LOW          (                    COMP_CFGRx_HYST_0)   /*!< Hysteresis level low */

+#define LL_COMP_HYSTERESIS_MEDIUM       (COMP_CFGRx_HYST_1                    )   /*!< Hysteresis level medium */

+#define LL_COMP_HYSTERESIS_HIGH         (COMP_CFGRx_HYST_1 | COMP_CFGRx_HYST_0)   /*!< Hysteresis level high */

+/**

+  * @}

+  */

+

+/** @defgroup COMP_LL_EC_OUTPUT_POLARITY Comparator output - Output polarity

+  * @{

+  */

+#define LL_COMP_OUTPUTPOL_NONINVERTED   (0x00000000UL)          /*!< COMP output polarity is not inverted: comparator output is high when the plus (non-inverting) input is at a higher voltage than the minus (inverting) input */

+#define LL_COMP_OUTPUTPOL_INVERTED      (COMP_CFGRx_POLARITY)   /*!< COMP output polarity is inverted: comparator output is low when the plus (non-inverting) input is at a lower voltage than the minus (inverting) input */

+/**

+  * @}

+  */

+

+/** @defgroup COMP_LL_EC_OUTPUT_BLANKING_SOURCE Comparator output - Blanking source

+  * @{

+  */

+#define LL_COMP_BLANKINGSRC_NONE      (0x00000000UL)                                  /*!<Comparator output without blanking */

+#define LL_COMP_BLANKINGSRC_TIM1_OC5  (COMP_CFGRx_BLANKING_0)                         /*!< Comparator output blanking source TIM1 OC5 (common to all COMP instances: COMP1, COMP2) */

+#define LL_COMP_BLANKINGSRC_TIM2_OC3  (COMP_CFGRx_BLANKING_1)                         /*!< Comparator output blanking source TIM2 OC3 (common to all COMP instances: COMP1, COMP2) */

+#define LL_COMP_BLANKINGSRC_TIM3_OC3  (COMP_CFGRx_BLANKING_0 |COMP_CFGRx_BLANKING_1)  /*!< Comparator output blanking source TIM3 OC3 (common to all COMP instances: COMP1, COMP2) */

+#define LL_COMP_BLANKINGSRC_TIM3_OC4  (COMP_CFGRx_BLANKING_2)                         /*!< Comparator output blanking source TIM3 OC4 (common to all COMP instances: COMP1, COMP2) */

+#define LL_COMP_BLANKINGSRC_TIM8_OC5  (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_0)   /*!< Comparator output blanking source TIM8 OC5 (common to all COMP instances: COMP1, COMP2) */

+#define LL_COMP_BLANKINGSRC_TIM15_OC1 (COMP_CFGRx_BLANKING_2|COMP_CFGRx_BLANKING_1)   /*!< Comparator output blanking source TIM15 OC1 (common to all COMP instances: COMP1, COMP2) */

+/**

+  * @}

+  */

+

+/** @defgroup COMP_LL_EC_OUTPUT_LEVEL Comparator output - Output level

+  * @{

+  */

+#define LL_COMP_OUTPUT_LEVEL_LOW        (0x00000000UL)           /*!< Comparator output level low (if the polarity is not inverted, otherwise to be complemented) */

+#define LL_COMP_OUTPUT_LEVEL_HIGH       (0x00000001UL)           /*!< Comparator output level high (if the polarity is not inverted, otherwise to be complemented) */

+/**

+  * @}

+  */

+/** @defgroup COMP_LL_EC_OUTPUT_BKIN_TIMER Comparator output - Output to BKIN timer

+  * @{

+  */

+#define LL_COMP_AF_PA6          COMP_OR_AFOPA6       /*!< Comparator Alternate Function PA6 source selected to timer BKIN input  */

+#define LL_COMP_AF_PA8          COMP_OR_AFOPA8       /*!< Comparator Alternate Function PA8 source selected to timer BKIN input  */

+#define LL_COMP_AF_PB12         COMP_OR_AFOPB12      /*!< Comparator Alternate Function PB12 source selected to timer BKIN input */

+#define LL_COMP_AF_PE6          COMP_OR_AFOPE6       /*!< Comparator Alternate Function PE6 source selected to timer BKIN input  */

+#define LL_COMP_AF_PE15         COMP_OR_AFOPE15      /*!< Comparator Alternate Function PE15 source selected to timer BKIN input */

+#define LL_COMP_AF_PG2          COMP_OR_AFOPG2       /*!< Comparator Alternate Function PG2 source selected to timer BKIN input  */

+#define LL_COMP_AF_PG3          COMP_OR_AFOPG3       /*!< Comparator Alternate Function PG3 source selected to timer BKIN input  */

+#define LL_COMP_AF_PG4          COMP_OR_AFOPG4       /*!< Comparator Alternate Function PG4 source selected to timer BKIN input  */

+#define LL_COMP_AF_PI1          COMP_OR_AFOPI1       /*!< Comparator Alternate Function PI1 source selected to timer BKIN input  */

+#define LL_COMP_AF_PI4          COMP_OR_AFOPI4       /*!< Comparator Alternate Function PI4 source selected to timer BKIN input  */

+#define LL_COMP_AF_PK2          COMP_OR_AFOPK2       /*!< Comparator Alternate Function PK2 source selected to timer BKIN input  */

+/**

+  * @}

+  */

+

+/** @defgroup COMP_LL_EC_HW_DELAYS  Definitions of COMP hardware constraints delays

+  * @note   Only COMP IP HW delays are defined in COMP LL driver driver,

+  *         not timeout values.

+  *         For details on delays values, refer to descriptions in source code

+  *         above each literal definition.

+  * @{

+  */

+

+/* Delay for comparator startup time.                                         */

+/* Note: Delay required to reach propagation delay specification.             */

+/* Literal set to maximum value (refer to device datasheet,                   */

+/* parameter "tSTART").                                                       */

+/* Unit: us                                                                   */

+#define LL_COMP_DELAY_STARTUP_US          ( 80UL)  /*!< Delay for COMP startup time */

+

+/* Delay for comparator voltage scaler stabilization time.                    */

+/* Note: Voltage scaler is used when selecting comparator input               */

+/*       based on VrefInt: VrefInt or subdivision of VrefInt.                 */

+/* Literal set to maximum value (refer to device datasheet,                   */

+/* parameter "tSTART_SCALER").                                                */

+/* Unit: us                                                                   */

+#define LL_COMP_DELAY_VOLTAGE_SCALER_STAB_US ( 200UL)  /*!< Delay for COMP voltage scaler stabilization time */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup COMP_LL_Exported_Macros COMP Exported Macros

+  * @{

+  */

+/** @defgroup COMP_LL_EM_WRITE_READ Common write and read registers macro

+  * @{

+  */

+

+/**

+  * @brief  Write a value in COMP register

+  * @param  __INSTANCE__ comparator instance

+  * @param  __REG__ Register to be written

+  * @param  __VALUE__ Value to be written in the register

+  * @retval None

+  */

+#define LL_COMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

+

+/**

+  * @brief  Read a value in COMP register

+  * @param  __INSTANCE__ comparator instance

+  * @param  __REG__ Register to be read

+  * @retval Register value

+  */

+#define LL_COMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)

+/**

+  * @}

+  */

+

+/** @defgroup COMP_LL_EM_HELPER_MACRO COMP helper macro

+  * @{

+  */

+

+/**

+  * @brief  Helper macro to select the COMP common instance

+  *         to which is belonging the selected COMP instance.

+  * @note   COMP common register instance can be used to

+  *         set parameters common to several COMP instances.

+  *         Refer to functions having argument "COMPxy_COMMON" as parameter.

+  * @param  __COMPx__ COMP instance

+  * @retval COMP common instance or value "0" if there is no COMP common instance.

+  */

+#define __LL_COMP_COMMON_INSTANCE(__COMPx__)                                   \

+  (COMP12_COMMON)

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup COMP_LL_Exported_Functions COMP Exported Functions

+  * @{

+  */

+

+/** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration of COMP hierarchical scope: common to several COMP instances

+  * @{

+  */

+

+/**

+  * @brief  Set window mode of a pair of comparators instances

+  *         (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).

+  * @rmtoll CFGRx    WINMODE        LL_COMP_SetCommonWindowMode

+  * @param  COMPxy_COMMON Comparator common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )

+  * @param  WindowMode This parameter can be one of the following values:

+  *         @arg @ref LL_COMP_WINDOWMODE_DISABLE

+  *         @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON

+  * @retval None

+  */

+__STATIC_INLINE void LL_COMP_SetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON, uint32_t WindowMode)

+{

+  /* Note: On this STM32 serie, window mode can be set only                   */

+  /*       from COMP instance: COMP2.                                         */

+  MODIFY_REG(COMPxy_COMMON->CFGR, COMP_CFGRx_WINMODE, WindowMode);

+}

+

+/**

+  * @brief  Get window mode of a pair of comparators instances

+  *         (2 consecutive COMP instances odd and even COMP<x> and COMP<x+1>).

+  * @rmtoll CFGRx    WINMODE        LL_COMP_GetCommonWindowMode

+  * @param  COMPxy_COMMON Comparator common instance

+  *         (can be set directly from CMSIS definition or by using helper macro @ref __LL_COMP_COMMON_INSTANCE() )

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_COMP_WINDOWMODE_DISABLE

+  *         @arg @ref LL_COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON

+  */

+__STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(COMP_Common_TypeDef *COMPxy_COMMON)

+{

+  return (uint32_t)(READ_BIT(COMPxy_COMMON->CFGR, COMP_CFGRx_WINMODE));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup COMP_LL_EF_Configuration_comparator_modes Configuration of comparator modes

+  * @{

+  */

+

+/**

+  * @brief  Set comparator instance operating mode to adjust power and speed.

+  * @rmtoll CFGRx    PWRMODE        LL_COMP_SetPowerMode

+  * @param  COMPx Comparator instance

+  * @param  PowerMode This parameter can be one of the following values:

+  *         @arg @ref LL_COMP_POWERMODE_HIGHSPEED

+  *         @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED

+  *         @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER

+  * @retval None

+  */

+__STATIC_INLINE void LL_COMP_SetPowerMode(COMP_TypeDef *COMPx, uint32_t PowerMode)

+{

+  MODIFY_REG(COMPx->CFGR, COMP_CFGRx_PWRMODE, PowerMode);

+}

+

+/**

+  * @brief  Get comparator instance operating mode to adjust power and speed.

+  * @rmtoll CFGRx    PWRMODE        LL_COMP_GetPowerMode

+  * @param  COMPx Comparator instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_COMP_POWERMODE_HIGHSPEED

+  *         @arg @ref LL_COMP_POWERMODE_MEDIUMSPEED

+  *         @arg @ref LL_COMP_POWERMODE_ULTRALOWPOWER

+  */

+__STATIC_INLINE uint32_t LL_COMP_GetPowerMode(COMP_TypeDef *COMPx)

+{

+  return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_PWRMODE));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup COMP_LL_EF_Configuration_comparator_inputs Configuration of comparator inputs

+  * @{

+  */

+

+/**

+  * @brief  Set comparator inputs minus (inverting) and plus (non-inverting).

+  * @note   In case of comparator input selected to be connected to IO:

+  *         GPIO pins are specific to each comparator instance.

+  *         Refer to description of parameters or to reference manual.

+  * @note   On this STM32 serie, scaler bridge is configurable:

+  *         to optimize power consumption, this function enables the

+  *         voltage scaler bridge only when required

+  *         (when selecting comparator input based on VrefInt: VrefInt or

+  *         subdivision of VrefInt).

+  *         - For scaler bridge power consumption values, 

+  *           refer to device datasheet, parameter "IDDA(SCALER)".

+  *         - Voltage scaler requires a delay for voltage stabilization.

+  *           Refer to device datasheet, parameter "tSTART_SCALER".

+  *         - Scaler bridge is common for all comparator instances,

+  *           therefore if at least one of the comparator instance

+  *           is requiring the scaler bridge, it remains enabled.

+  * @rmtoll CFGRx      INMSEL         LL_COMP_ConfigInputs\n

+  *         CFGRx      INPSEL         LL_COMP_ConfigInputs\n

+  *         CFGRx      BRGEN          LL_COMP_ConfigInputs\n

+  *         CFGRx      SCALEN         LL_COMP_ConfigInputs

+  * @param  COMPx Comparator instance

+  * @param  InputMinus This parameter can be one of the following values:

+  *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT

+  *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT

+  *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT

+  *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT

+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1

+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2 

+  *         @arg @ref LL_COMP_INPUT_MINUS_IO1

+  *         @arg @ref LL_COMP_INPUT_MINUS_IO2

+#if defined (COMP_CFGRx_INMSEL_3)

+  *         @arg @ref LL_COMP_INPUT_MINUS_TPSENS_DAC2CH1

+  *         @arg @ref LL_COMP_INPUT_MINUS_VBAT_VDDAP

+#endif

+  * @param  InputPlus This parameter can be one of the following values:

+  *         @arg @ref LL_COMP_INPUT_PLUS_IO1

+  *         @arg @ref LL_COMP_INPUT_PLUS_IO2

+#if defined (COMP_CFGRx_INP2SEL)

+  *         @arg @ref LL_COMP_INPUT_PLUS_DAC2_CH1

+#endif

+  * @retval None

+  */

+__STATIC_INLINE void LL_COMP_ConfigInputs(COMP_TypeDef *COMPx, uint32_t InputMinus, uint32_t InputPlus)

+{

+#if defined (COMP_CFGRx_INP2SEL)

+  MODIFY_REG(COMPx->CFGR,

+             COMP_CFGRx_INMSEL | COMP_CFGRx_INPSEL | 

+             COMP_CFGRx_INP2SEL | 

+             COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN,

+             InputMinus | InputPlus);

+#else

+  MODIFY_REG(COMPx->CFGR,

+             COMP_CFGRx_INMSEL | COMP_CFGRx_INPSEL | 

+             COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN,

+             InputMinus | InputPlus);

+#endif

+}

+

+/**

+  * @brief  Set comparator input plus (non-inverting).

+  * @note   In case of comparator input selected to be connected to IO:

+  *         GPIO pins are specific to each comparator instance.

+  *         Refer to description of parameters or to reference manual.

+  * @rmtoll CFGRx    INPSEL         LL_COMP_SetInputPlus

+  * @param  COMPx Comparator instance

+  * @param  InputPlus This parameter can be one of the following values:

+  *         @arg @ref LL_COMP_INPUT_PLUS_IO1

+  *         @arg @ref LL_COMP_INPUT_PLUS_IO2

+#if defined (COMP_CFGRx_INP2SEL)

+  *         @arg @ref LL_COMP_INPUT_PLUS_DAC2_CH1

+#endif

+  * @retval None

+  */

+__STATIC_INLINE void LL_COMP_SetInputPlus(COMP_TypeDef *COMPx, uint32_t InputPlus)

+{

+#if defined (COMP_CFGRx_INP2SEL)

+  MODIFY_REG(COMPx->CFGR, COMP_CFGRx_INPSEL | COMP_CFGRx_INP2SEL , InputPlus);

+#else

+  MODIFY_REG(COMPx->CFGR, COMP_CFGRx_INPSEL , InputPlus);

+#endif

+}

+

+/**

+  * @brief  Get comparator input plus (non-inverting).

+  * @note   In case of comparator input selected to be connected to IO:

+  *         GPIO pins are specific to each comparator instance.

+  *         Refer to description of parameters or to reference manual.

+  * @rmtoll CFGRx    INPSEL         LL_COMP_GetInputPlus

+  * @param  COMPx Comparator instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_COMP_INPUT_PLUS_IO1

+  *         @arg @ref LL_COMP_INPUT_PLUS_IO2

+#if defined (COMP_CFGRx_INP2SEL)

+  *         @arg @ref LL_COMP_INPUT_PLUS_DAC2_CH1

+#endif

+  */

+__STATIC_INLINE uint32_t LL_COMP_GetInputPlus(COMP_TypeDef *COMPx)

+{

+#if defined (COMP_CFGRx_INP2SEL)

+  return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_INPSEL | COMP_CFGRx_INP2SEL));

+#else

+  return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_INPSEL));

+#endif

+}

+

+/**

+  * @brief  Set comparator input minus (inverting).

+  * @note   In case of comparator input selected to be connected to IO:

+  *         GPIO pins are specific to each comparator instance.

+  *         Refer to description of parameters or to reference manual.

+  * @note   On this STM32 serie, scaler bridge is configurable:

+  *         to optimize power consumption, this function enables the

+  *         voltage scaler bridge only when required

+  *         (when selecting comparator input based on VrefInt: VrefInt or

+  *         subdivision of VrefInt).

+  *         - For scaler bridge power consumption values, 

+  *           refer to device datasheet, parameter "IDDA(SCALER)".

+  *         - Voltage scaler requires a delay for voltage stabilization.

+  *           Refer to device datasheet, parameter "tSTART_SCALER".

+  *         - Scaler bridge is common for all comparator instances,

+  *           therefore if at least one of the comparator instance

+  *           is requiring the scaler bridge, it remains enabled.

+  * @rmtoll CFGRx     INMSEL         LL_COMP_SetInputMinus\n

+  *         CFGRx     BRGEN          LL_COMP_SetInputMinus\n

+  *         CFGRx     SCALEN         LL_COMP_SetInputMinus

+  * @param  COMPx Comparator instance

+  * @param  InputMinus This parameter can be one of the following values:

+  *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT

+  *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT

+  *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT

+  *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT

+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1

+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2

+  *         @arg @ref LL_COMP_INPUT_MINUS_IO1

+  *         @arg @ref LL_COMP_INPUT_MINUS_IO2

+#if defined (COMP_CFGRx_INMSEL_3)

+  *         @arg @ref LL_COMP_INPUT_MINUS_TPSENS_DAC2CH1

+  *         @arg @ref LL_COMP_INPUT_MINUS_VBAT_VDDAP

+#endif

+  * @retval None

+  */

+__STATIC_INLINE void LL_COMP_SetInputMinus(COMP_TypeDef *COMPx, uint32_t InputMinus)

+{

+  MODIFY_REG(COMPx->CFGR, COMP_CFGRx_INMSEL | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN, InputMinus);

+}

+

+/**

+  * @brief  Get comparator input minus (inverting).

+  * @note   In case of comparator input selected to be connected to IO:

+  *         GPIO pins are specific to each comparator instance.

+  *         Refer to description of parameters or to reference manual.

+  * @rmtoll CFGRx     INMSEL         LL_COMP_GetInputMinus\n

+  *         CFGRx     BRGEN          LL_COMP_GetInputMinus\n

+  *         CFGRx     SCALEN         LL_COMP_GetInputMinus

+  * @param  COMPx Comparator instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_COMP_INPUT_MINUS_1_4VREFINT

+  *         @arg @ref LL_COMP_INPUT_MINUS_1_2VREFINT

+  *         @arg @ref LL_COMP_INPUT_MINUS_3_4VREFINT

+  *         @arg @ref LL_COMP_INPUT_MINUS_VREFINT

+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH1

+  *         @arg @ref LL_COMP_INPUT_MINUS_DAC1_CH2  

+  *         @arg @ref LL_COMP_INPUT_MINUS_IO1

+  *         @arg @ref LL_COMP_INPUT_MINUS_IO2

+#if defined (COMP_CFGRx_INMSEL_3)

+  *         @arg @ref LL_COMP_INPUT_MINUS_TPSENS_DAC2CH1

+  *         @arg @ref LL_COMP_INPUT_MINUS_VBAT_VDDAP

+#endif

+  */

+__STATIC_INLINE uint32_t LL_COMP_GetInputMinus(COMP_TypeDef *COMPx)

+{

+  return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_INMSEL | COMP_CFGRx_SCALEN | COMP_CFGRx_BRGEN));

+}

+

+/**

+  * @brief  Set comparator instance hysteresis mode of the input minus (inverting input).

+  * @rmtoll CFGRx    HYST           LL_COMP_SetInputHysteresis

+  * @param  COMPx Comparator instance

+  * @param  InputHysteresis This parameter can be one of the following values:

+  *         @arg @ref LL_COMP_HYSTERESIS_NONE

+  *         @arg @ref LL_COMP_HYSTERESIS_LOW

+  *         @arg @ref LL_COMP_HYSTERESIS_MEDIUM

+  *         @arg @ref LL_COMP_HYSTERESIS_HIGH

+  * @retval None

+  */

+__STATIC_INLINE void LL_COMP_SetInputHysteresis(COMP_TypeDef *COMPx, uint32_t InputHysteresis)

+{

+  MODIFY_REG(COMPx->CFGR, COMP_CFGRx_HYST, InputHysteresis);

+}

+

+/**

+  * @brief  Get comparator instance hysteresis mode of the minus (inverting) input.

+  * @rmtoll CSR      HYST           LL_COMP_GetInputHysteresis

+  * @param  COMPx Comparator instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_COMP_HYSTERESIS_NONE

+  *         @arg @ref LL_COMP_HYSTERESIS_LOW

+  *         @arg @ref LL_COMP_HYSTERESIS_MEDIUM

+  *         @arg @ref LL_COMP_HYSTERESIS_HIGH

+  */

+__STATIC_INLINE uint32_t LL_COMP_GetInputHysteresis(COMP_TypeDef *COMPx)

+{

+  return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_HYST));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup COMP_LL_EF_Configuration_comparator_output Configuration of comparator output

+  * @{

+  */

+

+/**

+  * @brief  Set comparator instance output polarity.

+  * @rmtoll CFGRx    POLARITY       LL_COMP_SetOutputPolarity

+  * @param  COMPx Comparator instance

+  * @param  OutputPolarity This parameter can be one of the following values:

+  *         @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED

+  *         @arg @ref LL_COMP_OUTPUTPOL_INVERTED

+  * @retval None

+  */

+__STATIC_INLINE void LL_COMP_SetOutputPolarity(COMP_TypeDef *COMPx, uint32_t OutputPolarity)

+{

+  MODIFY_REG(COMPx->CFGR, COMP_CFGRx_POLARITY, OutputPolarity);

+}

+

+/**

+  * @brief  Get comparator instance output polarity.

+  * @rmtoll CFGRx    POLARITY       LL_COMP_GetOutputPolarity

+  * @param  COMPx Comparator instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_COMP_OUTPUTPOL_NONINVERTED

+  *         @arg @ref LL_COMP_OUTPUTPOL_INVERTED

+  */

+__STATIC_INLINE uint32_t LL_COMP_GetOutputPolarity(COMP_TypeDef *COMPx)

+{

+  return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_POLARITY));

+}

+

+/**

+  * @brief  Set comparator instance blanking source.

+  * @note   Blanking source may be specific to each comparator instance.

+  *         Refer to description of parameters or to reference manual.

+  * @note   Availability of parameters of blanking source from timer

+  *         depends on timers availability on the selected device.

+  * @rmtoll CFGR     BLANKING       LL_COMP_SetOutputBlankingSource

+  * @param  COMPx Comparator instance

+  * @param  BlankingSource This parameter can be one of the following values:

+  *         @arg @ref LL_COMP_BLANKINGSRC_NONE

+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5  

+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3

+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3

+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4

+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5

+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1 

+  * @retval None

+  */

+__STATIC_INLINE void LL_COMP_SetOutputBlankingSource(COMP_TypeDef *COMPx, uint32_t BlankingSource)

+{

+  MODIFY_REG(COMPx->CFGR, COMP_CFGRx_BLANKING, BlankingSource);

+}

+

+/**

+  * @brief  Get comparator instance blanking source.

+  * @note   Availability of parameters of blanking source from timer

+  *         depends on timers availability on the selected device.

+  * @note   Blanking source may be specific to each comparator instance.

+  *         Refer to description of parameters or to reference manual.

+  * @rmtoll CFGR     BLANKING       LL_COMP_GetOutputBlankingSource

+  * @param  COMPx Comparator instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_COMP_BLANKINGSRC_NONE

+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM1_OC5 

+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM2_OC3 

+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC3

+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM3_OC4 

+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM8_OC5  

+  *         @arg @ref LL_COMP_BLANKINGSRC_TIM15_OC1  

+  */

+__STATIC_INLINE uint32_t LL_COMP_GetOutputBlankingSource(COMP_TypeDef *COMPx)

+{

+  return (uint32_t)(READ_BIT(COMPx->CFGR, COMP_CFGRx_BLANKING));

+}

+

+/** @brief  Set the output alternate function in the Option register

+  *         in order to be used with the alternate function

+  *         of the timer break input.

+  * @rmtoll OR    AFOP       COMP_LL_EC_OUTPUT_BKIN_TIMER

+  * @param  COMPx specifies the instance.

+  * @param  CompAFx specifies the Alternate Function source selection.

+  *          This parameter can be one of the following values:

+  *            @arg @ref LL_COMP_AF_PA6

+  *            @arg @ref LL_COMP_AF_PA8

+  *            @arg @ref LL_COMP_AF_PB12

+  *            @arg @ref LL_COMP_AF_PE6

+  *            @arg @ref LL_COMP_AF_PE15

+  *            @arg @ref LL_COMP_AF_PG2

+  *            @arg @ref LL_COMP_AF_PG3

+  *            @arg @ref LL_COMP_AF_PG4

+  *            @arg @ref LL_COMP_AF_PI1

+  *            @arg @ref LL_COMP_AF_PI4

+  *            @arg @ref LL_COMP_AF_PK2

+  * @retval None

+  */

+__STATIC_INLINE void LL_COMP_SetOutputAlternateFunction(COMP_TypeDef *COMPx, uint32_t CompAFx)

+{

+  MODIFY_REG(COMP12->OR, 0x7FFUL, (COMPx == COMP1) ? ((~CompAFx) & 0x7FFUL) : CompAFx);

+}

+

+/** @brief  Get the output alternate function from the Option register.

+  * @rmtoll OR     AFOP       COMP_LL_EC_OUTPUT_BKIN_TIMER

+  * @param  COMPx specifies the Comparator instance.

+  * @retval Returned value can be one of the following values:

+  *            @arg @ref LL_COMP_AF_PA6

+  *            @arg @ref LL_COMP_AF_PA8

+  *            @arg @ref LL_COMP_AF_PB12

+  *            @arg @ref LL_COMP_AF_PE6

+  *            @arg @ref LL_COMP_AF_PE15

+  *            @arg @ref LL_COMP_AF_PG2

+  *            @arg @ref LL_COMP_AF_PG3

+  *            @arg @ref LL_COMP_AF_PG4

+  *            @arg @ref LL_COMP_AF_PI1

+  *            @arg @ref LL_COMP_AF_PI4

+  *            @arg @ref LL_COMP_AF_PK2

+  */

+__STATIC_INLINE uint32_t LL_COMP_GetOutputAlternateFunction(COMP_TypeDef *COMPx )

+{

+  return (uint32_t) ((COMPx == COMP1) ? ((~COMP12->OR) & 0x7FFUL) : (COMP12->OR &  0x7FFUL));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup COMP_LL_EF_Operation Operation on comparator instance

+  * @{

+  */

+

+/**

+  * @brief  Enable comparator instance.

+  * @note   After enable from off state, comparator requires a delay

+  *         to reach reach propagation delay specification.

+  *         Refer to device datasheet, parameter "tSTART".

+  * @rmtoll CFGR     EN             LL_COMP_Enable

+  * @param  COMPx Comparator instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_COMP_Enable(COMP_TypeDef *COMPx)

+{

+  SET_BIT(COMPx->CFGR, COMP_CFGRx_EN);

+}

+

+/**

+  * @brief  Disable comparator instance.

+  * @rmtoll CFGR     EN             LL_COMP_Disable

+  * @param  COMPx Comparator instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_COMP_Disable(COMP_TypeDef *COMPx)

+{

+  CLEAR_BIT(COMPx->CFGR, COMP_CFGRx_EN);

+}

+

+/**

+  * @brief  Get comparator enable state

+  *         (0: COMP is disabled, 1: COMP is enabled)

+  * @rmtoll CFGR     EN             LL_COMP_IsEnabled

+  * @param  COMPx Comparator instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_COMP_IsEnabled(COMP_TypeDef *COMPx)

+{

+  return ((READ_BIT(COMPx->CFGR, COMP_CFGRx_EN) == (COMP_CFGRx_EN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Lock comparator instance.

+  * @note   Once locked, comparator configuration can be accessed in read-only.

+  * @note   The only way to unlock the comparator is a device hardware reset.

+  * @rmtoll CFGR     LOCK           LL_COMP_Lock

+  * @param  COMPx Comparator instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_COMP_Lock(COMP_TypeDef *COMPx)

+{

+  SET_BIT(COMPx->CFGR, COMP_CFGRx_LOCK);

+}

+

+/**

+  * @brief  Get comparator lock state

+  *         (0: COMP is unlocked, 1: COMP is locked).

+  * @note   Once locked, comparator configuration can be accessed in read-only.

+  * @note   The only way to unlock the comparator is a device hardware reset.

+  * @rmtoll CFGR     LOCK           LL_COMP_IsLocked

+  * @param  COMPx Comparator instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_COMP_IsLocked(COMP_TypeDef *COMPx)

+{

+  return ((READ_BIT(COMPx->CFGR, COMP_CFGRx_LOCK) == (COMP_CFGRx_LOCK)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Read comparator instance output level.

+  * @note   The comparator output level depends on the selected polarity

+  *         (Refer to function @ref LL_COMP_SetOutputPolarity()).

+  *         If the comparator polarity is not inverted:

+  *          - Comparator output is low when the input plus

+  *            is at a lower voltage than the input minus

+  *          - Comparator output is high when the input plus

+  *            is at a higher voltage than the input minus

+  *         If the comparator polarity is inverted:

+  *          - Comparator output is high when the input plus

+  *            is at a lower voltage than the input minus

+  *          - Comparator output is low when the input plus

+  *            is at a higher voltage than the input minus

+  * @rmtoll CFGR     VALUE          LL_COMP_ReadOutputLevel

+  * @param  COMPx Comparator instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_COMP_OUTPUT_LEVEL_LOW

+  *         @arg @ref LL_COMP_OUTPUT_LEVEL_HIGH

+  */

+__STATIC_INLINE uint32_t LL_COMP_ReadOutputLevel(COMP_TypeDef *COMPx)

+{

+  if (COMPx == COMP1)

+  {

+    return (uint32_t)(READ_BIT(COMP12->SR, COMP_SR_C1VAL));

+  }

+  else

+  {

+    return (uint32_t)((READ_BIT(COMP12->SR, COMP_SR_C2VAL))>> 1); 

+  }

+}

+

+/**

+  * @}

+  */

+

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup COMP_LL_EF_Init Initialization and de-initialization functions

+  * @{

+  */

+

+ErrorStatus LL_COMP_DeInit(COMP_TypeDef *COMPx);

+ErrorStatus LL_COMP_Init(COMP_TypeDef *COMPx, LL_COMP_InitTypeDef *COMP_InitStruct);

+void        LL_COMP_StructInit(LL_COMP_InitTypeDef *COMP_InitStruct);

+

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* COMP1 || COMP2 */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* __STM32H7xx_LL_COMP_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_cortex.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_cortex.h
new file mode 100644
index 0000000000..c7363b9c4a
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_cortex.h
@@ -0,0 +1,669 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_cortex.h

+  * @author  MCD Application Team

+  * @brief   Header file of CORTEX LL module.

+  @verbatim

+  ==============================================================================

+                     ##### How to use this driver #####

+  ==============================================================================

+    [..]

+    The LL CORTEX driver contains a set of generic APIs that can be

+    used by user:

+      (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick

+          functions

+      (+) Low power mode configuration (SCB register of Cortex-MCU)

+      (+) MPU API to configure and enable regions

+      (+) API to access to MCU info (CPUID register)

+      (+) API to enable fault handler (SHCSR accesses)

+

+  @endverbatim

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_LL_CORTEX_H

+#define STM32H7xx_LL_CORTEX_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+/** @defgroup CORTEX_LL CORTEX

+  * @{

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+

+/* Private constants ---------------------------------------------------------*/

+

+/* Private macros ------------------------------------------------------------*/

+

+/* Exported types ------------------------------------------------------------*/

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants

+  * @{

+  */

+

+/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source

+  * @{

+  */

+#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0x00000000UL                /*!< AHB clock divided by 8 selected as SysTick clock source.*/

+#define LL_SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk  /*!< AHB clock selected as SysTick clock source. */

+/**

+  * @}

+  */

+

+/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type

+  * @{

+  */

+#define LL_HANDLER_FAULT_USG               SCB_SHCSR_USGFAULTENA_Msk              /*!< Usage fault */

+#define LL_HANDLER_FAULT_BUS               SCB_SHCSR_BUSFAULTENA_Msk              /*!< Bus fault */

+#define LL_HANDLER_FAULT_MEM               SCB_SHCSR_MEMFAULTENA_Msk              /*!< Memory management fault */

+/**

+  * @}

+  */

+

+#if __MPU_PRESENT

+

+/** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control

+  * @{

+  */

+#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     0x00000000UL                                      /*!< Disable NMI and privileged SW access */

+#define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */

+#define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */

+#define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */

+/**

+  * @}

+  */

+

+/** @defgroup CORTEX_LL_EC_REGION MPU Region Number

+  * @{

+  */

+#define LL_MPU_REGION_NUMBER0              0x00UL /*!< REGION Number 0  */

+#define LL_MPU_REGION_NUMBER1              0x01UL /*!< REGION Number 1  */

+#define LL_MPU_REGION_NUMBER2              0x02UL /*!< REGION Number 2  */

+#define LL_MPU_REGION_NUMBER3              0x03UL /*!< REGION Number 3  */

+#define LL_MPU_REGION_NUMBER4              0x04UL /*!< REGION Number 4  */

+#define LL_MPU_REGION_NUMBER5              0x05UL /*!< REGION Number 5  */

+#define LL_MPU_REGION_NUMBER6              0x06UL /*!< REGION Number 6  */

+#define LL_MPU_REGION_NUMBER7              0x07UL /*!< REGION Number 7  */

+#if !defined(CORE_CM4)

+#define LL_MPU_REGION_NUMBER8              0x08UL /*!< REGION Number 8  */

+#define LL_MPU_REGION_NUMBER9              0x09UL /*!< REGION Number 9  */

+#define LL_MPU_REGION_NUMBER10             0x0AUL /*!< REGION Number 10 */

+#define LL_MPU_REGION_NUMBER11             0x0BUL /*!< REGION Number 11 */

+#define LL_MPU_REGION_NUMBER12             0x0CUL /*!< REGION Number 12 */

+#define LL_MPU_REGION_NUMBER13             0x0DUL /*!< REGION Number 13 */

+#define LL_MPU_REGION_NUMBER14             0x0EUL /*!< REGION Number 14 */

+#define LL_MPU_REGION_NUMBER15             0x0FUL /*!< REGION Number 15 */

+#endif /* !defined(CORE_CM4) */

+/**

+  * @}

+  */

+

+/** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size

+  * @{

+  */

+#define LL_MPU_REGION_SIZE_32B             (0x04UL << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */

+#define LL_MPU_REGION_SIZE_64B             (0x05UL << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */

+#define LL_MPU_REGION_SIZE_128B            (0x06UL << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */

+#define LL_MPU_REGION_SIZE_256B            (0x07UL << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */

+#define LL_MPU_REGION_SIZE_512B            (0x08UL << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */

+#define LL_MPU_REGION_SIZE_1KB             (0x09UL << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */

+#define LL_MPU_REGION_SIZE_2KB             (0x0AUL << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */

+#define LL_MPU_REGION_SIZE_4KB             (0x0BUL << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */

+#define LL_MPU_REGION_SIZE_8KB             (0x0CUL << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */

+#define LL_MPU_REGION_SIZE_16KB            (0x0DUL << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */

+#define LL_MPU_REGION_SIZE_32KB            (0x0EUL << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */

+#define LL_MPU_REGION_SIZE_64KB            (0x0FUL << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */

+#define LL_MPU_REGION_SIZE_128KB           (0x10UL << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */

+#define LL_MPU_REGION_SIZE_256KB           (0x11UL << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */

+#define LL_MPU_REGION_SIZE_512KB           (0x12UL << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */

+#define LL_MPU_REGION_SIZE_1MB             (0x13UL << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */

+#define LL_MPU_REGION_SIZE_2MB             (0x14UL << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */

+#define LL_MPU_REGION_SIZE_4MB             (0x15UL << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */

+#define LL_MPU_REGION_SIZE_8MB             (0x16UL << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */

+#define LL_MPU_REGION_SIZE_16MB            (0x17UL << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */

+#define LL_MPU_REGION_SIZE_32MB            (0x18UL << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */

+#define LL_MPU_REGION_SIZE_64MB            (0x19UL << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */

+#define LL_MPU_REGION_SIZE_128MB           (0x1AUL << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */

+#define LL_MPU_REGION_SIZE_256MB           (0x1BUL << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */

+#define LL_MPU_REGION_SIZE_512MB           (0x1CUL << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */

+#define LL_MPU_REGION_SIZE_1GB             (0x1DUL << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */

+#define LL_MPU_REGION_SIZE_2GB             (0x1EUL << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */

+#define LL_MPU_REGION_SIZE_4GB             (0x1FUL << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */

+/**

+  * @}

+  */

+

+/** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges

+  * @{

+  */

+#define LL_MPU_REGION_NO_ACCESS            (0x00UL << MPU_RASR_AP_Pos) /*!< No access*/

+#define LL_MPU_REGION_PRIV_RW              (0x01UL << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/

+#define LL_MPU_REGION_PRIV_RW_URO          (0x02UL << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */

+#define LL_MPU_REGION_FULL_ACCESS          (0x03UL << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */

+#define LL_MPU_REGION_PRIV_RO              (0x05UL << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/

+#define LL_MPU_REGION_PRIV_RO_URO          (0x06UL << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */

+/**

+  * @}

+  */

+

+/** @defgroup CORTEX_LL_EC_TEX MPU TEX Level

+  * @{

+  */

+#define LL_MPU_TEX_LEVEL0                  (0x00UL << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */

+#define LL_MPU_TEX_LEVEL1                  (0x01UL << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */

+#define LL_MPU_TEX_LEVEL2                  (0x02UL << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */

+#define LL_MPU_TEX_LEVEL4                  (0x04UL << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */

+/**

+  * @}

+  */

+

+/** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access

+  * @{

+  */

+#define LL_MPU_INSTRUCTION_ACCESS_ENABLE   0x00UL            /*!< Instruction fetches enabled */

+#define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/

+/**

+  * @}

+  */

+

+/** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access

+  * @{

+  */

+#define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */

+#define LL_MPU_ACCESS_NOT_SHAREABLE        0x00UL           /*!< Not Shareable memory attribute */

+/**

+  * @}

+  */

+

+/** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access

+  * @{

+  */

+#define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */

+#define LL_MPU_ACCESS_NOT_CACHEABLE        0x00UL           /*!< Not Cacheable memory attribute */

+/**

+  * @}

+  */

+

+/** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access

+  * @{

+  */

+#define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */

+#define LL_MPU_ACCESS_NOT_BUFFERABLE       0x00UL           /*!< Not Bufferable memory attribute */

+/**

+  * @}

+  */

+#endif /* __MPU_PRESENT */

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions

+  * @{

+  */

+

+/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK

+  * @{

+  */

+

+/**

+  * @brief  This function checks if the Systick counter flag is active or not.

+  * @note   It can be used in timeout function on application side.

+  * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)

+{

+  return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Configures the SysTick clock source

+  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource

+  * @param  Source This parameter can be one of the following values:

+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8

+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK

+  * @retval None

+  */

+__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)

+{

+  MODIFY_REG(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK, Source);

+}

+

+/**

+  * @brief  Get the SysTick clock source

+  * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8

+  *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK

+  */

+__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)

+{

+  return (uint32_t)(READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK));

+}

+

+/**

+  * @brief  Enable SysTick exception request

+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT

+  * @retval None

+  */

+__STATIC_INLINE void LL_SYSTICK_EnableIT(void)

+{

+  SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);

+}

+

+/**

+  * @brief  Disable SysTick exception request

+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT

+  * @retval None

+  */

+__STATIC_INLINE void LL_SYSTICK_DisableIT(void)

+{

+  CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);

+}

+

+/**

+  * @brief  Checks if the SYSTICK interrupt is enabled or disabled.

+  * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)

+{

+  return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE

+  * @{

+  */

+

+/**

+  * @brief  Processor uses sleep as its low power mode

+  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPM_EnableSleep(void)

+{

+  /* Clear SLEEPDEEP bit of Cortex System Control Register */

+  CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);

+}

+

+/**

+  * @brief  Processor uses deep sleep as its low power mode

+  * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPM_EnableDeepSleep(void)

+{

+  /* Set SLEEPDEEP bit of Cortex System Control Register */

+  SET_BIT(SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);

+}

+

+/**

+  * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.

+  * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an

+  *         empty main application.

+  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)

+{

+  /* Set SLEEPONEXIT bit of Cortex System Control Register */

+  SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);

+}

+

+/**

+  * @brief  Do not sleep when returning to Thread mode.

+  * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)

+{

+  /* Clear SLEEPONEXIT bit of Cortex System Control Register */

+  CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk);

+}

+

+/**

+  * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the

+  *         processor.

+  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPM_EnableEventOnPend(void)

+{

+  /* Set SEVEONPEND bit of Cortex System Control Register */

+  SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);

+}

+

+/**

+  * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are

+  *         excluded

+  * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPM_DisableEventOnPend(void)

+{

+  /* Clear SEVEONPEND bit of Cortex System Control Register */

+  CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup CORTEX_LL_EF_HANDLER HANDLER

+  * @{

+  */

+

+/**

+  * @brief  Enable a fault in System handler control register (SHCSR)

+  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_EnableFault

+  * @param  Fault This parameter can be a combination of the following values:

+  *         @arg @ref LL_HANDLER_FAULT_USG

+  *         @arg @ref LL_HANDLER_FAULT_BUS

+  *         @arg @ref LL_HANDLER_FAULT_MEM

+  * @retval None

+  */

+__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)

+{

+  /* Enable the system handler fault */

+  SET_BIT(SCB->SHCSR, Fault);

+}

+

+/**

+  * @brief  Disable a fault in System handler control register (SHCSR)

+  * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_DisableFault

+  * @param  Fault This parameter can be a combination of the following values:

+  *         @arg @ref LL_HANDLER_FAULT_USG

+  *         @arg @ref LL_HANDLER_FAULT_BUS

+  *         @arg @ref LL_HANDLER_FAULT_MEM

+  * @retval None

+  */

+__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)

+{

+  /* Disable the system handler fault */

+  CLEAR_BIT(SCB->SHCSR, Fault);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO

+  * @{

+  */

+

+/**

+  * @brief  Get Implementer code

+  * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer

+  * @retval Value should be equal to 0x41 for ARM

+  */

+__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)

+{

+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);

+}

+

+/**

+  * @brief  Get Variant number (The r value in the rnpn product revision identifier)

+  * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant

+  * @retval Value between 0 and 255 (0x0: revision 0)

+  */

+__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)

+{

+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);

+}

+

+/**

+  * @brief  Get Constant number

+  * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetConstant

+  * @retval Value should be equal to 0xF for Cortex-M7 and Cortex-M4 devices

+  */

+__STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)

+{

+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);

+}

+

+/**

+  * @brief  Get Part number

+  * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo

+  * @retval Value should be equal to 0xC27 for Cortex-M7 and equal to 0xC24 for Cortex-M4

+  */

+__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)

+{

+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);

+}

+

+/**

+  * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)

+  * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision

+  * @retval Value between 0 and 255 (0x1: patch 1)

+  */

+__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)

+{

+  return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);

+}

+

+/**

+  * @}

+  */

+

+#if __MPU_PRESENT

+/** @defgroup CORTEX_LL_EF_MPU MPU

+  * @{

+  */

+

+/**

+  * @brief  Enable MPU with input options

+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable

+  * @param  Options This parameter can be one of the following values:

+  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE

+  *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI

+  *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT

+  *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF

+  * @retval None

+  */

+__STATIC_INLINE void LL_MPU_Enable(uint32_t Options)

+{

+  /* Enable the MPU*/

+  WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));

+  /* Ensure MPU settings take effects */

+  __DSB();

+  /* Sequence instruction fetches using update settings */

+  __ISB();

+}

+

+/**

+  * @brief  Disable MPU

+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable

+  * @retval None

+  */

+__STATIC_INLINE void LL_MPU_Disable(void)

+{

+  /* Make sure outstanding transfers are done */

+  __DMB();

+  /* Disable MPU*/

+  WRITE_REG(MPU->CTRL, 0U);

+}

+

+/**

+  * @brief  Check if MPU is enabled or not

+  * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)

+{

+  return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable a MPU region

+  * @rmtoll MPU_RASR     ENABLE        LL_MPU_EnableRegion

+  * @param  Region This parameter can be one of the following values:

+  *         @arg @ref LL_MPU_REGION_NUMBER0

+  *         @arg @ref LL_MPU_REGION_NUMBER1

+  *         @arg @ref LL_MPU_REGION_NUMBER2

+  *         @arg @ref LL_MPU_REGION_NUMBER3

+  *         @arg @ref LL_MPU_REGION_NUMBER4

+  *         @arg @ref LL_MPU_REGION_NUMBER5

+  *         @arg @ref LL_MPU_REGION_NUMBER6

+  *         @arg @ref LL_MPU_REGION_NUMBER7

+  *         @arg @ref LL_MPU_REGION_NUMBER8

+  *         @arg @ref LL_MPU_REGION_NUMBER9

+  *         @arg @ref LL_MPU_REGION_NUMBER10

+  *         @arg @ref LL_MPU_REGION_NUMBER11

+  *         @arg @ref LL_MPU_REGION_NUMBER12

+  *         @arg @ref LL_MPU_REGION_NUMBER13

+  *         @arg @ref LL_MPU_REGION_NUMBER14

+  *         @arg @ref LL_MPU_REGION_NUMBER15

+  * @note   For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.

+  * @retval None

+  */

+__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)

+{

+  /* Set Region number */

+  WRITE_REG(MPU->RNR, Region);

+  /* Enable the MPU region */

+  SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);

+}

+

+/**

+  * @brief  Configure and enable a region

+  * @rmtoll MPU_RNR      REGION        LL_MPU_ConfigRegion\n

+  *         MPU_RBAR     REGION        LL_MPU_ConfigRegion\n

+  *         MPU_RBAR     ADDR          LL_MPU_ConfigRegion\n

+  *         MPU_RASR     XN            LL_MPU_ConfigRegion\n

+  *         MPU_RASR     AP            LL_MPU_ConfigRegion\n

+  *         MPU_RASR     S             LL_MPU_ConfigRegion\n

+  *         MPU_RASR     C             LL_MPU_ConfigRegion\n

+  *         MPU_RASR     B             LL_MPU_ConfigRegion\n

+  *         MPU_RASR     SIZE          LL_MPU_ConfigRegion

+  * @param  Region This parameter can be one of the following values:

+  *         @arg @ref LL_MPU_REGION_NUMBER0

+  *         @arg @ref LL_MPU_REGION_NUMBER1

+  *         @arg @ref LL_MPU_REGION_NUMBER2

+  *         @arg @ref LL_MPU_REGION_NUMBER3

+  *         @arg @ref LL_MPU_REGION_NUMBER4

+  *         @arg @ref LL_MPU_REGION_NUMBER5

+  *         @arg @ref LL_MPU_REGION_NUMBER6

+  *         @arg @ref LL_MPU_REGION_NUMBER7

+  *         @arg @ref LL_MPU_REGION_NUMBER8

+  *         @arg @ref LL_MPU_REGION_NUMBER9

+  *         @arg @ref LL_MPU_REGION_NUMBER10

+  *         @arg @ref LL_MPU_REGION_NUMBER11

+  *         @arg @ref LL_MPU_REGION_NUMBER12

+  *         @arg @ref LL_MPU_REGION_NUMBER13

+  *         @arg @ref LL_MPU_REGION_NUMBER14

+  *         @arg @ref LL_MPU_REGION_NUMBER15

+  * @param  Address Value of region base address

+  * @param  SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF

+  * @param  Attributes This parameter can be a combination of the following values:

+  *         @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B

+  *           or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB

+  *           or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB

+  *           or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB

+  *           or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB

+  *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB

+  *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS

+  *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO

+  *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4

+  *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE

+  *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE

+  *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE

+  *         @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE

+  * @note   For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.

+  * @retval None

+  */

+__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)

+{

+  /* Set Region number */

+  WRITE_REG(MPU->RNR, Region);

+  /* Set base address */

+  WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));

+  /* Configure MPU */

+  WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | (SubRegionDisable << MPU_RASR_SRD_Pos)));

+}

+

+/**

+  * @brief  Disable a region

+  * @rmtoll MPU_RNR      REGION        LL_MPU_DisableRegion\n

+  *         MPU_RASR     ENABLE        LL_MPU_DisableRegion

+  * @param  Region This parameter can be one of the following values:

+  *         @arg @ref LL_MPU_REGION_NUMBER0

+  *         @arg @ref LL_MPU_REGION_NUMBER1

+  *         @arg @ref LL_MPU_REGION_NUMBER2

+  *         @arg @ref LL_MPU_REGION_NUMBER3

+  *         @arg @ref LL_MPU_REGION_NUMBER4

+  *         @arg @ref LL_MPU_REGION_NUMBER5

+  *         @arg @ref LL_MPU_REGION_NUMBER6

+  *         @arg @ref LL_MPU_REGION_NUMBER7

+  *         @arg @ref LL_MPU_REGION_NUMBER8

+  *         @arg @ref LL_MPU_REGION_NUMBER9

+  *         @arg @ref LL_MPU_REGION_NUMBER10

+  *         @arg @ref LL_MPU_REGION_NUMBER11

+  *         @arg @ref LL_MPU_REGION_NUMBER12

+  *         @arg @ref LL_MPU_REGION_NUMBER13

+  *         @arg @ref LL_MPU_REGION_NUMBER14

+  *         @arg @ref LL_MPU_REGION_NUMBER15

+  * @note   For cortex-M4 only 8 regions are available i.e only values from LL_MPU_REGION_NUMBER0 to LL_MPU_REGION_NUMBER7 are possible.

+  * @retval None

+  */

+__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)

+{

+  /* Set Region number */

+  WRITE_REG(MPU->RNR, Region);

+  /* Disable the MPU region */

+  CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);

+}

+

+/**

+  * @}

+  */

+

+#endif /* __MPU_PRESENT */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_LL_CORTEX_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_crc.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_crc.h
new file mode 100644
index 0000000000..c7bf35a242
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_crc.h
@@ -0,0 +1,464 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_crc.h

+  * @author  MCD Application Team

+  * @brief   Header file of CRC LL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_LL_CRC_H

+#define STM32H7xx_LL_CRC_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+#if defined(CRC)

+

+/** @defgroup CRC_LL CRC

+  * @{

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/* Private macros ------------------------------------------------------------*/

+

+/* Exported types ------------------------------------------------------------*/

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants

+  * @{

+  */

+

+/** @defgroup CRC_LL_EC_POLYLENGTH Polynomial length

+  * @{

+  */

+#define LL_CRC_POLYLENGTH_32B              0x00000000U                              /*!< 32 bits Polynomial size */

+#define LL_CRC_POLYLENGTH_16B              CRC_CR_POLYSIZE_0                        /*!< 16 bits Polynomial size */

+#define LL_CRC_POLYLENGTH_8B               CRC_CR_POLYSIZE_1                        /*!< 8 bits Polynomial size */

+#define LL_CRC_POLYLENGTH_7B               (CRC_CR_POLYSIZE_1 | CRC_CR_POLYSIZE_0)  /*!< 7 bits Polynomial size */

+/**

+  * @}

+  */

+

+/** @defgroup CRC_LL_EC_INDATA_REVERSE Input Data Reverse

+  * @{

+  */

+#define LL_CRC_INDATA_REVERSE_NONE         0x00000000U                              /*!< Input Data bit order not affected */

+#define LL_CRC_INDATA_REVERSE_BYTE         CRC_CR_REV_IN_0                          /*!< Input Data bit reversal done by byte */

+#define LL_CRC_INDATA_REVERSE_HALFWORD     CRC_CR_REV_IN_1                          /*!< Input Data bit reversal done by half-word */

+#define LL_CRC_INDATA_REVERSE_WORD         (CRC_CR_REV_IN_1 | CRC_CR_REV_IN_0)      /*!< Input Data bit reversal done by word */

+/**

+  * @}

+  */

+

+/** @defgroup CRC_LL_EC_OUTDATA_REVERSE Output Data Reverse

+  * @{

+  */

+#define LL_CRC_OUTDATA_REVERSE_NONE        0x00000000U                               /*!< Output Data bit order not affected */

+#define LL_CRC_OUTDATA_REVERSE_BIT         CRC_CR_REV_OUT                            /*!< Output Data bit reversal done by bit */

+/**

+  * @}

+  */

+

+/** @defgroup CRC_LL_EC_Default_Polynomial_Value    Default CRC generating polynomial value

+  * @brief    Normal representation of this polynomial value is

+  *           X^32 + X^26 + X^23 + X^22 + X^16 + X^12 + X^11 + X^10 +X^8 + X^7 + X^5 + X^4 + X^2 + X + 1 .

+  * @{

+  */

+#define LL_CRC_DEFAULT_CRC32_POLY          0x04C11DB7U                               /*!< Default CRC generating polynomial value */

+/**

+  * @}

+  */

+

+/** @defgroup CRC_LL_EC_Default_InitValue    Default CRC computation initialization value

+  * @{

+  */

+#define LL_CRC_DEFAULT_CRC_INITVALUE       0xFFFFFFFFU                               /*!< Default CRC computation initialization value */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros

+  * @{

+  */

+

+/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros

+  * @{

+  */

+

+/**

+  * @brief  Write a value in CRC register

+  * @param  __INSTANCE__ CRC Instance

+  * @param  __REG__ Register to be written

+  * @param  __VALUE__ Value to be written in the register

+  * @retval None

+  */

+#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__)

+

+/**

+  * @brief  Read a value in CRC register

+  * @param  __INSTANCE__ CRC Instance

+  * @param  __REG__ Register to be read

+  * @retval Register value

+  */

+#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions

+  * @{

+  */

+

+/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions

+  * @{

+  */

+

+/**

+  * @brief  Reset the CRC calculation unit.

+  * @note   If Programmable Initial CRC value feature

+  *         is available, also set the Data Register to the value stored in the

+  *         CRC_INIT register, otherwise, reset Data Register to its default value.

+  * @rmtoll CR           RESET         LL_CRC_ResetCRCCalculationUnit

+  * @param  CRCx CRC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx)

+{

+  SET_BIT(CRCx->CR, CRC_CR_RESET);

+}

+

+/**

+  * @brief  Configure size of the polynomial.

+  * @rmtoll CR           POLYSIZE      LL_CRC_SetPolynomialSize

+  * @param  CRCx CRC Instance

+  * @param  PolySize This parameter can be one of the following values:

+  *         @arg @ref LL_CRC_POLYLENGTH_32B

+  *         @arg @ref LL_CRC_POLYLENGTH_16B

+  *         @arg @ref LL_CRC_POLYLENGTH_8B

+  *         @arg @ref LL_CRC_POLYLENGTH_7B

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySize)

+{

+  MODIFY_REG(CRCx->CR, CRC_CR_POLYSIZE, PolySize);

+}

+

+/**

+  * @brief  Return size of the polynomial.

+  * @rmtoll CR           POLYSIZE      LL_CRC_GetPolynomialSize

+  * @param  CRCx CRC Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_CRC_POLYLENGTH_32B

+  *         @arg @ref LL_CRC_POLYLENGTH_16B

+  *         @arg @ref LL_CRC_POLYLENGTH_8B

+  *         @arg @ref LL_CRC_POLYLENGTH_7B

+  */

+__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx)

+{

+  return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE));

+}

+

+/**

+  * @brief  Configure the reversal of the bit order of the input data

+  * @rmtoll CR           REV_IN        LL_CRC_SetInputDataReverseMode

+  * @param  CRCx CRC Instance

+  * @param  ReverseMode This parameter can be one of the following values:

+  *         @arg @ref LL_CRC_INDATA_REVERSE_NONE

+  *         @arg @ref LL_CRC_INDATA_REVERSE_BYTE

+  *         @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD

+  *         @arg @ref LL_CRC_INDATA_REVERSE_WORD

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)

+{

+  MODIFY_REG(CRCx->CR, CRC_CR_REV_IN, ReverseMode);

+}

+

+/**

+  * @brief  Return type of reversal for input data bit order

+  * @rmtoll CR           REV_IN        LL_CRC_GetInputDataReverseMode

+  * @param  CRCx CRC Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_CRC_INDATA_REVERSE_NONE

+  *         @arg @ref LL_CRC_INDATA_REVERSE_BYTE

+  *         @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD

+  *         @arg @ref LL_CRC_INDATA_REVERSE_WORD

+  */

+__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx)

+{

+  return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN));

+}

+

+/**

+  * @brief  Configure the reversal of the bit order of the Output data

+  * @rmtoll CR           REV_OUT       LL_CRC_SetOutputDataReverseMode

+  * @param  CRCx CRC Instance

+  * @param  ReverseMode This parameter can be one of the following values:

+  *         @arg @ref LL_CRC_OUTDATA_REVERSE_NONE

+  *         @arg @ref LL_CRC_OUTDATA_REVERSE_BIT

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t ReverseMode)

+{

+  MODIFY_REG(CRCx->CR, CRC_CR_REV_OUT, ReverseMode);

+}

+

+/**

+  * @brief  Configure the reversal of the bit order of the Output data

+  * @rmtoll CR           REV_OUT       LL_CRC_GetOutputDataReverseMode

+  * @param  CRCx CRC Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_CRC_OUTDATA_REVERSE_NONE

+  *         @arg @ref LL_CRC_OUTDATA_REVERSE_BIT

+  */

+__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx)

+{

+  return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT));

+}

+

+/**

+  * @brief  Initialize the Programmable initial CRC value.

+  * @note   If the CRC size is less than 32 bits, the least significant bits

+  *         are used to write the correct value

+  * @note   LL_CRC_DEFAULT_CRC_INITVALUE could be used as value for InitCrc parameter.

+  * @rmtoll INIT         INIT          LL_CRC_SetInitialData

+  * @param  CRCx CRC Instance

+  * @param  InitCrc Value to be programmed in Programmable initial CRC value register

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc)

+{

+  WRITE_REG(CRCx->INIT, InitCrc);

+}

+

+/**

+  * @brief  Return current Initial CRC value.

+  * @note   If the CRC size is less than 32 bits, the least significant bits

+  *         are used to read the correct value

+  * @rmtoll INIT         INIT          LL_CRC_GetInitialData

+  * @param  CRCx CRC Instance

+  * @retval Value programmed in Programmable initial CRC value register

+  */

+__STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx)

+{

+  return (uint32_t)(READ_REG(CRCx->INIT));

+}

+

+/**

+  * @brief  Initialize the Programmable polynomial value

+  *         (coefficients of the polynomial to be used for CRC calculation).

+  * @note   LL_CRC_DEFAULT_CRC32_POLY could be used as value for PolynomCoef parameter.

+  * @note   Please check Reference Manual and existing Errata Sheets,

+  *         regarding possible limitations for Polynomial values usage.

+  *         For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65

+  * @rmtoll POL          POL           LL_CRC_SetPolynomialCoef

+  * @param  CRCx CRC Instance

+  * @param  PolynomCoef Value to be programmed in Programmable Polynomial value register

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t PolynomCoef)

+{

+  WRITE_REG(CRCx->POL, PolynomCoef);

+}

+

+/**

+  * @brief  Return current Programmable polynomial value

+  * @note   Please check Reference Manual and existing Errata Sheets,

+  *         regarding possible limitations for Polynomial values usage.

+  *         For example, for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65

+  * @rmtoll POL          POL           LL_CRC_GetPolynomialCoef

+  * @param  CRCx CRC Instance

+  * @retval Value programmed in Programmable Polynomial value register

+  */

+__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx)

+{

+  return (uint32_t)(READ_REG(CRCx->POL));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup CRC_LL_EF_Data_Management Data_Management

+  * @{

+  */

+

+/**

+  * @brief  Write given 32-bit data to the CRC calculator

+  * @rmtoll DR           DR            LL_CRC_FeedData32

+  * @param  CRCx CRC Instance

+  * @param  InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData)

+{

+  WRITE_REG(CRCx->DR, InData);

+}

+

+/**

+  * @brief  Write given 16-bit data to the CRC calculator

+  * @rmtoll DR           DR            LL_CRC_FeedData16

+  * @param  CRCx CRC Instance

+  * @param  InData 16 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRC_FeedData16(CRC_TypeDef *CRCx, uint16_t InData)

+{

+  __IO uint16_t *pReg;

+

+  pReg = (__IO uint16_t *)(__IO void *)(&CRCx->DR);                             /* Derogation MisraC2012 R.11.5 */

+  *pReg = InData;

+}

+

+/**

+  * @brief  Write given 8-bit data to the CRC calculator

+  * @rmtoll DR           DR            LL_CRC_FeedData8

+  * @param  CRCx CRC Instance

+  * @param  InData 8 bit value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData)

+{

+  *(uint8_t __IO *)(&CRCx->DR) = (uint8_t) InData;

+}

+

+/**

+  * @brief  Return current CRC calculation result. 32 bits value is returned.

+  * @rmtoll DR           DR            LL_CRC_ReadData32

+  * @param  CRCx CRC Instance

+  * @retval Current CRC calculation result as stored in CRC_DR register (32 bits).

+  */

+__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx)

+{

+  return (uint32_t)(READ_REG(CRCx->DR));

+}

+

+/**

+  * @brief  Return current CRC calculation result. 16 bits value is returned.

+  * @note   This function is expected to be used in a 16 bits CRC polynomial size context.

+  * @rmtoll DR           DR            LL_CRC_ReadData16

+  * @param  CRCx CRC Instance

+  * @retval Current CRC calculation result as stored in CRC_DR register (16 bits).

+  */

+__STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx)

+{

+  return (uint16_t)READ_REG(CRCx->DR);

+}

+

+/**

+  * @brief  Return current CRC calculation result. 8 bits value is returned.

+  * @note   This function is expected to be used in a 8 bits CRC polynomial size context.

+  * @rmtoll DR           DR            LL_CRC_ReadData8

+  * @param  CRCx CRC Instance

+  * @retval Current CRC calculation result as stored in CRC_DR register (8 bits).

+  */

+__STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx)

+{

+  return (uint8_t)READ_REG(CRCx->DR);

+}

+

+/**

+  * @brief  Return current CRC calculation result. 7 bits value is returned.

+  * @note   This function is expected to be used in a 7 bits CRC polynomial size context.

+  * @rmtoll DR           DR            LL_CRC_ReadData7

+  * @param  CRCx CRC Instance

+  * @retval Current CRC calculation result as stored in CRC_DR register (7 bits).

+  */

+__STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx)

+{

+  return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU);

+}

+

+/**

+  * @brief  Return data stored in the Independent Data(IDR) register.

+  * @note   This register can be used as a temporary storage location for one 32-bit long data.

+  * @rmtoll IDR          IDR           LL_CRC_Read_IDR

+  * @param  CRCx CRC Instance

+  * @retval Value stored in CRC_IDR register (General-purpose 32-bit data register).

+  */

+__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx)

+{

+  return (uint32_t)(READ_REG(CRCx->IDR));

+}

+

+/**

+  * @brief  Store data in the Independent Data(IDR) register.

+  * @note   This register can be used as a temporary storage location for one 32-bit long data.

+  * @rmtoll IDR          IDR           LL_CRC_Write_IDR

+  * @param  CRCx CRC Instance

+  * @param  InData value to be stored in CRC_IDR register (32-bit) between Min_Data=0 and Max_Data=0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData)

+{

+  *((uint32_t __IO *)(&CRCx->IDR)) = (uint32_t) InData;

+}

+/**

+  * @}

+  */

+

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions

+  * @{

+  */

+

+ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx);

+

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* defined(CRC) */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_LL_CRC_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_crs.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_crs.h
new file mode 100644
index 0000000000..40baadd1ad
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_crs.h
@@ -0,0 +1,783 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_crs.h

+  * @author  MCD Application Team

+  * @brief   Header file of CRS LL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_LL_CRS_H

+#define STM32H7xx_LL_CRS_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+#if defined(CRS)

+

+/** @defgroup CRS_LL CRS

+  * @{

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/* Private macros ------------------------------------------------------------*/

+

+/* Exported types ------------------------------------------------------------*/

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants

+  * @{

+  */

+

+/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines

+  * @brief    Flags defines which can be used with LL_CRS_ReadReg function

+  * @{

+  */

+#define LL_CRS_ISR_SYNCOKF                 CRS_ISR_SYNCOKF

+#define LL_CRS_ISR_SYNCWARNF               CRS_ISR_SYNCWARNF

+#define LL_CRS_ISR_ERRF                    CRS_ISR_ERRF

+#define LL_CRS_ISR_ESYNCF                  CRS_ISR_ESYNCF

+#define LL_CRS_ISR_SYNCERR                 CRS_ISR_SYNCERR

+#define LL_CRS_ISR_SYNCMISS                CRS_ISR_SYNCMISS

+#define LL_CRS_ISR_TRIMOVF                 CRS_ISR_TRIMOVF

+/**

+  * @}

+  */

+

+/** @defgroup CRS_LL_EC_IT IT Defines

+  * @brief    IT defines which can be used with LL_CRS_ReadReg and  LL_CRS_WriteReg functions

+  * @{

+  */

+#define LL_CRS_CR_SYNCOKIE                 CRS_CR_SYNCOKIE

+#define LL_CRS_CR_SYNCWARNIE               CRS_CR_SYNCWARNIE

+#define LL_CRS_CR_ERRIE                    CRS_CR_ERRIE

+#define LL_CRS_CR_ESYNCIE                  CRS_CR_ESYNCIE

+/**

+  * @}

+  */

+

+/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider

+  * @{

+  */

+#define LL_CRS_SYNC_DIV_1                  0x00000000U                               /*!< Synchro Signal not divided (default) */

+#define LL_CRS_SYNC_DIV_2                  CRS_CFGR_SYNCDIV_0                        /*!< Synchro Signal divided by 2 */

+#define LL_CRS_SYNC_DIV_4                  CRS_CFGR_SYNCDIV_1                        /*!< Synchro Signal divided by 4 */

+#define LL_CRS_SYNC_DIV_8                  (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */

+#define LL_CRS_SYNC_DIV_16                 CRS_CFGR_SYNCDIV_2                        /*!< Synchro Signal divided by 16 */

+#define LL_CRS_SYNC_DIV_32                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */

+#define LL_CRS_SYNC_DIV_64                 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */

+#define LL_CRS_SYNC_DIV_128                CRS_CFGR_SYNCDIV                          /*!< Synchro Signal divided by 128 */

+/**

+  * @}

+  */

+

+/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source

+  * @{

+  */

+#define LL_CRS_SYNC_SOURCE_GPIO            0x00000000U             /*!< Synchro Signal soucre GPIO */

+#define LL_CRS_SYNC_SOURCE_LSE             CRS_CFGR_SYNCSRC_0      /*!< Synchro Signal source LSE */

+#define LL_CRS_SYNC_SOURCE_USB             CRS_CFGR_SYNCSRC_1      /*!< Synchro Signal source USB SOF (default)*/

+/**

+  * @}

+  */

+

+/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity

+  * @{

+  */

+#define LL_CRS_SYNC_POLARITY_RISING        0x00000000U           /*!< Synchro Active on rising edge (default) */

+#define LL_CRS_SYNC_POLARITY_FALLING       CRS_CFGR_SYNCPOL      /*!< Synchro Active on falling edge */

+/**

+  * @}

+  */

+

+/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction

+  * @{

+  */

+#define LL_CRS_FREQ_ERROR_DIR_UP           0x00000000U         /*!< Upcounting direction, the actual frequency is above the target */

+#define LL_CRS_FREQ_ERROR_DIR_DOWN         CRS_ISR_FEDIR       /*!< Downcounting direction, the actual frequency is below the target */

+/**

+  * @}

+  */

+

+/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values

+  * @{

+  */

+/**

+  * @brief Reset value of the RELOAD field

+  * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz

+  *       and a synchronization signal frequency of 1 kHz (SOF signal from USB)

+  */

+#define LL_CRS_RELOADVALUE_DEFAULT         0x0000BB7FU

+

+/**

+  * @brief Reset value of Frequency error limit.

+  */

+#define LL_CRS_ERRORLIMIT_DEFAULT          0x00000022U

+

+/**

+  * @brief Reset value of the HSI48 Calibration field

+  * @note The default value is 64, which corresponds to the middle of the trimming interval.

+  *       The trimming step is specified in the product datasheet.

+  *       A higher TRIM value corresponds to a higher output frequency.

+  */

+#define LL_CRS_HSI48CALIBRATION_DEFAULT    0x00000020U

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros

+  * @{

+  */

+

+/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros

+  * @{

+  */

+

+/**

+  * @brief  Write a value in CRS register

+  * @param  __INSTANCE__ CRS Instance

+  * @param  __REG__ Register to be written

+  * @param  __VALUE__ Value to be written in the register

+  * @retval None

+  */

+#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

+

+/**

+  * @brief  Read a value in CRS register

+  * @param  __INSTANCE__ CRS Instance

+  * @param  __REG__ Register to be read

+  * @retval Register value

+  */

+#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)

+/**

+  * @}

+  */

+

+/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload

+  * @{

+  */

+

+/**

+  * @brief  Macro to calculate reload value to be set in CRS register according to target and sync frequencies

+  * @note   The RELOAD value should be selected according to the ratio between

+  *         the target frequency and the frequency of the synchronization source after

+  *         prescaling. It is then decreased by one in order to reach the expected

+  *         synchronization on the zero value. The formula is the following:

+  *              RELOAD = (fTARGET / fSYNC) -1

+  * @param  __FTARGET__ Target frequency (value in Hz)

+  * @param  __FSYNC__ Synchronization signal frequency (value in Hz)

+  * @retval Reload value (in Hz)

+  */

+#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U)

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions

+  * @{

+  */

+

+/** @defgroup CRS_LL_EF_Configuration Configuration

+  * @{

+  */

+

+/**

+  * @brief  Enable Frequency error counter

+  * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified

+  * @rmtoll CR           CEN           LL_CRS_EnableFreqErrorCounter

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void)

+{

+  SET_BIT(CRS->CR, CRS_CR_CEN);

+}

+

+/**

+  * @brief  Disable Frequency error counter

+  * @rmtoll CR           CEN           LL_CRS_DisableFreqErrorCounter

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void)

+{

+  CLEAR_BIT(CRS->CR, CRS_CR_CEN);

+}

+

+/**

+  * @brief  Check if Frequency error counter is enabled or not

+  * @rmtoll CR           CEN           LL_CRS_IsEnabledFreqErrorCounter

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void)

+{

+  return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable Automatic trimming counter

+  * @rmtoll CR           AUTOTRIMEN    LL_CRS_EnableAutoTrimming

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void)

+{

+  SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);

+}

+

+/**

+  * @brief  Disable Automatic trimming counter

+  * @rmtoll CR           AUTOTRIMEN    LL_CRS_DisableAutoTrimming

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void)

+{

+  CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN);

+}

+

+/**

+  * @brief  Check if Automatic trimming is enabled or not

+  * @rmtoll CR           AUTOTRIMEN    LL_CRS_IsEnabledAutoTrimming

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void)

+{

+  return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set HSI48 oscillator smooth trimming

+  * @note   When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only

+  * @rmtoll CR           TRIM          LL_CRS_SetHSI48SmoothTrimming

+  * @param  Value a number between Min_Data = 0 and Max_Data = 127

+  * @note   Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value)

+{

+  MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos);

+}

+

+/**

+  * @brief  Get HSI48 oscillator smooth trimming

+  * @rmtoll CR           TRIM          LL_CRS_GetHSI48SmoothTrimming

+  * @retval a number between Min_Data = 0 and Max_Data = 127

+  */

+__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void)

+{

+  return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos);

+}

+

+/**

+  * @brief  Set counter reload value

+  * @rmtoll CFGR         RELOAD        LL_CRS_SetReloadCounter

+  * @param  Value a number between Min_Data = 0 and Max_Data = 0xFFFF

+  * @note   Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT

+  *         Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_)

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value)

+{

+  MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value);

+}

+

+/**

+  * @brief  Get counter reload value

+  * @rmtoll CFGR         RELOAD        LL_CRS_GetReloadCounter

+  * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF

+  */

+__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void)

+{

+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD));

+}

+

+/**

+  * @brief  Set frequency error limit

+  * @rmtoll CFGR         FELIM         LL_CRS_SetFreqErrorLimit

+  * @param  Value a number between Min_Data = 0 and Max_Data = 255

+  * @note   Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value)

+{

+  MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos);

+}

+

+/**

+  * @brief  Get frequency error limit

+  * @rmtoll CFGR         FELIM         LL_CRS_GetFreqErrorLimit

+  * @retval A number between Min_Data = 0 and Max_Data = 255

+  */

+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void)

+{

+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos);

+}

+

+/**

+  * @brief  Set division factor for SYNC signal

+  * @rmtoll CFGR         SYNCDIV       LL_CRS_SetSyncDivider

+  * @param  Divider This parameter can be one of the following values:

+  *         @arg @ref LL_CRS_SYNC_DIV_1

+  *         @arg @ref LL_CRS_SYNC_DIV_2

+  *         @arg @ref LL_CRS_SYNC_DIV_4

+  *         @arg @ref LL_CRS_SYNC_DIV_8

+  *         @arg @ref LL_CRS_SYNC_DIV_16

+  *         @arg @ref LL_CRS_SYNC_DIV_32

+  *         @arg @ref LL_CRS_SYNC_DIV_64

+  *         @arg @ref LL_CRS_SYNC_DIV_128

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider)

+{

+  MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider);

+}

+

+/**

+  * @brief  Get division factor for SYNC signal

+  * @rmtoll CFGR         SYNCDIV       LL_CRS_GetSyncDivider

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_CRS_SYNC_DIV_1

+  *         @arg @ref LL_CRS_SYNC_DIV_2

+  *         @arg @ref LL_CRS_SYNC_DIV_4

+  *         @arg @ref LL_CRS_SYNC_DIV_8

+  *         @arg @ref LL_CRS_SYNC_DIV_16

+  *         @arg @ref LL_CRS_SYNC_DIV_32

+  *         @arg @ref LL_CRS_SYNC_DIV_64

+  *         @arg @ref LL_CRS_SYNC_DIV_128

+  */

+__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void)

+{

+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV));

+}

+

+/**

+  * @brief  Set SYNC signal source

+  * @rmtoll CFGR         SYNCSRC       LL_CRS_SetSyncSignalSource

+  * @param  Source This parameter can be one of the following values:

+  *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO

+  *         @arg @ref LL_CRS_SYNC_SOURCE_LSE

+  *         @arg @ref LL_CRS_SYNC_SOURCE_USB

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source)

+{

+  MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source);

+}

+

+/**

+  * @brief  Get SYNC signal source

+  * @rmtoll CFGR         SYNCSRC       LL_CRS_GetSyncSignalSource

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO

+  *         @arg @ref LL_CRS_SYNC_SOURCE_LSE

+  *         @arg @ref LL_CRS_SYNC_SOURCE_USB

+  */

+__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void)

+{

+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC));

+}

+

+/**

+  * @brief  Set input polarity for the SYNC signal source

+  * @rmtoll CFGR         SYNCPOL       LL_CRS_SetSyncPolarity

+  * @param  Polarity This parameter can be one of the following values:

+  *         @arg @ref LL_CRS_SYNC_POLARITY_RISING

+  *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity)

+{

+  MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity);

+}

+

+/**

+  * @brief  Get input polarity for the SYNC signal source

+  * @rmtoll CFGR         SYNCPOL       LL_CRS_GetSyncPolarity

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_CRS_SYNC_POLARITY_RISING

+  *         @arg @ref LL_CRS_SYNC_POLARITY_FALLING

+  */

+__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void)

+{

+  return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL));

+}

+

+/**

+  * @brief  Configure CRS for the synchronization

+  * @rmtoll CR           TRIM          LL_CRS_ConfigSynchronization\n

+  *         CFGR         RELOAD        LL_CRS_ConfigSynchronization\n

+  *         CFGR         FELIM         LL_CRS_ConfigSynchronization\n

+  *         CFGR         SYNCDIV       LL_CRS_ConfigSynchronization\n

+  *         CFGR         SYNCSRC       LL_CRS_ConfigSynchronization\n

+  *         CFGR         SYNCPOL       LL_CRS_ConfigSynchronization

+  * @param  HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63

+  * @param  ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF

+  * @param  ReloadValue a number between Min_Data = 0 and Max_Data = 255

+  * @param  Settings This parameter can be a combination of the following values:

+  *         @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8

+  *              or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128

+  *         @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB

+  *         @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings)

+{

+  MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue);

+  MODIFY_REG(CRS->CFGR,

+             CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL,

+             ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup CRS_LL_EF_CRS_Management CRS_Management

+  * @{

+  */

+

+/**

+  * @brief  Generate software SYNC event

+  * @rmtoll CR           SWSYNC        LL_CRS_GenerateEvent_SWSYNC

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void)

+{

+  SET_BIT(CRS->CR, CRS_CR_SWSYNC);

+}

+

+/**

+  * @brief  Get the frequency error direction latched in the time of the last

+  * SYNC event

+  * @rmtoll ISR          FEDIR         LL_CRS_GetFreqErrorDirection

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_CRS_FREQ_ERROR_DIR_UP

+  *         @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN

+  */

+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void)

+{

+  return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR));

+}

+

+/**

+  * @brief  Get the frequency error counter value latched in the time of the last SYNC event

+  * @rmtoll ISR          FECAP         LL_CRS_GetFreqErrorCapture

+  * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF

+  */

+__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void)

+{

+  return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management

+  * @{

+  */

+

+/**

+  * @brief  Check if SYNC event OK signal occurred or not

+  * @rmtoll ISR          SYNCOKF       LL_CRS_IsActiveFlag_SYNCOK

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void)

+{

+  return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if SYNC warning signal occurred or not

+  * @rmtoll ISR          SYNCWARNF     LL_CRS_IsActiveFlag_SYNCWARN

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void)

+{

+  return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if Synchronization or trimming error signal occurred or not

+  * @rmtoll ISR          ERRF          LL_CRS_IsActiveFlag_ERR

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void)

+{

+  return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if Expected SYNC signal occurred or not

+  * @rmtoll ISR          ESYNCF        LL_CRS_IsActiveFlag_ESYNC

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void)

+{

+  return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if SYNC error signal occurred or not

+  * @rmtoll ISR          SYNCERR       LL_CRS_IsActiveFlag_SYNCERR

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void)

+{

+  return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if SYNC missed error signal occurred or not

+  * @rmtoll ISR          SYNCMISS      LL_CRS_IsActiveFlag_SYNCMISS

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void)

+{

+  return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if Trimming overflow or underflow occurred or not

+  * @rmtoll ISR          TRIMOVF       LL_CRS_IsActiveFlag_TRIMOVF

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void)

+{

+  return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the SYNC event OK flag

+  * @rmtoll ICR          SYNCOKC       LL_CRS_ClearFlag_SYNCOK

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void)

+{

+  WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC);

+}

+

+/**

+  * @brief  Clear the  SYNC warning flag

+  * @rmtoll ICR          SYNCWARNC     LL_CRS_ClearFlag_SYNCWARN

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void)

+{

+  WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC);

+}

+

+/**

+  * @brief  Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also

+  * the ERR flag

+  * @rmtoll ICR          ERRC          LL_CRS_ClearFlag_ERR

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void)

+{

+  WRITE_REG(CRS->ICR, CRS_ICR_ERRC);

+}

+

+/**

+  * @brief  Clear Expected SYNC flag

+  * @rmtoll ICR          ESYNCC        LL_CRS_ClearFlag_ESYNC

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void)

+{

+  WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup CRS_LL_EF_IT_Management IT_Management

+  * @{

+  */

+

+/**

+  * @brief  Enable SYNC event OK interrupt

+  * @rmtoll CR           SYNCOKIE      LL_CRS_EnableIT_SYNCOK

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void)

+{

+  SET_BIT(CRS->CR, CRS_CR_SYNCOKIE);

+}

+

+/**

+  * @brief  Disable SYNC event OK interrupt

+  * @rmtoll CR           SYNCOKIE      LL_CRS_DisableIT_SYNCOK

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void)

+{

+  CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE);

+}

+

+/**

+  * @brief  Check if SYNC event OK interrupt is enabled or not

+  * @rmtoll CR           SYNCOKIE      LL_CRS_IsEnabledIT_SYNCOK

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void)

+{

+  return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable SYNC warning interrupt

+  * @rmtoll CR           SYNCWARNIE    LL_CRS_EnableIT_SYNCWARN

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void)

+{

+  SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE);

+}

+

+/**

+  * @brief  Disable SYNC warning interrupt

+  * @rmtoll CR           SYNCWARNIE    LL_CRS_DisableIT_SYNCWARN

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void)

+{

+  CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE);

+}

+

+/**

+  * @brief  Check if SYNC warning interrupt is enabled or not

+  * @rmtoll CR           SYNCWARNIE    LL_CRS_IsEnabledIT_SYNCWARN

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void)

+{

+  return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable Synchronization or trimming error interrupt

+  * @rmtoll CR           ERRIE         LL_CRS_EnableIT_ERR

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRS_EnableIT_ERR(void)

+{

+  SET_BIT(CRS->CR, CRS_CR_ERRIE);

+}

+

+/**

+  * @brief  Disable Synchronization or trimming error interrupt

+  * @rmtoll CR           ERRIE         LL_CRS_DisableIT_ERR

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRS_DisableIT_ERR(void)

+{

+  CLEAR_BIT(CRS->CR, CRS_CR_ERRIE);

+}

+

+/**

+  * @brief  Check if Synchronization or trimming error interrupt is enabled or not

+  * @rmtoll CR           ERRIE         LL_CRS_IsEnabledIT_ERR

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void)

+{

+  return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable Expected SYNC interrupt

+  * @rmtoll CR           ESYNCIE       LL_CRS_EnableIT_ESYNC

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void)

+{

+  SET_BIT(CRS->CR, CRS_CR_ESYNCIE);

+}

+

+/**

+  * @brief  Disable Expected SYNC interrupt

+  * @rmtoll CR           ESYNCIE       LL_CRS_DisableIT_ESYNC

+  * @retval None

+  */

+__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void)

+{

+  CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE);

+}

+

+/**

+  * @brief  Check if Expected SYNC interrupt is enabled or not

+  * @rmtoll CR           ESYNCIE       LL_CRS_IsEnabledIT_ESYNC

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void)

+{

+  return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions

+  * @{

+  */

+

+ErrorStatus LL_CRS_DeInit(void);

+

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* defined(CRS) */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_LL_CRS_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_dac.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_dac.h
new file mode 100644
index 0000000000..a550c0a8e3
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_dac.h
@@ -0,0 +1,1839 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_dac.h

+  * @author  MCD Application Team

+  * @brief   Header file of DAC LL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_LL_DAC_H

+#define STM32H7xx_LL_DAC_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+#if defined(DAC1) || defined(DAC2)

+

+/** @defgroup DAC_LL DAC

+  * @{

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup DAC_LL_Private_Constants DAC Private Constants

+  * @{

+  */

+

+/* Internal masks for DAC channels definition */

+/* To select into literal LL_DAC_CHANNEL_x the relevant bits for:             */

+/* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR            */

+/* - channel bits position into register SWTRIG                               */

+/* - channel register offset of data holding register DHRx                    */

+/* - channel register offset of data output register DORx                     */

+/* - channel register offset of sample-and-hold sample time register SHSRx    */

+#define DAC_CR_CH1_BITOFFSET           0UL   /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */

+#define DAC_CR_CH2_BITOFFSET           16UL  /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */

+#define DAC_CR_CHX_BITOFFSET_MASK      (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET)

+

+#define DAC_SWTR_CH1                   (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. */

+#define DAC_SWTR_CH2                   (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. */

+#define DAC_SWTR_CHX_MASK              (DAC_SWTR_CH1 | DAC_SWTR_CH2)

+

+#define DAC_REG_DHR12R1_REGOFFSET      0x00000000UL            /* Register DHR12Rx channel 1 taken as reference */

+#define DAC_REG_DHR12L1_REGOFFSET      0x00100000UL            /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */

+#define DAC_REG_DHR8R1_REGOFFSET       0x02000000UL            /* Register offset of DHR8Rx  channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */

+#define DAC_REG_DHR12R2_REGOFFSET      0x30000000UL            /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */

+#define DAC_REG_DHR12L2_REGOFFSET      0x00400000UL            /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */

+#define DAC_REG_DHR8R2_REGOFFSET       0x05000000UL            /* Register offset of DHR8Rx  channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */

+#define DAC_REG_DHR12RX_REGOFFSET_MASK 0xF0000000UL

+#define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000UL

+#define DAC_REG_DHR8RX_REGOFFSET_MASK  0x0F000000UL

+#define DAC_REG_DHRX_REGOFFSET_MASK    (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK)

+

+#define DAC_REG_DOR1_REGOFFSET         0x00000000UL            /* Register DORx channel 1 taken as reference */

+#define DAC_REG_DOR2_REGOFFSET         0x00000020UL            /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 5 bits) */

+#define DAC_REG_DORX_REGOFFSET_MASK    (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET)

+#define DAC_REG_SHSR1_REGOFFSET        0x00000000UL            /* Register SHSRx channel 1 taken as reference */

+#define DAC_REG_SHSR2_REGOFFSET        0x00000040UL            /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 6 bits) */

+#define DAC_REG_SHSRX_REGOFFSET_MASK   (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET)

+

+

+#define DAC_REG_DHR_REGOFFSET_MASK_POSBIT0         0x0000000FUL /* Mask of data hold registers offset (DHR12Rx, DHR12Lx, DHR8Rx, ...) when shifted to position 0 */

+#define DAC_REG_DORX_REGOFFSET_MASK_POSBIT0        0x00000001UL /* Mask of DORx registers offset when shifted to position 0 */

+#define DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0       0x00000001UL /* Mask of SHSRx registers offset when shifted to position 0 */

+

+#define DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS           28UL  /* Position of bits register offset of DHR12Rx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 28 bits) */

+#define DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS           20UL  /* Position of bits register offset of DHR12Lx channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */

+#define DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS            24UL  /* Position of bits register offset of DHR8Rx  channel 1 or 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */

+#define DAC_REG_DORX_REGOFFSET_BITOFFSET_POS               5UL  /* Position of bits register offset of DORx channel 1 or 2 versus DORx channel 1 (shifted left of 5 bits) */

+#define DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS              6UL  /* Position of bits register offset of SHSRx channel 1 or 2 versus SHSRx channel 1 (shifted left of 6 bits) */

+

+/* DAC registers bits positions */

+#define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS                DAC_DHR12RD_DACC2DHR_Pos

+#define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS                DAC_DHR12LD_DACC2DHR_Pos

+#define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS                 DAC_DHR8RD_DACC2DHR_Pos

+

+/* Miscellaneous data */

+#define DAC_DIGITAL_SCALE_12BITS                        4095UL /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */

+

+/**

+  * @}

+  */

+

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup DAC_LL_Private_Macros DAC Private Macros

+  * @{

+  */

+

+/**

+  * @brief  Driver macro reserved for internal use: set a pointer to

+  *         a register from a register basis from which an offset

+  *         is applied.

+  * @param  __REG__ Register basis from which the offset is applied.

+  * @param  __REG_OFFFSET__ Offset to be applied (unit: number of registers).

+  * @retval Pointer to register address

+*/

+#define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__)                         \

+  ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL))))

+

+/**

+  * @}

+  */

+

+

+/* Exported types ------------------------------------------------------------*/

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup DAC_LL_ES_INIT DAC Exported Init structure

+  * @{

+  */

+

+/**

+  * @brief  Structure definition of some features of DAC instance.

+  */

+typedef struct

+{

+  uint32_t TriggerSource;               /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external peripheral (timer event, external interrupt line).

+                                             This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE

+

+                                             This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */

+

+  uint32_t WaveAutoGeneration;          /*!< Set the waveform automatic generation mode for the selected DAC channel.

+                                             This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE

+

+                                             This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */

+

+  uint32_t WaveAutoGenerationConfig;    /*!< Set the waveform automatic generation mode for the selected DAC channel.

+                                             If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS

+                                             If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE

+                                             @note If waveform automatic generation mode is disabled, this parameter is discarded.

+

+                                             This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR(), @ref LL_DAC_SetWaveTriangleAmplitude()

+                                             depending on the wave automatic generation selected. */

+

+  uint32_t OutputBuffer;                /*!< Set the output buffer for the selected DAC channel.

+                                             This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER

+

+                                             This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */

+

+  uint32_t OutputConnection;            /*!< Set the output connection for the selected DAC channel.

+                                             This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION

+

+                                             This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputConnection(). */

+

+  uint32_t OutputMode;                  /*!< Set the output mode normal or sample-and-hold for the selected DAC channel.

+                                             This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE

+

+                                             This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputMode(). */

+} LL_DAC_InitTypeDef;

+

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup DAC_LL_Exported_Constants DAC Exported Constants

+  * @{

+  */

+

+/** @defgroup DAC_LL_EC_GET_FLAG DAC flags

+  * @brief    Flags defines which can be used with LL_DAC_ReadReg function

+  * @{

+  */

+/* DAC channel 1 flags */

+#define LL_DAC_FLAG_DMAUDR1                (DAC_SR_DMAUDR1)   /*!< DAC channel 1 flag DMA underrun */

+#define LL_DAC_FLAG_CAL1                   (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */

+#define LL_DAC_FLAG_BWST1                  (DAC_SR_BWST1)     /*!< DAC channel 1 flag busy writing sample time */

+

+/* DAC channel 2 flags */

+#define LL_DAC_FLAG_DMAUDR2                (DAC_SR_DMAUDR2)   /*!< DAC channel 2 flag DMA underrun */

+#define LL_DAC_FLAG_CAL2                   (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */

+#define LL_DAC_FLAG_BWST2                  (DAC_SR_BWST2)     /*!< DAC channel 2 flag busy writing sample time */

+/**

+  * @}

+  */

+

+/** @defgroup DAC_LL_EC_IT DAC interruptions

+  * @brief    IT defines which can be used with LL_DAC_ReadReg and  LL_DAC_WriteReg functions

+  * @{

+  */

+#define LL_DAC_IT_DMAUDRIE1                (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */

+#define LL_DAC_IT_DMAUDRIE2                (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */

+/**

+  * @}

+  */

+

+/** @defgroup DAC_LL_EC_CHANNEL DAC channels

+  * @{

+  */

+#define LL_DAC_CHANNEL_1                   (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */

+#define LL_DAC_CHANNEL_2                   (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */

+/**

+  * @}

+  */

+

+/** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode

+  * @{

+  */

+#define LL_DAC_MODE_NORMAL_OPERATION       0x00000000UL            /*!< DAC channel in mode normal operation */

+#define LL_DAC_MODE_CALIBRATION            (DAC_CR_CEN1)           /*!< DAC channel in mode calibration */

+/**

+  * @}

+  */

+

+/** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source

+  * @{

+  */

+#define LL_DAC_TRIG_SOFTWARE               0x00000000U                                                         /*!< DAC channel conversion trigger internal (SW start) */

+#define LL_DAC_TRIG_EXT_TIM1_TRGO          (                                                   DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM1 TRGO. */

+#define LL_DAC_TRIG_EXT_TIM2_TRGO          (                                  DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external peripheral: TIM2 TRGO. */

+#define LL_DAC_TRIG_EXT_TIM4_TRGO          (                                  DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM4 TRGO. */

+#define LL_DAC_TRIG_EXT_TIM5_TRGO          (                 DAC_CR_TSEL1_2                                  ) /*!< DAC channel conversion trigger from external peripheral: TIM5 TRGO. */

+#define LL_DAC_TRIG_EXT_TIM6_TRGO          (                 DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM6 TRGO. */

+#define LL_DAC_TRIG_EXT_TIM7_TRGO          (                 DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external peripheral: TIM7 TRGO. */

+#define LL_DAC_TRIG_EXT_TIM8_TRGO          (                 DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM8 TRGO. */

+#define LL_DAC_TRIG_EXT_TIM15_TRGO         (DAC_CR_TSEL1_3                                                   ) /*!< DAC channel conversion trigger from external peripheral: TIM15 TRGO. */

+#if defined (HRTIM1)

+#define LL_DAC_TRIG_EXT_HRTIM_TRGO1        (DAC_CR_TSEL1_3                                   | DAC_CR_TSEL1_0) /*!< HR1 TRGO1 selected as external conversion trigger for DAC channel 1 */

+#define LL_DAC_TRIG_EXT_HRTIM_TRGO2        (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1                 ) /*!< HR1 TRGO2 selected as external conversion trigger for DAC channel 2 */

+#endif

+#define LL_DAC_TRIG_EXT_LPTIM1_OUT         (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: LPTIM1 TRGO. */

+#define LL_DAC_TRIG_EXT_LPTIM2_OUT         (DAC_CR_TSEL1_3                  | DAC_CR_TSEL1_2                 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM2 TRGO. */

+#define LL_DAC_TRIG_EXT_EXTI_LINE9         (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: external interrupt line 9. */

+#if defined(TIM23)

+#define LL_DAC_TRIG_EXT_TIM23_TRGO         (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external peripheral: TIM23 TRGO. */

+#endif

+#if defined(TIM24)

+#define LL_DAC_TRIG_EXT_TIM24_TRGO         (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external peripheral: TIM24 TRGO. */

+#endif

+#if defined (DAC2)

+#define LL_DAC_TRIG_EXT_LPTIM3_OUT         (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                 ) /*!< DAC channel conversion trigger from external peripheral: LPTIM3 TRGO. */

+#endif

+/**

+  * @}

+  */

+

+/** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode

+  * @{

+  */

+#define LL_DAC_WAVE_AUTO_GENERATION_NONE     0x00000000UL                    /*!< DAC channel wave auto generation mode disabled. */

+#define LL_DAC_WAVE_AUTO_GENERATION_NOISE    (               DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */

+#define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1               ) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */

+/**

+  * @}

+  */

+

+/** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits

+  * @{

+  */

+#define LL_DAC_NOISE_LFSR_UNMASK_BIT0      0x00000000UL                                                        /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */

+#define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0   (                                                   DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */

+#define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0   (                                  DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */

+#define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0   (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */

+#define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0   (                 DAC_CR_MAMP1_2                                  ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */

+#define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0   (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */

+#define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0   (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */

+#define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0   (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */

+#define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0   (DAC_CR_MAMP1_3                                                   ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */

+#define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0   (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */

+#define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0  (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */

+#define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0  (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */

+/**

+  * @}

+  */

+

+/** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude

+  * @{

+  */

+#define LL_DAC_TRIANGLE_AMPLITUDE_1        0x00000000UL                                                        /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */

+#define LL_DAC_TRIANGLE_AMPLITUDE_3        (                                                   DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */

+#define LL_DAC_TRIANGLE_AMPLITUDE_7        (                                  DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */

+#define LL_DAC_TRIANGLE_AMPLITUDE_15       (                                  DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */

+#define LL_DAC_TRIANGLE_AMPLITUDE_31       (                 DAC_CR_MAMP1_2                                  ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */

+#define LL_DAC_TRIANGLE_AMPLITUDE_63       (                 DAC_CR_MAMP1_2                  | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */

+#define LL_DAC_TRIANGLE_AMPLITUDE_127      (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */

+#define LL_DAC_TRIANGLE_AMPLITUDE_255      (                 DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */

+#define LL_DAC_TRIANGLE_AMPLITUDE_511      (DAC_CR_MAMP1_3                                                   ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */

+#define LL_DAC_TRIANGLE_AMPLITUDE_1023     (DAC_CR_MAMP1_3                                   | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */

+#define LL_DAC_TRIANGLE_AMPLITUDE_2047     (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1                 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */

+#define LL_DAC_TRIANGLE_AMPLITUDE_4095     (DAC_CR_MAMP1_3                  | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */

+/**

+  * @}

+  */

+

+/** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode

+  * @{

+  */

+#define LL_DAC_OUTPUT_MODE_NORMAL          0x00000000UL            /*!< The selected DAC channel output is on mode normal. */

+#define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2)       /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */

+/**

+  * @}

+  */

+

+/** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer

+  * @{

+  */

+#define LL_DAC_OUTPUT_BUFFER_ENABLE        0x00000000UL            /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */

+#define LL_DAC_OUTPUT_BUFFER_DISABLE       (DAC_MCR_MODE1_1)       /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */

+/**

+  * @}

+  */

+

+/** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection

+  * @{

+  */

+#define LL_DAC_OUTPUT_CONNECT_GPIO         0x00000000UL            /*!< The selected DAC channel output is connected to external pin */

+#define LL_DAC_OUTPUT_CONNECT_INTERNAL     (DAC_MCR_MODE1_0)       /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 serie, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */

+/**

+  * @}

+  */

+

+/** @defgroup DAC_LL_EC_LEGACY DAC literals legacy naming

+  * @{

+  */

+#define LL_DAC_TRIGGER_SOFTWARE            (LL_DAC_TRIG_SOFTWARE)

+#define LL_DAC_TRIGGER_TIM2_TRGO           (LL_DAC_TRIG_EXT_TIM2_TRGO)

+#define LL_DAC_TRIGGER_TIM4_TRGO           (LL_DAC_TRIG_EXT_TIM4_TRGO)

+#define LL_DAC_TRIGGER_TIM6_TRGO           (LL_DAC_TRIG_EXT_TIM6_TRGO)

+#define LL_DAC_TRIGGER_TIM7_TRGO           (LL_DAC_TRIG_EXT_TIM7_TRGO)

+#define LL_DAC_TRIGGER_TIM8_TRGO           (LL_DAC_TRIG_EXT_TIM8_TRGO)

+#define LL_DAC_TRIGGER_EXT_IT9             (LL_DAC_TRIG_EXT_EXTI_LINE9)

+

+#define LL_DAC_WAVEGENERATION_NONE         (LL_DAC_WAVE_AUTO_GENERATION_NONE)

+#define LL_DAC_WAVEGENERATION_NOISE        (LL_DAC_WAVE_AUTO_GENERATION_NOISE)

+#define LL_DAC_WAVEGENERATION_TRIANGLE     (LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE)

+

+#define LL_DAC_CONNECT_GPIO                (LL_DAC_OUTPUT_CONNECT_GPIO)

+#define LL_DAC_CONNECT_INTERNAL            (LL_DAC_OUTPUT_CONNECT_INTERNAL)

+/**

+  * @}

+  */

+/** @defgroup DAC_LL_EC_RESOLUTION  DAC channel output resolution

+  * @{

+  */

+#define LL_DAC_RESOLUTION_12B              0x00000000UL            /*!< DAC channel resolution 12 bits */

+#define LL_DAC_RESOLUTION_8B               0x00000002UL            /*!< DAC channel resolution 8 bits */

+/**

+  * @}

+  */

+

+/** @defgroup DAC_LL_EC_REGISTERS  DAC registers compliant with specific purpose

+  * @{

+  */

+/* List of DAC registers intended to be used (most commonly) with             */

+/* DMA transfer.                                                              */

+/* Refer to function @ref LL_DAC_DMA_GetRegAddr().                            */

+#define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED  DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits right aligned */

+#define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED   DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS /*!< DAC channel data holding register 12 bits left aligned */

+#define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED   DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS  /*!< DAC channel data holding register 8 bits right aligned */

+/**

+  * @}

+  */

+

+/** @defgroup DAC_LL_EC_HW_DELAYS  Definitions of DAC hardware constraints delays

+  * @note   Only DAC peripheral HW delays are defined in DAC LL driver driver,

+  *         not timeout values.

+  *         For details on delays values, refer to descriptions in source code

+  *         above each literal definition.

+  * @{

+  */

+

+/* Delay for DAC channel voltage settling time from DAC channel startup       */

+/* (transition from disable to enable).                                       */

+/* Note: DAC channel startup time depends on board application environment:   */

+/*       impedance connected to DAC channel output.                           */

+/*       The delay below is specified under conditions:                       */

+/*        - voltage maximum transition (lowest to highest value)              */

+/*        - until voltage reaches final value +-1LSB                          */

+/*        - DAC channel output buffer enabled                                 */

+/*        - load impedance of 5kOhm (min), 50pF (max)                         */

+/* Literal set to maximum value (refer to device datasheet,                   */

+/* parameter "tWAKEUP").                                                      */

+/* Unit: us                                                                   */

+#define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US             8UL  /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */

+

+/* Delay for DAC channel voltage settling time.                               */

+/* Note: DAC channel startup time depends on board application environment:   */

+/*       impedance connected to DAC channel output.                           */

+/*       The delay below is specified under conditions:                       */

+/*        - voltage maximum transition (lowest to highest value)              */

+/*        - until voltage reaches final value +-1LSB                          */

+/*        - DAC channel output buffer enabled                                 */

+/*        - load impedance of 5kOhm min, 50pF max                             */

+/* Literal set to maximum value (refer to device datasheet,                   */

+/* parameter "tSETTLING").                                                    */

+/* Unit: us                                                                   */

+#define LL_DAC_DELAY_VOLTAGE_SETTLING_US                     3UL /*!< Delay for DAC channel voltage settling time */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup DAC_LL_Exported_Macros DAC Exported Macros

+  * @{

+  */

+

+/** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros

+  * @{

+  */

+

+/**

+  * @brief  Write a value in DAC register

+  * @param  __INSTANCE__ DAC Instance

+  * @param  __REG__ Register to be written

+  * @param  __VALUE__ Value to be written in the register

+  * @retval None

+  */

+#define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

+

+/**

+  * @brief  Read a value in DAC register

+  * @param  __INSTANCE__ DAC Instance

+  * @param  __REG__ Register to be read

+  * @retval Register value

+  */

+#define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)

+

+/**

+  * @}

+  */

+

+/** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro

+  * @{

+  */

+

+/**

+  * @brief  Helper macro to get DAC channel number in decimal format

+  *         from literals LL_DAC_CHANNEL_x.

+  *         Example:

+  *            __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1)

+  *            will return decimal number "1".

+  * @note   The input can be a value from functions where a channel

+  *         number is returned.

+  * @param  __CHANNEL__ This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @retval 1...2

+  */

+#define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__)                            \

+  ((__CHANNEL__) & DAC_SWTR_CHX_MASK)

+

+/**

+  * @brief  Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x

+  *         from number in decimal format.

+  *         Example:

+  *           __LL_DAC_DECIMAL_NB_TO_CHANNEL(1)

+  *           will return a data equivalent to "LL_DAC_CHANNEL_1".

+  * @note  If the input parameter does not correspond to a DAC channel,

+  *        this macro returns value '0'.

+  * @param  __DECIMAL_NB__ 1...2

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  */

+#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__)                         \

+  (((__DECIMAL_NB__) == 1UL)                                                   \

+    ? (                                                                        \

+       LL_DAC_CHANNEL_1                                                        \

+      )                                                                        \

+      :                                                                        \

+      (((__DECIMAL_NB__) == 2UL)                                               \

+        ? (                                                                    \

+           LL_DAC_CHANNEL_2                                                    \

+          )                                                                    \

+          :                                                                    \

+          (                                                                    \

+           0UL                                                                 \

+          )                                                                    \

+      )                                                                        \

+  )

+

+/**

+  * @brief  Helper macro to define the DAC conversion data full-scale digital

+  *         value corresponding to the selected DAC resolution.

+  * @note   DAC conversion data full-scale corresponds to voltage range

+  *         determined by analog voltage references Vref+ and Vref-

+  *         (refer to reference manual).

+  * @param  __DAC_RESOLUTION__ This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_RESOLUTION_12B

+  *         @arg @ref LL_DAC_RESOLUTION_8B

+  * @retval ADC conversion data equivalent voltage value (unit: mVolt)

+  */

+#define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)                             \

+  ((0x00000FFFUL) >> ((__DAC_RESOLUTION__) << 1UL))

+

+/**

+  * @brief  Helper macro to calculate the DAC conversion data (unit: digital

+  *         value) corresponding to a voltage (unit: mVolt).

+  * @note   This helper macro is intended to provide input data in voltage

+  *         rather than digital value,

+  *         to be used with LL DAC functions such as

+  *         @ref LL_DAC_ConvertData12RightAligned().

+  * @note   Analog reference voltage (Vref+) must be either known from

+  *         user board environment or can be calculated using ADC measurement

+  *         and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE().

+  * @param  __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV)

+  * @param  __DAC_VOLTAGE__ Voltage to be generated by DAC channel

+  *                         (unit: mVolt).

+  * @param  __DAC_RESOLUTION__ This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_RESOLUTION_12B

+  *         @arg @ref LL_DAC_RESOLUTION_8B

+  * @retval DAC conversion data (unit: digital value)

+  */

+#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\

+                                      __DAC_VOLTAGE__,\

+                                      __DAC_RESOLUTION__)                      \

+  ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__)              \

+   / (__VREFANALOG_VOLTAGE__)                                                  \

+  )

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup DAC_LL_Exported_Functions DAC Exported Functions

+  * @{

+  */

+/** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels

+  * @{

+  */

+

+/**

+  * @brief  Set the operating mode for the selected DAC channel:

+  *         calibration or normal operating mode.

+  * @rmtoll CR       CEN1           LL_DAC_SetMode\n

+  *         CR       CEN2           LL_DAC_SetMode

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @param  ChannelMode This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_MODE_NORMAL_OPERATION

+  *         @arg @ref LL_DAC_MODE_CALIBRATION

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode)

+{

+  MODIFY_REG(DACx->CR,

+             DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),

+             ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));

+}

+

+/**

+  * @brief  Get the operating mode for the selected DAC channel:

+  *         calibration or normal operating mode.

+  * @rmtoll CR       CEN1           LL_DAC_GetMode\n

+  *         CR       CEN2           LL_DAC_GetMode

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DAC_MODE_NORMAL_OPERATION

+  *         @arg @ref LL_DAC_MODE_CALIBRATION

+  */

+__STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)

+{

+  return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))

+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)

+                   );

+}

+

+/**

+  * @brief  Set the offset trimming value for the selected DAC channel.

+  *         Trimming has an impact when output buffer is enabled

+  *         and is intended to replace factory calibration default values.

+  * @rmtoll CCR      OTRIM1         LL_DAC_SetTrimmingValue\n

+  *         CCR      OTRIM2         LL_DAC_SetTrimmingValue

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @param  TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue)

+{

+  MODIFY_REG(DACx->CCR,

+             DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),

+             TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));

+}

+

+/**

+  * @brief  Get the offset trimming value for the selected DAC channel.

+  *         Trimming has an impact when output buffer is enabled

+  *         and is intended to replace factory calibration default values.

+  * @rmtoll CCR      OTRIM1         LL_DAC_GetTrimmingValue\n

+  *         CCR      OTRIM2         LL_DAC_GetTrimmingValue

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F

+  */

+__STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel)

+{

+  return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))

+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)

+                   );

+}

+

+/**

+  * @brief  Set the conversion trigger source for the selected DAC channel.

+  * @note   For conversion trigger source to be effective, DAC trigger

+  *         must be enabled using function @ref LL_DAC_EnableTrigger().

+  * @note   To set conversion trigger source, DAC channel must be disabled.

+  *         Otherwise, the setting is discarded.

+  * @note   Availability of parameters of trigger sources from timer

+  *         depends on timers availability on the selected device.

+  * @rmtoll CR       TSEL1          LL_DAC_SetTriggerSource\n

+  *         CR       TSEL2          LL_DAC_SetTriggerSource

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @param  TriggerSource This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_TRIG_SOFTWARE

+  *         @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO

+  *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO

+  *         @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO

+  *         @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO

+  *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO

+  *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO

+  *         @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO

+  *         @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO

+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1    (1)

+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2    (1)

+  *         @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT

+  *         @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT

+  *         @arg @ref LL_DAC_TRIG_EXT_LPTIM3_OUT     (2)

+  *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9

+  *         @arg @ref LL_DAC_TRIG_EXT_TIM23_TRGO     (3)

+  *         @arg @ref LL_DAC_TRIG_EXT_TIM24_TRGO     (4)

+  *

+  *         (1) On this STM32 serie, parameter not available on all devices.

+  *          Only available if HRTIM feature is supported (refer to device datasheet for supported features list)

+  *         (2) On this STM32 serie, parameter only available on DAC2.

+  *         (3) On this STM32 serie, parameter not available on all devices.

+  *          Only available if TIM23 feature is supported (refer to device datasheet for supported features list)

+  *         (4) On this STM32 serie, parameter not available on all devices.

+  *          Only available if TIM24 feature is supported (refer to device datasheet for supported features list)

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource)

+{

+  MODIFY_REG(DACx->CR,

+             DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),

+             TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));

+}

+

+/**

+  * @brief  Get the conversion trigger source for the selected DAC channel.

+  * @note   For conversion trigger source to be effective, DAC trigger

+  *         must be enabled using function @ref LL_DAC_EnableTrigger().

+  * @note   Availability of parameters of trigger sources from timer

+  *         depends on timers availability on the selected device.

+  * @rmtoll CR       TSEL1          LL_DAC_GetTriggerSource\n

+  *         CR       TSEL2          LL_DAC_GetTriggerSource

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DAC_TRIG_SOFTWARE

+  *         @arg @ref LL_DAC_TRIG_EXT_TIM1_TRGO

+  *         @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO

+  *         @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO

+  *         @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO

+  *         @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO

+  *         @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO

+  *         @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO

+  *         @arg @ref LL_DAC_TRIG_EXT_TIM15_TRGO

+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO1    (1)

+  *         @arg @ref LL_DAC_TRIG_EXT_HRTIM_TRGO2    (1)

+  *         @arg @ref LL_DAC_TRIG_EXT_LPTIM1_OUT

+  *         @arg @ref LL_DAC_TRIG_EXT_LPTIM2_OUT

+  *         @arg @ref LL_DAC_TRIG_EXT_LPTIM3_OUT     (2)

+  *         @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9

+  *         @arg @ref LL_DAC_TRIG_EXT_TIM23_TRGO     (3)

+  *         @arg @ref LL_DAC_TRIG_EXT_TIM24_TRGO     (4)

+  *

+  *         (1) On this STM32 serie, parameter not available on all devices.

+  *          Only available if HRTIM feature is supported (refer to device datasheet for supported features list)

+  *         (2) On this STM32 serie, parameter only available on DAC2.

+  *         (3) On this STM32 serie, parameter not available on all devices.

+  *          Only available if TIM23 feature is supported (refer to device datasheet for supported features list)

+  *         (4) On this STM32 serie, parameter not available on all devices.

+  *          Only available if TIM24 feature is supported (refer to device datasheet for supported features list)

+  */

+__STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel)

+{

+  return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))

+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)

+                   );

+}

+

+/**

+  * @brief  Set the waveform automatic generation mode

+  *         for the selected DAC channel.

+  * @rmtoll CR       WAVE1          LL_DAC_SetWaveAutoGeneration\n

+  *         CR       WAVE2          LL_DAC_SetWaveAutoGeneration

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @param  WaveAutoGeneration This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE

+  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE

+  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration)

+{

+  MODIFY_REG(DACx->CR,

+             DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),

+             WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));

+}

+

+/**

+  * @brief  Get the waveform automatic generation mode

+  *         for the selected DAC channel.

+  * @rmtoll CR       WAVE1          LL_DAC_GetWaveAutoGeneration\n

+  *         CR       WAVE2          LL_DAC_GetWaveAutoGeneration

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE

+  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE

+  *         @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE

+  */

+__STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel)

+{

+  return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))

+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)

+                   );

+}

+

+/**

+  * @brief  Set the noise waveform generation for the selected DAC channel:

+  *         Noise mode and parameters LFSR (linear feedback shift register).

+  * @note   For wave generation to be effective, DAC channel

+  *         wave generation mode must be enabled using

+  *         function @ref LL_DAC_SetWaveAutoGeneration().

+  * @note   This setting can be set when the selected DAC channel is disabled

+  *         (otherwise, the setting operation is ignored).

+  * @rmtoll CR       MAMP1          LL_DAC_SetWaveNoiseLFSR\n

+  *         CR       MAMP2          LL_DAC_SetWaveNoiseLFSR

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @param  NoiseLFSRMask This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0

+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0

+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0

+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0

+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0

+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0

+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0

+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0

+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0

+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0

+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0

+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask)

+{

+  MODIFY_REG(DACx->CR,

+             DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),

+             NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));

+}

+

+/**

+  * @brief  Get the noise waveform generation for the selected DAC channel:

+  *         Noise mode and parameters LFSR (linear feedback shift register).

+  * @rmtoll CR       MAMP1          LL_DAC_GetWaveNoiseLFSR\n

+  *         CR       MAMP2          LL_DAC_GetWaveNoiseLFSR

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0

+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0

+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0

+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0

+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0

+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0

+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0

+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0

+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0

+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0

+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0

+  *         @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0

+  */

+__STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel)

+{

+  return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))

+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)

+                   );

+}

+

+/**

+  * @brief  Set the triangle waveform generation for the selected DAC channel:

+  *         triangle mode and amplitude.

+  * @note   For wave generation to be effective, DAC channel

+  *         wave generation mode must be enabled using

+  *         function @ref LL_DAC_SetWaveAutoGeneration().

+  * @note   This setting can be set when the selected DAC channel is disabled

+  *         (otherwise, the setting operation is ignored).

+  * @rmtoll CR       MAMP1          LL_DAC_SetWaveTriangleAmplitude\n

+  *         CR       MAMP2          LL_DAC_SetWaveTriangleAmplitude

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @param  TriangleAmplitude This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1

+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3

+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7

+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15

+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31

+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63

+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127

+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255

+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511

+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023

+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047

+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel,

+                                                     uint32_t TriangleAmplitude)

+{

+  MODIFY_REG(DACx->CR,

+             DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),

+             TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));

+}

+

+/**

+  * @brief  Get the triangle waveform generation for the selected DAC channel:

+  *         triangle mode and amplitude.

+  * @rmtoll CR       MAMP1          LL_DAC_GetWaveTriangleAmplitude\n

+  *         CR       MAMP2          LL_DAC_GetWaveTriangleAmplitude

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1

+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3

+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7

+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15

+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31

+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63

+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127

+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255

+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511

+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023

+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047

+  *         @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095

+  */

+__STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel)

+{

+  return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))

+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)

+                   );

+}

+

+/**

+  * @brief  Set the output for the selected DAC channel.

+  * @note   This function set several features:

+  *         - mode normal or sample-and-hold

+  *         - buffer

+  *         - connection to GPIO or internal path.

+  *         These features can also be set individually using

+  *         dedicated functions:

+  *         - @ref LL_DAC_SetOutputBuffer()

+  *         - @ref LL_DAC_SetOutputMode()

+  *         - @ref LL_DAC_SetOutputConnection()

+  * @note   On this STM32 serie, output connection depends on output mode

+  *         (normal or sample and hold) and output buffer state.

+  *         - if output connection is set to internal path and output buffer

+  *           is enabled (whatever output mode):

+  *           output connection is also connected to GPIO pin

+  *           (both connections to GPIO pin and internal path).

+  *         - if output connection is set to GPIO pin, output buffer

+  *           is disabled, output mode set to sample and hold:

+  *           output connection is also connected to internal path

+  *           (both connections to GPIO pin and internal path).

+  * @note   Mode sample-and-hold requires an external capacitor

+  *         to be connected between DAC channel output and ground.

+  *         Capacitor value depends on load on DAC channel output and

+  *         sample-and-hold timings configured.

+  *         As indication, capacitor typical value is 100nF

+  *         (refer to device datasheet, parameter "CSH").

+  * @rmtoll CR       MODE1          LL_DAC_ConfigOutput\n

+  *         CR       MODE2          LL_DAC_ConfigOutput

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @param  OutputMode This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_OUTPUT_MODE_NORMAL

+  *         @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD

+  * @param  OutputBuffer This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE

+  *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE

+  * @param  OutputConnection This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO

+  *         @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode,

+                                         uint32_t OutputBuffer, uint32_t OutputConnection)

+{

+  MODIFY_REG(DACx->MCR,

+             (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),

+             (OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));

+}

+

+/**

+  * @brief  Set the output mode normal or sample-and-hold

+  *         for the selected DAC channel.

+  * @note   Mode sample-and-hold requires an external capacitor

+  *         to be connected between DAC channel output and ground.

+  *         Capacitor value depends on load on DAC channel output and

+  *         sample-and-hold timings configured.

+  *         As indication, capacitor typical value is 100nF

+  *         (refer to device datasheet, parameter "CSH").

+  * @rmtoll CR       MODE1          LL_DAC_SetOutputMode\n

+  *         CR       MODE2          LL_DAC_SetOutputMode

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @param  OutputMode This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_OUTPUT_MODE_NORMAL

+  *         @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode)

+{

+  MODIFY_REG(DACx->MCR,

+             (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),

+             OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));

+}

+

+/**

+  * @brief  Get the output mode normal or sample-and-hold for the selected DAC channel.

+  * @rmtoll CR       MODE1          LL_DAC_GetOutputMode\n

+  *         CR       MODE2          LL_DAC_GetOutputMode

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DAC_OUTPUT_MODE_NORMAL

+  *         @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD

+  */

+__STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel)

+{

+  return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))

+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)

+                   );

+}

+

+/**

+  * @brief  Set the output buffer for the selected DAC channel.

+  * @note   On this STM32 serie, when buffer is enabled, its offset can be

+  *         trimmed: factory calibration default values can be

+  *         replaced by user trimming values, using function

+  *         @ref LL_DAC_SetTrimmingValue().

+  * @rmtoll CR       MODE1          LL_DAC_SetOutputBuffer\n

+  *         CR       MODE2          LL_DAC_SetOutputBuffer

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @param  OutputBuffer This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE

+  *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer)

+{

+  MODIFY_REG(DACx->MCR,

+             (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),

+             OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));

+}

+

+/**

+  * @brief  Get the output buffer state for the selected DAC channel.

+  * @rmtoll CR       MODE1          LL_DAC_GetOutputBuffer\n

+  *         CR       MODE2          LL_DAC_GetOutputBuffer

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE

+  *         @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE

+  */

+__STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel)

+{

+  return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))

+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)

+                   );

+}

+

+/**

+  * @brief  Set the output connection for the selected DAC channel.

+  * @note   On this STM32 serie, output connection depends on output mode (normal or

+  *         sample and hold) and output buffer state.

+  *         - if output connection is set to internal path and output buffer

+  *           is enabled (whatever output mode):

+  *           output connection is also connected to GPIO pin

+  *           (both connections to GPIO pin and internal path).

+  *         - if output connection is set to GPIO pin, output buffer

+  *           is disabled, output mode set to sample and hold:

+  *           output connection is also connected to internal path

+  *           (both connections to GPIO pin and internal path).

+  * @rmtoll CR       MODE1          LL_DAC_SetOutputConnection\n

+  *         CR       MODE2          LL_DAC_SetOutputConnection

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @param  OutputConnection This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO

+  *         @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection)

+{

+  MODIFY_REG(DACx->MCR,

+             (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),

+             OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));

+}

+

+/**

+  * @brief  Get the output connection for the selected DAC channel.

+  * @note   On this STM32 serie, output connection depends on output mode (normal or

+  *         sample and hold) and output buffer state.

+  *         - if output connection is set to internal path and output buffer

+  *           is enabled (whatever output mode):

+  *           output connection is also connected to GPIO pin

+  *           (both connections to GPIO pin and internal path).

+  *         - if output connection is set to GPIO pin, output buffer

+  *           is disabled, output mode set to sample and hold:

+  *           output connection is also connected to internal path

+  *           (both connections to GPIO pin and internal path).

+  * @rmtoll CR       MODE1          LL_DAC_GetOutputConnection\n

+  *         CR       MODE2          LL_DAC_GetOutputConnection

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO

+  *         @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL

+  */

+__STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel)

+{

+  return (uint32_t)(READ_BIT(DACx->MCR, (uint32_t)DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))

+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)

+                   );

+}

+

+/**

+  * @brief  Set the sample-and-hold timing for the selected DAC channel:

+  *         sample time

+  * @note   Sample time must be set when DAC channel is disabled

+  *         or during DAC operation when DAC channel flag BWSTx is reset,

+  *         otherwise the setting is ignored.

+  *         Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()".

+  * @rmtoll SHSR1    TSAMPLE1       LL_DAC_SetSampleAndHoldSampleTime\n

+  *         SHSR2    TSAMPLE2       LL_DAC_SetSampleAndHoldSampleTime

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @param  SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime)

+{

+  __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);

+

+  MODIFY_REG(*preg,

+             DAC_SHSR1_TSAMPLE1,

+             SampleTime);

+}

+

+/**

+  * @brief  Get the sample-and-hold timing for the selected DAC channel:

+  *         sample time

+  * @rmtoll SHSR1    TSAMPLE1       LL_DAC_GetSampleAndHoldSampleTime\n

+  *         SHSR2    TSAMPLE2       LL_DAC_GetSampleAndHoldSampleTime

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @retval Value between Min_Data=0x000 and Max_Data=0x3FF

+  */

+__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)

+{

+  __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, (DAC_Channel >> DAC_REG_SHSRX_REGOFFSET_BITOFFSET_POS) & DAC_REG_SHSRX_REGOFFSET_MASK_POSBIT0);

+

+  return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1);

+}

+

+/**

+  * @brief  Set the sample-and-hold timing for the selected DAC channel:

+  *         hold time

+  * @rmtoll SHHR     THOLD1         LL_DAC_SetSampleAndHoldHoldTime\n

+  *         SHHR     THOLD2         LL_DAC_SetSampleAndHoldHoldTime

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @param  HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime)

+{

+  MODIFY_REG(DACx->SHHR,

+             DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),

+             HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));

+}

+

+/**

+  * @brief  Get the sample-and-hold timing for the selected DAC channel:

+  *         hold time

+  * @rmtoll SHHR     THOLD1         LL_DAC_GetSampleAndHoldHoldTime\n

+  *         SHHR     THOLD2         LL_DAC_GetSampleAndHoldHoldTime

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @retval Value between Min_Data=0x000 and Max_Data=0x3FF

+  */

+__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)

+{

+  return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))

+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)

+                   );

+}

+

+/**

+  * @brief  Set the sample-and-hold timing for the selected DAC channel:

+  *         refresh time

+  * @rmtoll SHRR     TREFRESH1      LL_DAC_SetSampleAndHoldRefreshTime\n

+  *         SHRR     TREFRESH2      LL_DAC_SetSampleAndHoldRefreshTime

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @param  RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime)

+{

+  MODIFY_REG(DACx->SHRR,

+             DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK),

+             RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));

+}

+

+/**

+  * @brief  Get the sample-and-hold timing for the selected DAC channel:

+  *         refresh time

+  * @rmtoll SHRR     TREFRESH1      LL_DAC_GetSampleAndHoldRefreshTime\n

+  *         SHRR     TREFRESH2      LL_DAC_GetSampleAndHoldRefreshTime

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF

+  */

+__STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel)

+{

+  return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))

+                    >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)

+                   );

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup DAC_LL_EF_DMA_Management DMA Management

+  * @{

+  */

+

+/**

+  * @brief  Enable DAC DMA transfer request of the selected channel.

+  * @note   To configure DMA source address (peripheral address),

+  *         use function @ref LL_DAC_DMA_GetRegAddr().

+  * @rmtoll CR       DMAEN1         LL_DAC_EnableDMAReq\n

+  *         CR       DMAEN2         LL_DAC_EnableDMAReq

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)

+{

+  SET_BIT(DACx->CR,

+          DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));

+}

+

+/**

+  * @brief  Disable DAC DMA transfer request of the selected channel.

+  * @note   To configure DMA source address (peripheral address),

+  *         use function @ref LL_DAC_DMA_GetRegAddr().

+  * @rmtoll CR       DMAEN1         LL_DAC_DisableDMAReq\n

+  *         CR       DMAEN2         LL_DAC_DisableDMAReq

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel)

+{

+  CLEAR_BIT(DACx->CR,

+            DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));

+}

+

+/**

+  * @brief  Get DAC DMA transfer request state of the selected channel.

+  *         (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled)

+  * @rmtoll CR       DMAEN1         LL_DAC_IsDMAReqEnabled\n

+  *         CR       DMAEN2         LL_DAC_IsDMAReqEnabled

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)

+{

+  return ((READ_BIT(DACx->CR,

+                    DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))

+           == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Function to help to configure DMA transfer to DAC: retrieve the

+  *         DAC register address from DAC instance and a list of DAC registers

+  *         intended to be used (most commonly) with DMA transfer.

+  * @note   These DAC registers are data holding registers:

+  *         when DAC conversion is requested, DAC generates a DMA transfer

+  *         request to have data available in DAC data holding registers.

+  * @note   This macro is intended to be used with LL DMA driver, refer to

+  *         function "LL_DMA_ConfigAddresses()".

+  *         Example:

+  *           LL_DMA_ConfigAddresses(DMA1,

+  *                                  LL_DMA_CHANNEL_1,

+  *                                  (uint32_t)&< array or variable >,

+  *                                  LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED),

+  *                                  LL_DMA_DIRECTION_MEMORY_TO_PERIPH);

+  * @rmtoll DHR12R1  DACC1DHR       LL_DAC_DMA_GetRegAddr\n

+  *         DHR12L1  DACC1DHR       LL_DAC_DMA_GetRegAddr\n

+  *         DHR8R1   DACC1DHR       LL_DAC_DMA_GetRegAddr\n

+  *         DHR12R2  DACC2DHR       LL_DAC_DMA_GetRegAddr\n

+  *         DHR12L2  DACC2DHR       LL_DAC_DMA_GetRegAddr\n

+  *         DHR8R2   DACC2DHR       LL_DAC_DMA_GetRegAddr

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @param  Register This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED

+  *         @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED

+  *         @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED

+  * @retval DAC register address

+  */

+__STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register)

+{

+  /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on     */

+  /* DAC channel selected.                                                    */

+  return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1,

+                                          ((DAC_Channel >> (Register & 0x1FUL)) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0))));

+}

+/**

+  * @}

+  */

+

+/** @defgroup DAC_LL_EF_Operation Operation on DAC channels

+  * @{

+  */

+

+/**

+  * @brief  Enable DAC selected channel.

+  * @rmtoll CR       EN1            LL_DAC_Enable\n

+  *         CR       EN2            LL_DAC_Enable

+  * @note   After enable from off state, DAC channel requires a delay

+  *         for output voltage to reach accuracy +/- 1 LSB.

+  *         Refer to device datasheet, parameter "tWAKEUP".

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel)

+{

+  SET_BIT(DACx->CR,

+          DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));

+}

+

+/**

+  * @brief  Disable DAC selected channel.

+  * @rmtoll CR       EN1            LL_DAC_Disable\n

+  *         CR       EN2            LL_DAC_Disable

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel)

+{

+  CLEAR_BIT(DACx->CR,

+            DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));

+}

+

+/**

+  * @brief  Get DAC enable state of the selected channel.

+  *         (0: DAC channel is disabled, 1: DAC channel is enabled)

+  * @rmtoll CR       EN1            LL_DAC_IsEnabled\n

+  *         CR       EN2            LL_DAC_IsEnabled

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)

+{

+  return ((READ_BIT(DACx->CR,

+                    DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))

+           == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable DAC trigger of the selected channel.

+  * @note   - If DAC trigger is disabled, DAC conversion is performed

+  *           automatically once the data holding register is updated,

+  *           using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":

+  *           @ref LL_DAC_ConvertData12RightAligned(), ...

+  *         - If DAC trigger is enabled, DAC conversion is performed

+  *           only when a hardware of software trigger event is occurring.

+  *           Select trigger source using

+  *           function @ref LL_DAC_SetTriggerSource().

+  * @rmtoll CR       TEN1           LL_DAC_EnableTrigger\n

+  *         CR       TEN2           LL_DAC_EnableTrigger

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)

+{

+  SET_BIT(DACx->CR,

+          DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));

+}

+

+/**

+  * @brief  Disable DAC trigger of the selected channel.

+  * @rmtoll CR       TEN1           LL_DAC_DisableTrigger\n

+  *         CR       TEN2           LL_DAC_DisableTrigger

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel)

+{

+  CLEAR_BIT(DACx->CR,

+            DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK));

+}

+

+/**

+  * @brief  Get DAC trigger state of the selected channel.

+  *         (0: DAC trigger is disabled, 1: DAC trigger is enabled)

+  * @rmtoll CR       TEN1           LL_DAC_IsTriggerEnabled\n

+  *         CR       TEN2           LL_DAC_IsTriggerEnabled

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel)

+{

+  return ((READ_BIT(DACx->CR,

+                    DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))

+           == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Trig DAC conversion by software for the selected DAC channel.

+  * @note   Preliminarily, DAC trigger must be set to software trigger

+  *         using function

+  *           @ref LL_DAC_Init()

+  *           @ref LL_DAC_SetTriggerSource()

+  *         with parameter "LL_DAC_TRIGGER_SOFTWARE".

+  *         and DAC trigger must be enabled using

+  *         function @ref LL_DAC_EnableTrigger().

+  * @note   For devices featuring DAC with 2 channels: this function

+  *         can perform a SW start of both DAC channels simultaneously.

+  *         Two channels can be selected as parameter.

+  *         Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2)

+  * @rmtoll SWTRIGR  SWTRIG1        LL_DAC_TrigSWConversion\n

+  *         SWTRIGR  SWTRIG2        LL_DAC_TrigSWConversion

+  * @param  DACx DAC instance

+  * @param  DAC_Channel  This parameter can a combination of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel)

+{

+  SET_BIT(DACx->SWTRIGR,

+          (DAC_Channel & DAC_SWTR_CHX_MASK));

+}

+

+/**

+  * @brief  Set the data to be loaded in the data holding register

+  *         in format 12 bits left alignment (LSB aligned on bit 0),

+  *         for the selected DAC channel.

+  * @rmtoll DHR12R1  DACC1DHR       LL_DAC_ConvertData12RightAligned\n

+  *         DHR12R2  DACC2DHR       LL_DAC_ConvertData12RightAligned

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @param  Data Value between Min_Data=0x000 and Max_Data=0xFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)

+{

+  __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);

+

+  MODIFY_REG(*preg,

+             DAC_DHR12R1_DACC1DHR,

+             Data);

+}

+

+/**

+  * @brief  Set the data to be loaded in the data holding register

+  *         in format 12 bits left alignment (MSB aligned on bit 15),

+  *         for the selected DAC channel.

+  * @rmtoll DHR12L1  DACC1DHR       LL_DAC_ConvertData12LeftAligned\n

+  *         DHR12L2  DACC2DHR       LL_DAC_ConvertData12LeftAligned

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @param  Data Value between Min_Data=0x000 and Max_Data=0xFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)

+{

+  __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR12LX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);

+

+  MODIFY_REG(*preg,

+             DAC_DHR12L1_DACC1DHR,

+             Data);

+}

+

+/**

+  * @brief  Set the data to be loaded in the data holding register

+  *         in format 8 bits left alignment (LSB aligned on bit 0),

+  *         for the selected DAC channel.

+  * @rmtoll DHR8R1   DACC1DHR       LL_DAC_ConvertData8RightAligned\n

+  *         DHR8R2   DACC2DHR       LL_DAC_ConvertData8RightAligned

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data)

+{

+  __IO uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, (DAC_Channel >> DAC_REG_DHR8RX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DHR_REGOFFSET_MASK_POSBIT0);

+

+  MODIFY_REG(*preg,

+             DAC_DHR8R1_DACC1DHR,

+             Data);

+}

+

+

+/**

+  * @brief  Set the data to be loaded in the data holding register

+  *         in format 12 bits left alignment (LSB aligned on bit 0),

+  *         for both DAC channels.

+  * @rmtoll DHR12RD  DACC1DHR       LL_DAC_ConvertDualData12RightAligned\n

+  *         DHR12RD  DACC2DHR       LL_DAC_ConvertDualData12RightAligned

+  * @param  DACx DAC instance

+  * @param  DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF

+  * @param  DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,

+                                                          uint32_t DataChannel2)

+{

+  MODIFY_REG(DACx->DHR12RD,

+             (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR),

+             ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));

+}

+

+/**

+  * @brief  Set the data to be loaded in the data holding register

+  *         in format 12 bits left alignment (MSB aligned on bit 15),

+  *         for both DAC channels.

+  * @rmtoll DHR12LD  DACC1DHR       LL_DAC_ConvertDualData12LeftAligned\n

+  *         DHR12LD  DACC2DHR       LL_DAC_ConvertDualData12LeftAligned

+  * @param  DACx DAC instance

+  * @param  DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF

+  * @param  DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,

+                                                         uint32_t DataChannel2)

+{

+  /* Note: Data of DAC channel 2 shift value subtracted of 4 because          */

+  /*       data on 16 bits and DAC channel 2 bits field is on the 12 MSB,     */

+  /*       the 4 LSB must be taken into account for the shift value.          */

+  MODIFY_REG(DACx->DHR12LD,

+             (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR),

+             ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1));

+}

+

+/**

+  * @brief  Set the data to be loaded in the data holding register

+  *         in format 8 bits left alignment (LSB aligned on bit 0),

+  *         for both DAC channels.

+  * @rmtoll DHR8RD  DACC1DHR       LL_DAC_ConvertDualData8RightAligned\n

+  *         DHR8RD  DACC2DHR       LL_DAC_ConvertDualData8RightAligned

+  * @param  DACx DAC instance

+  * @param  DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF

+  * @param  DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1,

+                                                         uint32_t DataChannel2)

+{

+  MODIFY_REG(DACx->DHR8RD,

+             (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR),

+             ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1));

+}

+

+

+/**

+  * @brief  Retrieve output data currently generated for the selected DAC channel.

+  * @note   Whatever alignment and resolution settings

+  *         (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()":

+  *         @ref LL_DAC_ConvertData12RightAligned(), ...),

+  *         output data format is 12 bits right aligned (LSB aligned on bit 0).

+  * @rmtoll DOR1     DACC1DOR       LL_DAC_RetrieveOutputData\n

+  *         DOR2     DACC2DOR       LL_DAC_RetrieveOutputData

+  * @param  DACx DAC instance

+  * @param  DAC_Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DAC_CHANNEL_1

+  *         @arg @ref LL_DAC_CHANNEL_2

+  * @retval Value between Min_Data=0x000 and Max_Data=0xFFF

+  */

+__STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel)

+{

+  __IO uint32_t const *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, (DAC_Channel >> DAC_REG_DORX_REGOFFSET_BITOFFSET_POS) & DAC_REG_DORX_REGOFFSET_MASK_POSBIT0);

+

+  return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup DAC_LL_EF_FLAG_Management FLAG Management

+  * @{

+  */

+/**

+  * @brief  Get DAC calibration offset flag for DAC channel 1

+  * @rmtoll SR       CAL_FLAG1      LL_DAC_IsActiveFlag_CAL1

+  * @param  DACx DAC instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx)

+{

+  return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)) ? 1UL : 0UL);

+}

+

+

+/**

+  * @brief  Get DAC calibration offset flag for DAC channel 2

+  * @rmtoll SR       CAL_FLAG2      LL_DAC_IsActiveFlag_CAL2

+  * @param  DACx DAC instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx)

+{

+  return ((READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)) ? 1UL : 0UL);

+}

+

+

+/**

+  * @brief  Get DAC busy writing sample time flag for DAC channel 1

+  * @rmtoll SR       BWST1          LL_DAC_IsActiveFlag_BWST1

+  * @param  DACx DAC instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx)

+{

+  return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)) ? 1UL : 0UL);

+}

+

+

+/**

+  * @brief  Get DAC busy writing sample time flag for DAC channel 2

+  * @rmtoll SR       BWST2          LL_DAC_IsActiveFlag_BWST2

+  * @param  DACx DAC instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx)

+{

+  return ((READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)) ? 1UL : 0UL);

+}

+

+

+/**

+  * @brief  Get DAC underrun flag for DAC channel 1

+  * @rmtoll SR       DMAUDR1        LL_DAC_IsActiveFlag_DMAUDR1

+  * @param  DACx DAC instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx)

+{

+  return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)) ? 1UL : 0UL);

+}

+

+

+/**

+  * @brief  Get DAC underrun flag for DAC channel 2

+  * @rmtoll SR       DMAUDR2        LL_DAC_IsActiveFlag_DMAUDR2

+  * @param  DACx DAC instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx)

+{

+  return ((READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)) ? 1UL : 0UL);

+}

+

+

+/**

+  * @brief  Clear DAC underrun flag for DAC channel 1

+  * @rmtoll SR       DMAUDR1        LL_DAC_ClearFlag_DMAUDR1

+  * @param  DACx DAC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx)

+{

+  WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1);

+}

+

+

+/**

+  * @brief  Clear DAC underrun flag for DAC channel 2

+  * @rmtoll SR       DMAUDR2        LL_DAC_ClearFlag_DMAUDR2

+  * @param  DACx DAC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx)

+{

+  WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2);

+}

+

+

+/**

+  * @}

+  */

+

+/** @defgroup DAC_LL_EF_IT_Management IT management

+  * @{

+  */

+

+/**

+  * @brief  Enable DMA underrun interrupt for DAC channel 1

+  * @rmtoll CR       DMAUDRIE1      LL_DAC_EnableIT_DMAUDR1

+  * @param  DACx DAC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx)

+{

+  SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);

+}

+

+

+/**

+  * @brief  Enable DMA underrun interrupt for DAC channel 2

+  * @rmtoll CR       DMAUDRIE2      LL_DAC_EnableIT_DMAUDR2

+  * @param  DACx DAC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx)

+{

+  SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);

+}

+

+

+/**

+  * @brief  Disable DMA underrun interrupt for DAC channel 1

+  * @rmtoll CR       DMAUDRIE1      LL_DAC_DisableIT_DMAUDR1

+  * @param  DACx DAC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx)

+{

+  CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1);

+}

+

+

+/**

+  * @brief  Disable DMA underrun interrupt for DAC channel 2

+  * @rmtoll CR       DMAUDRIE2      LL_DAC_DisableIT_DMAUDR2

+  * @param  DACx DAC instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx)

+{

+  CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2);

+}

+

+

+/**

+  * @brief  Get DMA underrun interrupt for DAC channel 1

+  * @rmtoll CR       DMAUDRIE1      LL_DAC_IsEnabledIT_DMAUDR1

+  * @param  DACx DAC instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx)

+{

+  return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)) ? 1UL : 0UL);

+}

+

+

+/**

+  * @brief  Get DMA underrun interrupt for DAC channel 2

+  * @rmtoll CR       DMAUDRIE2      LL_DAC_IsEnabledIT_DMAUDR2

+  * @param  DACx DAC instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx)

+{

+  return ((READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)) ? 1UL : 0UL);

+}

+

+

+/**

+  * @}

+  */

+

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions

+  * @{

+  */

+

+ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx);

+ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef *DAC_InitStruct);

+void        LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct);

+

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* DAC1 || DAC2 */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_LL_DAC_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_delayblock.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_delayblock.h
new file mode 100644
index 0000000000..315151d4cb
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_delayblock.h
@@ -0,0 +1,88 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_delayblock.h

+  * @author  MCD Application Team

+  * @brief   Header file of Delay Block module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */ 

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_LL_DLYB_H

+#define STM32H7xx_LL_DLYB_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup DELAYBLOCK_LL

+  * @{

+  */ 

+

+/* Exported types ------------------------------------------------------------*/ 

+/** @defgroup DELAYBLOCK_LL_Exported_Types DELAYBLOCK_LL Exported Types

+  * @{

+  */

+  

+

+/**

+  * @}

+  */

+  

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup DLYB_Exported_Constants Delay Block Exported Constants

+  * @{

+  */

+

+

+#define DLYB_MAX_UNIT   ((uint32_t)0x00000080U) /*!< Max UNIT value (128)  */

+#define DLYB_MAX_SELECT ((uint32_t)0x0000000CU) /*!< Max SELECT value (12)  */

+

+/**

+  * @}

+  */ 

+ 

+/* Peripheral Control functions  ************************************************/

+/** @addtogroup HAL_DELAYBLOCK_LL_Group3 Delay Block functions

+  * @{

+  */

+HAL_StatusTypeDef DelayBlock_Enable(DLYB_TypeDef *DLYBx);

+HAL_StatusTypeDef DelayBlock_Disable(DLYB_TypeDef *DLYBx);

+HAL_StatusTypeDef DelayBlock_Configure(DLYB_TypeDef *DLYBx, uint32_t PhaseSel, uint32_t Units);

+

+/**

+  * @}

+  */

+  

+  

+/**

+  * @}

+  */

+

+  /**

+  * @}

+  */

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_LL_DLYB_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_dma.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_dma.h
new file mode 100644
index 0000000000..342f7d4e50
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_dma.h
@@ -0,0 +1,3246 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_dma.h

+  * @author  MCD Application Team

+  * @brief   Header file of DMA LL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_LL_DMA_H

+#define STM32H7xx_LL_DMA_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+#include "stm32h7xx_ll_dmamux.h"

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+#if defined (DMA1) || defined (DMA2)

+

+/** @defgroup DMA_LL DMA

+  * @{

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/** @defgroup DMA_LL_Private_Variables DMA Private Variables

+  * @{

+  */

+/* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */

+static const uint8_t LL_DMA_STR_OFFSET_TAB[] =

+{

+  (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),

+  (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),

+  (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),

+  (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),

+  (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),

+  (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),

+  (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),

+  (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)

+};

+

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+

+/**

+  * @brief  Helper macro to convert DMA Instance DMAx into DMAMUX channel

+  * @note   DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.

+  *         DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.

+  * @param  __DMA_INSTANCE__ DMAx

+  * @retval Channel_Offset (LL_DMAMUX_CHANNEL_8 or 0).

+  */

+#define LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__)   \

+(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0UL : 8UL)

+

+/* Exported types ------------------------------------------------------------*/

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure

+  * @{

+  */

+typedef struct

+{

+  uint32_t PeriphOrM2MSrcAddress;  /*!< Specifies the peripheral base address for DMA transfer

+                                        or as Source base address in case of memory to memory transfer direction.

+

+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */

+

+  uint32_t MemoryOrM2MDstAddress;  /*!< Specifies the memory base address for DMA transfer

+                                        or as Destination base address in case of memory to memory transfer direction.

+

+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */

+

+  uint32_t Direction;              /*!< Specifies if the data will be transferred from memory to peripheral,

+                                        from memory to memory or from peripheral to memory.

+                                        This parameter can be a value of @ref DMA_LL_EC_DIRECTION

+

+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */

+

+  uint32_t Mode;                   /*!< Specifies the normal or circular operation mode.

+                                        This parameter can be a value of @ref DMA_LL_EC_MODE

+                                        @note The circular buffer mode cannot be used if the memory to memory

+                                              data transfer direction is configured on the selected Stream

+

+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */

+

+  uint32_t PeriphOrM2MSrcIncMode;  /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction

+                                        is incremented or not.

+                                        This parameter can be a value of @ref DMA_LL_EC_PERIPH

+

+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */

+

+  uint32_t MemoryOrM2MDstIncMode;  /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction

+                                        is incremented or not.

+                                        This parameter can be a value of @ref DMA_LL_EC_MEMORY

+

+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */

+

+  uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)

+                                        in case of memory to memory transfer direction.

+                                        This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN

+

+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */

+

+  uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)

+                                        in case of memory to memory transfer direction.

+                                        This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN

+

+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */

+

+  uint32_t NbData;                 /*!< Specifies the number of data to transfer, in data unit.

+                                        The data unit is equal to the source buffer configuration set in PeripheralSize

+                                        or MemorySize parameters depending in the transfer direction.

+                                        This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF

+

+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */

+

+  uint32_t PeriphRequest;          /*!< Specifies the peripheral request.

+                                        This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST

+

+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */

+

+  uint32_t Priority;               /*!< Specifies the channel priority level.

+                                        This parameter can be a value of @ref DMA_LL_EC_PRIORITY

+

+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */

+

+  uint32_t FIFOMode;               /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.

+                                        This parameter can be a value of @ref DMA_LL_FIFOMODE

+                                        @note The Direct mode (FIFO mode disabled) cannot be used if the

+                                        memory-to-memory data transfer is configured on the selected stream

+

+                                        This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */

+

+  uint32_t FIFOThreshold;          /*!< Specifies the FIFO threshold level.

+                                        This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD

+

+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */

+

+  uint32_t MemBurst;               /*!< Specifies the Burst transfer configuration for the memory transfers.

+                                        It specifies the amount of data to be transferred in a single non interruptible

+                                        transaction.

+                                        This parameter can be a value of @ref DMA_LL_EC_MBURST

+                                        @note The burst mode is possible only if the address Increment mode is enabled.

+

+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */

+

+  uint32_t PeriphBurst;            /*!< Specifies the Burst transfer configuration for the peripheral transfers.

+                                        It specifies the amount of data to be transferred in a single non interruptible

+                                        transaction.

+                                        This parameter can be a value of @ref DMA_LL_EC_PBURST

+                                        @note The burst mode is possible only if the address Increment mode is enabled.

+

+                                        This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */

+

+} LL_DMA_InitTypeDef;

+/**

+  * @}

+  */

+#endif /*USE_FULL_LL_DRIVER*/

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants

+  * @{

+  */

+

+/** @defgroup DMA_LL_EC_STREAM STREAM

+  * @{

+  */

+#define LL_DMA_STREAM_0                   0x00000000U

+#define LL_DMA_STREAM_1                   0x00000001U

+#define LL_DMA_STREAM_2                   0x00000002U

+#define LL_DMA_STREAM_3                   0x00000003U

+#define LL_DMA_STREAM_4                   0x00000004U

+#define LL_DMA_STREAM_5                   0x00000005U

+#define LL_DMA_STREAM_6                   0x00000006U

+#define LL_DMA_STREAM_7                   0x00000007U

+#define LL_DMA_STREAM_ALL                 0xFFFF0000U

+/**

+  * @}

+  */

+

+

+/** @defgroup DMA_LL_EC_DIRECTION DIRECTION

+  * @{

+  */

+#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U               /*!< Peripheral to memory direction */

+#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0            /*!< Memory to peripheral direction */

+#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1            /*!< Memory to memory direction     */

+/**

+  * @}

+  */

+

+/** @defgroup DMA_LL_EC_MODE MODE

+  * @{

+  */

+#define LL_DMA_MODE_NORMAL                0x00000000U               /*!< Normal Mode                  */

+#define LL_DMA_MODE_CIRCULAR              DMA_SxCR_CIRC             /*!< Circular Mode                */

+#define LL_DMA_MODE_PFCTRL                DMA_SxCR_PFCTRL           /*!< Peripheral flow control mode */

+/**

+  * @}

+  */

+

+/** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE

+  * @{

+  */

+#define LL_DMA_DOUBLEBUFFER_MODE_DISABLE  0x00000000U               /*!< Disable double buffering mode */

+#define LL_DMA_DOUBLEBUFFER_MODE_ENABLE   DMA_SxCR_DBM              /*!< Enable double buffering mode  */

+/**

+  * @}

+  */

+

+/** @defgroup DMA_LL_EC_PERIPH PERIPH

+  * @{

+  */

+#define LL_DMA_PERIPH_NOINCREMENT         0x00000000U               /*!< Peripheral increment mode Disable */

+#define LL_DMA_PERIPH_INCREMENT           DMA_SxCR_PINC             /*!< Peripheral increment mode Enable  */

+/**

+  * @}

+  */

+

+/** @defgroup DMA_LL_EC_MEMORY MEMORY

+  * @{

+  */

+#define LL_DMA_MEMORY_NOINCREMENT         0x00000000U               /*!< Memory increment mode Disable */

+#define LL_DMA_MEMORY_INCREMENT           DMA_SxCR_MINC             /*!< Memory increment mode Enable  */

+/**

+  * @}

+  */

+

+/** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN

+  * @{

+  */

+#define LL_DMA_PDATAALIGN_BYTE            0x00000000U               /*!< Peripheral data alignment : Byte     */

+#define LL_DMA_PDATAALIGN_HALFWORD        DMA_SxCR_PSIZE_0          /*!< Peripheral data alignment : HalfWord */

+#define LL_DMA_PDATAALIGN_WORD            DMA_SxCR_PSIZE_1          /*!< Peripheral data alignment : Word     */

+/**

+  * @}

+  */

+

+/** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN

+  * @{

+  */

+#define LL_DMA_MDATAALIGN_BYTE            0x00000000U               /*!< Memory data alignment : Byte     */

+#define LL_DMA_MDATAALIGN_HALFWORD        DMA_SxCR_MSIZE_0          /*!< Memory data alignment : HalfWord */

+#define LL_DMA_MDATAALIGN_WORD            DMA_SxCR_MSIZE_1          /*!< Memory data alignment : Word     */

+/**

+  * @}

+  */

+

+/** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE

+  * @{

+  */

+#define LL_DMA_OFFSETSIZE_PSIZE           0x00000000U               /*!< Peripheral increment offset size is linked to the PSIZE           */

+#define LL_DMA_OFFSETSIZE_FIXEDTO4        DMA_SxCR_PINCOS           /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */

+/**

+  * @}

+  */

+

+/** @defgroup DMA_LL_EC_PRIORITY PRIORITY

+  * @{

+  */

+#define LL_DMA_PRIORITY_LOW               0x00000000U               /*!< Priority level : Low       */

+#define LL_DMA_PRIORITY_MEDIUM            DMA_SxCR_PL_0             /*!< Priority level : Medium    */

+#define LL_DMA_PRIORITY_HIGH              DMA_SxCR_PL_1             /*!< Priority level : High      */

+#define LL_DMA_PRIORITY_VERYHIGH          DMA_SxCR_PL               /*!< Priority level : Very_High */

+/**

+  * @}

+  */

+

+

+/** @defgroup DMA_LL_EC_MBURST MBURST

+  * @{

+  */

+#define LL_DMA_MBURST_SINGLE              0x00000000U                             /*!< Memory burst single transfer configuration      */

+#define LL_DMA_MBURST_INC4                DMA_SxCR_MBURST_0                       /*!< Memory burst of 4 beats transfer configuration  */

+#define LL_DMA_MBURST_INC8                DMA_SxCR_MBURST_1                       /*!< Memory burst of 8 beats transfer configuration  */

+#define LL_DMA_MBURST_INC16               (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */

+/**

+  * @}

+  */

+

+/** @defgroup DMA_LL_EC_PBURST PBURST

+  * @{

+  */

+#define LL_DMA_PBURST_SINGLE              0x00000000U                             /*!< Peripheral burst single transfer configuration      */

+#define LL_DMA_PBURST_INC4                DMA_SxCR_PBURST_0                       /*!< Peripheral burst of 4 beats transfer configuration  */

+#define LL_DMA_PBURST_INC8                DMA_SxCR_PBURST_1                       /*!< Peripheral burst of 8 beats transfer configuration  */

+#define LL_DMA_PBURST_INC16               (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */

+/**

+  * @}

+  */

+

+/** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE

+  * @{

+  */

+#define LL_DMA_FIFOMODE_DISABLE           0x00000000U                             /*!< FIFO mode disable (direct mode is enabled) */

+#define LL_DMA_FIFOMODE_ENABLE            DMA_SxFCR_DMDIS                         /*!< FIFO mode enable                           */

+/**

+  * @}

+  */

+

+/** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0

+  * @{

+  */

+#define LL_DMA_FIFOSTATUS_0_25            0x00000000U                             /*!< 0 < fifo_level < 1/4    */

+#define LL_DMA_FIFOSTATUS_25_50           DMA_SxFCR_FS_0                          /*!< 1/4 < fifo_level < 1/2  */

+#define LL_DMA_FIFOSTATUS_50_75           DMA_SxFCR_FS_1                          /*!< 1/2 < fifo_level < 3/4  */

+#define LL_DMA_FIFOSTATUS_75_100          (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0)       /*!< 3/4 < fifo_level < full */

+#define LL_DMA_FIFOSTATUS_EMPTY           DMA_SxFCR_FS_2                          /*!< FIFO is empty           */

+#define LL_DMA_FIFOSTATUS_FULL            (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0)       /*!< FIFO is full            */

+/**

+  * @}

+  */

+

+/** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD

+  * @{

+  */

+#define LL_DMA_FIFOTHRESHOLD_1_4          0x00000000U                             /*!< FIFO threshold 1 quart full configuration  */

+#define LL_DMA_FIFOTHRESHOLD_1_2          DMA_SxFCR_FTH_0                         /*!< FIFO threshold half full configuration     */

+#define LL_DMA_FIFOTHRESHOLD_3_4          DMA_SxFCR_FTH_1                         /*!< FIFO threshold 3 quarts full configuration */

+#define LL_DMA_FIFOTHRESHOLD_FULL         DMA_SxFCR_FTH                           /*!< FIFO threshold full configuration          */

+/**

+  * @}

+  */

+

+/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM

+  * @{

+  */

+#define LL_DMA_CURRENTTARGETMEM0          0x00000000U                             /*!< Set CurrentTarget Memory to Memory 0  */

+#define LL_DMA_CURRENTTARGETMEM1          DMA_SxCR_CT                             /*!< Set CurrentTarget Memory to Memory 1  */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros

+  * @{

+  */

+

+/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros

+  * @{

+  */

+/**

+  * @brief  Write a value in DMA register

+  * @param  __INSTANCE__ DMA Instance

+  * @param  __REG__ Register to be written

+  * @param  __VALUE__ Value to be written in the register

+  * @retval None

+  */

+#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))

+

+/**

+  * @brief  Read a value in DMA register

+  * @param  __INSTANCE__ DMA Instance

+  * @param  __REG__ Register to be read

+  * @retval Register value

+  */

+#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)

+/**

+  * @}

+  */

+

+/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy

+  * @{

+  */

+/**

+  * @brief  Convert DMAx_Streamy into DMAx

+  * @param  __STREAM_INSTANCE__ DMAx_Streamy

+  * @retval DMAx

+  */

+#define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__)   \

+(((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ?  DMA2 : DMA1)

+

+/**

+  * @brief  Convert DMAx_Streamy into LL_DMA_STREAM_y

+  * @param  __STREAM_INSTANCE__ DMAx_Streamy

+  * @retval LL_DMA_STREAM_y

+  */

+#define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__)   \

+(((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \

+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \

+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \

+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \

+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \

+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \

+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \

+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \

+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \

+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \

+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \

+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \

+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \

+ ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \

+ LL_DMA_STREAM_7)

+

+/**

+  * @brief  Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy

+  * @param  __DMA_INSTANCE__ DMAx

+  * @param  __STREAM__ LL_DMA_STREAM_y

+  * @retval DMAx_Streamy

+  */

+#define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__)   \

+((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \

+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \

+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \

+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \

+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \

+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \

+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \

+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \

+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \

+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \

+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \

+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \

+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \

+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \

+ (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \

+ DMA2_Stream7)

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions

+ * @{

+ */

+

+/** @defgroup DMA_LL_EF_Configuration Configuration

+  * @{

+  */

+/**

+  * @brief Enable DMA stream.

+  * @rmtoll CR          EN            LL_DMA_EnableStream

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN);

+}

+

+/**

+  * @brief Disable DMA stream.

+  * @rmtoll CR          EN            LL_DMA_DisableStream

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN);

+}

+

+/**

+  * @brief Check if DMA stream is enabled or disabled.

+  * @rmtoll CR          EN            LL_DMA_IsEnabledStream

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Configure all parameters linked to DMA transfer.

+  * @rmtoll CR          DIR           LL_DMA_ConfigTransfer\n

+  *         CR          CIRC          LL_DMA_ConfigTransfer\n

+  *         CR          PINC          LL_DMA_ConfigTransfer\n

+  *         CR          MINC          LL_DMA_ConfigTransfer\n

+  *         CR          PSIZE         LL_DMA_ConfigTransfer\n

+  *         CR          MSIZE         LL_DMA_ConfigTransfer\n

+  *         CR          PL            LL_DMA_ConfigTransfer\n

+  *         CR          PFCTRL        LL_DMA_ConfigTransfer

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @param  Configuration This parameter must be a combination of all the following values:

+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY

+  *         @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR  or @ref LL_DMA_MODE_PFCTRL

+  *         @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT

+  *         @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT

+  *         @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD

+  *         @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD

+  *         @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH

+  *@retval None

+  */

+__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR,

+             DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL,

+             Configuration);

+}

+

+/**

+  * @brief Set Data transfer direction (read from peripheral or from memory).

+  * @rmtoll CR          DIR           LL_DMA_SetDataTransferDirection

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @param  Direction This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY

+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH

+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Direction)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR, Direction);

+}

+

+/**

+  * @brief Get Data transfer direction (read from peripheral or from memory).

+  * @rmtoll CR          DIR           LL_DMA_GetDataTransferDirection

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY

+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH

+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY

+  */

+__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR));

+}

+

+/**

+  * @brief Set DMA mode normal, circular or peripheral flow control.

+  * @rmtoll CR          CIRC           LL_DMA_SetMode\n

+  *         CR          PFCTRL         LL_DMA_SetMode

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @param  Mode This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_MODE_NORMAL

+  *         @arg @ref LL_DMA_MODE_CIRCULAR

+  *         @arg @ref LL_DMA_MODE_PFCTRL

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode);

+}

+

+/**

+  * @brief Get DMA mode normal, circular or peripheral flow control.

+  * @rmtoll CR          CIRC           LL_DMA_GetMode\n

+  *         CR          PFCTRL         LL_DMA_GetMode

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMA_MODE_NORMAL

+  *         @arg @ref LL_DMA_MODE_CIRCULAR

+  *         @arg @ref LL_DMA_MODE_PFCTRL

+  */

+__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL));

+}

+

+/**

+  * @brief Set Peripheral increment mode.

+  * @rmtoll CR          PINC           LL_DMA_SetPeriphIncMode

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @param  IncrementMode This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT

+  *         @arg @ref LL_DMA_PERIPH_INCREMENT

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC, IncrementMode);

+}

+

+/**

+  * @brief Get Peripheral increment mode.

+  * @rmtoll CR          PINC           LL_DMA_GetPeriphIncMode

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMA_PERIPH_NOINCREMENT

+  *         @arg @ref LL_DMA_PERIPH_INCREMENT

+  */

+__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC));

+}

+

+/**

+  * @brief Set Memory increment mode.

+  * @rmtoll CR          MINC           LL_DMA_SetMemoryIncMode

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @param  IncrementMode This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT

+  *         @arg @ref LL_DMA_MEMORY_INCREMENT

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC, IncrementMode);

+}

+

+/**

+  * @brief Get Memory increment mode.

+  * @rmtoll CR          MINC           LL_DMA_GetMemoryIncMode

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMA_MEMORY_NOINCREMENT

+  *         @arg @ref LL_DMA_MEMORY_INCREMENT

+  */

+__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC));

+}

+

+/**

+  * @brief Set Peripheral size.

+  * @rmtoll CR          PSIZE           LL_DMA_SetPeriphSize

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @param  Size This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_PDATAALIGN_BYTE

+  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD

+  *         @arg @ref LL_DMA_PDATAALIGN_WORD

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Size)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE, Size);

+}

+

+/**

+  * @brief Get Peripheral size.

+  * @rmtoll CR          PSIZE           LL_DMA_GetPeriphSize

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMA_PDATAALIGN_BYTE

+  *         @arg @ref LL_DMA_PDATAALIGN_HALFWORD

+  *         @arg @ref LL_DMA_PDATAALIGN_WORD

+  */

+__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE));

+}

+

+/**

+  * @brief Set Memory size.

+  * @rmtoll CR          MSIZE           LL_DMA_SetMemorySize

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @param  Size This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_MDATAALIGN_BYTE

+  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD

+  *         @arg @ref LL_DMA_MDATAALIGN_WORD

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Size)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE, Size);

+}

+

+/**

+  * @brief Get Memory size.

+  * @rmtoll CR          MSIZE           LL_DMA_GetMemorySize

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMA_MDATAALIGN_BYTE

+  *         @arg @ref LL_DMA_MDATAALIGN_HALFWORD

+  *         @arg @ref LL_DMA_MDATAALIGN_WORD

+  */

+__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE));

+}

+

+/**

+  * @brief Set Peripheral increment offset size.

+  * @rmtoll CR          PINCOS           LL_DMA_SetIncOffsetSize

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @param  OffsetSize This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_OFFSETSIZE_PSIZE

+  *         @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS, OffsetSize);

+}

+

+/**

+  * @brief Get Peripheral increment offset size.

+  * @rmtoll CR          PINCOS           LL_DMA_GetIncOffsetSize

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMA_OFFSETSIZE_PSIZE

+  *         @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4

+  */

+__STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS));

+}

+

+/**

+  * @brief Set Stream priority level.

+  * @rmtoll CR          PL           LL_DMA_SetStreamPriorityLevel

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @param  Priority This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_PRIORITY_LOW

+  *         @arg @ref LL_DMA_PRIORITY_MEDIUM

+  *         @arg @ref LL_DMA_PRIORITY_HIGH

+  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t  Priority)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL, Priority);

+}

+

+/**

+  * @brief Get Stream priority level.

+  * @rmtoll CR          PL           LL_DMA_GetStreamPriorityLevel

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMA_PRIORITY_LOW

+  *         @arg @ref LL_DMA_PRIORITY_MEDIUM

+  *         @arg @ref LL_DMA_PRIORITY_HIGH

+  *         @arg @ref LL_DMA_PRIORITY_VERYHIGH

+  */

+__STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL));

+}

+

+/**

+  * @brief Enable DMA stream bufferable transfer.

+  * @rmtoll CR          TRBUFF            LL_DMA_EnableBufferableTransfer

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_EnableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF);

+}

+

+/**

+  * @brief Disable DMA stream bufferable transfer.

+  * @rmtoll CR          TRBUFF            LL_DMA_DisableBufferableTransfer

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_DisableBufferableTransfer(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TRBUFF);

+}

+

+/**

+  * @brief Set Number of data to transfer.

+  * @rmtoll NDTR          NDT           LL_DMA_SetDataLength

+  * @note   This action has no effect if

+  *         stream is enabled.

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @param  NbData Between 0 to 0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t NbData)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT, NbData);

+}

+

+/**

+  * @brief Get Number of data to transfer.

+  * @rmtoll NDTR          NDT           LL_DMA_GetDataLength

+  * @note   Once the stream is enabled, the return value indicate the

+  *         remaining bytes to be transmitted.

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval Between 0 to 0xFFFFFFFF

+  */

+__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT));

+}

+/**

+  * @brief  Set DMA request for DMA Streams on DMAMUX Channel x.

+  * @note   DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.

+  *         DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.

+  * @rmtoll CxCR         DMAREQ_ID     LL_DMA_SetPeriphRequest

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @param  Request This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX1_REQ_MEM2MEM

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR0

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR1

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR2

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR3

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR4

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR5

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR6

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR7

+  *         @arg @ref LL_DMAMUX1_REQ_ADC1

+  *         @arg @ref LL_DMAMUX1_REQ_ADC2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH3

+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH4

+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG

+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_COM

+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH3

+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH4

+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH3

+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH4

+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG

+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH3

+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_UP

+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_RX

+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_TX

+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_RX

+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_TX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_RX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_TX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_RX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_TX

+  *         @arg @ref LL_DMAMUX1_REQ_USART1_RX

+  *         @arg @ref LL_DMAMUX1_REQ_USART1_TX

+  *         @arg @ref LL_DMAMUX1_REQ_USART2_RX

+  *         @arg @ref LL_DMAMUX1_REQ_USART2_TX

+  *         @arg @ref LL_DMAMUX1_REQ_USART3_RX

+  *         @arg @ref LL_DMAMUX1_REQ_USART3_TX

+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH3

+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH4

+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG

+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_COM

+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH3

+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH4

+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG

+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_RX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_TX

+  *         @arg @ref LL_DMAMUX1_REQ_UART4_RX

+  *         @arg @ref LL_DMAMUX1_REQ_UART4_TX

+  *         @arg @ref LL_DMAMUX1_REQ_UART5_RX

+  *         @arg @ref LL_DMAMUX1_REQ_UART5_TX

+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM6_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM7_UP

+  *         @arg @ref LL_DMAMUX1_REQ_USART6_RX

+  *         @arg @ref LL_DMAMUX1_REQ_USART6_TX

+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_RX

+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_TX

+  *         @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI

+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_IN

+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_OUT

+  *         @arg @ref LL_DMAMUX1_REQ_HASH_IN

+  *         @arg @ref LL_DMAMUX1_REQ_UART7_RX

+  *         @arg @ref LL_DMAMUX1_REQ_UART7_TX

+  *         @arg @ref LL_DMAMUX1_REQ_UART8_RX

+  *         @arg @ref LL_DMAMUX1_REQ_UART8_TX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_RX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_TX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_RX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_TX

+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_A

+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_B

+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_A

+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_B

+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_RX

+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_TX

+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT

+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS

+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)

+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)

+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)

+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)

+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)

+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)

+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0

+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1

+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2

+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3

+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG

+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_COM

+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_UP

+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)

+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)

+  *         @arg @ref LL_DMAMUX1_REQ_ADC3 (*)

+  *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)

+  *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)

+  *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)

+  *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)

+  * @note   (*) Availability depends on devices.

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Request)

+{

+  MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);

+}

+

+/**

+  * @brief  Get DMA request for DMA Channels on DMAMUX Channel x.

+  * @note   DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.

+  *         DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.

+  * @rmtoll CxCR         DMAREQ_ID     LL_DMA_GetPeriphRequest

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMAMUX1_REQ_MEM2MEM

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR0

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR1

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR2

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR3

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR4

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR5

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR6

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR7

+  *         @arg @ref LL_DMAMUX1_REQ_ADC1

+  *         @arg @ref LL_DMAMUX1_REQ_ADC2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH3

+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH4

+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG

+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_COM

+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH3

+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH4

+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH3

+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH4

+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG

+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH3

+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_UP

+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_RX

+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_TX

+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_RX

+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_TX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_RX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_TX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_RX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_TX

+  *         @arg @ref LL_DMAMUX1_REQ_USART1_RX

+  *         @arg @ref LL_DMAMUX1_REQ_USART1_TX

+  *         @arg @ref LL_DMAMUX1_REQ_USART2_RX

+  *         @arg @ref LL_DMAMUX1_REQ_USART2_TX

+  *         @arg @ref LL_DMAMUX1_REQ_USART3_RX

+  *         @arg @ref LL_DMAMUX1_REQ_USART3_TX

+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH3

+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH4

+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG

+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_COM

+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH3

+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH4

+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG

+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_RX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_TX

+  *         @arg @ref LL_DMAMUX1_REQ_UART4_RX

+  *         @arg @ref LL_DMAMUX1_REQ_UART4_TX

+  *         @arg @ref LL_DMAMUX1_REQ_UART5_RX

+  *         @arg @ref LL_DMAMUX1_REQ_UART5_TX

+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM6_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM7_UP

+  *         @arg @ref LL_DMAMUX1_REQ_USART6_RX

+  *         @arg @ref LL_DMAMUX1_REQ_USART6_TX

+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_RX

+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_TX

+  *         @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI

+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_IN

+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_OUT

+  *         @arg @ref LL_DMAMUX1_REQ_HASH_IN

+  *         @arg @ref LL_DMAMUX1_REQ_UART7_RX

+  *         @arg @ref LL_DMAMUX1_REQ_UART7_TX

+  *         @arg @ref LL_DMAMUX1_REQ_UART8_RX

+  *         @arg @ref LL_DMAMUX1_REQ_UART8_TX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_RX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_TX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_RX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_TX

+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_A

+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_B

+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_A

+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_B

+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_RX

+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_TX

+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT

+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS

+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)

+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)

+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)

+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)

+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)

+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)

+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0

+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1

+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2

+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3

+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG

+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_COM

+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_UP

+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)

+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)

+  *         @arg @ref LL_DMAMUX1_REQ_ADC3 (*)

+  *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)

+  *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)

+  *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)

+  *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)

+  * @note   (*) Availability depends on devices.

+  */

+__STATIC_INLINE  uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID));

+}

+

+/**

+  * @brief Set Memory burst transfer configuration.

+  * @rmtoll CR          MBURST           LL_DMA_SetMemoryBurstxfer

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @param  Mburst This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_MBURST_SINGLE

+  *         @arg @ref LL_DMA_MBURST_INC4

+  *         @arg @ref LL_DMA_MBURST_INC8

+  *         @arg @ref LL_DMA_MBURST_INC16

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST, Mburst);

+}

+

+/**

+  * @brief Get Memory burst transfer configuration.

+  * @rmtoll CR          MBURST           LL_DMA_GetMemoryBurstxfer

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMA_MBURST_SINGLE

+  *         @arg @ref LL_DMA_MBURST_INC4

+  *         @arg @ref LL_DMA_MBURST_INC8

+  *         @arg @ref LL_DMA_MBURST_INC16

+  */

+__STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST));

+}

+

+/**

+  * @brief Set  Peripheral burst transfer configuration.

+  * @rmtoll CR          PBURST           LL_DMA_SetPeriphBurstxfer

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @param  Pburst This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_PBURST_SINGLE

+  *         @arg @ref LL_DMA_PBURST_INC4

+  *         @arg @ref LL_DMA_PBURST_INC8

+  *         @arg @ref LL_DMA_PBURST_INC16

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST, Pburst);

+}

+

+/**

+  * @brief Get Peripheral burst transfer configuration.

+  * @rmtoll CR          PBURST           LL_DMA_GetPeriphBurstxfer

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMA_PBURST_SINGLE

+  *         @arg @ref LL_DMA_PBURST_INC4

+  *         @arg @ref LL_DMA_PBURST_INC8

+  *         @arg @ref LL_DMA_PBURST_INC16

+  */

+__STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST));

+}

+

+/**

+  * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.

+  * @rmtoll CR          CT           LL_DMA_SetCurrentTargetMem

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @param CurrentMemory This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_CURRENTTARGETMEM0

+  *         @arg @ref LL_DMA_CURRENTTARGETMEM1

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT, CurrentMemory);

+}

+

+/**

+  * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.

+  * @rmtoll CR          CT           LL_DMA_GetCurrentTargetMem

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMA_CURRENTTARGETMEM0

+  *         @arg @ref LL_DMA_CURRENTTARGETMEM1

+  */

+__STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT));

+}

+

+/**

+  * @brief Enable the double buffer mode.

+  * @rmtoll CR          DBM           LL_DMA_EnableDoubleBufferMode

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM);

+}

+

+/**

+  * @brief Disable the double buffer mode.

+  * @rmtoll CR          DBM           LL_DMA_DisableDoubleBufferMode

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM);

+}

+

+/**

+  * @brief Get FIFO status.

+  * @rmtoll FCR          FS          LL_DMA_GetFIFOStatus

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMA_FIFOSTATUS_0_25

+  *         @arg @ref LL_DMA_FIFOSTATUS_25_50

+  *         @arg @ref LL_DMA_FIFOSTATUS_50_75

+  *         @arg @ref LL_DMA_FIFOSTATUS_75_100

+  *         @arg @ref LL_DMA_FIFOSTATUS_EMPTY

+  *         @arg @ref LL_DMA_FIFOSTATUS_FULL

+  */

+__STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FS));

+}

+

+/**

+  * @brief Disable Fifo mode.

+  * @rmtoll FCR          DMDIS          LL_DMA_DisableFifoMode

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS);

+}

+

+/**

+  * @brief Enable Fifo mode.

+  * @rmtoll FCR          DMDIS          LL_DMA_EnableFifoMode

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS);

+}

+

+/**

+  * @brief Select FIFO threshold.

+  * @rmtoll FCR         FTH          LL_DMA_SetFIFOThreshold

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @param  Threshold This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4

+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2

+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4

+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH, Threshold);

+}

+

+/**

+  * @brief Get FIFO threshold.

+  * @rmtoll FCR         FTH          LL_DMA_GetFIFOThreshold

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4

+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2

+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4

+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL

+  */

+__STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH));

+}

+

+/**

+  * @brief Configure the FIFO .

+  * @rmtoll FCR         FTH          LL_DMA_ConfigFifo\n

+  *         FCR         DMDIS        LL_DMA_ConfigFifo

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @param  FifoMode This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_FIFOMODE_ENABLE

+  *         @arg @ref LL_DMA_FIFOMODE_DISABLE

+  * @param  FifoThreshold This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_4

+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_1_2

+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_3_4

+  *         @arg @ref LL_DMA_FIFOTHRESHOLD_FULL

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH | DMA_SxFCR_DMDIS, FifoMode | FifoThreshold);

+}

+

+/**

+  * @brief Configure the Source and Destination addresses.

+  * @note   This API must not be called when the DMA stream is enabled.

+  * @rmtoll M0AR        M0A         LL_DMA_ConfigAddresses\n

+  *         PAR         PA          LL_DMA_ConfigAddresses

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @param  SrcAddress Between 0 to 0xFFFFFFFF

+  * @param  DstAddress Between 0 to 0xFFFFFFFF

+  * @param  Direction This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY

+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH

+  *         @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  /* Direction Memory to Periph */

+  if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)

+  {

+    WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, SrcAddress);

+    WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, DstAddress);

+  }

+  /* Direction Periph to Memory and Memory to Memory */

+  else

+  {

+    WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, SrcAddress);

+    WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, DstAddress);

+  }

+}

+

+/**

+  * @brief  Set the Memory address.

+  * @rmtoll M0AR        M0A         LL_DMA_SetMemoryAddress

+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.

+  * @note   This API must not be called when the DMA stream is enabled.

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @param  MemoryAddress Between 0 to 0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress);

+}

+

+/**

+  * @brief  Set the Peripheral address.

+  * @rmtoll PAR        PA         LL_DMA_SetPeriphAddress

+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.

+  * @note   This API must not be called when the DMA stream is enabled.

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @param  PeriphAddress Between 0 to 0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, PeriphAddress);

+}

+

+/**

+  * @brief  Get the Memory address.

+  * @rmtoll M0AR        M0A         LL_DMA_GetMemoryAddress

+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval Between 0 to 0xFFFFFFFF

+  */

+__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR));

+}

+

+/**

+  * @brief  Get the Peripheral address.

+  * @rmtoll PAR        PA         LL_DMA_GetPeriphAddress

+  * @note   Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval Between 0 to 0xFFFFFFFF

+  */

+__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR));

+}

+

+/**

+  * @brief  Set the Memory to Memory Source address.

+  * @rmtoll PAR        PA         LL_DMA_SetM2MSrcAddress

+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.

+  * @note   This API must not be called when the DMA stream is enabled.

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @param  MemoryAddress Between 0 to 0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, MemoryAddress);

+}

+

+/**

+  * @brief  Set the Memory to Memory Destination address.

+  * @rmtoll M0AR        M0A         LL_DMA_SetM2MDstAddress

+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.

+  * @note   This API must not be called when the DMA stream is enabled.

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @param  MemoryAddress Between 0 to 0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress);

+}

+

+/**

+  * @brief  Get the Memory to Memory Source address.

+  * @rmtoll PAR        PA         LL_DMA_GetM2MSrcAddress

+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval Between 0 to 0xFFFFFFFF

+  */

+__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR));

+}

+

+/**

+  * @brief  Get the Memory to Memory Destination address.

+  * @rmtoll M0AR        M0A         LL_DMA_GetM2MDstAddress

+  * @note   Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval Between 0 to 0xFFFFFFFF

+  */

+__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR));

+}

+

+/**

+  * @brief Set Memory 1 address (used in case of Double buffer mode).

+  * @rmtoll M1AR        M1A         LL_DMA_SetMemory1Address

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @param  Address Between 0 to 0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR, DMA_SxM1AR_M1A, Address);

+}

+

+/**

+  * @brief Get Memory 1 address (used in case of Double buffer mode).

+  * @rmtoll M1AR        M1A         LL_DMA_GetMemory1Address

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval Between 0 to 0xFFFFFFFF

+  */

+__STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  return (((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management

+  * @{

+  */

+

+/**

+  * @brief Get Stream 0 half transfer flag.

+  * @rmtoll LISR  HTIF0    LL_DMA_IsActiveFlag_HT0

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF0) == (DMA_LISR_HTIF0)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 1 half transfer flag.

+  * @rmtoll LISR  HTIF1    LL_DMA_IsActiveFlag_HT1

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF1) == (DMA_LISR_HTIF1)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 2 half transfer flag.

+  * @rmtoll LISR  HTIF2    LL_DMA_IsActiveFlag_HT2

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF2) == (DMA_LISR_HTIF2)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 3 half transfer flag.

+  * @rmtoll LISR  HTIF3    LL_DMA_IsActiveFlag_HT3

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->LISR, DMA_LISR_HTIF3) == (DMA_LISR_HTIF3)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 4 half transfer flag.

+  * @rmtoll HISR  HTIF4    LL_DMA_IsActiveFlag_HT4

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF4) == (DMA_HISR_HTIF4)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 5 half transfer flag.

+  * @rmtoll HISR  HTIF0    LL_DMA_IsActiveFlag_HT5

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF5) == (DMA_HISR_HTIF5)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 6 half transfer flag.

+  * @rmtoll HISR  HTIF6    LL_DMA_IsActiveFlag_HT6

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF6) == (DMA_HISR_HTIF6)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 7 half transfer flag.

+  * @rmtoll HISR  HTIF7    LL_DMA_IsActiveFlag_HT7

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->HISR, DMA_HISR_HTIF7) == (DMA_HISR_HTIF7)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 0 transfer complete flag.

+  * @rmtoll LISR  TCIF0    LL_DMA_IsActiveFlag_TC0

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF0) == (DMA_LISR_TCIF0)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 1 transfer complete flag.

+  * @rmtoll LISR  TCIF1    LL_DMA_IsActiveFlag_TC1

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF1) == (DMA_LISR_TCIF1)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 2 transfer complete flag.

+  * @rmtoll LISR  TCIF2    LL_DMA_IsActiveFlag_TC2

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF2) == (DMA_LISR_TCIF2)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 3 transfer complete flag.

+  * @rmtoll LISR  TCIF3    LL_DMA_IsActiveFlag_TC3

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TCIF3) == (DMA_LISR_TCIF3)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 4 transfer complete flag.

+  * @rmtoll HISR  TCIF4    LL_DMA_IsActiveFlag_TC4

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF4) == (DMA_HISR_TCIF4)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 5 transfer complete flag.

+  * @rmtoll HISR  TCIF0    LL_DMA_IsActiveFlag_TC5

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF5) == (DMA_HISR_TCIF5)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 6 transfer complete flag.

+  * @rmtoll HISR  TCIF6    LL_DMA_IsActiveFlag_TC6

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF6) == (DMA_HISR_TCIF6)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 7 transfer complete flag.

+  * @rmtoll HISR  TCIF7    LL_DMA_IsActiveFlag_TC7

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TCIF7) == (DMA_HISR_TCIF7)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 0 transfer error flag.

+  * @rmtoll LISR  TEIF0    LL_DMA_IsActiveFlag_TE0

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF0) == (DMA_LISR_TEIF0)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 1 transfer error flag.

+  * @rmtoll LISR  TEIF1    LL_DMA_IsActiveFlag_TE1

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF1) == (DMA_LISR_TEIF1)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 2 transfer error flag.

+  * @rmtoll LISR  TEIF2    LL_DMA_IsActiveFlag_TE2

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF2) == (DMA_LISR_TEIF2)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 3 transfer error flag.

+  * @rmtoll LISR  TEIF3    LL_DMA_IsActiveFlag_TE3

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->LISR, DMA_LISR_TEIF3) == (DMA_LISR_TEIF3)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 4 transfer error flag.

+  * @rmtoll HISR  TEIF4    LL_DMA_IsActiveFlag_TE4

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF4) == (DMA_HISR_TEIF4)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 5 transfer error flag.

+  * @rmtoll HISR  TEIF0    LL_DMA_IsActiveFlag_TE5

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF5) == (DMA_HISR_TEIF5)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 6 transfer error flag.

+  * @rmtoll HISR  TEIF6    LL_DMA_IsActiveFlag_TE6

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF6) == (DMA_HISR_TEIF6)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 7 transfer error flag.

+  * @rmtoll HISR  TEIF7    LL_DMA_IsActiveFlag_TE7

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->HISR, DMA_HISR_TEIF7) == (DMA_HISR_TEIF7)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 0 direct mode error flag.

+  * @rmtoll LISR  DMEIF0    LL_DMA_IsActiveFlag_DME0

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF0) == (DMA_LISR_DMEIF0)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 1 direct mode error flag.

+  * @rmtoll LISR  DMEIF1    LL_DMA_IsActiveFlag_DME1

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF1) == (DMA_LISR_DMEIF1)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 2 direct mode error flag.

+  * @rmtoll LISR  DMEIF2    LL_DMA_IsActiveFlag_DME2

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF2) == (DMA_LISR_DMEIF2)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 3 direct mode error flag.

+  * @rmtoll LISR  DMEIF3    LL_DMA_IsActiveFlag_DME3

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->LISR, DMA_LISR_DMEIF3) == (DMA_LISR_DMEIF3)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 4 direct mode error flag.

+  * @rmtoll HISR  DMEIF4    LL_DMA_IsActiveFlag_DME4

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF4) == (DMA_HISR_DMEIF4)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 5 direct mode error flag.

+  * @rmtoll HISR  DMEIF0    LL_DMA_IsActiveFlag_DME5

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF5) == (DMA_HISR_DMEIF5)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 6 direct mode error flag.

+  * @rmtoll HISR  DMEIF6    LL_DMA_IsActiveFlag_DME6

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF6) == (DMA_HISR_DMEIF6)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 7 direct mode error flag.

+  * @rmtoll HISR  DMEIF7    LL_DMA_IsActiveFlag_DME7

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->HISR, DMA_HISR_DMEIF7) == (DMA_HISR_DMEIF7)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 0 FIFO error flag.

+  * @rmtoll LISR  FEIF0    LL_DMA_IsActiveFlag_FE0

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF0) == (DMA_LISR_FEIF0)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 1 FIFO error flag.

+  * @rmtoll LISR  FEIF1    LL_DMA_IsActiveFlag_FE1

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF1) == (DMA_LISR_FEIF1)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 2 FIFO error flag.

+  * @rmtoll LISR  FEIF2    LL_DMA_IsActiveFlag_FE2

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF2) == (DMA_LISR_FEIF2)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 3 FIFO error flag.

+  * @rmtoll LISR  FEIF3    LL_DMA_IsActiveFlag_FE3

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->LISR, DMA_LISR_FEIF3) == (DMA_LISR_FEIF3)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 4 FIFO error flag.

+  * @rmtoll HISR  FEIF4    LL_DMA_IsActiveFlag_FE4

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF4) == (DMA_HISR_FEIF4)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 5 FIFO error flag.

+  * @rmtoll HISR  FEIF0    LL_DMA_IsActiveFlag_FE5

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF5) == (DMA_HISR_FEIF5)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 6 FIFO error flag.

+  * @rmtoll HISR  FEIF6    LL_DMA_IsActiveFlag_FE6

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF6) == (DMA_HISR_FEIF6)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get Stream 7 FIFO error flag.

+  * @rmtoll HISR  FEIF7    LL_DMA_IsActiveFlag_FE7

+  * @param  DMAx DMAx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)

+{

+  return ((READ_BIT(DMAx->HISR, DMA_HISR_FEIF7) == (DMA_HISR_FEIF7)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Clear Stream 0 half transfer flag.

+  * @rmtoll LIFCR  CHTIF0    LL_DMA_ClearFlag_HT0

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF0);

+}

+

+/**

+  * @brief Clear Stream 1 half transfer flag.

+  * @rmtoll LIFCR  CHTIF1    LL_DMA_ClearFlag_HT1

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF1);

+}

+

+/**

+  * @brief Clear Stream 2 half transfer flag.

+  * @rmtoll LIFCR  CHTIF2    LL_DMA_ClearFlag_HT2

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF2);

+}

+

+/**

+  * @brief Clear Stream 3 half transfer flag.

+  * @rmtoll LIFCR  CHTIF3    LL_DMA_ClearFlag_HT3

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CHTIF3);

+}

+

+/**

+  * @brief Clear Stream 4 half transfer flag.

+  * @rmtoll HIFCR  CHTIF4    LL_DMA_ClearFlag_HT4

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF4);

+}

+

+/**

+  * @brief Clear Stream 5 half transfer flag.

+  * @rmtoll HIFCR  CHTIF5    LL_DMA_ClearFlag_HT5

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF5);

+}

+

+/**

+  * @brief Clear Stream 6 half transfer flag.

+  * @rmtoll HIFCR  CHTIF6    LL_DMA_ClearFlag_HT6

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF6);

+}

+

+/**

+  * @brief Clear Stream 7 half transfer flag.

+  * @rmtoll HIFCR  CHTIF7    LL_DMA_ClearFlag_HT7

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CHTIF7);

+}

+

+/**

+  * @brief Clear Stream 0 transfer complete flag.

+  * @rmtoll LIFCR  CTCIF0    LL_DMA_ClearFlag_TC0

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF0);

+}

+

+/**

+  * @brief Clear Stream 1 transfer complete flag.

+  * @rmtoll LIFCR  CTCIF1    LL_DMA_ClearFlag_TC1

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF1);

+}

+

+/**

+  * @brief Clear Stream 2 transfer complete flag.

+  * @rmtoll LIFCR  CTCIF2    LL_DMA_ClearFlag_TC2

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF2);

+}

+

+/**

+  * @brief Clear Stream 3 transfer complete flag.

+  * @rmtoll LIFCR  CTCIF3    LL_DMA_ClearFlag_TC3

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTCIF3);

+}

+

+/**

+  * @brief Clear Stream 4 transfer complete flag.

+  * @rmtoll HIFCR  CTCIF4    LL_DMA_ClearFlag_TC4

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF4);

+}

+

+/**

+  * @brief Clear Stream 5 transfer complete flag.

+  * @rmtoll HIFCR  CTCIF5    LL_DMA_ClearFlag_TC5

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF5);

+}

+

+/**

+  * @brief Clear Stream 6 transfer complete flag.

+  * @rmtoll HIFCR  CTCIF6    LL_DMA_ClearFlag_TC6

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF6);

+}

+

+/**

+  * @brief Clear Stream 7 transfer complete flag.

+  * @rmtoll HIFCR  CTCIF7    LL_DMA_ClearFlag_TC7

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTCIF7);

+}

+

+/**

+  * @brief Clear Stream 0 transfer error flag.

+  * @rmtoll LIFCR  CTEIF0    LL_DMA_ClearFlag_TE0

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF0);

+}

+

+/**

+  * @brief Clear Stream 1 transfer error flag.

+  * @rmtoll LIFCR  CTEIF1    LL_DMA_ClearFlag_TE1

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF1);

+}

+

+/**

+  * @brief Clear Stream 2 transfer error flag.

+  * @rmtoll LIFCR  CTEIF2    LL_DMA_ClearFlag_TE2

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF2);

+}

+

+/**

+  * @brief Clear Stream 3 transfer error flag.

+  * @rmtoll LIFCR  CTEIF3    LL_DMA_ClearFlag_TE3

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CTEIF3);

+}

+

+/**

+  * @brief Clear Stream 4 transfer error flag.

+  * @rmtoll HIFCR  CTEIF4    LL_DMA_ClearFlag_TE4

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF4);

+}

+

+/**

+  * @brief Clear Stream 5 transfer error flag.

+  * @rmtoll HIFCR  CTEIF5    LL_DMA_ClearFlag_TE5

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF5);

+}

+

+/**

+  * @brief Clear Stream 6 transfer error flag.

+  * @rmtoll HIFCR  CTEIF6    LL_DMA_ClearFlag_TE6

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF6);

+}

+

+/**

+  * @brief Clear Stream 7 transfer error flag.

+  * @rmtoll HIFCR  CTEIF7    LL_DMA_ClearFlag_TE7

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CTEIF7);

+}

+

+/**

+  * @brief Clear Stream 0 direct mode error flag.

+  * @rmtoll LIFCR  CDMEIF0    LL_DMA_ClearFlag_DME0

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF0);

+}

+

+/**

+  * @brief Clear Stream 1 direct mode error flag.

+  * @rmtoll LIFCR  CDMEIF1    LL_DMA_ClearFlag_DME1

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF1);

+}

+

+/**

+  * @brief Clear Stream 2 direct mode error flag.

+  * @rmtoll LIFCR  CDMEIF2    LL_DMA_ClearFlag_DME2

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF2);

+}

+

+/**

+  * @brief Clear Stream 3 direct mode error flag.

+  * @rmtoll LIFCR  CDMEIF3    LL_DMA_ClearFlag_DME3

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CDMEIF3);

+}

+

+/**

+  * @brief Clear Stream 4 direct mode error flag.

+  * @rmtoll HIFCR  CDMEIF4    LL_DMA_ClearFlag_DME4

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF4);

+}

+

+/**

+  * @brief Clear Stream 5 direct mode error flag.

+  * @rmtoll HIFCR  CDMEIF5    LL_DMA_ClearFlag_DME5

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF5);

+}

+

+/**

+  * @brief Clear Stream 6 direct mode error flag.

+  * @rmtoll HIFCR  CDMEIF6    LL_DMA_ClearFlag_DME6

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF6);

+}

+

+/**

+  * @brief Clear Stream 7 direct mode error flag.

+  * @rmtoll HIFCR  CDMEIF7    LL_DMA_ClearFlag_DME7

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CDMEIF7);

+}

+

+/**

+  * @brief Clear Stream 0 FIFO error flag.

+  * @rmtoll LIFCR  CFEIF0    LL_DMA_ClearFlag_FE0

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF0);

+}

+

+/**

+  * @brief Clear Stream 1 FIFO error flag.

+  * @rmtoll LIFCR  CFEIF1    LL_DMA_ClearFlag_FE1

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF1);

+}

+

+/**

+  * @brief Clear Stream 2 FIFO error flag.

+  * @rmtoll LIFCR  CFEIF2    LL_DMA_ClearFlag_FE2

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF2);

+}

+

+/**

+  * @brief Clear Stream 3 FIFO error flag.

+  * @rmtoll LIFCR  CFEIF3    LL_DMA_ClearFlag_FE3

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->LIFCR, DMA_LIFCR_CFEIF3);

+}

+

+/**

+  * @brief Clear Stream 4 FIFO error flag.

+  * @rmtoll HIFCR  CFEIF4    LL_DMA_ClearFlag_FE4

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF4);

+}

+

+/**

+  * @brief Clear Stream 5 FIFO error flag.

+  * @rmtoll HIFCR  CFEIF5    LL_DMA_ClearFlag_FE5

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF5);

+}

+

+/**

+  * @brief Clear Stream 6 FIFO error flag.

+  * @rmtoll HIFCR  CFEIF6    LL_DMA_ClearFlag_FE6

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF6);

+}

+

+/**

+  * @brief Clear Stream 7 FIFO error flag.

+  * @rmtoll HIFCR  CFEIF7    LL_DMA_ClearFlag_FE7

+  * @param  DMAx DMAx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)

+{

+  WRITE_REG(DMAx->HIFCR, DMA_HIFCR_CFEIF7);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup DMA_LL_EF_IT_Management IT_Management

+  * @{

+  */

+

+/**

+  * @brief Enable Half transfer interrupt.

+  * @rmtoll CR        HTIE         LL_DMA_EnableIT_HT

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE);

+}

+

+/**

+  * @brief Enable Transfer error interrupt.

+  * @rmtoll CR        TEIE         LL_DMA_EnableIT_TE

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE);

+}

+

+/**

+  * @brief Enable Transfer complete interrupt.

+  * @rmtoll CR        TCIE         LL_DMA_EnableIT_TC

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE);

+}

+

+/**

+  * @brief Enable Direct mode error interrupt.

+  * @rmtoll CR        DMEIE         LL_DMA_EnableIT_DME

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE);

+}

+

+/**

+  * @brief Enable FIFO error interrupt.

+  * @rmtoll FCR        FEIE         LL_DMA_EnableIT_FE

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE);

+}

+

+/**

+  * @brief Disable Half transfer interrupt.

+  * @rmtoll CR        HTIE         LL_DMA_DisableIT_HT

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE);

+}

+

+/**

+  * @brief Disable Transfer error interrupt.

+  * @rmtoll CR        TEIE         LL_DMA_DisableIT_TE

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE);

+}

+

+/**

+  * @brief Disable Transfer complete interrupt.

+  * @rmtoll CR        TCIE         LL_DMA_DisableIT_TC

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE);

+}

+

+/**

+  * @brief Disable Direct mode error interrupt.

+  * @rmtoll CR        DMEIE         LL_DMA_DisableIT_DME

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE);

+}

+

+/**

+  * @brief Disable FIFO error interrupt.

+  * @rmtoll FCR        FEIE         LL_DMA_DisableIT_FE

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE);

+}

+

+/**

+  * @brief Check if Half transfer interrup is enabled.

+  * @rmtoll CR        HTIE         LL_DMA_IsEnabledIT_HT

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Check if Transfer error nterrup is enabled.

+  * @rmtoll CR        TEIE         LL_DMA_IsEnabledIT_TE

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Check if Transfer complete interrup is enabled.

+  * @rmtoll CR        TCIE         LL_DMA_IsEnabledIT_TC

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Check if Direct mode error interrupt is enabled.

+  * @rmtoll CR        DMEIE         LL_DMA_IsEnabledIT_DME

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Check if FIFO error interrup is enabled.

+  * @rmtoll FCR        FEIE         LL_DMA_IsEnabledIT_FE

+  * @param  DMAx DMAx Instance

+  * @param  Stream This parameter can be one of the following values:

+  *         @arg @ref LL_DMA_STREAM_0

+  *         @arg @ref LL_DMA_STREAM_1

+  *         @arg @ref LL_DMA_STREAM_2

+  *         @arg @ref LL_DMA_STREAM_3

+  *         @arg @ref LL_DMA_STREAM_4

+  *         @arg @ref LL_DMA_STREAM_5

+  *         @arg @ref LL_DMA_STREAM_6

+  *         @arg @ref LL_DMA_STREAM_7

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)

+{

+  register uint32_t dma_base_addr = (uint32_t)DMAx;

+

+  return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions

+  * @{

+  */

+

+uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct);

+uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream);

+void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);

+

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* DMA1 || DMA2 */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* __STM32H7xx_LL_DMA_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_dma2d.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_dma2d.h
new file mode 100644
index 0000000000..abfaa1f879
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_dma2d.h
@@ -0,0 +1,2174 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_dma2d.h

+  * @author  MCD Application Team

+  * @brief   Header file of DMA2D LL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_LL_DMA2D_H

+#define STM32H7xx_LL_DMA2D_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+#if defined (DMA2D)

+

+/** @defgroup DMA2D_LL DMA2D

+  * @{

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/* Private macros ------------------------------------------------------------*/

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup DMA2D_LL_Private_Macros DMA2D Private Macros

+  * @{

+  */

+

+/**

+  * @}

+  */

+#endif /*USE_FULL_LL_DRIVER*/

+

+/* Exported types ------------------------------------------------------------*/

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup DMA2D_LL_ES_Init_Struct DMA2D Exported Init structures

+  * @{

+  */

+

+/**

+  * @brief LL DMA2D Init Structure Definition

+  */

+typedef struct

+{

+  uint32_t Mode;                 /*!< Specifies the DMA2D transfer mode.

+                                      - This parameter can be one value of @ref DMA2D_LL_EC_MODE.

+

+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetMode().*/

+

+  uint32_t ColorMode;            /*!< Specifies the color format of the output image.

+                                      - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.

+

+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */

+

+  uint32_t OutputBlue;           /*!< Specifies the Blue value of the output image.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.

+

+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration

+                                      function @ref LL_DMA2D_ConfigOutputColor(). */

+

+  uint32_t OutputGreen;          /*!< Specifies the Green value of the output image.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.

+

+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration

+                                      function @ref LL_DMA2D_ConfigOutputColor(). */

+

+  uint32_t OutputRed;            /*!< Specifies the Red value of the output image.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.

+

+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration

+                                      function @ref LL_DMA2D_ConfigOutputColor(). */

+

+  uint32_t OutputAlpha;          /*!< Specifies the Alpha channel of the output image.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.

+                                      - This parameter is not considered if RGB888 or RGB565 color mode is selected.

+

+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration

+                                      function @ref LL_DMA2D_ConfigOutputColor(). */

+

+  uint32_t OutputMemoryAddress;  /*!< Specifies the memory address.

+                                      - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.

+

+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */

+

+  uint32_t OutputSwapMode;             /*!< Specifies the output swap mode color format of the output image.

+                                      - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_SWAP_MODE.

+

+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputSwapMode(). */

+

+  uint32_t LineOffsetMode;       /*!< Specifies the output line offset mode.

+                                      - This parameter can be one value of @ref DMA2D_LL_EC_LINE_OFFSET_MODE.

+

+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffsetMode(). */

+

+  uint32_t LineOffset;           /*!< Specifies the output line offset value.

+                                      - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

+

+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffset(). */

+

+  uint32_t NbrOfLines;           /*!< Specifies the number of lines of the area to be transferred.

+                                      - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

+

+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfLines(). */

+

+  uint32_t NbrOfPixelsPerLines;  /*!< Specifies the number of pixels per lines of the area to be transfered.

+                                      - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.

+

+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */

+

+  uint32_t AlphaInversionMode;   /*!< Specifies the output alpha inversion mode.

+                                      - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.

+

+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */

+

+  uint32_t RBSwapMode;           /*!< Specifies the output Red Blue swap mode.

+                                      - This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP.

+

+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */

+

+} LL_DMA2D_InitTypeDef;

+

+/**

+  * @brief LL DMA2D Layer Configuration Structure Definition

+  */

+typedef struct

+{

+  uint32_t MemoryAddress;        /*!< Specifies the foreground or background memory address.

+                                      - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.

+

+                                      This parameter can be modified afterwards using unitary functions

+                                      - @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer,

+                                      - @ref LL_DMA2D_BGND_SetMemAddr() for background layer. */

+

+  uint32_t LineOffset;           /*!< Specifies the foreground or background line offset value.

+                                      - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.

+

+                                      This parameter can be modified afterwards using unitary functions

+                                      - @ref LL_DMA2D_FGND_SetLineOffset() for foreground layer,

+                                      - @ref LL_DMA2D_BGND_SetLineOffset() for background layer. */

+

+  uint32_t ColorMode;            /*!< Specifies the foreground or background color mode.

+                                      - This parameter can be one value of @ref DMA2D_LL_EC_INPUT_COLOR_MODE.

+

+                                      This parameter can be modified afterwards using unitary functions

+                                      - @ref LL_DMA2D_FGND_SetColorMode() for foreground layer,

+                                      - @ref LL_DMA2D_BGND_SetColorMode() for background layer. */

+

+  uint32_t CLUTColorMode;        /*!< Specifies the foreground or background CLUT color mode.

+                                       - This parameter can be one value of @ref DMA2D_LL_EC_CLUT_COLOR_MODE.

+

+                                      This parameter can be modified afterwards using unitary functions

+                                      - @ref LL_DMA2D_FGND_SetCLUTColorMode() for foreground layer,

+                                      - @ref LL_DMA2D_BGND_SetCLUTColorMode() for background layer. */

+

+  uint32_t CLUTSize;             /*!< Specifies the foreground or background CLUT size.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

+

+                                      This parameter can be modified afterwards using unitary functions

+                                      - @ref LL_DMA2D_FGND_SetCLUTSize() for foreground layer,

+                                      - @ref LL_DMA2D_BGND_SetCLUTSize() for background layer. */

+

+  uint32_t AlphaMode;            /*!< Specifies the foreground or background alpha mode.

+                                       - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_MODE.

+

+                                      This parameter can be modified afterwards using unitary functions

+                                      - @ref LL_DMA2D_FGND_SetAlphaMode() for foreground layer,

+                                      - @ref LL_DMA2D_BGND_SetAlphaMode() for background layer. */

+

+  uint32_t Alpha;                /*!< Specifies the foreground or background Alpha value.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

+

+                                      This parameter can be modified afterwards using unitary functions

+                                      - @ref LL_DMA2D_FGND_SetAlpha() for foreground layer,

+                                      - @ref LL_DMA2D_BGND_SetAlpha() for background layer. */

+

+  uint32_t Blue;                 /*!< Specifies the foreground or background Blue color value.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

+

+                                      This parameter can be modified afterwards using unitary functions

+                                      - @ref LL_DMA2D_FGND_SetBlueColor() for foreground layer,

+                                      - @ref LL_DMA2D_BGND_SetBlueColor() for background layer. */

+

+  uint32_t Green;                /*!< Specifies the foreground or background Green color value.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

+

+                                      This parameter can be modified afterwards using unitary functions

+                                      - @ref LL_DMA2D_FGND_SetGreenColor() for foreground layer,

+                                      - @ref LL_DMA2D_BGND_SetGreenColor() for background layer. */

+

+  uint32_t Red;                  /*!< Specifies the foreground or background Red color value.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

+

+                                      This parameter can be modified afterwards using unitary functions

+                                      - @ref LL_DMA2D_FGND_SetRedColor() for foreground layer,

+                                      - @ref LL_DMA2D_BGND_SetRedColor() for background layer. */

+

+  uint32_t CLUTMemoryAddress;    /*!< Specifies the foreground or background CLUT memory address.

+                                      - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.

+

+                                      This parameter can be modified afterwards using unitary functions

+                                      - @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer,

+                                      - @ref LL_DMA2D_BGND_SetCLUTMemAddr() for background layer. */

+

+  uint32_t AlphaInversionMode;   /*!< Specifies the foreground or background alpha inversion mode.

+                                      - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.

+

+                                      This parameter can be modified afterwards using unitary functions

+                                      - @ref LL_DMA2D_FGND_SetAlphaInvMode() for foreground layer,

+                                      - @ref LL_DMA2D_BGND_SetAlphaInvMode() for background layer. */

+

+  uint32_t RBSwapMode;           /*!< Specifies the foreground or background Red Blue swap mode.

+                                      This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP .

+

+                                      This parameter can be modified afterwards using unitary functions

+                                      - @ref LL_DMA2D_FGND_SetRBSwapMode() for foreground layer,

+                                      - @ref LL_DMA2D_BGND_SetRBSwapMode() for background layer. */

+

+  uint32_t ChromaSubSampling;   /*!< Configure the chroma sub-sampling mode for the YCbCr color mode

+                                     This parameter is applicable for foreground layer only.

+                                     This parameter can be one value of @ref DMA2D_LL_CHROMA_SUB_SAMPLING

+

+                                     This parameter can be modified afterwards using unitary functions

+                                     - @ref LL_DMA2D_FGND_SetChrSubSampling() for foreground layer. */

+

+} LL_DMA2D_LayerCfgTypeDef;

+

+/**

+  * @brief LL DMA2D Output Color Structure Definition

+  */

+typedef struct

+{

+  uint32_t ColorMode;            /*!< Specifies the color format of the output image.

+                                      - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.

+

+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */

+

+  uint32_t OutputBlue;           /*!< Specifies the Blue value of the output image.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.

+

+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration

+                                      function @ref LL_DMA2D_ConfigOutputColor(). */

+

+  uint32_t OutputGreen;          /*!< Specifies the Green value of the output image.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.

+

+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration

+                                      function @ref LL_DMA2D_ConfigOutputColor(). */

+

+  uint32_t OutputRed;            /*!< Specifies the Red value of the output image.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.

+

+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration

+                                      function @ref LL_DMA2D_ConfigOutputColor(). */

+

+  uint32_t OutputAlpha;          /*!< Specifies the Alpha channel of the output image.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.

+                                      - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.

+                                      - This parameter is not considered if RGB888 or RGB565 color mode is selected.

+

+                                      This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration

+                                      function @ref LL_DMA2D_ConfigOutputColor(). */

+

+} LL_DMA2D_ColorTypeDef;

+

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup DMA2D_LL_Exported_Constants DMA2D Exported Constants

+  * @{

+  */

+

+/** @defgroup DMA2D_LL_EC_GET_FLAG Get Flags Defines

+  * @brief    Flags defines which can be used with LL_DMA2D_ReadReg function

+  * @{

+  */

+#define LL_DMA2D_FLAG_CEIF          DMA2D_ISR_CEIF     /*!< Configuration Error Interrupt Flag */

+#define LL_DMA2D_FLAG_CTCIF         DMA2D_ISR_CTCIF    /*!< CLUT Transfer Complete Interrupt Flag */

+#define LL_DMA2D_FLAG_CAEIF         DMA2D_ISR_CAEIF    /*!< CLUT Access Error Interrupt Flag */

+#define LL_DMA2D_FLAG_TWIF          DMA2D_ISR_TWIF     /*!< Transfer Watermark Interrupt Flag */

+#define LL_DMA2D_FLAG_TCIF          DMA2D_ISR_TCIF     /*!< Transfer Complete Interrupt Flag */

+#define LL_DMA2D_FLAG_TEIF          DMA2D_ISR_TEIF     /*!< Transfer Error Interrupt Flag */

+/**

+  * @}

+  */

+

+/** @defgroup DMA2D_LL_EC_IT IT Defines

+  * @brief    IT defines which can be used with LL_DMA2D_ReadReg and  LL_DMA2D_WriteReg functions

+  * @{

+  */

+#define LL_DMA2D_IT_CEIE             DMA2D_CR_CEIE    /*!< Configuration Error Interrupt */

+#define LL_DMA2D_IT_CTCIE            DMA2D_CR_CTCIE   /*!< CLUT Transfer Complete Interrupt */

+#define LL_DMA2D_IT_CAEIE            DMA2D_CR_CAEIE   /*!< CLUT Access Error Interrupt */

+#define LL_DMA2D_IT_TWIE             DMA2D_CR_TWIE    /*!< Transfer Watermark Interrupt */

+#define LL_DMA2D_IT_TCIE             DMA2D_CR_TCIE    /*!< Transfer Complete Interrupt */

+#define LL_DMA2D_IT_TEIE             DMA2D_CR_TEIE    /*!< Transfer Error Interrupt */

+/**

+  * @}

+  */

+

+/** @defgroup DMA2D_LL_EC_MODE Mode

+  * @{

+  */

+#define LL_DMA2D_MODE_M2M                       0x00000000U                       /*!< DMA2D memory to memory transfer mode */

+#define LL_DMA2D_MODE_M2M_PFC                   DMA2D_CR_MODE_0                   /*!< DMA2D memory to memory with pixel format conversion transfer mode */

+#define LL_DMA2D_MODE_M2M_BLEND                 DMA2D_CR_MODE_1                   /*!< DMA2D memory to memory with blending transfer mode */

+#define LL_DMA2D_MODE_R2M                       (DMA2D_CR_MODE_0|DMA2D_CR_MODE_1) /*!< DMA2D register to memory transfer mode */

+#define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG  DMA2D_CR_MODE_2                   /*!< DMA2D memory to memory with blending transfer mode and fixed color foreground */

+#define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG  (DMA2D_CR_MODE_0|DMA2D_CR_MODE_2) /*!< DMA2D memory to memory with blending transfer mode and fixed color background */

+/**

+  * @}

+  */

+

+/** @defgroup DMA2D_LL_EC_OUTPUT_COLOR_MODE Output Color Mode

+  * @{

+  */

+#define LL_DMA2D_OUTPUT_MODE_ARGB8888     0x00000000U                           /*!< ARGB8888 */

+#define LL_DMA2D_OUTPUT_MODE_RGB888       DMA2D_OPFCCR_CM_0                     /*!< RGB888   */

+#define LL_DMA2D_OUTPUT_MODE_RGB565       DMA2D_OPFCCR_CM_1                     /*!< RGB565   */

+#define LL_DMA2D_OUTPUT_MODE_ARGB1555     (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 */

+#define LL_DMA2D_OUTPUT_MODE_ARGB4444     DMA2D_OPFCCR_CM_2                     /*!< ARGB4444 */

+/**

+  * @}

+  */

+

+/** @defgroup DMA2D_LL_EC_INPUT_COLOR_MODE Input Color Mode

+  * @{

+  */

+#define LL_DMA2D_INPUT_MODE_ARGB8888      0x00000000U                                                /*!< ARGB8888 */

+#define LL_DMA2D_INPUT_MODE_RGB888        DMA2D_FGPFCCR_CM_0                                         /*!< RGB888   */

+#define LL_DMA2D_INPUT_MODE_RGB565        DMA2D_FGPFCCR_CM_1                                         /*!< RGB565   */

+#define LL_DMA2D_INPUT_MODE_ARGB1555      (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1)                    /*!< ARGB1555 */

+#define LL_DMA2D_INPUT_MODE_ARGB4444      DMA2D_FGPFCCR_CM_2                                         /*!< ARGB4444 */

+#define LL_DMA2D_INPUT_MODE_L8            (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2)                    /*!< L8       */

+#define LL_DMA2D_INPUT_MODE_AL44          (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2)                    /*!< AL44     */

+#define LL_DMA2D_INPUT_MODE_AL88          (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL88     */

+#define LL_DMA2D_INPUT_MODE_L4            DMA2D_FGPFCCR_CM_3                                         /*!< L4       */

+#define LL_DMA2D_INPUT_MODE_A8            (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3)                    /*!< A8       */

+#define LL_DMA2D_INPUT_MODE_A4            (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3)                    /*!< A4       */

+#define LL_DMA2D_INPUT_MODE_YCBCR         (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< YCbCr    */

+/**

+  * @}

+  */

+

+/** @defgroup DMA2D_LL_EC_ALPHA_MODE Alpha Mode

+  * @{

+  */

+#define LL_DMA2D_ALPHA_MODE_NO_MODIF       0x00000000U             /*!< No modification of the alpha channel value */

+#define LL_DMA2D_ALPHA_MODE_REPLACE        DMA2D_FGPFCCR_AM_0      /*!< Replace original alpha channel value by programmed alpha value */

+#define LL_DMA2D_ALPHA_MODE_COMBINE        DMA2D_FGPFCCR_AM_1      /*!< Replace original alpha channel value by programmed alpha value

+                                                                   with original alpha channel value                              */

+/**

+  * @}

+  */

+

+/** @defgroup DMA2D_LL_EC_OUTPUT_SWAP_MODE Swap Mode

+  * @{

+  */

+#define LL_DMA2D_SWAP_MODE_REGULAR        0x00000000U                      /*!< Regular order */

+#define LL_DMA2D_SWAP_MODE_TWO_BY_TWO     DMA2D_OPFCCR_SB                  /*!< Bytes swapped two by two */

+/**

+  * @}

+  */

+

+/** @defgroup DMA2D_LL_EC_RED_BLUE_SWAP Red Blue Swap

+  * @{

+  */

+#define LL_DMA2D_RB_MODE_REGULAR          0x00000000U                      /*!< RGB or ARGB */

+#define LL_DMA2D_RB_MODE_SWAP             DMA2D_FGPFCCR_RBS                /*!< BGR or ABGR */

+/**

+  * @}

+  */

+

+/** @defgroup DMA2D_LL_EC_ALPHA_INVERSION Alpha Inversion

+  * @{

+  */

+#define LL_DMA2D_ALPHA_REGULAR          0x00000000U                     /*!< Regular alpha  */

+#define LL_DMA2D_ALPHA_INVERTED         DMA2D_FGPFCCR_AI                /*!< Inverted alpha */

+/**

+  * @}

+  */

+

+

+/** @defgroup DMA2D_LL_EC_LINE_OFFSET_MODE Line Offset Mode

+  * @{

+  */

+#define LL_DMA2D_LINE_OFFSET_PIXELS     0x00000000U                     /*!< Line offsets are expressed in pixels  */

+#define LL_DMA2D_LINE_OFFSET_BYTES      DMA2D_CR_LOM                    /*!< Line offsets are expressed in bytes   */

+/**

+  * @}

+  */

+

+/** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode

+  * @{

+  */

+#define LL_DMA2D_CLUT_COLOR_MODE_ARGB8888          0x00000000U                     /*!< ARGB8888 */

+#define LL_DMA2D_CLUT_COLOR_MODE_RGB888            DMA2D_FGPFCCR_CCM               /*!< RGB888   */

+/**

+  * @}

+  */

+

+/** @defgroup DMA2D_LL_CHROMA_SUB_SAMPLING Chroma Sub Sampling

+  * @{

+  */

+#define LL_DMA2D_CSS_444              0x00000000U             /*!< No chroma sub-sampling 4:4:4 */

+#define LL_DMA2D_CSS_422              DMA2D_FGPFCCR_CSS_0     /*!< chroma sub-sampling 4:2:2 */

+#define LL_DMA2D_CSS_420              DMA2D_FGPFCCR_CSS_1     /*!< chroma sub-sampling 4:2:0 */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup DMA2D_LL_Exported_Macros DMA2D Exported Macros

+  * @{

+  */

+

+/** @defgroup DMA2D_LL_EM_WRITE_READ Common Write and read registers Macros

+  * @{

+  */

+

+/**

+  * @brief  Write a value in DMA2D register.

+  * @param  __INSTANCE__ DMA2D Instance

+  * @param  __REG__ Register to be written

+  * @param  __VALUE__ Value to be written in the register

+  * @retval None

+  */

+#define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))

+

+/**

+  * @brief  Read a value in DMA2D register.

+  * @param  __INSTANCE__ DMA2D Instance

+  * @param  __REG__ Register to be read

+  * @retval Register value

+  */

+#define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup DMA2D_LL_Exported_Functions DMA2D Exported Functions

+  * @{

+  */

+

+/** @defgroup DMA2D_LL_EF_Configuration Configuration Functions

+  * @{

+  */

+

+/**

+  * @brief  Start a DMA2D transfer.

+  * @rmtoll CR          START            LL_DMA2D_Start

+  * @param  DMA2Dx DMA2D Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx)

+{

+  SET_BIT(DMA2Dx->CR, DMA2D_CR_START);

+}

+

+/**

+  * @brief  Indicate if a DMA2D transfer is ongoing.

+  * @rmtoll CR          START            LL_DMA2D_IsTransferOngoing

+  * @param  DMA2Dx DMA2D Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx)

+{

+  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Suspend DMA2D transfer.

+  * @note   This API can be used to suspend automatic foreground or background CLUT loading.

+  * @rmtoll CR          SUSP            LL_DMA2D_Suspend

+  * @param  DMA2Dx DMA2D Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_Suspend(DMA2D_TypeDef *DMA2Dx)

+{

+  MODIFY_REG(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);

+}

+

+/**

+  * @brief  Resume DMA2D transfer.

+  * @note   This API can be used to resume automatic foreground or background CLUT loading.

+  * @rmtoll CR          SUSP            LL_DMA2D_Resume

+  * @param  DMA2Dx DMA2D Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx)

+{

+  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START);

+}

+

+/**

+  * @brief  Indicate if DMA2D transfer is suspended.

+  * @note   This API can be used to indicate whether or not automatic foreground or

+  *         background CLUT loading is suspended.

+  * @rmtoll CR          SUSP            LL_DMA2D_IsSuspended

+  * @param  DMA2Dx DMA2D Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx)

+{

+  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Abort DMA2D transfer.

+  * @note   This API can be used to abort automatic foreground or background CLUT loading.

+  * @rmtoll CR          ABORT            LL_DMA2D_Abort

+  * @param  DMA2Dx DMA2D Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx)

+{

+  MODIFY_REG(DMA2Dx->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);

+}

+

+/**

+  * @brief  Indicate if DMA2D transfer is aborted.

+  * @note   This API can be used to indicate whether or not automatic foreground or

+  *         background CLUT loading is aborted.

+  * @rmtoll CR          ABORT            LL_DMA2D_IsAborted

+  * @param  DMA2Dx DMA2D Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx)

+{

+  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set DMA2D mode.

+  * @rmtoll CR          MODE          LL_DMA2D_SetMode

+  * @param  DMA2Dx DMA2D Instance

+  * @param  Mode This parameter can be one of the following values:

+  *         @arg @ref LL_DMA2D_MODE_M2M

+  *         @arg @ref LL_DMA2D_MODE_M2M_PFC

+  *         @arg @ref LL_DMA2D_MODE_M2M_BLEND

+  *         @arg @ref LL_DMA2D_MODE_R2M

+  *         @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG

+  *         @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode)

+{

+  MODIFY_REG(DMA2Dx->CR, DMA2D_CR_MODE, Mode);

+}

+

+/**

+  * @brief  Return DMA2D mode

+  * @rmtoll CR          MODE         LL_DMA2D_GetMode

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMA2D_MODE_M2M

+  *         @arg @ref LL_DMA2D_MODE_M2M_PFC

+  *         @arg @ref LL_DMA2D_MODE_M2M_BLEND

+  *         @arg @ref LL_DMA2D_MODE_R2M

+  *         @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG

+  *         @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE));

+}

+

+/**

+  * @brief  Set DMA2D output color mode.

+  * @rmtoll OPFCCR          CM          LL_DMA2D_SetOutputColorMode

+  * @param  DMA2Dx DMA2D Instance

+  * @param  ColorMode This parameter can be one of the following values:

+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888

+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888

+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565

+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555

+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)

+{

+  MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, ColorMode);

+}

+

+/**

+  * @brief  Return DMA2D output color mode.

+  * @rmtoll OPFCCR          CM         LL_DMA2D_GetOutputColorMode

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888

+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888

+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565

+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555

+  *         @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM));

+}

+

+/**

+  * @brief  Set DMA2D output Red Blue swap mode.

+  * @rmtoll OPFCCR          RBS          LL_DMA2D_SetOutputRBSwapMode

+  * @param  DMA2Dx DMA2D Instance

+  * @param  RBSwapMode This parameter can be one of the following values:

+  *         @arg @ref LL_DMA2D_RB_MODE_REGULAR

+  *         @arg @ref LL_DMA2D_RB_MODE_SWAP

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)

+{

+  MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS, RBSwapMode);

+}

+

+/**

+  * @brief  Return DMA2D output Red Blue swap mode.

+  * @rmtoll OPFCCR          RBS         LL_DMA2D_GetOutputRBSwapMode

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMA2D_RB_MODE_REGULAR

+  *         @arg @ref LL_DMA2D_RB_MODE_SWAP

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS));

+}

+

+/**

+  * @brief  Set DMA2D output alpha inversion mode.

+  * @rmtoll OPFCCR          AI          LL_DMA2D_SetOutputAlphaInvMode

+  * @param  DMA2Dx DMA2D Instance

+  * @param  AlphaInversionMode This parameter can be one of the following values:

+  *         @arg @ref LL_DMA2D_ALPHA_REGULAR

+  *         @arg @ref LL_DMA2D_ALPHA_INVERTED

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)

+{

+  MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI, AlphaInversionMode);

+}

+

+/**

+  * @brief  Return DMA2D output alpha inversion mode.

+  * @rmtoll OPFCCR          AI         LL_DMA2D_GetOutputAlphaInvMode

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMA2D_ALPHA_REGULAR

+  *         @arg @ref LL_DMA2D_ALPHA_INVERTED

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI));

+}

+

+

+/**

+  * @brief  Set DMA2D output swap mode.

+  * @rmtoll OPFCCR          SB          LL_DMA2D_SetOutputSwapMode

+  * @param  DMA2Dx DMA2D Instance

+  * @param  OutputSwapMode This parameter can be one of the following values:

+  *         @arg @ref LL_DMA2D_SWAP_MODE_REGULAR

+  *         @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_SetOutputSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t OutputSwapMode)

+{

+  MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB, OutputSwapMode);

+}

+

+/**

+  * @brief  Return DMA2D output swap mode.

+  * @rmtoll OPFCCR          SB         LL_DMA2D_GetOutputSwapMode

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMA2D_SWAP_MODE_REGULAR

+  *         @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB));

+}

+

+/**

+  * @brief  Set DMA2D line offset mode.

+  * @rmtoll CR          LOM          LL_DMA2D_SetLineOffsetMode

+  * @param  DMA2Dx DMA2D Instance

+  * @param  LineOffsetMode This parameter can be one of the following values:

+  *         @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS

+  *         @arg @ref LL_DMA2D_LINE_OFFSET_BYTES

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffsetMode)

+{

+  MODIFY_REG(DMA2Dx->CR, DMA2D_CR_LOM, LineOffsetMode);

+}

+

+/**

+  * @brief  Return DMA2D line offset mode.

+  * @rmtoll CR          LOM         LL_DMA2D_GetLineOffsetMode

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS

+  *         @arg @ref LL_DMA2D_LINE_OFFSET_BYTES

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_LOM));

+}

+

+/**

+  * @brief  Set DMA2D line offset, expressed on 14 bits ([13:0] bits).

+  * @rmtoll OOR          LO          LL_DMA2D_SetLineOffset

+  * @param  DMA2Dx DMA2D Instance

+  * @param  LineOffset Value between Min_Data=0 and Max_Data=0xFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)

+{

+  MODIFY_REG(DMA2Dx->OOR, DMA2D_OOR_LO, LineOffset);

+}

+

+/**

+  * @brief  Return DMA2D line offset, expressed on 14 bits ([13:0] bits).

+  * @rmtoll OOR          LO         LL_DMA2D_GetLineOffset

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Line offset value between Min_Data=0 and Max_Data=0xFFFF

+  @endif

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO));

+}

+

+/**

+  * @brief  Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits).

+  * @rmtoll NLR          PL          LL_DMA2D_SetNbrOfPixelsPerLines

+  * @param  DMA2Dx DMA2D Instance

+  * @param  NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines)

+{

+  MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_PL, (NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos));

+}

+

+/**

+  * @brief  Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits)

+  * @rmtoll NLR          PL          LL_DMA2D_GetNbrOfPixelsPerLines

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos);

+}

+

+/**

+  * @brief  Set DMA2D number of lines, expressed on 16 bits ([15:0] bits).

+  * @rmtoll NLR          NL          LL_DMA2D_SetNbrOfLines

+  * @param  DMA2Dx DMA2D Instance

+  * @param  NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines)

+{

+  MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_NL, NbrOfLines);

+}

+

+/**

+  * @brief  Return DMA2D number of lines, expressed on 16 bits ([15:0] bits).

+  * @rmtoll NLR          NL          LL_DMA2D_GetNbrOfLines

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL));

+}

+

+/**

+  * @brief  Set DMA2D output memory address, expressed on 32 bits ([31:0] bits).

+  * @rmtoll OMAR          MA          LL_DMA2D_SetOutputMemAddr

+  * @param  DMA2Dx DMA2D Instance

+  * @param  OutputMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress)

+{

+  LL_DMA2D_WriteReg(DMA2Dx, OMAR, OutputMemoryAddress);

+}

+

+/**

+  * @brief  Get DMA2D output memory address, expressed on 32 bits ([31:0] bits).

+  * @rmtoll OMAR          MA          LL_DMA2D_GetOutputMemAddr

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR));

+}

+

+/**

+  * @brief  Set DMA2D output color, expressed on 32 bits ([31:0] bits).

+  * @note   Output color format depends on output color mode, ARGB8888, RGB888,

+  *         RGB565, ARGB1555 or ARGB4444.

+  * @note LL_DMA2D_ConfigOutputColor() API may be used instead if colors values formatting

+  *       with respect to color mode is not done by the user code.

+  * @rmtoll OCOLR        BLUE        LL_DMA2D_SetOutputColor\n

+  *         OCOLR        GREEN       LL_DMA2D_SetOutputColor\n

+  *         OCOLR        RED         LL_DMA2D_SetOutputColor\n

+  *         OCOLR        ALPHA       LL_DMA2D_SetOutputColor

+  * @param  DMA2Dx DMA2D Instance

+  * @param  OutputColor Value between Min_Data=0 and Max_Data=0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor)

+{

+  MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1), \

+             OutputColor);

+}

+

+/**

+  * @brief  Get DMA2D output color, expressed on 32 bits ([31:0] bits).

+  * @note   Alpha channel and red, green, blue color values must be retrieved from the returned

+  *         value based on the output color mode (ARGB8888, RGB888,  RGB565, ARGB1555 or ARGB4444)

+  *         as set by @ref LL_DMA2D_SetOutputColorMode.

+  * @rmtoll OCOLR        BLUE        LL_DMA2D_GetOutputColor\n

+  *         OCOLR        GREEN       LL_DMA2D_GetOutputColor\n

+  *         OCOLR        RED         LL_DMA2D_GetOutputColor\n

+  *         OCOLR        ALPHA       LL_DMA2D_GetOutputColor

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \

+                             (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1)));

+}

+

+/**

+  * @brief  Set DMA2D line watermark, expressed on 16 bits ([15:0] bits).

+  * @rmtoll LWR          LW          LL_DMA2D_SetLineWatermark

+  * @param  DMA2Dx DMA2D Instance

+  * @param  LineWatermark Value between Min_Data=0 and Max_Data=0xFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark)

+{

+  MODIFY_REG(DMA2Dx->LWR, DMA2D_LWR_LW, LineWatermark);

+}

+

+/**

+  * @brief  Return DMA2D line watermark, expressed on 16 bits ([15:0] bits).

+  * @rmtoll LWR          LW          LL_DMA2D_GetLineWatermark

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW));

+}

+

+/**

+  * @brief  Set DMA2D dead time, expressed on 8 bits ([7:0] bits).

+  * @rmtoll AMTCR          DT          LL_DMA2D_SetDeadTime

+  * @param  DMA2Dx DMA2D Instance

+  * @param  DeadTime Value between Min_Data=0 and Max_Data=0xFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime)

+{

+  MODIFY_REG(DMA2Dx->AMTCR, DMA2D_AMTCR_DT, (DeadTime << DMA2D_AMTCR_DT_Pos));

+}

+

+/**

+  * @brief  Return DMA2D dead time, expressed on 8 bits ([7:0] bits).

+  * @rmtoll AMTCR          DT          LL_DMA2D_GetDeadTime

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Dead time value between Min_Data=0 and Max_Data=0xFF

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos);

+}

+

+/**

+  * @brief  Enable DMA2D dead time functionality.

+  * @rmtoll AMTCR          EN            LL_DMA2D_EnableDeadTime

+  * @param  DMA2Dx DMA2D Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_EnableDeadTime(DMA2D_TypeDef *DMA2Dx)

+{

+  SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);

+}

+

+/**

+  * @brief  Disable DMA2D dead time functionality.

+  * @rmtoll AMTCR          EN            LL_DMA2D_DisableDeadTime

+  * @param  DMA2Dx DMA2D Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx)

+{

+  CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);

+}

+

+/**

+  * @brief  Indicate if DMA2D dead time functionality is enabled.

+  * @rmtoll AMTCR          EN            LL_DMA2D_IsEnabledDeadTime

+  * @param  DMA2Dx DMA2D Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx)

+{

+  return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL);

+}

+

+/** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions

+  * @{

+  */

+

+/**

+  * @brief  Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).

+  * @rmtoll FGMAR          MA          LL_DMA2D_FGND_SetMemAddr

+  * @param  DMA2Dx DMA2D Instance

+  * @param  MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)

+{

+  LL_DMA2D_WriteReg(DMA2Dx, FGMAR, MemoryAddress);

+}

+

+/**

+  * @brief  Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).

+  * @rmtoll FGMAR          MA          LL_DMA2D_FGND_GetMemAddr

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR));

+}

+

+/**

+  * @brief  Enable DMA2D foreground CLUT loading.

+  * @rmtoll FGPFCCR          START            LL_DMA2D_FGND_EnableCLUTLoad

+  * @param  DMA2Dx DMA2D Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)

+{

+  SET_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START);

+}

+

+/**

+  * @brief  Indicate if DMA2D foreground CLUT loading is enabled.

+  * @rmtoll FGPFCCR          START            LL_DMA2D_FGND_IsEnabledCLUTLoad

+  * @param  DMA2Dx DMA2D Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)

+{

+  return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set DMA2D foreground color mode.

+  * @rmtoll FGPFCCR          CM          LL_DMA2D_FGND_SetColorMode

+  * @param  DMA2Dx DMA2D Instance

+  * @param  ColorMode This parameter can be one of the following values:

+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888

+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB888

+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB565

+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555

+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444

+  *         @arg @ref LL_DMA2D_INPUT_MODE_L8

+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL44

+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL88

+  *         @arg @ref LL_DMA2D_INPUT_MODE_L4

+  *         @arg @ref LL_DMA2D_INPUT_MODE_A8

+  *         @arg @ref LL_DMA2D_INPUT_MODE_A4

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)

+{

+  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM, ColorMode);

+}

+

+/**

+  * @brief  Return DMA2D foreground color mode.

+  * @rmtoll FGPFCCR          CM         LL_DMA2D_FGND_GetColorMode

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888

+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB888

+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB565

+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555

+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444

+  *         @arg @ref LL_DMA2D_INPUT_MODE_L8

+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL44

+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL88

+  *         @arg @ref LL_DMA2D_INPUT_MODE_L4

+  *         @arg @ref LL_DMA2D_INPUT_MODE_A8

+  *         @arg @ref LL_DMA2D_INPUT_MODE_A4

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM));

+}

+

+/**

+  * @brief  Set DMA2D foreground alpha mode.

+  * @rmtoll FGPFCCR          AM          LL_DMA2D_FGND_SetAlphaMode

+  * @param  DMA2Dx DMA2D Instance

+  * @param  AphaMode This parameter can be one of the following values:

+  *         @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF

+  *         @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE

+  *         @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)

+{

+  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM, AphaMode);

+}

+

+/**

+  * @brief  Return DMA2D foreground alpha mode.

+  * @rmtoll FGPFCCR          AM         LL_DMA2D_FGND_GetAlphaMode

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF

+  *         @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE

+  *         @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM));

+}

+

+/**

+  * @brief  Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).

+  * @rmtoll FGPFCCR          ALPHA          LL_DMA2D_FGND_SetAlpha

+  * @param  DMA2Dx DMA2D Instance

+  * @param  Alpha Value between Min_Data=0 and Max_Data=0xFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)

+{

+  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA, (Alpha << DMA2D_FGPFCCR_ALPHA_Pos));

+}

+

+/**

+  * @brief  Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).

+  * @rmtoll FGPFCCR          ALPHA         LL_DMA2D_FGND_GetAlpha

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Alpha value between Min_Data=0 and Max_Data=0xFF

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos);

+}

+

+/**

+  * @brief  Set DMA2D foreground Red Blue swap mode.

+  * @rmtoll FGPFCCR          RBS          LL_DMA2D_FGND_SetRBSwapMode

+  * @param  DMA2Dx DMA2D Instance

+  * @param  RBSwapMode This parameter can be one of the following values:

+  *         @arg @ref LL_DMA2D_RB_MODE_REGULAR

+  *         @arg @ref LL_DMA2D_RB_MODE_SWAP

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)

+{

+  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS, RBSwapMode);

+}

+

+/**

+  * @brief  Return DMA2D foreground Red Blue swap mode.

+  * @rmtoll FGPFCCR          RBS         LL_DMA2D_FGND_GetRBSwapMode

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMA2D_RB_MODE_REGULAR

+  *         @arg @ref LL_DMA2D_RB_MODE_SWAP

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS));

+}

+

+/**

+  * @brief  Set DMA2D foreground alpha inversion mode.

+  * @rmtoll FGPFCCR          AI          LL_DMA2D_FGND_SetAlphaInvMode

+  * @param  DMA2Dx DMA2D Instance

+  * @param  AlphaInversionMode This parameter can be one of the following values:

+  *         @arg @ref LL_DMA2D_ALPHA_REGULAR

+  *         @arg @ref LL_DMA2D_ALPHA_INVERTED

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)

+{

+  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI, AlphaInversionMode);

+}

+

+/**

+  * @brief  Return DMA2D foreground alpha inversion mode.

+  * @rmtoll FGPFCCR          AI         LL_DMA2D_FGND_GetAlphaInvMode

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMA2D_ALPHA_REGULAR

+  *         @arg @ref LL_DMA2D_ALPHA_INVERTED

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI));

+}

+

+/**

+  * @brief  Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).

+  * @rmtoll FGOR          LO          LL_DMA2D_FGND_SetLineOffset

+  * @param  DMA2Dx DMA2D Instance

+  * @param  LineOffset Value between Min_Data=0 and Max_Data=0x3FF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)

+{

+  MODIFY_REG(DMA2Dx->FGOR, DMA2D_FGOR_LO, LineOffset);

+}

+

+/**

+  * @brief  Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).

+  * @rmtoll FGOR          LO         LL_DMA2D_FGND_GetLineOffset

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO));

+}

+

+/**

+  * @brief  Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits).

+  * @rmtoll FGCOLR          RED          LL_DMA2D_FGND_SetColor

+  * @rmtoll FGCOLR          GREEN        LL_DMA2D_FGND_SetColor

+  * @rmtoll FGCOLR          BLUE         LL_DMA2D_FGND_SetColor

+  * @param  DMA2Dx DMA2D Instance

+  * @param  Red   Value between Min_Data=0 and Max_Data=0xFF

+  * @param  Green Value between Min_Data=0 and Max_Data=0xFF

+  * @param  Blue  Value between Min_Data=0 and Max_Data=0xFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_FGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)

+{

+  MODIFY_REG(DMA2Dx->FGCOLR, (DMA2D_FGCOLR_RED | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_BLUE), \

+             ((Red << DMA2D_FGCOLR_RED_Pos) | (Green << DMA2D_FGCOLR_GREEN_Pos) | Blue));

+}

+

+/**

+  * @brief  Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).

+  * @rmtoll FGCOLR          RED          LL_DMA2D_FGND_SetRedColor

+  * @param  DMA2Dx DMA2D Instance

+  * @param  Red Value between Min_Data=0 and Max_Data=0xFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)

+{

+  MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED, (Red << DMA2D_FGCOLR_RED_Pos));

+}

+

+/**

+  * @brief  Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).

+  * @rmtoll FGCOLR          RED         LL_DMA2D_FGND_GetRedColor

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Red color value between Min_Data=0 and Max_Data=0xFF

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos);

+}

+

+/**

+  * @brief  Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).

+  * @rmtoll FGCOLR          GREEN          LL_DMA2D_FGND_SetGreenColor

+  * @param  DMA2Dx DMA2D Instance

+  * @param  Green Value between Min_Data=0 and Max_Data=0xFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)

+{

+  MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN, (Green << DMA2D_FGCOLR_GREEN_Pos));

+}

+

+/**

+  * @brief  Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).

+  * @rmtoll FGCOLR          GREEN         LL_DMA2D_FGND_GetGreenColor

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Green color value between Min_Data=0 and Max_Data=0xFF

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos);

+}

+

+/**

+  * @brief  Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).

+  * @rmtoll FGCOLR          BLUE          LL_DMA2D_FGND_SetBlueColor

+  * @param  DMA2Dx DMA2D Instance

+  * @param  Blue Value between Min_Data=0 and Max_Data=0xFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)

+{

+  MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE, Blue);

+}

+

+/**

+  * @brief  Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).

+  * @rmtoll FGCOLR          BLUE         LL_DMA2D_FGND_GetBlueColor

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Blue color value between Min_Data=0 and Max_Data=0xFF

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE));

+}

+

+/**

+  * @brief  Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).

+  * @rmtoll FGCMAR          MA          LL_DMA2D_FGND_SetCLUTMemAddr

+  * @param  DMA2Dx DMA2D Instance

+  * @param  CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)

+{

+  LL_DMA2D_WriteReg(DMA2Dx, FGCMAR, CLUTMemoryAddress);

+}

+

+/**

+  * @brief  Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).

+  * @rmtoll FGCMAR          MA          LL_DMA2D_FGND_GetCLUTMemAddr

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR));

+}

+

+/**

+  * @brief  Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).

+  * @rmtoll FGPFCCR          CS          LL_DMA2D_FGND_SetCLUTSize

+  * @param  DMA2Dx DMA2D Instance

+  * @param  CLUTSize Value between Min_Data=0 and Max_Data=0xFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)

+{

+  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS, (CLUTSize << DMA2D_FGPFCCR_CS_Pos));

+}

+

+/**

+  * @brief  Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).

+  * @rmtoll FGPFCCR          CS          LL_DMA2D_FGND_GetCLUTSize

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos);

+}

+

+/**

+  * @brief  Set DMA2D foreground CLUT color mode.

+  * @rmtoll FGPFCCR          CCM          LL_DMA2D_FGND_SetCLUTColorMode

+  * @param  DMA2Dx DMA2D Instance

+  * @param  CLUTColorMode This parameter can be one of the following values:

+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888

+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)

+{

+  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM, CLUTColorMode);

+}

+

+/**

+  * @brief  Return DMA2D foreground CLUT color mode.

+  * @rmtoll FGPFCCR          CCM         LL_DMA2D_FGND_GetCLUTColorMode

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888

+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM));

+}

+

+/**

+  * @brief  Set DMA2D foreground Chroma Sub Sampling (for YCbCr input color mode).

+  * @rmtoll FGPFCCR          CSS          LL_DMA2D_FGND_SetChrSubSampling

+  * @param  DMA2Dx DMA2D Instance

+  * @param  ChromaSubSampling This parameter can be one of the following values:

+  *         @arg @ref LL_DMA2D_CSS_444

+  *         @arg @ref LL_DMA2D_CSS_422

+  *         @arg @ref LL_DMA2D_CSS_420

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_FGND_SetChrSubSampling(DMA2D_TypeDef *DMA2Dx, uint32_t ChromaSubSampling)

+{

+  MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CSS, ChromaSubSampling);

+}

+

+/**

+  * @brief  Return DMA2D foreground Chroma Sub Sampling (for YCbCr input color mode).

+  * @rmtoll FGPFCCR          CSS         LL_DMA2D_FGND_GetChrSubSampling

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMA2D_CSS_444

+  *         @arg @ref LL_DMA2D_CSS_422

+  *         @arg @ref LL_DMA2D_CSS_420

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_FGND_GetChrSubSampling(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CSS));

+}

+/**

+  * @}

+  */

+

+/** @defgroup DMA2D_LL_EF_BGND_Configuration Background Configuration Functions

+  * @{

+  */

+

+/**

+  * @brief  Set DMA2D background memory address, expressed on 32 bits ([31:0] bits).

+  * @rmtoll BGMAR          MA          LL_DMA2D_BGND_SetMemAddr

+  * @param  DMA2Dx DMA2D Instance

+  * @param  MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)

+{

+  LL_DMA2D_WriteReg(DMA2Dx, BGMAR, MemoryAddress);

+}

+

+/**

+  * @brief  Get DMA2D background memory address, expressed on 32 bits ([31:0] bits).

+  * @rmtoll BGMAR          MA          LL_DMA2D_BGND_GetMemAddr

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR));

+}

+

+/**

+  * @brief  Enable DMA2D background CLUT loading.

+  * @rmtoll BGPFCCR          START            LL_DMA2D_BGND_EnableCLUTLoad

+  * @param  DMA2Dx DMA2D Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)

+{

+  SET_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START);

+}

+

+/**

+  * @brief  Indicate if DMA2D background CLUT loading is enabled.

+  * @rmtoll BGPFCCR          START            LL_DMA2D_BGND_IsEnabledCLUTLoad

+  * @param  DMA2Dx DMA2D Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)

+{

+  return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set DMA2D background color mode.

+  * @rmtoll BGPFCCR          CM          LL_DMA2D_BGND_SetColorMode

+  * @param  DMA2Dx DMA2D Instance

+  * @param  ColorMode This parameter can be one of the following values:

+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888

+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB888

+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB565

+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555

+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444

+  *         @arg @ref LL_DMA2D_INPUT_MODE_L8

+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL44

+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL88

+  *         @arg @ref LL_DMA2D_INPUT_MODE_L4

+  *         @arg @ref LL_DMA2D_INPUT_MODE_A8

+  *         @arg @ref LL_DMA2D_INPUT_MODE_A4

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)

+{

+  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM, ColorMode);

+}

+

+/**

+  * @brief  Return DMA2D background color mode.

+  * @rmtoll BGPFCCR          CM          LL_DMA2D_BGND_GetColorMode

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888

+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB888

+  *         @arg @ref LL_DMA2D_INPUT_MODE_RGB565

+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555

+  *         @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444

+  *         @arg @ref LL_DMA2D_INPUT_MODE_L8

+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL44

+  *         @arg @ref LL_DMA2D_INPUT_MODE_AL88

+  *         @arg @ref LL_DMA2D_INPUT_MODE_L4

+  *         @arg @ref LL_DMA2D_INPUT_MODE_A8

+  *         @arg @ref LL_DMA2D_INPUT_MODE_A4

+  */

+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM));

+}

+

+/**

+  * @brief  Set DMA2D background alpha mode.

+  * @rmtoll BGPFCCR          AM         LL_DMA2D_BGND_SetAlphaMode

+  * @param  DMA2Dx DMA2D Instance

+  * @param  AphaMode This parameter can be one of the following values:

+  *         @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF

+  *         @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE

+  *         @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)

+{

+  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM, AphaMode);

+}

+

+/**

+  * @brief  Return DMA2D background alpha mode.

+  * @rmtoll BGPFCCR          AM          LL_DMA2D_BGND_GetAlphaMode

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF

+  *         @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE

+  *         @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE

+  */

+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM));

+}

+

+/**

+  * @brief  Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits).

+  * @rmtoll BGPFCCR          ALPHA         LL_DMA2D_BGND_SetAlpha

+  * @param  DMA2Dx DMA2D Instance

+  * @param  Alpha Value between Min_Data=0 and Max_Data=0xFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)

+{

+  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA, (Alpha << DMA2D_BGPFCCR_ALPHA_Pos));

+}

+

+/**

+  * @brief  Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits).

+  * @rmtoll BGPFCCR          ALPHA          LL_DMA2D_BGND_GetAlpha

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Alpha value between Min_Data=0 and Max_Data=0xFF

+  */

+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos);

+}

+

+/**

+  * @brief  Set DMA2D background Red Blue swap mode.

+  * @rmtoll BGPFCCR          RBS         LL_DMA2D_BGND_SetRBSwapMode

+  * @param  DMA2Dx DMA2D Instance

+  * @param  RBSwapMode This parameter can be one of the following values:

+  *         @arg @ref LL_DMA2D_RB_MODE_REGULAR

+  *         @arg @ref LL_DMA2D_RB_MODE_SWAP

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)

+{

+  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS, RBSwapMode);

+}

+

+/**

+  * @brief  Return DMA2D background Red Blue swap mode.

+  * @rmtoll BGPFCCR          RBS          LL_DMA2D_BGND_GetRBSwapMode

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMA2D_RB_MODE_REGULAR

+  *         @arg @ref LL_DMA2D_RB_MODE_SWAP

+  */

+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS));

+}

+

+/**

+  * @brief  Set DMA2D background alpha inversion mode.

+  * @rmtoll BGPFCCR          AI         LL_DMA2D_BGND_SetAlphaInvMode

+  * @param  DMA2Dx DMA2D Instance

+  * @param  AlphaInversionMode This parameter can be one of the following values:

+  *         @arg @ref LL_DMA2D_ALPHA_REGULAR

+  *         @arg @ref LL_DMA2D_ALPHA_INVERTED

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)

+{

+  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI, AlphaInversionMode);

+}

+

+/**

+  * @brief  Return DMA2D background alpha inversion mode.

+  * @rmtoll BGPFCCR          AI          LL_DMA2D_BGND_GetAlphaInvMode

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMA2D_ALPHA_REGULAR

+  *         @arg @ref LL_DMA2D_ALPHA_INVERTED

+  */

+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI));

+}

+

+/**

+  * @brief  Set DMA2D background line offset, expressed on 14 bits ([13:0] bits).

+  * @rmtoll BGOR          LO         LL_DMA2D_BGND_SetLineOffset

+  * @param  DMA2Dx DMA2D Instance

+  * @param  LineOffset Value between Min_Data=0 and Max_Data=0x3FF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)

+{

+  MODIFY_REG(DMA2Dx->BGOR, DMA2D_BGOR_LO, LineOffset);

+}

+

+/**

+  * @brief  Return DMA2D background line offset, expressed on 14 bits ([13:0] bits).

+  * @rmtoll BGOR          LO          LL_DMA2D_BGND_GetLineOffset

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF

+  */

+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO));

+}

+

+/**

+  * @brief  Set DMA2D background color values, expressed on 24 bits ([23:0] bits).

+  * @rmtoll BGCOLR          RED          LL_DMA2D_BGND_SetColor

+  * @rmtoll BGCOLR          GREEN        LL_DMA2D_BGND_SetColor

+  * @rmtoll BGCOLR          BLUE         LL_DMA2D_BGND_SetColor

+  * @param  DMA2Dx DMA2D Instance

+  * @param  Red   Value between Min_Data=0 and Max_Data=0xFF

+  * @param  Green Value between Min_Data=0 and Max_Data=0xFF

+  * @param  Blue  Value between Min_Data=0 and Max_Data=0xFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_BGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)

+{

+  MODIFY_REG(DMA2Dx->BGCOLR, (DMA2D_BGCOLR_RED | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_BLUE), \

+             ((Red << DMA2D_BGCOLR_RED_Pos) | (Green << DMA2D_BGCOLR_GREEN_Pos) | Blue));

+}

+

+/**

+  * @brief  Set DMA2D background red color value, expressed on 8 bits ([7:0] bits).

+  * @rmtoll BGCOLR          RED         LL_DMA2D_BGND_SetRedColor

+  * @param  DMA2Dx DMA2D Instance

+  * @param  Red Value between Min_Data=0 and Max_Data=0xFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)

+{

+  MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED, (Red << DMA2D_BGCOLR_RED_Pos));

+}

+

+/**

+  * @brief  Return DMA2D background red color value, expressed on 8 bits ([7:0] bits).

+  * @rmtoll BGCOLR          RED          LL_DMA2D_BGND_GetRedColor

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Red color value between Min_Data=0 and Max_Data=0xFF

+  */

+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos);

+}

+

+/**

+  * @brief  Set DMA2D background green color value, expressed on 8 bits ([7:0] bits).

+  * @rmtoll BGCOLR          GREEN         LL_DMA2D_BGND_SetGreenColor

+  * @param  DMA2Dx DMA2D Instance

+  * @param  Green Value between Min_Data=0 and Max_Data=0xFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)

+{

+  MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN, (Green << DMA2D_BGCOLR_GREEN_Pos));

+}

+

+/**

+  * @brief  Return DMA2D background green color value, expressed on 8 bits ([7:0] bits).

+  * @rmtoll BGCOLR          GREEN          LL_DMA2D_BGND_GetGreenColor

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Green color value between Min_Data=0 and Max_Data=0xFF

+  */

+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos);

+}

+

+/**

+  * @brief  Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits).

+  * @rmtoll BGCOLR          BLUE         LL_DMA2D_BGND_SetBlueColor

+  * @param  DMA2Dx DMA2D Instance

+  * @param  Blue Value between Min_Data=0 and Max_Data=0xFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)

+{

+  MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE, Blue);

+}

+

+/**

+  * @brief  Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits).

+  * @rmtoll BGCOLR          BLUE          LL_DMA2D_BGND_GetBlueColor

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Blue color value between Min_Data=0 and Max_Data=0xFF

+  */

+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE));

+}

+

+/**

+  * @brief  Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).

+  * @rmtoll BGCMAR          MA         LL_DMA2D_BGND_SetCLUTMemAddr

+  * @param  DMA2Dx DMA2D Instance

+  * @param  CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)

+{

+  LL_DMA2D_WriteReg(DMA2Dx, BGCMAR, CLUTMemoryAddress);

+}

+

+/**

+  * @brief  Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).

+  * @rmtoll BGCMAR          MA           LL_DMA2D_BGND_GetCLUTMemAddr

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF

+  */

+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR));

+}

+

+/**

+  * @brief  Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).

+  * @rmtoll BGPFCCR          CS         LL_DMA2D_BGND_SetCLUTSize

+  * @param  DMA2Dx DMA2D Instance

+  * @param  CLUTSize Value between Min_Data=0 and Max_Data=0xFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)

+{

+  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS, (CLUTSize << DMA2D_BGPFCCR_CS_Pos));

+}

+

+/**

+  * @brief  Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).

+  * @rmtoll BGPFCCR          CS           LL_DMA2D_BGND_GetCLUTSize

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF

+  */

+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos);

+}

+

+/**

+  * @brief  Set DMA2D background CLUT color mode.

+  * @rmtoll BGPFCCR          CCM         LL_DMA2D_BGND_SetCLUTColorMode

+  * @param  DMA2Dx DMA2D Instance

+  * @param  CLUTColorMode This parameter can be one of the following values:

+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888

+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)

+{

+  MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM, CLUTColorMode);

+}

+

+/**

+  * @brief  Return DMA2D background CLUT color mode.

+  * @rmtoll BGPFCCR          CCM          LL_DMA2D_BGND_GetCLUTColorMode

+  * @param  DMA2Dx DMA2D Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888

+  *         @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888

+  */

+__STATIC_INLINE uint32_t  LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)

+{

+  return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM));

+}

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+

+/** @defgroup DMA2D_LL_EF_FLAG_MANAGEMENT Flag Management

+  * @{

+  */

+

+/**

+  * @brief  Check if the DMA2D Configuration Error Interrupt Flag is set or not

+  * @rmtoll ISR          CEIF            LL_DMA2D_IsActiveFlag_CE

+  * @param  DMA2Dx DMA2D Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx)

+{

+  return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not

+  * @rmtoll ISR          CTCIF            LL_DMA2D_IsActiveFlag_CTC

+  * @param  DMA2Dx DMA2D Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx)

+{

+  return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the DMA2D CLUT Access Error Interrupt Flag is set or not

+  * @rmtoll ISR          CAEIF            LL_DMA2D_IsActiveFlag_CAE

+  * @param  DMA2Dx DMA2D Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx)

+{

+  return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the DMA2D Transfer Watermark Interrupt Flag is set or not

+  * @rmtoll ISR          TWIF            LL_DMA2D_IsActiveFlag_TW

+  * @param  DMA2Dx DMA2D Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx)

+{

+  return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the DMA2D Transfer Complete Interrupt Flag is set or not

+  * @rmtoll ISR          TCIF            LL_DMA2D_IsActiveFlag_TC

+  * @param  DMA2Dx DMA2D Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx)

+{

+  return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the DMA2D Transfer Error Interrupt Flag is set or not

+  * @rmtoll ISR          TEIF            LL_DMA2D_IsActiveFlag_TE

+  * @param  DMA2Dx DMA2D Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx)

+{

+  return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear DMA2D Configuration Error Interrupt Flag

+  * @rmtoll IFCR          CCEIF          LL_DMA2D_ClearFlag_CE

+  * @param  DMA2Dx DMA2D Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef *DMA2Dx)

+{

+  WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCEIF);

+}

+

+/**

+  * @brief  Clear DMA2D CLUT Transfer Complete Interrupt Flag

+  * @rmtoll IFCR          CCTCIF          LL_DMA2D_ClearFlag_CTC

+  * @param  DMA2Dx DMA2D Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef *DMA2Dx)

+{

+  WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCTCIF);

+}

+

+/**

+  * @brief  Clear DMA2D CLUT Access Error Interrupt Flag

+  * @rmtoll IFCR          CAECIF          LL_DMA2D_ClearFlag_CAE

+  * @param  DMA2Dx DMA2D Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef *DMA2Dx)

+{

+  WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CAECIF);

+}

+

+/**

+  * @brief  Clear DMA2D Transfer Watermark Interrupt Flag

+  * @rmtoll IFCR          CTWIF          LL_DMA2D_ClearFlag_TW

+  * @param  DMA2Dx DMA2D Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef *DMA2Dx)

+{

+  WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTWIF);

+}

+

+/**

+  * @brief  Clear DMA2D Transfer Complete Interrupt Flag

+  * @rmtoll IFCR          CTCIF          LL_DMA2D_ClearFlag_TC

+  * @param  DMA2Dx DMA2D Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef *DMA2Dx)

+{

+  WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTCIF);

+}

+

+/**

+  * @brief  Clear DMA2D Transfer Error Interrupt Flag

+  * @rmtoll IFCR          CTEIF          LL_DMA2D_ClearFlag_TE

+  * @param  DMA2Dx DMA2D Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef *DMA2Dx)

+{

+  WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTEIF);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup DMA2D_LL_EF_IT_MANAGEMENT Interruption Management

+  * @{

+  */

+

+/**

+  * @brief  Enable Configuration Error Interrupt

+  * @rmtoll CR          CEIE        LL_DMA2D_EnableIT_CE

+  * @param  DMA2Dx DMA2D Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_EnableIT_CE(DMA2D_TypeDef *DMA2Dx)

+{

+  SET_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);

+}

+

+/**

+  * @brief  Enable CLUT Transfer Complete Interrupt

+  * @rmtoll CR          CTCIE        LL_DMA2D_EnableIT_CTC

+  * @param  DMA2Dx DMA2D Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef *DMA2Dx)

+{

+  SET_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);

+}

+

+/**

+  * @brief  Enable CLUT Access Error Interrupt

+  * @rmtoll CR          CAEIE        LL_DMA2D_EnableIT_CAE

+  * @param  DMA2Dx DMA2D Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef *DMA2Dx)

+{

+  SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);

+}

+

+/**

+  * @brief  Enable Transfer Watermark Interrupt

+  * @rmtoll CR          TWIE        LL_DMA2D_EnableIT_TW

+  * @param  DMA2Dx DMA2D Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_EnableIT_TW(DMA2D_TypeDef *DMA2Dx)

+{

+  SET_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);

+}

+

+/**

+  * @brief  Enable Transfer Complete Interrupt

+  * @rmtoll CR          TCIE        LL_DMA2D_EnableIT_TC

+  * @param  DMA2Dx DMA2D Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_EnableIT_TC(DMA2D_TypeDef *DMA2Dx)

+{

+  SET_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);

+}

+

+/**

+  * @brief  Enable Transfer Error Interrupt

+  * @rmtoll CR          TEIE        LL_DMA2D_EnableIT_TE

+  * @param  DMA2Dx DMA2D Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_EnableIT_TE(DMA2D_TypeDef *DMA2Dx)

+{

+  SET_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);

+}

+

+/**

+  * @brief  Disable Configuration Error Interrupt

+  * @rmtoll CR          CEIE        LL_DMA2D_DisableIT_CE

+  * @param  DMA2Dx DMA2D Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_DisableIT_CE(DMA2D_TypeDef *DMA2Dx)

+{

+  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);

+}

+

+/**

+  * @brief  Disable CLUT Transfer Complete Interrupt

+  * @rmtoll CR          CTCIE        LL_DMA2D_DisableIT_CTC

+  * @param  DMA2Dx DMA2D Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef *DMA2Dx)

+{

+  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);

+}

+

+/**

+  * @brief  Disable CLUT Access Error Interrupt

+  * @rmtoll CR          CAEIE        LL_DMA2D_DisableIT_CAE

+  * @param  DMA2Dx DMA2D Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef *DMA2Dx)

+{

+  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);

+}

+

+/**

+  * @brief  Disable Transfer Watermark Interrupt

+  * @rmtoll CR          TWIE        LL_DMA2D_DisableIT_TW

+  * @param  DMA2Dx DMA2D Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_DisableIT_TW(DMA2D_TypeDef *DMA2Dx)

+{

+  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);

+}

+

+/**

+  * @brief  Disable Transfer Complete Interrupt

+  * @rmtoll CR          TCIE        LL_DMA2D_DisableIT_TC

+  * @param  DMA2Dx DMA2D Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_DisableIT_TC(DMA2D_TypeDef *DMA2Dx)

+{

+  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);

+}

+

+/**

+  * @brief  Disable Transfer Error Interrupt

+  * @rmtoll CR          TEIE        LL_DMA2D_DisableIT_TE

+  * @param  DMA2Dx DMA2D Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx)

+{

+  CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);

+}

+

+/**

+  * @brief  Check if the DMA2D Configuration Error interrupt source is enabled or disabled.

+  * @rmtoll CR          CEIE        LL_DMA2D_IsEnabledIT_CE

+  * @param  DMA2Dx DMA2D Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx)

+{

+  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled.

+  * @rmtoll CR          CTCIE        LL_DMA2D_IsEnabledIT_CTC

+  * @param  DMA2Dx DMA2D Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx)

+{

+  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled.

+  * @rmtoll CR          CAEIE        LL_DMA2D_IsEnabledIT_CAE

+  * @param  DMA2Dx DMA2D Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx)

+{

+  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled.

+  * @rmtoll CR          TWIE        LL_DMA2D_IsEnabledIT_TW

+  * @param  DMA2Dx DMA2D Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx)

+{

+  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the DMA2D Transfer Complete interrupt source is enabled or disabled.

+  * @rmtoll CR          TCIE        LL_DMA2D_IsEnabledIT_TC

+  * @param  DMA2Dx DMA2D Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx)

+{

+  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the DMA2D Transfer Error interrupt source is enabled or disabled.

+  * @rmtoll CR          TEIE        LL_DMA2D_IsEnabledIT_TE

+  * @param  DMA2Dx DMA2D Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx)

+{

+  return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL);

+}

+

+

+

+/**

+  * @}

+  */

+

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions

+  * @{

+  */

+

+ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx);

+ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct);

+void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct);

+void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx);

+void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg);

+void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct);

+uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);

+uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);

+uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);

+uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);

+void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines);

+

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* defined (DMA2D) */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_LL_DMA2D_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_dmamux.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_dmamux.h
new file mode 100644
index 0000000000..13f81186d8
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_dmamux.h
@@ -0,0 +1,2363 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_dmamux.h

+  * @author  MCD Application Team

+  * @brief   Header file of DMAMUX LL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_LL_DMAMUX_H

+#define STM32H7xx_LL_DMAMUX_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+#if defined (DMAMUX1) || defined (DMAMUX2)

+

+/** @defgroup DMAMUX_LL DMAMUX

+  * @{

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants

+  * @{

+  */

+/* Define used to get DMAMUX CCR register size */

+#define DMAMUX_CCR_SIZE                   0x00000004U

+

+/* Define used to get DMAMUX RGCR register size */

+#define DMAMUX_RGCR_SIZE                  0x00000004U

+

+/* Define used to get DMAMUX RequestGenerator offset */

+#define DMAMUX_REQ_GEN_OFFSET             (DMAMUX1_RequestGenerator0_BASE - DMAMUX1_BASE)

+/* Define used to get DMAMUX Channel Status offset */

+#define DMAMUX_CH_STATUS_OFFSET           (DMAMUX1_ChannelStatus_BASE - DMAMUX1_BASE)

+/* Define used to get DMAMUX RequestGenerator status offset */

+#define DMAMUX_REQ_GEN_STATUS_OFFSET      (DMAMUX1_RequestGenStatus_BASE - DMAMUX1_BASE)

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/* Exported types ------------------------------------------------------------*/

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants

+  * @{

+  */

+/** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines

+  * @brief    Flags defines which can be used with LL_DMAMUX_WriteReg function

+  * @{

+  */

+#define LL_DMAMUX_CFR_CSOF0               DMAMUX_CFR_CSOF0       /*!< Synchronization Event Overrun Flag Channel 0   */

+#define LL_DMAMUX_CFR_CSOF1               DMAMUX_CFR_CSOF1       /*!< Synchronization Event Overrun Flag Channel 1   */

+#define LL_DMAMUX_CFR_CSOF2               DMAMUX_CFR_CSOF2       /*!< Synchronization Event Overrun Flag Channel 2   */

+#define LL_DMAMUX_CFR_CSOF3               DMAMUX_CFR_CSOF3       /*!< Synchronization Event Overrun Flag Channel 3   */

+#define LL_DMAMUX_CFR_CSOF4               DMAMUX_CFR_CSOF4       /*!< Synchronization Event Overrun Flag Channel 4   */

+#define LL_DMAMUX_CFR_CSOF5               DMAMUX_CFR_CSOF5       /*!< Synchronization Event Overrun Flag Channel 5   */

+#define LL_DMAMUX_CFR_CSOF6               DMAMUX_CFR_CSOF6       /*!< Synchronization Event Overrun Flag Channel 6   */

+#define LL_DMAMUX_CFR_CSOF7               DMAMUX_CFR_CSOF7       /*!< Synchronization Event Overrun Flag Channel 7   */

+#define LL_DMAMUX_CFR_CSOF8               DMAMUX_CFR_CSOF8       /*!< Synchronization Event Overrun Flag Channel 8   */

+#define LL_DMAMUX_CFR_CSOF9               DMAMUX_CFR_CSOF9       /*!< Synchronization Event Overrun Flag Channel 9   */

+#define LL_DMAMUX_CFR_CSOF10              DMAMUX_CFR_CSOF10      /*!< Synchronization Event Overrun Flag Channel 10  */

+#define LL_DMAMUX_CFR_CSOF11              DMAMUX_CFR_CSOF11      /*!< Synchronization Event Overrun Flag Channel 11  */

+#define LL_DMAMUX_CFR_CSOF12              DMAMUX_CFR_CSOF12      /*!< Synchronization Event Overrun Flag Channel 12  */

+#define LL_DMAMUX_CFR_CSOF13              DMAMUX_CFR_CSOF13      /*!< Synchronization Event Overrun Flag Channel 13  */

+#define LL_DMAMUX_CFR_CSOF14              DMAMUX_CFR_CSOF14      /*!< Synchronization Event Overrun Flag Channel 14  */

+#define LL_DMAMUX_CFR_CSOF15              DMAMUX_CFR_CSOF15      /*!< Synchronization Event Overrun Flag Channel 15  */

+#define LL_DMAMUX_RGCFR_RGCOF0            DMAMUX_RGCFR_COF0      /*!< Request Generator 0 Trigger Event Overrun Flag */

+#define LL_DMAMUX_RGCFR_RGCOF1            DMAMUX_RGCFR_COF1      /*!< Request Generator 1 Trigger Event Overrun Flag */

+#define LL_DMAMUX_RGCFR_RGCOF2            DMAMUX_RGCFR_COF2      /*!< Request Generator 2 Trigger Event Overrun Flag */

+#define LL_DMAMUX_RGCFR_RGCOF3            DMAMUX_RGCFR_COF3      /*!< Request Generator 3 Trigger Event Overrun Flag */

+#define LL_DMAMUX_RGCFR_RGCOF4            DMAMUX_RGCFR_COF4      /*!< Request Generator 4 Trigger Event Overrun Flag */

+#define LL_DMAMUX_RGCFR_RGCOF5            DMAMUX_RGCFR_COF5      /*!< Request Generator 5 Trigger Event Overrun Flag */

+#define LL_DMAMUX_RGCFR_RGCOF6            DMAMUX_RGCFR_COF6      /*!< Request Generator 6 Trigger Event Overrun Flag */

+#define LL_DMAMUX_RGCFR_RGCOF7            DMAMUX_RGCFR_COF7      /*!< Request Generator 7 Trigger Event Overrun Flag */

+/**

+  * @}

+  */

+

+/** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines

+  * @brief    Flags defines which can be used with LL_DMAMUX_ReadReg function

+  * @{

+  */

+#define LL_DMAMUX_CSR_SOF0                DMAMUX_CSR_SOF0       /*!< Synchronization Event Overrun Flag Channel 0   */

+#define LL_DMAMUX_CSR_SOF1                DMAMUX_CSR_SOF1       /*!< Synchronization Event Overrun Flag Channel 1   */

+#define LL_DMAMUX_CSR_SOF2                DMAMUX_CSR_SOF2       /*!< Synchronization Event Overrun Flag Channel 2   */

+#define LL_DMAMUX_CSR_SOF3                DMAMUX_CSR_SOF3       /*!< Synchronization Event Overrun Flag Channel 3   */

+#define LL_DMAMUX_CSR_SOF4                DMAMUX_CSR_SOF4       /*!< Synchronization Event Overrun Flag Channel 4   */

+#define LL_DMAMUX_CSR_SOF5                DMAMUX_CSR_SOF5       /*!< Synchronization Event Overrun Flag Channel 5   */

+#define LL_DMAMUX_CSR_SOF6                DMAMUX_CSR_SOF6       /*!< Synchronization Event Overrun Flag Channel 6   */

+#define LL_DMAMUX_CSR_SOF7                DMAMUX_CSR_SOF7       /*!< Synchronization Event Overrun Flag Channel 7   */

+#define LL_DMAMUX_CSR_SOF8                DMAMUX_CSR_SOF8       /*!< Synchronization Event Overrun Flag Channel 8   */

+#define LL_DMAMUX_CSR_SOF9                DMAMUX_CSR_SOF9       /*!< Synchronization Event Overrun Flag Channel 9   */

+#define LL_DMAMUX_CSR_SOF10               DMAMUX_CSR_SOF10      /*!< Synchronization Event Overrun Flag Channel 10  */

+#define LL_DMAMUX_CSR_SOF11               DMAMUX_CSR_SOF11      /*!< Synchronization Event Overrun Flag Channel 11  */

+#define LL_DMAMUX_CSR_SOF12               DMAMUX_CSR_SOF12      /*!< Synchronization Event Overrun Flag Channel 12  */

+#define LL_DMAMUX_CSR_SOF13               DMAMUX_CSR_SOF13      /*!< Synchronization Event Overrun Flag Channel 13  */

+#define LL_DMAMUX_CSR_SOF14               DMAMUX_CSR_SOF14      /*!< Synchronization Event Overrun Flag Channel 14  */

+#define LL_DMAMUX_CSR_SOF15               DMAMUX_CSR_SOF15      /*!< Synchronization Event Overrun Flag Channel 15  */

+#define LL_DMAMUX_RGSR_RGOF0              DMAMUX_RGSR_OF0       /*!< Request Generator 0 Trigger Event Overrun Flag */

+#define LL_DMAMUX_RGSR_RGOF1              DMAMUX_RGSR_OF1       /*!< Request Generator 1 Trigger Event Overrun Flag */

+#define LL_DMAMUX_RGSR_RGOF2              DMAMUX_RGSR_OF2       /*!< Request Generator 2 Trigger Event Overrun Flag */

+#define LL_DMAMUX_RGSR_RGOF3              DMAMUX_RGSR_OF3       /*!< Request Generator 3 Trigger Event Overrun Flag */

+#define LL_DMAMUX_RGSR_RGOF4              DMAMUX_RGSR_OF4       /*!< Request Generator 4 Trigger Event Overrun Flag */

+#define LL_DMAMUX_RGSR_RGOF5              DMAMUX_RGSR_OF5       /*!< Request Generator 5 Trigger Event Overrun Flag */

+#define LL_DMAMUX_RGSR_RGOF6              DMAMUX_RGSR_OF6       /*!< Request Generator 6 Trigger Event Overrun Flag */

+#define LL_DMAMUX_RGSR_RGOF7              DMAMUX_RGSR_OF7       /*!< Request Generator 7 Trigger Event Overrun Flag */

+/**

+  * @}

+  */

+

+/** @defgroup DMAMUX_LL_EC_IT IT Defines

+  * @brief    IT defines which can be used with LL_DMA_ReadReg and  LL_DMAMUX_WriteReg functions

+  * @{

+  */

+#define LL_DMAMUX_CCR_SOIE                DMAMUX_CxCR_SOIE          /*!< Synchronization Event Overrun Interrupt               */

+#define LL_DMAMUX_RGCR_RGOIE              DMAMUX_RGxCR_OIE          /*!< Request Generation Trigger Event Overrun Interrupt    */

+/**

+  * @}

+  */

+

+/** @defgroup DMAMUX_Request_selection DMAMUX Request selection

+  * @brief    DMA Request selection

+  * @{

+  */

+/* DMAMUX1 requests */

+#define LL_DMAMUX1_REQ_MEM2MEM          0U   /*!< memory to memory transfer       */

+#define LL_DMAMUX1_REQ_GENERATOR0       1U   /*!< DMAMUX1 request generator 0     */

+#define LL_DMAMUX1_REQ_GENERATOR1       2U   /*!< DMAMUX1 request generator 1     */

+#define LL_DMAMUX1_REQ_GENERATOR2       3U   /*!< DMAMUX1 request generator 2     */

+#define LL_DMAMUX1_REQ_GENERATOR3       4U   /*!< DMAMUX1 request generator 3     */

+#define LL_DMAMUX1_REQ_GENERATOR4       5U   /*!< DMAMUX1 request generator 4     */

+#define LL_DMAMUX1_REQ_GENERATOR5       6U   /*!< DMAMUX1 request generator 5     */

+#define LL_DMAMUX1_REQ_GENERATOR6       7U   /*!< DMAMUX1 request generator 6     */

+#define LL_DMAMUX1_REQ_GENERATOR7       8U   /*!< DMAMUX1 request generator 7     */

+#define LL_DMAMUX1_REQ_ADC1             9U   /*!< DMAMUX1 ADC1 request            */

+#define LL_DMAMUX1_REQ_ADC2             10U  /*!< DMAMUX1 ADC2 request            */

+#define LL_DMAMUX1_REQ_TIM1_CH1         11U  /*!< DMAMUX1 TIM1 CH1 request        */

+#define LL_DMAMUX1_REQ_TIM1_CH2         12U  /*!< DMAMUX1 TIM1 CH2 request        */

+#define LL_DMAMUX1_REQ_TIM1_CH3         13U  /*!< DMAMUX1 TIM1 CH3 request        */

+#define LL_DMAMUX1_REQ_TIM1_CH4         14U  /*!< DMAMUX1 TIM1 CH4 request        */

+#define LL_DMAMUX1_REQ_TIM1_UP          15U  /*!< DMAMUX1 TIM1 UP request         */

+#define LL_DMAMUX1_REQ_TIM1_TRIG        16U  /*!< DMAMUX1 TIM1 TRIG request       */

+#define LL_DMAMUX1_REQ_TIM1_COM         17U  /*!< DMAMUX1 TIM1 COM request        */

+#define LL_DMAMUX1_REQ_TIM2_CH1         18U  /*!< DMAMUX1 TIM2 CH1 request        */

+#define LL_DMAMUX1_REQ_TIM2_CH2         19U  /*!< DMAMUX1 TIM2 CH2 request        */

+#define LL_DMAMUX1_REQ_TIM2_CH3         20U  /*!< DMAMUX1 TIM2 CH3 request        */

+#define LL_DMAMUX1_REQ_TIM2_CH4         21U  /*!< DMAMUX1 TIM2 CH4 request        */

+#define LL_DMAMUX1_REQ_TIM2_UP          22U  /*!< DMAMUX1 TIM2 UP request         */

+#define LL_DMAMUX1_REQ_TIM3_CH1         23U  /*!< DMAMUX1 TIM3 CH1 request        */

+#define LL_DMAMUX1_REQ_TIM3_CH2         24U  /*!< DMAMUX1 TIM3 CH2 request        */

+#define LL_DMAMUX1_REQ_TIM3_CH3         25U  /*!< DMAMUX1 TIM3 CH3 request        */

+#define LL_DMAMUX1_REQ_TIM3_CH4         26U  /*!< DMAMUX1 TIM3 CH4 request        */

+#define LL_DMAMUX1_REQ_TIM3_UP          27U  /*!< DMAMUX1 TIM3 UP request         */

+#define LL_DMAMUX1_REQ_TIM3_TRIG        28U  /*!< DMAMUX1 TIM3 TRIG request       */

+#define LL_DMAMUX1_REQ_TIM4_CH1         29U  /*!< DMAMUX1 TIM4 CH1 request        */

+#define LL_DMAMUX1_REQ_TIM4_CH2         30U  /*!< DMAMUX1 TIM4 CH2 request        */

+#define LL_DMAMUX1_REQ_TIM4_CH3         31U  /*!< DMAMUX1 TIM4 CH3 request        */

+#define LL_DMAMUX1_REQ_TIM4_UP          32U  /*!< DMAMUX1 TIM4 UP request         */

+#define LL_DMAMUX1_REQ_I2C1_RX          33U  /*!< DMAMUX1 I2C1 RX request         */

+#define LL_DMAMUX1_REQ_I2C1_TX          34U  /*!< DMAMUX1 I2C1 TX request         */

+#define LL_DMAMUX1_REQ_I2C2_RX          35U  /*!< DMAMUX1 I2C2 RX request         */

+#define LL_DMAMUX1_REQ_I2C2_TX          36U  /*!< DMAMUX1 I2C2 TX request         */

+#define LL_DMAMUX1_REQ_SPI1_RX          37U  /*!< DMAMUX1 SPI1 RX request         */

+#define LL_DMAMUX1_REQ_SPI1_TX          38U  /*!< DMAMUX1 SPI1 TX request         */

+#define LL_DMAMUX1_REQ_SPI2_RX          39U  /*!< DMAMUX1 SPI2 RX request         */

+#define LL_DMAMUX1_REQ_SPI2_TX          40U  /*!< DMAMUX1 SPI2 TX request         */

+#define LL_DMAMUX1_REQ_USART1_RX        41U  /*!< DMAMUX1 USART1 RX request       */

+#define LL_DMAMUX1_REQ_USART1_TX        42U  /*!< DMAMUX1 USART1 TX request       */

+#define LL_DMAMUX1_REQ_USART2_RX        43U  /*!< DMAMUX1 USART2 RX request       */

+#define LL_DMAMUX1_REQ_USART2_TX        44U  /*!< DMAMUX1 USART2 TX request       */

+#define LL_DMAMUX1_REQ_USART3_RX        45U  /*!< DMAMUX1 USART3 RX request       */

+#define LL_DMAMUX1_REQ_USART3_TX        46U  /*!< DMAMUX1 USART3 TX request       */

+#define LL_DMAMUX1_REQ_TIM8_CH1         47U  /*!< DMAMUX1 TIM8 CH1 request        */

+#define LL_DMAMUX1_REQ_TIM8_CH2         48U  /*!< DMAMUX1 TIM8 CH2 request        */

+#define LL_DMAMUX1_REQ_TIM8_CH3         49U  /*!< DMAMUX1 TIM8 CH3 request        */

+#define LL_DMAMUX1_REQ_TIM8_CH4         50U  /*!< DMAMUX1 TIM8 CH4 request        */

+#define LL_DMAMUX1_REQ_TIM8_UP          51U  /*!< DMAMUX1 TIM8 UP request         */

+#define LL_DMAMUX1_REQ_TIM8_TRIG        52U  /*!< DMAMUX1 TIM8 TRIG request       */

+#define LL_DMAMUX1_REQ_TIM8_COM         53U  /*!< DMAMUX1 TIM8 COM request        */

+#define LL_DMAMUX1_REQ_TIM5_CH1         55U  /*!< DMAMUX1 TIM5 CH1 request        */

+#define LL_DMAMUX1_REQ_TIM5_CH2         56U  /*!< DMAMUX1 TIM5 CH2 request        */

+#define LL_DMAMUX1_REQ_TIM5_CH3         57U  /*!< DMAMUX1 TIM5 CH3 request        */

+#define LL_DMAMUX1_REQ_TIM5_CH4         58U  /*!< DMAMUX1 TIM5 CH4 request        */

+#define LL_DMAMUX1_REQ_TIM5_UP          59U  /*!< DMAMUX1 TIM5 UP request         */

+#define LL_DMAMUX1_REQ_TIM5_TRIG        60U  /*!< DMAMUX1 TIM5 TRIG request       */

+#define LL_DMAMUX1_REQ_SPI3_RX          61U  /*!< DMAMUX1 SPI3 RX request         */

+#define LL_DMAMUX1_REQ_SPI3_TX          62U  /*!< DMAMUX1 SPI3 TX request         */

+#define LL_DMAMUX1_REQ_UART4_RX         63U  /*!< DMAMUX1 UART4 RX request        */

+#define LL_DMAMUX1_REQ_UART4_TX         64U  /*!< DMAMUX1 UART4 TX request        */

+#define LL_DMAMUX1_REQ_UART5_RX         65U  /*!< DMAMUX1 UART5 RX request        */

+#define LL_DMAMUX1_REQ_UART5_TX         66U  /*!< DMAMUX1 UART5 TX request        */

+#define LL_DMAMUX1_REQ_DAC1_CH1         67U  /*!< DMAMUX1 DAC1 Channel 1 request  */

+#define LL_DMAMUX1_REQ_DAC1_CH2         68U  /*!< DMAMUX1 DAC1 Channel 2 request  */

+#define LL_DMAMUX1_REQ_TIM6_UP          69U  /*!< DMAMUX1 TIM6 UP request         */

+#define LL_DMAMUX1_REQ_TIM7_UP          70U  /*!< DMAMUX1 TIM7 UP request         */

+#define LL_DMAMUX1_REQ_USART6_RX        71U  /*!< DMAMUX1 USART6 RX request       */

+#define LL_DMAMUX1_REQ_USART6_TX        72U  /*!< DMAMUX1 USART6 TX request       */

+#define LL_DMAMUX1_REQ_I2C3_RX          73U  /*!< DMAMUX1 I2C3 RX request         */

+#define LL_DMAMUX1_REQ_I2C3_TX          74U  /*!< DMAMUX1 I2C3 TX request         */

+#if defined (PSSI)

+#define LL_DMAMUX1_REQ_DCMI_PSSI        75U  /*!< DMAMUX1 DCMI/PSSI request       */

+#define LL_DMAMUX1_REQ_DCMI             LL_DMAMUX1_REQ_DCMI_PSSI /* Legacy define */

+#else

+#define LL_DMAMUX1_REQ_DCMI             75U  /*!< DMAMUX1 DCMI request            */

+#endif /* PSSI */

+#define LL_DMAMUX1_REQ_CRYP_IN          76U  /*!< DMAMUX1 CRYP IN request         */

+#define LL_DMAMUX1_REQ_CRYP_OUT         77U  /*!< DMAMUX1 CRYP OUT request        */

+#define LL_DMAMUX1_REQ_HASH_IN          78U  /*!< DMAMUX1 HASH IN request         */

+#define LL_DMAMUX1_REQ_UART7_RX         79U  /*!< DMAMUX1 UART7 RX request        */

+#define LL_DMAMUX1_REQ_UART7_TX         80U  /*!< DMAMUX1 UART7 TX request        */

+#define LL_DMAMUX1_REQ_UART8_RX         81U  /*!< DMAMUX1 UART8 RX request        */

+#define LL_DMAMUX1_REQ_UART8_TX         82U  /*!< DMAMUX1 UART8 TX request        */

+#define LL_DMAMUX1_REQ_SPI4_RX          83U  /*!< DMAMUX1 SPI4 RX request         */

+#define LL_DMAMUX1_REQ_SPI4_TX          84U  /*!< DMAMUX1 SPI4 TX request         */

+#define LL_DMAMUX1_REQ_SPI5_RX          85U  /*!< DMAMUX1 SPI5 RX request         */

+#define LL_DMAMUX1_REQ_SPI5_TX          86U  /*!< DMAMUX1 SPI5 TX request         */

+#define LL_DMAMUX1_REQ_SAI1_A           87U  /*!< DMAMUX1 SAI1 A request          */

+#define LL_DMAMUX1_REQ_SAI1_B           88U  /*!< DMAMUX1 SAI1 B request          */

+#define LL_DMAMUX1_REQ_SAI2_A           89U  /*!< DMAMUX1 SAI2 A request          */

+#define LL_DMAMUX1_REQ_SAI2_B           90U  /*!< DMAMUX1 SAI2 B request          */

+#define LL_DMAMUX1_REQ_SWPMI_RX         91U  /*!< DMAMUX1 SWPMI RX request        */

+#define LL_DMAMUX1_REQ_SWPMI_TX         92U  /*!< DMAMUX1 SWPMI TX request        */

+#define LL_DMAMUX1_REQ_SPDIF_RX_DT      93U  /*!< DMAMUX1 SPDIF RXDT request      */

+#define LL_DMAMUX1_REQ_SPDIF_RX_CS      94U  /*!< DMAMUX1 SPDIF RXCS request      */

+#if defined (HRTIM1)

+#define LL_DMAMUX1_REQ_HRTIM_MASTER     95U  /*!< DMAMUX1 HRTIM1 Master request 1 */

+#define LL_DMAMUX1_REQ_HRTIM_TIMER_A    96U  /*!< DMAMUX1 HRTIM1 TimerA request 2 */

+#define LL_DMAMUX1_REQ_HRTIM_TIMER_B    97U  /*!< DMAMUX1 HRTIM1 TimerB request 3 */

+#define LL_DMAMUX1_REQ_HRTIM_TIMER_C    98U  /*!< DMAMUX1 HRTIM1 TimerC request 4 */

+#define LL_DMAMUX1_REQ_HRTIM_TIMER_D    99U  /*!< DMAMUX1 HRTIM1 TimerD request 5 */

+#define LL_DMAMUX1_REQ_HRTIM_TIMER_E   100U  /*!< DMAMUX1 HRTIM1 TimerE request 6 */

+#endif /* HRTIM1 */

+#define LL_DMAMUX1_REQ_DFSDM1_FLT0     101U  /*!< DMAMUX1 DFSDM1 Filter0 request  */

+#define LL_DMAMUX1_REQ_DFSDM1_FLT1     102U  /*!< DMAMUX1 DFSDM1 Filter1 request  */

+#define LL_DMAMUX1_REQ_DFSDM1_FLT2     103U  /*!< DMAMUX1 DFSDM1 Filter2 request  */

+#define LL_DMAMUX1_REQ_DFSDM1_FLT3     104U  /*!< DMAMUX1 DFSDM1 Filter3 request  */

+#define LL_DMAMUX1_REQ_TIM15_CH1       105U  /*!< DMAMUX1 TIM15 CH1 request       */

+#define LL_DMAMUX1_REQ_TIM15_UP        106U  /*!< DMAMUX1 TIM15 UP request        */

+#define LL_DMAMUX1_REQ_TIM15_TRIG      107U  /*!< DMAMUX1 TIM15 TRIG request      */

+#define LL_DMAMUX1_REQ_TIM15_COM       108U  /*!< DMAMUX1 TIM15 COM request       */

+#define LL_DMAMUX1_REQ_TIM16_CH1       109U  /*!< DMAMUX1 TIM16 CH1 request       */

+#define LL_DMAMUX1_REQ_TIM16_UP        110U  /*!< DMAMUX1 TIM16 UP request        */

+#define LL_DMAMUX1_REQ_TIM17_CH1       111U  /*!< DMAMUX1 TIM17 CH1 request       */

+#define LL_DMAMUX1_REQ_TIM17_UP        112U  /*!< DMAMUX1 TIM17 UP request        */

+#if defined (SAI3)

+#define LL_DMAMUX1_REQ_SAI3_A          113U  /*!< DMAMUX1 SAI3 A request          */

+#define LL_DMAMUX1_REQ_SAI3_B          114U  /*!< DMAMUX1 SAI3 B request          */

+#endif /* SAI3 */

+#if defined (ADC3)

+#define LL_DMAMUX1_REQ_ADC3            115U  /*!< DMAMUX1 ADC3  request           */

+#endif /* ADC3 */

+#if defined (UART9)

+#define LL_DMAMUX1_REQ_UART9_RX        116U  /*!< DMAMUX1 UART9 RX request        */

+#define LL_DMAMUX1_REQ_UART9_TX        117U  /*!< DMAMUX1 UART9 TX request        */

+#endif /* UART9 */

+#if defined (USART10)

+#define LL_DMAMUX1_REQ_USART10_RX      118U  /*!< DMAMUX1 USART10 RX request      */

+#define LL_DMAMUX1_REQ_USART10_TX      119U  /*!< DMAMUX1 USART10 TX request      */

+#endif /* USART10 */

+

+/* DMAMUX2 requests */

+#define LL_DMAMUX2_REQ_MEM2MEM          0U  /*!< memory to memory transfer        */

+#define LL_DMAMUX2_REQ_GENERATOR0       1U  /*!< DMAMUX2 request generator 0      */

+#define LL_DMAMUX2_REQ_GENERATOR1       2U  /*!< DMAMUX2 request generator 1      */

+#define LL_DMAMUX2_REQ_GENERATOR2       3U  /*!< DMAMUX2 request generator 2      */

+#define LL_DMAMUX2_REQ_GENERATOR3       4U  /*!< DMAMUX2 request generator 3      */

+#define LL_DMAMUX2_REQ_GENERATOR4       5U  /*!< DMAMUX2 request generator 4      */

+#define LL_DMAMUX2_REQ_GENERATOR5       6U  /*!< DMAMUX2 request generator 5      */

+#define LL_DMAMUX2_REQ_GENERATOR6       7U  /*!< DMAMUX2 request generator 6      */

+#define LL_DMAMUX2_REQ_GENERATOR7       8U  /*!< DMAMUX2 request generator 7      */

+#define LL_DMAMUX2_REQ_LPUART1_RX       9U  /*!< DMAMUX2 LP_UART1_RX request      */

+#define LL_DMAMUX2_REQ_LPUART1_TX      10U  /*!< DMAMUX2 LP_UART1_TX request      */

+#define LL_DMAMUX2_REQ_SPI6_RX         11U  /*!< DMAMUX2 SPI6 RX request          */

+#define LL_DMAMUX2_REQ_SPI6_TX         12U  /*!< DMAMUX2 SPI6 TX request          */

+#define LL_DMAMUX2_REQ_I2C4_RX         13U  /*!< DMAMUX2 I2C4 RX request          */

+#define LL_DMAMUX2_REQ_I2C4_TX         14U  /*!< DMAMUX2 I2C4 TX request          */

+#if defined (SAI4)

+#define LL_DMAMUX2_REQ_SAI4_A          15U  /*!< DMAMUX2 SAI4 A request           */

+#define LL_DMAMUX2_REQ_SAI4_B          16U  /*!< DMAMUX2 SAI4 B request           */

+#endif /* SAI4 */

+#if defined (ADC3)

+#define LL_DMAMUX2_REQ_ADC3            17U  /*!< DMAMUX2 ADC3 request             */

+#endif /* ADC3 */

+#if defined (DAC2)

+#define LL_DMAMUX2_REQ_DAC2_CH1        17U  /*!< DMAMUX2 DAC2 CH1 request         */

+#endif /* DAC2 */

+#if defined (DFSDM2_Channel0)

+#define LL_DMAMUX2_REQ_DFSDM2_FLT0     18U  /*!< DMAMUX2 DFSDM2 Filter0 request   */

+#endif /* DFSDM2_Channel0 */

+/**

+  * @}

+  */

+

+

+/** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel

+  * @{

+  */

+#define LL_DMAMUX_CHANNEL_0     0x00000000U  /*!< DMAMUX1 Channel 0  connected to DMA1 Channel 0 , DMAMUX2 Channel 0 connected to BDMA Channel 0 */

+#define LL_DMAMUX_CHANNEL_1     0x00000001U  /*!< DMAMUX1 Channel 1  connected to DMA1 Channel 1 , DMAMUX2 Channel 1 connected to BDMA Channel 1 */

+#define LL_DMAMUX_CHANNEL_2     0x00000002U  /*!< DMAMUX1 Channel 2  connected to DMA1 Channel 2 , DMAMUX2 Channel 2 connected to BDMA Channel 2 */

+#define LL_DMAMUX_CHANNEL_3     0x00000003U  /*!< DMAMUX1 Channel 3  connected to DMA1 Channel 3 , DMAMUX2 Channel 3 connected to BDMA Channel 3 */

+#define LL_DMAMUX_CHANNEL_4     0x00000004U  /*!< DMAMUX1 Channel 4  connected to DMA1 Channel 4 , DMAMUX2 Channel 4 connected to BDMA Channel 4 */

+#define LL_DMAMUX_CHANNEL_5     0x00000005U  /*!< DMAMUX1 Channel 5  connected to DMA1 Channel 5 , DMAMUX2 Channel 5 connected to BDMA Channel 5 */

+#define LL_DMAMUX_CHANNEL_6     0x00000006U  /*!< DMAMUX1 Channel 6  connected to DMA1 Channel 6 , DMAMUX2 Channel 6 connected to BDMA Channel 6 */

+#define LL_DMAMUX_CHANNEL_7     0x00000007U  /*!< DMAMUX1 Channel 7  connected to DMA1 Channel 7 , DMAMUX2 Channel 7 connected to BDMA Channel 7 */

+#define LL_DMAMUX_CHANNEL_8     0x00000008U  /*!< DMAMUX1 Channel 8  connected to DMA2 Channel 0 */

+#define LL_DMAMUX_CHANNEL_9     0x00000009U  /*!< DMAMUX1 Channel 9  connected to DMA2 Channel 1 */

+#define LL_DMAMUX_CHANNEL_10    0x0000000AU  /*!< DMAMUX1 Channel 10 connected to DMA2 Channel 2 */

+#define LL_DMAMUX_CHANNEL_11    0x0000000BU  /*!< DMAMUX1 Channel 11 connected to DMA2 Channel 3 */

+#define LL_DMAMUX_CHANNEL_12    0x0000000CU  /*!< DMAMUX1 Channel 12 connected to DMA2 Channel 4 */

+#define LL_DMAMUX_CHANNEL_13    0x0000000DU  /*!< DMAMUX1 Channel 13 connected to DMA2 Channel 5 */

+#define LL_DMAMUX_CHANNEL_14    0x0000000EU  /*!< DMAMUX1 Channel 14 connected to DMA2 Channel 6 */

+#define LL_DMAMUX_CHANNEL_15    0x0000000FU  /*!< DMAMUX1 Channel 15 connected to DMA2 Channel 7 */

+/**

+  * @}

+  */

+

+/** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity

+  * @{

+  */

+#define LL_DMAMUX_SYNC_NO_EVENT            0x00000000U                               /*!< All requests are blocked                            */

+#define LL_DMAMUX_SYNC_POL_RISING          DMAMUX_CxCR_SPOL_0                        /*!< Synchronization on event on rising edge             */

+#define LL_DMAMUX_SYNC_POL_FALLING         DMAMUX_CxCR_SPOL_1                        /*!< Synchronization on event on falling edge            */

+#define LL_DMAMUX_SYNC_POL_RISING_FALLING  (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */

+/**

+  * @}

+  */

+

+/** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event

+  * @{

+  */

+#define LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT   0x00000000U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel0 Event */

+#define LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT   0x01000000U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel1 Event */

+#define LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT   0x02000000U   /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel2 Event */

+#define LL_DMAMUX1_SYNC_LPTIM1_OUT        0x03000000U   /*!< DMAMUX1 synchronization Signal is LPTIM1 OUT             */

+#define LL_DMAMUX1_SYNC_LPTIM2_OUT        0x04000000U   /*!< DMAMUX1 synchronization Signal is LPTIM2 OUT             */

+#define LL_DMAMUX1_SYNC_LPTIM3_OUT        0x05000000U   /*!< DMAMUX1 synchronization Signal is LPTIM3 OUT             */

+#define LL_DMAMUX1_SYNC_EXTI0             0x06000000U   /*!< DMAMUX1 synchronization Signal is EXTI0 IT               */

+#define LL_DMAMUX1_SYNC_TIM12_TRGO        0x07000000U   /*!< DMAMUX1 synchronization Signal is TIM12 TRGO             */

+

+#define LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT   0x00000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel0 Event */

+#define LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT   0x01000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel1 Event */

+#define LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT   0x02000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel2 Event */

+#define LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT   0x03000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel3 Event */

+#define LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT   0x04000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel4 Event */

+#define LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT   0x05000000U   /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel5 Event */

+#define LL_DMAMUX2_SYNC_LPUART1_RX_WKUP   0x06000000U   /*!< DMAMUX2 synchronization Signal is LPUART1 RX Wakeup      */

+#define LL_DMAMUX2_SYNC_LPUART1_TX_WKUP   0x07000000U   /*!< DMAMUX2 synchronization Signal is LPUART1 TX Wakeup      */

+#define LL_DMAMUX2_SYNC_LPTIM2_OUT        0x08000000U   /*!< DMAMUX2 synchronization Signal is LPTIM2 output          */

+#define LL_DMAMUX2_SYNC_LPTIM3_OUT        0x09000000U   /*!< DMAMUX2 synchronization Signal is LPTIM3 output          */

+#define LL_DMAMUX2_SYNC_I2C4_WKUP         0x0A000000U   /*!< DMAMUX2 synchronization Signal is I2C4 Wakeup            */

+#define LL_DMAMUX2_SYNC_SPI6_WKUP         0x0B000000U   /*!< DMAMUX2 synchronization Signal is SPI6 Wakeup            */

+#define LL_DMAMUX2_SYNC_COMP1_OUT         0x0C000000U   /*!< DMAMUX2 synchronization Signal is Comparator 1 output    */

+#define LL_DMAMUX2_SYNC_RTC_WKUP          0x0D000000U   /*!< DMAMUX2 synchronization Signal is RTC Wakeup             */

+#define LL_DMAMUX2_SYNC_EXTI0             0x0E000000U   /*!< DMAMUX2 synchronization Signal is EXTI0 IT               */

+#define LL_DMAMUX2_SYNC_EXTI2             0x0F000000U   /*!< DMAMUX2 synchronization Signal is EXTI2 IT               */

+

+/**

+  * @}

+  */

+

+/** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel

+  * @{

+  */

+#define LL_DMAMUX_REQ_GEN_0           0x00000000U

+#define LL_DMAMUX_REQ_GEN_1           0x00000001U

+#define LL_DMAMUX_REQ_GEN_2           0x00000002U

+#define LL_DMAMUX_REQ_GEN_3           0x00000003U

+#define LL_DMAMUX_REQ_GEN_4           0x00000004U

+#define LL_DMAMUX_REQ_GEN_5           0x00000005U

+#define LL_DMAMUX_REQ_GEN_6           0x00000006U

+#define LL_DMAMUX_REQ_GEN_7           0x00000007U

+/**

+  * @}

+  */

+

+/** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity

+  * @{

+  */

+#define LL_DMAMUX_REQ_GEN_NO_EVENT             0x00000000U                                  /*!< No external DMA request  generation                        */

+#define LL_DMAMUX_REQ_GEN_POL_RISING           DMAMUX_RGxCR_GPOL_0                          /*!< External DMA request generation on event on rising edge    */

+#define LL_DMAMUX_REQ_GEN_POL_FALLING          DMAMUX_RGxCR_GPOL_1                          /*!< External DMA request generation on event on falling edge   */

+#define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING   (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1)  /*!< External DMA request generation on rising and falling edge */

+/**

+  * @}

+  */

+

+/** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation

+  * @{

+  */

+#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT   0U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel0 Event        */

+#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT   1U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel1 Event        */

+#define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT   2U   /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel2 Event        */

+#define LL_DMAMUX1_REQ_GEN_LPTIM1_OUT        3U   /*!< DMAMUX1 Request generator Signal is LPTIM1 OUT                    */

+#define LL_DMAMUX1_REQ_GEN_LPTIM2_OUT        4U   /*!< DMAMUX1 Request generator Signal is LPTIM2 OUT                    */

+#define LL_DMAMUX1_REQ_GEN_LPTIM3_OUT        5U   /*!< DMAMUX1 Request generator Signal is LPTIM3 OUT                    */

+#define LL_DMAMUX1_REQ_GEN_EXTI0             6U   /*!< DMAMUX1 Request generator Signal is EXTI0 IT                      */

+#define LL_DMAMUX1_REQ_GEN_TIM12_TRGO        7U   /*!< DMAMUX1 Request generator Signal is TIM12 TRGO                    */

+

+#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT   0U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel0 Event        */

+#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT   1U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel1 Event        */

+#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT   2U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel2 Event        */

+#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT   3U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel3 Event        */

+#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT   4U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel4 Event        */

+#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT   5U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel5 Event        */

+#define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT   6U   /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel6 Event        */

+#define LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP   7U   /*!< DMAMUX2 Request generator Signal is LPUART1 RX Wakeup             */

+#define LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP   8U   /*!< DMAMUX2 Request generator Signal is LPUART1 TX Wakeup             */

+#define LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP       9U   /*!< DMAMUX2 Request generator Signal is LPTIM2 Wakeup                 */

+#define LL_DMAMUX2_REQ_GEN_LPTIM2_OUT       10U   /*!< DMAMUX2 Request generator Signal is LPTIM2 OUT                    */

+#define LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP      11U   /*!< DMAMUX2 Request generator Signal is LPTIM3 Wakeup                 */

+#define LL_DMAMUX2_REQ_GEN_LPTIM3_OUT       12U   /*!< DMAMUX2 Request generator Signal is LPTIM3 OUT                    */

+#if defined (LPTIM4)

+#define LL_DMAMUX2_REQ_GEN_LPTIM4_WKUP      13U   /*!< DMAMUX2 Request generator Signal is LPTIM4 Wakeup                 */

+#endif /* LPTIM4 */

+#if defined (LPTIM5)

+#define LL_DMAMUX2_REQ_GEN_LPTIM5_WKUP      14U   /*!< DMAMUX2 Request generator Signal is LPTIM5 Wakeup                 */

+#endif /* LPTIM5 */

+#define LL_DMAMUX2_REQ_GEN_I2C4_WKUP        15U   /*!< DMAMUX2 Request generator Signal is I2C4 Wakeup                   */

+#define LL_DMAMUX2_REQ_GEN_SPI6_WKUP        16U   /*!< DMAMUX2 Request generator Signal is SPI6 Wakeup                   */

+#define LL_DMAMUX2_REQ_GEN_COMP1_OUT        17U   /*!< DMAMUX2 Request generator Signal is Comparator 1 output           */

+#define LL_DMAMUX2_REQ_GEN_COMP2_OUT        18U   /*!< DMAMUX2 Request generator Signal is Comparator 2 output           */

+#define LL_DMAMUX2_REQ_GEN_RTC_WKUP         19U   /*!< DMAMUX2 Request generator Signal is RTC Wakeup                    */

+#define LL_DMAMUX2_REQ_GEN_EXTI0            20U   /*!< DMAMUX2 Request generator Signal is EXTI0                         */

+#define LL_DMAMUX2_REQ_GEN_EXTI2            21U   /*!< DMAMUX2 Request generator Signal is EXTI2                         */

+#define LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT      22U   /*!< DMAMUX2 Request generator Signal is I2C4 IT Event                 */

+#define LL_DMAMUX2_REQ_GEN_SPI6_IT          23U   /*!< DMAMUX2 Request generator Signal is SPI6 IT                       */

+#define LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT    24U   /*!< DMAMUX2 Request generator Signal is LPUART1 Tx IT                 */

+#define LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT    25U   /*!< DMAMUX2 Request generator Signal is LPUART1 Rx IT                 */

+#if defined (ADC3)

+#define LL_DMAMUX2_REQ_GEN_ADC3_IT          26U   /*!< DMAMUX2 Request generator Signal is ADC3 IT                       */

+#define LL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT    27U   /*!< DMAMUX2 Request generator Signal is ADC3 Analog Watchdog 1 output */

+#endif /* ADC3 */

+#define LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT      28U   /*!< DMAMUX2 Request generator Signal is BDMA Channel 0 IT             */

+#define LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT      29U   /*!< DMAMUX2 Request generator Signal is BDMA Channel 1 IT             */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros

+  * @{

+  */

+

+/** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros

+  * @{

+  */

+/**

+  * @brief  Write a value in DMAMUX register

+  * @param  __INSTANCE__ DMAMUX Instance

+  * @param  __REG__ Register to be written

+  * @param  __VALUE__ Value to be written in the register

+  * @retval None

+  */

+#define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

+

+/**

+  * @brief  Read a value in DMAMUX register

+  * @param  __INSTANCE__ DMAMUX Instance

+  * @param  __REG__ Register to be read

+  * @retval Register value

+  */

+#define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions

+ * @{

+ */

+

+/** @defgroup DMAMUX_LL_EF_Configuration Configuration

+  * @{

+  */

+/**

+  * @brief  Set DMAMUX request ID for DMAMUX Channel x.

+  * @note   DMAMUX1 channel 0 to 7 are mapped to DMA1 channel 0 to 7.

+  *         DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7.

+  *         DMAMUX2 channel 0 to 7 are mapped to  BDMA channel 0 to 7.

+  * @rmtoll CxCR         DMAREQ_ID     LL_DMAMUX_SetRequestID

+  * @param  DMAMUXx DMAMUXx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX_CHANNEL_0

+  *         @arg @ref LL_DMAMUX_CHANNEL_1

+  *         @arg @ref LL_DMAMUX_CHANNEL_2

+  *         @arg @ref LL_DMAMUX_CHANNEL_3

+  *         @arg @ref LL_DMAMUX_CHANNEL_4

+  *         @arg @ref LL_DMAMUX_CHANNEL_5

+  *         @arg @ref LL_DMAMUX_CHANNEL_6

+  *         @arg @ref LL_DMAMUX_CHANNEL_7

+  *         @arg @ref LL_DMAMUX_CHANNEL_8

+  *         @arg @ref LL_DMAMUX_CHANNEL_9

+  *         @arg @ref LL_DMAMUX_CHANNEL_10

+  *         @arg @ref LL_DMAMUX_CHANNEL_11

+  *         @arg @ref LL_DMAMUX_CHANNEL_12

+  *         @arg @ref LL_DMAMUX_CHANNEL_13

+  *         @arg @ref LL_DMAMUX_CHANNEL_14

+  *         @arg @ref LL_DMAMUX_CHANNEL_15

+  * @param  Request This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX1_REQ_MEM2MEM

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR0

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR1

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR2

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR3

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR4

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR5

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR6

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR7

+  *         @arg @ref LL_DMAMUX1_REQ_ADC1

+  *         @arg @ref LL_DMAMUX1_REQ_ADC2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH3

+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH4

+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG

+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_COM

+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH3

+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH4

+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH3

+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH4

+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG

+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH3

+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_UP

+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_RX

+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_TX

+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_RX

+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_TX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_RX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_TX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_RX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_TX

+  *         @arg @ref LL_DMAMUX1_REQ_USART1_RX

+  *         @arg @ref LL_DMAMUX1_REQ_USART1_TX

+  *         @arg @ref LL_DMAMUX1_REQ_USART2_RX

+  *         @arg @ref LL_DMAMUX1_REQ_USART2_TX

+  *         @arg @ref LL_DMAMUX1_REQ_USART3_RX

+  *         @arg @ref LL_DMAMUX1_REQ_USART3_TX

+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH3

+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH4

+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG

+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_COM

+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH3

+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH4

+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG

+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_RX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_TX

+  *         @arg @ref LL_DMAMUX1_REQ_UART4_RX

+  *         @arg @ref LL_DMAMUX1_REQ_UART4_TX

+  *         @arg @ref LL_DMAMUX1_REQ_UART5_RX

+  *         @arg @ref LL_DMAMUX1_REQ_UART5_TX

+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM6_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM7_UP

+  *         @arg @ref LL_DMAMUX1_REQ_USART6_RX

+  *         @arg @ref LL_DMAMUX1_REQ_USART6_TX

+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_RX

+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_TX

+  *         @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI

+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_IN

+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_OUT

+  *         @arg @ref LL_DMAMUX1_REQ_HASH_IN

+  *         @arg @ref LL_DMAMUX1_REQ_UART7_RX

+  *         @arg @ref LL_DMAMUX1_REQ_UART7_TX

+  *         @arg @ref LL_DMAMUX1_REQ_UART8_RX

+  *         @arg @ref LL_DMAMUX1_REQ_UART8_TX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_RX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_TX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_RX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_TX

+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_A

+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_B

+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_A

+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_B

+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_RX

+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_TX

+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT

+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS

+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)

+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)

+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)

+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)

+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)

+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)

+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0

+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1

+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2

+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3

+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG

+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_COM

+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_UP

+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)

+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)

+  *         @arg @ref LL_DMAMUX1_REQ_ADC3 (*)

+  *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)

+  *         @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)

+  *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)

+  *         @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)

+  *         @arg @ref LL_DMAMUX2_REQ_MEM2MEM

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR0

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR1

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR2

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR3

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR4

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR5

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR6

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR7

+  *         @arg @ref LL_DMAMUX2_REQ_LPUART1_RX

+  *         @arg @ref LL_DMAMUX2_REQ_LPUART1_TX

+  *         @arg @ref LL_DMAMUX2_REQ_SPI6_RX

+  *         @arg @ref LL_DMAMUX2_REQ_SPI6_TX

+  *         @arg @ref LL_DMAMUX2_REQ_I2C4_RX

+  *         @arg @ref LL_DMAMUX2_REQ_I2C4_TX

+  *         @arg @ref LL_DMAMUX2_REQ_SAI4_A (*)

+  *         @arg @ref LL_DMAMUX2_REQ_SAI4_B (*)

+  *         @arg @ref LL_DMAMUX2_REQ_ADC3 (*)

+  *         @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*)

+  *         @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*)

+  * @note   (*) Availability depends on devices.

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);

+}

+

+/**

+  * @brief  Get DMAMUX request ID for DMAMUX Channel x.

+  * @note   DMAMUX1 channel 0 to 7  are mapped to DMA1 channel 0 to 7.

+  *         DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7.

+  *         DMAMUX2 channel 0 to 7  are mapped to BDMA channel 0 to 7.

+  * @rmtoll CxCR         DMAREQ_ID     LL_DMAMUX_GetRequestID

+  * @param  DMAMUXx DMAMUXx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX_CHANNEL_0

+  *         @arg @ref LL_DMAMUX_CHANNEL_1

+  *         @arg @ref LL_DMAMUX_CHANNEL_2

+  *         @arg @ref LL_DMAMUX_CHANNEL_3

+  *         @arg @ref LL_DMAMUX_CHANNEL_4

+  *         @arg @ref LL_DMAMUX_CHANNEL_5

+  *         @arg @ref LL_DMAMUX_CHANNEL_6

+  *         @arg @ref LL_DMAMUX_CHANNEL_7

+  *         @arg @ref LL_DMAMUX_CHANNEL_8

+  *         @arg @ref LL_DMAMUX_CHANNEL_9

+  *         @arg @ref LL_DMAMUX_CHANNEL_10

+  *         @arg @ref LL_DMAMUX_CHANNEL_11

+  *         @arg @ref LL_DMAMUX_CHANNEL_12

+  *         @arg @ref LL_DMAMUX_CHANNEL_13

+  *         @arg @ref LL_DMAMUX_CHANNEL_14

+  *         @arg @ref LL_DMAMUX_CHANNEL_15

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMAMUX1_REQ_MEM2MEM

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR0

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR1

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR2

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR3

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR4

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR5

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR6

+  *         @arg @ref LL_DMAMUX1_REQ_GENERATOR7

+  *         @arg @ref LL_DMAMUX1_REQ_ADC1

+  *         @arg @ref LL_DMAMUX1_REQ_ADC2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH3

+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_CH4

+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG

+  *         @arg @ref LL_DMAMUX1_REQ_TIM1_COM

+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH3

+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_CH4

+  *         @arg @ref LL_DMAMUX1_REQ_TIM2_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH3

+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_CH4

+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG

+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_CH3

+  *         @arg @ref LL_DMAMUX1_REQ_TIM4_UP

+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_RX

+  *         @arg @ref LL_DMAMUX1_REQ_I2C1_TX

+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_RX

+  *         @arg @ref LL_DMAMUX1_REQ_I2C2_TX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_RX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI1_TX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_RX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI2_TX

+  *         @arg @ref LL_DMAMUX1_REQ_USART1_RX

+  *         @arg @ref LL_DMAMUX1_REQ_USART1_TX

+  *         @arg @ref LL_DMAMUX1_REQ_USART2_RX

+  *         @arg @ref LL_DMAMUX1_REQ_USART2_TX

+  *         @arg @ref LL_DMAMUX1_REQ_USART3_RX

+  *         @arg @ref LL_DMAMUX1_REQ_USART3_TX

+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH3

+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_CH4

+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG

+  *         @arg @ref LL_DMAMUX1_REQ_TIM8_COM

+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH3

+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_CH4

+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG

+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_RX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI3_TX

+  *         @arg @ref LL_DMAMUX1_REQ_UART4_RX

+  *         @arg @ref LL_DMAMUX1_REQ_UART4_TX

+  *         @arg @ref LL_DMAMUX1_REQ_UART5_RX

+  *         @arg @ref LL_DMAMUX1_REQ_UART5_TX

+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_DAC1_CH2

+  *         @arg @ref LL_DMAMUX1_REQ_TIM6_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM7_UP

+  *         @arg @ref LL_DMAMUX1_REQ_USART6_RX

+  *         @arg @ref LL_DMAMUX1_REQ_USART6_TX

+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_RX

+  *         @arg @ref LL_DMAMUX1_REQ_I2C3_TX

+  *         @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI

+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_IN

+  *         @arg @ref LL_DMAMUX1_REQ_CRYP_OUT

+  *         @arg @ref LL_DMAMUX1_REQ_HASH_IN

+  *         @arg @ref LL_DMAMUX1_REQ_UART7_RX

+  *         @arg @ref LL_DMAMUX1_REQ_UART7_TX

+  *         @arg @ref LL_DMAMUX1_REQ_UART8_RX

+  *         @arg @ref LL_DMAMUX1_REQ_UART8_TX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_RX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI4_TX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_RX

+  *         @arg @ref LL_DMAMUX1_REQ_SPI5_TX

+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_A

+  *         @arg @ref LL_DMAMUX1_REQ_SAI1_B

+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_A

+  *         @arg @ref LL_DMAMUX1_REQ_SAI2_B

+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_RX

+  *         @arg @ref LL_DMAMUX1_REQ_SWPMI_TX

+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT

+  *         @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS

+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)

+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)

+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)

+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)

+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)

+  *         @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)

+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0

+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1

+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2

+  *         @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3

+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG

+  *         @arg @ref LL_DMAMUX1_REQ_TIM15_COM

+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM16_UP

+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_CH1

+  *         @arg @ref LL_DMAMUX1_REQ_TIM17_UP

+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)

+  *         @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)

+  *         @arg @ref LL_DMAMUX1_REQ_ADC3 (*)

+  *         @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)

+  *         @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)

+  *         @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)

+  *         @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)

+  *         @arg @ref LL_DMAMUX2_REQ_MEM2MEM

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR0

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR1

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR2

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR3

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR4

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR5

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR6

+  *         @arg @ref LL_DMAMUX2_REQ_GENERATOR7

+  *         @arg @ref LL_DMAMUX2_REQ_LPUART1_RX

+  *         @arg @ref LL_DMAMUX2_REQ_LPUART1_TX

+  *         @arg @ref LL_DMAMUX2_REQ_SPI6_RX

+  *         @arg @ref LL_DMAMUX2_REQ_SPI6_TX

+  *         @arg @ref LL_DMAMUX2_REQ_I2C4_RX

+  *         @arg @ref LL_DMAMUX2_REQ_I2C4_TX

+  *         @arg @ref LL_DMAMUX2_REQ_SAI4_A (*)

+  *         @arg @ref LL_DMAMUX2_REQ_SAI4_B (*)

+  *         @arg @ref LL_DMAMUX2_REQ_ADC3 (*)

+  *         @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*)

+  *         @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*)

+  * @note   (*) Availability depends on devices.

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID));

+}

+

+/**

+  * @brief  Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.

+  * @rmtoll CxCR         NBREQ         LL_DMAMUX_SetSyncRequestNb

+  * @param  DMAMUXx DMAMUXx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX_CHANNEL_0

+  *         @arg @ref LL_DMAMUX_CHANNEL_1

+  *         @arg @ref LL_DMAMUX_CHANNEL_2

+  *         @arg @ref LL_DMAMUX_CHANNEL_3

+  *         @arg @ref LL_DMAMUX_CHANNEL_4

+  *         @arg @ref LL_DMAMUX_CHANNEL_5

+  *         @arg @ref LL_DMAMUX_CHANNEL_6

+  *         @arg @ref LL_DMAMUX_CHANNEL_7

+  *         @arg @ref LL_DMAMUX_CHANNEL_8

+  *         @arg @ref LL_DMAMUX_CHANNEL_9

+  *         @arg @ref LL_DMAMUX_CHANNEL_10

+  *         @arg @ref LL_DMAMUX_CHANNEL_11

+  *         @arg @ref LL_DMAMUX_CHANNEL_12

+  *         @arg @ref LL_DMAMUX_CHANNEL_13

+  *         @arg @ref LL_DMAMUX_CHANNEL_14

+  *         @arg @ref LL_DMAMUX_CHANNEL_15

+  * @param  RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ, (RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos);

+}

+

+/**

+  * @brief  Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.

+  * @rmtoll CxCR         NBREQ         LL_DMAMUX_GetSyncRequestNb

+  * @param  DMAMUXx DMAMUXx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX_CHANNEL_0

+  *         @arg @ref LL_DMAMUX_CHANNEL_1

+  *         @arg @ref LL_DMAMUX_CHANNEL_2

+  *         @arg @ref LL_DMAMUX_CHANNEL_3

+  *         @arg @ref LL_DMAMUX_CHANNEL_4

+  *         @arg @ref LL_DMAMUX_CHANNEL_5

+  *         @arg @ref LL_DMAMUX_CHANNEL_6

+  *         @arg @ref LL_DMAMUX_CHANNEL_7

+  *         @arg @ref LL_DMAMUX_CHANNEL_8

+  *         @arg @ref LL_DMAMUX_CHANNEL_9

+  *         @arg @ref LL_DMAMUX_CHANNEL_10

+  *         @arg @ref LL_DMAMUX_CHANNEL_11

+  *         @arg @ref LL_DMAMUX_CHANNEL_12

+  *         @arg @ref LL_DMAMUX_CHANNEL_13

+  *         @arg @ref LL_DMAMUX_CHANNEL_14

+  *         @arg @ref LL_DMAMUX_CHANNEL_15

+  * @retval Between Min_Data = 1 and Max_Data = 32

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return (uint32_t)((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ) >> DMAMUX_CxCR_NBREQ_Pos) + 1U);

+}

+

+/**

+  * @brief  Set the polarity of the signal on which the DMA request is synchronized.

+  * @rmtoll CxCR         SPOL          LL_DMAMUX_SetSyncPolarity

+  * @param  DMAMUXx DMAMUXx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX_CHANNEL_0

+  *         @arg @ref LL_DMAMUX_CHANNEL_1

+  *         @arg @ref LL_DMAMUX_CHANNEL_2

+  *         @arg @ref LL_DMAMUX_CHANNEL_3

+  *         @arg @ref LL_DMAMUX_CHANNEL_4

+  *         @arg @ref LL_DMAMUX_CHANNEL_5

+  *         @arg @ref LL_DMAMUX_CHANNEL_6

+  *         @arg @ref LL_DMAMUX_CHANNEL_7

+  *         @arg @ref LL_DMAMUX_CHANNEL_8

+  *         @arg @ref LL_DMAMUX_CHANNEL_9

+  *         @arg @ref LL_DMAMUX_CHANNEL_10

+  *         @arg @ref LL_DMAMUX_CHANNEL_11

+  *         @arg @ref LL_DMAMUX_CHANNEL_12

+  *         @arg @ref LL_DMAMUX_CHANNEL_13

+  *         @arg @ref LL_DMAMUX_CHANNEL_14

+  *         @arg @ref LL_DMAMUX_CHANNEL_15

+  * @param  Polarity This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX_SYNC_NO_EVENT

+  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING

+  *         @arg @ref LL_DMAMUX_SYNC_POL_FALLING

+  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL, Polarity);

+}

+

+/**

+  * @brief  Get the polarity of the signal on which the DMA request is synchronized.

+  * @rmtoll CxCR         SPOL          LL_DMAMUX_GetSyncPolarity

+  * @param  DMAMUXx DMAMUXx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX_CHANNEL_0

+  *         @arg @ref LL_DMAMUX_CHANNEL_1

+  *         @arg @ref LL_DMAMUX_CHANNEL_2

+  *         @arg @ref LL_DMAMUX_CHANNEL_3

+  *         @arg @ref LL_DMAMUX_CHANNEL_4

+  *         @arg @ref LL_DMAMUX_CHANNEL_5

+  *         @arg @ref LL_DMAMUX_CHANNEL_6

+  *         @arg @ref LL_DMAMUX_CHANNEL_7

+  *         @arg @ref LL_DMAMUX_CHANNEL_8

+  *         @arg @ref LL_DMAMUX_CHANNEL_9

+  *         @arg @ref LL_DMAMUX_CHANNEL_10

+  *         @arg @ref LL_DMAMUX_CHANNEL_11

+  *         @arg @ref LL_DMAMUX_CHANNEL_12

+  *         @arg @ref LL_DMAMUX_CHANNEL_13

+  *         @arg @ref LL_DMAMUX_CHANNEL_14

+  *         @arg @ref LL_DMAMUX_CHANNEL_15

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMAMUX_SYNC_NO_EVENT

+  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING

+  *         @arg @ref LL_DMAMUX_SYNC_POL_FALLING

+  *         @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL));

+}

+

+/**

+  * @brief  Enable the Event Generation on DMAMUX channel x.

+  * @rmtoll CxCR         EGE           LL_DMAMUX_EnableEventGeneration

+  * @param  DMAMUXx DMAMUXx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX_CHANNEL_0

+  *         @arg @ref LL_DMAMUX_CHANNEL_1

+  *         @arg @ref LL_DMAMUX_CHANNEL_2

+  *         @arg @ref LL_DMAMUX_CHANNEL_3

+  *         @arg @ref LL_DMAMUX_CHANNEL_4

+  *         @arg @ref LL_DMAMUX_CHANNEL_5

+  *         @arg @ref LL_DMAMUX_CHANNEL_6

+  *         @arg @ref LL_DMAMUX_CHANNEL_7

+  *         @arg @ref LL_DMAMUX_CHANNEL_8

+  *         @arg @ref LL_DMAMUX_CHANNEL_9

+  *         @arg @ref LL_DMAMUX_CHANNEL_10

+  *         @arg @ref LL_DMAMUX_CHANNEL_11

+  *         @arg @ref LL_DMAMUX_CHANNEL_12

+  *         @arg @ref LL_DMAMUX_CHANNEL_13

+  *         @arg @ref LL_DMAMUX_CHANNEL_14

+  *         @arg @ref LL_DMAMUX_CHANNEL_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE);

+}

+

+/**

+  * @brief  Disable the Event Generation on DMAMUX channel x.

+  * @rmtoll CxCR         EGE           LL_DMAMUX_DisableEventGeneration

+  * @param  DMAMUXx DMAMUXx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX_CHANNEL_0

+  *         @arg @ref LL_DMAMUX_CHANNEL_1

+  *         @arg @ref LL_DMAMUX_CHANNEL_2

+  *         @arg @ref LL_DMAMUX_CHANNEL_3

+  *         @arg @ref LL_DMAMUX_CHANNEL_4

+  *         @arg @ref LL_DMAMUX_CHANNEL_5

+  *         @arg @ref LL_DMAMUX_CHANNEL_6

+  *         @arg @ref LL_DMAMUX_CHANNEL_7

+  *         @arg @ref LL_DMAMUX_CHANNEL_8

+  *         @arg @ref LL_DMAMUX_CHANNEL_9

+  *         @arg @ref LL_DMAMUX_CHANNEL_10

+  *         @arg @ref LL_DMAMUX_CHANNEL_11

+  *         @arg @ref LL_DMAMUX_CHANNEL_12

+  *         @arg @ref LL_DMAMUX_CHANNEL_13

+  *         @arg @ref LL_DMAMUX_CHANNEL_14

+  *         @arg @ref LL_DMAMUX_CHANNEL_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE);

+}

+

+/**

+  * @brief  Check if the Event Generation on DMAMUX channel x is enabled or disabled.

+  * @rmtoll CxCR         EGE           LL_DMAMUX_IsEnabledEventGeneration

+  * @param  DMAMUXx DMAMUXx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX_CHANNEL_0

+  *         @arg @ref LL_DMAMUX_CHANNEL_1

+  *         @arg @ref LL_DMAMUX_CHANNEL_2

+  *         @arg @ref LL_DMAMUX_CHANNEL_3

+  *         @arg @ref LL_DMAMUX_CHANNEL_4

+  *         @arg @ref LL_DMAMUX_CHANNEL_5

+  *         @arg @ref LL_DMAMUX_CHANNEL_6

+  *         @arg @ref LL_DMAMUX_CHANNEL_7

+  *         @arg @ref LL_DMAMUX_CHANNEL_8

+  *         @arg @ref LL_DMAMUX_CHANNEL_9

+  *         @arg @ref LL_DMAMUX_CHANNEL_10

+  *         @arg @ref LL_DMAMUX_CHANNEL_11

+  *         @arg @ref LL_DMAMUX_CHANNEL_12

+  *         @arg @ref LL_DMAMUX_CHANNEL_13

+  *         @arg @ref LL_DMAMUX_CHANNEL_14

+  *         @arg @ref LL_DMAMUX_CHANNEL_15

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the synchronization mode.

+  * @rmtoll CxCR         SE            LL_DMAMUX_EnableSync

+  * @param  DMAMUXx DMAMUXx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX_CHANNEL_0

+  *         @arg @ref LL_DMAMUX_CHANNEL_1

+  *         @arg @ref LL_DMAMUX_CHANNEL_2

+  *         @arg @ref LL_DMAMUX_CHANNEL_3

+  *         @arg @ref LL_DMAMUX_CHANNEL_4

+  *         @arg @ref LL_DMAMUX_CHANNEL_5

+  *         @arg @ref LL_DMAMUX_CHANNEL_6

+  *         @arg @ref LL_DMAMUX_CHANNEL_7

+  *         @arg @ref LL_DMAMUX_CHANNEL_8

+  *         @arg @ref LL_DMAMUX_CHANNEL_9

+  *         @arg @ref LL_DMAMUX_CHANNEL_10

+  *         @arg @ref LL_DMAMUX_CHANNEL_11

+  *         @arg @ref LL_DMAMUX_CHANNEL_12

+  *         @arg @ref LL_DMAMUX_CHANNEL_13

+  *         @arg @ref LL_DMAMUX_CHANNEL_14

+  *         @arg @ref LL_DMAMUX_CHANNEL_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE);

+}

+

+/**

+  * @brief  Disable the synchronization mode.

+  * @rmtoll CxCR         SE            LL_DMAMUX_DisableSync

+  * @param  DMAMUXx DMAMUXx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX_CHANNEL_0

+  *         @arg @ref LL_DMAMUX_CHANNEL_1

+  *         @arg @ref LL_DMAMUX_CHANNEL_2

+  *         @arg @ref LL_DMAMUX_CHANNEL_3

+  *         @arg @ref LL_DMAMUX_CHANNEL_4

+  *         @arg @ref LL_DMAMUX_CHANNEL_5

+  *         @arg @ref LL_DMAMUX_CHANNEL_6

+  *         @arg @ref LL_DMAMUX_CHANNEL_7

+  *         @arg @ref LL_DMAMUX_CHANNEL_8

+  *         @arg @ref LL_DMAMUX_CHANNEL_9

+  *         @arg @ref LL_DMAMUX_CHANNEL_10

+  *         @arg @ref LL_DMAMUX_CHANNEL_11

+  *         @arg @ref LL_DMAMUX_CHANNEL_12

+  *         @arg @ref LL_DMAMUX_CHANNEL_13

+  *         @arg @ref LL_DMAMUX_CHANNEL_14

+  *         @arg @ref LL_DMAMUX_CHANNEL_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE);

+}

+

+/**

+  * @brief  Check if the synchronization mode is enabled or disabled.

+  * @rmtoll CxCR         SE            LL_DMAMUX_IsEnabledSync

+  * @param  DMAMUXx DMAMUXx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX_CHANNEL_0

+  *         @arg @ref LL_DMAMUX_CHANNEL_1

+  *         @arg @ref LL_DMAMUX_CHANNEL_2

+  *         @arg @ref LL_DMAMUX_CHANNEL_3

+  *         @arg @ref LL_DMAMUX_CHANNEL_4

+  *         @arg @ref LL_DMAMUX_CHANNEL_5

+  *         @arg @ref LL_DMAMUX_CHANNEL_6

+  *         @arg @ref LL_DMAMUX_CHANNEL_7

+  *         @arg @ref LL_DMAMUX_CHANNEL_8

+  *         @arg @ref LL_DMAMUX_CHANNEL_9

+  *         @arg @ref LL_DMAMUX_CHANNEL_10

+  *         @arg @ref LL_DMAMUX_CHANNEL_11

+  *         @arg @ref LL_DMAMUX_CHANNEL_12

+  *         @arg @ref LL_DMAMUX_CHANNEL_13

+  *         @arg @ref LL_DMAMUX_CHANNEL_14

+  *         @arg @ref LL_DMAMUX_CHANNEL_15

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set DMAMUX synchronization ID  on DMAMUX Channel x.

+  * @rmtoll CxCR         SYNC_ID       LL_DMAMUX_SetSyncID

+  * @param  DMAMUXx DMAMUXx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX_CHANNEL_0

+  *         @arg @ref LL_DMAMUX_CHANNEL_1

+  *         @arg @ref LL_DMAMUX_CHANNEL_2

+  *         @arg @ref LL_DMAMUX_CHANNEL_3

+  *         @arg @ref LL_DMAMUX_CHANNEL_4

+  *         @arg @ref LL_DMAMUX_CHANNEL_5

+  *         @arg @ref LL_DMAMUX_CHANNEL_6

+  *         @arg @ref LL_DMAMUX_CHANNEL_7

+  *         @arg @ref LL_DMAMUX_CHANNEL_8

+  *         @arg @ref LL_DMAMUX_CHANNEL_9

+  *         @arg @ref LL_DMAMUX_CHANNEL_10

+  *         @arg @ref LL_DMAMUX_CHANNEL_11

+  *         @arg @ref LL_DMAMUX_CHANNEL_12

+  *         @arg @ref LL_DMAMUX_CHANNEL_13

+  *         @arg @ref LL_DMAMUX_CHANNEL_14

+  *         @arg @ref LL_DMAMUX_CHANNEL_15

+  * @param  SyncID This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT

+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT

+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT

+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT

+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT

+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT

+  *         @arg @ref LL_DMAMUX1_SYNC_EXTI0

+  *         @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO

+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT

+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT

+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT

+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT

+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT

+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT

+  *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP

+  *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP

+  *         @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT

+  *         @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT

+  *         @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP

+  *         @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP

+  *         @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT

+  *         @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP

+  *         @arg @ref LL_DMAMUX2_SYNC_EXTI0

+  *         @arg @ref LL_DMAMUX2_SYNC_EXTI2

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID, SyncID);

+}

+

+/**

+  * @brief  Get DMAMUX synchronization ID  on DMAMUX Channel x.

+  * @rmtoll CxCR         SYNC_ID       LL_DMAMUX_GetSyncID

+  * @param  DMAMUXx DMAMUXx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX_CHANNEL_0

+  *         @arg @ref LL_DMAMUX_CHANNEL_1

+  *         @arg @ref LL_DMAMUX_CHANNEL_2

+  *         @arg @ref LL_DMAMUX_CHANNEL_3

+  *         @arg @ref LL_DMAMUX_CHANNEL_4

+  *         @arg @ref LL_DMAMUX_CHANNEL_5

+  *         @arg @ref LL_DMAMUX_CHANNEL_6

+  *         @arg @ref LL_DMAMUX_CHANNEL_7

+  *         @arg @ref LL_DMAMUX_CHANNEL_8

+  *         @arg @ref LL_DMAMUX_CHANNEL_9

+  *         @arg @ref LL_DMAMUX_CHANNEL_10

+  *         @arg @ref LL_DMAMUX_CHANNEL_11

+  *         @arg @ref LL_DMAMUX_CHANNEL_12

+  *         @arg @ref LL_DMAMUX_CHANNEL_13

+  *         @arg @ref LL_DMAMUX_CHANNEL_14

+  *         @arg @ref LL_DMAMUX_CHANNEL_15

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT

+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT

+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT

+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT

+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT

+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT

+  *         @arg @ref LL_DMAMUX1_SYNC_EXTI0

+  *         @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO

+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT

+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT

+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT

+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT

+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT

+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT

+  *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP

+  *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP

+  *         @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT

+  *         @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT

+  *         @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP

+  *         @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP

+  *         @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT

+  *         @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP

+  *         @arg @ref LL_DMAMUX2_SYNC_EXTI0

+  *         @arg @ref LL_DMAMUX2_SYNC_EXTI2

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID));

+}

+

+/**

+  * @brief  Enable the Request Generator.

+  * @rmtoll RGxCR        GE            LL_DMAMUX_EnableRequestGen

+  * @param  DMAMUXx DMAMUXx Instance

+  * @param  RequestGenChannel This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX_REQ_GEN_0

+  *         @arg @ref LL_DMAMUX_REQ_GEN_1

+  *         @arg @ref LL_DMAMUX_REQ_GEN_2

+  *         @arg @ref LL_DMAMUX_REQ_GEN_3

+  *         @arg @ref LL_DMAMUX_REQ_GEN_4

+  *         @arg @ref LL_DMAMUX_REQ_GEN_5

+  *         @arg @ref LL_DMAMUX_REQ_GEN_6

+  *         @arg @ref LL_DMAMUX_REQ_GEN_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE);

+}

+

+/**

+  * @brief  Disable the Request Generator.

+  * @rmtoll RGxCR        GE            LL_DMAMUX_DisableRequestGen

+  * @param  DMAMUXx DMAMUXx Instance

+  * @param  RequestGenChannel This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX_REQ_GEN_0

+  *         @arg @ref LL_DMAMUX_REQ_GEN_1

+  *         @arg @ref LL_DMAMUX_REQ_GEN_2

+  *         @arg @ref LL_DMAMUX_REQ_GEN_3

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE);

+}

+

+/**

+  * @brief  Check if the Request Generator is enabled or disabled.

+  * @rmtoll RGxCR        GE            LL_DMAMUX_IsEnabledRequestGen

+  * @param  DMAMUXx DMAMUXx Instance

+  * @param  RequestGenChannel This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX_REQ_GEN_0

+  *         @arg @ref LL_DMAMUX_REQ_GEN_1

+  *         @arg @ref LL_DMAMUX_REQ_GEN_2

+  *         @arg @ref LL_DMAMUX_REQ_GEN_3

+  *         @arg @ref LL_DMAMUX_REQ_GEN_4

+  *         @arg @ref LL_DMAMUX_REQ_GEN_5

+  *         @arg @ref LL_DMAMUX_REQ_GEN_6

+  *         @arg @ref LL_DMAMUX_REQ_GEN_7

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set the polarity of the signal on which the DMA request is generated.

+  * @rmtoll RGxCR        GPOL          LL_DMAMUX_SetRequestGenPolarity

+  * @param  DMAMUXx DMAMUXx Instance

+  * @param  RequestGenChannel This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX_REQ_GEN_0

+  *         @arg @ref LL_DMAMUX_REQ_GEN_1

+  *         @arg @ref LL_DMAMUX_REQ_GEN_2

+  *         @arg @ref LL_DMAMUX_REQ_GEN_3

+  *         @arg @ref LL_DMAMUX_REQ_GEN_4

+  *         @arg @ref LL_DMAMUX_REQ_GEN_5

+  *         @arg @ref LL_DMAMUX_REQ_GEN_6

+  *         @arg @ref LL_DMAMUX_REQ_GEN_7

+  * @param  Polarity This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT

+  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING

+  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING

+  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL, Polarity);

+}

+

+/**

+  * @brief  Get the polarity of the signal on which the DMA request is generated.

+  * @rmtoll RGxCR        GPOL          LL_DMAMUX_GetRequestGenPolarity

+  * @param  DMAMUXx DMAMUXx Instance

+  * @param  RequestGenChannel This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX_REQ_GEN_0

+  *         @arg @ref LL_DMAMUX_REQ_GEN_1

+  *         @arg @ref LL_DMAMUX_REQ_GEN_2

+  *         @arg @ref LL_DMAMUX_REQ_GEN_3

+  *         @arg @ref LL_DMAMUX_REQ_GEN_4

+  *         @arg @ref LL_DMAMUX_REQ_GEN_5

+  *         @arg @ref LL_DMAMUX_REQ_GEN_6

+  *         @arg @ref LL_DMAMUX_REQ_GEN_7

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT

+  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING

+  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING

+  *         @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL));

+}

+

+/**

+  * @brief  Set the number of DMA request that will be autorized after a generation event.

+  * @note   This field can only be written when Generator is disabled.

+  * @rmtoll RGxCR        GNBREQ        LL_DMAMUX_SetGenRequestNb

+  * @param  DMAMUXx DMAMUXx Instance

+  * @param  RequestGenChannel This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX_REQ_GEN_0

+  *         @arg @ref LL_DMAMUX_REQ_GEN_1

+  *         @arg @ref LL_DMAMUX_REQ_GEN_2

+  *         @arg @ref LL_DMAMUX_REQ_GEN_3

+  *         @arg @ref LL_DMAMUX_REQ_GEN_4

+  *         @arg @ref LL_DMAMUX_REQ_GEN_5

+  *         @arg @ref LL_DMAMUX_REQ_GEN_6

+  *         @arg @ref LL_DMAMUX_REQ_GEN_7

+  * @param  RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos);

+}

+

+/**

+  * @brief  Get the number of DMA request that will be autorized after a generation event.

+  * @rmtoll RGxCR        GNBREQ        LL_DMAMUX_GetGenRequestNb

+  * @param  DMAMUXx DMAMUXx Instance

+  * @param  RequestGenChannel This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX_REQ_GEN_0

+  *         @arg @ref LL_DMAMUX_REQ_GEN_1

+  *         @arg @ref LL_DMAMUX_REQ_GEN_2

+  *         @arg @ref LL_DMAMUX_REQ_GEN_3

+  *         @arg @ref LL_DMAMUX_REQ_GEN_4

+  *         @arg @ref LL_DMAMUX_REQ_GEN_5

+  *         @arg @ref LL_DMAMUX_REQ_GEN_6

+  *         @arg @ref LL_DMAMUX_REQ_GEN_7

+  * @retval Between Min_Data = 1 and Max_Data = 32

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U);

+}

+

+/**

+  * @brief  Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.

+  * @rmtoll RGxCR        SIG_ID        LL_DMAMUX_SetRequestSignalID

+  * @param  DMAMUXx DMAMUXx Instance

+  * @param  RequestGenChannel This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX_REQ_GEN_0

+  *         @arg @ref LL_DMAMUX_REQ_GEN_1

+  *         @arg @ref LL_DMAMUX_REQ_GEN_2

+  *         @arg @ref LL_DMAMUX_REQ_GEN_3

+  *         @arg @ref LL_DMAMUX_REQ_GEN_4

+  *         @arg @ref LL_DMAMUX_REQ_GEN_5

+  *         @arg @ref LL_DMAMUX_REQ_GEN_6

+  *         @arg @ref LL_DMAMUX_REQ_GEN_7

+  * @param  RequestSignalID This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT

+  *         @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT

+  *         @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT

+  *         @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM1_OUT

+  *         @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM2_OUT

+  *         @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM3_OUT

+  *         @arg @ref LL_DMAMUX1_REQ_GEN_EXTI0

+  *         @arg @ref LL_DMAMUX1_REQ_GEN_TIM12_TRGO

+  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT

+  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT

+  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT

+  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT

+  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT

+  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT

+  *         @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT

+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP

+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP

+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP

+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM2_OUT

+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP

+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM3_OUT

+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM4_WKUP (*)

+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM5_WKUP (*)

+  *         @arg @ref LL_DMAMUX2_REQ_GEN_I2C4_WKUP

+  *         @arg @ref LL_DMAMUX2_REQ_GEN_SPI6_WKUP

+  *         @arg @ref LL_DMAMUX2_REQ_GEN_COMP1_OUT

+  *         @arg @ref LL_DMAMUX2_REQ_GEN_COMP2_OUT

+  *         @arg @ref LL_DMAMUX2_REQ_GEN_RTC_WKUP

+  *         @arg @ref LL_DMAMUX2_REQ_GEN_EXTI0

+  *         @arg @ref LL_DMAMUX2_REQ_GEN_EXTI2

+  *         @arg @ref LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT

+  *         @arg @ref LL_DMAMUX2_REQ_GEN_SPI6_IT

+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT

+  *         @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT

+  *         @arg @ref LL_DMAMUX2_REQ_GEN_ADC3_IT (*)

+  *         @arg @ref LL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT (*)

+  *         @arg @ref LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT

+  *         @arg @ref LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT

+  * @note   (*) Availability depends on devices.

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID);

+}

+

+/**

+  * @brief  Get DMAMUX external Request Signal ID set on DMAMUX Channel x.

+  * @rmtoll RGxCR        SIG_ID        LL_DMAMUX_GetRequestSignalID

+  * @param  DMAMUXx DMAMUXx Instance

+  * @param  RequestGenChannel This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX_REQ_GEN_0

+  *         @arg @ref LL_DMAMUX_REQ_GEN_1

+  *         @arg @ref LL_DMAMUX_REQ_GEN_2

+  *         @arg @ref LL_DMAMUX_REQ_GEN_3

+  *         @arg @ref LL_DMAMUX_REQ_GEN_4

+  *         @arg @ref LL_DMAMUX_REQ_GEN_5

+  *         @arg @ref LL_DMAMUX_REQ_GEN_6

+  *         @arg @ref LL_DMAMUX_REQ_GEN_7

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT

+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT

+  *         @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT

+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT

+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT

+  *         @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT

+  *         @arg @ref LL_DMAMUX1_SYNC_EXTI0

+  *         @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO

+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT

+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT

+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT

+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT

+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT

+  *         @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT

+  *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP

+  *         @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP

+  *         @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT

+  *         @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT

+  *         @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP

+  *         @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP

+  *         @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT

+  *         @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP

+  *         @arg @ref LL_DMAMUX2_SYNC_EXTI0

+  *         @arg @ref LL_DMAMUX2_SYNC_EXTI2

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management

+  * @{

+  */

+

+/**

+  * @brief  Get Synchronization Event Overrun Flag Channel 0.

+  * @rmtoll CSR          SOF0          LL_DMAMUX_IsActiveFlag_SO0

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Synchronization Event Overrun Flag Channel 1.

+  * @rmtoll CSR          SOF1          LL_DMAMUX_IsActiveFlag_SO1

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Synchronization Event Overrun Flag Channel 2.

+  * @rmtoll CSR          SOF2          LL_DMAMUX_IsActiveFlag_SO2

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Synchronization Event Overrun Flag Channel 3.

+  * @rmtoll CSR          SOF3          LL_DMAMUX_IsActiveFlag_SO3

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Synchronization Event Overrun Flag Channel 4.

+  * @rmtoll CSR          SOF4          LL_DMAMUX_IsActiveFlag_SO4

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Synchronization Event Overrun Flag Channel 5.

+  * @rmtoll CSR          SOF5          LL_DMAMUX_IsActiveFlag_SO5

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Synchronization Event Overrun Flag Channel 6.

+  * @rmtoll CSR          SOF6          LL_DMAMUX_IsActiveFlag_SO6

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Synchronization Event Overrun Flag Channel 7.

+  * @rmtoll CSR          SOF7          LL_DMAMUX_IsActiveFlag_SO7

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Synchronization Event Overrun Flag Channel 8.

+  * @rmtoll CSR          SOF8          LL_DMAMUX_IsActiveFlag_SO8

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Synchronization Event Overrun Flag Channel 9.

+  * @rmtoll CSR          SOF9          LL_DMAMUX_IsActiveFlag_SO9

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Synchronization Event Overrun Flag Channel 10.

+  * @rmtoll CSR          SOF10         LL_DMAMUX_IsActiveFlag_SO10

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Synchronization Event Overrun Flag Channel 11.

+  * @rmtoll CSR          SOF11         LL_DMAMUX_IsActiveFlag_SO11

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Synchronization Event Overrun Flag Channel 12.

+  * @rmtoll CSR          SOF12         LL_DMAMUX_IsActiveFlag_SO12

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Synchronization Event Overrun Flag Channel 13.

+  * @rmtoll CSR          SOF13         LL_DMAMUX_IsActiveFlag_SO13

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Synchronization Event Overrun Flag Channel 14.

+  * @rmtoll CSR          SOF14         LL_DMAMUX_IsActiveFlag_SO14

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF14) == (DMAMUX_CSR_SOF14)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Synchronization Event Overrun Flag Channel 15.

+  * @rmtoll CSR          SOF15         LL_DMAMUX_IsActiveFlag_SO15

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF15) == (DMAMUX_CSR_SOF15)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Request Generator 0 Trigger Event Overrun Flag.

+  * @rmtoll RGSR         OF0           LL_DMAMUX_IsActiveFlag_RGO0

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Request Generator 1 Trigger Event Overrun Flag.

+  * @rmtoll RGSR         OF1           LL_DMAMUX_IsActiveFlag_RGO1

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Request Generator 2 Trigger Event Overrun Flag.

+  * @rmtoll RGSR         OF2           LL_DMAMUX_IsActiveFlag_RGO2

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Request Generator 3 Trigger Event Overrun Flag.

+  * @rmtoll RGSR         OF3           LL_DMAMUX_IsActiveFlag_RGO3

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Request Generator 4 Trigger Event Overrun Flag.

+  * @rmtoll RGSR         OF4           LL_DMAMUX_IsActiveFlag_RGO4

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF4) == (DMAMUX_RGSR_OF4)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Request Generator 5 Trigger Event Overrun Flag.

+  * @rmtoll RGSR         OF5           LL_DMAMUX_IsActiveFlag_RGO5

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF5) == (DMAMUX_RGSR_OF5)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Request Generator 6 Trigger Event Overrun Flag.

+  * @rmtoll RGSR         OF6           LL_DMAMUX_IsActiveFlag_RGO6

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF6) == (DMAMUX_RGSR_OF6)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Request Generator 7 Trigger Event Overrun Flag.

+  * @rmtoll RGSR         OF7           LL_DMAMUX_IsActiveFlag_RGO7

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF7) == (DMAMUX_RGSR_OF7)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear Synchronization Event Overrun Flag Channel 0.

+  * @rmtoll CFR          CSOF0         LL_DMAMUX_ClearFlag_SO0

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF0);

+}

+

+/**

+  * @brief  Clear Synchronization Event Overrun Flag Channel 1.

+  * @rmtoll CFR          CSOF1         LL_DMAMUX_ClearFlag_SO1

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF1);

+}

+

+/**

+  * @brief  Clear Synchronization Event Overrun Flag Channel 2.

+  * @rmtoll CFR          CSOF2         LL_DMAMUX_ClearFlag_SO2

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF2);

+}

+

+/**

+  * @brief  Clear Synchronization Event Overrun Flag Channel 3.

+  * @rmtoll CFR          CSOF3         LL_DMAMUX_ClearFlag_SO3

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF3);

+}

+

+/**

+  * @brief  Clear Synchronization Event Overrun Flag Channel 4.

+  * @rmtoll CFR          CSOF4         LL_DMAMUX_ClearFlag_SO4

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF4);

+}

+

+/**

+  * @brief  Clear Synchronization Event Overrun Flag Channel 5.

+  * @rmtoll CFR          CSOF5         LL_DMAMUX_ClearFlag_SO5

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF5);

+}

+

+/**

+  * @brief  Clear Synchronization Event Overrun Flag Channel 6.

+  * @rmtoll CFR          CSOF6         LL_DMAMUX_ClearFlag_SO6

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF6);

+}

+

+/**

+  * @brief  Clear Synchronization Event Overrun Flag Channel 7.

+  * @rmtoll CFR          CSOF7         LL_DMAMUX_ClearFlag_SO7

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF7);

+}

+

+/**

+  * @brief  Clear Synchronization Event Overrun Flag Channel 8.

+  * @rmtoll CFR          CSOF8         LL_DMAMUX_ClearFlag_SO8

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF8);

+}

+

+/**

+  * @brief  Clear Synchronization Event Overrun Flag Channel 9.

+  * @rmtoll CFR          CSOF9         LL_DMAMUX_ClearFlag_SO9

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF9);

+}

+

+/**

+  * @brief  Clear Synchronization Event Overrun Flag Channel 10.

+  * @rmtoll CFR          CSOF10        LL_DMAMUX_ClearFlag_SO10

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF10);

+}

+

+/**

+  * @brief  Clear Synchronization Event Overrun Flag Channel 11.

+  * @rmtoll CFR          CSOF11        LL_DMAMUX_ClearFlag_SO11

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF11);

+}

+

+/**

+  * @brief  Clear Synchronization Event Overrun Flag Channel 12.

+  * @rmtoll CFR          CSOF12        LL_DMAMUX_ClearFlag_SO12

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF12);

+}

+

+/**

+  * @brief  Clear Synchronization Event Overrun Flag Channel 13.

+  * @rmtoll CFR          CSOF13        LL_DMAMUX_ClearFlag_SO13

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF13);

+}

+

+/**

+  * @brief  Clear Synchronization Event Overrun Flag Channel 14.

+  * @rmtoll CFR          CSOF14        LL_DMAMUX_ClearFlag_SO14

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF14);

+}

+

+/**

+  * @brief  Clear Synchronization Event Overrun Flag Channel 15.

+  * @rmtoll CFR          CSOF15        LL_DMAMUX_ClearFlag_SO15

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF15);

+}

+

+/**

+  * @brief  Clear Request Generator 0 Trigger Event Overrun Flag.

+  * @rmtoll RGCFR        COF0          LL_DMAMUX_ClearFlag_RGO0

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF0);

+}

+

+/**

+  * @brief  Clear Request Generator 1 Trigger Event Overrun Flag.

+  * @rmtoll RGCFR        COF1          LL_DMAMUX_ClearFlag_RGO1

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF1);

+}

+

+/**

+  * @brief  Clear Request Generator 2 Trigger Event Overrun Flag.

+  * @rmtoll RGCFR        COF2          LL_DMAMUX_ClearFlag_RGO2

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF2);

+}

+

+/**

+  * @brief  Clear Request Generator 3 Trigger Event Overrun Flag.

+  * @rmtoll RGCFR        COF3          LL_DMAMUX_ClearFlag_RGO3

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF3);

+}

+

+/**

+  * @brief  Clear Request Generator 4 Trigger Event Overrun Flag.

+  * @rmtoll RGCFR        COF4          LL_DMAMUX_ClearFlag_RGO4

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF4);

+}

+

+/**

+  * @brief  Clear Request Generator 5 Trigger Event Overrun Flag.

+  * @rmtoll RGCFR        COF5          LL_DMAMUX_ClearFlag_RGO5

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF5);

+}

+

+/**

+  * @brief  Clear Request Generator 6 Trigger Event Overrun Flag.

+  * @rmtoll RGCFR        COF6          LL_DMAMUX_ClearFlag_RGO6

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF6);

+}

+

+/**

+  * @brief  Clear Request Generator 7 Trigger Event Overrun Flag.

+  * @rmtoll RGCFR        COF7          LL_DMAMUX_ClearFlag_RGO7

+  * @param  DMAMUXx DMAMUXx DMAMUXx Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF7);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup DMAMUX_LL_EF_IT_Management IT_Management

+  * @{

+  */

+

+/**

+  * @brief  Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.

+  * @rmtoll CxCR         SOIE          LL_DMAMUX_EnableIT_SO

+  * @param  DMAMUXx DMAMUXx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX_CHANNEL_0

+  *         @arg @ref LL_DMAMUX_CHANNEL_1

+  *         @arg @ref LL_DMAMUX_CHANNEL_2

+  *         @arg @ref LL_DMAMUX_CHANNEL_3

+  *         @arg @ref LL_DMAMUX_CHANNEL_4

+  *         @arg @ref LL_DMAMUX_CHANNEL_5

+  *         @arg @ref LL_DMAMUX_CHANNEL_6

+  *         @arg @ref LL_DMAMUX_CHANNEL_7

+  *         @arg @ref LL_DMAMUX_CHANNEL_8

+  *         @arg @ref LL_DMAMUX_CHANNEL_9

+  *         @arg @ref LL_DMAMUX_CHANNEL_10

+  *         @arg @ref LL_DMAMUX_CHANNEL_11

+  *         @arg @ref LL_DMAMUX_CHANNEL_12

+  *         @arg @ref LL_DMAMUX_CHANNEL_13

+  *         @arg @ref LL_DMAMUX_CHANNEL_14

+  *         @arg @ref LL_DMAMUX_CHANNEL_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  SET_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE);

+}

+

+/**

+  * @brief  Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.

+  * @rmtoll CxCR         SOIE          LL_DMAMUX_DisableIT_SO

+  * @param  DMAMUXx DMAMUXx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX_CHANNEL_0

+  *         @arg @ref LL_DMAMUX_CHANNEL_1

+  *         @arg @ref LL_DMAMUX_CHANNEL_2

+  *         @arg @ref LL_DMAMUX_CHANNEL_3

+  *         @arg @ref LL_DMAMUX_CHANNEL_4

+  *         @arg @ref LL_DMAMUX_CHANNEL_5

+  *         @arg @ref LL_DMAMUX_CHANNEL_6

+  *         @arg @ref LL_DMAMUX_CHANNEL_7

+  *         @arg @ref LL_DMAMUX_CHANNEL_8

+  *         @arg @ref LL_DMAMUX_CHANNEL_9

+  *         @arg @ref LL_DMAMUX_CHANNEL_10

+  *         @arg @ref LL_DMAMUX_CHANNEL_11

+  *         @arg @ref LL_DMAMUX_CHANNEL_12

+  *         @arg @ref LL_DMAMUX_CHANNEL_13

+  *         @arg @ref LL_DMAMUX_CHANNEL_14

+  *         @arg @ref LL_DMAMUX_CHANNEL_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  CLEAR_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE);

+}

+

+/**

+  * @brief  Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.

+  * @rmtoll CxCR         SOIE          LL_DMAMUX_IsEnabledIT_SO

+  * @param  DMAMUXx DMAMUXx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX_CHANNEL_0

+  *         @arg @ref LL_DMAMUX_CHANNEL_1

+  *         @arg @ref LL_DMAMUX_CHANNEL_2

+  *         @arg @ref LL_DMAMUX_CHANNEL_3

+  *         @arg @ref LL_DMAMUX_CHANNEL_4

+  *         @arg @ref LL_DMAMUX_CHANNEL_5

+  *         @arg @ref LL_DMAMUX_CHANNEL_6

+  *         @arg @ref LL_DMAMUX_CHANNEL_7

+  *         @arg @ref LL_DMAMUX_CHANNEL_8

+  *         @arg @ref LL_DMAMUX_CHANNEL_9

+  *         @arg @ref LL_DMAMUX_CHANNEL_10

+  *         @arg @ref LL_DMAMUX_CHANNEL_11

+  *         @arg @ref LL_DMAMUX_CHANNEL_12

+  *         @arg @ref LL_DMAMUX_CHANNEL_13

+  *         @arg @ref LL_DMAMUX_CHANNEL_14

+  *         @arg @ref LL_DMAMUX_CHANNEL_15

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return (READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SOIE));

+}

+

+/**

+  * @brief  Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.

+  * @rmtoll RGxCR        OIE           LL_DMAMUX_EnableIT_RGO

+  * @param  DMAMUXx DMAMUXx Instance

+  * @param  RequestGenChannel This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX_REQ_GEN_0

+  *         @arg @ref LL_DMAMUX_REQ_GEN_1

+  *         @arg @ref LL_DMAMUX_REQ_GEN_2

+  *         @arg @ref LL_DMAMUX_REQ_GEN_3

+  *         @arg @ref LL_DMAMUX_REQ_GEN_4

+  *         @arg @ref LL_DMAMUX_REQ_GEN_5

+  *         @arg @ref LL_DMAMUX_REQ_GEN_6

+  *         @arg @ref LL_DMAMUX_REQ_GEN_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE);

+}

+

+/**

+  * @brief  Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.

+  * @rmtoll RGxCR        OIE           LL_DMAMUX_DisableIT_RGO

+  * @param  DMAMUXx DMAMUXx Instance

+  * @param  RequestGenChannel This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX_REQ_GEN_0

+  *         @arg @ref LL_DMAMUX_REQ_GEN_1

+  *         @arg @ref LL_DMAMUX_REQ_GEN_2

+  *         @arg @ref LL_DMAMUX_REQ_GEN_3

+  *         @arg @ref LL_DMAMUX_REQ_GEN_4

+  *         @arg @ref LL_DMAMUX_REQ_GEN_5

+  *         @arg @ref LL_DMAMUX_REQ_GEN_6

+  *         @arg @ref LL_DMAMUX_REQ_GEN_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE);

+}

+

+/**

+  * @brief  Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.

+  * @rmtoll RGxCR        OIE           LL_DMAMUX_IsEnabledIT_RGO

+  * @param  DMAMUXx DMAMUXx Instance

+  * @param  RequestGenChannel This parameter can be one of the following values:

+  *         @arg @ref LL_DMAMUX_REQ_GEN_0

+  *         @arg @ref LL_DMAMUX_REQ_GEN_1

+  *         @arg @ref LL_DMAMUX_REQ_GEN_2

+  *         @arg @ref LL_DMAMUX_REQ_GEN_3

+  *         @arg @ref LL_DMAMUX_REQ_GEN_4

+  *         @arg @ref LL_DMAMUX_REQ_GEN_5

+  *         @arg @ref LL_DMAMUX_REQ_GEN_6

+  *         @arg @ref LL_DMAMUX_REQ_GEN_7

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)

+{

+  register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;

+

+  return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* DMAMUX1 || DMAMUX2 */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* __STM32H7xx_LL_DMAMUX_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_exti.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_exti.h
new file mode 100644
index 0000000000..294f03a6c6
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_exti.h
@@ -0,0 +1,3159 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_exti.h

+  * @author  MCD Application Team

+  * @brief   Header file of EXTI LL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef __STM32H7xx_LL_EXTI_H

+#define __STM32H7xx_LL_EXTI_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+#if defined (EXTI)

+

+/** @defgroup EXTI_LL EXTI

+  * @{

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/* Private Macros ------------------------------------------------------------*/

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros

+  * @{

+  */

+/**

+  * @}

+  */

+#endif /*USE_FULL_LL_DRIVER*/

+/* Exported types ------------------------------------------------------------*/

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure

+  * @{

+  */

+typedef struct

+{

+

+  uint32_t Line_0_31;           /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31

+                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */

+

+  uint32_t Line_32_63;          /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 32 to 63

+                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */

+

+  uint32_t Line_64_95;          /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 64 to 95

+                                     This parameter can be any combination of @ref EXTI_LL_EC_LINE */

+

+  FunctionalState LineCommand;  /*!< Specifies the new state of the selected EXTI lines.

+                                     This parameter can be set either to ENABLE or DISABLE */

+

+  uint8_t Mode;                 /*!< Specifies the mode for the EXTI lines.

+                                     This parameter can be a value of @ref EXTI_LL_EC_MODE. */

+

+  uint8_t Trigger;              /*!< Specifies the trigger signal active edge for the EXTI lines.

+                                     This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */

+} LL_EXTI_InitTypeDef;

+

+/**

+  * @}

+  */

+#endif /*USE_FULL_LL_DRIVER*/

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants

+  * @{

+  */

+

+/** @defgroup EXTI_LL_EC_LINE LINE

+  * @{

+  */

+#define LL_EXTI_LINE_0                 EXTI_IMR1_IM0           /*!< Extended line 0 */

+#define LL_EXTI_LINE_1                 EXTI_IMR1_IM1           /*!< Extended line 1 */

+#define LL_EXTI_LINE_2                 EXTI_IMR1_IM2           /*!< Extended line 2 */

+#define LL_EXTI_LINE_3                 EXTI_IMR1_IM3           /*!< Extended line 3 */

+#define LL_EXTI_LINE_4                 EXTI_IMR1_IM4           /*!< Extended line 4 */

+#define LL_EXTI_LINE_5                 EXTI_IMR1_IM5           /*!< Extended line 5 */

+#define LL_EXTI_LINE_6                 EXTI_IMR1_IM6           /*!< Extended line 6 */

+#define LL_EXTI_LINE_7                 EXTI_IMR1_IM7           /*!< Extended line 7 */

+#define LL_EXTI_LINE_8                 EXTI_IMR1_IM8           /*!< Extended line 8 */

+#define LL_EXTI_LINE_9                 EXTI_IMR1_IM9           /*!< Extended line 9 */

+#define LL_EXTI_LINE_10                EXTI_IMR1_IM10          /*!< Extended line 10 */

+#define LL_EXTI_LINE_11                EXTI_IMR1_IM11          /*!< Extended line 11 */

+#define LL_EXTI_LINE_12                EXTI_IMR1_IM12          /*!< Extended line 12 */

+#define LL_EXTI_LINE_13                EXTI_IMR1_IM13          /*!< Extended line 13 */

+#define LL_EXTI_LINE_14                EXTI_IMR1_IM14          /*!< Extended line 14 */

+#define LL_EXTI_LINE_15                EXTI_IMR1_IM15          /*!< Extended line 15 */

+#define LL_EXTI_LINE_16                EXTI_IMR1_IM16          /*!< Extended line 16 */

+#define LL_EXTI_LINE_17                EXTI_IMR1_IM17          /*!< Extended line 17 */

+#define LL_EXTI_LINE_18                EXTI_IMR1_IM18          /*!< Extended line 18 */

+#define LL_EXTI_LINE_19                EXTI_IMR1_IM19          /*!< Extended line 19 */

+#define LL_EXTI_LINE_20                EXTI_IMR1_IM20          /*!< Extended line 20 */

+#define LL_EXTI_LINE_21                EXTI_IMR1_IM21          /*!< Extended line 21 */

+#define LL_EXTI_LINE_22                EXTI_IMR1_IM22          /*!< Extended line 22 */

+#define LL_EXTI_LINE_23                EXTI_IMR1_IM23          /*!< Extended line 23 */

+#define LL_EXTI_LINE_24                EXTI_IMR1_IM24          /*!< Extended line 24 */

+#define LL_EXTI_LINE_25                EXTI_IMR1_IM25          /*!< Extended line 25 */

+#define LL_EXTI_LINE_26                EXTI_IMR1_IM26          /*!< Extended line 26 */

+#define LL_EXTI_LINE_27                EXTI_IMR1_IM27          /*!< Extended line 27 */

+#define LL_EXTI_LINE_28                EXTI_IMR1_IM28          /*!< Extended line 28 */

+#define LL_EXTI_LINE_29                EXTI_IMR1_IM29          /*!< Extended line 29 */

+#define LL_EXTI_LINE_30                EXTI_IMR1_IM30          /*!< Extended line 30 */

+#define LL_EXTI_LINE_31                EXTI_IMR1_IM31          /*!< Extended line 31 */

+#define LL_EXTI_LINE_ALL_0_31          EXTI_IMR1_IM            /*!< All Extended line not reserved*/

+

+#define LL_EXTI_LINE_32                EXTI_IMR2_IM32          /*!< Extended line 32 */

+#define LL_EXTI_LINE_33                EXTI_IMR2_IM33          /*!< Extended line 33 */

+#define LL_EXTI_LINE_34                EXTI_IMR2_IM34          /*!< Extended line 34 */

+#define LL_EXTI_LINE_35                EXTI_IMR2_IM35          /*!< Extended line 35 */

+#define LL_EXTI_LINE_36                EXTI_IMR2_IM36          /*!< Extended line 36 */

+#define LL_EXTI_LINE_37                EXTI_IMR2_IM37          /*!< Extended line 37 */

+#define LL_EXTI_LINE_38                EXTI_IMR2_IM38          /*!< Extended line 38 */

+#define LL_EXTI_LINE_39                EXTI_IMR2_IM39          /*!< Extended line 39 */

+#define LL_EXTI_LINE_40                EXTI_IMR2_IM40          /*!< Extended line 40 */

+#define LL_EXTI_LINE_41                EXTI_IMR2_IM41          /*!< Extended line 41 */

+#define LL_EXTI_LINE_42                EXTI_IMR2_IM42          /*!< Extended line 42 */

+#define LL_EXTI_LINE_43                EXTI_IMR2_IM43          /*!< Extended line 43 */

+#if defined(USB2_OTG_FS)

+#define LL_EXTI_LINE_44                EXTI_IMR2_IM44          /*!< Extended line 44 */

+#endif /* USB2_OTG_FS */

+#if defined(DSI)

+#define LL_EXTI_LINE_46                EXTI_IMR2_IM46          /*!< Extended line 46 */

+#endif /* DSI */

+#define LL_EXTI_LINE_47                EXTI_IMR2_IM47          /*!< Extended line 47 */

+#define LL_EXTI_LINE_48                EXTI_IMR2_IM48          /*!< Extended line 48 */

+#define LL_EXTI_LINE_49                EXTI_IMR2_IM49          /*!< Extended line 49 */

+#define LL_EXTI_LINE_50                EXTI_IMR2_IM50          /*!< Extended line 50 */

+#define LL_EXTI_LINE_51                EXTI_IMR2_IM51          /*!< Extended line 51 */

+#define LL_EXTI_LINE_52                EXTI_IMR2_IM52          /*!< Extended line 52 */

+#define LL_EXTI_LINE_53                EXTI_IMR2_IM53          /*!< Extended line 53 */

+#define LL_EXTI_LINE_54                EXTI_IMR2_IM54          /*!< Extended line 54 */

+#define LL_EXTI_LINE_55                EXTI_IMR2_IM55          /*!< Extended line 55 */

+#define LL_EXTI_LINE_56                EXTI_IMR2_IM56          /*!< Extended line 56 */

+#define LL_EXTI_LINE_57                EXTI_IMR2_IM57          /*!< Extended line 57 */

+#define LL_EXTI_LINE_58                EXTI_IMR2_IM58          /*!< Extended line 58 */

+#define LL_EXTI_LINE_59                EXTI_IMR2_IM59          /*!< Extended line 59 */

+#define LL_EXTI_LINE_60                EXTI_IMR2_IM60          /*!< Extended line 60 */

+#define LL_EXTI_LINE_61                EXTI_IMR2_IM61          /*!< Extended line 61 */

+#define LL_EXTI_LINE_62                EXTI_IMR2_IM62          /*!< Extended line 62 */

+#define LL_EXTI_LINE_63                EXTI_IMR2_IM63          /*!< Extended line 63 */

+#define LL_EXTI_LINE_ALL_32_63         EXTI_IMR2_IM            /*!< All Extended line not reserved*/

+

+#define LL_EXTI_LINE_64                EXTI_IMR3_IM64          /*!< Extended line 64 */

+#define LL_EXTI_LINE_65                EXTI_IMR3_IM65          /*!< Extended line 65 */

+#define LL_EXTI_LINE_66                EXTI_IMR3_IM66          /*!< Extended line 66 */

+#define LL_EXTI_LINE_67                EXTI_IMR3_IM67          /*!< Extended line 67 */

+#define LL_EXTI_LINE_68                EXTI_IMR3_IM68          /*!< Extended line 68 */

+#define LL_EXTI_LINE_69                EXTI_IMR3_IM69          /*!< Extended line 69 */

+#define LL_EXTI_LINE_70                EXTI_IMR3_IM70          /*!< Extended line 70 */

+#define LL_EXTI_LINE_71                EXTI_IMR3_IM71          /*!< Extended line 71 */

+#define LL_EXTI_LINE_72                EXTI_IMR3_IM72          /*!< Extended line 72 */

+#define LL_EXTI_LINE_73                EXTI_IMR3_IM73          /*!< Extended line 73 */

+#define LL_EXTI_LINE_74                EXTI_IMR3_IM74          /*!< Extended line 74 */

+#if defined(ADC3)

+#define LL_EXTI_LINE_75                EXTI_IMR3_IM75          /*!< Extended line 75 */

+#endif /* ADC3 */

+#if defined(SAI4)

+#define LL_EXTI_LINE_76                EXTI_IMR3_IM76          /*!< Extended line 76 */

+#endif /* SAI4 */

+#if defined(DUAL_CORE)

+#define LL_EXTI_LINE_77                EXTI_IMR3_IM77          /*!< Extended line 77 */

+#define LL_EXTI_LINE_78                EXTI_IMR3_IM78          /*!< Extended line 78 */

+#define LL_EXTI_LINE_79                EXTI_IMR3_IM79          /*!< Extended line 79 */

+#define LL_EXTI_LINE_80                EXTI_IMR3_IM80          /*!< Extended line 80 */

+#define LL_EXTI_LINE_82                EXTI_IMR3_IM82          /*!< Extended line 82 */

+#define LL_EXTI_LINE_84                EXTI_IMR3_IM84          /*!< Extended line 84 */

+#endif /* DUAL_CORE */

+#define LL_EXTI_LINE_85                EXTI_IMR3_IM85          /*!< Extended line 85 */

+#if defined(ETH)

+#define LL_EXTI_LINE_86                EXTI_IMR3_IM86          /*!< Extended line 86 */

+#endif /* ETH */

+#define LL_EXTI_LINE_87                EXTI_IMR3_IM87          /*!< Extended line 87 */

+#if defined(DTS)

+#define LL_EXTI_LINE_88                EXTI_IMR3_IM88          /*!< Extended line 87 */

+#endif /* DTS */

+#define LL_EXTI_LINE_ALL_64_95         EXTI_IMR3_IM            /*!< All Extended line not reserved*/

+

+

+#define LL_EXTI_LINE_ALL               (0xFFFFFFFFU)  /*!< All Extended line */

+

+#if defined(USE_FULL_LL_DRIVER)

+#define LL_EXTI_LINE_NONE              (0x00000000U)  /*!< None Extended line */

+#endif /*USE_FULL_LL_DRIVER*/

+

+/**

+  * @}

+  */

+#if defined(USE_FULL_LL_DRIVER)

+

+/** @defgroup EXTI_LL_EC_MODE Mode

+  * @{

+  */

+#define LL_EXTI_MODE_IT               ((uint8_t)0x01U)      /*!< Cortex-M7 Interrupt Mode  */

+#define LL_EXTI_MODE_EVENT            ((uint8_t)0x02U)      /*!< Cortex-M7 Event Mode */

+#define LL_EXTI_MODE_IT_EVENT         ((uint8_t)0x03U)      /*!< Cortex-M7 Interrupt & Event Mode */

+

+#if defined(DUAL_CORE)

+#define LL_EXTI_MODE_C1_IT            LL_EXTI_MODE_IT       /*!< Cortex-M7 Interrupt Mode */

+#define LL_EXTI_MODE_C1_EVENT         LL_EXTI_MODE_EVENT    /*!< Cortex-M7 Event Mode */

+#define LL_EXTI_MODE_C1_IT_EVENT      LL_EXTI_MODE_IT_EVENT /*!< Cortex-M7 Interrupt & Event Mode */

+

+#define LL_EXTI_MODE_C2_IT            ((uint8_t)0x10U)      /*!< Cortex-M4 Interrupt Mode  */

+#define LL_EXTI_MODE_C2_EVENT         ((uint8_t)0x20U)      /*!< Cortex-M4 Event Mode  */

+#define LL_EXTI_MODE_C2_IT_EVENT      ((uint8_t)0x30U)      /*!< Cortex-M4 Interrupt & Event Mode */

+#endif /* DUAL_CORE */

+

+/**

+  * @}

+  */

+

+/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger

+  * @{

+  */

+#define LL_EXTI_TRIGGER_NONE            ((uint8_t)0x00U) /*!< No Trigger Mode */

+#define LL_EXTI_TRIGGER_RISING          ((uint8_t)0x01U) /*!< Trigger Rising Mode */

+#define LL_EXTI_TRIGGER_FALLING         ((uint8_t)0x02U) /*!< Trigger Falling Mode */

+#define LL_EXTI_TRIGGER_RISING_FALLING  ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */

+

+/**

+  * @}

+  */

+

+/** @defgroup EXTI_LL_D3_PEND_CLR D3 Pend Clear Source

+  * @{

+  */

+#define LL_EXTI_D3_PEND_CLR_DMACH6      ((uint8_t)0x00U) /*!< DMA ch6 event selected as D3 domain pendclear source */

+#define LL_EXTI_D3_PEND_CLR_DMACH7      ((uint8_t)0x01U) /*!< DMA ch7 event selected as D3 domain pendclear source */

+#if defined (LPTIM4)

+#define LL_EXTI_D3_PEND_CLR_LPTIM4      ((uint8_t)0x02U) /*!< LPTIM4 out selected as D3 domain pendclear source */

+#else

+#define LL_EXTI_D3_PEND_CLR_LPTIM2      ((uint8_t)0x02U) /*!< LPTIM2 out selected as D3 domain pendclear source */

+#endif /*LPTIM4*/

+#if defined (LPTIM5)

+#define LL_EXTI_D3_PEND_CLR_LPTIM5      ((uint8_t)0x03U) /*!< LPTIM5 out selected as D3 domain pendclear source */

+#else

+#define LL_EXTI_D3_PEND_CLR_LPTIM3      ((uint8_t)0x02U) /*!< LPTIM3 out selected as D3 domain pendclear source */

+#endif /*LPTIM5*/

+/**

+  * @}

+  */

+

+

+#endif /*USE_FULL_LL_DRIVER*/

+

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros

+  * @{

+  */

+

+/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros

+  * @{

+  */

+

+/**

+  * @brief  Write a value in EXTI register

+  * @param  __REG__ Register to be written

+  * @param  __VALUE__ Value to be written in the register

+  * @retval None

+  */

+#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__))

+

+/**

+  * @brief  Read a value in EXTI register

+  * @param  __REG__ Register to be read

+  * @retval Register value

+  */

+#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__)

+

+/**

+  * @}

+  */

+

+

+/**

+  * @}

+  */

+

+

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions

+ * @{

+ */

+/** @defgroup EXTI_LL_EF_IT_Management IT_Management

+  * @{

+  */

+

+/**

+  * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31

+  * @rmtoll IMR1         IMx           LL_EXTI_EnableIT_0_31

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_0

+  *         @arg @ref LL_EXTI_LINE_1

+  *         @arg @ref LL_EXTI_LINE_2

+  *         @arg @ref LL_EXTI_LINE_3

+  *         @arg @ref LL_EXTI_LINE_4

+  *         @arg @ref LL_EXTI_LINE_5

+  *         @arg @ref LL_EXTI_LINE_6

+  *         @arg @ref LL_EXTI_LINE_7

+  *         @arg @ref LL_EXTI_LINE_8

+  *         @arg @ref LL_EXTI_LINE_9

+  *         @arg @ref LL_EXTI_LINE_10

+  *         @arg @ref LL_EXTI_LINE_11

+  *         @arg @ref LL_EXTI_LINE_12

+  *         @arg @ref LL_EXTI_LINE_13

+  *         @arg @ref LL_EXTI_LINE_14

+  *         @arg @ref LL_EXTI_LINE_15

+  *         @arg @ref LL_EXTI_LINE_16

+  *         @arg @ref LL_EXTI_LINE_17

+  *         @arg @ref LL_EXTI_LINE_18

+  *         @arg @ref LL_EXTI_LINE_19

+  *         @arg @ref LL_EXTI_LINE_20

+  *         @arg @ref LL_EXTI_LINE_21

+  *         @arg @ref LL_EXTI_LINE_22

+  *         @arg @ref LL_EXTI_LINE_23

+  *         @arg @ref LL_EXTI_LINE_24

+  *         @arg @ref LL_EXTI_LINE_25

+  *         @arg @ref LL_EXTI_LINE_26

+  *         @arg @ref LL_EXTI_LINE_27

+  *         @arg @ref LL_EXTI_LINE_28

+  *         @arg @ref LL_EXTI_LINE_29

+  *         @arg @ref LL_EXTI_LINE_30

+  *         @arg @ref LL_EXTI_LINE_31

+  *         @arg @ref LL_EXTI_LINE_ALL_0_31

+  * @retval None

+  */

+__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine)

+{

+  SET_BIT(EXTI->IMR1, ExtiLine);

+}

+

+/**

+  * @brief  Enable ExtiLine Interrupt request for Lines in range 32 to 63

+  * @rmtoll IMR2         IMx           LL_EXTI_EnableIT_32_63

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_32

+  *         @arg @ref LL_EXTI_LINE_33

+  *         @arg @ref LL_EXTI_LINE_34

+  *         @arg @ref LL_EXTI_LINE_35

+  *         @arg @ref LL_EXTI_LINE_36

+  *         @arg @ref LL_EXTI_LINE_37

+  *         @arg @ref LL_EXTI_LINE_38

+  *         @arg @ref LL_EXTI_LINE_39

+  *         @arg @ref LL_EXTI_LINE_40

+  *         @arg @ref LL_EXTI_LINE_41

+  *         @arg @ref LL_EXTI_LINE_42

+  *         @arg @ref LL_EXTI_LINE_43

+  *         @arg @ref LL_EXTI_LINE_44

+  *         @arg @ref LL_EXTI_LINE_46

+  *         @arg @ref LL_EXTI_LINE_47

+  *         @arg @ref LL_EXTI_LINE_48

+  *         @arg @ref LL_EXTI_LINE_49

+  *         @arg @ref LL_EXTI_LINE_50

+  *         @arg @ref LL_EXTI_LINE_51

+  *         @arg @ref LL_EXTI_LINE_52

+  *         @arg @ref LL_EXTI_LINE_53

+  *         @arg @ref LL_EXTI_LINE_54

+  *         @arg @ref LL_EXTI_LINE_55

+  *         @arg @ref LL_EXTI_LINE_56

+  *         @arg @ref LL_EXTI_LINE_57

+  *         @arg @ref LL_EXTI_LINE_58

+  *         @arg @ref LL_EXTI_LINE_59

+  *         @arg @ref LL_EXTI_LINE_60

+  *         @arg @ref LL_EXTI_LINE_61

+  *         @arg @ref LL_EXTI_LINE_62

+  *         @arg @ref LL_EXTI_LINE_63

+  *         @arg @ref LL_EXTI_LINE_ALL_32_63

+  * @retval None

+  */

+__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine)

+{

+  SET_BIT(EXTI->IMR2, ExtiLine);

+}

+

+

+/**

+  * @brief  Enable ExtiLine Interrupt request for Lines in range 64 to 95

+  * @rmtoll IMR3         IMx           LL_EXTI_EnableIT_64_95

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_64

+  *         @arg @ref LL_EXTI_LINE_65

+  *         @arg @ref LL_EXTI_LINE_66

+  *         @arg @ref LL_EXTI_LINE_67

+  *         @arg @ref LL_EXTI_LINE_68

+  *         @arg @ref LL_EXTI_LINE_69

+  *         @arg @ref LL_EXTI_LINE_70

+  *         @arg @ref LL_EXTI_LINE_71

+  *         @arg @ref LL_EXTI_LINE_72

+  *         @arg @ref LL_EXTI_LINE_73

+  *         @arg @ref LL_EXTI_LINE_74

+  *         @arg @ref LL_EXTI_LINE_75

+  *         @arg @ref LL_EXTI_LINE_76

+  *         @arg @ref LL_EXTI_LINE_77

+  *         @arg @ref LL_EXTI_LINE_78

+  *         @arg @ref LL_EXTI_LINE_79

+  *         @arg @ref LL_EXTI_LINE_80

+  *         @arg @ref LL_EXTI_LINE_82

+  *         @arg @ref LL_EXTI_LINE_84

+  *         @arg @ref LL_EXTI_LINE_85

+  *         @arg @ref LL_EXTI_LINE_86

+  *         @arg @ref LL_EXTI_LINE_87

+  *         @arg @ref LL_EXTI_LINE_ALL_64_95

+  * @retval None

+  */

+__STATIC_INLINE void LL_EXTI_EnableIT_64_95(uint32_t ExtiLine)

+{

+  SET_BIT(EXTI->IMR3, ExtiLine);

+}

+

+

+/**

+  * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31

+  * @rmtoll IMR1         IMx           LL_EXTI_DisableIT_0_31

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_0

+  *         @arg @ref LL_EXTI_LINE_1

+  *         @arg @ref LL_EXTI_LINE_2

+  *         @arg @ref LL_EXTI_LINE_3

+  *         @arg @ref LL_EXTI_LINE_4

+  *         @arg @ref LL_EXTI_LINE_5

+  *         @arg @ref LL_EXTI_LINE_6

+  *         @arg @ref LL_EXTI_LINE_7

+  *         @arg @ref LL_EXTI_LINE_8

+  *         @arg @ref LL_EXTI_LINE_9

+  *         @arg @ref LL_EXTI_LINE_10

+  *         @arg @ref LL_EXTI_LINE_11

+  *         @arg @ref LL_EXTI_LINE_12

+  *         @arg @ref LL_EXTI_LINE_13

+  *         @arg @ref LL_EXTI_LINE_14

+  *         @arg @ref LL_EXTI_LINE_15

+  *         @arg @ref LL_EXTI_LINE_16

+  *         @arg @ref LL_EXTI_LINE_17

+  *         @arg @ref LL_EXTI_LINE_18

+  *         @arg @ref LL_EXTI_LINE_19

+  *         @arg @ref LL_EXTI_LINE_20

+  *         @arg @ref LL_EXTI_LINE_21

+  *         @arg @ref LL_EXTI_LINE_22

+  *         @arg @ref LL_EXTI_LINE_23

+  *         @arg @ref LL_EXTI_LINE_24

+  *         @arg @ref LL_EXTI_LINE_25

+  *         @arg @ref LL_EXTI_LINE_26

+  *         @arg @ref LL_EXTI_LINE_27

+  *         @arg @ref LL_EXTI_LINE_28

+  *         @arg @ref LL_EXTI_LINE_29

+  *         @arg @ref LL_EXTI_LINE_30

+  *         @arg @ref LL_EXTI_LINE_31

+  *         @arg @ref LL_EXTI_LINE_ALL_0_31

+  * @retval None

+  */

+__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine)

+{

+  CLEAR_BIT(EXTI->IMR1, ExtiLine);

+}

+

+

+/**

+  * @brief  Disable ExtiLine Interrupt request for Lines in range 32 to 63

+  * @rmtoll IMR2         IMx           LL_EXTI_DisableIT_32_63

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_32

+  *         @arg @ref LL_EXTI_LINE_33

+  *         @arg @ref LL_EXTI_LINE_34

+  *         @arg @ref LL_EXTI_LINE_35

+  *         @arg @ref LL_EXTI_LINE_36

+  *         @arg @ref LL_EXTI_LINE_37

+  *         @arg @ref LL_EXTI_LINE_38

+  *         @arg @ref LL_EXTI_LINE_39

+  *         @arg @ref LL_EXTI_LINE_40

+  *         @arg @ref LL_EXTI_LINE_41

+  *         @arg @ref LL_EXTI_LINE_42

+  *         @arg @ref LL_EXTI_LINE_43

+  *         @arg @ref LL_EXTI_LINE_44

+  *         @arg @ref LL_EXTI_LINE_46

+  *         @arg @ref LL_EXTI_LINE_47

+  *         @arg @ref LL_EXTI_LINE_48

+  *         @arg @ref LL_EXTI_LINE_49

+  *         @arg @ref LL_EXTI_LINE_50

+  *         @arg @ref LL_EXTI_LINE_51

+  *         @arg @ref LL_EXTI_LINE_52

+  *         @arg @ref LL_EXTI_LINE_53

+  *         @arg @ref LL_EXTI_LINE_54

+  *         @arg @ref LL_EXTI_LINE_55

+  *         @arg @ref LL_EXTI_LINE_56

+  *         @arg @ref LL_EXTI_LINE_57

+  *         @arg @ref LL_EXTI_LINE_58

+  *         @arg @ref LL_EXTI_LINE_59

+  *         @arg @ref LL_EXTI_LINE_60

+  *         @arg @ref LL_EXTI_LINE_61

+  *         @arg @ref LL_EXTI_LINE_62

+  *         @arg @ref LL_EXTI_LINE_63

+  *         @arg @ref LL_EXTI_LINE_ALL_32_63

+  * @retval None

+  */

+__STATIC_INLINE void LL_EXTI_DisableIT_32_63(uint32_t ExtiLine)

+{

+  CLEAR_BIT(EXTI->IMR2, ExtiLine);

+}

+

+/**

+  * @brief  Disable ExtiLine Interrupt request for Lines in range 64 to 95

+  * @rmtoll IMR3         IMx           LL_EXTI_DisableIT_64_95

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_64

+  *         @arg @ref LL_EXTI_LINE_65

+  *         @arg @ref LL_EXTI_LINE_66

+  *         @arg @ref LL_EXTI_LINE_67

+  *         @arg @ref LL_EXTI_LINE_68

+  *         @arg @ref LL_EXTI_LINE_69

+  *         @arg @ref LL_EXTI_LINE_70

+  *         @arg @ref LL_EXTI_LINE_71

+  *         @arg @ref LL_EXTI_LINE_72

+  *         @arg @ref LL_EXTI_LINE_73

+  *         @arg @ref LL_EXTI_LINE_74

+  *         @arg @ref LL_EXTI_LINE_75

+  *         @arg @ref LL_EXTI_LINE_76

+  *         @arg @ref LL_EXTI_LINE_77

+  *         @arg @ref LL_EXTI_LINE_78

+  *         @arg @ref LL_EXTI_LINE_79

+  *         @arg @ref LL_EXTI_LINE_80

+  *         @arg @ref LL_EXTI_LINE_82

+  *         @arg @ref LL_EXTI_LINE_84

+  *         @arg @ref LL_EXTI_LINE_85

+  *         @arg @ref LL_EXTI_LINE_86

+  *         @arg @ref LL_EXTI_LINE_87

+  *         @arg @ref LL_EXTI_LINE_ALL_64_95

+  * @retval None

+  */

+__STATIC_INLINE void LL_EXTI_DisableIT_64_95(uint32_t ExtiLine)

+{

+  CLEAR_BIT(EXTI->IMR3, ExtiLine);

+}

+

+

+/**

+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31

+  * @rmtoll IMR1         IMx           LL_EXTI_IsEnabledIT_0_31

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_0

+  *         @arg @ref LL_EXTI_LINE_1

+  *         @arg @ref LL_EXTI_LINE_2

+  *         @arg @ref LL_EXTI_LINE_3

+  *         @arg @ref LL_EXTI_LINE_4

+  *         @arg @ref LL_EXTI_LINE_5

+  *         @arg @ref LL_EXTI_LINE_6

+  *         @arg @ref LL_EXTI_LINE_7

+  *         @arg @ref LL_EXTI_LINE_8

+  *         @arg @ref LL_EXTI_LINE_9

+  *         @arg @ref LL_EXTI_LINE_10

+  *         @arg @ref LL_EXTI_LINE_11

+  *         @arg @ref LL_EXTI_LINE_12

+  *         @arg @ref LL_EXTI_LINE_13

+  *         @arg @ref LL_EXTI_LINE_14

+  *         @arg @ref LL_EXTI_LINE_15

+  *         @arg @ref LL_EXTI_LINE_16

+  *         @arg @ref LL_EXTI_LINE_17

+  *         @arg @ref LL_EXTI_LINE_18

+  *         @arg @ref LL_EXTI_LINE_19

+  *         @arg @ref LL_EXTI_LINE_20

+  *         @arg @ref LL_EXTI_LINE_21

+  *         @arg @ref LL_EXTI_LINE_22

+  *         @arg @ref LL_EXTI_LINE_23

+  *         @arg @ref LL_EXTI_LINE_24

+  *         @arg @ref LL_EXTI_LINE_25

+  *         @arg @ref LL_EXTI_LINE_26

+  *         @arg @ref LL_EXTI_LINE_27

+  *         @arg @ref LL_EXTI_LINE_28

+  *         @arg @ref LL_EXTI_LINE_29

+  *         @arg @ref LL_EXTI_LINE_30

+  *         @arg @ref LL_EXTI_LINE_31

+  *         @arg @ref LL_EXTI_LINE_ALL_0_31

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)

+{

+  return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);

+}

+

+

+/**

+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63

+  * @rmtoll IMR2         IMx           LL_EXTI_IsEnabledIT_32_63

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_32

+  *         @arg @ref LL_EXTI_LINE_33

+  *         @arg @ref LL_EXTI_LINE_34

+  *         @arg @ref LL_EXTI_LINE_35

+  *         @arg @ref LL_EXTI_LINE_36

+  *         @arg @ref LL_EXTI_LINE_37

+  *         @arg @ref LL_EXTI_LINE_38

+  *         @arg @ref LL_EXTI_LINE_39

+  *         @arg @ref LL_EXTI_LINE_40

+  *         @arg @ref LL_EXTI_LINE_41

+  *         @arg @ref LL_EXTI_LINE_42

+  *         @arg @ref LL_EXTI_LINE_43

+  *         @arg @ref LL_EXTI_LINE_44

+  *         @arg @ref LL_EXTI_LINE_46

+  *         @arg @ref LL_EXTI_LINE_47

+  *         @arg @ref LL_EXTI_LINE_48

+  *         @arg @ref LL_EXTI_LINE_49

+  *         @arg @ref LL_EXTI_LINE_50

+  *         @arg @ref LL_EXTI_LINE_51

+  *         @arg @ref LL_EXTI_LINE_52

+  *         @arg @ref LL_EXTI_LINE_53

+  *         @arg @ref LL_EXTI_LINE_54

+  *         @arg @ref LL_EXTI_LINE_55

+  *         @arg @ref LL_EXTI_LINE_56

+  *         @arg @ref LL_EXTI_LINE_57

+  *         @arg @ref LL_EXTI_LINE_58

+  *         @arg @ref LL_EXTI_LINE_59

+  *         @arg @ref LL_EXTI_LINE_60

+  *         @arg @ref LL_EXTI_LINE_61

+  *         @arg @ref LL_EXTI_LINE_62

+  *         @arg @ref LL_EXTI_LINE_63

+  *         @arg @ref LL_EXTI_LINE_ALL_32_63

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)

+{

+  return ((READ_BIT(EXTI->IMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);

+}

+

+

+/**

+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 64 to 95

+  * @rmtoll IMR3         IMx           LL_EXTI_IsEnabledIT_64_95

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_64

+  *         @arg @ref LL_EXTI_LINE_65

+  *         @arg @ref LL_EXTI_LINE_66

+  *         @arg @ref LL_EXTI_LINE_67

+  *         @arg @ref LL_EXTI_LINE_68

+  *         @arg @ref LL_EXTI_LINE_69

+  *         @arg @ref LL_EXTI_LINE_70

+  *         @arg @ref LL_EXTI_LINE_71

+  *         @arg @ref LL_EXTI_LINE_72

+  *         @arg @ref LL_EXTI_LINE_73

+  *         @arg @ref LL_EXTI_LINE_74

+  *         @arg @ref LL_EXTI_LINE_75

+  *         @arg @ref LL_EXTI_LINE_76

+  *         @arg @ref LL_EXTI_LINE_77

+  *         @arg @ref LL_EXTI_LINE_78

+  *         @arg @ref LL_EXTI_LINE_79

+  *         @arg @ref LL_EXTI_LINE_80

+  *         @arg @ref LL_EXTI_LINE_82

+  *         @arg @ref LL_EXTI_LINE_84

+  *         @arg @ref LL_EXTI_LINE_85

+  *         @arg @ref LL_EXTI_LINE_86

+  *         @arg @ref LL_EXTI_LINE_87

+  *         @arg @ref LL_EXTI_LINE_ALL_64_95

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_64_95(uint32_t ExtiLine)

+{

+  return ((READ_BIT(EXTI->IMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);

+}

+

+#if defined(DUAL_CORE)

+/**

+  * @brief  Enable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2

+  * @rmtoll C2IMR1         IMx           LL_C2_EXTI_EnableIT_0_31

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_0

+  *         @arg @ref LL_EXTI_LINE_1

+  *         @arg @ref LL_EXTI_LINE_2

+  *         @arg @ref LL_EXTI_LINE_3

+  *         @arg @ref LL_EXTI_LINE_4

+  *         @arg @ref LL_EXTI_LINE_5

+  *         @arg @ref LL_EXTI_LINE_6

+  *         @arg @ref LL_EXTI_LINE_7

+  *         @arg @ref LL_EXTI_LINE_8

+  *         @arg @ref LL_EXTI_LINE_9

+  *         @arg @ref LL_EXTI_LINE_10

+  *         @arg @ref LL_EXTI_LINE_11

+  *         @arg @ref LL_EXTI_LINE_12

+  *         @arg @ref LL_EXTI_LINE_13

+  *         @arg @ref LL_EXTI_LINE_14

+  *         @arg @ref LL_EXTI_LINE_15

+  *         @arg @ref LL_EXTI_LINE_16

+  *         @arg @ref LL_EXTI_LINE_17

+  *         @arg @ref LL_EXTI_LINE_18

+  *         @arg @ref LL_EXTI_LINE_19

+  *         @arg @ref LL_EXTI_LINE_20

+  *         @arg @ref LL_EXTI_LINE_21

+  *         @arg @ref LL_EXTI_LINE_22

+  *         @arg @ref LL_EXTI_LINE_23

+  *         @arg @ref LL_EXTI_LINE_24

+  *         @arg @ref LL_EXTI_LINE_25

+  *         @arg @ref LL_EXTI_LINE_26

+  *         @arg @ref LL_EXTI_LINE_27

+  *         @arg @ref LL_EXTI_LINE_28

+  *         @arg @ref LL_EXTI_LINE_29

+  *         @arg @ref LL_EXTI_LINE_30

+  *         @arg @ref LL_EXTI_LINE_31

+  *         @arg @ref LL_EXTI_LINE_ALL_0_31

+  * @retval None

+  */

+__STATIC_INLINE void LL_C2_EXTI_EnableIT_0_31(uint32_t ExtiLine)

+{

+  SET_BIT(EXTI->C2IMR1, ExtiLine);

+}

+

+

+/**

+  * @brief  Enable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2

+  * @rmtoll C2IMR2         IMx           LL_C2_EXTI_EnableIT_32_63

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_32

+  *         @arg @ref LL_EXTI_LINE_33

+  *         @arg @ref LL_EXTI_LINE_34

+  *         @arg @ref LL_EXTI_LINE_35

+  *         @arg @ref LL_EXTI_LINE_36

+  *         @arg @ref LL_EXTI_LINE_37

+  *         @arg @ref LL_EXTI_LINE_38

+  *         @arg @ref LL_EXTI_LINE_39

+  *         @arg @ref LL_EXTI_LINE_40

+  *         @arg @ref LL_EXTI_LINE_41

+  *         @arg @ref LL_EXTI_LINE_42

+  *         @arg @ref LL_EXTI_LINE_43

+  *         @arg @ref LL_EXTI_LINE_44

+  *         @arg @ref LL_EXTI_LINE_46

+  *         @arg @ref LL_EXTI_LINE_47

+  *         @arg @ref LL_EXTI_LINE_48

+  *         @arg @ref LL_EXTI_LINE_49

+  *         @arg @ref LL_EXTI_LINE_50

+  *         @arg @ref LL_EXTI_LINE_51

+  *         @arg @ref LL_EXTI_LINE_52

+  *         @arg @ref LL_EXTI_LINE_53

+  *         @arg @ref LL_EXTI_LINE_54

+  *         @arg @ref LL_EXTI_LINE_55

+  *         @arg @ref LL_EXTI_LINE_56

+  *         @arg @ref LL_EXTI_LINE_57

+  *         @arg @ref LL_EXTI_LINE_58

+  *         @arg @ref LL_EXTI_LINE_59

+  *         @arg @ref LL_EXTI_LINE_60

+  *         @arg @ref LL_EXTI_LINE_61

+  *         @arg @ref LL_EXTI_LINE_62

+  *         @arg @ref LL_EXTI_LINE_63

+  *         @arg @ref LL_EXTI_LINE_ALL_32_63

+  * @retval None

+  */

+__STATIC_INLINE void LL_C2_EXTI_EnableIT_32_63(uint32_t ExtiLine)

+{

+  SET_BIT(EXTI->C2IMR2, ExtiLine);

+}

+

+

+/**

+  * @brief  Enable ExtiLine Interrupt request for Lines in range 64 to 95

+  * @rmtoll C2IMR3         IMx           LL_C2_EXTI_EnableIT_64_95

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_64

+  *         @arg @ref LL_EXTI_LINE_65

+  *         @arg @ref LL_EXTI_LINE_66

+  *         @arg @ref LL_EXTI_LINE_67

+  *         @arg @ref LL_EXTI_LINE_68

+  *         @arg @ref LL_EXTI_LINE_69

+  *         @arg @ref LL_EXTI_LINE_70

+  *         @arg @ref LL_EXTI_LINE_71

+  *         @arg @ref LL_EXTI_LINE_72

+  *         @arg @ref LL_EXTI_LINE_73

+  *         @arg @ref LL_EXTI_LINE_74

+  *         @arg @ref LL_EXTI_LINE_75

+  *         @arg @ref LL_EXTI_LINE_76

+  *         @arg @ref LL_EXTI_LINE_77

+  *         @arg @ref LL_EXTI_LINE_78

+  *         @arg @ref LL_EXTI_LINE_79

+  *         @arg @ref LL_EXTI_LINE_80

+  *         @arg @ref LL_EXTI_LINE_82

+  *         @arg @ref LL_EXTI_LINE_84

+  *         @arg @ref LL_EXTI_LINE_85

+  *         @arg @ref LL_EXTI_LINE_86

+  *         @arg @ref LL_EXTI_LINE_87

+  *         @arg @ref LL_EXTI_LINE_ALL_64_95

+  * @retval None

+  */

+__STATIC_INLINE void LL_C2_EXTI_EnableIT_64_95(uint32_t ExtiLine)

+{

+  SET_BIT(EXTI->C2IMR3, ExtiLine);

+}

+

+

+/**

+  * @brief  Disable ExtiLine Interrupt request for Lines in range 0 to 31 for cpu2

+  * @rmtoll C2IMR1         IMx           LL_C2_EXTI_DisableIT_0_31

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_0

+  *         @arg @ref LL_EXTI_LINE_1

+  *         @arg @ref LL_EXTI_LINE_2

+  *         @arg @ref LL_EXTI_LINE_3

+  *         @arg @ref LL_EXTI_LINE_4

+  *         @arg @ref LL_EXTI_LINE_5

+  *         @arg @ref LL_EXTI_LINE_6

+  *         @arg @ref LL_EXTI_LINE_7

+  *         @arg @ref LL_EXTI_LINE_8

+  *         @arg @ref LL_EXTI_LINE_9

+  *         @arg @ref LL_EXTI_LINE_10

+  *         @arg @ref LL_EXTI_LINE_11

+  *         @arg @ref LL_EXTI_LINE_12

+  *         @arg @ref LL_EXTI_LINE_13

+  *         @arg @ref LL_EXTI_LINE_14

+  *         @arg @ref LL_EXTI_LINE_15

+  *         @arg @ref LL_EXTI_LINE_16

+  *         @arg @ref LL_EXTI_LINE_17

+  *         @arg @ref LL_EXTI_LINE_18

+  *         @arg @ref LL_EXTI_LINE_19

+  *         @arg @ref LL_EXTI_LINE_20

+  *         @arg @ref LL_EXTI_LINE_21

+  *         @arg @ref LL_EXTI_LINE_22

+  *         @arg @ref LL_EXTI_LINE_23

+  *         @arg @ref LL_EXTI_LINE_24

+  *         @arg @ref LL_EXTI_LINE_25

+  *         @arg @ref LL_EXTI_LINE_26

+  *         @arg @ref LL_EXTI_LINE_27

+  *         @arg @ref LL_EXTI_LINE_28

+  *         @arg @ref LL_EXTI_LINE_29

+  *         @arg @ref LL_EXTI_LINE_30

+  *         @arg @ref LL_EXTI_LINE_31

+  *         @arg @ref LL_EXTI_LINE_ALL_0_31

+  * @retval None

+  */

+__STATIC_INLINE void LL_C2_EXTI_DisableIT_0_31(uint32_t ExtiLine)

+{

+  CLEAR_BIT(EXTI->C2IMR1, ExtiLine);

+}

+

+

+

+/**

+  * @brief  Disable ExtiLine Interrupt request for Lines in range 32 to 63 for cpu2

+  * @rmtoll C2IMR2         IMx           LL_C2_EXTI_DisableIT_32_63

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_32

+  *         @arg @ref LL_EXTI_LINE_33

+  *         @arg @ref LL_EXTI_LINE_34

+  *         @arg @ref LL_EXTI_LINE_35

+  *         @arg @ref LL_EXTI_LINE_36

+  *         @arg @ref LL_EXTI_LINE_37

+  *         @arg @ref LL_EXTI_LINE_38

+  *         @arg @ref LL_EXTI_LINE_39

+  *         @arg @ref LL_EXTI_LINE_40

+  *         @arg @ref LL_EXTI_LINE_41

+  *         @arg @ref LL_EXTI_LINE_42

+  *         @arg @ref LL_EXTI_LINE_43

+  *         @arg @ref LL_EXTI_LINE_44

+  *         @arg @ref LL_EXTI_LINE_46

+  *         @arg @ref LL_EXTI_LINE_47

+  *         @arg @ref LL_EXTI_LINE_48

+  *         @arg @ref LL_EXTI_LINE_49

+  *         @arg @ref LL_EXTI_LINE_50

+  *         @arg @ref LL_EXTI_LINE_51

+  *         @arg @ref LL_EXTI_LINE_52

+  *         @arg @ref LL_EXTI_LINE_53

+  *         @arg @ref LL_EXTI_LINE_54

+  *         @arg @ref LL_EXTI_LINE_55

+  *         @arg @ref LL_EXTI_LINE_56

+  *         @arg @ref LL_EXTI_LINE_57

+  *         @arg @ref LL_EXTI_LINE_58

+  *         @arg @ref LL_EXTI_LINE_59

+  *         @arg @ref LL_EXTI_LINE_60

+  *         @arg @ref LL_EXTI_LINE_61

+  *         @arg @ref LL_EXTI_LINE_62

+  *         @arg @ref LL_EXTI_LINE_63

+  *         @arg @ref LL_EXTI_LINE_ALL_32_63

+  * @retval None

+  */

+__STATIC_INLINE void LL_C2_EXTI_DisableIT_32_63(uint32_t ExtiLine)

+{

+  CLEAR_BIT(EXTI->C2IMR2, ExtiLine);

+}

+

+

+/**

+  * @brief  Disable ExtiLine Interrupt request for Lines in range 64 to 95 for cpu2

+  * @rmtoll C2IMR3         IMx           LL_C2_EXTI_DisableIT_64_95

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_64

+  *         @arg @ref LL_EXTI_LINE_65

+  *         @arg @ref LL_EXTI_LINE_66

+  *         @arg @ref LL_EXTI_LINE_67

+  *         @arg @ref LL_EXTI_LINE_68

+  *         @arg @ref LL_EXTI_LINE_69

+  *         @arg @ref LL_EXTI_LINE_70

+  *         @arg @ref LL_EXTI_LINE_71

+  *         @arg @ref LL_EXTI_LINE_72

+  *         @arg @ref LL_EXTI_LINE_73

+  *         @arg @ref LL_EXTI_LINE_74

+  *         @arg @ref LL_EXTI_LINE_75

+  *         @arg @ref LL_EXTI_LINE_76

+  *         @arg @ref LL_EXTI_LINE_77

+  *         @arg @ref LL_EXTI_LINE_78

+  *         @arg @ref LL_EXTI_LINE_79

+  *         @arg @ref LL_EXTI_LINE_80

+  *         @arg @ref LL_EXTI_LINE_82

+  *         @arg @ref LL_EXTI_LINE_84

+  *         @arg @ref LL_EXTI_LINE_85

+  *         @arg @ref LL_EXTI_LINE_86

+  *         @arg @ref LL_EXTI_LINE_87

+  *         @arg @ref LL_EXTI_LINE_ALL_64_95

+  * @retval None

+  */

+__STATIC_INLINE void LL_C2_EXTI_DisableIT_64_95(uint32_t ExtiLine)

+{

+  CLEAR_BIT(EXTI->C2IMR3, ExtiLine);

+}

+

+

+/**

+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 for cpu2

+  * @rmtoll C2IMR1         IMx           LL_C2_EXTI_IsEnabledIT_0_31

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_0

+  *         @arg @ref LL_EXTI_LINE_1

+  *         @arg @ref LL_EXTI_LINE_2

+  *         @arg @ref LL_EXTI_LINE_3

+  *         @arg @ref LL_EXTI_LINE_4

+  *         @arg @ref LL_EXTI_LINE_5

+  *         @arg @ref LL_EXTI_LINE_6

+  *         @arg @ref LL_EXTI_LINE_7

+  *         @arg @ref LL_EXTI_LINE_8

+  *         @arg @ref LL_EXTI_LINE_9

+  *         @arg @ref LL_EXTI_LINE_10

+  *         @arg @ref LL_EXTI_LINE_11

+  *         @arg @ref LL_EXTI_LINE_12

+  *         @arg @ref LL_EXTI_LINE_13

+  *         @arg @ref LL_EXTI_LINE_14

+  *         @arg @ref LL_EXTI_LINE_15

+  *         @arg @ref LL_EXTI_LINE_16

+  *         @arg @ref LL_EXTI_LINE_17

+  *         @arg @ref LL_EXTI_LINE_18

+  *         @arg @ref LL_EXTI_LINE_19

+  *         @arg @ref LL_EXTI_LINE_20

+  *         @arg @ref LL_EXTI_LINE_21

+  *         @arg @ref LL_EXTI_LINE_22

+  *         @arg @ref LL_EXTI_LINE_23

+  *         @arg @ref LL_EXTI_LINE_24

+  *         @arg @ref LL_EXTI_LINE_25

+  *         @arg @ref LL_EXTI_LINE_26

+  *         @arg @ref LL_EXTI_LINE_27

+  *         @arg @ref LL_EXTI_LINE_28

+  *         @arg @ref LL_EXTI_LINE_29

+  *         @arg @ref LL_EXTI_LINE_30

+  *         @arg @ref LL_EXTI_LINE_31

+  *         @arg @ref LL_EXTI_LINE_ALL_0_31

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine)

+{

+  return ((READ_BIT(EXTI->C2IMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);

+}

+

+

+/**

+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 32 to 63 for cpu2

+  * @rmtoll C2IMR2         IMx           LL_C2_EXTI_IsEnabledIT_32_63

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_32

+  *         @arg @ref LL_EXTI_LINE_33

+  *         @arg @ref LL_EXTI_LINE_34

+  *         @arg @ref LL_EXTI_LINE_35

+  *         @arg @ref LL_EXTI_LINE_36

+  *         @arg @ref LL_EXTI_LINE_37

+  *         @arg @ref LL_EXTI_LINE_38

+  *         @arg @ref LL_EXTI_LINE_39

+  *         @arg @ref LL_EXTI_LINE_40

+  *         @arg @ref LL_EXTI_LINE_41

+  *         @arg @ref LL_EXTI_LINE_42

+  *         @arg @ref LL_EXTI_LINE_43

+  *         @arg @ref LL_EXTI_LINE_44

+  *         @arg @ref LL_EXTI_LINE_46

+  *         @arg @ref LL_EXTI_LINE_47

+  *         @arg @ref LL_EXTI_LINE_48

+  *         @arg @ref LL_EXTI_LINE_49

+  *         @arg @ref LL_EXTI_LINE_50

+  *         @arg @ref LL_EXTI_LINE_51

+  *         @arg @ref LL_EXTI_LINE_52

+  *         @arg @ref LL_EXTI_LINE_53

+  *         @arg @ref LL_EXTI_LINE_54

+  *         @arg @ref LL_EXTI_LINE_55

+  *         @arg @ref LL_EXTI_LINE_56

+  *         @arg @ref LL_EXTI_LINE_57

+  *         @arg @ref LL_EXTI_LINE_58

+  *         @arg @ref LL_EXTI_LINE_59

+  *         @arg @ref LL_EXTI_LINE_60

+  *         @arg @ref LL_EXTI_LINE_61

+  *         @arg @ref LL_EXTI_LINE_62

+  *         @arg @ref LL_EXTI_LINE_63

+  *         @arg @ref LL_EXTI_LINE_ALL_32_63

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_32_63(uint32_t ExtiLine)

+{

+  return ((READ_BIT(EXTI->C2IMR2, ExtiLine) == (ExtiLine))? 1U : 0U);

+}

+

+

+/**

+  * @brief  Indicate if ExtiLine Interrupt request is enabled for Lines in range 64 to 95

+  * @rmtoll C2IMR3         IMx           LL_C2_EXTI_IsEnabledIT_64_95

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_64

+  *         @arg @ref LL_EXTI_LINE_65

+  *         @arg @ref LL_EXTI_LINE_66

+  *         @arg @ref LL_EXTI_LINE_67

+  *         @arg @ref LL_EXTI_LINE_68

+  *         @arg @ref LL_EXTI_LINE_69

+  *         @arg @ref LL_EXTI_LINE_70

+  *         @arg @ref LL_EXTI_LINE_71

+  *         @arg @ref LL_EXTI_LINE_72

+  *         @arg @ref LL_EXTI_LINE_73

+  *         @arg @ref LL_EXTI_LINE_74

+  *         @arg @ref LL_EXTI_LINE_75

+  *         @arg @ref LL_EXTI_LINE_76

+  *         @arg @ref LL_EXTI_LINE_77

+  *         @arg @ref LL_EXTI_LINE_78

+  *         @arg @ref LL_EXTI_LINE_79

+  *         @arg @ref LL_EXTI_LINE_80

+  *         @arg @ref LL_EXTI_LINE_82

+  *         @arg @ref LL_EXTI_LINE_84

+  *         @arg @ref LL_EXTI_LINE_85

+  *         @arg @ref LL_EXTI_LINE_86

+  *         @arg @ref LL_EXTI_LINE_87

+  *         @arg @ref LL_EXTI_LINE_ALL_64_95

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledIT_64_95(uint32_t ExtiLine)

+{

+  return ((READ_BIT(EXTI->C2IMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);

+}

+

+#endif /* DUAL_CORE */

+

+

+/**

+  * @}

+  */

+

+/** @defgroup EXTI_LL_EF_Event_Management Event_Management

+  * @{

+  */

+

+/**

+  * @brief  Enable ExtiLine Event request for Lines in range 0 to 31

+  * @rmtoll EMR1         EMx           LL_EXTI_EnableEvent_0_31

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_0

+  *         @arg @ref LL_EXTI_LINE_1

+  *         @arg @ref LL_EXTI_LINE_2

+  *         @arg @ref LL_EXTI_LINE_3

+  *         @arg @ref LL_EXTI_LINE_4

+  *         @arg @ref LL_EXTI_LINE_5

+  *         @arg @ref LL_EXTI_LINE_6

+  *         @arg @ref LL_EXTI_LINE_7

+  *         @arg @ref LL_EXTI_LINE_8

+  *         @arg @ref LL_EXTI_LINE_9

+  *         @arg @ref LL_EXTI_LINE_10

+  *         @arg @ref LL_EXTI_LINE_11

+  *         @arg @ref LL_EXTI_LINE_12

+  *         @arg @ref LL_EXTI_LINE_13

+  *         @arg @ref LL_EXTI_LINE_14

+  *         @arg @ref LL_EXTI_LINE_15

+  *         @arg @ref LL_EXTI_LINE_16

+  *         @arg @ref LL_EXTI_LINE_17

+  *         @arg @ref LL_EXTI_LINE_18

+  *         @arg @ref LL_EXTI_LINE_19

+  *         @arg @ref LL_EXTI_LINE_20

+  *         @arg @ref LL_EXTI_LINE_21

+  *         @arg @ref LL_EXTI_LINE_22

+  *         @arg @ref LL_EXTI_LINE_23

+  *         @arg @ref LL_EXTI_LINE_24

+  *         @arg @ref LL_EXTI_LINE_25

+  *         @arg @ref LL_EXTI_LINE_26

+  *         @arg @ref LL_EXTI_LINE_27

+  *         @arg @ref LL_EXTI_LINE_28

+  *         @arg @ref LL_EXTI_LINE_29

+  *         @arg @ref LL_EXTI_LINE_30

+  *         @arg @ref LL_EXTI_LINE_31

+  *         @arg @ref LL_EXTI_LINE_ALL_0_31

+  * @retval None

+  */

+__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine)

+{

+  SET_BIT(EXTI->EMR1, ExtiLine);

+}

+

+/**

+  * @brief  Enable ExtiLine Event request for Lines in range 32 to 63

+  * @rmtoll EMR2         EMx           LL_EXTI_EnableEvent_32_63

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_32

+  *         @arg @ref LL_EXTI_LINE_33

+  *         @arg @ref LL_EXTI_LINE_34

+  *         @arg @ref LL_EXTI_LINE_35

+  *         @arg @ref LL_EXTI_LINE_36

+  *         @arg @ref LL_EXTI_LINE_37

+  *         @arg @ref LL_EXTI_LINE_38

+  *         @arg @ref LL_EXTI_LINE_39

+  *         @arg @ref LL_EXTI_LINE_40

+  *         @arg @ref LL_EXTI_LINE_41

+  *         @arg @ref LL_EXTI_LINE_42

+  *         @arg @ref LL_EXTI_LINE_43

+  *         @arg @ref LL_EXTI_LINE_44

+  *         @arg @ref LL_EXTI_LINE_46

+  *         @arg @ref LL_EXTI_LINE_47

+  *         @arg @ref LL_EXTI_LINE_48

+  *         @arg @ref LL_EXTI_LINE_49

+  *         @arg @ref LL_EXTI_LINE_50

+  *         @arg @ref LL_EXTI_LINE_51

+  *         @arg @ref LL_EXTI_LINE_52

+  *         @arg @ref LL_EXTI_LINE_53

+  *         @arg @ref LL_EXTI_LINE_54

+  *         @arg @ref LL_EXTI_LINE_55

+  *         @arg @ref LL_EXTI_LINE_56

+  *         @arg @ref LL_EXTI_LINE_57

+  *         @arg @ref LL_EXTI_LINE_58

+  *         @arg @ref LL_EXTI_LINE_59

+  *         @arg @ref LL_EXTI_LINE_60

+  *         @arg @ref LL_EXTI_LINE_61

+  *         @arg @ref LL_EXTI_LINE_62

+  *         @arg @ref LL_EXTI_LINE_63

+  *         @arg @ref LL_EXTI_LINE_ALL_32_63

+  * @retval None

+  */

+__STATIC_INLINE void LL_EXTI_EnableEvent_32_63(uint32_t ExtiLine)

+{

+  SET_BIT(EXTI->EMR2, ExtiLine);

+}

+

+/**

+  * @brief  Enable ExtiLine Event request for Lines in range 64 to 95

+  * @rmtoll EMR3         EMx           LL_EXTI_EnableEvent_64_95

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_64

+  *         @arg @ref LL_EXTI_LINE_65

+  *         @arg @ref LL_EXTI_LINE_66

+  *         @arg @ref LL_EXTI_LINE_67

+  *         @arg @ref LL_EXTI_LINE_68

+  *         @arg @ref LL_EXTI_LINE_69

+  *         @arg @ref LL_EXTI_LINE_70

+  *         @arg @ref LL_EXTI_LINE_71

+  *         @arg @ref LL_EXTI_LINE_72

+  *         @arg @ref LL_EXTI_LINE_73

+  *         @arg @ref LL_EXTI_LINE_74

+  *         @arg @ref LL_EXTI_LINE_75

+  *         @arg @ref LL_EXTI_LINE_76

+  *         @arg @ref LL_EXTI_LINE_77

+  *         @arg @ref LL_EXTI_LINE_78

+  *         @arg @ref LL_EXTI_LINE_79

+  *         @arg @ref LL_EXTI_LINE_80

+  *         @arg @ref LL_EXTI_LINE_82

+  *         @arg @ref LL_EXTI_LINE_84

+  *         @arg @ref LL_EXTI_LINE_85

+  *         @arg @ref LL_EXTI_LINE_86

+  *         @arg @ref LL_EXTI_LINE_87

+  *         @arg @ref LL_EXTI_LINE_ALL_64_95

+  * @retval None

+  */

+__STATIC_INLINE void LL_EXTI_EnableEvent_64_95(uint32_t ExtiLine)

+{

+  SET_BIT(EXTI->EMR3, ExtiLine);

+}

+

+/**

+  * @brief  Disable ExtiLine Event request for Lines in range 0 to 31

+  * @rmtoll EMR1         EMx           LL_EXTI_DisableEvent_0_31

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_0

+  *         @arg @ref LL_EXTI_LINE_1

+  *         @arg @ref LL_EXTI_LINE_2

+  *         @arg @ref LL_EXTI_LINE_3

+  *         @arg @ref LL_EXTI_LINE_4

+  *         @arg @ref LL_EXTI_LINE_5

+  *         @arg @ref LL_EXTI_LINE_6

+  *         @arg @ref LL_EXTI_LINE_7

+  *         @arg @ref LL_EXTI_LINE_8

+  *         @arg @ref LL_EXTI_LINE_9

+  *         @arg @ref LL_EXTI_LINE_10

+  *         @arg @ref LL_EXTI_LINE_11

+  *         @arg @ref LL_EXTI_LINE_12

+  *         @arg @ref LL_EXTI_LINE_13

+  *         @arg @ref LL_EXTI_LINE_14

+  *         @arg @ref LL_EXTI_LINE_15

+  *         @arg @ref LL_EXTI_LINE_16

+  *         @arg @ref LL_EXTI_LINE_17

+  *         @arg @ref LL_EXTI_LINE_18

+  *         @arg @ref LL_EXTI_LINE_19

+  *         @arg @ref LL_EXTI_LINE_20

+  *         @arg @ref LL_EXTI_LINE_21

+  *         @arg @ref LL_EXTI_LINE_22

+  *         @arg @ref LL_EXTI_LINE_23

+  *         @arg @ref LL_EXTI_LINE_24

+  *         @arg @ref LL_EXTI_LINE_25

+  *         @arg @ref LL_EXTI_LINE_26

+  *         @arg @ref LL_EXTI_LINE_27

+  *         @arg @ref LL_EXTI_LINE_28

+  *         @arg @ref LL_EXTI_LINE_29

+  *         @arg @ref LL_EXTI_LINE_30

+  *         @arg @ref LL_EXTI_LINE_31

+  *         @arg @ref LL_EXTI_LINE_ALL_0_31

+  * @retval None

+  */

+__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine)

+{

+  CLEAR_BIT(EXTI->EMR1, ExtiLine);

+}

+

+/**

+  * @brief  Disable ExtiLine Event request for Lines in range 32 to 63

+  * @rmtoll EMR2         EMx           LL_EXTI_DisableEvent_32_63

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_32

+  *         @arg @ref LL_EXTI_LINE_33

+  *         @arg @ref LL_EXTI_LINE_34

+  *         @arg @ref LL_EXTI_LINE_35

+  *         @arg @ref LL_EXTI_LINE_36

+  *         @arg @ref LL_EXTI_LINE_37

+  *         @arg @ref LL_EXTI_LINE_38

+  *         @arg @ref LL_EXTI_LINE_39

+  *         @arg @ref LL_EXTI_LINE_40

+  *         @arg @ref LL_EXTI_LINE_41

+  *         @arg @ref LL_EXTI_LINE_42

+  *         @arg @ref LL_EXTI_LINE_43

+  *         @arg @ref LL_EXTI_LINE_44

+  *         @arg @ref LL_EXTI_LINE_46

+  *         @arg @ref LL_EXTI_LINE_47

+  *         @arg @ref LL_EXTI_LINE_48

+  *         @arg @ref LL_EXTI_LINE_49

+  *         @arg @ref LL_EXTI_LINE_50

+  *         @arg @ref LL_EXTI_LINE_51

+  *         @arg @ref LL_EXTI_LINE_52

+  *         @arg @ref LL_EXTI_LINE_53

+  *         @arg @ref LL_EXTI_LINE_54

+  *         @arg @ref LL_EXTI_LINE_55

+  *         @arg @ref LL_EXTI_LINE_56

+  *         @arg @ref LL_EXTI_LINE_57

+  *         @arg @ref LL_EXTI_LINE_58

+  *         @arg @ref LL_EXTI_LINE_59

+  *         @arg @ref LL_EXTI_LINE_60

+  *         @arg @ref LL_EXTI_LINE_61

+  *         @arg @ref LL_EXTI_LINE_62

+  *         @arg @ref LL_EXTI_LINE_63

+  *         @arg @ref LL_EXTI_LINE_ALL_32_63

+  * @retval None

+  */

+__STATIC_INLINE void LL_EXTI_DisableEvent_32_63(uint32_t ExtiLine)

+{

+  CLEAR_BIT(EXTI->EMR2, ExtiLine);

+}

+

+/**

+  * @brief  Disable ExtiLine Event request for Lines in range 64 to 95

+  * @rmtoll EMR3         EMx           LL_EXTI_DisableEvent_64_95

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_64

+  *         @arg @ref LL_EXTI_LINE_65

+  *         @arg @ref LL_EXTI_LINE_66

+  *         @arg @ref LL_EXTI_LINE_67

+  *         @arg @ref LL_EXTI_LINE_68

+  *         @arg @ref LL_EXTI_LINE_69

+  *         @arg @ref LL_EXTI_LINE_70

+  *         @arg @ref LL_EXTI_LINE_71

+  *         @arg @ref LL_EXTI_LINE_72

+  *         @arg @ref LL_EXTI_LINE_73

+  *         @arg @ref LL_EXTI_LINE_74

+  *         @arg @ref LL_EXTI_LINE_75

+  *         @arg @ref LL_EXTI_LINE_76

+  *         @arg @ref LL_EXTI_LINE_77

+  *         @arg @ref LL_EXTI_LINE_78

+  *         @arg @ref LL_EXTI_LINE_79

+  *         @arg @ref LL_EXTI_LINE_80

+  *         @arg @ref LL_EXTI_LINE_82

+  *         @arg @ref LL_EXTI_LINE_84

+  *         @arg @ref LL_EXTI_LINE_85

+  *         @arg @ref LL_EXTI_LINE_86

+  *         @arg @ref LL_EXTI_LINE_87

+  *         @arg @ref LL_EXTI_LINE_ALL_64_95

+  * @retval None

+  */

+__STATIC_INLINE void LL_EXTI_DisableEvent_64_95(uint32_t ExtiLine)

+{

+  CLEAR_BIT(EXTI->EMR3, ExtiLine);

+}

+

+/**

+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31

+  * @rmtoll EMR1         EMx           LL_EXTI_IsEnabledEvent_0_31

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_0

+  *         @arg @ref LL_EXTI_LINE_1

+  *         @arg @ref LL_EXTI_LINE_2

+  *         @arg @ref LL_EXTI_LINE_3

+  *         @arg @ref LL_EXTI_LINE_4

+  *         @arg @ref LL_EXTI_LINE_5

+  *         @arg @ref LL_EXTI_LINE_6

+  *         @arg @ref LL_EXTI_LINE_7

+  *         @arg @ref LL_EXTI_LINE_8

+  *         @arg @ref LL_EXTI_LINE_9

+  *         @arg @ref LL_EXTI_LINE_10

+  *         @arg @ref LL_EXTI_LINE_11

+  *         @arg @ref LL_EXTI_LINE_12

+  *         @arg @ref LL_EXTI_LINE_13

+  *         @arg @ref LL_EXTI_LINE_14

+  *         @arg @ref LL_EXTI_LINE_15

+  *         @arg @ref LL_EXTI_LINE_16

+  *         @arg @ref LL_EXTI_LINE_17

+  *         @arg @ref LL_EXTI_LINE_18

+  *         @arg @ref LL_EXTI_LINE_19

+  *         @arg @ref LL_EXTI_LINE_20

+  *         @arg @ref LL_EXTI_LINE_21

+  *         @arg @ref LL_EXTI_LINE_22

+  *         @arg @ref LL_EXTI_LINE_23

+  *         @arg @ref LL_EXTI_LINE_24

+  *         @arg @ref LL_EXTI_LINE_25

+  *         @arg @ref LL_EXTI_LINE_26

+  *         @arg @ref LL_EXTI_LINE_27

+  *         @arg @ref LL_EXTI_LINE_28

+  *         @arg @ref LL_EXTI_LINE_29

+  *         @arg @ref LL_EXTI_LINE_30

+  *         @arg @ref LL_EXTI_LINE_31

+  *         @arg @ref LL_EXTI_LINE_ALL_0_31

+  * @note   Please check each device line mapping for EXTI Line availability

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)

+{

+  return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);

+}

+

+/**

+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63

+  * @rmtoll EMR2         EMx           LL_EXTI_IsEnabledEvent_32_63

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_32

+  *         @arg @ref LL_EXTI_LINE_33

+  *         @arg @ref LL_EXTI_LINE_34

+  *         @arg @ref LL_EXTI_LINE_35

+  *         @arg @ref LL_EXTI_LINE_36

+  *         @arg @ref LL_EXTI_LINE_37

+  *         @arg @ref LL_EXTI_LINE_38

+  *         @arg @ref LL_EXTI_LINE_39

+  *         @arg @ref LL_EXTI_LINE_40

+  *         @arg @ref LL_EXTI_LINE_41

+  *         @arg @ref LL_EXTI_LINE_42

+  *         @arg @ref LL_EXTI_LINE_43

+  *         @arg @ref LL_EXTI_LINE_44

+  *         @arg @ref LL_EXTI_LINE_46

+  *         @arg @ref LL_EXTI_LINE_47

+  *         @arg @ref LL_EXTI_LINE_48

+  *         @arg @ref LL_EXTI_LINE_49

+  *         @arg @ref LL_EXTI_LINE_50

+  *         @arg @ref LL_EXTI_LINE_51

+  *         @arg @ref LL_EXTI_LINE_52

+  *         @arg @ref LL_EXTI_LINE_53

+  *         @arg @ref LL_EXTI_LINE_54

+  *         @arg @ref LL_EXTI_LINE_55

+  *         @arg @ref LL_EXTI_LINE_56

+  *         @arg @ref LL_EXTI_LINE_57

+  *         @arg @ref LL_EXTI_LINE_58

+  *         @arg @ref LL_EXTI_LINE_59

+  *         @arg @ref LL_EXTI_LINE_60

+  *         @arg @ref LL_EXTI_LINE_61

+  *         @arg @ref LL_EXTI_LINE_62

+  *         @arg @ref LL_EXTI_LINE_63

+  *         @arg @ref LL_EXTI_LINE_ALL_32_63

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)

+{

+  return ((READ_BIT(EXTI->EMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);

+}

+

+/**

+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 64 to 95

+  * @rmtoll EMR3         EMx           LL_EXTI_IsEnabledEvent_64_95

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_64

+  *         @arg @ref LL_EXTI_LINE_65

+  *         @arg @ref LL_EXTI_LINE_66

+  *         @arg @ref LL_EXTI_LINE_67

+  *         @arg @ref LL_EXTI_LINE_68

+  *         @arg @ref LL_EXTI_LINE_69

+  *         @arg @ref LL_EXTI_LINE_70

+  *         @arg @ref LL_EXTI_LINE_71

+  *         @arg @ref LL_EXTI_LINE_72

+  *         @arg @ref LL_EXTI_LINE_73

+  *         @arg @ref LL_EXTI_LINE_74

+  *         @arg @ref LL_EXTI_LINE_75

+  *         @arg @ref LL_EXTI_LINE_76

+  *         @arg @ref LL_EXTI_LINE_77

+  *         @arg @ref LL_EXTI_LINE_78

+  *         @arg @ref LL_EXTI_LINE_79

+  *         @arg @ref LL_EXTI_LINE_80

+  *         @arg @ref LL_EXTI_LINE_82

+  *         @arg @ref LL_EXTI_LINE_84

+  *         @arg @ref LL_EXTI_LINE_85

+  *         @arg @ref LL_EXTI_LINE_86

+  *         @arg @ref LL_EXTI_LINE_87

+  *         @arg @ref LL_EXTI_LINE_ALL_64_95

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_64_95(uint32_t ExtiLine)

+{

+  return ((READ_BIT(EXTI->EMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);

+}

+

+#if defined(DUAL_CORE)

+

+/**

+  * @brief  Enable ExtiLine Event request for Lines in range 0 to 31 for cpu2

+  * @rmtoll C2EMR1         EMx           LL_C2_EXTI_EnableEvent_0_31

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_0

+  *         @arg @ref LL_EXTI_LINE_1

+  *         @arg @ref LL_EXTI_LINE_2

+  *         @arg @ref LL_EXTI_LINE_3

+  *         @arg @ref LL_EXTI_LINE_4

+  *         @arg @ref LL_EXTI_LINE_5

+  *         @arg @ref LL_EXTI_LINE_6

+  *         @arg @ref LL_EXTI_LINE_7

+  *         @arg @ref LL_EXTI_LINE_8

+  *         @arg @ref LL_EXTI_LINE_9

+  *         @arg @ref LL_EXTI_LINE_10

+  *         @arg @ref LL_EXTI_LINE_11

+  *         @arg @ref LL_EXTI_LINE_12

+  *         @arg @ref LL_EXTI_LINE_13

+  *         @arg @ref LL_EXTI_LINE_14

+  *         @arg @ref LL_EXTI_LINE_15

+  *         @arg @ref LL_EXTI_LINE_16

+  *         @arg @ref LL_EXTI_LINE_17

+  *         @arg @ref LL_EXTI_LINE_18

+  *         @arg @ref LL_EXTI_LINE_19

+  *         @arg @ref LL_EXTI_LINE_20

+  *         @arg @ref LL_EXTI_LINE_21

+  *         @arg @ref LL_EXTI_LINE_22

+  *         @arg @ref LL_EXTI_LINE_23

+  *         @arg @ref LL_EXTI_LINE_24

+  *         @arg @ref LL_EXTI_LINE_25

+  *         @arg @ref LL_EXTI_LINE_26

+  *         @arg @ref LL_EXTI_LINE_27

+  *         @arg @ref LL_EXTI_LINE_28

+  *         @arg @ref LL_EXTI_LINE_29

+  *         @arg @ref LL_EXTI_LINE_30

+  *         @arg @ref LL_EXTI_LINE_31

+  *         @arg @ref LL_EXTI_LINE_ALL_0_31

+  * @retval None

+  */

+__STATIC_INLINE void LL_C2_EXTI_EnableEvent_0_31(uint32_t ExtiLine)

+{

+  SET_BIT(EXTI->C2EMR1, ExtiLine);

+}

+

+

+/**

+  * @brief  Enable ExtiLine Event request for Lines in range 32 to 63 for cpu2

+  * @rmtoll C2EMR2         EMx           LL_C2_EXTI_EnableEvent_32_63

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_32

+  *         @arg @ref LL_EXTI_LINE_33

+  *         @arg @ref LL_EXTI_LINE_34

+  *         @arg @ref LL_EXTI_LINE_35

+  *         @arg @ref LL_EXTI_LINE_36

+  *         @arg @ref LL_EXTI_LINE_37

+  *         @arg @ref LL_EXTI_LINE_38

+  *         @arg @ref LL_EXTI_LINE_39

+  *         @arg @ref LL_EXTI_LINE_40

+  *         @arg @ref LL_EXTI_LINE_41

+  *         @arg @ref LL_EXTI_LINE_42

+  *         @arg @ref LL_EXTI_LINE_43

+  *         @arg @ref LL_EXTI_LINE_44

+  *         @arg @ref LL_EXTI_LINE_46

+  *         @arg @ref LL_EXTI_LINE_47

+  *         @arg @ref LL_EXTI_LINE_48

+  *         @arg @ref LL_EXTI_LINE_49

+  *         @arg @ref LL_EXTI_LINE_50

+  *         @arg @ref LL_EXTI_LINE_51

+  *         @arg @ref LL_EXTI_LINE_52

+  *         @arg @ref LL_EXTI_LINE_53

+  *         @arg @ref LL_EXTI_LINE_54

+  *         @arg @ref LL_EXTI_LINE_55

+  *         @arg @ref LL_EXTI_LINE_56

+  *         @arg @ref LL_EXTI_LINE_57

+  *         @arg @ref LL_EXTI_LINE_58

+  *         @arg @ref LL_EXTI_LINE_59

+  *         @arg @ref LL_EXTI_LINE_60

+  *         @arg @ref LL_EXTI_LINE_61

+  *         @arg @ref LL_EXTI_LINE_62

+  *         @arg @ref LL_EXTI_LINE_63

+  *         @arg @ref LL_EXTI_LINE_ALL_32_63

+  * @retval None

+  */

+__STATIC_INLINE void LL_C2_EXTI_EnableEvent_32_63(uint32_t ExtiLine)

+{

+  SET_BIT(EXTI->C2EMR2, ExtiLine);

+}

+

+/**

+  * @brief  Enable ExtiLine Event request for Lines in range 64 to 95 for cpu2

+  * @rmtoll C2EMR3         EMx           LL_C2_EXTI_EnableEvent_64_95

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_64

+  *         @arg @ref LL_EXTI_LINE_65

+  *         @arg @ref LL_EXTI_LINE_66

+  *         @arg @ref LL_EXTI_LINE_67

+  *         @arg @ref LL_EXTI_LINE_68

+  *         @arg @ref LL_EXTI_LINE_69

+  *         @arg @ref LL_EXTI_LINE_70

+  *         @arg @ref LL_EXTI_LINE_71

+  *         @arg @ref LL_EXTI_LINE_72

+  *         @arg @ref LL_EXTI_LINE_73

+  *         @arg @ref LL_EXTI_LINE_74

+  *         @arg @ref LL_EXTI_LINE_75

+  *         @arg @ref LL_EXTI_LINE_76

+  *         @arg @ref LL_EXTI_LINE_77

+  *         @arg @ref LL_EXTI_LINE_78

+  *         @arg @ref LL_EXTI_LINE_79

+  *         @arg @ref LL_EXTI_LINE_80

+  *         @arg @ref LL_EXTI_LINE_82

+  *         @arg @ref LL_EXTI_LINE_84

+  *         @arg @ref LL_EXTI_LINE_85

+  *         @arg @ref LL_EXTI_LINE_86

+  *         @arg @ref LL_EXTI_LINE_87

+  *         @arg @ref LL_EXTI_LINE_ALL_64_95

+  * @retval None

+  */

+__STATIC_INLINE void LL_C2_EXTI_EnableEvent_64_95(uint32_t ExtiLine)

+{

+  SET_BIT(EXTI->C2EMR3, ExtiLine);

+}

+

+

+/**

+  * @brief  Disable ExtiLine Event request for Lines in range 0 to 31 for cpu2

+  * @rmtoll C2EMR1         EMx           LL_C2_EXTI_DisableEvent_0_31

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_0

+  *         @arg @ref LL_EXTI_LINE_1

+  *         @arg @ref LL_EXTI_LINE_2

+  *         @arg @ref LL_EXTI_LINE_3

+  *         @arg @ref LL_EXTI_LINE_4

+  *         @arg @ref LL_EXTI_LINE_5

+  *         @arg @ref LL_EXTI_LINE_6

+  *         @arg @ref LL_EXTI_LINE_7

+  *         @arg @ref LL_EXTI_LINE_8

+  *         @arg @ref LL_EXTI_LINE_9

+  *         @arg @ref LL_EXTI_LINE_10

+  *         @arg @ref LL_EXTI_LINE_11

+  *         @arg @ref LL_EXTI_LINE_12

+  *         @arg @ref LL_EXTI_LINE_13

+  *         @arg @ref LL_EXTI_LINE_14

+  *         @arg @ref LL_EXTI_LINE_15

+  *         @arg @ref LL_EXTI_LINE_16

+  *         @arg @ref LL_EXTI_LINE_17

+  *         @arg @ref LL_EXTI_LINE_18

+  *         @arg @ref LL_EXTI_LINE_19

+  *         @arg @ref LL_EXTI_LINE_20

+  *         @arg @ref LL_EXTI_LINE_21

+  *         @arg @ref LL_EXTI_LINE_22

+  *         @arg @ref LL_EXTI_LINE_23

+  *         @arg @ref LL_EXTI_LINE_24

+  *         @arg @ref LL_EXTI_LINE_25

+  *         @arg @ref LL_EXTI_LINE_26

+  *         @arg @ref LL_EXTI_LINE_27

+  *         @arg @ref LL_EXTI_LINE_28

+  *         @arg @ref LL_EXTI_LINE_29

+  *         @arg @ref LL_EXTI_LINE_30

+  *         @arg @ref LL_EXTI_LINE_31

+  *         @arg @ref LL_EXTI_LINE_ALL_0_31

+  * @retval None

+  */

+__STATIC_INLINE void LL_C2_EXTI_DisableEvent_0_31(uint32_t ExtiLine)

+{

+  CLEAR_BIT(EXTI->C2EMR1, ExtiLine);

+}

+

+

+/**

+  * @brief  Disable ExtiLine Event request for Lines in range 32 to 63 for cpu2

+  * @rmtoll C2EMR2         EMx           LL_C2_EXTI_DisableEvent_32_63

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_32

+  *         @arg @ref LL_EXTI_LINE_33

+  *         @arg @ref LL_EXTI_LINE_34

+  *         @arg @ref LL_EXTI_LINE_35

+  *         @arg @ref LL_EXTI_LINE_36

+  *         @arg @ref LL_EXTI_LINE_37

+  *         @arg @ref LL_EXTI_LINE_38

+  *         @arg @ref LL_EXTI_LINE_39

+  *         @arg @ref LL_EXTI_LINE_40

+  *         @arg @ref LL_EXTI_LINE_41

+  *         @arg @ref LL_EXTI_LINE_42

+  *         @arg @ref LL_EXTI_LINE_43

+  *         @arg @ref LL_EXTI_LINE_44

+  *         @arg @ref LL_EXTI_LINE_46

+  *         @arg @ref LL_EXTI_LINE_47

+  *         @arg @ref LL_EXTI_LINE_48

+  *         @arg @ref LL_EXTI_LINE_49

+  *         @arg @ref LL_EXTI_LINE_50

+  *         @arg @ref LL_EXTI_LINE_51

+  *         @arg @ref LL_EXTI_LINE_52

+  *         @arg @ref LL_EXTI_LINE_53

+  *         @arg @ref LL_EXTI_LINE_54

+  *         @arg @ref LL_EXTI_LINE_55

+  *         @arg @ref LL_EXTI_LINE_56

+  *         @arg @ref LL_EXTI_LINE_57

+  *         @arg @ref LL_EXTI_LINE_58

+  *         @arg @ref LL_EXTI_LINE_59

+  *         @arg @ref LL_EXTI_LINE_60

+  *         @arg @ref LL_EXTI_LINE_61

+  *         @arg @ref LL_EXTI_LINE_62

+  *         @arg @ref LL_EXTI_LINE_63

+  *         @arg @ref LL_EXTI_LINE_ALL_32_63

+  * @retval None

+  */

+__STATIC_INLINE void LL_C2_EXTI_DisableEvent_32_63(uint32_t ExtiLine)

+{

+  CLEAR_BIT(EXTI->C2EMR2, ExtiLine);

+}

+

+

+/**

+  * @brief  Disable ExtiLine Event request for Lines in range 64 to 95 for cpu2

+  * @rmtoll C2EMR3         EMx           LL_C2_EXTI_DisableEvent_64_95

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_64

+  *         @arg @ref LL_EXTI_LINE_65

+  *         @arg @ref LL_EXTI_LINE_66

+  *         @arg @ref LL_EXTI_LINE_67

+  *         @arg @ref LL_EXTI_LINE_68

+  *         @arg @ref LL_EXTI_LINE_69

+  *         @arg @ref LL_EXTI_LINE_70

+  *         @arg @ref LL_EXTI_LINE_71

+  *         @arg @ref LL_EXTI_LINE_72

+  *         @arg @ref LL_EXTI_LINE_73

+  *         @arg @ref LL_EXTI_LINE_74

+  *         @arg @ref LL_EXTI_LINE_75

+  *         @arg @ref LL_EXTI_LINE_76

+  *         @arg @ref LL_EXTI_LINE_77

+  *         @arg @ref LL_EXTI_LINE_78

+  *         @arg @ref LL_EXTI_LINE_79

+  *         @arg @ref LL_EXTI_LINE_80

+  *         @arg @ref LL_EXTI_LINE_82

+  *         @arg @ref LL_EXTI_LINE_84

+  *         @arg @ref LL_EXTI_LINE_85

+  *         @arg @ref LL_EXTI_LINE_86

+  *         @arg @ref LL_EXTI_LINE_87

+  *         @arg @ref LL_EXTI_LINE_ALL_64_95

+  * @retval None

+  */

+__STATIC_INLINE void LL_C2_EXTI_DisableEvent_64_95(uint32_t ExtiLine)

+{

+  CLEAR_BIT(EXTI->C2EMR3, ExtiLine);

+}

+

+

+/**

+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 for cpu2

+  * @rmtoll C2EMR1         EMx           LL_C2_EXTI_IsEnabledEvent_0_31

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_0

+  *         @arg @ref LL_EXTI_LINE_1

+  *         @arg @ref LL_EXTI_LINE_2

+  *         @arg @ref LL_EXTI_LINE_3

+  *         @arg @ref LL_EXTI_LINE_4

+  *         @arg @ref LL_EXTI_LINE_5

+  *         @arg @ref LL_EXTI_LINE_6

+  *         @arg @ref LL_EXTI_LINE_7

+  *         @arg @ref LL_EXTI_LINE_8

+  *         @arg @ref LL_EXTI_LINE_9

+  *         @arg @ref LL_EXTI_LINE_10

+  *         @arg @ref LL_EXTI_LINE_11

+  *         @arg @ref LL_EXTI_LINE_12

+  *         @arg @ref LL_EXTI_LINE_13

+  *         @arg @ref LL_EXTI_LINE_14

+  *         @arg @ref LL_EXTI_LINE_15

+  *         @arg @ref LL_EXTI_LINE_16

+  *         @arg @ref LL_EXTI_LINE_17

+  *         @arg @ref LL_EXTI_LINE_18

+  *         @arg @ref LL_EXTI_LINE_19

+  *         @arg @ref LL_EXTI_LINE_20

+  *         @arg @ref LL_EXTI_LINE_21

+  *         @arg @ref LL_EXTI_LINE_22

+  *         @arg @ref LL_EXTI_LINE_23

+  *         @arg @ref LL_EXTI_LINE_24

+  *         @arg @ref LL_EXTI_LINE_25

+  *         @arg @ref LL_EXTI_LINE_26

+  *         @arg @ref LL_EXTI_LINE_27

+  *         @arg @ref LL_EXTI_LINE_28

+  *         @arg @ref LL_EXTI_LINE_29

+  *         @arg @ref LL_EXTI_LINE_30

+  *         @arg @ref LL_EXTI_LINE_31

+  *         @arg @ref LL_EXTI_LINE_ALL_0_31

+  * @note   Please check each device line mapping for EXTI Line availability

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine)

+{

+  return ((READ_BIT(EXTI->C2EMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);

+}

+

+

+/**

+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 32 to 63 for cpu2

+  * @rmtoll C2EMR2         EMx           LL_C2_EXTI_IsEnabledEvent_32_63

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_32

+  *         @arg @ref LL_EXTI_LINE_33

+  *         @arg @ref LL_EXTI_LINE_34

+  *         @arg @ref LL_EXTI_LINE_35

+  *         @arg @ref LL_EXTI_LINE_36

+  *         @arg @ref LL_EXTI_LINE_37

+  *         @arg @ref LL_EXTI_LINE_38

+  *         @arg @ref LL_EXTI_LINE_39

+  *         @arg @ref LL_EXTI_LINE_40

+  *         @arg @ref LL_EXTI_LINE_41

+  *         @arg @ref LL_EXTI_LINE_42

+  *         @arg @ref LL_EXTI_LINE_43

+  *         @arg @ref LL_EXTI_LINE_44

+  *         @arg @ref LL_EXTI_LINE_46

+  *         @arg @ref LL_EXTI_LINE_47

+  *         @arg @ref LL_EXTI_LINE_48

+  *         @arg @ref LL_EXTI_LINE_49

+  *         @arg @ref LL_EXTI_LINE_50

+  *         @arg @ref LL_EXTI_LINE_51

+  *         @arg @ref LL_EXTI_LINE_52

+  *         @arg @ref LL_EXTI_LINE_53

+  *         @arg @ref LL_EXTI_LINE_54

+  *         @arg @ref LL_EXTI_LINE_55

+  *         @arg @ref LL_EXTI_LINE_56

+  *         @arg @ref LL_EXTI_LINE_57

+  *         @arg @ref LL_EXTI_LINE_58

+  *         @arg @ref LL_EXTI_LINE_59

+  *         @arg @ref LL_EXTI_LINE_60

+  *         @arg @ref LL_EXTI_LINE_61

+  *         @arg @ref LL_EXTI_LINE_62

+  *         @arg @ref LL_EXTI_LINE_63

+  *         @arg @ref LL_EXTI_LINE_ALL_32_63

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_32_63(uint32_t ExtiLine)

+{

+  return ((READ_BIT(EXTI->C2EMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);

+}

+

+

+/**

+  * @brief  Indicate if ExtiLine Event request is enabled for Lines in range 64 to 95 for cpu2

+  * @rmtoll C2EMR3         EMx           LL_C2_EXTI_IsEnabledEvent_64_95

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_64

+  *         @arg @ref LL_EXTI_LINE_65

+  *         @arg @ref LL_EXTI_LINE_66

+  *         @arg @ref LL_EXTI_LINE_67

+  *         @arg @ref LL_EXTI_LINE_68

+  *         @arg @ref LL_EXTI_LINE_69

+  *         @arg @ref LL_EXTI_LINE_70

+  *         @arg @ref LL_EXTI_LINE_71

+  *         @arg @ref LL_EXTI_LINE_72

+  *         @arg @ref LL_EXTI_LINE_73

+  *         @arg @ref LL_EXTI_LINE_74

+  *         @arg @ref LL_EXTI_LINE_75

+  *         @arg @ref LL_EXTI_LINE_76

+  *         @arg @ref LL_EXTI_LINE_77

+  *         @arg @ref LL_EXTI_LINE_78

+  *         @arg @ref LL_EXTI_LINE_79

+  *         @arg @ref LL_EXTI_LINE_80

+  *         @arg @ref LL_EXTI_LINE_82

+  *         @arg @ref LL_EXTI_LINE_84

+  *         @arg @ref LL_EXTI_LINE_85

+  *         @arg @ref LL_EXTI_LINE_86

+  *         @arg @ref LL_EXTI_LINE_87

+  *         @arg @ref LL_EXTI_LINE_ALL_64_95

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C2_EXTI_IsEnabledEvent_64_95(uint32_t ExtiLine)

+{

+  return ((READ_BIT(EXTI->C2EMR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);

+}

+

+

+#endif /* DUAL_CORE */

+

+/**

+  * @}

+  */

+

+/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management

+  * @{

+  */

+

+/**

+  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31

+  * @note The configurable wakeup lines are edge-triggered. No glitch must be

+  *       generated on these lines. If a rising edge on a configurable interrupt

+  *       line occurs during a write operation in the EXTI_RTSR register, the

+  *       pending bit is not set.

+  *       Rising and falling edge triggers can be set for

+  *       the same interrupt line. In this case, both generate a trigger

+  *       condition.

+  * @rmtoll RTSR1        RTx           LL_EXTI_EnableRisingTrig_0_31

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_0

+  *         @arg @ref LL_EXTI_LINE_1

+  *         @arg @ref LL_EXTI_LINE_2

+  *         @arg @ref LL_EXTI_LINE_3

+  *         @arg @ref LL_EXTI_LINE_4

+  *         @arg @ref LL_EXTI_LINE_5

+  *         @arg @ref LL_EXTI_LINE_6

+  *         @arg @ref LL_EXTI_LINE_7

+  *         @arg @ref LL_EXTI_LINE_8

+  *         @arg @ref LL_EXTI_LINE_9

+  *         @arg @ref LL_EXTI_LINE_10

+  *         @arg @ref LL_EXTI_LINE_11

+  *         @arg @ref LL_EXTI_LINE_12

+  *         @arg @ref LL_EXTI_LINE_13

+  *         @arg @ref LL_EXTI_LINE_14

+  *         @arg @ref LL_EXTI_LINE_15

+  *         @arg @ref LL_EXTI_LINE_16

+  *         @arg @ref LL_EXTI_LINE_17

+  *         @arg @ref LL_EXTI_LINE_18

+  *         @arg @ref LL_EXTI_LINE_19

+  *         @arg @ref LL_EXTI_LINE_20

+  *         @arg @ref LL_EXTI_LINE_21

+  * @retval None

+  */

+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine)

+{

+  SET_BIT(EXTI->RTSR1, ExtiLine);

+

+}

+

+/**

+  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 32 to 63

+  * @note The configurable wakeup lines are edge-triggered. No glitch must be

+  *       generated on these lines. If a rising edge on a configurable interrupt

+  *       line occurs during a write operation in the EXTI_RTSR register, the

+  *       pending bit is not set.Rising and falling edge triggers can be set for

+  *       the same interrupt line. In this case, both generate a trigger

+  *       condition.

+  * @rmtoll RTSR2        RTx           LL_EXTI_EnableRisingTrig_32_63

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_49

+  *         @arg @ref LL_EXTI_LINE_51

+  * @retval None

+  */

+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_32_63(uint32_t ExtiLine)

+{

+  SET_BIT(EXTI->RTSR2, ExtiLine);

+}

+

+/**

+  * @brief  Enable ExtiLine Rising Edge Trigger for Lines in range 64 to 95

+  * @note The configurable wakeup lines are edge-triggered. No glitch must be

+  *       generated on these lines. If a rising edge on a configurable interrupt

+  *       line occurs during a write operation in the EXTI_RTSR register, the

+  *       pending bit is not set.Rising and falling edge triggers can be set for

+  *       the same interrupt line. In this case, both generate a trigger

+  *       condition.

+  * @rmtoll RTSR3        RTx           LL_EXTI_EnableRisingTrig_64_95

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_82

+  *         @arg @ref LL_EXTI_LINE_84

+  *         @arg @ref LL_EXTI_LINE_85

+  *         @arg @ref LL_EXTI_LINE_86

+  * @retval None

+  */

+__STATIC_INLINE void LL_EXTI_EnableRisingTrig_64_95(uint32_t ExtiLine)

+{

+  SET_BIT(EXTI->RTSR3, ExtiLine);

+}

+

+/**

+  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31

+  * @note The configurable wakeup lines are edge-triggered. No glitch must be

+  *       generated on these lines. If a rising edge on a configurable interrupt

+  *       line occurs during a write operation in the EXTI_RTSR register, the

+  *       pending bit is not set.

+  *       Rising and falling edge triggers can be set for

+  *       the same interrupt line. In this case, both generate a trigger

+  *       condition.

+  * @rmtoll RTSR1        RTx           LL_EXTI_DisableRisingTrig_0_31

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_0

+  *         @arg @ref LL_EXTI_LINE_1

+  *         @arg @ref LL_EXTI_LINE_2

+  *         @arg @ref LL_EXTI_LINE_3

+  *         @arg @ref LL_EXTI_LINE_4

+  *         @arg @ref LL_EXTI_LINE_5

+  *         @arg @ref LL_EXTI_LINE_6

+  *         @arg @ref LL_EXTI_LINE_7

+  *         @arg @ref LL_EXTI_LINE_8

+  *         @arg @ref LL_EXTI_LINE_9

+  *         @arg @ref LL_EXTI_LINE_10

+  *         @arg @ref LL_EXTI_LINE_11

+  *         @arg @ref LL_EXTI_LINE_12

+  *         @arg @ref LL_EXTI_LINE_13

+  *         @arg @ref LL_EXTI_LINE_14

+  *         @arg @ref LL_EXTI_LINE_15

+  *         @arg @ref LL_EXTI_LINE_16

+  *         @arg @ref LL_EXTI_LINE_17

+  *         @arg @ref LL_EXTI_LINE_18

+  *         @arg @ref LL_EXTI_LINE_19

+  *         @arg @ref LL_EXTI_LINE_20

+  *         @arg @ref LL_EXTI_LINE_21

+  * @retval None

+  */

+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine)

+{

+  CLEAR_BIT(EXTI->RTSR1, ExtiLine);

+

+}

+

+/**

+  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 32 to 63

+  * @note The configurable wakeup lines are edge-triggered. No glitch must be

+  *       generated on these lines. If a rising edge on a configurable interrupt

+  *       line occurs during a write operation in the EXTI_RTSR register, the

+  *       pending bit is not set.

+  *       Rising and falling edge triggers can be set for

+  *       the same interrupt line. In this case, both generate a trigger

+  *       condition.

+  * @rmtoll RTSR2        RTx           LL_EXTI_DisableRisingTrig_32_63

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_49

+  *         @arg @ref LL_EXTI_LINE_51

+  * @retval None

+  */

+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_32_63(uint32_t ExtiLine)

+{

+  CLEAR_BIT(EXTI->RTSR2, ExtiLine);

+}

+

+/**

+  * @brief  Disable ExtiLine Rising Edge Trigger for Lines in range 64 to 95

+  * @note The configurable wakeup lines are edge-triggered. No glitch must be

+  *       generated on these lines. If a rising edge on a configurable interrupt

+  *       line occurs during a write operation in the EXTI_RTSR register, the

+  *       pending bit is not set.

+  *       Rising and falling edge triggers can be set for

+  *       the same interrupt line. In this case, both generate a trigger

+  *       condition.

+  * @rmtoll RTSR3        RTx           LL_EXTI_DisableRisingTrig_64_95

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_82

+  *         @arg @ref LL_EXTI_LINE_84

+  *         @arg @ref LL_EXTI_LINE_85

+  *         @arg @ref LL_EXTI_LINE_86

+  * @retval None

+  */

+__STATIC_INLINE void LL_EXTI_DisableRisingTrig_64_95(uint32_t ExtiLine)

+{

+  CLEAR_BIT(EXTI->RTSR3, ExtiLine);

+}

+

+/**

+  * @brief  Check if rising edge trigger is enabled for Lines in range 0 to 31

+  * @rmtoll RTSR1        RTx           LL_EXTI_IsEnabledRisingTrig_0_31

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_0

+  *         @arg @ref LL_EXTI_LINE_1

+  *         @arg @ref LL_EXTI_LINE_2

+  *         @arg @ref LL_EXTI_LINE_3

+  *         @arg @ref LL_EXTI_LINE_4

+  *         @arg @ref LL_EXTI_LINE_5

+  *         @arg @ref LL_EXTI_LINE_6

+  *         @arg @ref LL_EXTI_LINE_7

+  *         @arg @ref LL_EXTI_LINE_8

+  *         @arg @ref LL_EXTI_LINE_9

+  *         @arg @ref LL_EXTI_LINE_10

+  *         @arg @ref LL_EXTI_LINE_11

+  *         @arg @ref LL_EXTI_LINE_12

+  *         @arg @ref LL_EXTI_LINE_13

+  *         @arg @ref LL_EXTI_LINE_14

+  *         @arg @ref LL_EXTI_LINE_15

+  *         @arg @ref LL_EXTI_LINE_16

+  *         @arg @ref LL_EXTI_LINE_17

+  *         @arg @ref LL_EXTI_LINE_18

+  *         @arg @ref LL_EXTI_LINE_19

+  *         @arg @ref LL_EXTI_LINE_20

+  *         @arg @ref LL_EXTI_LINE_21

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine)

+{

+  return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);

+}

+

+

+/**

+  * @brief  Check if rising edge trigger is enabled for Lines in range 32 to 63

+  * @rmtoll RTSR2        RTx           LL_EXTI_IsEnabledRisingTrig_32_63

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_49

+  *         @arg @ref LL_EXTI_LINE_51

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_32_63(uint32_t ExtiLine)

+{

+  return ((READ_BIT(EXTI->RTSR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);

+}

+

+/**

+  * @brief  Check if rising edge trigger is enabled for Lines in range 64 to 95

+  * @rmtoll RTSR3        RTx           LL_EXTI_IsEnabledRisingTrig_64_95

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_82

+  *         @arg @ref LL_EXTI_LINE_84

+  *         @arg @ref LL_EXTI_LINE_85

+  *         @arg @ref LL_EXTI_LINE_86

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_64_95(uint32_t ExtiLine)

+{

+  return ((READ_BIT(EXTI->RTSR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management

+  * @{

+  */

+

+/**

+  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31

+  * @note The configurable wakeup lines are edge-triggered. No glitch must be

+  *       generated on these lines. If a falling edge on a configurable interrupt

+  *       line occurs during a write operation in the EXTI_FTSR register, the

+  *       pending bit is not set.

+  *       Rising and falling edge triggers can be set for

+  *       the same interrupt line. In this case, both generate a trigger

+  *       condition.

+  * @rmtoll FTSR1        FTx           LL_EXTI_EnableFallingTrig_0_31

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_0

+  *         @arg @ref LL_EXTI_LINE_1

+  *         @arg @ref LL_EXTI_LINE_2

+  *         @arg @ref LL_EXTI_LINE_3

+  *         @arg @ref LL_EXTI_LINE_4

+  *         @arg @ref LL_EXTI_LINE_5

+  *         @arg @ref LL_EXTI_LINE_6

+  *         @arg @ref LL_EXTI_LINE_7

+  *         @arg @ref LL_EXTI_LINE_8

+  *         @arg @ref LL_EXTI_LINE_9

+  *         @arg @ref LL_EXTI_LINE_10

+  *         @arg @ref LL_EXTI_LINE_11

+  *         @arg @ref LL_EXTI_LINE_12

+  *         @arg @ref LL_EXTI_LINE_13

+  *         @arg @ref LL_EXTI_LINE_14

+  *         @arg @ref LL_EXTI_LINE_15

+  *         @arg @ref LL_EXTI_LINE_16

+  *         @arg @ref LL_EXTI_LINE_18

+  *         @arg @ref LL_EXTI_LINE_19

+  *         @arg @ref LL_EXTI_LINE_20

+  *         @arg @ref LL_EXTI_LINE_21

+  * @note   Please check each device line mapping for EXTI Line availability

+  * @retval None

+  */

+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine)

+{

+  SET_BIT(EXTI->FTSR1, ExtiLine);

+}

+

+/**

+  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 32 to 63

+  * @note The configurable wakeup lines are edge-triggered. No glitch must be

+  *       generated on these lines. If a Falling edge on a configurable interrupt

+  *       line occurs during a write operation in the EXTI_FTSR register, the

+  *       pending bit is not set.

+  *       Rising and falling edge triggers can be set for

+  *       the same interrupt line. In this case, both generate a trigger

+  *       condition.

+  * @rmtoll FTSR2        FTx           LL_EXTI_EnableFallingTrig_32_63

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_49

+  *         @arg @ref LL_EXTI_LINE_51

+  * @retval None

+  */

+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_32_63(uint32_t ExtiLine)

+{

+  SET_BIT(EXTI->FTSR2, ExtiLine);

+}

+

+/**

+  * @brief  Enable ExtiLine Falling Edge Trigger for Lines in range 64 to 95

+  * @note The configurable wakeup lines are edge-triggered. No glitch must be

+  *       generated on these lines. If a Falling edge on a configurable interrupt

+  *       line occurs during a write operation in the EXTI_FTSR register, the

+  *       pending bit is not set.

+  *       Rising and falling edge triggers can be set for

+  *       the same interrupt line. In this case, both generate a trigger

+  *       condition.

+  * @rmtoll FTSR3        FTx           LL_EXTI_EnableFallingTrig_64_95

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_82

+  *         @arg @ref LL_EXTI_LINE_84

+  *         @arg @ref LL_EXTI_LINE_85

+  *         @arg @ref LL_EXTI_LINE_86

+  * @retval None

+  */

+__STATIC_INLINE void LL_EXTI_EnableFallingTrig_64_95(uint32_t ExtiLine)

+{

+  SET_BIT(EXTI->FTSR3, ExtiLine);

+}

+

+

+/**

+  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31

+  * @note The configurable wakeup lines are edge-triggered. No glitch must be

+  *       generated on these lines. If a Falling edge on a configurable interrupt

+  *       line occurs during a write operation in the EXTI_FTSR register, the

+  *       pending bit is not set.

+  *       Rising and falling edge triggers can be set for the same interrupt line.

+  *       In this case, both generate a trigger condition.

+  * @rmtoll FTSR1        FTx           LL_EXTI_DisableFallingTrig_0_31

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_0

+  *         @arg @ref LL_EXTI_LINE_1

+  *         @arg @ref LL_EXTI_LINE_2

+  *         @arg @ref LL_EXTI_LINE_3

+  *         @arg @ref LL_EXTI_LINE_4

+  *         @arg @ref LL_EXTI_LINE_5

+  *         @arg @ref LL_EXTI_LINE_6

+  *         @arg @ref LL_EXTI_LINE_7

+  *         @arg @ref LL_EXTI_LINE_8

+  *         @arg @ref LL_EXTI_LINE_9

+  *         @arg @ref LL_EXTI_LINE_10

+  *         @arg @ref LL_EXTI_LINE_11

+  *         @arg @ref LL_EXTI_LINE_12

+  *         @arg @ref LL_EXTI_LINE_13

+  *         @arg @ref LL_EXTI_LINE_14

+  *         @arg @ref LL_EXTI_LINE_15

+  *         @arg @ref LL_EXTI_LINE_16

+  *         @arg @ref LL_EXTI_LINE_18

+  *         @arg @ref LL_EXTI_LINE_19

+  *         @arg @ref LL_EXTI_LINE_20

+  *         @arg @ref LL_EXTI_LINE_21

+  * @note   Please check each device line mapping for EXTI Line availability

+  * @retval None

+  */

+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine)

+{

+  CLEAR_BIT(EXTI->FTSR1, ExtiLine);

+}

+

+/**

+  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 32 to 63

+  * @note The configurable wakeup lines are edge-triggered. No glitch must be

+  *       generated on these lines. If a Falling edge on a configurable interrupt

+  *       line occurs during a write operation in the EXTI_FTSR register, the

+  *       pending bit is not set.

+  *       Rising and falling edge triggers can be set for the same interrupt line.

+  *       In this case, both generate a trigger condition.

+  * @rmtoll FTSR2        FTx           LL_EXTI_DisableFallingTrig_32_63

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_49

+  *         @arg @ref LL_EXTI_LINE_51

+  * @retval None

+  */

+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_32_63(uint32_t ExtiLine)

+{

+  CLEAR_BIT(EXTI->FTSR2, ExtiLine);

+}

+

+/**

+  * @brief  Disable ExtiLine Falling Edge Trigger for Lines in range 64 to 95

+  * @note The configurable wakeup lines are edge-triggered. No glitch must be

+  *       generated on these lines. If a Falling edge on a configurable interrupt

+  *       line occurs during a write operation in the EXTI_FTSR register, the

+  *       pending bit is not set.

+  *       Rising and falling edge triggers can be set for the same interrupt line.

+  *       In this case, both generate a trigger condition.

+  * @rmtoll FTSR3        FTx           LL_EXTI_DisableFallingTrig_64_95

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_82

+  *         @arg @ref LL_EXTI_LINE_84

+  *         @arg @ref LL_EXTI_LINE_85

+  *         @arg @ref LL_EXTI_LINE_86

+  * @retval None

+  */

+__STATIC_INLINE void LL_EXTI_DisableFallingTrig_64_95(uint32_t ExtiLine)

+{

+  CLEAR_BIT(EXTI->FTSR3, ExtiLine);

+}

+

+

+/**

+  * @brief  Check if falling edge trigger is enabled for Lines in range 0 to 31

+  * @rmtoll FTSR1        FTx           LL_EXTI_IsEnabledFallingTrig_0_31

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_0

+  *         @arg @ref LL_EXTI_LINE_1

+  *         @arg @ref LL_EXTI_LINE_2

+  *         @arg @ref LL_EXTI_LINE_3

+  *         @arg @ref LL_EXTI_LINE_4

+  *         @arg @ref LL_EXTI_LINE_5

+  *         @arg @ref LL_EXTI_LINE_6

+  *         @arg @ref LL_EXTI_LINE_7

+  *         @arg @ref LL_EXTI_LINE_8

+  *         @arg @ref LL_EXTI_LINE_9

+  *         @arg @ref LL_EXTI_LINE_10

+  *         @arg @ref LL_EXTI_LINE_11

+  *         @arg @ref LL_EXTI_LINE_12

+  *         @arg @ref LL_EXTI_LINE_13

+  *         @arg @ref LL_EXTI_LINE_14

+  *         @arg @ref LL_EXTI_LINE_15

+  *         @arg @ref LL_EXTI_LINE_16

+  *         @arg @ref LL_EXTI_LINE_18

+  *         @arg @ref LL_EXTI_LINE_19

+  *         @arg @ref LL_EXTI_LINE_20

+  *         @arg @ref LL_EXTI_LINE_21

+  * @note   Please check each device line mapping for EXTI Line availability

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine)

+{

+  return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);

+}

+

+/**

+  * @brief  Check if falling edge trigger is enabled for Lines in range 32 to 63

+  * @rmtoll FTSR2        FTx           LL_EXTI_IsEnabledFallingTrig_32_63

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_49

+  *         @arg @ref LL_EXTI_LINE_51

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_32_63(uint32_t ExtiLine)

+{

+  return ((READ_BIT(EXTI->FTSR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);

+}

+

+/**

+  * @brief  Check if falling edge trigger is enabled for Lines in range 64 to 95

+  * @rmtoll FTSR3        FTx           LL_EXTI_IsEnabledFallingTrig_64_95

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_82

+  *         @arg @ref LL_EXTI_LINE_84

+  *         @arg @ref LL_EXTI_LINE_85

+  *         @arg @ref LL_EXTI_LINE_86

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_64_95(uint32_t ExtiLine)

+{

+  return ((READ_BIT(EXTI->FTSR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);

+}

+

+

+/**

+  * @}

+  */

+

+/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management

+  * @{

+  */

+

+/**

+  * @brief  Generate a software Interrupt Event for Lines in range 0 to 31

+  * @note If the interrupt is enabled on this line in the EXTI_C1IMR1, writing a 1 to

+  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR1

+  *       resulting in an interrupt request generation.

+  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR1

+  *       register (by writing a 1 into the bit)

+  * @rmtoll SWIER1       SWIx          LL_EXTI_GenerateSWI_0_31

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_0

+  *         @arg @ref LL_EXTI_LINE_1

+  *         @arg @ref LL_EXTI_LINE_2

+  *         @arg @ref LL_EXTI_LINE_3

+  *         @arg @ref LL_EXTI_LINE_4

+  *         @arg @ref LL_EXTI_LINE_5

+  *         @arg @ref LL_EXTI_LINE_6

+  *         @arg @ref LL_EXTI_LINE_7

+  *         @arg @ref LL_EXTI_LINE_8

+  *         @arg @ref LL_EXTI_LINE_9

+  *         @arg @ref LL_EXTI_LINE_10

+  *         @arg @ref LL_EXTI_LINE_11

+  *         @arg @ref LL_EXTI_LINE_12

+  *         @arg @ref LL_EXTI_LINE_13

+  *         @arg @ref LL_EXTI_LINE_14

+  *         @arg @ref LL_EXTI_LINE_15

+  *         @arg @ref LL_EXTI_LINE_16

+  *         @arg @ref LL_EXTI_LINE_18

+  *         @arg @ref LL_EXTI_LINE_19

+  *         @arg @ref LL_EXTI_LINE_20

+  *         @arg @ref LL_EXTI_LINE_21

+  * @note   Please check each device line mapping for EXTI Line availability

+  * @retval None

+  */

+__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine)

+{

+  SET_BIT(EXTI->SWIER1, ExtiLine);

+}

+

+/**

+  * @brief  Generate a software Interrupt Event for Lines in range 32 to 63

+  * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to

+  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2

+  *       resulting in an interrupt request generation.

+  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR2

+  *       register (by writing a 1 into the bit)

+  * @rmtoll SWIER2       SWIx          LL_EXTI_GenerateSWI_32_63

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_49

+  *         @arg @ref LL_EXTI_LINE_51

+  * @retval None

+  */

+__STATIC_INLINE void LL_EXTI_GenerateSWI_32_63(uint32_t ExtiLine)

+{

+  SET_BIT(EXTI->SWIER2, ExtiLine);

+}

+

+/**

+  * @brief  Generate a software Interrupt Event for Lines in range 64 to 95

+  * @note If the interrupt is enabled on this line in the EXTI_IMR2, writing a 1 to

+  *       this bit when it is at '0' sets the corresponding pending bit in EXTI_PR2

+  *       resulting in an interrupt request generation.

+  *       This bit is cleared by clearing the corresponding bit in the EXTI_PR3

+  *       register (by writing a 1 into the bit)

+  * @rmtoll SWIER3       SWIx          LL_EXTI_GenerateSWI_64_95

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_82

+  *         @arg @ref LL_EXTI_LINE_84

+  *         @arg @ref LL_EXTI_LINE_85

+  *         @arg @ref LL_EXTI_LINE_86

+  * @retval None

+  */

+__STATIC_INLINE void LL_EXTI_GenerateSWI_64_95(uint32_t ExtiLine)

+{

+  SET_BIT(EXTI->SWIER3, ExtiLine);

+}

+

+

+/**

+  * @}

+  */

+

+/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management

+  * @{

+  */

+

+/**

+  * @brief  Check if the ExtLine Flag is set or not for Lines in range 0 to 31

+  * @note This bit is set when the selected edge event arrives on the interrupt

+  *       line. This bit is cleared by writing a 1 to the bit.

+  * @rmtoll PR1          PIFx           LL_EXTI_IsActiveFlag_0_31

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_0

+  *         @arg @ref LL_EXTI_LINE_1

+  *         @arg @ref LL_EXTI_LINE_2

+  *         @arg @ref LL_EXTI_LINE_3

+  *         @arg @ref LL_EXTI_LINE_4

+  *         @arg @ref LL_EXTI_LINE_5

+  *         @arg @ref LL_EXTI_LINE_6

+  *         @arg @ref LL_EXTI_LINE_7

+  *         @arg @ref LL_EXTI_LINE_8

+  *         @arg @ref LL_EXTI_LINE_9

+  *         @arg @ref LL_EXTI_LINE_10

+  *         @arg @ref LL_EXTI_LINE_11

+  *         @arg @ref LL_EXTI_LINE_12

+  *         @arg @ref LL_EXTI_LINE_13

+  *         @arg @ref LL_EXTI_LINE_14

+  *         @arg @ref LL_EXTI_LINE_15

+  *         @arg @ref LL_EXTI_LINE_16

+  *         @arg @ref LL_EXTI_LINE_17

+  *         @arg @ref LL_EXTI_LINE_18

+  *         @arg @ref LL_EXTI_LINE_19

+  *         @arg @ref LL_EXTI_LINE_20

+  *         @arg @ref LL_EXTI_LINE_21

+  *         @arg @ref LL_EXTI_LINE_ALL_0_31

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)

+{

+  return ((READ_BIT(EXTI->PR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);

+}

+

+/**

+  * @brief  Check if the ExtLine Flag is set or not for  Lines in range 32 to 63

+  * @note This bit is set when the selected edge event arrives on the interrupt

+  *       line. This bit is cleared by writing a 1 to the bit.

+  * @rmtoll PR2          PIFx           LL_EXTI_IsActiveFlag_32_63

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_49

+  *         @arg @ref LL_EXTI_LINE_51

+  *         @arg @ref LL_EXTI_LINE_ALL_32_63

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine)

+{

+  return ((READ_BIT(EXTI->PR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);

+}

+

+/**

+  * @brief  Check if the ExtLine Flag is set or not for  Lines in range 64 to 95

+  * @note This bit is set when the selected edge event arrives on the interrupt

+  *       line. This bit is cleared by writing a 1 to the bit.

+  * @rmtoll PR3          PIFx           LL_EXTI_IsActiveFlag_64_95

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_82

+  *         @arg @ref LL_EXTI_LINE_84

+  *         @arg @ref LL_EXTI_LINE_85

+  *         @arg @ref LL_EXTI_LINE_86

+  *         @arg @ref LL_EXTI_LINE_ALL_64_95

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag_64_95(uint32_t ExtiLine)

+{

+  return ((READ_BIT(EXTI->PR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);

+}

+

+

+/**

+  * @brief  Read ExtLine Combination Flag for Lines in range 0 to 31

+  * @note This bit is set when the selected edge event arrives on the interrupt

+  *       line. This bit is cleared by writing a 1 to the bit.

+  * @rmtoll PR1          PIFx           LL_EXTI_ReadFlag_0_31

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_0

+  *         @arg @ref LL_EXTI_LINE_1

+  *         @arg @ref LL_EXTI_LINE_2

+  *         @arg @ref LL_EXTI_LINE_3

+  *         @arg @ref LL_EXTI_LINE_4

+  *         @arg @ref LL_EXTI_LINE_5

+  *         @arg @ref LL_EXTI_LINE_6

+  *         @arg @ref LL_EXTI_LINE_7

+  *         @arg @ref LL_EXTI_LINE_8

+  *         @arg @ref LL_EXTI_LINE_9

+  *         @arg @ref LL_EXTI_LINE_10

+  *         @arg @ref LL_EXTI_LINE_11

+  *         @arg @ref LL_EXTI_LINE_12

+  *         @arg @ref LL_EXTI_LINE_13

+  *         @arg @ref LL_EXTI_LINE_14

+  *         @arg @ref LL_EXTI_LINE_15

+  *         @arg @ref LL_EXTI_LINE_16

+  *         @arg @ref LL_EXTI_LINE_17

+  *         @arg @ref LL_EXTI_LINE_18

+  *         @arg @ref LL_EXTI_LINE_19

+  *         @arg @ref LL_EXTI_LINE_20

+  *         @arg @ref LL_EXTI_LINE_21

+  * @retval @note This bit is set when the selected edge event arrives on the interrupt

+  */

+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_0_31(uint32_t ExtiLine)

+{

+  return (uint32_t)(READ_BIT(EXTI->PR1, ExtiLine));

+}

+

+

+/**

+  * @brief  Read ExtLine Combination Flag for  Lines in range 32 to 63

+  * @note This bit is set when the selected edge event arrives on the interrupt

+  *       line. This bit is cleared by writing a 1 to the bit.

+  * @rmtoll PR2          PIFx           LL_EXTI_ReadFlag_32_63

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_49

+  *         @arg @ref LL_EXTI_LINE_51

+  * @retval @note This bit is set when the selected edge event arrives on the interrupt

+  */

+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_32_63(uint32_t ExtiLine)

+{

+  return (uint32_t)(READ_BIT(EXTI->PR2, ExtiLine));

+}

+

+

+/**

+  * @brief  Read ExtLine Combination Flag for  Lines in range 64 to 95

+  * @note This bit is set when the selected edge event arrives on the interrupt

+  *       line. This bit is cleared by writing a 1 to the bit.

+  * @rmtoll PR3          PIFx           LL_EXTI_ReadFlag_64_95

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_82

+  *         @arg @ref LL_EXTI_LINE_84

+  *         @arg @ref LL_EXTI_LINE_85

+  *         @arg @ref LL_EXTI_LINE_86

+  * @retval @note This bit is set when the selected edge event arrives on the interrupt

+  */

+__STATIC_INLINE uint32_t LL_EXTI_ReadFlag_64_95(uint32_t ExtiLine)

+{

+  return (uint32_t)(READ_BIT(EXTI->PR3, ExtiLine));

+}

+

+/**

+  * @brief  Clear ExtLine Flags for Lines in range 0 to 31

+  * @note This bit is set when the selected edge event arrives on the interrupt

+  *       line. This bit is cleared by writing a 1 to the bit.

+  * @rmtoll PR1          PIFx           LL_EXTI_ClearFlag_0_31

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_0

+  *         @arg @ref LL_EXTI_LINE_1

+  *         @arg @ref LL_EXTI_LINE_2

+  *         @arg @ref LL_EXTI_LINE_3

+  *         @arg @ref LL_EXTI_LINE_4

+  *         @arg @ref LL_EXTI_LINE_5

+  *         @arg @ref LL_EXTI_LINE_6

+  *         @arg @ref LL_EXTI_LINE_7

+  *         @arg @ref LL_EXTI_LINE_8

+  *         @arg @ref LL_EXTI_LINE_9

+  *         @arg @ref LL_EXTI_LINE_10

+  *         @arg @ref LL_EXTI_LINE_11

+  *         @arg @ref LL_EXTI_LINE_12

+  *         @arg @ref LL_EXTI_LINE_13

+  *         @arg @ref LL_EXTI_LINE_14

+  *         @arg @ref LL_EXTI_LINE_15

+  *         @arg @ref LL_EXTI_LINE_16

+  *         @arg @ref LL_EXTI_LINE_17

+  *         @arg @ref LL_EXTI_LINE_18

+  *         @arg @ref LL_EXTI_LINE_19

+  *         @arg @ref LL_EXTI_LINE_20

+  *         @arg @ref LL_EXTI_LINE_21

+  * @retval None

+  */

+__STATIC_INLINE void LL_EXTI_ClearFlag_0_31(uint32_t ExtiLine)

+{

+  WRITE_REG(EXTI->PR1, ExtiLine);

+}

+

+/**

+  * @brief  Clear ExtLine Flags for Lines in range 32 to 63

+  * @note This bit is set when the selected edge event arrives on the interrupt

+  *       line. This bit is cleared by writing a 1 to the bit.

+  * @rmtoll PR2          PIFx           LL_EXTI_ClearFlag_32_63

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_49

+  *         @arg @ref LL_EXTI_LINE_51

+  * @retval None

+  */

+__STATIC_INLINE void LL_EXTI_ClearFlag_32_63(uint32_t ExtiLine)

+{

+  WRITE_REG(EXTI->PR2, ExtiLine);

+}

+

+/**

+  * @brief  Clear ExtLine Flags for Lines in range 64 to 95

+  * @note This bit is set when the selected edge event arrives on the interrupt

+  *       line. This bit is cleared by writing a 1 to the bit.

+  * @rmtoll PR3          PIFx           LL_EXTI_ClearFlag_64_95

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_82

+  *         @arg @ref LL_EXTI_LINE_84

+  *         @arg @ref LL_EXTI_LINE_85

+  *         @arg @ref LL_EXTI_LINE_86

+  * @retval None

+  */

+__STATIC_INLINE void LL_EXTI_ClearFlag_64_95(uint32_t ExtiLine)

+{

+  WRITE_REG(EXTI->PR3, ExtiLine);

+}

+

+#if defined(DUAL_CORE)

+

+/**

+  * @brief  Check if the ExtLine Flag is set or not for Lines in range 0 to 31 for cpu2

+  * @note This bit is set when the selected edge event arrives on the interrupt

+  *       line. This bit is cleared by writing a 1 to the bit.

+  * @rmtoll C2PR1          PIFx           LL_C2_EXTI_IsActiveFlag_0_31

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_0

+  *         @arg @ref LL_EXTI_LINE_1

+  *         @arg @ref LL_EXTI_LINE_2

+  *         @arg @ref LL_EXTI_LINE_3

+  *         @arg @ref LL_EXTI_LINE_4

+  *         @arg @ref LL_EXTI_LINE_5

+  *         @arg @ref LL_EXTI_LINE_6

+  *         @arg @ref LL_EXTI_LINE_7

+  *         @arg @ref LL_EXTI_LINE_8

+  *         @arg @ref LL_EXTI_LINE_9

+  *         @arg @ref LL_EXTI_LINE_10

+  *         @arg @ref LL_EXTI_LINE_11

+  *         @arg @ref LL_EXTI_LINE_12

+  *         @arg @ref LL_EXTI_LINE_13

+  *         @arg @ref LL_EXTI_LINE_14

+  *         @arg @ref LL_EXTI_LINE_15

+  *         @arg @ref LL_EXTI_LINE_16

+  *         @arg @ref LL_EXTI_LINE_17

+  *         @arg @ref LL_EXTI_LINE_18

+  *         @arg @ref LL_EXTI_LINE_19

+  *         @arg @ref LL_EXTI_LINE_20

+  *         @arg @ref LL_EXTI_LINE_21

+  *         @arg @ref LL_EXTI_LINE_ALL_0_31

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C2_EXTI_IsActiveFlag_0_31(uint32_t ExtiLine)

+{

+  return ((READ_BIT(EXTI->C2PR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);

+}

+

+/**

+  * @brief  Check if the ExtLine Flag is set or not for  Lines in range 32 to 63 for cpu2

+  * @note This bit is set when the selected edge event arrives on the interrupt

+  *       line. This bit is cleared by writing a 1 to the bit.

+  * @rmtoll C2PR2          PIFx           LL_C2_EXTI_IsActiveFlag_32_63

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_49

+  *         @arg @ref LL_EXTI_LINE_51

+  *         @arg @ref LL_EXTI_LINE_ALL_32_63

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C2_EXTI_IsActiveFlag_32_63(uint32_t ExtiLine)

+{

+  return ((READ_BIT(EXTI->C2PR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);

+}

+

+/**

+  * @brief  Check if the ExtLine Flag is set or not for  Lines in range 64 to 95 for cpu2

+  * @note This bit is set when the selected edge event arrives on the interrupt

+  *       line. This bit is cleared by writing a 1 to the bit.

+  * @rmtoll C2PR3          PIFx           LL_C2_EXTI_IsActiveFlag_64_95

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_82

+  *         @arg @ref LL_EXTI_LINE_84

+  *         @arg @ref LL_EXTI_LINE_85

+  *         @arg @ref LL_EXTI_LINE_86

+  *         @arg @ref LL_EXTI_LINE_ALL_64_95

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C2_EXTI_IsActiveFlag_64_95(uint32_t ExtiLine)

+{

+  return ((READ_BIT(EXTI->C2PR3, ExtiLine) == (ExtiLine)) ? 1U : 0U);

+}

+

+/**

+  * @brief  Read ExtLine Combination Flag for Lines in range 0 to 31 for cpu2

+  * @note This bit is set when the selected edge event arrives on the interrupt

+  *       line. This bit is cleared by writing a 1 to the bit.

+  * @rmtoll C2PR1          PIFx           LL_C2_EXTI_ReadFlag_0_31

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_0

+  *         @arg @ref LL_EXTI_LINE_1

+  *         @arg @ref LL_EXTI_LINE_2

+  *         @arg @ref LL_EXTI_LINE_3

+  *         @arg @ref LL_EXTI_LINE_4

+  *         @arg @ref LL_EXTI_LINE_5

+  *         @arg @ref LL_EXTI_LINE_6

+  *         @arg @ref LL_EXTI_LINE_7

+  *         @arg @ref LL_EXTI_LINE_8

+  *         @arg @ref LL_EXTI_LINE_9

+  *         @arg @ref LL_EXTI_LINE_10

+  *         @arg @ref LL_EXTI_LINE_11

+  *         @arg @ref LL_EXTI_LINE_12

+  *         @arg @ref LL_EXTI_LINE_13

+  *         @arg @ref LL_EXTI_LINE_14

+  *         @arg @ref LL_EXTI_LINE_15

+  *         @arg @ref LL_EXTI_LINE_16

+  *         @arg @ref LL_EXTI_LINE_17

+  *         @arg @ref LL_EXTI_LINE_18

+  *         @arg @ref LL_EXTI_LINE_19

+  *         @arg @ref LL_EXTI_LINE_20

+  *         @arg @ref LL_EXTI_LINE_21

+  * @retval @note This bit is set when the selected edge event arrives on the interrupt

+  */

+__STATIC_INLINE uint32_t LL_C2_EXTI_ReadFlag_0_31(uint32_t ExtiLine)

+{

+  return (uint32_t)(READ_BIT(EXTI->C2PR1, ExtiLine));

+}

+

+/**

+  * @brief  Read ExtLine Combination Flag for  Lines in range 32 to 63 for cpu2

+  * @note This bit is set when the selected edge event arrives on the interrupt

+  *       line. This bit is cleared by writing a 1 to the bit.

+  * @rmtoll C2PR2          PIFx           LL_C2_EXTI_ReadFlag_32_63

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_49

+  *         @arg @ref LL_EXTI_LINE_51

+  * @retval @note This bit is set when the selected edge event arrives on the interrupt

+  */

+__STATIC_INLINE uint32_t LL_C2_EXTI_ReadFlag_32_63(uint32_t ExtiLine)

+{

+  return (uint32_t)(READ_BIT(EXTI->C2PR2, ExtiLine));

+}

+

+

+/**

+  * @brief  Read ExtLine Combination Flag for  Lines in range 64 to 95 for cpu2

+  * @note This bit is set when the selected edge event arrives on the interrupt

+  *       line. This bit is cleared by writing a 1 to the bit.

+  * @rmtoll C2PR3          PIFx           LL_C2_EXTI_ReadFlag_64_95

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_82

+  *         @arg @ref LL_EXTI_LINE_84

+  *         @arg @ref LL_EXTI_LINE_85

+  *         @arg @ref LL_EXTI_LINE_86

+  * @retval @note This bit is set when the selected edge event arrives on the interrupt

+  */

+__STATIC_INLINE uint32_t LL_C2_EXTI_ReadFlag_64_95(uint32_t ExtiLine)

+{

+  return (uint32_t)(READ_BIT(EXTI->C2PR3, ExtiLine));

+}

+/**

+  * @brief  Clear ExtLine Flags for Lines in range 0 to 31 for cpu2

+  * @note This bit is set when the selected edge event arrives on the interrupt

+  *       line. This bit is cleared by writing a 1 to the bit.

+  * @rmtoll C2PR1          PIFx           LL_C2_EXTI_ClearFlag_0_31

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_0

+  *         @arg @ref LL_EXTI_LINE_1

+  *         @arg @ref LL_EXTI_LINE_2

+  *         @arg @ref LL_EXTI_LINE_3

+  *         @arg @ref LL_EXTI_LINE_4

+  *         @arg @ref LL_EXTI_LINE_5

+  *         @arg @ref LL_EXTI_LINE_6

+  *         @arg @ref LL_EXTI_LINE_7

+  *         @arg @ref LL_EXTI_LINE_8

+  *         @arg @ref LL_EXTI_LINE_9

+  *         @arg @ref LL_EXTI_LINE_10

+  *         @arg @ref LL_EXTI_LINE_11

+  *         @arg @ref LL_EXTI_LINE_12

+  *         @arg @ref LL_EXTI_LINE_13

+  *         @arg @ref LL_EXTI_LINE_14

+  *         @arg @ref LL_EXTI_LINE_15

+  *         @arg @ref LL_EXTI_LINE_16

+  *         @arg @ref LL_EXTI_LINE_17

+  *         @arg @ref LL_EXTI_LINE_18

+  *         @arg @ref LL_EXTI_LINE_19

+  *         @arg @ref LL_EXTI_LINE_20

+  *         @arg @ref LL_EXTI_LINE_21

+  * @retval None

+  */

+__STATIC_INLINE void LL_C2_EXTI_ClearFlag_0_31(uint32_t ExtiLine)

+{

+  WRITE_REG(EXTI->C2PR1, ExtiLine);

+}

+

+/**

+  * @brief  Clear ExtLine Flags for Lines in range 32 to 63 for cpu2

+  * @note This bit is set when the selected edge event arrives on the interrupt

+  *       line. This bit is cleared by writing a 1 to the bit.

+  * @rmtoll C2PR2          PIFx           LL_C2_EXTI_ClearFlag_32_63

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_49

+  *         @arg @ref LL_EXTI_LINE_51

+  * @retval None

+  */

+__STATIC_INLINE void LL_C2_EXTI_ClearFlag_32_63(uint32_t ExtiLine)

+{

+  WRITE_REG(EXTI->C2PR2, ExtiLine);

+}

+

+/**

+  * @brief  Clear ExtLine Flags for Lines in range 64 to 95 for cpu2

+  * @note This bit is set when the selected edge event arrives on the interrupt

+  *       line. This bit is cleared by writing a 1 to the bit.

+  * @rmtoll C2PR3          PIFx           LL_C2_EXTI_ClearFlag_64_95

+  * @param  ExtiLine This parameter can be a combination of the following values:

+  *         @arg @ref LL_EXTI_LINE_82

+  *         @arg @ref LL_EXTI_LINE_84

+  *         @arg @ref LL_EXTI_LINE_85

+  *         @arg @ref LL_EXTI_LINE_86

+  * @retval None

+  */

+__STATIC_INLINE void LL_C2_EXTI_ClearFlag_64_95(uint32_t ExtiLine)

+{

+  WRITE_REG(EXTI->C2PR3, ExtiLine);

+}

+

+#endif /* DUAL_CORE */

+

+/**

+  * @brief  Enable ExtiLine D3 Pending Mask for Lines in range 0 to 31

+  * @rmtoll D3PMR1         MRx           LL_D3_EXTI_EnablePendMask_0_31

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_0

+  *         @arg @ref LL_EXTI_LINE_1

+  *         @arg @ref LL_EXTI_LINE_2

+  *         @arg @ref LL_EXTI_LINE_3

+  *         @arg @ref LL_EXTI_LINE_4

+  *         @arg @ref LL_EXTI_LINE_5

+  *         @arg @ref LL_EXTI_LINE_6

+  *         @arg @ref LL_EXTI_LINE_7

+  *         @arg @ref LL_EXTI_LINE_8

+  *         @arg @ref LL_EXTI_LINE_9

+  *         @arg @ref LL_EXTI_LINE_10

+  *         @arg @ref LL_EXTI_LINE_11

+  *         @arg @ref LL_EXTI_LINE_12

+  *         @arg @ref LL_EXTI_LINE_13

+  *         @arg @ref LL_EXTI_LINE_14

+  *         @arg @ref LL_EXTI_LINE_15

+  *         @arg @ref LL_EXTI_LINE_19

+  *         @arg @ref LL_EXTI_LINE_20

+  *         @arg @ref LL_EXTI_LINE_21

+  *         @arg @ref LL_EXTI_LINE_25

+  * @retval None

+  */

+__STATIC_INLINE void LL_D3_EXTI_EnablePendMask_0_31(uint32_t ExtiLine)

+{

+  SET_BIT(EXTI->D3PMR1, ExtiLine);

+}

+

+/**

+  * @brief  Enable ExtiLine D3 Pending Mask for Lines in range 32 to 63

+  * @rmtoll D3PMR2         MRx           LL_D3_EXTI_EnablePendMask_32_63

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_34

+  *         @arg @ref LL_EXTI_LINE_35

+  *         @arg @ref LL_EXTI_LINE_41

+  *         @arg @ref LL_EXTI_LINE_48

+  *         @arg @ref LL_EXTI_LINE_49

+  *         @arg @ref LL_EXTI_LINE_50

+  *         @arg @ref LL_EXTI_LINE_51

+  *         @arg @ref LL_EXTI_LINE_52

+  *         @arg @ref LL_EXTI_LINE_53

+  * @retval None

+  */

+__STATIC_INLINE void LL_D3_EXTI_EnablePendMask_32_63(uint32_t ExtiLine)

+{

+  SET_BIT(EXTI->D3PMR2, ExtiLine);

+}

+

+/**

+  * @brief  Disable ExtiLine D3 Pending Mask for Lines in range 0 to 31

+  * @rmtoll D3PMR1         MRx           LL_D3_EXTI_DisablePendMask_0_31

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_0

+  *         @arg @ref LL_EXTI_LINE_1

+  *         @arg @ref LL_EXTI_LINE_2

+  *         @arg @ref LL_EXTI_LINE_3

+  *         @arg @ref LL_EXTI_LINE_4

+  *         @arg @ref LL_EXTI_LINE_5

+  *         @arg @ref LL_EXTI_LINE_6

+  *         @arg @ref LL_EXTI_LINE_7

+  *         @arg @ref LL_EXTI_LINE_8

+  *         @arg @ref LL_EXTI_LINE_9

+  *         @arg @ref LL_EXTI_LINE_10

+  *         @arg @ref LL_EXTI_LINE_11

+  *         @arg @ref LL_EXTI_LINE_12

+  *         @arg @ref LL_EXTI_LINE_13

+  *         @arg @ref LL_EXTI_LINE_14

+  *         @arg @ref LL_EXTI_LINE_15

+  *         @arg @ref LL_EXTI_LINE_19

+  *         @arg @ref LL_EXTI_LINE_20

+  *         @arg @ref LL_EXTI_LINE_21

+  *         @arg @ref LL_EXTI_LINE_25

+  * @retval None

+  */

+__STATIC_INLINE void LL_D3_EXTI_DisablePendMask_0_31(uint32_t ExtiLine)

+{

+  CLEAR_BIT(EXTI->D3PMR1, ExtiLine);

+}

+

+/**

+  * @brief  Disable ExtiLine D3 Pending Mask for Lines in range 32 to 63

+  * @rmtoll D3PMR2         MRx           LL_D3_EXTI_DisablePendMask_32_63

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_34

+  *         @arg @ref LL_EXTI_LINE_35

+  *         @arg @ref LL_EXTI_LINE_41

+  *         @arg @ref LL_EXTI_LINE_48

+  *         @arg @ref LL_EXTI_LINE_49

+  *         @arg @ref LL_EXTI_LINE_50

+  *         @arg @ref LL_EXTI_LINE_51

+  *         @arg @ref LL_EXTI_LINE_52

+  *         @arg @ref LL_EXTI_LINE_53

+  * @retval None

+  */

+__STATIC_INLINE void LL_D3_EXTI_DisablePendMask_32_63(uint32_t ExtiLine)

+{

+  CLEAR_BIT(EXTI->D3PMR2, ExtiLine);

+}

+

+/**

+  * @brief  Indicate if ExtiLine D3 Pending Mask is enabled for Lines in range 0 to 31

+  * @rmtoll D3PMR1         MRx           LL_D3_EXTI_IsEnabledPendMask_0_31

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_0

+  *         @arg @ref LL_EXTI_LINE_1

+  *         @arg @ref LL_EXTI_LINE_2

+  *         @arg @ref LL_EXTI_LINE_3

+  *         @arg @ref LL_EXTI_LINE_4

+  *         @arg @ref LL_EXTI_LINE_5

+  *         @arg @ref LL_EXTI_LINE_6

+  *         @arg @ref LL_EXTI_LINE_7

+  *         @arg @ref LL_EXTI_LINE_8

+  *         @arg @ref LL_EXTI_LINE_9

+  *         @arg @ref LL_EXTI_LINE_10

+  *         @arg @ref LL_EXTI_LINE_11

+  *         @arg @ref LL_EXTI_LINE_12

+  *         @arg @ref LL_EXTI_LINE_13

+  *         @arg @ref LL_EXTI_LINE_14

+  *         @arg @ref LL_EXTI_LINE_15

+  *         @arg @ref LL_EXTI_LINE_19

+  *         @arg @ref LL_EXTI_LINE_20

+  *         @arg @ref LL_EXTI_LINE_21

+  *         @arg @ref LL_EXTI_LINE_25

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_D3_EXTI_IsEnabledPendMask_0_31(uint32_t ExtiLine)

+{

+  return ((READ_BIT(EXTI->D3PMR1, ExtiLine) == (ExtiLine)) ? 1U : 0U);

+}

+

+/**

+  * @brief  Indicate if ExtiLine D3 Pending Mask is enabled for Lines in range 32 to 63

+  * @rmtoll D3PMR2         MRx           LL_D3_EXTI_IsEnabledPendMask_32_63

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_34

+  *         @arg @ref LL_EXTI_LINE_35

+  *         @arg @ref LL_EXTI_LINE_41

+  *         @arg @ref LL_EXTI_LINE_48

+  *         @arg @ref LL_EXTI_LINE_49

+  *         @arg @ref LL_EXTI_LINE_50

+  *         @arg @ref LL_EXTI_LINE_51

+  *         @arg @ref LL_EXTI_LINE_52

+  *         @arg @ref LL_EXTI_LINE_53

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_D3_EXTI_IsEnabledPendMask_32_63(uint32_t ExtiLine)

+{

+  return ((READ_BIT(EXTI->D3PMR2, ExtiLine) == (ExtiLine)) ? 1U : 0U);

+}

+

+/**

+  * @brief  Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 0 to 15

+  * @rmtoll D3PCR1L          PCSx           LL_D3_EXTI_SetPendClearSel_0_15

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_0

+  *         @arg @ref LL_EXTI_LINE_1

+  *         @arg @ref LL_EXTI_LINE_2

+  *         @arg @ref LL_EXTI_LINE_3

+  *         @arg @ref LL_EXTI_LINE_4

+  *         @arg @ref LL_EXTI_LINE_5

+  *         @arg @ref LL_EXTI_LINE_6

+  *         @arg @ref LL_EXTI_LINE_7

+  *         @arg @ref LL_EXTI_LINE_8

+  *         @arg @ref LL_EXTI_LINE_9

+  *         @arg @ref LL_EXTI_LINE_10

+  *         @arg @ref LL_EXTI_LINE_11

+  *         @arg @ref LL_EXTI_LINE_12

+  *         @arg @ref LL_EXTI_LINE_13

+  *         @arg @ref LL_EXTI_LINE_14

+  *         @arg @ref LL_EXTI_LINE_15

+  * @param  ClrSrc This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5

+  * @retval None

+  */

+__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_0_15(uint32_t ExtiLine, uint32_t ClrSrc)

+{

+  MODIFY_REG(EXTI->D3PCR1L, ((ExtiLine * ExtiLine) * 3UL), ((ExtiLine * ExtiLine) * ClrSrc));

+}

+

+/**

+  * @brief  Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 16 to 31

+  * @rmtoll D3PCR1H          PCSx           LL_D3_EXTI_SetPendClearSel_16_31

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_19

+  *         @arg @ref LL_EXTI_LINE_20

+  *         @arg @ref LL_EXTI_LINE_21

+  *         @arg @ref LL_EXTI_LINE_25

+  * @param  ClrSrc This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5

+  * @retval None

+  */

+__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_16_31(uint32_t ExtiLine, uint32_t ClrSrc)

+{

+  MODIFY_REG(EXTI->D3PCR1H, (((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)) * 3UL), (((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)) * ClrSrc));

+}

+

+

+/**

+  * @brief  Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 32 to 47

+  * @rmtoll D3PCR2L          PCSx           LL_D3_EXTI_SetPendClearSel_32_47

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_34

+  *         @arg @ref LL_EXTI_LINE_35

+  *         @arg @ref LL_EXTI_LINE_41

+  * @param  ClrSrc This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5

+  * @retval None

+  */

+__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_32_47(uint32_t ExtiLine, uint32_t ClrSrc)

+{

+  MODIFY_REG(EXTI->D3PCR2L, ((ExtiLine * ExtiLine) * 3UL), ((ExtiLine * ExtiLine) * ClrSrc));

+}

+

+/**

+  * @brief  Set ExtLine D3 Domain Pend Clear Source selection for Lines in range 48 to 63

+  * @rmtoll D3PCR2H          PCSx           LL_D3_EXTI_SetPendClearSel_48_63

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_48

+  *         @arg @ref LL_EXTI_LINE_49

+  *         @arg @ref LL_EXTI_LINE_50

+  *         @arg @ref LL_EXTI_LINE_51

+  *         @arg @ref LL_EXTI_LINE_52

+  *         @arg @ref LL_EXTI_LINE_53

+  * @param  ClrSrc This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5

+  * @retval None

+  */

+__STATIC_INLINE void LL_D3_EXTI_SetPendClearSel_48_63(uint32_t ExtiLine, uint32_t ClrSrc)

+{

+  MODIFY_REG(EXTI->D3PCR2H, (((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)) * 3UL), (((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)) * ClrSrc));

+}

+

+/**

+  * @brief  Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 0 to 15

+  * @rmtoll D3PCR1L          PCSx           LL_D3_EXTI_GetPendClearSel_0_15

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_0

+  *         @arg @ref LL_EXTI_LINE_1

+  *         @arg @ref LL_EXTI_LINE_2

+  *         @arg @ref LL_EXTI_LINE_3

+  *         @arg @ref LL_EXTI_LINE_4

+  *         @arg @ref LL_EXTI_LINE_5

+  *         @arg @ref LL_EXTI_LINE_6

+  *         @arg @ref LL_EXTI_LINE_7

+  *         @arg @ref LL_EXTI_LINE_8

+  *         @arg @ref LL_EXTI_LINE_9

+  *         @arg @ref LL_EXTI_LINE_10

+  *         @arg @ref LL_EXTI_LINE_11

+  *         @arg @ref LL_EXTI_LINE_12

+  *         @arg @ref LL_EXTI_LINE_13

+  *         @arg @ref LL_EXTI_LINE_14

+  *         @arg @ref LL_EXTI_LINE_15

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5

+  */

+__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_0_15(uint32_t ExtiLine)

+{

+  return (uint32_t)(READ_BIT(EXTI->D3PCR1L, ((ExtiLine * ExtiLine) * 3UL)) / (ExtiLine * ExtiLine));

+}

+

+/**

+  * @brief  Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 16 to 31

+  * @rmtoll D3PCR1H          PCSx           LL_D3_EXTI_GetPendClearSel_16_31

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_19

+  *         @arg @ref LL_EXTI_LINE_20

+  *         @arg @ref LL_EXTI_LINE_21

+  *         @arg @ref LL_EXTI_LINE_25

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5

+  */

+__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_16_31(uint32_t ExtiLine)

+{

+  return (uint32_t)(READ_BIT(EXTI->D3PCR1H, (((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)) * 3UL)) / ((ExtiLine >> EXTI_IMR1_IM16_Pos) * (ExtiLine >> EXTI_IMR1_IM16_Pos)));

+}

+

+/**

+  * @brief  Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 32 to 47

+  * @rmtoll D3PCR2L          PCSx           LL_D3_EXTI_GetPendClearSel_32_47

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_34

+  *         @arg @ref LL_EXTI_LINE_35

+  *         @arg @ref LL_EXTI_LINE_41

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5

+  */

+__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_32_47(uint32_t ExtiLine)

+{

+  return (uint32_t)(READ_BIT(EXTI->D3PCR2L, ((ExtiLine * ExtiLine) * 3UL)) / (ExtiLine * ExtiLine));

+}

+

+/**

+  * @brief  Get ExtLine D3 Domain Pend Clear Source selection for Lines in range 48 to 63

+  * @rmtoll D3PCR2H          PCSx           LL_D3_EXTI_GetPendClearSel_48_63

+  * @param  ExtiLine This parameter can be one of the following values:

+  *         @arg @ref LL_EXTI_LINE_48

+  *         @arg @ref LL_EXTI_LINE_49

+  *         @arg @ref LL_EXTI_LINE_50

+  *         @arg @ref LL_EXTI_LINE_51

+  *         @arg @ref LL_EXTI_LINE_52

+  *         @arg @ref LL_EXTI_LINE_53

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH6

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_DMACH7

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM4

+  *         @arg @ref LL_EXTI_D3_PEND_CLR_LPTIM5

+  */

+__STATIC_INLINE uint32_t LL_D3_EXTI_GetPendClearSel_48_63(uint32_t ExtiLine)

+{

+  return (uint32_t)(READ_BIT(EXTI->D3PCR2H, (((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)) * 3UL)) / ((ExtiLine >> EXTI_IMR2_IM48_Pos) * (ExtiLine >> EXTI_IMR2_IM48_Pos)));

+}

+

+

+

+/**

+  * @}

+  */

+

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions

+  * @{,

+  */

+

+ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct);

+ErrorStatus LL_EXTI_DeInit(void);

+void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct);

+

+

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* EXTI */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* __STM32H7xx_LL_EXTI_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_fmc.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_fmc.h
new file mode 100644
index 0000000000..a45860f1dd
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_fmc.h
@@ -0,0 +1,1148 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_fmc.h

+  * @author  MCD Application Team

+  * @brief   Header file of FMC HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                       opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_LL_FMC_H

+#define STM32H7xx_LL_FMC_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup FMC_LL

+  * @{

+  */

+

+/** @addtogroup FMC_LL_Private_Macros

+  * @{

+  */

+

+#define IS_FMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FMC_NORSRAM_BANK1) || \

+                                       ((__BANK__) == FMC_NORSRAM_BANK2) || \

+                                       ((__BANK__) == FMC_NORSRAM_BANK3) || \

+                                       ((__BANK__) == FMC_NORSRAM_BANK4))

+#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \

+                             ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))

+#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \

+                                   ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \

+                                   ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))

+#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8)  || \

+                                                ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \

+                                                ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))

+#define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \

+                                   ((__SIZE__) == FMC_PAGE_SIZE_128) || \

+                                   ((__SIZE__) == FMC_PAGE_SIZE_256) || \

+                                   ((__SIZE__) == FMC_PAGE_SIZE_512) || \

+                                   ((__SIZE__) == FMC_PAGE_SIZE_1024))

+#define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \

+                                     ((__FIFO__) == FMC_WRITE_FIFO_ENABLE))

+#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \

+                                      ((__MODE__) == FMC_ACCESS_MODE_B) || \

+                                      ((__MODE__) == FMC_ACCESS_MODE_C) || \

+                                      ((__MODE__) == FMC_ACCESS_MODE_D))

+#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \

+                                     ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))

+#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \

+                                            ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))

+#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \

+                                               ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))

+#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \

+                                               ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))

+#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \

+                                         ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))

+#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \

+                                        ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))

+#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \

+                                    ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))

+#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))

+#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \

+                                       ((__BURST__) == FMC_WRITE_BURST_ENABLE))

+#define IS_FMC_CONTINOUS_CLOCK(__CCLOCK__) (((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \

+                                            ((__CCLOCK__) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))

+#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)

+#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))

+#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))

+#define IS_FMC_DATAHOLD_DURATION(__DATAHOLD__) ((__DATAHOLD__) <= 3U)

+#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)

+#define IS_FMC_CLK_DIV(__DIV__) (((__DIV__) > 1U) && ((__DIV__) <= 16U))

+#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)

+#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)

+

+

+#define IS_FMC_NAND_BANK(__BANK__) ((__BANK__) == FMC_NAND_BANK3)

+#define IS_FMC_WAIT_FEATURE(__FEATURE__) (((__FEATURE__) == FMC_NAND_WAIT_FEATURE_DISABLE) || \

+                                          ((__FEATURE__) == FMC_NAND_WAIT_FEATURE_ENABLE))

+#define IS_FMC_NAND_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_8) || \

+                                             ((__WIDTH__) == FMC_NAND_MEM_BUS_WIDTH_16))

+#define IS_FMC_ECC_STATE(__STATE__) (((__STATE__) == FMC_NAND_ECC_DISABLE) || \

+                                     ((__STATE__) == FMC_NAND_ECC_ENABLE))

+

+#define IS_FMC_ECCPAGE_SIZE(__SIZE__) (((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_256BYTE)  || \

+                                       ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_512BYTE)  || \

+                                       ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \

+                                       ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \

+                                       ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \

+                                       ((__SIZE__) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))

+#define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255U)

+#define IS_FMC_TAR_TIME(__TIME__) ((__TIME__) <= 255U)

+#define IS_FMC_SETUP_TIME(__TIME__) ((__TIME__) <= 254U)

+#define IS_FMC_WAIT_TIME(__TIME__) ((__TIME__) <= 254U)

+#define IS_FMC_HOLD_TIME(__TIME__) ((__TIME__) <= 254U)

+#define IS_FMC_HIZ_TIME(__TIME__) ((__TIME__) <= 254U)

+#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)

+

+

+#define IS_FMC_SDMEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_8)  || \

+                                      ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \

+                                      ((__WIDTH__) == FMC_SDRAM_MEM_BUS_WIDTH_32))

+#define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \

+                                            ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))

+#define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE)  || \

+                                           ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \

+                                           ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3))

+#define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \

+                                       ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE))

+#define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \

+                                          ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \

+                                          ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2))

+#define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE)      || \

+                                          ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE)       || \

+                                          ((__COMMAND__) == FMC_SDRAM_CMD_PALL)             || \

+                                          ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \

+                                          ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE)        || \

+                                          ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \

+                                          ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE))

+#define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \

+                                           ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \

+                                           ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2))

+#define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))

+#define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))

+#define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U))

+#define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))

+#define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 16U))

+#define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))

+#define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0U) && ((__DELAY__) <= 16U))

+#define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0U) && ((__NUMBER__) <= 15U))

+#define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191U)

+#define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191U)

+#define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE)

+#define IS_FMC_SDRAM_BANK(__BANK__) (((__BANK__) == FMC_SDRAM_BANK1) || \

+                                 ((__BANK__) == FMC_SDRAM_BANK2))

+#define IS_FMC_COLUMNBITS_NUMBER(__COLUMN__) (((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_8)  || \

+                                          ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_9)  || \

+                                          ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \

+                                          ((__COLUMN__) == FMC_SDRAM_COLUMN_BITS_NUM_11))

+#define IS_FMC_ROWBITS_NUMBER(__ROW__) (((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_11) || \

+                                    ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_12) || \

+                                    ((__ROW__) == FMC_SDRAM_ROW_BITS_NUM_13))

+#define IS_FMC_INTERNALBANK_NUMBER(__NUMBER__) (((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \

+                                            ((__NUMBER__) == FMC_SDRAM_INTERN_BANKS_NUM_4))

+#define IS_FMC_CAS_LATENCY(__LATENCY__) (((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_1) || \

+                                     ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_2) || \

+                                     ((__LATENCY__) == FMC_SDRAM_CAS_LATENCY_3))

+

+

+/**

+  * @}

+  */

+

+/* Exported typedef ----------------------------------------------------------*/

+

+/** @defgroup FMC_LL_Exported_typedef FMC Low Layer Exported Types

+  * @{

+  */

+

+#define FMC_NORSRAM_TypeDef            FMC_Bank1_TypeDef

+#define FMC_NORSRAM_EXTENDED_TypeDef   FMC_Bank1E_TypeDef

+#define FMC_NAND_TypeDef               FMC_Bank3_TypeDef

+#define FMC_SDRAM_TypeDef              FMC_Bank5_6_TypeDef

+

+#define FMC_NORSRAM_DEVICE             FMC_Bank1_R

+#define FMC_NORSRAM_EXTENDED_DEVICE    FMC_Bank1E_R

+#define FMC_NAND_DEVICE                FMC_Bank3_R

+#define FMC_SDRAM_DEVICE               FMC_Bank5_6_R

+

+/**

+  * @brief  FMC NORSRAM Configuration Structure definition

+  */

+typedef struct

+{

+  uint32_t NSBank;                       /*!< Specifies the NORSRAM memory device that will be used.

+                                              This parameter can be a value of @ref FMC_NORSRAM_Bank                     */

+

+  uint32_t DataAddressMux;               /*!< Specifies whether the address and data values are

+                                              multiplexed on the data bus or not.

+                                              This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing    */

+

+  uint32_t MemoryType;                   /*!< Specifies the type of external memory attached to

+                                              the corresponding memory device.

+                                              This parameter can be a value of @ref FMC_Memory_Type                      */

+

+  uint32_t MemoryDataWidth;              /*!< Specifies the external memory device width.

+                                              This parameter can be a value of @ref FMC_NORSRAM_Data_Width               */

+

+  uint32_t BurstAccessMode;              /*!< Enables or disables the burst access mode for Flash memory,

+                                              valid only with synchronous burst Flash memories.

+                                              This parameter can be a value of @ref FMC_Burst_Access_Mode                */

+

+  uint32_t WaitSignalPolarity;           /*!< Specifies the wait signal polarity, valid only when accessing

+                                              the Flash memory in burst mode.

+                                              This parameter can be a value of @ref FMC_Wait_Signal_Polarity             */

+

+  uint32_t WaitSignalActive;             /*!< Specifies if the wait signal is asserted by the memory one

+                                              clock cycle before the wait state or during the wait state,

+                                              valid only when accessing memories in burst mode.

+                                              This parameter can be a value of @ref FMC_Wait_Timing                      */

+

+  uint32_t WriteOperation;               /*!< Enables or disables the write operation in the selected device by the FMC.

+                                              This parameter can be a value of @ref FMC_Write_Operation                  */

+

+  uint32_t WaitSignal;                   /*!< Enables or disables the wait state insertion via wait

+                                              signal, valid for Flash memory access in burst mode.

+                                              This parameter can be a value of @ref FMC_Wait_Signal                      */

+

+  uint32_t ExtendedMode;                 /*!< Enables or disables the extended mode.

+                                              This parameter can be a value of @ref FMC_Extended_Mode                    */

+

+  uint32_t AsynchronousWait;             /*!< Enables or disables wait signal during asynchronous transfers,

+                                              valid only with asynchronous Flash memories.

+                                              This parameter can be a value of @ref FMC_AsynchronousWait                 */

+

+  uint32_t WriteBurst;                   /*!< Enables or disables the write burst operation.

+                                              This parameter can be a value of @ref FMC_Write_Burst                      */

+

+  uint32_t ContinuousClock;              /*!< Enables or disables the FMC clock output to external memory devices.

+                                              This parameter is only enabled through the FMC_BCR1 register, and don't care

+                                              through FMC_BCR2..4 registers.

+                                              This parameter can be a value of @ref FMC_Continous_Clock                  */

+

+  uint32_t WriteFifo;                    /*!< Enables or disables the write FIFO used by the FMC controller.

+                                              This parameter is only enabled through the FMC_BCR1 register, and don't care

+                                              through FMC_BCR2..4 registers.

+                                              This parameter can be a value of @ref FMC_Write_FIFO                       */

+

+  uint32_t PageSize;                     /*!< Specifies the memory page size.

+                                              This parameter can be a value of @ref FMC_Page_Size                        */

+}FMC_NORSRAM_InitTypeDef;

+

+/**

+  * @brief  FMC NORSRAM Timing parameters structure definition

+  */

+typedef struct

+{

+  uint32_t AddressSetupTime;             /*!< Defines the number of HCLK cycles to configure

+                                              the duration of the address setup time.

+                                              This parameter can be a value between Min_Data = 0 and Max_Data = 15.

+                                              @note This parameter is not used with synchronous NOR Flash memories.      */

+

+  uint32_t AddressHoldTime;              /*!< Defines the number of HCLK cycles to configure

+                                              the duration of the address hold time.

+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 15.

+                                              @note This parameter is not used with synchronous NOR Flash memories.      */

+

+  uint32_t DataSetupTime;                /*!< Defines the number of HCLK cycles to configure

+                                              the duration of the data setup time.

+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 255.

+                                              @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed

+                                              NOR Flash memories.                                                        */

+

+  uint32_t BusTurnAroundDuration;        /*!< Defines the number of HCLK cycles to configure

+                                              the duration of the bus turnaround.

+                                              This parameter can be a value between Min_Data = 0 and Max_Data = 15.

+                                              @note This parameter is only used for multiplexed NOR Flash memories.      */

+

+  uint32_t CLKDivision;                  /*!< Defines the period of CLK clock output signal, expressed in number of

+                                              HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.

+                                              @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM

+                                              accesses.                                                                  */

+

+  uint32_t DataLatency;                  /*!< Defines the number of memory clock cycles to issue

+                                              to the memory before getting the first data.

+                                              The parameter value depends on the memory type as shown below:

+                                              - It must be set to 0 in case of a CRAM

+                                              - It is don't care in asynchronous NOR, SRAM or ROM accesses

+                                              - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories

+                                                with synchronous burst mode enable                                       */

+

+  uint32_t AccessMode;                   /*!< Specifies the asynchronous access mode.

+                                              This parameter can be a value of @ref FMC_Access_Mode                      */

+}FMC_NORSRAM_TimingTypeDef;

+

+/**

+  * @brief  FMC NAND Configuration Structure definition

+  */

+typedef struct

+{

+  uint32_t NandBank;               /*!< Specifies the NAND memory device that will be used.

+                                        This parameter can be a value of @ref FMC_NAND_Bank                    */

+

+  uint32_t Waitfeature;            /*!< Enables or disables the Wait feature for the NAND Memory device.

+                                        This parameter can be any value of @ref FMC_Wait_feature               */

+

+  uint32_t MemoryDataWidth;        /*!< Specifies the external memory device width.

+                                        This parameter can be any value of @ref FMC_NAND_Data_Width            */

+

+  uint32_t EccComputation;         /*!< Enables or disables the ECC computation.

+                                        This parameter can be any value of @ref FMC_ECC                        */

+

+  uint32_t ECCPageSize;            /*!< Defines the page size for the extended ECC.

+                                        This parameter can be any value of @ref FMC_ECC_Page_Size              */

+

+  uint32_t TCLRSetupTime;          /*!< Defines the number of HCLK cycles to configure the

+                                        delay between CLE low and RE low.

+                                        This parameter can be a value between Min_Data = 0 and Max_Data = 255  */

+

+  uint32_t TARSetupTime;           /*!< Defines the number of HCLK cycles to configure the

+                                        delay between ALE low and RE low.

+                                        This parameter can be a number between Min_Data = 0 and Max_Data = 255 */

+}FMC_NAND_InitTypeDef;

+

+/**

+  * @brief  FMC NAND Timing parameters structure definition

+  */

+typedef struct

+{

+  uint32_t SetupTime;            /*!< Defines the number of HCLK cycles to setup address before

+                                      the command assertion for NAND-Flash read or write access

+                                      to common/Attribute or I/O memory space (depending on

+                                      the memory space timing to be configured).

+                                      This parameter can be a value between Min_Data = 0 and Max_Data = 254    */

+

+  uint32_t WaitSetupTime;        /*!< Defines the minimum number of HCLK cycles to assert the

+                                      command for NAND-Flash read or write access to

+                                      common/Attribute or I/O memory space (depending on the

+                                      memory space timing to be configured).

+                                      This parameter can be a number between Min_Data = 0 and Max_Data = 254   */

+

+  uint32_t HoldSetupTime;        /*!< Defines the number of HCLK clock cycles to hold address

+                                      (and data for write access) after the command de-assertion

+                                      for NAND-Flash read or write access to common/Attribute

+                                      or I/O memory space (depending on the memory space timing

+                                      to be configured).

+                                      This parameter can be a number between Min_Data = 0 and Max_Data = 254   */

+

+  uint32_t HiZSetupTime;         /*!< Defines the number of HCLK clock cycles during which the

+                                      data bus is kept in HiZ after the start of a NAND-Flash

+                                      write access to common/Attribute or I/O memory space (depending

+                                      on the memory space timing to be configured).

+                                      This parameter can be a number between Min_Data = 0 and Max_Data = 254   */

+}FMC_NAND_PCC_TimingTypeDef;

+

+

+/**

+  * @brief  FMC SDRAM Configuration Structure definition

+  */

+typedef struct

+{

+  uint32_t SDBank;                      /*!< Specifies the SDRAM memory device that will be used.

+                                             This parameter can be a value of @ref FMC_SDRAM_Bank                */

+

+  uint32_t ColumnBitsNumber;            /*!< Defines the number of bits of column address.

+                                             This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */

+

+  uint32_t RowBitsNumber;               /*!< Defines the number of bits of column address.

+                                             This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number.    */

+

+  uint32_t MemoryDataWidth;             /*!< Defines the memory device width.

+                                             This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width.   */

+

+  uint32_t InternalBankNumber;          /*!< Defines the number of the device's internal banks.

+                                             This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number.      */

+

+  uint32_t CASLatency;                  /*!< Defines the SDRAM CAS latency in number of memory clock cycles.

+                                             This parameter can be a value of @ref FMC_SDRAM_CAS_Latency.        */

+

+  uint32_t WriteProtection;             /*!< Enables the SDRAM device to be accessed in write mode.

+                                             This parameter can be a value of @ref FMC_SDRAM_Write_Protection.   */

+

+  uint32_t SDClockPeriod;               /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow

+                                             to disable the clock before changing frequency.

+                                             This parameter can be a value of @ref FMC_SDRAM_Clock_Period.       */

+

+  uint32_t ReadBurst;                   /*!< This bit enable the SDRAM controller to anticipate the next read

+                                             commands during the CAS latency and stores data in the Read FIFO.

+                                             This parameter can be a value of @ref FMC_SDRAM_Read_Burst.         */

+

+  uint32_t ReadPipeDelay;               /*!< Define the delay in system clock cycles on read data path.

+                                             This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay.    */

+}FMC_SDRAM_InitTypeDef;

+

+/**

+  * @brief FMC SDRAM Timing parameters structure definition

+  */

+typedef struct

+{

+  uint32_t LoadToActiveDelay;            /*!< Defines the delay between a Load Mode Register command and

+                                              an active or Refresh command in number of memory clock cycles.

+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */

+

+  uint32_t ExitSelfRefreshDelay;         /*!< Defines the delay from releasing the self refresh command to

+                                              issuing the Activate command in number of memory clock cycles.

+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */

+

+  uint32_t SelfRefreshTime;              /*!< Defines the minimum Self Refresh period in number of memory clock

+                                              cycles.

+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */

+

+  uint32_t RowCycleDelay;                /*!< Defines the delay between the Refresh command and the Activate command

+                                              and the delay between two consecutive Refresh commands in number of

+                                              memory clock cycles.

+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */

+

+  uint32_t WriteRecoveryTime;            /*!< Defines the Write recovery Time in number of memory clock cycles.

+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */

+

+  uint32_t RPDelay;                      /*!< Defines the delay between a Precharge Command and an other command

+                                              in number of memory clock cycles.

+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */

+

+  uint32_t RCDDelay;                     /*!< Defines the delay between the Activate Command and a Read/Write

+                                              command in number of memory clock cycles.

+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 16  */

+}FMC_SDRAM_TimingTypeDef;

+

+/**

+  * @brief SDRAM command parameters structure definition

+  */

+typedef struct

+{

+  uint32_t CommandMode;                  /*!< Defines the command issued to the SDRAM device.

+                                              This parameter can be a value of @ref FMC_SDRAM_Command_Mode.          */

+

+  uint32_t CommandTarget;                /*!< Defines which device (1 or 2) the command will be issued to.

+                                              This parameter can be a value of @ref FMC_SDRAM_Command_Target.        */

+

+  uint32_t AutoRefreshNumber;            /*!< Defines the number of consecutive auto refresh command issued

+                                              in auto refresh mode.

+                                              This parameter can be a value between Min_Data = 1 and Max_Data = 15   */

+

+  uint32_t ModeRegisterDefinition;       /*!< Defines the SDRAM Mode register content                                */

+}FMC_SDRAM_CommandTypeDef;

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants

+  * @{

+  */

+

+/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller

+  * @{

+  */

+

+/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank

+  * @{

+  */

+#define FMC_NORSRAM_BANK1                       ((uint32_t)0x00000000)

+#define FMC_NORSRAM_BANK2                       ((uint32_t)0x00000002)

+#define FMC_NORSRAM_BANK3                       ((uint32_t)0x00000004)

+#define FMC_NORSRAM_BANK4                       ((uint32_t)0x00000006)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing

+  * @{

+  */

+#define FMC_DATA_ADDRESS_MUX_DISABLE            ((uint32_t)0x00000000)

+#define FMC_DATA_ADDRESS_MUX_ENABLE             ((uint32_t)0x00000002)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_Memory_Type FMC Memory Type

+  * @{

+  */

+#define FMC_MEMORY_TYPE_SRAM                    ((uint32_t)0x00000000)

+#define FMC_MEMORY_TYPE_PSRAM                   ((uint32_t)0x00000004)

+#define FMC_MEMORY_TYPE_NOR                     ((uint32_t)0x00000008)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width

+  * @{

+  */

+#define FMC_NORSRAM_MEM_BUS_WIDTH_8             ((uint32_t)0x00000000)

+#define FMC_NORSRAM_MEM_BUS_WIDTH_16            ((uint32_t)0x00000010)

+#define FMC_NORSRAM_MEM_BUS_WIDTH_32            ((uint32_t)0x00000020)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access

+  * @{

+  */

+#define FMC_NORSRAM_FLASH_ACCESS_ENABLE         ((uint32_t)0x00000040)

+#define FMC_NORSRAM_FLASH_ACCESS_DISABLE        ((uint32_t)0x00000000)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode

+  * @{

+  */

+#define FMC_BURST_ACCESS_MODE_DISABLE           ((uint32_t)0x00000000)

+#define FMC_BURST_ACCESS_MODE_ENABLE            ((uint32_t)0x00000100)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity

+  * @{

+  */

+#define FMC_WAIT_SIGNAL_POLARITY_LOW            ((uint32_t)0x00000000)

+#define FMC_WAIT_SIGNAL_POLARITY_HIGH           ((uint32_t)0x00000200)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_Wait_Timing FMC Wait Timing

+  * @{

+  */

+#define FMC_WAIT_TIMING_BEFORE_WS               ((uint32_t)0x00000000)

+#define FMC_WAIT_TIMING_DURING_WS               ((uint32_t)0x00000800)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_Write_Operation FMC Write Operation

+  * @{

+  */

+#define FMC_WRITE_OPERATION_DISABLE             ((uint32_t)0x00000000)

+#define FMC_WRITE_OPERATION_ENABLE              ((uint32_t)0x00001000)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_Wait_Signal FMC Wait Signal

+  * @{

+  */

+#define FMC_WAIT_SIGNAL_DISABLE                 ((uint32_t)0x00000000)

+#define FMC_WAIT_SIGNAL_ENABLE                  ((uint32_t)0x00002000)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_Extended_Mode FMC Extended Mode

+  * @{

+  */

+#define FMC_EXTENDED_MODE_DISABLE               ((uint32_t)0x00000000)

+#define FMC_EXTENDED_MODE_ENABLE                ((uint32_t)0x00004000)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait

+  * @{

+  */

+#define FMC_ASYNCHRONOUS_WAIT_DISABLE           ((uint32_t)0x00000000)

+#define FMC_ASYNCHRONOUS_WAIT_ENABLE            ((uint32_t)0x00008000)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_Page_Size FMC Page Size

+  * @{

+  */

+#define FMC_PAGE_SIZE_NONE                      ((uint32_t)0x00000000)

+#define FMC_PAGE_SIZE_128                       ((uint32_t)FMC_BCRx_CPSIZE_0)

+#define FMC_PAGE_SIZE_256                       ((uint32_t)FMC_BCRx_CPSIZE_1)

+#define FMC_PAGE_SIZE_512                       ((uint32_t)(FMC_BCRx_CPSIZE_0 | FMC_BCRx_CPSIZE_1))

+#define FMC_PAGE_SIZE_1024                      ((uint32_t)FMC_BCRx_CPSIZE_2)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_Write_Burst FMC Write Burst

+  * @{

+  */

+#define FMC_WRITE_BURST_DISABLE                 ((uint32_t)0x00000000)

+#define FMC_WRITE_BURST_ENABLE                  ((uint32_t)0x00080000)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_Continous_Clock FMC Continuous Clock

+  * @{

+  */

+#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY          ((uint32_t)0x00000000)

+#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC         ((uint32_t)0x00100000)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_Write_FIFO FMC Write FIFO

+  * @{

+  */

+#define FMC_WRITE_FIFO_DISABLE                  ((uint32_t)FMC_BCR1_WFDIS)

+#define FMC_WRITE_FIFO_ENABLE                   ((uint32_t)0x00000000)

+/**

+  * @}

+  */

+

+  /** @defgroup FMC_Access_Mode FMC Access Mode

+  * @{

+  */

+#define FMC_ACCESS_MODE_A                       ((uint32_t)0x00000000)

+#define FMC_ACCESS_MODE_B                       ((uint32_t)0x10000000)

+#define FMC_ACCESS_MODE_C                       ((uint32_t)0x20000000)

+#define FMC_ACCESS_MODE_D                       ((uint32_t)0x30000000)

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+

+/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller

+  * @{

+  */

+/** @defgroup FMC_NAND_Bank FMC NAND Bank

+  * @{

+  */

+#define FMC_NAND_BANK3                          ((uint32_t)0x00000100)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_Wait_feature FMC Wait feature

+  * @{

+  */

+#define FMC_NAND_WAIT_FEATURE_DISABLE           ((uint32_t)0x00000000)

+#define FMC_NAND_WAIT_FEATURE_ENABLE            ((uint32_t)0x00000002)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type

+  * @{

+  */

+#define FMC_PCR_MEMORY_TYPE_NAND                ((uint32_t)0x00000008)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width

+  * @{

+  */

+#define FMC_NAND_MEM_BUS_WIDTH_8                ((uint32_t)0x00000000)

+#define FMC_NAND_MEM_BUS_WIDTH_16               ((uint32_t)0x00000010)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_ECC FMC ECC

+  * @{

+  */

+#define FMC_NAND_ECC_DISABLE                    ((uint32_t)0x00000000)

+#define FMC_NAND_ECC_ENABLE                     ((uint32_t)0x00000040)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size

+  * @{

+  */

+#define FMC_NAND_ECC_PAGE_SIZE_256BYTE          ((uint32_t)0x00000000)

+#define FMC_NAND_ECC_PAGE_SIZE_512BYTE          ((uint32_t)0x00020000)

+#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE         ((uint32_t)0x00040000)

+#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE         ((uint32_t)0x00060000)

+#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE         ((uint32_t)0x00080000)

+#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE         ((uint32_t)0x000A0000)

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller

+  * @{

+  */

+/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank

+  * @{

+  */

+#define FMC_SDRAM_BANK1                         ((uint32_t)0x00000000)

+#define FMC_SDRAM_BANK2                         ((uint32_t)0x00000001)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number

+  * @{

+  */

+#define FMC_SDRAM_COLUMN_BITS_NUM_8             ((uint32_t)0x00000000)

+#define FMC_SDRAM_COLUMN_BITS_NUM_9             ((uint32_t)0x00000001)

+#define FMC_SDRAM_COLUMN_BITS_NUM_10            ((uint32_t)0x00000002)

+#define FMC_SDRAM_COLUMN_BITS_NUM_11            ((uint32_t)0x00000003)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number

+  * @{

+  */

+#define FMC_SDRAM_ROW_BITS_NUM_11               ((uint32_t)0x00000000)

+#define FMC_SDRAM_ROW_BITS_NUM_12               ((uint32_t)0x00000004)

+#define FMC_SDRAM_ROW_BITS_NUM_13               ((uint32_t)0x00000008)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width

+  * @{

+  */

+#define FMC_SDRAM_MEM_BUS_WIDTH_8               ((uint32_t)0x00000000)

+#define FMC_SDRAM_MEM_BUS_WIDTH_16              ((uint32_t)0x00000010)

+#define FMC_SDRAM_MEM_BUS_WIDTH_32              ((uint32_t)0x00000020)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number

+  * @{

+  */

+#define FMC_SDRAM_INTERN_BANKS_NUM_2            ((uint32_t)0x00000000)

+#define FMC_SDRAM_INTERN_BANKS_NUM_4            ((uint32_t)0x00000040)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency

+  * @{

+  */

+#define FMC_SDRAM_CAS_LATENCY_1                 ((uint32_t)0x00000080)

+#define FMC_SDRAM_CAS_LATENCY_2                 ((uint32_t)0x00000100)

+#define FMC_SDRAM_CAS_LATENCY_3                 ((uint32_t)0x00000180)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection

+  * @{

+  */

+#define FMC_SDRAM_WRITE_PROTECTION_DISABLE      ((uint32_t)0x00000000)

+#define FMC_SDRAM_WRITE_PROTECTION_ENABLE       ((uint32_t)0x00000200)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period

+  * @{

+  */

+#define FMC_SDRAM_CLOCK_DISABLE                 ((uint32_t)0x00000000)

+#define FMC_SDRAM_CLOCK_PERIOD_2                ((uint32_t)0x00000800)

+#define FMC_SDRAM_CLOCK_PERIOD_3                ((uint32_t)0x00000C00)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst

+  * @{

+  */

+#define FMC_SDRAM_RBURST_DISABLE                ((uint32_t)0x00000000)

+#define FMC_SDRAM_RBURST_ENABLE                 ((uint32_t)0x00001000)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay

+  * @{

+  */

+#define FMC_SDRAM_RPIPE_DELAY_0                 ((uint32_t)0x00000000)

+#define FMC_SDRAM_RPIPE_DELAY_1                 ((uint32_t)0x00002000)

+#define FMC_SDRAM_RPIPE_DELAY_2                 ((uint32_t)0x00004000)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode

+  * @{

+  */

+#define FMC_SDRAM_CMD_NORMAL_MODE               ((uint32_t)0x00000000)

+#define FMC_SDRAM_CMD_CLK_ENABLE                ((uint32_t)0x00000001)

+#define FMC_SDRAM_CMD_PALL                      ((uint32_t)0x00000002)

+#define FMC_SDRAM_CMD_AUTOREFRESH_MODE          ((uint32_t)0x00000003)

+#define FMC_SDRAM_CMD_LOAD_MODE                 ((uint32_t)0x00000004)

+#define FMC_SDRAM_CMD_SELFREFRESH_MODE          ((uint32_t)0x00000005)

+#define FMC_SDRAM_CMD_POWERDOWN_MODE            ((uint32_t)0x00000006)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target

+  * @{

+  */

+#define FMC_SDRAM_CMD_TARGET_BANK2              FMC_SDCMR_CTB2

+#define FMC_SDRAM_CMD_TARGET_BANK1              FMC_SDCMR_CTB1

+#define FMC_SDRAM_CMD_TARGET_BANK1_2            ((uint32_t)0x00000018)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status

+  * @{

+  */

+#define FMC_SDRAM_NORMAL_MODE                   ((uint32_t)0x00000000)

+#define FMC_SDRAM_SELF_REFRESH_MODE             FMC_SDSR_MODES1_0

+#define FMC_SDRAM_POWER_DOWN_MODE               FMC_SDSR_MODES1_1

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+

+/** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition

+  * @{

+  */

+#define FMC_IT_RISING_EDGE                      ((uint32_t)0x00000008)

+#define FMC_IT_LEVEL                            ((uint32_t)0x00000010)

+#define FMC_IT_FALLING_EDGE                     ((uint32_t)0x00000020)

+#define FMC_IT_REFRESH_ERROR                    ((uint32_t)0x00004000)

+/**

+  * @}

+  */

+

+/** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition

+  * @{

+  */

+#define FMC_FLAG_RISING_EDGE                    ((uint32_t)0x00000001)

+#define FMC_FLAG_LEVEL                          ((uint32_t)0x00000002)

+#define FMC_FLAG_FALLING_EDGE                   ((uint32_t)0x00000004)

+#define FMC_FLAG_FEMPT                          ((uint32_t)0x00000040)

+#define FMC_SDRAM_FLAG_REFRESH_IT               FMC_SDSR_RE

+#define FMC_SDRAM_FLAG_BUSY                     FMC_SDSR_BUSY

+#define FMC_SDRAM_FLAG_REFRESH_ERROR            FMC_SDRTR_CRE

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+  

+/* Private macro -------------------------------------------------------------*/

+/** @defgroup FMC_LL_Private_Macros FMC_LL  Private Macros

+  * @{

+  */

+  /**

+  * @brief  Enable the FMC Peripheral.

+  * @retval None

+  */

+#define __FMC_ENABLE()  (FMC_Bank1_R->BTCR[0] |= FMC_BCR1_FMCEN)

+

+/**

+  * @brief  Disable the FMC Peripheral.

+  * @retval None

+  */

+#define __FMC_DISABLE()  (FMC_Bank1_R->BTCR[0] &= ~FMC_BCR1_FMCEN)

+/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros

+  * @brief macros to handle NOR device enable/disable and read/write operations

+  * @{

+  */

+

+/**

+  * @brief  Enable the NORSRAM device access.

+  * @param  __INSTANCE__ FMC_NORSRAM Instance

+  * @param  __BANK__ FMC_NORSRAM Bank

+  * @retval None

+  */

+#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__)  ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCRx_MBKEN)

+

+/**

+  * @brief  Disable the NORSRAM device access.

+  * @param  __INSTANCE__ FMC_NORSRAM Instance

+  * @param  __BANK__ FMC_NORSRAM Bank

+  * @retval None

+  */

+#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCRx_MBKEN)

+

+/**

+  * @}

+  */

+

+/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros

+ *  @brief macros to handle NAND device enable/disable

+ *  @{

+ */

+

+/**

+  * @brief  Enable the NAND device access.

+  * @param  __INSTANCE__ FMC_NAND Instance

+  * @retval None

+  */

+#define __FMC_NAND_ENABLE(__INSTANCE__)  ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)

+

+/**

+  * @brief  Disable the NAND device access.

+  * @param  __INSTANCE__ FMC_NAND Instance

+  * @param  __BANK__     FMC_NAND Bank

+  * @retval None

+  */

+#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) CLEAR_BIT((__INSTANCE__)->PCR, FMC_PCR_PBKEN)

+

+/**

+  * @}

+  */

+

+/** @defgroup FMC_LL_NAND_Interrupt FMC NAND Interrupt

+  * @brief macros to handle NAND interrupts

+  * @{

+  */

+

+/**

+  * @brief  Enable the NAND device interrupt.

+  * @param  __INSTANCE__  FMC_NAND instance

+  * @param  __INTERRUPT__ FMC_NAND interrupt

+  *         This parameter can be any combination of the following values:

+  *            @arg FMC_IT_RISING_EDGE: Interrupt rising edge.

+  *            @arg FMC_IT_LEVEL: Interrupt level.

+  *            @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.

+  * @retval None

+  */

+#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SR |= (__INTERRUPT__))

+

+/**

+  * @brief  Disable the NAND device interrupt.

+  * @param  __INSTANCE__  FMC_NAND Instance

+  * @param  __INTERRUPT__ FMC_NAND interrupt

+  *         This parameter can be any combination of the following values:

+  *            @arg FMC_IT_RISING_EDGE: Interrupt rising edge.

+  *            @arg FMC_IT_LEVEL: Interrupt level.

+  *            @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.

+  * @retval None

+  */

+#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SR &= ~(__INTERRUPT__))

+

+/**

+  * @brief  Get flag status of the NAND device.

+  * @param  __INSTANCE__ FMC_NAND Instance

+  * @param  __BANK__     FMC_NAND Bank

+  * @param  __FLAG__     FMC_NAND flag

+  *         This parameter can be any combination of the following values:

+  *            @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.

+  *            @arg FMC_FLAG_LEVEL: Interrupt level edge flag.

+  *            @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.

+  *            @arg FMC_FLAG_FEMPT: FIFO empty flag.

+  * @retval The state of FLAG (SET or RESET).

+  */

+#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__)  (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))

+

+/**

+  * @brief  Clear flag status of the NAND device.

+  * @param  __INSTANCE__ FMC_NAND Instance

+  * @param  __FLAG__     FMC_NAND flag

+  *         This parameter can be any combination of the following values:

+  *            @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.

+  *            @arg FMC_FLAG_LEVEL: Interrupt level edge flag.

+  *            @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.

+  *            @arg FMC_FLAG_FEMPT: FIFO empty flag.

+  * @retval None

+  */

+#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->SR &= ~(__FLAG__))

+

+/**

+  * @}

+  */

+

+

+/** @defgroup FMC_LL_SDRAM_Interrupt FMC SDRAM Interrupt

+  * @brief macros to handle SDRAM interrupts

+  * @{

+  */

+

+/**

+  * @brief  Enable the SDRAM device interrupt.

+  * @param  __INSTANCE__  FMC_SDRAM instance

+  * @param  __INTERRUPT__ FMC_SDRAM interrupt

+  *         This parameter can be any combination of the following values:

+  *            @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error

+  * @retval None

+  */

+#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))

+

+/**

+  * @brief  Disable the SDRAM device interrupt.

+  * @param  __INSTANCE__  FMC_SDRAM instance

+  * @param  __INTERRUPT__ FMC_SDRAM interrupt

+  *         This parameter can be any combination of the following values:

+  *            @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error

+  * @retval None

+  */

+#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))

+

+/**

+  * @brief  Get flag status of the SDRAM device.

+  * @param  __INSTANCE__ FMC_SDRAM instance

+  * @param  __FLAG__     FMC_SDRAM flag

+  *         This parameter can be any combination of the following values:

+  *            @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.

+  *            @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.

+  *            @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.

+  * @retval The state of FLAG (SET or RESET).

+  */

+#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))

+

+/**

+  * @brief  Clear flag status of the SDRAM device.

+  * @param  __INSTANCE__ FMC_SDRAM instance

+  * @param  __FLAG__     FMC_SDRAM flag

+  *         This parameter can be any combination of the following values:

+  *           @arg FMC_SDRAM_FLAG_REFRESH_ERROR

+  * @retval None

+  */

+#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->SDRTR |= (__FLAG__))

+

+/**

+  * @}

+  */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Private functions ---------------------------------------------------------*/

+/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions

+  *  @{

+  */

+

+/** @defgroup FMC_LL_NORSRAM  NOR SRAM

+  *  @{

+  */

+/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions

+  *  @{

+  */

+HAL_StatusTypeDef  FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);

+HAL_StatusTypeDef  FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);

+HAL_StatusTypeDef  FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);

+HAL_StatusTypeDef  FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);

+/**

+  * @}

+  */

+

+/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions

+  *  @{

+  */

+HAL_StatusTypeDef  FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);

+HAL_StatusTypeDef  FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);

+/**

+  * @}

+  */

+/**

+  * @}

+  */

+

+/** @defgroup FMC_LL_NAND NAND

+  *  @{

+  */

+/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions

+  *  @{

+  */

+HAL_StatusTypeDef  FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);

+HAL_StatusTypeDef  FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);

+HAL_StatusTypeDef  FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);

+HAL_StatusTypeDef  FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);

+/**

+  * @}

+  */

+

+/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions

+  *  @{

+  */

+HAL_StatusTypeDef  FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);

+HAL_StatusTypeDef  FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);

+HAL_StatusTypeDef  FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);

+/**

+  * @}

+  */

+/**

+  * @}

+  */

+

+

+/** @defgroup FMC_LL_SDRAM SDRAM

+  *  @{

+  */

+/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions

+  *  @{

+  */

+HAL_StatusTypeDef  FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);

+HAL_StatusTypeDef  FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);

+HAL_StatusTypeDef  FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);

+/**

+  * @}

+  */

+

+/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions

+  *  @{

+  */

+HAL_StatusTypeDef  FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);

+HAL_StatusTypeDef  FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);

+HAL_StatusTypeDef  FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);

+HAL_StatusTypeDef  FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);

+HAL_StatusTypeDef  FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);

+uint32_t           FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);

+/**

+  * @}

+  */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_LL_FMC_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_gpio.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_gpio.h
new file mode 100644
index 0000000000..a375a1246c
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_gpio.h
@@ -0,0 +1,985 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_gpio.h

+  * @author  MCD Application Team

+  * @brief   Header file of GPIO LL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_LL_GPIO_H

+#define STM32H7xx_LL_GPIO_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK)

+

+/** @defgroup GPIO_LL GPIO

+  * @{

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/* Private macros ------------------------------------------------------------*/

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros

+  * @{

+  */

+

+/**

+  * @}

+  */

+#endif /*USE_FULL_LL_DRIVER*/

+

+/* Exported types ------------------------------------------------------------*/

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures

+  * @{

+  */

+

+/**

+  * @brief LL GPIO Init Structure definition

+  */

+typedef struct

+{

+  uint32_t Pin;          /*!< Specifies the GPIO pins to be configured.

+                              This parameter can be any value of @ref GPIO_LL_EC_PIN */

+

+  uint32_t Mode;         /*!< Specifies the operating mode for the selected pins.

+                              This parameter can be a value of @ref GPIO_LL_EC_MODE.

+

+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/

+

+  uint32_t Speed;        /*!< Specifies the speed for the selected pins.

+                              This parameter can be a value of @ref GPIO_LL_EC_SPEED.

+

+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/

+

+  uint32_t OutputType;   /*!< Specifies the operating output type for the selected pins.

+                              This parameter can be a value of @ref GPIO_LL_EC_OUTPUT.

+

+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/

+

+  uint32_t Pull;         /*!< Specifies the operating Pull-up/Pull down for the selected pins.

+                              This parameter can be a value of @ref GPIO_LL_EC_PULL.

+

+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/

+

+  uint32_t Alternate;    /*!< Specifies the Peripheral to be connected to the selected pins.

+                              This parameter can be a value of @ref GPIO_LL_EC_AF.

+

+                              GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/

+} LL_GPIO_InitTypeDef;

+

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants

+  * @{

+  */

+

+/** @defgroup GPIO_LL_EC_PIN PIN

+  * @{

+  */

+#define LL_GPIO_PIN_0                      GPIO_BSRR_BS0 /*!< Select pin 0 */

+#define LL_GPIO_PIN_1                      GPIO_BSRR_BS1 /*!< Select pin 1 */

+#define LL_GPIO_PIN_2                      GPIO_BSRR_BS2 /*!< Select pin 2 */

+#define LL_GPIO_PIN_3                      GPIO_BSRR_BS3 /*!< Select pin 3 */

+#define LL_GPIO_PIN_4                      GPIO_BSRR_BS4 /*!< Select pin 4 */

+#define LL_GPIO_PIN_5                      GPIO_BSRR_BS5 /*!< Select pin 5 */

+#define LL_GPIO_PIN_6                      GPIO_BSRR_BS6 /*!< Select pin 6 */

+#define LL_GPIO_PIN_7                      GPIO_BSRR_BS7 /*!< Select pin 7 */

+#define LL_GPIO_PIN_8                      GPIO_BSRR_BS8 /*!< Select pin 8 */

+#define LL_GPIO_PIN_9                      GPIO_BSRR_BS9 /*!< Select pin 9 */

+#define LL_GPIO_PIN_10                     GPIO_BSRR_BS10 /*!< Select pin 10 */

+#define LL_GPIO_PIN_11                     GPIO_BSRR_BS11 /*!< Select pin 11 */

+#define LL_GPIO_PIN_12                     GPIO_BSRR_BS12 /*!< Select pin 12 */

+#define LL_GPIO_PIN_13                     GPIO_BSRR_BS13 /*!< Select pin 13 */

+#define LL_GPIO_PIN_14                     GPIO_BSRR_BS14 /*!< Select pin 14 */

+#define LL_GPIO_PIN_15                     GPIO_BSRR_BS15 /*!< Select pin 15 */

+#define LL_GPIO_PIN_ALL                    (GPIO_BSRR_BS0 | GPIO_BSRR_BS1  | GPIO_BSRR_BS2  | \

+                                           GPIO_BSRR_BS3  | GPIO_BSRR_BS4  | GPIO_BSRR_BS5  | \

+                                           GPIO_BSRR_BS6  | GPIO_BSRR_BS7  | GPIO_BSRR_BS8  | \

+                                           GPIO_BSRR_BS9  | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \

+                                           GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \

+                                           GPIO_BSRR_BS15) /*!< Select all pins */

+/**

+  * @}

+  */

+

+/** @defgroup GPIO_LL_EC_MODE Mode

+  * @{

+  */

+#define LL_GPIO_MODE_INPUT                 (0x00000000U) /*!< Select input mode */

+#define LL_GPIO_MODE_OUTPUT                GPIO_MODER_MODE0_0  /*!< Select output mode */

+#define LL_GPIO_MODE_ALTERNATE             GPIO_MODER_MODE0_1  /*!< Select alternate function mode */

+#define LL_GPIO_MODE_ANALOG                GPIO_MODER_MODE0    /*!< Select analog mode */

+/**

+  * @}

+  */

+

+/** @defgroup GPIO_LL_EC_OUTPUT Output Type

+  * @{

+  */

+#define LL_GPIO_OUTPUT_PUSHPULL            (0x00000000U) /*!< Select push-pull as output type */

+#define LL_GPIO_OUTPUT_OPENDRAIN           GPIO_OTYPER_OT0 /*!< Select open-drain as output type */

+/**

+  * @}

+  */

+

+/** @defgroup GPIO_LL_EC_SPEED Output Speed

+  * @{

+  */

+#define LL_GPIO_SPEED_FREQ_LOW             (0x00000000U) /*!< Select I/O low output speed    */

+#define LL_GPIO_SPEED_FREQ_MEDIUM          GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */

+#define LL_GPIO_SPEED_FREQ_HIGH            GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed   */

+#define LL_GPIO_SPEED_FREQ_VERY_HIGH       GPIO_OSPEEDR_OSPEED0   /*!< Select I/O high output speed   */

+/**

+  * @}

+  */

+#define LL_GPIO_SPEED_LOW                  LL_GPIO_SPEED_FREQ_LOW

+#define LL_GPIO_SPEED_MEDIUM               LL_GPIO_SPEED_FREQ_MEDIUM

+#define LL_GPIO_SPEED_FAST                 LL_GPIO_SPEED_FREQ_HIGH

+#define LL_GPIO_SPEED_HIGH                 LL_GPIO_SPEED_FREQ_VERY_HIGH

+

+

+/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down

+  * @{

+  */

+#define LL_GPIO_PULL_NO                    (0x00000000U) /*!< Select I/O no pull */

+#define LL_GPIO_PULL_UP                    GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */

+#define LL_GPIO_PULL_DOWN                  GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */

+/**

+  * @}

+  */

+

+/** @defgroup GPIO_LL_EC_AF Alternate Function

+  * @{

+  */

+#define LL_GPIO_AF_0                       (0x0000000U) /*!< Select alternate function 0 */

+#define LL_GPIO_AF_1                       (0x0000001U) /*!< Select alternate function 1 */

+#define LL_GPIO_AF_2                       (0x0000002U) /*!< Select alternate function 2 */

+#define LL_GPIO_AF_3                       (0x0000003U) /*!< Select alternate function 3 */

+#define LL_GPIO_AF_4                       (0x0000004U) /*!< Select alternate function 4 */

+#define LL_GPIO_AF_5                       (0x0000005U) /*!< Select alternate function 5 */

+#define LL_GPIO_AF_6                       (0x0000006U) /*!< Select alternate function 6 */

+#define LL_GPIO_AF_7                       (0x0000007U) /*!< Select alternate function 7 */

+#define LL_GPIO_AF_8                       (0x0000008U) /*!< Select alternate function 8 */

+#define LL_GPIO_AF_9                       (0x0000009U) /*!< Select alternate function 9 */

+#define LL_GPIO_AF_10                      (0x000000AU) /*!< Select alternate function 10 */

+#define LL_GPIO_AF_11                      (0x000000BU) /*!< Select alternate function 11 */

+#define LL_GPIO_AF_12                      (0x000000CU) /*!< Select alternate function 12 */

+#define LL_GPIO_AF_13                      (0x000000DU) /*!< Select alternate function 13 */

+#define LL_GPIO_AF_14                      (0x000000EU) /*!< Select alternate function 14 */

+#define LL_GPIO_AF_15                      (0x000000FU) /*!< Select alternate function 15 */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros

+  * @{

+  */

+

+/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros

+  * @{

+  */

+

+/**

+  * @brief  Write a value in GPIO register

+  * @param  __INSTANCE__ GPIO Instance

+  * @param  __REG__ Register to be written

+  * @param  __VALUE__ Value to be written in the register

+  * @retval None

+  */

+#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

+

+/**

+  * @brief  Read a value in GPIO register

+  * @param  __INSTANCE__ GPIO Instance

+  * @param  __REG__ Register to be read

+  * @retval Register value

+  */

+#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions

+  * @{

+  */

+

+/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration

+  * @{

+  */

+

+/**

+  * @brief  Configure gpio mode for a dedicated pin on dedicated port.

+  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.

+  * @note   Warning: only one pin can be passed as parameter.

+  * @rmtoll MODER        MODEy         LL_GPIO_SetPinMode

+  * @param  GPIOx GPIO Port

+  * @param  Pin This parameter can be one of the following values:

+  *         @arg @ref LL_GPIO_PIN_0

+  *         @arg @ref LL_GPIO_PIN_1

+  *         @arg @ref LL_GPIO_PIN_2

+  *         @arg @ref LL_GPIO_PIN_3

+  *         @arg @ref LL_GPIO_PIN_4

+  *         @arg @ref LL_GPIO_PIN_5

+  *         @arg @ref LL_GPIO_PIN_6

+  *         @arg @ref LL_GPIO_PIN_7

+  *         @arg @ref LL_GPIO_PIN_8

+  *         @arg @ref LL_GPIO_PIN_9

+  *         @arg @ref LL_GPIO_PIN_10

+  *         @arg @ref LL_GPIO_PIN_11

+  *         @arg @ref LL_GPIO_PIN_12

+  *         @arg @ref LL_GPIO_PIN_13

+  *         @arg @ref LL_GPIO_PIN_14

+  *         @arg @ref LL_GPIO_PIN_15

+  * @param  Mode This parameter can be one of the following values:

+  *         @arg @ref LL_GPIO_MODE_INPUT

+  *         @arg @ref LL_GPIO_MODE_OUTPUT

+  *         @arg @ref LL_GPIO_MODE_ALTERNATE

+  *         @arg @ref LL_GPIO_MODE_ANALOG

+  * @retval None

+  */

+__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode)

+{

+  MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0), ((Pin * Pin) * Mode));

+}

+

+/**

+  * @brief  Return gpio mode for a dedicated pin on dedicated port.

+  * @note   I/O mode can be Input mode, General purpose output, Alternate function mode or Analog.

+  * @note   Warning: only one pin can be passed as parameter.

+  * @rmtoll MODER        MODEy         LL_GPIO_GetPinMode

+  * @param  GPIOx GPIO Port

+  * @param  Pin This parameter can be one of the following values:

+  *         @arg @ref LL_GPIO_PIN_0

+  *         @arg @ref LL_GPIO_PIN_1

+  *         @arg @ref LL_GPIO_PIN_2

+  *         @arg @ref LL_GPIO_PIN_3

+  *         @arg @ref LL_GPIO_PIN_4

+  *         @arg @ref LL_GPIO_PIN_5

+  *         @arg @ref LL_GPIO_PIN_6

+  *         @arg @ref LL_GPIO_PIN_7

+  *         @arg @ref LL_GPIO_PIN_8

+  *         @arg @ref LL_GPIO_PIN_9

+  *         @arg @ref LL_GPIO_PIN_10

+  *         @arg @ref LL_GPIO_PIN_11

+  *         @arg @ref LL_GPIO_PIN_12

+  *         @arg @ref LL_GPIO_PIN_13

+  *         @arg @ref LL_GPIO_PIN_14

+  *         @arg @ref LL_GPIO_PIN_15

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_GPIO_MODE_INPUT

+  *         @arg @ref LL_GPIO_MODE_OUTPUT

+  *         @arg @ref LL_GPIO_MODE_ALTERNATE

+  *         @arg @ref LL_GPIO_MODE_ANALOG

+  */

+__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin)

+{

+  return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0)) / (Pin * Pin));

+}

+

+/**

+  * @brief  Configure gpio output type for several pins on dedicated port.

+  * @note   Output type as to be set when gpio pin is in output or

+  *         alternate modes. Possible type are Push-pull or Open-drain.

+  * @rmtoll OTYPER       OTy           LL_GPIO_SetPinOutputType

+  * @param  GPIOx GPIO Port

+  * @param  PinMask This parameter can be a combination of the following values:

+  *         @arg @ref LL_GPIO_PIN_0

+  *         @arg @ref LL_GPIO_PIN_1

+  *         @arg @ref LL_GPIO_PIN_2

+  *         @arg @ref LL_GPIO_PIN_3

+  *         @arg @ref LL_GPIO_PIN_4

+  *         @arg @ref LL_GPIO_PIN_5

+  *         @arg @ref LL_GPIO_PIN_6

+  *         @arg @ref LL_GPIO_PIN_7

+  *         @arg @ref LL_GPIO_PIN_8

+  *         @arg @ref LL_GPIO_PIN_9

+  *         @arg @ref LL_GPIO_PIN_10

+  *         @arg @ref LL_GPIO_PIN_11

+  *         @arg @ref LL_GPIO_PIN_12

+  *         @arg @ref LL_GPIO_PIN_13

+  *         @arg @ref LL_GPIO_PIN_14

+  *         @arg @ref LL_GPIO_PIN_15

+  *         @arg @ref LL_GPIO_PIN_ALL

+  * @param  OutputType This parameter can be one of the following values:

+  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL

+  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN

+  * @retval None

+  */

+__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType)

+{

+  MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType));

+}

+

+/**

+  * @brief  Return gpio output type for several pins on dedicated port.

+  * @note   Output type as to be set when gpio pin is in output or

+  *         alternate modes. Possible type are Push-pull or Open-drain.

+  * @note   Warning: only one pin can be passed as parameter.

+  * @rmtoll OTYPER       OTy           LL_GPIO_GetPinOutputType

+  * @param  GPIOx GPIO Port

+  * @param  Pin This parameter can be one of the following values:

+  *         @arg @ref LL_GPIO_PIN_0

+  *         @arg @ref LL_GPIO_PIN_1

+  *         @arg @ref LL_GPIO_PIN_2

+  *         @arg @ref LL_GPIO_PIN_3

+  *         @arg @ref LL_GPIO_PIN_4

+  *         @arg @ref LL_GPIO_PIN_5

+  *         @arg @ref LL_GPIO_PIN_6

+  *         @arg @ref LL_GPIO_PIN_7

+  *         @arg @ref LL_GPIO_PIN_8

+  *         @arg @ref LL_GPIO_PIN_9

+  *         @arg @ref LL_GPIO_PIN_10

+  *         @arg @ref LL_GPIO_PIN_11

+  *         @arg @ref LL_GPIO_PIN_12

+  *         @arg @ref LL_GPIO_PIN_13

+  *         @arg @ref LL_GPIO_PIN_14

+  *         @arg @ref LL_GPIO_PIN_15

+  *         @arg @ref LL_GPIO_PIN_ALL

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_GPIO_OUTPUT_PUSHPULL

+  *         @arg @ref LL_GPIO_OUTPUT_OPENDRAIN

+  */

+__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin)

+{

+  return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin);

+}

+

+/**

+  * @brief  Configure gpio speed for a dedicated pin on dedicated port.

+  * @note   I/O speed can be Low, Medium, Fast or High speed.

+  * @note   Warning: only one pin can be passed as parameter.

+  * @note   Refer to datasheet for frequency specifications and the power

+  *         supply and load conditions for each speed.

+  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_SetPinSpeed

+  * @param  GPIOx GPIO Port

+  * @param  Pin This parameter can be one of the following values:

+  *         @arg @ref LL_GPIO_PIN_0

+  *         @arg @ref LL_GPIO_PIN_1

+  *         @arg @ref LL_GPIO_PIN_2

+  *         @arg @ref LL_GPIO_PIN_3

+  *         @arg @ref LL_GPIO_PIN_4

+  *         @arg @ref LL_GPIO_PIN_5

+  *         @arg @ref LL_GPIO_PIN_6

+  *         @arg @ref LL_GPIO_PIN_7

+  *         @arg @ref LL_GPIO_PIN_8

+  *         @arg @ref LL_GPIO_PIN_9

+  *         @arg @ref LL_GPIO_PIN_10

+  *         @arg @ref LL_GPIO_PIN_11

+  *         @arg @ref LL_GPIO_PIN_12

+  *         @arg @ref LL_GPIO_PIN_13

+  *         @arg @ref LL_GPIO_PIN_14

+  *         @arg @ref LL_GPIO_PIN_15

+  * @param  Speed This parameter can be one of the following values:

+  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW

+  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM

+  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH

+  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH

+  * @retval None

+  */

+__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t  Speed)

+{

+  MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0), ((Pin * Pin) * Speed));

+}

+

+/**

+  * @brief  Return gpio speed for a dedicated pin on dedicated port.

+  * @note   I/O speed can be Low, Medium, Fast or High speed.

+  * @note   Warning: only one pin can be passed as parameter.

+  * @note   Refer to datasheet for frequency specifications and the power

+  *         supply and load conditions for each speed.

+  * @rmtoll OSPEEDR      OSPEEDy       LL_GPIO_GetPinSpeed

+  * @param  GPIOx GPIO Port

+  * @param  Pin This parameter can be one of the following values:

+  *         @arg @ref LL_GPIO_PIN_0

+  *         @arg @ref LL_GPIO_PIN_1

+  *         @arg @ref LL_GPIO_PIN_2

+  *         @arg @ref LL_GPIO_PIN_3

+  *         @arg @ref LL_GPIO_PIN_4

+  *         @arg @ref LL_GPIO_PIN_5

+  *         @arg @ref LL_GPIO_PIN_6

+  *         @arg @ref LL_GPIO_PIN_7

+  *         @arg @ref LL_GPIO_PIN_8

+  *         @arg @ref LL_GPIO_PIN_9

+  *         @arg @ref LL_GPIO_PIN_10

+  *         @arg @ref LL_GPIO_PIN_11

+  *         @arg @ref LL_GPIO_PIN_12

+  *         @arg @ref LL_GPIO_PIN_13

+  *         @arg @ref LL_GPIO_PIN_14

+  *         @arg @ref LL_GPIO_PIN_15

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_GPIO_SPEED_FREQ_LOW

+  *         @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM

+  *         @arg @ref LL_GPIO_SPEED_FREQ_HIGH

+  *         @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH

+  */

+__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin)

+{

+  return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0)) / (Pin * Pin));

+}

+

+/**

+  * @brief  Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port.

+  * @note   Warning: only one pin can be passed as parameter.

+  * @rmtoll PUPDR        PUPDy         LL_GPIO_SetPinPull

+  * @param  GPIOx GPIO Port

+  * @param  Pin This parameter can be one of the following values:

+  *         @arg @ref LL_GPIO_PIN_0

+  *         @arg @ref LL_GPIO_PIN_1

+  *         @arg @ref LL_GPIO_PIN_2

+  *         @arg @ref LL_GPIO_PIN_3

+  *         @arg @ref LL_GPIO_PIN_4

+  *         @arg @ref LL_GPIO_PIN_5

+  *         @arg @ref LL_GPIO_PIN_6

+  *         @arg @ref LL_GPIO_PIN_7

+  *         @arg @ref LL_GPIO_PIN_8

+  *         @arg @ref LL_GPIO_PIN_9

+  *         @arg @ref LL_GPIO_PIN_10

+  *         @arg @ref LL_GPIO_PIN_11

+  *         @arg @ref LL_GPIO_PIN_12

+  *         @arg @ref LL_GPIO_PIN_13

+  *         @arg @ref LL_GPIO_PIN_14

+  *         @arg @ref LL_GPIO_PIN_15

+  * @param  Pull This parameter can be one of the following values:

+  *         @arg @ref LL_GPIO_PULL_NO

+  *         @arg @ref LL_GPIO_PULL_UP

+  *         @arg @ref LL_GPIO_PULL_DOWN

+  * @retval None

+  */

+__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull)

+{

+  MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0), ((Pin * Pin) * Pull));

+}

+

+/**

+  * @brief  Return gpio pull-up or pull-down for a dedicated pin on a dedicated port

+  * @note   Warning: only one pin can be passed as parameter.

+  * @rmtoll PUPDR        PUPDy         LL_GPIO_GetPinPull

+  * @param  GPIOx GPIO Port

+  * @param  Pin This parameter can be one of the following values:

+  *         @arg @ref LL_GPIO_PIN_0

+  *         @arg @ref LL_GPIO_PIN_1

+  *         @arg @ref LL_GPIO_PIN_2

+  *         @arg @ref LL_GPIO_PIN_3

+  *         @arg @ref LL_GPIO_PIN_4

+  *         @arg @ref LL_GPIO_PIN_5

+  *         @arg @ref LL_GPIO_PIN_6

+  *         @arg @ref LL_GPIO_PIN_7

+  *         @arg @ref LL_GPIO_PIN_8

+  *         @arg @ref LL_GPIO_PIN_9

+  *         @arg @ref LL_GPIO_PIN_10

+  *         @arg @ref LL_GPIO_PIN_11

+  *         @arg @ref LL_GPIO_PIN_12

+  *         @arg @ref LL_GPIO_PIN_13

+  *         @arg @ref LL_GPIO_PIN_14

+  *         @arg @ref LL_GPIO_PIN_15

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_GPIO_PULL_NO

+  *         @arg @ref LL_GPIO_PULL_UP

+  *         @arg @ref LL_GPIO_PULL_DOWN

+  */

+__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin)

+{

+  return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0)) / (Pin * Pin));

+}

+

+/**

+  * @brief  Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.

+  * @note   Possible values are from AF0 to AF15 depending on target.

+  * @note   Warning: only one pin can be passed as parameter.

+  * @rmtoll AFRL         AFSELy        LL_GPIO_SetAFPin_0_7

+  * @param  GPIOx GPIO Port

+  * @param  Pin This parameter can be one of the following values:

+  *         @arg @ref LL_GPIO_PIN_0

+  *         @arg @ref LL_GPIO_PIN_1

+  *         @arg @ref LL_GPIO_PIN_2

+  *         @arg @ref LL_GPIO_PIN_3

+  *         @arg @ref LL_GPIO_PIN_4

+  *         @arg @ref LL_GPIO_PIN_5

+  *         @arg @ref LL_GPIO_PIN_6

+  *         @arg @ref LL_GPIO_PIN_7

+  * @param  Alternate This parameter can be one of the following values:

+  *         @arg @ref LL_GPIO_AF_0

+  *         @arg @ref LL_GPIO_AF_1

+  *         @arg @ref LL_GPIO_AF_2

+  *         @arg @ref LL_GPIO_AF_3

+  *         @arg @ref LL_GPIO_AF_4

+  *         @arg @ref LL_GPIO_AF_5

+  *         @arg @ref LL_GPIO_AF_6

+  *         @arg @ref LL_GPIO_AF_7

+  *         @arg @ref LL_GPIO_AF_8

+  *         @arg @ref LL_GPIO_AF_9

+  *         @arg @ref LL_GPIO_AF_10

+  *         @arg @ref LL_GPIO_AF_11

+  *         @arg @ref LL_GPIO_AF_12

+  *         @arg @ref LL_GPIO_AF_13

+  *         @arg @ref LL_GPIO_AF_14

+  *         @arg @ref LL_GPIO_AF_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)

+{

+  MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0),

+             ((((Pin * Pin) * Pin) * Pin) * Alternate));

+}

+

+/**

+  * @brief  Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port.

+  * @rmtoll AFRL         AFSELy        LL_GPIO_GetAFPin_0_7

+  * @param  GPIOx GPIO Port

+  * @param  Pin This parameter can be one of the following values:

+  *         @arg @ref LL_GPIO_PIN_0

+  *         @arg @ref LL_GPIO_PIN_1

+  *         @arg @ref LL_GPIO_PIN_2

+  *         @arg @ref LL_GPIO_PIN_3

+  *         @arg @ref LL_GPIO_PIN_4

+  *         @arg @ref LL_GPIO_PIN_5

+  *         @arg @ref LL_GPIO_PIN_6

+  *         @arg @ref LL_GPIO_PIN_7

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_GPIO_AF_0

+  *         @arg @ref LL_GPIO_AF_1

+  *         @arg @ref LL_GPIO_AF_2

+  *         @arg @ref LL_GPIO_AF_3

+  *         @arg @ref LL_GPIO_AF_4

+  *         @arg @ref LL_GPIO_AF_5

+  *         @arg @ref LL_GPIO_AF_6

+  *         @arg @ref LL_GPIO_AF_7

+  *         @arg @ref LL_GPIO_AF_8

+  *         @arg @ref LL_GPIO_AF_9

+  *         @arg @ref LL_GPIO_AF_10

+  *         @arg @ref LL_GPIO_AF_11

+  *         @arg @ref LL_GPIO_AF_12

+  *         @arg @ref LL_GPIO_AF_13

+  *         @arg @ref LL_GPIO_AF_14

+  *         @arg @ref LL_GPIO_AF_15

+  */

+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin)

+{

+  return (uint32_t)(READ_BIT(GPIOx->AFR[0],

+                             ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin));

+}

+

+/**

+  * @brief  Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.

+  * @note   Possible values are from AF0 to AF15 depending on target.

+  * @note   Warning: only one pin can be passed as parameter.

+  * @rmtoll AFRH         AFSELy        LL_GPIO_SetAFPin_8_15

+  * @param  GPIOx GPIO Port

+  * @param  Pin This parameter can be one of the following values:

+  *         @arg @ref LL_GPIO_PIN_8

+  *         @arg @ref LL_GPIO_PIN_9

+  *         @arg @ref LL_GPIO_PIN_10

+  *         @arg @ref LL_GPIO_PIN_11

+  *         @arg @ref LL_GPIO_PIN_12

+  *         @arg @ref LL_GPIO_PIN_13

+  *         @arg @ref LL_GPIO_PIN_14

+  *         @arg @ref LL_GPIO_PIN_15

+  * @param  Alternate This parameter can be one of the following values:

+  *         @arg @ref LL_GPIO_AF_0

+  *         @arg @ref LL_GPIO_AF_1

+  *         @arg @ref LL_GPIO_AF_2

+  *         @arg @ref LL_GPIO_AF_3

+  *         @arg @ref LL_GPIO_AF_4

+  *         @arg @ref LL_GPIO_AF_5

+  *         @arg @ref LL_GPIO_AF_6

+  *         @arg @ref LL_GPIO_AF_7

+  *         @arg @ref LL_GPIO_AF_8

+  *         @arg @ref LL_GPIO_AF_9

+  *         @arg @ref LL_GPIO_AF_10

+  *         @arg @ref LL_GPIO_AF_11

+  *         @arg @ref LL_GPIO_AF_12

+  *         @arg @ref LL_GPIO_AF_13

+  *         @arg @ref LL_GPIO_AF_14

+  *         @arg @ref LL_GPIO_AF_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate)

+{

+  MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8),

+             (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate));

+}

+

+/**

+  * @brief  Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port.

+  * @note   Possible values are from AF0 to AF15 depending on target.

+  * @rmtoll AFRH         AFSELy        LL_GPIO_GetAFPin_8_15

+  * @param  GPIOx GPIO Port

+  * @param  Pin This parameter can be one of the following values:

+  *         @arg @ref LL_GPIO_PIN_8

+  *         @arg @ref LL_GPIO_PIN_9

+  *         @arg @ref LL_GPIO_PIN_10

+  *         @arg @ref LL_GPIO_PIN_11

+  *         @arg @ref LL_GPIO_PIN_12

+  *         @arg @ref LL_GPIO_PIN_13

+  *         @arg @ref LL_GPIO_PIN_14

+  *         @arg @ref LL_GPIO_PIN_15

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_GPIO_AF_0

+  *         @arg @ref LL_GPIO_AF_1

+  *         @arg @ref LL_GPIO_AF_2

+  *         @arg @ref LL_GPIO_AF_3

+  *         @arg @ref LL_GPIO_AF_4

+  *         @arg @ref LL_GPIO_AF_5

+  *         @arg @ref LL_GPIO_AF_6

+  *         @arg @ref LL_GPIO_AF_7

+  *         @arg @ref LL_GPIO_AF_8

+  *         @arg @ref LL_GPIO_AF_9

+  *         @arg @ref LL_GPIO_AF_10

+  *         @arg @ref LL_GPIO_AF_11

+  *         @arg @ref LL_GPIO_AF_12

+  *         @arg @ref LL_GPIO_AF_13

+  *         @arg @ref LL_GPIO_AF_14

+  *         @arg @ref LL_GPIO_AF_15

+  */

+__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin)

+{

+  return (uint32_t)(READ_BIT(GPIOx->AFR[1],

+                             (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / ((((Pin >> 8U) *

+                                 (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)));

+}

+

+

+/**

+  * @brief  Lock configuration of several pins for a dedicated port.

+  * @note   When the lock sequence has been applied on a port bit, the

+  *         value of this port bit can no longer be modified until the

+  *         next reset.

+  * @note   Each lock bit freezes a specific configuration register

+  *         (control and alternate function registers).

+  * @rmtoll LCKR         LCKK          LL_GPIO_LockPin

+  * @param  GPIOx GPIO Port

+  * @param  PinMask This parameter can be a combination of the following values:

+  *         @arg @ref LL_GPIO_PIN_0

+  *         @arg @ref LL_GPIO_PIN_1

+  *         @arg @ref LL_GPIO_PIN_2

+  *         @arg @ref LL_GPIO_PIN_3

+  *         @arg @ref LL_GPIO_PIN_4

+  *         @arg @ref LL_GPIO_PIN_5

+  *         @arg @ref LL_GPIO_PIN_6

+  *         @arg @ref LL_GPIO_PIN_7

+  *         @arg @ref LL_GPIO_PIN_8

+  *         @arg @ref LL_GPIO_PIN_9

+  *         @arg @ref LL_GPIO_PIN_10

+  *         @arg @ref LL_GPIO_PIN_11

+  *         @arg @ref LL_GPIO_PIN_12

+  *         @arg @ref LL_GPIO_PIN_13

+  *         @arg @ref LL_GPIO_PIN_14

+  *         @arg @ref LL_GPIO_PIN_15

+  *         @arg @ref LL_GPIO_PIN_ALL

+  * @retval None

+  */

+__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)

+{

+  __IO uint32_t temp;

+  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);

+  WRITE_REG(GPIOx->LCKR, PinMask);

+  WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask);

+  /* Read LCKK register. This read is mandatory to complete key lock sequence */

+  temp = READ_REG(GPIOx->LCKR);

+  (void) temp;

+}

+

+/**

+  * @brief  Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0.

+  * @rmtoll LCKR         LCKy          LL_GPIO_IsPinLocked

+  * @param  GPIOx GPIO Port

+  * @param  PinMask This parameter can be a combination of the following values:

+  *         @arg @ref LL_GPIO_PIN_0

+  *         @arg @ref LL_GPIO_PIN_1

+  *         @arg @ref LL_GPIO_PIN_2

+  *         @arg @ref LL_GPIO_PIN_3

+  *         @arg @ref LL_GPIO_PIN_4

+  *         @arg @ref LL_GPIO_PIN_5

+  *         @arg @ref LL_GPIO_PIN_6

+  *         @arg @ref LL_GPIO_PIN_7

+  *         @arg @ref LL_GPIO_PIN_8

+  *         @arg @ref LL_GPIO_PIN_9

+  *         @arg @ref LL_GPIO_PIN_10

+  *         @arg @ref LL_GPIO_PIN_11

+  *         @arg @ref LL_GPIO_PIN_12

+  *         @arg @ref LL_GPIO_PIN_13

+  *         @arg @ref LL_GPIO_PIN_14

+  *         @arg @ref LL_GPIO_PIN_15

+  *         @arg @ref LL_GPIO_PIN_ALL

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask)

+{

+  return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Return 1 if one of the pin of a dedicated port is locked. else return 0.

+  * @rmtoll LCKR         LCKK          LL_GPIO_IsAnyPinLocked

+  * @param  GPIOx GPIO Port

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx)

+{

+  return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup GPIO_LL_EF_Data_Access Data Access

+  * @{

+  */

+

+/**

+  * @brief  Return full input data register value for a dedicated port.

+  * @rmtoll IDR          IDy           LL_GPIO_ReadInputPort

+  * @param  GPIOx GPIO Port

+  * @retval Input data register value of port

+  */

+__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx)

+{

+  return (uint32_t)(READ_REG(GPIOx->IDR));

+}

+

+/**

+  * @brief  Return if input data level for several pins of dedicated port is high or low.

+  * @rmtoll IDR          IDy           LL_GPIO_IsInputPinSet

+  * @param  GPIOx GPIO Port

+  * @param  PinMask This parameter can be a combination of the following values:

+  *         @arg @ref LL_GPIO_PIN_0

+  *         @arg @ref LL_GPIO_PIN_1

+  *         @arg @ref LL_GPIO_PIN_2

+  *         @arg @ref LL_GPIO_PIN_3

+  *         @arg @ref LL_GPIO_PIN_4

+  *         @arg @ref LL_GPIO_PIN_5

+  *         @arg @ref LL_GPIO_PIN_6

+  *         @arg @ref LL_GPIO_PIN_7

+  *         @arg @ref LL_GPIO_PIN_8

+  *         @arg @ref LL_GPIO_PIN_9

+  *         @arg @ref LL_GPIO_PIN_10

+  *         @arg @ref LL_GPIO_PIN_11

+  *         @arg @ref LL_GPIO_PIN_12

+  *         @arg @ref LL_GPIO_PIN_13

+  *         @arg @ref LL_GPIO_PIN_14

+  *         @arg @ref LL_GPIO_PIN_15

+  *         @arg @ref LL_GPIO_PIN_ALL

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)

+{

+  return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Write output data register for the port.

+  * @rmtoll ODR          ODy           LL_GPIO_WriteOutputPort

+  * @param  GPIOx GPIO Port

+  * @param  PortValue Level value for each pin of the port

+  * @retval None

+  */

+__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue)

+{

+  WRITE_REG(GPIOx->ODR, PortValue);

+}

+

+/**

+  * @brief  Return full output data register value for a dedicated port.

+  * @rmtoll ODR          ODy           LL_GPIO_ReadOutputPort

+  * @param  GPIOx GPIO Port

+  * @retval Output data register value of port

+  */

+__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx)

+{

+  return (uint32_t)(READ_REG(GPIOx->ODR));

+}

+

+/**

+  * @brief  Return if input data level for several pins of dedicated port is high or low.

+  * @rmtoll ODR          ODy           LL_GPIO_IsOutputPinSet

+  * @param  GPIOx GPIO Port

+  * @param  PinMask This parameter can be a combination of the following values:

+  *         @arg @ref LL_GPIO_PIN_0

+  *         @arg @ref LL_GPIO_PIN_1

+  *         @arg @ref LL_GPIO_PIN_2

+  *         @arg @ref LL_GPIO_PIN_3

+  *         @arg @ref LL_GPIO_PIN_4

+  *         @arg @ref LL_GPIO_PIN_5

+  *         @arg @ref LL_GPIO_PIN_6

+  *         @arg @ref LL_GPIO_PIN_7

+  *         @arg @ref LL_GPIO_PIN_8

+  *         @arg @ref LL_GPIO_PIN_9

+  *         @arg @ref LL_GPIO_PIN_10

+  *         @arg @ref LL_GPIO_PIN_11

+  *         @arg @ref LL_GPIO_PIN_12

+  *         @arg @ref LL_GPIO_PIN_13

+  *         @arg @ref LL_GPIO_PIN_14

+  *         @arg @ref LL_GPIO_PIN_15

+  *         @arg @ref LL_GPIO_PIN_ALL

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask)

+{

+  return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set several pins to high level on dedicated gpio port.

+  * @rmtoll BSRR         BSy           LL_GPIO_SetOutputPin

+  * @param  GPIOx GPIO Port

+  * @param  PinMask This parameter can be a combination of the following values:

+  *         @arg @ref LL_GPIO_PIN_0

+  *         @arg @ref LL_GPIO_PIN_1

+  *         @arg @ref LL_GPIO_PIN_2

+  *         @arg @ref LL_GPIO_PIN_3

+  *         @arg @ref LL_GPIO_PIN_4

+  *         @arg @ref LL_GPIO_PIN_5

+  *         @arg @ref LL_GPIO_PIN_6

+  *         @arg @ref LL_GPIO_PIN_7

+  *         @arg @ref LL_GPIO_PIN_8

+  *         @arg @ref LL_GPIO_PIN_9

+  *         @arg @ref LL_GPIO_PIN_10

+  *         @arg @ref LL_GPIO_PIN_11

+  *         @arg @ref LL_GPIO_PIN_12

+  *         @arg @ref LL_GPIO_PIN_13

+  *         @arg @ref LL_GPIO_PIN_14

+  *         @arg @ref LL_GPIO_PIN_15

+  *         @arg @ref LL_GPIO_PIN_ALL

+  * @retval None

+  */

+__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)

+{

+  WRITE_REG(GPIOx->BSRR, PinMask);

+}

+

+/**

+  * @brief  Set several pins to low level on dedicated gpio port.

+  * @rmtoll BSRR         BRy           LL_GPIO_ResetOutputPin

+  * @param  GPIOx GPIO Port

+  * @param  PinMask This parameter can be a combination of the following values:

+  *         @arg @ref LL_GPIO_PIN_0

+  *         @arg @ref LL_GPIO_PIN_1

+  *         @arg @ref LL_GPIO_PIN_2

+  *         @arg @ref LL_GPIO_PIN_3

+  *         @arg @ref LL_GPIO_PIN_4

+  *         @arg @ref LL_GPIO_PIN_5

+  *         @arg @ref LL_GPIO_PIN_6

+  *         @arg @ref LL_GPIO_PIN_7

+  *         @arg @ref LL_GPIO_PIN_8

+  *         @arg @ref LL_GPIO_PIN_9

+  *         @arg @ref LL_GPIO_PIN_10

+  *         @arg @ref LL_GPIO_PIN_11

+  *         @arg @ref LL_GPIO_PIN_12

+  *         @arg @ref LL_GPIO_PIN_13

+  *         @arg @ref LL_GPIO_PIN_14

+  *         @arg @ref LL_GPIO_PIN_15

+  *         @arg @ref LL_GPIO_PIN_ALL

+  * @retval None

+  */

+__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask)

+{

+  WRITE_REG(GPIOx->BSRR, PinMask << 16U);

+}

+

+/**

+  * @brief  Toggle data value for several pin of dedicated port.

+  * @rmtoll ODR          ODy           LL_GPIO_TogglePin

+  * @param  GPIOx GPIO Port

+  * @param  PinMask This parameter can be a combination of the following values:

+  *         @arg @ref LL_GPIO_PIN_0

+  *         @arg @ref LL_GPIO_PIN_1

+  *         @arg @ref LL_GPIO_PIN_2

+  *         @arg @ref LL_GPIO_PIN_3

+  *         @arg @ref LL_GPIO_PIN_4

+  *         @arg @ref LL_GPIO_PIN_5

+  *         @arg @ref LL_GPIO_PIN_6

+  *         @arg @ref LL_GPIO_PIN_7

+  *         @arg @ref LL_GPIO_PIN_8

+  *         @arg @ref LL_GPIO_PIN_9

+  *         @arg @ref LL_GPIO_PIN_10

+  *         @arg @ref LL_GPIO_PIN_11

+  *         @arg @ref LL_GPIO_PIN_12

+  *         @arg @ref LL_GPIO_PIN_13

+  *         @arg @ref LL_GPIO_PIN_14

+  *         @arg @ref LL_GPIO_PIN_15

+  *         @arg @ref LL_GPIO_PIN_ALL

+  * @retval None

+  */

+__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask)

+{

+  WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask);

+}

+

+/**

+  * @}

+  */

+

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions

+  * @{

+  */

+

+ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx);

+ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct);

+void        LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct);

+

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /*defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) || defined (GPIOK) */

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_LL_GPIO_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_hrtim.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_hrtim.h
new file mode 100644
index 0000000000..38737e397f
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_hrtim.h
@@ -0,0 +1,10479 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_hrtim.h

+  * @author  MCD Application Team

+  * @brief   Header file of HRTIM LL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_LL_HRTIM_H

+#define STM32H7xx_LL_HRTIM_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+#if defined (HRTIM1)

+

+/** @defgroup HRTIM_LL HRTIM

+  * @{

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/** @defgroup HRTIM_LL_Private_Variables HRTIM Private Variables

+  * @{

+  */

+static const uint16_t REG_OFFSET_TAB_TIMER[] =

+{

+  0x00U,   /* 0: MASTER  */

+  0x80U,   /* 1: TIMER A */

+  0x100U,  /* 2: TIMER B */

+  0x180U,  /* 3: TIMER C */

+  0x200U,  /* 4: TIMER D */

+  0x280U   /* 5: TIMER E */

+};

+

+static const uint8_t REG_OFFSET_TAB_ADCxR[] =

+{

+  0x00U,   /* 0: HRTIM_ADC1R */

+  0x04U,   /* 1: HRTIM_ADC2R */

+  0x08U,   /* 2: HRTIM_ADC3R */

+  0x0CU,   /* 3: HRTIM_ADC4R */

+};

+

+static const uint16_t REG_OFFSET_TAB_SETxR[] =

+{

+  0x00U,   /* 0: TA1 */

+  0x08U,   /* 1: TA2 */

+  0x80U,   /* 2: TB1 */

+  0x88U,   /* 3: TB2 */

+  0x100U,  /* 4: TC1 */

+  0x108U,  /* 5: TC2 */

+  0x180U,  /* 6: TD1 */

+  0x188U,  /* 7: TD2 */

+  0x200U,  /* 8: TE1 */

+  0x208U   /* 9: TE2 */

+};

+

+static const uint16_t REG_OFFSET_TAB_OUTxR[] =

+{

+  0x00U,   /*  0: TA1 */

+  0x00U,   /*  1: TA2 */

+  0x80U,   /*  2: TB1 */

+  0x80U,   /*  3: TB2 */

+  0x100U,  /*  4: TC1 */

+  0x100U,  /*  5: TC2 */

+  0x180U,  /*  6: TD1 */

+  0x180U,  /*  7: TD2 */

+  0x200U,  /*  8: TE1 */

+  0x200U   /*  9: TE2 */

+};

+

+static const uint8_t REG_OFFSET_TAB_EECR[] =

+{

+  0x00U, /* LL_HRTIM_EVENT_1 */

+  0x00U, /* LL_HRTIM_EVENT_2 */

+  0x00U, /* LL_HRTIM_EVENT_3 */

+  0x00U, /* LL_HRTIM_EVENT_4 */

+  0x00U, /* LL_HRTIM_EVENT_5 */

+  0x04U, /* LL_HRTIM_EVENT_6 */

+  0x04U, /* LL_HRTIM_EVENT_7 */

+  0x04U, /* LL_HRTIM_EVENT_8 */

+  0x04U, /* LL_HRTIM_EVENT_9 */

+  0x04U  /* LL_HRTIM_EVENT_10 */

+};

+

+static const uint8_t REG_OFFSET_TAB_FLTINR[] =

+{

+  0x00U, /* LL_HRTIM_FAULT_1 */

+  0x00U, /* LL_HRTIM_FAULT_2 */

+  0x00U, /* LL_HRTIM_FAULT_3 */

+  0x00U, /* LL_HRTIM_FAULT_4 */

+  0x04U  /* LL_HRTIM_FAULT_5 */

+};

+

+static const uint32_t REG_MASK_TAB_UPDATETRIG[] =

+{

+  0x20000000U,  /* 0: MASTER  */

+  0x01FE0000U,  /* 1: TIMER A */

+  0x01FE0000U,  /* 2: TIMER B */

+  0x01FE0000U,  /* 3: TIMER C */

+  0x01FE0000U,  /* 4: TIMER D */

+  0x01FE0000U   /* 5: TIMER E */

+};

+

+static const uint8_t REG_SHIFT_TAB_UPDATETRIG[] =

+{

+  12U, /* 0: MASTER  */

+  0U,  /* 1: TIMER A */

+  0U,  /* 2: TIMER B  */

+  0U,  /* 3: TIMER C */

+  0U,  /* 4: TIMER D  */

+  0U   /* 5: TIMER E */

+};

+

+static const uint8_t REG_SHIFT_TAB_EExSRC[] =

+{

+  0U,  /* LL_HRTIM_EVENT_1  */

+  6U,  /* LL_HRTIM_EVENT_2  */

+  12U, /* LL_HRTIM_EVENT_3  */

+  18U, /* LL_HRTIM_EVENT_4  */

+  24U, /* LL_HRTIM_EVENT_5  */

+  0U,  /* LL_HRTIM_EVENT_6  */

+  6U,  /* LL_HRTIM_EVENT_7  */

+  12U, /* LL_HRTIM_EVENT_8  */

+  18U, /* LL_HRTIM_EVENT_9  */

+  24U  /* LL_HRTIM_EVENT_10 */

+};

+

+static const uint32_t REG_MASK_TAB_UPDATEGATING[] =

+{

+  HRTIM_MCR_BRSTDMA,   /* 0: MASTER  */

+  HRTIM_TIMCR_UPDGAT,  /* 1: TIMER A */

+  HRTIM_TIMCR_UPDGAT,  /* 2: TIMER B  */

+  HRTIM_TIMCR_UPDGAT,  /* 3: TIMER C */

+  HRTIM_TIMCR_UPDGAT,  /* 4: TIMER D  */

+  HRTIM_TIMCR_UPDGAT   /* 5: TIMER E */

+};

+

+static const uint8_t REG_SHIFT_TAB_UPDATEGATING[] =

+{

+  2U, /* 0: MASTER  */

+  0U, /* 1: TIMER A */

+  0U, /* 2: TIMER B  */

+  0U, /* 3: TIMER C */

+  0U, /* 4: TIMER D  */

+  0U  /* 5: TIMER E */

+};

+

+static const uint8_t REG_SHIFT_TAB_OUTxR[] =

+{

+  0U,  /* 0: TA1  */

+  16U, /* 1: TA2 */

+  0U,  /* 2: TB1  */

+  16U, /* 3: TB2 */

+  0U,  /* 4: TC1  */

+  16U, /* 5: TC2 */

+  0U,  /* 6: TD1  */

+  16U, /* 7: TD2 */

+  0U,  /* 8: TE1  */

+  16U  /* 9: TE2 */

+};

+

+static const uint8_t REG_SHIFT_TAB_OxSTAT[] =

+{

+  0U,  /* 0: TA1  */

+  1U,  /* 1: TA2 */

+  0U,  /* 2: TB1  */

+  1U,  /* 3: TB2 */

+  0U,  /* 4: TC1  */

+  1U,  /* 5: TC2 */

+  0U,  /* 6: TD1  */

+  1U,  /* 7: TD2 */

+  0U,  /* 8: TE1  */

+  1U   /* 9: TE2 */

+};

+

+static const uint8_t REG_SHIFT_TAB_FLTxE[] =

+{

+  0U,   /* LL_HRTIM_FAULT_1 */

+  8U,   /* LL_HRTIM_FAULT_2 */

+  16U,  /* LL_HRTIM_FAULT_3 */

+  24U,  /* LL_HRTIM_FAULT_4 */

+  0U    /* LL_HRTIM_FAULT_5 */

+};

+

+/**

+  * @}

+  */

+

+

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup HRTIM_LL_Private_Constants HRTIM Private Constants

+  * @{

+  */

+#define HRTIM_CR1_UDIS_MASK   ((uint32_t)(HRTIM_CR1_MUDIS  |\

+                                          HRTIM_CR1_TAUDIS |\

+                                          HRTIM_CR1_TBUDIS |\

+                                          HRTIM_CR1_TCUDIS |\

+                                          HRTIM_CR1_TDUDIS |\

+                                          HRTIM_CR1_TEUDIS))

+

+#define HRTIM_CR2_SWUPD_MASK   ((uint32_t)(HRTIM_CR2_MSWU |\

+                                           HRTIM_CR2_TASWU |\

+                                           HRTIM_CR2_TBSWU |\

+                                           HRTIM_CR2_TCSWU |\

+                                           HRTIM_CR2_TDSWU |\

+                                           HRTIM_CR2_TESWU))

+

+#define HRTIM_CR2_SWRST_MASK   ((uint32_t)(HRTIM_CR2_MRST |\

+                                           HRTIM_CR2_TARST |\

+                                           HRTIM_CR2_TBRST |\

+                                           HRTIM_CR2_TCRST |\

+                                           HRTIM_CR2_TDRST |\

+                                           HRTIM_CR2_TERST))

+

+#define HRTIM_OENR_OEN_MASK   ((uint32_t)(HRTIM_OENR_TA1OEN |\

+                                          HRTIM_OENR_TA2OEN |\

+                                          HRTIM_OENR_TB1OEN |\

+                                          HRTIM_OENR_TB2OEN |\

+                                          HRTIM_OENR_TC1OEN |\

+                                          HRTIM_OENR_TC2OEN |\

+                                          HRTIM_OENR_TD1OEN |\

+                                          HRTIM_OENR_TD2OEN |\

+                                          HRTIM_OENR_TE1OEN |\

+                                          HRTIM_OENR_TE2OEN))

+

+#define HRTIM_OENR_ODIS_MASK  ((uint32_t)(HRTIM_ODISR_TA1ODIS  |\

+                                          HRTIM_ODISR_TA2ODIS  |\

+                                          HRTIM_ODISR_TB1ODIS  |\

+                                          HRTIM_ODISR_TB2ODIS  |\

+                                          HRTIM_ODISR_TC1ODIS  |\

+                                          HRTIM_ODISR_TC2ODIS  |\

+                                          HRTIM_ODISR_TD1ODIS  |\

+                                          HRTIM_ODISR_TD2ODIS  |\

+                                          HRTIM_ODISR_TE1ODIS  |\

+                                          HRTIM_ODISR_TE2ODIS))

+

+#define HRTIM_OUT_CONFIG_MASK  ((uint32_t)(HRTIM_OUTR_POL1   |\

+                                           HRTIM_OUTR_IDLM1  |\

+                                           HRTIM_OUTR_IDLES1 |\

+                                           HRTIM_OUTR_FAULT1 |\

+                                           HRTIM_OUTR_CHP1   |\

+                                           HRTIM_OUTR_DIDL1))

+

+#define HRTIM_EE_CONFIG_MASK   ((uint32_t)(HRTIM_EECR1_EE1SRC |\

+                                           HRTIM_EECR1_EE1POL |\

+                                           HRTIM_EECR1_EE1SNS |\

+                                           HRTIM_EECR1_EE1FAST))

+

+#define HRTIM_FLT_CONFIG_MASK   ((uint32_t)(HRTIM_FLTINR1_FLT1P |\

+                                            HRTIM_FLTINR1_FLT1SRC))

+

+#define HRTIM_BM_CONFIG_MASK   ((uint32_t)( HRTIM_BMCR_BMPRSC |\

+                                            HRTIM_BMCR_BMCLK  |\

+                                            HRTIM_BMCR_BMOM))

+

+/**

+  * @}

+  */

+

+

+/* Private macros ------------------------------------------------------------*/

+/* Exported types ------------------------------------------------------------*/

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup HRTIM_LL_Exported_Constants HRTIM Exported Constants

+  * @{

+  */

+

+/** @defgroup HRTIM_LL_EC_GET_FLAG Get Flags Defines

+  * @brief    Flags defines which can be used with LL_HRTIM_ReadReg function

+  * @{

+  */

+#define LL_HRTIM_ISR_FLT1                  HRTIM_ISR_FLT1

+#define LL_HRTIM_ISR_FLT2                  HRTIM_ISR_FLT2

+#define LL_HRTIM_ISR_FLT3                  HRTIM_ISR_FLT3

+#define LL_HRTIM_ISR_FLT4                  HRTIM_ISR_FLT4

+#define LL_HRTIM_ISR_FLT5                  HRTIM_ISR_FLT5

+#define LL_HRTIM_ISR_SYSFLT                HRTIM_ISR_SYSFLT

+#define LL_HRTIM_ISR_BMPER                 HRTIM_ISR_BMPER

+

+#define LL_HRTIM_MISR_MCMP1                HRTIM_MISR_MCMP1

+#define LL_HRTIM_MISR_MCMP2                HRTIM_MISR_MCMP2

+#define LL_HRTIM_MISR_MCMP3                HRTIM_MISR_MCMP3

+#define LL_HRTIM_MISR_MCMP4                HRTIM_MISR_MCMP4

+#define LL_HRTIM_MISR_MREP                 HRTIM_MISR_MREP

+#define LL_HRTIM_MISR_SYNC                 HRTIM_MISR_SYNC

+#define LL_HRTIM_MISR_MUPD                 HRTIM_MISR_MUPD

+

+#define LL_HRTIM_TIMISR_CMP1               HRTIM_TIMISR_CMP1

+#define LL_HRTIM_TIMISR_CMP2               HRTIM_TIMISR_CMP2

+#define LL_HRTIM_TIMISR_CMP3               HRTIM_TIMISR_CMP3

+#define LL_HRTIM_TIMISR_CMP4               HRTIM_TIMISR_CMP4

+#define LL_HRTIM_TIMISR_REP                HRTIM_TIMISR_REP

+#define LL_HRTIM_TIMISR_UPD                HRTIM_TIMISR_UPD

+#define LL_HRTIM_TIMISR_CPT1               HRTIM_TIMISR_CPT1

+#define LL_HRTIM_TIMISR_CPT2               HRTIM_TIMISR_CPT2

+#define LL_HRTIM_TIMISR_SET1               HRTIM_TIMISR_SET1

+#define LL_HRTIM_TIMISR_RST1               HRTIM_TIMISR_RST1

+#define LL_HRTIM_TIMISR_SET2               HRTIM_TIMISR_SET2

+#define LL_HRTIM_TIMISR_RST2               HRTIM_TIMISR_RST2

+#define LL_HRTIM_TIMISR_RST                HRTIM_TIMISR_RST

+#define LL_HRTIM_TIMISR_DLYPRT             HRTIM_TIMISR_DLYPRT

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_IT IT Defines

+  * @brief    IT defines which can be used with LL_HRTIM_ReadReg and LL_HRTIM_WriteReg functions

+  * @{

+  */

+#define LL_HRTIM_IER_FLT1IE                HRTIM_IER_FLT1IE

+#define LL_HRTIM_IER_FLT2IE                HRTIM_IER_FLT2IE

+#define LL_HRTIM_IER_FLT3IE                HRTIM_IER_FLT3IE

+#define LL_HRTIM_IER_FLT4IE                HRTIM_IER_FLT4IE

+#define LL_HRTIM_IER_FLT5IE                HRTIM_IER_FLT5IE

+#define LL_HRTIM_IER_SYSFLTIE              HRTIM_IER_SYSFLTIE

+#define LL_HRTIM_IER_BMPERIE               HRTIM_IER_BMPERIE

+

+#define LL_HRTIM_MDIER_MCMP1IE             HRTIM_MDIER_MCMP1IE

+#define LL_HRTIM_MDIER_MCMP2IE             HRTIM_MDIER_MCMP2IE

+#define LL_HRTIM_MDIER_MCMP3IE             HRTIM_MDIER_MCMP3IE

+#define LL_HRTIM_MDIER_MCMP4IE             HRTIM_MDIER_MCMP4IE

+#define LL_HRTIM_MDIER_MREPIE              HRTIM_MDIER_MREPIE

+#define LL_HRTIM_MDIER_SYNCIE              HRTIM_MDIER_SYNCIE

+#define LL_HRTIM_MDIER_MUPDIE              HRTIM_MDIER_MUPDIE

+

+#define LL_HRTIM_TIMDIER_CMP1IE            HRTIM_TIMDIER_CMP1IE

+#define LL_HRTIM_TIMDIER_CMP2IE            HRTIM_TIMDIER_CMP2IE

+#define LL_HRTIM_TIMDIER_CMP3IE            HRTIM_TIMDIER_CMP3IE

+#define LL_HRTIM_TIMDIER_CMP4IE            HRTIM_TIMDIER_CMP4IE

+#define LL_HRTIM_TIMDIER_REPIE             HRTIM_TIMDIER_REPIE

+#define LL_HRTIM_TIMDIER_UPDIE             HRTIM_TIMDIER_UPDIE

+#define LL_HRTIM_TIMDIER_CPT1IE            HRTIM_TIMDIER_CPT1IE

+#define LL_HRTIM_TIMDIER_CPT2IE            HRTIM_TIMDIER_CPT2IE

+#define LL_HRTIM_TIMDIER_SET1IE            HRTIM_TIMDIER_SET1IE

+#define LL_HRTIM_TIMDIER_RST1IE            HRTIM_TIMDIER_RST1IE

+#define LL_HRTIM_TIMDIER_SET2IE            HRTIM_TIMDIER_SET2IE

+#define LL_HRTIM_TIMDIER_RST2IE            HRTIM_TIMDIER_RST2IE

+#define LL_HRTIM_TIMDIER_RSTIE             HRTIM_TIMDIER_RSTIE

+#define LL_HRTIM_TIMDIER_DLYPRTIE          HRTIM_TIMDIER_DLYPRTIE

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_SYNCIN_SRC  SYNCHRONIZATION INPUT SOURCE

+  * @{

+  * @brief Constants defining defining the synchronization input source.

+  */

+#define LL_HRTIM_SYNCIN_SRC_NONE            0x00000000U                      /*!< HRTIM is not synchronized and runs in standalone mode */

+#define LL_HRTIM_SYNCIN_SRC_TIM_EVENT       (HRTIM_MCR_SYNC_IN_1)                        /*!< The HRTIM is synchronized with the on-chip timer */

+#define LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT  (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0)  /*!< A positive pulse on SYNCIN input triggers the HRTIM */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_SYNCOUT_SRC  SYNCHRONIZATION OUTPUT SOURCE

+  * @{

+  * @brief Constants defining the source and event to be sent on the synchronization output.

+  */

+#define LL_HRTIM_SYNCOUT_SRC_MASTER_START  0x00000000U                        /*!< A pulse is sent on the SYNCOUT output upon master timer start event */

+#define LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1   (HRTIM_MCR_SYNC_SRC_0)                         /*!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event*/

+#define LL_HRTIM_SYNCOUT_SRC_TIMA_START    (HRTIM_MCR_SYNC_SRC_1)                         /*!< A pulse is sent on the SYNCOUT output upon timer A start or reset events */

+#define LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1     (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0)  /*!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_SYNCOUT_POLARITY  SYNCHRONIZATION OUTPUT POLARITY

+  * @{

+  * @brief Constants defining the routing and conditioning of the synchronization output event.

+  */

+#define LL_HRTIM_SYNCOUT_DISABLED     0x00000000U                         /*!< Synchronization output event is disabled */

+#define LL_HRTIM_SYNCOUT_POSITIVE_PULSE (HRTIM_MCR_SYNC_OUT_1)                        /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */

+#define LL_HRTIM_SYNCOUT_NEGATIVE_PULSE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_TIMER  TIMER ID

+  * @{

+  * @brief Constants identifying a timing unit.

+  */

+#define LL_HRTIM_TIMER_NONE                0U   /*!< Master timer identifier */

+#define LL_HRTIM_TIMER_MASTER              HRTIM_MCR_MCEN   /*!< Master timer identifier */

+#define LL_HRTIM_TIMER_A                   HRTIM_MCR_TACEN  /*!< Timer A identifier */

+#define LL_HRTIM_TIMER_B                   HRTIM_MCR_TBCEN  /*!< Timer B identifier */

+#define LL_HRTIM_TIMER_C                   HRTIM_MCR_TCCEN  /*!< Timer C identifier */

+#define LL_HRTIM_TIMER_D                   HRTIM_MCR_TDCEN  /*!< Timer D identifier */

+#define LL_HRTIM_TIMER_E                   HRTIM_MCR_TECEN  /*!< Timer E identifier */

+#define LL_HRTIM_TIMER_X                  (HRTIM_MCR_TACEN |\

+                                           HRTIM_MCR_TBCEN | HRTIM_MCR_TCCEN |\

+                                           HRTIM_MCR_TDCEN | HRTIM_MCR_TECEN )

+#define LL_HRTIM_TIMER_ALL                (LL_HRTIM_TIMER_MASTER | LL_HRTIM_TIMER_X)

+

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_OUTPUT  OUTPUT ID

+  * @{

+  * @brief Constants identifying an HRTIM output.

+  */

+#define LL_HRTIM_OUTPUT_TA1                HRTIM_OENR_TA1OEN  /*!< Timer A - Output 1 identifier */

+#define LL_HRTIM_OUTPUT_TA2                HRTIM_OENR_TA2OEN  /*!< Timer A - Output 2 identifier */

+#define LL_HRTIM_OUTPUT_TB1                HRTIM_OENR_TB1OEN  /*!< Timer B - Output 1 identifier */

+#define LL_HRTIM_OUTPUT_TB2                HRTIM_OENR_TB2OEN  /*!< Timer B - Output 2 identifier */

+#define LL_HRTIM_OUTPUT_TC1                HRTIM_OENR_TC1OEN  /*!< Timer C - Output 1 identifier */

+#define LL_HRTIM_OUTPUT_TC2                HRTIM_OENR_TC2OEN  /*!< Timer C - Output 2 identifier */

+#define LL_HRTIM_OUTPUT_TD1                HRTIM_OENR_TD1OEN  /*!< Timer D - Output 1 identifier */

+#define LL_HRTIM_OUTPUT_TD2                HRTIM_OENR_TD2OEN  /*!< Timer D - Output 2 identifier */

+#define LL_HRTIM_OUTPUT_TE1                HRTIM_OENR_TE1OEN  /*!< Timer E - Output 1 identifier */

+#define LL_HRTIM_OUTPUT_TE2                HRTIM_OENR_TE2OEN  /*!< Timer E - Output 2 identifier */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_COMPAREUNIT  COMPARE UNIT ID

+  * @{

+  * @brief Constants identifying a compare unit.

+  */

+#define LL_HRTIM_COMPAREUNIT_2             HRTIM_TIMCR_DELCMP2  /*!< Compare unit 2 identifier */

+#define LL_HRTIM_COMPAREUNIT_4             HRTIM_TIMCR_DELCMP4  /*!< Compare unit 4 identifier */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_CAPTUREUNIT  CAPTURE UNIT ID

+  * @{

+  * @brief Constants identifying a capture unit.

+  */

+#define LL_HRTIM_CAPTUREUNIT_1             0  /*!< Capture unit 1 identifier */

+#define LL_HRTIM_CAPTUREUNIT_2             1  /*!< Capture unit 2 identifier */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_FAULT  FAULT ID

+  * @{

+  * @brief Constants identifying a fault channel.

+  */

+#define LL_HRTIM_FAULT_1      HRTIM_FLTR_FLT1EN     /*!< Fault channel 1 identifier */

+#define LL_HRTIM_FAULT_2      HRTIM_FLTR_FLT2EN     /*!< Fault channel 2 identifier */

+#define LL_HRTIM_FAULT_3      HRTIM_FLTR_FLT3EN     /*!< Fault channel 3 identifier */

+#define LL_HRTIM_FAULT_4      HRTIM_FLTR_FLT4EN     /*!< Fault channel 4 identifier */

+#define LL_HRTIM_FAULT_5      HRTIM_FLTR_FLT5EN     /*!< Fault channel 5 identifier */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_EVENT  EXTERNAL EVENT ID

+  * @{

+  * @brief Constants identifying an external event channel.

+  */

+#define LL_HRTIM_EVENT_1        ((uint32_t)0x00000001U)     /*!< External event channel 1 identifier */

+#define LL_HRTIM_EVENT_2        ((uint32_t)0x00000002U)     /*!< External event channel 2 identifier */

+#define LL_HRTIM_EVENT_3        ((uint32_t)0x00000004U)     /*!< External event channel 3 identifier */

+#define LL_HRTIM_EVENT_4        ((uint32_t)0x00000008U)     /*!< External event channel 4 identifier */

+#define LL_HRTIM_EVENT_5        ((uint32_t)0x00000010U)     /*!< External event channel 5 identifier */

+#define LL_HRTIM_EVENT_6        ((uint32_t)0x00000020U)     /*!< External event channel 6 identifier */

+#define LL_HRTIM_EVENT_7        ((uint32_t)0x00000040U)     /*!< External event channel 7 identifier */

+#define LL_HRTIM_EVENT_8        ((uint32_t)0x00000080U)     /*!< External event channel 8 identifier */

+#define LL_HRTIM_EVENT_9        ((uint32_t)0x00000100U)     /*!< External event channel 9 identifier */

+#define LL_HRTIM_EVENT_10       ((uint32_t)0x00000200U)     /*!< External event channel 10 identifier */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_OUTPUTSTATE  OUTPUT STATE

+  * @{

+  * @brief Constants defining the state of an HRTIM output.

+  */

+#define LL_HRTIM_OUTPUTSTATE_IDLE          ((uint32_t)0x00000001U) /*!< Main operating mode, where the output can take the active or inactive level as programmed in the crossbar unit */

+#define LL_HRTIM_OUTPUTSTATE_RUN           ((uint32_t)0x00000002U) /*!< Default operating state (e.g. after an HRTIM reset, when the outputs are disabled by software or during a burst mode operation) */

+#define LL_HRTIM_OUTPUTSTATE_FAULT         ((uint32_t)0x00000003U) /*!< Safety state, entered in case of a shut-down request on FAULTx inputs */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_ADCTRIG  ADC TRIGGER

+  * @{

+  * @brief Constants identifying an ADC trigger.

+  */

+#define LL_HRTIM_ADCTRIG_1              ((uint32_t)0x00000000U) /*!< ADC trigger 1 identifier */

+#define LL_HRTIM_ADCTRIG_2              ((uint32_t)0x00000001U)  /*!< ADC trigger 2 identifier */

+#define LL_HRTIM_ADCTRIG_3              ((uint32_t)0x00000002U)  /*!< ADC trigger 3 identifier */

+#define LL_HRTIM_ADCTRIG_4              ((uint32_t)0x00000003U)  /*!< ADC trigger 4 identifier */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_ADCTRIG_UPDATE ADC TRIGGER UPDATE

+  * @{

+  * @brief constants defining the source triggering the update of the HRTIM_ADCxR register (transfer from preload to active register).

+  */

+#define LL_HRTIM_ADCTRIG_UPDATE_MASTER  0x00000000U                       /*!< HRTIM_ADCxR register update is triggered by the Master timer */

+#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_A (HRTIM_CR1_ADC1USRC_0)                        /*!< HRTIM_ADCxR register update is triggered by the Timer A */

+#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_B (HRTIM_CR1_ADC1USRC_1)                        /*!< HRTIM_ADCxR register update is triggered by the Timer B */

+#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< HRTIM_ADCxR register update is triggered by the Timer C */

+#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_D (HRTIM_CR1_ADC1USRC_2)                        /*!< HRTIM_ADCxR register update is triggered by the Timer D */

+#define LL_HRTIM_ADCTRIG_UPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< HRTIM_ADCxR register update is triggered by the Timer E */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_ADCTRIG_SRC13  ADC TRIGGER 1/3 SOURCE

+  * @{

+  * @brief constants defining the events triggering ADC conversion for ADC Triggers 1 and 3.

+  */

+#define LL_HRTIM_ADCTRIG_SRC13_NONE           0x00000000U              /*!< No ADC trigger event */

+#define LL_HRTIM_ADCTRIG_SRC13_MCMP1          HRTIM_ADC1R_AD1MC1       /*!< ADC Trigger on master compare 1 */

+#define LL_HRTIM_ADCTRIG_SRC13_MCMP2          HRTIM_ADC1R_AD1MC2       /*!< ADC Trigger on master compare 2 */

+#define LL_HRTIM_ADCTRIG_SRC13_MCMP3          HRTIM_ADC1R_AD1MC3       /*!< ADC Trigger on master compare 3 */

+#define LL_HRTIM_ADCTRIG_SRC13_MCMP4          HRTIM_ADC1R_AD1MC4       /*!< ADC Trigger on master compare 4 */

+#define LL_HRTIM_ADCTRIG_SRC13_MPER           HRTIM_ADC1R_AD1MPER      /*!< ADC Trigger on master period */

+#define LL_HRTIM_ADCTRIG_SRC13_EEV1           HRTIM_ADC1R_AD1EEV1      /*!< ADC Trigger on external event 1 */

+#define LL_HRTIM_ADCTRIG_SRC13_EEV2           HRTIM_ADC1R_AD1EEV2      /*!< ADC Trigger on external event 2 */

+#define LL_HRTIM_ADCTRIG_SRC13_EEV3           HRTIM_ADC1R_AD1EEV3      /*!< ADC Trigger on external event 3 */

+#define LL_HRTIM_ADCTRIG_SRC13_EEV4           HRTIM_ADC1R_AD1EEV4      /*!< ADC Trigger on external event 4 */

+#define LL_HRTIM_ADCTRIG_SRC13_EEV5           HRTIM_ADC1R_AD1EEV5      /*!< ADC Trigger on external event 5 */

+#define LL_HRTIM_ADCTRIG_SRC13_TIMACMP2       HRTIM_ADC1R_AD1TAC2      /*!< ADC Trigger on Timer A compare 2 */

+#define LL_HRTIM_ADCTRIG_SRC13_TIMACMP3       HRTIM_ADC1R_AD1TAC3      /*!< ADC Trigger on Timer A compare 3 */

+#define LL_HRTIM_ADCTRIG_SRC13_TIMACMP4       HRTIM_ADC1R_AD1TAC4      /*!< ADC Trigger on Timer A compare 4 */

+#define LL_HRTIM_ADCTRIG_SRC13_TIMAPER        HRTIM_ADC1R_AD1TAPER     /*!< ADC Trigger on Timer A period */

+#define LL_HRTIM_ADCTRIG_SRC13_TIMARST        HRTIM_ADC1R_AD1TARST     /*!< ADC Trigger on Timer A reset */

+#define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2       HRTIM_ADC1R_AD1TBC2      /*!< ADC Trigger on Timer B compare 2 */

+#define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3       HRTIM_ADC1R_AD1TBC3      /*!< ADC Trigger on Timer B compare 3 */

+#define LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4       HRTIM_ADC1R_AD1TBC4      /*!< ADC Trigger on Timer B compare 4 */

+#define LL_HRTIM_ADCTRIG_SRC13_TIMBPER        HRTIM_ADC1R_AD1TBPER     /*!< ADC Trigger on Timer B period */

+#define LL_HRTIM_ADCTRIG_SRC13_TIMBRST        HRTIM_ADC1R_AD1TBRST     /*!< ADC Trigger on Timer B reset */

+#define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2       HRTIM_ADC1R_AD1TCC2      /*!< ADC Trigger on Timer C compare 2 */

+#define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3       HRTIM_ADC1R_AD1TCC3      /*!< ADC Trigger on Timer C compare 3 */

+#define LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4       HRTIM_ADC1R_AD1TCC4      /*!< ADC Trigger on Timer C compare 4 */

+#define LL_HRTIM_ADCTRIG_SRC13_TIMCPER        HRTIM_ADC1R_AD1TCPER     /*!< ADC Trigger on Timer C period */

+#define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2       HRTIM_ADC1R_AD1TDC2      /*!< ADC Trigger on Timer D compare 2 */

+#define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3       HRTIM_ADC1R_AD1TDC3      /*!< ADC Trigger on Timer D compare 3 */

+#define LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4       HRTIM_ADC1R_AD1TDC4      /*!< ADC Trigger on Timer D compare 4 */

+#define LL_HRTIM_ADCTRIG_SRC13_TIMDPER        HRTIM_ADC1R_AD1TDPER     /*!< ADC Trigger on Timer D period */

+#define LL_HRTIM_ADCTRIG_SRC13_TIMECMP2       HRTIM_ADC1R_AD1TEC2      /*!< ADC Trigger on Timer E compare 2 */

+#define LL_HRTIM_ADCTRIG_SRC13_TIMECMP3       HRTIM_ADC1R_AD1TEC3      /*!< ADC Trigger on Timer E compare 3 */

+#define LL_HRTIM_ADCTRIG_SRC13_TIMECMP4       HRTIM_ADC1R_AD1TEC4      /*!< ADC Trigger on Timer E compare 4 */

+#define LL_HRTIM_ADCTRIG_SRC13_TIMEPER        HRTIM_ADC1R_AD1TEPER     /*!< ADC Trigger on Timer E period */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_ADCTRIG_SRC24  ADC TRIGGER 2/4 SOURCE

+  * @{

+  * @brief constants defining the events triggering ADC conversion for ADC Triggers 2 and 4.

+  */

+#define LL_HRTIM_ADCTRIG_SRC24_NONE           0x00000000U            /*!< No ADC trigger event */

+#define LL_HRTIM_ADCTRIG_SRC24_MCMP1          HRTIM_ADC2R_AD2MC1     /*!< ADC Trigger on master compare 1 */

+#define LL_HRTIM_ADCTRIG_SRC24_MCMP2          HRTIM_ADC2R_AD2MC2     /*!< ADC Trigger on master compare 2 */

+#define LL_HRTIM_ADCTRIG_SRC24_MCMP3          HRTIM_ADC2R_AD2MC3     /*!< ADC Trigger on master compare 3 */

+#define LL_HRTIM_ADCTRIG_SRC24_MCMP4          HRTIM_ADC2R_AD2MC4     /*!< ADC Trigger on master compare 4 */

+#define LL_HRTIM_ADCTRIG_SRC24_MPER           HRTIM_ADC2R_AD2MPER    /*!< ADC Trigger on master period */

+#define LL_HRTIM_ADCTRIG_SRC24_EEV6           HRTIM_ADC2R_AD2EEV6    /*!< ADC Trigger on external event 6 */

+#define LL_HRTIM_ADCTRIG_SRC24_EEV7           HRTIM_ADC2R_AD2EEV7    /*!< ADC Trigger on external event 7 */

+#define LL_HRTIM_ADCTRIG_SRC24_EEV8           HRTIM_ADC2R_AD2EEV8    /*!< ADC Trigger on external event 8 */

+#define LL_HRTIM_ADCTRIG_SRC24_EEV9           HRTIM_ADC2R_AD2EEV9    /*!< ADC Trigger on external event 9 */

+#define LL_HRTIM_ADCTRIG_SRC24_EEV10          HRTIM_ADC2R_AD2EEV10   /*!< ADC Trigger on external event 10 */

+#define LL_HRTIM_ADCTRIG_SRC24_TIMACMP2       HRTIM_ADC2R_AD2TAC2    /*!< ADC Trigger on Timer A compare 2 */

+#define LL_HRTIM_ADCTRIG_SRC24_TIMACMP3       HRTIM_ADC2R_AD2TAC3    /*!< ADC Trigger on Timer A compare 3 */

+#define LL_HRTIM_ADCTRIG_SRC24_TIMACMP4       HRTIM_ADC2R_AD2TAC4    /*!< ADC Trigger on Timer A compare 4 */

+#define LL_HRTIM_ADCTRIG_SRC24_TIMAPER        HRTIM_ADC2R_AD2TAPER   /*!< ADC Trigger on Timer A period */

+#define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2       HRTIM_ADC2R_AD2TBC2    /*!< ADC Trigger on Timer B compare 2 */

+#define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3       HRTIM_ADC2R_AD2TBC3    /*!< ADC Trigger on Timer B compare 3 */

+#define LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4       HRTIM_ADC2R_AD2TBC4    /*!< ADC Trigger on Timer B compare 4 */

+#define LL_HRTIM_ADCTRIG_SRC24_TIMBPER        HRTIM_ADC2R_AD2TBPER   /*!< ADC Trigger on Timer B period */

+#define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2       HRTIM_ADC2R_AD2TCC2    /*!< ADC Trigger on Timer C compare 2 */

+#define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3       HRTIM_ADC2R_AD2TCC3    /*!< ADC Trigger on Timer C compare 3 */

+#define LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4       HRTIM_ADC2R_AD2TCC4    /*!< ADC Trigger on Timer C compare 4 */

+#define LL_HRTIM_ADCTRIG_SRC24_TIMCPER        HRTIM_ADC2R_AD2TCPER   /*!< ADC Trigger on Timer C period */

+#define LL_HRTIM_ADCTRIG_SRC24_TIMCRST        HRTIM_ADC2R_AD2TCRST   /*!< ADC Trigger on Timer C reset */

+#define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2       HRTIM_ADC2R_AD2TDC2    /*!< ADC Trigger on Timer D compare 2 */

+#define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3       HRTIM_ADC2R_AD2TDC3    /*!< ADC Trigger on Timer D compare 3 */

+#define LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4       HRTIM_ADC2R_AD2TDC4    /*!< ADC Trigger on Timer D compare 4 */

+#define LL_HRTIM_ADCTRIG_SRC24_TIMDPER        HRTIM_ADC2R_AD2TDPER   /*!< ADC Trigger on Timer D period */

+#define LL_HRTIM_ADCTRIG_SRC24_TIMDRST        HRTIM_ADC2R_AD2TDRST   /*!< ADC Trigger on Timer D reset */

+#define LL_HRTIM_ADCTRIG_SRC24_TIMECMP2       HRTIM_ADC2R_AD2TEC2    /*!< ADC Trigger on Timer E compare 2 */

+#define LL_HRTIM_ADCTRIG_SRC24_TIMECMP3       HRTIM_ADC2R_AD2TEC3    /*!< ADC Trigger on Timer E compare 3 */

+#define LL_HRTIM_ADCTRIG_SRC24_TIMECMP4       HRTIM_ADC2R_AD2TEC4    /*!< ADC Trigger on Timer E compare 4 */

+#define LL_HRTIM_ADCTRIG_SRC24_TIMERST        HRTIM_ADC2R_AD2TERST   /*!< ADC Trigger on Timer E reset */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_PRESCALERRATIO  PRESCALER RATIO

+  * @{

+  * @brief Constants defining timer high-resolution clock prescaler ratio.

+  */

+#define LL_HRTIM_PRESCALERRATIO_DIV1       ((uint32_t)0x00000005U)  /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)      */

+#define LL_HRTIM_PRESCALERRATIO_DIV2       ((uint32_t)0x00000006U)  /*!< fHRCK: fHRTIM / 2 = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)      */

+#define LL_HRTIM_PRESCALERRATIO_DIV4       ((uint32_t)0x00000007U)  /*!< fHRCK: fHRTIM / 4 = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)      */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_MODE  COUNTER MODE

+  * @{

+  * @brief Constants defining timer counter operating mode.

+  */

+#define LL_HRTIM_MODE_CONTINUOUS           ((uint32_t)0x00000008U)  /*!< The timer operates in continuous (free-running) mode */

+#define LL_HRTIM_MODE_SINGLESHOT           0x00000000U              /*!< The timer operates in non retriggerable single-shot mode */

+#define LL_HRTIM_MODE_RETRIGGERABLE        ((uint32_t)0x00000010U)  /*!< The timer operates in retriggerable single-shot mode */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_DACTRIG  DAC TRIGGER

+  * @{

+  * @brief Constants defining on which output the DAC synchronization event is sent.

+  */

+#define LL_HRTIM_DACTRIG_NONE           0x00000000U                     /*!< No DAC synchronization event generated */

+#define LL_HRTIM_DACTRIG_DACTRIGOUT_1   (HRTIM_MCR_DACSYNC_0)                       /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */

+#define LL_HRTIM_DACTRIG_DACTRIGOUT_2   (HRTIM_MCR_DACSYNC_1)                       /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */

+#define LL_HRTIM_DACTRIG_DACTRIGOUT_3   (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut3 output upon timer update */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_UPDATETRIG  UPDATE TRIGGER

+  * @{

+  * @brief Constants defining whether the registers update is done synchronously with any other timer or master update.

+  */

+#define LL_HRTIM_UPDATETRIG_NONE        0x00000000U            /*!< Register update is disabled */

+#define LL_HRTIM_UPDATETRIG_MASTER      HRTIM_TIMCR_MSTU       /*!< Register update is triggered by the master timer update */

+#define LL_HRTIM_UPDATETRIG_TIMER_A     HRTIM_TIMCR_TAU        /*!< Register update is triggered by the timer A update */

+#define LL_HRTIM_UPDATETRIG_TIMER_B     HRTIM_TIMCR_TBU        /*!< Register update is triggered by the timer B update */

+#define LL_HRTIM_UPDATETRIG_TIMER_C     HRTIM_TIMCR_TCU        /*!< Register update is triggered by the timer C update*/

+#define LL_HRTIM_UPDATETRIG_TIMER_D     HRTIM_TIMCR_TDU        /*!< Register update is triggered by the timer D update */

+#define LL_HRTIM_UPDATETRIG_TIMER_E     HRTIM_TIMCR_TEU        /*!< Register update is triggered by the timer E update */

+#define LL_HRTIM_UPDATETRIG_REPETITION  HRTIM_TIMCR_TREPU      /*!< Register update is triggered when the counter rolls over and HRTIM_REPx = 0*/

+#define LL_HRTIM_UPDATETRIG_RESET       HRTIM_TIMCR_TRSTU      /*!< Register update is triggered by counter reset or roll-over to 0 after reaching the period value in continuous mode */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_UPDATEGATING  UPDATE GATING

+  * @{

+  * @brief Constants defining how the update occurs relatively to the burst DMA transaction and the external update request on update enable inputs 1 to 3.

+  */

+#define LL_HRTIM_UPDATEGATING_INDEPENDENT     0x00000000U                                               /*!< Update done independently from the DMA burst transfer completion */

+#define LL_HRTIM_UPDATEGATING_DMABURST        (HRTIM_TIMCR_UPDGAT_0)                                                /*!< Update done when the DMA burst transfer is completed */

+#define LL_HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1)                                                /*!< Update done on timer roll-over following a DMA burst transfer completion*/

+#define LL_HRTIM_UPDATEGATING_UPDEN1          (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)                         /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1 */

+#define LL_HRTIM_UPDATEGATING_UPDEN2          (HRTIM_TIMCR_UPDGAT_2)                                                /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2 */

+#define LL_HRTIM_UPDATEGATING_UPDEN3          (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0)                         /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3 */

+#define LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE   (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1)                         /*!< Slave timer only -  Update done on the update event following a rising edge of HRTIM update enable input 1 */

+#define LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE   (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0)  /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2 */

+#define LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE   (HRTIM_TIMCR_UPDGAT_3)                                                /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3 */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_COMPAREMODE  COMPARE MODE

+  * @{

+  * @brief Constants defining whether the compare register is behaving in regular mode (compare match issued as soon as counter equal compare) or in auto-delayed mode.

+  */

+#define LL_HRTIM_COMPAREMODE_REGULAR          0x00000000U                         /*!< standard compare mode */

+#define LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT  (HRTIM_TIMCR_DELCMP2_0)                         /*!< Compare event generated only if a capture has occurred */

+#define LL_HRTIM_COMPAREMODE_DELAY_CMP1       (HRTIM_TIMCR_DELCMP2_1)                         /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */

+#define LL_HRTIM_COMPAREMODE_DELAY_CMP3       (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_RESETTRIG  RESET TRIGGER

+  * @{

+  * @brief Constants defining the events that can be selected to trigger the reset of the timer counter.

+  */

+#define LL_HRTIM_RESETTRIG_NONE        0x00000000U            /*!< No counter reset trigger */

+#define LL_HRTIM_RESETTRIG_UPDATE      HRTIM_RSTR_UPDATE      /*!< The timer counter is reset upon update event */

+#define LL_HRTIM_RESETTRIG_CMP2        HRTIM_RSTR_CMP2        /*!< The timer counter is reset upon Timer Compare 2 event */

+#define LL_HRTIM_RESETTRIG_CMP4        HRTIM_RSTR_CMP4        /*!< The timer counter is reset upon Timer Compare 4 event */

+#define LL_HRTIM_RESETTRIG_MASTER_PER  HRTIM_RSTR_MSTPER      /*!< The timer counter is reset upon master timer period event */

+#define LL_HRTIM_RESETTRIG_MASTER_CMP1 HRTIM_RSTR_MSTCMP1     /*!< The timer counter is reset upon master timer Compare 1 event */

+#define LL_HRTIM_RESETTRIG_MASTER_CMP2 HRTIM_RSTR_MSTCMP2     /*!< The timer counter is reset upon master timer Compare 2 event */

+#define LL_HRTIM_RESETTRIG_MASTER_CMP3 HRTIM_RSTR_MSTCMP3     /*!< The timer counter is reset upon master timer Compare 3 event */

+#define LL_HRTIM_RESETTRIG_MASTER_CMP4 HRTIM_RSTR_MSTCMP4     /*!< The timer counter is reset upon master timer Compare 4 event */

+#define LL_HRTIM_RESETTRIG_EEV_1       HRTIM_RSTR_EXTEVNT1    /*!< The timer counter is reset upon external event 1 */

+#define LL_HRTIM_RESETTRIG_EEV_2       HRTIM_RSTR_EXTEVNT2    /*!< The timer counter is reset upon external event 2 */

+#define LL_HRTIM_RESETTRIG_EEV_3       HRTIM_RSTR_EXTEVNT3    /*!< The timer counter is reset upon external event 3 */

+#define LL_HRTIM_RESETTRIG_EEV_4       HRTIM_RSTR_EXTEVNT4    /*!< The timer counter is reset upon external event 4 */

+#define LL_HRTIM_RESETTRIG_EEV_5       HRTIM_RSTR_EXTEVNT5    /*!< The timer counter is reset upon external event 5 */

+#define LL_HRTIM_RESETTRIG_EEV_6       HRTIM_RSTR_EXTEVNT6    /*!< The timer counter is reset upon external event 6 */

+#define LL_HRTIM_RESETTRIG_EEV_7       HRTIM_RSTR_EXTEVNT7    /*!< The timer counter is reset upon external event 7 */

+#define LL_HRTIM_RESETTRIG_EEV_8       HRTIM_RSTR_EXTEVNT8    /*!< The timer counter is reset upon external event 8 */

+#define LL_HRTIM_RESETTRIG_EEV_9       HRTIM_RSTR_EXTEVNT9    /*!< The timer counter is reset upon external event 9 */

+#define LL_HRTIM_RESETTRIG_EEV_10      HRTIM_RSTR_EXTEVNT10   /*!< The timer counter is reset upon external event 10 */

+#define LL_HRTIM_RESETTRIG_OTHER1_CMP1 HRTIM_RSTR_TIMBCMP1    /*!< The timer counter is reset upon other timer Compare 1 event */

+#define LL_HRTIM_RESETTRIG_OTHER1_CMP2 HRTIM_RSTR_TIMBCMP2    /*!< The timer counter is reset upon other timer Compare 2 event */

+#define LL_HRTIM_RESETTRIG_OTHER1_CMP4 HRTIM_RSTR_TIMBCMP4    /*!< The timer counter is reset upon other timer Compare 4 event */

+#define LL_HRTIM_RESETTRIG_OTHER2_CMP1 HRTIM_RSTR_TIMCCMP1    /*!< The timer counter is reset upon other timer Compare 1 event */

+#define LL_HRTIM_RESETTRIG_OTHER2_CMP2 HRTIM_RSTR_TIMCCMP2    /*!< The timer counter is reset upon other timer Compare 2 event */

+#define LL_HRTIM_RESETTRIG_OTHER2_CMP4 HRTIM_RSTR_TIMCCMP4    /*!< The timer counter is reset upon other timer Compare 4 event */

+#define LL_HRTIM_RESETTRIG_OTHER3_CMP1 HRTIM_RSTR_TIMDCMP1    /*!< The timer counter is reset upon other timer Compare 1 event */

+#define LL_HRTIM_RESETTRIG_OTHER3_CMP2 HRTIM_RSTR_TIMDCMP2    /*!< The timer counter is reset upon other timer Compare 2 event */

+#define LL_HRTIM_RESETTRIG_OTHER3_CMP4 HRTIM_RSTR_TIMDCMP4    /*!< The timer counter is reset upon other timer Compare 4 event */

+#define LL_HRTIM_RESETTRIG_OTHER4_CMP1 HRTIM_RSTR_TIMECMP1    /*!< The timer counter is reset upon other timer Compare 1 event */

+#define LL_HRTIM_RESETTRIG_OTHER4_CMP2 HRTIM_RSTR_TIMECMP2    /*!< The timer counter is reset upon other timer Compare 2 event */

+#define LL_HRTIM_RESETTRIG_OTHER4_CMP4 HRTIM_RSTR_TIMECMP4    /*!< The timer counter is reset upon other timer Compare 4 event */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_CAPTURETRIG  CAPTURE TRIGGER

+  * @{

+  * @brief Constants defining the events that can be selected to trigger the capture of the timing unit counter.

+  */

+#define LL_HRTIM_CAPTURETRIG_NONE         ((uint32_t)0x00000000U)/*!< Capture trigger is disabled */

+#define LL_HRTIM_CAPTURETRIG_UPDATE       HRTIM_CPT1CR_UPDCPT    /*!< The update event triggers the Capture */

+#define LL_HRTIM_CAPTURETRIG_EEV_1        HRTIM_CPT1CR_EXEV1CPT  /*!< The External event 1 triggers the Capture */

+#define LL_HRTIM_CAPTURETRIG_EEV_2        HRTIM_CPT1CR_EXEV2CPT  /*!< The External event 2 triggers the Capture */

+#define LL_HRTIM_CAPTURETRIG_EEV_3        HRTIM_CPT1CR_EXEV3CPT  /*!< The External event 3 triggers the Capture */

+#define LL_HRTIM_CAPTURETRIG_EEV_4        HRTIM_CPT1CR_EXEV4CPT  /*!< The External event 4 triggers the Capture */

+#define LL_HRTIM_CAPTURETRIG_EEV_5        HRTIM_CPT1CR_EXEV5CPT  /*!< The External event 5 triggers the Capture */

+#define LL_HRTIM_CAPTURETRIG_EEV_6        HRTIM_CPT1CR_EXEV6CPT  /*!< The External event 6 triggers the Capture */

+#define LL_HRTIM_CAPTURETRIG_EEV_7        HRTIM_CPT1CR_EXEV7CPT  /*!< The External event 7 triggers the Capture */

+#define LL_HRTIM_CAPTURETRIG_EEV_8        HRTIM_CPT1CR_EXEV8CPT  /*!< The External event 8 triggers the Capture */

+#define LL_HRTIM_CAPTURETRIG_EEV_9        HRTIM_CPT1CR_EXEV9CPT  /*!< The External event 9 triggers the Capture */

+#define LL_HRTIM_CAPTURETRIG_EEV_10       HRTIM_CPT1CR_EXEV10CPT /*!< The External event 10 triggers the Capture */

+#define LL_HRTIM_CAPTURETRIG_TA1_SET      HRTIM_CPT1CR_TA1SET    /*!< Capture is triggered by TA1 output inactive to active transition */

+#define LL_HRTIM_CAPTURETRIG_TA1_RESET    HRTIM_CPT1CR_TA1RST    /*!< Capture is triggered by TA1 output active to inactive transition */

+#define LL_HRTIM_CAPTURETRIG_TIMA_CMP1    HRTIM_CPT1CR_TIMACMP1  /*!< Timer A Compare 1 triggers Capture */

+#define LL_HRTIM_CAPTURETRIG_TIMA_CMP2    HRTIM_CPT1CR_TIMACMP2  /*!< Timer A Compare 2 triggers Capture */

+#define LL_HRTIM_CAPTURETRIG_TB1_SET      HRTIM_CPT1CR_TB1SET    /*!< Capture is triggered by TB1 output inactive to active transition */

+#define LL_HRTIM_CAPTURETRIG_TB1_RESET    HRTIM_CPT1CR_TB1RST    /*!< Capture is triggered by TB1 output active to inactive transition */

+#define LL_HRTIM_CAPTURETRIG_TIMB_CMP1    HRTIM_CPT1CR_TIMBCMP1  /*!< Timer B Compare 1 triggers Capture */

+#define LL_HRTIM_CAPTURETRIG_TIMB_CMP2    HRTIM_CPT1CR_TIMBCMP2  /*!< Timer B Compare 2 triggers Capture */

+#define LL_HRTIM_CAPTURETRIG_TC1_SET      HRTIM_CPT1CR_TC1SET    /*!< Capture is triggered by TC1 output inactive to active transition */

+#define LL_HRTIM_CAPTURETRIG_TC1_RESET    HRTIM_CPT1CR_TC1RST    /*!< Capture is triggered by TC1 output active to inactive transition */

+#define LL_HRTIM_CAPTURETRIG_TIMC_CMP1    HRTIM_CPT1CR_TIMCCMP1  /*!< Timer C Compare 1 triggers Capture */

+#define LL_HRTIM_CAPTURETRIG_TIMC_CMP2    HRTIM_CPT1CR_TIMCCMP2  /*!< Timer C Compare 2 triggers Capture */

+#define LL_HRTIM_CAPTURETRIG_TD1_SET      HRTIM_CPT1CR_TD1SET    /*!< Capture is triggered by TD1 output inactive to active transition */

+#define LL_HRTIM_CAPTURETRIG_TD1_RESET    HRTIM_CPT1CR_TD1RST    /*!< Capture is triggered by TD1 output active to inactive transition */

+#define LL_HRTIM_CAPTURETRIG_TIMD_CMP1    HRTIM_CPT1CR_TIMDCMP1  /*!< Timer D Compare 1 triggers Capture */

+#define LL_HRTIM_CAPTURETRIG_TIMD_CMP2    HRTIM_CPT1CR_TIMDCMP2  /*!< Timer D Compare 2 triggers Capture */

+#define LL_HRTIM_CAPTURETRIG_TE1_SET      HRTIM_CPT1CR_TE1SET    /*!< Capture is triggered by TE1 output inactive to active transition */

+#define LL_HRTIM_CAPTURETRIG_TE1_RESET    HRTIM_CPT1CR_TE1RST    /*!< Capture is triggered by TE1 output active to inactive transition */

+#define LL_HRTIM_CAPTURETRIG_TIME_CMP1    HRTIM_CPT1CR_TIMECMP1  /*!< Timer E Compare 1 triggers Capture */

+#define LL_HRTIM_CAPTURETRIG_TIME_CMP2    HRTIM_CPT1CR_TIMECMP2  /*!< Timer E Compare 2 triggers Capture */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_DLYPRT  DELAYED PROTECTION (DLYPRT) MODE

+  * @{

+  * @brief Constants defining all possible delayed protection modes for a timer (also define the source and outputs on which the delayed protection schemes are applied).

+  */

+#define LL_HRTIM_DLYPRT_DELAYOUT1_EEV6  0x00000000U                                            /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6 */

+#define LL_HRTIM_DLYPRT_DELAYOUT2_EEV6  (HRTIM_OUTR_DLYPRT_0)                                             /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6 */

+#define LL_HRTIM_DLYPRT_DELAYBOTH_EEV6  (HRTIM_OUTR_DLYPRT_1)                                             /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6 */

+#define LL_HRTIM_DLYPRT_BALANCED_EEV6   (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0)                       /*!< Timers A, B, C: Balanced Idle on external Event 6 */

+#define LL_HRTIM_DLYPRT_DELAYOUT1_EEV7  (HRTIM_OUTR_DLYPRT_2)                                             /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7 */

+#define LL_HRTIM_DLYPRT_DELAYOUT2_EEV7  (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0)                       /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7 */

+#define LL_HRTIM_DLYPRT_DELAYBOTH_EEV7  (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1)                       /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7 */

+#define LL_HRTIM_DLYPRT_BALANCED_EEV7   (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0) /*!< Timers A, B, C: Balanced Idle on external Event 7 */

+

+#define LL_HRTIM_DLYPRT_DELAYOUT1_EEV8  0x00000000U                                             /*!< Timers D, E: Output 1 delayed Idle on external Event 8 */

+#define LL_HRTIM_DLYPRT_DELAYOUT2_EEV8  (HRTIM_OUTR_DLYPRT_0)                                               /*!< Timers D, E: Output 2 delayed Idle on external Event 8 */

+#define LL_HRTIM_DLYPRT_DELAYBOTH_EEV8  (HRTIM_OUTR_DLYPRT_1)                                               /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 8 */

+#define LL_HRTIM_DLYPRT_BALANCED_EEV8   (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0)                         /*!< Timers D, E: Balanced Idle on external Event 8 */

+#define LL_HRTIM_DLYPRT_DELAYOUT1_EEV9  (HRTIM_OUTR_DLYPRT_2)                                               /*!< Timers D, E: Output 1 delayed Idle on external Event 9 */

+#define LL_HRTIM_DLYPRT_DELAYOUT2_EEV9  (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0)                         /*!< Timers D, E: Output 2 delayed Idle on external Event 9 */

+#define LL_HRTIM_DLYPRT_DELAYBOTH_EEV9  (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1)                         /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 9 */

+#define LL_HRTIM_DLYPRT_BALANCED_EEV9   (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0)   /*!< Timers D, E: Balanced Idle on external Event 9 */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_BURSTMODE  BURST MODE

+  * @{

+  * @brief Constants defining how the timer behaves during a burst mode operation.

+  */

+#define LL_HRTIM_BURSTMODE_MAINTAINCLOCK (uint32_t)0x000000 /*!< Timer counter clock is maintained and the timer operates normally */

+#define LL_HRTIM_BURSTMODE_RESETCOUNTER  (HRTIM_BMCR_MTBM)  /*!< Timer counter clock is stopped and the counter is reset */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_BURSTDMA  BURST DMA

+  * @{

+  * @brief Constants defining the registers that can be written during a burst DMA operation.

+  */

+#define LL_HRTIM_BURSTDMA_NONE     0x00000000U               /*!< No register is updated by Burst DMA accesses */

+#define LL_HRTIM_BURSTDMA_MCR      (HRTIM_BDMUPR_MCR)        /*!< MCR  register is updated by Burst DMA accesses */

+#define LL_HRTIM_BURSTDMA_MICR     (HRTIM_BDMUPR_MICR)       /*!< MICR register is updated by Burst DMA accesses */

+#define LL_HRTIM_BURSTDMA_MDIER    (HRTIM_BDMUPR_MDIER)      /*!< MDIER register is updated by Burst DMA accesses */

+#define LL_HRTIM_BURSTDMA_MCNT     (HRTIM_BDMUPR_MCNT)       /*!< MCNTR register is updated by Burst DMA accesses */

+#define LL_HRTIM_BURSTDMA_MPER     (HRTIM_BDMUPR_MPER)       /*!< MPER register is updated by Burst DMA accesses */

+#define LL_HRTIM_BURSTDMA_MREP     (HRTIM_BDMUPR_MREP)       /*!< MREPR register is updated by Burst DMA accesses */

+#define LL_HRTIM_BURSTDMA_MCMP1    (HRTIM_BDMUPR_MCMP1)      /*!< MCMP1R register is updated by Burst DMA accesses */

+#define LL_HRTIM_BURSTDMA_MCMP2    (HRTIM_BDMUPR_MCMP2)      /*!< MCMP2R register is updated by Burst DMA accesses */

+#define LL_HRTIM_BURSTDMA_MCMP3    (HRTIM_BDMUPR_MCMP3)      /*!< MCMP3R register is updated by Burst DMA accesses */

+#define LL_HRTIM_BURSTDMA_MCMP4    (HRTIM_BDMUPR_MCMP4)      /*!< MCMP4R register is updated by Burst DMA accesses */

+#define LL_HRTIM_BURSTDMA_TIMMCR   (HRTIM_BDTUPR_TIMCR)      /*!< TIMxCR register is updated by Burst DMA accesses */

+#define LL_HRTIM_BURSTDMA_TIMICR   (HRTIM_BDTUPR_TIMICR)     /*!< TIMxICR register is updated by Burst DMA accesses */

+#define LL_HRTIM_BURSTDMA_TIMDIER  (HRTIM_BDTUPR_TIMDIER)    /*!< TIMxDIER register is updated by Burst DMA accesses */

+#define LL_HRTIM_BURSTDMA_TIMCNT   (HRTIM_BDTUPR_TIMCNT)     /*!< CNTxCR register is updated by Burst DMA accesses */

+#define LL_HRTIM_BURSTDMA_TIMPER   (HRTIM_BDTUPR_TIMPER)     /*!< PERxR register is updated by Burst DMA accesses */

+#define LL_HRTIM_BURSTDMA_TIMREP   (HRTIM_BDTUPR_TIMREP)     /*!< REPxR register is updated by Burst DMA accesses */

+#define LL_HRTIM_BURSTDMA_TIMCMP1  (HRTIM_BDTUPR_TIMCMP1)    /*!< CMP1xR register is updated by Burst DMA accesses */

+#define LL_HRTIM_BURSTDMA_TIMCMP2  (HRTIM_BDTUPR_TIMCMP2)    /*!< CMP2xR register is updated by Burst DMA accesses */

+#define LL_HRTIM_BURSTDMA_TIMCMP3  (HRTIM_BDTUPR_TIMCMP3)    /*!< CMP3xR register is updated by Burst DMA accesses */

+#define LL_HRTIM_BURSTDMA_TIMCMP4  (HRTIM_BDTUPR_TIMCMP4)    /*!< CMP4xR register is updated by Burst DMA accesses */

+#define LL_HRTIM_BURSTDMA_TIMDTR   (HRTIM_BDTUPR_TIMDTR)     /*!< DTxR register is updated by Burst DMA accesses */

+#define LL_HRTIM_BURSTDMA_TIMSET1R (HRTIM_BDTUPR_TIMSET1R)   /*!< SET1R register is updated by Burst DMA accesses */

+#define LL_HRTIM_BURSTDMA_TIMRST1R (HRTIM_BDTUPR_TIMRST1R)   /*!< RST1R register is updated by Burst DMA accesses */

+#define LL_HRTIM_BURSTDMA_TIMSET2R (HRTIM_BDTUPR_TIMSET2R)   /*!< SET2R register is updated by Burst DMA accesses */

+#define LL_HRTIM_BURSTDMA_TIMRST2R (HRTIM_BDTUPR_TIMRST2R)   /*!< RST1R register is updated by Burst DMA accesses */

+#define LL_HRTIM_BURSTDMA_TIMEEFR1 (HRTIM_BDTUPR_TIMEEFR1)   /*!< EEFxR1 register is updated by Burst DMA accesses */

+#define LL_HRTIM_BURSTDMA_TIMEEFR2 (HRTIM_BDTUPR_TIMEEFR2)   /*!< EEFxR2 register is updated by Burst DMA accesses */

+#define LL_HRTIM_BURSTDMA_TIMRSTR  (HRTIM_BDTUPR_TIMRSTR)    /*!< RSTxR register is updated by Burst DMA accesses */

+#define LL_HRTIM_BURSTDMA_TIMCHPR  (HRTIM_BDTUPR_TIMCHPR)    /*!< CHPxR register is updated by Burst DMA accesses */

+#define LL_HRTIM_BURSTDMA_TIMOUTR  (HRTIM_BDTUPR_TIMOUTR)    /*!< OUTxR register is updated by Burst DMA accesses */

+#define LL_HRTIM_BURSTDMA_TIMFLTR  (HRTIM_BDTUPR_TIMFLTR)    /*!< FLTxR register is updated by Burst DMA accesses */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_CPPSTAT  CURRENT PUSH-PULL STATUS

+  * @{

+  * @brief Constants defining on which output the signal is currently applied in push-pull mode.

+  */

+#define LL_HRTIM_CPPSTAT_OUTPUT1   ((uint32_t) 0x00000000U) /*!< Signal applied on output 1 and output 2 forced inactive */

+#define LL_HRTIM_CPPSTAT_OUTPUT2   (HRTIM_TIMISR_CPPSTAT)  /*!< Signal applied on output 2 and output 1 forced inactive */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_IPPSTAT  IDLE PUSH-PULL STATUS

+  * @{

+  * @brief Constants defining on which output the signal was applied, in push-pull mode balanced fault mode or delayed idle mode, when the protection was triggered.

+  */

+#define LL_HRTIM_IPPSTAT_OUTPUT1   ((uint32_t) 0x00000000U)    /*!< Protection occurred when the output 1 was active and output 2 forced inactive */

+#define LL_HRTIM_IPPSTAT_OUTPUT2   (HRTIM_TIMISR_IPPSTAT)     /*!< Protection occurred when the output 2 was active and output 1 forced inactive */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_TIM_EEFLTR TIMER EXTERNAL EVENT FILTER

+  * @{

+  * @brief Constants defining the event filtering applied to external events by a timer.

+  */

+#define LL_HRTIM_EEFLTR_NONE             (0x00000000U)

+#define LL_HRTIM_EEFLTR_BLANKINGCMP1     (HRTIM_EEFR1_EE1FLTR_0)                                                                         /*!< Blanking from counter reset/roll-over to Compare 1 */

+#define LL_HRTIM_EEFLTR_BLANKINGCMP2     (HRTIM_EEFR1_EE1FLTR_1)                                                                         /*!< Blanking from counter reset/roll-over to Compare 2 */

+#define LL_HRTIM_EEFLTR_BLANKINGCMP3     (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                                                 /*!< Blanking from counter reset/roll-over to Compare 3 */

+#define LL_HRTIM_EEFLTR_BLANKINGCMP4     (HRTIM_EEFR1_EE1FLTR_2)                                                                         /*!< Blanking from counter reset/roll-over to Compare 4 */

+#define LL_HRTIM_EEFLTR_BLANKINGFLTR1    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                                                 /*!< Blanking from another timing unit: TIMFLTR1 source */

+#define LL_HRTIM_EEFLTR_BLANKINGFLTR2    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                                                 /*!< Blanking from another timing unit: TIMFLTR2 source */

+#define LL_HRTIM_EEFLTR_BLANKINGFLTR3    (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                         /*!< Blanking from another timing unit: TIMFLTR3 source */

+#define LL_HRTIM_EEFLTR_BLANKINGFLTR4    (HRTIM_EEFR1_EE1FLTR_3)                                                                         /*!< Blanking from another timing unit: TIMFLTR4 source */

+#define LL_HRTIM_EEFLTR_BLANKINGFLTR5    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)                                                 /*!< Blanking from another timing unit: TIMFLTR5 source */

+#define LL_HRTIM_EEFLTR_BLANKINGFLTR6    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)                                                 /*!< Blanking from another timing unit: TIMFLTR6 source */

+#define LL_HRTIM_EEFLTR_BLANKINGFLTR7    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)                         /*!< Blanking from another timing unit: TIMFLTR7 source */

+#define LL_HRTIM_EEFLTR_BLANKINGFLTR8    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)                                                 /*!< Blanking from another timing unit: TIMFLTR8 source */

+#define LL_HRTIM_EEFLTR_WINDOWINGCMP2    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)                         /*!< Windowing from counter reset/roll-over to Compare 2 */

+#define LL_HRTIM_EEFLTR_WINDOWINGCMP3    (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)                         /*!< Windowing from counter reset/roll-over to Compare 3 */

+#define LL_HRTIM_EEFLTR_WINDOWINGTIM     (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_TIM_LATCHSTATUS TIMER EXTERNAL EVENT LATCH STATUS

+  * @{

+  * @brief Constants defining whether or not the external event is memorized (latched) and generated as soon as the blanking period is completed or the window ends.

+  */

+#define LL_HRTIM_EELATCH_DISABLED    0x00000000U             /*!< Event is ignored if it happens during a blank, or passed through during a window */

+#define LL_HRTIM_EELATCH_ENABLED     HRTIM_EEFR1_EE1LTCH     /*!< Event is latched and delayed till the end of the blanking or windowing period */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_DT_PRESCALER DEADTIME PRESCALER

+  * @{

+  * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the deadtime generator clock (fDTG).

+  */

+#define LL_HRTIM_DT_PRESCALER_MUL8    0x00000000U                                         /*!< fDTG = fHRTIM * 8 */

+#define LL_HRTIM_DT_PRESCALER_MUL4    (HRTIM_DTR_DTPRSC_0)                                            /*!< fDTG = fHRTIM * 4 */

+#define LL_HRTIM_DT_PRESCALER_MUL2    (HRTIM_DTR_DTPRSC_1)                                            /*!< fDTG = fHRTIM * 2 */

+#define LL_HRTIM_DT_PRESCALER_DIV1    (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0)                       /*!< fDTG = fHRTIM */

+#define LL_HRTIM_DT_PRESCALER_DIV2    (HRTIM_DTR_DTPRSC_2)                                            /*!< fDTG = fHRTIM / 2 */

+#define LL_HRTIM_DT_PRESCALER_DIV4    (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0)                       /*!< fDTG = fHRTIM / 4 */

+#define LL_HRTIM_DT_PRESCALER_DIV8    (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1)                       /*!< fDTG = fHRTIM / 8 */

+#define LL_HRTIM_DT_PRESCALER_DIV16   (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0)  /*!< fDTG = fHRTIM / 16 */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_DT_RISING_SIGN DEADTIME RISING SIGN

+  * @{

+  * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on rising edge.

+  */

+#define LL_HRTIM_DT_RISING_POSITIVE    0x00000000U             /*!< Positive deadtime on rising edge */

+#define LL_HRTIM_DT_RISING_NEGATIVE    (HRTIM_DTR_SDTR)        /*!< Negative deadtime on rising edge */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_DT_FALLING_SIGN DEADTIME FALLING SIGN

+  * @{

+  * @brief Constants defining whether the deadtime is positive or negative (overlapping signal) on falling edge.

+  */

+#define LL_HRTIM_DT_FALLING_POSITIVE    0x00000000U             /*!< Positive deadtime on falling edge */

+#define LL_HRTIM_DT_FALLING_NEGATIVE    (HRTIM_DTR_SDTF)        /*!< Negative deadtime on falling edge */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_CHP_PRESCALER CHOPPER MODE PRESCALER

+  * @{

+  * @brief Constants defining the frequency of the generated high frequency carrier (fCHPFRQ).

+  */

+#define LL_HRTIM_CHP_PRESCALER_DIV16  0x00000000U                                                                     /*!< fCHPFRQ = fHRTIM / 16  */

+#define LL_HRTIM_CHP_PRESCALER_DIV32  (HRTIM_CHPR_CARFRQ_0)                                                                    /*!< fCHPFRQ = fHRTIM / 32  */

+#define LL_HRTIM_CHP_PRESCALER_DIV48  (HRTIM_CHPR_CARFRQ_1)                                                                    /*!< fCHPFRQ = fHRTIM / 48  */

+#define LL_HRTIM_CHP_PRESCALER_DIV64  (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 64  */

+#define LL_HRTIM_CHP_PRESCALER_DIV80  (HRTIM_CHPR_CARFRQ_2)                                                                    /*!< fCHPFRQ = fHRTIM / 80  */

+#define LL_HRTIM_CHP_PRESCALER_DIV96  (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 96  */

+#define LL_HRTIM_CHP_PRESCALER_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1)                                              /*!< fCHPFRQ = fHRTIM / 112  */

+#define LL_HRTIM_CHP_PRESCALER_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 128  */

+#define LL_HRTIM_CHP_PRESCALER_DIV144 (HRTIM_CHPR_CARFRQ_3)                                                                    /*!< fCHPFRQ = fHRTIM / 144  */

+#define LL_HRTIM_CHP_PRESCALER_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0)                                              /*!< fCHPFRQ = fHRTIM / 160  */

+#define LL_HRTIM_CHP_PRESCALER_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1)                                              /*!< fCHPFRQ = fHRTIM / 176  */

+#define LL_HRTIM_CHP_PRESCALER_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 192  */

+#define LL_HRTIM_CHP_PRESCALER_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2)                                              /*!< fCHPFRQ = fHRTIM / 208  */

+#define LL_HRTIM_CHP_PRESCALER_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0)                        /*!< fCHPFRQ = fHRTIM / 224  */

+#define LL_HRTIM_CHP_PRESCALER_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1)                        /*!< fCHPFRQ = fHRTIM / 240  */

+#define LL_HRTIM_CHP_PRESCALER_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0)  /*!< fCHPFRQ = fHRTIM / 256  */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_CHP_DUTYCYCLE CHOPPER MODE DUTY CYCLE

+  * @{

+  * @brief Constants defining the duty cycle of the generated high frequency carrier. Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8).

+  */

+#define LL_HRTIM_CHP_DUTYCYCLE_0    0x00000000U                                              /*!< Only 1st pulse is present */

+#define LL_HRTIM_CHP_DUTYCYCLE_125  (HRTIM_CHPR_CARDTY_0)                                             /*!< Duty cycle of the carrier signal is 12.5 % */

+#define LL_HRTIM_CHP_DUTYCYCLE_250  (HRTIM_CHPR_CARDTY_1)                                             /*!< Duty cycle of the carrier signal is 25 % */

+#define LL_HRTIM_CHP_DUTYCYCLE_375  (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0)                       /*!< Duty cycle of the carrier signal is 37.5 % */

+#define LL_HRTIM_CHP_DUTYCYCLE_500  (HRTIM_CHPR_CARDTY_2)                                             /*!< Duty cycle of the carrier signal is 50 % */

+#define LL_HRTIM_CHP_DUTYCYCLE_625  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0)                       /*!< Duty cycle of the carrier signal is 62.5 % */

+#define LL_HRTIM_CHP_DUTYCYCLE_750  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1)                       /*!< Duty cycle of the carrier signal is 75 % */

+#define LL_HRTIM_CHP_DUTYCYCLE_875  (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5 % */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_CHP_PULSEWIDTH CHOPPER MODE PULSE WIDTH

+  * @{

+  * @brief Constants defining the pulse width of the first pulse of the generated high frequency carrier.

+  */

+#define LL_HRTIM_CHP_PULSEWIDTH_16   0x00000000U                                                                 /*!< tSTPW = tHRTIM x 16  */

+#define LL_HRTIM_CHP_PULSEWIDTH_32   (HRTIM_CHPR_STRPW_0)                                                                 /*!< tSTPW = tHRTIM x 32  */

+#define LL_HRTIM_CHP_PULSEWIDTH_48   (HRTIM_CHPR_STRPW_1)                                                                 /*!< tSTPW = tHRTIM x 48  */

+#define LL_HRTIM_CHP_PULSEWIDTH_64   (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 64  */

+#define LL_HRTIM_CHP_PULSEWIDTH_80   (HRTIM_CHPR_STRPW_2)                                                                 /*!< tSTPW = tHRTIM x 80  */

+#define LL_HRTIM_CHP_PULSEWIDTH_96   (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 96  */

+#define LL_HRTIM_CHP_PULSEWIDTH_112  (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1)                                            /*!< tSTPW = tHRTIM x 112  */

+#define LL_HRTIM_CHP_PULSEWIDTH_128  (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 128  */

+#define LL_HRTIM_CHP_PULSEWIDTH_144  (HRTIM_CHPR_STRPW_3)                                                                 /*!< tSTPW = tHRTIM x 144  */

+#define LL_HRTIM_CHP_PULSEWIDTH_160  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0)                                            /*!< tSTPW = tHRTIM x 160  */

+#define LL_HRTIM_CHP_PULSEWIDTH_176  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1)                                            /*!< tSTPW = tHRTIM x 176  */

+#define LL_HRTIM_CHP_PULSEWIDTH_192  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 192  */

+#define LL_HRTIM_CHP_PULSEWIDTH_208  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2)                                            /*!< tSTPW = tHRTIM x 208  */

+#define LL_HRTIM_CHP_PULSEWIDTH_224  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0)                       /*!< tSTPW = tHRTIM x 224  */

+#define LL_HRTIM_CHP_PULSEWIDTH_240  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1)                       /*!< tSTPW = tHRTIM x 240  */

+#define LL_HRTIM_CHP_PULSEWIDTH_256  (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0)  /*!< tSTPW = tHRTIM x 256  */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_CROSSBAR_INPUT CROSSBAR INPUT

+  * @{

+  * @brief Constants defining the events that can be selected to configure the set/reset crossbar of a timer output.

+  */

+#define LL_HRTIM_CROSSBAR_NONE       0x00000000U             /*!< Reset the output set crossbar */

+#define LL_HRTIM_CROSSBAR_RESYNC     (HRTIM_SET1R_RESYNC)    /*!< Timer reset event coming solely from software or SYNC input forces an output level transision */

+#define LL_HRTIM_CROSSBAR_TIMPER     (HRTIM_SET1R_PER)       /*!< Timer period event forces an output level transision */

+#define LL_HRTIM_CROSSBAR_TIMCMP1    (HRTIM_SET1R_CMP1)      /*!< Timer compare 1 event forces an output level transision */

+#define LL_HRTIM_CROSSBAR_TIMCMP2    (HRTIM_SET1R_CMP2)      /*!< Timer compare 2 event forces an output level transision */

+#define LL_HRTIM_CROSSBAR_TIMCMP3    (HRTIM_SET1R_CMP3)      /*!< Timer compare 3 event forces an output level transision */

+#define LL_HRTIM_CROSSBAR_TIMCMP4    (HRTIM_SET1R_CMP4)      /*!< Timer compare 4 event forces an output level transision */

+#define LL_HRTIM_CROSSBAR_MASTERPER  (HRTIM_SET1R_MSTPER)    /*!< The master timer period event forces an output level transision */

+#define LL_HRTIM_CROSSBAR_MASTERCMP1 (HRTIM_SET1R_MSTCMP1)   /*!< Master Timer compare 1 event forces an output level transision */

+#define LL_HRTIM_CROSSBAR_MASTERCMP2 (HRTIM_SET1R_MSTCMP2)   /*!< Master Timer compare 2 event forces an output level transision */

+#define LL_HRTIM_CROSSBAR_MASTERCMP3 (HRTIM_SET1R_MSTCMP3)   /*!< Master Timer compare 3 event forces an output level transision */

+#define LL_HRTIM_CROSSBAR_MASTERCMP4 (HRTIM_SET1R_MSTCMP4)   /*!< Master Timer compare 4 event forces an output level transision */

+#define LL_HRTIM_CROSSBAR_TIMEV_1    (HRTIM_SET1R_TIMEVNT1)  /*!< Timer event 1 forces an output level transision */

+#define LL_HRTIM_CROSSBAR_TIMEV_2    (HRTIM_SET1R_TIMEVNT2)  /*!< Timer event 2 forces an output level transision */

+#define LL_HRTIM_CROSSBAR_TIMEV_3    (HRTIM_SET1R_TIMEVNT3)  /*!< Timer event 3 forces an output level transision */

+#define LL_HRTIM_CROSSBAR_TIMEV_4    (HRTIM_SET1R_TIMEVNT4)  /*!< Timer event 4 forces an output level transision */

+#define LL_HRTIM_CROSSBAR_TIMEV_5    (HRTIM_SET1R_TIMEVNT5)  /*!< Timer event 5 forces an output level transision */

+#define LL_HRTIM_CROSSBAR_TIMEV_6    (HRTIM_SET1R_TIMEVNT6)  /*!< Timer event 6 forces an output level transision */

+#define LL_HRTIM_CROSSBAR_TIMEV_7    (HRTIM_SET1R_TIMEVNT7)  /*!< Timer event 7 forces an output level transision */

+#define LL_HRTIM_CROSSBAR_TIMEV_8    (HRTIM_SET1R_TIMEVNT8)  /*!< Timer event 8 forces an output level transision */

+#define LL_HRTIM_CROSSBAR_TIMEV_9    (HRTIM_SET1R_TIMEVNT9)  /*!< Timer event 9 forces an output level transision */

+#define LL_HRTIM_CROSSBAR_EEV_1      (HRTIM_SET1R_EXTVNT1)   /*!< External event 1 forces an output level transision */

+#define LL_HRTIM_CROSSBAR_EEV_2      (HRTIM_SET1R_EXTVNT2)   /*!< External event 2 forces an output level transision */

+#define LL_HRTIM_CROSSBAR_EEV_3      (HRTIM_SET1R_EXTVNT3)   /*!< External event 3 forces an output level transision */

+#define LL_HRTIM_CROSSBAR_EEV_4      (HRTIM_SET1R_EXTVNT4)   /*!< External event 4 forces an output level transision */

+#define LL_HRTIM_CROSSBAR_EEV_5      (HRTIM_SET1R_EXTVNT5)   /*!< External event 5 forces an output level transision */

+#define LL_HRTIM_CROSSBAR_EEV_6      (HRTIM_SET1R_EXTVNT6)   /*!< External event 6 forces an output level transision */

+#define LL_HRTIM_CROSSBAR_EEV_7      (HRTIM_SET1R_EXTVNT7)   /*!< External event 7 forces an output level transision */

+#define LL_HRTIM_CROSSBAR_EEV_8      (HRTIM_SET1R_EXTVNT8)   /*!< External event 8 forces an output level transision */

+#define LL_HRTIM_CROSSBAR_EEV_9      (HRTIM_SET1R_EXTVNT9)   /*!< External event 9 forces an output level transision */

+#define LL_HRTIM_CROSSBAR_EEV_10     (HRTIM_SET1R_EXTVNT10)  /*!< External event 10 forces an output level transision */

+#define LL_HRTIM_CROSSBAR_UPDATE     (HRTIM_SET1R_UPDATE)    /*!< Timer register update event forces an output level transision */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_OUT_POLARITY OUPUT_POLARITY

+  * @{

+  * @brief Constants defining the polarity of a timer output.

+  */

+#define LL_HRTIM_OUT_POSITIVE_POLARITY    0x00000000U             /*!< Output is acitve HIGH */

+#define LL_HRTIM_OUT_NEGATIVE_POLARITY    (HRTIM_OUTR_POL1)       /*!< Output is active LOW */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_OUT_IDLEMODE OUTPUT IDLE MODE

+  * @{

+  * @brief Constants defining whether or not the timer output transition to its IDLE state when burst mode is entered.

+  */

+#define LL_HRTIM_OUT_NO_IDLE             0x00000000U            /*!< The output is not affected by the burst mode operation */

+#define LL_HRTIM_OUT_IDLE_WHEN_BURST     (HRTIM_OUTR_IDLM1)     /*!< The output is in idle state when requested by the burst mode controller */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_HALF_MODE HALF MODE

+  * @{

+  * @brief Constants defining the half mode of an HRTIM Timer instance.

+  */

+#define LL_HRTIM_HALF_MODE_DISABLED          0x000U              /*!< HRTIM Half Mode is disabled */

+#define LL_HRTIM_HALF_MODE_ENABLE            HRTIM_MCR_HALF      /*!< HRTIM Half Mode is Half */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_OUT_IDLELEVEL OUTPUT IDLE LEVEL

+  * @{

+  * @brief Constants defining the output level when output is in IDLE state

+  */

+#define LL_HRTIM_OUT_IDLELEVEL_INACTIVE   0x00000000U           /*!< Output at inactive level when in IDLE state */

+#define LL_HRTIM_OUT_IDLELEVEL_ACTIVE     (HRTIM_OUTR_IDLES1)   /*!< Output at active level when in IDLE state */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_OUT_FAULTSTATE OUTPUT FAULT STATE

+  * @{

+  * @brief Constants defining the output level when output is in FAULT state.

+  */

+#define LL_HRTIM_OUT_FAULTSTATE_NO_ACTION 0x00000000U                      /*!< The output is not affected by the fault input */

+#define LL_HRTIM_OUT_FAULTSTATE_ACTIVE    (HRTIM_OUTR_FAULT1_0)                        /*!< Output at active level when in FAULT state */

+#define LL_HRTIM_OUT_FAULTSTATE_INACTIVE  (HRTIM_OUTR_FAULT1_1)                        /*!< Output at inactive level when in FAULT state */

+#define LL_HRTIM_OUT_FAULTSTATE_HIGHZ     (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0)  /*!< Output is tri-stated when in FAULT state */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_OUT_CHOPPERMODE OUTPUT CHOPPER MODE

+  * @{

+  * @brief Constants defining whether or not chopper mode is enabled for a timer output.

+  */

+#define LL_HRTIM_OUT_CHOPPERMODE_DISABLED   0x00000000U             /*!< Output signal is not altered  */

+#define LL_HRTIM_OUT_CHOPPERMODE_ENABLED    (HRTIM_OUTR_CHP1)       /*!< Output signal is chopped by a carrier signal  */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_OUT_BM_ENTRYMODE OUTPUT BURST MODE ENTRY MODE

+  * @{

+  * @brief Constants defining the idle state entry mode during a burst mode operation. It is possible to delay the burst mode entry and force the output to an inactive state

+during a programmable period before the output takes its idle state.

+  */

+#define LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR   0x00000000U            /*!< The programmed Idle state is applied immediately to the Output */

+#define LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED   (HRTIM_OUTR_DIDL1)     /*!< Deadtime is inserted on output before entering the idle mode */

+/**

+  * @}

+  */

+/** @defgroup HRTIM_LL_EC_OUT_LEVEL OUTPUT LEVEL

+  * @{

+  * @brief Constants defining the level of a timer output.

+  */

+#define LL_HRTIM_OUT_LEVEL_INACTIVE   0x00000000U            /*!< Corresponds to a logic level 0 for a positive polarity (High) and to a logic level 1 for a negative polarity (Low) */

+#define LL_HRTIM_OUT_LEVEL_ACTIVE     ((uint32_t)0x00000001) /*!< Corresponds to a logic level 1 for a positive polarity (High) and to a logic level 0 for a negative polarity (Low) */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_EE_SRC EXTERNAL EVENT SOURCE

+  * @{

+  * @brief Constants defining available sources associated to external events.

+  */

+#define LL_HRTIM_EE_SRC_1         0x00000000U                                    /*!< External event source 1 (EExSrc1)*/

+#define LL_HRTIM_EE_SRC_2         (HRTIM_EECR1_EE1SRC_0)                         /*!< External event source 2 (EExSrc2) */

+#define LL_HRTIM_EE_SRC_3         (HRTIM_EECR1_EE1SRC_1)                         /*!< External event source 3 (EExSrc3) */

+#define LL_HRTIM_EE_SRC_4         (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)  /*!< External event source 4 (EExSrc4) */

+/**

+  * @}

+  */

+/** @defgroup HRTIM_LL_EC_EE_POLARITY EXTERNAL EVENT POLARITY

+  * @{

+  * @brief Constants defining the polarity of an external event.

+  */

+#define LL_HRTIM_EE_POLARITY_HIGH    0x00000000U             /*!< External event is active high */

+#define LL_HRTIM_EE_POLARITY_LOW     (HRTIM_EECR1_EE1POL)    /*!< External event is active low */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_EE_SENSITIVITY EXTERNAL EVENT SENSITIVITY

+  * @{

+  * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive) of an external event.

+  */

+#define LL_HRTIM_EE_SENSITIVITY_LEVEL          0x00000000U                        /*!< External event is active on level */

+#define LL_HRTIM_EE_SENSITIVITY_RISINGEDGE     (HRTIM_EECR1_EE1SNS_0)                         /*!< External event is active on Rising edge */

+#define LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE    (HRTIM_EECR1_EE1SNS_1)                         /*!< External event is active on Falling edge */

+#define LL_HRTIM_EE_SENSITIVITY_BOTHEDGES      (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0)  /*!< External event is active on Rising and Falling edges */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_EE_FASTMODE EXTERNAL EVENT FAST MODE

+  * @{

+  * @brief Constants defining whether or not an external event is programmed in fast mode.

+  */

+#define LL_HRTIM_EE_FASTMODE_DISABLE         0x00000000U              /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */

+#define LL_HRTIM_EE_FASTMODE_ENABLE          (HRTIM_EECR1_EE1FAST)    /*!< External Event is acting asynchronously on outputs (low latency mode) */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_EE_FILTER EXTERNAL EVENT DIGITAL FILTER

+  * @{

+  * @brief Constants defining the frequency used to sample an external event input (fSAMPLING) and the length (N) of the digital filter applied.

+  */

+#define LL_HRTIM_EE_FILTER_NONE      0x00000000U                                                               /*!< Filter disabled */

+#define LL_HRTIM_EE_FILTER_1         (HRTIM_EECR3_EE6F_0)                                                                  /*!< fSAMPLING = fHRTIM, N=2 */

+#define LL_HRTIM_EE_FILTER_2         (HRTIM_EECR3_EE6F_1)                                                                  /*!< fSAMPLING = fHRTIM, N=4 */

+#define LL_HRTIM_EE_FILTER_3         (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING = fHRTIM, N=8 */

+#define LL_HRTIM_EE_FILTER_4         (HRTIM_EECR3_EE6F_2)                                                                  /*!< fSAMPLING = fEEVS/2, N=6 */

+#define LL_HRTIM_EE_FILTER_5         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING = fEEVS/2, N=8 */

+#define LL_HRTIM_EE_FILTER_6         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1)                                             /*!< fSAMPLING = fEEVS/4, N=6 */

+#define LL_HRTIM_EE_FILTER_7         (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                        /*!< fSAMPLING = fEEVS/4, N=8 */

+#define LL_HRTIM_EE_FILTER_8         (HRTIM_EECR3_EE6F_3)                                                                  /*!< fSAMPLING = fEEVS/8, N=6 */

+#define LL_HRTIM_EE_FILTER_9         (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0)                                             /*!< fSAMPLING = fEEVS/8, N=8 */

+#define LL_HRTIM_EE_FILTER_10        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1)                                             /*!< fSAMPLING = fEEVS/16, N=5 */

+#define LL_HRTIM_EE_FILTER_11        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)                        /*!< fSAMPLING = fEEVS/16, N=6 */

+#define LL_HRTIM_EE_FILTER_12        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2)                                             /*!< fSAMPLING = fEEVS/16, N=8 */

+#define LL_HRTIM_EE_FILTER_13        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_0)                       /*!< fSAMPLING = fEEVS/32, N=5 */

+#define LL_HRTIM_EE_FILTER_14        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_1)                       /*!< fSAMPLING = fEEVS/32, N=6 */

+#define LL_HRTIM_EE_FILTER_15        (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2  | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0)  /*!< fSAMPLING = fEEVS/32, N=8 */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_EE_PRESCALER EXTERNAL EVENT PRESCALER

+  * @{

+  * @brief Constants defining division ratio between the timer clock frequency (fHRTIM) and the external event signal sampling clock (fEEVS) used by the digital filters.

+  */

+#define LL_HRTIM_EE_PRESCALER_DIV1    0x00000000U                     /*!< fEEVS = fHRTIM */

+#define LL_HRTIM_EE_PRESCALER_DIV2    (HRTIM_EECR3_EEVSD_0)                       /*!< fEEVS = fHRTIM / 2 */

+#define LL_HRTIM_EE_PRESCALER_DIV4    (HRTIM_EECR3_EEVSD_1)                       /*!< fEEVS = fHRTIM / 4 */

+#define LL_HRTIM_EE_PRESCALER_DIV8    (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS = fHRTIM / 8 */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_FLT_SRC FAULT SOURCE

+  * @{

+  * @brief Constants defining whether a faults is be triggered by any external or internal fault source.

+  */

+#define LL_HRTIM_FLT_SRC_DIGITALINPUT         0x00000000U                /*!< Fault input is FLT input pin */

+#define LL_HRTIM_FLT_SRC_INTERNAL             HRTIM_FLTINR1_FLT1SRC      /*!< Fault input is FLT_Int signal (e.g. internal comparator) */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_FLT_POLARITY FAULT POLARITY

+  * @{

+  * @brief Constants defining the polarity of a fault event.

+  */

+#define LL_HRTIM_FLT_POLARITY_LOW     0x00000000U                /*!< Fault input is active low */

+#define LL_HRTIM_FLT_POLARITY_HIGH    (HRTIM_FLTINR1_FLT1P)      /*!< Fault input is active high */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_FLT_FILTER FAULT DIGITAL FILTER

+  * @{

+  * @brief Constants defining the frequency used to sample the fault input (fSAMPLING) and the length (N) of the digital filter applied.

+  */

+#define LL_HRTIM_FLT_FILTER_NONE      0x00000000U                                                                          /*!< Filter disabled */

+#define LL_HRTIM_FLT_FILTER_1         (HRTIM_FLTINR1_FLT1F_0)                                                                          /*!< fSAMPLING= fHRTIM, N=2 */

+#define LL_HRTIM_FLT_FILTER_2         (HRTIM_FLTINR1_FLT1F_1)                                                                          /*!< fSAMPLING= fHRTIM, N=4 */

+#define LL_HRTIM_FLT_FILTER_3         (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fHRTIM, N=8 */

+#define LL_HRTIM_FLT_FILTER_4         (HRTIM_FLTINR1_FLT1F_2)                                                                          /*!< fSAMPLING= fFLTS/2, N=6 */

+#define LL_HRTIM_FLT_FILTER_5         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fFLTS/2, N=8 */

+#define LL_HRTIM_FLT_FILTER_6         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)                                                  /*!< fSAMPLING= fFLTS/4, N=6 */

+#define LL_HRTIM_FLT_FILTER_7         (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/4, N=8 */

+#define LL_HRTIM_FLT_FILTER_8         (HRTIM_FLTINR1_FLT1F_3)                                                                          /*!< fSAMPLING= fFLTS/8, N=6 */

+#define LL_HRTIM_FLT_FILTER_9         (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0)                                                  /*!< fSAMPLING= fFLTS/8, N=8 */

+#define LL_HRTIM_FLT_FILTER_10        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1)                                                  /*!< fSAMPLING= fFLTS/16, N=5 */

+#define LL_HRTIM_FLT_FILTER_11        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/16, N=6 */

+#define LL_HRTIM_FLT_FILTER_12        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2)                                                  /*!< fSAMPLING= fFLTS/16, N=8 */

+#define LL_HRTIM_FLT_FILTER_13        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0)                          /*!< fSAMPLING= fFLTS/32, N=5 */

+#define LL_HRTIM_FLT_FILTER_14        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1)                          /*!< fSAMPLING= fFLTS/32, N=6 */

+#define LL_HRTIM_FLT_FILTER_15        (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0)  /*!< fSAMPLING= fFLTS/32, N=8 */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_FLT_PRESCALER BURST FAULT PRESCALER

+  * @{

+  * @brief Constants defining the division ratio between the timer clock frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used  by the digital filters.

+  */

+#define LL_HRTIM_FLT_PRESCALER_DIV1    0x00000000U                                     /*!< fFLTS = fHRTIM */

+#define LL_HRTIM_FLT_PRESCALER_DIV2    (HRTIM_FLTINR2_FLTSD_0)                         /*!< fFLTS = fHRTIM / 2 */

+#define LL_HRTIM_FLT_PRESCALER_DIV4    (HRTIM_FLTINR2_FLTSD_1)                         /*!< fFLTS = fHRTIM / 4 */

+#define LL_HRTIM_FLT_PRESCALER_DIV8    (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS = fHRTIM / 8 */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_BM_MODE BURST MODE OPERATING MODE

+  * @{

+  * @brief Constants defining if the burst mode is entered once or if it is continuously operating.

+  */

+#define LL_HRTIM_BM_MODE_SINGLESHOT  0x00000000U            /*!< Burst mode operates in single shot mode */

+#define LL_HRTIM_BM_MODE_CONTINOUS   (HRTIM_BMCR_BMOM)      /*!< Burst mode operates in continuous mode */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_BM_CLKSRC BURST MODE CLOCK SOURCE

+  * @{

+  * @brief Constants defining the clock source for the burst mode counter.

+  */

+#define LL_HRTIM_BM_CLKSRC_MASTER     0x00000000U                                         /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */

+#define LL_HRTIM_BM_CLKSRC_TIMER_A    (HRTIM_BMCR_BMCLK_0)                                            /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */

+#define LL_HRTIM_BM_CLKSRC_TIMER_B    (HRTIM_BMCR_BMCLK_1)                                            /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */

+#define LL_HRTIM_BM_CLKSRC_TIMER_C    (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)                       /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */

+#define LL_HRTIM_BM_CLKSRC_TIMER_D    (HRTIM_BMCR_BMCLK_2)                                            /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */

+#define LL_HRTIM_BM_CLKSRC_TIMER_E    (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0)                       /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */

+#define LL_HRTIM_BM_CLKSRC_TIM16_OC   (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1)                       /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */

+#define LL_HRTIM_BM_CLKSRC_TIM17_OC   (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0)  /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */

+#define LL_HRTIM_BM_CLKSRC_TIM7_TRGO  (HRTIM_BMCR_BMCLK_3)                                            /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */

+#define LL_HRTIM_BM_CLKSRC_FHRTIM     (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1)                       /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_BM_PRESCALER BURST MODE PRESCALER

+  * @{

+  * @brief Constants defining the prescaling ratio of the fHRTIM clock for the burst mode controller (fBRST).

+  */

+#define LL_HRTIM_BM_PRESCALER_DIV1     0x00000000U                                                                 /*!< fBRST = fHRTIM */

+#define LL_HRTIM_BM_PRESCALER_DIV2     (HRTIM_BMCR_BMPRSC_0)                                                                   /*!< fBRST = fHRTIM/2 */

+#define LL_HRTIM_BM_PRESCALER_DIV4     (HRTIM_BMCR_BMPRSC_1)                                                                   /*!< fBRST = fHRTIM/4 */

+#define LL_HRTIM_BM_PRESCALER_DIV8     (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/8 */

+#define LL_HRTIM_BM_PRESCALER_DIV16    (HRTIM_BMCR_BMPRSC_2)                                                                   /*!< fBRST = fHRTIM/16 */

+#define LL_HRTIM_BM_PRESCALER_DIV32    (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/32 */

+#define LL_HRTIM_BM_PRESCALER_DIV64    (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1)                                             /*!< fBRST = fHRTIM/64 */

+#define LL_HRTIM_BM_PRESCALER_DIV128   (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/128 */

+#define LL_HRTIM_BM_PRESCALER_DIV256   (HRTIM_BMCR_BMPRSC_3)                                                                   /*!< fBRST = fHRTIM/256 */

+#define LL_HRTIM_BM_PRESCALER_DIV512   (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0)                                             /*!< fBRST = fHRTIM/512 */

+#define LL_HRTIM_BM_PRESCALER_DIV1024  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1)                                             /*!< fBRST = fHRTIM/1024 */

+#define LL_HRTIM_BM_PRESCALER_DIV2048  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/2048*/

+#define LL_HRTIM_BM_PRESCALER_DIV4096  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2)                                             /*!< fBRST = fHRTIM/4096 */

+#define LL_HRTIM_BM_PRESCALER_DIV8192  (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0)                       /*!< fBRST = fHRTIM/8192 */

+#define LL_HRTIM_BM_PRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1)                       /*!< fBRST = fHRTIM/16384 */

+#define LL_HRTIM_BM_PRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768 */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_BM_TRIG HRTIM BURST MODE TRIGGER

+  * @{

+  * @brief Constants defining the events that can be used to trig the burst mode operation.

+  */

+#define LL_HRTIM_BM_TRIG_NONE               0x00000000U             /*!<  No trigger */

+#define LL_HRTIM_BM_TRIG_MASTER_RESET       (HRTIM_BMTRGR_MSTRST)   /*!<  Master timer reset event is starting the burst mode operation */

+#define LL_HRTIM_BM_TRIG_MASTER_REPETITION  (HRTIM_BMTRGR_MSTREP)   /*!<  Master timer repetition event is starting the burst mode operation */

+#define LL_HRTIM_BM_TRIG_MASTER_CMP1        (HRTIM_BMTRGR_MSTCMP1)  /*!<  Master timer compare 1 event is starting the burst mode operation */

+#define LL_HRTIM_BM_TRIG_MASTER_CMP2        (HRTIM_BMTRGR_MSTCMP2)  /*!<  Master timer compare 2 event is starting the burst mode operation */

+#define LL_HRTIM_BM_TRIG_MASTER_CMP3        (HRTIM_BMTRGR_MSTCMP3)  /*!<  Master timer compare 3 event is starting the burst mode operation */

+#define LL_HRTIM_BM_TRIG_MASTER_CMP4        (HRTIM_BMTRGR_MSTCMP4)  /*!<  Master timer compare 4 event is starting the burst mode operation */

+#define LL_HRTIM_BM_TRIG_TIMA_RESET         (HRTIM_BMTRGR_TARST)    /*!< Timer A reset event is starting the burst mode operation */

+#define LL_HRTIM_BM_TRIG_TIMA_REPETITION    (HRTIM_BMTRGR_TAREP)    /*!< Timer A repetition event is starting the burst mode operation */

+#define LL_HRTIM_BM_TRIG_TIMA_CMP1          (HRTIM_BMTRGR_TACMP1)   /*!< Timer A compare 1 event is starting the burst mode operation */

+#define LL_HRTIM_BM_TRIG_TIMA_CMP2          (HRTIM_BMTRGR_TACMP2)   /*!< Timer A compare 2 event is starting the burst mode operation */

+#define LL_HRTIM_BM_TRIG_TIMB_RESET         (HRTIM_BMTRGR_TBRST)    /*!< Timer B reset event is starting the burst mode operation */

+#define LL_HRTIM_BM_TRIG_TIMB_REPETITION    (HRTIM_BMTRGR_TBREP)    /*!< Timer B repetition event is starting the burst mode operation */

+#define LL_HRTIM_BM_TRIG_TIMB_CMP1          (HRTIM_BMTRGR_TBCMP1)   /*!< Timer B compare 1 event is starting the burst mode operation */

+#define LL_HRTIM_BM_TRIG_TIMB_CMP2          (HRTIM_BMTRGR_TBCMP2)   /*!< Timer B compare 2 event is starting the burst mode operation */

+#define LL_HRTIM_BM_TRIG_TIMC_RESET         (HRTIM_BMTRGR_TCRST)    /*!< Timer C resetevent is starting the burst mode operation  */

+#define LL_HRTIM_BM_TRIG_TIMC_REPETITION    (HRTIM_BMTRGR_TCREP)    /*!< Timer C repetition event is starting the burst mode operation */

+#define LL_HRTIM_BM_TRIG_TIMC_CMP1          (HRTIM_BMTRGR_TCCMP1)   /*!< Timer C compare 1 event is starting the burst mode operation */

+#define LL_HRTIM_BM_TRIG_TIMC_CMP2          (HRTIM_BMTRGR_TCCMP2)   /*!< Timer C compare 2 event is starting the burst mode operation */

+#define LL_HRTIM_BM_TRIG_TIMD_RESET         (HRTIM_BMTRGR_TDRST)    /*!< Timer D reset event is starting the burst mode operation */

+#define LL_HRTIM_BM_TRIG_TIMD_REPETITION    (HRTIM_BMTRGR_TDREP)    /*!< Timer D repetition event is starting the burst mode operation */

+#define LL_HRTIM_BM_TRIG_TIMD_CMP1          (HRTIM_BMTRGR_TDCMP1)   /*!< Timer D compare 1 event is starting the burst mode operation */

+#define LL_HRTIM_BM_TRIG_TIMD_CMP2          (HRTIM_BMTRGR_TDCMP2)   /*!< Timer D compare 2 event is starting the burst mode operation */

+#define LL_HRTIM_BM_TRIG_TIME_RESET         (HRTIM_BMTRGR_TERST)    /*!< Timer E reset event is starting the burst mode operation */

+#define LL_HRTIM_BM_TRIG_TIME_REPETITION    (HRTIM_BMTRGR_TEREP)    /*!< Timer E repetition event is starting the burst mode operation */

+#define LL_HRTIM_BM_TRIG_TIME_CMP1          (HRTIM_BMTRGR_TECMP1)   /*!< Timer E compare 1 event is starting the burst mode operation */

+#define LL_HRTIM_BM_TRIG_TIME_CMP2          (HRTIM_BMTRGR_TECMP2)   /*!< Timer E compare 2 event is starting the burst mode operation */

+#define LL_HRTIM_BM_TRIG_TIMA_EVENT7        (HRTIM_BMTRGR_TAEEV7)   /*!< Timer A period following an external event 7 (conditioned by TIMA filters) is starting the burst mode operation  */

+#define LL_HRTIM_BM_TRIG_TIMD_EVENT8        (HRTIM_BMTRGR_TDEEV8)   /*!< Timer D period following an external event 8 (conditioned by TIMD filters) is starting the burst mode operation  */

+#define LL_HRTIM_BM_TRIG_EVENT_7            (HRTIM_BMTRGR_EEV7)     /*!< External event 7 conditioned by TIMA filters is starting the burst mode operation */

+#define LL_HRTIM_BM_TRIG_EVENT_8            (HRTIM_BMTRGR_EEV8)     /*!< External event 8 conditioned by TIMD filters is starting the burst mode operation */

+#define LL_HRTIM_BM_TRIG_EVENT_ONCHIP       (HRTIM_BMTRGR_OCHPEV)   /*!< A rising edge on an on-chip Event (for instance from GP timer or comparator) triggers the burst mode operation */

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EC_BM_STATUS HRTIM BURST MODE STATUS

+  * @{

+  * @brief Constants defining the operating state of the burst mode controller.

+  */

+#define LL_HRTIM_BM_STATUS_NORMAL             0x00000000U           /*!< Normal operation */

+#define LL_HRTIM_BM_STATUS_BURST_ONGOING      HRTIM_BMCR_BMSTAT     /*!< Burst operation on-going */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup HRTIM_LL_Exported_Macros HRTIM Exported Macros

+  * @{

+  */

+

+/** @defgroup HRTIM_LL_EM_WRITE_READ Common Write and read registers Macros

+  * @{

+  */

+

+/**

+  * @brief  Write a value in HRTIM register

+  * @param  __INSTANCE__ HRTIM Instance

+  * @param  __REG__ Register to be written

+  * @param  __VALUE__ Value to be written in the register

+  * @retval None

+  */

+#define LL_HRTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

+

+/**

+  * @brief  Read a value in HRTIM register

+  * @param  __INSTANCE__ HRTIM Instance

+  * @param  __REG__ Register to be read

+  * @retval Register value

+  */

+#define LL_HRTIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EM_Exported_Macros Exported_Macros

+  * @{

+  */

+/**

+  * @brief  HELPER macro returning the output state from output enable/disable status

+  * @param  __OUTPUT_STATUS_EN__ output enable status

+  * @param  __OUTPUT_STATUS_DIS__ output Disable status

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUTPUTSTATE_IDLE

+  *         @arg @ref LL_HRTIM_OUTPUTSTATE_RUN

+  *         @arg @ref LL_HRTIM_OUTPUTSTATE_FAULT

+  */

+#define __LL_HRTIM_GET_OUTPUT_STATE(__OUTPUT_STATUS_EN__, __OUTPUT_STATUS_DIS__)\

+  (((__OUTPUT_STATUS_EN__) == 1) ?  LL_HRTIM_OUTPUTSTATE_RUN :\

+   ((__OUTPUT_STATUS_DIS__) == 0) ? LL_HRTIM_OUTPUTSTATE_IDLE : LL_HRTIM_OUTPUTSTATE_FAULT)

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup HRTIM_LL_Exported_Functions HRTIM Exported Functions

+  * @{

+  */

+/** @defgroup HRTIM_LL_EF_HRTIM_Control HRTIM_Control

+  * @{

+  */

+

+/**

+  * @brief  Select the HRTIM synchronization input source.

+  * @note This function must not be called when  the concerned timer(s) is (are) enabled .

+  * @rmtoll MCR          SYNCIN        LL_HRTIM_SetSyncInSrc

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  SyncInSrc This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_SYNCIN_SRC_NONE

+  *         @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT

+  *         @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_SetSyncInSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncInSrc)

+{

+  MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN, SyncInSrc);

+}

+

+/**

+  * @brief  Get actual HRTIM synchronization input source.

+  * @rmtoll MCR          SYNCIN        LL_HRTIM_SetSyncInSrc

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval SyncInSrc Returned value can be one of the following values:

+  *         @arg @ref LL_HRTIM_SYNCIN_SRC_NONE

+  *         @arg @ref LL_HRTIM_SYNCIN_SRC_TIM_EVENT

+  *         @arg @ref LL_HRTIM_SYNCIN_SRC_EXTERNAL_EVENT

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_GetSyncInSrc(HRTIM_TypeDef *HRTIMx)

+{

+  return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_IN));

+}

+

+/**

+  * @brief  Configure the HRTIM synchronization output.

+  * @rmtoll MCR          SYNCSRC      LL_HRTIM_ConfigSyncOut\n

+  *         MCR          SYNCOUT      LL_HRTIM_ConfigSyncOut

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Config This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_SYNCOUT_DISABLED

+  *         @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE

+  *         @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE

+  * @param  Src This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START

+  *         @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1

+  *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START

+  *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_ConfigSyncOut(HRTIM_TypeDef *HRTIMx, uint32_t Config, uint32_t Src)

+{

+  MODIFY_REG(HRTIMx->sMasterRegs.MCR, (HRTIM_MCR_SYNC_OUT | HRTIM_MCR_SYNC_SRC), (Config | Src));

+}

+

+/**

+  * @brief  Set the routing and conditioning of the synchronization output event.

+  * @rmtoll MCR          SYNCOUT      LL_HRTIM_SetSyncOutConfig

+  * @note This function can be called only when the master timer is enabled.

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  SyncOutConfig This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_SYNCOUT_DISABLED

+  *         @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE

+  *         @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_SetSyncOutConfig(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutConfig)

+{

+  MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT, SyncOutConfig);

+}

+

+/**

+  * @brief  Get actual routing and conditioning of the synchronization output event.

+  * @rmtoll MCR          SYNCOUT      LL_HRTIM_GetSyncOutConfig

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval SyncOutConfig Returned value can be one of the following values:

+  *         @arg @ref LL_HRTIM_SYNCOUT_DISABLED

+  *         @arg @ref LL_HRTIM_SYNCOUT_POSITIVE_PULSE

+  *         @arg @ref LL_HRTIM_SYNCOUT_NEGATIVE_PULSE

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutConfig(HRTIM_TypeDef *HRTIMx)

+{

+  return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_OUT));

+}

+

+/**

+  * @brief  Set the source and event to be sent on the HRTIM synchronization output.

+  * @rmtoll MCR          SYNCSRC      LL_HRTIM_SetSyncOutSrc

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  SyncOutSrc This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START

+  *         @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1

+  *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START

+  *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_SetSyncOutSrc(HRTIM_TypeDef *HRTIMx, uint32_t SyncOutSrc)

+{

+  MODIFY_REG(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC, SyncOutSrc);

+}

+

+/**

+  * @brief  Get actual  source and event sent on the HRTIM synchronization output.

+  * @rmtoll MCR          SYNCSRC      LL_HRTIM_GetSyncOutSrc

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval SyncOutSrc Returned value can be one of the following values:

+  *         @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_START

+  *         @arg @ref LL_HRTIM_SYNCOUT_SRC_MASTER_CMP1

+  *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_START

+  *         @arg @ref LL_HRTIM_SYNCOUT_SRC_TIMA_CMP1

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_GetSyncOutSrc(HRTIM_TypeDef *HRTIMx)

+{

+  return (READ_BIT(HRTIMx->sMasterRegs.MCR, HRTIM_MCR_SYNC_SRC));

+}

+

+/**

+  * @brief  Disable (temporarily) update event generation.

+  * @rmtoll CR1          MUDIS         LL_HRTIM_SuspendUpdate\n

+  *         CR1          TAUDIS        LL_HRTIM_SuspendUpdate\n

+  *         CR1          TBUDIS        LL_HRTIM_SuspendUpdate\n

+  *         CR1          TCUDIS        LL_HRTIM_SuspendUpdate\n

+  *         CR1          TDUDIS        LL_HRTIM_SuspendUpdate\n

+  *         CR1          TEUDIS        LL_HRTIM_SuspendUpdate

+  * @note Allow to temporarily disable the transfer from preload to active

+  *      registers, whatever the selected update event. This allows to modify

+  *      several registers in multiple timers.

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timers This parameter can be a combination of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_SuspendUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)

+{

+  SET_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));

+}

+

+/**

+  * @brief  Enable update event generation.

+  * @rmtoll CR1          MUDIS         LL_HRTIM_ResumeUpdate\n

+  *         CR1          TAUDIS        LL_HRTIM_ResumeUpdate\n

+  *         CR1          TBUDIS        LL_HRTIM_ResumeUpdate\n

+  *         CR1          TCUDIS        LL_HRTIM_ResumeUpdate\n

+  *         CR1          TDUDIS        LL_HRTIM_ResumeUpdate\n

+  *         CR1          TEUDIS        LL_HRTIM_ResumeUpdate

+  * @note The regular update event takes place.

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timers This parameter can be a combination of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_ResumeUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)

+{

+  CLEAR_BIT(HRTIMx->sCommonRegs.CR1, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR1_UDIS_MASK));

+}

+

+/**

+  * @brief  Force an immediate transfer from the preload to the active register .

+  * @rmtoll CR2          MSWU          LL_HRTIM_ForceUpdate\n

+  *         CR2          TASWU         LL_HRTIM_ForceUpdate\n

+  *         CR2          TBSWU         LL_HRTIM_ForceUpdate\n

+  *         CR2          TCSWU         LL_HRTIM_ForceUpdate\n

+  *         CR2          TDSWU         LL_HRTIM_ForceUpdate\n

+  *         CR2          TESWU         LL_HRTIM_ForceUpdate

+  * @note Any pending update request is cancelled.

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timers This parameter can be a combination of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_ForceUpdate(HRTIM_TypeDef *HRTIMx, uint32_t Timers)

+{

+  SET_BIT(HRTIMx->sCommonRegs.CR2, ((Timers >> HRTIM_MCR_MCEN_Pos) & HRTIM_CR2_SWUPD_MASK));

+}

+

+/**

+  * @brief  Reset the HRTIM timer(s) counter.

+  * @rmtoll CR2          MRST          LL_HRTIM_CounterReset\n

+  *         CR2          TARST         LL_HRTIM_CounterReset\n

+  *         CR2          TBRST         LL_HRTIM_CounterReset\n

+  *         CR2          TCRST         LL_HRTIM_CounterReset\n

+  *         CR2          TDRST         LL_HRTIM_CounterReset\n

+  *         CR2          TERST         LL_HRTIM_CounterReset

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timers This parameter can be a combination of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_CounterReset(HRTIM_TypeDef *HRTIMx, uint32_t Timers)

+{

+  SET_BIT(HRTIMx->sCommonRegs.CR2, (((Timers >> HRTIM_MCR_MCEN_Pos) << HRTIM_CR2_MRST_Pos) & HRTIM_CR2_SWRST_MASK));

+}

+

+/**

+  * @brief  Enable the HRTIM timer(s) output(s) .

+  * @rmtoll OENR         TA1OEN        LL_HRTIM_EnableOutput\n

+  *         OENR         TA2OEN        LL_HRTIM_EnableOutput\n

+  *         OENR         TB1OEN        LL_HRTIM_EnableOutput\n

+  *         OENR         TB2OEN        LL_HRTIM_EnableOutput\n

+  *         OENR         TC1OEN        LL_HRTIM_EnableOutput\n

+  *         OENR         TC2OEN        LL_HRTIM_EnableOutput\n

+  *         OENR         TD1OEN        LL_HRTIM_EnableOutput\n

+  *         OENR         TD2OEN        LL_HRTIM_EnableOutput\n

+  *         OENR         TE1OEN        LL_HRTIM_EnableOutput\n

+  *         OENR         TE2OEN        LL_HRTIM_EnableOutput

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Outputs This parameter can be a combination of the following values:

+  *         @arg @ref LL_HRTIM_OUTPUT_TA1

+  *         @arg @ref LL_HRTIM_OUTPUT_TA2

+  *         @arg @ref LL_HRTIM_OUTPUT_TB1

+  *         @arg @ref LL_HRTIM_OUTPUT_TB2

+  *         @arg @ref LL_HRTIM_OUTPUT_TC1

+  *         @arg @ref LL_HRTIM_OUTPUT_TC2

+  *         @arg @ref LL_HRTIM_OUTPUT_TD1

+  *         @arg @ref LL_HRTIM_OUTPUT_TD2

+  *         @arg @ref LL_HRTIM_OUTPUT_TE1

+  *         @arg @ref LL_HRTIM_OUTPUT_TE2

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs)

+{

+  SET_BIT(HRTIMx->sCommonRegs.OENR, (Outputs & HRTIM_OENR_OEN_MASK));

+}

+

+/**

+  * @brief  Disable the HRTIM timer(s) output(s) .

+  * @rmtoll OENR         TA1OEN        LL_HRTIM_DisableOutput\n

+  *         OENR         TA2OEN        LL_HRTIM_DisableOutput\n

+  *         OENR         TB1OEN        LL_HRTIM_DisableOutput\n

+  *         OENR         TB2OEN        LL_HRTIM_DisableOutput\n

+  *         OENR         TC1OEN        LL_HRTIM_DisableOutput\n

+  *         OENR         TC2OEN        LL_HRTIM_DisableOutput\n

+  *         OENR         TD1OEN        LL_HRTIM_DisableOutput\n

+  *         OENR         TD2OEN        LL_HRTIM_DisableOutput\n

+  *         OENR         TE1OEN        LL_HRTIM_DisableOutput\n

+  *         OENR         TE2OEN        LL_HRTIM_DisableOutput

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Outputs This parameter can be a combination of the following values:

+  *         @arg @ref LL_HRTIM_OUTPUT_TA1

+  *         @arg @ref LL_HRTIM_OUTPUT_TA2

+  *         @arg @ref LL_HRTIM_OUTPUT_TB1

+  *         @arg @ref LL_HRTIM_OUTPUT_TB2

+  *         @arg @ref LL_HRTIM_OUTPUT_TC1

+  *         @arg @ref LL_HRTIM_OUTPUT_TC2

+  *         @arg @ref LL_HRTIM_OUTPUT_TD1

+  *         @arg @ref LL_HRTIM_OUTPUT_TD2

+  *         @arg @ref LL_HRTIM_OUTPUT_TE1

+  *         @arg @ref LL_HRTIM_OUTPUT_TE2

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableOutput(HRTIM_TypeDef *HRTIMx, uint32_t Outputs)

+{

+  SET_BIT(HRTIMx->sCommonRegs.ODISR, (Outputs & HRTIM_OENR_ODIS_MASK));

+}

+

+/**

+  * @brief  Indicates whether the HRTIM timer output is enabled.

+  * @rmtoll OENR         TA1OEN        LL_HRTIM_IsEnabledOutput\n

+  *         OENR         TA2OEN        LL_HRTIM_IsEnabledOutput\n

+  *         OENR         TB1OEN        LL_HRTIM_IsEnabledOutput\n

+  *         OENR         TB2OEN        LL_HRTIM_IsEnabledOutput\n

+  *         OENR         TC1OEN        LL_HRTIM_IsEnabledOutput\n

+  *         OENR         TC2OEN        LL_HRTIM_IsEnabledOutput\n

+  *         OENR         TD1OEN        LL_HRTIM_IsEnabledOutput\n

+  *         OENR         TD2OEN        LL_HRTIM_IsEnabledOutput\n

+  *         OENR         TE1OEN        LL_HRTIM_IsEnabledOutput\n

+  *         OENR         TE2OEN        LL_HRTIM_IsEnabledOutput

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Output This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUTPUT_TA1

+  *         @arg @ref LL_HRTIM_OUTPUT_TA2

+  *         @arg @ref LL_HRTIM_OUTPUT_TB1

+  *         @arg @ref LL_HRTIM_OUTPUT_TB2

+  *         @arg @ref LL_HRTIM_OUTPUT_TC1

+  *         @arg @ref LL_HRTIM_OUTPUT_TC2

+  *         @arg @ref LL_HRTIM_OUTPUT_TD1

+  *         @arg @ref LL_HRTIM_OUTPUT_TD2

+  *         @arg @ref LL_HRTIM_OUTPUT_TE1

+  *         @arg @ref LL_HRTIM_OUTPUT_TE2

+  * @retval State of TxyOEN bit in HRTIM_OENR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledOutput(HRTIM_TypeDef *HRTIMx, uint32_t Output)

+{

+  return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == Output) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicates whether the HRTIM timer output is disabled.

+  * @rmtoll ODISR        TA1ODIS        LL_HRTIM_IsDisabledOutput\n

+  *         ODISR        TA2ODIS        LL_HRTIM_IsDisabledOutput\n

+  *         ODISR        TB1ODIS        LL_HRTIM_IsDisabledOutput\n

+  *         ODISR        TB2ODIS        LL_HRTIM_IsDisabledOutput\n

+  *         ODISR        TC1ODIS        LL_HRTIM_IsDisabledOutput\n

+  *         ODISR        TC2ODIS        LL_HRTIM_IsDisabledOutput\n

+  *         ODISR        TD1ODIS        LL_HRTIM_IsDisabledOutput\n

+  *         ODISR        TD2ODIS        LL_HRTIM_IsDisabledOutput\n

+  *         ODISR        TE1ODIS        LL_HRTIM_IsDisabledOutput\n

+  *         ODISR        TE2ODIS        LL_HRTIM_IsDisabledOutput

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Output This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUTPUT_TA1

+  *         @arg @ref LL_HRTIM_OUTPUT_TA2

+  *         @arg @ref LL_HRTIM_OUTPUT_TB1

+  *         @arg @ref LL_HRTIM_OUTPUT_TB2

+  *         @arg @ref LL_HRTIM_OUTPUT_TC1

+  *         @arg @ref LL_HRTIM_OUTPUT_TC2

+  *         @arg @ref LL_HRTIM_OUTPUT_TD1

+  *         @arg @ref LL_HRTIM_OUTPUT_TD2

+  *         @arg @ref LL_HRTIM_OUTPUT_TE1

+  *         @arg @ref LL_HRTIM_OUTPUT_TE2

+  * @retval State of TxyODS bit in HRTIM_OENR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsDisabledOutput(HRTIM_TypeDef *HRTIMx, uint32_t Output)

+{

+  return ((READ_BIT(HRTIMx->sCommonRegs.OENR, Output) == 0U) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Configure an ADC trigger.

+  * @rmtoll CR1          ADC1USRC        LL_HRTIM_ConfigADCTrig\n

+  *         CR1          ADC2USRC        LL_HRTIM_ConfigADCTrig\n

+  *         CR1          ADC3USRC        LL_HRTIM_ConfigADCTrig\n

+  *         CR1          ADC4USRC        LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1MC1         LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1MC2         LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1MC3         LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1MC4         LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1MPER        LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1EEV1        LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1EEV2        LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1EEV3        LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1EEV4        LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1EEV5        LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1TAC2        LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1TAC3        LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1TAC4        LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1TAPER       LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1TARST       LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1TBC2        LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1TBC3        LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1TBC4        LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1TBPER       LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1TBRST       LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1TCC2        LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1TCC3        LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1TCC4        LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1TCPER       LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1TDC2        LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1TDC3        LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1TDC4        LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1TDPER       LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1TEC2        LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1TEC3        LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1TEC4        LL_HRTIM_ConfigADCTrig\n

+  *         ADC1R        ADC1TEPER       LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2MC1         LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2MC2         LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2MC3         LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2MC4         LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2MPER        LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2EEV6        LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2EEV7        LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2EEV8        LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2EEV9        LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2EEV10       LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2TAC2        LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2TAC3        LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2TAC4        LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2TAPER       LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2TBC2        LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2TBC3        LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2TBC4        LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2TBPER       LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2TCC2        LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2TCC3        LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2TCC4        LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2TCPER       LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2TCRST       LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2TDC2        LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2TDC3        LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2TDC4        LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2TDPER       LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2TDRST       LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2TEC2        LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2TEC3        LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2TEC4        LL_HRTIM_ConfigADCTrig\n

+  *         ADC2R        ADC2TERST       LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3MC1         LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3MC2         LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3MC3         LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3MC4         LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3MPER        LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3EEV1        LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3EEV2        LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3EEV3        LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3EEV4        LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3EEV5        LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3TAC2        LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3TAC3        LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3TAC4        LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3TAPER       LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3TARST       LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3TBC2        LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3TBC3        LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3TBC4        LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3TBPER       LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3TBRST       LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3TCC2        LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3TCC3        LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3TCC4        LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3TCPER       LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3TDC2        LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3TDC3        LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3TDC4        LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3TDPER       LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3TEC2        LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3TEC3        LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3TEC4        LL_HRTIM_ConfigADCTrig\n

+  *         ADC3R        ADC3TEPER       LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4MC1         LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4MC2         LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4MC3         LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4MC4         LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4MPER        LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4EEV6        LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4EEV7        LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4EEV8        LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4EEV9        LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4EEV10       LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4TAC2        LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4TAC3        LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4TAC4        LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4TAPER       LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4TBC2        LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4TBC3        LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4TBC4        LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4TBPER       LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4TCC2        LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4TCC3        LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4TCC4        LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4TCPER       LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4TCRST       LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4TDC2        LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4TDC3        LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4TDC4        LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4TDPER       LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4TDRST       LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4TEC2        LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4TEC3        LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4TEC4        LL_HRTIM_ConfigADCTrig\n

+  *         ADC4R        ADC4TERST       LL_HRTIM_ConfigADCTrig

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  ADCTrig This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_ADCTRIG_1

+  *         @arg @ref LL_HRTIM_ADCTRIG_2

+  *         @arg @ref LL_HRTIM_ADCTRIG_3

+  *         @arg @ref LL_HRTIM_ADCTRIG_4

+  * @param  Update This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER

+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A

+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B

+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C

+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D

+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E

+  * @param  Src This parameter can be a combination of the following values:

+  *

+  *         For ADC trigger 1 and ADC trigger 3:

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER

+  *

+  *         For ADC trigger 2 and ADC trigger 4:

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST

+  *

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_ConfigADCTrig(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update, uint32_t Src)

+{

+  register uint32_t shift = ((3U * ADCTrig) & 0x1FU);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +

+                                                              REG_OFFSET_TAB_ADCxR[ADCTrig]));

+  MODIFY_REG(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift), (Update << shift));

+  WRITE_REG(*pReg, Src);

+}

+

+/**

+  * @brief  Associate the ADCx trigger to a timer triggering the update of the HRTIM_ADCxR register.

+  * @rmtoll CR1          ADC1USRC         LL_HRTIM_SetADCTrigUpdate\n

+  *         CR1          ADC2USRC         LL_HRTIM_SetADCTrigUpdate\n

+  *         CR1          ADC3USRC         LL_HRTIM_SetADCTrigUpdate\n

+  *         CR1          ADC4USRC         LL_HRTIM_SetADCTrigUpdate\n

+  * @note When the preload is disabled in the source timer, the HRTIM_ADCxR

+  *       registers are not preloaded either: a write access will result in an

+  *       immediate update of the trigger source.

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  ADCTrig This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_ADCTRIG_1

+  *         @arg @ref LL_HRTIM_ADCTRIG_2

+  *         @arg @ref LL_HRTIM_ADCTRIG_3

+  *         @arg @ref LL_HRTIM_ADCTRIG_4

+  * @param  Update This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER

+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A

+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B

+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C

+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D

+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_SetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Update)

+{

+  register uint32_t shift = ((3U * ADCTrig) & 0x1FU);

+  MODIFY_REG(HRTIMx->sCommonRegs.CR1, (HRTIM_CR1_ADC1USRC << shift), (Update << shift));

+}

+

+/**

+  * @brief  Get the source timer triggering the update of the HRTIM_ADCxR register.

+  * @rmtoll CR1          ADC1USRC        LL_HRTIM_GetADCTrigUpdate\n

+  *         CR1          ADC2USRC        LL_HRTIM_GetADCTrigUpdate\n

+  *         CR1          ADC3USRC        LL_HRTIM_GetADCTrigUpdate\n

+  *         CR1          ADC4USRC        LL_HRTIM_GetADCTrigUpdate\n

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  ADCTrig This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_ADCTRIG_1

+  *         @arg @ref LL_HRTIM_ADCTRIG_2

+  *         @arg @ref LL_HRTIM_ADCTRIG_3

+  *         @arg @ref LL_HRTIM_ADCTRIG_4

+  * @retval Update Returned value can be one of the following values:

+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_MASTER

+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_A

+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_B

+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_C

+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_D

+  *         @arg @ref LL_HRTIM_ADCTRIG_UPDATE_TIMER_E

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigUpdate(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)

+{

+  register const uint32_t shift = ((3U * ADCTrig) & 0x1FU);

+  return (READ_BIT(HRTIMx->sCommonRegs.CR1, (uint32_t)(HRTIM_CR1_ADC1USRC) << shift) >> shift);

+}

+

+/**

+  * @brief  Specify which events (timer events and/or external events) are used as triggers for ADC conversion.

+  * @rmtoll ADC1R        ADC1MC1         LL_HRTIM_SetADCTrigSrc\n

+  *         ADC1R        ADC1MC2         LL_HRTIM_SetADCTrigSrc\n

+  *         ADC1R        ADC1MC3         LL_HRTIM_SetADCTrigSrc\n

+  *         ADC1R        ADC1MC4         LL_HRTIM_SetADCTrigSrc\n

+  *         ADC1R        ADC1MPER        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC1R        ADC1EEV1        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC1R        ADC1EEV2        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC1R        ADC1EEV3        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC1R        ADC1EEV4        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC1R        ADC1EEV5        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC1R        ADC1TAC2        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC1R        ADC1TAC3        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC1R        ADC1TAC4        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC1R        ADC1TAPER       LL_HRTIM_SetADCTrigSrc\n

+  *         ADC1R        ADC1TARST       LL_HRTIM_SetADCTrigSrc\n

+  *         ADC1R        ADC1TBC2        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC1R        ADC1TBC3        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC1R        ADC1TBC4        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC1R        ADC1TBPER       LL_HRTIM_SetADCTrigSrc\n

+  *         ADC1R        ADC1TBRST       LL_HRTIM_SetADCTrigSrc\n

+  *         ADC1R        ADC1TCC2        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC1R        ADC1TCC3        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC1R        ADC1TCC4        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC1R        ADC1TCPER       LL_HRTIM_SetADCTrigSrc\n

+  *         ADC1R        ADC1TDC2        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC1R        ADC1TDC3        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC1R        ADC1TDC4        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC1R        ADC1TDPER       LL_HRTIM_SetADCTrigSrc\n

+  *         ADC1R        ADC1TEC2        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC1R        ADC1TEC3        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC1R        ADC1TEC4        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC1R        ADC1TEPER       LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2MC1         LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2MC2         LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2MC3         LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2MC4         LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2MPER        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2EEV6        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2EEV7        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2EEV8        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2EEV9        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2EEV10       LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2TAC2        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2TAC3        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2TAC4        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2TAPER       LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2TBC2        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2TBC3        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2TBC4        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2TBPER       LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2TCC2        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2TCC3        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2TCC4        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2TCPER       LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2TCRST       LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2TDC2        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2TDC3        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2TDC4        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2TDPER       LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2TDRST       LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2TEC2        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2TEC3        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2TEC4        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC2R        ADC2TERST       LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3MC1         LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3MC2         LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3MC3         LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3MC4         LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3MPER        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3EEV1        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3EEV2        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3EEV3        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3EEV4        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3EEV5        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3TAC2        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3TAC3        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3TAC4        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3TAPER       LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3TARST       LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3TBC2        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3TBC3        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3TBC4        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3TBPER       LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3TBRST       LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3TCC2        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3TCC3        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3TCC4        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3TCPER       LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3TDC2        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3TDC3        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3TDC4        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3TDPER       LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3TEC2        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3TEC3        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3TEC4        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC3R        ADC3TEPER       LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4MC1         LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4MC2         LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4MC3         LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4MC4         LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4MPER        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4EEV6        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4EEV7        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4EEV8        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4EEV9        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4EEV10       LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4TAC2        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4TAC3        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4TAC4        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4TAPER       LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4TBC2        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4TBC3        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4TBC4        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4TBPER       LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4TCC2        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4TCC3        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4TCC4        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4TCPER       LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4TCRST       LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4TDC2        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4TDC3        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4TDC4        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4TDPER       LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4TDRST       LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4TEC2        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4TEC3        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4TEC4        LL_HRTIM_SetADCTrigSrc\n

+  *         ADC4R        ADC4TERST       LL_HRTIM_SetADCTrigSrc\n

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  ADCTrig This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_ADCTRIG_1

+  *         @arg @ref LL_HRTIM_ADCTRIG_2

+  *         @arg @ref LL_HRTIM_ADCTRIG_3

+  *         @arg @ref LL_HRTIM_ADCTRIG_4

+  * @param  Src

+  *         For ADC trigger 1 and ADC trigger 3 this parameter can be a

+  *         combination of the following values:

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER

+  *

+  *         For ADC trigger 2 and ADC trigger 4 this parameter can be a

+  *         combination of the following values:

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST

+  *

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_SetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig, uint32_t Src)

+{

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +

+                                                              REG_OFFSET_TAB_ADCxR[ADCTrig]));

+  WRITE_REG(*pReg, Src);

+}

+

+/**

+  * @brief  Indicate which events (timer events and/or external events) are currently used as triggers for ADC conversion.

+  * @rmtoll ADC1R        ADC1MC1         LL_HRTIM_GetADCTrigSrc\n

+  *         ADC1R        ADC1MC2         LL_HRTIM_GetADCTrigSrc\n

+  *         ADC1R        ADC1MC3         LL_HRTIM_GetADCTrigSrc\n

+  *         ADC1R        ADC1MC4         LL_HRTIM_GetADCTrigSrc\n

+  *         ADC1R        ADC1MPER        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC1R        ADC1EEV1        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC1R        ADC1EEV2        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC1R        ADC1EEV3        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC1R        ADC1EEV4        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC1R        ADC1EEV5        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC1R        ADC1TAC2        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC1R        ADC1TAC3        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC1R        ADC1TAC4        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC1R        ADC1TAPER       LL_HRTIM_GetADCTrigSrc\n

+  *         ADC1R        ADC1TARST       LL_HRTIM_GetADCTrigSrc\n

+  *         ADC1R        ADC1TBC2        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC1R        ADC1TBC3        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC1R        ADC1TBC4        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC1R        ADC1TBPER       LL_HRTIM_GetADCTrigSrc\n

+  *         ADC1R        ADC1TBRST       LL_HRTIM_GetADCTrigSrc\n

+  *         ADC1R        ADC1TCC2        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC1R        ADC1TCC3        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC1R        ADC1TCC4        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC1R        ADC1TCPER       LL_HRTIM_GetADCTrigSrc\n

+  *         ADC1R        ADC1TDC2        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC1R        ADC1TDC3        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC1R        ADC1TDC4        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC1R        ADC1TDPER       LL_HRTIM_GetADCTrigSrc\n

+  *         ADC1R        ADC1TEC2        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC1R        ADC1TEC3        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC1R        ADC1TEC4        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC1R        ADC1TEPER       LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2MC1         LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2MC2         LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2MC3         LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2MC4         LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2MPER        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2EEV6        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2EEV7        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2EEV8        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2EEV9        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2EEV10       LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2TAC2        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2TAC3        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2TAC4        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2TAPER       LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2TBC2        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2TBC3        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2TBC4        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2TBPER       LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2TCC2        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2TCC3        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2TCC4        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2TCPER       LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2TCRST       LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2TDC2        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2TDC3        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2TDC4        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2TDPER       LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2TDRST       LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2TEC2        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2TEC3        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2TEC4        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC2R        ADC2TERST       LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3MC1         LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3MC2         LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3MC3         LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3MC4         LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3MPER        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3EEV1        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3EEV2        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3EEV3        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3EEV4        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3EEV5        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3TAC2        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3TAC3        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3TAC4        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3TAPER       LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3TARST       LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3TBC2        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3TBC3        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3TBC4        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3TBPER       LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3TBRST       LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3TCC2        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3TCC3        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3TCC4        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3TCPER       LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3TDC2        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3TDC3        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3TDC4        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3TDPER       LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3TEC2        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3TEC3        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3TEC4        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC3R        ADC3TEPER       LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4MC1         LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4MC2         LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4MC3         LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4MC4         LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4MPER        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4EEV6        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4EEV7        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4EEV8        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4EEV9        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4EEV10       LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4TAC2        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4TAC3        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4TAC4        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4TAPER       LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4TBC2        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4TBC3        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4TBC4        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4TBPER       LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4TCC2        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4TCC3        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4TCC4        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4TCPER       LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4TCRST       LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4TDC2        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4TDC3        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4TDC4        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4TDPER       LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4TDRST       LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4TEC2        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4TEC3        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4TEC4        LL_HRTIM_GetADCTrigSrc\n

+  *         ADC4R        ADC4TERST       LL_HRTIM_GetADCTrigSrc

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  ADCTrig This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_ADCTRIG_1

+  *         @arg @ref LL_HRTIM_ADCTRIG_2

+  *         @arg @ref LL_HRTIM_ADCTRIG_3

+  *         @arg @ref LL_HRTIM_ADCTRIG_4

+  * @retval Src This parameter can be a combination of the following values:

+  *

+  *         For ADC trigger 1 and ADC trigger 3 this parameter can be a

+  *         combination of the following values:

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_NONE

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP1

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MCMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_MPER

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV1

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_EEV5

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMACMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMAPER

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMARST

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBCMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBPER

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMBRST

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCCMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMCPER

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDCMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMDPER

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMECMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC13_TIMEPER

+  *

+  *         For ADC trigger 2 and ADC trigger 4 this parameter can be a

+  *         combination of the following values:

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_NONE

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP1

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MCMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_MPER

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV6

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV7

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV8

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV9

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_EEV10

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMACMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMAPER

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBCMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMBPER

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCCMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCPER

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMCRST

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDCMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDPER

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMDRST

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP2

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP3

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMECMP4

+  *         @arg @ref LL_HRTIM_ADCTRIG_SRC24_TIMERST

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_GetADCTrigSrc(HRTIM_TypeDef *HRTIMx, uint32_t ADCTrig)

+{

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.ADC1R) +

+                                                                    REG_OFFSET_TAB_ADCxR[ADCTrig]));

+  return (*pReg);

+

+}

+

+

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EF_HRTIM_Timer_Control HRTIM_Timer_Control

+  * @{

+  */

+

+/**

+  * @brief  Enable timer(s) counter.

+  * @rmtoll MDIER        TECEN         LL_HRTIM_TIM_CounterEnable\n

+  *         MDIER        TDCEN         LL_HRTIM_TIM_CounterEnable\n

+  *         MDIER        TCCEN         LL_HRTIM_TIM_CounterEnable\n

+  *         MDIER        TBCEN         LL_HRTIM_TIM_CounterEnable\n

+  *         MDIER        TACEN         LL_HRTIM_TIM_CounterEnable\n

+  *         MDIER        MCEN          LL_HRTIM_TIM_CounterEnable

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timers This parameter can be a combination of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_CounterEnable(HRTIM_TypeDef *HRTIMx, uint32_t Timers)

+{

+  SET_BIT(HRTIMx->sMasterRegs.MCR, Timers);

+}

+

+/**

+  * @brief  Disable timer(s) counter.

+  * @rmtoll MDIER        TECEN         LL_HRTIM_TIM_CounterDisable\n

+  *         MDIER        TDCEN         LL_HRTIM_TIM_CounterDisable\n

+  *         MDIER        TCCEN         LL_HRTIM_TIM_CounterDisable\n

+  *         MDIER        TBCEN         LL_HRTIM_TIM_CounterDisable\n

+  *         MDIER        TACEN         LL_HRTIM_TIM_CounterDisable\n

+  *         MDIER        MCEN          LL_HRTIM_TIM_CounterDisable

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timers This parameter can be a combination of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_CounterDisable(HRTIM_TypeDef *HRTIMx, uint32_t Timers)

+{

+  CLEAR_BIT(HRTIMx->sMasterRegs.MCR, Timers);

+}

+

+/**

+  * @brief  Indicate whether the timer counter is enabled.

+  * @rmtoll MDIER        TECEN         LL_HRTIM_TIM_IsCounterEnabled\n

+  *         MDIER        TDCEN         LL_HRTIM_TIM_IsCounterEnabled\n

+  *         MDIER        TCCEN         LL_HRTIM_TIM_IsCounterEnabled\n

+  *         MDIER        TBCEN         LL_HRTIM_TIM_IsCounterEnabled\n

+  *         MDIER        TACEN         LL_HRTIM_TIM_IsCounterEnabled\n

+  *         MDIER        MCEN          LL_HRTIM_TIM_IsCounterEnabled

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of MCEN or TxCEN bit HRTIM_MCR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsCounterEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  return ((READ_BIT(HRTIMx->sMasterRegs.MCR, Timer) == (Timer)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set the timer clock prescaler ratio.

+  * @rmtoll MCR        CKPSC         LL_HRTIM_TIM_SetPrescaler\n

+  *         TIMxCR     CKPSC         LL_HRTIM_TIM_SetPrescaler

+  * @note The counter clock equivalent frequency (CK_CNT) is equal to fHRCK / 2^CKPSC[2:0].

+  * @note The prescaling ratio cannot be modified once the timer counter is enabled.

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  Prescaler This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1

+  *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2

+  *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));

+  MODIFY_REG(*pReg, HRTIM_MCR_CK_PSC, Prescaler);

+}

+

+/**

+  * @brief  Get the timer clock prescaler ratio

+  * @rmtoll MCR        CKPSC         LL_HRTIM_TIM_GetPrescaler\n

+  *         TIMxCR     CKPSC         LL_HRTIM_TIM_GetPrescaler

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval Prescaler Returned value can be one of the following values:

+  *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV1

+  *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV2

+  *         @arg @ref LL_HRTIM_PRESCALERRATIO_DIV4

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));

+  return (READ_BIT(*pReg, HRTIM_MCR_CK_PSC));

+}

+

+/**

+  * @brief  Set the counter operating mode mode (single-shot, continuous or re-triggerable).

+  * @rmtoll MCR        CONT         LL_HRTIM_TIM_SetCounterMode\n

+  *         MCR        RETRIG       LL_HRTIM_TIM_SetCounterMode\n

+  *         TIMxCR     CONT         LL_HRTIM_TIM_SetCounterMode\n

+  *         TIMxCR     RETRIG       LL_HRTIM_TIM_SetCounterMode

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  Mode This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_MODE_CONTINUOUS

+  *         @arg @ref LL_HRTIM_MODE_SINGLESHOT

+  *         @arg @ref LL_HRTIM_MODE_RETRIGGERABLE

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_SetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Mode)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));

+  MODIFY_REG(*pReg, (HRTIM_TIMCR_RETRIG | HRTIM_MCR_CONT), Mode);

+}

+

+/**

+  * @brief  Get the counter operating mode mode

+  * @rmtoll MCR        CONT         LL_HRTIM_TIM_GetCounterMode\n

+  *         MCR        RETRIG       LL_HRTIM_TIM_GetCounterMode\n

+  *         TIMxCR     CONT         LL_HRTIM_TIM_GetCounterMode\n

+  *         TIMxCR     RETRIG       LL_HRTIM_TIM_GetCounterMode

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval Mode Returned value can be one of the following values:

+  *         @arg @ref LL_HRTIM_MODE_CONTINUOUS

+  *         @arg @ref LL_HRTIM_MODE_SINGLESHOT

+  *         @arg @ref LL_HRTIM_MODE_RETRIGGERABLE

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounterMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));

+  return (READ_BIT(*pReg, (HRTIM_MCR_RETRIG | HRTIM_MCR_CONT)));

+}

+

+/**

+  * @brief  Enable the half duty-cycle mode.

+  * @rmtoll MCR        HALF         LL_HRTIM_TIM_EnableHalfMode\n

+  *         TIMxCR     HALF         LL_HRTIM_TIM_EnableHalfMode

+  * @note When the half mode is enabled, HRTIM_MCMP1R (or HRTIM_CMP1xR)

+  *       active register is automatically updated with HRTIM_MPER/2

+  *       (or HRTIM_PERxR/2) value when HRTIM_MPER (or HRTIM_PERxR) register is written.

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_EnableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_MCR_HALF);

+}

+

+/**

+  * @brief  Disable the half duty-cycle mode.

+  * @rmtoll MCR        HALF         LL_HRTIM_TIM_DisableHalfMode\n

+  *         TIMxCR     HALF         LL_HRTIM_TIM_DisableHalfMode

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_DisableHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_MCR_HALF);

+}

+

+/**

+  * @brief  Indicate whether half duty-cycle mode is enabled for a given timer.

+  * @rmtoll MCR        HALF         LL_HRTIM_TIM_IsEnabledHalfMode\n

+  *         TIMxCR     HALF         LL_HRTIM_TIM_IsEnabledHalfMode

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of HALF bit to 1 in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledHalfMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_MCR_HALF) == (HRTIM_MCR_HALF)) ? 1UL : 0UL);

+}

+/**

+  * @brief  Enable the timer start when receiving a synchronization input event.

+  * @rmtoll MCR        SYNCSTRTM        LL_HRTIM_TIM_EnableStartOnSync\n

+  *         TIMxCR     SYNSTRTA         LL_HRTIM_TIM_EnableStartOnSync

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_EnableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_MCR_SYNCSTRTM);

+}

+

+/**

+  * @brief  Disable the timer start when receiving a synchronization input event.

+  * @rmtoll MCR        SYNCSTRTM        LL_HRTIM_TIM_DisableStartOnSync\n

+  *         TIMxCR     SYNSTRTA         LL_HRTIM_TIM_DisableStartOnSync

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_DisableStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_MCR_SYNCSTRTM);

+}

+

+/**

+  * @brief  Indicate whether the timer start when receiving a synchronization input event.

+  * @rmtoll MCR        SYNCSTRTM        LL_HRTIM_TIM_IsEnabledStartOnSync\n

+  *         TIMxCR     SYNSTRTA         LL_HRTIM_TIM_IsEnabledStartOnSync

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of SYNCSTRTx bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledStartOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_MCR_SYNCSTRTM) == (HRTIM_MCR_SYNCSTRTM)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the timer reset when receiving a synchronization input event.

+  * @rmtoll MCR        SYNCRSTM        LL_HRTIM_TIM_EnableResetOnSync\n

+  *         TIMxCR     SYNCRSTA        LL_HRTIM_TIM_EnableResetOnSync

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_EnableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_MCR_SYNCRSTM);

+}

+

+/**

+  * @brief  Disable the timer reset when receiving a synchronization input event.

+  * @rmtoll MCR        SYNCRSTM        LL_HRTIM_TIM_DisableResetOnSync\n

+  *         TIMxCR     SYNCRSTA        LL_HRTIM_TIM_DisableResetOnSync

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_DisableResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_MCR_SYNCRSTM);

+}

+

+/**

+  * @brief  Indicate whether the timer reset when receiving a synchronization input event.

+  * @rmtoll MCR        SYNCRSTM        LL_HRTIM_TIM_IsEnabledResetOnSync\n

+  *         TIMxCR     SYNCRSTA        LL_HRTIM_TIM_IsEnabledResetOnSync

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledResetOnSync(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_MCR_SYNCRSTM) == (HRTIM_MCR_SYNCRSTM)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).

+  * @rmtoll MCR        DACSYNC        LL_HRTIM_TIM_SetDACTrig\n

+  *         TIMxCR     DACSYNC        LL_HRTIM_TIM_SetDACTrig

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  DACTrig This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_DACTRIG_NONE

+  *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1

+  *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2

+  *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_SetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DACTrig)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));

+  MODIFY_REG(*pReg, HRTIM_MCR_DACSYNC, DACTrig);

+}

+

+/**

+  * @brief  Get the HRTIM output the DAC synchronization event is generated on (DACtrigOutx).

+  * @rmtoll MCR        DACSYNC        LL_HRTIM_TIM_GetDACTrig\n

+  *         TIMxCR     DACSYNC        LL_HRTIM_TIM_GetDACTrig

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval DACTrig Returned value can be one of the following values:

+  *         @arg @ref LL_HRTIM_DACTRIG_NONE

+  *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_1

+  *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_2

+  *         @arg @ref LL_HRTIM_DACTRIG_DACTRIGOUT_3

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDACTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));

+  return (READ_BIT(*pReg, HRTIM_MCR_DACSYNC));

+}

+

+/**

+  * @brief  Enable the timer registers preload mechanism.

+  * @rmtoll MCR        PREEN        LL_HRTIM_TIM_EnablePreload\n

+  *         TIMxCR     PREEN        LL_HRTIM_TIM_EnablePreload

+  * @note When the preload mode is enabled, accessed registers are shadow registers.

+  *       Their content is transferred into the active register after an update request,

+  *       either software or synchronized with an event.

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_EnablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_MCR_PREEN);

+}

+

+/**

+  * @brief  Disable the timer registers preload mechanism.

+  * @rmtoll MCR        PREEN        LL_HRTIM_TIM_DisablePreload\n

+  *         TIMxCR     PREEN        LL_HRTIM_TIM_DisablePreload

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_DisablePreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_MCR_PREEN);

+}

+

+/**

+  * @brief  Indicate whether the timer registers preload mechanism is enabled.

+  * @rmtoll MCR        PREEN        LL_HRTIM_TIM_IsEnabledPreload\n

+  *         TIMxCR     PREEN        LL_HRTIM_TIM_IsEnabledPreload

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of PREEN bit in HRTIM_MCR or HRTIM_TIMxCR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_MCR_PREEN) == (HRTIM_MCR_PREEN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set the timer register update trigger.

+  * @rmtoll MCR           MREPU      LL_HRTIM_TIM_SetUpdateTrig\n

+  *         TIMxCR        TAU        LL_HRTIM_TIM_SetUpdateTrig\n

+  *         TIMxCR        TBU        LL_HRTIM_TIM_SetUpdateTrig\n

+  *         TIMxCR        TCU        LL_HRTIM_TIM_SetUpdateTrig\n

+  *         TIMxCR        TDU        LL_HRTIM_TIM_SetUpdateTrig\n

+  *         TIMxCR        TEU        LL_HRTIM_TIM_SetUpdateTrig\n

+  *         TIMxCR        MSTU       LL_HRTIM_TIM_SetUpdateTrig

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  UpdateTrig This parameter can be one of the following values:

+  *

+  *         For the master timer this parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_UPDATETRIG_NONE

+  *         @arg @ref LL_HRTIM_UPDATETRIG_REPETITION

+  *

+  *         For timer A..E this parameter can be:

+  *         @arg @ref LL_HRTIM_UPDATETRIG_NONE

+  *         or a combination of the following values:

+  *         @arg @ref LL_HRTIM_UPDATETRIG_MASTER

+  *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A

+  *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B

+  *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C

+  *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D

+  *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E

+  *         @arg @ref LL_HRTIM_UPDATETRIG_REPETITION

+  *         @arg @ref LL_HRTIM_UPDATETRIG_RESET

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_SetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateTrig)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));

+  MODIFY_REG(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer], UpdateTrig << REG_SHIFT_TAB_UPDATETRIG[iTimer]);

+}

+

+/**

+  * @brief  Get the timer register update trigger.

+  * @rmtoll MCR           MREPU      LL_HRTIM_TIM_GetUpdateTrig\n

+  *         TIMxCR        TBU        LL_HRTIM_TIM_GetUpdateTrig\n

+  *         TIMxCR        TCU        LL_HRTIM_TIM_GetUpdateTrig\n

+  *         TIMxCR        TDU        LL_HRTIM_TIM_GetUpdateTrig\n

+  *         TIMxCR        TEU        LL_HRTIM_TIM_GetUpdateTrig\n

+  *         TIMxCR        MSTU       LL_HRTIM_TIM_GetUpdateTrig

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval UpdateTrig Returned value can be one of the following values:

+  *

+  *         For the master timer this parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_UPDATETRIG_NONE

+  *         @arg @ref LL_HRTIM_UPDATETRIG_REPETITION

+  *

+  *         For timer A..E this parameter can be:

+  *         @arg @ref LL_HRTIM_UPDATETRIG_NONE

+  *         or a combination of the following values:

+  *         @arg @ref LL_HRTIM_UPDATETRIG_MASTER

+  *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_A

+  *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_B

+  *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_C

+  *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_D

+  *         @arg @ref LL_HRTIM_UPDATETRIG_TIMER_E

+  *         @arg @ref LL_HRTIM_UPDATETRIG_REPETITION

+  *         @arg @ref LL_HRTIM_UPDATETRIG_RESET

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));

+  return (READ_BIT(*pReg, REG_MASK_TAB_UPDATETRIG[iTimer]) >>  REG_SHIFT_TAB_UPDATETRIG[iTimer]);

+}

+

+/**

+  * @brief  Set  the timer registers update condition (how the registers update occurs relatively to the burst DMA  transaction or an external update request received on one of the update enable inputs (UPD_EN[3:1])).

+  * @rmtoll MCR           BRSTDMA      LL_HRTIM_TIM_SetUpdateGating\n

+  *         TIMxCR        UPDGAT       LL_HRTIM_TIM_SetUpdateGating

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  UpdateGating This parameter can be one of the following values:

+  *

+  *         For the master timer this parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT

+  *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST

+  *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE

+  *

+  *         For the timer A..E this parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT

+  *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST

+  *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE

+  *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1

+  *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2

+  *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3

+  *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE

+  *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE

+  *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_SetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t UpdateGating)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));

+  MODIFY_REG(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer], (UpdateGating << REG_SHIFT_TAB_UPDATEGATING[iTimer]));

+}

+

+/**

+  * @brief  Get  the timer registers update condition.

+  * @rmtoll MCR           BRSTDMA      LL_HRTIM_TIM_GetUpdateGating\n

+  *         TIMxCR        UPDGAT       LL_HRTIM_TIM_GetUpdateGating

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval UpdateGating Returned value can be one of the following values:

+  *

+  *         For the master timer this parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT

+  *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST

+  *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE

+  *

+  *         For the timer A..E this parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_UPDATEGATING_INDEPENDENT

+  *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST

+  *         @arg @ref LL_HRTIM_UPDATEGATING_DMABURST_UPDATE

+  *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1

+  *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2

+  *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3

+  *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN1_UPDATE

+  *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN2_UPDATE

+  *         @arg @ref LL_HRTIM_UPDATEGATING_UPDEN3_UPDATE

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetUpdateGating(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCR) + REG_OFFSET_TAB_TIMER[iTimer]));

+  return (READ_BIT(*pReg, REG_MASK_TAB_UPDATEGATING[iTimer]) >>  REG_SHIFT_TAB_UPDATEGATING[iTimer]);

+}

+

+/**

+  * @brief  Enable the push-pull mode.

+  * @rmtoll TIMxCR        PSHPLL       LL_HRTIM_TIM_EnablePushPullMode

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_EnablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_TIMCR_PSHPLL);

+}

+

+/**

+  * @brief  Disable the push-pull mode.

+  * @rmtoll TIMxCR        PSHPLL       LL_HRTIM_TIM_DisablePushPullMode

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_DisablePushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_TIMCR_PSHPLL);

+}

+

+/**

+  * @brief  Indicate whether the push-pull mode is enabled.

+  * @rmtoll TIMxCR        PSHPLL       LL_HRTIM_TIM_IsEnabledPushPullMode\n

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of PSHPLL bit in HRTIM_TIMxCR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledPushPullMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  return ((READ_BIT(*pReg, HRTIM_TIMCR_PSHPLL) == (HRTIM_TIMCR_PSHPLL)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set the functioning mode of the compare unit (CMP2 or CMP4 can operate in standard mode or in auto delayed mode).

+  * @rmtoll TIMxCR        DELCMP2       LL_HRTIM_TIM_SetCompareMode\n

+  *         TIMxCR        DELCMP4       LL_HRTIM_TIM_SetCompareMode

+  * @note In auto-delayed mode  the compare match occurs independently from the timer counter value.

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  CompareUnit This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_COMPAREUNIT_2

+  *         @arg @ref LL_HRTIM_COMPAREUNIT_4

+  * @param  Mode This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_COMPAREMODE_REGULAR

+  *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT

+  *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1

+  *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_SetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit,

+                                                 uint32_t Mode)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  register uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU);

+  MODIFY_REG(* pReg, (HRTIM_TIMCR_DELCMP2 << shift), (Mode << shift));

+}

+

+/**

+  * @brief  Get the functioning mode of the compare unit.

+  * @rmtoll TIMxCR        DELCMP2       LL_HRTIM_TIM_GetCompareMode\n

+  *         TIMxCR        DELCMP4       LL_HRTIM_TIM_GetCompareMode

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  CompareUnit This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_COMPAREUNIT_2

+  *         @arg @ref LL_HRTIM_COMPAREUNIT_4

+  * @retval Mode Returned value can be one of the following values:

+  *         @arg @ref LL_HRTIM_COMPAREMODE_REGULAR

+  *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_NOTIMEOUT

+  *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP1

+  *         @arg @ref LL_HRTIM_COMPAREMODE_DELAY_CMP3

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompareMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareUnit)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxCR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  register uint32_t shift = (((uint32_t)POSITION_VAL(CompareUnit) - (uint32_t)POSITION_VAL(LL_HRTIM_COMPAREUNIT_2)) & 0x1FU);

+  return (READ_BIT(*pReg, (HRTIM_TIMCR_DELCMP2 << shift)) >>  shift);

+}

+

+/**

+  * @brief  Set the timer counter value.

+  * @rmtoll MCNTR        MCNT       LL_HRTIM_TIM_SetCounter\n

+  *         CNTxR        CNTx       LL_HRTIM_TIM_SetCounter

+  * @note  This function can only be called when the timer is stopped.

+  * @note  For HR clock prescaling ratio below 32 (CKPSC[2:0] < 5), the least

+  *        significant bits of the counter are not significant. They cannot be

+  *        written and return 0 when read.

+  * @note The timer behavior is not guaranteed if the counter value is set above

+  *       the period.

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  Counter Value between 0 and 0xFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_SetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Counter)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  MODIFY_REG(* pReg, HRTIM_MCNTR_MCNTR, Counter);

+}

+

+/**

+  * @brief  Get actual timer counter value.

+  * @rmtoll MCNTR        MCNT       LL_HRTIM_TIM_GetCounter\n

+  *         CNTxR        CNTx       LL_HRTIM_TIM_GetCounter

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval Counter Value between 0 and 0xFFFF

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCounter(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCNTR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  return (READ_BIT(*pReg, HRTIM_MCNTR_MCNTR));

+}

+

+/**

+  * @brief  Set the timer period value.

+  * @rmtoll MPER        MPER       LL_HRTIM_TIM_SetPeriod\n

+  *         PERxR       PERx       LL_HRTIM_TIM_SetPeriod

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  Period Value between 0 and 0xFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Period)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  MODIFY_REG(* pReg, HRTIM_MPER_MPER, Period);

+}

+

+/**

+  * @brief  Get actual timer period value.

+  * @rmtoll MPER        MPER       LL_HRTIM_TIM_GetPeriod\n

+  *         PERxR       PERx       LL_HRTIM_TIM_GetPeriod

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval Period Value between 0 and 0xFFFF

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MPER) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  return (READ_BIT(*pReg, HRTIM_MPER_MPER));

+}

+

+/**

+  * @brief  Set the timer repetition period value.

+  * @rmtoll MREP        MREP       LL_HRTIM_TIM_SetRepetition\n

+  *         REPxR       REPx       LL_HRTIM_TIM_SetRepetition

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  Repetition Value between 0 and 0xFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_SetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Repetition)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  MODIFY_REG(* pReg, HRTIM_MREP_MREP, Repetition);

+}

+

+/**

+  * @brief  Get actual timer repetition period value.

+  * @rmtoll MREP        MREP       LL_HRTIM_TIM_GetRepetition\n

+  *         REPxR       REPx       LL_HRTIM_TIM_GetRepetition

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval Repetition Value between 0 and 0xFF

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetRepetition(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MREP) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  return (READ_BIT(*pReg, HRTIM_MREP_MREP));

+}

+

+/**

+  * @brief  Set the compare value of the compare unit 1.

+  * @rmtoll MCMP1R      MCMP1       LL_HRTIM_TIM_SetCompare1\n

+  *         CMP1xR      CMP1x       LL_HRTIM_TIM_SetCompare1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  CompareValue Compare value must be above or equal to 3

+  *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,

+  *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_SetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP1R, CompareValue);

+}

+

+/**

+  * @brief  Get actual compare value of the compare unit 1.

+  * @rmtoll MCMP1R      MCMP1       LL_HRTIM_TIM_GetCompare1\n

+  *         CMP1xR      CMP1x       LL_HRTIM_TIM_GetCompare1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval CompareValue Compare value must be above or equal to 3

+  *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,

+  *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP1R) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP1R));

+}

+

+/**

+  * @brief  Set the compare value of the compare unit 2.

+  * @rmtoll MCMP2R      MCMP2       LL_HRTIM_TIM_SetCompare2\n

+  *         CMP2xR      CMP2x       LL_HRTIM_TIM_SetCompare2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  CompareValue Compare value must be above or equal to 3

+  *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,

+  *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_SetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP2R, CompareValue);

+}

+

+/**

+  * @brief  Get actual compare value of the compare unit 2.

+  * @rmtoll MCMP2R      MCMP2       LL_HRTIM_TIM_GetCompare2\n

+  *         CMP2xR      CMP2x       LL_HRTIM_TIM_GetCompare2\n

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval CompareValue Compare value must be above or equal to 3

+  *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,

+  *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP2R) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP2R));

+}

+

+/**

+  * @brief  Set the compare value of the compare unit 3.

+  * @rmtoll MCMP3R      MCMP3       LL_HRTIM_TIM_SetCompare3\n

+  *         CMP3xR      CMP3x       LL_HRTIM_TIM_SetCompare3

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  CompareValue Compare value must be above or equal to 3

+  *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,

+  *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_SetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP3R, CompareValue);

+}

+

+/**

+  * @brief  Get actual compare value of the compare unit 3.

+  * @rmtoll MCMP3R      MCMP3       LL_HRTIM_TIM_GetCompare3\n

+  *         CMP3xR      CMP3x       LL_HRTIM_TIM_GetCompare3

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval CompareValue Compare value must be above or equal to 3

+  *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,

+  *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP3R) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP3R));

+}

+

+/**

+  * @brief  Set the compare value of the compare unit 4.

+  * @rmtoll MCMP4R      MCMP4       LL_HRTIM_TIM_SetCompare4\n

+  *         CMP4xR      CMP4x       LL_HRTIM_TIM_SetCompare4

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  CompareValue Compare value must be above or equal to 3

+  *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,

+  *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_SetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CompareValue)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  MODIFY_REG(* pReg, HRTIM_MCMP1R_MCMP4R, CompareValue);

+}

+

+/**

+  * @brief  Get actual compare value of the compare unit 4.

+  * @rmtoll MCMP4R      MCMP4       LL_HRTIM_TIM_GetCompare4\n

+  *         CMP4xR      CMP4x       LL_HRTIM_TIM_GetCompare4

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval CompareValue Compare value must be above or equal to 3

+  *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,

+  *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCompare4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MCMP4R) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  return (READ_BIT(*pReg, HRTIM_MCMP1R_MCMP4R));

+}

+

+/**

+  * @brief  Set the reset trigger of a timer counter.

+  * @rmtoll RSTxR      UPDT           LL_HRTIM_TIM_SetResetTrig\n

+  *         RSTxR      CMP2           LL_HRTIM_TIM_SetResetTrig\n

+  *         RSTxR      CMP4           LL_HRTIM_TIM_SetResetTrig\n

+  *         RSTxR      MSTPER         LL_HRTIM_TIM_SetResetTrig\n

+  *         RSTxR      MSTCMP1        LL_HRTIM_TIM_SetResetTrig\n

+  *         RSTxR      MSTCMP2        LL_HRTIM_TIM_SetResetTrig\n

+  *         RSTxR      MSTCMP3        LL_HRTIM_TIM_SetResetTrig\n

+  *         RSTxR      MSTCMP4        LL_HRTIM_TIM_SetResetTrig\n

+  *         RSTxR      EXTEVNT1       LL_HRTIM_TIM_SetResetTrig\n

+  *         RSTxR      EXTEVNT2       LL_HRTIM_TIM_SetResetTrig\n

+  *         RSTxR      EXTEVNT3       LL_HRTIM_TIM_SetResetTrig\n

+  *         RSTxR      EXTEVNT4       LL_HRTIM_TIM_SetResetTrig\n

+  *         RSTxR      EXTEVNT5       LL_HRTIM_TIM_SetResetTrig\n

+  *         RSTxR      EXTEVNT6       LL_HRTIM_TIM_SetResetTrig\n

+  *         RSTxR      EXTEVNT7       LL_HRTIM_TIM_SetResetTrig\n

+  *         RSTxR      EXTEVNT8       LL_HRTIM_TIM_SetResetTrig\n

+  *         RSTxR      EXTEVNT9       LL_HRTIM_TIM_SetResetTrig\n

+  *         RSTxR      EXTEVNT10      LL_HRTIM_TIM_SetResetTrig\n

+  *         RSTxR      TIMBCMP1       LL_HRTIM_TIM_SetResetTrig\n

+  *         RSTxR      TIMBCMP2       LL_HRTIM_TIM_SetResetTrig\n

+  *         RSTxR      TIMBCMP4       LL_HRTIM_TIM_SetResetTrig\n

+  *         RSTxR      TIMCCMP1       LL_HRTIM_TIM_SetResetTrig\n

+  *         RSTxR      TIMCCMP2       LL_HRTIM_TIM_SetResetTrig\n

+  *         RSTxR      TIMCCMP4       LL_HRTIM_TIM_SetResetTrig\n

+  *         RSTxR      TIMDCMP1       LL_HRTIM_TIM_SetResetTrig\n

+  *         RSTxR      TIMDCMP2       LL_HRTIM_TIM_SetResetTrig\n

+  *         RSTxR      TIMDCMP4       LL_HRTIM_TIM_SetResetTrig\n

+  *         RSTxR      TIMECMP1       LL_HRTIM_TIM_SetResetTrig\n

+  *         RSTxR      TIMECMP2       LL_HRTIM_TIM_SetResetTrig\n

+  *         RSTxR      TIMECMP4       LL_HRTIM_TIM_SetResetTrig

+  * @note The reset of the timer counter can be triggered by up to 30 events

+  *       that can be selected among the following sources:

+  *         @arg The timing unit: Compare 2, Compare 4 and Update (3 events).

+  *         @arg The master timer: Reset and Compare 1..4 (5 events).

+  *         @arg The external events EXTEVNT1..10 (10 events).

+  *         @arg All other timing units (e.g. Timer B..E for timer A): Compare 1, 2 and 4 (12 events).

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  ResetTrig This parameter can be a combination of the following values:

+  *         @arg @ref LL_HRTIM_RESETTRIG_NONE

+  *         @arg @ref LL_HRTIM_RESETTRIG_UPDATE

+  *         @arg @ref LL_HRTIM_RESETTRIG_CMP2

+  *         @arg @ref LL_HRTIM_RESETTRIG_CMP4

+  *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER

+  *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1

+  *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2

+  *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3

+  *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4

+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_1

+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_2

+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_3

+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_4

+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_5

+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_6

+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_7

+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_8

+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_9

+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_10

+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1

+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2

+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4

+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1

+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2

+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4

+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1

+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2

+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4

+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1

+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2

+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_SetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t ResetTrig)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  WRITE_REG(*pReg, ResetTrig);

+}

+

+/**

+  * @brief  Get actual reset trigger of a timer counter.

+  * @rmtoll RSTxR      UPDT           LL_HRTIM_TIM_GetResetTrig\n

+  *         RSTxR      CMP2           LL_HRTIM_TIM_GetResetTrig\n

+  *         RSTxR      CMP4           LL_HRTIM_TIM_GetResetTrig\n

+  *         RSTxR      MSTPER         LL_HRTIM_TIM_GetResetTrig\n

+  *         RSTxR      MSTCMP1        LL_HRTIM_TIM_GetResetTrig\n

+  *         RSTxR      MSTCMP2        LL_HRTIM_TIM_GetResetTrig\n

+  *         RSTxR      MSTCMP3        LL_HRTIM_TIM_GetResetTrig\n

+  *         RSTxR      MSTCMP4        LL_HRTIM_TIM_GetResetTrig\n

+  *         RSTxR      EXTEVNT1       LL_HRTIM_TIM_GetResetTrig\n

+  *         RSTxR      EXTEVNT2       LL_HRTIM_TIM_GetResetTrig\n

+  *         RSTxR      EXTEVNT3       LL_HRTIM_TIM_GetResetTrig\n

+  *         RSTxR      EXTEVNT4       LL_HRTIM_TIM_GetResetTrig\n

+  *         RSTxR      EXTEVNT5       LL_HRTIM_TIM_GetResetTrig\n

+  *         RSTxR      EXTEVNT6       LL_HRTIM_TIM_GetResetTrig\n

+  *         RSTxR      EXTEVNT7       LL_HRTIM_TIM_GetResetTrig\n

+  *         RSTxR      EXTEVNT8       LL_HRTIM_TIM_GetResetTrig\n

+  *         RSTxR      EXTEVNT9       LL_HRTIM_TIM_GetResetTrig\n

+  *         RSTxR      EXTEVNT10      LL_HRTIM_TIM_GetResetTrig\n

+  *         RSTxR      TIMBCMP1       LL_HRTIM_TIM_GetResetTrig\n

+  *         RSTxR      TIMBCMP2       LL_HRTIM_TIM_GetResetTrig\n

+  *         RSTxR      TIMBCMP4       LL_HRTIM_TIM_GetResetTrig\n

+  *         RSTxR      TIMCCMP1       LL_HRTIM_TIM_GetResetTrig\n

+  *         RSTxR      TIMCCMP2       LL_HRTIM_TIM_GetResetTrig\n

+  *         RSTxR      TIMCCMP4       LL_HRTIM_TIM_GetResetTrig\n

+  *         RSTxR      TIMDCMP1       LL_HRTIM_TIM_GetResetTrig\n

+  *         RSTxR      TIMDCMP2       LL_HRTIM_TIM_GetResetTrig\n

+  *         RSTxR      TIMDCMP4       LL_HRTIM_TIM_GetResetTrig\n

+  *         RSTxR      TIMECMP1       LL_HRTIM_TIM_GetResetTrig\n

+  *         RSTxR      TIMECMP2       LL_HRTIM_TIM_GetResetTrig\n

+  *         RSTxR      TIMECMP4       LL_HRTIM_TIM_GetResetTrig

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval ResetTrig Returned value can be one of the following values:

+  *         @arg @ref LL_HRTIM_RESETTRIG_NONE

+  *         @arg @ref LL_HRTIM_RESETTRIG_UPDATE

+  *         @arg @ref LL_HRTIM_RESETTRIG_CMP2

+  *         @arg @ref LL_HRTIM_RESETTRIG_CMP4

+  *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_PER

+  *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP1

+  *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP2

+  *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP3

+  *         @arg @ref LL_HRTIM_RESETTRIG_MASTER_CMP4

+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_1

+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_2

+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_3

+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_4

+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_5

+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_6

+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_7

+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_8

+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_9

+  *         @arg @ref LL_HRTIM_RESETTRIG_EEV_10

+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP1

+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP2

+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER1_CMP4

+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP1

+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP2

+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER2_CMP4

+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP1

+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP2

+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER3_CMP4

+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP1

+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP2

+  *         @arg @ref LL_HRTIM_RESETTRIG_OTHER4_CMP4

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetResetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTxR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  return (READ_REG(*pReg));

+}

+

+/**

+  * @brief  Get captured value for capture unit 1.

+  * @rmtoll CPT1xR      CPT1x           LL_HRTIM_TIM_GetCapture1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval Captured value

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT1xR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  return (READ_REG(*pReg));

+}

+

+/**

+  * @brief  Get captured value for capture unit 2.

+  * @rmtoll CPT2xR      CPT2x           LL_HRTIM_TIM_GetCapture2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval Captured value

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCapture2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CPT2xR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  return (READ_REG(*pReg));

+}

+

+/**

+  * @brief  Set the trigger of a capture unit for a given timer.

+  * @rmtoll CPT1xCR      SWCPT            LL_HRTIM_TIM_SetCaptureTrig\n

+  *         CPT1xCR      UPDCPT           LL_HRTIM_TIM_SetCaptureTrig\n

+  *         CPT1xCR      EXEV1CPT         LL_HRTIM_TIM_SetCaptureTrig\n

+  *         CPT1xCR      EXEV2CPT         LL_HRTIM_TIM_SetCaptureTrig\n

+  *         CPT1xCR      EXEV3CPT         LL_HRTIM_TIM_SetCaptureTrig\n

+  *         CPT1xCR      EXEV4CPT         LL_HRTIM_TIM_SetCaptureTrig\n

+  *         CPT1xCR      EXEV5CPT         LL_HRTIM_TIM_SetCaptureTrig\n

+  *         CPT1xCR      EXEV6CPT         LL_HRTIM_TIM_SetCaptureTrig\n

+  *         CPT1xCR      EXEV7CPT         LL_HRTIM_TIM_SetCaptureTrig\n

+  *         CPT1xCR      EXEV8CPT         LL_HRTIM_TIM_SetCaptureTrig\n

+  *         CPT1xCR      EXEV9CPT         LL_HRTIM_TIM_SetCaptureTrig\n

+  *         CPT1xCR      EXEV10CPT        LL_HRTIM_TIM_SetCaptureTrig\n

+  *         CPT1xCR      TA1SET           LL_HRTIM_TIM_SetCaptureTrig\n

+  *         CPT1xCR      TA1RST           LL_HRTIM_TIM_SetCaptureTrig\n

+  *         CPT1xCR      TACMP1           LL_HRTIM_TIM_SetCaptureTrig\n

+  *         CPT1xCR      TACMP2           LL_HRTIM_TIM_SetCaptureTrig\n

+  *         CPT1xCR      TB1SET           LL_HRTIM_TIM_SetCaptureTrig\n

+  *         CPT1xCR      TB1RST           LL_HRTIM_TIM_SetCaptureTrig\n

+  *         CPT1xCR      TBCMP1           LL_HRTIM_TIM_SetCaptureTrig\n

+  *         CPT1xCR      TBCMP2           LL_HRTIM_TIM_SetCaptureTrig\n

+  *         CPT1xCR      TC1SET           LL_HRTIM_TIM_SetCaptureTrig\n

+  *         CPT1xCR      TC1RST           LL_HRTIM_TIM_SetCaptureTrig\n

+  *         CPT1xCR      TCCMP1           LL_HRTIM_TIM_SetCaptureTrig\n

+  *         CPT1xCR      TCCMP2           LL_HRTIM_TIM_SetCaptureTrig\n

+  *         CPT1xCR      TD1SET           LL_HRTIM_TIM_SetCaptureTrig\n

+  *         CPT1xCR      TD1RST           LL_HRTIM_TIM_SetCaptureTrig\n

+  *         CPT1xCR      TDCMP1           LL_HRTIM_TIM_SetCaptureTrig\n

+  *         CPT1xCR      TDCMP2           LL_HRTIM_TIM_SetCaptureTrig\n

+  *         CPT1xCR      TE1SET           LL_HRTIM_TIM_SetCaptureTrig\n

+  *         CPT1xCR      TE1RST           LL_HRTIM_TIM_SetCaptureTrig\n

+  *         CPT1xCR      TECMP1           LL_HRTIM_TIM_SetCaptureTrig\n

+  *         CPT1xCR      TECMP2           LL_HRTIM_TIM_SetCaptureTrig

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  CaptureUnit This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_CAPTUREUNIT_1

+  *         @arg @ref LL_HRTIM_CAPTUREUNIT_2

+  * @param  CaptureTrig This parameter can be a combination of the following values:

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_NONE

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_SetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit,

+                                                 uint32_t CaptureTrig)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U)));

+  WRITE_REG(*pReg, CaptureTrig);

+}

+

+/**

+  * @brief  Get actual trigger of a capture unit for a given timer.

+  * @rmtoll CPT1xCR      SWCPT            LL_HRTIM_TIM_GetCaptureTrig\n

+  *         CPT1xCR      UPDCPT           LL_HRTIM_TIM_GetCaptureTrig\n

+  *         CPT1xCR      EXEV1CPT         LL_HRTIM_TIM_GetCaptureTrig\n

+  *         CPT1xCR      EXEV2CPT         LL_HRTIM_TIM_GetCaptureTrig\n

+  *         CPT1xCR      EXEV3CPT         LL_HRTIM_TIM_GetCaptureTrig\n

+  *         CPT1xCR      EXEV4CPT         LL_HRTIM_TIM_GetCaptureTrig\n

+  *         CPT1xCR      EXEV5CPT         LL_HRTIM_TIM_GetCaptureTrig\n

+  *         CPT1xCR      EXEV6CPT         LL_HRTIM_TIM_GetCaptureTrig\n

+  *         CPT1xCR      EXEV7CPT         LL_HRTIM_TIM_GetCaptureTrig\n

+  *         CPT1xCR      EXEV8CPT         LL_HRTIM_TIM_GetCaptureTrig\n

+  *         CPT1xCR      EXEV9CPT         LL_HRTIM_TIM_GetCaptureTrig\n

+  *         CPT1xCR      EXEV10CPT        LL_HRTIM_TIM_GetCaptureTrig\n

+  *         CPT1xCR      TA1SET           LL_HRTIM_TIM_GetCaptureTrig\n

+  *         CPT1xCR      TA1RST           LL_HRTIM_TIM_GetCaptureTrig\n

+  *         CPT1xCR      TACMP1           LL_HRTIM_TIM_GetCaptureTrig\n

+  *         CPT1xCR      TACMP2           LL_HRTIM_TIM_GetCaptureTrig\n

+  *         CPT1xCR      TB1SET           LL_HRTIM_TIM_GetCaptureTrig\n

+  *         CPT1xCR      TB1RST           LL_HRTIM_TIM_GetCaptureTrig\n

+  *         CPT1xCR      TBCMP1           LL_HRTIM_TIM_GetCaptureTrig\n

+  *         CPT1xCR      TBCMP2           LL_HRTIM_TIM_GetCaptureTrig\n

+  *         CPT1xCR      TC1SET           LL_HRTIM_TIM_GetCaptureTrig\n

+  *         CPT1xCR      TC1RST           LL_HRTIM_TIM_GetCaptureTrig\n

+  *         CPT1xCR      TCCMP1           LL_HRTIM_TIM_GetCaptureTrig\n

+  *         CPT1xCR      TCCMP2           LL_HRTIM_TIM_GetCaptureTrig\n

+  *         CPT1xCR      TD1SET           LL_HRTIM_TIM_GetCaptureTrig\n

+  *         CPT1xCR      TD1RST           LL_HRTIM_TIM_GetCaptureTrig\n

+  *         CPT1xCR      TDCMP1           LL_HRTIM_TIM_GetCaptureTrig\n

+  *         CPT1xCR      TDCMP2           LL_HRTIM_TIM_GetCaptureTrig\n

+  *         CPT1xCR      TE1SET           LL_HRTIM_TIM_GetCaptureTrig\n

+  *         CPT1xCR      TE1RST           LL_HRTIM_TIM_GetCaptureTrig\n

+  *         CPT1xCR      TECMP1           LL_HRTIM_TIM_GetCaptureTrig\n

+  *         CPT1xCR      TECMP2           LL_HRTIM_TIM_GetCaptureTrig

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  CaptureUnit This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_CAPTUREUNIT_1

+  *         @arg @ref LL_HRTIM_CAPTUREUNIT_2

+  * @retval CaptureTrig This parameter can be a combination of the following values:

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_NONE

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_UPDATE

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_1

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_2

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_3

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_4

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_5

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_6

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_7

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_8

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_9

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_EEV_10

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TA1_SET

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TA1_RESET

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP1

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMA_CMP2

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TB1_SET

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TB1_RESET

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP1

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMB_CMP2

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TC1_SET

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TC1_RESET

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP1

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMC_CMP2

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TD1_SET

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TD1_RESET

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP1

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIMD_CMP2

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TE1_SET

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TE1_RESET

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP1

+  *         @arg @ref LL_HRTIM_CAPTURETRIG_TIME_CMP2

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCaptureTrig(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t CaptureUnit)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0U].CPT1xCR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer] + (CaptureUnit * 4U)));

+  return (READ_REG(*pReg));

+}

+

+/**

+  * @brief  Enable deadtime insertion for a given timer.

+  * @rmtoll OUTxR      DTEN           LL_HRTIM_TIM_EnableDeadTime

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_EnableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_OUTR_DTEN);

+}

+

+/**

+  * @brief  Disable deadtime insertion for a given timer.

+  * @rmtoll OUTxR      DTEN           LL_HRTIM_TIM_DisableDeadTime

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_DisableDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_OUTR_DTEN);

+}

+

+/**

+  * @brief  Indicate whether deadtime insertion is enabled for a given timer.

+  * @rmtoll OUTxR      DTEN           LL_HRTIM_TIM_IsEnabledDeadTime

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of DTEN bit in HRTIM_OUTxR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDeadTime(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_OUTR_DTEN) == (HRTIM_OUTR_DTEN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set the delayed protection (DLYPRT) mode.

+  * @rmtoll OUTxR      DLYPRTEN       LL_HRTIM_TIM_SetDLYPRTMode\n

+  *         OUTxR      DLYPRT         LL_HRTIM_TIM_SetDLYPRTMode

+  * @note   This function must be called prior enabling the delayed protection

+  * @note   Balanced Idle mode is only available in push-pull mode

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  DLYPRTMode Delayed protection (DLYPRT) mode

+  *

+  *         For timers A, B and C this parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6

+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6

+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6

+  *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6

+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7

+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7

+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7

+  *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7

+  *

+  *         For timers D and E this parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8

+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8

+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8

+  *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8

+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9

+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9

+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9

+  *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_SetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DLYPRTMode)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  MODIFY_REG(*pReg, HRTIM_OUTR_DLYPRT, DLYPRTMode);

+}

+

+/**

+  * @brief  Get the delayed protection (DLYPRT) mode.

+  * @rmtoll OUTxR      DLYPRTEN       LL_HRTIM_TIM_GetDLYPRTMode\n

+  *         OUTxR      DLYPRT         LL_HRTIM_TIM_GetDLYPRTMode

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval DLYPRTMode Delayed protection (DLYPRT) mode

+  *

+  *         For timers A, B and C this parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV6

+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV6

+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV6

+  *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV6

+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV7

+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV7

+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV7

+  *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV7

+  *

+  *         For timers D and E this parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV8

+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV8

+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV8

+  *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV8

+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT1_EEV9

+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYOUT2_EEV9

+  *         @arg @ref LL_HRTIM_DLYPRT_DELAYBOTH_EEV9

+  *         @arg @ref LL_HRTIM_DLYPRT_BALANCED_EEV9

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetDLYPRTMode(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  return (READ_BIT(*pReg, HRTIM_OUTR_DLYPRT));

+}

+

+/**

+  * @brief  Enable delayed protection (DLYPRT) for a given timer.

+  * @rmtoll OUTxR      DLYPRTEN       LL_HRTIM_TIM_EnableDLYPRT

+  * @note   This function must not be called once the concerned timer is enabled

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_EnableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_OUTR_DLYPRTEN);

+}

+

+/**

+  * @brief  Disable delayed protection (DLYPRT) for a given timer.

+  * @rmtoll OUTxR      DLYPRTEN       LL_HRTIM_TIM_DisableDLYPRT

+  * @note   This function must not be called once the concerned timer is enabled

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_DisableDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_OUTR_DLYPRTEN);

+}

+

+/**

+  * @brief  Indicate whether delayed protection (DLYPRT) is enabled for a given timer.

+  * @rmtoll OUTxR      DLYPRTEN       LL_HRTIM_TIM_IsEnabledDLYPRT

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of DLYPRTEN bit in HRTIM_OUTxR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledDLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  return ((READ_BIT(*pReg, HRTIM_OUTR_DLYPRTEN) == (HRTIM_OUTR_DLYPRTEN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the fault channel(s) for a given timer.

+  * @rmtoll FLTxR      FLT1EN       LL_HRTIM_TIM_EnableFault\n

+  *         FLTxR      FLT2EN       LL_HRTIM_TIM_EnableFault\n

+  *         FLTxR      FLT3EN       LL_HRTIM_TIM_EnableFault\n

+  *         FLTxR      FLT4EN       LL_HRTIM_TIM_EnableFault\n

+  *         FLTxR      FLT5EN       LL_HRTIM_TIM_EnableFault

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  Faults This parameter can be a combination of the following values:

+  *         @arg @ref LL_HRTIM_FAULT_1

+  *         @arg @ref LL_HRTIM_FAULT_2

+  *         @arg @ref LL_HRTIM_FAULT_3

+  *         @arg @ref LL_HRTIM_FAULT_4

+  *         @arg @ref LL_HRTIM_FAULT_5

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_EnableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, Faults);

+}

+

+/**

+  * @brief  Disable the fault channel(s) for a given timer.

+  * @rmtoll FLTxR      FLT1EN       LL_HRTIM_TIM_DisableFault\n

+  *         FLTxR      FLT2EN       LL_HRTIM_TIM_DisableFault\n

+  *         FLTxR      FLT3EN       LL_HRTIM_TIM_DisableFault\n

+  *         FLTxR      FLT4EN       LL_HRTIM_TIM_DisableFault\n

+  *         FLTxR      FLT5EN       LL_HRTIM_TIM_DisableFault

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  Faults This parameter can be a combination of the following values:

+  *         @arg @ref LL_HRTIM_FAULT_1

+  *         @arg @ref LL_HRTIM_FAULT_2

+  *         @arg @ref LL_HRTIM_FAULT_3

+  *         @arg @ref LL_HRTIM_FAULT_4

+  *         @arg @ref LL_HRTIM_FAULT_5

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_DisableFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Faults)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, Faults);

+}

+

+/**

+  * @brief  Indicate whether the fault channel is enabled for a given timer.

+  * @rmtoll FLTxR      FLT1EN       LL_HRTIM_TIM_IsEnabledFault\n

+  *         FLTxR      FLT2EN       LL_HRTIM_TIM_IsEnabledFault\n

+  *         FLTxR      FLT3EN       LL_HRTIM_TIM_IsEnabledFault\n

+  *         FLTxR      FLT4EN       LL_HRTIM_TIM_IsEnabledFault\n

+  *         FLTxR      FLT5EN       LL_HRTIM_TIM_IsEnabledFault

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  Fault This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_FAULT_1

+  *         @arg @ref LL_HRTIM_FAULT_2

+  *         @arg @ref LL_HRTIM_FAULT_3

+  *         @arg @ref LL_HRTIM_FAULT_4

+  *         @arg @ref LL_HRTIM_FAULT_5

+  * @retval State of FLTxEN bit in HRTIM_FLTxR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_IsEnabledFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Fault)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, Fault) == (Fault)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Lock the fault conditioning set-up for a given timer.

+  * @rmtoll FLTxR      FLTLCK       LL_HRTIM_TIM_LockFault

+  * @note Timer fault-related set-up is frozen until the next HRTIM or system reset

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_LockFault(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].FLTxR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_FLTR_FLTLCK);

+}

+

+/**

+  * @brief  Define how the timer behaves during a burst mode operation.

+  * @rmtoll BMCR      MTBM       LL_HRTIM_TIM_SetBurstModeOption\n

+  *         BMCR      TABM       LL_HRTIM_TIM_SetBurstModeOption\n

+  *         BMCR      TBBM       LL_HRTIM_TIM_SetBurstModeOption\n

+  *         BMCR      TCBM       LL_HRTIM_TIM_SetBurstModeOption\n

+  *         BMCR      TDBM       LL_HRTIM_TIM_SetBurstModeOption\n

+  *         BMCR      TEBM       LL_HRTIM_TIM_SetBurstModeOption

+  * @note This function must not be called when the burst mode is enabled

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  BurtsModeOption This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK

+  *         @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_SetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t BurtsModeOption)

+{

+  register uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU);

+  MODIFY_REG(HRTIMx->sCommonRegs.BMCR, Timer, BurtsModeOption << iTimer);

+}

+

+/**

+  * @brief  Retrieve how the timer behaves during a burst mode operation.

+  * @rmtoll BMCR      MCR        LL_HRTIM_TIM_GetBurstModeOption\n

+  *         BMCR      TABM       LL_HRTIM_TIM_GetBurstModeOption\n

+  *         BMCR      TBBM       LL_HRTIM_TIM_GetBurstModeOption\n

+  *         BMCR      TCBM       LL_HRTIM_TIM_GetBurstModeOption\n

+  *         BMCR      TDBM       LL_HRTIM_TIM_GetBurstModeOption\n

+  *         BMCR      TEBM       LL_HRTIM_TIM_GetBurstModeOption

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval BurtsMode This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_BURSTMODE_MAINTAINCLOCK

+  *         @arg @ref LL_HRTIM_BURSTMODE_RESETCOUNTER

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetBurstModeOption(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)((POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos) & 0x1FU);

+  return (READ_BIT(HRTIMx->sCommonRegs.BMCR, Timer) >> iTimer);

+}

+

+/**

+  * @brief  Program which registers are to be written by Burst DMA transfers.

+  * @rmtoll BDMUPDR      MTBM        LL_HRTIM_TIM_ConfigBurstDMA\n

+  *         BDMUPDR      MICR        LL_HRTIM_TIM_ConfigBurstDMA\n

+  *         BDMUPDR      MDIER       LL_HRTIM_TIM_ConfigBurstDMA\n

+  *         BDMUPDR      MCNT        LL_HRTIM_TIM_ConfigBurstDMA\n

+  *         BDMUPDR      MPER        LL_HRTIM_TIM_ConfigBurstDMA\n

+  *         BDMUPDR      MREP        LL_HRTIM_TIM_ConfigBurstDMA\n

+  *         BDMUPDR      MCMP1       LL_HRTIM_TIM_ConfigBurstDMA\n

+  *         BDMUPDR      MCMP2       LL_HRTIM_TIM_ConfigBurstDMA\n

+  *         BDMUPDR      MCMP3       LL_HRTIM_TIM_ConfigBurstDMA\n

+  *         BDMUPDR      MCMP4       LL_HRTIM_TIM_ConfigBurstDMA\n

+  *         BDTxUPDR     TIMxCR      LL_HRTIM_TIM_ConfigBurstDMA\n

+  *         BDTxUPDR     TIMxICR     LL_HRTIM_TIM_ConfigBurstDMA\n

+  *         BDTxUPDR     TIMxDIER    LL_HRTIM_TIM_ConfigBurstDMA\n

+  *         BDTxUPDR     TIMxCNT     LL_HRTIM_TIM_ConfigBurstDMA\n

+  *         BDTxUPDR     TIMxPER     LL_HRTIM_TIM_ConfigBurstDMA\n

+  *         BDTxUPDR     TIMxREP     LL_HRTIM_TIM_ConfigBurstDMA\n

+  *         BDTxUPDR     TIMxCMP1    LL_HRTIM_TIM_ConfigBurstDMA\n

+  *         BDTxUPDR     TIMxCMP2    LL_HRTIM_TIM_ConfigBurstDMA\n

+  *         BDTxUPDR     TIMxCMP3    LL_HRTIM_TIM_ConfigBurstDMA\n

+  *         BDTxUPDR     TIMxCMP4    LL_HRTIM_TIM_ConfigBurstDMA\n

+  *         BDTxUPDR     TIMxDTR     LL_HRTIM_TIM_ConfigBurstDMA\n

+  *         BDTxUPDR     TIMxSET1R   LL_HRTIM_TIM_ConfigBurstDMA\n

+  *         BDTxUPDR     TIMxRST1R   LL_HRTIM_TIM_ConfigBurstDMA\n

+  *         BDTxUPDR     TIMxSET2R   LL_HRTIM_TIM_ConfigBurstDMA\n

+  *         BDTxUPDR     TIMxRST2R   LL_HRTIM_TIM_ConfigBurstDMA\n

+  *         BDTxUPDR     TIMxEEFR1   LL_HRTIM_TIM_ConfigBurstDMA\n

+  *         BDTxUPDR     TIMxEEFR2   LL_HRTIM_TIM_ConfigBurstDMA\n

+  *         BDTxUPDR     TIMxRSTR    LL_HRTIM_TIM_ConfigBurstDMA\n

+  *         BDTxUPDR     TIMxOUTR    LL_HRTIM_TIM_ConfigBurstDMA\n

+  *         BDTxUPDR     TIMxLTCH    LL_HRTIM_TIM_ConfigBurstDMA

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  Registers Registers to be updated by the DMA request

+  *

+  *         For Master timer this parameter can be can be a combination of the following values:

+  *         @arg @ref LL_HRTIM_BURSTDMA_NONE

+  *         @arg @ref LL_HRTIM_BURSTDMA_MCR

+  *         @arg @ref LL_HRTIM_BURSTDMA_MICR

+  *         @arg @ref LL_HRTIM_BURSTDMA_MDIER

+  *         @arg @ref LL_HRTIM_BURSTDMA_MCNT

+  *         @arg @ref LL_HRTIM_BURSTDMA_MPER

+  *         @arg @ref LL_HRTIM_BURSTDMA_MREP

+  *         @arg @ref LL_HRTIM_BURSTDMA_MCMP1

+  *         @arg @ref LL_HRTIM_BURSTDMA_MCMP2

+  *         @arg @ref LL_HRTIM_BURSTDMA_MCMP3

+  *         @arg @ref LL_HRTIM_BURSTDMA_MCMP4

+  *

+  *         For Timers A..E this parameter can be can be a combination of the following values:

+  *         @arg @ref LL_HRTIM_BURSTDMA_NONE

+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMMCR

+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMICR

+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMDIER

+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMCNT

+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMPER

+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMREP

+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMCMP1

+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMCMP2

+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMCMP3

+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMCMP4

+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMDTR

+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMSET1R

+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMRST1R

+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMSET2R

+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMRST2R

+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR1

+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMEEFR2

+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMRSTR

+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMCHPR

+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMOUTR

+  *         @arg @ref LL_HRTIM_BURSTDMA_TIMFLTR

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_ConfigBurstDMA(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Registers)

+{

+

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.BDMUPR) + (4U * iTimer)));

+  WRITE_REG(*pReg, Registers);

+}

+

+/**

+  * @brief  Indicate on which output the signal is currently applied.

+  * @rmtoll TIMxISR      CPPSTAT        LL_HRTIM_TIM_GetCurrentPushPullStatus

+  * @note Only significant when the timer operates in push-pull mode.

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval CPPSTAT This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_CPPSTAT_OUTPUT1

+  *         @arg @ref LL_HRTIM_CPPSTAT_OUTPUT2

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetCurrentPushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  return (READ_BIT(*pReg, HRTIM_TIMISR_CPPSTAT));

+}

+

+/**

+  * @brief  Indicate on which output the signal was applied, in push-pull mode, balanced fault mode or delayed idle mode, when the protection was triggered.

+  * @rmtoll TIMxISR      IPPSTAT        LL_HRTIM_TIM_GetIdlePushPullStatus

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval IPPSTAT This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_IPPSTAT_OUTPUT1

+  *         @arg @ref LL_HRTIM_IPPSTAT_OUTPUT2

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetIdlePushPullStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  return (READ_BIT(*pReg, HRTIM_TIMISR_IPPSTAT));

+}

+

+/**

+  * @brief  Set the event filter for a given timer.

+  * @rmtoll EEFxR1      EE1LTCH        LL_HRTIM_TIM_SetEventFilter\n

+  *         EEFxR1      EE2LTCH        LL_HRTIM_TIM_SetEventFilter\n

+  *         EEFxR1      EE3LTCH        LL_HRTIM_TIM_SetEventFilter\n

+  *         EEFxR1      EE4LTCH        LL_HRTIM_TIM_SetEventFilter\n

+  *         EEFxR1      EE5LTCH        LL_HRTIM_TIM_SetEventFilter\n

+  *         EEFxR2      EE6LTCH        LL_HRTIM_TIM_SetEventFilter\n

+  *         EEFxR2      EE7LTCH        LL_HRTIM_TIM_SetEventFilter\n

+  *         EEFxR2      EE8LTCH        LL_HRTIM_TIM_SetEventFilter\n

+  *         EEFxR2      EE9LTCH        LL_HRTIM_TIM_SetEventFilter\n

+  *         EEFxR2      EE10LTCH       LL_HRTIM_TIM_SetEventFilter

+  * @note This function must not be called when the timer counter is enabled.

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  Event This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_EVENT_1

+  *         @arg @ref LL_HRTIM_EVENT_2

+  *         @arg @ref LL_HRTIM_EVENT_3

+  *         @arg @ref LL_HRTIM_EVENT_4

+  *         @arg @ref LL_HRTIM_EVENT_5

+  *         @arg @ref LL_HRTIM_EVENT_6

+  *         @arg @ref LL_HRTIM_EVENT_7

+  *         @arg @ref LL_HRTIM_EVENT_8

+  *         @arg @ref LL_HRTIM_EVENT_9

+  *         @arg @ref LL_HRTIM_EVENT_10

+  * @param  Filter This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_EEFLTR_NONE

+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1

+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2

+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3

+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4

+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR1

+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR2

+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR3

+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR4

+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR5

+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR6

+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR7

+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR8

+  *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2

+  *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3

+  *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM

+

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_SetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event, uint32_t Filter)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));

+  register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));

+  MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1FLTR << REG_SHIFT_TAB_EExSRC[iEvent]), (Filter << REG_SHIFT_TAB_EExSRC[iEvent]));

+}

+

+/**

+  * @brief  Get actual event filter settings for a given timer.

+  * @rmtoll EEFxR1      EE1FLTR        LL_HRTIM_TIM_GetEventFilter\n

+  *         EEFxR1      EE2FLTR        LL_HRTIM_TIM_GetEventFilter\n

+  *         EEFxR1      EE3FLTR        LL_HRTIM_TIM_GetEventFilter\n

+  *         EEFxR1      EE4FLTR        LL_HRTIM_TIM_GetEventFilter\n

+  *         EEFxR1      EE5FLTR        LL_HRTIM_TIM_GetEventFilter\n

+  *         EEFxR2      EE6FLTR        LL_HRTIM_TIM_GetEventFilter\n

+  *         EEFxR2      EE7FLTR        LL_HRTIM_TIM_GetEventFilter\n

+  *         EEFxR2      EE8FLTR        LL_HRTIM_TIM_GetEventFilter\n

+  *         EEFxR2      EE9FLTR        LL_HRTIM_TIM_GetEventFilter\n

+  *         EEFxR2      EE10FLTR       LL_HRTIM_TIM_GetEventFilter

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  Event This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_EVENT_1

+  *         @arg @ref LL_HRTIM_EVENT_2

+  *         @arg @ref LL_HRTIM_EVENT_3

+  *         @arg @ref LL_HRTIM_EVENT_4

+  *         @arg @ref LL_HRTIM_EVENT_5

+  *         @arg @ref LL_HRTIM_EVENT_6

+  *         @arg @ref LL_HRTIM_EVENT_7

+  *         @arg @ref LL_HRTIM_EVENT_8

+  *         @arg @ref LL_HRTIM_EVENT_9

+  *         @arg @ref LL_HRTIM_EVENT_10

+  * @retval Filter This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_EEFLTR_NONE

+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP1

+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP2

+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP3

+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGCMP4

+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR1

+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR2

+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR3

+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR4

+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR5

+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR6

+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR7

+  *         @arg @ref LL_HRTIM_EEFLTR_BLANKINGFLTR8

+  *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP2

+  *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGCMP3

+  *         @arg @ref LL_HRTIM_EEFLTR_WINDOWINGTIM

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventFilter(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));

+  register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));

+  return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1FLTR) << (REG_SHIFT_TAB_EExSRC[iEvent])) >> (REG_SHIFT_TAB_EExSRC[iEvent]));

+}

+

+/**

+  * @brief  Enable or disable event latch mechanism for a given timer.

+  * @rmtoll EEFxR1      EE1LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n

+  *         EEFxR1      EE2LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n

+  *         EEFxR1      EE3LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n

+  *         EEFxR1      EE4LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n

+  *         EEFxR1      EE5LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n

+  *         EEFxR2      EE6LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n

+  *         EEFxR2      EE7LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n

+  *         EEFxR2      EE8LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n

+  *         EEFxR2      EE9LTCH        LL_HRTIM_TIM_SetEventLatchStatus\n

+  *         EEFxR2      EE10LTCH       LL_HRTIM_TIM_SetEventLatchStatus

+  * @note This function must not be called when the timer counter is enabled.

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  Event This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_EVENT_1

+  *         @arg @ref LL_HRTIM_EVENT_2

+  *         @arg @ref LL_HRTIM_EVENT_3

+  *         @arg @ref LL_HRTIM_EVENT_4

+  *         @arg @ref LL_HRTIM_EVENT_5

+  *         @arg @ref LL_HRTIM_EVENT_6

+  *         @arg @ref LL_HRTIM_EVENT_7

+  *         @arg @ref LL_HRTIM_EVENT_8

+  *         @arg @ref LL_HRTIM_EVENT_9

+  *         @arg @ref LL_HRTIM_EVENT_10

+  * @param  LatchStatus This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_EELATCH_DISABLED

+  *         @arg @ref LL_HRTIM_EELATCH_ENABLED

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_TIM_SetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event,

+                                                      uint32_t LatchStatus)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));

+  register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));

+  MODIFY_REG(*pReg, (HRTIM_EEFR1_EE1LTCH << REG_SHIFT_TAB_EExSRC[iEvent]), (LatchStatus << REG_SHIFT_TAB_EExSRC[iEvent]));

+}

+

+/**

+  * @brief  Get actual event latch status for a given timer.

+  * @rmtoll EEFxR1      EE1LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n

+  *         EEFxR1      EE2LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n

+  *         EEFxR1      EE3LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n

+  *         EEFxR1      EE4LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n

+  *         EEFxR1      EE5LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n

+  *         EEFxR2      EE6LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n

+  *         EEFxR2      EE7LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n

+  *         EEFxR2      EE8LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n

+  *         EEFxR2      EE9LTCH        LL_HRTIM_TIM_GetEventLatchStatus\n

+  *         EEFxR2      EE10LTCH       LL_HRTIM_TIM_GetEventLatchStatus

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  Event This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_EVENT_1

+  *         @arg @ref LL_HRTIM_EVENT_2

+  *         @arg @ref LL_HRTIM_EVENT_3

+  *         @arg @ref LL_HRTIM_EVENT_4

+  *         @arg @ref LL_HRTIM_EVENT_5

+  *         @arg @ref LL_HRTIM_EVENT_6

+  *         @arg @ref LL_HRTIM_EVENT_7

+  *         @arg @ref LL_HRTIM_EVENT_8

+  *         @arg @ref LL_HRTIM_EVENT_9

+  *         @arg @ref LL_HRTIM_EVENT_10

+  * @retval LatchStatus This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_EELATCH_DISABLED

+  *         @arg @ref LL_HRTIM_EELATCH_ENABLED

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_TIM_GetEventLatchStatus(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Event)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - POSITION_VAL(LL_HRTIM_TIMER_A));

+  register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].EEFxR1) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer] + REG_OFFSET_TAB_EECR[iEvent]));

+  return (READ_BIT(*pReg, (uint32_t)(HRTIM_EEFR1_EE1LTCH) << REG_SHIFT_TAB_EExSRC[iEvent]) >> (REG_SHIFT_TAB_EExSRC[iEvent]));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EF_Dead_Time_Configuration Dead_Time_Configuration

+  * @{

+  */

+

+/**

+  * @brief  Configure the dead time insertion feature for a given timer.

+  * @rmtoll DTxR      DTPRSC     LL_HRTIM_DT_Config\n

+  *         DTxR      SDTF       LL_HRTIM_DT_Config\n

+  *         DTxR      SDRT       LL_HRTIM_DT_Config

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  Configuration This parameter must be a combination of all the following values:

+  *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL8 or ... or @ref LL_HRTIM_DT_PRESCALER_DIV16

+  *         @arg @ref LL_HRTIM_DT_RISING_POSITIVE or @ref LL_HRTIM_DT_RISING_NEGATIVE

+  *         @arg @ref LL_HRTIM_DT_FALLING_POSITIVE or @ref LL_HRTIM_DT_FALLING_NEGATIVE

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  MODIFY_REG(*pReg, HRTIM_DTR_SDTF | HRTIM_DTR_DTPRSC | HRTIM_DTR_SDTR, Configuration);

+}

+

+/**

+  * @brief  Set the deadtime prescaler value.

+  * @rmtoll DTxR      DTPRSC     LL_HRTIM_DT_SetPrescaler

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  Prescaler This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL8

+  *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL4

+  *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL2

+  *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV1

+  *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV2

+  *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV4

+  *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV8

+  *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV16

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  MODIFY_REG(*pReg, HRTIM_DTR_DTPRSC, Prescaler);

+}

+

+/**

+  * @brief  Get actual deadtime prescaler value.

+  * @rmtoll DTxR      DTPRSC     LL_HRTIM_DT_GetPrescaler

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval Prescaler This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL8

+  *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL4

+  *         @arg @ref LL_HRTIM_DT_PRESCALER_MUL2

+  *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV1

+  *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV2

+  *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV4

+  *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV8

+  *         @arg @ref LL_HRTIM_DT_PRESCALER_DIV16

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_DT_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  return (READ_BIT(*pReg, HRTIM_DTR_DTPRSC));

+}

+

+/**

+  * @brief  Set the deadtime rising value.

+  * @rmtoll DTxR      DTR       LL_HRTIM_DT_SetRisingValue

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  RisingValue Value between 0 and 0x1FF

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DT_SetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingValue)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  MODIFY_REG(*pReg, HRTIM_DTR_DTR, RisingValue);

+}

+

+/**

+  * @brief  Get actual deadtime rising value.

+  * @rmtoll DTxR      DTR       LL_HRTIM_DT_GetRisingValue

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval RisingValue Value between 0 and 0x1FF

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  return (READ_BIT(*pReg, HRTIM_DTR_DTR));

+}

+

+/**

+  * @brief  Set the deadtime sign on rising edge.

+  * @rmtoll DTxR      SDTR       LL_HRTIM_DT_SetRisingSign

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  RisingSign This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_DT_RISING_POSITIVE

+  *         @arg @ref LL_HRTIM_DT_RISING_NEGATIVE

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DT_SetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t RisingSign)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  MODIFY_REG(*pReg, HRTIM_DTR_SDTR, RisingSign);

+}

+

+/**

+  * @brief  Get actual deadtime sign on rising edge.

+  * @rmtoll DTxR      SDTR       LL_HRTIM_DT_GetRisingSign

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval RisingSign This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_DT_RISING_POSITIVE

+  *         @arg @ref LL_HRTIM_DT_RISING_NEGATIVE

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_DT_GetRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  return (READ_BIT(*pReg, HRTIM_DTR_SDTR));

+}

+

+/**

+  * @brief  Set the deadime falling value.

+  * @rmtoll DTxR      DTF       LL_HRTIM_DT_SetFallingValue

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  FallingValue Value between 0 and 0x1FF

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DT_SetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingValue)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  MODIFY_REG(*pReg, HRTIM_DTR_DTF, FallingValue << HRTIM_DTR_DTF_Pos);

+}

+

+/**

+  * @brief  Get actual deadtime falling value

+  * @rmtoll DTxR      DTF       LL_HRTIM_DT_GetFallingValue

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval FallingValue Value between 0 and 0x1FF

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingValue(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  return ((READ_BIT(*pReg, HRTIM_DTR_DTF)) >> HRTIM_DTR_DTF_Pos);

+}

+

+/**

+  * @brief  Set the deadtime sign on falling edge.

+  * @rmtoll DTxR      SDTF       LL_HRTIM_DT_SetFallingSign

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  FallingSign This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_DT_FALLING_POSITIVE

+  *         @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DT_SetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t FallingSign)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  MODIFY_REG(*pReg, HRTIM_DTR_SDTF, FallingSign);

+}

+

+/**

+  * @brief  Get actual deadtime sign on falling edge.

+  * @rmtoll DTxR      SDTF       LL_HRTIM_DT_GetFallingSign

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval FallingSign This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_DT_FALLING_POSITIVE

+  *         @arg @ref LL_HRTIM_DT_FALLING_NEGATIVE

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_DT_GetFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  return (READ_BIT(*pReg, HRTIM_DTR_SDTF));

+}

+

+/**

+  * @brief  Lock the deadtime value and sign on rising edge.

+  * @rmtoll DTxR      DTRLK       LL_HRTIM_DT_LockRising

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DT_LockRising(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_DTR_DTRLK);

+}

+

+/**

+  * @brief  Lock the deadtime sign on rising edge.

+  * @rmtoll DTxR      DTRSLK       LL_HRTIM_DT_LockRisingSign

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DT_LockRisingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_DTR_DTRSLK);

+}

+

+/**

+  * @brief  Lock the deadtime value and sign on falling edge.

+  * @rmtoll DTxR      DTFLK       LL_HRTIM_DT_LockFalling

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DT_LockFalling(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_DTR_DTFLK);

+}

+

+/**

+  * @brief  Lock the deadtime sign on falling edge.

+  * @rmtoll DTxR      DTFSLK       LL_HRTIM_DT_LockFallingSign

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DT_LockFallingSign(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].DTxR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_DTR_DTFSLK);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EF_Chopper_Mode_Configuration Chopper_Mode_Configuration

+  * @{

+  */

+

+/**

+  * @brief  Configure the chopper stage for a given timer.

+  * @rmtoll CHPxR      CARFRQ       LL_HRTIM_CHP_Config\n

+  *         CHPxR      CARDTY       LL_HRTIM_CHP_Config\n

+  *         CHPxR      STRTPW       LL_HRTIM_CHP_Config

+  * @note This function must not be called if the chopper mode is already

+  *       enabled for one of the timer outputs.

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  Configuration This parameter must be a combination of all the following values:

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16 or ... or @ref LL_HRTIM_CHP_PRESCALER_DIV256

+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0 or ... or @ref LL_HRTIM_CHP_DUTYCYCLE_875

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16 or ... or @ref LL_HRTIM_CHP_PULSEWIDTH_256

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_CHP_Config(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Configuration)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  MODIFY_REG(*pReg, HRTIM_CHPR_STRPW | HRTIM_CHPR_CARDTY | HRTIM_CHPR_CARFRQ, Configuration);

+}

+

+/**

+  * @brief  Set prescaler determining the carrier frequency to be added on top

+  *         of the timer output signals when chopper mode is enabled.

+  * @rmtoll CHPxR      CARFRQ       LL_HRTIM_CHP_SetPrescaler

+  * @note This function must not be called if the chopper mode is already

+  *       enabled for one of the timer outputs.

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  Prescaler This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_CHP_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t Prescaler)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  MODIFY_REG(*pReg, HRTIM_CHPR_CARFRQ, Prescaler);

+}

+

+/**

+  * @brief  Get actual chopper stage prescaler value.

+  * @rmtoll CHPxR      CARFRQ       LL_HRTIM_CHP_GetPrescaler

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval Prescaler This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV16

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV32

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV48

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV64

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV80

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV96

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV112

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV128

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV144

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV160

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV176

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV192

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV208

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV224

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV240

+  *         @arg @ref LL_HRTIM_CHP_PRESCALER_DIV256

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  return (READ_BIT(*pReg, HRTIM_CHPR_CARFRQ));

+}

+

+/**

+  * @brief  Set the chopper duty cycle.

+  * @rmtoll CHPxR      CARDTY       LL_HRTIM_CHP_SetDutyCycle

+  * @note Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)

+  * @note This function must not be called if the chopper mode is already

+  *       enabled for one of the timer outputs.

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  DutyCycle This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0

+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125

+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250

+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375

+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500

+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625

+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750

+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_CHP_SetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t DutyCycle)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  MODIFY_REG(*pReg, HRTIM_CHPR_CARDTY, DutyCycle);

+}

+

+/**

+  * @brief  Get actual chopper duty cycle.

+  * @rmtoll CHPxR      CARDTY       LL_HRTIM_CHP_GetDutyCycle

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval DutyCycle This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_0

+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_125

+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_250

+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_375

+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_500

+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_625

+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_750

+  *         @arg @ref LL_HRTIM_CHP_DUTYCYCLE_875

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetDutyCycle(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  return (READ_BIT(*pReg, HRTIM_CHPR_CARDTY));

+}

+

+/**

+  * @brief  Set the start pulse width.

+  * @rmtoll CHPxR      STRPW       LL_HRTIM_CHP_SetPulseWidth

+  * @note This function must not be called if the chopper mode is already

+  *       enabled for one of the timer outputs.

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @param  PulseWidth This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_CHP_SetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer, uint32_t PulseWidth)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  MODIFY_REG(*pReg, HRTIM_CHPR_STRPW, PulseWidth);

+}

+

+/**

+  * @brief  Get actual start pulse width.

+  * @rmtoll CHPxR      STRPW       LL_HRTIM_CHP_GetPulseWidth

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval PulseWidth This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_16

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_32

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_48

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_64

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_80

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_96

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_112

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_128

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_144

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_160

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_176

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_192

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_208

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_224

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_240

+  *         @arg @ref LL_HRTIM_CHP_PULSEWIDTH_256

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_CHP_GetPulseWidth(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_TACEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].CHPxR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  return (READ_BIT(*pReg, HRTIM_CHPR_STRPW));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EF_Output_Management Output_Management

+  * @{

+  */

+

+/**

+  * @brief  Set the timer output set source.

+  * @rmtoll SETx1R      SST          LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      RESYNC       LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      PER          LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      CMP1         LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      CMP2         LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      CMP3         LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      CMP4         LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      MSTPER       LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      MSTCMP1      LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      MSTCMP2      LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      MSTCMP3      LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      MSTCMP4      LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      TIMEVNT1     LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      TIMEVNT2     LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      TIMEVNT3     LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      TIMEVNT4     LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      TIMEVNT5     LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      TIMEVNT6     LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      TIMEVNT7     LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      TIMEVNT8     LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      TIMEVNT9     LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      EXEVNT1      LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      EXEVNT2      LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      EXEVNT3      LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      EXEVNT4      LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      EXEVNT5      LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      EXEVNT6      LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      EXEVNT7      LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      EXEVNT8      LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      EXEVNT9      LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      EXEVNT10     LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      UPDATE       LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      SST          LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      RESYNC       LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      PER          LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      CMP1         LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      CMP2         LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      CMP3         LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      CMP4         LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      MSTPER       LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      MSTCMP1      LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      MSTCMP2      LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      MSTCMP3      LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      MSTCMP4      LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      TIMEVNT1     LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      TIMEVNT2     LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      TIMEVNT3     LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      TIMEVNT4     LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      TIMEVNT5     LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      TIMEVNT6     LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      TIMEVNT7     LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      TIMEVNT8     LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      TIMEVNT9     LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      EXEVNT1      LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      EXEVNT2      LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      EXEVNT3      LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      EXEVNT4      LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      EXEVNT5      LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      EXEVNT6      LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      EXEVNT7      LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      EXEVNT8      LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      EXEVNT9      LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      EXEVNT10     LL_HRTIM_OUT_SetOutputSetSrc\n

+  *         SETx1R      UPDATE       LL_HRTIM_OUT_SetOutputSetSrc

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Output This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUTPUT_TA1

+  *         @arg @ref LL_HRTIM_OUTPUT_TA2

+  *         @arg @ref LL_HRTIM_OUTPUT_TB1

+  *         @arg @ref LL_HRTIM_OUTPUT_TB2

+  *         @arg @ref LL_HRTIM_OUTPUT_TC1

+  *         @arg @ref LL_HRTIM_OUTPUT_TC2

+  *         @arg @ref LL_HRTIM_OUTPUT_TD1

+  *         @arg @ref LL_HRTIM_OUTPUT_TD2

+  *         @arg @ref LL_HRTIM_OUTPUT_TE1

+  *         @arg @ref LL_HRTIM_OUTPUT_TE2

+  * @param SetSrc This parameter can be a combination of the following values:

+  *         @arg @ref LL_HRTIM_CROSSBAR_NONE

+  *         @arg @ref LL_HRTIM_CROSSBAR_RESYNC

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMPER

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4

+  *         @arg @ref LL_HRTIM_CROSSBAR_MASTERPER

+  *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1

+  *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2

+  *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3

+  *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_1

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_2

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_3

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_4

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_5

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_6

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_7

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_8

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_9

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_10

+  *         @arg @ref LL_HRTIM_CROSSBAR_UPDATE

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_OUT_SetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t SetSrc)

+{

+  register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +

+                                                              REG_OFFSET_TAB_SETxR[iOutput]));

+  WRITE_REG(*pReg, SetSrc);

+}

+

+/**

+  * @brief  Get the timer output set source.

+  * @rmtoll SETx1R      SST          LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      RESYNC       LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      PER          LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      CMP1         LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      CMP2         LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      CMP3         LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      CMP4         LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      MSTPER       LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      MSTCMP1      LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      MSTCMP2      LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      MSTCMP3      LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      MSTCMP4      LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      TIMEVNT1     LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      TIMEVNT2     LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      TIMEVNT3     LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      TIMEVNT4     LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      TIMEVNT5     LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      TIMEVNT6     LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      TIMEVNT7     LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      TIMEVNT8     LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      TIMEVNT9     LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      EXEVNT1      LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      EXEVNT2      LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      EXEVNT3      LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      EXEVNT4      LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      EXEVNT5      LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      EXEVNT6      LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      EXEVNT7      LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      EXEVNT8      LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      EXEVNT9      LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      EXEVNT10     LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      UPDATE       LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      SST          LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      RESYNC       LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      PER          LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      CMP1         LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      CMP2         LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      CMP3         LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      CMP4         LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      MSTPER       LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      MSTCMP1      LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      MSTCMP2      LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      MSTCMP3      LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      MSTCMP4      LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      TIMEVNT1     LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      TIMEVNT2     LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      TIMEVNT3     LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      TIMEVNT4     LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      TIMEVNT5     LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      TIMEVNT6     LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      TIMEVNT7     LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      TIMEVNT8     LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      TIMEVNT9     LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      EXEVNT1      LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      EXEVNT2      LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      EXEVNT3      LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      EXEVNT4      LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      EXEVNT5      LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      EXEVNT6      LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      EXEVNT7      LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      EXEVNT8      LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      EXEVNT9      LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      EXEVNT10     LL_HRTIM_OUT_GetOutputSetSrc\n

+  *         SETx1R      UPDATE       LL_HRTIM_OUT_GetOutputSetSrc

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Output This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUTPUT_TA1

+  *         @arg @ref LL_HRTIM_OUTPUT_TA2

+  *         @arg @ref LL_HRTIM_OUTPUT_TB1

+  *         @arg @ref LL_HRTIM_OUTPUT_TB2

+  *         @arg @ref LL_HRTIM_OUTPUT_TC1

+  *         @arg @ref LL_HRTIM_OUTPUT_TC2

+  *         @arg @ref LL_HRTIM_OUTPUT_TD1

+  *         @arg @ref LL_HRTIM_OUTPUT_TD2

+  *         @arg @ref LL_HRTIM_OUTPUT_TE1

+  *         @arg @ref LL_HRTIM_OUTPUT_TE2

+  * @retval SetSrc This parameter can be a combination of the following values:

+  *         @arg @ref LL_HRTIM_CROSSBAR_NONE

+  *         @arg @ref LL_HRTIM_CROSSBAR_RESYNC

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMPER

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4

+  *         @arg @ref LL_HRTIM_CROSSBAR_MASTERPER

+  *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1

+  *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2

+  *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3

+  *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_1

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_2

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_3

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_4

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_5

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_6

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_7

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_8

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_9

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_10

+  *         @arg @ref LL_HRTIM_CROSSBAR_UPDATE

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputSetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output)

+{

+  register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +

+                                                                    REG_OFFSET_TAB_SETxR[iOutput]));

+  return (uint32_t) READ_REG(*pReg);

+}

+

+/**

+  * @brief  Set the timer output reset source.

+  * @rmtoll RSTx1R      RST          LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      RESYNC       LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      PER          LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      CMP1         LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      CMP2         LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      CMP3         LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      CMP4         LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      MSTPER       LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      MSTCMP1      LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      MSTCMP2      LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      MSTCMP3      LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      MSTCMP4      LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT1     LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT2     LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT3     LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT4     LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT5     LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT6     LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT7     LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT8     LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT9     LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      EXEVNT1      LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      EXEVNT2      LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      EXEVNT3      LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      EXEVNT4      LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      EXEVNT5      LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      EXEVNT6      LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      EXEVNT7      LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      EXEVNT8      LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      EXEVNT9      LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      EXEVNT10     LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      UPDATE       LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      RST          LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      RESYNC       LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      PER          LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      CMP1         LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      CMP2         LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      CMP3         LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      CMP4         LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      MSTPER       LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      MSTCMP1      LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      MSTCMP2      LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      MSTCMP3      LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      MSTCMP4      LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT1     LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT2     LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT3     LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT4     LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT5     LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT6     LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT7     LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT8     LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT9     LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      EXEVNT1      LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      EXEVNT2      LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      EXEVNT3      LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      EXEVNT4      LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      EXEVNT5      LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      EXEVNT6      LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      EXEVNT7      LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      EXEVNT8      LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      EXEVNT9      LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      EXEVNT10     LL_HRTIM_OUT_SetOutputResetSrc\n

+  *         RSTx1R      UPDATE       LL_HRTIM_OUT_SetOutputResetSrc

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Output This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUTPUT_TA1

+  *         @arg @ref LL_HRTIM_OUTPUT_TA2

+  *         @arg @ref LL_HRTIM_OUTPUT_TB1

+  *         @arg @ref LL_HRTIM_OUTPUT_TB2

+  *         @arg @ref LL_HRTIM_OUTPUT_TC1

+  *         @arg @ref LL_HRTIM_OUTPUT_TC2

+  *         @arg @ref LL_HRTIM_OUTPUT_TD1

+  *         @arg @ref LL_HRTIM_OUTPUT_TD2

+  *         @arg @ref LL_HRTIM_OUTPUT_TE1

+  *         @arg @ref LL_HRTIM_OUTPUT_TE2

+  * @param ResetSrc This parameter can be a combination of the following values:

+  *         @arg @ref LL_HRTIM_CROSSBAR_NONE

+  *         @arg @ref LL_HRTIM_CROSSBAR_RESYNC

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMPER

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4

+  *         @arg @ref LL_HRTIM_CROSSBAR_MASTERPER

+  *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1

+  *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2

+  *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3

+  *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_1

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_2

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_3

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_4

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_5

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_6

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_7

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_8

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_9

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_10

+  *         @arg @ref LL_HRTIM_CROSSBAR_UPDATE

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_OUT_SetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ResetSrc)

+{

+  register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +

+                                                              REG_OFFSET_TAB_SETxR[iOutput]));

+  WRITE_REG(*pReg, ResetSrc);

+}

+

+/**

+  * @brief  Get the timer output set source.

+  * @rmtoll RSTx1R      RST          LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      RESYNC       LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      PER          LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      CMP1         LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      CMP2         LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      CMP3         LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      CMP4         LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      MSTPER       LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      MSTCMP1      LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      MSTCMP2      LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      MSTCMP3      LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      MSTCMP4      LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT1     LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT2     LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT3     LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT4     LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT5     LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT6     LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT7     LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT8     LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT9     LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      EXEVNT1      LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      EXEVNT2      LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      EXEVNT3      LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      EXEVNT4      LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      EXEVNT5      LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      EXEVNT6      LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      EXEVNT7      LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      EXEVNT8      LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      EXEVNT9      LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      EXEVNT10     LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      UPDATE       LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      RST          LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      RESYNC       LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      PER          LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      CMP1         LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      CMP2         LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      CMP3         LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      CMP4         LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      MSTPER       LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      MSTCMP1      LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      MSTCMP2      LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      MSTCMP3      LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      MSTCMP4      LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT1     LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT2     LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT3     LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT4     LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT5     LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT6     LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT7     LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT8     LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      TIMEVNT9     LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      EXEVNT1      LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      EXEVNT2      LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      EXEVNT3      LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      EXEVNT4      LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      EXEVNT5      LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      EXEVNT6      LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      EXEVNT7      LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      EXEVNT8      LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      EXEVNT9      LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      EXEVNT10     LL_HRTIM_OUT_GetOutputResetSrc\n

+  *         RSTx1R      UPDATE       LL_HRTIM_OUT_GetOutputResetSrc

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Output This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUTPUT_TA1

+  *         @arg @ref LL_HRTIM_OUTPUT_TA2

+  *         @arg @ref LL_HRTIM_OUTPUT_TB1

+  *         @arg @ref LL_HRTIM_OUTPUT_TB2

+  *         @arg @ref LL_HRTIM_OUTPUT_TC1

+  *         @arg @ref LL_HRTIM_OUTPUT_TC2

+  *         @arg @ref LL_HRTIM_OUTPUT_TD1

+  *         @arg @ref LL_HRTIM_OUTPUT_TD2

+  *         @arg @ref LL_HRTIM_OUTPUT_TE1

+  *         @arg @ref LL_HRTIM_OUTPUT_TE2

+  * @retval ResetSrc This parameter can be a combination of the following values:

+  *         @arg @ref LL_HRTIM_CROSSBAR_NONE

+  *         @arg @ref LL_HRTIM_CROSSBAR_RESYNC

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMPER

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP1

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP2

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP3

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMCMP4

+  *         @arg @ref LL_HRTIM_CROSSBAR_MASTERPER

+  *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP1

+  *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP2

+  *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP3

+  *         @arg @ref LL_HRTIM_CROSSBAR_MASTERCMP4

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_1

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_2

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_3

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_4

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_5

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_6

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_7

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_8

+  *         @arg @ref LL_HRTIM_CROSSBAR_TIMEV_9

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_1

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_2

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_3

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_4

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_5

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_6

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_7

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_8

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_9

+  *         @arg @ref LL_HRTIM_CROSSBAR_EEV_10

+  *         @arg @ref LL_HRTIM_CROSSBAR_UPDATE

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetOutputResetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Output)

+{

+  register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].RSTx1R) +

+                                                                    REG_OFFSET_TAB_SETxR[iOutput]));

+  return (uint32_t) READ_REG(*pReg);

+}

+

+/**

+  * @brief  Configure a timer output.

+  * @rmtoll OUTxR      POL1          LL_HRTIM_OUT_Config\n

+  *         OUTxR      IDLEM1        LL_HRTIM_OUT_Config\n

+  *         OUTxR      IDLES1        LL_HRTIM_OUT_Config\n

+  *         OUTxR      FAULT1        LL_HRTIM_OUT_Config\n

+  *         OUTxR      CHP1          LL_HRTIM_OUT_Config\n

+  *         OUTxR      DIDL1         LL_HRTIM_OUT_Config\n

+  *         OUTxR      POL2          LL_HRTIM_OUT_Config\n

+  *         OUTxR      IDLEM2        LL_HRTIM_OUT_Config\n

+  *         OUTxR      IDLES2        LL_HRTIM_OUT_Config\n

+  *         OUTxR      FAULT2        LL_HRTIM_OUT_Config\n

+  *         OUTxR      CHP2          LL_HRTIM_OUT_Config\n

+  *         OUTxR      DIDL2         LL_HRTIM_OUT_Config

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Output This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUTPUT_TA1

+  *         @arg @ref LL_HRTIM_OUTPUT_TA2

+  *         @arg @ref LL_HRTIM_OUTPUT_TB1

+  *         @arg @ref LL_HRTIM_OUTPUT_TB2

+  *         @arg @ref LL_HRTIM_OUTPUT_TC1

+  *         @arg @ref LL_HRTIM_OUTPUT_TC2

+  *         @arg @ref LL_HRTIM_OUTPUT_TD1

+  *         @arg @ref LL_HRTIM_OUTPUT_TD2

+  *         @arg @ref LL_HRTIM_OUTPUT_TE1

+  *         @arg @ref LL_HRTIM_OUTPUT_TE2

+  * @param  Configuration This parameter must be a combination of all the following values:

+  *         @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY or @ref LL_HRTIM_OUT_NEGATIVE_POLARITY

+  *         @arg @ref LL_HRTIM_OUT_NO_IDLE or @ref LL_HRTIM_OUT_IDLE_WHEN_BURST

+  *         @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE or @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE

+  *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION or @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE or @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ

+  *         @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED or @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED

+  *         @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR or @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_OUT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Configuration)

+{

+  register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +

+                                                              REG_OFFSET_TAB_OUTxR[iOutput]));

+  MODIFY_REG(*pReg, (HRTIM_OUT_CONFIG_MASK << REG_SHIFT_TAB_OUTxR[iOutput]),

+             (Configuration << REG_SHIFT_TAB_OUTxR[iOutput]));

+}

+

+/**

+  * @brief  Set the polarity of a timer output.

+  * @rmtoll OUTxR      POL1          LL_HRTIM_OUT_SetPolarity\n

+  *         OUTxR      POL2          LL_HRTIM_OUT_SetPolarity

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Output This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUTPUT_TA1

+  *         @arg @ref LL_HRTIM_OUTPUT_TA2

+  *         @arg @ref LL_HRTIM_OUTPUT_TB1

+  *         @arg @ref LL_HRTIM_OUTPUT_TB2

+  *         @arg @ref LL_HRTIM_OUTPUT_TC1

+  *         @arg @ref LL_HRTIM_OUTPUT_TC2

+  *         @arg @ref LL_HRTIM_OUTPUT_TD1

+  *         @arg @ref LL_HRTIM_OUTPUT_TD2

+  *         @arg @ref LL_HRTIM_OUTPUT_TE1

+  *         @arg @ref LL_HRTIM_OUTPUT_TE2

+  * @param  Polarity This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY

+  *         @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_OUT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t Polarity)

+{

+  register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +

+                                                              REG_OFFSET_TAB_OUTxR[iOutput]));

+  MODIFY_REG(*pReg, (HRTIM_OUTR_POL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (Polarity << REG_SHIFT_TAB_OUTxR[iOutput]));

+}

+

+/**

+  * @brief  Get actual polarity of the timer output.

+  * @rmtoll OUTxR      POL1          LL_HRTIM_OUT_GetPolarity\n

+  *         OUTxR      POL2          LL_HRTIM_OUT_GetPolarity

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Output This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUTPUT_TA1

+  *         @arg @ref LL_HRTIM_OUTPUT_TA2

+  *         @arg @ref LL_HRTIM_OUTPUT_TB1

+  *         @arg @ref LL_HRTIM_OUTPUT_TB2

+  *         @arg @ref LL_HRTIM_OUTPUT_TC1

+  *         @arg @ref LL_HRTIM_OUTPUT_TC2

+  *         @arg @ref LL_HRTIM_OUTPUT_TD1

+  *         @arg @ref LL_HRTIM_OUTPUT_TD2

+  *         @arg @ref LL_HRTIM_OUTPUT_TE1

+  *         @arg @ref LL_HRTIM_OUTPUT_TE2

+  * @retval Polarity This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUT_POSITIVE_POLARITY

+  *         @arg @ref LL_HRTIM_OUT_NEGATIVE_POLARITY

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Output)

+{

+  register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +

+                                                                    REG_OFFSET_TAB_OUTxR[iOutput]));

+  return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_POL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);

+}

+

+/**

+  * @brief  Set the output IDLE mode.

+  * @rmtoll OUTxR      IDLEM1          LL_HRTIM_OUT_SetIdleMode\n

+  *         OUTxR      IDLEM2          LL_HRTIM_OUT_SetIdleMode

+  * @note This function must not be called when the burst mode is active

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Output This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUTPUT_TA1

+  *         @arg @ref LL_HRTIM_OUTPUT_TA2

+  *         @arg @ref LL_HRTIM_OUTPUT_TB1

+  *         @arg @ref LL_HRTIM_OUTPUT_TB2

+  *         @arg @ref LL_HRTIM_OUTPUT_TC1

+  *         @arg @ref LL_HRTIM_OUTPUT_TC2

+  *         @arg @ref LL_HRTIM_OUTPUT_TD1

+  *         @arg @ref LL_HRTIM_OUTPUT_TD2

+  *         @arg @ref LL_HRTIM_OUTPUT_TE1

+  *         @arg @ref LL_HRTIM_OUTPUT_TE2

+  * @param  IdleMode This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUT_NO_IDLE

+  *         @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_OUT_SetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleMode)

+{

+  register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +

+                                                              REG_OFFSET_TAB_OUTxR[iOutput]));

+  MODIFY_REG(*pReg, (HRTIM_OUTR_IDLM1 << (REG_SHIFT_TAB_OUTxR[iOutput])), (IdleMode << (REG_SHIFT_TAB_OUTxR[iOutput])));

+}

+

+/**

+  * @brief  Get actual output IDLE mode.

+  * @rmtoll OUTxR      IDLEM1          LL_HRTIM_OUT_GetIdleMode\n

+  *         OUTxR      IDLEM2          LL_HRTIM_OUT_GetIdleMode

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Output This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUTPUT_TA1

+  *         @arg @ref LL_HRTIM_OUTPUT_TA2

+  *         @arg @ref LL_HRTIM_OUTPUT_TB1

+  *         @arg @ref LL_HRTIM_OUTPUT_TB2

+  *         @arg @ref LL_HRTIM_OUTPUT_TC1

+  *         @arg @ref LL_HRTIM_OUTPUT_TC2

+  *         @arg @ref LL_HRTIM_OUTPUT_TD1

+  *         @arg @ref LL_HRTIM_OUTPUT_TD2

+  *         @arg @ref LL_HRTIM_OUTPUT_TE1

+  *         @arg @ref LL_HRTIM_OUTPUT_TE2

+  * @retval IdleMode This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUT_NO_IDLE

+  *         @arg @ref LL_HRTIM_OUT_IDLE_WHEN_BURST

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)

+{

+  register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +

+                                                                    REG_OFFSET_TAB_OUTxR[iOutput]));

+  return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLM1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);

+}

+

+/**

+  * @brief  Set the output IDLE level.

+  * @rmtoll OUTxR      IDLES1          LL_HRTIM_OUT_SetIdleLevel\n

+  *         OUTxR      IDLES2          LL_HRTIM_OUT_SetIdleLevel

+  * @note This function must be called prior enabling the timer.

+  * @note Idle level isn't relevant when the output idle mode is set to LL_HRTIM_OUT_NO_IDLE.

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Output This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUTPUT_TA1

+  *         @arg @ref LL_HRTIM_OUTPUT_TA2

+  *         @arg @ref LL_HRTIM_OUTPUT_TB1

+  *         @arg @ref LL_HRTIM_OUTPUT_TB2

+  *         @arg @ref LL_HRTIM_OUTPUT_TC1

+  *         @arg @ref LL_HRTIM_OUTPUT_TC2

+  *         @arg @ref LL_HRTIM_OUTPUT_TD1

+  *         @arg @ref LL_HRTIM_OUTPUT_TD2

+  *         @arg @ref LL_HRTIM_OUTPUT_TE1

+  *         @arg @ref LL_HRTIM_OUTPUT_TE2

+  * @param  IdleLevel This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE

+  *         @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_OUT_SetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t IdleLevel)

+{

+  register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +

+                                                              REG_OFFSET_TAB_OUTxR[iOutput]));

+  MODIFY_REG(*pReg, (HRTIM_OUTR_IDLES1 << REG_SHIFT_TAB_OUTxR[iOutput]), (IdleLevel << REG_SHIFT_TAB_OUTxR[iOutput]));

+}

+

+/**

+  * @brief  Get actual output IDLE level.

+  * @rmtoll OUTxR      IDLES1          LL_HRTIM_OUT_GetIdleLevel\n

+  *         OUTxR      IDLES2          LL_HRTIM_OUT_GetIdleLevel

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Output This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUTPUT_TA1

+  *         @arg @ref LL_HRTIM_OUTPUT_TA2

+  *         @arg @ref LL_HRTIM_OUTPUT_TB1

+  *         @arg @ref LL_HRTIM_OUTPUT_TB2

+  *         @arg @ref LL_HRTIM_OUTPUT_TC1

+  *         @arg @ref LL_HRTIM_OUTPUT_TC2

+  *         @arg @ref LL_HRTIM_OUTPUT_TD1

+  *         @arg @ref LL_HRTIM_OUTPUT_TD2

+  *         @arg @ref LL_HRTIM_OUTPUT_TE1

+  *         @arg @ref LL_HRTIM_OUTPUT_TE2

+  * @retval IdleLevel This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUT_IDLELEVEL_INACTIVE

+  *         @arg @ref LL_HRTIM_OUT_IDLELEVEL_ACTIVE

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetIdleLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output)

+{

+  register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +

+                                                                    REG_OFFSET_TAB_OUTxR[iOutput]));

+  return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_IDLES1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);

+}

+

+/**

+  * @brief  Set the output FAULT state.

+  * @rmtoll OUTxR      FAULT1          LL_HRTIM_OUT_SetFaultState\n

+  *         OUTxR      FAULT2          LL_HRTIM_OUT_SetFaultState

+  * @note This function must not called when the timer is enabled and a fault

+  *       channel is enabled at timer level.

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Output This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUTPUT_TA1

+  *         @arg @ref LL_HRTIM_OUTPUT_TA2

+  *         @arg @ref LL_HRTIM_OUTPUT_TB1

+  *         @arg @ref LL_HRTIM_OUTPUT_TB2

+  *         @arg @ref LL_HRTIM_OUTPUT_TC1

+  *         @arg @ref LL_HRTIM_OUTPUT_TC2

+  *         @arg @ref LL_HRTIM_OUTPUT_TD1

+  *         @arg @ref LL_HRTIM_OUTPUT_TD2

+  *         @arg @ref LL_HRTIM_OUTPUT_TE1

+  *         @arg @ref LL_HRTIM_OUTPUT_TE2

+  * @param  FaultState This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION

+  *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE

+  *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE

+  *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_OUT_SetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t FaultState)

+{

+  register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +

+                                                              REG_OFFSET_TAB_OUTxR[iOutput]));

+  MODIFY_REG(*pReg, (HRTIM_OUTR_FAULT1 << REG_SHIFT_TAB_OUTxR[iOutput]), (FaultState << REG_SHIFT_TAB_OUTxR[iOutput]));

+}

+

+/**

+  * @brief  Get actual FAULT state.

+  * @rmtoll OUTxR      FAULT1          LL_HRTIM_OUT_GetFaultState\n

+  *         OUTxR      FAULT2          LL_HRTIM_OUT_GetFaultState

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Output This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUTPUT_TA1

+  *         @arg @ref LL_HRTIM_OUTPUT_TA2

+  *         @arg @ref LL_HRTIM_OUTPUT_TB1

+  *         @arg @ref LL_HRTIM_OUTPUT_TB2

+  *         @arg @ref LL_HRTIM_OUTPUT_TC1

+  *         @arg @ref LL_HRTIM_OUTPUT_TC2

+  *         @arg @ref LL_HRTIM_OUTPUT_TD1

+  *         @arg @ref LL_HRTIM_OUTPUT_TD2

+  *         @arg @ref LL_HRTIM_OUTPUT_TE1

+  *         @arg @ref LL_HRTIM_OUTPUT_TE2

+  * @retval FaultState This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_NO_ACTION

+  *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_ACTIVE

+  *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_INACTIVE

+  *         @arg @ref LL_HRTIM_OUT_FAULTSTATE_HIGHZ

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetFaultState(HRTIM_TypeDef *HRTIMx, uint32_t Output)

+{

+  register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +

+                                                                    REG_OFFSET_TAB_OUTxR[iOutput]));

+  return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_FAULT1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);

+}

+

+/**

+  * @brief  Set the output chopper mode.

+  * @rmtoll OUTxR      CHP1          LL_HRTIM_OUT_SetChopperMode\n

+  *         OUTxR      CHP2          LL_HRTIM_OUT_SetChopperMode

+  * @note This function must not called when the timer is enabled.

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Output This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUTPUT_TA1

+  *         @arg @ref LL_HRTIM_OUTPUT_TA2

+  *         @arg @ref LL_HRTIM_OUTPUT_TB1

+  *         @arg @ref LL_HRTIM_OUTPUT_TB2

+  *         @arg @ref LL_HRTIM_OUTPUT_TC1

+  *         @arg @ref LL_HRTIM_OUTPUT_TC2

+  *         @arg @ref LL_HRTIM_OUTPUT_TD1

+  *         @arg @ref LL_HRTIM_OUTPUT_TD2

+  *         @arg @ref LL_HRTIM_OUTPUT_TE1

+  *         @arg @ref LL_HRTIM_OUTPUT_TE2

+  * @param  ChopperMode This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED

+  *         @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_OUT_SetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t ChopperMode)

+{

+  register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +

+                                                              REG_OFFSET_TAB_OUTxR[iOutput]));

+  MODIFY_REG(*pReg, (HRTIM_OUTR_CHP1 << REG_SHIFT_TAB_OUTxR[iOutput]), (ChopperMode << REG_SHIFT_TAB_OUTxR[iOutput]));

+}

+

+/**

+  * @brief  Get actual output chopper mode

+  * @rmtoll OUTxR      CHP1          LL_HRTIM_OUT_GetChopperMode\n

+  *         OUTxR      CHP2          LL_HRTIM_OUT_GetChopperMode

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Output This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUTPUT_TA1

+  *         @arg @ref LL_HRTIM_OUTPUT_TA2

+  *         @arg @ref LL_HRTIM_OUTPUT_TB1

+  *         @arg @ref LL_HRTIM_OUTPUT_TB2

+  *         @arg @ref LL_HRTIM_OUTPUT_TC1

+  *         @arg @ref LL_HRTIM_OUTPUT_TC2

+  *         @arg @ref LL_HRTIM_OUTPUT_TD1

+  *         @arg @ref LL_HRTIM_OUTPUT_TD2

+  *         @arg @ref LL_HRTIM_OUTPUT_TE1

+  *         @arg @ref LL_HRTIM_OUTPUT_TE2

+  * @retval ChopperMode This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUT_CHOPPERMODE_DISABLED

+  *         @arg @ref LL_HRTIM_OUT_CHOPPERMODE_ENABLED

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetChopperMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)

+{

+  register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +

+                                                                    REG_OFFSET_TAB_OUTxR[iOutput]));

+  return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_CHP1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);

+}

+

+/**

+  * @brief  Set the output burst mode entry mode.

+  * @rmtoll OUTxR      DIDL1          LL_HRTIM_OUT_SetBMEntryMode\n

+  *         OUTxR      DIDL2          LL_HRTIM_OUT_SetBMEntryMode

+  * @note This function must not called when the timer is enabled.

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Output This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUTPUT_TA1

+  *         @arg @ref LL_HRTIM_OUTPUT_TA2

+  *         @arg @ref LL_HRTIM_OUTPUT_TB1

+  *         @arg @ref LL_HRTIM_OUTPUT_TB2

+  *         @arg @ref LL_HRTIM_OUTPUT_TC1

+  *         @arg @ref LL_HRTIM_OUTPUT_TC2

+  *         @arg @ref LL_HRTIM_OUTPUT_TD1

+  *         @arg @ref LL_HRTIM_OUTPUT_TD2

+  *         @arg @ref LL_HRTIM_OUTPUT_TE1

+  *         @arg @ref LL_HRTIM_OUTPUT_TE2

+  * @param  BMEntryMode This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR

+  *         @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_OUT_SetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t BMEntryMode)

+{

+  register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +

+                                                              REG_OFFSET_TAB_OUTxR[iOutput]));

+  MODIFY_REG(*pReg, (HRTIM_OUTR_DIDL1 << REG_SHIFT_TAB_OUTxR[iOutput]), (BMEntryMode << REG_SHIFT_TAB_OUTxR[iOutput]));

+}

+

+/**

+  * @brief  Get actual output burst mode entry mode.

+  * @rmtoll OUTxR      DIDL1          LL_HRTIM_OUT_GetBMEntryMode\n

+  *         OUTxR      DIDL2          LL_HRTIM_OUT_GetBMEntryMode

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Output This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUTPUT_TA1

+  *         @arg @ref LL_HRTIM_OUTPUT_TA2

+  *         @arg @ref LL_HRTIM_OUTPUT_TB1

+  *         @arg @ref LL_HRTIM_OUTPUT_TB2

+  *         @arg @ref LL_HRTIM_OUTPUT_TC1

+  *         @arg @ref LL_HRTIM_OUTPUT_TC2

+  *         @arg @ref LL_HRTIM_OUTPUT_TD1

+  *         @arg @ref LL_HRTIM_OUTPUT_TD2

+  *         @arg @ref LL_HRTIM_OUTPUT_TE1

+  *         @arg @ref LL_HRTIM_OUTPUT_TE2

+  * @retval BMEntryMode This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_REGULAR

+  *         @arg @ref LL_HRTIM_OUT_BM_ENTRYMODE_DELAYED

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetBMEntryMode(HRTIM_TypeDef *HRTIMx, uint32_t Output)

+{

+  register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].OUTxR) +

+                                                                    REG_OFFSET_TAB_OUTxR[iOutput]));

+  return (READ_BIT(*pReg, (uint32_t)(HRTIM_OUTR_DIDL1) << REG_SHIFT_TAB_OUTxR[iOutput]) >> REG_SHIFT_TAB_OUTxR[iOutput]);

+}

+

+/**

+  * @brief  Get the level (active or inactive) of the designated output when the

+  *         delayed protection was triggered.

+  * @rmtoll TIMxISR      O1SRSR          LL_HRTIM_OUT_GetDLYPRTOutStatus\n

+  *         TIMxISR      O2SRSR          LL_HRTIM_OUT_GetDLYPRTOutStatus

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Output This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUTPUT_TA1

+  *         @arg @ref LL_HRTIM_OUTPUT_TA2

+  *         @arg @ref LL_HRTIM_OUTPUT_TB1

+  *         @arg @ref LL_HRTIM_OUTPUT_TB2

+  *         @arg @ref LL_HRTIM_OUTPUT_TC1

+  *         @arg @ref LL_HRTIM_OUTPUT_TC2

+  *         @arg @ref LL_HRTIM_OUTPUT_TD1

+  *         @arg @ref LL_HRTIM_OUTPUT_TD2

+  *         @arg @ref LL_HRTIM_OUTPUT_TE1

+  *         @arg @ref LL_HRTIM_OUTPUT_TE2

+  * @retval OutputLevel This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE

+  *         @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetDLYPRTOutStatus(HRTIM_TypeDef *HRTIMx, uint32_t Output)

+{

+  register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +

+                                                                    REG_OFFSET_TAB_OUTxR[iOutput]));

+  return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1STAT) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>

+          HRTIM_TIMISR_O1STAT_Pos);

+}

+

+/**

+  * @brief  Force the timer output to its active or inactive level.

+  * @rmtoll SETx1R      SST          LL_HRTIM_OUT_ForceLevel\n

+  *         RSTx1R      SRT          LL_HRTIM_OUT_ForceLevel\n

+  *         SETx2R      SST          LL_HRTIM_OUT_ForceLevel\n

+  *         RSTx2R      SRT          LL_HRTIM_OUT_ForceLevel

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Output This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUTPUT_TA1

+  *         @arg @ref LL_HRTIM_OUTPUT_TA2

+  *         @arg @ref LL_HRTIM_OUTPUT_TB1

+  *         @arg @ref LL_HRTIM_OUTPUT_TB2

+  *         @arg @ref LL_HRTIM_OUTPUT_TC1

+  *         @arg @ref LL_HRTIM_OUTPUT_TC2

+  *         @arg @ref LL_HRTIM_OUTPUT_TD1

+  *         @arg @ref LL_HRTIM_OUTPUT_TD2

+  *         @arg @ref LL_HRTIM_OUTPUT_TE1

+  *         @arg @ref LL_HRTIM_OUTPUT_TE2

+  * @param  OutputLevel This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE

+  *         @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_OUT_ForceLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output, uint32_t OutputLevel)

+{

+  const uint8_t REG_OFFSET_TAB_OUT_LEVEL[] =

+  {

+    0x04U,   /* 0: LL_HRTIM_OUT_LEVEL_INACTIVE  */

+    0x00U    /* 1: LL_HRTIM_OUT_LEVEL_ACTIVE  */

+  };

+

+  register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].SETx1R) +

+                                                              REG_OFFSET_TAB_SETxR[iOutput] + REG_OFFSET_TAB_OUT_LEVEL[OutputLevel]));

+  SET_BIT(*pReg, HRTIM_SET1R_SST);

+}

+

+/**

+  * @brief  Get actual output level, before the output stage (chopper, polarity).

+  * @rmtoll TIMxISR     O1CPY          LL_HRTIM_OUT_GetLevel\n

+  *         TIMxISR     O2CPY          LL_HRTIM_OUT_GetLevel

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Output This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUTPUT_TA1

+  *         @arg @ref LL_HRTIM_OUTPUT_TA2

+  *         @arg @ref LL_HRTIM_OUTPUT_TB1

+  *         @arg @ref LL_HRTIM_OUTPUT_TB2

+  *         @arg @ref LL_HRTIM_OUTPUT_TC1

+  *         @arg @ref LL_HRTIM_OUTPUT_TC2

+  *         @arg @ref LL_HRTIM_OUTPUT_TD1

+  *         @arg @ref LL_HRTIM_OUTPUT_TD2

+  *         @arg @ref LL_HRTIM_OUTPUT_TE1

+  *         @arg @ref LL_HRTIM_OUTPUT_TE2

+  * @retval OutputLevel This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_OUT_LEVEL_INACTIVE

+  *         @arg @ref LL_HRTIM_OUT_LEVEL_ACTIVE

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_OUT_GetLevel(HRTIM_TypeDef *HRTIMx, uint32_t Output)

+{

+  register uint32_t iOutput = (uint8_t)(POSITION_VAL(Output) - POSITION_VAL(LL_HRTIM_OUTPUT_TA1));

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sTimerxRegs[0].TIMxISR) +

+                                                                    REG_OFFSET_TAB_OUTxR[iOutput]));

+  return ((READ_BIT(*pReg, (uint32_t)(HRTIM_TIMISR_O1CPY) << REG_SHIFT_TAB_OxSTAT[iOutput]) >> REG_SHIFT_TAB_OxSTAT[iOutput]) >>

+          HRTIM_TIMISR_O1CPY_Pos);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EF_External_Event_management External_Event_management

+  * @{

+  */

+

+/**

+  * @brief  Configure external event conditioning.

+  * @rmtoll EECR1     EE1SRC          LL_HRTIM_EE_Config\n

+  *         EECR1     EE1POL          LL_HRTIM_EE_Config\n

+  *         EECR1     EE1SNS          LL_HRTIM_EE_Config\n

+  *         EECR1     EE1FAST         LL_HRTIM_EE_Config\n

+  *         EECR1     EE2SRC          LL_HRTIM_EE_Config\n

+  *         EECR1     EE2POL          LL_HRTIM_EE_Config\n

+  *         EECR1     EE2SNS          LL_HRTIM_EE_Config\n

+  *         EECR1     EE2FAST         LL_HRTIM_EE_Config\n

+  *         EECR1     EE3SRC          LL_HRTIM_EE_Config\n

+  *         EECR1     EE3POL          LL_HRTIM_EE_Config\n

+  *         EECR1     EE3SNS          LL_HRTIM_EE_Config\n

+  *         EECR1     EE3FAST         LL_HRTIM_EE_Config\n

+  *         EECR1     EE4SRC          LL_HRTIM_EE_Config\n

+  *         EECR1     EE4POL          LL_HRTIM_EE_Config\n

+  *         EECR1     EE4SNS          LL_HRTIM_EE_Config\n

+  *         EECR1     EE4FAST         LL_HRTIM_EE_Config\n

+  *         EECR1     EE5SRC          LL_HRTIM_EE_Config\n

+  *         EECR1     EE5POL          LL_HRTIM_EE_Config\n

+  *         EECR1     EE5SNS          LL_HRTIM_EE_Config\n

+  *         EECR1     EE5FAST         LL_HRTIM_EE_Config\n

+  *         EECR2     EE6SRC          LL_HRTIM_EE_Config\n

+  *         EECR2     EE6POL          LL_HRTIM_EE_Config\n

+  *         EECR2     EE6SNS          LL_HRTIM_EE_Config\n

+  *         EECR2     EE6FAST         LL_HRTIM_EE_Config\n

+  *         EECR2     EE7SRC          LL_HRTIM_EE_Config\n

+  *         EECR2     EE7POL          LL_HRTIM_EE_Config\n

+  *         EECR2     EE7SNS          LL_HRTIM_EE_Config\n

+  *         EECR2     EE7FAST         LL_HRTIM_EE_Config\n

+  *         EECR2     EE8SRC          LL_HRTIM_EE_Config\n

+  *         EECR2     EE8POL          LL_HRTIM_EE_Config\n

+  *         EECR2     EE8SNS          LL_HRTIM_EE_Config\n

+  *         EECR2     EE8FAST         LL_HRTIM_EE_Config\n

+  *         EECR2     EE9SRC          LL_HRTIM_EE_Config\n

+  *         EECR2     EE9POL          LL_HRTIM_EE_Config\n

+  *         EECR2     EE9SNS          LL_HRTIM_EE_Config\n

+  *         EECR2     EE9FAST         LL_HRTIM_EE_Config\n

+  *         EECR2     EE10SRC         LL_HRTIM_EE_Config\n

+  *         EECR2     EE10POL         LL_HRTIM_EE_Config\n

+  *         EECR2     EE10SNS         LL_HRTIM_EE_Config\n

+  *         EECR2     EE10FAST        LL_HRTIM_EE_Config

+  * @note This function must not be called when the timer counter is enabled.

+  * @note Event source (EExSrc1..EExSRC4) mapping depends on configured event channel.

+  * @note Fast mode is available only for LL_HRTIM_EVENT_1..5.

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Event This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_EVENT_1

+  *         @arg @ref LL_HRTIM_EVENT_2

+  *         @arg @ref LL_HRTIM_EVENT_3

+  *         @arg @ref LL_HRTIM_EVENT_4

+  *         @arg @ref LL_HRTIM_EVENT_5

+  *         @arg @ref LL_HRTIM_EVENT_6

+  *         @arg @ref LL_HRTIM_EVENT_7

+  *         @arg @ref LL_HRTIM_EVENT_8

+  *         @arg @ref LL_HRTIM_EVENT_9

+  *         @arg @ref LL_HRTIM_EVENT_10

+  * @param  Configuration This parameter must be a combination of all the following values:

+  *         @arg External event source 1 or External event source 2 or External event source 3 or External event source 4

+  *         @arg @ref LL_HRTIM_EE_POLARITY_HIGH or @ref LL_HRTIM_EE_POLARITY_LOW

+  *         @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL or @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE or @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES

+  *         @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE or @ref LL_HRTIM_EE_FASTMODE_ENABLE

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EE_Config(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Configuration)

+{

+  register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +

+                                                              REG_OFFSET_TAB_EECR[iEvent]));

+  MODIFY_REG(*pReg, (HRTIM_EE_CONFIG_MASK << REG_SHIFT_TAB_EExSRC[iEvent]),

+             (Configuration << REG_SHIFT_TAB_EExSRC[iEvent]));

+}

+

+/**

+  * @brief  Set the external event source.

+  * @rmtoll EECR1     EE1SRC          LL_HRTIM_EE_SetSrc\n

+  *         EECR1     EE2SRC          LL_HRTIM_EE_SetSrc\n

+  *         EECR1     EE3SRC          LL_HRTIM_EE_SetSrc\n

+  *         EECR1     EE4SRC          LL_HRTIM_EE_SetSrc\n

+  *         EECR1     EE5SRC          LL_HRTIM_EE_SetSrc\n

+  *         EECR2     EE6SRC          LL_HRTIM_EE_SetSrc\n

+  *         EECR2     EE7SRC          LL_HRTIM_EE_SetSrc\n

+  *         EECR2     EE8SRC          LL_HRTIM_EE_SetSrc\n

+  *         EECR2     EE9SRC          LL_HRTIM_EE_SetSrc\n

+  *         EECR2     EE10SRC         LL_HRTIM_EE_SetSrc

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Event This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_EVENT_1

+  *         @arg @ref LL_HRTIM_EVENT_2

+  *         @arg @ref LL_HRTIM_EVENT_3

+  *         @arg @ref LL_HRTIM_EVENT_4

+  *         @arg @ref LL_HRTIM_EVENT_5

+  *         @arg @ref LL_HRTIM_EVENT_6

+  *         @arg @ref LL_HRTIM_EVENT_7

+  *         @arg @ref LL_HRTIM_EVENT_8

+  *         @arg @ref LL_HRTIM_EVENT_9

+  *         @arg @ref LL_HRTIM_EVENT_10

+  * @param  Src This parameter can be one of the following values:

+  *         @arg External event source 1

+  *         @arg External event source 2

+  *         @arg External event source 3

+  *         @arg External event source 4

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EE_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Src)

+{

+  register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +

+                                                              REG_OFFSET_TAB_EECR[iEvent]));

+  MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SRC << REG_SHIFT_TAB_EExSRC[iEvent]), (Src << REG_SHIFT_TAB_EExSRC[iEvent]));

+}

+

+/**

+  * @brief  Get actual external event source.

+  * @rmtoll EECR1     EE1SRC          LL_HRTIM_EE_GetSrc\n

+  *         EECR1     EE2SRC          LL_HRTIM_EE_GetSrc\n

+  *         EECR1     EE3SRC          LL_HRTIM_EE_GetSrc\n

+  *         EECR1     EE4SRC          LL_HRTIM_EE_GetSrc\n

+  *         EECR1     EE5SRC          LL_HRTIM_EE_GetSrc\n

+  *         EECR2     EE6SRC          LL_HRTIM_EE_GetSrc\n

+  *         EECR2     EE7SRC          LL_HRTIM_EE_GetSrc\n

+  *         EECR2     EE8SRC          LL_HRTIM_EE_GetSrc\n

+  *         EECR2     EE9SRC          LL_HRTIM_EE_GetSrc\n

+  *         EECR2     EE10SRC         LL_HRTIM_EE_GetSrc

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Event This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_EVENT_1

+  *         @arg @ref LL_HRTIM_EVENT_2

+  *         @arg @ref LL_HRTIM_EVENT_3

+  *         @arg @ref LL_HRTIM_EVENT_4

+  *         @arg @ref LL_HRTIM_EVENT_5

+  *         @arg @ref LL_HRTIM_EVENT_6

+  *         @arg @ref LL_HRTIM_EVENT_7

+  *         @arg @ref LL_HRTIM_EVENT_8

+  *         @arg @ref LL_HRTIM_EVENT_9

+  *         @arg @ref LL_HRTIM_EVENT_10

+  * @retval EventSrc This parameter can be one of the following values:

+  *         @arg External event source 1

+  *         @arg External event source 2

+  *         @arg External event source 3

+  *         @arg External event source 4

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_EE_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Event)

+{

+  register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +

+                                                                    REG_OFFSET_TAB_EECR[iEvent]));

+  return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SRC) << REG_SHIFT_TAB_EExSRC[iEvent]) >>  REG_SHIFT_TAB_EExSRC[iEvent]);

+}

+

+/**

+  * @brief  Set the polarity of an external event.

+  * @rmtoll EECR1     EE1POL          LL_HRTIM_EE_SetPolarity\n

+  *         EECR1     EE2POL          LL_HRTIM_EE_SetPolarity\n

+  *         EECR1     EE3POL          LL_HRTIM_EE_SetPolarity\n

+  *         EECR1     EE4POL          LL_HRTIM_EE_SetPolarity\n

+  *         EECR1     EE5POL          LL_HRTIM_EE_SetPolarity\n

+  *         EECR2     EE6POL          LL_HRTIM_EE_SetPolarity\n

+  *         EECR2     EE7POL          LL_HRTIM_EE_SetPolarity\n

+  *         EECR2     EE8POL          LL_HRTIM_EE_SetPolarity\n

+  *         EECR2     EE9POL          LL_HRTIM_EE_SetPolarity\n

+  *         EECR2     EE10POL         LL_HRTIM_EE_SetPolarity

+  * @note This function must not be called when the timer counter is enabled.

+  * @note Event polarity is only significant when event detection is level-sensitive.

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Event This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_EVENT_1

+  *         @arg @ref LL_HRTIM_EVENT_2

+  *         @arg @ref LL_HRTIM_EVENT_3

+  *         @arg @ref LL_HRTIM_EVENT_4

+  *         @arg @ref LL_HRTIM_EVENT_5

+  *         @arg @ref LL_HRTIM_EVENT_6

+  *         @arg @ref LL_HRTIM_EVENT_7

+  *         @arg @ref LL_HRTIM_EVENT_8

+  *         @arg @ref LL_HRTIM_EVENT_9

+  *         @arg @ref LL_HRTIM_EVENT_10

+  * @param  Polarity This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_EE_POLARITY_HIGH

+  *         @arg @ref LL_HRTIM_EE_POLARITY_LOW

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EE_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Polarity)

+{

+  register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +

+                                                              REG_OFFSET_TAB_EECR[iEvent]));

+  MODIFY_REG(*pReg, (HRTIM_EECR1_EE1POL << REG_SHIFT_TAB_EExSRC[iEvent]), (Polarity << REG_SHIFT_TAB_EExSRC[iEvent]));

+}

+

+/**

+  * @brief  Get actual polarity setting of an external event.

+  * @rmtoll EECR1     EE1POL          LL_HRTIM_EE_GetPolarity\n

+  *         EECR1     EE2POL          LL_HRTIM_EE_GetPolarity\n

+  *         EECR1     EE3POL          LL_HRTIM_EE_GetPolarity\n

+  *         EECR1     EE4POL          LL_HRTIM_EE_GetPolarity\n

+  *         EECR1     EE5POL          LL_HRTIM_EE_GetPolarity\n

+  *         EECR2     EE6POL          LL_HRTIM_EE_GetPolarity\n

+  *         EECR2     EE7POL          LL_HRTIM_EE_GetPolarity\n

+  *         EECR2     EE8POL          LL_HRTIM_EE_GetPolarity\n

+  *         EECR2     EE9POL          LL_HRTIM_EE_GetPolarity\n

+  *         EECR2     EE10POL         LL_HRTIM_EE_GetPolarity

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Event This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_EVENT_1

+  *         @arg @ref LL_HRTIM_EVENT_2

+  *         @arg @ref LL_HRTIM_EVENT_3

+  *         @arg @ref LL_HRTIM_EVENT_4

+  *         @arg @ref LL_HRTIM_EVENT_5

+  *         @arg @ref LL_HRTIM_EVENT_6

+  *         @arg @ref LL_HRTIM_EVENT_7

+  *         @arg @ref LL_HRTIM_EVENT_8

+  *         @arg @ref LL_HRTIM_EVENT_9

+  *         @arg @ref LL_HRTIM_EVENT_10

+  * @retval Polarity This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_EE_POLARITY_HIGH

+  *         @arg @ref LL_HRTIM_EE_POLARITY_LOW

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_EE_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Event)

+{

+  register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +

+                                                                    REG_OFFSET_TAB_EECR[iEvent]));

+  return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1POL) << REG_SHIFT_TAB_EExSRC[iEvent]) >>  REG_SHIFT_TAB_EExSRC[iEvent]);

+}

+

+/**

+  * @brief  Set the sensitivity of an external event.

+  * @rmtoll EECR1     EE1SNS          LL_HRTIM_EE_SetSensitivity\n

+  *         EECR1     EE2SNS          LL_HRTIM_EE_SetSensitivity\n

+  *         EECR1     EE3SNS          LL_HRTIM_EE_SetSensitivity\n

+  *         EECR1     EE4SNS          LL_HRTIM_EE_SetSensitivity\n

+  *         EECR1     EE5SNS          LL_HRTIM_EE_SetSensitivity\n

+  *         EECR2     EE6SNS          LL_HRTIM_EE_SetSensitivity\n

+  *         EECR2     EE7SNS          LL_HRTIM_EE_SetSensitivity\n

+  *         EECR2     EE8SNS          LL_HRTIM_EE_SetSensitivity\n

+  *         EECR2     EE9SNS          LL_HRTIM_EE_SetSensitivity\n

+  *         EECR2     EE10SNS         LL_HRTIM_EE_SetSensitivity

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Event This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_EVENT_1

+  *         @arg @ref LL_HRTIM_EVENT_2

+  *         @arg @ref LL_HRTIM_EVENT_3

+  *         @arg @ref LL_HRTIM_EVENT_4

+  *         @arg @ref LL_HRTIM_EVENT_5

+  *         @arg @ref LL_HRTIM_EVENT_6

+  *         @arg @ref LL_HRTIM_EVENT_7

+  *         @arg @ref LL_HRTIM_EVENT_8

+  *         @arg @ref LL_HRTIM_EVENT_9

+  *         @arg @ref LL_HRTIM_EVENT_10

+  * @param  Sensitivity This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL

+  *         @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE

+  *         @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE

+  *         @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES

+  * @retval None

+  */

+

+__STATIC_INLINE void LL_HRTIM_EE_SetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Sensitivity)

+{

+  register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +

+                                                              REG_OFFSET_TAB_EECR[iEvent]));

+  MODIFY_REG(*pReg, (HRTIM_EECR1_EE1SNS << REG_SHIFT_TAB_EExSRC[iEvent]), (Sensitivity << REG_SHIFT_TAB_EExSRC[iEvent]));

+}

+

+/**

+  * @brief  Get actual sensitivity setting of an external event.

+  * @rmtoll EECR1     EE1SNS          LL_HRTIM_EE_GetSensitivity\n

+  *         EECR1     EE2SNS          LL_HRTIM_EE_GetSensitivity\n

+  *         EECR1     EE3SNS          LL_HRTIM_EE_GetSensitivity\n

+  *         EECR1     EE4SNS          LL_HRTIM_EE_GetSensitivity\n

+  *         EECR1     EE5SNS          LL_HRTIM_EE_GetSensitivity\n

+  *         EECR2     EE6SNS          LL_HRTIM_EE_GetSensitivity\n

+  *         EECR2     EE7SNS          LL_HRTIM_EE_GetSensitivity\n

+  *         EECR2     EE8SNS          LL_HRTIM_EE_GetSensitivity\n

+  *         EECR2     EE9SNS          LL_HRTIM_EE_GetSensitivity\n

+  *         EECR2     EE10SNS         LL_HRTIM_EE_GetSensitivity

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Event This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_EVENT_1

+  *         @arg @ref LL_HRTIM_EVENT_2

+  *         @arg @ref LL_HRTIM_EVENT_3

+  *         @arg @ref LL_HRTIM_EVENT_4

+  *         @arg @ref LL_HRTIM_EVENT_5

+  *         @arg @ref LL_HRTIM_EVENT_6

+  *         @arg @ref LL_HRTIM_EVENT_7

+  *         @arg @ref LL_HRTIM_EVENT_8

+  *         @arg @ref LL_HRTIM_EVENT_9

+  *         @arg @ref LL_HRTIM_EVENT_10

+  * @retval Polarity This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_EE_SENSITIVITY_LEVEL

+  *         @arg @ref LL_HRTIM_EE_SENSITIVITY_RISINGEDGE

+  *         @arg @ref LL_HRTIM_EE_SENSITIVITY_FALLINGEDGE

+  *         @arg @ref LL_HRTIM_EE_SENSITIVITY_BOTHEDGES

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_EE_GetSensitivity(HRTIM_TypeDef *HRTIMx, uint32_t Event)

+{

+  register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +

+                                                                    REG_OFFSET_TAB_EECR[iEvent]));

+  return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1SNS) << REG_SHIFT_TAB_EExSRC[iEvent]) >>  REG_SHIFT_TAB_EExSRC[iEvent]);

+}

+

+/**

+  * @brief  Set the fast mode of an external event.

+  * @rmtoll EECR1     EE1FAST         LL_HRTIM_EE_SetFastMode\n

+  *         EECR1     EE2FAST         LL_HRTIM_EE_SetFastMode\n

+  *         EECR1     EE3FAST         LL_HRTIM_EE_SetFastMode\n

+  *         EECR1     EE4FAST         LL_HRTIM_EE_SetFastMode\n

+  *         EECR1     EE5FAST         LL_HRTIM_EE_SetFastMode\n

+  *         EECR2     EE6FAST         LL_HRTIM_EE_SetFastMode\n

+  *         EECR2     EE7FAST         LL_HRTIM_EE_SetFastMode\n

+  *         EECR2     EE8FAST         LL_HRTIM_EE_SetFastMode\n

+  *         EECR2     EE9FAST         LL_HRTIM_EE_SetFastMode\n

+  *         EECR2     EE10FAST        LL_HRTIM_EE_SetFastMode

+  * @note This function must not be called when the timer counter is enabled.

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Event This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_EVENT_1

+  *         @arg @ref LL_HRTIM_EVENT_2

+  *         @arg @ref LL_HRTIM_EVENT_3

+  *         @arg @ref LL_HRTIM_EVENT_4

+  *         @arg @ref LL_HRTIM_EVENT_5

+  * @param  FastMode This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE

+  *         @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EE_SetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t FastMode)

+{

+  register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +

+                                                              REG_OFFSET_TAB_EECR[iEvent]));

+  MODIFY_REG(*pReg, (HRTIM_EECR1_EE1FAST << REG_SHIFT_TAB_EExSRC[iEvent]), (FastMode << REG_SHIFT_TAB_EExSRC[iEvent]));

+}

+

+/**

+  * @brief  Get actual fast mode setting of an external event.

+  * @rmtoll EECR1     EE1FAST         LL_HRTIM_EE_GetFastMode\n

+  *         EECR1     EE2FAST         LL_HRTIM_EE_GetFastMode\n

+  *         EECR1     EE3FAST         LL_HRTIM_EE_GetFastMode\n

+  *         EECR1     EE4FAST         LL_HRTIM_EE_GetFastMode\n

+  *         EECR1     EE5FAST         LL_HRTIM_EE_GetFastMode\n

+  *         EECR2     EE6FAST         LL_HRTIM_EE_GetFastMode\n

+  *         EECR2     EE7FAST         LL_HRTIM_EE_GetFastMode\n

+  *         EECR2     EE8FAST         LL_HRTIM_EE_GetFastMode\n

+  *         EECR2     EE9FAST         LL_HRTIM_EE_GetFastMode\n

+  *         EECR2     EE10FAST        LL_HRTIM_EE_GetFastMode

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Event This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_EVENT_1

+  *         @arg @ref LL_HRTIM_EVENT_2

+  *         @arg @ref LL_HRTIM_EVENT_3

+  *         @arg @ref LL_HRTIM_EVENT_4

+  *         @arg @ref LL_HRTIM_EVENT_5

+  * @retval FastMode This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_EE_FASTMODE_DISABLE

+  *         @arg @ref LL_HRTIM_EE_FASTMODE_ENABLE

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_EE_GetFastMode(HRTIM_TypeDef *HRTIMx, uint32_t Event)

+{

+  register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.EECR1) +

+                                                                    REG_OFFSET_TAB_EECR[iEvent]));

+  return (READ_BIT(*pReg, (uint32_t)(HRTIM_EECR1_EE1FAST) << REG_SHIFT_TAB_EExSRC[iEvent]) >>  REG_SHIFT_TAB_EExSRC[iEvent]);

+}

+

+/**

+  * @brief  Set the digital noise filter of a external event.

+  * @rmtoll EECR3     EE6F         LL_HRTIM_EE_SetFilter\n

+  *         EECR3     EE7F         LL_HRTIM_EE_SetFilter\n

+  *         EECR3     EE8F         LL_HRTIM_EE_SetFilter\n

+  *         EECR3     EE9F         LL_HRTIM_EE_SetFilter\n

+  *         EECR3     EE10F        LL_HRTIM_EE_SetFilter

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Event This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_EVENT_6

+  *         @arg @ref LL_HRTIM_EVENT_7

+  *         @arg @ref LL_HRTIM_EVENT_8

+  *         @arg @ref LL_HRTIM_EVENT_9

+  *         @arg @ref LL_HRTIM_EVENT_10

+  * @param  Filter This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_EE_FILTER_NONE

+  *         @arg @ref LL_HRTIM_EE_FILTER_1

+  *         @arg @ref LL_HRTIM_EE_FILTER_2

+  *         @arg @ref LL_HRTIM_EE_FILTER_3

+  *         @arg @ref LL_HRTIM_EE_FILTER_4

+  *         @arg @ref LL_HRTIM_EE_FILTER_5

+  *         @arg @ref LL_HRTIM_EE_FILTER_6

+  *         @arg @ref LL_HRTIM_EE_FILTER_7

+  *         @arg @ref LL_HRTIM_EE_FILTER_8

+  *         @arg @ref LL_HRTIM_EE_FILTER_9

+  *         @arg @ref LL_HRTIM_EE_FILTER_10

+  *         @arg @ref LL_HRTIM_EE_FILTER_11

+  *         @arg @ref LL_HRTIM_EE_FILTER_12

+  *         @arg @ref LL_HRTIM_EE_FILTER_13

+  *         @arg @ref LL_HRTIM_EE_FILTER_14

+  *         @arg @ref LL_HRTIM_EE_FILTER_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EE_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event, uint32_t Filter)

+{

+  register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_1));

+  MODIFY_REG(HRTIMx->sCommonRegs.EECR3, (HRTIM_EECR3_EE6F << REG_SHIFT_TAB_EExSRC[iEvent]),

+             (Filter << REG_SHIFT_TAB_EExSRC[iEvent]));

+}

+

+/**

+  * @brief  Get actual digital noise filter setting of a external event.

+  * @rmtoll EECR3     EE6F         LL_HRTIM_EE_GetFilter\n

+  *         EECR3     EE7F         LL_HRTIM_EE_GetFilter\n

+  *         EECR3     EE8F         LL_HRTIM_EE_GetFilter\n

+  *         EECR3     EE9F         LL_HRTIM_EE_GetFilter\n

+  *         EECR3     EE10F        LL_HRTIM_EE_GetFilter

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Event This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_EVENT_6

+  *         @arg @ref LL_HRTIM_EVENT_7

+  *         @arg @ref LL_HRTIM_EVENT_8

+  *         @arg @ref LL_HRTIM_EVENT_9

+  *         @arg @ref LL_HRTIM_EVENT_10

+  * @retval Filter This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_EE_FILTER_NONE

+  *         @arg @ref LL_HRTIM_EE_FILTER_1

+  *         @arg @ref LL_HRTIM_EE_FILTER_2

+  *         @arg @ref LL_HRTIM_EE_FILTER_3

+  *         @arg @ref LL_HRTIM_EE_FILTER_4

+  *         @arg @ref LL_HRTIM_EE_FILTER_5

+  *         @arg @ref LL_HRTIM_EE_FILTER_6

+  *         @arg @ref LL_HRTIM_EE_FILTER_7

+  *         @arg @ref LL_HRTIM_EE_FILTER_8

+  *         @arg @ref LL_HRTIM_EE_FILTER_9

+  *         @arg @ref LL_HRTIM_EE_FILTER_10

+  *         @arg @ref LL_HRTIM_EE_FILTER_11

+  *         @arg @ref LL_HRTIM_EE_FILTER_12

+  *         @arg @ref LL_HRTIM_EE_FILTER_13

+  *         @arg @ref LL_HRTIM_EE_FILTER_14

+  *         @arg @ref LL_HRTIM_EE_FILTER_15

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_EE_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Event)

+{

+  register uint32_t iEvent = (uint8_t)(POSITION_VAL(Event) - POSITION_VAL(LL_HRTIM_EVENT_6));

+  return (READ_BIT(HRTIMx->sCommonRegs.EECR3,

+                   (uint32_t)(HRTIM_EECR3_EE6F) << REG_SHIFT_TAB_EExSRC[iEvent]) >>  REG_SHIFT_TAB_EExSRC[iEvent]);

+}

+

+/**

+  * @brief  Set the external event prescaler.

+  * @rmtoll EECR3     EEVSD        LL_HRTIM_EE_SetPrescaler

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Prescaler This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV1

+  *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV2

+  *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV4

+  *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV8

+  * @retval None

+  */

+

+__STATIC_INLINE void LL_HRTIM_EE_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)

+{

+  MODIFY_REG(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD, Prescaler);

+}

+

+/**

+  * @brief  Get actual external event prescaler setting.

+  * @rmtoll EECR3     EEVSD        LL_HRTIM_EE_GetPrescaler

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval Prescaler This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV1

+  *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV2

+  *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV4

+  *         @arg @ref LL_HRTIM_EE_PRESCALER_DIV8

+  */

+

+__STATIC_INLINE uint32_t LL_HRTIM_EE_GetPrescaler(HRTIM_TypeDef *HRTIMx)

+{

+  return (READ_BIT(HRTIMx->sCommonRegs.EECR3, HRTIM_EECR3_EEVSD));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EF_Fault_management Fault_management

+  * @{

+  */

+/**

+  * @brief  Configure fault signal conditioning Polarity and Source.

+  * @rmtoll FLTINR1     FLT1P        LL_HRTIM_FLT_Config\n

+  *         FLTINR1     FLT1SRC      LL_HRTIM_FLT_Config\n

+  *         FLTINR1     FLT2P        LL_HRTIM_FLT_Config\n

+  *         FLTINR1     FLT2SRC      LL_HRTIM_FLT_Config\n

+  *         FLTINR1     FLT3P        LL_HRTIM_FLT_Config\n

+  *         FLTINR1     FLT3SRC      LL_HRTIM_FLT_Config\n

+  *         FLTINR1     FLT4P        LL_HRTIM_FLT_Config\n

+  *         FLTINR1     FLT4SRC      LL_HRTIM_FLT_Config\n

+  *         FLTINR2     FLT5P        LL_HRTIM_FLT_Config\n

+  *         FLTINR2     FLT5SRC      LL_HRTIM_FLT_Config

+  * @note This function must not be called when the fault channel is enabled.

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Fault This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_FAULT_1

+  *         @arg @ref LL_HRTIM_FAULT_2

+  *         @arg @ref LL_HRTIM_FAULT_3

+  *         @arg @ref LL_HRTIM_FAULT_4

+  *         @arg @ref LL_HRTIM_FAULT_5

+  * @param  Configuration This parameter must be a combination of all the following values:

+  *         @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT..LL_HRTIM_FLT_SRC_INTERNAL

+  *         @arg @ref LL_HRTIM_FLT_POLARITY_LOW..LL_HRTIM_FLT_POLARITY_HIGH

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_FLT_Config(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Configuration)

+{

+  register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +

+                                                              REG_OFFSET_TAB_FLTINR[iFault]));

+  MODIFY_REG(*pReg, (HRTIM_FLT_CONFIG_MASK << REG_SHIFT_TAB_FLTxE[iFault]),

+             (Configuration << REG_SHIFT_TAB_FLTxE[iFault]));

+}

+

+/**

+  * @brief  Set the source of a fault signal.

+  * @rmtoll FLTINR1     FLT1SRC      LL_HRTIM_FLT_SetSrc\n

+  *         FLTINR1     FLT2SRC      LL_HRTIM_FLT_SetSrc\n

+  *         FLTINR1     FLT3SRC      LL_HRTIM_FLT_SetSrc\n

+  *         FLTINR1     FLT4SRC      LL_HRTIM_FLT_SetSrc\n

+  *         FLTINR2     FLT5SRC      LL_HRTIM_FLT_SetSrc

+  * @note This function must not be called when the fault channel is enabled.

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Fault This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_FAULT_1

+  *         @arg @ref LL_HRTIM_FAULT_2

+  *         @arg @ref LL_HRTIM_FAULT_3

+  *         @arg @ref LL_HRTIM_FAULT_4

+  *         @arg @ref LL_HRTIM_FAULT_5

+  * @param  Src This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT

+  *         @arg @ref LL_HRTIM_FLT_SRC_INTERNAL

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_FLT_SetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Src)

+{

+  register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +

+                                                              REG_OFFSET_TAB_FLTINR[iFault]));

+  MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault]), (Src << REG_SHIFT_TAB_FLTxE[iFault]));

+}

+

+/**

+  * @brief  Get actual source of a fault signal.

+  * @rmtoll FLTINR1     FLT1SRC      LL_HRTIM_FLT_GetSrc\n

+  *         FLTINR1     FLT2SRC      LL_HRTIM_FLT_GetSrc\n

+  *         FLTINR1     FLT3SRC      LL_HRTIM_FLT_GetSrc\n

+  *         FLTINR1     FLT4SRC      LL_HRTIM_FLT_GetSrc\n

+  *         FLTINR2     FLT5SRC      LL_HRTIM_FLT_GetSrc

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Fault This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_FAULT_1

+  *         @arg @ref LL_HRTIM_FAULT_2

+  *         @arg @ref LL_HRTIM_FAULT_3

+  *         @arg @ref LL_HRTIM_FAULT_4

+  *         @arg @ref LL_HRTIM_FAULT_5

+  * @retval Source This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_FLT_SRC_DIGITALINPUT

+  *         @arg @ref LL_HRTIM_FLT_SRC_INTERNAL

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetSrc(HRTIM_TypeDef *HRTIMx, uint32_t Fault)

+{

+  register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +

+                                                              REG_OFFSET_TAB_FLTINR[iFault]));

+  return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1SRC << REG_SHIFT_TAB_FLTxE[iFault])) >>  REG_SHIFT_TAB_FLTxE[iFault]);

+}

+

+/**

+  * @brief  Set the polarity of a fault signal.

+  * @rmtoll FLTINR1     FLT1P        LL_HRTIM_FLT_SetPolarity\n

+  *         FLTINR1     FLT2P        LL_HRTIM_FLT_SetPolarity\n

+  *         FLTINR1     FLT3P        LL_HRTIM_FLT_SetPolarity\n

+  *         FLTINR1     FLT4P        LL_HRTIM_FLT_SetPolarity\n

+  *         FLTINR2     FLT5P        LL_HRTIM_FLT_SetPolarity

+  * @note This function must not be called when the fault channel is enabled.

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Fault This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_FAULT_1

+  *         @arg @ref LL_HRTIM_FAULT_2

+  *         @arg @ref LL_HRTIM_FAULT_3

+  *         @arg @ref LL_HRTIM_FAULT_4

+  *         @arg @ref LL_HRTIM_FAULT_5

+  * @param  Polarity This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_FLT_POLARITY_LOW

+  *         @arg @ref LL_HRTIM_FLT_POLARITY_HIGH

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_FLT_SetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Polarity)

+{

+  register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +

+                                                              REG_OFFSET_TAB_FLTINR[iFault]));

+  MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault]), (Polarity << REG_SHIFT_TAB_FLTxE[iFault]));

+}

+

+/**

+  * @brief  Get actual polarity of a fault signal.

+  * @rmtoll FLTINR1     FLT1P        LL_HRTIM_FLT_GetPolarity\n

+  *         FLTINR1     FLT2P        LL_HRTIM_FLT_GetPolarity\n

+  *         FLTINR1     FLT3P        LL_HRTIM_FLT_GetPolarity\n

+  *         FLTINR1     FLT4P        LL_HRTIM_FLT_GetPolarity\n

+  *         FLTINR2     FLT5P        LL_HRTIM_FLT_GetPolarity

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Fault This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_FAULT_1

+  *         @arg @ref LL_HRTIM_FAULT_2

+  *         @arg @ref LL_HRTIM_FAULT_3

+  *         @arg @ref LL_HRTIM_FAULT_4

+  *         @arg @ref LL_HRTIM_FAULT_5

+  * @retval Polarity This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_FLT_POLARITY_LOW

+  *         @arg @ref LL_HRTIM_FLT_POLARITY_HIGH

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPolarity(HRTIM_TypeDef *HRTIMx, uint32_t Fault)

+{

+  register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +

+                                                              REG_OFFSET_TAB_FLTINR[iFault]));

+  return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1P << REG_SHIFT_TAB_FLTxE[iFault])) >>  REG_SHIFT_TAB_FLTxE[iFault]);

+}

+

+/**

+  * @brief  Set the digital noise filter of a fault signal.

+  * @rmtoll FLTINR1     FLT1F      LL_HRTIM_FLT_SetFilter\n

+  *         FLTINR1     FLT2F      LL_HRTIM_FLT_SetFilter\n

+  *         FLTINR1     FLT3F      LL_HRTIM_FLT_SetFilter\n

+  *         FLTINR1     FLT4F      LL_HRTIM_FLT_SetFilter\n

+  *         FLTINR2     FLT5F      LL_HRTIM_FLT_SetFilter

+  * @note This function must not be called when the fault channel is enabled.

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Fault This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_FAULT_1

+  *         @arg @ref LL_HRTIM_FAULT_2

+  *         @arg @ref LL_HRTIM_FAULT_3

+  *         @arg @ref LL_HRTIM_FAULT_4

+  *         @arg @ref LL_HRTIM_FAULT_5

+  * @param  Filter This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_FLT_FILTER_NONE

+  *         @arg @ref LL_HRTIM_FLT_FILTER_1

+  *         @arg @ref LL_HRTIM_FLT_FILTER_2

+  *         @arg @ref LL_HRTIM_FLT_FILTER_3

+  *         @arg @ref LL_HRTIM_FLT_FILTER_4

+  *         @arg @ref LL_HRTIM_FLT_FILTER_5

+  *         @arg @ref LL_HRTIM_FLT_FILTER_6

+  *         @arg @ref LL_HRTIM_FLT_FILTER_7

+  *         @arg @ref LL_HRTIM_FLT_FILTER_8

+  *         @arg @ref LL_HRTIM_FLT_FILTER_9

+  *         @arg @ref LL_HRTIM_FLT_FILTER_10

+  *         @arg @ref LL_HRTIM_FLT_FILTER_11

+  *         @arg @ref LL_HRTIM_FLT_FILTER_12

+  *         @arg @ref LL_HRTIM_FLT_FILTER_13

+  *         @arg @ref LL_HRTIM_FLT_FILTER_14

+  *         @arg @ref LL_HRTIM_FLT_FILTER_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_FLT_SetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault, uint32_t Filter)

+{

+  register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +

+                                                              REG_OFFSET_TAB_FLTINR[iFault]));

+  MODIFY_REG(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault]), (Filter << REG_SHIFT_TAB_FLTxE[iFault]));

+}

+

+/**

+  * @brief  Get actual digital noise filter setting of a fault signal.

+  * @rmtoll FLTINR1     FLT1F      LL_HRTIM_FLT_GetFilter\n

+  *         FLTINR1     FLT2F      LL_HRTIM_FLT_GetFilter\n

+  *         FLTINR1     FLT3F      LL_HRTIM_FLT_GetFilter\n

+  *         FLTINR1     FLT4F      LL_HRTIM_FLT_GetFilter\n

+  *         FLTINR2     FLT5F      LL_HRTIM_FLT_GetFilter

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Fault This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_FAULT_1

+  *         @arg @ref LL_HRTIM_FAULT_2

+  *         @arg @ref LL_HRTIM_FAULT_3

+  *         @arg @ref LL_HRTIM_FAULT_4

+  *         @arg @ref LL_HRTIM_FAULT_5

+  * @retval Filter This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_FLT_FILTER_NONE

+  *         @arg @ref LL_HRTIM_FLT_FILTER_1

+  *         @arg @ref LL_HRTIM_FLT_FILTER_2

+  *         @arg @ref LL_HRTIM_FLT_FILTER_3

+  *         @arg @ref LL_HRTIM_FLT_FILTER_4

+  *         @arg @ref LL_HRTIM_FLT_FILTER_5

+  *         @arg @ref LL_HRTIM_FLT_FILTER_6

+  *         @arg @ref LL_HRTIM_FLT_FILTER_7

+  *         @arg @ref LL_HRTIM_FLT_FILTER_8

+  *         @arg @ref LL_HRTIM_FLT_FILTER_9

+  *         @arg @ref LL_HRTIM_FLT_FILTER_10

+  *         @arg @ref LL_HRTIM_FLT_FILTER_11

+  *         @arg @ref LL_HRTIM_FLT_FILTER_12

+  *         @arg @ref LL_HRTIM_FLT_FILTER_13

+  *         @arg @ref LL_HRTIM_FLT_FILTER_14

+  *         @arg @ref LL_HRTIM_FLT_FILTER_15

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetFilter(HRTIM_TypeDef *HRTIMx, uint32_t Fault)

+{

+  register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +

+                                                              REG_OFFSET_TAB_FLTINR[iFault]));

+  return (READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1F << REG_SHIFT_TAB_FLTxE[iFault])) >>  REG_SHIFT_TAB_FLTxE[iFault]);

+

+}

+

+/**

+  * @brief  Set the fault circuitry prescaler.

+  * @rmtoll FLTINR2     FLTSD      LL_HRTIM_FLT_SetPrescaler

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Prescaler This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1

+  *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2

+  *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4

+  *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_FLT_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)

+{

+  MODIFY_REG(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD, Prescaler);

+}

+

+/**

+  * @brief  Get actual fault circuitry prescaler setting.

+  * @rmtoll FLTINR2     FLTSD      LL_HRTIM_FLT_GetPrescaler

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval Prescaler This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV1

+  *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV2

+  *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV4

+  *         @arg @ref LL_HRTIM_FLT_PRESCALER_DIV8

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_FLT_GetPrescaler(HRTIM_TypeDef *HRTIMx)

+{

+  return (READ_BIT(HRTIMx->sCommonRegs.FLTINR2, HRTIM_FLTINR2_FLTSD));

+}

+

+/**

+  * @brief  Lock the fault signal conditioning settings.

+  * @rmtoll FLTINR1     FLT1LCK      LL_HRTIM_FLT_Lock\n

+  *         FLTINR1     FLT2LCK      LL_HRTIM_FLT_Lock\n

+  *         FLTINR1     FLT3LCK      LL_HRTIM_FLT_Lock\n

+  *         FLTINR1     FLT4LCK      LL_HRTIM_FLT_Lock\n

+  *         FLTINR2     FLT5LCK      LL_HRTIM_FLT_Lock

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Fault This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_FAULT_1

+  *         @arg @ref LL_HRTIM_FAULT_2

+  *         @arg @ref LL_HRTIM_FAULT_3

+  *         @arg @ref LL_HRTIM_FAULT_4

+  *         @arg @ref LL_HRTIM_FAULT_5

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_FLT_Lock(HRTIM_TypeDef *HRTIMx, uint32_t Fault)

+{

+  register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +

+                                                              REG_OFFSET_TAB_FLTINR[iFault]));

+  SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1LCK << REG_SHIFT_TAB_FLTxE[iFault]));

+}

+

+/**

+  * @brief  Enable the fault circuitry for the designated fault input.

+  * @rmtoll FLTINR1     FLT1E      LL_HRTIM_FLT_Enable\n

+  *         FLTINR1     FLT2E      LL_HRTIM_FLT_Enable\n

+  *         FLTINR1     FLT3E      LL_HRTIM_FLT_Enable\n

+  *         FLTINR1     FLT4E      LL_HRTIM_FLT_Enable\n

+  *         FLTINR2     FLT5E      LL_HRTIM_FLT_Enable

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Fault This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_FAULT_1

+  *         @arg @ref LL_HRTIM_FAULT_2

+  *         @arg @ref LL_HRTIM_FAULT_3

+  *         @arg @ref LL_HRTIM_FAULT_4

+  *         @arg @ref LL_HRTIM_FAULT_5

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_FLT_Enable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)

+{

+  register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +

+                                                              REG_OFFSET_TAB_FLTINR[iFault]));

+  SET_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault]));

+}

+

+/**

+  * @brief  Disable the fault circuitry for for the designated fault input.

+  * @rmtoll FLTINR1     FLT1E      LL_HRTIM_FLT_Disable\n

+  *         FLTINR1     FLT2E      LL_HRTIM_FLT_Disable\n

+  *         FLTINR1     FLT3E      LL_HRTIM_FLT_Disable\n

+  *         FLTINR1     FLT4E      LL_HRTIM_FLT_Disable\n

+  *         FLTINR2     FLT5E      LL_HRTIM_FLT_Disable

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Fault This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_FAULT_1

+  *         @arg @ref LL_HRTIM_FAULT_2

+  *         @arg @ref LL_HRTIM_FAULT_3

+  *         @arg @ref LL_HRTIM_FAULT_4

+  *         @arg @ref LL_HRTIM_FAULT_5

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_FLT_Disable(HRTIM_TypeDef *HRTIMx, uint32_t Fault)

+{

+  register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +

+                                                              REG_OFFSET_TAB_FLTINR[iFault]));

+  CLEAR_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault]));

+}

+

+/**

+  * @brief  Indicate whether the fault circuitry is enabled for a given fault input.

+  * @rmtoll FLTINR1     FLT1E      LL_HRTIM_FLT_IsEnabled\n

+  *         FLTINR1     FLT2E      LL_HRTIM_FLT_IsEnabled\n

+  *         FLTINR1     FLT3E      LL_HRTIM_FLT_IsEnabled\n

+  *         FLTINR1     FLT4E      LL_HRTIM_FLT_IsEnabled\n

+  *         FLTINR2     FLT5E      LL_HRTIM_FLT_IsEnabled

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Fault This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_FAULT_1

+  *         @arg @ref LL_HRTIM_FAULT_2

+  *         @arg @ref LL_HRTIM_FAULT_3

+  *         @arg @ref LL_HRTIM_FAULT_4

+  *         @arg @ref LL_HRTIM_FAULT_5

+  * @retval State of FLTxEN bit in HRTIM_FLTINRx register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_FLT_IsEnabled(HRTIM_TypeDef *HRTIMx, uint32_t Fault)

+{

+  register uint32_t iFault = (uint8_t)POSITION_VAL(Fault);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sCommonRegs.FLTINR1) +

+                                                                    REG_OFFSET_TAB_FLTINR[iFault]));

+  return (((READ_BIT(*pReg, (HRTIM_FLTINR1_FLT1E << REG_SHIFT_TAB_FLTxE[iFault])) >> REG_SHIFT_TAB_FLTxE[iFault]) ==

+           (HRTIM_IER_FLT1)) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EF_Burst_Mode_management Burst_Mode_management

+  * @{

+  */

+

+/**

+  * @brief  Configure the burst mode controller.

+  * @rmtoll BMCR     BMOM        LL_HRTIM_BM_Config\n

+  *         BMCR     BMCLK       LL_HRTIM_BM_Config\n

+  *         BMCR     BMPRSC      LL_HRTIM_BM_Config

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Configuration This parameter must be a combination of all the following values:

+  *         @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT or @ref LL_HRTIM_BM_MODE_CONTINOUS

+  *         @arg @ref LL_HRTIM_BM_CLKSRC_MASTER or ... or @ref LL_HRTIM_BM_CLKSRC_FHRTIM

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV1 or ... @ref LL_HRTIM_BM_PRESCALER_DIV32768

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_BM_Config(HRTIM_TypeDef *HRTIMx, uint32_t Configuration)

+{

+  MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BM_CONFIG_MASK, Configuration);

+}

+

+/**

+  * @brief  Set the burst mode controller operating mode.

+  * @rmtoll BMCR     BMOM        LL_HRTIM_BM_SetMode

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Mode This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT

+  *         @arg @ref LL_HRTIM_BM_MODE_CONTINOUS

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_BM_SetMode(HRTIM_TypeDef *HRTIMx, uint32_t Mode)

+{

+  MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM, Mode);

+}

+

+/**

+  * @brief  Get actual burst mode controller operating mode.

+  * @rmtoll BMCR     BMOM        LL_HRTIM_BM_GetMode

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval Mode This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_BM_MODE_SINGLESHOT

+  *         @arg @ref LL_HRTIM_BM_MODE_CONTINOUS

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetMode(HRTIM_TypeDef *HRTIMx)

+{

+  return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMOM);

+}

+

+/**

+  * @brief  Set the burst mode controller clock source.

+  * @rmtoll BMCR     BMCLK       LL_HRTIM_BM_SetClockSrc

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  ClockSrc This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_BM_CLKSRC_MASTER

+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A

+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B

+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C

+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D

+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E

+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC

+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC

+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO

+  *         @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_BM_SetClockSrc(HRTIM_TypeDef *HRTIMx, uint32_t ClockSrc)

+{

+  MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK, ClockSrc);

+}

+

+/**

+  * @brief  Get actual burst mode controller clock source.

+  * @rmtoll BMCR     BMCLK       LL_HRTIM_BM_GetClockSrc

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval ClockSrc This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_BM_CLKSRC_MASTER

+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A

+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B

+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C

+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D

+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E

+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC

+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC

+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO

+  *         @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM

+  * @retval ClockSrc This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_BM_CLKSRC_MASTER

+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_A

+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_B

+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_C

+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_D

+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIMER_E

+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM16_OC

+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM17_OC

+  *         @arg @ref LL_HRTIM_BM_CLKSRC_TIM7_TRGO

+  *         @arg @ref LL_HRTIM_BM_CLKSRC_FHRTIM

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetClockSrc(HRTIM_TypeDef *HRTIMx)

+{

+  return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMCLK);

+}

+

+/**

+  * @brief  Set the burst mode controller prescaler.

+  * @rmtoll BMCR     BMPRSC      LL_HRTIM_BM_SetPrescaler

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Prescaler This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV1

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV2

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV4

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV8

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV16

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV32

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV64

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV128

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV256

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV512

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_BM_SetPrescaler(HRTIM_TypeDef *HRTIMx, uint32_t Prescaler)

+{

+  MODIFY_REG(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC, Prescaler);

+}

+

+/**

+  * @brief  Get actual burst mode controller prescaler setting.

+  * @rmtoll BMCR     BMPRSC      LL_HRTIM_BM_GetPrescaler

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval Prescaler This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV1

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV2

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV4

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV8

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV16

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV32

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV64

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV128

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV256

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV512

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV1024

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV2048

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV4096

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV8192

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV16384

+  *         @arg @ref LL_HRTIM_BM_PRESCALER_DIV32768

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetPrescaler(HRTIM_TypeDef *HRTIMx)

+{

+  return (uint32_t)READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPRSC);

+}

+

+/**

+  * @brief  Enable burst mode compare and period registers preload.

+  * @rmtoll BMCR     BMPREN      LL_HRTIM_BM_EnablePreload

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_BM_EnablePreload(HRTIM_TypeDef *HRTIMx)

+{

+  SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);

+}

+

+/**

+  * @brief  Disable burst mode compare and period registers preload.

+  * @rmtoll BMCR     BMPREN      LL_HRTIM_BM_DisablePreload

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_BM_DisablePreload(HRTIM_TypeDef *HRTIMx)

+{

+  CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);

+}

+

+/**

+  * @brief  Indicate whether burst mode compare and period registers are preloaded.

+  * @rmtoll BMCR     BMPREN      LL_HRTIM_BM_IsEnabledPreload

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval State of BMPREN bit in HRTIM_BMCR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabledPreload(HRTIM_TypeDef *HRTIMx)

+{

+  uint32_t temp; /* MISRAC-2012 compliancy */

+  temp = READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMPREN);

+

+  return ((temp == (HRTIM_BMCR_BMPREN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set the burst mode controller trigger

+  * @rmtoll BMTRGR     SW           LL_HRTIM_BM_SetTrig\n

+  *         BMTRGR     MSTRST       LL_HRTIM_BM_SetTrig\n

+  *         BMTRGR     MSTREP       LL_HRTIM_BM_SetTrig\n

+  *         BMTRGR     MSTCMP1      LL_HRTIM_BM_SetTrig\n

+  *         BMTRGR     MSTCMP2      LL_HRTIM_BM_SetTrig\n

+  *         BMTRGR     MSTCMP3      LL_HRTIM_BM_SetTrig\n

+  *         BMTRGR     MSTCMP4      LL_HRTIM_BM_SetTrig\n

+  *         BMTRGR     TARST        LL_HRTIM_BM_SetTrig\n

+  *         BMTRGR     TAREP        LL_HRTIM_BM_SetTrig\n

+  *         BMTRGR     TACMP1       LL_HRTIM_BM_SetTrig\n

+  *         BMTRGR     TACMP2       LL_HRTIM_BM_SetTrig\n

+  *         BMTRGR     TBRST        LL_HRTIM_BM_SetTrig\n

+  *         BMTRGR     TBREP        LL_HRTIM_BM_SetTrig\n

+  *         BMTRGR     TBCMP1       LL_HRTIM_BM_SetTrig\n

+  *         BMTRGR     TBCMP2       LL_HRTIM_BM_SetTrig\n

+  *         BMTRGR     TCRST        LL_HRTIM_BM_SetTrig\n

+  *         BMTRGR     TCREP        LL_HRTIM_BM_SetTrig\n

+  *         BMTRGR     TCCMP1       LL_HRTIM_BM_SetTrig\n

+  *         BMTRGR     TCCMP2       LL_HRTIM_BM_SetTrig\n

+  *         BMTRGR     TDRST        LL_HRTIM_BM_SetTrig\n

+  *         BMTRGR     TDREP        LL_HRTIM_BM_SetTrig\n

+  *         BMTRGR     TDCMP1       LL_HRTIM_BM_SetTrig\n

+  *         BMTRGR     TDCMP2       LL_HRTIM_BM_SetTrig\n

+  *         BMTRGR     TERST        LL_HRTIM_BM_SetTrig\n

+  *         BMTRGR     TEREP        LL_HRTIM_BM_SetTrig\n

+  *         BMTRGR     TECMP1       LL_HRTIM_BM_SetTrig\n

+  *         BMTRGR     TECMP2       LL_HRTIM_BM_SetTrig\n

+  *         BMTRGR     TAEEV7       LL_HRTIM_BM_SetTrig\n

+  *         BMTRGR     TAEEV8       LL_HRTIM_BM_SetTrig\n

+  *         BMTRGR     EEV7         LL_HRTIM_BM_SetTrig\n

+  *         BMTRGR     EEV8         LL_HRTIM_BM_SetTrig\n

+  *         BMTRGR     OCHIPEV      LL_HRTIM_BM_SetTrig

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Trig This parameter can be a combination of the following values:

+  *         @arg @ref LL_HRTIM_BM_TRIG_NONE

+  *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET

+  *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION

+  *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1

+  *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2

+  *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3

+  *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP2

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP1

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIME_RESET

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8

+  *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_7

+  *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_8

+  *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP

+    * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_BM_SetTrig(HRTIM_TypeDef *HRTIMx, uint32_t Trig)

+{

+  WRITE_REG(HRTIMx->sCommonRegs.BMTRGR, Trig);

+}

+

+/**

+  * @brief  Get actual burst mode controller trigger.

+  * @rmtoll BMTRGR     SW           LL_HRTIM_BM_GetTrig\n

+  *         BMTRGR     MSTRST       LL_HRTIM_BM_GetTrig\n

+  *         BMTRGR     MSTREP       LL_HRTIM_BM_GetTrig\n

+  *         BMTRGR     MSTCMP1      LL_HRTIM_BM_GetTrig\n

+  *         BMTRGR     MSTCMP2      LL_HRTIM_BM_GetTrig\n

+  *         BMTRGR     MSTCMP3      LL_HRTIM_BM_GetTrig\n

+  *         BMTRGR     MSTCMP4      LL_HRTIM_BM_GetTrig\n

+  *         BMTRGR     TARST        LL_HRTIM_BM_GetTrig\n

+  *         BMTRGR     TAREP        LL_HRTIM_BM_GetTrig\n

+  *         BMTRGR     TACMP1       LL_HRTIM_BM_GetTrig\n

+  *         BMTRGR     TACMP2       LL_HRTIM_BM_GetTrig\n

+  *         BMTRGR     TBRST        LL_HRTIM_BM_GetTrig\n

+  *         BMTRGR     TBREP        LL_HRTIM_BM_GetTrig\n

+  *         BMTRGR     TBCMP1       LL_HRTIM_BM_GetTrig\n

+  *         BMTRGR     TBCMP2       LL_HRTIM_BM_GetTrig\n

+  *         BMTRGR     TCRST        LL_HRTIM_BM_GetTrig\n

+  *         BMTRGR     TCREP        LL_HRTIM_BM_GetTrig\n

+  *         BMTRGR     TCCMP1       LL_HRTIM_BM_GetTrig\n

+  *         BMTRGR     TCCMP2       LL_HRTIM_BM_GetTrig\n

+  *         BMTRGR     TDRST        LL_HRTIM_BM_GetTrig\n

+  *         BMTRGR     TDREP        LL_HRTIM_BM_GetTrig\n

+  *         BMTRGR     TDCMP1       LL_HRTIM_BM_GetTrig\n

+  *         BMTRGR     TDCMP2       LL_HRTIM_BM_GetTrig\n

+  *         BMTRGR     TERST        LL_HRTIM_BM_GetTrig\n

+  *         BMTRGR     TEREP        LL_HRTIM_BM_GetTrig\n

+  *         BMTRGR     TECMP1       LL_HRTIM_BM_GetTrig\n

+  *         BMTRGR     TECMP2       LL_HRTIM_BM_GetTrig\n

+  *         BMTRGR     TAEEV7       LL_HRTIM_BM_GetTrig\n

+  *         BMTRGR     TAEEV8       LL_HRTIM_BM_GetTrig\n

+  *         BMTRGR     EEV7         LL_HRTIM_BM_GetTrig\n

+  *         BMTRGR     EEV8         LL_HRTIM_BM_GetTrig\n

+  *         BMTRGR     OCHIPEV      LL_HRTIM_BM_GetTrig

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval Trig This parameter can be a combination of the following values:

+  *         @arg @ref LL_HRTIM_BM_TRIG_NONE

+  *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_RESET

+  *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_REPETITION

+  *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP1

+  *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP2

+  *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP3

+  *         @arg @ref LL_HRTIM_BM_TRIG_MASTER_CMP4

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_RESET

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_REPETITION

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP1

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_CMP2

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_RESET

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_REPETITION

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP1

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMB_CMP2

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_RESET

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_REPETITION

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP1

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMC_CMP2

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_RESET

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_REPETITION

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP1

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_CMP2

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIME_RESET

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIME_REPETITION

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP1

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIME_CMP2

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMA_EVENT7

+  *         @arg @ref LL_HRTIM_BM_TRIG_TIMD_EVENT8

+  *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_7

+  *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_8

+  *         @arg @ref LL_HRTIM_BM_TRIG_EVENT_ONCHIP

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetTrig(HRTIM_TypeDef *HRTIMx)

+{

+  return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMTRGR);

+}

+

+/**

+  * @brief  Set the burst mode controller compare value.

+  * @rmtoll BMCMPR     BMCMP      LL_HRTIM_BM_SetCompare

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  CompareValue Compare value must be above or equal to 3

+  *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,

+  *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_BM_SetCompare(HRTIM_TypeDef *HRTIMx, uint32_t CompareValue)

+{

+  WRITE_REG(HRTIMx->sCommonRegs.BMCMPR, CompareValue);

+}

+

+/**

+  * @brief  Get actual burst mode controller compare value.

+  * @rmtoll BMCMPR     BMCMP      LL_HRTIM_BM_GetCompare

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval CompareValue Compare value must be above or equal to 3

+  *         periods of the fHRTIM clock, that is 0x60 if CKPSC[2:0] = 0,

+  *         0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetCompare(HRTIM_TypeDef *HRTIMx)

+{

+  return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMCMPR);

+}

+

+/**

+  * @brief  Set the burst mode controller period.

+  * @rmtoll BMPER     BMPER      LL_HRTIM_BM_SetPeriod

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Period The period value must be above or equal to 3 periods of the fHRTIM clock,

+  *         that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...

+  *         The maximum value is 0x0000 FFDF.

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_BM_SetPeriod(HRTIM_TypeDef *HRTIMx, uint32_t Period)

+{

+  WRITE_REG(HRTIMx->sCommonRegs.BMPER, Period);

+}

+

+/**

+  * @brief  Get actual burst mode controller period.

+  * @rmtoll BMPER     BMPER      LL_HRTIM_BM_GetPeriod

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval The period value must be above or equal to 3 periods of the fHRTIM clock,

+  *         that is 0x60 if CKPSC[2:0] = 0, 0x30 if CKPSC[2:0] = 1, 0x18 if CKPSC[2:0] = 2,...

+  *         The maximum value is 0x0000 FFDF.

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetPeriod(HRTIM_TypeDef *HRTIMx)

+{

+  return (uint32_t)READ_REG(HRTIMx->sCommonRegs.BMPER);

+}

+

+/**

+  * @brief  Enable the burst mode controller

+  * @rmtoll BMCR     BME      LL_HRTIM_BM_Enable

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_BM_Enable(HRTIM_TypeDef *HRTIMx)

+{

+  SET_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME);

+}

+

+/**

+  * @brief  Disable the burst mode controller

+  * @rmtoll BMCR     BME      LL_HRTIM_BM_Disable

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_BM_Disable(HRTIM_TypeDef *HRTIMx)

+{

+  CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME);

+}

+

+/**

+  * @brief  Indicate whether the burst mode controller is enabled.

+  * @rmtoll BMCR     BME      LL_HRTIM_BM_IsEnabled

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval State of BME bit in HRTIM_BMCR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_BM_IsEnabled(HRTIM_TypeDef *HRTIMx)

+{

+  return ((READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BME) == (HRTIM_BMCR_BME)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Trigger the burst operation (software trigger)

+  * @rmtoll BMTRGR     SW           LL_HRTIM_BM_Start

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_BM_Start(HRTIM_TypeDef *HRTIMx)

+{

+  SET_BIT(HRTIMx->sCommonRegs.BMTRGR, HRTIM_BMTRGR_SW);

+}

+

+/**

+  * @brief  Stop the burst mode operation.

+  * @rmtoll BMCR     BMSTAT           LL_HRTIM_BM_Stop

+  * @note Causes a burst mode early termination.

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_BM_Stop(HRTIM_TypeDef *HRTIMx)

+{

+  CLEAR_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT);

+}

+

+/**

+  * @brief  Get actual burst mode status

+  * @rmtoll BMCR     BMSTAT           LL_HRTIM_BM_GetStatus

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval Status This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_BM_STATUS_NORMAL

+  *         @arg @ref LL_HRTIM_BM_STATUS_BURST_ONGOING

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_BM_GetStatus(HRTIM_TypeDef *HRTIMx)

+{

+  return (READ_BIT(HRTIMx->sCommonRegs.BMCR, HRTIM_BMCR_BMSTAT));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EF_FLAG_Management FLAG_Management

+  * @{

+  */

+

+/**

+  * @brief  Clear the Fault 1 interrupt flag.

+  * @rmtoll ICR     FLT1C           LL_HRTIM_ClearFlag_FLT1

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT1(HRTIM_TypeDef *HRTIMx)

+{

+  SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT1C);

+}

+

+/**

+  * @brief  Indicate whether Fault 1 interrupt occurred.

+  * @rmtoll ICR     FLT1           LL_HRTIM_IsActiveFlag_FLT1

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval State of FLT1 bit in HRTIM_ISR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT1(HRTIM_TypeDef *HRTIMx)

+{

+  return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT1) == (HRTIM_ISR_FLT1)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the Fault 2 interrupt flag.

+  * @rmtoll ICR     FLT2C           LL_HRTIM_ClearFlag_FLT2

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT2(HRTIM_TypeDef *HRTIMx)

+{

+  SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT2C);

+}

+

+/**

+  * @brief  Indicate whether Fault 2 interrupt occurred.

+  * @rmtoll ICR     FLT2           LL_HRTIM_IsActiveFlag_FLT2

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval State of FLT2 bit in HRTIM_ISR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT2(HRTIM_TypeDef *HRTIMx)

+{

+  return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT2) == (HRTIM_ISR_FLT2)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the Fault 3 interrupt flag.

+  * @rmtoll ICR     FLT3C           LL_HRTIM_ClearFlag_FLT3

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT3(HRTIM_TypeDef *HRTIMx)

+{

+  SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT3C);

+}

+

+/**

+  * @brief  Indicate whether Fault 3 interrupt occurred.

+  * @rmtoll ICR     FLT3           LL_HRTIM_IsActiveFlag_FLT3

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval State of FLT3 bit in HRTIM_ISR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT3(HRTIM_TypeDef *HRTIMx)

+{

+  return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT3) == (HRTIM_ISR_FLT3)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the Fault 4 interrupt flag.

+  * @rmtoll ICR     FLT4C           LL_HRTIM_ClearFlag_FLT4

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT4(HRTIM_TypeDef *HRTIMx)

+{

+  SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT4C);

+}

+

+/**

+  * @brief  Indicate whether Fault 4 interrupt occurred.

+  * @rmtoll ICR     FLT4           LL_HRTIM_IsActiveFlag_FLT4

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval State of FLT4 bit in HRTIM_ISR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT4(HRTIM_TypeDef *HRTIMx)

+{

+  return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT4) == (HRTIM_ISR_FLT4)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the Fault 5 interrupt flag.

+  * @rmtoll ICR     FLT5C           LL_HRTIM_ClearFlag_FLT5

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_ClearFlag_FLT5(HRTIM_TypeDef *HRTIMx)

+{

+  SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_FLT5C);

+}

+

+/**

+  * @brief  Indicate whether Fault 5 interrupt occurred.

+  * @rmtoll ICR     FLT5           LL_HRTIM_IsActiveFlag_FLT5

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval State of FLT5 bit in HRTIM_ISR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_FLT5(HRTIM_TypeDef *HRTIMx)

+{

+  return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_FLT5) == (HRTIM_ISR_FLT5)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the System Fault interrupt flag.

+  * @rmtoll ICR     SYSFLTC           LL_HRTIM_ClearFlag_SYSFLT

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_ClearFlag_SYSFLT(HRTIM_TypeDef *HRTIMx)

+{

+  SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_SYSFLTC);

+}

+

+/**

+  * @brief  Indicate whether System Fault interrupt occurred.

+  * @rmtoll ISR     SYSFLT           LL_HRTIM_IsActiveFlag_SYSFLT

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval State of SYSFLT bit in HRTIM_ISR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYSFLT(HRTIM_TypeDef *HRTIMx)

+{

+  return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_SYSFLT) == (HRTIM_ISR_SYSFLT)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the Burst Mode period interrupt flag.

+  * @rmtoll ICR     BMPERC           LL_HRTIM_ClearFlag_BMPER

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_ClearFlag_BMPER(HRTIM_TypeDef *HRTIMx)

+{

+  SET_BIT(HRTIMx->sCommonRegs.ICR, HRTIM_ICR_BMPERC);

+}

+

+/**

+  * @brief  Indicate whether Burst Mode period interrupt occurred.

+  * @rmtoll ISR     BMPER           LL_HRTIM_IsActiveFlag_BMPER

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval State of BMPER bit in HRTIM_ISR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_BMPER(HRTIM_TypeDef *HRTIMx)

+{

+  return ((READ_BIT(HRTIMx->sCommonRegs.ISR, HRTIM_ISR_BMPER) == (HRTIM_ISR_BMPER)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the Synchronization Input interrupt flag.

+  * @rmtoll MICR     SYNCC           LL_HRTIM_ClearFlag_SYNC

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_ClearFlag_SYNC(HRTIM_TypeDef *HRTIMx)

+{

+  SET_BIT(HRTIMx->sMasterRegs.MICR, HRTIM_MICR_SYNC);

+}

+

+/**

+  * @brief  Indicate whether the Synchronization Input interrupt occurred.

+  * @rmtoll MISR     SYNC           LL_HRTIM_IsActiveFlag_SYNC

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval State of SYNC bit in HRTIM_MISR register  (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SYNC(HRTIM_TypeDef *HRTIMx)

+{

+  return ((READ_BIT(HRTIMx->sMasterRegs.MISR, HRTIM_MISR_SYNC) == (HRTIM_MISR_SYNC)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the update interrupt flag for a given timer (including the master timer) .

+  * @rmtoll MICR        MUPDC          LL_HRTIM_ClearFlag_UPDATE\n

+  *         TIMxICR     UPDC           LL_HRTIM_ClearFlag_UPDATE

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_ClearFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_MICR_MUPD);

+}

+

+/**

+  * @brief  Indicate whether the update interrupt has occurred for a given timer (including the master timer) .

+  * @rmtoll MISR        MUPD          LL_HRTIM_IsActiveFlag_UPDATE\n

+  *         TIMxISR     UPD           LL_HRTIM_IsActiveFlag_UPDATE

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of MUPD/UPD bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_MISR_MUPD) == (HRTIM_MISR_MUPD)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the repetition interrupt flag for a given timer (including the master timer) .

+  * @rmtoll MICR        MREPC          LL_HRTIM_ClearFlag_REP\n

+  *         TIMxICR     REPC           LL_HRTIM_ClearFlag_REP

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_ClearFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_MICR_MREP);

+

+}

+

+/**

+  * @brief  Indicate whether the repetition  interrupt has occurred for a given timer (including the master timer) .

+  * @rmtoll MISR        MREP          LL_HRTIM_IsActiveFlag_REP\n

+  *         TIMxISR     REP           LL_HRTIM_IsActiveFlag_REP

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of MREP/REP bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_MISR_MREP) == (HRTIM_MISR_MREP)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the compare 1 match interrupt for a given timer (including the master timer).

+  * @rmtoll MICR        MCMP1C          LL_HRTIM_ClearFlag_CMP1\n

+  *         TIMxICR     CMP1C           LL_HRTIM_ClearFlag_CMP1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_MICR_MCMP1);

+}

+

+/**

+  * @brief  Indicate whether the compare match 1  interrupt has occurred for a given timer (including the master timer) .

+  * @rmtoll MISR        MCMP1          LL_HRTIM_IsActiveFlag_CMP1\n

+  *         TIMxISR     CMP1           LL_HRTIM_IsActiveFlag_CMP1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of MCMP1/CMP1 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_MISR_MCMP1) == (HRTIM_MISR_MCMP1)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the compare 2 match interrupt for a given timer (including the master timer).

+  * @rmtoll MICR        MCMP2C          LL_HRTIM_ClearFlag_CMP2\n

+  *         TIMxICR     CMP2C           LL_HRTIM_ClearFlag_CMP2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_MICR_MCMP2);

+}

+

+/**

+  * @brief  Indicate whether the compare match 2  interrupt has occurred for a given timer (including the master timer) .

+  * @rmtoll MISR        MCMP2          LL_HRTIM_IsActiveFlag_CMP2\n

+  *         TIMxISR     CMP2           LL_HRTIM_IsActiveFlag_CMP2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of MCMP2/CMP2 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_MISR_MCMP2) == (HRTIM_MISR_MCMP2)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the compare 3 match interrupt for a given timer (including the master timer).

+  * @rmtoll MICR        MCMP3C          LL_HRTIM_ClearFlag_CMP3\n

+  *         TIMxICR     CMP3C           LL_HRTIM_ClearFlag_CMP3

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_MICR_MCMP3);

+}

+

+/**

+  * @brief  Indicate whether the compare match 3  interrupt has occurred for a given timer (including the master timer) .

+  * @rmtoll MISR        MCMP3          LL_HRTIM_IsActiveFlag_CMP3\n

+  *         TIMxISR     CMP3           LL_HRTIM_IsActiveFlag_CMP3

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of MCMP3/CMP3 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_MISR_MCMP3) == (HRTIM_MISR_MCMP3)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the compare 4 match interrupt for a given timer (including the master timer).

+  * @rmtoll MICR        MCMP4C          LL_HRTIM_ClearFlag_CMP4\n

+  *         TIMxICR     CMP4C           LL_HRTIM_ClearFlag_CMP4

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_ClearFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_MICR_MCMP4);

+}

+

+/**

+  * @brief  Indicate whether the compare match 4  interrupt has occurred for a given timer (including the master timer) .

+  * @rmtoll MISR        MCMP4          LL_HRTIM_IsActiveFlag_CMP4\n

+  *         TIMxISR     CMP4           LL_HRTIM_IsActiveFlag_CMP4

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of MCMP4/CMP4 bit in HRTIM_MISR/HRTIM_TIMxISR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_MISR_MCMP4) == (HRTIM_MISR_MCMP4)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the capture 1 interrupt flag for a given timer.

+  * @rmtoll TIMxICR     CPT1C           LL_HRTIM_ClearFlag_CPT1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_ClearFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_TIMICR_CPT1C);

+}

+

+/**

+  * @brief  Indicate whether the capture 1 interrupt occurred for a given timer.

+  * @rmtoll TIMxISR     CPT1           LL_HRTIM_IsActiveFlag_CPT1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of CPT1 bit in HRTIM_TIMxISR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT1) == (HRTIM_TIMISR_CPT1)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the capture 2 interrupt flag for a given timer.

+  * @rmtoll TIMxICR     CPT2C           LL_HRTIM_ClearFlag_CPT2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_ClearFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_TIMICR_CPT2C);

+}

+

+/**

+  * @brief  Indicate whether the capture 2 interrupt occurred for a given timer.

+  * @rmtoll TIMxISR     CPT2           LL_HRTIM_IsActiveFlag_CPT2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of CPT2 bit in HRTIM_TIMxISR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_TIMISR_CPT2) == (HRTIM_TIMISR_CPT2)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the output 1 set interrupt flag for a given timer.

+  * @rmtoll TIMxICR     SET1C           LL_HRTIM_ClearFlag_SET1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_ClearFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_TIMICR_SET1C);

+}

+

+/**

+  * @brief  Indicate whether the output 1 set interrupt occurred for a given timer.

+  * @rmtoll TIMxISR     SET1           LL_HRTIM_IsActiveFlag_SET1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of SETx1 bit in HRTIM_TIMxISR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_TIMISR_SET1) == (HRTIM_TIMISR_SET1)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the output 1 reset interrupt flag for a given timer.

+  * @rmtoll TIMxICR     RST1C           LL_HRTIM_ClearFlag_RST1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_ClearFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_TIMICR_RST1C);

+}

+

+/**

+  * @brief  Indicate whether the output 1 reset interrupt occurred for a given timer.

+  * @rmtoll TIMxISR     RST1           LL_HRTIM_IsActiveFlag_RST1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of RSTx1 bit in HRTIM_TIMxISR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_TIMISR_RST1) == (HRTIM_TIMISR_RST1)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the output 2 set interrupt flag for a given timer.

+  * @rmtoll TIMxICR     SET2C           LL_HRTIM_ClearFlag_SET2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_ClearFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_TIMICR_SET2C);

+}

+

+/**

+  * @brief  Indicate whether the output 2 set interrupt occurred for a given timer.

+  * @rmtoll TIMxISR     SET2           LL_HRTIM_IsActiveFlag_SET2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of SETx2 bit in HRTIM_TIMxISR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_TIMISR_SET2) == (HRTIM_TIMISR_SET2)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the output 2reset interrupt flag for a given timer.

+  * @rmtoll TIMxICR     RST2C           LL_HRTIM_ClearFlag_RST2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_ClearFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_TIMICR_RST2C);

+}

+

+/**

+  * @brief  Indicate whether the output 2 reset interrupt occurred for a given timer.

+  * @rmtoll TIMxISR     RST2           LL_HRTIM_IsActiveFlag_RST2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of RSTx2 bit in HRTIM_TIMxISR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_TIMISR_RST2) == (HRTIM_TIMISR_RST2)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the reset and/or roll-over interrupt flag for a given timer.

+  * @rmtoll TIMxICR     RSTC           LL_HRTIM_ClearFlag_RST

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_ClearFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_TIMICR_RSTC);

+}

+

+/**

+  * @brief  Indicate whether the  reset and/or roll-over interrupt occurred for a given timer.

+  * @rmtoll TIMxISR     RST           LL_HRTIM_IsActiveFlag_RST

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of RST bit in HRTIM_TIMxISR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_TIMISR_RST) == (HRTIM_TIMISR_RST)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the delayed protection interrupt flag for a given timer.

+  * @rmtoll TIMxICR     DLYPRTC           LL_HRTIM_ClearFlag_DLYPRT

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_ClearFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MICR) +

+                                                              REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_TIMICR_DLYPRTC);

+}

+

+/**

+  * @brief  Indicate whether the  delayed protection interrupt occurred for a given timer.

+  * @rmtoll TIMxISR     DLYPRT           LL_HRTIM_IsActiveFlag_DLYPRT

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of DLYPRT bit in HRTIM_TIMxISR register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsActiveFlag_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MISR) +

+                                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_TIMISR_DLYPRT) == (HRTIM_TIMISR_DLYPRT)) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EF_IT_Management IT_Management

+  * @{

+  */

+

+/**

+  * @brief  Enable the fault 1 interrupt.

+  * @rmtoll IER     FLT1IE           LL_HRTIM_EnableIT_FLT1

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableIT_FLT1(HRTIM_TypeDef *HRTIMx)

+{

+  SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1);

+}

+

+/**

+  * @brief  Disable the fault 1 interrupt.

+  * @rmtoll IER     FLT1IE           LL_HRTIM_DisableIT_FLT1

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableIT_FLT1(HRTIM_TypeDef *HRTIMx)

+{

+  CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1);

+}

+

+/**

+  * @brief  Indicate whether the fault 1 interrupt is enabled.

+  * @rmtoll IER     FLT1IE           LL_HRTIM_IsEnabledIT_FLT1

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval State of FLT1IE bit in HRTIM_IER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT1(HRTIM_TypeDef *HRTIMx)

+{

+  return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT1) == (HRTIM_IER_FLT1)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the fault 2 interrupt.

+  * @rmtoll IER     FLT2IE           LL_HRTIM_EnableIT_FLT2

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableIT_FLT2(HRTIM_TypeDef *HRTIMx)

+{

+  SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2);

+}

+

+/**

+  * @brief  Disable the fault 2 interrupt.

+  * @rmtoll IER     FLT2IE           LL_HRTIM_DisableIT_FLT2

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableIT_FLT2(HRTIM_TypeDef *HRTIMx)

+{

+  CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2);

+}

+

+/**

+  * @brief  Indicate whether the fault 2 interrupt is enabled.

+  * @rmtoll IER     FLT2IE           LL_HRTIM_IsEnabledIT_FLT2

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval State of FLT2IE bit in HRTIM_IER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT2(HRTIM_TypeDef *HRTIMx)

+{

+  return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT2) == (HRTIM_IER_FLT2)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the fault 3 interrupt.

+  * @rmtoll IER     FLT3IE           LL_HRTIM_EnableIT_FLT3

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableIT_FLT3(HRTIM_TypeDef *HRTIMx)

+{

+  SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3);

+}

+

+/**

+  * @brief  Disable the fault 3 interrupt.

+  * @rmtoll IER     FLT3IE           LL_HRTIM_DisableIT_FLT3

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableIT_FLT3(HRTIM_TypeDef *HRTIMx)

+{

+  CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3);

+}

+

+/**

+  * @brief  Indicate whether the fault 3 interrupt is enabled.

+  * @rmtoll IER     FLT3IE           LL_HRTIM_IsEnabledIT_FLT3

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval State of FLT3IE bit in HRTIM_IER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT3(HRTIM_TypeDef *HRTIMx)

+{

+  return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT3) == (HRTIM_IER_FLT3)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the fault 4 interrupt.

+  * @rmtoll IER     FLT4IE           LL_HRTIM_EnableIT_FLT4

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableIT_FLT4(HRTIM_TypeDef *HRTIMx)

+{

+  SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4);

+}

+

+/**

+  * @brief  Disable the fault 4 interrupt.

+  * @rmtoll IER     FLT4IE           LL_HRTIM_DisableIT_FLT4

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableIT_FLT4(HRTIM_TypeDef *HRTIMx)

+{

+  CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4);

+}

+

+/**

+  * @brief  Indicate whether the fault 4 interrupt is enabled.

+  * @rmtoll IER     FLT4IE           LL_HRTIM_IsEnabledIT_FLT4

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval State of FLT4IE bit in HRTIM_IER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT4(HRTIM_TypeDef *HRTIMx)

+{

+  return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT4) == (HRTIM_IER_FLT4)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the fault 5 interrupt.

+  * @rmtoll IER     FLT5IE           LL_HRTIM_EnableIT_FLT5

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableIT_FLT5(HRTIM_TypeDef *HRTIMx)

+{

+  SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5);

+}

+

+/**

+  * @brief  Disable the fault 5 interrupt.

+  * @rmtoll IER     FLT5IE           LL_HRTIM_DisableIT_FLT5

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableIT_FLT5(HRTIM_TypeDef *HRTIMx)

+{

+  CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5);

+}

+

+/**

+  * @brief  Indicate whether the fault 5 interrupt is enabled.

+  * @rmtoll IER     FLT5IE           LL_HRTIM_IsEnabledIT_FLT5

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval State of FLT5IE bit in HRTIM_IER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_FLT5(HRTIM_TypeDef *HRTIMx)

+{

+  return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_FLT5) == (HRTIM_IER_FLT5)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the system fault interrupt.

+  * @rmtoll IER     SYSFLTIE           LL_HRTIM_EnableIT_SYSFLT

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableIT_SYSFLT(HRTIM_TypeDef *HRTIMx)

+{

+  SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT);

+}

+

+/**

+  * @brief  Disable the system fault interrupt.

+  * @rmtoll IER     SYSFLTIE           LL_HRTIM_DisableIT_SYSFLT

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableIT_SYSFLT(HRTIM_TypeDef *HRTIMx)

+{

+  CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT);

+}

+

+/**

+  * @brief  Indicate whether the system fault interrupt is enabled.

+  * @rmtoll IER     SYSFLTIE           LL_HRTIM_IsEnabledIT_SYSFLT

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval State of SYSFLTIE bit in HRTIM_IER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYSFLT(HRTIM_TypeDef *HRTIMx)

+{

+  return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_SYSFLT) == (HRTIM_IER_SYSFLT)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the burst mode period interrupt.

+  * @rmtoll IER     BMPERIE           LL_HRTIM_EnableIT_BMPER

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableIT_BMPER(HRTIM_TypeDef *HRTIMx)

+{

+  SET_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER);

+}

+

+/**

+  * @brief  Disable the burst mode period interrupt.

+  * @rmtoll IER     BMPERIE           LL_HRTIM_DisableIT_BMPER

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableIT_BMPER(HRTIM_TypeDef *HRTIMx)

+{

+  CLEAR_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER);

+}

+

+/**

+  * @brief  Indicate whether the burst mode period interrupt is enabled.

+  * @rmtoll IER     BMPERIE           LL_HRTIM_IsEnabledIT_BMPER

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval State of BMPERIE bit in HRTIM_IER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_BMPER(HRTIM_TypeDef *HRTIMx)

+{

+  return ((READ_BIT(HRTIMx->sCommonRegs.IER, HRTIM_IER_BMPER) == (HRTIM_IER_BMPER)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the synchronization input interrupt.

+  * @rmtoll MDIER     SYNCIE           LL_HRTIM_EnableIT_SYNC

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableIT_SYNC(HRTIM_TypeDef *HRTIMx)

+{

+  SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE);

+}

+

+/**

+  * @brief  Disable the synchronization input interrupt.

+  * @rmtoll MDIER     SYNCIE           LL_HRTIM_DisableIT_SYNC

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableIT_SYNC(HRTIM_TypeDef *HRTIMx)

+{

+  CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE);

+}

+

+/**

+  * @brief  Indicate whether the synchronization input interrupt is enabled.

+  * @rmtoll MDIER     SYNCIE           LL_HRTIM_IsEnabledIT_SYNC

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval State of SYNCIE bit in HRTIM_MDIER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SYNC(HRTIM_TypeDef *HRTIMx)

+{

+  return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCIE) == (HRTIM_MDIER_SYNCIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the update interrupt for a given timer.

+  * @rmtoll MDIER        MUPDIE           LL_HRTIM_EnableIT_UPDATE\n

+  *         TIMxDIER     UPDIE            LL_HRTIM_EnableIT_UPDATE

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_MDIER_MUPDIE);

+}

+

+/**

+  * @brief  Disable the update interrupt for a given timer.

+  * @rmtoll MDIER        MUPDIE           LL_HRTIM_DisableIT_UPDATE\n

+  *         TIMxDIER     UPDIE            LL_HRTIM_DisableIT_UPDATE

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDIE);

+}

+

+/**

+  * @brief  Indicate whether the update interrupt is enabled for a given timer.

+  * @rmtoll MDIER        MUPDIE           LL_HRTIM_IsEnabledIT_UPDATE\n

+  *         TIMxDIER     UPDIE            LL_HRTIM_IsEnabledIT_UPDATE

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of MUPDIE/UPDIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDIE) == (HRTIM_MDIER_MUPDIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the repetition interrupt for a given timer.

+  * @rmtoll MDIER        MREPIE           LL_HRTIM_EnableIT_REP\n

+  *         TIMxDIER     REPIE            LL_HRTIM_EnableIT_REP

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_MDIER_MREPIE);

+}

+

+/**

+  * @brief  Disable the repetition interrupt for a given timer.

+  * @rmtoll MDIER        MREPIE           LL_HRTIM_DisableIT_REP\n

+  *         TIMxDIER     REPIE            LL_HRTIM_DisableIT_REP

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_MDIER_MREPIE);

+}

+

+/**

+  * @brief  Indicate whether the repetition interrupt is enabled for a given timer.

+  * @rmtoll MDIER        MREPIE           LL_HRTIM_IsEnabledIT_REP\n

+  *         TIMxDIER     REPIE            LL_HRTIM_IsEnabledIT_REP

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of MREPIE/REPIE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_MDIER_MREPIE) == (HRTIM_MDIER_MREPIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the compare 1 interrupt for a given timer.

+  * @rmtoll MDIER        MCMP1IE           LL_HRTIM_EnableIT_CMP1\n

+  *         TIMxDIER     CMP1IE            LL_HRTIM_EnableIT_CMP1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_MDIER_MCMP1IE);

+}

+

+/**

+  * @brief  Disable the compare 1 interrupt for a given timer.

+  * @rmtoll MDIER        MCMP1IE           LL_HRTIM_DisableIT_CMP1\n

+  *         TIMxDIER     CMP1IE            LL_HRTIM_DisableIT_CMP1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1IE);

+}

+

+/**

+  * @brief  Indicate whether the compare 1 interrupt is enabled for a given timer.

+  * @rmtoll MDIER        MCMP1IE           LL_HRTIM_IsEnabledIT_CMP1\n

+  *         TIMxDIER     CMP1IE            LL_HRTIM_IsEnabledIT_CMP1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of MCMP1IE/CMP1IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1IE) == (HRTIM_MDIER_MCMP1IE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the compare 2 interrupt for a given timer.

+  * @rmtoll MDIER        MCMP2IE           LL_HRTIM_EnableIT_CMP2\n

+  *         TIMxDIER     CMP2IE            LL_HRTIM_EnableIT_CMP2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_MDIER_MCMP2IE);

+}

+

+/**

+  * @brief  Disable the compare 2 interrupt for a given timer.

+  * @rmtoll MDIER        MCMP2IE           LL_HRTIM_DisableIT_CMP2\n

+  *         TIMxDIER     CMP2IE            LL_HRTIM_DisableIT_CMP2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2IE);

+}

+

+/**

+  * @brief  Indicate whether the compare 2 interrupt is enabled for a given timer.

+  * @rmtoll MDIER        MCMP2IE           LL_HRTIM_IsEnabledIT_CMP2\n

+  *         TIMxDIER     CMP2IE            LL_HRTIM_IsEnabledIT_CMP2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of MCMP2IE/CMP2IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2IE) == (HRTIM_MDIER_MCMP2IE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the compare 3 interrupt for a given timer.

+  * @rmtoll MDIER        MCMP3IE           LL_HRTIM_EnableIT_CMP3\n

+  *         TIMxDIER     CMP3IE            LL_HRTIM_EnableIT_CMP3

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_MDIER_MCMP3IE);

+}

+

+/**

+  * @brief  Disable the compare 3 interrupt for a given timer.

+  * @rmtoll MDIER        MCMP3IE           LL_HRTIM_DisableIT_CMP3\n

+  *         TIMxDIER     CMP3IE            LL_HRTIM_DisableIT_CMP3

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3IE);

+}

+

+/**

+  * @brief  Indicate whether the compare 3 interrupt is enabled for a given timer.

+  * @rmtoll MDIER        MCMP3IE           LL_HRTIM_IsEnabledIT_CMP3\n

+  *         TIMxDIER     CMP3IE            LL_HRTIM_IsEnabledIT_CMP3

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of MCMP3IE/CMP3IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3IE) == (HRTIM_MDIER_MCMP3IE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the compare 4 interrupt for a given timer.

+  * @rmtoll MDIER        MCMP4IE           LL_HRTIM_EnableIT_CMP4\n

+  *         TIMxDIER     CMP4IE            LL_HRTIM_EnableIT_CMP4

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_MDIER_MCMP4IE);

+}

+

+/**

+  * @brief  Disable the compare 4 interrupt for a given timer.

+  * @rmtoll MDIER        MCMP4IE           LL_HRTIM_DisableIT_CMP4\n

+  *         TIMxDIER     CMP4IE            LL_HRTIM_DisableIT_CMP4

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4IE);

+}

+

+/**

+  * @brief  Indicate whether the compare 4 interrupt is enabled for a given timer.

+  * @rmtoll MDIER        MCMP4IE           LL_HRTIM_IsEnabledIT_CMP4\n

+  *         TIMxDIER     CMP4IE            LL_HRTIM_IsEnabledIT_CMP4

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of MCMP4IE/CMP4IE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4IE) == (HRTIM_MDIER_MCMP4IE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the capture 1 interrupt for a given timer.

+  * @rmtoll TIMxDIER     CPT1IE            LL_HRTIM_EnableIT_CPT1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_TIMDIER_CPT1IE);

+}

+

+/**

+  * @brief  Enable the capture 1 interrupt for a given timer.

+  * @rmtoll TIMxDIER     CPT1IE            LL_HRTIM_DisableIT_CPT1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1IE);

+}

+

+/**

+  * @brief  Indicate whether the capture 1 interrupt is enabled for a given timer.

+  * @rmtoll TIMxDIER     CPT1IE            LL_HRTIM_IsEnabledIT_CPT1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of CPT1IE bit in HRTIM_TIMxDIER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1IE) == (HRTIM_TIMDIER_CPT1IE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the capture 2 interrupt for a given timer.

+  * @rmtoll TIMxDIER     CPT2IE            LL_HRTIM_EnableIT_CPT2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_TIMDIER_CPT2IE);

+}

+

+/**

+  * @brief  Enable the capture 2 interrupt for a given timer.

+  * @rmtoll TIMxDIER     CPT2IE            LL_HRTIM_DisableIT_CPT2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2IE);

+}

+

+/**

+  * @brief  Indicate whether the capture 2 interrupt is enabled for a given timer.

+  * @rmtoll TIMxDIER     CPT2IE            LL_HRTIM_IsEnabledIT_CPT2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of CPT2IE bit in HRTIM_TIMxDIER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2IE) == (HRTIM_TIMDIER_CPT2IE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the output 1 set interrupt for a given timer.

+  * @rmtoll TIMxDIER     SET1IE            LL_HRTIM_EnableIT_SET1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_TIMDIER_SET1IE);

+}

+

+/**

+  * @brief  Disable the output 1 set interrupt for a given timer.

+  * @rmtoll TIMxDIER     SET1IE            LL_HRTIM_DisableIT_SET1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1IE);

+}

+

+/**

+  * @brief  Indicate whether the output 1 set interrupt is enabled for a given timer.

+  * @rmtoll TIMxDIER     SET1IE            LL_HRTIM_IsEnabledIT_SET1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of SET1xIE bit in HRTIM_TIMxDIER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1IE) == (HRTIM_TIMDIER_SET1IE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the output 1 reset interrupt for a given timer.

+  * @rmtoll TIMxDIER     RST1IE            LL_HRTIM_EnableIT_RST1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_TIMDIER_RST1IE);

+}

+

+/**

+  * @brief  Disable the output 1 reset interrupt for a given timer.

+  * @rmtoll TIMxDIER     RST1IE            LL_HRTIM_DisableIT_RST1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1IE);

+}

+

+/**

+  * @brief  Indicate whether the output 1 reset interrupt is enabled for a given timer.

+  * @rmtoll TIMxDIER     RST1IE            LL_HRTIM_IsEnabledIT_RST1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of RST1xIE bit in HRTIM_TIMxDIER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1IE) == (HRTIM_TIMDIER_RST1IE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the output 2 set interrupt for a given timer.

+  * @rmtoll TIMxDIER     SET2IE            LL_HRTIM_EnableIT_SET2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_TIMDIER_SET2IE);

+}

+

+/**

+  * @brief  Disable the output 2 set interrupt for a given timer.

+  * @rmtoll TIMxDIER     SET2IE            LL_HRTIM_DisableIT_SET2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2IE);

+}

+

+/**

+  * @brief  Indicate whether the output 2 set interrupt is enabled for a given timer.

+  * @rmtoll TIMxDIER     SET2IE            LL_HRTIM_IsEnabledIT_SET2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of SET2xIE bit in HRTIM_TIMxDIER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2IE) == (HRTIM_TIMDIER_SET2IE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the output 2 reset interrupt for a given timer.

+  * @rmtoll TIMxDIER     RST2IE            LL_HRTIM_EnableIT_RST2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_TIMDIER_RST2IE);

+}

+

+/**

+  * @brief  Disable the output 2 reset interrupt for a given timer.

+  * @rmtoll TIMxDIER     RST2IE            LL_HRTIM_DisableIT_RST2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2IE);

+}

+

+/**

+  * @brief  Indicate whether the output 2 reset LL_HRTIM_IsEnabledIT_RST2 is enabled for a given timer.

+  * @rmtoll TIMxDIER     RST2IE            LL_HRTIM_DisableIT_RST2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of RST2xIE bit in HRTIM_TIMxDIER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2IE) == (HRTIM_TIMDIER_RST2IE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the reset/roll-over interrupt for a given timer.

+  * @rmtoll TIMxDIER     RSTIE            LL_HRTIM_EnableIT_RST

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_TIMDIER_RSTIE);

+}

+

+/**

+  * @brief  Disable the reset/roll-over interrupt for a given timer.

+  * @rmtoll TIMxDIER     RSTIE            LL_HRTIM_DisableIT_RST

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTIE);

+}

+

+/**

+  * @brief  Indicate whether the reset/roll-over interrupt is enabled for a given timer.

+  * @rmtoll TIMxDIER     RSTIE            LL_HRTIM_IsEnabledIT_RST

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of RSTIE bit in HRTIM_TIMxDIER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTIE) == (HRTIM_TIMDIER_RSTIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the delayed protection interrupt for a given timer.

+  * @rmtoll TIMxDIER     DLYPRTIE            LL_HRTIM_EnableIT_DLYPRT

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE);

+}

+

+/**

+  * @brief  Disable the delayed protection interrupt for a given timer.

+  * @rmtoll TIMxDIER     DLYPRTIE            LL_HRTIM_DisableIT_DLYPRT

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE);

+}

+

+/**

+  * @brief  Indicate whether the delayed protection interrupt is enabled for a given timer.

+  * @rmtoll TIMxDIER     DLYPRTIE            LL_HRTIM_IsEnabledIT_DLYPRT

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of DLYPRTIE bit in HRTIM_TIMxDIER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledIT_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTIE) == (HRTIM_TIMDIER_DLYPRTIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup HRTIM_LL_EF_DMA_Management DMA_Management

+  * @{

+  */

+

+/**

+  * @brief  Enable the synchronization input DMA request.

+  * @rmtoll MDIER     SYNCDE            LL_HRTIM_EnableDMAReq_SYNC

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)

+{

+  SET_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE);

+}

+

+/**

+  * @brief  Disable the synchronization input DMA request

+  * @rmtoll MDIER     SYNCDE            LL_HRTIM_DisableDMAReq_SYNC

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)

+{

+  CLEAR_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE);

+}

+

+/**

+  * @brief  Indicate whether the synchronization input DMA request is enabled.

+  * @rmtoll MDIER     SYNCDE            LL_HRTIM_IsEnabledDMAReq_SYNC

+  * @param  HRTIMx High Resolution Timer instance

+  * @retval State of SYNCDE bit in HRTIM_MDIER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SYNC(HRTIM_TypeDef *HRTIMx)

+{

+  return ((READ_BIT(HRTIMx->sMasterRegs.MDIER, HRTIM_MDIER_SYNCDE) == (HRTIM_MDIER_SYNCDE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the update DMA request for a given timer.

+  * @rmtoll MDIER        MUPDDE            LL_HRTIM_EnableDMAReq_UPDATE\n

+  *         TIMxDIER     UPDDE             LL_HRTIM_EnableDMAReq_UPDATE

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_MDIER_MUPDDE);

+}

+

+/**

+  * @brief  Disable the update DMA request for a given timer.

+  * @rmtoll MDIER        MUPDDE            LL_HRTIM_DisableDMAReq_UPDATE\n

+  *         TIMxDIER     UPDDE             LL_HRTIM_DisableDMAReq_UPDATE

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_MDIER_MUPDDE);

+}

+

+/**

+  * @brief  Indicate whether the update DMA request is enabled for a given timer.

+  * @rmtoll MDIER        MUPDDE            LL_HRTIM_IsEnabledDMAReq_UPDATE\n

+  *         TIMxDIER     UPDDE             LL_HRTIM_IsEnabledDMAReq_UPDATE

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of MUPDDE/UPDDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_UPDATE(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_MDIER_MUPDDE) == (HRTIM_MDIER_MUPDDE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the repetition DMA request for a given timer.

+  * @rmtoll MDIER        MREPDE            LL_HRTIM_EnableDMAReq_REP\n

+  *         TIMxDIER     REPDE             LL_HRTIM_EnableDMAReq_REP

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_MDIER_MREPDE);

+}

+

+/**

+  * @brief  Disable the repetition DMA request for a given timer.

+  * @rmtoll MDIER        MREPDE            LL_HRTIM_DisableDMAReq_REP\n

+  *         TIMxDIER     REPDE             LL_HRTIM_DisableDMAReq_REP

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_MDIER_MREPDE);

+}

+

+/**

+  * @brief  Indicate whether the repetition DMA request is enabled for a given timer.

+  * @rmtoll MDIER        MREPDE            LL_HRTIM_IsEnabledDMAReq_REP\n

+  *         TIMxDIER     REPDE             LL_HRTIM_IsEnabledDMAReq_REP

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of MREPDE/REPDE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_REP(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_MDIER_MREPDE) == (HRTIM_MDIER_MREPDE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the compare 1 DMA request for a given timer.

+  * @rmtoll MDIER        MCMP1DE            LL_HRTIM_EnableDMAReq_CMP1\n

+  *         TIMxDIER     CMP1DE             LL_HRTIM_EnableDMAReq_CMP1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_MDIER_MCMP1DE);

+}

+

+/**

+  * @brief  Disable the compare 1 DMA request for a given timer.

+  * @rmtoll MDIER        MCMP1DE            LL_HRTIM_DisableDMAReq_CMP1\n

+  *         TIMxDIER     CMP1DE             LL_HRTIM_DisableDMAReq_CMP1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP1DE);

+}

+

+/**

+  * @brief  Indicate whether the compare 1 DMA request is enabled for a given timer.

+  * @rmtoll MDIER        MCMP1DE            LL_HRTIM_IsEnabledDMAReq_CMP1\n

+  *         TIMxDIER     CMP1DE             LL_HRTIM_IsEnabledDMAReq_CMP1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of MCMP1DE/CMP1DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP1DE) == (HRTIM_MDIER_MCMP1DE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the compare 2 DMA request for a given timer.

+  * @rmtoll MDIER        MCMP2DE            LL_HRTIM_EnableDMAReq_CMP2\n

+  *         TIMxDIER     CMP2DE             LL_HRTIM_EnableDMAReq_CMP2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_MDIER_MCMP2DE);

+}

+

+/**

+  * @brief  Disable the compare 2 DMA request for a given timer.

+  * @rmtoll MDIER        MCMP2DE            LL_HRTIM_DisableDMAReq_CMP2\n

+  *         TIMxDIER     CMP2DE             LL_HRTIM_DisableDMAReq_CMP2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP2DE);

+}

+

+/**

+  * @brief  Indicate whether the compare 2 DMA request is enabled for a given timer.

+  * @rmtoll MDIER        MCMP2DE            LL_HRTIM_IsEnabledDMAReq_CMP2\n

+  *         TIMxDIER     CMP2DE             LL_HRTIM_IsEnabledDMAReq_CMP2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of MCMP2DE/CMP2DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP2DE) == (HRTIM_MDIER_MCMP2DE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the compare 3 DMA request for a given timer.

+  * @rmtoll MDIER        MCMP3DE            LL_HRTIM_EnableDMAReq_CMP3\n

+  *         TIMxDIER     CMP3DE             LL_HRTIM_EnableDMAReq_CMP3

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_MDIER_MCMP3DE);

+}

+

+/**

+  * @brief  Disable the compare 3 DMA request for a given timer.

+  * @rmtoll MDIER        MCMP3DE            LL_HRTIM_DisableDMAReq_CMP3\n

+  *         TIMxDIER     CMP3DE             LL_HRTIM_DisableDMAReq_CMP3

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP3DE);

+}

+

+/**

+  * @brief  Indicate whether the compare 3 DMA request is enabled for a given timer.

+  * @rmtoll MDIER        MCMP3DE            LL_HRTIM_IsEnabledDMAReq_CMP3\n

+  *         TIMxDIER     CMP3DE             LL_HRTIM_IsEnabledDMAReq_CMP3

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of MCMP3DE/CMP3DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP3(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP3DE) == (HRTIM_MDIER_MCMP3DE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the compare 4 DMA request for a given timer.

+  * @rmtoll MDIER        MCMP4DE            LL_HRTIM_EnableDMAReq_CMP4\n

+  *         TIMxDIER     CMP4DE             LL_HRTIM_EnableDMAReq_CMP4

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_MDIER_MCMP4DE);

+}

+

+/**

+  * @brief  Disable the compare 4 DMA request for a given timer.

+  * @rmtoll MDIER        MCMP4DE            LL_HRTIM_DisableDMAReq_CMP4\n

+  *         TIMxDIER     CMP4DE             LL_HRTIM_DisableDMAReq_CMP4

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_MDIER_MCMP4DE);

+}

+

+/**

+  * @brief  Indicate whether the compare 4 DMA request is enabled for a given timer.

+  * @rmtoll MDIER        MCMP4DE            LL_HRTIM_IsEnabledDMAReq_CMP4\n

+  *         TIMxDIER     CMP4DE             LL_HRTIM_IsEnabledDMAReq_CMP4

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_MASTER

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of MCMP4DE/CMP4DE bit in HRTIM_MDIER/HRTIM_TIMxDIER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CMP4(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_MDIER_MCMP4DE) == (HRTIM_MDIER_MCMP4DE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the capture 1 DMA request for a given timer.

+  * @rmtoll TIMxDIER     CPT1DE             LL_HRTIM_EnableDMAReq_CPT1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_TIMDIER_CPT1DE);

+}

+

+/**

+  * @brief  Disable the capture 1 DMA request for a given timer.

+  * @rmtoll TIMxDIER     CPT1DE             LL_HRTIM_DisableDMAReq_CPT1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT1DE);

+}

+

+/**

+  * @brief  Indicate whether the capture 1 DMA request is enabled for a given timer.

+  * @rmtoll TIMxDIER     CPT1DE             LL_HRTIM_IsEnabledDMAReq_CPT1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of CPT1DE bit in HRTIM_TIMxDIER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT1DE) == (HRTIM_TIMDIER_CPT1DE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the capture 2 DMA request for a given timer.

+  * @rmtoll TIMxDIER     CPT2DE             LL_HRTIM_EnableDMAReq_CPT2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_TIMDIER_CPT2DE);

+}

+

+/**

+  * @brief  Disable the capture 2 DMA request for a given timer.

+  * @rmtoll TIMxDIER     CPT2DE             LL_HRTIM_DisableDMAReq_CPT2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_CPT2DE);

+}

+

+/**

+  * @brief  Indicate whether the capture 2 DMA request is enabled for a given timer.

+  * @rmtoll TIMxDIER     CPT2DE             LL_HRTIM_IsEnabledDMAReq_CPT2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of CPT2DE bit in HRTIM_TIMxDIER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_CPT2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_CPT2DE) == (HRTIM_TIMDIER_CPT2DE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the output 1 set  DMA request for a given timer.

+  * @rmtoll TIMxDIER     SET1DE             LL_HRTIM_EnableDMAReq_SET1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_TIMDIER_SET1DE);

+}

+

+/**

+  * @brief  Disable the output 1 set  DMA request for a given timer.

+  * @rmtoll TIMxDIER     SET1DE             LL_HRTIM_DisableDMAReq_SET1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET1DE);

+}

+

+/**

+  * @brief  Indicate whether the output 1 set  DMA request is enabled for a given timer.

+  * @rmtoll TIMxDIER     SET1DE             LL_HRTIM_IsEnabledDMAReq_SET1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of SET1xDE bit in HRTIM_TIMxDIER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET1DE) == (HRTIM_TIMDIER_SET1DE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the output 1 reset  DMA request for a given timer.

+  * @rmtoll TIMxDIER     RST1DE             LL_HRTIM_EnableDMAReq_RST1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_TIMDIER_RST1DE);

+}

+

+/**

+  * @brief  Disable the output 1 reset  DMA request for a given timer.

+  * @rmtoll TIMxDIER     RST1DE             LL_HRTIM_DisableDMAReq_RST1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST1DE);

+}

+

+/**

+  * @brief  Indicate whether the output 1 reset interrupt is enabled for a given timer.

+  * @rmtoll TIMxDIER     RST1DE             LL_HRTIM_IsEnabledDMAReq_RST1

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of RST1xDE bit in HRTIM_TIMxDIER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST1(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST1DE) == (HRTIM_TIMDIER_RST1DE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the output 2 set  DMA request for a given timer.

+  * @rmtoll TIMxDIER     SET2DE             LL_HRTIM_EnableDMAReq_SET2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_TIMDIER_SET2DE);

+}

+

+/**

+  * @brief  Disable the output 2 set  DMA request for a given timer.

+  * @rmtoll TIMxDIER     SET2DE             LL_HRTIM_DisableDMAReq_SET2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_SET2DE);

+}

+

+/**

+  * @brief  Indicate whether the output 2 set  DMA request is enabled for a given timer.

+  * @rmtoll TIMxDIER     SET2DE             LL_HRTIM_IsEnabledDMAReq_SET2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of SET2xDE bit in HRTIM_TIMxDIER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_SET2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_SET2DE) == (HRTIM_TIMDIER_SET2DE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the output 2 reset  DMA request for a given timer.

+  * @rmtoll TIMxDIER     RST2DE             LL_HRTIM_EnableDMAReq_RST2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_TIMDIER_RST2DE);

+}

+

+/**

+  * @brief  Disable the output 2 reset  DMA request for a given timer.

+  * @rmtoll TIMxDIER     RST2DE             LL_HRTIM_DisableDMAReq_RST2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_RST2DE);

+}

+

+/**

+  * @brief  Indicate whether the output 2 reset  DMA request is enabled for a given timer.

+  * @rmtoll TIMxDIER     RST2DE             LL_HRTIM_IsEnabledDMAReq_RST2

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of RST2xDE bit in HRTIM_TIMxDIER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST2(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_RST2DE) == (HRTIM_TIMDIER_RST2DE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the reset/roll-over DMA request for a given timer.

+  * @rmtoll TIMxDIER     RSTDE             LL_HRTIM_EnableDMAReq_RST

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_TIMDIER_RSTDE);

+}

+

+/**

+  * @brief  Disable the reset/roll-over DMA request for a given timer.

+  * @rmtoll TIMxDIER     RSTDE             LL_HRTIM_DisableDMAReq_RST

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_RSTDE);

+}

+

+/**

+  * @brief  Indicate whether the reset/roll-over DMA request is enabled for a given timer.

+  * @rmtoll TIMxDIER     RSTDE             LL_HRTIM_IsEnabledDMAReq_RST

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of RSTDE bit in HRTIM_TIMxDIER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_RST(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_RSTDE) == (HRTIM_TIMDIER_RSTDE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the delayed protection DMA request for a given timer.

+  * @rmtoll TIMxDIER     DLYPRTDE             LL_HRTIM_EnableDMAReq_DLYPRT

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_EnableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  SET_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE);

+}

+

+/**

+  * @brief  Disable the delayed protection DMA request for a given timer.

+  * @rmtoll TIMxDIER     DLYPRTDE             LL_HRTIM_DisableDMAReq_DLYPRT

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval None

+  */

+__STATIC_INLINE void LL_HRTIM_DisableDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+  CLEAR_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE);

+}

+

+/**

+  * @brief  Indicate whether the delayed protection DMA request is enabled for a given timer.

+  * @rmtoll TIMxDIER     DLYPRTDE             LL_HRTIM_IsEnabledDMAReq_DLYPRT

+  * @param  HRTIMx High Resolution Timer instance

+  * @param  Timer This parameter can be one of the following values:

+  *         @arg @ref LL_HRTIM_TIMER_A

+  *         @arg @ref LL_HRTIM_TIMER_B

+  *         @arg @ref LL_HRTIM_TIMER_C

+  *         @arg @ref LL_HRTIM_TIMER_D

+  *         @arg @ref LL_HRTIM_TIMER_E

+  * @retval State of DLYPRTDE bit in HRTIM_TIMxDIER register (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HRTIM_IsEnabledDMAReq_DLYPRT(HRTIM_TypeDef *HRTIMx, uint32_t Timer)

+{

+  register uint32_t iTimer = (uint8_t)(POSITION_VAL(Timer) - HRTIM_MCR_MCEN_Pos);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&HRTIMx->sMasterRegs.MDIER) +

+                                                    REG_OFFSET_TAB_TIMER[iTimer]));

+

+  return ((READ_BIT(*pReg, HRTIM_TIMDIER_DLYPRTDE) == (HRTIM_TIMDIER_DLYPRTDE)) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup HRTIM_LL_LL_EF_Init In-initialization and de-initialization functions

+  * @{

+  */

+ErrorStatus LL_HRTIM_DeInit(HRTIM_TypeDef* HRTIMx);

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* HRTIM1 */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_LL_HRTIM_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

+

+

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_hsem.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_hsem.h
new file mode 100644
index 0000000000..d0256f3287
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_hsem.h
@@ -0,0 +1,901 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_hsem.h

+  * @author  MCD Application Team

+  * @brief   Header file of HSEM LL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_LL_HSEM_H

+#define STM32H7xx_LL_HSEM_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+#if defined(HSEM)

+

+/** @defgroup HSEM_LL HSEM

+  * @{

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/* Private macros ------------------------------------------------------------*/

+

+/* Exported types ------------------------------------------------------------*/

+/* Exported constants --------------------------------------------------------*/

+

+/** @defgroup HSEM_LL_Exported_Constants HSEM Exported Constants

+  * @{

+  */

+

+/** @defgroup HSEM_LL_EC_COREID COREID Defines

+  * @{

+  */

+#define LL_HSEM_COREID_NONE             0U

+#define LL_HSEM_COREID_CPU1             HSEM_CR_COREID_CPU1

+#if defined(DUAL_CORE)

+#define LL_HSEM_COREID_CPU2             HSEM_CR_COREID_CPU2

+#endif /* DUAL_CORE */

+#define LL_HSEM_COREID                  HSEM_CR_COREID_CURRENT

+/**

+  * @}

+  */

+

+/** @defgroup HSEM_LL_EC_GET_FLAG Get Flags Defines

+  * @brief    Flags defines which can be used with LL_HSEM_ReadReg function

+  * @{

+  */

+

+#define LL_HSEM_SEMAPHORE_0                HSEM_C1IER_ISE0

+#define LL_HSEM_SEMAPHORE_1                HSEM_C1IER_ISE1

+#define LL_HSEM_SEMAPHORE_2                HSEM_C1IER_ISE2

+#define LL_HSEM_SEMAPHORE_3                HSEM_C1IER_ISE3

+#define LL_HSEM_SEMAPHORE_4                HSEM_C1IER_ISE4

+#define LL_HSEM_SEMAPHORE_5                HSEM_C1IER_ISE5

+#define LL_HSEM_SEMAPHORE_6                HSEM_C1IER_ISE6

+#define LL_HSEM_SEMAPHORE_7                HSEM_C1IER_ISE7

+#define LL_HSEM_SEMAPHORE_8                HSEM_C1IER_ISE8

+#define LL_HSEM_SEMAPHORE_9                HSEM_C1IER_ISE9

+#define LL_HSEM_SEMAPHORE_10               HSEM_C1IER_ISE10

+#define LL_HSEM_SEMAPHORE_11               HSEM_C1IER_ISE11

+#define LL_HSEM_SEMAPHORE_12               HSEM_C1IER_ISE12

+#define LL_HSEM_SEMAPHORE_13               HSEM_C1IER_ISE13

+#define LL_HSEM_SEMAPHORE_14               HSEM_C1IER_ISE14

+#define LL_HSEM_SEMAPHORE_15               HSEM_C1IER_ISE15

+#if (HSEM_SEMID_MAX == 15)

+#define LL_HSEM_SEMAPHORE_ALL              0x0000FFFFU

+#else /* HSEM_SEMID_MAX == 31 */

+#define LL_HSEM_SEMAPHORE_16               HSEM_C1IER_ISE16

+#define LL_HSEM_SEMAPHORE_17               HSEM_C1IER_ISE17

+#define LL_HSEM_SEMAPHORE_18               HSEM_C1IER_ISE18

+#define LL_HSEM_SEMAPHORE_19               HSEM_C1IER_ISE19

+#define LL_HSEM_SEMAPHORE_20               HSEM_C1IER_ISE20

+#define LL_HSEM_SEMAPHORE_21               HSEM_C1IER_ISE21

+#define LL_HSEM_SEMAPHORE_22               HSEM_C1IER_ISE22

+#define LL_HSEM_SEMAPHORE_23               HSEM_C1IER_ISE23

+#define LL_HSEM_SEMAPHORE_24               HSEM_C1IER_ISE24

+#define LL_HSEM_SEMAPHORE_25               HSEM_C1IER_ISE25

+#define LL_HSEM_SEMAPHORE_26               HSEM_C1IER_ISE26

+#define LL_HSEM_SEMAPHORE_27               HSEM_C1IER_ISE27

+#define LL_HSEM_SEMAPHORE_28               HSEM_C1IER_ISE28

+#define LL_HSEM_SEMAPHORE_29               HSEM_C1IER_ISE29

+#define LL_HSEM_SEMAPHORE_30               HSEM_C1IER_ISE30

+#define LL_HSEM_SEMAPHORE_31               HSEM_C1IER_ISE31

+#define LL_HSEM_SEMAPHORE_ALL              0xFFFFFFFFU

+#endif /* HSEM_SEMID_MAX == 15 */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup HSEM_LL_Exported_Macros HSEM Exported Macros

+  * @{

+  */

+

+/** @defgroup HSEM_LL_EM_WRITE_READ Common Write and read registers Macros

+  * @{

+  */

+

+/**

+  * @brief  Write a value in HSEM register

+  * @param  __INSTANCE__ HSEM Instance

+  * @param  __REG__ Register to be written

+  * @param  __VALUE__ Value to be written in the register

+  * @retval None

+  */

+#define LL_HSEM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

+

+/**

+  * @brief  Read a value in HSEM register

+  * @param  __INSTANCE__ HSEM Instance

+  * @param  __REG__ Register to be read

+  * @retval Register value

+  */

+#define LL_HSEM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup HSEM_LL_Exported_Functions HSEM Exported Functions

+  * @{

+  */

+

+/** @defgroup HSEM_LL_EF_Data_Management Data_Management

+  * @{

+  */

+

+

+/**

+  * @brief  Return 1 if the semaphore is locked, else return 0.

+  * @rmtoll R            LOCK          LL_HSEM_IsSemaphoreLocked

+  * @param  HSEMx HSEM Instance.

+  * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(HSEM_TypeDef *HSEMx, uint32_t Semaphore)

+{

+  return ((READ_BIT(HSEMx->R[Semaphore], HSEM_R_LOCK) == (HSEM_R_LOCK_Msk)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get core id.

+  * @rmtoll R            COREID        LL_HSEM_GetCoreId

+  * @param  HSEMx HSEM Instance.

+  * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_HSEM_COREID_NONE

+  *         @arg @ref LL_HSEM_COREID_CPU1

+  *         @arg @ref LL_HSEM_COREID_CPU2

+  */

+__STATIC_INLINE uint32_t LL_HSEM_GetCoreId(HSEM_TypeDef *HSEMx, uint32_t Semaphore)

+{

+  return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_COREID_Msk));

+}

+

+/**

+  * @brief  Get process id.

+  * @rmtoll R            PROCID        LL_HSEM_GetProcessId

+  * @param  HSEMx HSEM Instance.

+  * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31

+  * @retval Process number. Value between Min_Data=0 and Max_Data=255

+  */

+__STATIC_INLINE uint32_t LL_HSEM_GetProcessId(HSEM_TypeDef *HSEMx, uint32_t Semaphore)

+{

+  return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_PROCID_Msk));

+}

+

+/**

+  * @brief  Get the lock by writing in R register.

+  * @note The R register has to be read to determined if the lock is taken.

+  * @rmtoll R            LOCK          LL_HSEM_SetLock

+  * @rmtoll R            COREID        LL_HSEM_SetLock

+  * @rmtoll R            PROCID        LL_HSEM_SetLock

+  * @param  HSEMx HSEM Instance.

+  * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31

+  * @param  process Process id. Value between Min_Data=0 and Max_Data=255

+  * @retval None

+  */

+__STATIC_INLINE void LL_HSEM_SetLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)

+{

+  WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process));

+}

+

+/**

+  * @brief  Get the lock with 2-step lock.

+  * @rmtoll R            LOCK          LL_HSEM_2StepLock

+  * @rmtoll R            COREID        LL_HSEM_2StepLock

+  * @rmtoll R            PROCID        LL_HSEM_2StepLock

+  * @param  HSEMx HSEM Instance.

+  * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31

+  * @param  process Process id. Value between Min_Data=0 and Max_Data=255

+  * @retval 1 lock fail, 0 lock successful or already locked by same process and core

+  */

+__STATIC_INLINE uint32_t LL_HSEM_2StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)

+{

+  WRITE_REG(HSEMx->R[Semaphore], (HSEM_R_LOCK | LL_HSEM_COREID | process));

+  return ((HSEMx->R[Semaphore] != (HSEM_R_LOCK | LL_HSEM_COREID | process)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get the lock with 1-step lock.

+  * @rmtoll RLR          LOCK          LL_HSEM_1StepLock

+  * @rmtoll RLR          COREID        LL_HSEM_1StepLock

+  * @rmtoll RLR          PROCID        LL_HSEM_1StepLock

+  * @param  HSEMx HSEM Instance.

+  * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31

+  * @retval 1 lock fail, 0 lock successful or already locked by same core

+  */

+__STATIC_INLINE uint32_t LL_HSEM_1StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore)

+{

+  return ((HSEMx->RLR[Semaphore] != (HSEM_R_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Release the lock of the semaphore.

+  * @note In case of LL_HSEM_1StepLock usage to lock a semaphore, the process is 0.

+  * @rmtoll R            LOCK          LL_HSEM_ReleaseLock

+  * @param  HSEMx HSEM Instance.

+  * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31

+  * @param  process Process number. Value between Min_Data=0 and Max_Data=255

+  * @retval None

+  */

+__STATIC_INLINE void LL_HSEM_ReleaseLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore, uint32_t process)

+{

+  WRITE_REG(HSEMx->R[Semaphore], (LL_HSEM_COREID | process));

+}

+

+/**

+  * @brief  Get the lock status of the semaphore.

+  * @rmtoll R            LOCK          LL_HSEM_GetStatus

+  * @param  HSEMx HSEM Instance.

+  * @param  Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31

+  * @retval 0 semaphore is free, 1 semaphore is locked  */

+__STATIC_INLINE uint32_t LL_HSEM_GetStatus(HSEM_TypeDef *HSEMx, uint32_t Semaphore)

+{

+  return ((HSEMx->R[Semaphore] != 0U) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set the key.

+  * @rmtoll KEYR         KEY           LL_HSEM_SetKey

+  * @param  HSEMx HSEM Instance.

+  * @param  key Key value.

+  * @retval None

+  */

+__STATIC_INLINE void LL_HSEM_SetKey(HSEM_TypeDef *HSEMx, uint32_t key)

+{

+  WRITE_REG(HSEMx->KEYR, key << HSEM_KEYR_KEY_Pos);

+}

+

+/**

+  * @brief  Get the key.

+  * @rmtoll KEYR         KEY           LL_HSEM_GetKey

+  * @param  HSEMx HSEM Instance.

+  * @retval key to unlock all semaphore from the same core

+  */

+__STATIC_INLINE uint32_t LL_HSEM_GetKey(HSEM_TypeDef *HSEMx)

+{

+  return (uint32_t)(READ_BIT(HSEMx->KEYR, HSEM_KEYR_KEY) >> HSEM_KEYR_KEY_Pos);

+}

+

+/**

+  * @brief  Release all semaphore with the same core id.

+  * @rmtoll CR           KEY           LL_HSEM_ResetAllLock

+  * @param  HSEMx HSEM Instance.

+  * @param  key Key value.

+  * @param  core This parameter can be one of the following values:

+  *         @arg @ref LL_HSEM_COREID_CPU1

+  *         @arg @ref LL_HSEM_COREID_CPU2

+  * @retval None

+  */

+__STATIC_INLINE void LL_HSEM_ResetAllLock(HSEM_TypeDef *HSEMx, uint32_t key, uint32_t core)

+{

+  WRITE_REG(HSEMx->CR, (key << HSEM_CR_KEY_Pos) | core);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup HSEM_LL_EF_IT_Management IT_Management

+  * @{

+  */

+

+/**

+  * @brief  Enable interrupt.

+  * @rmtoll C1IER         ISEM          LL_HSEM_EnableIT_C1IER

+  * @param  HSEMx HSEM Instance.

+  * @param  SemaphoreMask This parameter can be a combination of the following values:

+  *         @arg @ref LL_HSEM_SEMAPHORE_0

+  *         @arg @ref LL_HSEM_SEMAPHORE_1

+  *         @arg @ref LL_HSEM_SEMAPHORE_2

+  *         @arg @ref LL_HSEM_SEMAPHORE_3

+  *         @arg @ref LL_HSEM_SEMAPHORE_4

+  *         @arg @ref LL_HSEM_SEMAPHORE_5

+  *         @arg @ref LL_HSEM_SEMAPHORE_6

+  *         @arg @ref LL_HSEM_SEMAPHORE_7

+  *         @arg @ref LL_HSEM_SEMAPHORE_8

+  *         @arg @ref LL_HSEM_SEMAPHORE_9

+  *         @arg @ref LL_HSEM_SEMAPHORE_10

+  *         @arg @ref LL_HSEM_SEMAPHORE_11

+  *         @arg @ref LL_HSEM_SEMAPHORE_12

+  *         @arg @ref LL_HSEM_SEMAPHORE_13

+  *         @arg @ref LL_HSEM_SEMAPHORE_14

+  *         @arg @ref LL_HSEM_SEMAPHORE_15

+  *         @arg @ref LL_HSEM_SEMAPHORE_16

+  *         @arg @ref LL_HSEM_SEMAPHORE_17

+  *         @arg @ref LL_HSEM_SEMAPHORE_18

+  *         @arg @ref LL_HSEM_SEMAPHORE_19

+  *         @arg @ref LL_HSEM_SEMAPHORE_20

+  *         @arg @ref LL_HSEM_SEMAPHORE_21

+  *         @arg @ref LL_HSEM_SEMAPHORE_22

+  *         @arg @ref LL_HSEM_SEMAPHORE_23

+  *         @arg @ref LL_HSEM_SEMAPHORE_24

+  *         @arg @ref LL_HSEM_SEMAPHORE_25

+  *         @arg @ref LL_HSEM_SEMAPHORE_26

+  *         @arg @ref LL_HSEM_SEMAPHORE_27

+  *         @arg @ref LL_HSEM_SEMAPHORE_28

+  *         @arg @ref LL_HSEM_SEMAPHORE_29

+  *         @arg @ref LL_HSEM_SEMAPHORE_30

+  *         @arg @ref LL_HSEM_SEMAPHORE_31

+  *         @arg @ref LL_HSEM_SEMAPHORE_ALL

+  * @note   Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31

+  *         depends on devices.

+  * @retval None

+  */

+__STATIC_INLINE void LL_HSEM_EnableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)

+{

+  SET_BIT(HSEMx->C1IER, SemaphoreMask);

+}

+

+/**

+  * @brief  Disable interrupt.

+  * @rmtoll C1IER          ISEM          LL_HSEM_DisableIT_C1IER

+  * @param  HSEMx HSEM Instance.

+  * @param  SemaphoreMask This parameter can be a combination of the following values:

+  *         @arg @ref LL_HSEM_SEMAPHORE_0

+  *         @arg @ref LL_HSEM_SEMAPHORE_1

+  *         @arg @ref LL_HSEM_SEMAPHORE_2

+  *         @arg @ref LL_HSEM_SEMAPHORE_3

+  *         @arg @ref LL_HSEM_SEMAPHORE_4

+  *         @arg @ref LL_HSEM_SEMAPHORE_5

+  *         @arg @ref LL_HSEM_SEMAPHORE_6

+  *         @arg @ref LL_HSEM_SEMAPHORE_7

+  *         @arg @ref LL_HSEM_SEMAPHORE_8

+  *         @arg @ref LL_HSEM_SEMAPHORE_9

+  *         @arg @ref LL_HSEM_SEMAPHORE_10

+  *         @arg @ref LL_HSEM_SEMAPHORE_11

+  *         @arg @ref LL_HSEM_SEMAPHORE_12

+  *         @arg @ref LL_HSEM_SEMAPHORE_13

+  *         @arg @ref LL_HSEM_SEMAPHORE_14

+  *         @arg @ref LL_HSEM_SEMAPHORE_15

+  *         @arg @ref LL_HSEM_SEMAPHORE_16

+  *         @arg @ref LL_HSEM_SEMAPHORE_17

+  *         @arg @ref LL_HSEM_SEMAPHORE_18

+  *         @arg @ref LL_HSEM_SEMAPHORE_19

+  *         @arg @ref LL_HSEM_SEMAPHORE_20

+  *         @arg @ref LL_HSEM_SEMAPHORE_21

+  *         @arg @ref LL_HSEM_SEMAPHORE_22

+  *         @arg @ref LL_HSEM_SEMAPHORE_23

+  *         @arg @ref LL_HSEM_SEMAPHORE_24

+  *         @arg @ref LL_HSEM_SEMAPHORE_25

+  *         @arg @ref LL_HSEM_SEMAPHORE_26

+  *         @arg @ref LL_HSEM_SEMAPHORE_27

+  *         @arg @ref LL_HSEM_SEMAPHORE_28

+  *         @arg @ref LL_HSEM_SEMAPHORE_29

+  *         @arg @ref LL_HSEM_SEMAPHORE_30

+  *         @arg @ref LL_HSEM_SEMAPHORE_31

+  *         @arg @ref LL_HSEM_SEMAPHORE_ALL

+  * @note   Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31

+  *         depends on devices.

+  * @retval None

+  */

+__STATIC_INLINE void LL_HSEM_DisableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)

+{

+  CLEAR_BIT(HSEMx->C1IER, SemaphoreMask);

+}

+

+/**

+  * @brief  Check if interrupt is enabled.

+  * @rmtoll C1IER          ISEM          LL_HSEM_IsEnabledIT_C1IER

+  * @param  HSEMx HSEM Instance.

+  * @param  SemaphoreMask This parameter can be a combination of the following values:

+  *         @arg @ref LL_HSEM_SEMAPHORE_0

+  *         @arg @ref LL_HSEM_SEMAPHORE_1

+  *         @arg @ref LL_HSEM_SEMAPHORE_2

+  *         @arg @ref LL_HSEM_SEMAPHORE_3

+  *         @arg @ref LL_HSEM_SEMAPHORE_4

+  *         @arg @ref LL_HSEM_SEMAPHORE_5

+  *         @arg @ref LL_HSEM_SEMAPHORE_6

+  *         @arg @ref LL_HSEM_SEMAPHORE_7

+  *         @arg @ref LL_HSEM_SEMAPHORE_8

+  *         @arg @ref LL_HSEM_SEMAPHORE_9

+  *         @arg @ref LL_HSEM_SEMAPHORE_10

+  *         @arg @ref LL_HSEM_SEMAPHORE_11

+  *         @arg @ref LL_HSEM_SEMAPHORE_12

+  *         @arg @ref LL_HSEM_SEMAPHORE_13

+  *         @arg @ref LL_HSEM_SEMAPHORE_14

+  *         @arg @ref LL_HSEM_SEMAPHORE_15

+  *         @arg @ref LL_HSEM_SEMAPHORE_16

+  *         @arg @ref LL_HSEM_SEMAPHORE_17

+  *         @arg @ref LL_HSEM_SEMAPHORE_18

+  *         @arg @ref LL_HSEM_SEMAPHORE_19

+  *         @arg @ref LL_HSEM_SEMAPHORE_20

+  *         @arg @ref LL_HSEM_SEMAPHORE_21

+  *         @arg @ref LL_HSEM_SEMAPHORE_22

+  *         @arg @ref LL_HSEM_SEMAPHORE_23

+  *         @arg @ref LL_HSEM_SEMAPHORE_24

+  *         @arg @ref LL_HSEM_SEMAPHORE_25

+  *         @arg @ref LL_HSEM_SEMAPHORE_26

+  *         @arg @ref LL_HSEM_SEMAPHORE_27

+  *         @arg @ref LL_HSEM_SEMAPHORE_28

+  *         @arg @ref LL_HSEM_SEMAPHORE_29

+  *         @arg @ref LL_HSEM_SEMAPHORE_30

+  *         @arg @ref LL_HSEM_SEMAPHORE_31

+  *         @arg @ref LL_HSEM_SEMAPHORE_ALL

+  * @note   Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31

+  *         depends on devices.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)

+{

+  return ((READ_BIT(HSEMx->C1IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);

+}

+

+#if defined(DUAL_CORE)

+/**

+  * @brief  Enable interrupt.

+  * @rmtoll C2IER         ISEM          LL_HSEM_EnableIT_C2IER

+  * @param  HSEMx HSEM Instance.

+  * @param  SemaphoreMask This parameter can be a combination of the following values:

+  *         @arg @ref LL_HSEM_SEMAPHORE_0

+  *         @arg @ref LL_HSEM_SEMAPHORE_1

+  *         @arg @ref LL_HSEM_SEMAPHORE_2

+  *         @arg @ref LL_HSEM_SEMAPHORE_3

+  *         @arg @ref LL_HSEM_SEMAPHORE_4

+  *         @arg @ref LL_HSEM_SEMAPHORE_5

+  *         @arg @ref LL_HSEM_SEMAPHORE_6

+  *         @arg @ref LL_HSEM_SEMAPHORE_7

+  *         @arg @ref LL_HSEM_SEMAPHORE_8

+  *         @arg @ref LL_HSEM_SEMAPHORE_9

+  *         @arg @ref LL_HSEM_SEMAPHORE_10

+  *         @arg @ref LL_HSEM_SEMAPHORE_11

+  *         @arg @ref LL_HSEM_SEMAPHORE_12

+  *         @arg @ref LL_HSEM_SEMAPHORE_13

+  *         @arg @ref LL_HSEM_SEMAPHORE_14

+  *         @arg @ref LL_HSEM_SEMAPHORE_15

+  *         @arg @ref LL_HSEM_SEMAPHORE_16

+  *         @arg @ref LL_HSEM_SEMAPHORE_17

+  *         @arg @ref LL_HSEM_SEMAPHORE_18

+  *         @arg @ref LL_HSEM_SEMAPHORE_19

+  *         @arg @ref LL_HSEM_SEMAPHORE_20

+  *         @arg @ref LL_HSEM_SEMAPHORE_21

+  *         @arg @ref LL_HSEM_SEMAPHORE_22

+  *         @arg @ref LL_HSEM_SEMAPHORE_23

+  *         @arg @ref LL_HSEM_SEMAPHORE_24

+  *         @arg @ref LL_HSEM_SEMAPHORE_25

+  *         @arg @ref LL_HSEM_SEMAPHORE_26

+  *         @arg @ref LL_HSEM_SEMAPHORE_27

+  *         @arg @ref LL_HSEM_SEMAPHORE_28

+  *         @arg @ref LL_HSEM_SEMAPHORE_29

+  *         @arg @ref LL_HSEM_SEMAPHORE_30

+  *         @arg @ref LL_HSEM_SEMAPHORE_31

+  *         @arg @ref LL_HSEM_SEMAPHORE_ALL

+  * @retval None

+  */

+__STATIC_INLINE void LL_HSEM_EnableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)

+{

+  SET_BIT(HSEMx->C2IER, SemaphoreMask);

+}

+

+/**

+  * @brief  Disable interrupt.

+  * @rmtoll C2IER          ISEM          LL_HSEM_DisableIT_C2IER

+  * @param  HSEMx HSEM Instance.

+  * @param  SemaphoreMask This parameter can be a combination of the following values:

+  *         @arg @ref LL_HSEM_SEMAPHORE_0

+  *         @arg @ref LL_HSEM_SEMAPHORE_1

+  *         @arg @ref LL_HSEM_SEMAPHORE_2

+  *         @arg @ref LL_HSEM_SEMAPHORE_3

+  *         @arg @ref LL_HSEM_SEMAPHORE_4

+  *         @arg @ref LL_HSEM_SEMAPHORE_5

+  *         @arg @ref LL_HSEM_SEMAPHORE_6

+  *         @arg @ref LL_HSEM_SEMAPHORE_7

+  *         @arg @ref LL_HSEM_SEMAPHORE_8

+  *         @arg @ref LL_HSEM_SEMAPHORE_9

+  *         @arg @ref LL_HSEM_SEMAPHORE_10

+  *         @arg @ref LL_HSEM_SEMAPHORE_11

+  *         @arg @ref LL_HSEM_SEMAPHORE_12

+  *         @arg @ref LL_HSEM_SEMAPHORE_13

+  *         @arg @ref LL_HSEM_SEMAPHORE_14

+  *         @arg @ref LL_HSEM_SEMAPHORE_15

+  *         @arg @ref LL_HSEM_SEMAPHORE_16

+  *         @arg @ref LL_HSEM_SEMAPHORE_17

+  *         @arg @ref LL_HSEM_SEMAPHORE_18

+  *         @arg @ref LL_HSEM_SEMAPHORE_19

+  *         @arg @ref LL_HSEM_SEMAPHORE_20

+  *         @arg @ref LL_HSEM_SEMAPHORE_21

+  *         @arg @ref LL_HSEM_SEMAPHORE_22

+  *         @arg @ref LL_HSEM_SEMAPHORE_23

+  *         @arg @ref LL_HSEM_SEMAPHORE_24

+  *         @arg @ref LL_HSEM_SEMAPHORE_25

+  *         @arg @ref LL_HSEM_SEMAPHORE_26

+  *         @arg @ref LL_HSEM_SEMAPHORE_27

+  *         @arg @ref LL_HSEM_SEMAPHORE_28

+  *         @arg @ref LL_HSEM_SEMAPHORE_29

+  *         @arg @ref LL_HSEM_SEMAPHORE_30

+  *         @arg @ref LL_HSEM_SEMAPHORE_31

+  *         @arg @ref LL_HSEM_SEMAPHORE_ALL

+  * @retval None

+  */

+__STATIC_INLINE void LL_HSEM_DisableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)

+{

+  CLEAR_BIT(HSEMx->C2IER, SemaphoreMask);

+}

+

+/**

+  * @brief  Check if interrupt is enabled.

+  * @rmtoll C2IER          ISEM          LL_HSEM_IsEnabledIT_C2IER

+  * @param  HSEMx HSEM Instance.

+  * @param  SemaphoreMask This parameter can be a combination of the following values:

+  *         @arg @ref LL_HSEM_SEMAPHORE_0

+  *         @arg @ref LL_HSEM_SEMAPHORE_1

+  *         @arg @ref LL_HSEM_SEMAPHORE_2

+  *         @arg @ref LL_HSEM_SEMAPHORE_3

+  *         @arg @ref LL_HSEM_SEMAPHORE_4

+  *         @arg @ref LL_HSEM_SEMAPHORE_5

+  *         @arg @ref LL_HSEM_SEMAPHORE_6

+  *         @arg @ref LL_HSEM_SEMAPHORE_7

+  *         @arg @ref LL_HSEM_SEMAPHORE_8

+  *         @arg @ref LL_HSEM_SEMAPHORE_9

+  *         @arg @ref LL_HSEM_SEMAPHORE_10

+  *         @arg @ref LL_HSEM_SEMAPHORE_11

+  *         @arg @ref LL_HSEM_SEMAPHORE_12

+  *         @arg @ref LL_HSEM_SEMAPHORE_13

+  *         @arg @ref LL_HSEM_SEMAPHORE_14

+  *         @arg @ref LL_HSEM_SEMAPHORE_15

+  *         @arg @ref LL_HSEM_SEMAPHORE_16

+  *         @arg @ref LL_HSEM_SEMAPHORE_17

+  *         @arg @ref LL_HSEM_SEMAPHORE_18

+  *         @arg @ref LL_HSEM_SEMAPHORE_19

+  *         @arg @ref LL_HSEM_SEMAPHORE_20

+  *         @arg @ref LL_HSEM_SEMAPHORE_21

+  *         @arg @ref LL_HSEM_SEMAPHORE_22

+  *         @arg @ref LL_HSEM_SEMAPHORE_23

+  *         @arg @ref LL_HSEM_SEMAPHORE_24

+  *         @arg @ref LL_HSEM_SEMAPHORE_25

+  *         @arg @ref LL_HSEM_SEMAPHORE_26

+  *         @arg @ref LL_HSEM_SEMAPHORE_27

+  *         @arg @ref LL_HSEM_SEMAPHORE_28

+  *         @arg @ref LL_HSEM_SEMAPHORE_29

+  *         @arg @ref LL_HSEM_SEMAPHORE_30

+  *         @arg @ref LL_HSEM_SEMAPHORE_31

+  *         @arg @ref LL_HSEM_SEMAPHORE_ALL

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)

+{

+  return ((READ_BIT(HSEMx->C2IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);

+}

+#endif /* DUAL_CORE */

+/**

+  * @}

+  */

+

+/** @defgroup HSEM_LL_EF_FLAG_Management FLAG_Management

+  * @{

+  */

+

+/**

+  * @brief  Clear interrupt status.

+  * @rmtoll C1ICR         ISEM          LL_HSEM_ClearFlag_C1ICR

+  * @param  HSEMx HSEM Instance.

+  * @param  SemaphoreMask This parameter can be a combination of the following values:

+  *         @arg @ref LL_HSEM_SEMAPHORE_0

+  *         @arg @ref LL_HSEM_SEMAPHORE_1

+  *         @arg @ref LL_HSEM_SEMAPHORE_2

+  *         @arg @ref LL_HSEM_SEMAPHORE_3

+  *         @arg @ref LL_HSEM_SEMAPHORE_4

+  *         @arg @ref LL_HSEM_SEMAPHORE_5

+  *         @arg @ref LL_HSEM_SEMAPHORE_6

+  *         @arg @ref LL_HSEM_SEMAPHORE_7

+  *         @arg @ref LL_HSEM_SEMAPHORE_8

+  *         @arg @ref LL_HSEM_SEMAPHORE_9

+  *         @arg @ref LL_HSEM_SEMAPHORE_10

+  *         @arg @ref LL_HSEM_SEMAPHORE_11

+  *         @arg @ref LL_HSEM_SEMAPHORE_12

+  *         @arg @ref LL_HSEM_SEMAPHORE_13

+  *         @arg @ref LL_HSEM_SEMAPHORE_14

+  *         @arg @ref LL_HSEM_SEMAPHORE_15

+  *         @arg @ref LL_HSEM_SEMAPHORE_16

+  *         @arg @ref LL_HSEM_SEMAPHORE_17

+  *         @arg @ref LL_HSEM_SEMAPHORE_18

+  *         @arg @ref LL_HSEM_SEMAPHORE_19

+  *         @arg @ref LL_HSEM_SEMAPHORE_20

+  *         @arg @ref LL_HSEM_SEMAPHORE_21

+  *         @arg @ref LL_HSEM_SEMAPHORE_22

+  *         @arg @ref LL_HSEM_SEMAPHORE_23

+  *         @arg @ref LL_HSEM_SEMAPHORE_24

+  *         @arg @ref LL_HSEM_SEMAPHORE_25

+  *         @arg @ref LL_HSEM_SEMAPHORE_26

+  *         @arg @ref LL_HSEM_SEMAPHORE_27

+  *         @arg @ref LL_HSEM_SEMAPHORE_28

+  *         @arg @ref LL_HSEM_SEMAPHORE_29

+  *         @arg @ref LL_HSEM_SEMAPHORE_30

+  *         @arg @ref LL_HSEM_SEMAPHORE_31

+  *         @arg @ref LL_HSEM_SEMAPHORE_ALL

+  * @note   Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31

+  *         depends on devices.

+  * @retval None

+  */

+__STATIC_INLINE void LL_HSEM_ClearFlag_C1ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)

+{

+  WRITE_REG(HSEMx->C1ICR, SemaphoreMask);

+}

+

+/**

+  * @brief  Get interrupt status from ISR register.

+  * @rmtoll C1ISR         ISEM          LL_HSEM_IsActiveFlag_C1ISR

+  * @param  HSEMx HSEM Instance.

+  * @param  SemaphoreMask This parameter can be a combination of the following values:

+  *         @arg @ref LL_HSEM_SEMAPHORE_0

+  *         @arg @ref LL_HSEM_SEMAPHORE_1

+  *         @arg @ref LL_HSEM_SEMAPHORE_2

+  *         @arg @ref LL_HSEM_SEMAPHORE_3

+  *         @arg @ref LL_HSEM_SEMAPHORE_4

+  *         @arg @ref LL_HSEM_SEMAPHORE_5

+  *         @arg @ref LL_HSEM_SEMAPHORE_6

+  *         @arg @ref LL_HSEM_SEMAPHORE_7

+  *         @arg @ref LL_HSEM_SEMAPHORE_8

+  *         @arg @ref LL_HSEM_SEMAPHORE_9

+  *         @arg @ref LL_HSEM_SEMAPHORE_10

+  *         @arg @ref LL_HSEM_SEMAPHORE_11

+  *         @arg @ref LL_HSEM_SEMAPHORE_12

+  *         @arg @ref LL_HSEM_SEMAPHORE_13

+  *         @arg @ref LL_HSEM_SEMAPHORE_14

+  *         @arg @ref LL_HSEM_SEMAPHORE_15

+  *         @arg @ref LL_HSEM_SEMAPHORE_16

+  *         @arg @ref LL_HSEM_SEMAPHORE_17

+  *         @arg @ref LL_HSEM_SEMAPHORE_18

+  *         @arg @ref LL_HSEM_SEMAPHORE_19

+  *         @arg @ref LL_HSEM_SEMAPHORE_20

+  *         @arg @ref LL_HSEM_SEMAPHORE_21

+  *         @arg @ref LL_HSEM_SEMAPHORE_22

+  *         @arg @ref LL_HSEM_SEMAPHORE_23

+  *         @arg @ref LL_HSEM_SEMAPHORE_24

+  *         @arg @ref LL_HSEM_SEMAPHORE_25

+  *         @arg @ref LL_HSEM_SEMAPHORE_26

+  *         @arg @ref LL_HSEM_SEMAPHORE_27

+  *         @arg @ref LL_HSEM_SEMAPHORE_28

+  *         @arg @ref LL_HSEM_SEMAPHORE_29

+  *         @arg @ref LL_HSEM_SEMAPHORE_30

+  *         @arg @ref LL_HSEM_SEMAPHORE_31

+  *         @arg @ref LL_HSEM_SEMAPHORE_ALL

+  * @note   Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31

+  *         depends on devices.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)

+{

+  return ((READ_BIT(HSEMx->C1ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get interrupt status from MISR register.

+  * @rmtoll C1MISR        ISEM          LL_HSEM_IsActiveFlag_C1MISR

+  * @param  HSEMx HSEM Instance.

+  * @param  SemaphoreMask This parameter can be a combination of the following values:

+  *         @arg @ref LL_HSEM_SEMAPHORE_0

+  *         @arg @ref LL_HSEM_SEMAPHORE_1

+  *         @arg @ref LL_HSEM_SEMAPHORE_2

+  *         @arg @ref LL_HSEM_SEMAPHORE_3

+  *         @arg @ref LL_HSEM_SEMAPHORE_4

+  *         @arg @ref LL_HSEM_SEMAPHORE_5

+  *         @arg @ref LL_HSEM_SEMAPHORE_6

+  *         @arg @ref LL_HSEM_SEMAPHORE_7

+  *         @arg @ref LL_HSEM_SEMAPHORE_8

+  *         @arg @ref LL_HSEM_SEMAPHORE_9

+  *         @arg @ref LL_HSEM_SEMAPHORE_10

+  *         @arg @ref LL_HSEM_SEMAPHORE_11

+  *         @arg @ref LL_HSEM_SEMAPHORE_12

+  *         @arg @ref LL_HSEM_SEMAPHORE_13

+  *         @arg @ref LL_HSEM_SEMAPHORE_14

+  *         @arg @ref LL_HSEM_SEMAPHORE_15

+  *         @arg @ref LL_HSEM_SEMAPHORE_16

+  *         @arg @ref LL_HSEM_SEMAPHORE_17

+  *         @arg @ref LL_HSEM_SEMAPHORE_18

+  *         @arg @ref LL_HSEM_SEMAPHORE_19

+  *         @arg @ref LL_HSEM_SEMAPHORE_20

+  *         @arg @ref LL_HSEM_SEMAPHORE_21

+  *         @arg @ref LL_HSEM_SEMAPHORE_22

+  *         @arg @ref LL_HSEM_SEMAPHORE_23

+  *         @arg @ref LL_HSEM_SEMAPHORE_24

+  *         @arg @ref LL_HSEM_SEMAPHORE_25

+  *         @arg @ref LL_HSEM_SEMAPHORE_26

+  *         @arg @ref LL_HSEM_SEMAPHORE_27

+  *         @arg @ref LL_HSEM_SEMAPHORE_28

+  *         @arg @ref LL_HSEM_SEMAPHORE_29

+  *         @arg @ref LL_HSEM_SEMAPHORE_30

+  *         @arg @ref LL_HSEM_SEMAPHORE_31

+  *         @arg @ref LL_HSEM_SEMAPHORE_ALL

+  * @note   Availability of flags LL_HSEM_SEMAPHORE_16 to LL_HSEM_SEMAPHORE_31

+  *         depends on devices.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)

+{

+  return ((READ_BIT(HSEMx->C1MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);

+}

+

+#if defined(DUAL_CORE)

+/**

+  * @brief  Clear interrupt status.

+  * @rmtoll C2ICR         ISEM          LL_HSEM_ClearFlag_C2ICR

+  * @param  HSEMx HSEM Instance.

+  * @param  SemaphoreMask This parameter can be a combination of the following values:

+  *         @arg @ref LL_HSEM_SEMAPHORE_0

+  *         @arg @ref LL_HSEM_SEMAPHORE_1

+  *         @arg @ref LL_HSEM_SEMAPHORE_2

+  *         @arg @ref LL_HSEM_SEMAPHORE_3

+  *         @arg @ref LL_HSEM_SEMAPHORE_4

+  *         @arg @ref LL_HSEM_SEMAPHORE_5

+  *         @arg @ref LL_HSEM_SEMAPHORE_6

+  *         @arg @ref LL_HSEM_SEMAPHORE_7

+  *         @arg @ref LL_HSEM_SEMAPHORE_8

+  *         @arg @ref LL_HSEM_SEMAPHORE_9

+  *         @arg @ref LL_HSEM_SEMAPHORE_10

+  *         @arg @ref LL_HSEM_SEMAPHORE_11

+  *         @arg @ref LL_HSEM_SEMAPHORE_12

+  *         @arg @ref LL_HSEM_SEMAPHORE_13

+  *         @arg @ref LL_HSEM_SEMAPHORE_14

+  *         @arg @ref LL_HSEM_SEMAPHORE_15

+  *         @arg @ref LL_HSEM_SEMAPHORE_16

+  *         @arg @ref LL_HSEM_SEMAPHORE_17

+  *         @arg @ref LL_HSEM_SEMAPHORE_18

+  *         @arg @ref LL_HSEM_SEMAPHORE_19

+  *         @arg @ref LL_HSEM_SEMAPHORE_20

+  *         @arg @ref LL_HSEM_SEMAPHORE_21

+  *         @arg @ref LL_HSEM_SEMAPHORE_22

+  *         @arg @ref LL_HSEM_SEMAPHORE_23

+  *         @arg @ref LL_HSEM_SEMAPHORE_24

+  *         @arg @ref LL_HSEM_SEMAPHORE_25

+  *         @arg @ref LL_HSEM_SEMAPHORE_26

+  *         @arg @ref LL_HSEM_SEMAPHORE_27

+  *         @arg @ref LL_HSEM_SEMAPHORE_28

+  *         @arg @ref LL_HSEM_SEMAPHORE_29

+  *         @arg @ref LL_HSEM_SEMAPHORE_30

+  *         @arg @ref LL_HSEM_SEMAPHORE_31

+  *         @arg @ref LL_HSEM_SEMAPHORE_ALL

+  * @retval None

+  */

+__STATIC_INLINE void LL_HSEM_ClearFlag_C2ICR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)

+{

+  WRITE_REG(HSEMx->C2ICR, SemaphoreMask);

+}

+

+/**

+  * @brief  Get interrupt status from ISR register.

+  * @rmtoll C2ISR         ISEM          LL_HSEM_IsActiveFlag_C2ISR

+  * @param  HSEMx HSEM Instance.

+  * @param  SemaphoreMask This parameter can be a combination of the following values:

+  *         @arg @ref LL_HSEM_SEMAPHORE_0

+  *         @arg @ref LL_HSEM_SEMAPHORE_1

+  *         @arg @ref LL_HSEM_SEMAPHORE_2

+  *         @arg @ref LL_HSEM_SEMAPHORE_3

+  *         @arg @ref LL_HSEM_SEMAPHORE_4

+  *         @arg @ref LL_HSEM_SEMAPHORE_5

+  *         @arg @ref LL_HSEM_SEMAPHORE_6

+  *         @arg @ref LL_HSEM_SEMAPHORE_7

+  *         @arg @ref LL_HSEM_SEMAPHORE_8

+  *         @arg @ref LL_HSEM_SEMAPHORE_9

+  *         @arg @ref LL_HSEM_SEMAPHORE_10

+  *         @arg @ref LL_HSEM_SEMAPHORE_11

+  *         @arg @ref LL_HSEM_SEMAPHORE_12

+  *         @arg @ref LL_HSEM_SEMAPHORE_13

+  *         @arg @ref LL_HSEM_SEMAPHORE_14

+  *         @arg @ref LL_HSEM_SEMAPHORE_15

+  *         @arg @ref LL_HSEM_SEMAPHORE_16

+  *         @arg @ref LL_HSEM_SEMAPHORE_17

+  *         @arg @ref LL_HSEM_SEMAPHORE_18

+  *         @arg @ref LL_HSEM_SEMAPHORE_19

+  *         @arg @ref LL_HSEM_SEMAPHORE_20

+  *         @arg @ref LL_HSEM_SEMAPHORE_21

+  *         @arg @ref LL_HSEM_SEMAPHORE_22

+  *         @arg @ref LL_HSEM_SEMAPHORE_23

+  *         @arg @ref LL_HSEM_SEMAPHORE_24

+  *         @arg @ref LL_HSEM_SEMAPHORE_25

+  *         @arg @ref LL_HSEM_SEMAPHORE_26

+  *         @arg @ref LL_HSEM_SEMAPHORE_27

+  *         @arg @ref LL_HSEM_SEMAPHORE_28

+  *         @arg @ref LL_HSEM_SEMAPHORE_29

+  *         @arg @ref LL_HSEM_SEMAPHORE_30

+  *         @arg @ref LL_HSEM_SEMAPHORE_31

+  *         @arg @ref LL_HSEM_SEMAPHORE_ALL

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)

+{

+  return ((READ_BIT(HSEMx->C2ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get interrupt status from MISR register.

+  * @rmtoll C2MISR        ISEM          LL_HSEM_IsActiveFlag_C2MISR

+  * @param  HSEMx HSEM Instance.

+  * @param  SemaphoreMask This parameter can be a combination of the following values:

+  *         @arg @ref LL_HSEM_SEMAPHORE_0

+  *         @arg @ref LL_HSEM_SEMAPHORE_1

+  *         @arg @ref LL_HSEM_SEMAPHORE_2

+  *         @arg @ref LL_HSEM_SEMAPHORE_3

+  *         @arg @ref LL_HSEM_SEMAPHORE_4

+  *         @arg @ref LL_HSEM_SEMAPHORE_5

+  *         @arg @ref LL_HSEM_SEMAPHORE_6

+  *         @arg @ref LL_HSEM_SEMAPHORE_7

+  *         @arg @ref LL_HSEM_SEMAPHORE_8

+  *         @arg @ref LL_HSEM_SEMAPHORE_9

+  *         @arg @ref LL_HSEM_SEMAPHORE_10

+  *         @arg @ref LL_HSEM_SEMAPHORE_11

+  *         @arg @ref LL_HSEM_SEMAPHORE_12

+  *         @arg @ref LL_HSEM_SEMAPHORE_13

+  *         @arg @ref LL_HSEM_SEMAPHORE_14

+  *         @arg @ref LL_HSEM_SEMAPHORE_15

+  *         @arg @ref LL_HSEM_SEMAPHORE_16

+  *         @arg @ref LL_HSEM_SEMAPHORE_17

+  *         @arg @ref LL_HSEM_SEMAPHORE_18

+  *         @arg @ref LL_HSEM_SEMAPHORE_19

+  *         @arg @ref LL_HSEM_SEMAPHORE_20

+  *         @arg @ref LL_HSEM_SEMAPHORE_21

+  *         @arg @ref LL_HSEM_SEMAPHORE_22

+  *         @arg @ref LL_HSEM_SEMAPHORE_23

+  *         @arg @ref LL_HSEM_SEMAPHORE_24

+  *         @arg @ref LL_HSEM_SEMAPHORE_25

+  *         @arg @ref LL_HSEM_SEMAPHORE_26

+  *         @arg @ref LL_HSEM_SEMAPHORE_27

+  *         @arg @ref LL_HSEM_SEMAPHORE_28

+  *         @arg @ref LL_HSEM_SEMAPHORE_29

+  *         @arg @ref LL_HSEM_SEMAPHORE_30

+  *         @arg @ref LL_HSEM_SEMAPHORE_31

+  *         @arg @ref LL_HSEM_SEMAPHORE_ALL

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask)

+{

+  return ((READ_BIT(HSEMx->C2MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL);

+}

+#endif /* DUAL_CORE */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* defined(HSEM) */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* __STM32H7xx_LL_HSEM_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_i2c.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_i2c.h
new file mode 100644
index 0000000000..5656b27d63
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_i2c.h
@@ -0,0 +1,2228 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_i2c.h

+  * @author  MCD Application Team

+  * @brief   Header file of I2C LL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_LL_I2C_H

+#define STM32H7xx_LL_I2C_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+#if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4)

+

+/** @defgroup I2C_LL I2C

+  * @{

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup I2C_LL_Private_Constants I2C Private Constants

+  * @{

+  */

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup I2C_LL_Private_Macros I2C Private Macros

+  * @{

+  */

+/**

+  * @}

+  */

+#endif /*USE_FULL_LL_DRIVER*/

+

+/* Exported types ------------------------------------------------------------*/

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure

+  * @{

+  */

+typedef struct

+{

+  uint32_t PeripheralMode;      /*!< Specifies the peripheral mode.

+                                     This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE

+

+                                     This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */

+

+  uint32_t Timing;              /*!< Specifies the SDA setup, hold time and the SCL high, low period values.

+                                     This parameter must be set by referring to the STM32CubeMX Tool and

+                                     the helper macro @ref __LL_I2C_CONVERT_TIMINGS()

+

+                                     This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */

+

+  uint32_t AnalogFilter;        /*!< Enables or disables analog noise filter.

+                                     This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION

+

+                                     This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */

+

+  uint32_t DigitalFilter;       /*!< Configures the digital noise filter.

+                                     This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F

+

+                                     This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */

+

+  uint32_t OwnAddress1;         /*!< Specifies the device own address 1.

+                                     This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF

+

+                                     This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */

+

+  uint32_t TypeAcknowledge;     /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.

+                                     This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE

+

+                                     This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */

+

+  uint32_t OwnAddrSize;         /*!< Specifies the device own address 1 size (7-bit or 10-bit).

+                                     This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1

+

+                                     This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */

+} LL_I2C_InitTypeDef;

+/**

+  * @}

+  */

+#endif /*USE_FULL_LL_DRIVER*/

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants

+  * @{

+  */

+

+/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines

+  * @brief    Flags defines which can be used with LL_I2C_WriteReg function

+  * @{

+  */

+#define LL_I2C_ICR_ADDRCF                   I2C_ICR_ADDRCF          /*!< Address Matched flag   */

+#define LL_I2C_ICR_NACKCF                   I2C_ICR_NACKCF          /*!< Not Acknowledge flag   */

+#define LL_I2C_ICR_STOPCF                   I2C_ICR_STOPCF          /*!< Stop detection flag    */

+#define LL_I2C_ICR_BERRCF                   I2C_ICR_BERRCF          /*!< Bus error flag         */

+#define LL_I2C_ICR_ARLOCF                   I2C_ICR_ARLOCF          /*!< Arbitration Lost flag  */

+#define LL_I2C_ICR_OVRCF                    I2C_ICR_OVRCF           /*!< Overrun/Underrun flag  */

+#define LL_I2C_ICR_PECCF                    I2C_ICR_PECCF           /*!< PEC error flag         */

+#define LL_I2C_ICR_TIMOUTCF                 I2C_ICR_TIMOUTCF        /*!< Timeout detection flag */

+#define LL_I2C_ICR_ALERTCF                  I2C_ICR_ALERTCF         /*!< Alert flag             */

+/**

+  * @}

+  */

+

+/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines

+  * @brief    Flags defines which can be used with LL_I2C_ReadReg function

+  * @{

+  */

+#define LL_I2C_ISR_TXE                      I2C_ISR_TXE             /*!< Transmit data register empty        */

+#define LL_I2C_ISR_TXIS                     I2C_ISR_TXIS            /*!< Transmit interrupt status           */

+#define LL_I2C_ISR_RXNE                     I2C_ISR_RXNE            /*!< Receive data register not empty     */

+#define LL_I2C_ISR_ADDR                     I2C_ISR_ADDR            /*!< Address matched (slave mode)        */

+#define LL_I2C_ISR_NACKF                    I2C_ISR_NACKF           /*!< Not Acknowledge received flag       */

+#define LL_I2C_ISR_STOPF                    I2C_ISR_STOPF           /*!< Stop detection flag                 */

+#define LL_I2C_ISR_TC                       I2C_ISR_TC              /*!< Transfer Complete (master mode)     */

+#define LL_I2C_ISR_TCR                      I2C_ISR_TCR             /*!< Transfer Complete Reload            */

+#define LL_I2C_ISR_BERR                     I2C_ISR_BERR            /*!< Bus error                           */

+#define LL_I2C_ISR_ARLO                     I2C_ISR_ARLO            /*!< Arbitration lost                    */

+#define LL_I2C_ISR_OVR                      I2C_ISR_OVR             /*!< Overrun/Underrun (slave mode)       */

+#define LL_I2C_ISR_PECERR                   I2C_ISR_PECERR          /*!< PEC Error in reception (SMBus mode) */

+#define LL_I2C_ISR_TIMEOUT                  I2C_ISR_TIMEOUT         /*!< Timeout detection flag (SMBus mode) */

+#define LL_I2C_ISR_ALERT                    I2C_ISR_ALERT           /*!< SMBus alert (SMBus mode)            */

+#define LL_I2C_ISR_BUSY                     I2C_ISR_BUSY            /*!< Bus busy                            */

+/**

+  * @}

+  */

+

+/** @defgroup I2C_LL_EC_IT IT Defines

+  * @brief    IT defines which can be used with LL_I2C_ReadReg and  LL_I2C_WriteReg functions

+  * @{

+  */

+#define LL_I2C_CR1_TXIE                     I2C_CR1_TXIE            /*!< TX Interrupt enable                         */

+#define LL_I2C_CR1_RXIE                     I2C_CR1_RXIE            /*!< RX Interrupt enable                         */

+#define LL_I2C_CR1_ADDRIE                   I2C_CR1_ADDRIE          /*!< Address match Interrupt enable (slave only) */

+#define LL_I2C_CR1_NACKIE                   I2C_CR1_NACKIE          /*!< Not acknowledge received Interrupt enable   */

+#define LL_I2C_CR1_STOPIE                   I2C_CR1_STOPIE          /*!< STOP detection Interrupt enable             */

+#define LL_I2C_CR1_TCIE                     I2C_CR1_TCIE            /*!< Transfer Complete interrupt enable          */

+#define LL_I2C_CR1_ERRIE                    I2C_CR1_ERRIE           /*!< Error interrupts enable                     */

+/**

+  * @}

+  */

+

+/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode

+  * @{

+  */

+#define LL_I2C_MODE_I2C                    0x00000000U              /*!< I2C Master or Slave mode                                    */

+#define LL_I2C_MODE_SMBUS_HOST             I2C_CR1_SMBHEN           /*!< SMBus Host address acknowledge                              */

+#define LL_I2C_MODE_SMBUS_DEVICE           0x00000000U              /*!< SMBus Device default mode (Default address not acknowledge) */

+#define LL_I2C_MODE_SMBUS_DEVICE_ARP       I2C_CR1_SMBDEN           /*!< SMBus Device Default address acknowledge                    */

+/**

+  * @}

+  */

+

+/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection

+  * @{

+  */

+#define LL_I2C_ANALOGFILTER_ENABLE          0x00000000U             /*!< Analog filter is enabled.  */

+#define LL_I2C_ANALOGFILTER_DISABLE         I2C_CR1_ANFOFF          /*!< Analog filter is disabled. */

+/**

+  * @}

+  */

+

+/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode

+  * @{

+  */

+#define LL_I2C_ADDRESSING_MODE_7BIT         0x00000000U              /*!< Master operates in 7-bit addressing mode. */

+#define LL_I2C_ADDRESSING_MODE_10BIT        I2C_CR2_ADD10            /*!< Master operates in 10-bit addressing mode.*/

+/**

+  * @}

+  */

+

+/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length

+  * @{

+  */

+#define LL_I2C_OWNADDRESS1_7BIT             0x00000000U             /*!< Own address 1 is a 7-bit address. */

+#define LL_I2C_OWNADDRESS1_10BIT            I2C_OAR1_OA1MODE        /*!< Own address 1 is a 10-bit address.*/

+/**

+  * @}

+  */

+

+/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks

+  * @{

+  */

+#define LL_I2C_OWNADDRESS2_NOMASK           I2C_OAR2_OA2NOMASK      /*!< Own Address2 No mask.                                */

+#define LL_I2C_OWNADDRESS2_MASK01           I2C_OAR2_OA2MASK01      /*!< Only Address2 bits[7:2] are compared.                */

+#define LL_I2C_OWNADDRESS2_MASK02           I2C_OAR2_OA2MASK02      /*!< Only Address2 bits[7:3] are compared.                */

+#define LL_I2C_OWNADDRESS2_MASK03           I2C_OAR2_OA2MASK03      /*!< Only Address2 bits[7:4] are compared.                */

+#define LL_I2C_OWNADDRESS2_MASK04           I2C_OAR2_OA2MASK04      /*!< Only Address2 bits[7:5] are compared.                */

+#define LL_I2C_OWNADDRESS2_MASK05           I2C_OAR2_OA2MASK05      /*!< Only Address2 bits[7:6] are compared.                */

+#define LL_I2C_OWNADDRESS2_MASK06           I2C_OAR2_OA2MASK06      /*!< Only Address2 bits[7] are compared.                  */

+#define LL_I2C_OWNADDRESS2_MASK07           I2C_OAR2_OA2MASK07      /*!< No comparison is done. All Address2 are acknowledged.*/

+/**

+  * @}

+  */

+

+/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation

+  * @{

+  */

+#define LL_I2C_ACK                          0x00000000U              /*!< ACK is sent after current received byte. */

+#define LL_I2C_NACK                         I2C_CR2_NACK             /*!< NACK is sent after current received byte.*/

+/**

+  * @}

+  */

+

+/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length

+  * @{

+  */

+#define LL_I2C_ADDRSLAVE_7BIT               0x00000000U              /*!< Slave Address in 7-bit. */

+#define LL_I2C_ADDRSLAVE_10BIT              I2C_CR2_ADD10            /*!< Slave Address in 10-bit.*/

+/**

+  * @}

+  */

+

+/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction

+  * @{

+  */

+#define LL_I2C_REQUEST_WRITE                0x00000000U              /*!< Master request a write transfer. */

+#define LL_I2C_REQUEST_READ                 I2C_CR2_RD_WRN           /*!< Master request a read transfer.  */

+/**

+  * @}

+  */

+

+/** @defgroup I2C_LL_EC_MODE Transfer End Mode

+  * @{

+  */

+#define LL_I2C_MODE_RELOAD                  I2C_CR2_RELOAD                                      /*!< Enable I2C Reload mode.                                   */

+#define LL_I2C_MODE_AUTOEND                 I2C_CR2_AUTOEND                                     /*!< Enable I2C Automatic end mode with no HW PEC comparison.  */

+#define LL_I2C_MODE_SOFTEND                 0x00000000U                                         /*!< Enable I2C Software end mode with no HW PEC comparison.   */

+#define LL_I2C_MODE_SMBUS_RELOAD            LL_I2C_MODE_RELOAD                                  /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */

+#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC    LL_I2C_MODE_AUTOEND                                 /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */

+#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC    LL_I2C_MODE_SOFTEND                                 /*!< Enable SMBUS Software end mode with HW PEC comparison.    */

+#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE)   /*!< Enable SMBUS Automatic end mode with HW PEC comparison.   */

+#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC  (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE)   /*!< Enable SMBUS Software end mode with HW PEC comparison.    */

+/**

+  * @}

+  */

+

+/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation

+  * @{

+  */

+#define LL_I2C_GENERATE_NOSTARTSTOP         0x00000000U                                                                /*!< Don't Generate Stop and Start condition.                */

+#define LL_I2C_GENERATE_STOP                (uint32_t)(0x80000000U | I2C_CR2_STOP)                                     /*!< Generate Stop condition (Size should be set to 0).      */

+#define LL_I2C_GENERATE_START_READ          (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)                   /*!< Generate Start for read request.                        */

+#define LL_I2C_GENERATE_START_WRITE         (uint32_t)(0x80000000U | I2C_CR2_START)                                    /*!< Generate Start for write request.                       */

+#define LL_I2C_GENERATE_RESTART_7BIT_READ   (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)                   /*!< Generate Restart for read request, slave 7Bit address.  */

+#define LL_I2C_GENERATE_RESTART_7BIT_WRITE  (uint32_t)(0x80000000U | I2C_CR2_START)                                    /*!< Generate Restart for write request, slave 7Bit address. */

+#define LL_I2C_GENERATE_RESTART_10BIT_READ  (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */

+#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)                                    /*!< Generate Restart for write request, slave 10Bit address.*/

+/**

+  * @}

+  */

+

+/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction

+  * @{

+  */

+#define LL_I2C_DIRECTION_WRITE              0x00000000U              /*!< Write transfer request by master, slave enters receiver mode.  */

+#define LL_I2C_DIRECTION_READ               I2C_ISR_DIR              /*!< Read transfer request by master, slave enters transmitter mode.*/

+/**

+  * @}

+  */

+

+/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data

+  * @{

+  */

+#define LL_I2C_DMA_REG_DATA_TRANSMIT        0x00000000U              /*!< Get address of data register used for transmission */

+#define LL_I2C_DMA_REG_DATA_RECEIVE         0x00000001U              /*!< Get address of data register used for reception */

+/**

+  * @}

+  */

+

+/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout

+  * @{

+  */

+#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW      0x00000000U          /*!< TimeoutA is used to detect SCL low level timeout.              */

+#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE   /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/

+/**

+  * @}

+  */

+

+/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection

+  * @{

+  */

+#define LL_I2C_SMBUS_TIMEOUTA               I2C_TIMEOUTR_TIMOUTEN                                   /*!< TimeoutA enable bit                                */

+#define LL_I2C_SMBUS_TIMEOUTB               I2C_TIMEOUTR_TEXTEN                                     /*!< TimeoutB (extended clock) enable bit               */

+#define LL_I2C_SMBUS_ALL_TIMEOUT            (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros

+  * @{

+  */

+

+/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros

+  * @{

+  */

+

+/**

+  * @brief  Write a value in I2C register

+  * @param  __INSTANCE__ I2C Instance

+  * @param  __REG__ Register to be written

+  * @param  __VALUE__ Value to be written in the register

+  * @retval None

+  */

+#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

+

+/**

+  * @brief  Read a value in I2C register

+  * @param  __INSTANCE__ I2C Instance

+  * @param  __REG__ Register to be read

+  * @retval Register value

+  */

+#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)

+/**

+  * @}

+  */

+

+/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings

+  * @{

+  */

+/**

+  * @brief  Configure the SDA setup, hold time and the SCL high, low period.

+  * @param  __PRESCALER__ This parameter must be a value between  Min_Data=0 and Max_Data=0xF.

+  * @param  __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)

+  * @param  __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)

+  * @param  __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)

+  * @param  __CLOCK_LOW_PERIOD__ This parameter must be a value between  Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)

+  * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF

+  */

+#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__)   \

+        ((((uint32_t)(__PRESCALER__)         << I2C_TIMINGR_PRESC_Pos)  & I2C_TIMINGR_PRESC)   | \

+         (((uint32_t)(__DATA_SETUP_TIME__)   << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL)  | \

+         (((uint32_t)(__DATA_HOLD_TIME__)    << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL)  | \

+         (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos)   & I2C_TIMINGR_SCLH)    | \

+         (((uint32_t)(__CLOCK_LOW_PERIOD__)  << I2C_TIMINGR_SCLL_Pos)   & I2C_TIMINGR_SCLL))

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions

+  * @{

+  */

+

+/** @defgroup I2C_LL_EF_Configuration Configuration

+  * @{

+  */

+

+/**

+  * @brief  Enable I2C peripheral (PE = 1).

+  * @rmtoll CR1          PE            LL_I2C_Enable

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->CR1, I2C_CR1_PE);

+}

+

+/**

+  * @brief  Disable I2C peripheral (PE = 0).

+  * @note   When PE = 0, the I2C SCL and SDA lines are released.

+  *         Internal state machines and status bits are put back to their reset value.

+  *         When cleared, PE must be kept low for at least 3 APB clock cycles.

+  * @rmtoll CR1          PE            LL_I2C_Disable

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)

+{

+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);

+}

+

+/**

+  * @brief  Check if the I2C peripheral is enabled or disabled.

+  * @rmtoll CR1          PE            LL_I2C_IsEnabled

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Configure Noise Filters (Analog and Digital).

+  * @note   If the analog filter is also enabled, the digital filter is added to analog filter.

+  *         The filters can only be programmed when the I2C is disabled (PE = 0).

+  * @rmtoll CR1          ANFOFF        LL_I2C_ConfigFilters\n

+  *         CR1          DNF           LL_I2C_ConfigFilters

+  * @param  I2Cx I2C Instance.

+  * @param  AnalogFilter This parameter can be one of the following values:

+  *         @arg @ref LL_I2C_ANALOGFILTER_ENABLE

+  *         @arg @ref LL_I2C_ANALOGFILTER_DISABLE

+  * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).

+  *         This parameter is used to configure the digital noise filter on SDA and SCL input.

+  *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)

+{

+  MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));

+}

+

+/**

+  * @brief  Configure Digital Noise Filter.

+  * @note   If the analog filter is also enabled, the digital filter is added to analog filter.

+  *         This filter can only be programmed when the I2C is disabled (PE = 0).

+  * @rmtoll CR1          DNF           LL_I2C_SetDigitalFilter

+  * @param  I2Cx I2C Instance.

+  * @param  DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).

+  *         This parameter is used to configure the digital noise filter on SDA and SCL input.

+  *         The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)

+{

+  MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);

+}

+

+/**

+  * @brief  Get the current Digital Noise Filter configuration.

+  * @rmtoll CR1          DNF           LL_I2C_GetDigitalFilter

+  * @param  I2Cx I2C Instance.

+  * @retval Value between Min_Data=0x0 and Max_Data=0xF

+  */

+__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)

+{

+  return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);

+}

+

+/**

+  * @brief  Enable Analog Noise Filter.

+  * @note   This filter can only be programmed when the I2C is disabled (PE = 0).

+  * @rmtoll CR1          ANFOFF        LL_I2C_EnableAnalogFilter

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)

+{

+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);

+}

+

+/**

+  * @brief  Disable Analog Noise Filter.

+  * @note   This filter can only be programmed when the I2C is disabled (PE = 0).

+  * @rmtoll CR1          ANFOFF        LL_I2C_DisableAnalogFilter

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);

+}

+

+/**

+  * @brief  Check if Analog Noise Filter is enabled or disabled.

+  * @rmtoll CR1          ANFOFF        LL_I2C_IsEnabledAnalogFilter

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable DMA transmission requests.

+  * @rmtoll CR1          TXDMAEN       LL_I2C_EnableDMAReq_TX

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);

+}

+

+/**

+  * @brief  Disable DMA transmission requests.

+  * @rmtoll CR1          TXDMAEN       LL_I2C_DisableDMAReq_TX

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)

+{

+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);

+}

+

+/**

+  * @brief  Check if DMA transmission requests are enabled or disabled.

+  * @rmtoll CR1          TXDMAEN       LL_I2C_IsEnabledDMAReq_TX

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable DMA reception requests.

+  * @rmtoll CR1          RXDMAEN       LL_I2C_EnableDMAReq_RX

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);

+}

+

+/**

+  * @brief  Disable DMA reception requests.

+  * @rmtoll CR1          RXDMAEN       LL_I2C_DisableDMAReq_RX

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)

+{

+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);

+}

+

+/**

+  * @brief  Check if DMA reception requests are enabled or disabled.

+  * @rmtoll CR1          RXDMAEN       LL_I2C_IsEnabledDMAReq_RX

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get the data register address used for DMA transfer

+  * @rmtoll TXDR         TXDATA        LL_I2C_DMA_GetRegAddr\n

+  *         RXDR         RXDATA        LL_I2C_DMA_GetRegAddr

+  * @param  I2Cx I2C Instance

+  * @param  Direction This parameter can be one of the following values:

+  *         @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT

+  *         @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE

+  * @retval Address of data register

+  */

+__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)

+{

+  register uint32_t data_reg_addr;

+

+  if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)

+  {

+    /* return address of TXDR register */

+    data_reg_addr = (uint32_t) & (I2Cx->TXDR);

+  }

+  else

+  {

+    /* return address of RXDR register */

+    data_reg_addr = (uint32_t) & (I2Cx->RXDR);

+  }

+

+  return data_reg_addr;

+}

+

+/**

+  * @brief  Enable Clock stretching.

+  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).

+  * @rmtoll CR1          NOSTRETCH     LL_I2C_EnableClockStretching

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)

+{

+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);

+}

+

+/**

+  * @brief  Disable Clock stretching.

+  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).

+  * @rmtoll CR1          NOSTRETCH     LL_I2C_DisableClockStretching

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);

+}

+

+/**

+  * @brief  Check if Clock stretching is enabled or disabled.

+  * @rmtoll CR1          NOSTRETCH     LL_I2C_IsEnabledClockStretching

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable hardware byte control in slave mode.

+  * @rmtoll CR1          SBC           LL_I2C_EnableSlaveByteControl

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->CR1, I2C_CR1_SBC);

+}

+

+/**

+  * @brief  Disable hardware byte control in slave mode.

+  * @rmtoll CR1          SBC           LL_I2C_DisableSlaveByteControl

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)

+{

+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);

+}

+

+/**

+  * @brief  Check if hardware byte control in slave mode is enabled or disabled.

+  * @rmtoll CR1          SBC           LL_I2C_IsEnabledSlaveByteControl

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable Wakeup from STOP.

+  * @note   Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not

+  *         WakeUpFromStop feature is supported by the I2Cx Instance.

+  * @note   This bit can only be programmed when Digital Filter is disabled.

+  * @rmtoll CR1          WUPEN         LL_I2C_EnableWakeUpFromStop

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN);

+}

+

+/**

+  * @brief  Disable Wakeup from STOP.

+  * @note   Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not

+  *         WakeUpFromStop feature is supported by the I2Cx Instance.

+  * @rmtoll CR1          WUPEN         LL_I2C_DisableWakeUpFromStop

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)

+{

+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN);

+}

+

+/**

+  * @brief  Check if Wakeup from STOP is enabled or disabled.

+  * @note   Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not

+  *         WakeUpFromStop feature is supported by the I2Cx Instance.

+  * @rmtoll CR1          WUPEN         LL_I2C_IsEnabledWakeUpFromStop

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable General Call.

+  * @note   When enabled the Address 0x00 is ACKed.

+  * @rmtoll CR1          GCEN          LL_I2C_EnableGeneralCall

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);

+}

+

+/**

+  * @brief  Disable General Call.

+  * @note   When disabled the Address 0x00 is NACKed.

+  * @rmtoll CR1          GCEN          LL_I2C_DisableGeneralCall

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)

+{

+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);

+}

+

+/**

+  * @brief  Check if General Call is enabled or disabled.

+  * @rmtoll CR1          GCEN          LL_I2C_IsEnabledGeneralCall

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Configure the Master to operate in 7-bit or 10-bit addressing mode.

+  * @note   Changing this bit is not allowed, when the START bit is set.

+  * @rmtoll CR2          ADD10         LL_I2C_SetMasterAddressingMode

+  * @param  I2Cx I2C Instance.

+  * @param  AddressingMode This parameter can be one of the following values:

+  *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT

+  *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)

+{

+  MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);

+}

+

+/**

+  * @brief  Get the Master addressing mode.

+  * @rmtoll CR2          ADD10         LL_I2C_GetMasterAddressingMode

+  * @param  I2Cx I2C Instance.

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_I2C_ADDRESSING_MODE_7BIT

+  *         @arg @ref LL_I2C_ADDRESSING_MODE_10BIT

+  */

+__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)

+{

+  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));

+}

+

+/**

+  * @brief  Set the Own Address1.

+  * @rmtoll OAR1         OA1           LL_I2C_SetOwnAddress1\n

+  *         OAR1         OA1MODE       LL_I2C_SetOwnAddress1

+  * @param  I2Cx I2C Instance.

+  * @param  OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.

+  * @param  OwnAddrSize This parameter can be one of the following values:

+  *         @arg @ref LL_I2C_OWNADDRESS1_7BIT

+  *         @arg @ref LL_I2C_OWNADDRESS1_10BIT

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)

+{

+  MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);

+}

+

+/**

+  * @brief  Enable acknowledge on Own Address1 match address.

+  * @rmtoll OAR1         OA1EN         LL_I2C_EnableOwnAddress1

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);

+}

+

+/**

+  * @brief  Disable acknowledge on Own Address1 match address.

+  * @rmtoll OAR1         OA1EN         LL_I2C_DisableOwnAddress1

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)

+{

+  CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);

+}

+

+/**

+  * @brief  Check if Own Address1 acknowledge is enabled or disabled.

+  * @rmtoll OAR1         OA1EN         LL_I2C_IsEnabledOwnAddress1

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set the 7bits Own Address2.

+  * @note   This action has no effect if own address2 is enabled.

+  * @rmtoll OAR2         OA2           LL_I2C_SetOwnAddress2\n

+  *         OAR2         OA2MSK        LL_I2C_SetOwnAddress2

+  * @param  I2Cx I2C Instance.

+  * @param  OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.

+  * @param  OwnAddrMask This parameter can be one of the following values:

+  *         @arg @ref LL_I2C_OWNADDRESS2_NOMASK

+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK01

+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK02

+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK03

+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK04

+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK05

+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK06

+  *         @arg @ref LL_I2C_OWNADDRESS2_MASK07

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)

+{

+  MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);

+}

+

+/**

+  * @brief  Enable acknowledge on Own Address2 match address.

+  * @rmtoll OAR2         OA2EN         LL_I2C_EnableOwnAddress2

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);

+}

+

+/**

+  * @brief  Disable  acknowledge on Own Address2 match address.

+  * @rmtoll OAR2         OA2EN         LL_I2C_DisableOwnAddress2

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)

+{

+  CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);

+}

+

+/**

+  * @brief  Check if Own Address1 acknowledge is enabled or disabled.

+  * @rmtoll OAR2         OA2EN         LL_I2C_IsEnabledOwnAddress2

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Configure the SDA setup, hold time and the SCL high, low period.

+  * @note   This bit can only be programmed when the I2C is disabled (PE = 0).

+  * @rmtoll TIMINGR      TIMINGR       LL_I2C_SetTiming

+  * @param  I2Cx I2C Instance.

+  * @param  Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.

+  * @note   This parameter is computed with the STM32CubeMX Tool.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)

+{

+  WRITE_REG(I2Cx->TIMINGR, Timing);

+}

+

+/**

+  * @brief  Get the Timing Prescaler setting.

+  * @rmtoll TIMINGR      PRESC         LL_I2C_GetTimingPrescaler

+  * @param  I2Cx I2C Instance.

+  * @retval Value between Min_Data=0x0 and Max_Data=0xF

+  */

+__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)

+{

+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);

+}

+

+/**

+  * @brief  Get the SCL low period setting.

+  * @rmtoll TIMINGR      SCLL          LL_I2C_GetClockLowPeriod

+  * @param  I2Cx I2C Instance.

+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF

+  */

+__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)

+{

+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);

+}

+

+/**

+  * @brief  Get the SCL high period setting.

+  * @rmtoll TIMINGR      SCLH          LL_I2C_GetClockHighPeriod

+  * @param  I2Cx I2C Instance.

+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF

+  */

+__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)

+{

+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);

+}

+

+/**

+  * @brief  Get the SDA hold time.

+  * @rmtoll TIMINGR      SDADEL        LL_I2C_GetDataHoldTime

+  * @param  I2Cx I2C Instance.

+  * @retval Value between Min_Data=0x0 and Max_Data=0xF

+  */

+__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)

+{

+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);

+}

+

+/**

+  * @brief  Get the SDA setup time.

+  * @rmtoll TIMINGR      SCLDEL        LL_I2C_GetDataSetupTime

+  * @param  I2Cx I2C Instance.

+  * @retval Value between Min_Data=0x0 and Max_Data=0xF

+  */

+__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)

+{

+  return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);

+}

+

+/**

+  * @brief  Configure peripheral mode.

+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not

+  *         SMBus feature is supported by the I2Cx Instance.

+  * @rmtoll CR1          SMBHEN        LL_I2C_SetMode\n

+  *         CR1          SMBDEN        LL_I2C_SetMode

+  * @param  I2Cx I2C Instance.

+  * @param  PeripheralMode This parameter can be one of the following values:

+  *         @arg @ref LL_I2C_MODE_I2C

+  *         @arg @ref LL_I2C_MODE_SMBUS_HOST

+  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE

+  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)

+{

+  MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);

+}

+

+/**

+  * @brief  Get peripheral mode.

+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not

+  *         SMBus feature is supported by the I2Cx Instance.

+  * @rmtoll CR1          SMBHEN        LL_I2C_GetMode\n

+  *         CR1          SMBDEN        LL_I2C_GetMode

+  * @param  I2Cx I2C Instance.

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_I2C_MODE_I2C

+  *         @arg @ref LL_I2C_MODE_SMBUS_HOST

+  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE

+  *         @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP

+  */

+__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)

+{

+  return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));

+}

+

+/**

+  * @brief  Enable SMBus alert (Host or Device mode)

+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not

+  *         SMBus feature is supported by the I2Cx Instance.

+  * @note   SMBus Device mode:

+  *         - SMBus Alert pin is drived low and

+  *           Alert Response Address Header acknowledge is enabled.

+  *         SMBus Host mode:

+  *         - SMBus Alert pin management is supported.

+  * @rmtoll CR1          ALERTEN       LL_I2C_EnableSMBusAlert

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);

+}

+

+/**

+  * @brief  Disable SMBus alert (Host or Device mode)

+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not

+  *         SMBus feature is supported by the I2Cx Instance.

+  * @note   SMBus Device mode:

+  *         - SMBus Alert pin is not drived (can be used as a standard GPIO) and

+  *           Alert Response Address Header acknowledge is disabled.

+  *         SMBus Host mode:

+  *         - SMBus Alert pin management is not supported.

+  * @rmtoll CR1          ALERTEN       LL_I2C_DisableSMBusAlert

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)

+{

+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);

+}

+

+/**

+  * @brief  Check if SMBus alert (Host or Device mode) is enabled or disabled.

+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not

+  *         SMBus feature is supported by the I2Cx Instance.

+  * @rmtoll CR1          ALERTEN       LL_I2C_IsEnabledSMBusAlert

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable SMBus Packet Error Calculation (PEC).

+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not

+  *         SMBus feature is supported by the I2Cx Instance.

+  * @rmtoll CR1          PECEN         LL_I2C_EnableSMBusPEC

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);

+}

+

+/**

+  * @brief  Disable SMBus Packet Error Calculation (PEC).

+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not

+  *         SMBus feature is supported by the I2Cx Instance.

+  * @rmtoll CR1          PECEN         LL_I2C_DisableSMBusPEC

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)

+{

+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);

+}

+

+/**

+  * @brief  Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.

+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not

+  *         SMBus feature is supported by the I2Cx Instance.

+  * @rmtoll CR1          PECEN         LL_I2C_IsEnabledSMBusPEC

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Configure the SMBus Clock Timeout.

+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not

+  *         SMBus feature is supported by the I2Cx Instance.

+  * @note   This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).

+  * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_ConfigSMBusTimeout\n

+  *         TIMEOUTR     TIDLE         LL_I2C_ConfigSMBusTimeout\n

+  *         TIMEOUTR     TIMEOUTB      LL_I2C_ConfigSMBusTimeout

+  * @param  I2Cx I2C Instance.

+  * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.

+  * @param  TimeoutAMode This parameter can be one of the following values:

+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW

+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH

+  * @param  TimeoutB

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,

+                                               uint32_t TimeoutB)

+{

+  MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,

+             TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));

+}

+

+/**

+  * @brief  Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).

+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not

+  *         SMBus feature is supported by the I2Cx Instance.

+  * @note   These bits can only be programmed when TimeoutA is disabled.

+  * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_SetSMBusTimeoutA

+  * @param  I2Cx I2C Instance.

+  * @param  TimeoutA This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)

+{

+  WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);

+}

+

+/**

+  * @brief  Get the SMBus Clock TimeoutA setting.

+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not

+  *         SMBus feature is supported by the I2Cx Instance.

+  * @rmtoll TIMEOUTR     TIMEOUTA      LL_I2C_GetSMBusTimeoutA

+  * @param  I2Cx I2C Instance.

+  * @retval Value between Min_Data=0 and Max_Data=0xFFF

+  */

+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)

+{

+  return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));

+}

+

+/**

+  * @brief  Set the SMBus Clock TimeoutA mode.

+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not

+  *         SMBus feature is supported by the I2Cx Instance.

+  * @note   This bit can only be programmed when TimeoutA is disabled.

+  * @rmtoll TIMEOUTR     TIDLE         LL_I2C_SetSMBusTimeoutAMode

+  * @param  I2Cx I2C Instance.

+  * @param  TimeoutAMode This parameter can be one of the following values:

+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW

+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)

+{

+  WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);

+}

+

+/**

+  * @brief  Get the SMBus Clock TimeoutA mode.

+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not

+  *         SMBus feature is supported by the I2Cx Instance.

+  * @rmtoll TIMEOUTR     TIDLE         LL_I2C_GetSMBusTimeoutAMode

+  * @param  I2Cx I2C Instance.

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW

+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH

+  */

+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)

+{

+  return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));

+}

+

+/**

+  * @brief  Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).

+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not

+  *         SMBus feature is supported by the I2Cx Instance.

+  * @note   These bits can only be programmed when TimeoutB is disabled.

+  * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_SetSMBusTimeoutB

+  * @param  I2Cx I2C Instance.

+  * @param  TimeoutB This parameter must be a value between  Min_Data=0 and Max_Data=0xFFF.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)

+{

+  WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);

+}

+

+/**

+  * @brief  Get the SMBus Extented Cumulative Clock TimeoutB setting.

+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not

+  *         SMBus feature is supported by the I2Cx Instance.

+  * @rmtoll TIMEOUTR     TIMEOUTB      LL_I2C_GetSMBusTimeoutB

+  * @param  I2Cx I2C Instance.

+  * @retval Value between Min_Data=0 and Max_Data=0xFFF

+  */

+__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)

+{

+  return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);

+}

+

+/**

+  * @brief  Enable the SMBus Clock Timeout.

+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not

+  *         SMBus feature is supported by the I2Cx Instance.

+  * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_EnableSMBusTimeout\n

+  *         TIMEOUTR     TEXTEN        LL_I2C_EnableSMBusTimeout

+  * @param  I2Cx I2C Instance.

+  * @param  ClockTimeout This parameter can be one of the following values:

+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA

+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTB

+  *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)

+{

+  SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);

+}

+

+/**

+  * @brief  Disable the SMBus Clock Timeout.

+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not

+  *         SMBus feature is supported by the I2Cx Instance.

+  * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_DisableSMBusTimeout\n

+  *         TIMEOUTR     TEXTEN        LL_I2C_DisableSMBusTimeout

+  * @param  I2Cx I2C Instance.

+  * @param  ClockTimeout This parameter can be one of the following values:

+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA

+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTB

+  *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)

+{

+  CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);

+}

+

+/**

+  * @brief  Check if the SMBus Clock Timeout is enabled or disabled.

+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not

+  *         SMBus feature is supported by the I2Cx Instance.

+  * @rmtoll TIMEOUTR     TIMOUTEN      LL_I2C_IsEnabledSMBusTimeout\n

+  *         TIMEOUTR     TEXTEN        LL_I2C_IsEnabledSMBusTimeout

+  * @param  I2Cx I2C Instance.

+  * @param  ClockTimeout This parameter can be one of the following values:

+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTA

+  *         @arg @ref LL_I2C_SMBUS_TIMEOUTB

+  *         @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)

+{

+  return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout)) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup I2C_LL_EF_IT_Management IT_Management

+  * @{

+  */

+

+/**

+  * @brief  Enable TXIS interrupt.

+  * @rmtoll CR1          TXIE          LL_I2C_EnableIT_TX

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);

+}

+

+/**

+  * @brief  Disable TXIS interrupt.

+  * @rmtoll CR1          TXIE          LL_I2C_DisableIT_TX

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)

+{

+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);

+}

+

+/**

+  * @brief  Check if the TXIS Interrupt is enabled or disabled.

+  * @rmtoll CR1          TXIE          LL_I2C_IsEnabledIT_TX

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable RXNE interrupt.

+  * @rmtoll CR1          RXIE          LL_I2C_EnableIT_RX

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);

+}

+

+/**

+  * @brief  Disable RXNE interrupt.

+  * @rmtoll CR1          RXIE          LL_I2C_DisableIT_RX

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)

+{

+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);

+}

+

+/**

+  * @brief  Check if the RXNE Interrupt is enabled or disabled.

+  * @rmtoll CR1          RXIE          LL_I2C_IsEnabledIT_RX

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable Address match interrupt (slave mode only).

+  * @rmtoll CR1          ADDRIE        LL_I2C_EnableIT_ADDR

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);

+}

+

+/**

+  * @brief  Disable Address match interrupt (slave mode only).

+  * @rmtoll CR1          ADDRIE        LL_I2C_DisableIT_ADDR

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)

+{

+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);

+}

+

+/**

+  * @brief  Check if Address match interrupt is enabled or disabled.

+  * @rmtoll CR1          ADDRIE        LL_I2C_IsEnabledIT_ADDR

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable Not acknowledge received interrupt.

+  * @rmtoll CR1          NACKIE        LL_I2C_EnableIT_NACK

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);

+}

+

+/**

+  * @brief  Disable Not acknowledge received interrupt.

+  * @rmtoll CR1          NACKIE        LL_I2C_DisableIT_NACK

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)

+{

+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);

+}

+

+/**

+  * @brief  Check if Not acknowledge received interrupt is enabled or disabled.

+  * @rmtoll CR1          NACKIE        LL_I2C_IsEnabledIT_NACK

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable STOP detection interrupt.

+  * @rmtoll CR1          STOPIE        LL_I2C_EnableIT_STOP

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);

+}

+

+/**

+  * @brief  Disable STOP detection interrupt.

+  * @rmtoll CR1          STOPIE        LL_I2C_DisableIT_STOP

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)

+{

+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);

+}

+

+/**

+  * @brief  Check if STOP detection interrupt is enabled or disabled.

+  * @rmtoll CR1          STOPIE        LL_I2C_IsEnabledIT_STOP

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable Transfer Complete interrupt.

+  * @note   Any of these events will generate interrupt :

+  *         Transfer Complete (TC)

+  *         Transfer Complete Reload (TCR)

+  * @rmtoll CR1          TCIE          LL_I2C_EnableIT_TC

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);

+}

+

+/**

+  * @brief  Disable Transfer Complete interrupt.

+  * @note   Any of these events will generate interrupt :

+  *         Transfer Complete (TC)

+  *         Transfer Complete Reload (TCR)

+  * @rmtoll CR1          TCIE          LL_I2C_DisableIT_TC

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)

+{

+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);

+}

+

+/**

+  * @brief  Check if Transfer Complete interrupt is enabled or disabled.

+  * @rmtoll CR1          TCIE          LL_I2C_IsEnabledIT_TC

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable Error interrupts.

+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not

+  *         SMBus feature is supported by the I2Cx Instance.

+  * @note   Any of these errors will generate interrupt :

+  *         Arbitration Loss (ARLO)

+  *         Bus Error detection (BERR)

+  *         Overrun/Underrun (OVR)

+  *         SMBus Timeout detection (TIMEOUT)

+  *         SMBus PEC error detection (PECERR)

+  *         SMBus Alert pin event detection (ALERT)

+  * @rmtoll CR1          ERRIE         LL_I2C_EnableIT_ERR

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);

+}

+

+/**

+  * @brief  Disable Error interrupts.

+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not

+  *         SMBus feature is supported by the I2Cx Instance.

+  * @note   Any of these errors will generate interrupt :

+  *         Arbitration Loss (ARLO)

+  *         Bus Error detection (BERR)

+  *         Overrun/Underrun (OVR)

+  *         SMBus Timeout detection (TIMEOUT)

+  *         SMBus PEC error detection (PECERR)

+  *         SMBus Alert pin event detection (ALERT)

+  * @rmtoll CR1          ERRIE         LL_I2C_DisableIT_ERR

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)

+{

+  CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);

+}

+

+/**

+  * @brief  Check if Error interrupts are enabled or disabled.

+  * @rmtoll CR1          ERRIE         LL_I2C_IsEnabledIT_ERR

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup I2C_LL_EF_FLAG_management FLAG_management

+  * @{

+  */

+

+/**

+  * @brief  Indicate the status of Transmit data register empty flag.

+  * @note   RESET: When next data is written in Transmit data register.

+  *         SET: When Transmit data register is empty.

+  * @rmtoll ISR          TXE           LL_I2C_IsActiveFlag_TXE

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicate the status of Transmit interrupt flag.

+  * @note   RESET: When next data is written in Transmit data register.

+  *         SET: When Transmit data register is empty.

+  * @rmtoll ISR          TXIS          LL_I2C_IsActiveFlag_TXIS

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicate the status of Receive data register not empty flag.

+  * @note   RESET: When Receive data register is read.

+  *         SET: When the received data is copied in Receive data register.

+  * @rmtoll ISR          RXNE          LL_I2C_IsActiveFlag_RXNE

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicate the status of Address matched flag (slave mode).

+  * @note   RESET: Clear default value.

+  *         SET: When the received slave address matched with one of the enabled slave address.

+  * @rmtoll ISR          ADDR          LL_I2C_IsActiveFlag_ADDR

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicate the status of Not Acknowledge received flag.

+  * @note   RESET: Clear default value.

+  *         SET: When a NACK is received after a byte transmission.

+  * @rmtoll ISR          NACKF         LL_I2C_IsActiveFlag_NACK

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicate the status of Stop detection flag.

+  * @note   RESET: Clear default value.

+  *         SET: When a Stop condition is detected.

+  * @rmtoll ISR          STOPF         LL_I2C_IsActiveFlag_STOP

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicate the status of Transfer complete flag (master mode).

+  * @note   RESET: Clear default value.

+  *         SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.

+  * @rmtoll ISR          TC            LL_I2C_IsActiveFlag_TC

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicate the status of Transfer complete flag (master mode).

+  * @note   RESET: Clear default value.

+  *         SET: When RELOAD=1 and NBYTES date have been transferred.

+  * @rmtoll ISR          TCR           LL_I2C_IsActiveFlag_TCR

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicate the status of Bus error flag.

+  * @note   RESET: Clear default value.

+  *         SET: When a misplaced Start or Stop condition is detected.

+  * @rmtoll ISR          BERR          LL_I2C_IsActiveFlag_BERR

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicate the status of Arbitration lost flag.

+  * @note   RESET: Clear default value.

+  *         SET: When arbitration lost.

+  * @rmtoll ISR          ARLO          LL_I2C_IsActiveFlag_ARLO

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicate the status of Overrun/Underrun flag (slave mode).

+  * @note   RESET: Clear default value.

+  *         SET: When an overrun/underrun error occurs (Clock Stretching Disabled).

+  * @rmtoll ISR          OVR           LL_I2C_IsActiveFlag_OVR

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicate the status of SMBus PEC error flag in reception.

+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not

+  *         SMBus feature is supported by the I2Cx Instance.

+  * @note   RESET: Clear default value.

+  *         SET: When the received PEC does not match with the PEC register content.

+  * @rmtoll ISR          PECERR        LL_I2C_IsActiveSMBusFlag_PECERR

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicate the status of SMBus Timeout detection flag.

+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not

+  *         SMBus feature is supported by the I2Cx Instance.

+  * @note   RESET: Clear default value.

+  *         SET: When a timeout or extended clock timeout occurs.

+  * @rmtoll ISR          TIMEOUT       LL_I2C_IsActiveSMBusFlag_TIMEOUT

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicate the status of SMBus alert flag.

+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not

+  *         SMBus feature is supported by the I2Cx Instance.

+  * @note   RESET: Clear default value.

+  *         SET: When SMBus host configuration, SMBus alert enabled and

+  *              a falling edge event occurs on SMBA pin.

+  * @rmtoll ISR          ALERT         LL_I2C_IsActiveSMBusFlag_ALERT

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicate the status of Bus Busy flag.

+  * @note   RESET: Clear default value.

+  *         SET: When a Start condition is detected.

+  * @rmtoll ISR          BUSY          LL_I2C_IsActiveFlag_BUSY

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear Address Matched flag.

+  * @rmtoll ICR          ADDRCF        LL_I2C_ClearFlag_ADDR

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);

+}

+

+/**

+  * @brief  Clear Not Acknowledge flag.

+  * @rmtoll ICR          NACKCF        LL_I2C_ClearFlag_NACK

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);

+}

+

+/**

+  * @brief  Clear Stop detection flag.

+  * @rmtoll ICR          STOPCF        LL_I2C_ClearFlag_STOP

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);

+}

+

+/**

+  * @brief  Clear Transmit data register empty flag (TXE).

+  * @note   This bit can be clear by software in order to flush the transmit data register (TXDR).

+  * @rmtoll ISR          TXE           LL_I2C_ClearFlag_TXE

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)

+{

+  WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);

+}

+

+/**

+  * @brief  Clear Bus error flag.

+  * @rmtoll ICR          BERRCF        LL_I2C_ClearFlag_BERR

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);

+}

+

+/**

+  * @brief  Clear Arbitration lost flag.

+  * @rmtoll ICR          ARLOCF        LL_I2C_ClearFlag_ARLO

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);

+}

+

+/**

+  * @brief  Clear Overrun/Underrun flag.

+  * @rmtoll ICR          OVRCF         LL_I2C_ClearFlag_OVR

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);

+}

+

+/**

+  * @brief  Clear SMBus PEC error flag.

+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not

+  *         SMBus feature is supported by the I2Cx Instance.

+  * @rmtoll ICR          PECCF         LL_I2C_ClearSMBusFlag_PECERR

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);

+}

+

+/**

+  * @brief  Clear SMBus Timeout detection flag.

+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not

+  *         SMBus feature is supported by the I2Cx Instance.

+  * @rmtoll ICR          TIMOUTCF      LL_I2C_ClearSMBusFlag_TIMEOUT

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);

+}

+

+/**

+  * @brief  Clear SMBus Alert flag.

+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not

+  *         SMBus feature is supported by the I2Cx Instance.

+  * @rmtoll ICR          ALERTCF       LL_I2C_ClearSMBusFlag_ALERT

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup I2C_LL_EF_Data_Management Data_Management

+  * @{

+  */

+

+/**

+  * @brief  Enable automatic STOP condition generation (master mode).

+  * @note   Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.

+  *         This bit has no effect in slave mode or when RELOAD bit is set.

+  * @rmtoll CR2          AUTOEND       LL_I2C_EnableAutoEndMode

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);

+}

+

+/**

+  * @brief  Disable automatic STOP condition generation (master mode).

+  * @note   Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.

+  * @rmtoll CR2          AUTOEND       LL_I2C_DisableAutoEndMode

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)

+{

+  CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);

+}

+

+/**

+  * @brief  Check if automatic STOP condition is enabled or disabled.

+  * @rmtoll CR2          AUTOEND       LL_I2C_IsEnabledAutoEndMode

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable reload mode (master mode).

+  * @note   The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.

+  * @rmtoll CR2          RELOAD       LL_I2C_EnableReloadMode

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);

+}

+

+/**

+  * @brief  Disable reload mode (master mode).

+  * @note   The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).

+  * @rmtoll CR2          RELOAD       LL_I2C_DisableReloadMode

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)

+{

+  CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);

+}

+

+/**

+  * @brief  Check if reload mode is enabled or disabled.

+  * @rmtoll CR2          RELOAD       LL_I2C_IsEnabledReloadMode

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Configure the number of bytes for transfer.

+  * @note   Changing these bits when START bit is set is not allowed.

+  * @rmtoll CR2          NBYTES           LL_I2C_SetTransferSize

+  * @param  I2Cx I2C Instance.

+  * @param  TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)

+{

+  MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);

+}

+

+/**

+  * @brief  Get the number of bytes configured for transfer.

+  * @rmtoll CR2          NBYTES           LL_I2C_GetTransferSize

+  * @param  I2Cx I2C Instance.

+  * @retval Value between Min_Data=0x0 and Max_Data=0xFF

+  */

+__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)

+{

+  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);

+}

+

+/**

+  * @brief  Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.

+  * @note   Usage in Slave mode only.

+  * @rmtoll CR2          NACK          LL_I2C_AcknowledgeNextData

+  * @param  I2Cx I2C Instance.

+  * @param  TypeAcknowledge This parameter can be one of the following values:

+  *         @arg @ref LL_I2C_ACK

+  *         @arg @ref LL_I2C_NACK

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)

+{

+  MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);

+}

+

+/**

+  * @brief  Generate a START or RESTART condition

+  * @note   The START bit can be set even if bus is BUSY or I2C is in slave mode.

+  *         This action has no effect when RELOAD is set.

+  * @rmtoll CR2          START           LL_I2C_GenerateStartCondition

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->CR2, I2C_CR2_START);

+}

+

+/**

+  * @brief  Generate a STOP condition after the current byte transfer (master mode).

+  * @rmtoll CR2          STOP          LL_I2C_GenerateStopCondition

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->CR2, I2C_CR2_STOP);

+}

+

+/**

+  * @brief  Enable automatic RESTART Read request condition for 10bit address header (master mode).

+  * @note   The master sends the complete 10bit slave address read sequence :

+  *         Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.

+  * @rmtoll CR2          HEAD10R       LL_I2C_EnableAuto10BitRead

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)

+{

+  CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);

+}

+

+/**

+  * @brief  Disable automatic RESTART Read request condition for 10bit address header (master mode).

+  * @note   The master only sends the first 7 bits of 10bit address in Read direction.

+  * @rmtoll CR2          HEAD10R       LL_I2C_DisableAuto10BitRead

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);

+}

+

+/**

+  * @brief  Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.

+  * @rmtoll CR2          HEAD10R       LL_I2C_IsEnabledAuto10BitRead

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Configure the transfer direction (master mode).

+  * @note   Changing these bits when START bit is set is not allowed.

+  * @rmtoll CR2          RD_WRN           LL_I2C_SetTransferRequest

+  * @param  I2Cx I2C Instance.

+  * @param  TransferRequest This parameter can be one of the following values:

+  *         @arg @ref LL_I2C_REQUEST_WRITE

+  *         @arg @ref LL_I2C_REQUEST_READ

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)

+{

+  MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);

+}

+

+/**

+  * @brief  Get the transfer direction requested (master mode).

+  * @rmtoll CR2          RD_WRN           LL_I2C_GetTransferRequest

+  * @param  I2Cx I2C Instance.

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_I2C_REQUEST_WRITE

+  *         @arg @ref LL_I2C_REQUEST_READ

+  */

+__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)

+{

+  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));

+}

+

+/**

+  * @brief  Configure the slave address for transfer (master mode).

+  * @note   Changing these bits when START bit is set is not allowed.

+  * @rmtoll CR2          SADD           LL_I2C_SetSlaveAddr

+  * @param  I2Cx I2C Instance.

+  * @param  SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)

+{

+  MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);

+}

+

+/**

+  * @brief  Get the slave address programmed for transfer.

+  * @rmtoll CR2          SADD           LL_I2C_GetSlaveAddr

+  * @param  I2Cx I2C Instance.

+  * @retval Value between Min_Data=0x0 and Max_Data=0x3F

+  */

+__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)

+{

+  return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));

+}

+

+/**

+  * @brief  Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).

+  * @rmtoll CR2          SADD          LL_I2C_HandleTransfer\n

+  *         CR2          ADD10         LL_I2C_HandleTransfer\n

+  *         CR2          RD_WRN        LL_I2C_HandleTransfer\n

+  *         CR2          START         LL_I2C_HandleTransfer\n

+  *         CR2          STOP          LL_I2C_HandleTransfer\n

+  *         CR2          RELOAD        LL_I2C_HandleTransfer\n

+  *         CR2          NBYTES        LL_I2C_HandleTransfer\n

+  *         CR2          AUTOEND       LL_I2C_HandleTransfer\n

+  *         CR2          HEAD10R       LL_I2C_HandleTransfer

+  * @param  I2Cx I2C Instance.

+  * @param  SlaveAddr Specifies the slave address to be programmed.

+  * @param  SlaveAddrSize This parameter can be one of the following values:

+  *         @arg @ref LL_I2C_ADDRSLAVE_7BIT

+  *         @arg @ref LL_I2C_ADDRSLAVE_10BIT

+  * @param  TransferSize Specifies the number of bytes to be programmed.

+  *                       This parameter must be a value between Min_Data=0 and Max_Data=255.

+  * @param  EndMode This parameter can be one of the following values:

+  *         @arg @ref LL_I2C_MODE_RELOAD

+  *         @arg @ref LL_I2C_MODE_AUTOEND

+  *         @arg @ref LL_I2C_MODE_SOFTEND

+  *         @arg @ref LL_I2C_MODE_SMBUS_RELOAD

+  *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC

+  *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC

+  *         @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC

+  *         @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC

+  * @param  Request This parameter can be one of the following values:

+  *         @arg @ref LL_I2C_GENERATE_NOSTARTSTOP

+  *         @arg @ref LL_I2C_GENERATE_STOP

+  *         @arg @ref LL_I2C_GENERATE_START_READ

+  *         @arg @ref LL_I2C_GENERATE_START_WRITE

+  *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ

+  *         @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE

+  *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ

+  *         @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,

+                                           uint32_t TransferSize, uint32_t EndMode, uint32_t Request)

+{

+  MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |

+             I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,

+             SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);

+}

+

+/**

+  * @brief  Indicate the value of transfer direction (slave mode).

+  * @note   RESET: Write transfer, Slave enters in receiver mode.

+  *         SET: Read transfer, Slave enters in transmitter mode.

+  * @rmtoll ISR          DIR           LL_I2C_GetTransferDirection

+  * @param  I2Cx I2C Instance.

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_I2C_DIRECTION_WRITE

+  *         @arg @ref LL_I2C_DIRECTION_READ

+  */

+__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)

+{

+  return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));

+}

+

+/**

+  * @brief  Return the slave matched address.

+  * @rmtoll ISR          ADDCODE       LL_I2C_GetAddressMatchCode

+  * @param  I2Cx I2C Instance.

+  * @retval Value between Min_Data=0x00 and Max_Data=0x3F

+  */

+__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)

+{

+  return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);

+}

+

+/**

+  * @brief  Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).

+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not

+  *         SMBus feature is supported by the I2Cx Instance.

+  * @note   This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.

+  *         This bit has no effect when RELOAD bit is set.

+  *         This bit has no effect in device mode when SBC bit is not set.

+  * @rmtoll CR2          PECBYTE       LL_I2C_EnableSMBusPECCompare

+  * @param  I2Cx I2C Instance.

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)

+{

+  SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);

+}

+

+/**

+  * @brief  Check if the SMBus Packet Error byte internal comparison is requested or not.

+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not

+  *         SMBus feature is supported by the I2Cx Instance.

+  * @rmtoll CR2          PECBYTE       LL_I2C_IsEnabledSMBusPECCompare

+  * @param  I2Cx I2C Instance.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)

+{

+  return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get the SMBus Packet Error byte calculated.

+  * @note   Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not

+  *         SMBus feature is supported by the I2Cx Instance.

+  * @rmtoll PECR         PEC           LL_I2C_GetSMBusPEC

+  * @param  I2Cx I2C Instance.

+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF

+*/

+__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)

+{

+  return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));

+}

+

+/**

+  * @brief  Read Receive Data register.

+  * @rmtoll RXDR         RXDATA        LL_I2C_ReceiveData8

+  * @param  I2Cx I2C Instance.

+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF

+  */

+__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)

+{

+  return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));

+}

+

+/**

+  * @brief  Write in Transmit Data Register .

+  * @rmtoll TXDR         TXDATA        LL_I2C_TransmitData8

+  * @param  I2Cx I2C Instance.

+  * @param  Data Value between Min_Data=0x00 and Max_Data=0xFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)

+{

+  WRITE_REG(I2Cx->TXDR, Data);

+}

+

+/**

+  * @}

+  */

+

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions

+  * @{

+  */

+

+ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);

+ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx);

+void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);

+

+

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* I2C1 || I2C2 || I2C3 || I2C4 */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_LL_I2C_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_iwdg.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_iwdg.h
new file mode 100644
index 0000000000..8a8e2a138a
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_iwdg.h
@@ -0,0 +1,342 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_iwdg.h

+  * @author  MCD Application Team

+  * @brief   Header file of IWDG LL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_LL_IWDG_H

+#define STM32H7xx_LL_IWDG_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+#if defined(IWDG1) || defined(IWDG2)

+

+/** @defgroup IWDG_LL IWDG

+  * @{

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants

+  * @{

+  */

+#define LL_IWDG_KEY_RELOAD                 0x0000AAAAU               /*!< IWDG Reload Counter Enable   */

+#define LL_IWDG_KEY_ENABLE                 0x0000CCCCU               /*!< IWDG Peripheral Enable       */

+#define LL_IWDG_KEY_WR_ACCESS_ENABLE       0x00005555U               /*!< IWDG KR Write Access Enable  */

+#define LL_IWDG_KEY_WR_ACCESS_DISABLE      0x00000000U               /*!< IWDG KR Write Access Disable */

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+

+/* Exported types ------------------------------------------------------------*/

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants

+  * @{

+  */

+

+/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines

+  * @brief    Flags defines which can be used with LL_IWDG_ReadReg function

+  * @{

+  */

+#define LL_IWDG_SR_PVU                     IWDG_SR_PVU                           /*!< Watchdog prescaler value update */

+#define LL_IWDG_SR_RVU                     IWDG_SR_RVU                           /*!< Watchdog counter reload value update */

+#define LL_IWDG_SR_WVU                     IWDG_SR_WVU                           /*!< Watchdog counter window value update */

+/**

+  * @}

+  */

+

+/** @defgroup IWDG_LL_EC_PRESCALER  Prescaler Divider

+  * @{

+  */

+#define LL_IWDG_PRESCALER_4                0x00000000U                           /*!< Divider by 4   */

+#define LL_IWDG_PRESCALER_8                (IWDG_PR_PR_0)                        /*!< Divider by 8   */

+#define LL_IWDG_PRESCALER_16               (IWDG_PR_PR_1)                        /*!< Divider by 16  */

+#define LL_IWDG_PRESCALER_32               (IWDG_PR_PR_1 | IWDG_PR_PR_0)         /*!< Divider by 32  */

+#define LL_IWDG_PRESCALER_64               (IWDG_PR_PR_2)                        /*!< Divider by 64  */

+#define LL_IWDG_PRESCALER_128              (IWDG_PR_PR_2 | IWDG_PR_PR_0)         /*!< Divider by 128 */

+#define LL_IWDG_PRESCALER_256              (IWDG_PR_PR_2 | IWDG_PR_PR_1)         /*!< Divider by 256 */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros

+  * @{

+  */

+

+/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros

+  * @{

+  */

+

+/**

+  * @brief  Write a value in IWDG register

+  * @param  __INSTANCE__ IWDG Instance

+  * @param  __REG__ Register to be written

+  * @param  __VALUE__ Value to be written in the register

+  * @retval None

+  */

+#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

+

+/**

+  * @brief  Read a value in IWDG register

+  * @param  __INSTANCE__ IWDG Instance

+  * @param  __REG__ Register to be read

+  * @retval Register value

+  */

+#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions

+  * @{

+  */

+/** @defgroup IWDG_LL_EF_Configuration Configuration

+  * @{

+  */

+

+/**

+  * @brief  Start the Independent Watchdog

+  * @note   Except if the hardware watchdog option is selected

+  * @rmtoll KR           KEY           LL_IWDG_Enable

+  * @param  IWDGx IWDG Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx)

+{

+  WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE);

+}

+

+/**

+  * @brief  Reloads IWDG counter with value defined in the reload register

+  * @rmtoll KR           KEY           LL_IWDG_ReloadCounter

+  * @param  IWDGx IWDG Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx)

+{

+  WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD);

+}

+

+/**

+  * @brief  Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers

+  * @rmtoll KR           KEY           LL_IWDG_EnableWriteAccess

+  * @param  IWDGx IWDG Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx)

+{

+  WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE);

+}

+

+/**

+  * @brief  Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers

+  * @rmtoll KR           KEY           LL_IWDG_DisableWriteAccess

+  * @param  IWDGx IWDG Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx)

+{

+  WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE);

+}

+

+/**

+  * @brief  Select the prescaler of the IWDG

+  * @rmtoll PR           PR            LL_IWDG_SetPrescaler

+  * @param  IWDGx IWDG Instance

+  * @param  Prescaler This parameter can be one of the following values:

+  *         @arg @ref LL_IWDG_PRESCALER_4

+  *         @arg @ref LL_IWDG_PRESCALER_8

+  *         @arg @ref LL_IWDG_PRESCALER_16

+  *         @arg @ref LL_IWDG_PRESCALER_32

+  *         @arg @ref LL_IWDG_PRESCALER_64

+  *         @arg @ref LL_IWDG_PRESCALER_128

+  *         @arg @ref LL_IWDG_PRESCALER_256

+  * @retval None

+  */

+__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler)

+{

+  WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler);

+}

+

+/**

+  * @brief  Get the selected prescaler of the IWDG

+  * @rmtoll PR           PR            LL_IWDG_GetPrescaler

+  * @param  IWDGx IWDG Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_IWDG_PRESCALER_4

+  *         @arg @ref LL_IWDG_PRESCALER_8

+  *         @arg @ref LL_IWDG_PRESCALER_16

+  *         @arg @ref LL_IWDG_PRESCALER_32

+  *         @arg @ref LL_IWDG_PRESCALER_64

+  *         @arg @ref LL_IWDG_PRESCALER_128

+  *         @arg @ref LL_IWDG_PRESCALER_256

+  */

+__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx)

+{

+  return (READ_REG(IWDGx->PR));

+}

+

+/**

+  * @brief  Specify the IWDG down-counter reload value

+  * @rmtoll RLR          RL            LL_IWDG_SetReloadCounter

+  * @param  IWDGx IWDG Instance

+  * @param  Counter Value between Min_Data=0 and Max_Data=0x0FFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter)

+{

+  WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter);

+}

+

+/**

+  * @brief  Get the specified IWDG down-counter reload value

+  * @rmtoll RLR          RL            LL_IWDG_GetReloadCounter

+  * @param  IWDGx IWDG Instance

+  * @retval Value between Min_Data=0 and Max_Data=0x0FFF

+  */

+__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx)

+{

+  return (READ_REG(IWDGx->RLR));

+}

+

+/**

+  * @brief  Specify high limit of the window value to be compared to the down-counter.

+  * @rmtoll WINR         WIN           LL_IWDG_SetWindow

+  * @param  IWDGx IWDG Instance

+  * @param  Window Value between Min_Data=0 and Max_Data=0x0FFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window)

+{

+  WRITE_REG(IWDGx->WINR, IWDG_WINR_WIN & Window);

+}

+

+/**

+  * @brief  Get the high limit of the window value specified.

+  * @rmtoll WINR         WIN           LL_IWDG_GetWindow

+  * @param  IWDGx IWDG Instance

+  * @retval Value between Min_Data=0 and Max_Data=0x0FFF

+  */

+__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx)

+{

+  return (READ_REG(IWDGx->WINR));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management

+  * @{

+  */

+

+/**

+  * @brief  Check if flag Prescaler Value Update is set or not

+  * @rmtoll SR           PVU           LL_IWDG_IsActiveFlag_PVU

+  * @param  IWDGx IWDG Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx)

+{

+  return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if flag Reload Value Update is set or not

+  * @rmtoll SR           RVU           LL_IWDG_IsActiveFlag_RVU

+  * @param  IWDGx IWDG Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx)

+{

+  return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if flag Window Value Update is set or not

+  * @rmtoll SR           WVU           LL_IWDG_IsActiveFlag_WVU

+  * @param  IWDGx IWDG Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx)

+{

+  return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if all flags Prescaler, Reload & Window Value Update are reset or not

+  * @rmtoll SR           PVU           LL_IWDG_IsReady\n

+  *         SR           WVU           LL_IWDG_IsReady\n

+  *         SR           RVU           LL_IWDG_IsReady

+  * @param  IWDGx IWDG Instance

+  * @retval State of bits (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx)

+{

+  return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* IWDG1 || IWDG2 */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_LL_IWDG_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_lptim.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_lptim.h
new file mode 100644
index 0000000000..fe6a11af7c
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_lptim.h
@@ -0,0 +1,1494 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_lptim.h

+  * @author  MCD Application Team

+  * @brief   Header file of LPTIM LL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_LL_LPTIM_H

+#define STM32H7xx_LL_LPTIM_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+#if defined (LPTIM1) || defined (LPTIM2) || defined (LPTIM3) || defined (LPTIM4) || defined (LPTIM5)

+

+/** @defgroup LPTIM_LL LPTIM

+  * @{

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+

+/* Private constants ---------------------------------------------------------*/

+

+/* Private macros ------------------------------------------------------------*/

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup LPTIM_LL_Private_Macros LPTIM Private Macros

+  * @{

+  */

+/**

+  * @}

+  */

+#endif /*USE_FULL_LL_DRIVER*/

+

+/* Exported types ------------------------------------------------------------*/

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup LPTIM_LL_ES_INIT LPTIM Exported Init structure

+  * @{

+  */

+

+/**

+  * @brief  LPTIM Init structure definition

+  */

+typedef struct

+{

+  uint32_t ClockSource;    /*!< Specifies the source of the clock used by the LPTIM instance.

+                                This parameter can be a value of @ref LPTIM_LL_EC_CLK_SOURCE.

+

+                                This feature can be modified afterwards using unitary function @ref LL_LPTIM_SetClockSource().*/

+

+  uint32_t Prescaler;      /*!< Specifies the prescaler division ratio.

+                                This parameter can be a value of @ref LPTIM_LL_EC_PRESCALER.

+

+                                This feature can be modified afterwards using using unitary function @ref LL_LPTIM_SetPrescaler().*/

+

+  uint32_t Waveform;       /*!< Specifies the waveform shape.

+                                This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_WAVEFORM.

+

+                                This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/

+

+  uint32_t Polarity;       /*!< Specifies waveform polarity.

+                                This parameter can be a value of @ref LPTIM_LL_EC_OUTPUT_POLARITY.

+

+                                This feature can be modified afterwards using unitary function @ref LL_LPTIM_ConfigOutput().*/

+} LL_LPTIM_InitTypeDef;

+

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup LPTIM_LL_Exported_Constants LPTIM Exported Constants

+  * @{

+  */

+

+/** @defgroup LPTIM_LL_EC_GET_FLAG Get Flags Defines

+  * @brief    Flags defines which can be used with LL_LPTIM_ReadReg function

+  * @{

+  */

+#define LL_LPTIM_ISR_CMPM                     LPTIM_ISR_CMPM     /*!< Compare match */

+#define LL_LPTIM_ISR_ARRM                     LPTIM_ISR_ARRM     /*!< Autoreload match */

+#define LL_LPTIM_ISR_EXTTRIG                  LPTIM_ISR_EXTTRIG  /*!< External trigger edge event */

+#define LL_LPTIM_ISR_CMPOK                    LPTIM_ISR_CMPOK    /*!< Compare register update OK */

+#define LL_LPTIM_ISR_ARROK                    LPTIM_ISR_ARROK    /*!< Autoreload register update OK */

+#define LL_LPTIM_ISR_UP                       LPTIM_ISR_UP       /*!< Counter direction change down to up */

+#define LL_LPTIM_ISR_DOWN                     LPTIM_ISR_DOWN     /*!< Counter direction change up to down */

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_LL_EC_IT IT Defines

+  * @brief    IT defines which can be used with LL_LPTIM_ReadReg and  LL_LPTIM_WriteReg functions

+  * @{

+  */

+#define LL_LPTIM_IER_CMPMIE                   LPTIM_IER_CMPMIE       /*!< Compare match Interrupt Enable */

+#define LL_LPTIM_IER_ARRMIE                   LPTIM_IER_ARRMIE       /*!< Autoreload match Interrupt Enable */

+#define LL_LPTIM_IER_EXTTRIGIE                LPTIM_IER_EXTTRIGIE    /*!< External trigger valid edge Interrupt Enable */

+#define LL_LPTIM_IER_CMPOKIE                  LPTIM_IER_CMPOKIE      /*!< Compare register update OK Interrupt Enable */

+#define LL_LPTIM_IER_ARROKIE                  LPTIM_IER_ARROKIE      /*!< Autoreload register update OK Interrupt Enable */

+#define LL_LPTIM_IER_UPIE                     LPTIM_IER_UPIE         /*!< Direction change to UP Interrupt Enable */

+#define LL_LPTIM_IER_DOWNIE                   LPTIM_IER_DOWNIE       /*!< Direction change to down Interrupt Enable */

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_LL_EC_OPERATING_MODE Operating Mode

+  * @{

+  */

+#define LL_LPTIM_OPERATING_MODE_CONTINUOUS    LPTIM_CR_CNTSTRT /*!<LP Timer starts in continuous mode*/

+#define LL_LPTIM_OPERATING_MODE_ONESHOT       LPTIM_CR_SNGSTRT /*!<LP Tilmer starts in single mode*/

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_LL_EC_UPDATE_MODE Update Mode

+  * @{

+  */

+#define LL_LPTIM_UPDATE_MODE_IMMEDIATE        0x00000000U        /*!<Preload is disabled: registers are updated after each APB bus write access*/

+#define LL_LPTIM_UPDATE_MODE_ENDOFPERIOD      LPTIM_CFGR_PRELOAD /*!<preload is enabled: registers are updated at the end of the current LPTIM period*/

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_LL_EC_COUNTER_MODE Counter Mode

+  * @{

+  */

+#define LL_LPTIM_COUNTER_MODE_INTERNAL        0x00000000U          /*!<The counter is incremented following each internal clock pulse*/

+#define LL_LPTIM_COUNTER_MODE_EXTERNAL        LPTIM_CFGR_COUNTMODE /*!<The counter is incremented following each valid clock pulse on the LPTIM external Input1*/

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_LL_EC_OUTPUT_WAVEFORM Output Waveform Type

+  * @{

+  */

+#define LL_LPTIM_OUTPUT_WAVEFORM_PWM          0x00000000U     /*!<LPTIM  generates either a PWM waveform or a One pulse waveform depending on chosen operating mode CONTINOUS or SINGLE*/

+#define LL_LPTIM_OUTPUT_WAVEFORM_SETONCE      LPTIM_CFGR_WAVE /*!<LPTIM  generates a Set Once waveform*/

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_LL_EC_OUTPUT_POLARITY Output Polarity

+  * @{

+  */

+#define LL_LPTIM_OUTPUT_POLARITY_REGULAR      0x00000000U             /*!<The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/

+#define LL_LPTIM_OUTPUT_POLARITY_INVERSE      LPTIM_CFGR_WAVPOL       /*!<The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers*/

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_LL_EC_PRESCALER Prescaler Value

+  * @{

+  */

+#define LL_LPTIM_PRESCALER_DIV1               0x00000000U                               /*!<Prescaler division factor is set to 1*/

+#define LL_LPTIM_PRESCALER_DIV2               LPTIM_CFGR_PRESC_0                        /*!<Prescaler division factor is set to 2*/

+#define LL_LPTIM_PRESCALER_DIV4               LPTIM_CFGR_PRESC_1                        /*!<Prescaler division factor is set to 4*/

+#define LL_LPTIM_PRESCALER_DIV8               (LPTIM_CFGR_PRESC_1 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 8*/

+#define LL_LPTIM_PRESCALER_DIV16              LPTIM_CFGR_PRESC_2                        /*!<Prescaler division factor is set to 16*/

+#define LL_LPTIM_PRESCALER_DIV32              (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_0) /*!<Prescaler division factor is set to 32*/

+#define LL_LPTIM_PRESCALER_DIV64              (LPTIM_CFGR_PRESC_2 | LPTIM_CFGR_PRESC_1) /*!<Prescaler division factor is set to 64*/

+#define LL_LPTIM_PRESCALER_DIV128             LPTIM_CFGR_PRESC                          /*!<Prescaler division factor is set to 128*/

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_LL_EC_TRIG_SOURCE Trigger Source

+  * @{

+  */

+#define LL_LPTIM_TRIG_SOURCE_GPIO             0x00000000U                                                          /*!<External input trigger is connected to TIMx_ETR input*/

+#define LL_LPTIM_TRIG_SOURCE_RTCALARMA        LPTIM_CFGR_TRIGSEL_0                                                 /*!<External input trigger is connected to RTC Alarm A*/

+#define LL_LPTIM_TRIG_SOURCE_RTCALARMB        LPTIM_CFGR_TRIGSEL_1                                                 /*!<External input trigger is connected to RTC Alarm B*/

+#define LL_LPTIM_TRIG_SOURCE_RTCTAMP1         (LPTIM_CFGR_TRIGSEL_1 | LPTIM_CFGR_TRIGSEL_0)                        /*!<External input trigger is connected to RTC Tamper 1*/

+#define LL_LPTIM_TRIG_SOURCE_RTCTAMP2         LPTIM_CFGR_TRIGSEL_2                                                 /*!<External input trigger is connected to RTC Tamper 2*/

+#define LL_LPTIM_TRIG_SOURCE_RTCTAMP3         (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_0)                        /*!<External input trigger is connected to RTC Tamper 3*/

+#define LL_LPTIM_TRIG_SOURCE_COMP1            (LPTIM_CFGR_TRIGSEL_2 | LPTIM_CFGR_TRIGSEL_1)                        /*!<External input trigger is connected to COMP1 output*/

+#define LL_LPTIM_TRIG_SOURCE_COMP2            LPTIM_CFGR_TRIGSEL                                                   /*!<External input trigger is connected to COMP2 output*/

+#define LL_LPTIM_TRIG_SOURCE_LPTIM2           0x00000000U                                                          /*!<External input trigger is connected to LPTIM2 output*/

+#define LL_LPTIM_TRIG_SOURCE_LPTIM3           LPTIM_CFGR_TRIGSEL_0                                                 /*!<External input trigger is connected to LPTIM3 output*/

+#define LL_LPTIM_TRIG_SOURCE_LPTIM4           LPTIM_CFGR_TRIGSEL_1                                                 /*!<External input trigger is connected to LPTIM4 output*/

+#define LL_LPTIM_TRIG_SOURCE_LPTIM5           (LPTIM_CFGR_TRIGSEL_1|LPTIM_CFGR_TRIGSEL_0)                          /*!<External input trigger is connected to LPTIM5 output*/

+#define LL_LPTIM_TRIG_SOURCE_SAI1_FS_A        LPTIM_CFGR_TRIGSEL_2                                                 /*!<External input trigger is connected to SAI1 FS A output*/

+#define LL_LPTIM_TRIG_SOURCE_SAI1_FS_B        (LPTIM_CFGR_TRIGSEL_2|LPTIM_CFGR_TRIGSEL_0)                          /*!<External input trigger is connected to SAI1 FS B output*/

+#define LL_LPTIM_TRIG_SOURCE_SAI2_FS_A        LPTIM_CFGR_TRIGSEL_2                                                 /*!<External input trigger is connected to SAI2 FS A output*/

+#define LL_LPTIM_TRIG_SOURCE_SAI2_FS_B        (LPTIM_CFGR_TRIGSEL_2|LPTIM_CFGR_TRIGSEL_0)                          /*!<External input trigger is connected to SAI2 FS B output*/

+#define LL_LPTIM_TRIG_SOURCE_SAI4_FS_A        (LPTIM_CFGR_TRIGSEL_1|LPTIM_CFGR_TRIGSEL_0)                          /*!<External input trigger is connected to SAI4 FS A output*/

+#define LL_LPTIM_TRIG_SOURCE_SAI4_FS_B        LPTIM_CFGR_TRIGSEL_2                                                 /*!<External input trigger is connected to SAI4 FS B output*/

+#define LL_LPTIM_TRIG_SOURCE_DFSDM2_BRK       (LPTIM_CFGR_TRIGSEL_2|LPTIM_CFGR_TRIGSEL_1)                          /*!<External input trigger is connected to DFSDM2_BRK[0] */

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_LL_EC_TRIG_FILTER Trigger Filter

+  * @{

+  */

+#define LL_LPTIM_TRIG_FILTER_NONE             0x00000000U         /*!<Any trigger active level change is considered as a valid trigger*/

+#define LL_LPTIM_TRIG_FILTER_2                LPTIM_CFGR_TRGFLT_0 /*!<Trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger*/

+#define LL_LPTIM_TRIG_FILTER_4                LPTIM_CFGR_TRGFLT_1 /*!<Trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger*/

+#define LL_LPTIM_TRIG_FILTER_8                LPTIM_CFGR_TRGFLT   /*!<Trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger*/

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_LL_EC_TRIG_POLARITY Trigger Polarity

+  * @{

+  */

+#define LL_LPTIM_TRIG_POLARITY_RISING         LPTIM_CFGR_TRIGEN_0 /*!<LPTIM counter starts when a rising edge is detected*/

+#define LL_LPTIM_TRIG_POLARITY_FALLING        LPTIM_CFGR_TRIGEN_1 /*!<LPTIM counter starts when a falling edge is detected*/

+#define LL_LPTIM_TRIG_POLARITY_RISING_FALLING LPTIM_CFGR_TRIGEN   /*!<LPTIM counter starts when a rising or a falling edge is detected*/

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_LL_EC_CLK_SOURCE Clock Source

+  * @{

+  */

+#define LL_LPTIM_CLK_SOURCE_INTERNAL          0x00000000U      /*!<LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators)*/

+#define LL_LPTIM_CLK_SOURCE_EXTERNAL          LPTIM_CFGR_CKSEL /*!<LPTIM is clocked by an external clock source through the LPTIM external Input1*/

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_LL_EC_CLK_FILTER Clock Filter

+  * @{

+  */

+#define LL_LPTIM_CLK_FILTER_NONE              0x00000000U        /*!<Any external clock signal level change is considered as a valid transition*/

+#define LL_LPTIM_CLK_FILTER_2                 LPTIM_CFGR_CKFLT_0 /*!<External clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition*/

+#define LL_LPTIM_CLK_FILTER_4                 LPTIM_CFGR_CKFLT_1 /*!<External clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition*/

+#define LL_LPTIM_CLK_FILTER_8                 LPTIM_CFGR_CKFLT   /*!<External clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition*/

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_LL_EC_CLK_POLARITY Clock Polarity

+  * @{

+  */

+#define LL_LPTIM_CLK_POLARITY_RISING          0x00000000U        /*!< The rising edge is the active edge used for counting*/

+#define LL_LPTIM_CLK_POLARITY_FALLING         LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/

+#define LL_LPTIM_CLK_POLARITY_RISING_FALLING  LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_LL_EC_ENCODER_MODE Encoder Mode

+  * @{

+  */

+#define LL_LPTIM_ENCODER_MODE_RISING          0x00000000U        /*!< The rising edge is the active edge used for counting*/

+#define LL_LPTIM_ENCODER_MODE_FALLING         LPTIM_CFGR_CKPOL_0 /*!< The falling edge is the active edge used for counting*/

+#define LL_LPTIM_ENCODER_MODE_RISING_FALLING  LPTIM_CFGR_CKPOL_1 /*!< Both edges are active edges*/

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_EC_INPUT1_SRC Input1 Source

+  * @{

+  */

+#define LL_LPTIM_INPUT1_SRC_GPIO         0x00000000U                                            /*!< For LPTIM1 and LPTIM2 */

+#define LL_LPTIM_INPUT1_SRC_COMP1        LPTIM_CFGR2_IN1SEL_0                                   /*!< For LPTIM1 and LPTIM2 */

+#define LL_LPTIM_INPUT1_SRC_COMP2        LPTIM_CFGR2_IN1SEL_1                                   /*!< For LPTIM2 */

+#define LL_LPTIM_INPUT1_SRC_COMP1_COMP2  (LPTIM_CFGR2_IN1SEL_1 | LPTIM_CFGR2_IN1SEL_0)          /*!< For LPTIM2 */

+#define LL_LPTIM_INPUT1_SRC_SAI4_FS_A    LPTIM_CFGR2_IN1SEL_0                                   /*!< For LPTIM3 */

+#define LL_LPTIM_INPUT1_SRC_SAI4_FS_B    LPTIM_CFGR2_IN1SEL_1                                   /*!< For LPTIM3 */

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_EC_INPUT2_SRC Input2 Source

+  * @{

+  */

+#define LL_LPTIM_INPUT2_SRC_GPIO         0x00000000U                   /*!< For LPTIM1 */

+#define LL_LPTIM_INPUT2_SRC_COMP2        LPTIM_CFGR2_IN2SEL_0          /*!< For LPTIM1 */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup LPTIM_LL_Exported_Macros LPTIM Exported Macros

+  * @{

+  */

+

+/** @defgroup LPTIM_LL_EM_WRITE_READ Common Write and read registers Macros

+  * @{

+  */

+

+/**

+  * @brief  Write a value in LPTIM register

+  * @param  __INSTANCE__ LPTIM Instance

+  * @param  __REG__ Register to be written

+  * @param  __VALUE__ Value to be written in the register

+  * @retval None

+  */

+#define LL_LPTIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))

+

+/**

+  * @brief  Read a value in LPTIM register

+  * @param  __INSTANCE__ LPTIM Instance

+  * @param  __REG__ Register to be read

+  * @retval Register value

+  */

+#define LL_LPTIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup LPTIM_LL_Exported_Functions LPTIM Exported Functions

+  * @{

+  */

+

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup LPTIM_LL_EF_Init Initialisation and deinitialisation functions

+  * @{

+  */

+

+ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx);

+void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct);

+ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, LL_LPTIM_InitTypeDef *LPTIM_InitStruct);

+void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx);

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/** @defgroup LPTIM_LL_EF_LPTIM_Configuration LPTIM Configuration

+  * @{

+  */

+

+/**

+  * @brief  Enable the LPTIM instance

+  * @note After setting the ENABLE bit, a delay of two counter clock is needed

+  *       before the LPTIM instance is actually enabled.

+  * @rmtoll CR           ENABLE        LL_LPTIM_Enable

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_Enable(LPTIM_TypeDef *LPTIMx)

+{

+  SET_BIT(LPTIMx->CR, LPTIM_CR_ENABLE);

+}

+

+/**

+  * @brief  Indicates whether the LPTIM instance is enabled.

+  * @rmtoll CR           ENABLE        LL_LPTIM_IsEnabled

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabled(LPTIM_TypeDef *LPTIMx)

+{

+  return (((READ_BIT(LPTIMx->CR, LPTIM_CR_ENABLE) == LPTIM_CR_ENABLE) ? 1UL : 0UL));

+}

+

+/**

+  * @brief  Starts the LPTIM counter in the desired mode.

+  * @note LPTIM instance must be enabled before starting the counter.

+  * @note It is possible to change on the fly from One Shot mode to

+  *       Continuous mode.

+  * @rmtoll CR           CNTSTRT       LL_LPTIM_StartCounter\n

+  *         CR           SNGSTRT       LL_LPTIM_StartCounter

+  * @param  LPTIMx Low-Power Timer instance

+  * @param  OperatingMode This parameter can be one of the following values:

+  *         @arg @ref LL_LPTIM_OPERATING_MODE_CONTINUOUS

+  *         @arg @ref LL_LPTIM_OPERATING_MODE_ONESHOT

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_StartCounter(LPTIM_TypeDef *LPTIMx, uint32_t OperatingMode)

+{

+  MODIFY_REG(LPTIMx->CR, LPTIM_CR_CNTSTRT | LPTIM_CR_SNGSTRT, OperatingMode);

+}

+

+/**

+  * @brief  Enable reset after read.

+  * @note After calling this function any read access to LPTIM_CNT

+  *        register will asynchronously reset the LPTIM_CNT register content.

+  * @rmtoll CR           RSTARE        LL_LPTIM_EnableResetAfterRead

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_EnableResetAfterRead(LPTIM_TypeDef *LPTIMx)

+{

+  SET_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);

+}

+

+/**

+  * @brief  Disable reset after read.

+  * @rmtoll CR           RSTARE        LL_LPTIM_DisableResetAfterRead

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_DisableResetAfterRead(LPTIM_TypeDef *LPTIMx)

+{

+  CLEAR_BIT(LPTIMx->CR, LPTIM_CR_RSTARE);

+}

+

+/**

+  * @brief  Indicate whether the reset after read feature is enabled.

+  * @rmtoll CR           RSTARE        LL_LPTIM_IsEnabledResetAfterRead

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledResetAfterRead(LPTIM_TypeDef *LPTIMx)

+{

+  return (((READ_BIT(LPTIMx->CR, LPTIM_CR_RSTARE) == LPTIM_CR_RSTARE) ? 1UL : 0UL));

+}

+

+/**

+  * @brief  Reset of the LPTIM_CNT counter register (synchronous).

+  * @note Due to the synchronous nature of this reset, it only takes

+  *       place after a synchronization delay of 3 LPTIM core clock cycles

+  *      (LPTIM core clock may be different from APB clock).

+  * @note COUNTRST is automatically cleared by hardware

+  * @rmtoll CR           COUNTRST       LL_LPTIM_ResetCounter\n

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_ResetCounter(LPTIM_TypeDef *LPTIMx)

+{

+  SET_BIT(LPTIMx->CR, LPTIM_CR_COUNTRST);

+}

+

+/**

+  * @brief  Set the LPTIM registers update mode (enable/disable register preload)

+  * @note This function must be called when the LPTIM instance is disabled.

+  * @rmtoll CFGR         PRELOAD       LL_LPTIM_SetUpdateMode

+  * @param  LPTIMx Low-Power Timer instance

+  * @param  UpdateMode This parameter can be one of the following values:

+  *         @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE

+  *         @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_SetUpdateMode(LPTIM_TypeDef *LPTIMx, uint32_t UpdateMode)

+{

+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD, UpdateMode);

+}

+

+/**

+  * @brief  Get the LPTIM registers update mode

+  * @rmtoll CFGR         PRELOAD       LL_LPTIM_GetUpdateMode

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_LPTIM_UPDATE_MODE_IMMEDIATE

+  *         @arg @ref LL_LPTIM_UPDATE_MODE_ENDOFPERIOD

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_GetUpdateMode(LPTIM_TypeDef *LPTIMx)

+{

+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRELOAD));

+}

+

+/**

+  * @brief  Set the auto reload value

+  * @note The LPTIMx_ARR register content must only be modified when the LPTIM is enabled

+  * @note After a write to the LPTIMx_ARR register a new write operation to the

+  *       same register can only be performed when the previous write operation

+  *       is completed. Any successive write before  the ARROK flag is set, will

+  *       lead to unpredictable results.

+  * @note autoreload value be strictly greater than the compare value.

+  * @rmtoll ARR          ARR           LL_LPTIM_SetAutoReload

+  * @param  LPTIMx Low-Power Timer instance

+  * @param  AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_SetAutoReload(LPTIM_TypeDef *LPTIMx, uint32_t AutoReload)

+{

+  MODIFY_REG(LPTIMx->ARR, LPTIM_ARR_ARR, AutoReload);

+}

+

+/**

+  * @brief  Get actual auto reload value

+  * @rmtoll ARR          ARR           LL_LPTIM_GetAutoReload

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval AutoReload Value between Min_Data=0x00 and Max_Data=0xFFFF

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_GetAutoReload(LPTIM_TypeDef *LPTIMx)

+{

+  return (uint32_t)(READ_BIT(LPTIMx->ARR, LPTIM_ARR_ARR));

+}

+

+/**

+  * @brief  Set the compare value

+  * @note After a write to the LPTIMx_CMP register a new write operation to the

+  *       same register can only be performed when the previous write operation

+  *       is completed. Any successive write before the CMPOK flag is set, will

+  *       lead to unpredictable results.

+  * @rmtoll CMP          CMP           LL_LPTIM_SetCompare

+  * @param  LPTIMx Low-Power Timer instance

+  * @param  CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_SetCompare(LPTIM_TypeDef *LPTIMx, uint32_t CompareValue)

+{

+  MODIFY_REG(LPTIMx->CMP, LPTIM_CMP_CMP, CompareValue);

+}

+

+/**

+  * @brief  Get actual compare value

+  * @rmtoll CMP          CMP           LL_LPTIM_GetCompare

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval CompareValue Value between Min_Data=0x00 and Max_Data=0xFFFF

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_GetCompare(LPTIM_TypeDef *LPTIMx)

+{

+  return (uint32_t)(READ_BIT(LPTIMx->CMP, LPTIM_CMP_CMP));

+}

+

+/**

+  * @brief  Get actual counter value

+  * @note When the LPTIM instance is running with an asynchronous clock, reading

+  *       the LPTIMx_CNT register may return unreliable values. So in this case

+  *       it is necessary to perform two consecutive read accesses and verify

+  *       that the two returned values are identical.

+  * @rmtoll CNT          CNT           LL_LPTIM_GetCounter

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval Counter value

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_GetCounter(LPTIM_TypeDef *LPTIMx)

+{

+  return (uint32_t)(READ_BIT(LPTIMx->CNT, LPTIM_CNT_CNT));

+}

+

+/**

+  * @brief  Set the counter mode (selection of the LPTIM counter clock source).

+  * @note The counter mode can be set only when the LPTIM instance is disabled.

+  * @rmtoll CFGR         COUNTMODE     LL_LPTIM_SetCounterMode

+  * @param  LPTIMx Low-Power Timer instance

+  * @param  CounterMode This parameter can be one of the following values:

+  *         @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL

+  *         @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_SetCounterMode(LPTIM_TypeDef *LPTIMx, uint32_t CounterMode)

+{

+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE, CounterMode);

+}

+

+/**

+  * @brief  Get the counter mode

+  * @rmtoll CFGR         COUNTMODE     LL_LPTIM_GetCounterMode

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_LPTIM_COUNTER_MODE_INTERNAL

+  *         @arg @ref LL_LPTIM_COUNTER_MODE_EXTERNAL

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_GetCounterMode(LPTIM_TypeDef *LPTIMx)

+{

+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_COUNTMODE));

+}

+

+/**

+  * @brief  Configure the LPTIM instance output (LPTIMx_OUT)

+  * @note This function must be called when the LPTIM instance is disabled.

+  * @note Regarding the LPTIM output polarity the change takes effect

+  *       immediately, so the output default value will change immediately after

+  *       the polarity is re-configured, even before the timer is enabled.

+  * @rmtoll CFGR         WAVE          LL_LPTIM_ConfigOutput\n

+  *         CFGR         WAVPOL        LL_LPTIM_ConfigOutput

+  * @param  LPTIMx Low-Power Timer instance

+  * @param  Waveform This parameter can be one of the following values:

+  *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM

+  *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE

+  * @param  Polarity This parameter can be one of the following values:

+  *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR

+  *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_ConfigOutput(LPTIM_TypeDef *LPTIMx, uint32_t Waveform, uint32_t Polarity)

+{

+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE | LPTIM_CFGR_WAVPOL, Waveform | Polarity);

+}

+

+/**

+  * @brief  Set  waveform shape

+  * @rmtoll CFGR         WAVE          LL_LPTIM_SetWaveform

+  * @param  LPTIMx Low-Power Timer instance

+  * @param  Waveform This parameter can be one of the following values:

+  *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM

+  *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_SetWaveform(LPTIM_TypeDef *LPTIMx, uint32_t Waveform)

+{

+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVE, Waveform);

+}

+

+/**

+  * @brief  Get actual waveform shape

+  * @rmtoll CFGR         WAVE          LL_LPTIM_GetWaveform

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_PWM

+  *         @arg @ref LL_LPTIM_OUTPUT_WAVEFORM_SETONCE

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_GetWaveform(LPTIM_TypeDef *LPTIMx)

+{

+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVE));

+}

+

+/**

+  * @brief  Set  output polarity

+  * @rmtoll CFGR         WAVPOL        LL_LPTIM_SetPolarity

+  * @param  LPTIMx Low-Power Timer instance

+  * @param  Polarity This parameter can be one of the following values:

+  *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR

+  *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_SetPolarity(LPTIM_TypeDef *LPTIMx, uint32_t Polarity)

+{

+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL, Polarity);

+}

+

+/**

+  * @brief  Get actual output polarity

+  * @rmtoll CFGR         WAVPOL        LL_LPTIM_GetPolarity

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_REGULAR

+  *         @arg @ref LL_LPTIM_OUTPUT_POLARITY_INVERSE

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_GetPolarity(LPTIM_TypeDef *LPTIMx)

+{

+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_WAVPOL));

+}

+

+/**

+  * @brief  Set actual prescaler division ratio.

+  * @note This function must be called when the LPTIM instance is disabled.

+  * @note When the LPTIM is configured to be clocked by an internal clock source

+  *       and the LPTIM counter is configured to be updated by active edges

+  *       detected on the LPTIM external Input1, the internal clock provided to

+  *       the LPTIM must be not be prescaled.

+  * @rmtoll CFGR         PRESC         LL_LPTIM_SetPrescaler

+  * @param  LPTIMx Low-Power Timer instance

+  * @param  Prescaler This parameter can be one of the following values:

+  *         @arg @ref LL_LPTIM_PRESCALER_DIV1

+  *         @arg @ref LL_LPTIM_PRESCALER_DIV2

+  *         @arg @ref LL_LPTIM_PRESCALER_DIV4

+  *         @arg @ref LL_LPTIM_PRESCALER_DIV8

+  *         @arg @ref LL_LPTIM_PRESCALER_DIV16

+  *         @arg @ref LL_LPTIM_PRESCALER_DIV32

+  *         @arg @ref LL_LPTIM_PRESCALER_DIV64

+  *         @arg @ref LL_LPTIM_PRESCALER_DIV128

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_SetPrescaler(LPTIM_TypeDef *LPTIMx, uint32_t Prescaler)

+{

+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_PRESC, Prescaler);

+}

+

+/**

+  * @brief  Get actual prescaler division ratio.

+  * @rmtoll CFGR         PRESC         LL_LPTIM_GetPrescaler

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_LPTIM_PRESCALER_DIV1

+  *         @arg @ref LL_LPTIM_PRESCALER_DIV2

+  *         @arg @ref LL_LPTIM_PRESCALER_DIV4

+  *         @arg @ref LL_LPTIM_PRESCALER_DIV8

+  *         @arg @ref LL_LPTIM_PRESCALER_DIV16

+  *         @arg @ref LL_LPTIM_PRESCALER_DIV32

+  *         @arg @ref LL_LPTIM_PRESCALER_DIV64

+  *         @arg @ref LL_LPTIM_PRESCALER_DIV128

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_GetPrescaler(LPTIM_TypeDef *LPTIMx)

+{

+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_PRESC));

+}

+

+/**

+  * @brief  Set LPTIM input 1 source (default GPIO).

+  * @rmtoll CFGR2      IN1SEL       LL_LPTIM_SetInput1Src

+  * @param  LPTIMx Low-Power Timer instance

+  * @param  Src This parameter can be one of the following values:

+  *         @arg @ref LL_LPTIM_INPUT1_SRC_GPIO

+  *         @arg @ref LL_LPTIM_INPUT1_SRC_COMP1

+  *         @arg @ref LL_LPTIM_INPUT1_SRC_COMP2

+  *         @arg @ref LL_LPTIM_INPUT1_SRC_COMP1_COMP2

+  *         @arg @ref LL_LPTIM_INPUT1_SRC_SAI4_FS_A

+  *         @arg @ref LL_LPTIM_INPUT1_SRC_SAI4_FS_B

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_SetInput1Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)

+{

+  MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN1SEL, Src);

+}

+

+/**

+  * @brief  Set LPTIM input 2 source (default GPIO).

+  * @rmtoll CFGR2      IN2SEL       LL_LPTIM_SetInput2Src

+  * @param  LPTIMx Low-Power Timer instance

+  * @param  Src This parameter can be one of the following values:

+  *         @arg @ref LL_LPTIM_INPUT2_SRC_GPIO

+  *         @arg @ref LL_LPTIM_INPUT2_SRC_COMP2

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_SetInput2Src(LPTIM_TypeDef *LPTIMx, uint32_t Src)

+{

+  MODIFY_REG(LPTIMx->CFGR2, LPTIM_CFGR2_IN2SEL, Src);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_LL_EF_Trigger_Configuration Trigger Configuration

+  * @{

+  */

+

+/**

+  * @brief  Enable the timeout function

+  * @note This function must be called when the LPTIM instance is disabled.

+  * @note The first trigger event will start the timer, any successive trigger

+  *       event will reset the counter and the timer will restart.

+  * @note The timeout value corresponds to the compare value; if no trigger

+  *       occurs within the expected time frame, the MCU is waked-up by the

+  *       compare match event.

+  * @rmtoll CFGR         TIMOUT        LL_LPTIM_EnableTimeout

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_EnableTimeout(LPTIM_TypeDef *LPTIMx)

+{

+  SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);

+}

+

+/**

+  * @brief  Disable the timeout function

+  * @note This function must be called when the LPTIM instance is disabled.

+  * @note A trigger event arriving when the timer is already started will be

+  *       ignored.

+  * @rmtoll CFGR         TIMOUT        LL_LPTIM_DisableTimeout

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_DisableTimeout(LPTIM_TypeDef *LPTIMx)

+{

+  CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT);

+}

+

+/**

+  * @brief  Indicate whether the timeout function is enabled.

+  * @rmtoll CFGR         TIMOUT        LL_LPTIM_IsEnabledTimeout

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledTimeout(LPTIM_TypeDef *LPTIMx)

+{

+  return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TIMOUT) == LPTIM_CFGR_TIMOUT) ? 1UL : 0UL));

+}

+

+/**

+  * @brief  Start the LPTIM counter

+  * @note This function must be called when the LPTIM instance is disabled.

+  * @rmtoll CFGR         TRIGEN        LL_LPTIM_TrigSw

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_TrigSw(LPTIM_TypeDef *LPTIMx)

+{

+  CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN);

+}

+

+/**

+  * @brief  Configure the external trigger used as a trigger event for the LPTIM.

+  * @note This function must be called when the LPTIM instance is disabled.

+  * @note An internal clock source must be present when a digital filter is

+  *       required for the trigger.

+  * @rmtoll CFGR         TRIGSEL       LL_LPTIM_ConfigTrigger\n

+  *         CFGR         TRGFLT        LL_LPTIM_ConfigTrigger\n

+  *         CFGR         TRIGEN        LL_LPTIM_ConfigTrigger

+  * @param  LPTIMx Low-Power Timer instance

+  * @param  Source This parameter can be one of the following values:

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM2     (*)

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM3     (*)

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM4     (*)

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM5     (*)

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1_FS_A  (*)

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1_FS_B  (*)

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_A  (*)

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_B  (*)

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_SAI4_FS_A  (*)

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_SAI4_FS_B  (*)

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_DFSDM2_BRK (*)

+  *

+  *         (*)  Value not defined in all devices. \n

+  *

+  * @param  Filter This parameter can be one of the following values:

+  *         @arg @ref LL_LPTIM_TRIG_FILTER_NONE

+  *         @arg @ref LL_LPTIM_TRIG_FILTER_2

+  *         @arg @ref LL_LPTIM_TRIG_FILTER_4

+  *         @arg @ref LL_LPTIM_TRIG_FILTER_8

+  * @param  Polarity This parameter can be one of the following values:

+  *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING

+  *         @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING

+  *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_ConfigTrigger(LPTIM_TypeDef *LPTIMx, uint32_t Source, uint32_t Filter, uint32_t Polarity)

+{

+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL | LPTIM_CFGR_TRGFLT | LPTIM_CFGR_TRIGEN, Source | Filter | Polarity);

+}

+

+/**

+  * @brief  Get actual external trigger source.

+  * @rmtoll CFGR         TRIGSEL       LL_LPTIM_GetTriggerSource

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_GPIO

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMA

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCALARMB

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP1

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP2

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_RTCTAMP3

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP1

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_COMP2

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM2     (*)

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM3     (*)

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM4     (*)

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_LPTIM5     (*)

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1_FS_A  (*)

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_SAI1_FS_B  (*)

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_A  (*)

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_SAI2_FS_B  (*)

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_SAI4_FS_A  (*)

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_SAI4_FS_B  (*)

+  *         @arg @ref LL_LPTIM_TRIG_SOURCE_DFSDM2_BRK (*)

+  *

+  *         (*)  Value not defined in all devices. \n

+  *

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerSource(LPTIM_TypeDef *LPTIMx)

+{

+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGSEL));

+}

+

+/**

+  * @brief  Get actual external trigger filter.

+  * @rmtoll CFGR         TRGFLT        LL_LPTIM_GetTriggerFilter

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_LPTIM_TRIG_FILTER_NONE

+  *         @arg @ref LL_LPTIM_TRIG_FILTER_2

+  *         @arg @ref LL_LPTIM_TRIG_FILTER_4

+  *         @arg @ref LL_LPTIM_TRIG_FILTER_8

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerFilter(LPTIM_TypeDef *LPTIMx)

+{

+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRGFLT));

+}

+

+/**

+  * @brief  Get actual external trigger polarity.

+  * @rmtoll CFGR         TRIGEN        LL_LPTIM_GetTriggerPolarity

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING

+  *         @arg @ref LL_LPTIM_TRIG_POLARITY_FALLING

+  *         @arg @ref LL_LPTIM_TRIG_POLARITY_RISING_FALLING

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_GetTriggerPolarity(LPTIM_TypeDef *LPTIMx)

+{

+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_TRIGEN));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_LL_EF_Clock_Configuration Clock Configuration

+  * @{

+  */

+

+/**

+  * @brief  Set the source of the clock used by the LPTIM instance.

+  * @note This function must be called when the LPTIM instance is disabled.

+  * @rmtoll CFGR         CKSEL         LL_LPTIM_SetClockSource

+  * @param  LPTIMx Low-Power Timer instance

+  * @param  ClockSource This parameter can be one of the following values:

+  *         @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL

+  *         @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_SetClockSource(LPTIM_TypeDef *LPTIMx, uint32_t ClockSource)

+{

+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKSEL, ClockSource);

+}

+

+/**

+  * @brief  Get actual LPTIM instance clock source.

+  * @rmtoll CFGR         CKSEL         LL_LPTIM_GetClockSource

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_LPTIM_CLK_SOURCE_INTERNAL

+  *         @arg @ref LL_LPTIM_CLK_SOURCE_EXTERNAL

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_GetClockSource(LPTIM_TypeDef *LPTIMx)

+{

+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKSEL));

+}

+

+/**

+  * @brief  Configure the active edge or edges used by the counter when the LPTIM is clocked by an external clock source.

+  * @note This function must be called when the LPTIM instance is disabled.

+  * @note When both external clock signal edges are considered active ones,

+  *       the LPTIM must also be clocked by an internal clock source with a

+  *       frequency equal to at least four times the external clock frequency.

+  * @note An internal clock source must be present when a digital filter is

+  *       required for external clock.

+  * @rmtoll CFGR         CKFLT         LL_LPTIM_ConfigClock\n

+  *         CFGR         CKPOL         LL_LPTIM_ConfigClock

+  * @param  LPTIMx Low-Power Timer instance

+  * @param  ClockFilter This parameter can be one of the following values:

+  *         @arg @ref LL_LPTIM_CLK_FILTER_NONE

+  *         @arg @ref LL_LPTIM_CLK_FILTER_2

+  *         @arg @ref LL_LPTIM_CLK_FILTER_4

+  *         @arg @ref LL_LPTIM_CLK_FILTER_8

+  * @param  ClockPolarity This parameter can be one of the following values:

+  *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING

+  *         @arg @ref LL_LPTIM_CLK_POLARITY_FALLING

+  *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_ConfigClock(LPTIM_TypeDef *LPTIMx, uint32_t ClockFilter, uint32_t ClockPolarity)

+{

+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKFLT | LPTIM_CFGR_CKPOL, ClockFilter | ClockPolarity);

+}

+

+/**

+  * @brief  Get actual clock polarity

+  * @rmtoll CFGR         CKPOL         LL_LPTIM_GetClockPolarity

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING

+  *         @arg @ref LL_LPTIM_CLK_POLARITY_FALLING

+  *         @arg @ref LL_LPTIM_CLK_POLARITY_RISING_FALLING

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_GetClockPolarity(LPTIM_TypeDef *LPTIMx)

+{

+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));

+}

+

+/**

+  * @brief  Get actual clock digital filter

+  * @rmtoll CFGR         CKFLT         LL_LPTIM_GetClockFilter

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_LPTIM_CLK_FILTER_NONE

+  *         @arg @ref LL_LPTIM_CLK_FILTER_2

+  *         @arg @ref LL_LPTIM_CLK_FILTER_4

+  *         @arg @ref LL_LPTIM_CLK_FILTER_8

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_GetClockFilter(LPTIM_TypeDef *LPTIMx)

+{

+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKFLT));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_LL_EF_Encoder_Mode Encoder Mode

+  * @{

+  */

+

+/**

+  * @brief  Configure the encoder mode.

+  * @note This function must be called when the LPTIM instance is disabled.

+  * @rmtoll CFGR         CKPOL         LL_LPTIM_SetEncoderMode

+  * @param  LPTIMx Low-Power Timer instance

+  * @param  EncoderMode This parameter can be one of the following values:

+  *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING

+  *         @arg @ref LL_LPTIM_ENCODER_MODE_FALLING

+  *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_SetEncoderMode(LPTIM_TypeDef *LPTIMx, uint32_t EncoderMode)

+{

+  MODIFY_REG(LPTIMx->CFGR, LPTIM_CFGR_CKPOL, EncoderMode);

+}

+

+/**

+  * @brief  Get actual encoder mode.

+  * @rmtoll CFGR         CKPOL         LL_LPTIM_GetEncoderMode

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING

+  *         @arg @ref LL_LPTIM_ENCODER_MODE_FALLING

+  *         @arg @ref LL_LPTIM_ENCODER_MODE_RISING_FALLING

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_GetEncoderMode(LPTIM_TypeDef *LPTIMx)

+{

+  return (uint32_t)(READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_CKPOL));

+}

+

+/**

+  * @brief  Enable the encoder mode

+  * @note This function must be called when the LPTIM instance is disabled.

+  * @note In this mode the LPTIM instance must be clocked by an internal clock

+  *       source. Also, the prescaler division ratio must be equal to 1.

+  * @note LPTIM instance must be configured in continuous mode prior enabling

+  *       the encoder mode.

+  * @rmtoll CFGR         ENC           LL_LPTIM_EnableEncoderMode

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_EnableEncoderMode(LPTIM_TypeDef *LPTIMx)

+{

+  SET_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);

+}

+

+/**

+  * @brief  Disable the encoder mode

+  * @note This function must be called when the LPTIM instance is disabled.

+  * @rmtoll CFGR         ENC           LL_LPTIM_DisableEncoderMode

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_DisableEncoderMode(LPTIM_TypeDef *LPTIMx)

+{

+  CLEAR_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC);

+}

+

+/**

+  * @brief  Indicates whether the LPTIM operates in encoder mode.

+  * @rmtoll CFGR         ENC           LL_LPTIM_IsEnabledEncoderMode

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledEncoderMode(LPTIM_TypeDef *LPTIMx)

+{

+  return (((READ_BIT(LPTIMx->CFGR, LPTIM_CFGR_ENC) == LPTIM_CFGR_ENC) ? 1UL : 0UL));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_LL_EF_FLAG_Management FLAG Management

+  * @{

+  */

+

+/**

+  * @brief  Clear the compare match flag (CMPMCF)

+  * @rmtoll ICR          CMPMCF        LL_LPTIM_ClearFLAG_CMPM

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_ClearFLAG_CMPM(LPTIM_TypeDef *LPTIMx)

+{

+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPMCF);

+}

+

+/**

+  * @brief  Inform application whether a compare match interrupt has occurred.

+  * @rmtoll ISR          CMPM          LL_LPTIM_IsActiveFlag_CMPM

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPM(LPTIM_TypeDef *LPTIMx)

+{

+  return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPM) == LPTIM_ISR_CMPM) ? 1UL : 0UL));

+}

+

+/**

+  * @brief  Clear the autoreload match flag (ARRMCF)

+  * @rmtoll ICR          ARRMCF        LL_LPTIM_ClearFLAG_ARRM

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_ClearFLAG_ARRM(LPTIM_TypeDef *LPTIMx)

+{

+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARRMCF);

+}

+

+/**

+  * @brief  Inform application whether a autoreload match interrupt has occurred.

+  * @rmtoll ISR          ARRM          LL_LPTIM_IsActiveFlag_ARRM

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARRM(LPTIM_TypeDef *LPTIMx)

+{

+  return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARRM) == LPTIM_ISR_ARRM) ? 1UL : 0UL));

+}

+

+/**

+  * @brief  Clear the external trigger valid edge flag(EXTTRIGCF).

+  * @rmtoll ICR          EXTTRIGCF     LL_LPTIM_ClearFlag_EXTTRIG

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_ClearFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)

+{

+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_EXTTRIGCF);

+}

+

+/**

+  * @brief  Inform application whether a valid edge on the selected external trigger input has occurred.

+  * @rmtoll ISR          EXTTRIG       LL_LPTIM_IsActiveFlag_EXTTRIG

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_EXTTRIG(LPTIM_TypeDef *LPTIMx)

+{

+  return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_EXTTRIG) == LPTIM_ISR_EXTTRIG) ? 1UL : 0UL));

+}

+

+/**

+  * @brief  Clear the compare register update interrupt flag (CMPOKCF).

+  * @rmtoll ICR          CMPOKCF       LL_LPTIM_ClearFlag_CMPOK

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_ClearFlag_CMPOK(LPTIM_TypeDef *LPTIMx)

+{

+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_CMPOKCF);

+}

+

+/**

+  * @brief  Informs application whether the APB bus write operation to the LPTIMx_CMP register has been successfully completed. If so, a new one can be initiated.

+  * @rmtoll ISR          CMPOK         LL_LPTIM_IsActiveFlag_CMPOK

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_CMPOK(LPTIM_TypeDef *LPTIMx)

+{

+  return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_CMPOK) == LPTIM_ISR_CMPOK) ? 1UL : 0UL));

+}

+

+/**

+  * @brief  Clear the autoreload register update interrupt flag (ARROKCF).

+  * @rmtoll ICR          ARROKCF       LL_LPTIM_ClearFlag_ARROK

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_ClearFlag_ARROK(LPTIM_TypeDef *LPTIMx)

+{

+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_ARROKCF);

+}

+

+/**

+  * @brief  Informs application whether the APB bus write operation to the LPTIMx_ARR register has been successfully completed. If so, a new one can be initiated.

+  * @rmtoll ISR          ARROK         LL_LPTIM_IsActiveFlag_ARROK

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_ARROK(LPTIM_TypeDef *LPTIMx)

+{

+  return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_ARROK) == LPTIM_ISR_ARROK) ? 1UL : 0UL));

+}

+

+/**

+  * @brief  Clear the counter direction change to up interrupt flag (UPCF).

+  * @rmtoll ICR          UPCF          LL_LPTIM_ClearFlag_UP

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_ClearFlag_UP(LPTIM_TypeDef *LPTIMx)

+{

+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_UPCF);

+}

+

+/**

+  * @brief  Informs the application whether the counter direction has changed from down to up (when the LPTIM instance operates in encoder mode).

+  * @rmtoll ISR          UP            LL_LPTIM_IsActiveFlag_UP

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_UP(LPTIM_TypeDef *LPTIMx)

+{

+  return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_UP) == LPTIM_ISR_UP) ? 1UL : 0UL));

+}

+

+/**

+  * @brief  Clear the counter direction change to down interrupt flag (DOWNCF).

+  * @rmtoll ICR          DOWNCF        LL_LPTIM_ClearFlag_DOWN

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_ClearFlag_DOWN(LPTIM_TypeDef *LPTIMx)

+{

+  SET_BIT(LPTIMx->ICR, LPTIM_ICR_DOWNCF);

+}

+

+/**

+  * @brief  Informs the application whether the counter direction has changed from up to down (when the LPTIM instance operates in encoder mode).

+  * @rmtoll ISR          DOWN          LL_LPTIM_IsActiveFlag_DOWN

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_IsActiveFlag_DOWN(LPTIM_TypeDef *LPTIMx)

+{

+  return (((READ_BIT(LPTIMx->ISR, LPTIM_ISR_DOWN) == LPTIM_ISR_DOWN) ? 1UL : 0UL));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup LPTIM_LL_EF_IT_Management Interrupt Management

+  * @{

+  */

+

+/**

+  * @brief  Enable compare match interrupt (CMPMIE).

+  * @rmtoll IER          CMPMIE        LL_LPTIM_EnableIT_CMPM

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_EnableIT_CMPM(LPTIM_TypeDef *LPTIMx)

+{

+  SET_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);

+}

+

+/**

+  * @brief  Disable compare match interrupt (CMPMIE).

+  * @rmtoll IER          CMPMIE        LL_LPTIM_DisableIT_CMPM

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_DisableIT_CMPM(LPTIM_TypeDef *LPTIMx)

+{

+  CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE);

+}

+

+/**

+  * @brief  Indicates whether the compare match interrupt (CMPMIE) is enabled.

+  * @rmtoll IER          CMPMIE        LL_LPTIM_IsEnabledIT_CMPM

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPM(LPTIM_TypeDef *LPTIMx)

+{

+  return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPMIE) == LPTIM_IER_CMPMIE) ? 1UL : 0UL));

+}

+

+/**

+  * @brief  Enable autoreload match interrupt (ARRMIE).

+  * @rmtoll IER          ARRMIE        LL_LPTIM_EnableIT_ARRM

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_EnableIT_ARRM(LPTIM_TypeDef *LPTIMx)

+{

+  SET_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);

+}

+

+/**

+  * @brief  Disable autoreload match interrupt (ARRMIE).

+  * @rmtoll IER          ARRMIE        LL_LPTIM_DisableIT_ARRM

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_DisableIT_ARRM(LPTIM_TypeDef *LPTIMx)

+{

+  CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE);

+}

+

+/**

+  * @brief  Indicates whether the autoreload match interrupt (ARRMIE) is enabled.

+  * @rmtoll IER          ARRMIE        LL_LPTIM_IsEnabledIT_ARRM

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARRM(LPTIM_TypeDef *LPTIMx)

+{

+  return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARRMIE) == LPTIM_IER_ARRMIE) ? 1UL : 0UL));

+}

+

+/**

+  * @brief  Enable external trigger valid edge interrupt (EXTTRIGIE).

+  * @rmtoll IER          EXTTRIGIE     LL_LPTIM_EnableIT_EXTTRIG

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_EnableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)

+{

+  SET_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);

+}

+

+/**

+  * @brief  Disable external trigger valid edge interrupt (EXTTRIGIE).

+  * @rmtoll IER          EXTTRIGIE     LL_LPTIM_DisableIT_EXTTRIG

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_DisableIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)

+{

+  CLEAR_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE);

+}

+

+/**

+  * @brief  Indicates external trigger valid edge interrupt (EXTTRIGIE) is enabled.

+  * @rmtoll IER          EXTTRIGIE     LL_LPTIM_IsEnabledIT_EXTTRIG

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_EXTTRIG(LPTIM_TypeDef *LPTIMx)

+{

+  return (((READ_BIT(LPTIMx->IER, LPTIM_IER_EXTTRIGIE) == LPTIM_IER_EXTTRIGIE) ? 1UL : 0UL));

+}

+

+/**

+  * @brief  Enable compare register write completed interrupt (CMPOKIE).

+  * @rmtoll IER          CMPOKIE       LL_LPTIM_EnableIT_CMPOK

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_EnableIT_CMPOK(LPTIM_TypeDef *LPTIMx)

+{

+  SET_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);

+}

+

+/**

+  * @brief  Disable compare register write completed interrupt (CMPOKIE).

+  * @rmtoll IER          CMPOKIE       LL_LPTIM_DisableIT_CMPOK

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_DisableIT_CMPOK(LPTIM_TypeDef *LPTIMx)

+{

+  CLEAR_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE);

+}

+

+/**

+  * @brief  Indicates whether the compare register write completed interrupt (CMPOKIE) is enabled.

+  * @rmtoll IER          CMPOKIE       LL_LPTIM_IsEnabledIT_CMPOK

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_CMPOK(LPTIM_TypeDef *LPTIMx)

+{

+  return (((READ_BIT(LPTIMx->IER, LPTIM_IER_CMPOKIE) == LPTIM_IER_CMPOKIE) ? 1UL : 0UL));

+}

+

+/**

+  * @brief  Enable autoreload register write completed interrupt (ARROKIE).

+  * @rmtoll IER          ARROKIE       LL_LPTIM_EnableIT_ARROK

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_EnableIT_ARROK(LPTIM_TypeDef *LPTIMx)

+{

+  SET_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);

+}

+

+/**

+  * @brief  Disable autoreload register write completed interrupt (ARROKIE).

+  * @rmtoll IER          ARROKIE       LL_LPTIM_DisableIT_ARROK

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_DisableIT_ARROK(LPTIM_TypeDef *LPTIMx)

+{

+  CLEAR_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE);

+}

+

+/**

+  * @brief  Indicates whether the autoreload register write completed interrupt (ARROKIE) is enabled.

+  * @rmtoll IER          ARROKIE       LL_LPTIM_IsEnabledIT_ARROK

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval State of bit(1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_ARROK(LPTIM_TypeDef *LPTIMx)

+{

+  return (((READ_BIT(LPTIMx->IER, LPTIM_IER_ARROKIE) == LPTIM_IER_ARROKIE) ? 1UL : 0UL));

+}

+

+/**

+  * @brief  Enable direction change to up interrupt (UPIE).

+  * @rmtoll IER          UPIE          LL_LPTIM_EnableIT_UP

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_EnableIT_UP(LPTIM_TypeDef *LPTIMx)

+{

+  SET_BIT(LPTIMx->IER, LPTIM_IER_UPIE);

+}

+

+/**

+  * @brief  Disable direction change to up interrupt (UPIE).

+  * @rmtoll IER          UPIE          LL_LPTIM_DisableIT_UP

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_DisableIT_UP(LPTIM_TypeDef *LPTIMx)

+{

+  CLEAR_BIT(LPTIMx->IER, LPTIM_IER_UPIE);

+}

+

+/**

+  * @brief  Indicates whether the direction change to up interrupt (UPIE) is enabled.

+  * @rmtoll IER          UPIE          LL_LPTIM_IsEnabledIT_UP

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval State of bit(1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_UP(LPTIM_TypeDef *LPTIMx)

+{

+  return (((READ_BIT(LPTIMx->IER, LPTIM_IER_UPIE) == LPTIM_IER_UPIE) ? 1UL : 0UL));

+}

+

+/**

+  * @brief  Enable direction change to down interrupt (DOWNIE).

+  * @rmtoll IER          DOWNIE        LL_LPTIM_EnableIT_DOWN

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_EnableIT_DOWN(LPTIM_TypeDef *LPTIMx)

+{

+  SET_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);

+}

+

+/**

+  * @brief  Disable direction change to down interrupt (DOWNIE).

+  * @rmtoll IER          DOWNIE        LL_LPTIM_DisableIT_DOWN

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPTIM_DisableIT_DOWN(LPTIM_TypeDef *LPTIMx)

+{

+  CLEAR_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE);

+}

+

+/**

+  * @brief  Indicates whether the direction change to down interrupt (DOWNIE) is enabled.

+  * @rmtoll IER          DOWNIE        LL_LPTIM_IsEnabledIT_DOWN

+  * @param  LPTIMx Low-Power Timer instance

+  * @retval State of bit(1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPTIM_IsEnabledIT_DOWN(LPTIM_TypeDef *LPTIMx)

+{

+  return ((READ_BIT(LPTIMx->IER, LPTIM_IER_DOWNIE) == LPTIM_IER_DOWNIE) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* LPTIM1 || LPTIM2 ||  LPTIM3 || LPTIM4 || LPTIM5 */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_LL_LPTIM_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_lpuart.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_lpuart.h
new file mode 100644
index 0000000000..172f96cfe0
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_lpuart.h
@@ -0,0 +1,2634 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_lpuart.h

+  * @author  MCD Application Team

+  * @brief   Header file of LPUART LL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_LL_LPUART_H

+#define STM32H7xx_LL_LPUART_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+#if defined (LPUART1)

+

+/** @defgroup LPUART_LL LPUART

+  * @{

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/** @defgroup LPUART_LL_Private_Variables LPUART Private Variables

+  * @{

+  */

+/* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */

+static const uint16_t LPUART_PRESCALER_TAB[] =

+{

+  (uint16_t)1,

+  (uint16_t)2,

+  (uint16_t)4,

+  (uint16_t)6,

+  (uint16_t)8,

+  (uint16_t)10,

+  (uint16_t)12,

+  (uint16_t)16,

+  (uint16_t)32,

+  (uint16_t)64,

+  (uint16_t)128,

+  (uint16_t)256

+};

+/**

+  * @}

+  */

+

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup LPUART_LL_Private_Constants LPUART Private Constants

+  * @{

+  */

+/* Defines used in Baud Rate related macros and corresponding register setting computation */

+#define LPUART_LPUARTDIV_FREQ_MUL     256U

+#define LPUART_BRR_MASK               0x000FFFFFU

+#define LPUART_BRR_MIN_VALUE          0x00000300U

+/**

+  * @}

+  */

+

+

+/* Private macros ------------------------------------------------------------*/

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup LPUART_LL_Private_Macros LPUART Private Macros

+  * @{

+  */

+/**

+  * @}

+  */

+#endif /*USE_FULL_LL_DRIVER*/

+

+/* Exported types ------------------------------------------------------------*/

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures

+  * @{

+  */

+

+/**

+  * @brief LL LPUART Init Structure definition

+  */

+typedef struct

+{

+  uint32_t PrescalerValue;            /*!< Specifies the Prescaler to compute the communication baud rate.

+                                           This parameter can be a value of @ref LPUART_LL_EC_PRESCALER.

+

+                                           This feature can be modified afterwards using unitary function @ref LL_LPUART_SetPrescaler().*/

+

+  uint32_t BaudRate;                  /*!< This field defines expected LPUART communication baud rate.

+

+                                           This feature can be modified afterwards using unitary function @ref LL_LPUART_SetBaudRate().*/

+

+  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.

+                                           This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH.

+

+                                           This feature can be modified afterwards using unitary function @ref LL_LPUART_SetDataWidth().*/

+

+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.

+                                           This parameter can be a value of @ref LPUART_LL_EC_STOPBITS.

+

+                                           This feature can be modified afterwards using unitary function @ref LL_LPUART_SetStopBitsLength().*/

+

+  uint32_t Parity;                    /*!< Specifies the parity mode.

+                                           This parameter can be a value of @ref LPUART_LL_EC_PARITY.

+

+                                           This feature can be modified afterwards using unitary function @ref LL_LPUART_SetParity().*/

+

+  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.

+                                           This parameter can be a value of @ref LPUART_LL_EC_DIRECTION.

+

+                                           This feature can be modified afterwards using unitary function @ref LL_LPUART_SetTransferDirection().*/

+

+  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.

+                                           This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL.

+

+                                           This feature can be modified afterwards using unitary function @ref LL_LPUART_SetHWFlowCtrl().*/

+

+} LL_LPUART_InitTypeDef;

+

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants

+  * @{

+  */

+

+/** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines

+  * @brief    Flags defines which can be used with LL_LPUART_WriteReg function

+  * @{

+  */

+#define LL_LPUART_ICR_PECF                 USART_ICR_PECF                /*!< Parity error flag */

+#define LL_LPUART_ICR_FECF                 USART_ICR_FECF                /*!< Framing error flag */

+#define LL_LPUART_ICR_NCF                  USART_ICR_NECF                /*!< Noise error detected flag */

+#define LL_LPUART_ICR_ORECF                USART_ICR_ORECF               /*!< Overrun error flag */

+#define LL_LPUART_ICR_IDLECF               USART_ICR_IDLECF              /*!< Idle line detected flag */

+#define LL_LPUART_ICR_TXFECF               USART_ICR_TXFECF              /*!< TX FIFO Empty Clear flag */

+#define LL_LPUART_ICR_TCCF                 USART_ICR_TCCF                /*!< Transmission complete flag */

+#define LL_LPUART_ICR_CTSCF                USART_ICR_CTSCF               /*!< CTS flag */

+#define LL_LPUART_ICR_CMCF                 USART_ICR_CMCF                /*!< Character match flag */

+#define LL_LPUART_ICR_WUCF                 USART_ICR_WUCF                /*!< Wakeup from Stop mode flag */

+/**

+  * @}

+  */

+

+/** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines

+  * @brief    Flags defines which can be used with LL_LPUART_ReadReg function

+  * @{

+  */

+#define LL_LPUART_ISR_PE                   USART_ISR_PE                  /*!< Parity error flag */

+#define LL_LPUART_ISR_FE                   USART_ISR_FE                  /*!< Framing error flag */

+#define LL_LPUART_ISR_NE                   USART_ISR_NE                  /*!< Noise detected flag */

+#define LL_LPUART_ISR_ORE                  USART_ISR_ORE                 /*!< Overrun error flag */

+#define LL_LPUART_ISR_IDLE                 USART_ISR_IDLE                /*!< Idle line detected flag */

+#define LL_LPUART_ISR_RXNE_RXFNE           USART_ISR_RXNE_RXFNE          /*!< Read data register or RX FIFO not empty flag */

+#define LL_LPUART_ISR_TC                   USART_ISR_TC                  /*!< Transmission complete flag */

+#define LL_LPUART_ISR_TXE_TXFNF            USART_ISR_TXE_TXFNF           /*!< Transmit data register empty or TX FIFO Not Full flag*/

+#define LL_LPUART_ISR_CTSIF                USART_ISR_CTSIF               /*!< CTS interrupt flag */

+#define LL_LPUART_ISR_CTS                  USART_ISR_CTS                 /*!< CTS flag */

+#define LL_LPUART_ISR_BUSY                 USART_ISR_BUSY                /*!< Busy flag */

+#define LL_LPUART_ISR_CMF                  USART_ISR_CMF                 /*!< Character match flag */

+#define LL_LPUART_ISR_SBKF                 USART_ISR_SBKF                /*!< Send break flag */

+#define LL_LPUART_ISR_RWU                  USART_ISR_RWU                 /*!< Receiver wakeup from Mute mode flag */

+#define LL_LPUART_ISR_WUF                  USART_ISR_WUF                 /*!< Wakeup from Stop mode flag */

+#define LL_LPUART_ISR_TEACK                USART_ISR_TEACK               /*!< Transmit enable acknowledge flag */

+#define LL_LPUART_ISR_REACK                USART_ISR_REACK               /*!< Receive enable acknowledge flag */

+#define LL_LPUART_ISR_TXFE                 USART_ISR_TXFE                /*!< TX FIFO empty flag */

+#define LL_LPUART_ISR_RXFF                 USART_ISR_RXFF                /*!< RX FIFO full flag */

+#define LL_LPUART_ISR_RXFT                 USART_ISR_RXFT                /*!< RX FIFO threshold flag */

+#define LL_LPUART_ISR_TXFT                 USART_ISR_TXFT                /*!< TX FIFO threshold flag */

+/**

+  * @}

+  */

+

+/** @defgroup LPUART_LL_EC_IT IT Defines

+  * @brief    IT defines which can be used with LL_LPUART_ReadReg and  LL_LPUART_WriteReg functions

+  * @{

+  */

+#define LL_LPUART_CR1_IDLEIE               USART_CR1_IDLEIE              /*!< IDLE interrupt enable */

+#define LL_LPUART_CR1_RXNEIE_RXFNEIE       USART_CR1_RXNEIE_RXFNEIE      /*!< Read data register and RXFIFO not empty interrupt enable */

+#define LL_LPUART_CR1_TCIE                 USART_CR1_TCIE                /*!< Transmission complete interrupt enable */

+#define LL_LPUART_CR1_TXEIE_TXFNFIE        USART_CR1_TXEIE_TXFNFIE       /*!< Transmit data register empty and TX FIFO not full interrupt enable */

+#define LL_LPUART_CR1_PEIE                 USART_CR1_PEIE                /*!< Parity error */

+#define LL_LPUART_CR1_CMIE                 USART_CR1_CMIE                /*!< Character match interrupt enable */

+#define LL_LPUART_CR1_TXFEIE               USART_CR1_TXFEIE              /*!< TX FIFO empty interrupt enable */

+#define LL_LPUART_CR1_RXFFIE               USART_CR1_RXFFIE              /*!< RX FIFO full interrupt enable */

+#define LL_LPUART_CR3_EIE                  USART_CR3_EIE                 /*!< Error interrupt enable */

+#define LL_LPUART_CR3_CTSIE                USART_CR3_CTSIE               /*!< CTS interrupt enable */

+#define LL_LPUART_CR3_WUFIE                USART_CR3_WUFIE               /*!< Wakeup from Stop mode interrupt enable */

+#define LL_LPUART_CR3_TXFTIE               USART_CR3_TXFTIE              /*!< TX FIFO threshold interrupt enable */

+#define LL_LPUART_CR3_RXFTIE               USART_CR3_RXFTIE              /*!< RX FIFO threshold interrupt enable */

+/**

+  * @}

+  */

+

+/** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold

+  * @{

+  */

+#define LL_LPUART_FIFOTHRESHOLD_1_8        0x00000000U /*!< FIFO reaches 1/8 of its depth */

+#define LL_LPUART_FIFOTHRESHOLD_1_4        0x00000001U /*!< FIFO reaches 1/4 of its depth */

+#define LL_LPUART_FIFOTHRESHOLD_1_2        0x00000002U /*!< FIFO reaches 1/2 of its depth */

+#define LL_LPUART_FIFOTHRESHOLD_3_4        0x00000003U /*!< FIFO reaches 3/4 of its depth */

+#define LL_LPUART_FIFOTHRESHOLD_7_8        0x00000004U /*!< FIFO reaches 7/8 of its depth */

+#define LL_LPUART_FIFOTHRESHOLD_8_8        0x00000005U /*!< FIFO becomes empty for TX and full for RX */

+/**

+  * @}

+  */

+

+/** @defgroup LPUART_LL_EC_DIRECTION Direction

+  * @{

+  */

+#define LL_LPUART_DIRECTION_NONE           0x00000000U                        /*!< Transmitter and Receiver are disabled */

+#define LL_LPUART_DIRECTION_RX             USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */

+#define LL_LPUART_DIRECTION_TX             USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */

+#define LL_LPUART_DIRECTION_TX_RX          (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */

+/**

+  * @}

+  */

+

+/** @defgroup LPUART_LL_EC_PARITY Parity Control

+  * @{

+  */

+#define LL_LPUART_PARITY_NONE              0x00000000U                        /*!< Parity control disabled */

+#define LL_LPUART_PARITY_EVEN              USART_CR1_PCE                      /*!< Parity control enabled and Even Parity is selected */

+#define LL_LPUART_PARITY_ODD               (USART_CR1_PCE | USART_CR1_PS)     /*!< Parity control enabled and Odd Parity is selected */

+/**

+  * @}

+  */

+

+/** @defgroup LPUART_LL_EC_WAKEUP Wakeup

+  * @{

+  */

+#define LL_LPUART_WAKEUP_IDLELINE          0x00000000U                        /*!<  LPUART wake up from Mute mode on Idle Line */

+#define LL_LPUART_WAKEUP_ADDRESSMARK       USART_CR1_WAKE                     /*!<  LPUART wake up from Mute mode on Address Mark */

+/**

+  * @}

+  */

+

+/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth

+  * @{

+  */

+#define LL_LPUART_DATAWIDTH_7B             USART_CR1_M1                       /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */

+#define LL_LPUART_DATAWIDTH_8B             0x00000000U                        /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */

+#define LL_LPUART_DATAWIDTH_9B             USART_CR1_M0                       /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */

+/**

+  * @}

+  */

+

+/** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler

+  * @{

+  */

+#define LL_LPUART_PRESCALER_DIV1           0x00000000U                                                                   /*!< Input clock not devided   */

+#define LL_LPUART_PRESCALER_DIV2           (USART_PRESC_PRESCALER_0)                                                     /*!< Input clock devided by 2  */

+#define LL_LPUART_PRESCALER_DIV4           (USART_PRESC_PRESCALER_1)                                                     /*!< Input clock devided by 4  */

+#define LL_LPUART_PRESCALER_DIV6           (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 6  */

+#define LL_LPUART_PRESCALER_DIV8           (USART_PRESC_PRESCALER_2)                                                     /*!< Input clock devided by 8  */

+#define LL_LPUART_PRESCALER_DIV10          (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 10 */

+#define LL_LPUART_PRESCALER_DIV12          (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)                           /*!< Input clock devided by 12 */

+#define LL_LPUART_PRESCALER_DIV16          (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 16 */

+#define LL_LPUART_PRESCALER_DIV32          (USART_PRESC_PRESCALER_3)                                                     /*!< Input clock devided by 32 */

+#define LL_LPUART_PRESCALER_DIV64          (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 64 */

+#define LL_LPUART_PRESCALER_DIV128         (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)                           /*!< Input clock devided by 128 */

+#define LL_LPUART_PRESCALER_DIV256         (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 256 */

+/**

+  * @}

+  */

+

+/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits

+  * @{

+  */

+#define LL_LPUART_STOPBITS_1               0x00000000U                        /*!< 1 stop bit */

+#define LL_LPUART_STOPBITS_2               USART_CR2_STOP_1                   /*!< 2 stop bits */

+/**

+  * @}

+  */

+

+/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap

+  * @{

+  */

+#define LL_LPUART_TXRX_STANDARD            0x00000000U                        /*!< TX/RX pins are used as defined in standard pinout */

+#define LL_LPUART_TXRX_SWAPPED             (USART_CR2_SWAP)                   /*!< TX and RX pins functions are swapped.             */

+/**

+  * @}

+  */

+

+/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion

+  * @{

+  */

+#define LL_LPUART_RXPIN_LEVEL_STANDARD     0x00000000U                        /*!< RX pin signal works using the standard logic levels */

+#define LL_LPUART_RXPIN_LEVEL_INVERTED     (USART_CR2_RXINV)                  /*!< RX pin signal values are inverted.                  */

+/**

+  * @}

+  */

+

+/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion

+  * @{

+  */

+#define LL_LPUART_TXPIN_LEVEL_STANDARD     0x00000000U                        /*!< TX pin signal works using the standard logic levels */

+#define LL_LPUART_TXPIN_LEVEL_INVERTED     (USART_CR2_TXINV)                  /*!< TX pin signal values are inverted.                  */

+/**

+  * @}

+  */

+

+/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion

+  * @{

+  */

+#define LL_LPUART_BINARY_LOGIC_POSITIVE    0x00000000U                        /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */

+#define LL_LPUART_BINARY_LOGIC_NEGATIVE    USART_CR2_DATAINV                  /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */

+/**

+  * @}

+  */

+

+/** @defgroup LPUART_LL_EC_BITORDER Bit Order

+  * @{

+  */

+#define LL_LPUART_BITORDER_LSBFIRST        0x00000000U                        /*!< data is transmitted/received with data bit 0 first, following the start bit */

+#define LL_LPUART_BITORDER_MSBFIRST        USART_CR2_MSBFIRST                 /*!< data is transmitted/received with the MSB first, following the start bit */

+/**

+  * @}

+  */

+

+/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection

+  * @{

+  */

+#define LL_LPUART_ADDRESS_DETECT_4B        0x00000000U                        /*!< 4-bit address detection method selected */

+#define LL_LPUART_ADDRESS_DETECT_7B        USART_CR2_ADDM7                    /*!< 7-bit address detection (in 8-bit data mode) method selected */

+/**

+  * @}

+  */

+

+/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control

+  * @{

+  */

+#define LL_LPUART_HWCONTROL_NONE           0x00000000U                        /*!< CTS and RTS hardware flow control disabled */

+#define LL_LPUART_HWCONTROL_RTS            USART_CR3_RTSE                     /*!< RTS output enabled, data is only requested when there is space in the receive buffer */

+#define LL_LPUART_HWCONTROL_CTS            USART_CR3_CTSE                     /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */

+#define LL_LPUART_HWCONTROL_RTS_CTS        (USART_CR3_RTSE | USART_CR3_CTSE)  /*!< CTS and RTS hardware flow control enabled */

+/**

+  * @}

+  */

+

+/** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation

+  * @{

+  */

+#define LL_LPUART_WAKEUP_ON_ADDRESS        0x00000000U                             /*!< Wake up active on address match */

+#define LL_LPUART_WAKEUP_ON_STARTBIT       USART_CR3_WUS_1                         /*!< Wake up active on Start bit detection */

+#define LL_LPUART_WAKEUP_ON_RXNE           (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake up active on RXNE */

+/**

+  * @}

+  */

+

+/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity

+  * @{

+  */

+#define LL_LPUART_DE_POLARITY_HIGH         0x00000000U                        /*!< DE signal is active high */

+#define LL_LPUART_DE_POLARITY_LOW          USART_CR3_DEP                      /*!< DE signal is active low */

+/**

+  * @}

+  */

+

+/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data

+  * @{

+  */

+#define LL_LPUART_DMA_REG_DATA_TRANSMIT    0x00000000U                       /*!< Get address of data register used for transmission */

+#define LL_LPUART_DMA_REG_DATA_RECEIVE     0x00000001U                       /*!< Get address of data register used for reception */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros

+  * @{

+  */

+

+/** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros

+  * @{

+  */

+

+/**

+  * @brief  Write a value in LPUART register

+  * @param  __INSTANCE__ LPUART Instance

+  * @param  __REG__ Register to be written

+  * @param  __VALUE__ Value to be written in the register

+  * @retval None

+  */

+#define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

+

+/**

+  * @brief  Read a value in LPUART register

+  * @param  __INSTANCE__ LPUART Instance

+  * @param  __REG__ Register to be read

+  * @retval Register value

+  */

+#define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)

+/**

+  * @}

+  */

+

+/** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros

+  * @{

+  */

+

+/**

+  * @brief  Compute LPUARTDIV value according to Peripheral Clock and

+  *         expected Baud Rate (20-bit value of LPUARTDIV is returned)

+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance

+  * @param  __PRESCALER__ This parameter can be one of the following values:

+  *         @arg @ref LL_LPUART_PRESCALER_DIV1

+  *         @arg @ref LL_LPUART_PRESCALER_DIV2

+  *         @arg @ref LL_LPUART_PRESCALER_DIV4

+  *         @arg @ref LL_LPUART_PRESCALER_DIV6

+  *         @arg @ref LL_LPUART_PRESCALER_DIV8

+  *         @arg @ref LL_LPUART_PRESCALER_DIV10

+  *         @arg @ref LL_LPUART_PRESCALER_DIV12

+  *         @arg @ref LL_LPUART_PRESCALER_DIV16

+  *         @arg @ref LL_LPUART_PRESCALER_DIV32

+  *         @arg @ref LL_LPUART_PRESCALER_DIV64

+  *         @arg @ref LL_LPUART_PRESCALER_DIV128

+  *         @arg @ref LL_LPUART_PRESCALER_DIV256

+  * @param  __BAUDRATE__ Baud Rate value to achieve

+  * @retval LPUARTDIV value to be used for BRR register filling

+  */

+#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)])) * LPUART_LPUARTDIV_FREQ_MUL)\

+                                                                                + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK)

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions

+  * @{

+  */

+

+/** @defgroup LPUART_LL_EF_Configuration Configuration functions

+  * @{

+  */

+

+/**

+  * @brief  LPUART Enable

+  * @rmtoll CR1          UE            LL_LPUART_Enable

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx)

+{

+  SET_BIT(LPUARTx->CR1, USART_CR1_UE);

+}

+

+/**

+  * @brief  LPUART Disable

+  * @note   When LPUART is disabled, LPUART prescalers and outputs are stopped immediately,

+  *         and current operations are discarded. The configuration of the LPUART is kept, but all the status

+  *         flags, in the LPUARTx_ISR are set to their default values.

+  * @note   In order to go into low-power mode without generating errors on the line,

+  *         the TE bit must be reset before and the software must wait

+  *         for the TC bit in the LPUART_ISR to be set before resetting the UE bit.

+  *         The DMA requests are also reset when UE = 0 so the DMA channel must

+  *         be disabled before resetting the UE bit.

+  * @rmtoll CR1          UE            LL_LPUART_Disable

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx)

+{

+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE);

+}

+

+/**

+  * @brief  Indicate if LPUART is enabled

+  * @rmtoll CR1          UE            LL_LPUART_IsEnabled

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  FIFO Mode Enable

+  * @rmtoll CR1          FIFOEN        LL_LPUART_EnableFIFO

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx)

+{

+  SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);

+}

+

+/**

+  * @brief  FIFO Mode Disable

+  * @rmtoll CR1          FIFOEN        LL_LPUART_DisableFIFO

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx)

+{

+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN);

+}

+

+/**

+  * @brief  Indicate if FIFO Mode is enabled

+  * @rmtoll CR1          FIFOEN        LL_LPUART_IsEnabledFIFO

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Configure TX FIFO Threshold

+  * @rmtoll CR3          TXFTCFG       LL_LPUART_SetTXFIFOThreshold

+  * @param  LPUARTx LPUART Instance

+  * @param  Threshold This parameter can be one of the following values:

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)

+{

+  MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);

+}

+

+/**

+  * @brief  Return TX FIFO Threshold Configuration

+  * @rmtoll CR3          TXFTCFG       LL_LPUART_GetTXFIFOThreshold

+  * @param  LPUARTx LPUART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8

+  */

+__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(USART_TypeDef *LPUARTx)

+{

+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);

+}

+

+/**

+  * @brief  Configure RX FIFO Threshold

+  * @rmtoll CR3          RXFTCFG       LL_LPUART_SetRXFIFOThreshold

+  * @param  LPUARTx LPUART Instance

+  * @param  Threshold This parameter can be one of the following values:

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold)

+{

+  MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);

+}

+

+/**

+  * @brief  Return RX FIFO Threshold Configuration

+  * @rmtoll CR3          RXFTCFG       LL_LPUART_GetRXFIFOThreshold

+  * @param  LPUARTx LPUART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8

+  */

+__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx)

+{

+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);

+}

+

+/**

+  * @brief  Configure TX and RX FIFOs Threshold

+  * @rmtoll CR3          TXFTCFG       LL_LPUART_ConfigFIFOsThreshold\n

+  *         CR3          RXFTCFG       LL_LPUART_ConfigFIFOsThreshold

+  * @param  LPUARTx LPUART Instance

+  * @param  TXThreshold This parameter can be one of the following values:

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8

+  * @param  RXThreshold This parameter can be one of the following values:

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8

+  *         @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold)

+{

+  MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | (RXThreshold << USART_CR3_RXFTCFG_Pos));

+}

+

+/**

+  * @brief  LPUART enabled in STOP Mode

+  * @note   When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that

+  *         LPUART clock selection is HSI or LSE in RCC.

+  * @rmtoll CR1          UESM          LL_LPUART_EnableInStopMode

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx)

+{

+  SET_BIT(LPUARTx->CR1, USART_CR1_UESM);

+}

+

+/**

+  * @brief  LPUART disabled in STOP Mode

+  * @note   When this function is disabled, LPUART is not able to wake up the MCU from Stop mode

+  * @rmtoll CR1          UESM          LL_LPUART_DisableInStopMode

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx)

+{

+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM);

+}

+

+/**

+  * @brief  Indicate if LPUART is enabled in STOP Mode

+  *         (able to wake up MCU from Stop mode or not)

+  * @rmtoll CR1          UESM          LL_LPUART_IsEnabledInStopMode

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)

+  * @rmtoll CR1          RE            LL_LPUART_EnableDirectionRx

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx)

+{

+  SET_BIT(LPUARTx->CR1, USART_CR1_RE);

+}

+

+/**

+  * @brief  Receiver Disable

+  * @rmtoll CR1          RE            LL_LPUART_DisableDirectionRx

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx)

+{

+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE);

+}

+

+/**

+  * @brief  Transmitter Enable

+  * @rmtoll CR1          TE            LL_LPUART_EnableDirectionTx

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx)

+{

+  SET_BIT(LPUARTx->CR1, USART_CR1_TE);

+}

+

+/**

+  * @brief  Transmitter Disable

+  * @rmtoll CR1          TE            LL_LPUART_DisableDirectionTx

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx)

+{

+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE);

+}

+

+/**

+  * @brief  Configure simultaneously enabled/disabled states

+  *         of Transmitter and Receiver

+  * @rmtoll CR1          RE            LL_LPUART_SetTransferDirection\n

+  *         CR1          TE            LL_LPUART_SetTransferDirection

+  * @param  LPUARTx LPUART Instance

+  * @param  TransferDirection This parameter can be one of the following values:

+  *         @arg @ref LL_LPUART_DIRECTION_NONE

+  *         @arg @ref LL_LPUART_DIRECTION_RX

+  *         @arg @ref LL_LPUART_DIRECTION_TX

+  *         @arg @ref LL_LPUART_DIRECTION_TX_RX

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection)

+{

+  MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);

+}

+

+/**

+  * @brief  Return enabled/disabled states of Transmitter and Receiver

+  * @rmtoll CR1          RE            LL_LPUART_GetTransferDirection\n

+  *         CR1          TE            LL_LPUART_GetTransferDirection

+  * @param  LPUARTx LPUART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_LPUART_DIRECTION_NONE

+  *         @arg @ref LL_LPUART_DIRECTION_RX

+  *         @arg @ref LL_LPUART_DIRECTION_TX

+  *         @arg @ref LL_LPUART_DIRECTION_TX_RX

+  */

+__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx)

+{

+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE));

+}

+

+/**

+  * @brief  Configure Parity (enabled/disabled and parity mode if enabled)

+  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.

+  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position

+  *         (depending on data width) and parity is checked on the received data.

+  * @rmtoll CR1          PS            LL_LPUART_SetParity\n

+  *         CR1          PCE           LL_LPUART_SetParity

+  * @param  LPUARTx LPUART Instance

+  * @param  Parity This parameter can be one of the following values:

+  *         @arg @ref LL_LPUART_PARITY_NONE

+  *         @arg @ref LL_LPUART_PARITY_EVEN

+  *         @arg @ref LL_LPUART_PARITY_ODD

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity)

+{

+  MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);

+}

+

+/**

+  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)

+  * @rmtoll CR1          PS            LL_LPUART_GetParity\n

+  *         CR1          PCE           LL_LPUART_GetParity

+  * @param  LPUARTx LPUART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_LPUART_PARITY_NONE

+  *         @arg @ref LL_LPUART_PARITY_EVEN

+  *         @arg @ref LL_LPUART_PARITY_ODD

+  */

+__STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx)

+{

+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE));

+}

+

+/**

+  * @brief  Set Receiver Wake Up method from Mute mode.

+  * @rmtoll CR1          WAKE          LL_LPUART_SetWakeUpMethod

+  * @param  LPUARTx LPUART Instance

+  * @param  Method This parameter can be one of the following values:

+  *         @arg @ref LL_LPUART_WAKEUP_IDLELINE

+  *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method)

+{

+  MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method);

+}

+

+/**

+  * @brief  Return Receiver Wake Up method from Mute mode

+  * @rmtoll CR1          WAKE          LL_LPUART_GetWakeUpMethod

+  * @param  LPUARTx LPUART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_LPUART_WAKEUP_IDLELINE

+  *         @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK

+  */

+__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx)

+{

+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE));

+}

+

+/**

+  * @brief  Set Word length (nb of data bits, excluding start and stop bits)

+  * @rmtoll CR1          M             LL_LPUART_SetDataWidth

+  * @param  LPUARTx LPUART Instance

+  * @param  DataWidth This parameter can be one of the following values:

+  *         @arg @ref LL_LPUART_DATAWIDTH_7B

+  *         @arg @ref LL_LPUART_DATAWIDTH_8B

+  *         @arg @ref LL_LPUART_DATAWIDTH_9B

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth)

+{

+  MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth);

+}

+

+/**

+  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)

+  * @rmtoll CR1          M             LL_LPUART_GetDataWidth

+  * @param  LPUARTx LPUART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_LPUART_DATAWIDTH_7B

+  *         @arg @ref LL_LPUART_DATAWIDTH_8B

+  *         @arg @ref LL_LPUART_DATAWIDTH_9B

+  */

+__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx)

+{

+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M));

+}

+

+/**

+  * @brief  Allow switch between Mute Mode and Active mode

+  * @rmtoll CR1          MME           LL_LPUART_EnableMuteMode

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx)

+{

+  SET_BIT(LPUARTx->CR1, USART_CR1_MME);

+}

+

+/**

+  * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.

+  * @rmtoll CR1          MME           LL_LPUART_DisableMuteMode

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx)

+{

+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME);

+}

+

+/**

+  * @brief  Indicate if switch between Mute Mode and Active mode is allowed

+  * @rmtoll CR1          MME           LL_LPUART_IsEnabledMuteMode

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Configure Clock source prescaler for baudrate generator and oversampling

+  * @rmtoll PRESC        PRESCALER     LL_LPUART_SetPrescaler

+  * @param  LPUARTx LPUART Instance

+  * @param  PrescalerValue This parameter can be one of the following values:

+  *         @arg @ref LL_LPUART_PRESCALER_DIV1

+  *         @arg @ref LL_LPUART_PRESCALER_DIV2

+  *         @arg @ref LL_LPUART_PRESCALER_DIV4

+  *         @arg @ref LL_LPUART_PRESCALER_DIV6

+  *         @arg @ref LL_LPUART_PRESCALER_DIV8

+  *         @arg @ref LL_LPUART_PRESCALER_DIV10

+  *         @arg @ref LL_LPUART_PRESCALER_DIV12

+  *         @arg @ref LL_LPUART_PRESCALER_DIV16

+  *         @arg @ref LL_LPUART_PRESCALER_DIV32

+  *         @arg @ref LL_LPUART_PRESCALER_DIV64

+  *         @arg @ref LL_LPUART_PRESCALER_DIV128

+  *         @arg @ref LL_LPUART_PRESCALER_DIV256

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue)

+{

+  MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);

+}

+

+/**

+  * @brief  Retrieve the Clock source prescaler for baudrate generator and oversampling

+  * @rmtoll PRESC        PRESCALER     LL_LPUART_GetPrescaler

+  * @param  LPUARTx LPUART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_LPUART_PRESCALER_DIV1

+  *         @arg @ref LL_LPUART_PRESCALER_DIV2

+  *         @arg @ref LL_LPUART_PRESCALER_DIV4

+  *         @arg @ref LL_LPUART_PRESCALER_DIV6

+  *         @arg @ref LL_LPUART_PRESCALER_DIV8

+  *         @arg @ref LL_LPUART_PRESCALER_DIV10

+  *         @arg @ref LL_LPUART_PRESCALER_DIV12

+  *         @arg @ref LL_LPUART_PRESCALER_DIV16

+  *         @arg @ref LL_LPUART_PRESCALER_DIV32

+  *         @arg @ref LL_LPUART_PRESCALER_DIV64

+  *         @arg @ref LL_LPUART_PRESCALER_DIV128

+  *         @arg @ref LL_LPUART_PRESCALER_DIV256

+  */

+__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(USART_TypeDef *LPUARTx)

+{

+  return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER));

+}

+

+/**

+  * @brief  Set the length of the stop bits

+  * @rmtoll CR2          STOP          LL_LPUART_SetStopBitsLength

+  * @param  LPUARTx LPUART Instance

+  * @param  StopBits This parameter can be one of the following values:

+  *         @arg @ref LL_LPUART_STOPBITS_1

+  *         @arg @ref LL_LPUART_STOPBITS_2

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits)

+{

+  MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);

+}

+

+/**

+  * @brief  Retrieve the length of the stop bits

+  * @rmtoll CR2          STOP          LL_LPUART_GetStopBitsLength

+  * @param  LPUARTx LPUART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_LPUART_STOPBITS_1

+  *         @arg @ref LL_LPUART_STOPBITS_2

+  */

+__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx)

+{

+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP));

+}

+

+/**

+  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)

+  * @note   Call of this function is equivalent to following function call sequence :

+  *         - Data Width configuration using @ref LL_LPUART_SetDataWidth() function

+  *         - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function

+  *         - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function

+  * @rmtoll CR1          PS            LL_LPUART_ConfigCharacter\n

+  *         CR1          PCE           LL_LPUART_ConfigCharacter\n

+  *         CR1          M             LL_LPUART_ConfigCharacter\n

+  *         CR2          STOP          LL_LPUART_ConfigCharacter

+  * @param  LPUARTx LPUART Instance

+  * @param  DataWidth This parameter can be one of the following values:

+  *         @arg @ref LL_LPUART_DATAWIDTH_7B

+  *         @arg @ref LL_LPUART_DATAWIDTH_8B

+  *         @arg @ref LL_LPUART_DATAWIDTH_9B

+  * @param  Parity This parameter can be one of the following values:

+  *         @arg @ref LL_LPUART_PARITY_NONE

+  *         @arg @ref LL_LPUART_PARITY_EVEN

+  *         @arg @ref LL_LPUART_PARITY_ODD

+  * @param  StopBits This parameter can be one of the following values:

+  *         @arg @ref LL_LPUART_STOPBITS_1

+  *         @arg @ref LL_LPUART_STOPBITS_2

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity,

+                                               uint32_t StopBits)

+{

+  MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);

+  MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits);

+}

+

+/**

+  * @brief  Configure TX/RX pins swapping setting.

+  * @rmtoll CR2          SWAP          LL_LPUART_SetTXRXSwap

+  * @param  LPUARTx LPUART Instance

+  * @param  SwapConfig This parameter can be one of the following values:

+  *         @arg @ref LL_LPUART_TXRX_STANDARD

+  *         @arg @ref LL_LPUART_TXRX_SWAPPED

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig)

+{

+  MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig);

+}

+

+/**

+  * @brief  Retrieve TX/RX pins swapping configuration.

+  * @rmtoll CR2          SWAP          LL_LPUART_GetTXRXSwap

+  * @param  LPUARTx LPUART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_LPUART_TXRX_STANDARD

+  *         @arg @ref LL_LPUART_TXRX_SWAPPED

+  */

+__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx)

+{

+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP));

+}

+

+/**

+  * @brief  Configure RX pin active level logic

+  * @rmtoll CR2          RXINV         LL_LPUART_SetRXPinLevel

+  * @param  LPUARTx LPUART Instance

+  * @param  PinInvMethod This parameter can be one of the following values:

+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD

+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)

+{

+  MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod);

+}

+

+/**

+  * @brief  Retrieve RX pin active level logic configuration

+  * @rmtoll CR2          RXINV         LL_LPUART_GetRXPinLevel

+  * @param  LPUARTx LPUART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD

+  *         @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED

+  */

+__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx)

+{

+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV));

+}

+

+/**

+  * @brief  Configure TX pin active level logic

+  * @rmtoll CR2          TXINV         LL_LPUART_SetTXPinLevel

+  * @param  LPUARTx LPUART Instance

+  * @param  PinInvMethod This parameter can be one of the following values:

+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD

+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod)

+{

+  MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod);

+}

+

+/**

+  * @brief  Retrieve TX pin active level logic configuration

+  * @rmtoll CR2          TXINV         LL_LPUART_GetTXPinLevel

+  * @param  LPUARTx LPUART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD

+  *         @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED

+  */

+__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx)

+{

+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV));

+}

+

+/**

+  * @brief  Configure Binary data logic.

+  *

+  * @note   Allow to define how Logical data from the data register are send/received :

+  *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)

+  * @rmtoll CR2          DATAINV       LL_LPUART_SetBinaryDataLogic

+  * @param  LPUARTx LPUART Instance

+  * @param  DataLogic This parameter can be one of the following values:

+  *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE

+  *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic)

+{

+  MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic);

+}

+

+/**

+  * @brief  Retrieve Binary data configuration

+  * @rmtoll CR2          DATAINV       LL_LPUART_GetBinaryDataLogic

+  * @param  LPUARTx LPUART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE

+  *         @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE

+  */

+__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx)

+{

+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV));

+}

+

+/**

+  * @brief  Configure transfer bit order (either Less or Most Significant Bit First)

+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.

+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.

+  * @rmtoll CR2          MSBFIRST      LL_LPUART_SetTransferBitOrder

+  * @param  LPUARTx LPUART Instance

+  * @param  BitOrder This parameter can be one of the following values:

+  *         @arg @ref LL_LPUART_BITORDER_LSBFIRST

+  *         @arg @ref LL_LPUART_BITORDER_MSBFIRST

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder)

+{

+  MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder);

+}

+

+/**

+  * @brief  Return transfer bit order (either Less or Most Significant Bit First)

+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.

+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.

+  * @rmtoll CR2          MSBFIRST      LL_LPUART_GetTransferBitOrder

+  * @param  LPUARTx LPUART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_LPUART_BITORDER_LSBFIRST

+  *         @arg @ref LL_LPUART_BITORDER_MSBFIRST

+  */

+__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx)

+{

+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST));

+}

+

+/**

+  * @brief  Set Address of the LPUART node.

+  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,

+  *         for wake up with address mark detection.

+  * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.

+  *         (b7-b4 should be set to 0)

+  *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.

+  *         (This is used in multiprocessor communication during Mute mode or Stop mode,

+  *         for wake up with 7-bit address mark detection.

+  *         The MSB of the character sent by the transmitter should be equal to 1.

+  *         It may also be used for character detection during normal reception,

+  *         Mute mode inactive (for example, end of block detection in ModBus protocol).

+  *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]

+  *         value and CMF flag is set on match)

+  * @rmtoll CR2          ADD           LL_LPUART_ConfigNodeAddress\n

+  *         CR2          ADDM7         LL_LPUART_ConfigNodeAddress

+  * @param  LPUARTx LPUART Instance

+  * @param  AddressLen This parameter can be one of the following values:

+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B

+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B

+  * @param  NodeAddress 4 or 7 bit Address of the LPUART node.

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress)

+{

+  MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,

+             (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));

+}

+

+/**

+  * @brief  Return 8 bit Address of the LPUART node as set in ADD field of CR2.

+  * @note   If 4-bit Address Detection is selected in ADDM7,

+  *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)

+  *         If 7-bit Address Detection is selected in ADDM7,

+  *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)

+  * @rmtoll CR2          ADD           LL_LPUART_GetNodeAddress

+  * @param  LPUARTx LPUART Instance

+  * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255)

+  */

+__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx)

+{

+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);

+}

+

+/**

+  * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)

+  * @rmtoll CR2          ADDM7         LL_LPUART_GetNodeAddressLen

+  * @param  LPUARTx LPUART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_4B

+  *         @arg @ref LL_LPUART_ADDRESS_DETECT_7B

+  */

+__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx)

+{

+  return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7));

+}

+

+/**

+  * @brief  Enable RTS HW Flow Control

+  * @rmtoll CR3          RTSE          LL_LPUART_EnableRTSHWFlowCtrl

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)

+{

+  SET_BIT(LPUARTx->CR3, USART_CR3_RTSE);

+}

+

+/**

+  * @brief  Disable RTS HW Flow Control

+  * @rmtoll CR3          RTSE          LL_LPUART_DisableRTSHWFlowCtrl

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx)

+{

+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE);

+}

+

+/**

+  * @brief  Enable CTS HW Flow Control

+  * @rmtoll CR3          CTSE          LL_LPUART_EnableCTSHWFlowCtrl

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)

+{

+  SET_BIT(LPUARTx->CR3, USART_CR3_CTSE);

+}

+

+/**

+  * @brief  Disable CTS HW Flow Control

+  * @rmtoll CR3          CTSE          LL_LPUART_DisableCTSHWFlowCtrl

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx)

+{

+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE);

+}

+

+/**

+  * @brief  Configure HW Flow Control mode (both CTS and RTS)

+  * @rmtoll CR3          RTSE          LL_LPUART_SetHWFlowCtrl\n

+  *         CR3          CTSE          LL_LPUART_SetHWFlowCtrl

+  * @param  LPUARTx LPUART Instance

+  * @param  HardwareFlowControl This parameter can be one of the following values:

+  *         @arg @ref LL_LPUART_HWCONTROL_NONE

+  *         @arg @ref LL_LPUART_HWCONTROL_RTS

+  *         @arg @ref LL_LPUART_HWCONTROL_CTS

+  *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl)

+{

+  MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);

+}

+

+/**

+  * @brief  Return HW Flow Control configuration (both CTS and RTS)

+  * @rmtoll CR3          RTSE          LL_LPUART_GetHWFlowCtrl\n

+  *         CR3          CTSE          LL_LPUART_GetHWFlowCtrl

+  * @param  LPUARTx LPUART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_LPUART_HWCONTROL_NONE

+  *         @arg @ref LL_LPUART_HWCONTROL_RTS

+  *         @arg @ref LL_LPUART_HWCONTROL_CTS

+  *         @arg @ref LL_LPUART_HWCONTROL_RTS_CTS

+  */

+__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx)

+{

+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));

+}

+

+/**

+  * @brief  Enable Overrun detection

+  * @rmtoll CR3          OVRDIS        LL_LPUART_EnableOverrunDetect

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx)

+{

+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);

+}

+

+/**

+  * @brief  Disable Overrun detection

+  * @rmtoll CR3          OVRDIS        LL_LPUART_DisableOverrunDetect

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx)

+{

+  SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS);

+}

+

+/**

+  * @brief  Indicate if Overrun detection is enabled

+  * @rmtoll CR3          OVRDIS        LL_LPUART_IsEnabledOverrunDetect

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)

+  * @rmtoll CR3          WUS           LL_LPUART_SetWKUPType

+  * @param  LPUARTx LPUART Instance

+  * @param  Type This parameter can be one of the following values:

+  *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS

+  *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT

+  *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type)

+{

+  MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type);

+}

+

+/**

+  * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)

+  * @rmtoll CR3          WUS           LL_LPUART_GetWKUPType

+  * @param  LPUARTx LPUART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS

+  *         @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT

+  *         @arg @ref LL_LPUART_WAKEUP_ON_RXNE

+  */

+__STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx)

+{

+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS));

+}

+

+/**

+  * @brief  Configure LPUART BRR register for achieving expected Baud Rate value.

+  *

+  * @note   Compute and set LPUARTDIV value in BRR Register (full BRR content)

+  *         according to used Peripheral Clock and expected Baud Rate values

+  * @note   Peripheral clock and Baud Rate values provided as function parameters should be valid

+  *         (Baud rate value != 0).

+  * @note   Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit,

+  *         a care should be taken when generating high baud rates using high PeriphClk

+  *         values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate].

+  * @rmtoll BRR          BRR           LL_LPUART_SetBaudRate

+  * @param  LPUARTx LPUART Instance

+  * @param  PeriphClk Peripheral Clock

+  * @param  PrescalerValue This parameter can be one of the following values:

+  *         @arg @ref LL_LPUART_PRESCALER_DIV1

+  *         @arg @ref LL_LPUART_PRESCALER_DIV2

+  *         @arg @ref LL_LPUART_PRESCALER_DIV4

+  *         @arg @ref LL_LPUART_PRESCALER_DIV6

+  *         @arg @ref LL_LPUART_PRESCALER_DIV8

+  *         @arg @ref LL_LPUART_PRESCALER_DIV10

+  *         @arg @ref LL_LPUART_PRESCALER_DIV12

+  *         @arg @ref LL_LPUART_PRESCALER_DIV16

+  *         @arg @ref LL_LPUART_PRESCALER_DIV32

+  *         @arg @ref LL_LPUART_PRESCALER_DIV64

+  *         @arg @ref LL_LPUART_PRESCALER_DIV128

+  *         @arg @ref LL_LPUART_PRESCALER_DIV256

+  * @param  BaudRate Baud Rate

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue,

+                                           uint32_t BaudRate)

+{

+  LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate);

+}

+

+/**

+  * @brief  Return current Baud Rate value, according to LPUARTDIV present in BRR register

+  *         (full BRR content), and to used Peripheral Clock values

+  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.

+  * @rmtoll BRR          BRR           LL_LPUART_GetBaudRate

+  * @param  LPUARTx LPUART Instance

+  * @param  PeriphClk Peripheral Clock

+  * @param  PrescalerValue This parameter can be one of the following values:

+  *         @arg @ref LL_LPUART_PRESCALER_DIV1

+  *         @arg @ref LL_LPUART_PRESCALER_DIV2

+  *         @arg @ref LL_LPUART_PRESCALER_DIV4

+  *         @arg @ref LL_LPUART_PRESCALER_DIV6

+  *         @arg @ref LL_LPUART_PRESCALER_DIV8

+  *         @arg @ref LL_LPUART_PRESCALER_DIV10

+  *         @arg @ref LL_LPUART_PRESCALER_DIV12

+  *         @arg @ref LL_LPUART_PRESCALER_DIV16

+  *         @arg @ref LL_LPUART_PRESCALER_DIV32

+  *         @arg @ref LL_LPUART_PRESCALER_DIV64

+  *         @arg @ref LL_LPUART_PRESCALER_DIV128

+  *         @arg @ref LL_LPUART_PRESCALER_DIV256

+  * @retval Baud Rate

+  */

+__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue)

+{

+  register uint32_t lpuartdiv;

+  register uint32_t brrresult;

+  register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue]));

+

+  lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK;

+

+  if (lpuartdiv >= LPUART_BRR_MIN_VALUE)

+  {

+    brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv);

+  }

+  else

+  {

+    brrresult = 0x0UL;

+  }

+

+  return (brrresult);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature

+  * @{

+  */

+

+/**

+  * @brief  Enable Single Wire Half-Duplex mode

+  * @rmtoll CR3          HDSEL         LL_LPUART_EnableHalfDuplex

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx)

+{

+  SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL);

+}

+

+/**

+  * @brief  Disable Single Wire Half-Duplex mode

+  * @rmtoll CR3          HDSEL         LL_LPUART_DisableHalfDuplex

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx)

+{

+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL);

+}

+

+/**

+  * @brief  Indicate if Single Wire Half-Duplex mode is enabled

+  * @rmtoll CR3          HDSEL         LL_LPUART_IsEnabledHalfDuplex

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature

+  * @{

+  */

+

+/**

+  * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).

+  * @rmtoll CR1          DEDT          LL_LPUART_SetDEDeassertionTime

+  * @param  LPUARTx LPUART Instance

+  * @param  Time Value between Min_Data=0 and Max_Data=31

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time)

+{

+  MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);

+}

+

+/**

+  * @brief  Return DEDT (Driver Enable De-Assertion Time)

+  * @rmtoll CR1          DEDT          LL_LPUART_GetDEDeassertionTime

+  * @param  LPUARTx LPUART Instance

+  * @retval Time value expressed on 5 bits ([4:0] bits) : c

+  */

+__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx)

+{

+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);

+}

+

+/**

+  * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).

+  * @rmtoll CR1          DEAT          LL_LPUART_SetDEAssertionTime

+  * @param  LPUARTx LPUART Instance

+  * @param  Time Value between Min_Data=0 and Max_Data=31

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time)

+{

+  MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);

+}

+

+/**

+  * @brief  Return DEAT (Driver Enable Assertion Time)

+  * @rmtoll CR1          DEAT          LL_LPUART_GetDEAssertionTime

+  * @param  LPUARTx LPUART Instance

+  * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31

+  */

+__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx)

+{

+  return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);

+}

+

+/**

+  * @brief  Enable Driver Enable (DE) Mode

+  * @rmtoll CR3          DEM           LL_LPUART_EnableDEMode

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx)

+{

+  SET_BIT(LPUARTx->CR3, USART_CR3_DEM);

+}

+

+/**

+  * @brief  Disable Driver Enable (DE) Mode

+  * @rmtoll CR3          DEM           LL_LPUART_DisableDEMode

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx)

+{

+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM);

+}

+

+/**

+  * @brief  Indicate if Driver Enable (DE) Mode is enabled

+  * @rmtoll CR3          DEM           LL_LPUART_IsEnabledDEMode

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Select Driver Enable Polarity

+  * @rmtoll CR3          DEP           LL_LPUART_SetDESignalPolarity

+  * @param  LPUARTx LPUART Instance

+  * @param  Polarity This parameter can be one of the following values:

+  *         @arg @ref LL_LPUART_DE_POLARITY_HIGH

+  *         @arg @ref LL_LPUART_DE_POLARITY_LOW

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity)

+{

+  MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity);

+}

+

+/**

+  * @brief  Return Driver Enable Polarity

+  * @rmtoll CR3          DEP           LL_LPUART_GetDESignalPolarity

+  * @param  LPUARTx LPUART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_LPUART_DE_POLARITY_HIGH

+  *         @arg @ref LL_LPUART_DE_POLARITY_LOW

+  */

+__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx)

+{

+  return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management

+  * @{

+  */

+

+/**

+  * @brief  Check if the LPUART Parity Error Flag is set or not

+  * @rmtoll ISR          PE            LL_LPUART_IsActiveFlag_PE

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the LPUART Framing Error Flag is set or not

+  * @rmtoll ISR          FE            LL_LPUART_IsActiveFlag_FE

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the LPUART Noise error detected Flag is set or not

+  * @rmtoll ISR          NE            LL_LPUART_IsActiveFlag_NE

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the LPUART OverRun Error Flag is set or not

+  * @rmtoll ISR          ORE           LL_LPUART_IsActiveFlag_ORE

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the LPUART IDLE line detected Flag is set or not

+  * @rmtoll ISR          IDLE          LL_LPUART_IsActiveFlag_IDLE

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);

+}

+

+/* Legacy define */

+#define LL_LPUART_IsActiveFlag_RXNE  LL_LPUART_IsActiveFlag_RXNE_RXFNE

+

+/**

+  * @brief  Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not

+  * @rmtoll ISR          RXNE_RXFNE    LL_LPUART_IsActiveFlag_RXNE_RXFNE

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the LPUART Transmission Complete Flag is set or not

+  * @rmtoll ISR          TC            LL_LPUART_IsActiveFlag_TC

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);

+}

+

+/* Legacy define */

+#define LL_LPUART_IsActiveFlag_TXE  LL_LPUART_IsActiveFlag_TXE_TXFNF

+

+/**

+  * @brief  Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not

+  * @rmtoll ISR          TXE_TXFNF     LL_LPUART_IsActiveFlag_TXE_TXFNF

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the LPUART CTS interrupt Flag is set or not

+  * @rmtoll ISR          CTSIF         LL_LPUART_IsActiveFlag_nCTS

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the LPUART CTS Flag is set or not

+  * @rmtoll ISR          CTS           LL_LPUART_IsActiveFlag_CTS

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the LPUART Busy Flag is set or not

+  * @rmtoll ISR          BUSY          LL_LPUART_IsActiveFlag_BUSY

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the LPUART Character Match Flag is set or not

+  * @rmtoll ISR          CMF           LL_LPUART_IsActiveFlag_CM

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the LPUART Send Break Flag is set or not

+  * @rmtoll ISR          SBKF          LL_LPUART_IsActiveFlag_SBK

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the LPUART Receive Wake Up from mute mode Flag is set or not

+  * @rmtoll ISR          RWU           LL_LPUART_IsActiveFlag_RWU

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the LPUART Wake Up from stop mode Flag is set or not

+  * @rmtoll ISR          WUF           LL_LPUART_IsActiveFlag_WKUP

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the LPUART Transmit Enable Acknowledge Flag is set or not

+  * @rmtoll ISR          TEACK         LL_LPUART_IsActiveFlag_TEACK

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the LPUART Receive Enable Acknowledge Flag is set or not

+  * @rmtoll ISR          REACK         LL_LPUART_IsActiveFlag_REACK

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the LPUART TX FIFO Empty Flag is set or not

+  * @rmtoll ISR          TXFE          LL_LPUART_IsActiveFlag_TXFE

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the LPUART RX FIFO Full Flag is set or not

+  * @rmtoll ISR          RXFF          LL_LPUART_IsActiveFlag_RXFF

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the LPUART TX FIFO Threshold Flag is set or not

+  * @rmtoll ISR          TXFT          LL_LPUART_IsActiveFlag_TXFT

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the LPUART RX FIFO Threshold Flag is set or not

+  * @rmtoll ISR          RXFT          LL_LPUART_IsActiveFlag_RXFT

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear Parity Error Flag

+  * @rmtoll ICR          PECF          LL_LPUART_ClearFlag_PE

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx)

+{

+  WRITE_REG(LPUARTx->ICR, USART_ICR_PECF);

+}

+

+/**

+  * @brief  Clear Framing Error Flag

+  * @rmtoll ICR          FECF          LL_LPUART_ClearFlag_FE

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx)

+{

+  WRITE_REG(LPUARTx->ICR, USART_ICR_FECF);

+}

+

+/**

+  * @brief  Clear Noise detected Flag

+  * @rmtoll ICR          NECF          LL_LPUART_ClearFlag_NE

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx)

+{

+  WRITE_REG(LPUARTx->ICR, USART_ICR_NECF);

+}

+

+/**

+  * @brief  Clear OverRun Error Flag

+  * @rmtoll ICR          ORECF         LL_LPUART_ClearFlag_ORE

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx)

+{

+  WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF);

+}

+

+/**

+  * @brief  Clear IDLE line detected Flag

+  * @rmtoll ICR          IDLECF        LL_LPUART_ClearFlag_IDLE

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx)

+{

+  WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF);

+}

+

+/**

+  * @brief  Clear TX FIFO Empty Flag

+  * @rmtoll ICR          TXFECF        LL_LPUART_ClearFlag_TXFE

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_ClearFlag_TXFE(USART_TypeDef *LPUARTx)

+{

+  WRITE_REG(LPUARTx->ICR, USART_ICR_TXFECF);

+}

+

+/**

+  * @brief  Clear Transmission Complete Flag

+  * @rmtoll ICR          TCCF          LL_LPUART_ClearFlag_TC

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx)

+{

+  WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF);

+}

+

+/**

+  * @brief  Clear CTS Interrupt Flag

+  * @rmtoll ICR          CTSCF         LL_LPUART_ClearFlag_nCTS

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx)

+{

+  WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF);

+}

+

+/**

+  * @brief  Clear Character Match Flag

+  * @rmtoll ICR          CMCF          LL_LPUART_ClearFlag_CM

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx)

+{

+  WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF);

+}

+

+/**

+  * @brief  Clear Wake Up from stop mode Flag

+  * @rmtoll ICR          WUCF          LL_LPUART_ClearFlag_WKUP

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx)

+{

+  WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup LPUART_LL_EF_IT_Management IT_Management

+  * @{

+  */

+

+/**

+  * @brief  Enable IDLE Interrupt

+  * @rmtoll CR1          IDLEIE        LL_LPUART_EnableIT_IDLE

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx)

+{

+  SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);

+}

+

+/* Legacy define */

+#define LL_LPUART_EnableIT_RXNE  LL_LPUART_EnableIT_RXNE_RXFNE

+

+/**

+  * @brief  Enable RX Not Empty and RX FIFO Not Empty Interrupt

+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_EnableIT_RXNE_RXFNE

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)

+{

+  SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);

+}

+

+/**

+  * @brief  Enable Transmission Complete Interrupt

+  * @rmtoll CR1          TCIE          LL_LPUART_EnableIT_TC

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx)

+{

+  SET_BIT(LPUARTx->CR1, USART_CR1_TCIE);

+}

+

+/* Legacy define */

+#define LL_LPUART_EnableIT_TXE  LL_LPUART_EnableIT_TXE_TXFNF

+

+/**

+  * @brief  Enable TX Empty and TX FIFO Not Full Interrupt

+  * @rmtoll CR1         TXEIE_TXFNFIE  LL_LPUART_EnableIT_TXE_TXFNF

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)

+{

+  SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);

+}

+

+/**

+  * @brief  Enable Parity Error Interrupt

+  * @rmtoll CR1          PEIE          LL_LPUART_EnableIT_PE

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx)

+{

+  SET_BIT(LPUARTx->CR1, USART_CR1_PEIE);

+}

+

+/**

+  * @brief  Enable Character Match Interrupt

+  * @rmtoll CR1          CMIE          LL_LPUART_EnableIT_CM

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx)

+{

+  SET_BIT(LPUARTx->CR1, USART_CR1_CMIE);

+}

+

+/**

+  * @brief  Enable TX FIFO Empty Interrupt

+  * @rmtoll CR1          TXFEIE        LL_LPUART_EnableIT_TXFE

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx)

+{

+  SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);

+}

+

+/**

+  * @brief  Enable RX FIFO Full Interrupt

+  * @rmtoll CR1          RXFFIE        LL_LPUART_EnableIT_RXFF

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx)

+{

+  SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);

+}

+

+/**

+  * @brief  Enable Error Interrupt

+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing

+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).

+  *         - 0: Interrupt is inhibited

+  *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.

+  * @rmtoll CR3          EIE           LL_LPUART_EnableIT_ERROR

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx)

+{

+  SET_BIT(LPUARTx->CR3, USART_CR3_EIE);

+}

+

+/**

+  * @brief  Enable CTS Interrupt

+  * @rmtoll CR3          CTSIE         LL_LPUART_EnableIT_CTS

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx)

+{

+  SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE);

+}

+

+/**

+  * @brief  Enable Wake Up from Stop Mode Interrupt

+  * @rmtoll CR3          WUFIE         LL_LPUART_EnableIT_WKUP

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx)

+{

+  SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE);

+}

+

+/**

+  * @brief  Enable TX FIFO Threshold Interrupt

+  * @rmtoll CR3          TXFTIE        LL_LPUART_EnableIT_TXFT

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx)

+{

+  SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);

+}

+

+/**

+  * @brief  Enable RX FIFO Threshold Interrupt

+  * @rmtoll CR3          RXFTIE        LL_LPUART_EnableIT_RXFT

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx)

+{

+  SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);

+}

+

+/**

+  * @brief  Disable IDLE Interrupt

+  * @rmtoll CR1          IDLEIE        LL_LPUART_DisableIT_IDLE

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx)

+{

+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE);

+}

+

+/* Legacy define */

+#define LL_LPUART_DisableIT_RXNE  LL_LPUART_DisableIT_RXNE_RXFNE

+

+/**

+  * @brief  Disable RX Not Empty and RX FIFO Not Empty Interrupt

+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_DisableIT_RXNE_RXFNE

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)

+{

+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);

+}

+

+/**

+  * @brief  Disable Transmission Complete Interrupt

+  * @rmtoll CR1          TCIE          LL_LPUART_DisableIT_TC

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx)

+{

+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE);

+}

+

+/* Legacy define */

+#define LL_LPUART_DisableIT_TXE  LL_LPUART_DisableIT_TXE_TXFNF

+

+/**

+  * @brief  Disable TX Empty and TX FIFO Not Full Interrupt

+  * @rmtoll CR1        TXEIE_TXFNFIE  LL_LPUART_DisableIT_TXE_TXFNF

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx)

+{

+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE);

+}

+

+/**

+  * @brief  Disable Parity Error Interrupt

+  * @rmtoll CR1          PEIE          LL_LPUART_DisableIT_PE

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx)

+{

+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE);

+}

+

+/**

+  * @brief  Disable Character Match Interrupt

+  * @rmtoll CR1          CMIE          LL_LPUART_DisableIT_CM

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx)

+{

+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE);

+}

+

+/**

+  * @brief  Disable TX FIFO Empty Interrupt

+  * @rmtoll CR1          TXFEIE        LL_LPUART_DisableIT_TXFE

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx)

+{

+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE);

+}

+

+/**

+  * @brief  Disable RX FIFO Full Interrupt

+  * @rmtoll CR1          RXFFIE        LL_LPUART_DisableIT_RXFF

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx)

+{

+  CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE);

+}

+

+/**

+  * @brief  Disable Error Interrupt

+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing

+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register).

+  *         - 0: Interrupt is inhibited

+  *         - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register.

+  * @rmtoll CR3          EIE           LL_LPUART_DisableIT_ERROR

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx)

+{

+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE);

+}

+

+/**

+  * @brief  Disable CTS Interrupt

+  * @rmtoll CR3          CTSIE         LL_LPUART_DisableIT_CTS

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx)

+{

+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE);

+}

+

+/**

+  * @brief  Disable Wake Up from Stop Mode Interrupt

+  * @rmtoll CR3          WUFIE         LL_LPUART_DisableIT_WKUP

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx)

+{

+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE);

+}

+

+/**

+  * @brief  Disable TX FIFO Threshold Interrupt

+  * @rmtoll CR3          TXFTIE        LL_LPUART_DisableIT_TXFT

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx)

+{

+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE);

+}

+

+/**

+  * @brief  Disable RX FIFO Threshold Interrupt

+  * @rmtoll CR3          RXFTIE        LL_LPUART_DisableIT_RXFT

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx)

+{

+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE);

+}

+

+/**

+  * @brief  Check if the LPUART IDLE Interrupt  source is enabled or disabled.

+  * @rmtoll CR1          IDLEIE        LL_LPUART_IsEnabledIT_IDLE

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);

+}

+

+/* Legacy define */

+#define LL_LPUART_IsEnabledIT_RXNE  LL_LPUART_IsEnabledIT_RXNE_RXFNE

+

+/**

+  * @brief  Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled.

+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_LPUART_IsEnabledIT_RXNE_RXFNE

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the LPUART Transmission Complete Interrupt is enabled or disabled.

+  * @rmtoll CR1          TCIE          LL_LPUART_IsEnabledIT_TC

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);

+}

+

+/* Legacy define */

+#define LL_LPUART_IsEnabledIT_TXE  LL_LPUART_IsEnabledIT_TXE_TXFNF

+

+/**

+  * @brief  Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled

+  * @rmtoll CR1         TXEIE_TXFNFIE  LL_LPUART_IsEnabledIT_TXE_TXFNF

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the LPUART Parity Error Interrupt is enabled or disabled.

+  * @rmtoll CR1          PEIE          LL_LPUART_IsEnabledIT_PE

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the LPUART Character Match Interrupt is enabled or disabled.

+  * @rmtoll CR1          CMIE          LL_LPUART_IsEnabledIT_CM

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled

+  * @rmtoll CR1          TXFEIE        LL_LPUART_IsEnabledIT_TXFE

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the LPUART RX FIFO Full Interrupt is enabled or disabled

+  * @rmtoll CR1          RXFFIE        LL_LPUART_IsEnabledIT_RXFF

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the LPUART Error Interrupt is enabled or disabled.

+  * @rmtoll CR3          EIE           LL_LPUART_IsEnabledIT_ERROR

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the LPUART CTS Interrupt is enabled or disabled.

+  * @rmtoll CR3          CTSIE         LL_LPUART_IsEnabledIT_CTS

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled.

+  * @rmtoll CR3          WUFIE         LL_LPUART_IsEnabledIT_WKUP

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled

+  * @rmtoll CR3          TXFTIE        LL_LPUART_IsEnabledIT_TXFT

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled

+  * @rmtoll CR3          RXFTIE        LL_LPUART_IsEnabledIT_RXFT

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup LPUART_LL_EF_DMA_Management DMA_Management

+  * @{

+  */

+

+/**

+  * @brief  Enable DMA Mode for reception

+  * @rmtoll CR3          DMAR          LL_LPUART_EnableDMAReq_RX

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx)

+{

+  SET_BIT(LPUARTx->CR3, USART_CR3_DMAR);

+}

+

+/**

+  * @brief  Disable DMA Mode for reception

+  * @rmtoll CR3          DMAR          LL_LPUART_DisableDMAReq_RX

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx)

+{

+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR);

+}

+

+/**

+  * @brief  Check if DMA Mode is enabled for reception

+  * @rmtoll CR3          DMAR          LL_LPUART_IsEnabledDMAReq_RX

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable DMA Mode for transmission

+  * @rmtoll CR3          DMAT          LL_LPUART_EnableDMAReq_TX

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx)

+{

+  SET_BIT(LPUARTx->CR3, USART_CR3_DMAT);

+}

+

+/**

+  * @brief  Disable DMA Mode for transmission

+  * @rmtoll CR3          DMAT          LL_LPUART_DisableDMAReq_TX

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx)

+{

+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT);

+}

+

+/**

+  * @brief  Check if DMA Mode is enabled for transmission

+  * @rmtoll CR3          DMAT          LL_LPUART_IsEnabledDMAReq_TX

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable DMA Disabling on Reception Error

+  * @rmtoll CR3          DDRE          LL_LPUART_EnableDMADeactOnRxErr

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx)

+{

+  SET_BIT(LPUARTx->CR3, USART_CR3_DDRE);

+}

+

+/**

+  * @brief  Disable DMA Disabling on Reception Error

+  * @rmtoll CR3          DDRE          LL_LPUART_DisableDMADeactOnRxErr

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx)

+{

+  CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE);

+}

+

+/**

+  * @brief  Indicate if DMA Disabling on Reception Error is disabled

+  * @rmtoll CR3          DDRE          LL_LPUART_IsEnabledDMADeactOnRxErr

+  * @param  LPUARTx LPUART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx)

+{

+  return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get the LPUART data register address used for DMA transfer

+  * @rmtoll RDR          RDR           LL_LPUART_DMA_GetRegAddr\n

+  * @rmtoll TDR          TDR           LL_LPUART_DMA_GetRegAddr

+  * @param  LPUARTx LPUART Instance

+  * @param  Direction This parameter can be one of the following values:

+  *         @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT

+  *         @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE

+  * @retval Address of data register

+  */

+__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction)

+{

+  register uint32_t data_reg_addr;

+

+  if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT)

+  {

+    /* return address of TDR register */

+    data_reg_addr = (uint32_t) &(LPUARTx->TDR);

+  }

+  else

+  {

+    /* return address of RDR register */

+    data_reg_addr = (uint32_t) &(LPUARTx->RDR);

+  }

+

+  return data_reg_addr;

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup LPUART_LL_EF_Data_Management Data_Management

+  * @{

+  */

+

+/**

+  * @brief  Read Receiver Data register (Receive Data value, 8 bits)

+  * @rmtoll RDR          RDR           LL_LPUART_ReceiveData8

+  * @param  LPUARTx LPUART Instance

+  * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF

+  */

+__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx)

+{

+  return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU);

+}

+

+/**

+  * @brief  Read Receiver Data register (Receive Data value, 9 bits)

+  * @rmtoll RDR          RDR           LL_LPUART_ReceiveData9

+  * @param  LPUARTx LPUART Instance

+  * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF

+  */

+__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx)

+{

+  return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR));

+}

+

+/**

+  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)

+  * @rmtoll TDR          TDR           LL_LPUART_TransmitData8

+  * @param  LPUARTx LPUART Instance

+  * @param  Value between Min_Data=0x00 and Max_Data=0xFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value)

+{

+  LPUARTx->TDR = Value;

+}

+

+/**

+  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)

+  * @rmtoll TDR          TDR           LL_LPUART_TransmitData9

+  * @param  LPUARTx LPUART Instance

+  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value)

+{

+  LPUARTx->TDR = Value & 0x1FFUL;

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup LPUART_LL_EF_Execution Execution

+  * @{

+  */

+

+/**

+  * @brief  Request Break sending

+  * @rmtoll RQR          SBKRQ         LL_LPUART_RequestBreakSending

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx)

+{

+  SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ);

+}

+

+/**

+  * @brief  Put LPUART in mute mode and set the RWU flag

+  * @rmtoll RQR          MMRQ          LL_LPUART_RequestEnterMuteMode

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx)

+{

+  SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ);

+}

+

+/**

+  * @brief  Request a Receive Data and FIFO flush

+  * @note   Allows to discard the received data without reading them, and avoid an overrun

+  *         condition.

+  * @rmtoll RQR          RXFRQ         LL_LPUART_RequestRxDataFlush

+  * @param  LPUARTx LPUART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx)

+{

+  SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ);

+}

+

+/**

+  * @}

+  */

+

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions

+  * @{

+  */

+ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx);

+ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct);

+void        LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct);

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* LPUART1 */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_LL_LPUART_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_mdma.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_mdma.h
new file mode 100644
index 0000000000..6e4b776a13
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_mdma.h
@@ -0,0 +1,4360 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_mdma.h

+  * @author  MCD Application Team

+  * @brief   Header file of MDMA LL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_LL_MDMA_H

+#define STM32H7xx_LL_MDMA_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+#if defined (MDMA)

+

+/** @defgroup MDMA_LL MDMA

+  * @{

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/** @defgroup MDMA_LL_Private_Variables MDMA Private Variables

+  * @{

+  */

+/* Array used to get the MDMA channel register offset versus channel index LL_MDMA_CHANNEL_x */

+static const uint32_t LL_MDMA_CH_OFFSET_TAB[] =

+{

+  (uint32_t)(MDMA_Channel0_BASE - MDMA_BASE),

+  (uint32_t)(MDMA_Channel1_BASE - MDMA_BASE),

+  (uint32_t)(MDMA_Channel2_BASE - MDMA_BASE),

+  (uint32_t)(MDMA_Channel3_BASE - MDMA_BASE),

+  (uint32_t)(MDMA_Channel4_BASE - MDMA_BASE),

+  (uint32_t)(MDMA_Channel5_BASE - MDMA_BASE),

+  (uint32_t)(MDMA_Channel6_BASE - MDMA_BASE),

+  (uint32_t)(MDMA_Channel7_BASE - MDMA_BASE),

+  (uint32_t)(MDMA_Channel8_BASE - MDMA_BASE),

+  (uint32_t)(MDMA_Channel9_BASE - MDMA_BASE),

+  (uint32_t)(MDMA_Channel10_BASE - MDMA_BASE),

+  (uint32_t)(MDMA_Channel11_BASE - MDMA_BASE),

+  (uint32_t)(MDMA_Channel12_BASE - MDMA_BASE),

+  (uint32_t)(MDMA_Channel13_BASE - MDMA_BASE),

+  (uint32_t)(MDMA_Channel14_BASE - MDMA_BASE),

+  (uint32_t)(MDMA_Channel15_BASE - MDMA_BASE)

+};

+

+/**

+  * @}

+  */

+

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup MDMA_LL_Private_Constants MDMA Private Constants

+  * @{

+  */

+/**

+  * @}

+  */

+

+

+/* Private macros ------------------------------------------------------------*/

+/* Exported types ------------------------------------------------------------*/

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup MDMA_LL_ES_INIT MDMA Exported Init structure

+  * @{

+  */

+typedef struct

+{

+  uint32_t SrcAddress;            /*!< Specifies the transfer source address

+                                       This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.

+                                       This feature can be modified afterwards using unitary function @ref LL_MDMA_SetSourceAddress() */

+

+  uint32_t DstAddress;            /*!< Specifies the transfer destination address

+                                       This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF.

+                                       This feature can be modified afterwards using unitary function @ref LL_MDMA_SetDestinationAddress() */

+

+  uint32_t RequestMode;           /*!< Specifies the request mode Hardware or Software.

+                                       This parameter can be a value of @ref MDMA_LL_EC_REQUEST_MODE

+                                       This feature can be modified afterwards using unitary function @ref LL_MDMA_SetRequestMode() */

+

+  uint32_t TriggerMode;           /*!< Specifies the transfer trigger mode.

+                                       This parameter can be a value of @ref MDMA_LL_EC_TRIGGER_MODE

+                                       This feature can be modified afterwards using unitary function @ref LL_MDMA_SetTriggerMode() */

+

+  uint32_t HWTrigger;             /*!< Specifies the HW transfer trigger used when RequestMode is HW.

+                                       This parameter can be a value of @ref MDMA_LL_EC_HW_TRIGGER_SELCTION

+                                       This feature can be modified afterwards using unitary function @ref LL_MDMA_SetHWTrigger() */

+

+  uint32_t BlockDataLength;       /*!< Specifies the length of a block transfer in bytes

+                                       This parameter must be a value between Min_Data = 0 and Max_Data = 0x00010000.

+                                       This feature can be modified afterwards using unitary function @ref LL_MDMA_SetBlkDataLength() */

+

+  uint32_t BlockRepeatCount;      /*!< Specifies the Block Repeat Count

+                                       This parameter must be a value between Min_Data = 0 and Max_Data = 0x00000FFF.

+                                       This feature can be modified afterwards using unitary function @ref LL_MDMA_SetBlkRepeatCount() */

+

+  uint32_t BlockRepeatDestAddrUpdateMode; /*!< Specifies the block repeat destination address update mode.

+                                               This parameter can be a value of @ref MDMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE

+                                               This feature can be modified afterwards using unitary function @ref LL_MDMA_SetBlkRepeatDestAddrUpdate() */

+

+  uint32_t BlockRepeatSrcAddrUpdateMode;  /*!< Specifies the block repeat source address update mode.

+                                               This parameter can be a value of @ref MDMA_LL_EC_SRC_BLK_RPT_ADDR_UPDATE_MODE

+                                               This feature can be modified afterwards using unitary function @ref LL_MDMA_SetBlkRepeatSrcAddrUpdate() */

+

+  uint32_t BlockRepeatDestAddrUpdateVal;  /*!< Specifies the block repeat destination address update value.

+                                               This parameter can be a value Between 0 to 0x0000FFFF

+                                               This feature can be modified afterwards using unitary function @ref LL_MDMA_SetBlkRptDestAddrUpdateValue() */

+

+  uint32_t BlockRepeatSrcAddrUpdateVal;   /*!< Specifies the block repeat source address update value.

+                                               This parameter can be a value Between 0 to 0x0000FFFF

+                                               This feature can be modified afterwards using unitary function @ref LL_MDMA_SetBlkRptSrcAddrUpdateValue() */

+

+  uint32_t LinkAddress;                   /*!< Specifies the linked list next transfer node address.

+                                               This parameter can be a value Between 0 to 0xFFFFFFFF

+                                               This feature can be modified afterwards using unitary function @ref LL_MDMA_SetLinkAddress() */

+

+  uint32_t WordEndianess;         /*!< Specifies the Word transfer endianness

+                                       This parameter can be a value of @ref MDMA_LL_EC_WORD_ENDIANNESS.

+                                       This feature can be modified afterwards using unitary function @ref LL_MDMA_SetWordEndianness() */

+

+  uint32_t HalfWordEndianess;     /*!< Specifies the Half Word transfer endianness

+                                       This parameter can be a value of @ref MDMA_LL_EC_HALFWORD_ENDIANNESS.

+                                       This feature can be modified afterwards using unitary function @ref LL_MDMA_SetHalfWordEndianness() */

+

+  uint32_t ByteEndianess;         /*!< Specifies the Byte transfer endianness

+                                       This parameter can be a value of @ref MDMA_LL_EC_BYTE_ENDIANNESS.

+                                       This feature can be modified afterwards using unitary function @ref LL_MDMA_SetByteEndianness() */

+

+  uint32_t Priority;              /*!< Specifies the channel priority level.

+                                       This parameter can be a value of @ref MDMA_LL_EC_PRIORITY

+                                       This feature can be modified afterwards using unitary function @ref LL_MDMA_SetChannelPriorityLevel() */

+

+  uint32_t BufferableWriteMode;   /*!< Specifies the transfer Bufferable Write Mode.

+                                       This parameter can be a value of @ref MDMA_LL_EC_BUFF_WRITE_MODE

+                                       This feature can be modified afterwards using unitary function @ref LL_MDMA_EnableBufferableWrMode()

+                                       and LL_MDMA_DisableBufferableWrMode */

+

+

+  uint32_t PaddingAlignment;     /*!< Specifies the transfer Padding and Alignment.

+                                       This parameter can be a value of @ref MDMA_LL_EC_PADDING_ALIGNMENT_MODE

+                                       This feature can be modified afterwards using unitary function @ref LL_MDMA_SetPaddingAlignment() */

+

+  uint32_t PackMode;              /*!< Specifies the transfer Packing enabled or disabled.

+                                       This parameter can be a value of @ref MDMA_LL_EC_PACKING_MODE

+                                       This feature can be modified afterwards using unitary function @ref LL_MDMA_EnablePacking()

+                                       and LL_MDMA_DisablePacking() */

+

+  uint32_t BufferTransferLength;  /*!< Specifies the length of a buffer transfer in bytes

+                                       This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000007F.

+                                       This feature can be modified afterwards using unitary function @ref LL_MDMA_SetBufferTransferLength() */

+

+  uint32_t DestBurst;             /*!< Specifies the destination burst size.

+                                       This parameter can be a value of @ref MDMA_LL_EC_DEST_BURST

+                                       This feature can be modified afterwards using unitary function @ref LL_MDMA_SetDestinationBurstSize() */

+

+  uint32_t SrctBurst;             /*!< Specifies the source burst size.

+                                       This parameter can be a value of @ref MDMA_LL_EC_SRC_BURST

+                                       This feature can be modified afterwards using unitary function @ref LL_MDMA_SetSourceBurstSize() */

+

+  uint32_t DestIncSize;           /*!< Specifies the destination increment size.

+                                       This parameter can be a value of @ref MDMA_LL_EC_DEST_INC_OFFSET_SIZE

+                                       This feature can be modified afterwards using unitary function @ref LL_MDMA_SetDestinationIncSize() */

+

+  uint32_t SrcIncSize;            /*!< Specifies the source increment size.

+                                       This parameter can be a value of @ref MDMA_LL_EC_SRC_INC_OFFSET_SIZE

+                                       This feature can be modified afterwards using unitary function @ref LL_MDMA_SetSourceIncSize() */

+

+  uint32_t DestDataSize;          /*!< Specifies the destination data size.

+                                       This parameter can be a value of @ref MDMA_LL_EC_DEST_DATA_SIZE

+                                       This feature can be modified afterwards using unitary function @ref LL_MDMA_SetDestinationDataSize() */

+

+  uint32_t SrcDataSize;           /*!< Specifies the source data size.

+                                       This parameter can be a value of @ref MDMA_LL_EC_SRC_DATA_SIZE

+                                       This feature can be modified afterwards using unitary function @ref LL_MDMA_SetSourceDataSize() */

+

+  uint32_t DestIncMode;           /*!< Specifies the destination increment mode.

+                                       This parameter can be a value of @ref MDMA_LL_EC_DEST_INC_MODE

+                                       This feature can be modified afterwards using unitary function @ref LL_MDMA_SetDestinationIncMode() */

+

+  uint32_t SrcIncMode;            /*!< Specifies the source increment mode.

+                                       This parameter can be a value of @ref MDMA_LL_EC_SRC_INC_MODE

+                                       This feature can be modified afterwards using unitary function @ref LL_MDMA_SetSourceIncMode() */

+

+

+  uint32_t DestBus;               /*!< Specifies the destination transfer bus, System AXI or AHB/TCM bus.

+                                       This parameter can be a value of @ref MDMA_LL_EC_DEST_BUS

+                                       This feature can be modified afterwards using unitary function @ref LL_MDMA_SetDestBusSelection() */

+

+  uint32_t SrcBus;                /*!< Specifies the source transfer bus, System AXI or AHB/TCM bus.

+                                       This parameter can be a value of @ref MDMA_LL_EC_SRC_BUS

+                                       This feature can be modified afterwards using unitary function @ref LL_MDMA_SetSrcBusSelection() */

+

+  uint32_t MaskAddress;           /*!< Specifies the address to be updated (written) with MaskData after a request is served.

+                                       MaskAddress and MaskData could be used to automatically clear a peripheral flag when the request is served

+                                       This parameter can be a value Between 0 to 0xFFFFFFFF

+                                       This feature can be modified afterwards using unitary function @ref LL_MDMA_SetMaskAddress() */

+

+  uint32_t MaskData;              /*!< Specifies the value to be written to MaskAddress after a request is served.

+                                       MaskAddress and MaskData could be used to automatically clear a peripheral flag when the request is served

+                                       This parameter can be a value Between 0 to 0xFFFFFFFF

+                                       This feature can be modified afterwards using unitary function @ref LL_MDMA_SetMaskData() */

+

+} LL_MDMA_InitTypeDef;

+

+/**

+  * @brief  LL MDMA linked list node structure definition

+  * @note   The Linked list node allows to define a new MDMA configuration

+  *         (CTCR ,CBNDTR ,CSAR ,CDAR ,CBRUR, CLAR, CTBR, CMAR and CMDR registers).

+  *         When CLAR register is configured to a non NULL value , each time a transfer ends,

+  *         a new configuration (linked list node) is automatically loaded from the address given in CLAR register.

+  */

+typedef struct

+{

+  __IO uint32_t CTCR;     /*!< New CTCR register configuration for the given MDMA linked list node   */

+  __IO uint32_t CBNDTR;   /*!< New CBNDTR register configuration for the given MDMA linked list node */

+  __IO uint32_t CSAR;     /*!< New CSAR register configuration for the given MDMA linked list node   */

+  __IO uint32_t CDAR;     /*!< New CDAR register configuration for the given MDMA linked list node   */

+  __IO uint32_t CBRUR;    /*!< New CBRUR register configuration for the given MDMA linked list node  */

+  __IO uint32_t CLAR;     /*!< New CLAR register configuration for the given MDMA linked list node   */

+  __IO uint32_t CTBR;     /*!< New CTBR register configuration for the given MDMA linked list node   */

+  __IO uint32_t Reserved; /*!< Reserved register*/

+  __IO uint32_t CMAR;     /*!< New CMAR register configuration for the given MDMA linked list node   */

+  __IO uint32_t CMDR;     /*!< New CMDR register configuration for the given MDMA linked list node   */

+

+}LL_MDMA_LinkNodeTypeDef;

+

+/**

+  * @}

+  */

+#endif /*USE_FULL_LL_DRIVER*/

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup MDMA_LL_Exported_Constants MDMA Exported Constants

+  * @{

+  */

+

+/** @defgroup MDMA_LL_EC_CHANNEL CHANNEL

+  * @{

+  */

+#define LL_MDMA_CHANNEL_0                   0x00000000U

+#define LL_MDMA_CHANNEL_1                   0x00000001U

+#define LL_MDMA_CHANNEL_2                   0x00000002U

+#define LL_MDMA_CHANNEL_3                   0x00000003U

+#define LL_MDMA_CHANNEL_4                   0x00000004U

+#define LL_MDMA_CHANNEL_5                   0x00000005U

+#define LL_MDMA_CHANNEL_6                   0x00000006U

+#define LL_MDMA_CHANNEL_7                   0x00000007U

+#define LL_MDMA_CHANNEL_8                   0x00000008U

+#define LL_MDMA_CHANNEL_9                   0x00000009U

+#define LL_MDMA_CHANNEL_10                  0x0000000AU

+#define LL_MDMA_CHANNEL_11                  0x0000000BU

+#define LL_MDMA_CHANNEL_12                  0x0000000CU

+#define LL_MDMA_CHANNEL_13                  0x0000000DU

+#define LL_MDMA_CHANNEL_14                  0x0000000EU

+#define LL_MDMA_CHANNEL_15                  0x0000000FU

+#define LL_MDMA_CHANNEL_ALL                 0xFFFF0000U

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_LL_EC_WORD_ENDIANNESS Word Endianness

+  * @{

+  */

+#define LL_MDMA_WORD_ENDIANNESS_PRESERVE     0x00000000U  /*!< Little endianess preserved for words */

+#define LL_MDMA_WORD_ENDIANNESS_EXCHANGE     MDMA_CCR_WEX /*!< word order exchanged when destination data size is double word  */

+

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_LL_EC_HALFWORD_ENDIANNESS Half Word Endianness

+  * @{

+  */

+#define LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE     0x00000000U  /*!< Little endianess preserved for half words */

+#define LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE     MDMA_CCR_HEX /*!< half word order exchanged when destination data size is word or double word  */

+

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_LL_EC_BYTE_ENDIANNESS Byte Endianness

+  * @{

+  */

+#define LL_MDMA_BYTE_ENDIANNESS_PRESERVE     0x00000000U  /*!< Little endianess preserved for bytes */

+#define LL_MDMA_BYTE_ENDIANNESS_EXCHANGE     MDMA_CCR_BEX /*!< byte order exchanged when destination data size is half word , word or double word  */

+

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_LL_EC_PRIORITY Transfer Priority level

+  * @{

+  */

+#define LL_MDMA_PRIORITY_LOW               0x00000000U               /*!< Priority level : Low       */

+#define LL_MDMA_PRIORITY_MEDIUM            MDMA_CCR_PL_0             /*!< Priority level : Medium    */

+#define LL_MDMA_PRIORITY_HIGH              MDMA_CCR_PL_1             /*!< Priority level : High      */

+#define LL_MDMA_PRIORITY_VERYHIGH          MDMA_CCR_PL               /*!< Priority level : Very_High */

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_LL_EC_BUFF_WRITE_MODE Bufferable Write Mode

+  * @{

+  */

+#define LL_MDMA_BUFF_WRITE_DISABLE         0x00000000U               /*!< destination write operation is non-bufferable */

+#define LL_MDMA_BUFF_WRITE_ENABLE          MDMA_CTCR_BWM             /*!< destination write operation is bufferable     */

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_LL_EC_REQUEST_MODE Request Mode

+  * @{

+  */

+#define LL_MDMA_REQUEST_MODE_HW            0x00000000U               /*!< Request mode is Hardware    */

+#define LL_MDMA_REQUEST_MODE_SW            MDMA_CTCR_SWRM            /*!< Request mode is Software    */

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_LL_EC_TRIGGER_MODE Trigger Mode

+  * @{

+  */

+#define LL_MDMA_BUFFER_TRANSFER          0x00000000U               /*!< Each MDMA request (SW or HW) triggers a buffer transfer */

+#define LL_MDMA_BLOCK_TRANSFER           MDMA_CTCR_TRGM_0          /*!< Each MDMA request (SW or HW) triggers a block transfer */

+#define LL_MDMA_REPEAT_BLOCK_TRANSFER    MDMA_CTCR_TRGM_1          /*!< Each MDMA request (SW or HW) triggers a repeated block transfer */

+#define LL_MDMA_FULL_TRANSFER            MDMA_CTCR_TRGM            /*!< Each MDMA request (SW or HW) triggers a Full transfer or a linked list transfer if any */

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_LL_EC_PADDING_ALIGNMENT_MODE Padding Alignment Mode

+  * @{

+  */

+#define LL_MDMA_DATAALIGN_RIGHT          0x00000000U              /*!< Right Aligned, padded w/ 0s (default) */

+#define LL_MDMA_DATAALIGN_RIGHT_SIGNED   MDMA_CTCR_PAM_0          /*!< Right Aligned, Sign extended ,

+                                                                       Note : this mode is allowed only if the Source data size smaller than Destination data size  */

+#define LL_MDMA_DATAALIGN_LEFT           MDMA_CTCR_PAM_1          /*!< Left Aligned (padded with 0s) */

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_LL_EC_PACKING_MODE Transfer Packing

+  * @{

+  */

+#define LL_MDMA_PACK_DISABLE          0x00000000U              /*!< Packing disabled */

+#define LL_MDMA_PACK_ENABLE           MDMA_CTCR_PKE            /*!< Packing enabled  */

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_LL_EC_DEST_BURST Transfer Destination Burst

+  * @{

+  */

+#define LL_MDMA_DEST_BURST_SINGLE        0x00000000U                               /*!< Single transfer */

+#define LL_MDMA_DEST_BURST_2BEATS        MDMA_CTCR_DBURST_0                        /*!< Burst 2 beats   */

+#define LL_MDMA_DEST_BURST_4BEATS        MDMA_CTCR_DBURST_1                        /*!< Burst 4 beats   */

+#define LL_MDMA_DEST_BURST_8BEATS       (MDMA_CTCR_DBURST_0 | MDMA_CTCR_DBURST_1)  /*!< Burst 8 beats   */

+#define LL_MDMA_DEST_BURST_16BEATS       MDMA_CTCR_DBURST_2                        /*!< Burst 16 beats  */

+#define LL_MDMA_DEST_BURST_32BEATS      (MDMA_CTCR_DBURST_0 | MDMA_CTCR_DBURST_2)  /*!< Burst 32 beats  */

+#define LL_MDMA_DEST_BURST_64BEATS      (MDMA_CTCR_DBURST_1 | MDMA_CTCR_DBURST_2)  /*!< Burst 64 beats  */

+#define LL_MDMA_DEST_BURST_128BEATS     (MDMA_CTCR_DBURST)                         /*!< Burst 128 beats */

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_LL_EC_SRC_BURST Transfer Source Burst

+  * @{

+  */

+#define LL_MDMA_SRC_BURST_SINGLE        0x00000000U                                /*!< Single transfer */

+#define LL_MDMA_SRC_BURST_2BEATS        MDMA_CTCR_SBURST_0                         /*!< Burst 2 beats   */

+#define LL_MDMA_SRC_BURST_4BEATS        MDMA_CTCR_SBURST_1                         /*!< Burst 4 beats   */

+#define LL_MDMA_SRC_BURST_8BEATS       (MDMA_CTCR_SBURST_0 | MDMA_CTCR_SBURST_1)   /*!< Burst 8 beats   */

+#define LL_MDMA_SRC_BURST_16BEATS       MDMA_CTCR_SBURST_2                         /*!< Burst 16 beats  */

+#define LL_MDMA_SRC_BURST_32BEATS      (MDMA_CTCR_SBURST_0 | MDMA_CTCR_SBURST_2)   /*!< Burst 32 beats  */

+#define LL_MDMA_SRC_BURST_64BEATS      (MDMA_CTCR_SBURST_1 | MDMA_CTCR_SBURST_2)   /*!< Burst 64 beats  */

+#define LL_MDMA_SRC_BURST_128BEATS      MDMA_CTCR_SBURST                           /*!< Burst 128 beats */

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_LL_EC_DEST_INC_OFFSET_SIZE Destination Increment Offset Size

+  * @{

+  */

+#define LL_MDMA_DEST_INC_OFFSET_BYTE        0x00000000U                           /*!< offset is Byte (8-bit)         */

+#define LL_MDMA_DEST_INC_OFFSET_HALFWORD    MDMA_CTCR_DINCOS_0                    /*!< offset is Half Word (16-bit)   */

+#define LL_MDMA_DEST_INC_OFFSET_WORD        MDMA_CTCR_DINCOS_1                    /*!< offset is Word (32-bit)        */

+#define LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD  MDMA_CTCR_DINCOS                      /*!< offset is Double Word (64-bit) */

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_LL_EC_SRC_INC_OFFSET_SIZE Source Increment Offset Size

+  * @{

+  */

+#define LL_MDMA_SRC_INC_OFFSET_BYTE        0x00000000U                           /*!< offset is Byte (8-bit)         */

+#define LL_MDMA_SRC_INC_OFFSET_HALFWORD    MDMA_CTCR_SINCOS_0                    /*!< offset is Half Word (16-bit)   */

+#define LL_MDMA_SRC_INC_OFFSET_WORD        MDMA_CTCR_SINCOS_1                    /*!< offset is Word (32-bit)        */

+#define LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD  MDMA_CTCR_SINCOS                      /*!< offset is Double Word (64-bit) */

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_LL_EC_DEST_DATA_SIZE Destination Data Size

+  * @{

+  */

+#define LL_MDMA_DEST_DATA_SIZE_BYTE       0x00000000U                            /*!< Destination data size is Byte        */

+#define LL_MDMA_DEST_DATA_SIZE_HALFWORD   MDMA_CTCR_DSIZE_0                      /*!< Destination data size is half word   */

+#define LL_MDMA_DEST_DATA_SIZE_WORD       MDMA_CTCR_DSIZE_1                      /*!< Destination data size is word        */

+#define LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD MDMA_CTCR_DSIZE                        /*!< Destination data size is double word */

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_LL_EC_SRC_DATA_SIZE Source Data Size

+  * @{

+  */

+#define LL_MDMA_SRC_DATA_SIZE_BYTE       0x00000000U                            /*!< Source data size is Byte        */

+#define LL_MDMA_SRC_DATA_SIZE_HALFWORD   MDMA_CTCR_SSIZE_0                      /*!< Source data size is half word   */

+#define LL_MDMA_SRC_DATA_SIZE_WORD       MDMA_CTCR_SSIZE_1                      /*!< Source data size is word        */

+#define LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD MDMA_CTCR_SSIZE                        /*!< Source data size is double word */

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_LL_EC_DEST_INC_MODE Destination Increment Mode

+  * @{

+  */

+#define LL_MDMA_DEST_FIXED               0x00000000U                            /*!< Destination address pointer is fixed */

+#define LL_MDMA_DEST_INCREMENT           MDMA_CTCR_DINC_1                       /*!< Destination address pointer is incremented after each data transfer */

+#define LL_MDMA_DEST_DECREMENT           MDMA_CTCR_DINC                         /*!< Destination address pointer is decremented after each data transfer */

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_LL_EC_SRC_INC_MODE Source Increment Mode

+  * @{

+  */

+#define LL_MDMA_SRC_FIXED                0x00000000U                            /*!< Destination address pointer is fixed */

+#define LL_MDMA_SRC_INCREMENT            MDMA_CTCR_SINC_1                       /*!< Destination address pointer is incremented after each data transfer */

+#define LL_MDMA_SRC_DECREMENT            MDMA_CTCR_SINC                         /*!< Destination address pointer is decremented after each data transfer */

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE Block Repeat Destination address Update Mode

+  * @{

+  */

+#define LL_MDMA_BLK_RPT_DEST_ADDR_INCREMENT   0x00000000U                       /*!< Destination address pointer is incremented after each block transfer by Destination Update Value */

+#define LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT   MDMA_CBNDTR_BRDUM                 /*!< Destination address pointer is decremented after each block transfer by Destination Update Value */

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_LL_EC_SRC_BLK_RPT_ADDR_UPDATE_MODE Source Block Repeat address Update Mode

+  * @{

+  */

+#define LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT   0x00000000U                        /*!< Source address pointer is incremented after each block transfer by Source Update Value */

+#define LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT   MDMA_CBNDTR_BRSUM                  /*!< Source address pointer is decremented after each block transfer by Source Update Value */

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_LL_EC_DEST_BUS Destination BUS Selection

+  * @{

+  */

+#define  LL_MDMA_DEST_BUS_SYSTEM_AXI    0x00000000U                             /*!< System/AXI bus is used as destination */

+#define  LL_MDMA_DEST_BUS_AHB_TCM       MDMA_CTBR_DBUS                          /*!< AHB bus/TCM is used as destination    */

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_LL_EC_SRC_BUS Source BUS Selection

+  * @{

+  */

+#define LL_MDMA_SRC_BUS_SYSTEM_AXI     0x00000000U                             /*!< System/AXI bus is used as source */

+#define LL_MDMA_SRC_BUS_AHB_TCM        MDMA_CTBR_SBUS                          /*!< AHB bus/TCM is used as source    */

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_LL_EC_HW_TRIGGER_SELCTION HW Trigger Selection

+  * @{

+  */

+#define LL_MDMA_REQ_DMA1_STREAM0_TC          0x00000000U    /*!< MDMA HW Trigger (request) is DMA1 Stream 0 Transfer Complete Flag   */

+#define LL_MDMA_REQ_DMA1_STREAM1_TC          0x00000001U    /*!< MDMA HW Trigger (request) is DMA1 Stream 1 Transfer Complete Flag   */

+#define LL_MDMA_REQ_DMA1_STREAM2_TC          0x00000002U    /*!< MDMA HW Trigger (request) is DMA1 Stream 2 Transfer Complete Flag   */

+#define LL_MDMA_REQ_DMA1_STREAM3_TC          0x00000003U    /*!< MDMA HW Trigger (request) is DMA1 Stream 3 Transfer Complete Flag   */

+#define LL_MDMA_REQ_DMA1_STREAM4_TC          0x00000004U    /*!< MDMA HW Trigger (request) is DMA1 Stream 4 Transfer Complete Flag   */

+#define LL_MDMA_REQ_DMA1_STREAM5_TC          0x00000005U    /*!< MDMA HW Trigger (request) is DMA1 Stream 5 Transfer Complete Flag   */

+#define LL_MDMA_REQ_DMA1_STREAM6_TC          0x00000006U    /*!< MDMA HW Trigger (request) is DMA1 Stream 6 Transfer Complete Flag   */

+#define LL_MDMA_REQ_DMA1_STREAM7_TC          0x00000007U    /*!< MDMA HW Trigger (request) is DMA1 Stream 7 Transfer Complete Flag   */

+#define LL_MDMA_REQ_DMA2_STREAM0_TC          0x00000008U    /*!< MDMA HW Trigger (request) is DMA2 Stream 0 Transfer Complete Flag   */

+#define LL_MDMA_REQ_DMA2_STREAM1_TC          0x00000009U    /*!< MDMA HW Trigger (request) is DMA2 Stream 1 Transfer Complete Flag   */

+#define LL_MDMA_REQ_DMA2_STREAM2_TC          0x0000000AU    /*!< MDMA HW Trigger (request) is DMA2 Stream 2 Transfer Complete Flag   */

+#define LL_MDMA_REQ_DMA2_STREAM3_TC          0x0000000BU    /*!< MDMA HW Trigger (request) is DMA2 Stream 3 Transfer Complete Flag   */

+#define LL_MDMA_REQ_DMA2_STREAM4_TC          0x0000000CU    /*!< MDMA HW Trigger (request) is DMA2 Stream 4 Transfer Complete Flag   */

+#define LL_MDMA_REQ_DMA2_STREAM5_TC          0x0000000DU    /*!< MDMA HW Trigger (request) is DMA2 Stream 5 Transfer Complete Flag   */

+#define LL_MDMA_REQ_DMA2_STREAM6_TC          0x0000000EU    /*!< MDMA HW Trigger (request) is DMA2 Stream 6 Transfer Complete Flag   */

+#define LL_MDMA_REQ_DMA2_STREAM7_TC          0x0000000FU    /*!< MDMA HW Trigger (request) is DMA2 Stream 7 Transfer Complete Flag   */

+#if defined (LTDC)

+#define LL_MDMA_REQ_LTDC_LINE_IT             0x00000010U    /*!< MDMA HW Trigger (request) is LTDC Line interrupt Flag               */

+#endif /* LTDC */

+#if defined (JPEG)

+#define LL_MDMA_REQ_JPEG_INFIFO_TH           0x00000011U    /*!< MDMA HW Trigger (request) is JPEG Input FIFO threshold Flag         */

+#define LL_MDMA_REQ_JPEG_INFIFO_NF           0x00000012U    /*!< MDMA HW Trigger (request) is JPEG Input FIFO not full Flag          */

+#define LL_MDMA_REQ_JPEG_OUTFIFO_TH          0x00000013U    /*!< MDMA HW Trigger (request) is JPEG Output FIFO threshold Flag        */

+#define LL_MDMA_REQ_JPEG_OUTFIFO_NE          0x00000014U    /*!< MDMA HW Trigger (request) is JPEG Output FIFO not empty Flag        */

+#define LL_MDMA_REQ_JPEG_END_CONVERSION      0x00000015U    /*!< MDMA HW Trigger (request) is JPEG End of conversion Flag            */

+#endif /* JPEG */

+#if defined (QUADSPI)

+#define LL_MDMA_REQ_QUADSPI_FIFO_TH          0x00000016U    /*!< MDMA HW Trigger (request) is QSPI FIFO threshold Flag               */

+#define LL_MDMA_REQ_QUADSPI_TC               0x00000017U    /*!< MDMA HW Trigger (request) is QSPI Transfer complete Flag            */

+#endif /* QUADSPI */

+#if defined (OCTOSPI1)

+#define LL_MDMA_REQ_OCTOSPI1_FIFO_TH         0x00000016U    /*!< MDMA HW Trigger (request) is OCTOSPI1 FIFO threshold Flag           */

+#define LL_MDMA_REQ_OCTOSPI1_TC              0x00000017U    /*!< MDMA HW Trigger (request) is OCTOSPI1 Transfer complete Flag        */

+#endif /* OCTOSPI1 */

+#define LL_MDMA_REQ_DMA2D_CLUT_TC            0x00000018U    /*!< MDMA HW Trigger (request) is DMA2D CLUT Transfer Complete Flag      */

+#define LL_MDMA_REQ_DMA2D_TC                 0x00000019U    /*!< MDMA HW Trigger (request) is DMA2D Transfer Complete Flag           */

+#define LL_MDMA_REQ_DMA2D_TW                 0x0000001AU    /*!< MDMA HW Trigger (request) is DMA2D Transfer Watermark Flag          */

+#if defined (DSI)

+#define LL_MDMA_REQ_DSI_TEARING_EFFECT       0x0000001BU    /*!< MDMA HW Trigger (request) is DSI Tearing Effect Flag                */

+#define LL_MDMA_REQ_DSI_END_REFRESH          0x0000001CU    /*!< MDMA HW Trigger (request) is DSI End of refresh  Flag               */

+#endif /* DSI */

+#define LL_MDMA_REQ_SDMMC1_END_DATA          0x0000001DU    /*!< MDMA HW Trigger (request) is SDMMC1 End of Data Flag                */

+#define LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER     0x0000001EU    /*!< MDMA HW Trigger (request) is SDMMC1 Internal DMA buffer End Flag : This trigger is available starting from STM32H7 Rev.B devices */

+#define LL_MDMA_REQ_SDMMC1_COMMAND_END       0x0000001FU    /*!< MDMA HW Trigger (request) is SDMMC1 Command End Flag : This trigger is available starting from STM32H7 Rev.B devices */

+#if defined (OCTOSPI2)

+#define LL_MDMA_REQ_OCTOSPI2_FIFO_TH         0x00000020U    /*!< MDMA HW Trigger (request) is OCTOSPI2 FIFO threshold Flag           */

+#define LL_MDMA_REQ_OCTOSPI2_TC              0x00000021U    /*!< MDMA HW Trigger (request) is OCTOSPI2 Transfer complete Flag        */

+#endif /* OCTOSPI2 */

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_LL_EC_XFER_ERROR_DIRECTION Transfer Error Direction

+  * @{

+  */

+#define LL_MDMA_READ_ERROR                       0x00000000U                /*!< Last transfer error on the channel was a related to a read access    */

+#define LL_MDMA_WRITE_ERROR                      MDMA_CESR_TED              /*!< Last transfer error on the channel was a related to a write access   */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup MDMA_LL_Exported_Macros MDMA Exported Macros

+  * @{

+  */

+

+/** @defgroup MDMA_LL_EM_WRITE_READ Common Write and read registers macros

+  * @{

+  */

+/**

+  * @brief  Write a value in MDMA register

+  * @param  __INSTANCE__ MDMA Instance

+  * @param  __REG__ Register to be written

+  * @param  __VALUE__ Value to be written in the register

+  * @retval None

+  */

+#define LL_MDMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))

+

+/**

+  * @brief  Read a value in MDMA register

+  * @param  __INSTANCE__ MDMA Instance

+  * @param  __REG__ Register to be read

+  * @retval Register value

+  */

+#define LL_MDMA_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_LL_EM_CONVERT_DMAxCHANNELy Convert MDMAxChannely

+  * @{

+  */

+/**

+  * @brief  Convert MDMAx_Channely into MDMAx

+  * @param  __CHANNEL_INSTANCE__ MDMAx_Channely

+  * @retval MDMAx

+  */

+#define LL_MDMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (MDMA)

+

+/**

+  * @brief  Convert MDMAx_Channely into LL_MDMA_CHANNEL_y

+  * @param  __CHANNEL_INSTANCE__ MDMAx_Channely

+  * @retval LL_MDMA_CHANNEL_y

+  */

+#define LL_MDMA_GET_CHANNEL(__CHANNEL_INSTANCE__)   \

+(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel0 )) ? LL_MDMA_CHANNEL_0  : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel1 )) ? LL_MDMA_CHANNEL_1  : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel2 )) ? LL_MDMA_CHANNEL_2  : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel3 )) ? LL_MDMA_CHANNEL_3  : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel4 )) ? LL_MDMA_CHANNEL_4  : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel5 )) ? LL_MDMA_CHANNEL_5  : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel6 )) ? LL_MDMA_CHANNEL_6  : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel7 )) ? LL_MDMA_CHANNEL_7  : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel8 )) ? LL_MDMA_CHANNEL_8  : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel9 )) ? LL_MDMA_CHANNEL_9  : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel10)) ? LL_MDMA_CHANNEL_10 : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel11)) ? LL_MDMA_CHANNEL_11 : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel12)) ? LL_MDMA_CHANNEL_12 : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel13)) ? LL_MDMA_CHANNEL_13 : \

+ ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)MDMA_Channel14)) ? LL_MDMA_CHANNEL_14 : \

+ LL_MDMA_CHANNEL_15)

+

+/**

+  * @brief  Convert MDMA Instance MDMAx and LL_MDMA_CHANNEL_y into MDMAx_Channely

+  * @param  __MDMA_INSTANCE__ MDMAx

+  * @param  __CHANNEL__ LL_MDMA_CHANNEL_y

+  * @retval MDMAx_Channely

+  */

+#define LL_MDMA_GET_CHANNEL_INSTANCE(__MDMA_INSTANCE__, __CHANNEL__)   \

+(((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_0 )) ? MDMA_Channel0  : \

+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_1 )) ? MDMA_Channel1  : \

+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_2 )) ? MDMA_Channel2  : \

+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_3 )) ? MDMA_Channel3  : \

+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_4 )) ? MDMA_Channel4  : \

+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_5 )) ? MDMA_Channel5  : \

+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_6 )) ? MDMA_Channel6  : \

+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_7 )) ? MDMA_Channel7  : \

+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_8 )) ? MDMA_Channel8  : \

+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_9 )) ? MDMA_Channel9  : \

+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_10)) ? MDMA_Channel10 : \

+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_11)) ? MDMA_Channel11 : \

+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_12)) ? MDMA_Channel12 : \

+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_13)) ? MDMA_Channel13 : \

+ ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_MDMA_CHANNEL_14)) ? MDMA_Channel14 : \

+ MDMA_Channel15)

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+

+/* Exported functions --------------------------------------------------------*/

+ /** @defgroup MDMA_LL_Exported_Functions MDMA Exported Functions

+  * @{

+  */

+

+/** @defgroup MDMA_LL_EF_Configuration Configuration

+  * @{

+  */

+/**

+  * @brief Enable MDMA channel.

+  * @rmtoll CCR          EN            LL_MDMA_EnableChannel

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_EnableChannel(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  SET_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_EN);

+}

+

+/**

+  * @brief Disable MDMA channel.

+  * @rmtoll CCR          EN            LL_MDMA_DisableChannel

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_DisableChannel(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  CLEAR_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_EN);

+}

+

+/**

+  * @brief Check if MDMA channel is enabled or disabled.

+  * @rmtoll CCR          EN            LL_MDMA_IsEnabledChannel

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_MDMA_IsEnabledChannel(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_EN) == (MDMA_CCR_EN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Generate a SW transfer request on the MDMA channel.

+  * @rmtoll CCR          SWRQ            LL_MDMA_GenerateSWRequest

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_GenerateSWRequest(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  SET_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_SWRQ);

+}

+

+/**

+  * @brief Configure Transfer endianness paremeters : Word, Half word and Bytes Endianess.

+  * @rmtoll CCR          WEX            LL_MDMA_ConfigXferEndianness\n

+  * @rmtoll CCR          HEX            LL_MDMA_ConfigXferEndianness\n

+  * @rmtoll CCR          BEX            LL_MDMA_ConfigXferEndianness

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  Configuration This parameter must be a combination of all the following values:

+  *         @arg @ref LL_MDMA_WORD_ENDIANNESS_PRESERVE or @ref LL_MDMA_WORD_ENDIANNESS_EXCHANGE

+  *         @arg @ref LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE or @ref LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE

+  *         @arg @ref LL_MDMA_BYTE_ENDIANNESS_PRESERVE or @ref LL_MDMA_BYTE_ENDIANNESS_EXCHANGE

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_ConfigXferEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR,

+             MDMA_CCR_WEX | MDMA_CCR_HEX | MDMA_CCR_BEX, Configuration);

+}

+

+/**

+  * @brief Set Words Endianess.

+  * @rmtoll CCR          WEX            LL_MDMA_SetWordEndianness

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  Endianness This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_WORD_ENDIANNESS_PRESERVE

+  *         @arg @ref LL_MDMA_WORD_ENDIANNESS_EXCHANGE

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_SetWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_WEX, Endianness);

+}

+

+/**

+  * @brief Get Words Endianess.

+  * @rmtoll CCR          WEX            LL_MDMA_GetWordEndianness

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_MDMA_WORD_ENDIANNESS_PRESERVE

+  *         @arg @ref LL_MDMA_WORD_ENDIANNESS_EXCHANGE

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_WEX));

+}

+

+/**

+  * @brief Set Half Words Endianess.

+  * @rmtoll CCR          HEX            LL_MDMA_SetHalfWordEndianness

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  Endianness This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE

+  *         @arg @ref LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_SetHalfWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_HEX, Endianness);

+}

+

+/**

+  * @brief Get Half Words Endianess.

+  * @rmtoll CCR          HEX            LL_MDMA_GetHalfWordEndianness

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_MDMA_HALFWORD_ENDIANNESS_PRESERVE

+  *         @arg @ref LL_MDMA_HALFWORD_ENDIANNESS_EXCHANGE

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetHalfWordEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_HEX));

+}

+

+/**

+  * @brief Set Bytes Endianess.

+  * @rmtoll CCR          BEX            LL_MDMA_SetByteEndianness

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  Endianness This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_BYTE_ENDIANNESS_PRESERVE

+  *         @arg @ref LL_MDMA_BYTE_ENDIANNESS_EXCHANGE

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_SetByteEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Endianness)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_BEX, Endianness);

+}

+

+/**

+  * @brief Get Bytes Endianess.

+  * @rmtoll CCR          BEX            LL_MDMA_GetByteEndianness

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_MDMA_BYTE_ENDIANNESS_PRESERVE

+  *         @arg @ref LL_MDMA_BYTE_ENDIANNESS_EXCHANGE

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetByteEndianness(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_BEX));

+}

+

+/**

+  * @brief Set Channel priority level.

+  * @rmtoll CCR          PL            LL_MDMA_SetChannelPriorityLevel

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  Priority This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_PRIORITY_LOW

+  *         @arg @ref LL_MDMA_PRIORITY_MEDIUM

+  *         @arg @ref LL_MDMA_PRIORITY_HIGH

+  *         @arg @ref LL_MDMA_PRIORITY_VERYHIGH

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_SetChannelPriorityLevel(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Priority)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_PL, Priority);

+}

+

+/**

+  * @brief Get Channel priority level.

+  * @rmtoll CCR          PL            LL_MDMA_GetChannelPriorityLevel

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_MDMA_PRIORITY_LOW

+  *         @arg @ref LL_MDMA_PRIORITY_MEDIUM

+  *         @arg @ref LL_MDMA_PRIORITY_HIGH

+  *         @arg @ref LL_MDMA_PRIORITY_VERYHIGH

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetChannelPriorityLevel(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR, MDMA_CCR_PL));

+}

+

+/**

+  * @brief Configure MDMA transfer parameters.

+  * @rmtoll CTCR          BWM            LL_MDMA_ConfigTransfer\n

+  * @rmtoll CTCR          SWRM           LL_MDMA_ConfigTransfer\n

+  * @rmtoll CTCR          TRGM           LL_MDMA_ConfigTransfer\n

+  * @rmtoll CTCR          PAM            LL_MDMA_ConfigTransfer\n

+  * @rmtoll CTCR          PKE            LL_MDMA_ConfigTransfer\n

+  * @rmtoll CTCR          TLEN           LL_MDMA_ConfigTransfer\n

+  * @rmtoll CTCR          DBURST         LL_MDMA_ConfigTransfer\n

+  * @rmtoll CTCR          SBURST         LL_MDMA_ConfigTransfer\n

+  * @rmtoll CTCR          DINCOS         LL_MDMA_ConfigTransfer\n

+  * @rmtoll CTCR          SINCOS         LL_MDMA_ConfigTransfer\n

+  * @rmtoll CTCR          DSIZE          LL_MDMA_ConfigTransfer\n

+  * @rmtoll CTCR          SSIZE          LL_MDMA_ConfigTransfer\n

+  * @rmtoll CTCR          DINC           LL_MDMA_ConfigTransfer\n

+  * @rmtoll CTCR          SINC           LL_MDMA_ConfigTransfer

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  Configuration This parameter must be a combination of all the following values:

+  *         @arg @ref LL_MDMA_BUFF_WRITE_DISABLE or @ref LL_MDMA_BUFF_WRITE_ENABLE

+  *         @arg @ref LL_MDMA_REQUEST_MODE_HW or @ref LL_MDMA_REQUEST_MODE_SW

+  *         @arg @ref LL_MDMA_BUFFER_TRANSFER or @ref LL_MDMA_BLOCK_TRANSFER or @ref LL_MDMA_REPEAT_BLOCK_TRANSFER or @ref LL_MDMA_FULL_TRANSFER

+  *         @arg @ref LL_MDMA_DATAALIGN_RIGHT or @ref LL_MDMA_DATAALIGN_RIGHT_SIGNED or @ref LL_MDMA_DATAALIGN_LEFT

+  *         @arg @ref LL_MDMA_PACK_DISABLE or @ref LL_MDMA_PACK_ENABLE

+  *         @arg @ref LL_MDMA_DEST_BURST_SINGLE or @ref LL_MDMA_DEST_BURST_2BEATS or @ref LL_MDMA_DEST_BURST_4BEATS or @ref LL_MDMA_DEST_BURST_8BEATS

+  *              or @ref LL_MDMA_DEST_BURST_16BEATS or @ref LL_MDMA_DEST_BURST_32BEATS or @ref LL_MDMA_DEST_BURST_64BEATS or @ref LL_MDMA_DEST_BURST_128BEATS

+  *         @arg @ref LL_MDMA_SRC_BURST_SINGLE or @ref LL_MDMA_SRC_BURST_2BEATS or @ref LL_MDMA_SRC_BURST_4BEATS or @ref LL_MDMA_SRC_BURST_8BEATS

+  *              or @ref LL_MDMA_SRC_BURST_16BEATS or @ref LL_MDMA_SRC_BURST_32BEATS or @ref LL_MDMA_SRC_BURST_64BEATS or @ref LL_MDMA_SRC_BURST_128BEATS

+  *         @arg @ref LL_MDMA_DEST_INC_OFFSET_BYTE or @ref LL_MDMA_DEST_INC_OFFSET_HALFWORD or @ref LL_MDMA_DEST_INC_OFFSET_WORD or @ref LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD

+  *         @arg @ref LL_MDMA_SRC_INC_OFFSET_BYTE or @ref LL_MDMA_SRC_INC_OFFSET_HALFWORD or @ref LL_MDMA_SRC_INC_OFFSET_WORD or @ref LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD

+  *         @arg @ref LL_MDMA_DEST_DATA_SIZE_BYTE or @ref LL_MDMA_DEST_DATA_SIZE_HALFWORD or @ref LL_MDMA_DEST_DATA_SIZE_WORD or @ref LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD

+  *         @arg @ref LL_MDMA_SRC_DATA_SIZE_BYTE or @ref LL_MDMA_SRC_DATA_SIZE_HALFWORD or @ref LL_MDMA_SRC_DATA_SIZE_WORD or @ref LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD

+  *         @arg @ref LL_MDMA_DEST_FIXED or @ref LL_MDMA_DEST_INCREMENT or @ref LL_MDMA_DEST_DECREMENT

+  *         @arg @ref LL_MDMA_SRC_FIXED or @ref LL_MDMA_SRC_INCREMENT or @ref LL_MDMA_SRC_DECREMENT

+  * @param  BufferXferLength This parameter can be a value Between 0 to 0x0000007F

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_ConfigTransfer(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration, uint32_t BufferXferLength)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR,

+  Configuration | ((BufferXferLength << MDMA_CTCR_TLEN_Pos) & MDMA_CTCR_TLEN_Msk));

+}

+

+/**

+  * @brief Enable Bufferable Write Mode.

+  * @rmtoll CTCR          BWM            LL_MDMA_EnableBufferableWrMode

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_EnableBufferableWrMode(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  SET_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_BWM);

+}

+

+/**

+  * @brief Disable Bufferable Write Mode.

+  * @rmtoll CTCR          BWM            LL_MDMA_DisableBufferableWrMode

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_DisableBufferableWrMode(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  CLEAR_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_BWM);

+}

+

+/**

+  * @brief Check if Bufferable Write Mode is enabled or disabled.

+  * @rmtoll CTCR          BWM            LL_MDMA_IsEnabledBufferableWrMode

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_MDMA_IsEnabledBufferableWrMode(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_BWM) == (MDMA_CTCR_BWM)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Set Request Mode.

+  * @rmtoll CTCR          SWRM            LL_MDMA_SetRequestMode

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  RequestMode This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_REQUEST_MODE_HW

+  *         @arg @ref LL_MDMA_REQUEST_MODE_SW

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_SetRequestMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t RequestMode)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SWRM, RequestMode);

+}

+

+/**

+  * @brief Get Request Mode.

+  * @rmtoll CTCR          SWRM            LL_MDMA_GetRequestMode

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_MDMA_REQUEST_MODE_HW

+  *         @arg @ref LL_MDMA_REQUEST_MODE_SW

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetRequestMode(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SWRM));

+}

+

+/**

+  * @brief Set Trigger Mode.

+  * @rmtoll CTCR          TRGM            LL_MDMA_SetTriggerMode

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  TriggerMode This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_BUFFER_TRANSFER

+  *         @arg @ref LL_MDMA_BLOCK_TRANSFER

+  *         @arg @ref LL_MDMA_REPEAT_BLOCK_TRANSFER

+  *         @arg @ref LL_MDMA_FULL_TRANSFER

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_SetTriggerMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t TriggerMode)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_TRGM, TriggerMode);

+}

+

+/**

+  * @brief Get Trigger Mode.

+  * @rmtoll CTCR          TRGM            LL_MDMA_GetTriggerMode

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_MDMA_BUFFER_TRANSFER

+  *         @arg @ref LL_MDMA_BLOCK_TRANSFER

+  *         @arg @ref LL_MDMA_REPEAT_BLOCK_TRANSFER

+  *         @arg @ref LL_MDMA_FULL_TRANSFER

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetTriggerMode(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_TRGM));

+}

+

+/**

+  * @brief Set Padding Alignment.

+  * @rmtoll CTCR          PAM            LL_MDMA_SetPaddingAlignment

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  PaddingAlignment This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_DATAALIGN_RIGHT

+  *         @arg @ref LL_MDMA_DATAALIGN_RIGHT_SIGNED

+  *         @arg @ref LL_MDMA_DATAALIGN_LEFT

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_SetPaddingAlignment(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t PaddingAlignment)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_PAM, PaddingAlignment);

+}

+

+/**

+  * @brief Get Padding Alignment.

+  * @rmtoll CTCR          PAM            LL_MDMA_GetPaddingAlignment

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_MDMA_DATAALIGN_RIGHT

+  *         @arg @ref LL_MDMA_DATAALIGN_RIGHT_SIGNED

+  *         @arg @ref LL_MDMA_DATAALIGN_LEFT

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetPaddingAlignment(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_PAM));

+}

+

+

+/**

+  * @brief Enable Packing.

+  * @rmtoll CTCR          PKE            LL_MDMA_EnablePacking

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_EnablePacking(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  SET_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_PKE);

+}

+

+/**

+  * @brief Disable Packing.

+  * @rmtoll CTCR          PKE            LL_MDMA_DisablePacking

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_DisablePacking(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  CLEAR_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_PKE);

+}

+

+/**

+  * @brief Check if packing is enabled or disabled.

+  * @rmtoll CTCR          PKE            LL_MDMA_IsEnabledPacking

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_MDMA_IsEnabledPacking(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_PKE) == (MDMA_CTCR_PKE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Set Buffer Transfer Length.

+  * @rmtoll CTCR          TLEN            LL_MDMA_SetBufferTransferLength

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  Length Between 0 to 0x0000007F

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_SetBufferTransferLength(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Length)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_TLEN,

+              (Length << MDMA_CTCR_TLEN_Pos) & MDMA_CTCR_TLEN_Msk);

+}

+

+/**

+  * @brief Get Buffer Transfer Length.

+  * @rmtoll CTCR          TLEN            LL_MDMA_GetBufferTransferLength

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Between 0 to 0x0000007F

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetBufferTransferLength(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return(READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_TLEN) >> MDMA_CTCR_TLEN_Pos);

+}

+

+/**

+  * @brief Set Destination burst transfer.

+  * @rmtoll CTCR          DBURST            LL_MDMA_SetDestinationBurstSize

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  Dburst This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_DEST_BURST_SINGLE

+  *         @arg @ref LL_MDMA_DEST_BURST_2BEATS

+  *         @arg @ref LL_MDMA_DEST_BURST_4BEATS

+  *         @arg @ref LL_MDMA_DEST_BURST_8BEATS

+  *         @arg @ref LL_MDMA_DEST_BURST_16BEATS

+  *         @arg @ref LL_MDMA_DEST_BURST_32BEATS

+  *         @arg @ref LL_MDMA_DEST_BURST_64BEATS

+  *         @arg @ref LL_MDMA_DEST_BURST_128BEATS

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_SetDestinationBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Dburst)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DBURST, Dburst);

+}

+

+/**

+  * @brief Get Destination burst transfer.

+  * @rmtoll CTCR          DBURST            LL_MDMA_GetDestinationBurstSize

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_MDMA_DEST_BURST_SINGLE

+  *         @arg @ref LL_MDMA_DEST_BURST_2BEATS

+  *         @arg @ref LL_MDMA_DEST_BURST_4BEATS

+  *         @arg @ref LL_MDMA_DEST_BURST_8BEATS

+  *         @arg @ref LL_MDMA_DEST_BURST_16BEATS

+  *         @arg @ref LL_MDMA_DEST_BURST_32BEATS

+  *         @arg @ref LL_MDMA_DEST_BURST_64BEATS

+  *         @arg @ref LL_MDMA_DEST_BURST_128BEATS

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetDestinationBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return(READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DBURST));

+}

+

+/**

+  * @brief Set Source burst transfer.

+  * @rmtoll CTCR          SBURST            LL_MDMA_SetSourceBurstSize

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  Sburst This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_SRC_BURST_SINGLE

+  *         @arg @ref LL_MDMA_SRC_BURST_2BEATS

+  *         @arg @ref LL_MDMA_SRC_BURST_4BEATS

+  *         @arg @ref LL_MDMA_SRC_BURST_8BEATS

+  *         @arg @ref LL_MDMA_SRC_BURST_16BEATS

+  *         @arg @ref LL_MDMA_SRC_BURST_32BEATS

+  *         @arg @ref LL_MDMA_SRC_BURST_64BEATS

+  *         @arg @ref LL_MDMA_SRC_BURST_128BEATS

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_SetSourceBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Sburst)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SBURST, Sburst);

+}

+

+/**

+  * @brief Get Source burst transfer.

+  * @rmtoll CTCR          SBURST            LL_MDMA_GetSourceBurstSize

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_MDMA_SRC_BURST_SINGLE

+  *         @arg @ref LL_MDMA_SRC_BURST_2BEATS

+  *         @arg @ref LL_MDMA_SRC_BURST_4BEATS

+  *         @arg @ref LL_MDMA_SRC_BURST_8BEATS

+  *         @arg @ref LL_MDMA_SRC_BURST_16BEATS

+  *         @arg @ref LL_MDMA_SRC_BURST_32BEATS

+  *         @arg @ref LL_MDMA_SRC_BURST_64BEATS

+  *         @arg @ref LL_MDMA_SRC_BURST_128BEATS

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetSourceBurstSize(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return(READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SBURST));

+}

+

+/**

+  * @brief Set Destination Increment Offset Size.

+  * @rmtoll CTCR          DINCOS            LL_MDMA_SetDestinationIncSize

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  IncSize This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_DEST_INC_OFFSET_BYTE

+  *         @arg @ref LL_MDMA_DEST_INC_OFFSET_HALFWORD

+  *         @arg @ref LL_MDMA_DEST_INC_OFFSET_WORD

+  *         @arg @ref LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_SetDestinationIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t IncSize)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DINCOS, IncSize);

+}

+

+/**

+  * @brief Get Destination Increment Offset Size.

+  * @rmtoll CTCR          DINCOS            LL_MDMA_GetDestinationIncSize

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_MDMA_DEST_INC_OFFSET_BYTE

+  *         @arg @ref LL_MDMA_DEST_INC_OFFSET_HALFWORD

+  *         @arg @ref LL_MDMA_DEST_INC_OFFSET_WORD

+  *         @arg @ref LL_MDMA_DEST_INC_OFFSET_DOUBLEWORD

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DINCOS));

+}

+

+/**

+  * @brief Set Source Increment Offset Size.

+  * @rmtoll CTCR          SINCOS            LL_MDMA_SetSourceIncSize

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  IncSize This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_SRC_INC_OFFSET_BYTE

+  *         @arg @ref LL_MDMA_SRC_INC_OFFSET_HALFWORD

+  *         @arg @ref LL_MDMA_SRC_INC_OFFSET_WORD

+  *         @arg @ref LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_SetSourceIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t IncSize)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SINCOS, IncSize);

+}

+

+/**

+  * @brief Get Source Increment Offset Size.

+  * @rmtoll CTCR          SINCOS            LL_MDMA_GetSourceIncSize

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_MDMA_SRC_INC_OFFSET_BYTE

+  *         @arg @ref LL_MDMA_SRC_INC_OFFSET_HALFWORD

+  *         @arg @ref LL_MDMA_SRC_INC_OFFSET_WORD

+  *         @arg @ref LL_MDMA_SRC_INC_OFFSET_DOUBLEWORD

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetSourceIncSize(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SINCOS));

+}

+

+/**

+  * @brief Set Destination Data Size.

+  * @rmtoll CTCR          DSIZE            LL_MDMA_SetDestinationDataSize

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  DestDataSize This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_DEST_DATA_SIZE_BYTE

+  *         @arg @ref LL_MDMA_DEST_DATA_SIZE_HALFWORD

+  *         @arg @ref LL_MDMA_DEST_DATA_SIZE_WORD

+  *         @arg @ref LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_SetDestinationDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestDataSize)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DSIZE, DestDataSize);

+}

+

+/**

+  * @brief Get Destination Data Size.

+  * @rmtoll CTCR          DSIZE            LL_MDMA_GetDestinationDataSize

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_MDMA_DEST_DATA_SIZE_BYTE

+  *         @arg @ref LL_MDMA_DEST_DATA_SIZE_HALFWORD

+  *         @arg @ref LL_MDMA_DEST_DATA_SIZE_WORD

+  *         @arg @ref LL_MDMA_DEST_DATA_SIZE_DOUBLEWORD

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetDestinationDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DSIZE));

+}

+

+/**

+  * @brief Set Source Data Size.

+  * @rmtoll CTCR          SSIZE            LL_MDMA_SetSourceDataSize

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  SrcDataSize This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_SRC_DATA_SIZE_BYTE

+  *         @arg @ref LL_MDMA_SRC_DATA_SIZE_HALFWORD

+  *         @arg @ref LL_MDMA_SRC_DATA_SIZE_WORD

+  *         @arg @ref LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_SetSourceDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcDataSize)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SSIZE, SrcDataSize);

+}

+

+/**

+  * @brief Get Source Data Size.

+  * @rmtoll CTCR          SSIZE            LL_MDMA_GetSourceDataSize

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_MDMA_SRC_DATA_SIZE_BYTE

+  *         @arg @ref LL_MDMA_SRC_DATA_SIZE_HALFWORD

+  *         @arg @ref LL_MDMA_SRC_DATA_SIZE_WORD

+  *         @arg @ref LL_MDMA_SRC_DATA_SIZE_DOUBLEWORD

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetSourceDataSize(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SSIZE));

+}

+

+/**

+  * @brief Set Destination Increment Mode.

+  * @rmtoll CTCR          DINC            LL_MDMA_SetDestinationIncMode

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  DestIncMode This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_DEST_FIXED

+  *         @arg @ref LL_MDMA_DEST_INCREMENT

+  *         @arg @ref LL_MDMA_DEST_DECREMENT

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_SetDestinationIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestIncMode)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DINC, DestIncMode);

+}

+

+/**

+  * @brief Get Destination Increment Mode.

+  * @rmtoll CTCR          DINC            LL_MDMA_GetDestinationIncMode

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_MDMA_DEST_FIXED

+  *         @arg @ref LL_MDMA_DEST_INCREMENT

+  *         @arg @ref LL_MDMA_DEST_DECREMENT

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetDestinationIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_DINC));

+}

+

+/**

+  * @brief Set Source Increment Mode.

+  * @rmtoll CTCR          SINC            LL_MDMA_SetSourceIncMode

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  SrcIncMode This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_SRC_FIXED

+  *         @arg @ref LL_MDMA_SRC_INCREMENT

+  *         @arg @ref LL_MDMA_SRC_DECREMENT

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_SetSourceIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcIncMode)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SINC, SrcIncMode);

+}

+

+/**

+  * @brief Get Source Increment Mode.

+  * @rmtoll CTCR          SINC            LL_MDMA_GetSourceIncMode

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_MDMA_SRC_FIXED

+  *         @arg @ref LL_MDMA_SRC_INCREMENT

+  *         @arg @ref LL_MDMA_SRC_DECREMENT

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetSourceIncMode(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTCR, MDMA_CTCR_SINC));

+}

+

+/**

+  * @brief Configure MDMA Block number of data and repeat Count.

+  * @rmtoll CBNDTR        BRC            LL_MDMA_ConfigBlkCounters\n

+  * @rmtoll CBNDTR        BNDT           LL_MDMA_ConfigBlkCounters

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  BlockRepeatCount Between 0 to 0x00000FFF

+  * @param  BlkDataLength Between 0 to 0x00010000

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_ConfigBlkCounters(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlockRepeatCount, uint32_t BlkDataLength)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR,

+               MDMA_CBNDTR_BRC | MDMA_CBNDTR_BNDT,

+              ((BlockRepeatCount << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC_Msk) | (BlkDataLength & MDMA_CBNDTR_BNDT_Msk));

+}

+

+/**

+  * @brief Set Block Number of data bytes to transfer.

+  * @rmtoll CBNDTR          BNDT            LL_MDMA_SetBlkDataLength

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  BlkDataLength Between 0 to 0x00010000

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_SetBlkDataLength(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlkDataLength)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BNDT, (BlkDataLength & MDMA_CBNDTR_BNDT_Msk));

+}

+

+/**

+  * @brief Get Block Number of data bytes to transfer.

+  * @rmtoll CBNDTR          BNDT            LL_MDMA_GetBlkDataLength

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Between 0 to 0x00010000

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetBlkDataLength(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BNDT));

+}

+

+/**

+  * @brief Set Block Repeat Count.

+  * @rmtoll CBNDTR          BRC            LL_MDMA_SetBlkRepeatCount

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  BlockRepeatCount Between 0 to 0x00000FFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_SetBlkRepeatCount(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t BlockRepeatCount)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BRC,

+              (BlockRepeatCount << MDMA_CBNDTR_BRC_Pos) & MDMA_CBNDTR_BRC_Msk);

+}

+

+/**

+  * @brief Get Block Repeat Count.

+  * @rmtoll CBNDTR          BRC            LL_MDMA_GetBlkRepeatCount

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Between 0 to 0x00000FFF

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatCount(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BRC) >> MDMA_CBNDTR_BRC_Pos);

+}

+

+/**

+  * @brief Configure MDMA block repeat address update mode.

+  * @rmtoll CBNDTR        BRDUM            LL_MDMA_ConfigBlkRepeatAddrUpdate\n

+  * @rmtoll CBNDTR        BRSUM            LL_MDMA_ConfigBlkRepeatAddrUpdate

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  Configuration This parameter must be a combination of all the following values:

+  *         @arg @ref LL_MDMA_BLK_RPT_DEST_ADDR_INCREMENT or @ref LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT

+  *         @arg @ref LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT or @ref LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_ConfigBlkRepeatAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR,

+               MDMA_CBNDTR_BRDUM | MDMA_CBNDTR_BRSUM,

+               Configuration);

+}

+

+/**

+  * @brief Set Block Repeat Destination address Update Mode.

+  * @rmtoll CBNDTR          BRDUM            LL_MDMA_SetBlkRepeatDestAddrUpdate

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  DestAdrUpdateMode This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_BLK_RPT_DEST_ADDR_INCREMENT

+  *         @arg @ref LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_SetBlkRepeatDestAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAdrUpdateMode)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BRDUM, DestAdrUpdateMode);

+}

+

+/**

+  * @brief Get Block Repeat Destination address Update Mode.

+  * @rmtoll CBNDTR          BRDUM            LL_MDMA_GetBlkRepeatDestAddrUpdate

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_MDMA_BLK_RPT_DEST_ADDR_INCREMENT

+  *         @arg @ref LL_MDMA_BLK_RPT_DEST_ADDR_DECREMENT

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatDestAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BRDUM));

+}

+

+/**

+  * @brief Set Block Repeat Source address Update Mode.

+  * @rmtoll CBNDTR          BRSUM            LL_MDMA_SetBlkRepeatSrcAddrUpdate

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  SrcAdrUpdateMode This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT

+  *         @arg @ref LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_SetBlkRepeatSrcAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAdrUpdateMode)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BRSUM, SrcAdrUpdateMode);

+}

+

+/**

+  * @brief Get Block Repeat Source address Update Mode.

+  * @rmtoll CBNDTR          BRSUM            LL_MDMA_GetBlkRepeatSrcAddrUpdate

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_MDMA_BLK_RPT_SRC_ADDR_INCREMENT

+  *         @arg @ref LL_MDMA_BLK_RPT_SRC_ADDR_DECREMENT

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetBlkRepeatSrcAddrUpdate(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBNDTR, MDMA_CBNDTR_BRSUM));

+}

+

+/**

+  * @brief  Configure the Source and Destination addresses.

+  * @note   This API must not be called when the MDMA channel is enabled.

+  * @rmtoll CSAR        SAR            LL_MDMA_ConfigAddresses\n

+  * @rmtoll CDAR        DAR            LL_MDMA_ConfigAddresses

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

+  * @param  DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_ConfigAddresses(MDMA_TypeDef *MDMAx, uint32_t Channel,  uint32_t SrcAddress, uint32_t DstAddress)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress);

+  WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CDAR, DstAddress);

+}

+/**

+  * @brief Set transfer Source address.

+  * @rmtoll CSAR          SAR            LL_MDMA_SetSourceAddress

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  SrcAddress Between 0 to 0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_SetSourceAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAddress)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress);

+}

+

+/**

+  * @brief Get transfer Source address.

+  * @rmtoll CSAR          SAR            LL_MDMA_GetSourceAddress

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Between 0 to 0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetSourceAddress(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return (READ_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CSAR));

+}

+

+/**

+  * @brief Set transfer Destination address.

+  * @rmtoll CDAR          DAR            LL_MDMA_SetDestinationAddress

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  DestAddress Between 0 to 0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_SetDestinationAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAddress)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress);

+}

+

+/**

+  * @brief Get transfer Destination address.

+  * @rmtoll CDAR          DAR            LL_MDMA_GetDestinationAddress

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Between 0 to 0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetDestinationAddress(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return (READ_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CDAR));

+}

+

+/**

+  * @brief  Configure the Source and Destination Block repeat addresses Update value.

+  * @note   This API must not be called when the MDMA channel is enabled.

+  * @rmtoll CBRUR        DUV            LL_MDMA_ConfigBlkRptAddrUpdateValue\n

+  * @rmtoll CBRUR        SUV            LL_MDMA_ConfigBlkRptAddrUpdateValue

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  SrctAdrUpdateValue Min_Data = 0 and Max_Data = 0x0000FFFF

+  * @param  DestAdrUpdateValue Between Min_Data = 0 and Max_Data = 0x0000FFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_ConfigBlkRptAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel,  uint32_t SrctAdrUpdateValue, uint32_t DestAdrUpdateValue)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBRUR,

+              (SrctAdrUpdateValue & MDMA_CBRUR_SUV_Msk)  | ((DestAdrUpdateValue << MDMA_CBRUR_DUV_Pos) & MDMA_CBRUR_DUV_Msk));

+}

+

+/**

+  * @brief Set transfer Destination address Update Value.

+  * @rmtoll CBRUR          DUV            LL_MDMA_SetBlkRptDestAddrUpdateValue

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  DestAdrUpdateValue Between 0 to 0x0000FFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_SetBlkRptDestAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestAdrUpdateValue)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBRUR, MDMA_CBRUR_DUV,

+               ((DestAdrUpdateValue << MDMA_CBRUR_DUV_Pos) & MDMA_CBRUR_DUV_Msk));

+}

+

+/**

+  * @brief Get transfer Destination address Update Value.

+  * @rmtoll CBRUR          DUV            LL_MDMA_GetBlkRptDestAddrUpdateValue

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Between 0 to 0x0000FFFF

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetBlkRptDestAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBRUR, MDMA_CBRUR_DUV) >> MDMA_CBRUR_DUV_Pos);

+}

+

+/**

+  * @brief Set transfer Source address Update Value.

+  * @rmtoll CBRUR          SUV            LL_MDMA_SetBlkRptSrcAddrUpdateValue

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  SrcAdrUpdateValue Between 0 to 0x0000FFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_SetBlkRptSrcAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcAdrUpdateValue)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBRUR, MDMA_CBRUR_SUV, SrcAdrUpdateValue);

+}

+

+/**

+  * @brief Get transfer Source address Update Value.

+  * @rmtoll CBRUR          SUV            LL_MDMA_GetBlkRptSrcAddrUpdateValue

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Between 0 to 0x0000FFFF

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetBlkRptSrcAddrUpdateValue(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CBRUR, MDMA_CBRUR_SUV));

+}

+

+/**

+  * @brief Set transfer Link Address.

+  * @rmtoll CLAR          LAR            LL_MDMA_SetLinkAddress

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  LinkAddress Between 0 to 0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_SetLinkAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t LinkAddress)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CLAR, LinkAddress);

+}

+

+/**

+  * @brief Get transfer Link Address.

+  * @rmtoll CLAR          LAR            LL_MDMA_GetLinkAddress

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Between 0 to 0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetLinkAddress(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return (READ_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CLAR));

+}

+

+/**

+  * @brief Configure MDMA source and destination bus selection.

+  * @rmtoll CTBR        DBUS            LL_MDMA_ConfigBusSelection\n

+  * @rmtoll CTBR        SBUS            LL_MDMA_ConfigBusSelection

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  Configuration This parameter must be a combination of all the following values:

+  *         @arg @ref LL_MDMA_DEST_BUS_SYSTEM_AXI or @ref LL_MDMA_DEST_BUS_AHB_TCM

+  *         @arg @ref LL_MDMA_SRC_BUS_SYSTEM_AXI or @ref LL_MDMA_SRC_BUS_AHB_TCM

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_ConfigBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t Configuration)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTBR,

+               MDMA_CTBR_DBUS | MDMA_CTBR_SBUS,

+              Configuration);

+}

+

+/**

+  * @brief Set Destination Bus Selection.

+  * @rmtoll CTBR          DBUS            LL_MDMA_SetDestBusSelection

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  DestBus This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_DEST_BUS_SYSTEM_AXI

+  *         @arg @ref LL_MDMA_DEST_BUS_AHB_TCM

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_SetDestBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t DestBus)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTBR, MDMA_CTBR_DBUS, DestBus);

+}

+

+/**

+  * @brief Get Destination Bus Selection.

+  * @rmtoll CTBR          DBUS            LL_MDMA_GetDestBusSelection

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_MDMA_DEST_BUS_SYSTEM_AXI

+  *         @arg @ref LL_MDMA_DEST_BUS_AHB_TCM

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetDestBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTBR, MDMA_CTBR_DBUS));

+}

+

+/**

+  * @brief Set Source Bus Selection.

+  * @rmtoll CTBR          SBUS            LL_MDMA_SetSrcBusSelection

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  SrcBus This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_SRC_BUS_SYSTEM_AXI

+  *         @arg @ref LL_MDMA_SRC_BUS_AHB_TCM

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_SetSrcBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t SrcBus)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTBR, MDMA_CTBR_SBUS, SrcBus);

+}

+

+/**

+  * @brief Get Source Bus Selection.

+  * @rmtoll CTBR          SBUS            LL_MDMA_GetSrcBusSelection

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_MDMA_SRC_BUS_SYSTEM_AXI

+  *         @arg @ref LL_MDMA_SRC_BUS_AHB_TCM

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetSrcBusSelection(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTBR, MDMA_CTBR_SBUS));

+}

+

+/**

+  * @brief Set Transfer hardware trigger (Request).

+  * @rmtoll CTBR          TSEL            LL_MDMA_SetHWTrigger

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  HWRequest This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_REQ_DMA1_STREAM0_TC

+  *         @arg @ref LL_MDMA_REQ_DMA1_STREAM1_TC

+  *         @arg @ref LL_MDMA_REQ_DMA1_STREAM2_TC

+  *         @arg @ref LL_MDMA_REQ_DMA1_STREAM3_TC

+  *         @arg @ref LL_MDMA_REQ_DMA1_STREAM4_TC

+  *         @arg @ref LL_MDMA_REQ_DMA1_STREAM5_TC

+  *         @arg @ref LL_MDMA_REQ_DMA1_STREAM6_TC

+  *         @arg @ref LL_MDMA_REQ_DMA1_STREAM7_TC

+  *         @arg @ref LL_MDMA_REQ_DMA2_STREAM0_TC

+  *         @arg @ref LL_MDMA_REQ_DMA2_STREAM1_TC

+  *         @arg @ref LL_MDMA_REQ_DMA2_STREAM2_TC

+  *         @arg @ref LL_MDMA_REQ_DMA2_STREAM3_TC

+  *         @arg @ref LL_MDMA_REQ_DMA2_STREAM4_TC

+  *         @arg @ref LL_MDMA_REQ_DMA2_STREAM5_TC

+  *         @arg @ref LL_MDMA_REQ_DMA2_STREAM6_TC

+  *         @arg @ref LL_MDMA_REQ_DMA2_STREAM7_TC

+  *         @arg @ref LL_MDMA_REQ_LTDC_LINE_IT (*)

+  *         @arg @ref LL_MDMA_REQ_JPEG_INFIFO_TH (*)

+  *         @arg @ref LL_MDMA_REQ_JPEG_INFIFO_NF (*)

+  *         @arg @ref LL_MDMA_REQ_JPEG_OUTFIFO_TH (*)

+  *         @arg @ref LL_MDMA_REQ_JPEG_OUTFIFO_NE (*)

+  *         @arg @ref LL_MDMA_REQ_JPEG_END_CONVERSION (*)

+  *         @arg @ref LL_MDMA_REQ_QUADSPI_FIFO_TH (*)

+  *         @arg @ref LL_MDMA_REQ_QUADSPI_TC (*)

+  *         @arg @ref LL_MDMA_REQ_OCTOSPI1_FIFO_TH (*)

+  *         @arg @ref LL_MDMA_REQ_OCTOSPI1_TC (*)

+  *         @arg @ref LL_MDMA_REQ_DMA2D_CLUT_TC

+  *         @arg @ref LL_MDMA_REQ_DMA2D_TC

+  *         @arg @ref LL_MDMA_REQ_DMA2D_TW

+  *         @arg @ref LL_MDMA_REQ_DSI_TEARING_EFFECT (*)

+  *         @arg @ref LL_MDMA_REQ_DSI_END_REFRESH (*)

+  *         @arg @ref LL_MDMA_REQ_SDMMC1_END_DATA

+  *         @arg @ref LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER (*)

+  *         @arg @ref LL_MDMA_REQ_SDMMC1_COMMAND_END (*)

+  *         @arg @ref LL_MDMA_REQ_OCTOSPI2_FIFO_TH (*)

+  *         @arg @ref LL_MDMA_REQ_OCTOSPI2_TC (*)

+  * @note   (*) Availability depends on devices.

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_SetHWTrigger(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t HWRequest)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  MODIFY_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTBR, MDMA_CTBR_TSEL, HWRequest);

+}

+

+/**

+  * @brief Get Transfer hardware trigger (Request).

+  * @rmtoll CTBR          TSEL            LL_MDMA_GetHWTrigger

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_MDMA_REQ_DMA1_STREAM0_TC

+  *         @arg @ref LL_MDMA_REQ_DMA1_STREAM1_TC

+  *         @arg @ref LL_MDMA_REQ_DMA1_STREAM2_TC

+  *         @arg @ref LL_MDMA_REQ_DMA1_STREAM3_TC

+  *         @arg @ref LL_MDMA_REQ_DMA1_STREAM4_TC

+  *         @arg @ref LL_MDMA_REQ_DMA1_STREAM5_TC

+  *         @arg @ref LL_MDMA_REQ_DMA1_STREAM6_TC

+  *         @arg @ref LL_MDMA_REQ_DMA1_STREAM7_TC

+  *         @arg @ref LL_MDMA_REQ_DMA2_STREAM0_TC

+  *         @arg @ref LL_MDMA_REQ_DMA2_STREAM1_TC

+  *         @arg @ref LL_MDMA_REQ_DMA2_STREAM2_TC

+  *         @arg @ref LL_MDMA_REQ_DMA2_STREAM3_TC

+  *         @arg @ref LL_MDMA_REQ_DMA2_STREAM4_TC

+  *         @arg @ref LL_MDMA_REQ_DMA2_STREAM5_TC

+  *         @arg @ref LL_MDMA_REQ_DMA2_STREAM6_TC

+  *         @arg @ref LL_MDMA_REQ_DMA2_STREAM7_TC

+  *         @arg @ref LL_MDMA_REQ_LTDC_LINE_IT (*)

+  *         @arg @ref LL_MDMA_REQ_JPEG_INFIFO_TH (*)

+  *         @arg @ref LL_MDMA_REQ_JPEG_INFIFO_NF (*)

+  *         @arg @ref LL_MDMA_REQ_JPEG_OUTFIFO_TH (*)

+  *         @arg @ref LL_MDMA_REQ_JPEG_OUTFIFO_NE (*)

+  *         @arg @ref LL_MDMA_REQ_JPEG_END_CONVERSION (*)

+  *         @arg @ref LL_MDMA_REQ_QUADSPI_FIFO_TH (*)

+  *         @arg @ref LL_MDMA_REQ_QUADSPI_TC (*)

+  *         @arg @ref LL_MDMA_REQ_OCTOSPI1_FIFO_TH (*)

+  *         @arg @ref LL_MDMA_REQ_OCTOSPI1_TC (*)

+  *         @arg @ref LL_MDMA_REQ_DMA2D_CLUT_TC

+  *         @arg @ref LL_MDMA_REQ_DMA2D_TC

+  *         @arg @ref LL_MDMA_REQ_DMA2D_TW

+  *         @arg @ref LL_MDMA_REQ_DSI_TEARING_EFFECT (*)

+  *         @arg @ref LL_MDMA_REQ_DSI_END_REFRESH (*)

+  *         @arg @ref LL_MDMA_REQ_SDMMC1_END_DATA

+  *         @arg @ref LL_MDMA_REQ_SDMMC1_DMA_ENDBUFFER (*)

+  *         @arg @ref LL_MDMA_REQ_SDMMC1_COMMAND_END (*)

+  *         @arg @ref LL_MDMA_REQ_OCTOSPI2_FIFO_TH (*)

+  *         @arg @ref LL_MDMA_REQ_OCTOSPI2_TC (*)

+  * @note   (*) Availability depends on devices.

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetHWTrigger(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CTBR, MDMA_CTBR_TSEL));

+}

+

+/**

+  * @brief Set Mask Address.

+  * @rmtoll CMAR          MAR            LL_MDMA_SetMaskAddress

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  MaskAddress Between 0 to 0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_SetMaskAddress(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t MaskAddress)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CMAR, MaskAddress);

+}

+

+/**

+  * @brief Get Mask Address.

+  * @rmtoll CMAR          MAR            LL_MDMA_GetMaskAddress

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Between 0 to 0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetMaskAddress(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return (READ_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CMAR));

+}

+

+/**

+  * @brief Set Mask Data.

+  * @rmtoll CMDR          MDR            LL_MDMA_SetMaskData

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @param  MaskData Between 0 to 0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_SetMaskData(MDMA_TypeDef *MDMAx, uint32_t Channel, uint32_t MaskData)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  WRITE_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CMDR, MaskData);

+}

+

+/**

+  * @brief Get Mask Data.

+  * @rmtoll CMDR          MDR            LL_MDMA_GetMaskData

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Between 0 to 0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetMaskData(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return (READ_REG(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CMDR));

+}

+

+/**

+  * @brief Get Transfer Error Direction.

+  * @rmtoll CESR          TED            LL_MDMA_GetXferErrorDirection

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_MDMA_READ_ERROR

+  *         @arg @ref LL_MDMA_WRITE_ERROR

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetXferErrorDirection(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CESR, MDMA_CESR_TED));

+}

+

+/**

+  * @brief Get Transfer Error LSB Address.

+  * @rmtoll CESR          TEA            LL_MDMA_GetXferErrorLSBAddress

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval Between 0 to 0x0000007F

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_MDMA_GetXferErrorLSBAddress(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return (READ_BIT(((MDMA_Channel_TypeDef *)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CESR, MDMA_CESR_TEA));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_LL_EF_FLAG_Management FLAG_Management

+  * @{

+  */

+

+/**

+  * @brief Get MDMA Channel x Global Interrupt flag.

+  * @rmtoll GISR0  GIFx    LL_MDMA_IsActiveFlag_GI

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_GI(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  return ((READ_BIT(MDMAx->GISR0 ,(MDMA_GISR0_GIF0 << (Channel & 0x0000000FU)))==(MDMA_GISR0_GIF0 << (Channel & 0x0000000FU))) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get MDMA Channel x Transfer Error interrupt flag.

+  * @rmtoll CISR  TEIF    LL_MDMA_IsActiveFlag_TE

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TE(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CISR, MDMA_CISR_TEIF) == (MDMA_CISR_TEIF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get MDMA Channel x Channel Transfer Complete interrupt flag.

+  * @rmtoll CISR  CTCIF    LL_MDMA_IsActiveFlag_CTC

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CISR, MDMA_CISR_CTCIF) == (MDMA_CISR_CTCIF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get MDMA Channel x Block Repeat Transfer complete interrupt flag.

+  * @rmtoll CISR  BRTIF    LL_MDMA_IsActiveFlag_BRT

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CISR, MDMA_CISR_BRTIF) == (MDMA_CISR_BRTIF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get MDMA Channel x Block Transfer complete interrupt flag.

+  * @rmtoll CISR  BTIF    LL_MDMA_IsActiveFlag_BT

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BT(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CISR, MDMA_CISR_BTIF) == (MDMA_CISR_BTIF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get MDMA Channel x buffer transfer complete interrupt flag.

+  * @rmtoll CISR  TCIF    LL_MDMA_IsActiveFlag_TC

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TC(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CISR, MDMA_CISR_TCIF) == (MDMA_CISR_TCIF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get MDMA Channel x ReQuest Active flag.

+  * @rmtoll CISR  CRQA    LL_MDMA_IsActiveFlag_CRQA

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_CRQA(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CISR, MDMA_CISR_CRQA) == (MDMA_CISR_CRQA)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get MDMA Channel x Block Size Error flag.

+  * @rmtoll CESR  BSE    LL_MDMA_IsActiveFlag_BSE

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_BSE(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CESR, MDMA_CESR_BSE) == (MDMA_CESR_BSE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get MDMA Channel x Address/Size Error flag.

+  * @rmtoll CESR  ASE    LL_MDMA_IsActiveFlag_ASE

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_ASE(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CESR, MDMA_CESR_ASE) == (MDMA_CESR_ASE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get MDMA Channel x Transfer Error Mask Data flag.

+  * @rmtoll CESR  TEMD    LL_MDMA_IsActiveFlag_TEMD

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TEMD(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CESR, MDMA_CESR_TEMD) == (MDMA_CESR_TEMD)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Get MDMA Channel x Transfer Error Link Data flag.

+  * @rmtoll CESR  TELD    LL_MDMA_IsActiveFlag_TELD

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_MDMA_IsActiveFlag_TELD(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CESR, MDMA_CESR_TELD) == (MDMA_CESR_TELD)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Clear MDMA Channel x Transfer Error interrupt flag.

+  * @rmtoll CIFCR  CTEIF    LL_MDMA_ClearFlag_TE

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_ClearFlag_TE(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  WRITE_REG(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CIFCR ,MDMA_CIFCR_CTEIF);

+}

+

+/**

+  * @brief Clear MDMA Channel x Channel Transfer Complete interrupt flag.

+  * @rmtoll CIFCR  CCTCIF    LL_MDMA_ClearFlag_CTC

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_ClearFlag_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  WRITE_REG(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CIFCR ,MDMA_CIFCR_CCTCIF);

+}

+

+/**

+  * @brief Clear MDMA Channel x Block Repeat Transfer complete interrupt flag.

+  * @rmtoll CIFCR  CBRTIF    LL_MDMA_ClearFlag_BRT

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_ClearFlag_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  WRITE_REG(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CIFCR ,MDMA_CIFCR_CBRTIF);

+}

+

+/**

+  * @brief Clear MDMA Channel x Block Transfer complete interrupt flag.

+  * @rmtoll CIFCR  CBTIF    LL_MDMA_ClearFlag_BT

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_ClearFlag_BT(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  WRITE_REG(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CIFCR ,MDMA_CIFCR_CBTIF);

+}

+

+/**

+  * @brief Clear MDMA Channel x buffer transfer Complete Interrupt Flag.

+  * @rmtoll CIFCR  CLTCIF    LL_MDMA_ClearFlag_TC

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_ClearFlag_TC(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  WRITE_REG(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CIFCR ,MDMA_CIFCR_CLTCIF);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup MDMA_LL_EF_IT_Management IT_Management

+  * @{

+  */

+

+/**

+  * @brief Enable MDMA Channel x Transfer Error interrupt.

+  * @rmtoll CCR  TEIE    LL_MDMA_EnableIT_TE

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_EnableIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  SET_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_TEIE);

+}

+

+/**

+  * @brief Enable MDMA Channel x Channel Transfer Complete interrupt.

+  * @rmtoll CCR  CTCIE    LL_MDMA_EnableIT_CTC

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_EnableIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  SET_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_CTCIE);

+}

+

+/**

+  * @brief Enable MDMA Channel x Block Repeat Transfer interrupt.

+  * @rmtoll CCR  BRTIE    LL_MDMA_EnableIT_BRT

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_EnableIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  SET_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_BRTIE);

+}

+

+/**

+  * @brief Enable MDMA Channel x Block Transfer interrupt.

+  * @rmtoll CCR  BTIE    LL_MDMA_EnableIT_BT

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_EnableIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  SET_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_BTIE);

+}

+

+/**

+  * @brief Enable MDMA Channel x buffer transfer complete interrupt.

+  * @rmtoll CCR  TCIE    LL_MDMA_EnableIT_TC

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_EnableIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  SET_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_TCIE);

+}

+

+/**

+  * @brief Disable MDMA Channel x Transfer Error interrupt.

+  * @rmtoll CCR  TEIE    LL_MDMA_DisableIT_TE

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_DisableIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  CLEAR_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_TEIE);

+}

+

+/**

+  * @brief Disable MDMA Channel x Channel Transfer Complete interrupt.

+  * @rmtoll CCR  CTCIE    LL_MDMA_DisableIT_CTC

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_DisableIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  CLEAR_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_CTCIE);

+}

+

+/**

+  * @brief Disable MDMA Channel x Block Repeat Transfer interrupt.

+  * @rmtoll CCR  BRTIE    LL_MDMA_DisableIT_BRT

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_DisableIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  CLEAR_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_BRTIE);

+}

+

+/**

+  * @brief Disable MDMA Channel x Block Transfer interrupt.

+  * @rmtoll CCR  BTIE    LL_MDMA_DisableIT_BT

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_DisableIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  CLEAR_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_BTIE);

+}

+

+/**

+  * @brief Disable MDMA Channel x buffer transfer complete interrupt.

+  * @rmtoll CCR  TCIE    LL_MDMA_DisableIT_TC

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_MDMA_DisableIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  CLEAR_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_TCIE);

+}

+

+/**

+  * @brief Check if MDMA Channel x Transfer Error interrupt is enabled.

+  * @rmtoll CCR  TEIE    LL_MDMA_IsEnabledIT_TE

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_TE(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_TEIE) == MDMA_CCR_TEIE) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Check if MDMA Channel x Channel Transfer Complete interrupt is enabled.

+  * @rmtoll CCR  CTCIE    LL_MDMA_IsEnabledIT_CTC

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_CTC(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_CTCIE) == MDMA_CCR_CTCIE) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Check if MDMA Channel x Block Repeat Transfer complete interrupt is enabled.

+  * @rmtoll CCR  BRTIE    LL_MDMA_IsEnabledIT_BRT

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BRT(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_BRTIE) == MDMA_CCR_BRTIE) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Check if MDMA Channel x Block Transfer interrupt is enabled.

+  * @rmtoll CCR  BTIE    LL_MDMA_IsEnabledIT_BT

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_BT(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_BTIE) == MDMA_CCR_BTIE) ? 1UL : 0UL);

+}

+

+/**

+  * @brief Check if MDMA Channel x buffer transfer complete interrupt is enabled.

+  * @rmtoll CCR  TCIE    LL_MDMA_IsEnabledIT_TC

+  * @param  MDMAx MDMAx Instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_MDMA_CHANNEL_0

+  *         @arg @ref LL_MDMA_CHANNEL_1

+  *         @arg @ref LL_MDMA_CHANNEL_2

+  *         @arg @ref LL_MDMA_CHANNEL_3

+  *         @arg @ref LL_MDMA_CHANNEL_4

+  *         @arg @ref LL_MDMA_CHANNEL_5

+  *         @arg @ref LL_MDMA_CHANNEL_6

+  *         @arg @ref LL_MDMA_CHANNEL_7

+  *         @arg @ref LL_MDMA_CHANNEL_8

+  *         @arg @ref LL_MDMA_CHANNEL_9

+  *         @arg @ref LL_MDMA_CHANNEL_10

+  *         @arg @ref LL_MDMA_CHANNEL_11

+  *         @arg @ref LL_MDMA_CHANNEL_12

+  *         @arg @ref LL_MDMA_CHANNEL_13

+  *         @arg @ref LL_MDMA_CHANNEL_14

+  *         @arg @ref LL_MDMA_CHANNEL_15

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_MDMA_IsEnabledIT_TC(MDMA_TypeDef *MDMAx, uint32_t Channel)

+{

+  register uint32_t mdma_base_addr = (uint32_t)MDMAx;

+

+  return ((READ_BIT(((MDMA_Channel_TypeDef*)(mdma_base_addr + LL_MDMA_CH_OFFSET_TAB[Channel]))->CCR ,MDMA_CCR_TCIE) == MDMA_CCR_TCIE) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup MDMA_LL_EF_Init Initialization and de-initialization functions

+  * @{

+  */

+

+uint32_t LL_MDMA_Init(MDMA_TypeDef *MDMAx, uint32_t Channel, LL_MDMA_InitTypeDef *MDMA_InitStruct);

+uint32_t LL_MDMA_DeInit(MDMA_TypeDef *MDMAx, uint32_t Channel);

+void LL_MDMA_StructInit(LL_MDMA_InitTypeDef *MDMA_InitStruct);

+void LL_MDMA_CreateLinkNode(LL_MDMA_InitTypeDef *MDMA_InitStruct, LL_MDMA_LinkNodeTypeDef *pNode);

+void LL_MDMA_ConnectLinkNode(LL_MDMA_LinkNodeTypeDef *pPrevLinkNode, LL_MDMA_LinkNodeTypeDef *pNewLinkNode);

+void LL_MDMA_DisconnectNextLinkNode(LL_MDMA_LinkNodeTypeDef *pLinkNode);

+

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* MDMA */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_LL_MDMA_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_opamp.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_opamp.h
new file mode 100644
index 0000000000..2d6200bab8
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_opamp.h
@@ -0,0 +1,825 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_opamp.h

+  * @author  MCD Application Team

+  * @brief   Header file of OPAMP LL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef __STM32H7xx_LL_OPAMP_H

+#define __STM32H7xx_LL_OPAMP_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+#if defined (OPAMP1) || defined (OPAMP2)

+

+/** @defgroup OPAMP_LL OPAMP

+  * @{

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup OPAMP_LL_Private_Constants OPAMP Private Constants

+  * @{

+  */

+

+/* Internal mask for OPAMP power mode:                                        */

+/* To select into literal LL_OPAMP_POWERMODE_x the relevant bits for:         */

+/* - OPAMP power mode into control register                                   */

+/* - OPAMP trimming register offset                                           */

+

+/* Internal register offset for OPAMP trimming configuration */

+#define OPAMP_POWERMODE_OTR_REGOFFSET       0x00000000U

+#define OPAMP_POWERMODE_HSOTR_REGOFFSET     0x00000001U

+#define OPAMP_POWERMODE_OTR_REGOFFSET_MASK  (OPAMP_POWERMODE_OTR_REGOFFSET | OPAMP_POWERMODE_HSOTR_REGOFFSET)

+

+/* Mask for OPAMP power mode into control register */

+#define OPAMP_POWERMODE_CSR_BIT_MASK        (OPAMP_CSR_OPAHSM)

+

+/* Internal mask for OPAMP trimming of transistors differential pair NMOS     */

+/* or PMOS.                                                                   */

+/* To select into literal LL_OPAMP_TRIMMING_x the relevant bits for:          */

+/* - OPAMP trimming selection of transistors differential pair                */

+/* - OPAMP trimming values of transistors differential pair                   */

+#define OPAMP_TRIMMING_SELECT_MASK          0x00030000U

+#define OPAMP_TRIMMING_VALUE_MASK           (OPAMP_OTR_TRIMOFFSETP | OPAMP_OTR_TRIMOFFSETN)

+

+/**

+  * @}

+  */

+

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup OPAMP_LL_Private_Macros OPAMP Private Macros

+  * @{

+  */

+

+/**

+  * @brief  Driver macro reserved for internal use: set a pointer to

+  *         a register from a register basis from which an offset

+  *         is applied.

+  * @param  __REG__ Register basis from which the offset is applied.

+  * @param  __REG_OFFSET__ Offset to be applied (unit: number of registers).

+  * @retval Register address

+*/

+#define __OPAMP_PTR_REG_OFFSET(__REG__, __REG_OFFSET__)                        \

+ ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFSET__) << 2U))))

+

+

+

+/**

+  * @}

+  */

+

+

+/* Exported types ------------------------------------------------------------*/

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup OPAMP_LL_ES_INIT OPAMP Exported Init structure

+  * @{

+  */

+

+/**

+  * @brief  Structure definition of some features of OPAMP instance.

+  */

+typedef struct

+{

+  uint32_t PowerMode;                   /*!< Set OPAMP power mode.

+                                             This parameter can be a value of @ref OPAMP_LL_EC_POWER_MODE

+

+                                             This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetPowerMode(). */

+

+

+  uint32_t FunctionalMode;              /*!< Set OPAMP functional mode by setting internal connections: OPAMP operation in standalone, follower, ...

+                                             This parameter can be a value of @ref OPAMP_LL_EC_FUNCTIONAL_MODE

+                                             @note If OPAMP is configured in mode PGA, the gain can be configured using function @ref LL_OPAMP_SetPGAGain().

+

+                                             This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetFunctionalMode(). */

+

+  uint32_t InputNonInverting;           /*!< Set OPAMP input non-inverting connection.

+                                             This parameter can be a value of @ref OPAMP_LL_EC_INPUT_NONINVERTING

+

+                                             This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetInputNonInverting(). */

+

+  uint32_t InputInverting;              /*!< Set OPAMP inverting input connection.

+                                             This parameter can be a value of @ref OPAMP_LL_EC_INPUT_INVERTING

+                                             @note OPAMP inverting input is used with OPAMP in mode standalone or PGA with external capacitors for filtering circuit. Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin), this parameter is discarded.

+

+                                             This feature can be modified afterwards using unitary function @ref LL_OPAMP_SetInputInverting(). */

+

+} LL_OPAMP_InitTypeDef;

+

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup OPAMP_LL_Exported_Constants OPAMP Exported Constants

+  * @{

+  */

+

+/** @defgroup OPAMP_LL_EC_MODE OPAMP mode calibration or functional.

+  * @{

+  */

+#define LL_OPAMP_MODE_FUNCTIONAL        0x00000000U                               /*!< OPAMP functional mode */

+#define LL_OPAMP_MODE_CALIBRATION       (OPAMP_CSR_CALON)                           /*!< OPAMP calibration mode */

+/**

+  * @}

+  */

+

+/** @defgroup OPAMP_LL_EC_FUNCTIONAL_MODE OPAMP functional mode

+  * @{

+  */

+#define LL_OPAMP_MODE_STANDALONE        0x00000000U                                                 /*!< OPAMP functional mode, OPAMP operation in standalone */

+#define LL_OPAMP_MODE_FOLLOWER          (OPAMP_CSR_VMSEL_1 | OPAMP_CSR_VMSEL_0)                       /*!< OPAMP functional mode, OPAMP operation in follower */

+#define LL_OPAMP_MODE_PGA               (OPAMP_CSR_VMSEL_1)                                           /*!< OPAMP functional mode, OPAMP operation in PGA */

+#define LL_OPAMP_MODE_PGA_IO0           (OPAMP_CSR_PGGAIN_2|OPAMP_CSR_VMSEL_1)                        /*!< In PGA mode, the inverting input is connected to VINM0 for filtering */

+#define LL_OPAMP_MODE_PGA_IO0_BIAS      (OPAMP_CSR_PGGAIN_3|OPAMP_CSR_VMSEL_1)                        /*!< In PGA mode, the inverting input is connected to VINM0

+                                                                                                          - Input signal on VINM0, bias on VINPx: negative gain

+                                                                                                          - Bias on VINM0, input signal on VINPx: positive gain */

+#define LL_OPAMP_MODE_PGA_IO0_IO1_BIAS  (OPAMP_CSR_PGGAIN_3|OPAMP_CSR_PGGAIN_2|OPAMP_CSR_VMSEL_1)    /*!< In PGA mode, the inverting input is connected to VINM0

+                                                                                                          - Input signal on VINM0, bias on VINPx: negative gain

+                                                                                                          - Bias on VINM0, input signal on VINPx: positive gain

+                                                                                                          And VINM1 is connected too for filtering */

+

+/**

+  * @}

+  */

+

+/** @defgroup OPAMP_LL_EC_MODE_PGA_GAIN OPAMP PGA gain (relevant when OPAMP is in functional mode PGA)

+  * @note Gain sign:

+  *         - is positive if the @ref OPAMP_LL_EC_FUNCTIONAL_MODE configuration is

+  *           @ref LL_OPAMP_MODE_PGA or LL_OPAMP_MODE_PGA_IO0

+  *         - may be positive or negative if the @ref OPAMP_LL_EC_FUNCTIONAL_MODE configuration is

+  *           @ref LL_OPAMP_MODE_PGA_IO0_BIAS or LL_OPAMP_MODE_PGA_IO0_IO1_BIAS

+  *       see @ref OPAMP_LL_EC_FUNCTIONAL_MODE for more details

+  * @{

+  */

+#define LL_OPAMP_PGA_GAIN_2_OR_MINUS_1             0x00000000U                                                    /*!< OPAMP PGA gain 2  or -1  */

+#define LL_OPAMP_PGA_GAIN_4_OR_MINUS_3             (                                          OPAMP_CSR_PGGAIN_0) /*!< OPAMP PGA gain 4  or -3  */

+#define LL_OPAMP_PGA_GAIN_8_OR_MINUS_7             (                     OPAMP_CSR_PGGAIN_1                     ) /*!< OPAMP PGA gain 8  or -7  */

+#define LL_OPAMP_PGA_GAIN_16_OR_MINUS_15           (                     OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0) /*!< OPAMP PGA gain 16 or -15 */

+/**

+  * @}

+  */

+

+/** @defgroup OPAMP_LL_EC_INPUT_NONINVERTING OPAMP input non-inverting

+  * @{

+  */

+#define LL_OPAMP_INPUT_NONINVERT_IO0         0x00000000U           /*!< OPAMP non inverting input connected to I/O VINP0

+                                                                        (PB0  for OPAMP1, PE9  for OPAMP2)

+                                                                        Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */

+#define LL_OPAMP_INPUT_NONINVERT_DAC         OPAMP_CSR_VPSEL_0     /*!< OPAMP non inverting input connected internally to DAC channel

+                                                                        (DAC1_CH1 for OPAMP1, DAC1_CH2  for OPAMP2)

+                                                                        Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */

+#if defined(DAC2)

+#define LL_OPAMP_INPUT_NONINVERT_DAC2        OPAMP_CSR_VPSEL_1     /*!< OPAMP non inverting input connected internally to DAC2 channel

+                                                                        (DAC3 only for OPAMP2)*/

+#endif /* DAC2 */

+

+/**

+  * @}

+  */

+

+/** @defgroup OPAMP_LL_EC_INPUT_INVERTING OPAMP input inverting

+  * @note OPAMP inverting input is used with OPAMP in mode standalone or PGA with negative gain or bias.

+  *       Otherwise (OPAMP in mode follower), OPAMP inverting input is not used (not connected to GPIO pin).

+  * @{

+  */

+#define LL_OPAMP_INPUT_INVERT_IO0         0x00000000U              /*!< OPAMP inverting input connected to I/O VINM0

+                                                                        (PC5  for OPAMP1, PE8  for OPAMP2)

+                                                                        Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */

+#define LL_OPAMP_INPUT_INVERT_IO1         OPAMP_CSR_VMSEL_0        /*!< OPAMP inverting input connected to I/0 VINM1

+                                                                        (PA7  for OPAMP1, PG1  for OPAMP2)

+                                                                        Note: On this STM32 serie, all OPAMPx are not available on all devices. Refer to device datasheet for more details */

+#define LL_OPAMP_INPUT_INVERT_CONNECT_NO  OPAMP_CSR_VMSEL_1        /*!< OPAMP inverting input not externally connected (intended for OPAMP in mode follower or PGA with positive gain without bias).

+                                                                        Note: On this STM32 serie, this literal include cases of value 0x11 for mode follower and value 0x10 for mode PGA. */

+/**

+  * @}

+  */

+

+

+

+/** @defgroup OPAMP_LL_EC_POWER_MODE OPAMP PowerMode

+  * @{

+  */

+#define LL_OPAMP_POWERMODE_NORMAL        (OPAMP_POWERMODE_OTR_REGOFFSET)                            /*!< OPAMP output in normal mode */

+#define LL_OPAMP_POWERMODE_HIGHSPEED     (OPAMP_POWERMODE_HSOTR_REGOFFSET | OPAMP_CSR_OPAHSM)       /*!< OPAMP output in highspeed mode */

+/**

+  * @}

+  */

+

+/** @defgroup OPAMP_LL_EC_TRIMMING_MODE OPAMP trimming mode

+  * @{

+  */

+#define LL_OPAMP_TRIMMING_FACTORY       0x00000000U             /*!< OPAMP trimming factors set to factory values */

+#define LL_OPAMP_TRIMMING_USER          OPAMP_CSR_USERTRIM      /*!< OPAMP trimming factors set to user values */

+/**

+  * @}

+  */

+

+/** @defgroup OPAMP_LL_EC_TRIMMING_TRANSISTORS_DIFF_PAIR OPAMP trimming of transistors differential pair NMOS or PMOS

+  * @{

+  */

+#define LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA  (OPAMP_OTR_TRIMOFFSETN | ((OPAMP_CSR_CALSEL_1 | OPAMP_CSR_CALSEL_0) << 4)) /*!< OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.9*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */

+#define LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA  (OPAMP_OTR_TRIMOFFSETN                      | (OPAMP_CSR_CALSEL_1 << 4))   /*!< OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.5*Vdda). */

+#define LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA  (OPAMP_OTR_TRIMOFFSETP                      | (OPAMP_CSR_CALSEL_0 << 4))   /*!< OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.1*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */

+#define LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA (OPAMP_OTR_TRIMOFFSETP                                          )          /*!< OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.33*Vdda). */

+#define LL_OPAMP_TRIMMING_NMOS                 (LL_OPAMP_TRIMMING_NMOS_VREF_90PC_VDDA)                                    /*!< OPAMP trimming of transistors differential pair NMOS (internal reference voltage set to 0.9*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */

+#define LL_OPAMP_TRIMMING_PMOS                 (LL_OPAMP_TRIMMING_PMOS_VREF_10PC_VDDA)                                    /*!< OPAMP trimming of transistors differential pair PMOS (internal reference voltage set to 0.1*Vdda). Default parameters to be used for calibration using two trimming steps (one with each transistors differential pair NMOS and PMOS). */

+/**

+  * @}

+  */

+

+/** @defgroup OPAMP_LL_EC_HW_DELAYS  Definitions of OPAMP hardware constraints delays

+  * @note   Only OPAMP IP HW delays are defined in OPAMP LL driver driver,

+  *         not timeout values.

+  *         For details on delays values, refer to descriptions in source code

+  *         above each literal definition.

+  * @{

+  */

+

+/* Delay for OPAMP startup time (transition from state disable to enable).    */

+/* Note: OPAMP startup time depends on board application environment:         */

+/*       impedance connected to OPAMP output.                                 */

+/*       The delay below is specified under conditions:                       */

+/*        - OPAMP in functional mode follower                                 */

+/*        - load impedance of 4kOhm (min), 50pF (max)                         */

+/* Literal set to maximum value (refer to device datasheet,                   */

+/* parameter "tWAKEUP").                                                      */

+/* Unit: us                                                                   */

+#define LL_OPAMP_DELAY_STARTUP_US         (3U)  /*!< Delay for OPAMP startup time */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup OPAMP_LL_Exported_Macros OPAMP Exported Macros

+  * @{

+  */

+/** @defgroup OPAMP_LL_EM_WRITE_READ Common write and read registers macro

+  * @{

+  */

+/**

+  * @brief  Write a value in OPAMP LL_OPAMP_GetPowerModeregister

+  * @param  __INSTANCE__ OPAMP Instance

+  * @param  __REG__ Register to be written

+  * @param  __VALUE__ Value to be written in the register

+  * @retval None

+  */

+#define LL_OPAMP_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))

+

+/**

+  * @brief  Read a value in OPAMP register

+  * @param  __INSTANCE__ OPAMP Instance

+  * @param  __REG__ Register to be read

+  * @retval Register value

+  */

+#define LL_OPAMP_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)

+/**

+  * @}

+  */

+/** @defgroup OPAMP_LL_EM_HELPER_MACRO OPAMP helper macro

+  * @{

+  */

+

+/**

+  * @brief  Helper macro to select the OPAMP common instance

+  *         to which is belonging the selected OPAMP instance.

+  * @note   OPAMP common register instance can be used to

+  *         set parameters common to several OPAMP instances.

+  *         Refer to functions having argument "OPAMPxy_COMMON" as parameter.

+  * @param  __OPAMPx__ OPAMP instance

+  * @retval OPAMP common instance

+  */

+#if defined(OPAMP1) && defined(OPAMP2)

+#define __LL_OPAMP_COMMON_INSTANCE(__OPAMPx__)                                 \

+  (OPAMP12_COMMON)

+#endif

+

+/**

+  * @brief  Helper macro to check if all OPAMP instances sharing the same

+  *         OPAMP common instance are disabled.

+  * @note   This check is required by functions with setting conditioned to

+  *         OPAMP state:

+  *         All OPAMP instances of the OPAMP common group must be disabled.

+  *         Refer to functions having argument "OPAMPxy_COMMON" as parameter.

+  * @retval 0: All OPAMP instances sharing the same OPAMP common instance

+  *            are disabled.

+  *         1: At least one OPAMP instance sharing the same OPAMP common instance

+  *            is enabled

+  */

+#if defined(OPAMP1) && defined(OPAMP2)

+#define __LL_OPAMP_IS_ENABLED_ALL_COMMON_INSTANCE()                            \

+  (LL_OPAMP_IsEnabled(OPAMP1) |                                                \

+   LL_OPAMP_IsEnabled(OPAMP2)  )

+#endif

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup OPAMP_LL_Exported_Functions OPAMP Exported Functions

+  * @{

+  */

+

+/** @defgroup OPAMP_LL_EF_CONFIGURATION_OPAMP_INSTANCE Configuration of OPAMP hierarchical scope: OPAMP instance

+  * @{

+  */

+

+/**

+  * @brief  Set OPAMP mode calibration or functional.

+  * @note   OPAMP mode corresponds to functional or calibration mode:

+  *          - functional mode: OPAMP operation in standalone, follower, ...

+  *            Set functional mode using function

+  *            @ref LL_OPAMP_SetFunctionalMode().

+  *          - calibration mode: offset calibration of the selected

+  *            transistors differential pair NMOS or PMOS.

+  * @rmtoll CSR      CALON          LL_OPAMP_SetMode

+  * @param  OPAMPx OPAMP instance

+  * @param  Mode This parameter can be one of the following values:

+  *         @arg @ref LL_OPAMP_MODE_FUNCTIONAL

+  *         @arg @ref LL_OPAMP_MODE_CALIBRATION

+  * @retval None

+  */

+__STATIC_INLINE void LL_OPAMP_SetMode(OPAMP_TypeDef *OPAMPx, uint32_t Mode)

+{

+  MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_CALON, Mode);

+}

+

+/**

+  * @brief  Get OPAMP mode calibration or functional.

+  * @note   OPAMP mode corresponds to functional or calibration mode:

+  *          - functional mode: OPAMP operation in standalone, follower, ...

+  *            Set functional mode using function

+  *            @ref LL_OPAMP_SetFunctionalMode().

+  *          - calibration mode: offset calibration of the selected

+  *            transistors differential pair NMOS or PMOS.

+  * @rmtoll CSR      CALON          LL_OPAMP_GetMode

+  * @param  OPAMPx OPAMP instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_OPAMP_MODE_FUNCTIONAL

+  *         @arg @ref LL_OPAMP_MODE_CALIBRATION

+  */

+__STATIC_INLINE uint32_t LL_OPAMP_GetMode(OPAMP_TypeDef *OPAMPx)

+{

+  return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALON));

+}

+

+/**

+  * @brief  Set OPAMP functional mode by setting internal connections.

+  *         OPAMP operation in standalone, follower, ...

+  * @note   This function reset bit of calibration mode to ensure

+  *         to be in functional mode, in order to have OPAMP parameters

+  *         (inputs selection, ...) set with the corresponding OPAMP mode

+  *         to be effective.

+  * @rmtoll CSR      VMSEL          LL_OPAMP_SetFunctionalMode

+  * @param  OPAMPx OPAMP instance

+  * @param  FunctionalMode This parameter can be one of the following values:

+  *         @arg @ref LL_OPAMP_MODE_STANDALONE

+  *         @arg @ref LL_OPAMP_MODE_FOLLOWER

+  *         @arg @ref LL_OPAMP_MODE_PGA

+  *         @arg @ref LL_OPAMP_MODE_PGA_IO0

+  *         @arg @ref LL_OPAMP_MODE_PGA_IO0_BIAS

+  *         @arg @ref LL_OPAMP_MODE_PGA_IO0_IO1_BIAS

+  * @retval None

+  */

+__STATIC_INLINE void LL_OPAMP_SetFunctionalMode(OPAMP_TypeDef *OPAMPx, uint32_t FunctionalMode)

+{

+  /* Note: Bit OPAMP_CSR_CALON reset to ensure to be in functional mode */

+  MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_PGGAIN_3 | OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_VMSEL | OPAMP_CSR_CALON, FunctionalMode);

+}

+

+/**

+  * @brief  Get OPAMP functional mode from setting of internal connections.

+  *         OPAMP operation in standalone, follower, ...

+  * @rmtoll CSR      VMSEL          LL_OPAMP_GetFunctionalMode

+  * @param  OPAMPx OPAMP instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_OPAMP_MODE_STANDALONE

+  *         @arg @ref LL_OPAMP_MODE_FOLLOWER

+  *         @arg @ref LL_OPAMP_MODE_PGA

+  *         @arg @ref LL_OPAMP_MODE_PGA_IO0

+  *         @arg @ref LL_OPAMP_MODE_PGA_IO0_BIAS

+  *         @arg @ref LL_OPAMP_MODE_PGA_IO0_IO1_BIAS

+  */

+__STATIC_INLINE uint32_t LL_OPAMP_GetFunctionalMode(OPAMP_TypeDef *OPAMPx)

+{

+  return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGGAIN_3 | OPAMP_CSR_PGGAIN_2 | OPAMP_CSR_VMSEL));

+}

+

+/**

+  * @brief  Set OPAMP PGA gain.

+  * @note   Preliminarily, OPAMP must be set in mode PGA

+  *         using function @ref LL_OPAMP_SetFunctionalMode().

+  * @rmtoll CSR      PGGAIN         LL_OPAMP_SetPGAGain

+  * @param  OPAMPx OPAMP instance

+  * @param  PGAGain This parameter can be one of the following values:

+  *         @arg @ref LL_OPAMP_PGA_GAIN_2_OR_MINUS_1

+  *         @arg @ref LL_OPAMP_PGA_GAIN_4_OR_MINUS_3

+  *         @arg @ref LL_OPAMP_PGA_GAIN_8_OR_MINUS_7

+  *         @arg @ref LL_OPAMP_PGA_GAIN_16_OR_MINUS_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_OPAMP_SetPGAGain(OPAMP_TypeDef *OPAMPx, uint32_t PGAGain)

+{

+  MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0, PGAGain);

+}

+

+/**

+  * @brief  Get OPAMP PGA gain.

+  * @note   Preliminarily, OPAMP must be set in mode PGA

+  *         using function @ref LL_OPAMP_SetFunctionalMode().

+  * @rmtoll CSR      PGGAIN         LL_OPAMP_GetPGAGain

+  * @param  OPAMPx OPAMP instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_OPAMP_PGA_GAIN_2_OR_MINUS_1

+  *         @arg @ref LL_OPAMP_PGA_GAIN_4_OR_MINUS_3

+  *         @arg @ref LL_OPAMP_PGA_GAIN_8_OR_MINUS_7

+  *         @arg @ref LL_OPAMP_PGA_GAIN_16_OR_MINUS_15

+  */

+__STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain(OPAMP_TypeDef *OPAMPx)

+{

+  return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGGAIN_1 | OPAMP_CSR_PGGAIN_0));

+}

+

+/**

+  * @brief  Set OPAMP power mode normal or highspeed.

+  * @note   OPAMP highspeed mode allows output stage to have a better slew rate.

+  * @rmtoll CSR      OPAHSM     LL_OPAMP_SetPowerMode

+  * @param  OPAMPx OPAMP instance

+  * @param  PowerMode This parameter can be one of the following values:

+  *         @arg @ref LL_OPAMP_POWERMODE_NORMAL

+  *         @arg @ref LL_OPAMP_POWERMODE_HIGHSPEED

+  * @retval None

+  */

+__STATIC_INLINE void LL_OPAMP_SetPowerMode(OPAMP_TypeDef *OPAMPx, uint32_t PowerMode)

+{

+  MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_OPAHSM, (PowerMode & OPAMP_POWERMODE_CSR_BIT_MASK));

+}

+

+/**

+  * @brief  Get OPAMP power mode normal or highspeed.

+  * @note   OPAMP highspeed mode allows output stage to have a better slew rate.

+  * @rmtoll CSR      OPAHSM     LL_OPAMP_GetPowerMode

+  * @param  OPAMPx OPAMP instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_OPAMP_POWERMODE_NORMAL

+  *         @arg @ref LL_OPAMP_POWERMODE_HIGHSPEED

+  */

+__STATIC_INLINE uint32_t LL_OPAMP_GetPowerMode(OPAMP_TypeDef *OPAMPx)

+{

+  register uint32_t power_mode = (READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAHSM));

+

+  return (uint32_t)(power_mode | (power_mode >> (OPAMP_CSR_OPAHSM_Pos)));

+}

+/**

+  * @}

+  */

+

+/** @defgroup OPAMP_LL_EF_CONFIGURATION_INPUTS Configuration of OPAMP inputs

+  * @{

+  */

+

+/**

+  * @brief  Set OPAMP non-inverting input connection.

+  * @rmtoll CSR      VPSEL          LL_OPAMP_SetInputNonInverting

+  * @param  OPAMPx OPAMP instance

+  * @param  InputNonInverting This parameter can be one of the following values:

+  *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0

+  *         @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC

+  *         @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC2 (Only for OPAMP2)

+  * @retval None

+  */

+__STATIC_INLINE void LL_OPAMP_SetInputNonInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputNonInverting)

+{

+  MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_VPSEL, InputNonInverting);

+}

+

+/**

+  * @brief  Get OPAMP non-inverting input connection.

+  * @rmtoll CSR      VPSEL          LL_OPAMP_GetInputNonInverting

+  * @param  OPAMPx OPAMP instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0

+  *         @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC

+  *         @arg @ref LL_OPAMP_INPUT_NONINVERT_DAC2 (Only for OPAMP2)

+  */

+__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting(OPAMP_TypeDef *OPAMPx)

+{

+  return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VPSEL));

+}

+

+/**

+  * @brief  Set OPAMP inverting input connection.

+  * @note   OPAMP inverting input is used with OPAMP in mode standalone

+  *         or PGA with external capacitors for filtering circuit.

+  *         Otherwise (OPAMP in mode follower), OPAMP inverting input

+  *         is not used (not connected to GPIO pin).

+  * @rmtoll CSR      VMSEL          LL_OPAMP_SetInputInverting

+  * @param  OPAMPx OPAMP instance

+  * @param  InputInverting This parameter can be one of the following values:

+  *         @arg @ref LL_OPAMP_INPUT_INVERT_IO0

+  *         @arg @ref LL_OPAMP_INPUT_INVERT_IO1

+  *         @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO

+  * @retval None

+  */

+__STATIC_INLINE void LL_OPAMP_SetInputInverting(OPAMP_TypeDef *OPAMPx, uint32_t InputInverting)

+{

+  /* Manage cases of OPAMP inverting input not connected (0x10 and 0x11)      */

+  /* to not modify OPAMP mode follower or PGA.                                */

+  /* Bit OPAMP_CSR_VMSEL_1 is set by OPAMP mode (follower, PGA). */

+  MODIFY_REG(OPAMPx->CSR, (~(InputInverting >> 1)) & OPAMP_CSR_VMSEL_0, InputInverting);

+}

+

+/**

+  * @brief  Get OPAMP inverting input connection.

+  * @rmtoll CSR      VMSEL          LL_OPAMP_GetInputInverting

+  * @param  OPAMPx OPAMP instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_OPAMP_INPUT_INVERT_IO0

+  *         @arg @ref LL_OPAMP_INPUT_INVERT_IO1

+  *         @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO

+  */

+__STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting(OPAMP_TypeDef *OPAMPx)

+{

+  register uint32_t input_inverting = READ_BIT(OPAMPx->CSR, OPAMP_CSR_VMSEL);

+

+  /* Manage cases 0x10 and 0x11 to return the same value: OPAMP inverting     */

+  /* input not connected.                                                     */

+  return (input_inverting & ~((input_inverting >> 1) & OPAMP_CSR_VMSEL_0));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup OPAMP_LL_EF_OPAMP_TRIMMING Configuration and operation of OPAMP trimming

+  * @{

+  */

+

+/**

+  * @brief  Set OPAMP trimming mode.

+  * @rmtoll CSR      USERTRIM       LL_OPAMP_SetTrimmingMode

+  * @param  OPAMPx OPAMP instance

+  * @param  TrimmingMode This parameter can be one of the following values:

+  *         @arg @ref LL_OPAMP_TRIMMING_FACTORY

+  *         @arg @ref LL_OPAMP_TRIMMING_USER

+  * @retval None

+  */

+__STATIC_INLINE void LL_OPAMP_SetTrimmingMode(OPAMP_TypeDef *OPAMPx, uint32_t TrimmingMode)

+{

+  MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_USERTRIM, TrimmingMode);

+}

+

+/**

+  * @brief  Get OPAMP trimming mode.

+  * @rmtoll CSR      USERTRIM       LL_OPAMP_GetTrimmingMode

+  * @param  OPAMPx OPAMP instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_OPAMP_TRIMMING_FACTORY

+  *         @arg @ref LL_OPAMP_TRIMMING_USER

+  */

+__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingMode(OPAMP_TypeDef *OPAMPx)

+{

+  return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_USERTRIM));

+}

+

+/**

+  * @brief  Set OPAMP offset to calibrate the selected transistors

+  *         differential pair NMOS or PMOS.

+  * @note   Preliminarily, OPAMP must be set in mode calibration

+  *         using function @ref LL_OPAMP_SetMode().

+  * @rmtoll CSR      CALSEL         LL_OPAMP_SetCalibrationSelection

+  * @param  OPAMPx OPAMP instance

+  * @param  TransistorsDiffPair This parameter can be one of the following values:

+  *         @arg @ref LL_OPAMP_TRIMMING_NMOS            (1)

+  *         @arg @ref LL_OPAMP_TRIMMING_PMOS            (1)

+  *         @arg @ref LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA

+  *         @arg @ref LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA

+  *

+  *         (1) Default parameters to be used for calibration

+  *             using two trimming steps (one with each transistors differential

+  *             pair NMOS and PMOS)

+  * @retval None

+  */

+__STATIC_INLINE void LL_OPAMP_SetCalibrationSelection(OPAMP_TypeDef *OPAMPx, uint32_t TransistorsDiffPair)

+{

+  /* Parameter used with mask "OPAMP_TRIMMING_SELECT_MASK" because            */

+  /* containing other bits reserved for other purpose.                        */

+  MODIFY_REG(OPAMPx->CSR, OPAMP_CSR_CALSEL, ((TransistorsDiffPair & OPAMP_TRIMMING_SELECT_MASK) >> 4));

+}

+

+/**

+  * @brief  Get OPAMP offset to calibrate the selected transistors

+  *         differential pair NMOS or PMOS.

+  * @note   Preliminarily, OPAMP must be set in mode calibration

+  *         using function @ref LL_OPAMP_SetMode().

+  * @rmtoll CSR      CALSEL         LL_OPAMP_GetCalibrationSelection

+  * @param  OPAMPx OPAMP instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_OPAMP_TRIMMING_NMOS            (1)

+  *         @arg @ref LL_OPAMP_TRIMMING_PMOS            (1)

+  *         @arg @ref LL_OPAMP_TRIMMING_NMOS_VREF_50PC_VDDA

+  *         @arg @ref LL_OPAMP_TRIMMING_PMOS_VREF_3_3PC_VDDA

+  *

+  *         (1) Default parameters to be used for calibration

+  *             using two trimming steps (one with each transistors differential

+  *             pair NMOS and PMOS)

+  */

+__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx)

+{

+  register uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALSEL));

+

+  return (uint32_t)((CalibrationSelection << 4)|

+          (((CalibrationSelection & OPAMP_CSR_CALSEL_1) == 0UL) ? OPAMP_OTR_TRIMOFFSETN : OPAMP_OTR_TRIMOFFSETP));

+}

+

+/**

+  * @brief  Get OPAMP calibration result of toggling output.

+  * @note   This functions returns:

+  *         0 if OPAMP calibration output is reset

+  *         1 if OPAMP calibration output is set

+  * @rmtoll CSR      OUTCAL         LL_OPAMP_IsCalibrationOutputSet

+  * @param  OPAMPx OPAMP instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(OPAMP_TypeDef *OPAMPx)

+{

+  return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALOUT) == OPAMP_CSR_CALOUT)?1UL:0UL);

+}

+

+/**

+  * @brief  Set OPAMP trimming factor for the selected transistors

+  *         differential pair NMOS or PMOS, corresponding to the selected

+  *         power mode.

+  * @rmtoll OTR      TRIMOFFSETN    LL_OPAMP_SetTrimmingValue\n

+  *         OTR      TRIMOFFSETP    LL_OPAMP_SetTrimmingValue\n

+  *         HSOTR    TRIMHSOFFSETN  LL_OPAMP_SetTrimmingValue\n

+  *         HSOTR    TRIMHSOFFSETP  LL_OPAMP_SetTrimmingValue

+  * @param  OPAMPx OPAMP instance

+  * @param  PowerMode This parameter can be one of the following values:

+  *         @arg @ref LL_OPAMP_POWERMODE_NORMAL

+  *         @arg @ref LL_OPAMP_POWERMODE_HIGHSPEED

+  * @param  TransistorsDiffPair This parameter can be one of the following values:

+  *         @arg @ref LL_OPAMP_TRIMMING_NMOS

+  *         @arg @ref LL_OPAMP_TRIMMING_PMOS

+  * @param  TrimmingValue 0x00...0x1F

+  * @retval None

+  */

+__STATIC_INLINE void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair, uint32_t TrimmingValue)

+{

+  register __IO uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK));

+

+  /* Set bits with position in register depending on parameter                */

+  /* "TransistorsDiffPair".                                                   */

+  /* Parameter used with mask "OPAMP_TRIMMING_VALUE_MASK" because             */

+  /* containing other bits reserved for other purpose.                        */

+  MODIFY_REG(*preg,

+             (TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK) << 1U,

+             TrimmingValue << ((TransistorsDiffPair == LL_OPAMP_TRIMMING_NMOS) ? OPAMP_OTR_TRIMOFFSETN_Pos : OPAMP_OTR_TRIMOFFSETP_Pos));

+}

+

+/**

+  * @brief  Get OPAMP trimming factor for the selected transistors

+  *         differential pair NMOS or PMOS, corresponding to the selected

+  *         power mode.

+  * @rmtoll OTR      TRIMOFFSETN    LL_OPAMP_GetTrimmingValue\n

+  *         OTR      TRIMOFFSETP    LL_OPAMP_GetTrimmingValue\n

+  *         HSOTR    TRIMHSOFFSETN  LL_OPAMP_GetTrimmingValue\n

+  *         HSOTR    TRIMHSOFFSETP  LL_OPAMP_GetTrimmingValue

+  * @param  OPAMPx OPAMP instance

+  * @param  PowerMode This parameter can be one of the following values:

+  *         @arg @ref LL_OPAMP_POWERMODE_NORMAL

+  *         @arg @ref LL_OPAMP_POWERMODE_HIGHSPEED

+  * @param  TransistorsDiffPair This parameter can be one of the following values:

+  *         @arg @ref LL_OPAMP_TRIMMING_NMOS

+  *         @arg @ref LL_OPAMP_TRIMMING_PMOS

+  * @retval 0x0...0x1F

+  */

+__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair)

+{

+  register const __IO uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK));

+

+  /* Retrieve bits with position in register depending on parameter           */

+  /* "TransistorsDiffPair".                                                   */

+  /* Parameter used with mask "OPAMP_TRIMMING_VALUE_MASK" because             */

+  /* containing other bits reserved for other purpose.                        */

+  return (uint32_t)(READ_BIT(*preg, (TransistorsDiffPair & OPAMP_TRIMMING_VALUE_MASK))

+                    >> ((TransistorsDiffPair == LL_OPAMP_TRIMMING_NMOS) ? OPAMP_OTR_TRIMOFFSETN_Pos : OPAMP_OTR_TRIMOFFSETP_Pos));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup OPAMP_LL_EF_OPERATION Operation on OPAMP instance

+  * @{

+  */

+/**

+  * @brief  Enable OPAMP instance.

+  * @note   After enable from off state, OPAMP requires a delay

+  *         to fullfill wake up time specification.

+  *         Refer to device datasheet, parameter "tWAKEUP".

+  * @rmtoll CSR      OPAMPXEN       LL_OPAMP_Enable

+  * @param  OPAMPx OPAMP instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_OPAMP_Enable(OPAMP_TypeDef *OPAMPx)

+{

+  SET_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN);

+}

+

+/**

+  * @brief  Disable OPAMP instance.

+  * @rmtoll CSR      OPAMPXEN       LL_OPAMP_Disable

+  * @param  OPAMPx OPAMP instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_OPAMP_Disable(OPAMP_TypeDef *OPAMPx)

+{

+  CLEAR_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN);

+}

+

+/**

+  * @brief  Get OPAMP instance enable state

+  *         (0: OPAMP is disabled, 1: OPAMP is enabled)

+  * @rmtoll CSR      OPAMPXEN       LL_OPAMP_IsEnabled

+  * @param  OPAMPx OPAMP instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_OPAMP_IsEnabled(OPAMP_TypeDef *OPAMPx)

+{

+  return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN) == (OPAMP_CSR_OPAMPxEN))?1UL:0UL);

+}

+/**

+  * @}

+  */

+

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup OPAMP_LL_EF_Init Initialization and de-initialization functions

+  * @{

+  */

+

+ErrorStatus LL_OPAMP_DeInit(OPAMP_TypeDef *OPAMPx);

+ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct);

+void        LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct);

+

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* OPAMP1 || OPAMP2 */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* __STM32H7xx_LL_OPAMP_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_pwr.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_pwr.h
new file mode 100644
index 0000000000..1916958450
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_pwr.h
@@ -0,0 +1,2249 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_pwr.h

+  * @author  MCD Application Team

+  * @brief   Header file of PWR LL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_LL_PWR_H

+#define STM32H7xx_LL_PWR_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+#if defined (PWR)

+

+/** @defgroup PWR_LL PWR

+  * @{

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup PWR_LL_Private_Constants PWR Private Constants

+  * @{

+  */

+

+/** @defgroup PWR_LL_WAKEUP_PIN_OFFSET Wake-Up Pins register offsets Defines

+  * @brief    Flags defines which can be used with LL_PWR_WriteReg function

+  * @{

+  */

+/* Wake-Up Pins PWR register offsets */

+#define LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET    2UL

+#define LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK       0x1FU

+/**

+  * @}

+  */

+/**

+  * @}

+  */

+/* Private macros ------------------------------------------------------------*/

+/* Exported types ------------------------------------------------------------*/

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants

+  * @{

+  */

+

+/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines

+  * @brief    Flags defines which can be used with LL_PWR_WriteReg function

+  * @{

+  */

+#define LL_PWR_FLAG_CPU_CSSF          PWR_CPUCR_CSSF      /*!< Clear flags for CPU  */

+#if defined (DUAL_CORE)

+#define LL_PWR_FLAG_CPU2_CSSF         PWR_CPU2CR_CSSF     /*!< Clear flags for CPU2 */

+#endif /* DUAL_CORE */

+#define LL_PWR_FLAG_WKUPCR_WKUPC6     PWR_WKUPCR_WKUPC6   /*!< Clear PC1 WKUP flag  */

+#define LL_PWR_FLAG_WKUPCR_WKUPC5     PWR_WKUPCR_WKUPC5   /*!< Clear PI11 WKUP flag */

+#define LL_PWR_FLAG_WKUPCR_WKUPC4     PWR_WKUPCR_WKUPC4   /*!< Clear PC13 WKUP flag */

+#define LL_PWR_FLAG_WKUPCR_WKUPC3     PWR_WKUPCR_WKUPC3   /*!< Clear PI8 WKUP flag  */

+#define LL_PWR_FLAG_WKUPCR_WKUPC2     PWR_WKUPCR_WKUPC2   /*!< Clear PA2 WKUP flag  */

+#define LL_PWR_FLAG_WKUPCR_WKUPC1     PWR_WKUPCR_WKUPC1   /*!< Clear PA0 WKUP flag  */

+/**

+  * @}

+  */

+

+/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines

+  * @brief    Flags defines which can be used with LL_PWR_ReadReg function

+  * @{

+  */

+#define LL_PWR_FLAG_AVDO              PWR_CSR1_AVDO       /*!< Analog voltage detector output on VDDA flag                          */

+#define LL_PWR_FLAG_PVDO              PWR_CSR1_PVDO       /*!< Programmable voltage detect output flag                              */

+#define LL_PWR_FLAG_ACTVOS            PWR_CSR1_ACTVOS     /*!< Current VOS applied for VCORE voltage scaling flag                   */

+#define LL_PWR_FLAG_ACTVOSRDY         PWR_CSR1_ACTVOSRDY  /*!< Ready bit for current actual used VOS for VCORE voltage scaling flag */

+#if defined (PWR_CSR1_MMCVDO)

+#define LL_PWR_FLAG_MMCVDO            PWR_CSR1_MMCVDO     /*!< Voltage detector output on VDDMMC flag                               */

+#endif /* PWR_CSR1_MMCVDO */

+

+#define LL_PWR_FLAG_TEMPH             PWR_CR2_TEMPH       /*!< Temperature high threshold flag */

+#define LL_PWR_FLAG_TEMPL             PWR_CR2_TEMPL       /*!< Temperature low threshold flag  */

+#define LL_PWR_FLAG_VBATH             PWR_CR2_VBATH       /*!< VBAT high threshold flag        */

+#define LL_PWR_FLAG_VBATL             PWR_CR2_VBATL       /*!< VBAT low threshold flag         */

+#define LL_PWR_FLAG_BRRDY             PWR_CR2_BRRDY       /*!< Backup Regulator ready flag     */

+

+#define LL_PWR_FLAG_USBRDY            PWR_CR3_USB33RDY    /*!< USB supply ready flag           */

+#define LL_PWR_FLAG_SMPSEXTRDY        PWR_CR3_SMPSEXTRDY  /*!< SMPS External supply ready flag */

+

+#if defined (PWR_CPUCR_SBF_D2)

+#define LL_PWR_FLAG_CPU_SBF_D2        PWR_CPUCR_SBF_D2    /*!< D2 domain DSTANDBY Flag  */

+#endif /* PWR_CPUCR_SBF_D2 */

+#if defined (PWR_CPUCR_SBF_D1)

+#define LL_PWR_FLAG_CPU_SBF_D1        PWR_CPUCR_SBF_D1    /*!< D1 domain DSTANDBY Flag  */

+#endif /* PWR_CPUCR_SBF_D1 */

+#define LL_PWR_FLAG_CPU_SBF           PWR_CPUCR_SBF       /*!< System STANDBY Flag      */

+#define LL_PWR_FLAG_CPU_STOPF         PWR_CPUCR_STOPF     /*!< STOP Flag                */

+#if defined (DUAL_CORE)

+#define LL_PWR_FLAG_CPU_HOLD2F        PWR_CPUCR_HOLD2F    /*!< CPU2 in hold wakeup flag */

+#endif /* DUAL_CORE */

+

+#if defined (DUAL_CORE)

+#define LL_PWR_FLAG_CPU2_SBF_D2       PWR_CPU2CR_SBF_D2   /*!< D2 domain DSTANDBY Flag  */

+#define LL_PWR_FLAG_CPU2_SBF_D1       PWR_CPU2CR_SBF_D1   /*!< D1 domain DSTANDBY Flag  */

+#define LL_PWR_FLAG_CPU2_SBF          PWR_CPU2CR_SBF      /*!< System STANDBY Flag      */

+#define LL_PWR_FLAG_CPU2_STOPF        PWR_CPU2CR_STOPF    /*!< STOP Flag                */

+#define LL_PWR_FLAG_CPU2_HOLD1F       PWR_CPU2CR_HOLD1F   /*!< CPU1 in hold wakeup flag */

+#endif /* DUAL_CORE */

+

+#if defined (PWR_CPUCR_PDDS_D2)

+#define LL_PWR_D3CR_VOSRDY            PWR_D3CR_VOSRDY     /*!< Voltage scaling ready flag */

+#else

+#define LL_PWR_SRDCR_VOSRDY           PWR_SRDCR_VOSRDY    /*!< Voltage scaling ready flag */

+#endif /* PWR_CPUCR_PDDS_D2 */

+

+#define LL_PWR_WKUPFR_WKUPF6          PWR_WKUPFR_WKUPF6   /*!< Wakeup flag on PC1  */

+#define LL_PWR_WKUPFR_WKUPF5          PWR_WKUPFR_WKUPF5   /*!< Wakeup flag on PI11 */

+#define LL_PWR_WKUPFR_WKUPF4          PWR_WKUPFR_WKUPF4   /*!< Wakeup flag on PC13 */

+#define LL_PWR_WKUPFR_WKUPF3          PWR_WKUPFR_WKUPF3   /*!< Wakeup flag on PI8  */

+#define LL_PWR_WKUPFR_WKUPF2          PWR_WKUPFR_WKUPF2   /*!< Wakeup flag on PA2  */

+#define LL_PWR_WKUPFR_WKUPF1          PWR_WKUPFR_WKUPF1   /*!< Wakeup flag on PA0  */

+/**

+  * @}

+  */

+

+/** @defgroup PWR_LL_EC_MODE_PWR Power mode

+  * @{

+  */

+#if defined (PWR_CPUCR_PDDS_D2)

+#define LL_PWR_CPU_MODE_D1STOP        0x00000000U           /*!< Enter D1 domain to Stop mode when the CPU enters deepsleep       */

+#define LL_PWR_CPU_MODE_D1STANDBY     PWR_CPUCR_PDDS_D1     /*!< Enter D1 domain to Standby mode when the CPU enters deepsleep    */

+#else

+#define LL_PWR_CPU_MODE_CDSTOP        0x00000000U           /*!< Enter CD domain to Stop mode when the CPU enters deepsleep       */

+#define LL_PWR_CPU_MODE_CDSTOP2       PWR_CPUCR_RETDS_CD    /*!< Enter CD domain to Stop2 mode when the CPU enters deepsleep      */

+#endif /* PWR_CPUCR_PDDS_D2 */

+

+#if defined (PWR_CPUCR_PDDS_D2)

+#define LL_PWR_CPU_MODE_D2STOP        0x00000000U           /*!< Enter D2 domain to Stop mode when the CPU enters deepsleep       */

+#define LL_PWR_CPU_MODE_D2STANDBY     PWR_CPUCR_PDDS_D2     /*!< Enter D2 domain to Standby mode when the CPU enters deepsleep    */

+#endif /* PWR_CPUCR_PDDS_D2 */

+

+#if defined (PWR_CPUCR_PDDS_D2)

+#define LL_PWR_CPU_MODE_D3RUN         PWR_CPUCR_RUN_D3      /*!< Keep system D3 domain in Run mode when the CPU enter deepsleep   */

+#define LL_PWR_CPU_MODE_D3STOP        0x00000000U           /*!< Enter D3 domain to Stop mode when the CPU enters deepsleep       */

+#define LL_PWR_CPU_MODE_D3STANDBY     PWR_CPUCR_PDDS_D3     /*!< Enter D3 domain to Standby mode when the CPU enters deepsleep    */

+#else

+#define LL_PWR_CPU_MODE_SRDRUN        PWR_CPUCR_RUN_SRD     /*!< Keep system SRD domain in Run mode when the CPU enter deepsleep  */

+#define LL_PWR_CPU_MODE_SRDSTOP       0x00000000U           /*!< Enter SRD domain to Stop mode when the CPU enters deepsleep      */

+#define LL_PWR_CPU_MODE_SRDSTANDBY    PWR_CPUCR_PDDS_SRD    /*!< Enter SRD domain to Standby mode when the CPU enters deepsleep   */

+#endif /* PWR_CPUCR_PDDS_D2 */

+

+#if defined (DUAL_CORE)

+#define LL_PWR_CPU2_MODE_D1STOP       0x00000000U           /*!< Enter D1 domain to Stop mode when the CPU2 enters deepsleep      */

+#define LL_PWR_CPU2_MODE_D1STANDBY    PWR_CPU2CR_PDDS_D1    /*!< Enter D1 domain to Standby mode when the CPU2 enters deepsleep   */

+#define LL_PWR_CPU2_MODE_D2STOP       0x00000000U           /*!< Enter D2 domain to Stop mode when the CPU2 enters deepsleep      */

+#define LL_PWR_CPU2_MODE_D2STANDBY    PWR_CPU2CR_PDDS_D2    /*!< Enter D2 domain to Standby mode when the CPU2 enters deepsleep   */

+#define LL_PWR_CPU2_MODE_D3RUN        PWR_CPU2CR_RUN_D3     /*!< Keep system D3 domain in RUN mode when the CPU2 enter deepsleep  */

+#define LL_PWR_CPU2_MODE_D3STOP       0x00000000U           /*!< Enter D3 domain to Stop mode when the CPU2 enters deepsleep      */

+#define LL_PWR_CPU2_MODE_D3STANDBY    PWR_CPU2CR_PDDS_D3    /*!< Enter D3 domain to Standby mode when the CPU2 enter deepsleep    */

+#endif /* DUAL_CORE */

+/**

+  * @}

+  */

+

+/** @defgroup PWR_LL_EC_REGU_VOLTAGE Run mode Regulator Voltage Scaling

+  * @{

+  */

+#if defined (PWR_CPUCR_PDDS_D2)

+#define LL_PWR_REGU_VOLTAGE_SCALE3      PWR_D3CR_VOS_0                    /*!< Select voltage scale 3 */

+#define LL_PWR_REGU_VOLTAGE_SCALE2      PWR_D3CR_VOS_1                    /*!< Select voltage scale 2 */

+#define LL_PWR_REGU_VOLTAGE_SCALE1      (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 1 */

+#define LL_PWR_REGU_VOLTAGE_SCALE0      (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 0 */

+#else

+#define LL_PWR_REGU_VOLTAGE_SCALE3      0x00000000U                       /*!< Select voltage scale 3 */

+#define LL_PWR_REGU_VOLTAGE_SCALE2      PWR_D3CR_VOS_0                    /*!< Select voltage scale 2 */

+#define LL_PWR_REGU_VOLTAGE_SCALE1      PWR_D3CR_VOS_1                    /*!< Select voltage scale 1 */

+#define LL_PWR_REGU_VOLTAGE_SCALE0      (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 0 */

+#endif /* PWR_CPUCR_PDDS_D2 */

+/**

+  * @}

+  */

+

+/** @defgroup PWR_LL_EC_STOP_MODE_REGU_VOLTAGE Stop mode Regulator Voltage Scaling

+  * @{

+  */

+#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE5   PWR_CR1_SVOS_0                    /*!< Select voltage scale 5 when system enters STOP mode */

+#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE4   PWR_CR1_SVOS_1                    /*!< Select voltage scale 4 when system enters STOP mode */

+#define LL_PWR_REGU_VOLTAGE_SVOS_SCALE3   (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1) /*!< Select voltage scale 3 when system enters STOP mode */

+/**

+  * @}

+  */

+

+/** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE  Regulator Mode In Deep Sleep Mode

+  * @{

+  */

+#define LL_PWR_REGU_DSMODE_MAIN           0x00000000U   /*!< Voltage Regulator in main mode during deepsleep mode      */

+#define LL_PWR_REGU_DSMODE_LOW_POWER      PWR_CR1_LPDS  /*!< Voltage Regulator in low-power mode during deepsleep mode */

+/**

+  * @}

+  */

+

+/** @defgroup PWR_LL_EC_PVDLEVEL Power Digital Voltage Level Detector

+  * @{

+  */

+#define LL_PWR_PVDLEVEL_0   PWR_CR1_PLS_LEV0  /*!< Voltage threshold detected by PVD 1.95 V */

+#define LL_PWR_PVDLEVEL_1   PWR_CR1_PLS_LEV1  /*!< Voltage threshold detected by PVD 2.1 V  */

+#define LL_PWR_PVDLEVEL_2   PWR_CR1_PLS_LEV2  /*!< Voltage threshold detected by PVD 2.25 V */

+#define LL_PWR_PVDLEVEL_3   PWR_CR1_PLS_LEV3  /*!< Voltage threshold detected by PVD 2.4 V  */

+#define LL_PWR_PVDLEVEL_4   PWR_CR1_PLS_LEV4  /*!< Voltage threshold detected by PVD 2.55 V */

+#define LL_PWR_PVDLEVEL_5   PWR_CR1_PLS_LEV5  /*!< Voltage threshold detected by PVD 2.7 V  */

+#define LL_PWR_PVDLEVEL_6   PWR_CR1_PLS_LEV6  /*!< Voltage threshold detected by PVD 2.85 V */

+#define LL_PWR_PVDLEVEL_7   PWR_CR1_PLS_LEV7  /*!< External voltage level on PVD_IN pin, compared to internal VREFINT level. */

+/**

+  * @}

+  */

+

+/** @defgroup PWR_LL_EC_AVDLEVEL Power Analog Voltage Level Detector

+  * @{

+  */

+#define LL_PWR_AVDLEVEL_0   PWR_CR1_ALS_LEV0  /*!< Analog Voltage threshold detected by AVD 1.7 V */

+#define LL_PWR_AVDLEVEL_1   PWR_CR1_ALS_LEV1  /*!< Analog Voltage threshold detected by AVD 2.1 V */

+#define LL_PWR_AVDLEVEL_2   PWR_CR1_ALS_LEV2  /*!< Analog Voltage threshold detected by AVD 2.5 V */

+#define LL_PWR_AVDLEVEL_3   PWR_CR1_ALS_LEV3  /*!< Analog Voltage threshold detected by AVD 2.8 V */

+

+/**

+  * @}

+  */

+

+/** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR Battery Charge Resistor

+  * @{

+  */

+#define LL_PWR_BATT_CHARG_RESISTOR_5K     0x00000000U   /*!< Charge the Battery through a 5 kO resistor    */

+#define LL_PWR_BATT_CHARGRESISTOR_1_5K    PWR_CR3_VBRS  /*!< Charge the Battery through a 1.5 kO resistor  */

+/**

+  * @}

+  */

+

+/** @defgroup PWR_LL_EC_WAKEUP_PIN  Wakeup Pins

+  * @{

+  */

+#define LL_PWR_WAKEUP_PIN1    PWR_WKUPEPR_WKUPEN1  /*!< Wake-Up pin 1 : PA0  */

+#define LL_PWR_WAKEUP_PIN2    PWR_WKUPEPR_WKUPEN2  /*!< Wake-Up pin 2 : PA2  */

+#define LL_PWR_WAKEUP_PIN3    PWR_WKUPEPR_WKUPEN3  /*!< Wake-Up pin 3 : PI8  */

+#define LL_PWR_WAKEUP_PIN4    PWR_WKUPEPR_WKUPEN4  /*!< Wake-Up pin 4 : PC13 */

+#define LL_PWR_WAKEUP_PIN5    PWR_WKUPEPR_WKUPEN5  /*!< Wake-Up pin 5 : PI11 */

+#define LL_PWR_WAKEUP_PIN6    PWR_WKUPEPR_WKUPEN6  /*!< Wake-Up pin 6 : PC1  */

+/**

+  * @}

+  */

+

+/** @defgroup PWR_LL_EC_WAKEUP_PIN_PULL  Wakeup Pins pull configuration

+  * @{

+  */

+#define LL_PWR_WAKEUP_PIN_NOPULL      0x00000000UL   /*!< Configure Wake-Up pin in no pull   */

+#define LL_PWR_WAKEUP_PIN_PULLUP      0x00000001UL   /*!< Configure Wake-Up pin in pull Up   */

+#define LL_PWR_WAKEUP_PIN_PULLDOWN    0x00000002UL   /*!< Configure Wake-Up pin in pull Down */

+/**

+  * @}

+  */

+

+/** @defgroup PWR_LL_EC_SUPPLY_PWR Power supply source configuration

+  * @{

+  */

+#define LL_PWR_LDO_SUPPLY                     PWR_CR3_LDOEN                                                               /*!< Core domains are suppplied from the LDO                                                                     */

+#if defined (SMPS)                                                                                                                                                                                                                       

+#define LL_PWR_DIRECT_SMPS_SUPPLY             PWR_CR3_SMPSEN                                                              /*!< Core domains are suppplied from the SMPS                                                                    */

+#define LL_PWR_SMPS_1V8_SUPPLIES_LDO          (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)                      /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains                                       */

+#define LL_PWR_SMPS_2V5_SUPPLIES_LDO          (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)                      /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains                                       */

+#define LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO  (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */

+#define LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO  (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN)  /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */

+#define LL_PWR_SMPS_1V8_SUPPLIES_EXT          (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains                            */

+#define LL_PWR_SMPS_2V5_SUPPLIES_EXT          (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains                            */

+#endif /* SMPS */

+#define LL_PWR_EXTERNAL_SOURCE_SUPPLY         PWR_CR3_BYPASS                                                              /*!< The SMPS and the LDO are Bypassed. The Core domains are supplied from an external source                    */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros

+  * @{

+  */

+

+/** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros

+  * @{

+  */

+

+/**

+  * @brief  Write a value in PWR register

+  * @param  __REG__ Register to be written

+  * @param  __VALUE__ Value to be written in the register

+  * @retval None

+  */

+#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))

+

+/**

+  * @brief  Read a value in PWR register

+  * @param  __REG__ Register to be read

+  * @retval Register value

+  */

+#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions

+  * @{

+  */

+

+/** @defgroup PWR_LL_EF_Configuration Configuration

+  * @{

+  */

+

+  /**

+  * @brief  Set the voltage Regulator mode during deep sleep mode

+  * @rmtoll CR1    LPDS         LL_PWR_SetRegulModeDS

+  * @param  RegulMode This parameter can be one of the following values:

+  *         @arg @ref LL_PWR_REGU_DSMODE_MAIN

+  *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)

+{

+  MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, RegulMode);

+}

+

+/**

+  * @brief  Get the voltage Regulator mode during deep sleep mode

+  * @rmtoll CR1    LPDS         LL_PWR_GetRegulModeDS

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_PWR_REGU_DSMODE_MAIN

+  *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER

+  */

+__STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)

+{

+  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPDS));

+}

+

+/**

+  * @brief  Enable Power Voltage Detector

+  * @rmtoll CR1    PVDEN       LL_PWR_EnablePVD

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_EnablePVD(void)

+{

+  SET_BIT(PWR->CR1, PWR_CR1_PVDEN);

+}

+

+/**

+  * @brief  Disable Power Voltage Detector

+  * @rmtoll CR1    PVDEN       LL_PWR_DisablePVD

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_DisablePVD(void)

+{

+  CLEAR_BIT(PWR->CR1, PWR_CR1_PVDEN);

+}

+

+/**

+  * @brief  Check if Power Voltage Detector is enabled

+  * @rmtoll CR1    PVDEN       LL_PWR_IsEnabledPVD

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)

+{

+  return ((READ_BIT(PWR->CR1, PWR_CR1_PVDEN) == (PWR_CR1_PVDEN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Configure the voltage threshold detected by the Power Voltage Detector

+  * @rmtoll CR1    PLS       LL_PWR_SetPVDLevel

+  * @param  PVDLevel This parameter can be one of the following values:

+  *         @arg @ref LL_PWR_PVDLEVEL_0

+  *         @arg @ref LL_PWR_PVDLEVEL_1

+  *         @arg @ref LL_PWR_PVDLEVEL_2

+  *         @arg @ref LL_PWR_PVDLEVEL_3

+  *         @arg @ref LL_PWR_PVDLEVEL_4

+  *         @arg @ref LL_PWR_PVDLEVEL_5

+  *         @arg @ref LL_PWR_PVDLEVEL_6

+  *         @arg @ref LL_PWR_PVDLEVEL_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)

+{

+  MODIFY_REG(PWR->CR1, PWR_CR1_PLS, PVDLevel);

+}

+

+/**

+  * @brief  Get the voltage threshold detection

+  * @rmtoll CR1    PLS       LL_PWR_GetPVDLevel

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_PWR_PVDLEVEL_0

+  *         @arg @ref LL_PWR_PVDLEVEL_1

+  *         @arg @ref LL_PWR_PVDLEVEL_2

+  *         @arg @ref LL_PWR_PVDLEVEL_3

+  *         @arg @ref LL_PWR_PVDLEVEL_4

+  *         @arg @ref LL_PWR_PVDLEVEL_5

+  *         @arg @ref LL_PWR_PVDLEVEL_6

+  *         @arg @ref LL_PWR_PVDLEVEL_7

+  */

+__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)

+{

+  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_PLS));

+}

+

+/**

+  * @brief  Enable access to the backup domain

+  * @rmtoll CR1    DBP       LL_PWR_EnableBkUpAccess

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)

+{

+  SET_BIT(PWR->CR1, PWR_CR1_DBP);

+}

+

+/**

+  * @brief  Disable access to the backup domain

+  * @rmtoll CR1    DBP       LL_PWR_DisableBkUpAccess

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)

+{

+  CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);

+}

+

+/**

+  * @brief  Check if the backup domain is enabled

+  * @rmtoll CR1    DBP       LL_PWR_IsEnabledBkUpAccess

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)

+{

+  return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the Flash Power Down in Stop Mode

+  * @rmtoll CR1    FLPS       LL_PWR_EnableFlashPowerDown

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)

+{

+  SET_BIT(PWR->CR1, PWR_CR1_FLPS);

+}

+

+/**

+  * @brief  Disable the Flash Power Down in Stop Mode

+  * @rmtoll CR1    FLPS       LL_PWR_DisableFlashPowerDown

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)

+{

+  CLEAR_BIT(PWR->CR1, PWR_CR1_FLPS);

+}

+

+/**

+  * @brief  Check if the Flash Power Down in Stop Mode is enabled

+  * @rmtoll CR1    FLPS       LL_PWR_IsEnabledFlashPowerDown

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)

+{

+  return ((READ_BIT(PWR->CR1, PWR_CR1_FLPS) == (PWR_CR1_FLPS)) ? 1UL : 0UL);

+}

+

+#if defined (PWR_CR1_BOOSTE)

+/**

+  * @brief  Enable the Analog Voltage Booster (VDDA)

+  * @rmtoll CR1    BOOSTE     LL_PWR_EnableAnalogBooster

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_EnableAnalogBooster(void)

+{

+  SET_BIT(PWR->CR1, PWR_CR1_BOOSTE);

+}

+

+/**

+  * @brief  Disable the Analog Voltage Booster (VDDA)

+  * @rmtoll CR1    BOOSTE     LL_PWR_DisableAnalogBooster

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_DisableAnalogBooster(void)

+{

+  CLEAR_BIT(PWR->CR1, PWR_CR1_BOOSTE);

+}

+

+/**

+  * @brief  Check if the Analog Voltage Booster (VDDA) is enabled

+  * @rmtoll CR1    BOOSTE     LL_PWR_IsEnabledAnalogBooster

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogBooster(void)

+{

+  return ((READ_BIT(PWR->CR1, PWR_CR1_BOOSTE) == (PWR_CR1_BOOSTE)) ? 1UL : 0UL);

+}

+#endif /* PWR_CR1_BOOSTE */

+

+#if defined (PWR_CR1_AVD_READY)

+/**

+  * @brief  Enable the Analog Voltage Ready to isolate the BOOST IP untill VDDA will be ready

+  * @rmtoll CR1    AVD_READY  LL_PWR_EnableAnalogVoltageReady

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_EnableAnalogVoltageReady(void)

+{

+  SET_BIT(PWR->CR1, PWR_CR1_AVD_READY);

+}

+

+/**

+  * @brief  Disable the Analog Voltage Ready (VDDA)

+  * @rmtoll CR1    AVD_READY  LL_PWR_DisableAnalogVoltageReady

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_DisableAnalogVoltageReady(void)

+{

+  CLEAR_BIT(PWR->CR1, PWR_CR1_AVD_READY);

+}

+

+/**

+  * @brief  Check if the Analog Voltage Booster (VDDA) is enabled

+  * @rmtoll CR1    AVD_READY  LL_PWR_IsEnabledAnalogVoltageReady

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogVoltageReady(void)

+{

+  return ((READ_BIT(PWR->CR1, PWR_CR1_AVD_READY) == (PWR_CR1_AVD_READY)) ? 1UL : 0UL);

+}

+#endif /* PWR_CR1_AVD_READY */

+

+/**

+  * @brief  Set the internal Regulator output voltage in STOP mode

+  * @rmtoll CR1    SVOS       LL_PWR_SetStopModeRegulVoltageScaling

+  * @param  VoltageScaling This parameter can be one of the following values:

+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3

+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4

+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_SetStopModeRegulVoltageScaling(uint32_t VoltageScaling)

+{

+  MODIFY_REG(PWR->CR1, PWR_CR1_SVOS, VoltageScaling);

+}

+

+/**

+  * @brief  Get the internal Regulator output voltage in STOP mode

+  * @rmtoll CR1    SVOS       LL_PWR_GetStopModeRegulVoltageScaling

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3

+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4

+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5

+  */

+__STATIC_INLINE uint32_t LL_PWR_GetStopModeRegulVoltageScaling(void)

+{

+  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_SVOS));

+}

+

+/**

+  * @brief  Enable Analog Power Voltage Detector

+  * @rmtoll CR1    AVDEN       LL_PWR_EnableAVD

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_EnableAVD(void)

+{

+  SET_BIT(PWR->CR1, PWR_CR1_AVDEN);

+}

+

+/**

+  * @brief  Disable Analog Power Voltage Detector

+  * @rmtoll CR1    AVDEN       LL_PWR_DisableAVD

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_DisableAVD(void)

+{

+  CLEAR_BIT(PWR->CR1, PWR_CR1_AVDEN);

+}

+

+/**

+  * @brief  Check if Analog Power Voltage Detector is enabled

+  * @rmtoll CR1    AVDEN       LL_PWR_IsEnabledAVD

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAVD(void)

+{

+  return ((READ_BIT(PWR->CR1, PWR_CR1_AVDEN) == (PWR_CR1_AVDEN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Configure the voltage threshold to be detected by the Analog Power Voltage Detector

+  * @rmtoll CR1    ALS       LL_PWR_SetAVDLevel

+  * @param  AVDLevel This parameter can be one of the following values:

+  *         @arg @ref LL_PWR_AVDLEVEL_0

+  *         @arg @ref LL_PWR_AVDLEVEL_1

+  *         @arg @ref LL_PWR_AVDLEVEL_2

+  *         @arg @ref LL_PWR_AVDLEVEL_3

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_SetAVDLevel(uint32_t AVDLevel)

+{

+  MODIFY_REG(PWR->CR1, PWR_CR1_ALS, AVDLevel);

+}

+

+/**

+  * @brief  Get the Analog Voltage threshold to be detected by the Analog Power Voltage Detector

+  * @rmtoll CR1    ALS       LL_PWR_GetAVDLevel

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_PWR_AVDLEVEL_0

+  *         @arg @ref LL_PWR_AVDLEVEL_1

+  *         @arg @ref LL_PWR_AVDLEVEL_2

+  *         @arg @ref LL_PWR_AVDLEVEL_3

+  */

+__STATIC_INLINE uint32_t LL_PWR_GetAVDLevel(void)

+{

+  return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_ALS));

+}

+

+#if defined (PWR_CR1_AXIRAM1SO)

+/**

+  * @brief  Enable the AXI RAM1 shut-off in DStop/DStop2 mode

+  * @rmtoll CR1    AXIRAM1SO     LL_PWR_EnableAXIRAM1ShutOff

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_EnableAXIRAM1ShutOff(void)

+{

+  SET_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO);

+}

+

+/**

+  * @brief  Disable the AXI RAM1 shut-off in DStop/DStop2 mode

+  * @rmtoll CR1    AXIRAM1SO     LL_PWR_DisableAXIRAM1ShutOff

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_DisableAXIRAM1ShutOff(void)

+{

+  CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO);

+}

+

+/**

+  * @brief  Check if the AXI RAM1 shut-off in DStop/DStop2 mode is enabled

+  * @rmtoll CR1    AXIRAM1SO     LL_PWR_IsEnabledAXIRAM1ShutOff

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM1ShutOff(void)

+{

+  return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO) == (PWR_CR1_AXIRAM1SO)) ? 1UL : 0UL);

+}

+#endif /* PWR_CR1_AXIRAM1SO */

+

+#if defined (PWR_CR1_AXIRAM2SO)

+/**

+  * @brief  Enable the AXI RAM2 shut-off in DStop/DStop2 mode

+  * @rmtoll CR1    AXIRAM2SO     LL_PWR_EnableAXIRAM2ShutOff

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_EnableAXIRAM2ShutOff(void)

+{

+  SET_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO);

+}

+

+/**

+  * @brief  Disable the AXI RAM2 shut-off in DStop/DStop2 mode

+  * @rmtoll CR1    AXIRAM2SO     LL_PWR_DisableAXIRAM2ShutOff

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_DisableAXIRAM2ShutOff(void)

+{

+  CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO);

+}

+

+/**

+  * @brief  Check if the AXI RAM2 shut-off in DStop/DStop2 mode is enabled

+  * @rmtoll CR1    AXIRAM2SO     LL_PWR_IsEnabledAXIRAM2ShutOff

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM2ShutOff(void)

+{

+  return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO) == (PWR_CR1_AXIRAM2SO)) ? 1UL : 0UL);

+}

+#endif /* PWR_CR1_AXIRAM2SO */

+

+#if defined (PWR_CR1_AXIRAM3SO)

+/**

+  * @brief  Enable the AXI RAM3 shut-off in DStop/DStop2 mode

+  * @rmtoll CR1    AXIRAM3SO     LL_PWR_EnableAXIRAM3ShutOff

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_EnableAXIRAM3ShutOff(void)

+{

+  SET_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO);

+}

+

+/**

+  * @brief  Disable the AXI RAM3 shut-off in DStop/DStop2 mode

+  * @rmtoll CR1    AXIRAM3SO     LL_PWR_DisableAXIRAM3ShutOff

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_DisableAXIRAM3ShutOff(void)

+{

+  CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO);

+}

+

+/**

+  * @brief  Check if the AXI RAM3 shut-off in DStop/DStop2 mode is enabled

+  * @rmtoll CR1    AXIRAM3SO     LL_PWR_IsEnabledAXIRAM3ShutOff

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM3ShutOff(void)

+{

+  return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO) == (PWR_CR1_AXIRAM3SO)) ? 1UL : 0UL);

+}

+#endif /* PWR_CR1_AXIRAM3SO */

+

+#if defined (PWR_CR1_AHBRAM1SO)

+/**

+  * @brief  Enable the AHB RAM1 shut-off in DStop/DStop2 mode

+  * @rmtoll CR1    AHBRAM1SO     LL_PWR_EnableAHBRAM1ShutOff

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_EnableAHBRAM1ShutOff(void)

+{

+  SET_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO);

+}

+

+/**

+  * @brief  Disable the AHB RAM1 shut-off in DStop/DStop2 mode

+  * @rmtoll CR1    AHBRAM1SO     LL_PWR_DisableAHBRAM1ShutOff

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_DisableAHBRAM1ShutOff(void)

+{

+  CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO);

+}

+

+/**

+  * @brief  Check if the AHB RAM1 shut-off in DStop/DStop2 mode is enabled

+  * @rmtoll CR1    AHBRAM1SO     LL_PWR_IsEnabledAHBRAM1ShutOff

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM1ShutOff(void)

+{

+  return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO) == (PWR_CR1_AHBRAM1SO)) ? 1UL : 0UL);

+}

+#endif /* PWR_CR1_AHBRAM1SO */

+

+#if defined (PWR_CR1_AHBRAM2SO)

+/**

+  * @brief  Enable the AHB RAM2 shut-off in DStop/DStop2 mode

+  * @rmtoll CR1    AHBRAM2SO     LL_PWR_EnableAHBRAM2ShutOff

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_EnableAHBRAM2ShutOff(void)

+{

+  SET_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO);

+}

+

+/**

+  * @brief  Disable the AHB RAM2 shut-off in DStop/DStop2 mode

+  * @rmtoll CR1    AHBRAM2SO     LL_PWR_DisableAHBRAM2ShutOff

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_DisableAHBRAM2ShutOff(void)

+{

+  CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO);

+}

+

+/**

+  * @brief  Check if the AHB RAM2 shut-off in DStop/DStop2 mode is enabled

+  * @rmtoll CR1    AHBRAM2SO     LL_PWR_IsEnabledAHBRAM2ShutOff

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2ShutOff(void)

+{

+  return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO) == (PWR_CR1_AHBRAM2SO)) ? 1UL : 0UL);

+}

+#endif /* PWR_CR1_AHBRAM2SO */

+

+#if defined (PWR_CR1_ITCMSO)

+/**

+  * @brief  Enable the ITCM shut-off in DStop/DStop2 mode

+  * @rmtoll CR1    ITCMSO     LL_PWR_EnableITCMSOShutOff

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_EnableITCMSOShutOff(void)

+{

+  SET_BIT(PWR->CR1, PWR_CR1_ITCMSO);

+}

+

+/**

+  * @brief  Disable the ITCM shut-off in DStop/DStop2 mode

+  * @rmtoll CR1    ITCMSO     LL_PWR_DisableITCMSOShutOff

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_DisableITCMSOShutOff(void)

+{

+  CLEAR_BIT(PWR->CR1, PWR_CR1_ITCMSO);

+}

+

+/**

+  * @brief  Check if the ITCM shut-off in DStop/DStop2 mode is enabled

+  * @rmtoll CR1    ITCMSO     LL_PWR_IsEnabledITCMShutOff

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsEnabledITCMShutOff(void)

+{

+  return ((READ_BIT(PWR->CR1, PWR_CR1_ITCMSO) == (PWR_CR1_ITCMSO)) ? 1UL : 0UL);

+}

+#endif /* PWR_CR1_ITCMSO */

+

+#if defined (PWR_CR1_HSITFSO)

+/**

+  * @brief  Enable the USB and FDCAN shut-off in DStop/DStop2 mode

+  * @rmtoll CR1    HSITFSO     LL_PWR_EnableHSITFShutOff

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_EnableHSITFShutOff(void)

+{

+  SET_BIT(PWR->CR1, PWR_CR1_HSITFSO);

+}

+

+/**

+  * @brief  Disable the USB and FDCAN shut-off in DStop/DStop2 mode

+  * @rmtoll CR1    HSITFSO     LL_PWR_DisableHSITFShutOff

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_DisableHSITFShutOff(void)

+{

+  CLEAR_BIT(PWR->CR1, PWR_CR1_HSITFSO);

+}

+

+/**

+  * @brief  Check if the USB and FDCAN shut-off in DStop/DStop2 mode is enabled

+  * @rmtoll CR1    HSITFSO     LL_PWR_IsEnabledHSITFShutOff

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsEnabledHSITFShutOff(void)

+{

+  return ((READ_BIT(PWR->CR1, PWR_CR1_HSITFSO) == (PWR_CR1_HSITFSO)) ? 1UL : 0UL);

+}

+#endif /* PWR_CR1_HSITFSO */

+

+#if defined (PWR_CR1_SRDRAMSO)

+/**

+  * @brief  Enable the SRD AHB RAM shut-off in DStop/DStop2 mode

+  * @rmtoll CR1    SRDRAMSO     LL_PWR_EnableSRDRAMShutOff

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_EnableSRDRAMShutOff(void)

+{

+  SET_BIT(PWR->CR1, PWR_CR1_SRDRAMSO);

+}

+

+/**

+  * @brief  Disable the SRD AHB RAM shut-off in DStop/DStop2 mode

+  * @rmtoll CR1    SRDRAMSO     LL_PWR_DisableSRDRAMShutOff

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_DisableSRDRAMShutOff(void)

+{

+  CLEAR_BIT(PWR->CR1, PWR_CR1_SRDRAMSO);

+}

+

+/**

+  * @brief  Check if the SRD AHB RAM shut-off in DStop/DStop2 mode is enabled

+  * @rmtoll CR1    SRDRAMSO     LL_PWR_IsEnabledSRDRAMShutOff

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRDRAMShutOff(void)

+{

+  return ((READ_BIT(PWR->CR1, PWR_CR1_SRDRAMSO) == (PWR_CR1_SRDRAMSO)) ? 1UL : 0UL);

+}

+#endif /* PWR_CR1_SRDRAMSO */

+

+/**

+  * @brief  Enable Backup Regulator

+  * @rmtoll CR2    BREN       LL_PWR_EnableBkUpRegulator

+  * @note When set, the Backup Regulator (used to maintain backup SRAM content in Standby and

+  *       VBAT modes) is enabled. If BRE is reset, the backup Regulator is switched off. The backup

+  *       SRAM can still be used but its content will be lost in the Standby and VBAT modes. Once set,

+  *       the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that

+  *       the data written into the RAM will be maintained in the Standby and VBAT modes.

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)

+{

+  SET_BIT(PWR->CR2, PWR_CR2_BREN);

+}

+

+/**

+  * @brief  Disable Backup Regulator

+  * @rmtoll CR2    BREN       LL_PWR_DisableBkUpRegulator

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)

+{

+  CLEAR_BIT(PWR->CR2, PWR_CR2_BREN);

+}

+

+/**

+  * @brief  Check if the backup Regulator is enabled

+  * @rmtoll CR2    BREN      LL_PWR_IsEnabledBkUpRegulator

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)

+{

+  return ((READ_BIT(PWR->CR2, PWR_CR2_BREN) == (PWR_CR2_BREN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable VBAT and Temperature monitoring

+  * @rmtoll CR2    MONEN       LL_PWR_EnableMonitoring

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_EnableMonitoring(void)

+{

+  SET_BIT(PWR->CR2, PWR_CR2_MONEN);

+}

+

+/**

+  * @brief  Disable VBAT and Temperature monitoring

+  * @rmtoll CR2    MONEN       LL_PWR_DisableMonitoring

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_DisableMonitoring(void)

+{

+  CLEAR_BIT(PWR->CR2, PWR_CR2_MONEN);

+}

+

+/**

+  * @brief  Check if the VBAT and Temperature monitoring is enabled

+  * @rmtoll CR2    MONEN      LL_PWR_IsEnabledMonitoring

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void)

+{

+  return ((READ_BIT(PWR->CR2, PWR_CR2_MONEN) == (PWR_CR2_MONEN)) ? 1UL : 0UL);

+}

+

+#if defined (SMPS)

+/**

+  * @brief  Configure the PWR supply

+  * @rmtoll CR3          BYPASS          LL_PWR_ConfigSupply

+  * @rmtoll CR3          LDOEN           LL_PWR_ConfigSupply

+  * @rmtoll CR3          SMPSEN          LL_PWR_ConfigSupply

+  * @rmtoll CR3          SMPSEXTHP       LL_PWR_ConfigSupply

+  * @rmtoll CR3          SMPSLEVEL       LL_PWR_ConfigSupply

+  * @param  SupplySource This parameter can be one of the following values:

+  *         @arg @ref LL_PWR_LDO_SUPPLY

+  *         @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY

+  *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO

+  *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_LDO

+  *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO

+  *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO

+  *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT

+  *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT

+  *         @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource)

+{

+  /* Set the power supply configuration */

+  MODIFY_REG(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), SupplySource);

+}

+#else

+/**

+  * @brief  Configure the PWR supply

+  * @rmtoll CR3          BYPASS          LL_PWR_ConfigSupply

+  * @rmtoll CR3          LDOEN           LL_PWR_ConfigSupply

+  * @rmtoll CR3          SCUEN           LL_PWR_ConfigSupply

+  * @param  SupplySource This parameter can be one of the following values:

+  *         @arg @ref LL_PWR_LDO_SUPPLY

+  *         @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource)

+{

+  /* Set the power supply configuration */

+  MODIFY_REG(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), SupplySource);

+}

+#endif /* defined (SMPS) */

+

+#if defined (SMPS)

+/**

+  * @brief  Get the PWR supply

+  * @rmtoll CR3          BYPASS          LL_PWR_GetSupply

+  * @rmtoll CR3          LDOEN           LL_PWR_GetSupply

+  * @rmtoll CR3          SMPSEN          LL_PWR_GetSupply

+  * @rmtoll CR3          SMPSEXTHP       LL_PWR_GetSupply

+  * @rmtoll CR3          SMPSLEVEL       LL_PWR_GetSupply

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_PWR_LDO_SUPPLY

+  *         @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY

+  *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO

+  *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_LDO

+  *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO

+  *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO

+  *         @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT

+  *         @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT

+  *         @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY

+  */

+__STATIC_INLINE uint32_t LL_PWR_GetSupply(void)

+{

+  /* Get the power supply configuration */

+  return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)));

+}

+#else

+/**

+  * @brief  Get the PWR supply

+  * @rmtoll CR3          BYPASS          LL_PWR_GetSupply

+  * @rmtoll CR3          LDOEN           LL_PWR_GetSupply

+  * @rmtoll CR3          SCUEN           LL_PWR_GetSupply

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_PWR_LDO_SUPPLY

+  *         @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY

+  */

+__STATIC_INLINE uint32_t LL_PWR_GetSupply(void)

+{

+  /* Get the power supply configuration */

+  return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)));

+}

+#endif /* defined (SMPS) */

+

+/**

+  * @brief  Enable battery charging

+  * @rmtoll CR3          VBE           LL_PWR_EnableBatteryCharging

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)

+{

+  SET_BIT(PWR->CR3, PWR_CR3_VBE);

+}

+

+/**

+  * @brief  Disable battery charging

+  * @rmtoll CR3          VBE           LL_PWR_DisableBatteryCharging

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)

+{

+  CLEAR_BIT(PWR->CR3, PWR_CR3_VBE);

+}

+

+/**

+  * @brief  Check if battery charging is enabled

+  * @rmtoll CR3          VBE           LL_PWR_IsEnabledBatteryCharging

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)

+{

+  return ((READ_BIT(PWR->CR3, PWR_CR3_VBE) == (PWR_CR3_VBE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set the Battery charge resistor impedance

+  * @rmtoll CR3          VBRS          LL_PWR_SetBattChargResistor

+  * @param  Resistor This parameter can be one of the following values:

+  *         @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K

+  *         @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)

+{

+  MODIFY_REG(PWR->CR3, PWR_CR3_VBRS, Resistor);

+}

+

+/**

+  * @brief  Get the Battery charge resistor impedance

+  * @rmtoll CR3          VBRS          LL_PWR_GetBattChargResistor

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K

+  *         @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K

+  */

+__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)

+{

+  return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_VBRS));

+}

+

+/**

+  * @brief  Enable the USB regulator

+  * @rmtoll CR3          USBREGEN           LL_PWR_EnableUSBReg

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_EnableUSBReg(void)

+{

+  SET_BIT(PWR->CR3, PWR_CR3_USBREGEN);

+}

+

+/**

+  * @brief  Disable the USB regulator

+  * @rmtoll CR3          USBREGEN           LL_PWR_DisableUSBReg

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_DisableUSBReg(void)

+{

+  CLEAR_BIT(PWR->CR3, PWR_CR3_USBREGEN);

+}

+

+/**

+  * @brief  Check if the USB regulator is enabled

+  * @rmtoll CR3          USBREGEN           LL_PWR_IsEnabledUSBReg

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBReg(void)

+{

+  return ((READ_BIT(PWR->CR3, PWR_CR3_USBREGEN) == (PWR_CR3_USBREGEN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the USB voltage detector

+  * @rmtoll CR3          USB33DEN           LL_PWR_EnableUSBVoltageDetector

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_EnableUSBVoltageDetector(void)

+{

+  SET_BIT(PWR->CR3, PWR_CR3_USB33DEN);

+}

+

+/**

+  * @brief  Disable the USB voltage detector

+  * @rmtoll CR3          USB33DEN           LL_PWR_DisableUSBVoltageDetector

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_DisableUSBVoltageDetector(void)

+{

+  CLEAR_BIT(PWR->CR3, PWR_CR3_USB33DEN);

+}

+

+/**

+  * @brief  Check if the USB voltage detector is enabled

+  * @rmtoll CR3          USB33DEN           LL_PWR_IsEnabledUSBVoltageDetector

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBVoltageDetector(void)

+{

+  return ((READ_BIT(PWR->CR3, PWR_CR3_USB33DEN) == (PWR_CR3_USB33DEN)) ? 1UL : 0UL);

+}

+

+#if defined (PWR_CPUCR_PDDS_D2)

+/**

+  * @brief  Set the D1 domain Power Down mode when the CPU enters deepsleep

+  * @rmtoll CPUCR     PDDS_D1       LL_PWR_CPU_SetD1PowerMode

+  * @param  PDMode This parameter can be one of the following values:

+  *         @arg @ref LL_PWR_CPU_MODE_D1STOP

+  *         @arg @ref LL_PWR_CPU_MODE_D1STANDBY

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_CPU_SetD1PowerMode(uint32_t PDMode)

+{

+  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D1, PDMode);

+}

+#else

+/**

+  * @brief  Set the CPU domain Power Down mode when the CPU enters deepsleep

+  * @rmtoll CPUCR     RETDS_CD       LL_PWR_CPU_SetCDPowerMode

+  * @param  PDMode This parameter can be one of the following values:

+  *         @arg @ref LL_PWR_CPU_MODE_CDSTOP

+  *         @arg @ref LL_PWR_CPU_MODE_CDSTOP2

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_CPU_SetCDPowerMode(uint32_t PDMode)

+{

+  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_RETDS_CD, PDMode);

+}

+#endif /* PWR_CPUCR_PDDS_D2 */

+

+#if defined (DUAL_CORE)

+/**

+  * @brief  Set the D1 domain Power Down mode when the CPU2 enters deepsleep

+  * @rmtoll CPU2CR     PDDS_D1       LL_PWR_CPU2_SetD1PowerMode

+  * @param  PDMode This parameter can be one of the following values:

+  *         @arg @ref LL_PWR_CPU2_MODE_D1STOP

+  *         @arg @ref LL_PWR_CPU2_MODE_D1STANDBY

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_CPU2_SetD1PowerMode(uint32_t PDMode)

+{

+  MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1, PDMode);

+}

+#endif /* DUAL_CORE */

+

+#if defined (PWR_CPUCR_PDDS_D2)

+/**

+  * @brief  Get the D1 Domain Power Down mode when the CPU enters deepsleep

+  * @rmtoll CPUCR     PDDS_D1       LL_PWR_CPU_GetD1PowerMode

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_PWR_CPU_MODE_D1STOP

+  *         @arg @ref LL_PWR_CPU_MODE_D1STANDBY

+  */

+__STATIC_INLINE uint32_t LL_PWR_CPU_GetD1PowerMode(void)

+{

+  return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1));

+}

+#else

+/**

+  * @brief  Get the CD Domain Power Down mode when the CPU enters deepsleep

+  * @rmtoll CPUCR     RETDS_CD       LL_PWR_CPU_GetCDPowerMode

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_PWR_CPU_MODE_CDSTOP

+  *         @arg @ref LL_PWR_CPU_MODE_CDSTOP2

+  */

+__STATIC_INLINE uint32_t LL_PWR_CPU_GetCDPowerMode(void)

+{

+  return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_RETDS_CD));

+}

+#endif /* PWR_CPUCR_PDDS_D2 */

+

+#if defined (DUAL_CORE)

+/**

+  * @brief  Get the D1 Domain Power Down mode when the CPU2 enters deepsleep

+  * @rmtoll CPU2CR     PDDS_D1       LL_PWR_CPU2_GetD1PowerMode

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_PWR_CPU2_MODE_D1STOP

+  *         @arg @ref LL_PWR_CPU2_MODE_D1STANDBY

+  */

+__STATIC_INLINE uint32_t LL_PWR_CPU2_GetD1PowerMode(void)

+{

+  return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1));

+}

+#endif /* DUAL_CORE */

+

+#if defined (PWR_CPUCR_PDDS_D2)

+/**

+  * @brief  Set the D2 domain Power Down mode when the CPU enters deepsleep

+  * @rmtoll CPUCR     PDDS_D2       LL_PWR_CPU_SetD2PowerMode

+  * @param  PDMode This parameter can be one of the following values:

+  *         @arg @ref LL_PWR_CPU_MODE_D2STOP

+  *         @arg @ref LL_PWR_CPU_MODE_D2STANDBY

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_CPU_SetD2PowerMode(uint32_t PDMode)

+{

+  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D2, PDMode);

+}

+#endif /* PWR_CPUCR_PDDS_D2 */

+

+#if defined (DUAL_CORE)

+/**

+  * @brief  Set the D2 domain Power Down mode when the CPU2 enters deepsleep

+  * @rmtoll CPU2CR     PDDS_D2       LL_PWR_CPU2_SetD2PowerMode

+  * @param  PDMode This parameter can be one of the following values:

+  *         @arg @ref LL_PWR_CPU2_MODE_D2STOP

+  *         @arg @ref LL_PWR_CPU2_MODE_D2STANDBY

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_CPU2_SetD2PowerMode(uint32_t PDMode)

+{

+  MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2, PDMode);

+}

+#endif /* DUAL_CORE */

+

+#if defined (PWR_CPUCR_PDDS_D2)

+/**

+  * @brief  Get the D2 Domain Power Down mode when the CPU enters deepsleep

+  * @rmtoll CPUCR     PDDS_D2       LL_PWR_CPU_GetD2PowerMode

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_PWR_CPU_MODE_D2STOP

+  *         @arg @ref LL_PWR_CPU_MODE_D2STANDBY

+  */

+__STATIC_INLINE uint32_t LL_PWR_CPU_GetD2PowerMode(void)

+{

+  return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2));

+}

+#endif /* PWR_CPUCR_PDDS_D2 */

+

+#if defined (DUAL_CORE)

+/**

+  * @brief  Get the D2 Domain Power Down mode when the CPU2 enters deepsleep

+  * @rmtoll CPU2CR     PDDS_D2       LL_PWR_CPU2_GetD2PowerMode

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_PWR_CPU2_MODE_D2STOP

+  *         @arg @ref LL_PWR_CPU2_MODE_D2STANDBY

+  */

+__STATIC_INLINE uint32_t LL_PWR_CPU2_GetD2PowerMode(void)

+{

+  return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2));

+}

+#endif /* DUAL_CORE */

+

+#if defined (PWR_CPUCR_PDDS_D2)

+/**

+  * @brief  Set the D3 domain Power Down mode when the CPU enters deepsleep

+  * @rmtoll CPUCR     PDDS_D3       LL_PWR_CPU_SetD3PowerMode

+  * @param  PDMode This parameter can be one of the following values:

+  *         @arg @ref LL_PWR_CPU_MODE_D3STOP

+  *         @arg @ref LL_PWR_CPU_MODE_D3STANDBY

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_CPU_SetD3PowerMode(uint32_t PDMode)

+{

+  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D3 , PDMode);

+}

+#else

+/**

+  * @brief  Set the SRD domain Power Down mode when the CPU enters deepsleep

+  * @rmtoll CPUCR     PDDS_SRD       LL_PWR_CPU_SetSRDPowerMode

+  * @param  PDMode This parameter can be one of the following values:

+  *         @arg @ref LL_PWR_CPU_MODE_SRDSTOP

+  *         @arg @ref LL_PWR_CPU_MODE_SRDSTANDBY

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_CPU_SetSRDPowerMode(uint32_t PDMode)

+{

+  MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_SRD , PDMode);

+}

+#endif /* PWR_CPUCR_PDDS_D2 */

+

+#if defined (DUAL_CORE)

+/**

+  * @brief  Set the D3 domain Power Down mode when the CPU2 enters deepsleep

+  * @rmtoll CPU2CR     PDDS_D3       LL_PWR_CPU2_SetD3PowerMode

+  * @param  PDMode This parameter can be one of the following values:

+  *         @arg @ref LL_PWR_CPU2_MODE_D3STOP

+  *         @arg @ref LL_PWR_CPU2_MODE_D3STANDBY

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_CPU2_SetD3PowerMode(uint32_t PDMode)

+{

+  MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3, PDMode);

+}

+#endif /* DUAL_CORE */

+

+#if defined (PWR_CPUCR_PDDS_D3)

+/**

+  * @brief  Get the D3 Domain Power Down mode when the CPU enters deepsleep

+  * @rmtoll CPUCR     PDDS_D3       LL_PWR_CPU_GetD3PowerMode

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_PWR_CPU_MODE_D3STOP

+  *         @arg @ref LL_PWR_CPU_MODE_D3STANDBY

+  */

+__STATIC_INLINE uint32_t LL_PWR_CPU_GetD3PowerMode(void)

+{

+  return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3));

+}

+#else

+/**

+  * @brief  Get the SRD Domain Power Down mode when the CPU enters deepsleep

+  * @rmtoll CPUCR     PDDS_SRD       LL_PWR_CPU_GetSRDPowerMode

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_PWR_CPU_MODE_SRDSTOP

+  *         @arg @ref LL_PWR_CPU_MODE_SRDSTANDBY

+  */

+__STATIC_INLINE uint32_t LL_PWR_CPU_GetSRDPowerMode(void)

+{

+  return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_SRD));

+}

+#endif /* PWR_CPUCR_PDDS_D3 */

+

+#if defined (DUAL_CORE)

+/**

+  * @brief  Get the D3 Domain Power Down mode when the CPU2 enters deepsleep

+  * @rmtoll CPU2CR     PDDS_D3       LL_PWR_CPU2_GetD3PowerMode

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_PWR_CPU2_MODE_D3STOP

+  *         @arg @ref LL_PWR_CPU2_MODE_D3STANDBY

+  */

+__STATIC_INLINE uint32_t LL_PWR_CPU2_GetD3PowerMode(void)

+{

+  return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3));

+}

+#endif /* DUAL_CORE */

+

+#if defined (DUAL_CORE)

+/**

+  * @brief  Hold the CPU1 and allocated peripherals when exiting from STOP mode

+  * @rmtoll CPU2CR     HOLD1       LL_PWR_HoldCPU1

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_HoldCPU1(void)

+{

+  SET_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1);

+}

+

+/**

+  * @brief  Release the CPU1 and allocated peripherals

+  * @rmtoll CPU2CR     HOLD1       LL_PWR_ReleaseCPU1

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_ReleaseCPU1(void)

+{

+  CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1);

+}

+

+/**

+  * @brief  Ckeck if the CPU1 and allocated peripherals are held

+  * @rmtoll CPU2CR     HOLD1       LL_PWR_IsCPU1Held

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsCPU1Held(void)

+{

+  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1) == (PWR_CPU2CR_HOLD1))  ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Hold the CPU2 and allocated peripherals when exiting from STOP mode

+  * @rmtoll CPUCR     HOLD2       LL_PWR_HoldCPU2

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_HoldCPU2(void)

+{

+  SET_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2);

+}

+

+/**

+  * @brief  Release the CPU2 and allocated peripherals

+  * @rmtoll CPUCR     HOLD2       LL_PWR_ReleaseCPU2

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_ReleaseCPU2(void)

+{

+  CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2);

+}

+

+/**

+  * @brief  Ckeck if the CPU2 and allocated peripherals are held

+  * @rmtoll CPUCR     HOLD2       LL_PWR_IsCPU2Held

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsCPU2Held(void)

+{

+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2) == (PWR_CPUCR_HOLD2)) ? 1UL : 0UL);

+}

+#endif /* DUAL_CORE */

+

+#if defined (PWR_CPUCR_PDDS_D2)

+/**

+  * @brief  D3 domain remains in Run mode regardless of CPU subsystem modes

+  * @rmtoll CPUCR     RUN_D3       LL_PWR_CPU_EnableD3RunInLowPowerMode

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_CPU_EnableD3RunInLowPowerMode(void)

+{

+  SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3);

+}

+#else

+/**

+  * @brief  SRD domain remains in Run mode regardless of CPU subsystem modes

+  * @rmtoll CPUCR     RUN_SRD      LL_PWR_CPU_EnableSRDRunInLowPowerMode

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_CPU_EnableSRDRunInLowPowerMode(void)

+{

+  SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD);

+}

+#endif /* PWR_CPUCR_PDDS_D2 */

+

+#if defined (DUAL_CORE)

+/**

+  * @brief  D3 domain remains in Run mode regardless of CPU2 subsystem modes

+  * @rmtoll CPU2CR     RUN_D3       LL_PWR_CPU2_EnableD3RunInLowPowerMode

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_CPU2_EnableD3RunInLowPowerMode(void)

+{

+  SET_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3);

+}

+#endif /* DUAL_CORE */

+

+#if defined (PWR_CPUCR_PDDS_D2)

+/**

+  * @brief  D3 domain follows CPU subsystem modes

+  * @rmtoll CPUCR     RUN_D3       LL_PWR_CPU_DisableD3RunInLowPowerMode

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_CPU_DisableD3RunInLowPowerMode(void)

+{

+  CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3);

+}

+#else

+/**

+  * @brief  SRD domain follows CPU subsystem modes

+  * @rmtoll CPUCR     RUN_SRD      LL_PWR_CPU_DisableSRDRunInLowPowerMode

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_CPU_DisableSRDRunInLowPowerMode(void)

+{

+  CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD);

+}

+#endif /* PWR_CPUCR_PDDS_D2 */

+

+#if defined (DUAL_CORE)

+/**

+  * @brief  D3 domain follows CPU2 subsystem modes

+  * @rmtoll CPU2CR     RUN_D3       LL_PWR_CPU2_DisableD3RunInLowPowerMode

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_CPU2_DisableD3RunInLowPowerMode(void)

+{

+  CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3);

+}

+#endif /* DUAL_CORE */

+

+#if defined (PWR_CPUCR_PDDS_D2)

+/**

+  * @brief  Check if D3 is kept in Run mode when CPU enters low power mode

+  * @rmtoll CPUCR     RUN_D3    LL_PWR_CPU_IsEnabledD3RunInLowPowerMode

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledD3RunInLowPowerMode(void)

+{

+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3) == (PWR_CPUCR_RUN_D3)) ? 1UL : 0UL);

+}

+#else

+/**

+  * @brief  Check if SRD is kept in Run mode when CPU enters low power mode

+  * @rmtoll CPUCR     RUN_SRD    LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode(void)

+{

+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD) == (PWR_CPUCR_RUN_SRD)) ? 1UL : 0UL);

+}

+#endif /* PWR_CPUCR_PDDS_D2 */

+

+#if defined (DUAL_CORE)

+/**

+  * @brief  Check if D3 is kept in Run mode when CPU2 enters low power mode

+  * @rmtoll CPU2CR     RUN_D3    LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode(void)

+{

+  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3) == (PWR_CPU2CR_RUN_D3)) ? 1UL : 0UL);

+}

+#endif /* DUAL_CORE */

+

+/**

+  * @brief  Set the main internal Regulator output voltage

+  * @rmtoll D3CR    VOS       LL_PWR_SetRegulVoltageScaling

+  * @param  VoltageScaling This parameter can be one of the following values:

+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0

+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1

+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2

+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3

+  * @note   For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, VOS0 

+  *         is applied when PWR_D3CR_VOS[1:0] = 0b11 and  SYSCFG_PWRCR_ODEN = 0b1.

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)

+{

+#if defined (PWR_CPUCR_PDDS_D2)

+  MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling);

+#else

+  MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, VoltageScaling);

+#endif /* PWR_CPUCR_PDDS_D2 */

+}

+

+/**

+  * @brief  Get the main internal Regulator output voltage

+  * @rmtoll D3CR    VOS       LL_PWR_GetRegulVoltageScaling

+  * @note   For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, checking 

+  *         VOS0 need the check of PWR_D3CR_VOS[1:0] field and SYSCFG_PWRCR_ODEN bit.

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0

+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1

+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2

+  *         @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3

+  */

+__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)

+{

+#if defined (PWR_CPUCR_PDDS_D2)

+  return (uint32_t)(READ_BIT(PWR->D3CR, PWR_D3CR_VOS));

+#else

+  return (uint32_t)(READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS));

+#endif /* PWR_CPUCR_PDDS_D2 */

+}

+

+/**

+  * @brief  Enable the WakeUp PINx functionality

+  * @rmtoll WKUPEPR   WKUPEN1       LL_PWR_EnableWakeUpPin\n

+  *         WKUPEPR   WKUPEN2       LL_PWR_EnableWakeUpPin\n

+  *         WKUPEPR   WKUPEN3       LL_PWR_EnableWakeUpPin\n

+  *         WKUPEPR   WKUPEN4       LL_PWR_EnableWakeUpPin\n

+  *         WKUPEPR   WKUPEN5       LL_PWR_EnableWakeUpPin\n

+  *         WKUPEPR   WKUPEN6       LL_PWR_EnableWakeUpPin

+  * @param  WakeUpPin This parameter can be one of the following values:

+  *         @arg @ref LL_PWR_WAKEUP_PIN1

+  *         @arg @ref LL_PWR_WAKEUP_PIN2

+  *         @arg @ref LL_PWR_WAKEUP_PIN3

+  *         @arg @ref LL_PWR_WAKEUP_PIN4

+  *         @arg @ref LL_PWR_WAKEUP_PIN5

+  *         @arg @ref LL_PWR_WAKEUP_PIN6

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)

+{

+  SET_BIT(PWR->WKUPEPR, WakeUpPin);

+}

+

+/**

+  * @brief  Disable the WakeUp PINx functionality

+  * @rmtoll WKUPEPR   WKUPEN1       LL_PWR_DisableWakeUpPin\n

+  *         WKUPEPR   WKUPEN2       LL_PWR_DisableWakeUpPin\n

+  *         WKUPEPR   WKUPEN3       LL_PWR_DisableWakeUpPin\n

+  *         WKUPEPR   WKUPEN4       LL_PWR_DisableWakeUpPin\n

+  *         WKUPEPR   WKUPEN5       LL_PWR_DisableWakeUpPin\n

+  *         WKUPEPR   WKUPEN6       LL_PWR_DisableWakeUpPin

+  * @param  WakeUpPin This parameter can be one of the following values:

+  *         @arg @ref LL_PWR_WAKEUP_PIN1

+  *         @arg @ref LL_PWR_WAKEUP_PIN2

+  *         @arg @ref LL_PWR_WAKEUP_PIN3

+  *         @arg @ref LL_PWR_WAKEUP_PIN4

+  *         @arg @ref LL_PWR_WAKEUP_PIN5

+  *         @arg @ref LL_PWR_WAKEUP_PIN6

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)

+{

+  CLEAR_BIT(PWR->WKUPEPR, WakeUpPin);

+}

+

+/**

+  * @brief  Check if the WakeUp PINx functionality is enabled

+  * @rmtoll WKUPEPR   WKUPEN1       LL_PWR_IsEnabledWakeUpPin\n

+  *         WKUPEPR   WKUPEN2       LL_PWR_IsEnabledWakeUpPin\n

+  *         WKUPEPR   WKUPEN3       LL_PWR_IsEnabledWakeUpPin\n

+  *         WKUPEPR   WKUPEN4       LL_PWR_IsEnabledWakeUpPin\n

+  *         WKUPEPR   WKUPEN5       LL_PWR_IsEnabledWakeUpPin\n

+  *         WKUPEPR   WKUPEN6       LL_PWR_IsEnabledWakeUpPin

+  * @param  WakeUpPin This parameter can be one of the following values:

+  *         @arg @ref LL_PWR_WAKEUP_PIN1

+  *         @arg @ref LL_PWR_WAKEUP_PIN2

+  *         @arg @ref LL_PWR_WAKEUP_PIN3

+  *         @arg @ref LL_PWR_WAKEUP_PIN4

+  *         @arg @ref LL_PWR_WAKEUP_PIN5

+  *         @arg @ref LL_PWR_WAKEUP_PIN6

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)

+{

+  return ((READ_BIT(PWR->WKUPEPR, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set the Wake-Up pin polarity low for the event detection

+  * @rmtoll WKUPEPR   WKUPP1       LL_PWR_SetWakeUpPinPolarityLow\n

+  *         WKUPEPR   WKUPP2       LL_PWR_SetWakeUpPinPolarityLow\n

+  *         WKUPEPR   WKUPP3       LL_PWR_SetWakeUpPinPolarityLow\n

+  *         WKUPEPR   WKUPP4       LL_PWR_SetWakeUpPinPolarityLow\n

+  *         WKUPEPR   WKUPP5       LL_PWR_SetWakeUpPinPolarityLow\n

+  *         WKUPEPR   WKUPP6       LL_PWR_SetWakeUpPinPolarityLow

+  * @param  WakeUpPin This parameter can be one of the following values:

+  *         @arg @ref LL_PWR_WAKEUP_PIN1

+  *         @arg @ref LL_PWR_WAKEUP_PIN2

+  *         @arg @ref LL_PWR_WAKEUP_PIN3

+  *         @arg @ref LL_PWR_WAKEUP_PIN4

+  *         @arg @ref LL_PWR_WAKEUP_PIN5

+  *         @arg @ref LL_PWR_WAKEUP_PIN6

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)

+{

+  SET_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos));

+}

+

+/**

+  * @brief  Set the Wake-Up pin polarity high for the event detection

+  * @rmtoll WKUPEPR   WKUPP1       LL_PWR_SetWakeUpPinPolarityHigh\n

+  *         WKUPEPR   WKUPP2       LL_PWR_SetWakeUpPinPolarityHigh\n

+  *         WKUPEPR   WKUPP3       LL_PWR_SetWakeUpPinPolarityHigh\n

+  *         WKUPEPR   WKUPP4       LL_PWR_SetWakeUpPinPolarityHigh\n

+  *         WKUPEPR   WKUPP5       LL_PWR_SetWakeUpPinPolarityHigh\n

+  *         WKUPEPR   WKUPP6       LL_PWR_SetWakeUpPinPolarityHigh

+  * @param  WakeUpPin This parameter can be one of the following values:

+  *         @arg @ref LL_PWR_WAKEUP_PIN1

+  *         @arg @ref LL_PWR_WAKEUP_PIN2

+  *         @arg @ref LL_PWR_WAKEUP_PIN3

+  *         @arg @ref LL_PWR_WAKEUP_PIN4

+  *         @arg @ref LL_PWR_WAKEUP_PIN5

+  *         @arg @ref LL_PWR_WAKEUP_PIN6

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)

+{

+  CLEAR_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos));

+}

+

+/**

+  * @brief  Get the Wake-Up pin polarity for the event detection

+  * @rmtoll WKUPEPR   WKUPP1       LL_PWR_IsWakeUpPinPolarityLow\n

+  *         WKUPEPR   WKUPP2       LL_PWR_IsWakeUpPinPolarityLow\n

+  *         WKUPEPR   WKUPP3       LL_PWR_IsWakeUpPinPolarityLow\n

+  *         WKUPEPR   WKUPP4       LL_PWR_IsWakeUpPinPolarityLow\n

+  *         WKUPEPR   WKUPP5       LL_PWR_IsWakeUpPinPolarityLow\n

+  *         WKUPEPR   WKUPP6       LL_PWR_IsWakeUpPinPolarityLow

+  * @param  WakeUpPin This parameter can be one of the following values:

+  *         @arg @ref LL_PWR_WAKEUP_PIN1

+  *         @arg @ref LL_PWR_WAKEUP_PIN2

+  *         @arg @ref LL_PWR_WAKEUP_PIN3

+  *         @arg @ref LL_PWR_WAKEUP_PIN4

+  *         @arg @ref LL_PWR_WAKEUP_PIN5

+  *         @arg @ref LL_PWR_WAKEUP_PIN6

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)

+{

+  return ((READ_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) == (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set the Wake-Up pin Pull None

+  * @rmtoll WKUPEPR   WKUPPUPD1       LL_PWR_SetWakeUpPinPullNone\n

+  *         WKUPEPR   WKUPPUPD2       LL_PWR_SetWakeUpPinPullNone\n

+  *         WKUPEPR   WKUPPUPD3       LL_PWR_SetWakeUpPinPullNone\n

+  *         WKUPEPR   WKUPPUPD4       LL_PWR_SetWakeUpPinPullNone\n

+  *         WKUPEPR   WKUPPUPD5       LL_PWR_SetWakeUpPinPullNone\n

+  *         WKUPEPR   WKUPPUPD6       LL_PWR_SetWakeUpPinPullNone

+  * @param  WakeUpPin This parameter can be one of the following values:

+  *         @arg @ref LL_PWR_WAKEUP_PIN1

+  *         @arg @ref LL_PWR_WAKEUP_PIN2

+  *         @arg @ref LL_PWR_WAKEUP_PIN3

+  *         @arg @ref LL_PWR_WAKEUP_PIN4

+  *         @arg @ref LL_PWR_WAKEUP_PIN5

+  *         @arg @ref LL_PWR_WAKEUP_PIN6

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin)

+{

+  MODIFY_REG(PWR->WKUPEPR, \

+            (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \

+            (LL_PWR_WAKEUP_PIN_NOPULL << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));

+}

+

+/**

+  * @brief  Set the Wake-Up pin Pull Up

+  * @rmtoll WKUPEPR   WKUPPUPD1       LL_PWR_SetWakeUpPinPullUp\n

+  *         WKUPEPR   WKUPPUPD2       LL_PWR_SetWakeUpPinPullUp\n

+  *         WKUPEPR   WKUPPUPD3       LL_PWR_SetWakeUpPinPullUp\n

+  *         WKUPEPR   WKUPPUPD4       LL_PWR_SetWakeUpPinPullUp\n

+  *         WKUPEPR   WKUPPUPD5       LL_PWR_SetWakeUpPinPullUp\n

+  *         WKUPEPR   WKUPPUPD6       LL_PWR_SetWakeUpPinPullUp

+  * @param  WakeUpPin This parameter can be one of the following values:

+  *         @arg @ref LL_PWR_WAKEUP_PIN1

+  *         @arg @ref LL_PWR_WAKEUP_PIN2

+  *         @arg @ref LL_PWR_WAKEUP_PIN3

+  *         @arg @ref LL_PWR_WAKEUP_PIN4

+  *         @arg @ref LL_PWR_WAKEUP_PIN5

+  *         @arg @ref LL_PWR_WAKEUP_PIN6

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin)

+{

+  MODIFY_REG(PWR->WKUPEPR, \

+            (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \

+            (LL_PWR_WAKEUP_PIN_PULLUP << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));

+}

+

+/**

+  * @brief  Set the Wake-Up pin Pull Down

+  * @rmtoll WKUPEPR   WKUPPUPD1       LL_PWR_SetWakeUpPinPullDown\n

+  *         WKUPEPR   WKUPPUPD2       LL_PWR_SetWakeUpPinPullDown\n

+  *         WKUPEPR   WKUPPUPD3       LL_PWR_SetWakeUpPinPullDown\n

+  *         WKUPEPR   WKUPPUPD4       LL_PWR_SetWakeUpPinPullDown\n

+  *         WKUPEPR   WKUPPUPD5       LL_PWR_SetWakeUpPinPullDown\n

+  *         WKUPEPR   WKUPPUPD6       LL_PWR_SetWakeUpPinPullDown

+  * @param  WakeUpPin This parameter can be one of the following values:

+  *         @arg @ref LL_PWR_WAKEUP_PIN1

+  *         @arg @ref LL_PWR_WAKEUP_PIN2

+  *         @arg @ref LL_PWR_WAKEUP_PIN3

+  *         @arg @ref LL_PWR_WAKEUP_PIN4

+  *         @arg @ref LL_PWR_WAKEUP_PIN5

+  *         @arg @ref LL_PWR_WAKEUP_PIN6

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin)

+{

+  MODIFY_REG(PWR->WKUPEPR, \

+            (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \

+            (LL_PWR_WAKEUP_PIN_PULLDOWN << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));

+}

+

+/**

+  * @brief  Get the Wake-Up pin pull

+  * @rmtoll WKUPEPR   WKUPPUPD1       LL_PWR_GetWakeUpPinPull\n

+  *         WKUPEPR   WKUPPUPD2       LL_PWR_GetWakeUpPinPull\n

+  *         WKUPEPR   WKUPPUPD3       LL_PWR_GetWakeUpPinPull\n

+  *         WKUPEPR   WKUPPUPD4       LL_PWR_GetWakeUpPinPull\n

+  *         WKUPEPR   WKUPPUPD5       LL_PWR_GetWakeUpPinPull\n

+  *         WKUPEPR   WKUPPUPD6       LL_PWR_GetWakeUpPinPull

+  * @param  WakeUpPin This parameter can be one of the following values:

+  *         @arg @ref LL_PWR_WAKEUP_PIN1

+  *         @arg @ref LL_PWR_WAKEUP_PIN2

+  *         @arg @ref LL_PWR_WAKEUP_PIN3

+  *         @arg @ref LL_PWR_WAKEUP_PIN4

+  *         @arg @ref LL_PWR_WAKEUP_PIN5

+  *         @arg @ref LL_PWR_WAKEUP_PIN6

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_PWR_WAKEUP_PIN_NOPULL

+  *         @arg @ref LL_PWR_WAKEUP_PIN_PULLUP

+  *         @arg @ref LL_PWR_WAKEUP_PIN_PULLDOWN

+  */

+__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin)

+{

+  register uint32_t regValue = READ_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));

+

+  return (uint32_t)(regValue >> ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management

+  * @{

+  */

+

+/**

+  * @brief  Indicate whether VDD voltage is below the selected PVD threshold

+  * @rmtoll CSR1   PVDO       LL_PWR_IsActiveFlag_PVDO

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)

+{

+  return ((READ_BIT(PWR->CSR1, PWR_CSR1_PVDO) == (PWR_CSR1_PVDO)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicate whether the voltage level is ready for current actual used VOS

+  * @rmtoll CSR1   ACTVOSRDY       LL_PWR_IsActiveFlag_ACTVOS

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS(void)

+{

+  return ((READ_BIT(PWR->CSR1, PWR_CSR1_ACTVOSRDY) == (PWR_CSR1_ACTVOSRDY)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicate whether VDDA voltage is below the selected AVD threshold

+  * @rmtoll CSR1   AVDO       LL_PWR_IsActiveFlag_AVDO

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_AVDO(void)

+{

+  return ((READ_BIT(PWR->CSR1, PWR_CSR1_AVDO) == (PWR_CSR1_AVDO)) ? 1UL : 0UL);

+}

+

+#if defined (PWR_CSR1_MMCVDO)

+/**

+  * @brief  Indicate whether VDDMMC voltage is below 1V2

+  * @rmtoll CSR1   MMCVDO     LL_PWR_IsActiveFlag_MMCVDO

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_MMCVDO(void)

+{

+  return ((READ_BIT(PWR->CSR1, PWR_CSR1_MMCVDO) == (PWR_CSR1_MMCVDO)) ? 1UL : 0UL);

+}

+#endif /* PWR_CSR1_MMCVDO */

+

+/**

+  * @brief  Get Backup Regulator ready Flag

+  * @rmtoll CR2   BRRDY       LL_PWR_IsActiveFlag_BRR

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)

+{

+  return ((READ_BIT(PWR->CR2, PWR_CR2_BRRDY) == (PWR_CR2_BRRDY)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicate whether the VBAT level is above or below low threshold

+  * @rmtoll CR2   VBATL       LL_PWR_IsActiveFlag_VBATL

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATL(void)

+{

+  return ((READ_BIT(PWR->CR2, PWR_CR2_VBATL) == (PWR_CR2_VBATL)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicate whether the VBAT level is above or below high threshold

+  * @rmtoll CR2   VBATH       LL_PWR_IsActiveFlag_VBATH

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void)

+{

+  return ((READ_BIT(PWR->CR2, PWR_CR2_VBATH) == (PWR_CR2_VBATH)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicate whether the CPU temperature level is above or below low threshold

+  * @rmtoll CR2   TEMPL       LL_PWR_IsActiveFlag_TEMPL

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void)

+{

+  return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPL) == (PWR_CR2_TEMPL)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicate whether the CPU temperature level is above or below high threshold

+  * @rmtoll CR2   TEMPH       LL_PWR_IsActiveFlag_TEMPH

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void)

+{

+  return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPH) == (PWR_CR2_TEMPH)) ? 1UL : 0UL);

+}

+

+#if defined (SMPS)

+/**

+  * @brief  Indicate whether the SMPS external supply is ready or not

+  * @rmtoll CR3   SMPSEXTRDY       LL_PWR_IsActiveFlag_SMPSEXT

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SMPSEXT(void)

+{

+  return ((READ_BIT(PWR->CR3, PWR_CR3_SMPSEXTRDY) == (PWR_CR3_SMPSEXTRDY)) ? 1UL : 0UL);

+}

+#endif /* SMPS */

+

+/**

+  * @brief  Indicate whether the USB supply is ready or not

+  * @rmtoll CR3   USBRDY       LL_PWR_IsActiveFlag_USB

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_USB(void)

+{

+  return ((READ_BIT(PWR->CR3, PWR_CR3_USB33RDY) == (PWR_CR3_USB33RDY)) ? 1UL : 0UL);

+}

+

+#if defined (DUAL_CORE)

+/**

+  * @brief  Get HOLD2 Flag

+  * @rmtoll CPUCR   HOLD2F       LL_PWR_IsActiveFlag_HOLD2

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_HOLD2(void)

+{

+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2F) == (PWR_CPUCR_HOLD2F)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get HOLD1 Flag

+  * @rmtoll CPU2CR   HOLD1F       LL_PWR_IsActiveFlag_HOLD1

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_HOLD1(void)

+{

+  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1F) == (PWR_CPU2CR_HOLD1F)) ? 1UL : 0UL);

+}

+#endif /* DUAL_CORE */

+

+/**

+  * @brief  Get CPU System Stop Flag

+  * @rmtoll CPUCR   STOPF       LL_PWR_CPU_IsActiveFlag_STOP

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_STOP(void)

+{

+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_STOPF) == (PWR_CPUCR_STOPF)) ? 1UL : 0UL);

+}

+

+#if defined (DUAL_CORE)

+/**

+  * @brief  Get CPU2 System Stop Flag

+  * @rmtoll CPU2CR   STOPF       LL_PWR_CPU2_IsActiveFlag_STOP

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_STOP(void)

+{

+  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_STOPF) == (PWR_CPU2CR_STOPF)) ? 1UL : 0UL);

+}

+#endif /* DUAL_CORE */

+

+/**

+  * @brief  Get CPU System Standby Flag

+  * @rmtoll CPUCR   SBF       LL_PWR_CPU_IsActiveFlag_SB

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB(void)

+{

+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF) == (PWR_CPUCR_SBF)) ? 1UL : 0UL);

+}

+

+#if defined (DUAL_CORE)

+/**

+  * @brief  Get CPU2 System Standby Flag

+  * @rmtoll CPU2CR   SBF       LL_PWR_CPU2_IsActiveFlag_SB

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB(void)

+{

+  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF) == (PWR_CPU2CR_SBF)) ? 1UL : 0UL);

+}

+#endif /* DUAL_CORE */

+

+#if defined (PWR_CPUCR_SBF_D1)

+/**

+  * @brief  Get CPU D1 Domain Standby Flag

+  * @rmtoll CPUCR   SBF_D1       LL_PWR_CPU_IsActiveFlag_SB_D1

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D1(void)

+{

+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D1) == (PWR_CPUCR_SBF_D1)) ? 1UL : 0UL);

+}

+#endif /* PWR_CPUCR_SBF_D1 */

+

+#if defined (DUAL_CORE)

+/**

+  * @brief  Get CPU2 D1 Domain Standby Flag

+  * @rmtoll CPU2CR   SBF_D1       LL_PWR_CPU2_IsActiveFlag_SB_D1

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB_D1(void)

+{

+  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D1) == (PWR_CPU2CR_SBF_D1)) ? 1UL : 0UL);

+}

+#endif /* DUAL_CORE */

+

+#if defined (PWR_CPUCR_SBF_D2)

+/**

+  * @brief  Get CPU D2 Domain Standby Flag

+  * @rmtoll CPUCR   SBF_D2       LL_PWR_CPU_IsActiveFlag_SB_D2

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D2(void)

+{

+  return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D2) == (PWR_CPUCR_SBF_D2)) ? 1UL : 0UL);

+}

+#endif /* PWR_CPUCR_SBF_D2 */

+

+#if defined (DUAL_CORE)

+/**

+  * @brief  Get CPU2 D2 Domain Standby Flag

+  * @rmtoll CPU2CR   SBF_D2       LL_PWR_CPU2_IsActiveFlag_SB_D2

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB_D2(void)

+{

+  return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D2) == (PWR_CPU2CR_SBF_D2)) ? 1UL : 0UL);

+}

+#endif /* DUAL_CORE */

+

+

+/**

+  * @brief  Indicate whether the Regulator is ready in the selected voltage range

+  *         or if its output voltage is still changing to the required voltage level

+  * @rmtoll D3CR   VOSRDY       LL_PWR_IsActiveFlag_VOS

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)

+{

+#if defined (PWR_CPUCR_PDDS_D2)

+  return ((READ_BIT(PWR->D3CR, PWR_D3CR_VOSRDY) == (PWR_D3CR_VOSRDY)) ? 1UL : 0UL);

+#else

+  return ((READ_BIT(PWR->SRDCR, PWR_SRDCR_VOSRDY) == (PWR_SRDCR_VOSRDY)) ? 1UL : 0UL);

+#endif /* PWR_CPUCR_PDDS_D2 */

+}

+

+/**

+  * @brief  Get Wake-up Flag 6

+  * @rmtoll WKUPFR          WKUPF6          LL_PWR_IsActiveFlag_WU6

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)

+{

+  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF6) == (PWR_WKUPFR_WKUPF6)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Wake-up Flag 5

+  * @rmtoll WKUPFR          WKUPF5          LL_PWR_IsActiveFlag_WU5

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)

+{

+  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF5) == (PWR_WKUPFR_WKUPF5)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Wake-up Flag 4

+  * @rmtoll WKUPFR          WKUPF4          LL_PWR_IsActiveFlag_WU4

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)

+{

+  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF4) == (PWR_WKUPFR_WKUPF4)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Wake-up Flag 3

+  * @rmtoll WKUPFR          WKUPF3          LL_PWR_IsActiveFlag_WU3

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)

+{

+  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF3) == (PWR_WKUPFR_WKUPF3)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Wake-up Flag 2

+  * @rmtoll WKUPFR          WKUPF2          LL_PWR_IsActiveFlag_WU2

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)

+{

+  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF2) == (PWR_WKUPFR_WKUPF2)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Wake-up Flag 1

+  * @rmtoll WKUPFR          WKUPF1          LL_PWR_IsActiveFlag_WU1

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)

+{

+  return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) == (PWR_WKUPFR_WKUPF1)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear CPU STANDBY, STOP and HOLD flags

+  * @rmtoll CPUCR   CSSF       LL_PWR_ClearFlag_CPU

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_ClearFlag_CPU(void)

+{

+  SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF);

+}

+

+#if defined (DUAL_CORE)

+/**

+  * @brief  Clear CPU2 STANDBY, STOP and HOLD flags

+  * @rmtoll CPU2CR   CSSF       LL_PWR_ClearFlag_CPU2

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_ClearFlag_CPU2(void)

+{

+  SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF);

+}

+#endif /* DUAL_CORE */

+

+/**

+  * @brief  Clear Wake-up Flag 6

+  * @rmtoll WKUPCR          WKUPC6         LL_PWR_ClearFlag_WU6

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)

+{

+  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC6);

+}

+

+/**

+  * @brief  Clear Wake-up Flag 5

+  * @rmtoll WKUPCR          WKUPC5         LL_PWR_ClearFlag_WU5

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)

+{

+  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC5);

+}

+

+/**

+  * @brief  Clear Wake-up Flag 4

+  * @rmtoll WKUPCR          WKUPC4         LL_PWR_ClearFlag_WU4

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)

+{

+  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC4);

+}

+

+/**

+  * @brief  Clear Wake-up Flag 3

+  * @rmtoll WKUPCR          WKUPC3         LL_PWR_ClearFlag_WU3

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)

+{

+  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC3);

+}

+

+/**

+  * @brief  Clear Wake-up Flag 2

+  * @rmtoll WKUPCR          WKUPC2         LL_PWR_ClearFlag_WU2

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)

+{

+  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC2);

+}

+

+/**

+  * @brief  Clear Wake-up Flag 1

+  * @rmtoll WKUPCR          WKUPC1         LL_PWR_ClearFlag_WU1

+  * @retval None

+  */

+__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)

+{

+  WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC1);

+}

+

+#if defined (USE_FULL_LL_DRIVER)

+/** @defgroup PWR_LL_EF_Init De-initialization function

+  * @{

+  */

+ErrorStatus LL_PWR_DeInit(void);

+/**

+  * @}

+  */

+#endif /* defined (USE_FULL_LL_DRIVER) */

+

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* defined (PWR) */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_LL_PWR_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_rcc.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_rcc.h
new file mode 100644
index 0000000000..2fdd1d02ee
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_rcc.h
@@ -0,0 +1,6326 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_rcc.h

+  * @author  MCD Application Team

+  * @version $VERSION$

+  * @date    $DATE$

+  * @brief   Header file of RCC LL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_LL_RCC_H

+#define STM32H7xx_LL_RCC_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+#include <math.h>

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+#if defined(RCC)

+

+/** @defgroup RCC_LL RCC

+  * @{

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/** @defgroup RCC_LL_Private_Variables RCC Private Variables

+  * @{

+  */

+extern const uint8_t LL_RCC_PrescTable[16];

+

+/**

+  * @}

+  */

+/* Private constants ---------------------------------------------------------*/

+/* Private macros ------------------------------------------------------------*/

+#if !defined(UNUSED)

+#define UNUSED(x) ((void)(x))

+#endif

+

+/* 32            24           16            8             0

+   --------------------------------------------------------

+   | Mask        | ClkSource   |  Bit       | Register    |

+   |             |  Config     | Position   | Offset      |

+   --------------------------------------------------------*/

+

+#if defined(RCC_VER_2_0)

+/* Clock source register offset Vs CDCCIPR regsiter */

+#define CDCCIP    0x0UL

+#define CDCCIP1   0x4UL

+#define CDCCIP2   0x8UL

+#define SRDCCIP   0xCUL

+#else

+/* Clock source register offset Vs D1CCIPR regsiter */

+#define D1CCIP    0x0UL

+#define D2CCIP1   0x4UL

+#define D2CCIP2   0x8UL

+#define D3CCIP    0xCUL

+#endif /* RCC_VER_2_0 */

+

+#define LL_RCC_REG_SHIFT     0U

+#define LL_RCC_POS_SHIFT     8U

+#define LL_RCC_CONFIG_SHIFT  16U

+#define LL_RCC_MASK_SHIFT    24U

+

+#define LL_CLKSOURCE_SHIFT(__CLKSOURCE__)   (((__CLKSOURCE__) >> LL_RCC_POS_SHIFT   ) & 0x1FUL)

+

+#define LL_CLKSOURCE_MASK(__CLKSOURCE__)   ((((__CLKSOURCE__) >> LL_RCC_MASK_SHIFT  ) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))

+

+#define LL_CLKSOURCE_CONFIG(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_CONFIG_SHIFT) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))

+

+#define LL_CLKSOURCE_REG(__CLKSOURCE__)     (((__CLKSOURCE__) >> LL_RCC_REG_SHIFT   ) & 0xFFUL)

+

+#define LL_CLKSOURCE(__REG__, __MSK__, __POS__, __CLK__) ((uint32_t)((((__MSK__) >> (__POS__)) << LL_RCC_MASK_SHIFT) | \

+                                                                     (( __POS__              ) << LL_RCC_POS_SHIFT)  | \

+                                                                     (( __REG__              ) << LL_RCC_REG_SHIFT)  | \

+                                                                     (((__CLK__) >> (__POS__)) << LL_RCC_CONFIG_SHIFT)))

+

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup RCC_LL_Private_Macros RCC Private Macros

+  * @{

+  */

+/**

+  * @}

+  */

+#endif /*USE_FULL_LL_DRIVER*/

+/* Exported types ------------------------------------------------------------*/

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup RCC_LL_Exported_Types RCC Exported Types

+  * @{

+  */

+

+/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure

+  * @{

+  */

+

+/**

+  * @brief  RCC Clocks Frequency Structure

+  */

+typedef struct

+{

+  uint32_t SYSCLK_Frequency;

+  uint32_t CPUCLK_Frequency;

+  uint32_t HCLK_Frequency;

+  uint32_t PCLK1_Frequency;

+  uint32_t PCLK2_Frequency;

+  uint32_t PCLK3_Frequency;

+  uint32_t PCLK4_Frequency;

+} LL_RCC_ClocksTypeDef;

+

+/**

+  * @}

+  */

+

+/**

+  * @brief  PLL Clocks Frequency Structure

+  */

+typedef struct

+{

+  uint32_t PLL_P_Frequency;

+  uint32_t PLL_Q_Frequency;

+  uint32_t PLL_R_Frequency;

+} LL_PLL_ClocksTypeDef;

+

+/**

+  * @}

+  */

+

+#endif /* USE_FULL_LL_DRIVER */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants

+  * @{

+  */

+

+/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation

+  * @brief    Defines used to adapt values of different oscillators

+  * @note     These values could be modified in the user environment according to

+  *           HW set-up.

+  * @{

+  */

+#if !defined  (HSE_VALUE)

+#if defined(RCC_VER_X)

+#define HSE_VALUE    25000000U  /*!< Value of the HSE oscillator in Hz */

+#else

+#define HSE_VALUE    24000000U  /*!< Value of the HSE oscillator in Hz */

+#endif /* RCC_VER_X */

+#endif /* HSE_VALUE */

+

+#if !defined  (HSI_VALUE)

+#define HSI_VALUE    64000000U  /*!< Value of the HSI oscillator in Hz */

+#endif /* HSI_VALUE */

+

+#if !defined  (CSI_VALUE)

+#define CSI_VALUE    4000000U   /*!< Value of the CSI oscillator in Hz */

+#endif /* CSI_VALUE */

+

+#if !defined  (LSE_VALUE)

+#define LSE_VALUE    32768U     /*!< Value of the LSE oscillator in Hz */

+#endif /* LSE_VALUE */

+

+#if !defined  (LSI_VALUE)

+#define LSI_VALUE    32000U     /*!< Value of the LSI oscillator in Hz */

+#endif /* LSI_VALUE */

+

+#if !defined  (EXTERNAL_CLOCK_VALUE)

+#define EXTERNAL_CLOCK_VALUE    12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */

+#endif /* EXTERNAL_CLOCK_VALUE */

+

+#if !defined  (HSI48_VALUE)

+#define HSI48_VALUE  48000000U  /*!< Value of the HSI48 oscillator in Hz */

+#endif /* HSI48_VALUE */

+

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_HSIDIV  HSI oscillator divider

+  * @{

+  */

+#define LL_RCC_HSI_DIV1                   RCC_CR_HSIDIV_1

+#define LL_RCC_HSI_DIV2                   RCC_CR_HSIDIV_2

+#define LL_RCC_HSI_DIV4                   RCC_CR_HSIDIV_4

+#define LL_RCC_HSI_DIV8                   RCC_CR_HSIDIV_8

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_LSEDRIVE  LSE oscillator drive capability

+  * @{

+  */

+#define LL_RCC_LSEDRIVE_LOW                (uint32_t)(0x00000000U)

+#define LL_RCC_LSEDRIVE_MEDIUMLOW          (uint32_t)(RCC_BDCR_LSEDRV_0)

+#define LL_RCC_LSEDRIVE_MEDIUMHIGH         (uint32_t)(RCC_BDCR_LSEDRV_1)

+#define LL_RCC_LSEDRIVE_HIGH               (uint32_t)(RCC_BDCR_LSEDRV)

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE  System clock switch

+  * @{

+  */

+#define LL_RCC_SYS_CLKSOURCE_HSI           RCC_CFGR_SW_HSI

+#define LL_RCC_SYS_CLKSOURCE_CSI           RCC_CFGR_SW_CSI

+#define LL_RCC_SYS_CLKSOURCE_HSE           RCC_CFGR_SW_HSE

+#define LL_RCC_SYS_CLKSOURCE_PLL1          RCC_CFGR_SW_PLL1

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS  System clock switch status

+  * @{

+  */

+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI    RCC_CFGR_SWS_HSI   /*!< HSI used as system clock */

+#define LL_RCC_SYS_CLKSOURCE_STATUS_CSI    RCC_CFGR_SWS_CSI   /*!< CSI used as system clock */

+#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE    RCC_CFGR_SWS_HSE   /*!< HSE used as system clock */

+#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1   RCC_CFGR_SWS_PLL1  /*!< PLL1 used as system clock */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_SYSWAKEUP_CLKSOURCE  System wakeup clock source

+  * @{

+  */

+#define LL_RCC_SYSWAKEUP_CLKSOURCE_HSI     (uint32_t)(0x00000000U)

+#define LL_RCC_SYSWAKEUP_CLKSOURCE_CSI     (uint32_t)(RCC_CFGR_STOPWUCK)

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_KERWAKEUP_CLKSOURCE  Kernel wakeup clock source

+  * @{

+  */

+#define LL_RCC_KERWAKEUP_CLKSOURCE_HSI     (uint32_t)(0x00000000U)

+#define LL_RCC_KERWAKEUP_CLKSOURCE_CSI     (uint32_t)(RCC_CFGR_STOPKERWUCK)

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_SYSCLK_DIV  System prescaler

+  * @{

+  */

+#if defined(RCC_D1CFGR_D1CPRE_DIV1)

+#define LL_RCC_SYSCLK_DIV_1                RCC_D1CFGR_D1CPRE_DIV1

+#define LL_RCC_SYSCLK_DIV_2                RCC_D1CFGR_D1CPRE_DIV2

+#define LL_RCC_SYSCLK_DIV_4                RCC_D1CFGR_D1CPRE_DIV4

+#define LL_RCC_SYSCLK_DIV_8                RCC_D1CFGR_D1CPRE_DIV8

+#define LL_RCC_SYSCLK_DIV_16               RCC_D1CFGR_D1CPRE_DIV16

+#define LL_RCC_SYSCLK_DIV_64               RCC_D1CFGR_D1CPRE_DIV64

+#define LL_RCC_SYSCLK_DIV_128              RCC_D1CFGR_D1CPRE_DIV128

+#define LL_RCC_SYSCLK_DIV_256              RCC_D1CFGR_D1CPRE_DIV256

+#define LL_RCC_SYSCLK_DIV_512              RCC_D1CFGR_D1CPRE_DIV512

+#else

+#define LL_RCC_SYSCLK_DIV_1                RCC_CDCFGR1_CDCPRE_DIV1

+#define LL_RCC_SYSCLK_DIV_2                RCC_CDCFGR1_CDCPRE_DIV2

+#define LL_RCC_SYSCLK_DIV_4                RCC_CDCFGR1_CDCPRE_DIV4

+#define LL_RCC_SYSCLK_DIV_8                RCC_CDCFGR1_CDCPRE_DIV8

+#define LL_RCC_SYSCLK_DIV_16               RCC_CDCFGR1_CDCPRE_DIV16

+#define LL_RCC_SYSCLK_DIV_64               RCC_CDCFGR1_CDCPRE_DIV64

+#define LL_RCC_SYSCLK_DIV_128              RCC_CDCFGR1_CDCPRE_DIV128

+#define LL_RCC_SYSCLK_DIV_256              RCC_CDCFGR1_CDCPRE_DIV256

+#define LL_RCC_SYSCLK_DIV_512              RCC_CDCFGR1_CDCPRE_DIV512

+#endif /* RCC_D1CFGR_D1CPRE_DIV1 */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_AHB_DIV  AHB prescaler

+  * @{

+  */

+#if defined(RCC_D1CFGR_HPRE_DIV1)

+#define LL_RCC_AHB_DIV_1                   RCC_D1CFGR_HPRE_DIV1

+#define LL_RCC_AHB_DIV_2                   RCC_D1CFGR_HPRE_DIV2

+#define LL_RCC_AHB_DIV_4                   RCC_D1CFGR_HPRE_DIV4

+#define LL_RCC_AHB_DIV_8                   RCC_D1CFGR_HPRE_DIV8

+#define LL_RCC_AHB_DIV_16                  RCC_D1CFGR_HPRE_DIV16

+#define LL_RCC_AHB_DIV_64                  RCC_D1CFGR_HPRE_DIV64

+#define LL_RCC_AHB_DIV_128                 RCC_D1CFGR_HPRE_DIV128

+#define LL_RCC_AHB_DIV_256                 RCC_D1CFGR_HPRE_DIV256

+#define LL_RCC_AHB_DIV_512                 RCC_D1CFGR_HPRE_DIV512

+#else

+#define LL_RCC_AHB_DIV_1                   RCC_CDCFGR1_HPRE_DIV1

+#define LL_RCC_AHB_DIV_2                   RCC_CDCFGR1_HPRE_DIV2

+#define LL_RCC_AHB_DIV_4                   RCC_CDCFGR1_HPRE_DIV4

+#define LL_RCC_AHB_DIV_8                   RCC_CDCFGR1_HPRE_DIV8

+#define LL_RCC_AHB_DIV_16                  RCC_CDCFGR1_HPRE_DIV16

+#define LL_RCC_AHB_DIV_64                  RCC_CDCFGR1_HPRE_DIV64

+#define LL_RCC_AHB_DIV_128                 RCC_CDCFGR1_HPRE_DIV128

+#define LL_RCC_AHB_DIV_256                 RCC_CDCFGR1_HPRE_DIV256

+#define LL_RCC_AHB_DIV_512                 RCC_CDCFGR1_HPRE_DIV512

+#endif /* RCC_D1CFGR_HPRE_DIV1 */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_APB1_DIV  APB low-speed prescaler (APB1)

+  * @{

+  */

+#if defined(RCC_D2CFGR_D2PPRE1_DIV1)

+#define LL_RCC_APB1_DIV_1                  RCC_D2CFGR_D2PPRE1_DIV1

+#define LL_RCC_APB1_DIV_2                  RCC_D2CFGR_D2PPRE1_DIV2

+#define LL_RCC_APB1_DIV_4                  RCC_D2CFGR_D2PPRE1_DIV4

+#define LL_RCC_APB1_DIV_8                  RCC_D2CFGR_D2PPRE1_DIV8

+#define LL_RCC_APB1_DIV_16                 RCC_D2CFGR_D2PPRE1_DIV16

+#else

+#define LL_RCC_APB1_DIV_1                  RCC_CDCFGR2_CDPPRE1_DIV1

+#define LL_RCC_APB1_DIV_2                  RCC_CDCFGR2_CDPPRE1_DIV2

+#define LL_RCC_APB1_DIV_4                  RCC_CDCFGR2_CDPPRE1_DIV4

+#define LL_RCC_APB1_DIV_8                  RCC_CDCFGR2_CDPPRE1_DIV8

+#define LL_RCC_APB1_DIV_16                 RCC_CDCFGR2_CDPPRE1_DIV16

+#endif /* RCC_D2CFGR_D2PPRE1_DIV1 */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_APB2_DIV  APB low-speed prescaler (APB2)

+  * @{

+  */

+#if defined(RCC_D2CFGR_D2PPRE2_DIV1)

+#define LL_RCC_APB2_DIV_1                  RCC_D2CFGR_D2PPRE2_DIV1

+#define LL_RCC_APB2_DIV_2                  RCC_D2CFGR_D2PPRE2_DIV2

+#define LL_RCC_APB2_DIV_4                  RCC_D2CFGR_D2PPRE2_DIV4

+#define LL_RCC_APB2_DIV_8                  RCC_D2CFGR_D2PPRE2_DIV8

+#define LL_RCC_APB2_DIV_16                 RCC_D2CFGR_D2PPRE2_DIV16

+#else

+#define LL_RCC_APB2_DIV_1                  RCC_CDCFGR2_CDPPRE2_DIV1

+#define LL_RCC_APB2_DIV_2                  RCC_CDCFGR2_CDPPRE2_DIV2

+#define LL_RCC_APB2_DIV_4                  RCC_CDCFGR2_CDPPRE2_DIV4

+#define LL_RCC_APB2_DIV_8                  RCC_CDCFGR2_CDPPRE2_DIV8

+#define LL_RCC_APB2_DIV_16                 RCC_CDCFGR2_CDPPRE2_DIV16

+#endif /* RCC_D2CFGR_D2PPRE2_DIV1 */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_APB3_DIV  APB low-speed prescaler (APB3)

+  * @{

+  */

+#if defined(RCC_D1CFGR_D1PPRE_DIV1)

+#define LL_RCC_APB3_DIV_1                  RCC_D1CFGR_D1PPRE_DIV1

+#define LL_RCC_APB3_DIV_2                  RCC_D1CFGR_D1PPRE_DIV2

+#define LL_RCC_APB3_DIV_4                  RCC_D1CFGR_D1PPRE_DIV4

+#define LL_RCC_APB3_DIV_8                  RCC_D1CFGR_D1PPRE_DIV8

+#define LL_RCC_APB3_DIV_16                 RCC_D1CFGR_D1PPRE_DIV16

+#else

+#define LL_RCC_APB3_DIV_1                  RCC_CDCFGR1_CDPPRE_DIV1

+#define LL_RCC_APB3_DIV_2                  RCC_CDCFGR1_CDPPRE_DIV2

+#define LL_RCC_APB3_DIV_4                  RCC_CDCFGR1_CDPPRE_DIV4

+#define LL_RCC_APB3_DIV_8                  RCC_CDCFGR1_CDPPRE_DIV8

+#define LL_RCC_APB3_DIV_16                 RCC_CDCFGR1_CDPPRE_DIV16

+#endif /* RCC_D1CFGR_D1PPRE_DIV1 */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_APB4_DIV  APB low-speed prescaler (APB4)

+  * @{

+  */

+#if defined(RCC_D3CFGR_D3PPRE_DIV1)

+#define LL_RCC_APB4_DIV_1                  RCC_D3CFGR_D3PPRE_DIV1

+#define LL_RCC_APB4_DIV_2                  RCC_D3CFGR_D3PPRE_DIV2

+#define LL_RCC_APB4_DIV_4                  RCC_D3CFGR_D3PPRE_DIV4

+#define LL_RCC_APB4_DIV_8                  RCC_D3CFGR_D3PPRE_DIV8

+#define LL_RCC_APB4_DIV_16                 RCC_D3CFGR_D3PPRE_DIV16

+#else

+#define LL_RCC_APB4_DIV_1                  RCC_SRDCFGR_SRDPPRE_DIV1

+#define LL_RCC_APB4_DIV_2                  RCC_SRDCFGR_SRDPPRE_DIV2

+#define LL_RCC_APB4_DIV_4                  RCC_SRDCFGR_SRDPPRE_DIV4

+#define LL_RCC_APB4_DIV_8                  RCC_SRDCFGR_SRDPPRE_DIV8

+#define LL_RCC_APB4_DIV_16                 RCC_SRDCFGR_SRDPPRE_DIV16

+#endif /* RCC_D3CFGR_D3PPRE_DIV1 */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_MCOxSOURCE  MCO source selection

+  * @{

+  */

+#define LL_RCC_MCO1SOURCE_HSI              (uint32_t)((RCC_CFGR_MCO1>>16U) | 0x00000000U)

+#define LL_RCC_MCO1SOURCE_LSE              (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_0)

+#define LL_RCC_MCO1SOURCE_HSE              (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1)

+#define LL_RCC_MCO1SOURCE_PLL1QCLK         (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0)

+#define LL_RCC_MCO1SOURCE_HSI48            (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_2)

+#define LL_RCC_MCO2SOURCE_SYSCLK           (uint32_t)((RCC_CFGR_MCO2>>16U) | 0x00000000U)

+#define LL_RCC_MCO2SOURCE_PLL2PCLK         (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_0)

+#define LL_RCC_MCO2SOURCE_HSE              (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1)

+#define LL_RCC_MCO2SOURCE_PLL1PCLK         (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0)

+#define LL_RCC_MCO2SOURCE_CSI              (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2)

+#define LL_RCC_MCO2SOURCE_LSI              (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2|RCC_CFGR_MCO2_0)

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_MCOx_DIV  MCO prescaler

+  * @{

+  */

+#define LL_RCC_MCO1_DIV_1                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0)

+#define LL_RCC_MCO1_DIV_2                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1)

+#define LL_RCC_MCO1_DIV_3                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)

+#define LL_RCC_MCO1_DIV_4                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2)

+#define LL_RCC_MCO1_DIV_5                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)

+#define LL_RCC_MCO1_DIV_6                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)

+#define LL_RCC_MCO1_DIV_7                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)

+#define LL_RCC_MCO1_DIV_8                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_3)

+#define LL_RCC_MCO1_DIV_9                  (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)

+#define LL_RCC_MCO1_DIV_10                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)

+#define LL_RCC_MCO1_DIV_11                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)

+#define LL_RCC_MCO1_DIV_12                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)

+#define LL_RCC_MCO1_DIV_13                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)

+#define LL_RCC_MCO1_DIV_14                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)

+#define LL_RCC_MCO1_DIV_15                 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE)

+#define LL_RCC_MCO2_DIV_1                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0)

+#define LL_RCC_MCO2_DIV_2                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1)

+#define LL_RCC_MCO2_DIV_3                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1)

+#define LL_RCC_MCO2_DIV_4                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2)

+#define LL_RCC_MCO2_DIV_5                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2)

+#define LL_RCC_MCO2_DIV_6                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)

+#define LL_RCC_MCO2_DIV_7                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)

+#define LL_RCC_MCO2_DIV_8                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_3)

+#define LL_RCC_MCO2_DIV_9                  (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_3)

+#define LL_RCC_MCO2_DIV_10                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3)

+#define LL_RCC_MCO2_DIV_11                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3)

+#define LL_RCC_MCO2_DIV_12                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)

+#define LL_RCC_MCO2_DIV_13                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)

+#define LL_RCC_MCO2_DIV_14                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)

+#define LL_RCC_MCO2_DIV_15                 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE)

+

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_RTC_HSEDIV  HSE prescaler for RTC clock

+  * @{

+  */

+#define LL_RCC_RTC_NOCLOCK                  (uint32_t)(0x00000000U)

+#define LL_RCC_RTC_HSE_DIV_2                (uint32_t)(RCC_CFGR_RTCPRE_1)

+#define LL_RCC_RTC_HSE_DIV_3                (uint32_t)(RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

+#define LL_RCC_RTC_HSE_DIV_4                (uint32_t)(RCC_CFGR_RTCPRE_2)

+#define LL_RCC_RTC_HSE_DIV_5                (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)

+#define LL_RCC_RTC_HSE_DIV_6                (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)

+#define LL_RCC_RTC_HSE_DIV_7                (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

+#define LL_RCC_RTC_HSE_DIV_8                (uint32_t)(RCC_CFGR_RTCPRE_3)

+#define LL_RCC_RTC_HSE_DIV_9                (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)

+#define LL_RCC_RTC_HSE_DIV_10               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)

+#define LL_RCC_RTC_HSE_DIV_11               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

+#define LL_RCC_RTC_HSE_DIV_12               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)

+#define LL_RCC_RTC_HSE_DIV_13               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)

+#define LL_RCC_RTC_HSE_DIV_14               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)

+#define LL_RCC_RTC_HSE_DIV_15               (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

+#define LL_RCC_RTC_HSE_DIV_16               (uint32_t)(RCC_CFGR_RTCPRE_4)

+#define LL_RCC_RTC_HSE_DIV_17               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)

+#define LL_RCC_RTC_HSE_DIV_18               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)

+#define LL_RCC_RTC_HSE_DIV_19               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

+#define LL_RCC_RTC_HSE_DIV_20               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)

+#define LL_RCC_RTC_HSE_DIV_21               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)

+#define LL_RCC_RTC_HSE_DIV_22               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)

+#define LL_RCC_RTC_HSE_DIV_23               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

+#define LL_RCC_RTC_HSE_DIV_24               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)

+#define LL_RCC_RTC_HSE_DIV_25               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)

+#define LL_RCC_RTC_HSE_DIV_26               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)

+#define LL_RCC_RTC_HSE_DIV_27               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

+#define LL_RCC_RTC_HSE_DIV_28               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)

+#define LL_RCC_RTC_HSE_DIV_29               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)

+#define LL_RCC_RTC_HSE_DIV_30               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)

+#define LL_RCC_RTC_HSE_DIV_31               (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

+#define LL_RCC_RTC_HSE_DIV_32               (uint32_t)(RCC_CFGR_RTCPRE_5)

+#define LL_RCC_RTC_HSE_DIV_33               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_0)

+#define LL_RCC_RTC_HSE_DIV_34               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1)

+#define LL_RCC_RTC_HSE_DIV_35               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

+#define LL_RCC_RTC_HSE_DIV_36               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2)

+#define LL_RCC_RTC_HSE_DIV_37               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)

+#define LL_RCC_RTC_HSE_DIV_38               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)

+#define LL_RCC_RTC_HSE_DIV_39               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

+#define LL_RCC_RTC_HSE_DIV_40               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3)

+#define LL_RCC_RTC_HSE_DIV_41               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)

+#define LL_RCC_RTC_HSE_DIV_42               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)

+#define LL_RCC_RTC_HSE_DIV_43               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

+#define LL_RCC_RTC_HSE_DIV_44               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)

+#define LL_RCC_RTC_HSE_DIV_45               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)

+#define LL_RCC_RTC_HSE_DIV_46               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)

+#define LL_RCC_RTC_HSE_DIV_47               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

+#define LL_RCC_RTC_HSE_DIV_48               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4)

+#define LL_RCC_RTC_HSE_DIV_49               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)

+#define LL_RCC_RTC_HSE_DIV_50               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)

+#define LL_RCC_RTC_HSE_DIV_51               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

+#define LL_RCC_RTC_HSE_DIV_52               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)

+#define LL_RCC_RTC_HSE_DIV_53               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)

+#define LL_RCC_RTC_HSE_DIV_54               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)

+#define LL_RCC_RTC_HSE_DIV_55               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

+#define LL_RCC_RTC_HSE_DIV_56               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)

+#define LL_RCC_RTC_HSE_DIV_57               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)

+#define LL_RCC_RTC_HSE_DIV_58               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)

+#define LL_RCC_RTC_HSE_DIV_59               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

+#define LL_RCC_RTC_HSE_DIV_60               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)

+#define LL_RCC_RTC_HSE_DIV_61               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)

+#define LL_RCC_RTC_HSE_DIV_62               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)

+#define LL_RCC_RTC_HSE_DIV_63               (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_USARTx_CLKSOURCE  Peripheral USART clock source selection

+  * @{

+  */

+#if defined(RCC_D2CCIP2R_USART16SEL)

+#define LL_RCC_USART16_CLKSOURCE_PCLK2         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U)

+#define LL_RCC_USART16_CLKSOURCE_PLL2Q         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0)

+#define LL_RCC_USART16_CLKSOURCE_PLL3Q         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_1)

+#define LL_RCC_USART16_CLKSOURCE_HSI           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)

+#define LL_RCC_USART16_CLKSOURCE_CSI           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_2)

+#define LL_RCC_USART16_CLKSOURCE_LSE           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)

+#else

+#define LL_RCC_USART16910_CLKSOURCE_PCLK2      LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U)

+#define LL_RCC_USART16910_CLKSOURCE_PLL2Q      LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0)

+#define LL_RCC_USART16910_CLKSOURCE_PLL3Q      LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_1)

+#define LL_RCC_USART16910_CLKSOURCE_HSI        LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1)

+#define LL_RCC_USART16910_CLKSOURCE_CSI        LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_2)

+#define LL_RCC_USART16910_CLKSOURCE_LSE        LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2)

+/*  Aliases */

+#define LL_RCC_USART16_CLKSOURCE_PCLK2         LL_RCC_USART16910_CLKSOURCE_PCLK2

+#define LL_RCC_USART16_CLKSOURCE_PLL2Q         LL_RCC_USART16910_CLKSOURCE_PLL2Q

+#define LL_RCC_USART16_CLKSOURCE_PLL3Q         LL_RCC_USART16910_CLKSOURCE_PLL3Q

+#define LL_RCC_USART16_CLKSOURCE_HSI           LL_RCC_USART16910_CLKSOURCE_HSI

+#define LL_RCC_USART16_CLKSOURCE_CSI           LL_RCC_USART16910_CLKSOURCE_CSI

+#define LL_RCC_USART16_CLKSOURCE_LSE           LL_RCC_USART16910_CLKSOURCE_LSE

+#endif  /* RCC_D2CCIP2R_USART16SEL */

+#if defined(RCC_D2CCIP2R_USART28SEL)

+#define LL_RCC_USART234578_CLKSOURCE_PCLK1     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U)

+#define LL_RCC_USART234578_CLKSOURCE_PLL2Q     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0)

+#define LL_RCC_USART234578_CLKSOURCE_PLL3Q     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_1)

+#define LL_RCC_USART234578_CLKSOURCE_HSI       LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)

+#define LL_RCC_USART234578_CLKSOURCE_CSI       LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_2)

+#define LL_RCC_USART234578_CLKSOURCE_LSE       LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)

+#else

+#define LL_RCC_USART234578_CLKSOURCE_PCLK1     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U)

+#define LL_RCC_USART234578_CLKSOURCE_PLL2Q     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0)

+#define LL_RCC_USART234578_CLKSOURCE_PLL3Q     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_1)

+#define LL_RCC_USART234578_CLKSOURCE_HSI       LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1)

+#define LL_RCC_USART234578_CLKSOURCE_CSI       LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_2)

+#define LL_RCC_USART234578_CLKSOURCE_LSE       LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2)

+#endif /* RCC_D2CCIP2R_USART28SEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_LPUARTx_CLKSOURCE  Peripheral LPUART clock source selection

+  * @{

+  */

+#if defined(RCC_D3CCIPR_LPUART1SEL)

+#define LL_RCC_LPUART1_CLKSOURCE_PCLK4         (0x00000000U)

+#define LL_RCC_LPUART1_CLKSOURCE_PLL2Q         (RCC_D3CCIPR_LPUART1SEL_0)

+#define LL_RCC_LPUART1_CLKSOURCE_PLL3Q         (RCC_D3CCIPR_LPUART1SEL_1)

+#define LL_RCC_LPUART1_CLKSOURCE_HSI           (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1)

+#define LL_RCC_LPUART1_CLKSOURCE_CSI           (RCC_D3CCIPR_LPUART1SEL_2)

+#define LL_RCC_LPUART1_CLKSOURCE_LSE           (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_2)

+#else

+#define LL_RCC_LPUART1_CLKSOURCE_PCLK4         (0x00000000U)

+#define LL_RCC_LPUART1_CLKSOURCE_PLL2Q         (RCC_SRDCCIPR_LPUART1SEL_0)

+#define LL_RCC_LPUART1_CLKSOURCE_PLL3Q         (RCC_SRDCCIPR_LPUART1SEL_1)

+#define LL_RCC_LPUART1_CLKSOURCE_HSI           (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1)

+#define LL_RCC_LPUART1_CLKSOURCE_CSI           (RCC_SRDCCIPR_LPUART1SEL_2)

+#define LL_RCC_LPUART1_CLKSOURCE_LSE           (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_2)

+#endif /* RCC_D3CCIPR_LPUART1SEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE  Peripheral I2C clock source selection

+  * @{

+  */

+#if defined (RCC_D2CCIP2R_I2C123SEL)

+#define LL_RCC_I2C123_CLKSOURCE_PCLK1          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U)

+#define LL_RCC_I2C123_CLKSOURCE_PLL3R          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0)

+#define LL_RCC_I2C123_CLKSOURCE_HSI            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_1)

+#define LL_RCC_I2C123_CLKSOURCE_CSI            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)

+#else

+#define LL_RCC_I2C123_CLKSOURCE_PCLK1          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U)

+#define LL_RCC_I2C123_CLKSOURCE_PLL3R          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0)

+#define LL_RCC_I2C123_CLKSOURCE_HSI            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_1)

+#define LL_RCC_I2C123_CLKSOURCE_CSI            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1)

+#endif /* RCC_D2CCIP2R_I2C123SEL */

+#if defined (RCC_D3CCIPR_I2C4SEL)

+#define LL_RCC_I2C4_CLKSOURCE_PCLK4            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    0x00000000U)

+#define LL_RCC_I2C4_CLKSOURCE_PLL3R            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    RCC_D3CCIPR_I2C4SEL_0)

+#define LL_RCC_I2C4_CLKSOURCE_HSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    RCC_D3CCIPR_I2C4SEL_1)

+#define LL_RCC_I2C4_CLKSOURCE_CSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1)

+#else

+#define LL_RCC_I2C4_CLKSOURCE_PCLK4            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    0x00000000U)

+#define LL_RCC_I2C4_CLKSOURCE_PLL3R            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    RCC_SRDCCIPR_I2C4SEL_0)

+#define LL_RCC_I2C4_CLKSOURCE_HSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    RCC_SRDCCIPR_I2C4SEL_1)

+#define LL_RCC_I2C4_CLKSOURCE_CSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_I2C4SEL,    RCC_SRDCCIPR_I2C4SEL_Pos,    RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1)

+#endif /* RCC_D3CCIPR_I2C4SEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE  Peripheral LPTIM clock source selection

+  * @{

+  */

+#if defined(RCC_D2CCIP2R_LPTIM1SEL)

+#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  0x00000000U)

+#define LL_RCC_LPTIM1_CLKSOURCE_PLL2P          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_0)

+#define LL_RCC_LPTIM1_CLKSOURCE_PLL3R          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_1)

+#define LL_RCC_LPTIM1_CLKSOURCE_LSE            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1)

+#define LL_RCC_LPTIM1_CLKSOURCE_LSI            LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_2)

+#define LL_RCC_LPTIM1_CLKSOURCE_CLKP           LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,  RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2)

+#else

+#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  0x00000000U)

+#define LL_RCC_LPTIM1_CLKSOURCE_PLL2P          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_0)

+#define LL_RCC_LPTIM1_CLKSOURCE_PLL3R          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_1)

+#define LL_RCC_LPTIM1_CLKSOURCE_LSE            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1)

+#define LL_RCC_LPTIM1_CLKSOURCE_LSI            LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_2)

+#define LL_RCC_LPTIM1_CLKSOURCE_CLKP           LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,  RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2)

+#endif /* RCC_D2CCIP2R_LPTIM1SEL */

+#if defined(RCC_D3CCIPR_LPTIM2SEL)

+#define LL_RCC_LPTIM2_CLKSOURCE_PCLK4          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   0x00000000U)

+#define LL_RCC_LPTIM2_CLKSOURCE_PLL2P          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_0)

+#define LL_RCC_LPTIM2_CLKSOURCE_PLL3R          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_1)

+#define LL_RCC_LPTIM2_CLKSOURCE_LSE            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1)

+#define LL_RCC_LPTIM2_CLKSOURCE_LSI            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_2)

+#define LL_RCC_LPTIM2_CLKSOURCE_CLKP           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,   RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2)

+#else

+#define LL_RCC_LPTIM2_CLKSOURCE_PCLK4          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   0x00000000U)

+#define LL_RCC_LPTIM2_CLKSOURCE_PLL2P          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_0)

+#define LL_RCC_LPTIM2_CLKSOURCE_PLL3R          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_1)

+#define LL_RCC_LPTIM2_CLKSOURCE_LSE            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1)

+#define LL_RCC_LPTIM2_CLKSOURCE_LSI            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_2)

+#define LL_RCC_LPTIM2_CLKSOURCE_CLKP           LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM2SEL,   RCC_SRDCCIPR_LPTIM2SEL_Pos,   RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2)

+#endif /* RCC_D3CCIPR_LPTIM2SEL */

+#if defined(RCC_D3CCIPR_LPTIM345SEL)

+#define LL_RCC_LPTIM345_CLKSOURCE_PCLK4        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, 0x00000000U)

+#define LL_RCC_LPTIM345_CLKSOURCE_PLL2P        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0)

+#define LL_RCC_LPTIM345_CLKSOURCE_PLL3R        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_1)

+#define LL_RCC_LPTIM345_CLKSOURCE_LSE          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)

+#define LL_RCC_LPTIM345_CLKSOURCE_LSI          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_2)

+#define LL_RCC_LPTIM345_CLKSOURCE_CLKP         LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)

+#else

+#define LL_RCC_LPTIM345_CLKSOURCE_PCLK4        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, 0x00000000U)

+#define LL_RCC_LPTIM345_CLKSOURCE_PLL2P        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0)

+#define LL_RCC_LPTIM345_CLKSOURCE_PLL3R        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_1)

+#define LL_RCC_LPTIM345_CLKSOURCE_LSE          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1)

+#define LL_RCC_LPTIM345_CLKSOURCE_LSI          LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_2)

+#define LL_RCC_LPTIM345_CLKSOURCE_CLKP         LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2)

+/* aliases*/

+#define LL_RCC_LPTIM3_CLKSOURCE_PCLK4          LL_RCC_LPTIM345_CLKSOURCE_PCLK4

+#define LL_RCC_LPTIM3_CLKSOURCE_PLL2P          LL_RCC_LPTIM345_CLKSOURCE_PLL2P

+#define LL_RCC_LPTIM3_CLKSOURCE_PLL3R          LL_RCC_LPTIM345_CLKSOURCE_PLL3R

+#define LL_RCC_LPTIM3_CLKSOURCE_LSE            LL_RCC_LPTIM345_CLKSOURCE_LSE

+#define LL_RCC_LPTIM3_CLKSOURCE_LSI            LL_RCC_LPTIM345_CLKSOURCE_LSI

+#define LL_RCC_LPTIM3_CLKSOURCE_CLKP           LL_RCC_LPTIM345_CLKSOURCE_CLKP

+#endif /* RCC_D3CCIPR_LPTIM345SEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE  Peripheral SAI clock source selection

+  * @{

+  */

+#if defined(RCC_D2CCIP1R_SAI1SEL)

+#define LL_RCC_SAI1_CLKSOURCE_PLL1Q            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  0x00000000U)

+#define LL_RCC_SAI1_CLKSOURCE_PLL2P            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_0)

+#define LL_RCC_SAI1_CLKSOURCE_PLL3P            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_1)

+#define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN         LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1)

+#define LL_RCC_SAI1_CLKSOURCE_CLKP             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  RCC_D2CCIP1R_SAI1SEL_2)

+#else

+#define LL_RCC_SAI1_CLKSOURCE_PLL1Q            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  0x00000000U)

+#define LL_RCC_SAI1_CLKSOURCE_PLL2P            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_0)

+#define LL_RCC_SAI1_CLKSOURCE_PLL3P            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_1)

+#define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN         LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1)

+#define LL_RCC_SAI1_CLKSOURCE_CLKP             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  RCC_CDCCIP1R_SAI1SEL_2)

+#endif

+#if defined(SAI3)

+#define LL_RCC_SAI23_CLKSOURCE_PLL1Q           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U)

+#define LL_RCC_SAI23_CLKSOURCE_PLL2P           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0)

+#define LL_RCC_SAI23_CLKSOURCE_PLL3P           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_1)

+#define LL_RCC_SAI23_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1)

+#define LL_RCC_SAI23_CLKSOURCE_CLKP            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_2)

+#endif /* SAI3 */

+#if defined(RCC_CDCCIP1R_SAI2ASEL)

+#define LL_RCC_SAI2A_CLKSOURCE_PLL1Q           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  0x00000000U)

+#define LL_RCC_SAI2A_CLKSOURCE_PLL2P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_0)

+#define LL_RCC_SAI2A_CLKSOURCE_PLL3P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_1)

+#define LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1)

+#define LL_RCC_SAI2A_CLKSOURCE_CLKP            LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_2)

+#define LL_RCC_SAI2A_CLKSOURCE_SPDIF           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2)

+#endif /* RCC_CDCCIP1R_SAI2ASEL */

+#if defined(RCC_CDCCIP1R_SAI2BSEL)

+#define LL_RCC_SAI2B_CLKSOURCE_PLL1Q           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  0x00000000U)

+#define LL_RCC_SAI2B_CLKSOURCE_PLL2P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_0)

+#define LL_RCC_SAI2B_CLKSOURCE_PLL3P           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_1)

+#define LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1)

+#define LL_RCC_SAI2B_CLKSOURCE_CLKP            LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_2)

+#define LL_RCC_SAI2B_CLKSOURCE_SPDIF           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2)

+#endif /* RCC_CDCCIP1R_SAI2BSEL */

+#if defined(SAI4_Block_A)

+#define LL_RCC_SAI4A_CLKSOURCE_PLL1Q           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  0x00000000U)

+#define LL_RCC_SAI4A_CLKSOURCE_PLL2P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_0)

+#define LL_RCC_SAI4A_CLKSOURCE_PLL3P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_1)

+#define LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1)

+#define LL_RCC_SAI4A_CLKSOURCE_CLKP            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  RCC_D3CCIPR_SAI4ASEL_2)

+#endif /* SAI4_Block_A */

+#if defined(SAI4_Block_B)

+#define LL_RCC_SAI4B_CLKSOURCE_PLL1Q           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  0x00000000U)

+#define LL_RCC_SAI4B_CLKSOURCE_PLL2P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_0)

+#define LL_RCC_SAI4B_CLKSOURCE_PLL3P           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_1)

+#define LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1)

+#define LL_RCC_SAI4B_CLKSOURCE_CLKP            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  RCC_D3CCIPR_SAI4BSEL_2)

+#endif /* SAI4_Block_B */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_SDMMC_CLKSOURCE  Peripheral SDMMC clock source selection

+  * @{

+  */

+#if defined(RCC_D1CCIPR_SDMMCSEL)

+#define LL_RCC_SDMMC_CLKSOURCE_PLL1Q           (0x00000000U)

+#define LL_RCC_SDMMC_CLKSOURCE_PLL2R           (RCC_D1CCIPR_SDMMCSEL)

+#else

+#define LL_RCC_SDMMC_CLKSOURCE_PLL1Q           (0x00000000U)

+#define LL_RCC_SDMMC_CLKSOURCE_PLL2R           (RCC_CDCCIPR_SDMMCSEL)

+#endif /* RCC_D1CCIPR_SDMMCSEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_RNG_CLKSOURCE  Peripheral RNG clock source selection

+  * @{

+  */

+#if defined(RCC_D2CCIP2R_RNGSEL)

+#define LL_RCC_RNG_CLKSOURCE_HSI48             (0x00000000U)

+#define LL_RCC_RNG_CLKSOURCE_PLL1Q             (RCC_D2CCIP2R_RNGSEL_0)

+#define LL_RCC_RNG_CLKSOURCE_LSE               (RCC_D2CCIP2R_RNGSEL_1)

+#define LL_RCC_RNG_CLKSOURCE_LSI               (RCC_D2CCIP2R_RNGSEL_1 | RCC_D2CCIP2R_RNGSEL_0)

+#else

+#define LL_RCC_RNG_CLKSOURCE_HSI48             (0x00000000U)

+#define LL_RCC_RNG_CLKSOURCE_PLL1Q             (RCC_CDCCIP2R_RNGSEL_0)

+#define LL_RCC_RNG_CLKSOURCE_LSE               (RCC_CDCCIP2R_RNGSEL_1)

+#define LL_RCC_RNG_CLKSOURCE_LSI               (RCC_CDCCIP2R_RNGSEL_1 | RCC_CDCCIP2R_RNGSEL_0)

+#endif /* RCC_D2CCIP2R_RNGSEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_USB_CLKSOURCE  Peripheral USB clock source selection

+  * @{

+  */

+#if defined(RCC_D2CCIP2R_USBSEL)

+#define LL_RCC_USB_CLKSOURCE_DISABLE           (0x00000000U)

+#define LL_RCC_USB_CLKSOURCE_PLL1Q             (RCC_D2CCIP2R_USBSEL_0)

+#define LL_RCC_USB_CLKSOURCE_PLL3Q             (RCC_D2CCIP2R_USBSEL_1)

+#define LL_RCC_USB_CLKSOURCE_HSI48             (RCC_D2CCIP2R_USBSEL_1 | RCC_D2CCIP2R_USBSEL_0)

+#else

+#define LL_RCC_USB_CLKSOURCE_DISABLE           (0x00000000U)

+#define LL_RCC_USB_CLKSOURCE_PLL1Q             (RCC_CDCCIP2R_USBSEL_0)

+#define LL_RCC_USB_CLKSOURCE_PLL3Q             (RCC_CDCCIP2R_USBSEL_1)

+#define LL_RCC_USB_CLKSOURCE_HSI48             (RCC_CDCCIP2R_USBSEL_1 | RCC_CDCCIP2R_USBSEL_0)

+#endif /* RCC_D2CCIP2R_USBSEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_CEC_CLKSOURCE  Peripheral CEC clock source selection

+  * @{

+  */

+#if defined(RCC_D2CCIP2R_CECSEL)

+#define LL_RCC_CEC_CLKSOURCE_LSE               (0x00000000U)

+#define LL_RCC_CEC_CLKSOURCE_LSI               (RCC_D2CCIP2R_CECSEL_0)

+#define LL_RCC_CEC_CLKSOURCE_CSI_DIV122        (RCC_D2CCIP2R_CECSEL_1)

+#else

+#define LL_RCC_CEC_CLKSOURCE_LSE               (0x00000000U)

+#define LL_RCC_CEC_CLKSOURCE_LSI               (RCC_CDCCIP2R_CECSEL_0)

+#define LL_RCC_CEC_CLKSOURCE_CSI_DIV122        (RCC_CDCCIP2R_CECSEL_1)

+#endif

+/**

+  * @}

+  */

+

+#if defined(DSI)

+/** @defgroup RCC_LL_EC_DSI_CLKSOURCE  Peripheral DSI clock source selection

+  * @{

+  */

+#define LL_RCC_DSI_CLKSOURCE_PHY               (0x00000000U)

+#define LL_RCC_DSI_CLKSOURCE_PLL2Q             (RCC_D1CCIPR_DSISEL)

+/**

+  * @}

+  */

+#endif /* DSI */

+

+/** @defgroup RCC_LL_EC_DFSDM_CLKSOURCE  Peripheral DFSDM clock source selection

+  * @{

+  */

+#if defined(RCC_D2CCIP1R_DFSDM1SEL)

+#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2          (0x00000000U)

+#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK         (RCC_D2CCIP1R_DFSDM1SEL)

+#else

+#define LL_RCC_DFSDM1_CLKSOURCE_PCLK2          (0x00000000U)

+#define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK         (RCC_CDCCIP1R_DFSDM1SEL)

+#endif /* RCC_D2CCIP1R_DFSDM1SEL */

+/**

+  * @}

+  */

+

+#if defined(DFSDM2_BASE)

+/** @defgroup RCC_LL_EC_DFSDM2_CLKSOURCE  Peripheral DFSDM2 clock source selection

+  * @{

+  */

+#define LL_RCC_DFSDM2_CLKSOURCE_PCLK4          (0x00000000U)

+#define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK         (RCC_SRDCCIPR_DFSDM2SEL)

+/**

+  * @}

+  */

+#endif /* DFSDM2_BASE */

+

+/** @defgroup RCC_LL_EC_FMC_CLKSOURCE  Peripheral FMC clock source selection

+  * @{

+  */

+#if defined(RCC_D1CCIPR_FMCSEL)

+#define LL_RCC_FMC_CLKSOURCE_HCLK              (0x00000000U)

+#define LL_RCC_FMC_CLKSOURCE_PLL1Q             (RCC_D1CCIPR_FMCSEL_0)

+#define LL_RCC_FMC_CLKSOURCE_PLL2R             (RCC_D1CCIPR_FMCSEL_1)

+#define LL_RCC_FMC_CLKSOURCE_CLKP              (RCC_D1CCIPR_FMCSEL_0 | RCC_D1CCIPR_FMCSEL_1)

+#else

+#define LL_RCC_FMC_CLKSOURCE_HCLK              (0x00000000U)

+#define LL_RCC_FMC_CLKSOURCE_PLL1Q             (RCC_CDCCIPR_FMCSEL_0)

+#define LL_RCC_FMC_CLKSOURCE_PLL2R             (RCC_CDCCIPR_FMCSEL_1)

+#define LL_RCC_FMC_CLKSOURCE_CLKP              (RCC_CDCCIPR_FMCSEL_0 | RCC_CDCCIPR_FMCSEL_1)

+#endif /* RCC_D1CCIPR_FMCSEL */

+/**

+  * @}

+  */

+

+#if defined(QUADSPI)

+/** @defgroup RCC_LL_EC_QSPI_CLKSOURCE  Peripheral QSPI clock source selection

+  * @{

+  */

+#define LL_RCC_QSPI_CLKSOURCE_HCLK             (0x00000000U)

+#define LL_RCC_QSPI_CLKSOURCE_PLL1Q            (RCC_D1CCIPR_QSPISEL_0)

+#define LL_RCC_QSPI_CLKSOURCE_PLL2R            (RCC_D1CCIPR_QSPISEL_1)

+#define LL_RCC_QSPI_CLKSOURCE_CLKP             (RCC_D1CCIPR_QSPISEL_0 | RCC_D1CCIPR_QSPISEL_1)

+/**

+  * @}

+  */

+#endif /* QUADSPI */

+

+

+#if defined(OCTOSPI1) || defined(OCTOSPI2)

+/** @defgroup RCC_LL_EC_OSPI_CLKSOURCE  Peripheral OSPI clock source selection

+  * @{

+  */

+#define LL_RCC_OSPI_CLKSOURCE_HCLK             (0x00000000U)

+#define LL_RCC_OSPI_CLKSOURCE_PLL1Q            (RCC_CDCCIPR_OCTOSPISEL_0)

+#define LL_RCC_OSPI_CLKSOURCE_PLL2R            (RCC_CDCCIPR_OCTOSPISEL_1)

+#define LL_RCC_OSPI_CLKSOURCE_CLKP             (RCC_CDCCIPR_OCTOSPISEL_0 | RCC_CDCCIPR_OCTOSPISEL_1)

+/**

+  * @}

+  */

+#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */

+

+

+/** @defgroup RCC_LL_EC_CLKP_CLKSOURCE  Peripheral CLKP clock source selection

+  * @{

+  */

+#if defined(RCC_D1CCIPR_CKPERSEL)

+#define LL_RCC_CLKP_CLKSOURCE_HSI              (0x00000000U)

+#define LL_RCC_CLKP_CLKSOURCE_CSI              (RCC_D1CCIPR_CKPERSEL_0)

+#define LL_RCC_CLKP_CLKSOURCE_HSE              (RCC_D1CCIPR_CKPERSEL_1)

+#else

+#define LL_RCC_CLKP_CLKSOURCE_HSI              (0x00000000U)

+#define LL_RCC_CLKP_CLKSOURCE_CSI              (RCC_CDCCIPR_CKPERSEL_0)

+#define LL_RCC_CLKP_CLKSOURCE_HSE              (RCC_CDCCIPR_CKPERSEL_1)

+#endif /* RCC_D1CCIPR_CKPERSEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_SPIx_CLKSOURCE  Peripheral SPI clock source selection

+  * @{

+  */

+#if defined(RCC_D2CCIP1R_SPI123SEL)

+#define LL_RCC_SPI123_CLKSOURCE_PLL1Q          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U)

+#define LL_RCC_SPI123_CLKSOURCE_PLL2P          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0)

+#define LL_RCC_SPI123_CLKSOURCE_PLL3P          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_1)

+#define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN       LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)

+#define LL_RCC_SPI123_CLKSOURCE_CLKP           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_2)

+#else

+#define LL_RCC_SPI123_CLKSOURCE_PLL1Q          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U)

+#define LL_RCC_SPI123_CLKSOURCE_PLL2P          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0)

+#define LL_RCC_SPI123_CLKSOURCE_PLL3P          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_1)

+#define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN       LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1)

+#define LL_RCC_SPI123_CLKSOURCE_CLKP           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_2)

+#endif /* RCC_D2CCIP1R_SPI123SEL */

+#if defined(RCC_D2CCIP1R_SPI45SEL)

+#define LL_RCC_SPI45_CLKSOURCE_PCLK2           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  0x00000000U)

+#define LL_RCC_SPI45_CLKSOURCE_PLL2Q           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_0)

+#define LL_RCC_SPI45_CLKSOURCE_PLL3Q           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_1)

+#define LL_RCC_SPI45_CLKSOURCE_HSI             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)

+#define LL_RCC_SPI45_CLKSOURCE_CSI             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_2)

+#define LL_RCC_SPI45_CLKSOURCE_HSE             LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)

+#else

+#define LL_RCC_SPI45_CLKSOURCE_PCLK2           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  0x00000000U)

+#define LL_RCC_SPI45_CLKSOURCE_PLL2Q           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_0)

+#define LL_RCC_SPI45_CLKSOURCE_PLL3Q           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_1)

+#define LL_RCC_SPI45_CLKSOURCE_HSI             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1)

+#define LL_RCC_SPI45_CLKSOURCE_CSI             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_2)

+#define LL_RCC_SPI45_CLKSOURCE_HSE             LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2)

+#endif /* (RCC_D2CCIP1R_SPI45SEL */

+#if defined(RCC_D3CCIPR_SPI6SEL)

+#define LL_RCC_SPI6_CLKSOURCE_PCLK4            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    0x00000000U)

+#define LL_RCC_SPI6_CLKSOURCE_PLL2Q            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_0)

+#define LL_RCC_SPI6_CLKSOURCE_PLL3Q            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_1)

+#define LL_RCC_SPI6_CLKSOURCE_HSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1)

+#define LL_RCC_SPI6_CLKSOURCE_CSI              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_2)

+#define LL_RCC_SPI6_CLKSOURCE_HSE              LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2)

+#else

+#define LL_RCC_SPI6_CLKSOURCE_PCLK4            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    0x00000000U)

+#define LL_RCC_SPI6_CLKSOURCE_PLL2Q            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_0)

+#define LL_RCC_SPI6_CLKSOURCE_PLL3Q            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_1)

+#define LL_RCC_SPI6_CLKSOURCE_HSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)

+#define LL_RCC_SPI6_CLKSOURCE_CSI              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_2)

+#define LL_RCC_SPI6_CLKSOURCE_HSE              LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)

+#define LL_RCC_SPI6_CLKSOURCE_I2S_CKIN         LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,    RCC_SRDCCIPR_SPI6SEL_Pos,    RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)

+#endif /* RCC_D3CCIPR_SPI6SEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_SPDIF_CLKSOURCE  Peripheral SPDIF clock source selection

+  * @{

+  */

+#if defined(RCC_D2CCIP1R_SPDIFSEL)

+#define LL_RCC_SPDIF_CLKSOURCE_PLL1Q           (0x00000000U)

+#define LL_RCC_SPDIF_CLKSOURCE_PLL2R           (RCC_D2CCIP1R_SPDIFSEL_0)

+#define LL_RCC_SPDIF_CLKSOURCE_PLL3R           (RCC_D2CCIP1R_SPDIFSEL_1)

+#define LL_RCC_SPDIF_CLKSOURCE_HSI             (RCC_D2CCIP1R_SPDIFSEL_0 | RCC_D2CCIP1R_SPDIFSEL_1)

+#else

+#define LL_RCC_SPDIF_CLKSOURCE_PLL1Q           (0x00000000U)

+#define LL_RCC_SPDIF_CLKSOURCE_PLL2R           (RCC_CDCCIP1R_SPDIFSEL_0)

+#define LL_RCC_SPDIF_CLKSOURCE_PLL3R           (RCC_CDCCIP1R_SPDIFSEL_1)

+#define LL_RCC_SPDIF_CLKSOURCE_HSI             (RCC_CDCCIP1R_SPDIFSEL_0 | RCC_CDCCIP1R_SPDIFSEL_1)

+#endif /* RCC_D2CCIP1R_SPDIFSEL */

+/**

+  * @}

+  */

+

+#if defined(FDCAN1) || defined(FDCAN2)

+/** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE  Peripheral FDCAN clock source selection

+  * @{

+  */

+#if defined(RCC_D2CCIP1R_FDCANSEL)

+#define LL_RCC_FDCAN_CLKSOURCE_HSE             (0x00000000U)

+#define LL_RCC_FDCAN_CLKSOURCE_PLL1Q           (RCC_D2CCIP1R_FDCANSEL_0)

+#define LL_RCC_FDCAN_CLKSOURCE_PLL2Q           (RCC_D2CCIP1R_FDCANSEL_1)

+#else

+#define LL_RCC_FDCAN_CLKSOURCE_HSE             (0x00000000U)

+#define LL_RCC_FDCAN_CLKSOURCE_PLL1Q           (RCC_CDCCIP1R_FDCANSEL_0)

+#define LL_RCC_FDCAN_CLKSOURCE_PLL2Q           (RCC_CDCCIP1R_FDCANSEL_1)

+#endif /* RCC_D2CCIP1R_FDCANSEL */

+/**

+  * @}

+  */

+#endif /*FDCAN1 || FDCAN2*/

+

+/** @defgroup RCC_LL_EC_SWP_CLKSOURCE  Peripheral SWP clock source selection

+  * @{

+  */

+#if defined(RCC_D2CCIP1R_SWPSEL)

+#define LL_RCC_SWP_CLKSOURCE_PCLK1             (0x00000000U)

+#define LL_RCC_SWP_CLKSOURCE_HSI               (RCC_D2CCIP1R_SWPSEL)

+#else

+#define LL_RCC_SWP_CLKSOURCE_PCLK1             (0x00000000U)

+#define LL_RCC_SWP_CLKSOURCE_HSI               (RCC_CDCCIP1R_SWPSEL)

+#endif /* RCC_D2CCIP1R_SWPSEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_ADC_CLKSOURCE  Peripheral ADC clock source selection

+  * @{

+  */

+#if defined(RCC_D3CCIPR_ADCSEL)

+#define LL_RCC_ADC_CLKSOURCE_PLL2P             (0x00000000U)

+#define LL_RCC_ADC_CLKSOURCE_PLL3R             (RCC_D3CCIPR_ADCSEL_0)

+#define LL_RCC_ADC_CLKSOURCE_CLKP              (RCC_D3CCIPR_ADCSEL_1)

+#else

+#define LL_RCC_ADC_CLKSOURCE_PLL2P             (0x00000000U)

+#define LL_RCC_ADC_CLKSOURCE_PLL3R             (RCC_SRDCCIPR_ADCSEL_0)

+#define LL_RCC_ADC_CLKSOURCE_CLKP              (RCC_SRDCCIPR_ADCSEL_1)

+#endif /* RCC_D3CCIPR_ADCSEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_USARTx_CLKSOURCE  Peripheral USART get clock source

+  * @{

+  */

+#if defined (RCC_D2CCIP2R_USART16SEL)

+#define LL_RCC_USART16_CLKSOURCE         LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U)

+#else

+#define LL_RCC_USART16_CLKSOURCE         LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U)

+/* alias*/

+#define LL_RCC_USART16910_CLKSOURCE      LL_RCC_USART16_CLKSOURCE

+#endif /* RCC_D2CCIP2R_USART16SEL */

+#if defined (RCC_D2CCIP2R_USART28SEL)

+#define LL_RCC_USART234578_CLKSOURCE     LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U)

+#else

+#define LL_RCC_USART234578_CLKSOURCE     LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U)

+#endif /* RCC_D2CCIP2R_USART28SEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_LPUARTx_CLKSOURCE  Peripheral LPUART get clock source

+  * @{

+  */

+#if defined(RCC_D3CCIPR_LPUART1SEL)

+#define LL_RCC_LPUART1_CLKSOURCE         RCC_D3CCIPR_LPUART1SEL

+#else

+#define LL_RCC_LPUART1_CLKSOURCE         RCC_SRDCCIPR_LPUART1SEL

+#endif /* RCC_D3CCIPR_LPUART1SEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE  Peripheral I2C get clock source

+  * @{

+  */

+#if defined(RCC_D2CCIP2R_I2C123SEL)

+#define LL_RCC_I2C123_CLKSOURCE          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U)

+#else

+#define LL_RCC_I2C123_CLKSOURCE          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U)

+#endif /* RCC_D2CCIP2R_I2C123SEL */

+#if defined(RCC_D3CCIPR_I2C4SEL)

+#define LL_RCC_I2C4_CLKSOURCE            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_I2C4SEL,    RCC_D3CCIPR_I2C4SEL_Pos,    0x00000000U)

+#else

+#define LL_RCC_I2C4_CLKSOURCE            LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL,   RCC_SRDCCIPR_I2C4SEL_Pos,   0x00000000U)

+#endif /* RCC_D3CCIPR_I2C4SEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE  Peripheral LPTIM get clock source

+  * @{

+  */

+#if defined(RCC_D2CCIP2R_LPTIM1SEL)

+#define LL_RCC_LPTIM1_CLKSOURCE          LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL,  RCC_D2CCIP2R_LPTIM1SEL_Pos,   0x00000000U)

+#else

+#define LL_RCC_LPTIM1_CLKSOURCE          LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL,  RCC_CDCCIP2R_LPTIM1SEL_Pos,   0x00000000U)

+#endif /* RCC_D2CCIP2R_LPTIM1SEL) */

+#if defined(RCC_D3CCIPR_LPTIM2SEL)

+#define LL_RCC_LPTIM2_CLKSOURCE          LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM2SEL,   RCC_D3CCIPR_LPTIM2SEL_Pos,    0x00000000U)

+#else

+#define LL_RCC_LPTIM2_CLKSOURCE          LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL,  RCC_SRDCCIPR_LPTIM2SEL_Pos,   0x00000000U)

+#endif /* RCC_D3CCIPR_LPTIM2SEL */

+#if defined(RCC_D3CCIPR_LPTIM345SEL)

+#define LL_RCC_LPTIM345_CLKSOURCE        LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos,  0x00000000U)

+#else

+#define LL_RCC_LPTIM345_CLKSOURCE        LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos,   0x00000000U)

+#define LL_RCC_LPTIM3_CLKSOURCE          LL_RCC_LPTIM345_CLKSOURCE  /* alias */

+#endif /* RCC_D3CCIPR_LPTIM345SEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_SAIx_CLKSOURCE  Peripheral SAI get clock source

+  * @{

+  */

+#if defined(RCC_D2CCIP1R_SAI1SEL)

+#define LL_RCC_SAI1_CLKSOURCE            LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL,  RCC_D2CCIP1R_SAI1SEL_Pos,  0x00000000U)

+#else

+#define LL_RCC_SAI1_CLKSOURCE            LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL,  RCC_CDCCIP1R_SAI1SEL_Pos,  0x00000000U)

+#endif /* RCC_D2CCIP1R_SAI1SEL */

+#if defined(RCC_D2CCIP1R_SAI23SEL)

+#define LL_RCC_SAI23_CLKSOURCE           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U)

+#endif /* RCC_D2CCIP1R_SAI23SEL */

+#if defined(RCC_CDCCIP1R_SAI2ASEL)

+#define LL_RCC_SAI2A_CLKSOURCE           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2ASEL,  RCC_CDCCIP1R_SAI2ASEL_Pos,  0x00000000U)

+#endif /* RCC_CDCCIP1R_SAI2ASEL */

+#if defined(RCC_CDCCIP1R_SAI2BSEL)

+#define LL_RCC_SAI2B_CLKSOURCE           LL_CLKSOURCE(CDCCIP1,  RCC_CDCCIP1R_SAI2BSEL,  RCC_CDCCIP1R_SAI2BSEL_Pos,  0x00000000U)

+#endif /*  RCC_CDCCIP1R_SAI2BSEL */

+#if defined(RCC_D3CCIPR_SAI4ASEL)

+#define LL_RCC_SAI4A_CLKSOURCE           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4ASEL,  RCC_D3CCIPR_SAI4ASEL_Pos,  0x00000000U)

+#endif /* RCC_D3CCIPR_SAI4ASEL */

+#if defined(RCC_D3CCIPR_SAI4BSEL)

+#define LL_RCC_SAI4B_CLKSOURCE           LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SAI4BSEL,  RCC_D3CCIPR_SAI4BSEL_Pos,  0x00000000U)

+#endif /*  RCC_D3CCIPR_SAI4BSEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_SDMMC_CLKSOURCE  Peripheral SDMMC get clock source

+  * @{

+  */

+#if defined(RCC_D1CCIPR_SDMMCSEL)

+#define LL_RCC_SDMMC_CLKSOURCE           RCC_D1CCIPR_SDMMCSEL

+#else

+#define LL_RCC_SDMMC_CLKSOURCE           RCC_CDCCIPR_SDMMCSEL

+#endif /* RCC_D1CCIPR_SDMMCSEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_RNG_CLKSOURCE  Peripheral RNG get clock source

+  * @{

+  */

+#if (RCC_D2CCIP2R_RNGSEL)

+#define LL_RCC_RNG_CLKSOURCE             RCC_D2CCIP2R_RNGSEL

+#else

+#define LL_RCC_RNG_CLKSOURCE             RCC_CDCCIP2R_RNGSEL

+#endif /* RCC_D2CCIP2R_RNGSEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_USB_CLKSOURCE  Peripheral USB get clock source

+  * @{

+  */

+#if (RCC_D2CCIP2R_USBSEL)

+#define LL_RCC_USB_CLKSOURCE             RCC_D2CCIP2R_USBSEL

+#else

+#define LL_RCC_USB_CLKSOURCE             RCC_CDCCIP2R_USBSEL

+#endif  /* RCC_D2CCIP2R_USBSEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_CEC_CLKSOURCE  Peripheral CEC get clock source

+  * @{

+  */

+#if (RCC_D2CCIP2R_CECSEL)

+#define LL_RCC_CEC_CLKSOURCE             RCC_D2CCIP2R_CECSEL

+#else

+#define LL_RCC_CEC_CLKSOURCE             RCC_CDCCIP2R_CECSEL

+#endif /* RCC_D2CCIP2R_CECSEL */

+/**

+  * @}

+  */

+

+#if defined(DSI)

+/** @defgroup RCC_LL_EC_DSI_CLKSOURCE  Peripheral DSI get clock source

+  * @{

+  */

+#define LL_RCC_DSI_CLKSOURCE             RCC_D1CCIPR_DSISEL

+/**

+  * @}

+  */

+#endif /* DSI */

+

+/** @defgroup RCC_LL_EC_DFSDM_CLKSOURCE  Peripheral DFSDM get clock source

+  * @{

+  */

+#if defined(RCC_D2CCIP1R_DFSDM1SEL)

+#define LL_RCC_DFSDM1_CLKSOURCE          RCC_D2CCIP1R_DFSDM1SEL

+#else

+#define LL_RCC_DFSDM1_CLKSOURCE          RCC_CDCCIP1R_DFSDM1SEL

+#endif /* RCC_D2CCIP1R_DFSDM1SEL */

+/**

+  * @}

+  */

+

+#if defined(DFSDM2_BASE)

+/** @defgroup RCC_LL_EC_DFSDM2_CLKSOURCE  Peripheral DFSDM2 get clock source

+  * @{

+  */

+#define LL_RCC_DFSDM2_CLKSOURCE          RCC_SRDCCIPR_DFSDM2SEL

+/**

+  * @}

+  */

+#endif /* DFSDM2 */

+

+

+/** @defgroup RCC_LL_EC_FMC_CLKSOURCE  Peripheral FMC get clock source

+  * @{

+  */

+#if defined(RCC_D1CCIPR_FMCSEL)

+#define LL_RCC_FMC_CLKSOURCE             RCC_D1CCIPR_FMCSEL

+#else

+#define LL_RCC_FMC_CLKSOURCE             RCC_CDCCIPR_FMCSEL

+#endif

+/**

+  * @}

+  */

+

+#if defined(QUADSPI)

+/** @defgroup RCC_LL_EC_QSPI_CLKSOURCE  Peripheral QSPI get clock source

+  * @{

+  */

+#define LL_RCC_QSPI_CLKSOURCE            RCC_D1CCIPR_QSPISEL

+/**

+  * @}

+  */

+#endif /* QUADSPI */

+

+#if defined(OCTOSPI1) || defined(OCTOSPI2)

+/** @defgroup RCC_LL_EC_OSPI_CLKSOURCE  Peripheral OSPI get clock source

+  * @{

+  */

+#define LL_RCC_OSPI_CLKSOURCE            RCC_CDCCIPR_OCTOSPISEL

+/**

+  * @}

+  */

+#endif /* OCTOSPI1 || OCTOSPI2 */

+

+/** @defgroup RCC_LL_EC_CLKP_CLKSOURCE  Peripheral CLKP get clock source

+  * @{

+  */

+#if defined(RCC_D1CCIPR_CKPERSEL)

+#define LL_RCC_CLKP_CLKSOURCE            RCC_D1CCIPR_CKPERSEL

+#else

+#define LL_RCC_CLKP_CLKSOURCE            RCC_CDCCIPR_CKPERSEL

+#endif /* RCC_D1CCIPR_CKPERSEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_SPIx_CLKSOURCE  Peripheral SPI get clock source

+  * @{

+  */

+#if defined(RCC_D2CCIP1R_SPI123SEL)

+#define LL_RCC_SPI123_CLKSOURCE          LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U)

+#else

+#define LL_RCC_SPI123_CLKSOURCE          LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U)

+#endif /* RCC_D2CCIP1R_SPI123SEL */

+#if defined(RCC_D2CCIP1R_SPI45SEL)

+#define LL_RCC_SPI45_CLKSOURCE           LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL,  RCC_D2CCIP1R_SPI45SEL_Pos,  0x00000000U)

+#else

+#define LL_RCC_SPI45_CLKSOURCE           LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL,  RCC_CDCCIP1R_SPI45SEL_Pos,  0x00000000U)

+#endif /* RCC_D2CCIP1R_SPI45SEL */

+#if defined(RCC_D3CCIPR_SPI6SEL)

+#define LL_RCC_SPI6_CLKSOURCE            LL_CLKSOURCE(D3CCIP,  RCC_D3CCIPR_SPI6SEL,    RCC_D3CCIPR_SPI6SEL_Pos,    0x00000000U)

+#else

+#define LL_RCC_SPI6_CLKSOURCE            LL_CLKSOURCE(SRDCCIP,  RCC_SRDCCIPR_SPI6SEL,   RCC_SRDCCIPR_SPI6SEL_Pos,  0x00000000U)

+#endif /* RCC_D3CCIPR_SPI6SEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_SPDIF_CLKSOURCE  Peripheral SPDIF get clock source

+  * @{

+  */

+#if defined(RCC_D2CCIP1R_SPDIFSEL)

+#define LL_RCC_SPDIF_CLKSOURCE           RCC_D2CCIP1R_SPDIFSEL

+#else

+#define LL_RCC_SPDIF_CLKSOURCE           RCC_CDCCIP1R_SPDIFSEL

+#endif /* RCC_D2CCIP1R_SPDIFSEL */

+/**

+  * @}

+  */

+

+#if defined(FDCAN1) || defined(FDCAN2)

+/** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE  Peripheral FDCAN get clock source

+  * @{

+  */

+#if defined(RCC_D2CCIP1R_FDCANSEL)

+#define LL_RCC_FDCAN_CLKSOURCE           RCC_D2CCIP1R_FDCANSEL

+#else

+#define LL_RCC_FDCAN_CLKSOURCE           RCC_CDCCIP1R_FDCANSEL

+#endif

+/**

+  * @}

+  */

+#endif /*FDCAN1 || FDCAN2*/

+

+/** @defgroup RCC_LL_EC_SWP_CLKSOURCE  Peripheral SWP get clock source

+  * @{

+  */

+#if defined(RCC_D2CCIP1R_SWPSEL)

+#define LL_RCC_SWP_CLKSOURCE             RCC_D2CCIP1R_SWPSEL

+#else

+#define LL_RCC_SWP_CLKSOURCE             RCC_CDCCIP1R_SWPSEL

+#endif /* RCC_D2CCIP1R_SWPSEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_ADC_CLKSOURCE  Peripheral ADC get clock source

+  * @{

+  */

+#if defined(RCC_D3CCIPR_ADCSEL)

+#define LL_RCC_ADC_CLKSOURCE             RCC_D3CCIPR_ADCSEL

+#else

+#define LL_RCC_ADC_CLKSOURCE             RCC_SRDCCIPR_ADCSEL

+#endif /* RCC_D3CCIPR_ADCSEL */

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_RTC_CLKSOURCE  RTC clock source selection

+  * @{

+  */

+#define LL_RCC_RTC_CLKSOURCE_NONE          (uint32_t)(0x00000000U)

+#define LL_RCC_RTC_CLKSOURCE_LSE           (uint32_t)(RCC_BDCR_RTCSEL_0)

+#define LL_RCC_RTC_CLKSOURCE_LSI           (uint32_t)(RCC_BDCR_RTCSEL_1)

+#define LL_RCC_RTC_CLKSOURCE_HSE           (uint32_t)(RCC_BDCR_RTCSEL_0 | RCC_BDCR_RTCSEL_1)

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_TIM_CLKPRESCALER  Timers clocks prescalers selection

+  * @{

+  */

+#define LL_RCC_TIM_PRESCALER_TWICE          (uint32_t)(0x00000000U)

+#define LL_RCC_TIM_PRESCALER_FOUR_TIMES     (uint32_t)(RCC_CFGR_TIMPRE)

+/**

+  * @}

+  */

+

+#if defined(HRTIM1)

+/** @defgroup RCC_LL_EC_HRTIM_CLKSOURCE  High Resolution Timers clock selection

+  * @{

+  */

+#define LL_RCC_HRTIM_CLKSOURCE_TIM          (uint32_t)(0x00000000U)           /* HRTIM Clock source is same as other timers */

+#define LL_RCC_HRTIM_CLKSOURCE_CPU          (uint32_t)(RCC_CFGR_HRTIMSEL)     /* HRTIM Clock source is the CPU clock */

+/**

+  * @}

+  */

+#endif /* HRTIM1 */

+

+/** @defgroup RCC_LL_EC_PLLSOURCE   All PLLs entry clock source

+  * @{

+  */

+#define LL_RCC_PLLSOURCE_HSI               RCC_PLLCKSELR_PLLSRC_HSI

+#define LL_RCC_PLLSOURCE_CSI               RCC_PLLCKSELR_PLLSRC_CSI

+#define LL_RCC_PLLSOURCE_HSE               RCC_PLLCKSELR_PLLSRC_HSE

+#define LL_RCC_PLLSOURCE_NONE              RCC_PLLCKSELR_PLLSRC_NONE

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_PLLINPUTRANGE   All PLLs input range

+  * @{

+  */

+#define LL_RCC_PLLINPUTRANGE_1_2           (uint32_t)(0x00000000U)

+#define LL_RCC_PLLINPUTRANGE_2_4           (uint32_t)(0x00000001)

+#define LL_RCC_PLLINPUTRANGE_4_8           (uint32_t)(0x00000002)

+#define LL_RCC_PLLINPUTRANGE_8_16          (uint32_t)(0x00000003)

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EC_PLLVCORANGE   All PLLs VCO range

+  * @{

+  */

+#define LL_RCC_PLLVCORANGE_WIDE            (uint32_t)(0x00000000U)      /* VCO output range: 192 to 836 MHz   OR  128 to 544 MHz (*) */

+#define LL_RCC_PLLVCORANGE_MEDIUM          (uint32_t)(0x00000001)       /* VCO output range: 150 to 420 MHz */

+/**

+  * (*) : For stm32h7a3xx and stm32h7b3xx family lines.

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros

+  * @{

+  */

+

+/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros

+  * @{

+  */

+

+/**

+  * @brief  Write a value in RCC register

+  * @param  __REG__ Register to be written

+  * @param  __VALUE__ Value to be written in the register

+  * @retval None

+  */

+#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))

+

+/**

+  * @brief  Read a value in RCC register

+  * @param  __REG__ Register to be read

+  * @retval Register value

+  */

+#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies

+  * @{

+  */

+

+/**

+  * @brief  Helper macro to calculate the SYSCLK frequency

+  * @param  __SYSINPUTCLKFREQ__ Frequency of the input of sys_ck (based on HSE/CSI/HSI/PLL1P)

+  * @param  __SYSPRESCALER__ This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_SYSCLK_DIV_1

+  *         @arg @ref LL_RCC_SYSCLK_DIV_2

+  *         @arg @ref LL_RCC_SYSCLK_DIV_4

+  *         @arg @ref LL_RCC_SYSCLK_DIV_8

+  *         @arg @ref LL_RCC_SYSCLK_DIV_16

+  *         @arg @ref LL_RCC_SYSCLK_DIV_64

+  *         @arg @ref LL_RCC_SYSCLK_DIV_128

+  *         @arg @ref LL_RCC_SYSCLK_DIV_256

+  *         @arg @ref LL_RCC_SYSCLK_DIV_512

+  * @retval SYSCLK clock frequency (in Hz)

+  */

+#if defined(RCC_D1CFGR_D1CPRE)

+#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_D1CFGR_D1CPRE) >>  RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU))

+#else

+#define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU))

+#endif /* RCC_D1CFGR_D1CPRE */

+

+/**

+  * @brief  Helper macro to calculate the HCLK frequency

+  * @param  __SYSCLKFREQ__ SYSCLK frequency.

+  * @param  __HPRESCALER__ This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_AHB_DIV_1

+  *         @arg @ref LL_RCC_AHB_DIV_2

+  *         @arg @ref LL_RCC_AHB_DIV_4

+  *         @arg @ref LL_RCC_AHB_DIV_8

+  *         @arg @ref LL_RCC_AHB_DIV_16

+  *         @arg @ref LL_RCC_AHB_DIV_64

+  *         @arg @ref LL_RCC_AHB_DIV_128

+  *         @arg @ref LL_RCC_AHB_DIV_256

+  *         @arg @ref LL_RCC_AHB_DIV_512

+  * @retval HCLK clock frequency (in Hz)

+  */

+#if defined(RCC_D1CFGR_HPRE)

+#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_D1CFGR_HPRE) >>  RCC_D1CFGR_HPRE_Pos]) & 0x1FU))

+#else

+#define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_CDCFGR1_HPRE) >>  RCC_CDCFGR1_HPRE_Pos]) & 0x1FU))

+#endif  /* RCC_D1CFGR_HPRE */

+

+/**

+  * @brief  Helper macro to calculate the PCLK1 frequency (ABP1)

+  * @param  __HCLKFREQ__ HCLK frequency

+  * @param  __APB1PRESCALER__ This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_APB1_DIV_1

+  *         @arg @ref LL_RCC_APB1_DIV_2

+  *         @arg @ref LL_RCC_APB1_DIV_4

+  *         @arg @ref LL_RCC_APB1_DIV_8

+  *         @arg @ref LL_RCC_APB1_DIV_16

+  * @retval PCLK1 clock frequency (in Hz)

+  */

+#if defined(RCC_D2CFGR_D2PPRE1)

+#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_D2CFGR_D2PPRE1) >>  RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU))

+#else

+#define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_CDCFGR2_CDPPRE1) >>  RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU))

+#endif /* RCC_D2CFGR_D2PPRE1 */

+

+/**

+  * @brief  Helper macro to calculate the PCLK2 frequency (ABP2)

+  * @param  __HCLKFREQ__ HCLK frequency

+  * @param  __APB2PRESCALER__ This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_APB2_DIV_1

+  *         @arg @ref LL_RCC_APB2_DIV_2

+  *         @arg @ref LL_RCC_APB2_DIV_4

+  *         @arg @ref LL_RCC_APB2_DIV_8

+  *         @arg @ref LL_RCC_APB2_DIV_16

+  * @retval PCLK2 clock frequency (in Hz)

+  */

+#if defined(RCC_D2CFGR_D2PPRE2)

+#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_D2CFGR_D2PPRE2) >>  RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU))

+#else

+#define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU))

+#endif /* RCC_D2CFGR_D2PPRE2 */

+

+/**

+  * @brief  Helper macro to calculate the PCLK3 frequency (APB3)

+  * @param  __HCLKFREQ__ HCLK frequency

+  * @param  __APB3PRESCALER__ This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_APB3_DIV_1

+  *         @arg @ref LL_RCC_APB3_DIV_2

+  *         @arg @ref LL_RCC_APB3_DIV_4

+  *         @arg @ref LL_RCC_APB3_DIV_8

+  *         @arg @ref LL_RCC_APB3_DIV_16

+  * @retval PCLK1 clock frequency (in Hz)

+  */

+#if defined(RCC_D1CFGR_D1PPRE)

+#define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_D1CFGR_D1PPRE) >>  RCC_D1CFGR_D1PPRE_Pos]) & 0x1FU))

+#else

+#define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_CDCFGR1_CDPPRE) >> RCC_CDCFGR1_CDPPRE_Pos]) & 0x1FU))

+#endif /* RCC_D1CFGR_D1PPRE */

+

+/**

+  * @brief  Helper macro to calculate the PCLK4 frequency (ABP4)

+  * @param  __HCLKFREQ__ HCLK frequency

+  * @param  __APB4PRESCALER__ This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_APB4_DIV_1

+  *         @arg @ref LL_RCC_APB4_DIV_2

+  *         @arg @ref LL_RCC_APB4_DIV_4

+  *         @arg @ref LL_RCC_APB4_DIV_8

+  *         @arg @ref LL_RCC_APB4_DIV_16

+  * @retval PCLK1 clock frequency (in Hz)

+  */

+#if defined(RCC_D3CFGR_D3PPRE)

+#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_D3CFGR_D3PPRE) >>  RCC_D3CFGR_D3PPRE_Pos]) & 0x1FU))

+#else

+#define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_SRDCFGR_SRDPPRE) >>  RCC_SRDCFGR_SRDPPRE_Pos]) & 0x1FU))

+#endif /* RCC_D3CFGR_D3PPRE */

+

+/**

+  * @}

+  */

+

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency

+  * @{

+  */

+#define LL_RCC_PERIPH_FREQUENCY_NO         0x00000000U                 /*!< No clock enabled for the peripheral            */

+#define LL_RCC_PERIPH_FREQUENCY_NA         0xFFFFFFFFU                 /*!< Frequency cannot be provided as external clock */

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions

+  * @{

+  */

+

+/** @defgroup RCC_LL_EF_HSE HSE

+  * @{

+  */

+

+/**

+  * @brief  Enable the Clock Security System.

+  * @note Once HSE Clock Security System is enabled it cannot be changed anymore unless

+  *       a reset occurs or system enter in standby mode.

+  * @rmtoll CR           CSSHSEON         LL_RCC_HSE_EnableCSS

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)

+{

+  SET_BIT(RCC->CR, RCC_CR_CSSHSEON);

+}

+

+/**

+  * @brief  Enable HSE external oscillator (HSE Bypass)

+  * @rmtoll CR           HSEBYP        LL_RCC_HSE_EnableBypass

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)

+{

+  SET_BIT(RCC->CR, RCC_CR_HSEBYP);

+}

+

+/**

+  * @brief  Disable HSE external oscillator (HSE Bypass)

+  * @rmtoll CR           HSEBYP        LL_RCC_HSE_DisableBypass

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)

+{

+  CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);

+}

+

+#if defined(RCC_CR_HSEEXT)

+/**

+  * @brief  Select the Analog HSE external clock type in Bypass mode

+  * @rmtoll CR           HSEEXT        LL_RCC_HSE_SelectAnalogClock

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_HSE_SelectAnalogClock(void)

+{

+  CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);

+}

+

+/**

+  * @brief  Select the Digital HSE external clock type in Bypass mode

+  * @rmtoll CR           HSEEXT        LL_RCC_HSE_SelectDigitalClock

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_HSE_SelectDigitalClock(void)

+{

+  SET_BIT(RCC->CR, RCC_CR_HSEEXT);

+}

+#endif /* RCC_CR_HSEEXT */

+

+/**

+  * @brief  Enable HSE crystal oscillator (HSE ON)

+  * @rmtoll CR           HSEON         LL_RCC_HSE_Enable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_HSE_Enable(void)

+{

+  SET_BIT(RCC->CR, RCC_CR_HSEON);

+}

+

+/**

+  * @brief  Disable HSE crystal oscillator (HSE ON)

+  * @rmtoll CR           HSEON         LL_RCC_HSE_Disable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_HSE_Disable(void)

+{

+  CLEAR_BIT(RCC->CR, RCC_CR_HSEON);

+}

+

+/**

+  * @brief  Check if HSE oscillator Ready

+  * @rmtoll CR           HSERDY        LL_RCC_HSE_IsReady

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)

+{

+  return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY))?1UL:0UL);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EF_HSI HSI

+  * @{

+  */

+

+/**

+  * @brief  Enable HSI oscillator

+  * @rmtoll CR           HSION         LL_RCC_HSI_Enable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_HSI_Enable(void)

+{

+  SET_BIT(RCC->CR, RCC_CR_HSION);

+}

+

+/**

+  * @brief  Disable HSI oscillator

+  * @rmtoll CR           HSION         LL_RCC_HSI_Disable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_HSI_Disable(void)

+{

+  CLEAR_BIT(RCC->CR, RCC_CR_HSION);

+}

+

+/**

+  * @brief  Check if HSI clock is ready

+  * @rmtoll CR           HSIRDY        LL_RCC_HSI_IsReady

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)

+{

+  return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if HSI new divider applied and ready

+  * @rmtoll CR           HSIDIVF        LL_RCC_HSI_IsDividerReady

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_HSI_IsDividerReady(void)

+{

+  return ((READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == (RCC_CR_HSIDIVF))?1UL:0UL);

+}

+

+/**

+  * @brief  Set HSI divider

+  * @rmtoll CR           HSIDIV        LL_RCC_HSI_SetDivider

+  * @param  Divider This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_HSI_DIV1

+  *         @arg @ref LL_RCC_HSI_DIV2

+  *         @arg @ref LL_RCC_HSI_DIV4

+  *         @arg @ref LL_RCC_HSI_DIV8

+  * @retval None.

+  */

+__STATIC_INLINE void LL_RCC_HSI_SetDivider(uint32_t Divider)

+{

+  MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, Divider);

+}

+

+/**

+  * @brief  Get HSI divider

+  * @rmtoll CR           HSIDIV        LL_RCC_HSI_GetDivider

+  * @retval can be one of the following values:

+  *         @arg @ref LL_RCC_HSI_DIV1

+  *         @arg @ref LL_RCC_HSI_DIV2

+  *         @arg @ref LL_RCC_HSI_DIV4

+  *         @arg @ref LL_RCC_HSI_DIV8

+  */

+__STATIC_INLINE uint32_t LL_RCC_HSI_GetDivider(void)

+{

+  return (READ_BIT(RCC->CR, RCC_CR_HSIDIV));

+}

+

+/**

+  * @brief  Enable HSI oscillator in Stop mode

+  * @rmtoll CR           HSIKERON         LL_RCC_HSI_EnableStopMode

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_HSI_EnableStopMode(void)

+{

+  SET_BIT(RCC->CR, RCC_CR_HSIKERON);

+}

+

+/**

+  * @brief  Disable HSI oscillator in Stop mode

+  * @rmtoll CR           HSION         LL_RCC_HSI_DisableStopMode

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_HSI_DisableStopMode(void)

+{

+  CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);

+}

+

+/**

+  * @brief  Get HSI Calibration value

+  * @note When HSITRIM is written, HSICAL is updated with the sum of

+  *       HSITRIM and the factory trim value

+  * @rmtoll HSICFGR        HSICAL        LL_RCC_HSI_GetCalibration

+  * @retval A value between 0 and 4095 (0xFFF)

+  */

+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)

+{

+  return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSICAL) >> RCC_HSICFGR_HSICAL_Pos);

+}

+

+/**

+  * @brief  Set HSI Calibration trimming

+  * @note user-programmable trimming value that is added to the HSICAL

+  * @note Default value is 64 (32 for Cut1.x), which, when added to the HSICAL value,

+  *       should trim the HSI to 64 MHz +/- 1 %

+  * @rmtoll HSICFGR        HSITRIM       LL_RCC_HSI_SetCalibTrimming

+  * @param  Parameter can be a value between 0 and 127 (63 for Cut1.x)

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)

+{

+#if defined(RCC_VER_X)

+  if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)

+  {

+    /* STM32H7 Rev.Y */

+    MODIFY_REG(RCC->HSICFGR, 0x3F000U, Value << 12U);

+  }

+  else

+  {

+    /* STM32H7 Rev.V */

+    MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos);

+  }

+#else

+    MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos);

+#endif /* RCC_VER_X */

+}

+

+/**

+  * @brief  Get HSI Calibration trimming

+  * @rmtoll HSICFGR        HSITRIM       LL_RCC_HSI_GetCalibTrimming

+  * @retval A value between 0 and 127 (63 for Cut1.x)

+  */

+__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)

+{

+#if defined(RCC_VER_X)

+  if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)

+  {

+    /* STM32H7 Rev.Y */

+    return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x3F000U) >> 12U);

+  }

+  else

+  {

+    /* STM32H7 Rev.V */

+    return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);

+  }

+#else

+    return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);

+#endif /* RCC_VER_X */

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EF_CSI CSI

+  * @{

+  */

+

+/**

+  * @brief  Enable CSI oscillator

+  * @rmtoll CR           CSION         LL_RCC_CSI_Enable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_CSI_Enable(void)

+{

+  SET_BIT(RCC->CR, RCC_CR_CSION);

+}

+

+/**

+  * @brief  Disable CSI oscillator

+  * @rmtoll CR           CSION         LL_RCC_CSI_Disable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_CSI_Disable(void)

+{

+  CLEAR_BIT(RCC->CR, RCC_CR_CSION);

+}

+

+/**

+  * @brief  Check if CSI clock is ready

+  * @rmtoll CR           CSIRDY        LL_RCC_CSI_IsReady

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_CSI_IsReady(void)

+{

+  return ((READ_BIT(RCC->CR, RCC_CR_CSIRDY) == (RCC_CR_CSIRDY))?1UL:0UL);

+}

+

+/**

+  * @brief  Enable CSI oscillator in Stop mode

+  * @rmtoll CR           CSIKERON         LL_RCC_CSI_EnableStopMode

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_CSI_EnableStopMode(void)

+{

+  SET_BIT(RCC->CR, RCC_CR_CSIKERON);

+}

+

+/**

+  * @brief  Disable CSI oscillator in Stop mode

+  * @rmtoll CR           CSIKERON         LL_RCC_CSI_DisableStopMode

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_CSI_DisableStopMode(void)

+{

+  CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON);

+}

+

+/**

+  * @brief  Get CSI Calibration value

+  * @note When CSITRIM is written, CSICAL is updated with the sum of

+  *       CSITRIM and the factory trim value

+  * @rmtoll CSICFGR        CSICAL        LL_RCC_CSI_GetCalibration

+  * @retval A value between 0 and 255 (0xFF)

+  */

+__STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibration(void)

+{

+#if defined(RCC_VER_X)

+  if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)

+  {

+    /* STM32H7 Rev.Y */

+    return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x3FC0000U) >> 18U);

+  }

+  else

+  {

+    /* STM32H7 Rev.V */

+    return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos);

+  }

+#else

+    return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos);

+#endif /* RCC_VER_X */

+}

+

+/**

+  * @brief  Set CSI Calibration trimming

+  * @note user-programmable trimming value that is added to the CSICAL

+  * @note Default value is 16, which, when added to the CSICAL value,

+  *       should trim the CSI to 4 MHz +/- 1 %

+  * @rmtoll CSICFGR        CSITRIM       LL_RCC_CSI_SetCalibTrimming

+  * @param  Value can be a value between 0 and 31

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_CSI_SetCalibTrimming(uint32_t Value)

+{

+#if defined(RCC_VER_X)

+  if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)

+  {

+    /* STM32H7 Rev.Y */

+    MODIFY_REG(RCC->HSICFGR, 0x7C000000U, Value << 26U);

+  }

+  else

+  {

+    /* STM32H7 Rev.V */

+    MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos);

+  }

+#else

+    MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos);

+#endif /* RCC_VER_X */

+}

+

+/**

+  * @brief  Get CSI Calibration trimming

+  * @rmtoll CSICFGR        CSITRIM       LL_RCC_CSI_GetCalibTrimming

+  * @retval A value between 0 and 31

+  */

+__STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibTrimming(void)

+{

+#if defined(RCC_VER_X)

+  if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)

+  {

+    /* STM32H7 Rev.Y */

+    return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x7C000000U) >> 26U);

+  }

+  else

+  {

+    /* STM32H7 Rev.V */

+    return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);

+  }

+#else

+    return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);

+#endif /* RCC_VER_X */

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EF_HSI48 HSI48

+  * @{

+  */

+

+/**

+  * @brief  Enable HSI48 oscillator

+  * @rmtoll CR           HSI48ON         LL_RCC_HSI48_Enable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_HSI48_Enable(void)

+{

+  SET_BIT(RCC->CR, RCC_CR_HSI48ON);

+}

+

+/**

+  * @brief  Disable HSI48 oscillator

+  * @rmtoll CR           HSI48ON         LL_RCC_HSI48_Disable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_HSI48_Disable(void)

+{

+  CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);

+}

+

+/**

+  * @brief  Check if HSI48 clock is ready

+  * @rmtoll CR           HSI48RDY        LL_RCC_HSI48_IsReady

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)

+{

+  return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == (RCC_CR_HSI48RDY))?1UL:0UL);

+}

+

+/**

+  * @brief  Get HSI48 Calibration value

+  * @note When HSI48TRIM is written, HSI48CAL is updated with the sum of

+  *       HSI48TRIM and the factory trim value

+  * @rmtoll CRRCR        HSI48CAL        LL_RCC_HSI48_GetCalibration

+  * @retval A value between 0 and 1023 (0x3FF)

+  */

+__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)

+{

+  return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);

+}

+/**

+  * @}

+  */

+

+#if defined(RCC_CR_D1CKRDY)

+

+/** @defgroup RCC_LL_EF_D1CLK D1CKREADY

+  * @{

+  */

+

+/**

+  * @brief  Check if D1 clock is ready

+  * @rmtoll CR           D1CKRDY        LL_RCC_D1CK_IsReady

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_D1CK_IsReady(void)

+{

+  return ((READ_BIT(RCC->CR, RCC_CR_D1CKRDY) == (RCC_CR_D1CKRDY))?1UL:0UL);

+}

+

+/**

+  * @}

+  */

+#else

+

+/** @defgroup RCC_LL_EF_CPUCLK CPUCKREADY

+  * @{

+  */

+

+/**

+  * @brief  Check if CPU clock is ready

+  * @rmtoll CR           CPUCKRDY        LL_RCC_CPUCK_IsReady

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_CPUCK_IsReady(void)

+{

+  return ((READ_BIT(RCC->CR, RCC_CR_CPUCKRDY) == (RCC_CR_CPUCKRDY))?1UL:0UL);

+}

+ /* alias */

+#define LL_RCC_D1CK_IsReady  LL_RCC_CPUCK_IsReady

+/**

+  * @}

+  */

+#endif /* RCC_CR_D1CKRDY */

+

+#if defined(RCC_CR_D2CKRDY)

+

+/** @defgroup RCC_LL_EF_D2CLK D2CKREADY

+  * @{

+  */

+

+/**

+  * @brief  Check if D2 clock is ready

+  * @rmtoll CR           D2CKRDY        LL_RCC_D2CK_IsReady

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_D2CK_IsReady(void)

+{

+  return ((READ_BIT(RCC->CR, RCC_CR_D2CKRDY) == (RCC_CR_D2CKRDY))?1UL:0UL);

+}

+/**

+  * @}

+  */

+#else

+

+/** @defgroup RCC_LL_EF_CDCLK CDCKREADY

+  * @{

+  */

+

+/**

+  * @brief  Check if CD clock is ready

+  * @rmtoll CR           CDCKRDY        LL_RCC_CDCK_IsReady

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_CDCK_IsReady(void)

+{

+  return ((READ_BIT(RCC->CR, RCC_CR_CDCKRDY) == (RCC_CR_CDCKRDY))?1UL:0UL);

+}

+#define LL_RCC_D2CK_IsReady LL_RCC_CDCK_IsReady

+/**

+  * @}

+  */

+#endif /* RCC_CR_D2CKRDY */

+

+/** @defgroup RCC_LL_EF_SYSTEM_WIDE_RESET RESET

+  * @{

+  */

+#if defined(RCC_GCR_WW1RSC)

+

+/**

+  * @brief  Enable system wide reset for Window Watch Dog 1

+  * @rmtoll GCR          WW1RSC        LL_RCC_WWDG1_EnableSystemReset

+  * @retval None.

+  */

+__STATIC_INLINE void LL_RCC_WWDG1_EnableSystemReset(void)

+{

+  SET_BIT(RCC->GCR, RCC_GCR_WW1RSC);

+}

+

+/**

+  * @brief  Check if Window Watch Dog 1 reset is system wide

+  * @rmtoll GCR          WW1RSC        LL_RCC_WWDG1_IsSystemReset

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_WWDG1_IsSystemReset(void)

+{

+  return ((READ_BIT(RCC->GCR, RCC_GCR_WW1RSC) == RCC_GCR_WW1RSC)?1UL:0UL);

+}

+#endif  /* RCC_GCR_WW1RSC */

+

+#if defined(DUAL_CORE)

+/**

+  * @brief  Enable system wide reset for Window Watch Dog 2

+  * @rmtoll GCR          WW1RSC        LL_RCC_WWDG2_EnableSystemReset

+  * @retval None.

+  */

+__STATIC_INLINE void LL_RCC_WWDG2_EnableSystemReset(void)

+{

+  SET_BIT(RCC->GCR, RCC_GCR_WW2RSC);

+}

+

+/**

+  * @brief  Check if Window Watch Dog 2 reset is system wide

+  * @rmtoll GCR          WW2RSC        LL_RCC_WWDG2_IsSystemReset

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_WWDG2_IsSystemReset(void)

+{

+  return ((READ_BIT(RCC->GCR, RCC_GCR_WW2RSC) == RCC_GCR_WW2RSC)?1UL:0UL);

+}

+#endif  /*DUAL_CORE*/

+/**

+  * @}

+  */

+

+#if defined(DUAL_CORE)

+/** @defgroup RCC_LL_EF_BOOT_CPU CPU

+  * @{

+  */

+

+/**

+  * @brief  Force CM4 boot (if hold by option byte BCM4 = 0)

+  * @rmtoll GCR          BOOT_C2        LL_RCC_ForceCM4Boot

+  * @retval None.

+  */

+__STATIC_INLINE void LL_RCC_ForceCM4Boot(void)

+{

+  SET_BIT(RCC->GCR, RCC_GCR_BOOT_C2);

+}

+

+/**

+  * @brief  Check if CM4 boot is forced

+  * @rmtoll GCR          BOOT_C2        LL_RCC_IsCM4BootForced

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsCM4BootForced(void)

+{

+  return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C2) == RCC_GCR_BOOT_C2)?1UL:0UL);

+}

+

+/**

+  * @brief  Force CM7 boot (if hold by option byte BCM7 = 0)

+  * @rmtoll GCR          BOOT_C1        LL_RCC_ForceCM7Boot

+  * @retval None.

+  */

+__STATIC_INLINE void LL_RCC_ForceCM7Boot(void)

+{

+  SET_BIT(RCC->GCR, RCC_GCR_BOOT_C1);

+}

+

+/**

+  * @brief  Check if CM7 boot is forced

+  * @rmtoll GCR          BOOT_C1        LL_RCC_IsCM7BootForced

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsCM7BootForced(void)

+{

+  return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C1) == RCC_GCR_BOOT_C1)?1UL:0UL);

+}

+

+/**

+  * @}

+  */

+#endif  /*DUAL_CORE*/

+

+/** @defgroup RCC_LL_EF_LSE LSE

+  * @{

+  */

+

+/**

+  * @brief  Enable the Clock Security System on LSE.

+  * @note Once LSE Clock Security System is enabled it cannot be changed anymore unless

+  *       a clock failure is detected.

+  * @rmtoll BDCR          LSECSSON         LL_RCC_LSE_EnableCSS

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)

+{

+  SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);

+}

+

+/**

+  * @brief  Check if LSE failure is detected by Clock Security System

+  * @rmtoll BDCR         LSECSSD       LL_RCC_LSE_IsFailureDetected

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_LSE_IsFailureDetected(void)

+{

+  return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD))?1UL:0UL);

+}

+

+/**

+  * @brief  Enable  Low Speed External (LSE) crystal.

+  * @rmtoll BDCR         LSEON         LL_RCC_LSE_Enable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_LSE_Enable(void)

+{

+  SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);

+}

+

+/**

+  * @brief  Disable  Low Speed External (LSE) crystal.

+  * @rmtoll BDCR         LSEON         LL_RCC_LSE_Disable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_LSE_Disable(void)

+{

+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);

+}

+

+/**

+  * @brief  Enable external clock source (LSE bypass).

+  * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_EnableBypass

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)

+{

+  SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);

+}

+

+/**

+  * @brief  Disable external clock source (LSE bypass).

+  * @rmtoll BDCR         LSEBYP        LL_RCC_LSE_DisableBypass

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)

+{

+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);

+}

+

+#if defined(RCC_BDCR_LSEEXT)

+/**

+  * @brief  Enable Low-speed external DIGITAL clock type in Bypass mode (not to be used if RTC is active).

+  * @note   The external clock must be enabled with the LSEON bit, to be used by the device.

+  *         The LSEEXT bit can be written only if the LSE oscillator is disabled.

+  * @rmtoll BDCR         LSEEXT        LL_RCC_LSE_SelectDigitalClock

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_LSE_SelectDigitalClock(void)

+{

+  SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);

+}

+

+/**

+  * @brief  Enable Low-speed external ANALOG clock type in Bypass mode (default after Backup domain reset).

+  * @note   The external clock must be enabled with the LSEON bit, to be used by the device.

+  *         The LSEEXT bit can be written only if the LSE oscillator is disabled.

+  * @rmtoll BDCR         LSEEXT        LL_RCC_LSE_SelectAnalogClock

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_LSE_SelectAnalogClock(void)

+{

+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);

+}

+#endif /* RCC_BDCR_LSEEXT */

+

+/**

+  * @brief  Set LSE oscillator drive capability

+  * @note The oscillator is in Xtal mode when it is not in bypass mode.

+  * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_SetDriveCapability

+  * @param  LSEDrive This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_LSEDRIVE_LOW

+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW

+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH

+  *         @arg @ref LL_RCC_LSEDRIVE_HIGH

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)

+{

+  MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);

+}

+

+/**

+  * @brief  Get LSE oscillator drive capability

+  * @rmtoll BDCR         LSEDRV        LL_RCC_LSE_GetDriveCapability

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_LSEDRIVE_LOW

+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW

+  *         @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH

+  *         @arg @ref LL_RCC_LSEDRIVE_HIGH

+  */

+__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)

+{

+  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));

+}

+

+/**

+  * @brief  Check if LSE oscillator Ready

+  * @rmtoll BDCR         LSERDY        LL_RCC_LSE_IsReady

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)

+{

+  return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY))?1UL:0UL);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EF_LSI LSI

+  * @{

+  */

+

+/**

+  * @brief  Enable LSI Oscillator

+  * @rmtoll CSR          LSION         LL_RCC_LSI_Enable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_LSI_Enable(void)

+{

+  SET_BIT(RCC->CSR, RCC_CSR_LSION);

+}

+

+/**

+  * @brief  Disable LSI Oscillator

+  * @rmtoll CSR          LSION         LL_RCC_LSI_Disable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_LSI_Disable(void)

+{

+  CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);

+}

+

+/**

+  * @brief  Check if LSI is Ready

+  * @rmtoll CSR          LSIRDY        LL_RCC_LSI_IsReady

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)

+{

+  return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY))?1UL:0UL);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EF_System System

+  * @{

+  */

+

+/**

+  * @brief  Configure the system clock source

+  * @rmtoll CFGR         SW            LL_RCC_SetSysClkSource

+  * @param  Source This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_CSI

+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_HSE

+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_PLL1

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)

+{

+  MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);

+}

+

+/**

+  * @brief  Get the system clock source

+  * @rmtoll CFGR         SWS           LL_RCC_GetSysClkSource

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI

+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_CSI

+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE

+  *         @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL1

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)

+{

+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));

+}

+

+/**

+  * @brief  Configure the system wakeup clock source

+  * @rmtoll CFGR         STOPWUCK       LL_RCC_SetSysWakeUpClkSource

+  * @param  Source This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetSysWakeUpClkSource(uint32_t Source)

+{

+  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Source);

+}

+

+/**

+  * @brief  Get the system wakeup clock source

+  * @rmtoll CFGR         STOPWUCK           LL_RCC_GetSysWakeUpClkSource

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetSysWakeUpClkSource(void)

+{

+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));

+}

+

+/**

+  * @brief  Configure the kernel wakeup clock source

+  * @rmtoll CFGR         STOPKERWUCK       LL_RCC_SetKerWakeUpClkSource

+  * @param  Source This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetKerWakeUpClkSource(uint32_t Source)

+{

+  MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, Source);

+}

+

+/**

+  * @brief  Get the kernel wakeup clock source

+  * @rmtoll CFGR         STOPKERWUCK           LL_RCC_GetKerWakeUpClkSource

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetKerWakeUpClkSource(void)

+{

+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPKERWUCK));

+}

+

+/**

+  * @brief  Set System prescaler

+  * @rmtoll D1CFGR/CDCFGR1        D1CPRE/CDCPRE          LL_RCC_SetSysPrescaler

+  * @param  Prescaler This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_SYSCLK_DIV_1

+  *         @arg @ref LL_RCC_SYSCLK_DIV_2

+  *         @arg @ref LL_RCC_SYSCLK_DIV_4

+  *         @arg @ref LL_RCC_SYSCLK_DIV_8

+  *         @arg @ref LL_RCC_SYSCLK_DIV_16

+  *         @arg @ref LL_RCC_SYSCLK_DIV_64

+  *         @arg @ref LL_RCC_SYSCLK_DIV_128

+  *         @arg @ref LL_RCC_SYSCLK_DIV_256

+  *         @arg @ref LL_RCC_SYSCLK_DIV_512

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetSysPrescaler(uint32_t Prescaler)

+{

+#if defined(RCC_D1CFGR_D1CPRE)

+  MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, Prescaler);

+#else

+  MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, Prescaler);

+#endif /* RCC_D1CFGR_D1CPRE */

+}

+

+/**

+  * @brief  Set AHB prescaler

+  * @rmtoll D1CFGR/CDCFGR1        HPRE         LL_RCC_SetAHBPrescaler

+  * @param  Prescaler This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_AHB_DIV_1

+  *         @arg @ref LL_RCC_AHB_DIV_2

+  *         @arg @ref LL_RCC_AHB_DIV_4

+  *         @arg @ref LL_RCC_AHB_DIV_8

+  *         @arg @ref LL_RCC_AHB_DIV_16

+  *         @arg @ref LL_RCC_AHB_DIV_64

+  *         @arg @ref LL_RCC_AHB_DIV_128

+  *         @arg @ref LL_RCC_AHB_DIV_256

+  *         @arg @ref LL_RCC_AHB_DIV_512

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)

+{

+#if defined(RCC_D1CFGR_HPRE)

+  MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, Prescaler);

+#else

+  MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, Prescaler);

+#endif /* RCC_D1CFGR_HPRE */

+}

+

+/**

+  * @brief  Set APB1 prescaler

+  * @rmtoll D2CFGR/CDCFGR2         D2PPRE1/CDPPRE1         LL_RCC_SetAPB1Prescaler

+  * @param  Prescaler This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_APB1_DIV_1

+  *         @arg @ref LL_RCC_APB1_DIV_2

+  *         @arg @ref LL_RCC_APB1_DIV_4

+  *         @arg @ref LL_RCC_APB1_DIV_8

+  *         @arg @ref LL_RCC_APB1_DIV_16

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)

+{

+#if defined(RCC_D2CFGR_D2PPRE1)

+  MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, Prescaler);

+#else

+  MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, Prescaler);

+#endif /* RCC_D2CFGR_D2PPRE1 */

+}

+

+/**

+  * @brief  Set APB2 prescaler

+  * @rmtoll D2CFGR/CDCFGR2         D2PPRE2/CDPPRE2         LL_RCC_SetAPB2Prescaler

+  * @param  Prescaler This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_APB2_DIV_1

+  *         @arg @ref LL_RCC_APB2_DIV_2

+  *         @arg @ref LL_RCC_APB2_DIV_4

+  *         @arg @ref LL_RCC_APB2_DIV_8

+  *         @arg @ref LL_RCC_APB2_DIV_16

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)

+{

+#if defined(RCC_D2CFGR_D2PPRE2)

+  MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, Prescaler);

+#else

+  MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, Prescaler);

+#endif /* RCC_D2CFGR_D2PPRE2 */

+}

+

+/**

+  * @brief  Set APB3 prescaler

+  * @rmtoll D1CFGR/CDCFGR1         D1PPRE/CDPPRE         LL_RCC_SetAPB3Prescaler

+  * @param  Prescaler This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_APB3_DIV_1

+  *         @arg @ref LL_RCC_APB3_DIV_2

+  *         @arg @ref LL_RCC_APB3_DIV_4

+  *         @arg @ref LL_RCC_APB3_DIV_8

+  *         @arg @ref LL_RCC_APB3_DIV_16

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetAPB3Prescaler(uint32_t Prescaler)

+{

+#if defined(RCC_D1CFGR_D1PPRE)

+  MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, Prescaler);

+#else

+  MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, Prescaler);

+#endif /* RCC_D1CFGR_D1PPRE */

+}

+

+/**

+  * @brief  Set APB4 prescaler

+  * @rmtoll D3CFGR/SRDCFGR         D3PPRE/SRDPPRE         LL_RCC_SetAPB4Prescaler

+  * @param  Prescaler This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_APB4_DIV_1

+  *         @arg @ref LL_RCC_APB4_DIV_2

+  *         @arg @ref LL_RCC_APB4_DIV_4

+  *         @arg @ref LL_RCC_APB4_DIV_8

+  *         @arg @ref LL_RCC_APB4_DIV_16

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetAPB4Prescaler(uint32_t Prescaler)

+{

+#if defined(RCC_D3CFGR_D3PPRE)

+  MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, Prescaler);

+#else

+  MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, Prescaler);

+#endif /* RCC_D3CFGR_D3PPRE */

+}

+

+/**

+  * @brief  Get System prescaler

+  * @rmtoll D1CFGR/CDCFGR1        D1CPRE/CDCPRE          LL_RCC_GetSysPrescaler

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_SYSCLK_DIV_1

+  *         @arg @ref LL_RCC_SYSCLK_DIV_2

+  *         @arg @ref LL_RCC_SYSCLK_DIV_4

+  *         @arg @ref LL_RCC_SYSCLK_DIV_8

+  *         @arg @ref LL_RCC_SYSCLK_DIV_16

+  *         @arg @ref LL_RCC_SYSCLK_DIV_64

+  *         @arg @ref LL_RCC_SYSCLK_DIV_128

+  *         @arg @ref LL_RCC_SYSCLK_DIV_256

+  *         @arg @ref LL_RCC_SYSCLK_DIV_512

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetSysPrescaler(void)

+{

+#if defined(RCC_D1CFGR_D1CPRE)

+  return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1CPRE));

+#else

+  return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE));

+#endif /* RCC_D1CFGR_D1CPRE */

+}

+

+/**

+  * @brief  Get AHB prescaler

+  * @rmtoll D1CFGR/ CDCFGR1       HPRE         LL_RCC_GetAHBPrescaler

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_AHB_DIV_1

+  *         @arg @ref LL_RCC_AHB_DIV_2

+  *         @arg @ref LL_RCC_AHB_DIV_4

+  *         @arg @ref LL_RCC_AHB_DIV_8

+  *         @arg @ref LL_RCC_AHB_DIV_16

+  *         @arg @ref LL_RCC_AHB_DIV_64

+  *         @arg @ref LL_RCC_AHB_DIV_128

+  *         @arg @ref LL_RCC_AHB_DIV_256

+  *         @arg @ref LL_RCC_AHB_DIV_512

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)

+{

+#if defined(RCC_D1CFGR_HPRE)

+  return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_HPRE));

+#else

+  return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_HPRE));

+#endif /* RCC_D1CFGR_HPRE */

+}

+

+/**

+  * @brief  Get APB1 prescaler

+  * @rmtoll D2CFGR/CDCFGR2         D2PPRE1/CDPPRE1         LL_RCC_GetAPB1Prescaler

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_APB1_DIV_1

+  *         @arg @ref LL_RCC_APB1_DIV_2

+  *         @arg @ref LL_RCC_APB1_DIV_4

+  *         @arg @ref LL_RCC_APB1_DIV_8

+  *         @arg @ref LL_RCC_APB1_DIV_16

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)

+{

+#if defined(RCC_D2CFGR_D2PPRE1)

+  return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1));

+#else

+  return (uint32_t)(READ_BIT(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1));

+#endif /* RCC_D2CFGR_D2PPRE1 */

+}

+

+/**

+  * @brief  Get APB2 prescaler

+  * @rmtoll D2CFGR/CDCFGR2         D2PPRE2/CDPPRE2         LL_RCC_GetAPB2Prescaler

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_APB2_DIV_1

+  *         @arg @ref LL_RCC_APB2_DIV_2

+  *         @arg @ref LL_RCC_APB2_DIV_4

+  *         @arg @ref LL_RCC_APB2_DIV_8

+  *         @arg @ref LL_RCC_APB2_DIV_16

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)

+{

+#if defined(RCC_D2CFGR_D2PPRE2)

+  return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2));

+#else

+  return (uint32_t)(READ_BIT(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2));

+#endif /* RCC_D2CFGR_D2PPRE2 */

+}

+

+/**

+  * @brief  Get APB3 prescaler

+  * @rmtoll D1CFGR/CDCFGR1         D1PPRE/CDPPRE         LL_RCC_GetAPB3Prescaler

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_APB3_DIV_1

+  *         @arg @ref LL_RCC_APB3_DIV_2

+  *         @arg @ref LL_RCC_APB3_DIV_4

+  *         @arg @ref LL_RCC_APB3_DIV_8

+  *         @arg @ref LL_RCC_APB3_DIV_16

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetAPB3Prescaler(void)

+{

+#if defined(RCC_D1CFGR_D1PPRE)

+  return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1PPRE));

+#else

+  return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE));

+#endif /* RCC_D1CFGR_D1PPRE */

+}

+

+/**

+  * @brief  Get APB4 prescaler

+  * @rmtoll D3CFGR/SRDCFGR         D3PPRE/SRDPPRE         LL_RCC_GetAPB4Prescaler

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_APB4_DIV_1

+  *         @arg @ref LL_RCC_APB4_DIV_2

+  *         @arg @ref LL_RCC_APB4_DIV_4

+  *         @arg @ref LL_RCC_APB4_DIV_8

+  *         @arg @ref LL_RCC_APB4_DIV_16

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetAPB4Prescaler(void)

+{

+#if defined(RCC_D3CFGR_D3PPRE)

+  return (uint32_t)(READ_BIT(RCC->D3CFGR, RCC_D3CFGR_D3PPRE));

+#else

+  return (uint32_t)(READ_BIT(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE));

+#endif /* RCC_D3CFGR_D3PPRE */

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EF_MCO MCO

+  * @{

+  */

+

+/**

+  * @brief  Configure MCOx

+  * @rmtoll CFGR         MCO1          LL_RCC_ConfigMCO\n

+  *         CFGR         MCO1PRE       LL_RCC_ConfigMCO\n

+  *         CFGR         MCO2          LL_RCC_ConfigMCO\n

+  *         CFGR         MCO2PRE       LL_RCC_ConfigMCO

+  * @param  MCOxSource This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_MCO1SOURCE_HSI

+  *         @arg @ref LL_RCC_MCO1SOURCE_LSE

+  *         @arg @ref LL_RCC_MCO1SOURCE_HSE

+  *         @arg @ref LL_RCC_MCO1SOURCE_PLL1QCLK

+  *         @arg @ref LL_RCC_MCO1SOURCE_HSI48

+  *         @arg @ref LL_RCC_MCO2SOURCE_SYSCLK

+  *         @arg @ref LL_RCC_MCO2SOURCE_PLL2PCLK

+  *         @arg @ref LL_RCC_MCO2SOURCE_HSE

+  *         @arg @ref LL_RCC_MCO2SOURCE_PLL1PCLK

+  *         @arg @ref LL_RCC_MCO2SOURCE_CSI

+  *         @arg @ref LL_RCC_MCO2SOURCE_LSI

+  * @param  MCOxPrescaler This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_MCO1_DIV_1

+  *         @arg @ref LL_RCC_MCO1_DIV_2

+  *         @arg @ref LL_RCC_MCO1_DIV_3

+  *         @arg @ref LL_RCC_MCO1_DIV_4

+  *         @arg @ref LL_RCC_MCO1_DIV_5

+  *         @arg @ref LL_RCC_MCO1_DIV_6

+  *         @arg @ref LL_RCC_MCO1_DIV_7

+  *         @arg @ref LL_RCC_MCO1_DIV_8

+  *         @arg @ref LL_RCC_MCO1_DIV_9

+  *         @arg @ref LL_RCC_MCO1_DIV_10

+  *         @arg @ref LL_RCC_MCO1_DIV_11

+  *         @arg @ref LL_RCC_MCO1_DIV_12

+  *         @arg @ref LL_RCC_MCO1_DIV_13

+  *         @arg @ref LL_RCC_MCO1_DIV_14

+  *         @arg @ref LL_RCC_MCO1_DIV_15

+  *         @arg @ref LL_RCC_MCO2_DIV_1

+  *         @arg @ref LL_RCC_MCO2_DIV_2

+  *         @arg @ref LL_RCC_MCO2_DIV_3

+  *         @arg @ref LL_RCC_MCO2_DIV_4

+  *         @arg @ref LL_RCC_MCO2_DIV_5

+  *         @arg @ref LL_RCC_MCO2_DIV_6

+  *         @arg @ref LL_RCC_MCO2_DIV_7

+  *         @arg @ref LL_RCC_MCO2_DIV_8

+  *         @arg @ref LL_RCC_MCO2_DIV_9

+  *         @arg @ref LL_RCC_MCO2_DIV_10

+  *         @arg @ref LL_RCC_MCO2_DIV_11

+  *         @arg @ref LL_RCC_MCO2_DIV_12

+  *         @arg @ref LL_RCC_MCO2_DIV_13

+  *         @arg @ref LL_RCC_MCO2_DIV_14

+  *         @arg @ref LL_RCC_MCO2_DIV_15

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)

+{

+  MODIFY_REG(RCC->CFGR,  (MCOxSource << 16U) | (MCOxPrescaler << 16U), (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source

+  * @{

+  */

+

+/**

+  * @brief  Configure periph clock source

+  * @rmtoll D2CCIP1R/CDCCIP1R        *     LL_RCC_SetClockSource\n

+  *         D2CCIP2R/CDCCIP2R        *     LL_RCC_SetClockSource\n

+  *         D3CCIPR/SRDCCIPR         *     LL_RCC_SetClockSource

+  * @param  ClkSource This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2

+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q

+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q

+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_CSI

+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_LSE

+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1

+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q

+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q

+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI

+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE

+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1

+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R

+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI

+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4

+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R

+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI

+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1

+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P

+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R

+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE

+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI

+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP

+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4

+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P

+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R

+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE

+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI

+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP

+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4

+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P

+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R

+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE

+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI

+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP

+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q

+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P

+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P

+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN

+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP

+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q

+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P

+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P

+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN

+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP

+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)

+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P  (*)

+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P  (*)

+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN  (*)

+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q  (*)

+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P  (*)

+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P  (*)

+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN  (*)

+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP  (*)

+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF  (*)

+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q  (*)

+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)

+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)

+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)

+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)

+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)

+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)

+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)

+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)

+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)

+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF  (*)

+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q

+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P

+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P

+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN

+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP

+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2

+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q

+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q

+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI

+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE

+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4

+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q

+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q

+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI

+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE

+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetClockSource(uint32_t ClkSource)

+{

+#if defined(RCC_D1CCIPR_FMCSEL)

+  register uint32_t * pReg = (uint32_t *)((uint32_t)&RCC->D1CCIPR + LL_CLKSOURCE_REG(ClkSource));

+#else

+  register uint32_t * pReg = (uint32_t *)((uint32_t)&RCC->CDCCIPR + LL_CLKSOURCE_REG(ClkSource));

+#endif /*  */

+  MODIFY_REG(*pReg, LL_CLKSOURCE_MASK(ClkSource), LL_CLKSOURCE_CONFIG(ClkSource));

+}

+

+/**

+  * @brief  Configure USARTx clock source

+  * @rmtoll D2CCIP2R / D2CCIP2R        USART16SEL     LL_RCC_SetUSARTClockSource\n

+  *         D2CCIP2R / D2CCIP2R        USART28SEL     LL_RCC_SetUSARTClockSource

+  * @param  ClkSource This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2

+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q

+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q

+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_CSI

+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_LSE

+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1

+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q

+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q

+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI

+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t ClkSource)

+{

+  LL_RCC_SetClockSource(ClkSource);

+}

+

+/**

+  * @brief  Configure LPUARTx clock source

+  * @rmtoll D3CCIPR / SRDCCIPR        LPUART1SEL     LL_RCC_SetLPUARTClockSource

+  * @param  ClkSource This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4

+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q

+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q

+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI

+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t ClkSource)

+{

+#if defined(RCC_D3CCIPR_LPUART1SEL)

+  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, ClkSource);

+#else

+  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, ClkSource);

+#endif /* RCC_D3CCIPR_LPUART1SEL */

+}

+

+/**

+  * @brief  Configure I2Cx clock source

+  * @rmtoll D2CCIP2R / CDCCIP2R       I2C123SEL       LL_RCC_SetI2CClockSource\n

+  *         D3CCIPR / SRDCCIPR        I2C4SEL         LL_RCC_SetI2CClockSource

+  * @param  ClkSource This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1

+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R

+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI

+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4

+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R

+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t ClkSource)

+{

+  LL_RCC_SetClockSource(ClkSource);

+}

+

+/**

+  * @brief  Configure LPTIMx clock source

+  * @rmtoll D2CCIP2R / CDCCIP2R      LPTIM1SEL     LL_RCC_SetLPTIMClockSource

+  *         D3CCIPR  / SRDCCIPR      LPTIM2SEL     LL_RCC_SetLPTIMClockSource\n

+  *         D3CCIPR  / SRDCCIPR      LPTIM345SEL   LL_RCC_SetLPTIMClockSource

+  * @param  ClkSource This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1

+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P

+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R

+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE

+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI

+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP

+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4

+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P

+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R

+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE

+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI

+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP

+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4

+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P

+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R

+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE

+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI

+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t ClkSource)

+{

+  LL_RCC_SetClockSource(ClkSource);

+}

+

+/**

+  * @brief  Configure SAIx clock source

+  * @rmtoll D2CCIP1R / CDCCIP1R       SAI1SEL       LL_RCC_SetSAIClockSource\n

+  *         D2CCIP1R / CDCCIP1R       SAI23SEL      LL_RCC_SetSAIClockSource

+  *         D3CCIPR  / SRDCCIPR       SAI4ASEL      LL_RCC_SetSAI4xClockSource\n

+  *         D3CCIPR  / SRDCCIPR       SAI4BSEL      LL_RCC_SetSAI4xClockSource

+  * @param  ClkSource This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q

+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P

+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P

+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN

+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP

+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q

+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P

+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P

+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN

+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP

+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)

+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P  (*)

+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P  (*)

+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN  (*)

+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q  (*)

+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P  (*)

+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P  (*)

+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN  (*)

+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP  (*)

+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF  (*)

+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q  (*)

+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)

+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)

+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)

+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)

+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)

+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)

+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)

+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)

+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)

+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF  (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t ClkSource)

+{

+  LL_RCC_SetClockSource(ClkSource);

+}

+

+/**

+  * @brief  Configure SDMMCx clock source

+  * @rmtoll D1CCIPR / CDCCIPR       SDMMCSEL      LL_RCC_SetSDMMCClockSource

+  * @param  ClkSource This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL1Q

+  *         @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2R

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t ClkSource)

+{

+#if defined(RCC_D1CCIPR_SDMMCSEL)

+  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, ClkSource);

+#else

+  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, ClkSource);

+#endif /* RCC_D1CCIPR_SDMMCSEL */

+}

+

+/**

+  * @brief  Configure RNGx clock source

+  * @rmtoll D2CCIP2R / CDCCIP2R       RNGSEL      LL_RCC_SetRNGClockSource

+  * @param  ClkSource This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48

+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q

+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSE

+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSI

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t ClkSource)

+{

+#if defined(RCC_D2CCIP2R_RNGSEL)

+  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, ClkSource);

+#else

+  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, ClkSource);

+#endif /* RCC_D2CCIP2R_RNGSEL */

+}

+

+/**

+  * @brief  Configure USBx clock source

+  * @rmtoll D2CCIP2R / CDCCIP2R      USBSEL      LL_RCC_SetUSBClockSource

+  * @param  ClkSource This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_USB_CLKSOURCE_DISABLE

+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q

+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q

+  *         @arg @ref LL_RCC_USB_CLKSOURCE_HSI48

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t ClkSource)

+{

+#if defined(RCC_D2CCIP2R_USBSEL)

+  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, ClkSource);

+#else

+  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, ClkSource);

+#endif /* RCC_D2CCIP2R_USBSEL */

+}

+

+/**

+  * @brief  Configure CECx clock source

+  * @rmtoll D2CCIP2R / CDCCIP2R         CECSEL        LL_RCC_SetCECClockSource

+  * @param  ClkSource This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE

+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSI

+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t ClkSource)

+{

+#if defined(RCC_D2CCIP2R_CECSEL)

+  MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, ClkSource);

+#else

+  MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL, ClkSource);

+#endif /* RCC_D2CCIP2R_CECSEL */

+}

+

+#if defined(DSI)

+/**

+  * @brief  Configure DSIx clock source

+  * @rmtoll D1CCIPR         DSISEL        LL_RCC_SetDSIClockSource

+  * @param  ClkSource This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY

+  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL2Q

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t ClkSource)

+{

+  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, ClkSource);

+}

+#endif /* DSI */

+

+/**

+  * @brief  Configure DFSDMx Kernel clock source

+  * @rmtoll D2CCIP1R / CDCCIP1R         DFSDM1SEL        LL_RCC_SetDFSDMClockSource

+  * @param  ClkSource This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2

+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t ClkSource)

+{

+#if defined(RCC_D2CCIP1R_DFSDM1SEL)

+  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, ClkSource);

+#else

+  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, ClkSource);

+#endif /* RCC_D2CCIP1R_DFSDM1SEL */

+}

+

+#if defined(DFSDM2_BASE)

+/**

+  * @brief  Configure DFSDMx Kernel clock source

+  * @rmtoll SRDCCIPR                   DFSDM2SEL        LL_RCC_SetDFSDM2ClockSource

+  * @param  ClkSource This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK2

+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetDFSDM2ClockSource(uint32_t ClkSource)

+{

+   MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, ClkSource);

+}

+#endif /* DFSDM2 */

+

+/**

+  * @brief  Configure FMCx Kernel clock source

+  * @rmtoll D1CCIPR / CDCCIPR        FMCSEL        LL_RCC_SetFMCClockSource

+  * @param  ClkSource This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK

+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q

+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R

+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetFMCClockSource(uint32_t ClkSource)

+{

+#if defined(RCC_D1CCIPR_FMCSEL)

+  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, ClkSource);

+#else

+  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, ClkSource);

+#endif /* RCC_D1CCIPR_FMCSEL */

+}

+

+#if defined(QUADSPI)

+/**

+  * @brief  Configure QSPIx Kernel clock source

+  * @rmtoll D1CCIPR         QSPISEL        LL_RCC_SetQSPIClockSource

+  * @param  ClkSource This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_HCLK

+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL1Q

+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL2R

+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_CLKP

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetQSPIClockSource(uint32_t ClkSource)

+{

+  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, ClkSource);

+}

+#endif /* QUADSPI */

+

+#if defined(OCTOSPI1) || defined(OCTOSPI2)

+/**

+  * @brief  Configure OSPIx Kernel clock source

+  * @rmtoll D1CCIPR         OPISEL        LL_RCC_SetOSPIClockSource

+  * @param  ClkSource This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK

+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q

+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R

+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetOSPIClockSource(uint32_t ClkSource)

+{

+  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, ClkSource);

+}

+#endif /* OCTOSPI1 || OCTOSPI2 */

+

+/**

+  * @brief  Configure CLKP Kernel clock source

+  * @rmtoll D1CCIPR / CDCCIPR         CKPERSEL        LL_RCC_SetCLKPClockSource

+  * @param  ClkSource This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI

+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetCLKPClockSource(uint32_t ClkSource)

+{

+#if defined(RCC_D1CCIPR_CKPERSEL)

+  MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, ClkSource);

+#else

+  MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, ClkSource);

+#endif /* RCC_D1CCIPR_CKPERSEL */

+}

+

+/**

+  * @brief  Configure SPIx Kernel clock source

+  * @rmtoll D2CCIP1R / CDCCIP1R       SPI123SEL        LL_RCC_SetSPIClockSource\n

+  *         D2CCIP1R / CDCCIP1R       SPI45SEL         LL_RCC_SetSPIClockSource\n

+  *         D3CCIPR  / SRDCCIPR       SPI6SEL          LL_RCC_SetSPIClockSource

+  * @param  ClkSource This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q

+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P

+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P

+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN

+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP

+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2

+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q

+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q

+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI

+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE

+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4

+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q

+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q

+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI

+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE

+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t ClkSource)

+{

+  LL_RCC_SetClockSource(ClkSource);

+}

+

+/**

+  * @brief  Configure SPDIFx Kernel clock source

+  * @rmtoll D2CCIP1R / CDCCIP1R       SPDIFSEL        LL_RCC_SetSPDIFClockSource

+  * @param  ClkSource This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL1Q

+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL2R

+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL3R

+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_HSI

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetSPDIFClockSource(uint32_t ClkSource)

+{

+#if defined(RCC_D2CCIP1R_SPDIFSEL)

+  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, ClkSource);

+#else

+  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, ClkSource);

+#endif /* RCC_D2CCIP1R_SPDIFSEL */

+}

+

+/**

+  * @brief  Configure FDCANx Kernel clock source

+  * @rmtoll D2CCIP1R / CDCCIP1R      FDCANSEL        LL_RCC_SetFDCANClockSource

+  * @param  ClkSource This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE

+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q

+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t ClkSource)

+{

+#if defined(RCC_D2CCIP1R_FDCANSEL)

+  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, ClkSource);

+#else

+  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, ClkSource);

+#endif /* RCC_D2CCIP1R_FDCANSEL */

+}

+

+/**

+  * @brief  Configure SWPx Kernel clock source

+  * @rmtoll D2CCIP1R /  CDCCIP1R       SWPSEL        LL_RCC_SetSWPClockSource

+  * @param  ClkSource This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_SWP_CLKSOURCE_PCLK1

+  *         @arg @ref LL_RCC_SWP_CLKSOURCE_HSI

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetSWPClockSource(uint32_t ClkSource)

+{

+#if defined(RCC_D2CCIP1R_SWPSEL)

+  MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, ClkSource);

+#else

+  MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, ClkSource);

+#endif /* RCC_D2CCIP1R_SWPSEL */

+}

+

+/**

+  * @brief  Configure ADCx Kernel clock source

+  * @rmtoll D3CCIPR / SRDCCIPR        ADCSEL        LL_RCC_SetADCClockSource

+  * @param  ClkSource This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P

+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R

+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ClkSource)

+{

+#if defined(RCC_D3CCIPR_ADCSEL)

+  MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, ClkSource);

+#else

+  MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, ClkSource);

+#endif /* RCC_D3CCIPR_ADCSEL */

+}

+

+/**

+  * @brief  Get periph clock source

+  * @rmtoll D1CCIPR  / CDCCIPR       *     LL_RCC_GetClockSource\n

+  *         D2CCIP1R / CDCCIP1R      *     LL_RCC_GetClockSource\n

+  *         D2CCIP2R / CDCCIP2R      *     LL_RCC_GetClockSource\n

+  *         D3CCIPR  / SRDCCIPR      *     LL_RCC_GetClockSource

+  * @param  Periph This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_USART16_CLKSOURCE

+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE

+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE

+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE

+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE

+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE

+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE

+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE

+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE

+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE (*)

+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE (*)

+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE (*)

+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE (*)

+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE (*)

+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE (*)

+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE (*)

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2

+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q

+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q

+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_CSI

+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_LSE

+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1

+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q

+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q

+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI

+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE

+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1

+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R

+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI

+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4

+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R

+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI

+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1

+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P

+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R

+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE

+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI

+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP

+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4

+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P

+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R

+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE

+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI

+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP

+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4

+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P

+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R

+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE

+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI

+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP

+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q

+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P

+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P

+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN

+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP

+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)

+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)

+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)

+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)

+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)

+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)

+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)

+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)

+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)

+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP (*)

+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*)

+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)

+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)

+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)

+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)

+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)

+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)

+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)

+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*)

+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*)

+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)

+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)

+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)

+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)

+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)

+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)

+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)

+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q

+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P

+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P

+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN

+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP

+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2

+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q

+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q

+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI

+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE

+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4

+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q

+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q

+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI

+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE

+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)

+  *

+  *         (*) value not defined in all devices.

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph)

+{

+#if defined(RCC_D1CCIPR_FMCSEL)

+  register const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->D1CCIPR) + LL_CLKSOURCE_REG(Periph)));

+#else

+  register const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->CDCCIPR) + LL_CLKSOURCE_REG(Periph)));

+#endif /* RCC_D1CCIPR_FMCSEL */

+  return (uint32_t) (Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> LL_CLKSOURCE_SHIFT(Periph)) << LL_RCC_CONFIG_SHIFT) );

+}

+

+/**

+  * @brief  Get USARTx clock source

+  * @rmtoll D2CCIP2R / CDCCIP2R      USART16SEL     LL_RCC_GetUSARTClockSource\n

+  *         D2CCIP2R / CDCCIP2R      USART28SEL     LL_RCC_GetUSARTClockSource

+  * @param  Periph This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_USART16_CLKSOURCE

+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2

+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q

+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q

+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_CSI

+  *         @arg @ref LL_RCC_USART16_CLKSOURCE_LSE

+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1

+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q

+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q

+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI

+  *         @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t Periph)

+{

+  return LL_RCC_GetClockSource(Periph);

+}

+

+/**

+  * @brief  Get LPUART clock source

+  * @rmtoll D3CCIPR / SRDCCIPR       LPUART1SEL     LL_RCC_GetLPUARTClockSource

+  * @param  Periph This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4

+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q

+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q

+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI

+  *         @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t Periph)

+{

+  UNUSED(Periph);

+#if defined(RCC_D3CCIPR_LPUART1SEL)

+  return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL));

+#else

+  return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL));

+#endif  /* RCC_D3CCIPR_LPUART1SEL */

+}

+

+/**

+  * @brief  Get I2Cx clock source

+  * @rmtoll D2CCIP2R / CDCCIP2R     I2C123SEL       LL_RCC_GetI2CClockSource\n

+  *         D3CCIPR  / SRDCCIPR     I2C4SEL         LL_RCC_GetI2CClockSource

+  * @param  Periph This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE

+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1

+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R

+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI

+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4

+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R

+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t Periph)

+{

+  return LL_RCC_GetClockSource(Periph);

+}

+

+/**

+  * @brief  Get LPTIM clock source

+  * @rmtoll D2CCIP2R / CDCCIP2R      LPTIM1SEL     LL_RCC_GetLPTIMClockSource\n

+  *         D3CCIPR  / SRDCCIPR      LPTIM2SEL     LL_RCC_GetLPTIMClockSource\n

+  *         D3CCIPR  / SRDCCIPR      LPTIM345SEL   LL_RCC_GetLPTIMClockSource

+  * @param  Perihp This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE

+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE

+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1

+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P

+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R

+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE

+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI

+  *         @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP

+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4

+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P

+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R

+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE

+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI

+  *         @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP

+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4

+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P

+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R

+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE

+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI

+  *         @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP

+  * @retval None

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t Periph)

+{

+  return LL_RCC_GetClockSource(Periph);

+}

+

+/**

+  * @brief  Get SAIx clock source

+  * @rmtoll D2CCIP1R / CDCCIP1R     SAI1SEL       LL_RCC_GetSAIClockSource\n

+  *         D2CCIP1R / CDCCIP1R     SAI23SEL      LL_RCC_GetSAIClockSource

+  *         D3CCIPR  / SRDCCIPR     SAI4ASEL      LL_RCC_GetSAIClockSource\n

+  *         D3CCIPR  / SRDCCIPR     SAI4BSEL      LL_RCC_GetSAIClockSource

+  * @param  Periph This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE

+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE

+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE

+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q

+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P

+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P

+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN

+  *         @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP

+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)

+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)

+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)

+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)

+  *         @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)

+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)

+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)

+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)

+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*)

+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*)

+  *         @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF (*)

+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)

+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)

+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)

+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)

+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)

+  *         @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)

+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)

+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)

+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)

+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)

+  *         @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP (*)

+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*)

+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)

+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)

+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)

+  *         @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)

+  * 

+  *  (*) value not defined in all devices.

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t Periph)

+{

+  return LL_RCC_GetClockSource(Periph);

+}

+

+/**

+  * @brief  Get SDMMC clock source

+  * @rmtoll D1CCIPR / CDCCIPR      SDMMCSEL      LL_RCC_GetSDMMCClockSource

+  * @param  Periph This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_SDMMC_CLKSOURCE

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL1Q

+  *         @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2R

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t Periph)

+{

+  UNUSED(Periph);

+#if defined(RCC_D1CCIPR_SDMMCSEL)

+  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL));

+#else

+  return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL));

+#endif /* RCC_D1CCIPR_SDMMCSEL */

+}

+

+/**

+  * @brief  Get RNG clock source

+  * @rmtoll D2CCIP2R        RNGSEL      LL_RCC_GetRNGClockSource

+  * @param  Periph This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_RNG_CLKSOURCE

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48

+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q

+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSE

+  *         @arg @ref LL_RCC_RNG_CLKSOURCE_LSI

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t Periph)

+{

+  UNUSED(Periph);

+#if defined(RCC_D2CCIP2R_RNGSEL)

+  return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL));

+#else

+  return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL));

+#endif /* RCC_D2CCIP2R_RNGSEL */

+}

+

+/**

+  * @brief  Get USB clock source

+  * @rmtoll D2CCIP2R / CDCCIP2R      USBSEL      LL_RCC_GetUSBClockSource

+  * @param  Periph This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_USB_CLKSOURCE

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_USB_CLKSOURCE_DISABLE

+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q

+  *         @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q

+  *         @arg @ref LL_RCC_USB_CLKSOURCE_HSI48

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t Periph)

+{

+  UNUSED(Periph);

+#if defined(RCC_D2CCIP2R_USBSEL)

+  return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL));

+#else

+  return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL));

+#endif /* RCC_D2CCIP2R_USBSEL */

+}

+

+/**

+  * @brief  Get CEC clock source

+  * @rmtoll D2CCIP2R / CDCCIP2R        CECSEL        LL_RCC_GetCECClockSource

+  * @param  Periph This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_CEC_CLKSOURCE

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSE

+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_LSI

+  *         @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t Periph)

+{

+  UNUSED(Periph);

+#if defined(RCC_D2CCIP2R_CECSEL)

+  return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL));

+#else

+  return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL));

+#endif  /* RCC_D2CCIP2R_CECSEL */

+}

+

+#if defined(DSI)

+/**

+  * @brief  Get DSI clock source

+  * @rmtoll D1CCIPR         DSISEL        LL_RCC_GetDSIClockSource

+  * @param  Periph This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_DSI_CLKSOURCE

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PHY

+  *         @arg @ref LL_RCC_DSI_CLKSOURCE_PLL2Q

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t Periph)

+{

+  UNUSED(Periph);

+  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL));

+}

+#endif /* DSI */

+

+/**

+  * @brief  Get DFSDM Kernel clock source

+  * @rmtoll D2CCIP1R / CDCCIP1R         DFSDM1SEL        LL_RCC_GetDFSDMClockSource

+  * @param  Periph This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2

+  *         @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t Periph)

+{

+  UNUSED(Periph);

+#if defined(RCC_D2CCIP1R_DFSDM1SEL)

+  return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL));

+#else

+  return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL));

+#endif /* RCC_D2CCIP1R_DFSDM1SEL */

+}

+

+#if defined(DFSDM2_BASE)

+/**

+  * @brief  Get DFSDM2 Kernel clock source

+  * @rmtoll SRDCCIPR         DFSDM2SEL        LL_RCC_GetDFSDM2ClockSource

+  * @param  Periph This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK4

+  *         @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetDFSDM2ClockSource(uint32_t Periph)

+{

+  UNUSED(Periph);

+  return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL));

+}

+#endif /* DFSDM2_BASE */

+

+/**

+  * @brief  Get FMC Kernel clock source

+  * @rmtoll D1CCIPR / D1CCIPR         FMCSEL        LL_RCC_GetFMCClockSource

+  * @param  Periph This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_FMC_CLKSOURCE

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK

+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q

+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R

+  *         @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetFMCClockSource(uint32_t Periph)

+{

+  UNUSED(Periph);

+#if defined(RCC_D1CCIPR_FMCSEL)

+  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL));

+#else

+  return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL));

+#endif /* RCC_D1CCIPR_FMCSEL */

+}

+

+#if defined(QUADSPI)

+/**

+  * @brief  Get QSPI Kernel clock source

+  * @rmtoll D1CCIPR / CDCCIPR      QSPISEL        LL_RCC_GetQSPIClockSource

+  * @param  Periph This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_HCLK

+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL1Q

+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL2R

+  *         @arg @ref LL_RCC_QSPI_CLKSOURCE_CLKP

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetQSPIClockSource(uint32_t Periph)

+{

+  UNUSED(Periph);

+  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL));

+}

+#endif /* QUADSPI */

+

+#if defined(OCTOSPI1) || defined(OCTOSPI2)

+/**

+  * @brief  Get OSPI Kernel clock source

+  * @rmtoll CDCCIPR      OSPISEL        LL_RCC_GetOSPIClockSource

+  * @param  Periph This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK

+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q

+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R

+  *         @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetOSPIClockSource(uint32_t Periph)

+{

+  UNUSED(Periph);

+  return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL));

+}

+#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */

+

+/**

+  * @brief  Get CLKP Kernel clock source

+  * @rmtoll D1CCIPR / CDCCIPR       CKPERSEL        LL_RCC_GetCLKPClockSource

+  * @param  Periph This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI

+  *         @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetCLKPClockSource(uint32_t Periph)

+{

+  UNUSED(Periph);

+#if defined(RCC_D1CCIPR_CKPERSEL)

+  return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL));

+#else

+  return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL));

+#endif /* RCC_D1CCIPR_CKPERSEL */

+}

+

+/**

+  * @brief  Get SPIx Kernel clock source

+  * @rmtoll D2CCIP1R / CDCCIP1R     SPI123SEL       LL_RCC_GetSPIClockSource\n

+  *         D2CCIP1R / CDCCIP1R     SPI45SEL        LL_RCC_GetSPIClockSource\n

+  *         D3CCIPR  / SRDCCIPR     SPI6SEL         LL_RCC_GetSPIClockSource

+  * @param  Periph This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE

+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE

+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q

+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P

+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P

+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN

+  *         @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP

+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2

+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q

+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q

+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI

+  *         @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE

+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4

+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q

+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q

+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI

+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI

+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE

+  *         @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)

+  *

+  *         (*) value not defined in all stm32h7xx lines.

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t Periph)

+{

+  return LL_RCC_GetClockSource(Periph);

+}

+

+/**

+  * @brief  Get SPDIF Kernel clock source

+  * @rmtoll D2CCIP1R / CDCCIP1R      SPDIFSEL        LL_RCC_GetSPDIFClockSource

+  * @param  Periph This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL1Q

+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL2R

+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL3R

+  *         @arg @ref LL_RCC_SPDIF_CLKSOURCE_HSI

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetSPDIFClockSource(uint32_t Periph)

+{

+  UNUSED(Periph);

+#if defined(RCC_D2CCIP1R_SPDIFSEL)

+  return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL));

+#else

+  return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL));

+#endif /* RCC_D2CCIP1R_SPDIFSEL */

+}

+

+/**

+  * @brief  Get FDCAN Kernel clock source

+  * @rmtoll D2CCIP1R / CDCCIP1R       FDCANSEL        LL_RCC_GetFDCANClockSource

+  * @param  Periph This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE

+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q

+  *         @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t Periph)

+{

+  UNUSED(Periph);

+#if defined(RCC_D2CCIP1R_FDCANSEL)

+  return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL));

+#else

+  return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL));

+#endif /* RCC_D2CCIP1R_FDCANSEL */

+}

+

+/**

+  * @brief  Get SWP Kernel clock source

+  * @rmtoll D2CCIP1R / CDCCIP1R       SWPSEL        LL_RCC_GetSWPClockSource

+  * @param  Periph This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_SWP_CLKSOURCE

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_SWP_CLKSOURCE_PCLK1

+  *         @arg @ref LL_RCC_SWP_CLKSOURCE_HSI

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetSWPClockSource(uint32_t Periph)

+{

+  UNUSED(Periph);

+#if defined(RCC_D2CCIP1R_SWPSEL)

+  return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL));

+#else

+  return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL));

+#endif /* RCC_D2CCIP1R_SWPSEL */

+}

+

+/**

+  * @brief  Get ADC Kernel clock source

+  * @rmtoll D3CCIPR / SRDCCIPR       ADCSEL        LL_RCC_GetADCClockSource

+  * @param  Periph This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_ADC_CLKSOURCE

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P

+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R

+  *         @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t Periph)

+{

+  UNUSED(Periph);

+#if defined (RCC_D3CCIPR_ADCSEL)

+  return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL));

+#else

+  return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL));

+#endif /* RCC_D3CCIPR_ADCSEL */

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EF_RTC RTC

+  * @{

+  */

+

+/**

+  * @brief  Set RTC Clock Source

+  * @note   Once the RTC clock source has been selected, it cannot be changed anymore unless

+  *         the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is

+  *         set). The BDRST bit can be used to reset them.

+  * @rmtoll BDCR         RTCSEL        LL_RCC_SetRTCClockSource

+  * @param  Source This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE

+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE

+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI

+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)

+{

+  MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);

+}

+

+/**

+  * @brief  Get RTC Clock Source

+  * @rmtoll BDCR         RTCSEL        LL_RCC_GetRTCClockSource

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_NONE

+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSE

+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_LSI

+  *         @arg @ref LL_RCC_RTC_CLKSOURCE_HSE

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)

+{

+  return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));

+}

+

+/**

+  * @brief  Enable RTC

+  * @rmtoll BDCR         RTCEN         LL_RCC_EnableRTC

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_EnableRTC(void)

+{

+  SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);

+}

+

+/**

+  * @brief  Disable RTC

+  * @rmtoll BDCR         RTCEN         LL_RCC_DisableRTC

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_DisableRTC(void)

+{

+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);

+}

+

+/**

+  * @brief  Check if RTC has been enabled or not

+  * @rmtoll BDCR         RTCEN         LL_RCC_IsEnabledRTC

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)

+{

+  return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN))?1UL:0UL);

+}

+

+/**

+  * @brief  Force the Backup domain reset

+  * @rmtoll BDCR         BDRST / VSWRST         LL_RCC_ForceBackupDomainReset

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)

+{

+  SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);

+}

+

+/**

+  * @brief  Release the Backup domain reset

+  * @rmtoll BDCR         BDRST / VSWRST          LL_RCC_ReleaseBackupDomainReset

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)

+{

+#if defined(RCC_BDCR_BDRST)

+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);

+#else

+  CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST);

+#endif /* RCC_BDCR_BDRST */

+}

+

+/**

+  * @brief  Set HSE Prescalers for RTC Clock

+  * @rmtoll CFGR         RTCPRE        LL_RCC_SetRTC_HSEPrescaler

+  * @param  Prescaler This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_RTC_NOCLOCK

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_2

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_3

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_4

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_5

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_6

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_7

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_8

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_9

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_10

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_11

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_12

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_13

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_14

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_15

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_16

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_17

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_18

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_19

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_20

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_21

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_22

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_23

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_24

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_25

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_26

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_27

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_28

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_29

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_30

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_31

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_32

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_33

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_34

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_35

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_36

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_37

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_38

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_39

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_40

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_41

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_42

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_43

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_44

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_45

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_46

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_47

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_48

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_49

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_50

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_51

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_52

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_53

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_54

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_55

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_56

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_57

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_58

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_59

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_60

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_61

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_62

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_63

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)

+{

+  MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);

+}

+

+/**

+  * @brief  Get HSE Prescalers for RTC Clock

+  * @rmtoll CFGR         RTCPRE        LL_RCC_GetRTC_HSEPrescaler

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_RTC_NOCLOCK

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_2

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_3

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_4

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_5

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_6

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_7

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_8

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_9

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_10

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_11

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_12

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_13

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_14

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_15

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_16

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_17

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_18

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_19

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_20

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_21

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_22

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_23

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_24

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_25

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_26

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_27

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_28

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_29

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_30

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_31

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_32

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_33

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_34

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_35

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_36

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_37

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_38

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_39

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_40

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_41

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_42

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_43

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_44

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_45

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_46

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_47

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_48

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_49

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_50

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_51

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_52

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_53

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_54

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_55

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_56

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_57

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_58

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_59

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_60

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_61

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_62

+  *         @arg @ref LL_RCC_RTC_HSE_DIV_63

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)

+{

+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM

+  * @{

+  */

+

+/**

+  * @brief  Set Timers Clock Prescalers

+  * @rmtoll CFGR         TIMPRE        LL_RCC_SetTIMPrescaler

+  * @param  Prescaler This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_TIM_PRESCALER_TWICE

+  *         @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)

+{

+  MODIFY_REG(RCC->CFGR, RCC_CFGR_TIMPRE, Prescaler);

+}

+

+/**

+  * @brief  Get Timers Clock Prescalers

+  * @rmtoll CFGR         TIMPRE        LL_RCC_GetTIMPrescaler

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_TIM_PRESCALER_TWICE

+  *         @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)

+{

+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_TIMPRE));

+}

+

+/**

+  * @}

+  */

+

+#if defined(HRTIM1)

+/** @defgroup RCC_LL_EF_HRTIM_SET_CLOCK_SOURCE HRTIM

+  * @{

+  */

+

+/**

+  * @brief  Set High Resolution Timers Clock Source

+  * @rmtoll CFGR         HRTIMSEL        LL_RCC_SetHRTIMClockSource

+  * @param  Prescaler This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_HRTIM_CLKSOURCE_TIM

+  *         @arg @ref LL_RCC_HRTIM_CLKSOURCE_CPU

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_SetHRTIMClockSource(uint32_t Prescaler)

+{

+  MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, Prescaler);

+}

+#endif /* HRTIM1 */

+

+#if defined(HRTIM1)

+/**

+  * @brief  Get High Resolution Timers Clock Source

+  * @rmtoll CFGR         HRTIMSEL        LL_RCC_GetHRTIMClockSource

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_HRTIM_CLKSOURCE_TIM

+  *         @arg @ref LL_RCC_HRTIM_CLKSOURCE_CPU

+  */

+__STATIC_INLINE uint32_t LL_RCC_GetHRTIMClockSource(void)

+{

+  return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL));

+}

+/**

+  * @}

+  */

+#endif /* HRTIM1 */

+

+/** @defgroup RCC_LL_EF_PLL PLL

+  * @{

+  */

+

+/**

+  * @brief  Set the oscillator used as PLL clock source.

+  * @note   PLLSRC can be written only when All PLLs are disabled.

+  * @rmtoll PLLCKSELR      PLLSRC        LL_RCC_PLL_SetSource

+  * @param  PLLSource parameter can be one of the following values:

+  *         @arg @ref LL_RCC_PLLSOURCE_HSI

+  *         @arg @ref LL_RCC_PLLSOURCE_CSI

+  *         @arg @ref LL_RCC_PLLSOURCE_HSE

+  *         @arg @ref LL_RCC_PLLSOURCE_NONE

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL_SetSource(uint32_t PLLSource)

+{

+  MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, PLLSource);

+}

+

+/**

+  * @brief  Get the oscillator used as PLL clock source.

+  * @rmtoll PLLCKSELR      PLLSRC        LL_RCC_PLL_GetSource

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RCC_PLLSOURCE_HSI

+  *         @arg @ref LL_RCC_PLLSOURCE_CSI

+  *         @arg @ref LL_RCC_PLLSOURCE_HSE

+  *         @arg @ref LL_RCC_PLLSOURCE_NONE

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL_GetSource(void)

+{

+  return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC));

+}

+

+/**

+  * @brief  Enable PLL1

+  * @rmtoll CR           PLL1ON         LL_RCC_PLL1_Enable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL1_Enable(void)

+{

+  SET_BIT(RCC->CR, RCC_CR_PLL1ON);

+}

+

+/**

+  * @brief  Disable PLL1

+  * @note Cannot be disabled if the PLL1 clock is used as the system clock

+  * @rmtoll CR           PLL1ON         LL_RCC_PLL1_Disable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL1_Disable(void)

+{

+  CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);

+}

+

+/**

+  * @brief  Check if PLL1 Ready

+  * @rmtoll CR           PLL1RDY        LL_RCC_PLL1_IsReady

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void)

+{

+  return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == (RCC_CR_PLL1RDY))?1UL:0UL);

+}

+

+/**

+  * @brief  Enable PLL1P

+  * @note   This API shall be called only when PLL1 is disabled.

+  * @rmtoll PLLCFGR           DIVP1EN         LL_RCC_PLL1P_Enable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL1P_Enable(void)

+{

+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN);

+}

+

+/**

+  * @brief  Enable PLL1Q

+  * @note   This API shall be called only when PLL1 is disabled.

+  * @rmtoll PLLCFGR           DIVQ1EN         LL_RCC_PLL1Q_Enable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL1Q_Enable(void)

+{

+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN);

+}

+

+/**

+  * @brief  Enable PLL1R

+  * @note   This API shall be called only when PLL1 is disabled.

+  * @rmtoll PLLCFGR           DIVR1EN         LL_RCC_PLL1R_Enable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL1R_Enable(void)

+{

+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN);

+}

+

+/**

+  * @brief  Enable PLL1 FRACN

+  * @rmtoll PLLCFGR           PLL1FRACEN         LL_RCC_PLL1FRACN_Enable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void)

+{

+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN);

+}

+

+/**

+  * @brief  Check if PLL1 P is enabled

+  * @rmtoll PLLCFGR           DIVP1EN         LL_RCC_PLL1P_IsEnabled

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL1P_IsEnabled(void)

+{

+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN) == RCC_PLLCFGR_DIVP1EN)?1UL:0UL);

+}

+

+/**

+  * @brief  Check if PLL1 Q is enabled

+  * @rmtoll PLLCFGR           DIVQ1EN         LL_RCC_PLL1Q_IsEnabled

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL1Q_IsEnabled(void)

+{

+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN) == RCC_PLLCFGR_DIVQ1EN)?1UL:0UL);

+}

+

+/**

+  * @brief  Check if PLL1 R is enabled

+  * @rmtoll PLLCFGR           DIVR1EN         LL_RCC_PLL1R_IsEnabled

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL1R_IsEnabled(void)

+{

+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN) == RCC_PLLCFGR_DIVR1EN)?1UL:0UL);

+}

+

+/**

+  * @brief  Check if PLL1 FRACN is enabled

+  * @rmtoll PLLCFGR           PLL1FRACEN         LL_RCC_PLL1FRACN_IsEnabled

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void)

+{

+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) == RCC_PLLCFGR_PLL1FRACEN)?1UL:0UL);

+}

+

+/**

+  * @brief  Disable PLL1P

+  * @note   This API shall be called only when PLL1 is disabled.

+  * @rmtoll PLLCFGR           DIVP1EN         LL_RCC_PLL1P_Disable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL1P_Disable(void)

+{

+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN);

+}

+

+/**

+  * @brief  Disable PLL1Q

+  * @note   This API shall be called only when PLL1 is disabled.

+  * @rmtoll PLLCFGR           DIVQ1EN         LL_RCC_PLL1Q_Disable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL1Q_Disable(void)

+{

+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN);

+}

+

+/**

+  * @brief  Disable PLL1R

+  * @note   This API shall be called only when PLL1 is disabled.

+  * @rmtoll PLLCFGR           DIVR1EN         LL_RCC_PLL1R_Disable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL1R_Disable(void)

+{

+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN);

+}

+

+/**

+  * @brief  Disable PLL1 FRACN

+  * @rmtoll PLLCFGR           PLL1FRACEN         LL_RCC_PLL1FRACN_Enable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL1FRACN_Disable(void)

+{

+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN);

+}

+

+/**

+  * @brief  Set PLL1 VCO OutputRange

+  * @note   This API shall be called only when PLL1 is disabled.

+  * @rmtoll PLLCFGR        PLL1VCOSEL       LL_RCC_PLL1_SetVCOOuputRange

+  * @param  VCORange This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_PLLVCORANGE_WIDE

+  *         @arg @ref LL_RCC_PLLVCORANGE_MEDIUM

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL1_SetVCOOutputRange(uint32_t VCORange)

+{

+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, VCORange << RCC_PLLCFGR_PLL1VCOSEL_Pos);

+}

+

+/**

+  * @brief  Set PLL1 VCO Input Range

+  * @note   This API shall be called only when PLL1 is disabled.

+  * @rmtoll PLLCFGR        PLL1RGE       LL_RCC_PLL1_SetVCOInputRange

+  * @param  InputRange This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_PLLINPUTRANGE_1_2

+  *         @arg @ref LL_RCC_PLLINPUTRANGE_2_4

+  *         @arg @ref LL_RCC_PLLINPUTRANGE_4_8

+  *         @arg @ref LL_RCC_PLLINPUTRANGE_8_16

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange)

+{

+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, InputRange << RCC_PLLCFGR_PLL1RGE_Pos);

+}

+

+/**

+  * @brief  Get PLL1 N Coefficient

+  * @rmtoll PLL1DIVR        N1          LL_RCC_PLL1_GetN

+  * @retval A value between 4 and 512

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void)

+{

+  return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_N1) >>  RCC_PLL1DIVR_N1_Pos) + 1UL);

+}

+

+/**

+  * @brief  Get PLL1 M Coefficient

+  * @rmtoll PLLCKSELR       DIVM1          LL_RCC_PLL1_GetM

+  * @retval A value between 0 and 63

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetM(void)

+{

+  return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1) >>  RCC_PLLCKSELR_DIVM1_Pos);

+}

+

+/**

+  * @brief  Get PLL1 P Coefficient

+  * @rmtoll PLL1DIVR        P1          LL_RCC_PLL1_GetP

+  * @retval A value between 2 and 128

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void)

+{

+  return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_P1) >>  RCC_PLL1DIVR_P1_Pos) + 1UL);

+}

+

+/**

+  * @brief  Get PLL1 Q Coefficient

+  * @rmtoll PLL1DIVR        Q1          LL_RCC_PLL1_GetQ

+  * @retval A value between 1 and 128

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ(void)

+{

+  return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1) >>  RCC_PLL1DIVR_Q1_Pos) + 1UL);

+}

+

+/**

+  * @brief  Get PLL1 R Coefficient

+  * @rmtoll PLL1DIVR        R1          LL_RCC_PLL1_GetR

+  * @retval A value between 1 and 128

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetR(void)

+{

+  return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_R1) >>  RCC_PLL1DIVR_R1_Pos) + 1UL);

+}

+

+/**

+  * @brief  Get PLL1 FRACN Coefficient

+  * @rmtoll PLL1FRACR      FRACN1          LL_RCC_PLL1_GetFRACN

+  * @retval A value between 0 and 8191 (0x1FFF)

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void)

+{

+  return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1) >>  RCC_PLL1FRACR_FRACN1_Pos);

+}

+

+/**

+  * @brief  Set PLL1 N Coefficient

+  * @note   This API shall be called only when PLL1 is disabled.

+  * @rmtoll PLL1DIVR        N1          LL_RCC_PLL1_SetN

+  * @param  N parameter can be a value between 4 and 512

+  */

+__STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t N)

+{

+  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_N1, (N-1UL) << RCC_PLL1DIVR_N1_Pos);

+}

+

+/**

+  * @brief  Set PLL1 M Coefficient

+  * @note   This API shall be called only when PLL1 is disabled.

+  * @rmtoll PLLCKSELR       DIVM1          LL_RCC_PLL1_SetM

+  * @param  M parameter can be a value between 0 and 63

+  */

+__STATIC_INLINE void LL_RCC_PLL1_SetM(uint32_t M)

+{

+  MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1, M << RCC_PLLCKSELR_DIVM1_Pos);

+}

+

+/**

+  * @brief  Set PLL1 P Coefficient

+  * @note   This API shall be called only when PLL1 is disabled.

+  * @rmtoll PLL1DIVR        P1          LL_RCC_PLL1_SetP

+  * @param  P parameter can be a value between 2 and 128 (ODD division factor not supportted)

+  */

+__STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t P)

+{

+  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_P1, (P-1UL) << RCC_PLL1DIVR_P1_Pos);

+}

+

+/**

+  * @brief  Set PLL1 Q Coefficient

+  * @note   This API shall be called only when PLL1 is disabled.

+  * @rmtoll PLL1DIVR        Q1          LL_RCC_PLL1_SetQ

+  * @param  Q parameter can be a value between 1 and 128

+  */

+__STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t Q)

+{

+  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1, (Q-1UL) << RCC_PLL1DIVR_Q1_Pos);

+}

+

+/**

+  * @brief  Set PLL1 R Coefficient

+  * @note   This API shall be called only when PLL1 is disabled.

+  * @rmtoll PLL1DIVR        R1          LL_RCC_PLL1_SetR

+  * @param  R parameter can be a value between 1 and 128

+  */

+__STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t R)

+{

+  MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_R1, (R-1UL) << RCC_PLL1DIVR_R1_Pos);

+}

+

+/**

+  * @brief  Set PLL1 FRACN Coefficient

+  * @rmtoll PLL1FRACR        FRACN1          LL_RCC_PLL1_SetFRACN

+  * @param  FRACN parameter can be a value between 0 and 8191 (0x1FFF)

+  */

+__STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN)

+{

+  MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, FRACN << RCC_PLL1FRACR_FRACN1_Pos);

+}

+

+/**

+  * @brief  Enable PLL2

+  * @rmtoll CR           PLL2ON         LL_RCC_PLL2_Enable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL2_Enable(void)

+{

+  SET_BIT(RCC->CR, RCC_CR_PLL2ON);

+}

+

+/**

+  * @brief  Disable PLL2

+  * @note Cannot be disabled if the PLL2 clock is used as the system clock

+  * @rmtoll CR           PLL2ON         LL_RCC_PLL2_Disable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL2_Disable(void)

+{

+  CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);

+}

+

+/**

+  * @brief  Check if PLL2 Ready

+  * @rmtoll CR           PLL2RDY        LL_RCC_PLL2_IsReady

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void)

+{

+  return ((READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY))?1UL:0UL);

+}

+

+/**

+  * @brief  Enable PLL2P

+  * @note   This API shall be called only when PLL2 is disabled.

+  * @rmtoll PLLCFGR           DIVP2EN         LL_RCC_PLL2P_Enable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL2P_Enable(void)

+{

+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN);

+}

+

+/**

+  * @brief  Enable PLL2Q

+  * @note   This API shall be called only when PLL2 is disabled.

+  * @rmtoll PLLCFGR           DIVQ2EN         LL_RCC_PLL2Q_Enable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL2Q_Enable(void)

+{

+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN);

+}

+

+/**

+  * @brief  Enable PLL2R

+  * @note   This API shall be called only when PLL2 is disabled.

+  * @rmtoll PLLCFGR           DIVR2EN         LL_RCC_PLL2R_Enable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL2R_Enable(void)

+{

+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN);

+}

+

+/**

+  * @brief  Enable PLL2 FRACN

+  * @rmtoll PLLCFGR           PLL2FRACEN         LL_RCC_PLL2FRACN_Enable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL2FRACN_Enable(void)

+{

+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN);

+}

+

+/**

+  * @brief  Check if PLL2 P is enabled

+  * @rmtoll PLLCFGR           DIVP2EN         LL_RCC_PLL2P_IsEnabled

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL2P_IsEnabled(void)

+{

+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN) == RCC_PLLCFGR_DIVP2EN)?1UL:0UL);

+}

+

+/**

+  * @brief  Check if PLL2 Q is enabled

+  * @rmtoll PLLCFGR           DIVQ2EN         LL_RCC_PLL2Q_IsEnabled

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL2Q_IsEnabled(void)

+{

+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN) == RCC_PLLCFGR_DIVQ2EN)?1UL:0UL);

+}

+

+/**

+  * @brief  Check if PLL2 R is enabled

+  * @rmtoll PLLCFGR           DIVR2EN         LL_RCC_PLL2R_IsEnabled

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL2R_IsEnabled(void)

+{

+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN) == RCC_PLLCFGR_DIVR2EN)?1UL:0UL);

+}

+

+/**

+  * @brief  Check if PLL2 FRACN is enabled

+  * @rmtoll PLLCFGR           PLL2FRACEN         LL_RCC_PLL2FRACN_IsEnabled

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL2FRACN_IsEnabled(void)

+{

+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) == RCC_PLLCFGR_PLL2FRACEN)?1UL:0UL);

+}

+

+/**

+  * @brief  Disable PLL2P

+  * @note   This API shall be called only when PLL2 is disabled.

+  * @rmtoll PLLCFGR           DIVP2EN         LL_RCC_PLL2P_Disable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL2P_Disable(void)

+{

+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN);

+}

+

+/**

+  * @brief  Disable PLL2Q

+  * @note   This API shall be called only when PLL2 is disabled.

+  * @rmtoll PLLCFGR           DIVQ2EN         LL_RCC_PLL2Q_Disable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL2Q_Disable(void)

+{

+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN);

+}

+

+/**

+  * @brief  Disable PLL2R

+  * @note   This API shall be called only when PLL2 is disabled.

+  * @rmtoll PLLCFGR           DIVR2EN         LL_RCC_PLL2R_Disable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL2R_Disable(void)

+{

+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN);

+}

+

+/**

+  * @brief  Disable PLL2 FRACN

+  * @rmtoll PLLCFGR           PLL2FRACEN         LL_RCC_PLL2FRACN_Enable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL2FRACN_Disable(void)

+{

+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN);

+}

+

+/**

+  * @brief  Set PLL2 VCO OutputRange

+  * @note   This API shall be called only when PLL2 is disabled.

+  * @rmtoll PLLCFGR        PLL2VCOSEL       LL_RCC_PLL2_SetVCOOuputRange

+  * @param  VCORange This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_PLLVCORANGE_WIDE

+  *         @arg @ref LL_RCC_PLLVCORANGE_MEDIUM

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL2_SetVCOOutputRange(uint32_t VCORange)

+{

+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, VCORange << RCC_PLLCFGR_PLL2VCOSEL_Pos);

+}

+

+/**

+  * @brief  Set PLL2 VCO Input Range

+  * @note   This API shall be called only when PLL2 is disabled.

+  * @rmtoll PLLCFGR        PLL2RGE       LL_RCC_PLL2_SetVCOInputRange

+  * @param  InputRange This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_PLLINPUTRANGE_1_2

+  *         @arg @ref LL_RCC_PLLINPUTRANGE_2_4

+  *         @arg @ref LL_RCC_PLLINPUTRANGE_4_8

+  *         @arg @ref LL_RCC_PLLINPUTRANGE_8_16

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL2_SetVCOInputRange(uint32_t InputRange)

+{

+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, InputRange << RCC_PLLCFGR_PLL2RGE_Pos);

+}

+

+/**

+  * @brief  Get PLL2 N Coefficient

+  * @rmtoll PLL2DIVR        N2          LL_RCC_PLL2_GetN

+  * @retval A value between 4 and 512

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetN(void)

+{

+  return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_N2) >>  RCC_PLL2DIVR_N2_Pos) + 1UL);

+}

+

+/**

+  * @brief  Get PLL2 M Coefficient

+  * @rmtoll PLLCKSELR       DIVM2          LL_RCC_PLL2_GetM

+  * @retval A value between 0 and 63

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetM(void)

+{

+  return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2) >>  RCC_PLLCKSELR_DIVM2_Pos);

+}

+

+/**

+  * @brief  Get PLL2 P Coefficient

+  * @rmtoll PLL2DIVR        P2          LL_RCC_PLL2_GetP

+  * @retval A value between 1 and 128

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetP(void)

+{

+  return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_P2) >>  RCC_PLL2DIVR_P2_Pos) + 1UL);

+}

+

+/**

+  * @brief  Get PLL2 Q Coefficient

+  * @rmtoll PLL2DIVR        Q2          LL_RCC_PLL2_GetQ

+  * @retval A value between 1 and 128

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetQ(void)

+{

+  return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2) >>  RCC_PLL2DIVR_Q2_Pos) + 1UL);

+}

+

+/**

+  * @brief  Get PLL2 R Coefficient

+  * @rmtoll PLL2DIVR        R2          LL_RCC_PLL2_GetR

+  * @retval A value between 1 and 128

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetR(void)

+{

+  return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_R2) >>  RCC_PLL2DIVR_R2_Pos) + 1UL);

+}

+

+/**

+  * @brief  Get PLL2 FRACN Coefficient

+  * @rmtoll PLL2FRACR      FRACN2          LL_RCC_PLL2_GetFRACN

+  * @retval A value between 0 and 8191 (0x1FFF)

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void)

+{

+  return (uint32_t)(READ_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2) >>  RCC_PLL2FRACR_FRACN2_Pos);

+}

+

+/**

+  * @brief  Set PLL2 N Coefficient

+  * @note   This API shall be called only when PLL2 is disabled.

+  * @rmtoll PLL2DIVR        N2          LL_RCC_PLL2_SetN

+  * @param  N parameter can be a value between 4 and 512

+  */

+__STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t N)

+{

+  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_N2, (N-1UL) << RCC_PLL2DIVR_N2_Pos);

+}

+

+/**

+  * @brief  Set PLL2 M Coefficient

+  * @note   This API shall be called only when PLL2 is disabled.

+  * @rmtoll PLLCKSELR       DIVM2          LL_RCC_PLL2_SetM

+  * @param  M parameter can be a value between 0 and 63

+  */

+__STATIC_INLINE void LL_RCC_PLL2_SetM(uint32_t M)

+{

+  MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2, M << RCC_PLLCKSELR_DIVM2_Pos);

+}

+

+/**

+  * @brief  Set PLL2 P Coefficient

+  * @note   This API shall be called only when PLL2 is disabled.

+  * @rmtoll PLL2DIVR        P2          LL_RCC_PLL2_SetP

+  * @param  P parameter can be a value between 1 and 128

+  */

+__STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t P)

+{

+  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_P2, (P-1UL) << RCC_PLL2DIVR_P2_Pos);

+}

+

+/**

+  * @brief  Set PLL2 Q Coefficient

+  * @note   This API shall be called only when PLL2 is disabled.

+  * @rmtoll PLL2DIVR        Q2          LL_RCC_PLL2_SetQ

+  * @param  Q parameter can be a value between 1 and 128

+  */

+__STATIC_INLINE void LL_RCC_PLL2_SetQ(uint32_t Q)

+{

+  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2, (Q-1UL) << RCC_PLL2DIVR_Q2_Pos);

+}

+

+/**

+  * @brief  Set PLL2 R Coefficient

+  * @note   This API shall be called only when PLL2 is disabled.

+  * @rmtoll PLL2DIVR        R2          LL_RCC_PLL2_SetR

+  * @param  R parameter can be a value between 1 and 128

+  */

+__STATIC_INLINE void LL_RCC_PLL2_SetR(uint32_t R)

+{

+  MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_R2, (R-1UL) << RCC_PLL2DIVR_R2_Pos);

+}

+

+/**

+  * @brief  Set PLL2 FRACN Coefficient

+  * @rmtoll PLL2FRACR        FRACN2          LL_RCC_PLL2_SetFRACN

+  * @param  FRACN parameter can be a value between 0 and 8191 (0x1FFF)

+  */

+__STATIC_INLINE void LL_RCC_PLL2_SetFRACN(uint32_t FRACN)

+{

+  MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2, FRACN << RCC_PLL2FRACR_FRACN2_Pos);

+}

+

+/**

+  * @brief  Enable PLL3

+  * @rmtoll CR           PLL3ON         LL_RCC_PLL3_Enable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL3_Enable(void)

+{

+  SET_BIT(RCC->CR, RCC_CR_PLL3ON);

+}

+

+/**

+  * @brief  Disable PLL3

+  * @note Cannot be disabled if the PLL3 clock is used as the system clock

+  * @rmtoll CR           PLL3ON         LL_RCC_PLL3_Disable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL3_Disable(void)

+{

+  CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);

+}

+

+/**

+  * @brief  Check if PLL3 Ready

+  * @rmtoll CR           PLL3RDY        LL_RCC_PLL3_IsReady

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void)

+{

+  return ((READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY))?1UL:0UL);

+}

+

+/**

+  * @brief  Enable PLL3P

+  * @note   This API shall be called only when PLL3 is disabled.

+  * @rmtoll PLLCFGR           DIVP3EN         LL_RCC_PLL3P_Enable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL3P_Enable(void)

+{

+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN);

+}

+

+/**

+  * @brief  Enable PLL3Q

+  * @note   This API shall be called only when PLL3 is disabled.

+  * @rmtoll PLLCFGR           DIVQ3EN         LL_RCC_PLL3Q_Enable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL3Q_Enable(void)

+{

+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN);

+}

+

+/**

+  * @brief  Enable PLL3R

+  * @note   This API shall be called only when PLL3 is disabled.

+  * @rmtoll PLLCFGR           DIVR3EN         LL_RCC_PLL3R_Enable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL3R_Enable(void)

+{

+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN);

+}

+

+/**

+  * @brief  Enable PLL3 FRACN

+  * @rmtoll PLLCFGR           PLL3FRACEN         LL_RCC_PLL3FRACN_Enable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL3FRACN_Enable(void)

+{

+  SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN);

+}

+

+/**

+  * @brief  Check if PLL3 P is enabled

+  * @rmtoll PLLCFGR           DIVP3EN         LL_RCC_PLL3P_IsEnabled

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL3P_IsEnabled(void)

+{

+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN) == RCC_PLLCFGR_DIVP3EN)?1UL:0UL);

+}

+

+/**

+  * @brief  Check if PLL3 Q is enabled

+  * @rmtoll PLLCFGR           DIVQ3EN         LL_RCC_PLL3Q_IsEnabled

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL3Q_IsEnabled(void)

+{

+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN) == RCC_PLLCFGR_DIVQ3EN)?1UL:0UL);

+}

+

+/**

+  * @brief  Check if PLL3 R is enabled

+  * @rmtoll PLLCFGR           DIVR3EN         LL_RCC_PLL3R_IsEnabled

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL3R_IsEnabled(void)

+{

+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN) == RCC_PLLCFGR_DIVR3EN)?1UL:0UL);

+}

+

+/**

+  * @brief  Check if PLL3 FRACN is enabled

+  * @rmtoll PLLCFGR           PLL3FRACEN         LL_RCC_PLL3FRACN_IsEnabled

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL3FRACN_IsEnabled(void)

+{

+  return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) == RCC_PLLCFGR_PLL3FRACEN)?1UL:0UL);

+}

+

+/**

+  * @brief  Disable PLL3P

+  * @note   This API shall be called only when PLL3 is disabled.

+  * @rmtoll PLLCFGR           DIVP2EN         LL_RCC_PLL3P_Disable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL3P_Disable(void)

+{

+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN);

+}

+

+/**

+  * @brief  Disable PLL3Q

+  * @note   This API shall be called only when PLL3 is disabled.

+  * @rmtoll PLLCFGR           DIVQ3EN         LL_RCC_PLL3Q_Disable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL3Q_Disable(void)

+{

+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN);

+}

+

+/**

+  * @brief  Disable PLL3R

+  * @note   This API shall be called only when PLL3 is disabled.

+  * @rmtoll PLLCFGR           DIVR3EN         LL_RCC_PLL3R_Disable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL3R_Disable(void)

+{

+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN);

+}

+

+/**

+  * @brief  Disable PLL3 FRACN

+  * @rmtoll PLLCFGR           PLL3FRACEN         LL_RCC_PLL3FRACN_Enable

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL3FRACN_Disable(void)

+{

+  CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN);

+}

+

+/**

+  * @brief  Set PLL3 VCO OutputRange

+  * @note   This API shall be called only when PLL3 is disabled.

+  * @rmtoll PLLCFGR        PLL3VCOSEL       LL_RCC_PLL3_SetVCOOuputRange

+  * @param  VCORange This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_PLLVCORANGE_WIDE

+  *         @arg @ref LL_RCC_PLLVCORANGE_MEDIUM

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL3_SetVCOOutputRange(uint32_t VCORange)

+{

+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, VCORange << RCC_PLLCFGR_PLL3VCOSEL_Pos);

+}

+

+/**

+  * @brief  Set PLL3 VCO Input Range

+  * @note   This API shall be called only when PLL3 is disabled.

+  * @rmtoll PLLCFGR        PLL3RGE       LL_RCC_PLL3_SetVCOInputRange

+  * @param  InputRange This parameter can be one of the following values:

+  *         @arg @ref LL_RCC_PLLINPUTRANGE_1_2

+  *         @arg @ref LL_RCC_PLLINPUTRANGE_2_4

+  *         @arg @ref LL_RCC_PLLINPUTRANGE_4_8

+  *         @arg @ref LL_RCC_PLLINPUTRANGE_8_16

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange)

+{

+  MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, InputRange << RCC_PLLCFGR_PLL3RGE_Pos);

+}

+

+/**

+  * @brief  Get PLL3 N Coefficient

+  * @rmtoll PLL3DIVR        N3          LL_RCC_PLL3_GetN

+  * @retval A value between 4 and 512

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetN(void)

+{

+  return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_N3) >>  RCC_PLL3DIVR_N3_Pos) + 1UL);

+}

+

+/**

+  * @brief  Get PLL3 M Coefficient

+  * @rmtoll PLLCKSELR       DIVM3          LL_RCC_PLL3_GetM

+  * @retval A value between 0 and 63

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetM(void)

+{

+  return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3) >>  RCC_PLLCKSELR_DIVM3_Pos);

+}

+

+/**

+  * @brief  Get PLL3 P Coefficient

+  * @rmtoll PLL3DIVR        P3          LL_RCC_PLL3_GetP

+  * @retval A value between 1 and 128

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetP(void)

+{

+  return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_P3) >>  RCC_PLL3DIVR_P3_Pos) + 1UL);

+}

+

+/**

+  * @brief  Get PLL3 Q Coefficient

+  * @rmtoll PLL3DIVR        Q3          LL_RCC_PLL3_GetQ

+  * @retval A value between 1 and 128

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetQ(void)

+{

+  return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3) >>  RCC_PLL3DIVR_Q3_Pos) + 1UL);

+}

+

+/**

+  * @brief  Get PLL3 R Coefficient

+  * @rmtoll PLL3DIVR        R3          LL_RCC_PLL3_GetR

+  * @retval A value between 1 and 128

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetR(void)

+{

+  return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_R3) >>  RCC_PLL3DIVR_R3_Pos) + 1UL);

+}

+

+/**

+  * @brief  Get PLL3 FRACN Coefficient

+  * @rmtoll PLL3FRACR      FRACN3          LL_RCC_PLL3_GetFRACN

+  * @retval A value between 0 and 8191 (0x1FFF)

+  */

+__STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void)

+{

+  return (uint32_t)(READ_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3) >>  RCC_PLL3FRACR_FRACN3_Pos);

+}

+

+/**

+  * @brief  Set PLL3 N Coefficient

+  * @note   This API shall be called only when PLL3 is disabled.

+  * @rmtoll PLL3DIVR        N3          LL_RCC_PLL3_SetN

+  * @param  N parameter can be a value between 4 and 512

+  */

+__STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t N)

+{

+  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_N3, (N-1UL) << RCC_PLL3DIVR_N3_Pos);

+}

+

+/**

+  * @brief  Set PLL3 M Coefficient

+  * @note   This API shall be called only when PLL3 is disabled.

+  * @rmtoll PLLCKSELR       DIVM3          LL_RCC_PLL3_SetM

+  * @param  M parameter can be a value between 0 and 63

+  */

+__STATIC_INLINE void LL_RCC_PLL3_SetM(uint32_t M)

+{

+  MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3, M << RCC_PLLCKSELR_DIVM3_Pos);

+}

+

+/**

+  * @brief  Set PLL3 P Coefficient

+  * @note   This API shall be called only when PLL3 is disabled.

+  * @rmtoll PLL3DIVR        P3          LL_RCC_PLL3_SetP

+  * @param  P parameter can be a value between 1 and 128

+  */

+__STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t P)

+{

+  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_P3, (P-1UL) << RCC_PLL3DIVR_P3_Pos);

+}

+

+/**

+  * @brief  Set PLL3 Q Coefficient

+  * @note   This API shall be called only when PLL3 is disabled.

+  * @rmtoll PLL3DIVR        Q3          LL_RCC_PLL3_SetQ

+  * @param  Q parameter can be a value between 1 and 128

+  */

+__STATIC_INLINE void LL_RCC_PLL3_SetQ(uint32_t Q)

+{

+  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3, (Q-1UL) << RCC_PLL3DIVR_Q3_Pos);

+}

+

+/**

+  * @brief  Set PLL3 R Coefficient

+  * @note   This API shall be called only when PLL3 is disabled.

+  * @rmtoll PLL3DIVR        R3          LL_RCC_PLL3_SetR

+  * @param  R parameter can be a value between 1 and 128

+  */

+__STATIC_INLINE void LL_RCC_PLL3_SetR(uint32_t R)

+{

+  MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_R3, (R-1UL) << RCC_PLL3DIVR_R3_Pos);

+}

+

+/**

+  * @brief  Set PLL3 FRACN Coefficient

+  * @rmtoll PLL3FRACR        FRACN3          LL_RCC_PLL3_SetFRACN

+  * @param  FRACN parameter can be a value between 0 and 8191 (0x1FFF)

+  */

+__STATIC_INLINE void LL_RCC_PLL3_SetFRACN(uint32_t FRACN)

+{

+  MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, FRACN << RCC_PLL3FRACR_FRACN3_Pos);

+}

+

+

+/**

+  * @}

+  */

+

+

+/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management

+  * @{

+  */

+

+/**

+  * @brief  Clear LSI ready interrupt flag

+  * @rmtoll CICR         LSIRDYC       LL_RCC_ClearFlag_LSIRDY

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)

+{

+  SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);

+}

+

+/**

+  * @brief  Clear LSE ready interrupt flag

+  * @rmtoll CICR         LSERDYC       LL_RCC_ClearFlag_LSERDY

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)

+{

+  SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);

+}

+

+/**

+  * @brief  Clear HSI ready interrupt flag

+  * @rmtoll CICR         HSIRDYC       LL_RCC_ClearFlag_HSIRDY

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)

+{

+  SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);

+}

+

+/**

+  * @brief  Clear HSE ready interrupt flag

+  * @rmtoll CICR         HSERDYC       LL_RCC_ClearFlag_HSERDY

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)

+{

+  SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);

+}

+

+/**

+  * @brief  Clear CSI ready interrupt flag

+  * @rmtoll CICR         CSIRDYC       LL_RCC_ClearFlag_CSIRDY

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_ClearFlag_CSIRDY(void)

+{

+  SET_BIT(RCC->CICR, RCC_CICR_CSIRDYC);

+}

+

+/**

+  * @brief  Clear HSI48 ready interrupt flag

+  * @rmtoll CICR         HSI48RDYC       LL_RCC_ClearFlag_HSI48RDY

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)

+{

+  SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);

+}

+

+/**

+  * @brief  Clear PLL1 ready interrupt flag

+  * @rmtoll CICR         PLL1RDYC       LL_RCC_ClearFlag_PLL1RDY

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void)

+{

+  SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);

+}

+

+/**

+  * @brief  Clear PLL2 ready interrupt flag

+  * @rmtoll CICR         PLL2RDYC       LL_RCC_ClearFlag_PLL2RDY

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void)

+{

+  SET_BIT(RCC->CICR, RCC_CICR_PLL2RDYC);

+}

+

+/**

+  * @brief  Clear PLL3 ready interrupt flag

+  * @rmtoll CICR         PLL3RDYC       LL_RCC_ClearFlag_PLL3RDY

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_ClearFlag_PLL3RDY(void)

+{

+  SET_BIT(RCC->CICR, RCC_CICR_PLL3RDYC);

+}

+

+/**

+  * @brief  Clear LSE Clock security system interrupt flag

+  * @rmtoll CICR         LSECSSC         LL_RCC_ClearFlag_LSECSS

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)

+{

+  SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);

+}

+

+/**

+  * @brief  Clear HSE Clock security system interrupt flag

+  * @rmtoll CICR         HSECSSC         LL_RCC_ClearFlag_HSECSS

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)

+{

+  SET_BIT(RCC->CICR, RCC_CICR_HSECSSC);

+}

+

+/**

+  * @brief  Check if LSI ready interrupt occurred or not

+  * @rmtoll CIFR         LSIRDYF       LL_RCC_IsActiveFlag_LSIRDY

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)

+{

+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if LSE ready interrupt occurred or not

+  * @rmtoll CIFR         LSERDYF       LL_RCC_IsActiveFlag_LSERDY

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)

+{

+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if HSI ready interrupt occurred or not

+  * @rmtoll CIFR         HSIRDYF       LL_RCC_IsActiveFlag_HSIRDY

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)

+{

+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if HSE ready interrupt occurred or not

+  * @rmtoll CIFR         HSERDYF       LL_RCC_IsActiveFlag_HSERDY

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)

+{

+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if CSI ready interrupt occurred or not

+  * @rmtoll CIFR         CSIRDYF       LL_RCC_IsActiveFlag_CSIRDY

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CSIRDY(void)

+{

+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSIRDYF) == (RCC_CIFR_CSIRDYF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if HSI48 ready interrupt occurred or not

+  * @rmtoll CIFR         HSI48RDYF       LL_RCC_IsActiveFlag_HSI48RDY

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)

+{

+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if PLL1 ready interrupt occurred or not

+  * @rmtoll CIFR         PLLRDYF       LL_RCC_IsActiveFlag_PLL1RDY

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void)

+{

+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if PLL2 ready interrupt occurred or not

+  * @rmtoll CIFR         PLL2RDYF       LL_RCC_IsActiveFlag_PLL2RDY

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void)

+{

+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == (RCC_CIFR_PLL2RDYF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if PLL3 ready interrupt occurred or not

+  * @rmtoll CIFR         PLL3RDYF       LL_RCC_IsActiveFlag_PLL3RDY

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void)

+{

+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == (RCC_CIFR_PLL3RDYF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if LSE Clock security system interrupt occurred or not

+  * @rmtoll CIFR         LSECSSF          LL_RCC_IsActiveFlag_LSECSS

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)

+{

+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if HSE Clock security system interrupt occurred or not

+  * @rmtoll CIFR         HSECSSF          LL_RCC_IsActiveFlag_HSECSS

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)

+{

+  return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == (RCC_CIFR_HSECSSF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if RCC flag Low Power D1 reset is set or not.

+  * @rmtoll RSR          LPWRRSTF       LL_RCC_IsActiveFlag_LPWRRST (*)\n

+  *         RSR          LPWR1RSTF      LL_RCC_IsActiveFlag_LPWRRST (**)

+  *

+  * (*) Only available for single core devices

+  * (**) Only available for Dual core devices

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)

+{

+#if defined(DUAL_CORE)

+  return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL);

+#else

+  return ((READ_BIT(RCC->RSR, RCC_RSR_LPWRRSTF) == (RCC_RSR_LPWRRSTF))?1UL:0UL);

+#endif /*DUAL_CORE*/

+}

+

+#if defined(DUAL_CORE)

+/**

+  * @brief  Check if RCC flag Low Power D2 reset is set or not.

+  * @rmtoll RSR          LPWR2RSTF      LL_RCC_IsActiveFlag_LPWR2RST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWR2RST(void)

+{

+  return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL);

+}

+#endif  /*DUAL_CORE*/

+

+/**

+  * @brief  Check if RCC flag Window Watchdog 1 reset is set or not.

+  * @rmtoll RSR          WWDG1RSTF      LL_RCC_IsActiveFlag_WWDG1RST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG1RST(void)

+{

+  return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL);

+}

+

+#if defined(DUAL_CORE)

+/**

+  * @brief  Check if RCC flag Window Watchdog 2 reset is set or not.

+  * @rmtoll RSR          WWDG2RSTF      LL_RCC_IsActiveFlag_WWDG2RST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG2RST(void)

+{

+  return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL);

+}

+#endif  /*DUAL_CORE*/

+

+/**

+  * @brief  Check if RCC flag Independent Watchdog 1 reset is set or not.

+  * @rmtoll RSR          IWDG1RSTF      LL_RCC_IsActiveFlag_IWDG1RST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG1RST(void)

+{

+  return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL);

+}

+

+#if defined(DUAL_CORE)

+/**

+  * @brief  Check if RCC flag Independent Watchdog 2 reset is set or not.

+  * @rmtoll RSR          IWDG2RSTF      LL_RCC_IsActiveFlag_IWDG2RST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG2RST(void)

+{

+  return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL);

+}

+#endif  /*DUAL_CORE*/

+

+/**

+  * @brief  Check if RCC flag Software reset is set or not.

+  * @rmtoll RSR          SFTRSTF        LL_RCC_IsActiveFlag_SFTRST (*)\n

+  *         RSR          SFT1RSTF       LL_RCC_IsActiveFlag_SFTRST (**)

+  *

+  * (*) Only available for single core devices

+  * (**) Only available for Dual core devices

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)

+{

+#if defined(DUAL_CORE)

+  return ((READ_BIT(RCC->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL);

+#else

+  return ((READ_BIT(RCC->RSR, RCC_RSR_SFTRSTF) == (RCC_RSR_SFTRSTF))?1UL:0UL);

+#endif  /*DUAL_CORE*/

+}

+

+#if defined(DUAL_CORE)

+/**

+  * @brief  Check if RCC flag Software reset is set or not.

+  * @rmtoll RSR          SFT2RSTF       LL_RCC_IsActiveFlag_SFT2RST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFT2RST(void)

+{

+  return ((READ_BIT(RCC->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL);

+}

+#endif  /*DUAL_CORE*/

+

+/**

+  * @brief  Check if RCC flag POR/PDR reset is set or not.

+  * @rmtoll RSR          PORRSTF       LL_RCC_IsActiveFlag_PORRST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)

+{

+  return ((READ_BIT(RCC->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if RCC flag Pin reset is set or not.

+  * @rmtoll RSR          PINRSTF       LL_RCC_IsActiveFlag_PINRST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)

+{

+  return ((READ_BIT(RCC->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if RCC flag BOR reset is set or not.

+  * @rmtoll RSR          BORRSTF       LL_RCC_IsActiveFlag_BORRST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)

+{

+  return ((READ_BIT(RCC->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL);

+}

+

+#if defined(RCC_RSR_D1RSTF)

+/**

+  * @brief  Check if RCC flag D1 reset is set or not.

+  * @rmtoll RSR          D1RSTF       LL_RCC_IsActiveFlag_D1RST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D1RST(void)

+{

+  return ((READ_BIT(RCC->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL);

+}

+#endif /* RCC_RSR_D1RSTF */

+

+#if defined(RCC_RSR_CDRSTF)

+/**

+  * @brief  Check if RCC flag CD reset is set or not.

+  * @rmtoll RSR          CDRSTF       LL_RCC_IsActiveFlag_CDRST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CDRST(void)

+{

+  return ((READ_BIT(RCC->RSR, RCC_RSR_CDRSTF) == (RCC_RSR_CDRSTF))?1UL:0UL);

+}

+#endif /* RCC_RSR_CDRSTF */

+

+#if defined(RCC_RSR_D2RSTF)

+/**

+  * @brief  Check if RCC flag D2 reset is set or not.

+  * @rmtoll RSR          D2RSTF       LL_RCC_IsActiveFlag_D2RST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D2RST(void)

+{

+  return ((READ_BIT(RCC->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL);

+}

+#endif /* RCC_RSR_D2RSTF */

+

+#if defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF)

+/**

+  * @brief  Check if RCC flag CPU reset is set or not.

+  * @rmtoll RSR          CPURSTF       LL_RCC_IsActiveFlag_CPURST (*)\n

+  *         RSR          C1RSTF        LL_RCC_IsActiveFlag_CPURST (**)

+  *

+  * (*) Only available for single core devices

+  * (**) Only available for Dual core devices

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPURST(void)

+{

+#if defined(DUAL_CORE)

+  return ((READ_BIT(RCC->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL);

+#else

+  return ((READ_BIT(RCC->RSR, RCC_RSR_CPURSTF) == (RCC_RSR_CPURSTF))?1UL:0UL);

+#endif/*DUAL_CORE*/

+}

+#endif /* defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF) */

+

+#if defined(DUAL_CORE)

+/**

+  * @brief  Check if RCC flag CPU2 reset is set or not.

+  * @rmtoll RSR          C2RSTF       LL_RCC_IsActiveFlag_CPU2RST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPU2RST(void)

+{

+  return ((READ_BIT(RCC->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL);

+}

+#endif  /*DUAL_CORE*/

+

+/**

+  * @brief  Set RMVF bit to clear all reset flags.

+  * @rmtoll RSR          RMVF          LL_RCC_ClearResetFlags

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_ClearResetFlags(void)

+{

+  SET_BIT(RCC->RSR, RCC_RSR_RMVF);

+}

+

+#if defined(DUAL_CORE)

+/**

+  * @brief  Check if RCC_C1 flag Low Power D1 reset is set or not.

+  * @rmtoll RSR          LPWR1RSTF      LL_C1_RCC_IsActiveFlag_LPWRRST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWRRST(void)

+{

+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if RCC_C1 flag Low Power D2 reset is set or not.

+  * @rmtoll RSR          LPWR2RSTF      LL_C1_RCC_IsActiveFlag_LPWR2RST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWR2RST(void)

+{

+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if RCC_C1 flag Window Watchdog 1 reset is set or not.

+  * @rmtoll RSR          WWDG1RSTF      LL_C1_RCC_IsActiveFlag_WWDG1RST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG1RST(void)

+{

+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if RCC_C1 flag Window Watchdog 2 reset is set or not.

+  * @rmtoll RSR          WWDG2RSTF      LL_C1_RCC_IsActiveFlag_WWDG2RST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG2RST(void)

+{

+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if RCC_C1 flag Independent Watchdog 1 reset is set or not.

+  * @rmtoll RSR          IWDG1RSTF      LL_C1_RCC_IsActiveFlag_IWDG1RST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG1RST(void)

+{

+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if RCC_C1 flag Independent Watchdog 2 reset is set or not.

+  * @rmtoll RSR          IWDG2RSTF      LL_C1_RCC_IsActiveFlag_IWDG2RST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG2RST(void)

+{

+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if RCC_C1 flag Software reset is set or not.

+  * @rmtoll RSR          SFT1RSTF       LL_C1_RCC_IsActiveFlag_SFTRST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFTRST(void)

+{

+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if RCC_C1 flag Software reset is set or not.

+  * @rmtoll RSR          SFT2RSTF       LL_C1_RCC_IsActiveFlag_SFT2RST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFT2RST(void)

+{

+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if RCC_C1 flag POR/PDR reset is set or not.

+  * @rmtoll RSR          PORRSTF       LL_C1_RCC_IsActiveFlag_PORRST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PORRST(void)

+{

+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if RCC_C1 flag Pin reset is set or not.

+  * @rmtoll RSR          PINRSTF       LL_C1_RCC_IsActiveFlag_PINRST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PINRST(void)

+{

+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if RCC_C1 flag BOR reset is set or not.

+  * @rmtoll RSR          BORRSTF       LL_C1_RCC_IsActiveFlag_BORRST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_BORRST(void)

+{

+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if RCC_C1 flag D1 reset is set or not.

+  * @rmtoll RSR          D1RSTF       LL_C1_RCC_IsActiveFlag_D1RST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D1RST(void)

+{

+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if RCC_C1 flag D2 reset is set or not.

+  * @rmtoll RSR          D2RSTF       LL_C1_RCC_IsActiveFlag_D2RST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D2RST(void)

+{

+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if RCC_C1 flag CPU reset is set or not.

+  * @rmtoll RSR          C1RSTF       LL_C1_RCC_IsActiveFlag_CPURST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPURST(void)

+{

+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if RCC_C1 flag CPU2 reset is set or not.

+  * @rmtoll RSR          C2RSTF       LL_C1_RCC_IsActiveFlag_CPU2RST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPU2RST(void)

+{

+  return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Set RMVF bit to clear the reset flags.

+  * @rmtoll RSR          RMVF          LL_C1_RCC_ClearResetFlags

+  * @retval None

+  */

+__STATIC_INLINE void LL_C1_RCC_ClearResetFlags(void)

+{

+  SET_BIT(RCC_C1->RSR, RCC_RSR_RMVF);

+}

+

+/**

+  * @brief  Check if RCC_C2 flag Low Power D1 reset is set or not.

+  * @rmtoll RSR          LPWR1RSTF      LL_C2_RCC_IsActiveFlag_LPWRRST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWRRST(void)

+{

+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if RCC_C2 flag Low Power D2 reset is set or not.

+  * @rmtoll RSR          LPWR2RSTF      LL_C2_RCC_IsActiveFlag_LPWR2RST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWR2RST(void)

+{

+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if RCC_C2 flag Window Watchdog 1 reset is set or not.

+  * @rmtoll RSR          WWDG1RSTF      LL_C2_RCC_IsActiveFlag_WWDG1RST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG1RST(void)

+{

+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if RCC_C2 flag Window Watchdog 2 reset is set or not.

+  * @rmtoll RSR          WWDG2RSTF      LL_C2_RCC_IsActiveFlag_WWDG2RST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG2RST(void)

+{

+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if RCC_C2 flag Independent Watchdog 1 reset is set or not.

+  * @rmtoll RSR          IWDG1RSTF      LL_C2_RCC_IsActiveFlag_IWDG1RST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG1RST(void)

+{

+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if RCC_C2 flag Independent Watchdog 2 reset is set or not.

+  * @rmtoll RSR          IWDG2RSTF      LL_C2_RCC_IsActiveFlag_IWDG2RST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG2RST(void)

+{

+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if RCC_C2 flag Software reset is set or not.

+  * @rmtoll RSR          SFT1RSTF       LL_C2_RCC_IsActiveFlag_SFTRST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFTRST(void)

+{

+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if RCC_C2 flag Software reset is set or not.

+  * @rmtoll RSR          SFT2RSTF       LL_C2_RCC_IsActiveFlag_SFT2RST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFT2RST(void)

+{

+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if RCC_C2 flag POR/PDR reset is set or not.

+  * @rmtoll RSR          PORRSTF       LL_C2_RCC_IsActiveFlag_PORRST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PORRST(void)

+{

+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if RCC_C2 flag Pin reset is set or not.

+  * @rmtoll RSR          PINRSTF       LL_C2_RCC_IsActiveFlag_PINRST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PINRST(void)

+{

+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if RCC_C2 flag BOR reset is set or not.

+  * @rmtoll RSR          BORRSTF       LL_C2_RCC_IsActiveFlag_BORRST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_BORRST(void)

+{

+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if RCC_C2 flag D1 reset is set or not.

+  * @rmtoll RSR          D1RSTF       LL_C2_RCC_IsActiveFlag_D1RST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D1RST(void)

+{

+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if RCC_C2 flag D2 reset is set or not.

+  * @rmtoll RSR          D2RSTF       LL_C2_RCC_IsActiveFlag_D2RST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D2RST(void)

+{

+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if RCC_C2 flag CPU reset is set or not.

+  * @rmtoll RSR          C1RSTF       LL_C2_RCC_IsActiveFlag_CPURST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPURST(void)

+{

+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Check if RCC_C2 flag CPU2 reset is set or not.

+  * @rmtoll RSR          C2RSTF       LL_C2_RCC_IsActiveFlag_CPU2RST

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPU2RST(void)

+{

+  return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF))?1UL:0UL);

+}

+

+/**

+  * @brief  Set RMVF bit to clear the reset flags.

+  * @rmtoll RSR          RMVF          LL_C2_RCC_ClearResetFlags

+  * @retval None

+  */

+__STATIC_INLINE void LL_C2_RCC_ClearResetFlags(void)

+{

+  SET_BIT(RCC_C2->RSR, RCC_RSR_RMVF);

+}

+#endif /*DUAL_CORE*/

+

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EF_IT_Management IT Management

+  * @{

+  */

+

+/**

+  * @brief  Enable LSI ready interrupt

+  * @rmtoll CIER         LSIRDYIE      LL_RCC_EnableIT_LSIRDY

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)

+{

+  SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);

+}

+

+/**

+  * @brief  Enable LSE ready interrupt

+  * @rmtoll CIER         LSERDYIE      LL_RCC_EnableIT_LSERDY

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)

+{

+  SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);

+}

+

+/**

+  * @brief  Enable HSI ready interrupt

+  * @rmtoll CIER         HSIRDYIE      LL_RCC_EnableIT_HSIRDY

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)

+{

+  SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);

+}

+

+/**

+  * @brief  Enable HSE ready interrupt

+  * @rmtoll CIER         HSERDYIE      LL_RCC_EnableIT_HSERDY

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)

+{

+  SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);

+}

+

+/**

+  * @brief  Enable CSI ready interrupt

+  * @rmtoll CIER         CSIRDYIE      LL_RCC_EnableIT_CSIRDY

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_EnableIT_CSIRDY(void)

+{

+  SET_BIT(RCC->CIER, RCC_CIER_CSIRDYIE);

+}

+

+/**

+  * @brief  Enable HSI48 ready interrupt

+  * @rmtoll CIER         HSI48RDYIE      LL_RCC_EnableIT_HSI48RDY

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)

+{

+  SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);

+}

+

+/**

+  * @brief  Enable PLL1 ready interrupt

+  * @rmtoll CIER         PLL1RDYIE      LL_RCC_EnableIT_PLL1RDY

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void)

+{

+  SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);

+}

+

+/**

+  * @brief  Enable PLL2 ready interrupt

+  * @rmtoll CIER         PLL2RDYIE  LL_RCC_EnableIT_PLL2RDY

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void)

+{

+  SET_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);

+}

+

+/**

+  * @brief  Enable PLL3 ready interrupt

+  * @rmtoll CIER         PLL3RDYIE  LL_RCC_EnableIT_PLL3RDY

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_EnableIT_PLL3RDY(void)

+{

+  SET_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);

+}

+

+/**

+  * @brief  Enable LSECSS interrupt

+  * @rmtoll CIER         LSECSSIE  LL_RCC_EnableIT_LSECSS

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)

+{

+  SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);

+}

+

+/**

+  * @brief  Disable LSI ready interrupt

+  * @rmtoll CIER         LSIRDYIE      LL_RCC_DisableIT_LSIRDY

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)

+{

+  CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);

+}

+

+/**

+  * @brief  Disable LSE ready interrupt

+  * @rmtoll CIER         LSERDYIE      LL_RCC_DisableIT_LSERDY

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)

+{

+  CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);

+}

+

+/**

+  * @brief  Disable HSI ready interrupt

+  * @rmtoll CIER         HSIRDYIE      LL_RCC_DisableIT_HSIRDY

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)

+{

+  CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);

+}

+

+/**

+  * @brief  Disable HSE ready interrupt

+  * @rmtoll CIER         HSERDYIE      LL_RCC_DisableIT_HSERDY

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)

+{

+  CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);

+}

+

+/**

+  * @brief  Disable CSI ready interrupt

+  * @rmtoll CIER         CSIRDYIE      LL_RCC_DisableIT_CSIRDY

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_DisableIT_CSIRDY(void)

+{

+  CLEAR_BIT(RCC->CIER, RCC_CIER_CSIRDYIE);

+}

+

+/**

+  * @brief  Disable HSI48 ready interrupt

+  * @rmtoll CIER         HSI48RDYIE      LL_RCC_DisableIT_HSI48RDY

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)

+{

+  CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);

+}

+

+/**

+  * @brief  Disable PLL1 ready interrupt

+  * @rmtoll CIER         PLL1RDYIE      LL_RCC_DisableIT_PLL1RDY

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void)

+{

+  CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);

+}

+

+/**

+  * @brief  Disable PLL2 ready interrupt

+  * @rmtoll CIER         PLL2RDYIE  LL_RCC_DisableIT_PLL2RDY

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void)

+{

+  CLEAR_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);

+}

+

+/**

+  * @brief  Disable PLL3 ready interrupt

+  * @rmtoll CIER         PLL3RDYIE  LL_RCC_DisableIT_PLL3RDY

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_DisableIT_PLL3RDY(void)

+{

+  CLEAR_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);

+}

+

+/**

+  * @brief  Disable LSECSS interrupt

+  * @rmtoll CIER         LSECSSIE  LL_RCC_DisableIT_LSECSS

+  * @retval None

+  */

+__STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)

+{

+  CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);

+}

+

+/**

+  * @brief  Checks if LSI ready interrupt source is enabled or disabled.

+  * @rmtoll CIER         LSIRDYIE      LL_RCC_IsEnableIT_LSIRDY

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSIRDY(void)

+{

+  return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE)?1UL:0UL);

+}

+

+/**

+  * @brief  Checks if LSE ready interrupt source is enabled or disabled.

+  * @rmtoll CIER         LSERDYIE      LL_RCC_IsEnableIT_LSERDY

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSERDY(void)

+{

+  return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE)?1UL:0UL);

+}

+

+/**

+  * @brief  Checks if HSI ready interrupt source is enabled or disabled.

+  * @rmtoll CIER         HSIRDYIE      LL_RCC_IsEnableIT_HSIRDY

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSIRDY(void)

+{

+  return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE)?1UL:0UL);

+}

+

+/**

+  * @brief  Checks if HSE ready interrupt source is enabled or disabled.

+  * @rmtoll CIER         HSERDYIE      LL_RCC_IsEnableIT_HSERDY

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSERDY(void)

+{

+  return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE)?1UL:0UL);

+}

+

+/**

+  * @brief  Checks if CSI ready interrupt source is enabled or disabled.

+  * @rmtoll CIER         CSIRDYIE      LL_RCC_IsEnableIT_CSIRDY

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_CSIRDY(void)

+{

+  return ((READ_BIT(RCC->CIER, RCC_CIER_CSIRDYIE) == RCC_CIER_CSIRDYIE)?1UL:0UL);

+}

+

+/**

+  * @brief  Checks if HSI48 ready interrupt source is enabled or disabled.

+  * @rmtoll CIER         HSI48RDYIE      LL_RCC_IsEnableIT_HSI48RDY

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSI48RDY(void)

+{

+  return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE)?1UL:0UL);

+}

+

+/**

+  * @brief  Checks if PLL1 ready interrupt source is enabled or disabled.

+  * @rmtoll CIER         PLL1RDYIE      LL_RCC_IsEnableIT_PLL1RDY

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL1RDY(void)

+{

+  return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE)?1UL:0UL);

+}

+

+/**

+  * @brief  Checks if PLL2 ready interrupt source is enabled or disabled.

+  * @rmtoll CIER         PLL2RDYIE  LL_RCC_IsEnableIT_PLL2RDY

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL2RDY(void)

+{

+  return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE)?1UL:0UL);

+}

+

+/**

+  * @brief  Checks if PLL3 ready interrupt source is enabled or disabled.

+  * @rmtoll CIER         PLL3RDYIE  LL_RCC_IsEnableIT_PLL3RDY

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL3RDY(void)

+{

+  return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE)?1UL:0UL);

+}

+

+/**

+  * @brief  Checks if LSECSS interrupt source is enabled or disabled.

+  * @rmtoll CIER         LSECSSIE  LL_RCC_IsEnableIT_LSECSS

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSECSS(void)

+{

+  return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE)?1UL:0UL);

+}

+/**

+  * @}

+  */

+

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup RCC_LL_EF_Init De-initialization function

+  * @{

+  */

+void LL_RCC_DeInit(void);

+/**

+  * @}

+  */

+

+/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions

+  * @{

+  */

+uint32_t    LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR);

+

+void        LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);

+void        LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);

+void        LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);

+void        LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);

+

+uint32_t    LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);

+uint32_t    LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);

+uint32_t    LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);

+uint32_t    LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);

+uint32_t    LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);

+uint32_t    LL_RCC_GetADCClockFreq(uint32_t ADCxSource);

+uint32_t    LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);

+uint32_t    LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);

+uint32_t    LL_RCC_GetCECClockFreq(uint32_t CECxSource);

+uint32_t    LL_RCC_GetUSBClockFreq(uint32_t USBxSource);

+uint32_t    LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);

+#if defined(DFSDM2_BASE)

+uint32_t    LL_RCC_GetDFSDM2ClockFreq(uint32_t DFSDMxSource);

+#endif /* DFSDM2 */

+#if defined(DSI)

+uint32_t    LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);

+#endif /* DSI */

+uint32_t    LL_RCC_GetSPDIFClockFreq(uint32_t SPDIFxSource);

+uint32_t    LL_RCC_GetSPIClockFreq(uint32_t SPIxSource);

+uint32_t    LL_RCC_GetSWPClockFreq(uint32_t SWPxSource);

+uint32_t    LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);

+uint32_t    LL_RCC_GetFMCClockFreq(uint32_t FMCxSource);

+#if defined(QUADSPI)

+uint32_t    LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource);

+#endif /* QUADSPI */

+#if defined(OCTOSPI1) || defined(OCTOSPI2)

+uint32_t    LL_RCC_GetOSPIClockFreq(uint32_t OSPIxSource);

+#endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */

+uint32_t    LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource);

+

+

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/**

+  * @}

+  */

+

+

+/**

+  * @}

+  */

+#endif /* defined(RCC) */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_LL_RCC_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_rng.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_rng.h
new file mode 100644
index 0000000000..b174c2ef7d
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_rng.h
@@ -0,0 +1,682 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_rng.h

+  * @author  MCD Application Team

+  * @brief   Header file of RNG LL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_LL_RNG_H

+#define STM32H7xx_LL_RNG_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+#if defined (RNG)

+

+/** @defgroup RNG_LL RNG

+  * @{

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/* Private macros ------------------------------------------------------------*/

+

+/* Exported types ------------------------------------------------------------*/

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup RNG_LL_ES_Init_Struct RNG Exported Init structures

+  * @{

+  */

+

+

+/**

+  * @brief LL RNG Init Structure Definition

+  */

+typedef struct

+{

+  uint32_t         ClockErrorDetection; /*!< Clock error detection.

+                                      This parameter can be one value of @ref RNG_LL_CED.

+

+                                      This parameter can be modified using unitary functions @ref LL_RNG_EnableClkErrorDetect(). */

+} LL_RNG_InitTypeDef;

+

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup RNG_LL_Exported_Constants RNG Exported Constants

+  * @{

+  */

+

+/** @defgroup RNG_LL_CED Clock Error Detection

+  * @{

+  */

+#define LL_RNG_CED_ENABLE         0x00000000U              /*!< Clock error detection enabled  */

+#define LL_RNG_CED_DISABLE        RNG_CR_CED               /*!< Clock error detection disabled */

+/**

+  * @}

+  */

+

+#if defined(RNG_CR_CONDRST)

+/** @defgroup RNG_LL_Clock_Divider_Factor  Value used to configure an internal

+ *            programmable divider acting on the incoming RNG clock

+  * @{

+  */

+#define LL_RNG_CLKDIV_BY_1       (0x00000000UL)                                                           /*!< No clock division                             */

+#define LL_RNG_CLKDIV_BY_2       (RNG_CR_CLKDIV_0)                                                        /*!< 2 RNG clock cycles per internal RNG clock     */

+#define LL_RNG_CLKDIV_BY_4       (RNG_CR_CLKDIV_1)                                                        /*!< 4 RNG clock cycles per internal RNG clock     */

+#define LL_RNG_CLKDIV_BY_8       (RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)                                      /*!< 8 RNG clock cycles per internal RNG clock     */

+#define LL_RNG_CLKDIV_BY_16      (RNG_CR_CLKDIV_2)                                                        /*!< 16 RNG clock cycles per internal RNG clock    */

+#define LL_RNG_CLKDIV_BY_32      (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)                                      /*!< 32 RNG clock cycles per internal RNG clock    */

+#define LL_RNG_CLKDIV_BY_64      (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)                                      /*!< 64 RNG clock cycles per internal RNG clock    */

+#define LL_RNG_CLKDIV_BY_128     (RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)                    /*!< 128 RNG clock cycles per internal RNG clock   */

+#define LL_RNG_CLKDIV_BY_256     (RNG_CR_CLKDIV_3)                                                        /*!< 256 RNG clock cycles per internal RNG clock   */

+#define LL_RNG_CLKDIV_BY_512     (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_0)                                      /*!< 512 RNG clock cycles per internal RNG clock   */

+#define LL_RNG_CLKDIV_BY_1024    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1)                                      /*!< 1024 RNG clock cycles per internal RNG clock  */

+#define LL_RNG_CLKDIV_BY_2048    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)                    /*!< 2048 RNG clock cycles per internal RNG clock  */

+#define LL_RNG_CLKDIV_BY_4096    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2)                                      /*!< 4096 RNG clock cycles per internal RNG clock  */

+#define LL_RNG_CLKDIV_BY_8192    (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_0)                    /*!< 8192 RNG clock cycles per internal RNG clock  */

+#define LL_RNG_CLKDIV_BY_16384   (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1)                    /*!< 16384 RNG clock cycles per internal RNG clock */

+#define LL_RNG_CLKDIV_BY_32768   (RNG_CR_CLKDIV_3 | RNG_CR_CLKDIV_2 | RNG_CR_CLKDIV_1 | RNG_CR_CLKDIV_0)  /*!< 32768 RNG clock cycles per internal RNG clock */

+/**

+  * @}

+  */

+

+/** @defgroup RNG_LL_NIST_Compliance  NIST Compliance configuration

+  * @{

+  */

+#define LL_RNG_NIST_COMPLIANT     (0x00000000UL) /*!< Default NIST compliant configuration*/

+#define LL_RNG_CUSTOM_NIST        (RNG_CR_NISTC) /*!< Custom NIST configuration */

+

+/**

+  * @}

+  */

+

+#endif/*RNG_CR_CONDRST*/

+/** @defgroup RNG_LL_EC_GET_FLAG Get Flags Defines

+  * @brief    Flags defines which can be used with LL_RNG_ReadReg function

+  * @{

+  */

+#define LL_RNG_SR_DRDY RNG_SR_DRDY    /*!< Register contains valid random data */

+#define LL_RNG_SR_CECS RNG_SR_CECS    /*!< Clock error current status */

+#define LL_RNG_SR_SECS RNG_SR_SECS    /*!< Seed error current status */

+#define LL_RNG_SR_CEIS RNG_SR_CEIS    /*!< Clock error interrupt status */

+#define LL_RNG_SR_SEIS RNG_SR_SEIS    /*!< Seed error interrupt status */

+/**

+  * @}

+  */

+

+/** @defgroup RNG_LL_EC_IT IT Defines

+  * @brief    IT defines which can be used with LL_RNG_ReadReg and  LL_RNG_WriteReg macros

+  * @{

+  */

+#define LL_RNG_CR_IE   RNG_CR_IE      /*!< RNG Interrupt enable */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup RNG_LL_Exported_Macros RNG Exported Macros

+  * @{

+  */

+

+/** @defgroup RNG_LL_EM_WRITE_READ Common Write and read registers Macros

+  * @{

+  */

+

+/**

+  * @brief  Write a value in RNG register

+  * @param  __INSTANCE__ RNG Instance

+  * @param  __REG__ Register to be written

+  * @param  __VALUE__ Value to be written in the register

+  * @retval None

+  */

+#define LL_RNG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

+

+/**

+  * @brief  Read a value in RNG register

+  * @param  __INSTANCE__ RNG Instance

+  * @param  __REG__ Register to be read

+  * @retval Register value

+  */

+#define LL_RNG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup RNG_LL_Exported_Functions RNG Exported Functions

+  * @{

+  */

+/** @defgroup RNG_LL_EF_Configuration RNG Configuration functions

+  * @{

+  */

+

+/**

+  * @brief  Enable Random Number Generation

+  * @rmtoll CR           RNGEN         LL_RNG_Enable

+  * @param  RNGx RNG Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RNG_Enable(RNG_TypeDef *RNGx)

+{

+  SET_BIT(RNGx->CR, RNG_CR_RNGEN);

+}

+

+/**

+  * @brief  Disable Random Number Generation

+  * @rmtoll CR           RNGEN         LL_RNG_Disable

+  * @param  RNGx RNG Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx)

+{

+  CLEAR_BIT(RNGx->CR, RNG_CR_RNGEN);

+}

+

+/**

+  * @brief  Check if Random Number Generator is enabled

+  * @rmtoll CR           RNGEN         LL_RNG_IsEnabled

+  * @param  RNGx RNG Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx)

+{

+  return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable Clock Error Detection

+  * @rmtoll CR           CED           LL_RNG_EnableClkErrorDetect

+  * @param  RNGx RNG Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx)

+{

+  CLEAR_BIT(RNGx->CR, RNG_CR_CED);

+}

+

+/**

+  * @brief  Disable RNG Clock Error Detection

+  * @rmtoll CR           CED         LL_RNG_DisableClkErrorDetect

+  * @param  RNGx RNG Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx)

+{

+  SET_BIT(RNGx->CR, RNG_CR_CED);

+}

+

+/**

+  * @brief  Check if RNG Clock Error Detection is enabled

+  * @rmtoll CR           CED         LL_RNG_IsEnabledClkErrorDetect

+  * @param  RNGx RNG Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(RNG_TypeDef *RNGx)

+{

+  return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL);

+}

+

+#if defined(RNG_CR_CONDRST)

+/**

+  * @brief  Set RNG Conditioning Soft Reset bit

+  * @rmtoll CR           CONDRST          LL_RNG_EnableCondReset

+  * @param  RNGx RNG Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RNG_EnableCondReset(RNG_TypeDef *RNGx)

+{

+  SET_BIT(RNGx->CR, RNG_CR_CONDRST);

+}

+

+/**

+  * @brief  Reset RNG  Conditioning Soft Reset bit

+  * @rmtoll CR           CONDRST         LL_RNG_DisableCondReset

+  * @param  RNGx RNG Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RNG_DisableCondReset(RNG_TypeDef *RNGx)

+{

+  CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST);

+}

+

+/**

+  * @brief  Check if RNG Conditioning Soft Reset bit is set

+  * @rmtoll CR           CONDRST         LL_RNG_IsEnabledCondReset

+  * @param  RNGx RNG Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset(RNG_TypeDef *RNGx)

+{

+  return ((READ_BIT(RNGx->CR, RNG_CR_CONDRST) == (RNG_CR_CONDRST)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable RNG Config Lock

+  * @rmtoll CR           CONFIGLOCK          LL_RNG_ConfigLock

+  * @param  RNGx RNG Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RNG_ConfigLock(RNG_TypeDef *RNGx)

+{

+  SET_BIT(RNGx->CR, RNG_CR_CONFIGLOCK);

+}

+

+/**

+  * @brief  Check if RNG Config Lock is enabled

+  * @rmtoll CR           CONFIGLOCK         LL_RNG_IsConfigLocked

+  * @param  RNGx RNG Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(RNG_TypeDef *RNGx)

+{

+  return ((READ_BIT(RNGx->CR, RNG_CR_CONFIGLOCK) == (RNG_CR_CONFIGLOCK)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable NIST Compliance

+  * @rmtoll CR           NISTC         LL_RNG_EnableNistCompliance

+  * @param  RNGx RNG Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx)

+{

+  CLEAR_BIT(RNGx->CR, RNG_CR_NISTC);

+}

+

+/**

+  * @brief  Disable NIST Compliance

+  * @rmtoll CR           NISTC         LL_RNG_DisableNistCompliance

+  * @param  RNGx RNG Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx)

+{

+  SET_BIT(RNGx->CR, RNG_CR_NISTC);

+}

+

+/**

+  * @brief  Check if NIST Compliance is enabled

+  * @rmtoll CR           NISTC         LL_RNG_IsEnabledNistCompliance

+  * @param  RNGx RNG Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(RNG_TypeDef *RNGx)

+{

+  return ((READ_BIT(RNGx->CR, RNG_CR_NISTC) != (RNG_CR_NISTC)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set RNG  Config1 Configuration field value

+  * @rmtoll CR           RNG_CONFIG1         LL_RNG_SetConfig1

+  * @param  RNGx RNG Instance

+  * @param  Config1 Value between 0 and 0x3F

+  * @retval None

+  */

+__STATIC_INLINE void LL_RNG_SetConfig1(RNG_TypeDef *RNGx, uint32_t Config1)

+{

+  MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG1, Config1 << RNG_CR_RNG_CONFIG1_Pos);

+}

+

+/**

+  * @brief  Get RNG  Config1 Configuration field value

+  * @rmtoll CR           RNG_CONFIG1         LL_RNG_GetConfig1

+  * @param  RNGx RNG Instance

+  * @retval Returned Value expressed on 6 bits : Value between 0 and 0x3F

+  */

+__STATIC_INLINE uint32_t LL_RNG_GetConfig1(RNG_TypeDef *RNGx)

+{

+  return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos);

+}

+

+/**

+  * @brief  Set RNG  Config2 Configuration field value

+  * @rmtoll CR           RNG_CONFIG2         LL_RNG_SetConfig2

+  * @param  RNGx RNG Instance

+  * @param  Config2 Value between 0 and 0x7

+  * @retval None

+  */

+__STATIC_INLINE void LL_RNG_SetConfig2(RNG_TypeDef *RNGx, uint32_t Config2)

+{

+  MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG2, Config2 << RNG_CR_RNG_CONFIG2_Pos);

+}

+

+/**

+  * @brief  Get RNG  Config2 Configuration field value

+  * @rmtoll CR           RNG_CONFIG2         LL_RNG_GetConfig2

+  * @param  RNGx RNG Instance

+  * @retval Returned Value expressed on 3 bits : Value between 0 and 0x7

+  */

+__STATIC_INLINE uint32_t LL_RNG_GetConfig2(RNG_TypeDef *RNGx)

+{

+  return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos);

+}

+

+/**

+  * @brief  Set RNG  Config3 Configuration field value

+  * @rmtoll CR           RNG_CONFIG3         LL_RNG_SetConfig3

+  * @param  RNGx RNG Instance

+  * @param  Config3 Value between 0 and 0xF

+  * @retval None

+  */

+__STATIC_INLINE void LL_RNG_SetConfig3(RNG_TypeDef *RNGx, uint32_t Config3)

+{

+  MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG3, Config3 << RNG_CR_RNG_CONFIG3_Pos);

+}

+

+/**

+  * @brief  Get RNG  Config3 Configuration field value

+  * @rmtoll CR           RNG_CONFIG3         LL_RNG_GetConfig3

+  * @param  RNGx RNG Instance

+  * @retval Returned Value expressed on 4 bits : Value between 0 and 0xF

+  */

+__STATIC_INLINE uint32_t LL_RNG_GetConfig3(RNG_TypeDef *RNGx)

+{

+  return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos);

+}

+

+/**

+  * @brief  Set RNG  Clock divider factor

+  * @rmtoll CR           CLKDIV         LL_RNG_SetClockDivider

+  * @param  RNGx RNG Instance

+  * @param  Divider can be one of the following values:

+  *         @arg @ref LL_RNG_CLKDIV_BY_1

+  *         @arg @ref LL_RNG_CLKDIV_BY_2

+  *         @arg @ref LL_RNG_CLKDIV_BY_4

+  *         @arg @ref LL_RNG_CLKDIV_BY_8

+  *         @arg @ref LL_RNG_CLKDIV_BY_16

+  *         @arg @ref LL_RNG_CLKDIV_BY_32

+  *         @arg @ref LL_RNG_CLKDIV_BY_64

+  *         @arg @ref LL_RNG_CLKDIV_BY_128

+  *         @arg @ref LL_RNG_CLKDIV_BY_256

+  *         @arg @ref LL_RNG_CLKDIV_BY_512

+  *         @arg @ref LL_RNG_CLKDIV_BY_1024

+  *         @arg @ref LL_RNG_CLKDIV_BY_2048

+  *         @arg @ref LL_RNG_CLKDIV_BY_4096

+  *         @arg @ref LL_RNG_CLKDIV_BY_8192

+  *         @arg @ref LL_RNG_CLKDIV_BY_16384

+  *         @arg @ref LL_RNG_CLKDIV_BY_32768

+  * @retval None

+  */

+__STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider)

+{

+  MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV, Divider << RNG_CR_CLKDIV_Pos);

+}

+

+/**

+  * @brief  Get RNG  Clock divider factor

+  * @rmtoll CR           CLKDIV         LL_RNG_GetClockDivider

+  * @param  RNGx RNG Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RNG_CLKDIV_BY_1

+  *         @arg @ref LL_RNG_CLKDIV_BY_2

+  *         @arg @ref LL_RNG_CLKDIV_BY_4

+  *         @arg @ref LL_RNG_CLKDIV_BY_8

+  *         @arg @ref LL_RNG_CLKDIV_BY_16

+  *         @arg @ref LL_RNG_CLKDIV_BY_32

+  *         @arg @ref LL_RNG_CLKDIV_BY_64

+  *         @arg @ref LL_RNG_CLKDIV_BY_128

+  *         @arg @ref LL_RNG_CLKDIV_BY_256

+  *         @arg @ref LL_RNG_CLKDIV_BY_512

+  *         @arg @ref LL_RNG_CLKDIV_BY_1024

+  *         @arg @ref LL_RNG_CLKDIV_BY_2048

+  *         @arg @ref LL_RNG_CLKDIV_BY_4096

+  *         @arg @ref LL_RNG_CLKDIV_BY_8192

+  *         @arg @ref LL_RNG_CLKDIV_BY_16384

+  *         @arg @ref LL_RNG_CLKDIV_BY_32768

+  */

+__STATIC_INLINE uint32_t LL_RNG_GetClockDivider(RNG_TypeDef *RNGx)

+{

+  return (uint32_t)READ_BIT(RNGx->CR, RNG_CR_CLKDIV);

+}

+#endif /* RNG_CR_CONDRST */

+/**

+  * @}

+  */

+

+/** @defgroup RNG_LL_EF_FLAG_Management FLAG Management

+  * @{

+  */

+

+/**

+  * @brief  Indicate if the RNG Data ready Flag is set or not

+  * @rmtoll SR           DRDY          LL_RNG_IsActiveFlag_DRDY

+  * @param  RNGx RNG Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx)

+{

+  return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicate if the Clock Error Current Status Flag is set or not

+  * @rmtoll SR           CECS          LL_RNG_IsActiveFlag_CECS

+  * @param  RNGx RNG Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx)

+{

+  return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicate if the Seed Error Current Status Flag is set or not

+  * @rmtoll SR           SECS          LL_RNG_IsActiveFlag_SECS

+  * @param  RNGx RNG Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx)

+{

+  return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicate if the Clock Error Interrupt Status Flag is set or not

+  * @rmtoll SR           CEIS          LL_RNG_IsActiveFlag_CEIS

+  * @param  RNGx RNG Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx)

+{

+  return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicate if the Seed Error Interrupt Status Flag is set or not

+  * @rmtoll SR           SEIS          LL_RNG_IsActiveFlag_SEIS

+  * @param  RNGx RNG Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx)

+{

+  return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear Clock Error interrupt Status (CEIS) Flag

+  * @rmtoll SR           CEIS          LL_RNG_ClearFlag_CEIS

+  * @param  RNGx RNG Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RNG_ClearFlag_CEIS(RNG_TypeDef *RNGx)

+{

+  WRITE_REG(RNGx->SR, ~RNG_SR_CEIS);

+}

+

+/**

+  * @brief  Clear Seed Error interrupt Status (SEIS) Flag

+  * @rmtoll SR           SEIS          LL_RNG_ClearFlag_SEIS

+  * @param  RNGx RNG Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RNG_ClearFlag_SEIS(RNG_TypeDef *RNGx)

+{

+  WRITE_REG(RNGx->SR, ~RNG_SR_SEIS);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup RNG_LL_EF_IT_Management IT Management

+  * @{

+  */

+

+/**

+  * @brief  Enable Random Number Generator Interrupt

+  *         (applies for either Seed error, Clock Error or Data ready interrupts)

+  * @rmtoll CR           IE            LL_RNG_EnableIT

+  * @param  RNGx RNG Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RNG_EnableIT(RNG_TypeDef *RNGx)

+{

+  SET_BIT(RNGx->CR, RNG_CR_IE);

+}

+

+/**

+  * @brief  Disable Random Number Generator Interrupt

+  *         (applies for either Seed error, Clock Error or Data ready interrupts)

+  * @rmtoll CR           IE            LL_RNG_DisableIT

+  * @param  RNGx RNG Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx)

+{

+  CLEAR_BIT(RNGx->CR, RNG_CR_IE);

+}

+

+/**

+  * @brief  Check if Random Number Generator Interrupt is enabled

+  *         (applies for either Seed error, Clock Error or Data ready interrupts)

+  * @rmtoll CR           IE            LL_RNG_IsEnabledIT

+  * @param  RNGx RNG Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx)

+{

+  return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup RNG_LL_EF_Data_Management Data Management

+  * @{

+  */

+

+/**

+  * @brief  Return32-bit Random Number value

+  * @rmtoll DR           RNDATA        LL_RNG_ReadRandData32

+  * @param  RNGx RNG Instance

+  * @retval Generated 32-bit random value

+  */

+__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx)

+{

+  return (uint32_t)(READ_REG(RNGx->DR));

+}

+

+/**

+  * @}

+  */

+

+#if defined (RNG_VER_3_1)

+/** @defgroup RNG_LL_EF_Health_Test_Control Health Test Control

+  * @{

+  */

+

+/**

+  * @brief  Set RNG Health Test Control

+  * @rmtoll HTCR       HTCFG       LL_RNG_SetHealthConfig

+  * @param  RNGx RNG Instance

+  * @param  HTCFG can be values of 32 bits

+  * @retval None

+  */

+__STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG)

+{

+  WRITE_REG(RNGx->HTCR, HTCFG);

+}

+

+/**

+  * @brief  Get RNG Health Test Control

+  * @rmtoll HTCR         HTCFG        LL_RNG_GetHealthConfig

+  * @param  RNGx RNG Instance

+  * @retval Return 32-bit RNG Health Test configuration

+  */

+__STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(RNG_TypeDef *RNGx)

+{

+  return (uint32_t)READ_REG(RNGx->HTCR);

+}

+

+/**

+  * @}

+  */

+#endif  /*RNG_VER_3_1*/

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions

+  * @{

+  */

+ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct);

+void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct);

+ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx);

+

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* RNG */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* __STM32H7xx_LL_RNG_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_rtc.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_rtc.h
new file mode 100644
index 0000000000..044030130d
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_rtc.h
@@ -0,0 +1,5378 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_rtc.h

+  * @author  MCD Application Team

+  * @brief   Header file of RTC LL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_LL_RTC_H

+#define STM32H7xx_LL_RTC_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+#if defined(RTC)

+

+/** @defgroup RTC_LL RTC

+  * @{

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup RTC_LL_Private_Constants RTC Private Constants

+  * @{

+  */

+/* Masks Definition */

+#define RTC_LL_INIT_MASK              0xFFFFFFFFU

+#define RTC_LL_RSF_MASK               0xFFFFFF5FU

+

+/* Write protection defines */

+#define RTC_WRITE_PROTECTION_DISABLE  0xFFU

+#define RTC_WRITE_PROTECTION_ENABLE_1 0xCAU

+#define RTC_WRITE_PROTECTION_ENABLE_2 0x53U

+

+/* Defines used to combine date & time */

+#define RTC_OFFSET_WEEKDAY            24U

+#define RTC_OFFSET_DAY                16U

+#define RTC_OFFSET_MONTH              8U

+#define RTC_OFFSET_HOUR               16U

+#define RTC_OFFSET_MINUTE             8U

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup RTC_LL_Private_Macros RTC Private Macros

+  * @{

+  */

+/**

+  * @}

+  */

+#endif /*USE_FULL_LL_DRIVER*/

+

+/* Exported types ------------------------------------------------------------*/

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup RTC_LL_ES_INIT RTC Exported Init structure

+  * @{

+  */

+

+/**

+  * @brief  RTC Init structures definition

+  */

+typedef struct

+{

+  uint32_t HourFormat;   /*!< Specifies the RTC Hours Format.

+                              This parameter can be a value of @ref RTC_LL_EC_HOURFORMAT

+

+                              This feature can be modified afterwards using unitary function

+                              @ref LL_RTC_SetHourFormat(). */

+

+  uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value.

+                              This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F

+

+                              This feature can be modified afterwards using unitary function

+                              @ref LL_RTC_SetAsynchPrescaler(). */

+

+  uint32_t SynchPrescaler;  /*!< Specifies the RTC Synchronous Predivider value.

+                              This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF

+

+                              This feature can be modified afterwards using unitary function

+                              @ref LL_RTC_SetSynchPrescaler(). */

+} LL_RTC_InitTypeDef;

+

+/**

+  * @brief  RTC Time structure definition

+  */

+typedef struct

+{

+  uint32_t TimeFormat; /*!< Specifies the RTC AM/PM Time.

+                            This parameter can be a value of @ref RTC_LL_EC_TIME_FORMAT

+

+                            This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetFormat(). */

+

+  uint8_t Hours;       /*!< Specifies the RTC Time Hours.

+                            This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the @ref LL_RTC_TIME_FORMAT_PM is selected.

+                            This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the @ref LL_RTC_TIME_FORMAT_AM_OR_24 is selected.

+

+                            This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetHour(). */

+

+  uint8_t Minutes;     /*!< Specifies the RTC Time Minutes.

+                            This parameter must be a number between Min_Data = 0 and Max_Data = 59

+

+                            This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetMinute(). */

+

+  uint8_t Seconds;     /*!< Specifies the RTC Time Seconds.

+                            This parameter must be a number between Min_Data = 0 and Max_Data = 59

+

+                            This feature can be modified afterwards using unitary function @ref LL_RTC_TIME_SetSecond(). */

+} LL_RTC_TimeTypeDef;

+

+/**

+  * @brief  RTC Date structure definition

+  */

+typedef struct

+{

+  uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.

+                         This parameter can be a value of @ref RTC_LL_EC_WEEKDAY

+

+                         This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetWeekDay(). */

+

+  uint8_t Month;    /*!< Specifies the RTC Date Month.

+                         This parameter can be a value of @ref RTC_LL_EC_MONTH

+

+                         This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetMonth(). */

+

+  uint8_t Day;      /*!< Specifies the RTC Date Day.

+                         This parameter must be a number between Min_Data = 1 and Max_Data = 31

+

+                         This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetDay(). */

+

+  uint8_t Year;     /*!< Specifies the RTC Date Year.

+                         This parameter must be a number between Min_Data = 0 and Max_Data = 99

+

+                         This feature can be modified afterwards using unitary function @ref LL_RTC_DATE_SetYear(). */

+} LL_RTC_DateTypeDef;

+

+/**

+  * @brief  RTC Alarm structure definition

+  */

+typedef struct

+{

+  LL_RTC_TimeTypeDef AlarmTime;  /*!< Specifies the RTC Alarm Time members. */

+

+  uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.

+                                      This parameter can be a value of @ref RTC_LL_EC_ALMA_MASK for ALARM A or @ref RTC_LL_EC_ALMB_MASK for ALARM B.

+

+                                      This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetMask() for ALARM A

+                                      or @ref LL_RTC_ALMB_SetMask() for ALARM B

+                                 */

+

+  uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on day or WeekDay.

+                                      This parameter can be a value of @ref RTC_LL_EC_ALMA_WEEKDAY_SELECTION for ALARM A or @ref RTC_LL_EC_ALMB_WEEKDAY_SELECTION for ALARM B

+

+                                      This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_EnableWeekday() or @ref LL_RTC_ALMA_DisableWeekday()

+                                      for ALARM A or @ref LL_RTC_ALMB_EnableWeekday() or @ref LL_RTC_ALMB_DisableWeekday() for ALARM B

+                                 */

+

+  uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Day/WeekDay.

+                                      If AlarmDateWeekDaySel set to day, this parameter  must be a number between Min_Data = 1 and Max_Data = 31.

+

+                                      This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetDay()

+                                      for ALARM A or @ref LL_RTC_ALMB_SetDay() for ALARM B.

+

+                                      If AlarmDateWeekDaySel set to Weekday, this parameter can be a value of @ref RTC_LL_EC_WEEKDAY.

+

+                                      This feature can be modified afterwards using unitary function @ref LL_RTC_ALMA_SetWeekDay()

+                                      for ALARM A or @ref LL_RTC_ALMB_SetWeekDay() for ALARM B.

+                                 */

+} LL_RTC_AlarmTypeDef;

+

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup RTC_LL_Exported_Constants RTC Exported Constants

+  * @{

+  */

+

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup RTC_LL_EC_FORMAT FORMAT

+  * @{

+  */

+#define LL_RTC_FORMAT_BIN                  0x00000000U /*!< Binary data format */

+#define LL_RTC_FORMAT_BCD                  0x00000001U /*!< BCD data format */

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EC_ALMA_WEEKDAY_SELECTION RTC Alarm A Date WeekDay

+  * @{

+  */

+#define LL_RTC_ALMA_DATEWEEKDAYSEL_DATE    0x00000000U             /*!< Alarm A Date is selected */

+#define LL_RTC_ALMA_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMAR_WDSEL        /*!< Alarm A WeekDay is selected */

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EC_ALMB_WEEKDAY_SELECTION RTC Alarm B Date WeekDay

+  * @{

+  */

+#define LL_RTC_ALMB_DATEWEEKDAYSEL_DATE    0x00000000U             /*!< Alarm B Date is selected */

+#define LL_RTC_ALMB_DATEWEEKDAYSEL_WEEKDAY RTC_ALRMBR_WDSEL        /*!< Alarm B WeekDay is selected */

+/**

+  * @}

+  */

+

+#endif /* USE_FULL_LL_DRIVER */

+

+/** @defgroup RTC_LL_EC_GET_FLAG Get Flags Defines

+  * @brief    Flags defines which can be used with LL_RTC_ReadReg function

+  * @{

+  */

+#if defined(RTC_SCR_CALRAF)

+#define LL_RTC_SCR_ITSF                    RTC_SCR_CITSF

+#define LL_RTC_SCR_TSOVF                   RTC_SCR_CTSOVF

+#define LL_RTC_SCR_TSF                     RTC_SCR_CTSF

+#define LL_RTC_SCR_WUTF                    RTC_SCR_CWUTF

+#define LL_RTC_SCR_ALRBF                   RTC_SCR_CALRBF

+#define LL_RTC_SCR_ALRAF                   RTC_SCR_CALRAF

+#endif /* RTC_SCR_CALRAF */

+

+#if defined(RTC_ICSR_ALRAWF)

+#define LL_RTC_ICSR_RECALPF                RTC_ICSR_RECALPF

+#define LL_RTC_ICSR_INITF                  RTC_ICSR_INITF

+#define LL_RTC_ICSR_RSF                    RTC_ICSR_RSF

+#define LL_RTC_ICSR_INITS                  RTC_ICSR_INITS

+#define LL_RTC_ICSR_SHPF                   RTC_ICSR_SHPF

+#define LL_RTC_ICSR_WUTWF                  RTC_ICSR_WUTWF

+#endif /* RTC_ICSR_ALRAWF */

+#if defined(RTC_ISR_ALRAWF)

+#define LL_RTC_ISR_ITSF                    RTC_ISR_ITSF

+#define LL_RTC_ISR_RECALPF                 RTC_ISR_RECALPF

+#define LL_RTC_ISR_TAMP3F                  RTC_ISR_TAMP3F

+#define LL_RTC_ISR_TAMP2F                  RTC_ISR_TAMP2F

+#define LL_RTC_ISR_TAMP1F                  RTC_ISR_TAMP1F

+#define LL_RTC_ISR_TSOVF                   RTC_ISR_TSOVF

+#define LL_RTC_ISR_TSF                     RTC_ISR_TSF

+#define LL_RTC_ISR_WUTF                    RTC_ISR_WUTF

+#define LL_RTC_ISR_ALRBF                   RTC_ISR_ALRBF

+#define LL_RTC_ISR_ALRAF                   RTC_ISR_ALRAF

+#define LL_RTC_ISR_INITF                   RTC_ISR_INITF

+#define LL_RTC_ISR_RSF                     RTC_ISR_RSF

+#define LL_RTC_ISR_INITS                   RTC_ISR_INITS

+#define LL_RTC_ISR_SHPF                    RTC_ISR_SHPF

+#define LL_RTC_ISR_WUTWF                   RTC_ISR_WUTWF

+#define LL_RTC_ISR_ALRBWF                  RTC_ISR_ALRBWF

+#define LL_RTC_ISR_ALRAWF                  RTC_ISR_ALRAWF

+#endif /* RTC_ISR_ALRAWF */

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EC_IT IT Defines

+  * @brief    IT defines which can be used with LL_RTC_ReadReg and  LL_RTC_WriteReg functions

+  * @{

+  */

+#define LL_RTC_CR_TSIE                     RTC_CR_TSIE

+#define LL_RTC_CR_WUTIE                    RTC_CR_WUTIE

+#define LL_RTC_CR_ALRBIE                   RTC_CR_ALRBIE

+#define LL_RTC_CR_ALRAIE                   RTC_CR_ALRAIE

+#if defined(RTC_TAMPCR_TAMP3E)

+#define LL_RTC_TAMPCR_TAMP3IE              RTC_TAMPCR_TAMP3IE

+#endif /* RTC_TAMPCR_TAMP3E */

+#if defined(RTC_TAMPCR_TAMP2E)

+#define LL_RTC_TAMPCR_TAMP2IE              RTC_TAMPCR_TAMP2IE

+#endif /* RTC_TAMPCR_TAMP2E */

+#if defined(RTC_TAMPCR_TAMP1E)

+#define LL_RTC_TAMPCR_TAMP1IE              RTC_TAMPCR_TAMP1IE

+#endif /* RTC_TAMPCR_TAMP1E */

+#if defined(RTC_TAMPCR_TAMPIE)

+#define LL_RTC_TAMPCR_TAMPIE               RTC_TAMPCR_TAMPIE

+#endif /* RTC_TAMPCR_TAMPIE */

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EC_WEEKDAY  WEEK DAY

+  * @{

+  */

+#define LL_RTC_WEEKDAY_MONDAY              (uint8_t)0x01 /*!< Monday    */

+#define LL_RTC_WEEKDAY_TUESDAY             (uint8_t)0x02 /*!< Tuesday   */

+#define LL_RTC_WEEKDAY_WEDNESDAY           (uint8_t)0x03 /*!< Wednesday */

+#define LL_RTC_WEEKDAY_THURSDAY            (uint8_t)0x04 /*!< Thrusday  */

+#define LL_RTC_WEEKDAY_FRIDAY              (uint8_t)0x05 /*!< Friday    */

+#define LL_RTC_WEEKDAY_SATURDAY            (uint8_t)0x06 /*!< Saturday  */

+#define LL_RTC_WEEKDAY_SUNDAY              (uint8_t)0x07 /*!< Sunday    */

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EC_MONTH  MONTH

+  * @{

+  */

+#define LL_RTC_MONTH_JANUARY               (uint8_t)0x01  /*!< January   */

+#define LL_RTC_MONTH_FEBRUARY              (uint8_t)0x02  /*!< February  */

+#define LL_RTC_MONTH_MARCH                 (uint8_t)0x03  /*!< March     */

+#define LL_RTC_MONTH_APRIL                 (uint8_t)0x04  /*!< April     */

+#define LL_RTC_MONTH_MAY                   (uint8_t)0x05  /*!< May       */

+#define LL_RTC_MONTH_JUNE                  (uint8_t)0x06  /*!< June      */

+#define LL_RTC_MONTH_JULY                  (uint8_t)0x07  /*!< July      */

+#define LL_RTC_MONTH_AUGUST                (uint8_t)0x08  /*!< August    */

+#define LL_RTC_MONTH_SEPTEMBER             (uint8_t)0x09  /*!< September */

+#define LL_RTC_MONTH_OCTOBER               (uint8_t)0x10  /*!< October   */

+#define LL_RTC_MONTH_NOVEMBER              (uint8_t)0x11  /*!< November  */

+#define LL_RTC_MONTH_DECEMBER              (uint8_t)0x12  /*!< December  */

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EC_HOURFORMAT  HOUR FORMAT

+  * @{

+  */

+#define LL_RTC_HOURFORMAT_24HOUR           0x00000000U           /*!< 24 hour/day format */

+#define LL_RTC_HOURFORMAT_AMPM             RTC_CR_FMT            /*!< AM/PM hour format */

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EC_ALARMOUT  ALARM OUTPUT

+  * @{

+  */

+#define LL_RTC_ALARMOUT_DISABLE            0x00000000U             /*!< Output disabled */

+#define LL_RTC_ALARMOUT_ALMA               RTC_CR_OSEL_0           /*!< Alarm A output enabled */

+#define LL_RTC_ALARMOUT_ALMB               RTC_CR_OSEL_1           /*!< Alarm B output enabled */

+#define LL_RTC_ALARMOUT_WAKEUP             RTC_CR_OSEL             /*!< Wakeup output enabled */

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EC_ALARM_OUTPUTTYPE  ALARM OUTPUT TYPE

+  * @{

+  */

+#if defined(RTC_CR_TAMPALRM_TYPE)

+#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN  RTC_CR_TAMPALRM_TYPE   /*!< RTC_ALARM is open-drain output */

+#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL   0x00000000U            /*!< RTC_ALARM is push-pull output */

+#endif /* RTC_CR_TAMPALRM_TYPE */

+#if defined(RTC_OR_ALARMOUTTYPE)

+#define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN  0x00000000U            /*!< RTC_ALARM, when mapped on PC13, is open-drain output */

+#define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL   RTC_OR_ALARMOUTTYPE    /*!< RTC_ALARM, when mapped on PC13, is push-pull output */

+#endif /* RTC_OR_ALARMOUTTYPE */

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN  OUTPUT POLARITY PIN

+  * @{

+  */

+#define LL_RTC_OUTPUTPOLARITY_PIN_HIGH     0x00000000U           /*!< Pin is high when ALRAF/ALRBF/WUTF is asserted (depending on OSEL)*/

+#define LL_RTC_OUTPUTPOLARITY_PIN_LOW      RTC_CR_POL            /*!< Pin is low when ALRAF/ALRBF/WUTF is asserted (depending on OSEL) */

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EC_TIME_FORMAT TIME FORMAT

+  * @{

+  */

+#define LL_RTC_TIME_FORMAT_AM_OR_24        0x00000000U           /*!< AM or 24-hour format */

+#define LL_RTC_TIME_FORMAT_PM              RTC_TR_PM             /*!< PM */

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EC_SHIFT_SECOND  SHIFT SECOND

+  * @{

+  */

+#define LL_RTC_SHIFT_SECOND_DELAY          0x00000000U           /* Delay (seconds) = SUBFS / (PREDIV_S + 1) */

+#define LL_RTC_SHIFT_SECOND_ADVANCE        RTC_SHIFTR_ADD1S      /* Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))) */

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EC_ALMA_MASK  ALARMA MASK

+  * @{

+  */

+#define LL_RTC_ALMA_MASK_NONE              0x00000000U             /*!< No masks applied on Alarm A*/

+#define LL_RTC_ALMA_MASK_DATEWEEKDAY       RTC_ALRMAR_MSK4         /*!< Date/day do not care in Alarm A comparison */

+#define LL_RTC_ALMA_MASK_HOURS             RTC_ALRMAR_MSK3         /*!< Hours do not care in Alarm A comparison */

+#define LL_RTC_ALMA_MASK_MINUTES           RTC_ALRMAR_MSK2         /*!< Minutes do not care in Alarm A comparison */

+#define LL_RTC_ALMA_MASK_SECONDS           RTC_ALRMAR_MSK1         /*!< Seconds do not care in Alarm A comparison */

+#define LL_RTC_ALMA_MASK_ALL               (RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1) /*!< Masks all */

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EC_ALMA_TIME_FORMAT  ALARMA TIME FORMAT

+  * @{

+  */

+#define LL_RTC_ALMA_TIME_FORMAT_AM         0x00000000U           /*!< AM or 24-hour format */

+#define LL_RTC_ALMA_TIME_FORMAT_PM         RTC_ALRMAR_PM         /*!< PM */

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EC_ALMB_MASK  ALARMB MASK

+  * @{

+  */

+#define LL_RTC_ALMB_MASK_NONE              0x00000000U             /*!< No masks applied on Alarm B*/

+#define LL_RTC_ALMB_MASK_DATEWEEKDAY       RTC_ALRMBR_MSK4         /*!< Date/day do not care in Alarm B comparison */

+#define LL_RTC_ALMB_MASK_HOURS             RTC_ALRMBR_MSK3         /*!< Hours do not care in Alarm B comparison */

+#define LL_RTC_ALMB_MASK_MINUTES           RTC_ALRMBR_MSK2         /*!< Minutes do not care in Alarm B comparison */

+#define LL_RTC_ALMB_MASK_SECONDS           RTC_ALRMBR_MSK1         /*!< Seconds do not care in Alarm B comparison */

+#define LL_RTC_ALMB_MASK_ALL               (RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1) /*!< Masks all */

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EC_ALMB_TIME_FORMAT  ALARMB TIME FORMAT

+  * @{

+  */

+#define LL_RTC_ALMB_TIME_FORMAT_AM         0x00000000U           /*!< AM or 24-hour format */

+#define LL_RTC_ALMB_TIME_FORMAT_PM         RTC_ALRMBR_PM         /*!< PM */

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EC_TIMESTAMP_EDGE  TIMESTAMP EDGE

+  * @{

+  */

+#define LL_RTC_TIMESTAMP_EDGE_RISING       0x00000000U           /*!< RTC_TS input rising edge generates a time-stamp event */

+#define LL_RTC_TIMESTAMP_EDGE_FALLING      RTC_CR_TSEDGE         /*!< RTC_TS input falling edge generates a time-stamp even */

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EC_TS_TIME_FORMAT  TIMESTAMP TIME FORMAT

+  * @{

+  */

+#define LL_RTC_TS_TIME_FORMAT_AM           0x00000000U           /*!< AM or 24-hour format */

+#define LL_RTC_TS_TIME_FORMAT_PM           RTC_TSTR_PM           /*!< PM */

+/**

+  * @}

+  */

+

+#if defined(TAMP_CR1_TAMP1E)

+/** @defgroup RTC_LL_EC_TAMPER  TAMPER

+  * @{

+  */

+#define LL_RTC_TAMPER_1                    TAMP_CR1_TAMP1E /*!< Tamper 1 input detection */

+#endif /* TAMP_CR1_TAMP1E */

+#if defined(TAMP_CR1_TAMP2E)

+#define LL_RTC_TAMPER_2                    TAMP_CR1_TAMP2E /*!< Tamper 2 input detection */

+#endif /* TAMP_CR1_TAMP2E */

+#if defined(TAMP_CR1_TAMP3E)

+#define LL_RTC_TAMPER_3                    TAMP_CR1_TAMP3E /*!< Tamper 3 input detection */

+#endif /* TAMP_CR1_TAMP3E */

+/**

+  * @}

+  */

+

+#if defined(TAMP_CR1_TAMP1E)

+/** @defgroup RTC_LL_EC_TAMPER_MASK  TAMPER MASK

+  * @{

+  */

+#define LL_RTC_TAMPER_MASK_TAMPER1         TAMP_CR2_TAMP1MSK /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware. The backup registers are not erased */

+#endif /* TAMP_CR1_TAMP1E */

+#if defined(TAMP_CR1_TAMP2E)

+#define LL_RTC_TAMPER_MASK_TAMPER2         TAMP_CR2_TAMP2MSK /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */

+#endif /* TAMP_CR1_TAMP2E */

+#if defined(TAMP_CR1_TAMP3E)

+#define LL_RTC_TAMPER_MASK_TAMPER3         TAMP_CR2_TAMP3MSK /*!< Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased. */

+#endif /* TAMP_CR1_TAMP3E */

+/**

+  * @}

+  */

+

+#if defined(TAMP_CR1_TAMP1E)

+/** @defgroup RTC_LL_EC_TAMPER_NOERASE  TAMPER NO ERASE

+  * @{

+  */

+#define LL_RTC_TAMPER_NOERASE_TAMPER1      TAMP_CR2_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */

+#endif /* TAMP_CR1_TAMP1E */

+#if defined(TAMP_CR1_TAMP2E)

+#define LL_RTC_TAMPER_NOERASE_TAMPER2      TAMP_CR2_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */

+#endif /* TAMP_CR1_TAMP2E */

+#if defined(TAMP_CR1_TAMP3E)

+#define LL_RTC_TAMPER_NOERASE_TAMPER3      TAMP_CR2_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */

+#endif /* TAMP_CR1_TAMP3E */

+/**

+  * @}

+  */

+

+#if defined(TAMP_FLTCR_TAMPPRCH)

+/** @defgroup RTC_LL_EC_TAMPER_DURATION  TAMPER DURATION

+  * @{

+  */

+#define LL_RTC_TAMPER_DURATION_1RTCCLK     0x00000000U            /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle  */

+#define LL_RTC_TAMPER_DURATION_2RTCCLK     TAMP_FLTCR_TAMPPRCH_0  /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */

+#define LL_RTC_TAMPER_DURATION_4RTCCLK     TAMP_FLTCR_TAMPPRCH_1  /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */

+#define LL_RTC_TAMPER_DURATION_8RTCCLK     TAMP_FLTCR_TAMPPRCH    /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */

+/**

+  * @}

+  */

+#endif /* TAMP_FLTCR_TAMPPRCH */

+

+#if defined(TAMP_FLTCR_TAMPFLT)

+/** @defgroup RTC_LL_EC_TAMPER_FILTER  TAMPER FILTER

+  * @{

+  */

+#define LL_RTC_TAMPER_FILTER_DISABLE       0x00000000U             /*!< Tamper filter is disabled */

+#define LL_RTC_TAMPER_FILTER_2SAMPLE       TAMP_FLTCR_TAMPFLT_0    /*!< Tamper is activated after 2 consecutive samples at the active level */

+#define LL_RTC_TAMPER_FILTER_4SAMPLE       TAMP_FLTCR_TAMPFLT_1    /*!< Tamper is activated after 4 consecutive samples at the active level */

+#define LL_RTC_TAMPER_FILTER_8SAMPLE       TAMP_FLTCR_TAMPFLT      /*!< Tamper is activated after 8 consecutive samples at the active level. */

+/**

+  * @}

+  */

+#endif /* TAMP_FLTCR_TAMPFLT */

+

+#if defined(TAMP_FLTCR_TAMPFREQ)

+/** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV  TAMPER SAMPLING FREQUENCY DIVIDER

+  * @{

+  */

+#define LL_RTC_TAMPER_SAMPLFREQDIV_32768   0x00000000U                                     /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 32768 */

+#define LL_RTC_TAMPER_SAMPLFREQDIV_16384   TAMP_FLTCR_TAMPFREQ_0                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 16384 */

+#define LL_RTC_TAMPER_SAMPLFREQDIV_8192    TAMP_FLTCR_TAMPFREQ_1                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 8192 */

+#define LL_RTC_TAMPER_SAMPLFREQDIV_4096    (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 4096 */

+#define LL_RTC_TAMPER_SAMPLFREQDIV_2048    TAMP_FLTCR_TAMPFREQ_2                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 2048 */

+#define LL_RTC_TAMPER_SAMPLFREQDIV_1024    (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 1024 */

+#define LL_RTC_TAMPER_SAMPLFREQDIV_512     (TAMP_FLTCR_TAMPFREQ_2 | TAMP_FLTCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 512 */

+#define LL_RTC_TAMPER_SAMPLFREQDIV_256     TAMP_FLTCR_TAMPFREQ                             /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 256 */

+/**

+  * @}

+  */

+#endif /* TAMP_FLTCR_TAMPFREQ */

+

+#if defined(TAMP_CR1_TAMP1E)

+/** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL  TAMPER ACTIVE LEVEL

+  * @{

+  */

+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1    TAMP_CR2_TAMP1TRG /*!< Tamper 1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */

+#endif /* TAMP_CR1_TAMP1E */

+#if defined(TAMP_CR1_TAMP2E)

+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2    TAMP_CR2_TAMP2TRG /*!< Tamper 2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */

+#endif /* TAMP_CR1_TAMP2E */

+#if defined(TAMP_CR1_TAMP3E)

+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3    TAMP_CR2_TAMP3TRG /*!< Tamper 3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event */

+#endif /* TAMP_CR1_TAMP3E */

+/**

+  * @}

+  */

+

+#if defined (RTC_TAMPCR_TAMP1E)

+/** @defgroup RTC_LL_EC_TAMPER  TAMPER

+  * @{

+  */

+#define LL_RTC_TAMPER_1                    RTC_TAMPCR_TAMP1E /*!< RTC_TAMP1 input detection */

+#endif /* RTC_TAMPCR_TAMP1E */

+#if defined (RTC_TAMPCR_TAMP2E)

+#define LL_RTC_TAMPER_2                    RTC_TAMPCR_TAMP2E /*!< RTC_TAMP2 input detection */

+#endif /* RTC_TAMPCR_TAMP2E */

+#if defined (RTC_TAMPCR_TAMP3E)

+#define LL_RTC_TAMPER_3                    RTC_TAMPCR_TAMP3E /*!< RTC_TAMP3 input detection */

+#endif /* RTC_TAMPCR_TAMP3E */

+/**

+  * @}

+  */

+

+#if defined (RTC_TAMPCR_TAMP1E)

+/** @defgroup RTC_LL_EC_TAMPER_MASK  TAMPER MASK

+  * @{

+  */

+#define LL_RTC_TAMPER_MASK_TAMPER1         RTC_TAMPCR_TAMP1MF /*!< Tamper 1 event generates a trigger event. TAMP1F is masked and internally cleared by hardware.The backup registers are not erased */

+#endif /* RTC_TAMPCR_TAMP1E */

+#if defined (RTC_TAMPCR_TAMP2E)

+#define LL_RTC_TAMPER_MASK_TAMPER2         RTC_TAMPCR_TAMP2MF /*!< Tamper 2 event generates a trigger event. TAMP2F is masked and internally cleared by hardware. The backup registers are not erased. */

+#endif /* RTC_TAMPCR_TAMP2E */

+#if defined (RTC_TAMPCR_TAMP3E)

+#define LL_RTC_TAMPER_MASK_TAMPER3         RTC_TAMPCR_TAMP3MF /*!< Tamper 3 event generates a trigger event. TAMP3F is masked and internally cleared by hardware. The backup registers are not erased */

+#endif /* RTC_TAMPCR_TAMP3E */

+/**

+  * @}

+  */

+

+#if defined (RTC_TAMPCR_TAMP1E)

+/** @defgroup RTC_LL_EC_TAMPER_NOERASE  TAMPER NO ERASE

+  * @{

+  */

+#define LL_RTC_TAMPER_NOERASE_TAMPER1      RTC_TAMPCR_TAMP1NOERASE /*!< Tamper 1 event does not erase the backup registers. */

+#endif /* RTC_TAMPCR_TAMP1E */

+#if defined (RTC_TAMPCR_TAMP2E)

+#define LL_RTC_TAMPER_NOERASE_TAMPER2      RTC_TAMPCR_TAMP2NOERASE /*!< Tamper 2 event does not erase the backup registers. */

+#endif /* RTC_TAMPCR_TAMP2E */

+#if defined (RTC_TAMPCR_TAMP3E)

+#define LL_RTC_TAMPER_NOERASE_TAMPER3      RTC_TAMPCR_TAMP3NOERASE /*!< Tamper 3 event does not erase the backup registers. */

+#endif /* RTC_TAMPCR_TAMP3E */

+/**

+  * @}

+  */

+

+#if defined(RTC_TAMPCR_TAMPPRCH)

+/** @defgroup RTC_LL_EC_TAMPER_DURATION  TAMPER DURATION

+  * @{

+  */

+#define LL_RTC_TAMPER_DURATION_1RTCCLK     0x00000000U                             /*!< Tamper pins are pre-charged before sampling during 1 RTCCLK cycle  */

+#define LL_RTC_TAMPER_DURATION_2RTCCLK     RTC_TAMPCR_TAMPPRCH_0  /*!< Tamper pins are pre-charged before sampling during 2 RTCCLK cycles */

+#define LL_RTC_TAMPER_DURATION_4RTCCLK     RTC_TAMPCR_TAMPPRCH_1  /*!< Tamper pins are pre-charged before sampling during 4 RTCCLK cycles */

+#define LL_RTC_TAMPER_DURATION_8RTCCLK     RTC_TAMPCR_TAMPPRCH    /*!< Tamper pins are pre-charged before sampling during 8 RTCCLK cycles */

+/**

+  * @}

+  */

+#endif /* RTC_TAMPCR_TAMPPRCH */

+

+#if defined(RTC_TAMPCR_TAMPFLT)

+/** @defgroup RTC_LL_EC_TAMPER_FILTER  TAMPER FILTER

+  * @{

+  */

+#define LL_RTC_TAMPER_FILTER_DISABLE       0x00000000U                              /*!< Tamper filter is disabled */

+#define LL_RTC_TAMPER_FILTER_2SAMPLE       RTC_TAMPCR_TAMPFLT_0    /*!< Tamper is activated after 2 consecutive samples at the active level */

+#define LL_RTC_TAMPER_FILTER_4SAMPLE       RTC_TAMPCR_TAMPFLT_1    /*!< Tamper is activated after 4 consecutive samples at the active level */

+#define LL_RTC_TAMPER_FILTER_8SAMPLE       RTC_TAMPCR_TAMPFLT      /*!< Tamper is activated after 8 consecutive samples at the active level. */

+/**

+  * @}

+  */

+#endif /* RTC_TAMPCR_TAMPFLT */

+

+#if defined(RTC_TAMPCR_TAMPFREQ)

+/** @defgroup RTC_LL_EC_TAMPER_SAMPLFREQDIV  TAMPER SAMPLING FREQUENCY DIVIDER

+  * @{

+  */

+#define LL_RTC_TAMPER_SAMPLFREQDIV_32768   0x00000000U                                                      /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 32768 */

+#define LL_RTC_TAMPER_SAMPLFREQDIV_16384   RTC_TAMPCR_TAMPFREQ_0                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 16384 */

+#define LL_RTC_TAMPER_SAMPLFREQDIV_8192    RTC_TAMPCR_TAMPFREQ_1                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 8192 */

+#define LL_RTC_TAMPER_SAMPLFREQDIV_4096    (RTC_TAMPCR_TAMPFREQ_1 | RTC_TAMPCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 4096 */

+#define LL_RTC_TAMPER_SAMPLFREQDIV_2048    RTC_TAMPCR_TAMPFREQ_2                           /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 2048 */

+#define LL_RTC_TAMPER_SAMPLFREQDIV_1024    (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_0) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 1024 */

+#define LL_RTC_TAMPER_SAMPLFREQDIV_512     (RTC_TAMPCR_TAMPFREQ_2 | RTC_TAMPCR_TAMPFREQ_1) /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 512 */

+#define LL_RTC_TAMPER_SAMPLFREQDIV_256     RTC_TAMPCR_TAMPFREQ                             /*!< Each of the tamper inputs are sampled with a frequency =  RTCCLK / 256 */

+/**

+  * @}

+  */

+#endif /* RTC_TAMPCR_TAMPFREQ */

+

+#if defined (RTC_TAMPCR_TAMP1E)

+/** @defgroup RTC_LL_EC_TAMPER_ACTIVELEVEL  TAMPER ACTIVE LEVEL

+  * @{

+  */

+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP1    RTC_TAMPCR_TAMP1TRG /*!< RTC_TAMP1 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/

+#endif /* RTC_TAMPCR_TAMP1E */

+#if defined (RTC_TAMPCR_TAMP2E)

+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP2    RTC_TAMPCR_TAMP2TRG /*!< RTC_TAMP2 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/

+#endif /* RTC_TAMPCR_TAMP2E */

+#if defined (RTC_TAMPCR_TAMP3E)

+#define LL_RTC_TAMPER_ACTIVELEVEL_TAMP3    RTC_TAMPCR_TAMP3TRG /*!< RTC_TAMP3 input falling edge (if TAMPFLT = 00) or staying high (if TAMPFLT != 00) triggers a tamper detection event*/

+#endif /* RTC_TAMPCR_TAMP3E */

+/**

+  * @}

+  */

+

+#if defined(TAMP_ATCR1_TAMP1AM)

+/** @defgroup RTC_LL_EC_ACTIVE_MODE   ACTIVE TAMPER MODE

+  * @{

+  */

+#define LL_RTC_TAMPER_ATAMP_TAMP1AM               TAMP_ATCR1_TAMP1AM /*!< tamper 1 is active */

+#endif /* TAMP_ATCR1_TAMP1AM */

+#if defined(TAMP_ATCR1_TAMP2AM)

+#define LL_RTC_TAMPER_ATAMP_TAMP2AM               TAMP_ATCR1_TAMP2AM /*!< tamper 2 is active */

+#endif /* TAMP_ATCR1_TAMP2AM */

+#if defined(TAMP_ATCR1_TAMP3AM)

+#define LL_RTC_TAMPER_ATAMP_TAMP3AM               TAMP_ATCR1_TAMP3AM /*!< tamper 3 is active */

+#endif /* TAMP_ATCR1_TAMP3AM */

+/**

+  * @}

+  */

+

+#if defined(TAMP_ATCR1_ATCKSEL)

+/** @defgroup RTC_LL_EC_ACTIVE_ASYNC_PRESCALER   ACTIVE TAMPER ASYNCHRONOUS PRESCALER CLOCK

+  * @{

+  */

+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK      0U                                                                      /*!< RTCCLK */

+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_2    TAMP_ATCR1_ATCKSEL_0                                                    /*!< RTCCLK/2 */

+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_4    TAMP_ATCR1_ATCKSEL_1                                                    /*!< RTCCLK/4 */

+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_8    (TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)                           /*!< RTCCLK/8 */

+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_16   TAMP_ATCR1_ATCKSEL_2                                                    /*!< RTCCLK/16 */

+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_32   (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_0)                           /*!< RTCCLK/32 */

+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_64   (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1)                           /*!< RTCCLK/64 */

+#define LL_RTC_TAMPER_ATAMP_ASYNCPRES_RTCCLK_128  (TAMP_ATCR1_ATCKSEL_2 | TAMP_ATCR1_ATCKSEL_1 | TAMP_ATCR1_ATCKSEL_0)    /*!< RTCCLK/128 */

+/**

+  * @}

+  */

+#endif /* TAMP_ATCR1_ATCKSEL */

+

+#if defined(TAMP_ATCR1_TAMP1AM)

+/** @defgroup RTC_LL_EC_ACTIVE_OUTPUT_SELECTION   ACTIVE TAMPER OUTPUT SELECTION

+  * @{

+  */

+#define LL_RTC_TAMPER_ATAMP1IN_ATAMP1OUT  (0UL << TAMP_ATCR2_ATOSEL1_Pos)

+#define LL_RTC_TAMPER_ATAMP1IN_ATAMP2OUT  (1UL << TAMP_ATCR2_ATOSEL1_Pos)

+#define LL_RTC_TAMPER_ATAMP1IN_ATAMP3OUT  (2UL << TAMP_ATCR2_ATOSEL1_Pos)

+#endif /* TAMP_ATCR1_TAMP1AM */

+

+#if defined(TAMP_ATCR1_TAMP2AM)

+#define LL_RTC_TAMPER_ATAMP2IN_ATAMP1OUT  (0UL << TAMP_ATCR2_ATOSEL2_Pos)

+#define LL_RTC_TAMPER_ATAMP2IN_ATAMP2OUT  (1UL << TAMP_ATCR2_ATOSEL2_Pos)

+#define LL_RTC_TAMPER_ATAMP2IN_ATAMP3OUT  (2UL << TAMP_ATCR2_ATOSEL2_Pos)

+#endif /* TAMP_ATCR1_TAMP2AM */

+

+#if defined(TAMP_ATCR1_TAMP3AM)

+#define LL_RTC_TAMPER_ATAMP3IN_ATAMP1OUT  (0UL << TAMP_ATCR2_ATOSEL3_Pos)

+#define LL_RTC_TAMPER_ATAMP3IN_ATAMP2OUT  (1UL << TAMP_ATCR2_ATOSEL3_Pos)

+#define LL_RTC_TAMPER_ATAMP3IN_ATAMP3OUT  (2UL << TAMP_ATCR2_ATOSEL3_Pos)

+#endif /* TAMP_ATCR1_TAMP3AM */

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EC_WAKEUPCLOCK_DIV  WAKEUP CLOCK DIV

+  * @{

+  */

+#define LL_RTC_WAKEUPCLOCK_DIV_16          0x00000000U                           /*!< RTC/16 clock is selected */

+#define LL_RTC_WAKEUPCLOCK_DIV_8           RTC_CR_WUCKSEL_0                      /*!< RTC/8 clock is selected */

+#define LL_RTC_WAKEUPCLOCK_DIV_4           RTC_CR_WUCKSEL_1                      /*!< RTC/4 clock is selected */

+#define LL_RTC_WAKEUPCLOCK_DIV_2           (RTC_CR_WUCKSEL_1 | RTC_CR_WUCKSEL_0) /*!< RTC/2 clock is selected */

+#define LL_RTC_WAKEUPCLOCK_CKSPRE          RTC_CR_WUCKSEL_2                      /*!< ck_spre (usually 1 Hz) clock is selected */

+#define LL_RTC_WAKEUPCLOCK_CKSPRE_WUT      (RTC_CR_WUCKSEL_2 | RTC_CR_WUCKSEL_1) /*!< ck_spre (usually 1 Hz) clock is selected and 2exp16 is added to the WUT counter value*/

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EC_BKP  BACKUP

+  * @{

+  */

+#define LL_RTC_BKP_DR0                     0x00000000U

+#define LL_RTC_BKP_DR1                     0x00000001U

+#define LL_RTC_BKP_DR2                     0x00000002U

+#define LL_RTC_BKP_DR3                     0x00000003U

+#define LL_RTC_BKP_DR4                     0x00000004U

+#define LL_RTC_BKP_DR5                     0x00000005U

+#define LL_RTC_BKP_DR6                     0x00000006U

+#define LL_RTC_BKP_DR7                     0x00000007U

+#define LL_RTC_BKP_DR8                     0x00000008U

+#define LL_RTC_BKP_DR9                     0x00000009U

+#define LL_RTC_BKP_DR10                    0x0000000AU

+#define LL_RTC_BKP_DR11                    0x0000000BU

+#define LL_RTC_BKP_DR12                    0x0000000CU

+#define LL_RTC_BKP_DR13                    0x0000000DU

+#define LL_RTC_BKP_DR14                    0x0000000EU

+#define LL_RTC_BKP_DR15                    0x0000000FU

+#define LL_RTC_BKP_DR16                    0x00000010U

+#define LL_RTC_BKP_DR17                    0x00000011U

+#define LL_RTC_BKP_DR18                    0x00000012U

+#define LL_RTC_BKP_DR19                    0x00000013U

+#define LL_RTC_BKP_DR20                    0x00000014U

+#define LL_RTC_BKP_DR21                    0x00000015U

+#define LL_RTC_BKP_DR22                    0x00000016U

+#define LL_RTC_BKP_DR23                    0x00000017U

+#define LL_RTC_BKP_DR24                    0x00000018U

+#define LL_RTC_BKP_DR25                    0x00000019U

+#define LL_RTC_BKP_DR26                    0x0000001AU

+#define LL_RTC_BKP_DR27                    0x0000001BU

+#define LL_RTC_BKP_DR28                    0x0000001CU

+#define LL_RTC_BKP_DR29                    0x0000001DU

+#define LL_RTC_BKP_DR30                    0x0000001EU

+#define LL_RTC_BKP_DR31                    0x0000001FU

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EC_CALIB_OUTPUT  Calibration output

+  * @{

+  */

+#define LL_RTC_CALIB_OUTPUT_NONE           0x00000000U                 /*!< Calibration output disabled */

+#define LL_RTC_CALIB_OUTPUT_1HZ            (RTC_CR_COE | RTC_CR_COSEL) /*!< Calibration output is 1 Hz */

+#define LL_RTC_CALIB_OUTPUT_512HZ           RTC_CR_COE                 /*!< Calibration output is 512 Hz */

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EC_CALIB_INSERTPULSE  Calibration pulse insertion

+  * @{

+  */

+#define LL_RTC_CALIB_INSERTPULSE_NONE      0x00000000U           /*!< No RTCCLK pulses are added */

+#define LL_RTC_CALIB_INSERTPULSE_SET       RTC_CALR_CALP         /*!< One RTCCLK pulse is effectively inserted every 2exp11 pulses (frequency increased by 488.5 ppm) */

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EC_CALIB_PERIOD  Calibration period

+  * @{

+  */

+#define LL_RTC_CALIB_PERIOD_32SEC          0x00000000U           /*!< Use a 32-second calibration cycle period */

+#define LL_RTC_CALIB_PERIOD_16SEC          RTC_CALR_CALW16       /*!< Use a 16-second calibration cycle period */

+#define LL_RTC_CALIB_PERIOD_8SEC           RTC_CALR_CALW8        /*!< Use a 8-second calibration cycle period */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup RTC_LL_Exported_Macros RTC Exported Macros

+  * @{

+  */

+

+/** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros

+  * @{

+  */

+

+/**

+  * @brief  Write a value in RTC register

+  * @param  __INSTANCE__ RTC Instance

+  * @param  __REG__ Register to be written

+  * @param  __VALUE__ Value to be written in the register

+  * @retval None

+  */

+#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, __VALUE__)

+

+/**

+  * @brief  Read a value in RTC register

+  * @param  __INSTANCE__ RTC Instance

+  * @param  __REG__ Register to be read

+  * @retval Register value

+  */

+#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EM_Convert Convert helper Macros

+  * @{

+  */

+

+/**

+  * @brief  Helper macro to convert a value from 2 digit decimal format to BCD format

+  * @param  __VALUE__ Byte to be converted

+  * @retval Converted byte

+  */

+#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U))

+

+/**

+  * @brief  Helper macro to convert a value from BCD format to 2 digit decimal format

+  * @param  __VALUE__ BCD value to be converted

+  * @retval Converted byte

+  */

+#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) ((uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0) >> (uint8_t)0x4) * 10U) + ((__VALUE__) & (uint8_t)0x0F)))

+

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EM_Date Date helper Macros

+  * @{

+  */

+

+/**

+  * @brief  Helper macro to retrieve weekday.

+  * @param  __RTC_DATE__ Date returned by @ref  LL_RTC_DATE_Get function.

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY

+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY

+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY

+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY

+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY

+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY

+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY

+  */

+#define __LL_RTC_GET_WEEKDAY(__RTC_DATE__) (((__RTC_DATE__) >> RTC_OFFSET_WEEKDAY) & 0x000000FFU)

+

+/**

+  * @brief  Helper macro to retrieve Year in BCD format

+  * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get

+  * @retval Year in BCD format (0x00 . . . 0x99)

+  */

+#define __LL_RTC_GET_YEAR(__RTC_DATE__) ((__RTC_DATE__) & 0x000000FFU)

+

+/**

+  * @brief  Helper macro to retrieve Month in BCD format

+  * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RTC_MONTH_JANUARY

+  *         @arg @ref LL_RTC_MONTH_FEBRUARY

+  *         @arg @ref LL_RTC_MONTH_MARCH

+  *         @arg @ref LL_RTC_MONTH_APRIL

+  *         @arg @ref LL_RTC_MONTH_MAY

+  *         @arg @ref LL_RTC_MONTH_JUNE

+  *         @arg @ref LL_RTC_MONTH_JULY

+  *         @arg @ref LL_RTC_MONTH_AUGUST

+  *         @arg @ref LL_RTC_MONTH_SEPTEMBER

+  *         @arg @ref LL_RTC_MONTH_OCTOBER

+  *         @arg @ref LL_RTC_MONTH_NOVEMBER

+  *         @arg @ref LL_RTC_MONTH_DECEMBER

+  */

+#define __LL_RTC_GET_MONTH(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_MONTH) & 0x000000FFU)

+

+/**

+  * @brief  Helper macro to retrieve Day in BCD format

+  * @param  __RTC_DATE__ Value returned by @ref  LL_RTC_DATE_Get

+  * @retval Day in BCD format (0x01 . . . 0x31)

+  */

+#define __LL_RTC_GET_DAY(__RTC_DATE__) (((__RTC_DATE__) >>RTC_OFFSET_DAY) & 0x000000FFU)

+

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EM_Time Time helper Macros

+  * @{

+  */

+

+/**

+  * @brief  Helper macro to retrieve hour in BCD format

+  * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function

+  * @retval Hours in BCD format (0x01. . .0x12 or between Min_Data=0x00 and Max_Data=0x23)

+  */

+#define __LL_RTC_GET_HOUR(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_HOUR) & 0x000000FFU)

+

+/**

+  * @brief  Helper macro to retrieve minute in BCD format

+  * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function

+  * @retval Minutes in BCD format (0x00. . .0x59)

+  */

+#define __LL_RTC_GET_MINUTE(__RTC_TIME__) (((__RTC_TIME__) >> RTC_OFFSET_MINUTE) & 0x000000FFU)

+

+/**

+  * @brief  Helper macro to retrieve second in BCD format

+  * @param  __RTC_TIME__ RTC time returned by @ref LL_RTC_TIME_Get function

+  * @retval Seconds in  format (0x00. . .0x59)

+  */

+#define __LL_RTC_GET_SECOND(__RTC_TIME__) ((__RTC_TIME__) & 0x000000FFU)

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup RTC_LL_Exported_Functions RTC Exported Functions

+  * @{

+  */

+

+/** @defgroup RTC_LL_EF_Configuration Configuration

+  * @{

+  */

+

+/**

+  * @brief  Set Hours format (24 hour/day or AM/PM hour format)

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)

+  * @rmtoll RTC_CR           FMT           LL_RTC_SetHourFormat

+  * @param  RTCx RTC Instance

+  * @param  HourFormat This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_HOURFORMAT_24HOUR

+  *         @arg @ref LL_RTC_HOURFORMAT_AMPM

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat)

+{

+  MODIFY_REG(RTCx->CR, RTC_CR_FMT, HourFormat);

+}

+

+/**

+  * @brief  Get Hours format (24 hour/day or AM/PM hour format)

+  * @rmtoll RTC_CR           FMT           LL_RTC_GetHourFormat

+  * @param  RTCx RTC Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RTC_HOURFORMAT_24HOUR

+  *         @arg @ref LL_RTC_HOURFORMAT_AMPM

+  */

+__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT));

+}

+

+/**

+  * @brief  Select the flag to be routed to RTC_ALARM output

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @rmtoll RTC_CR           OSEL          LL_RTC_SetAlarmOutEvent

+  * @param  RTCx RTC Instance

+  * @param  AlarmOutput This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_ALARMOUT_DISABLE

+  *         @arg @ref LL_RTC_ALARMOUT_ALMA

+  *         @arg @ref LL_RTC_ALARMOUT_ALMB

+  *         @arg @ref LL_RTC_ALARMOUT_WAKEUP

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOutput)

+{

+  MODIFY_REG(RTCx->CR, RTC_CR_OSEL, AlarmOutput);

+}

+

+/**

+  * @brief  Get the flag to be routed to RTC_ALARM output

+  * @rmtoll RTC_CR           OSEL          LL_RTC_GetAlarmOutEvent

+  * @param  RTCx RTC Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RTC_ALARMOUT_DISABLE

+  *         @arg @ref LL_RTC_ALARMOUT_ALMA

+  *         @arg @ref LL_RTC_ALARMOUT_ALMB

+  *         @arg @ref LL_RTC_ALARMOUT_WAKEUP

+  */

+__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL));

+}

+

+#if defined(RTC_CR_TAMPALRM_TYPE)

+/**

+  * @brief  Set RTC_ALARM output type (ALARM in push-pull or open-drain output)

+  * @rmtoll RTC_CR           TAMPALRM_TYPE          LL_RTC_SetAlarmOutputType

+  * @param  RTCx RTC Instance

+  * @param  Output This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN

+  *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output)

+{

+  MODIFY_REG(RTCx->CR, RTC_CR_TAMPALRM_TYPE, Output);

+}

+

+/**

+  * @brief  Get RTC_ALARM output type (ALARM in push-pull or open-drain output)

+  * @rmtoll RTC_CR           TAMPALRM_TYPE          LL_RTC_SetAlarmOutputType

+  * @param  RTCx RTC Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN

+  *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL

+  */

+__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_TYPE));

+}

+#endif /* RTC_CR_TAMPALRM_TYPE */

+

+#if defined(RTC_ICSR_INIT)

+/**

+  * @brief  Enable initialization mode

+  * @note   Initialization mode is used to program time and date register (RTC_TR and RTC_DR)

+  *         and prescaler register (RTC_PRER).

+  *         Counters are stopped and start counting from the new value when INIT is reset.

+  * @rmtoll RTC_ICSR          INIT          LL_RTC_EnableInitMode

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx)

+{

+  /* Set the Initialization mode */

+  WRITE_REG(RTCx->ICSR, RTC_LL_INIT_MASK);

+}

+

+/**

+  * @brief  Disable initialization mode (Free running mode)

+  * @rmtoll RTC_ICSR          INIT          LL_RTC_DisableInitMode

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx)

+{

+  /* Exit Initialization mode */

+  WRITE_REG(RTCx->ICSR, (uint32_t)~RTC_ICSR_INIT);

+}

+

+#endif /* RTC_ICSR_INIT */

+

+#if defined(RTC_OR_ALARMOUTTYPE)

+/**

+  * @brief  Set RTC_ALARM output type (ALARM in push-pull or open-drain output)

+  * @note   Used only when RTC_ALARM is mapped on PC13

+  * @rmtoll OR        ALARMOUTTYPE  LL_RTC_SetAlarmOutputType

+  * @param  RTCx RTC Instance

+  * @param  Output This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN

+  *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Output)

+{

+  MODIFY_REG(RTCx->OR, RTC_OR_ALARMOUTTYPE, Output);

+}

+

+/**

+  * @brief  Get RTC_ALARM output type (ALARM in push-pull or open-drain output)

+  * @note   used only when RTC_ALARM is mapped on PC13

+  * @rmtoll OR        ALARMOUTTYPE  LL_RTC_GetAlarmOutputType

+  * @param  RTCx RTC Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN

+  *         @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL

+  */

+__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->OR, RTC_OR_ALARMOUTTYPE));

+}

+#endif /* RTC_OR_ALARMOUTTYPE */

+

+#if defined(RTC_ISR_INIT)

+/**

+  * @brief  Enable initialization mode

+  * @note   Initialization mode is used to program time and date register (RTC_TR and RTC_DR)

+  *         and prescaler register (RTC_PRER).

+  *         Counters are stopped and start counting from the new value when INIT is reset.

+  * @rmtoll ISR          INIT          LL_RTC_EnableInitMode

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_EnableInitMode(RTC_TypeDef *RTCx)

+{

+  /* Set the Initialization mode */

+  WRITE_REG(RTCx->ISR, RTC_LL_INIT_MASK);

+}

+

+/**

+  * @brief  Disable initialization mode (Free running mode)

+  * @rmtoll ISR          INIT          LL_RTC_DisableInitMode

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_DisableInitMode(RTC_TypeDef *RTCx)

+{

+  /* Exit Initialization mode */

+  WRITE_REG(RTCx->ISR, (uint32_t)~RTC_ISR_INIT);

+}

+#endif /* RTC_ISR_INIT */

+

+/**

+  * @brief  Set Output polarity (pin is low when ALRAF/ALRBF/WUTF is asserted)

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @rmtoll RTC_CR           POL           LL_RTC_SetOutputPolarity

+  * @param  RTCx RTC Instance

+  * @param  Polarity This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH

+  *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polarity)

+{

+  MODIFY_REG(RTCx->CR, RTC_CR_POL, Polarity);

+}

+

+/**

+  * @brief  Get Output polarity

+  * @rmtoll RTC_CR           POL           LL_RTC_GetOutputPolarity

+  * @param  RTCx RTC Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH

+  *         @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW

+  */

+__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL));

+}

+

+/**

+  * @brief  Enable Bypass the shadow registers

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @rmtoll RTC_CR           BYPSHAD       LL_RTC_EnableShadowRegBypass

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_EnableShadowRegBypass(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->CR, RTC_CR_BYPSHAD);

+}

+

+/**

+  * @brief  Disable Bypass the shadow registers

+  * @rmtoll RTC_CR           BYPSHAD       LL_RTC_DisableShadowRegBypass

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx)

+{

+  CLEAR_BIT(RTCx->CR, RTC_CR_BYPSHAD);

+}

+

+/**

+  * @brief  Check if Shadow registers bypass is enabled or not.

+  * @rmtoll RTC_CR           BYPSHAD       LL_RTC_IsShadowRegBypassEnabled

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable RTC_REFIN reference clock detection (50 or 60 Hz)

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)

+  * @rmtoll RTC_CR           REFCKON       LL_RTC_EnableRefClock

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_EnableRefClock(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->CR, RTC_CR_REFCKON);

+}

+

+/**

+  * @brief  Disable RTC_REFIN reference clock detection (50 or 60 Hz)

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)

+  * @rmtoll RTC_CR           REFCKON       LL_RTC_DisableRefClock

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_DisableRefClock(RTC_TypeDef *RTCx)

+{

+  CLEAR_BIT(RTCx->CR, RTC_CR_REFCKON);

+}

+

+/**

+  * @brief  Set Asynchronous prescaler factor

+  * @rmtoll RTC_PRER         PREDIV_A      LL_RTC_SetAsynchPrescaler

+  * @param  RTCx RTC Instance

+  * @param  AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7F

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler)

+{

+  MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_A, AsynchPrescaler << RTC_PRER_PREDIV_A_Pos);

+}

+

+/**

+  * @brief  Set Synchronous prescaler factor

+  * @rmtoll RTC_PRER         PREDIV_S      LL_RTC_SetSynchPrescaler

+  * @param  RTCx RTC Instance

+  * @param  SynchPrescaler Value between Min_Data = 0 and Max_Data = 0x7FFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchPrescaler)

+{

+  MODIFY_REG(RTCx->PRER, RTC_PRER_PREDIV_S, SynchPrescaler);

+}

+

+/**

+  * @brief  Get Asynchronous prescaler factor

+  * @rmtoll RTC_PRER         PREDIV_A      LL_RTC_GetAsynchPrescaler

+  * @param  RTCx RTC Instance

+  * @retval Value between Min_Data = 0 and Max_Data = 0x7F

+  */

+__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos);

+}

+

+/**

+  * @brief  Get Synchronous prescaler factor

+  * @rmtoll RTC_PRER         PREDIV_S      LL_RTC_GetSynchPrescaler

+  * @param  RTCx RTC Instance

+  * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF

+  */

+__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S));

+}

+

+/**

+  * @brief  Enable the write protection for RTC registers.

+  * @rmtoll RTC_WPR          KEY           LL_RTC_EnableWriteProtection

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx)

+{

+  WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_DISABLE);

+}

+

+/**

+  * @brief  Disable the write protection for RTC registers.

+  * @rmtoll RTC_WPR          KEY           LL_RTC_DisableWriteProtection

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx)

+{

+  WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_1);

+  WRITE_REG(RTCx->WPR, RTC_WRITE_PROTECTION_ENABLE_2);

+}

+

+#if defined(RTC_CR_TAMPOE)

+/**

+  * @brief  Enable tamper output.

+  * @note When the tamper output is enabled, all external and internal tamper flags

+  *       are ORed and routed to the TAMPALRM output.

+  * @rmtoll RTC_CR           TAMPOE       LL_RTC_EnableTamperOutput

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_EnableTamperOutput(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->CR, RTC_CR_TAMPOE);

+}

+

+/**

+  * @brief  Disable tamper output.

+  * @rmtoll RTC_CR           TAMPOE       LL_RTC_DisableTamperOutput

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_DisableTamperOutput(RTC_TypeDef *RTCx)

+{

+  CLEAR_BIT(RTCx->CR, RTC_CR_TAMPOE);

+}

+

+/**

+  * @brief  Check if tamper output is enabled or not.

+  * @rmtoll RTC_CR           TAMPOE       LL_RTC_IsTamperOutputEnabled

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->CR, RTC_CR_TAMPOE) == (RTC_CR_TAMPOE)) ? 1UL : 0UL);

+}

+#endif /* RTC_CR_TAMPOE */

+

+#if defined(RTC_CR_TAMPALRM_PU)

+/**

+  * @brief  Enable internal pull-up in output mode.

+  * @rmtoll RTC_CR           TAMPALRM_PU       LL_RTC_EnableAlarmPullUp

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_EnableAlarmPullUp(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU);

+}

+

+/**

+  * @brief  Disable internal pull-up in output mode.

+  * @rmtoll RTC_CR           TAMPALRM_PU       LL_RTC_EnableAlarmPullUp

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_DisableAlarmPullUp(RTC_TypeDef *RTCx)

+{

+  CLEAR_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU);

+}

+

+/**

+  * @brief  Check if internal pull-up in output mode is enabled or not.

+  * @rmtoll RTC_CR           TAMPALRM_PU       LL_RTC_IsAlarmPullUpEnabled

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU) == (RTC_CR_TAMPALRM_PU)) ? 1UL : 0UL);

+}

+#endif /* RTC_CR_TAMPALRM_PU */

+

+#if defined(RTC_CR_OUT2EN)

+/**

+  * @brief  Enable RTC_OUT2 output

+  * @note RTC_OUT2 mapping depends on both OSEL (@ref LL_RTC_SetAlarmOutEvent)

+  *       and COE (@ref LL_RTC_CAL_SetOutputFreq) settings.

+  * @note RTC_OUT2 isn't available ins VBAT mode.

+  * @rmtoll RTC_CR           OUT2EN       LL_RTC_EnableOutput2

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_EnableOutput2(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->CR, RTC_CR_OUT2EN);

+}

+

+/**

+  * @brief  Disable RTC_OUT2 output

+  * @rmtoll RTC_CR           OUT2EN       LL_RTC_DisableOutput2

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_DisableOutput2(RTC_TypeDef *RTCx)

+{

+  CLEAR_BIT(RTCx->CR, RTC_CR_OUT2EN);

+}

+

+/**

+  * @brief  Check if RTC_OUT2 output is enabled or not.

+  * @rmtoll RTC_CR           OUT2EN       LL_RTC_IsOutput2Enabled

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->CR, RTC_CR_OUT2EN) == (RTC_CR_OUT2EN)) ? 1UL : 0UL);

+}

+

+#endif /* RTC_CR_OUT2EN */

+

+#if defined(RTC_OR_OUT_RMP)

+/**

+  * @brief  Enable RTC_OUT remap

+  * @rmtoll OR           OUT_RMP       LL_RTC_EnableOutRemap

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_EnableOutRemap(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->OR, RTC_OR_OUT_RMP);

+}

+

+/**

+  * @brief  Disable RTC_OUT remap

+  * @rmtoll OR           OUT_RMP       LL_RTC_DisableOutRemap

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_DisableOutRemap(RTC_TypeDef *RTCx)

+{

+  CLEAR_BIT(RTCx->OR, RTC_OR_OUT_RMP);

+}

+#endif /* RTC_OR_OUT_RMP */

+

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EF_Time Time

+  * @{

+  */

+

+/**

+  * @brief  Set time format (AM/24-hour or PM notation)

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)

+  * @rmtoll RTC_TR           PM            LL_RTC_TIME_SetFormat

+  * @param  RTCx RTC Instance

+  * @param  TimeFormat This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24

+  *         @arg @ref LL_RTC_TIME_FORMAT_PM

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)

+{

+  MODIFY_REG(RTCx->TR, RTC_TR_PM, TimeFormat);

+}

+

+/**

+  * @brief  Get time format (AM or PM notation)

+  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set

+  *       before reading this bit

+  * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar

+  *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).

+  * @rmtoll RTC_TR           PM            LL_RTC_TIME_GetFormat

+  * @param  RTCx RTC Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24

+  *         @arg @ref LL_RTC_TIME_FORMAT_PM

+  */

+__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM));

+}

+

+/**

+  * @brief  Set Hours in BCD format

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)

+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert hour from binary to BCD format

+  * @rmtoll RTC_TR           HT            LL_RTC_TIME_SetHour

+  *         RTC_TR           HU            LL_RTC_TIME_SetHour

+  * @param  RTCx RTC Instance

+  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)

+{

+  MODIFY_REG(RTCx->TR, (RTC_TR_HT | RTC_TR_HU),

+             (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos)));

+}

+

+/**

+  * @brief  Get Hours in BCD format

+  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set

+  *       before reading this bit

+  * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar

+  *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).

+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert hour from BCD to

+  *       Binary format

+  * @rmtoll RTC_TR           HT            LL_RTC_TIME_GetHour

+  *         RTC_TR           HU            LL_RTC_TIME_GetHour

+  * @param  RTCx RTC Instance

+  * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

+  */

+__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos);

+}

+

+/**

+  * @brief  Set Minutes in BCD format

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)

+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format

+  * @rmtoll RTC_TR           MNT           LL_RTC_TIME_SetMinute

+  *         RTC_TR           MNU           LL_RTC_TIME_SetMinute

+  * @param  RTCx RTC Instance

+  * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)

+{

+  MODIFY_REG(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU),

+             (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)));

+}

+

+/**

+  * @brief  Get Minutes in BCD format

+  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set

+  *       before reading this bit

+  * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar

+  *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).

+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert minute from BCD

+  *       to Binary format

+  * @rmtoll RTC_TR           MNT           LL_RTC_TIME_GetMinute

+  *         RTC_TR           MNU           LL_RTC_TIME_GetMinute

+  * @param  RTCx RTC Instance

+  * @retval Value between Min_Data=0x00 and Max_Data=0x59

+  */

+__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos);

+}

+

+/**

+  * @brief  Set Seconds in BCD format

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)

+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format

+  * @rmtoll RTC_TR           ST            LL_RTC_TIME_SetSecond

+  *         RTC_TR           SU            LL_RTC_TIME_SetSecond

+  * @param  RTCx RTC Instance

+  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)

+{

+  MODIFY_REG(RTCx->TR, (RTC_TR_ST | RTC_TR_SU),

+             (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos)));

+}

+

+/**

+  * @brief  Get Seconds in BCD format

+  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set

+  *       before reading this bit

+  * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar

+  *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).

+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD

+  *       to Binary format

+  * @rmtoll RTC_TR           ST            LL_RTC_TIME_GetSecond

+  *         RTC_TR           SU            LL_RTC_TIME_GetSecond

+  * @param  RTCx RTC Instance

+  * @retval Value between Min_Data=0x00 and Max_Data=0x59

+  */

+__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos);

+}

+

+/**

+  * @brief  Set time (hour, minute and second) in BCD format

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @note   It can be written in initialization mode only (@ref LL_RTC_EnableInitMode function)

+  * @note TimeFormat and Hours should follow the same format

+  * @rmtoll RTC_TR           PM            LL_RTC_TIME_Config

+  *         RTC_TR           HT            LL_RTC_TIME_Config

+  *         RTC_TR           HU            LL_RTC_TIME_Config

+  *         RTC_TR           MNT           LL_RTC_TIME_Config

+  *         RTC_TR           MNU           LL_RTC_TIME_Config

+  *         RTC_TR           ST            LL_RTC_TIME_Config

+  *         RTC_TR           SU            LL_RTC_TIME_Config

+  * @param  RTCx RTC Instance

+  * @param  Format12_24 This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24

+  *         @arg @ref LL_RTC_TIME_FORMAT_PM

+  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

+  * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59

+  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)

+{

+  register uint32_t temp;

+

+  temp = Format12_24                                                                                    | \

+         (((Hours & 0xF0U) << (RTC_TR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_TR_HU_Pos))     | \

+         (((Minutes & 0xF0U) << (RTC_TR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_TR_MNU_Pos)) | \

+         (((Seconds & 0xF0U) << (RTC_TR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_TR_SU_Pos));

+  MODIFY_REG(RTCx->TR, (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU), temp);

+}

+

+/**

+  * @brief  Get time (hour, minute and second) in BCD format

+  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set

+  *       before reading this bit

+  * @note Read either RTC_SSR or RTC_TR locks the values in the higher-order calendar

+  *       shadow registers until RTC_DR is read (LL_RTC_ReadReg(RTC, DR)).

+  * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND

+  *       are available to get independently each parameter.

+  * @rmtoll RTC_TR           HT            LL_RTC_TIME_Get

+  *         RTC_TR           HU            LL_RTC_TIME_Get

+  *         RTC_TR           MNT           LL_RTC_TIME_Get

+  *         RTC_TR           MNU           LL_RTC_TIME_Get

+  *         RTC_TR           ST            LL_RTC_TIME_Get

+  *         RTC_TR           SU            LL_RTC_TIME_Get

+  * @param  RTCx RTC Instance

+  * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS).

+  */

+__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx)

+{

+  register uint32_t temp;

+

+  temp = READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU | RTC_TR_MNT | RTC_TR_MNU | RTC_TR_ST | RTC_TR_SU));

+  return (uint32_t)((((((temp & RTC_TR_HT) >> RTC_TR_HT_Pos) << 4U) | ((temp & RTC_TR_HU) >> RTC_TR_HU_Pos)) << RTC_OFFSET_HOUR)       |  \

+                    (((((temp & RTC_TR_MNT) >> RTC_TR_MNT_Pos) << 4U) | ((temp & RTC_TR_MNU) >> RTC_TR_MNU_Pos)) << RTC_OFFSET_MINUTE) | \

+                    ((((temp & RTC_TR_ST) >> RTC_TR_ST_Pos) << 4U) | ((temp & RTC_TR_SU) >> RTC_TR_SU_Pos)));

+}

+

+/**

+  * @brief  Memorize whether the daylight saving time change has been performed

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @rmtoll RTC_CR           BKP           LL_RTC_TIME_EnableDayLightStore

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TIME_EnableDayLightStore(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->CR, RTC_CR_BKP);

+}

+

+/**

+  * @brief  Disable memorization whether the daylight saving time change has been performed.

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @rmtoll RTC_CR           BKP           LL_RTC_TIME_DisableDayLightStore

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx)

+{

+  CLEAR_BIT(RTCx->CR, RTC_CR_BKP);

+}

+

+/**

+  * @brief  Check if RTC Day Light Saving stored operation has been enabled or not

+  * @rmtoll RTC_CR           BKP           LL_RTC_TIME_IsDayLightStoreEnabled

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Subtract 1 hour (winter time change)

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @rmtoll RTC_CR           SUB1H         LL_RTC_TIME_DecHour

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TIME_DecHour(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->CR, RTC_CR_SUB1H);

+}

+

+/**

+  * @brief  Add 1 hour (summer time change)

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @rmtoll RTC_CR           ADD1H         LL_RTC_TIME_IncHour

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->CR, RTC_CR_ADD1H);

+}

+

+/**

+  * @brief  Get Sub second value in the synchronous prescaler counter.

+  * @note  You can use both SubSeconds value and SecondFraction (PREDIV_S through

+  *        LL_RTC_GetSynchPrescaler function) terms returned to convert Calendar

+  *        SubSeconds value in second fraction ratio with time unit following

+  *        generic formula:

+  *          ==> Seconds fraction ratio * time_unit= [(SecondFraction-SubSeconds)/(SecondFraction+1)] * time_unit

+  *        This conversion can be performed only if no shift operation is pending

+  *        (ie. SHFP=0) when PREDIV_S >= SS.

+  * @rmtoll RTC_SSR          SS            LL_RTC_TIME_GetSubSecond

+  * @param  RTCx RTC Instance

+  * @retval Sub second value (number between 0 and 65535)

+  */

+__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS));

+}

+

+/**

+  * @brief  Synchronize to a remote clock with a high degree of precision.

+  * @note   This operation effectively subtracts from (delays) or advance the clock of a fraction of a second.

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @note   When REFCKON is set, firmware must not write to Shift control register.

+  * @rmtoll RTC_SHIFTR       ADD1S         LL_RTC_TIME_Synchronize

+  *         RTC_SHIFTR       SUBFS         LL_RTC_TIME_Synchronize

+  * @param  RTCx RTC Instance

+  * @param  ShiftSecond This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_SHIFT_SECOND_DELAY

+  *         @arg @ref LL_RTC_SHIFT_SECOND_ADVANCE

+  * @param  Fraction Number of Seconds Fractions (any value from 0 to 0x7FFF)

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TIME_Synchronize(RTC_TypeDef *RTCx, uint32_t ShiftSecond, uint32_t Fraction)

+{

+  WRITE_REG(RTCx->SHIFTR, ShiftSecond | Fraction);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EF_Date Date

+  * @{

+  */

+

+/**

+  * @brief  Set Year in BCD format

+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Year from binary to BCD format

+  * @rmtoll RTC_DR           YT            LL_RTC_DATE_SetYear

+  *         RTC_DR           YU            LL_RTC_DATE_SetYear

+  * @param  RTCx RTC Instance

+  * @param  Year Value between Min_Data=0x00 and Max_Data=0x99

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year)

+{

+  MODIFY_REG(RTCx->DR, (RTC_DR_YT | RTC_DR_YU),

+             (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos)));

+}

+

+/**

+  * @brief  Get Year in BCD format

+  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set

+  *       before reading this bit

+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Year from BCD to Binary format

+  * @rmtoll RTC_DR           YT            LL_RTC_DATE_GetYear

+  *         RTC_DR           YU            LL_RTC_DATE_GetYear

+  * @param  RTCx RTC Instance

+  * @retval Value between Min_Data=0x00 and Max_Data=0x99

+  */

+__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos);

+}

+

+/**

+  * @brief  Set Week day

+  * @rmtoll RTC_DR           WDU           LL_RTC_DATE_SetWeekDay

+  * @param  RTCx RTC Instance

+  * @param  WeekDay This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY

+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY

+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY

+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY

+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY

+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY

+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)

+{

+  MODIFY_REG(RTCx->DR, RTC_DR_WDU, WeekDay << RTC_DR_WDU_Pos);

+}

+

+/**

+  * @brief  Get Week day

+  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set

+  *       before reading this bit

+  * @rmtoll RTC_DR           WDU           LL_RTC_DATE_GetWeekDay

+  * @param  RTCx RTC Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY

+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY

+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY

+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY

+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY

+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY

+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY

+  */

+__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos);

+}

+

+/**

+  * @brief  Set Month in BCD format

+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Month from binary to BCD format

+  * @rmtoll RTC_DR           MT            LL_RTC_DATE_SetMonth

+  *         RTC_DR           MU            LL_RTC_DATE_SetMonth

+  * @param  RTCx RTC Instance

+  * @param  Month This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_MONTH_JANUARY

+  *         @arg @ref LL_RTC_MONTH_FEBRUARY

+  *         @arg @ref LL_RTC_MONTH_MARCH

+  *         @arg @ref LL_RTC_MONTH_APRIL

+  *         @arg @ref LL_RTC_MONTH_MAY

+  *         @arg @ref LL_RTC_MONTH_JUNE

+  *         @arg @ref LL_RTC_MONTH_JULY

+  *         @arg @ref LL_RTC_MONTH_AUGUST

+  *         @arg @ref LL_RTC_MONTH_SEPTEMBER

+  *         @arg @ref LL_RTC_MONTH_OCTOBER

+  *         @arg @ref LL_RTC_MONTH_NOVEMBER

+  *         @arg @ref LL_RTC_MONTH_DECEMBER

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month)

+{

+  MODIFY_REG(RTCx->DR, (RTC_DR_MT | RTC_DR_MU),

+             (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)));

+}

+

+/**

+  * @brief  Get Month in BCD format

+  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set

+  *       before reading this bit

+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format

+  * @rmtoll RTC_DR           MT            LL_RTC_DATE_GetMonth

+  *         RTC_DR           MU            LL_RTC_DATE_GetMonth

+  * @param  RTCx RTC Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RTC_MONTH_JANUARY

+  *         @arg @ref LL_RTC_MONTH_FEBRUARY

+  *         @arg @ref LL_RTC_MONTH_MARCH

+  *         @arg @ref LL_RTC_MONTH_APRIL

+  *         @arg @ref LL_RTC_MONTH_MAY

+  *         @arg @ref LL_RTC_MONTH_JUNE

+  *         @arg @ref LL_RTC_MONTH_JULY

+  *         @arg @ref LL_RTC_MONTH_AUGUST

+  *         @arg @ref LL_RTC_MONTH_SEPTEMBER

+  *         @arg @ref LL_RTC_MONTH_OCTOBER

+  *         @arg @ref LL_RTC_MONTH_NOVEMBER

+  *         @arg @ref LL_RTC_MONTH_DECEMBER

+  */

+__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU))) >> RTC_DR_MU_Pos);

+}

+

+/**

+  * @brief  Set Day in BCD format

+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format

+  * @rmtoll RTC_DR           DT            LL_RTC_DATE_SetDay

+  *         RTC_DR           DU            LL_RTC_DATE_SetDay

+  * @param  RTCx RTC Instance

+  * @param  Day Value between Min_Data=0x01 and Max_Data=0x31

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day)

+{

+  MODIFY_REG(RTCx->DR, (RTC_DR_DT | RTC_DR_DU),

+             (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos)));

+}

+

+/**

+  * @brief  Get Day in BCD format

+  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set

+  *       before reading this bit

+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format

+  * @rmtoll RTC_DR           DT            LL_RTC_DATE_GetDay

+  *         RTC_DR           DU            LL_RTC_DATE_GetDay

+  * @param  RTCx RTC Instance

+  * @retval Value between Min_Data=0x01 and Max_Data=0x31

+  */

+__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos);

+}

+

+/**

+  * @brief  Set date (WeekDay, Day, Month and Year) in BCD format

+  * @rmtoll RTC_DR           WDU           LL_RTC_DATE_Config

+  *         RTC_DR           MT            LL_RTC_DATE_Config

+  *         RTC_DR           MU            LL_RTC_DATE_Config

+  *         RTC_DR           DT            LL_RTC_DATE_Config

+  *         RTC_DR           DU            LL_RTC_DATE_Config

+  *         RTC_DR           YT            LL_RTC_DATE_Config

+  *         RTC_DR           YU            LL_RTC_DATE_Config

+  * @param  RTCx RTC Instance

+  * @param  WeekDay This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY

+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY

+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY

+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY

+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY

+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY

+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY

+  * @param  Day Value between Min_Data=0x01 and Max_Data=0x31

+  * @param  Month This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_MONTH_JANUARY

+  *         @arg @ref LL_RTC_MONTH_FEBRUARY

+  *         @arg @ref LL_RTC_MONTH_MARCH

+  *         @arg @ref LL_RTC_MONTH_APRIL

+  *         @arg @ref LL_RTC_MONTH_MAY

+  *         @arg @ref LL_RTC_MONTH_JUNE

+  *         @arg @ref LL_RTC_MONTH_JULY

+  *         @arg @ref LL_RTC_MONTH_AUGUST

+  *         @arg @ref LL_RTC_MONTH_SEPTEMBER

+  *         @arg @ref LL_RTC_MONTH_OCTOBER

+  *         @arg @ref LL_RTC_MONTH_NOVEMBER

+  *         @arg @ref LL_RTC_MONTH_DECEMBER

+  * @param  Year Value between Min_Data=0x00 and Max_Data=0x99

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year)

+{

+  register uint32_t temp;

+

+  temp = (WeekDay << RTC_DR_WDU_Pos)                                                        | \

+         (((Year & 0xF0U) << (RTC_DR_YT_Pos - 4U)) | ((Year & 0x0FU) << RTC_DR_YU_Pos))   | \

+         (((Month & 0xF0U) << (RTC_DR_MT_Pos - 4U)) | ((Month & 0x0FU) << RTC_DR_MU_Pos)) | \

+         (((Day & 0xF0U) << (RTC_DR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_DR_DU_Pos));

+

+  MODIFY_REG(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU), temp);

+}

+

+/**

+  * @brief  Get date (WeekDay, Day, Month and Year) in BCD format

+  * @note if shadow mode is disabled (BYPSHAD=0), need to check if RSF flag is set

+  *       before reading this bit

+  * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_YEAR, __LL_RTC_GET_MONTH,

+  * and __LL_RTC_GET_DAY are available to get independently each parameter.

+  * @rmtoll RTC_DR           WDU           LL_RTC_DATE_Get

+  *         RTC_DR           MT            LL_RTC_DATE_Get

+  *         RTC_DR           MU            LL_RTC_DATE_Get

+  *         RTC_DR           DT            LL_RTC_DATE_Get

+  *         RTC_DR           DU            LL_RTC_DATE_Get

+  *         RTC_DR           YT            LL_RTC_DATE_Get

+  *         RTC_DR           YU            LL_RTC_DATE_Get

+  * @param  RTCx RTC Instance

+  * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY).

+  */

+__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx)

+{

+  register uint32_t temp;

+

+  temp = READ_BIT(RTCx->DR, (RTC_DR_WDU | RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | RTC_DR_DU | RTC_DR_YT | RTC_DR_YU));

+  return (uint32_t)((((temp & RTC_DR_WDU) >> RTC_DR_WDU_Pos) << RTC_OFFSET_WEEKDAY) | \

+                    (((((temp & RTC_DR_DT) >> RTC_DR_DT_Pos) << 4U) | ((temp & RTC_DR_DU) >> RTC_DR_DU_Pos)) << RTC_OFFSET_DAY)   | \

+                    (((((temp & RTC_DR_MT) >> RTC_DR_MT_Pos) << 4U) | ((temp & RTC_DR_MU) >> RTC_DR_MU_Pos)) << RTC_OFFSET_MONTH) | \

+                    ((((temp & RTC_DR_YT) >> RTC_DR_YT_Pos) << 4U) | ((temp & RTC_DR_YU) >> RTC_DR_YU_Pos)));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EF_ALARMA ALARMA

+  * @{

+  */

+

+/**

+  * @brief  Enable Alarm A

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @rmtoll RTC_CR           ALRAE         LL_RTC_ALMA_Enable

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ALMA_Enable(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->CR, RTC_CR_ALRAE);

+}

+

+/**

+  * @brief  Disable Alarm A

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @rmtoll RTC_CR           ALRAE         LL_RTC_ALMA_Disable

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ALMA_Disable(RTC_TypeDef *RTCx)

+{

+  CLEAR_BIT(RTCx->CR, RTC_CR_ALRAE);

+}

+

+/**

+  * @brief  Specify the Alarm A masks.

+  * @rmtoll RTC_ALRMAR       MSK4          LL_RTC_ALMA_SetMask

+  *         RTC_ALRMAR       MSK3          LL_RTC_ALMA_SetMask

+  *         RTC_ALRMAR       MSK2          LL_RTC_ALMA_SetMask

+  *         RTC_ALRMAR       MSK1          LL_RTC_ALMA_SetMask

+  * @param  RTCx RTC Instance

+  * @param  Mask This parameter can be a combination of the following values:

+  *         @arg @ref LL_RTC_ALMA_MASK_NONE

+  *         @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY

+  *         @arg @ref LL_RTC_ALMA_MASK_HOURS

+  *         @arg @ref LL_RTC_ALMA_MASK_MINUTES

+  *         @arg @ref LL_RTC_ALMA_MASK_SECONDS

+  *         @arg @ref LL_RTC_ALMA_MASK_ALL

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)

+{

+  MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1, Mask);

+}

+

+/**

+  * @brief  Get the Alarm A masks.

+  * @rmtoll RTC_ALRMAR       MSK4          LL_RTC_ALMA_GetMask

+  *         RTC_ALRMAR       MSK3          LL_RTC_ALMA_GetMask

+  *         RTC_ALRMAR       MSK2          LL_RTC_ALMA_GetMask

+  *         RTC_ALRMAR       MSK1          LL_RTC_ALMA_GetMask

+  * @param  RTCx RTC Instance

+  * @retval Returned value can be can be a combination of the following values:

+  *         @arg @ref LL_RTC_ALMA_MASK_NONE

+  *         @arg @ref LL_RTC_ALMA_MASK_DATEWEEKDAY

+  *         @arg @ref LL_RTC_ALMA_MASK_HOURS

+  *         @arg @ref LL_RTC_ALMA_MASK_MINUTES

+  *         @arg @ref LL_RTC_ALMA_MASK_SECONDS

+  *         @arg @ref LL_RTC_ALMA_MASK_ALL

+  */

+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1));

+}

+

+/**

+  * @brief  Enable AlarmA Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)

+  * @rmtoll RTC_ALRMAR       WDSEL         LL_RTC_ALMA_EnableWeekday

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ALMA_EnableWeekday(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);

+}

+

+/**

+  * @brief  Disable AlarmA Week day selection (DU[3:0] represents the date )

+  * @rmtoll RTC_ALRMAR       WDSEL         LL_RTC_ALMA_DisableWeekday

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ALMA_DisableWeekday(RTC_TypeDef *RTCx)

+{

+  CLEAR_BIT(RTCx->ALRMAR, RTC_ALRMAR_WDSEL);

+}

+

+/**

+  * @brief  Set ALARM A Day in BCD format

+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format

+  * @rmtoll RTC_ALRMAR       DT            LL_RTC_ALMA_SetDay

+  *         RTC_ALRMAR       DU            LL_RTC_ALMA_SetDay

+  * @param  RTCx RTC Instance

+  * @param  Day Value between Min_Data=0x01 and Max_Data=0x31

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day)

+{

+  MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU),

+             (((Day & 0xF0U) << (RTC_ALRMAR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMAR_DU_Pos)));

+}

+

+/**

+  * @brief  Get ALARM A Day in BCD format

+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format

+  * @rmtoll RTC_ALRMAR       DT            LL_RTC_ALMA_GetDay

+  *         RTC_ALRMAR       DU            LL_RTC_ALMA_GetDay

+  * @param  RTCx RTC Instance

+  * @retval Value between Min_Data=0x01 and Max_Data=0x31

+  */

+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos);

+}

+

+/**

+  * @brief  Set ALARM A Weekday

+  * @rmtoll RTC_ALRMAR       DU            LL_RTC_ALMA_SetWeekDay

+  * @param  RTCx RTC Instance

+  * @param  WeekDay This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY

+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY

+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY

+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY

+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY

+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY

+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)

+{

+  MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_DU, WeekDay << RTC_ALRMAR_DU_Pos);

+}

+

+/**

+  * @brief  Get ALARM A Weekday

+  * @rmtoll RTC_ALRMAR       DU            LL_RTC_ALMA_GetWeekDay

+  * @param  RTCx RTC Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY

+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY

+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY

+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY

+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY

+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY

+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY

+  */

+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos);

+}

+

+/**

+  * @brief  Set Alarm A time format (AM/24-hour or PM notation)

+  * @rmtoll RTC_ALRMAR       PM            LL_RTC_ALMA_SetTimeFormat

+  * @param  RTCx RTC Instance

+  * @param  TimeFormat This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM

+  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)

+{

+  MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM, TimeFormat);

+}

+

+/**

+  * @brief  Get Alarm A time format (AM or PM notation)

+  * @rmtoll RTC_ALRMAR       PM            LL_RTC_ALMA_GetTimeFormat

+  * @param  RTCx RTC Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM

+  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM

+  */

+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM));

+}

+

+/**

+  * @brief  Set ALARM A Hours in BCD format

+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format

+  * @rmtoll RTC_ALRMAR       HT            LL_RTC_ALMA_SetHour

+  *         RTC_ALRMAR       HU            LL_RTC_ALMA_SetHour

+  * @param  RTCx RTC Instance

+  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)

+{

+  MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU),

+             (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos)));

+}

+

+/**

+  * @brief  Get ALARM A Hours in BCD format

+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format

+  * @rmtoll RTC_ALRMAR       HT            LL_RTC_ALMA_GetHour

+  *         RTC_ALRMAR       HU            LL_RTC_ALMA_GetHour

+  * @param  RTCx RTC Instance

+  * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

+  */

+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos);

+}

+

+/**

+  * @brief  Set ALARM A Minutes in BCD format

+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format

+  * @rmtoll RTC_ALRMAR       MNT           LL_RTC_ALMA_SetMinute

+  *         RTC_ALRMAR       MNU           LL_RTC_ALMA_SetMinute

+  * @param  RTCx RTC Instance

+  * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)

+{

+  MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU),

+             (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)));

+}

+

+/**

+  * @brief  Get ALARM A Minutes in BCD format

+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format

+  * @rmtoll RTC_ALRMAR       MNT           LL_RTC_ALMA_GetMinute

+  *         RTC_ALRMAR       MNU           LL_RTC_ALMA_GetMinute

+  * @param  RTCx RTC Instance

+  * @retval Value between Min_Data=0x00 and Max_Data=0x59

+  */

+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos);

+}

+

+/**

+  * @brief  Set ALARM A Seconds in BCD format

+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format

+  * @rmtoll RTC_ALRMAR       ST            LL_RTC_ALMA_SetSecond

+  *         RTC_ALRMAR       SU            LL_RTC_ALMA_SetSecond

+  * @param  RTCx RTC Instance

+  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)

+{

+  MODIFY_REG(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU),

+             (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)));

+}

+

+/**

+  * @brief  Get ALARM A Seconds in BCD format

+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format

+  * @rmtoll RTC_ALRMAR       ST            LL_RTC_ALMA_GetSecond

+  *         RTC_ALRMAR       SU            LL_RTC_ALMA_GetSecond

+  * @param  RTCx RTC Instance

+  * @retval Value between Min_Data=0x00 and Max_Data=0x59

+  */

+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos);

+}

+

+/**

+  * @brief  Set Alarm A Time (hour, minute and second) in BCD format

+  * @rmtoll RTC_ALRMAR       PM            LL_RTC_ALMA_ConfigTime

+  *         RTC_ALRMAR       HT            LL_RTC_ALMA_ConfigTime

+  *         RTC_ALRMAR       HU            LL_RTC_ALMA_ConfigTime

+  *         RTC_ALRMAR       MNT           LL_RTC_ALMA_ConfigTime

+  *         RTC_ALRMAR       MNU           LL_RTC_ALMA_ConfigTime

+  *         RTC_ALRMAR       ST            LL_RTC_ALMA_ConfigTime

+  *         RTC_ALRMAR       SU            LL_RTC_ALMA_ConfigTime

+  * @param  RTCx RTC Instance

+  * @param  Format12_24 This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM

+  *         @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM

+  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

+  * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59

+  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)

+{

+  register uint32_t temp;

+

+  temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMAR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMAR_HU_Pos))    | \

+         (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \

+         (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos));

+

+  MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp);

+}

+

+/**

+  * @brief  Get Alarm B Time (hour, minute and second) in BCD format

+  * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND

+  * are available to get independently each parameter.

+  * @rmtoll RTC_ALRMAR       HT            LL_RTC_ALMA_GetTime

+  *         RTC_ALRMAR       HU            LL_RTC_ALMA_GetTime

+  *         RTC_ALRMAR       MNT           LL_RTC_ALMA_GetTime

+  *         RTC_ALRMAR       MNU           LL_RTC_ALMA_GetTime

+  *         RTC_ALRMAR       ST            LL_RTC_ALMA_GetTime

+  *         RTC_ALRMAR       SU            LL_RTC_ALMA_GetTime

+  * @param  RTCx RTC Instance

+  * @retval Combination of hours, minutes and seconds.

+  */

+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx));

+}

+

+/**

+  * @brief  Set Alarm A Mask the most-significant bits starting at this bit

+  * @note This register can be written only when ALRAE is reset in RTC_CR register,

+  *       or in initialization mode.

+  * @rmtoll RTC_ALRMASSR     MASKSS        LL_RTC_ALMA_SetSubSecondMask

+  * @param  RTCx RTC Instance

+  * @param  Mask Value between Min_Data=0x00 and Max_Data=0xF

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)

+{

+  MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS, Mask << RTC_ALRMASSR_MASKSS_Pos);

+}

+

+/**

+  * @brief  Get Alarm A Mask the most-significant bits starting at this bit

+  * @rmtoll RTC_ALRMASSR     MASKSS        LL_RTC_ALMA_GetSubSecondMask

+  * @param  RTCx RTC Instance

+  * @retval Value between Min_Data=0x00 and Max_Data=0xF

+  */

+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos);

+}

+

+/**

+  * @brief  Set Alarm A Sub seconds value

+  * @rmtoll RCT_ALRMASSR     SS            LL_RTC_ALMA_SetSubSecond

+  * @param  RTCx RTC Instance

+  * @param  Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)

+{

+  MODIFY_REG(RTCx->ALRMASSR, RTC_ALRMASSR_SS, Subsecond);

+}

+

+/**

+  * @brief  Get Alarm A Sub seconds value

+  * @rmtoll RCT_ALRMASSR     SS            LL_RTC_ALMA_GetSubSecond

+  * @param  RTCx RTC Instance

+  * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF

+  */

+__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EF_ALARMB ALARMB

+  * @{

+  */

+

+/**

+  * @brief  Enable Alarm B

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @rmtoll RTC_CR           ALRBE         LL_RTC_ALMB_Enable

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ALMB_Enable(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->CR, RTC_CR_ALRBE);

+}

+

+/**

+  * @brief  Disable Alarm B

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @rmtoll RTC_CR           ALRBE         LL_RTC_ALMB_Disable

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ALMB_Disable(RTC_TypeDef *RTCx)

+{

+  CLEAR_BIT(RTCx->CR, RTC_CR_ALRBE);

+}

+

+/**

+  * @brief  Specify the Alarm B masks.

+  * @rmtoll RTC_ALRMBR       MSK4          LL_RTC_ALMB_SetMask

+  *         RTC_ALRMBR       MSK3          LL_RTC_ALMB_SetMask

+  *         RTC_ALRMBR       MSK2          LL_RTC_ALMB_SetMask

+  *         RTC_ALRMBR       MSK1          LL_RTC_ALMB_SetMask

+  * @param  RTCx RTC Instance

+  * @param  Mask This parameter can be a combination of the following values:

+  *         @arg @ref LL_RTC_ALMB_MASK_NONE

+  *         @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY

+  *         @arg @ref LL_RTC_ALMB_MASK_HOURS

+  *         @arg @ref LL_RTC_ALMB_MASK_MINUTES

+  *         @arg @ref LL_RTC_ALMB_MASK_SECONDS

+  *         @arg @ref LL_RTC_ALMB_MASK_ALL

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask)

+{

+  MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1, Mask);

+}

+

+/**

+  * @brief  Get the Alarm B masks.

+  * @rmtoll RTC_ALRMBR       MSK4          LL_RTC_ALMB_GetMask

+  *         RTC_ALRMBR       MSK3          LL_RTC_ALMB_GetMask

+  *         RTC_ALRMBR       MSK2          LL_RTC_ALMB_GetMask

+  *         RTC_ALRMBR       MSK1          LL_RTC_ALMB_GetMask

+  * @param  RTCx RTC Instance

+  * @retval Returned value can be can be a combination of the following values:

+  *         @arg @ref LL_RTC_ALMB_MASK_NONE

+  *         @arg @ref LL_RTC_ALMB_MASK_DATEWEEKDAY

+  *         @arg @ref LL_RTC_ALMB_MASK_HOURS

+  *         @arg @ref LL_RTC_ALMB_MASK_MINUTES

+  *         @arg @ref LL_RTC_ALMB_MASK_SECONDS

+  *         @arg @ref LL_RTC_ALMB_MASK_ALL

+  */

+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1));

+}

+

+/**

+  * @brief  Enable AlarmB Week day selection (DU[3:0] represents the week day. DT[1:0] is do not care)

+  * @rmtoll RTC_ALRMBR       WDSEL         LL_RTC_ALMB_EnableWeekday

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ALMB_EnableWeekday(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);

+}

+

+/**

+  * @brief  Disable AlarmB Week day selection (DU[3:0] represents the date )

+  * @rmtoll RTC_ALRMBR       WDSEL         LL_RTC_ALMB_DisableWeekday

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ALMB_DisableWeekday(RTC_TypeDef *RTCx)

+{

+  CLEAR_BIT(RTCx->ALRMBR, RTC_ALRMBR_WDSEL);

+}

+

+/**

+  * @brief  Set ALARM B Day in BCD format

+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Day from binary to BCD format

+  * @rmtoll RTC_ALRMBR       DT            LL_RTC_ALMB_SetDay

+  *         RTC_ALRMBR       DU            LL_RTC_ALMB_SetDay

+  * @param  RTCx RTC Instance

+  * @param  Day Value between Min_Data=0x01 and Max_Data=0x31

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day)

+{

+  MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU),

+             (((Day & 0xF0U) << (RTC_ALRMBR_DT_Pos - 4U)) | ((Day & 0x0FU) << RTC_ALRMBR_DU_Pos)));

+}

+

+/**

+  * @brief  Get ALARM B Day in BCD format

+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format

+  * @rmtoll RTC_ALRMBR       DT            LL_RTC_ALMB_GetDay

+  *         RTC_ALRMBR       DU            LL_RTC_ALMB_GetDay

+  * @param  RTCx RTC Instance

+  * @retval Value between Min_Data=0x01 and Max_Data=0x31

+  */

+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos);

+}

+

+/**

+  * @brief  Set ALARM B Weekday

+  * @rmtoll RTC_ALRMBR       DU            LL_RTC_ALMB_SetWeekDay

+  * @param  RTCx RTC Instance

+  * @param  WeekDay This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY

+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY

+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY

+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY

+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY

+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY

+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay)

+{

+  MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_DU, WeekDay << RTC_ALRMBR_DU_Pos);

+}

+

+/**

+  * @brief  Get ALARM B Weekday

+  * @rmtoll RTC_ALRMBR       DU            LL_RTC_ALMB_GetWeekDay

+  * @param  RTCx RTC Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY

+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY

+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY

+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY

+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY

+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY

+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY

+  */

+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos);

+}

+

+/**

+  * @brief  Set ALARM B time format (AM/24-hour or PM notation)

+  * @rmtoll RTC_ALRMBR       PM            LL_RTC_ALMB_SetTimeFormat

+  * @param  RTCx RTC Instance

+  * @param  TimeFormat This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM

+  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeFormat)

+{

+  MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM, TimeFormat);

+}

+

+/**

+  * @brief  Get ALARM B time format (AM or PM notation)

+  * @rmtoll RTC_ALRMBR       PM            LL_RTC_ALMB_GetTimeFormat

+  * @param  RTCx RTC Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM

+  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM

+  */

+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM));

+}

+

+/**

+  * @brief  Set ALARM B Hours in BCD format

+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Hours from binary to BCD format

+  * @rmtoll RTC_ALRMBR       HT            LL_RTC_ALMB_SetHour

+  *         RTC_ALRMBR       HU            LL_RTC_ALMB_SetHour

+  * @param  RTCx RTC Instance

+  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours)

+{

+  MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU),

+             (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos)));

+}

+

+/**

+  * @brief  Get ALARM B Hours in BCD format

+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format

+  * @rmtoll RTC_ALRMBR       HT            LL_RTC_ALMB_GetHour

+  *         RTC_ALRMBR       HU            LL_RTC_ALMB_GetHour

+  * @param  RTCx RTC Instance

+  * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

+  */

+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos);

+}

+

+/**

+  * @brief  Set ALARM B Minutes in BCD format

+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Minutes from binary to BCD format

+  * @rmtoll RTC_ALRMBR       MNT           LL_RTC_ALMB_SetMinute

+  *         RTC_ALRMBR       MNU           LL_RTC_ALMB_SetMinute

+  * @param  RTCx RTC Instance

+  * @param  Minutes between Min_Data=0x00 and Max_Data=0x59

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes)

+{

+  MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU),

+             (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)));

+}

+

+/**

+  * @brief  Get ALARM B Minutes in BCD format

+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format

+  * @rmtoll RTC_ALRMBR       MNT           LL_RTC_ALMB_GetMinute

+  *         RTC_ALRMBR       MNU           LL_RTC_ALMB_GetMinute

+  * @param  RTCx RTC Instance

+  * @retval Value between Min_Data=0x00 and Max_Data=0x59

+  */

+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos);

+}

+

+/**

+  * @brief  Set ALARM B Seconds in BCD format

+  * @note helper macro __LL_RTC_CONVERT_BIN2BCD is available to convert Seconds from binary to BCD format

+  * @rmtoll RTC_ALRMBR       ST            LL_RTC_ALMB_SetSecond

+  *         RTC_ALRMBR       SU            LL_RTC_ALMB_SetSecond

+  * @param  RTCx RTC Instance

+  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds)

+{

+  MODIFY_REG(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU),

+             (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)));

+}

+

+/**

+  * @brief  Get ALARM B Seconds in BCD format

+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format

+  * @rmtoll RTC_ALRMBR       ST            LL_RTC_ALMB_GetSecond

+  *         RTC_ALRMBR       SU            LL_RTC_ALMB_GetSecond

+  * @param  RTCx RTC Instance

+  * @retval Value between Min_Data=0x00 and Max_Data=0x59

+  */

+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos);

+}

+

+/**

+  * @brief  Set Alarm B Time (hour, minute and second) in BCD format

+  * @rmtoll RTC_ALRMBR       PM            LL_RTC_ALMB_ConfigTime

+  *         RTC_ALRMBR       HT            LL_RTC_ALMB_ConfigTime

+  *         RTC_ALRMBR       HU            LL_RTC_ALMB_ConfigTime

+  *         RTC_ALRMBR       MNT           LL_RTC_ALMB_ConfigTime

+  *         RTC_ALRMBR       MNU           LL_RTC_ALMB_ConfigTime

+  *         RTC_ALRMBR       ST            LL_RTC_ALMB_ConfigTime

+  *         RTC_ALRMBR       SU            LL_RTC_ALMB_ConfigTime

+  * @param  RTCx RTC Instance

+  * @param  Format12_24 This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM

+  *         @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM

+  * @param  Hours Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

+  * @param  Minutes Value between Min_Data=0x00 and Max_Data=0x59

+  * @param  Seconds Value between Min_Data=0x00 and Max_Data=0x59

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds)

+{

+  register uint32_t temp;

+

+  temp = Format12_24 | (((Hours & 0xF0U) << (RTC_ALRMBR_HT_Pos - 4U)) | ((Hours & 0x0FU) << RTC_ALRMBR_HU_Pos))    | \

+         (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \

+         (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos));

+

+  MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM | RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp);

+}

+

+/**

+  * @brief  Get Alarm B Time (hour, minute and second) in BCD format

+  * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND

+  * are available to get independently each parameter.

+  * @rmtoll RTC_ALRMBR       HT            LL_RTC_ALMB_GetTime

+  *         RTC_ALRMBR       HU            LL_RTC_ALMB_GetTime

+  *         RTC_ALRMBR       MNT           LL_RTC_ALMB_GetTime

+  *         RTC_ALRMBR       MNU           LL_RTC_ALMB_GetTime

+  *         RTC_ALRMBR       ST            LL_RTC_ALMB_GetTime

+  *         RTC_ALRMBR       SU            LL_RTC_ALMB_GetTime

+  * @param  RTCx RTC Instance

+  * @retval Combination of hours, minutes and seconds.

+  */

+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTime(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)((LL_RTC_ALMB_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMB_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMB_GetSecond(RTCx));

+}

+

+/**

+  * @brief  Set Alarm B Mask the most-significant bits starting at this bit

+  * @note This register can be written only when ALRBE is reset in RTC_CR register,

+  *       or in initialization mode.

+  * @rmtoll RTC_ALRMBSSR     MASKSS        LL_RTC_ALMB_SetSubSecondMask

+  * @param  RTCx RTC Instance

+  * @param  Mask Value between Min_Data=0x00 and Max_Data=0xF

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Mask)

+{

+  MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS, Mask << RTC_ALRMBSSR_MASKSS_Pos);

+}

+

+/**

+  * @brief  Get Alarm B Mask the most-significant bits starting at this bit

+  * @rmtoll RTC_ALRMBSSR     MASKSS        LL_RTC_ALMB_GetSubSecondMask

+  * @param  RTCx RTC Instance

+  * @retval Value between Min_Data=0x00 and Max_Data=0xF

+  */

+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS)  >> RTC_ALRMBSSR_MASKSS_Pos);

+}

+

+/**

+  * @brief  Set Alarm B Sub seconds value

+  * @rmtoll RTC_ALRMBSSR     SS            LL_RTC_ALMB_SetSubSecond

+  * @param  RTCx RTC Instance

+  * @param  Subsecond Value between Min_Data=0x00 and Max_Data=0x7FFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsecond)

+{

+  MODIFY_REG(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS, Subsecond);

+}

+

+/**

+  * @brief  Get Alarm B Sub seconds value

+  * @rmtoll RTC_ALRMBSSR     SS            LL_RTC_ALMB_GetSubSecond

+  * @param  RTCx RTC Instance

+  * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF

+  */

+__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EF_Timestamp Timestamp

+  * @{

+  */

+

+/**

+  * @brief  Enable internal event timestamp

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @rmtoll RTC_CR           ITSE          LL_RTC_TS_EnableInternalEvent

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TS_EnableInternalEvent(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->CR, RTC_CR_ITSE);

+}

+

+/**

+  * @brief  Disable internal event timestamp

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @rmtoll RTC_CR           ITSE          LL_RTC_TS_DisableInternalEvent

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TS_DisableInternalEvent(RTC_TypeDef *RTCx)

+{

+  CLEAR_BIT(RTCx->CR, RTC_CR_ITSE);

+}

+

+/**

+  * @brief  Enable Timestamp

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @rmtoll RTC_CR           TSE           LL_RTC_TS_Enable

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TS_Enable(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->CR, RTC_CR_TSE);

+}

+

+/**

+  * @brief  Disable Timestamp

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @rmtoll RTC_CR           TSE           LL_RTC_TS_Disable

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TS_Disable(RTC_TypeDef *RTCx)

+{

+  CLEAR_BIT(RTCx->CR, RTC_CR_TSE);

+}

+

+/**

+  * @brief  Set Time-stamp event active edge

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @note TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting

+  * @rmtoll RTC_CR           TSEDGE        LL_RTC_TS_SetActiveEdge

+  * @param  RTCx RTC Instance

+  * @param  Edge This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING

+  *         @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge)

+{

+  MODIFY_REG(RTCx->CR, RTC_CR_TSEDGE, Edge);

+}

+

+/**

+  * @brief  Get Time-stamp event active edge

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @rmtoll RTC_CR           TSEDGE        LL_RTC_TS_GetActiveEdge

+  * @param  RTCx RTC Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING

+  *         @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING

+  */

+__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE));

+}

+

+/**

+  * @brief  Get Timestamp AM/PM notation (AM or 24-hour format)

+  * @rmtoll RTC_TSTR         PM            LL_RTC_TS_GetTimeFormat

+  * @param  RTCx RTC Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RTC_TS_TIME_FORMAT_AM

+  *         @arg @ref LL_RTC_TS_TIME_FORMAT_PM

+  */

+__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM));

+}

+

+/**

+  * @brief  Get Timestamp Hours in BCD format

+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Hours from BCD to Binary format

+  * @rmtoll RTC_TSTR         HT            LL_RTC_TS_GetHour

+  *         RTC_TSTR         HU            LL_RTC_TS_GetHour

+  * @param  RTCx RTC Instance

+  * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23

+  */

+__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos);

+}

+

+/**

+  * @brief  Get Timestamp Minutes in BCD format

+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Minutes from BCD to Binary format

+  * @rmtoll RTC_TSTR         MNT           LL_RTC_TS_GetMinute

+  *         RTC_TSTR         MNU           LL_RTC_TS_GetMinute

+  * @param  RTCx RTC Instance

+  * @retval Value between Min_Data=0x00 and Max_Data=0x59

+  */

+__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos);

+}

+

+/**

+  * @brief  Get Timestamp Seconds in BCD format

+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Seconds from BCD to Binary format

+  * @rmtoll RTC_TSTR         ST            LL_RTC_TS_GetSecond

+  *         RTC_TSTR         SU            LL_RTC_TS_GetSecond

+  * @param  RTCx RTC Instance

+  * @retval Value between Min_Data=0x00 and Max_Data=0x59

+  */

+__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU));

+}

+

+/**

+  * @brief  Get Timestamp time (hour, minute and second) in BCD format

+  * @note helper macros __LL_RTC_GET_HOUR, __LL_RTC_GET_MINUTE and __LL_RTC_GET_SECOND

+  * are available to get independently each parameter.

+  * @rmtoll RTC_TSTR         HT            LL_RTC_TS_GetTime

+  *         RTC_TSTR         HU            LL_RTC_TS_GetTime

+  *         RTC_TSTR         MNT           LL_RTC_TS_GetTime

+  *         RTC_TSTR         MNU           LL_RTC_TS_GetTime

+  *         RTC_TSTR         ST            LL_RTC_TS_GetTime

+  *         RTC_TSTR         SU            LL_RTC_TS_GetTime

+  * @param  RTCx RTC Instance

+  * @retval Combination of hours, minutes and seconds.

+  */

+__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->TSTR,

+                             RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU));

+}

+

+/**

+  * @brief  Get Timestamp Week day

+  * @rmtoll RTC_TSDR         WDU           LL_RTC_TS_GetWeekDay

+  * @param  RTCx RTC Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RTC_WEEKDAY_MONDAY

+  *         @arg @ref LL_RTC_WEEKDAY_TUESDAY

+  *         @arg @ref LL_RTC_WEEKDAY_WEDNESDAY

+  *         @arg @ref LL_RTC_WEEKDAY_THURSDAY

+  *         @arg @ref LL_RTC_WEEKDAY_FRIDAY

+  *         @arg @ref LL_RTC_WEEKDAY_SATURDAY

+  *         @arg @ref LL_RTC_WEEKDAY_SUNDAY

+  */

+__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos);

+}

+

+/**

+  * @brief  Get Timestamp Month in BCD format

+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Month from BCD to Binary format

+  * @rmtoll RTC_TSDR         MT            LL_RTC_TS_GetMonth

+  *         RTC_TSDR         MU            LL_RTC_TS_GetMonth

+  * @param  RTCx RTC Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RTC_MONTH_JANUARY

+  *         @arg @ref LL_RTC_MONTH_FEBRUARY

+  *         @arg @ref LL_RTC_MONTH_MARCH

+  *         @arg @ref LL_RTC_MONTH_APRIL

+  *         @arg @ref LL_RTC_MONTH_MAY

+  *         @arg @ref LL_RTC_MONTH_JUNE

+  *         @arg @ref LL_RTC_MONTH_JULY

+  *         @arg @ref LL_RTC_MONTH_AUGUST

+  *         @arg @ref LL_RTC_MONTH_SEPTEMBER

+  *         @arg @ref LL_RTC_MONTH_OCTOBER

+  *         @arg @ref LL_RTC_MONTH_NOVEMBER

+  *         @arg @ref LL_RTC_MONTH_DECEMBER

+  */

+__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos);

+}

+

+/**

+  * @brief  Get Timestamp Day in BCD format

+  * @note helper macro __LL_RTC_CONVERT_BCD2BIN is available to convert Day from BCD to Binary format

+  * @rmtoll RTC_TSDR         DT            LL_RTC_TS_GetDay

+  *         RTC_TSDR         DU            LL_RTC_TS_GetDay

+  * @param  RTCx RTC Instance

+  * @retval Value between Min_Data=0x01 and Max_Data=0x31

+  */

+__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU));

+}

+

+/**

+  * @brief  Get Timestamp date (WeekDay, Day and Month) in BCD format

+  * @note helper macros __LL_RTC_GET_WEEKDAY, __LL_RTC_GET_MONTH,

+  * and __LL_RTC_GET_DAY are available to get independently each parameter.

+  * @rmtoll RTC_TSDR         WDU           LL_RTC_TS_GetDate

+  *         RTC_TSDR         MT            LL_RTC_TS_GetDate

+  *         RTC_TSDR         MU            LL_RTC_TS_GetDate

+  *         RTC_TSDR         DT            LL_RTC_TS_GetDate

+  *         RTC_TSDR         DU            LL_RTC_TS_GetDate

+  * @param  RTCx RTC Instance

+  * @retval Combination of Weekday, Day and Month

+  */

+__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU));

+}

+

+/**

+  * @brief  Get time-stamp sub second value

+  * @rmtoll RTC_TSSSR         SS            LL_RTC_TS_GetSubSecond

+  * @param  RTCx RTC Instance

+  * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF

+  */

+__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EF_Tamper_Timestamp Time-stamp on Tamper

+  * @{

+  */

+

+#if defined(RTC_TAMPCR_TAMPTS)

+/**

+  * @brief  Activate timestamp on tamper detection event

+  * @rmtoll RTC_CR       TAMPTS        LL_RTC_TS_EnableOnTamper

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPTS);

+}

+

+/**

+  * @brief  Disable timestamp on tamper detection event

+  * @rmtoll RTC_CR       TAMPTS        LL_RTC_TS_DisableOnTamper

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx)

+{

+  CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPTS);

+}

+#endif /* RTC_TAMPCR_TAMPTS */

+

+#if defined(RTC_CR_TAMPTS)

+/**

+  * @brief  Activate timestamp on tamper detection event

+  * @rmtoll RTC_CR       TAMPTS        LL_RTC_TS_EnableOnTamper

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+

+__STATIC_INLINE void LL_RTC_TS_EnableOnTamper(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->CR, RTC_CR_TAMPTS);

+}

+

+/**

+  * @brief  Disable timestamp on tamper detection event

+  * @rmtoll RTC_CR       TAMPTS        LL_RTC_TS_DisableOnTamper

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx)

+{

+  CLEAR_BIT(RTCx->CR, RTC_CR_TAMPTS);

+}

+#endif /* RTC_CR_TAMPTS */

+

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EF_Tamper Tamper

+  * @{

+  */

+

+#if defined(RTC_TAMPCR_TAMP1E)

+/**

+  * @brief  Enable RTC_TAMPx input detection

+  * @rmtoll TAMPCR       TAMP1E        LL_RTC_TAMPER_Enable

+  *         TAMPCR       TAMP2E        LL_RTC_TAMPER_Enable

+  *         TAMPCR       TAMP3E        LL_RTC_TAMPER_Enable

+  * @param  RTCx RTC Instance

+  * @param  Tamper This parameter can be a combination of the following values:

+  *         @arg @ref LL_RTC_TAMPER_1

+  *         @arg @ref LL_RTC_TAMPER_2

+  *         @arg @ref LL_RTC_TAMPER_3

+  *

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper)

+{

+  SET_BIT(RTCx->TAMPCR, Tamper);

+}

+

+/**

+  * @brief  Clear RTC_TAMPx input detection

+  * @rmtoll TAMPCR       TAMP1E        LL_RTC_TAMPER_Disable

+  *         TAMPCR       TAMP2E        LL_RTC_TAMPER_Disable

+  *         TAMPCR       TAMP3E        LL_RTC_TAMPER_Disable

+  * @param  RTCx RTC Instance

+  * @param  Tamper This parameter can be a combination of the following values:

+  *         @arg @ref LL_RTC_TAMPER_1

+  *         @arg @ref LL_RTC_TAMPER_2

+  *         @arg @ref LL_RTC_TAMPER_3

+  *

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper)

+{

+  CLEAR_BIT(RTCx->TAMPCR, Tamper);

+}

+

+/**

+  * @brief  Enable Tamper mask flag

+  * @note Associated Tamper IT must not enabled when tamper mask is set.

+  * @rmtoll TAMPCR       TAMP1MF       LL_RTC_TAMPER_EnableMask

+  *         TAMPCR       TAMP2MF       LL_RTC_TAMPER_EnableMask

+  *         TAMPCR       TAMP3MF       LL_RTC_TAMPER_EnableMask

+  * @param  RTCx RTC Instance

+  * @param  Mask This parameter can be a combination of the following values:

+  *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER1

+  *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER2

+  *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER3

+  *

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef *RTCx, uint32_t Mask)

+{

+  SET_BIT(RTCx->TAMPCR, Mask);

+}

+

+/**

+  * @brief  Disable Tamper mask flag

+  * @rmtoll TAMPCR       TAMP1MF       LL_RTC_TAMPER_DisableMask

+  *         TAMPCR       TAMP2MF       LL_RTC_TAMPER_DisableMask

+  *         TAMPCR       TAMP3MF       LL_RTC_TAMPER_DisableMask

+  * @param  RTCx RTC Instance

+  * @param  Mask This parameter can be a combination of the following values:

+  *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER1

+  *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER2

+  *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER3

+  *

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef *RTCx, uint32_t Mask)

+{

+  CLEAR_BIT(RTCx->TAMPCR, Mask);

+}

+

+/**

+  * @brief  Enable backup register erase after Tamper event detection

+  * @rmtoll TAMPCR       TAMP1NOERASE  LL_RTC_TAMPER_EnableEraseBKP

+  *         TAMPCR       TAMP2NOERASE  LL_RTC_TAMPER_EnableEraseBKP

+  *         TAMPCR       TAMP3NOERASE  LL_RTC_TAMPER_EnableEraseBKP

+  * @param  RTCx RTC Instance

+  * @param  Tamper This parameter can be a combination of the following values:

+  *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1

+  *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2

+  *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3

+  *

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper)

+{

+  CLEAR_BIT(RTCx->TAMPCR, Tamper);

+}

+

+/**

+  * @brief  Disable backup register erase after Tamper event detection

+  * @rmtoll TAMPCR       TAMP1NOERASE  LL_RTC_TAMPER_DisableEraseBKP

+  *         TAMPCR       TAMP2NOERASE  LL_RTC_TAMPER_DisableEraseBKP

+  *         TAMPCR       TAMP3NOERASE  LL_RTC_TAMPER_DisableEraseBKP

+  * @param  RTCx RTC Instance

+  * @param  Tamper This parameter can be a combination of the following values:

+  *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1

+  *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2

+  *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3

+  *

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper)

+{

+  SET_BIT(RTCx->TAMPCR, Tamper);

+}

+#endif /* RTC_TAMPCR_TAMP1E */

+

+#if defined(RTC_TAMPCR_TAMPPUDIS)

+/**

+  * @brief  Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)

+  * @rmtoll TAMPCR       TAMPPUDIS     LL_RTC_TAMPER_DisablePullUp

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPUDIS);

+}

+

+/**

+  * @brief  Enable RTC_TAMPx pull-up disable ( Precharge RTC_TAMPx pins before sampling)

+  * @rmtoll TAMPCR       TAMPPUDIS     LL_RTC_TAMPER_EnablePullUp

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx)

+{

+  CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPUDIS);

+}

+#endif /* RTC_TAMPCR_TAMPPUDIS */

+

+#if defined(RTC_TAMPCR_TAMPPRCH)

+/**

+  * @brief  Set RTC_TAMPx precharge duration

+  * @rmtoll TAMPCR       TAMPPRCH      LL_RTC_TAMPER_SetPrecharge

+  * @param  RTCx RTC Instance

+  * @param  Duration This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK

+  *         @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK

+  *         @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK

+  *         @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Duration)

+{

+  MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPPRCH, Duration);

+}

+

+/**

+  * @brief  Get RTC_TAMPx precharge duration

+  * @rmtoll TAMPCR       TAMPPRCH      LL_RTC_TAMPER_GetPrecharge

+  * @param  RTCx RTC Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK

+  *         @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK

+  *         @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK

+  *         @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK

+  */

+__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPPRCH));

+}

+#endif /* RTC_TAMPCR_TAMPPRCH */

+

+#if defined(RTC_TAMPCR_TAMPFLT)

+/**

+  * @brief  Set RTC_TAMPx filter count

+  * @rmtoll TAMPCR       TAMPFLT       LL_RTC_TAMPER_SetFilterCount

+  * @param  RTCx RTC Instance

+  * @param  FilterCount This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_TAMPER_FILTER_DISABLE

+  *         @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE

+  *         @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE

+  *         @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t FilterCount)

+{

+  MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPFLT, FilterCount);

+}

+

+/**

+  * @brief  Get RTC_TAMPx filter count

+  * @rmtoll TAMPCR       TAMPFLT       LL_RTC_TAMPER_GetFilterCount

+  * @param  RTCx RTC Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RTC_TAMPER_FILTER_DISABLE

+  *         @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE

+  *         @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE

+  *         @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE

+  */

+__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFLT));

+}

+#endif /* RTC_TAMPCR_TAMPFLT */

+

+#if defined(RTC_TAMPCR_TAMPFREQ)

+/**

+  * @brief  Set Tamper sampling frequency

+  * @rmtoll TAMPCR       TAMPFREQ      LL_RTC_TAMPER_SetSamplingFreq

+  * @param  RTCx RTC Instance

+  * @param  SamplingFreq This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t SamplingFreq)

+{

+  MODIFY_REG(RTCx->TAMPCR, RTC_TAMPCR_TAMPFREQ, SamplingFreq);

+}

+

+/**

+  * @brief  Get Tamper sampling frequency

+  * @rmtoll TAMPCR       TAMPFREQ      LL_RTC_TAMPER_GetSamplingFreq

+  * @param  RTCx RTC Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256

+  */

+__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPFREQ));

+}

+#endif /* RTC_TAMPCR_TAMPFREQ */

+

+#if defined(RTC_TAMPCR_TAMP1E)

+/**

+  * @brief  Enable Active level for Tamper input

+  * @rmtoll TAMPCR       TAMP1TRG      LL_RTC_TAMPER_EnableActiveLevel

+  *         TAMPCR       TAMP2TRG      LL_RTC_TAMPER_EnableActiveLevel

+  *         TAMPCR       TAMP3TRG      LL_RTC_TAMPER_EnableActiveLevel

+  * @param  RTCx RTC Instance

+  * @param  Tamper This parameter can be a combination of the following values:

+  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1

+  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2

+  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3

+  *

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)

+{

+  SET_BIT(RTCx->TAMPCR, Tamper);

+}

+

+/**

+  * @brief  Disable Active level for Tamper input

+  * @rmtoll TAMPCR       TAMP1TRG      LL_RTC_TAMPER_DisableActiveLevel

+  *         TAMPCR       TAMP2TRG      LL_RTC_TAMPER_DisableActiveLevel

+  *         TAMPCR       TAMP3TRG      LL_RTC_TAMPER_DisableActiveLevel

+  * @param  RTCx RTC Instance

+  * @param  Tamper This parameter can be a combination of the following values:

+  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1

+  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2

+  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3

+  *

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper)

+{

+  CLEAR_BIT(RTCx->TAMPCR, Tamper);

+}

+#endif /* RTC_TAMPCR_TAMP1E */

+

+#if defined(TAMP_CR1_TAMP1E)

+/**

+  * @brief  Enable TAMPx input detection

+  * @rmtoll TAMP_CR1       TAMP1E        LL_RTC_TAMPER_Enable

+  *         TAMP_CR1       TAMP2E        LL_RTC_TAMPER_Enable

+  *         TAMP_CR1       TAMP3E        LL_RTC_TAMPER_Enable

+  * @param  TAMPx TAMP Instance

+  * @param  Tamper This parameter can be a combination of the following values:

+  *         @arg @ref LL_RTC_TAMPER_1

+  *         @arg @ref LL_RTC_TAMPER_2

+  *         @arg @ref LL_RTC_TAMPER_3

+  *

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_Enable(TAMP_TypeDef *TAMPx, uint32_t Tamper)

+{

+  SET_BIT(TAMPx->CR1, Tamper);

+}

+

+/**

+  * @brief  Clear TAMPx input detection

+  * @rmtoll TAMP_CR1       TAMP1E        LL_RTC_TAMPER_Disable

+  *         TAMP_CR1       TAMP2E        LL_RTC_TAMPER_Disable

+  *         TAMP_CR1       TAMP3E        LL_RTC_TAMPER_Disable

+  * @param  TAMPx TAMP Instance

+  * @param  Tamper This parameter can be a combination of the following values:

+  *         @arg @ref LL_RTC_TAMPER_1

+  *         @arg @ref LL_RTC_TAMPER_2

+  *         @arg @ref LL_RTC_TAMPER_3

+  *

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_Disable(TAMP_TypeDef *TAMPx, uint32_t Tamper)

+{

+  CLEAR_BIT(TAMPx->CR1, Tamper);

+}

+#endif /* TAMP_CR1_TAMP1E */

+

+#if defined(TAMP_CR2_TAMP1MSK)

+/**

+  * @brief  Enable Tamper mask flag

+  * @note Associated Tamper IT must not enabled when tamper mask is set.

+  * @rmtoll TAMP_CR2       TAMP1MF       LL_RTC_TAMPER_EnableMask

+  *         TAMP_CR2       TAMP2MF       LL_RTC_TAMPER_EnableMask

+  *         TAMP_CR2       TAMP3MF       LL_RTC_TAMPER_EnableMask

+  * @param  TAMPx TAMP Instance

+  * @param  Mask This parameter can be a combination of the following values:

+  *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER1

+  *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER2

+  *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER3

+  *

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_EnableMask(TAMP_TypeDef *TAMPx, uint32_t Mask)

+{

+  SET_BIT(TAMPx->CR2, Mask);

+}

+

+/**

+  * @brief  Disable Tamper mask flag

+  * @rmtoll TAMP_CR2       TAMP1MF       LL_RTC_TAMPER_DisableMask

+  *         TAMP_CR2       TAMP2MF       LL_RTC_TAMPER_DisableMask

+  *         TAMP_CR2       TAMP3MF       LL_RTC_TAMPER_DisableMask

+  * @param  TAMPx TAMP Instance

+  * @param  Mask This parameter can be a combination of the following values:

+  *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER1

+  *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER2

+  *         @arg @ref LL_RTC_TAMPER_MASK_TAMPER3

+  *

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_DisableMask(TAMP_TypeDef *TAMPx, uint32_t Mask)

+{

+  CLEAR_BIT(TAMPx->CR2, Mask);

+}

+

+/**

+  * @brief  Enable backup register erase after Tamper event detection

+  * @rmtoll TAMP_CR2       TAMP1NOERASE  LL_RTC_TAMPER_EnableEraseBKP

+  *         TAMP_CR2       TAMP2NOERASE  LL_RTC_TAMPER_EnableEraseBKP

+  *         TAMP_CR2       TAMP3NOERASE  LL_RTC_TAMPER_EnableEraseBKP

+  * @param  TAMPx TAMP Instance

+  * @param  Tamper This parameter can be a combination of the following values:

+  *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1

+  *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2

+  *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3

+  *

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(TAMP_TypeDef *TAMPx, uint32_t Tamper)

+{

+  CLEAR_BIT(TAMPx->CR2, Tamper);

+}

+

+/**

+  * @brief  Disable backup register erase after Tamper event detection

+  * @rmtoll TAMP_CR2       TAMP1NOERASE  LL_RTC_TAMPER_DisableEraseBKP

+  *         TAMP_CR2       TAMP2NOERASE  LL_RTC_TAMPER_DisableEraseBKP

+  *         TAMP_CR2       TAMP3NOERASE  LL_RTC_TAMPER_DisableEraseBKP

+  * @param  TAMPx TAMP Instance

+  * @param  Tamper This parameter can be a combination of the following values:

+  *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER1

+  *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER2

+  *         @arg @ref LL_RTC_TAMPER_NOERASE_TAMPER3

+  *

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(TAMP_TypeDef *TAMPx, uint32_t Tamper)

+{

+  SET_BIT(TAMPx->CR2, Tamper);

+}

+

+/**

+  * @brief  Enable Active level for Tamper input

+  * @rmtoll TAMP_CR2       TAMP1TRG      LL_RTC_TAMPER_EnableActiveLevel

+  *         TAMP_CR2       TAMP2TRG      LL_RTC_TAMPER_EnableActiveLevel

+  *         TAMP_CR2       TAMP3TRG      LL_RTC_TAMPER_EnableActiveLevel

+  * @param  TAMPx TAMP Instance

+  * @param  Tamper This parameter can be a combination of the following values:

+  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1

+  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2

+  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3

+  *

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(TAMP_TypeDef *TAMPx, uint32_t Tamper)

+{

+  SET_BIT(TAMPx->CR2, Tamper);

+}

+

+/**

+  * @brief  Disable Active level for Tamper input

+  * @rmtoll TAMP_CR2       TAMP1TRG      LL_RTC_TAMPER_DisableActiveLevel

+  *         TAMP_CR2       TAMP2TRG      LL_RTC_TAMPER_DisableActiveLevel

+  *         TAMP_CR2       TAMP3TRG      LL_RTC_TAMPER_DisableActiveLevel

+  * @param  TAMPx TAMP Instance

+  * @param  Tamper This parameter can be a combination of the following values:

+  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP1

+  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP2

+  *         @arg @ref LL_RTC_TAMPER_ACTIVELEVEL_TAMP3

+  *

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(TAMP_TypeDef *TAMPx, uint32_t Tamper)

+{

+  CLEAR_BIT(TAMPx->CR2, Tamper);

+}

+#endif /* TAMP_CR2_TAMP1MSK */

+

+#if defined(TAMP_FLTCR_TAMPPUDIS)

+/**

+  * @brief  Disable RTC_TAMPx pull-up disable (Disable precharge of RTC_TAMPx pins)

+  * @rmtoll TAMP_FLTCR       TAMPPUDIS     LL_RTC_TAMPER_DisablePullUp

+  * @param  TAMPx TAMP Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(TAMP_TypeDef *TAMPx)

+{

+  SET_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPPUDIS);

+}

+

+/**

+  * @brief  Enable RTC_TAMPx pull-up disable (Precharge RTC_TAMPx pins before sampling)

+  * @rmtoll TAMP_FLTCR       TAMPPUDIS     LL_RTC_TAMPER_EnablePullUp

+  * @param  TAMPx TAMP Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(TAMP_TypeDef *TAMPx)

+{

+  CLEAR_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPPUDIS);

+}

+

+/**

+  * @brief  Set RTC_TAMPx precharge duration

+  * @rmtoll TAMP_FLTCR       TAMPPRCH      LL_RTC_TAMPER_SetPrecharge

+  * @param  TAMPx TAMP Instance

+  * @param  Duration This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK

+  *         @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK

+  *         @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK

+  *         @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(TAMP_TypeDef *TAMPx, uint32_t Duration)

+{

+  MODIFY_REG(TAMPx->FLTCR, TAMP_FLTCR_TAMPPRCH, Duration);

+}

+

+/**

+  * @brief  Get RTC_TAMPx precharge duration

+  * @rmtoll TAMP_FLTCR       TAMPPRCH      LL_RTC_TAMPER_GetPrecharge

+  * @param  TAMPx TAMP Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RTC_TAMPER_DURATION_1RTCCLK

+  *         @arg @ref LL_RTC_TAMPER_DURATION_2RTCCLK

+  *         @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK

+  *         @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK

+  */

+__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(TAMP_TypeDef *TAMPx)

+{

+  return (uint32_t)(READ_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPPRCH));

+}

+

+/**

+  * @brief  Set RTC_TAMPx filter count

+  * @rmtoll TAMP_FLTCR       TAMPFLT       LL_RTC_TAMPER_SetFilterCount

+  * @param  TAMPx TAMP Instance

+  * @param  FilterCount This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_TAMPER_FILTER_DISABLE

+  *         @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE

+  *         @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE

+  *         @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(TAMP_TypeDef *TAMPx, uint32_t FilterCount)

+{

+  MODIFY_REG(TAMPx->FLTCR, TAMP_FLTCR_TAMPFLT, FilterCount);

+}

+

+/**

+  * @brief  Get RTC_TAMPx filter count

+  * @rmtoll TAMP_FLTCR       TAMPFLT       LL_RTC_TAMPER_GetFilterCount

+  * @param  TAMPx TAMP Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RTC_TAMPER_FILTER_DISABLE

+  *         @arg @ref LL_RTC_TAMPER_FILTER_2SAMPLE

+  *         @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE

+  *         @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE

+  */

+__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(TAMP_TypeDef *TAMPx)

+{

+  return (uint32_t)(READ_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPFLT));

+}

+

+/**

+  * @brief  Set Tamper sampling frequency

+  * @rmtoll TAMP_FLTCR       TAMPFREQ      LL_RTC_TAMPER_SetSamplingFreq

+  * @param  TAMPx TAMP Instance

+  * @param  SamplingFreq This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(TAMP_TypeDef *TAMPx, uint32_t SamplingFreq)

+{

+  MODIFY_REG(TAMPx->FLTCR, TAMP_FLTCR_TAMPFREQ, SamplingFreq);

+}

+

+/**

+  * @brief  Get Tamper sampling frequency

+  * @rmtoll TAMP_FLTCR       TAMPFREQ      LL_RTC_TAMPER_GetSamplingFreq

+  * @param  TAMPx TAMP Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_32768

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_16384

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_8192

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_4096

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_2048

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_1024

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512

+  *         @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256

+  */

+__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(TAMP_TypeDef *TAMPx)

+{

+  return (uint32_t)(READ_BIT(TAMPx->FLTCR, TAMP_FLTCR_TAMPFREQ));

+}

+#endif /* TAMP_FLTCR_TAMPPUDIS */

+

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EF_Wakeup Wakeup

+  * @{

+  */

+

+/**

+  * @brief  Enable Wakeup timer

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @rmtoll RTC_CR           WUTE          LL_RTC_WAKEUP_Enable

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_WAKEUP_Enable(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->CR, RTC_CR_WUTE);

+}

+

+/**

+  * @brief  Disable Wakeup timer

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @rmtoll RTC_CR           WUTE          LL_RTC_WAKEUP_Disable

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx)

+{

+  CLEAR_BIT(RTCx->CR, RTC_CR_WUTE);

+}

+

+/**

+  * @brief  Check if Wakeup timer is enabled or not

+  * @rmtoll RTC_CR           WUTE          LL_RTC_WAKEUP_IsEnabled

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Select Wakeup clock

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @note Bit can be written only when RTC_CR WUTE bit = 0 and RTC_ISR WUTWF bit = 1

+  * @rmtoll RTC_CR           WUCKSEL       LL_RTC_WAKEUP_SetClock

+  * @param  RTCx RTC Instance

+  * @param  WakeupClock This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16

+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8

+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4

+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2

+  *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE

+  *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupClock)

+{

+  MODIFY_REG(RTCx->CR, RTC_CR_WUCKSEL, WakeupClock);

+}

+

+/**

+  * @brief  Get Wakeup clock

+  * @rmtoll RTC_CR           WUCKSEL       LL_RTC_WAKEUP_GetClock

+  * @param  RTCx RTC Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_16

+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_8

+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_4

+  *         @arg @ref LL_RTC_WAKEUPCLOCK_DIV_2

+  *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE

+  *         @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT

+  */

+__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL));

+}

+

+/**

+  * @brief  Set Wakeup auto-reload value

+  * @note Bit can be written only when WUTWF is set to 1 in RTC_ISR

+  * @rmtoll RTC_WUTR         WUT           LL_RTC_WAKEUP_SetAutoReload

+  * @param  RTCx RTC Instance

+  * @param  Value Value between Min_Data=0x00 and Max_Data=0xFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Value)

+{

+  MODIFY_REG(RTCx->WUTR, RTC_WUTR_WUT, Value);

+}

+

+/**

+  * @brief  Get Wakeup auto-reload value

+  * @rmtoll RTC_WUTR         WUT           LL_RTC_WAKEUP_GetAutoReload

+  * @param  RTCx RTC Instance

+  * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF

+  */

+__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT));

+}

+

+/**

+  * @}

+  */

+

+

+/** @defgroup RTC_LL_EF_Backup_Registers Backup_Registers

+  * @{

+  */

+

+#if defined(RTC_BKP0R)

+/**

+  * @brief  Writes a data in a specified RTC Backup data register.

+  * @rmtoll BKPxR        BKP           LL_RTC_BAK_SetRegister

+  * @param  RTCx RTC Instance

+  * @param  BackupRegister This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_BKP_DR0

+  *         @arg @ref LL_RTC_BKP_DR1

+  *         @arg @ref LL_RTC_BKP_DR2

+  *         @arg @ref LL_RTC_BKP_DR3

+  *         @arg @ref LL_RTC_BKP_DR4

+  *         @arg @ref LL_RTC_BKP_DR5

+  *         @arg @ref LL_RTC_BKP_DR6

+  *         @arg @ref LL_RTC_BKP_DR7

+  *         @arg @ref LL_RTC_BKP_DR8

+  *         @arg @ref LL_RTC_BKP_DR9

+  *         @arg @ref LL_RTC_BKP_DR10

+  *         @arg @ref LL_RTC_BKP_DR11

+  *         @arg @ref LL_RTC_BKP_DR12

+  *         @arg @ref LL_RTC_BKP_DR13

+  *         @arg @ref LL_RTC_BKP_DR14

+  *         @arg @ref LL_RTC_BKP_DR15

+  *         @arg @ref LL_RTC_BKP_DR16

+  *         @arg @ref LL_RTC_BKP_DR17

+  *         @arg @ref LL_RTC_BKP_DR18

+  *         @arg @ref LL_RTC_BKP_DR19

+  *         @arg @ref LL_RTC_BKP_DR20

+  *         @arg @ref LL_RTC_BKP_DR21

+  *         @arg @ref LL_RTC_BKP_DR22

+  *         @arg @ref LL_RTC_BKP_DR23

+  *         @arg @ref LL_RTC_BKP_DR24

+  *         @arg @ref LL_RTC_BKP_DR25

+  *         @arg @ref LL_RTC_BKP_DR26

+  *         @arg @ref LL_RTC_BKP_DR27

+  *         @arg @ref LL_RTC_BKP_DR28

+  *         @arg @ref LL_RTC_BKP_DR29

+  *         @arg @ref LL_RTC_BKP_DR30

+  *         @arg @ref LL_RTC_BKP_DR31

+  * @param  Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_BAK_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data)

+{

+  register uint32_t tmp;

+

+  tmp = (uint32_t)(&(RTCx->BKP0R));

+  tmp += (BackupRegister * 4U);

+

+  /* Write the specified register */

+  *(__IO uint32_t *)tmp = (uint32_t)Data;

+}

+

+/**

+  * @brief  Reads data from the specified RTC Backup data Register.

+  * @rmtoll BKPxR        BKP           LL_RTC_BAK_GetRegister

+  * @param  RTCx RTC Instance

+  * @param  BackupRegister This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_BKP_DR0

+  *         @arg @ref LL_RTC_BKP_DR1

+  *         @arg @ref LL_RTC_BKP_DR2

+  *         @arg @ref LL_RTC_BKP_DR3

+  *         @arg @ref LL_RTC_BKP_DR4

+  *         @arg @ref LL_RTC_BKP_DR5

+  *         @arg @ref LL_RTC_BKP_DR6

+  *         @arg @ref LL_RTC_BKP_DR7

+  *         @arg @ref LL_RTC_BKP_DR8

+  *         @arg @ref LL_RTC_BKP_DR9

+  *         @arg @ref LL_RTC_BKP_DR10

+  *         @arg @ref LL_RTC_BKP_DR11

+  *         @arg @ref LL_RTC_BKP_DR12

+  *         @arg @ref LL_RTC_BKP_DR13

+  *         @arg @ref LL_RTC_BKP_DR14

+  *         @arg @ref LL_RTC_BKP_DR15

+  *         @arg @ref LL_RTC_BKP_DR16

+  *         @arg @ref LL_RTC_BKP_DR17

+  *         @arg @ref LL_RTC_BKP_DR18

+  *         @arg @ref LL_RTC_BKP_DR19

+  *         @arg @ref LL_RTC_BKP_DR20

+  *         @arg @ref LL_RTC_BKP_DR21

+  *         @arg @ref LL_RTC_BKP_DR22

+  *         @arg @ref LL_RTC_BKP_DR23

+  *         @arg @ref LL_RTC_BKP_DR24

+  *         @arg @ref LL_RTC_BKP_DR25

+  *         @arg @ref LL_RTC_BKP_DR26

+  *         @arg @ref LL_RTC_BKP_DR27

+  *         @arg @ref LL_RTC_BKP_DR28

+  *         @arg @ref LL_RTC_BKP_DR29

+  *         @arg @ref LL_RTC_BKP_DR30

+  *         @arg @ref LL_RTC_BKP_DR31

+  * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF

+  */

+__STATIC_INLINE uint32_t LL_RTC_BAK_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister)

+{

+  register uint32_t tmp;

+

+  tmp = (uint32_t)(&(RTCx->BKP0R));

+  tmp += (BackupRegister * 4U);

+

+  /* Read the specified register */

+  return (*(__IO uint32_t *)tmp);

+}

+#endif /* RTC_BKP0R */

+

+#if defined(TAMP_BKP0R_BKP)

+/**

+  * @brief  Writes a data in a specified Backup data register.

+  * @rmtoll TAMP_BKPxR        BKP           LL_RTC_BKP_SetRegister

+  * @param  TAMPx RTC Instance

+  * @param  BackupRegister This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_BKP_DR0

+  *         @arg @ref LL_RTC_BKP_DR1

+  *         @arg @ref LL_RTC_BKP_DR2

+  *         @arg @ref LL_RTC_BKP_DR3

+  *         @arg @ref LL_RTC_BKP_DR4

+  *         @arg @ref LL_RTC_BKP_DR5

+  *         @arg @ref LL_RTC_BKP_DR6

+  *         @arg @ref LL_RTC_BKP_DR7

+  *         @arg @ref LL_RTC_BKP_DR8

+  *         @arg @ref LL_RTC_BKP_DR9

+  *         @arg @ref LL_RTC_BKP_DR10

+  *         @arg @ref LL_RTC_BKP_DR11

+  *         @arg @ref LL_RTC_BKP_DR12

+  *         @arg @ref LL_RTC_BKP_DR13

+  *         @arg @ref LL_RTC_BKP_DR14

+  *         @arg @ref LL_RTC_BKP_DR15

+  *         @arg @ref LL_RTC_BKP_DR16

+  *         @arg @ref LL_RTC_BKP_DR17

+  *         @arg @ref LL_RTC_BKP_DR18

+  *         @arg @ref LL_RTC_BKP_DR19

+  *         @arg @ref LL_RTC_BKP_DR20

+  *         @arg @ref LL_RTC_BKP_DR21

+  *         @arg @ref LL_RTC_BKP_DR22

+  *         @arg @ref LL_RTC_BKP_DR23

+  *         @arg @ref LL_RTC_BKP_DR24

+  *         @arg @ref LL_RTC_BKP_DR25

+  *         @arg @ref LL_RTC_BKP_DR26

+  *         @arg @ref LL_RTC_BKP_DR27

+  *         @arg @ref LL_RTC_BKP_DR28

+  *         @arg @ref LL_RTC_BKP_DR29

+  *         @arg @ref LL_RTC_BKP_DR30

+  *         @arg @ref LL_RTC_BKP_DR31

+  * @param  Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_BKP_SetRegister(TAMP_TypeDef *TAMPx, uint32_t BackupRegister, uint32_t Data)

+{

+  register uint32_t tmp = 0U;

+

+  tmp = (uint32_t)(&(TAMPx->BKP0R));

+  tmp += (BackupRegister * 4U);

+

+  /* Write the specified register */

+  *(__IO uint32_t *)tmp = (uint32_t)Data;

+}

+

+/**

+  * @brief  Reads data from the specified RTC Backup data Register.

+  * @rmtoll TAMP_BKPxR        BKP           LL_RTC_BKP_GetRegister

+  * @param  TAMPx RTC Instance

+  * @param  BackupRegister This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_BKP_DR0

+  *         @arg @ref LL_RTC_BKP_DR1

+  *         @arg @ref LL_RTC_BKP_DR2

+  *         @arg @ref LL_RTC_BKP_DR3

+  *         @arg @ref LL_RTC_BKP_DR4

+  *         @arg @ref LL_RTC_BKP_DR5

+  *         @arg @ref LL_RTC_BKP_DR6

+  *         @arg @ref LL_RTC_BKP_DR7

+  *         @arg @ref LL_RTC_BKP_DR8

+  *         @arg @ref LL_RTC_BKP_DR9

+  *         @arg @ref LL_RTC_BKP_DR10

+  *         @arg @ref LL_RTC_BKP_DR11

+  *         @arg @ref LL_RTC_BKP_DR12

+  *         @arg @ref LL_RTC_BKP_DR13

+  *         @arg @ref LL_RTC_BKP_DR14

+  *         @arg @ref LL_RTC_BKP_DR15

+  *         @arg @ref LL_RTC_BKP_DR16

+  *         @arg @ref LL_RTC_BKP_DR17

+  *         @arg @ref LL_RTC_BKP_DR18

+  *         @arg @ref LL_RTC_BKP_DR19

+  *         @arg @ref LL_RTC_BKP_DR20

+  *         @arg @ref LL_RTC_BKP_DR21

+  *         @arg @ref LL_RTC_BKP_DR22

+  *         @arg @ref LL_RTC_BKP_DR23

+  *         @arg @ref LL_RTC_BKP_DR24

+  *         @arg @ref LL_RTC_BKP_DR25

+  *         @arg @ref LL_RTC_BKP_DR26

+  *         @arg @ref LL_RTC_BKP_DR27

+  *         @arg @ref LL_RTC_BKP_DR28

+  *         @arg @ref LL_RTC_BKP_DR29

+  *         @arg @ref LL_RTC_BKP_DR30

+  *         @arg @ref LL_RTC_BKP_DR31

+  * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF

+  */

+__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(TAMP_TypeDef *TAMPx, uint32_t BackupRegister)

+{

+  register uint32_t tmp = 0U;

+

+  tmp = (uint32_t)(&(TAMPx->BKP0R));

+  tmp += (BackupRegister * 4U);

+

+  /* Read the specified register */

+  return (*(__IO uint32_t *)tmp);

+}

+#endif /* TAMP_BKP0R_BKP */

+

+/**

+  * @}

+  */

+

+

+/** @defgroup RTC_LL_EF_Calibration Calibration

+  * @{

+  */

+

+/**

+  * @brief  Set Calibration output frequency (1 Hz or 512 Hz)

+  * @note Bits are write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @rmtoll RTC_CR           COE           LL_RTC_CAL_SetOutputFreq

+  *         RTC_CR           COSEL         LL_RTC_CAL_SetOutputFreq

+  * @param  RTCx RTC Instance

+  * @param  Frequency This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_CALIB_OUTPUT_NONE

+  *         @arg @ref LL_RTC_CALIB_OUTPUT_1HZ

+  *         @arg @ref LL_RTC_CALIB_OUTPUT_512HZ

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Frequency)

+{

+  MODIFY_REG(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL, Frequency);

+}

+

+/**

+  * @brief  Get Calibration output frequency (1 Hz or 512 Hz)

+  * @rmtoll RTC_CR           COE           LL_RTC_CAL_GetOutputFreq

+  *         RTC_CR           COSEL         LL_RTC_CAL_GetOutputFreq

+  * @param  RTCx RTC Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RTC_CALIB_OUTPUT_NONE

+  *         @arg @ref LL_RTC_CALIB_OUTPUT_1HZ

+  *         @arg @ref LL_RTC_CALIB_OUTPUT_512HZ

+  */

+__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL));

+}

+

+/**

+  * @brief  Insert or not One RTCCLK pulse every 2exp11 pulses (frequency increased by 488.5 ppm)

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @note   Bit can be written only when RECALPF is set to 0 in RTC_ISR

+  * @rmtoll RTC_CALR         CALP          LL_RTC_CAL_SetPulse

+  * @param  RTCx RTC Instance

+  * @param  Pulse This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_CALIB_INSERTPULSE_NONE

+  *         @arg @ref LL_RTC_CALIB_INSERTPULSE_SET

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse)

+{

+  MODIFY_REG(RTCx->CALR, RTC_CALR_CALP, Pulse);

+}

+

+/**

+  * @brief  Check if one RTCCLK has been inserted or not every 2exp11 pulses (frequency increased by 488.5 ppm)

+  * @rmtoll RTC_CALR         CALP          LL_RTC_CAL_IsPulseInserted

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set the calibration cycle period

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @note   Bit can be written only when RECALPF is set to 0 in RTC_ISR

+  * @rmtoll RTC_CALR         CALW8         LL_RTC_CAL_SetPeriod

+  *         RTC_CALR         CALW16        LL_RTC_CAL_SetPeriod

+  * @param  RTCx RTC Instance

+  * @param  Period This parameter can be one of the following values:

+  *         @arg @ref LL_RTC_CALIB_PERIOD_32SEC

+  *         @arg @ref LL_RTC_CALIB_PERIOD_16SEC

+  *         @arg @ref LL_RTC_CALIB_PERIOD_8SEC

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period)

+{

+  MODIFY_REG(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16, Period);

+}

+

+/**

+  * @brief  Get the calibration cycle period

+  * @rmtoll RTC_CALR         CALW8         LL_RTC_CAL_GetPeriod

+  *         RTC_CALR         CALW16        LL_RTC_CAL_GetPeriod

+  * @param  RTCx RTC Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_RTC_CALIB_PERIOD_32SEC

+  *         @arg @ref LL_RTC_CALIB_PERIOD_16SEC

+  *         @arg @ref LL_RTC_CALIB_PERIOD_8SEC

+  */

+__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16));

+}

+

+/**

+  * @brief  Set Calibration minus

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @note   Bit can be written only when RECALPF is set to 0 in RTC_ISR

+  * @rmtoll RTC_CALR         CALM          LL_RTC_CAL_SetMinus

+  * @param  RTCx RTC Instance

+  * @param  CalibMinus Value between Min_Data=0x00 and Max_Data=0x1FF

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus)

+{

+  MODIFY_REG(RTCx->CALR, RTC_CALR_CALM, CalibMinus);

+}

+

+/**

+  * @brief  Get Calibration minus

+  * @rmtoll RTC_CALR         CALM          LL_RTC_CAL_GetMinus

+  * @param  RTCx RTC Instance

+  * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF

+  */

+__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx)

+{

+  return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM));

+}

+

+/**

+  * @}

+  */

+

+

+/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management

+  * @{

+  */

+

+#if defined(RTC_ISR_ITSF)

+/**

+  * @brief  Get Internal Time-stamp flag

+  * @rmtoll RTC_ISR          ITSF          LL_RTC_IsActiveFlag_ITS

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->ISR, RTC_ISR_ITSF) == (RTC_ISR_ITSF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Recalibration pending Flag

+  * @rmtoll ISR          RECALPF       LL_RTC_IsActiveFlag_RECALP

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->ISR, RTC_ISR_RECALPF) == (RTC_ISR_RECALPF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get RTC_TAMP3 detection flag

+  * @rmtoll ISR          TAMP3F        LL_RTC_IsActiveFlag_TAMP3

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP3F) == (RTC_ISR_TAMP3F)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get RTC_TAMP2 detection flag

+  * @rmtoll ISR          TAMP2F        LL_RTC_IsActiveFlag_TAMP2

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP2F) == (RTC_ISR_TAMP2F)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get RTC_TAMP1 detection flag

+  * @rmtoll ISR          TAMP1F        LL_RTC_IsActiveFlag_TAMP1

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->ISR, RTC_ISR_TAMP1F) == (RTC_ISR_TAMP1F)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Time-stamp overflow flag

+  * @rmtoll ISR          TSOVF         LL_RTC_IsActiveFlag_TSOV

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->ISR, RTC_ISR_TSOVF) == (RTC_ISR_TSOVF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Time-stamp flag

+  * @rmtoll ISR          TSF           LL_RTC_IsActiveFlag_TS

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->ISR, RTC_ISR_TSF) == (RTC_ISR_TSF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Wakeup timer flag

+  * @rmtoll ISR          WUTF          LL_RTC_IsActiveFlag_WUT

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTF) == (RTC_ISR_WUTF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Alarm B flag

+  * @rmtoll ISR          ALRBF         LL_RTC_IsActiveFlag_ALRB

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBF) == (RTC_ISR_ALRBF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Alarm A flag

+  * @rmtoll ISR          ALRAF         LL_RTC_IsActiveFlag_ALRA

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAF) == (RTC_ISR_ALRAF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear Internal Time-stamp flag

+  * @rmtoll ISR          ITSF          LL_RTC_ClearFlag_ITS

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ClearFlag_ITS(RTC_TypeDef *RTCx)

+{

+  WRITE_REG(RTCx->ISR, (~((RTC_ISR_ITSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));

+}

+

+/**

+  * @brief  Clear RTC_TAMP3 detection flag

+  * @rmtoll ISR          TAMP3F        LL_RTC_ClearFlag_TAMP3

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx)

+{

+  WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP3F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));

+}

+

+/**

+  * @brief  Clear RTC_TAMP2 detection flag

+  * @rmtoll ISR          TAMP2F        LL_RTC_ClearFlag_TAMP2

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx)

+{

+  WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP2F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));

+}

+

+/**

+  * @brief  Clear RTC_TAMP1 detection flag

+  * @rmtoll ISR          TAMP1F        LL_RTC_ClearFlag_TAMP1

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef *RTCx)

+{

+  WRITE_REG(RTCx->ISR, (~((RTC_ISR_TAMP1F | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));

+}

+

+/**

+  * @brief  Clear Time-stamp overflow flag

+  * @rmtoll ISR          TSOVF         LL_RTC_ClearFlag_TSOV

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx)

+{

+  WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSOVF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));

+}

+

+/**

+  * @brief  Clear Time-stamp flag

+  * @rmtoll ISR          TSF           LL_RTC_ClearFlag_TS

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx)

+{

+  WRITE_REG(RTCx->ISR, (~((RTC_ISR_TSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));

+}

+

+/**

+  * @brief  Clear Wakeup timer flag

+  * @rmtoll ISR          WUTF          LL_RTC_ClearFlag_WUT

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx)

+{

+  WRITE_REG(RTCx->ISR, (~((RTC_ISR_WUTF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));

+}

+

+/**

+  * @brief  Clear Alarm B flag

+  * @rmtoll ISR          ALRBF         LL_RTC_ClearFlag_ALRB

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx)

+{

+  WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRBF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));

+}

+

+/**

+  * @brief  Clear Alarm A flag

+  * @rmtoll ISR          ALRAF         LL_RTC_ClearFlag_ALRA

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx)

+{

+  WRITE_REG(RTCx->ISR, (~((RTC_ISR_ALRAF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));

+}

+

+/**

+  * @brief  Get Initialization flag

+  * @rmtoll ISR          INITF         LL_RTC_IsActiveFlag_INIT

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->ISR, RTC_ISR_INITF) == (RTC_ISR_INITF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Registers synchronization flag

+  * @rmtoll ISR          RSF           LL_RTC_IsActiveFlag_RS

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->ISR, RTC_ISR_RSF) == (RTC_ISR_RSF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear Registers synchronization flag

+  * @rmtoll ISR          RSF           LL_RTC_ClearFlag_RS

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx)

+{

+  WRITE_REG(RTCx->ISR, (~((RTC_ISR_RSF | RTC_ISR_INIT) & 0x0000FFFFU) | (RTCx->ISR & RTC_ISR_INIT)));

+}

+

+/**

+  * @brief  Get Initialization status flag

+  * @rmtoll ISR          INITS         LL_RTC_IsActiveFlag_INITS

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->ISR, RTC_ISR_INITS) == (RTC_ISR_INITS)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Shift operation pending flag

+  * @rmtoll ISR          SHPF          LL_RTC_IsActiveFlag_SHP

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->ISR, RTC_ISR_SHPF) == (RTC_ISR_SHPF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Wakeup timer write flag

+  * @rmtoll ISR          WUTWF         LL_RTC_IsActiveFlag_WUTW

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->ISR, RTC_ISR_WUTWF) == (RTC_ISR_WUTWF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Alarm B write flag

+  * @rmtoll ISR          ALRBWF        LL_RTC_IsActiveFlag_ALRBW

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRBWF) == (RTC_ISR_ALRBWF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Alarm A write flag

+  * @rmtoll ISR          ALRAWF        LL_RTC_IsActiveFlag_ALRAW

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->ISR, RTC_ISR_ALRAWF) == (RTC_ISR_ALRAWF)) ? 1UL : 0UL);

+}

+#endif /* RTC_ISR_ITSF */

+

+#if defined(RTC_SR_ITSF)

+/**

+  * @brief  Get Internal Time-stamp flag

+  * @rmtoll RTC_SR          ITSF          LL_RTC_IsActiveFlag_ITS

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->SR, RTC_SR_ITSF) == (RTC_SR_ITSF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Time-stamp overflow flag

+  * @rmtoll RTC_SR          TSOVF         LL_RTC_IsActiveFlag_TSOV

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->SR, RTC_SR_TSOVF) == (RTC_SR_TSOVF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Time-stamp flag

+  * @rmtoll RTC_SR          TSF           LL_RTC_IsActiveFlag_TS

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->SR, RTC_SR_TSF) == (RTC_SR_TSF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Wakeup timer flag

+  * @rmtoll RTC_SR          WUTF          LL_RTC_IsActiveFlag_WUT

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->SR, RTC_SR_WUTF) == (RTC_SR_WUTF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Alarm B flag

+  * @rmtoll RTC_SR          ALRBF         LL_RTC_IsActiveFlag_ALRB

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->SR, RTC_SR_ALRBF) == (RTC_SR_ALRBF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Alarm A flag

+  * @rmtoll RTC_SR          ALRAF         LL_RTC_IsActiveFlag_ALRA

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->SR, RTC_SR_ALRAF) == (RTC_SR_ALRAF)) ? 1UL : 0UL);

+}

+#endif /* RTC_SR_ITSF */

+

+#if defined(RTC_SCR_CITSF)

+/**

+  * @brief  Clear Internal Time-stamp flag

+  * @rmtoll RTC_SCR          CITSF          LL_RTC_ClearFlag_ITS

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ClearFlag_ITS(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->SCR, RTC_SCR_CITSF);

+}

+

+/**

+  * @brief  Clear Time-stamp overflow flag

+  * @rmtoll RTC_SCR          CTSOVF         LL_RTC_ClearFlag_TSOV

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ClearFlag_TSOV(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->SCR, RTC_SCR_CTSOVF);

+}

+

+/**

+  * @brief  Clear Time-stamp flag

+  * @rmtoll RTC_SCR          CTSF           LL_RTC_ClearFlag_TS

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ClearFlag_TS(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->SCR, RTC_SCR_CTSF);

+}

+

+/**

+  * @brief  Clear Wakeup timer flag

+  * @rmtoll RTC_SCR          CWUTF          LL_RTC_ClearFlag_WUT

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ClearFlag_WUT(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->SCR, RTC_SCR_CWUTF);

+}

+

+/**

+  * @brief  Clear Alarm B flag

+  * @rmtoll RTC_SCR          CALRBF         LL_RTC_ClearFlag_ALRB

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ClearFlag_ALRB(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->SCR, RTC_SCR_CALRBF);

+}

+

+/**

+  * @brief  Clear Alarm A flag

+  * @rmtoll RTC_SCR          CALRAF         LL_RTC_ClearFlag_ALRA

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->SCR, RTC_SCR_CALRAF);

+}

+#endif /* RTC_SCR_CITSF */

+

+#if defined(RTC_ICSR_RECALPF)

+/**

+  * @brief  Get Recalibration pending Flag

+  * @rmtoll RTC_ICSR          RECALPF       LL_RTC_IsActiveFlag_RECALP

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RECALPF) == (RTC_ICSR_RECALPF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Initialization flag

+  * @rmtoll RTC_ICSR          INITF         LL_RTC_IsActiveFlag_INIT

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITF) == (RTC_ICSR_INITF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Registers synchronization flag

+  * @rmtoll RTC_ICSR          RSF           LL_RTC_IsActiveFlag_RS

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RSF) == (RTC_ICSR_RSF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear Registers synchronization flag

+  * @rmtoll RTC_ICSR          RSF           LL_RTC_ClearFlag_RS

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx)

+{

+  WRITE_REG(RTCx->ICSR, (~((RTC_ICSR_RSF | RTC_ICSR_INIT) & 0x000000FFU) | (RTCx->ICSR & RTC_ICSR_INIT)));

+}

+

+/**

+  * @brief  Get Initialization status flag

+  * @rmtoll RTC_ICSR          INITS         LL_RTC_IsActiveFlag_INITS

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITS) == (RTC_ICSR_INITS)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Shift operation pending flag

+  * @rmtoll RTC_ICSR          SHPF          LL_RTC_IsActiveFlag_SHP

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->ICSR, RTC_ICSR_SHPF) == (RTC_ICSR_SHPF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Wakeup timer write flag

+  * @rmtoll RTC_ICSR          WUTWF         LL_RTC_IsActiveFlag_WUTW

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->ICSR, RTC_ICSR_WUTWF) == (RTC_ICSR_WUTWF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Alarm B write flag

+  * @rmtoll RTC_ICSR         ALRBWF        LL_RTC_IsActiveFlag_ALRBW

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBW(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->ICSR, RTC_ICSR_ALRBWF) == (RTC_ICSR_ALRBWF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Alarm A write flag

+  * @rmtoll RTC_ICSR         ALRAWF        LL_RTC_IsActiveFlag_ALRAW

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAW(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->ICSR, RTC_ICSR_ALRAWF) == (RTC_ICSR_ALRAWF)) ? 1UL : 0UL);

+}

+#endif /* RTC_ICSR_RECALPF */

+

+#if defined(RTC_MISR_ALRAMF)

+/**

+  * @brief  Get Alarm A masked flag.

+  * @rmtoll RTC_MISR          ALRAMF        LL_RTC_IsActiveFlag_ALRAM

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRAMF) == (RTC_MISR_ALRAMF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Alarm B masked flag.

+  * @rmtoll RTC_MISR          ALRBMF        LL_RTC_IsActiveFlag_ALRBM

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRBMF) == (RTC_MISR_ALRBMF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Wakeup timer masked flag.

+  * @rmtoll RTC_MISR          WUTMF        LL_RTC_IsActiveFlag_WUTM

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->MISR, RTC_MISR_WUTMF) == (RTC_MISR_WUTMF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Time-stamp masked flag.

+  * @rmtoll RTC_MISR          TSMF        LL_RTC_IsActiveFlag_TSM

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->MISR, RTC_MISR_TSMF) == (RTC_MISR_TSMF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Time-stamp overflow masked flag.

+  * @rmtoll RTC_MISR          TSOVMF        LL_RTC_IsActiveFlag_TSOVM

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->MISR, RTC_MISR_TSOVMF) == (RTC_MISR_TSOVMF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Internal Time-stamp masked flag.

+  * @rmtoll RTC_MISR          ITSMF        LL_RTC_IsActiveFlag_ITSM

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->MISR, RTC_MISR_ITSMF) == (RTC_MISR_ITSMF)) ? 1UL : 0UL);

+}

+#endif /* RTC_MISR_ALRAMF */

+

+#if defined(TAMP_CR1_TAMP1E)

+/**

+  * @brief  Get tamper 1 detection flag.

+  * @rmtoll TAMP_SR          TAMP1F        LL_RTC_IsActiveFlag_TAMP1

+  * @param  TAMPx TAMP Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(TAMP_TypeDef *TAMPx)

+{

+  return ((READ_BIT(TAMPx->SR, TAMP_SR_TAMP1F) == (TAMP_SR_TAMP1F)) ? 1UL : 0UL);

+}

+#endif /* TAMP_CR1_TAMP1E */

+

+#if defined(TAMP_CR1_TAMP2E)

+/**

+  * @brief  Get tamper 2 detection flag.

+  * @rmtoll TAMP_SR          TAMP2F        LL_RTC_IsActiveFlag_TAMP2

+  * @param  TAMPx TAMP Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(TAMP_TypeDef *TAMPx)

+{

+  return ((READ_BIT(TAMPx->SR, TAMP_SR_TAMP2F) == (TAMP_SR_TAMP2F)) ? 1UL : 0UL);

+}

+#endif /* TAMP_CR1_TAMP2E */

+

+#if defined(TAMP_CR1_TAMP3E)

+/**

+  * @brief  Get tamper 3 detection flag.

+  * @rmtoll TAMP_SR          TAMP3F        LL_RTC_IsActiveFlag_TAMP3

+  * @param  TAMPx TAMP Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(TAMP_TypeDef *TAMPx)

+{

+  return ((READ_BIT(TAMPx->SR, TAMP_SR_TAMP3F) == (TAMP_SR_TAMP3F)) ? 1UL : 0UL);

+}

+#endif /* TAMP_CR1_TAMP3E */

+

+#if defined(TAMP_CR1_TAMP1E)

+/**

+  * @brief  Get tamper 1 interrupt masked flag.

+  * @rmtoll TAMP_MISR          TAMP1MF        LL_RTC_IsActiveFlag_TAMP1M

+  * @param  TAMPx TAMP Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(TAMP_TypeDef *TAMPx)

+{

+  return ((READ_BIT(TAMPx->MISR, TAMP_MISR_TAMP1MF) == (TAMP_MISR_TAMP1MF)) ? 1UL : 0UL);

+}

+#endif /* TAMP_CR1_TAMP1E */

+

+#if defined(TAMP_CR1_TAMP2E)

+/**

+  * @brief  Get tamper 2 interrupt masked flag.

+  * @rmtoll TAMP_MISR          TAMP2MF        LL_RTC_IsActiveFlag_TAMP2M

+  * @param  TAMPx TAMP Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(TAMP_TypeDef *TAMPx)

+{

+  return ((READ_BIT(TAMPx->MISR, TAMP_MISR_TAMP2MF) == (TAMP_MISR_TAMP2MF)) ? 1UL : 0UL);

+}

+#endif /* TAMP_CR1_TAMP2E */

+

+#if defined(TAMP_CR1_TAMP3E)

+/**

+  * @brief  Get tamper 3 interrupt masked flag.

+  * @rmtoll TAMP_MISR          TAMP3MF        LL_RTC_IsActiveFlag_TAMP3M

+  * @param  TAMPx TAMP Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(TAMP_TypeDef *TAMPx)

+{

+  return ((READ_BIT(TAMPx->MISR, TAMP_MISR_TAMP3MF) == (TAMP_MISR_TAMP3MF)) ? 1UL : 0UL);

+}

+#endif /* TAMP_CR1_TAMP3E */

+

+#if defined(TAMP_CR1_TAMP1E)

+/**

+  * @brief  Clear tamper 1 detection flag.

+  * @rmtoll TAMP_SCR          CTAMP1F         LL_RTC_ClearFlag_TAMP1

+  * @param  TAMPx TAMP Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(TAMP_TypeDef *TAMPx)

+{

+  SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP1F);

+}

+#endif /* TAMP_CR1_TAMP1E */

+

+#if defined(TAMP_CR1_TAMP2E)

+/**

+  * @brief  Clear tamper 2 detection flag.

+  * @rmtoll TAMP_SCR          CTAMP2F         LL_RTC_ClearFlag_TAMP2

+  * @param  TAMPx TAMP Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(TAMP_TypeDef *TAMPx)

+{

+  SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP2F);

+}

+#endif /* TAMP_CR1_TAMP2E */

+

+#if defined(TAMP_CR1_TAMP3E)

+/**

+  * @brief  Clear tamper 3 detection flag.

+  * @rmtoll TAMP_SCR          CTAMP3F         LL_RTC_ClearFlag_TAMP3

+  * @param  TAMPx TAMP Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(TAMP_TypeDef *TAMPx)

+{

+  SET_BIT(TAMPx->SCR, TAMP_SCR_CTAMP3F);

+}

+#endif /* TAMP_CR1_TAMP3E */

+

+/**

+  * @}

+  */

+

+/** @defgroup RTC_LL_EF_IT_Management IT_Management

+  * @{

+  */

+

+/**

+  * @brief  Enable Time-stamp interrupt

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @rmtoll RTC_CR          TSIE         LL_RTC_EnableIT_TS

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_EnableIT_TS(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->CR, RTC_CR_TSIE);

+}

+

+/**

+  * @brief  Disable Time-stamp interrupt

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @rmtoll RTC_CR          TSIE         LL_RTC_DisableIT_TS

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_DisableIT_TS(RTC_TypeDef *RTCx)

+{

+  CLEAR_BIT(RTCx->CR, RTC_CR_TSIE);

+}

+

+/**

+  * @brief  Enable Wakeup timer interrupt

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @rmtoll RTC_CR          WUTIE         LL_RTC_EnableIT_WUT

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_EnableIT_WUT(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->CR, RTC_CR_WUTIE);

+}

+

+/**

+  * @brief  Disable Wakeup timer interrupt

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @rmtoll RTC_CR          WUTIE         LL_RTC_DisableIT_WUT

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_DisableIT_WUT(RTC_TypeDef *RTCx)

+{

+  CLEAR_BIT(RTCx->CR, RTC_CR_WUTIE);

+}

+

+/**

+  * @brief  Enable Alarm B interrupt

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @rmtoll RTC_CR           ALRBIE        LL_RTC_EnableIT_ALRB

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_EnableIT_ALRB(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->CR, RTC_CR_ALRBIE);

+}

+

+/**

+  * @brief  Disable Alarm B interrupt

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @rmtoll RTC_CR           ALRBIE        LL_RTC_DisableIT_ALRB

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_DisableIT_ALRB(RTC_TypeDef *RTCx)

+{

+  CLEAR_BIT(RTCx->CR, RTC_CR_ALRBIE);

+}

+

+/**

+  * @brief  Enable Alarm A interrupt

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @rmtoll RTC_CR           ALRAIE        LL_RTC_EnableIT_ALRA

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_EnableIT_ALRA(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->CR, RTC_CR_ALRAIE);

+}

+

+/**

+  * @brief  Disable Alarm A interrupt

+  * @note   Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before.

+  * @rmtoll RTC_CR           ALRAIE        LL_RTC_DisableIT_ALRA

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx)

+{

+  CLEAR_BIT(RTCx->CR, RTC_CR_ALRAIE);

+}

+

+#if defined(RTC_TAMPCR_TAMP3E)

+/**

+  * @brief  Enable Tamper 3 interrupt

+  * @rmtoll TAMPCR       TAMP3IE       LL_RTC_EnableIT_TAMP3

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_EnableIT_TAMP3(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE);

+}

+

+/**

+  * @brief  Disable Tamper 3 interrupt

+  * @rmtoll TAMPCR       TAMP3IE       LL_RTC_DisableIT_TAMP3

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_DisableIT_TAMP3(RTC_TypeDef *RTCx)

+{

+  CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE);

+}

+#endif /* RTC_TAMPCR_TAMP3E */

+

+#if defined(RTC_TAMPCR_TAMP2E)

+/**

+  * @brief  Enable Tamper 2 interrupt

+  * @rmtoll TAMPCR       TAMP2IE       LL_RTC_EnableIT_TAMP2

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_EnableIT_TAMP2(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE);

+}

+

+/**

+  * @brief  Disable Tamper 2 interrupt

+  * @rmtoll TAMPCR       TAMP2IE       LL_RTC_DisableIT_TAMP2

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_DisableIT_TAMP2(RTC_TypeDef *RTCx)

+{

+  CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE);

+}

+#endif /* RTC_TAMPCR_TAMP2E */

+

+#if defined(RTC_TAMPCR_TAMP1E)

+/**

+  * @brief  Enable Tamper 1 interrupt

+  * @rmtoll TAMPCR       TAMP1IE       LL_RTC_EnableIT_TAMP1

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_EnableIT_TAMP1(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE);

+}

+

+/**

+  * @brief  Disable Tamper 1 interrupt

+  * @rmtoll TAMPCR       TAMP1IE       LL_RTC_DisableIT_TAMP1

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_DisableIT_TAMP1(RTC_TypeDef *RTCx)

+{

+  CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE);

+}

+#endif /* RTC_TAMPCR_TAMP1E */

+

+#if defined(RTC_TAMPCR_TAMPIE)

+/**

+  * @brief  Enable all Tamper Interrupt

+  * @rmtoll TAMPCR       TAMPIE        LL_RTC_EnableIT_TAMP

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_EnableIT_TAMP(RTC_TypeDef *RTCx)

+{

+  SET_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE);

+}

+

+/**

+  * @brief  Disable all Tamper Interrupt

+  * @rmtoll TAMPCR       TAMPIE        LL_RTC_DisableIT_TAMP

+  * @param  RTCx RTC Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_DisableIT_TAMP(RTC_TypeDef *RTCx)

+{

+  CLEAR_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE);

+}

+#endif /* RTC_TAMPCR_TAMPIE */

+

+/**

+  * @brief  Check if  Time-stamp interrupt is enabled or not

+  * @rmtoll CR           TSIE          LL_RTC_IsEnabledIT_TS

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if  Wakeup timer interrupt is enabled or not

+  * @rmtoll CR           WUTIE         LL_RTC_IsEnabledIT_WUT

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if  Alarm B interrupt is enabled or not

+  * @rmtoll CR           ALRBIE        LL_RTC_IsEnabledIT_ALRB

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if  Alarm A interrupt is enabled or not

+  * @rmtoll CR           ALRAIE        LL_RTC_IsEnabledIT_ALRA

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1UL : 0UL);

+}

+

+#if defined(RTC_TAMPCR_TAMP3E)

+/**

+  * @brief  Check if  Tamper 3 interrupt is enabled or not

+  * @rmtoll TAMPCR       TAMP3IE       LL_RTC_IsEnabledIT_TAMP3

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP3IE) == (RTC_TAMPCR_TAMP3IE)) ? 1UL : 0UL);

+}

+#endif /* RTC_TAMPCR_TAMP3E */

+

+#if defined(RTC_TAMPCR_TAMP2E)

+/**

+  * @brief  Check if  Tamper 2 interrupt is enabled or not

+  * @rmtoll TAMPCR       TAMP2IE       LL_RTC_IsEnabledIT_TAMP2

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP2IE) == (RTC_TAMPCR_TAMP2IE)) ? 1UL : 0UL);

+

+}

+#endif /* RTC_TAMPCR_TAMP2E */

+

+#if defined(RTC_TAMPCR_TAMP1E)

+/**

+  * @brief  Check if  Tamper 1 interrupt is enabled or not

+  * @rmtoll TAMPCR       TAMP1IE       LL_RTC_IsEnabledIT_TAMP1

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMP1IE) == (RTC_TAMPCR_TAMP1IE)) ? 1UL : 0UL);

+}

+#endif /* RTC_TAMPCR_TAMP1E */

+

+#if defined(RTC_TAMPCR_TAMPIE)

+/**

+  * @brief  Check if all the TAMPER interrupts are enabled or not

+  * @rmtoll TAMPCR       TAMPIE        LL_RTC_IsEnabledIT_TAMP

+  * @param  RTCx RTC Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP(RTC_TypeDef *RTCx)

+{

+  return ((READ_BIT(RTCx->TAMPCR, RTC_TAMPCR_TAMPIE) == (RTC_TAMPCR_TAMPIE)) ? 1UL : 0UL);

+}

+#endif /* RTC_TAMPCR_TAMPIE */

+

+#if defined(TAMP_CR1_TAMP1E)

+/**

+  * @brief  Enable tamper 1 interrupt.

+  * @rmtoll TAMP_IER           TAMP1IE          LL_RTC_EnableIT_TAMP1

+  * @param  TAMPx TAMP Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_EnableIT_TAMP1(TAMP_TypeDef *TAMPx)

+{

+  SET_BIT(TAMPx->IER, TAMP_IER_TAMP1IE);

+}

+

+/**

+  * @brief  Disable tamper 1 interrupt.

+  * @rmtoll TAMP_IER           TAMP1IE          LL_RTC_DisableIT_TAMP1

+  * @param  TAMPx TAMP Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_DisableIT_TAMP1(TAMP_TypeDef *TAMPx)

+{

+  CLEAR_BIT(TAMPx->IER, TAMP_IER_TAMP1IE);

+}

+#endif /* TAMP_CR1_TAMP1E */

+

+#if defined(TAMP_CR1_TAMP2E)

+/**

+  * @brief  Enable tamper 2 interrupt.

+  * @rmtoll TAMP_IER           TAMP2IE          LL_RTC_EnableIT_TAMP2

+  * @param  TAMPx TAMP Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_EnableIT_TAMP2(TAMP_TypeDef *TAMPx)

+{

+  SET_BIT(TAMPx->IER, TAMP_IER_TAMP2IE);

+}

+

+/**

+  * @brief  Disable tamper 2 interrupt.

+  * @rmtoll TAMP_IER           TAMP2IE          LL_RTC_DisableIT_TAMP2

+  * @param  TAMPx TAMP Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_DisableIT_TAMP2(TAMP_TypeDef *TAMPx)

+{

+  CLEAR_BIT(TAMPx->IER, TAMP_IER_TAMP2IE);

+}

+#endif /* TAMP_CR1_TAMP2E */

+

+#if defined(TAMP_CR1_TAMP3E)

+/**

+  * @brief  Enable tamper 3 interrupt.

+  * @rmtoll TAMP_IER           TAMP3IE          LL_RTC_EnableIT_TAMP3

+  * @param  TAMPx TAMP Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_EnableIT_TAMP3(TAMP_TypeDef *TAMPx)

+{

+  SET_BIT(TAMPx->IER, TAMP_IER_TAMP3IE);

+}

+

+/**

+  * @brief  Disable tamper 3 interrupt.

+  * @rmtoll TAMP_IER           TAMP3IE          LL_RTC_DisableIT_TAMP3

+  * @param  TAMPx TAMP Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_DisableIT_TAMP3(TAMP_TypeDef *TAMPx)

+{

+  CLEAR_BIT(TAMPx->IER, TAMP_IER_TAMP3IE);

+}

+#endif /* TAMP_CR1_TAMP3E */

+

+#if defined(TAMP_CR1_TAMP1E)

+/**

+  * @brief  Check if tamper 1 interrupt is enabled or not.

+  * @rmtoll TAMP_IER           TAMP1IE        LL_RTC_IsEnabledIT_TAMP1

+  * @param  TAMPx TAMP Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(TAMP_TypeDef *TAMPx)

+{

+  return ((READ_BIT(TAMPx->IER, TAMP_IER_TAMP1IE) == (TAMP_IER_TAMP1IE)) ? 1UL : 0UL);

+}

+#endif /* TAMP_CR1_TAMP1E */

+

+#if defined(TAMP_CR1_TAMP2E)

+/**

+  * @brief  Check if tamper 2 interrupt is enabled or not.

+  * @rmtoll TAMP_IER           TAMP2IE        LL_RTC_IsEnabledIT_TAMP2

+  * @param  TAMPx TAMP Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(TAMP_TypeDef *TAMPx)

+{

+  return ((READ_BIT(TAMPx->IER, TAMP_IER_TAMP2IE) == (TAMP_IER_TAMP2IE)) ? 1UL : 0UL);

+}

+#endif /* TAMP_CR1_TAMP2E */

+

+#if defined(TAMP_CR1_TAMP3E)

+/**

+  * @brief  Check if tamper 3 interrupt is enabled or not.

+  * @rmtoll TAMP_IER           TAMP3IE        LL_RTC_IsEnabledIT_TAMP3

+  * @param  TAMPx TAMP Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(TAMP_TypeDef *TAMPx)

+{

+  return ((READ_BIT(TAMPx->IER, TAMP_IER_TAMP3IE) == (TAMP_IER_TAMP3IE)) ? 1UL : 0UL);

+}

+#endif /* TAMP_CR1_TAMP3E */

+

+/**

+  * @}

+  */

+

+#if defined (TAMP_ATCR1_TAMP1AM)

+/** @defgroup RTC_LL_EF_Active_Tamper Active Tamper

+  * @{

+  */

+/**

+  * @brief  Enable tamper active mode.

+  * @rmtoll TAMP_ATCR1     TAMP1AM       LL_RTC_TAMPER_ATAMP_EnableActiveMode

+  * @rmtoll TAMP_ATCR1     TAMP2AM       LL_RTC_TAMPER_ATAMP_EnableActiveMode

+  * @rmtoll TAMP_ATCR1     TAMPxAM       LL_RTC_TAMPER_ATAMP_EnableActiveMode

+  * @param  Tamper to configure as active. This parameter can be a combination of the following values:

+  *         @arg @ref RTC_LL_EC_ACTIVE_MODE

+  *

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableActiveMode(uint32_t Tamper)

+{

+  SET_BIT(TAMP->ATCR1, Tamper);

+}

+

+/**

+  * @brief  Disable tamper active mode.

+  * @rmtoll TAMP_ATCR1     TAMP1AM       LL_RTC_TAMPER_ATAMP_DisableActiveMode

+  * @rmtoll TAMP_ATCR1     TAMP2AM       LL_RTC_TAMPER_ATAMP_DisableActiveMode

+  * @rmtoll TAMP_ATCR1     TAMPxAM       LL_RTC_TAMPER_ATAMP_DisableActiveMode

+  * @param  Tamper to configure as active. This parameter can be a combination of the following values:

+  *         @arg @ref RTC_LL_EC_ACTIVE_MODE

+  *

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableActiveMode(uint32_t Tamper)

+{

+  CLEAR_BIT(TAMP->ATCR1, Tamper);

+}

+

+/**

+  * @brief  Enable active tamper filter.

+  * @rmtoll TAMP_ATCR1     FLTEN         LL_RTC_TAMPER_ATAMP_EnableFilter

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableFilter(void)

+{

+  SET_BIT(TAMP->ATCR1, TAMP_ATCR1_FLTEN);

+}

+

+/**

+  * @brief  Disable active tamper filter.

+  * @rmtoll TAMP_ATCR1     FLTEN         LL_RTC_TAMPER_ATAMP_DisableFilter

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableFilter(void)

+{

+  CLEAR_BIT(TAMP->ATCR1, TAMP_ATCR1_FLTEN);

+}

+

+/**

+  * @brief  Set Active tamper output change period.

+  * @rmtoll TAMP_ATCR1     ATPER         LL_RTC_TAMPER_ATAMP_SetOutputChangePeriod

+  * @param  ActiveOutputChangePeriod This parameter can be a value from 0 to 7

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetOutputChangePeriod(uint32_t ActiveOutputChangePeriod)

+{

+  MODIFY_REG(TAMP->ATCR1, TAMP_ATCR1_ATPER, (ActiveOutputChangePeriod << TAMP_ATCR1_ATPER_Pos));

+}

+

+/**

+  * @brief  Get Active tamper output change period.

+  * @rmtoll TAMP_ATCR1     ATPER         LL_RTC_TAMPER_ATAMP_GetOutputChangePeriod

+  * @retval Output change period. This parameter can be a value from 0 to 7.

+  */

+__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetOutputChangePeriod(void)

+{

+  return (READ_BIT(TAMP->ATCR1, TAMP_ATCR1_ATPER) >> TAMP_ATCR1_ATPER_Pos);

+}

+

+/**

+  * @brief  Set Active tamper asynchronous prescaler clock selection.

+  * @rmtoll TAMP_ATCR1     ATCKSEL       LL_RTC_TAMPER_ATAMP_SetAsyncPrescaler

+  * @param  ActiveAsynvPrescaler Specifies the Active Tamper asynchronous Prescaler clock.

+            This parameter can be a value of the following values:

+  *         @arg @ref RTC_LL_EC_ACTIVE_ASYNC_PRESCALER

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetAsyncPrescaler(uint32_t ActiveAsynvPrescaler)

+{

+  MODIFY_REG(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL, ActiveAsynvPrescaler);

+}

+

+/**

+  * @brief  Get Active tamper asynchronous prescaler clock selection.

+  * @rmtoll TAMP_ATCR1     ATCKSEL       LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler

+  * @retval One of @arg @ref RTC_LL_EC_ACTIVE_ASYNC_PRESCALER

+  */

+__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler(void)

+{

+  return (READ_BIT(TAMP->ATCR1, TAMP_ATCR1_ATCKSEL));

+}

+

+/**

+  * @brief  Enable active tamper output sharing.

+  * @rmtoll TAMP_ATCR1     ATOSHARE      LL_RTC_TAMPER_ATAMP_EnableOutputSharing

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_EnableOutputSharing(void)

+{

+  SET_BIT(TAMP->ATCR1, TAMP_ATCR1_ATOSHARE);

+}

+

+/**

+  * @brief  Disable active tamper output sharing.

+  * @rmtoll TAMP_ATCR1     ATOSHARE      LL_RTC_TAMPER_ATAMP_DisableOutputSharing

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_DisableOutputSharing(void)

+{

+  CLEAR_BIT(TAMP->ATCR1, TAMP_ATCR1_ATOSHARE);

+}

+

+/**

+  * @brief  Set Active tamper output selection.

+  * @rmtoll TAMP_ATCR1     ATCKSEL       LL_RTC_TAMPER_ATAMP_SetSharedOuputSelection

+  * @param  OutputSelection Specifies all the output selection of the Active Tamper.

+            This parameter is a combinasation of the following values:

+  *         One of @arg @ref RTC_LL_EC_ACTIVE_OUTPUT_SELECTION

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_SetSharedOuputSelection(uint32_t OutputSelection)

+{

+  MODIFY_REG(TAMP->ATCR1, (TAMP_ATCR1_ATOSEL1 | TAMP_ATCR1_ATOSEL2 | TAMP_ATCR1_ATOSEL3), \

+             OutputSelection);

+}

+

+/**

+  * @brief  Get Active tamper asynchronous prescaler clock selection.

+  * @rmtoll TAMP_ATCR2     ATCKSEL       LL_RTC_TAMPER_ATAMP_GetAsyncPrescaler

+  * @retval A combination of @arg @ref RTC_LL_EC_ACTIVE_OUTPUT_SELECTION

+  */

+__STATIC_INLINE uint32_t LL_RTC_TAMPER_ATAMP_GetSharedOuputSelection(void)

+{

+  return (READ_BIT(TAMP->ATCR1, (TAMP_ATCR1_ATOSEL1 | TAMP_ATCR1_ATOSEL2 | TAMP_ATCR1_ATOSEL3)));

+}

+#endif /* TAMP_ATCR1_TAMP1AM */

+

+#if defined(ATSEEDR)

+/**

+  * @brief  Write active tamper seed.

+  * @rmtoll TAMP_ATSEEDR   SEED          LL_RTC_TAMPER_ATAMP_WriteSeed

+  * @param  Seed

+  * @retval None

+  */

+__STATIC_INLINE void LL_RTC_TAMPER_ATAMP_WriteSeed(uint32_t Seed)

+{

+  WRITE_REG(TAMP->ATSEEDR, Seed);

+}

+#endif /* ATSEEDR */

+

+#if defined(TAMP_ATOR_INITS)

+/**

+  * @brief  Get active tamper initialization status flag.

+  * @rmtoll TAMP_ATOR      INITS         LL_RTC_IsActiveFlag_ATAMP_INITS

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ATAMP_INITS(void)

+{

+  return ((READ_BIT(TAMP->ATOR, TAMP_ATOR_INITS) == (TAMP_ATOR_INITS)) ? 1U : 0U);

+}

+

+/**

+  * @brief  Get active tamper seed running status flag.

+  * @rmtoll TAMP_ATOR      INITS         LL_RTC_IsActiveFlag_ATAMP_INITS

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ATAMP_SEEDF(void)

+{

+  return ((READ_BIT(TAMP->ATOR, TAMP_ATOR_SEEDF) == (TAMP_ATOR_SEEDF)) ? 1U : 0U);

+}

+#endif /* TAMP_ATOR_INITS */

+

+/**

+  * @}

+  */

+

+

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions

+  * @{

+  */

+

+ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx);

+ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct);

+void        LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct);

+ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct);

+void        LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct);

+ErrorStatus LL_RTC_DATE_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_DateTypeDef *RTC_DateStruct);

+void        LL_RTC_DATE_StructInit(LL_RTC_DateTypeDef *RTC_DateStruct);

+ErrorStatus LL_RTC_ALMA_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);

+ErrorStatus LL_RTC_ALMB_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct);

+void        LL_RTC_ALMA_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);

+void        LL_RTC_ALMB_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct);

+ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx);

+ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx);

+ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx);

+

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* defined(RTC) */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_LL_RTC_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_sdmmc.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_sdmmc.h
new file mode 100644
index 0000000000..51ec6e9abc
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_sdmmc.h
@@ -0,0 +1,1102 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_sdmmc.h

+  * @author  MCD Application Team

+  * @brief   Header file of SDMMC HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                       opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_LL_SDMMC_H

+#define STM32H7xx_LL_SDMMC_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+/** @addtogroup STM32H7xx_Driver

+  * @{

+  */

+

+/** @addtogroup SDMMC_LL

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types

+  * @{

+  */

+

+/**

+  * @brief  SDMMC Configuration Structure definition

+  */

+typedef struct

+{

+  uint32_t ClockEdge;            /*!< Specifies the SDMMC_CCK clock transition on which Data and Command change.

+                                      This parameter can be a value of @ref SDMMC_LL_Clock_Edge                 */

+

+  uint32_t ClockPowerSave;       /*!< Specifies whether SDMMC Clock output is enabled or

+                                      disabled when the bus is idle.

+                                      This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save           */

+

+  uint32_t BusWide;              /*!< Specifies the SDMMC bus width.

+                                      This parameter can be a value of @ref SDMMC_LL_Bus_Wide                   */

+

+  uint32_t HardwareFlowControl;  /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.

+                                      This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control      */

+

+  uint32_t ClockDiv;             /*!< Specifies the clock frequency of the SDMMC controller.

+                                      This parameter can be a value between Min_Data = 0 and Max_Data = 1023   */

+

+#if (USE_SD_TRANSCEIVER != 0U)

+  uint32_t TranceiverPresent;    /*!< Specifies if there is a 1V8 Tranceiver/Switcher.

+                                      This parameter can be a value of @ref SDMMC_LL_TRANCEIVER_PRESENT        */

+#endif /* USE_SD_TRANSCEIVER */

+}SDMMC_InitTypeDef;

+

+

+/**

+  * @brief  SDMMC Command Control structure

+  */

+typedef struct

+{

+  uint32_t Argument;            /*!< Specifies the SDMMC command argument which is sent

+                                     to a card as part of a command message. If a command

+                                     contains an argument, it must be loaded into this register

+                                     before writing the command to the command register.              */

+

+  uint32_t CmdIndex;            /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and

+                                     Max_Data = 64                                                    */

+

+  uint32_t Response;            /*!< Specifies the SDMMC response type.

+                                     This parameter can be a value of @ref SDMMC_LL_Response_Type         */

+

+  uint32_t WaitForInterrupt;    /*!< Specifies whether SDMMC wait for interrupt request is

+                                     enabled or disabled.

+                                     This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State  */

+

+  uint32_t CPSM;                /*!< Specifies whether SDMMC Command path state machine (CPSM)

+                                     is enabled or disabled.

+                                     This parameter can be a value of @ref SDMMC_LL_CPSM_State            */

+}SDMMC_CmdInitTypeDef;

+

+

+/**

+  * @brief  SDMMC Data Control structure

+  */

+typedef struct

+{

+  uint32_t DataTimeOut;         /*!< Specifies the data timeout period in card bus clock periods.  */

+

+  uint32_t DataLength;          /*!< Specifies the number of data bytes to be transferred.         */

+

+  uint32_t DataBlockSize;       /*!< Specifies the data block size for block transfer.

+                                     This parameter can be a value of @ref SDMMC_LL_Data_Block_Size    */

+

+  uint32_t TransferDir;         /*!< Specifies the data transfer direction, whether the transfer

+                                     is a read or write.

+                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */

+

+  uint32_t TransferMode;        /*!< Specifies whether data transfer is in stream or block mode.

+                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Type      */

+

+  uint32_t DPSM;                /*!< Specifies whether SDMMC Data path state machine (DPSM)

+                                     is enabled or disabled.

+                                     This parameter can be a value of @ref SDMMC_LL_DPSM_State         */

+}SDMMC_DataInitTypeDef;

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants

+  * @{

+  */

+#define SDMMC_ERROR_NONE                     ((uint32_t)0x00000000U)   /*!< No error                                                      */

+#define SDMMC_ERROR_CMD_CRC_FAIL             ((uint32_t)0x00000001U)   /*!< Command response received (but CRC check failed)              */

+#define SDMMC_ERROR_DATA_CRC_FAIL            ((uint32_t)0x00000002U)   /*!< Data block sent/received (CRC check failed)                   */

+#define SDMMC_ERROR_CMD_RSP_TIMEOUT          ((uint32_t)0x00000004U)   /*!< Command response timeout                                      */

+#define SDMMC_ERROR_DATA_TIMEOUT             ((uint32_t)0x00000008U)   /*!< Data timeout                                                  */

+#define SDMMC_ERROR_TX_UNDERRUN              ((uint32_t)0x00000010U)   /*!< Transmit FIFO underrun                                        */

+#define SDMMC_ERROR_RX_OVERRUN               ((uint32_t)0x00000020U)   /*!< Receive FIFO overrun                                          */

+#define SDMMC_ERROR_ADDR_MISALIGNED          ((uint32_t)0x00000040U)   /*!< Misaligned address                                            */

+#define SDMMC_ERROR_BLOCK_LEN_ERR            ((uint32_t)0x00000080U)   /*!< Transferred block length is not allowed for the card or the

+                                                                            number of transferred bytes does not match the block length   */

+#define SDMMC_ERROR_ERASE_SEQ_ERR            ((uint32_t)0x00000100U)   /*!< An error in the sequence of erase command occurs              */

+#define SDMMC_ERROR_BAD_ERASE_PARAM          ((uint32_t)0x00000200U)   /*!< An invalid selection for erase groups                         */

+#define SDMMC_ERROR_WRITE_PROT_VIOLATION     ((uint32_t)0x00000400U)   /*!< Attempt to program a write protect block                      */

+#define SDMMC_ERROR_LOCK_UNLOCK_FAILED       ((uint32_t)0x00000800U)   /*!< Sequence or password error has been detected in unlock

+                                                                            command or if there was an attempt to access a locked card    */

+#define SDMMC_ERROR_COM_CRC_FAILED           ((uint32_t)0x00001000U)   /*!< CRC check of the previous command failed                      */

+#define SDMMC_ERROR_ILLEGAL_CMD              ((uint32_t)0x00002000U)   /*!< Command is not legal for the card state                       */

+#define SDMMC_ERROR_CARD_ECC_FAILED          ((uint32_t)0x00004000U)   /*!< Card internal ECC was applied but failed to correct the data  */

+#define SDMMC_ERROR_CC_ERR                   ((uint32_t)0x00008000U)   /*!< Internal card controller error                                */

+#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR      ((uint32_t)0x00010000U)   /*!< General or unknown error                                      */

+#define SDMMC_ERROR_STREAM_READ_UNDERRUN     ((uint32_t)0x00020000U)   /*!< The card could not sustain data reading in stream rmode       */

+#define SDMMC_ERROR_STREAM_WRITE_OVERRUN     ((uint32_t)0x00040000U)   /*!< The card could not sustain data programming in stream mode    */

+#define SDMMC_ERROR_CID_CSD_OVERWRITE        ((uint32_t)0x00080000U)   /*!< CID/CSD overwrite error                                       */

+#define SDMMC_ERROR_WP_ERASE_SKIP            ((uint32_t)0x00100000U)   /*!< Only partial address space was erased                         */

+#define SDMMC_ERROR_CARD_ECC_DISABLED        ((uint32_t)0x00200000U)   /*!< Command has been executed without using internal ECC          */

+#define SDMMC_ERROR_ERASE_RESET              ((uint32_t)0x00400000U)   /*!< Erase sequence was cleared before executing because an out

+                                                                            of erase sequence command was received                        */

+#define SDMMC_ERROR_AKE_SEQ_ERR              ((uint32_t)0x00800000U)   /*!< Error in sequence of authentication                           */

+#define SDMMC_ERROR_INVALID_VOLTRANGE        ((uint32_t)0x01000000U)   /*!< Error in case of invalid voltage range                        */

+#define SDMMC_ERROR_ADDR_OUT_OF_RANGE        ((uint32_t)0x02000000U)   /*!< Error when addressed block is out of range                    */

+#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE   ((uint32_t)0x04000000U)   /*!< Error when command request is not applicable                  */

+#define SDMMC_ERROR_INVALID_PARAMETER        ((uint32_t)0x08000000U)   /*!< the used parameter is not valid                               */

+#define SDMMC_ERROR_UNSUPPORTED_FEATURE      ((uint32_t)0x10000000U)   /*!< Error when feature is not insupported                         */

+#define SDMMC_ERROR_BUSY                     ((uint32_t)0x20000000U)   /*!< Error when transfer process is busy                           */

+#define SDMMC_ERROR_DMA                      ((uint32_t)0x40000000U)   /*!< Error while DMA transfer                                      */

+#define SDMMC_ERROR_TIMEOUT                  ((uint32_t)0x80000000U)   /*!< Timeout error                                                 */

+

+/**

+  * @brief SDMMC Commands Index

+  */

+#define SDMMC_CMD_GO_IDLE_STATE                       ((uint8_t)0U)   /*!< Resets the SD memory card.                                                               */

+#define SDMMC_CMD_SEND_OP_COND                        ((uint8_t)1U)   /*!< Sends host capacity support information and activates the card's initialization process. */

+#define SDMMC_CMD_ALL_SEND_CID                        ((uint8_t)2U)   /*!< Asks any card connected to the host to send the CID numbers on the CMD line.             */

+#define SDMMC_CMD_SET_REL_ADDR                        ((uint8_t)3U)   /*!< Asks the card to publish a new relative address (RCA).                                   */

+#define SDMMC_CMD_SET_DSR                             ((uint8_t)4U)   /*!< Programs the DSR of all cards.                                                           */

+#define SDMMC_CMD_SDMMC_SEN_OP_COND                   ((uint8_t)5U)   /*!< Sends host capacity support information (HCS) and asks the accessed card to send its

+                                                                           operating condition register (OCR) content in the response on the CMD line.                  */

+#define SDMMC_CMD_HS_SWITCH                           ((uint8_t)6U)   /*!< Checks switchable function (mode 0) and switch card function (mode 1).                   */

+#define SDMMC_CMD_SEL_DESEL_CARD                      ((uint8_t)7U)   /*!< Selects the card by its own relative address and gets deselected by any other address    */

+#define SDMMC_CMD_HS_SEND_EXT_CSD                     ((uint8_t)8U)   /*!< Sends SD Memory Card interface condition, which includes host supply voltage information

+                                                                           and asks the card whether card supports voltage.                                             */

+#define SDMMC_CMD_SEND_CSD                            ((uint8_t)9U)   /*!< Addressed card sends its card specific data (CSD) on the CMD line.                       */

+#define SDMMC_CMD_SEND_CID                            ((uint8_t)10U)  /*!< Addressed card sends its card identification (CID) on the CMD line.                      */

+#define SDMMC_CMD_VOLTAGE_SWITCH                      ((uint8_t)11U)  /*!< SD card Voltage switch to 1.8V mode.                                                     */

+#define SDMMC_CMD_STOP_TRANSMISSION                   ((uint8_t)12U)  /*!< Forces the card to stop transmission.                                                    */

+#define SDMMC_CMD_SEND_STATUS                         ((uint8_t)13U)  /*!< Addressed card sends its status register.                                                */

+#define SDMMC_CMD_HS_BUSTEST_READ                     ((uint8_t)14U)  /*!< Reserved                                                                                 */

+#define SDMMC_CMD_GO_INACTIVE_STATE                   ((uint8_t)15U)  /*!< Sends an addressed card into the inactive state.                                         */

+#define SDMMC_CMD_SET_BLOCKLEN                        ((uint8_t)16U)  /*!< Sets the block length (in bytes for SDSC) for all following block commands

+                                                                           (read, write, lock). Default block length is fixed to 512 Bytes. Not effective

+                                                                           for SDHS and SDXC.                                                                       */

+#define SDMMC_CMD_READ_SINGLE_BLOCK                   ((uint8_t)17U)  /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of

+                                                                           fixed 512 bytes in case of SDHC and SDXC.                                                */

+#define SDMMC_CMD_READ_MULT_BLOCK                     ((uint8_t)18U)  /*!< Continuously transfers data blocks from card to host until interrupted by

+                                                                           STOP_TRANSMISSION command.                                                               */

+#define SDMMC_CMD_HS_BUSTEST_WRITE                    ((uint8_t)19U)  /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104.                                    */

+#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP                ((uint8_t)20U)  /*!< Speed class control command.                                                             */

+#define SDMMC_CMD_SET_BLOCK_COUNT                     ((uint8_t)23U)  /*!< Specify block count for CMD18 and CMD25.                                                 */

+#define SDMMC_CMD_WRITE_SINGLE_BLOCK                  ((uint8_t)24U)  /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of

+                                                                           fixed 512 bytes in case of SDHC and SDXC.                                                */

+#define SDMMC_CMD_WRITE_MULT_BLOCK                    ((uint8_t)25U)  /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows.                    */

+#define SDMMC_CMD_PROG_CID                            ((uint8_t)26U)  /*!< Reserved for manufacturers.                                                              */

+#define SDMMC_CMD_PROG_CSD                            ((uint8_t)27U)  /*!< Programming of the programmable bits of the CSD.                                         */

+#define SDMMC_CMD_SET_WRITE_PROT                      ((uint8_t)28U)  /*!< Sets the write protection bit of the addressed group.                                    */

+#define SDMMC_CMD_CLR_WRITE_PROT                      ((uint8_t)29U)  /*!< Clears the write protection bit of the addressed group.                                  */

+#define SDMMC_CMD_SEND_WRITE_PROT                     ((uint8_t)30U)  /*!< Asks the card to send the status of the write protection bits.                           */

+#define SDMMC_CMD_SD_ERASE_GRP_START                  ((uint8_t)32U)  /*!< Sets the address of the first write block to be erased. (For SD card only).              */

+#define SDMMC_CMD_SD_ERASE_GRP_END                    ((uint8_t)33U)  /*!< Sets the address of the last write block of the continuous range to be erased.           */

+#define SDMMC_CMD_ERASE_GRP_START                     ((uint8_t)35U)  /*!< Sets the address of the first write block to be erased. Reserved for each command

+                                                                           system set by switch function command (CMD6).                                            */

+#define SDMMC_CMD_ERASE_GRP_END                       ((uint8_t)36U)  /*!< Sets the address of the last write block of the continuous range to be erased.

+                                                                           Reserved for each command system set by switch function command (CMD6).                  */

+#define SDMMC_CMD_ERASE                               ((uint8_t)38U)  /*!< Reserved for SD security applications.                                                   */

+#define SDMMC_CMD_FAST_IO                             ((uint8_t)39U)  /*!< SD card doesn't support it (Reserved).                                                   */

+#define SDMMC_CMD_GO_IRQ_STATE                        ((uint8_t)40U)  /*!< SD card doesn't support it (Reserved).                                                   */

+#define SDMMC_CMD_LOCK_UNLOCK                         ((uint8_t)42U)  /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by

+                                                                           the SET_BLOCK_LEN command.                                                               */

+#define SDMMC_CMD_APP_CMD                             ((uint8_t)55U)  /*!< Indicates to the card that the next command is an application specific command rather

+                                                                           than a standard command.                                                                 */

+#define SDMMC_CMD_GEN_CMD                             ((uint8_t)56U)  /*!< Used either to transfer a data block to the card or to get a data block from the card

+                                                                           for general purpose/application specific commands.                                       */

+#define SDMMC_CMD_NO_CMD                              ((uint8_t)64U)  /*!< No command                                                                               */

+

+/**

+  * @brief Following commands are SD Card Specific commands.

+  *        SDMMC_APP_CMD should be sent before sending these commands.

+  */

+#define SDMMC_CMD_APP_SD_SET_BUSWIDTH                 ((uint8_t)6U)   /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus

+                                                                            widths are given in SCR register.                                                       */

+#define SDMMC_CMD_SD_APP_STATUS                       ((uint8_t)13U)  /*!< (ACMD13) Sends the SD status.                                                            */

+#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS        ((uint8_t)22U)  /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with

+                                                                           32bit+CRC data block.                                                                    */

+#define SDMMC_CMD_SD_APP_OP_COND                      ((uint8_t)41U)  /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to

+                                                                           send its operating condition register (OCR) content in the response on the CMD line.     */

+#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT          ((uint8_t)42U)  /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card  */

+#define SDMMC_CMD_SD_APP_SEND_SCR                     ((uint8_t)51U)  /*!< Reads the SD Configuration Register (SCR).                                               */

+#define SDMMC_CMD_SDMMC_RW_DIRECT                     ((uint8_t)52U)  /*!< For SD I/O card only, reserved for security specification.                               */

+#define SDMMC_CMD_SDMMC_RW_EXTENDED                   ((uint8_t)53U)  /*!< For SD I/O card only, reserved for security specification.                               */

+

+/**

+  * @brief Following commands are SD Card Specific security commands.

+  *        SDMMC_CMD_APP_CMD should be sent before sending these commands.

+  */

+#define SDMMC_CMD_SD_APP_GET_MKB                      ((uint8_t)43U)

+#define SDMMC_CMD_SD_APP_GET_MID                      ((uint8_t)44U)

+#define SDMMC_CMD_SD_APP_SET_CER_RN1                  ((uint8_t)45U)

+#define SDMMC_CMD_SD_APP_GET_CER_RN2                  ((uint8_t)46U)

+#define SDMMC_CMD_SD_APP_SET_CER_RES2                 ((uint8_t)47U)

+#define SDMMC_CMD_SD_APP_GET_CER_RES1                 ((uint8_t)48U)

+#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK   ((uint8_t)18U)

+#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK  ((uint8_t)25U)

+#define SDMMC_CMD_SD_APP_SECURE_ERASE                 ((uint8_t)38U)

+#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA           ((uint8_t)49U)

+#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB             ((uint8_t)48U)

+

+/**

+  * @brief  Masks for errors Card Status R1 (OCR Register)

+  */

+#define SDMMC_OCR_ADDR_OUT_OF_RANGE        ((uint32_t)0x80000000U)

+#define SDMMC_OCR_ADDR_MISALIGNED          ((uint32_t)0x40000000U)

+#define SDMMC_OCR_BLOCK_LEN_ERR            ((uint32_t)0x20000000U)

+#define SDMMC_OCR_ERASE_SEQ_ERR            ((uint32_t)0x10000000U)

+#define SDMMC_OCR_BAD_ERASE_PARAM          ((uint32_t)0x08000000U)

+#define SDMMC_OCR_WRITE_PROT_VIOLATION     ((uint32_t)0x04000000U)

+#define SDMMC_OCR_LOCK_UNLOCK_FAILED       ((uint32_t)0x01000000U)

+#define SDMMC_OCR_COM_CRC_FAILED           ((uint32_t)0x00800000U)

+#define SDMMC_OCR_ILLEGAL_CMD              ((uint32_t)0x00400000U)

+#define SDMMC_OCR_CARD_ECC_FAILED          ((uint32_t)0x00200000U)

+#define SDMMC_OCR_CC_ERROR                 ((uint32_t)0x00100000U)

+#define SDMMC_OCR_GENERAL_UNKNOWN_ERROR    ((uint32_t)0x00080000U)

+#define SDMMC_OCR_STREAM_READ_UNDERRUN     ((uint32_t)0x00040000U)

+#define SDMMC_OCR_STREAM_WRITE_OVERRUN     ((uint32_t)0x00020000U)

+#define SDMMC_OCR_CID_CSD_OVERWRITE        ((uint32_t)0x00010000U)

+#define SDMMC_OCR_WP_ERASE_SKIP            ((uint32_t)0x00008000U)

+#define SDMMC_OCR_CARD_ECC_DISABLED        ((uint32_t)0x00004000U)

+#define SDMMC_OCR_ERASE_RESET              ((uint32_t)0x00002000U)

+#define SDMMC_OCR_AKE_SEQ_ERROR            ((uint32_t)0x00000008U)

+#define SDMMC_OCR_ERRORBITS                ((uint32_t)0xFDFFE008U)

+

+/**

+  * @brief  Masks for R6 Response

+  */

+#define SDMMC_R6_GENERAL_UNKNOWN_ERROR     ((uint32_t)0x00002000U)

+#define SDMMC_R6_ILLEGAL_CMD               ((uint32_t)0x00004000U)

+#define SDMMC_R6_COM_CRC_FAILED            ((uint32_t)0x00008000U)

+

+#define SDMMC_VOLTAGE_WINDOW_SD            ((uint32_t)0x80100000U)

+#define SDMMC_HIGH_CAPACITY                ((uint32_t)0x40000000U)

+#define SDMMC_STD_CAPACITY                 ((uint32_t)0x00000000U)

+#define SDMMC_CHECK_PATTERN                ((uint32_t)0x000001AAU)

+#define SD_SWITCH_1_8V_CAPACITY            ((uint32_t)0x01000000U)

+#define SDMMC_DDR50_SWITCH_PATTERN         ((uint32_t)0x80FFFF04U)

+#define SDMMC_SDR104_SWITCH_PATTERN        ((uint32_t)0x80FF1F03U)

+#define SDMMC_SDR50_SWITCH_PATTERN         ((uint32_t)0x80FF1F02U)

+#define SDMMC_SDR25_SWITCH_PATTERN         ((uint32_t)0x80FFFF01U)

+

+#define SDMMC_MAX_VOLT_TRIAL               ((uint32_t)0x0000FFFFU)

+

+#define SDMMC_MAX_TRIAL                    ((uint32_t)0x0000FFFFU)

+

+#define SDMMC_ALLZERO                      ((uint32_t)0x00000000U)

+

+#define SDMMC_WIDE_BUS_SUPPORT             ((uint32_t)0x00040000U)

+#define SDMMC_SINGLE_BUS_SUPPORT           ((uint32_t)0x00010000U)

+#define SDMMC_CARD_LOCKED                  ((uint32_t)0x02000000U)

+

+#define SDMMC_DATATIMEOUT                  ((uint32_t)0xFFFFFFFFU)

+

+#define SDMMC_0TO7BITS                     ((uint32_t)0x000000FFU)

+#define SDMMC_8TO15BITS                    ((uint32_t)0x0000FF00U)

+#define SDMMC_16TO23BITS                   ((uint32_t)0x00FF0000U)

+#define SDMMC_24TO31BITS                   ((uint32_t)0xFF000000U)

+#define SDMMC_MAX_DATA_LENGTH              ((uint32_t)0x01FFFFFFU)

+

+#define SDMMC_HALFFIFO                     ((uint32_t)0x00000008U)

+#define SDMMC_HALFFIFOBYTES                ((uint32_t)0x00000020U)

+

+/**

+  * @brief  Command Class supported

+  */

+#define SDMMC_CCCC_ERASE                   ((uint32_t)0x00000020U)

+

+#define SDMMC_CMDTIMEOUT                   ((uint32_t)5000U)        /* Command send and response timeout     */

+#define SDMMC_MAXERASETIMEOUT              ((uint32_t)63000U)       /* Max erase Timeout 63 s                */

+#define SDMMC_STOPTRANSFERTIMEOUT          ((uint32_t)100000000U)   /* Timeout for STOP TRANSMISSION command */

+

+/** @defgroup SDMMC_LL_Clock_Edge Clock Edge

+  * @{

+  */

+#define SDMMC_CLOCK_EDGE_RISING               ((uint32_t)0x00000000U)

+#define SDMMC_CLOCK_EDGE_FALLING              SDMMC_CLKCR_NEGEDGE

+

+#define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \

+                                   ((EDGE) == SDMMC_CLOCK_EDGE_FALLING))

+/**

+  * @}

+  */

+

+/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving

+  * @{

+  */

+#define SDMMC_CLOCK_POWER_SAVE_DISABLE         ((uint32_t)0x00000000U)

+#define SDMMC_CLOCK_POWER_SAVE_ENABLE          SDMMC_CLKCR_PWRSAV

+

+#define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \

+                                         ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))

+/**

+  * @}

+  */

+

+/** @defgroup SDMMC_LL_Bus_Wide Bus Width

+  * @{

+  */

+#define SDMMC_BUS_WIDE_1B                      ((uint32_t)0x00000000U)

+#define SDMMC_BUS_WIDE_4B                      SDMMC_CLKCR_WIDBUS_0

+#define SDMMC_BUS_WIDE_8B                      SDMMC_CLKCR_WIDBUS_1

+

+#define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \

+                                 ((WIDE) == SDMMC_BUS_WIDE_4B) || \

+                                 ((WIDE) == SDMMC_BUS_WIDE_8B))

+/**

+  * @}

+  */

+

+/** @defgroup SDMMC_LL_Speed_Mode

+  * @{

+  */

+#define SDMMC_SPEED_MODE_AUTO                  ((uint32_t)0x00000000U)

+#define SDMMC_SPEED_MODE_DEFAULT               ((uint32_t)0x00000001U)

+#define SDMMC_SPEED_MODE_HIGH                  ((uint32_t)0x00000002U)

+#define SDMMC_SPEED_MODE_ULTRA                 ((uint32_t)0x00000003U)

+#define SDMMC_SPEED_MODE_DDR                   ((uint32_t)0x00000004U)

+

+#define IS_SDMMC_SPEED_MODE(MODE) (((MODE) == SDMMC_SPEED_MODE_AUTO) || \

+                                ((MODE) == SDMMC_SPEED_MODE_DEFAULT) || \

+                                ((MODE) == SDMMC_SPEED_MODE_HIGH) || \

+                                ((MODE) == SDMMC_SPEED_MODE_ULTRA) || \

+                                ((MODE) == SDMMC_SPEED_MODE_DDR))

+

+/**

+  * @}

+  */

+

+/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control

+  * @{

+  */

+#define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE    ((uint32_t)0x00000000U)

+#define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE     SDMMC_CLKCR_HWFC_EN

+

+#define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \

+                                                 ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))

+/**

+  * @}

+  */

+

+/** @defgroup SDMMC_LL_Clock_Division Clock Division

+  * @{

+  */

+/* SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV] */

+#define IS_SDMMC_CLKDIV(DIV)   ((DIV) < 0x400U)

+/**

+  * @}

+  */

+

+/** @defgroup SDMMC_LL_TRANSCEIVER_PRESENT Tranceiver Present

+  * @{

+  */

+#define SDMMC_TRANSCEIVER_UNKNOWN             ((uint32_t)0x00000000U)

+#define SDMMC_TRANSCEIVER_NOT_PRESENT         ((uint32_t)0x00000001U)

+#define SDMMC_TRANSCEIVER_PRESENT             ((uint32_t)0x00000002U)

+

+/**

+  * @}

+  */

+

+/** @defgroup SDMMC_LL_Command_Index Command Index

+  * @{

+  */

+#define IS_SDMMC_CMD_INDEX(INDEX)            ((INDEX) < 0x40U)

+/**

+  * @}

+  */

+

+/** @defgroup SDMMC_LL_Response_Type Response Type

+  * @{

+  */

+#define SDMMC_RESPONSE_NO                    ((uint32_t)0x00000000U)

+#define SDMMC_RESPONSE_SHORT                 SDMMC_CMD_WAITRESP_0

+#define SDMMC_RESPONSE_LONG                  SDMMC_CMD_WAITRESP

+

+#define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO)    || \

+                                     ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \

+                                     ((RESPONSE) == SDMMC_RESPONSE_LONG))

+/**

+  * @}

+  */

+

+/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt

+  * @{

+  */

+#define SDMMC_WAIT_NO                        ((uint32_t)0x00000000U)

+#define SDMMC_WAIT_IT                        SDMMC_CMD_WAITINT

+#define SDMMC_WAIT_PEND                      SDMMC_CMD_WAITPEND

+

+#define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \

+                             ((WAIT) == SDMMC_WAIT_IT) || \

+                             ((WAIT) == SDMMC_WAIT_PEND))

+/**

+  * @}

+  */

+

+/** @defgroup SDMMC_LL_CPSM_State CPSM State

+  * @{

+  */

+#define SDMMC_CPSM_DISABLE                   ((uint32_t)0x00000000U)

+#define SDMMC_CPSM_ENABLE                    SDMMC_CMD_CPSMEN

+

+#define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \

+                             ((CPSM) == SDMMC_CPSM_ENABLE))

+/**

+  * @}

+  */

+

+/** @defgroup SDMMC_LL_Response_Registers Response Register

+  * @{

+  */

+#define SDMMC_RESP1                          ((uint32_t)0x00000000U)

+#define SDMMC_RESP2                          ((uint32_t)0x00000004U)

+#define SDMMC_RESP3                          ((uint32_t)0x00000008U)

+#define SDMMC_RESP4                          ((uint32_t)0x0000000CU)

+

+#define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \

+                             ((RESP) == SDMMC_RESP2) || \

+                             ((RESP) == SDMMC_RESP3) || \

+                             ((RESP) == SDMMC_RESP4))

+

+/** @defgroup SDMMC_Internal_DMA_Mode  SDMMC Internal DMA Mode

+  * @{

+  */

+#define SDMMC_DISABLE_IDMA              ((uint32_t)0x00000000)

+#define SDMMC_ENABLE_IDMA_SINGLE_BUFF   (SDMMC_IDMA_IDMAEN)

+#define SDMMC_ENABLE_IDMA_DOUBLE_BUFF0  (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE)

+#define SDMMC_ENABLE_IDMA_DOUBLE_BUFF1  (SDMMC_IDMA_IDMAEN | SDMMC_IDMA_IDMABMODE | SDMMC_IDMA_IDMABACT)

+

+/**

+  * @}

+  */

+

+/** @defgroup SDMMC_LL_Data_Length Data Lenght

+  * @{

+  */

+#define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFFU)

+/**

+  * @}

+  */

+

+/** @defgroup SDMMC_LL_Data_Block_Size  Data Block Size

+  * @{

+  */

+#define SDMMC_DATABLOCK_SIZE_1B               ((uint32_t)0x00000000U)

+#define SDMMC_DATABLOCK_SIZE_2B               SDMMC_DCTRL_DBLOCKSIZE_0

+#define SDMMC_DATABLOCK_SIZE_4B               SDMMC_DCTRL_DBLOCKSIZE_1

+#define SDMMC_DATABLOCK_SIZE_8B               (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1)

+#define SDMMC_DATABLOCK_SIZE_16B              SDMMC_DCTRL_DBLOCKSIZE_2

+#define SDMMC_DATABLOCK_SIZE_32B              (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2)

+#define SDMMC_DATABLOCK_SIZE_64B              (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)

+#define SDMMC_DATABLOCK_SIZE_128B             (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)

+#define SDMMC_DATABLOCK_SIZE_256B             SDMMC_DCTRL_DBLOCKSIZE_3

+#define SDMMC_DATABLOCK_SIZE_512B             (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3)

+#define SDMMC_DATABLOCK_SIZE_1024B            (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)

+#define SDMMC_DATABLOCK_SIZE_2048B            (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)

+#define SDMMC_DATABLOCK_SIZE_4096B            (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)

+#define SDMMC_DATABLOCK_SIZE_8192B            (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)

+#define SDMMC_DATABLOCK_SIZE_16384B           (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)

+

+#define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B)    || \

+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_2B)    || \

+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_4B)    || \

+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_8B)    || \

+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_16B)   || \

+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_32B)   || \

+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_64B)   || \

+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_128B)  || \

+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_256B)  || \

+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_512B)  || \

+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \

+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \

+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \

+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \

+                                   ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))

+/**

+  * @}

+  */

+

+/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction

+  * @{

+  */

+#define SDMMC_TRANSFER_DIR_TO_CARD            ((uint32_t)0x00000000U)

+#define SDMMC_TRANSFER_DIR_TO_SDMMC            SDMMC_DCTRL_DTDIR

+

+#define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \

+                                    ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))

+/**

+  * @}

+  */

+

+/** @defgroup SDMMC_LL_Transfer_Type Transfer Type

+  * @{

+  */

+#define SDMMC_TRANSFER_MODE_BLOCK             ((uint32_t)0x00000000U)

+#define SDMMC_TRANSFER_MODE_STREAM            SDMMC_DCTRL_DTMODE_1

+

+#define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \

+                                      ((MODE) == SDMMC_TRANSFER_MODE_STREAM))

+/**

+  * @}

+  */

+

+/** @defgroup SDMMC_LL_DPSM_State DPSM State

+  * @{

+  */

+#define SDMMC_DPSM_DISABLE                    ((uint32_t)0x00000000U)

+#define SDMMC_DPSM_ENABLE                     SDMMC_DCTRL_DTEN

+

+#define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\

+                             ((DPSM) == SDMMC_DPSM_ENABLE))

+/**

+  * @}

+  */

+

+/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode

+  * @{

+  */

+#define SDMMC_READ_WAIT_MODE_DATA2                ((uint32_t)0x00000000U)

+#define SDMMC_READ_WAIT_MODE_CLK                  (SDMMC_DCTRL_RWMOD)

+

+#define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \

+                                      ((MODE) == SDMMC_READ_WAIT_MODE_DATA2))

+/**

+  * @}

+  */

+

+/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources

+  * @{

+  */

+#define SDMMC_IT_CCRCFAIL                  SDMMC_MASK_CCRCFAILIE

+#define SDMMC_IT_DCRCFAIL                  SDMMC_MASK_DCRCFAILIE

+#define SDMMC_IT_CTIMEOUT                  SDMMC_MASK_CTIMEOUTIE

+#define SDMMC_IT_DTIMEOUT                  SDMMC_MASK_DTIMEOUTIE

+#define SDMMC_IT_TXUNDERR                  SDMMC_MASK_TXUNDERRIE

+#define SDMMC_IT_RXOVERR                   SDMMC_MASK_RXOVERRIE

+#define SDMMC_IT_CMDREND                   SDMMC_MASK_CMDRENDIE

+#define SDMMC_IT_CMDSENT                   SDMMC_MASK_CMDSENTIE

+#define SDMMC_IT_DATAEND                   SDMMC_MASK_DATAENDIE

+#define SDMMC_IT_DHOLD                     SDMMC_MASK_DHOLDIE

+#define SDMMC_IT_DBCKEND                   SDMMC_MASK_DBCKENDIE

+#define SDMMC_IT_DABORT                    SDMMC_MASK_DABORTIE

+#define SDMMC_IT_TXFIFOHE                  SDMMC_MASK_TXFIFOHEIE

+#define SDMMC_IT_RXFIFOHF                  SDMMC_MASK_RXFIFOHFIE

+#define SDMMC_IT_RXFIFOF                   SDMMC_MASK_RXFIFOFIE

+#define SDMMC_IT_TXFIFOE                   SDMMC_MASK_TXFIFOEIE

+#define SDMMC_IT_BUSYD0END                 SDMMC_MASK_BUSYD0ENDIE

+#define SDMMC_IT_SDIOIT                    SDMMC_MASK_SDIOITIE

+#define SDMMC_IT_ACKFAIL                   SDMMC_MASK_ACKFAILIE

+#define SDMMC_IT_ACKTIMEOUT                SDMMC_MASK_ACKTIMEOUTIE

+#define SDMMC_IT_VSWEND                    SDMMC_MASK_VSWENDIE

+#define SDMMC_IT_CKSTOP                    SDMMC_MASK_CKSTOPIE

+#define SDMMC_IT_IDMABTC                   SDMMC_MASK_IDMABTCIE

+/**

+  * @}

+  */

+

+/** @defgroup SDMMC_LL_Flags Flags

+  * @{

+  */

+#define SDMMC_FLAG_CCRCFAIL                  SDMMC_STA_CCRCFAIL

+#define SDMMC_FLAG_DCRCFAIL                  SDMMC_STA_DCRCFAIL

+#define SDMMC_FLAG_CTIMEOUT                  SDMMC_STA_CTIMEOUT

+#define SDMMC_FLAG_DTIMEOUT                  SDMMC_STA_DTIMEOUT

+#define SDMMC_FLAG_TXUNDERR                  SDMMC_STA_TXUNDERR

+#define SDMMC_FLAG_RXOVERR                   SDMMC_STA_RXOVERR

+#define SDMMC_FLAG_CMDREND                   SDMMC_STA_CMDREND

+#define SDMMC_FLAG_CMDSENT                   SDMMC_STA_CMDSENT

+#define SDMMC_FLAG_DATAEND                   SDMMC_STA_DATAEND

+#define SDMMC_FLAG_DHOLD                     SDMMC_STA_DHOLD

+#define SDMMC_FLAG_DBCKEND                   SDMMC_STA_DBCKEND

+#define SDMMC_FLAG_DABORT                    SDMMC_STA_DABORT

+#define SDMMC_FLAG_DPSMACT                   SDMMC_STA_DPSMACT

+#define SDMMC_FLAG_CMDACT                    SDMMC_STA_CPSMACT

+#define SDMMC_FLAG_TXFIFOHE                  SDMMC_STA_TXFIFOHE

+#define SDMMC_FLAG_RXFIFOHF                  SDMMC_STA_RXFIFOHF

+#define SDMMC_FLAG_TXFIFOF                   SDMMC_STA_TXFIFOF

+#define SDMMC_FLAG_RXFIFOF                   SDMMC_STA_RXFIFOF

+#define SDMMC_FLAG_TXFIFOE                   SDMMC_STA_TXFIFOE

+#define SDMMC_FLAG_RXFIFOE                   SDMMC_STA_RXFIFOE

+#define SDMMC_FLAG_BUSYD0                    SDMMC_STA_BUSYD0

+#define SDMMC_FLAG_BUSYD0END                 SDMMC_STA_BUSYD0END

+#define SDMMC_FLAG_SDIOIT                    SDMMC_STA_SDIOIT

+#define SDMMC_FLAG_ACKFAIL                   SDMMC_STA_ACKFAIL

+#define SDMMC_FLAG_ACKTIMEOUT                SDMMC_STA_ACKTIMEOUT

+#define SDMMC_FLAG_VSWEND                    SDMMC_STA_VSWEND

+#define SDMMC_FLAG_CKSTOP                    SDMMC_STA_CKSTOP

+#define SDMMC_FLAG_IDMATE                    SDMMC_STA_IDMATE

+#define SDMMC_FLAG_IDMABTC                   SDMMC_STA_IDMABTC

+

+#define SDMMC_STATIC_FLAGS                   ((uint32_t)(SDMMC_FLAG_CCRCFAIL   | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\

+                                                         SDMMC_FLAG_DTIMEOUT   | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR  |\

+                                                         SDMMC_FLAG_CMDREND    | SDMMC_FLAG_CMDSENT  | SDMMC_FLAG_DATAEND  |\

+                                                         SDMMC_FLAG_DHOLD      | SDMMC_FLAG_DBCKEND  | SDMMC_FLAG_DABORT   |\

+                                                         SDMMC_FLAG_BUSYD0END  | SDMMC_FLAG_SDIOIT   | SDMMC_FLAG_ACKFAIL  |\

+                                                         SDMMC_FLAG_ACKTIMEOUT | SDMMC_FLAG_VSWEND   | SDMMC_FLAG_CKSTOP   |\

+                                                         SDMMC_FLAG_IDMATE     | SDMMC_FLAG_IDMABTC))

+

+#define SDMMC_STATIC_CMD_FLAGS               ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CTIMEOUT  | SDMMC_FLAG_CMDREND |\

+                                                         SDMMC_FLAG_CMDSENT  | SDMMC_FLAG_BUSYD0END))

+

+#define SDMMC_STATIC_DATA_FLAGS              ((uint32_t)(SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR |\

+                                                         SDMMC_FLAG_RXOVERR  | SDMMC_FLAG_DATAEND  | SDMMC_FLAG_DHOLD    |\

+                                                         SDMMC_FLAG_DBCKEND  | SDMMC_FLAG_DABORT   | SDMMC_FLAG_IDMATE   |\

+                                                         SDMMC_FLAG_IDMABTC))

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros

+  * @{

+  */

+

+/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions

+  * @brief SDMMC_LL registers bit address in the alias region

+  * @{

+  */

+/* ---------------------- SDMMC registers bit mask --------------------------- */

+/* --- CLKCR Register ---*/

+/* CLKCR register clear mask */

+#define CLKCR_CLEAR_MASK         ((uint32_t)(SDMMC_CLKCR_CLKDIV  | SDMMC_CLKCR_PWRSAV |\

+                                             SDMMC_CLKCR_WIDBUS |\

+                                             SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN |\

+                                             SDMMC_CLKCR_DDR | SDMMC_CLKCR_BUSSPEED |\

+                                             SDMMC_CLKCR_SELCLKRX))

+

+/* --- DCTRL Register ---*/

+/* SDMMC DCTRL Clear Mask */

+#define DCTRL_CLEAR_MASK         ((uint32_t)(SDMMC_DCTRL_DTEN    | SDMMC_DCTRL_DTDIR |\

+                                             SDMMC_DCTRL_DTMODE  | SDMMC_DCTRL_DBLOCKSIZE))

+

+/* --- CMD Register ---*/

+/* CMD Register clear mask */

+#define CMD_CLEAR_MASK           ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\

+                                             SDMMC_CMD_WAITINT  | SDMMC_CMD_WAITPEND |\

+                                             SDMMC_CMD_CPSMEN   | SDMMC_CMD_CMDSUSPEND))

+

+/* SDMMC Initialization Frequency (400KHz max) for Peripheral CLK 200MHz*/

+#define SDMMC_INIT_CLK_DIV ((uint8_t)0xFA)

+

+/* SDMMC Default Speed Frequency (25Mhz max) for Peripheral CLK 200MHz*/

+#define SDMMC_NSpeed_CLK_DIV ((uint8_t)0x4)

+

+/* SDMMC High Speed Frequency (50Mhz max) for Peripheral CLK 200MHz*/

+#define SDMMC_HSpeed_CLK_DIV ((uint8_t)0x2)

+/**

+  * @}

+  */

+

+/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration

+ *  @brief macros to handle interrupts and specific clock configurations

+ * @{

+ */

+

+/**

+  * @brief  Enable the SDMMC device interrupt.

+  * @param  __INSTANCE__ Pointer to SDMMC register base

+  * @param  __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled.

+  *         This parameter can be one or a combination of the following values:

+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt

+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt

+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt

+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt

+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt

+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt

+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt

+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt

+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt

+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt

+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt

+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt

+  *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt

+  *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt

+  *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt

+  *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt

+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt

+  *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt

+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt

+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt

+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt

+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt

+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt

+  * @retval None

+  */

+#define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK |= (__INTERRUPT__))

+

+/**

+  * @brief  Disable the SDMMC device interrupt.

+  * @param  __INSTANCE__ Pointer to SDMMC register base

+  * @param  __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled.

+  *          This parameter can be one or a combination of the following values:

+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt

+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt

+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt

+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt

+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt

+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt

+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt

+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt

+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt

+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt

+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt

+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt

+  *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt

+  *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt

+  *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt

+  *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt

+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt

+  *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt

+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt

+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt

+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt

+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt

+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt

+  * @retval None

+  */

+#define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))

+

+/**

+  * @brief  Checks whether the specified SDMMC flag is set or not.

+  * @param  __INSTANCE__ Pointer to SDMMC register base

+  * @param  __FLAG__ specifies the flag to check.

+  *          This parameter can be one of the following values:

+  *            @arg SDMMC_FLAG_CCRCFAIL:   Command response received (CRC check failed)

+  *            @arg SDMMC_FLAG_DCRCFAIL:   Data block sent/received (CRC check failed)

+  *            @arg SDMMC_FLAG_CTIMEOUT:   Command response timeout

+  *            @arg SDMMC_FLAG_DTIMEOUT:   Data timeout

+  *            @arg SDMMC_FLAG_TXUNDERR:   Transmit FIFO underrun error

+  *            @arg SDMMC_FLAG_RXOVERR:    Received FIFO overrun error

+  *            @arg SDMMC_FLAG_CMDREND:    Command response received (CRC check passed)

+  *            @arg SDMMC_FLAG_CMDSENT:    Command sent (no response required)

+  *            @arg SDMMC_FLAG_DATAEND:    Data end (data counter, DATACOUNT, is zero)

+  *            @arg SDMMC_FLAG_DHOLD:      Data transfer Hold

+  *            @arg SDMMC_FLAG_DBCKEND:    Data block sent/received (CRC check passed)

+  *            @arg SDMMC_FLAG_DABORT:     Data transfer aborted by CMD12

+  *            @arg SDMMC_FLAG_DPSMACT:    Data path state machine active

+  *            @arg SDMMC_FLAG_CPSMACT:    Command path state machine active

+  *            @arg SDMMC_FLAG_TXFIFOHE:   Transmit FIFO Half Empty

+  *            @arg SDMMC_FLAG_RXFIFOHF:   Receive FIFO Half Full

+  *            @arg SDMMC_FLAG_TXFIFOF:    Transmit FIFO full

+  *            @arg SDMMC_FLAG_RXFIFOF:    Receive FIFO full

+  *            @arg SDMMC_FLAG_TXFIFOE:    Transmit FIFO empty

+  *            @arg SDMMC_FLAG_RXFIFOE:    Receive FIFO empty

+  *            @arg SDMMC_FLAG_BUSYD0:     Inverted value of SDMMC_D0 line (Busy)

+  *            @arg SDMMC_FLAG_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected

+  *            @arg SDMMC_FLAG_SDIOIT:     SDIO interrupt received

+  *            @arg SDMMC_FLAG_ACKFAIL:    Boot Acknowledgment received

+  *            @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout

+  *            @arg SDMMC_FLAG_VSWEND:     Voltage switch critical timing section completion

+  *            @arg SDMMC_FLAG_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure

+  *            @arg SDMMC_FLAG_IDMATE:     IDMA transfer error

+  *            @arg SDMMC_FLAG_IDMABTC:    IDMA buffer transfer complete

+  * @retval The new state of SDMMC_FLAG (SET or RESET).

+  */

+#define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__)  (((__INSTANCE__)->STA &(__FLAG__)) != 0U)

+

+

+/**

+  * @brief  Clears the SDMMC pending flags.

+  * @param  __INSTANCE__ Pointer to SDMMC register base

+  * @param  __FLAG__ specifies the flag to clear.

+  *          This parameter can be one or a combination of the following values:

+  *            @arg SDMMC_FLAG_CCRCFAIL:   Command response received (CRC check failed)

+  *            @arg SDMMC_FLAG_DCRCFAIL:   Data block sent/received (CRC check failed)

+  *            @arg SDMMC_FLAG_CTIMEOUT:   Command response timeout

+  *            @arg SDMMC_FLAG_DTIMEOUT:   Data timeout

+  *            @arg SDMMC_FLAG_TXUNDERR:   Transmit FIFO underrun error

+  *            @arg SDMMC_FLAG_RXOVERR:    Received FIFO overrun error

+  *            @arg SDMMC_FLAG_CMDREND:    Command response received (CRC check passed)

+  *            @arg SDMMC_FLAG_CMDSENT:    Command sent (no response required)

+  *            @arg SDMMC_FLAG_DATAEND:    Data end (data counter, DATACOUNT, is zero)

+  *            @arg SDMMC_FLAG_DHOLD:      Data transfer Hold

+  *            @arg SDMMC_FLAG_DBCKEND:    Data block sent/received (CRC check passed)

+  *            @arg SDMMC_FLAG_DABORT:     Data transfer aborted by CMD12

+  *            @arg SDMMC_FLAG_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected

+  *            @arg SDMMC_FLAG_SDIOIT:     SDIO interrupt received

+  *            @arg SDMMC_FLAG_ACKFAIL:    Boot Acknowledgment received

+  *            @arg SDMMC_FLAG_ACKTIMEOUT: Boot Acknowledgment timeout

+  *            @arg SDMMC_FLAG_VSWEND:     Voltage switch critical timing section completion

+  *            @arg SDMMC_FLAG_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure

+  *            @arg SDMMC_FLAG_IDMATE:     IDMA transfer error

+  *            @arg SDMMC_FLAG_IDMABTC:    IDMA buffer transfer complete

+  * @retval None

+  */

+#define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__)  ((__INSTANCE__)->ICR = (__FLAG__))

+

+/**

+  * @brief  Checks whether the specified SDMMC interrupt has occurred or not.

+  * @param  __INSTANCE__ Pointer to SDMMC register base

+  * @param  __INTERRUPT__ specifies the SDMMC interrupt source to check.

+  *          This parameter can be one of the following values:

+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt

+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt

+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt

+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt

+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt

+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt

+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt

+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt

+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt

+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt

+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt

+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt

+  *            @arg SDMMC_IT_TXFIFOHE:   Transmit FIFO Half Empty interrupt

+  *            @arg SDMMC_IT_RXFIFOHF:   Receive FIFO Half Full interrupt

+  *            @arg SDMMC_IT_RXFIFOF:    Receive FIFO full interrupt

+  *            @arg SDMMC_IT_TXFIFOE:    Transmit FIFO empty interrupt

+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt

+  *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt

+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt

+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt

+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt

+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt

+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt

+  * @retval The new state of SDMMC_IT (SET or RESET).

+  */

+#define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__)  (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))

+

+/**

+  * @brief  Clears the SDMMC's interrupt pending bits.

+  * @param  __INSTANCE__ Pointer to SDMMC register base

+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.

+  *          This parameter can be one or a combination of the following values:

+  *            @arg SDMMC_IT_CCRCFAIL:   Command response received (CRC check failed) interrupt

+  *            @arg SDMMC_IT_DCRCFAIL:   Data block sent/received (CRC check failed) interrupt

+  *            @arg SDMMC_IT_CTIMEOUT:   Command response timeout interrupt

+  *            @arg SDMMC_IT_DTIMEOUT:   Data timeout interrupt

+  *            @arg SDMMC_IT_TXUNDERR:   Transmit FIFO underrun error interrupt

+  *            @arg SDMMC_IT_RXOVERR:    Received FIFO overrun error interrupt

+  *            @arg SDMMC_IT_CMDREND:    Command response received (CRC check passed) interrupt

+  *            @arg SDMMC_IT_CMDSENT:    Command sent (no response required) interrupt

+  *            @arg SDMMC_IT_DATAEND:    Data end (data counter, DATACOUNT, is zero) interrupt

+  *            @arg SDMMC_IT_DHOLD:      Data transfer Hold interrupt

+  *            @arg SDMMC_IT_DBCKEND:    Data block sent/received (CRC check passed) interrupt

+  *            @arg SDMMC_IT_DABORT:     Data transfer aborted by CMD12 interrupt

+  *            @arg SDMMC_IT_BUSYD0END:  End of SDMMC_D0 Busy following a CMD response detected interrupt

+  *            @arg SDMMC_IT_SDIOIT:     SDIO interrupt received interrupt

+  *            @arg SDMMC_IT_ACKFAIL:    Boot Acknowledgment received interrupt

+  *            @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt

+  *            @arg SDMMC_IT_VSWEND:     Voltage switch critical timing section completion interrupt

+  *            @arg SDMMC_IT_CKSTOP:     SDMMC_CK stopped in Voltage switch procedure interrupt

+  *            @arg SDMMC_IT_IDMABTC:    IDMA buffer transfer complete interrupt

+  * @retval None

+  */

+#define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->ICR = (__INTERRUPT__))

+

+/**

+  * @brief  Enable Start the SD I/O Read Wait operation.

+  * @param  __INSTANCE__ Pointer to SDMMC register base

+  * @retval None

+  */

+#define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART)

+

+/**

+  * @brief  Disable Start the SD I/O Read Wait operations.

+  * @param  __INSTANCE__ Pointer to SDMMC register base

+  * @retval None

+  */

+#define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)

+

+/**

+  * @brief  Enable Start the SD I/O Read Wait operation.

+  * @param  __INSTANCE__ Pointer to SDMMC register base

+  * @retval None

+  */

+#define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP)

+

+/**

+  * @brief  Disable Stop the SD I/O Read Wait operations.

+  * @param  __INSTANCE__ Pointer to SDMMC register base

+  * @retval None

+  */

+#define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)

+

+/**

+  * @brief  Enable the SD I/O Mode Operation.

+  * @param  __INSTANCE__ Pointer to SDMMC register base

+  * @retval None

+  */

+#define __SDMMC_OPERATION_ENABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN)

+

+/**

+  * @brief  Disable the SD I/O Mode Operation.

+  * @param  __INSTANCE__ Pointer to SDMMC register base

+  * @retval None

+  */

+#define __SDMMC_OPERATION_DISABLE(__INSTANCE__)  ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN)

+

+/**

+  * @brief  Enable the SD I/O Suspend command sending.

+  * @param  __INSTANCE__ Pointer to SDMMC register base

+  * @retval None

+  */

+#define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSUSPEND)

+

+/**

+  * @brief  Disable the SD I/O Suspend command sending.

+  * @param  __INSTANCE__ Pointer to SDMMC register base

+  * @retval None

+  */

+#define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSUSPEND)

+

+/**

+  * @brief  Enable the CMDTRANS mode.

+  * @param  __INSTANCE__ Pointer to SDMMC register base

+  * @retval None

+  */

+#define __SDMMC_CMDTRANS_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDTRANS)

+

+/**

+  * @brief  Disable the CMDTRANS mode.

+  * @param  __INSTANCE__ Pointer to SDMMC register base

+  * @retval None

+  */

+#define __SDMMC_CMDTRANS_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDTRANS)

+

+/**

+  * @brief  Enable the CMDSTOP mode.

+  * @param  __INSTANCE__ Pointer to SDMMC register base

+  * @retval None

+  */

+#define __SDMMC_CMDSTOP_ENABLE(__INSTANCE__)  ((__INSTANCE__)->CMD |= SDMMC_CMD_CMDSTOP)

+

+/**

+  * @brief  Disable the CMDSTOP mode.

+  * @param  __INSTANCE__ Pointer to SDMMC register base

+  * @retval None

+  */

+#define __SDMMC_CMDSTOP_DISABLE(__INSTANCE__)  ((__INSTANCE__)->CMD &= ~SDMMC_CMD_CMDSTOP)

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup SDMMC_LL_Exported_Functions

+  * @{

+  */

+

+/* Initialization/de-initialization functions  **********************************/

+/** @addtogroup HAL_SDMMC_LL_Group1

+  * @{

+  */

+HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);

+/**

+  * @}

+  */

+

+/* I/O operation functions  *****************************************************/

+/** @addtogroup HAL_SDMMC_LL_Group2

+  * @{

+  */

+uint32_t          SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);

+HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData);

+/**

+  * @}

+  */

+

+/* Peripheral Control functions  ************************************************/

+/** @addtogroup HAL_SDMMC_LL_Group3

+  * @{

+  */

+HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);

+HAL_StatusTypeDef SDMMC_PowerState_Cycle(SDMMC_TypeDef *SDMMCx);

+HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);

+uint32_t          SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);

+

+/* Command path state machine (CPSM) management functions */

+HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command);

+uint8_t           SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);

+uint32_t          SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);

+

+/* Data path state machine (DPSM) management functions */

+HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data);

+uint32_t          SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);

+uint32_t          SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);

+

+/* SDMMC Cards mode management functions */

+HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);

+

+/* SDMMC Commands management functions */

+uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize);

+uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);

+uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);

+uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);

+uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);

+uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);

+uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);

+uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);

+uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);

+uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx);

+uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx);

+uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr);

+uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx);

+uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx);

+uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);

+uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);

+uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth);

+uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx);

+uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx);

+uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);

+uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA);

+uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument);

+uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx);

+uint32_t SDMMC_CmdVoltageSwitch(SDMMC_TypeDef *SDMMCx);

+uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument);

+uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument);

+uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+  /**

+  * @}

+  */

+

+/**

+  * @}

+  */

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_LL_SDMMC_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_spi.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_spi.h
new file mode 100644
index 0000000000..7fe9133279
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_spi.h
@@ -0,0 +1,3712 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_spi.h

+  * @author  MCD Application Team

+  * @brief   Header file of SPI LL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_LL_SPI_H

+#define STM32H7xx_LL_SPI_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+#if defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6)

+

+/** @defgroup SPI_LL SPI

+  * @{

+  */

+

+/* Private variables ---------------------------------------------------------*/

+

+/* Private constants ---------------------------------------------------------*/

+

+/* Private macros ------------------------------------------------------------*/

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup SPI_LL_Private_Macros SPI Private Macros

+  * @{

+  */

+

+/**

+  * @brief  SPI Init structures definition

+  */

+typedef struct

+{

+  uint32_t TransferDirection;       /*!< Specifies the SPI unidirectional or bidirectional data mode.

+                                         This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE.

+

+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/

+

+  uint32_t Mode;                    /*!< Specifies the SPI mode (Master/Slave).

+                                         This parameter can be a value of @ref SPI_LL_EC_MODE.

+

+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/

+

+  uint32_t DataWidth;               /*!< Specifies the SPI data width.

+                                         This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH.

+

+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/

+

+  uint32_t ClockPolarity;           /*!< Specifies the serial clock steady state.

+                                         This parameter can be a value of @ref SPI_LL_EC_POLARITY.

+

+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/

+

+  uint32_t ClockPhase;              /*!< Specifies the clock active edge for the bit capture.

+                                         This parameter can be a value of @ref SPI_LL_EC_PHASE.

+

+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/

+

+  uint32_t NSS;                     /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit.

+                                         This parameter can be a value of @ref SPI_LL_EC_NSS_MODE.

+

+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/

+

+  uint32_t BaudRate;                /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock.

+                                         This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER.

+                                         @note The communication clock is derived from the master clock. The slave clock does not need to be set.

+

+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/

+

+  uint32_t BitOrder;                /*!< Specifies whether data transfers start from MSB or LSB bit.

+                                         This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER.

+

+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/

+

+  uint32_t CRCCalculation;          /*!< Specifies if the CRC calculation is enabled or not.

+                                         This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION.

+

+                                         This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/

+

+  uint32_t CRCPoly;                 /*!< Specifies the polynomial used for the CRC calculation.

+                                         This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFFFFFF.

+

+                                         This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/

+

+} LL_SPI_InitTypeDef;

+

+/**

+  * @}

+  */

+#endif /*USE_FULL_LL_DRIVER*/

+

+/* Exported types ------------------------------------------------------------*/

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants

+  * @{

+  */

+

+/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines

+  * @brief    Flags defines which can be used with LL_SPI_ReadReg function

+  * @{

+  */

+#define LL_SPI_SR_RXP                              (SPI_SR_RXP)

+#define LL_SPI_SR_TXP                              (SPI_SR_TXP)

+#define LL_SPI_SR_DXP                              (SPI_SR_DXP)

+#define LL_SPI_SR_EOT                              (SPI_SR_EOT)

+#define LL_SPI_SR_TXTF                             (SPI_SR_TXTF)

+#define LL_SPI_SR_UDR                              (SPI_SR_UDR)

+#define LL_SPI_SR_CRCE                             (SPI_SR_CRCE)

+#define LL_SPI_SR_MODF                             (SPI_SR_MODF)

+#define LL_SPI_SR_OVR                              (SPI_SR_OVR)

+#define LL_SPI_SR_TIFRE                            (SPI_SR_TIFRE)

+#define LL_SPI_SR_TSERF                            (SPI_SR_TSERF)

+#define LL_SPI_SR_SUSP                             (SPI_SR_SUSP)

+#define LL_SPI_SR_TXC                              (SPI_SR_TXC)

+#define LL_SPI_SR_RXWNE                            (SPI_SR_RXWNE)

+/**

+  * @}

+  */

+

+/** @defgroup SPI_LL_EC_IT IT Defines

+  * @brief    IT defines which can be used with LL_SPI_ReadReg and  LL_SPI_WriteReg functions

+  * @{

+  */

+#define LL_SPI_IER_RXPIE                           (SPI_IER_RXPIE)

+#define LL_SPI_IER_TXPIE                           (SPI_IER_TXPIE)

+#define LL_SPI_IER_DXPIE                           (SPI_IER_DXPIE)

+#define LL_SPI_IER_EOTIE                           (SPI_IER_EOTIE)

+#define LL_SPI_IER_TXTFIE                          (SPI_IER_TXTFIE)

+#define LL_SPI_IER_UDRIE                           (SPI_IER_UDRIE)

+#define LL_SPI_IER_OVRIE                           (SPI_IER_OVRIE)

+#define LL_SPI_IER_CRCEIE                          (SPI_IER_CRCEIE)

+#define LL_SPI_IER_TIFREIE                         (SPI_IER_TIFREIE)

+#define LL_SPI_IER_MODFIE                          (SPI_IER_MODFIE)

+#define LL_SPI_IER_TSERFIE                         (SPI_IER_TSERFIE)

+/**

+  * @}

+  */

+

+/** @defgroup SPI_LL_EC_MODE Mode

+  * @{

+  */

+#define LL_SPI_MODE_MASTER                         (SPI_CFG2_MASTER)

+#define LL_SPI_MODE_SLAVE                          (0x00000000UL)

+/**

+  * @}

+  */

+

+/** @defgroup SPI_LL_EC_SS_LEVEL SS Level

+  * @{

+  */

+#define LL_SPI_SS_LEVEL_HIGH                       (SPI_CR1_SSI)

+#define LL_SPI_SS_LEVEL_LOW                        (0x00000000UL)

+/**

+  * @}

+  */

+

+/** @defgroup SPI_LL_EC_SS_IDLENESS SS Idleness

+  * @{

+  */

+#define LL_SPI_SS_IDLENESS_00CYCLE                 (0x00000000UL)

+#define LL_SPI_SS_IDLENESS_01CYCLE                 (SPI_CFG2_MSSI_0)

+#define LL_SPI_SS_IDLENESS_02CYCLE                 (SPI_CFG2_MSSI_1)

+#define LL_SPI_SS_IDLENESS_03CYCLE                 (SPI_CFG2_MSSI_0 | SPI_CFG2_MSSI_1)

+#define LL_SPI_SS_IDLENESS_04CYCLE                 (SPI_CFG2_MSSI_2)

+#define LL_SPI_SS_IDLENESS_05CYCLE                 (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)

+#define LL_SPI_SS_IDLENESS_06CYCLE                 (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)

+#define LL_SPI_SS_IDLENESS_07CYCLE                 (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)

+#define LL_SPI_SS_IDLENESS_08CYCLE                 (SPI_CFG2_MSSI_3)

+#define LL_SPI_SS_IDLENESS_09CYCLE                 (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_0)

+#define LL_SPI_SS_IDLENESS_10CYCLE                 (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1)

+#define LL_SPI_SS_IDLENESS_11CYCLE                 (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)

+#define LL_SPI_SS_IDLENESS_12CYCLE                 (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2)

+#define LL_SPI_SS_IDLENESS_13CYCLE                 (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0)

+#define LL_SPI_SS_IDLENESS_14CYCLE                 (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1)

+#define LL_SPI_SS_IDLENESS_15CYCLE                 (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0)

+/**

+  * @}

+  */

+

+/** @defgroup SPI_LL_EC_ID_IDLENESS Master Inter-Data Idleness

+  * @{

+  */

+#define LL_SPI_ID_IDLENESS_00CYCLE                 (0x00000000UL)

+#define LL_SPI_ID_IDLENESS_01CYCLE                 (SPI_CFG2_MIDI_0)

+#define LL_SPI_ID_IDLENESS_02CYCLE                 (SPI_CFG2_MIDI_1)

+#define LL_SPI_ID_IDLENESS_03CYCLE                 (SPI_CFG2_MIDI_0 | SPI_CFG2_MIDI_1)

+#define LL_SPI_ID_IDLENESS_04CYCLE                 (SPI_CFG2_MIDI_2)

+#define LL_SPI_ID_IDLENESS_05CYCLE                 (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)

+#define LL_SPI_ID_IDLENESS_06CYCLE                 (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)

+#define LL_SPI_ID_IDLENESS_07CYCLE                 (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)

+#define LL_SPI_ID_IDLENESS_08CYCLE                 (SPI_CFG2_MIDI_3)

+#define LL_SPI_ID_IDLENESS_09CYCLE                 (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_0)

+#define LL_SPI_ID_IDLENESS_10CYCLE                 (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1)

+#define LL_SPI_ID_IDLENESS_11CYCLE                 (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)

+#define LL_SPI_ID_IDLENESS_12CYCLE                 (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2)

+#define LL_SPI_ID_IDLENESS_13CYCLE                 (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0)

+#define LL_SPI_ID_IDLENESS_14CYCLE                 (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1)

+#define LL_SPI_ID_IDLENESS_15CYCLE                 (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0)

+/**

+  * @}

+  */

+

+/** @defgroup SPI_LL_EC_TXCRCINIT_ALL TXCRC Init All

+  * @{

+  */

+#define LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN          (0x00000000UL)

+#define LL_SPI_TXCRCINIT_ALL_ONES_PATTERN          (SPI_CR1_TCRCINI)

+/**

+  * @}

+  */

+

+/** @defgroup SPI_LL_EC_RXCRCINIT_ALL RXCRC Init All

+  * @{

+  */

+#define LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN          (0x00000000UL)

+#define LL_SPI_RXCRCINIT_ALL_ONES_PATTERN          (SPI_CR1_RCRCINI)

+/**

+  * @}

+  */

+

+/** @defgroup SPI_LL_EC_UDR_CONFIG_REGISTER UDR Config Register

+  * @{

+  */

+#define LL_SPI_UDR_CONFIG_REGISTER_PATTERN         (0x00000000UL)

+#define LL_SPI_UDR_CONFIG_LAST_RECEIVED            (SPI_CFG1_UDRCFG_0)

+#define LL_SPI_UDR_CONFIG_LAST_TRANSMITTED         (SPI_CFG1_UDRCFG_1)

+/**

+  * @}

+  */

+

+/** @defgroup SPI_LL_EC_UDR_DETECT_BEGIN_DATA UDR Detect Begin Data

+  * @{

+  */

+#define LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME         (0x00000000UL)

+#define LL_SPI_UDR_DETECT_END_DATA_FRAME           (SPI_CFG1_UDRDET_0)

+#define LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS         (SPI_CFG1_UDRDET_1)

+/**

+  * @}

+  */

+

+/** @defgroup SPI_LL_EC_PROTOCOL Protocol

+  * @{

+  */

+#define LL_SPI_PROTOCOL_MOTOROLA                   (0x00000000UL)

+#define LL_SPI_PROTOCOL_TI                         (SPI_CFG2_SP_0)

+/**

+  * @}

+  */

+

+/** @defgroup SPI_LL_EC_PHASE Phase

+  * @{

+  */

+#define LL_SPI_PHASE_1EDGE                         (0x00000000UL)

+#define LL_SPI_PHASE_2EDGE                         (SPI_CFG2_CPHA)

+/**

+  * @}

+  */

+

+/** @defgroup SPI_LL_EC_POLARITY Polarity

+  * @{

+  */

+#define LL_SPI_POLARITY_LOW                        (0x00000000UL)

+#define LL_SPI_POLARITY_HIGH                       (SPI_CFG2_CPOL)

+/**

+  * @}

+  */

+

+/** @defgroup SPI_LL_EC_NSS_POLARITY NSS Polarity

+  * @{

+  */

+#define LL_SPI_NSS_POLARITY_LOW                    (0x00000000UL)

+#define LL_SPI_NSS_POLARITY_HIGH                   (SPI_CFG2_SSIOP)

+/**

+  * @}

+  */

+

+/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler

+  * @{

+  */

+#define LL_SPI_BAUDRATEPRESCALER_DIV2              (0x00000000UL)

+#define LL_SPI_BAUDRATEPRESCALER_DIV4              (SPI_CFG1_MBR_0)

+#define LL_SPI_BAUDRATEPRESCALER_DIV8              (SPI_CFG1_MBR_1)

+#define LL_SPI_BAUDRATEPRESCALER_DIV16             (SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)

+#define LL_SPI_BAUDRATEPRESCALER_DIV32             (SPI_CFG1_MBR_2)

+#define LL_SPI_BAUDRATEPRESCALER_DIV64             (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_0)

+#define LL_SPI_BAUDRATEPRESCALER_DIV128            (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1)

+#define LL_SPI_BAUDRATEPRESCALER_DIV256            (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0)

+/**

+  * @}

+  */

+

+/** @defgroup SPI_LL_EC_BIT_ORDER Bit Order

+  * @{

+  */

+#define LL_SPI_LSB_FIRST                           (SPI_CFG2_LSBFRST)

+#define LL_SPI_MSB_FIRST                           (0x00000000UL)

+/**

+  * @}

+  */

+

+/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode

+  * @{

+  */

+#define LL_SPI_FULL_DUPLEX                         (0x00000000UL)

+#define LL_SPI_SIMPLEX_TX                          (SPI_CFG2_COMM_0)

+#define LL_SPI_SIMPLEX_RX                          (SPI_CFG2_COMM_1)

+#define LL_SPI_HALF_DUPLEX_RX                      (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1)

+#define LL_SPI_HALF_DUPLEX_TX                      (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1|SPI_CR1_HDDIR)

+/**

+  * @}

+  */

+

+/** @defgroup SPI_LL_EC_DATAWIDTH Data Width

+  * @{

+  */

+#define LL_SPI_DATAWIDTH_4BIT                      (SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)

+#define LL_SPI_DATAWIDTH_5BIT                      (SPI_CFG1_DSIZE_2)

+#define LL_SPI_DATAWIDTH_6BIT                      (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)

+#define LL_SPI_DATAWIDTH_7BIT                      (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)

+#define LL_SPI_DATAWIDTH_8BIT                      (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)

+#define LL_SPI_DATAWIDTH_9BIT                      (SPI_CFG1_DSIZE_3)

+#define LL_SPI_DATAWIDTH_10BIT                     (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)

+#define LL_SPI_DATAWIDTH_11BIT                     (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)

+#define LL_SPI_DATAWIDTH_12BIT                     (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)

+#define LL_SPI_DATAWIDTH_13BIT                     (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)

+#define LL_SPI_DATAWIDTH_14BIT                     (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)

+#define LL_SPI_DATAWIDTH_15BIT                     (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)

+#define LL_SPI_DATAWIDTH_16BIT                     (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)

+#define LL_SPI_DATAWIDTH_17BIT                     (SPI_CFG1_DSIZE_4)

+#define LL_SPI_DATAWIDTH_18BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0)

+#define LL_SPI_DATAWIDTH_19BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_1)

+#define LL_SPI_DATAWIDTH_20BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1)

+#define LL_SPI_DATAWIDTH_21BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2)

+#define LL_SPI_DATAWIDTH_22BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)

+#define LL_SPI_DATAWIDTH_23BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)

+#define LL_SPI_DATAWIDTH_24BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)

+#define LL_SPI_DATAWIDTH_25BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3)

+#define LL_SPI_DATAWIDTH_26BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0)

+#define LL_SPI_DATAWIDTH_27BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1)

+#define LL_SPI_DATAWIDTH_28BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)

+#define LL_SPI_DATAWIDTH_29BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2)

+#define LL_SPI_DATAWIDTH_30BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0)

+#define LL_SPI_DATAWIDTH_31BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1)

+#define LL_SPI_DATAWIDTH_32BIT                     (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0)

+/**

+  * @}

+  */

+

+/** @defgroup SPI_LL_EC_FIFO_TH FIFO Threshold

+  * @{

+  */

+#define LL_SPI_FIFO_TH_01DATA                      (0x00000000UL)

+#define LL_SPI_FIFO_TH_02DATA                      (SPI_CFG1_FTHLV_0)

+#define LL_SPI_FIFO_TH_03DATA                      (SPI_CFG1_FTHLV_1)

+#define LL_SPI_FIFO_TH_04DATA                      (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1)

+#define LL_SPI_FIFO_TH_05DATA                      (SPI_CFG1_FTHLV_2)

+#define LL_SPI_FIFO_TH_06DATA                      (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)

+#define LL_SPI_FIFO_TH_07DATA                      (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)

+#define LL_SPI_FIFO_TH_08DATA                      (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)

+#define LL_SPI_FIFO_TH_09DATA                      (SPI_CFG1_FTHLV_3)

+#define LL_SPI_FIFO_TH_10DATA                      (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_0)

+#define LL_SPI_FIFO_TH_11DATA                      (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1)

+#define LL_SPI_FIFO_TH_12DATA                      (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)

+#define LL_SPI_FIFO_TH_13DATA                      (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2)

+#define LL_SPI_FIFO_TH_14DATA                      (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0)

+#define LL_SPI_FIFO_TH_15DATA                      (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1)

+#define LL_SPI_FIFO_TH_16DATA                      (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0)

+/**

+  * @}

+  */

+

+#if defined(USE_FULL_LL_DRIVER)

+

+/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation

+  * @{

+  */

+#define LL_SPI_CRCCALCULATION_DISABLE              (0x00000000UL)            /*!< CRC calculation disabled */

+#define LL_SPI_CRCCALCULATION_ENABLE               (SPI_CFG1_CRCEN)          /*!< CRC calculation enabled  */

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/** @defgroup SPI_LL_EC_CRC CRC

+  * @{

+  */

+#define LL_SPI_CRC_4BIT                            (SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)

+#define LL_SPI_CRC_5BIT                            (SPI_CFG1_CRCSIZE_2)

+#define LL_SPI_CRC_6BIT                            (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)

+#define LL_SPI_CRC_7BIT                            (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)

+#define LL_SPI_CRC_8BIT                            (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)

+#define LL_SPI_CRC_9BIT                            (SPI_CFG1_CRCSIZE_3)

+#define LL_SPI_CRC_10BIT                           (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)

+#define LL_SPI_CRC_11BIT                           (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)

+#define LL_SPI_CRC_12BIT                           (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)

+#define LL_SPI_CRC_13BIT                           (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)

+#define LL_SPI_CRC_14BIT                           (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)

+#define LL_SPI_CRC_15BIT                           (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)

+#define LL_SPI_CRC_16BIT                           (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)

+#define LL_SPI_CRC_17BIT                           (SPI_CFG1_CRCSIZE_4)

+#define LL_SPI_CRC_18BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0)

+#define LL_SPI_CRC_19BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_1)

+#define LL_SPI_CRC_20BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1)

+#define LL_SPI_CRC_21BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2)

+#define LL_SPI_CRC_22BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)

+#define LL_SPI_CRC_23BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)

+#define LL_SPI_CRC_24BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)

+#define LL_SPI_CRC_25BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3)

+#define LL_SPI_CRC_26BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0)

+#define LL_SPI_CRC_27BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1)

+#define LL_SPI_CRC_28BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)

+#define LL_SPI_CRC_29BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2)

+#define LL_SPI_CRC_30BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0)

+#define LL_SPI_CRC_31BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1)

+#define LL_SPI_CRC_32BIT                           (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0)

+/**

+  * @}

+  */

+

+/** @defgroup SPI_LL_EC_NSS_MODE NSS Mode

+  * @{

+  */

+#define LL_SPI_NSS_SOFT                            (SPI_CFG2_SSM)

+#define LL_SPI_NSS_HARD_INPUT                      (0x00000000UL)

+#define LL_SPI_NSS_HARD_OUTPUT                     (SPI_CFG2_SSOE)

+/**

+  * @}

+  */

+

+/** @defgroup SPI_LL_EC_RX_FIFO RxFIFO Packing LeVel

+  * @{

+  */

+#define LL_SPI_RX_FIFO_0PACKET                     (0x00000000UL)                      /* 0 or multiple of 4 packet available is the RxFIFO */

+#define LL_SPI_RX_FIFO_1PACKET                     (SPI_SR_RXPLVL_0)

+#define LL_SPI_RX_FIFO_2PACKET                     (SPI_SR_RXPLVL_1)

+#define LL_SPI_RX_FIFO_3PACKET                     (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0)

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros

+  * @{

+  */

+

+/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros

+  * @{

+  */

+

+/**

+  * @brief  Write a value in SPI register

+  * @param  __INSTANCE__ SPI Instance

+  * @param  __REG__ Register to be written

+  * @param  __VALUE__ Value to be written in the register

+  * @retval None

+  */

+#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

+

+/**

+  * @brief  Read a value in SPI register

+  * @param  __INSTANCE__ SPI Instance

+  * @param  __REG__ Register to be read

+  * @retval Register value

+  */

+#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+

+/* Exported functions --------------------------------------------------------*/

+

+/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions

+  * @{

+  */

+

+/** @defgroup SPI_LL_EF_Configuration Configuration

+  * @{

+  */

+

+/**

+  * @brief  Enable SPI peripheral

+  * @rmtoll CR1          SPE           LL_SPI_Enable

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->CR1, SPI_CR1_SPE);

+}

+

+/**

+  * @brief  Disable SPI peripheral

+  * @note   When disabling the SPI, follow the procedure described in the Reference Manual.

+  * @rmtoll CR1          SPE           LL_SPI_Disable

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx)

+{

+  CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);

+}

+

+/**

+  * @brief  Check if SPI peripheral is enabled

+  * @rmtoll CR1          SPE           LL_SPI_IsEnabled

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Swap the MOSI and MISO pin

+  * @note   This configuration can not be changed when SPI is enabled.

+  * @rmtoll CFG2         IOSWP         LL_SPI_EnableIOSwap

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_EnableIOSwap(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->CFG2, SPI_CFG2_IOSWP);

+}

+

+/**

+  * @brief  Restore default function for MOSI and MISO pin

+  * @note   This configuration can not be changed when SPI is enabled.

+  * @rmtoll CFG2         IOSWP         LL_SPI_DisableIOSwap

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_DisableIOSwap(SPI_TypeDef *SPIx)

+{

+  CLEAR_BIT(SPIx->CFG2, SPI_CFG2_IOSWP);

+}

+

+/**

+  * @brief  Check if MOSI and MISO pin are swapped

+  * @rmtoll CFG2         IOSWP         LL_SPI_IsEnabledIOSwap

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOSwap(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable GPIO control

+  * @note   This configuration can not be changed when SPI is enabled.

+  * @rmtoll CFG2         AFCNTR        LL_SPI_EnableGPIOControl

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_EnableGPIOControl(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR);

+}

+

+/**

+  * @brief  Disable GPIO control

+  * @note   This configuration can not be changed when SPI is enabled.

+  * @rmtoll CFG2         AFCNTR        LL_SPI_DisableGPIOControl

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_DisableGPIOControl(SPI_TypeDef *SPIx)

+{

+  CLEAR_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR);

+}

+

+/**

+  * @brief  Check if GPIO control is active

+  * @rmtoll CFG2         AFCNTR        LL_SPI_IsEnabledGPIOControl

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsEnabledGPIOControl(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR) == (SPI_CFG2_AFCNTR)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set SPI Mode to Master or Slave

+  * @note   This configuration can not be changed when SPI is enabled.

+  * @rmtoll CFG2         MASTER        LL_SPI_SetMode

+  * @param  SPIx SPI Instance

+  * @param  Mode This parameter can be one of the following values:

+  *         @arg @ref LL_SPI_MODE_MASTER

+  *         @arg @ref LL_SPI_MODE_SLAVE

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode)

+{

+  MODIFY_REG(SPIx->CFG2, SPI_CFG2_MASTER, Mode);

+}

+

+/**

+  * @brief  Get SPI Mode (Master or Slave)

+  * @rmtoll CFG2         MASTER        LL_SPI_GetMode

+  * @param  SPIx SPI Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_SPI_MODE_MASTER

+  *         @arg @ref LL_SPI_MODE_SLAVE

+  */

+__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MASTER));

+}

+

+/**

+  * @brief  Configure the Idleness applied by master between active edge of SS and first send data

+  * @rmtoll CFG2         MSSI          LL_SPI_SetMasterSSIdleness

+  * @param  SPIx SPI Instance

+  * @param  MasterSSIdleness This parameter can be one of the following values:

+  *         @arg @ref LL_SPI_SS_IDLENESS_00CYCLE

+  *         @arg @ref LL_SPI_SS_IDLENESS_01CYCLE

+  *         @arg @ref LL_SPI_SS_IDLENESS_02CYCLE

+  *         @arg @ref LL_SPI_SS_IDLENESS_03CYCLE

+  *         @arg @ref LL_SPI_SS_IDLENESS_04CYCLE

+  *         @arg @ref LL_SPI_SS_IDLENESS_05CYCLE

+  *         @arg @ref LL_SPI_SS_IDLENESS_06CYCLE

+  *         @arg @ref LL_SPI_SS_IDLENESS_07CYCLE

+  *         @arg @ref LL_SPI_SS_IDLENESS_08CYCLE

+  *         @arg @ref LL_SPI_SS_IDLENESS_09CYCLE

+  *         @arg @ref LL_SPI_SS_IDLENESS_10CYCLE

+  *         @arg @ref LL_SPI_SS_IDLENESS_11CYCLE

+  *         @arg @ref LL_SPI_SS_IDLENESS_12CYCLE

+  *         @arg @ref LL_SPI_SS_IDLENESS_13CYCLE

+  *         @arg @ref LL_SPI_SS_IDLENESS_14CYCLE

+  *         @arg @ref LL_SPI_SS_IDLENESS_15CYCLE

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_SetMasterSSIdleness(SPI_TypeDef *SPIx, uint32_t MasterSSIdleness)

+{

+  MODIFY_REG(SPIx->CFG2, SPI_CFG2_MSSI, MasterSSIdleness);

+}

+

+/**

+  * @brief  Get the configured Idleness applied by master

+  * @rmtoll CFG2         MSSI          LL_SPI_GetMasterSSIdleness

+  * @param  SPIx SPI Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_SPI_SS_IDLENESS_00CYCLE

+  *         @arg @ref LL_SPI_SS_IDLENESS_01CYCLE

+  *         @arg @ref LL_SPI_SS_IDLENESS_02CYCLE

+  *         @arg @ref LL_SPI_SS_IDLENESS_03CYCLE

+  *         @arg @ref LL_SPI_SS_IDLENESS_04CYCLE

+  *         @arg @ref LL_SPI_SS_IDLENESS_05CYCLE

+  *         @arg @ref LL_SPI_SS_IDLENESS_06CYCLE

+  *         @arg @ref LL_SPI_SS_IDLENESS_07CYCLE

+  *         @arg @ref LL_SPI_SS_IDLENESS_08CYCLE

+  *         @arg @ref LL_SPI_SS_IDLENESS_09CYCLE

+  *         @arg @ref LL_SPI_SS_IDLENESS_10CYCLE

+  *         @arg @ref LL_SPI_SS_IDLENESS_11CYCLE

+  *         @arg @ref LL_SPI_SS_IDLENESS_12CYCLE

+  *         @arg @ref LL_SPI_SS_IDLENESS_13CYCLE

+  *         @arg @ref LL_SPI_SS_IDLENESS_14CYCLE

+  *         @arg @ref LL_SPI_SS_IDLENESS_15CYCLE

+  */

+__STATIC_INLINE uint32_t LL_SPI_GetMasterSSIdleness(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MSSI));

+}

+

+/**

+  * @brief  Configure the idleness applied by master between data frame

+  * @rmtoll CFG2         MIDI          LL_SPI_SetInterDataIdleness

+  * @param  SPIx SPI Instance

+  * @param  MasterInterDataIdleness This parameter can be one of the following values:

+  *         @arg @ref LL_SPI_ID_IDLENESS_00CYCLE

+  *         @arg @ref LL_SPI_ID_IDLENESS_01CYCLE

+  *         @arg @ref LL_SPI_ID_IDLENESS_02CYCLE

+  *         @arg @ref LL_SPI_ID_IDLENESS_03CYCLE

+  *         @arg @ref LL_SPI_ID_IDLENESS_04CYCLE

+  *         @arg @ref LL_SPI_ID_IDLENESS_05CYCLE

+  *         @arg @ref LL_SPI_ID_IDLENESS_06CYCLE

+  *         @arg @ref LL_SPI_ID_IDLENESS_07CYCLE

+  *         @arg @ref LL_SPI_ID_IDLENESS_08CYCLE

+  *         @arg @ref LL_SPI_ID_IDLENESS_09CYCLE

+  *         @arg @ref LL_SPI_ID_IDLENESS_10CYCLE

+  *         @arg @ref LL_SPI_ID_IDLENESS_11CYCLE

+  *         @arg @ref LL_SPI_ID_IDLENESS_12CYCLE

+  *         @arg @ref LL_SPI_ID_IDLENESS_13CYCLE

+  *         @arg @ref LL_SPI_ID_IDLENESS_14CYCLE

+  *         @arg @ref LL_SPI_ID_IDLENESS_15CYCLE

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_SetInterDataIdleness(SPI_TypeDef *SPIx, uint32_t MasterInterDataIdleness)

+{

+  MODIFY_REG(SPIx->CFG2, SPI_CFG2_MIDI, MasterInterDataIdleness);

+}

+

+/**

+  * @brief  Get the configured inter data idleness

+  * @rmtoll CFG2         MIDI          LL_SPI_SetInterDataIdleness

+  * @param  SPIx SPI Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_SPI_ID_IDLENESS_00CYCLE

+  *         @arg @ref LL_SPI_ID_IDLENESS_01CYCLE

+  *         @arg @ref LL_SPI_ID_IDLENESS_02CYCLE

+  *         @arg @ref LL_SPI_ID_IDLENESS_03CYCLE

+  *         @arg @ref LL_SPI_ID_IDLENESS_04CYCLE

+  *         @arg @ref LL_SPI_ID_IDLENESS_05CYCLE

+  *         @arg @ref LL_SPI_ID_IDLENESS_06CYCLE

+  *         @arg @ref LL_SPI_ID_IDLENESS_07CYCLE

+  *         @arg @ref LL_SPI_ID_IDLENESS_08CYCLE

+  *         @arg @ref LL_SPI_ID_IDLENESS_09CYCLE

+  *         @arg @ref LL_SPI_ID_IDLENESS_10CYCLE

+  *         @arg @ref LL_SPI_ID_IDLENESS_11CYCLE

+  *         @arg @ref LL_SPI_ID_IDLENESS_12CYCLE

+  *         @arg @ref LL_SPI_ID_IDLENESS_13CYCLE

+  *         @arg @ref LL_SPI_ID_IDLENESS_14CYCLE

+  *         @arg @ref LL_SPI_ID_IDLENESS_15CYCLE

+  */

+__STATIC_INLINE uint32_t LL_SPI_GetInterDataIdleness(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MIDI));

+}

+

+/**

+  * @brief  Set transfer size

+  * @note    Count is the number of frame to be transferred

+  * @rmtoll CR2          TSIZE         LL_SPI_SetTransferSize

+  * @param  SPIx SPI Instance

+  * @param  Count 0..0xFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_SetTransferSize(SPI_TypeDef *SPIx, uint32_t Count)

+{

+  MODIFY_REG(SPIx->CR2, SPI_CR2_TSIZE, Count);

+}

+

+/**

+  * @brief  Get transfer size

+  * @note    Count is the number of frame to be transferred

+  * @rmtoll CR2          TSIZE         LL_SPI_GetTransferSize

+  * @param  SPIx SPI Instance

+  * @retval 0..0xFFFF

+  */

+__STATIC_INLINE uint32_t LL_SPI_GetTransferSize(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSIZE));

+}

+

+/**

+  * @brief  Set reload transfer size

+  * @note    Count is the number of frame to be transferred

+  * @rmtoll CR2          TSER          LL_SPI_SetReloadSize

+  * @param  SPIx SPI Instance

+  * @param  Count 0..0xFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_SetReloadSize(SPI_TypeDef *SPIx, uint32_t Count)

+{

+  MODIFY_REG(SPIx->CR2, SPI_CR2_TSER, Count << SPI_CR2_TSER_Pos);

+}

+

+/**

+  * @brief  Get reload transfer size

+  * @note    Count is the number of frame to be transferred

+  * @rmtoll CR2          TSER          LL_SPI_GetReloadSize

+  * @param  SPIx SPI Instance

+  * @retval 0..0xFFFF

+  */

+__STATIC_INLINE uint32_t LL_SPI_GetReloadSize(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSER) >> SPI_CR2_TSER_Pos);

+}

+

+/**

+  * @brief  Lock the AF configuration of associated IOs

+  * @note   Once this bit is set, the AF configuration remains locked until a hardware reset occurs.

+  *         the reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist.

+  * @rmtoll CR1          IOLOCK        LL_SPI_EnableIOLock

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_EnableIOLock(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->CR1, SPI_CR1_IOLOCK);

+}

+

+/**

+  * @brief  Check if the AF configuration is locked.

+  * @rmtoll CR1          IOLOCK        LL_SPI_IsEnabledIOLock

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set Tx CRC Initialization Pattern

+  * @rmtoll CR1          TCRCINI         LL_SPI_SetTxCRCInitPattern

+  * @param  SPIx SPI Instance

+  * @param  TXCRCInitAll This parameter can be one of the following values:

+  *         @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN

+  *         @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_SetTxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t TXCRCInitAll)

+{

+  MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, TXCRCInitAll);

+}

+

+/**

+  * @brief  Get Tx CRC Initialization Pattern

+  * @rmtoll CR1          TCRCINI         LL_SPI_GetTxCRCInitPattern

+  * @param  SPIx SPI Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN

+  *         @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN

+  */

+__STATIC_INLINE uint32_t LL_SPI_GetTxCRCInitPattern(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_TCRCINI));

+}

+

+/**

+  * @brief  Set Rx CRC Initialization Pattern

+  * @rmtoll CR1          RCRCINI         LL_SPI_SetRxCRCInitPattern

+  * @param  SPIx SPI Instance

+  * @param  RXCRCInitAll This parameter can be one of the following values:

+  *         @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN

+  *         @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_SetRxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t RXCRCInitAll)

+{

+  MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, RXCRCInitAll);

+}

+

+/**

+  * @brief  Get Rx CRC Initialization Pattern

+  * @rmtoll CR1          RCRCINI         LL_SPI_GetRxCRCInitPattern

+  * @param  SPIx SPI Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN

+  *         @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN

+  */

+__STATIC_INLINE uint32_t LL_SPI_GetRxCRCInitPattern(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RCRCINI));

+}

+

+/**

+  * @brief  Set internal SS input level ignoring what comes from PIN.

+  * @note   This configuration has effect only with config LL_SPI_NSS_SOFT

+  * @rmtoll CR1          SSI           LL_SPI_SetInternalSSLevel

+  * @param  SPIx SPI Instance

+  * @param  SSLevel This parameter can be one of the following values:

+  *         @arg @ref LL_SPI_SS_LEVEL_HIGH

+  *         @arg @ref LL_SPI_SS_LEVEL_LOW

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_SetInternalSSLevel(SPI_TypeDef *SPIx, uint32_t SSLevel)

+{

+  MODIFY_REG(SPIx->CR1, SPI_CR1_SSI, SSLevel);

+}

+

+/**

+  * @brief  Get internal SS input level

+  * @rmtoll CR1          SSI           LL_SPI_GetInternalSSLevel

+  * @param  SPIx SPI Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_SPI_SS_LEVEL_HIGH

+  *         @arg @ref LL_SPI_SS_LEVEL_LOW

+  */

+__STATIC_INLINE uint32_t LL_SPI_GetInternalSSLevel(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_SSI));

+}

+

+/**

+  * @brief  Enable CRC computation on 33/17 bits

+  * @rmtoll CR1          CRC33_17      LL_SPI_EnableFullSizeCRC

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_EnableFullSizeCRC(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->CR1, SPI_CR1_CRC33_17);

+}

+

+/**

+  * @brief  Disable CRC computation on 33/17 bits

+  * @rmtoll CR1          CRC33_17      LL_SPI_DisableFullSizeCRC

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_DisableFullSizeCRC(SPI_TypeDef *SPIx)

+{

+  CLEAR_BIT(SPIx->CR1, SPI_CR1_CRC33_17);

+}

+

+/**

+  * @brief  Check if Enable CRC computation on 33/17 bits is enabled

+  * @rmtoll CR1          CRC33_17      LL_SPI_IsEnabledFullSizeCRC

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsEnabledFullSizeCRC(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->CR1, SPI_CR1_CRC33_17) == (SPI_CR1_CRC33_17)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Suspend an ongoing transfer for Master configuration

+  * @rmtoll CR1          CSUSP         LL_SPI_SuspendMasterTransfer

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_SuspendMasterTransfer(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->CR1, SPI_CR1_CSUSP);

+}

+

+/**

+  * @brief  Start effective transfer on wire for Master configuration

+  * @rmtoll CR1          CSTART        LL_SPI_StartMasterTransfer

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_StartMasterTransfer(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->CR1, SPI_CR1_CSTART);

+}

+

+/**

+  * @brief  Check if there is an unfinished master transfer

+  * @rmtoll CR1          CSTART        LL_SPI_IsMasterTransferActive

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsActiveMasterTransfer(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->CR1, SPI_CR1_CSTART) == (SPI_CR1_CSTART)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable Master Rx auto suspend in case of overrun

+  * @rmtoll CR1          MASRX         LL_SPI_EnableMasterRxAutoSuspend

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_EnableMasterRxAutoSuspend(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->CR1, SPI_CR1_MASRX);

+}

+

+/**

+  * @brief  Disable Master Rx auto suspend in case of overrun

+  * @rmtoll CR1          MASRX         LL_SPI_DisableMasterRxAutoSuspend

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_DisableMasterRxAutoSuspend(SPI_TypeDef *SPIx)

+{

+  CLEAR_BIT(SPIx->CR1, SPI_CR1_MASRX);

+}

+

+/**

+  * @brief  Check if Master Rx auto suspend is activated

+  * @rmtoll CR1          MASRX         LL_SPI_IsEnabledMasterRxAutoSuspend

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsEnabledMasterRxAutoSuspend(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->CR1, SPI_CR1_MASRX) == (SPI_CR1_MASRX)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set Underrun behavior

+  * @note   This configuration can not be changed when SPI is enabled.

+  * @rmtoll CFG1         UDRCFG        LL_SPI_SetUDRConfiguration

+  * @param  SPIx SPI Instance

+  * @param  UDRConfig This parameter can be one of the following values:

+  *         @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN

+  *         @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED

+  *         @arg @ref LL_SPI_UDR_CONFIG_LAST_TRANSMITTED

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_SetUDRConfiguration(SPI_TypeDef *SPIx, uint32_t UDRConfig)

+{

+  MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRCFG, UDRConfig);

+}

+

+/**

+  * @brief  Get Underrun behavior

+  * @rmtoll CFG1         UDRCFG        LL_SPI_GetUDRConfiguration

+  * @param  SPIx SPI Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN

+  *         @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED

+  *         @arg @ref LL_SPI_UDR_CONFIG_LAST_TRANSMITTED

+  */

+__STATIC_INLINE uint32_t LL_SPI_GetUDRConfiguration(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG));

+}

+

+/**

+  * @brief  Set Underrun Detection method

+  * @note   This configuration can not be changed when SPI is enabled.

+  * @rmtoll CFG1         UDRDET        LL_SPI_SetUDRDetection

+  * @param  SPIx SPI Instance

+  * @param  UDRDetection This parameter can be one of the following values:

+  *         @arg @ref LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME

+  *         @arg @ref LL_SPI_UDR_DETECT_END_DATA_FRAME

+  *         @arg @ref LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_SetUDRDetection(SPI_TypeDef *SPIx, uint32_t UDRDetection)

+{

+  MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRDET, UDRDetection);

+}

+

+/**

+  * @brief  Get Underrun Detection method

+  * @rmtoll CFG1         UDRDET        LL_SPI_GetUDRDetection

+  * @param  SPIx SPI Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_SPI_UDR_DETECT_BEGIN_DATA_FRAME

+  *         @arg @ref LL_SPI_UDR_DETECT_END_DATA_FRAME

+  *         @arg @ref LL_SPI_UDR_DETECT_BEGIN_ACTIVE_NSS

+  */

+__STATIC_INLINE uint32_t LL_SPI_GetUDRDetection(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRDET));

+}

+

+/**

+  * @brief  Set Serial protocol used

+  * @note   This configuration can not be changed when SPI is enabled.

+  * @rmtoll CFG2         SP            LL_SPI_SetStandard

+  * @param  SPIx SPI Instance

+  * @param  Standard This parameter can be one of the following values:

+  *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA

+  *         @arg @ref LL_SPI_PROTOCOL_TI

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)

+{

+  MODIFY_REG(SPIx->CFG2, SPI_CFG2_SP, Standard);

+}

+

+/**

+  * @brief  Get Serial protocol used

+  * @rmtoll CFG2         SP            LL_SPI_GetStandard

+  * @param  SPIx SPI Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_SPI_PROTOCOL_MOTOROLA

+  *         @arg @ref LL_SPI_PROTOCOL_TI

+  */

+__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SP));

+}

+

+/**

+  * @brief  Set Clock phase

+  * @note   This configuration can not be changed when SPI is enabled.

+  *         This bit is not used in SPI TI mode.

+  * @rmtoll CFG2         CPHA          LL_SPI_SetClockPhase

+  * @param  SPIx SPI Instance

+  * @param  ClockPhase This parameter can be one of the following values:

+  *         @arg @ref LL_SPI_PHASE_1EDGE

+  *         @arg @ref LL_SPI_PHASE_2EDGE

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase)

+{

+  MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPHA, ClockPhase);

+}

+

+/**

+  * @brief  Get Clock phase

+  * @rmtoll CFG2         CPHA          LL_SPI_GetClockPhase

+  * @param  SPIx SPI Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_SPI_PHASE_1EDGE

+  *         @arg @ref LL_SPI_PHASE_2EDGE

+  */

+__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPHA));

+}

+

+/**

+  * @brief  Set Clock polarity

+  * @note   This configuration can not be changed when SPI is enabled.

+  *         This bit is not used in SPI TI mode.

+  * @rmtoll CFG2         CPOL          LL_SPI_SetClockPolarity

+  * @param  SPIx SPI Instance

+  * @param  ClockPolarity This parameter can be one of the following values:

+  *         @arg @ref LL_SPI_POLARITY_LOW

+  *         @arg @ref LL_SPI_POLARITY_HIGH

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)

+{

+  MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPOL, ClockPolarity);

+}

+

+/**

+  * @brief  Get Clock polarity

+  * @rmtoll CFG2         CPOL          LL_SPI_GetClockPolarity

+  * @param  SPIx SPI Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_SPI_POLARITY_LOW

+  *         @arg @ref LL_SPI_POLARITY_HIGH

+  */

+__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPOL));

+}

+

+/**

+  * @brief  Set NSS polarity

+  * @note   This configuration can not be changed when SPI is enabled.

+  *         This bit is not used in SPI TI mode.

+  * @rmtoll CFG2         SSIOP          LL_SPI_SetNSSPolarity

+  * @param  SPIx SPI Instance

+  * @param  NSSPolarity This parameter can be one of the following values:

+  *         @arg @ref LL_SPI_NSS_POLARITY_LOW

+  *         @arg @ref LL_SPI_NSS_POLARITY_HIGH

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_SetNSSPolarity(SPI_TypeDef *SPIx, uint32_t NSSPolarity)

+{

+  MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSIOP, NSSPolarity);

+}

+

+/**

+  * @brief  Get NSS polarity

+  * @rmtoll CFG2         SSIOP          LL_SPI_GetNSSPolarity

+  * @param  SPIx SPI Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_SPI_NSS_POLARITY_LOW

+  *         @arg @ref LL_SPI_NSS_POLARITY_HIGH

+  */

+__STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSIOP));

+}

+

+/**

+  * @brief  Set Baudrate Prescaler

+  * @note   This configuration can not be changed when SPI is enabled.

+  *         SPI BaudRate = fPCLK/Pescaler.

+  * @rmtoll CFG1         MBR           LL_SPI_SetBaudRatePrescaler

+  * @param  SPIx SPI Instance

+  * @param  Baudrate This parameter can be one of the following values:

+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2

+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4

+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8

+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16

+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32

+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64

+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128

+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Baudrate)

+{

+  MODIFY_REG(SPIx->CFG1, SPI_CFG1_MBR, Baudrate);

+}

+

+/**

+  * @brief  Get Baudrate Prescaler

+  * @rmtoll CFG1         MBR           LL_SPI_GetBaudRatePrescaler

+  * @param  SPIx SPI Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2

+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4

+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8

+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16

+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32

+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64

+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128

+  *         @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256

+  */

+__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_MBR));

+}

+

+/**

+  * @brief  Set Transfer Bit Order

+  * @note   This configuration can not be changed when SPI is enabled.

+  *         This bit is not used in SPI TI mode.

+  * @rmtoll CFG2         LSBFRST       LL_SPI_SetTransferBitOrder

+  * @param  SPIx SPI Instance

+  * @param  BitOrder This parameter can be one of the following values:

+  *         @arg @ref LL_SPI_LSB_FIRST

+  *         @arg @ref LL_SPI_MSB_FIRST

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)

+{

+  MODIFY_REG(SPIx->CFG2, SPI_CFG2_LSBFRST, BitOrder);

+}

+

+/**

+  * @brief  Get Transfer Bit Order

+  * @rmtoll CFG2         LSBFRST       LL_SPI_GetTransferBitOrder

+  * @param  SPIx SPI Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_SPI_LSB_FIRST

+  *         @arg @ref LL_SPI_MSB_FIRST

+  */

+__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_LSBFRST));

+}

+

+/**

+  * @brief  Set Transfer Mode

+  * @note   This configuration can not be changed when SPI is enabled except for half duplex direction using LL_SPI_SetHalfDuplexDirection.

+  * @rmtoll CR1          HDDIR         LL_SPI_SetTransferDirection\n

+  *         CFG2         COMM          LL_SPI_SetTransferDirection

+  * @param  SPIx SPI Instance

+  * @param  TransferDirection This parameter can be one of the following values:

+  *         @arg @ref LL_SPI_FULL_DUPLEX

+  *         @arg @ref LL_SPI_SIMPLEX_TX

+  *         @arg @ref LL_SPI_SIMPLEX_RX

+  *         @arg @ref LL_SPI_HALF_DUPLEX_RX

+  *         @arg @ref LL_SPI_HALF_DUPLEX_TX

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection)

+{

+  MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR,  TransferDirection & SPI_CR1_HDDIR);

+  MODIFY_REG(SPIx->CFG2, SPI_CFG2_COMM, TransferDirection & SPI_CFG2_COMM);

+}

+

+/**

+  * @brief  Get Transfer Mode

+  * @rmtoll CR1          HDDIR         LL_SPI_GetTransferDirection\n

+  *         CFG2         COMM          LL_SPI_GetTransferDirection

+  * @param  SPIx SPI Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_SPI_FULL_DUPLEX

+  *         @arg @ref LL_SPI_SIMPLEX_TX

+  *         @arg @ref LL_SPI_SIMPLEX_RX

+  *         @arg @ref LL_SPI_HALF_DUPLEX_RX

+  *         @arg @ref LL_SPI_HALF_DUPLEX_TX

+  */

+__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx)

+{

+  register uint32_t Hddir = READ_BIT(SPIx->CR1, SPI_CR1_HDDIR);

+  register uint32_t Comm = READ_BIT(SPIx->CFG2, SPI_CFG2_COMM);

+  return (Hddir | Comm);

+}

+

+/**

+  * @brief  Set direction for Half-Duplex Mode

+  * @note   In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex.

+  * @rmtoll CR1          HDDIR         LL_SPI_SetHalfDuplexDirection

+  * @param  SPIx SPI Instance

+  * @param  HalfDuplexDirection This parameter can be one of the following values:

+  *         @arg @ref LL_SPI_HALF_DUPLEX_RX

+  *         @arg @ref LL_SPI_HALF_DUPLEX_TX

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_SetHalfDuplexDirection(SPI_TypeDef *SPIx, uint32_t HalfDuplexDirection)

+{

+  MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, HalfDuplexDirection & SPI_CR1_HDDIR);

+}

+

+/**

+  * @brief  Get direction for Half-Duplex Mode

+  * @note   In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex.

+  * @rmtoll CR1          HDDIR         LL_SPI_GetHalfDuplexDirection

+  * @param  SPIx SPI Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_SPI_HALF_DUPLEX_RX

+  *         @arg @ref LL_SPI_HALF_DUPLEX_TX

+  */

+__STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_HDDIR) | SPI_CFG2_COMM);

+}

+

+/**

+  * @brief  Set Frame Data Size

+  * @note   This configuration can not be changed when SPI is enabled.

+  * @rmtoll CFG1         DSIZE         LL_SPI_SetDataWidth

+  * @param  SPIx SPI Instance

+  * @param  DataWidth This parameter can be one of the following values:

+  *         @arg @ref LL_SPI_DATAWIDTH_4BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_5BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_6BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_7BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_8BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_9BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_10BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_11BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_12BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_13BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_14BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_15BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_16BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_17BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_18BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_19BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_20BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_21BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_22BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_23BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_24BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_25BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_26BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_27BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_28BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_29BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_30BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_31BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_32BIT

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth)

+{

+  MODIFY_REG(SPIx->CFG1, SPI_CFG1_DSIZE, DataWidth);

+}

+

+/**

+  * @brief  Get Frame Data Size

+  * @rmtoll CFG1         DSIZE         LL_SPI_GetDataWidth

+  * @param  SPIx SPI Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_SPI_DATAWIDTH_4BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_5BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_6BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_7BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_8BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_9BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_10BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_11BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_12BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_13BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_14BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_15BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_16BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_17BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_18BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_19BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_20BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_21BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_22BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_23BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_24BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_25BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_26BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_27BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_28BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_29BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_30BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_31BIT

+  *         @arg @ref LL_SPI_DATAWIDTH_32BIT

+  */

+__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE));

+}

+

+/**

+  * @brief  Set threshold of FIFO that triggers a transfer event

+  * @note   This configuration can not be changed when SPI is enabled.

+  * @rmtoll CFG1         FTHLV         LL_SPI_SetFIFOThreshold

+  * @param  SPIx SPI Instance

+  * @param  Threshold This parameter can be one of the following values:

+  *         @arg @ref LL_SPI_FIFO_TH_01DATA

+  *         @arg @ref LL_SPI_FIFO_TH_02DATA

+  *         @arg @ref LL_SPI_FIFO_TH_03DATA

+  *         @arg @ref LL_SPI_FIFO_TH_04DATA

+  *         @arg @ref LL_SPI_FIFO_TH_05DATA

+  *         @arg @ref LL_SPI_FIFO_TH_06DATA

+  *         @arg @ref LL_SPI_FIFO_TH_07DATA

+  *         @arg @ref LL_SPI_FIFO_TH_08DATA

+  *         @arg @ref LL_SPI_FIFO_TH_09DATA

+  *         @arg @ref LL_SPI_FIFO_TH_10DATA

+  *         @arg @ref LL_SPI_FIFO_TH_11DATA

+  *         @arg @ref LL_SPI_FIFO_TH_12DATA

+  *         @arg @ref LL_SPI_FIFO_TH_13DATA

+  *         @arg @ref LL_SPI_FIFO_TH_14DATA

+  *         @arg @ref LL_SPI_FIFO_TH_15DATA

+  *         @arg @ref LL_SPI_FIFO_TH_16DATA

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)

+{

+  MODIFY_REG(SPIx->CFG1, SPI_CFG1_FTHLV, Threshold);

+}

+

+/**

+  * @brief  Get threshold of FIFO that triggers a transfer event

+  * @rmtoll CFG1         FTHLV         LL_SPI_GetFIFOThreshold

+  * @param  SPIx SPI Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_SPI_FIFO_TH_01DATA

+  *         @arg @ref LL_SPI_FIFO_TH_02DATA

+  *         @arg @ref LL_SPI_FIFO_TH_03DATA

+  *         @arg @ref LL_SPI_FIFO_TH_04DATA

+  *         @arg @ref LL_SPI_FIFO_TH_05DATA

+  *         @arg @ref LL_SPI_FIFO_TH_06DATA

+  *         @arg @ref LL_SPI_FIFO_TH_07DATA

+  *         @arg @ref LL_SPI_FIFO_TH_08DATA

+  *         @arg @ref LL_SPI_FIFO_TH_09DATA

+  *         @arg @ref LL_SPI_FIFO_TH_10DATA

+  *         @arg @ref LL_SPI_FIFO_TH_11DATA

+  *         @arg @ref LL_SPI_FIFO_TH_12DATA

+  *         @arg @ref LL_SPI_FIFO_TH_13DATA

+  *         @arg @ref LL_SPI_FIFO_TH_14DATA

+  *         @arg @ref LL_SPI_FIFO_TH_15DATA

+  *         @arg @ref LL_SPI_FIFO_TH_16DATA

+  */

+__STATIC_INLINE uint32_t LL_SPI_GetFIFOThreshold(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV));

+}

+

+/**

+  * @brief  Enable CRC

+  * @note   This configuration can not be changed when SPI is enabled.

+  * @rmtoll CFG1         CRCEN         LL_SPI_EnableCRC

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);

+}

+

+/**

+  * @brief  Disable CRC

+  * @rmtoll CFG1         CRCEN         LL_SPI_DisableCRC

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx)

+{

+  CLEAR_BIT(SPIx->CFG1, SPI_CFG1_CRCEN);

+}

+

+/**

+  * @brief  Check if CRC is enabled

+  * @rmtoll CFG1         CRCEN         LL_SPI_IsEnabledCRC

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->CFG1, SPI_CFG1_CRCEN) == SPI_CFG1_CRCEN) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set CRC Length

+  * @note   This configuration can not be changed when SPI is enabled.

+  * @rmtoll CFG1         CRCSIZE       LL_SPI_SetCRCWidth

+  * @param  SPIx SPI Instance

+  * @param  CRCLength This parameter can be one of the following values:

+  *         @arg @ref LL_SPI_CRC_4BIT

+  *         @arg @ref LL_SPI_CRC_5BIT

+  *         @arg @ref LL_SPI_CRC_6BIT

+  *         @arg @ref LL_SPI_CRC_7BIT

+  *         @arg @ref LL_SPI_CRC_8BIT

+  *         @arg @ref LL_SPI_CRC_9BIT

+  *         @arg @ref LL_SPI_CRC_10BIT

+  *         @arg @ref LL_SPI_CRC_11BIT

+  *         @arg @ref LL_SPI_CRC_12BIT

+  *         @arg @ref LL_SPI_CRC_13BIT

+  *         @arg @ref LL_SPI_CRC_14BIT

+  *         @arg @ref LL_SPI_CRC_15BIT

+  *         @arg @ref LL_SPI_CRC_16BIT

+  *         @arg @ref LL_SPI_CRC_17BIT

+  *         @arg @ref LL_SPI_CRC_18BIT

+  *         @arg @ref LL_SPI_CRC_19BIT

+  *         @arg @ref LL_SPI_CRC_20BIT

+  *         @arg @ref LL_SPI_CRC_21BIT

+  *         @arg @ref LL_SPI_CRC_22BIT

+  *         @arg @ref LL_SPI_CRC_23BIT

+  *         @arg @ref LL_SPI_CRC_24BIT

+  *         @arg @ref LL_SPI_CRC_25BIT

+  *         @arg @ref LL_SPI_CRC_26BIT

+  *         @arg @ref LL_SPI_CRC_27BIT

+  *         @arg @ref LL_SPI_CRC_28BIT

+  *         @arg @ref LL_SPI_CRC_29BIT

+  *         @arg @ref LL_SPI_CRC_30BIT

+  *         @arg @ref LL_SPI_CRC_31BIT

+  *         @arg @ref LL_SPI_CRC_32BIT

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength)

+{

+  MODIFY_REG(SPIx->CFG1, SPI_CFG1_CRCSIZE, CRCLength);

+}

+

+/**

+  * @brief  Get CRC Length

+  * @rmtoll CFG1          CRCSIZE       LL_SPI_GetCRCWidth

+  * @param  SPIx SPI Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_SPI_CRC_4BIT

+  *         @arg @ref LL_SPI_CRC_5BIT

+  *         @arg @ref LL_SPI_CRC_6BIT

+  *         @arg @ref LL_SPI_CRC_7BIT

+  *         @arg @ref LL_SPI_CRC_8BIT

+  *         @arg @ref LL_SPI_CRC_9BIT

+  *         @arg @ref LL_SPI_CRC_10BIT

+  *         @arg @ref LL_SPI_CRC_11BIT

+  *         @arg @ref LL_SPI_CRC_12BIT

+  *         @arg @ref LL_SPI_CRC_13BIT

+  *         @arg @ref LL_SPI_CRC_14BIT

+  *         @arg @ref LL_SPI_CRC_15BIT

+  *         @arg @ref LL_SPI_CRC_16BIT

+  *         @arg @ref LL_SPI_CRC_17BIT

+  *         @arg @ref LL_SPI_CRC_18BIT

+  *         @arg @ref LL_SPI_CRC_19BIT

+  *         @arg @ref LL_SPI_CRC_20BIT

+  *         @arg @ref LL_SPI_CRC_21BIT

+  *         @arg @ref LL_SPI_CRC_22BIT

+  *         @arg @ref LL_SPI_CRC_23BIT

+  *         @arg @ref LL_SPI_CRC_24BIT

+  *         @arg @ref LL_SPI_CRC_25BIT

+  *         @arg @ref LL_SPI_CRC_26BIT

+  *         @arg @ref LL_SPI_CRC_27BIT

+  *         @arg @ref LL_SPI_CRC_28BIT

+  *         @arg @ref LL_SPI_CRC_29BIT

+  *         @arg @ref LL_SPI_CRC_30BIT

+  *         @arg @ref LL_SPI_CRC_31BIT

+  *         @arg @ref LL_SPI_CRC_32BIT

+  */

+__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_CRCSIZE));

+}

+

+/**

+  * @brief  Set NSS Mode

+  * @note   This configuration can not be changed when SPI is enabled.

+  *         This bit is not used in SPI TI mode.

+  * @rmtoll CFG2         SSM           LL_SPI_SetNSSMode\n

+  *         CFG2         SSOE          LL_SPI_SetNSSMode

+  * @param  SPIx SPI Instance

+  * @param  NSS This parameter can be one of the following values:

+  *         @arg @ref LL_SPI_NSS_SOFT

+  *         @arg @ref LL_SPI_NSS_HARD_INPUT

+  *         @arg @ref LL_SPI_NSS_HARD_OUTPUT

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS)

+{

+  MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE, NSS);

+}

+

+/**

+  * @brief  Set NSS Mode

+  * @rmtoll CFG2         SSM           LL_SPI_GetNSSMode\n

+  *         CFG2         SSOE          LL_SPI_GetNSSMode

+  * @param  SPIx SPI Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_SPI_NSS_SOFT

+  *         @arg @ref LL_SPI_NSS_HARD_INPUT

+  *         @arg @ref LL_SPI_NSS_HARD_OUTPUT

+  */

+__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE));

+}

+

+/**

+  * @brief  Enable NSS pulse mgt

+  * @note   This configuration can not be changed when SPI is enabled.

+  *         This bit is not used in SPI TI mode.

+  * @rmtoll CFG2         SSOM          LL_SPI_EnableNSSPulseMgt

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->CFG2, SPI_CFG2_SSOM);

+}

+

+/**

+  * @brief  Disable NSS pulse mgt

+  * @note   This configuration can not be changed when SPI is enabled.

+  *         This bit is not used in SPI TI mode.

+  * @rmtoll CFG2         SSOM          LL_SPI_DisableNSSPulseMgt

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx)

+{

+  CLEAR_BIT(SPIx->CFG2, SPI_CFG2_SSOM);

+}

+

+/**

+  * @brief  Check if NSS pulse is enabled

+  * @rmtoll CFG2         SSOM          LL_SPI_IsEnabledNSSPulse

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->CFG2, SPI_CFG2_SSOM) == SPI_CFG2_SSOM) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup SPI_LL_EF_FLAG_Management FLAG_Management

+  * @{

+  */

+

+/**

+  * @brief  Check if there is enough data in FIFO to read a full packet

+  * @rmtoll SR           RXP           LL_SPI_IsActiveFlag_RXP

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->SR, SPI_SR_RXP) == (SPI_SR_RXP)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if there is enough space in FIFO to hold a full packet

+  * @rmtoll SR           TXP           LL_SPI_IsActiveFlag_TXP

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->SR, SPI_SR_TXP) == (SPI_SR_TXP)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if there enough space in FIFO to hold a full packet, AND enough data to read a full packet

+  * @rmtoll SR           DXP           LL_SPI_IsActiveFlag_DXP

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->SR, SPI_SR_DXP) == (SPI_SR_DXP)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check that end of transfer event occured

+  * @rmtoll SR           EOT           LL_SPI_IsActiveFlag_EOT

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->SR, SPI_SR_EOT) == (SPI_SR_EOT)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check that all required data has been filled in the fifo according to transfer size

+  * @rmtoll SR           TXTF          LL_SPI_IsActiveFlag_TXTF

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->SR, SPI_SR_TXTF) == (SPI_SR_TXTF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Underrun error flag

+  * @rmtoll SR           UDR           LL_SPI_IsActiveFlag_UDR

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get CRC error flag

+  * @rmtoll SR           CRCE        LL_SPI_IsActiveFlag_CRCERR

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->SR, SPI_SR_CRCE) == (SPI_SR_CRCE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get  Mode fault error flag

+  * @rmtoll SR           MODF          LL_SPI_IsActiveFlag_MODF

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Overrun error flag

+  * @rmtoll SR           OVR           LL_SPI_IsActiveFlag_OVR

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get TI Frame format error flag

+  * @rmtoll SR           TIFRE         LL_SPI_IsActiveFlag_FRE

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->SR, SPI_SR_TIFRE) == (SPI_SR_TIFRE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the additional number of data has been reloaded

+  * @rmtoll SR           TSERF         LL_SPI_IsActiveFlag_TSER

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TSER(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->SR, SPI_SR_TSERF) == (SPI_SR_TSERF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if a suspend operation is done

+  * @rmtoll SR           SUSP          LL_SPI_IsActiveFlag_SUSP

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->SR, SPI_SR_SUSP) == (SPI_SR_SUSP)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if last TxFIFO or CRC frame transmission is completed

+  * @rmtoll SR           TXC           LL_SPI_IsActiveFlag_TXC

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->SR, SPI_SR_TXC) == (SPI_SR_TXC)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if at least one 32-bit data is available in RxFIFO

+  * @rmtoll SR           RXWNE         LL_SPI_IsActiveFlag_RXWNE

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->SR, SPI_SR_RXWNE) == (SPI_SR_RXWNE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get number of data framed remaining in current TSIZE

+  * @rmtoll SR           CTSIZE           LL_SPI_GetRemainingDataFrames

+  * @param  SPIx SPI Instance

+  * @retval 0..0xFFFF

+  */

+__STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_CTSIZE) >> SPI_SR_CTSIZE_Pos);

+}

+

+/**

+  * @brief  Get RxFIFO packing Level

+  * @rmtoll SR           RXPLVL        LL_SPI_GetRxFIFOPackingLevel

+  * @param  SPIx SPI Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_SPI_RX_FIFO_0PACKET

+  *         @arg @ref LL_SPI_RX_FIFO_1PACKET

+  *         @arg @ref LL_SPI_RX_FIFO_2PACKET

+  *         @arg @ref LL_SPI_RX_FIFO_3PACKET

+  */

+__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOPackingLevel(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_RXPLVL));

+}

+

+/**

+  * @brief  Clear End Of Transfer flag

+  * @rmtoll IFCR         EOTC          LL_SPI_ClearFlag_EOT

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_ClearFlag_EOT(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->IFCR, SPI_IFCR_EOTC);

+}

+

+/**

+  * @brief  Clear TXTF flag

+  * @rmtoll IFCR         TXTFC         LL_SPI_ClearFlag_TXTF

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_ClearFlag_TXTF(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->IFCR, SPI_IFCR_TXTFC);

+}

+

+/**

+  * @brief  Clear Underrun error flag

+  * @rmtoll IFCR         UDRC          LL_SPI_ClearFlag_UDR

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_ClearFlag_UDR(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->IFCR, SPI_IFCR_UDRC);

+}

+

+/**

+  * @brief  Clear Overrun error flag

+  * @rmtoll IFCR         OVRC          LL_SPI_ClearFlag_OVR

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->IFCR, SPI_IFCR_OVRC);

+}

+

+/**

+  * @brief  Clear CRC error flag

+  * @rmtoll IFCR         CRCEC        LL_SPI_ClearFlag_CRCERR

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->IFCR, SPI_IFCR_CRCEC);

+}

+

+/**

+  * @brief  Clear  Mode fault error flag

+  * @rmtoll IFCR         MODFC         LL_SPI_ClearFlag_MODF

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->IFCR, SPI_IFCR_MODFC);

+}

+

+/**

+  * @brief  Clear Frame format error flag

+  * @rmtoll IFCR         TIFREC        LL_SPI_ClearFlag_FRE

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->IFCR, SPI_IFCR_TIFREC);

+}

+

+/**

+  * @brief  Clear TSER flag

+  * @rmtoll IFCR         TSERFC        LL_SPI_ClearFlag_TSER

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_ClearFlag_TSER(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->IFCR, SPI_IFCR_TSERFC);

+}

+

+/**

+  * @brief  Clear SUSP flag

+  * @rmtoll IFCR         SUSPC         LL_SPI_ClearFlag_SUSP

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_ClearFlag_SUSP(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->IFCR, SPI_IFCR_SUSPC);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup SPI_LL_EF_IT_Management IT_Management

+  * @{

+  */

+

+/**

+  * @brief  Enable Rx Packet available IT

+  * @rmtoll IER          RXPIE         LL_SPI_EnableIT_RXP

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_EnableIT_RXP(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->IER, SPI_IER_RXPIE);

+}

+

+/**

+  * @brief  Enable Tx Packet space available IT

+  * @rmtoll IER          TXPIE         LL_SPI_EnableIT_TXP

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_EnableIT_TXP(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->IER, SPI_IER_TXPIE);

+}

+

+/**

+  * @brief  Enable Duplex Packet available IT

+  * @rmtoll IER          DXPIE         LL_SPI_EnableIT_DXP

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_EnableIT_DXP(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->IER, SPI_IER_DXPIE);

+}

+

+/**

+  * @brief  Enable End Of Transfer IT

+  * @rmtoll IER          EOTIE         LL_SPI_EnableIT_EOT

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_EnableIT_EOT(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->IER, SPI_IER_EOTIE);

+}

+

+/**

+  * @brief  Enable TXTF IT

+  * @rmtoll IER          TXTFIE        LL_SPI_EnableIT_TXTF

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_EnableIT_TXTF(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->IER, SPI_IER_TXTFIE);

+}

+

+/**

+  * @brief  Enable Underrun IT

+  * @rmtoll IER          UDRIE         LL_SPI_EnableIT_UDR

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_EnableIT_UDR(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->IER, SPI_IER_UDRIE);

+}

+

+/**

+  * @brief  Enable Overrun IT

+  * @rmtoll IER          OVRIE         LL_SPI_EnableIT_OVR

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_EnableIT_OVR(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->IER, SPI_IER_OVRIE);

+}

+

+/**

+  * @brief  Enable CRC Error IT

+  * @rmtoll IER          CRCEIE        LL_SPI_EnableIT_CRCERR

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_EnableIT_CRCERR(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->IER, SPI_IER_CRCEIE);

+}

+

+/**

+  * @brief  Enable TI Frame Format Error IT

+  * @rmtoll IER          TIFREIE       LL_SPI_EnableIT_FRE

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_EnableIT_FRE(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->IER, SPI_IER_TIFREIE);

+}

+

+/**

+  * @brief  Enable MODF IT

+  * @rmtoll IER          MODFIE        LL_SPI_EnableIT_MODF

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_EnableIT_MODF(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->IER, SPI_IER_MODFIE);

+}

+

+/**

+  * @brief  Enable TSER reload IT

+  * @rmtoll IER          TSERFIE       LL_SPI_EnableIT_TSER

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_EnableIT_TSER(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->IER, SPI_IER_TSERFIE);

+}

+

+/**

+  * @brief  Disable Rx Packet available IT

+  * @rmtoll IER          RXPIE         LL_SPI_DisableIT_RXP

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_DisableIT_RXP(SPI_TypeDef *SPIx)

+{

+  CLEAR_BIT(SPIx->IER, SPI_IER_RXPIE);

+}

+

+/**

+  * @brief  Disable Tx Packet space available IT

+  * @rmtoll IER          TXPIE         LL_SPI_DisableIT_TXP

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_DisableIT_TXP(SPI_TypeDef *SPIx)

+{

+  CLEAR_BIT(SPIx->IER, SPI_IER_TXPIE);

+}

+

+/**

+  * @brief  Disable Duplex Packet available IT

+  * @rmtoll IER          DXPIE         LL_SPI_DisableIT_DXP

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_DisableIT_DXP(SPI_TypeDef *SPIx)

+{

+  CLEAR_BIT(SPIx->IER, SPI_IER_DXPIE);

+}

+

+/**

+  * @brief  Disable End Of Transfer IT

+  * @rmtoll IER          EOTIE         LL_SPI_DisableIT_EOT

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_DisableIT_EOT(SPI_TypeDef *SPIx)

+{

+  CLEAR_BIT(SPIx->IER, SPI_IER_EOTIE);

+}

+

+/**

+  * @brief  Disable TXTF IT

+  * @rmtoll IER          TXTFIE        LL_SPI_DisableIT_TXTF

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_DisableIT_TXTF(SPI_TypeDef *SPIx)

+{

+  CLEAR_BIT(SPIx->IER, SPI_IER_TXTFIE);

+}

+

+/**

+  * @brief  Disable Underrun IT

+  * @rmtoll IER          UDRIE         LL_SPI_DisableIT_UDR

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_DisableIT_UDR(SPI_TypeDef *SPIx)

+{

+  CLEAR_BIT(SPIx->IER, SPI_IER_UDRIE);

+}

+

+/**

+  * @brief  Disable Overrun IT

+  * @rmtoll IER          OVRIE         LL_SPI_DisableIT_OVR

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_DisableIT_OVR(SPI_TypeDef *SPIx)

+{

+  CLEAR_BIT(SPIx->IER, SPI_IER_OVRIE);

+}

+

+/**

+  * @brief  Disable CRC Error IT

+  * @rmtoll IER          CRCEIE        LL_SPI_DisableIT_CRCERR

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_DisableIT_CRCERR(SPI_TypeDef *SPIx)

+{

+  CLEAR_BIT(SPIx->IER, SPI_IER_CRCEIE);

+}

+

+/**

+  * @brief  Disable TI Frame Format Error IT

+  * @rmtoll IER          TIFREIE       LL_SPI_DisableIT_FRE

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_DisableIT_FRE(SPI_TypeDef *SPIx)

+{

+  CLEAR_BIT(SPIx->IER, SPI_IER_TIFREIE);

+}

+

+/**

+  * @brief  Disable MODF IT

+  * @rmtoll IER          MODFIE        LL_SPI_DisableIT_MODF

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_DisableIT_MODF(SPI_TypeDef *SPIx)

+{

+  CLEAR_BIT(SPIx->IER, SPI_IER_MODFIE);

+}

+

+/**

+  * @brief  Disable TSER reload IT

+  * @rmtoll IER          TSERFIE       LL_SPI_DisableIT_TSER

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_DisableIT_TSER(SPI_TypeDef *SPIx)

+{

+  CLEAR_BIT(SPIx->IER, SPI_IER_TSERFIE);

+}

+

+/**

+  * @brief  Check if Rx Packet available IT is enabled

+  * @rmtoll IER          RXPIE         LL_SPI_IsEnabledIT_RXP

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->IER, SPI_IER_RXPIE) == (SPI_IER_RXPIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if Tx Packet space available IT is enabled

+  * @rmtoll IER          TXPIE         LL_SPI_IsEnabledIT_TXP

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->IER, SPI_IER_TXPIE) == (SPI_IER_TXPIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if Duplex Packet available IT is enabled

+  * @rmtoll IER          DXPIE         LL_SPI_IsEnabledIT_DXP

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->IER, SPI_IER_DXPIE) == (SPI_IER_DXPIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if End Of Transfer IT is enabled

+  * @rmtoll IER          EOTIE         LL_SPI_IsEnabledIT_EOT

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->IER, SPI_IER_EOTIE) == (SPI_IER_EOTIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if TXTF IT is enabled

+  * @rmtoll IER          TXTFIE        LL_SPI_IsEnabledIT_TXTF

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->IER, SPI_IER_TXTFIE) == (SPI_IER_TXTFIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if Underrun IT is enabled

+  * @rmtoll IER          UDRIE         LL_SPI_IsEnabledIT_UDR

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->IER, SPI_IER_UDRIE) == (SPI_IER_UDRIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if Overrun IT is enabled

+  * @rmtoll IER          OVRIE         LL_SPI_IsEnabledIT_OVR

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->IER, SPI_IER_OVRIE) == (SPI_IER_OVRIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if CRC Error IT is enabled

+  * @rmtoll IER          CRCEIE        LL_SPI_IsEnabledIT_CRCERR

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->IER, SPI_IER_CRCEIE) == (SPI_IER_CRCEIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if TI Frame Format Error IT is enabled

+  * @rmtoll IER          TIFREIE       LL_SPI_IsEnabledIT_FRE

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->IER, SPI_IER_TIFREIE) == (SPI_IER_TIFREIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if MODF IT is enabled

+  * @rmtoll IER          MODFIE        LL_SPI_IsEnabledIT_MODF

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->IER, SPI_IER_MODFIE) == (SPI_IER_MODFIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if TSER reload IT is enabled

+  * @rmtoll IER          TSERFIE       LL_SPI_IsEnabledIT_TSER

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TSER(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->IER, SPI_IER_TSERFIE) == (SPI_IER_TSERFIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup SPI_LL_EF_DMA_Management DMA Management

+  * @{

+  */

+

+/**

+  * @brief  Enable DMA Rx

+  * @rmtoll CFG1         RXDMAEN       LL_SPI_EnableDMAReq_RX

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);

+}

+

+/**

+  * @brief  Disable DMA Rx

+  * @rmtoll CFG1         RXDMAEN       LL_SPI_DisableDMAReq_RX

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx)

+{

+  CLEAR_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN);

+}

+

+/**

+  * @brief  Check if DMA Rx is enabled

+  * @rmtoll CFG1         RXDMAEN       LL_SPI_IsEnabledDMAReq_RX

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN) == (SPI_CFG1_RXDMAEN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable DMA Tx

+  * @rmtoll CFG1         TXDMAEN       LL_SPI_EnableDMAReq_TX

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);

+}

+

+/**

+  * @brief  Disable DMA Tx

+  * @rmtoll CFG1         TXDMAEN       LL_SPI_DisableDMAReq_TX

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx)

+{

+  CLEAR_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN);

+}

+

+/**

+  * @brief  Check if DMA Tx is enabled

+  * @rmtoll CFG1         TXDMAEN       LL_SPI_IsEnabledDMAReq_TX

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN) == (SPI_CFG1_TXDMAEN)) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup SPI_LL_EF_DATA_Management DATA_Management

+  * @{

+  */

+

+/**

+  * @brief  Read Data Register

+  * @rmtoll RXDR         .       LL_SPI_ReceiveData8

+  * @param  SPIx SPI Instance

+  * @retval 0..0xFF

+  */

+__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx)

+{

+  return (*((__IO uint8_t *)&SPIx->RXDR));

+}

+

+/**

+  * @brief  Read Data Register

+  * @rmtoll RXDR         .       LL_SPI_ReceiveData16

+  * @param  SPIx SPI Instance

+  * @retval 0..0xFFFF

+  */

+__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx)

+{

+  return (uint16_t)(READ_REG(SPIx->RXDR));

+}

+

+/**

+  * @brief  Read Data Register

+  * @rmtoll RXDR         .       LL_SPI_ReceiveData32

+  * @param  SPIx SPI Instance

+  * @retval  0..0xFFFFFFFF

+  */

+__STATIC_INLINE uint32_t LL_SPI_ReceiveData32(SPI_TypeDef *SPIx)

+{

+  return (*((__IO uint32_t *)&SPIx->RXDR));

+}

+

+/**

+  * @brief  Write Data Register

+  * @rmtoll TXDR         .       LL_SPI_TransmitData8

+  * @param  SPIx SPI Instance

+  * @param  TxData 0..0xFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData)

+{

+  *((__IO uint8_t *)&SPIx->TXDR) = TxData;

+}

+

+/**

+  * @brief  Write Data Register

+  * @rmtoll TXDR         .       LL_SPI_TransmitData16

+  * @param  SPIx SPI Instance

+  * @param  TxData 0..0xFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)

+{

+#if defined (__GNUC__)

+  __IO uint16_t *spitxdr = ((__IO uint16_t *)&SPIx->TXDR);

+  *spitxdr = TxData;

+#else

+  SPIx->TXDR = TxData;

+#endif

+}

+

+/**

+  * @brief  Write Data Register

+  * @rmtoll TXDR         .       LL_SPI_TransmitData32

+  * @param  SPIx SPI Instance

+  * @param  TxData 0..0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData)

+{

+  *((__IO uint32_t *)&SPIx->TXDR) = TxData;

+}

+

+/**

+  * @brief  Set polynomial for CRC calcul

+  * @rmtoll CRCPOLY      CRCPOLY       LL_SPI_SetCRCPolynomial

+  * @param  SPIx SPI Instance

+  * @param  CRCPoly 0..0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly)

+{

+  WRITE_REG(SPIx->CRCPOLY, CRCPoly);

+}

+

+/**

+  * @brief  Get polynomial for CRC calcul

+  * @rmtoll CRCPOLY      CRCPOLY       LL_SPI_GetCRCPolynomial

+  * @param  SPIx SPI Instance

+  * @retval 0..0xFFFFFFFF

+  */

+__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_REG(SPIx->CRCPOLY));

+}

+

+/**

+  * @brief  Set the underrun pattern

+  * @rmtoll UDRDR        UDRDR         LL_SPI_SetUDRPattern

+  * @param  SPIx SPI Instance

+  * @param  Pattern 0..0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_SPI_SetUDRPattern(SPI_TypeDef *SPIx, uint32_t Pattern)

+{

+  WRITE_REG(SPIx->UDRDR, Pattern);

+}

+

+/**

+  * @brief  Get the underrun pattern

+  * @rmtoll UDRDR        UDRDR         LL_SPI_GetUDRPattern

+  * @param  SPIx SPI Instance

+  * @retval 0..0xFFFFFFFF

+  */

+__STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_REG(SPIx->UDRDR));

+}

+

+/**

+  * @brief  Get Rx CRC

+  * @rmtoll RXCRCR       RXCRC         LL_SPI_GetRxCRC

+  * @param  SPIx SPI Instance

+  * @retval 0..0xFFFFFFFF

+  */

+__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_REG(SPIx->RXCRC));

+}

+

+/**

+  * @brief  Get Tx CRC

+  * @rmtoll TXCRCR       TXCRC         LL_SPI_GetTxCRC

+  * @param  SPIx SPI Instance

+  * @retval 0..0xFFFFFFFF

+  */

+__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_REG(SPIx->TXCRC));

+}

+

+/**

+  * @}

+  */

+

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions

+  * @{

+  */

+

+ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx);

+ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct);

+void        LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct);

+

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+/**

+  * @}

+  */

+

+/** @defgroup I2S_LL I2S

+  * @{

+  */

+

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/* Private macros ------------------------------------------------------------*/

+

+/* Exported types ------------------------------------------------------------*/

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup I2S_LL_ES_INIT I2S Exported Init structure

+  * @{

+  */

+

+/**

+  * @brief  I2S Init structure definition

+  */

+

+typedef struct

+{

+  uint32_t Mode;                    /*!< Specifies the I2S operating mode.

+                                         This parameter can be a value of @ref I2S_LL_EC_MODE

+

+                                         This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/

+

+  uint32_t Standard;                /*!< Specifies the standard used for the I2S communication.

+                                         This parameter can be a value of @ref I2S_LL_EC_STANDARD

+

+                                         This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/

+

+

+  uint32_t DataFormat;              /*!< Specifies the data format for the I2S communication.

+                                         This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT

+

+                                         This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/

+

+

+  uint32_t MCLKOutput;              /*!< Specifies whether the I2S MCLK output is enabled or not.

+                                         This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT

+

+                                         This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/

+

+

+  uint32_t AudioFreq;               /*!< Specifies the frequency selected for the I2S communication.

+                                         This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ

+

+                                         Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity

+                                         and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/

+

+

+  uint32_t ClockPolarity;           /*!< Specifies the idle state of the I2S clock.

+                                         This parameter can be a value of @ref I2S_LL_EC_POLARITY

+

+                                         This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/

+

+} LL_I2S_InitTypeDef;

+

+/**

+  * @}

+  */

+#endif /*USE_FULL_LL_DRIVER*/

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup I2S_LL_Exported_Constants I2S Exported Constants

+  * @{

+  */

+

+/** @defgroup I2S_LL_EC_DATA_FORMAT Data Format

+  * @{

+  */

+#define LL_I2S_DATAFORMAT_16B               (0x00000000UL)

+#define LL_I2S_DATAFORMAT_16B_EXTENDED      (SPI_I2SCFGR_CHLEN)

+#define LL_I2S_DATAFORMAT_24B               (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0)

+#define LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED  (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0 | SPI_I2SCFGR_DATFMT)

+#define LL_I2S_DATAFORMAT_32B               (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1)

+/**

+  * @}

+  */

+

+/** @defgroup I2S_LL_EC_CHANNEL_LENGTH_TYPE Type of Channel Length

+  * @{

+  */

+#define LL_I2S_SLAVE_VARIABLE_CH_LENGTH     (0x00000000UL)

+#define LL_I2S_SLAVE_FIXED_CH_LENGTH        (SPI_I2SCFGR_FIXCH)

+/**

+  * @}

+  */

+

+/** @defgroup I2S_LL_EC_POLARITY Clock Polarity

+  * @{

+  */

+#define LL_I2S_POLARITY_LOW                 (0x00000000UL)

+#define LL_I2S_POLARITY_HIGH                (SPI_I2SCFGR_CKPOL)

+/**

+  * @}

+  */

+

+/** @defgroup I2S_LL_EC_STANDARD I2S Standard

+  * @{

+  */

+#define LL_I2S_STANDARD_PHILIPS             (0x00000000UL)

+#define LL_I2S_STANDARD_MSB                 (SPI_I2SCFGR_I2SSTD_0)

+#define LL_I2S_STANDARD_LSB                 (SPI_I2SCFGR_I2SSTD_1)

+#define LL_I2S_STANDARD_PCM_SHORT           (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1)

+#define LL_I2S_STANDARD_PCM_LONG            (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC)

+/**

+  * @}

+  */

+

+/** @defgroup I2S_LL_EC_MODE Operation Mode

+  * @{

+  */

+#define LL_I2S_MODE_SLAVE_TX                (0x00000000UL)

+#define LL_I2S_MODE_SLAVE_RX                (SPI_I2SCFGR_I2SCFG_0)

+#define LL_I2S_MODE_SLAVE_FULL_DUPLEX       (SPI_I2SCFGR_I2SCFG_2)

+#define LL_I2S_MODE_MASTER_TX               (SPI_I2SCFGR_I2SCFG_1)

+#define LL_I2S_MODE_MASTER_RX               (SPI_I2SCFGR_I2SCFG_1 | SPI_I2SCFGR_I2SCFG_0)

+#define LL_I2S_MODE_MASTER_FULL_DUPLEX      (SPI_I2SCFGR_I2SCFG_2 | SPI_I2SCFGR_I2SCFG_0)

+/**

+  * @}

+  */

+

+/** @defgroup I2S_LL_EC_PRESCALER_PARITY Prescaler Factor

+  * @{

+  */

+#define LL_I2S_PRESCALER_PARITY_EVEN        (0x00000000UL)           /*!< Odd factor: Real divider value is =  I2SDIV * 2    */

+#define LL_I2S_PRESCALER_PARITY_ODD         (0x00000001UL)           /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */

+/**

+  * @}

+  */

+

+/** @defgroup I2S_LL_EC_FIFO_TH FIFO Threshold Level

+  * @{

+  */

+#define LL_I2S_FIFO_TH_01DATA               (LL_SPI_FIFO_TH_01DATA)

+#define LL_I2S_FIFO_TH_02DATA               (LL_SPI_FIFO_TH_02DATA)

+#define LL_I2S_FIFO_TH_03DATA               (LL_SPI_FIFO_TH_03DATA)

+#define LL_I2S_FIFO_TH_04DATA               (LL_SPI_FIFO_TH_04DATA)

+#define LL_I2S_FIFO_TH_05DATA               (LL_SPI_FIFO_TH_05DATA)

+#define LL_I2S_FIFO_TH_06DATA               (LL_SPI_FIFO_TH_06DATA)

+#define LL_I2S_FIFO_TH_07DATA               (LL_SPI_FIFO_TH_07DATA)

+#define LL_I2S_FIFO_TH_08DATA               (LL_SPI_FIFO_TH_08DATA)

+/**

+  * @}

+  */

+

+/** @defgroup I2S_LL_EC_BIT_ORDER Transmission Bit Order

+  * @{

+  */

+#define LL_I2S_LSB_FIRST                    (LL_SPI_LSB_FIRST)

+#define LL_I2S_MSB_FIRST                    (LL_SPI_MSB_FIRST)

+/**

+  * @}

+  */

+

+#if defined(USE_FULL_LL_DRIVER)

+

+/** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output

+  * @{

+  */

+#define LL_I2S_MCLK_OUTPUT_DISABLE          (0x00000000UL)

+#define LL_I2S_MCLK_OUTPUT_ENABLE           (SPI_I2SCFGR_MCKOE)

+/**

+  * @}

+  */

+

+/** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency

+  * @{

+  */

+

+#define LL_I2S_AUDIOFREQ_192K               192000UL       /*!< Audio Frequency configuration 192000 Hz       */

+#define LL_I2S_AUDIOFREQ_96K                96000UL        /*!< Audio Frequency configuration  96000 Hz       */

+#define LL_I2S_AUDIOFREQ_48K                48000UL        /*!< Audio Frequency configuration  48000 Hz       */

+#define LL_I2S_AUDIOFREQ_44K                44100UL        /*!< Audio Frequency configuration  44100 Hz       */

+#define LL_I2S_AUDIOFREQ_32K                32000UL        /*!< Audio Frequency configuration  32000 Hz       */

+#define LL_I2S_AUDIOFREQ_22K                22050UL        /*!< Audio Frequency configuration  22050 Hz       */

+#define LL_I2S_AUDIOFREQ_16K                16000UL        /*!< Audio Frequency configuration  16000 Hz       */

+#define LL_I2S_AUDIOFREQ_11K                11025UL        /*!< Audio Frequency configuration  11025 Hz       */

+#define LL_I2S_AUDIOFREQ_8K                 8000UL         /*!< Audio Frequency configuration   8000 Hz       */

+#define LL_I2S_AUDIOFREQ_DEFAULT            0UL            /*!< Audio Freq not specified. Register I2SDIV = 0 */

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup I2S_LL_Exported_Macros I2S Exported Macros

+  * @{

+  */

+

+/** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros

+  * @{

+  */

+

+/**

+  * @brief  Write a value in I2S register

+  * @param  __INSTANCE__ I2S Instance

+  * @param  __REG__ Register to be written

+  * @param  __VALUE__ Value to be written in the register

+  * @retval None

+  */

+#define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

+

+/**

+  * @brief  Read a value in I2S register

+  * @param  __INSTANCE__ I2S Instance

+  * @param  __REG__ Register to be read

+  * @retval Register value

+  */

+#define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+

+/* Exported functions --------------------------------------------------------*/

+

+/** @defgroup I2S_LL_Exported_Functions I2S Exported Functions

+  * @{

+  */

+

+/** @defgroup I2S_LL_EF_Configuration Configuration

+  * @{

+  */

+

+/**

+  * @brief  Set I2S Data frame format

+  * @rmtoll I2SCFGR      DATLEN        LL_I2S_SetDataFormat\n

+  *         I2SCFGR      CHLEN         LL_I2S_SetDataFormat\n

+  *         I2SCFGR      DATFMT        LL_I2S_SetDataFormat

+  * @param  SPIx SPI Handle

+  * @param  DataLength This parameter can be one of the following values:

+  *         @arg @ref LL_I2S_DATAFORMAT_16B

+  *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED

+  *         @arg @ref LL_I2S_DATAFORMAT_24B

+  *         @arg @ref LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED

+  *         @arg @ref LL_I2S_DATAFORMAT_32B

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataLength)

+{

+  MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATFMT, DataLength);

+}

+

+/**

+  * @brief  Get I2S Data frame format

+  * @rmtoll I2SCFGR      DATLEN        LL_I2S_GetDataFormat\n

+  *         I2SCFGR      CHLEN         LL_I2S_GetDataFormat\n

+  *         I2SCFGR      DATFMT        LL_I2S_GetDataFormat

+  * @param  SPIx SPI Handle

+  * @retval Return value can be one of the following values:

+  *         @arg @ref LL_I2S_DATAFORMAT_16B

+  *         @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED

+  *         @arg @ref LL_I2S_DATAFORMAT_24B

+  *         @arg @ref LL_I2S_DATAFORMAT_24B_LEFT_ALIGNED

+  *         @arg @ref LL_I2S_DATAFORMAT_32B

+  */

+__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATFMT));

+}

+

+/**

+  * @brief  Set I2S Channel Length Type

+  * @note   This feature is usefull with SLAVE only

+  * @rmtoll I2SCFGR      FIXCH        LL_I2S_SetChannelLengthType

+  * @param  SPIx SPI Handle

+  * @param  ChannelLengthType This parameter can be one of the following values:

+  *         @arg @ref LL_I2S_SLAVE_VARIABLE_CH_LENGTH

+  *         @arg @ref LL_I2S_SLAVE_FIXED_CH_LENGTH

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_SetChannelLengthType(SPI_TypeDef *SPIx, uint32_t ChannelLengthType)

+{

+  MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_FIXCH, ChannelLengthType);

+}

+

+/**

+  * @brief  Get I2S Channel Length Type

+  * @note   This feature is usefull with SLAVE only

+  * @rmtoll I2SCFGR      FIXCH         LL_I2S_GetChannelLengthType

+  * @param  SPIx SPI Handle

+  * @retval Return value can be one of the following values:

+  *         @arg @ref LL_I2S_SLAVE_VARIABLE_CH_LENGTH

+  *         @arg @ref LL_I2S_SLAVE_FIXED_CH_LENGTH

+  */

+__STATIC_INLINE uint32_t LL_I2S_GetChannelLengthType(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_FIXCH));

+}

+

+/**

+  * @brief  Invert the default polarity of WS signal

+  * @rmtoll I2SCFGR      WSINV         LL_I2S_EnableWordSelectInversion

+  * @param  SPIx SPI Handle

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_EnableWordSelectInversion(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV);

+}

+

+/**

+  * @brief  Use the default polarity of WS signal

+  * @rmtoll I2SCFGR      WSINV         LL_I2S_DisableWordSelectInversion

+  * @param  SPIx SPI Handle

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_DisableWordSelectInversion(SPI_TypeDef *SPIx)

+{

+  CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV);

+}

+

+/**

+  * @brief  Check if polarity of WS signal is inverted

+  * @rmtoll I2SCFGR      WSINV         LL_I2S_IsEnabledWordSelectInversion

+  * @param  SPIx SPI Handle

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_I2S_IsEnabledWordSelectInversion(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_WSINV) == (SPI_I2SCFGR_WSINV)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set 2S Clock Polarity

+  * @rmtoll I2SCFGR      CKPOL         LL_I2S_SetClockPolarity

+  * @param  SPIx SPI Handle

+  * @param  ClockPolarity This parameter can be one of the following values:

+  *         @arg @ref LL_I2S_POLARITY_LOW

+  *         @arg @ref LL_I2S_POLARITY_HIGH

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity)

+{

+  MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL, ClockPolarity);

+}

+

+/**

+  * @brief  Get 2S Clock Polarity

+  * @rmtoll I2SCFGR      CKPOL         LL_I2S_GetClockPolarity

+  * @param  SPIx SPI Handle

+  * @retval Return value can be one of the following values:

+  *         @arg @ref LL_I2S_POLARITY_LOW

+  *         @arg @ref LL_I2S_POLARITY_HIGH

+  */

+__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL));

+}

+

+/**

+  * @brief  Set I2S standard

+  * @rmtoll I2SCFGR      I2SSTD        LL_I2S_SetStandard\n

+  *         I2SCFGR      PCMSYNC       LL_I2S_SetStandard

+  * @param  SPIx SPI Handle

+  * @param  Standard This parameter can be one of the following values:

+  *         @arg @ref LL_I2S_STANDARD_PHILIPS

+  *         @arg @ref LL_I2S_STANDARD_MSB

+  *         @arg @ref LL_I2S_STANDARD_LSB

+  *         @arg @ref LL_I2S_STANDARD_PCM_SHORT

+  *         @arg @ref LL_I2S_STANDARD_PCM_LONG

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard)

+{

+  MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard);

+}

+

+/**

+  * @brief  Get I2S standard

+  * @rmtoll I2SCFGR      I2SSTD        LL_I2S_GetStandard\n

+  *         I2SCFGR      PCMSYNC       LL_I2S_GetStandard

+  * @param  SPIx SPI Handle

+  * @retval Return value can be one of the following values:

+  *         @arg @ref LL_I2S_STANDARD_PHILIPS

+  *         @arg @ref LL_I2S_STANDARD_MSB

+  *         @arg @ref LL_I2S_STANDARD_LSB

+  *         @arg @ref LL_I2S_STANDARD_PCM_SHORT

+  *         @arg @ref LL_I2S_STANDARD_PCM_LONG

+  */

+__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC));

+}

+

+/**

+  * @brief  Set I2S config

+  * @rmtoll I2SCFGR      I2SCFG        LL_I2S_SetTransferMode

+  * @param  SPIx SPI Handle

+  * @param  Standard This parameter can be one of the following values:

+  *         @arg @ref LL_I2S_MODE_SLAVE_TX

+  *         @arg @ref LL_I2S_MODE_SLAVE_RX

+  *         @arg @ref LL_I2S_MODE_SLAVE_FULL_DUPLEX

+  *         @arg @ref LL_I2S_MODE_MASTER_TX

+  *         @arg @ref LL_I2S_MODE_MASTER_RX

+  *         @arg @ref LL_I2S_MODE_MASTER_FULL_DUPLEX

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Standard)

+{

+  MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Standard);

+}

+

+/**

+  * @brief  Get I2S config

+  * @rmtoll I2SCFGR      I2SCFG        LL_I2S_GetTransferMode

+  * @param  SPIx SPI Handle

+  * @retval Return value can be one of the following values:

+  *         @arg @ref LL_I2S_MODE_SLAVE_TX

+  *         @arg @ref LL_I2S_MODE_SLAVE_RX

+  *         @arg @ref LL_I2S_MODE_SLAVE_FULL_DUPLEX

+  *         @arg @ref LL_I2S_MODE_MASTER_TX

+  *         @arg @ref LL_I2S_MODE_MASTER_RX

+  *         @arg @ref LL_I2S_MODE_MASTER_FULL_DUPLEX

+  */

+__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG));

+}

+

+/**

+  * @brief  Select I2S mode and Enable I2S peripheral

+  * @rmtoll I2SCFGR      I2SMOD        LL_I2S_Enable\n

+  *         CR1          SPE           LL_I2S_Enable

+  * @param  SPIx SPI Handle

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);

+  SET_BIT(SPIx->CR1, SPI_CR1_SPE);

+}

+

+/**

+  * @brief  Disable I2S peripheral and disable I2S mode

+  * @rmtoll CR1          SPE           LL_I2S_Disable\n

+  *         I2SCFGR      I2SMOD        LL_I2S_Disable

+  * @param  SPIx SPI Handle

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx)

+{

+  CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE);

+  CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD);

+}

+

+/**

+  * @brief  Swap the SDO and SDI pin

+  * @note   This configuration can not be changed when I2S is enabled.

+  * @rmtoll CFG2         IOSWP         LL_I2S_EnableIOSwap

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_EnableIOSwap(SPI_TypeDef *SPIx)

+{

+  LL_SPI_EnableIOSwap(SPIx);

+}

+

+/**

+  * @brief  Restore default function for SDO and SDI pin

+  * @note   This configuration can not be changed when I2S is enabled.

+  * @rmtoll CFG2         IOSWP         LL_I2S_DisableIOSwap

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_DisableIOSwap(SPI_TypeDef *SPIx)

+{

+  LL_SPI_DisableIOSwap(SPIx);

+}

+

+/**

+  * @brief  Check if SDO and SDI pin are swapped

+  * @rmtoll CFG2         IOSWP         LL_I2S_IsEnabledIOSwap

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIOSwap(SPI_TypeDef *SPIx)

+{

+  return LL_SPI_IsEnabledIOSwap(SPIx);

+}

+

+/**

+  * @brief  Enable GPIO control

+  * @note   This configuration can not be changed when I2S is enabled.

+  * @rmtoll CFG2         AFCNTR        LL_I2S_EnableGPIOControl

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_EnableGPIOControl(SPI_TypeDef *SPIx)

+{

+  LL_SPI_EnableGPIOControl(SPIx);

+}

+

+/**

+  * @brief  Disable GPIO control

+  * @note   This configuration can not be changed when I2S is enabled.

+  * @rmtoll CFG2         AFCNTR        LL_I2S_DisableGPIOControl

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_DisableGPIOControl(SPI_TypeDef *SPIx)

+{

+  LL_SPI_DisableGPIOControl(SPIx);

+}

+

+/**

+  * @brief  Check if GPIO control is active

+  * @rmtoll CFG2         AFCNTR        LL_I2S_IsEnabledGPIOControl

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_I2S_IsEnabledGPIOControl(SPI_TypeDef *SPIx)

+{

+  return LL_SPI_IsEnabledGPIOControl(SPIx);

+}

+

+/**

+  * @brief  Lock the AF configuration of associated IOs

+  * @note   Once this bit is set, the SPI_CFG2 register content can not be modified until a hardware reset occurs.

+  *         The reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist.

+  * @rmtoll CR1          IOLOCK        LL_SPI_EnableIOLock

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_EnableIOLock(SPI_TypeDef *SPIx)

+{

+  LL_SPI_EnableIOLock(SPIx);

+}

+

+/**

+  * @brief  Check if the the SPI_CFG2 register is locked

+  * @rmtoll CR1          IOLOCK        LL_I2S_IsEnabledIOLock

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIOLock(SPI_TypeDef *SPIx)

+{

+  return LL_SPI_IsEnabledIOLock(SPIx);

+}

+

+/**

+  * @brief  Set Transfer Bit Order

+  * @note   This configuration can not be changed when I2S is enabled.

+  * @rmtoll CFG2         LSBFRST       LL_I2S_SetTransferBitOrder

+  * @param  SPIx SPI Instance

+  * @param  BitOrder This parameter can be one of the following values:

+  *         @arg @ref LL_I2S_LSB_FIRST

+  *         @arg @ref LL_I2S_MSB_FIRST

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder)

+{

+  LL_SPI_SetTransferBitOrder(SPIx, BitOrder);

+}

+/**

+  * @brief  Get Transfer Bit Order

+  * @rmtoll CFG2         LSBFRST       LL_I2S_GetTransferBitOrder

+  * @param  SPIx SPI Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_I2S_LSB_FIRST

+  *         @arg @ref LL_I2S_MSB_FIRST

+  */

+__STATIC_INLINE uint32_t LL_I2S_GetTransferBitOrder(SPI_TypeDef *SPIx)

+{

+  return LL_SPI_GetTransferBitOrder(SPIx);

+}

+

+/**

+  * @brief  Start effective transfer on wire

+  * @rmtoll CR1          CSTART        LL_I2S_StartTransfer

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_StartTransfer(SPI_TypeDef *SPIx)

+{

+  LL_SPI_StartMasterTransfer(SPIx);

+}

+

+/**

+  * @brief  Check if there is an unfinished transfer

+  * @rmtoll CR1          CSTART        LL_I2S_IsTransferActive

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_I2S_IsActiveTransfer(SPI_TypeDef *SPIx)

+{

+  return LL_SPI_IsActiveMasterTransfer(SPIx);

+}

+

+/**

+  * @brief  Set threshold of FIFO that triggers a transfer event

+  * @note   This configuration can not be changed when I2S is enabled.

+  * @rmtoll CFG1         FTHLV         LL_I2S_SetFIFOThreshold

+  * @param  SPIx SPI Instance

+  * @param  Threshold This parameter can be one of the following values:

+  *         @arg @ref LL_I2S_FIFO_TH_01DATA

+  *         @arg @ref LL_I2S_FIFO_TH_02DATA

+  *         @arg @ref LL_I2S_FIFO_TH_03DATA

+  *         @arg @ref LL_I2S_FIFO_TH_04DATA

+  *         @arg @ref LL_I2S_FIFO_TH_05DATA

+  *         @arg @ref LL_I2S_FIFO_TH_06DATA

+  *         @arg @ref LL_I2S_FIFO_TH_07DATA

+  *         @arg @ref LL_I2S_FIFO_TH_08DATA

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold)

+{

+  LL_SPI_SetFIFOThreshold(SPIx, Threshold);

+}

+

+/**

+  * @brief  Get threshold of FIFO that triggers a transfer event

+  * @rmtoll CFG1         FTHLV         LL_I2S_GetFIFOThreshold

+  * @param  SPIx SPI Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_I2S_FIFO_TH_01DATA

+  *         @arg @ref LL_I2S_FIFO_TH_02DATA

+  *         @arg @ref LL_I2S_FIFO_TH_03DATA

+  *         @arg @ref LL_I2S_FIFO_TH_04DATA

+  *         @arg @ref LL_I2S_FIFO_TH_05DATA

+  *         @arg @ref LL_I2S_FIFO_TH_06DATA

+  *         @arg @ref LL_I2S_FIFO_TH_07DATA

+  *         @arg @ref LL_I2S_FIFO_TH_08DATA

+  */

+__STATIC_INLINE uint32_t LL_I2S_GetFIFOThreshold(SPI_TypeDef *SPIx)

+{

+  return LL_SPI_GetFIFOThreshold(SPIx);

+}

+

+/**

+  * @brief  Set I2S linear prescaler

+  * @rmtoll I2SCFGR        I2SDIV        LL_I2S_SetPrescalerLinear

+  * @param  SPIx SPI Instance

+  * @param  PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF

+  * @note   PrescalerLinear '1' is not authorized with parity LL_I2S_PRESCALER_PARITY_ODD

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint32_t PrescalerLinear)

+{

+  MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV, (PrescalerLinear << SPI_I2SCFGR_I2SDIV_Pos));

+}

+

+/**

+  * @brief  Get I2S linear prescaler

+  * @rmtoll I2SCFGR        I2SDIV        LL_I2S_GetPrescalerLinear

+  * @param  SPIx SPI Instance

+  * @retval PrescalerLinear Value between Min_Data=0x00 and Max_Data=0xFF

+  */

+__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SDIV) >> SPI_I2SCFGR_I2SDIV_Pos);

+}

+

+/**

+  * @brief  Set I2S parity prescaler

+  * @rmtoll I2SCFGR        ODD           LL_I2S_SetPrescalerParity

+  * @param  SPIx SPI Instance

+  * @param  PrescalerParity This parameter can be one of the following values:

+  *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN

+  *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity)

+{

+  MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_ODD, PrescalerParity << SPI_I2SCFGR_ODD_Pos);

+}

+

+/**

+  * @brief  Get I2S parity prescaler

+  * @rmtoll I2SCFGR        ODD           LL_I2S_GetPrescalerParity

+  * @param  SPIx SPI Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_I2S_PRESCALER_PARITY_EVEN

+  *         @arg @ref LL_I2S_PRESCALER_PARITY_ODD

+  */

+__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx)

+{

+  return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ODD) >> SPI_I2SCFGR_ODD_Pos);

+}

+

+/**

+  * @brief  Enable the Master Clock Output (Pin MCK)

+  * @rmtoll I2SCFGR      MCKOE         LL_I2S_EnableMasterClock

+  * @param  SPIx SPI Handle

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx)

+{

+  SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE);

+}

+

+/**

+  * @brief  Disable the Master Clock Ouput (Pin MCK)

+  * @rmtoll I2SCFGR      MCKOE         LL_I2S_DisableMasterClock

+  * @param  SPIx SPI Handle

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx)

+{

+  CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE);

+}

+

+/**

+  * @brief  Check if the master clock output (Pin MCK) is enabled

+  * @rmtoll I2SCFGR        MCKOE         LL_I2S_IsEnabledMasterClock

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx)

+{

+  return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_MCKOE) == (SPI_I2SCFGR_MCKOE)) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+

+/** @defgroup I2S_LL_EF_FLAG_Management FLAG_Management

+  * @{

+  */

+

+/**

+  * @brief  Check if there enough data in FIFO to read a full packet

+  * @rmtoll SR           RXP           LL_I2S_IsActiveFlag_RXP

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXP(SPI_TypeDef *SPIx)

+{

+  return LL_SPI_IsActiveFlag_RXP(SPIx);

+}

+

+/**

+  * @brief  Check if there enough space in FIFO to hold a full packet

+  * @rmtoll SR           TXP           LL_I2S_IsActiveFlag_TXP

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXP(SPI_TypeDef *SPIx)

+{

+  return LL_SPI_IsActiveFlag_TXP(SPIx);

+}

+

+/**

+  * @brief  Get Underrun error flag

+  * @rmtoll SR           UDR           LL_I2S_IsActiveFlag_UDR

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx)

+{

+  return LL_SPI_IsActiveFlag_UDR(SPIx);

+}

+

+/**

+  * @brief  Get Overrun error flag

+  * @rmtoll SR           OVR           LL_I2S_IsActiveFlag_OVR

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx)

+{

+  return LL_SPI_IsActiveFlag_OVR(SPIx);

+}

+

+/**

+  * @brief  Get TI Frame format error flag

+  * @rmtoll SR           TIFRE         LL_I2S_IsActiveFlag_FRE

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx)

+{

+  return LL_SPI_IsActiveFlag_FRE(SPIx);

+}

+

+/**

+  * @brief  Clear Underrun error flag

+  * @rmtoll IFCR         UDRC          LL_I2S_ClearFlag_UDR

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx)

+{

+  LL_SPI_ClearFlag_UDR(SPIx);

+}

+

+/**

+  * @brief  Clear Overrun error flag

+  * @rmtoll IFCR         OVRC          LL_I2S_ClearFlag_OVR

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx)

+{

+  LL_SPI_ClearFlag_OVR(SPIx);

+}

+

+/**

+  * @brief  Clear Frame format error flag

+  * @rmtoll IFCR         TIFREC        LL_I2S_ClearFlag_FRE

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx)

+{

+  LL_SPI_ClearFlag_FRE(SPIx);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup I2S_LL_EF_IT_Management IT_Management

+  * @{

+  */

+

+/**

+  * @brief  Enable Rx Packet available IT

+  * @rmtoll IER          RXPIE         LL_I2S_EnableIT_RXP

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_EnableIT_RXP(SPI_TypeDef *SPIx)

+{

+  LL_SPI_EnableIT_RXP(SPIx);

+}

+

+/**

+  * @brief  Enable Tx Packet space available IT

+  * @rmtoll IER          TXPIE         LL_I2S_EnableIT_TXP

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_EnableIT_TXP(SPI_TypeDef *SPIx)

+{

+  LL_SPI_EnableIT_TXP(SPIx);

+}

+

+/**

+  * @brief  Enable Underrun IT

+  * @rmtoll IER          UDRIE         LL_I2S_EnableIT_UDR

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_EnableIT_UDR(SPI_TypeDef *SPIx)

+{

+  LL_SPI_EnableIT_UDR(SPIx);

+}

+

+/**

+  * @brief  Enable Overrun IT

+  * @rmtoll IER          OVRIE         LL_I2S_EnableIT_OVR

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_EnableIT_OVR(SPI_TypeDef *SPIx)

+{

+  LL_SPI_EnableIT_OVR(SPIx);

+}

+

+/**

+  * @brief  Enable TI Frame Format Error IT

+  * @rmtoll IER          TIFREIE       LL_I2S_EnableIT_FRE

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_EnableIT_FRE(SPI_TypeDef *SPIx)

+{

+  LL_SPI_EnableIT_FRE(SPIx);

+}

+

+/**

+  * @brief  Disable Rx Packet available IT

+  * @rmtoll IER          RXPIE         LL_I2S_DisableIT_RXP

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_DisableIT_RXP(SPI_TypeDef *SPIx)

+{

+  LL_SPI_DisableIT_RXP(SPIx);

+}

+

+/**

+  * @brief  Disable Tx Packet space available IT

+  * @rmtoll IER          TXPIE         LL_I2S_DisableIT_TXP

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_DisableIT_TXP(SPI_TypeDef *SPIx)

+{

+  LL_SPI_DisableIT_TXP(SPIx);

+}

+

+/**

+  * @brief  Disable Underrun IT

+  * @rmtoll IER          UDRIE         LL_I2S_DisableIT_UDR

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_DisableIT_UDR(SPI_TypeDef *SPIx)

+{

+  LL_SPI_DisableIT_UDR(SPIx);

+}

+

+/**

+  * @brief  Disable Overrun IT

+  * @rmtoll IER          OVRIE         LL_I2S_DisableIT_OVR

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_DisableIT_OVR(SPI_TypeDef *SPIx)

+{

+  LL_SPI_DisableIT_OVR(SPIx);

+}

+

+/**

+  * @brief  Disable TI Frame Format Error IT

+  * @rmtoll IER          TIFREIE       LL_I2S_DisableIT_FRE

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_DisableIT_FRE(SPI_TypeDef *SPIx)

+{

+  LL_SPI_DisableIT_FRE(SPIx);

+}

+

+/**

+  * @brief  Check if Rx Packet available IT is enabled

+  * @rmtoll IER          RXPIE         LL_I2S_IsEnabledIT_RXP

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXP(SPI_TypeDef *SPIx)

+{

+  return LL_SPI_IsEnabledIT_RXP(SPIx);

+}

+

+/**

+  * @brief  Check if Tx Packet space available IT is enabled

+  * @rmtoll IER          TXPIE         LL_I2S_IsEnabledIT_TXP

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXP(SPI_TypeDef *SPIx)

+{

+  return LL_SPI_IsEnabledIT_TXP(SPIx);

+}

+

+/**

+  * @brief  Check if Underrun IT is enabled

+  * @rmtoll IER          UDRIE         LL_I2S_IsEnabledIT_UDR

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_UDR(SPI_TypeDef *SPIx)

+{

+  return LL_SPI_IsEnabledIT_UDR(SPIx);

+}

+

+/**

+  * @brief  Check if Overrun IT is enabled

+  * @rmtoll IER          OVRIE         LL_I2S_IsEnabledIT_OVR

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_OVR(SPI_TypeDef *SPIx)

+{

+  return LL_SPI_IsEnabledIT_OVR(SPIx);

+}

+

+/**

+  * @brief  Check if TI Frame Format Error IT is enabled

+  * @rmtoll IER          TIFREIE       LL_I2S_IsEnabledIT_FRE

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_FRE(SPI_TypeDef *SPIx)

+{

+  return LL_SPI_IsEnabledIT_FRE(SPIx);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup I2S_LL_EF_DMA_Management DMA_Management

+  * @{

+  */

+

+/**

+  * @brief  Enable DMA Rx

+  * @rmtoll CFG1         RXDMAEN       LL_I2S_EnableDMAReq_RX

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx)

+{

+  LL_SPI_EnableDMAReq_RX(SPIx);

+}

+

+/**

+  * @brief  Disable DMA Rx

+  * @rmtoll CFG1         RXDMAEN       LL_I2S_DisableDMAReq_RX

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx)

+{

+  LL_SPI_DisableDMAReq_RX(SPIx);

+}

+

+/**

+  * @brief  Check if DMA Rx is enabled

+  * @rmtoll CFG1         RXDMAEN       LL_I2S_IsEnabledDMAReq_RX

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx)

+{

+  return LL_SPI_IsEnabledDMAReq_RX(SPIx);

+}

+

+/**

+  * @brief  Enable DMA Tx

+  * @rmtoll CFG1         TXDMAEN       LL_I2S_EnableDMAReq_TX

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx)

+{

+  LL_SPI_EnableDMAReq_TX(SPIx);

+}

+

+/**

+  * @brief  Disable DMA Tx

+  * @rmtoll CFG1         TXDMAEN       LL_I2S_DisableDMAReq_TX

+  * @param  SPIx SPI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx)

+{

+  LL_SPI_DisableDMAReq_TX(SPIx);

+}

+

+/**

+  * @brief  Check if DMA Tx is enabled

+  * @rmtoll CFG1         TXDMAEN       LL_I2S_IsEnabledDMAReq_TX

+  * @param  SPIx SPI Instance

+  * @retval State of bit (1 or 0)

+  */

+__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx)

+{

+  return LL_SPI_IsEnabledDMAReq_TX(SPIx);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup I2S_LL_EF_DATA_Management DATA_Management

+  * @{

+  */

+

+/**

+  * @brief  Read Data Register

+  * @rmtoll RXDR         .       LL_I2S_ReceiveData16

+  * @param  SPIx SPI Instance

+  * @retval 0..0xFFFF

+  */

+__STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx)

+{

+  return LL_SPI_ReceiveData16(SPIx);

+}

+

+/**

+  * @brief  Read Data Register

+  * @rmtoll RXDR         .       LL_I2S_ReceiveData32

+  * @param  SPIx SPI Instance

+  * @retval  0..0xFFFFFFFF

+  */

+__STATIC_INLINE uint32_t LL_I2S_ReceiveData32(SPI_TypeDef *SPIx)

+{

+  return LL_SPI_ReceiveData32(SPIx);

+}

+

+/**

+  * @brief  Write Data Register

+  * @rmtoll TXDR         .       LL_I2S_TransmitData16

+  * @param  SPIx SPI Instance

+  * @param  TxData 0..0xFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData)

+{

+  LL_SPI_TransmitData16(SPIx, TxData);

+}

+

+/**

+  * @brief  Write Data Register

+  * @rmtoll TXDR         .       LL_I2S_TransmitData32

+  * @param  SPIx SPI Instance

+  * @param  TxData 0..0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_I2S_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData)

+{

+  LL_SPI_TransmitData32(SPIx, TxData);

+}

+

+/**

+  * @}

+  */

+

+

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions

+  * @{

+  */

+

+ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx);

+ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct);

+void        LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct);

+void        LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity);

+

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) || defined(SPI4) || defined(SPI5) || defined(SPI6) */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_LL_SPI_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_swpmi.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_swpmi.h
new file mode 100644
index 0000000000..0a73bc5301
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_swpmi.h
@@ -0,0 +1,1242 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_swpmi.h

+  * @author  MCD Application Team

+  * @brief   Header file of SWPMI LL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_LL_SWPMI_H

+#define STM32H7xx_LL_SWPMI_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+

+/** @defgroup SWPMI_LL SWPMI

+  * @{

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/* Private macros ------------------------------------------------------------*/

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup SWPMI_LL_Private_Macros SWPMI Private Macros

+  * @{

+  */

+/**

+  * @}

+  */

+#endif /*USE_FULL_LL_DRIVER*/

+

+/* Exported types ------------------------------------------------------------*/

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup SWPMI_LL_ES_INIT SWPMI Exported Init structure

+  * @{

+  */

+

+/**

+  * @brief  SWPMI Init structures definition

+  */

+typedef struct

+{

+  uint32_t VoltageClass;           /*!< Specifies the SWP Voltage Class.

+                                        This parameter can be a value of @ref SWPMI_LL_EC_VOLTAGE_CLASS

+

+                                        This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetVoltageClass. */

+

+  uint32_t BitRatePrescaler;       /*!< Specifies the SWPMI bitrate prescaler.

+                                        This parameter must be a number between Min_Data=0 and Max_Data=255U.

+

+                                        The value can be calculated thanks to helper macro @ref __LL_SWPMI_CALC_BITRATE_PRESCALER

+

+                                        This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetBitRatePrescaler. */

+

+  uint32_t TxBufferingMode;        /*!< Specifies the transmission buffering mode.

+                                        This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_TX

+

+                                        This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetTransmissionMode. */

+

+  uint32_t RxBufferingMode;        /*!< Specifies the reception buffering mode.

+                                        This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_RX

+

+                                        This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetReceptionMode. */

+} LL_SWPMI_InitTypeDef;

+

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup SWPMI_LL_Exported_Constants SWPMI Exported Constants

+  * @{

+  */

+

+/** @defgroup SWPMI_LL_EC_CLEAR_FLAG Clear Flags Defines

+  * @brief    Flags defines which can be used with LL_SWPMI_WriteReg function

+  * @{

+  */

+#define LL_SWPMI_ICR_CRXBFF                SWPMI_ICR_CRXBFF  /*!< Clear receive buffer full flag     */

+#define LL_SWPMI_ICR_CTXBEF                SWPMI_ICR_CTXBEF  /*!< Clear transmit buffer empty flag   */

+#define LL_SWPMI_ICR_CRXBERF               SWPMI_ICR_CRXBERF /*!< Clear receive CRC error flag       */

+#define LL_SWPMI_ICR_CRXOVRF               SWPMI_ICR_CRXOVRF /*!< Clear receive overrun error flag   */

+#define LL_SWPMI_ICR_CTXUNRF               SWPMI_ICR_CTXUNRF /*!< Clear transmit underrun error flag */

+#define LL_SWPMI_ICR_CTCF                  SWPMI_ICR_CTCF    /*!< Clear transfer complete flag       */

+#define LL_SWPMI_ICR_CSRF                  SWPMI_ICR_CSRF    /*!< Clear slave resume flag            */

+/**

+  * @}

+  */

+

+/** @defgroup SWPMI_LL_EC_GET_FLAG Get Flags Defines

+  * @brief    Flags defines which can be used with LL_SWPMI_ReadReg function

+  * @{

+  */

+#define LL_SWPMI_ISR_RXBFF                 SWPMI_ISR_RXBFF   /*!< Receive buffer full flag           */

+#define LL_SWPMI_ISR_TXBEF                 SWPMI_ISR_TXBEF   /*!< Transmit buffer empty flag         */

+#define LL_SWPMI_ISR_RXBERF                SWPMI_ISR_RXBERF  /*!< Receive CRC error flag             */

+#define LL_SWPMI_ISR_RXOVRF                SWPMI_ISR_RXOVRF  /*!< Receive overrun error flag         */

+#define LL_SWPMI_ISR_TXUNRF                SWPMI_ISR_TXUNRF  /*!< Transmit underrun error flag       */

+#define LL_SWPMI_ISR_RXNE                  SWPMI_ISR_RXNE    /*!< Receive data register not empty    */

+#define LL_SWPMI_ISR_TXE                   SWPMI_ISR_TXE     /*!< Transmit data register empty       */

+#define LL_SWPMI_ISR_TCF                   SWPMI_ISR_TCF     /*!< Transfer complete flag             */

+#define LL_SWPMI_ISR_SRF                   SWPMI_ISR_SRF     /*!< Slave resume flag                  */

+#define LL_SWPMI_ISR_SUSP                  SWPMI_ISR_SUSP    /*!< SUSPEND flag                       */

+#define LL_SWPMI_ISR_DEACTF                SWPMI_ISR_DEACTF  /*!< DEACTIVATED flag                   */

+/**

+  * @}

+  */

+

+/** @defgroup SWPMI_LL_EC_IT IT Defines

+  * @brief    IT defines which can be used with LL_SWPMI_ReadReg and  LL_SWPMI_WriteReg functions

+  * @{

+  */

+#define LL_SWPMI_IER_SRIE                  SWPMI_IER_SRIE    /*!< Slave resume interrupt enable            */

+#define LL_SWPMI_IER_TCIE                  SWPMI_IER_TCIE    /*!< Transmit complete interrupt enable       */

+#define LL_SWPMI_IER_TIE                   SWPMI_IER_TIE     /*!< Transmit interrupt enable                */

+#define LL_SWPMI_IER_RIE                   SWPMI_IER_RIE     /*!< Receive interrupt enable                 */

+#define LL_SWPMI_IER_TXUNRIE               SWPMI_IER_TXUNRIE /*!< Transmit underrun error interrupt enable */

+#define LL_SWPMI_IER_RXOVRIE               SWPMI_IER_RXOVRIE /*!< Receive overrun error interrupt enable   */

+#define LL_SWPMI_IER_RXBERIE               SWPMI_IER_RXBERIE /*!< Receive CRC error interrupt enable       */

+#define LL_SWPMI_IER_TXBEIE                SWPMI_IER_TXBEIE  /*!< Transmit buffer empty interrupt enable   */

+#define LL_SWPMI_IER_RXBFIE                SWPMI_IER_RXBFIE  /*!< Receive buffer full interrupt enable     */

+/**

+  * @}

+  */

+

+/** @defgroup SWPMI_LL_EC_SW_BUFFER_RX SW BUFFER RX

+  * @{

+  */

+#define LL_SWPMI_SW_BUFFER_RX_SINGLE ((uint32_t)0x00000000)  /*!< Single software buffer mode for reception */

+#define LL_SWPMI_SW_BUFFER_RX_MULTI  SWPMI_CR_RXMODE         /*!< Multi software buffermode for reception   */

+/**

+  * @}

+  */

+

+/** @defgroup SWPMI_LL_EC_SW_BUFFER_TX SW BUFFER TX

+  * @{

+  */

+#define LL_SWPMI_SW_BUFFER_TX_SINGLE ((uint32_t)0x00000000)  /*!< Single software buffer mode for transmission */

+#define LL_SWPMI_SW_BUFFER_TX_MULTI  SWPMI_CR_TXMODE         /*!< Multi software buffermode for transmission   */

+/**

+  * @}

+  */

+

+/** @defgroup SWPMI_LL_EC_VOLTAGE_CLASS VOLTAGE CLASS

+  * @{

+  */

+#define LL_SWPMI_VOLTAGE_CLASS_C     ((uint32_t)0x00000000)  /*!< SWPMI_IO uses directly VDD voltage to operate in class C          */

+#define LL_SWPMI_VOLTAGE_CLASS_B     SWPMI_OR_CLASS          /*!< SWPMI_IO uses an internal voltage regulator to operate in class B */

+/**

+  * @}

+  */

+

+/** @defgroup SWPMI_LL_EC_DMA_REG_DATA DMA register data

+  * @{

+  */

+#define LL_SWPMI_DMA_REG_DATA_TRANSMIT     (uint32_t)0       /*!< Get address of data register used for transmission */

+#define LL_SWPMI_DMA_REG_DATA_RECEIVE      (uint32_t)1       /*!< Get address of data register used for reception    */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup SWPMI_LL_Exported_Macros SWPMI Exported Macros

+  * @{

+  */

+

+/** @defgroup SWPMI_LL_EM_WRITE_READ Common Write and read registers Macros

+  * @{

+  */

+

+/**

+  * @brief  Write a value in SWPMI register

+  * @param  __INSTANCE__ SWPMI Instance

+  * @param  __REG__ Register to be written

+  * @param  __VALUE__ Value to be written in the register

+  * @retval None

+  */

+#define LL_SWPMI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

+

+/**

+  * @brief  Read a value in SWPMI register

+  * @param  __INSTANCE__ SWPMI Instance

+  * @param  __REG__ Register to be read

+  * @retval Register value

+  */

+#define LL_SWPMI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)

+/**

+  * @}

+  */

+

+/** @defgroup SWPMI_LL_EM_BitRate Bit rate calculation helper Macros

+  * @{

+  */

+

+/**

+  * @brief  Helper macro to calculate bit rate value to set in BRR register (@ref LL_SWPMI_SetBitRatePrescaler function)

+  * @note ex: @ref __LL_SWPMI_CALC_BITRATE_PRESCALER(2000000, 80000000);

+  * @param  __FSWP__ Within the following range: from 100 Kbit/s up to 2Mbit/s (in bit/s)

+  * @param  __FSWPCLK__ PCLK or HSI frequency (in Hz)

+  * @retval Bitrate prescaler (BRR register)

+  */

+#define __LL_SWPMI_CALC_BITRATE_PRESCALER(__FSWP__, __FSWPCLK__)   ((uint32_t)(((__FSWPCLK__) / ((__FSWP__) * 4)) - 1))

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup SWPMI_LL_Exported_Functions SWPMI Exported Functions

+  * @{

+  */

+

+/** @defgroup SWPMI_LL_EF_Configuration Configuration

+  * @{

+  */

+

+/**

+  * @brief  Set Reception buffering mode

+  * @note   If Multi software buffer mode is chosen, RXDMA bits must also be set.

+  * @rmtoll CR           RXMODE        LL_SWPMI_SetReceptionMode

+  * @param  SWPMIx SWPMI Instance

+  * @param  RxBufferingMode This parameter can be one of the following values:

+  *         @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE

+  *         @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_SetReceptionMode(SWPMI_TypeDef *SWPMIx, uint32_t RxBufferingMode)

+{

+  MODIFY_REG(SWPMIx->CR, SWPMI_CR_RXMODE, RxBufferingMode);

+}

+

+/**

+  * @brief  Get Reception buffering mode

+  * @rmtoll CR           RXMODE        LL_SWPMI_GetReceptionMode

+  * @param  SWPMIx SWPMI Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE

+  *         @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_GetReceptionMode(SWPMI_TypeDef *SWPMIx)

+{

+  return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_RXMODE));

+}

+

+/**

+  * @brief  Set Transmission buffering mode

+  * @note   If Multi software buffer mode is chosen, TXDMA bits must also be set.

+  * @rmtoll CR           TXMODE        LL_SWPMI_SetTransmissionMode

+  * @param  SWPMIx SWPMI Instance

+  * @param  TxBufferingMode This parameter can be one of the following values:

+  *         @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE

+  *         @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_SetTransmissionMode(SWPMI_TypeDef *SWPMIx, uint32_t TxBufferingMode)

+{

+  MODIFY_REG(SWPMIx->CR, SWPMI_CR_TXMODE, TxBufferingMode);

+}

+

+/**

+  * @brief  Get Transmission buffering mode

+  * @rmtoll CR           TXMODE        LL_SWPMI_GetTransmissionMode

+  * @param  SWPMIx SWPMI Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE

+  *         @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_GetTransmissionMode(SWPMI_TypeDef *SWPMIx)

+{

+  return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_TXMODE));

+}

+

+/**

+  * @brief  Enable loopback mode

+  * @rmtoll CR           LPBK          LL_SWPMI_EnableLoopback

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_EnableLoopback(SWPMI_TypeDef *SWPMIx)

+{

+  SET_BIT(SWPMIx->CR, SWPMI_CR_LPBK);

+}

+

+/**

+  * @brief  Disable loopback mode

+  * @rmtoll CR           LPBK          LL_SWPMI_DisableLoopback

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_DisableLoopback(SWPMI_TypeDef *SWPMIx)

+{

+  CLEAR_BIT(SWPMIx->CR, SWPMI_CR_LPBK);

+}

+

+/**

+  * @brief  Enable SWPMI transceiver

+  * @note   SWPMI_IO pin is controlled by SWPMI

+  * @rmtoll CR           SWPEN          LL_SWPMI_EnableTransceiver

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_EnableTransceiver(SWPMI_TypeDef *SWPMIx)

+{

+  SET_BIT(SWPMIx->CR, SWPMI_CR_SWPEN);

+}

+

+/**

+  * @brief  Disable SWPMI transceiver

+  * @note   SWPMI_IO pin is controlled by GPIO controller

+  * @rmtoll CR           SWPEN          LL_SWPMI_DisableTransceiver

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_DisableTransceiver(SWPMI_TypeDef *SWPMIx)

+{

+  CLEAR_BIT(SWPMIx->CR, SWPMI_CR_SWPEN);

+}

+

+/**

+  * @brief  Check if SWPMI transceiver is enabled

+  * @rmtoll CR           SWPEN         LL_SWPMI_IsEnabledTransceiver

+  * @param  SWPMIx SWPMI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledTransceiver(SWPMI_TypeDef *SWPMIx)

+{

+  return ((READ_BIT(SWPMIx->CR, SWPMI_CR_SWPEN) == (SWPMI_CR_SWPEN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Activate Single wire protocol bus (SUSPENDED or ACTIVATED state)

+  * @note   SWP bus stays in the ACTIVATED state as long as there is a communication

+  *         with the slave, either in transmission or in reception. The SWP bus switches back

+  *         to the SUSPENDED state as soon as there is no more transmission or reception

+  *         activity, after 7 idle bits.

+  * @rmtoll CR           SWPACT        LL_SWPMI_Activate

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_Activate(SWPMI_TypeDef *SWPMIx)

+{

+  /* In order to activate SWP again, the software must clear DEACT bit*/

+  CLEAR_BIT(SWPMIx->CR, SWPMI_CR_DEACT);

+

+  /* Set SWACT bit */

+  SET_BIT(SWPMIx->CR, SWPMI_CR_SWPACT);

+}

+

+/**

+  * @brief  Check if Single wire protocol bus is in ACTIVATED state.

+  * @rmtoll CR           SWPACT        LL_SWPMI_Activate

+  * @param  SWPMIx SWPMI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_IsActivated(SWPMI_TypeDef *SWPMIx)

+{

+  return ((READ_BIT(SWPMIx->CR, SWPMI_CR_SWPACT) == (SWPMI_CR_SWPACT)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Deactivate immediately Single wire protocol bus (immediate transition to

+  *         DEACTIVATED state)

+  * @rmtoll CR           SWPACT        LL_SWPMI_Deactivate

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_Deactivate(SWPMI_TypeDef *SWPMIx)

+{

+  CLEAR_BIT(SWPMIx->CR, SWPMI_CR_SWPACT);

+}

+

+/**

+  * @brief  Request a deactivation of Single wire protocol bus (request to go in DEACTIVATED

+  *         state if no resume from slave)

+  * @rmtoll CR           DEACT         LL_SWPMI_RequestDeactivation

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_RequestDeactivation(SWPMI_TypeDef *SWPMIx)

+{

+  SET_BIT(SWPMIx->CR, SWPMI_CR_DEACT);

+}

+

+/**

+  * @brief  Set Bitrate prescaler SWPMI_freq = SWPMI_clk / (((BitRate) + 1)  * 4)

+  * @rmtoll BRR          BR            LL_SWPMI_SetBitRatePrescaler

+  * @param  SWPMIx SWPMI Instance

+  * @param  BitRatePrescaler A number between Min_Data=0 and Max_Data=255U

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_SetBitRatePrescaler(SWPMI_TypeDef *SWPMIx, uint32_t BitRatePrescaler)

+{

+  WRITE_REG(SWPMIx->BRR, BitRatePrescaler);

+}

+

+/**

+  * @brief  Get Bitrate prescaler

+  * @rmtoll BRR          BR            LL_SWPMI_GetBitRatePrescaler

+  * @param  SWPMIx SWPMI Instance

+  * @retval A number between Min_Data=0 and Max_Data=255U

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_GetBitRatePrescaler(SWPMI_TypeDef *SWPMIx)

+{

+  return (uint32_t)(READ_BIT(SWPMIx->BRR, SWPMI_BRR_BR));

+}

+

+/**

+  * @brief  Set SWP Voltage Class

+  * @rmtoll OR           CLASS         LL_SWPMI_SetVoltageClass

+  * @param  SWPMIx SWPMI Instance

+  * @param  VoltageClass This parameter can be one of the following values:

+  *         @arg @ref LL_SWPMI_VOLTAGE_CLASS_C

+  *         @arg @ref LL_SWPMI_VOLTAGE_CLASS_B

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_SetVoltageClass(SWPMI_TypeDef *SWPMIx, uint32_t VoltageClass)

+{

+  MODIFY_REG(SWPMIx->OR, SWPMI_OR_CLASS, VoltageClass);

+}

+

+/**

+  * @brief  Get SWP Voltage Class

+  * @rmtoll OR           CLASS         LL_SWPMI_GetVoltageClass

+  * @param  SWPMIx SWPMI Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_SWPMI_VOLTAGE_CLASS_C

+  *         @arg @ref LL_SWPMI_VOLTAGE_CLASS_B

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass(SWPMI_TypeDef *SWPMIx)

+{

+  return (uint32_t)(READ_BIT(SWPMIx->OR, SWPMI_OR_CLASS));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup SWPMI_LL_EF_FLAG_Management FLAG_Management

+  * @{

+  */

+

+/**

+  * @brief  Check if the last word of the frame under reception has arrived in SWPMI_RDR.

+  * @rmtoll ISR          RXBFF         LL_SWPMI_IsActiveFlag_RXBF

+  * @param  SWPMIx SWPMI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(SWPMI_TypeDef *SWPMIx)

+{

+  return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBFF) == (SWPMI_ISR_RXBFF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if Frame transmission buffer has been emptied

+  * @rmtoll ISR          TXBEF         LL_SWPMI_IsActiveFlag_TXBE

+  * @param  SWPMIx SWPMI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(SWPMI_TypeDef *SWPMIx)

+{

+  return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXBEF) == (SWPMI_ISR_TXBEF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if CRC error in reception has been detected

+  * @rmtoll ISR          RXBERF        LL_SWPMI_IsActiveFlag_RXBER

+  * @param  SWPMIx SWPMI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(SWPMI_TypeDef *SWPMIx)

+{

+  return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBERF) == (SWPMI_ISR_RXBERF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if Overrun in reception has been detected

+  * @rmtoll ISR          RXOVRF        LL_SWPMI_IsActiveFlag_RXOVR

+  * @param  SWPMIx SWPMI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(SWPMI_TypeDef *SWPMIx)

+{

+  return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXOVRF) == (SWPMI_ISR_RXOVRF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if underrun error in transmission has been detected

+  * @rmtoll ISR          TXUNRF        LL_SWPMI_IsActiveFlag_TXUNR

+  * @param  SWPMIx SWPMI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(SWPMI_TypeDef *SWPMIx)

+{

+  return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXUNRF) == (SWPMI_ISR_TXUNRF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if Receive data register not empty (it means that Received data is ready

+  *         to be read in the SWPMI_RDR register)

+  * @rmtoll ISR          RXNE          LL_SWPMI_IsActiveFlag_RXNE

+  * @param  SWPMIx SWPMI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(SWPMI_TypeDef *SWPMIx)

+{

+  return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXNE) == (SWPMI_ISR_RXNE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if Transmit data register is empty (it means that Data written in transmit

+  *         data register SWPMI_TDR has been transmitted and SWPMI_TDR can be written to again)

+  * @rmtoll ISR          TXE           LL_SWPMI_IsActiveFlag_TXE

+  * @param  SWPMIx SWPMI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(SWPMI_TypeDef *SWPMIx)

+{

+  return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXE) == (SWPMI_ISR_TXE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if Both transmission and reception are completed and SWP is switched to

+  *         the SUSPENDED state

+  * @rmtoll ISR          TCF           LL_SWPMI_IsActiveFlag_TC

+  * @param  SWPMIx SWPMI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(SWPMI_TypeDef *SWPMIx)

+{

+  return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_TCF) == (SWPMI_ISR_TCF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if a Resume by slave state has been detected during the SWP bus SUSPENDED

+  *         state

+  * @rmtoll ISR          SRF           LL_SWPMI_IsActiveFlag_SR

+  * @param  SWPMIx SWPMI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(SWPMI_TypeDef *SWPMIx)

+{

+  return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_SRF) == (SWPMI_ISR_SRF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if SWP bus is in SUSPENDED or DEACTIVATED state

+  * @rmtoll ISR          SUSP          LL_SWPMI_IsActiveFlag_SUSP

+  * @param  SWPMIx SWPMI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(SWPMI_TypeDef *SWPMIx)

+{

+  return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_SUSP) == (SWPMI_ISR_SUSP)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if SWP bus is in DEACTIVATED state

+  * @rmtoll ISR          DEACTF        LL_SWPMI_IsActiveFlag_DEACT

+  * @param  SWPMIx SWPMI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT(SWPMI_TypeDef *SWPMIx)

+{

+  return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_DEACTF) == (SWPMI_ISR_DEACTF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if SWPMI transceiver is ready

+  * @rmtoll ISR          RDYF        LL_SWPMI_IsActiveFlag_RDYF

+  * @param  SWPMIx SWPMI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RDYF(SWPMI_TypeDef *SWPMIx)

+{

+  return ((READ_BIT(SWPMIx->ISR, SWPMI_ISR_RDYF) == (SWPMI_ISR_RDYF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear receive buffer full flag

+  * @rmtoll ICR          CRXBFF        LL_SWPMI_ClearFlag_RXBF

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_ClearFlag_RXBF(SWPMI_TypeDef *SWPMIx)

+{

+  WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBFF);

+}

+

+/**

+  * @brief  Clear transmit buffer empty flag

+  * @rmtoll ICR          CTXBEF        LL_SWPMI_ClearFlag_TXBE

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_ClearFlag_TXBE(SWPMI_TypeDef *SWPMIx)

+{

+  WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXBEF);

+}

+

+/**

+  * @brief  Clear receive CRC error flag

+  * @rmtoll ICR          CRXBERF       LL_SWPMI_ClearFlag_RXBER

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_ClearFlag_RXBER(SWPMI_TypeDef *SWPMIx)

+{

+  WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBERF);

+}

+

+/**

+  * @brief  Clear receive overrun error flag

+  * @rmtoll ICR          CRXOVRF       LL_SWPMI_ClearFlag_RXOVR

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_ClearFlag_RXOVR(SWPMI_TypeDef *SWPMIx)

+{

+  WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXOVRF);

+}

+

+/**

+  * @brief  Clear transmit underrun error flag

+  * @rmtoll ICR          CTXUNRF       LL_SWPMI_ClearFlag_TXUNR

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_ClearFlag_TXUNR(SWPMI_TypeDef *SWPMIx)

+{

+  WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXUNRF);

+}

+

+/**

+  * @brief  Clear transfer complete flag

+  * @rmtoll ICR          CTCF          LL_SWPMI_ClearFlag_TC

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_ClearFlag_TC(SWPMI_TypeDef *SWPMIx)

+{

+  WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTCF);

+}

+

+/**

+  * @brief  Clear slave resume flag

+  * @rmtoll ICR          CSRF          LL_SWPMI_ClearFlag_SR

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_ClearFlag_SR(SWPMI_TypeDef *SWPMIx)

+{

+  WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CSRF);

+}

+

+/**

+  * @brief  Clear SWPMI transceiver ready flag

+  * @rmtoll ISR          CRDYF        LL_SWPMI_ClearFlag_RDY

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_ClearFlag_RDY(SWPMI_TypeDef *SWPMIx)

+{

+  WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRDYF);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup SWPMI_LL_EF_IT_Management IT_Management

+  * @{

+  */

+

+/**

+  * @brief  Enable SWPMI transceiver ready interrupt

+  * @rmtoll IER          RDYIE         LL_SWPMI_EnableIT_RDY

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_EnableIT_RDY(SWPMI_TypeDef *SWPMIx)

+{

+  SET_BIT(SWPMIx->IER, SWPMI_IER_RDYIE);

+}

+

+/**

+  * @brief  Enable Slave resume interrupt

+  * @rmtoll IER          SRIE          LL_SWPMI_EnableIT_SR

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_EnableIT_SR(SWPMI_TypeDef *SWPMIx)

+{

+  SET_BIT(SWPMIx->IER, SWPMI_IER_SRIE);

+}

+

+/**

+  * @brief  Enable Transmit complete interrupt

+  * @rmtoll IER          TCIE          LL_SWPMI_EnableIT_TC

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_EnableIT_TC(SWPMI_TypeDef *SWPMIx)

+{

+  SET_BIT(SWPMIx->IER, SWPMI_IER_TCIE);

+}

+

+/**

+  * @brief  Enable Transmit interrupt

+  * @rmtoll IER          TIE           LL_SWPMI_EnableIT_TX

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_EnableIT_TX(SWPMI_TypeDef *SWPMIx)

+{

+  SET_BIT(SWPMIx->IER, SWPMI_IER_TIE);

+}

+

+/**

+  * @brief  Enable Receive interrupt

+  * @rmtoll IER          RIE           LL_SWPMI_EnableIT_RX

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_EnableIT_RX(SWPMI_TypeDef *SWPMIx)

+{

+  SET_BIT(SWPMIx->IER, SWPMI_IER_RIE);

+}

+

+/**

+  * @brief  Enable Transmit underrun error interrupt

+  * @rmtoll IER          TXUNRIE       LL_SWPMI_EnableIT_TXUNR

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_EnableIT_TXUNR(SWPMI_TypeDef *SWPMIx)

+{

+  SET_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE);

+}

+

+/**

+  * @brief  Enable Receive overrun error interrupt

+  * @rmtoll IER          RXOVRIE       LL_SWPMI_EnableIT_RXOVR

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_EnableIT_RXOVR(SWPMI_TypeDef *SWPMIx)

+{

+  SET_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE);

+}

+

+/**

+  * @brief  Enable Receive CRC error interrupt

+  * @rmtoll IER          RXBERIE       LL_SWPMI_EnableIT_RXBER

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_EnableIT_RXBER(SWPMI_TypeDef *SWPMIx)

+{

+  SET_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE);

+}

+

+/**

+  * @brief  Enable Transmit buffer empty interrupt

+  * @rmtoll IER          TXBEIE        LL_SWPMI_EnableIT_TXBE

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_EnableIT_TXBE(SWPMI_TypeDef *SWPMIx)

+{

+  SET_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE);

+}

+

+/**

+  * @brief  Enable Receive buffer full interrupt

+  * @rmtoll IER          RXBFIE        LL_SWPMI_EnableIT_RXBF

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_EnableIT_RXBF(SWPMI_TypeDef *SWPMIx)

+{

+  SET_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE);

+}

+

+/**

+  * @brief  Disable SWPMI transceiver ready interrupt

+  * @rmtoll IER          RDYIE         LL_SWPMI_DisableIT_RDY

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_DisableIT_RDY(SWPMI_TypeDef *SWPMIx)

+{

+  CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RDYIE);

+}

+

+/**

+  * @brief  Disable Slave resume interrupt

+  * @rmtoll IER          SRIE          LL_SWPMI_DisableIT_SR

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_DisableIT_SR(SWPMI_TypeDef *SWPMIx)

+{

+  CLEAR_BIT(SWPMIx->IER, SWPMI_IER_SRIE);

+}

+

+/**

+  * @brief  Disable Transmit complete interrupt

+  * @rmtoll IER          TCIE          LL_SWPMI_DisableIT_TC

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_DisableIT_TC(SWPMI_TypeDef *SWPMIx)

+{

+  CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TCIE);

+}

+

+/**

+  * @brief  Disable Transmit interrupt

+  * @rmtoll IER          TIE           LL_SWPMI_DisableIT_TX

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_DisableIT_TX(SWPMI_TypeDef *SWPMIx)

+{

+  CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TIE);

+}

+

+/**

+  * @brief  Disable Receive interrupt

+  * @rmtoll IER          RIE           LL_SWPMI_DisableIT_RX

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_DisableIT_RX(SWPMI_TypeDef *SWPMIx)

+{

+  CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RIE);

+}

+

+/**

+  * @brief  Disable Transmit underrun error interrupt

+  * @rmtoll IER          TXUNRIE       LL_SWPMI_DisableIT_TXUNR

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_DisableIT_TXUNR(SWPMI_TypeDef *SWPMIx)

+{

+  CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE);

+}

+

+/**

+  * @brief  Disable Receive overrun error interrupt

+  * @rmtoll IER          RXOVRIE       LL_SWPMI_DisableIT_RXOVR

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_DisableIT_RXOVR(SWPMI_TypeDef *SWPMIx)

+{

+  CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE);

+}

+

+/**

+  * @brief  Disable Receive CRC error interrupt

+  * @rmtoll IER          RXBERIE       LL_SWPMI_DisableIT_RXBER

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_DisableIT_RXBER(SWPMI_TypeDef *SWPMIx)

+{

+  CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE);

+}

+

+/**

+  * @brief  Disable Transmit buffer empty interrupt

+  * @rmtoll IER          TXBEIE        LL_SWPMI_DisableIT_TXBE

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_DisableIT_TXBE(SWPMI_TypeDef *SWPMIx)

+{

+  CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE);

+}

+

+/**

+  * @brief  Disable Receive buffer full interrupt

+  * @rmtoll IER          RXBFIE        LL_SWPMI_DisableIT_RXBF

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_DisableIT_RXBF(SWPMI_TypeDef *SWPMIx)

+{

+  CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE);

+}

+

+/**

+  * @brief  Check if SWPMI transceiver ready interrupt is enabled

+  * @rmtoll IER          RDYIE         LL_SWPMI_IsEnabledIT_RDY

+  * @param  SWPMIx SWPMI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RDY(SWPMI_TypeDef *SWPMIx)

+{

+  return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RDYIE) == (SWPMI_IER_RDYIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if Slave resume interrupt is enabled

+  * @rmtoll IER          SRIE          LL_SWPMI_IsEnabledIT_SR

+  * @param  SWPMIx SWPMI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(SWPMI_TypeDef *SWPMIx)

+{

+  return ((READ_BIT(SWPMIx->IER, SWPMI_IER_SRIE) == (SWPMI_IER_SRIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if Transmit complete interrupt is enabled

+  * @rmtoll IER          TCIE          LL_SWPMI_IsEnabledIT_TC

+  * @param  SWPMIx SWPMI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(SWPMI_TypeDef *SWPMIx)

+{

+  return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TCIE) == (SWPMI_IER_TCIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if Transmit interrupt is enabled

+  * @rmtoll IER          TIE           LL_SWPMI_IsEnabledIT_TX

+  * @param  SWPMIx SWPMI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(SWPMI_TypeDef *SWPMIx)

+{

+  return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TIE) == (SWPMI_IER_TIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if Receive interrupt is enabled

+  * @rmtoll IER          RIE           LL_SWPMI_IsEnabledIT_RX

+  * @param  SWPMIx SWPMI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(SWPMI_TypeDef *SWPMIx)

+{

+  return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RIE) == (SWPMI_IER_RIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if Transmit underrun error interrupt is enabled

+  * @rmtoll IER          TXUNRIE       LL_SWPMI_IsEnabledIT_TXUNR

+  * @param  SWPMIx SWPMI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(SWPMI_TypeDef *SWPMIx)

+{

+  return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE) == (SWPMI_IER_TXUNRIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if Receive overrun error interrupt is enabled

+  * @rmtoll IER          RXOVRIE       LL_SWPMI_IsEnabledIT_RXOVR

+  * @param  SWPMIx SWPMI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(SWPMI_TypeDef *SWPMIx)

+{

+  return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE) == (SWPMI_IER_RXOVRIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if Receive CRC error interrupt is enabled

+  * @rmtoll IER          RXBERIE       LL_SWPMI_IsEnabledIT_RXBER

+  * @param  SWPMIx SWPMI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(SWPMI_TypeDef *SWPMIx)

+{

+  return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE) == (SWPMI_IER_RXBERIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if Transmit buffer empty interrupt is enabled

+  * @rmtoll IER          TXBEIE        LL_SWPMI_IsEnabledIT_TXBE

+  * @param  SWPMIx SWPMI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(SWPMI_TypeDef *SWPMIx)

+{

+  return ((READ_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE) == (SWPMI_IER_TXBEIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if Receive buffer full interrupt is enabled

+  * @rmtoll IER          RXBFIE        LL_SWPMI_IsEnabledIT_RXBF

+  * @param  SWPMIx SWPMI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBF(SWPMI_TypeDef *SWPMIx)

+{

+  return ((READ_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE) == (SWPMI_IER_RXBFIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup SWPMI_LL_EF_DMA_Management DMA_Management

+  * @{

+  */

+

+/**

+  * @brief  Enable DMA mode for reception

+  * @rmtoll CR           RXDMA         LL_SWPMI_EnableDMAReq_RX

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_EnableDMAReq_RX(SWPMI_TypeDef *SWPMIx)

+{

+  SET_BIT(SWPMIx->CR, SWPMI_CR_RXDMA);

+}

+

+/**

+  * @brief  Disable DMA mode for reception

+  * @rmtoll CR           RXDMA         LL_SWPMI_DisableDMAReq_RX

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_DisableDMAReq_RX(SWPMI_TypeDef *SWPMIx)

+{

+  CLEAR_BIT(SWPMIx->CR, SWPMI_CR_RXDMA);

+}

+

+/**

+  * @brief  Check if DMA mode for reception is enabled

+  * @rmtoll CR           RXDMA         LL_SWPMI_IsEnabledDMAReq_RX

+  * @param  SWPMIx SWPMI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_RX(SWPMI_TypeDef *SWPMIx)

+{

+  return ((READ_BIT(SWPMIx->CR, SWPMI_CR_RXDMA) == (SWPMI_CR_RXDMA)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable DMA mode for transmission

+  * @rmtoll CR           TXDMA         LL_SWPMI_EnableDMAReq_TX

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_EnableDMAReq_TX(SWPMI_TypeDef *SWPMIx)

+{

+  SET_BIT(SWPMIx->CR, SWPMI_CR_TXDMA);

+}

+

+/**

+  * @brief  Disable DMA mode for transmission

+  * @rmtoll CR           TXDMA         LL_SWPMI_DisableDMAReq_TX

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_DisableDMAReq_TX(SWPMI_TypeDef *SWPMIx)

+{

+  CLEAR_BIT(SWPMIx->CR, SWPMI_CR_TXDMA);

+}

+

+/**

+  * @brief  Check if DMA mode for transmission is enabled

+  * @rmtoll CR           TXDMA         LL_SWPMI_IsEnabledDMAReq_TX

+  * @param  SWPMIx SWPMI Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(SWPMI_TypeDef *SWPMIx)

+{

+  return ((READ_BIT(SWPMIx->CR, SWPMI_CR_TXDMA) == (SWPMI_CR_TXDMA)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get the data register address used for DMA transfer

+  * @rmtoll TDR          TD            LL_SWPMI_DMA_GetRegAddr\n

+  *         RDR          RD            LL_SWPMI_DMA_GetRegAddr

+  * @param  SWPMIx SWPMI Instance

+  * @param  Direction This parameter can be one of the following values:

+  *         @arg @ref LL_SWPMI_DMA_REG_DATA_TRANSMIT

+  *         @arg @ref LL_SWPMI_DMA_REG_DATA_RECEIVE

+  * @retval Address of data register

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr(SWPMI_TypeDef *SWPMIx, uint32_t Direction)

+{

+  uint32_t data_reg_addr;

+

+  if (Direction == LL_SWPMI_DMA_REG_DATA_TRANSMIT)

+  {

+    /* return address of TDR register */

+    data_reg_addr = (uint32_t)&(SWPMIx->TDR);

+  }

+  else

+  {

+    /* return address of RDR register */

+    data_reg_addr = (uint32_t)&(SWPMIx->RDR);

+  }

+

+  return data_reg_addr;

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup SWPMI_LL_EF_Data_Management Data_Management

+  * @{

+  */

+

+/**

+  * @brief  Retrieve number of data bytes present in payload of received frame

+  * @rmtoll RFL          RFL           LL_SWPMI_GetReceiveFrameLength

+  * @param  SWPMIx SWPMI Instance

+  * @retval Value between Min_Data=0x00 and Max_Data=0x1F

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_GetReceiveFrameLength(SWPMI_TypeDef *SWPMIx)

+{

+  return (uint32_t)(READ_BIT(SWPMIx->RFL, SWPMI_RFL_RFL));

+}

+

+/**

+  * @brief  Transmit Data Register

+  * @rmtoll TDR          TD            LL_SWPMI_TransmitData32

+  * @param  SWPMIx SWPMI Instance

+  * @param  TxData Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_TransmitData32(SWPMI_TypeDef *SWPMIx, uint32_t TxData)

+{

+  WRITE_REG(SWPMIx->TDR, TxData);

+}

+

+/**

+  * @brief  Receive Data Register

+  * @rmtoll RDR          RD            LL_SWPMI_ReceiveData32

+  * @param  SWPMIx SWPMI Instance

+  * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF

+  */

+__STATIC_INLINE uint32_t LL_SWPMI_ReceiveData32(SWPMI_TypeDef *SWPMIx)

+{

+  return (uint32_t)(READ_BIT(SWPMIx->RDR, SWPMI_RDR_RD));

+}

+

+/**

+  * @brief  Enable SWP Transceiver Bypass

+  * @note   The external interface for SWPMI is SWPMI_IO

+  *         (SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are not available on GPIOs)

+  * @rmtoll OR           TBYP          LL_SWPMI_EnableTXBypass

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_EnableTXBypass(SWPMI_TypeDef *SWPMIx)

+{

+  CLEAR_BIT(SWPMIx->OR, SWPMI_OR_TBYP);

+}

+

+/**

+  * @brief  Disable SWP Transceiver Bypass

+  * @note   SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are available as alternate

+  *         function on GPIOs. This configuration is selected to connect an external transceiver

+  * @note   In SWPMI_IO bypass mode, SWPEN bit in SWPMI_CR register must be kept cleared

+  * @rmtoll OR           TBYP          LL_SWPMI_DisableTXBypass

+  * @param  SWPMIx SWPMI Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_SWPMI_DisableTXBypass(SWPMI_TypeDef *SWPMIx)

+{

+  SET_BIT(SWPMIx->OR, SWPMI_OR_TBYP);

+}

+

+/**

+  * @}

+  */

+

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup SWPMI_LL_EF_Init Initialization and de-initialization functions

+  * @{

+  */

+

+ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx);

+ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_InitStruct);

+void        LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct);

+

+/**

+  * @}

+  */

+#endif /*USE_FULL_LL_DRIVER*/

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_LL_SWPMI_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_system.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_system.h
new file mode 100644
index 0000000000..77fc4ff5c4
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_system.h
@@ -0,0 +1,2274 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_system.h

+  * @author  MCD Application Team

+  * @brief   Header file of SYSTEM LL module.

+  @verbatim

+  ==============================================================================

+                     ##### How to use this driver #####

+  ==============================================================================

+    [..]

+    The LL SYSTEM driver contains a set of generic APIs that can be

+    used by user:

+      (+) Some of the FLASH features need to be handled in the SYSTEM file.

+      (+) Access to DBGCMU registers

+      (+) Access to SYSCFG registers

+

+  @endverbatim

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef __STM32H7xx_LL_SYSTEM_H

+#define __STM32H7xx_LL_SYSTEM_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)

+

+/** @defgroup SYSTEM_LL SYSTEM

+  * @{

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants

+  * @{

+  */

+/** @defgroup SYSTEM_LL_EC_FLASH_BANK1_SECTORS SYSCFG Flash Bank1 sectors bits status

+  * @{

+  */

+#define LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT   0x10000U

+#define LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT   0x20000U

+#define LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT   0x40000U

+#define LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT   0x80000U

+#define LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT   0x100000U

+#define LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT   0x200000U

+#define LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT   0x400000U

+#define LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT   0x800000U

+/**

+  * @}

+  */

+

+/** @defgroup SYSTEM_LL_EC_FLASH_BANK2_SECTORS SYSCFG Flash Bank2 sectors bits status

+  * @{

+  */

+#define LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT   0x10000U

+#define LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT   0x20000U

+#define LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT   0x40000U

+#define LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT   0x80000U

+#define LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT   0x100000U

+#define LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT   0x200000U

+#define LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT   0x400000U

+#define LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT   0x800000U

+/**

+  * @}

+  */

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+

+/* Exported types ------------------------------------------------------------*/

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants

+  * @{

+  */

+

+/** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS

+  * @{

+  */

+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1        SYSCFG_PMCR_I2C1_FMP       /*!< Enable Fast Mode Plus for I2C1      */

+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2        SYSCFG_PMCR_I2C2_FMP       /*!< Enable Fast Mode Plus for I2C2      */

+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3        SYSCFG_PMCR_I2C3_FMP       /*!< Enable Fast Mode Plus for I2C3      */

+#define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4        SYSCFG_PMCR_I2C4_FMP       /*!< Enable Fast Mode Plus for I2C4      */

+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB6         SYSCFG_PMCR_I2C_PB6_FMP    /*!< Enable Fast Mode Plus on PB6        */

+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB7         SYSCFG_PMCR_I2C_PB7_FMP    /*!< Enable Fast Mode Plus on PB7        */

+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB8         SYSCFG_PMCR_I2C_PB8_FMP    /*!< Enable Fast Mode Plus on PB8        */

+#define LL_SYSCFG_I2C_FASTMODEPLUS_PB9         SYSCFG_PMCR_I2C_PB9_FMP    /*!< Enable Fast Mode Plus on PB9        */

+/**

+  * @}

+  */

+

+/** @defgroup SYSTEM_LL_EC_ANALOG_SWITCH Analog Switch control

+* @{

+*/

+#define LL_SYSCFG_ANALOG_SWITCH_BOOSTEN           SYSCFG_PMCR_BOOSTEN               /*!< I/O analog switch voltage booster enable */

+#define LL_SYSCFG_ANALOG_SWITCH_PA0               SYSCFG_PMCR_PA0SO                 /*!< PA0 Switch Open */

+#define LL_SYSCFG_ANALOG_SWITCH_PA1               SYSCFG_PMCR_PA1SO                 /*!< PA1 Switch Open */

+#define LL_SYSCFG_ANALOG_SWITCH_PC2               SYSCFG_PMCR_PC2SO                 /*!< PC2 Switch Open */

+#define LL_SYSCFG_ANALOG_SWITCH_PC3               SYSCFG_PMCR_PC3SO                 /*!< PC3 Switch Open */

+/**

+  * @}

+  */

+

+#if defined(SYSCFG_PMCR_EPIS_SEL)

+/** @defgroup SYSTEM_LL_EC_EPIS Ethernet PHY Interface Selection

+* @{

+*/

+#define LL_SYSCFG_ETH_MII               0x00000000U                           /*!< ETH Media MII interface */

+#define LL_SYSCFG_ETH_RMII              SYSCFG_PMCR_EPIS_SEL                   /*!< ETH Media RMII interface */

+/**

+  * @}

+  */

+#endif /* SYSCFG_PMCR_EPIS_SEL */

+

+/** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT

+  * @{

+  */

+#define LL_SYSCFG_EXTI_PORTA               0U               /*!< EXTI PORT A                        */

+#define LL_SYSCFG_EXTI_PORTB               1U               /*!< EXTI PORT B                        */

+#define LL_SYSCFG_EXTI_PORTC               2U               /*!< EXTI PORT C                        */

+#define LL_SYSCFG_EXTI_PORTD               3U               /*!< EXTI PORT D                        */

+#define LL_SYSCFG_EXTI_PORTE               4U               /*!< EXTI PORT E                        */

+#define LL_SYSCFG_EXTI_PORTF               5U               /*!< EXTI PORT F                        */

+#define LL_SYSCFG_EXTI_PORTG               6U               /*!< EXTI PORT G                        */

+#define LL_SYSCFG_EXTI_PORTH               7U               /*!< EXTI PORT H                        */

+#define LL_SYSCFG_EXTI_PORTI               8U               /*!< EXTI PORT I                        */

+#define LL_SYSCFG_EXTI_PORTJ               9U               /*!< EXTI PORT J                        */

+#define LL_SYSCFG_EXTI_PORTK               10U              /*!< EXTI PORT k                        */

+/**

+  * @}

+  */

+

+/** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE

+  * @{

+  */

+#define LL_SYSCFG_EXTI_LINE0               ((0x000FUL << 16U) | 0U)  /*!< EXTI_POSITION_0  | EXTICR[0] */

+#define LL_SYSCFG_EXTI_LINE1               ((0x00F0UL << 16U) | 0U)  /*!< EXTI_POSITION_4  | EXTICR[0] */

+#define LL_SYSCFG_EXTI_LINE2               ((0x0F00UL << 16U) | 0U)  /*!< EXTI_POSITION_8  | EXTICR[0] */

+#define LL_SYSCFG_EXTI_LINE3               ((0xF000UL << 16U) | 0U)  /*!< EXTI_POSITION_12 | EXTICR[0] */

+#define LL_SYSCFG_EXTI_LINE4               ((0x000FUL << 16U) | 1U)  /*!< EXTI_POSITION_0  | EXTICR[1] */

+#define LL_SYSCFG_EXTI_LINE5               ((0x00F0UL << 16U) | 1U)  /*!< EXTI_POSITION_4  | EXTICR[1] */

+#define LL_SYSCFG_EXTI_LINE6               ((0x0F00UL << 16U) | 1U)  /*!< EXTI_POSITION_8  | EXTICR[1] */

+#define LL_SYSCFG_EXTI_LINE7               ((0xF000UL << 16U) | 1U)  /*!< EXTI_POSITION_12 | EXTICR[1] */

+#define LL_SYSCFG_EXTI_LINE8               ((0x000FUL << 16U) | 2U)  /*!< EXTI_POSITION_0  | EXTICR[2] */

+#define LL_SYSCFG_EXTI_LINE9               ((0x00F0UL << 16U) | 2U)  /*!< EXTI_POSITION_4  | EXTICR[2] */

+#define LL_SYSCFG_EXTI_LINE10              ((0x0F00UL << 16U) | 2U)  /*!< EXTI_POSITION_8  | EXTICR[2] */

+#define LL_SYSCFG_EXTI_LINE11              ((0xF000UL << 16U) | 2U)  /*!< EXTI_POSITION_12 | EXTICR[2] */

+#define LL_SYSCFG_EXTI_LINE12              ((0x000FUL << 16U) | 3U)  /*!< EXTI_POSITION_0  | EXTICR[3] */

+#define LL_SYSCFG_EXTI_LINE13              ((0x00F0UL << 16U) | 3U)  /*!< EXTI_POSITION_4  | EXTICR[3] */

+#define LL_SYSCFG_EXTI_LINE14              ((0x0F00UL << 16U) | 3U)  /*!< EXTI_POSITION_8  | EXTICR[3] */

+#define LL_SYSCFG_EXTI_LINE15              ((0xF000UL << 16U) | 3U)  /*!< EXTI_POSITION_12 | EXTICR[3] */

+/**

+  * @}

+  */

+

+/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK

+  * @{

+  */

+#define LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC SYSCFG_CFGR_AXISRAML /*!< Enables and locks the AXIRAM double ECC error signal

+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */

+

+#define LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC    SYSCFG_CFGR_ITCML    /*!< Enables and locks the ITCM double ECC error signal

+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */

+

+#define LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC    SYSCFG_CFGR_DTCML    /*!< Enables and locks the DTCM double ECC error signal

+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */

+

+#define LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC   SYSCFG_CFGR_SRAM1L   /*!< Enables and locks the SRAM1 double ECC error signal

+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */

+

+#define LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC   SYSCFG_CFGR_SRAM2L   /*!< Enables and locks the SRAM2 double ECC error signal

+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */

+

+#define LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC   SYSCFG_CFGR_SRAM3L   /*!< Enables and locks the SRAM3 double ECC error signal

+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */

+

+#define LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC   SYSCFG_CFGR_SRAM4L   /*!< Enables and locks the SRAM4 double ECC error signal

+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */

+

+#define LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC   SYSCFG_CFGR_BKRAML   /*!< Enables and locks the BKRAM double ECC error signal

+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */

+

+#define LL_SYSCFG_TIMBREAK_CM7_LOCKUP      SYSCFG_CFGR_CM7L     /*!< Enables and locks the Cortex-M7 LOCKUP signal

+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */

+

+#define LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC   SYSCFG_CFGR_FLASHL   /*!< Enables and locks the FLASH double ECC error signal

+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */

+

+#define LL_SYSCFG_TIMBREAK_PVD             SYSCFG_CFGR_PVDL     /*!< Enables and locks the PVD connection

+                                                                     with TIM1/8/15/16/17 and HRTIM Break Input

+                                                                     and also the PVDE and PLS bits of the Power Control Interface */

+#if defined(DUAL_CORE)

+#define LL_SYSCFG_TIMBREAK_CM4_LOCKUP      SYSCFG_CFGR_CM4L     /*!< Enables and locks the Cortex-M4 LOCKUP signal

+                                                                     with Break Input of TIM1/8/15/16/17 and HRTIM        */

+#endif /* DUAL_CORE */

+/**

+  * @}

+  */

+

+/** @defgroup SYSTEM_LL_EC_CS SYSCFG I/O compensation cell Code selection

+  * @{

+  */

+#define LL_SYSCFG_CELL_CODE               0U

+#define LL_SYSCFG_REGISTER_CODE           SYSCFG_CCCSR_CS

+/**

+  * @}

+  */

+

+/** @defgroup SYSTEM_LL_IWDG1_CONTROL_MODES SYSCFG IWDG1 control modes

+  * @{

+  */

+#define LL_SYSCFG_IWDG1_SW_CONTROL_MODE   0U

+#define LL_SYSCFG_IWDG1_HW_CONTROL_MODE   SYSCFG_UR11_IWDG1M

+/**

+  * @}

+  */

+

+#if defined (DUAL_CORE)

+/** @defgroup SYSTEM_LL_IWDG2_CONTROL_MODES SYSCFG IWDG2 control modes

+  * @{

+  */

+#define LL_SYSCFG_IWDG2_SW_CONTROL_MODE   0U

+#define LL_SYSCFG_IWDG2_HW_CONTROL_MODE   SYSCFG_UR12_IWDG2M

+/**

+  * @}

+  */

+#endif /* DUAL_CORE */

+

+/** @defgroup SYSTEM_LL_DTCM_RAM_SIZE SYSCFG DTCM RAM size configuration

+  * @{

+  */

+#define LL_SYSCFG_DTCM_RAM_SIZE_2KB     0U

+#define LL_SYSCFG_DTCM_RAM_SIZE_4KB     1U

+#define LL_SYSCFG_DTCM_RAM_SIZE_8KB     2U

+#define LL_SYSCFG_DTCM_RAM_SIZE_16KB    3U

+/**

+  * @}

+  */

+#ifdef SYSCFG_PKGR_PKG

+/** @defgroup SYSTEM_LL_PACKAGE SYSCFG device package

+  * @{

+  */

+#define LL_SYSCFG_LQFP100_PACKAGE             0U

+#define LL_SYSCFG_TQFP144_PACKAGE             2U

+#define LL_SYSCFG_TQFP176_UFBGA176_PACKAGE    5U

+#define LL_SYSCFG_LQFP208_TFBGA240_PACKAGE    8U

+/**

+  * @}

+  */

+#endif /* SYSCFG_PKGR_PKG */

+

+/** @defgroup SYSTEM_LL_SYSCFG_BOR SYSCFG Brownout Reset Threshold Level

+  * @{

+  */

+#define LL_SYSCFG_BOR_OFF_RESET_LEVEL      0x00000000U

+#define LL_SYSCFG_BOR_LOW_RESET_LEVEL      SYSCFG_UR2_BORH_0

+#define LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL   SYSCFG_UR2_BORH_1

+#define LL_SYSCFG_BOR_HIGH_RESET_LEVEL     SYSCFG_UR2_BORH

+

+/**

+  * @}

+  */

+

+/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment

+  * @{

+  */

+#define LL_DBGMCU_TRACE_NONE               0x00000000U                                     /*!< TRACE pins not assigned (default state) */

+#define LL_DBGMCU_TRACE_ASYNCH             DBGMCU_CR_TRACE_IOEN                            /*!< TRACE pin assignment for Asynchronous Mode */

+#define LL_DBGMCU_TRACE_SYNCH_SIZE1        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */

+#define LL_DBGMCU_TRACE_SYNCH_SIZE2        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */

+#define LL_DBGMCU_TRACE_SYNCH_SIZE4        (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)   /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */

+/**

+  * @}

+  */

+

+/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP

+  * @{

+  */

+#define LL_DBGMCU_APB1_GRP1_TIM2_STOP      DBGMCU_APB1LFZ1_DBG_TIM2     /*!< TIM2 counter stopped when core is halted */

+#define LL_DBGMCU_APB1_GRP1_TIM3_STOP      DBGMCU_APB1LFZ1_DBG_TIM3     /*!< TIM3 counter stopped when core is halted */

+#define LL_DBGMCU_APB1_GRP1_TIM4_STOP      DBGMCU_APB1LFZ1_DBG_TIM4     /*!< TIM4 counter stopped when core is halted */

+#define LL_DBGMCU_APB1_GRP1_TIM5_STOP      DBGMCU_APB1LFZ1_DBG_TIM5     /*!< TIM5 counter stopped when core is halted */

+#define LL_DBGMCU_APB1_GRP1_TIM6_STOP      DBGMCU_APB1LFZ1_DBG_TIM6     /*!< TIM6 counter stopped when core is halted */

+#define LL_DBGMCU_APB1_GRP1_TIM7_STOP      DBGMCU_APB1LFZ1_DBG_TIM7     /*!< TIM7 counter stopped when core is halted */

+#define LL_DBGMCU_APB1_GRP1_TIM12_STOP     DBGMCU_APB1LFZ1_DBG_TIM12    /*!< TIM12 counter stopped when core is halted */

+#define LL_DBGMCU_APB1_GRP1_TIM13_STOP     DBGMCU_APB1LFZ1_DBG_TIM13    /*!< TIM13 counter stopped when core is halted */

+#define LL_DBGMCU_APB1_GRP1_TIM14_STOP     DBGMCU_APB1LFZ1_DBG_TIM14    /*!< TIM14 counter stopped when core is halted */

+#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP    DBGMCU_APB1LFZ1_DBG_LPTIM1   /*!< LPTIM1 counter stopped when core is halted */

+#define LL_DBGMCU_APB1_GRP1_I2C1_STOP      DBGMCU_APB1LFZ1_DBG_I2C1     /*!< I2C1 SMBUS timeout mode stopped when Core is halted */

+#define LL_DBGMCU_APB1_GRP1_I2C2_STOP      DBGMCU_APB1LFZ1_DBG_I2C2     /*!< I2C2 SMBUS timeout mode stopped when Core is halted */

+#define LL_DBGMCU_APB1_GRP1_I2C3_STOP      DBGMCU_APB1LFZ1_DBG_I2C3     /*!< I2C3 SMBUS timeout mode stopped when Core is halted */

+/**

+  * @}

+  */

+

+/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP

+  * @{

+  */

+#define LL_DBGMCU_APB1_GRP2_FDCAN_STOP    DBGMCU_APB1HFZ1_DBG_FDCAN    /*!< FDCAN is frozen while the core is in debug mode */

+/**

+  * @}

+  */

+

+/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP

+  * @{

+  */

+#define LL_DBGMCU_APB2_GRP1_TIM1_STOP      DBGMCU_APB2FZ1_DBG_TIM1    /*!< TIM1 counter stopped when core is halted */

+#define LL_DBGMCU_APB2_GRP1_TIM8_STOP      DBGMCU_APB2FZ1_DBG_TIM8    /*!< TIM8 counter stopped when core is halted */

+#define LL_DBGMCU_APB2_GRP1_TIM15_STOP     DBGMCU_APB2FZ1_DBG_TIM15   /*!< TIM15 counter stopped when core is halted */

+#define LL_DBGMCU_APB2_GRP1_TIM16_STOP     DBGMCU_APB2FZ1_DBG_TIM16   /*!< TIM16 counter stopped when core is halted */

+#define LL_DBGMCU_APB2_GRP1_TIM17_STOP     DBGMCU_APB2FZ1_DBG_TIM17   /*!< TIM17 counter stopped when core is halted */

+#define LL_DBGMCU_APB2_GRP1_HRTIM_STOP     DBGMCU_APB2FZ1_DBG_HRTIM   /*!< HRTIM counter stopped when core is halted */

+/**

+  * @}

+  */

+

+/** @defgroup SYSTEM_LL_EC_APB3_GRP1_STOP_IP DBGMCU APB3 GRP1 STOP IP

+  * @{

+  */

+#define LL_DBGMCU_APB3_GRP1_WWDG1_STOP      DBGMCU_APB3FZ1_DBG_WWDG1   /*!< WWDG1 is frozen while the core is in debug mode */

+/**

+  * @}

+  */

+

+/** @defgroup SYSTEM_LL_EC_APB4_GRP1_STOP_IP DBGMCU APB4 GRP1 STOP IP

+  * @{

+  */

+#define LL_DBGMCU_APB4_GRP1_I2C4_STOP       DBGMCU_APB4FZ1_DBG_I2C4     /*!< I2C4 is frozen while the core is in debug mode */

+#define LL_DBGMCU_APB4_GRP1_LPTIM2_STOP     DBGMCU_APB4FZ1_DBG_LPTIM2   /*!< LPTIM2 is frozen while the core is in debug mode */

+#define LL_DBGMCU_APB4_GRP1_LPTIM3_STOP     DBGMCU_APB4FZ1_DBG_LPTIM3   /*!< LPTIM3 is frozen while the core is in debug mode */

+#define LL_DBGMCU_APB4_GRP1_LPTIM4_STOP     DBGMCU_APB4FZ1_DBG_LPTIM4   /*!< LPTIM4 is frozen while the core is in debug mode */

+#define LL_DBGMCU_APB4_GRP1_LPTIM5_STOP     DBGMCU_APB4FZ1_DBG_LPTIM5   /*!< LPTIM5 is frozen while the core is in debug mode */

+#define LL_DBGMCU_APB4_GRP1_RTC_STOP        DBGMCU_APB4FZ1_DBG_RTC      /*!< RTC is frozen while the core is in debug mode */

+#define LL_DBGMCU_APB4_GRP1_IWDG1_STOP      DBGMCU_APB4FZ1_DBG_IWDG1    /*!< IWDG1 is frozen while the core is in debug mode */

+/**

+  * @}

+  */

+

+/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY

+  * @{

+  */

+#define LL_FLASH_LATENCY_0                 FLASH_ACR_LATENCY_0WS   /*!< FLASH Zero wait state */

+#define LL_FLASH_LATENCY_1                 FLASH_ACR_LATENCY_1WS   /*!< FLASH One wait state */

+#define LL_FLASH_LATENCY_2                 FLASH_ACR_LATENCY_2WS   /*!< FLASH Two wait states */

+#define LL_FLASH_LATENCY_3                 FLASH_ACR_LATENCY_3WS   /*!< FLASH Three wait states */

+#define LL_FLASH_LATENCY_4                 FLASH_ACR_LATENCY_4WS   /*!< FLASH Four wait states */

+#define LL_FLASH_LATENCY_5                 FLASH_ACR_LATENCY_5WS   /*!< FLASH five wait state */

+#define LL_FLASH_LATENCY_6                 FLASH_ACR_LATENCY_6WS   /*!< FLASH six wait state */

+#define LL_FLASH_LATENCY_7                 FLASH_ACR_LATENCY_7WS   /*!< FLASH seven wait states */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions

+  * @{

+  */

+

+/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG

+  * @{

+  */

+

+#if defined(SYSCFG_PMCR_EPIS_SEL)

+/**

+  * @brief  Select Ethernet PHY interface

+  * @rmtoll PMCR    EPIS_SEL    LL_SYSCFG_SetPHYInterface

+  * @param  Interface This parameter can be one of the following values:

+  *         @arg @ref LL_SYSCFG_ETH_MII

+  *         @arg @ref LL_SYSCFG_ETH_RMII

+  * @retval None

+  */

+__STATIC_INLINE void LL_SYSCFG_SetPHYInterface(uint32_t Interface)

+{

+  MODIFY_REG(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL, Interface);

+}

+

+/**

+  * @brief  Get Ethernet PHY interface

+  * @rmtoll PMCR    EPIS_SEL    LL_SYSCFG_GetPHYInterface

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_SYSCFG_ETH_MII

+  *         @arg @ref LL_SYSCFG_ETH_RMII

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_GetPHYInterface(void)

+{

+  return (uint32_t)(READ_BIT(SYSCFG->PMCR, SYSCFG_PMCR_EPIS_SEL));

+}

+

+#endif /* SYSCFG_PMCR_EPIS_SEL */

+/**

+  * @brief  Open an Analog Switch

+  * @rmtoll PMCR    PA0SO   LL_SYSCFG_OpenAnalogSwitch

+  * @rmtoll PMCR    PA1SO   LL_SYSCFG_OpenAnalogSwitch

+  * @rmtoll PMCR    PC2SO   LL_SYSCFG_OpenAnalogSwitch

+  * @rmtoll PMCR    PC3SO   LL_SYSCFG_OpenAnalogSwitch

+  * @param  AnalogSwitch This parameter can be one of the following values:

+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch

+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PA1:  PA1 analog switch

+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch

+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PC3:  PC3 analog switch

+  * @retval None

+  */

+__STATIC_INLINE void LL_SYSCFG_OpenAnalogSwitch(uint32_t AnalogSwitch)

+{

+  SET_BIT(SYSCFG->PMCR, AnalogSwitch);

+}

+

+/**

+  * @brief  Close an Analog Switch

+  * @rmtoll PMCR    PA0SO   LL_SYSCFG_CloseAnalogSwitch

+  * @rmtoll PMCR    PA1SO   LL_SYSCFG_CloseAnalogSwitch

+  * @rmtoll PMCR    PC2SO   LL_SYSCFG_CloseAnalogSwitch

+  * @rmtoll PMCR    PC3SO   LL_SYSCFG_CloseAnalogSwitch

+  * @param  AnalogSwitch This parameter can be one of the following values:

+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PA0 : PA0 analog switch

+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PA1:  PA1 analog switch

+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PC2 : PC2 analog switch

+  *         @arg LL_SYSCFG_ANALOG_SWITCH_PC3:  PC3 analog switch

+  * @retval None

+  */

+__STATIC_INLINE void LL_SYSCFG_CloseAnalogSwitch(uint32_t AnalogSwitch)

+{

+  CLEAR_BIT(SYSCFG->PMCR, AnalogSwitch);

+}

+#ifdef SYSCFG_PMCR_BOOSTEN

+/**

+  * @brief  Enable the Analog booster to reduce the total harmonic distortion

+  *         of the analog switch when the supply voltage is lower than 2.7 V

+  * @rmtoll PMCR    BOOSTEN   LL_SYSCFG_EnableAnalogBooster

+  * @note   Activating the booster allows to guaranty the analog switch AC performance

+  *         when the supply voltage is below 2.7 V: in this case, the analog switch

+  *         performance is the same on the full voltage range

+  * @retval None

+  */

+__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void)

+{

+ SET_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;

+}

+

+/**

+  * @brief  Disable the Analog booster

+  * @rmtoll PMCR    BOOSTEN   LL_SYSCFG_DisableAnalogBooster

+  * @note   Activating the booster allows to guaranty the analog switch AC performance

+  *         when the supply voltage is below 2.7 V: in this case, the analog switch

+  *         performance is the same on the full voltage range

+  * @retval None

+  */

+__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void)

+{

+ CLEAR_BIT(SYSCFG->PMCR, SYSCFG_PMCR_BOOSTEN) ;

+}

+#endif /*SYSCFG_PMCR_BOOSTEN*/

+/**

+  * @brief  Enable the I2C fast mode plus driving capability.

+  * @rmtoll SYSCFG_PMCR   I2C_PBx_FMP   LL_SYSCFG_EnableFastModePlus\n

+  *         SYSCFG_PMCR   I2Cx_FMP      LL_SYSCFG_EnableFastModePlus

+  * @param  ConfigFastModePlus This parameter can be a combination of the following values:

+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6

+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7

+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)

+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)

+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1

+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)

+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3

+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4(*)

+  *

+  *         (*) value not defined in all devices

+  * @retval None

+  */

+__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus)

+{

+  SET_BIT(SYSCFG->PMCR, ConfigFastModePlus);

+}

+

+/**

+  * @brief  Disable the I2C fast mode plus driving capability.

+  * @rmtoll SYSCFG_PMCR    I2C_PBx_FMP   LL_SYSCFG_DisableFastModePlus\n

+  *         SYSCFG_PMCR    I2Cx_FMP      LL_SYSCFG_DisableFastModePlus

+  * @param  ConfigFastModePlus This parameter can be a combination of the following values:

+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6

+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7

+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)

+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)

+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1

+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)

+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3

+  *         @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4

+  *         (*) value not defined in all devices

+  * @retval None

+  */

+__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus)

+{

+  CLEAR_BIT(SYSCFG->PMCR, ConfigFastModePlus);

+}

+

+/**

+  * @brief  Configure source input for the EXTI external interrupt.

+  * @rmtoll SYSCFG_EXTICR1  EXTIx         LL_SYSCFG_SetEXTISource\n

+  *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_SetEXTISource\n

+  *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_SetEXTISource\n

+  *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_SetEXTISource

+  * @param  Port This parameter can be one of the following values:

+  *         @arg @ref LL_SYSCFG_EXTI_PORTA

+  *         @arg @ref LL_SYSCFG_EXTI_PORTB

+  *         @arg @ref LL_SYSCFG_EXTI_PORTC

+  *         @arg @ref LL_SYSCFG_EXTI_PORTD

+  *         @arg @ref LL_SYSCFG_EXTI_PORTE

+  *         @arg @ref LL_SYSCFG_EXTI_PORTF

+  *         @arg @ref LL_SYSCFG_EXTI_PORTG

+  *         @arg @ref LL_SYSCFG_EXTI_PORTH

+  *         @arg @ref LL_SYSCFG_EXTI_PORTI

+  *         @arg @ref LL_SYSCFG_EXTI_PORTJ

+  *         @arg @ref LL_SYSCFG_EXTI_PORTK

+  *

+  *         (*) value not defined in all devices

+  * @param  Line This parameter can be one of the following values:

+  *         @arg @ref LL_SYSCFG_EXTI_LINE0

+  *         @arg @ref LL_SYSCFG_EXTI_LINE1

+  *         @arg @ref LL_SYSCFG_EXTI_LINE2

+  *         @arg @ref LL_SYSCFG_EXTI_LINE3

+  *         @arg @ref LL_SYSCFG_EXTI_LINE4

+  *         @arg @ref LL_SYSCFG_EXTI_LINE5

+  *         @arg @ref LL_SYSCFG_EXTI_LINE6

+  *         @arg @ref LL_SYSCFG_EXTI_LINE7

+  *         @arg @ref LL_SYSCFG_EXTI_LINE8

+  *         @arg @ref LL_SYSCFG_EXTI_LINE9

+  *         @arg @ref LL_SYSCFG_EXTI_LINE10

+  *         @arg @ref LL_SYSCFG_EXTI_LINE11

+  *         @arg @ref LL_SYSCFG_EXTI_LINE12

+  *         @arg @ref LL_SYSCFG_EXTI_LINE13

+  *         @arg @ref LL_SYSCFG_EXTI_LINE14

+  *         @arg @ref LL_SYSCFG_EXTI_LINE15

+  * @retval None

+  */

+__STATIC_INLINE void LL_SYSCFG_SetEXTISource(uint32_t Port, uint32_t Line)

+{

+  MODIFY_REG(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U), Port << ((POSITION_VAL(Line >> 16U)) & 31U));

+}

+

+/**

+  * @brief  Get the configured defined for specific EXTI Line

+  * @rmtoll SYSCFG_EXTICR1 EXTIx         LL_SYSCFG_GetEXTISource\n

+  *         SYSCFG_EXTICR2 EXTIx         LL_SYSCFG_GetEXTISource\n

+  *         SYSCFG_EXTICR3 EXTIx         LL_SYSCFG_GetEXTISource\n

+  *         SYSCFG_EXTICR4 EXTIx         LL_SYSCFG_GetEXTISource

+  * @param  Line This parameter can be one of the following values:

+  *         @arg @ref LL_SYSCFG_EXTI_LINE0

+  *         @arg @ref LL_SYSCFG_EXTI_LINE1

+  *         @arg @ref LL_SYSCFG_EXTI_LINE2

+  *         @arg @ref LL_SYSCFG_EXTI_LINE3

+  *         @arg @ref LL_SYSCFG_EXTI_LINE4

+  *         @arg @ref LL_SYSCFG_EXTI_LINE5

+  *         @arg @ref LL_SYSCFG_EXTI_LINE6

+  *         @arg @ref LL_SYSCFG_EXTI_LINE7

+  *         @arg @ref LL_SYSCFG_EXTI_LINE8

+  *         @arg @ref LL_SYSCFG_EXTI_LINE9

+  *         @arg @ref LL_SYSCFG_EXTI_LINE10

+  *         @arg @ref LL_SYSCFG_EXTI_LINE11

+  *         @arg @ref LL_SYSCFG_EXTI_LINE12

+  *         @arg @ref LL_SYSCFG_EXTI_LINE13

+  *         @arg @ref LL_SYSCFG_EXTI_LINE14

+  *         @arg @ref LL_SYSCFG_EXTI_LINE15

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_SYSCFG_EXTI_PORTA

+  *         @arg @ref LL_SYSCFG_EXTI_PORTB

+  *         @arg @ref LL_SYSCFG_EXTI_PORTC

+  *         @arg @ref LL_SYSCFG_EXTI_PORTD

+  *         @arg @ref LL_SYSCFG_EXTI_PORTE

+  *         @arg @ref LL_SYSCFG_EXTI_PORTF

+  *         @arg @ref LL_SYSCFG_EXTI_PORTG

+  *         @arg @ref LL_SYSCFG_EXTI_PORTH

+  *         @arg @ref LL_SYSCFG_EXTI_PORTI

+  *         @arg @ref LL_SYSCFG_EXTI_PORTJ

+  *         @arg @ref LL_SYSCFG_EXTI_PORTK

+  *         (*) value not defined in all devices

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line)

+{

+  return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x3U], (Line >> 16U)) >> (POSITION_VAL(Line >> 16U) & 31U));

+}

+

+/**

+  * @brief  Set connections to TIM1/8/15/16/17 and HRTIM Break inputs

+  * @note this feature is available on STM32H7 rev.B and above

+  * @rmtoll SYSCFG_CFGR AXISRAML       LL_SYSCFG_SetTIMBreakInputs\n

+  *         SYSCFG_CFGR ITCML          LL_SYSCFG_SetTIMBreakInputs\n

+  *         SYSCFG_CFGR DTCML          LL_SYSCFG_SetTIMBreakInputs\n

+  *         SYSCFG_CFGR SRAM1L         LL_SYSCFG_SetTIMBreakInputs\n

+  *         SYSCFG_CFGR SRAM2L         LL_SYSCFG_SetTIMBreakInputs\n

+  *         SYSCFG_CFGR SRAM3L         LL_SYSCFG_SetTIMBreakInputs\n

+  *         SYSCFG_CFGR SRAM4L         LL_SYSCFG_SetTIMBreakInputs\n

+  *         SYSCFG_CFGR BKRAML         LL_SYSCFG_SetTIMBreakInputs\n

+  *         SYSCFG_CFGR CM7L           LL_SYSCFG_SetTIMBreakInputs\n

+  *         SYSCFG_CFGR FLASHL         LL_SYSCFG_SetTIMBreakInputs\n

+  *         SYSCFG_CFGR PVDL           LL_SYSCFG_SetTIMBreakInputs\n

+  *         SYSCFG_CFGR_CM4L           LL_SYSCFG_SetTIMBreakInputs

+  * @param  Break This parameter can be a combination of the following values:

+  *         @arg @ref LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC

+  *         @arg @ref LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC

+  *         @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC

+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC

+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC

+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC

+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC

+  *         @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC

+  *         @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP

+  *         @arg @ref LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC

+  *         @arg @ref LL_SYSCFG_TIMBREAK_PVD

+  *         @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only)

+  * @retval None

+  */

+__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break)

+{

+#if defined(DUAL_CORE)

+  MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \

+                           SYSCFG_CFGR_SRAM3L   | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L   | SYSCFG_CFGR_FLASHL | \

+                           SYSCFG_CFGR_PVDL     | SYSCFG_CFGR_CM4L, Break);

+#elif defined (SYSCFG_CFGR_AXISRAML)

+  MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  | SYSCFG_CFGR_SRAM1L | SYSCFG_CFGR_SRAM2L | \

+                           SYSCFG_CFGR_SRAM3L   | SYSCFG_CFGR_SRAM4L | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L   | SYSCFG_CFGR_FLASHL | \

+                           SYSCFG_CFGR_PVDL, Break);

+#else

+  MODIFY_REG(SYSCFG->CFGR, SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  |\

+                           SYSCFG_CFGR_CM7L   | SYSCFG_CFGR_FLASHL | \

+                           SYSCFG_CFGR_PVDL, Break);

+#endif /* DUAL_CORE */

+}

+

+/**

+  * @brief  Get connections to TIM1/8/15/16/17 and HRTIM Break inputs

+  * @note this feature is available on STM32H7 rev.B and above

+  * @rmtoll SYSCFG_CFGR AXISRAML       LL_SYSCFG_GetTIMBreakInputs\n

+  *         SYSCFG_CFGR ITCML          LL_SYSCFG_GetTIMBreakInputs\n

+  *         SYSCFG_CFGR DTCML          LL_SYSCFG_GetTIMBreakInputs\n

+  *         SYSCFG_CFGR SRAM1L         LL_SYSCFG_GetTIMBreakInputs\n

+  *         SYSCFG_CFGR SRAM2L         LL_SYSCFG_GetTIMBreakInputs\n

+  *         SYSCFG_CFGR SRAM3L         LL_SYSCFG_GetTIMBreakInputs\n

+  *         SYSCFG_CFGR SRAM4L         LL_SYSCFG_GetTIMBreakInputs\n

+  *         SYSCFG_CFGR BKRAML         LL_SYSCFG_GetTIMBreakInputs\n

+  *         SYSCFG_CFGR CM7L           LL_SYSCFG_GetTIMBreakInputs\n

+  *         SYSCFG_CFGR FLASHL         LL_SYSCFG_GetTIMBreakInputs\n

+  *         SYSCFG_CFGR PVDL           LL_SYSCFG_GetTIMBreakInputs\n

+  *         SYSCFG_CFGR_CM4L           LL_SYSCFG_GetTIMBreakInputs

+  * @retval Returned value can be can be a combination of the following values:

+  *         @arg @ref LL_SYSCFG_TIMBREAK_AXISRAM_DBL_ECC

+  *         @arg @ref LL_SYSCFG_TIMBREAK_ITCM_DBL_ECC

+  *         @arg @ref LL_SYSCFG_TIMBREAK_DTCM_DBL_ECC

+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM1_DBL_ECC

+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM2_DBL_ECC

+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM3_DBL_ECC

+  *         @arg @ref LL_SYSCFG_TIMBREAK_SRAM4_DBL_ECC

+  *         @arg @ref LL_SYSCFG_TIMBREAK_BKRAM_DBL_ECC

+  *         @arg @ref LL_SYSCFG_TIMBREAK_CM7_LOCKUP

+  *         @arg @ref LL_SYSCFG_TIMBREAK_FLASH_DBL_ECC

+  *         @arg @ref LL_SYSCFG_TIMBREAK_PVD

+  *         @arg @ref LL_SYSCFG_TIMBREAK_CM4_LOCKUP (available for dual core lines only)

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void)

+{

+#if defined(DUAL_CORE)

+  return (uint32_t)(READ_BIT(SYSCFG->CFGR,  SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  | \

+                                            SYSCFG_CFGR_SRAM1L   | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \

+                                            SYSCFG_CFGR_SRAM4L   | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L   | \

+                                            SYSCFG_CFGR_FLASHL   | SYSCFG_CFGR_PVDL   | SYSCFG_CFGR_CM4L));

+#elif defined (SYSCFG_CFGR_AXISRAML)

+  return (uint32_t)(READ_BIT(SYSCFG->CFGR,  SYSCFG_CFGR_AXISRAML | SYSCFG_CFGR_ITCML  | SYSCFG_CFGR_DTCML  | \

+                                            SYSCFG_CFGR_SRAM1L   | SYSCFG_CFGR_SRAM2L | SYSCFG_CFGR_SRAM3L | \

+                                            SYSCFG_CFGR_SRAM4L   | SYSCFG_CFGR_BKRAML | SYSCFG_CFGR_CM7L   | \

+                                            SYSCFG_CFGR_FLASHL   | SYSCFG_CFGR_PVDL ));

+#else

+  return (uint32_t)(READ_BIT(SYSCFG->CFGR,  SYSCFG_CFGR_ITCML    | SYSCFG_CFGR_DTCML  | SYSCFG_CFGR_CM7L   | \

+                                            SYSCFG_CFGR_FLASHL   | SYSCFG_CFGR_PVDL ));

+#endif /* DUAL_CORE */

+}

+

+/**

+  * @brief  Enable the Compensation Cell

+  * @rmtoll CCCSR   EN    LL_SYSCFG_EnableCompensationCell

+  * @note   The I/O compensation cell can be used only when the device supply

+  *         voltage ranges from 2.4 to 3.6 V

+  * @retval None

+  */

+__STATIC_INLINE void LL_SYSCFG_EnableCompensationCell(void)

+{

+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);

+}

+

+/**

+  * @brief  Disable the Compensation Cell

+  * @rmtoll CCCSR   EN    LL_SYSCFG_DisableCompensationCell

+  * @note   The I/O compensation cell can be used only when the device supply

+  *         voltage ranges from 2.4 to 3.6 V

+  * @retval None

+  */

+__STATIC_INLINE void LL_SYSCFG_DisableCompensationCell(void)

+{

+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN);

+}

+

+/**

+  * @brief  Check if the Compensation Cell is enabled

+  * @rmtoll CCCSR   EN    LL_SYSCFG_IsEnabledCompensationCell

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledCompensationCell(void)

+{

+  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN) == SYSCFG_CCCSR_EN) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get Compensation Cell ready Flag

+  * @rmtoll CCCSR   READY   LL_SYSCFG_IsActiveFlag_CMPCR

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)

+{

+  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_READY) == (SYSCFG_CCCSR_READY)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the I/O speed optimization when the product voltage is low.

+  * @rmtoll CCCSR   HSLV    LL_SYSCFG_EnableIOSpeedOptimize

+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the

+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V

+  *         might be destructive.

+  * @retval None

+  */

+__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization(void)

+{

+#if defined(SYSCFG_CCCSR_HSLV)

+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);

+#else

+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0);

+#endif   /* SYSCFG_CCCSR_HSLV */

+}

+

+#if defined(SYSCFG_CCCSR_HSLV1)

+/**

+  * @brief  Enable the I/O speed optimization when the product voltage is low.

+  * @rmtoll CCCSR   HSLV1    LL_SYSCFG_EnableIOSpeedOptimize

+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the

+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V

+  *         might be destructive.

+  * @retval None

+  */

+__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization1(void)

+{

+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1);

+}

+

+/**

+  * @brief  Enable the I/O speed optimization when the product voltage is low.

+  * @rmtoll CCCSR   HSLV2    LL_SYSCFG_EnableIOSpeedOptimize

+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the

+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V

+  *         might be destructive.

+  * @retval None

+  */

+__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization2(void)

+{

+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2);

+}

+

+/**

+  * @brief  Enable the I/O speed optimization when the product voltage is low.

+  * @rmtoll CCCSR   HSLV3    LL_SYSCFG_EnableIOSpeedOptimize

+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the

+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V

+  *         might be destructive.

+  * @retval None

+  */

+__STATIC_INLINE void LL_SYSCFG_EnableIOSpeedOptimization3(void)

+{

+  SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3);

+}

+#endif /*SYSCFG_CCCSR_HSLV1*/

+

+

+/**

+  * @brief  To Disable optimize the I/O speed when the product voltage is low.

+  * @rmtoll CCCSR   HSLV    LL_SYSCFG_DisableIOSpeedOptimize

+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the

+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V

+  *         might be destructive.

+  * @retval None

+  */

+__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization(void)

+{

+#if defined(SYSCFG_CCCSR_HSLV)

+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV);

+#else

+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0);

+#endif   /* SYSCFG_CCCSR_HSLV */

+}

+

+#if defined(SYSCFG_CCCSR_HSLV1)

+/**

+  * @brief  To Disable optimize the I/O speed when the product voltage is low.

+  * @rmtoll CCCSR   HSLV1    LL_SYSCFG_DisableIOSpeedOptimize

+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the

+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V

+  *         might be destructive.

+  * @retval None

+  */

+__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization1(void)

+{

+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1);

+}

+

+/**

+  * @brief  To Disable optimize the I/O speed when the product voltage is low.

+  * @rmtoll CCCSR   HSLV2    LL_SYSCFG_DisableIOSpeedOptimize

+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the

+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V

+  *         might be destructive.

+  * @retval None

+  */

+__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization2(void)

+{

+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2);

+}

+

+/**

+  * @brief  To Disable optimize the I/O speed when the product voltage is low.

+  * @rmtoll CCCSR   HSLV3    LL_SYSCFG_DisableIOSpeedOptimize

+  * @note   This bit is active only if IO_HSLV user option bit is set. It must be used only if the

+  *         product supply voltage is below 2.7 V. Setting this bit when VDD is higher than 2.7 V

+  *         might be destructive.

+  * @retval None

+  */

+__STATIC_INLINE void LL_SYSCFG_DisableIOSpeedOptimization3(void)

+{

+  CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3);

+}

+#endif /*SYSCFG_CCCSR_HSLV1*/

+

+/**

+  * @brief  Check if the I/O speed optimization is enabled

+  * @rmtoll CCCSR   HSLV    LL_SYSCFG_IsEnabledIOSpeedOptimization

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization(void)

+{

+#if defined(SYSCFG_CCCSR_HSLV)

+  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV) == SYSCFG_CCCSR_HSLV) ? 1UL : 0UL);

+#else

+  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV0) == SYSCFG_CCCSR_HSLV0) ? 1UL : 0UL);

+#endif /*SYSCFG_CCCSR_HSLV*/

+}

+

+#if defined(SYSCFG_CCCSR_HSLV1)

+/**

+  * @brief  Check if the I/O speed optimization is enabled

+  * @rmtoll CCCSR   HSLV1    LL_SYSCFG_IsEnabledIOSpeedOptimization

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization1(void)

+{

+  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV1) == SYSCFG_CCCSR_HSLV1) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the I/O speed optimization is enabled

+  * @rmtoll CCCSR   HSLV2    LL_SYSCFG_IsEnabledIOSpeedOptimization

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization2(void)

+{

+  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV2) == SYSCFG_CCCSR_HSLV2) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the I/O speed optimization is enabled

+  * @rmtoll CCCSR   HSLV3    LL_SYSCFG_IsEnabledIOSpeedOptimization

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIOSpeedOptimization3(void)

+{

+  return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_HSLV3) == SYSCFG_CCCSR_HSLV3) ? 1UL : 0UL);

+}

+#endif /*SYSCFG_CCCSR_HSLV1*/

+

+/**

+  * @brief  Set the code selection for the I/O Compensation cell

+  * @rmtoll CCCSR   CS    LL_SYSCFG_SetCellCompensationCode

+  * @param  CompCode: Selects the code to be applied for the I/O compensation cell

+  *   This parameter can be one of the following values:

+  *   @arg LL_SYSCFG_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR)

+  *   @arg LL_SYSCFG_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR)

+  * @retval None

+  */

+__STATIC_INLINE void LL_SYSCFG_SetCellCompensationCode(uint32_t CompCode)

+{

+  SET_BIT(SYSCFG->CCCSR, CompCode);

+}

+

+/**

+  * @brief  Get the code selected for the I/O Compensation cell

+  * @rmtoll CCCSR   CS    LL_SYSCFG_GetCellCompensationCode

+  * @retval Returned value can be one of the following values:

+  *   @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)

+  *   @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR)

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_GetCellCompensationCode(void)

+{

+  return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS));

+}

+

+#ifdef SYSCFG_CCCSR_CS_MMC

+

+/**

+  * @brief  Get the code selected for the I/O Compensation cell on the VDDMMC power rail

+  * @rmtoll CCCSR   CS    LL_SYSCFG_GetCellCompensationCode

+  * @retval Returned value can be one of the following values:

+  *   @arg LL_SYSCFG_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR)

+  *   @arg LL_SYSCFG_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR)

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_MMCGetCellCompensationCode(void)

+{

+  return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS_MMC));

+}

+#endif /*SYSCFG_CCCSR_CS_MMC*/

+

+/**

+  * @brief  Get I/O compensation cell value for PMOS transistors

+  * @rmtoll CCVR    PCV   LL_SYSCFG_GetPMOSCompensationValue

+  * @retval Returned value is the I/O compensation cell value for PMOS transistors

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationValue(void)

+{

+  return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV));

+}

+

+/**

+  * @brief  Get I/O compensation cell value for NMOS transistors

+  * @rmtoll CCVR    NCV   LL_SYSCFG_GetNMOSCompensationValue

+  * @retval Returned value is the I/O compensation cell value for NMOS transistors

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationValue(void)

+{

+  return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV));

+}

+

+/**

+  * @brief  Set I/O compensation cell code for PMOS transistors

+  * @rmtoll CCCR    PCC   LL_SYSCFG_SetPMOSCompensationCode

+  * @param  PMOSCode PMOS compensation code

+  *         This code is applied to the I/O compensation cell when the CS bit of the

+  *         SYSCFG_CMPCR is set

+  * @retval None

+  */

+__STATIC_INLINE void LL_SYSCFG_SetPMOSCompensationCode(uint32_t PMOSCode)

+{

+  MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC, PMOSCode);

+}

+

+/**

+  * @brief  Get I/O compensation cell code for PMOS transistors

+  * @rmtoll CCCR    PCC   LL_SYSCFG_GetPMOSCompensationCode

+  * @retval Returned value is the I/O compensation cell code for PMOS transistors

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSCompensationCode(void)

+{

+  return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC));

+}

+

+#ifdef SYSCFG_CCCR_PCC_MMC

+

+/**

+  * @brief  Set I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail

+  * @rmtoll CCCR    PCC   LL_SYSCFG_SetPMOSCompensationCode

+  * @param  PMOSCode PMOS compensation code

+  *         This code is applied to the I/O compensation cell when the CS bit of the

+  *         SYSCFG_CMPCR is set

+  * @retval None

+  */

+__STATIC_INLINE void LL_SYSCFG_MMCSetPMOSCompensationCode(uint32_t PMOSCode)

+{

+  MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC, PMOSCode);

+}

+

+/**

+  * @brief  Get I/O compensation cell code for PMOS transistors corresponding to the VDDMMC power rail

+  * @rmtoll CCCR    PCC   LL_SYSCFG_GetPMOSCompensationCode

+  * @retval Returned value is the I/O compensation cell code for PMOS transistors

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_MMCGetPMOSCompensationCode(void)

+{

+  return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC_MMC));

+}

+#endif /* SYSCFG_CCCR_PCC_MMC */

+

+/**

+  * @brief  Set I/O compensation cell code for NMOS transistors

+  * @rmtoll CCCR    NCC   LL_SYSCFG_SetNMOSCompensationCode

+  * @param  NMOSCode NMOS compensation code

+  *         This code is applied to the I/O compensation cell when the CS bit of the

+  *         SYSCFG_CMPCR is set

+  * @retval None

+  */

+__STATIC_INLINE void LL_SYSCFG_SetNMOSCompensationCode(uint32_t NMOSCode)

+{

+  MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC, NMOSCode);

+}

+

+/**

+  * @brief  Get I/O compensation cell code for NMOS transistors

+  * @rmtoll CCCR    NCC   LL_SYSCFG_GetNMOSCompensationCode

+  * @retval Returned value is the I/O compensation cell code for NMOS transistors

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSCompensationCode(void)

+{

+  return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC));

+}

+

+#ifdef SYSCFG_CCCR_NCC_MMC

+

+/**

+  * @brief  Set I/O compensation cell code for NMOS transistors on the VDDMMC power rail.

+  * @rmtoll CCCR    NCC   LL_SYSCFG_SetNMOSCompensationCode

+  * @param  NMOSCode: NMOS compensation code

+  *         This code is applied to the I/O compensation cell when the CS bit of the

+  *         SYSCFG_CMPCR is set

+  * @retval None

+  */

+__STATIC_INLINE void LL_SYSCFG_VDMMCSetNMOSCompensationCode(uint32_t NMOSCode)

+{

+  MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC, NMOSCode);

+}

+

+/**

+  * @brief  Get I/O compensation cell code for NMOS transistors on the VDDMMC power rail.

+  * @rmtoll CCCR    NCC   LL_SYSCFG_GetNMOSCompensationCode

+  * @retval Returned value is the I/O compensation cell code for NMOS transistors

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_VDMMCGetNMOSCompensationCode(void)

+{

+  return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC_MMC));

+}

+#endif /*SYSCFG_CCCR_NCC_MMC*/

+

+#ifdef SYSCFG_PKGR_PKG

+/**

+  * @brief  Get the device package

+  * @rmtoll PKGR    PKG   LL_SYSCFG_GetPackage

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_SYSCFG_LQFP100_PACKAGE

+  *         @arg @ref LL_SYSCFG_TQFP144_PACKAGE

+  *         @arg @ref LL_SYSCFG_TQFP176_UFBGA176_PACKAGE

+  *         @arg @ref LL_SYSCFG_LQFP208_TFBGA240_PACKAGE

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_GetPackage(void)

+{

+  return (uint32_t)(READ_BIT(SYSCFG->PKGR, SYSCFG_PKGR_PKG));

+}

+#endif /*SYSCFG_PKGR_PKG*/

+

+#ifdef SYSCFG_UR0_RDP

+/**

+  * @brief  Get the Flash memory protection level

+  * @rmtoll UR0   RDP   LL_SYSCFG_GetFLashProtectionLevel

+  * @retval Returned value can be one of the following values:

+  *         0xAA : RDP level 0

+  *         0xCC : RDP level 2

+  *         Any other value : RDP level 1

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_GetFLashProtectionLevel(void)

+{

+  return (uint32_t)(READ_BIT(SYSCFG->UR0, SYSCFG_UR0_RDP));

+}

+/**

+  * @brief  Indicate if the Flash memory bank addresses are inverted or not

+  * @rmtoll UR0   BKS   LL_SYSCFG_IsFLashBankAddressesSwaped

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsFLashBankAddressesSwaped(void)

+{

+  return ((READ_BIT(SYSCFG->UR0, SYSCFG_UR0_BKS) == 0U) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get the BOR Threshold Reset Level

+  * @rmtoll UR2   BORH    LL_SYSCFG_GetBrownoutResetLevel

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_SYSCFG_BOR_HIGH_RESET_LEVEL

+  *         @arg @ref LL_SYSCFG_BOR_MEDIUM_RESET_LEVEL

+  *         @arg @ref LL_SYSCFG_BOR_LOW_RESET_LEVEL

+  *         @arg @ref LL_SYSCFG_BOR_OFF_RESET_LEVEL

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_GetBrownoutResetLevel(void)

+{

+  return (uint32_t)(READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BORH));

+}

+/**

+  * @brief  BootCM7 address 0 configuration

+  * @rmtoll UR2   BOOT_ADD0   LL_SYSCFG_SetCM7BootAddress0

+  * @param  BootAddress :Specifies the CM7 Boot Address to be loaded in Address0

+  * @retval None

+  */

+__STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress0(uint16_t BootAddress)

+{

+  /* Configure CM7 BOOT ADD0 */

+#if defined(DUAL_CORE)

+  MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BCM7_ADD0_Pos));

+#else

+  MODIFY_REG(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0, ((uint32_t)BootAddress << SYSCFG_UR2_BOOT_ADD0_Pos));

+#endif /*DUAL_CORE*/

+

+}

+

+/**

+  * @brief  Get BootCM7 address 0

+  * @rmtoll UR2   BOOT_ADD0   LL_SYSCFG_GetCM7BootAddress0

+  * @retval Returned the CM7 Boot Address0

+  */

+__STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress0(void)

+{

+  /* Get CM7 BOOT ADD0 */

+#if defined(DUAL_CORE)

+  return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BCM7_ADD0) >> SYSCFG_UR2_BCM7_ADD0_Pos);

+#else

+  return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR2, SYSCFG_UR2_BOOT_ADD0) >> SYSCFG_UR2_BOOT_ADD0_Pos);

+#endif /*DUAL_CORE*/

+}

+

+/**

+  * @brief  BootCM7 address 1 configuration

+  * @rmtoll UR3   BOOT_ADD1   LL_SYSCFG_SetCM7BootAddress1

+  * @param  BootAddress :Specifies the CM7 Boot Address to be loaded in Address1

+  * @retval None

+  */

+__STATIC_INLINE void LL_SYSCFG_SetCM7BootAddress1(uint16_t BootAddress)

+{

+  /* Configure CM7 BOOT ADD1 */

+#if defined(DUAL_CORE)

+  MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1, BootAddress);

+#else

+  MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1, BootAddress);

+#endif /*DUAL_CORE*/

+}

+

+/**

+  * @brief  Get BootCM7 address 1

+  * @rmtoll UR3   BOOT_ADD1   LL_SYSCFG_GetCM7BootAddress1

+  * @retval Returned the CM7 Boot Address0

+  */

+__STATIC_INLINE uint16_t LL_SYSCFG_GetCM7BootAddress1(void)

+{

+  /* Get CM7 BOOT ADD0 */

+#if defined(DUAL_CORE)

+  return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM7_ADD1));

+#else

+  return (uint16_t)(READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BOOT_ADD1));

+#endif /* DUAL_CORE */

+}

+

+#if defined(DUAL_CORE)

+/**

+  * @brief  BootCM4 address 0 configuration

+  * @rmtoll UR3   BCM4_ADD0   LL_SYSCFG_SetCM4BootAddress0

+  * @param  BootAddress :Specifies the CM4 Boot Address to be loaded in Address0

+  * @retval None

+  */

+__STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress0(uint16_t BootAddress)

+{

+  /* Configure CM4 BOOT ADD0 */

+  MODIFY_REG(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0, ((uint32_t)BootAddress << SYSCFG_UR3_BCM4_ADD0_Pos));

+}

+

+/**

+  * @brief  Get BootCM4 address 0

+  * @rmtoll UR3   BCM4_ADD0   LL_SYSCFG_GetCM4BootAddress0

+  * @retval Returned the CM4 Boot Address0

+  */

+__STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress0(void)

+{

+  /* Get CM4 BOOT ADD0 */

+  return (uint16_t)((uint32_t)READ_BIT(SYSCFG->UR3, SYSCFG_UR3_BCM4_ADD0) >> SYSCFG_UR3_BCM4_ADD0_Pos);

+}

+

+/**

+  * @brief  BootCM4 address 1 configuration

+  * @rmtoll UR4   BCM4_ADD1   LL_SYSCFG_SetCM4BootAddress1

+  * @param  BootAddress :Specifies the CM4 Boot Address to be loaded in Address1

+  * @retval None

+  */

+__STATIC_INLINE void LL_SYSCFG_SetCM4BootAddress1(uint16_t BootAddress)

+{

+  /* Configure CM4 BOOT ADD1 */

+  MODIFY_REG(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1, BootAddress);

+}

+

+/**

+  * @brief  Get BootCM4 address 1

+  * @rmtoll UR4   BCM4_ADD1   LL_SYSCFG_GetCM4BootAddress1

+  * @retval Returned the CM4 Boot Address0

+  */

+__STATIC_INLINE uint16_t LL_SYSCFG_GetCM4BootAddress1(void)

+{

+  /* Get CM4 BOOT ADD0 */

+  return (uint16_t)(READ_BIT(SYSCFG->UR4, SYSCFG_UR4_BCM4_ADD1));

+}

+#endif /*DUAL_CORE*/

+

+/**

+  * @brief  Indicates if the flash protected area (Bank 1) is erased by a mass erase

+  * @rmtoll UR4   MEPAD_BANK1   LL_SYSCFG_IsFlashB1ProtectedAreaErasable

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1ProtectedAreaErasable(void)

+{

+  return ((READ_BIT(SYSCFG->UR4, SYSCFG_UR4_MEPAD_BANK1) == SYSCFG_UR4_MEPAD_BANK1) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicates if the flash secured area (Bank 1) is erased by a mass erase

+  * @rmtoll UR5   MESAD_BANK1   LL_SYSCFG_IsFlashB1SecuredAreaErasable

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1SecuredAreaErasable(void)

+{

+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_MESAD_BANK1) == SYSCFG_UR5_MESAD_BANK1) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicates if the sector 0 of the Flash memory bank 1 is write protected

+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector0WriteProtected

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector0WriteProtected(void)

+{

+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR0_STATUS_BIT)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicates if the sector 1 of the Flash memory bank 1 is write protected

+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector1WriteProtected

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector1WriteProtected(void)

+{

+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR1_STATUS_BIT)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicates if the sector 2 of the Flash memory bank 1 is write protected

+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector2WriteProtected

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector2WriteProtected(void)

+{

+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR2_STATUS_BIT)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicates if the sector 3 of the Flash memory bank 1 is write protected

+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector3WriteProtected

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector3WriteProtected(void)

+{

+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR3_STATUS_BIT)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicates if the sector 4 of the Flash memory bank 1 is write protected

+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector4WriteProtected

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector4WriteProtected(void)

+{

+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR4_STATUS_BIT)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicates if the sector 5 of the Flash memory bank 1 is write protected

+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector5WriteProtected

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector5WriteProtected(void)

+{

+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR5_STATUS_BIT)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicates if the sector 6 of the Flash memory bank 1 is write protected

+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector6WriteProtected

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector6WriteProtected(void)

+{

+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR6_STATUS_BIT)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicates if the sector 7 of the Flash memory bank 1 is write protected

+  * @rmtoll UR5   WRPN_BANK1    LL_SYSCFG_IsFlashB1Sector7WriteProtected

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB1Sector7WriteProtected(void)

+{

+  return ((READ_BIT(SYSCFG->UR5, SYSCFG_UR5_WRPN_BANK1) == (SYSCFG_UR5_WRPN_BANK1 & LL_SYSCFG_FLASH_B1_SECTOR7_STATUS_BIT)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get the protected area start address for Flash bank 1

+  * @rmtoll UR6   PABEG_BANK1    LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress

+  * @retval Returned the protected area start address for Flash bank 1

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaStartAddress(void)

+{

+  return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PABEG_BANK1));

+}

+

+/**

+  * @brief  Get the protected area end address for Flash bank 1

+  * @rmtoll UR6   PAEND_BANK1   LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress

+  * @retval Returned the protected area end address for Flash bank 1

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1ProtectedAreaEndAddress(void)

+{

+  return (uint32_t)(READ_BIT(SYSCFG->UR6, SYSCFG_UR6_PAEND_BANK1));

+}

+

+/**

+  * @brief  Get the secured area start address for Flash bank 1

+  * @rmtoll UR7   SABEG_BANK1   LL_SYSCFG_GetFlashB1SecuredAreaStartAddress

+  * @retval Returned the secured area start address for Flash bank 1

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaStartAddress(void)

+{

+  return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SABEG_BANK1));

+}

+

+/**

+  * @brief  Get the secured area end address for Flash bank 1

+  * @rmtoll UR7   SAEND_BANK1   LL_SYSCFG_GetFlashB1SecuredAreaEndAddress

+  * @retval Returned the secured area end address for Flash bank 1

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB1SecuredAreaEndAddress(void)

+{

+  return (uint32_t)(READ_BIT(SYSCFG->UR7, SYSCFG_UR7_SAEND_BANK1));

+}

+

+/**

+  * @brief  Indicates if the flash protected area (Bank 2) is erased by a mass erase

+  * @rmtoll UR8   MEPAD_BANK2   LL_SYSCFG_IsFlashB2ProtectedAreaErasable

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2ProtectedAreaErasable(void)

+{

+  return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MEPAD_BANK2) == SYSCFG_UR8_MEPAD_BANK2) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicates if the flash secured area (Bank 2) is erased by a mass erase

+  * @rmtoll UR8   MESAD_BANK2   LL_SYSCFG_IsFlashB2SecuredAreaErasable

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2SecuredAreaErasable(void)

+{

+  return ((READ_BIT(SYSCFG->UR8, SYSCFG_UR8_MESAD_BANK2) == SYSCFG_UR8_MESAD_BANK2) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicates if the sector 0 of the Flash memory bank 2 is write protected

+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector0WriteProtected

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector0WriteProtected(void)

+{

+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR0_STATUS_BIT)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicates if the sector 1 of the Flash memory bank 2 is write protected

+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector1WriteProtected

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector1WriteProtected(void)

+{

+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR1_STATUS_BIT)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicates if the sector 2 of the Flash memory bank 2 is write protected

+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector2WriteProtected

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector2WriteProtected(void)

+{

+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR2_STATUS_BIT)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicates if the sector 3 of the Flash memory bank 2 is write protected

+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector3WriteProtected

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector3WriteProtected(void)

+{

+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR3_STATUS_BIT)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicates if the sector 4 of the Flash memory bank 2 is write protected

+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector4WriteProtected

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector4WriteProtected(void)

+{

+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR4_STATUS_BIT)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicates if the sector 5 of the Flash memory bank 2 is write protected

+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector5WriteProtected

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector5WriteProtected(void)

+{

+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR5_STATUS_BIT)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicates if the sector 6 of the Flash memory bank 2 is write protected

+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector6WriteProtected

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector6WriteProtected(void)

+{

+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR6_STATUS_BIT)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicates if the sector 7 of the Flash memory bank 2 is write protected

+  * @rmtoll UR9   WRPN_BANK2    LL_SYSCFG_IsFlashB2Sector7WriteProtected

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsFlashB2Sector7WriteProtected(void)

+{

+  return ((READ_BIT(SYSCFG->UR9, SYSCFG_UR9_WRPN_BANK2) == (SYSCFG_UR9_WRPN_BANK2 & LL_SYSCFG_FLASH_B2_SECTOR7_STATUS_BIT)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get the protected area start address for Flash bank 2

+  * @rmtoll UR9   PABEG_BANK2   LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress

+  * @retval Returned the protected area start address for Flash bank 2

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaStartAddress(void)

+{

+  return (uint32_t)(READ_BIT(SYSCFG->UR9, SYSCFG_UR9_PABEG_BANK2));

+}

+

+/**

+  * @brief  Get the protected area end address for Flash bank 2

+  * @rmtoll UR10    PAEND_BANK2   LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress

+  * @retval Returned the protected area end address for Flash bank 2

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2ProtectedAreaEndAddress(void)

+{

+  return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_PAEND_BANK2));

+}

+

+/**

+  * @brief  Get the secured area start address for Flash bank 2

+  * @rmtoll UR10    SABEG_BANK2   LL_SYSCFG_GetFlashB2SecuredAreaStartAddress

+  * @retval Returned the secured area start address for Flash bank 2

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaStartAddress(void)

+{

+  return (uint32_t)(READ_BIT(SYSCFG->UR10, SYSCFG_UR10_SABEG_BANK2));

+}

+

+/**

+  * @brief  Get the secured area end address for Flash bank 2

+  * @rmtoll UR11    SAEND_BANK2   LL_SYSCFG_GetFlashB2SecuredAreaEndAddress

+  * @retval Returned the secured area end address for Flash bank 2

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_GetFlashB2SecuredAreaEndAddress(void)

+{

+  return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_SAEND_BANK2));

+}

+

+/**

+  * @brief  Get the Independent Watchdog 1 control mode (Software or Hardware)

+  * @rmtoll UR11    IWDG1M    LL_SYSCFG_GetIWDG1ControlMode

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_SYSCFG_IWDG1_SW_CONTROL_MODE

+  *         @arg @ref LL_SYSCFG_IWDG1_HW_CONTROL_MODE

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG1ControlMode(void)

+{

+  return (uint32_t)(READ_BIT(SYSCFG->UR11, SYSCFG_UR11_IWDG1M));

+}

+

+#if defined (DUAL_CORE)

+/**

+  * @brief  Get the Independent Watchdog 2 control mode (Software or Hardware)

+  * @rmtoll UR12    IWDG2M    LL_SYSCFG_GetIWDG2ControlMode

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_SYSCFG_IWDG2_SW_CONTROL_MODE

+  *         @arg @ref LL_SYSCFG_IWDG2_HW_CONTROL_MODE

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_GetIWDG2ControlMode(void)

+{

+  return (uint32_t)(READ_BIT(SYSCFG->UR12, SYSCFG_UR12_IWDG2M));

+}

+#endif /* DUAL_CORE */

+

+/**

+  * @brief  Indicates the Secure mode status

+  * @rmtoll UR12    SECURE    LL_SYSCFG_IsSecureModeEnabled

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsSecureModeEnabled(void)

+{

+  return ((READ_BIT(SYSCFG->UR12, SYSCFG_UR12_SECURE) == SYSCFG_UR12_SECURE) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicates if a reset is generated when D1 domain enters DStandby mode

+  * @rmtoll UR13    D1SBRST   LL_SYSCFG_IsD1StandbyGenerateReset

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsD1StandbyGenerateReset(void)

+{

+  return ((READ_BIT(SYSCFG->UR13, SYSCFG_UR13_D1SBRST) == 0U) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get the secured DTCM RAM size

+  * @rmtoll UR13    SDRS    LL_SYSCFG_GetSecuredDTCMSize

+  * @retval Returned value can be one of the following values:

+  *           @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_2KB

+  *           @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_4KB

+  *           @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_8KB

+  *           @arg @ref LL_SYSCFG_DTCM_RAM_SIZE_16KB

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_GetSecuredDTCMSize(void)

+{

+  return (uint32_t)(READ_BIT(SYSCFG->UR13, SYSCFG_UR13_SDRS));

+}

+

+/**

+  * @brief  Indicates if a reset is generated when D1 domain enters DStop mode

+  * @rmtoll UR14    D1STPRST    LL_SYSCFG_IsD1StopGenerateReset

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsD1StopGenerateReset(void)

+{

+  return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D1STPRST) == 0U) ? 1UL : 0UL);

+}

+

+#if defined (DUAL_CORE)

+/**

+  * @brief  Indicates if a reset is generated when D2 domain enters DStandby mode

+  * @rmtoll UR14    D2SBRST   LL_SYSCFG_IsD2StandbyGenerateReset

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsD2StandbyGenerateReset(void)

+{

+  return ((READ_BIT(SYSCFG->UR14, SYSCFG_UR14_D2SBRST) == 0U) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicates if a reset is generated when D2 domain enters DStop mode

+  * @rmtoll UR15    D2STPRST    LL_SYSCFG_IsD2StopGenerateReset

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsD2StopGenerateReset(void)

+{

+  return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_D2STPRST) == 0U) ? 1UL : 0UL);

+}

+#endif /* DUAL_CORE */

+

+/**

+  * @brief  Indicates if the independent watchdog is frozen in Standby mode

+  * @rmtoll UR15    FZIWDGSTB   LL_SYSCFG_IsIWDGFrozenInStandbyMode

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStandbyMode(void)

+{

+  return ((READ_BIT(SYSCFG->UR15, SYSCFG_UR15_FZIWDGSTB) == 0U) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicates if the independent watchdog is frozen in Stop mode

+  * @rmtoll UR16    FZIWDGSTP   LL_SYSCFG_IsIWDGFrozenInStopMode

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsIWDGFrozenInStopMode(void)

+{

+  return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_FZIWDGSTP) == 0U) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicates if the device private key is programmed

+  * @rmtoll UR16    PKP   LL_SYSCFG_IsPrivateKeyProgrammed

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsPrivateKeyProgrammed(void)

+{

+  return ((READ_BIT(SYSCFG->UR16, SYSCFG_UR16_PKP) == SYSCFG_UR16_PKP) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Indicates if the Product is working on the full voltage range or not

+  * @rmtoll UR17    IOHSLV    LL_SYSCFG_IsActiveFlag_IOHSLV

+  * @note   When the IOHSLV option bit is set the Product is working below 2.7 V.

+  *         When the IOHSLV option bit is reset the Product is working on the

+  *         full voltage range.

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_IOHSLV(void)

+{

+  return ((READ_BIT(SYSCFG->UR17, SYSCFG_UR17_IOHSLV) == SYSCFG_UR17_IOHSLV) ? 1UL : 0UL);

+}

+#endif /*SYSCFG_UR0_RDP*/

+

+/**

+  * @}

+  */

+

+/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU

+  * @{

+  */

+

+/**

+  * @brief  Return the device identifier

+  * @rmtoll DBGMCU_IDCODE DEV_ID        LL_DBGMCU_GetDeviceID

+  * @retval Values between Min_Data=0x00 and Max_Data=0xFFF

+  */

+__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void)

+{

+  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID));

+}

+

+/**

+  * @brief  Return the device revision identifier

+  * @note This field indicates the revision of the device.

+          For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001

+  * @rmtoll DBGMCU_IDCODE REV_ID        LL_DBGMCU_GetRevisionID

+  * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF

+  */

+__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void)

+{

+  return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos);

+}

+

+/**

+  * @brief  Enable D1 Domain/CDomain debug during SLEEP mode

+  * @rmtoll DBGMCU_CR    DBGSLEEP_D1/DBGSLEEP_CD     LL_DBGMCU_EnableD1DebugInSleepMode

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInSleepMode(void)

+{

+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);

+}

+

+/**

+  * @brief  Disable D1 Domain/CDomain debug during SLEEP mode

+  * @rmtoll DBGMCU_CR    DBGSLEEP_D1/DBGSLEEP_CD     LL_DBGMCU_DisableD1DebugInSleepMode

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInSleepMode(void)

+{

+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD1);

+}

+

+/**

+  * @brief  Enable D1 Domain/CDomain debug during STOP mode

+  * @rmtoll DBGMCU_CR    DBGSTOP_D1/DBGSLEEP_CD     LL_DBGMCU_EnableD1DebugInStopMode

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStopMode(void)

+{

+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);

+}

+

+/**

+  * @brief  Disable D1 Domain/CDomain debug during STOP mode

+  * @rmtoll DBGMCU_CR    DBGSTOP_D1/DBGSLEEP_CD     LL_DBGMCU_DisableD1DebugInStopMode

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStopMode(void)

+{

+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD1);

+}

+

+/**

+  * @brief  Enable D1 Domain/CDomain debug during STANDBY mode

+  * @rmtoll DBGMCU_CR    DBGSTBY_D1/DBGSLEEP_CD     LL_DBGMCU_EnableD1DebugInStandbyMode

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_EnableD1DebugInStandbyMode(void)

+{

+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);

+}

+

+/**

+  * @brief  Disable D1 Domain/CDomain debug during STANDBY mode

+  * @rmtoll DBGMCU_CR    DBGSTBY_D1/DBGSLEEP_CD     LL_DBGMCU_DisableD1DebugInStandbyMode

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_DisableD1DebugInStandbyMode(void)

+{

+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD1);

+}

+

+#if defined (DUAL_CORE)

+/**

+  * @brief  Enable D2 Domain debug during SLEEP mode

+  * @rmtoll DBGMCU_CR    DBGSLEEP_D2     LL_DBGMCU_EnableD2DebugInSleepMode

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_EnableD2DebugInSleepMode(void)

+{

+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);

+}

+

+/**

+  * @brief  Disable D2 Domain debug during SLEEP mode

+  * @rmtoll DBGMCU_CR    DBGSLEEP_D2     LL_DBGMCU_DisableD2DebugInSleepMode

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_DisableD2DebugInSleepMode(void)

+{

+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEPD2);

+}

+

+/**

+  * @brief  Enable D2 Domain debug during STOP mode

+  * @rmtoll DBGMCU_CR    DBGSTOP_D2     LL_DBGMCU_EnableD2DebugInStopMode

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStopMode(void)

+{

+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);

+}

+

+/**

+  * @brief  Disable D2 Domain debug during STOP mode

+  * @rmtoll DBGMCU_CR    DBGSTOP_D2     LL_DBGMCU_DisableD2DebugInStopMode

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStopMode(void)

+{

+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD2);

+}

+

+/**

+  * @brief  Enable D2 Domain debug during STANDBY mode

+  * @rmtoll DBGMCU_CR    DBGSTBY_D2     LL_DBGMCU_EnableD2DebugInStandbyMode

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_EnableD2DebugInStandbyMode(void)

+{

+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);

+}

+

+/**

+  * @brief  Disable D2 Domain debug during STANDBY mode

+  * @rmtoll DBGMCU_CR    DBGSTBY_D2     LL_DBGMCU_DisableD2DebugInStandbyMode

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_DisableD2DebugInStandbyMode(void)

+{

+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD2);

+}

+#endif /* DUAL_CORE */

+

+

+/**

+  * @brief  Enable D3 Domain/SRDomain debug during STOP mode

+  * @rmtoll DBGMCU_CR    DBGSTOP_D3/DBGSTOP_SRD    LL_DBGMCU_EnableD3DebugInStopMode

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStopMode(void)

+{

+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);

+}

+

+/**

+  * @brief  Disable D3 Domain/SRDomain debug during STOP mode

+  * @rmtoll DBGMCU_CR    DBGSTOP_D3/DBGSTOP_SRD     LL_DBGMCU_DisableD3DebugInStopMode

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStopMode(void)

+{

+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOPD3);

+}

+

+/**

+  * @brief  Enable D3 Domain/SRDomain debug during STANDBY mode

+  * @rmtoll DBGMCU_CR    DBGSTBY_D3/DBGSTBY_SRD     LL_DBGMCU_EnableD3DebugInStandbyMode

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_EnableD3DebugInStandbyMode(void)

+{

+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);

+}

+

+/**

+  * @brief  Disable D3 Domain/SRDomain debug during STANDBY mode

+  * @rmtoll DBGMCU_CR    DBGSTBY_D3/DBGSTBY_SRD     LL_DBGMCU_DisableD3DebugInStandbyMode

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_DisableD3DebugInStandbyMode(void)

+{

+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBYD3);

+}

+

+/**

+  * @brief  Enable the trace port clock

+  * @rmtoll DBGMCU_CR    TRACECKEN     LL_DBGMCU_EnableTracePortClock

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_EnableTracePortClock(void)

+{

+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN);

+}

+

+/**

+  * @brief  Disable the trace port clock

+  * @rmtoll DBGMCU_CR    TRACECKEN     LL_DBGMCU_DisableTracePortClock

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_DisableTracePortClock(void)

+{

+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRACECKEN);

+}

+

+/**

+  * @brief  Enable the Domain1/CDomain debug clock enable

+  * @rmtoll DBGMCU_CR    CKD1EN/CKCDEN     LL_DBGMCU_EnableD1DebugClock

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_EnableD1DebugClock(void)

+{

+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN);

+}

+

+/**

+  * @brief  Disable the Domain1/CDomain debug clock enable

+  * @rmtoll DBGMCU_CR    CKD1EN/CKCDEN     LL_DBGMCU_DisableD1DebugClock

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_DisableD1DebugClock(void)

+{

+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD1EN);

+}

+

+/**

+  * @brief  Enable the Domain3/SRDomain debug clock enable

+  * @rmtoll DBGMCU_CR    CKD3EN/CKSRDEN     LL_DBGMCU_EnableD3DebugClock

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_EnableD3DebugClock(void)

+{

+  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN);

+}

+

+/**

+  * @brief  Disable the Domain3/SRDomain debug clock enable

+  * @rmtoll DBGMCU_CR    CKD3EN/CKSRDEN    LL_DBGMCU_DisableD3DebugClock

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_DisableD3DebugClock(void)

+{

+  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_CKD3EN);

+}

+

+#define LL_DBGMCU_TRGIO_INPUT_DIRECTION   0U

+#define LL_DBGMCU_TRGIO_OUTPUT_DIRECTION  DBGMCU_CR_DBG_TRGOEN

+/**

+  * @brief  Set the direction of the bi-directional trigger pin TRGIO

+  * @rmtoll DBGMCU_CR    TRGOEN    LL_DBGMCU_SetExternalTriggerPinDirection\n

+  * @param  PinDirection This parameter can be one of the following values:

+  *         @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION

+  *         @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_SetExternalTriggerPinDirection(uint32_t PinDirection)

+{

+  MODIFY_REG(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN, PinDirection);

+}

+

+/**

+  * @brief  Get the direction of the bi-directional trigger pin TRGIO

+  * @rmtoll DBGMCU_CR    TRGOEN    LL_DBGMCU_GetExternalTriggerPinDirection\n

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_DBGMCU_TRGIO_INPUT_DIRECTION

+  *         @arg @ref LL_DBGMCU_TRGIO_OUTPUT_DIRECTION

+  */

+__STATIC_INLINE uint32_t LL_DBGMCU_GetExternalTriggerPinDirection(void)

+{

+  return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_DBG_TRGOEN));

+}

+

+/**

+  * @brief  Freeze APB1 group1 peripherals

+  * @rmtoll DBGMCU_APB1LFZ1   TIM2      LL_DBGMCU_APB1_GRP1_FreezePeriph\n

+  *         DBGMCU_APB1LFZ1   TIM3      LL_DBGMCU_APB1_GRP1_FreezePeriph\n

+  *         DBGMCU_APB1LFZ1   TIM4      LL_DBGMCU_APB1_GRP1_FreezePeriph\n

+  *         DBGMCU_APB1LFZ1   TIM5      LL_DBGMCU_APB1_GRP1_FreezePeriph\n

+  *         DBGMCU_APB1LFZ1   TIM6      LL_DBGMCU_APB1_GRP1_FreezePeriph\n

+  *         DBGMCU_APB1LFZ1   TIM7      LL_DBGMCU_APB1_GRP1_FreezePeriph\n

+  *         DBGMCU_APB1LFZ1   TIM12     LL_DBGMCU_APB1_GRP1_FreezePeriph\n

+  *         DBGMCU_APB1LFZ1   TIM13     LL_DBGMCU_APB1_GRP1_FreezePeriph\n

+  *         DBGMCU_APB1LFZ1   TIM14     LL_DBGMCU_APB1_GRP1_FreezePeriph\n

+  *         DBGMCU_APB1LFZ1   LPTIM1    LL_DBGMCU_APB1_GRP1_FreezePeriph\n

+  *         DBGMCU_APB1LFZ1   I2C1      LL_DBGMCU_APB1_GRP1_FreezePeriph\n

+  *         DBGMCU_APB1LFZ1   I2C2      LL_DBGMCU_APB1_GRP1_FreezePeriph\n

+  *         DBGMCU_APB1LFZ1   I2C3      LL_DBGMCU_APB1_GRP1_FreezePeriph\n

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP

+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP

+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP

+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP

+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP

+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP

+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP

+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP

+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP

+  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP

+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP

+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP

+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs)

+{

+  SET_BIT(DBGMCU->APB1LFZ1, Periphs);

+}

+

+/**

+  * @brief  Unfreeze APB1 peripherals (group1 peripherals)

+  * @rmtoll DBGMCU_APB1LFZ1   TIM2      LL_DBGMCU_APB1_GRP1_FreezePeriph\n

+  *         DBGMCU_APB1LFZ1   TIM3      LL_DBGMCU_APB1_GRP1_FreezePeriph\n

+  *         DBGMCU_APB1LFZ1   TIM4      LL_DBGMCU_APB1_GRP1_FreezePeriph\n

+  *         DBGMCU_APB1LFZ1   TIM5      LL_DBGMCU_APB1_GRP1_FreezePeriph\n

+  *         DBGMCU_APB1LFZ1   TIM6      LL_DBGMCU_APB1_GRP1_FreezePeriph\n

+  *         DBGMCU_APB1LFZ1   TIM7      LL_DBGMCU_APB1_GRP1_FreezePeriph\n

+  *         DBGMCU_APB1LFZ1   TIM12     LL_DBGMCU_APB1_GRP1_FreezePeriph\n

+  *         DBGMCU_APB1LFZ1   TIM13     LL_DBGMCU_APB1_GRP1_FreezePeriph\n

+  *         DBGMCU_APB1LFZ1   TIM14     LL_DBGMCU_APB1_GRP1_FreezePeriph\n

+  *         DBGMCU_APB1LFZ1   LPTIM1    LL_DBGMCU_APB1_GRP1_FreezePeriph\n

+  *         DBGMCU_APB1LFZ1   I2C1      LL_DBGMCU_APB1_GRP1_FreezePeriph\n

+  *         DBGMCU_APB1LFZ1   I2C2      LL_DBGMCU_APB1_GRP1_FreezePeriph\n

+  *         DBGMCU_APB1LFZ1   I2C3      LL_DBGMCU_APB1_GRP1_FreezePeriph\n

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP

+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP

+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP

+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP

+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP

+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP

+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP

+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP

+  *         @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP

+  *         @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP

+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP

+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP

+  *         @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs)

+{

+  CLEAR_BIT(DBGMCU->APB1LFZ1, Periphs);

+}

+

+/**

+  * @brief  Freeze APB1 group2 peripherals

+  * @rmtoll DBGMCU_APB1HFZ1   FDCAN   LL_DBGMCU_APB1_GRP2_FreezePeriph\n

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs)

+{

+  SET_BIT(DBGMCU->APB1HFZ1, Periphs);

+}

+

+/**

+  * @brief  Unfreeze APB1 group2 peripherals

+  * @rmtoll DBGMCU_APB1HFZ1   FDCAN   LL_DBGMCU_APB1_GRP2_UnFreezePeriph\n

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_DBGMCU_APB1_GRP2_FDCAN_STOP

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs)

+{

+  CLEAR_BIT(DBGMCU->APB1HFZ1, Periphs);

+}

+

+/**

+  * @brief  Freeze APB2 peripherals

+  * @rmtoll DBGMCU_APB2FZ1    TIM1     LL_DBGMCU_APB2_GRP1_FreezePeriph\n

+  *         DBGMCU_APB2FZ1    TIM8     LL_DBGMCU_APB2_GRP1_FreezePeriph\n

+  *         DBGMCU_APB2FZ1    TIM15    LL_DBGMCU_APB2_GRP1_FreezePeriph\n

+  *         DBGMCU_APB2FZ1    TIM16    LL_DBGMCU_APB2_GRP1_FreezePeriph\n

+  *         DBGMCU_APB2FZ1    TIM17    LL_DBGMCU_APB2_GRP1_FreezePeriph

+  *         DBGMCU_APB2FZ1    HRTIM    LL_DBGMCU_APB2_GRP1_FreezePeriph

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP

+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP

+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP

+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP

+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP

+  *         @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs)

+{

+  SET_BIT(DBGMCU->APB2FZ1, Periphs);

+}

+

+/**

+  * @brief  Unfreeze APB2 peripherals

+  * @rmtoll DBGMCU_APB2FZ1    TIM1     LL_DBGMCU_APB2_GRP1_FreezePeriph\n

+  *         DBGMCU_APB2FZ1    TIM8     LL_DBGMCU_APB2_GRP1_FreezePeriph\n

+  *         DBGMCU_APB2FZ1    TIM15    LL_DBGMCU_APB2_GRP1_FreezePeriph\n

+  *         DBGMCU_APB2FZ1    TIM16    LL_DBGMCU_APB2_GRP1_FreezePeriph\n

+  *         DBGMCU_APB2FZ1    TIM17    LL_DBGMCU_APB2_GRP1_FreezePeriph

+  *         DBGMCU_APB2FZ1    HRTIM    LL_DBGMCU_APB2_GRP1_FreezePeriph

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP

+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP

+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP

+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP

+  *         @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP

+  *         @arg @ref LL_DBGMCU_APB2_GRP1_HRTIM_STOP

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs)

+{

+  CLEAR_BIT(DBGMCU->APB2FZ1, Periphs);

+}

+

+/**

+  * @brief  Freeze APB3 peripherals

+  * @rmtoll DBGMCU_APB3FZ1    WWDG1     LL_DBGMCU_APB3_GRP1_FreezePeriph\n

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs)

+{

+  SET_BIT(DBGMCU->APB3FZ1, Periphs);

+}

+

+/**

+  * @brief  Unfreeze APB3 peripherals

+  * @rmtoll DBGMCU_APB3FZ1    WWDG1     LL_DBGMCU_APB3_GRP1_UnFreezePeriph\n

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_DBGMCU_APB3_GRP1_WWDG1_STOP

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs)

+{

+  CLEAR_BIT(DBGMCU->APB3FZ1, Periphs);

+}

+

+/**

+  * @brief  Freeze APB4 peripherals

+  * @rmtoll DBGMCU_APB4FZ1    I2C4      LL_DBGMCU_APB4_GRP1_FreezePeriph\n

+  * @rmtoll DBGMCU_APB4FZ1    LPTIM2    LL_DBGMCU_APB4_GRP1_FreezePeriph\n

+  * @rmtoll DBGMCU_APB4FZ1    LPTIM3    LL_DBGMCU_APB4_GRP1_FreezePeriph\n

+  * @rmtoll DBGMCU_APB4FZ1    LPTIM4    LL_DBGMCU_APB4_GRP1_FreezePeriph\n

+  * @rmtoll DBGMCU_APB4FZ1    LPTIM5    LL_DBGMCU_APB4_GRP1_FreezePeriph\n

+  * @rmtoll DBGMCU_APB4FZ1    RTC       LL_DBGMCU_APB4_GRP1_FreezePeriph\n

+  * @rmtoll DBGMCU_APB4FZ1    WDGLSD1   LL_DBGMCU_APB4_GRP1_FreezePeriph\n

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP

+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP

+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP

+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP

+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP

+  *         @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP

+  *         @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_APB4_GRP1_FreezePeriph(uint32_t Periphs)

+{

+  SET_BIT(DBGMCU->APB4FZ1, Periphs);

+}

+

+/**

+  * @brief  Unfreeze APB4 peripherals

+  * @rmtoll DBGMCU_APB4FZ1    I2C4      LL_DBGMCU_APB4_GRP1_FreezePeriph\n

+  * @rmtoll DBGMCU_APB4FZ1    LPTIM2    LL_DBGMCU_APB4_GRP1_FreezePeriph\n

+  * @rmtoll DBGMCU_APB4FZ1    LPTIM3    LL_DBGMCU_APB4_GRP1_FreezePeriph\n

+  * @rmtoll DBGMCU_APB4FZ1    LPTIM4    LL_DBGMCU_APB4_GRP1_FreezePeriph\n

+  * @rmtoll DBGMCU_APB4FZ1    LPTIM5    LL_DBGMCU_APB4_GRP1_FreezePeriph\n

+  * @rmtoll DBGMCU_APB4FZ1    RTC       LL_DBGMCU_APB4_GRP1_FreezePeriph\n

+  * @rmtoll DBGMCU_APB4FZ1    WDGLSD1   LL_DBGMCU_APB4_GRP1_FreezePeriph\n

+  * @param  Periphs This parameter can be a combination of the following values:

+  *         @arg @ref LL_DBGMCU_APB4_GRP1_I2C4_STOP

+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM2_STOP

+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM3_STOP

+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM4_STOP

+  *         @arg @ref LL_DBGMCU_APB4_GRP1_LPTIM5_STOP

+  *         @arg @ref LL_DBGMCU_APB4_GRP1_RTC_STOP

+  *         @arg @ref LL_DBGMCU_APB4_GRP1_IWDG1_STOP

+  * @retval None

+  */

+__STATIC_INLINE void LL_DBGMCU_APB4_GRP1_UnFreezePeriph(uint32_t Periphs)

+{

+  CLEAR_BIT(DBGMCU->APB4FZ1, Periphs);

+}

+/**

+  * @}

+  */

+

+/** @defgroup SYSTEM_LL_EF_FLASH FLASH

+  * @{

+  */

+

+/**

+  * @brief  Set FLASH Latency

+  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_SetLatency

+  * @param  Latency This parameter can be one of the following values:

+  *         @arg @ref LL_FLASH_LATENCY_0

+  *         @arg @ref LL_FLASH_LATENCY_1

+  *         @arg @ref LL_FLASH_LATENCY_2

+  *         @arg @ref LL_FLASH_LATENCY_3

+  *         @arg @ref LL_FLASH_LATENCY_4

+  *         @arg @ref LL_FLASH_LATENCY_5

+  *         @arg @ref LL_FLASH_LATENCY_6

+  *         @arg @ref LL_FLASH_LATENCY_7

+  * @retval None

+  */

+__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency)

+{

+  MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency);

+}

+

+/**

+  * @brief  Get FLASH Latency

+  * @rmtoll FLASH_ACR    LATENCY       LL_FLASH_GetLatency

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_FLASH_LATENCY_0

+  *         @arg @ref LL_FLASH_LATENCY_1

+  *         @arg @ref LL_FLASH_LATENCY_2

+  *         @arg @ref LL_FLASH_LATENCY_3

+  *         @arg @ref LL_FLASH_LATENCY_4

+  *         @arg @ref LL_FLASH_LATENCY_5

+  *         @arg @ref LL_FLASH_LATENCY_6

+  *         @arg @ref LL_FLASH_LATENCY_7

+  */

+__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void)

+{

+  return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY));

+}

+

+/**

+  * @}

+  */

+

+#if defined(DUAL_CORE)

+/** @defgroup SYSTEM_LL_EF_ART ART

+  * @{

+  */

+

+/**

+  * @brief  Enable the Cortex-M4 ART cache.

+  * @rmtoll ART_CTR    EN   LL_ART_Enable

+  * @retval None

+  */

+__STATIC_INLINE void LL_ART_Enable(void)

+{

+ SET_BIT(ART->CTR, ART_CTR_EN);

+}

+

+/**

+  * @brief  Disable the Cortex-M4 ART cache.

+  * @rmtoll ART_CTR    EN   LL_ART_Disable

+  * @retval None

+  */

+__STATIC_INLINE void LL_ART_Disable(void)

+{

+ CLEAR_BIT(ART->CTR, ART_CTR_EN);

+}

+

+/**

+  * @brief  Check if the Cortex-M4 ART cache is enabled

+  * @rmtoll ART_CTR   EN    LL_ART_IsEnabled

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_ART_IsEnabled(void)

+{

+  return ((READ_BIT(ART->CTR, ART_CTR_EN) == ART_CTR_EN) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set the Cortex-M4 ART cache Base Address.

+  * @rmtoll ART_CTR    PCACHEADDR   LL_ART_SetBaseAddress

+  * @param  BaseAddress Specifies the Base address of 1 Mbyte address page (cacheable page)

+            from which the ART accelerator loads code to the cache.

+  * @retval None

+  */

+__STATIC_INLINE void LL_ART_SetBaseAddress(uint32_t BaseAddress)

+{

+ MODIFY_REG(ART->CTR, ART_CTR_PCACHEADDR, (((BaseAddress) >> 12U) & 0x000FFF00UL));

+}

+

+/**

+  * @brief  Get the Cortex-M4 ART cache Base Address.

+  * @rmtoll ART_CTR    PCACHEADDR   LL_ART_GetBaseAddress

+  * @retval the Base address of 1 Mbyte address page (cacheable page)

+            from which the ART accelerator loads code to the cache

+  */

+__STATIC_INLINE uint32_t LL_ART_GetBaseAddress(void)

+{

+  return (uint32_t)(READ_BIT(ART->CTR, ART_CTR_PCACHEADDR) << 12U);

+}

+#endif /* DUAL_CORE */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* __STM32H7xx_LL_SYSTEM_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_tim.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_tim.h
new file mode 100644
index 0000000000..4d726a844e
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_tim.h
@@ -0,0 +1,4929 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_tim.h

+  * @author  MCD Application Team

+  * @brief   Header file of TIM LL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef __STM32H7xx_LL_TIM_H

+#define __STM32H7xx_LL_TIM_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17)

+

+/** @defgroup TIM_LL TIM

+  * @{

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/** @defgroup TIM_LL_Private_Variables TIM Private Variables

+  * @{

+  */

+static const uint8_t OFFSET_TAB_CCMRx[] =

+{

+  0x00U,   /* 0: TIMx_CH1  */

+  0x00U,   /* 1: TIMx_CH1N */

+  0x00U,   /* 2: TIMx_CH2  */

+  0x00U,   /* 3: TIMx_CH2N */

+  0x04U,   /* 4: TIMx_CH3  */

+  0x04U,   /* 5: TIMx_CH3N */

+  0x04U,   /* 6: TIMx_CH4  */

+  0x3CU,   /* 7: TIMx_CH5  */

+  0x3CU    /* 8: TIMx_CH6  */

+};

+

+static const uint8_t SHIFT_TAB_OCxx[] =

+{

+  0U,            /* 0: OC1M, OC1FE, OC1PE */

+  0U,            /* 1: - NA */

+  8U,            /* 2: OC2M, OC2FE, OC2PE */

+  0U,            /* 3: - NA */

+  0U,            /* 4: OC3M, OC3FE, OC3PE */

+  0U,            /* 5: - NA */

+  8U,            /* 6: OC4M, OC4FE, OC4PE */

+  0U,            /* 7: OC5M, OC5FE, OC5PE */

+  8U             /* 8: OC6M, OC6FE, OC6PE */

+};

+

+static const uint8_t SHIFT_TAB_ICxx[] =

+{

+  0U,            /* 0: CC1S, IC1PSC, IC1F */

+  0U,            /* 1: - NA */

+  8U,            /* 2: CC2S, IC2PSC, IC2F */

+  0U,            /* 3: - NA */

+  0U,            /* 4: CC3S, IC3PSC, IC3F */

+  0U,            /* 5: - NA */

+  8U,            /* 6: CC4S, IC4PSC, IC4F */

+  0U,            /* 7: - NA */

+  0U             /* 8: - NA */

+};

+

+static const uint8_t SHIFT_TAB_CCxP[] =

+{

+  0U,            /* 0: CC1P */

+  2U,            /* 1: CC1NP */

+  4U,            /* 2: CC2P */

+  6U,            /* 3: CC2NP */

+  8U,            /* 4: CC3P */

+  10U,           /* 5: CC3NP */

+  12U,           /* 6: CC4P */

+  16U,           /* 7: CC5P */

+  20U            /* 8: CC6P */

+};

+

+static const uint8_t SHIFT_TAB_OISx[] =

+{

+  0U,            /* 0: OIS1 */

+  1U,            /* 1: OIS1N */

+  2U,            /* 2: OIS2 */

+  3U,            /* 3: OIS2N */

+  4U,            /* 4: OIS3 */

+  5U,            /* 5: OIS3N */

+  6U,            /* 6: OIS4 */

+  8U,            /* 7: OIS5 */

+  10U            /* 8: OIS6 */

+};

+/**

+  * @}

+  */

+

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup TIM_LL_Private_Constants TIM Private Constants

+  * @{

+  */

+

+#if   defined(TIM_BREAK_INPUT_SUPPORT)

+/* Defines used for the bit position in the register and perform offsets */

+#define TIM_POSITION_BRK_SOURCE            (POSITION_VAL(Source) & 0x1FUL)

+

+/* Generic bit definitions for TIMx_AF1 register */

+#define TIMx_AF1_BKINP     TIM1_AF1_BKINP     /*!< BRK BKIN input polarity */

+#define TIMx_AF1_ETRSEL    TIM1_AF1_ETRSEL    /*!< TIMx ETR source selection */

+#endif /* TIM_BREAK_INPUT_SUPPORT */

+

+

+/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */

+#define DT_DELAY_1 ((uint8_t)0x7F)

+#define DT_DELAY_2 ((uint8_t)0x3F)

+#define DT_DELAY_3 ((uint8_t)0x1F)

+#define DT_DELAY_4 ((uint8_t)0x1F)

+

+/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */

+#define DT_RANGE_1 ((uint8_t)0x00)

+#define DT_RANGE_2 ((uint8_t)0x80)

+#define DT_RANGE_3 ((uint8_t)0xC0)

+#define DT_RANGE_4 ((uint8_t)0xE0)

+

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup TIM_LL_Private_Macros TIM Private Macros

+  * @{

+  */

+/** @brief  Convert channel id into channel index.

+  * @param  __CHANNEL__ This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CHANNEL_CH1

+  *         @arg @ref LL_TIM_CHANNEL_CH1N

+  *         @arg @ref LL_TIM_CHANNEL_CH2

+  *         @arg @ref LL_TIM_CHANNEL_CH2N

+  *         @arg @ref LL_TIM_CHANNEL_CH3

+  *         @arg @ref LL_TIM_CHANNEL_CH3N

+  *         @arg @ref LL_TIM_CHANNEL_CH4

+  *         @arg @ref LL_TIM_CHANNEL_CH5

+  *         @arg @ref LL_TIM_CHANNEL_CH6

+  * @retval none

+  */

+#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \

+  (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\

+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\

+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\

+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\

+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\

+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\

+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\

+   ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)

+

+/** @brief  Calculate the deadtime sampling period(in ps).

+  * @param  __TIMCLK__ timer input clock frequency (in Hz).

+  * @param  __CKD__ This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1

+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2

+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4

+  * @retval none

+  */

+#define TIM_CALC_DTS(__TIMCLK__, __CKD__)                                                        \

+  (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__))         : \

+   ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \

+   ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))

+/**

+  * @}

+  */

+

+

+/* Exported types ------------------------------------------------------------*/

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure

+  * @{

+  */

+

+/**

+  * @brief  TIM Time Base configuration structure definition.

+  */

+typedef struct

+{

+  uint16_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.

+                                   This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.

+

+                                   This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/

+

+  uint32_t CounterMode;       /*!< Specifies the counter mode.

+                                   This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.

+

+                                   This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/

+

+  uint32_t Autoreload;        /*!< Specifies the auto reload value to be loaded into the active

+                                   Auto-Reload Register at the next update event.

+                                   This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.

+                                   Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.

+

+                                   This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/

+

+  uint32_t ClockDivision;     /*!< Specifies the clock division.

+                                   This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.

+

+                                   This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/

+

+  uint32_t RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter

+                                   reaches zero, an update event is generated and counting restarts

+                                   from the RCR value (N).

+                                   This means in PWM mode that (N+1) corresponds to:

+                                      - the number of PWM periods in edge-aligned mode

+                                      - the number of half PWM period in center-aligned mode

+                                   GP timers: this parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.

+                                   Advanced timers: this parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

+

+                                   This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/

+} LL_TIM_InitTypeDef;

+

+/**

+  * @brief  TIM Output Compare configuration structure definition.

+  */

+typedef struct

+{

+  uint32_t OCMode;        /*!< Specifies the output mode.

+                               This parameter can be a value of @ref TIM_LL_EC_OCMODE.

+

+                               This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/

+

+  uint32_t OCState;       /*!< Specifies the TIM Output Compare state.

+                               This parameter can be a value of @ref TIM_LL_EC_OCSTATE.

+

+                               This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/

+

+  uint32_t OCNState;      /*!< Specifies the TIM complementary Output Compare state.

+                               This parameter can be a value of @ref TIM_LL_EC_OCSTATE.

+

+                               This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/

+

+  uint32_t CompareValue;  /*!< Specifies the Compare value to be loaded into the Capture Compare Register.

+                               This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.

+

+                               This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/

+

+  uint32_t OCPolarity;    /*!< Specifies the output polarity.

+                               This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.

+

+                               This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/

+

+  uint32_t OCNPolarity;   /*!< Specifies the complementary output polarity.

+                               This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.

+

+                               This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/

+

+

+  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.

+                               This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.

+

+                               This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/

+

+  uint32_t OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.

+                               This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.

+

+                               This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/

+} LL_TIM_OC_InitTypeDef;

+

+/**

+  * @brief  TIM Input Capture configuration structure definition.

+  */

+

+typedef struct

+{

+

+  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.

+                               This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.

+

+                               This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/

+

+  uint32_t ICActiveInput; /*!< Specifies the input.

+                               This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.

+

+                               This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/

+

+  uint32_t ICPrescaler;   /*!< Specifies the Input Capture Prescaler.

+                               This parameter can be a value of @ref TIM_LL_EC_ICPSC.

+

+                               This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/

+

+  uint32_t ICFilter;      /*!< Specifies the input capture filter.

+                               This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.

+

+                               This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/

+} LL_TIM_IC_InitTypeDef;

+

+

+/**

+  * @brief  TIM Encoder interface configuration structure definition.

+  */

+typedef struct

+{

+  uint32_t EncoderMode;     /*!< Specifies the encoder resolution (x2 or x4).

+                                 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.

+

+                                 This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/

+

+  uint32_t IC1Polarity;     /*!< Specifies the active edge of TI1 input.

+                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.

+

+                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/

+

+  uint32_t IC1ActiveInput;  /*!< Specifies the TI1 input source

+                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.

+

+                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/

+

+  uint32_t IC1Prescaler;    /*!< Specifies the TI1 input prescaler value.

+                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.

+

+                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/

+

+  uint32_t IC1Filter;       /*!< Specifies the TI1 input filter.

+                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.

+

+                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/

+

+  uint32_t IC2Polarity;      /*!< Specifies the active edge of TI2 input.

+                                 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.

+

+                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/

+

+  uint32_t IC2ActiveInput;  /*!< Specifies the TI2 input source

+                                 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.

+

+                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/

+

+  uint32_t IC2Prescaler;    /*!< Specifies the TI2 input prescaler value.

+                                 This parameter can be a value of @ref TIM_LL_EC_ICPSC.

+

+                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/

+

+  uint32_t IC2Filter;       /*!< Specifies the TI2 input filter.

+                                 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.

+

+                                 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/

+

+} LL_TIM_ENCODER_InitTypeDef;

+

+/**

+  * @brief  TIM Hall sensor interface configuration structure definition.

+  */

+typedef struct

+{

+

+  uint32_t IC1Polarity;        /*!< Specifies the active edge of TI1 input.

+                                    This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.

+

+                                    This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/

+

+  uint32_t IC1Prescaler;       /*!< Specifies the TI1 input prescaler value.

+                                    Prescaler must be set to get a maximum counter period longer than the

+                                    time interval between 2 consecutive changes on the Hall inputs.

+                                    This parameter can be a value of @ref TIM_LL_EC_ICPSC.

+

+                                    This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/

+

+  uint32_t IC1Filter;          /*!< Specifies the TI1 input filter.

+                                    This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.

+

+                                    This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/

+

+  uint32_t CommutationDelay;   /*!< Specifies the compare value to be loaded into the Capture Compare Register.

+                                    A positive pulse (TRGO event) is generated with a programmable delay every time

+                                    a change occurs on the Hall inputs.

+                                    This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.

+

+                                    This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/

+} LL_TIM_HALLSENSOR_InitTypeDef;

+

+/**

+  * @brief  BDTR (Break and Dead Time) structure definition

+  */

+typedef struct

+{

+  uint32_t OSSRState;            /*!< Specifies the Off-State selection used in Run mode.

+                                      This parameter can be a value of @ref TIM_LL_EC_OSSR

+

+                                      This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()

+

+                                      @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */

+

+  uint32_t OSSIState;            /*!< Specifies the Off-State used in Idle state.

+                                      This parameter can be a value of @ref TIM_LL_EC_OSSI

+

+                                      This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()

+

+                                      @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */

+

+  uint32_t LockLevel;            /*!< Specifies the LOCK level parameters.

+                                      This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL

+

+                                      @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register

+                                            has been written, their content is frozen until the next reset.*/

+

+  uint8_t DeadTime;              /*!< Specifies the delay time between the switching-off and the

+                                      switching-on of the outputs.

+                                      This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.

+

+                                      This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()

+

+                                      @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */

+

+  uint16_t BreakState;           /*!< Specifies whether the TIM Break input is enabled or not.

+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE

+

+                                      This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()

+

+                                      @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */

+

+  uint32_t BreakPolarity;        /*!< Specifies the TIM Break Input pin polarity.

+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY

+

+                                      This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()

+

+                                      @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */

+

+  uint32_t BreakFilter;          /*!< Specifies the TIM Break Filter.

+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER

+

+                                      This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()

+

+                                      @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */

+

+  uint32_t Break2State;          /*!< Specifies whether the TIM Break2 input is enabled or not.

+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE

+

+                                      This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()

+

+                                      @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */

+

+  uint32_t Break2Polarity;        /*!< Specifies the TIM Break2 Input pin polarity.

+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY

+

+                                      This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()

+

+                                      @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */

+

+  uint32_t Break2Filter;          /*!< Specifies the TIM Break2 Filter.

+                                      This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER

+

+                                      This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()

+

+                                      @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */

+

+  uint32_t AutomaticOutput;      /*!< Specifies whether the TIM Automatic Output feature is enabled or not.

+                                      This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE

+

+                                      This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()

+

+                                      @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */

+} LL_TIM_BDTR_InitTypeDef;

+

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants

+  * @{

+  */

+

+/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines

+  * @brief    Flags defines which can be used with LL_TIM_ReadReg function.

+  * @{

+  */

+#define LL_TIM_SR_UIF                          TIM_SR_UIF           /*!< Update interrupt flag */

+#define LL_TIM_SR_CC1IF                        TIM_SR_CC1IF         /*!< Capture/compare 1 interrupt flag */

+#define LL_TIM_SR_CC2IF                        TIM_SR_CC2IF         /*!< Capture/compare 2 interrupt flag */

+#define LL_TIM_SR_CC3IF                        TIM_SR_CC3IF         /*!< Capture/compare 3 interrupt flag */

+#define LL_TIM_SR_CC4IF                        TIM_SR_CC4IF         /*!< Capture/compare 4 interrupt flag */

+#define LL_TIM_SR_CC5IF                        TIM_SR_CC5IF         /*!< Capture/compare 5 interrupt flag */

+#define LL_TIM_SR_CC6IF                        TIM_SR_CC6IF         /*!< Capture/compare 6 interrupt flag */

+#define LL_TIM_SR_COMIF                        TIM_SR_COMIF         /*!< COM interrupt flag */

+#define LL_TIM_SR_TIF                          TIM_SR_TIF           /*!< Trigger interrupt flag */

+#define LL_TIM_SR_BIF                          TIM_SR_BIF           /*!< Break interrupt flag */

+#define LL_TIM_SR_B2IF                         TIM_SR_B2IF          /*!< Second break interrupt flag */

+#define LL_TIM_SR_CC1OF                        TIM_SR_CC1OF         /*!< Capture/Compare 1 overcapture flag */

+#define LL_TIM_SR_CC2OF                        TIM_SR_CC2OF         /*!< Capture/Compare 2 overcapture flag */

+#define LL_TIM_SR_CC3OF                        TIM_SR_CC3OF         /*!< Capture/Compare 3 overcapture flag */

+#define LL_TIM_SR_CC4OF                        TIM_SR_CC4OF         /*!< Capture/Compare 4 overcapture flag */

+#define LL_TIM_SR_SBIF                         TIM_SR_SBIF          /*!< System Break interrupt flag  */

+/**

+  * @}

+  */

+

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable

+  * @{

+  */

+#define LL_TIM_BREAK_DISABLE            0x00000000U             /*!< Break function disabled */

+#define LL_TIM_BREAK_ENABLE             TIM_BDTR_BKE            /*!< Break function enabled */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable

+  * @{

+  */

+#define LL_TIM_BREAK2_DISABLE            0x00000000U              /*!< Break2 function disabled */

+#define LL_TIM_BREAK2_ENABLE             TIM_BDTR_BK2E            /*!< Break2 function enabled */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable

+  * @{

+  */

+#define LL_TIM_AUTOMATICOUTPUT_DISABLE         0x00000000U             /*!< MOE can be set only by software */

+#define LL_TIM_AUTOMATICOUTPUT_ENABLE          TIM_BDTR_AOE            /*!< MOE can be set by software or automatically at the next update event */

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/** @defgroup TIM_LL_EC_IT IT Defines

+  * @brief    IT defines which can be used with LL_TIM_ReadReg and  LL_TIM_WriteReg functions.

+  * @{

+  */

+#define LL_TIM_DIER_UIE                        TIM_DIER_UIE         /*!< Update interrupt enable */

+#define LL_TIM_DIER_CC1IE                      TIM_DIER_CC1IE       /*!< Capture/compare 1 interrupt enable */

+#define LL_TIM_DIER_CC2IE                      TIM_DIER_CC2IE       /*!< Capture/compare 2 interrupt enable */

+#define LL_TIM_DIER_CC3IE                      TIM_DIER_CC3IE       /*!< Capture/compare 3 interrupt enable */

+#define LL_TIM_DIER_CC4IE                      TIM_DIER_CC4IE       /*!< Capture/compare 4 interrupt enable */

+#define LL_TIM_DIER_COMIE                      TIM_DIER_COMIE       /*!< COM interrupt enable */

+#define LL_TIM_DIER_TIE                        TIM_DIER_TIE         /*!< Trigger interrupt enable */

+#define LL_TIM_DIER_BIE                        TIM_DIER_BIE         /*!< Break interrupt enable */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source

+  * @{

+  */

+#define LL_TIM_UPDATESOURCE_REGULAR            0x00000000U          /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */

+#define LL_TIM_UPDATESOURCE_COUNTER            TIM_CR1_URS          /*!< Only counter overflow/underflow generates an update request */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode

+  * @{

+  */

+#define LL_TIM_ONEPULSEMODE_SINGLE             TIM_CR1_OPM          /*!< Counter is not stopped at update event */

+#define LL_TIM_ONEPULSEMODE_REPETITIVE         0x00000000U          /*!< Counter stops counting at the next update event */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode

+  * @{

+  */

+#define LL_TIM_COUNTERMODE_UP                  0x00000000U          /*!<Counter used as upcounter */

+#define LL_TIM_COUNTERMODE_DOWN                TIM_CR1_DIR          /*!< Counter used as downcounter */

+#define LL_TIM_COUNTERMODE_CENTER_UP           TIM_CR1_CMS_0        /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting down. */

+#define LL_TIM_COUNTERMODE_CENTER_DOWN         TIM_CR1_CMS_1        /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up */

+#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN      TIM_CR1_CMS          /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels  are set only when the counter is counting up or down. */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division

+  * @{

+  */

+#define LL_TIM_CLOCKDIVISION_DIV1              0x00000000U          /*!< tDTS=tCK_INT */

+#define LL_TIM_CLOCKDIVISION_DIV2              TIM_CR1_CKD_0        /*!< tDTS=2*tCK_INT */

+#define LL_TIM_CLOCKDIVISION_DIV4              TIM_CR1_CKD_1        /*!< tDTS=4*tCK_INT */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction

+  * @{

+  */

+#define LL_TIM_COUNTERDIRECTION_UP             0x00000000U          /*!< Timer counter counts up */

+#define LL_TIM_COUNTERDIRECTION_DOWN           TIM_CR1_DIR          /*!< Timer counter counts down */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare  Update Source

+  * @{

+  */

+#define LL_TIM_CCUPDATESOURCE_COMG_ONLY        0x00000000U          /*!< Capture/compare control bits are updated by setting the COMG bit only */

+#define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI    TIM_CR2_CCUS         /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request

+  * @{

+  */

+#define LL_TIM_CCDMAREQUEST_CC                 0x00000000U          /*!< CCx DMA request sent when CCx event occurs */

+#define LL_TIM_CCDMAREQUEST_UPDATE             TIM_CR2_CCDS         /*!< CCx DMA requests sent when update event occurs */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level

+  * @{

+  */

+#define LL_TIM_LOCKLEVEL_OFF                   0x00000000U          /*!< LOCK OFF - No bit is write protected */

+#define LL_TIM_LOCKLEVEL_1                     TIM_BDTR_LOCK_0      /*!< LOCK Level 1 */

+#define LL_TIM_LOCKLEVEL_2                     TIM_BDTR_LOCK_1      /*!< LOCK Level 2 */

+#define LL_TIM_LOCKLEVEL_3                     TIM_BDTR_LOCK        /*!< LOCK Level 3 */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_CHANNEL Channel

+  * @{

+  */

+#define LL_TIM_CHANNEL_CH1                     TIM_CCER_CC1E     /*!< Timer input/output channel 1 */

+#define LL_TIM_CHANNEL_CH1N                    TIM_CCER_CC1NE    /*!< Timer complementary output channel 1 */

+#define LL_TIM_CHANNEL_CH2                     TIM_CCER_CC2E     /*!< Timer input/output channel 2 */

+#define LL_TIM_CHANNEL_CH2N                    TIM_CCER_CC2NE    /*!< Timer complementary output channel 2 */

+#define LL_TIM_CHANNEL_CH3                     TIM_CCER_CC3E     /*!< Timer input/output channel 3 */

+#define LL_TIM_CHANNEL_CH3N                    TIM_CCER_CC3NE    /*!< Timer complementary output channel 3 */

+#define LL_TIM_CHANNEL_CH4                     TIM_CCER_CC4E     /*!< Timer input/output channel 4 */

+#define LL_TIM_CHANNEL_CH5                     TIM_CCER_CC5E     /*!< Timer output channel 5 */

+#define LL_TIM_CHANNEL_CH6                     TIM_CCER_CC6E     /*!< Timer output channel 6 */

+/**

+  * @}

+  */

+

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup TIM_LL_EC_OCSTATE Output Configuration State

+  * @{

+  */

+#define LL_TIM_OCSTATE_DISABLE                 0x00000000U             /*!< OCx is not active */

+#define LL_TIM_OCSTATE_ENABLE                  TIM_CCER_CC1E           /*!< OCx signal is output on the corresponding output pin */

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode

+  * @{

+  */

+#define LL_TIM_OCMODE_FROZEN                   0x00000000U                                              /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */

+#define LL_TIM_OCMODE_ACTIVE                   TIM_CCMR1_OC1M_0                                         /*!<OCyREF is forced high on compare match*/

+#define LL_TIM_OCMODE_INACTIVE                 TIM_CCMR1_OC1M_1                                         /*!<OCyREF is forced low on compare match*/

+#define LL_TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF toggles on compare match*/

+#define LL_TIM_OCMODE_FORCED_INACTIVE          TIM_CCMR1_OC1M_2                                         /*!<OCyREF is forced low*/

+#define LL_TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0)                    /*!<OCyREF is forced high*/

+#define LL_TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1)                    /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive.  In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/

+#define LL_TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active.  In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/

+#define LL_TIM_OCMODE_RETRIG_OPM1              TIM_CCMR1_OC1M_3                                         /*!<Retrigerrable OPM mode 1*/

+#define LL_TIM_OCMODE_RETRIG_OPM2              (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0)                    /*!<Retrigerrable OPM mode 2*/

+#define LL_TIM_OCMODE_COMBINED_PWM1            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2)                    /*!<Combined PWM mode 1*/

+#define LL_TIM_OCMODE_COMBINED_PWM2            (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/

+#define LL_TIM_OCMODE_ASSYMETRIC_PWM1          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/

+#define LL_TIM_OCMODE_ASSYMETRIC_PWM2          (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M)                      /*!<Asymmetric PWM mode 2*/

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity

+  * @{

+  */

+#define LL_TIM_OCPOLARITY_HIGH                 0x00000000U                 /*!< OCxactive high*/

+#define LL_TIM_OCPOLARITY_LOW                  TIM_CCER_CC1P               /*!< OCxactive low*/

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State

+  * @{

+  */

+#define LL_TIM_OCIDLESTATE_LOW                 0x00000000U             /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/

+#define LL_TIM_OCIDLESTATE_HIGH                TIM_CR2_OIS1            /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5

+  * @{

+  */

+#define LL_TIM_GROUPCH5_NONE                   0x00000000U           /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */

+#define LL_TIM_GROUPCH5_OC1REFC                TIM_CCR5_GC5C1        /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */

+#define LL_TIM_GROUPCH5_OC2REFC                TIM_CCR5_GC5C2        /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */

+#define LL_TIM_GROUPCH5_OC3REFC                TIM_CCR5_GC5C3        /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection

+  * @{

+  */

+#define LL_TIM_ACTIVEINPUT_DIRECTTI            (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */

+#define LL_TIM_ACTIVEINPUT_INDIRECTTI          (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */

+#define LL_TIM_ACTIVEINPUT_TRC                 (TIM_CCMR1_CC1S << 16U)   /*!< ICx is mapped on TRC */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler

+  * @{

+  */

+#define LL_TIM_ICPSC_DIV1                      0x00000000U                    /*!< No prescaler, capture is done each time an edge is detected on the capture input */

+#define LL_TIM_ICPSC_DIV2                      (TIM_CCMR1_IC1PSC_0 << 16U)    /*!< Capture is done once every 2 events */

+#define LL_TIM_ICPSC_DIV4                      (TIM_CCMR1_IC1PSC_1 << 16U)    /*!< Capture is done once every 4 events */

+#define LL_TIM_ICPSC_DIV8                      (TIM_CCMR1_IC1PSC << 16U)      /*!< Capture is done once every 8 events */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter

+  * @{

+  */

+#define LL_TIM_IC_FILTER_FDIV1                 0x00000000U                                                        /*!< No filter, sampling is done at fDTS */

+#define LL_TIM_IC_FILTER_FDIV1_N2              (TIM_CCMR1_IC1F_0 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=2 */

+#define LL_TIM_IC_FILTER_FDIV1_N4              (TIM_CCMR1_IC1F_1 << 16U)                                          /*!< fSAMPLING=fCK_INT, N=4 */

+#define LL_TIM_IC_FILTER_FDIV1_N8              ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fCK_INT, N=8 */

+#define LL_TIM_IC_FILTER_FDIV2_N6              (TIM_CCMR1_IC1F_2 << 16U)                                          /*!< fSAMPLING=fDTS/2, N=6 */

+#define LL_TIM_IC_FILTER_FDIV2_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/2, N=8 */

+#define LL_TIM_IC_FILTER_FDIV4_N6              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/4, N=6 */

+#define LL_TIM_IC_FILTER_FDIV4_N8              ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/4, N=8 */

+#define LL_TIM_IC_FILTER_FDIV8_N6              (TIM_CCMR1_IC1F_3 << 16U)                                          /*!< fSAMPLING=fDTS/8, N=6 */

+#define LL_TIM_IC_FILTER_FDIV8_N8              ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U)                     /*!< fSAMPLING=fDTS/8, N=8 */

+#define LL_TIM_IC_FILTER_FDIV16_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U)                     /*!< fSAMPLING=fDTS/16, N=5 */

+#define LL_TIM_IC_FILTER_FDIV16_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/16, N=6 */

+#define LL_TIM_IC_FILTER_FDIV16_N8             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U)                     /*!< fSAMPLING=fDTS/16, N=8 */

+#define LL_TIM_IC_FILTER_FDIV32_N5             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U)  /*!< fSAMPLING=fDTS/32, N=5 */

+#define LL_TIM_IC_FILTER_FDIV32_N6             ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U)  /*!< fSAMPLING=fDTS/32, N=6 */

+#define LL_TIM_IC_FILTER_FDIV32_N8             (TIM_CCMR1_IC1F << 16U)                                            /*!< fSAMPLING=fDTS/32, N=8 */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity

+  * @{

+  */

+#define LL_TIM_IC_POLARITY_RISING              0x00000000U                      /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */

+#define LL_TIM_IC_POLARITY_FALLING             TIM_CCER_CC1P                    /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */

+#define LL_TIM_IC_POLARITY_BOTHEDGE            (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source

+  * @{

+  */

+#define LL_TIM_CLOCKSOURCE_INTERNAL            0x00000000U                                          /*!< The timer is clocked by the internal clock provided from the RCC */

+#define LL_TIM_CLOCKSOURCE_EXT_MODE1           (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)   /*!< Counter counts at each rising or falling edge on a selected input*/

+#define LL_TIM_CLOCKSOURCE_EXT_MODE2           TIM_SMCR_ECE                                         /*!< Counter counts at each rising or falling edge on the external trigger input ETR */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode

+  * @{

+  */

+#define LL_TIM_ENCODERMODE_X2_TI1                     TIM_SMCR_SMS_0                                                     /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */

+#define LL_TIM_ENCODERMODE_X2_TI2                     TIM_SMCR_SMS_1                                                     /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */

+#define LL_TIM_ENCODERMODE_X4_TI12                   (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)                                   /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_TRGO Trigger Output

+  * @{

+  */

+#define LL_TIM_TRGO_RESET                      0x00000000U                                     /*!< UG bit from the TIMx_EGR register is used as trigger output */

+#define LL_TIM_TRGO_ENABLE                     TIM_CR2_MMS_0                                   /*!< Counter Enable signal (CNT_EN) is used as trigger output */

+#define LL_TIM_TRGO_UPDATE                     TIM_CR2_MMS_1                                   /*!< Update event is used as trigger output */

+#define LL_TIM_TRGO_CC1IF                      (TIM_CR2_MMS_1 | TIM_CR2_MMS_0)                 /*!< CC1 capture or a compare match is used as trigger output */

+#define LL_TIM_TRGO_OC1REF                     TIM_CR2_MMS_2                                   /*!< OC1REF signal is used as trigger output */

+#define LL_TIM_TRGO_OC2REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_0)                 /*!< OC2REF signal is used as trigger output */

+#define LL_TIM_TRGO_OC3REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1)                 /*!< OC3REF signal is used as trigger output */

+#define LL_TIM_TRGO_OC4REF                     (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2

+  * @{

+  */

+#define LL_TIM_TRGO2_RESET                     0x00000000U                                                         /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */

+#define LL_TIM_TRGO2_ENABLE                    TIM_CR2_MMS2_0                                                      /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */

+#define LL_TIM_TRGO2_UPDATE                    TIM_CR2_MMS2_1                                                      /*!< Update event is used as trigger output 2 */

+#define LL_TIM_TRGO2_CC1F                      (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                                   /*!< CC1 capture or a compare match is used as trigger output 2 */

+#define LL_TIM_TRGO2_OC1                       TIM_CR2_MMS2_2                                                      /*!< OC1REF signal is used as trigger output 2 */

+#define LL_TIM_TRGO2_OC2                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                                   /*!< OC2REF signal is used as trigger output 2 */

+#define LL_TIM_TRGO2_OC3                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1)                                   /*!< OC3REF signal is used as trigger output 2 */

+#define LL_TIM_TRGO2_OC4                       (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC4REF signal is used as trigger output 2 */

+#define LL_TIM_TRGO2_OC5                       TIM_CR2_MMS2_3                                                      /*!< OC5REF signal is used as trigger output 2 */

+#define LL_TIM_TRGO2_OC6                       (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0)                                   /*!< OC6REF signal is used as trigger output 2 */

+#define LL_TIM_TRGO2_OC4_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1)                                   /*!< OC4REF rising or falling edges are used as trigger output 2 */

+#define LL_TIM_TRGO2_OC6_RISINGFALLING         (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0)                  /*!< OC6REF rising or falling edges are used as trigger output 2 */

+#define LL_TIM_TRGO2_OC4_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2)                                   /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */

+#define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0)                  /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */

+#define LL_TIM_TRGO2_OC5_RISING_OC6_RISING     (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1)                   /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */

+#define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING    (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode

+  * @{

+  */

+#define LL_TIM_SLAVEMODE_DISABLED              0x00000000U                         /*!< Slave mode disabled */

+#define LL_TIM_SLAVEMODE_RESET                 TIM_SMCR_SMS_2                      /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */

+#define LL_TIM_SLAVEMODE_GATED                 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0)   /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */

+#define LL_TIM_SLAVEMODE_TRIGGER               (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1)   /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */

+#define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3                      /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI)  reinitializes the counter, generates an update of the registers and starts the counter */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_TS Trigger Selection

+  * @{

+  */

+#define LL_TIM_TS_ITR0                         0x00000000U                                                     /*!< Internal Trigger 0 (ITR0) is used as trigger input */

+#define LL_TIM_TS_ITR1                         TIM_SMCR_TS_0                                                   /*!< Internal Trigger 1 (ITR1) is used as trigger input */

+#define LL_TIM_TS_ITR2                         TIM_SMCR_TS_1                                                   /*!< Internal Trigger 2 (ITR2) is used as trigger input */

+#define LL_TIM_TS_ITR3                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)                                 /*!< Internal Trigger 3 (ITR3) is used as trigger input */

+#define LL_TIM_TS_TI1F_ED                      TIM_SMCR_TS_2                                                   /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */

+#define LL_TIM_TS_TI1FP1                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_0)                                 /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */

+#define LL_TIM_TS_TI2FP2                       (TIM_SMCR_TS_2 | TIM_SMCR_TS_1)                                 /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */

+#define LL_TIM_TS_ETRF                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0)                 /*!< Filtered external Trigger (ETRF) is used as trigger input */

+#define LL_TIM_TS_ITR4                         (TIM_SMCR_TS_3)                                                 /*!< Internal Trigger 4 (ITR4) is used as trigger input */

+#define LL_TIM_TS_ITR5                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_3)                                 /*!< Internal Trigger 5 (ITR5) is used as trigger input */

+#define LL_TIM_TS_ITR6                         (TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                                 /*!< Internal Trigger 6 (ITR6) is used as trigger input */

+#define LL_TIM_TS_ITR7                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3)                 /*!< Internal Trigger 7 (ITR7) is used as trigger input */

+#define LL_TIM_TS_ITR8                         (TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                                 /*!< Internal Trigger 8 (ITR8) is used as trigger input */

+#define LL_TIM_TS_ITR9                         (TIM_SMCR_TS_0 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                 /*!< Internal Trigger 9 (ITR9) is used as trigger input */

+#define LL_TIM_TS_ITR10                        (TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3)                 /*!< Internal Trigger 10 (ITR10) is used as trigger input */

+#define LL_TIM_TS_ITR11                        (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) is used as trigger input */

+#define LL_TIM_TS_ITR12                        (TIM_SMCR_TS_4)                                                 /*!< Internal Trigger 12 (ITR12) is used as trigger input */

+#define LL_TIM_TS_ITR13                        (TIM_SMCR_TS_0 | TIM_SMCR_TS_4)                                 /*!< Internal Trigger 13 (ITR13) is used as trigger input */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity

+  * @{

+  */

+#define LL_TIM_ETR_POLARITY_NONINVERTED        0x00000000U             /*!< ETR is non-inverted, active at high level or rising edge */

+#define LL_TIM_ETR_POLARITY_INVERTED           TIM_SMCR_ETP            /*!< ETR is inverted, active at low level or falling edge */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler

+  * @{

+  */

+#define LL_TIM_ETR_PRESCALER_DIV1              0x00000000U             /*!< ETR prescaler OFF */

+#define LL_TIM_ETR_PRESCALER_DIV2              TIM_SMCR_ETPS_0         /*!< ETR frequency is divided by 2 */

+#define LL_TIM_ETR_PRESCALER_DIV4              TIM_SMCR_ETPS_1         /*!< ETR frequency is divided by 4 */

+#define LL_TIM_ETR_PRESCALER_DIV8              TIM_SMCR_ETPS           /*!< ETR frequency is divided by 8 */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter

+  * @{

+  */

+#define LL_TIM_ETR_FILTER_FDIV1                0x00000000U                                          /*!< No filter, sampling is done at fDTS */

+#define LL_TIM_ETR_FILTER_FDIV1_N2             TIM_SMCR_ETF_0                                       /*!< fSAMPLING=fCK_INT, N=2 */

+#define LL_TIM_ETR_FILTER_FDIV1_N4             TIM_SMCR_ETF_1                                       /*!< fSAMPLING=fCK_INT, N=4 */

+#define LL_TIM_ETR_FILTER_FDIV1_N8             (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fCK_INT, N=8 */

+#define LL_TIM_ETR_FILTER_FDIV2_N6             TIM_SMCR_ETF_2                                       /*!< fSAMPLING=fDTS/2, N=6 */

+#define LL_TIM_ETR_FILTER_FDIV2_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/2, N=8 */

+#define LL_TIM_ETR_FILTER_FDIV4_N6             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/4, N=6 */

+#define LL_TIM_ETR_FILTER_FDIV4_N8             (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/4, N=8 */

+#define LL_TIM_ETR_FILTER_FDIV8_N6             TIM_SMCR_ETF_3                                       /*!< fSAMPLING=fDTS/8, N=8 */

+#define LL_TIM_ETR_FILTER_FDIV8_N8             (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0)                    /*!< fSAMPLING=fDTS/16, N=5 */

+#define LL_TIM_ETR_FILTER_FDIV16_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1)                    /*!< fSAMPLING=fDTS/16, N=6 */

+#define LL_TIM_ETR_FILTER_FDIV16_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/16, N=8 */

+#define LL_TIM_ETR_FILTER_FDIV16_N8            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2)                    /*!< fSAMPLING=fDTS/16, N=5 */

+#define LL_TIM_ETR_FILTER_FDIV32_N5            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0)   /*!< fSAMPLING=fDTS/32, N=5 */

+#define LL_TIM_ETR_FILTER_FDIV32_N6            (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1)   /*!< fSAMPLING=fDTS/32, N=6 */

+#define LL_TIM_ETR_FILTER_FDIV32_N8            TIM_SMCR_ETF                                         /*!< fSAMPLING=fDTS/32, N=8 */

+/**

+  * @}

+  */

+

+#define LL_TIM_TIM1_ETRSOURCE_GPIO        0x00000000U                                                 /* !< TIM1_ETR is connected to GPIO */

+#define LL_TIM_TIM1_ETRSOURCE_COMP1       TIM1_AF1_ETRSEL_0                                           /* !< TIM1_ETR is connected to COMP1 OUT */

+#define LL_TIM_TIM1_ETRSOURCE_COMP2       TIM1_AF1_ETRSEL_1                                           /* !< TIM1_ETR is connected to COMP2 OUT */

+#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1   (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0)                     /* !< TIM1_ETR is connected to ADC1 AWD1 */

+#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2   (TIM1_AF1_ETRSEL_2)                                         /* !< TIM1_ETR is connected to ADC1 AWD2 */

+#define LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0)                     /* !< TIM1_ETR is connected to ADC1 AWD3 */

+#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1)                     /* !< TIM1_ETR is connected to ADC3 AWD1 */

+#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2   (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /* !< TIM1_ETR is connected to ADC3 AWD2 */

+#define LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3   TIM1_AF1_ETRSEL_3                                           /* !< TIM1_ETR is connected to ADC3 AWD3 */

+

+#define LL_TIM_TIM8_ETRSOURCE_GPIO        0x00000000U                                                 /* !< TIM8_ETR is connected to GPIO */

+#define LL_TIM_TIM8_ETRSOURCE_COMP1       TIM8_AF1_ETRSEL_0                                           /* !< TIM8_ETR is connected to COMP1 OUT */

+#define LL_TIM_TIM8_ETRSOURCE_COMP2       TIM8_AF1_ETRSEL_1                                           /* !< TIM8_ETR is connected to COMP2 OUT */

+#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1   (TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                     /* !< TIM8_ETR is connected to ADC2 AWD1 */

+#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2   (TIM8_AF1_ETRSEL_2)                                         /* !< TIM8_ETR is connected to ADC2 AWD2 */

+#define LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)                     /* !< TIM8_ETR is connected to ADC2 AWD3 */

+#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1)                     /* !< TIM8_ETR is connected to ADC3 AWD1 */

+#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2   (TIM8_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0) /* !< TIM8_ETR is connected to ADC3 AWD2 */

+#define LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3   TIM8_AF1_ETRSEL_3                                           /* !< TIM8_ETR is connected to ADC3 AWD3 */

+

+#define LL_TIM_TIM2_ETRSOURCE_GPIO        0x00000000U                                                 /* !< TIM2_ETR is connected to GPIO */

+#define LL_TIM_TIM2_ETRSOURCE_COMP1       (TIM2_AF1_ETRSEL_0)                                         /* !< TIM2_ETR is connected to COMP1 OUT */

+#define LL_TIM_TIM2_ETRSOURCE_COMP2       (TIM2_AF1_ETRSEL_1)                                         /* !< TIM2_ETR is connected to COMP2 OUT */

+#define LL_TIM_TIM2_ETRSOURCE_RCC_LSE     (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                     /* !< TIM2_ETR is connected to RCC LSE */

+#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSA    TIM2_AF1_ETRSEL_2                                           /* !< TIM2_ETR is connected to SAI1 FS_A */

+#define LL_TIM_TIM2_ETRSOURCE_SAI1_FSB    (TIM2_AF1_ETRSEL_2 | TIM8_AF1_ETRSEL_0)                     /* !< TIM2_ETR is connected to SAI1 FS_B */

+

+#define LL_TIM_TIM3_ETRSOURCE_GPIO        0x00000000U                                                 /* !< TIM3_ETR is connected to GPIO */

+#define LL_TIM_TIM3_ETRSOURCE_COMP1       TIM3_AF1_ETRSEL_0                                           /* !< TIM3_ETR is connected to COMP1 OUT */

+

+#define LL_TIM_TIM5_ETRSOURCE_GPIO        0x00000000U                                                 /* !< TIM5_ETR is connected to GPIO */

+#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSA    TIM5_AF1_ETRSEL_0                                           /* !< TIM5_ETR is connected to SAI2 FS_A */

+#define LL_TIM_TIM5_ETRSOURCE_SAI2_FSB    TIM5_AF1_ETRSEL_1                                           /* !< TIM5_ETR is connected to SAI2 FS_B */

+#define LL_TIM_TIM5_ETRSOURCE_SAI4_FSA    TIM5_AF1_ETRSEL_0                                           /* !< TIM5_ETR is connected to SAI4 FS_A */

+#define LL_TIM_TIM5_ETRSOURCE_SAI4_FSB    TIM5_AF1_ETRSEL_1                                           /* !< TIM5_ETR is connected to SAI4 FS_B */

+

+#define LL_TIM_TIM23_ETRSOURCE_GPIO       0x00000000U                                                 /* !< TIM23_ETR is connected to GPIO */

+#define LL_TIM_TIM23_ETRSOURCE_COMP1      (TIM2_AF1_ETRSEL_0)                                         /* !< TIM23_ETR is connected to COMP1 OUT */

+#define LL_TIM_TIM23_ETRSOURCE_COMP2      (TIM2_AF1_ETRSEL_1)                                         /* !< TIM23_ETR is connected to COMP2 OUT */

+

+#define LL_TIM_TIM24_ETRSOURCE_GPIO        0x00000000U                                                /* !< TIM24_ETR is connected to GPIO */

+#define LL_TIM_TIM24_ETRSOURCE_SAI4_FSA    TIM5_AF1_ETRSEL_0                                          /* !< TIM24_ETR is connected to SAI4 FS_A */

+#define LL_TIM_TIM24_ETRSOURCE_SAI4_FSB    TIM5_AF1_ETRSEL_1                                          /* !< TIM24_ETR is connected to SAI4 FS_B */

+#define LL_TIM_TIM24_ETRSOURCE_SAI1_FSA    (TIM2_AF1_ETRSEL_1 | TIM8_AF1_ETRSEL_0)                    /* !< TIM24_ETR is connected to SAI1 FS_A */

+#define LL_TIM_TIM24_ETRSOURCE_SAI1_FSB    TIM2_AF1_ETRSEL_2                                          /* !< TIM24_ETR is connected to SAI1 FS_B */

+

+/** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity

+  * @{

+  */

+#define LL_TIM_BREAK_POLARITY_LOW              0x00000000U               /*!< Break input BRK is active low */

+#define LL_TIM_BREAK_POLARITY_HIGH             TIM_BDTR_BKP              /*!< Break input BRK is active high */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_BREAK_FILTER break filter

+  * @{

+  */

+#define LL_TIM_BREAK_FILTER_FDIV1              0x00000000U   /*!< No filter, BRK acts asynchronously */

+#define LL_TIM_BREAK_FILTER_FDIV1_N2           0x00010000U   /*!< fSAMPLING=fCK_INT, N=2 */

+#define LL_TIM_BREAK_FILTER_FDIV1_N4           0x00020000U   /*!< fSAMPLING=fCK_INT, N=4 */

+#define LL_TIM_BREAK_FILTER_FDIV1_N8           0x00030000U   /*!< fSAMPLING=fCK_INT, N=8 */

+#define LL_TIM_BREAK_FILTER_FDIV2_N6           0x00040000U   /*!< fSAMPLING=fDTS/2, N=6 */

+#define LL_TIM_BREAK_FILTER_FDIV2_N8           0x00050000U   /*!< fSAMPLING=fDTS/2, N=8 */

+#define LL_TIM_BREAK_FILTER_FDIV4_N6           0x00060000U   /*!< fSAMPLING=fDTS/4, N=6 */

+#define LL_TIM_BREAK_FILTER_FDIV4_N8           0x00070000U   /*!< fSAMPLING=fDTS/4, N=8 */

+#define LL_TIM_BREAK_FILTER_FDIV8_N6           0x00080000U   /*!< fSAMPLING=fDTS/8, N=6 */

+#define LL_TIM_BREAK_FILTER_FDIV8_N8           0x00090000U   /*!< fSAMPLING=fDTS/8, N=8 */

+#define LL_TIM_BREAK_FILTER_FDIV16_N5          0x000A0000U   /*!< fSAMPLING=fDTS/16, N=5 */

+#define LL_TIM_BREAK_FILTER_FDIV16_N6          0x000B0000U   /*!< fSAMPLING=fDTS/16, N=6 */

+#define LL_TIM_BREAK_FILTER_FDIV16_N8          0x000C0000U   /*!< fSAMPLING=fDTS/16, N=8 */

+#define LL_TIM_BREAK_FILTER_FDIV32_N5          0x000D0000U   /*!< fSAMPLING=fDTS/32, N=5 */

+#define LL_TIM_BREAK_FILTER_FDIV32_N6          0x000E0000U   /*!< fSAMPLING=fDTS/32, N=6 */

+#define LL_TIM_BREAK_FILTER_FDIV32_N8          0x000F0000U   /*!< fSAMPLING=fDTS/32, N=8 */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY

+  * @{

+  */

+#define LL_TIM_BREAK2_POLARITY_LOW             0x00000000U             /*!< Break input BRK2 is active low */

+#define LL_TIM_BREAK2_POLARITY_HIGH            TIM_BDTR_BK2P           /*!< Break input BRK2 is active high */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER

+  * @{

+  */

+#define LL_TIM_BREAK2_FILTER_FDIV1             0x00000000U   /*!< No filter, BRK acts asynchronously */

+#define LL_TIM_BREAK2_FILTER_FDIV1_N2          0x00100000U   /*!< fSAMPLING=fCK_INT, N=2 */

+#define LL_TIM_BREAK2_FILTER_FDIV1_N4          0x00200000U   /*!< fSAMPLING=fCK_INT, N=4 */

+#define LL_TIM_BREAK2_FILTER_FDIV1_N8          0x00300000U   /*!< fSAMPLING=fCK_INT, N=8 */

+#define LL_TIM_BREAK2_FILTER_FDIV2_N6          0x00400000U   /*!< fSAMPLING=fDTS/2, N=6 */

+#define LL_TIM_BREAK2_FILTER_FDIV2_N8          0x00500000U   /*!< fSAMPLING=fDTS/2, N=8 */

+#define LL_TIM_BREAK2_FILTER_FDIV4_N6          0x00600000U   /*!< fSAMPLING=fDTS/4, N=6 */

+#define LL_TIM_BREAK2_FILTER_FDIV4_N8          0x00700000U   /*!< fSAMPLING=fDTS/4, N=8 */

+#define LL_TIM_BREAK2_FILTER_FDIV8_N6          0x00800000U   /*!< fSAMPLING=fDTS/8, N=6 */

+#define LL_TIM_BREAK2_FILTER_FDIV8_N8          0x00900000U   /*!< fSAMPLING=fDTS/8, N=8 */

+#define LL_TIM_BREAK2_FILTER_FDIV16_N5         0x00A00000U   /*!< fSAMPLING=fDTS/16, N=5 */

+#define LL_TIM_BREAK2_FILTER_FDIV16_N6         0x00B00000U   /*!< fSAMPLING=fDTS/16, N=6 */

+#define LL_TIM_BREAK2_FILTER_FDIV16_N8         0x00C00000U   /*!< fSAMPLING=fDTS/16, N=8 */

+#define LL_TIM_BREAK2_FILTER_FDIV32_N5         0x00D00000U   /*!< fSAMPLING=fDTS/32, N=5 */

+#define LL_TIM_BREAK2_FILTER_FDIV32_N6         0x00E00000U   /*!< fSAMPLING=fDTS/32, N=6 */

+#define LL_TIM_BREAK2_FILTER_FDIV32_N8         0x00F00000U   /*!< fSAMPLING=fDTS/32, N=8 */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_OSSI OSSI

+  * @{

+  */

+#define LL_TIM_OSSI_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */

+#define LL_TIM_OSSI_ENABLE                     TIM_BDTR_OSSI           /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_OSSR OSSR

+  * @{

+  */

+#define LL_TIM_OSSR_DISABLE                    0x00000000U             /*!< When inactive, OCx/OCxN outputs are disabled */

+#define LL_TIM_OSSR_ENABLE                     TIM_BDTR_OSSR           /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */

+/**

+  * @}

+  */

+

+#if   defined(TIM_BREAK_INPUT_SUPPORT)

+/** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT

+  * @{

+  */

+#define LL_TIM_BREAK_INPUT_BKIN                0x00000000U  /*!< TIMx_BKIN input */

+#define LL_TIM_BREAK_INPUT_BKIN2               0x00000004U  /*!< TIMx_BKIN2 input */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE

+  * @{

+  */

+#define LL_TIM_BKIN_SOURCE_BKIN                TIM1_AF1_BKINE      /*!< BKIN input from AF controller */

+#define LL_TIM_BKIN_SOURCE_BKCOMP1             TIM1_AF1_BKCMP1E    /*!< internal signal: COMP1 output */

+#define LL_TIM_BKIN_SOURCE_BKCOMP2             TIM1_AF1_BKCMP2E    /*!< internal signal: COMP2 output */

+#define LL_TIM_BKIN_SOURCE_DF1BK               TIM1_AF1_BKDF1BK0E  /*!< internal signal: DFSDM1 break output */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY

+  * @{

+  */

+#define LL_TIM_BKIN_POLARITY_LOW               TIM1_AF1_BKINP           /*!< BRK BKIN input is active low */

+#define LL_TIM_BKIN_POLARITY_HIGH              0x00000000U              /*!< BRK BKIN input is active high */

+/**

+  * @}

+  */

+#endif /* TIM_BREAK_INPUT_SUPPORT */

+

+/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address

+  * @{

+  */

+#define LL_TIM_DMABURST_BASEADDR_CR1           0x00000000U                                                      /*!< TIMx_CR1 register is the DMA base address for DMA burst */

+#define LL_TIM_DMABURST_BASEADDR_CR2           TIM_DCR_DBA_0                                                    /*!< TIMx_CR2 register is the DMA base address for DMA burst */

+#define LL_TIM_DMABURST_BASEADDR_SMCR          TIM_DCR_DBA_1                                                    /*!< TIMx_SMCR register is the DMA base address for DMA burst */

+#define LL_TIM_DMABURST_BASEADDR_DIER          (TIM_DCR_DBA_1 |  TIM_DCR_DBA_0)                                 /*!< TIMx_DIER register is the DMA base address for DMA burst */

+#define LL_TIM_DMABURST_BASEADDR_SR            TIM_DCR_DBA_2                                                    /*!< TIMx_SR register is the DMA base address for DMA burst */

+#define LL_TIM_DMABURST_BASEADDR_EGR           (TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                                  /*!< TIMx_EGR register is the DMA base address for DMA burst */

+#define LL_TIM_DMABURST_BASEADDR_CCMR1         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                                  /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */

+#define LL_TIM_DMABURST_BASEADDR_CCMR2         (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */

+#define LL_TIM_DMABURST_BASEADDR_CCER          TIM_DCR_DBA_3                                                    /*!< TIMx_CCER register is the DMA base address for DMA burst */

+#define LL_TIM_DMABURST_BASEADDR_CNT           (TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                                  /*!< TIMx_CNT register is the DMA base address for DMA burst */

+#define LL_TIM_DMABURST_BASEADDR_PSC           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                                  /*!< TIMx_PSC register is the DMA base address for DMA burst */

+#define LL_TIM_DMABURST_BASEADDR_ARR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)                  /*!< TIMx_ARR register is the DMA base address for DMA burst */

+#define LL_TIM_DMABURST_BASEADDR_RCR           (TIM_DCR_DBA_3 | TIM_DCR_DBA_2)                                  /*!< TIMx_RCR register is the DMA base address for DMA burst */

+#define LL_TIM_DMABURST_BASEADDR_CCR1          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCR1 register is the DMA base address for DMA burst */

+#define LL_TIM_DMABURST_BASEADDR_CCR2          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR2 register is the DMA base address for DMA burst */

+#define LL_TIM_DMABURST_BASEADDR_CCR3          (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR3 register is the DMA base address for DMA burst */

+#define LL_TIM_DMABURST_BASEADDR_CCR4          TIM_DCR_DBA_4                                                    /*!< TIMx_CCR4 register is the DMA base address for DMA burst */

+#define LL_TIM_DMABURST_BASEADDR_BDTR          (TIM_DCR_DBA_4 | TIM_DCR_DBA_0)                                  /*!< TIMx_BDTR register is the DMA base address for DMA burst */

+#define LL_TIM_DMABURST_BASEADDR_CCMR3         (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0)                  /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */

+#define LL_TIM_DMABURST_BASEADDR_CCR5          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1)                  /*!< TIMx_CCR5 register is the DMA base address for DMA burst */

+#define LL_TIM_DMABURST_BASEADDR_CCR6          (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0)  /*!< TIMx_CCR6 register is the DMA base address for DMA burst */

+#if defined(TIM_AF1_BKINE)&&defined(TIM_AF2_BKINE)

+#define LL_TIM_DMABURST_BASEADDR_AF1           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3)                                  /*!< TIMx_AF1 register is the DMA base address for DMA burst */

+#define LL_TIM_DMABURST_BASEADDR_AF2           (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_0)                  /*!< TIMx_AF2 register is the DMA base address for DMA burst */

+#endif /* TIM_AF1_BKINE && TIM_AF2_BKINE */

+#define LL_TIM_DMABURST_BASEADDR_TISEL         (TIM_DCR_DBA_4 | TIM_DCR_DBA_3 | TIM_DCR_DBA_1)                  /*!< TIMx_TISEL register is the DMA base address for DMA burst */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length

+  * @{

+  */

+#define LL_TIM_DMABURST_LENGTH_1TRANSFER       0x00000000U                                                     /*!< Transfer is done to 1 register starting from the DMA burst base address */

+#define LL_TIM_DMABURST_LENGTH_2TRANSFERS      TIM_DCR_DBL_0                                                   /*!< Transfer is done to 2 registers starting from the DMA burst base address */

+#define LL_TIM_DMABURST_LENGTH_3TRANSFERS      TIM_DCR_DBL_1                                                   /*!< Transfer is done to 3 registers starting from the DMA burst base address */

+#define LL_TIM_DMABURST_LENGTH_4TRANSFERS      (TIM_DCR_DBL_1 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 4 registers starting from the DMA burst base address */

+#define LL_TIM_DMABURST_LENGTH_5TRANSFERS      TIM_DCR_DBL_2                                                   /*!< Transfer is done to 5 registers starting from the DMA burst base address */

+#define LL_TIM_DMABURST_LENGTH_6TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 6 registers starting from the DMA burst base address */

+#define LL_TIM_DMABURST_LENGTH_7TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 7 registers starting from the DMA burst base address */

+#define LL_TIM_DMABURST_LENGTH_8TRANSFERS      (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 1 registers starting from the DMA burst base address */

+#define LL_TIM_DMABURST_LENGTH_9TRANSFERS      TIM_DCR_DBL_3                                                   /*!< Transfer is done to 9 registers starting from the DMA burst base address */

+#define LL_TIM_DMABURST_LENGTH_10TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_0)                                 /*!< Transfer is done to 10 registers starting from the DMA burst base address */

+#define LL_TIM_DMABURST_LENGTH_11TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1)                                 /*!< Transfer is done to 11 registers starting from the DMA burst base address */

+#define LL_TIM_DMABURST_LENGTH_12TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 12 registers starting from the DMA burst base address */

+#define LL_TIM_DMABURST_LENGTH_13TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2)                                 /*!< Transfer is done to 13 registers starting from the DMA burst base address */

+#define LL_TIM_DMABURST_LENGTH_14TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0)                 /*!< Transfer is done to 14 registers starting from the DMA burst base address */

+#define LL_TIM_DMABURST_LENGTH_15TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1)                 /*!< Transfer is done to 15 registers starting from the DMA burst base address */

+#define LL_TIM_DMABURST_LENGTH_16TRANSFERS     (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */

+#define LL_TIM_DMABURST_LENGTH_17TRANSFERS     TIM_DCR_DBL_4                                                   /*!< Transfer is done to 17 registers starting from the DMA burst base address */

+#define LL_TIM_DMABURST_LENGTH_18TRANSFERS     (TIM_DCR_DBL_4 |  TIM_DCR_DBL_0)                                /*!< Transfer is done to 18 registers starting from the DMA burst base address */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_TIM1_TI1_RMP  TIM1 Timer Input Ch1 Remap

+  * @{

+  */

+#define LL_TIM_TIM1_TI1_RMP_GPIO                          0x00000000U                               /* !< TIM1 input 1 is connected to GPIO */

+#define LL_TIM_TIM1_TI1_RMP_COMP1                         TIM_TISEL_TI1SEL_0                        /* !< TIM1 input 1 is connected to COMP1 OUT */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_TIM8_TI1_RMP  TIM8 Timer Input Ch1 Remap

+  * @{

+  */

+#define LL_TIM_TIM8_TI1_RMP_GPIO                          0x00000000U                               /* !< TIM8 input 1 is connected to GPIO */

+#define LL_TIM_TIM8_TI1_RMP_COMP2                         TIM_TISEL_TI1SEL_0                        /* !< TIM8 input 1 is connected to COMP2 OUT */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_TIM2_TI4_RMP  TIM2 Timer Input Ch4 Remap

+  * @{

+  */

+#define LL_TIM_TIM2_TI4_RMP_GPIO                          0x00000000U                               /* !< TIM2 input 4 is connected to GPIO */

+#define LL_TIM_TIM2_TI4_RMP_COMP1                         TIM_TISEL_TI4SEL_0                        /* !< TIM2 input 4 is connected to COMP1 OUT */

+#define LL_TIM_TIM2_TI4_RMP_COMP2                         TIM_TISEL_TI4SEL_1                        /* !< TIM2 input 4 is connected to COMP2 OUT */

+#define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2                   (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM2 input 4 is connected to COMP2 OUT OR COMP2 OUT */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_TIM3_TI1_RMP  TIM3 Timer Input Ch1 Remap

+  * @{

+  */

+#define LL_TIM_TIM3_TI1_RMP_GPIO                          0x00000000U                               /* !< TIM3 input 1 is connected to GPIO */

+#define LL_TIM_TIM3_TI1_RMP_COMP1                         TIM_TISEL_TI1SEL_0                        /* !< TIM3 input 1 is connected to COMP1 OUT */

+#define LL_TIM_TIM3_TI1_RMP_COMP2                         TIM_TISEL_TI1SEL_1                        /* !< TIM3 input 1 is connected to COMP2 OUT */

+#define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2                   (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM3 input 1 is connected to COMP1 OUT or COMP2 OUT */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_TIM5_TI1_RMP  TIM5 Timer Input Ch1 Remap

+  * @{

+  */

+#define LL_TIM_TIM5_TI1_RMP_GPIO                          0x00000000U                               /* !< TIM5 input 1 is connected to GPIO */

+#define LL_TIM_TIM5_TI1_RMP_CAN_TMP                       TIM_TISEL_TI1SEL_0                        /* !< TIM5 input 1 is connected to CAN TMP */

+#define LL_TIM_TIM5_TI1_RMP_CAN_RTP                       TIM_TISEL_TI1SEL_1                        /* !< TIM5 input 1 is connected to CAN RTP */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_TIM12_TI1_RMP  TIM12 Timer Input Ch1 Remap

+  * @{

+  */

+#define LL_TIM_TIM12_TI1_RMP_GPIO                         0x00000000U                               /* !< TIM12 input 1 is connected to GPIO */

+#define LL_TIM_TIM12_TI1_RMP_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /* !< TIM12 input 1 is connected to SPDIF FS */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_TIM15_TI1_RMP  TIM15 Timer Input Ch1 Remap

+  * @{

+  */

+#define LL_TIM_TIM15_TI1_RMP_GPIO                         0x00000000U                               /* !< TIM15 input 1 is connected to GPIO */

+#define LL_TIM_TIM15_TI1_RMP_TIM2_CH1                     TIM_TISEL_TI1SEL_0                        /* !< TIM15 input 1 is connected to TIM2 CH1 */

+#define LL_TIM_TIM15_TI1_RMP_TIM3_CH1                     TIM_TISEL_TI1SEL_1                        /* !< TIM15 input 1 is connected to TIM3 CH1 */

+#define LL_TIM_TIM15_TI1_RMP_TIM4_CH1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM15 input 1 is connected to TIM4 CH1 */

+#define LL_TIM_TIM15_TI1_RMP_RCC_LSE                      (TIM_TISEL_TI1SEL_2)                      /* !< TIM15 input 1 is connected to RCC LSE  */

+#define LL_TIM_TIM15_TI1_RMP_RCC_CSI                      (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /* !< TIM15 input 1 is connected to RCC CSI  */

+#define LL_TIM_TIM15_TI1_RMP_RCC_MCO2                     (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /* !< TIM15 input 1 is connected to RCC MCO2 */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_TIM15_TI2_RMP  TIM15 Timer Input Ch2 Remap

+  * @{

+  */

+#define LL_TIM_TIM15_TI2_RMP_GPIO                         0x00000000U                               /* !< TIM15 input 2 is connected to GPIO */

+#define LL_TIM_TIM15_TI2_RMP_TIM2_CH2                     (TIM_TISEL_TI2SEL_0)                      /* !< TIM15 input 2 is connected to TIM2 CH2 */

+#define LL_TIM_TIM15_TI2_RMP_TIM3_CH2                     (TIM_TISEL_TI2SEL_1)                      /* !< TIM15 input 2 is connected to TIM3 CH2 */

+#define LL_TIM_TIM15_TI2_RMP_TIM4_CH2                     (TIM_TISEL_TI2SEL_0 | TIM_TISEL_TI2SEL_1) /* !< TIM15 input 2 is connected to TIM4 CH2 */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_TIM16_TI1_RMP  TIM16 Timer Input Ch1 Remap

+  * @{

+  */

+#define LL_TIM_TIM16_TI1_RMP_GPIO                         0x00000000U                               /* !< TIM16 input 1 is connected to GPIO */

+#define LL_TIM_TIM16_TI1_RMP_RCC_LSI                      TIM_TISEL_TI1SEL_0                        /* !< TIM16 input 1 is connected to RCC LSI */

+#define LL_TIM_TIM16_TI1_RMP_RCC_LSE                      TIM_TISEL_TI1SEL_1                        /* !< TIM16 input 1 is connected to RCC LSE */

+#define LL_TIM_TIM16_TI1_RMP_WKUP_IT                      (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM16 input 1 is connected to WKUP_IT */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_TIM17_TI1_RMP  TIM17 Timer Input Ch1 Remap

+  * @{

+  */

+#define LL_TIM_TIM17_TI1_RMP_GPIO                         0x00000000U                               /* !< TIM17 input 1 is connected to GPIO */

+#define LL_TIM_TIM17_TI1_RMP_SPDIF_FS                     TIM_TISEL_TI1SEL_0                        /* !< TIM17 input 1 is connected to SPDIF FS */

+#define LL_TIM_TIM17_TI1_RMP_RCC_HSE1MHZ                  TIM_TISEL_TI1SEL_1                        /* !< TIM17 input 1 is connected to RCC HSE 1Mhz */

+#define LL_TIM_TIM17_TI1_RMP_RCC_MCO1                     (TIM_TISEL_TI1SEL_0 | TIM_TISEL_TI1SEL_1) /* !< TIM17 input 1 is connected to RCC MCO1 */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_TIM23_TI4_RMP  TIM23 Timer Input Ch4 Remap

+  * @{

+  */

+#define LL_TIM_TIM23_TI4_RMP_GPIO                         0x00000000U                               /* !< TIM23 input 4 is connected to GPIO */

+#define LL_TIM_TIM23_TI4_RMP_COMP1                        TIM_TISEL_TI4SEL_0                        /* !< TIM23 input 4 is connected to COMP1 OUT */

+#define LL_TIM_TIM23_TI4_RMP_COMP2                        TIM_TISEL_TI4SEL_1                        /* !< TIM23 input 4 is connected to COMP2 OUT */

+#define LL_TIM_TIM23_TI4_RMP_COMP1_COMP2                  (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM23 input 4 is connected to COMP1 OUT or COMP2 OUT */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EC_TIM24_TI1_RMP  TIM24 Timer Input Ch1 Remap

+  * @{

+  */

+#define LL_TIM_TIM24_TI1_RMP_GPIO                         0x00000000U                               /* !< TIM24 input 1 is connected to GPIO */

+#define LL_TIM_TIM24_TI1_RMP_CAN_TMP                      TIM_TISEL_TI1SEL_0                        /* !< TIM24 input 1 is connected to CAN TMP  */

+#define LL_TIM_TIM24_TI1_RMP_CAN_RTP                      TIM_TISEL_TI1SEL_1                        /* !< TIM24 input 1 is connected to CAN RTP  */

+#define LL_TIM_TIM24_TI1_RMP_CAN_SOC                      (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /* !< TIM24 input 1 is connected to CAN SOC */

+

+#if defined(TIM_BREAK_INPUT_SUPPORT)

+/** Legacy definitions for compatibility purpose

+@cond 0

+  */

+#define LL_TIM_BKIN_SOURCE_DFBK  LL_TIM_BKIN_SOURCE_DF1BK

+/**

+@endcond

+  */

+#endif /* TIM_BREAK_INPUT_SUPPORT */

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup TIM_LL_Exported_Macros TIM Exported Macros

+  * @{

+  */

+

+/** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros

+  * @{

+  */

+/**

+  * @brief  Write a value in TIM register.

+  * @param  __INSTANCE__ TIM Instance

+  * @param  __REG__ Register to be written

+  * @param  __VALUE__ Value to be written in the register

+  * @retval None

+  */

+#define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))

+

+/**

+  * @brief  Read a value in TIM register.

+  * @param  __INSTANCE__ TIM Instance

+  * @param  __REG__ Register to be read

+  * @retval Register value

+  */

+#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros

+  * @{

+  */

+

+/**

+  * @brief  HELPER macro retrieving the UIFCPY flag from the counter value.

+  * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());

+  * @note  Relevant only if UIF flag remapping has been enabled  (UIF status bit is copied

+  *        to TIMx_CNT register bit 31)

+  * @param  __CNT__ Counter value

+  * @retval UIF status bit

+  */

+#define __LL_TIM_GETFLAG_UIFCPY(__CNT__)  \

+  (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)

+

+/**

+  * @brief  HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.

+  * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);

+  * @param  __TIMCLK__ timer input clock frequency (in Hz)

+  * @param  __CKD__ This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1

+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2

+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4

+  * @param  __DT__ deadtime duration (in ns)

+  * @retval DTG[0:7]

+  */

+#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__)  \

+  ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))    ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__)))  & DT_DELAY_1) :                                               \

+    (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\

+    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))))  ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\

+    (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\

+    0U)

+

+/**

+  * @brief  HELPER macro calculating the prescaler value to achieve the required counter clock frequency.

+  * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);

+  * @param  __TIMCLK__ timer input clock frequency (in Hz)

+  * @param  __CNTCLK__ counter clock frequency (in Hz)

+  * @retval Prescaler value  (between Min_Data=0 and Max_Data=65535)

+  */

+#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__)   \

+  (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U)

+

+/**

+  * @brief  HELPER macro calculating the auto-reload value to achieve the required output signal frequency.

+  * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);

+  * @param  __TIMCLK__ timer input clock frequency (in Hz)

+  * @param  __PSC__ prescaler

+  * @param  __FREQ__ output signal frequency (in Hz)

+  * @retval  Auto-reload value  (between Min_Data=0 and Max_Data=65535)

+  */

+#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \

+  ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U)

+

+/**

+  * @brief  HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.

+  * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);

+  * @param  __TIMCLK__ timer input clock frequency (in Hz)

+  * @param  __PSC__ prescaler

+  * @param  __DELAY__ timer output compare active/inactive delay (in us)

+  * @retval Compare value  (between Min_Data=0 and Max_Data=65535)

+  */

+#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__)  \

+  ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \

+              / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))

+

+/**

+  * @brief  HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).

+  * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);

+  * @param  __TIMCLK__ timer input clock frequency (in Hz)

+  * @param  __PSC__ prescaler

+  * @param  __DELAY__ timer output compare active/inactive delay (in us)

+  * @param  __PULSE__ pulse duration (in us)

+  * @retval Auto-reload value  (between Min_Data=0 and Max_Data=65535)

+  */

+#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__)  \

+  ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \

+              + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))

+

+/**

+  * @brief  HELPER macro retrieving the ratio of the input capture prescaler

+  * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());

+  * @param  __ICPSC__ This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_ICPSC_DIV1

+  *         @arg @ref LL_TIM_ICPSC_DIV2

+  *         @arg @ref LL_TIM_ICPSC_DIV4

+  *         @arg @ref LL_TIM_ICPSC_DIV8

+  * @retval Input capture prescaler ratio (1, 2, 4 or 8)

+  */

+#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__)  \

+  ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))

+

+

+/**

+  * @}

+  */

+

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions

+  * @{

+  */

+

+/** @defgroup TIM_LL_EF_Time_Base Time Base configuration

+  * @{

+  */

+/**

+  * @brief  Enable timer counter.

+  * @rmtoll CR1          CEN           LL_TIM_EnableCounter

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->CR1, TIM_CR1_CEN);

+}

+

+/**

+  * @brief  Disable timer counter.

+  * @rmtoll CR1          CEN           LL_TIM_DisableCounter

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)

+{

+  CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);

+}

+

+/**

+  * @brief  Indicates whether the timer counter is enabled.

+  * @rmtoll CR1          CEN           LL_TIM_IsEnabledCounter

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable update event generation.

+  * @rmtoll CR1          UDIS          LL_TIM_EnableUpdateEvent

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)

+{

+  CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);

+}

+

+/**

+  * @brief  Disable update event generation.

+  * @rmtoll CR1          UDIS          LL_TIM_DisableUpdateEvent

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->CR1, TIM_CR1_UDIS);

+}

+

+/**

+  * @brief  Indicates whether update event generation is enabled.

+  * @rmtoll CR1          UDIS          LL_TIM_IsEnabledUpdateEvent

+  * @param  TIMx Timer instance

+  * @retval Inverted state of bit (0 or 1).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set update event source

+  * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events

+  *       generate an update interrupt or DMA request if enabled:

+  *        - Counter overflow/underflow

+  *        - Setting the UG bit

+  *        - Update generation through the slave mode controller

+  * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter

+  *       overflow/underflow generates an update interrupt or DMA request if enabled.

+  * @rmtoll CR1          URS           LL_TIM_SetUpdateSource

+  * @param  TIMx Timer instance

+  * @param  UpdateSource This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR

+  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)

+{

+  MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);

+}

+

+/**

+  * @brief  Get actual event update source

+  * @rmtoll CR1          URS           LL_TIM_GetUpdateSource

+  * @param  TIMx Timer instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_TIM_UPDATESOURCE_REGULAR

+  *         @arg @ref LL_TIM_UPDATESOURCE_COUNTER

+  */

+__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)

+{

+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));

+}

+

+/**

+  * @brief  Set one pulse mode (one shot v.s. repetitive).

+  * @rmtoll CR1          OPM           LL_TIM_SetOnePulseMode

+  * @param  TIMx Timer instance

+  * @param  OnePulseMode This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE

+  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)

+{

+  MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);

+}

+

+/**

+  * @brief  Get actual one pulse mode.

+  * @rmtoll CR1          OPM           LL_TIM_GetOnePulseMode

+  * @param  TIMx Timer instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_TIM_ONEPULSEMODE_SINGLE

+  *         @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE

+  */

+__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)

+{

+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));

+}

+

+/**

+  * @brief  Set the timer counter counting mode.

+  * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to

+  *       check whether or not the counter mode selection feature is supported

+  *       by a timer instance.

+  * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)

+  *       requires a timer reset to avoid unexpected direction

+  *       due to DIR bit readonly in center aligned mode.

+  * @rmtoll CR1          DIR           LL_TIM_SetCounterMode\n

+  *         CR1          CMS           LL_TIM_SetCounterMode

+  * @param  TIMx Timer instance

+  * @param  CounterMode This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_COUNTERMODE_UP

+  *         @arg @ref LL_TIM_COUNTERMODE_DOWN

+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP

+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN

+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)

+{

+  MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode);

+}

+

+/**

+  * @brief  Get actual counter mode.

+  * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to

+  *       check whether or not the counter mode selection feature is supported

+  *       by a timer instance.

+  * @rmtoll CR1          DIR           LL_TIM_GetCounterMode\n

+  *         CR1          CMS           LL_TIM_GetCounterMode

+  * @param  TIMx Timer instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_TIM_COUNTERMODE_UP

+  *         @arg @ref LL_TIM_COUNTERMODE_DOWN

+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP

+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN

+  *         @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN

+  */

+__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)

+{

+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));

+}

+

+/**

+  * @brief  Enable auto-reload (ARR) preload.

+  * @rmtoll CR1          ARPE          LL_TIM_EnableARRPreload

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->CR1, TIM_CR1_ARPE);

+}

+

+/**

+  * @brief  Disable auto-reload (ARR) preload.

+  * @rmtoll CR1          ARPE          LL_TIM_DisableARRPreload

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)

+{

+  CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);

+}

+

+/**

+  * @brief  Indicates whether auto-reload (ARR) preload is enabled.

+  * @rmtoll CR1          ARPE          LL_TIM_IsEnabledARRPreload

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set the division ratio between the timer clock  and the sampling clock used by the dead-time generators (when supported) and the digital filters.

+  * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check

+  *       whether or not the clock division feature is supported by the timer

+  *       instance.

+  * @rmtoll CR1          CKD           LL_TIM_SetClockDivision

+  * @param  TIMx Timer instance

+  * @param  ClockDivision This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1

+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2

+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)

+{

+  MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);

+}

+

+/**

+  * @brief  Get the actual division ratio between the timer clock  and the sampling clock used by the dead-time generators (when supported) and the digital filters.

+  * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check

+  *       whether or not the clock division feature is supported by the timer

+  *       instance.

+  * @rmtoll CR1          CKD           LL_TIM_GetClockDivision

+  * @param  TIMx Timer instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV1

+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV2

+  *         @arg @ref LL_TIM_CLOCKDIVISION_DIV4

+  */

+__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)

+{

+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));

+}

+

+/**

+  * @brief  Set the counter value.

+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check

+  *       whether or not a timer instance supports a 32 bits counter.

+  * @rmtoll CNT          CNT           LL_TIM_SetCounter

+  * @param  TIMx Timer instance

+  * @param  Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)

+{

+  WRITE_REG(TIMx->CNT, Counter);

+}

+

+/**

+  * @brief  Get the counter value.

+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check

+  *       whether or not a timer instance supports a 32 bits counter.

+  * @rmtoll CNT          CNT           LL_TIM_GetCounter

+  * @param  TIMx Timer instance

+  * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)

+  */

+__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)

+{

+  return (uint32_t)(READ_REG(TIMx->CNT));

+}

+

+/**

+  * @brief  Get the current direction of the counter

+  * @rmtoll CR1          DIR           LL_TIM_GetDirection

+  * @param  TIMx Timer instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_TIM_COUNTERDIRECTION_UP

+  *         @arg @ref LL_TIM_COUNTERDIRECTION_DOWN

+  */

+__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)

+{

+  return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));

+}

+

+/**

+  * @brief  Set the prescaler value.

+  * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).

+  * @note The prescaler can be changed on the fly as this control register is buffered. The new

+  *       prescaler ratio is taken into account at the next update event.

+  * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter

+  * @rmtoll PSC          PSC           LL_TIM_SetPrescaler

+  * @param  TIMx Timer instance

+  * @param  Prescaler between Min_Data=0 and Max_Data=65535

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)

+{

+  WRITE_REG(TIMx->PSC, Prescaler);

+}

+

+/**

+  * @brief  Get the prescaler value.

+  * @rmtoll PSC          PSC           LL_TIM_GetPrescaler

+  * @param  TIMx Timer instance

+  * @retval  Prescaler value between Min_Data=0 and Max_Data=65535

+  */

+__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)

+{

+  return (uint32_t)(READ_REG(TIMx->PSC));

+}

+

+/**

+  * @brief  Set the auto-reload value.

+  * @note The counter is blocked while the auto-reload value is null.

+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check

+  *       whether or not a timer instance supports a 32 bits counter.

+  * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter

+  * @rmtoll ARR          ARR           LL_TIM_SetAutoReload

+  * @param  TIMx Timer instance

+  * @param  AutoReload between Min_Data=0 and Max_Data=65535

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)

+{

+  WRITE_REG(TIMx->ARR, AutoReload);

+}

+

+/**

+  * @brief  Get the auto-reload value.

+  * @rmtoll ARR          ARR           LL_TIM_GetAutoReload

+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check

+  *       whether or not a timer instance supports a 32 bits counter.

+  * @param  TIMx Timer instance

+  * @retval Auto-reload value

+  */

+__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)

+{

+  return (uint32_t)(READ_REG(TIMx->ARR));

+}

+

+/**

+  * @brief  Set the repetition counter value.

+  * @note For advanced timer instances RepetitionCounter can be up to 65535.

+  * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check

+  *       whether or not a timer instance supports a repetition counter.

+  * @rmtoll RCR          REP           LL_TIM_SetRepetitionCounter

+  * @param  TIMx Timer instance

+  * @param  RepetitionCounter between Min_Data=0 and Max_Data=255 or 65535 for advanced timer.

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)

+{

+  WRITE_REG(TIMx->RCR, RepetitionCounter);

+}

+

+/**

+  * @brief  Get the repetition counter value.

+  * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check

+  *       whether or not a timer instance supports a repetition counter.

+  * @rmtoll RCR          REP           LL_TIM_GetRepetitionCounter

+  * @param  TIMx Timer instance

+  * @retval Repetition counter value

+  */

+__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)

+{

+  return (uint32_t)(READ_REG(TIMx->RCR));

+}

+

+/**

+  * @brief  Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).

+  * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.

+  * @rmtoll CR1          UIFREMAP      LL_TIM_EnableUIFRemap

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);

+}

+

+/**

+  * @brief  Disable update interrupt flag (UIF) remapping.

+  * @rmtoll CR1          UIFREMAP      LL_TIM_DisableUIFRemap

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)

+{

+  CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);

+}

+

+/**

+  * @brief  Indicate whether update interrupt flag (UIF) copy is set.

+  * @param  Counter Counter value

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsActiveUIFCPY(uint32_t Counter)

+{

+  return (((Counter & TIM_CNT_UIFCPY) == (TIM_CNT_UIFCPY)) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration

+  * @{

+  */

+/**

+  * @brief  Enable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.

+  * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,

+  *       they are updated only when a commutation event (COM) occurs.

+  * @note Only on channels that have a complementary output.

+  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check

+  *       whether or not a timer instance is able to generate a commutation event.

+  * @rmtoll CR2          CCPC          LL_TIM_CC_EnablePreload

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->CR2, TIM_CR2_CCPC);

+}

+

+/**

+  * @brief  Disable  the capture/compare control bits (CCxE, CCxNE and OCxM) preload.

+  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check

+  *       whether or not a timer instance is able to generate a commutation event.

+  * @rmtoll CR2          CCPC          LL_TIM_CC_DisablePreload

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)

+{

+  CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);

+}

+

+/**

+  * @brief  Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).

+  * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check

+  *       whether or not a timer instance is able to generate a commutation event.

+  * @rmtoll CR2          CCUS          LL_TIM_CC_SetUpdate

+  * @param  TIMx Timer instance

+  * @param  CCUpdateSource This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY

+  *         @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)

+{

+  MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);

+}

+

+/**

+  * @brief  Set the trigger of the capture/compare DMA request.

+  * @rmtoll CR2          CCDS          LL_TIM_CC_SetDMAReqTrigger

+  * @param  TIMx Timer instance

+  * @param  DMAReqTrigger This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CCDMAREQUEST_CC

+  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)

+{

+  MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);

+}

+

+/**

+  * @brief  Get actual trigger of the capture/compare DMA request.

+  * @rmtoll CR2          CCDS          LL_TIM_CC_GetDMAReqTrigger

+  * @param  TIMx Timer instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_TIM_CCDMAREQUEST_CC

+  *         @arg @ref LL_TIM_CCDMAREQUEST_UPDATE

+  */

+__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)

+{

+  return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));

+}

+

+/**

+  * @brief  Set the lock level to freeze the

+  *         configuration of several capture/compare parameters.

+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not

+  *       the lock mechanism is supported by a timer instance.

+  * @rmtoll BDTR         LOCK          LL_TIM_CC_SetLockLevel

+  * @param  TIMx Timer instance

+  * @param  LockLevel This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_LOCKLEVEL_OFF

+  *         @arg @ref LL_TIM_LOCKLEVEL_1

+  *         @arg @ref LL_TIM_LOCKLEVEL_2

+  *         @arg @ref LL_TIM_LOCKLEVEL_3

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)

+{

+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);

+}

+

+/**

+  * @brief  Enable capture/compare channels.

+  * @rmtoll CCER         CC1E          LL_TIM_CC_EnableChannel\n

+  *         CCER         CC1NE         LL_TIM_CC_EnableChannel\n

+  *         CCER         CC2E          LL_TIM_CC_EnableChannel\n

+  *         CCER         CC2NE         LL_TIM_CC_EnableChannel\n

+  *         CCER         CC3E          LL_TIM_CC_EnableChannel\n

+  *         CCER         CC3NE         LL_TIM_CC_EnableChannel\n

+  *         CCER         CC4E          LL_TIM_CC_EnableChannel\n

+  *         CCER         CC5E          LL_TIM_CC_EnableChannel\n

+  *         CCER         CC6E          LL_TIM_CC_EnableChannel

+  * @param  TIMx Timer instance

+  * @param  Channels This parameter can be a combination of the following values:

+  *         @arg @ref LL_TIM_CHANNEL_CH1

+  *         @arg @ref LL_TIM_CHANNEL_CH1N

+  *         @arg @ref LL_TIM_CHANNEL_CH2

+  *         @arg @ref LL_TIM_CHANNEL_CH2N

+  *         @arg @ref LL_TIM_CHANNEL_CH3

+  *         @arg @ref LL_TIM_CHANNEL_CH3N

+  *         @arg @ref LL_TIM_CHANNEL_CH4

+  *         @arg @ref LL_TIM_CHANNEL_CH5

+  *         @arg @ref LL_TIM_CHANNEL_CH6

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)

+{

+  SET_BIT(TIMx->CCER, Channels);

+}

+

+/**

+  * @brief  Disable capture/compare channels.

+  * @rmtoll CCER         CC1E          LL_TIM_CC_DisableChannel\n

+  *         CCER         CC1NE         LL_TIM_CC_DisableChannel\n

+  *         CCER         CC2E          LL_TIM_CC_DisableChannel\n

+  *         CCER         CC2NE         LL_TIM_CC_DisableChannel\n

+  *         CCER         CC3E          LL_TIM_CC_DisableChannel\n

+  *         CCER         CC3NE         LL_TIM_CC_DisableChannel\n

+  *         CCER         CC4E          LL_TIM_CC_DisableChannel\n

+  *         CCER         CC5E          LL_TIM_CC_DisableChannel\n

+  *         CCER         CC6E          LL_TIM_CC_DisableChannel

+  * @param  TIMx Timer instance

+  * @param  Channels This parameter can be a combination of the following values:

+  *         @arg @ref LL_TIM_CHANNEL_CH1

+  *         @arg @ref LL_TIM_CHANNEL_CH1N

+  *         @arg @ref LL_TIM_CHANNEL_CH2

+  *         @arg @ref LL_TIM_CHANNEL_CH2N

+  *         @arg @ref LL_TIM_CHANNEL_CH3

+  *         @arg @ref LL_TIM_CHANNEL_CH3N

+  *         @arg @ref LL_TIM_CHANNEL_CH4

+  *         @arg @ref LL_TIM_CHANNEL_CH5

+  *         @arg @ref LL_TIM_CHANNEL_CH6

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)

+{

+  CLEAR_BIT(TIMx->CCER, Channels);

+}

+

+/**

+  * @brief  Indicate whether channel(s) is(are) enabled.

+  * @rmtoll CCER         CC1E          LL_TIM_CC_IsEnabledChannel\n

+  *         CCER         CC1NE         LL_TIM_CC_IsEnabledChannel\n

+  *         CCER         CC2E          LL_TIM_CC_IsEnabledChannel\n

+  *         CCER         CC2NE         LL_TIM_CC_IsEnabledChannel\n

+  *         CCER         CC3E          LL_TIM_CC_IsEnabledChannel\n

+  *         CCER         CC3NE         LL_TIM_CC_IsEnabledChannel\n

+  *         CCER         CC4E          LL_TIM_CC_IsEnabledChannel\n

+  *         CCER         CC5E          LL_TIM_CC_IsEnabledChannel\n

+  *         CCER         CC6E          LL_TIM_CC_IsEnabledChannel

+  * @param  TIMx Timer instance

+  * @param  Channels This parameter can be a combination of the following values:

+  *         @arg @ref LL_TIM_CHANNEL_CH1

+  *         @arg @ref LL_TIM_CHANNEL_CH1N

+  *         @arg @ref LL_TIM_CHANNEL_CH2

+  *         @arg @ref LL_TIM_CHANNEL_CH2N

+  *         @arg @ref LL_TIM_CHANNEL_CH3

+  *         @arg @ref LL_TIM_CHANNEL_CH3N

+  *         @arg @ref LL_TIM_CHANNEL_CH4

+  *         @arg @ref LL_TIM_CHANNEL_CH5

+  *         @arg @ref LL_TIM_CHANNEL_CH6

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)

+{

+  return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration

+  * @{

+  */

+/**

+  * @brief  Configure an output channel.

+  * @rmtoll CCMR1        CC1S          LL_TIM_OC_ConfigOutput\n

+  *         CCMR1        CC2S          LL_TIM_OC_ConfigOutput\n

+  *         CCMR2        CC3S          LL_TIM_OC_ConfigOutput\n

+  *         CCMR2        CC4S          LL_TIM_OC_ConfigOutput\n

+  *         CCMR3        CC5S          LL_TIM_OC_ConfigOutput\n

+  *         CCMR3        CC6S          LL_TIM_OC_ConfigOutput\n

+  *         CCER         CC1P          LL_TIM_OC_ConfigOutput\n

+  *         CCER         CC2P          LL_TIM_OC_ConfigOutput\n

+  *         CCER         CC3P          LL_TIM_OC_ConfigOutput\n

+  *         CCER         CC4P          LL_TIM_OC_ConfigOutput\n

+  *         CCER         CC5P          LL_TIM_OC_ConfigOutput\n

+  *         CCER         CC6P          LL_TIM_OC_ConfigOutput\n

+  *         CR2          OIS1          LL_TIM_OC_ConfigOutput\n

+  *         CR2          OIS2          LL_TIM_OC_ConfigOutput\n

+  *         CR2          OIS3          LL_TIM_OC_ConfigOutput\n

+  *         CR2          OIS4          LL_TIM_OC_ConfigOutput\n

+  *         CR2          OIS5          LL_TIM_OC_ConfigOutput\n

+  *         CR2          OIS6          LL_TIM_OC_ConfigOutput

+  * @param  TIMx Timer instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CHANNEL_CH1

+  *         @arg @ref LL_TIM_CHANNEL_CH2

+  *         @arg @ref LL_TIM_CHANNEL_CH3

+  *         @arg @ref LL_TIM_CHANNEL_CH4

+  *         @arg @ref LL_TIM_CHANNEL_CH5

+  *         @arg @ref LL_TIM_CHANNEL_CH6

+  * @param  Configuration This parameter must be a combination of all the following values:

+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW

+  *         @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)

+{

+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));

+  CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));

+  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),

+             (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);

+  MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),

+             (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);

+}

+

+/**

+  * @brief  Define the behavior of the output reference signal OCxREF from which

+  *         OCx and OCxN (when relevant) are derived.

+  * @rmtoll CCMR1        OC1M          LL_TIM_OC_SetMode\n

+  *         CCMR1        OC2M          LL_TIM_OC_SetMode\n

+  *         CCMR2        OC3M          LL_TIM_OC_SetMode\n

+  *         CCMR2        OC4M          LL_TIM_OC_SetMode\n

+  *         CCMR3        OC5M          LL_TIM_OC_SetMode\n

+  *         CCMR3        OC6M          LL_TIM_OC_SetMode

+  * @param  TIMx Timer instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CHANNEL_CH1

+  *         @arg @ref LL_TIM_CHANNEL_CH2

+  *         @arg @ref LL_TIM_CHANNEL_CH3

+  *         @arg @ref LL_TIM_CHANNEL_CH4

+  *         @arg @ref LL_TIM_CHANNEL_CH5

+  *         @arg @ref LL_TIM_CHANNEL_CH6

+  * @param  Mode This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_OCMODE_FROZEN

+  *         @arg @ref LL_TIM_OCMODE_ACTIVE

+  *         @arg @ref LL_TIM_OCMODE_INACTIVE

+  *         @arg @ref LL_TIM_OCMODE_TOGGLE

+  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE

+  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE

+  *         @arg @ref LL_TIM_OCMODE_PWM1

+  *         @arg @ref LL_TIM_OCMODE_PWM2

+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1

+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2

+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1

+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2

+  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1

+  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)

+{

+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));

+  MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]),  Mode << SHIFT_TAB_OCxx[iChannel]);

+}

+

+/**

+  * @brief  Get the output compare mode of an output channel.

+  * @rmtoll CCMR1        OC1M          LL_TIM_OC_GetMode\n

+  *         CCMR1        OC2M          LL_TIM_OC_GetMode\n

+  *         CCMR2        OC3M          LL_TIM_OC_GetMode\n

+  *         CCMR2        OC4M          LL_TIM_OC_GetMode\n

+  *         CCMR3        OC5M          LL_TIM_OC_GetMode\n

+  *         CCMR3        OC6M          LL_TIM_OC_GetMode

+  * @param  TIMx Timer instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CHANNEL_CH1

+  *         @arg @ref LL_TIM_CHANNEL_CH2

+  *         @arg @ref LL_TIM_CHANNEL_CH3

+  *         @arg @ref LL_TIM_CHANNEL_CH4

+  *         @arg @ref LL_TIM_CHANNEL_CH5

+  *         @arg @ref LL_TIM_CHANNEL_CH6

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_TIM_OCMODE_FROZEN

+  *         @arg @ref LL_TIM_OCMODE_ACTIVE

+  *         @arg @ref LL_TIM_OCMODE_INACTIVE

+  *         @arg @ref LL_TIM_OCMODE_TOGGLE

+  *         @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE

+  *         @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE

+  *         @arg @ref LL_TIM_OCMODE_PWM1

+  *         @arg @ref LL_TIM_OCMODE_PWM2

+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM1

+  *         @arg @ref LL_TIM_OCMODE_RETRIG_OPM2

+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM1

+  *         @arg @ref LL_TIM_OCMODE_COMBINED_PWM2

+  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1

+  *         @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2

+  */

+__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)

+{

+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));

+  return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M  | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);

+}

+

+/**

+  * @brief  Set the polarity of an output channel.

+  * @rmtoll CCER         CC1P          LL_TIM_OC_SetPolarity\n

+  *         CCER         CC1NP         LL_TIM_OC_SetPolarity\n

+  *         CCER         CC2P          LL_TIM_OC_SetPolarity\n

+  *         CCER         CC2NP         LL_TIM_OC_SetPolarity\n

+  *         CCER         CC3P          LL_TIM_OC_SetPolarity\n

+  *         CCER         CC3NP         LL_TIM_OC_SetPolarity\n

+  *         CCER         CC4P          LL_TIM_OC_SetPolarity\n

+  *         CCER         CC5P          LL_TIM_OC_SetPolarity\n

+  *         CCER         CC6P          LL_TIM_OC_SetPolarity

+  * @param  TIMx Timer instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CHANNEL_CH1

+  *         @arg @ref LL_TIM_CHANNEL_CH1N

+  *         @arg @ref LL_TIM_CHANNEL_CH2

+  *         @arg @ref LL_TIM_CHANNEL_CH2N

+  *         @arg @ref LL_TIM_CHANNEL_CH3

+  *         @arg @ref LL_TIM_CHANNEL_CH3N

+  *         @arg @ref LL_TIM_CHANNEL_CH4

+  *         @arg @ref LL_TIM_CHANNEL_CH5

+  *         @arg @ref LL_TIM_CHANNEL_CH6

+  * @param  Polarity This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH

+  *         @arg @ref LL_TIM_OCPOLARITY_LOW

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)

+{

+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);

+  MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),  Polarity << SHIFT_TAB_CCxP[iChannel]);

+}

+

+/**

+  * @brief  Get the polarity of an output channel.

+  * @rmtoll CCER         CC1P          LL_TIM_OC_GetPolarity\n

+  *         CCER         CC1NP         LL_TIM_OC_GetPolarity\n

+  *         CCER         CC2P          LL_TIM_OC_GetPolarity\n

+  *         CCER         CC2NP         LL_TIM_OC_GetPolarity\n

+  *         CCER         CC3P          LL_TIM_OC_GetPolarity\n

+  *         CCER         CC3NP         LL_TIM_OC_GetPolarity\n

+  *         CCER         CC4P          LL_TIM_OC_GetPolarity\n

+  *         CCER         CC5P          LL_TIM_OC_GetPolarity\n

+  *         CCER         CC6P          LL_TIM_OC_GetPolarity

+  * @param  TIMx Timer instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CHANNEL_CH1

+  *         @arg @ref LL_TIM_CHANNEL_CH1N

+  *         @arg @ref LL_TIM_CHANNEL_CH2

+  *         @arg @ref LL_TIM_CHANNEL_CH2N

+  *         @arg @ref LL_TIM_CHANNEL_CH3

+  *         @arg @ref LL_TIM_CHANNEL_CH3N

+  *         @arg @ref LL_TIM_CHANNEL_CH4

+  *         @arg @ref LL_TIM_CHANNEL_CH5

+  *         @arg @ref LL_TIM_CHANNEL_CH6

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_TIM_OCPOLARITY_HIGH

+  *         @arg @ref LL_TIM_OCPOLARITY_LOW

+  */

+__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)

+{

+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);

+  return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);

+}

+

+/**

+  * @brief  Set the IDLE state of an output channel

+  * @note This function is significant only for the timer instances

+  *       supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx)

+  *       can be used to check whether or not a timer instance provides

+  *       a break input.

+  * @rmtoll CR2         OIS1          LL_TIM_OC_SetIdleState\n

+  *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n

+  *         CR2         OIS2          LL_TIM_OC_SetIdleState\n

+  *         CR2         OIS2N         LL_TIM_OC_SetIdleState\n

+  *         CR2         OIS3          LL_TIM_OC_SetIdleState\n

+  *         CR2         OIS3N         LL_TIM_OC_SetIdleState\n

+  *         CR2         OIS4          LL_TIM_OC_SetIdleState\n

+  *         CR2         OIS5          LL_TIM_OC_SetIdleState\n

+  *         CR2         OIS6          LL_TIM_OC_SetIdleState

+  * @param  TIMx Timer instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CHANNEL_CH1

+  *         @arg @ref LL_TIM_CHANNEL_CH1N

+  *         @arg @ref LL_TIM_CHANNEL_CH2

+  *         @arg @ref LL_TIM_CHANNEL_CH2N

+  *         @arg @ref LL_TIM_CHANNEL_CH3

+  *         @arg @ref LL_TIM_CHANNEL_CH3N

+  *         @arg @ref LL_TIM_CHANNEL_CH4

+  *         @arg @ref LL_TIM_CHANNEL_CH5

+  *         @arg @ref LL_TIM_CHANNEL_CH6

+  * @param  IdleState This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_OCIDLESTATE_LOW

+  *         @arg @ref LL_TIM_OCIDLESTATE_HIGH

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)

+{

+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);

+  MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),  IdleState << SHIFT_TAB_OISx[iChannel]);

+}

+

+/**

+  * @brief  Get the IDLE state of an output channel

+  * @rmtoll CR2         OIS1          LL_TIM_OC_GetIdleState\n

+  *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n

+  *         CR2         OIS2          LL_TIM_OC_GetIdleState\n

+  *         CR2         OIS2N         LL_TIM_OC_GetIdleState\n

+  *         CR2         OIS3          LL_TIM_OC_GetIdleState\n

+  *         CR2         OIS3N         LL_TIM_OC_GetIdleState\n

+  *         CR2         OIS4          LL_TIM_OC_GetIdleState\n

+  *         CR2         OIS5          LL_TIM_OC_GetIdleState\n

+  *         CR2         OIS6          LL_TIM_OC_GetIdleState

+  * @param  TIMx Timer instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CHANNEL_CH1

+  *         @arg @ref LL_TIM_CHANNEL_CH1N

+  *         @arg @ref LL_TIM_CHANNEL_CH2

+  *         @arg @ref LL_TIM_CHANNEL_CH2N

+  *         @arg @ref LL_TIM_CHANNEL_CH3

+  *         @arg @ref LL_TIM_CHANNEL_CH3N

+  *         @arg @ref LL_TIM_CHANNEL_CH4

+  *         @arg @ref LL_TIM_CHANNEL_CH5

+  *         @arg @ref LL_TIM_CHANNEL_CH6

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_TIM_OCIDLESTATE_LOW

+  *         @arg @ref LL_TIM_OCIDLESTATE_HIGH

+  */

+__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)

+{

+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);

+  return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);

+}

+

+/**

+  * @brief  Enable fast mode for the output channel.

+  * @note Acts only if the channel is configured in PWM1 or PWM2 mode.

+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_EnableFast\n

+  *         CCMR1        OC2FE          LL_TIM_OC_EnableFast\n

+  *         CCMR2        OC3FE          LL_TIM_OC_EnableFast\n

+  *         CCMR2        OC4FE          LL_TIM_OC_EnableFast\n

+  *         CCMR3        OC5FE          LL_TIM_OC_EnableFast\n

+  *         CCMR3        OC6FE          LL_TIM_OC_EnableFast

+  * @param  TIMx Timer instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CHANNEL_CH1

+  *         @arg @ref LL_TIM_CHANNEL_CH2

+  *         @arg @ref LL_TIM_CHANNEL_CH3

+  *         @arg @ref LL_TIM_CHANNEL_CH4

+  *         @arg @ref LL_TIM_CHANNEL_CH5

+  *         @arg @ref LL_TIM_CHANNEL_CH6

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)

+{

+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));

+  SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));

+

+}

+

+/**

+  * @brief  Disable fast mode for the output channel.

+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_DisableFast\n

+  *         CCMR1        OC2FE          LL_TIM_OC_DisableFast\n

+  *         CCMR2        OC3FE          LL_TIM_OC_DisableFast\n

+  *         CCMR2        OC4FE          LL_TIM_OC_DisableFast\n

+  *         CCMR3        OC5FE          LL_TIM_OC_DisableFast\n

+  *         CCMR3        OC6FE          LL_TIM_OC_DisableFast

+  * @param  TIMx Timer instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CHANNEL_CH1

+  *         @arg @ref LL_TIM_CHANNEL_CH2

+  *         @arg @ref LL_TIM_CHANNEL_CH3

+  *         @arg @ref LL_TIM_CHANNEL_CH4

+  *         @arg @ref LL_TIM_CHANNEL_CH5

+  *         @arg @ref LL_TIM_CHANNEL_CH6

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)

+{

+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));

+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));

+

+}

+

+/**

+  * @brief  Indicates whether fast mode is enabled for the output channel.

+  * @rmtoll CCMR1        OC1FE          LL_TIM_OC_IsEnabledFast\n

+  *         CCMR1        OC2FE          LL_TIM_OC_IsEnabledFast\n

+  *         CCMR2        OC3FE          LL_TIM_OC_IsEnabledFast\n

+  *         CCMR2        OC4FE          LL_TIM_OC_IsEnabledFast\n

+  *         CCMR3        OC5FE          LL_TIM_OC_IsEnabledFast\n

+  *         CCMR3        OC6FE          LL_TIM_OC_IsEnabledFast

+  * @param  TIMx Timer instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CHANNEL_CH1

+  *         @arg @ref LL_TIM_CHANNEL_CH2

+  *         @arg @ref LL_TIM_CHANNEL_CH3

+  *         @arg @ref LL_TIM_CHANNEL_CH4

+  *         @arg @ref LL_TIM_CHANNEL_CH5

+  *         @arg @ref LL_TIM_CHANNEL_CH6

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)

+{

+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));

+  register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];

+  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable compare register (TIMx_CCRx) preload for the output channel.

+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_EnablePreload\n

+  *         CCMR1        OC2PE          LL_TIM_OC_EnablePreload\n

+  *         CCMR2        OC3PE          LL_TIM_OC_EnablePreload\n

+  *         CCMR2        OC4PE          LL_TIM_OC_EnablePreload\n

+  *         CCMR3        OC5PE          LL_TIM_OC_EnablePreload\n

+  *         CCMR3        OC6PE          LL_TIM_OC_EnablePreload

+  * @param  TIMx Timer instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CHANNEL_CH1

+  *         @arg @ref LL_TIM_CHANNEL_CH2

+  *         @arg @ref LL_TIM_CHANNEL_CH3

+  *         @arg @ref LL_TIM_CHANNEL_CH4

+  *         @arg @ref LL_TIM_CHANNEL_CH5

+  *         @arg @ref LL_TIM_CHANNEL_CH6

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)

+{

+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));

+  SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));

+}

+

+/**

+  * @brief  Disable compare register (TIMx_CCRx) preload for the output channel.

+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_DisablePreload\n

+  *         CCMR1        OC2PE          LL_TIM_OC_DisablePreload\n

+  *         CCMR2        OC3PE          LL_TIM_OC_DisablePreload\n

+  *         CCMR2        OC4PE          LL_TIM_OC_DisablePreload\n

+  *         CCMR3        OC5PE          LL_TIM_OC_DisablePreload\n

+  *         CCMR3        OC6PE          LL_TIM_OC_DisablePreload

+  * @param  TIMx Timer instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CHANNEL_CH1

+  *         @arg @ref LL_TIM_CHANNEL_CH2

+  *         @arg @ref LL_TIM_CHANNEL_CH3

+  *         @arg @ref LL_TIM_CHANNEL_CH4

+  *         @arg @ref LL_TIM_CHANNEL_CH5

+  *         @arg @ref LL_TIM_CHANNEL_CH6

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)

+{

+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));

+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));

+}

+

+/**

+  * @brief  Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.

+  * @rmtoll CCMR1        OC1PE          LL_TIM_OC_IsEnabledPreload\n

+  *         CCMR1        OC2PE          LL_TIM_OC_IsEnabledPreload\n

+  *         CCMR2        OC3PE          LL_TIM_OC_IsEnabledPreload\n

+  *         CCMR2        OC4PE          LL_TIM_OC_IsEnabledPreload\n

+  *         CCMR3        OC5PE          LL_TIM_OC_IsEnabledPreload\n

+  *         CCMR3        OC6PE          LL_TIM_OC_IsEnabledPreload

+  * @param  TIMx Timer instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CHANNEL_CH1

+  *         @arg @ref LL_TIM_CHANNEL_CH2

+  *         @arg @ref LL_TIM_CHANNEL_CH3

+  *         @arg @ref LL_TIM_CHANNEL_CH4

+  *         @arg @ref LL_TIM_CHANNEL_CH5

+  *         @arg @ref LL_TIM_CHANNEL_CH6

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)

+{

+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));

+  register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];

+  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable clearing the output channel on an external event.

+  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.

+  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether

+  *       or not a timer instance can clear the OCxREF signal on an external event.

+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_EnableClear\n

+  *         CCMR1        OC2CE          LL_TIM_OC_EnableClear\n

+  *         CCMR2        OC3CE          LL_TIM_OC_EnableClear\n

+  *         CCMR2        OC4CE          LL_TIM_OC_EnableClear\n

+  *         CCMR3        OC5CE          LL_TIM_OC_EnableClear\n

+  *         CCMR3        OC6CE          LL_TIM_OC_EnableClear

+  * @param  TIMx Timer instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CHANNEL_CH1

+  *         @arg @ref LL_TIM_CHANNEL_CH2

+  *         @arg @ref LL_TIM_CHANNEL_CH3

+  *         @arg @ref LL_TIM_CHANNEL_CH4

+  *         @arg @ref LL_TIM_CHANNEL_CH5

+  *         @arg @ref LL_TIM_CHANNEL_CH6

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)

+{

+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));

+  SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));

+}

+

+/**

+  * @brief  Disable clearing the output channel on an external event.

+  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether

+  *       or not a timer instance can clear the OCxREF signal on an external event.

+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_DisableClear\n

+  *         CCMR1        OC2CE          LL_TIM_OC_DisableClear\n

+  *         CCMR2        OC3CE          LL_TIM_OC_DisableClear\n

+  *         CCMR2        OC4CE          LL_TIM_OC_DisableClear\n

+  *         CCMR3        OC5CE          LL_TIM_OC_DisableClear\n

+  *         CCMR3        OC6CE          LL_TIM_OC_DisableClear

+  * @param  TIMx Timer instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CHANNEL_CH1

+  *         @arg @ref LL_TIM_CHANNEL_CH2

+  *         @arg @ref LL_TIM_CHANNEL_CH3

+  *         @arg @ref LL_TIM_CHANNEL_CH4

+  *         @arg @ref LL_TIM_CHANNEL_CH5

+  *         @arg @ref LL_TIM_CHANNEL_CH6

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)

+{

+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));

+  CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));

+}

+

+/**

+  * @brief  Indicates clearing the output channel on an external event is enabled for the output channel.

+  * @note This function enables clearing the output channel on an external event.

+  * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.

+  * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether

+  *       or not a timer instance can clear the OCxREF signal on an external event.

+  * @rmtoll CCMR1        OC1CE          LL_TIM_OC_IsEnabledClear\n

+  *         CCMR1        OC2CE          LL_TIM_OC_IsEnabledClear\n

+  *         CCMR2        OC3CE          LL_TIM_OC_IsEnabledClear\n

+  *         CCMR2        OC4CE          LL_TIM_OC_IsEnabledClear\n

+  *         CCMR3        OC5CE          LL_TIM_OC_IsEnabledClear\n

+  *         CCMR3        OC6CE          LL_TIM_OC_IsEnabledClear

+  * @param  TIMx Timer instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CHANNEL_CH1

+  *         @arg @ref LL_TIM_CHANNEL_CH2

+  *         @arg @ref LL_TIM_CHANNEL_CH3

+  *         @arg @ref LL_TIM_CHANNEL_CH4

+  *         @arg @ref LL_TIM_CHANNEL_CH5

+  *         @arg @ref LL_TIM_CHANNEL_CH6

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)

+{

+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));

+  register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];

+  return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals).

+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not

+  *       dead-time insertion feature is supported by a timer instance.

+  * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter

+  * @rmtoll BDTR         DTG           LL_TIM_OC_SetDeadTime

+  * @param  TIMx Timer instance

+  * @param  DeadTime between Min_Data=0 and Max_Data=255

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)

+{

+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);

+}

+

+/**

+  * @brief  Set compare value for output channel 1 (TIMx_CCR1).

+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.

+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check

+  *       whether or not a timer instance supports a 32 bits counter.

+  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not

+  *       output channel 1 is supported by a timer instance.

+  * @rmtoll CCR1         CCR1          LL_TIM_OC_SetCompareCH1

+  * @param  TIMx Timer instance

+  * @param  CompareValue between Min_Data=0 and Max_Data=65535

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)

+{

+  WRITE_REG(TIMx->CCR1, CompareValue);

+}

+

+/**

+  * @brief  Set compare value for output channel 2 (TIMx_CCR2).

+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.

+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check

+  *       whether or not a timer instance supports a 32 bits counter.

+  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not

+  *       output channel 2 is supported by a timer instance.

+  * @rmtoll CCR2         CCR2          LL_TIM_OC_SetCompareCH2

+  * @param  TIMx Timer instance

+  * @param  CompareValue between Min_Data=0 and Max_Data=65535

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)

+{

+  WRITE_REG(TIMx->CCR2, CompareValue);

+}

+

+/**

+  * @brief  Set compare value for output channel 3 (TIMx_CCR3).

+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.

+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check

+  *       whether or not a timer instance supports a 32 bits counter.

+  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not

+  *       output channel is supported by a timer instance.

+  * @rmtoll CCR3         CCR3          LL_TIM_OC_SetCompareCH3

+  * @param  TIMx Timer instance

+  * @param  CompareValue between Min_Data=0 and Max_Data=65535

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)

+{

+  WRITE_REG(TIMx->CCR3, CompareValue);

+}

+

+/**

+  * @brief  Set compare value for output channel 4 (TIMx_CCR4).

+  * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.

+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check

+  *       whether or not a timer instance supports a 32 bits counter.

+  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not

+  *       output channel 4 is supported by a timer instance.

+  * @rmtoll CCR4         CCR4          LL_TIM_OC_SetCompareCH4

+  * @param  TIMx Timer instance

+  * @param  CompareValue between Min_Data=0 and Max_Data=65535

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)

+{

+  WRITE_REG(TIMx->CCR4, CompareValue);

+}

+

+/**

+  * @brief  Set compare value for output channel 5 (TIMx_CCR5).

+  * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not

+  *       output channel 5 is supported by a timer instance.

+  * @rmtoll CCR5         CCR5          LL_TIM_OC_SetCompareCH5

+  * @param  TIMx Timer instance

+  * @param  CompareValue between Min_Data=0 and Max_Data=65535

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)

+{

+  MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, CompareValue);

+}

+

+/**

+  * @brief  Set compare value for output channel 6 (TIMx_CCR6).

+  * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not

+  *       output channel 6 is supported by a timer instance.

+  * @rmtoll CCR6         CCR6          LL_TIM_OC_SetCompareCH6

+  * @param  TIMx Timer instance

+  * @param  CompareValue between Min_Data=0 and Max_Data=65535

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)

+{

+  WRITE_REG(TIMx->CCR6, CompareValue);

+}

+

+/**

+  * @brief  Get compare value (TIMx_CCR1) set for  output channel 1.

+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.

+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check

+  *       whether or not a timer instance supports a 32 bits counter.

+  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not

+  *       output channel 1 is supported by a timer instance.

+  * @rmtoll CCR1         CCR1          LL_TIM_OC_GetCompareCH1

+  * @param  TIMx Timer instance

+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)

+  */

+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)

+{

+  return (uint32_t)(READ_REG(TIMx->CCR1));

+}

+

+/**

+  * @brief  Get compare value (TIMx_CCR2) set for  output channel 2.

+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.

+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check

+  *       whether or not a timer instance supports a 32 bits counter.

+  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not

+  *       output channel 2 is supported by a timer instance.

+  * @rmtoll CCR2         CCR2          LL_TIM_OC_GetCompareCH2

+  * @param  TIMx Timer instance

+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)

+  */

+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)

+{

+  return (uint32_t)(READ_REG(TIMx->CCR2));

+}

+

+/**

+  * @brief  Get compare value (TIMx_CCR3) set for  output channel 3.

+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.

+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check

+  *       whether or not a timer instance supports a 32 bits counter.

+  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not

+  *       output channel 3 is supported by a timer instance.

+  * @rmtoll CCR3         CCR3          LL_TIM_OC_GetCompareCH3

+  * @param  TIMx Timer instance

+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)

+  */

+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)

+{

+  return (uint32_t)(READ_REG(TIMx->CCR3));

+}

+

+/**

+  * @brief  Get compare value (TIMx_CCR4) set for  output channel 4.

+  * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.

+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check

+  *       whether or not a timer instance supports a 32 bits counter.

+  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not

+  *       output channel 4 is supported by a timer instance.

+  * @rmtoll CCR4         CCR4          LL_TIM_OC_GetCompareCH4

+  * @param  TIMx Timer instance

+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)

+  */

+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)

+{

+  return (uint32_t)(READ_REG(TIMx->CCR4));

+}

+

+/**

+  * @brief  Get compare value (TIMx_CCR5) set for  output channel 5.

+  * @note Macro IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not

+  *       output channel 5 is supported by a timer instance.

+  * @rmtoll CCR5         CCR5          LL_TIM_OC_GetCompareCH5

+  * @param  TIMx Timer instance

+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)

+  */

+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)

+{

+  return (uint32_t)(READ_BIT(TIMx->CCR5, TIM_CCR5_CCR5));

+}

+

+/**

+  * @brief  Get compare value (TIMx_CCR6) set for  output channel 6.

+  * @note Macro IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not

+  *       output channel 6 is supported by a timer instance.

+  * @rmtoll CCR6         CCR6          LL_TIM_OC_GetCompareCH6

+  * @param  TIMx Timer instance

+  * @retval CompareValue (between Min_Data=0 and Max_Data=65535)

+  */

+__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)

+{

+  return (uint32_t)(READ_REG(TIMx->CCR6));

+}

+

+/**

+  * @brief  Select on which reference signal the OC5REF is combined to.

+  * @note Macro IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check

+  *       whether or not a timer instance supports the combined 3-phase PWM mode.

+  * @rmtoll CCR5         GC5C3          LL_TIM_SetCH5CombinedChannels\n

+  *         CCR5         GC5C2          LL_TIM_SetCH5CombinedChannels\n

+  *         CCR5         GC5C1          LL_TIM_SetCH5CombinedChannels

+  * @param  TIMx Timer instance

+  * @param  GroupCH5 This parameter can be a combination of the following values:

+  *         @arg @ref LL_TIM_GROUPCH5_NONE

+  *         @arg @ref LL_TIM_GROUPCH5_OC1REFC

+  *         @arg @ref LL_TIM_GROUPCH5_OC2REFC

+  *         @arg @ref LL_TIM_GROUPCH5_OC3REFC

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)

+{

+  MODIFY_REG(TIMx->CCR5, (TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1), GroupCH5);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration

+  * @{

+  */

+/**

+  * @brief  Configure input channel.

+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_Config\n

+  *         CCMR1        IC1PSC        LL_TIM_IC_Config\n

+  *         CCMR1        IC1F          LL_TIM_IC_Config\n

+  *         CCMR1        CC2S          LL_TIM_IC_Config\n

+  *         CCMR1        IC2PSC        LL_TIM_IC_Config\n

+  *         CCMR1        IC2F          LL_TIM_IC_Config\n

+  *         CCMR2        CC3S          LL_TIM_IC_Config\n

+  *         CCMR2        IC3PSC        LL_TIM_IC_Config\n

+  *         CCMR2        IC3F          LL_TIM_IC_Config\n

+  *         CCMR2        CC4S          LL_TIM_IC_Config\n

+  *         CCMR2        IC4PSC        LL_TIM_IC_Config\n

+  *         CCMR2        IC4F          LL_TIM_IC_Config\n

+  *         CCER         CC1P          LL_TIM_IC_Config\n

+  *         CCER         CC1NP         LL_TIM_IC_Config\n

+  *         CCER         CC2P          LL_TIM_IC_Config\n

+  *         CCER         CC2NP         LL_TIM_IC_Config\n

+  *         CCER         CC3P          LL_TIM_IC_Config\n

+  *         CCER         CC3NP         LL_TIM_IC_Config\n

+  *         CCER         CC4P          LL_TIM_IC_Config\n

+  *         CCER         CC4NP         LL_TIM_IC_Config

+  * @param  TIMx Timer instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CHANNEL_CH1

+  *         @arg @ref LL_TIM_CHANNEL_CH2

+  *         @arg @ref LL_TIM_CHANNEL_CH3

+  *         @arg @ref LL_TIM_CHANNEL_CH4

+  * @param  Configuration This parameter must be a combination of all the following values:

+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC

+  *         @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8

+  *         @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)

+{

+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));

+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),

+             ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S))  << SHIFT_TAB_ICxx[iChannel]);

+  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),

+             (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);

+}

+

+/**

+  * @brief  Set the active input.

+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_SetActiveInput\n

+  *         CCMR1        CC2S          LL_TIM_IC_SetActiveInput\n

+  *         CCMR2        CC3S          LL_TIM_IC_SetActiveInput\n

+  *         CCMR2        CC4S          LL_TIM_IC_SetActiveInput

+  * @param  TIMx Timer instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CHANNEL_CH1

+  *         @arg @ref LL_TIM_CHANNEL_CH2

+  *         @arg @ref LL_TIM_CHANNEL_CH3

+  *         @arg @ref LL_TIM_CHANNEL_CH4

+  * @param  ICActiveInput This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI

+  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI

+  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)

+{

+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));

+  MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);

+}

+

+/**

+  * @brief  Get the current active input.

+  * @rmtoll CCMR1        CC1S          LL_TIM_IC_GetActiveInput\n

+  *         CCMR1        CC2S          LL_TIM_IC_GetActiveInput\n

+  *         CCMR2        CC3S          LL_TIM_IC_GetActiveInput\n

+  *         CCMR2        CC4S          LL_TIM_IC_GetActiveInput

+  * @param  TIMx Timer instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CHANNEL_CH1

+  *         @arg @ref LL_TIM_CHANNEL_CH2

+  *         @arg @ref LL_TIM_CHANNEL_CH3

+  *         @arg @ref LL_TIM_CHANNEL_CH4

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI

+  *         @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI

+  *         @arg @ref LL_TIM_ACTIVEINPUT_TRC

+  */

+__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)

+{

+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));

+  return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);

+}

+

+/**

+  * @brief  Set the prescaler of input channel.

+  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_SetPrescaler\n

+  *         CCMR1        IC2PSC        LL_TIM_IC_SetPrescaler\n

+  *         CCMR2        IC3PSC        LL_TIM_IC_SetPrescaler\n

+  *         CCMR2        IC4PSC        LL_TIM_IC_SetPrescaler

+  * @param  TIMx Timer instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CHANNEL_CH1

+  *         @arg @ref LL_TIM_CHANNEL_CH2

+  *         @arg @ref LL_TIM_CHANNEL_CH3

+  *         @arg @ref LL_TIM_CHANNEL_CH4

+  * @param  ICPrescaler This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_ICPSC_DIV1

+  *         @arg @ref LL_TIM_ICPSC_DIV2

+  *         @arg @ref LL_TIM_ICPSC_DIV4

+  *         @arg @ref LL_TIM_ICPSC_DIV8

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)

+{

+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));

+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);

+}

+

+/**

+  * @brief  Get the current prescaler value acting on an  input channel.

+  * @rmtoll CCMR1        IC1PSC        LL_TIM_IC_GetPrescaler\n

+  *         CCMR1        IC2PSC        LL_TIM_IC_GetPrescaler\n

+  *         CCMR2        IC3PSC        LL_TIM_IC_GetPrescaler\n

+  *         CCMR2        IC4PSC        LL_TIM_IC_GetPrescaler

+  * @param  TIMx Timer instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CHANNEL_CH1

+  *         @arg @ref LL_TIM_CHANNEL_CH2

+  *         @arg @ref LL_TIM_CHANNEL_CH3

+  *         @arg @ref LL_TIM_CHANNEL_CH4

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_TIM_ICPSC_DIV1

+  *         @arg @ref LL_TIM_ICPSC_DIV2

+  *         @arg @ref LL_TIM_ICPSC_DIV4

+  *         @arg @ref LL_TIM_ICPSC_DIV8

+  */

+__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)

+{

+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));

+  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);

+}

+

+/**

+  * @brief  Set the input filter duration.

+  * @rmtoll CCMR1        IC1F          LL_TIM_IC_SetFilter\n

+  *         CCMR1        IC2F          LL_TIM_IC_SetFilter\n

+  *         CCMR2        IC3F          LL_TIM_IC_SetFilter\n

+  *         CCMR2        IC4F          LL_TIM_IC_SetFilter

+  * @param  TIMx Timer instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CHANNEL_CH1

+  *         @arg @ref LL_TIM_CHANNEL_CH2

+  *         @arg @ref LL_TIM_CHANNEL_CH3

+  *         @arg @ref LL_TIM_CHANNEL_CH4

+  * @param  ICFilter This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)

+{

+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));

+  MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);

+}

+

+/**

+  * @brief  Get the input filter duration.

+  * @rmtoll CCMR1        IC1F          LL_TIM_IC_GetFilter\n

+  *         CCMR1        IC2F          LL_TIM_IC_GetFilter\n

+  *         CCMR2        IC3F          LL_TIM_IC_GetFilter\n

+  *         CCMR2        IC4F          LL_TIM_IC_GetFilter

+  * @param  TIMx Timer instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CHANNEL_CH1

+  *         @arg @ref LL_TIM_CHANNEL_CH2

+  *         @arg @ref LL_TIM_CHANNEL_CH3

+  *         @arg @ref LL_TIM_CHANNEL_CH4

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N2

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N4

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV1_N8

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N6

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV2_N8

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N6

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV4_N8

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N6

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV8_N8

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N5

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N6

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV16_N8

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N5

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N6

+  *         @arg @ref LL_TIM_IC_FILTER_FDIV32_N8

+  */

+__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)

+{

+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);

+  register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));

+  return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);

+}

+

+/**

+  * @brief  Set the input channel polarity.

+  * @rmtoll CCER         CC1P          LL_TIM_IC_SetPolarity\n

+  *         CCER         CC1NP         LL_TIM_IC_SetPolarity\n

+  *         CCER         CC2P          LL_TIM_IC_SetPolarity\n

+  *         CCER         CC2NP         LL_TIM_IC_SetPolarity\n

+  *         CCER         CC3P          LL_TIM_IC_SetPolarity\n

+  *         CCER         CC3NP         LL_TIM_IC_SetPolarity\n

+  *         CCER         CC4P          LL_TIM_IC_SetPolarity\n

+  *         CCER         CC4NP         LL_TIM_IC_SetPolarity

+  * @param  TIMx Timer instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CHANNEL_CH1

+  *         @arg @ref LL_TIM_CHANNEL_CH2

+  *         @arg @ref LL_TIM_CHANNEL_CH3

+  *         @arg @ref LL_TIM_CHANNEL_CH4

+  * @param  ICPolarity This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_IC_POLARITY_RISING

+  *         @arg @ref LL_TIM_IC_POLARITY_FALLING

+  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)

+{

+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);

+  MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),

+             ICPolarity << SHIFT_TAB_CCxP[iChannel]);

+}

+

+/**

+  * @brief  Get the current input channel polarity.

+  * @rmtoll CCER         CC1P          LL_TIM_IC_GetPolarity\n

+  *         CCER         CC1NP         LL_TIM_IC_GetPolarity\n

+  *         CCER         CC2P          LL_TIM_IC_GetPolarity\n

+  *         CCER         CC2NP         LL_TIM_IC_GetPolarity\n

+  *         CCER         CC3P          LL_TIM_IC_GetPolarity\n

+  *         CCER         CC3NP         LL_TIM_IC_GetPolarity\n

+  *         CCER         CC4P          LL_TIM_IC_GetPolarity\n

+  *         CCER         CC4NP         LL_TIM_IC_GetPolarity

+  * @param  TIMx Timer instance

+  * @param  Channel This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CHANNEL_CH1

+  *         @arg @ref LL_TIM_CHANNEL_CH2

+  *         @arg @ref LL_TIM_CHANNEL_CH3

+  *         @arg @ref LL_TIM_CHANNEL_CH4

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_TIM_IC_POLARITY_RISING

+  *         @arg @ref LL_TIM_IC_POLARITY_FALLING

+  *         @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE

+  */

+__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)

+{

+  register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);

+  return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>

+          SHIFT_TAB_CCxP[iChannel]);

+}

+

+/**

+  * @brief  Connect the TIMx_CH1, CH2 and CH3 pins  to the TI1 input (XOR combination).

+  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not

+  *       a timer instance provides an XOR input.

+  * @rmtoll CR2          TI1S          LL_TIM_IC_EnableXORCombination

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->CR2, TIM_CR2_TI1S);

+}

+

+/**

+  * @brief  Disconnect the TIMx_CH1, CH2 and CH3 pins  from the TI1 input.

+  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not

+  *       a timer instance provides an XOR input.

+  * @rmtoll CR2          TI1S          LL_TIM_IC_DisableXORCombination

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)

+{

+  CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);

+}

+

+/**

+  * @brief  Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.

+  * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not

+  * a timer instance provides an XOR input.

+  * @rmtoll CR2          TI1S          LL_TIM_IC_IsEnabledXORCombination

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get captured value for input channel 1.

+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.

+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check

+  *       whether or not a timer instance supports a 32 bits counter.

+  * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not

+  *       input channel 1 is supported by a timer instance.

+  * @rmtoll CCR1         CCR1          LL_TIM_IC_GetCaptureCH1

+  * @param  TIMx Timer instance

+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)

+  */

+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)

+{

+  return (uint32_t)(READ_REG(TIMx->CCR1));

+}

+

+/**

+  * @brief  Get captured value for input channel 2.

+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.

+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check

+  *       whether or not a timer instance supports a 32 bits counter.

+  * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not

+  *       input channel 2 is supported by a timer instance.

+  * @rmtoll CCR2         CCR2          LL_TIM_IC_GetCaptureCH2

+  * @param  TIMx Timer instance

+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)

+  */

+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)

+{

+  return (uint32_t)(READ_REG(TIMx->CCR2));

+}

+

+/**

+  * @brief  Get captured value for input channel 3.

+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.

+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check

+  *       whether or not a timer instance supports a 32 bits counter.

+  * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not

+  *       input channel 3 is supported by a timer instance.

+  * @rmtoll CCR3         CCR3          LL_TIM_IC_GetCaptureCH3

+  * @param  TIMx Timer instance

+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)

+  */

+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)

+{

+  return (uint32_t)(READ_REG(TIMx->CCR3));

+}

+

+/**

+  * @brief  Get captured value for input channel 4.

+  * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.

+  * @note Macro IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check

+  *       whether or not a timer instance supports a 32 bits counter.

+  * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not

+  *       input channel 4 is supported by a timer instance.

+  * @rmtoll CCR4         CCR4          LL_TIM_IC_GetCaptureCH4

+  * @param  TIMx Timer instance

+  * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)

+  */

+__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)

+{

+  return (uint32_t)(READ_REG(TIMx->CCR4));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection

+  * @{

+  */

+/**

+  * @brief  Enable external clock mode 2.

+  * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.

+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check

+  *       whether or not a timer instance supports external clock mode2.

+  * @rmtoll SMCR         ECE           LL_TIM_EnableExternalClock

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);

+}

+

+/**

+  * @brief  Disable external clock mode 2.

+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check

+  *       whether or not a timer instance supports external clock mode2.

+  * @rmtoll SMCR         ECE           LL_TIM_DisableExternalClock

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)

+{

+  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);

+}

+

+/**

+  * @brief  Indicate whether external clock mode 2 is enabled.

+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check

+  *       whether or not a timer instance supports external clock mode2.

+  * @rmtoll SMCR         ECE           LL_TIM_IsEnabledExternalClock

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set the clock source of the counter clock.

+  * @note when selected clock source is external clock mode 1, the timer input

+  *       the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()

+  *       function. This timer input must be configured by calling

+  *       the @ref LL_TIM_IC_Config() function.

+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check

+  *       whether or not a timer instance supports external clock mode1.

+  * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check

+  *       whether or not a timer instance supports external clock mode2.

+  * @rmtoll SMCR         SMS           LL_TIM_SetClockSource\n

+  *         SMCR         ECE           LL_TIM_SetClockSource

+  * @param  TIMx Timer instance

+  * @param  ClockSource This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL

+  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1

+  *         @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)

+{

+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);

+}

+

+/**

+  * @brief  Set the encoder interface mode.

+  * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check

+  *       whether or not a timer instance supports the encoder mode.

+  * @rmtoll SMCR         SMS           LL_TIM_SetEncoderMode

+  * @param  TIMx Timer instance

+  * @param  EncoderMode This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI1

+  *         @arg @ref LL_TIM_ENCODERMODE_X2_TI2

+  *         @arg @ref LL_TIM_ENCODERMODE_X4_TI12

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)

+{

+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration

+  * @{

+  */

+/**

+  * @brief  Set the trigger output (TRGO) used for timer synchronization .

+  * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check

+  *       whether or not a timer instance can operate as a master timer.

+  * @rmtoll CR2          MMS           LL_TIM_SetTriggerOutput

+  * @param  TIMx Timer instance

+  * @param  TimerSynchronization This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_TRGO_RESET

+  *         @arg @ref LL_TIM_TRGO_ENABLE

+  *         @arg @ref LL_TIM_TRGO_UPDATE

+  *         @arg @ref LL_TIM_TRGO_CC1IF

+  *         @arg @ref LL_TIM_TRGO_OC1REF

+  *         @arg @ref LL_TIM_TRGO_OC2REF

+  *         @arg @ref LL_TIM_TRGO_OC3REF

+  *         @arg @ref LL_TIM_TRGO_OC4REF

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)

+{

+  MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);

+}

+

+/**

+  * @brief  Set the trigger output 2 (TRGO2) used for ADC synchronization .

+  * @note Macro IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check

+  *       whether or not a timer instance can be used for ADC synchronization.

+  * @rmtoll CR2          MMS2          LL_TIM_SetTriggerOutput2

+  * @param  TIMx Timer Instance

+  * @param  ADCSynchronization This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_TRGO2_RESET

+  *         @arg @ref LL_TIM_TRGO2_ENABLE

+  *         @arg @ref LL_TIM_TRGO2_UPDATE

+  *         @arg @ref LL_TIM_TRGO2_CC1F

+  *         @arg @ref LL_TIM_TRGO2_OC1

+  *         @arg @ref LL_TIM_TRGO2_OC2

+  *         @arg @ref LL_TIM_TRGO2_OC3

+  *         @arg @ref LL_TIM_TRGO2_OC4

+  *         @arg @ref LL_TIM_TRGO2_OC5

+  *         @arg @ref LL_TIM_TRGO2_OC6

+  *         @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING

+  *         @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING

+  *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING

+  *         @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING

+  *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING

+  *         @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)

+{

+  MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);

+}

+

+/**

+  * @brief  Set the synchronization mode of a slave timer.

+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not

+  *       a timer instance can operate as a slave timer.

+  * @rmtoll SMCR         SMS           LL_TIM_SetSlaveMode

+  * @param  TIMx Timer instance

+  * @param  SlaveMode This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_SLAVEMODE_DISABLED

+  *         @arg @ref LL_TIM_SLAVEMODE_RESET

+  *         @arg @ref LL_TIM_SLAVEMODE_GATED

+  *         @arg @ref LL_TIM_SLAVEMODE_TRIGGER

+  *         @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)

+{

+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);

+}

+

+/**

+  * @brief  Set the selects the trigger input to be used to synchronize the counter.

+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not

+  *       a timer instance can operate as a slave timer.

+  * @rmtoll SMCR         TS            LL_TIM_SetTriggerInput

+  * @param  TIMx Timer instance

+  * @param  TriggerInput This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_TS_ITR0

+  *         @arg @ref LL_TIM_TS_ITR1

+  *         @arg @ref LL_TIM_TS_ITR2

+  *         @arg @ref LL_TIM_TS_ITR3

+  *         @arg @ref LL_TIM_TS_TI1F_ED

+  *         @arg @ref LL_TIM_TS_TI1FP1

+  *         @arg @ref LL_TIM_TS_TI2FP2

+  *         @arg @ref LL_TIM_TS_ETRF

+  *         @arg @ref LL_TIM_TS_ITR4

+  *         @arg @ref LL_TIM_TS_ITR5

+  *         @arg @ref LL_TIM_TS_ITR6

+  *         @arg @ref LL_TIM_TS_ITR7

+  *         @arg @ref LL_TIM_TS_ITR8 (*)

+  *         @arg @ref LL_TIM_TS_ITR9 (*)

+  *         @arg @ref LL_TIM_TS_ITR10 (*)

+  *         @arg @ref LL_TIM_TS_ITR11 (*)

+  *         @arg @ref LL_TIM_TS_ITR12 (*)

+  *         @arg @ref LL_TIM_TS_ITR13 (*)

+  *

+  *      (*)  Value not defined in all devices.

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)

+{

+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);

+}

+

+/**

+  * @brief  Enable the Master/Slave mode.

+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not

+  *       a timer instance can operate as a slave timer.

+  * @rmtoll SMCR         MSM           LL_TIM_EnableMasterSlaveMode

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);

+}

+

+/**

+  * @brief  Disable the Master/Slave mode.

+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not

+  *       a timer instance can operate as a slave timer.

+  * @rmtoll SMCR         MSM           LL_TIM_DisableMasterSlaveMode

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)

+{

+  CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);

+}

+

+/**

+  * @brief Indicates whether the Master/Slave mode is enabled.

+  * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not

+  * a timer instance can operate as a slave timer.

+  * @rmtoll SMCR         MSM           LL_TIM_IsEnabledMasterSlaveMode

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Configure the external trigger (ETR) input.

+  * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not

+  *       a timer instance provides an external trigger input.

+  * @rmtoll SMCR         ETP           LL_TIM_ConfigETR\n

+  *         SMCR         ETPS          LL_TIM_ConfigETR\n

+  *         SMCR         ETF           LL_TIM_ConfigETR

+  * @param  TIMx Timer instance

+  * @param  ETRPolarity This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED

+  *         @arg @ref LL_TIM_ETR_POLARITY_INVERTED

+  * @param  ETRPrescaler This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV1

+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV2

+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV4

+  *         @arg @ref LL_TIM_ETR_PRESCALER_DIV8

+  * @param  ETRFilter This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1

+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2

+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4

+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8

+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6

+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8

+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6

+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8

+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6

+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8

+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5

+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6

+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8

+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5

+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6

+  *         @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,

+                                      uint32_t ETRFilter)

+{

+  MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);

+}

+

+/**

+  * @brief  Select the external trigger (ETR) input source.

+  * @note Macro IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or

+  *       not a timer instance supports ETR source selection.

+  * @rmtoll AF1          ETRSEL        LL_TIM_SetETRSource

+  * @param  TIMx Timer instance

+  * @param  ETRSource This parameter can be one of the following values:

+  *      For TIM1, the parameter is one of the following values:

+  *         @arg LL_TIM_TIM1_ETRSOURCE_GPIO:               TIM1_ETR is connected to GPIO

+  *         @arg LL_TIM_TIM1_ETRSOURCE_COMP1:              TIM1_ETR is connected to COMP1 output

+  *         @arg LL_TIM_TIM1_ETRSOURCE_COMP2:              TIM1_ETR is connected to COMP2 output

+  *         @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD1:          TIM1_ETR is connected to ADC1 AWD1

+  *         @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD2:          TIM1_ETR is connected to ADC1 AWD2

+  *         @arg LL_TIM_TIM1_ETRSOURCE_ADC1_AWD3:          TIM1_ETR is connected to ADC1 AWD3

+  *         @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD1:          TIM1_ETR is connected to ADC3 AWD1

+  *         @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD2:          TIM1_ETR is connected to ADC3 AWD2

+  *         @arg LL_TIM_TIM1_ETRSOURCE_ADC3_AWD3:          TIM1_ETR is connected to ADC3 AWD3

+  *

+  *      For TIM2, the parameter is one of the following values:

+  *         @arg LL_TIM_TIM2_ETRSOURCE_GPIO:               TIM2_ETR is connected to GPIO

+  *         @arg LL_TIM_TIM2_ETRSOURCE_COMP1:              TIM2_ETR is connected to COMP1 output

+  *         @arg LL_TIM_TIM2_ETRSOURCE_COMP2:              TIM2_ETR is connected to COMP2 output

+  *         @arg LL_TIM_TIM2_ETRSOURCE_LSE:                TIM2_ETR is connected to LSE

+  *         @arg LL_TIM_TIM2_ETRSOURCE_SAI1_FSA:           TIM2_ETR is connected to SAI1 FS_A

+  *         @arg LL_TIM_TIM2_ETRSOURCE_SAI1_FSB:           TIM2_ETR is connected to SAI1 FS_B

+  *

+  *      For TIM3, the parameter is one of the following values:

+  *         @arg LL_TIM_TIM3_ETRSOURCE_GPIO:               TIM3_ETR is connected to GPIO

+  *         @arg LL_TIM_TIM3_ETRSOURCE_COMP1:              TIM3_ETR is connected to COMP1 output

+  *

+  *      For TIM5, the parameter is one of the following values:

+  *         @arg LL_TIM_TIM5_ETRSOURCE_GPIO:               TIM5_ETR is connected to GPIO

+  *         @arg LL_TIM_TIM5_ETRSOURCE_SAI2_FSA:           TIM5_ETR is connected to SAI2 FS_A (*)

+  *         @arg LL_TIM_TIM5_ETRSOURCE_SAI2_FSB:           TIM5_ETR is connected to SAI2 FS_B (*)

+  *         @arg LL_TIM_TIM5_ETRSOURCE_SAI4_FSA:           TIM5_ETR is connected to SAI2 FS_A (*)

+  *         @arg LL_TIM_TIM5_ETRSOURCE_SAI4_FSB:           TIM5_ETR is connected to SAI2 FS_B (*)

+  *

+  *      For TIM8, the parameter is one of the following values:

+  *         @arg LL_TIM_TIM8_ETRSOURCE_GPIO:               TIM8_ETR is connected to GPIO

+  *         @arg LL_TIM_TIM8_ETRSOURCE_COMP1:              TIM8_ETR is connected to COMP1 output

+  *         @arg LL_TIM_TIM8_ETRSOURCE_COMP2:              TIM8_ETR is connected to COMP2 output

+  *         @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD1:          TIM8_ETR is connected to ADC2 AWD1

+  *         @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD2:          TIM8_ETR is connected to ADC2 AWD2

+  *         @arg LL_TIM_TIM8_ETRSOURCE_ADC2_AWD3:          TIM8_ETR is connected to ADC2 AWD3

+  *         @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD1:          TIM8_ETR is connected to ADC3 AWD1

+  *         @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD2:          TIM8_ETR is connected to ADC3 AWD2

+  *         @arg LL_TIM_TIM8_ETRSOURCE_ADC3_AWD3:          TIM8_ETR is connected to ADC3 AWD3

+  *

+  *      For TIM23, the parameter is one of the following values: (*)

+  *         @arg LL_TIM_TIM23_ETRSOURCE_GPIO               TIM23_ETR is connected to GPIO

+  *         @arg LL_TIM_TIM23_ETRSOURCE_COMP1              TIM23_ETR is connected to COMP1 output

+  *         @arg LL_TIM_TIM23_ETRSOURCE_COMP2              TIM23_ETR is connected to COMP2 output

+  *

+  *      For TIM24, the parameter is one of the following values: (*)

+  *        @arg LL_TIM_TIM24_ETRSOURCE_GPIO                TIM24_ETR is connected to GPIO

+  *        @arg LL_TIM_TIM24_ETRSOURCE_SAI4_FSA            TIM24_ETR is connected to SAI4 FS_A

+  *        @arg LL_TIM_TIM24_ETRSOURCE_SAI4_FSB            TIM24_ETR is connected to SAI4 FS_B

+  *        @arg LL_TIM_TIM24_ETRSOURCE_SAI1_FSA            TIM24_ETR is connected to SAI1 FS_A

+  *        @arg LL_TIM_TIM24_ETRSOURCE_SAI1_FSB            TIM24_ETR is connected to SAI1 FS_B

+  *

+  *      (*)  Value not defined in all devices.

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource)

+{

+

+  MODIFY_REG(TIMx->AF1, TIMx_AF1_ETRSEL, ETRSource);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EF_Break_Function Break function configuration

+  * @{

+  */

+/**

+  * @brief  Enable the break function.

+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not

+  *       a timer instance provides a break input.

+  * @rmtoll BDTR         BKE           LL_TIM_EnableBRK

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);

+}

+

+/**

+  * @brief  Disable the break function.

+  * @rmtoll BDTR         BKE           LL_TIM_DisableBRK

+  * @param  TIMx Timer instance

+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not

+  *       a timer instance provides a break input.

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)

+{

+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);

+}

+

+/**

+  * @brief  Configure the break input.

+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not

+  *       a timer instance provides a break input.

+  * @rmtoll BDTR         BKP           LL_TIM_ConfigBRK\n

+  *         BDTR         BKF           LL_TIM_ConfigBRK

+  * @param  TIMx Timer instance

+  * @param  BreakPolarity This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_BREAK_POLARITY_LOW

+  *         @arg @ref LL_TIM_BREAK_POLARITY_HIGH

+  * @param  BreakFilter This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1

+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2

+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4

+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8

+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6

+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8

+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6

+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8

+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6

+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8

+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5

+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6

+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8

+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5

+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6

+  *         @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity,

+                                      uint32_t BreakFilter)

+{

+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);

+}

+

+/**

+  * @brief  Enable the break 2 function.

+  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not

+  *       a timer instance provides a second break input.

+  * @rmtoll BDTR         BK2E          LL_TIM_EnableBRK2

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);

+}

+

+/**

+  * @brief  Disable the break  2 function.

+  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not

+  *       a timer instance provides a second break input.

+  * @rmtoll BDTR         BK2E          LL_TIM_DisableBRK2

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)

+{

+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);

+}

+

+/**

+  * @brief  Configure the break 2 input.

+  * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not

+  *       a timer instance provides a second break input.

+  * @rmtoll BDTR         BK2P          LL_TIM_ConfigBRK2\n

+  *         BDTR         BK2F          LL_TIM_ConfigBRK2

+  * @param  TIMx Timer instance

+  * @param  Break2Polarity This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_BREAK2_POLARITY_LOW

+  *         @arg @ref LL_TIM_BREAK2_POLARITY_HIGH

+  * @param  Break2Filter This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1

+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2

+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4

+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8

+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6

+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8

+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6

+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8

+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6

+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8

+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5

+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6

+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8

+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5

+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6

+  *         @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)

+{

+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);

+}

+

+/**

+  * @brief  Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.

+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not

+  *       a timer instance provides a break input.

+  * @rmtoll BDTR         OSSI          LL_TIM_SetOffStates\n

+  *         BDTR         OSSR          LL_TIM_SetOffStates

+  * @param  TIMx Timer instance

+  * @param  OffStateIdle This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_OSSI_DISABLE

+  *         @arg @ref LL_TIM_OSSI_ENABLE

+  * @param  OffStateRun This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_OSSR_DISABLE

+  *         @arg @ref LL_TIM_OSSR_ENABLE

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)

+{

+  MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);

+}

+

+/**

+  * @brief  Enable automatic output (MOE can be set by software or automatically when a break input is active).

+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not

+  *       a timer instance provides a break input.

+  * @rmtoll BDTR         AOE           LL_TIM_EnableAutomaticOutput

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);

+}

+

+/**

+  * @brief  Disable automatic output (MOE can be set only by software).

+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not

+  *       a timer instance provides a break input.

+  * @rmtoll BDTR         AOE           LL_TIM_DisableAutomaticOutput

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)

+{

+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);

+}

+

+/**

+  * @brief  Indicate whether automatic output is enabled.

+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not

+  *       a timer instance provides a break input.

+  * @rmtoll BDTR         AOE           LL_TIM_IsEnabledAutomaticOutput

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable the outputs (set the MOE bit in TIMx_BDTR register).

+  * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by

+  *       software and is reset in case of break or break2 event

+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not

+  *       a timer instance provides a break input.

+  * @rmtoll BDTR         MOE           LL_TIM_EnableAllOutputs

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);

+}

+

+/**

+  * @brief  Disable the outputs (reset the MOE bit in TIMx_BDTR register).

+  * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by

+  *       software and is reset in case of break or break2 event.

+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not

+  *       a timer instance provides a break input.

+  * @rmtoll BDTR         MOE           LL_TIM_DisableAllOutputs

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)

+{

+  CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);

+}

+

+/**

+  * @brief  Indicates whether outputs are enabled.

+  * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not

+  *       a timer instance provides a break input.

+  * @rmtoll BDTR         MOE           LL_TIM_IsEnabledAllOutputs

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL);

+}

+

+#if defined(TIM_BREAK_INPUT_SUPPORT)

+/**

+  * @brief  Enable the signals connected to the designated timer break input.

+  * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether

+  *       or not a timer instance allows for break input selection.

+  * @rmtoll AF1          BKINE         LL_TIM_EnableBreakInputSource\n

+  *         AF1          BKCMP1E       LL_TIM_EnableBreakInputSource\n

+  *         AF1          BKCMP2E       LL_TIM_EnableBreakInputSource\n

+  *         AF1          BKDF1BK0E     LL_TIM_EnableBreakInputSource\n

+  *         AF2          BK2INE        LL_TIM_EnableBreakInputSource\n

+  *         AF2          BK2CMP1E      LL_TIM_EnableBreakInputSource\n

+  *         AF2          BK2CMP2E      LL_TIM_EnableBreakInputSource\n

+  *         AF2          BK2DF1BK1E    LL_TIM_EnableBreakInputSource

+  * @param  TIMx Timer instance

+  * @param  BreakInput This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN

+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2

+  * @param  Source This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN

+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1

+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2

+  *         @arg @ref LL_TIM_BKIN_SOURCE_DF1BK

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)

+{

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));

+  SET_BIT(*pReg, Source);

+}

+

+/**

+  * @brief  Disable the signals connected to the designated timer break input.

+  * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether

+  *       or not a timer instance allows for break input selection.

+  * @rmtoll AF1          BKINE         LL_TIM_DisableBreakInputSource\n

+  *         AF1          BKCMP1E       LL_TIM_DisableBreakInputSource\n

+  *         AF1          BKCMP2E       LL_TIM_DisableBreakInputSource\n

+  *         AF1          BKDF1BK0E     LL_TIM_DisableBreakInputSource\n

+  *         AF2          BK2INE        LL_TIM_DisableBreakInputSource\n

+  *         AF2          BK2CMP1E      LL_TIM_DisableBreakInputSource\n

+  *         AF2          BK2CMP2E      LL_TIM_DisableBreakInputSource\n

+  *         AF2          BK2DF1BK1E    LL_TIM_DisableBreakInputSource

+  * @param  TIMx Timer instance

+  * @param  BreakInput This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN

+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2

+  * @param  Source This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN

+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1

+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2

+  *         @arg @ref LL_TIM_BKIN_SOURCE_DF1BK

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)

+{

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));

+  CLEAR_BIT(*pReg, Source);

+}

+

+/**

+  * @brief  Set the polarity of the break signal for the timer break input.

+  * @note Macro IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether

+  *       or not a timer instance allows for break input selection.

+  * @rmtoll AF1          BKINP         LL_TIM_SetBreakInputSourcePolarity\n

+  *         AF1          BKCMP1P       LL_TIM_SetBreakInputSourcePolarity\n

+  *         AF1          BKCMP2P       LL_TIM_SetBreakInputSourcePolarity\n

+  *         AF2          BK2INP        LL_TIM_SetBreakInputSourcePolarity\n

+  *         AF2          BK2CMP1P      LL_TIM_SetBreakInputSourcePolarity\n

+  *         AF2          BK2CMP2P      LL_TIM_SetBreakInputSourcePolarity

+  * @param  TIMx Timer instance

+  * @param  BreakInput This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN

+  *         @arg @ref LL_TIM_BREAK_INPUT_BKIN2

+  * @param  Source This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKIN

+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1

+  *         @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2

+  * @param  Polarity This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_BKIN_POLARITY_LOW

+  *         @arg @ref LL_TIM_BKIN_POLARITY_HIGH

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,

+                                                        uint32_t Polarity)

+{

+  register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));

+  MODIFY_REG(*pReg, (TIMx_AF1_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE));

+}

+#endif /* TIM_BREAK_INPUT_SUPPORT */

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration

+  * @{

+  */

+/**

+  * @brief  Configures the timer DMA burst feature.

+  * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or

+  *       not a timer instance supports the DMA burst mode.

+  * @rmtoll DCR          DBL           LL_TIM_ConfigDMABurst\n

+  *         DCR          DBA           LL_TIM_ConfigDMABurst

+  * @param  TIMx Timer instance

+  * @param  DMABurstBaseAddress This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR1

+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CR2

+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR

+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_DIER

+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_SR

+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_EGR

+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1

+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2

+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCER

+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CNT

+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_PSC

+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_ARR

+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_RCR

+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1

+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2

+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3

+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4

+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR

+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 

+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5  

+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6  

+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF1  

+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_AF2  

+  *         @arg @ref LL_TIM_DMABURST_BASEADDR_TISEL

+  *         

+  * @param  DMABurstLength This parameter can be one of the following values:

+  *         @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER

+  *         @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS

+  *         @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS

+  *         @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS

+  *         @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS

+  *         @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS

+  *         @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS

+  *         @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS

+  *         @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS

+  *         @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS

+  *         @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS

+  *         @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS

+  *         @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS

+  *         @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS

+  *         @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS

+  *         @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS

+  *         @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS

+  *         @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)

+{

+  MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping

+  * @{

+  */

+/**

+  * @brief  Remap TIM inputs (input channel, internal/external triggers).

+  * @note Macro IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not

+  *       a some timer inputs can be remapped.

+  *         TIM1: one of the following values:

+  *            @arg LL_TIM_TIM1_TI1_RMP_GPIO:                TIM1 TI1 is connected to GPIO

+  *            @arg LL_TIM_TIM1_TI1_RMP_COMP1:               TIM1 TI1 is connected to COMP1 output

+  *

+  *         TIM2: one of the following values:

+  *            @arg LL_TIM_TIM2_TI4_RMP_GPIO:                TIM2 TI4 is connected to GPIO

+  *            @arg LL_TIM_TIM2_TI4_RMP_COMP1:               TIM2 TI4 is connected to COMP1 output

+  *            @arg LL_TIM_TIM2_TI4_RMP_COMP2:               TIM2 TI4 is connected to COMP2 output

+  *            @arg LL_TIM_TIM2_TI4_RMP_COMP1_COMP2:         TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output

+  *

+  *         TIM3: one of the following values:

+  *            @arg LL_TIM_TIM3_TI1_RMP_GPIO:                TIM3 TI1 is connected to GPIO

+  *            @arg LL_TIM_TIM3_TI1_RMP_COMP1:               TIM3 TI1 is connected to COMP1 output

+  *            @arg LL_TIM_TIM3_TI1_RMP_COMP2:               TIM3 TI1 is connected to COMP2 output

+  *            @arg LL_TIM_TIM3_TI1_RMP_COMP1_COMP2:         TIM3 TI1 is connected to logical OR between COMP1 and COMP2 output

+  *

+  *         TIM5: one of the following values:

+  *            @arg LL_TIM_TIM5_TI1_RMP_GPIO:                TIM5 TI1 is connected to GPIO

+  *            @arg LL_TIM_TIM5_TI1_RMP_CAN_TMP:             TIM5 TI1 is connected to CAN TMP

+  *            @arg LL_TIM_TIM5_TI1_RMP_CAN_RTP:             TIM5 TI1 is connected to CAN RTP

+  *

+  *         TIM8: one of the following values:

+  *            @arg LL_TIM_TIM8_TI1_RMP_GPIO:               TIM8 TI1 is connected to GPIO

+  *            @arg LL_TIM_TIM8_TI1_RMP_COMP2:              TIM8 TI1 is connected to COMP2 output

+  *

+  *         TIM12: one of the following values: (*)

+  *            @arg LL_TIM_TIM12_TI1_RMP_GPIO:              TIM12 TI1 is connected to GPIO

+  *            @arg LL_TIM_TIM12_TI1_RMP_SPDIF_FS:          TIM12 TI1 is connected to SPDIF FS

+  *

+  *         TIM15: one of the following values:

+  *            @arg LL_TIM_TIM15_TI1_RMP_GPIO:              TIM15 TI1 is connected to GPIO

+  *            @arg LL_TIM_TIM15_TI1_RMP_TIM2:              TIM15 TI1 is connected to TIM2 CH1

+  *            @arg LL_TIM_TIM15_TI1_RMP_TIM3:              TIM15 TI1 is connected to TIM3 CH1

+  *            @arg LL_TIM_TIM15_TI1_RMP_TIM4:              TIM15 TI1 is connected to TIM4 CH1

+  *            @arg LL_TIM_TIM15_TI1_RMP_LSE:               TIM15 TI1 is connected to LSE

+  *            @arg LL_TIM_TIM15_TI1_RMP_CSI:               TIM15 TI1 is connected to CSI

+  *            @arg LL_TIM_TIM15_TI1_RMP_MCO2:              TIM15 TI1 is connected to MCO2

+  *            @arg LL_TIM_TIM15_TI2_RMP_GPIO:              TIM15 TI2 is connected to GPIO

+  *            @arg LL_TIM_TIM15_TI2_RMP_TIM2:              TIM15 TI2 is connected to TIM2 CH2

+  *            @arg LL_TIM_TIM15_TI2_RMP_TIM3:              TIM15 TI2 is connected to TIM3 CH2

+  *            @arg LL_TIM_TIM15_TI2_RMP_TIM4:              TIM15 TI2 is connected to TIM4 CH2

+  *

+  *         TIM16: one of the following values:

+  *            @arg LL_TIM_TIM16_TI1_RMP_GPIO:              TIM16 TI1 is connected to GPIO

+  *            @arg LL_TIM_TIM16_TI1_RMP_LSI:               TIM16 TI1 is connected to LSI

+  *            @arg LL_TIM_TIM16_TI1_RMP_LSE:               TIM16 TI1 is connected to LSE

+  *            @arg LL_TIM_TIM16_TI1_RMP_RTC:               TIM16 TI1 is connected to RTC wakeup interrupt

+  *

+  *         TIM17: one of the following values:

+  *            @arg LL_TIM_TIM17_TI1_RMP_GPIO:              TIM17 TI1 is connected to GPIO

+  *            @arg LL_TIM_TIM17_TI1_RMP_SPDIF_FS:          TIM17 TI1 is connected to SPDIF FS (*)

+  *            @arg LL_TIM_TIM17_TI1_RMP_HSE_1MHZ:          TIM17 TI1 is connected to HSE 1MHz

+  *            @arg LL_TIM_TIM17_TI1_RMP_MCO1:              TIM17 TI1 is connected to MCO1

+  *

+  *         TIM23: one of the following values: (*)

+  *            @arg LL_TIM_TIM23_TI4_RMP_GPIO               TIM23_TI4 is connected to GPIO

+  *            @arg LL_TIM_TIM23_TI4_RMP_COMP1              TIM23_TI4 is connected to COMP1 output

+  *            @arg LL_TIM_TIM23_TI4_RMP_COMP2              TIM23_TI4 is connected to COMP2 output

+  *            @arg LL_TIM_TIM23_TI4_RMP_COMP1_COMP2        TIM23_TI4 is connected to COMP2 output

+  *

+  *         TIM24: one of the following values: (*)

+  *            @arg LL_TIM_TIM24_TI1_RMP_GPIO               TIM24_TI1 is connected to GPIO

+  *            @arg LL_TIM_TIM24_TI1_RMP_CAN_TMP            TIM24_TI1 is connected to CAN_TMP

+  *            @arg LL_TIM_TIM24_TI1_RMP_CAN_RTP            TIM24_TI1 is connected to CAN_RTP

+  *            @arg LL_TIM_TIM24_TI1_RMP_CAN_SOC            TIM24_TI1 is connected to CAN_SOC

+  *

+  *         (*)  Value not defined in all devices. \n

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)

+{

+  MODIFY_REG(TIMx->TISEL, (TIM_TISEL_TI1SEL | TIM_TISEL_TI2SEL | TIM_TISEL_TI3SEL | TIM_TISEL_TI4SEL), Remap);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management

+  * @{

+  */

+/**

+  * @brief  Clear the update interrupt flag (UIF).

+  * @rmtoll SR           UIF           LL_TIM_ClearFlag_UPDATE

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)

+{

+  WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));

+}

+

+/**

+  * @brief  Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).

+  * @rmtoll SR           UIF           LL_TIM_IsActiveFlag_UPDATE

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the Capture/Compare 1 interrupt flag (CC1F).

+  * @rmtoll SR           CC1IF         LL_TIM_ClearFlag_CC1

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)

+{

+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));

+}

+

+/**

+  * @brief  Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).

+  * @rmtoll SR           CC1IF         LL_TIM_IsActiveFlag_CC1

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the Capture/Compare 2 interrupt flag (CC2F).

+  * @rmtoll SR           CC2IF         LL_TIM_ClearFlag_CC2

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)

+{

+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));

+}

+

+/**

+  * @brief  Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).

+  * @rmtoll SR           CC2IF         LL_TIM_IsActiveFlag_CC2

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the Capture/Compare 3 interrupt flag (CC3F).

+  * @rmtoll SR           CC3IF         LL_TIM_ClearFlag_CC3

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)

+{

+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));

+}

+

+/**

+  * @brief  Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).

+  * @rmtoll SR           CC3IF         LL_TIM_IsActiveFlag_CC3

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the Capture/Compare 4 interrupt flag (CC4F).

+  * @rmtoll SR           CC4IF         LL_TIM_ClearFlag_CC4

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)

+{

+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));

+}

+

+/**

+  * @brief  Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).

+  * @rmtoll SR           CC4IF         LL_TIM_IsActiveFlag_CC4

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the Capture/Compare 5 interrupt flag (CC5F).

+  * @rmtoll SR           CC5IF         LL_TIM_ClearFlag_CC5

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)

+{

+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));

+}

+

+/**

+  * @brief  Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).

+  * @rmtoll SR           CC5IF         LL_TIM_IsActiveFlag_CC5

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the Capture/Compare 6 interrupt flag (CC6F).

+  * @rmtoll SR           CC6IF         LL_TIM_ClearFlag_CC6

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)

+{

+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));

+}

+

+/**

+  * @brief  Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).

+  * @rmtoll SR           CC6IF         LL_TIM_IsActiveFlag_CC6

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the commutation interrupt flag (COMIF).

+  * @rmtoll SR           COMIF         LL_TIM_ClearFlag_COM

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)

+{

+  WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));

+}

+

+/**

+  * @brief  Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).

+  * @rmtoll SR           COMIF         LL_TIM_IsActiveFlag_COM

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the trigger interrupt flag (TIF).

+  * @rmtoll SR           TIF           LL_TIM_ClearFlag_TRIG

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)

+{

+  WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));

+}

+

+/**

+  * @brief  Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).

+  * @rmtoll SR           TIF           LL_TIM_IsActiveFlag_TRIG

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the break interrupt flag (BIF).

+  * @rmtoll SR           BIF           LL_TIM_ClearFlag_BRK

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)

+{

+  WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));

+}

+

+/**

+  * @brief  Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).

+  * @rmtoll SR           BIF           LL_TIM_IsActiveFlag_BRK

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the break 2 interrupt flag (B2IF).

+  * @rmtoll SR           B2IF          LL_TIM_ClearFlag_BRK2

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)

+{

+  WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));

+}

+

+/**

+  * @brief  Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).

+  * @rmtoll SR           B2IF          LL_TIM_IsActiveFlag_BRK2

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).

+  * @rmtoll SR           CC1OF         LL_TIM_ClearFlag_CC1OVR

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)

+{

+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));

+}

+

+/**

+  * @brief  Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).

+  * @rmtoll SR           CC1OF         LL_TIM_IsActiveFlag_CC1OVR

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).

+  * @rmtoll SR           CC2OF         LL_TIM_ClearFlag_CC2OVR

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)

+{

+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));

+}

+

+/**

+  * @brief  Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).

+  * @rmtoll SR           CC2OF         LL_TIM_IsActiveFlag_CC2OVR

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).

+  * @rmtoll SR           CC3OF         LL_TIM_ClearFlag_CC3OVR

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)

+{

+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));

+}

+

+/**

+  * @brief  Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).

+  * @rmtoll SR           CC3OF         LL_TIM_IsActiveFlag_CC3OVR

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).

+  * @rmtoll SR           CC4OF         LL_TIM_ClearFlag_CC4OVR

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)

+{

+  WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));

+}

+

+/**

+  * @brief  Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).

+  * @rmtoll SR           CC4OF         LL_TIM_IsActiveFlag_CC4OVR

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear the system break interrupt flag (SBIF).

+  * @rmtoll SR           SBIF          LL_TIM_ClearFlag_SYSBRK

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)

+{

+  WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));

+}

+

+/**

+  * @brief  Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).

+  * @rmtoll SR           SBIF          LL_TIM_IsActiveFlag_SYSBRK

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EF_IT_Management IT-Management

+  * @{

+  */

+/**

+  * @brief  Enable update interrupt (UIE).

+  * @rmtoll DIER         UIE           LL_TIM_EnableIT_UPDATE

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->DIER, TIM_DIER_UIE);

+}

+

+/**

+  * @brief  Disable update interrupt (UIE).

+  * @rmtoll DIER         UIE           LL_TIM_DisableIT_UPDATE

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)

+{

+  CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);

+}

+

+/**

+  * @brief  Indicates whether the update interrupt (UIE) is enabled.

+  * @rmtoll DIER         UIE           LL_TIM_IsEnabledIT_UPDATE

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable capture/compare 1 interrupt (CC1IE).

+  * @rmtoll DIER         CC1IE         LL_TIM_EnableIT_CC1

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);

+}

+

+/**

+  * @brief  Disable capture/compare 1  interrupt (CC1IE).

+  * @rmtoll DIER         CC1IE         LL_TIM_DisableIT_CC1

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)

+{

+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);

+}

+

+/**

+  * @brief  Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.

+  * @rmtoll DIER         CC1IE         LL_TIM_IsEnabledIT_CC1

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable capture/compare 2 interrupt (CC2IE).

+  * @rmtoll DIER         CC2IE         LL_TIM_EnableIT_CC2

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);

+}

+

+/**

+  * @brief  Disable capture/compare 2  interrupt (CC2IE).

+  * @rmtoll DIER         CC2IE         LL_TIM_DisableIT_CC2

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)

+{

+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);

+}

+

+/**

+  * @brief  Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.

+  * @rmtoll DIER         CC2IE         LL_TIM_IsEnabledIT_CC2

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable capture/compare 3 interrupt (CC3IE).

+  * @rmtoll DIER         CC3IE         LL_TIM_EnableIT_CC3

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);

+}

+

+/**

+  * @brief  Disable capture/compare 3  interrupt (CC3IE).

+  * @rmtoll DIER         CC3IE         LL_TIM_DisableIT_CC3

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)

+{

+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);

+}

+

+/**

+  * @brief  Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.

+  * @rmtoll DIER         CC3IE         LL_TIM_IsEnabledIT_CC3

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable capture/compare 4 interrupt (CC4IE).

+  * @rmtoll DIER         CC4IE         LL_TIM_EnableIT_CC4

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);

+}

+

+/**

+  * @brief  Disable capture/compare 4  interrupt (CC4IE).

+  * @rmtoll DIER         CC4IE         LL_TIM_DisableIT_CC4

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)

+{

+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);

+}

+

+/**

+  * @brief  Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.

+  * @rmtoll DIER         CC4IE         LL_TIM_IsEnabledIT_CC4

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable commutation interrupt (COMIE).

+  * @rmtoll DIER         COMIE         LL_TIM_EnableIT_COM

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->DIER, TIM_DIER_COMIE);

+}

+

+/**

+  * @brief  Disable commutation interrupt (COMIE).

+  * @rmtoll DIER         COMIE         LL_TIM_DisableIT_COM

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)

+{

+  CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);

+}

+

+/**

+  * @brief  Indicates whether the commutation interrupt (COMIE) is enabled.

+  * @rmtoll DIER         COMIE         LL_TIM_IsEnabledIT_COM

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable trigger interrupt (TIE).

+  * @rmtoll DIER         TIE           LL_TIM_EnableIT_TRIG

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->DIER, TIM_DIER_TIE);

+}

+

+/**

+  * @brief  Disable trigger interrupt (TIE).

+  * @rmtoll DIER         TIE           LL_TIM_DisableIT_TRIG

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)

+{

+  CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);

+}

+

+/**

+  * @brief  Indicates whether the trigger interrupt (TIE) is enabled.

+  * @rmtoll DIER         TIE           LL_TIM_IsEnabledIT_TRIG

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable break interrupt (BIE).

+  * @rmtoll DIER         BIE           LL_TIM_EnableIT_BRK

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->DIER, TIM_DIER_BIE);

+}

+

+/**

+  * @brief  Disable break interrupt (BIE).

+  * @rmtoll DIER         BIE           LL_TIM_DisableIT_BRK

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)

+{

+  CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);

+}

+

+/**

+  * @brief  Indicates whether the break interrupt (BIE) is enabled.

+  * @rmtoll DIER         BIE           LL_TIM_IsEnabledIT_BRK

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EF_DMA_Management DMA-Management

+  * @{

+  */

+/**

+  * @brief  Enable update DMA request (UDE).

+  * @rmtoll DIER         UDE           LL_TIM_EnableDMAReq_UPDATE

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->DIER, TIM_DIER_UDE);

+}

+

+/**

+  * @brief  Disable update DMA request (UDE).

+  * @rmtoll DIER         UDE           LL_TIM_DisableDMAReq_UPDATE

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)

+{

+  CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);

+}

+

+/**

+  * @brief  Indicates whether the update DMA request  (UDE) is enabled.

+  * @rmtoll DIER         UDE           LL_TIM_IsEnabledDMAReq_UPDATE

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable capture/compare 1 DMA request (CC1DE).

+  * @rmtoll DIER         CC1DE         LL_TIM_EnableDMAReq_CC1

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);

+}

+

+/**

+  * @brief  Disable capture/compare 1  DMA request (CC1DE).

+  * @rmtoll DIER         CC1DE         LL_TIM_DisableDMAReq_CC1

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)

+{

+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);

+}

+

+/**

+  * @brief  Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.

+  * @rmtoll DIER         CC1DE         LL_TIM_IsEnabledDMAReq_CC1

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable capture/compare 2 DMA request (CC2DE).

+  * @rmtoll DIER         CC2DE         LL_TIM_EnableDMAReq_CC2

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);

+}

+

+/**

+  * @brief  Disable capture/compare 2  DMA request (CC2DE).

+  * @rmtoll DIER         CC2DE         LL_TIM_DisableDMAReq_CC2

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)

+{

+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);

+}

+

+/**

+  * @brief  Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.

+  * @rmtoll DIER         CC2DE         LL_TIM_IsEnabledDMAReq_CC2

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable capture/compare 3 DMA request (CC3DE).

+  * @rmtoll DIER         CC3DE         LL_TIM_EnableDMAReq_CC3

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);

+}

+

+/**

+  * @brief  Disable capture/compare 3  DMA request (CC3DE).

+  * @rmtoll DIER         CC3DE         LL_TIM_DisableDMAReq_CC3

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)

+{

+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);

+}

+

+/**

+  * @brief  Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.

+  * @rmtoll DIER         CC3DE         LL_TIM_IsEnabledDMAReq_CC3

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable capture/compare 4 DMA request (CC4DE).

+  * @rmtoll DIER         CC4DE         LL_TIM_EnableDMAReq_CC4

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);

+}

+

+/**

+  * @brief  Disable capture/compare 4  DMA request (CC4DE).

+  * @rmtoll DIER         CC4DE         LL_TIM_DisableDMAReq_CC4

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)

+{

+  CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);

+}

+

+/**

+  * @brief  Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.

+  * @rmtoll DIER         CC4DE         LL_TIM_IsEnabledDMAReq_CC4

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable commutation DMA request (COMDE).

+  * @rmtoll DIER         COMDE         LL_TIM_EnableDMAReq_COM

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->DIER, TIM_DIER_COMDE);

+}

+

+/**

+  * @brief  Disable commutation DMA request (COMDE).

+  * @rmtoll DIER         COMDE         LL_TIM_DisableDMAReq_COM

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)

+{

+  CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);

+}

+

+/**

+  * @brief  Indicates whether the commutation DMA request (COMDE) is enabled.

+  * @rmtoll DIER         COMDE         LL_TIM_IsEnabledDMAReq_COM

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable trigger interrupt (TDE).

+  * @rmtoll DIER         TDE           LL_TIM_EnableDMAReq_TRIG

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->DIER, TIM_DIER_TDE);

+}

+

+/**

+  * @brief  Disable trigger interrupt (TDE).

+  * @rmtoll DIER         TDE           LL_TIM_DisableDMAReq_TRIG

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)

+{

+  CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);

+}

+

+/**

+  * @brief  Indicates whether the trigger interrupt (TDE) is enabled.

+  * @rmtoll DIER         TDE           LL_TIM_IsEnabledDMAReq_TRIG

+  * @param  TIMx Timer instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)

+{

+  return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management

+  * @{

+  */

+/**

+  * @brief  Generate an update event.

+  * @rmtoll EGR          UG            LL_TIM_GenerateEvent_UPDATE

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->EGR, TIM_EGR_UG);

+}

+

+/**

+  * @brief  Generate Capture/Compare 1 event.

+  * @rmtoll EGR          CC1G          LL_TIM_GenerateEvent_CC1

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->EGR, TIM_EGR_CC1G);

+}

+

+/**

+  * @brief  Generate Capture/Compare 2 event.

+  * @rmtoll EGR          CC2G          LL_TIM_GenerateEvent_CC2

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->EGR, TIM_EGR_CC2G);

+}

+

+/**

+  * @brief  Generate Capture/Compare 3 event.

+  * @rmtoll EGR          CC3G          LL_TIM_GenerateEvent_CC3

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->EGR, TIM_EGR_CC3G);

+}

+

+/**

+  * @brief  Generate Capture/Compare 4 event.

+  * @rmtoll EGR          CC4G          LL_TIM_GenerateEvent_CC4

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->EGR, TIM_EGR_CC4G);

+}

+

+/**

+  * @brief  Generate commutation event.

+  * @rmtoll EGR          COMG          LL_TIM_GenerateEvent_COM

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->EGR, TIM_EGR_COMG);

+}

+

+/**

+  * @brief  Generate trigger event.

+  * @rmtoll EGR          TG            LL_TIM_GenerateEvent_TRIG

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->EGR, TIM_EGR_TG);

+}

+

+/**

+  * @brief  Generate break event.

+  * @rmtoll EGR          BG            LL_TIM_GenerateEvent_BRK

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->EGR, TIM_EGR_BG);

+}

+

+/**

+  * @brief  Generate break 2 event.

+  * @rmtoll EGR          B2G           LL_TIM_GenerateEvent_BRK2

+  * @param  TIMx Timer instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)

+{

+  SET_BIT(TIMx->EGR, TIM_EGR_B2G);

+}

+

+/**

+  * @}

+  */

+

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions

+  * @{

+  */

+

+ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);

+void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);

+ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);

+void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);

+ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);

+void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);

+ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);

+void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);

+ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);

+void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);

+ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);

+void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);

+ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM12 || TIM13 ||TIM14 || TIM15 || TIM16 || TIM17 */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* __STM32H7xx_LL_TIM_H */

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_usart.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_usart.h
new file mode 100644
index 0000000000..639410185c
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_usart.h
@@ -0,0 +1,4385 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_usart.h

+  * @author  MCD Application Team

+  * @brief   Header file of USART LL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_LL_USART_H

+#define STM32H7xx_LL_USART_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+#if defined (USART1) || defined (USART2) || defined (USART3) || defined (USART6) || defined (UART4) || defined (UART5) || defined (UART7) || defined (UART8) || defined (UART9) || defined (USART10)

+

+/** @defgroup USART_LL USART

+  * @{

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/** @defgroup USART_LL_Private_Variables USART Private Variables

+  * @{

+  */

+/* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */

+static const uint32_t USART_PRESCALER_TAB[] =

+{

+  1UL,

+  2UL,

+  4UL,

+  6UL,

+  8UL,

+  10UL,

+  12UL,

+  16UL,

+  32UL,

+  64UL,

+  128UL,

+  256UL

+};

+/**

+  * @}

+  */

+

+/* Private constants ---------------------------------------------------------*/

+/* Private macros ------------------------------------------------------------*/

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup USART_LL_Private_Macros USART Private Macros

+  * @{

+  */

+/**

+  * @}

+  */

+#endif /*USE_FULL_LL_DRIVER*/

+

+/* Exported types ------------------------------------------------------------*/

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup USART_LL_ES_INIT USART Exported Init structures

+  * @{

+  */

+

+/**

+  * @brief LL USART Init Structure definition

+  */

+typedef struct

+{

+  uint32_t PrescalerValue;            /*!< Specifies the Prescaler to compute the communication baud rate.

+                                           This parameter can be a value of @ref USART_LL_EC_PRESCALER.

+

+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetPrescaler().*/

+

+  uint32_t BaudRate;                  /*!< This field defines expected Usart communication baud rate.

+

+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/

+

+  uint32_t DataWidth;                 /*!< Specifies the number of data bits transmitted or received in a frame.

+                                           This parameter can be a value of @ref USART_LL_EC_DATAWIDTH.

+

+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/

+

+  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.

+                                           This parameter can be a value of @ref USART_LL_EC_STOPBITS.

+

+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/

+

+  uint32_t Parity;                    /*!< Specifies the parity mode.

+                                           This parameter can be a value of @ref USART_LL_EC_PARITY.

+

+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/

+

+  uint32_t TransferDirection;         /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled.

+                                           This parameter can be a value of @ref USART_LL_EC_DIRECTION.

+

+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/

+

+  uint32_t HardwareFlowControl;       /*!< Specifies whether the hardware flow control mode is enabled or disabled.

+                                           This parameter can be a value of @ref USART_LL_EC_HWCONTROL.

+

+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/

+

+  uint32_t OverSampling;              /*!< Specifies whether USART oversampling mode is 16 or 8.

+                                           This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING.

+

+                                           This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/

+

+} LL_USART_InitTypeDef;

+

+/**

+  * @brief LL USART Clock Init Structure definition

+  */

+typedef struct

+{

+  uint32_t ClockOutput;               /*!< Specifies whether the USART clock is enabled or disabled.

+                                           This parameter can be a value of @ref USART_LL_EC_CLOCK.

+

+                                           USART HW configuration can be modified afterwards using unitary functions

+                                           @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput().

+                                           For more details, refer to description of this function. */

+

+  uint32_t ClockPolarity;             /*!< Specifies the steady state of the serial clock.

+                                           This parameter can be a value of @ref USART_LL_EC_POLARITY.

+

+                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity().

+                                           For more details, refer to description of this function. */

+

+  uint32_t ClockPhase;                /*!< Specifies the clock transition on which the bit capture is made.

+                                           This parameter can be a value of @ref USART_LL_EC_PHASE.

+

+                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase().

+                                           For more details, refer to description of this function. */

+

+  uint32_t LastBitClockPulse;         /*!< Specifies whether the clock pulse corresponding to the last transmitted

+                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.

+                                           This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE.

+

+                                           USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput().

+                                           For more details, refer to description of this function. */

+

+} LL_USART_ClockInitTypeDef;

+

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup USART_LL_Exported_Constants USART Exported Constants

+  * @{

+  */

+

+/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines

+  * @brief    Flags defines which can be used with LL_USART_WriteReg function

+  * @{

+  */

+#define LL_USART_ICR_PECF                       USART_ICR_PECF                /*!< Parity error flag */

+#define LL_USART_ICR_FECF                       USART_ICR_FECF                /*!< Framing error flag */

+#define LL_USART_ICR_NECF                       USART_ICR_NECF                /*!< Noise error detected flag */

+#define LL_USART_ICR_ORECF                      USART_ICR_ORECF               /*!< Overrun error flag */

+#define LL_USART_ICR_IDLECF                     USART_ICR_IDLECF              /*!< Idle line detected flag */

+#define LL_USART_ICR_TXFECF                     USART_ICR_TXFECF              /*!< TX FIFO Empty Clear flag */

+#define LL_USART_ICR_TCCF                       USART_ICR_TCCF                /*!< Transmission complete flag */

+#define LL_USART_ICR_TCBGTCF                    USART_ICR_TCBGTCF             /*!< Transmission completed before guard time flag */

+#define LL_USART_ICR_LBDCF                      USART_ICR_LBDCF               /*!< LIN break detection flag */

+#define LL_USART_ICR_CTSCF                      USART_ICR_CTSCF               /*!< CTS flag */

+#define LL_USART_ICR_RTOCF                      USART_ICR_RTOCF               /*!< Receiver timeout flag */

+#define LL_USART_ICR_EOBCF                      USART_ICR_EOBCF               /*!< End of block flag */

+#define LL_USART_ICR_UDRCF                      USART_ICR_UDRCF               /*!< SPI Slave Underrun Clear flag */

+#define LL_USART_ICR_CMCF                       USART_ICR_CMCF                /*!< Character match flag */

+#define LL_USART_ICR_WUCF                       USART_ICR_WUCF                /*!< Wakeup from Stop mode flag */

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines

+  * @brief    Flags defines which can be used with LL_USART_ReadReg function

+  * @{

+  */

+#define LL_USART_ISR_PE                         USART_ISR_PE                  /*!< Parity error flag */

+#define LL_USART_ISR_FE                         USART_ISR_FE                  /*!< Framing error flag */

+#define LL_USART_ISR_NE                         USART_ISR_NE                  /*!< Noise detected flag */

+#define LL_USART_ISR_ORE                        USART_ISR_ORE                 /*!< Overrun error flag */

+#define LL_USART_ISR_IDLE                       USART_ISR_IDLE                /*!< Idle line detected flag */

+#define LL_USART_ISR_RXNE_RXFNE                 USART_ISR_RXNE_RXFNE          /*!< Read data register or RX FIFO not empty flag */

+#define LL_USART_ISR_TC                         USART_ISR_TC                  /*!< Transmission complete flag */

+#define LL_USART_ISR_TXE_TXFNF                  USART_ISR_TXE_TXFNF           /*!< Transmit data register empty or TX FIFO Not Full flag*/

+#define LL_USART_ISR_LBDF                       USART_ISR_LBDF                /*!< LIN break detection flag */

+#define LL_USART_ISR_CTSIF                      USART_ISR_CTSIF               /*!< CTS interrupt flag */

+#define LL_USART_ISR_CTS                        USART_ISR_CTS                 /*!< CTS flag */

+#define LL_USART_ISR_RTOF                       USART_ISR_RTOF                /*!< Receiver timeout flag */

+#define LL_USART_ISR_EOBF                       USART_ISR_EOBF                /*!< End of block flag */

+#define LL_USART_ISR_UDR                        USART_ISR_UDR                 /*!< SPI Slave underrun error flag */

+#define LL_USART_ISR_ABRE                       USART_ISR_ABRE                /*!< Auto baud rate error flag */

+#define LL_USART_ISR_ABRF                       USART_ISR_ABRF                /*!< Auto baud rate flag */

+#define LL_USART_ISR_BUSY                       USART_ISR_BUSY                /*!< Busy flag */

+#define LL_USART_ISR_CMF                        USART_ISR_CMF                 /*!< Character match flag */

+#define LL_USART_ISR_SBKF                       USART_ISR_SBKF                /*!< Send break flag */

+#define LL_USART_ISR_RWU                        USART_ISR_RWU                 /*!< Receiver wakeup from Mute mode flag */

+#define LL_USART_ISR_WUF                        USART_ISR_WUF                 /*!< Wakeup from Stop mode flag */

+#define LL_USART_ISR_TEACK                      USART_ISR_TEACK               /*!< Transmit enable acknowledge flag */

+#define LL_USART_ISR_REACK                      USART_ISR_REACK               /*!< Receive enable acknowledge flag */

+#define LL_USART_ISR_TXFE                       USART_ISR_TXFE                /*!< TX FIFO empty flag */

+#define LL_USART_ISR_RXFF                       USART_ISR_RXFF                /*!< RX FIFO full flag */

+#define LL_USART_ISR_TCBGT                      USART_ISR_TCBGT               /*!< Transmission complete before guard time completion flag */

+#define LL_USART_ISR_RXFT                       USART_ISR_RXFT                /*!< RX FIFO threshold flag */

+#define LL_USART_ISR_TXFT                       USART_ISR_TXFT                /*!< TX FIFO threshold flag */

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EC_IT IT Defines

+  * @brief    IT defines which can be used with LL_USART_ReadReg and  LL_USART_WriteReg functions

+  * @{

+  */

+#define LL_USART_CR1_IDLEIE                     USART_CR1_IDLEIE              /*!< IDLE interrupt enable */

+#define LL_USART_CR1_RXNEIE_RXFNEIE             USART_CR1_RXNEIE_RXFNEIE      /*!< Read data register and RXFIFO not empty interrupt enable */

+#define LL_USART_CR1_TCIE                       USART_CR1_TCIE                /*!< Transmission complete interrupt enable */

+#define LL_USART_CR1_TXEIE_TXFNFIE              USART_CR1_TXEIE_TXFNFIE       /*!< Transmit data register empty and TX FIFO not full interrupt enable */

+#define LL_USART_CR1_PEIE                       USART_CR1_PEIE                /*!< Parity error */

+#define LL_USART_CR1_CMIE                       USART_CR1_CMIE                /*!< Character match interrupt enable */

+#define LL_USART_CR1_RTOIE                      USART_CR1_RTOIE               /*!< Receiver timeout interrupt enable */

+#define LL_USART_CR1_EOBIE                      USART_CR1_EOBIE               /*!< End of Block interrupt enable */

+#define LL_USART_CR1_TXFEIE                     USART_CR1_TXFEIE              /*!< TX FIFO empty interrupt enable */

+#define LL_USART_CR1_RXFFIE                     USART_CR1_RXFFIE              /*!< RX FIFO full interrupt enable */

+#define LL_USART_CR2_LBDIE                      USART_CR2_LBDIE               /*!< LIN break detection interrupt enable */

+#define LL_USART_CR3_EIE                        USART_CR3_EIE                 /*!< Error interrupt enable */

+#define LL_USART_CR3_CTSIE                      USART_CR3_CTSIE               /*!< CTS interrupt enable */

+#define LL_USART_CR3_WUFIE                      USART_CR3_WUFIE               /*!< Wakeup from Stop mode interrupt enable */

+#define LL_USART_CR3_TXFTIE                     USART_CR3_TXFTIE              /*!< TX FIFO threshold interrupt enable */

+#define LL_USART_CR3_TCBGTIE                    USART_CR3_TCBGTIE             /*!< Transmission complete before guard time interrupt enable */

+#define LL_USART_CR3_RXFTIE                     USART_CR3_RXFTIE              /*!< RX FIFO threshold interrupt enable */

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold

+  * @{

+  */

+#define LL_USART_FIFOTHRESHOLD_1_8              0x00000000U /*!< FIFO reaches 1/8 of its depth */

+#define LL_USART_FIFOTHRESHOLD_1_4              0x00000001U /*!< FIFO reaches 1/4 of its depth */

+#define LL_USART_FIFOTHRESHOLD_1_2              0x00000002U /*!< FIFO reaches 1/2 of its depth */

+#define LL_USART_FIFOTHRESHOLD_3_4              0x00000003U /*!< FIFO reaches 3/4 of its depth */

+#define LL_USART_FIFOTHRESHOLD_7_8              0x00000004U /*!< FIFO reaches 7/8 of its depth */

+#define LL_USART_FIFOTHRESHOLD_8_8              0x00000005U /*!< FIFO becomes empty for TX and full for RX */

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EC_DIRECTION Communication Direction

+  * @{

+  */

+#define LL_USART_DIRECTION_NONE                 0x00000000U                        /*!< Transmitter and Receiver are disabled */

+#define LL_USART_DIRECTION_RX                   USART_CR1_RE                       /*!< Transmitter is disabled and Receiver is enabled */

+#define LL_USART_DIRECTION_TX                   USART_CR1_TE                       /*!< Transmitter is enabled and Receiver is disabled */

+#define LL_USART_DIRECTION_TX_RX                (USART_CR1_TE |USART_CR1_RE)       /*!< Transmitter and Receiver are enabled */

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EC_PARITY Parity Control

+  * @{

+  */

+#define LL_USART_PARITY_NONE                    0x00000000U                          /*!< Parity control disabled */

+#define LL_USART_PARITY_EVEN                    USART_CR1_PCE                        /*!< Parity control enabled and Even Parity is selected */

+#define LL_USART_PARITY_ODD                     (USART_CR1_PCE | USART_CR1_PS)       /*!< Parity control enabled and Odd Parity is selected */

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EC_WAKEUP Wakeup

+  * @{

+  */

+#define LL_USART_WAKEUP_IDLELINE                0x00000000U           /*!<  USART wake up from Mute mode on Idle Line */

+#define LL_USART_WAKEUP_ADDRESSMARK             USART_CR1_WAKE        /*!<  USART wake up from Mute mode on Address Mark */

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EC_DATAWIDTH Datawidth

+  * @{

+  */

+#define LL_USART_DATAWIDTH_7B                   USART_CR1_M1            /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */

+#define LL_USART_DATAWIDTH_8B                   0x00000000U             /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */

+#define LL_USART_DATAWIDTH_9B                   USART_CR1_M0            /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling

+  * @{

+  */

+#define LL_USART_OVERSAMPLING_16                0x00000000U            /*!< Oversampling by 16 */

+#define LL_USART_OVERSAMPLING_8                 USART_CR1_OVER8        /*!< Oversampling by 8 */

+/**

+  * @}

+  */

+

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup USART_LL_EC_CLOCK Clock Signal

+  * @{

+  */

+

+#define LL_USART_CLOCK_DISABLE                  0x00000000U            /*!< Clock signal not provided */

+#define LL_USART_CLOCK_ENABLE                   USART_CR2_CLKEN        /*!< Clock signal provided */

+/**

+  * @}

+  */

+#endif /*USE_FULL_LL_DRIVER*/

+

+/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse

+  * @{

+  */

+#define LL_USART_LASTCLKPULSE_NO_OUTPUT         0x00000000U           /*!< The clock pulse of the last data bit is not output to the SCLK pin */

+#define LL_USART_LASTCLKPULSE_OUTPUT            USART_CR2_LBCL        /*!< The clock pulse of the last data bit is output to the SCLK pin */

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EC_PHASE Clock Phase

+  * @{

+  */

+#define LL_USART_PHASE_1EDGE                    0x00000000U           /*!< The first clock transition is the first data capture edge */

+#define LL_USART_PHASE_2EDGE                    USART_CR2_CPHA        /*!< The second clock transition is the first data capture edge */

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EC_POLARITY Clock Polarity

+  * @{

+  */

+#define LL_USART_POLARITY_LOW                   0x00000000U           /*!< Steady low value on SCLK pin outside transmission window*/

+#define LL_USART_POLARITY_HIGH                  USART_CR2_CPOL        /*!< Steady high value on SCLK pin outside transmission window */

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler

+  * @{

+  */

+#define LL_USART_PRESCALER_DIV1                 0x00000000U                                                                   /*!< Input clock not devided   */

+#define LL_USART_PRESCALER_DIV2                 (USART_PRESC_PRESCALER_0)                                                     /*!< Input clock devided by 2  */

+#define LL_USART_PRESCALER_DIV4                 (USART_PRESC_PRESCALER_1)                                                     /*!< Input clock devided by 4  */

+#define LL_USART_PRESCALER_DIV6                 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 6  */

+#define LL_USART_PRESCALER_DIV8                 (USART_PRESC_PRESCALER_2)                                                     /*!< Input clock devided by 8  */

+#define LL_USART_PRESCALER_DIV10                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 10 */

+#define LL_USART_PRESCALER_DIV12                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1)                           /*!< Input clock devided by 12 */

+#define LL_USART_PRESCALER_DIV16                (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 16 */

+#define LL_USART_PRESCALER_DIV32                (USART_PRESC_PRESCALER_3)                                                     /*!< Input clock devided by 32 */

+#define LL_USART_PRESCALER_DIV64                (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0)                           /*!< Input clock devided by 64 */

+#define LL_USART_PRESCALER_DIV128               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1)                           /*!< Input clock devided by 128 */

+#define LL_USART_PRESCALER_DIV256               (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 256 */

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EC_STOPBITS Stop Bits

+  * @{

+  */

+#define LL_USART_STOPBITS_0_5                   USART_CR2_STOP_0                           /*!< 0.5 stop bit */

+#define LL_USART_STOPBITS_1                     0x00000000U                                /*!< 1 stop bit */

+#define LL_USART_STOPBITS_1_5                   (USART_CR2_STOP_0 | USART_CR2_STOP_1)      /*!< 1.5 stop bits */

+#define LL_USART_STOPBITS_2                     USART_CR2_STOP_1                           /*!< 2 stop bits */

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap

+  * @{

+  */

+#define LL_USART_TXRX_STANDARD                  0x00000000U           /*!< TX/RX pins are used as defined in standard pinout */

+#define LL_USART_TXRX_SWAPPED                   (USART_CR2_SWAP)      /*!< TX and RX pins functions are swapped.             */

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion

+  * @{

+  */

+#define LL_USART_RXPIN_LEVEL_STANDARD           0x00000000U           /*!< RX pin signal works using the standard logic levels */

+#define LL_USART_RXPIN_LEVEL_INVERTED           (USART_CR2_RXINV)     /*!< RX pin signal values are inverted.                  */

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion

+  * @{

+  */

+#define LL_USART_TXPIN_LEVEL_STANDARD           0x00000000U           /*!< TX pin signal works using the standard logic levels */

+#define LL_USART_TXPIN_LEVEL_INVERTED           (USART_CR2_TXINV)     /*!< TX pin signal values are inverted.                  */

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion

+  * @{

+  */

+#define LL_USART_BINARY_LOGIC_POSITIVE          0x00000000U           /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */

+#define LL_USART_BINARY_LOGIC_NEGATIVE          USART_CR2_DATAINV     /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EC_BITORDER Bit Order

+  * @{

+  */

+#define LL_USART_BITORDER_LSBFIRST              0x00000000U           /*!< data is transmitted/received with data bit 0 first, following the start bit */

+#define LL_USART_BITORDER_MSBFIRST              USART_CR2_MSBFIRST    /*!< data is transmitted/received with the MSB first, following the start bit */

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection

+  * @{

+  */

+#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT    0x00000000U                                 /*!< Measurement of the start bit is used to detect the baud rate */

+#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0                         /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */

+#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME    USART_CR2_ABRMODE_1                         /*!< 0x7F frame detection */

+#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME    (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection

+  * @{

+  */

+#define LL_USART_ADDRESS_DETECT_4B              0x00000000U           /*!< 4-bit address detection method selected */

+#define LL_USART_ADDRESS_DETECT_7B              USART_CR2_ADDM7       /*!< 7-bit address detection (in 8-bit data mode) method selected */

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EC_HWCONTROL Hardware Control

+  * @{

+  */

+#define LL_USART_HWCONTROL_NONE                 0x00000000U                          /*!< CTS and RTS hardware flow control disabled */

+#define LL_USART_HWCONTROL_RTS                  USART_CR3_RTSE                       /*!< RTS output enabled, data is only requested when there is space in the receive buffer */

+#define LL_USART_HWCONTROL_CTS                  USART_CR3_CTSE                       /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */

+#define LL_USART_HWCONTROL_RTS_CTS              (USART_CR3_RTSE | USART_CR3_CTSE)    /*!< CTS and RTS hardware flow control enabled */

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EC_WAKEUP_ON Wakeup Activation

+  * @{

+  */

+#define LL_USART_WAKEUP_ON_ADDRESS              0x00000000U                             /*!< Wake up active on address match */

+#define LL_USART_WAKEUP_ON_STARTBIT             USART_CR3_WUS_1                         /*!< Wake up active on Start bit detection */

+#define LL_USART_WAKEUP_ON_RXNE                 (USART_CR3_WUS_0 | USART_CR3_WUS_1)     /*!< Wake up active on RXNE */

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power

+  * @{

+  */

+#define LL_USART_IRDA_POWER_NORMAL              0x00000000U           /*!< IrDA normal power mode */

+#define LL_USART_IRDA_POWER_LOW                 USART_CR3_IRLP        /*!< IrDA low power mode */

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length

+  * @{

+  */

+#define LL_USART_LINBREAK_DETECT_10B            0x00000000U           /*!< 10-bit break detection method selected */

+#define LL_USART_LINBREAK_DETECT_11B            USART_CR2_LBDL        /*!< 11-bit break detection method selected */

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity

+  * @{

+  */

+#define LL_USART_DE_POLARITY_HIGH               0x00000000U           /*!< DE signal is active high */

+#define LL_USART_DE_POLARITY_LOW                USART_CR3_DEP         /*!< DE signal is active low */

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data

+  * @{

+  */

+#define LL_USART_DMA_REG_DATA_TRANSMIT          0x00000000U          /*!< Get address of data register used for transmission */

+#define LL_USART_DMA_REG_DATA_RECEIVE           0x00000001U          /*!< Get address of data register used for reception */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup USART_LL_Exported_Macros USART Exported Macros

+  * @{

+  */

+

+/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros

+  * @{

+  */

+

+/**

+  * @brief  Write a value in USART register

+  * @param  __INSTANCE__ USART Instance

+  * @param  __REG__ Register to be written

+  * @param  __VALUE__ Value to be written in the register

+  * @retval None

+  */

+#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

+

+/**

+  * @brief  Read a value in USART register

+  * @param  __INSTANCE__ USART Instance

+  * @param  __REG__ Register to be read

+  * @retval Register value

+  */

+#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper

+  * @{

+  */

+

+/**

+  * @brief  Compute USARTDIV value according to Peripheral Clock and

+  *         expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned)

+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance

+  * @param  __PRESCALER__ This parameter can be one of the following values:

+  *         @arg @ref LL_USART_PRESCALER_DIV1

+  *         @arg @ref LL_USART_PRESCALER_DIV2

+  *         @arg @ref LL_USART_PRESCALER_DIV4

+  *         @arg @ref LL_USART_PRESCALER_DIV6

+  *         @arg @ref LL_USART_PRESCALER_DIV8

+  *         @arg @ref LL_USART_PRESCALER_DIV10

+  *         @arg @ref LL_USART_PRESCALER_DIV12

+  *         @arg @ref LL_USART_PRESCALER_DIV16

+  *         @arg @ref LL_USART_PRESCALER_DIV32

+  *         @arg @ref LL_USART_PRESCALER_DIV64

+  *         @arg @ref LL_USART_PRESCALER_DIV128

+  *         @arg @ref LL_USART_PRESCALER_DIV256

+  * @param  __BAUDRATE__ Baud rate value to achieve

+  * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case

+  */

+#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\

+                                                                               + ((__BAUDRATE__)/2U))/(__BAUDRATE__))

+

+/**

+  * @brief  Compute USARTDIV value according to Peripheral Clock and

+  *         expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned)

+  * @param  __PERIPHCLK__ Peripheral Clock frequency used for USART instance

+  * @param  __PRESCALER__ This parameter can be one of the following values:

+  *         @arg @ref LL_USART_PRESCALER_DIV1

+  *         @arg @ref LL_USART_PRESCALER_DIV2

+  *         @arg @ref LL_USART_PRESCALER_DIV4

+  *         @arg @ref LL_USART_PRESCALER_DIV6

+  *         @arg @ref LL_USART_PRESCALER_DIV8

+  *         @arg @ref LL_USART_PRESCALER_DIV10

+  *         @arg @ref LL_USART_PRESCALER_DIV12

+  *         @arg @ref LL_USART_PRESCALER_DIV16

+  *         @arg @ref LL_USART_PRESCALER_DIV32

+  *         @arg @ref LL_USART_PRESCALER_DIV64

+  *         @arg @ref LL_USART_PRESCALER_DIV128

+  *         @arg @ref LL_USART_PRESCALER_DIV256

+  * @param  __BAUDRATE__ Baud rate value to achieve

+  * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case

+  */

+#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\

+                                                                                + ((__BAUDRATE__)/2U))/(__BAUDRATE__))

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+

+/** @defgroup USART_LL_Exported_Functions USART Exported Functions

+  * @{

+  */

+

+/** @defgroup USART_LL_EF_Configuration Configuration functions

+  * @{

+  */

+

+/**

+  * @brief  USART Enable

+  * @rmtoll CR1          UE            LL_USART_Enable

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR1, USART_CR1_UE);

+}

+

+/**

+  * @brief  USART Disable (all USART prescalers and outputs are disabled)

+  * @note   When USART is disabled, USART prescalers and outputs are stopped immediately,

+  *         and current operations are discarded. The configuration of the USART is kept, but all the status

+  *         flags, in the USARTx_ISR are set to their default values.

+  * @rmtoll CR1          UE            LL_USART_Disable

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR1, USART_CR1_UE);

+}

+

+/**

+  * @brief  Indicate if USART is enabled

+  * @rmtoll CR1          UE            LL_USART_IsEnabled

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  FIFO Mode Enable

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll CR1          FIFOEN        LL_USART_EnableFIFO

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR1, USART_CR1_FIFOEN);

+}

+

+/**

+  * @brief  FIFO Mode Disable

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll CR1          FIFOEN        LL_USART_DisableFIFO

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN);

+}

+

+/**

+  * @brief  Indicate if FIFO Mode is enabled

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll CR1          FIFOEN        LL_USART_IsEnabledFIFO

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Configure TX FIFO Threshold

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll CR3          TXFTCFG       LL_USART_SetTXFIFOThreshold

+  * @param  USARTx USART Instance

+  * @param  Threshold This parameter can be one of the following values:

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)

+{

+  MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos);

+}

+

+/**

+  * @brief  Return TX FIFO Threshold Configuration

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll CR3          TXFTCFG       LL_USART_GetTXFIFOThreshold

+  * @param  USARTx USART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8

+  */

+__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos);

+}

+

+/**

+  * @brief  Configure RX FIFO Threshold

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll CR3          RXFTCFG       LL_USART_SetRXFIFOThreshold

+  * @param  USARTx USART Instance

+  * @param  Threshold This parameter can be one of the following values:

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold)

+{

+  MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos);

+}

+

+/**

+  * @brief  Return RX FIFO Threshold Configuration

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll CR3          RXFTCFG       LL_USART_GetRXFIFOThreshold

+  * @param  USARTx USART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8

+  */

+__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos);

+}

+

+/**

+  * @brief  Configure TX and RX FIFOs Threshold

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll CR3          TXFTCFG       LL_USART_ConfigFIFOsThreshold\n

+  *         CR3          RXFTCFG       LL_USART_ConfigFIFOsThreshold

+  * @param  USARTx USART Instance

+  * @param  TXThreshold This parameter can be one of the following values:

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8

+  * @param  RXThreshold This parameter can be one of the following values:

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_8

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_4

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_1_2

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_3_4

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_7_8

+  *         @arg @ref LL_USART_FIFOTHRESHOLD_8_8

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold)

+{

+  MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | (RXThreshold << USART_CR3_RXFTCFG_Pos));

+}

+

+/**

+  * @brief  USART enabled in STOP Mode.

+  * @note   When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that

+  *         USART clock selection is HSI or LSE in RCC.

+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not

+  *         Wake-up from Stop mode feature is supported by the USARTx instance.

+  * @rmtoll CR1          UESM          LL_USART_EnableInStopMode

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR1, USART_CR1_UESM);

+}

+

+/**

+  * @brief  USART disabled in STOP Mode.

+  * @note   When this function is disabled, USART is not able to wake up the MCU from Stop mode

+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not

+  *         Wake-up from Stop mode feature is supported by the USARTx instance.

+  * @rmtoll CR1          UESM          LL_USART_DisableInStopMode

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR1, USART_CR1_UESM);

+}

+

+/**

+  * @brief  Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not)

+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not

+  *         Wake-up from Stop mode feature is supported by the USARTx instance.

+  * @rmtoll CR1          UESM          LL_USART_IsEnabledInStopMode

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Receiver Enable (Receiver is enabled and begins searching for a start bit)

+  * @rmtoll CR1          RE            LL_USART_EnableDirectionRx

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR1, USART_CR1_RE);

+}

+

+/**

+  * @brief  Receiver Disable

+  * @rmtoll CR1          RE            LL_USART_DisableDirectionRx

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR1, USART_CR1_RE);

+}

+

+/**

+  * @brief  Transmitter Enable

+  * @rmtoll CR1          TE            LL_USART_EnableDirectionTx

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR1, USART_CR1_TE);

+}

+

+/**

+  * @brief  Transmitter Disable

+  * @rmtoll CR1          TE            LL_USART_DisableDirectionTx

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR1, USART_CR1_TE);

+}

+

+/**

+  * @brief  Configure simultaneously enabled/disabled states

+  *         of Transmitter and Receiver

+  * @rmtoll CR1          RE            LL_USART_SetTransferDirection\n

+  *         CR1          TE            LL_USART_SetTransferDirection

+  * @param  USARTx USART Instance

+  * @param  TransferDirection This parameter can be one of the following values:

+  *         @arg @ref LL_USART_DIRECTION_NONE

+  *         @arg @ref LL_USART_DIRECTION_RX

+  *         @arg @ref LL_USART_DIRECTION_TX

+  *         @arg @ref LL_USART_DIRECTION_TX_RX

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection)

+{

+  MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection);

+}

+

+/**

+  * @brief  Return enabled/disabled states of Transmitter and Receiver

+  * @rmtoll CR1          RE            LL_USART_GetTransferDirection\n

+  *         CR1          TE            LL_USART_GetTransferDirection

+  * @param  USARTx USART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_USART_DIRECTION_NONE

+  *         @arg @ref LL_USART_DIRECTION_RX

+  *         @arg @ref LL_USART_DIRECTION_TX

+  *         @arg @ref LL_USART_DIRECTION_TX_RX

+  */

+__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE));

+}

+

+/**

+  * @brief  Configure Parity (enabled/disabled and parity mode if enabled).

+  * @note   This function selects if hardware parity control (generation and detection) is enabled or disabled.

+  *         When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position

+  *         (9th or 8th bit depending on data width) and parity is checked on the received data.

+  * @rmtoll CR1          PS            LL_USART_SetParity\n

+  *         CR1          PCE           LL_USART_SetParity

+  * @param  USARTx USART Instance

+  * @param  Parity This parameter can be one of the following values:

+  *         @arg @ref LL_USART_PARITY_NONE

+  *         @arg @ref LL_USART_PARITY_EVEN

+  *         @arg @ref LL_USART_PARITY_ODD

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity)

+{

+  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity);

+}

+

+/**

+  * @brief  Return Parity configuration (enabled/disabled and parity mode if enabled)

+  * @rmtoll CR1          PS            LL_USART_GetParity\n

+  *         CR1          PCE           LL_USART_GetParity

+  * @param  USARTx USART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_USART_PARITY_NONE

+  *         @arg @ref LL_USART_PARITY_EVEN

+  *         @arg @ref LL_USART_PARITY_ODD

+  */

+__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE));

+}

+

+/**

+  * @brief  Set Receiver Wake Up method from Mute mode.

+  * @rmtoll CR1          WAKE          LL_USART_SetWakeUpMethod

+  * @param  USARTx USART Instance

+  * @param  Method This parameter can be one of the following values:

+  *         @arg @ref LL_USART_WAKEUP_IDLELINE

+  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method)

+{

+  MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method);

+}

+

+/**

+  * @brief  Return Receiver Wake Up method from Mute mode

+  * @rmtoll CR1          WAKE          LL_USART_GetWakeUpMethod

+  * @param  USARTx USART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_USART_WAKEUP_IDLELINE

+  *         @arg @ref LL_USART_WAKEUP_ADDRESSMARK

+  */

+__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE));

+}

+

+/**

+  * @brief  Set Word length (i.e. nb of data bits, excluding start and stop bits)

+  * @rmtoll CR1          M0            LL_USART_SetDataWidth\n

+  *         CR1          M1            LL_USART_SetDataWidth

+  * @param  USARTx USART Instance

+  * @param  DataWidth This parameter can be one of the following values:

+  *         @arg @ref LL_USART_DATAWIDTH_7B

+  *         @arg @ref LL_USART_DATAWIDTH_8B

+  *         @arg @ref LL_USART_DATAWIDTH_9B

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth)

+{

+  MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth);

+}

+

+/**

+  * @brief  Return Word length (i.e. nb of data bits, excluding start and stop bits)

+  * @rmtoll CR1          M0            LL_USART_GetDataWidth\n

+  *         CR1          M1            LL_USART_GetDataWidth

+  * @param  USARTx USART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_USART_DATAWIDTH_7B

+  *         @arg @ref LL_USART_DATAWIDTH_8B

+  *         @arg @ref LL_USART_DATAWIDTH_9B

+  */

+__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M));

+}

+

+/**

+  * @brief  Allow switch between Mute Mode and Active mode

+  * @rmtoll CR1          MME           LL_USART_EnableMuteMode

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR1, USART_CR1_MME);

+}

+

+/**

+  * @brief  Prevent Mute Mode use. Set Receiver in active mode permanently.

+  * @rmtoll CR1          MME           LL_USART_DisableMuteMode

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR1, USART_CR1_MME);

+}

+

+/**

+  * @brief  Indicate if switch between Mute Mode and Active mode is allowed

+  * @rmtoll CR1          MME           LL_USART_IsEnabledMuteMode

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set Oversampling to 8-bit or 16-bit mode

+  * @rmtoll CR1          OVER8         LL_USART_SetOverSampling

+  * @param  USARTx USART Instance

+  * @param  OverSampling This parameter can be one of the following values:

+  *         @arg @ref LL_USART_OVERSAMPLING_16

+  *         @arg @ref LL_USART_OVERSAMPLING_8

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling)

+{

+  MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling);

+}

+

+/**

+  * @brief  Return Oversampling mode

+  * @rmtoll CR1          OVER8         LL_USART_GetOverSampling

+  * @param  USARTx USART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_USART_OVERSAMPLING_16

+  *         @arg @ref LL_USART_OVERSAMPLING_8

+  */

+__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8));

+}

+

+/**

+  * @brief  Configure if Clock pulse of the last data bit is output to the SCLK pin or not

+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not

+  *         Synchronous mode is supported by the USARTx instance.

+  * @rmtoll CR2          LBCL          LL_USART_SetLastClkPulseOutput

+  * @param  USARTx USART Instance

+  * @param  LastBitClockPulse This parameter can be one of the following values:

+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT

+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse)

+{

+  MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse);

+}

+

+/**

+  * @brief  Retrieve Clock pulse of the last data bit output configuration

+  *         (Last bit Clock pulse output to the SCLK pin or not)

+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not

+  *         Synchronous mode is supported by the USARTx instance.

+  * @rmtoll CR2          LBCL          LL_USART_GetLastClkPulseOutput

+  * @param  USARTx USART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT

+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT

+  */

+__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL));

+}

+

+/**

+  * @brief  Select the phase of the clock output on the SCLK pin in synchronous mode

+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not

+  *         Synchronous mode is supported by the USARTx instance.

+  * @rmtoll CR2          CPHA          LL_USART_SetClockPhase

+  * @param  USARTx USART Instance

+  * @param  ClockPhase This parameter can be one of the following values:

+  *         @arg @ref LL_USART_PHASE_1EDGE

+  *         @arg @ref LL_USART_PHASE_2EDGE

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase)

+{

+  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase);

+}

+

+/**

+  * @brief  Return phase of the clock output on the SCLK pin in synchronous mode

+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not

+  *         Synchronous mode is supported by the USARTx instance.

+  * @rmtoll CR2          CPHA          LL_USART_GetClockPhase

+  * @param  USARTx USART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_USART_PHASE_1EDGE

+  *         @arg @ref LL_USART_PHASE_2EDGE

+  */

+__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA));

+}

+

+/**

+  * @brief  Select the polarity of the clock output on the SCLK pin in synchronous mode

+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not

+  *         Synchronous mode is supported by the USARTx instance.

+  * @rmtoll CR2          CPOL          LL_USART_SetClockPolarity

+  * @param  USARTx USART Instance

+  * @param  ClockPolarity This parameter can be one of the following values:

+  *         @arg @ref LL_USART_POLARITY_LOW

+  *         @arg @ref LL_USART_POLARITY_HIGH

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity)

+{

+  MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity);

+}

+

+/**

+  * @brief  Return polarity of the clock output on the SCLK pin in synchronous mode

+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not

+  *         Synchronous mode is supported by the USARTx instance.

+  * @rmtoll CR2          CPOL          LL_USART_GetClockPolarity

+  * @param  USARTx USART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_USART_POLARITY_LOW

+  *         @arg @ref LL_USART_POLARITY_HIGH

+  */

+__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL));

+}

+

+/**

+  * @brief  Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse)

+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not

+  *         Synchronous mode is supported by the USARTx instance.

+  * @note   Call of this function is equivalent to following function call sequence :

+  *         - Clock Phase configuration using @ref LL_USART_SetClockPhase() function

+  *         - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function

+  *         - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function

+  * @rmtoll CR2          CPHA          LL_USART_ConfigClock\n

+  *         CR2          CPOL          LL_USART_ConfigClock\n

+  *         CR2          LBCL          LL_USART_ConfigClock

+  * @param  USARTx USART Instance

+  * @param  Phase This parameter can be one of the following values:

+  *         @arg @ref LL_USART_PHASE_1EDGE

+  *         @arg @ref LL_USART_PHASE_2EDGE

+  * @param  Polarity This parameter can be one of the following values:

+  *         @arg @ref LL_USART_POLARITY_LOW

+  *         @arg @ref LL_USART_POLARITY_HIGH

+  * @param  LBCPOutput This parameter can be one of the following values:

+  *         @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT

+  *         @arg @ref LL_USART_LASTCLKPULSE_OUTPUT

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput)

+{

+  MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput);

+}

+

+/**

+  * @brief  Configure Clock source prescaler for baudrate generator and oversampling

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll PRESC        PRESCALER     LL_USART_SetPrescaler

+  * @param  USARTx USART Instance

+  * @param  PrescalerValue This parameter can be one of the following values:

+  *         @arg @ref LL_USART_PRESCALER_DIV1

+  *         @arg @ref LL_USART_PRESCALER_DIV2

+  *         @arg @ref LL_USART_PRESCALER_DIV4

+  *         @arg @ref LL_USART_PRESCALER_DIV6

+  *         @arg @ref LL_USART_PRESCALER_DIV8

+  *         @arg @ref LL_USART_PRESCALER_DIV10

+  *         @arg @ref LL_USART_PRESCALER_DIV12

+  *         @arg @ref LL_USART_PRESCALER_DIV16

+  *         @arg @ref LL_USART_PRESCALER_DIV32

+  *         @arg @ref LL_USART_PRESCALER_DIV64

+  *         @arg @ref LL_USART_PRESCALER_DIV128

+  *         @arg @ref LL_USART_PRESCALER_DIV256

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)

+{

+  MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue);

+}

+

+/**

+  * @brief  Retrieve the Clock source prescaler for baudrate generator and oversampling

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll PRESC        PRESCALER     LL_USART_GetPrescaler

+  * @param  USARTx USART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_USART_PRESCALER_DIV1

+  *         @arg @ref LL_USART_PRESCALER_DIV2

+  *         @arg @ref LL_USART_PRESCALER_DIV4

+  *         @arg @ref LL_USART_PRESCALER_DIV6

+  *         @arg @ref LL_USART_PRESCALER_DIV8

+  *         @arg @ref LL_USART_PRESCALER_DIV10

+  *         @arg @ref LL_USART_PRESCALER_DIV12

+  *         @arg @ref LL_USART_PRESCALER_DIV16

+  *         @arg @ref LL_USART_PRESCALER_DIV32

+  *         @arg @ref LL_USART_PRESCALER_DIV64

+  *         @arg @ref LL_USART_PRESCALER_DIV128

+  *         @arg @ref LL_USART_PRESCALER_DIV256

+  */

+__STATIC_INLINE uint32_t LL_USART_GetPrescaler(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER));

+}

+

+/**

+  * @brief  Enable Clock output on SCLK pin

+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not

+  *         Synchronous mode is supported by the USARTx instance.

+  * @rmtoll CR2          CLKEN         LL_USART_EnableSCLKOutput

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);

+}

+

+/**

+  * @brief  Disable Clock output on SCLK pin

+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not

+  *         Synchronous mode is supported by the USARTx instance.

+  * @rmtoll CR2          CLKEN         LL_USART_DisableSCLKOutput

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN);

+}

+

+/**

+  * @brief  Indicate if Clock output on SCLK pin is enabled

+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not

+  *         Synchronous mode is supported by the USARTx instance.

+  * @rmtoll CR2          CLKEN         LL_USART_IsEnabledSCLKOutput

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set the length of the stop bits

+  * @rmtoll CR2          STOP          LL_USART_SetStopBitsLength

+  * @param  USARTx USART Instance

+  * @param  StopBits This parameter can be one of the following values:

+  *         @arg @ref LL_USART_STOPBITS_0_5

+  *         @arg @ref LL_USART_STOPBITS_1

+  *         @arg @ref LL_USART_STOPBITS_1_5

+  *         @arg @ref LL_USART_STOPBITS_2

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits)

+{

+  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);

+}

+

+/**

+  * @brief  Retrieve the length of the stop bits

+  * @rmtoll CR2          STOP          LL_USART_GetStopBitsLength

+  * @param  USARTx USART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_USART_STOPBITS_0_5

+  *         @arg @ref LL_USART_STOPBITS_1

+  *         @arg @ref LL_USART_STOPBITS_1_5

+  *         @arg @ref LL_USART_STOPBITS_2

+  */

+__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP));

+}

+

+/**

+  * @brief  Configure Character frame format (Datawidth, Parity control, Stop Bits)

+  * @note   Call of this function is equivalent to following function call sequence :

+  *         - Data Width configuration using @ref LL_USART_SetDataWidth() function

+  *         - Parity Control and mode configuration using @ref LL_USART_SetParity() function

+  *         - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function

+  * @rmtoll CR1          PS            LL_USART_ConfigCharacter\n

+  *         CR1          PCE           LL_USART_ConfigCharacter\n

+  *         CR1          M0            LL_USART_ConfigCharacter\n

+  *         CR1          M1            LL_USART_ConfigCharacter\n

+  *         CR2          STOP          LL_USART_ConfigCharacter

+  * @param  USARTx USART Instance

+  * @param  DataWidth This parameter can be one of the following values:

+  *         @arg @ref LL_USART_DATAWIDTH_7B

+  *         @arg @ref LL_USART_DATAWIDTH_8B

+  *         @arg @ref LL_USART_DATAWIDTH_9B

+  * @param  Parity This parameter can be one of the following values:

+  *         @arg @ref LL_USART_PARITY_NONE

+  *         @arg @ref LL_USART_PARITY_EVEN

+  *         @arg @ref LL_USART_PARITY_ODD

+  * @param  StopBits This parameter can be one of the following values:

+  *         @arg @ref LL_USART_STOPBITS_0_5

+  *         @arg @ref LL_USART_STOPBITS_1

+  *         @arg @ref LL_USART_STOPBITS_1_5

+  *         @arg @ref LL_USART_STOPBITS_2

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity,

+                                              uint32_t StopBits)

+{

+  MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth);

+  MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits);

+}

+

+/**

+  * @brief  Configure TX/RX pins swapping setting.

+  * @rmtoll CR2          SWAP          LL_USART_SetTXRXSwap

+  * @param  USARTx USART Instance

+  * @param  SwapConfig This parameter can be one of the following values:

+  *         @arg @ref LL_USART_TXRX_STANDARD

+  *         @arg @ref LL_USART_TXRX_SWAPPED

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig)

+{

+  MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig);

+}

+

+/**

+  * @brief  Retrieve TX/RX pins swapping configuration.

+  * @rmtoll CR2          SWAP          LL_USART_GetTXRXSwap

+  * @param  USARTx USART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_USART_TXRX_STANDARD

+  *         @arg @ref LL_USART_TXRX_SWAPPED

+  */

+__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP));

+}

+

+/**

+  * @brief  Configure RX pin active level logic

+  * @rmtoll CR2          RXINV         LL_USART_SetRXPinLevel

+  * @param  USARTx USART Instance

+  * @param  PinInvMethod This parameter can be one of the following values:

+  *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD

+  *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)

+{

+  MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod);

+}

+

+/**

+  * @brief  Retrieve RX pin active level logic configuration

+  * @rmtoll CR2          RXINV         LL_USART_GetRXPinLevel

+  * @param  USARTx USART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_USART_RXPIN_LEVEL_STANDARD

+  *         @arg @ref LL_USART_RXPIN_LEVEL_INVERTED

+  */

+__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV));

+}

+

+/**

+  * @brief  Configure TX pin active level logic

+  * @rmtoll CR2          TXINV         LL_USART_SetTXPinLevel

+  * @param  USARTx USART Instance

+  * @param  PinInvMethod This parameter can be one of the following values:

+  *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD

+  *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod)

+{

+  MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod);

+}

+

+/**

+  * @brief  Retrieve TX pin active level logic configuration

+  * @rmtoll CR2          TXINV         LL_USART_GetTXPinLevel

+  * @param  USARTx USART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_USART_TXPIN_LEVEL_STANDARD

+  *         @arg @ref LL_USART_TXPIN_LEVEL_INVERTED

+  */

+__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV));

+}

+

+/**

+  * @brief  Configure Binary data logic.

+  * @note   Allow to define how Logical data from the data register are send/received :

+  *         either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H)

+  * @rmtoll CR2          DATAINV       LL_USART_SetBinaryDataLogic

+  * @param  USARTx USART Instance

+  * @param  DataLogic This parameter can be one of the following values:

+  *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE

+  *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic)

+{

+  MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic);

+}

+

+/**

+  * @brief  Retrieve Binary data configuration

+  * @rmtoll CR2          DATAINV       LL_USART_GetBinaryDataLogic

+  * @param  USARTx USART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_USART_BINARY_LOGIC_POSITIVE

+  *         @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE

+  */

+__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV));

+}

+

+/**

+  * @brief  Configure transfer bit order (either Less or Most Significant Bit First)

+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.

+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.

+  * @rmtoll CR2          MSBFIRST      LL_USART_SetTransferBitOrder

+  * @param  USARTx USART Instance

+  * @param  BitOrder This parameter can be one of the following values:

+  *         @arg @ref LL_USART_BITORDER_LSBFIRST

+  *         @arg @ref LL_USART_BITORDER_MSBFIRST

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder)

+{

+  MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder);

+}

+

+/**

+  * @brief  Return transfer bit order (either Less or Most Significant Bit First)

+  * @note   MSB First means data is transmitted/received with the MSB first, following the start bit.

+  *         LSB First means data is transmitted/received with data bit 0 first, following the start bit.

+  * @rmtoll CR2          MSBFIRST      LL_USART_GetTransferBitOrder

+  * @param  USARTx USART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_USART_BITORDER_LSBFIRST

+  *         @arg @ref LL_USART_BITORDER_MSBFIRST

+  */

+__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST));

+}

+

+/**

+  * @brief  Enable Auto Baud-Rate Detection

+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not

+  *         Auto Baud Rate detection feature is supported by the USARTx instance.

+  * @rmtoll CR2          ABREN         LL_USART_EnableAutoBaudRate

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR2, USART_CR2_ABREN);

+}

+

+/**

+  * @brief  Disable Auto Baud-Rate Detection

+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not

+  *         Auto Baud Rate detection feature is supported by the USARTx instance.

+  * @rmtoll CR2          ABREN         LL_USART_DisableAutoBaudRate

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN);

+}

+

+/**

+  * @brief  Indicate if Auto Baud-Rate Detection mechanism is enabled

+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not

+  *         Auto Baud Rate detection feature is supported by the USARTx instance.

+  * @rmtoll CR2          ABREN         LL_USART_IsEnabledAutoBaud

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set Auto Baud-Rate mode bits

+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not

+  *         Auto Baud Rate detection feature is supported by the USARTx instance.

+  * @rmtoll CR2          ABRMODE       LL_USART_SetAutoBaudRateMode

+  * @param  USARTx USART Instance

+  * @param  AutoBaudRateMode This parameter can be one of the following values:

+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT

+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE

+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME

+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode)

+{

+  MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode);

+}

+

+/**

+  * @brief  Return Auto Baud-Rate mode

+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not

+  *         Auto Baud Rate detection feature is supported by the USARTx instance.

+  * @rmtoll CR2          ABRMODE       LL_USART_GetAutoBaudRateMode

+  * @param  USARTx USART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT

+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE

+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME

+  *         @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME

+  */

+__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));

+}

+

+/**

+  * @brief  Enable Receiver Timeout

+  * @rmtoll CR2          RTOEN         LL_USART_EnableRxTimeout

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR2, USART_CR2_RTOEN);

+}

+

+/**

+  * @brief  Disable Receiver Timeout

+  * @rmtoll CR2          RTOEN         LL_USART_DisableRxTimeout

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN);

+}

+

+/**

+  * @brief  Indicate if Receiver Timeout feature is enabled

+  * @rmtoll CR2          RTOEN         LL_USART_IsEnabledRxTimeout

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set Address of the USART node.

+  * @note   This is used in multiprocessor communication during Mute mode or Stop mode,

+  *         for wake up with address mark detection.

+  * @note   4bits address node is used when 4-bit Address Detection is selected in ADDM7.

+  *         (b7-b4 should be set to 0)

+  *         8bits address node is used when 7-bit Address Detection is selected in ADDM7.

+  *         (This is used in multiprocessor communication during Mute mode or Stop mode,

+  *         for wake up with 7-bit address mark detection.

+  *         The MSB of the character sent by the transmitter should be equal to 1.

+  *         It may also be used for character detection during normal reception,

+  *         Mute mode inactive (for example, end of block detection in ModBus protocol).

+  *         In this case, the whole received character (8-bit) is compared to the ADD[7:0]

+  *         value and CMF flag is set on match)

+  * @rmtoll CR2          ADD           LL_USART_ConfigNodeAddress\n

+  *         CR2          ADDM7         LL_USART_ConfigNodeAddress

+  * @param  USARTx USART Instance

+  * @param  AddressLen This parameter can be one of the following values:

+  *         @arg @ref LL_USART_ADDRESS_DETECT_4B

+  *         @arg @ref LL_USART_ADDRESS_DETECT_7B

+  * @param  NodeAddress 4 or 7 bit Address of the USART node.

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress)

+{

+  MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7,

+             (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos)));

+}

+

+/**

+  * @brief  Return 8 bit Address of the USART node as set in ADD field of CR2.

+  * @note   If 4-bit Address Detection is selected in ADDM7,

+  *         only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant)

+  *         If 7-bit Address Detection is selected in ADDM7,

+  *         only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant)

+  * @rmtoll CR2          ADD           LL_USART_GetNodeAddress

+  * @param  USARTx USART Instance

+  * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255)

+  */

+__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos);

+}

+

+/**

+  * @brief  Return Length of Node Address used in Address Detection mode (7-bit or 4-bit)

+  * @rmtoll CR2          ADDM7         LL_USART_GetNodeAddressLen

+  * @param  USARTx USART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_USART_ADDRESS_DETECT_4B

+  *         @arg @ref LL_USART_ADDRESS_DETECT_7B

+  */

+__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7));

+}

+

+/**

+  * @brief  Enable RTS HW Flow Control

+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not

+  *         Hardware Flow control feature is supported by the USARTx instance.

+  * @rmtoll CR3          RTSE          LL_USART_EnableRTSHWFlowCtrl

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR3, USART_CR3_RTSE);

+}

+

+/**

+  * @brief  Disable RTS HW Flow Control

+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not

+  *         Hardware Flow control feature is supported by the USARTx instance.

+  * @rmtoll CR3          RTSE          LL_USART_DisableRTSHWFlowCtrl

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE);

+}

+

+/**

+  * @brief  Enable CTS HW Flow Control

+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not

+  *         Hardware Flow control feature is supported by the USARTx instance.

+  * @rmtoll CR3          CTSE          LL_USART_EnableCTSHWFlowCtrl

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR3, USART_CR3_CTSE);

+}

+

+/**

+  * @brief  Disable CTS HW Flow Control

+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not

+  *         Hardware Flow control feature is supported by the USARTx instance.

+  * @rmtoll CR3          CTSE          LL_USART_DisableCTSHWFlowCtrl

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE);

+}

+

+/**

+  * @brief  Configure HW Flow Control mode (both CTS and RTS)

+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not

+  *         Hardware Flow control feature is supported by the USARTx instance.

+  * @rmtoll CR3          RTSE          LL_USART_SetHWFlowCtrl\n

+  *         CR3          CTSE          LL_USART_SetHWFlowCtrl

+  * @param  USARTx USART Instance

+  * @param  HardwareFlowControl This parameter can be one of the following values:

+  *         @arg @ref LL_USART_HWCONTROL_NONE

+  *         @arg @ref LL_USART_HWCONTROL_RTS

+  *         @arg @ref LL_USART_HWCONTROL_CTS

+  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl)

+{

+  MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl);

+}

+

+/**

+  * @brief  Return HW Flow Control configuration (both CTS and RTS)

+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not

+  *         Hardware Flow control feature is supported by the USARTx instance.

+  * @rmtoll CR3          RTSE          LL_USART_GetHWFlowCtrl\n

+  *         CR3          CTSE          LL_USART_GetHWFlowCtrl

+  * @param  USARTx USART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_USART_HWCONTROL_NONE

+  *         @arg @ref LL_USART_HWCONTROL_RTS

+  *         @arg @ref LL_USART_HWCONTROL_CTS

+  *         @arg @ref LL_USART_HWCONTROL_RTS_CTS

+  */

+__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE));

+}

+

+/**

+  * @brief  Enable One bit sampling method

+  * @rmtoll CR3          ONEBIT        LL_USART_EnableOneBitSamp

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR3, USART_CR3_ONEBIT);

+}

+

+/**

+  * @brief  Disable One bit sampling method

+  * @rmtoll CR3          ONEBIT        LL_USART_DisableOneBitSamp

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT);

+}

+

+/**

+  * @brief  Indicate if One bit sampling method is enabled

+  * @rmtoll CR3          ONEBIT        LL_USART_IsEnabledOneBitSamp

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable Overrun detection

+  * @rmtoll CR3          OVRDIS        LL_USART_EnableOverrunDetect

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS);

+}

+

+/**

+  * @brief  Disable Overrun detection

+  * @rmtoll CR3          OVRDIS        LL_USART_DisableOverrunDetect

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR3, USART_CR3_OVRDIS);

+}

+

+/**

+  * @brief  Indicate if Overrun detection is enabled

+  * @rmtoll CR3          OVRDIS        LL_USART_IsEnabledOverrunDetect

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Select event type for Wake UP Interrupt Flag (WUS[1:0] bits)

+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not

+  *         Wake-up from Stop mode feature is supported by the USARTx instance.

+  * @rmtoll CR3          WUS           LL_USART_SetWKUPType

+  * @param  USARTx USART Instance

+  * @param  Type This parameter can be one of the following values:

+  *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS

+  *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT

+  *         @arg @ref LL_USART_WAKEUP_ON_RXNE

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type)

+{

+  MODIFY_REG(USARTx->CR3, USART_CR3_WUS, Type);

+}

+

+/**

+  * @brief  Return event type for Wake UP Interrupt Flag (WUS[1:0] bits)

+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not

+  *         Wake-up from Stop mode feature is supported by the USARTx instance.

+  * @rmtoll CR3          WUS           LL_USART_GetWKUPType

+  * @param  USARTx USART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_USART_WAKEUP_ON_ADDRESS

+  *         @arg @ref LL_USART_WAKEUP_ON_STARTBIT

+  *         @arg @ref LL_USART_WAKEUP_ON_RXNE

+  */

+__STATIC_INLINE uint32_t LL_USART_GetWKUPType(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_WUS));

+}

+

+/**

+  * @brief  Configure USART BRR register for achieving expected Baud Rate value.

+  * @note   Compute and set USARTDIV value in BRR Register (full BRR content)

+  *         according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values

+  * @note   Peripheral clock and Baud rate values provided as function parameters should be valid

+  *         (Baud rate value != 0)

+  * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.

+  * @rmtoll BRR          BRR           LL_USART_SetBaudRate

+  * @param  USARTx USART Instance

+  * @param  PeriphClk Peripheral Clock

+  * @param  PrescalerValue This parameter can be one of the following values:

+  *         @arg @ref LL_USART_PRESCALER_DIV1

+  *         @arg @ref LL_USART_PRESCALER_DIV2

+  *         @arg @ref LL_USART_PRESCALER_DIV4

+  *         @arg @ref LL_USART_PRESCALER_DIV6

+  *         @arg @ref LL_USART_PRESCALER_DIV8

+  *         @arg @ref LL_USART_PRESCALER_DIV10

+  *         @arg @ref LL_USART_PRESCALER_DIV12

+  *         @arg @ref LL_USART_PRESCALER_DIV16

+  *         @arg @ref LL_USART_PRESCALER_DIV32

+  *         @arg @ref LL_USART_PRESCALER_DIV64

+  *         @arg @ref LL_USART_PRESCALER_DIV128

+  *         @arg @ref LL_USART_PRESCALER_DIV256

+  * @param  OverSampling This parameter can be one of the following values:

+  *         @arg @ref LL_USART_OVERSAMPLING_16

+  *         @arg @ref LL_USART_OVERSAMPLING_8

+  * @param  BaudRate Baud Rate

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,

+                                          uint32_t OverSampling,

+                                          uint32_t BaudRate)

+{

+  uint32_t usartdiv;

+  register uint32_t brrtemp;

+

+  if (PrescalerValue > LL_USART_PRESCALER_DIV256)

+  {

+    /* Do not overstep the size of USART_PRESCALER_TAB */

+  }

+  else if (OverSampling == LL_USART_OVERSAMPLING_8)

+  {

+    usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate));

+    brrtemp = usartdiv & 0xFFF0U;

+    brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U);

+    USARTx->BRR = brrtemp;

+  }

+  else

+  {

+    USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate));

+  }

+}

+

+/**

+  * @brief  Return current Baud Rate value, according to USARTDIV present in BRR register

+  *         (full BRR content), and to used Peripheral Clock and Oversampling mode values

+  * @note   In case of non-initialized or invalid value stored in BRR register, value 0 will be returned.

+  * @note   In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d.

+  * @rmtoll BRR          BRR           LL_USART_GetBaudRate

+  * @param  USARTx USART Instance

+  * @param  PeriphClk Peripheral Clock

+  * @param  PrescalerValue This parameter can be one of the following values:

+  *         @arg @ref LL_USART_PRESCALER_DIV1

+  *         @arg @ref LL_USART_PRESCALER_DIV2

+  *         @arg @ref LL_USART_PRESCALER_DIV4

+  *         @arg @ref LL_USART_PRESCALER_DIV6

+  *         @arg @ref LL_USART_PRESCALER_DIV8

+  *         @arg @ref LL_USART_PRESCALER_DIV10

+  *         @arg @ref LL_USART_PRESCALER_DIV12

+  *         @arg @ref LL_USART_PRESCALER_DIV16

+  *         @arg @ref LL_USART_PRESCALER_DIV32

+  *         @arg @ref LL_USART_PRESCALER_DIV64

+  *         @arg @ref LL_USART_PRESCALER_DIV128

+  *         @arg @ref LL_USART_PRESCALER_DIV256

+  * @param  OverSampling This parameter can be one of the following values:

+  *         @arg @ref LL_USART_OVERSAMPLING_16

+  *         @arg @ref LL_USART_OVERSAMPLING_8

+  * @retval Baud Rate

+  */

+__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue,

+                                              uint32_t OverSampling)

+{

+  register uint32_t usartdiv;

+  register uint32_t brrresult = 0x0U;

+  register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue]));

+

+  usartdiv = USARTx->BRR;

+

+  if (usartdiv == 0U)

+  {

+    /* Do not perform a division by 0 */

+  }

+  else if (OverSampling == LL_USART_OVERSAMPLING_8)

+  {

+    usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ;

+    if (usartdiv != 0U)

+    {

+      brrresult = (periphclkpresc * 2U) / usartdiv;

+    }

+  }

+  else

+  {

+    if ((usartdiv & 0xFFFFU) != 0U)

+    {

+      brrresult = periphclkpresc / usartdiv;

+    }

+  }

+  return (brrresult);

+}

+

+/**

+  * @brief  Set Receiver Time Out Value (expressed in nb of bits duration)

+  * @rmtoll RTOR         RTO           LL_USART_SetRxTimeout

+  * @param  USARTx USART Instance

+  * @param  Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout)

+{

+  MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout);

+}

+

+/**

+  * @brief  Get Receiver Time Out Value (expressed in nb of bits duration)

+  * @rmtoll RTOR         RTO           LL_USART_GetRxTimeout

+  * @param  USARTx USART Instance

+  * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF

+  */

+__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO));

+}

+

+/**

+  * @brief  Set Block Length value in reception

+  * @rmtoll RTOR         BLEN          LL_USART_SetBlockLength

+  * @param  USARTx USART Instance

+  * @param  BlockLength Value between Min_Data=0x00 and Max_Data=0xFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength)

+{

+  MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos);

+}

+

+/**

+  * @brief  Get Block Length value in reception

+  * @rmtoll RTOR         BLEN          LL_USART_GetBlockLength

+  * @param  USARTx USART Instance

+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF

+  */

+__STATIC_INLINE uint32_t LL_USART_GetBlockLength(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature

+  * @{

+  */

+

+/**

+  * @brief  Enable IrDA mode

+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not

+  *         IrDA feature is supported by the USARTx instance.

+  * @rmtoll CR3          IREN          LL_USART_EnableIrda

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR3, USART_CR3_IREN);

+}

+

+/**

+  * @brief  Disable IrDA mode

+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not

+  *         IrDA feature is supported by the USARTx instance.

+  * @rmtoll CR3          IREN          LL_USART_DisableIrda

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR3, USART_CR3_IREN);

+}

+

+/**

+  * @brief  Indicate if IrDA mode is enabled

+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not

+  *         IrDA feature is supported by the USARTx instance.

+  * @rmtoll CR3          IREN          LL_USART_IsEnabledIrda

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Configure IrDA Power Mode (Normal or Low Power)

+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not

+  *         IrDA feature is supported by the USARTx instance.

+  * @rmtoll CR3          IRLP          LL_USART_SetIrdaPowerMode

+  * @param  USARTx USART Instance

+  * @param  PowerMode This parameter can be one of the following values:

+  *         @arg @ref LL_USART_IRDA_POWER_NORMAL

+  *         @arg @ref LL_USART_IRDA_POWER_LOW

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode)

+{

+  MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode);

+}

+

+/**

+  * @brief  Retrieve IrDA Power Mode configuration (Normal or Low Power)

+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not

+  *         IrDA feature is supported by the USARTx instance.

+  * @rmtoll CR3          IRLP          LL_USART_GetIrdaPowerMode

+  * @param  USARTx USART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_USART_IRDA_POWER_NORMAL

+  *         @arg @ref LL_USART_PHASE_2EDGE

+  */

+__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP));

+}

+

+/**

+  * @brief  Set Irda prescaler value, used for dividing the USART clock source

+  *         to achieve the Irda Low Power frequency (8 bits value)

+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not

+  *         IrDA feature is supported by the USARTx instance.

+  * @rmtoll GTPR         PSC           LL_USART_SetIrdaPrescaler

+  * @param  USARTx USART Instance

+  * @param  PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)

+{

+  MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue);

+}

+

+/**

+  * @brief  Return Irda prescaler value, used for dividing the USART clock source

+  *         to achieve the Irda Low Power frequency (8 bits value)

+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not

+  *         IrDA feature is supported by the USARTx instance.

+  * @rmtoll GTPR         PSC           LL_USART_GetIrdaPrescaler

+  * @param  USARTx USART Instance

+  * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF)

+  */

+__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature

+  * @{

+  */

+

+/**

+  * @brief  Enable Smartcard NACK transmission

+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not

+  *         Smartcard feature is supported by the USARTx instance.

+  * @rmtoll CR3          NACK          LL_USART_EnableSmartcardNACK

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR3, USART_CR3_NACK);

+}

+

+/**

+  * @brief  Disable Smartcard NACK transmission

+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not

+  *         Smartcard feature is supported by the USARTx instance.

+  * @rmtoll CR3          NACK          LL_USART_DisableSmartcardNACK

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR3, USART_CR3_NACK);

+}

+

+/**

+  * @brief  Indicate if Smartcard NACK transmission is enabled

+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not

+  *         Smartcard feature is supported by the USARTx instance.

+  * @rmtoll CR3          NACK          LL_USART_IsEnabledSmartcardNACK

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable Smartcard mode

+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not

+  *         Smartcard feature is supported by the USARTx instance.

+  * @rmtoll CR3          SCEN          LL_USART_EnableSmartcard

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR3, USART_CR3_SCEN);

+}

+

+/**

+  * @brief  Disable Smartcard mode

+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not

+  *         Smartcard feature is supported by the USARTx instance.

+  * @rmtoll CR3          SCEN          LL_USART_DisableSmartcard

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN);

+}

+

+/**

+  * @brief  Indicate if Smartcard mode is enabled

+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not

+  *         Smartcard feature is supported by the USARTx instance.

+  * @rmtoll CR3          SCEN          LL_USART_IsEnabledSmartcard

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)

+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not

+  *         Smartcard feature is supported by the USARTx instance.

+  * @note   This bit-field specifies the number of retries in transmit and receive, in Smartcard mode.

+  *         In transmission mode, it specifies the number of automatic retransmission retries, before

+  *         generating a transmission error (FE bit set).

+  *         In reception mode, it specifies the number or erroneous reception trials, before generating a

+  *         reception error (RXNE and PE bits set)

+  * @rmtoll CR3          SCARCNT       LL_USART_SetSmartcardAutoRetryCount

+  * @param  USARTx USART Instance

+  * @param  AutoRetryCount Value between Min_Data=0 and Max_Data=7

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount)

+{

+  MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos);

+}

+

+/**

+  * @brief  Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits)

+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not

+  *         Smartcard feature is supported by the USARTx instance.

+  * @rmtoll CR3          SCARCNT       LL_USART_GetSmartcardAutoRetryCount

+  * @param  USARTx USART Instance

+  * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7)

+  */

+__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos);

+}

+

+/**

+  * @brief  Set Smartcard prescaler value, used for dividing the USART clock

+  *         source to provide the SMARTCARD Clock (5 bits value)

+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not

+  *         Smartcard feature is supported by the USARTx instance.

+  * @rmtoll GTPR         PSC           LL_USART_SetSmartcardPrescaler

+  * @param  USARTx USART Instance

+  * @param  PrescalerValue Value between Min_Data=0 and Max_Data=31

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue)

+{

+  MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)PrescalerValue);

+}

+

+/**

+  * @brief  Return Smartcard prescaler value, used for dividing the USART clock

+  *         source to provide the SMARTCARD Clock (5 bits value)

+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not

+  *         Smartcard feature is supported by the USARTx instance.

+  * @rmtoll GTPR         PSC           LL_USART_GetSmartcardPrescaler

+  * @param  USARTx USART Instance

+  * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31)

+  */

+__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC));

+}

+

+/**

+  * @brief  Set Smartcard Guard time value, expressed in nb of baud clocks periods

+  *         (GT[7:0] bits : Guard time value)

+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not

+  *         Smartcard feature is supported by the USARTx instance.

+  * @rmtoll GTPR         GT            LL_USART_SetSmartcardGuardTime

+  * @param  USARTx USART Instance

+  * @param  GuardTime Value between Min_Data=0x00 and Max_Data=0xFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime)

+{

+  MODIFY_REG(USARTx->GTPR, (uint16_t)USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos));

+}

+

+/**

+  * @brief  Return Smartcard Guard time value, expressed in nb of baud clocks periods

+  *         (GT[7:0] bits : Guard time value)

+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not

+  *         Smartcard feature is supported by the USARTx instance.

+  * @rmtoll GTPR         GT            LL_USART_GetSmartcardGuardTime

+  * @param  USARTx USART Instance

+  * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF)

+  */

+__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature

+  * @{

+  */

+

+/**

+  * @brief  Enable Single Wire Half-Duplex mode

+  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not

+  *         Half-Duplex mode is supported by the USARTx instance.

+  * @rmtoll CR3          HDSEL         LL_USART_EnableHalfDuplex

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);

+}

+

+/**

+  * @brief  Disable Single Wire Half-Duplex mode

+  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not

+  *         Half-Duplex mode is supported by the USARTx instance.

+  * @rmtoll CR3          HDSEL         LL_USART_DisableHalfDuplex

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL);

+}

+

+/**

+  * @brief  Indicate if Single Wire Half-Duplex mode is enabled

+  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not

+  *         Half-Duplex mode is supported by the USARTx instance.

+  * @rmtoll CR3          HDSEL         LL_USART_IsEnabledHalfDuplex

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature

+  * @{

+  */

+/**

+  * @brief  Enable SPI Synchronous Slave mode

+  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not

+  *         SPI Slave mode feature is supported by the USARTx instance.

+  * @rmtoll CR2          SLVEN         LL_USART_EnableSPISlave

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR2, USART_CR2_SLVEN);

+}

+

+/**

+  * @brief  Disable SPI Synchronous Slave mode

+  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not

+  *         SPI Slave mode feature is supported by the USARTx instance.

+  * @rmtoll CR2          SLVEN         LL_USART_DisableSPISlave

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN);

+}

+

+/**

+  * @brief  Indicate if  SPI Synchronous Slave mode is enabled

+  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not

+  *         SPI Slave mode feature is supported by the USARTx instance.

+  * @rmtoll CR2          SLVEN         LL_USART_IsEnabledSPISlave

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable SPI Slave Selection using NSS input pin

+  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not

+  *         SPI Slave mode feature is supported by the USARTx instance.

+  * @note   SPI Slave Selection depends on NSS input pin

+  *         (The slave is selected when NSS is low and deselected when NSS is high).

+  * @rmtoll CR2          DIS_NSS       LL_USART_EnableSPISlaveSelect

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS);

+}

+

+/**

+  * @brief  Disable SPI Slave Selection using NSS input pin

+  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not

+  *         SPI Slave mode feature is supported by the USARTx instance.

+  * @note   SPI Slave will be always selected and NSS input pin will be ignored.

+  * @rmtoll CR2          DIS_NSS       LL_USART_DisableSPISlaveSelect

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS);

+}

+

+/**

+  * @brief  Indicate if  SPI Slave Selection depends on NSS input pin

+  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not

+  *         SPI Slave mode feature is supported by the USARTx instance.

+  * @rmtoll CR2          DIS_NSS       LL_USART_IsEnabledSPISlaveSelect

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature

+  * @{

+  */

+

+/**

+  * @brief  Set LIN Break Detection Length

+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not

+  *         LIN feature is supported by the USARTx instance.

+  * @rmtoll CR2          LBDL          LL_USART_SetLINBrkDetectionLen

+  * @param  USARTx USART Instance

+  * @param  LINBDLength This parameter can be one of the following values:

+  *         @arg @ref LL_USART_LINBREAK_DETECT_10B

+  *         @arg @ref LL_USART_LINBREAK_DETECT_11B

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength)

+{

+  MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength);

+}

+

+/**

+  * @brief  Return LIN Break Detection Length

+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not

+  *         LIN feature is supported by the USARTx instance.

+  * @rmtoll CR2          LBDL          LL_USART_GetLINBrkDetectionLen

+  * @param  USARTx USART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_USART_LINBREAK_DETECT_10B

+  *         @arg @ref LL_USART_LINBREAK_DETECT_11B

+  */

+__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL));

+}

+

+/**

+  * @brief  Enable LIN mode

+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not

+  *         LIN feature is supported by the USARTx instance.

+  * @rmtoll CR2          LINEN         LL_USART_EnableLIN

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR2, USART_CR2_LINEN);

+}

+

+/**

+  * @brief  Disable LIN mode

+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not

+  *         LIN feature is supported by the USARTx instance.

+  * @rmtoll CR2          LINEN         LL_USART_DisableLIN

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN);

+}

+

+/**

+  * @brief  Indicate if LIN mode is enabled

+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not

+  *         LIN feature is supported by the USARTx instance.

+  * @rmtoll CR2          LINEN         LL_USART_IsEnabledLIN

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature

+  * @{

+  */

+

+/**

+  * @brief  Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits).

+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not

+  *         Driver Enable feature is supported by the USARTx instance.

+  * @rmtoll CR1          DEDT          LL_USART_SetDEDeassertionTime

+  * @param  USARTx USART Instance

+  * @param  Time Value between Min_Data=0 and Max_Data=31

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time)

+{

+  MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos);

+}

+

+/**

+  * @brief  Return DEDT (Driver Enable De-Assertion Time)

+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not

+  *         Driver Enable feature is supported by the USARTx instance.

+  * @rmtoll CR1          DEDT          LL_USART_GetDEDeassertionTime

+  * @param  USARTx USART Instance

+  * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31

+  */

+__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos);

+}

+

+/**

+  * @brief  Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits).

+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not

+  *         Driver Enable feature is supported by the USARTx instance.

+  * @rmtoll CR1          DEAT          LL_USART_SetDEAssertionTime

+  * @param  USARTx USART Instance

+  * @param  Time Value between Min_Data=0 and Max_Data=31

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time)

+{

+  MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos);

+}

+

+/**

+  * @brief  Return DEAT (Driver Enable Assertion Time)

+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not

+  *         Driver Enable feature is supported by the USARTx instance.

+  * @rmtoll CR1          DEAT          LL_USART_GetDEAssertionTime

+  * @param  USARTx USART Instance

+  * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31

+  */

+__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos);

+}

+

+/**

+  * @brief  Enable Driver Enable (DE) Mode

+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not

+  *         Driver Enable feature is supported by the USARTx instance.

+  * @rmtoll CR3          DEM           LL_USART_EnableDEMode

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR3, USART_CR3_DEM);

+}

+

+/**

+  * @brief  Disable Driver Enable (DE) Mode

+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not

+  *         Driver Enable feature is supported by the USARTx instance.

+  * @rmtoll CR3          DEM           LL_USART_DisableDEMode

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR3, USART_CR3_DEM);

+}

+

+/**

+  * @brief  Indicate if Driver Enable (DE) Mode is enabled

+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not

+  *         Driver Enable feature is supported by the USARTx instance.

+  * @rmtoll CR3          DEM           LL_USART_IsEnabledDEMode

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Select Driver Enable Polarity

+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not

+  *         Driver Enable feature is supported by the USARTx instance.

+  * @rmtoll CR3          DEP           LL_USART_SetDESignalPolarity

+  * @param  USARTx USART Instance

+  * @param  Polarity This parameter can be one of the following values:

+  *         @arg @ref LL_USART_DE_POLARITY_HIGH

+  *         @arg @ref LL_USART_DE_POLARITY_LOW

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity)

+{

+  MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity);

+}

+

+/**

+  * @brief  Return Driver Enable Polarity

+  * @note   Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not

+  *         Driver Enable feature is supported by the USARTx instance.

+  * @rmtoll CR3          DEP           LL_USART_GetDESignalPolarity

+  * @param  USARTx USART Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_USART_DE_POLARITY_HIGH

+  *         @arg @ref LL_USART_DE_POLARITY_LOW

+  */

+__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(USART_TypeDef *USARTx)

+{

+  return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services

+  * @{

+  */

+

+/**

+  * @brief  Perform basic configuration of USART for enabling use in Asynchronous Mode (UART)

+  * @note   In UART mode, the following bits must be kept cleared:

+  *           - LINEN bit in the USART_CR2 register,

+  *           - CLKEN bit in the USART_CR2 register,

+  *           - SCEN bit in the USART_CR3 register,

+  *           - IREN bit in the USART_CR3 register,

+  *           - HDSEL bit in the USART_CR3 register.

+  * @note   Call of this function is equivalent to following function call sequence :

+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function

+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function

+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function

+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function

+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function

+  * @note   Other remaining configurations items related to Asynchronous Mode

+  *         (as Baud Rate, Word length, Parity, ...) should be set using

+  *         dedicated functions

+  * @rmtoll CR2          LINEN         LL_USART_ConfigAsyncMode\n

+  *         CR2          CLKEN         LL_USART_ConfigAsyncMode\n

+  *         CR3          SCEN          LL_USART_ConfigAsyncMode\n

+  *         CR3          IREN          LL_USART_ConfigAsyncMode\n

+  *         CR3          HDSEL         LL_USART_ConfigAsyncMode

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx)

+{

+  /* In Asynchronous mode, the following bits must be kept cleared:

+  - LINEN, CLKEN bits in the USART_CR2 register,

+  - SCEN, IREN and HDSEL bits in the USART_CR3 register.

+  */

+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));

+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));

+}

+

+/**

+  * @brief  Perform basic configuration of USART for enabling use in Synchronous Mode

+  * @note   In Synchronous mode, the following bits must be kept cleared:

+  *           - LINEN bit in the USART_CR2 register,

+  *           - SCEN bit in the USART_CR3 register,

+  *           - IREN bit in the USART_CR3 register,

+  *           - HDSEL bit in the USART_CR3 register.

+  *         This function also sets the USART in Synchronous mode.

+  * @note   Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not

+  *         Synchronous mode is supported by the USARTx instance.

+  * @note   Call of this function is equivalent to following function call sequence :

+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function

+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function

+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function

+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function

+  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function

+  * @note   Other remaining configurations items related to Synchronous Mode

+  *         (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using

+  *         dedicated functions

+  * @rmtoll CR2          LINEN         LL_USART_ConfigSyncMode\n

+  *         CR2          CLKEN         LL_USART_ConfigSyncMode\n

+  *         CR3          SCEN          LL_USART_ConfigSyncMode\n

+  *         CR3          IREN          LL_USART_ConfigSyncMode\n

+  *         CR3          HDSEL         LL_USART_ConfigSyncMode

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx)

+{

+  /* In Synchronous mode, the following bits must be kept cleared:

+  - LINEN bit in the USART_CR2 register,

+  - SCEN, IREN and HDSEL bits in the USART_CR3 register.

+  */

+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));

+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL));

+  /* set the UART/USART in Synchronous mode */

+  SET_BIT(USARTx->CR2, USART_CR2_CLKEN);

+}

+

+/**

+  * @brief  Perform basic configuration of USART for enabling use in LIN Mode

+  * @note   In LIN mode, the following bits must be kept cleared:

+  *           - STOP and CLKEN bits in the USART_CR2 register,

+  *           - SCEN bit in the USART_CR3 register,

+  *           - IREN bit in the USART_CR3 register,

+  *           - HDSEL bit in the USART_CR3 register.

+  *         This function also set the UART/USART in LIN mode.

+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not

+  *         LIN feature is supported by the USARTx instance.

+  * @note   Call of this function is equivalent to following function call sequence :

+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function

+  *         - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function

+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function

+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function

+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function

+  *         - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function

+  * @note   Other remaining configurations items related to LIN Mode

+  *         (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using

+  *         dedicated functions

+  * @rmtoll CR2          CLKEN         LL_USART_ConfigLINMode\n

+  *         CR2          STOP          LL_USART_ConfigLINMode\n

+  *         CR2          LINEN         LL_USART_ConfigLINMode\n

+  *         CR3          IREN          LL_USART_ConfigLINMode\n

+  *         CR3          SCEN          LL_USART_ConfigLINMode\n

+  *         CR3          HDSEL         LL_USART_ConfigLINMode

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx)

+{

+  /* In LIN mode, the following bits must be kept cleared:

+  - STOP and CLKEN bits in the USART_CR2 register,

+  - IREN, SCEN and HDSEL bits in the USART_CR3 register.

+  */

+  CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP));

+  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));

+  /* Set the UART/USART in LIN mode */

+  SET_BIT(USARTx->CR2, USART_CR2_LINEN);

+}

+

+/**

+  * @brief  Perform basic configuration of USART for enabling use in Half Duplex Mode

+  * @note   In Half Duplex mode, the following bits must be kept cleared:

+  *           - LINEN bit in the USART_CR2 register,

+  *           - CLKEN bit in the USART_CR2 register,

+  *           - SCEN bit in the USART_CR3 register,

+  *           - IREN bit in the USART_CR3 register,

+  *         This function also sets the UART/USART in Half Duplex mode.

+  * @note   Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not

+  *         Half-Duplex mode is supported by the USARTx instance.

+  * @note   Call of this function is equivalent to following function call sequence :

+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function

+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function

+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function

+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function

+  *         - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function

+  * @note   Other remaining configurations items related to Half Duplex Mode

+  *         (as Baud Rate, Word length, Parity, ...) should be set using

+  *         dedicated functions

+  * @rmtoll CR2          LINEN         LL_USART_ConfigHalfDuplexMode\n

+  *         CR2          CLKEN         LL_USART_ConfigHalfDuplexMode\n

+  *         CR3          HDSEL         LL_USART_ConfigHalfDuplexMode\n

+  *         CR3          SCEN          LL_USART_ConfigHalfDuplexMode\n

+  *         CR3          IREN          LL_USART_ConfigHalfDuplexMode

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx)

+{

+  /* In Half Duplex mode, the following bits must be kept cleared:

+  - LINEN and CLKEN bits in the USART_CR2 register,

+  - SCEN and IREN bits in the USART_CR3 register.

+  */

+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));

+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN));

+  /* set the UART/USART in Half Duplex mode */

+  SET_BIT(USARTx->CR3, USART_CR3_HDSEL);

+}

+

+/**

+  * @brief  Perform basic configuration of USART for enabling use in Smartcard Mode

+  * @note   In Smartcard mode, the following bits must be kept cleared:

+  *           - LINEN bit in the USART_CR2 register,

+  *           - IREN bit in the USART_CR3 register,

+  *           - HDSEL bit in the USART_CR3 register.

+  *         This function also configures Stop bits to 1.5 bits and

+  *         sets the USART in Smartcard mode (SCEN bit).

+  *         Clock Output is also enabled (CLKEN).

+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not

+  *         Smartcard feature is supported by the USARTx instance.

+  * @note   Call of this function is equivalent to following function call sequence :

+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function

+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function

+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function

+  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function

+  *         - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function

+  *         - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function

+  * @note   Other remaining configurations items related to Smartcard Mode

+  *         (as Baud Rate, Word length, Parity, ...) should be set using

+  *         dedicated functions

+  * @rmtoll CR2          LINEN         LL_USART_ConfigSmartcardMode\n

+  *         CR2          STOP          LL_USART_ConfigSmartcardMode\n

+  *         CR2          CLKEN         LL_USART_ConfigSmartcardMode\n

+  *         CR3          HDSEL         LL_USART_ConfigSmartcardMode\n

+  *         CR3          SCEN          LL_USART_ConfigSmartcardMode

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx)

+{

+  /* In Smartcard mode, the following bits must be kept cleared:

+  - LINEN bit in the USART_CR2 register,

+  - IREN and HDSEL bits in the USART_CR3 register.

+  */

+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN));

+  CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));

+  /* Configure Stop bits to 1.5 bits */

+  /* Synchronous mode is activated by default */

+  SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN));

+  /* set the UART/USART in Smartcard mode */

+  SET_BIT(USARTx->CR3, USART_CR3_SCEN);

+}

+

+/**

+  * @brief  Perform basic configuration of USART for enabling use in Irda Mode

+  * @note   In IRDA mode, the following bits must be kept cleared:

+  *           - LINEN bit in the USART_CR2 register,

+  *           - STOP and CLKEN bits in the USART_CR2 register,

+  *           - SCEN bit in the USART_CR3 register,

+  *           - HDSEL bit in the USART_CR3 register.

+  *         This function also sets the UART/USART in IRDA mode (IREN bit).

+  * @note   Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not

+  *         IrDA feature is supported by the USARTx instance.

+  * @note   Call of this function is equivalent to following function call sequence :

+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function

+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function

+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function

+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function

+  *         - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function

+  *         - Set IREN in CR3 using @ref LL_USART_EnableIrda() function

+  * @note   Other remaining configurations items related to Irda Mode

+  *         (as Baud Rate, Word length, Power mode, ...) should be set using

+  *         dedicated functions

+  * @rmtoll CR2          LINEN         LL_USART_ConfigIrdaMode\n

+  *         CR2          CLKEN         LL_USART_ConfigIrdaMode\n

+  *         CR2          STOP          LL_USART_ConfigIrdaMode\n

+  *         CR3          SCEN          LL_USART_ConfigIrdaMode\n

+  *         CR3          HDSEL         LL_USART_ConfigIrdaMode\n

+  *         CR3          IREN          LL_USART_ConfigIrdaMode

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx)

+{

+  /* In IRDA mode, the following bits must be kept cleared:

+  - LINEN, STOP and CLKEN bits in the USART_CR2 register,

+  - SCEN and HDSEL bits in the USART_CR3 register.

+  */

+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP));

+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));

+  /* set the UART/USART in IRDA mode */

+  SET_BIT(USARTx->CR3, USART_CR3_IREN);

+}

+

+/**

+  * @brief  Perform basic configuration of USART for enabling use in Multi processor Mode

+  *         (several USARTs connected in a network, one of the USARTs can be the master,

+  *         its TX output connected to the RX inputs of the other slaves USARTs).

+  * @note   In MultiProcessor mode, the following bits must be kept cleared:

+  *           - LINEN bit in the USART_CR2 register,

+  *           - CLKEN bit in the USART_CR2 register,

+  *           - SCEN bit in the USART_CR3 register,

+  *           - IREN bit in the USART_CR3 register,

+  *           - HDSEL bit in the USART_CR3 register.

+  * @note   Call of this function is equivalent to following function call sequence :

+  *         - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function

+  *         - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function

+  *         - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function

+  *         - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function

+  *         - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function

+  * @note   Other remaining configurations items related to Multi processor Mode

+  *         (as Baud Rate, Wake Up Method, Node address, ...) should be set using

+  *         dedicated functions

+  * @rmtoll CR2          LINEN         LL_USART_ConfigMultiProcessMode\n

+  *         CR2          CLKEN         LL_USART_ConfigMultiProcessMode\n

+  *         CR3          SCEN          LL_USART_ConfigMultiProcessMode\n

+  *         CR3          HDSEL         LL_USART_ConfigMultiProcessMode\n

+  *         CR3          IREN          LL_USART_ConfigMultiProcessMode

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx)

+{

+  /* In Multi Processor mode, the following bits must be kept cleared:

+  - LINEN and CLKEN bits in the USART_CR2 register,

+  - IREN, SCEN and HDSEL bits in the USART_CR3 register.

+  */

+  CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN));

+  CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management

+  * @{

+  */

+

+/**

+  * @brief  Check if the USART Parity Error Flag is set or not

+  * @rmtoll ISR          PE            LL_USART_IsActiveFlag_PE

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART Framing Error Flag is set or not

+  * @rmtoll ISR          FE            LL_USART_IsActiveFlag_FE

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART Noise error detected Flag is set or not

+  * @rmtoll ISR          NE            LL_USART_IsActiveFlag_NE

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART OverRun Error Flag is set or not

+  * @rmtoll ISR          ORE           LL_USART_IsActiveFlag_ORE

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART IDLE line detected Flag is set or not

+  * @rmtoll ISR          IDLE          LL_USART_IsActiveFlag_IDLE

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL);

+}

+

+/* Legacy define */

+#define LL_USART_IsActiveFlag_RXNE  LL_USART_IsActiveFlag_RXNE_RXFNE

+

+/**

+  * @brief  Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll ISR          RXNE_RXFNE    LL_USART_IsActiveFlag_RXNE_RXFNE

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART Transmission Complete Flag is set or not

+  * @rmtoll ISR          TC            LL_USART_IsActiveFlag_TC

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL);

+}

+

+/* Legacy define */

+#define LL_USART_IsActiveFlag_TXE  LL_USART_IsActiveFlag_TXE_TXFNF

+

+/**

+  * @brief  Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll ISR          TXE_TXFNF     LL_USART_IsActiveFlag_TXE_TXFNF

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART LIN Break Detection Flag is set or not

+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not

+  *         LIN feature is supported by the USARTx instance.

+  * @rmtoll ISR          LBDF          LL_USART_IsActiveFlag_LBD

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART CTS interrupt Flag is set or not

+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not

+  *         Hardware Flow control feature is supported by the USARTx instance.

+  * @rmtoll ISR          CTSIF         LL_USART_IsActiveFlag_nCTS

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART CTS Flag is set or not

+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not

+  *         Hardware Flow control feature is supported by the USARTx instance.

+  * @rmtoll ISR          CTS           LL_USART_IsActiveFlag_CTS

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART Receiver Time Out Flag is set or not

+  * @rmtoll ISR          RTOF          LL_USART_IsActiveFlag_RTO

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART End Of Block Flag is set or not

+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not

+  *         Smartcard feature is supported by the USARTx instance.

+  * @rmtoll ISR          EOBF          LL_USART_IsActiveFlag_EOB

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the SPI Slave Underrun error flag is set or not

+  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not

+  *         SPI Slave mode feature is supported by the USARTx instance.

+  * @rmtoll ISR          UDR           LL_USART_IsActiveFlag_UDR

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART Auto-Baud Rate Error Flag is set or not

+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not

+  *         Auto Baud Rate detection feature is supported by the USARTx instance.

+  * @rmtoll ISR          ABRE          LL_USART_IsActiveFlag_ABRE

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART Auto-Baud Rate Flag is set or not

+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not

+  *         Auto Baud Rate detection feature is supported by the USARTx instance.

+  * @rmtoll ISR          ABRF          LL_USART_IsActiveFlag_ABR

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART Busy Flag is set or not

+  * @rmtoll ISR          BUSY          LL_USART_IsActiveFlag_BUSY

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART Character Match Flag is set or not

+  * @rmtoll ISR          CMF           LL_USART_IsActiveFlag_CM

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART Send Break Flag is set or not

+  * @rmtoll ISR          SBKF          LL_USART_IsActiveFlag_SBK

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART Receive Wake Up from mute mode Flag is set or not

+  * @rmtoll ISR          RWU           LL_USART_IsActiveFlag_RWU

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART Wake Up from stop mode Flag is set or not

+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not

+  *         Wake-up from Stop mode feature is supported by the USARTx instance.

+  * @rmtoll ISR          WUF           LL_USART_IsActiveFlag_WKUP

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_WKUP(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART Transmit Enable Acknowledge Flag is set or not

+  * @rmtoll ISR          TEACK         LL_USART_IsActiveFlag_TEACK

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART Receive Enable Acknowledge Flag is set or not

+  * @rmtoll ISR          REACK         LL_USART_IsActiveFlag_REACK

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART TX FIFO Empty Flag is set or not

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll ISR          TXFE          LL_USART_IsActiveFlag_TXFE

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART RX FIFO Full Flag is set or not

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll ISR          RXFF          LL_USART_IsActiveFlag_RXFF

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not

+  * @rmtoll ISR          TCBGT         LL_USART_IsActiveFlag_TCBGT

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART TX FIFO Threshold Flag is set or not

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll ISR          TXFT          LL_USART_IsActiveFlag_TXFT

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART RX FIFO Threshold Flag is set or not

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll ISR          RXFT          LL_USART_IsActiveFlag_RXFT

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear Parity Error Flag

+  * @rmtoll ICR          PECF          LL_USART_ClearFlag_PE

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx)

+{

+  WRITE_REG(USARTx->ICR, USART_ICR_PECF);

+}

+

+/**

+  * @brief  Clear Framing Error Flag

+  * @rmtoll ICR          FECF          LL_USART_ClearFlag_FE

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx)

+{

+  WRITE_REG(USARTx->ICR, USART_ICR_FECF);

+}

+

+/**

+  * @brief  Clear Noise Error detected Flag

+  * @rmtoll ICR          NECF          LL_USART_ClearFlag_NE

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx)

+{

+  WRITE_REG(USARTx->ICR, USART_ICR_NECF);

+}

+

+/**

+  * @brief  Clear OverRun Error Flag

+  * @rmtoll ICR          ORECF         LL_USART_ClearFlag_ORE

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx)

+{

+  WRITE_REG(USARTx->ICR, USART_ICR_ORECF);

+}

+

+/**

+  * @brief  Clear IDLE line detected Flag

+  * @rmtoll ICR          IDLECF        LL_USART_ClearFlag_IDLE

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx)

+{

+  WRITE_REG(USARTx->ICR, USART_ICR_IDLECF);

+}

+

+/**

+  * @brief  Clear TX FIFO Empty Flag

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll ICR          TXFECF        LL_USART_ClearFlag_TXFE

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx)

+{

+  WRITE_REG(USARTx->ICR, USART_ICR_TXFECF);

+}

+

+/**

+  * @brief  Clear Transmission Complete Flag

+  * @rmtoll ICR          TCCF          LL_USART_ClearFlag_TC

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx)

+{

+  WRITE_REG(USARTx->ICR, USART_ICR_TCCF);

+}

+

+/**

+  * @brief  Clear Smartcard Transmission Complete Before Guard Time Flag

+  * @rmtoll ICR          TCBGTCF       LL_USART_ClearFlag_TCBGT

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx)

+{

+  WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF);

+}

+

+/**

+  * @brief  Clear LIN Break Detection Flag

+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not

+  *         LIN feature is supported by the USARTx instance.

+  * @rmtoll ICR          LBDCF         LL_USART_ClearFlag_LBD

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx)

+{

+  WRITE_REG(USARTx->ICR, USART_ICR_LBDCF);

+}

+

+/**

+  * @brief  Clear CTS Interrupt Flag

+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not

+  *         Hardware Flow control feature is supported by the USARTx instance.

+  * @rmtoll ICR          CTSCF         LL_USART_ClearFlag_nCTS

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx)

+{

+  WRITE_REG(USARTx->ICR, USART_ICR_CTSCF);

+}

+

+/**

+  * @brief  Clear Receiver Time Out Flag

+  * @rmtoll ICR          RTOCF         LL_USART_ClearFlag_RTO

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx)

+{

+  WRITE_REG(USARTx->ICR, USART_ICR_RTOCF);

+}

+

+/**

+  * @brief  Clear End Of Block Flag

+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not

+  *         Smartcard feature is supported by the USARTx instance.

+  * @rmtoll ICR          EOBCF         LL_USART_ClearFlag_EOB

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx)

+{

+  WRITE_REG(USARTx->ICR, USART_ICR_EOBCF);

+}

+

+/**

+  * @brief  Clear SPI Slave Underrun Flag

+  * @note   Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not

+  *         SPI Slave mode feature is supported by the USARTx instance.

+  * @rmtoll ICR          UDRCF         LL_USART_ClearFlag_UDR

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx)

+{

+  WRITE_REG(USARTx->ICR, USART_ICR_UDRCF);

+}

+

+/**

+  * @brief  Clear Character Match Flag

+  * @rmtoll ICR          CMCF          LL_USART_ClearFlag_CM

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx)

+{

+  WRITE_REG(USARTx->ICR, USART_ICR_CMCF);

+}

+

+/**

+  * @brief  Clear Wake Up from stop mode Flag

+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not

+  *         Wake-up from Stop mode feature is supported by the USARTx instance.

+  * @rmtoll ICR          WUCF          LL_USART_ClearFlag_WKUP

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_ClearFlag_WKUP(USART_TypeDef *USARTx)

+{

+  WRITE_REG(USARTx->ICR, USART_ICR_WUCF);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EF_IT_Management IT_Management

+  * @{

+  */

+

+/**

+  * @brief  Enable IDLE Interrupt

+  * @rmtoll CR1          IDLEIE        LL_USART_EnableIT_IDLE

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR1, USART_CR1_IDLEIE);

+}

+

+/* Legacy define */

+#define LL_USART_EnableIT_RXNE  LL_USART_EnableIT_RXNE_RXFNE

+

+/**

+  * @brief  Enable RX Not Empty and RX FIFO Not Empty Interrupt

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_EnableIT_RXNE_RXFNE

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);

+}

+

+/**

+  * @brief  Enable Transmission Complete Interrupt

+  * @rmtoll CR1          TCIE          LL_USART_EnableIT_TC

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR1, USART_CR1_TCIE);

+}

+

+/* Legacy define */

+#define LL_USART_EnableIT_TXE  LL_USART_EnableIT_TXE_TXFNF

+

+/**

+  * @brief  Enable TX Empty and TX FIFO Not Full Interrupt

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_EnableIT_TXE_TXFNF

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);

+}

+

+/**

+  * @brief  Enable Parity Error Interrupt

+  * @rmtoll CR1          PEIE          LL_USART_EnableIT_PE

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR1, USART_CR1_PEIE);

+}

+

+/**

+  * @brief  Enable Character Match Interrupt

+  * @rmtoll CR1          CMIE          LL_USART_EnableIT_CM

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR1, USART_CR1_CMIE);

+}

+

+/**

+  * @brief  Enable Receiver Timeout Interrupt

+  * @rmtoll CR1          RTOIE         LL_USART_EnableIT_RTO

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR1, USART_CR1_RTOIE);

+}

+

+/**

+  * @brief  Enable End Of Block Interrupt

+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not

+  *         Smartcard feature is supported by the USARTx instance.

+  * @rmtoll CR1          EOBIE         LL_USART_EnableIT_EOB

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR1, USART_CR1_EOBIE);

+}

+

+/**

+  * @brief  Enable TX FIFO Empty Interrupt

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll CR1          TXFEIE        LL_USART_EnableIT_TXFE

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR1, USART_CR1_TXFEIE);

+}

+

+/**

+  * @brief  Enable RX FIFO Full Interrupt

+  * @rmtoll CR1          RXFFIE        LL_USART_EnableIT_RXFF

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR1, USART_CR1_RXFFIE);

+}

+

+/**

+  * @brief  Enable LIN Break Detection Interrupt

+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not

+  *         LIN feature is supported by the USARTx instance.

+  * @rmtoll CR2          LBDIE         LL_USART_EnableIT_LBD

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR2, USART_CR2_LBDIE);

+}

+

+/**

+  * @brief  Enable Error Interrupt

+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing

+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).

+  *           0: Interrupt is inhibited

+  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.

+  * @rmtoll CR3          EIE           LL_USART_EnableIT_ERROR

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR3, USART_CR3_EIE);

+}

+

+/**

+  * @brief  Enable CTS Interrupt

+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not

+  *         Hardware Flow control feature is supported by the USARTx instance.

+  * @rmtoll CR3          CTSIE         LL_USART_EnableIT_CTS

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR3, USART_CR3_CTSIE);

+}

+

+/**

+  * @brief  Enable Wake Up from Stop Mode Interrupt

+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not

+  *         Wake-up from Stop mode feature is supported by the USARTx instance.

+  * @rmtoll CR3          WUFIE         LL_USART_EnableIT_WKUP

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR3, USART_CR3_WUFIE);

+}

+

+/**

+  * @brief  Enable TX FIFO Threshold Interrupt

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll CR3          TXFTIE        LL_USART_EnableIT_TXFT

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR3, USART_CR3_TXFTIE);

+}

+

+/**

+  * @brief  Enable Smartcard Transmission Complete Before Guard Time Interrupt

+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not

+  *         Smartcard feature is supported by the USARTx instance.

+  * @rmtoll CR3          TCBGTIE       LL_USART_EnableIT_TCBGT

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE);

+}

+

+/**

+  * @brief  Enable RX FIFO Threshold Interrupt

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll CR3          RXFTIE        LL_USART_EnableIT_RXFT

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR3, USART_CR3_RXFTIE);

+}

+

+/**

+  * @brief  Disable IDLE Interrupt

+  * @rmtoll CR1          IDLEIE        LL_USART_DisableIT_IDLE

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE);

+}

+

+/* Legacy define */

+#define LL_USART_DisableIT_RXNE  LL_USART_DisableIT_RXNE_RXFNE

+

+/**

+  * @brief  Disable RX Not Empty and RX FIFO Not Empty Interrupt

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_DisableIT_RXNE_RXFNE

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE);

+}

+

+/**

+  * @brief  Disable Transmission Complete Interrupt

+  * @rmtoll CR1          TCIE          LL_USART_DisableIT_TC

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE);

+}

+

+/* Legacy define */

+#define LL_USART_DisableIT_TXE  LL_USART_DisableIT_TXE_TXFNF

+

+/**

+  * @brief  Disable TX Empty and TX FIFO Not Full Interrupt

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll CR1        TXEIE_TXFNFIE  LL_USART_DisableIT_TXE_TXFNF

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE);

+}

+

+/**

+  * @brief  Disable Parity Error Interrupt

+  * @rmtoll CR1          PEIE          LL_USART_DisableIT_PE

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE);

+}

+

+/**

+  * @brief  Disable Character Match Interrupt

+  * @rmtoll CR1          CMIE          LL_USART_DisableIT_CM

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE);

+}

+

+/**

+  * @brief  Disable Receiver Timeout Interrupt

+  * @rmtoll CR1          RTOIE         LL_USART_DisableIT_RTO

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE);

+}

+

+/**

+  * @brief  Disable End Of Block Interrupt

+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not

+  *         Smartcard feature is supported by the USARTx instance.

+  * @rmtoll CR1          EOBIE         LL_USART_DisableIT_EOB

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE);

+}

+

+/**

+  * @brief  Disable TX FIFO Empty Interrupt

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll CR1          TXFEIE        LL_USART_DisableIT_TXFE

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE);

+}

+

+/**

+  * @brief  Disable RX FIFO Full Interrupt

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll CR1          RXFFIE        LL_USART_DisableIT_RXFF

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE);

+}

+

+/**

+  * @brief  Disable LIN Break Detection Interrupt

+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not

+  *         LIN feature is supported by the USARTx instance.

+  * @rmtoll CR2          LBDIE         LL_USART_DisableIT_LBD

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE);

+}

+

+/**

+  * @brief  Disable Error Interrupt

+  * @note   When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing

+  *         error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register).

+  *           0: Interrupt is inhibited

+  *           1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register.

+  * @rmtoll CR3          EIE           LL_USART_DisableIT_ERROR

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR3, USART_CR3_EIE);

+}

+

+/**

+  * @brief  Disable CTS Interrupt

+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not

+  *         Hardware Flow control feature is supported by the USARTx instance.

+  * @rmtoll CR3          CTSIE         LL_USART_DisableIT_CTS

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE);

+}

+

+/**

+  * @brief  Disable Wake Up from Stop Mode Interrupt

+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not

+  *         Wake-up from Stop mode feature is supported by the USARTx instance.

+  * @rmtoll CR3          WUFIE         LL_USART_DisableIT_WKUP

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR3, USART_CR3_WUFIE);

+}

+

+/**

+  * @brief  Disable TX FIFO Threshold Interrupt

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll CR3          TXFTIE        LL_USART_DisableIT_TXFT

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE);

+}

+

+/**

+  * @brief  Disable Smartcard Transmission Complete Before Guard Time Interrupt

+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not

+  *         Smartcard feature is supported by the USARTx instance.

+  * @rmtoll CR3          TCBGTIE       LL_USART_DisableIT_TCBGT

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE);

+}

+

+/**

+  * @brief  Disable RX FIFO Threshold Interrupt

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll CR3          RXFTIE        LL_USART_DisableIT_RXFT

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE);

+}

+

+/**

+  * @brief  Check if the USART IDLE Interrupt  source is enabled or disabled.

+  * @rmtoll CR1          IDLEIE        LL_USART_IsEnabledIT_IDLE

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL);

+}

+

+/* Legacy define */

+#define LL_USART_IsEnabledIT_RXNE  LL_USART_IsEnabledIT_RXNE_RXFNE

+

+/**

+  * @brief  Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled.

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll CR1        RXNEIE_RXFNEIE  LL_USART_IsEnabledIT_RXNE_RXFNE

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART Transmission Complete Interrupt is enabled or disabled.

+  * @rmtoll CR1          TCIE          LL_USART_IsEnabledIT_TC

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL);

+}

+

+/* Legacy define */

+#define LL_USART_IsEnabledIT_TXE  LL_USART_IsEnabledIT_TXE_TXFNF

+

+/**

+  * @brief  Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll CR1         TXEIE_TXFNFIE  LL_USART_IsEnabledIT_TXE_TXFNF

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART Parity Error Interrupt is enabled or disabled.

+  * @rmtoll CR1          PEIE          LL_USART_IsEnabledIT_PE

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART Character Match Interrupt is enabled or disabled.

+  * @rmtoll CR1          CMIE          LL_USART_IsEnabledIT_CM

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART Receiver Timeout Interrupt is enabled or disabled.

+  * @rmtoll CR1          RTOIE         LL_USART_IsEnabledIT_RTO

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART End Of Block Interrupt is enabled or disabled.

+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not

+  *         Smartcard feature is supported by the USARTx instance.

+  * @rmtoll CR1          EOBIE         LL_USART_IsEnabledIT_EOB

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART TX FIFO Empty Interrupt is enabled or disabled

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll CR1          TXFEIE        LL_USART_IsEnabledIT_TXFE

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART RX FIFO Full Interrupt is enabled or disabled

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll CR1          RXFFIE        LL_USART_IsEnabledIT_RXFF

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART LIN Break Detection Interrupt is enabled or disabled.

+  * @note   Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not

+  *         LIN feature is supported by the USARTx instance.

+  * @rmtoll CR2          LBDIE         LL_USART_IsEnabledIT_LBD

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART Error Interrupt is enabled or disabled.

+  * @rmtoll CR3          EIE           LL_USART_IsEnabledIT_ERROR

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART CTS Interrupt is enabled or disabled.

+  * @note   Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not

+  *         Hardware Flow control feature is supported by the USARTx instance.

+  * @rmtoll CR3          CTSIE         LL_USART_IsEnabledIT_CTS

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled.

+  * @note   Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not

+  *         Wake-up from Stop mode feature is supported by the USARTx instance.

+  * @rmtoll CR3          WUFIE         LL_USART_IsEnabledIT_WKUP

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if USART TX FIFO Threshold Interrupt is enabled or disabled

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll CR3          TXFTIE        LL_USART_IsEnabledIT_TXFT

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled.

+  * @note   Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not

+  *         Smartcard feature is supported by the USARTx instance.

+  * @rmtoll CR3          TCBGTIE       LL_USART_IsEnabledIT_TCBGT

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Check if USART RX FIFO Threshold Interrupt is enabled or disabled

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll CR3          RXFTIE        LL_USART_IsEnabledIT_RXFT

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EF_DMA_Management DMA_Management

+  * @{

+  */

+

+/**

+  * @brief  Enable DMA Mode for reception

+  * @rmtoll CR3          DMAR          LL_USART_EnableDMAReq_RX

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR3, USART_CR3_DMAR);

+}

+

+/**

+  * @brief  Disable DMA Mode for reception

+  * @rmtoll CR3          DMAR          LL_USART_DisableDMAReq_RX

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR);

+}

+

+/**

+  * @brief  Check if DMA Mode is enabled for reception

+  * @rmtoll CR3          DMAR          LL_USART_IsEnabledDMAReq_RX

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable DMA Mode for transmission

+  * @rmtoll CR3          DMAT          LL_USART_EnableDMAReq_TX

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR3, USART_CR3_DMAT);

+}

+

+/**

+  * @brief  Disable DMA Mode for transmission

+  * @rmtoll CR3          DMAT          LL_USART_DisableDMAReq_TX

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT);

+}

+

+/**

+  * @brief  Check if DMA Mode is enabled for transmission

+  * @rmtoll CR3          DMAT          LL_USART_IsEnabledDMAReq_TX

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Enable DMA Disabling on Reception Error

+  * @rmtoll CR3          DDRE          LL_USART_EnableDMADeactOnRxErr

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->CR3, USART_CR3_DDRE);

+}

+

+/**

+  * @brief  Disable DMA Disabling on Reception Error

+  * @rmtoll CR3          DDRE          LL_USART_DisableDMADeactOnRxErr

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx)

+{

+  CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE);

+}

+

+/**

+  * @brief  Indicate if DMA Disabling on Reception Error is disabled

+  * @rmtoll CR3          DDRE          LL_USART_IsEnabledDMADeactOnRxErr

+  * @param  USARTx USART Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(USART_TypeDef *USARTx)

+{

+  return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Get the data register address used for DMA transfer

+  * @rmtoll RDR          RDR           LL_USART_DMA_GetRegAddr\n

+  * @rmtoll TDR          TDR           LL_USART_DMA_GetRegAddr

+  * @param  USARTx USART Instance

+  * @param  Direction This parameter can be one of the following values:

+  *         @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT

+  *         @arg @ref LL_USART_DMA_REG_DATA_RECEIVE

+  * @retval Address of data register

+  */

+__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx, uint32_t Direction)

+{

+  register uint32_t data_reg_addr;

+

+  if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT)

+  {

+    /* return address of TDR register */

+    data_reg_addr = (uint32_t) &(USARTx->TDR);

+  }

+  else

+  {

+    /* return address of RDR register */

+    data_reg_addr = (uint32_t) &(USARTx->RDR);

+  }

+

+  return data_reg_addr;

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EF_Data_Management Data_Management

+  * @{

+  */

+

+/**

+  * @brief  Read Receiver Data register (Receive Data value, 8 bits)

+  * @rmtoll RDR          RDR           LL_USART_ReceiveData8

+  * @param  USARTx USART Instance

+  * @retval Value between Min_Data=0x00 and Max_Data=0xFF

+  */

+__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx)

+{

+  return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU);

+}

+

+/**

+  * @brief  Read Receiver Data register (Receive Data value, 9 bits)

+  * @rmtoll RDR          RDR           LL_USART_ReceiveData9

+  * @param  USARTx USART Instance

+  * @retval Value between Min_Data=0x00 and Max_Data=0x1FF

+  */

+__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx)

+{

+  return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR));

+}

+

+/**

+  * @brief  Write in Transmitter Data Register (Transmit Data value, 8 bits)

+  * @rmtoll TDR          TDR           LL_USART_TransmitData8

+  * @param  USARTx USART Instance

+  * @param  Value between Min_Data=0x00 and Max_Data=0xFF

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value)

+{

+  USARTx->TDR = Value;

+}

+

+/**

+  * @brief  Write in Transmitter Data Register (Transmit Data value, 9 bits)

+  * @rmtoll TDR          TDR           LL_USART_TransmitData9

+  * @param  USARTx USART Instance

+  * @param  Value between Min_Data=0x00 and Max_Data=0x1FF

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value)

+{

+  USARTx->TDR = (uint16_t)(Value & 0x1FFUL);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup USART_LL_EF_Execution Execution

+  * @{

+  */

+

+/**

+  * @brief  Request an Automatic Baud Rate measurement on next received data frame

+  * @note   Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not

+  *         Auto Baud Rate detection feature is supported by the USARTx instance.

+  * @rmtoll RQR          ABRRQ         LL_USART_RequestAutoBaudRate

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ);

+}

+

+/**

+  * @brief  Request Break sending

+  * @rmtoll RQR          SBKRQ         LL_USART_RequestBreakSending

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ);

+}

+

+/**

+  * @brief  Put USART in mute mode and set the RWU flag

+  * @rmtoll RQR          MMRQ          LL_USART_RequestEnterMuteMode

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ);

+}

+

+/**

+  * @brief  Request a Receive Data and FIFO flush

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @note   Allows to discard the received data without reading them, and avoid an overrun

+  *         condition.

+  * @rmtoll RQR          RXFRQ         LL_USART_RequestRxDataFlush

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ);

+}

+

+/**

+  * @brief  Request a Transmit data and FIFO flush

+  * @note   Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not

+  *         FIFO mode feature is supported by the USARTx instance.

+  * @rmtoll RQR          TXFRQ         LL_USART_RequestTxDataFlush

+  * @param  USARTx USART Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx)

+{

+  SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ);

+}

+

+/**

+  * @}

+  */

+

+#if defined(USE_FULL_LL_DRIVER)

+/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions

+  * @{

+  */

+ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx);

+ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct);

+void        LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct);

+ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct);

+void        LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct);

+/**

+  * @}

+  */

+#endif /* USE_FULL_LL_DRIVER */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* USART1 || USART2 || USART3 || USART6 || UART4 || UART5 || UART7 || UART8 || UART9 || USART10 */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_LL_USART_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_usb.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_usb.h
new file mode 100644
index 0000000000..503b12f3e3
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_usb.h
@@ -0,0 +1,510 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_usb.h

+  * @author  MCD Application Team

+  * @brief   Header file of USB Low Layer HAL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_LL_USB_H

+#define STM32H7xx_LL_USB_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx_hal_def.h"

+

+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)

+/** @addtogroup STM32H7xx_HAL_Driver

+  * @{

+  */

+

+/** @addtogroup USB_LL

+  * @{

+  */

+

+/* Exported types ------------------------------------------------------------*/

+

+/**

+  * @brief  USB Mode definition

+  */

+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)

+

+typedef enum

+{

+  USB_DEVICE_MODE  = 0,

+  USB_HOST_MODE    = 1,

+  USB_DRD_MODE     = 2

+} USB_OTG_ModeTypeDef;

+

+/**

+  * @brief  URB States definition

+  */

+typedef enum

+{

+  URB_IDLE = 0,

+  URB_DONE,

+  URB_NOTREADY,

+  URB_NYET,

+  URB_ERROR,

+  URB_STALL

+} USB_OTG_URBStateTypeDef;

+

+/**

+  * @brief  Host channel States  definition

+  */

+typedef enum

+{

+  HC_IDLE = 0,

+  HC_XFRC,

+  HC_HALTED,

+  HC_NAK,

+  HC_NYET,

+  HC_STALL,

+  HC_XACTERR,

+  HC_BBLERR,

+  HC_DATATGLERR

+} USB_OTG_HCStateTypeDef;

+

+/**

+  * @brief  USB OTG Initialization Structure definition

+  */

+typedef struct

+{

+  uint32_t dev_endpoints;           /*!< Device Endpoints number.

+                                         This parameter depends on the used USB core.

+                                         This parameter must be a number between Min_Data = 1 and Max_Data = 15 */

+

+  uint32_t Host_channels;           /*!< Host Channels number.

+                                         This parameter Depends on the used USB core.

+                                         This parameter must be a number between Min_Data = 1 and Max_Data = 15 */

+

+  uint32_t speed;                   /*!< USB Core speed.

+                                         This parameter can be any value of @ref USB_Core_Speed_                */

+

+  uint32_t dma_enable;              /*!< Enable or disable of the USB embedded DMA used only for OTG HS.        */

+

+  uint32_t ep0_mps;                 /*!< Set the Endpoint 0 Max Packet size.                                    */

+

+  uint32_t phy_itface;              /*!< Select the used PHY interface.

+                                         This parameter can be any value of @ref USB_Core_PHY_                  */

+

+  uint32_t Sof_enable;              /*!< Enable or disable the output of the SOF signal.                        */

+

+  uint32_t low_power_enable;        /*!< Enable or disable the low power mode.                                  */

+

+  uint32_t lpm_enable;              /*!< Enable or disable Link Power Management.                               */

+

+  uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.                                    */

+

+  uint32_t vbus_sensing_enable;     /*!< Enable or disable the VBUS Sensing feature.                            */

+

+  uint32_t use_dedicated_ep1;       /*!< Enable or disable the use of the dedicated EP1 interrupt.              */

+

+  uint32_t use_external_vbus;       /*!< Enable or disable the use of the external VBUS.                        */

+} USB_OTG_CfgTypeDef;

+

+typedef struct

+{

+  uint8_t   num;                  /*!< Endpoint number

+                                       This parameter must be a number between Min_Data = 1 and Max_Data = 15   */

+

+  uint8_t   is_in;                /*!< Endpoint direction

+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */

+

+  uint8_t   is_stall;             /*!< Endpoint stall condition

+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */

+

+  uint8_t   type;                 /*!< Endpoint type

+                                       This parameter can be any value of @ref USB_EP_Type_                     */

+

+  uint8_t   data_pid_start;       /*!< Initial data PID

+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */

+

+  uint8_t   even_odd_frame;       /*!< IFrame parity

+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 1    */

+

+  uint16_t  tx_fifo_num;          /*!< Transmission FIFO number

+                                       This parameter must be a number between Min_Data = 1 and Max_Data = 15   */

+

+  uint32_t  maxpacket;            /*!< Endpoint Max packet size

+                                       This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */

+

+  uint8_t   *xfer_buff;           /*!< Pointer to transfer buffer                                               */

+

+  uint32_t  dma_addr;             /*!< 32 bits aligned transfer buffer address                                  */

+

+  uint32_t  xfer_len;             /*!< Current transfer length                                                  */

+

+  uint32_t  xfer_count;           /*!< Partial transfer length in case of multi packet transfer                 */

+} USB_OTG_EPTypeDef;

+

+typedef struct

+{

+  uint8_t   dev_addr ;          /*!< USB device address.

+                                     This parameter must be a number between Min_Data = 1 and Max_Data = 255    */

+

+  uint8_t   ch_num;             /*!< Host channel number.

+                                     This parameter must be a number between Min_Data = 1 and Max_Data = 15     */

+

+  uint8_t   ep_num;             /*!< Endpoint number.

+                                     This parameter must be a number between Min_Data = 1 and Max_Data = 15     */

+

+  uint8_t   ep_is_in;           /*!< Endpoint direction

+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */

+

+  uint8_t   speed;              /*!< USB Host speed.

+                                     This parameter can be any value of @ref USB_Core_Speed_                    */

+

+  uint8_t   do_ping;            /*!< Enable or disable the use of the PING protocol for HS mode.                */

+

+  uint8_t   process_ping;       /*!< Execute the PING protocol for HS mode.                                     */

+

+  uint8_t   ep_type;            /*!< Endpoint Type.

+                                     This parameter can be any value of @ref USB_EP_Type_                       */

+

+  uint16_t  max_packet;         /*!< Endpoint Max packet size.

+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 64KB   */

+

+  uint8_t   data_pid;           /*!< Initial data PID.

+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */

+

+  uint8_t   *xfer_buff;         /*!< Pointer to transfer buffer.                                                */

+

+  uint32_t  xfer_len;           /*!< Current transfer length.                                                   */

+

+  uint32_t  xfer_count;         /*!< Partial transfer length in case of multi packet transfer.                  */

+

+  uint8_t   toggle_in;          /*!< IN transfer current toggle flag.

+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */

+

+  uint8_t   toggle_out;         /*!< OUT transfer current toggle flag

+                                     This parameter must be a number between Min_Data = 0 and Max_Data = 1      */

+

+  uint32_t  dma_addr;           /*!< 32 bits aligned transfer buffer address.                                   */

+

+  uint32_t  ErrCnt;             /*!< Host channel error count.*/

+

+  USB_OTG_URBStateTypeDef  urb_state;  /*!< URB state.

+                                            This parameter can be any value of @ref USB_OTG_URBStateTypeDef */

+

+  USB_OTG_HCStateTypeDef   state;     /*!< Host Channel state.

+                                           This parameter can be any value of @ref USB_OTG_HCStateTypeDef   */

+} USB_OTG_HCTypeDef;

+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */

+

+

+/* Exported constants --------------------------------------------------------*/

+

+/** @defgroup PCD_Exported_Constants PCD Exported Constants

+  * @{

+  */

+

+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)

+/** @defgroup USB_OTG_CORE VERSION ID

+  * @{

+  */

+#define USB_OTG_CORE_ID_300A          0x4F54300AU

+#define USB_OTG_CORE_ID_310A          0x4F54310AU

+/**

+  * @}

+  */

+

+/** @defgroup USB_Core_Mode_ USB Core Mode

+  * @{

+  */

+#define USB_OTG_MODE_DEVICE                    0U

+#define USB_OTG_MODE_HOST                      1U

+#define USB_OTG_MODE_DRD                       2U

+/**

+  * @}

+  */

+

+/** @defgroup USB_LL Device Speed

+  * @{

+  */

+#define USBD_HS_SPEED               0U

+#define USBD_HSINFS_SPEED           1U

+#define USBH_HS_SPEED               0U

+#define USBD_FS_SPEED               2U

+#define USBH_FS_SPEED               1U

+/**

+  * @}

+  */

+

+/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed

+  * @{

+  */

+#define USB_OTG_SPEED_HIGH                     0U

+#define USB_OTG_SPEED_HIGH_IN_FULL             1U

+#define USB_OTG_SPEED_FULL                     3U

+/**

+  * @}

+  */

+

+/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY

+  * @{

+  */

+#define USB_OTG_ULPI_PHY                       1U

+#define USB_OTG_EMBEDDED_PHY                   2U

+/**

+  * @}

+  */

+

+/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value

+  * @{

+  */

+#ifndef USBD_HS_TRDT_VALUE

+#define USBD_HS_TRDT_VALUE           9U

+#endif /* USBD_HS_TRDT_VALUE */

+#ifndef USBD_FS_TRDT_VALUE

+#define USBD_FS_TRDT_VALUE           5U

+#define USBD_DEFAULT_TRDT_VALUE      9U

+#endif /* USBD_HS_TRDT_VALUE */

+/**

+  * @}

+  */

+

+/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS

+  * @{

+  */

+#define USB_OTG_HS_MAX_PACKET_SIZE             512U

+#define USB_OTG_FS_MAX_PACKET_SIZE             64U

+#define USB_OTG_MAX_EP0_SIZE                   64U

+/**

+  * @}

+  */

+

+/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency

+  * @{

+  */

+#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ     (0U << 1)

+#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ     (1U << 1)

+#define DSTS_ENUMSPD_FS_PHY_48MHZ              (3U << 1)

+/**

+  * @}

+  */

+

+/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval

+  * @{

+  */

+#define DCFG_FRAME_INTERVAL_80                 0U

+#define DCFG_FRAME_INTERVAL_85                 1U

+#define DCFG_FRAME_INTERVAL_90                 2U

+#define DCFG_FRAME_INTERVAL_95                 3U

+/**

+  * @}

+  */

+

+/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS

+  * @{

+  */

+#define DEP0CTL_MPS_64                         0U

+#define DEP0CTL_MPS_32                         1U

+#define DEP0CTL_MPS_16                         2U

+#define DEP0CTL_MPS_8                          3U

+/**

+  * @}

+  */

+

+/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed

+  * @{

+  */

+#define EP_SPEED_LOW                           0U

+#define EP_SPEED_FULL                          1U

+#define EP_SPEED_HIGH                          2U

+/**

+  * @}

+  */

+

+/** @defgroup USB_LL_EP_Type USB Low Layer EP Type

+  * @{

+  */

+#define EP_TYPE_CTRL                           0U

+#define EP_TYPE_ISOC                           1U

+#define EP_TYPE_BULK                           2U

+#define EP_TYPE_INTR                           3U

+#define EP_TYPE_MSK                            3U

+/**

+  * @}

+  */

+

+/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines

+  * @{

+  */

+#define STS_GOUT_NAK                           1U

+#define STS_DATA_UPDT                          2U

+#define STS_XFER_COMP                          3U

+#define STS_SETUP_COMP                         4U

+#define STS_SETUP_UPDT                         6U

+/**

+  * @}

+  */

+

+/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines

+  * @{

+  */

+#define HCFG_30_60_MHZ                         0U

+#define HCFG_48_MHZ                            1U

+#define HCFG_6_MHZ                             2U

+/**

+  * @}

+  */

+

+/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines

+  * @{

+  */

+#define HPRT0_PRTSPD_HIGH_SPEED                0U

+#define HPRT0_PRTSPD_FULL_SPEED                1U

+#define HPRT0_PRTSPD_LOW_SPEED                 2U

+/**

+  * @}

+  */

+

+#define HCCHAR_CTRL                            0U

+#define HCCHAR_ISOC                            1U

+#define HCCHAR_BULK                            2U

+#define HCCHAR_INTR                            3U

+

+#define HC_PID_DATA0                           0U

+#define HC_PID_DATA2                           1U

+#define HC_PID_DATA1                           2U

+#define HC_PID_SETUP                           3U

+

+#define GRXSTS_PKTSTS_IN                       2U

+#define GRXSTS_PKTSTS_IN_XFER_COMP             3U

+#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR          5U

+#define GRXSTS_PKTSTS_CH_HALTED                7U

+

+#define USBx_PCGCCTL    *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE)

+#define USBx_HPRT0      *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE)

+

+#define USBx_DEVICE     ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE))

+#define USBx_INEP(i)    ((USB_OTG_INEndpointTypeDef *)(USBx_BASE + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))

+#define USBx_OUTEP(i)   ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE)))

+#define USBx_DFIFO(i)   *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE))

+

+#define USBx_HOST       ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE))

+#define USBx_HC(i)      ((USB_OTG_HostChannelTypeDef *)(USBx_BASE + USB_OTG_HOST_CHANNEL_BASE + ((i) * USB_OTG_HOST_CHANNEL_SIZE)))

+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */

+

+#define EP_ADDR_MSK                            0xFU

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros

+  * @{

+  */

+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)

+#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)     ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__))

+#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__)   ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__))

+

+#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__)          (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__))

+#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__)         (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__))

+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions

+  * @{

+  */

+#if defined (USB_OTG_FS) || defined (USB_OTG_HS)

+HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);

+HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);

+HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx);

+HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx);

+HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed);

+HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode);

+HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx, uint8_t speed);

+HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx);

+HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num);

+HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);

+HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);

+HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);

+HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);

+HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);

+HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma);

+HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma);

+void             *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len);

+HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);

+HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep);

+HAL_StatusTypeDef USB_SetDevAddress(USB_OTG_GlobalTypeDef *USBx, uint8_t address);

+HAL_StatusTypeDef USB_DevConnect(USB_OTG_GlobalTypeDef *USBx);

+HAL_StatusTypeDef USB_DevDisconnect(USB_OTG_GlobalTypeDef *USBx);

+HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx);

+HAL_StatusTypeDef USB_ActivateSetup(USB_OTG_GlobalTypeDef *USBx);

+HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup);

+uint8_t           USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx);

+uint32_t          USB_GetMode(USB_OTG_GlobalTypeDef *USBx);

+uint32_t          USB_ReadInterrupts(USB_OTG_GlobalTypeDef *USBx);

+uint32_t          USB_ReadDevAllOutEpInterrupt(USB_OTG_GlobalTypeDef *USBx);

+uint32_t          USB_ReadDevOutEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);

+uint32_t          USB_ReadDevAllInEpInterrupt(USB_OTG_GlobalTypeDef *USBx);

+uint32_t          USB_ReadDevInEPInterrupt(USB_OTG_GlobalTypeDef *USBx, uint8_t epnum);

+void              USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt);

+

+HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg);

+HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx, uint8_t freq);

+HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx);

+HAL_StatusTypeDef USB_DriveVbus(USB_OTG_GlobalTypeDef *USBx, uint8_t state);

+uint32_t          USB_GetHostSpeed(USB_OTG_GlobalTypeDef *USBx);

+uint32_t          USB_GetCurrentFrame(USB_OTG_GlobalTypeDef *USBx);

+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,

+                              uint8_t ch_num,

+                              uint8_t epnum,

+                              uint8_t dev_address,

+                              uint8_t speed,

+                              uint8_t ep_type,

+                              uint16_t mps);

+HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma);

+uint32_t          USB_HC_ReadInterrupt(USB_OTG_GlobalTypeDef *USBx);

+HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num);

+HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num);

+HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx);

+HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);

+HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_OTG_GlobalTypeDef *USBx);

+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */

+

+#ifdef __cplusplus

+}

+#endif

+

+

+#endif /* STM32H7xx_LL_USB_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_utils.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_utils.h
new file mode 100644
index 0000000000..ca336c268f
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_utils.h
@@ -0,0 +1,382 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_utils.h

+  * @author  MCD Application Team

+  * @brief   Header file of UTILS LL module.

+  @verbatim

+  ==============================================================================

+                     ##### How to use this driver #####

+  ==============================================================================

+    [..]

+    The LL UTILS driver contains a set of generic APIs that can be

+    used by user:

+      (+) Device electronic signature

+      (+) Timing functions

+      (+) PLL configuration functions

+

+  @endverbatim

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_LL_UTILS_H

+#define STM32H7xx_LL_UTILS_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+#include "stm32h7xx_ll_system.h"

+#include "stm32h7xx_ll_bus.h"

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+/** @defgroup UTILS_LL UTILS

+  * @{

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+

+/* Private constants ---------------------------------------------------------*/

+/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants

+  * @{

+  */

+

+/* Max delay can be used in LL_mDelay */

+#define LL_MAX_DELAY                  0xFFFFFFFFU

+

+/**

+ * @brief Unique device ID register base address

+ */

+#define UID_BASE_ADDRESS              UID_BASE

+

+/**

+ * @brief Flash size data register base address

+ */

+#define FLASHSIZE_BASE_ADDRESS        FLASHSIZE_BASE

+

+/**

+ * @brief Package data register base address

+ */

+#define PACKAGE_BASE_ADDRESS          PACKAGE_BASE

+

+/**

+  * @}

+  */

+

+/* Private macros ------------------------------------------------------------*/

+/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros

+  * @{

+  */

+/**

+  * @}

+  */

+/* Exported types ------------------------------------------------------------*/

+/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures

+  * @{

+  */

+/**

+  * @brief  UTILS PLL structure definition

+  */

+typedef struct

+{

+  uint32_t PLLM;   /*!< Division factor for PLL VCO input clock.

+                        This parameter must be a number between Min_Data = 0 and Max_Data = 63

+

+                        This feature can be modified afterwards using unitary function

+                        @ref LL_RCC_PLL1_SetM(). */

+

+  uint32_t PLLN;   /*!< Multiplication factor for PLL VCO output clock.

+                        This parameter must be a number between Min_Data = 4 and Max_Data = 512

+

+                        This feature can be modified afterwards using unitary function

+                        @ref LL_RCC_PLL1_SetN(). */

+

+  uint32_t PLLP;   /*!< Division for the main system clock.

+                        This parameter must be a number between Min_Data = 2 and Max_Data = 128

+                          odd division factors are not allowed

+

+                        This feature can be modified afterwards using unitary function

+                        @ref LL_RCC_PLL1_SetP(). */

+

+  uint32_t FRACN;  /*!< Fractional part of the multiplication factor for PLL VCO.

+                        This parameter can be a value between 0 and 8191

+

+                        This feature can be modified afterwards using unitary function

+                        @ref LL_RCC_PLL1_SetFRACN(). */

+

+  uint32_t VCO_Input;  /*!< PLL clock Input range.

+                        This parameter can be a value of @ref RCC_LL_EC_PLLINPUTRANGE

+

+                        This feature can be modified afterwards using unitary function

+                        @ref LL_RCC_PLL1_SetVCOInputRange(). */

+

+  uint32_t VCO_Output;  /*!< PLL clock Output range.

+                        This parameter can be a value of @ref RCC_LL_EC_PLLVCORANGE

+

+                      This feature can be modified afterwards using unitary function

+                      @ref LL_RCC_PLL1_SetVCOOutputRange(). */

+

+} LL_UTILS_PLLInitTypeDef;

+

+/**

+  * @brief  UTILS System, AHB and APB buses clock configuration structure definition

+  */

+typedef struct

+{

+  uint32_t SYSCLKDivider;         /*!< The System clock (SYSCLK) divider. This clock is derived from the PLL output.

+                                     This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV

+

+                                     This feature can be modified afterwards using unitary function

+                                     @ref LL_RCC_SetSysPrescaler(). */

+

+  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).

+                                       This parameter can be a value of @ref RCC_LL_EC_AHB_DIV

+

+                                       This feature can be modified afterwards using unitary function

+                                       @ref LL_RCC_SetAHBPrescaler(). */

+

+  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).

+                                       This parameter can be a value of @ref RCC_LL_EC_APB1_DIV

+

+                                       This feature can be modified afterwards using unitary function

+                                       @ref LL_RCC_SetAPB1Prescaler(). */

+

+  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).

+                                       This parameter can be a value of @ref RCC_LL_EC_APB2_DIV

+

+                                       This feature can be modified afterwards using unitary function

+                                       @ref LL_RCC_SetAPB2Prescaler(). */

+

+  uint32_t APB3CLKDivider;        /*!< The APB2 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK).

+                                       This parameter can be a value of @ref RCC_LL_EC_APB3_DIV

+

+                                       This feature can be modified afterwards using unitary function

+                                       @ref LL_RCC_SetAPB3Prescaler(). */

+

+  uint32_t APB4CLKDivider;        /*!< The APB4 clock (PCLK4) divider. This clock is derived from the AHB clock (HCLK).

+                                       This parameter can be a value of @ref RCC_LL_EC_APB4_DIV

+

+                                       This feature can be modified afterwards using unitary function

+                                       @ref LL_RCC_SetAPB4Prescaler(). */

+

+} LL_UTILS_ClkInitTypeDef;

+

+/**

+  * @}

+  */

+

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants

+  * @{

+  */

+

+/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation

+  * @{

+  */

+#define LL_UTILS_HSEBYPASS_OFF        0x00000000U       /*!< HSE Bypass is not enabled                */

+#define LL_UTILS_HSEBYPASS_ON         0x00000001U       /*!< HSE Bypass is enabled                    */

+/**

+  * @}

+  */

+

+/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE

+  * @{

+  */

+#if defined(SYSCFG_PKGR_PKG)

+#define LL_UTILS_PACKAGETYPE_LQFP100            LL_SYSCFG_LQFP100_PACKAGE          /*!< LQFP100 package type             */

+#define LL_UTILS_PACKAGETYPE_TQFP144            LL_SYSCFG_TQFP144_PACKAGE          /*!< TQFP144 package type             */

+#define LL_UTILS_PACKAGETYPE_TQFP176_UFBGA176   LL_SYSCFG_TQFP176_UFBGA176_PACKAGE /*!< TQFP176 or UFBGA176 package type */

+#define LL_UTILS_PACKAGETYPE_LQFP208_TFBGA240   LL_SYSCFG_LQFP208_TFBGA240_PACKAGE /*!< LQFP208 or TFBGA240 package type */

+#else

+#define LL_UTILS_PACKAGETYPE_LQFP64                  0x00000000UL                  /*!< LQFP64 package type              */

+#define LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100        0x00000001UL                  /*!< TFBGA100 or LQFP100 package type */

+#define LL_UTILS_PACKAGETYPE_LQFP100_SMPS            0x00000002UL                  /*!< LQFP100  with SMPS package type  */

+#define LL_UTILS_PACKAGETYPE_TFBGA100_SMPS           0x00000003UL                  /*!< TFBGA100 with SMPS package type  */

+#define LL_UTILS_PACKAGETYPE_WLCSP132_SMPS           0x00000004UL                  /*!< WLCSP132 package type            */

+#define LL_UTILS_PACKAGETYPE_LQFP144                 0x00000005UL                  /*!< LQFP144 package type             */

+#define LL_UTILS_PACKAGETYPE_LQFP144_SMPS            0x00000006UL                  /*!< LQFP144 with SMPS package type   */

+#define LL_UTILS_PACKAGETYPE_UFBGA169                0x00000007UL                  /*!< UFBGA169 package type            */

+#define LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176        0x00000008UL                  /*!< UFBGA176 or LQFP176 package type */

+#define LL_UTILS_PACKAGETYPE_LQFP176_SMPS            0x00000009UL                  /*!< LQFP176 with SMPS package type   */

+#define LL_UTILS_PACKAGETYPE_UFBGA176_SMPS           0x0000000AUL                  /*!< UFBGA176 with SMPS package type  */

+#define LL_UTILS_PACKAGETYPE_TFBGA216                0x0000000CUL                  /*!< TFBGA216  package type           */

+#define LL_UTILS_PACKAGETYPE_TFBGA225                0x0000000EUL                  /*!< TFBGA225  package type           */

+#endif /* SYSCFG_PKGR_PKG */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions

+  * @{

+  */

+

+/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE

+  * @{

+  */

+

+/**

+  * @brief  Get Word0 of the unique device identifier (UID based on 96 bits)

+  * @retval UID[31:0]

+  */

+__STATIC_INLINE uint32_t LL_GetUID_Word0(void)

+{

+  return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS)));

+}

+

+/**

+  * @brief  Get Word1 of the unique device identifier (UID based on 96 bits)

+  * @retval UID[63:32]

+  */

+__STATIC_INLINE uint32_t LL_GetUID_Word1(void)

+{

+  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U))));

+}

+

+/**

+  * @brief  Get Word2 of the unique device identifier (UID based on 96 bits)

+  * @retval UID[95:64]

+  */

+__STATIC_INLINE uint32_t LL_GetUID_Word2(void)

+{

+  return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U))));

+}

+

+/**

+  * @brief  Get Flash memory size

+  * @note   This bitfield indicates the size of the device Flash memory expressed in

+  *         Kbytes. As an example, 0x040 corresponds to 64 Kbytes.

+  * @retval FLASH_SIZE[15:0]: Flash memory size

+  */

+__STATIC_INLINE uint32_t LL_GetFlashSize(void)

+{

+  return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));

+}

+

+/**

+  * @brief  Get Package type

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP100

+  *         @arg @ref LL_UTILS_PACKAGETYPE_TQFP144

+  *         @arg @ref LL_UTILS_PACKAGETYPE_TQFP176_UFBGA176

+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP208_TFBGA240

+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP64 (*)

+  *         @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_LQFP100  (*)

+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_SMPS  (*)

+  *         @arg @ref LL_UTILS_PACKAGETYPE_TFBGA100_SMPS  (*)

+  *         @arg @ref LL_UTILS_PACKAGETYPE_WLCSP132_SMPS  (*)

+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP144     (*)

+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_SMPS (*)

+  *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169  (*)

+  *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_LQFP176  (*)

+  *         @arg @ref LL_UTILS_PACKAGETYPE_LQFP176_SMPS    (*)

+  *         @arg @ref LL_UTILS_PACKAGETYPE_UFBGA176_SMPS   (*)

+  *         @arg @ref LL_UTILS_PACKAGETYPE_TFBGA216   (*)

+  *         @arg @ref LL_UTILS_PACKAGETYPE_TFBGA225   (*)

+  *

+  *        (*) Packages available on some STM32H7 lines only.

+  * @note   For some SM32H7 lines, enabling the SYSCFG clock is mandatory.

+            the SYSCFG clock enabling is ensured by LL_APB4_GRP1_EnableClock

+  */

+__STATIC_INLINE uint32_t LL_GetPackageType(void)

+{

+#if defined(SYSCFG_PKGR_PKG)

+

+  return LL_SYSCFG_GetPackage();

+#else

+   return (uint16_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)));

+

+#endif  /* SYSCFG_PKGR_PKG */

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup UTILS_LL_EF_DELAY DELAY

+  * @{

+  */

+

+/**

+  * @brief  This function configures the Cortex-M SysTick source of the time base.

+  * @param  HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)

+  * @note   When a RTOS is used, it is recommended to avoid changing the SysTick

+  *         configuration by calling this function, for a delay use rather osDelay RTOS service.

+  * @param  Ticks Number of ticks

+  * @retval None

+  */

+__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)

+{

+  /* Configure the SysTick to have interrupt in 1ms time base */

+  SysTick->LOAD  = (uint32_t)((HCLKFrequency / Ticks) - 1UL);  /* set reload register */

+  SysTick->VAL   = 0UL;                                       /* Load the SysTick Counter Value */

+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |

+                   SysTick_CTRL_ENABLE_Msk;                   /* Enable the Systick Timer */

+}

+

+void        LL_Init1msTick(uint32_t CPU_Frequency);

+void        LL_mDelay(uint32_t Delay);

+

+/**

+  * @}

+  */

+

+/** @defgroup UTILS_EF_SYSTEM SYSTEM

+  * @{

+  */

+

+void        LL_SetSystemCoreClock(uint32_t CPU_Frequency);

+ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,

+                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);

+ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency,

+                                         uint32_t HSEBypass,

+                                         LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct,

+                                         LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct);

+ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency);

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_LL_UTILS_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/stm32h7xx_ll_wwdg.h b/bsps/arm/stm32h7/include/stm32h7xx_ll_wwdg.h
new file mode 100644
index 0000000000..bc36ed88a1
--- /dev/null
+++ b/bsps/arm/stm32h7/include/stm32h7xx_ll_wwdg.h
@@ -0,0 +1,331 @@
+/**

+  ******************************************************************************

+  * @file    stm32h7xx_ll_wwdg.h

+  * @author  MCD Application Team

+  * @brief   Header file of WWDG LL module.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/* Define to prevent recursive inclusion -------------------------------------*/

+#ifndef STM32H7xx_LL_WWDG_H

+#define STM32H7xx_LL_WWDG_H

+

+#ifdef __cplusplus

+extern "C" {

+#endif

+

+/* Includes ------------------------------------------------------------------*/

+#include "stm32h7xx.h"

+

+/** @addtogroup STM32H7xx_LL_Driver

+  * @{

+  */

+

+#if defined (WWDG1) || defined (WWDG2)

+

+/** @defgroup WWDG_LL WWDG

+  * @{

+  */

+

+/* Private types -------------------------------------------------------------*/

+/* Private variables ---------------------------------------------------------*/

+/* Private constants ---------------------------------------------------------*/

+/* Private macros ------------------------------------------------------------*/

+/* Exported types ------------------------------------------------------------*/

+/* Exported constants --------------------------------------------------------*/

+/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants

+  * @{

+  */

+

+/** @defgroup WWDG_LL_EC_IT IT Defines

+  * @brief    IT defines which can be used with LL_WWDG_ReadReg and  LL_WWDG_WriteReg functions

+  * @{

+  */

+#define LL_WWDG_CFR_EWI                     WWDG_CFR_EWI

+/**

+  * @}

+  */

+

+/** @defgroup WWDG_LL_EC_PRESCALER  PRESCALER

+  * @{

+  */

+#define LL_WWDG_PRESCALER_1                 0x00000000u                                               /*!< WWDG counter clock = (PCLK1/4096)/1 */

+#define LL_WWDG_PRESCALER_2                 WWDG_CFR_WDGTB_0                                          /*!< WWDG counter clock = (PCLK1/4096)/2 */

+#define LL_WWDG_PRESCALER_4                 WWDG_CFR_WDGTB_1                                          /*!< WWDG counter clock = (PCLK1/4096)/4 */

+#define LL_WWDG_PRESCALER_8                 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1)                     /*!< WWDG counter clock = (PCLK1/4096)/8 */

+#define LL_WWDG_PRESCALER_16                WWDG_CFR_WDGTB_2                                          /*!< WWDG counter clock = (PCLK1/4096)/16 */

+#define LL_WWDG_PRESCALER_32                (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_0)                     /*!< WWDG counter clock = (PCLK1/4096)/32 */

+#define LL_WWDG_PRESCALER_64                (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1)                     /*!< WWDG counter clock = (PCLK1/4096)/64 */

+#define LL_WWDG_PRESCALER_128               (WWDG_CFR_WDGTB_2 | WWDG_CFR_WDGTB_1 | WWDG_CFR_WDGTB_0)  /*!< WWDG counter clock = (PCLK1/4096)/128 */

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported macro ------------------------------------------------------------*/

+/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros

+  * @{

+  */

+/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros

+  * @{

+  */

+/**

+  * @brief  Write a value in WWDG register

+  * @param  __INSTANCE__ WWDG Instance

+  * @param  __REG__ Register to be written

+  * @param  __VALUE__ Value to be written in the register

+  * @retval None

+  */

+#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))

+

+/**

+  * @brief  Read a value in WWDG register

+  * @param  __INSTANCE__ WWDG Instance

+  * @param  __REG__ Register to be read

+  * @retval Register value

+  */

+#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/* Exported functions --------------------------------------------------------*/

+/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions

+  * @{

+  */

+

+/** @defgroup WWDG_LL_EF_Configuration Configuration

+  * @{

+  */

+/**

+  * @brief  Enable Window Watchdog. The watchdog is always disabled after a reset.

+  * @note   It is enabled by setting the WDGA bit in the WWDG_CR register,

+  *         then it cannot be disabled again except by a reset.

+  *         This bit is set by software and only cleared by hardware after a reset.

+  *         When WDGA = 1, the watchdog can generate a reset.

+  * @rmtoll CR           WDGA          LL_WWDG_Enable

+  * @param  WWDGx WWDG Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx)

+{

+  SET_BIT(WWDGx->CR, WWDG_CR_WDGA);

+}

+

+/**

+  * @brief  Checks if Window Watchdog is enabled

+  * @rmtoll CR           WDGA          LL_WWDG_IsEnabled

+  * @param  WWDGx WWDG Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx)

+{

+  return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Set the Watchdog counter value to provided value (7-bits T[6:0])

+  * @note   When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset

+  *         This counter is decremented every (4096 x 2expWDGTB) PCLK cycles

+  *         A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared)

+  *         Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled)

+  * @rmtoll CR           T             LL_WWDG_SetCounter

+  * @param  WWDGx WWDG Instance

+  * @param  Counter 0..0x7F (7 bit counter value)

+  * @retval None

+  */

+__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter)

+{

+  MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter);

+}

+

+/**

+  * @brief  Return current Watchdog Counter Value (7 bits counter value)

+  * @rmtoll CR           T             LL_WWDG_GetCounter

+  * @param  WWDGx WWDG Instance

+  * @retval 7 bit Watchdog Counter value

+  */

+__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx)

+{

+  return (READ_BIT(WWDGx->CR, WWDG_CR_T));

+}

+

+/**

+  * @brief  Set the time base of the prescaler (WDGTB).

+  * @note   Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter

+  *         is decremented every (4096 x 2expWDGTB) PCLK cycles

+  * @rmtoll CFR          WDGTB         LL_WWDG_SetPrescaler

+  * @param  WWDGx WWDG Instance

+  * @param  Prescaler This parameter can be one of the following values:

+  *         @arg @ref LL_WWDG_PRESCALER_1

+  *         @arg @ref LL_WWDG_PRESCALER_2

+  *         @arg @ref LL_WWDG_PRESCALER_4

+  *         @arg @ref LL_WWDG_PRESCALER_8

+  *         @arg @ref LL_WWDG_PRESCALER_16

+  *         @arg @ref LL_WWDG_PRESCALER_32

+  *         @arg @ref LL_WWDG_PRESCALER_64

+  *         @arg @ref LL_WWDG_PRESCALER_128

+  * @retval None

+  */

+__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler)

+{

+  MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler);

+}

+

+/**

+  * @brief  Return current Watchdog Prescaler Value

+  * @rmtoll CFR          WDGTB         LL_WWDG_GetPrescaler

+  * @param  WWDGx WWDG Instance

+  * @retval Returned value can be one of the following values:

+  *         @arg @ref LL_WWDG_PRESCALER_1

+  *         @arg @ref LL_WWDG_PRESCALER_2

+  *         @arg @ref LL_WWDG_PRESCALER_4

+  *         @arg @ref LL_WWDG_PRESCALER_8

+  *         @arg @ref LL_WWDG_PRESCALER_16

+  *         @arg @ref LL_WWDG_PRESCALER_32

+  *         @arg @ref LL_WWDG_PRESCALER_64

+  *         @arg @ref LL_WWDG_PRESCALER_128

+  */

+__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx)

+{

+  return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB));

+}

+

+/**

+  * @brief  Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]).

+  * @note   This window value defines when write in the WWDG_CR register

+  *         to program Watchdog counter is allowed.

+  *         Watchdog counter value update must occur only when the counter value

+  *         is lower than the Watchdog window register value.

+  *         Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value

+  *         (in the control register) is refreshed before the downcounter has reached

+  *         the watchdog window register value.

+  *         Physically is possible to set the Window lower then 0x40 but it is not recommended.

+  *         To generate an immediate reset, it is possible to set the Counter lower than 0x40.

+  * @rmtoll CFR          W             LL_WWDG_SetWindow

+  * @param  WWDGx WWDG Instance

+  * @param  Window 0x00..0x7F (7 bit Window value)

+  * @retval None

+  */

+__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window)

+{

+  MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window);

+}

+

+/**

+  * @brief  Return current Watchdog Window Value (7 bits value)

+  * @rmtoll CFR          W             LL_WWDG_GetWindow

+  * @param  WWDGx WWDG Instance

+  * @retval 7 bit Watchdog Window value

+  */

+__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx)

+{

+  return (READ_BIT(WWDGx->CFR, WWDG_CFR_W));

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management

+  * @{

+  */

+/**

+  * @brief  Indicates if the WWDG Early Wakeup Interrupt Flag is set or not.

+  * @note   This bit is set by hardware when the counter has reached the value 0x40.

+  *         It must be cleared by software by writing 0.

+  *         A write of 1 has no effect. This bit is also set if the interrupt is not enabled.

+  * @rmtoll SR           EWIF          LL_WWDG_IsActiveFlag_EWKUP

+  * @param  WWDGx WWDG Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx)

+{

+  return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL);

+}

+

+/**

+  * @brief  Clear WWDG Early Wakeup Interrupt Flag (EWIF)

+  * @rmtoll SR           EWIF          LL_WWDG_ClearFlag_EWKUP

+  * @param  WWDGx WWDG Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx)

+{

+  WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF);

+}

+

+/**

+  * @}

+  */

+

+/** @defgroup WWDG_LL_EF_IT_Management IT_Management

+  * @{

+  */

+/**

+  * @brief  Enable the Early Wakeup Interrupt.

+  * @note   When set, an interrupt occurs whenever the counter reaches value 0x40.

+  *         This interrupt is only cleared by hardware after a reset

+  * @rmtoll CFR          EWI           LL_WWDG_EnableIT_EWKUP

+  * @param  WWDGx WWDG Instance

+  * @retval None

+  */

+__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx)

+{

+  SET_BIT(WWDGx->CFR, WWDG_CFR_EWI);

+}

+

+/**

+  * @brief  Check if Early Wakeup Interrupt is enabled

+  * @rmtoll CFR          EWI           LL_WWDG_IsEnabledIT_EWKUP

+  * @param  WWDGx WWDG Instance

+  * @retval State of bit (1 or 0).

+  */

+__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx)

+{

+  return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL);

+}

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+

+#endif /* WWDG1 || WWDG2 */

+

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* STM32H7xx_LL_WWDG_H */

+

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

diff --git a/bsps/arm/stm32h7/include/system_stm32h7xx.h b/bsps/arm/stm32h7/include/system_stm32h7xx.h
new file mode 100644
index 0000000000..dd75af67ff
--- /dev/null
+++ b/bsps/arm/stm32h7/include/system_stm32h7xx.h
@@ -0,0 +1,105 @@
+/**

+  ******************************************************************************

+  * @file    system_stm32h7xx.h

+  * @author  MCD Application Team

+  * @brief   CMSIS Cortex-Mx Device System Source File for STM32H7xx devices.

+  ******************************************************************************

+  * @attention

+  *

+  * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.

+  * All rights reserved.</center></h2>

+  *

+  * This software component is licensed by ST under BSD 3-Clause license,

+  * the "License"; You may not use this file except in compliance with the

+  * License. You may obtain a copy of the License at:

+  *                        opensource.org/licenses/BSD-3-Clause

+  *

+  ******************************************************************************

+  */

+

+/** @addtogroup CMSIS

+  * @{

+  */

+

+/** @addtogroup stm32h7xx_system

+  * @{

+  */

+

+/**

+  * @brief Define to prevent recursive inclusion

+  */

+#ifndef SYSTEM_STM32H7XX_H

+#define SYSTEM_STM32H7XX_H

+

+#ifdef __cplusplus

+ extern "C" {

+#endif

+

+/** @addtogroup STM32H7xx_System_Includes

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+

+/** @addtogroup STM32H7xx_System_Exported_types

+  * @{

+  */

+  /* This variable is updated in three ways:

+      1) by calling CMSIS function SystemCoreClockUpdate()

+      2) by calling HAL API function HAL_RCC_GetSysClockFreq()

+      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency

+         Note: If you use this function to configure the system clock; then there

+               is no need to call the 2 first functions listed above, since SystemCoreClock

+               variable is updated automatically.

+  */

+extern uint32_t SystemCoreClock;             /*!< System Domain1 Clock Frequency  */

+extern uint32_t SystemD2Clock;               /*!< System Domain2 Clock Frequency  */

+extern const  uint8_t D1CorePrescTable[16] ; /*!< D1CorePrescTable prescalers table values */

+

+/**

+  * @}

+  */

+

+/** @addtogroup STM32H7xx_System_Exported_Constants

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/** @addtogroup STM32H7xx_System_Exported_Macros

+  * @{

+  */

+

+/**

+  * @}

+  */

+

+/** @addtogroup STM32H7xx_System_Exported_Functions

+  * @{

+  */

+

+extern void SystemInit(void);

+extern void SystemCoreClockUpdate(void);

+/**

+  * @}

+  */

+

+#ifdef __cplusplus

+}

+#endif

+

+#endif /* SYSTEM_STM32H7XX_H */

+

+/**

+  * @}

+  */

+

+/**

+  * @}

+  */

+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/